From 5c7a30cdf6bb5c4b4cb85e2d029a161b805a9558 Mon Sep 17 00:00:00 2001
From: Liqing Qin <qinliqing@physi.uni-heidelberg.de>
Date: Fri, 11 Oct 2024 14:42:06 +0200
Subject: [PATCH] git code

---
 FPGA_firmware/.gitignore                      |     72 +
 FPGA_firmware/README.txt                      |      2 +
 FPGA_firmware/clkctrl.BAK.qsys                |     71 +
 FPGA_firmware/clkctrl.qsys                    |     71 +
 FPGA_firmware/clkctrl.sopcinfo                |    257 +
 FPGA_firmware/clkctrl/clkctrl.bsf             |     60 +
 FPGA_firmware/clkctrl/clkctrl.csv             |     18 +
 FPGA_firmware/clkctrl/clkctrl.spd             |     10 +
 FPGA_firmware/clkctrl/clkctrl.xml             |    131 +
 .../clkctrl/synthesis/clkctrl.debuginfo       |    339 +
 FPGA_firmware/clkctrl/synthesis/clkctrl.qip   |     39 +
 FPGA_firmware/clkctrl/synthesis/clkctrl.v     |     16 +
 .../submodules/clkctrl_altclkctrl_0.v         |    115 +
 FPGA_firmware/debouncer.v                     |     57 +
 FPGA_firmware/debouncer_testbench.v           |     90 +
 FPGA_firmware/debug.log                       |      0
 .../devkit_simple_socket_server.qp_info       |      2 +
 .../devkit_simple_socket_server/filelist.txt  |      2 +
 FPGA_firmware/enet_gtx_clk_ddio.xml           |     31 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf   |     82 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip   |     74 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip   |      7 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd   |     10 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio.v     |    124 +
 .../enet_gtx_clk_ddio/altera_gpio_lite.sv     |   1200 +
 .../enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f |      2 +
 FPGA_firmware/filelist.txt                    |   2887 +
 FPGA_firmware/hit20v3.qpf                     |     30 +
 FPGA_firmware/hit20v3.qsf                     |    668 +
 FPGA_firmware/hit20v3_assignment_defaults.qdf |    807 +
 FPGA_firmware/hit20v3_test.out.sdc            |   1145 +
 FPGA_firmware/m10_rgmii.out.sdc               |     87 +
 FPGA_firmware/m10_rgmii.v                     |    342 +
 FPGA_firmware/output_file_sum.map             |     24 +
 .../output_files/.qsys_edit/filters.xml       |      2 +
 .../output_files/.qsys_edit/preferences.xml   |     15 +
 FPGA_firmware/output_files/ChainFlash.cdf     |     15 +
 .../output_files/flash/ext_flash.pof          |    Bin 0 -> 67109105 bytes
 .../output_files/flash/flash_loader.sof       |    Bin 0 -> 3227565 bytes
 FPGA_firmware/output_files/hit20v3.cdf        |     15 +
 FPGA_firmware/output_files/hit20v3.pof        |    Bin 0 -> 1450250 bytes
 FPGA_firmware/output_files/hit20v3.sld        |     24 +
 FPGA_firmware/output_files/hit20v3.sof        |    Bin 0 -> 3434231 bytes
 FPGA_firmware/output_files/hit20v3_bkgsub.pof |    Bin 0 -> 1450250 bytes
 .../output_files/hit20v3_time_limited.sof     |    Bin 0 -> 3411934 bytes
 FPGA_firmware/output_files/stp2.stp           |    860 +
 FPGA_firmware/output_files/stp_clu.stp        |    402 +
 FPGA_firmware/q_sys.BAK.qsys                  |   2495 +
 FPGA_firmware/q_sys.qsys                      |   2812 +
 FPGA_firmware/q_sys.sopcinfo                  |  45271 ++++++
 FPGA_firmware/q_sys/cali_ram.bsf              |    200 +
 FPGA_firmware/q_sys/cali_ram.xml              |    343 +
 FPGA_firmware/q_sys/cali_ram_bb.v             |     40 +
 FPGA_firmware/q_sys/cali_ram_inst.v           |     21 +
 FPGA_firmware/q_sys/q_sys.bsf                 |    640 +
 FPGA_firmware/q_sys/q_sys.csv                 |   1000 +
 FPGA_firmware/q_sys/q_sys.spd                 |   3346 +
 FPGA_firmware/q_sys/q_sys.xml                 |  21598 +++
 FPGA_firmware/q_sys/q_sys_bb.v                |    132 +
 FPGA_firmware/q_sys/q_sys_inst.v              |     67 +
 FPGA_firmware/q_sys/sensor_algo.bsf           |     38 +
 FPGA_firmware/q_sys/sensor_algo.xml           |    121 +
 FPGA_firmware/q_sys/sensor_algo_bb.v          |      5 +
 FPGA_firmware/q_sys/sensor_algo_inst.v        |      3 +
 FPGA_firmware/q_sys/st_splitter16.bsf         |    213 +
 FPGA_firmware/q_sys/st_splitter16.xml         |    292 +
 FPGA_firmware/q_sys/st_splitter16_bb.v        |     44 +
 FPGA_firmware/q_sys/st_splitter16_inst.v      |     23 +
 FPGA_firmware/q_sys/synthesis/q_sys.debuginfo |  63314 +++++++++
 FPGA_firmware/q_sys/synthesis/q_sys.qip       |   8602 ++
 FPGA_firmware/q_sys/synthesis/q_sys.regmap    |    769 +
 FPGA_firmware/q_sys/synthesis/q_sys.v         |   1638 +
 .../synthesis/submodules/MM_to_ST_Adapter.v   |    365 +
 .../synthesis/submodules/ST_to_MM_Adapter.v   |    154 +
 .../synthesis/submodules/afi_mux_ddr3_ddrx.v  |    253 +
 .../submodules/algo_reconstruction.sdc        |    112 +
 .../submodules/algo_reconstruction.sv         |    311 +
 .../submodules/algo_reconstruction.v          |    329 +
 .../submodules/algo_reconstruction_bkg.v      |    349 +
 .../algo_reconstruction_interface.v           |    283 +
 .../q_sys/synthesis/submodules/algo_state.sv  |    202 +
 .../submodules/algo_top_cl_cali_rms.v         |    352 +
 .../submodules/alt_mem_ddrx_addr_cmd.v        |    563 +
 .../submodules/alt_mem_ddrx_addr_cmd_wrap.v   |    808 +
 .../submodules/alt_mem_ddrx_arbiter.v         |   1242 +
 .../alt_mem_ddrx_axi_st_converter.v           |   1662 +
 .../submodules/alt_mem_ddrx_buffer.v          |    155 +
 .../submodules/alt_mem_ddrx_buffer_manager.v  |    263 +
 .../submodules/alt_mem_ddrx_burst_gen.v       |   1582 +
 .../submodules/alt_mem_ddrx_burst_tracking.v  |    140 +
 .../submodules/alt_mem_ddrx_cmd_gen.v         |   2472 +
 .../submodules/alt_mem_ddrx_controller.v      |   2513 +
 .../alt_mem_ddrx_controller_st_top.v          |   1208 +
 .../synthesis/submodules/alt_mem_ddrx_csr.v   |   1433 +
 .../submodules/alt_mem_ddrx_dataid_manager.v  |   1003 +
 .../submodules/alt_mem_ddrx_ddr2_odt_gen.v    |    458 +
 .../submodules/alt_mem_ddrx_ddr3_odt_gen.v    |    473 +
 .../submodules/alt_mem_ddrx_define.iv         |     41 +
 .../submodules/alt_mem_ddrx_ecc_decoder.v     |    427 +
 .../alt_mem_ddrx_ecc_decoder_32_syn.v         |    496 +
 .../alt_mem_ddrx_ecc_decoder_64_syn.v         |    721 +
 .../submodules/alt_mem_ddrx_ecc_encoder.v     |    295 +
 .../alt_mem_ddrx_ecc_encoder_32_syn.v         |    288 +
 .../alt_mem_ddrx_ecc_encoder_64_syn.v         |    394 +
 ...alt_mem_ddrx_ecc_encoder_decoder_wrapper.v |   1156 +
 .../synthesis/submodules/alt_mem_ddrx_fifo.v  |    239 +
 .../submodules/alt_mem_ddrx_input_if.v        |    315 +
 .../synthesis/submodules/alt_mem_ddrx_list.v  |    242 +
 .../submodules/alt_mem_ddrx_lpddr2_addr_cmd.v |    400 +
 .../submodules/alt_mem_ddrx_mm_st_converter.v |    289 +
 .../submodules/alt_mem_ddrx_odt_gen.v         |    297 +
 .../submodules/alt_mem_ddrx_rank_timer.v      |   2995 +
 .../submodules/alt_mem_ddrx_rdata_path.v      |   1202 +
 .../submodules/alt_mem_ddrx_rdwr_data_tmg.v   |   4108 +
 .../submodules/alt_mem_ddrx_sideband.v        |   1745 +
 .../synthesis/submodules/alt_mem_ddrx_tbp.v   |   3539 +
 .../submodules/alt_mem_ddrx_timing_param.v    |    732 +
 .../submodules/alt_mem_ddrx_wdata_path.v      |   1128 +
 ...alt_mem_if_nextgen_ddr3_controller_core.sv |    535 +
 .../submodules/altera_avalon_sc_fifo.v        |    915 +
 .../altera_avalon_st_clock_crosser.v          |    141 +
 ...tera_avalon_st_handshake_clock_crosser.sdc |     71 +
 ...altera_avalon_st_handshake_clock_crosser.v |    218 +
 .../altera_avalon_st_pipeline_base.v          |    139 +
 .../altera_avalon_st_pipeline_stage.sv        |    166 +
 .../submodules/altera_avalon_st_splitter.sv   |    422 +
 .../altera_default_burst_converter.sv         |    189 +
 .../synthesis/submodules/altera_dual_boot.v   |     61 +
 .../submodules/altera_epcq_controller.sv      |    611 +
 .../submodules/altera_epcq_controller_arb.sv  |    230 +
 .../submodules/altera_eth_tse_mac.sdc         |    303 +
 .../synthesis/submodules/altera_eth_tse_mac.v |    Bin 0 -> 76504 bytes
 .../altera_eth_tse_ptp_std_synchronizer.v     |     40 +
 .../altera_eth_tse_std_synchronizer.v         |     65 +
 .../altera_eth_tse_std_synchronizer_bundle.v  |     60 +
 .../synthesis/submodules/altera_gpio_lite.sv  |   1200 +
 .../submodules/altera_incr_burst_converter.sv |    310 +
 .../submodules/altera_irq_clock_crosser.sv    |     49 +
 .../submodules/altera_mem_if_sequencer_rst.sv |    117 +
 .../altera_merlin_address_alignment.sv        |    263 +
 .../submodules/altera_merlin_arbitrator.sv    |    272 +
 .../submodules/altera_merlin_burst_adapter.sv |    261 +
 .../altera_merlin_burst_adapter_13_1.sv       |   1174 +
 .../altera_merlin_burst_adapter_new.sv        |   1890 +
 .../altera_merlin_burst_adapter_uncmpr.sv     |     94 +
 .../altera_merlin_burst_uncompressor.sv       |    296 +
 .../submodules/altera_merlin_master_agent.sv  |    303 +
 .../altera_merlin_master_translator.sv        |    556 +
 .../altera_merlin_reorder_memory.sv           |    297 +
 .../submodules/altera_merlin_slave_agent.sv   |    622 +
 .../altera_merlin_slave_translator.sv         |    482 +
 .../altera_merlin_traffic_limiter.sv          |    787 +
 .../submodules/altera_merlin_width_adapter.sv |   1206 +
 .../submodules/altera_msgdma_prefetcher.v     |    249 +
 .../submodules/altera_msgdma_prefetcher_csr.v |    226 +
 .../altera_msgdma_prefetcher_fifo.v           |    142 +
 .../altera_msgdma_prefetcher_interrrupt.v     |     55 +
 .../altera_msgdma_prefetcher_read.v           |    515 +
 .../altera_msgdma_prefetcher_write_back.v     |    416 +
 .../altera_nios2_gen2_rtl_module.ocp          |    Bin 0 -> 880 bytes
 .../altera_nios2_gen2_rtl_module.sv           |    Bin 0 -> 12424 bytes
 .../submodules/altera_onchip_flash.sdc        |     92 +
 .../submodules/altera_onchip_flash.v          |    331 +
 .../altera_onchip_flash_avmm_csr_controller.v |    182 +
 ...altera_onchip_flash_avmm_data_controller.v |   1263 +
 .../submodules/altera_onchip_flash_util.v     |    270 +
 .../submodules/altera_reset_controller.sdc    |     30 +
 .../submodules/altera_reset_controller.v      |    319 +
 .../submodules/altera_reset_synchronizer.v    |     87 +
 .../altera_std_synchronizer_nocut.v           |    195 +
 .../submodules/altera_tse_a_fifo_13.v         |    Bin 0 -> 8480 bytes
 .../submodules/altera_tse_a_fifo_24.v         |    Bin 0 -> 9152 bytes
 .../submodules/altera_tse_a_fifo_34.v         |    Bin 0 -> 7312 bytes
 .../submodules/altera_tse_a_fifo_opt_1246.v   |    Bin 0 -> 14328 bytes
 .../submodules/altera_tse_a_fifo_opt_14_44.v  |    Bin 0 -> 12328 bytes
 .../submodules/altera_tse_a_fifo_opt_36_10.v  |    Bin 0 -> 15344 bytes
 .../submodules/altera_tse_altshifttaps.v      |    Bin 0 -> 2480 bytes
 .../altera_tse_altsyncram_dpm_fifo.v          |    Bin 0 -> 3728 bytes
 .../synthesis/submodules/altera_tse_bin_cnt.v |    Bin 0 -> 3256 bytes
 .../submodules/altera_tse_clk_cntl.v          |    Bin 0 -> 4656 bytes
 .../submodules/altera_tse_clock_crosser.v     |    Bin 0 -> 4472 bytes
 .../submodules/altera_tse_crc328checker.v     |    Bin 0 -> 4616 bytes
 .../submodules/altera_tse_crc328generator.v   |    Bin 0 -> 3512 bytes
 .../submodules/altera_tse_crc32ctl8.v         |    Bin 0 -> 2656 bytes
 .../submodules/altera_tse_crc32galois8.v      |    Bin 0 -> 7784 bytes
 .../submodules/altera_tse_dpram_16x32.v       |    Bin 0 -> 10576 bytes
 .../submodules/altera_tse_dpram_8x32.v        |    Bin 0 -> 10560 bytes
 .../submodules/altera_tse_dpram_ecc_16x32.v   |    Bin 0 -> 10936 bytes
 .../submodules/altera_tse_ecc_dec_x10.v       |    Bin 0 -> 10824 bytes
 .../submodules/altera_tse_ecc_dec_x14.v       |    Bin 0 -> 12240 bytes
 .../submodules/altera_tse_ecc_dec_x2.v        |    Bin 0 -> 8264 bytes
 .../submodules/altera_tse_ecc_dec_x23.v       |    Bin 0 -> 15040 bytes
 .../submodules/altera_tse_ecc_dec_x30.v       |    Bin 0 -> 17488 bytes
 .../submodules/altera_tse_ecc_dec_x36.v       |    Bin 0 -> 19472 bytes
 .../submodules/altera_tse_ecc_dec_x40.v       |    Bin 0 -> 20848 bytes
 .../submodules/altera_tse_ecc_enc_x10.v       |    Bin 0 -> 6136 bytes
 .../altera_tse_ecc_enc_x10_wrapper.v          |    Bin 0 -> 1360 bytes
 .../submodules/altera_tse_ecc_enc_x14.v       |    Bin 0 -> 6672 bytes
 .../altera_tse_ecc_enc_x14_wrapper.v          |    Bin 0 -> 1360 bytes
 .../submodules/altera_tse_ecc_enc_x2.v        |    Bin 0 -> 5216 bytes
 .../submodules/altera_tse_ecc_enc_x23.v       |    Bin 0 -> 7672 bytes
 .../altera_tse_ecc_enc_x23_wrapper.v          |    Bin 0 -> 1360 bytes
 .../altera_tse_ecc_enc_x2_wrapper.v           |    Bin 0 -> 1336 bytes
 .../submodules/altera_tse_ecc_enc_x30.v       |    Bin 0 -> 8640 bytes
 .../altera_tse_ecc_enc_x30_wrapper.v          |    Bin 0 -> 1360 bytes
 .../submodules/altera_tse_ecc_enc_x36.v       |    Bin 0 -> 9424 bytes
 .../altera_tse_ecc_enc_x36_wrapper.v          |    Bin 0 -> 1360 bytes
 .../submodules/altera_tse_ecc_enc_x40.v       |    Bin 0 -> 10008 bytes
 .../altera_tse_ecc_enc_x40_wrapper.v          |    Bin 0 -> 1360 bytes
 .../altera_tse_ecc_status_crosser.v           |    Bin 0 -> 2704 bytes
 .../submodules/altera_tse_false_path_marker.v |     66 +
 .../submodules/altera_tse_fifoless_mac_rx.v   |    Bin 0 -> 129336 bytes
 .../submodules/altera_tse_fifoless_mac_tx.v   |    Bin 0 -> 108208 bytes
 .../altera_tse_fifoless_retransmit_cntl.v     |    Bin 0 -> 28344 bytes
 .../synthesis/submodules/altera_tse_gmii_io.v |    Bin 0 -> 6448 bytes
 .../submodules/altera_tse_gray_cnt.v          |    Bin 0 -> 5016 bytes
 .../synthesis/submodules/altera_tse_hashing.v |    Bin 0 -> 6512 bytes
 .../submodules/altera_tse_host_control.v      |    Bin 0 -> 10152 bytes
 .../altera_tse_host_control_small.v           |    Bin 0 -> 10736 bytes
 .../submodules/altera_tse_lb_read_cntl.v      |    Bin 0 -> 3624 bytes
 .../submodules/altera_tse_lb_wrt_cntl.v       |    Bin 0 -> 4080 bytes
 .../synthesis/submodules/altera_tse_lfsr_10.v |    Bin 0 -> 4040 bytes
 .../submodules/altera_tse_loopback_ff.v       |    Bin 0 -> 8768 bytes
 .../submodules/altera_tse_mac_control.v       |    Bin 0 -> 47320 bytes
 .../synthesis/submodules/altera_tse_mac_rx.v  |    Bin 0 -> 116184 bytes
 .../synthesis/submodules/altera_tse_mac_tx.v  |    Bin 0 -> 92432 bytes
 .../submodules/altera_tse_magic_detection.v   |    Bin 0 -> 19952 bytes
 .../synthesis/submodules/altera_tse_mdio.v    |    Bin 0 -> 17760 bytes
 .../submodules/altera_tse_mdio_clk_gen.v      |    Bin 0 -> 3384 bytes
 .../submodules/altera_tse_mdio_cntl.v         |    Bin 0 -> 9232 bytes
 .../submodules/altera_tse_mii_rx_if.v         |    Bin 0 -> 9472 bytes
 .../submodules/altera_tse_mii_tx_if.v         |    Bin 0 -> 5072 bytes
 .../submodules/altera_tse_nf_rgmii_module.v   |    Bin 0 -> 7368 bytes
 .../submodules/altera_tse_ph_calculator.sv    |    Bin 0 -> 5760 bytes
 .../submodules/altera_tse_pipeline_base.v     |    Bin 0 -> 4280 bytes
 .../submodules/altera_tse_pipeline_stage.sv   |    Bin 0 -> 5256 bytes
 .../submodules/altera_tse_register_map.v      |    Bin 0 -> 98272 bytes
 .../altera_tse_register_map_small.v           |    Bin 0 -> 88576 bytes
 .../altera_tse_reset_synchronizer.v           |    100 +
 .../submodules/altera_tse_retransmit_cntl.v   |    Bin 0 -> 26112 bytes
 .../submodules/altera_tse_rgmii_in1.v         |    119 +
 .../submodules/altera_tse_rgmii_in4.v         |    115 +
 .../submodules/altera_tse_rgmii_module.v      |    302 +
 .../submodules/altera_tse_rgmii_out1.v        |    123 +
 .../submodules/altera_tse_rgmii_out4.v        |    118 +
 .../submodules/altera_tse_rx_counter_cntl.v   |    Bin 0 -> 31016 bytes
 .../synthesis/submodules/altera_tse_rx_ff.v   |    Bin 0 -> 22776 bytes
 .../submodules/altera_tse_rx_ff_cntrl.v       |    Bin 0 -> 20784 bytes
 .../submodules/altera_tse_rx_ff_cntrl_32.v    |    Bin 0 -> 22368 bytes
 .../altera_tse_rx_ff_cntrl_32_shift16.v       |    Bin 0 -> 30800 bytes
 .../submodules/altera_tse_rx_ff_length.v      |    Bin 0 -> 3928 bytes
 .../submodules/altera_tse_rx_min_ff.v         |    Bin 0 -> 41992 bytes
 .../submodules/altera_tse_rx_stat_extract.v   |    Bin 0 -> 17368 bytes
 .../submodules/altera_tse_sdpm_altsyncram.v   |    Bin 0 -> 3824 bytes
 .../submodules/altera_tse_sdpm_gen.v          |    Bin 0 -> 2520 bytes
 .../altera_tse_shared_mac_control.v           |    Bin 0 -> 33976 bytes
 .../altera_tse_shared_register_map.v          |    Bin 0 -> 100400 bytes
 .../submodules/altera_tse_timing_adapter32.v  |    Bin 0 -> 5512 bytes
 .../submodules/altera_tse_timing_adapter8.v   |    Bin 0 -> 5320 bytes
 .../altera_tse_timing_adapter_fifo32.v        |    Bin 0 -> 12496 bytes
 .../altera_tse_timing_adapter_fifo8.v         |    Bin 0 -> 12160 bytes
 .../submodules/altera_tse_top_1geth.v         |    Bin 0 -> 31984 bytes
 .../altera_tse_top_fifoless_1geth.v           |    Bin 0 -> 33736 bytes
 .../submodules/altera_tse_top_gen_host.v      |    Bin 0 -> 66696 bytes
 .../submodules/altera_tse_top_mdio.v          |    Bin 0 -> 7496 bytes
 .../submodules/altera_tse_top_w_fifo.v        |    Bin 0 -> 51568 bytes
 .../altera_tse_top_w_fifo_10_100_1000.ocp     |    Bin 0 -> 1616 bytes
 .../altera_tse_top_w_fifo_10_100_1000.v       |    Bin 0 -> 49032 bytes
 .../submodules/altera_tse_top_wo_fifo.v       |    Bin 0 -> 52976 bytes
 .../altera_tse_top_wo_fifo_10_100_1000.ocp    |    Bin 0 -> 1744 bytes
 .../altera_tse_top_wo_fifo_10_100_1000.v      |    Bin 0 -> 54768 bytes
 .../submodules/altera_tse_tx_counter_cntl.v   |    Bin 0 -> 24312 bytes
 .../synthesis/submodules/altera_tse_tx_ff.v   |    Bin 0 -> 44064 bytes
 .../submodules/altera_tse_tx_ff_cntrl.v       |    Bin 0 -> 10472 bytes
 .../submodules/altera_tse_tx_ff_cntrl_32.v    |    Bin 0 -> 12256 bytes
 .../altera_tse_tx_ff_cntrl_32_shift16.v       |    Bin 0 -> 16680 bytes
 .../submodules/altera_tse_tx_ff_length.v      |    Bin 0 -> 3128 bytes
 .../submodules/altera_tse_tx_ff_read_cntl.v   |    Bin 0 -> 9952 bytes
 .../submodules/altera_tse_tx_min_ff.v         |    Bin 0 -> 40448 bytes
 .../submodules/altera_tse_tx_stat_extract.v   |    Bin 0 -> 15968 bytes
 .../submodules/altera_wrap_burst_converter.sv |    335 +
 .../q_sys/synthesis/submodules/bkg.sv         |    106 +
 .../submodules/bkg_subtraction_pipe.v         |    312 +
 .../submodules/byte_enable_generator.v        |    838 +
 .../synthesis/submodules/cali_ram_cali_ram.v  |    126 +
 .../q_sys/synthesis/submodules/calibration.v  |    233 +
 .../synthesis/submodules/cluster_locate.sv    |    186 +
 .../q_sys/synthesis/submodules/csr_block.v    |    414 +
 .../synthesis/submodules/data_caled_ram.qip   |      6 +
 .../synthesis/submodules/data_caled_ram.v     |    243 +
 .../synthesis/submodules/data_interface.sv    |    320 +
 .../synthesis/submodules/descriptor_buffers.v |    421 +
 .../q_sys/synthesis/submodules/dispatcher.v   |    430 +
 .../q_sys/synthesis/submodules/div.qip        |      6 +
 .../q_sys/synthesis/submodules/div.v          |    116 +
 .../submodules/fifo_with_byteenables.v        |    185 +
 .../synthesis/submodules/frame_counter.v      |     36 +
 .../synthesis/submodules/max10emif_dcfifo.sv  |     69 +
 .../synthesis/submodules/q_sys_altpll_shift.v |    335 +
 .../submodules/q_sys_avalon_st_adapter.v      |    214 +
 .../submodules/q_sys_avalon_st_adapter_001.v  |    216 +
 ...s_avalon_st_adapter_001_error_adapter_0.sv |    115 +
 ..._avalon_st_adapter_001_timing_adapter_0.sv |    132 +
 ...on_st_adapter_001_timing_adapter_0_fifo.sv |    163 +
 .../submodules/q_sys_avalon_st_adapter_002.v  |    214 +
 ...s_avalon_st_adapter_002_error_adapter_0.sv |    115 +
 ...sys_avalon_st_adapter_channel_adapter_0.sv |    106 +
 ...q_sys_avalon_st_adapter_error_adapter_0.sv |    116 +
 ..._sys_avalon_st_adapter_timing_adapter_0.sv |    132 +
 ...avalon_st_adapter_timing_adapter_0_fifo.sv |    163 +
 .../synthesis/submodules/q_sys_button_pio.v   |     59 +
 .../synthesis/submodules/q_sys_cali_ram.v     |     83 +
 .../submodules/q_sys_calibration_ram.v        |    126 +
 .../submodules/q_sys_channel_adapter_0.sv     |    101 +
 .../q_sys/synthesis/submodules/q_sys_cpu.v    |     71 +
 .../synthesis/submodules/q_sys_cpu_cpu.ocp    |    Bin 0 -> 848 bytes
 .../synthesis/submodules/q_sys_cpu_cpu.sdc    |     53 +
 .../synthesis/submodules/q_sys_cpu_cpu.v      |  14962 ++
 .../submodules/q_sys_cpu_cpu_bht_ram.mif      |    267 +
 .../submodules/q_sys_cpu_cpu_dc_tag_ram.mif   |     75 +
 .../q_sys_cpu_cpu_debug_slave_sysclk.v        |    162 +
 .../q_sys_cpu_cpu_debug_slave_tck.v           |    239 +
 .../q_sys_cpu_cpu_debug_slave_wrapper.v       |    222 +
 .../submodules/q_sys_cpu_cpu_ic_tag_ram.mif   |     75 +
 .../submodules/q_sys_cpu_cpu_mult_cell.v      |    174 +
 .../q_sys_cpu_cpu_ociram_default_contents.mif |    267 +
 .../submodules/q_sys_cpu_cpu_rf_ram_a.mif     |     42 +
 .../submodules/q_sys_cpu_cpu_rf_ram_b.mif     |     42 +
 .../submodules/q_sys_cpu_cpu_test_bench.v     |   1063 +
 .../synthesis/submodules/q_sys_ddr3_ram.v     |    412 +
 .../synthesis/submodules/q_sys_ddr3_ram_c0.v  |    309 +
 .../submodules/q_sys_ddr3_ram_p0.ppf          |    348 +
 .../submodules/q_sys_ddr3_ram_p0.sdc          |    480 +
 .../synthesis/submodules/q_sys_ddr3_ram_p0.sv |    448 +
 .../q_sys_ddr3_ram_p0_addr_cmd_datapath.v     |    215 +
 .../q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v     |    513 +
 .../q_sys_ddr3_ram_p0_clock_pair_generator.v  |    102 +
 .../q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv       |    414 +
 .../submodules/q_sys_ddr3_ram_p0_flop_mem.v   |    109 +
 .../q_sys_ddr3_ram_p0_fr_cycle_shifter.v      |     88 +
 .../submodules/q_sys_ddr3_ram_p0_iss_probe.v  |     60 +
 .../q_sys_ddr3_ram_p0_memphy_m10.sv           |    580 +
 .../q_sys_ddr3_ram_p0_read_datapath_m10.sv    |    187 +
 .../q_sys_ddr3_ram_p0_read_valid_selector.v   |     89 +
 .../submodules/q_sys_ddr3_ram_p0_reset_m10.v  |     82 +
 .../submodules/q_sys_ddr3_ram_p0_reset_sync.v |     62 +
 .../q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv  |     94 +
 .../q_sys_ddr3_ram_p0_write_datapath_m10.v    |    195 +
 .../submodules/q_sys_ddr3_ram_pll0.sv         |    223 +
 .../synthesis/submodules/q_sys_ddr3_ram_s0.v  |    289 +
 .../submodules/q_sys_ddr3_ram_s0_AC_ROM.hex   |     41 +
 .../submodules/q_sys_ddr3_ram_s0_inst_ROM.hex |    129 +
 .../q_sys_ddr3_ram_s0_mm_interconnect_0.v     |   1258 +
 ...m_s0_mm_interconnect_0_avalon_st_adapter.v |    202 +
 ...ect_0_avalon_st_adapter_error_adapter_0.sv |    107 +
 ...ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv |    130 +
 ...s_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv |     96 +
 ...ys_ddr3_ram_s0_mm_interconnect_0_router.sv |    234 +
 ...dr3_ram_s0_mm_interconnect_0_router_001.sv |    215 +
 ...ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv |    100 +
 ...s_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv |    365 +
 .../sequencer_defines.h                       |    164 +
 .../sequencer_m10.c                           |    720 +
 .../sequencer_m10.h                           |    345 +
 .../synthesis/submodules/q_sys_debug_uart.v   |    921 +
 .../submodules/q_sys_descriptor_memory.v      |     86 +
 .../synthesis/submodules/q_sys_enet_pll.v     |    343 +
 .../synthesis/submodules/q_sys_eth_tse.v      |    406 +
 .../synthesis/submodules/q_sys_ext_flash.sv   |    212 +
 ...ys_ext_flash_asmi_parallel_instance_name.v |     66 +
 ...nstance_name_asmi_parallel_instance_name.v |   2872 +
 ..._ext_flash_epcq_controller_instance_name.v |    207 +
 ...s_ext_flash_soft_asmiblock_instance_name.v |     58 +
 .../synthesis/submodules/q_sys_frame_timer.v  |    203 +
 .../q_sys/synthesis/submodules/q_sys_glad.v   |     87 +
 .../synthesis/submodules/q_sys_irq_mapper.sv  |     66 +
 .../synthesis/submodules/q_sys_jtag_uart.v    |    588 +
 .../synthesis/submodules/q_sys_led_pio.v      |     70 +
 .../synthesis/submodules/q_sys_log_ram.hex    |  32764 +++++
 .../synthesis/submodules/q_sys_log_ram.v      |     87 +
 .../submodules/q_sys_mem_if_ddr3_emif_0.v     |    412 +
 .../submodules/q_sys_mem_if_ddr3_emif_0_c0.v  |    309 +
 .../q_sys_mem_if_ddr3_emif_0_p0.ppf           |    348 +
 .../q_sys_mem_if_ddr3_emif_0_p0.sdc           |    480 +
 .../submodules/q_sys_mem_if_ddr3_emif_0_p0.sv |    448 +
 ..._mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v |    215 +
 ..._mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v |    513 +
 ...m_if_ddr3_emif_0_p0_clock_pair_generator.v |    101 +
 ...ys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv |    414 +
 .../q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v    |    109 +
 ...s_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v |     88 +
 .../q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v   |     60 +
 .../q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv |    580 +
 ...mem_if_ddr3_emif_0_p0_read_datapath_m10.sv |    187 +
 ...em_if_ddr3_emif_0_p0_read_valid_selector.v |     89 +
 .../q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v   |     82 +
 .../q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v  |     62 +
 ...m_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv |     94 +
 ...mem_if_ddr3_emif_0_p0_write_datapath_m10.v |    195 +
 .../q_sys_mem_if_ddr3_emif_0_pll0.sv          |    223 +
 .../submodules/q_sys_mem_if_ddr3_emif_0_s0.v  |    289 +
 .../q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex    |     41 +
 .../q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex  |    129 +
 ..._mem_if_ddr3_emif_0_s0_mm_interconnect_0.v |   1258 +
 ...0_s0_mm_interconnect_0_avalon_st_adapter.v |    202 +
 ...ect_0_avalon_st_adapter_error_adapter_0.sv |    107 +
 ...3_emif_0_s0_mm_interconnect_0_cmd_demux.sv |    130 +
 ...dr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv |     96 +
 ...ddr3_emif_0_s0_mm_interconnect_0_router.sv |    234 +
 ..._emif_0_s0_mm_interconnect_0_router_001.sv |    215 +
 ...3_emif_0_s0_mm_interconnect_0_rsp_demux.sv |    100 +
 ...dr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv |    365 +
 .../sequencer_defines.h                       |    164 +
 .../sequencer_m10.c                           |    720 +
 .../sequencer_m10.h                           |    345 +
 .../submodules/q_sys_mm_interconnect_0.v      |    161 +
 ..._sys_mm_interconnect_0_avalon_st_adapter.v |    202 +
 ..._mm_interconnect_0_avalon_st_adapter_010.v |    202 +
 ...0_avalon_st_adapter_010_error_adapter_0.sv |    107 +
 ..._mm_interconnect_0_avalon_st_adapter_012.v |    202 +
 ...0_avalon_st_adapter_012_error_adapter_0.sv |    107 +
 ..._mm_interconnect_0_avalon_st_adapter_013.v |    202 +
 ...0_avalon_st_adapter_013_error_adapter_0.sv |    107 +
 ..._mm_interconnect_0_avalon_st_adapter_020.v |    202 +
 ...0_avalon_st_adapter_020_error_adapter_0.sv |    107 +
 ...ect_0_avalon_st_adapter_error_adapter_0.sv |    107 +
 .../q_sys_mm_interconnect_0_cmd_demux.sv      |    415 +
 .../q_sys_mm_interconnect_0_cmd_demux_001.sv  |    145 +
 .../q_sys_mm_interconnect_0_cmd_demux_002.sv  |    100 +
 .../q_sys_mm_interconnect_0_cmd_demux_003.sv  |    115 +
 .../q_sys_mm_interconnect_0_cmd_demux_004.sv  |    100 +
 .../q_sys_mm_interconnect_0_cmd_demux_005.sv  |    145 +
 .../q_sys_mm_interconnect_0_cmd_demux_006.sv  |    115 +
 .../q_sys_mm_interconnect_0_cmd_demux_007.sv  |    115 +
 .../q_sys_mm_interconnect_0_cmd_mux.sv        |    408 +
 .../q_sys_mm_interconnect_0_cmd_mux_001.sv    |     96 +
 .../q_sys_mm_interconnect_0_cmd_mux_002.sv    |    366 +
 .../q_sys_mm_interconnect_0_cmd_mux_003.sv    |    366 +
 .../q_sys_mm_interconnect_0_cmd_mux_004.sv    |     96 +
 .../q_sys_mm_interconnect_0_cmd_mux_010.sv    |    429 +
 .../q_sys_mm_interconnect_0_cmd_mux_012.sv    |    429 +
 .../q_sys_mm_interconnect_0_cmd_mux_013.sv    |    429 +
 .../q_sys_mm_interconnect_0_cmd_mux_014.sv    |    429 +
 .../q_sys_mm_interconnect_0_cmd_mux_015.sv    |    429 +
 .../q_sys_mm_interconnect_0_cmd_mux_016.sv    |    450 +
 .../q_sys_mm_interconnect_0_router.sv         |    372 +
 .../q_sys_mm_interconnect_0_router_001.sv     |    241 +
 .../q_sys_mm_interconnect_0_router_002.sv     |    216 +
 .../q_sys_mm_interconnect_0_router_003.sv     |    216 +
 .../q_sys_mm_interconnect_0_router_004.sv     |    216 +
 .../q_sys_mm_interconnect_0_router_005.sv     |    241 +
 .../q_sys_mm_interconnect_0_router_006.sv     |    216 +
 .../q_sys_mm_interconnect_0_router_008.sv     |    234 +
 .../q_sys_mm_interconnect_0_router_009.sv     |    215 +
 .../q_sys_mm_interconnect_0_router_010.sv     |    224 +
 .../q_sys_mm_interconnect_0_router_011.sv     |    224 +
 .../q_sys_mm_interconnect_0_router_012.sv     |    215 +
 .../q_sys_mm_interconnect_0_router_013.sv     |    215 +
 .../q_sys_mm_interconnect_0_router_014.sv     |    215 +
 .../q_sys_mm_interconnect_0_router_018.sv     |    238 +
 .../q_sys_mm_interconnect_0_router_020.sv     |    238 +
 .../q_sys_mm_interconnect_0_router_021.sv     |    215 +
 .../q_sys_mm_interconnect_0_router_022.sv     |    238 +
 .../q_sys_mm_interconnect_0_router_023.sv     |    238 +
 .../q_sys_mm_interconnect_0_router_024.sv     |    242 +
 .../q_sys_mm_interconnect_0_router_025.sv     |    242 +
 .../q_sys_mm_interconnect_0_router_028.sv     |    215 +
 .../q_sys_mm_interconnect_0_rsp_demux.sv      |    145 +
 .../q_sys_mm_interconnect_0_rsp_demux_001.sv  |    100 +
 .../q_sys_mm_interconnect_0_rsp_demux_002.sv  |    115 +
 .../q_sys_mm_interconnect_0_rsp_demux_003.sv  |    115 +
 .../q_sys_mm_interconnect_0_rsp_demux_010.sv  |    115 +
 .../q_sys_mm_interconnect_0_rsp_demux_011.sv  |    115 +
 .../q_sys_mm_interconnect_0_rsp_demux_012.sv  |    160 +
 .../q_sys_mm_interconnect_0_rsp_demux_013.sv  |    160 +
 .../q_sys_mm_interconnect_0_rsp_demux_014.sv  |    160 +
 .../q_sys_mm_interconnect_0_rsp_demux_015.sv  |    160 +
 .../q_sys_mm_interconnect_0_rsp_demux_016.sv  |    175 +
 .../q_sys_mm_interconnect_0_rsp_demux_021.sv  |    145 +
 .../q_sys_mm_interconnect_0_rsp_mux.sv        |    745 +
 .../q_sys_mm_interconnect_0_rsp_mux_001.sv    |    385 +
 .../q_sys_mm_interconnect_0_rsp_mux_002.sv    |     96 +
 .../q_sys_mm_interconnect_0_rsp_mux_003.sv    |     96 +
 .../q_sys_mm_interconnect_0_rsp_mux_004.sv    |     96 +
 .../q_sys_mm_interconnect_0_rsp_mux_005.sv    |    385 +
 .../q_sys_mm_interconnect_0_rsp_mux_006.sv    |    345 +
 .../submodules/q_sys_mm_interconnect_1.v      |  10366 ++
 ..._sys_mm_interconnect_1_avalon_st_adapter.v |    202 +
 ..._mm_interconnect_1_avalon_st_adapter_020.v |    202 +
 ...1_avalon_st_adapter_020_error_adapter_0.sv |    107 +
 ..._mm_interconnect_1_avalon_st_adapter_021.v |    202 +
 ...1_avalon_st_adapter_021_error_adapter_0.sv |    107 +
 ...ect_1_avalon_st_adapter_error_adapter_0.sv |    107 +
 .../q_sys_mm_interconnect_1_cmd_demux.sv      |    400 +
 .../q_sys_mm_interconnect_1_cmd_demux_001.sv  |    145 +
 .../q_sys_mm_interconnect_1_cmd_demux_002.sv  |    100 +
 .../q_sys_mm_interconnect_1_cmd_mux.sv        |    408 +
 .../q_sys_mm_interconnect_1_cmd_mux_001.sv    |     96 +
 .../q_sys_mm_interconnect_1_cmd_mux_002.sv    |    366 +
 .../q_sys_mm_interconnect_1_cmd_mux_014.sv    |    429 +
 .../q_sys_mm_interconnect_1_router.sv         |    365 +
 .../q_sys_mm_interconnect_1_router_001.sv     |    241 +
 .../q_sys_mm_interconnect_1_router_002.sv     |    216 +
 .../q_sys_mm_interconnect_1_router_004.sv     |    216 +
 .../q_sys_mm_interconnect_1_router_008.sv     |    234 +
 .../q_sys_mm_interconnect_1_router_009.sv     |    215 +
 .../q_sys_mm_interconnect_1_router_010.sv     |    224 +
 .../q_sys_mm_interconnect_1_router_022.sv     |    238 +
 .../q_sys_mm_interconnect_1_router_028.sv     |    215 +
 .../q_sys_mm_interconnect_1_router_029.sv     |    215 +
 .../q_sys_mm_interconnect_1_rsp_demux.sv      |    145 +
 .../q_sys_mm_interconnect_1_rsp_demux_001.sv  |    100 +
 .../q_sys_mm_interconnect_1_rsp_demux_002.sv  |    115 +
 .../q_sys_mm_interconnect_1_rsp_demux_010.sv  |    115 +
 .../q_sys_mm_interconnect_1_rsp_demux_014.sv  |    160 +
 .../q_sys_mm_interconnect_1_rsp_mux.sv        |    725 +
 .../q_sys_mm_interconnect_1_rsp_mux_001.sv    |    385 +
 .../q_sys_mm_interconnect_1_rsp_mux_002.sv    |     96 +
 .../submodules/q_sys_msgdma_debug_tx.v        |    144 +
 .../synthesis/submodules/q_sys_msgdma_rx.v    |    200 +
 .../synthesis/submodules/q_sys_msgdma_tx.v    |    204 +
 .../synthesis/submodules/q_sys_onchip_ram.v   |     86 +
 .../synthesis/submodules/q_sys_output_pio.v   |     70 +
 .../synthesis/submodules/q_sys_sgdma_rx.v     |   2275 +
 .../synthesis/submodules/q_sys_sgdma_tx.v     |   2339 +
 .../submodules/q_sys_sys_clk_timer.v          |    211 +
 .../q_sys/synthesis/submodules/q_sys_sysid.v  |     56 +
 .../synthesis/submodules/q_sys_tse_0_dma_rx.v |    200 +
 .../synthesis/submodules/q_sys_tse_0_dma_tx.v |    204 +
 .../synthesis/submodules/q_sys_tse_0_tse.v    |    406 +
 .../submodules/q_sys_tx_multiplexer.sv        |    273 +
 .../q_sys/synthesis/submodules/ram4bkg.qip    |      6 +
 .../q_sys/synthesis/submodules/ram4bkg.v      |    214 +
 .../q_sys/synthesis/submodules/ram4sig.qip    |      5 +
 .../q_sys/synthesis/submodules/ram4sig.v      |    216 +
 .../synthesis/submodules/read_burst_control.v |    107 +
 .../q_sys/synthesis/submodules/read_master.v  |    795 +
 .../submodules/read_signal_breakout.v         |    137 +
 .../synthesis/submodules/response_block.v     |    225 +
 .../q_sys/synthesis/submodules/rms.sv         |    396 +
 .../q_sys/synthesis/submodules/rom_bkg.v      |    236 +
 .../synthesis/submodules/rtl/alt_dual_boot.v  |    Bin 0 -> 14888 bytes
 .../submodules/rtl/alt_dual_boot_avmm.v       |    Bin 0 -> 5520 bytes
 .../rtl/altera_onchip_flash_block.v           |    Bin 0 -> 4888 bytes
 .../submodules/rw_manager_ac_ROM_reg.v        |     49 +
 .../submodules/rw_manager_bitcheck.v          |     96 +
 .../synthesis/submodules/rw_manager_core.sv   |    668 +
 .../submodules/rw_manager_data_broadcast.v    |     58 +
 .../submodules/rw_manager_data_decoder.v      |     80 +
 .../synthesis/submodules/rw_manager_datamux.v |     42 +
 .../synthesis/submodules/rw_manager_ddr3.v    |    232 +
 .../submodules/rw_manager_di_buffer.v         |    139 +
 .../submodules/rw_manager_di_buffer_wrap.v    |     78 +
 .../submodules/rw_manager_dm_decoder.v        |     55 +
 .../submodules/rw_manager_generic.sv          |    713 +
 .../submodules/rw_manager_inst_ROM_reg.v      |     50 +
 .../submodules/rw_manager_jumplogic.v         |    127 +
 .../synthesis/submodules/rw_manager_lfsr12.v  |     48 +
 .../synthesis/submodules/rw_manager_lfsr36.v  |     72 +
 .../synthesis/submodules/rw_manager_lfsr72.v  |     44 +
 .../submodules/rw_manager_m10_ac_ROM.v        |     61 +
 .../submodules/rw_manager_m10_inst_ROM.v      |    148 +
 .../submodules/rw_manager_pattern_fifo.v      |     95 +
 .../synthesis/submodules/rw_manager_ram.v     |     56 +
 .../synthesis/submodules/rw_manager_ram_csr.v |     89 +
 .../submodules/rw_manager_read_datapath.v     |    158 +
 .../submodules/rw_manager_write_decoder.v     |    112 +
 .../q_sys/synthesis/submodules/sensor_algo.v  |    139 +
 .../sensor_algo_avalon_st_adapter.v           |    212 +
 .../sensor_algo_avalon_st_adapter_001.v       |    227 +
 ...on_st_adapter_001_data_format_adapter_0.sv |     99 +
 ..._avalon_st_adapter_001_timing_adapter_0.sv |    115 +
 ...avalon_st_adapter_data_format_adapter_0.sv |    396 +
 ..._adapter_data_format_adapter_0_data_ram.sv |    360 +
 ...adapter_data_format_adapter_0_state_ram.sv |    360 +
 ...algo_avalon_st_adapter_timing_adapter_0.sv |    115 +
 .../submodules/sensor_algo_cali_fac.v         |    126 +
 .../submodules/sensor_algo_calibration.v      |    126 +
 .../sensor_algo_mm_interconnect_0.v           |    163 +
 .../synthesis/submodules/sensor_interface.v   |    784 +
 .../q_sys/synthesis/submodules/sensor_rms.v   |    180 +
 .../synthesis/submodules/sequencer_m10.sv     |   1209 +
 .../synthesis/submodules/sequencer_phy_mgr.sv |    537 +
 .../synthesis/submodules/sequencer_pll_mgr.sv |    193 +
 .../q_sys/synthesis/submodules/serial_rx.v    |     84 +
 .../q_sys/synthesis/submodules/serial_tx.v    |    115 +
 .../synthesis/submodules/soft_asmiblock.sv    |     81 +
 .../q_sys/synthesis/submodules/sqrt.qip       |      6 +
 .../q_sys/synthesis/submodules/sqrt.v         |    104 +
 .../q_sys/synthesis/submodules/st2mm.v        |     81 +
 .../synthesis/submodules/st_splitter16.qip    |     52 +
 .../synthesis/submodules/st_splitter16.v      |    179 +
 .../q_sys/synthesis/submodules/stl2sts.v      |     84 +
 .../synthesis/submodules/udp_generator.v      |    396 +
 .../submodules/write_burst_control.v          |    300 +
 .../q_sys/synthesis/submodules/write_master.v |    920 +
 .../submodules/write_signal_breakout.v        |    125 +
 FPGA_firmware/q_sys_bk.qsys                   |   2547 +
 FPGA_firmware/q_sys_ddr3_ram_p0_summary.csv   |     23 +
 .../q_sys_mem_if_ddr3_emif_0_p0_summary.csv   |     23 +
 FPGA_firmware/quartus.ini                     |      1 +
 FPGA_firmware/rgmii_sdc/rgmii_clocks.sdc      |     90 +
 FPGA_firmware/rgmii_sdc/rgmii_input.sdc       |     63 +
 FPGA_firmware/rgmii_sdc/rgmii_output.sdc      |     90 +
 .../sensor_algo_qsys/.qsys_edit/cali_ram.xml  |   2185 +
 .../.qsys_edit/cali_ram_schematic.nlv         |      8 +
 .../sensor_algo_qsys/.qsys_edit/filters.xml   |      2 +
 .../.qsys_edit/preferences.xml                |     15 +
 .../.qsys_edit/sensor_algo.xml                |   2167 +
 .../.qsys_edit/sensor_algo_schematic.nlv      |     12 +
 .../.qsys_edit/sensor_recon.xml               |   2185 +
 .../.qsys_edit/sensor_recon_schematic.nlv     |      0
 .../.qsys_edit/st_splitter16.xml              |   2185 +
 .../.qsys_edit/st_splitter16_schematic.nlv    |      8 +
 .../sensor_algo_qsys/.qsys_edit/unsaved.xml   |   2185 +
 .../.qsys_edit/unsaved_schematic.nlv          |     14 +
 FPGA_firmware/sensor_algo_qsys/algo_top.v     |     91 +
 FPGA_firmware/sensor_algo_qsys/algo_top_cl.v  |    125 +
 .../sensor_algo_qsys/algo_top_cl_cali.v       |    206 +
 .../sensor_algo_qsys/algo_top_cl_cali_rms.v   |    352 +
 FPGA_firmware/sensor_algo_qsys/bkg_ram.sv     |    130 +
 .../sensor_algo_qsys/bkg_subtraction.v        |    217 +
 .../sensor_algo_qsys/bkg_subtraction_pipe.v   |    312 +
 FPGA_firmware/sensor_algo_qsys/cali_ram.qsys  |     91 +
 .../sensor_algo_qsys/cali_ram.sopcinfo        |   1491 +
 FPGA_firmware/sensor_algo_qsys/calibration.v  |    233 +
 .../sensor_algo_qsys/cluster_locate.sv        |    186 +
 .../sensor_algo_qsys/cluster_locate.v         |    165 +
 .../sensor_algo_qsys/data_caled_ram.qip       |      6 +
 .../sensor_algo_qsys/data_caled_ram.v         |    243 +
 .../sensor_algo_qsys/data_caled_ram_bb.v      |    180 +
 .../sensor_algo_qsys/data_caled_ram_inst.v    |     11 +
 FPGA_firmware/sensor_algo_qsys/div.bsf        |     86 +
 FPGA_firmware/sensor_algo_qsys/div.qip        |      6 +
 FPGA_firmware/sensor_algo_qsys/div.v          |    116 +
 FPGA_firmware/sensor_algo_qsys/div_inst.v     |      8 +
 .../sensor_algo_qsys/frame_counter.v          |     36 +
 .../sensor_algo_qsys/greybox_tmp/cbx_args.txt |     14 +
 .../greybox_tmp/greybox_tmp/mgd3n.v           |     67 +
 .../output_files/sensor_algo_qsys.pof         |    Bin 0 -> 1450250 bytes
 .../output_files/sensor_algo_qsys.sld         |      9 +
 .../output_files/sensor_algo_qsys.sof         |    Bin 0 -> 3221332 bytes
 .../sensor_algo_qsys/q_sys/cali_ram.bsf       |    200 +
 .../sensor_algo_qsys/q_sys/cali_ram.xml       |    343 +
 .../sensor_algo_qsys/q_sys/cali_ram_bb.v      |     40 +
 .../sensor_algo_qsys/q_sys/cali_ram_inst.v    |     21 +
 .../sensor_algo_qsys/q_sys/sensor_algo.bsf    |     38 +
 .../sensor_algo_qsys/q_sys/sensor_algo.xml    |    121 +
 .../sensor_algo_qsys/q_sys/sensor_algo_bb.v   |      5 +
 .../sensor_algo_qsys/q_sys/sensor_algo_inst.v |      3 +
 .../sensor_algo_qsys/q_sys/sensor_recon.bsf   |    294 +
 .../sensor_algo_qsys/q_sys/sensor_recon.xml   |    529 +
 .../sensor_algo_qsys/q_sys/sensor_recon_bb.v  |     62 +
 .../q_sys/sensor_recon_inst.v                 |     32 +
 .../sensor_algo_qsys/q_sys/st_splitter16.bsf  |    213 +
 .../sensor_algo_qsys/q_sys/st_splitter16.xml  |    292 +
 .../sensor_algo_qsys/q_sys/st_splitter16_bb.v |     44 +
 .../q_sys/st_splitter16_inst.v                |     23 +
 .../synthesis/altera_avalon_st_splitter.sv    |    422 +
 .../q_sys/synthesis/cali_ram.debuginfo        |   1513 +
 .../q_sys/synthesis/cali_ram.qip              |     69 +
 .../q_sys/synthesis/cali_ram.v                |     51 +
 .../q_sys/synthesis/sensor_algo.debuginfo     |   1312 +
 .../q_sys/synthesis/sensor_algo.qip           |     26 +
 .../q_sys/synthesis/sensor_algo.v             |     42 +
 .../q_sys/synthesis/sensor_recon.debuginfo    |   1318 +
 .../q_sys/synthesis/sensor_recon.qip          |     50 +
 .../q_sys/synthesis/sensor_recon.v            |     70 +
 .../q_sys/synthesis/st_splitter16.debuginfo   |    899 +
 .../q_sys/synthesis/st_splitter16.qip         |     52 +
 .../q_sys/synthesis/st_splitter16.v           |    179 +
 .../submodules/algo_top_cl_cali_rms.v         |    352 +
 .../submodules/altera_avalon_st_splitter.sv   |    422 +
 .../altera_merlin_master_translator.sv        |    556 +
 .../altera_merlin_slave_translator.sv         |    482 +
 .../submodules/altera_reset_controller.sdc    |     30 +
 .../submodules/altera_reset_controller.v      |    319 +
 .../submodules/altera_reset_synchronizer.v    |     87 +
 .../submodules/bkg_subtraction_pipe.v         |    287 +
 .../synthesis/submodules/cali_ram_cali_ram.v  |    126 +
 .../q_sys/synthesis/submodules/calibration.v  |    172 +
 .../synthesis/submodules/cluster_locate.sv    |    186 +
 .../synthesis/submodules/data_caled_ram.v     |    243 +
 .../q_sys/synthesis/submodules/div.v          |    116 +
 .../synthesis/submodules/frame_counter.v      |     36 +
 .../q_sys/synthesis/submodules/ram4bkg.v      |    214 +
 .../q_sys/synthesis/submodules/rms.sv         |    398 +
 .../q_sys/synthesis/submodules/sensor_algo.v  |    139 +
 .../sensor_algo_avalon_st_adapter.v           |    212 +
 .../sensor_algo_avalon_st_adapter_001.v       |    227 +
 ...on_st_adapter_001_data_format_adapter_0.sv |     99 +
 ..._avalon_st_adapter_001_timing_adapter_0.sv |    115 +
 ...avalon_st_adapter_data_format_adapter_0.sv |    396 +
 ..._adapter_data_format_adapter_0_data_ram.sv |    360 +
 ...adapter_data_format_adapter_0_state_ram.sv |    360 +
 ...algo_avalon_st_adapter_timing_adapter_0.sv |    115 +
 .../submodules/sensor_algo_cali_fac.v         |    126 +
 .../submodules/sensor_algo_calibration.v      |    126 +
 .../sensor_algo_mm_interconnect_0.v           |    163 +
 .../synthesis/submodules/sensor_interface.v   |    784 +
 .../q_sys/synthesis/submodules/serial_rx.v    |     84 +
 .../q_sys/synthesis/submodules/serial_tx.v    |    115 +
 .../q_sys/synthesis/submodules/sqrt.v         |    104 +
 .../q_sys/synthesis/submodules/st2mm.v        |     81 +
 .../synthesis/submodules/st_splitter16.v      |    179 +
 .../q_sys/synthesis/submodules/stl2sts.v      |     84 +
 .../q_sys/synthesis/unsaved.debuginfo         |   1318 +
 .../q_sys/synthesis/unsaved.qip               |     49 +
 .../q_sys/synthesis/unsaved.v                 |     70 +
 .../sensor_algo_qsys/q_sys/unsaved.bsf        |    294 +
 .../sensor_algo_qsys/q_sys/unsaved.xml        |    521 +
 .../sensor_algo_qsys/q_sys/unsaved_bb.v       |     62 +
 .../sensor_algo_qsys/q_sys/unsaved_inst.v     |     32 +
 FPGA_firmware/sensor_algo_qsys/ram4bkg.qip    |      6 +
 FPGA_firmware/sensor_algo_qsys/ram4bkg.v      |    214 +
 FPGA_firmware/sensor_algo_qsys/ram4bkg_bb.v   |    160 +
 FPGA_firmware/sensor_algo_qsys/ram4bkg_inst.v |      8 +
 FPGA_firmware/sensor_algo_qsys/ram_sim.qip    |      6 +
 FPGA_firmware/sensor_algo_qsys/ram_sim.v      |    253 +
 FPGA_firmware/sensor_algo_qsys/ram_sim_bb.v   |    190 +
 FPGA_firmware/sensor_algo_qsys/ram_sim_inst.v |     13 +
 FPGA_firmware/sensor_algo_qsys/rms.sv         |    396 +
 .../sensor_algo_qsys/sensor_algo.sopcinfo     |   1260 +
 FPGA_firmware/sensor_algo_qsys/sensor_algo.v  |    139 +
 .../sensor_algo_qsys/sensor_algo_inst.v       |     42 +
 .../sensor_algo_qsys/sensor_algo_qsys.qpf     |     31 +
 .../sensor_algo_qsys/sensor_algo_qsys.qsf     |    133 +
 .../sensor_algo_qsys/sensor_interface.v       |    784 +
 .../sensor_algo_qsys/sensor_recon.sopcinfo    |   1286 +
 FPGA_firmware/sensor_algo_qsys/serial_rx.v    |     84 +
 FPGA_firmware/sensor_algo_qsys/serial_tx.v    |    115 +
 FPGA_firmware/sensor_algo_qsys/sqrt.qip       |      6 +
 FPGA_firmware/sensor_algo_qsys/sqrt.v         |    104 +
 FPGA_firmware/sensor_algo_qsys/sqrt_bb.v      |     76 +
 FPGA_firmware/sensor_algo_qsys/sqrt_inst.v    |      7 +
 FPGA_firmware/sensor_algo_qsys/st2mm.v        |     86 +
 FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v    |     80 +
 .../sensor_algo_qsys/st_splitter16.qsys       |     91 +
 .../sensor_algo_qsys/st_splitter16.sopcinfo   |    847 +
 FPGA_firmware/sensor_algo_qsys/stl2sts.v      |     84 +
 FPGA_firmware/sensor_algo_qsys/sts2stl.v      |    108 +
 .../testbench/algo_top_cl_cali_rms_tb.v       |    177 +
 .../testbench/algo_top_cl_cali_tb.v           |    158 +
 .../testbench/algo_top_cl_tb.v                |    160 +
 .../sensor_algo_qsys/testbench/algo_top_tb.v  |    136 +
 .../testbench/bkg_subtraction_pipe_tb.v       |    143 +
 .../testbench/bkg_subtraction_tb.v            |    136 +
 .../testbench/calibration_tb.v                |    217 +
 .../testbench/cluster_locate_tb.v             |    172 +
 .../testbench/sensor_algo_tb.v                |    171 +
 .../sensor_algo_qsys/testbench/st2mm_tb.v     |    135 +
 .../sensor_algo_qsys/testbench/stl2sts_tb.v   |    126 +
 .../sensor_algo_qsys/testbench/sts2stl_tb.v   |    126 +
 FPGA_firmware/sensor_algo_qsys/unsaved.qsys   |     86 +
 .../sensor_algo_qsys/unsaved.sopcinfo         |   1286 +
 FPGA_firmware/sensor_testbench.v              |    131 +
 FPGA_firmware/serial_rx.v                     |     84 +
 FPGA_firmware/serial_testbench.v              |     77 +
 FPGA_firmware/serial_tx.v                     |    115 +
 FPGA_firmware/tcl_readme.txt                  |      3 +
 FPGA_firmware/udp_generator.v                 |    396 +
 FPGA_firmware/udp_testbench.v                 |    180 +
 FPGA_nios/.gitignore                          |     60 +
 FPGA_nios/hit_pat/.force_relink               |      0
 FPGA_nios/hit_pat/.project                    |     41 +
 FPGA_nios/hit_pat/create-this-app             |    131 +
 FPGA_nios/hit_pat/hit_pat.elf                 |    Bin 0 -> 2092301 bytes
 FPGA_nios/hit_pat/hit_pat.map                 |   5024 +
 FPGA_nios/hit_pat/hit_pat.objdump             | 106020 +++++++++++++++
 FPGA_nios/hit_pat/inc/control.h               |     39 +
 FPGA_nios/hit_pat/inc/dev_commands.h          |    136 +
 FPGA_nios/hit_pat/inc/network_utilities.h     |     49 +
 FPGA_nios/hit_pat/inc/sensor.h                |     67 +
 FPGA_nios/hit_pat/inc/socket_server.h         |    144 +
 FPGA_nios/hit_pat/inc/udpgen.h                |     54 +
 FPGA_nios/hit_pat/inc/utils.h                 |     34 +
 FPGA_nios/hit_pat/mem_init/ext_flash.hex      |  19658 +++
 .../hit_pat/mem_init/hdl_sim/onchip_flash.dat |      0
 .../hit_pat/mem_init/hdl_sim/onchip_flash.sym |   1138 +
 .../hdl_sim/q_sys_calibration_ram.dat         |      0
 .../hdl_sim/q_sys_calibration_ram.sym         |   1138 +
 .../hdl_sim/q_sys_descriptor_memory.dat       |      0
 .../hdl_sim/q_sys_descriptor_memory.sym       |   1138 +
 FPGA_nios/hit_pat/mem_init/meminit.qip        |      1 +
 FPGA_nios/hit_pat/mem_init/meminit.spd        |     10 +
 FPGA_nios/hit_pat/mem_init/onchip_flash.hex   |      1 +
 .../mem_init/q_sys_calibration_ram.hex        |     22 +
 .../mem_init/q_sys_descriptor_memory.hex      |    258 +
 FPGA_nios/hit_pat/obj/default/src/control.d   |    140 +
 FPGA_nios/hit_pat/obj/default/src/main.d      |     99 +
 .../obj/default/src/network_utilities.d       |    121 +
 FPGA_nios/hit_pat/obj/default/src/sensor.d    |    140 +
 .../hit_pat/obj/default/src/socket_server.d   |    124 +
 .../hit_pat/obj/default/src/tse_my_system.d   |     99 +
 FPGA_nios/hit_pat/obj/default/src/udpgen.d    |    137 +
 FPGA_nios/hit_pat/obj/default/src/utils.d     |    108 +
 FPGA_nios/hit_pat/onchip_flash.flash          |      2 +
 FPGA_nios/hit_pat/readme.txt                  |    101 +
 FPGA_nios/hit_pat/src/control.c               |    390 +
 FPGA_nios/hit_pat/src/main.c                  |    161 +
 FPGA_nios/hit_pat/src/network_utilities.c     |    456 +
 FPGA_nios/hit_pat/src/sensor.c                |     53 +
 FPGA_nios/hit_pat/src/socket_server.c         |    332 +
 FPGA_nios/hit_pat/src/tse_my_system.c         |     12 +
 FPGA_nios/hit_pat/src/udpgen.c                |     51 +
 FPGA_nios/hit_pat/src/utils.c                 |    131 +
 FPGA_nios/hit_pat_bsp/.project                |     29 +
 FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h     |     54 +
 .../HAL/inc/altera_nios2_gen2_irq.h           |     80 +
 FPGA_nios/hit_pat_bsp/HAL/inc/includes.h      |     65 +
 FPGA_nios/hit_pat_bsp/HAL/inc/io.h            |     81 +
 FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h         |    300 +
 FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h        |    145 +
 .../hit_pat_bsp/HAL/inc/priv/alt_alarm.h      |    101 +
 .../hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h |     35 +
 .../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h  |     77 +
 .../inc/priv/alt_exception_handler_registry.h |     39 +
 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h |    179 +
 .../HAL/inc/priv/alt_iic_isr_register.h       |     39 +
 .../hit_pat_bsp/HAL/inc/priv/alt_irq_table.h  |     59 +
 .../hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h |    158 +
 .../hit_pat_bsp/HAL/inc/priv/alt_no_error.h   |     77 +
 .../HAL/inc/priv/nios2_gmon_data.h            |     47 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h |    126 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h |    117 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h |     45 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h   |    115 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h   |    226 +
 .../hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h     |    200 +
 .../hit_pat_bsp/HAL/inc/sys/alt_driver.h      |    168 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h |     87 +
 .../hit_pat_bsp/HAL/inc/sys/alt_exceptions.h  |    166 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h |    181 +
 .../hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h   |    100 +
 .../hit_pat_bsp/HAL/inc/sys/alt_flash_types.h |     64 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h   |    245 +
 .../hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h   |     39 +
 .../HAL/inc/sys/alt_license_reminder_ucosii.h |     77 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h |    123 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h  |     78 +
 .../hit_pat_bsp/HAL/inc/sys/alt_log_printf.h  |    354 +
 .../hit_pat_bsp/HAL/inc/sys/alt_set_args.h    |     71 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h   |     91 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h |    126 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h |     66 +
 .../hit_pat_bsp/HAL/inc/sys/alt_sys_init.h    |     62 +
 .../HAL/inc/sys/alt_sys_wrappers.h            |    100 +
 .../hit_pat_bsp/HAL/inc/sys/alt_timestamp.h   |     60 +
 .../hit_pat_bsp/HAL/inc/sys/alt_warning.h     |     75 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h     |     90 +
 FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h   |    181 +
 .../hit_pat_bsp/HAL/src/alt_alarm_start.c     |    112 +
 .../hit_pat_bsp/HAL/src/alt_busy_sleep.c      |    133 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_close.c     |    103 +
 .../hit_pat_bsp/HAL/src/alt_dcache_flush.c    |     70 +
 .../HAL/src/alt_dcache_flush_all.c            |     51 +
 .../HAL/src/alt_dcache_flush_no_writeback.c   |     69 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c       |    149 +
 .../HAL/src/alt_dev_llist_insert.c            |     59 +
 .../hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c |     63 +
 .../hit_pat_bsp/HAL/src/alt_dma_txchan_open.c |     63 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c  |     64 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c  |     64 +
 .../hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S |    102 +
 .../HAL/src/alt_ecc_fatal_exception.c         |     75 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c   |     42 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c     |     44 +
 .../hit_pat_bsp/HAL/src/alt_exception_entry.S |    402 +
 .../HAL/src/alt_exception_muldiv.S            |    583 +
 .../hit_pat_bsp/HAL/src/alt_exception_trap.S  |     95 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c    |     55 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c      |     71 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c     |    101 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c   |     75 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c |     56 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c  |     88 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c |     89 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c |     69 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c      |     57 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c    |     75 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c     |    128 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c    |    105 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c   |     70 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c    |     47 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c    |    125 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c      |    272 +
 .../hit_pat_bsp/HAL/src/alt_icache_flush.c    |     84 +
 .../HAL/src/alt_icache_flush_all.c            |     46 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c       |    106 +
 .../HAL/src/alt_iic_isr_register.c            |    104 +
 .../HAL/src/alt_instruction_exception_entry.c |    206 +
 .../src/alt_instruction_exception_register.c  |     82 +
 .../hit_pat_bsp/HAL/src/alt_io_redirect.c     |     98 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c     |    170 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S |    108 +
 .../hit_pat_bsp/HAL/src/alt_irq_handler.c     |    169 +
 .../hit_pat_bsp/HAL/src/alt_irq_register.c    |    102 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c  |     47 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c    |    125 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c      |    121 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c      |     56 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c      |     99 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S |     60 +
 .../hit_pat_bsp/HAL/src/alt_log_printf.c      |    479 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c     |    117 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c      |    161 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S    |    198 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c      |    173 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c    |    132 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c   |     68 +
 .../hit_pat_bsp/HAL/src/alt_putcharbuf.c      |     80 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c    |     64 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c      |    125 +
 .../hit_pat_bsp/HAL/src/alt_release_fd.c      |     54 +
 .../hit_pat_bsp/HAL/src/alt_remap_cached.c    |     55 +
 .../hit_pat_bsp/HAL/src/alt_remap_uncached.c  |     54 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c    |     55 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c      |    136 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c    |     96 +
 .../HAL/src/alt_software_exception.S          |     53 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c      |     59 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c      |    149 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c     |     71 +
 .../hit_pat_bsp/HAL/src/alt_uncached_free.c   |     53 +
 .../hit_pat_bsp/HAL/src/alt_uncached_malloc.c |     77 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c    |     55 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c    |    104 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c      |     52 +
 FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c     |    138 +
 .../HAL/src/altera_nios2_gen2_irq.c           |     37 +
 FPGA_nios/hit_pat_bsp/HAL/src/crt0.S          |    521 +
 FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S      |    270 +
 FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c      |    243 +
 .../Micrium_45_Day_Evaluation_License.pdf     |    Bin 0 -> 96321 bytes
 .../hit_pat_bsp/UCOSII/inc/os/alt_flag.h      |     87 +
 .../hit_pat_bsp/UCOSII/inc/os/alt_hooks.h     |     69 +
 FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h |     85 +
 FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h     |     65 +
 .../UCOSII/inc/priv/alt_flag_ucosii.h         |    109 +
 .../UCOSII/inc/priv/alt_sem_ucosii.h          |     82 +
 FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h    |   1930 +
 .../hit_pat_bsp/UCOSII/license-ucosii.txt     |     20 +
 .../hit_pat_bsp/UCOSII/src/alt_env_lock.c     |    122 +
 .../hit_pat_bsp/UCOSII/src/alt_malloc_lock.c  |    147 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c    |   2018 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c     |    312 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c    |   1174 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c    |    629 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c     |    434 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c   |    715 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c       |    868 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c     |    609 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c    |   1095 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c    |    268 +
 FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c     |   1116 +
 FPGA_nios/hit_pat_bsp/alt_sys_init.c          |    115 +
 FPGA_nios/hit_pat_bsp/create-this-bsp         |     52 +
 .../drivers/inc/altera_avalon_pio_regs.h      |     67 +
 .../drivers/inc/altera_avalon_sysid_qsys.h    |     60 +
 .../inc/altera_avalon_sysid_qsys_regs.h       |     42 +
 .../drivers/inc/altera_avalon_timer.h         |    193 +
 .../drivers/inc/altera_avalon_timer_regs.h    |    202 +
 .../drivers/inc/altera_avalon_tse.h           |   1023 +
 .../inc/altera_avalon_tse_system_info.h       |    352 +
 .../drivers/inc/altera_avalon_uart.h          |    319 +
 .../drivers/inc/altera_avalon_uart_fd.h       |    143 +
 .../drivers/inc/altera_avalon_uart_regs.h     |    137 +
 .../hit_pat_bsp/drivers/inc/altera_eth_tse.h  |     45 +
 .../drivers/inc/altera_eth_tse_regs.h         |    735 +
 .../inc/altera_generic_quad_spi_controller.h  |    126 +
 .../altera_generic_quad_spi_controller_regs.h |    260 +
 .../hit_pat_bsp/drivers/inc/altera_msgdma.h   |    512 +
 .../drivers/inc/altera_msgdma_csr_regs.h      |    175 +
 .../inc/altera_msgdma_descriptor_regs.h       |    163 +
 .../inc/altera_msgdma_prefetcher_regs.h       |    292 +
 .../drivers/inc/altera_msgdma_response_regs.h |     70 +
 .../drivers/inc/altera_onchip_flash.h         |    167 +
 .../drivers/inc/altera_onchip_flash_regs.h    |    241 +
 .../inc/iniche/altera_eth_tse_iniche.h        |    250 +
 .../drivers/inc/iniche/ins_tse_mac.h          |     88 +
 .../drivers/src/altera_avalon_sysid_qsys.c    |     82 +
 .../drivers/src/altera_avalon_timer_sc.c      |    110 +
 .../drivers/src/altera_avalon_timer_ts.c      |    143 +
 .../drivers/src/altera_avalon_timer_vars.c    |     45 +
 .../drivers/src/altera_avalon_tse.c           |   2339 +
 .../src/altera_avalon_tse_system_info.c       |     61 +
 .../drivers/src/altera_avalon_uart_fd.c       |    100 +
 .../drivers/src/altera_avalon_uart_init.c     |    312 +
 .../drivers/src/altera_avalon_uart_ioctl.c    |    153 +
 .../drivers/src/altera_avalon_uart_read.c     |    240 +
 .../drivers/src/altera_avalon_uart_write.c    |    232 +
 .../src/altera_generic_quad_spi_controller.c  |    797 +
 .../hit_pat_bsp/drivers/src/altera_msgdma.c   |   1806 +
 .../drivers/src/altera_onchip_flash.c         |    590 +
 .../drivers/src/iniche/ins_tse_mac.c          |    911 +
 .../hit_pat_bsp/iniche/inc/alt_iniche_dev.h   |    215 +
 .../hit_pat_bsp/iniche/inc/os/alt_syscall.h   |     77 +
 .../iniche/src/allports/allports.c            |    947 +
 .../iniche/src/allports/timeouts.c            |    360 +
 .../hit_pat_bsp/iniche/src/allports/tk_misc.c |    358 +
 .../hit_pat_bsp/iniche/src/alt_iniche_close.c |     61 +
 .../hit_pat_bsp/iniche/src/alt_iniche_dev.c   |    147 +
 .../hit_pat_bsp/iniche/src/alt_iniche_fcntl.c |     74 +
 .../hit_pat_bsp/iniche/src/alt_iniche_read.c  |     64 +
 .../hit_pat_bsp/iniche/src/alt_iniche_write.c |     72 +
 .../hit_pat_bsp/iniche/src/autoip4/autoip.c   |    383 +
 .../hit_pat_bsp/iniche/src/autoip4/autoip.h   |     58 +
 .../hit_pat_bsp/iniche/src/autoip4/ds_app.h   |     75 +
 .../hit_pat_bsp/iniche/src/autoip4/upnp.c     |    651 +
 .../hit_pat_bsp/iniche/src/autoip4/upnp.h     |     61 +
 .../hit_pat_bsp/iniche/src/autoip4/upnpmenu.c |    266 +
 .../hit_pat_bsp/iniche/src/ftp/ftpclnt.c      |   2424 +
 .../hit_pat_bsp/iniche/src/ftp/ftpclnt.h      |    244 +
 .../hit_pat_bsp/iniche/src/ftp/ftpcport.c     |    205 +
 .../hit_pat_bsp/iniche/src/ftp/ftpcprn.c      |    137 +
 .../hit_pat_bsp/iniche/src/ftp/ftpmenu.c      |    971 +
 .../hit_pat_bsp/iniche/src/ftp/ftpport.h      |    128 +
 .../hit_pat_bsp/iniche/src/ftp/ftpsport.c     |    535 +
 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c |   2061 +
 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h |    159 +
 .../hit_pat_bsp/iniche/src/ftp/ftpssock.c     |    759 +
 .../hit_pat_bsp/iniche/src/ftp/ftpsvfs.c      |    233 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h |    145 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h      |    127 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h  |    154 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h  |    116 +
 .../hit_pat_bsp/iniche/src/h/crypt_api.h      |    245 +
 .../hit_pat_bsp/iniche/src/h/crypt_port.h     |    241 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h |    266 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h      |    216 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h  |     40 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h    |     94 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h  |    142 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h |    123 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/icmp.h     |    207 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ifmap.h    |     44 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/in_utils.h |    131 +
 .../hit_pat_bsp/iniche/src/h/iniche_log.h     |     52 +
 .../iniche/src/h/iniche_log_port.h            |     18 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/intimers.h |     40 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ip.h       |    498 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ip6.h      |    464 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/libport.h  |     72 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/mbuf.h     |     84 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/memwrap.h  |     24 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/menu.h     |     59 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/msring.h   |     37 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/nameser.h  |    427 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/net.h      |    478 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/netbuf.h   |    177 +
 .../hit_pat_bsp/iniche/src/h/nios2/ipport.h   |    872 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/nptcp.h    |    348 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/nptypes.h  |     80 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ns.h       |    374 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ns_debug.h |     84 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/nvfsio.h   |     79 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/nvparms.h  |    238 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/pmtu.h     |     81 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/ppp_port.h |    151 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/profiler.h |    118 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/q.h        |    111 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/snmp_vie.h |   1048 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/snmpport.h |    257 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/sockcall.h |    123 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/socket.h   |    201 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/socket6.h  |     87 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/sockvar.h  |    249 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/syslog.h   |    162 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/task.h     |     81 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/tcp.h      |     96 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/tcpapp.h   |     36 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/tcpport.h  |    326 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/tk_crnos.h |    147 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/tk_ntask.h |     67 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/udp.h      |    153 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/userpass.h |     53 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/vfsfiles.h |    336 +
 FPGA_nios/hit_pat_bsp/iniche/src/h/webport.h  |     76 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/et_arp.c  |   1223 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/icmp.c    |    633 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/iface.c   |    884 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ip.c      |   1407 +
 .../hit_pat_bsp/iniche/src/ip/ip_reasm.c      |   1343 +
 .../hit_pat_bsp/iniche/src/ip/ip_reasm.h      |    130 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipdemux.c |    673 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipmc.c    |    242 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipnet.c   |    727 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipport.c  |    127 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipraw.c   |    348 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/iproute.c |    725 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipstart.c |    311 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/pmtu.c    |    407 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/rtbtree.c |    884 +
 FPGA_nios/hit_pat_bsp/iniche/src/ip/udp.c     |    694 +
 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.c  |    164 +
 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.h  |    117 +
 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.c |    431 +
 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.h |     39 +
 .../hit_pat_bsp/iniche/src/ipmc/igmp_cmn.c    |    747 +
 .../hit_pat_bsp/iniche/src/ipmc/igmp_cmn.h    |    189 +
 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/ipopt.c |    435 +
 .../hit_pat_bsp/iniche/src/ipmc/u_mctest.c    |    291 +
 .../hit_pat_bsp/iniche/src/misclib/app_ping.c |   1140 +
 .../hit_pat_bsp/iniche/src/misclib/bsdsock.c  |    645 +
 .../hit_pat_bsp/iniche/src/misclib/cksum.c    |    233 +
 .../hit_pat_bsp/iniche/src/misclib/cu_srv.c   |    613 +
 .../hit_pat_bsp/iniche/src/misclib/dhcsetup.c |    184 +
 .../hit_pat_bsp/iniche/src/misclib/genlist.c  |    904 +
 .../hit_pat_bsp/iniche/src/misclib/in_utils.c |    619 +
 .../iniche/src/misclib/iniche_log.c           |    326 +
 .../iniche/src/misclib/iniche_qsort.c         |    174 +
 .../iniche/src/misclib/localtime.c            |    115 +
 .../hit_pat_bsp/iniche/src/misclib/memdev.c   |    396 +
 .../hit_pat_bsp/iniche/src/misclib/memio.c    |    397 +
 .../hit_pat_bsp/iniche/src/misclib/memwrap.c  |    222 +
 .../hit_pat_bsp/iniche/src/misclib/menulib.c  |    430 +
 .../hit_pat_bsp/iniche/src/misclib/menus.c    |    445 +
 .../hit_pat_bsp/iniche/src/misclib/msring.c   |    131 +
 .../hit_pat_bsp/iniche/src/misclib/netmain.c  |    582 +
 .../hit_pat_bsp/iniche/src/misclib/nextcarg.c |     74 +
 .../hit_pat_bsp/iniche/src/misclib/nrmenus.c  |   2126 +
 .../hit_pat_bsp/iniche/src/misclib/nvfsio.c   |    329 +
 .../hit_pat_bsp/iniche/src/misclib/nvparms.c  |   1367 +
 .../hit_pat_bsp/iniche/src/misclib/parseip.c  |    597 +
 .../hit_pat_bsp/iniche/src/misclib/pcycles.c  |    858 +
 .../hit_pat_bsp/iniche/src/misclib/profiler.c |    539 +
 .../hit_pat_bsp/iniche/src/misclib/rawiptst.c |   1298 +
 .../hit_pat_bsp/iniche/src/misclib/reshost.c  |    127 +
 .../hit_pat_bsp/iniche/src/misclib/rfsim.c    |    249 +
 .../hit_pat_bsp/iniche/src/misclib/rttest.c   |    744 +
 .../hit_pat_bsp/iniche/src/misclib/soperr.c   |     77 +
 .../hit_pat_bsp/iniche/src/misclib/strilib.c  |    142 +
 .../hit_pat_bsp/iniche/src/misclib/strlib.c   |    239 +
 .../hit_pat_bsp/iniche/src/misclib/strtol.c   |    260 +
 .../hit_pat_bsp/iniche/src/misclib/syslog.c   |   1811 +
 .../hit_pat_bsp/iniche/src/misclib/task.c     |    488 +
 .../hit_pat_bsp/iniche/src/misclib/tcp_echo.c |   1147 +
 .../hit_pat_bsp/iniche/src/misclib/tcpcksum.c |    114 +
 .../hit_pat_bsp/iniche/src/misclib/testmenu.c |    519 +
 .../hit_pat_bsp/iniche/src/misclib/tk_crnos.c |    284 +
 .../hit_pat_bsp/iniche/src/misclib/ttyio.c    |    850 +
 .../hit_pat_bsp/iniche/src/misclib/udp_echo.c |    751 +
 .../hit_pat_bsp/iniche/src/misclib/userpass.c |    237 +
 .../hit_pat_bsp/iniche/src/net/dhcpclnt.c     |   1507 +
 .../hit_pat_bsp/iniche/src/net/dhcputil.c     |     59 +
 .../hit_pat_bsp/iniche/src/net/dnsclnt.c      |   3628 +
 .../hit_pat_bsp/iniche/src/net/heapbuf.h      |     71 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/ifmap.c  |    170 +
 .../hit_pat_bsp/iniche/src/net/macloop.c      |    577 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/ping.c   |    140 +
 .../hit_pat_bsp/iniche/src/net/pktalloc.c     |   1024 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/q.c      |    178 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/slip.c   |    199 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/slip.h   |     80 +
 FPGA_nios/hit_pat_bsp/iniche/src/net/slipif.c |    494 +
 .../hit_pat_bsp/iniche/src/net/slipport.h     |     62 +
 .../hit_pat_bsp/iniche/src/net/udp_open.c     |    174 +
 .../hit_pat_bsp/iniche/src/nios2/asm_cksum.S  |    168 +
 .../hit_pat_bsp/iniche/src/nios2/brdutils.c   |    241 +
 .../hit_pat_bsp/iniche/src/nios2/osport.h     |    156 +
 .../hit_pat_bsp/iniche/src/nios2/osportco.c   |    481 +
 .../hit_pat_bsp/iniche/src/nios2/targnios.c   |    887 +
 FPGA_nios/hit_pat_bsp/iniche/src/nios2/uart.h |     29 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.c |    443 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.h |    120 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/nptcp.c  |   1623 +
 .../hit_pat_bsp/iniche/src/tcp/protosw.h      |    239 +
 .../hit_pat_bsp/iniche/src/tcp/rawsock.c      |    438 +
 .../hit_pat_bsp/iniche/src/tcp/sockcall.c     |   1150 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket.c |   1431 +
 .../hit_pat_bsp/iniche/src/tcp/socket2.c      |    903 +
 .../hit_pat_bsp/iniche/src/tcp/soselect.c     |    465 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_fsm.h      |    111 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_in.c |   2184 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_menu.c     |    275 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_out.c      |   1103 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_seq.h      |     80 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_subr.c     |    569 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_timr.c     |    438 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_timr.h     |    147 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_usr.c      |    617 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_var.h      |    314 +
 .../hit_pat_bsp/iniche/src/tcp/tcp_zio.c      |    272 +
 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpip.h  |    111 +
 .../hit_pat_bsp/iniche/src/tcp/tcpport.c      |    117 +
 .../hit_pat_bsp/iniche/src/tcp/tcpsack.c      |    394 +
 .../hit_pat_bsp/iniche/src/tcp/udpsock.c      |    560 +
 .../hit_pat_bsp/iniche/src/telnet/telerr.c    |     90 +
 .../hit_pat_bsp/iniche/src/telnet/telmenu.c   |    239 +
 .../hit_pat_bsp/iniche/src/telnet/telnet.c    |   1145 +
 .../hit_pat_bsp/iniche/src/telnet/telnet.h    |    350 +
 .../hit_pat_bsp/iniche/src/telnet/telparse.c  |    685 +
 .../hit_pat_bsp/iniche/src/telnet/telport.c   |    902 +
 .../hit_pat_bsp/iniche/src/telnet/telport.h   |    220 +
 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftp.h  |    186 +
 .../hit_pat_bsp/iniche/src/tftp/tftpcli.c     |    191 +
 .../hit_pat_bsp/iniche/src/tftp/tftpmenu.c    |    276 +
 .../hit_pat_bsp/iniche/src/tftp/tftpport.c    |    105 +
 .../hit_pat_bsp/iniche/src/tftp/tftpport.h    |     69 +
 .../hit_pat_bsp/iniche/src/tftp/tftpsrv.c     |    288 +
 .../hit_pat_bsp/iniche/src/tftp/tftpudp.c     |    314 +
 .../hit_pat_bsp/iniche/src/tftp/tftputil.c    |    858 +
 .../hit_pat_bsp/iniche/src/vfs/vfsfiles.c     |   1932 +
 .../hit_pat_bsp/iniche/src/vfs/vfsport.c      |    108 +
 .../hit_pat_bsp/iniche/src/vfs/vfsport.h      |     45 +
 .../hit_pat_bsp/iniche/src/vfs/vfssync.c      |    434 +
 .../hit_pat_bsp/iniche/src/vfs/vfsutil.c      |   1190 +
 FPGA_nios/hit_pat_bsp/linker.h                |    103 +
 FPGA_nios/hit_pat_bsp/linker.x                |    402 +
 FPGA_nios/hit_pat_bsp/mem_init.mk             |    455 +
 FPGA_nios/hit_pat_bsp/memory.gdb              |     62 +
 .../hit_pat_bsp/obj/HAL/src/alt_alarm_start.d |     20 +
 .../hit_pat_bsp/obj/HAL/src/alt_busy_sleep.d  |     10 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_close.d |     52 +
 .../obj/HAL/src/alt_dcache_flush.d            |     13 +
 .../obj/HAL/src/alt_dcache_flush_all.d        |     13 +
 .../HAL/src/alt_dcache_flush_no_writeback.d   |     13 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev.d   |     46 +
 .../obj/HAL/src/alt_dev_llist_insert.d        |     11 +
 .../obj/HAL/src/alt_dma_rxchan_open.d         |     53 +
 .../obj/HAL/src/alt_dma_txchan_open.d         |     53 +
 .../hit_pat_bsp/obj/HAL/src/alt_do_ctors.d    |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_do_dtors.d    |      1 +
 .../obj/HAL/src/alt_ecc_fatal_entry.d         |      1 +
 .../obj/HAL/src/alt_ecc_fatal_exception.d     |     17 +
 .../hit_pat_bsp/obj/HAL/src/alt_environ.d     |      4 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_errno.d |      6 +
 .../obj/HAL/src/alt_exception_entry.d         |      6 +
 .../obj/HAL/src/alt_exception_muldiv.d        |      1 +
 .../obj/HAL/src/alt_exception_trap.d          |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_execve.d      |     11 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exit.d  |     43 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fcntl.d |     50 +
 .../hit_pat_bsp/obj/HAL/src/alt_fd_lock.d     |     45 +
 .../hit_pat_bsp/obj/HAL/src/alt_fd_unlock.d   |     46 +
 .../hit_pat_bsp/obj/HAL/src/alt_find_dev.d    |     46 +
 .../hit_pat_bsp/obj/HAL/src/alt_find_file.d   |     46 +
 .../hit_pat_bsp/obj/HAL/src/alt_flash_dev.d   |     51 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fork.d  |     10 +
 .../hit_pat_bsp/obj/HAL/src/alt_fs_reg.d      |     46 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fstat.d |     52 +
 .../hit_pat_bsp/obj/HAL/src/alt_get_fd.d      |     46 +
 .../hit_pat_bsp/obj/HAL/src/alt_getchar.d     |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_getpid.d      |      4 +
 .../hit_pat_bsp/obj/HAL/src/alt_gettod.d      |     13 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gmon.d  |     22 +
 .../obj/HAL/src/alt_icache_flush.d            |     13 +
 .../obj/HAL/src/alt_icache_flush_all.d        |     13 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic.d   |     17 +
 .../obj/HAL/src/alt_iic_isr_register.d        |     20 +
 .../HAL/src/alt_instruction_exception_entry.d |     13 +
 .../src/alt_instruction_exception_register.d  |     14 +
 .../hit_pat_bsp/obj/HAL/src/alt_io_redirect.d |     46 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ioctl.d |     55 +
 .../hit_pat_bsp/obj/HAL/src/alt_irq_entry.d   |      5 +
 .../hit_pat_bsp/obj/HAL/src/alt_irq_handler.d |     36 +
 .../obj/HAL/src/alt_irq_register.d            |     43 +
 .../hit_pat_bsp/obj/HAL/src/alt_irq_vars.d    |      8 +
 .../hit_pat_bsp/obj/HAL/src/alt_isatty.d      |     53 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_kill.d  |      8 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_link.d  |     10 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_load.d  |      8 +
 .../hit_pat_bsp/obj/HAL/src/alt_log_macro.d   |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_log_printf.d  |      1 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_lseek.d |     52 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_main.d  |     55 +
 .../hit_pat_bsp/obj/HAL/src/alt_mcount.d      |      1 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_open.d  |     52 +
 .../hit_pat_bsp/obj/HAL/src/alt_printf.d      |      3 +
 .../hit_pat_bsp/obj/HAL/src/alt_putchar.d     |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_putcharbuf.d  |      1 +
 .../hit_pat_bsp/obj/HAL/src/alt_putstr.d      |      1 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_read.d  |     52 +
 .../hit_pat_bsp/obj/HAL/src/alt_release_fd.d  |     46 +
 .../obj/HAL/src/alt_remap_cached.d            |     13 +
 .../obj/HAL/src/alt_remap_uncached.d          |     13 +
 .../hit_pat_bsp/obj/HAL/src/alt_rename.d      |     11 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_sbrk.d  |     17 +
 .../hit_pat_bsp/obj/HAL/src/alt_settod.d      |     15 +
 .../obj/HAL/src/alt_software_exception.d      |      6 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_stat.d  |      3 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_tick.d  |     36 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_times.d |     15 +
 .../obj/HAL/src/alt_uncached_free.d           |     13 +
 .../obj/HAL/src/alt_uncached_malloc.d         |     13 +
 .../hit_pat_bsp/obj/HAL/src/alt_unlink.d      |     11 +
 .../hit_pat_bsp/obj/HAL/src/alt_usleep.d      |     36 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_wait.d  |      8 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_write.d |     55 +
 .../obj/HAL/src/altera_nios2_gen2_irq.d       |     15 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/crt0.d      |     10 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_a.d  |      8 +
 FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_c.d  |     31 +
 .../hit_pat_bsp/obj/UCOSII/src/alt_env_lock.d |     31 +
 .../obj/UCOSII/src/alt_malloc_lock.d          |     31 +
 .../hit_pat_bsp/obj/UCOSII/src/os_core.d      |     26 +
 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_dbg.d |     26 +
 .../hit_pat_bsp/obj/UCOSII/src/os_flag.d      |     26 +
 .../hit_pat_bsp/obj/UCOSII/src/os_mbox.d      |     26 +
 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mem.d |     26 +
 .../hit_pat_bsp/obj/UCOSII/src/os_mutex.d     |     26 +
 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_q.d   |     26 +
 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_sem.d |     26 +
 .../hit_pat_bsp/obj/UCOSII/src/os_task.d      |     26 +
 .../hit_pat_bsp/obj/UCOSII/src/os_time.d      |     26 +
 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_tmr.d |     26 +
 FPGA_nios/hit_pat_bsp/obj/alt_sys_init.d      |    173 +
 .../drivers/src/altera_avalon_sysid_qsys.d    |     19 +
 .../obj/drivers/src/altera_avalon_timer_sc.d  |     42 +
 .../obj/drivers/src/altera_avalon_timer_ts.d  |     31 +
 .../drivers/src/altera_avalon_timer_vars.d    |     21 +
 .../obj/drivers/src/altera_avalon_tse.d       |     84 +
 .../src/altera_avalon_tse_system_info.d       |     88 +
 .../obj/drivers/src/altera_avalon_uart_fd.d   |     58 +
 .../obj/drivers/src/altera_avalon_uart_init.d |     73 +
 .../drivers/src/altera_avalon_uart_ioctl.d    |     74 +
 .../obj/drivers/src/altera_avalon_uart_read.d |     74 +
 .../drivers/src/altera_avalon_uart_write.d    |     73 +
 .../src/altera_generic_quad_spi_controller.d  |     33 +
 .../obj/drivers/src/altera_msgdma.d           |     87 +
 .../obj/drivers/src/altera_onchip_flash.d     |     31 +
 .../obj/drivers/src/iniche/ins_tse_mac.d      |    162 +
 .../obj/iniche/src/allports/allports.d        |     86 +
 .../obj/iniche/src/allports/timeouts.d        |     64 +
 .../obj/iniche/src/allports/tk_misc.d         |     81 +
 .../obj/iniche/src/alt_iniche_close.d         |     78 +
 .../obj/iniche/src/alt_iniche_dev.d           |     80 +
 .../obj/iniche/src/alt_iniche_fcntl.d         |     78 +
 .../obj/iniche/src/alt_iniche_read.d          |     78 +
 .../obj/iniche/src/alt_iniche_write.d         |     78 +
 .../obj/iniche/src/autoip4/autoip.d           |     41 +
 .../hit_pat_bsp/obj/iniche/src/autoip4/upnp.d |     41 +
 .../obj/iniche/src/autoip4/upnpmenu.d         |     41 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpclnt.d  |     78 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpcport.d |     78 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpcprn.d  |     78 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpmenu.d  |     78 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpsport.d |    116 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpsrv.d   |     83 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpssock.d |     83 +
 .../hit_pat_bsp/obj/iniche/src/ftp/ftpsvfs.d  |     85 +
 .../hit_pat_bsp/obj/iniche/src/ip/et_arp.d    |     62 +
 .../hit_pat_bsp/obj/iniche/src/ip/icmp.d      |     59 +
 .../hit_pat_bsp/obj/iniche/src/ip/iface.d     |     88 +
 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip.d  |     61 +
 .../hit_pat_bsp/obj/iniche/src/ip/ip_reasm.d  |     41 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipdemux.d   |     62 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipmc.d      |     55 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipnet.d     |     59 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipport.d    |     55 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipraw.d     |     55 +
 .../hit_pat_bsp/obj/iniche/src/ip/iproute.d   |     55 +
 .../hit_pat_bsp/obj/iniche/src/ip/ipstart.d   |     64 +
 .../hit_pat_bsp/obj/iniche/src/ip/pmtu.d      |     41 +
 .../hit_pat_bsp/obj/iniche/src/ip/rtbtree.d   |     41 +
 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/udp.d |     87 +
 .../hit_pat_bsp/obj/iniche/src/ipmc/igmp.d    |     83 +
 .../hit_pat_bsp/obj/iniche/src/ipmc/igmp2.d   |     86 +
 .../obj/iniche/src/ipmc/igmp_cmn.d            |     86 +
 .../hit_pat_bsp/obj/iniche/src/ipmc/ipopt.d   |     78 +
 .../obj/iniche/src/ipmc/u_mctest.d            |     78 +
 .../obj/iniche/src/misclib/app_ping.d         |     41 +
 .../obj/iniche/src/misclib/bsdsock.d          |     83 +
 .../obj/iniche/src/misclib/cksum.d            |     41 +
 .../obj/iniche/src/misclib/cu_srv.d           |     41 +
 .../obj/iniche/src/misclib/dhcsetup.d         |     41 +
 .../obj/iniche/src/misclib/genlist.d          |     43 +
 .../obj/iniche/src/misclib/in_utils.d         |     71 +
 .../obj/iniche/src/misclib/iniche_log.d       |     41 +
 .../obj/iniche/src/misclib/iniche_qsort.d     |     41 +
 .../obj/iniche/src/misclib/localtime.d        |     41 +
 .../obj/iniche/src/misclib/memdev.d           |     43 +
 .../obj/iniche/src/misclib/memio.d            |     48 +
 .../obj/iniche/src/misclib/memwrap.d          |     48 +
 .../obj/iniche/src/misclib/menulib.d          |     73 +
 .../obj/iniche/src/misclib/menus.d            |     41 +
 .../obj/iniche/src/misclib/msring.d           |     73 +
 .../obj/iniche/src/misclib/netmain.d          |     81 +
 .../obj/iniche/src/misclib/nextcarg.d         |     45 +
 .../obj/iniche/src/misclib/nrmenus.d          |     41 +
 .../obj/iniche/src/misclib/nvfsio.d           |     41 +
 .../obj/iniche/src/misclib/nvparms.d          |     41 +
 .../obj/iniche/src/misclib/parseip.d          |     66 +
 .../obj/iniche/src/misclib/pcycles.d          |     41 +
 .../obj/iniche/src/misclib/profiler.d         |     41 +
 .../obj/iniche/src/misclib/rawiptst.d         |     41 +
 .../obj/iniche/src/misclib/reshost.d          |     57 +
 .../obj/iniche/src/misclib/rfsim.d            |     41 +
 .../obj/iniche/src/misclib/rttest.d           |     41 +
 .../obj/iniche/src/misclib/soperr.d           |     73 +
 .../obj/iniche/src/misclib/strilib.d          |     45 +
 .../obj/iniche/src/misclib/strlib.d           |     45 +
 .../obj/iniche/src/misclib/strtol.d           |     41 +
 .../obj/iniche/src/misclib/syslog.d           |     41 +
 .../hit_pat_bsp/obj/iniche/src/misclib/task.d |     41 +
 .../obj/iniche/src/misclib/tcp_echo.d         |     41 +
 .../obj/iniche/src/misclib/tcpcksum.d         |     78 +
 .../obj/iniche/src/misclib/testmenu.d         |     41 +
 .../obj/iniche/src/misclib/tk_crnos.d         |     81 +
 .../obj/iniche/src/misclib/ttyio.d            |     41 +
 .../obj/iniche/src/misclib/udp_echo.d         |     41 +
 .../obj/iniche/src/misclib/userpass.d         |     52 +
 .../hit_pat_bsp/obj/iniche/src/net/dhcpclnt.d |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/dhcputil.d |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/dnsclnt.d  |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/ifmap.d    |     57 +
 .../hit_pat_bsp/obj/iniche/src/net/macloop.d  |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/ping.d     |     57 +
 .../hit_pat_bsp/obj/iniche/src/net/pktalloc.d |     55 +
 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/q.d  |     43 +
 .../hit_pat_bsp/obj/iniche/src/net/slip.d     |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/slipif.d   |     41 +
 .../hit_pat_bsp/obj/iniche/src/net/udp_open.d |     57 +
 .../obj/iniche/src/nios2/asm_cksum.d          |      1 +
 .../obj/iniche/src/nios2/brdutils.d           |     43 +
 .../obj/iniche/src/nios2/osportco.d           |     85 +
 .../obj/iniche/src/nios2/targnios.d           |    122 +
 .../hit_pat_bsp/obj/iniche/src/tcp/in_pcb.d   |     78 +
 .../hit_pat_bsp/obj/iniche/src/tcp/nptcp.d    |    100 +
 .../hit_pat_bsp/obj/iniche/src/tcp/rawsock.d  |     87 +
 .../hit_pat_bsp/obj/iniche/src/tcp/sockcall.d |     90 +
 .../hit_pat_bsp/obj/iniche/src/tcp/socket.d   |     92 +
 .../hit_pat_bsp/obj/iniche/src/tcp/socket2.d  |     76 +
 .../hit_pat_bsp/obj/iniche/src/tcp/soselect.d |     78 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_in.d   |     93 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_menu.d |     41 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_out.d  |     95 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_subr.d |     95 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_timr.d |     95 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_usr.d  |     95 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcp_zio.d  |     41 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcpport.d  |     80 +
 .../hit_pat_bsp/obj/iniche/src/tcp/tcpsack.d  |     73 +
 .../hit_pat_bsp/obj/iniche/src/tcp/udpsock.d  |     87 +
 .../obj/iniche/src/telnet/telerr.d            |     88 +
 .../obj/iniche/src/telnet/telmenu.d           |     88 +
 .../obj/iniche/src/telnet/telnet.d            |     88 +
 .../obj/iniche/src/telnet/telparse.d          |     88 +
 .../obj/iniche/src/telnet/telport.d           |     88 +
 .../hit_pat_bsp/obj/iniche/src/tftp/tftpcli.d |     45 +
 .../obj/iniche/src/tftp/tftpmenu.d            |     69 +
 .../obj/iniche/src/tftp/tftpport.d            |     69 +
 .../hit_pat_bsp/obj/iniche/src/tftp/tftpsrv.d |     45 +
 .../hit_pat_bsp/obj/iniche/src/tftp/tftpudp.d |     64 +
 .../obj/iniche/src/tftp/tftputil.d            |     48 +
 .../hit_pat_bsp/obj/iniche/src/vfs/vfsfiles.d |     48 +
 .../hit_pat_bsp/obj/iniche/src/vfs/vfsport.d  |     50 +
 .../hit_pat_bsp/obj/iniche/src/vfs/vfssync.d  |     43 +
 .../hit_pat_bsp/obj/iniche/src/vfs/vfsutil.d  |     52 +
 FPGA_nios/hit_pat_bsp/public.mk               |    443 +
 FPGA_nios/hit_pat_bsp/settings.bsp            |   2001 +
 FPGA_nios/hit_pat_bsp/summary.html            |   4294 +
 FPGA_nios/hit_pat_bsp/system.h                |    822 +
 1453 files changed, 696209 insertions(+)
 create mode 100644 FPGA_firmware/.gitignore
 create mode 100644 FPGA_firmware/README.txt
 create mode 100644 FPGA_firmware/clkctrl.BAK.qsys
 create mode 100644 FPGA_firmware/clkctrl.qsys
 create mode 100644 FPGA_firmware/clkctrl.sopcinfo
 create mode 100644 FPGA_firmware/clkctrl/clkctrl.bsf
 create mode 100644 FPGA_firmware/clkctrl/clkctrl.csv
 create mode 100644 FPGA_firmware/clkctrl/clkctrl.spd
 create mode 100644 FPGA_firmware/clkctrl/clkctrl.xml
 create mode 100644 FPGA_firmware/clkctrl/synthesis/clkctrl.debuginfo
 create mode 100644 FPGA_firmware/clkctrl/synthesis/clkctrl.qip
 create mode 100644 FPGA_firmware/clkctrl/synthesis/clkctrl.v
 create mode 100644 FPGA_firmware/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
 create mode 100644 FPGA_firmware/debouncer.v
 create mode 100644 FPGA_firmware/debouncer_testbench.v
 create mode 100644 FPGA_firmware/debug.log
 create mode 100644 FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/devkit_simple_socket_server.qp_info
 create mode 100644 FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/filelist.txt
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio.xml
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.v
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio/altera_gpio_lite.sv
 create mode 100644 FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f
 create mode 100644 FPGA_firmware/filelist.txt
 create mode 100644 FPGA_firmware/hit20v3.qpf
 create mode 100644 FPGA_firmware/hit20v3.qsf
 create mode 100644 FPGA_firmware/hit20v3_assignment_defaults.qdf
 create mode 100644 FPGA_firmware/hit20v3_test.out.sdc
 create mode 100644 FPGA_firmware/m10_rgmii.out.sdc
 create mode 100644 FPGA_firmware/m10_rgmii.v
 create mode 100644 FPGA_firmware/output_file_sum.map
 create mode 100644 FPGA_firmware/output_files/.qsys_edit/filters.xml
 create mode 100644 FPGA_firmware/output_files/.qsys_edit/preferences.xml
 create mode 100644 FPGA_firmware/output_files/ChainFlash.cdf
 create mode 100644 FPGA_firmware/output_files/flash/ext_flash.pof
 create mode 100644 FPGA_firmware/output_files/flash/flash_loader.sof
 create mode 100644 FPGA_firmware/output_files/hit20v3.cdf
 create mode 100644 FPGA_firmware/output_files/hit20v3.pof
 create mode 100644 FPGA_firmware/output_files/hit20v3.sld
 create mode 100644 FPGA_firmware/output_files/hit20v3.sof
 create mode 100644 FPGA_firmware/output_files/hit20v3_bkgsub.pof
 create mode 100644 FPGA_firmware/output_files/hit20v3_time_limited.sof
 create mode 100644 FPGA_firmware/output_files/stp2.stp
 create mode 100644 FPGA_firmware/output_files/stp_clu.stp
 create mode 100644 FPGA_firmware/q_sys.BAK.qsys
 create mode 100644 FPGA_firmware/q_sys.qsys
 create mode 100644 FPGA_firmware/q_sys.sopcinfo
 create mode 100644 FPGA_firmware/q_sys/cali_ram.bsf
 create mode 100644 FPGA_firmware/q_sys/cali_ram.xml
 create mode 100644 FPGA_firmware/q_sys/cali_ram_bb.v
 create mode 100644 FPGA_firmware/q_sys/cali_ram_inst.v
 create mode 100644 FPGA_firmware/q_sys/q_sys.bsf
 create mode 100644 FPGA_firmware/q_sys/q_sys.csv
 create mode 100644 FPGA_firmware/q_sys/q_sys.spd
 create mode 100644 FPGA_firmware/q_sys/q_sys.xml
 create mode 100644 FPGA_firmware/q_sys/q_sys_bb.v
 create mode 100644 FPGA_firmware/q_sys/q_sys_inst.v
 create mode 100644 FPGA_firmware/q_sys/sensor_algo.bsf
 create mode 100644 FPGA_firmware/q_sys/sensor_algo.xml
 create mode 100644 FPGA_firmware/q_sys/sensor_algo_bb.v
 create mode 100644 FPGA_firmware/q_sys/sensor_algo_inst.v
 create mode 100644 FPGA_firmware/q_sys/st_splitter16.bsf
 create mode 100644 FPGA_firmware/q_sys/st_splitter16.xml
 create mode 100644 FPGA_firmware/q_sys/st_splitter16_bb.v
 create mode 100644 FPGA_firmware/q_sys/st_splitter16_inst.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/q_sys.debuginfo
 create mode 100644 FPGA_firmware/q_sys/synthesis/q_sys.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/q_sys.regmap
 create mode 100644 FPGA_firmware/q_sys/synthesis/q_sys.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/MM_to_ST_Adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/ST_to_MM_Adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_bkg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_interface.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_state.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_list.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_default_burst_converter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_dual_boot.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_gpio_lite.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_incr_burst_converter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_util.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_reset_synchronizer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altshifttaps.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_bin_cnt.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clk_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clock_crosser.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328checker.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328generator.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32galois8.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_false_path_marker.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gmii_io.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gray_cnt.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_hashing.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control_small.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lfsr_10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_loopback_ff.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_control.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_magic_detection.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_base.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map_small.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_module.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_register_map.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_1geth.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_gen_host.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_mdio.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/bkg.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/byte_enable_generator.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/cali_ram_cali_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/calibration.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/cluster_locate.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/csr_block.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/data_interface.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/descriptor_buffers.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/dispatcher.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/div.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/div.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/fifo_with_byteenables.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/frame_counter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/max10emif_dcfifo.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_altpll_shift.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_channel_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_button_pio.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cali_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_calibration_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.ocp
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_debug_uart.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_descriptor_memory.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_enet_pll.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_eth_tse.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_frame_timer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_glad.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_irq_mapper.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_jtag_uart.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_led_pio.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.hex
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_003.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_004.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_005.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_006.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_007.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_003.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_004.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_012.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_013.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_015.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_016.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_003.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_005.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_006.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_011.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_012.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_013.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_014.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_020.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_021.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_022.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_023.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_024.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_025.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_028.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_011.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_012.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_013.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_015.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_016.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_021.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_003.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_004.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_005.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_006.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_029.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_debug_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_onchip_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_output_pio.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_sysid.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_tse.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/ram4sig.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/ram4sig.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/read_burst_control.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/read_master.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/read_signal_breakout.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/response_block.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rms.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rom_bkg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot_avmm.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_bitcheck.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_core.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_broadcast.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_decoder.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_datamux.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ddr3.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_dm_decoder.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_generic.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_jumplogic.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr12.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr36.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr72.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram_csr.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_read_datapath.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/rw_manager_write_decoder.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_calibration.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_interface.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sensor_rms.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sequencer_m10.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sequencer_phy_mgr.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sequencer_pll_mgr.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/serial_rx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/serial_tx.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/soft_asmiblock.sv
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sqrt.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/sqrt.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/st2mm.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.qip
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/stl2sts.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/udp_generator.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/write_burst_control.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/write_master.v
 create mode 100644 FPGA_firmware/q_sys/synthesis/submodules/write_signal_breakout.v
 create mode 100644 FPGA_firmware/q_sys_bk.qsys
 create mode 100644 FPGA_firmware/q_sys_ddr3_ram_p0_summary.csv
 create mode 100644 FPGA_firmware/q_sys_mem_if_ddr3_emif_0_p0_summary.csv
 create mode 100644 FPGA_firmware/quartus.ini
 create mode 100644 FPGA_firmware/rgmii_sdc/rgmii_clocks.sdc
 create mode 100644 FPGA_firmware/rgmii_sdc/rgmii_input.sdc
 create mode 100644 FPGA_firmware/rgmii_sdc/rgmii_output.sdc
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram_schematic.nlv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/filters.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/preferences.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo_schematic.nlv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon_schematic.nlv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16_schematic.nlv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved_schematic.nlv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/algo_top.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/algo_top_cl.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali_rms.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/bkg_ram.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/bkg_subtraction.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/cali_ram.qsys
 create mode 100644 FPGA_firmware/sensor_algo_qsys/cali_ram.sopcinfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/calibration.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/cluster_locate.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/cluster_locate.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/data_caled_ram.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/data_caled_ram.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/data_caled_ram_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/data_caled_ram_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/div.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/div.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/div.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/div_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/frame_counter.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/greybox_tmp/cbx_args.txt
 create mode 100644 FPGA_firmware/sensor_algo_qsys/greybox_tmp/greybox_tmp/mgd3n.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.pof
 create mode 100644 FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sld
 create mode 100644 FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sof
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.debuginfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.debuginfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.debuginfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.debuginfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.sdc
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_synchronizer.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/div.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/frame_counter.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_calibration.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st2mm.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.debuginfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.bsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.xml
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram4bkg.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram4bkg.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram4bkg_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram4bkg_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram_sim.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram_sim.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram_sim_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/ram_sim_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/rms.sv
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_algo.sopcinfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_algo.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_algo_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qpf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qsf
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_interface.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sensor_recon.sopcinfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/serial_rx.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/serial_tx.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sqrt.qip
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sqrt.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sqrt_bb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sqrt_inst.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/st2mm.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/st_splitter16.qsys
 create mode 100644 FPGA_firmware/sensor_algo_qsys/st_splitter16.sopcinfo
 create mode 100644 FPGA_firmware/sensor_algo_qsys/stl2sts.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/sts2stl.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v
 create mode 100644 FPGA_firmware/sensor_algo_qsys/unsaved.qsys
 create mode 100644 FPGA_firmware/sensor_algo_qsys/unsaved.sopcinfo
 create mode 100644 FPGA_firmware/sensor_testbench.v
 create mode 100644 FPGA_firmware/serial_rx.v
 create mode 100644 FPGA_firmware/serial_testbench.v
 create mode 100644 FPGA_firmware/serial_tx.v
 create mode 100644 FPGA_firmware/tcl_readme.txt
 create mode 100644 FPGA_firmware/udp_generator.v
 create mode 100644 FPGA_firmware/udp_testbench.v
 create mode 100644 FPGA_nios/.gitignore
 create mode 100644 FPGA_nios/hit_pat/.force_relink
 create mode 100644 FPGA_nios/hit_pat/.project
 create mode 100644 FPGA_nios/hit_pat/create-this-app
 create mode 100644 FPGA_nios/hit_pat/hit_pat.elf
 create mode 100644 FPGA_nios/hit_pat/hit_pat.map
 create mode 100644 FPGA_nios/hit_pat/hit_pat.objdump
 create mode 100644 FPGA_nios/hit_pat/inc/control.h
 create mode 100644 FPGA_nios/hit_pat/inc/dev_commands.h
 create mode 100644 FPGA_nios/hit_pat/inc/network_utilities.h
 create mode 100644 FPGA_nios/hit_pat/inc/sensor.h
 create mode 100644 FPGA_nios/hit_pat/inc/socket_server.h
 create mode 100644 FPGA_nios/hit_pat/inc/udpgen.h
 create mode 100644 FPGA_nios/hit_pat/inc/utils.h
 create mode 100644 FPGA_nios/hit_pat/mem_init/ext_flash.hex
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.dat
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.dat
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.sym
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.dat
 create mode 100644 FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.sym
 create mode 100644 FPGA_nios/hit_pat/mem_init/meminit.qip
 create mode 100644 FPGA_nios/hit_pat/mem_init/meminit.spd
 create mode 100644 FPGA_nios/hit_pat/mem_init/onchip_flash.hex
 create mode 100644 FPGA_nios/hit_pat/mem_init/q_sys_calibration_ram.hex
 create mode 100644 FPGA_nios/hit_pat/mem_init/q_sys_descriptor_memory.hex
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/control.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/main.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/network_utilities.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/sensor.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/socket_server.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/tse_my_system.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/udpgen.d
 create mode 100644 FPGA_nios/hit_pat/obj/default/src/utils.d
 create mode 100644 FPGA_nios/hit_pat/onchip_flash.flash
 create mode 100644 FPGA_nios/hit_pat/readme.txt
 create mode 100644 FPGA_nios/hit_pat/src/control.c
 create mode 100644 FPGA_nios/hit_pat/src/main.c
 create mode 100644 FPGA_nios/hit_pat/src/network_utilities.c
 create mode 100644 FPGA_nios/hit_pat/src/sensor.c
 create mode 100644 FPGA_nios/hit_pat/src/socket_server.c
 create mode 100644 FPGA_nios/hit_pat/src/tse_my_system.c
 create mode 100644 FPGA_nios/hit_pat/src/udpgen.c
 create mode 100644 FPGA_nios/hit_pat/src/utils.c
 create mode 100644 FPGA_nios/hit_pat_bsp/.project
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/includes.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/io.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_close.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/crt0.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S
 create mode 100644 FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c
 create mode 100644 FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/alt_sys_init.c
 create mode 100644 FPGA_nios/hit_pat_bsp/create-this-bsp
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c
 create mode 100644 FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/icmp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ifmap.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/in_utils.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log_port.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/intimers.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ip.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ip6.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/libport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/mbuf.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/memwrap.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/menu.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/msring.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nameser.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/net.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/netbuf.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nios2/ipport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nptcp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nptypes.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ns.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ns_debug.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nvfsio.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/nvparms.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/pmtu.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/ppp_port.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/profiler.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/q.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/snmp_vie.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/snmpport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/sockcall.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/socket.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/socket6.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/sockvar.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/syslog.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/task.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/tcp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/tcpapp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/tcpport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/tk_crnos.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/tk_ntask.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/udp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/userpass.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/vfsfiles.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/h/webport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/et_arp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/icmp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/iface.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ip.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipdemux.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipmc.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipnet.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipraw.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/iproute.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/ipstart.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/pmtu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/rtbtree.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ip/udp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/ipopt.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/ipmc/u_mctest.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/app_ping.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/bsdsock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/cksum.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/cu_srv.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/dhcsetup.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/genlist.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/in_utils.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_log.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_qsort.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/localtime.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/memdev.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/memio.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/memwrap.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/menulib.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/menus.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/msring.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/netmain.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/nextcarg.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/nrmenus.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvfsio.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvparms.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/parseip.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/pcycles.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/profiler.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/rawiptst.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/reshost.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/rfsim.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/rttest.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/soperr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/strilib.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/strlib.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/strtol.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/syslog.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/task.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcp_echo.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcpcksum.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/testmenu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/tk_crnos.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/ttyio.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/udp_echo.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/misclib/userpass.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/dhcpclnt.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/dhcputil.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/dnsclnt.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/heapbuf.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/ifmap.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/macloop.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/ping.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/pktalloc.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/q.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/slip.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/slip.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/slipif.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/slipport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/net/udp_open.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/asm_cksum.S
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/brdutils.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/osport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/osportco.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/targnios.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/nios2/uart.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/nptcp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/protosw.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/rawsock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/sockcall.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket2.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/soselect.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_fsm.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_in.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_menu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_out.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_seq.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_subr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_usr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_var.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_zio.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpip.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpsack.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tcp/udpsock.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telerr.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telmenu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telparse.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftp.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpcli.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpmenu.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpsrv.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpudp.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftputil.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsfiles.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.h
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfssync.c
 create mode 100644 FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsutil.c
 create mode 100644 FPGA_nios/hit_pat_bsp/linker.h
 create mode 100644 FPGA_nios/hit_pat_bsp/linker.x
 create mode 100644 FPGA_nios/hit_pat_bsp/mem_init.mk
 create mode 100644 FPGA_nios/hit_pat_bsp/memory.gdb
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_alarm_start.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_busy_sleep.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_close.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_all.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev_llist_insert.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_rxchan_open.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_txchan_open.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_ctors.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_dtors.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_entry.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_exception.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_environ.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_errno.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_entry.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_muldiv.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_trap.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_execve.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exit.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fcntl.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_lock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_unlock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_dev.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_file.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_flash_dev.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fork.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fs_reg.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fstat.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_get_fd.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getchar.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getpid.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gettod.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gmon.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush_all.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic_isr_register.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_entry.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_register.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_io_redirect.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ioctl.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_entry.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_handler.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_register.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_vars.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_isatty.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_kill.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_link.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_load.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_macro.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_printf.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_lseek.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_main.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_mcount.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_open.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_printf.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putchar.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putcharbuf.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putstr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_read.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_release_fd.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_cached.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_uncached.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_rename.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_sbrk.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_settod.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_software_exception.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_stat.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_tick.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_times.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_free.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_malloc.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_unlink.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_usleep.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_wait.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_write.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/altera_nios2_gen2_irq.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/crt0.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_a.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_c.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_env_lock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_malloc_lock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_core.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_dbg.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_flag.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mbox.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mem.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mutex.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_q.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_sem.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_task.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_time.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_tmr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/alt_sys_init.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_sc.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_ts.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_vars.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse_system_info.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_fd.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_init.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_read.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_write.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_generic_quad_spi_controller.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_msgdma.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_onchip_flash.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/drivers/src/iniche/ins_tse_mac.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/allports.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/timeouts.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/tk_misc.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_close.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_dev.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_fcntl.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_read.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_write.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/autoip.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnpmenu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpclnt.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcprn.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpmenu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsrv.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpssock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsvfs.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/et_arp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/icmp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iface.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip_reasm.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipdemux.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipmc.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipnet.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipraw.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iproute.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipstart.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/pmtu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/rtbtree.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/udp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp2.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp_cmn.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/ipopt.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/u_mctest.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/app_ping.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/bsdsock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cksum.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cu_srv.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/dhcsetup.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/genlist.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/in_utils.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_log.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_qsort.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/localtime.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memdev.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memio.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memwrap.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menulib.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menus.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/msring.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/netmain.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nextcarg.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nrmenus.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvfsio.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvparms.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/parseip.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/pcycles.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/profiler.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rawiptst.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/reshost.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rfsim.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rttest.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/soperr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strilib.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strlib.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strtol.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/syslog.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/task.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcp_echo.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcpcksum.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/testmenu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tk_crnos.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/ttyio.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/udp_echo.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/userpass.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcpclnt.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcputil.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dnsclnt.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ifmap.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/macloop.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ping.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/pktalloc.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/q.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slip.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slipif.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/net/udp_open.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/asm_cksum.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/brdutils.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/osportco.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/targnios.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/in_pcb.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/nptcp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/rawsock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/sockcall.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket2.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/soselect.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_in.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_menu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_out.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_subr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_timr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_usr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_zio.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpsack.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/udpsock.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telerr.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telmenu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telnet.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telparse.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpcli.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpmenu.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpsrv.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpudp.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftputil.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsfiles.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsport.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfssync.d
 create mode 100644 FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsutil.d
 create mode 100644 FPGA_nios/hit_pat_bsp/public.mk
 create mode 100644 FPGA_nios/hit_pat_bsp/settings.bsp
 create mode 100644 FPGA_nios/hit_pat_bsp/summary.html
 create mode 100644 FPGA_nios/hit_pat_bsp/system.h

diff --git a/FPGA_firmware/.gitignore b/FPGA_firmware/.gitignore
new file mode 100644
index 0000000..c60f61b
--- /dev/null
+++ b/FPGA_firmware/.gitignore
@@ -0,0 +1,72 @@
+# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
+# but if you follow some rules it can be accomplished. :)
+# This file should be placed into the main directory where the .qpf file is
+# found. Generally Q2 throws all entities and so on in the main directory, but
+# you can place all stuff also in separate folders. This approach is followed
+# here. So when you create a new design create one or more folders where your
+# entities will be located and put a .gitignore in there that overrides the
+# ignores of this file, e.g. one single rule stating "!*" which allows now all
+# type of files. When you add a MegaFunction or another entity to your design,
+# simply add it to one of your private folders and Q2 will be happy and manage
+# everything quite good. When you want to do versioning of your generated
+# SOF/POF files, you can do this by redirecting the generated output to an own
+# folder. To do this go to:
+# "Assignments"
+# -> "Settings
+# -> "Compilation Process Settings"
+# -> "Save project output files in specified directory"
+# Now you can either place a .gitignore in the directory and allow the following
+# list of types:
+!*.sof
+!*.pof
+# or you create an own submodule in the folder to keep binary files out of your
+# design.
+
+# Need to keep all HDL files
+!*.vhd
+!*.v
+!*.sv
+
+# ignore Quartus II generated files
+*_generation_script*
+*_inst.vhd
+*.bak
+*.cmp
+*.done
+*.eqn
+#*.hex
+*.html
+*.jdi
+*.jpg
+# *.mif
+*.pin
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+#*.sopc_builder
+*.summary
+*.tcl
+*.txt # Explicitly add any text files used
+*~
+*example*
+# *sopc_*
+# *.sdc # I want those timing files
+
+# ignore Quartus II generated folders
+*/db/
+*/incremental_db/
+*/simulation/
+**/simulation/
+*/timing/
+software/
+*.o
+*.d
+#*/testbench/
+*/*_sim/
+incremental_db/
+db/
+_output_files/
+PLLJ_PLLSPE_INFO.txt
diff --git a/FPGA_firmware/README.txt b/FPGA_firmware/README.txt
new file mode 100644
index 0000000..1fdf76e
--- /dev/null
+++ b/FPGA_firmware/README.txt
@@ -0,0 +1,2 @@
+The Firmware is developed from: 
+http://www.alterawiki.com/uploads/7/71/Simple_Socket_Ethernet_guide.pdf
diff --git a/FPGA_firmware/clkctrl.BAK.qsys b/FPGA_firmware/clkctrl.BAK.qsys
new file mode 100644
index 0000000..905c31d
--- /dev/null
+++ b/FPGA_firmware/clkctrl.BAK.qsys
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altclkctrl_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="m10_rgmii.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altclkctrl_input"
+   internal="altclkctrl_0.altclkctrl_input"
+   type="conduit"
+   dir="end">
+  <port name="inclk" internal="inclk" />
+ </interface>
+ <interface
+   name="altclkctrl_output"
+   internal="altclkctrl_0.altclkctrl_output"
+   type="conduit"
+   dir="end">
+  <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="18.0"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CLOCK_TYPE" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="NUMBER_OF_CLOCKS" value="1" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/FPGA_firmware/clkctrl.qsys b/FPGA_firmware/clkctrl.qsys
new file mode 100644
index 0000000..aaf67e1
--- /dev/null
+++ b/FPGA_firmware/clkctrl.qsys
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altclkctrl_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="m10_rgmii.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altclkctrl_input"
+   internal="altclkctrl_0.altclkctrl_input"
+   type="conduit"
+   dir="end">
+  <port name="inclk" internal="inclk" />
+ </interface>
+ <interface
+   name="altclkctrl_output"
+   internal="altclkctrl_0.altclkctrl_output"
+   type="conduit"
+   dir="end">
+  <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="19.1"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CLOCK_TYPE" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="NUMBER_OF_CLOCKS" value="1" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/FPGA_firmware/clkctrl.sopcinfo b/FPGA_firmware/clkctrl.sopcinfo
new file mode 100644
index 0000000..d8e435a
--- /dev/null
+++ b/FPGA_firmware/clkctrl.sopcinfo
@@ -0,0 +1,257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="clkctrl" kind="clkctrl" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2023.06.07.19:47:52 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1686160072</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="19.1"
+   path="altclkctrl_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="CLOCK_TYPE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUMBER_OF_CLOCKS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENA_REGISTER_MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GUI_USE_ENA">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="altclkctrl_input" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>input</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>inclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk</role>
+   </port>
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>output</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>outclk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>outclk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altclkctrl</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/clkctrl/clkctrl.bsf b/FPGA_firmware/clkctrl/clkctrl.bsf
new file mode 100644
index 0000000..0eeceef
--- /dev/null
+++ b/FPGA_firmware/clkctrl/clkctrl.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 272 104)
+	(text "clkctrl" (rect 119 -1 141 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 88 20 100)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk" (rect 0 0 16 12)(font "Arial" (font_size 8)))
+		(text "inclk" (rect 4 61 34 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 96 72)(line_width 1))
+	)
+	(port
+		(pt 272 72)
+		(output)
+		(text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "outclk" (rect 242 61 278 72)(font "Arial" (font_size 8)))
+		(line (pt 272 72)(pt 160 72)(line_width 1))
+	)
+	(drawing
+		(text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "inclk" (rect 101 67 232 144)(font "Arial" (color 0 0 0)))
+		(text "altclkctrl_output" (rect 161 43 424 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "outclk" (rect 132 67 300 144)(font "Arial" (color 0 0 0)))
+		(text " clkctrl " (rect 243 88 540 186)(font "Arial" ))
+		(line (pt 96 32)(pt 160 32)(line_width 1))
+		(line (pt 160 32)(pt 160 88)(line_width 1))
+		(line (pt 96 88)(pt 160 88)(line_width 1))
+		(line (pt 96 32)(pt 96 88)(line_width 1))
+		(line (pt 97 52)(pt 97 76)(line_width 1))
+		(line (pt 98 52)(pt 98 76)(line_width 1))
+		(line (pt 159 52)(pt 159 76)(line_width 1))
+		(line (pt 158 52)(pt 158 76)(line_width 1))
+		(line (pt 0 0)(pt 272 0)(line_width 1))
+		(line (pt 272 0)(pt 272 104)(line_width 1))
+		(line (pt 0 104)(pt 272 104)(line_width 1))
+		(line (pt 0 0)(pt 0 104)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/clkctrl/clkctrl.csv b/FPGA_firmware/clkctrl/clkctrl.csv
new file mode 100644
index 0000000..4c23a66
--- /dev/null
+++ b/FPGA_firmware/clkctrl/clkctrl.csv
@@ -0,0 +1,18 @@
+# system info clkctrl on 2023.06.07.19:47:50
+system_info:
+name,value
+DEVICE,10M50DAF484C6GES
+DEVICE_FAMILY,MAX 10
+GENERATION_ID,1686160070
+#
+#
+# Files generated for clkctrl on 2023.06.07.19:47:50
+files:
+filepath,kind,attributes,module,is_top
+simulation/clkctrl.v,VERILOG,,clkctrl,true
+simulation/submodules/clkctrl_altclkctrl_0.v,VERILOG,,clkctrl_altclkctrl_0,false
+#
+# Map from instance-path to kind of module
+instances:
+instancePath,module
+clkctrl.altclkctrl_0,clkctrl_altclkctrl_0
diff --git a/FPGA_firmware/clkctrl/clkctrl.spd b/FPGA_firmware/clkctrl/clkctrl.spd
new file mode 100644
index 0000000..01b6c1a
--- /dev/null
+++ b/FPGA_firmware/clkctrl/clkctrl.spd
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="simulation/submodules/clkctrl_altclkctrl_0.v"
+   type="VERILOG"
+   library="altclkctrl_0" />
+ <file path="simulation/clkctrl.v" type="VERILOG" />
+ <topLevel name="clkctrl" />
+ <deviceFamily name="max10" />
+</simPackage>
diff --git a/FPGA_firmware/clkctrl/clkctrl.xml b/FPGA_firmware/clkctrl/clkctrl.xml
new file mode 100644
index 0000000..9a1a1a1
--- /dev/null
+++ b/FPGA_firmware/clkctrl/clkctrl.xml
@@ -0,0 +1,131 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2023.06.07.19:47:52"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="altclkctrl_input" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="inclk" direction="input" role="inclk" width="1" />
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="outclk" direction="output" role="outclk" width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="clkctrl:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1686160072,AUTO_UNIQUE_ID=(altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
+   instancePathKey="clkctrl"
+   kind="clkctrl"
+   version="1.0"
+   name="clkctrl">
+  <parameter name="AUTO_GENERATION_ID" value="1686160072" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/clkctrl.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="clkctrl">queue size: 0 starting:clkctrl "clkctrl"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="clkctrl"><![CDATA["<b>clkctrl</b>" reuses <b>altclkctrl</b> "<b>submodules/clkctrl_altclkctrl_0</b>"]]></message>
+   <message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
+   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
+   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
+   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
+   instancePathKey="clkctrl:.:altclkctrl_0"
+   kind="altclkctrl"
+   version="19.1"
+   name="clkctrl_altclkctrl_0">
+  <parameter name="NUMBER_OF_CLOCKS" value="1" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="CLOCK_TYPE" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="clkctrl" as="altclkctrl_0" />
+  <messages>
+   <message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
+   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
+   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
+   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/clkctrl/synthesis/clkctrl.debuginfo b/FPGA_firmware/clkctrl/synthesis/clkctrl.debuginfo
new file mode 100644
index 0000000..a148b89
--- /dev/null
+++ b/FPGA_firmware/clkctrl/synthesis/clkctrl.debuginfo
@@ -0,0 +1,339 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="clkctrl" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2023.06.07.19:47:52 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1686160072</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>true</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value>m10_rgmii.qpf</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="19.1"
+   path="altclkctrl_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="CLOCK_TYPE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUMBER_OF_CLOCKS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENA_REGISTER_MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GUI_USE_ENA">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="altclkctrl_input" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>input</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>inclk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk</role>
+   </port>
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>output</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>outclk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>outclk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altclkctrl</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>02424A4180BE0000018896F8DFE3</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/clkctrl/synthesis/clkctrl.qip b/FPGA_firmware/clkctrl/synthesis/clkctrl.qip
new file mode 100644
index 0000000..f7b4116
--- /dev/null
+++ b/FPGA_firmware/clkctrl/synthesis/clkctrl.qip
@@ -0,0 +1,39 @@
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "clkctrl" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../clkctrl.sopcinfo"]
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name SLD_INFO "QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"
+set_global_assignment -library "clkctrl" -name MISC_FILE [file join $::quartus(qip_path) "../clkctrl.cmp"]
+set_global_assignment -library "clkctrl" -name SLD_FILE [file join $::quartus(qip_path) "clkctrl.debuginfo"]
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_QSYS_MODE "STANDALONE"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "clkctrl" -name MISC_FILE [file join $::quartus(qip_path) "../../clkctrl.qsys"]
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_NAME "Y2xrY3RybA=="
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_DISPLAY_NAME "Y2xrY3RybA=="
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY4NjE2MDA3Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_NAME "Y2xrY3RybF9hbHRjbGtjdHJsXzA="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ"
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
+
+set_global_assignment -library "clkctrl" -name VERILOG_FILE [file join $::quartus(qip_path) "clkctrl.v"]
+set_global_assignment -library "clkctrl" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clkctrl_altclkctrl_0.v"]
+
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_NAME "altclkctrl"
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_ENV "Qsys"
diff --git a/FPGA_firmware/clkctrl/synthesis/clkctrl.v b/FPGA_firmware/clkctrl/synthesis/clkctrl.v
new file mode 100644
index 0000000..fb5218a
--- /dev/null
+++ b/FPGA_firmware/clkctrl/synthesis/clkctrl.v
@@ -0,0 +1,16 @@
+// clkctrl.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module clkctrl (
+		input  wire  inclk,  //  altclkctrl_input.inclk
+		output wire  outclk  // altclkctrl_output.outclk
+	);
+
+	clkctrl_altclkctrl_0 altclkctrl_0 (
+		.inclk  (inclk),  //  altclkctrl_input.inclk
+		.outclk (outclk)  // altclkctrl_output.outclk
+	);
+
+endmodule
diff --git a/FPGA_firmware/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v b/FPGA_firmware/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
new file mode 100644
index 0000000..efa02fd
--- /dev/null
+++ b/FPGA_firmware/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
@@ -0,0 +1,115 @@
+//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="MAX 10" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
+//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = clkctrl 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  clkctrl_altclkctrl_0_sub
+	( 
+	ena,
+	inclk,
+	outclk) /* synthesis synthesis_clearbox=1 */;
+	input   ena;
+	input   [3:0]  inclk;
+	output   outclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1   ena;
+	tri0   [3:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  wire_clkctrl1_outclk;
+	wire [1:0]  clkselect;
+	wire  [1:0]  clkselect_wire;
+	wire  [3:0]  inclk_wire;
+
+	fiftyfivenm_clkctrl   clkctrl1
+	( 
+	.clkselect(clkselect_wire),
+	.ena(ena),
+	.inclk(inclk_wire),
+	.outclk(wire_clkctrl1_outclk)
+	// synopsys translate_off
+	,
+	.devclrn(1'b1),
+	.devpor(1'b1)
+	// synopsys translate_on
+	);
+	defparam
+		clkctrl1.clock_type = "Global Clock",
+		clkctrl1.ena_register_mode = "falling edge",
+		clkctrl1.lpm_type = "fiftyfivenm_clkctrl";
+	assign
+		clkselect = {2{1'b0}},
+		clkselect_wire = {clkselect},
+		inclk_wire = {inclk},
+		outclk = wire_clkctrl1_outclk;
+endmodule //clkctrl_altclkctrl_0_sub
+//VALID FILE // (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module  clkctrl_altclkctrl_0  (
+    inclk,
+    outclk);
+
+    input    inclk;
+    output   outclk;
+
+    wire  sub_wire0;
+    wire  outclk;
+    wire  sub_wire1;
+    wire  sub_wire2;
+    wire [3:0] sub_wire3;
+    wire [2:0] sub_wire4;
+
+    assign  outclk = sub_wire0;
+    assign  sub_wire1 = 1'h1;
+    assign  sub_wire2 = inclk;
+    assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
+    assign sub_wire4[2:0] = 3'h0;
+
+    clkctrl_altclkctrl_0_sub  clkctrl_altclkctrl_0_sub_component (
+                .ena (sub_wire1),
+                .inclk (sub_wire3),
+                .outclk (sub_wire0));
+
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/debouncer.v b/FPGA_firmware/debouncer.v
new file mode 100644
index 0000000..dca59e6
--- /dev/null
+++ b/FPGA_firmware/debouncer.v
@@ -0,0 +1,57 @@
+// Signal debouncer
+
+`timescale 100 ps / 100 ps
+module debouncer (
+		input	wire		rst,		//reset
+		input	wire       	clk,        //clock
+		input 	wire		in,			//signal input
+		output	wire   		out			//signal output
+	);
+
+	parameter LENGTH=8;
+	
+	integer i;
+
+	reg	[LENGTH-1:0]	queue;		//State of the state machine
+	reg 				reg_out;
+	wire 				all_low;
+	wire 				all_high;
+	
+		//Little helpers
+	assign all_low = ~(|queue);
+	assign all_high = &queue;
+	
+	
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			queue[LENGTH-1:0] <= 0;		
+			reg_out <= 0;
+		end
+		else
+		begin
+			queue[LENGTH-2:0] <= queue[LENGTH-1:1];	
+			queue[LENGTH-1] <= in;
+			
+				//change the output state only if all the queue has a correct state
+			case (reg_out)
+				0:
+				begin
+					if (all_high)
+						reg_out <= 1;
+				end
+				1:
+				begin
+					if (all_low)
+						reg_out <= 0;
+				end
+			endcase
+		end
+	end
+	
+		//Assign output
+	assign out = reg_out;
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/debouncer_testbench.v b/FPGA_firmware/debouncer_testbench.v
new file mode 100644
index 0000000..70f5ab7
--- /dev/null
+++ b/FPGA_firmware/debouncer_testbench.v
@@ -0,0 +1,90 @@
+//This is a testbench from the UDP generator
+
+
+`timescale 1 ns / 1 ns
+module debouncer_testbench();
+
+
+//Signals
+
+	reg         clk;               
+	reg         rst;                
+	reg  	    in;          
+	wire        out; 
+
+initial
+begin
+	clk 		= 0;
+	rst 		= 1;
+	in			= 0;
+
+	#50 
+	rst 		= 0;
+
+	#20
+	in 	= 1;
+	#20
+	in 	= 0;
+
+	#200
+	in 	= 1;
+	#200
+	in 	= 0;
+
+	#100
+	in 	= 1;
+	#100
+	in 	= 0;
+
+	#20
+	in 	= 1;
+	#200
+	in 	= 0;
+
+	#20
+	in 	= 1;
+	#20
+	in 	= 0;
+
+	#20
+	in 	= 1;
+	#20
+	in 	= 0;
+
+	#20
+	in 	= 1;
+	#20
+	in 	= 0;
+
+	#20
+	in 	= 1;
+	#20
+	in 	= 0;
+
+	#1000
+	in 	= 1;
+	#500
+	in 	= 0;	
+	
+	#20000
+	$stop;
+
+end
+
+always #5 clk = ~clk;
+
+
+debouncer #(
+	.LENGTH	(25)
+) the_debouncer(
+	.clk	(clk),                	
+	.rst	(rst),              	
+	.in		(in),            	
+	.out	(out)        
+	);	
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/debug.log b/FPGA_firmware/debug.log
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/devkit_simple_socket_server.qp_info b/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/devkit_simple_socket_server.qp_info
new file mode 100644
index 0000000..854e63e
--- /dev/null
+++ b/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/devkit_simple_socket_server.qp_info
@@ -0,0 +1,2 @@
+<platform><name>Nios II Simple Socket Server Ethernet Example</name><category>Design Example</category><version>1.0</version><acds_version>17.1std.1</acds_version><board>MAX 10 FPGA Development Kit</board><family>MAX 10</family><device>10M50DA</device><part>10M50DAF256C7G</part><vendor>Altera</vendor><description>This design example demonstrates communication with a telnet client on a development host PC. The telnet client offers a convenient way of issuing
+commands over a TCP/IP socket to the Ethernet-connected NicheStack TCP/IP Stackrunning on the Altera development board with a simple TCP/IP socket server example. The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.</description><documentation><title>Nios II Simple Socket Server Ethernet Guide</title><url>http://www.alterawiki.com/uploads/e/e5/Simple_Socket_Ethernet.pdf</url></documentation><documentation><title>Using the NicheStack TCP/IP Stack - Nios II Tutorial</title><url>https://www.altera.com/en_US/pdfs/literature/tt/tt_nios2_tcpip.pdf</url></documentation></platform>
\ No newline at end of file
diff --git a/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/filelist.txt b/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/filelist.txt
new file mode 100644
index 0000000..00ab0e8
--- /dev/null
+++ b/FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/filelist.txt
@@ -0,0 +1,2 @@
+devkit_simple_socket_server.qp_info
+devkit_simple_socket_server.qar
\ No newline at end of file
diff --git a/FPGA_firmware/enet_gtx_clk_ddio.xml b/FPGA_firmware/enet_gtx_clk_ddio.xml
new file mode 100644
index 0000000..606ec20
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<instance entity-name="altera_gpio_lite" version="18.0" >
+<generic name="DEVICE_FAMILY" value="MAX 10" />
+<generic name="PIN_TYPE" value="output" />
+<generic name="SIZE" value="1" />
+<generic name="gui_true_diff_buf" value="false" />
+<generic name="gui_pseudo_diff_buf" value="false" />
+<generic name="gui_bus_hold" value="false" />
+<generic name="gui_open_drain" value="false" />
+<generic name="gui_enable_oe_port" value="false" />
+<generic name="gui_enable_nsleep_port" value="false" />
+<generic name="gui_io_reg_mode" value="ddr" />
+<generic name="gui_enable_aclr_port" value="true" />
+<generic name="gui_enable_aset_port" value="false" />
+<generic name="gui_enable_sclr_port" value="false" />
+<generic name="gui_set_registers_to_power_up_high" value="false" />
+<generic name="gui_clock_enable" value="false" />
+<generic name="gui_invert_output" value="false" />
+<generic name="gui_invert_input_clock" value="false" />
+<generic name="gui_use_register_to_drive_obuf_oe" value="false" />
+<generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
+<generic name="gui_use_advanced_ddr_features" value="false" />
+<generic name="gui_enable_phase_detector_for_ck" value="false" />
+<generic name="gui_enable_oe_half_cycle_delay" value="true" />
+<generic name="gui_enable_hr_clock" value="false" />
+<generic name="gui_enable_invert_hr_clock_port" value="false" />
+<generic name="gui_invert_clkdiv_input_clock" value="false" />
+<generic name="gui_invert_output_clock" value="false" />
+<generic name="gui_invert_oe_inclock" value="false" />
+<generic name="gui_use_hardened_ddio_input_registers" value="false" />
+</instance>
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf
new file mode 100644
index 0000000..06065c3
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 208 184)
+	(text "enet_gtx_clk_ddio" (rect 51 -1 122 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "outclock" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 61 52 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "din[1..0]" (rect 0 0 29 12)(font "Arial" (font_size 8)))
+		(text "din[1..0]" (rect 4 101 58 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 64 112)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "aclr" (rect 0 0 14 12)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 4 141 28 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 64 152)(line_width 1))
+	)
+	(port
+		(pt 208 72)
+		(output)
+		(text "pad_out" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "pad_out" (rect 166 61 208 72)(font "Arial" (font_size 8)))
+		(line (pt 208 72)(pt 144 72)(line_width 1))
+	)
+	(drawing
+		(text "outclock" (rect 18 43 84 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 67 174 144)(font "Arial" (color 0 0 0)))
+		(text "din" (rect 48 83 114 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 107 174 224)(font "Arial" (color 0 0 0)))
+		(text "pad_out" (rect 145 43 332 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 114 67 264 144)(font "Arial" (color 0 0 0)))
+		(text "aclr" (rect 44 123 112 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 147 174 304)(font "Arial" (color 0 0 0)))
+		(text " altera_gpio_lite " (rect 140 168 388 346)(font "Arial" ))
+		(line (pt 64 32)(pt 144 32)(line_width 1))
+		(line (pt 144 32)(pt 144 168)(line_width 1))
+		(line (pt 64 168)(pt 144 168)(line_width 1))
+		(line (pt 64 32)(pt 64 168)(line_width 1))
+		(line (pt 65 52)(pt 65 76)(line_width 1))
+		(line (pt 66 52)(pt 66 76)(line_width 1))
+		(line (pt 65 92)(pt 65 116)(line_width 1))
+		(line (pt 66 92)(pt 66 116)(line_width 1))
+		(line (pt 143 52)(pt 143 76)(line_width 1))
+		(line (pt 142 52)(pt 142 76)(line_width 1))
+		(line (pt 65 132)(pt 65 156)(line_width 1))
+		(line (pt 66 132)(pt 66 156)(line_width 1))
+		(line (pt 0 0)(pt 208 0)(line_width 1))
+		(line (pt 208 0)(pt 208 184)(line_width 1))
+		(line (pt 0 184)(pt 208 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
new file mode 100644
index 0000000..2c8f2fc
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
@@ -0,0 +1,74 @@
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio.cmp"]
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_NAME "ZW5ldF9ndHhfY2xrX2RkaW8="
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::dHJ1ZQ==::RW5hYmxlIGFjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::Y2xlYXI=::QVNZTkNfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
+
+set_global_assignment -library "enet_gtx_clk_ddio" -name VERILOG_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio.v"]
+set_global_assignment -library "enet_gtx_clk_ddio" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio/altera_gpio_lite.sv"]
+
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip
new file mode 100644
index 0000000..241b239
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip
@@ -0,0 +1,7 @@
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_enet_gtx_clk_ddio" -name SPD_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio.spd"]
+
+set_global_assignment -library "lib_enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v"]
+set_global_assignment -library "lib_enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv"]
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd
new file mode 100644
index 0000000..4967f5a
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG"
+   library="enet_gtx_clk_ddio" />
+ <file path="enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v" type="VERILOG" />
+ <topLevel name="enet_gtx_clk_ddio" />
+ <deviceFamily name="max10" />
+</simPackage>
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.v b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.v
new file mode 100644
index 0000000..57dac25
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.v
@@ -0,0 +1,124 @@
+// megafunction wizard: %GPIO Lite Intel FPGA IP v19.1%
+// GENERATION: XML
+// enet_gtx_clk_ddio.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module enet_gtx_clk_ddio (
+		input  wire       outclock, // outclock.export
+		input  wire [1:0] din,      //      din.export
+		output wire [0:0] pad_out,  //  pad_out.export
+		input  wire       aclr      //     aclr.export
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("output"),
+		.SIZE                                     (1),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("clear"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) enet_gtx_clk_ddio_inst (
+		.outclock        (outclock), // outclock.export
+		.din             (din),      //      din.export
+		.pad_out         (pad_out),  //  pad_out.export
+		.aclr            (aclr),     //     aclr.export
+		.outclocken      (1'b1),     // (terminated)
+		.inclock         (1'b0),     // (terminated)
+		.inclocken       (1'b0),     // (terminated)
+		.fr_clock        (),         // (terminated)
+		.hr_clock        (),         // (terminated)
+		.invert_hr_clock (1'b0),     // (terminated)
+		.phy_mem_clock   (1'b0),     // (terminated)
+		.mimic_clock     (),         // (terminated)
+		.dout            (),         // (terminated)
+		.pad_io          (),         // (terminated)
+		.pad_io_b        (),         // (terminated)
+		.pad_in          (1'b0),     // (terminated)
+		.pad_in_b        (1'b0),     // (terminated)
+		.pad_out_b       (),         // (terminated)
+		.aset            (1'b0),     // (terminated)
+		.sclr            (1'b0),     // (terminated)
+		.nsleep          (1'b0),     // (terminated)
+		.oe              (1'b0)      // (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2023 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_gpio_lite" version="19.1" >
+// Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
+// Retrieval info: 	<generic name="PIN_TYPE" value="output" />
+// Retrieval info: 	<generic name="SIZE" value="1" />
+// Retrieval info: 	<generic name="gui_true_diff_buf" value="false" />
+// Retrieval info: 	<generic name="gui_pseudo_diff_buf" value="false" />
+// Retrieval info: 	<generic name="gui_bus_hold" value="false" />
+// Retrieval info: 	<generic name="gui_open_drain" value="false" />
+// Retrieval info: 	<generic name="gui_enable_oe_port" value="false" />
+// Retrieval info: 	<generic name="gui_enable_nsleep_port" value="false" />
+// Retrieval info: 	<generic name="gui_io_reg_mode" value="ddr" />
+// Retrieval info: 	<generic name="gui_enable_aclr_port" value="true" />
+// Retrieval info: 	<generic name="gui_enable_aset_port" value="false" />
+// Retrieval info: 	<generic name="gui_enable_sclr_port" value="false" />
+// Retrieval info: 	<generic name="gui_set_registers_to_power_up_high" value="false" />
+// Retrieval info: 	<generic name="gui_clock_enable" value="false" />
+// Retrieval info: 	<generic name="gui_invert_output" value="false" />
+// Retrieval info: 	<generic name="gui_invert_input_clock" value="false" />
+// Retrieval info: 	<generic name="gui_use_register_to_drive_obuf_oe" value="false" />
+// Retrieval info: 	<generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
+// Retrieval info: 	<generic name="gui_use_advanced_ddr_features" value="false" />
+// Retrieval info: 	<generic name="gui_enable_phase_detector_for_ck" value="false" />
+// Retrieval info: 	<generic name="gui_enable_oe_half_cycle_delay" value="true" />
+// Retrieval info: 	<generic name="gui_enable_hr_clock" value="false" />
+// Retrieval info: 	<generic name="gui_enable_invert_hr_clock_port" value="false" />
+// Retrieval info: 	<generic name="gui_invert_clkdiv_input_clock" value="false" />
+// Retrieval info: 	<generic name="gui_invert_output_clock" value="false" />
+// Retrieval info: 	<generic name="gui_invert_oe_inclock" value="false" />
+// Retrieval info: 	<generic name="gui_use_hardened_ddio_input_registers" value="false" />
+// Retrieval info: </instance>
+// IPFS_FILES : enet_gtx_clk_ddio.vo
+// RELATED_FILES: enet_gtx_clk_ddio.v, altera_gpio_lite.sv
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio/altera_gpio_lite.sv b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio/altera_gpio_lite.sv
new file mode 100644
index 0000000..e3fde01
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio/altera_gpio_lite.sv
@@ -0,0 +1,1200 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f
new file mode 100644
index 0000000..3cab828
--- /dev/null
+++ b/FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f
@@ -0,0 +1,2 @@
+enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v
+enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv
diff --git a/FPGA_firmware/filelist.txt b/FPGA_firmware/filelist.txt
new file mode 100644
index 0000000..59be493
--- /dev/null
+++ b/FPGA_firmware/filelist.txt
@@ -0,0 +1,2887 @@
+platform_setup.tcl
+filelist.txt
+top.qpf
+
+platform/clkctrl/simulation/clkctrl.v
+platform/clkctrl/simulation/submodules/clkctrl_altclkctrl_0.v
+platform/clkctrl/simulation/clkctrl.sip
+platform/clkctrl/simulation/clkctrl.spd
+platform/clkctrl/synthesis/clkctrl.v
+platform/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
+platform/clkctrl/synthesis/clkctrl.qip
+platform/clkctrl/clkctrl.sopcinfo
+platform/q_sys/simulation/q_sys.v
+platform/q_sys/simulation/submodules/q_sys_altpll_shift.vo
+platform/q_sys/simulation/submodules/q_sys_cpu.v
+platform/q_sys/simulation/submodules/q_sys_descriptor_memory.v
+platform/q_sys/simulation/submodules/mentor/altera_dual_boot.v
+platform/q_sys/simulation/submodules/mentor/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/mentor/alt_dual_boot.v
+platform/q_sys/simulation/submodules/aldec/altera_dual_boot.v
+platform/q_sys/simulation/submodules/aldec/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/aldec/alt_dual_boot.v
+platform/q_sys/simulation/submodules/cadence/altera_dual_boot.v
+platform/q_sys/simulation/submodules/cadence/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/cadence/alt_dual_boot.v
+platform/q_sys/simulation/submodules/synopsys/altera_dual_boot.v
+platform/q_sys/simulation/submodules/synopsys/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/synopsys/alt_dual_boot.v
+platform/q_sys/simulation/submodules/q_sys_enet_pll.vo
+platform/q_sys/simulation/submodules/q_sys_eth_tse.v
+platform/q_sys/simulation/submodules/generic_qspi_controller.sv
+platform/q_sys/simulation/submodules/q_sys_jtag_uart.v
+platform/q_sys/simulation/submodules/q_sys_led_pio.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0.v
+platform/q_sys/simulation/submodules/q_sys_onchip_ram.v
+platform/q_sys/simulation/submodules/q_sys_sgdma_rx.v
+platform/q_sys/simulation/submodules/q_sys_sgdma_tx.v
+platform/q_sys/simulation/submodules/q_sys_sys_clk_timer.v
+platform/q_sys/simulation/submodules/q_sys_sysid.v
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0.v
+platform/q_sys/simulation/submodules/q_sys_irq_mapper.sv
+platform/q_sys/simulation/submodules/altera_irq_clock_crosser.sv
+platform/q_sys/simulation/submodules/q_sys_avalon_st_adapter.v
+platform/q_sys/simulation/submodules/altera_reset_controller.v
+platform/q_sys/simulation/submodules/altera_reset_synchronizer.v
+platform/q_sys/simulation/submodules/altera_reset_controller.sdc
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_test_bench.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu.vo
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_nios2_waves.do
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu.sdc
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_mult_cell.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_tck.v
+platform/q_sys/simulation/submodules/mentor/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/aldec/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/synopsys/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/cadence/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/aldec/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/synopsys/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/cadence/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/mentor/altera_eth_tse_std_synchronizer.v
+platform/q_sys/simulation/submodules/aldec/altera_eth_tse_std_synchronizer.v
+platform/q_sys/simulation/submodules/synopsys/altera_eth_tse_std_synchronizer.v
+platform/q_sys/simulation/submodules/cadence/altera_eth_tse_std_synchronizer.v
+platform/q_sys/simulation/submodules/mentor/altera_eth_tse_std_synchronizer_bundle.v
+platform/q_sys/simulation/submodules/aldec/altera_eth_tse_std_synchronizer_bundle.v
+platform/q_sys/simulation/submodules/synopsys/altera_eth_tse_std_synchronizer_bundle.v
+platform/q_sys/simulation/submodules/cadence/altera_eth_tse_std_synchronizer_bundle.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/aldec/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/cadence/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/mentor/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/altera_gpio_lite.sv
+platform/q_sys/simulation/submodules/soft_asmiblock_core.v
+platform/q_sys/simulation/submodules/altera_asmi_parallel_core.v
+platform/q_sys/simulation/submodules/altera_epcq_controller_core.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
+platform/q_sys/simulation/submodules/max10emif_dcfifo.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
+platform/q_sys/simulation/submodules/altera_gpio_lite.sv
+platform/q_sys/simulation/submodules/afi_mux_ddr3_ddrx.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_make_qsys_seq.tcl
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
+platform/q_sys/simulation/submodules/rw_manager_write_decoder.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/simulation/submodules/rw_manager_bitcheck.v
+platform/q_sys/simulation/submodules/sequencer_phy_mgr.sv
+platform/q_sys/simulation/submodules/altera_merlin_burst_uncompressor.sv
+platform/q_sys/simulation/submodules/rw_manager_inst_ROM_reg.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/simulation/submodules/altera_merlin_master_translator.sv
+platform/q_sys/simulation/submodules/rw_manager_dm_decoder.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/simulation/submodules/rw_manager_di_buffer_wrap.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/simulation/submodules/sequencer_m10.sv
+platform/q_sys/simulation/submodules/altera_merlin_slave_translator.sv
+platform/q_sys/simulation/submodules/rw_manager_datamux.v
+platform/q_sys/simulation/submodules/rw_manager_generic.sv
+platform/q_sys/simulation/submodules/rw_manager_di_buffer.v
+platform/q_sys/simulation/submodules/rw_manager_ram_csr.v
+platform/q_sys/simulation/submodules/rw_manager_data_broadcast.v
+platform/q_sys/simulation/submodules/altera_merlin_slave_agent.sv
+platform/q_sys/simulation/submodules/rw_manager_ddr3.v
+platform/q_sys/simulation/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/simulation/submodules/rw_manager_ac_ROM_reg.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/simulation/submodules/rw_manager_jumplogic.v
+platform/q_sys/simulation/submodules/rw_manager_data_decoder.v
+platform/q_sys/simulation/submodules/rw_manager_read_datapath.v
+platform/q_sys/simulation/submodules/sequencer_pll_mgr.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/simulation/submodules/rw_manager_core.sv
+platform/q_sys/simulation/submodules/rw_manager_lfsr12.v
+platform/q_sys/simulation/submodules/altera_mem_if_sequencer_rst.sv
+platform/q_sys/simulation/submodules/rw_manager_ram.v
+platform/q_sys/simulation/submodules/altera_merlin_master_agent.sv
+platform/q_sys/simulation/submodules/rw_manager_lfsr72.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
+platform/q_sys/simulation/submodules/rw_manager_pattern_fifo.v
+platform/q_sys/simulation/submodules/rw_manager_lfsr36.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
+platform/q_sys/simulation/submodules/rw_manager_m10_ac_ROM.v
+platform/q_sys/simulation/submodules/rw_manager_m10_inst_ROM.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
+platform/q_sys/simulation/submodules/altera_merlin_master_translator.sv
+platform/q_sys/simulation/submodules/altera_merlin_slave_translator.sv
+platform/q_sys/simulation/submodules/altera_merlin_master_agent.sv
+platform/q_sys/simulation/submodules/altera_merlin_slave_agent.sv
+platform/q_sys/simulation/submodules/altera_merlin_burst_uncompressor.sv
+platform/q_sys/simulation/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_001.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_002.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_004.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_008.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_009.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_010.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_router_018.sv
+platform/q_sys/simulation/submodules/altera_merlin_traffic_limiter.sv
+platform/q_sys/simulation/submodules/altera_merlin_reorder_memory.sv
+platform/q_sys/simulation/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/simulation/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/simulation/submodules/altera_merlin_burst_adapter.sv
+platform/q_sys/simulation/submodules/altera_merlin_burst_adapter_uncmpr.sv
+platform/q_sys/simulation/submodules/altera_merlin_burst_adapter_13_1.sv
+platform/q_sys/simulation/submodules/altera_merlin_burst_adapter_new.sv
+platform/q_sys/simulation/submodules/altera_incr_burst_converter.sv
+platform/q_sys/simulation/submodules/altera_wrap_burst_converter.sv
+platform/q_sys/simulation/submodules/altera_default_burst_converter.sv
+platform/q_sys/simulation/submodules/altera_merlin_address_alignment.sv
+platform/q_sys/simulation/submodules/altera_avalon_st_pipeline_stage.sv
+platform/q_sys/simulation/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
+platform/q_sys/simulation/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/simulation/submodules/altera_avalon_st_handshake_clock_crosser.v
+platform/q_sys/simulation/submodules/altera_avalon_st_clock_crosser.v
+platform/q_sys/simulation/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/simulation/submodules/altera_std_synchronizer_nocut.v
+platform/q_sys/simulation/submodules/altera_avalon_st_handshake_clock_crosser.sdc
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/simulation/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
+platform/q_sys/simulation/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
+platform/q_sys/simulation/submodules/soft_asmiblock.sv
+platform/q_sys/simulation/submodules/q_sys_ext_flash_altera_asmi_parallel_core_altera_asmi_parallel_core.v
+platform/q_sys/simulation/submodules/altera_epcq_controller_arb.sv
+platform/q_sys/simulation/submodules/altera_epcq_controller.sv
+platform/q_sys/simulation/submodules/alt_mem_ddrx_addr_cmd.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_addr_cmd_wrap.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ddr2_odt_gen.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ddr3_odt_gen.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_odt_gen.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_rdwr_data_tmg.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_arbiter.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_burst_gen.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_cmd_gen.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_csr.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_buffer.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_buffer_manager.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_burst_tracking.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_dataid_manager.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_fifo.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_list.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_rdata_path.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_wdata_path.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_define.iv
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_decoder.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_encoder.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_axi_st_converter.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_input_if.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_rank_timer.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_sideband.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_tbp.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_timing_param.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_controller.v
+platform/q_sys/simulation/submodules/alt_mem_ddrx_controller_st_top.v
+platform/q_sys/simulation/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
+platform/q_sys/simulation/submodules/alt_mem_ddrx_mm_st_converter.v
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/simulation/q_sys.sip
+platform/q_sys/simulation/q_sys.spd
+platform/q_sys/synthesis/q_sys.v
+platform/q_sys/synthesis/submodules/q_sys_altpll_shift.v
+platform/q_sys/synthesis/submodules/q_sys_cpu.v
+platform/q_sys/synthesis/submodules/q_sys_descriptor_memory.v
+platform/q_sys/synthesis/submodules/altera_dual_boot.v
+platform/q_sys/synthesis/submodules/rtl/alt_dual_boot_avmm.v
+platform/q_sys/synthesis/submodules/rtl/alt_dual_boot.v
+platform/q_sys/synthesis/submodules/q_sys_enet_pll.v
+platform/q_sys/synthesis/submodules/q_sys_eth_tse.v
+platform/q_sys/synthesis/submodules/generic_qspi_controller.sv
+platform/q_sys/synthesis/submodules/q_sys_jtag_uart.v
+platform/q_sys/synthesis/submodules/q_sys_led_pio.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v
+platform/q_sys/synthesis/submodules/q_sys_onchip_ram.v
+platform/q_sys/synthesis/submodules/q_sys_sgdma_rx.v
+platform/q_sys/synthesis/submodules/q_sys_sgdma_tx.v
+platform/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v
+platform/q_sys/synthesis/submodules/q_sys_sysid.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v
+platform/q_sys/synthesis/submodules/q_sys_irq_mapper.sv
+platform/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/altera_reset_controller.v
+platform/q_sys/synthesis/submodules/altera_reset_synchronizer.v
+platform/q_sys/synthesis/submodules/altera_reset_controller.sdc
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.ocp
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.v
+platform/q_sys/synthesis/submodules/altera_eth_tse_mac.v
+platform/q_sys/synthesis/submodules/altera_tse_clk_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_crc328checker.v
+platform/q_sys/synthesis/submodules/altera_tse_crc328generator.v
+platform/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v
+platform/q_sys/synthesis/submodules/altera_tse_crc32galois8.v
+platform/q_sys/synthesis/submodules/altera_tse_gmii_io.v
+platform/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_hashing.v
+platform/q_sys/synthesis/submodules/altera_tse_host_control.v
+platform/q_sys/synthesis/submodules/altera_tse_host_control_small.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_control.v
+platform/q_sys/synthesis/submodules/altera_tse_register_map.v
+platform/q_sys/synthesis/submodules/altera_tse_register_map_small.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v
+platform/q_sys/synthesis/submodules/altera_tse_shared_register_map.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_lfsr_10.v
+platform/q_sys/synthesis/submodules/altera_tse_loopback_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_altshifttaps.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_rx.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_tx.v
+platform/q_sys/synthesis/submodules/altera_tse_magic_detection.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_top_mdio.v
+platform/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v
+platform/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v
+platform/q_sys/synthesis/submodules/altera_tse_pipeline_base.v
+platform/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv
+platform/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v
+platform/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v
+platform/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v
+platform/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_module.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/synthesis/submodules/altera_tse_top_1geth.v
+platform/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/synthesis/submodules/altera_tse_top_gen_host.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v
+platform/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v
+platform/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v
+platform/q_sys/synthesis/submodules/altera_tse_false_path_marker.v
+platform/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v
+platform/q_sys/synthesis/submodules/altera_tse_clock_crosser.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/synthesis/submodules/altera_tse_gray_cnt.v
+platform/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v
+platform/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_bin_cnt.v
+platform/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv
+platform/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp
+platform/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc
+platform/q_sys/synthesis/submodules/altera_gpio_lite.sv
+platform/q_sys/synthesis/submodules/soft_asmiblock_core.v
+platform/q_sys/synthesis/submodules/altera_asmi_parallel_core.v
+platform/q_sys/synthesis/submodules/altera_epcq_controller_core.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
+platform/q_sys/synthesis/submodules/max10emif_dcfifo.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
+platform/q_sys/synthesis/submodules/altera_gpio_lite.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_timing.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_report_timing.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_report_timing_core.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_pin_map.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_parameters.tcl
+platform/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_make_qsys_seq.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
+platform/q_sys/synthesis/submodules/rw_manager_write_decoder.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/synthesis/submodules/rw_manager_bitcheck.v
+platform/q_sys/synthesis/submodules/sequencer_phy_mgr.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
+platform/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
+platform/q_sys/synthesis/submodules/rw_manager_dm_decoder.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/synthesis/submodules/sequencer_m10.sv
+platform/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
+platform/q_sys/synthesis/submodules/rw_manager_datamux.v
+platform/q_sys/synthesis/submodules/rw_manager_generic.sv
+platform/q_sys/synthesis/submodules/rw_manager_di_buffer.v
+platform/q_sys/synthesis/submodules/rw_manager_ram_csr.v
+platform/q_sys/synthesis/submodules/rw_manager_data_broadcast.v
+platform/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
+platform/q_sys/synthesis/submodules/rw_manager_ddr3.v
+platform/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/synthesis/submodules/rw_manager_jumplogic.v
+platform/q_sys/synthesis/submodules/rw_manager_data_decoder.v
+platform/q_sys/synthesis/submodules/rw_manager_read_datapath.v
+platform/q_sys/synthesis/submodules/sequencer_pll_mgr.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/synthesis/submodules/rw_manager_core.sv
+platform/q_sys/synthesis/submodules/rw_manager_lfsr12.v
+platform/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv
+platform/q_sys/synthesis/submodules/rw_manager_ram.v
+platform/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
+platform/q_sys/synthesis/submodules/rw_manager_lfsr72.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
+platform/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v
+platform/q_sys/synthesis/submodules/rw_manager_lfsr36.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
+platform/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v
+platform/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
+platform/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
+platform/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
+platform/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
+platform/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
+platform/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv
+platform/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv
+platform/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv
+platform/q_sys/synthesis/submodules/altera_incr_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_default_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
+platform/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v
+platform/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
+platform/q_sys/synthesis/submodules/soft_asmiblock.sv
+platform/q_sys/synthesis/submodules/q_sys_ext_flash_altera_asmi_parallel_core_altera_asmi_parallel_core.v
+platform/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv
+platform/q_sys/synthesis/submodules/altera_epcq_controller.sv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_list.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v
+platform/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/synthesis/q_sys.qip
+platform/q_sys/q_sys.sopcinfo
+RevC_to_RevB.tcl
+RevB_to_RevC.tcl
+tcl_readme.txt
+README.txt
+clkctrl/synthesis/clkctrl.qip
+clkctrl/synthesis/clkctrl.v
+clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
+clkctrl/synthesis/clkctrl.debuginfo
+clkctrl/synthesis/clkctrl.qip.bak
+clkctrl/clkctrl_generation.rpt
+clkctrl/clkctrl.html
+clkctrl/clkctrl.bsf
+clkctrl/clkctrl.cmp
+clkctrl/clkctrl.xml
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.cmp
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd
+enet_gtx_clk_ddio/enet_gtx_clk_ddio.v
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f
+enet_gtx_clk_ddio/enet_gtx_clk_ddio/altera_gpio_lite.sv
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/aldec/rivierapro_setup.tcl
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/cadence/cds.lib
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/cadence/hdl.var
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/cadence/ncsim_setup.sh
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/cadence/cds_libs/enet_gtx_clk_ddio.cds.lib
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/mentor/msim_setup.tcl
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/synopsys/vcs/vcs_setup.sh
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/synopsys/vcsmx/synopsys_sim.setup
+enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim/synopsys/vcsmx/vcsmx_setup.sh
+m10_rgmii.out.sdc
+m10_rgmii.v
+master_image/m10_rgmii.pof
+master_image/m10_rgmii.sof
+master_image/niosII_simple_socket_server.elf
+platform/q_sys/q_sys.sopcinfo
+platform/q_sys/simulation/q_sys.sip
+platform/q_sys/simulation/q_sys.spd
+platform/q_sys/simulation/q_sys.v
+platform/q_sys/simulation/submodules/afi_mux_ddr3_ddrx.v
+platform/q_sys/simulation/submodules/aldec/alt_dual_boot.v
+platform/q_sys/simulation/submodules/aldec/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/aldec/altera_dual_boot.v
+platform/q_sys/simulation/submodules/aldec/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/aldec/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/aldec/altera_tse_quad_16x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_quad_8x32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/aldec/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/altera_asmi_parallel_core.v
+platform/q_sys/simulation/submodules/altera_epcq_controller_core.v
+platform/q_sys/simulation/submodules/altera_gpio_lite.sv
+platform/q_sys/simulation/submodules/altera_irq_clock_crosser.sv
+platform/q_sys/simulation/submodules/altera_reset_controller.sdc
+platform/q_sys/simulation/submodules/altera_reset_controller.v
+platform/q_sys/simulation/submodules/altera_reset_synchronizer.v
+platform/q_sys/simulation/submodules/cadence/alt_dual_boot.v
+platform/q_sys/simulation/submodules/cadence/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/cadence/altera_dual_boot.v
+platform/q_sys/simulation/submodules/cadence/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/cadence/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/cadence/altera_tse_quad_16x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_quad_8x32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/cadence/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/generic_qspi_controller.sv
+platform/q_sys/simulation/submodules/mentor/alt_dual_boot.v
+platform/q_sys/simulation/submodules/mentor/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/mentor/altera_dual_boot.v
+platform/q_sys/simulation/submodules/mentor/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/mentor/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/mentor/altera_tse_quad_16x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_quad_8x32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/mentor/altera_tse_tx_stat_extract.v
+platform/q_sys/simulation/submodules/q_sys_altpll_shift.vo
+platform/q_sys/simulation/submodules/q_sys_avalon_st_adapter.v
+platform/q_sys/simulation/submodules/q_sys_cpu.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu.ocp
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu.sdc
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu.vo
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_bht_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_tck.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_mult_cell.v
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_nios2_waves.do
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_a.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.dat
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.hex
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_rf_ram_b.mif
+platform/q_sys/simulation/submodules/q_sys_cpu_cpu_test_bench.v
+platform/q_sys/simulation/submodules/q_sys_descriptor_memory.v
+platform/q_sys/simulation/submodules/q_sys_enet_pll.vo
+platform/q_sys/simulation/submodules/q_sys_eth_tse.v
+platform/q_sys/simulation/submodules/q_sys_irq_mapper.sv
+platform/q_sys/simulation/submodules/q_sys_jtag_uart.v
+platform/q_sys/simulation/submodules/q_sys_led_pio.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
+platform/q_sys/simulation/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
+platform/q_sys/simulation/submodules/q_sys_mm_interconnect_0.v
+platform/q_sys/simulation/submodules/q_sys_onchip_ram.v
+platform/q_sys/simulation/submodules/q_sys_sgdma_rx.v
+platform/q_sys/simulation/submodules/q_sys_sgdma_tx.v
+platform/q_sys/simulation/submodules/q_sys_sys_clk_timer.v
+platform/q_sys/simulation/submodules/q_sys_sysid.vo
+platform/q_sys/simulation/submodules/soft_asmiblock_core.v
+platform/q_sys/simulation/submodules/synopsys/alt_dual_boot.v
+platform/q_sys/simulation/submodules/synopsys/alt_dual_boot_avmm.v
+platform/q_sys/simulation/submodules/synopsys/altera_dual_boot.v
+platform/q_sys/simulation/submodules/synopsys/altera_eth_tse_mac.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_13.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_24.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_34.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_altshifttaps.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_bin_cnt.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_clk_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_clock_crosser.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc328checker.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc328generator.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc32ctl8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_crc32galois8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_16x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_8x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x14.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x2.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x23.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x30.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x36.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_dec_x40.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x14.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x2.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x23.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x30.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x36.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x40.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ecc_status_crosser.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_false_path_marker.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_mac_rx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_mac_tx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_gmii_io.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_gray_cnt.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_hashing.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_host_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_host_control_small.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lb_read_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lb_wrt_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_lfsr_10.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_loopback_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_rx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mac_tx.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_magic_detection.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio_clk_gen.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mdio_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mii_rx_if.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_mii_tx_if.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_nf_rgmii_module.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_ph_calculator.sv
+platform/q_sys/simulation/submodules/synopsys/altera_tse_pipeline_base.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_pipeline_stage.sv
+platform/q_sys/simulation/submodules/synopsys/altera_tse_quad_16x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_quad_8x32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_register_map.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_register_map_small.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_reset_synchronizer.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_retransmit_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_in1.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_in4.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_module.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_out1.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rgmii_out4.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_counter_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_ff_length.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_min_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_rx_stat_extract.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_sdpm_altsyncram.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_sdpm_gen.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_shared_mac_control.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_shared_register_map.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_1geth.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_fifoless_1geth.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_gen_host.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_mdio.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_w_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_wo_fifo.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_counter_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_length.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_min_ff.v
+platform/q_sys/simulation/submodules/synopsys/altera_tse_tx_stat_extract.v
+platform/q_sys/synthesis/q_sys.qip
+platform/q_sys/synthesis/q_sys.v
+platform/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
+platform/q_sys/synthesis/submodules/altera_asmi_parallel_core.v
+platform/q_sys/synthesis/submodules/altera_dual_boot.v
+platform/q_sys/synthesis/submodules/altera_epcq_controller_core.v
+platform/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc
+platform/q_sys/synthesis/submodules/altera_eth_tse_mac.v
+platform/q_sys/synthesis/submodules/altera_gpio_lite.sv
+platform/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv
+platform/q_sys/synthesis/submodules/altera_reset_controller.sdc
+platform/q_sys/synthesis/submodules/altera_reset_controller.v
+platform/q_sys/synthesis/submodules/altera_reset_synchronizer.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v
+platform/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v
+platform/q_sys/synthesis/submodules/altera_tse_altshifttaps.v
+platform/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_bin_cnt.v
+platform/q_sys/synthesis/submodules/altera_tse_clk_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_clock_crosser.v
+platform/q_sys/synthesis/submodules/altera_tse_crc328checker.v
+platform/q_sys/synthesis/submodules/altera_tse_crc328generator.v
+platform/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v
+platform/q_sys/synthesis/submodules/altera_tse_crc32galois8.v
+platform/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v
+platform/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v
+platform/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v
+platform/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v
+platform/q_sys/synthesis/submodules/altera_tse_false_path_marker.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v
+platform/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_gmii_io.v
+platform/q_sys/synthesis/submodules/altera_tse_gray_cnt.v
+platform/q_sys/synthesis/submodules/altera_tse_hashing.v
+platform/q_sys/synthesis/submodules/altera_tse_host_control.v
+platform/q_sys/synthesis/submodules/altera_tse_host_control_small.v
+platform/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_lfsr_10.v
+platform/q_sys/synthesis/submodules/altera_tse_loopback_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_control.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_rx.v
+platform/q_sys/synthesis/submodules/altera_tse_mac_tx.v
+platform/q_sys/synthesis/submodules/altera_tse_magic_detection.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v
+platform/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v
+platform/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v
+platform/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v
+platform/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv
+platform/q_sys/synthesis/submodules/altera_tse_pipeline_base.v
+platform/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv
+platform/q_sys/synthesis/submodules/altera_tse_quad_16x32.v
+platform/q_sys/synthesis/submodules/altera_tse_quad_8x32.v
+platform/q_sys/synthesis/submodules/altera_tse_register_map.v
+platform/q_sys/synthesis/submodules/altera_tse_register_map_small.v
+platform/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v
+platform/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_module.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v
+platform/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v
+platform/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v
+platform/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v
+platform/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v
+platform/q_sys/synthesis/submodules/altera_tse_shared_register_map.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v
+platform/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v
+platform/q_sys/synthesis/submodules/altera_tse_top_1geth.v
+platform/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v
+platform/q_sys/synthesis/submodules/altera_tse_top_gen_host.v
+platform/q_sys/synthesis/submodules/altera_tse_top_mdio.v
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp
+platform/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp
+platform/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v
+platform/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v
+platform/q_sys/synthesis/submodules/generic_qspi_controller.sv
+platform/q_sys/synthesis/submodules/q_sys_altpll_shift.v
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/q_sys_cpu.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.ocp
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif
+platform/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v
+platform/q_sys/synthesis/submodules/q_sys_descriptor_memory.v
+platform/q_sys/synthesis/submodules/q_sys_enet_pll.v
+platform/q_sys/synthesis/submodules/q_sys_eth_tse.v
+platform/q_sys/synthesis/submodules/q_sys_irq_mapper.sv
+platform/q_sys/synthesis/submodules/q_sys_jtag_uart.v
+platform/q_sys/synthesis/submodules/q_sys_led_pio.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_parameters.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_pin_map.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_report_timing.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_report_timing_core.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_timing.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v
+platform/q_sys/synthesis/submodules/q_sys_onchip_ram.v
+platform/q_sys/synthesis/submodules/q_sys_sgdma_rx.v
+platform/q_sys/synthesis/submodules/q_sys_sgdma_tx.v
+platform/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v
+platform/q_sys/synthesis/submodules/q_sys_sysid.v
+platform/q_sys/synthesis/submodules/rtl/alt_dual_boot.v
+platform/q_sys/synthesis/submodules/rtl/alt_dual_boot_avmm.v
+platform/q_sys/synthesis/submodules/soft_asmiblock_core.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_make_qsys_seq.tcl
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
+platform/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
+platform/q_sys/synthesis/submodules/rw_manager_di_buffer.v
+platform/q_sys/synthesis/submodules/rw_manager_lfsr36.v
+platform/q_sys/synthesis/submodules/rw_manager_lfsr72.v
+platform/q_sys/synthesis/submodules/sequencer_phy_mgr.sv
+platform/q_sys/synthesis/submodules/rw_manager_datamux.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v
+platform/q_sys/synthesis/submodules/sequencer_m10.sv
+platform/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
+platform/q_sys/synthesis/submodules/rw_manager_read_datapath.v
+platform/q_sys/synthesis/submodules/rw_manager_core.sv
+platform/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v
+platform/q_sys/synthesis/submodules/rw_manager_jumplogic.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
+platform/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
+platform/q_sys/synthesis/submodules/rw_manager_write_decoder.v
+platform/q_sys/synthesis/submodules/rw_manager_data_decoder.v
+platform/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
+platform/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v
+platform/q_sys/synthesis/submodules/rw_manager_ram.v
+platform/q_sys/synthesis/submodules/rw_manager_lfsr12.v
+platform/q_sys/synthesis/submodules/rw_manager_ddr3.v
+platform/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
+platform/q_sys/synthesis/submodules/rw_manager_data_broadcast.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
+platform/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
+platform/q_sys/synthesis/submodules/sequencer_pll_mgr.sv
+platform/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
+platform/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv
+platform/q_sys/synthesis/submodules/rw_manager_generic.sv
+platform/q_sys/synthesis/submodules/rw_manager_ram_csr.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/synthesis/submodules/rw_manager_bitcheck.v
+platform/q_sys/synthesis/submodules/rw_manager_dm_decoder.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
+platform/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v
+platform/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v
+platform/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv
+platform/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
+platform/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv
+platform/q_sys/synthesis/submodules/altera_incr_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_default_burst_converter.sv
+platform/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
+platform/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
+platform/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
+platform/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
+platform/q_sys/synthesis/submodules/soft_asmiblock.sv
+platform/q_sys/synthesis/submodules/q_sys_ext_flash_altera_asmi_parallel_core_altera_asmi_parallel_core.v
+platform/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv
+platform/q_sys/synthesis/submodules/altera_epcq_controller.sv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_list.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v
+platform/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
+platform/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v
+platform/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
+platform/q_sys/synthesis/q_sys.regmap
+platform/q_sys/synthesis/q_sys.debuginfo
+platform/q_sys/q_sys_generation_previous.rpt
+platform/q_sys/q_sys.html
+platform/q_sys/q_sys.bsf
+platform/q_sys/q_sys.cmp
+platform/q_sys/q_sys.xml
+platform/q_sys/q_sys_generation.rpt
+q_sys.qsys
+software/src/alt_error_handler.c
+software/src/alt_error_handler.h
+software/src/iniche_init.c
+software/src/led.c
+software/src/network_utilities.c
+software/src/network_utilities.h
+software/src/simple_socket_server.c
+software/src/simple_socket_server.h
+software/src/tse_my_system.c
+software/q_sys.sopcinfo
+software/new_bsp/create-this-bsp
+software/new_bsp/settings.bsp
+software/new_bsp/summary.html
+software/new_bsp/HAL/src/alt_alarm_start.c
+software/new_bsp/HAL/src/alt_close.c
+software/new_bsp/HAL/src/alt_dev.c
+software/new_bsp/HAL/src/alt_dev_llist_insert.c
+software/new_bsp/HAL/src/alt_dma_rxchan_open.c
+software/new_bsp/HAL/src/alt_dma_txchan_open.c
+software/new_bsp/HAL/src/alt_environ.c
+software/new_bsp/HAL/src/alt_errno.c
+software/new_bsp/HAL/src/alt_execve.c
+software/new_bsp/HAL/src/alt_exit.c
+software/new_bsp/HAL/src/alt_fcntl.c
+software/new_bsp/HAL/src/alt_fd_lock.c
+software/new_bsp/HAL/src/alt_fd_unlock.c
+software/new_bsp/HAL/src/alt_find_dev.c
+software/new_bsp/HAL/src/alt_find_file.c
+software/new_bsp/HAL/src/alt_flash_dev.c
+software/new_bsp/HAL/src/alt_fork.c
+software/new_bsp/HAL/src/alt_fs_reg.c
+software/new_bsp/HAL/src/alt_fstat.c
+software/new_bsp/HAL/src/alt_get_fd.c
+software/new_bsp/HAL/src/alt_getchar.c
+software/new_bsp/HAL/src/alt_getpid.c
+software/new_bsp/HAL/src/alt_gettod.c
+software/new_bsp/HAL/src/alt_iic_isr_register.c
+software/new_bsp/HAL/src/alt_instruction_exception_register.c
+software/new_bsp/HAL/src/alt_ioctl.c
+software/new_bsp/HAL/src/alt_io_redirect.c
+software/new_bsp/HAL/src/alt_irq_handler.c
+software/new_bsp/HAL/src/alt_isatty.c
+software/new_bsp/HAL/src/alt_kill.c
+software/new_bsp/HAL/src/alt_link.c
+software/new_bsp/HAL/src/alt_load.c
+software/new_bsp/HAL/src/alt_log_printf.c
+software/new_bsp/HAL/src/alt_lseek.c
+software/new_bsp/HAL/src/alt_main.c
+software/new_bsp/HAL/src/alt_open.c
+software/new_bsp/HAL/src/alt_printf.c
+software/new_bsp/HAL/src/alt_putchar.c
+software/new_bsp/HAL/src/alt_putstr.c
+software/new_bsp/HAL/src/alt_read.c
+software/new_bsp/HAL/src/alt_release_fd.c
+software/new_bsp/HAL/src/alt_rename.c
+software/new_bsp/HAL/src/alt_sbrk.c
+software/new_bsp/HAL/src/alt_settod.c
+software/new_bsp/HAL/src/alt_stat.c
+software/new_bsp/HAL/src/alt_tick.c
+software/new_bsp/HAL/src/alt_times.c
+software/new_bsp/HAL/src/alt_unlink.c
+software/new_bsp/HAL/src/alt_wait.c
+software/new_bsp/HAL/src/alt_write.c
+software/new_bsp/HAL/src/altera_nios2_gen2_irq.c
+software/new_bsp/HAL/src/alt_busy_sleep.c
+software/new_bsp/HAL/src/alt_irq_vars.c
+software/new_bsp/HAL/src/alt_icache_flush.c
+software/new_bsp/HAL/src/alt_icache_flush_all.c
+software/new_bsp/HAL/src/alt_dcache_flush.c
+software/new_bsp/HAL/src/alt_dcache_flush_all.c
+software/new_bsp/HAL/src/alt_dcache_flush_no_writeback.c
+software/new_bsp/HAL/src/alt_ecc_fatal_exception.c
+software/new_bsp/HAL/src/alt_instruction_exception_entry.c
+software/new_bsp/HAL/src/alt_irq_register.c
+software/new_bsp/HAL/src/alt_iic.c
+software/new_bsp/HAL/src/alt_remap_cached.c
+software/new_bsp/HAL/src/alt_remap_uncached.c
+software/new_bsp/HAL/src/alt_uncached_free.c
+software/new_bsp/HAL/src/alt_uncached_malloc.c
+software/new_bsp/HAL/src/alt_do_ctors.c
+software/new_bsp/HAL/src/alt_do_dtors.c
+software/new_bsp/HAL/src/alt_gmon.c
+software/new_bsp/HAL/src/alt_usleep.c
+software/new_bsp/HAL/src/os_cpu_c.c
+software/new_bsp/HAL/src/alt_ecc_fatal_entry.S
+software/new_bsp/HAL/src/alt_exception_entry.S
+software/new_bsp/HAL/src/alt_exception_trap.S
+software/new_bsp/HAL/src/alt_exception_muldiv.S
+software/new_bsp/HAL/src/alt_irq_entry.S
+software/new_bsp/HAL/src/alt_software_exception.S
+software/new_bsp/HAL/src/alt_mcount.S
+software/new_bsp/HAL/src/alt_log_macro.S
+software/new_bsp/HAL/src/crt0.S
+software/new_bsp/HAL/src/os_cpu_a.S
+software/new_bsp/HAL/inc/priv/alt_alarm.h
+software/new_bsp/HAL/inc/priv/alt_dev_llist.h
+software/new_bsp/HAL/inc/priv/alt_exception_handler_registry.h
+software/new_bsp/HAL/inc/priv/alt_file.h
+software/new_bsp/HAL/inc/priv/alt_iic_isr_register.h
+software/new_bsp/HAL/inc/priv/alt_irq_table.h
+software/new_bsp/HAL/inc/priv/alt_no_error.h
+software/new_bsp/HAL/inc/priv/alt_busy_sleep.h
+software/new_bsp/HAL/inc/priv/alt_legacy_irq.h
+software/new_bsp/HAL/inc/priv/nios2_gmon_data.h
+software/new_bsp/HAL/inc/sys/alt_alarm.h
+software/new_bsp/HAL/inc/sys/alt_cache.h
+software/new_bsp/HAL/inc/sys/alt_dev.h
+software/new_bsp/HAL/inc/sys/alt_dma.h
+software/new_bsp/HAL/inc/sys/alt_dma_dev.h
+software/new_bsp/HAL/inc/sys/alt_driver.h
+software/new_bsp/HAL/inc/sys/alt_errno.h
+software/new_bsp/HAL/inc/sys/alt_flash.h
+software/new_bsp/HAL/inc/sys/alt_flash_dev.h
+software/new_bsp/HAL/inc/sys/alt_flash_types.h
+software/new_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h
+software/new_bsp/HAL/inc/sys/alt_llist.h
+software/new_bsp/HAL/inc/sys/alt_load.h
+software/new_bsp/HAL/inc/sys/alt_log_printf.h
+software/new_bsp/HAL/inc/sys/alt_set_args.h
+software/new_bsp/HAL/inc/sys/alt_stdio.h
+software/new_bsp/HAL/inc/sys/alt_sys_init.h
+software/new_bsp/HAL/inc/sys/alt_sys_wrappers.h
+software/new_bsp/HAL/inc/sys/alt_timestamp.h
+software/new_bsp/HAL/inc/sys/ioctl.h
+software/new_bsp/HAL/inc/sys/termios.h
+software/new_bsp/HAL/inc/sys/alt_debug.h
+software/new_bsp/HAL/inc/sys/alt_exceptions.h
+software/new_bsp/HAL/inc/sys/alt_irq_entry.h
+software/new_bsp/HAL/inc/sys/alt_irq.h
+software/new_bsp/HAL/inc/sys/alt_sim.h
+software/new_bsp/HAL/inc/sys/alt_stack.h
+software/new_bsp/HAL/inc/sys/alt_warning.h
+software/new_bsp/HAL/inc/altera_nios2_gen2_irq.h
+software/new_bsp/HAL/inc/alt_types.h
+software/new_bsp/HAL/inc/io.h
+software/new_bsp/HAL/inc/nios2.h
+software/new_bsp/HAL/inc/includes.h
+software/new_bsp/HAL/inc/os_cpu.h
+software/new_bsp/UCOSII/src/alt_env_lock.c
+software/new_bsp/UCOSII/src/alt_malloc_lock.c
+software/new_bsp/UCOSII/src/os_core.c
+software/new_bsp/UCOSII/src/os_dbg.c
+software/new_bsp/UCOSII/src/os_flag.c
+software/new_bsp/UCOSII/src/os_mbox.c
+software/new_bsp/UCOSII/src/os_mem.c
+software/new_bsp/UCOSII/src/os_mutex.c
+software/new_bsp/UCOSII/src/os_q.c
+software/new_bsp/UCOSII/src/os_sem.c
+software/new_bsp/UCOSII/src/os_task.c
+software/new_bsp/UCOSII/src/os_time.c
+software/new_bsp/UCOSII/src/os_tmr.c
+software/new_bsp/UCOSII/inc/os/alt_flag.h
+software/new_bsp/UCOSII/inc/os/alt_hooks.h
+software/new_bsp/UCOSII/inc/os/alt_sem.h
+software/new_bsp/UCOSII/inc/priv/alt_flag_ucosii.h
+software/new_bsp/UCOSII/inc/priv/alt_sem_ucosii.h
+software/new_bsp/UCOSII/inc/os_cfg.h
+software/new_bsp/UCOSII/inc/ucos_ii.h
+software/new_bsp/drivers/src/altera_avalon_tse_system_info.c
+software/new_bsp/drivers/src/altera_avalon_tse.c
+software/new_bsp/drivers/src/iniche/ins_tse_mac.c
+software/new_bsp/drivers/src/altera_avalon_sgdma.c
+software/new_bsp/drivers/src/altera_avalon_timer_sc.c
+software/new_bsp/drivers/src/altera_avalon_timer_ts.c
+software/new_bsp/drivers/src/altera_avalon_timer_vars.c
+software/new_bsp/drivers/src/altera_avalon_jtag_uart_init.c
+software/new_bsp/drivers/src/altera_avalon_jtag_uart_read.c
+software/new_bsp/drivers/src/altera_avalon_jtag_uart_write.c
+software/new_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c
+software/new_bsp/drivers/src/altera_avalon_jtag_uart_fd.c
+software/new_bsp/drivers/src/altera_avalon_sysid_qsys.c
+software/new_bsp/drivers/src/altera_generic_quad_spi_controller.c
+software/new_bsp/drivers/inc/altera_avalon_tse_system_info.h
+software/new_bsp/drivers/inc/altera_avalon_tse.h
+software/new_bsp/drivers/inc/altera_eth_tse.h
+software/new_bsp/drivers/inc/altera_eth_tse_regs.h
+software/new_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h
+software/new_bsp/drivers/inc/iniche/ins_tse_mac.h
+software/new_bsp/drivers/inc/altera_avalon_sgdma.h
+software/new_bsp/drivers/inc/altera_avalon_sgdma_descriptor.h
+software/new_bsp/drivers/inc/altera_avalon_sgdma_regs.h
+software/new_bsp/drivers/inc/altera_avalon_timer.h
+software/new_bsp/drivers/inc/altera_avalon_timer_regs.h
+software/new_bsp/drivers/inc/altera_avalon_jtag_uart.h
+software/new_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h
+software/new_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h
+software/new_bsp/drivers/inc/altera_avalon_sysid_qsys.h
+software/new_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h
+software/new_bsp/drivers/inc/altera_avalon_pio_regs.h
+software/new_bsp/drivers/inc/altera_generic_quad_spi_controller.h
+software/new_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h
+software/new_bsp/iniche/src/alt_iniche_close.c
+software/new_bsp/iniche/src/alt_iniche_dev.c
+software/new_bsp/iniche/src/alt_iniche_fcntl.c
+software/new_bsp/iniche/src/alt_iniche_read.c
+software/new_bsp/iniche/src/alt_iniche_write.c
+software/new_bsp/iniche/src/allports/allports.c
+software/new_bsp/iniche/src/allports/timeouts.c
+software/new_bsp/iniche/src/allports/tk_misc.c
+software/new_bsp/iniche/src/autoip4/autoip.c
+software/new_bsp/iniche/src/autoip4/upnp.c
+software/new_bsp/iniche/src/autoip4/upnpmenu.c
+software/new_bsp/iniche/src/autoip4/autoip.h
+software/new_bsp/iniche/src/autoip4/ds_app.h
+software/new_bsp/iniche/src/autoip4/upnp.h
+software/new_bsp/iniche/src/ftp/ftpclnt.c
+software/new_bsp/iniche/src/ftp/ftpsrv.c
+software/new_bsp/iniche/src/ftp/ftpcport.c
+software/new_bsp/iniche/src/ftp/ftpssock.c
+software/new_bsp/iniche/src/ftp/ftpcprn.c
+software/new_bsp/iniche/src/ftp/ftpsvfs.c
+software/new_bsp/iniche/src/ftp/ftpmenu.c
+software/new_bsp/iniche/src/ftp/ftpsport.c
+software/new_bsp/iniche/src/ftp/ftpclnt.h
+software/new_bsp/iniche/src/ftp/ftpport.h
+software/new_bsp/iniche/src/ftp/ftpsrv.h
+software/new_bsp/iniche/src/ip/et_arp.c
+software/new_bsp/iniche/src/ip/icmp.c
+software/new_bsp/iniche/src/ip/iface.c
+software/new_bsp/iniche/src/ip/ip.c
+software/new_bsp/iniche/src/ip/ipdemux.c
+software/new_bsp/iniche/src/ip/ipmc.c
+software/new_bsp/iniche/src/ip/ipnet.c
+software/new_bsp/iniche/src/ip/ipport.c
+software/new_bsp/iniche/src/ip/ipraw.c
+software/new_bsp/iniche/src/ip/ip_reasm.c
+software/new_bsp/iniche/src/ip/iproute.c
+software/new_bsp/iniche/src/ip/ipstart.c
+software/new_bsp/iniche/src/ip/pmtu.c
+software/new_bsp/iniche/src/ip/rtbtree.c
+software/new_bsp/iniche/src/ip/udp.c
+software/new_bsp/iniche/src/ip/ip_reasm.h
+software/new_bsp/iniche/src/ipmc/igmp2.c
+software/new_bsp/iniche/src/ipmc/igmp.c
+software/new_bsp/iniche/src/ipmc/igmp_cmn.c
+software/new_bsp/iniche/src/ipmc/ipopt.c
+software/new_bsp/iniche/src/ipmc/u_mctest.c
+software/new_bsp/iniche/src/ipmc/igmp.h
+software/new_bsp/iniche/src/ipmc/igmp2.h
+software/new_bsp/iniche/src/ipmc/igmp_cmn.h
+software/new_bsp/iniche/src/misclib/app_ping.c
+software/new_bsp/iniche/src/misclib/bsdsock.c
+software/new_bsp/iniche/src/misclib/cksum.c
+software/new_bsp/iniche/src/misclib/cu_srv.c
+software/new_bsp/iniche/src/misclib/dhcsetup.c
+software/new_bsp/iniche/src/misclib/genlist.c
+software/new_bsp/iniche/src/misclib/iniche_log.c
+software/new_bsp/iniche/src/misclib/iniche_qsort.c
+software/new_bsp/iniche/src/misclib/in_utils.c
+software/new_bsp/iniche/src/misclib/localtime.c
+software/new_bsp/iniche/src/misclib/memdev.c
+software/new_bsp/iniche/src/misclib/memio.c
+software/new_bsp/iniche/src/misclib/memwrap.c
+software/new_bsp/iniche/src/misclib/menulib.c
+software/new_bsp/iniche/src/misclib/menus.c
+software/new_bsp/iniche/src/misclib/msring.c
+software/new_bsp/iniche/src/misclib/netmain.c
+software/new_bsp/iniche/src/misclib/nextcarg.c
+software/new_bsp/iniche/src/misclib/nrmenus.c
+software/new_bsp/iniche/src/misclib/nvfsio.c
+software/new_bsp/iniche/src/misclib/nvparms.c
+software/new_bsp/iniche/src/misclib/parseip.c
+software/new_bsp/iniche/src/misclib/pcycles.c
+software/new_bsp/iniche/src/misclib/profiler.c
+software/new_bsp/iniche/src/misclib/rawiptst.c
+software/new_bsp/iniche/src/misclib/reshost.c
+software/new_bsp/iniche/src/misclib/rfsim.c
+software/new_bsp/iniche/src/misclib/rttest.c
+software/new_bsp/iniche/src/misclib/soperr.c
+software/new_bsp/iniche/src/misclib/strilib.c
+software/new_bsp/iniche/src/misclib/strlib.c
+software/new_bsp/iniche/src/misclib/strtol.c
+software/new_bsp/iniche/src/misclib/syslog.c
+software/new_bsp/iniche/src/misclib/task.c
+software/new_bsp/iniche/src/misclib/tcpcksum.c
+software/new_bsp/iniche/src/misclib/tcp_echo.c
+software/new_bsp/iniche/src/misclib/testmenu.c
+software/new_bsp/iniche/src/misclib/tk_crnos.c
+software/new_bsp/iniche/src/misclib/ttyio.c
+software/new_bsp/iniche/src/misclib/udp_echo.c
+software/new_bsp/iniche/src/misclib/userpass.c
+software/new_bsp/iniche/src/net/dhcpclnt.c
+software/new_bsp/iniche/src/net/dhcputil.c
+software/new_bsp/iniche/src/net/dnsclnt.c
+software/new_bsp/iniche/src/net/ifmap.c
+software/new_bsp/iniche/src/net/macloop.c
+software/new_bsp/iniche/src/net/ping.c
+software/new_bsp/iniche/src/net/pktalloc.c
+software/new_bsp/iniche/src/net/q.c
+software/new_bsp/iniche/src/net/slip.c
+software/new_bsp/iniche/src/net/slipif.c
+software/new_bsp/iniche/src/net/udp_open.c
+software/new_bsp/iniche/src/net/heapbuf.h
+software/new_bsp/iniche/src/net/slip.h
+software/new_bsp/iniche/src/net/slipport.h
+software/new_bsp/iniche/src/nios2/brdutils.c
+software/new_bsp/iniche/src/nios2/osportco.c
+software/new_bsp/iniche/src/nios2/targnios.c
+software/new_bsp/iniche/src/nios2/asm_cksum.S
+software/new_bsp/iniche/src/nios2/osport.h
+software/new_bsp/iniche/src/nios2/uart.h
+software/new_bsp/iniche/src/tcp/in_pcb.c
+software/new_bsp/iniche/src/tcp/nptcp.c
+software/new_bsp/iniche/src/tcp/rawsock.c
+software/new_bsp/iniche/src/tcp/sockcall.c
+software/new_bsp/iniche/src/tcp/socket.c
+software/new_bsp/iniche/src/tcp/socket2.c
+software/new_bsp/iniche/src/tcp/soselect.c
+software/new_bsp/iniche/src/tcp/tcp_in.c
+software/new_bsp/iniche/src/tcp/tcp_menu.c
+software/new_bsp/iniche/src/tcp/tcp_out.c
+software/new_bsp/iniche/src/tcp/tcpport.c
+software/new_bsp/iniche/src/tcp/tcpsack.c
+software/new_bsp/iniche/src/tcp/tcp_subr.c
+software/new_bsp/iniche/src/tcp/tcp_timr.c
+software/new_bsp/iniche/src/tcp/tcp_usr.c
+software/new_bsp/iniche/src/tcp/tcp_zio.c
+software/new_bsp/iniche/src/tcp/udpsock.c
+software/new_bsp/iniche/src/tcp/in_pcb.h
+software/new_bsp/iniche/src/tcp/protosw.h
+software/new_bsp/iniche/src/tcp/tcp_fsm.h
+software/new_bsp/iniche/src/tcp/tcpip.h
+software/new_bsp/iniche/src/tcp/tcp_seq.h
+software/new_bsp/iniche/src/tcp/tcp_timr.h
+software/new_bsp/iniche/src/tcp/tcp_var.h
+software/new_bsp/iniche/src/telnet/telerr.c
+software/new_bsp/iniche/src/telnet/telparse.c
+software/new_bsp/iniche/src/telnet/telmenu.c
+software/new_bsp/iniche/src/telnet/telport.c
+software/new_bsp/iniche/src/telnet/telnet.c
+software/new_bsp/iniche/src/telnet/telnet.h
+software/new_bsp/iniche/src/telnet/telport.h
+software/new_bsp/iniche/src/tftp/tftpcli.c
+software/new_bsp/iniche/src/tftp/tftpsrv.c
+software/new_bsp/iniche/src/tftp/tftpmenu.c
+software/new_bsp/iniche/src/tftp/tftpudp.c
+software/new_bsp/iniche/src/tftp/tftpport.c
+software/new_bsp/iniche/src/tftp/tftputil.c
+software/new_bsp/iniche/src/tftp/tftp.h
+software/new_bsp/iniche/src/tftp/tftpport.h
+software/new_bsp/iniche/src/vfs/vfsfiles.c
+software/new_bsp/iniche/src/vfs/vfsport.c
+software/new_bsp/iniche/src/vfs/vfssync.c
+software/new_bsp/iniche/src/vfs/vfsutil.c
+software/new_bsp/iniche/src/vfs/vfsport.h
+software/new_bsp/iniche/src/h/app_ping.h
+software/new_bsp/iniche/src/h/arp.h
+software/new_bsp/iniche/src/h/bsdsock.h
+software/new_bsp/iniche/src/h/comline.h
+software/new_bsp/iniche/src/h/crypt_api.h
+software/new_bsp/iniche/src/h/crypt_port.h
+software/new_bsp/iniche/src/h/dhcpclnt.h
+software/new_bsp/iniche/src/h/dns.h
+software/new_bsp/iniche/src/h/dnsport.h
+software/new_bsp/iniche/src/h/ether.h
+software/new_bsp/iniche/src/h/genlist.h
+software/new_bsp/iniche/src/h/htcmptab.h
+software/new_bsp/iniche/src/h/icmp.h
+software/new_bsp/iniche/src/h/ifmap.h
+software/new_bsp/iniche/src/h/iniche_log.h
+software/new_bsp/iniche/src/h/iniche_log_port.h
+software/new_bsp/iniche/src/h/intimers.h
+software/new_bsp/iniche/src/h/in_utils.h
+software/new_bsp/iniche/src/h/ip.h
+software/new_bsp/iniche/src/h/ip6.h
+software/new_bsp/iniche/src/h/libport.h
+software/new_bsp/iniche/src/h/mbuf.h
+software/new_bsp/iniche/src/h/memwrap.h
+software/new_bsp/iniche/src/h/menu.h
+software/new_bsp/iniche/src/h/msring.h
+software/new_bsp/iniche/src/h/nameser.h
+software/new_bsp/iniche/src/h/net.h
+software/new_bsp/iniche/src/h/netbuf.h
+software/new_bsp/iniche/src/h/nptcp.h
+software/new_bsp/iniche/src/h/nptypes.h
+software/new_bsp/iniche/src/h/ns.h
+software/new_bsp/iniche/src/h/ns_debug.h
+software/new_bsp/iniche/src/h/nvfsio.h
+software/new_bsp/iniche/src/h/nvparms.h
+software/new_bsp/iniche/src/h/pmtu.h
+software/new_bsp/iniche/src/h/ppp_port.h
+software/new_bsp/iniche/src/h/profiler.h
+software/new_bsp/iniche/src/h/q.h
+software/new_bsp/iniche/src/h/snmpport.h
+software/new_bsp/iniche/src/h/snmp_vie.h
+software/new_bsp/iniche/src/h/sockcall.h
+software/new_bsp/iniche/src/h/socket.h
+software/new_bsp/iniche/src/h/socket6.h
+software/new_bsp/iniche/src/h/sockvar.h
+software/new_bsp/iniche/src/h/syslog.h
+software/new_bsp/iniche/src/h/task.h
+software/new_bsp/iniche/src/h/tcp.h
+software/new_bsp/iniche/src/h/tcpapp.h
+software/new_bsp/iniche/src/h/tcpport.h
+software/new_bsp/iniche/src/h/tk_crnos.h
+software/new_bsp/iniche/src/h/tk_ntask.h
+software/new_bsp/iniche/src/h/udp.h
+software/new_bsp/iniche/src/h/userpass.h
+software/new_bsp/iniche/src/h/vfsfiles.h
+software/new_bsp/iniche/src/h/webport.h
+software/new_bsp/iniche/src/h/nios2/ipport.h
+software/new_bsp/iniche/inc/alt_iniche_dev.h
+software/new_bsp/iniche/inc/os/alt_syscall.h
+software/new_bsp/system.h
+software/new_bsp/alt_sys_init.c
+software/new_bsp/public.mk
+software/new_bsp/mem_init.mk
+software/new_bsp/linker.x
+software/new_bsp/linker.h
+software/new_bsp/memory.gdb
+software/new_bsp/Makefile
+software/new_bsp/.project
+software/new_bsp/.cproject
+software/new_bsp/.settings/language.settings.xml
+software/new_bsp/obj/HAL/src/alt_alarm_start.o
+software/new_bsp/obj/HAL/src/alt_alarm_start.d
+software/new_bsp/obj/HAL/src/alt_busy_sleep.o
+software/new_bsp/obj/HAL/src/alt_busy_sleep.d
+software/new_bsp/obj/HAL/src/alt_close.o
+software/new_bsp/obj/HAL/src/alt_close.d
+software/new_bsp/obj/HAL/src/alt_dcache_flush.o
+software/new_bsp/obj/HAL/src/alt_dcache_flush.d
+software/new_bsp/obj/HAL/src/alt_dcache_flush_all.o
+software/new_bsp/obj/HAL/src/alt_dcache_flush_all.d
+software/new_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o
+software/new_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d
+software/new_bsp/obj/HAL/src/alt_dev.o
+software/new_bsp/obj/HAL/src/alt_dev.d
+software/new_bsp/obj/HAL/src/alt_dev_llist_insert.o
+software/new_bsp/obj/HAL/src/alt_dev_llist_insert.d
+software/new_bsp/obj/HAL/src/alt_dma_rxchan_open.o
+software/new_bsp/obj/HAL/src/alt_dma_rxchan_open.d
+software/new_bsp/obj/HAL/src/alt_dma_txchan_open.o
+software/new_bsp/obj/HAL/src/alt_dma_txchan_open.d
+software/new_bsp/obj/HAL/src/alt_do_ctors.o
+software/new_bsp/obj/HAL/src/alt_do_ctors.d
+software/new_bsp/obj/HAL/src/alt_do_dtors.o
+software/new_bsp/obj/HAL/src/alt_do_dtors.d
+software/new_bsp/obj/HAL/src/alt_ecc_fatal_entry.o
+software/new_bsp/obj/HAL/src/alt_ecc_fatal_entry.d
+software/new_bsp/obj/HAL/src/alt_ecc_fatal_exception.o
+software/new_bsp/obj/HAL/src/alt_ecc_fatal_exception.d
+software/new_bsp/obj/HAL/src/alt_environ.o
+software/new_bsp/obj/HAL/src/alt_environ.d
+software/new_bsp/obj/HAL/src/alt_errno.o
+software/new_bsp/obj/HAL/src/alt_errno.d
+software/new_bsp/obj/HAL/src/alt_exception_entry.o
+software/new_bsp/obj/HAL/src/alt_exception_entry.d
+software/new_bsp/obj/HAL/src/alt_exception_muldiv.o
+software/new_bsp/obj/HAL/src/alt_exception_muldiv.d
+software/new_bsp/obj/HAL/src/alt_exception_trap.o
+software/new_bsp/obj/HAL/src/alt_exception_trap.d
+software/new_bsp/obj/HAL/src/alt_execve.o
+software/new_bsp/obj/HAL/src/alt_execve.d
+software/new_bsp/obj/HAL/src/alt_exit.o
+software/new_bsp/obj/HAL/src/alt_exit.d
+software/new_bsp/obj/HAL/src/alt_fcntl.o
+software/new_bsp/obj/HAL/src/alt_fcntl.d
+software/new_bsp/obj/HAL/src/alt_fd_lock.o
+software/new_bsp/obj/HAL/src/alt_fd_lock.d
+software/new_bsp/obj/HAL/src/alt_fd_unlock.o
+software/new_bsp/obj/HAL/src/alt_fd_unlock.d
+software/new_bsp/obj/HAL/src/alt_find_dev.o
+software/new_bsp/obj/HAL/src/alt_find_dev.d
+software/new_bsp/obj/HAL/src/alt_find_file.o
+software/new_bsp/obj/HAL/src/alt_find_file.d
+software/new_bsp/obj/HAL/src/alt_flash_dev.o
+software/new_bsp/obj/HAL/src/alt_flash_dev.d
+software/new_bsp/obj/HAL/src/alt_fork.o
+software/new_bsp/obj/HAL/src/alt_fork.d
+software/new_bsp/obj/HAL/src/alt_fs_reg.o
+software/new_bsp/obj/HAL/src/alt_fs_reg.d
+software/new_bsp/obj/HAL/src/alt_fstat.o
+software/new_bsp/obj/HAL/src/alt_fstat.d
+software/new_bsp/obj/HAL/src/alt_get_fd.o
+software/new_bsp/obj/HAL/src/alt_get_fd.d
+software/new_bsp/obj/HAL/src/alt_getchar.o
+software/new_bsp/obj/HAL/src/alt_getchar.d
+software/new_bsp/obj/HAL/src/alt_getpid.o
+software/new_bsp/obj/HAL/src/alt_getpid.d
+software/new_bsp/obj/HAL/src/alt_gettod.o
+software/new_bsp/obj/HAL/src/alt_gettod.d
+software/new_bsp/obj/HAL/src/alt_gmon.o
+software/new_bsp/obj/HAL/src/alt_gmon.d
+software/new_bsp/obj/HAL/src/alt_icache_flush.o
+software/new_bsp/obj/HAL/src/alt_icache_flush.d
+software/new_bsp/obj/HAL/src/alt_icache_flush_all.o
+software/new_bsp/obj/HAL/src/alt_icache_flush_all.d
+software/new_bsp/obj/HAL/src/alt_iic.o
+software/new_bsp/obj/HAL/src/alt_iic.d
+software/new_bsp/obj/HAL/src/alt_iic_isr_register.o
+software/new_bsp/obj/HAL/src/alt_iic_isr_register.d
+software/new_bsp/obj/HAL/src/alt_instruction_exception_entry.o
+software/new_bsp/obj/HAL/src/alt_instruction_exception_entry.d
+software/new_bsp/obj/HAL/src/alt_instruction_exception_register.o
+software/new_bsp/obj/HAL/src/alt_instruction_exception_register.d
+software/new_bsp/obj/HAL/src/alt_io_redirect.o
+software/new_bsp/obj/HAL/src/alt_io_redirect.d
+software/new_bsp/obj/HAL/src/alt_ioctl.o
+software/new_bsp/obj/HAL/src/alt_ioctl.d
+software/new_bsp/obj/HAL/src/alt_irq_entry.o
+software/new_bsp/obj/HAL/src/alt_irq_entry.d
+software/new_bsp/obj/HAL/src/alt_irq_handler.o
+software/new_bsp/obj/HAL/src/alt_irq_handler.d
+software/new_bsp/obj/HAL/src/alt_irq_register.o
+software/new_bsp/obj/HAL/src/alt_irq_register.d
+software/new_bsp/obj/HAL/src/alt_irq_vars.o
+software/new_bsp/obj/HAL/src/alt_irq_vars.d
+software/new_bsp/obj/HAL/src/alt_isatty.o
+software/new_bsp/obj/HAL/src/alt_isatty.d
+software/new_bsp/obj/HAL/src/alt_kill.o
+software/new_bsp/obj/HAL/src/alt_kill.d
+software/new_bsp/obj/HAL/src/alt_link.o
+software/new_bsp/obj/HAL/src/alt_link.d
+software/new_bsp/obj/HAL/src/alt_load.o
+software/new_bsp/obj/HAL/src/alt_load.d
+software/new_bsp/obj/HAL/src/alt_log_macro.o
+software/new_bsp/obj/HAL/src/alt_log_macro.d
+software/new_bsp/obj/HAL/src/alt_log_printf.o
+software/new_bsp/obj/HAL/src/alt_log_printf.d
+software/new_bsp/obj/HAL/src/alt_lseek.o
+software/new_bsp/obj/HAL/src/alt_lseek.d
+software/new_bsp/obj/HAL/src/alt_main.o
+software/new_bsp/obj/HAL/src/alt_main.d
+software/new_bsp/obj/HAL/src/alt_mcount.o
+software/new_bsp/obj/HAL/src/alt_mcount.d
+software/new_bsp/obj/HAL/src/alt_open.o
+software/new_bsp/obj/HAL/src/alt_open.d
+software/new_bsp/obj/HAL/src/alt_printf.o
+software/new_bsp/obj/HAL/src/alt_printf.d
+software/new_bsp/obj/HAL/src/alt_putchar.o
+software/new_bsp/obj/HAL/src/alt_putchar.d
+software/new_bsp/obj/HAL/src/alt_putstr.o
+software/new_bsp/obj/HAL/src/alt_putstr.d
+software/new_bsp/obj/HAL/src/alt_read.o
+software/new_bsp/obj/HAL/src/alt_read.d
+software/new_bsp/obj/HAL/src/alt_release_fd.o
+software/new_bsp/obj/HAL/src/alt_release_fd.d
+software/new_bsp/obj/HAL/src/alt_remap_cached.o
+software/new_bsp/obj/HAL/src/alt_remap_cached.d
+software/new_bsp/obj/HAL/src/alt_remap_uncached.o
+software/new_bsp/obj/HAL/src/alt_remap_uncached.d
+software/new_bsp/obj/HAL/src/alt_rename.o
+software/new_bsp/obj/HAL/src/alt_rename.d
+software/new_bsp/obj/HAL/src/alt_sbrk.o
+software/new_bsp/obj/HAL/src/alt_sbrk.d
+software/new_bsp/obj/HAL/src/alt_settod.o
+software/new_bsp/obj/HAL/src/alt_settod.d
+software/new_bsp/obj/HAL/src/alt_software_exception.o
+software/new_bsp/obj/HAL/src/alt_software_exception.d
+software/new_bsp/obj/HAL/src/alt_stat.o
+software/new_bsp/obj/HAL/src/alt_stat.d
+software/new_bsp/obj/HAL/src/alt_tick.o
+software/new_bsp/obj/HAL/src/alt_tick.d
+software/new_bsp/obj/HAL/src/alt_times.o
+software/new_bsp/obj/HAL/src/alt_times.d
+software/new_bsp/obj/HAL/src/alt_uncached_free.o
+software/new_bsp/obj/HAL/src/alt_uncached_free.d
+software/new_bsp/obj/HAL/src/alt_uncached_malloc.o
+software/new_bsp/obj/HAL/src/alt_uncached_malloc.d
+software/new_bsp/obj/HAL/src/alt_unlink.o
+software/new_bsp/obj/HAL/src/alt_unlink.d
+software/new_bsp/obj/HAL/src/alt_usleep.o
+software/new_bsp/obj/HAL/src/alt_usleep.d
+software/new_bsp/obj/HAL/src/alt_wait.o
+software/new_bsp/obj/HAL/src/alt_wait.d
+software/new_bsp/obj/HAL/src/alt_write.o
+software/new_bsp/obj/HAL/src/alt_write.d
+software/new_bsp/obj/HAL/src/altera_nios2_gen2_irq.o
+software/new_bsp/obj/HAL/src/altera_nios2_gen2_irq.d
+software/new_bsp/obj/HAL/src/crt0.o
+software/new_bsp/obj/HAL/src/crt0.d
+software/new_bsp/obj/HAL/src/os_cpu_a.o
+software/new_bsp/obj/HAL/src/os_cpu_a.d
+software/new_bsp/obj/HAL/src/os_cpu_c.o
+software/new_bsp/obj/HAL/src/os_cpu_c.d
+software/new_bsp/obj/UCOSII/src/alt_env_lock.o
+software/new_bsp/obj/UCOSII/src/alt_env_lock.d
+software/new_bsp/obj/UCOSII/src/alt_malloc_lock.o
+software/new_bsp/obj/UCOSII/src/alt_malloc_lock.d
+software/new_bsp/obj/UCOSII/src/os_core.o
+software/new_bsp/obj/UCOSII/src/os_core.d
+software/new_bsp/obj/UCOSII/src/os_dbg.o
+software/new_bsp/obj/UCOSII/src/os_dbg.d
+software/new_bsp/obj/UCOSII/src/os_flag.o
+software/new_bsp/obj/UCOSII/src/os_flag.d
+software/new_bsp/obj/UCOSII/src/os_mbox.o
+software/new_bsp/obj/UCOSII/src/os_mbox.d
+software/new_bsp/obj/UCOSII/src/os_mem.o
+software/new_bsp/obj/UCOSII/src/os_mem.d
+software/new_bsp/obj/UCOSII/src/os_mutex.o
+software/new_bsp/obj/UCOSII/src/os_mutex.d
+software/new_bsp/obj/UCOSII/src/os_q.o
+software/new_bsp/obj/UCOSII/src/os_q.d
+software/new_bsp/obj/UCOSII/src/os_sem.o
+software/new_bsp/obj/UCOSII/src/os_sem.d
+software/new_bsp/obj/UCOSII/src/os_task.o
+software/new_bsp/obj/UCOSII/src/os_task.d
+software/new_bsp/obj/UCOSII/src/os_time.o
+software/new_bsp/obj/UCOSII/src/os_time.d
+software/new_bsp/obj/UCOSII/src/os_tmr.o
+software/new_bsp/obj/UCOSII/src/os_tmr.d
+software/new_bsp/obj/alt_sys_init.o
+software/new_bsp/obj/alt_sys_init.d
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o
+software/new_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d
+software/new_bsp/obj/drivers/src/altera_avalon_sgdma.o
+software/new_bsp/obj/drivers/src/altera_avalon_sgdma.d
+software/new_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o
+software/new_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d
+software/new_bsp/obj/drivers/src/altera_avalon_timer_sc.o
+software/new_bsp/obj/drivers/src/altera_avalon_timer_sc.d
+software/new_bsp/obj/drivers/src/altera_avalon_timer_ts.o
+software/new_bsp/obj/drivers/src/altera_avalon_timer_ts.d
+software/new_bsp/obj/drivers/src/altera_avalon_timer_vars.o
+software/new_bsp/obj/drivers/src/altera_avalon_timer_vars.d
+software/new_bsp/obj/drivers/src/altera_avalon_tse.o
+software/new_bsp/obj/drivers/src/altera_avalon_tse.d
+software/new_bsp/obj/drivers/src/altera_avalon_tse_system_info.o
+software/new_bsp/obj/drivers/src/altera_avalon_tse_system_info.d
+software/new_bsp/obj/drivers/src/altera_generic_quad_spi_controller.o
+software/new_bsp/obj/drivers/src/altera_generic_quad_spi_controller.d
+software/new_bsp/obj/drivers/src/iniche/ins_tse_mac.o
+software/new_bsp/obj/drivers/src/iniche/ins_tse_mac.d
+software/new_bsp/obj/iniche/src/allports/allports.o
+software/new_bsp/obj/iniche/src/allports/allports.d
+software/new_bsp/obj/iniche/src/allports/timeouts.o
+software/new_bsp/obj/iniche/src/allports/timeouts.d
+software/new_bsp/obj/iniche/src/allports/tk_misc.o
+software/new_bsp/obj/iniche/src/allports/tk_misc.d
+software/new_bsp/obj/iniche/src/alt_iniche_close.o
+software/new_bsp/obj/iniche/src/alt_iniche_close.d
+software/new_bsp/obj/iniche/src/alt_iniche_dev.o
+software/new_bsp/obj/iniche/src/alt_iniche_dev.d
+software/new_bsp/obj/iniche/src/alt_iniche_fcntl.o
+software/new_bsp/obj/iniche/src/alt_iniche_fcntl.d
+software/new_bsp/obj/iniche/src/alt_iniche_read.o
+software/new_bsp/obj/iniche/src/alt_iniche_read.d
+software/new_bsp/obj/iniche/src/alt_iniche_write.o
+software/new_bsp/obj/iniche/src/alt_iniche_write.d
+software/new_bsp/obj/iniche/src/autoip4/autoip.o
+software/new_bsp/obj/iniche/src/autoip4/autoip.d
+software/new_bsp/obj/iniche/src/autoip4/upnp.o
+software/new_bsp/obj/iniche/src/autoip4/upnp.d
+software/new_bsp/obj/iniche/src/autoip4/upnpmenu.o
+software/new_bsp/obj/iniche/src/autoip4/upnpmenu.d
+software/new_bsp/obj/iniche/src/ftp/ftpclnt.o
+software/new_bsp/obj/iniche/src/ftp/ftpclnt.d
+software/new_bsp/obj/iniche/src/ftp/ftpcport.o
+software/new_bsp/obj/iniche/src/ftp/ftpcport.d
+software/new_bsp/obj/iniche/src/ftp/ftpcprn.o
+software/new_bsp/obj/iniche/src/ftp/ftpcprn.d
+software/new_bsp/obj/iniche/src/ftp/ftpmenu.o
+software/new_bsp/obj/iniche/src/ftp/ftpmenu.d
+software/new_bsp/obj/iniche/src/ftp/ftpsport.o
+software/new_bsp/obj/iniche/src/ftp/ftpsport.d
+software/new_bsp/obj/iniche/src/ftp/ftpsrv.o
+software/new_bsp/obj/iniche/src/ftp/ftpsrv.d
+software/new_bsp/obj/iniche/src/ftp/ftpssock.o
+software/new_bsp/obj/iniche/src/ftp/ftpssock.d
+software/new_bsp/obj/iniche/src/ftp/ftpsvfs.o
+software/new_bsp/obj/iniche/src/ftp/ftpsvfs.d
+software/new_bsp/obj/iniche/src/ip/et_arp.o
+software/new_bsp/obj/iniche/src/ip/et_arp.d
+software/new_bsp/obj/iniche/src/ip/icmp.o
+software/new_bsp/obj/iniche/src/ip/icmp.d
+software/new_bsp/obj/iniche/src/ip/iface.o
+software/new_bsp/obj/iniche/src/ip/iface.d
+software/new_bsp/obj/iniche/src/ip/ip.o
+software/new_bsp/obj/iniche/src/ip/ip.d
+software/new_bsp/obj/iniche/src/ip/ip_reasm.o
+software/new_bsp/obj/iniche/src/ip/ip_reasm.d
+software/new_bsp/obj/iniche/src/ip/ipdemux.o
+software/new_bsp/obj/iniche/src/ip/ipdemux.d
+software/new_bsp/obj/iniche/src/ip/ipmc.o
+software/new_bsp/obj/iniche/src/ip/ipmc.d
+software/new_bsp/obj/iniche/src/ip/ipnet.o
+software/new_bsp/obj/iniche/src/ip/ipnet.d
+software/new_bsp/obj/iniche/src/ip/ipport.o
+software/new_bsp/obj/iniche/src/ip/ipport.d
+software/new_bsp/obj/iniche/src/ip/ipraw.o
+software/new_bsp/obj/iniche/src/ip/ipraw.d
+software/new_bsp/obj/iniche/src/ip/iproute.o
+software/new_bsp/obj/iniche/src/ip/iproute.d
+software/new_bsp/obj/iniche/src/ip/ipstart.o
+software/new_bsp/obj/iniche/src/ip/ipstart.d
+software/new_bsp/obj/iniche/src/ip/pmtu.o
+software/new_bsp/obj/iniche/src/ip/pmtu.d
+software/new_bsp/obj/iniche/src/ip/rtbtree.o
+software/new_bsp/obj/iniche/src/ip/rtbtree.d
+software/new_bsp/obj/iniche/src/ip/udp.o
+software/new_bsp/obj/iniche/src/ip/udp.d
+software/new_bsp/obj/iniche/src/ipmc/igmp.o
+software/new_bsp/obj/iniche/src/ipmc/igmp.d
+software/new_bsp/obj/iniche/src/ipmc/igmp2.o
+software/new_bsp/obj/iniche/src/ipmc/igmp2.d
+software/new_bsp/obj/iniche/src/ipmc/igmp_cmn.o
+software/new_bsp/obj/iniche/src/ipmc/igmp_cmn.d
+software/new_bsp/obj/iniche/src/ipmc/ipopt.o
+software/new_bsp/obj/iniche/src/ipmc/ipopt.d
+software/new_bsp/obj/iniche/src/ipmc/u_mctest.o
+software/new_bsp/obj/iniche/src/ipmc/u_mctest.d
+software/new_bsp/obj/iniche/src/misclib/app_ping.o
+software/new_bsp/obj/iniche/src/misclib/app_ping.d
+software/new_bsp/obj/iniche/src/misclib/bsdsock.o
+software/new_bsp/obj/iniche/src/misclib/bsdsock.d
+software/new_bsp/obj/iniche/src/misclib/cksum.o
+software/new_bsp/obj/iniche/src/misclib/cksum.d
+software/new_bsp/obj/iniche/src/misclib/cu_srv.o
+software/new_bsp/obj/iniche/src/misclib/cu_srv.d
+software/new_bsp/obj/iniche/src/misclib/dhcsetup.o
+software/new_bsp/obj/iniche/src/misclib/dhcsetup.d
+software/new_bsp/obj/iniche/src/misclib/genlist.o
+software/new_bsp/obj/iniche/src/misclib/genlist.d
+software/new_bsp/obj/iniche/src/misclib/in_utils.o
+software/new_bsp/obj/iniche/src/misclib/in_utils.d
+software/new_bsp/obj/iniche/src/misclib/iniche_log.o
+software/new_bsp/obj/iniche/src/misclib/iniche_log.d
+software/new_bsp/obj/iniche/src/misclib/iniche_qsort.o
+software/new_bsp/obj/iniche/src/misclib/iniche_qsort.d
+software/new_bsp/obj/iniche/src/misclib/localtime.o
+software/new_bsp/obj/iniche/src/misclib/localtime.d
+software/new_bsp/obj/iniche/src/misclib/memdev.o
+software/new_bsp/obj/iniche/src/misclib/memdev.d
+software/new_bsp/obj/iniche/src/misclib/memio.o
+software/new_bsp/obj/iniche/src/misclib/memio.d
+software/new_bsp/obj/iniche/src/misclib/memwrap.o
+software/new_bsp/obj/iniche/src/misclib/memwrap.d
+software/new_bsp/obj/iniche/src/misclib/menulib.o
+software/new_bsp/obj/iniche/src/misclib/menulib.d
+software/new_bsp/obj/iniche/src/misclib/menus.o
+software/new_bsp/obj/iniche/src/misclib/menus.d
+software/new_bsp/obj/iniche/src/misclib/msring.o
+software/new_bsp/obj/iniche/src/misclib/msring.d
+software/new_bsp/obj/iniche/src/misclib/netmain.o
+software/new_bsp/obj/iniche/src/misclib/netmain.d
+software/new_bsp/obj/iniche/src/misclib/nextcarg.o
+software/new_bsp/obj/iniche/src/misclib/nextcarg.d
+software/new_bsp/obj/iniche/src/misclib/nrmenus.o
+software/new_bsp/obj/iniche/src/misclib/nrmenus.d
+software/new_bsp/obj/iniche/src/misclib/nvfsio.o
+software/new_bsp/obj/iniche/src/misclib/nvfsio.d
+software/new_bsp/obj/iniche/src/misclib/nvparms.o
+software/new_bsp/obj/iniche/src/misclib/nvparms.d
+software/new_bsp/obj/iniche/src/misclib/parseip.o
+software/new_bsp/obj/iniche/src/misclib/parseip.d
+software/new_bsp/obj/iniche/src/misclib/pcycles.o
+software/new_bsp/obj/iniche/src/misclib/pcycles.d
+software/new_bsp/obj/iniche/src/misclib/profiler.o
+software/new_bsp/obj/iniche/src/misclib/profiler.d
+software/new_bsp/obj/iniche/src/misclib/rawiptst.o
+software/new_bsp/obj/iniche/src/misclib/rawiptst.d
+software/new_bsp/obj/iniche/src/misclib/reshost.o
+software/new_bsp/obj/iniche/src/misclib/reshost.d
+software/new_bsp/obj/iniche/src/misclib/rfsim.o
+software/new_bsp/obj/iniche/src/misclib/rfsim.d
+software/new_bsp/obj/iniche/src/misclib/rttest.o
+software/new_bsp/obj/iniche/src/misclib/rttest.d
+software/new_bsp/obj/iniche/src/misclib/soperr.o
+software/new_bsp/obj/iniche/src/misclib/soperr.d
+software/new_bsp/obj/iniche/src/misclib/strilib.o
+software/new_bsp/obj/iniche/src/misclib/strilib.d
+software/new_bsp/obj/iniche/src/misclib/strlib.o
+software/new_bsp/obj/iniche/src/misclib/strlib.d
+software/new_bsp/obj/iniche/src/misclib/strtol.o
+software/new_bsp/obj/iniche/src/misclib/strtol.d
+software/new_bsp/obj/iniche/src/misclib/syslog.o
+software/new_bsp/obj/iniche/src/misclib/syslog.d
+software/new_bsp/obj/iniche/src/misclib/task.o
+software/new_bsp/obj/iniche/src/misclib/task.d
+software/new_bsp/obj/iniche/src/misclib/tcp_echo.o
+software/new_bsp/obj/iniche/src/misclib/tcp_echo.d
+software/new_bsp/obj/iniche/src/misclib/tcpcksum.o
+software/new_bsp/obj/iniche/src/misclib/tcpcksum.d
+software/new_bsp/obj/iniche/src/misclib/testmenu.o
+software/new_bsp/obj/iniche/src/misclib/testmenu.d
+software/new_bsp/obj/iniche/src/misclib/tk_crnos.o
+software/new_bsp/obj/iniche/src/misclib/tk_crnos.d
+software/new_bsp/obj/iniche/src/misclib/ttyio.o
+software/new_bsp/obj/iniche/src/misclib/ttyio.d
+software/new_bsp/obj/iniche/src/misclib/udp_echo.o
+software/new_bsp/obj/iniche/src/misclib/udp_echo.d
+software/new_bsp/obj/iniche/src/misclib/userpass.o
+software/new_bsp/obj/iniche/src/misclib/userpass.d
+software/new_bsp/obj/iniche/src/net/dhcpclnt.o
+software/new_bsp/obj/iniche/src/net/dhcpclnt.d
+software/new_bsp/obj/iniche/src/net/dhcputil.o
+software/new_bsp/obj/iniche/src/net/dhcputil.d
+software/new_bsp/obj/iniche/src/net/dnsclnt.o
+software/new_bsp/obj/iniche/src/net/dnsclnt.d
+software/new_bsp/obj/iniche/src/net/ifmap.o
+software/new_bsp/obj/iniche/src/net/ifmap.d
+software/new_bsp/obj/iniche/src/net/macloop.o
+software/new_bsp/obj/iniche/src/net/macloop.d
+software/new_bsp/obj/iniche/src/net/ping.o
+software/new_bsp/obj/iniche/src/net/ping.d
+software/new_bsp/obj/iniche/src/net/pktalloc.o
+software/new_bsp/obj/iniche/src/net/pktalloc.d
+software/new_bsp/obj/iniche/src/net/q.o
+software/new_bsp/obj/iniche/src/net/q.d
+software/new_bsp/obj/iniche/src/net/slip.o
+software/new_bsp/obj/iniche/src/net/slip.d
+software/new_bsp/obj/iniche/src/net/slipif.o
+software/new_bsp/obj/iniche/src/net/slipif.d
+software/new_bsp/obj/iniche/src/net/udp_open.o
+software/new_bsp/obj/iniche/src/net/udp_open.d
+software/new_bsp/obj/iniche/src/nios2/asm_cksum.o
+software/new_bsp/obj/iniche/src/nios2/asm_cksum.d
+software/new_bsp/obj/iniche/src/nios2/brdutils.o
+software/new_bsp/obj/iniche/src/nios2/brdutils.d
+software/new_bsp/obj/iniche/src/nios2/osportco.o
+software/new_bsp/obj/iniche/src/nios2/osportco.d
+software/new_bsp/obj/iniche/src/nios2/targnios.o
+software/new_bsp/obj/iniche/src/nios2/targnios.d
+software/new_bsp/obj/iniche/src/tcp/in_pcb.o
+software/new_bsp/obj/iniche/src/tcp/in_pcb.d
+software/new_bsp/obj/iniche/src/tcp/nptcp.o
+software/new_bsp/obj/iniche/src/tcp/nptcp.d
+software/new_bsp/obj/iniche/src/tcp/rawsock.o
+software/new_bsp/obj/iniche/src/tcp/rawsock.d
+software/new_bsp/obj/iniche/src/tcp/sockcall.o
+software/new_bsp/obj/iniche/src/tcp/sockcall.d
+software/new_bsp/obj/iniche/src/tcp/socket.o
+software/new_bsp/obj/iniche/src/tcp/socket.d
+software/new_bsp/obj/iniche/src/tcp/socket2.o
+software/new_bsp/obj/iniche/src/tcp/socket2.d
+software/new_bsp/obj/iniche/src/tcp/soselect.o
+software/new_bsp/obj/iniche/src/tcp/soselect.d
+software/new_bsp/obj/iniche/src/tcp/tcp_in.o
+software/new_bsp/obj/iniche/src/tcp/tcp_in.d
+software/new_bsp/obj/iniche/src/tcp/tcp_menu.o
+software/new_bsp/obj/iniche/src/tcp/tcp_menu.d
+software/new_bsp/obj/iniche/src/tcp/tcp_out.o
+software/new_bsp/obj/iniche/src/tcp/tcp_out.d
+software/new_bsp/obj/iniche/src/tcp/tcp_subr.o
+software/new_bsp/obj/iniche/src/tcp/tcp_subr.d
+software/new_bsp/obj/iniche/src/tcp/tcp_timr.o
+software/new_bsp/obj/iniche/src/tcp/tcp_timr.d
+software/new_bsp/obj/iniche/src/tcp/tcp_usr.o
+software/new_bsp/obj/iniche/src/tcp/tcp_usr.d
+software/new_bsp/obj/iniche/src/tcp/tcp_zio.o
+software/new_bsp/obj/iniche/src/tcp/tcp_zio.d
+software/new_bsp/obj/iniche/src/tcp/tcpport.o
+software/new_bsp/obj/iniche/src/tcp/tcpport.d
+software/new_bsp/obj/iniche/src/tcp/tcpsack.o
+software/new_bsp/obj/iniche/src/tcp/tcpsack.d
+software/new_bsp/obj/iniche/src/tcp/udpsock.o
+software/new_bsp/obj/iniche/src/tcp/udpsock.d
+software/new_bsp/obj/iniche/src/telnet/telerr.o
+software/new_bsp/obj/iniche/src/telnet/telerr.d
+software/new_bsp/obj/iniche/src/telnet/telmenu.o
+software/new_bsp/obj/iniche/src/telnet/telmenu.d
+software/new_bsp/obj/iniche/src/telnet/telnet.o
+software/new_bsp/obj/iniche/src/telnet/telnet.d
+software/new_bsp/obj/iniche/src/telnet/telparse.o
+software/new_bsp/obj/iniche/src/telnet/telparse.d
+software/new_bsp/obj/iniche/src/telnet/telport.o
+software/new_bsp/obj/iniche/src/telnet/telport.d
+software/new_bsp/obj/iniche/src/tftp/tftpcli.o
+software/new_bsp/obj/iniche/src/tftp/tftpcli.d
+software/new_bsp/obj/iniche/src/tftp/tftpmenu.o
+software/new_bsp/obj/iniche/src/tftp/tftpmenu.d
+software/new_bsp/obj/iniche/src/tftp/tftpport.o
+software/new_bsp/obj/iniche/src/tftp/tftpport.d
+software/new_bsp/obj/iniche/src/tftp/tftpsrv.o
+software/new_bsp/obj/iniche/src/tftp/tftpsrv.d
+software/new_bsp/obj/iniche/src/tftp/tftpudp.o
+software/new_bsp/obj/iniche/src/tftp/tftpudp.d
+software/new_bsp/obj/iniche/src/tftp/tftputil.o
+software/new_bsp/obj/iniche/src/tftp/tftputil.d
+software/new_bsp/obj/iniche/src/vfs/vfsfiles.o
+software/new_bsp/obj/iniche/src/vfs/vfsfiles.d
+software/new_bsp/obj/iniche/src/vfs/vfsport.o
+software/new_bsp/obj/iniche/src/vfs/vfsport.d
+software/new_bsp/obj/iniche/src/vfs/vfssync.o
+software/new_bsp/obj/iniche/src/vfs/vfssync.d
+software/new_bsp/obj/iniche/src/vfs/vfsutil.o
+software/new_bsp/obj/iniche/src/vfs/vfsutil.d
+software/new_bsp/libucosii_bsp.a
+software/new/create-this-app
+software/new/.force_relink
+software/new/obj/default/.force_relink
+software/new/obj/default/alt_error_handler.o
+software/new/obj/default/alt_error_handler.d
+software/new/obj/default/iniche_init.o
+software/new/obj/default/iniche_init.d
+software/new/obj/default/led.o
+software/new/obj/default/led.d
+software/new/obj/default/network_utilities.o
+software/new/obj/default/network_utilities.d
+software/new/obj/default/simple_socket_server.o
+software/new/obj/default/simple_socket_server.d
+software/new/obj/default/tse_my_system.o
+software/new/obj/default/tse_my_system.d
+software/new/alt_error_handler.c
+software/new/alt_error_handler.h
+software/new/iniche_init.c
+software/new/led.c
+software/new/network_utilities.c
+software/new/network_utilities.h
+software/new/simple_socket_server.c
+software/new/readme.txt
+software/new/Makefile
+software/new/.project
+software/new/.cproject
+software/new/.settings/language.settings.xml
+software/new/simple_socket_server.h
+software/new/tse_my_system.c
+software/new/new.map
+software/new/new.elf
+software/new/new.objdump
+q_sys_orig/synthesis/q_sys.qip
+q_sys.sopcinfo
+clkctrl.qsys
+clkctrl.sopcinfo
+rgmii_sdc/rgmii_clocks.sdc
+rgmii_sdc/rgmii_input.sdc
+rgmii_sdc/rgmii_output.sdc
+rgmii_sdc/software/.metadata/.lock
+rgmii_sdc/software/.metadata/version.ini
+rgmii_sdc/software/.metadata/.log
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.markers.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.syncinfo.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server_bsp/.markers.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server_bsp/.syncinfo.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server_bsp/.indexes/properties.index
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server/.markers.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server/.syncinfo.snap
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.projects/niosII_simple_socket_server/.indexes/properties.index
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/32/7021a664ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/b0/606ba864ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/b0/20b1ac64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/10/2040aa64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/b4/7003ab64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/7d/c0c6ab64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/8/5026ad64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/3c/c037ae64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.resources/.history/36/00d4ae64ffff00141671fb438ea93755
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.tasks.ui.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-niosII_simple_socket_server_bsp.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-niosII_simple_socket_server.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml
+rgmii_sdc/software/.metadata/.plugins/org.eclipse.cdt.core/.log
+PLLJ_PLLSPE_INFO.txt
+simulation/modelsim/top_modelsim.xrf
+simulation/modelsim/top.vho
+simulation/modelsim/top.sft
diff --git a/FPGA_firmware/hit20v3.qpf b/FPGA_firmware/hit20v3.qpf
new file mode 100644
index 0000000..6c7ba4b
--- /dev/null
+++ b/FPGA_firmware/hit20v3.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 13:50:14  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.0"
+DATE = "13:50:14  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "hit20v3"
diff --git a/FPGA_firmware/hit20v3.qsf b/FPGA_firmware/hit20v3.qsf
new file mode 100644
index 0000000..f8f3285
--- /dev/null
+++ b/FPGA_firmware/hit20v3.qsf
@@ -0,0 +1,668 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 13:50:14  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		hit20v3_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C6GES
+set_global_assignment -name TOP_LEVEL_ENTITY m10_rgmii
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:12  JUNE 15, 2015"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_location_assignment PIN_M9 -to clk_50_max10
+set_location_assignment PIN_D9 -to fpga_resetn
+set_location_assignment PIN_T20 -to user_led[0]
+set_location_assignment PIN_U22 -to user_led[1]
+set_location_assignment PIN_U21 -to user_led[2]
+set_location_assignment PIN_AA21 -to user_led[3]
+set_location_assignment PIN_AA22 -to user_led[4]
+set_location_assignment PIN_L22 -to user_pb[0]
+set_location_assignment PIN_M21 -to user_pb[1]
+set_location_assignment PIN_M22 -to user_pb[2]
+set_location_assignment PIN_N21 -to user_pb[3]
+set_location_assignment PIN_H21 -to user_dipsw[0]
+set_location_assignment PIN_H22 -to user_dipsw[1]
+set_location_assignment PIN_J21 -to user_dipsw[2]
+set_location_assignment PIN_J22 -to user_dipsw[3]
+set_location_assignment PIN_G19 -to user_dipsw[4]
+set_location_assignment PIN_B2 -to qspi_clk
+set_location_assignment PIN_C6 -to qspi_io[0]
+set_location_assignment PIN_C3 -to qspi_io[1]
+set_location_assignment PIN_C5 -to qspi_io[2]
+set_location_assignment PIN_B1 -to qspi_io[3]
+set_location_assignment PIN_C2 -to qspi_csn
+set_location_assignment PIN_Y6 -to enet_mdc
+set_location_assignment PIN_Y5 -to enet_mdio
+set_location_assignment PIN_T5 -to enet_gtx_clk
+set_location_assignment PIN_V8 -to enet_resetn
+set_location_assignment PIN_P3 -to enet_rx_clk
+set_location_assignment PIN_N9 -to enet_rx_d[0]
+set_location_assignment PIN_T1 -to enet_rx_d[1]
+set_location_assignment PIN_N1 -to enet_rx_d[2]
+set_location_assignment PIN_T3 -to enet_rx_d[3]
+set_location_assignment PIN_T2 -to enet_rx_dv
+set_location_assignment PIN_E10 -to enet_tx_clk
+set_location_assignment PIN_R5 -to enet_tx_d[0]
+set_location_assignment PIN_P5 -to enet_tx_d[1]
+set_location_assignment PIN_W1 -to enet_tx_d[2]
+set_location_assignment PIN_W2 -to enet_tx_d[3]
+set_location_assignment PIN_R4 -to enet_tx_en
+set_location_assignment PIN_R9 -to enet_led_link100
+set_location_assignment PIN_C22 -to mem_a[13]
+set_location_assignment PIN_J14 -to mem_a[12]
+set_location_assignment PIN_E20 -to mem_a[11]
+set_location_assignment PIN_Y20 -to mem_a[10]
+set_location_assignment PIN_E22 -to mem_a[9]
+set_location_assignment PIN_D22 -to mem_a[8]
+set_location_assignment PIN_B20 -to mem_a[7]
+set_location_assignment PIN_E21 -to mem_a[6]
+set_location_assignment PIN_F19 -to mem_a[5]
+set_location_assignment PIN_C20 -to mem_a[4]
+set_location_assignment PIN_U20 -to mem_a[3]
+set_location_assignment PIN_A21 -to mem_a[2]
+set_location_assignment PIN_D19 -to mem_a[1]
+set_location_assignment PIN_V20 -to mem_a[0]
+set_location_assignment PIN_W22 -to mem_ba[2]
+set_location_assignment PIN_N18 -to mem_ba[1]
+set_location_assignment PIN_V22 -to mem_ba[0]
+set_location_assignment PIN_U19 -to mem_cas_n[0]
+set_location_assignment PIN_D18 -to mem_ck[0]
+set_location_assignment PIN_E18 -to mem_ck_n[0]
+set_location_assignment PIN_W20 -to mem_cke[0]
+set_location_assignment PIN_Y22 -to mem_cs_n[0]
+set_location_assignment PIN_J15 -to mem_dm[0]
+set_location_assignment PIN_K19 -to mem_dq[7]
+set_location_assignment PIN_H20 -to mem_dq[6]
+set_location_assignment PIN_J20 -to mem_dq[5]
+set_location_assignment PIN_H19 -to mem_dq[4]
+set_location_assignment PIN_K18 -to mem_dq[3]
+set_location_assignment PIN_H18 -to mem_dq[2]
+set_location_assignment PIN_K20 -to mem_dq[1]
+set_location_assignment PIN_J18 -to mem_dq[0]
+set_location_assignment PIN_K14 -to mem_dqs[0]
+set_location_assignment PIN_W19 -to mem_odt[0]
+set_location_assignment PIN_V18 -to mem_ras_n[0]
+set_location_assignment PIN_B22 -to mem_reset_n
+set_location_assignment PIN_Y21 -to mem_we_n[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_csn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_tx_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en
+set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_led_link100
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name CKN_CK_PAIR ON -from mem_ck_n[0] -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name DM_PIN ON -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to q_sys_inst|mem_if_ddr3_emif_0 -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name UNIPHY_TEMP_VER_CODE 2133383589
+set_global_assignment -name ECO_REGENERATE_REPORT ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
+set_global_assignment -name MUX_RESTRUCTURE OFF
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE"
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_location_assignment PIN_E9 -to pmoda[7]
+set_location_assignment PIN_A5 -to pmoda[6]
+set_location_assignment PIN_A4 -to pmoda[5]
+set_location_assignment PIN_D8 -to pmoda[4]
+set_location_assignment PIN_B7 -to pmoda[3]
+set_location_assignment PIN_A6 -to pmoda[2]
+set_location_assignment PIN_C8 -to pmoda[1]
+set_location_assignment PIN_C7 -to pmoda[0]
+set_location_assignment PIN_B3 -to pmodb[7]
+set_location_assignment PIN_B4 -to pmodb[6]
+set_location_assignment PIN_A3 -to pmodb[5]
+set_location_assignment PIN_A2 -to pmodb[4]
+set_location_assignment PIN_C4 -to pmodb[3]
+set_location_assignment PIN_B5 -to pmodb[2]
+set_location_assignment PIN_D5 -to pmodb[1]
+set_location_assignment PIN_E8 -to pmodb[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmoda
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pmodb
+set_location_assignment PIN_Y19 -to debug_rxd
+set_location_assignment PIN_W18 -to debug_txd
+set_location_assignment PIN_P12 -to adc_cnv[1]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv[1]
+set_location_assignment PIN_R12 -to "adc_cnv[1](n)"
+set_location_assignment PIN_V16 -to adc_cnv[0]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sck[1]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv[0]
+set_location_assignment PIN_U15 -to "adc_cnv[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to adc_cnv
+set_location_assignment PIN_V12 -to adc_sck[1]
+set_location_assignment PIN_V11 -to "adc_sck[1](n)"
+set_location_assignment PIN_Y14 -to adc_sck[0]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sck[0]
+set_location_assignment PIN_Y13 -to "adc_sck[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sck
+set_location_assignment PIN_AB20 -to adc_sdo[4]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[4]
+set_location_assignment PIN_AB19 -to "adc_sdo[4](n)"
+set_location_assignment PIN_AB11 -to adc_sdo[3]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[3]
+set_location_assignment PIN_AB10 -to "adc_sdo[3](n)"
+set_location_assignment PIN_AB18 -to adc_sdo[2]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[2]
+set_location_assignment PIN_AB17 -to "adc_sdo[2](n)"
+set_location_assignment PIN_Y16 -to adc_sdo[1]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[1]
+set_location_assignment PIN_AA15 -to "adc_sdo[1](n)"
+set_location_assignment PIN_W13 -to adc_sdo[0]
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo[0]
+set_location_assignment PIN_W12 -to "adc_sdo[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to adc_sdo
+set_location_assignment PIN_U7 -to link_dir[3]
+set_instance_assignment -name IO_STANDARD LVDS -to link_dir[3]
+set_location_assignment PIN_U6 -to "link_dir[3](n)"
+set_location_assignment PIN_W8 -to link_dir[2]
+set_instance_assignment -name IO_STANDARD LVDS -to link_dir[2]
+set_location_assignment PIN_W7 -to "link_dir[2](n)"
+set_location_assignment PIN_AA7 -to link_dir[1]
+set_instance_assignment -name IO_STANDARD LVDS -to link_dir[1]
+set_location_assignment PIN_AA6 -to "link_dir[1](n)"
+set_location_assignment PIN_W10 -to link_dir[0]
+set_instance_assignment -name IO_STANDARD LVDS -to link_dir[0]
+set_location_assignment PIN_W9 -to "link_dir[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to link_dir
+set_location_assignment PIN_AB8 -to link_rx[3]
+set_instance_assignment -name IO_STANDARD LVDS -to link_rx[3]
+set_location_assignment PIN_AA8 -to "link_rx[3](n)"
+set_location_assignment PIN_AB9 -to link_rx[2]
+set_instance_assignment -name IO_STANDARD LVDS -to link_rx[2]
+set_location_assignment PIN_AA9 -to "link_rx[2](n)"
+set_location_assignment PIN_AB7 -to link_rx[1]
+set_instance_assignment -name IO_STANDARD LVDS -to link_rx[1]
+set_location_assignment PIN_AB6 -to "link_rx[1](n)"
+set_location_assignment PIN_Y4 -to link_rx[0]
+set_instance_assignment -name IO_STANDARD LVDS -to link_rx[0]
+set_location_assignment PIN_Y3 -to "link_rx[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to link_rx
+set_location_assignment PIN_W3 -to link_tx[3]
+set_instance_assignment -name IO_STANDARD LVDS -to link_tx[3]
+set_location_assignment PIN_W4 -to "link_tx[3](n)"
+set_location_assignment PIN_W6 -to link_tx[2]
+set_instance_assignment -name IO_STANDARD LVDS -to link_tx[2]
+set_location_assignment PIN_W5 -to "link_tx[2](n)"
+set_location_assignment PIN_AA10 -to link_tx[1]
+set_instance_assignment -name IO_STANDARD LVDS -to link_tx[1]
+set_location_assignment PIN_Y10 -to "link_tx[1](n)"
+set_location_assignment PIN_P10 -to link_tx[0]
+set_instance_assignment -name IO_STANDARD LVDS -to link_tx[0]
+set_location_assignment PIN_R10 -to "link_tx[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to link_tx
+set_location_assignment PIN_AA12 -to sensor_clk[1]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk[1]
+set_location_assignment PIN_AA11 -to "sensor_clk[1](n)"
+set_location_assignment PIN_W16 -to sensor_clk[0]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk[0]
+set_location_assignment PIN_V15 -to "sensor_clk[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_clk
+set_location_assignment PIN_Y17 -to sensor_reset[1]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset[1]
+set_location_assignment PIN_AA17 -to "sensor_reset[1](n)"
+set_location_assignment PIN_V17 -to sensor_reset[0]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset[0]
+set_location_assignment PIN_W17 -to "sensor_reset[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_reset
+set_location_assignment PIN_AB13 -to sensor_trig[4]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[4]
+set_location_assignment PIN_AB12 -to "sensor_trig[4](n)"
+set_location_assignment PIN_Y11 -to sensor_trig[3]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[3]
+set_location_assignment PIN_W11 -to "sensor_trig[3](n)"
+set_location_assignment PIN_AA16 -to sensor_trig[2]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[2]
+set_location_assignment PIN_AB16 -to "sensor_trig[2](n)"
+set_location_assignment PIN_AB15 -to sensor_trig[1]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[1]
+set_location_assignment PIN_AA14 -to "sensor_trig[1](n)"
+set_location_assignment PIN_AB5 -to sensor_trig[0]
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig[0]
+set_location_assignment PIN_AA5 -to "sensor_trig[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to sensor_trig
+set_location_assignment PIN_AA1 -to sensor_gainn
+set_location_assignment PIN_AA2 -to sensor_gainp
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sensor_algo_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME sensor_algo_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sensor_algo_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sensor_algo_tb -section_id sensor_algo_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ../dev_room_qlq/algo_dev/testbeanch/sensor_algo_tb.sv -section_id sensor_algo_tb
+set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES ON
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to ddr3_ram_pll_ref_clk_clk
+set_location_assignment PIN_N15 -to "ddr3_ram_pll_ref_clk_clk(n)"
+set_location_assignment PIN_N14 -to ddr3_ram_pll_ref_clk_clk
+set_global_assignment -name VERILOG_FILE debouncer.v
+set_global_assignment -name QIP_FILE software/hit20_v3/mem_init/meminit.qip
+set_global_assignment -name SDC_FILE m10_rgmii.out.sdc
+set_global_assignment -name QIP_FILE enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
+set_global_assignment -name QIP_FILE clkctrl/synthesis/clkctrl.qip
+set_global_assignment -name QIP_FILE q_sys/synthesis/q_sys.qip
+set_global_assignment -name VERILOG_FILE m10_rgmii.v
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to ddr3_ram_pll_ref_clk_clk -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=2" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_MGR_ENTITY=sld_reserved_hit20v3_auto_signaltap_0_flow_mgr_c90c" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=2" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=141" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=21" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=141" -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SLD_FILE db/stp2_auto_stripped.stp
\ No newline at end of file
diff --git a/FPGA_firmware/hit20v3_assignment_defaults.qdf b/FPGA_firmware/hit20v3_assignment_defaults.qdf
new file mode 100644
index 0000000..79a597e
--- /dev/null
+++ b/FPGA_firmware/hit20v3_assignment_defaults.qdf
@@ -0,0 +1,807 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 13:50:18  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/FPGA_firmware/hit20v3_test.out.sdc b/FPGA_firmware/hit20v3_test.out.sdc
new file mode 100644
index 0000000..0e2fc38
--- /dev/null
+++ b/FPGA_firmware/hit20v3_test.out.sdc
@@ -0,0 +1,1145 @@
+## Generated SDC file "hit20v3_test.out.sdc"
+
+## Copyright (C) 2019  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and any partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors.  Please
+## refer to the applicable agreement for further details, at
+## https://fpgasoftware.intel.com/eula.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"
+
+## DATE    "Wed Aug 16 13:45:52 2023"
+
+##
+## DEVICE  "10M50DAF484C6GES"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {altera_reserved_tck} -period 41.667 -waveform { 0.000 20.833 } [get_ports { altera_reserved_tck }]
+create_clock -name {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} -period 181.818 -waveform { 0.000 90.909 } [get_pins {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}]
+create_clock -name {clk_50_max10} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50_max10}]
+create_clock -name {enet_rx_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {enet_rx_clk}]
+create_clock -name {virtual_phy_clk} -period 8.000 -waveform { 0.000 4.000 } 
+create_clock -name {mem_dqs[0]_IN} -period 3.333 -waveform { 0.000 1.667 } [get_ports {mem_dqs[0]}] -add
+create_clock -name {q_sys:q_sys_inst|algo_reconstruction:algo_reconstruction_0|data_in_state.DATA_IN_STATE_FINISH} -period 20.000 -waveform { 0.000 10.000 } 
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 6 -master_clock {clk_50_max10} [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 6 -phase 270/1 -master_clock {clk_50_max10} [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] 
+create_generated_clock -name {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 6 -master_clock {clk_50_max10} [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] 
+create_generated_clock -name {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 6 -phase 270/1 -master_clock {clk_50_max10} [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] 
+create_generated_clock -name {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 3 -master_clock {clk_50_max10} [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] 
+create_generated_clock -name {q_sys_inst|enet_pll|sd1|pll7|clk[0]} -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}] -duty_cycle 50/1 -multiply_by 5 -divide_by 2 -master_clock {clk_50_max10} [get_pins {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] 
+create_generated_clock -name {q_sys_inst|enet_pll|sd1|pll7|clk[1]} -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {clk_50_max10} [get_pins {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] 
+create_generated_clock -name {q_sys_inst|enet_pll|sd1|pll7|clk[2]} -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 20 -master_clock {clk_50_max10} [get_pins {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] 
+create_generated_clock -name {q_sys_inst|enet_pll|sd1|pll7|clk[3]} -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}] -duty_cycle 50/1 -multiply_by 5 -divide_by 2 -phase -135/1 -master_clock {clk_50_max10} [get_pins {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] 
+create_generated_clock -name {q_sys_inst|enet_pll|sd1|pll7|clk[4]} -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -phase -90/1 -master_clock {clk_50_max10} [get_pins {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] 
+create_generated_clock -name {tx_clk_125} -source [get_pins { q_sys_inst|enet_pll|sd1|pll7|clk[3] }] -master_clock {q_sys_inst|enet_pll|sd1|pll7|clk[3]} [get_pins {tx_clk_to_the_tse_mac|combout}] -add
+create_generated_clock -name {tx_clk_25} -source [get_pins { q_sys_inst|enet_pll|sd1|pll7|clk[4] }] -master_clock {q_sys_inst|enet_pll|sd1|pll7|clk[4]} [get_pins {tx_clk_to_the_tse_mac|combout}] -add
+create_generated_clock -name {tx_clk_2p5} -source [get_pins { q_sys_inst|enet_pll|sd1|pll7|clk[2] }] -master_clock {q_sys_inst|enet_pll|sd1|pll7|clk[2]} [get_pins {tx_clk_to_the_tse_mac|combout}] -add
+create_generated_clock -name {enet_gtx_clk_125} -source [get_pins {tx_clk_to_the_tse_mac|combout}] -master_clock {tx_clk_125} [get_ports {enet_gtx_clk}] -add
+create_generated_clock -name {enet_gtx_clk_25} -source [get_pins {tx_clk_to_the_tse_mac|combout}] -master_clock {tx_clk_25} [get_ports {enet_gtx_clk}] -add
+create_generated_clock -name {enet_gtx_clk_2p5} -source [get_pins {tx_clk_to_the_tse_mac|combout}] -master_clock {tx_clk_2p5} [get_ports {enet_gtx_clk}] -add
+create_generated_clock -name {mem_ck[0]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -master_clock {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]} [get_ports {mem_ck[0]}] 
+create_generated_clock -name {mem_ck_n[0]} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -master_clock {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]} -invert [get_ports {mem_ck_n[0]}] 
+create_generated_clock -name {q_sys_inst|ddr3_ram_resync_x2_capture_0} -source [get_pins {q_sys_inst|ddr3_ram|p0|umemphy|dq_ddio[0].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clk}] -divide_by 2 -master_clock {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]} [get_pins {q_sys_inst|ddr3_ram|p0|umemphy|dq_ddio[0].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clkout}] 
+create_generated_clock -name {mem_dqs[0]_OUT} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -master_clock {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]} [get_ports {mem_dqs[0]}] -add
+create_generated_clock -name {mem_dqs_n[0]_OUT} -source [get_pins {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -master_clock {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]} -invert [get_ports {mem_dqs_n[0]}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_25}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_25}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_125}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_125}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_2p5}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_2p5}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {virtual_phy_clk}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {virtual_phy_clk}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_50_max10}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_50_max10}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_rx_clk}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_rx_clk}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_125}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_125}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_25}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_25}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_25}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_25}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_gtx_clk_125}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_gtx_clk_125}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_2p5}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_2p5}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {virtual_phy_clk}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {virtual_phy_clk}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_50_max10}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_50_max10}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {enet_rx_clk}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {enet_rx_clk}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_125}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_125}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {tx_clk_25}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {tx_clk_25}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_2p5}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_25}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_gtx_clk_125}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}]  0.025  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.110  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {tx_clk_2p5}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {tx_clk_2p5}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {enet_gtx_clk_2p5}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {enet_gtx_clk_2p5}]  0.110  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -rise_to [get_clocks {tx_clk_2p5}]  0.030  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_2p5}] -fall_to [get_clocks {tx_clk_2p5}]  0.030  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {clk_50_max10}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {clk_50_max10}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -rise_to [get_clocks {clk_50_max10}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}] -fall_to [get_clocks {clk_50_max10}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {virtual_phy_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {clk_50_max10}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {clk_50_max10}]  0.100  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -setup 0.070  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -hold 0.100  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -setup 0.090  
+set_clock_uncertainty -rise_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[4]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[3]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[2]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {clk_50_max10}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {clk_50_max10}]  0.100  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -setup 0.070  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -hold 0.100  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -rise_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -setup 0.090  
+set_clock_uncertainty -fall_from [get_clocks {clk_50_max10}] -fall_to [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {clk_50_max10}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {clk_50_max10}] -hold 0.070  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {clk_50_max10}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {clk_50_max10}] -hold 0.070  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram_resync_x2_capture_0}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|enet_pll|sd1|pll7|clk[1]}]  0.150  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {clk_50_max10}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {clk_50_max10}] -hold 0.070  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {clk_50_max10}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {clk_50_max10}] -hold 0.070  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -rise_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {enet_rx_clk}] -fall_to [get_clocks {enet_rx_clk}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}] -setup 0.130  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}] -hold 0.140  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}] -setup 0.130  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}] -hold 0.140  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {tx_clk_125}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {tx_clk_125}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}] -setup 0.130  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {enet_gtx_clk_125}] -hold 0.140  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}] -setup 0.130  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {enet_gtx_clk_125}] -hold 0.140  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -rise_to [get_clocks {tx_clk_125}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_125}] -fall_to [get_clocks {tx_clk_125}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}] -setup 0.130  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}] -hold 0.140  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}] -setup 0.130  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}] -hold 0.140  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {tx_clk_25}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {tx_clk_25}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}] -setup 0.130  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {enet_gtx_clk_25}] -hold 0.140  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}] -setup 0.130  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {enet_gtx_clk_25}] -hold 0.140  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -rise_to [get_clocks {tx_clk_25}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {tx_clk_25}] -fall_to [get_clocks {tx_clk_25}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.010  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[1]}]  0.010  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {clk_50_max10}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {clk_50_max10}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {clk_50_max10}] -setup 0.060  
+set_clock_uncertainty -rise_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {clk_50_max10}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {clk_50_max10}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -rise_to [get_clocks {clk_50_max10}] -hold 0.090  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {clk_50_max10}] -setup 0.060  
+set_clock_uncertainty -fall_from [get_clocks {q_sys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] -fall_to [get_clocks {clk_50_max10}] -hold 0.090  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {altera_reserved_tck}]  5.000 [get_ports {altera_reserved_tdi}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {altera_reserved_tck}]  5.000 [get_ports {altera_reserved_tms}]
+set_input_delay -add_delay  -clock [get_clocks {clk_50_max10}]  2.000 [get_ports {enet_mdio}]
+set_input_delay -add_delay -max -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[0]}]
+set_input_delay -add_delay -min -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[0]}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[0]}]
+set_input_delay -add_delay -min -clock_fall -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[0]}]
+set_input_delay -add_delay -max -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[1]}]
+set_input_delay -add_delay -min -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[1]}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[1]}]
+set_input_delay -add_delay -min -clock_fall -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[1]}]
+set_input_delay -add_delay -max -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[2]}]
+set_input_delay -add_delay -min -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[2]}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[2]}]
+set_input_delay -add_delay -min -clock_fall -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[2]}]
+set_input_delay -add_delay -max -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[3]}]
+set_input_delay -add_delay -min -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[3]}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_d[3]}]
+set_input_delay -add_delay -min -clock_fall -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_d[3]}]
+set_input_delay -add_delay -max -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_dv}]
+set_input_delay -add_delay -min -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_dv}]
+set_input_delay -add_delay -max -clock_fall -clock [get_clocks {virtual_phy_clk}]  1.600 [get_ports {enet_rx_dv}]
+set_input_delay -add_delay -min -clock_fall -clock [get_clocks {virtual_phy_clk}]  -0.800 [get_ports {enet_rx_dv}]
+set_input_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  10.000 [get_ports {qspi_io[0]}]
+set_input_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  10.000 [get_ports {qspi_io[1]}]
+set_input_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  10.000 [get_ports {qspi_io[2]}]
+set_input_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  10.000 [get_ports {qspi_io[3]}]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock [get_clocks {altera_reserved_tck}]  5.000 [get_ports {altera_reserved_tdo}]
+set_output_delay -add_delay  -clock [get_clocks {clk_50_max10}]  2.000 [get_ports {enet_mdc}]
+set_output_delay -add_delay  -clock [get_clocks {clk_50_max10}]  2.000 [get_ports {enet_mdio}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_d[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_2p5}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_25}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  1.000 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -min -clock_fall -clock [get_clocks {enet_gtx_clk_125}]  -0.800 [get_ports {enet_tx_en}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[4]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[4]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[5]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[5]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[6]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[6]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[7]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[7]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[8]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[8]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[9]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[9]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[10]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[10]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[11]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[11]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[12]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[12]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_a[13]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_a[13]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_ba[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_ba[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_ba[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_ba[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_ba[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_ba[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_cas_n[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_cas_n[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_cke[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_cke[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_cs_n[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_cs_n[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dm[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dm[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dm[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dm[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[1]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[1]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[2]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[2]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[3]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[3]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[4]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[4]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[4]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[4]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[5]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[5]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[5]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[5]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[6]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[6]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[6]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[6]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.368 [get_ports {mem_dq[7]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.406 [get_ports {mem_dq[7]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.368 [get_ports {mem_dq[7]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.406 [get_ports {mem_dq[7]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  1.510 [get_ports {mem_dqs[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.756 [get_ports {mem_dqs[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_odt[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_odt[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_ras_n[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_ras_n[0]}]
+set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.561 [get_ports {mem_we_n[0]}]
+set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.585 [get_ports {mem_we_n[0]}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_clk}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_csn}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_io[0]}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_io[1]}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_io[2]}]
+set_output_delay -add_delay -rise -min -clock [get_clocks {clk_50_max10}]  11.000 [get_ports {qspi_io[3]}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+set_clock_groups -exclusive -group [get_clocks {tx_clk_125}] -group [get_clocks {tx_clk_25}] -group [get_clocks {tx_clk_2p5}] 
+set_clock_groups -exclusive -group [get_clocks {tx_clk_125}] -group [get_clocks {enet_gtx_clk_25 enet_gtx_clk_2p5}] 
+set_clock_groups -exclusive -group [get_clocks {tx_clk_25}] -group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_2p5}] 
+set_clock_groups -exclusive -group [get_clocks {tx_clk_2p5}] -group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25}] 
+set_clock_groups -exclusive -group [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] -group [get_clocks {enet_rx_clk}] -group [get_clocks {clk_50_max10}] 
+set_clock_groups -logically_exclusive -group [get_clocks {clk_50_max10 q_sys:q_sys_inst|algo_reconstruction:algo_reconstruction_0|data_in_state.DATA_IN_STATE_FINISH}] 
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -setup -rise_from  [get_clocks {virtual_phy_clk}]  -fall_to  [get_clocks {enet_rx_clk}]
+set_false_path -setup -fall_from  [get_clocks {virtual_phy_clk}]  -rise_to  [get_clocks {enet_rx_clk}]
+set_false_path -hold -rise_from  [get_clocks {virtual_phy_clk}]  -rise_to  [get_clocks {enet_rx_clk}]
+set_false_path -hold -fall_from  [get_clocks {virtual_phy_clk}]  -fall_to  [get_clocks {enet_rx_clk}]
+set_false_path -setup -rise_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -fall_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+set_false_path -setup -fall_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -rise_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+set_false_path -hold -rise_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -rise_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+set_false_path -hold -fall_from  [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}]  -fall_to  [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
+set_false_path -to [get_keepers {*phasedone_state*}]
+set_false_path -to [get_keepers {*internal_phasestep*}]
+set_false_path -to [get_ports {enet_gtx_clk}]
+set_false_path -from [get_ports {fpga_resetn}] 
+set_false_path -from [get_ports {user_dipsw[*]}] 
+set_false_path -from [get_ports {user_pb[*]}] 
+set_false_path -to [get_ports {user_led[*]}]
+set_false_path -to [get_ports {enet_resetn}]
+set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]
+set_false_path -to [get_registers {*|flash_busy_reg}]
+set_false_path -to [get_registers {*|flash_busy_clear_reg}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[9]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|frm_length[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+set_false_path -to [get_pins -nocase -compatibility_mode {*|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn}]
+set_false_path -fall_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -to [get_ports {{mem_dqs[0]}}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[0]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[1]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[2]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[3]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[4]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[5]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[6]}]
+set_false_path -from [get_registers {*dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*}] -to [get_ports {mem_dq[7]}]
+set_false_path -rise_from [get_clocks {q_sys_inst|ddr3_ram|pll0|upll_memphy|auto_generated|pll1|clk[0]}] -to [get_ports {{mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[13]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} {mem_cs_n[0]} {mem_we_n[0]} {mem_ras_n[0]} {mem_cas_n[0]} {mem_cke[0]} {mem_odt[0]}}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_oci_break:the_q_sys_cpu_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr*}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_oci_debug:the_q_sys_cpu_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr[33]}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_oci_debug:the_q_sys_cpu_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr[0]}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_oci_debug:the_q_sys_cpu_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr[34]}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_ocimem:the_q_sys_cpu_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr*}]
+set_false_path -from [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck|*sr*}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_sysclk:the_q_sys_cpu_cpu_debug_slave_sysclk|*jdo*}]
+set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper|q_sys_cpu_cpu_debug_slave_sysclk:the_q_sys_cpu_cpu_debug_slave_sysclk|ir*}]
+set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*q_sys_cpu_cpu:*|q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci|q_sys_cpu_cpu_nios2_oci_debug:the_q_sys_cpu_cpu_nios2_oci_debug|monitor_go}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -setup -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*}] -to [get_registers *] 5
+set_multicycle_path -setup -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] -to [get_registers *] 5
+set_multicycle_path -setup -end -from [get_registers *] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] 5
+set_multicycle_path -hold -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*}] -to [get_registers *] 5
+set_multicycle_path -hold -end -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] -to [get_registers *] 5
+set_multicycle_path -hold -end -from [get_registers *] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*}] 5
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+set_max_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] 100.000
+set_max_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers *] -to [get_registers {*altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|out_data_buffer[*]}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_g_ptr_reg[*]}] -to [get_registers {*altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 100.000
+set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
+set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
+set_max_delay -from [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*}] -to [get_registers {*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*}] 7.000
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+set_min_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] -100.000
+set_min_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers *] -to [get_registers {*altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|out_data_buffer[*]}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|in_data_toggle}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|out_data_toggle_flopped}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_g_ptr_reg[*]}] -to [get_registers {*altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+set_min_delay -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] -100.000
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Net Delay
+#**************************************************************
+
+set_net_delay -max 2.000 -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}]
+set_net_delay -max 2.000 -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*|q}] -to [get_registers {*altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_clock_crosser:*|in_data_toggle|q}] -to [get_registers {*altera_tse_clock_crosser:*|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_clock_crosser:*|out_data_toggle_flopped|q}] -to [get_registers {*altera_tse_clock_crosser:*|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1}]
+set_net_delay -max 4.000 -from [get_pins -compatibility_mode {*altera_tse_clock_crosser:*|in_data_buffer[*]|q}] -to [get_registers {*altera_tse_clock_crosser:*|out_data_buffer[*]}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_34:RX_STATUS|wr_g_ptr_reg[*]|q}] -to [get_registers {*altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+set_net_delay -max 6.000 -from [get_pins -compatibility_mode {*altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[*]|q}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}]
+
+
+#**************************************************************
+# Set Max Skew
+#**************************************************************
+
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_convert_addr_tx_clock_crosser|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_clock_crosser:host_data_tx_clock_crosser|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_data_clock_cross|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_rx_counter_cntl:U_RXCNT|altera_tse_clock_crosser:host_convert_addr_clock_cross|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_6|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_7|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_8|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_10|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_11|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_toggle q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|in_data_buffer[*]}] -to [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1 q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_SYNC_12|out_data_buffer[*]}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_g_ptr_reg[*]}] -to [get_registers {*altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_registers {q_sys:q_sys_inst|q_sys_eth_tse:eth_tse|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1*}] 7.500 
+set_max_skew -from [get_ports {mem_dq[0]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[1]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[2]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[3]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[4]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[5]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[6]}] -to * 0.100 
+set_max_skew -from [get_ports {mem_dq[7]}] -to * 0.100 
+set_max_skew -from * -to [get_ports {mem_dqs[0]}] 0.100 
+set_max_skew -from * -to [get_ports {mem_dqs_n[0]}] 0.100 
+set_max_skew -from * -to [get_ports {mem_ck[0]}] 0.100 
+set_max_skew -from * -to [get_ports {mem_ck_n[0]}] 0.100 
+set_max_skew -from * -to [get_ports {mem_reset_n}] 0.100 
diff --git a/FPGA_firmware/m10_rgmii.out.sdc b/FPGA_firmware/m10_rgmii.out.sdc
new file mode 100644
index 0000000..5f6b8ba
--- /dev/null
+++ b/FPGA_firmware/m10_rgmii.out.sdc
@@ -0,0 +1,87 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+# RX clock, 125 MHz - M.D. 2019.10.07
+#create_clock -name enet_rx_clk -period 8.000 [get_ports {enet_rx_clk}]
+
+derive_pll_clocks
+
+# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays
+create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }]
+set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
+
+create_clock -name {clk_50_max10} -period 20.000 {clk_50_max10}
+
+#for DDR3 from CLK_DDR3_100_P
+create_clock -name {ddr3_ram_pll_ref_clk_clk} -period 10.000 {ddr3_ram_pll_ref_clk_clk}
+
+################################ SDC for RGMII interface #################################################
+#set enet_pll_125 { q_sys_inst|enet_pll|sd1|pll7|clk[0] };
+#set enet_pll_25  { q_sys_inst|enet_pll|sd1|pll7|clk[1] };
+#set enet_pll_2p5 { q_sys_inst|enet_pll|sd1|pll7|clk[2] };
+
+set enet_pll_125 { q_sys_inst|enet_pll|sd1|pll7|clk[3] };
+set enet_pll_25  { q_sys_inst|enet_pll|sd1|pll7|clk[4] };
+set enet_pll_2p5 { q_sys_inst|enet_pll|sd1|pll7|clk[2] };
+
+#call sdc files for rgmii interface
+source rgmii_sdc/rgmii_clocks.sdc
+source rgmii_sdc/rgmii_input.sdc
+source rgmii_sdc/rgmii_output.sdc
+
+#
+# Create false paths between clock domains that are not fully constrained by the IP that makes these paths.
+# Ideally we should not have to do this, however, these paths must be cut to meet timing and in most cases
+# the IP should be accounting for synchronization between these paths.
+# The risk of a global cut like these is that if the IP is not synchronizing properly between the two domains
+# then you have significant problems with the design.  Ideally the IP should synchronize it's clock crossing
+# paths and create constraints to cut those paths so we don't have to perform a global cut like this.
+#
+
+set_clock_groups \
+    -exclusive \
+    -group [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+    -group [get_clocks enet_rx_clk] \
+    -group [get_clocks clk_50_max10]
+
+##
+## These are the constraints out of the TSE MAC SDC file that are relevant to us.
+## The TSE MAC SDC file should be commented out by this script.
+##
+#set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+#set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+#set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+#set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+#set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+#set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+#set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+
+#
+#some clock uncertainty is required
+#
+derive_clock_uncertainty
+
+# QSPI interface
+set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_io[*]}]
+set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_clk}]
+set_output_delay -clock { clk_50_max10 } -rise -min 11 [get_ports {qspi_csn}]
+set_input_delay  -clock { clk_50_max10 } -rise -min 10 [get_ports {qspi_io[*]}]
+
+# Ethernet MDIO interface
+set_output_delay  -clock [ get_clocks clk_50_max10 ] 2   [ get_ports {enet_mdc} ]
+set_input_delay   -clock [ get_clocks clk_50_max10 ] 2   [ get_ports {enet_mdio} ]
+set_output_delay  -clock [ get_clocks clk_50_max10 ] 2   [ get_ports {enet_mdio} ]
+
+set_false_path -from [get_ports {fpga_resetn}] 
+set_false_path -from [get_ports {user_dipsw[*]}] 
+set_false_path -from [get_ports {user_pb[*]}] 
+set_false_path -to [get_ports {user_led[*]}]
+set_false_path -to [get_ports {enet_resetn}]
+
+#set_false_path -from * -to {sld_signaltap:auto_signaltap_0|*}
+#set_false_path -from {sld_signaltap:auto_signaltap_0|*} -to *
diff --git a/FPGA_firmware/m10_rgmii.v b/FPGA_firmware/m10_rgmii.v
new file mode 100644
index 0000000..f8bb8b6
--- /dev/null
+++ b/FPGA_firmware/m10_rgmii.v
@@ -0,0 +1,342 @@
+module  m10_rgmii (
+        //Clock and Reset
+        input  wire        clk_50_max10,
+        input  wire        fpga_resetn,
+		  
+
+        //LED PB DIPSW
+        output wire [4:0]  user_led,
+        input  wire [3:0]  user_pb,
+        input  wire [4:0]  user_dipsw,
+
+        //Dual Ethernet
+        output wire        enet_mdc,
+        inout  wire        enet_mdio,	
+        output wire        enet_resetn,	
+        input  wire        enet_rx_clk,
+        input  wire        enet_tx_clk,
+        output wire        enet_gtx_clk,
+        input  wire [3:0]  enet_rx_d,
+        output wire [3:0]  enet_tx_d,
+        output wire        enet_tx_en,
+        input  wire        enet_rx_dv,
+        input  wire        enet_led_link100,
+ 
+		  input  wire        ddr3_ram_pll_ref_clk_clk,                    //                ddr3_ram_pll_ref_clk.clk
+	
+        output wire [13:0] mem_a,
+        output wire [2:0]  mem_ba,
+        inout  wire [0:0]  mem_ck,
+        inout  wire [0:0]  mem_ck_n,
+        output wire [0:0]  mem_cke,
+        output wire [0:0]  mem_cs_n,
+        output wire [0:0]  mem_dm,
+        output wire [0:0]  mem_ras_n,
+        output wire [0:0]  mem_cas_n,
+        output wire [0:0]  mem_we_n,
+        output wire        mem_reset_n,
+        inout  wire [7:0]  mem_dq,
+        inout  wire [0:0]  mem_dqs,
+        inout  wire [0:0]  mem_dqs_n,
+        output wire [0:0]  mem_odt,
+
+        //QSPI
+        output          qspi_clk,
+        inout  [3:0]    qspi_io,
+        output          qspi_csn,
+			
+		//Sensors
+		output wire [1:0] sensor_reset,
+		output wire [1:0] sensor_clk,
+		input  wire [4:0] sensor_trig,
+		output wire [1:0] adc_cnv,
+		output wire [1:0] adc_sck,
+		input  wire [4:0] adc_sdo,
+		output wire	  sensor_gainp,
+		output wire	  sensor_gainn,
+		
+		//Synchro
+		input  wire [3:0] link_rx,
+		output wire [3:0] link_tx,
+		output wire [3:0] link_dir,
+			
+			  
+		  //PMOD
+		input wire  [7:0] pmoda,	//used for 8-fold SMA input;)
+		output wire [7:0] pmodb,
+			  
+	  //USB UART
+	  output wire		  debug_txd,
+	  input wire		  debug_rxd		  
+		  
+        );
+
+//*********************************** Signals *************************************
+	
+//Heart-beat counter
+reg   [25:0]  heart_beat_cnt;
+
+//DDR3 interface assignments
+wire          local_init_done;
+wire          local_cal_success;
+wire          local_cal_fail;
+
+//Ethernet interface assignments
+wire          phy_resetn;
+wire          system_resetn;
+
+wire          mdio_oen_from_the_tse_mac;
+wire          mdio_out_from_the_tse_mac;
+wire          eth_mode_from_the_tse_mac;
+wire          ena_10_from_the_tse_mac;
+wire          enet_tx_125;
+wire          enet_tx_25;
+wire          enet_tx_2p5;
+wire          locked_from_the_enet_pll;
+wire          tx_clk_to_the_tse_mac;
+wire          tx_clk_to_the_tse_mac_g;
+
+wire          enet_tx_125_shift;
+wire          enet_tx_25_shift;
+wire          enet_tx_2p5_shift;
+wire          enet_tx_250_shift; // signaltap sample clock
+wire          locked_from_the_shift_pll;
+wire          tx_clk_to_the_tse_mac_shift;
+wire          tx_clk_to_the_tse_mac_shift_g;
+
+//User interface ;)
+wire [8:0]	user_input;
+wire [7:0]	int_output;
+
+//Sensor interface
+wire        int_sensor_in_trg;                               
+wire        int_sensor_out_adc_clk;
+wire        int_sensor_out_adc_cnv;
+wire [4:0]  int_sensor_in_adc_data;
+wire        int_sensor_out_sensor_rst;
+wire        int_sensor_out_sensor_clk;
+wire        int_sensor_out_sensor_gain;
+wire [7:0]  int_sensor_status;
+
+
+//Trigger stuff
+wire	    int_frame_timer;
+reg	    sym_frame_timer;
+
+//*********************************** Sensor connections *************************************
+
+assign sensor_reset[0] 	= int_sensor_out_sensor_rst;
+assign sensor_reset[1] 	= int_sensor_out_sensor_rst;
+assign sensor_clk[0]	= ~int_sensor_out_sensor_clk;
+assign sensor_clk[1]	= ~int_sensor_out_sensor_clk;
+assign sensor_gainp	= int_sensor_out_sensor_gain;
+assign sensor_gainn	= ~int_sensor_out_sensor_gain;
+assign adc_cnv[0]	= int_sensor_out_adc_cnv;
+assign adc_cnv[1]	= int_sensor_out_adc_cnv;
+assign adc_sck[0]	= ~int_sensor_out_adc_clk;
+assign adc_sck[1]	= ~int_sensor_out_adc_clk;
+assign int_sensor_in_adc_data = adc_sdo;	//all of them are not-inverted :)
+
+
+//*********************************** Frame trigger & synchro routing (master/slave) *************************************
+
+//Synchro pulse is LINK3 (inverted)
+//Global counter transmission is LINK2 (inverted)
+
+wire trig_mode;
+assign trig_mode = int_output[7];
+wire int_synchro_rx;
+wire int_synchro_tx;
+wire int_trig_debouncer_in;
+wire int_ser_debouncer_in;
+
+	//Pulse flip-flop
+always @(posedge int_frame_timer or negedge fpga_resetn)
+begin
+	if (!fpga_resetn)
+		sym_frame_timer <= 0; 
+	else if (trig_mode == 0)
+		sym_frame_timer <= 0;
+	else
+		sym_frame_timer <= ~sym_frame_timer;
+end
+	//Trigger Assignments
+assign link_dir[3]		= trig_mode;		//set link direction according to M/S setting (LED PIO 7)
+assign link_tx[3]		= ~sym_frame_timer;	//connect internal frame trigger to TX
+assign int_trig_debouncer_in 	= trig_mode ? sym_frame_timer : link_rx[3];	//connect either internal or external frame trigger
+
+	//Debouncer for trigger signals - limit trigger bandwidth to 2.5 MHz
+debouncer #(
+	.LENGTH	(10)
+) trig_debouncer (
+	.rst	(!system_resetn),
+	.clk	(clk_50_max10),
+	.in	(int_trig_debouncer_in),
+	.out	(int_sensor_in_trg)
+);
+
+	//Serial assignments
+assign link_dir[2]		= trig_mode;
+assign int_ser_debouncer_in   	= trig_mode ? int_synchro_tx : link_rx[2];
+assign link_tx[2] 		= ~int_synchro_tx;
+
+	//Debouncer for serial RX - limit bandwidth to 2.5 MHz
+debouncer #(
+	.LENGTH	(10)
+) ser_debouncer (
+	.rst	(!system_resetn),
+	.clk	(clk_50_max10),
+	.in	(int_ser_debouncer_in),
+	.out	(int_synchro_rx)
+);
+	
+	
+//*********************************** Various logic *************************************
+
+assign system_resetn = fpga_resetn & local_init_done;
+
+	//PMOD debug lines
+assign pmodb[0] 	= int_trig_debouncer_in;
+assign pmodb[1] 	= int_sensor_in_trg;
+assign pmodb[7:2] 	= int_sensor_status[5:0];
+
+	//Buttons/switches
+assign user_input[3:0] = user_pb[3:0];
+assign user_input[8:4] = user_dipsw[4:0];
+
+//LED forwarding
+assign user_led[3:0] = ~int_output[3:0];
+	//disable user_led[4] blink with int_output[5]; force user_led[4] with int_output[4]
+assign user_led[4] = ~int_output[4] & (heart_beat_cnt[25] | int_output[5]);	
+	//int_output[6] is used for PHY hard reset
+	//int_output[7] is used for master/slave frame trigger routing
+
+	
+//Heart beat by 50MHz clock
+always @(posedge clk_50_max10 or negedge fpga_resetn)
+  if (!fpga_resetn)
+      heart_beat_cnt <= 26'h0; //0x3FFFFFF
+  else
+      heart_beat_cnt <= heart_beat_cnt + 1'b1;
+
+
+		
+//*********************************** Ethernet *************************************	
+	
+	//PHY power-on reset control
+parameter MSB = 20; // PHY interface: need minimum 10ms delay for POR
+reg [MSB:0] epcount;
+
+always @(posedge clk_50_max10 or negedge fpga_resetn)
+  if (!fpga_resetn)
+      epcount <= MSB + 1'b0;
+  else if (epcount[MSB] == 1'b0)
+      epcount <= epcount + 1;
+  else
+      epcount <= epcount;
+
+assign phy_resetn    = user_pb[0] & !(int_output[6] & epcount[MSB]) & !epcount[MSB-1];		//PHY hard reset by counter, user button or software
+assign enet_resetn   = phy_resetn;
+
+//MDIO output control
+assign enet_mdio = ( !mdio_oen_from_the_tse_mac ) ? ( mdio_out_from_the_tse_mac ) : ( 1'bz );
+
+assign enet_tx_2p5_shift = !enet_tx_2p5;
+
+//RGMII clock solution
+assign tx_clk_to_the_tse_mac = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125 ) :  // GbE Mode = 125MHz clock
+                               ( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5 ) :    // 10Mb Mode = 2.5MHz clock
+                               ( enet_tx_25 );                                    // 100Mb Mode = 25MHz clock
+
+assign tx_clk_to_the_tse_mac_shift = ( eth_mode_from_the_tse_mac ) ? ( enet_tx_125_shift ) :  // GbE Mode = 125MHz clock
+                                     ( ena_10_from_the_tse_mac ) ? ( enet_tx_2p5_shift ) :    // 10Mb Mode = 2.5MHz clock
+                                     ( enet_tx_25_shift);                                     // 100Mb Mode = 25MHz clock
+
+clkctrl             clkctrl_inst0 (
+                    .inclk        (tx_clk_to_the_tse_mac  ),
+                    .outclk       (tx_clk_to_the_tse_mac_g)
+                    );
+
+clkctrl             clkctrl_inst1 (
+                    .inclk        (tx_clk_to_the_tse_mac_shift  ),
+                    .outclk       (tx_clk_to_the_tse_mac_shift_g)
+                    );
+
+enet_gtx_clk_ddio   enet_gtx_clk_ddio_inst (
+                    .outclock              (tx_clk_to_the_tse_mac_shift_g), // tx_clk_to_the_tse_mac_g ),
+                    .din                   (2'b10                        ),
+                    .pad_out               (enet_gtx_clk                 ),
+                    .aclr                  (!phy_resetn                  )
+                    );
+
+		    
+//*********************************** Main QSYS *************************************
+		    
+q_sys               q_sys_inst (
+                    .sys_clk_clk                                                   (clk_50_max10              ), //                             sys_clk.clk
+                    .reset_reset_n                                                 (system_resetn             ), //                               reset.reset_n
+                    .mem_resetn_in_reset_reset_n                                   (fpga_resetn               ), //                 mem_resetn_in_reset.reset_n
+                    .altpll_shift_c0_clk                                           (enet_tx_250_shift         ), //                     altpll_shift_c0.clk
+                    .altpll_shift_locked_conduit_export                            (locked_from_the_shift_pll ), //         altpll_shift_locked_conduit.export
+                    .clock_bridge_0_in_clk_clk                                     (enet_tx_25                ), //               clock_bridge_0_in_clk.clk
+                    .enet_pll_c0_clk                                               (enet_tx_125               ), //                         enet_pll_c0.clk
+                    .enet_pll_c1_clk                                               (enet_tx_25                ), //                         enet_pll_c1.clk
+                    .enet_pll_c2_clk                                               (enet_tx_2p5               ), //                         enet_pll_c2.clk
+                    .enet_pll_c3_clk                                               (enet_tx_125_shift         ), //                         enet_pll_c3.clk
+                    .enet_pll_c4_clk                                               (enet_tx_25_shift          ), //                         enet_pll_c4.clk
+                    .enet_pll_locked_conduit_export                                (locked_from_the_enet_pll  ), //             enet_pll_locked_conduit.export
+                    .eth_tse_mac_mdio_connection_mdc                               (enet_mdc                  ), //         eth_tse_mac_mdio_connection.mdc
+                    .eth_tse_mac_mdio_connection_mdio_in                           (enet_mdio                 ), //                                    .mdio_in
+                    .eth_tse_mac_mdio_connection_mdio_out                          (mdio_out_from_the_tse_mac ), //                                    .mdio_out
+                    .eth_tse_mac_mdio_connection_mdio_oen                          (mdio_oen_from_the_tse_mac ), //                                    .mdio_oen
+                    .eth_tse_mac_rgmii_connection_rgmii_in                         (enet_rx_d                 ), //        eth_tse_mac_rgmii_connection.rgmii_in
+                    .eth_tse_mac_rgmii_connection_rgmii_out                        (enet_tx_d                 ), //                                    .rgmii_out
+                    .eth_tse_mac_rgmii_connection_rx_control                       (enet_rx_dv                ), //                                    .rx_control
+                    .eth_tse_mac_rgmii_connection_tx_control                       (enet_tx_en                ), //                                    .tx_control
+                    .eth_tse_mac_status_connection_set_10                          (                          ), //       eth_tse_mac_status_connection.set_10
+                    .eth_tse_mac_status_connection_set_1000                        (                          ), //                                    .set_1000
+                    .eth_tse_mac_status_connection_eth_mode                        (eth_mode_from_the_tse_mac ), //                                    .eth_mode
+                    .eth_tse_mac_status_connection_ena_10                          (ena_10_from_the_tse_mac   ), //                                    .ena_10
+                    .eth_tse_pcs_mac_rx_clock_connection_clk                       (enet_rx_clk               ), // eth_tse_pcs_mac_rx_clock_connection.clk
+                    .eth_tse_pcs_mac_tx_clock_connection_clk                       (tx_clk_to_the_tse_mac_g   ), // eth_tse_pcs_mac_tx_clock_connection.clk
+                    .ext_flash_flash_dataout_conduit_dataout                       (qspi_io                   ), //             ext_flash_flash_dataout.conduit_dataout
+                    .ext_flash_flash_dclk_out_conduit_dclk_out                     (qspi_clk                  ), //            ext_flash_flash_dclk_out.conduit_dclk_out
+                    .ext_flash_flash_ncs_conduit_ncs                               (qspi_csn                  ), //                 ext_flash_flash_ncs.conduit_ncs
+						  .ddr3_ram_pll_ref_clk_clk												  (ddr3_ram_pll_ref_clk_clk ),
+                    .memory_mem_a                                                  (mem_a                     ), //                              memory.mem_a
+                    .memory_mem_ba                                                 (mem_ba                    ), //                                    .mem_ba
+                    .memory_mem_ck                                                 (mem_ck                    ), //                                    .mem_ck
+                    .memory_mem_ck_n                                               (mem_ck_n                  ), //                                    .mem_ck_n
+                    .memory_mem_cke                                                (mem_cke                   ), //                                    .mem_cke
+                    .memory_mem_cs_n                                               (mem_cs_n                  ), //                                    .mem_cs_n
+                    .memory_mem_dm                                                 (mem_dm                    ), //                                    .mem_dm
+                    .memory_mem_ras_n                                              (mem_ras_n                 ), //                                    .mem_ras_n
+                    .memory_mem_cas_n                                              (mem_cas_n                 ), //                                    .mem_cas_n
+                    .memory_mem_we_n                                               (mem_we_n                  ), //                                    .mem_we_n
+                    .memory_mem_reset_n                                            (mem_reset_n               ), //                                    .mem_reset_n
+                    .memory_mem_dq                                                 (mem_dq                    ), //                                    .mem_dq
+                    .memory_mem_dqs                                                (mem_dqs                   ), //                                    .mem_dqs
+                    .memory_mem_dqs_n                                              (mem_dqs_n                 ), //                                    .mem_dqs_n
+                    .memory_mem_odt                                                (mem_odt                   ), //                                    .mem_odt
+                    .led_pio_external_connection_export                            (int_output[7:0]              ), //         led_pio_external_connection.export
+                    .mem_if_ddr3_emif_0_status_local_init_done                     (local_init_done           ), //           mem_if_ddr3_emif_0_status.local_init_done
+                    .mem_if_ddr3_emif_0_status_local_cal_success                   (local_cal_success         ), //                                    .local_cal_success
+                    .mem_if_ddr3_emif_0_status_local_cal_fail                      (local_cal_fail            ), //                                    .local_cal_fail
+                    .button_pio_external_connection_export			   (user_input	  	      ), //
+		    .debug_uart_external_connection_rxd         		   (debug_rxd		      ), //      
+		    .debug_uart_external_connection_txd         		   (debug_txd		      ), //
+		    .sensor_in_trg 						   (int_sensor_in_trg	      ),                               
+		    .sensor_out_adc_clk 					   (int_sensor_out_adc_clk    ),
+		    .sensor_out_adc_cnv 					   (int_sensor_out_adc_cnv    ),
+		    .sensor_in_adc_data 					   (int_sensor_in_adc_data    ),
+		    .sensor_out_sensor_rst 					   (int_sensor_out_sensor_rst ),
+		    .sensor_out_sensor_clk  					   (int_sensor_out_sensor_clk ),
+		    .sensor_out_sensor_gain 					   (int_sensor_out_sensor_gain),
+		    .frame_timer_export						   (int_frame_timer),
+		    .sensor_synchro_serial_rx                    		   (int_synchro_rx),//                      sensor_synchro.serial_rx
+		    .sensor_synchro_serial_tx                    		   (int_synchro_tx),//                                    .serial_tx
+		    .sensor_synchro_ext_input				           (pmoda),
+		    .sensor_status_status_out					   (int_sensor_status)
+			);
+						  
+endmodule						  
diff --git a/FPGA_firmware/output_file_sum.map b/FPGA_firmware/output_file_sum.map
new file mode 100644
index 0000000..b6c6d35
--- /dev/null
+++ b/FPGA_firmware/output_file_sum.map
@@ -0,0 +1,24 @@
+BLOCK		START ADDRESS		END ADDRESS
+
+ICB			0x00000000			0x00001FFF
+UFM			0x00002000			0x00071FFF
+CFM0		0x00072000			0x00161FFF (0x0014BA6B)
+
+
+Max 10 Setting:
+
+	EPOF: OFF
+	Verify protect: OFF
+	Watchdog value: Not activated
+	Configure device from CFM0 only: OFF
+	POR: Instant ON
+	IO Pullup: ON
+	SPI IO Pullup: ON
+
+
+
+Notes:
+
+- Data checksum for this conversion is 0x0753386E
+
+- All the addresses in this file are byte addresses
\ No newline at end of file
diff --git a/FPGA_firmware/output_files/.qsys_edit/filters.xml b/FPGA_firmware/output_files/.qsys_edit/filters.xml
new file mode 100644
index 0000000..9927661
--- /dev/null
+++ b/FPGA_firmware/output_files/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="19.1" />
diff --git a/FPGA_firmware/output_files/.qsys_edit/preferences.xml b/FPGA_firmware/output_files/.qsys_edit/preferences.xml
new file mode 100644
index 0000000..32bdc9d
--- /dev/null
+++ b/FPGA_firmware/output_files/.qsys_edit/preferences.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+   <inputclock preferredWidth="170" />
+   <name preferredWidth="186" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Library,Project" />
+ <window width="1920" height="1017" x="0" y="23" />
+ <hdlexample language="VERILOG" />
+</preferences>
diff --git a/FPGA_firmware/output_files/ChainFlash.cdf b/FPGA_firmware/output_files/ChainFlash.cdf
new file mode 100644
index 0000000..4759aa8
--- /dev/null
+++ b/FPGA_firmware/output_files/ChainFlash.cdf
@@ -0,0 +1,15 @@
+/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(10M50DAF484ES) MfrSpec(OpMask(0) SEC_Device(QSPI_512MB) Child_OpMask(2 0 1) PFLPath("/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/output_files/flash/ext_flash.pof"));
+	P ActionCode(Ign)
+		Device PartName(VTAP10) MfrSpec(OpMask(0));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/FPGA_firmware/output_files/flash/ext_flash.pof b/FPGA_firmware/output_files/flash/ext_flash.pof
new file mode 100644
index 0000000000000000000000000000000000000000..6fb7d0f23d0f68acbba430b3d092bf5992506648
GIT binary patch
literal 67109105
zcmdSC4R}=Lo$!61ITLas31&>d34wA#v<-q1gg!!p%SdaDUlpz0(sGbv9p8;xy3Sf`
zXSdnq1gA1oY=ey&3tcCG?Wnbet**G>GF8^vt=3p+%NBPT1?zO%u4%O`T_())``_nG
zz6h<op67bs>*czJ^L2mxzrXJLoUFL&gGwnwRqFq5<o~O0z5bSUw|?4Qam!7gx{?2H
z{)=0#|J0{$yv6?W8*lmaO*j9Qy<o|C3(jk`m*0BR+PM9{E@-t|m&`x^{Q2j%E?8o(
zxPILY9XEd3ZauH{{7<io&*Qj+qy6E_>?>|sccXoA{HAq`p+f33rh5MeFJ1HA1?OM6
zT$!qh>yP}^x|`Omy)mvLs#>Wqcl>|0p`0n6I!~FlbB5Po&nhiR?khGpv~VidDVJk&
z>4c}x2e=o>SL^dyIq$BH+bS9_o#@r~`jv7YEh^{C&ahi5D%(@5ok%}N)7!6%_Swp?
zoSFq!I32Ck&85<|<eK6PXPOG}{3*um-LFEr%}y2iz-*;b$-|{E&u7|R=s%oFTiG%C
zPgBztyle~XwI{Zp{|V3Y<Xr!YsV^#zvl%&6JCEamuOHL*=Yeia)vLEvR6o}@>CdrN
z##-|AjLOSROZm?y+j7++zcByFFT+os|NrTq{Y2?=S!Ev2#zKwRoY9!I&Bkm-ZOyu&
zt=YV>HCt<Ly{>vdWxLg??26E;?0~T<+iI@L_NznLMCed<&^VN}%tP69XscZ+{W#lh
z9&$E!tMipnAI~W(9#diSm@?eFQrY&<@j_|nOuJOPH?&9@$(XXreG2q1$a7%1Zi-i5
z0G<Ny6o97yJO$t>08asU3cykTmIAO8fTaK|1z;%vO95Ey=giMJwZ`x4`@zixw~RV&
z^E3a<GMvpBm0dPeS>Tr~@!MCdMCMd>J@-nb$^u7cN>enRR#su(Q01B`*E-j`2s!SH
z7TRV7_iD@c!i7CEEo9t6o}*60Q+oWvjKxoI*5gI`EImHsiF{`{y6-6}nIC#oCO=oS
zj4oi4{*hl)7CaL=0CNmH>eVd!FnHMDk>egeVBWY!@Cf>^o@`qS^Nh>2^E~(0Gw$6L
zljC`C;27Ywv9RyNMqrHstL4Vf&5FIumzi+R7Il$&9%;5`4Ot!ghSWUO?6xTLbLV*%
zxh=O|`pJ3Fq~$wTTIYH1S1muiKN`=OR#w`3hP8HI$ufUAXlVUj5A5K>v*S)=TVoUI
zV^$abBwU3L1In~^tuIx+#IYYf4KU9x@NELuCNJa(4~*+#25mP6*UAjXPCd^u;K~74
zOz5nR&wl7ZwTrQAyG!*m?ygetq_Jf#Y?bxS#}D|mzPK?9?L`&}%0PxnmGPK?ykwM{
zMlYDl#cmeBPvk*lEeC!Ji-zcrCGx3diDz1VI7+)J+9a<kB7Xr7p)q#SmzghtUjqF4
zxyLViGcc?vR%Y)<-UZh;8Ec`T`e%XbEba>o7BH+~{!3k}89r%P>iWXKqh-8sv%r=~
z4}gQf=F~Jrv$U6Xqv5gyt|y9?wAXD*C4JsRKmWRzmS-X>{`Coc-86hXge)12PGqni
zdNcn(be<RU>_1<bGLFDwff0V2uk1HO)<uWixKg^!_gALOt<t85ybD~&CG=ic8Ulww
z%Z?ey3et4?Q6syIe%<)4m@kv##}yl)@!}}wX9!*ybZU*vKVTK$tMQsL;=cpeeM6O#
zV?4K&rQ!G&9}YJY&~$YBhiSilsM6<gC@tqtGd48U=ik=nraphhzfb#8WiDn$7Z%N^
z%=>gqr4|-d3i;iNel-fc^t@O5G!mOtnDR@jumZbqKeU!#peL#+X4q@SUN`rcYMyny
zdc68At3X?PttHpr*vvI;hp(@A%bI=WGk)9Wc_w@W?=qjI&tu%r9)`Baw%9@2MplCH
z?CM`}-WQ$iAzz0}l}_D}u;AlFj)ZfbkKaysCjB(+Im)?~^$Utt)0<=UU9R7;PVPe|
zV(5e?dV)@rkdbdxOm6Z_<<#||kKI<`8<msowH1>EMj01ABY)j0v{`IPp6C9vEJrz?
z3V+0pX<a5-5Zhp{4d0<{Q3>4FR!+vhTG?-eCxg#~w$>hJix?}MU4LSu*r5S_zWy=y
z4CXGwIiqqiwpiKIU(ocN5LRgq9$Aj#$5|IMeVAR}?v%$uj%fb}U_A^CZD^PaY@67P
zydt1d#&|n0WexW0R?o863l8Y3p$u))=KJ#R%gm59>7fU$_>G?R2gj-K&;jTHy+xO8
zbXx3!j2pT-825D1L*Iv&+xfH`0N3uQ<_TlGr2H|$b4)Awh>D&e$FPcqn>gOXwHy;F
zI?3jEjfzI(nBf{eCfCx=hUc#+%l$J?g=hP1Ce7yF7r6J|o|+Wl-iPQXN9iZyy^nqo
z+B{2}&(Lpy-zHqey^FYakEbf?xK~oqIyo|bxS3-e@W_#I!VMh%hT{_Y{Dwa7V=j3%
znK|mXcbt3w#XU9IN-8fJk)zDNkT$2&&+f94kJ9EA=8|XKUbIqGS;=0{a_{nd`}tsC
zKLehrSBTw~2hZ;FpNT%0Kg7n4ZnG_D^ZSuD>h*DLs)IHUjI=R-Ij+sopv@2cHnSyO
z7~dutw5b^xC-nJo<Dlf)9)4<MoRiwL25l}JHO`!I<K%)i&x{&pe491s(7v*-6F)QH
z`+yGz{%XuK^k9iUN56+J8BN18PchEr<Hsp!+x+-L*kAgeG|neaG0v)S<A@KJct(Z1
zd6w(h=M1LQOi%Omq%m(h#h8`j#?*dxfS5&j#)YTA^VU<0_0fsP5_vo2SpTkkKF=@n
zuwTs{hYvW8+^Zf;g&rEm<Ew))?l1G$@P@|-+GD#%?v0|8*dMJU{}7C^eq;<gHkPge
z$M}0=_&+TeBXiJ?VMfcw?ZLBw;2AO{a~r=#KR+HkOZ(4^4cvR^6f}+=^kXRckM`L+
z|LYX8^z<plNliS?*G@IgX2t=ZvR$sh1}9e{|HE*I-bkG3#~rrXCD&20=S|9t60t=W
zmP*mbu)!mJh%4zo5?9I?+GqRmVvi4FIS(t(J*=N=0~~<sBzez}ACZr_x!~ye#|iVZ
zasE3?Jfm&TcAp>inNLf8qEvs(DC?PFdWLTEkA9os9H2Df?<JNh)4^7CO5@IR9T#yF
ze_MSTbR-8*55n{H)Kk{upFR9Dxq#$b=Skdr#=2A}-}8=hA%WlA+hc^fjv8)^m_}?c
zIa}ek<dn;bzHR$kA8wV28EVionv2R)CpwHBz@+oOM}cDnaC8$V@RKnm2O{_0D6|ND
zzhGo-Ma@Aq+Ul=WHf8`T@ytsvSXs|#ob8d56VuM7E<`Nr*)RQYGkhZt1)sa@l=*Id
zF7>+Q=b7W<lJb1SCxv~*jiHx3BOA~xo)ft%ZdC6Yxi=wSXMsZ=99(eVHyVfR;nGIo
z&o53Ro~>>Qa`6*B-@g{fRm`Y_50>!Bxq}=%XIMHGzR9)bgCAiyIn?#YI5~{SHSzHL
z4gP(J!wSnvmGeRdwKbg&`7-?@pYGD9fDSpIbhQrX^UH0k)kFt^G4;JmZR-M^tNHWj
zdpFrScXK{jJJR?6WSqI+RwR%4zX20C=sf8E!dMb(W|1NCzH00Ox#U1t>)daB{-8$_
z$K&_IcNe~A;5$FjO?Y4F{$*fi-{tc_j};kp-r$d`+wP{S`%I8Ctk*hSx#KYQDmZ`U
z@Q}`-7l)CFO0iqm@|VkgsjqVU^C+@HET{W-i2O2+mJ5z@u5ChaewwtcBv*>zgBer9
zbCz#^v8gAGEjhB(bDF-nMBCgPawW8D^@!gSzWkoem|B0BV`L1|S{yc`c4aB5WgL5L
z&qr2E*Z}OO&`s0mMxREm>%(votXqlO=@XyoA1Bns-@y|Lo(#ehe&DWkPH@w6JTi(8
zJ4T&<(mxN8U}ppR#LrPy6a6z^!gq8SYCFfiFBL0y@XK6PtZYU%w_gQK4-ct6jxyH{
zj+%GKXXZu!d^<;Z))yRia73q7X8us+_WAxeeVn87Y6nMYn|ahfZV!%q!Er}$%-kG2
z4~~5tcic=ZO2&PYao-Ha<y_=<2S+{bte{_T><f-NIBNRrIhYFl{h*QE2kiXf&%swm
z^25Bg0odhAY+9xLC5~%=xfc6-KW({R$WXJozqFA$z{bL1>R8Lj*Qp_j4K<q>6F&R=
zpP+U*-iFdg;1wAe=G}Kj@$1D2`1K87-8WQ;Na>@<Pcu1tCWr;Z|Ia>L8oq9p=cV9!
zJ@R_FtNTg4soV$uf)14!(~l>7nfGm&j34MgTIQAU{cCD6T+8@n9g+CNrf!jw_(W<m
z;74sEm1AvU!urgcfsObRX(lwbo$wu@2S$9B)S3!T<>Yy)4?9Ml|BBRlsVCQRpYvY;
zXIbVehHlbz3gdmF`oHG46T0lDt>}DN9yDDTL+Io`^XVkCDL<2X-RNgRr}8s&Xv{OA
zS^1eA8~aS=FF%_-?wQQ5pFww@=Kt^U=#(=3BDSa%TQq<z;+K7t*k)N^hst_(7`@>q
zwIMC<%Y0o*_Cs^-YaK&(b#3luj<a~ahF>1JoQ0m<kDjgZ^-OeA^e~yCuk<PTx}V*L
zowcy3Z&LH%+}VU*mzY^GMu~gKWFkWxG48qam-fO-8AED#BF7z13~4(~KW&c-(B6r>
z>fg(8PVGs{(=uSuK8QIU1s-Y7y$S8Mj?18v?Z;2lw(!IG>J0O89?j5C>}py5c9h^V
z_u?64Jp&H8eYB&_EceBK=xgFFk<(|mCu=qGOvaG*Qac=8M^VgMu7~e~XEAu@$vy4U
z{aDRi?B`lCRwS>azwljTS>`~-xd#ooCo(Men)4&~M0VvKv?M<F+lgMtJ-c`0p2)l&
zuXUua$U65%<_y}{RA<U#;hTq_+qqzj*r+jrd%!UaXVbWQ!}K68C<skr!5YDOXflc(
z8b|CVbka1CxrMjG{iSc2o`0mT*kAGxJ&r!l`R5W3PdMJqz|swWYMFyyb{4hSr4^H#
z@0U7XKXtwVcuwu)ThAG`9jw>Qg746*lK42;9n{@B0)7V1q>sAs14e=I%sZ%U$bFBP
zYkhH}y+)6%*B7K+C>0;h5jtAYHED}XX?k!@9;)e4ILuhTijz+Tb)M8>Kc@y>9mnl&
zId!h}0(hPeo<9Ije%Vi9JH!_VuCq?YRn}`{-R4|nD0}MXsjH)J>xo7CB_H+c8j_!>
z*AFl!_3QP>@g|pbxr=<CaQpLVxu<oVqnszcG^Av{GOXEOGRHo~3}Z|7jqP7}_64h>
z04>Jfzx@Tv{^dvw*0{4;*51a<UAX;4&Hs)(dU4XT7er_Ln38AuoTIc$d=B_ZzKv-n
zhLzmY{Uo_9^V#={z0onf#vdM_o8)(|!@FhR&;kz2#=|idR&!>x5zm9usCM?GavhyG
zd=+xSGYu0*IZu3aNV$&y!!r1ngMTs6BjV8Y%!M3q?wMPjGqTWC`01_yj?xGmW5$1&
z@p(3kKj(@0LrUlBx0G}B4ERkDPrb?fwalMqetyWt#;o`Xk)OjS%MW%;^)Ca5`+?>1
z%!rSd>r4GSa2L;o|Kfi}%T7UfybPM#dd*DN+SP9k7zu3iX!&U-o^$tu?*#p&jwW)Z
zcAVT#VsICOFuLDpI%$2?W0I%dU#bjbI-GqLxdLY$*S<ZG?wx{m_d~nUdEGwo+tefu
z<8Ot2>rbZNNpkza7pz9HH{)o4FH`PW;IeNV4QWsQDKe>JXQ74p)kVX0Mvv7V*si^S
z?V50mz>bZ2Hl9{xJ5ttbEq@cq(0Cg(6FU47I(#ai!&fJu!_1TMIwc)WBlmj>d77Y)
z{nR*{F+m%x7weJ9)!3!~;CCUhFa7M*6X^bWU-#p0Ba;)1HF`d+_d6$Ur+M^C@c)$F
zBVmR9;S@Z&Cg9Nob7?sjUo-02JK>RQBR8Y$vB=Vdx<AhL;0JuUElt2L=r=}}wHyXA
zH0s%S_}&p5htVS&`@>IQ`2Q@Xn;>S;Her&_Bil7p-(mdrqvY=#oAG-RZ<14}?Hrr1
z>3tlVqvX+Y9i#mk^6fQ#j-5G7Tbs5V^|SkVc7O1UcF3vPu8;oO`OfOMsPB!eqia84
z!P^q~G%<(7f4Zg{tbsS<w<W%iHE`CyE5E&_q;tq}3_99BSoD`Y725a9nClrcc8W2@
zj+Mu}f7F=tDeIQ>FOO-f=Hd1H*}=J9!^bD+{9>Q3VVnd%d9EjU!|+^(N6keaJr_r@
ziF*AW_=jV^@v-P=nJU}m67v^)`ssPdZ6pWWv7RwY{`mg=AV;Ae`A;}U-lKEIF>U&y
z&p?;*eTnb0JlA>BvZ2b3zZk;5dA{B$WV;;au0hr_T=OHoz*k@=1+EVSa4i$v6Szz(
z11+BBxSiv-IredUM&R9t-C9qdLH3#uLkjJkI)NGem2+Sg+o9tT_Sc9k<o1<(9C&^b
z&pzwd$wa1xaX1VPhfaaRdT@Z=xLUm?pmpRPUq|%$7ya{L{KxZVAN^zW_k=DoMkbso
zk*D#C+wA!Y`!fHHmbWZfFB!hhzGX?9zP%Nbzs-+&NZLP&+`ekro&NrW@;(5Gqhy`$
zlyGP~d>G)tMv(#5g#3LfG1jlRcIHw)F5k<&H6m}|KFm{%57)5(m-YUBuN+6g=OxCO
z18rr0ncySWEiwQ4r4luH*%#xTV(d{cj;7NT#*4d3(?jwqr{Vgj9!F^ADdcVf+51z+
zg5IYbYXY1FUk#T<{2^-@)~~cY$$cNjCUhe2)AjV`anAzytv@j5Dd5*KQya*Pz$`LT
zzJ?wX(qbI^z*R3Y2#urtz$<b#MyA%6D*Mqvk+&Q?liF4?XG90MFStI&+WAED6ueOC
zw#V~^#F~ZQT#+tc+srS1j(iwBU|(#EeW<Ze3Ypp}YmTA!P`l@uoeOg7W$27<%Rbr|
z?Q`Z<f6ObHcOZ=J(qE-RYiz%t?e{ChjFh*jJDA^Z%e}PN2f1%Q%DA<v&55MMX4Gf9
zLv6Co=0x__o2z2RY^BoK4C`k2rg`km%;t?o;`c_oV^0*g8zmpe+VpYRGnP{VTO)XM
z#be4SBn(69!UH*@zE#y(NmoS+y=HxL=@(v$idfDRx3`~XS?&q^%x|dk^G0%jdV0)I
z1>h(EPXYMs0UsY}lU1RuY+wY>&{p@%qO4~rcYcw4M{?AGu+Z82R?JwajBq@xtbA}3
z{c&ST<>6yIs-j{C7jm9FT%^VoO3xoEdCfzmZP?46^THLLQ+<u+O!-8w9j@5yOu4?7
znm|-+q_mYb<>&G&et$74x*}uB`0QtoI(67y_S@=t-(Zir#9^}k_9<w-9KP>Wd$LQ-
zw(K_5hED*0;lWYrSv}Rzb8B`3J|bl9$rg=0+0M|O>?=lF)(N$#A;Dd2UbmI)HyVXc
z?4xcRrunLv(7a(3%^SwiyaAdww8o&r$KZ)=HpClLbb)JF4KeJ>li1)M=3UG$$(rhJ
zezp9%`K?fmP9!}u+sb*GpDovqRY2pK_{GYa)Qw)O%K%%dMra-Xu0rQiRj(-nSu&cY
zcSD;s`0cuXeK3BLiWHLU$KK68ab;|GBCjnL`eo(X3(d~*tQL5ZeZUh_%VqDjj3e#X
zGu9ZtURhjUN}mU}X9bRK;Xm?FiXp$8_X<BAVcq&Pd)83pv<~L}cNJY-Wn1&q`+0tZ
z{e~|^ooUKqb8>C<75;C2a4cVsJ}%_hg~9W)IZg`B&*7-v!Ef|ff9Skr2JaL6!iT4P
z9NoS?cqaGeuN{GXbennGM($t0c%z^Fq4TDBsulw2`DJeT*^Ym&-0$>Y>~q(u+VkYc
z^|bQ6=l!|P3y#uf5$6Rh;{y$5K4T=$&ubYi%Utr=qV+3ew&QkU5oF(Q+g|}c8_dHt
zYx_o{`y75v<mRGc#QkDXNgI2y*o}b(qqxG5bqbM9_nSORq7V4q@oltTSjf~O{19Un
z(8B_HRzS}R=ve_hE1;JJ^s<1y70|Z=`e{F1wm<t7YmyQ}J#uy|wBSgo_)919Y>V8h
zL7$S?fwHW{zg8sv=ADv%a>MaMtOXuZ$3;%5VPs}2m9dYhHupg#FMK?U{#@yvQ^Yo@
zU*aokDpnYk$qm$e^|)fMA487{D*lhfYJYC?<Nn+~n?8DOcY9Ig7z6)w32VWZwRq}T
z)`Kr|_ZHCw<u$Jed3vsG(8x6!r7iZXMeJI~&+SN-d*!~m-`hoXjtbygR8%~xFRw96
z-z0l4%k5=+yEf$Meko}S?k~7uSqrwqPg>blqp`Ktm=vGl!DDEzLfL|c`#{HK-t!gD
zV(_rWemwcQ%|0?ixxe!KaenWHrEl_Fzi+E;PLlotck(k{wAC^v#ebiPYWPbh9><1?
z?ko3%r|}fJ6Z#9DE%77BQ-b$T^6F4!X=r-#9<f*b)5UgZ|Kggf)IZl6$l<C2Z3?uF
z|J221^|UyV0~H-_W-6GcP4<Xu9RDhS?ZgOd8ZP!sYPi;8W5qv$<Dd%dUi0&wsrZ75
zj`d1vKhvMih7QI1JgfP5NeS-Gl*UQPF3(DS+XJSZlZ5Yr4|a5>`)$F;Y%I$WegL0j
zg16b2IVOJEm#cC=aBN(ljPJ%hHHCe7kGG~m-xZt7I?^<!?$^6IKK*|0wJf?K^=a(x
z?5x^~{Au4ve7`|>>f2+rVb~rYj%j;LpDEI(i9WKY3VO>s8ylJ?>a)!66Ag!c6o1QO
z?!kZVaNqB>hK#D@pFuaqAqLw`|JiyRuE`I!56}5uet-55%t1z~oVwe0b#yB`;e~c#
z>!*q?JCW@zVkeSk#iHV~v@Q5bCvi(GcbcubnhxxKR^~}AR$*co8{4o4-!Mt)CHAsn
z(;2j}@iW9MVS$0%I|@9n5$9-MBy^~asdRjPF<iDg$V-K`J@<A}+w{i}`ug~!XOd&%
z(|dK!1%8WV490vK-1L}M4Eg;uHgCKwdzkfb#&M4XdbBm;%l{Mb2{{@g|4HS`*&%z3
z{7byy4h1s$awc4G)mG6V<RzSZIA^um=u<U&d@S{Be4RZ>#uYgdKP&Nt#Jg^Hr!V8r
z`17~e>e=K%9|n<ekwuYBk!|#Gx1RH2rCMTv%{UhH|E0`tHqKKOdjAo6zneK0&s%n!
z7^|X!7|yd}Mik#o{MB8BE*k93Sj9UhT2F~P_GG&a;!LB_cxce@^%DK0O|m0r$v85`
z=>F=p#F%!8)^DRj{rm>`={YLI4ve%@t2!>REzw7-9sBz-ae^1K?da~N=Ho-QGv(}e
zH)Ff0vt&dkMYr644e0wXqv-Q5W9cJw5xC2GpNL8P^P`Mo+EcM98K>^<irE9ye$d0p
zQfd0^flv<lQ|v48_lW<!idMjn<S$~_sr*boC(9daCf82A?q@41)=aLiSm=cww_A;=
zPR+GFJ4)p3HMNg7mx_y%j~2t{D|LIkLWQx@?5{zt*&h^bCC>YI*|$=P(ofOHaO&=z
z>D!G|)V(LbYg@**-v>wRcd`oEgqI>ef?L`CByWu&OW5%D#>km{8|+>k@Skx+_O$#w
zJ(fPB<wx*#+mWBzKz@F;SKB**u@Cy#Ny$TE-VV<Fxp}_;+Tvfr;$LK}IruB_9d=UX
z#ZC%Moyb9zd~Y$T`B>v(W6yqfa+eoPel<5e`Ff`XjlLGYC|03qQExOh*W;V(C08)6
zj2<*ji}&O#f!+PlUe$uWXdgNa*w9<aMcn;9oCS}yDWOTsx5>a`xqY1)2hk0ACbD0C
z?*6=}p9$V4J)2xq$+W7N8Z)LQ2bE>Fh92KhAHrtsoFsN$V8kCyPk8E|#V?6GvTyE3
zi?OkG<%u7~yE>;4Ydr3r=v2I0N!t|s-7oD90artI&|Jk>A##psZj9I}asc_-Pn^+>
ze;SC8gL$GWYDudBUD$U}Y$`v?5Qmqa8_Qdb<mtu8)L7{8<Y$XheccST74-NA8?eLZ
z^U(@q{X&7=y}YQZdW}nxA62LE?&VhAz1&*X%RuKFRW-Vszz&IiZ}GH$5Wd?-cc-A0
zB|Zu}I<bFxKIi8P9mq(n+1O#5@E1QrY@u!HXW&Oa&%{m-kh3Zy<lE~bVeB$v1~~}N
zb^dXu?|TZh$VI8xlK9(Bd)TKO4SdS?bKz`0)Mnc%gG?NUj=o>PpOpPVd|GalUm?E<
z{G0fM3H(Z>_ACFkSHtYXM{Iimc_e;2@%DNzfMHux8HS@Oj6G}P9on|6C9s5Y@O%dE
z(5@<Eg#XZfysv8+?d$M!Ug+s8c%K5Mh=yt1-U)r3%$K}C{M{fqT5lC`Q(FNz3Nk-1
z30=v#dSz_i2bvpXE=}WaVcUoa#Q!GN>^m8^o#SycV}jc|$ID#)NAa4q^b~lRu`zfF
zPJ-JX!|8*bmP7XjY{NMJ9{>4X%WYeF(*5Mmms*7mbOO3a{E~by7N-8ORpgi0FdZL4
z9{P<_%k3!MCEuM33q7TOS*D?X7}|^M4bwh;H)D>2FZl>?1TeT41Ai@Z?&iH#^ezG)
zu|Hq8W5)9MVgG$nVx*8BSI@8Z5Z6@17sV{zscz(bYUWoD$lf2?okqJa_`Fbi;C)51
zSM<xcOwZBn+XLXf3}4<(zt@LtLpyRgXb=-f>`q)@spHyCa1K92##SM3hmg0%_(p+C
zVXuy?Bo;i*oaa!pzD(vt*WO5e#H%C*JgrHOpT!2ItwI_&qsS)heL4ZF=fi4ApGkWw
zWzAk>+wC2WE4K~Dl?RYf3;k<H|DF^5GjrL5!8`4tL)jLwwSSVl{&77#|CI7NP7jSk
z1z;!uQvo;%z*qprKd6s$1KFK5Rz}$~yGr8&UfLEM7?Bg+m4^q+!!vh$zd`yXLVlm*
zs6O16ckSK#nWt6Pz-F?qeX8>_m)xIqj61HKniIQmM?Enj{-@^8cZ=`QIpU)dM+H7*
zZ>JKyNi=v~A#Y&!Wvp#h$Ih;BVui~4_A`G>WVEac@b)!d9*C{B`Zm6!(~~`OjZWRR
zLdSM5uXPdGPjqyJeZ8apI_xiA>&0H4>@OzyV`+KL<J+hMCf?`u2t0{aV95(?z{32<
zL>GF+nCK+3iOi;uzpcn<DmfI>`ip<37QGF-zpaoMTAB~+{>EXu|4MAM?`a$7d)^?g
z*%+^m{VBf3(7ZkOm6Lpr*r8;uh;C8$-Azm`aC_*!uU8Kw=c)>H>J9wha`!+{C9W;S
zPP2{a0&{X!%o3QXA-739LK_=cr~Cd=^4y+jZbm7w1@^KN3(l~ONc?I~^!Nck7c<ad
z^f<6FVmrvitWmj`?=!ClZeT0W&WU8T&pgS#{fm#A&Jq81DLUPw+~cos+*#v()Zs|3
zJr%px?b{=XORz)Y+v>|X$w_(0Z(>&So8<6QZm5*H0ye5Kd49}lOdHYodSaLrMq^9J
zcz4G}IS=j0BvfNXFYj~=l9Qh2Srut=jt}t+`OCIr<1BS(dYU*rgFLO|UJkkL=DQdL
zj@WCdwc8!sSLl`}wRqD5#;NS*S!H%+3}PQ(PFao2fzD$W1&5yL$y`k0p-FNqbeN5L
zK42}ZG#e|K&#5C%C2opm6tI|$r;$(ailmjuynlLAsrZJp-yW4c^TlkoL+$DKhge1P
z3gUBYXO-CV=`o8Kv#t4{#Hy(ZXm?2BO=7^1>&KbUF-0uUO$-_G)GR-~lxy;ksrugO
ztwwFHX)wp#$rq`q5r6V5OujO;`Jm`ex&b}H2g}$;E7pBK*4rFaTO~KbUQmlrDQPeM
zs`()FT{9G&y_ondicHjP&&nF>Y<<4N%BIC$fIs#h-$wk~(;L4F+6-U^B6nkl4pg9n
za`bb)qNgNJkbGoERvj<r8}56sVRmRMd2Lwo=ruoQJw=7m$ZXpE1u|9ltSz~U8x=X*
z7VcQpnRma_Dc?4!O3MECTHq+#i_?_07p^Lv93y<%5&1qY@@*ebtHAXQE$6@PR8Lcr
zliUgYe572L^Xq@k$>UteIE<ln;EcTjlXA^Yb-HJeFZE21zvAiqSMUe!HhbspCik9K
z)JgVdz=NONHTY#6ds3^6pxYUAo4x+3P2x_$*Ok~)$HSuAYD@g)@v*00?>R;6>D#1V
z`7rzT+>eI~&=i_eLxhJmF@n@B4s9c5L3cGh{~_gmzVl@K|ExTg)Pb-Q$M>Gx=KJH?
zyiA+j@@<6W<RbsvBfiAXMZ^z;f?8Q<gV-qSla+jRuO&FUyT*=vk{|ub2rtI?QDo&L
z+jWbB?tuG|rDL9nUD9^@6QjoBo_p3SO5Qb>xF!C?D^d5K=+_U;21fg`BlW|+4A^}h
zgwo0Hsd|Aw@tM8U0b;q@WhYW%!|}Ub@*1yR^c-I2MbD9$$T;7lYijYO-gw`m{qAT!
zpM+z!On1>ipU+|+WUY&Nz~z9{jN7mQ#2adr`;6G^0`p7W5#qkYH|lkK$!R(URO;W#
z@gIKcIR15GvZn}K_^Oy{hyRv)LUf=vg3JW55q1z><Kv!2hqZqep2qh$mizo(UGoAK
z`cP;4`YXfN$b@n?zM|fV&1V0Gr)_p%@5kG2vD;4M-u65(kJ#@pb};!9>@s#=Y?Jt>
za(qnAKGpXd_=8$?NXNz;wLH-`xkW*@40(8_MeKUE78zii#x%Kfo*HmdXOtMaG5%_&
zw)^5EoSNqLME`9n`6clMq9+F`@(J3UAif^(YgSSV6a0}6+b&=u=81g^@;`DU_$Kj-
z$VLseLCb=Ue@1Al<w5Jqa^>sG=l81e_)-sZ59%>T^XAwn-VFDT{}sGhI94yTPIPS>
zlUKP7d(~1kDJyeiz{lO)shT{Mai8e~_5+l39E=g`%bT|87~q}KIDVfW8##45+OyEs
zy@?u**Et;<5pzp>$LOnu>n9^{6`+U6dg8lF!|qwdliQv~+p@j>%H9d(3wi$M;kdxl
zvb$%ZxL_n6AU+`Oh#%gIZ1nWGKVsgM#1*Z|TldXk7PzhKO4b&XO3VGVhl^SFw?z~p
zbV&34*;kar1L8kBJ|J}#>cjt|u=fWne5U9r&()shUX`D4&F<g`PKgxx)!zyqpw+n(
z(8>~8$z0g=fDXJv5_W$fdV65H*aL8w?wZ^De04y4+r7xG(b$nQG@MS|S1X{=*J)qT
z;iw7?*AI$5uXhAI-x(aA503anEern>9DfiTUkRRf1;^KdBjbo2LEgnCN)5VfPh@>V
zY{_=<55xAaV`=y#`}gpSv9WhzsnpF`EJLR5n4#kjyVb1N5rtPCGTh5}X`X!xx(Po5
z+y&3X4MiQhxV%*D$29USntQQ%JZlY}t>D=T=(Jmn)V~YLuYa#Zr;Cn47KmZ)j*8Am
ztmiiEmDpvH*pB46)H8lu1n*2p{DXUOr;>Mi%4?nORh@cn@s~2UTUqq&MK5F5Gj?E0
zw660^>bDx7`@qKqA7!@7dIK^wUDo%XCeDH1@b@v+SpBt59p~g`1p7cn-qDr)ARE|E
zBl}Paz3RYAIrCa*bS<&;we}_JKWDF0t88_f%C7X<&Sx(+zKlH>1C80mU2WNe8``qF
zZ#zy56K1bUW42cv+Lgn;=8aYCm01NpS7mK}G3cM+=c-28y94j7M8Dqq(nw9*ibD(L
zH(EGn9G+()1;#BfM}avC%xx!c)8E>Xxv`m5=C@q^EhxT)XuD7N`&$aXxl+DW^ErHV
z8*{hGK04--c)DKJPN|t%?0JdGT(ZA|ajf_U^d1i*Uaz9)XPW&r;RWy^`55gphJn2>
z;sdfzgZeb%6&Sm~*yX)PejCO5K%e+HgEa-lHw6dP8dkmWtBT<k%Z&DOPh`~ntjGa-
zgQ<&;hJ)|YMOiZl$B!v_7dR|6ZQ?bfC1wb1jbtOwD^xmcko!I?b;JSY=#Hol`{PJk
z_bn}BN@~c3R`waW#3vT;!&_+^S}bi<7yDBTY2SSF5cycG#Ng~3qW^nX2ah3J%80-V
zJ+FrOHr~aMy-+z~3Si{7sQkSFeDWUny@ziY?#Z%dn6*vl4*fmV)^VQELjO6dtJYQ7
znb0DBJCW~Q(C>98^1H{8+nLxK;`7IVPxki=;0wE{U7L+Ysg->^Vxx{)YZs|w*nVur
z0JZn$pkJPESW>$yl{OID_VBH(9==mF!<n(8#hF_>gYzp`?`(JGw#)v+v@_$&XR&X#
z*NOaUr8C#%{q(y&;LOcPyA*pvx&La^nbRuYyx2ycuv7Et&Dm0^$C;atuKRlNV&<4B
z`>yQL(9CtU##H8=iOfbN9|uPEy0P~O-4I;Y9v+&C9cltr{CT%w?Cdr=c8ac>OC*-@
zVGk`}Kk63NG&ZBRn}H(?9Lzri9k4%hYs0`<@5~*PwW73Bmj_1RpJVeZ&-&HuG<#92
z*FACK?A28+>jy`s0%J6QF&e<gcLM(yjF|?19~t=)d_?c}@a@Mv*xNnGM_WPo4KEAu
za%7Jg@!VC&7xH0Wf=n!?eprC#S$N)p&h0jjXAdG1E0Kv_WFm@8bWqdqh^J%bR>^hX
zX>}p2+R)AFcr9|CHd5MtvL}_jn$(SqG;J;8^;&~Gzp|stYe1ikMazEQz*?q?Uw@kg
zOpH}tuN>ebstF_6%UH*xPNZcxT1XL#ot3i+DYaGhS<F8ABsQCUdJ5Q&J{i?DgB<n~
zm<!-h0B-#Fo&s<efV%)*_|&!nxD~+7PMX>V6+H62cI@lJVc;?v`35Gi48VteWVE}|
zd|x-ZdB93e@rX<5|D52On$y(UWt>)vybR`|wxvAr&rZXQ4UE^=WP4psV{MwX$@@aT
zl{JEHYhKd{PjGP}Kj@YEUKSrDIL}-EmS_H5!kB-k!J9w-EpK*X)#m1VH_F;DHf<oP
z{xV^l*Lblv|4VOq&5N$wY+ro|&;0Lq83X+?Hb2P|jz-N74jS{1&e7vE|NY-=Znp0j
zGY<37ZZJw8{3Lsc{Qi2L;W0ig@RoVuw?n5bSv&4nEo&F4IcH{!8gS^7bx^+ZS)=#8
z{NPE(*}<MczQyP9zPIKnyrf^^x710x6>CaEk93?JtH8E2CjKc_gS}-BCBDQq_CUXE
zmTQg~iPu>R1kT4)@}8Jg<)IJEjb272=7auXzZ)w>PoB(KwLFhs7qjGESkCFA<tESg
zNotxu{kF;u;L}`9bLt?f(sGUJf@`!Te{73BV}pb@eU_b3X`wIoqU#P9H}iegjnJzy
z^d$0|V+_lvJTqs^Nv>B_@qJ=@sm0!q^Qh&9<(sF@9dDCAUZm`R9_(M32~FDZHSNg{
z=At4W@G8=zlr8JHw6*OGPtJ)CD%LDB<Z$^jh&8?{{J(DU+uR$7#%)#27@MH$CTwhz
z$b=mOhDVD$&qDX-qJB+zfZ9_(V+@{QJRq{MlV?Yxg>H1ml^7LyTlSX6*s|}SLGv_j
zbDw+@+2J|&2N`2T_H>{8Wa&e@fvCughPxVngMG{PLu2R~|0i_QhCYM-HR}Q3De&Om
zwM<F>x2<3v&b1tBI7I#hR_f`(TWVmT)yRs-7CJscOD$VDvr)@eUfQP5z^1H%SG(gE
z=L8QmZ`Q9pc(zLLFSHt43;m+cKJ5NH(1Yg%#tHB>GAgt(Xwx9LsTr)vGH%BiA`_Y>
zz{l9j7`tDsl5u=`_Xl`DOX<V2j$4|PtmjS=+59FpEC)^cv7ZUaDbbHsIX=c7u~3^^
ztCSCu?Ef1@chR-|wiW-N@f7oFUDbT(p6m(l%jY~3`f=^+zyHj)4MInu=?Lxj2edEu
z@nM(wq2E)`d;#N*fn!JM#D%^LrJ^D$<7ttYT(l&QM%OHK7<!6N@2(VEUpR&w*gBt@
zNeqD9Mn-<t$-XHw>psYulA2@_?=5hqd~k_x7mr4=$}q$yh;K+<x89m(lgr=(L>8PW
zH#RgsvqkK^uR}E-X-KxHse0U-b6QT&9n0RlhwuGdq}Vs!Xg~iX^I~7<<GzbI?GXEB
zPV_iauGu2AgP+v3icMnIWxucc@5JuFnfye|m%D2Ag1|rb9`3_K>MwhU#qa^-55I@E
z=zd*}Jw{7Z6j>dk_rygl=z5E`KP|L%>C<kg<jk1JDYP7bcj#lr=P7NsA_L-cc#hpi
zo}fMQmr@=3JaQ!HnKSn|)fX$b<SBHZjsCP56d90y4ZhC%{2$@_V`ZHS+6LomIg);5
z8SZY-a-9n?F7MRX=2pAasL2pN3hc<pHsZmp$aPxa!&Xt>Fn1-lsp@&7<Pvy**`EX3
z11>#L@#pb(AuF!vTqZ*NK&~$G_Jk$x`<7*TqQ2x+3v~Y{g>GehyRj<+6%*ro;1A$C
zf~)iwe3AQ)Am>+WUVz64>~BYsTTh&eu1>{v?-@lW%^%-)4#T7G`S|YFyz8jdwxdjQ
zf!B{~))r+=;*t2gV$Cz9;_5<<T7HiG<B4a&Tw{mcmOL+1-oG>{p})y8Gx?^}ThwyG
z)Rpc|VzxZ%7Vjb7iJ6TNd{z7ckG+?&Z)2!M>g$OeUHXVGZNsM`Baaiq?$kME$N4ex
zA>oD8{3S;|8WrCwbzShU4DG1}?v$0NHSI)R>f4!yj=OI=TlcAZy+QVIImEb<2g+P=
zk?%Z5)^rk(6kO@w&zy`^lCdOK9)LztA4}mu<=)#uvtfHdj5Slna_V-qByacF`#Tzz
zomR(%My3!mz?B^HYaV^~lc%FkLkhey*@b!Te}uT6_hAIK(>&FiyqR^yyj=H1eSCpk
z;~c;a&K*B96z^q&qt-|0LClx#20r{zH@4say5~aA{w~%$Mr@tno4gXd(Me#nk?l6&
zqj|UBb^u<9e9M^KQ_bBOy{|~@><;n{k#m1fk&l1JRVCV{!AWYY15?4v6FA7bR{5~#
zad>{fGRQ%mA!kY44m>&Pb|O3f?e%bvSp03-`xYH5JH@a1vZLSale|pxMQn8ZyPXEH
zMFqLV+1%H-%YDxI`F33PwMp#Ou~zB0tsJjWcMW2+yB~=EZ0~Tqh5SkV#zt1{Y)t8x
zOWv&z8cN*7*g6(-KeAU%B36SYtTiFa{m@cuoGo(6TGc>6Yx;@qbzJ(C@Y{2%_A2%W
zQpZ(|$;e(E%gLAm@8}p!;0VUh@ABwt;K(wb`>ReZJM6P;OuTO|buwhOE;C2RpRztW
zeXopH6T~XeWt49gTh_T(^20~mrF*IE5TB5XXg_g$snp}zkhM0k+wR+v!wZka?v&-~
zfaN|*4xXoW{&9}Ak~?e(>$tF?HtoK+6xfvQz9umABip{-_<Dp)##nnq2a<35I)F@8
zNxf)wmCYP|RrsB>T3BoNde9ejXJ{DUXIbWeL(6DNulpqq;wzy^#|x&NoaaTb1qO1}
zCbn8&q6W2#oOGsMbBdX=ciqCKG*T~T?GsuqlKpf8$aMEq;`&u0pTRZq%N|yV1vrw2
zuG0I`^6>g9Px!v8BjZ(wJUKOIR!Cjdsj1%`S6)R&J+kc@Qj5Jh-m{^_r{Q?`4}fp^
zo-eQQu-W9}CUIx^nQwFa`{IxG1M7%haxStCj~>&y1<l1)YaNleN*xe<-j+CyeTnMI
zcr$x3e0;Tj3Vz5B{+P9y4;KUdPtoS6B{dk~*JR<>50GzgO7?e3|6u$<#XHqr05kUm
zj-48gMDFj<Z}Q((YMv7F*xCp0#;&xK`v-GJvOG(+7Y+CKA~Qa2!iU5idM?Hsp@l!!
z0UfK8!)3J{`)_<R`j*(#rDehWF!4^U#3R0a@?{UX{TMM6@~-2o>XA6BnK;RPU@tTP
zj{7=w+=hM-vo%GM4|ZCMmi^BHY)zz)5ggP5VlSbYCHm(6wXch!gCd7nY=AqT`R#GG
z_P;dUN7+-=F0r-POk@esQ|)d|C$MEI+=t{Sd=*}n^)6+(ub~Td545<QJ|5&<vKE~#
zbdTh#?APFLbQn5+kX%4~<HDTz6nmj<VnEr$v&y}6slPt{J-_xVyr<r{Jo)dP?61m1
z-I!9})^=X|@-cgn(Wja5Sw+iz5*$~c3m4+UGsL*9UGRUz9|ITf%0Y{jv^z--{CL}4
zAb9?t<!<zcrlK!?EUII`R%$2xV#B(DsbBn+=!DKEuxoyN^I3y+rONyK=Xwl7=lV1D
z(#MZm-OG>(_?Ubg+4p44!q0o%pDgud<*l)@68|Q2LH39tgnxh34+`BA4;yMy0@^>L
zLbK6N<bixnT@9QK?rdo1g}Our#5Vv-mz@joQ)%k%n^#x0Qa{{p89&lG>@g?yuPiU<
z?^C+}9{0<@3oms1TK9(KKC)L$PZ**2jZzC#%iT+mE9TX64$`Mpk#|xfvqGyRwk2=a
zn(fD)axJ_RxtdPh%FjEc9@rg?vmSw7F-E3J_6#u=z8ap4ib==jcRS$+Io)t>eY70+
zGR`2+y1`|jN@5PyPnHN@ca%yOCO=xdP}Ysb&Im8du<E&Hz2zAL{h~MJF+?^D$wfN8
ziH&O=&Zl*rEn}Y4mOL@>%ca5l)Ne<Rpa&xJVOh^T41d25E!&|*hIeWD;d9*%=F)O6
zwM6!S26F$tz1j!FUlZG8?nzv{ECVdQocc7W5_&-YE*}@a{slb1Eb=O{>(|dTZWGin
zL^jz=ut#i_)Gg+Xs%f~BU(vFQjBRC{h*S3)MU7|Xgf$83UDSPM`uq{P9*xGYQ8QU5
zj!B)z-mrVQ<ojZW;Tbebg-)vRWT^3YW*0S%E{Pp|+)U4osV3e%o5?p4spX|2l7Gfu
zdSyl#XE)-*iR{O;O$8_SW?~4fL!t`?a*%46o#6Wk5-<MuUSJ6H^QWCk^7nEcGTfgy
zCi$4oQ$oplcy?`3x0AZP<SWDN9%f}3JrG}>{7%v8I9ANK$7mZf8tbs{*nI6*ST|x#
z0l13H7d+$rLH*3F+^d8}?q9y5=NL2oQ%n8$YI6`@z3Kq_fRZ)xuxCb-gL|X)pda76
z`MruYn0oy;e{$5Ym1-kjJ)VsrPhP0aUn7$BuA|{(5u59o^)2cmS)-~?JOpi4sEgv8
zRfszNl2&D>>5mNM$!kJg$;)K_j^4k({M`+F!!y*#w-Vyhm0ll`zS6E0n5eTcw(8>V
zE3uB0NylSc56Zd7x$s|fYh;Y%UY;v;pR6;*Z&Be%`A~{DslFnkQt?Gf)@O``rG0wM
zDeEcLcGw@mdJy}qmc%o`novxy2{p)?P?q%|YzVSz9>>;D^Cun!f97bjGeOOpHJ|v+
zMPkL!BHkUBZ~ZRfebWWW4(xP>_tayC(UA-3wKym8Kvm+$Cv0*d)_2904kAyYV;TqQ
z!T%cRVC_lZM~`@C#9tqCkBiKh^&NMYlzT|*V@A36a<9cOWN)#wr+(5UI4vyw3-8AZ
zPO7U_HAmw|iqWjJ+d+H9JKHxFqm%OFa|so0$Ux&(pYFqRHPeo<hR4x#3dTB@_th^b
zQa1`M(J*|Km|L$aA|EmHIJyyrM`3D@VfnV%Ao7r0A+{JA@*G|cuMaZD@ca1E4jKwC
zjnVBk{LqE|1L1g1h0EVUxQ+EqeSYf|>3NF%RKNI1PuIoT*6a7=&y#y!{fxdR?`z{L
z!}d=OMR{)}Z2w0n)hs#ESIuyCbtsjcslu6pvbOW<<F|ufCdxIxK7Kp+@t%^@zpV3A
zECy`h^VIvj^VCKBnCFZ2%k9XS+w7@RH`_zgdd^d!7;C-qKBEOMEOIt#dHgc`Tz+|p
z_f<RJ7)-Nfk<Jc;((GHjCYuYbq+gVNQTkDr=Vz-Zutk9_3T#neivn8|*rLD|1-2+L
zTlid=GediqU!FZVwQ42f_cDGj<M%e%j6WWxT&R6CTz`xP6Tyw$;{6~a?D*d*@V`+Y
z-<v=`s0%JSYh`GG*bD4qy}diM1>D-8<8gD3@G51Ad`Rrz)5>T8=QMktwuns%{dKMA
z9k~-SGg{|tU*|;TL<VHc!mU@d$ebd7$Q}LmhvNqrd!}l_E+J0_x>VvDq^$X+<ZlF)
zqK&0uFLPP(-6}i?418N4Jik;@*rn*nv|=xd4ev7iT;$`A$O|@u?<??2^J~WjXt@t;
zMlP@!*d6Q*@=hH6NzrEv!p~hp)~AENj}$RJ>l$L8lIR6%>fmZdMEA<FKU&VUzIluX
zFS-~<^F;U({K~qc_2nx+>DkaQ@@)})Z>E2*Z14GdYSbHiTd(<MYu&E5@BSTnzcXxB
z4hmgapW_{H?36R*VtjgPLG$5Ulk>f>?7wYtz8f}bRg>YbmFSv6mD#aE^c!FB+T!>M
zQ}n&cylPN*{ReHVQ#WAiw)B_py-9sT<Mi$qguc|!_AfX`YD9G@k%h(bOxkDP{d|jz
zFS6>sA#@%Mhq}+H%cm_n)SKK>tUu3N?iFf2)N_u=fM>Gqyge=VvhRMO-hH^J;=jf}
zjM_sXat8mf@5r>!qg3jWZwd0Z4-9g(8NlE<ku6dC?%!;NPN_mnU166_#Hg2F8-KUj
z0Gz4wsRKKaFQk(7Y6jn6x(NHY9NJUEcy%S~%PZ|4{*LE;?UE10&o}Qv-&baH#x?9C
zxGerf6#{4WD1>^ElW@I(9OL77zmxpH+zig))sqKUN0T)<>LLwiq!^2}FTO)kQ<nnH
zH2T=fSgb3n&9bh*wcZZ_O|jJ@GJ6{|WXuf$FMb2ufHAT?E${(n3OL%G$fjugGP8%6
zBbCjm9>z@p+e%;yxsA{sS)?87^C$34KD_a{#qf2P*ILt{MRK01UwucdMQoK?Q<a!u
zCqlsc*5-mz+kkajd^tzn)djAUGv(@@buqrdEbluUE^fn4FsI<6_?a^}54+!D58Xc!
zgX9dMz2IK2=jWPsn}u$Uyjvve8SgK$CrNm*J)O)8FG^jqF9KY83($ue8np6plJ8^6
zIE6c}5d37m>a|xEk(G;7;ddWOBX<#FMc!~9FRE!7zUJDk>ZfJFuUFMO->bEn51Of_
zgCUKhyr(U5y0@bD1vAy$5!}BGADc0&iMgtMyuhtY%byh$e61ImMqaLP8m@t#E3W1F
zX7}%y^C9LUmRZAGtjnjGcL!s>SDtzDEWCOybUtRL>|?>R2bh1o=`|e-dG5vX?S>J#
za{rTfAZAp@zpVEn)!Q#(<MYIzIqZ2WG2sCF99FQep__HNTJ|-##EThhhmB2EygMEf
zJ(pOqr#gNXKFc=iWpB{}<PBLoJARaV-Pq|o>s4w}hL{qX>{ParcY*t{6$7+WTjOco
z-)DVhooBq4<5c3tXyW(KAZAiilsftYyx-p!#cox^`TJHfo{T$sjO6bmPBRw}6D+V}
zp#@?SWNhXz%sk&0neXqn61W7u<klj4pMW!FG|}$W<kc!VPgN>;|Cztl>R~6OriUGP
z44B_m$U<X0q-M6Fi}5PO{R35N&owS=4SVT0?;;WpcCpu=oJ4)~J><+z-A`E$|MFRD
zets6Y^8=f%o4gYo`>WQ))F!dBoQGRgmqlGe(*QWD#ec?kaLqVAZhR}2oEw_xy<*MB
z*JF>Htrp(dCLWhqd5#mge<?g^LY~k)^(te}giiE1Ks}<LnwH*^Q)&EXt@f7%@+SB&
zQ|dcT<R8C5+a~mcdvA*@K<_8cb?V;0XPalUPo-gid4_3Z7G;fo7xrS8rtyD>jAP%C
z72caYPMu~C@$a4jvQj{fr~^>rC9XzZ(6=_b-}jLnpE2(&$H_jAsGab>1F&0(l;pZU
zd~bY`lDbA91HZY@se641FfRt)v*VY*>ws_Zlxjfs=$ir8#~RjoCU`w2bvuK4QP;Zn
z6bsOQY2uQh2cd=3U#YG4S7~}E+5|F!4QYW6hTda$yf|iWp2X|!4L+`7>wGyrpm7(v
zC65>Jm&hLZozR89VS{Y<H^_S{%r{fM9TG1}4Mg6h`Ek~rD{;7CtWB!|FgC3nG%u8z
z;JSHc7JDW#+n`QwHJll5wMZ_ZX{F($&JCRsjk2fUC}aKZLibXE>!|3?g_^HEexh47
zBRnVfuiF7#zI+z+Blb{Tyq{f`J0Ir@$X~IQB0nNK?vzpbLtGwzlIN@CxvsTqI{M?I
z-_VVIHBQ~DyIDWWB0J1s^trpFefLcF<s$Ky0Zi0JZ}P`Af7nf*K`VKSz=3>dnJ@3x
zGmLUvwD9;4H9+aZI(3e?6q_zG={5x4`I>}%TZ7$_m?neGk{nv{T2I@kHhZRVRy-;8
z<*3*x>}qHZG@c`C>K*+mB4f#U4ZPudWb(}+;OaJbU(5fyi)VH=I5kr%h)p8)N@@%*
z3cTzod7{XenF{!Kyuh4=@j0aH%eu_zJ_?NY2Qa$8n8B7#1ZPU%?9sV5v>FR*VjQgb
zGOPmvZ^I~fE1a5-OdW>zssP>#G`v&M$>Y2uy=Ow0^JSRX?>--xbxbrt{zn{)yz<>P
z>OmYk2E~RM_$}fLW!C4QCARyNIpOHOi7%a;8+IjD7{hr0d@TItL+IuhI3mQw5xo}X
z3I8-4MgRvfp@zd4fny}z@%5KIr0hinj^VyO9GaF9ANG+x8lI(oJ|wY#{YH(B$48&r
zABDf|ikv7_|EpZ6hrC?B^P9~|e7zqZuyaO-MVt`nZ#4G|7|5Q)a*ejSNVTeE(Xgr`
zUNNimzGL!%0{y4~u!jOT7}xIbc_Z=)Evj1a0jx<{>~$5Lpw^JldlX6UN3K7s>j(9|
zen3BDHERP`F4Tq(r1r@kVfOhpTc&(>upS>GJe2sP-j{3Ur!D%@W(V?2&WwHPZ<H7r
z$0~X+ve1}(PGlg&v+juYV~g1<u4113lY=R#Verl$c_OgeVsohxd!el@{B56pd6pp;
zS`2M!Zm5!L*$WO0yYyJ!88G7a`t}$&!QC{@LB9H-gZKwv*8QcA(5BVEw@+r@FfuWR
zcG73KEq#aE6Q7NqLtu<!_gnG*=Rg~`4f&Vv{~~|QvCtxIU%H`REiqA^n8-EujL~D{
z^URF!VP`mbP+8OLP*3tfRWJF2ZHH{z<?n8>E-U$$pKJBuGgJ%luND6rY^Voaa;l5J
zSFU|Lu_^fXNo-E+?#HJBSC(t&qH`-dh8;Yii0}M7t>Yh5WbL~`TV&4qzehiw_pIwK
zw<Gb3fQNp`tQTE<haI8jnO;-1qS{WV_7Qk~a3An2ve%#JAs$;K@RVV3>RxN9wW%we
zslthSW#4bfb6tgf!d6acP7gn?<oQOaU0^3?6&GP+mJn0N>>s|pJpR9^{dp#13am|h
z3-PrUi!tL_FHHXZG3?>T5-YrDz3}gH_6be4k*m;sqRXo%cgr3()<TI58tk+aInq#2
zs#o>|18*<#+(q0^jm(fevx}kES*s`K*&89bQC)cLWh%`#8N<}81a|RB<QWUA<(}+C
z=I`8~3v$oD#(&f9L~Kn}3wm4N_u$9yRi}a1()hR3QXlWx?LOY*n6;`tvCzkx_-)K{
z%jWs4Vm*Dkgr~^v7U1jxMx96Tt+*!SXi3%%Ejb6A$k(Wo^s$FhT@6lGBkyDRorB*w
zt@Gl4cozvfflRW`g?P)@b4uI3!nYr`5%RDZUh|-exdwhUr&?r<C;30cmeKr5&M970
zrXlz?2p!km%HP$FsU^ZgWTnrU^4^NIxe)Q<_H%1(`1Y47s&l0p|L?XJes{%g$?2WQ
z5Bu<IyW(}qYR=gY*y=)LU@Ebu-b<lt2eNjo^Z$=2Yi&d5DLoD~0OS*X^;M9o!=pU!
z+L@1+=g{pdiT&z+^b|5NRqkis{i3zdQ$z7jv4^7W?IAm6K4r(6h$%A#V0emSc46u1
zEOQetqDRyn_#TjzWRDOr68G=PmgmmK%qQW=1I*9Z?`P~6qVVUb_zh-Ly=~USZ-D0>
zI=lXahrg<kZ-bK0r^vy>wCkGfN&NR^0~?ac#zHCjM3ZmnKERurDPtBsdsTE@%z$o;
z|Jf_`vG4@<J|5hA;>xJ|Uy8iVWIveXJkK_X{bRf($PxBtlr8u(9iN5Vl;&%f``J!)
z-Q_O2kDhg^@U#p%e4Ps0g-|d0U*Ft;4n@#=Y`@m~4{}7e!Kv4oQkNoEf#1M<xP<(M
zdPNR=UBiyX)FNbbvFx#$mf;<f87ew0iwyAhjh*k=5#F&*Hyu>%VrSgHkhN>`<J8cn
z!;fvUX5v0C`yqV$h71O};oCRH4Rm7^ZhXgZ&E(byHZS7d+Bw`;@Gsj%sRwDB=;&`0
zqGzhhJxWe}hfD1t)Qi2-cuSlc|Ag5jvJ9?$zD+_N>$ac0HWoTt%ksbSz1D!X+P8uy
z@7brJnUB+*osut|M(nXUImKuPw`%P0W%4ak>|BFWZF`cd!6V|{?$p}N#dN%ycUZ&@
zjj=c8$Hm^@Q>V+j-?ptDaJNYvpqsT6sRNkzX`5HmOg+eGaDOj6&LGEqY9cv~-y&lX
zzuf{~vhX`huKGQf+649Dg8}{*NxcAGg|V~nif?G8n|B9z{b#50<^M(W_6U0SqUG-A
zn{%by-N{rjEHp!p9ytfSfWCb)kJh`ItFj_@BG>L+I^O5+^B6Ow{xR(#;OM1(1srxV
z)XQ8xABf$jJ=DeDhgR0=x%j1HM%q3W!0{DmvA*~QbG^=Y$k0J>>V*f|FLqbS8jiqH
z)>Yx7d|zVPL$^icyS%IC!t-PB{8%s-@?)=OU+Xc0T8N6d8)W>DoO^C3`XaP_5Im`0
zVe9MT{7pD`TOIFJ)j4I#ezBgUYgW5B9*H-#&1hFqc@}Rsdhs<Wz8xIK)<^3-XgjE)
z@fCcJTlWq1#Ji=|)W<lXZEj2{-4EX&{gTUyX^}BU=aw12?tW=&J#DX@KQt8M9huEe
z%_pvK=Cnu83x{LPLqnH2HJ6`Zhr`R!-LP}|4QDu!T`QgH8?dW4;Md%h$&KQ}hAe@_
z_Lzfrw1V}eYWc=kHT5Uv4D-$x@7B0Iz#dJ01OK?JbcJ(A2k-mmH6286olSE6<qv?m
z1DzcFm}A@Qb7hYu@ANqEc_sE}CHJCyH+^OD(NefIr#3s0m#<xzQ&&(EVytdr-{<%?
zrAqM~^$$38gBz%aUqc<RhxdA}0nTmEZiZbdZdg6JHVhv&Q-7h>sZy(}csD4LhkgS+
z=uWjyr+iqRqdWL{sqei7Eko?@8)C1rDSxx87rWIfZKa*yBY7Bl7IMF&btt@Uh3cV>
z+q15g_#pCX8XH+neLIy?tR)c#vhP5~(6PSI%YP>>k6bYCFI0J6<~wQL9t~s7_4S&r
zJwn$L(6t>t4MK-JwE%G6B-dYPhpyX%cABQkioN`ezis@zoZiBEj_Wy=II^w*T|+)y
zf8f)#Aas3>@dlx5=o(`4ZP4}_r|!!epm#5Hb?Sxpv-m#cD7ucPspRLQ=w!KH_OCUq
znnfp&F=QpamRvz_e;yu0(t=0WB_844Hu6vGx~2)VFRp}ty{uhVS9@w(68<kNLhDOg
z!_~HOc;9C;@1F6_S?gwM&LO^s<~Vm)tdFbZ&L&H~y(G0|Vj+Gpqt}-!__;>ozm0uH
z+sOSyrnEdcb!qrdAKq;P-{sig5cqEM<;dJN8eejz8NRHDjGX9A?kmmEyz=F}+Wj83
z;5pV6m-(?jGOpLQfTIoD#+>`><!_d*u5$6cM<nl!5-)Sq>s`IXu@bM#e%Isphc;qZ
ze@)r;<FDDZh9~Pl=EVa>_BryNCnWzRcY9IWOxtOA_Z(!y12=;`Z<}QAjkJ|DRN@Hg
zaz=~$7x=Hds>e6f3#`C`&EEkGI`7rr7!jOw-j^fai%|>lBsbk(PmH%naujkr`I{3x
z<U`yapuPgm$co6a{Cxvw2JZ;YwSn!eUS~#M+L>$d?jW>^47NLS>>1A71m{QiW`8N%
zae8qPwZa+T8(~k9z-_FqvSn?e37Z!ohD}441>nivHt52f)b87`BhY6gw}e*2zO3yi
zlf4t6o?tK17WN|X8@(6lsIH5G?^bH?5$F(s4prmmz`UUraBlGJ9>=ZtfN~uMz6u>A
z2exBs+w2(M>L}NZT%EJeDCc+7j;f^|R~0iO$<6Yec=l50^`;}7hk82p$=}7mC&}Ka
zyx9nC!JRzXHZA%zBvbT>g@}Rgg&ryDnyTrDtSQB0|1y8uYrg-DQ`vKfuAYtG!^fuH
zn^+N|=J_4y_H5H1>9gRS)ODI-s%du2v}J#Rz%Of(7w{gY<nGR#+OTaKYLQtAv#%oR
zT*`IKuokIh{`DrVJ-I$zUyDs9Z?HO8zh9&*<c4|#=e{l>&rd+>TJkmI5I%($dgw{5
zl0E&=<S}LOzHyY=E$?pmc^y30eereCWEObly4XX5Z_Q$ZW7GyN=Nfnx5{K&RJGcg(
zg<_+5zM63ap7Z58r|N@o<!@p{%VQ&dDtISd!&Qba=u6$ihk=~@bE5Ym8={L@&pa-?
zg$EwFY74TQM&^#A^KEu4$g9@SC#dP6W8Xl={h9&#FS_QBw;!9iv$`Xrp2T*N|Lo*i
zzJnz7A>Ox&@lC(T#<S6bO$kr6lyzWrRl8wljCT6)&f33Swk{XCjPbzVjIP~xV&&?p
zj)v7$Rt4`GZ=u~LC-U=av4>Zzb<Jzt4LI$&i>F|Nr(kz@Z`inO-BR9nSH=PK`TOx%
z#dq;7RL0#64A?%UzR2%KwEYp!Q`DeeffwP0rQ+@AK6du4qBG;jL1%7slK<YZ$Zq~1
zKi<`?6`p+GncGQB@#z${;hwcWE`A8Q{#ND_IO3lxPAMpp`DD&s=9E2n$J7Adq!pXO
zoKa`Smi;n6_UKvSjugNB&YWbJe)s72gllei7h_N3Z>3D4{VUii<_9K$VQw<I_JZOE
znR8kh-?h!9YZKjs@1@ci<n`Aer{(vU&p=l2X~ibF&w3;EA>K!VU+{3xscO3AwRCvU
zhK?V{CSzYiZIS~ZGr~)WtFWCrk;{}p49PpOp(WIpBktQuT_^WixTmPmtdw^9MK28g
zW(4Q`_>}?VfcKPm|AW3&*vL(V=gbD_SB{0?Q7`jv$|_?q^H_Y3lH4#;h1?xK3GR$9
zqrupW?~hGiY^1Ve50Z=__Hi|KTizFjFZ}Rt&p+Ag?}g?$PF(as`injY+_RTZi^v!e
z$yKQBMY7<@m=TF7w5<(ns_4UYckHi5#_PqdI*~UPXnhgd2_0SYIQoU%6P-8!4SU$@
zAL>cuR0}>t;w9{Ck@M~fnH%4gPIR+B+6ygMUG)KQ%45ra!1vsB3>w9+v&W71<|22U
z1urjUPgfQ1zTAzT==cKLQ*GCVVou$6?-E?8UG|Fqlm1S_)jdwlhlxv15UZZ(bsBHE
zcI}(RmB>^o?n(S`RO*N=_~0^cDkkE~JF&?!pUfe1%Y1xKWu<#2dT7fx2UxRbKO8X<
z@kVPDoKxs{53wpb@lucLDYdSay-(;2^4o)c^deI|@ijx+*5!<C<SBkmfejY^h%NSO
z!T4U{S>{-zc~JIy!UtsEsrx$ecT{XsHFL^04CW=DQ)T}O-;YG}+z&~OaESMf`TOkn
zc%fl@&53R6R)oYRh&*E3Qt*av{p#-s_rOQPc4JC)yeaDuyk|v?Py0<f^f6$%SnM1;
zIs=<Fo&6B-JAD!M>}tkSGAHlx&L}AA1=P`?-52;)0JM0y9y?I&)V<921K6vKy>jMu
zbB}iz^|ubnwkfm#I`hrQYlPN(_aGl#`{UBp>#~YDvhcMZomBFDg3I{vjRJpcXKsOU
zwGD*!M^-v>Rs`Q9SRpd<g|$}|uYlIeox1Eft0%Xdwz{eX+xDPCu0lO!=rU+SodCN-
zo==^x{g2rf@y))!@nZ;ljwRn8;QfG}dDT+CJW`*CNeq(l`CE5HIS=QfwHbV?P2HVX
z#%VkP|NQ6n;bL!HUh>+!{sxPDbKPmAjyhg0;6J)@me@1+aMtRou+*-waq=#1Y7TPR
zBry_l!Pwmqkrn?P8tSZduZGc&in<v2W~tP~H$9@W_m!-533CqnUyOJ=F-6^%!%kys
z+G)5X;xsh#H*!yOIW^aB;a%(Kx`EK9!alAWYtcPB?dFw=+w^I;0r|<u``G$@f#5ud
zBTsFkso4Y5mU^er)#I<tm~(`#vooy0HZ(<~b}Zi|DF_UWD|+1fu~)P3;W^oVyq~|f
z!#ZM2VgPV`IE;NG4#=>sXk)MP5+ClIAv~IAQ%fa3Us&>*kaOPUxOhw4Q`~2d9JJ#b
zE69F#BQ|bN=yKvik8eO0biS|^o7Vtu?@R8Mm@;Hb4Vb+I#_WDm&3>_y@jlNQKkww#
z5>qNQ2YZdL%rp>V9xnhNas<Cdt<ls5u}JW)l+#d)Jz!0y@p}C687Y~ISf)|tjen;|
zyu{wsOTgPxTLrctW^E7{iH*eO+Th%fJXFN*xRIt8|IWH@li1oL4ai9^@Kg!^Wp8Vt
z)&Ry(i_{i;yRYepobcTo7atkW4jP4puEzP@2L5@g$dULS<SQ!o3U+7<W8X)eVXISj
zS4!Z&j@Z+wdkNjUE0stfYY$32Aaxe{N<Y1aA6qhD7!RPo%ykl7@;+VWEj!^kGw#A(
z90|Lp17{HDL6hUPuILAQT>HfzYk5-=7chq!|84<!t?+S7{I{km9M<o+>F*h&TCh*j
z=A?Gbd}HOhI|gTf=Vo+F*AP}yi(SpWDEwEN_$sxoRsNn-UdP+y{(R@iudA#*EZ;@x
z>uFvy#F~iYSLOHFwuINQPYOO_*NWk_`-s~l?#72)cSnD{_>DxXk%ouhb|k#6#SBv?
zz-N@Sy;vvvXSEH-elIH$^ZLGm_W0o=;lztW)eG~~u)f4P26?&DID50~O-ep`Vzd7K
zICBZjWKNwo!(Z$KIx=d{Fg^_5Pkn{8T8<s$9E?>>jRn7<=^$&z)Y@1(rf-2U$ouuT
zN2mjAMYjAs#hi;wj2<gN4h`R{JNVYo$e4PpXhn>5{k#%dMYGJq_^eNj9Y5Ho5$s9z
z=iSgXU<fX{w&`IPf5TqX7`9O3#Xi&+@f*2rd{E=%uZ0ua1bEehm&gFL^mFnNyn>uJ
zzzz9lO><<wG<Xe<72s9h!G1~^%O6v(ulsnl4&x<j?oodqWWVSfI)yH2JV)jeoRH^w
z!Pk8g`Iqk-+1Rud=w~<UnzgKJ=8ZkW-!;l%>jY=;M{ld+FUk7#WBd+;o2k9ZI^*dX
zY8aQX4$T^fGi6ej`2CJAC}Ztu)YnTxHN+(zb@6lgegQIl&z!_IGs2o+-oE?oH{kIl
z#I~Q0|FzoA{!02UKsR@N9^KzeJiIyiYwAo>WN+iZmc+|uJ@>5S`OtfP=}uj<uX~Gc
zeGqF*xw;--ft~&B7S@rz8h=@BPkh&$8Q&nW+HbdX6#2FYdk3jGP+uI{GOe3Ef;r>?
zUqw#7mmF?Ja+V5LXZY5MQg<eQObv&c0I=OzpEua2M-9vNkY9BtIq3{LW;}vDCI?h^
z;w#t-vvUSClC?3eA7fm3Mjlp|Sx{~3zcsKqeiy#1W`V5z0kctY4!CeGzG14YTR`6$
z*Hu#gw~>3buBOx!tn;x>byR%)pZwh-p;!D}V$TMM!<a|!&pv9!JD?%F;oH6Nrqtj}
zAr|1B*!WMycME-t>f~Q3t4t4Sos1!|T)rm2o7$Y<i(S$*)O*aPN=?3ukJQnax0*d+
z{LMbrCy_1o?XgD5-jfWz3%MIp0~#<tcbmXh(>hORMBh09ji_@O6?RPG-tMVoy2)H_
z4RZwY0bja0{(FcvJLf=m$-Unbw5<|crLWLfXyVj_Td<So3f<ki<(&udH)f6IwTHjE
z9eIwKHSoDXcq;2fz$)+HR*aV)?)h>Rqppc8mE|h=+p;{FHOW60d7@o;jvVrKo!AZL
z7?vk=oaZC*#5K>6rx1ND{T;^APy==voSWgtzoO&!%yGXaF-+-BN9%$@7p_UU8%E$|
zJoNRRO=Y;;uV}sqJsM>HmRp4#uz8PV-q1{Nq=sjnq$AK`Y4YQv@OfwgeEy$_@yU8V
z9)bh%vlQN3$a!VJ8`e(^bhLZwFkd{iRP*I&aEKW-;cjCyyleor8gOVJhpt9Hgl-ap
z-0A*A@Znw3gS6+GeJcN(x%ZE=t19pP_daLBoFOw|CK+Ic89IBCsDp_ReyBmHbL2)0
z)=K26jd+^b)uW^}z7pG5&(++{2@Yhico|~UAk;bep&k{R355#?bq*mSwcpA>)#8ud
z8HCC~yiK%t^_B_ezCX|2`}~?SNu>IH^^f)1d#}BIJnLD{^Q>n*>sf2H;cL;ImkyD0
zJ}#XHUFqZg$I9(y9Ejf<`2We5<xb!Vc-UWSWySo9%V}ftrk$yRk3KZ`ay)?{lLtm0
zIpMiq@egdPw4){+bg{N7-3wNCxBu~S-QCr7i`FUgE9j-z_-8-vwY$Ce>fR=K<zKQb
z{0EJdN^QYE-ko@x|Ec-lr2axx{eKsg-=K{1`8UZ}k!37!7~7L(AC<nOGX{e_K?##H
z;{Ogex60L=mHN?tum@wSuyLPv@^7~>m@<&vmjHix-;jK=q?41@(fFjX7dc?}cbX4Y
zsILX_vc+?rb~gTe{<JqG+y~j9huvCp2KcB(H?wv2)2{5&ot)rwj!qWofohNWZjs-e
z#77Igf%_3?(-Z8onww8PLl>5&&4;PJPH58fp{YXEUb`gYX@o;B{`{(#cwz+pJWN~m
z%Wl-G`ZKE>&c*v@{vAc;+8(lwi30j0c^K2Nn^&zX<l-O6J~QR^hx_hgS5Da(i}Gy}
zE*rH?X$)8G!TvDqAsb*nnS8J6+i|=$3f61yopOu2X`_6lJmyS|e58OG9xk_imF{|#
z&p3u-+CsY}quA5x#BN8v<<j``LN}b1=)Cd|7cOs0KQ6yW&LU4TK4zVM#;<2cyB*v}
z&*_f;{gnA@LT68>kIZV_7JqGL0b>;BA%nAD!#@Ui7Ni!v`YY(!d0^JKb64h)aE;~<
zW*z4OX!K0+6zhRmr|a6*b<B~q9v14q3&F!ybg5mmxsx_O2Yud&UUiXsU;f*%`|@uE
zM^C{=Y51rh`SX<ep7!6?TIQwqC*^<KQgvTzOWl2~E!@}IvI?1+J_maD;w|Ybs_tuj
zhVg47b&L_FoSytTrw2O<=O6IyI6X5C=li}syqopuf@rW=xK$avFZhvTJiDiIH|w|m
zCH=>oAvG26DY8w6GJeFoK>pc@yuP!sy?Oq%C(+OPHFk1NrBl9}^&WUGx|?+Yee^GT
z+XavI>rBAwFC?jxciqj(+1q`k#2NUda8{J9Yq2*kOCRqpzUI?SsWY6ei%)mjFZ`Dv
zv{b!EanbV({+$*6kMSG~^PI->;*$tbIVXCa^}z}}CrW$TU5(Q&uPWobPc}}|sO*;S
zIPI$m)&G{0zd9}vmUqe9oc34nekq|fjC(C{%6n<})ccatop$;LeuJ-O*f%lb87-dg
z2X_HyK4tf^wru<{b1tLb37u7A>0^J*nx^CS_yZ39R?y4?v#0xSX07tug)VQ*&dCVU
z!876AtQ~eYE8+;bov2S^Jiz(5nQID~|MV2$r6RmlgrAD=QxSeD!cRqbtq89b;j1Ei
z<+TR$M$r{(Ys~$er(crPnw#$M9$Brpwj?w*&boL=Z|RrL$~R+I=97g^?q*Feg!PC{
zv4P~E^BiXb+~?oqM0c|`2Y0i&&6K@k0rRs=oHkmy@!i3BpAS3f3ub$Rx?@)bb^rb1
z>bm`<x|`LtyTf%B(E#fmoLQXk?+@(k%htJB@v8iR&@XzBhq7-o9dVmC4isGE$9?#v
zl+Vr3IXW-rylu;K5$pD|@z&M&*m}*SF6Ci=yw1$B^t3CBo}jx~6Y|@!wx3(*l<nVZ
z;x2EG`~2FuL-jG_O98%jbWfdo54vC%^>V%q|B{;1{Lx*R=aX7{!#~GyRCm|o$fedo
z*MP_Uc$_0W5ZsT~?4vUc1o!wg`<~i_orw)Kd)nQ~J$}5aF6^(=L%i<s^IYV`oz6M5
zP4%c>@V~)#f;;>!$a06@Y)){b7Il6;b8WIKGf`Na`K+xqem?#2WSi>H{ea8z^x<D*
zgSNh_(5d?eGvCcZ$94B-PK5WgK3p&uumj(v`X%G#XKc9IAL8oq3a&C=;ok59`=Wxo
zX!n~vhVRUuCxiPqUzKEB56bd?5tfq=;rL+#IQqhSJnv4{zyUov+7BkUg$rbDp1Shs
zcP7uq4`XqrC5cR*06(@T@@xp^os5S+Ku!nu*z#mv^8;XgXZn|<U2=DxIepuftj-AI
zPLqOjpT9}>J;Dz|N%^i;?g@Q6cRF&<W9DX_x+nCB<SBwfG$EM}pC%?8<}2^r7UVxO
z8Q^(crG4}*cbtZ8Gr!q5`J=mV?_{2qYuk9C-G#gOP&;?wj%CBUaQlP1aC6*+JCmh-
zyEs=~XCvDltqy-CYcv({EwFT%?F`s*@N>k+QNHt?*w-1u&%h3P7iSaPx@yGvdU49q
zjexsW)|F4e$9K=h4}R475$F6s`!Vc;txMa(vmK)Q26cBD`SR;xx3(vpUEI@ax+!C>
z`3Hz+(p}U;KIj)aS9m9GUB2|eY*YH~Y>gbm{_;-riyy=!Gyi!T_XIh&3PyY<-dQBx
z>(bf3+D|#!!6t%-(%%rwe|N{mHP<GY)3*sG#^1g9tjief_9U1`%U_xG$C`Sq{I63!
zX_%*Vtjao{gTL{K{L~)yRphu=cMr0YGneD~znU_8GP7C6|3J6!|KNT{@0Rc0tmWJC
zy=+cpo$5K)Ay=}x*D>>|WRti3KKz~Boa`OoW0&v)zVW%4{T%neT$jeL3Awq8G_ncG
z59l7jPWj;19pQZO*6OiBx(xGxTdfUm7LK?RDJ&~$4}HH2-S*bZr*)2aE|1<KyvUAW
zWhau@o8CR!n*Q@z{9Bn{4e%nKGoH98plQiByL$uL6-`T?i55l6l3^w<R)l;oQk5s>
zn9OOE$9Vh6Fwd{5@}z3>sC?Bk^lZQ{TUMf@mhX_gE0<bwSKHDl$x6FJc5(R**;j1q
zItBjBtPJmvJ*0WtjIHPKJexhnx<j^YXyHX|7iR14knP|O+0s4u5(an3UfbXf*-LBg
zkY%6Y-RS7z)91SUUpbD=@fP22e5$tAk1Kx1Hv7j|!<u4vZ)$+ogg+Gg6JF=!+rSx9
zZ_l=!uDemspbvF7YF_KiySN+G%}Mqn+ZJ!hx_3y{(T|mTQ76NDQKz>dOP=c}dd{t!
zVWT_ekcWG!?wq@b^PEe68{Rp0cB-xaF5P!d8xN`;*<YzE8^~R7`WSQhC7;=|<?-3V
zsh)eicp&qOY^(P*(SNKE(*KBuzKp(wkKpV>iy1r8tF<14O+KLiYmwWB0{WMZjg9`w
z+0GjJXHP8aE4M~6-e|V%e&$xl_)uO%WlK%~;|Oacw+e<LV?pL+_=+ZDhrsK@@C5a7
zCx!8w3%@bXc>}(zKdI#ljU`skA5#zSQ9Y79)iP<zNB$y7+jm;q4@GTv!nVh%+Wx{-
zw0$xD5Or;jV40`w_)lPuxU~$=n``00@6yT*+O56%YPVC!T%$HS*QPr5t_|88yDVt4
zWO%$Y^JZI<lWam>j5hhN+!pyhKqI3avTs)RfpC%j-E9e-<rUDtSdi{5=)a3<Wi9>>
z(Rdul^}WCx^;4BRFOtssFdO@U|9`j#1zzS{`5t7ZlP@B3g0#@vDDrcRwFcoc9`nB@
zI^Mm&&&@igda>Px`$D!el)D9gMshcPIHbE));YQsla6~LD8n78(4AXF2eBLH(A}@V
z{S3JG8Nch>l%P$-m)jNA5%fd+Fl(6fgIlO>W2SkQdGJ2T@|g9B(O~=s^vCaT{(<`I
zGTQiA+WI^G<7(p=xQ-XBKmLrn1<PZU#<1Lg%|(8)%}H;s#lO+*nU~r)QKXI#kGrg#
zH*K?V%-;X>QtG(V@t5B3;PcA(U5|geYc1<v2Q8HQBJB6o)Z1HI?;IRGDHwwBJirU|
zS>5MvxS#rWHTyRTj^{f3e={1qkv=|ywqtV`J;V35Im}I*eZaPdb>c`z_BSD8o!G7D
zKuyxkYVMvZ{gCo-h$_PjJ)cHh934U0`}`lMzOl2BC#HJ@cWlW{${kzihSEEr%Xj*B
z-H%>`9`GfnD|6PYV5%+iKFN8Fg^c6CP;{UZ>4wj%e%g~{o=BPCSoDkDH`Ugkl>9u(
z`HHb0V7rA+0{zD+-#Lx^4b$ehqasSLJEsG<;2H9<&hUfGnX`-s*l(_xJ>CCf;SPU_
zbsD2{ZTXGZWQy2irri642me9NSp_!nP5QQNUE;Sx%w;rRS<3t|nm5^e>B~QKPRqLJ
zpLZ_SJ&65THwTa9G_D9g-v0ak)_*Vh5N#Lzz*G2IURwUv_~rkZ;kZj<f&UTuu-q3R
z{d@p964IOUSM$4n#{C-CZ}q>VGQPc7bqW@LXBdC$rNRGChtIc!&)*CG(=YhkwMrgn
zZ-<q&G5qI+&$BNL;-5Epw#(9fT=^cSuUJzS+~3+}wp!z};-z6<$FyFZ-;#9}%eEsN
zil#ItuEAmd4@3KI?Y%tNYuCws`TxtkJPvhXd;E>x%VYk5N%s=Qq)X8CFJUhIJUF-{
zwDTh4Mk=<xZRmBrOPjT)iv6oe{9=)-tlhhuVU$?qwC`pfe@^<agMAeHY)*Um_jGO9
z<%~iX8soPk6L;sahvKg=0?%%TFIF?YyXjrQUik}1hc2J!PP)-q39Ox9O93YAotH3v
zUxIC+eC`>12wvF7EBnuC2m2580*~MjJe;Z1RNU=sA7Ib&veLh@Zo7EIY{$UI8B5zE
z7&ktveJx>GoFTxz99t7Ge)vmlsj~OSXQ8P|nskrsw<S+!Ck1wXThF#N09%u14FLYZ
z$K3&+Q^-KA159WQiM@iaW6u$|W<4PO;F|yNdO)Lf2IoC5zT8yrqr0$ge*_sAo|VOZ
zM%M6IpB%OI>_sdW<4a`guguT1{wkko+RM5HV=c0V{<Uvt;d%Hh@Q-kuF8+0C{Ze}q
zNQ1q=>1tx_jI{*T%kT~OrSLok@8Vl#XK>BTDaV8M{4dPn$H`dhV}HrvC%c2OZ4j6X
z;I)dT@qL7jwQf<h2K1Dj3m4k<_ER7JsN}1mF)y;s1$`d-jt{Nv*Su3_Y}+}4qCK5+
zv9T!HgD0?!WxDvM`<-(5)FnuZpM=syXZdkg#rAYTFokiW2+f%p_I`6n5l`*s7QG#%
zJkgkZUR5@01)lAtKXW!bcO}TLGl_%#57wWq{UH7z<67guu3r#u!`D7I$zjh=%GYT>
zxOmEVJ9gTX%ekfIcS8ByXJT`cUmm#c-si+GVLZwC>l_@C<J+O#?q!VAz}*smZWXxL
z73_mu=_Jy-oCOcszr&8wGmg5Uzl<y1NAB{BoxjY{IJ0+P>pjlFf}^vOtX<H7>u$M{
zcKLC4W5Rq$%K6!UhF#Q6ERb#DZrgw8hJG+DG5kbyo`mFe`f2ea=T)LJYVHfXk`3iF
z{$|mYeAqb)1AM^ybJzA~f<70%qx;UZ--Yj1TjPMvio4^j1FQ>85XY0V+T7NU{`Zsg
z!C~!@vO25E;>=1bOHY+WzetXZ0s9nZbBZRBdGw(NJ*po4Lxz^mEz~{%t)0!4HFa|4
z;L+cToN+IH@#SJ`YPI`lf#3V1uhM5@tu_v2%_plhwubdtA3ss#rMHK(oryR3pA7oR
z^6s&GuF|Ft%qCzXH~mPs4o2Tac~kg&iBDz@RL;Z*a2@i^r|H9nc$_P<-M78?HVcO0
z%Yfkwbna5=BgoB8_6BLsUN5lIepfzHt*N+|h~y@;(8HPkwssfA>6|z7jXFt~<G=gj
z#{+1#>4K!2IE$e18CtV7<B$HmZ@y<`{Q-KF?42WTu?cBx)|gD*F8tiWak+zW`3Qa@
zOYA;7>^cdJ%g8KuRXb<N-QhH?!heUcy=j%lc~&3e2@Dzhd<L??nH;8nV9No<{tNN*
zWDk>clI{3;+PO+Pmk6A0hqg>sTOC;!KFT>;e#$wq#$#2w1$-u2F&Ta)_KP|h&iT4_
zCM&i+H{FcP+M;#$9KJbmS3ZWOE3g;Q`kC`Vbw;A}2;_z99bL35#<_>!lJi5{e&I8-
zLbPgp-JvnYUs$VWFfJPI7%N?TD%=YvOI_8vi0&BFx8#-Zrh1U&j`l`Q@y^;&*8o1U
z<@g6@oux_iboNw4=dD`$zop)`rR)s`CdRWO^D)Nm&dfkOao({P*vtFERh*f)R{MHW
zt^M>_f0xI;UVO6FiYEN!j*~eIP2<~1K72xB`1!l=^j`M+{+WD%INO4>n~&`-P&PUm
z>pQ`k54P&A8Pb{@FSxrkhUhyp<)S+}Bie(^_@V#hyD)SIhVafm+k2os)Boyk{a3v0
zCGgO33(h6#7i>_^2m09I-r_gf65>IP<K}Cy4jIpX{9Z39l0G_523dhEg7Gg*$C;R2
z{cD6rhrKBw&Tm2%4~4#%VSTDgKAEZ)zGzi_%p1k;(g%_CQ#_IPQT<aVsJ|+$_Dauz
z;k1zUR1Y!++0xk>L*FVmi5xf;Eea<=K9{}8;oge~SMs&=S^sCund5IM9U{^z7?+sS
znO>E7o$WP2x7Gfz{Y_i%cXzE&x%gmi{hT|xGUhs)dbhWx-sj_Q6!#>Pu~&8#Zq^-h
zPY<xZ$DDrO06G&s?+e^i&o!@1b-%tf)%}vwQ*9SroLcc#`A@X5w+s8_)amiu1UzTw
zVqo`Vk7a2U-y`e|On0YNcrB^knU`Sm?B1HwJbCW`dcpQh+1S9Q&X4kq9=_yho|eBm
zC`&ej;M>YN=c2Y$?<W_q$M2j}+e==tHRpVhv)Rr^-%n7^IhzKueCN7S=cwKp_@=+r
z{}S}?$-e^MeaFcLFda?^4_p5|Hefh7k8?2I=XV?r2bm9pgB6{eWqN%-Yj6i;3o!cN
z3=(8aPXI6UVrP;xYWvPT@E><?sQu1p(Eb;K_WzT<@#9(Y6i++Tq`Ok4;Xr<#-4z^s
zmorEL9H`8#xmbvY*-^v8LVf3&3=hJ=fa7c$ja%Puy(b>@`z!IAd!OIy`A)Xd@Aq-9
zkDCK`yRk{PWxnaOZTg&ZX)3nolftKO_7?C8P5wH5nWAfGy*KkkaQJ)FndHobH*khP
z%<ag0&*D0~B>PGiSX^u70~Xh6aaSY%x;aC(=hgj2gX#ll&S+7%f)+#ELvwt$r7srE
z1^xV-?gBlSI;Y8n{<>4Wci#p6-L1Zx5Aa_)d(#84fvvA|^PJm=U1;wB>mK~GK4=Td
zg??2ZaRL4*tM}&9*)Mc)s;#+ytIvG8<NAK1!B@rlw|>{rS+C@|zCU%2&-%rP_Na9E
z=hBXzK6vK?_osS31TVcC9_rhXTCu#DcI}}K{DAR;Xj`*7)qVQyVVi=uDqf=A=8&H{
zQoUoVjh=kbPp*i)Wc#K&oZ{9C*z0V24>+?Xps5zoPlcv9Q`~$mo-;fdU7oY`Y;bix
zZDURT^53OhHzPNGX6;(({A}z0=iD5$>+sKnPtsn;UMcY1&pZ3QS9G%H`(y0&euD5A
z|F*<ZOAb@UkI*fi<eu42UdOqtyU&FO(f5^?x#X_fH?=zl8K;mR(AV3+(K$YQcFw;G
znZlaJ%=)e4CG+{0PL)~#?Re16H+d($WTyXBd)NHk@$azrR{w9dDQyS3x#v$2$NjbT
z{v`2QtMZi&pU=MupPbtv{_|g<C+kdq!F|#6q5L82`A^u+4WD}l{P$J8Kg_stp60fU
zVM*lj6nfS=2VZz>gY7Q9@W^W)*_>m}=b8S+xH8g|StPmqZNgK?rCm*1Z;RyebDf)>
zaYx~c*399ocm*Da<tqFsx%}OHAeTR%M=rO(8|SBb-oA%BQCC7Y>`nXgSEg26ME{P_
zpV|jL71FW!SVK?TZ6&#U&Rb6hFALb4kI(eGPv2V5-k>K}Z_373Z|d64UaRl$9r$Gj
zw0M}hgYO_e`*_Gp-$MiM?%0Zr!15>KtG8x@ciEXzJ^cgLx0@Qt;im#Q{H1sxhd;zw
zH}CViJ%9c-XTC$5)jsyMLxcB*Fm(hl8hprykpGSE)yBPfV00V9cwN*^x2~OTrJZ|`
zx3iy1wfP6P{?}t&IxipkY1%pwM~|B6#INmn?C|)h$2q&y#ZMi-BKjSD<q~vW^c8d#
z=mR^u>98yCn^(TAYvUs;V@`I{UHDzUFM%wMA&Zmz8@sk}^F8~yTgt=t`Z{>{-pod)
z8`*y8rk5R){f_W&H>cbu*gN%PuWS*mG4>dAqr3bb<s{jkakt6RZv5axN8O?$|82~>
zH0IyJJjTX+;?AHgJ>Ko9?mxRU)zf>By>;iO+CDT2j?X4ua!LMKZK>{;twb&igmNi}
zi)e{`RM5fM0Zn<(#m&1@-ObQq|LMpPWYfMpvgyW6ZalyB1<5APqaiM}<lFoUXbQdk
z){1-z;;{Kv$*11tKt4So`Sdc@cW>S5$LZ^D97K;8-Sp%5!L9F&cLXx(8_4{1?Bh(d
zFizf(YU|Mc&Jo-DEt_BO!P}5g>`gzKVq9R~=aZE4^V@)ld#}gV==|t&9rpjRUo5p^
z9r}w$`vmhC{k>;&(<aWtTIn!G!aMGD^nu398RT};J*l2$1ITvCW!L{Kxb1$=#i^b%
z4jPXJe94#v&(iJ?myGSSSA2^tSu|&KeGdG!g7Kqw&*=eQ&&Ok5hkltumCLj7%DzMT
zWxU#>@rrflHynfq`1g(THznie!>9JH{dfMIv(DCkJVskSH;{7oz_aR~o6#e4EdjmH
zwEFjLb67J%ZcRD<muMSjdawqZ_1~y>Xv~A2MtSd;>GqFW9CDYqf7?b}uE~Fg{!MiH
z+x2{Mwa)e0xL*49QD;jMU4O}A+1EHai)Vs)1$$V=@ZmrQ)w`c{9QJ@F*yFYf-I(W-
zUF>z<r8x>^JDZX*&P=|8bB>nTnGhQmuIuC+m#(z-TXWV`3LPZ1WGqWrS=r{4$M2gh
z*Dv_CWCIwg>Q?%oZv1w_x}k%x?slhZ1LsD-m!q8hHEMNE*VRe6>B-q%f0{aL>Yr$0
z-|()D1K1;@Hlkn2{<;wxWlcMWXeV_YubtLD+N7t!e4e$jY3sw(vDWGc+M+tJ=~mSd
zv`2OLjoTBJZRcxP*_)9go|Du%1-!>xbM0GGi~LmT%U-YSMC^C%-0<wirVY;yv<^MH
zu5+km?P8t3IP~lm_BnCR0ef99EN$oR1jfq(W20;nZEw698O^@u!=&%xZ2FDx<rm%b
z+vB^oe8x?tUn_sE?QVJ|n^?*GbnzDV)Xd#ZqP?Bx%d_aM=oL$DUX$uhv%j$aYWA*v
zhJCB+Q*H0*PQ^EJR?s!?NG<vM#mq5YnsPt!Qu<=&MNQmA@&tCQrdSgBbX986OV_0T
zO}^q|EzW0;%I*}Ft9{4oI7e*><Lxz^=i9z(<9~NnquZ@!{<|F*Ix~+82F;iDj;4Cv
zMOy0Z?k6An&*IE~pi5wYuSOisGU>+t%~>RFcT+a7?J_UFCFMSS5oc8_mmSz(yIlM8
zoc?CoEu3Y(1+2|4WPw$8>yB)A#_Qa01^8V^`G4Qe`KQR9FE+U=y|`?x=MO!zrUU)0
zi!;4wzmH6M*XrY~+ho4&oQh86o=@Lou7lUw);&g<>oc#(y6MhrXXeM82l`BU@k(b2
z>vk%48RhnO4=r4~*uUR#w)~uaS|0Y(y~1nQPd^O$DO~_ZeWjN-wL2d}POfHN*5uip
z?q8(e)K~923tXM0KJ!~0=5Nc^r~lQ?Q9CugJFEVGW4b8|jpP%)_PZ<@8_2xJL4R5I
zSo(;=zQ-3v(l2B?drH}n^w+b<m9b9$y0Dzjhvj$%-y741!g8J!pFDkessq|^$G%4%
zql?Td4ELV;D)YtJgm4VLxkF*CwYj<UQ8#ltXTGD4!ULTB*}hYKWasO(Em==HsQ;<&
z1!eABWBvJRyIa=!GYx*0m9if71+wS{?j-n0g#T+tp>6updn|pr!&*g_zIfky{HhiU
z*Xe)Hp0(0xhi1il-kOV&&Q8uG7)3_tj)$&`l5P`c`O{bE(u=$|!Bf4QM}f?I7@qXt
zul7nGwzZFz+qLMwQs>f9<|~WS-_6ptxU-V7gT7vZO(N_0KZf^18We6)OLlOE>*A5j
z1+0m@U$`9WHs0~$@FwHrbNEOPvyRu@ehc_;{2NIV;>TY->&&I6Wdmv>d~&M)9`!MO
zv*Zi(jd*td4dAgw_rXGU7iR`!Ym)!w2!S<@i{~#-cSah$d^n_+hqD2_TolsFCp8X@
zbuQ*^iOgR)o$c*B*W>fju5$pUcBQ)CyOXmAu4mu!^{Jk<;QKwdq~hzq*L!K#kJdv&
z?*PVkz`v9;lJFmxb$UwIj;0@SI*~6|S-F26mirya<C7?N3FR(%`ZbjM8erdT{iw44
z5?_SA+5RTvPO7JAxz>hsjx*yYct+l|rGZT{Cw*~1Un4d*>USJ(WwYHI%Q*vYY1**R
z>mGW>XJ2fbx$HFq8x~52T(jDLcAFFMse3B(Z1HJW{ukF)__Q59y=J-p9sE>2ss2Dt
ze9&kP+Uh_)Fh(yz{vr2FKHMJSgS%3M5C3z_olZt(!<W)cRyvEb&<b{G$v*avBkL%a
zF%jBkPNn^O>8~MksC&aR?WD8%Tj8P6D4jnb`dHTm?}R+-QBFVdGbl&<9s_!lEC|L3
z<ge%d^)_gB?PK6{vH!hBG#1K0XuG+T9nFl%NA%gt;r;KMT<MtFIrL1LGo?13WjLk}
z!QDIjGbwk;Q{PW5`R4kdkN59Xd;AaMi+HEgDI2ue0ikW^Jf=3z*FM{OXuR@|5$wB6
z=4_&GYU&s(*HLcMscMtoxZegv3ond7Ya^+it9C*Qtvde~db}~!Ej~Ewa`1AB_&|Fa
z$})<2U#yIhe3G0hk25BtR&n;}GWC_@Z>#3v^zAJf?z#_TfcU>2pFvx#5Ak!FukUp?
zYNIhA?Q(BsnO{24Nuh=RwaxmVLf@PN@((I|3v{&@x{Bztzc-*OX!G14&%AW`^<M+W
zU#Nyv@@8zO|4qf^;JIKt@rUnsyqj2i{Ib`{zWn=!p6%q!B<B*wDvx_vv`3$NxMusg
zlkxfd1onz4Y!&OURkWjv`O?p}gHzU{7d4@eJhvcyv%`6%A5CQbFXz3staCR!+m3#=
zoI5XH$m?8?l}+w`$zPMhU-o;WG4aCEM;U+8w@L3q4tAl(ba7@ZXK}Z8Z+LcH>rhLA
z^DEFJ(5JZ9;&k+d<+2rYdhX4s)B3LCKGRm6&BUE*l)a~;_&4u2+xd$7oc1#=aoSfA
zT7D2diHpAVPoaf4{a;WOPA4wa*21~qe{omFbz<kR{;hGTUwZzIS?YNXd2(kr?T^u(
zt_A2rnb&3$&3gXVY~mC>2Q+p&%-3!^d&^l_=?E>EE3(MBbuAag+&1|ktc*u;_LXg@
z2(Mg%4wuPDJ}z(Da78;d^X=#@FTDZ1t;zS$Q7B7&7|84WPU?#u_xr}3p=WxVD>~dC
zfh+%4q-$Y)>-i#m$K5IS;rnnOKI`|fPagXNHV66_|Fuhs^f~u7n$2NZX?wYB?LQO_
z(w921bXS(PVjB$R-?wV)#vXX9=GRLnUl?6F6K5TJc5P}2cD(NPcQCibhM9O1V+-Ta
z-u$w`SYCZ*_lUGzME`NN#fZ~}9}V+)_tx|Q##`1#f^uET)t*J}ZJ(T_Z1zPBAA4nL
z$(<kP%&h)YPY3pgmtcQ*)yUEU>l91AOW6TkX&*9c4$IMNu*L3ouxEJ7O4sHzrumnv
z-|lod=h5PpDbDPIq|3%U>T`^D&$9cAtiNp@!`}B5*8iie%N+XudgLpeMPI;6vz+02
zjPkadUV%>4mPRM$*$p4q-OK1kw*+#a19^WNbhAGuzl2S{@7|kkbMHkK+y!occf?7(
zZ&fUH1!M9R9(08tP1_q*YCQow^?;|IRA^rYKlV<0;K8vjvk{!*%f50DTLo(<|H3?e
zSz;^ahlMumwyis2yyFA8<Y}H}yAIY0!gu=C)+em&z?N}Ns`nq|f8Mgyi;V{5%<kU$
zk1A(|b%XXc)(AO2XYXjL?bV#!$Jyj7wzOgcdsAvfnl+d&#8SPVz^41~JDB$~U)s5b
zeAs<IaSOJS^%dJmnzb08Jxi=rbUbwnYc;Dk{X6HLeHGZ3e6ByGJ7wH|>Bn}8pD1(z
z{Nk(h`{VSH*{B1Xd-yJYNa2IE;T~Yb<}7?XeKzg7m9YT773ZDUglL1UE$!a)9c=q=
ziw|JiM^D&GofZ7xqx4SZo;~vYHap22T*clQ+I_&)|M^4VO1|H!8~=XQlMn0Jx#?%r
z^MN>P2wID!9-Z&CWFNBerEg8GSc?s6_J&mN)EaC{*quhN0%x76-k+yvqv369(gA0p
zyQ7>b)*j-FafGvc&@FdwS{FyRkB`2bdt-FQH)lpkFaLNI?Qs`3`p+etn~0o*c5m2p
z3hQcLBj4BK^zVK<uW0M*kM*0azXP4!eG<O>(Q52G$g)z~*2Qkernl2KXQ0zVOa3#^
z@y}<k7-BC6dSc7aGfgenI<Ql{q|?8E^>pOKQr58+&)_rO9?Oef)DP)(tj(Lgf6)!%
zQ-4CdiT?=yBoBgoG4ioKjL)6&F>jU+$*t*^ZR;ZM2y=LB5~JM9Xa1ocyeoZUIdlG|
z%=@=#&fk>zQ~YLUwqqOnBi4e}-N0PCg|ojt4$gPWM*}!pB$vZ^c1vZR%^8_4Hm;7F
zmjhqIbfi=592~((0OkeTc;3c+%2hJ+d+20;b*uwFms>ae@7e8IE7-d71#FoCZTWBF
zJ5z$zj(tTmpt+6kp1GnlN*jAJEv1C?fGz(x>%pVQBbVo0uaFO{=4IOFD&F(|ggrt9
zx1|faK>EAeShtVeuxuDv2+WKxojS*D>oY+=26ff;rN3*|{I>ZA&+Xima<OxE+`%}$
zXB6Aat^N=2Gw73S9T{LAj!xI~icG<2>OU%6cF@1eZ%D<LvktZV9QN<rfV@>dadtj&
z8lM=m{Il3!6vC)~nYYa*HeBH~p<i)Ue0xH7|1_Y{v$Y4J$XflTXG@d`P5u>a{&Irz
z(WEnQR%<DHnP{4MKJ(fuu-Qs~K#!6QNjik@oQe*yo_%$vX7KS(x4Vm@b@No)z)sFV
zKedNEvirfWqnw4C$Q(H~lJ?@eSd)(-BX$~X$QG!!=xOz@ZBYLocXHOg)qP><+N*}1
z^?LCQQ29HtIrehqJmn31CgmJGHS@5uIMvp@J2UE>!W|*lC&IGZwtR*$zZc!f@}$~6
zusgHf>1Ex9eSkXK$#rNG^HBOju#leedefX^p5`6^#Q`^ElkX91h>R_qDRI@tz85ar
zbXsYBdMtj{)|ZveO8-*(9&(+Q-fRr6l?M&jbJG`QZ`}IMV<UEc`HOAu<5lh561I00
z?VYG=FSxPx9>wk|xW~X1PK8n1bcbSkRoHfDD{8y;qzL}>blC3AVY|<x-O$sPf^(Jj
zN=5y>@c=mZ5IFF_!SmqY?g|bzof)=wNc81*+BsFpQ2+JiD-r6y>(GCz*XnZUzXj>P
z&|RqiN_S4bCe&U3hjdpD{kIAIcMbD_(&|*(0(WJT(~r!Af1gu*b^7me^xwDkrn%R`
z^xqNFe_Q70za39^qeml?r2ldb)M*!d4%^}_TGQcd(6&$qZYqA@uS^H-KhtUNz9tCg
z@O()aV#G(^dRM%@dwGw-S-hkFtz1_6=*5{&Ne6b3S^EPWxLI;&;&gNt`28@t%5&0z
z&&KCVI`G+<ou&hyo$g^?39P2uprhgA(`vfY7k%d5vm-;#AcGe*ZP&V+*1w_8j=*Q&
z1Z!kdfxgN*`1bVu`0#||M*7S~dgKgxq;ym#%lTp0V_C21J_S9po$=sud_<a-FD;Zj
z#(j-x);}88R5t!-tbL52N3yrC^idD}Kj*jTU(3q$M)))C(0-jI9*kKUr)Y1ex3c$r
zcoy3XcA=iDm<P9C5$MFrna4cYO`VLZGmh@BqwF${eC%V4;f8C|KlcdNhnqO3%V0nU
z&H4XFaln;zbDEcsE~j<z6_zj5Q~y<ICKmX&NX|MQ@6<Dk55fzc>XRJ|J=N8`jb}?n
zHg4oAIs^CC$u5E~kM;3k(^ol*nYE_Q7<%4i!5Z6-UV|=oIqRk`VU36Ll<)aG{f8cL
zLu@O1-p&=TcHFy&vy!#GhJLh@@UxeudLMdiYQ=i=#{uZ(8#hzd`c%jFUxmKI_cz~|
z>fQIy)@1xs=duQ4Yi%puid}p5b*bJvuVyXo^{L)x-$vdufCqhZ%^Cb-?D{wKr2NNt
zUZ3jt9)0%2`c&_yK1VsJ0FF<xzFWK^)%&?uqFZf9t!O$69jZ5V&KC6X8<qke_|_S)
zyY{C#es+JV_cLGHnsk>2d2cxd9Z&7PnsOfprnM>ei@?11Vb*wd(?-5IzrJJaufYRt
zcy=V^^3T2Q%{l`N`_6v;e@16j(`VGNWBZ0H)^zdyz=kWD+@UYGpEdMlY_M&YzlHG;
zdl~!?XI-!D4ILN7@K0=eeMkCgt+{v|*x_8x9zTD>Li|fuXH}YIrFiF-+p*=dP8aGi
z9aVZvN6LK&J?463&*22~PV;}S%sUsj+y&Rkyt6CwVaDfYJa=f}nhwEb@=bMcAG6PT
zT}T_yPnk9r`2SNhCcocEXNz<_^8>#%y-j)^>APRjYPuS>vx;t~b-N&)>2*cffR%QE
zWQyajM+XrNaW?VdE%=e%y{!pb@u=>2>7Th4TkE^FGZ*BH*Q;($^+2m_9y;9`*`^0B
z%yKrw4Cfma;)y1FO|eI5kA8wROYqKGEPfpqHL-W)aoYz<8<=~k&S$sroa)vZIJQ&t
z$tRnzX(gD?x{OZ=^q)?2Nb8fJkCt_y{|uo2n4B0|h&+?L18@E^=|AyA7xk-r?(gi{
zaE0$~cxH_YPP?k~pE6GU-2t9cUtZfQJZtSNwWtLhL;8*1$y~(t`=q|C^|C~4!?S6|
z7%#Em*)`0&wsWsDdj_0fFHm#o+BYJvnO9{m!e0~m>Uzge%laniNU63z?igxW-J1Cy
z&SG0jU2?<g(pSfKZ+WwmOmCO|!W!Dftk!0(MxTylhHY&omichBewD+<`}(su_x8=H
z?u!@U18}uyF%@6E2zq@qwFI77^3bbN?#@@ClV5N8v*yE1abyoZQH!owo^E!`rXYGi
zPOc5?yv%htOV?}&-D}>0&1d(<e{+_mmW(ci7GmwtOJ;wz3%Y?Wp1^P9E%d+6`DN{@
zhxxVf&AWDk|JA~IW1fhMC-}dUar7{B!1~?>TgQ1FV=sK3y)1J+u$FCl{Y}_nu-m{F
z&#X$w76Xl~OnosC3)axwbB3N-&e=)m_`w?5dd9NjuAyyt6L`KL#4~sEmht@30MF^7
z*1%p^3hl*MCwxuCwl2K)BO}0hd=0pMLx=wv2YP$U_m?``UWeY;ss2o_kMGXxa$?{t
zSf{&zak%YW525dVKl3Hl=^oE^WnN1EnjL)2DFIJ|zqX~zS;IO->vT%XnVGUJ$I`#j
zx?1+K^qpDc+i1ey!2DyDyL7H8?aut2>WQnKuFOSQ>RI|wW}Nk?Z|R--ekUura!T1w
zYdDg<pLz~c&yvxXL#Mr&TNt~^%h?h^onH;>97iuyo#%uwvCd^MVLvmNt_@-Og=Ep!
zzsuSRHudj6O8*{K-?H|n^-<a1Ix=6=8lC!4Yjj$B8>P<v4s_9&?kJLOBE5ulx?4mC
z{vT0h+v~q?bk*_DqtG+uj#;_sf2vxiGdyLJ`~!xZ<NuCq+=)}v#`Hhazh#^6yGCRi
z!ald2bvR&YKa1~h9S+&Q=v~Zd_rsskg`Uzn9JbW<?sER}IvlWb51ec~=uQLao#k~n
zY)zs=TZc<(o>-yd4&9G|Z|cbFGCyP;?r%+YcNqWq&RTdYmd>zWJy?gk+2mnUrTyk3
zw*>rZ{lNJ8sawErcZT)>$N8Blt+PEv`<WZxMZNRU)=Q4_??UQ>9@0N&GF;kzYMS*`
z^yY_51}zI^&^YT%wuWvp=oI9|+u?~bQay>w0~zE2&+C!LMaJu|(`S3=vrnu=9-Qjm
zp!Frnh0n_6{&iUH`%kjmC6v45p>rAI&&8L3JF6)7Nn2~XtO@x99BXX6Nk~R9-gJwv
z*4!M(CS;n?$cUpeC2QB(kTVN?#`tx*Uj+N+<*Qi-qAizSBwxjomIv2ugJ$8Q&xL&S
zw;`WgAM(*FXIWFzxOxH^-f_z*{$--$cGi)jwS4ZgZ0jF^uFsM!0~rQ<7k@vZ^~~Pc
zMe6rJo@iaqTkHRXbe}cdqN*J1!?xy^27mi|{SnpUHT>`YNHih3Grnd#*?HLPv~SmX
zO0`^BqWVTnuE?LW?Y$3y^KSnfE4xbmRHbXxS{!mKA=<q+lpTA&g&m{`zX*JURxh$X
zz{am}&HoU%UGmVk7}LI=a(_(!Kg}2d{1;&NDd5xdRq?vk7X7nA9MraxwZ-}Vn+?p`
zxi93eu~8eFQsB5;=T}8@hpo=V>gUVV#twgPeH-P=5z5#jqMc(gXp^y||CEq6J^1V$
z*wEmacfN`;&JfS&PQCiN4A)1u%@6nQ14je7oBn!(b+P|;oO1X_|J|Ja&^BcKuK_cD
zx{SktUV-cZ?~ebw)iB))|KEJrf34zd{VORR^l4Lyc|W$D(5~}QTMw3PNM}8#7JYzw
zVi@z#9c`TP#Xq^w26NR2wimO_q|7Gsf!nYd1$TUXc~z(M0?A=?vKtqc;y0ofV4K3%
z%y)WQX12H5zBp$=z$YDh%qA0+y=>KX`rv1y*e`(#-F1fXYx=*lp2C>Wvup(Z>q;NM
zjuHB+E%TI~yR&-wyZmu@dlFycBsPmI{>JEn>4)XBFoNE<rfK7d-h*|P{+Vo6zI(b$
zfp(6tPpfNLQfsycThXhws|`zY+-<D!L^>~iAHf>bVeqJNZp!eP;+%Z>5ivi=g8Lhp
zqjZ43UHID&-rb2k{Q2_U??O0lUow*Q??cC)l)nEKe39G$7s9*7&p)6Y!?Z)XY&O{M
z!x`vJ8ms2Oofq7ZKKO3Rie&@1v5jj#%A%#aef-%1nCU;@jrxavL4NtWsdLVmqycRG
zlo#}6a2_&p`<KkKp|MR<j(o72)IX`;Yi|nta{mkUJlVwF7;O7NzsiS0{bD|~1-B{n
zKGG(M!(Js{Q}d0yiS`c4N1T33I?sCq?&RCyd8hm(_w((D#eVAMIaiQ9+|B7R_IK&M
zfbG|>ymQCI4$kb|p}k1*gH)PS$4{G?TRmTNRAzwt3Vjflr5^HFx#%NSu1C4K%6n91
zsv}F=6dIJNzM>xb>v?SAJ;kRMEKC<DgJ%SfcNy=E@=lZ2BX0qC2x@nJlC}&VYu>2#
z@m$V4N_()p^}mmt-qWS_iB9su10kIV;dNLeV7{h#u(c)p=FX1_ZrGnzoIKX-F{S}C
z<w0*b$8p|rlzAbxn*rNjCt2{DZ>#Qa=g#%~0Bt4YUk&bG9k!F_3ER1)wq4k`&DQBp
zpy1xE{+>z{DKpM~;o^smH8-(88Jk-|?TdHUwomPD*dPCqz8t50KJClVJ_7ek?#K_m
zup>WxYzK7KEWBHv@|?G=!}KY^`c&`g!x{QibYJydq|72^i$6qTq6M|H|0A5stM?>#
zM*dUqE?U?EO~l_5;6UG!pV%#|pOxO?PJ%uqN8HyI-T1#I+@+3_js0uh%`aZCu>5}2
zf`#6r3l`>wk2TAFad7fj^P>dvC6rb)rgq@Ro^afv%f5}Q_lbLNwEfVZ`06hC_IsbW
zXT<&5Pu<wcpStHce1CfNi1W$I+~U#&3yXW37Z%^u^q1J?kmXa%6UGt<FOv^~L1#yZ
zXXD?w%=N54=nJ2|7y?hN@C>jNCriy{_tzcii?Rvzi{Zduun_wqdz+zs{^j{D`qVch
z_@BUcrQh-B57sq}zw(2WMNk<w?oPp5<Wbuz`St|ml&E8xc!JeQ8lyi4__CpFdLH^|
zf_{EQ93j608Tc}#n@TL3rEP19?%p>XYd%B}UCUSEfzyI_gP(rre*=4;LcGMz%)1YM
zBlvGJVTSgwH!8zEl;V%nXY9M>sXePj^`YgR0H+$;#uCnZ^7JwCfHb0yJozO91Nk$L
zES#hbN!pNAyJ!P_p}JTXO6UomtWLda>=52muIe`$>B+mtE&m6Uznt<9Q$8VoA3O$c
z9eQlRLg578lSFzGbD8EkynO_`5e#pw;0<}Bck8RGz}rV^@pd9wc~oW5mW<lf4*bL5
zwH>_f4Drg-a5h+>5r0cCF4fQhbuYEL8{l1KKqq<1H@p`l_fLTTKJYUGexUh??&sj=
zFk`lOfwBd64KJv^67kfHT`!>XNxli9Tc1Hr|EwPcpVF-h`%!oxZ#7>Oud3=-e{TDa
z+t){EOFM0up)G{`G<`jUJRJ|@Y2hb9pWApnj=Vuv$-%!irj1b7^s(jw^q_tgyq(!_
zY*$*RD(%JquZELB^;aEEh%=l}UVj05sKy!OiL+tU-8W4768|SFI4X`GYep0&9^_xc
zF=jLE8lzq9w2L6wlpm*EeRb{fz<(cghVAk%qD?~$+7zaX+T^dPYR{zLs%sB%)}C>6
ztL;G>1Zyk0gU*be(}#V>nx$h3x4vZDP=JRbFq@nJ50+<|x(FuU$RivyZ2#S~e=Y4F
zrTv8bm9+mR+JD+H%FFdm{1W)4882_*Ng2f}LwHM+Pk)MTea=A^Z$$mO0N8XVd2{%b
z9I&&Hk~%-Ss;}QAxs`SNI$jd|IxE!hQdN)Y$b4ZoQA2B#DPOoUt=*V)3XfIMqUtPE
z{oh5M;<s_&AFt~R;v^6DP0lt?5cUny?ndq1-k`mghV3mlUDjU41OL52x~U{|56!3Z
z;Ey)wTRaerzY|HuFz~B&f&5J+lLH!)CGYo50_SPrztc+A2UEmpyqMtWpXE3Y4j!}n
zMfUOZUmn!SFq~k%m8i}u`GOAKrLqMF<HB+4t*K{QP!DUb39BbnsV6@KjD$yXVLO*o
zuHrn#@2s<1?|F~=bF3ZQ8+{t%kQ2fYrnB@(=tSe8;=o0aFL<i#GS2vaFn4^M)xdr<
zfPEkv!Y;m<2BtphAsCN<f1~dz8dVwoy`(K2haR!xK1ez{{|MPz=96j4J3{#cE1z=3
zgH~n-WuCQQVPTb<co6xfd9-*}ahzR_?cv=`xmC1}@4c%iljqbgOU(zTh=V`f&8S%_
z{{ZC^RDS%u*pEfmn~B?8N7uxOu2s$<>XZylCpjO@0pDFg`O<6i!=xdYesI%VdW_mu
zgWHLqE#m9FA<V@qLs_(O)Ri8rdaL8a^EI#(oCIt337z}lzm@dB5Xq7)>=RfBy`rCV
z^(c+-aat`u_-j=Mx}n8~^feaHm&r)lo<EPa5sur}$m(L)Pkw^;x_b1lKa?eY`#k@X
zk*vvD8*^d*Mg7S5Y5mD~6FkRw3cg2xk0AJj--fb!7+IY~Ry)Dm*8O}h#?w(Zem~)Y
zQ7*F{b=|wyy6)#6cH@`lU3V$pKkh}(mz-@dS1wUrSXQL7Mdx@$GPW67(R!o4C3A8-
z%jJ=`tS?VfmIrJF;t17xj+J@miS?YQ&U9Fx_+9ly@uJm8wr7x~v2TsKg*%!T9=b#F
zK5l3Ir;l=Wi+$^^KtJ&c=IWZK7r*+IME;x5p~4osue=L?@<j3Hp^nJY?d=W5PVgV;
zSmm~Y_oCVx*)9fY?|g0Dc=BzP-W|26jO)ijT=TTCyb(NtC7P@B0ZX->S*qyZhWpNw
zfQPzFF6<8AG29au!KV9-%KhL&vn6P@3NFc?vQ9k+{s^LFe+)iR+G*kl7UzX=L&Omj
zH!q%tX<HS|M|6rGSJ?l^$UA_OAo%C&^E@&rcI|O^p&p0Bv(53#NiUf?sP@#!RN_ot
zekP<Jo|0SDIEi4jKKK|o`%~tlCB~GU=!7bFS~#gImpChzbdOGj<0*3};ZWb@F_3Q?
z5315}X0WBxxFTF!IDwp>isBfHuMFnWrgxCf#u%QF?DmsEznH8dJ}PHb5*Z-fg}4VM
z;)%kSkO7QYIi89uP!If<SgLq<t>7@$6Mu+!&2bA8;!Umlvkt>J7o}rpuyn;-sOt^W
z_Mr+*Sbbqzx=54xeXWh0SeEtw2(c)6SIr|O=!kFG1j}Vq|F7@=N%UZBI_SXoi_G-q
zrX`beT{*!w2_C?S+FU;C;&1Lv>?<8>evlv?UwC-1L7F{b8u?17A0FTvKc2*1o`(o?
z=y#a%2nW@VdWQ~~uh_f#M`aYIDI+{f%lejd*0($hL#1XLm-Qav()x2WD6hUhAEdvc
z{;_@}pZZbp4f}60uzNXE%sWVHHqZ7D*7k6IHq87CUBLcN0{=`rp|&<0lP2k>q~t7P
z2>DER7!LC2J)kw{insvB&=B#5pv&t2(xITWt|;BUB<X<ffn<>G0ooMkT{DKuJz>1c
z5Bjkh4*{NodUy|UZ8)i;=UV&)d?*>OyjG|3s?WqL*tNt%4e4<jJb2)NkRJ^25a|v^
z1MRe95PkuV;*;`RECUb!w(&%L^Ulw7mR(r?zDf9j{;tr|Ja{Bcy<DizCwcaw@Hhw_
z3*eDZZO^atGq|(*1AdM8M>HSxv*N_pMo(c{(bHUB2gY^uHSLysh{`JWyKJ14rT?P0
zhW$PSygA?{sNeI`@Yi4<V}(z>tGqqoyWrfb_vr?-aF}_I{tZXG62NqbxSF=<yN*}t
z^BMlfXxnh5Z4cCyqkqOnrQ^^CcTF{HcXdBaLhqElCmG<9wLr54>|;#!XM!<`F^jm8
z&8cKBk!~vckKRw?opbdX*JFHD(Nn#Jmt|ieJNG}`IO2SN)Rn&I{nN*7E@baVcn6k)
z=v4m0)J^$}TZRYG4Z4ZFFFP7{_7sBmeTCq^w<?@dk>B2VK3WQ3J;+n<r)>e&KY(Y3
zE9Kg}obUQF%dq`PmCUHuOH0s?6O42D&onK}{e<us;bTn;_wvmDoNz%?W0^Ba-ee$q
zb6;v&D89`D$3C@Pc<0^l4m}A6qJP6XPrXNY-+Kr35%S+8oHb8febiN@vvQ^{=P<iH
z@M@3e@}6{ig7*G`^C;aOt#h(Q(&Odg^cU+CfADeqlcpTqm*=hbN8&Ht=q>{W)*={_
zFUxupAKnEIWn=H#IRE^oo)%so3uxh=R~jvN`SAOzw^wN6pI=d-jrZ|B8RBO&z>m>H
zu0j*JhlBUM4~I1Icoj|Po&5E9T$F_-*cTyuBMZv(Rb5v8Pn#ARegw~{$DxO+K9&6+
z9j0@FavSl{6!G9Nq5pah&c+P&EoiDd-x#Ft3ZYD;%=~bmCrwOJu52sN2XxUT+R@mw
z6g^LM7qI!rPN(^;)x%To>=ijFUe%n^^yc9}ruBzwLz+Jru1d(sp9J%O|5S6uVepj|
z{+#DE?$4(;20G!G=~~reW_^0}o~9i0ofFE@VfqIB%=lORg1oYR0p|fP(=Vin`lXr<
zC4VCuOy;JFd{UY@x^*>;QJ&T3NAe<|_nNYYtI9@BH!O1qoaK<y9(W_zSQz!c;HND$
z{ZE|fLKlSdF`lA5qe1Eujkurcb>%bRT}jy!l)Z|w35>~2`6Jl8H_PTd#+}C4>iRTh
z&NNLNC^b)DH!9QK@#=;Tqx#bLxeCWNw;|qOndX}i(QEMt;|KhpbOq|$vnqHun-Os~
z593+Z{R{E(c!MvC?wJVcz~09?pS@3=2fSYR4(tcR_k9!0-}{a=hkoIfHiyovID9eT
zzZr|$7s3$f*_s>Ta}($-z_N!tg7-njHt7WQ|M!OfO;;tI*}3$TUZiKJL*%!F--+;f
zG<=5hlKk4>TVr6g+|wGn`(5lbJY!d%V18Z_UNxs`r|wd-<fV8g|J4J`#jzI(o?Or#
z*63`0p4QmSJYDJW9|&N!Z|Plib6@fYc&eNG5^r-~$~fNKxA3vh&coB_V+i^n1on`e
zW46;0Fpd*XP<%i3(1!CSqiN`Q0$$l1$a(s-HUCIy$HW2hYVImJ9%fBrbA|s-(O9D~
z<`Em)o$@-$|8<-Kw8Yx2t-tS^q|XUy@Km6j3x9<zkSFrQ(cIO~Iy@<xa-<ua$Zn!C
z>|VBice*+p?7K<s+?vJy`>zh(XneDd!u~B=SNGqHEZH2an@mB|nl}adQ>l6C0OQAm
z+ok!W*;yuNOPE$PEgh>`*VR9*xA+Chd<4C0bzrYGT9~fzr~l#k>I4VW@f)dcsM6p5
zWtI92USL<-=CpOHs;yI%wmw<{FSd>_W9^@}jpG$s^7o&p&R{K|+}0OUUmx`mM7w4S
z9EJvu5Jym)^lJ6Pvd1fSbL+Eu`%ND*dj|R@K+8>9qn#L{Eb>QVep+-qPM>;FS@6)e
zLtEP<bxzJRW?Wq*w~Lg)x7N?{dIIm#Y=uUqhLEq&kI_q(wEQ<cJ&fCzB(4NpgVaY*
z8wHbiBGS16yI<vBe-#bR8C&bds))B)&)AWJJ{T8k+kYPL6he46!<YXf=;LTCFY`O;
zB)i4$;tBu9C$LGXJ*2aB#X{igwXYQLy~g{(0ceGITl>^H&SK`C{O24{E5D2*$}k-9
z6i$j)BZqmnc@)oyWRTu)Pn|XP!1IDU_;NM-T7T64abO}Cp83CYZKX}pt^L-Z{nnqu
zeEYPMd4r83(`y5p6mlldKlP>dU<;lX4R0Ui5Co6fZ!#&1zZdp#tv{*F2LHMc{v)I(
zMDQ<*Xbl(yzjQq5Vhv^f$@(tjz$q{-^#a_$KaP)Wz+^OK&&wA>b>qYs<&=PHkURu~
zxvxS;R_+At8p0<bDV+k}jPW|(jA`-`qP)U~=IjmIcL1KZJ<ss{7~>jc<@?anjx_Mi
z0Ehiy`~2rlqHW`KZEJ7PHp+~6#9vRl`i|qHQQa=`Eem<tUqwFZ5<ZH+E<2ZeRqDrk
z(SUGK*6Hi#^=|+d_n@<`1{Z|<nb8<OX7=fcr-j2@Q|=mjc1?VNej2Wm4O+i+s%YS`
z6ZlFTg7(g=!;@%<aw5D~pWj9~*UY0U0FUVkJf$mC%ZwAPffUGNI>HrII>PnHmVd6(
z5uPLN{ool`<y$fJbf6<>K01ZWpL!a;F1lT1eiR*tX{94*4qBrl@XusCc1-1;m<r|n
z5VT7$+64#dFXi>e9cSuk=26$Yuw&{Aj6a{2UavE9j^aZe_(m4#uh_GJys4I1{uT4V
zjXY&6`VYh02h4;yFkkp<!VG;za?1aF1?IA@0*<At)Zjc{h4YyT&V|#mt}-94H&Y*B
z4&49k*M$23<q%Yk|I-t}4bJmbIRABFK99Nxb6{o+{<Y}i5y~ML%o-<#;pHodBPdS3
zN#emsXEGYZ52)+|auaE9s?&9dvoQ{uF8hG2rcc6e`Sj>rb58Hm)PtOguY1^4Tr?le
zpGF!&1jB>mF&`2ykO^hq2oIPgYm$+y$vOrja#`g~O$EM7W!fHLP64lPL|14*AHm0?
zt38YEzqUd%$KzA;{|NcH5pDSq4u1*!gs6Wa{Fw}EmtK$!aQz|D5u$VvpEn$%rjg5$
zjRHOBxbvP;fMd1)Abo0Mz$8zC>Uxy8Ir`r(DL;YSKZ@KZ<j;%bK6AU9nA<&~Jk0H`
zq<=*h=QWVmH&w<lYim3lABU(LeYVDqLY(xD0_CL(p*}Z-d|gZ5QMTl(^~EF9TfOGU
zKbv#N4jQJLdZdcaqyJ<4r~GOeD8Hhm;dp8Abvur1{VK=wwh}Uyd7<$2fEU;uY+Sgi
zYFyA5@cp`R0r~0wNdylvocvSdw>i~dfPZ~II#>$)hhOe?JxaXkEhX#>=!bjxK147*
zjy;Aph7AJ`YxqGs=a#E7(uW+%Jx*CatSYNFDht@c^}!RudglpX-CtGyniH3AFt0xW
z%<yBm{YNQtl78$1j|Aft`mu(m(g9D&jv?Oi3*j>xJk>^9x73r6c>>*gk}{9*O;DNA
z4Xbr%<F5n!#|}_Kx5SBVBicJS&AZCl%##qoCtiM(e+_wg9A5L`GeX(F8J?EDI%obg
zRL4{B#|e3#a>PH4cwc&j!8RPi<^V^He-Ga?z%_{uJSaVK2E7kkW!7z;n1;`=Rp#L3
ziE-MCj4iB!E_n{LV{;GR&7LUvJ0AKH@@{L%>qt8YY?NcRL*C^#u*Xvw%+L5X`{E>J
zXM?n6w^V!<8O>932(w388s<|a;s}x<*3X0dS6=;(-Ua7Gv~G72>%_xqXRZIpgT&R^
z${9CisFSkG>#pc{C%4{?oGpN7g-gP<pGUu4S^IhPJC(JcKjxjboYcBtl6DV=^Io1F
z^54c{^4mL4**xGa>>=U0Aad!r>w;Bf+B%S6ySi#kpnm>PZ%>DgkhPr?gX%j1bZIaR
zSM1GG^i!n!ik_Aosq!BpUF2gD*{LJ{67wnL|8Lq}T0eg%(gx`$(jyx3v$dJN%mw@`
zK90r{dk5dvX7bzK5&bU^HyPpt+KSe9&5vq0pm+2AB#+sMouF@x&iOBYC(AR<yKp+l
zlOX$dd2Z(bQ^ecnA#<kqCgl6z?Qk6;f1m`Phx)`2WenBHJL0VDH)6Y*=08t^fv2@m
zPt`llKZ40W(wVInS=qla(#>*??PcgA?J#Nk@DZ21#D7UVY_^J3$a?)#+tgmghu_s{
zMMt7x!`~6c0@e~G7dD-C3_l$5AbSn()M4dJ2lbWlb%c12@)fW5LioO!_ayJYEg7l*
zbM&M>@Hhh=3FSQ;$ZnI#lavP>HRA<wYM<mT>ph9|0OjgE8`8uu?`kV?249$N8Fxon
zoZu|+Z;*5Z!|!+q-!S?C`lS7z=073&zqDAv`<yl$p$#u~j}6E@neoTVg?5>tI=jpy
za1tUoh39$gGAC<y^1x|dm0e~egwg7nr$5GzV`CYt!ZqbC>k4pbYtBQ+Qrh;S_rc6F
z_8U%zsdu;zUgC^?ruipY(6itsHu>ydDDiKSZ-VgIUvwQ`da=@ELz)t8>3ay;R-E2F
zTTioh<AYKyeMvW-Lo?MfZV>q~jeYE7=zfs;LKut}^&P@t@aQ`kz-7Fr??U*kr@p=L
zTh9`(4iiT(8k(-8SG!V6p6F5=wcggS9fQz*f$=v94=b!X6!>EN_@c`A`{P%dUU6_Z
z@Ws)5N%Cg-MBMzmJ^pKNsKJsAV3Hj-N1ck>n}Z&CdgvT^o>6}3V|p+9;_%P(8lLs}
zZLAd>$k(zwuODlTk7+|YvIu%Mn<afBIUMPcO<Bfw!P8f#M_$Fc+fPDY?C^h$&F-?3
z;h{j!)Sjc%?|J4IrMjhiDo*RRJ@Ti+FFc6HH<<IkH80ZKPH|@cvOM5Uy40#*-c`2S
zL}{cS@@_N}rjt&lIyPw!W{H1;&;r5eq7VFMLcaAI$VmQ6_Gqjxua^vwpAhBO|AsVF
zCznXmB;4o5fdTy2<F#g;=&=*ywLm%b{<&${5=#x*xUM4S{gw2o<!!h1@|tz%KdG!e
znU8&49r>@`9+W=~4hRtr&>w=en_<S9)!>nGZ0ypr1Uy4kI3rDzUT~zY@DeNNAM0!W
zHC)ds(C_@)SD<~v%!T)3v+k>mZw>XWo8aLs@bCn*Pskq#bj<uCtW}){Oq1{cWB42%
zc%;Gu`tLLUujwoPm)ErPza{LeA+@niE)!?6mvr*M6dk5%L%r^(^=HM~dexoS2^NLx
zRZX;)yte)$9Pn;9;2H6c@zfye;e={>u)ZRl=(G4I@CEP27d&lUOW*3BNuJ}tPO$!b
zB*-Isz4r6j|33Z`qW|S}EtN404*ryMyw}4N#qAj+KmUy;rg;+5M}do{cv<_-gqzGd
zx9b7Yn$2SxeflQ@wr5LsoOzt1Vrymeqx&}rSLH=Gm2a57f9rTU0_+6g;lWa^EkHI>
z;o9)FF2vhr(i0-QmDke_1bB;Vd=2Th-q!X=NWV87+c9ya@<YFm)X}d8PH(EvuOG`+
zXgB;9$!}llB#(u%J<3-IW#OB$f&MlQ{Nr^rO`MIb)LqlxlcbH}=u4C7PXUj`)yZ_?
zjL*Y=4P|<iMlzlE8ks&>CDVub*GJt1!}Cp5GTq4rHq;~hCq)0%Pg*C5;N26#ZuB`w
zT7uDKSkKmfVC=B*B%XMHwAw$i^@GHb&TIzL@ZWUx+#g=$pZRSwjv3!)&|z!RgfcHm
z7y0p%W{zE<E}!wr47erle0GJhjOnDEq_aJhLp%xTH9_9MUkE*QNOe~EoRhxZ=R9hw
z>IOdc#VXGeUHg*SQ(MU&@G<36kNDH%I^~t&jK+2T%RgJ|^(tFF_U3b@wBh((_75XY
z{$bW${mWL$H6JnlM{TL`0V94-n6IIa82{xXR_5i65l-uTtIFlq`Bo8czEy+A_pS2p
zY0w8<5st!kP0*&uXJ#nCO*PIdIA-sN)f?oC+Fjmb67~iCGAbV_^EU&&nsFXlmJLNT
zJ-}I7W;@}%Y?He(w8<fJoNJJ^!|>PvXonykDzEKqCXV@V&0Ll^lMj?vUfU^zduow0
zrbpcr$Vyv}=DoaDqj@U%ijRbA)7r<Q|H(*y$)0#0t6)73xCnx^p=_<w&CJ#T9hS%W
zBx7_Io$t?qr>{=N>Ywz%AD>u9Q{EaG32af^p76bx4f-J+&D91;LlErVZtA%sz=_GD
z;c%SHh4P4R#zfn%t+7&bWc9arpr*h30$wyZbdmJcs`0ch7*8X3rr^mM{hPcdt9k0*
z1JqHb)9|0-s&$W|d>Z*DnXP})!8gr>`u8;LBSduMWoY97Z7h*~h<}9WpY&>-;S}Ml
ztS9zWV2b8O)jCXBA3vG7&|q!9_p9HRQs?+Q{eFMg@6&2W9qkjBA0(c<)%|WVun(SA
zUx)vqxV?(w-yvk0`p3pi_(XB$*T8>28Q>t7C7%2bB!fKroS;10lQK-b<dMEv_OS-<
z&}!iOPCU&TmCe2o`o2r<@xQ!R(DqDRi7qu*+ZSbgI_T1ot<dJkd>7EI(aA~EnWGNL
z3L6tCyMF&!q~lkQElM+Iyd!Sumo%r<{>=a{W=E&&@;FjwN4I(>gE6E492z^y;{^H4
zznJ*yxZjk2@dJz@X48-Mp;BKUm+Qt0;%&U3UykdG3!IJogv)dM>VD{JU~80aI8>ou
zJI^2&&`yo7%#9%}57KXgb+k;J$#Kdty=amrp?t2!Zpu@f=jvRIQCoBI&;{tPe5sOl
zndbeP$CK91$*?@ot)5AAeh;~zckuzwycf{4>1bZShs$OH`LB7i`Z+&MdV=JH<i;F3
z)Op}!in-r9=#!8?60R?7R-0=1-DJ#9P67|im8@Mn(*@eDxl@+5>e&FM^tH&@R`yj7
z0qam5ZizG8zML{A`A<lHn=<(}{OLJNnsNRStevDO$_@>lrfA0>ws;ABn~jNo<ux&-
zDTMgdyYR{Xsm-jP<bwBuqJ<LUD&s`XA&z&O6Y{iv%m#7g`4sUs?<@s#Z}VZ$oRWCK
zW6uZ=eUw2E%+_C|X*dR7NgqwnN2}-~!W>`HN&1?0M*Lr<VaD}{hV|e7THXAd|K<6)
z{{Qs}<n<)*k}jG{s&C7>bC$J#Xs*VelrzHoFNO1Sbb942<B4~}6VLKo;^p9J5IhOb
zda7^vFZ#B5Iq!x;p4JEY7A}FSdOVaqqdYdhoP{s+f1G*<Mj!ky&&yTDFm1n`wri}<
zhI8l5;oO=3QG0Ff%=d4t4Sf}QDC^nTIv-Sc(r9WDxQ~#Y5Vfg1X9h;K>9}*|YWwpv
zwodx)WY!_9uP9qQXL5+A@lf@*NB{91@lJk{v;@J~aD03O`d$TnPeI>=NCu%t@0hT*
zK;N`;4t*b}(6`AZw~oH~AMvgI{~i8E^Y|PzrTm3RUq*kzmULVksExqUP{xbC)z06B
zjHlijIS$;$6D8>O5cJJFpgc#(HkhLz&+N<zWP5pzG7hW+^+|b-GDO^b^0(0(Wd{D9
z3hFP8g=1L=o4>{33{Cot@A8~wEKJK<sq`3~Jy1@QjQSya;&}_Ol=ma`0W-mPpd^}a
za9&RR9A+rA4{=spZd|+qoI?%hi*h6RY4n4?kI}~@bxzieQ^bkqR8Ax>()%5ovlqrg
z`_~rm)z0~%+)GoIGr%Gno%lV{FRRPYT~ykCaiTmCubWOiSm{^cCc?k!usP*$9X*jo
z^i<}}`nf<o{>B@xjo7%84Cj2%<#BNZETX?Mu2zL}E#$BKt>u4iwoB60x5@hA+t3pE
ztL4$7xj^nr<<Nue?CfKeb-iiQ5=1BcGp^%5PX1xy3ZYImEL{MdtdFP0AO1;yQ=de-
zxank;C-`61$rP6j;!GBnfO&{GLXFJ(P2hF!ZyB$5{s-|Y`;G7sjsfZ)(_0mn3~?0w
z^T55<<@sm2m*tbc{R#S@bdvZzz__xGab=8gg%GXjK|ifI<haS6@jAYb==bfvCZ6wc
z5(Ub<0D6(ni4Q|X`a}&qQ(r{$(kJFkr#23PGlFPHWv>!0vw=QfJaFxQu&<cYsNC}f
z^TUi^!@rq+^AjiLtzzK>JOnHa`LA@6eQz==?Dsz8mHcxCk@J1?^!K)~zlXrVP@QZi
z&iaD9W={ZT`$Wrpm+c9}c}d2=$=`rYfpSf*P4gs_=aD{rq&N>Aaj2g<C9C`-__p`p
zzsW(qC$gj={ZuYUdr;ql<Qb<7LXB*yo+nSkHy(V0y~2Fzekb&)`_^-nHT`e>!hEo7
zUH!AXPli5qtHQpYtnjesgO_3IB#piEZ0I+46ZRC+<sB#R3s4=*0m^gvdimKvhgEwc
zJ<;}|!q3JlT_?fM<drQd@+(M(_*UGqXl_m#v+<Qenivf5C_jWbbL(;N=!3@`cq9Nv
z(**e?cdG5D2H*aZfRDM3;gM&$KwoR_lMUz9b?^v}wr<FCSu}U$-F!up&;jpe57hrT
zXP^XgSEXsFPdzffzMk7mxs$c}y7fa2cn?(cDbcI{Kj-S}<@u=oe?G*?Aha`B$CJc~
z=2T83Plb~?^U=-Vfp}Xl#&5#kTeZKDyydp@Zu3!|rdw;y&b!SwdD?ta-@-Zd=BKHf
zARbb?l*i_qKZXAFe~ABt=zn>>sWOIX8{@3T2jC6XYSGP2-{F7M9-D9S{i0zU2L^&*
zknUIQk6i=vx)A0*(i0+>%k#+)=19kEND~dlTIjkn&z`>t%B&x2jV3&3g0dqW+rPYu
z9>Rao{7riV%5%3UUpRNu*}0}`4g>#i9i0%DF9mpr?9Ay2>KzYwz0B8qm-%{<^aR5L
z@TqV8AA+N*dDhEi7Y^5j%4<P=;XDi7)#h0x>Yk=7g32n-vj&N4M9-vG9rLaQMX*T5
z@*e5+=Ceq?vJaisg7p8_nNv}BHO)5cV;fVEXYI%{g53w8KAvYDRp$G?N*|l7`wh;c
z%KS5Q^7E+U<%wv#TK7`Fi7z62zvy{XA98aB{Q2OIVE(R*1(Fl>W0vHYzx5>On!J&`
zNQZN%`u3U4ak4_wMu#0a$KMDYkw4&zQep+?@}yT`V-DjeCz$*2UFMBJ(QZJ`)|W7c
zl|M~9L3G}~YM!$$j?n&ycHj~7uaizTK2Q6<9k$=fuH$RstdGcRI$0m<)6#GFj?Nvk
zKBEniw>lf#Y!#(&ou>r6#4pu4&v4Z`&!pm5=i#X};qp4qxbQ^zec-|g^{64rAgIm4
zMdR^5?CZhM<}idjoR&<Y-Gg=QmRzH}vOF9)x&F8Din7Y`P37o&8ap;HTf6y==p<AB
zzYx$td5kIn-z04#1Z}H3lk+C}aSL=jLE8wloiiI}I^`?Idspre<qz$N<CHUA*LTFJ
z`~vA}*FwJ%+(*PeWJ-A~^47r%lgNL{w>7^4?L*#aomX`#zP=ozjY0h8ebTDDBa}x_
zdzPxaPt#`p+n5-o*-RRO(k$b=7QdM~9|_jS_Du)yYE5hp?++5xPdZ~~FYgajedl<u
zhe<wWL3=sV2H9V;<~&Gxd>Zx*Q9timx7!oGYYl8K?+*^uuJaw@TYjImPK{nu|6ewX
zL*$G0`sx3iwZpnH%^w9^JP_rpTQ}6Y-Jxm93D@rGeRT9)n1;?9ofkVu+h*X!5>G<<
zIl-)V!Bz36sfJl?P#W{03DfP9uSQ)ygL{mArd-ju@|D{V`OxrhkN7uC6SYHW6{mmd
z(+WJnchH{jOwuYC)K7M1>Ne^P-z8@xQ=)Y}ttr&QTHi1KsoO|f?7Yyrb_rjZPXue<
zg-0sBNb3Kx?-B2jzmagghjm}!sldCPH8lxO9spMa@mtNA%h`&JqoE%1A>_{}@+X1(
zA!t1;e}MV@dBNQmCV!Bx$F=3thVmRt{Lgo_uI3$u|6>9F*UOg7?bv#d3l058RL&6X
zA_TJYsP>!gC<0$mYf5{2UD1j1<1^pG9IS`=uFf1_{FuOY7TCsP=X0mXWH1IvhSlH)
zTaCtW?M<*Y_EBG7os1<eUkd7}hQI8WJWd{hVAMD#JCxzz2=N5POYSzr|Et0O!{C1{
z_$SojpS_KoaaQy>XW@}q{4W`UZW1iNf&SP#Pk*FNzCWgb1zaZ@_X%fCTsgZ#Y4V(7
z$r*6W|9E;lgL5I8uov$L`>5+bbswEaA5GCm>*ynb#%P<H(+_33PdW)t<J>F2>*iz4
zc2+lW{i6L}gtRpXJq*^-7I8*f<e4)b6Q{DOY0l2@AEq3FjmIVOPxDO>o!MCXchDdI
z%j2=q43UPQG)o23TY@xm{Y5G^`f7g}jdv=uK0Ty9+9*EK!B572Mq^nzhuoliy_+94
zdSuOc+R^{^s{he>+Upn#C&^1lgY)8KuqRUGMdt=a=Qn768O?p?y=$P4vIxSJ`;Up>
z{QGg@#_RfyIP1G;9kdXXt$A>cxFT(EU(@UAj5~|tS>K-~Lxw5a#~wWs;vh$R{Hpgq
z4evw?(`jB_%yG9zj&VS7q_;SqIG?yvv9}N({ny#3`j+jZ<{ZHiX^xPeptjb?#q0^j
zjRWvRBYuEhYiOUjzS?ZGJ&OHMzA4kxIbDZK;)F}-q7R~{?HlHu@BAQ7g5Z0QIRB}T
zmxhQRsw;!Ih?nN@%p~avWu6)5o1k)yXORE;U&Awfq#-Dc@l1P=MtIz(F}PHVzlQUc
z2C^gC-<qTB8vA9AJ_lDzy=eWGd1W-e9|V@cy7m%h?WLSKvV*t+VGbUKDTiQpQI*I)
z%{M`9G@lag$(C=9+7jJqWjG0S!fH7(C;dbqQ@n>m9z6mN>rS#s>QG(dJPA=<nrmsi
zY&b4H0)18aF-Yd-H=~!}#}KVIm1VC7-VR_>2=S(K1W%~19BF_v;<Sb{FV5PjN9~xd
z!Ws203vuQz587||iqZ~|mSAnJPP?15=rDHQ*<_%bv?ANe_nnPb;fj1qqdKN4I4*(@
zTl<gB(&{4*A*xIGZHU_jG@08hS_<_F;AyxfUpmS0XpsB_!O=g;SaU%YUi`T@H2ymj
zq>1*=uSzl|+(z1A>clp<Y_e)^9&u(bw11(WCi6C>jqVG{{3`f<06zUq`bb*;579n?
z+E*hpr$SwFjJA|&>D~9jxV}ms8IRFPmi7qo1eNK5vxfa<G8a8$3_XM(o-ke*4*PAI
zG8)O%;ef79MhO4We4qMc8`}r0@{5S#3r9kK?}FP^{+|tf(#SK1KPIV{V6v6Es%3<?
zmj2&F+59idR;3vy4?*p<{=YLwBmH9EApC%=Tgn_c^2N2e<z(&t5T%(j53kE-^Vu2N
zOx}5Yc=;!~8-V7bdLsI&ww*j!3fqu9!PvMN*)>K#wbM@olU-GNFikd5=e#^N-as}H
zS0K#6{V?Sa%H!G~-vr^+Y%^=YEC0*5FM<1M(h$nHr|-ST@fBgdWas;xf{j+`hDb+H
zI?-xFnmmbhxy+565l4OL)^Plvq}<86v5dHUiFjz!XkZu`7;ZoV{IAwam1YhN)a5JF
zfao6jiq03RJ`Y9p%ElMnCseI>*!&RspLgx_2>snof6p*~^PNjPp6YYp3hvDr1c&ld
zpSCAw)Y!92=hT$Pu%we%nuk|dyDX4?dH;iUr_J)CqRA(^3YKS2*Ye%Yz!dqG@5bNb
zYlNX#R_%97t2pC-kDH$qZYh6-7o4%fyY@Rr@p@PKcx%y>|I&cdl+}Cm)Y_|b)o9&T
z>t^bEd`qrjF3R2Uj_v@v#4Ch%1kWdvG&e$4wB{JoXj?z?U#&@<koFtN7hsx?#!Yto
z8skfOeDIM8rCJ*I27vLlfM23{Lo^<h?~wu)jYl>2ND&vw3)wMs*N~qK%CYq<%M*-K
z8rL$9{}#ulad1Tt&l=r&z)_-|eZ&)v%gfWyv4_kely!kY@(tGUDsjfEp9$B{OMFj~
zj-c|@S0*bQ%F2dxQeE~SHl~x%H6+LK)M4;brj={5C>zM4>hdRn9s0xuM4blz4sZD>
ze_1S{gTD2r@CJ7GY~B5J4f4b`_1YcN0iMEo>hldzSB|>809W4bI6OE3OjFLvgrD`g
zj*i6MR<t`eBHzSwb-&75?pOKBYS-S|ZybqzwrD<^8e{We`!*(Btz+A_aAbR&OYr+l
zaK3}a!~C0r{qQw$-y&`-@Qq(S<BXPV;^(p_%JLKE{1?aDw5+TA@2{hO;n@*y{tCRl
zr^`Fq%>Dp;P6pNY>Q~;g%y%YvXKrBqqNjZ`_k=#m|Mkwl!fUk07u!Io0=sABKhd?k
z;Ea@Ec>jSgEoWF1oY9qucRQYQVFkwjUHKo_lgG$k!A0)u+ecLwI7{Sssy@Bvc`ChV
zX5%l8bs5et1^>Ty5BPtbQ~X~yCG7dykJIJ}!c>sv+#5&YANp00=9w@}cU_v6C=Gr3
zO3FOFY5x0F>S#rGIG|(Lddck}E@c<~DKMW%Ho6CX8jQ=dX$~*c(`X+wIs=XR&?rIc
za=HhDKHZU@F743xZ#X*0ec8xo;VsX*$`w5FR}g%8?5WrmcAV>Q-^`=`?Z)CDI>IFL
zmYw3MdH7?Ry5Yfy5A)gB4s3us@aLrMRlMspkPYyw?ovUX04s0~(}#jhxS9;#v!cQ9
zJ;{3(8>!NG^PH<v-v_|2^W${BqVbsKRL}}^W9L1cS8yG#rG>Le+^&`4+m)G-_^nB|
zf9O~+C!PfV;7I<i>bDCBnP1K(JTI0l4kB+>(@#+v>d|=XY;3Z-xn;vh&oJ-hDLa>y
z|HI6P`(#pg_k?%Z=K}dw->2i?)u&H$;Fb{esrrnu+5B~6V>S5^*jOnCJNTr*&=vdp
zU%C5A=v4&S$^Jw2(Faz~Z?e8Y+E<`$1lByEv%n8fIL@n$;kTDu640jPV<8yd$~<3{
zXO+`o=U#|563cE*WDc;-68;xmiN4Evts{C3>2VS`l6(_{W8;Zr(ARm&60Jn@QTrYa
z;8gsJFY{Ql<{u|r-ZU_J(1LK4ls*>V40xOEP6J@7nJawoD~aMjD6<Ek*WLIgG)Pm(
z2Wbj<=_|o~vY9R6UODnb^P}Luz6055bbLoZ$M$}Gz%#1D`i5uW`@y*n!u`f)k97s#
z&VaYu$-1Ao40$r9yGz}0Z0O2=5ZNB)sc(zyB+<VzAAPopk22`d4f8VQO^Wx%Y@c%o
zzulAQez)CioJZs0Oqg$q_pvT#^JSJ+ZOc(lln<VgANDm3b>%DRvkCfa6@4{DpXrH>
zEV66m&qLm!|C+A0nddaLc7W#~&+~YK!(x*46X2IFS15$Gj{<WC=?vq{<F~*MRsYPc
zUiEEha*ktt)DiTN$$>(WJ%iBBWY&2g#M|m7<`>P!5{WGIvdRf$)j2_)`ZU6$myKnu
z+?NFXAUM=d7WWT9K70S$s(QbWHF!<07=mX1A9rsbC&yLXd-v?FykpDY6?R}jHruP!
z1%YKtfD_EiWyZ!}19@U4n2Q54GfoyFf<Q|!c*EO_K_CGRR)|BCm}Ev4fq5<ltqBPP
zxXj3Mf_Z@J^%DZ-C7BU|WRe)9oA?F;E6?-&)j8eM)7!Ia69_!_kN$M`d8t#Us!mm%
zI;T%RClr12%i(wSZ@eSeE1QjvGS+zfwYGm`5j~VHtM3&C%Kmp(_O1s~_BXFx22bmO
zt>Wka%=$lPm%A-h?&cxo4yVc;7*g&?s@%aL<yx&2evcZ0U#i^AL&_aal{+w`+>und
zgG0)-!W4dg1W($?$AXuSe;X!O-bTJSF}5Ft%urW*10*Y>FD}Ywhi~KZIWN3$ESL_*
zm!_2$>6MLljG9kp{_~5j*_)Ob^35Mqe)mPMwSQQq%fx!-@&qooEFUj}uv|YKu6^BM
z_%p74B>ca&3jSYP1^@beeSf3A3jSa7_#3W${L{2i+>t$917l?2snjjNW7d7r<&!iz
z@YHKo%x`@1n!L_xNW+j1*a`;QJV2XS<?s;)aBF-L+$!Kkj5%FCiCg{ktKjy7Rq{_+
zCI9WK<Uf0r{J&l$|1r?+*D`2_4NlXp{`w5sQEnOSelVn5ivNvMhLmfic=7fj<-%0C
zXAdb?PnG-YA?3=ca*sg<n#jOqSuzmpo$2+0*xr0#In1P-G+s7DMw`$tNVS^*%jP!K
zRJoVAu@|=R3#IQEOS9N|-NPbj+$F=7#y#xx{bWmP`f}VQ<I<4_xa+yTjk#XQ`)1s=
zma4eXj^It4>rx*c?@P}?nD0cfO`A(CIe*;F2`ISzXtsw79E{dk{=npYHor1I<O_W3
zDj#+hII4q>u0AI1dH3<?x4WJHn&iQee}1hy>n>{J0teT8j!!4rxDwbNrs8!Gk7Wy^
zbnUH*(q;RUF8VdNx1gP3%I3$uf^&U){g^|m4bDCM+c%vwI%dY5Y@UN3I55Xx&%#?L
zbDC4SIR^8{uiuSNoDsK5`2ObiGe^<fzRP_8hSGYZZM`rXPIGXcWBl9d_!rSNgw|#g
zE4}ggA~dJ3wnskM=ZGHaH|HFSkIUkJE3`G>+rNN$$_j1W=6zG6@q=kgesKlfw2&u{
zyJXb*244r-+~#Ot{HCm{m&-?cTCD9S59wzKn%4dNye+;EV<`AI!zB)Gy1(-0P3A8n
zzsWcRPqm%I&&GNIT#DdIp3O(v=&mCDA-$Y;{flH&V<*NJdhYmxK{*|u<BJor8YJey
z1^U9gGLkVH=fD+yA$Zulyhl5vJrbOvJq7VR7J1m5I~izBr2Vy$Ywamed0UU#rnpmT
zE}c~enN%IOHl8kjk~Z9!DHC&_W}Vpf-&Gurf<JUl{vi5i`@F$_Q*fP)Pn{bP_oMFn
z(R-7fA8Y-5u()i2){E$bZP1%b^FnyZKR`?tf&<(Sb3GA#sMwLwn;6bCWy;ln@kY$(
zA-`^UMqBcT<1NcmtPkETOJ6Vkk$3(8ycz3jEW>T&xU@8Wu(mXQfa{1Ki}NkkL&vYQ
zxcNcSy5KH76v^!T!`%Gzr`?y$%xA?L(a*lGpL20I`<@M(p>*|SGjq)FiQl*L1?>5w
zJlmX^^nc|U-dg%;-{+jM9<n?-Nj+kP#Mhtu!%3IV^W%Sr4OrmvbC}<Bez)19*ExG6
zT~yv*bY~@2!LP~qDsZ)UZu{pV&m}!$6Rw)f9jx(;ZW;OFWbS}H^G;pqhBzkhqMs3(
z=N-+rw1R4QYJT_VUjAFFzFfxsj)fq96#S3X<R>KPbibohR8I1={Sj|;;|?8qw6?V8
zKbMCm#7A`Q;+XO79Ui|Pyn8{_pK0#sZ@$hH{c9pi@A(<w!Gz<1=yt4j|9>j&h}*B%
z9%1Omf8ad*{whJg7eT*5-&UFK>ab5h|EFvs@Au!G3*UWlRnNH_uFP3{D^WhOJ5l+O
zugYg~b#tSGbt5>V3wP(%W0QVn_@nXNJ30O{!=LjK{J9*zVhUTzIF@gsIiupjvZ)Q$
zhVY-O(=GqqEj${1`F^+dQOBNqX~_6K)4~5)uy32un`W;+M?ag4Tk!5qqMJBxCi$*?
zF_8|E&ek~(iizsk&XPc8?YT(ZqU5)3e#ngMX)CZbUD;{bYuQ1S)w+@Fx}JZ5=h<Hx
zLa$didX+gxBf{x$!^eJy(fG4JJ2XCzzBTBh{jav^XzcKJYYn3L5#JxaQLcJj%lUka
z`QP7f>t=)f?$>MWaCDFyrtAGQeWst8v0Unp<;=NcYF=h@oibyf#Z~1has`fml2hpc
z`Tfi0cPseP+S|SoycT+8sE@u2zjz-$F_->F#=J*%B>wMLy(Hg(?<LKL=#15;_(p~`
z6pOEBwTt}ee^oZ$+7|>mJA*l3{LiV!)3;kmi{@aB3btuV@64gLoSeL?hYqY!hi?_F
zToanC!S5>dwBClFaM0*;Yr&n%5$!dz|KKqPQu-qMD<c@1#~BX(+d3=9H-RcAnNP#k
zfBJ^f>NvETfL2_NR&{9Q_n?*3&-z%sX7|bZ)XFqcEFhwh_%0f04C`4mvgb-7CNkBh
zQ5N2k8TCo{Ti@3ous-VD;9LKRbtLDX*U_IhGbj2CebUAMRoQF9T*rJx?)&m1ub#-A
z_msa3HvB)2%s0s2eD}Iw!~U=48;>|Se*Qb35QKBD&Nu#m=dJ9kdEyiDjTZvrD_rcS
zPQ#hWKhC~QAl??#!Bx8YX6_rpTyQ||q#x9~@|(OD$>)Avz`WoGzhkkX@HMO8NPdjt
zzk%1}9|jv9|Cjm3TGF5U@*tdeT)y!xo`35dJcIl5c>d_E4)@O!CpZ_re2D86T>rwg
zp6e#A7ju1`>uFq{;(7zu54py<_AIeSoxWY_asRCE8+YrQ-qkm~t8b6>ed8YY?Su5|
z!`Xe?{K;PprbU19&!7BiF!NRD|4Q)Q^lJL>j(p=gz@ZN_Tj|d^^x=<}#>1<C#dj2G
z9&CoDGj-(a_t=M61()Z0T(}#q+-CxC)jRk4-}t_851-;<c42u9Yr8=e*sSZiH4Cln
zhKGIreM9p9QF4w<J))ZvALD2G6+b^E@qD=d9IgKj*RjZP6&dF0mtADdiTx#KkJ);R
zouB;4AUM_&T%Y$%m#4IWxDo65ahWF$FVo#5UF~5#cX+w}dcH6FN5jkB=52Kh_mtsf
zBR?fB`wzp*Mm|7X_I1O{Ms`0gd;ajUw|O5SF8dN!_6RgZhU^^bV?Feek7w-oezZ5i
z+qv{UoDzDe4nITq$z|~o>C3{>_|0D%TdRFV<>yp`V->}%-MV5FM~z}4vWc@-S1opD
z-@hH^TLNp}#q(T@&*q$NUs}%L%)TGnE752=`=FRu6w8bI_XJmVM*E3A;^tRJTFy_J
zWv#>JTcPuz>iF>{gTFdvF?i|jC~g?T`%?$c%00xDE8mANT3|nZI0*M}8t&h@^2xfH
zZ5(uM*mnrvptyXDTN1`v2k(Gryt^7ee@Bm=vrY5c`t&$j>BkkU{TC<baxZjIohJJg
zThM}M#%KN*b&ggv{@80hz`LXFKTbtg*8C#zFm!&uy?0y;GzlZ7;gb_>=Y8A7T>iF}
zrysEp!-urPQJRMxpW9Q0=HMC8MsX&+*MolDm>)0er$xM<e>?LF`WLmcOvc&{$D<YE
z1PMBzN2No?jE0@vrmF-al9N-AA^op<jqb%@a+dYp@+5H@=*SvMHQe#G>tj0H?dlKY
z&t~Kk&yMR~kdZ&(@`=M$!;gM{8GJi?1{}qgBcZ49U4#9P(_6$n74!ST+bp(c&zs*y
zpA+Nn7Ke9|eyzHP`#|cC_<l2oQ@`dfcKjKj;kE<~k%#hS0c%qiL%+A*Xte)-J&Y)Q
zHkH2Bm%kvDj@)b(oR9us08S>2E=<TxM7N>+^S0tQ9bS=KtxgwT@9l&2A~~JCV~|hF
z<n$L@y%pv3(VkXwZj9LY3=+2RsLLOebC1{OBKS@}$VS9#F+I1x`7k_G`T_1H6V3j3
z*zw{wO-4G|&eLxu&M0}oA=B5Yd$VHYR?o%srE}2P_U-Et5C0%{;TWws?)YzReKyn2
z_&9dyGVIb`>=IYw4A!4ymzu=v(U+Xr$=))q<4g7r`+@l#`_1${XEeX#J4?#A81um`
zocU8g-@X-E`Z7lfZXROq&+=<QcX}9q)n6Oxa;AmkV)lRMCiyPL>FOHgxU^n$4A|<Q
z_XC|RdX}TV*{?Hcld@`0_CWtmy6PQe)0I~}ubzLBzK>zP)VLg&w6pzPF74nA?)^zE
zc*OI;68&z|hYNt$UhYfDPwH~M!u)R5I5YC)A04^De-}5IRfc_q;A!7nXVjPfc%(pI
zx2UiEc(RS_-*Np#CW3<{;v^l1qhv&D0Fhs!JvKYmo}AP<DDx*6r!}?5x<w&^>tg5z
z^Q{i1JwI=EY}*ZH6WTzpSSSC`l|2HT;<OjKw8P1?LoQ8cqnT{H;L6<mW`~FTnZ^`w
zbrpF&4sPlAV9mt`Hw5gH=2@}b=vi^w=-J}7Gw-o7iutOaiV@BFK3j~g%lo2lo4gqB
z;1Xw_e4Q@k^qs9@ciLNN>kb|1d;IRXOB`K%dQ@(@h@AdS(f(^AdT9)b#`es;dxjh9
zl1c3Y*tz}W<Ob#&`i?5fBSwlZf!yDbo77$3=SkLMJTG*3>O3jQ#4&7czpnaoLiR`V
z7w7+-<@>eEjZyvkU2y>Ek4#-)aT9bw6c2#jc1Bo}allyCSkRadA8Z||#F<~bYYt-b
z{x50V4OxqBLjzsnbAh|Az2Gv{*MajkM*MnJNo9!T{rqI^W<9sLru;V})RA24+=8Rz
z9V_+5zgbe8=LCIE$n!T{|KWlAUKRVFjL}F&B3o*)8jX`4bbq=(OY)Wn*`G4<wGsI$
zfM18_-Trwm|H{$Y!94Hn2iLzoeV`R^Id^B}KL2y7&-=8_TV1)|zwY~uZdH3aM?!Rs
z<?i7QrgUqgN#D3K<!1_8(m{U8*b*+CuV?FV;<>LE#|43J>y;Jml(RL;0?!pMTY7FX
zhC=TzT>ws`9V?{t{vUc7?;+!?>GM6F+hfpn^<%$cZb<!aFRw4zI+ryIjTNmOWw!gp
zta?j(*vHL!{;!V>#M{zy!8UXXp;HSwacTS<@MB1JH}^_@ruA8_;7Y!|aQ5dI{TrCe
zv*$%|M#*zzlcROq*%o|+j=A@;_Jv(g-J`t}-A+3E)oyt!eWZ-Wfb>=DxA5%v22Wmd
zW$rL#lz+g(Q`^z_+3`ImL&`r$zUIb}KO_5NdkwPoC0YCtT6CZVmtv5O61JiZK4sbm
zmidS+o@q~elQLz6dZSO+pHu8jbtAka!y0oV@7Ry67_AZqs+!FpP3r{OOPtBy4>|hW
z2D~JUY0Zz{=+<T$d@m!I#QumIv3@8VSj&P2L6o<lIGC5&)(2f%;(ZwdD7gnNv=`4h
zb|&F9oJo*b_jop*8mrp>8kVpzte*?d4b{QE&wg+z8)oZvvxn)v59MKc+(QTPP<~|0
z#|nJWB|g$W$!E;RW@5~XhO6)~lMW{w&gI?EujlD!GVkfPe+d1qboII>bI1g~gX!vF
za&b*IZH(Sm4$_<WXe<{dYd0<N%|!+uK0kyH-^gxjC?9I*l`><g&RF8Iv6SS2=&nmV
zDCpVo;N}X?1<wOLdmbFL=Lb2KsPj$q$bcR8W9bNa%f`~_)xg%+X;ZY%qL20%iN4YW
z%AbL*GcEi<)nN?V7-{2+FlLl5x@YAd@cA2t<RA3;8qZnv>s1F|?I(3e+`i9O`&s!1
ze7@Sx%0C#@FJ|Z0i>`g?l&tzU`+VV_m4CqJ&kU)5Fp)o9Tu$G5%hQ+oS@}2ne8aE0
zy#4{7AFBO~{DVG!rkb5!4}JSX@^AL}rsp!?A0Yo|mVEx2*8#}TZGrPQB&X)@zq6lr
zIGy*ke%_IE-Us@5t!fJ9zxVTQOXvMbKksll?{GiwNILJ<eqO7XYVV)=dAFtW-qz1M
zoX-2(e%_IE-iKXYH1Elz>&broRx5>5f<CvU^AhwqoX$(o=SVv5Ns0EtRC}-J=SA_(
zn8)M&yu;~wFLZfPKhru)wkFdTPS2%EnxAl<M-Ba2;wpO`T;Q30m~T_?HnB-s#p&aN
zJ(YJh@nBoeDSb?ye4AE{dE>{lcMSW|^7@NB=|`QHtMhS_KFJ1+Z^6Z1Io88p!`C?6
z&X_}Oas3xu=@rw9L*UxDexPtW8_mZkU&!8lKj$~Skx`#{9dnq(yw2kk)f?9CvU*p#
zHjh9HvqSVlv>R$q(|%3C^N{*B#}f~mJnM>h*z`8FM_R@4u&!t7%CC{{th%kBFP~<6
z#lto{yv^}2wlUNb4<!djxRN~7x041J9(Kt4CjQQmUIq^@aQ%*KquGWba7D`p4EO1M
zxUo$e0#`cy0mJ=QFB?}3%0^cGWjywMP0Gdts^|L>)f<NIvi3Z#hoQg86#ZXOrVinw
zZNo=nZ;I_tsd<^2LN01tk||(Guf#Idb21hA&5FI4|3+QORHN<c4#*UFrWdA=sT-Y4
zY5W@R$upTMAyZtDOif2T5?o|TdGuHDqCGmp!R+C)`#g{Rh#~McJP>#v@w{g3C!&2C
z579gehp2qIon_^H8=8wK_GWzY^cgz#(|lq-@doB~8i#goy88itmu@EBVexY9Jr<7+
zPLWn&PRG2UdwfV-tOW0LRpEQh@o|<oOvI;^;+>IA(!2_soDCr^8OedgwDz3jpUU9y
z-yb9n=pl>q&EB2Uy3@fnb2;#gU`O8zSbRdU=R{ugox#B-aSblX^^t)1757#P`ulxL
z(r4QrI%Dwy<sGiNGP3Kg4ClwHu1{};KHZ;huDsiPp8N!>V|g8SMx<aj9Ze4x9c<bD
z0oXqMaFp)rAEusg6MwZAQ!zB{#atFkOVj(M#6jBrTa^hvZz*73r<{JUF|^Lh{I}e{
zaK!IvWJ_aO<-(H98=e38tG+CD@<@}hY_gFkyFa7sUcTK_S=w(DmJH@}F{2!Oo6)?=
zw;TII-*#=vPG$NwXQ0DQpu^^vV=jz5jk5`!7V3Em^Zq-T_aiIOSU5NZ|4Fxa@f5ru
zo*l)jx&bl^{S;%5*N}Gcekb1)Du%^<EoHQ4_NeOKsq@9XUw)p)(bw(na<Ogor(8gn
z(C_k#kxSy_>W9Y1KwPT?ypq$a8mI9XZ1c=DdyMu~rs&5dX_4%k{%AY>s<KCbZRf>-
zr`{uf-@ZNK{kAASboqz<yY~D_mpHkq2L}%Ui)%jb`flTB!S(&vRBBFr<_i7)uZmA)
z#JV=I?gM<ukZAjowXAy)mrm+``WDBrR3@1(8=uTC-w%B$V|Z@!It#kQI!iQ))@XRv
z8cq2US10<GD}uLT9TdIV(LRl2`RI9B8y53+{Se$_x#(HAn6HeDO3sxHukD^rCmg@D
zb`<YDhMz<C9;=V?)tcxG;>MDNmFlW}{95&i^}~K$jdQJm&T^J!GBz>{UbL?%3*Lc4
zz^ZW}bBa?O=AHI<-Zz<h+GOtN)Y4;*P2K<4Fm&gUC21ks4}R+?pEJGnL$8Y>Jy`H|
zhr7mgG(Pl={f^xyCyyet;@cY9wsWd^j_gKAcw2fEy=3x_&O^64T3B0O@$yZb*k)r_
zbFblh*W-RY%a3`r5mtJ?!FQTJ>=rp|usZUzZh%e-{n<PP^c8u7-_BC!ZEme#E8n`z
z@9^t;g^g}~uR=b1bfuTVd3Uar;Z=YCK>j`SE!z95@^|%E0|>_TUEP?@6j^Z{U>IJ1
z=kO9-?Hvva?i^da8xGqNI8at)&Ta9Hg>TQw>`0V3ZxG&wANJwNcL>QB4B`5t_ECB)
z(^mYbeH=^R@B6r^`hQp-Z&}{QbBn1yZb+0_fsfh`{y4r>jAijB&Qs<uEo^=ho8QC6
zH<6=<__a4=N^)iYHI>Z+w@pRtD0hu{d#}28mD9H{wq`~C;~7sXr!po_0qs;*IAd#o
zCbC!mE8dsCX(XE-vCp4`ZE~8?r*j7T^d#`p_ny{=V!sbcH{BNHRR{CTM*6(RQP%pX
zz60X{^}U1+tE0n0aOA?Lx9|7y-S&uv=1Y0Hh1>9Tl?H5^zo|^qo#z%Tegb=#aX!G0
z3I50}L*Nh51H<ulHYz9%fp<Cd@aJNs&&0Al8xf6VD>~4-$u}JMg!)!u19nL^SNm&n
z|G3w!ACS*?hxyy4oV}UXI=<@aJIJ=#x!~3k`k2f1b$_?v>XD~<W}9hqw&=g(!bZv$
z)j1&sXCH8C9?leSxCY>mXK=WSCTTc&Px^|D3gx(LPmk~%I}$Xi;L+o`#r~D!*k1Id
zbh_rryzgOOel@({i`Pg0!ddY=#<V;XSj#VfBk<LR@vY);2#bD<H2d%P8g|~EaE$V$
zBetTWOx}@4t>uoMd!c>%w>5v=Kzi_q3!!f{+osgueR7=(+!}4SW^Cj0jnKRRE-mPx
zJNV6C#{Mfkci=<C^P%bPH*=59WY?VOF1<IgyUoE^n&NrEKV6n{u-(7OwU^9jQUG=!
zI`}qQ8hiU_Q?hnovc8RTO;rXvYkP<FOc{7;`_W<;MR-RUJ3mil;OUIn>#Gg_2JZ%k
zdd6qqQ^xI8@P63?8sGFy=UIv;-4K|%*Wt~tK_@+zb9vL>(pliKHMl50dp*yo@)7<<
zU*&ZiJv5)ydC=qsH*+7Luih)r7kZ+f;ypXIwlDe$j`~-H7ESsWj@oy9+t(c%YhBs@
zmek?mXlQ$~!`$SPPPo3Xzrx`Pj7@o;2JOr*kKh-*+!kn$OMSF6(UnixneWL@g6_N<
z-IX4}ts_%qPb({{a~x7-1J5J%!SiUSOgE9~BD$Rmd%8#GnU?F=%8Kwh)%3xJCUe`e
zv!8}X4}65juEhR|AYm^nz^r03NZY>dee1j5^8YR7uDxxVcZL`1y!;G%@D=KAqV65Q
z<7(UhPG>N;|K7<xjca>*6!%eFse7%%Z+pO8lGs{9G`fMy>&;tB=-d+D+g#qCziO@%
zytI)k-{JZv8Pb@vdPR7CgBvp~jhQnfL+G$Gl-3!u{hWeNIVXGYmUqr^w)0rJ-#a-z
zSBEcF#^q_8&3}-yOlV_%J2ITkyT$QQbCi*e>`f;>Q?xxC{eKypPVDFOdSH8852enw
zK1BNkkAD?;8}m3J7uHtb<$!)gav*tY?4k~roqsKyI?$o!b<-5zERCNGZsvX~dvD|M
z!yNdoDfZS(E$zAM`2BlkE(Z?#P#8yix99f$DQ=g$hjCP)zt|1YWd0n^F;yGz#q7>{
z?3em;Cuw)4`a{}})SoTD;!=N(^oTRaW=Up|GvSgcXFow1RliNIdKrynOt!cUU00IL
z)4=%#`cseOEFs&W(@XRBAUE`DwjShj*AL1~{6Co~V8E|wd;yC)>a26p2I!lAtCQi?
z<fR5It^s*D?!INab(fbH?zbLF$;&R}Wf$^tXo$RMUM+c1e|_I(|IwZOgAe2E+Zp|F
z*kU|Jv@sipT$_!%lJP1S=sVlf+(YhO>*WrbKWMpopmf<nn_Nbh?=i+`cl((K@b5D8
zn(0~eT2*?|>Dn+{<;?dfbYX`&W$JJd-;DP+Ne61*mg0@_0X5#HOUV57$Pe!(b0zS3
zP8iQ?&JB<yaFpzHPj|XOI!Acl5=f@dkJb73EF6s^=?kruMs*Z-Fc~8KD#h`tP9|+%
zdlR^%mq^$ALi|XkEAF>7Or=vs@y^*|ZgP5y8?*5|2^&H@1>2Ny_BOc2XN32lK?N8g
z_<}=(cTAJK!{7Se14sUOAUw_QwRiM1eVwV$zHA?9A^YCU{vvZRKEfrM6aFZ?+39)H
z1cwr_W^}6B=w1&^O1<%GBD=nsGtGNFivw%ysz1itS?W{H>QE+*r}00Hh$q{hQ_gQ5
z$pzu4KgX&9d@h^&=~?Y1c~6@0K1zo_;<3(quz4kZX<Uaq$%}j|)iHWW$M%r3ESbL(
z`Q3{AE<!ghzUSBz{ZFiMsORSIIwKeyWRDucVTyZ+`*G-_eaocpxR5*PvsZFI#C?*x
z%7||0m}@p6yV3h`-t+z)8fl-r<|NzCJT}IqGXlnUPLR)iN7=)noY9*$jou&i^!_cs
zPEi9V#u<L0`yX7Bxf=ADZBXAo8~xkxrr>md^t{HQ*21nqw#5TWYbMGx$>%ayox$;&
zt{2vPy>-7ksr~eh<_Gls#~#Unz8RMPt~R9;P1b4K-qA@$;}Y#%<K$Xpv}gVn=~Sgl
zCg87lFaO)(2I74pPrR3Z9rL~n@0*O3s<%-U^w1aGKUgy5A+dgA>o)Kv`hRQVPA3nI
z8e<tA8@_jP2fk>pwH?WVjqNQ7efI-!AYJ~8>dB|TA3+DR|F*_D!0}J;-wM*XtS<NR
zbEzX5st&v#7)NdLZ(|*2iZ)AJ`u?a%U0av*<<C5TKBOJSW@C!9DPUD76N=9~lO{XR
zC@D|;02lh2`$z^Z_kv4Ja2+4EpLx{${%fi^?OmR192X2^7{5GPQ_??nG(NolMLBm~
zk=htNn$gA%@d>=BV|X=zS@7?Yl>+a=Tlspg@ZL6m(4Fg5<NXVarFL(8=O3S(lwW1*
zkv)~quytwO*o4o_`5MS-qvZKq@pMJEsjXO78?N-NA{@C&34T@v`Kfgo(cNU4vclc$
zSxL_>rf=&THa3RfT0%$F(NQ5fiVImYy=1mkI084uZ5lfAuCb!D4Q=d&)}oa5i=^EG
zK0ZGz`Z->YJT9A~_~)6@$^64xe1H0_VAA&1b0&k0$G`Yae*43N{3AY9o!G(^yrDX=
zm1~mg=|irKq@T`3yvY8;Qf9uu+JSri7|&z=nLRBbc0qL2e<}H9!98!}Ik?U}@7D80
z?s=ZIJoWFJ{XT1)OFu;8DcPqrb^5=L{?o^?a{qbKr^onB&_;w4wl>D8=-c~}Z;x?l
zW9)3?u?Y<eT-TG<Bu1feruQ$nGB)mbXFb^QMEf3;-@_l=$+*&Uh37B0XXbSQcFFkw
z3*Zb)mEqs^ZZ4<i6TTjJm`o{6^Lg&_Cv%UI-(6oJPJ}#_y*#y%{Sva@L!Tg1k}biB
z<w`Oy_&wpwb&VTq@mK_R>0x_s`ZD*rzF#9+sE*$0$Ic>tl>9&&qaMGc-_l0jL*%^$
zeq4&9Zz<w0Jo0aCF0Aurr0=x$ZE*H#O*g2H9@?4HT8+k=wQ&Y*Y;$MQXg+N5f8lm|
z-+wrT^!YPZum=@z!N+TW--C`56sQ~Zp~sj-KO!f4L<`BN#r7GaVGTTKKz&kd$9PE}
z%<gfIV?91jqW)>@noJa3e9O{WKCR`_V%~#$>=Qm1oWAkn!)Xzmv<CMv*>doo_PFX?
ze4T&xexE+$(~qRmW%t$J#V`fOr{9%I59>z9ew?+Odhd8zbylF&6#VPJ`?4P=C2U-&
zKL!r-Eu{3z>|Uo+6c-d<#lM-Ro6|PvtI0lj8sEm#9%;O*Pa5Y+)Bn<~T#NK-0uK7k
zY<L96=MTVATF${S7>nRUY~5lQZQ5$5=Gdf}z7igkHJ@zjD0XSzq<z=fB)>o&m(3d~
z7x#7BU|%;C(X|!IQbv7>@X~iv>HcgA6J>>SwO@W{?5{0d0R6e5*q_EwL;o^To0lO^
zRs3bIV_FeU7+0nnwAVoRAv-pg(sP05s*}Sm|2nex7{2!AVBBO=G3d;(vkP4IfeY6%
zT=ehtaAZ%n9_;Cs`F~O;H@<)`Q7_%Ur(WY<^HcsDtt8I-r5BN@J91<EOJ;0wYH81t
zdP}>vuWJzZ?FKvdj$S!m9evc!6S>O<${ml&?WNou!OqTz$~|mnJ)j(W4Ll7@w?%Zo
zZayG7K%YhAWdRzfe5=$O*S87wT<eYNI|My1sz0HBX6|yUf7bWY%4f{jJSL`TX9!Kx
z-`L-Po{VCt-VT|*zX85UW{PfX*xs80X{q$>=Z0?IPTS`ZTao;m4N_UX7n}_;z5Dyn
zMd_STC_h>8#Ji3YFS<P8)4><TWF!B;##N0v&|@HWMVgJP2&aU6M|diJ%i7E2J%QKT
zP3n|@#bsmd41Dx?Xs5X3g@NgXzHQ_GkC#rH4`X`~ev9?*-{;?09{(tYG%dULKT~$k
zaDrdDhtS{*Hz(7W&n?X7=6_=;FP}>>W&77J?azK9z-F>n4Ba#ohsUgd19KRyy~nmU
zjRW!WXkIhA!{boy^CRldOppHP9DLQ6Zi6oNyx`<d@taL`uUjgdXMMb{GgpjDLwkeM
z8q`Iy!;M|!afv78yM5cq_TX)!LK(GpXR5tBNxw5C8>9`D4Yjw0I$S0LH}H%+M*WX<
z5q?Nlwmgb8tu%Jper^c=Ze<+B{VXQNPqP0$Jsv*=e2hoqf7kHE@l|8~SG)`|&P@hi
z;`nbew;q0zZ~W%|qqJ#t{20CFQsS(lh2EQt;Wzkqjn(6f)m@C$U8%8(Zq!&czE4qi
zD#ZuVY`h7s=X*HeZKqFLHb&22EZpbEq{amF92gVybzoe+dWA9Zzp`lbBaF+{aQOZT
zIJ|BZ93ITL{F)ydo|Z<tg<wDW6Tjux$2L{Ho-0B3L(rT{GM<#lXuc*Nc$u8-^K$l(
z75cM1t3OW88$H_Wp>u0$cUtF)+x$<l!}-S&e^2Di%4SIh5@S#GY+t6*eIJGIrU_)Q
z4a}9+iAvN-)RP^$CGflk)-pMx{Ewsu(tavFMKsqiKMCKaQO&Kl`5WtDj3xB$0{(#C
zXYiJJ=7|p=MzRWA*4f;*2>(&IEswA87QXWJG;dlBZaQ|C#<zuU7UG-L<(n<xo8iO2
z-$nQ+KWDK9-O9mD_%Q34f39clw!TrM{Z;6f`;{T|`|;qj9(-=X2L>N-%D^X0_o4V)
zi~qWp`Ai-g!nMqY4e?>?_^@T@)PYVD**<JUuNL%LoVtI{;&J@(at^wU2+x~hJXhi4
zP(1&mKK~|kQiZYCT*c?FxLASwef}?q|9`6XCD}I+tNN{5pk=gX&_r$u{n#P$1r4EN
z2Rcqb$9>ST##{he)v-?tyO2Bdp!^J*zd)y*nhO9Yo(t@XeEf{LK(gGSs9eTe0Qi}6
z0j<9kXuA!4_R)7eBmXu((sPwL(KeqBT^d#Y-12iJ$}HCC13ta#wx*aPM9;^WBlzb<
z^>f0NSv<rX!9Q<bw;$i;Zen;#pKbK+|Ezo{(@ibP_WbiA&tV2nXissk*e8-dRP}3b
ztLed2<T0q;_hZq6Y5n@+f}0-aL*cGE&XLPHa#>zM4^A+SJLsG;I;Spuh#nOET3#PY
z4~Z95?oIB2?Xw`(*taVqi$m!7<H2t|_}zrQ20w5Nm*dx{k{7VQFJ(W5;`L<4^d0EO
z%aAFqW%{wqxb85nC!pUx=(p`b=*J24V+Z|c_Qm5{_w)?8i=Lvd=vm|rJs&XM1@LZx
zGZ$lu7^B;}7RPSyWxT^9=AHP___9&_^+vBJ<qP4@Cv~RAmz@_<p&t3trSnle&4+xt
z{HyXl-nmEc<8phWbbKY{TNz+!yfgouznt}B;40m8aK*J{@z1798$QnIZ-@St=x>ew
z)|U3r-!Y5%{1NT)9>r1c(=Npix>RZ1*2r$HxA6a=8|{6O_rlU1*4=Kjy1zo*66Jzm
zH#8a3yj=5q=|-c;#r=Gp+eVwN-qZW(lA8#|_H|A#6T`j~pX^ed)9G;2exwsxtM#$0
z1a4(;6AX`A+{W$HRXYEB*FFnZhUWs$dM{vul&?$uY|_uiF7;tmcpvAzX5ZD)e#h2|
zp^e#sm=AjIL4WDsCeO8qKmM8Y;e28Il;I7R@S+@huR5pK+xW_?71p6Aw6HY>=@0tm
z;&hTx-WxsSX+iyj?j7W&$(?I+u-5!`;<0v@FRrqZL(MlE+^vpeyZ~IzTuQ=dwUPS{
zGERRs2M_Uf{%UsyEilU=Z8lTw05gK!DpB8$k(az9r2nj!(m(y1Jf=l8H9t2W0eWnM
z9$ea6z?|OB+m|1p=Q?&irU&`Z!^!X)!H0L_r`4+u@XPiG_UQA83>sk{9WBVKdAcm}
zOdrHcv-PT5>Gv<DT^ri@f17p1{{rvYAE@%at=91sXi3}4XeoRWZMAmwX?aydOZvDX
zEx&?}OYgb-9`bH+tj^iene}Tq)AHkzp~M;%aV*=%cLw(@^x+0B#SiG$t!?55?Nt1r
z;Nk~XuAH1hy8nx0%@OqtQu*bq6Z-YdpJ;qg_`}QD+x=X1!O?c57?^mssYsu>8*aye
zfuA-IyCluVn&30GlCk-S7V^z({@SGM6y>-ymoG~%sa_J7D(zKBs|?1+1Y;&z8|is`
z4p9#OZ~!0D9uz*ifWakvB7Ch6cP8fC@H2!C+M}R;w5~-CL+A(|wl=}tWLG#w>n^0V
zkg3@@SMG6vqhs7g%gKnX^WOjtYJ;?yCBLpCy#l-q#4v3g2Y71l@hLblZ3QC{e;BG;
z4ly3Kp<A>TF){Kqe4(e=x<nJ5fgM1%@K29L#sz)~enq|Q^-YO+Z;f#>MZap!cgJUA
z?Z@e}+%xXWX%C9o!bNZ|K+|=*(Ra58`iH0Vp!fAu2i>=@PIhMGS@-2u{Lb(vh3~CD
zA$-lJg1$v`H<$TU=#_Ah{g4&<J91CFXGi}s9NniF0PB7sG1I`UcW1^_cEPuOz?}dt
zm+ZKm2gm$SdrSt_*?2d3sybP+{VYCBF(~^_Qkxi-(vUgH`?OzAjLVX4W%*WfK2=uf
zhI2yJZ7fW98Bf5C<<qBW?uftFU&kOl#(jdZqH<+$3K?%ITOOU{o71?w(UHCfSFnCT
z*-$#UY4#{^|22`^@$ZP}TO#soe#%|`sAN=Qqs$%xtq(X|gRP=%^ZDEUo1T}RbG@Cf
zTY_irxhJRbZE@>ox_IJ`yzW@RCtUP)w!rgN|J>vmJs86c;B$4zx3)caU(s0Y&zVMl
zFeH|gmPcO~yGs2<^9vtr-DJDD&;97_4z1fn){Dq`RWv}>!FkpF#K);KL7fhDxa33X
z`z3rA{CvM3vw$pAkON)VLdn-$nK8#*{*CQZs_?uxIyt8~O9A_gLvQ7`!Kbz_Q%kJz
zmDu~HJy?RtK9$*R$gqEo#+uoqCVPjfj3wkxdrM_gHD)r$dWpW&=?51+UOz^J9_a$7
zQK4?z+aNtlhIltQw|ClU1^KY)+A+V_r=M1IdFq>RD3_hCHhV@H+Z$Z)u*f(3f`lyA
zz^x3OBm5#d3pdpRhV|dmcSl6WU-NVnjlj*yT;s;$hBkDT->SOoi?IEwZQ4%m58kPK
z#{K1EvHsLp77fdq1E?;r88b2crPsuR3xcQb<)5R@cjqjUTcl@!KUakp<ZG|D@hFDj
z=bHDTd#X<N0As(+0WM^}1K**WKa<2q&ux!e3@43Cuy=DXJ%~qdhzwi~ofn|<R%p+~
zUd=s?UC8qx<avvi=i|_ueqdwVzS1T%;N4_<7qY$0_0!(*lboz8AG{9HuJ&W%|HiWZ
zIq0bR5s&no<k4NqAHsv_eqG~%hqDq7${+ALc#3wKZm+PN=ghNUggx*36v!_yE=iAZ
zuKGQsCGsj<_-3|uw1lph5>4HAJF*3Cd{UpXw$DuE<=^OCds(4@_7+As*xaY-b%OGn
zl;;|b6Z@70uO|3M@o(y5a|!&yDG$r`aGr4TY4}pF)Ncoz(f^Cg*Y=%lI4APt568GC
z(`h&AgYiy!3S3oIYnUddDV~|nN!m!bJ044RmP7$rqON3O{tsE#Z@Im&vX!x45RI`m
z<?LBw>_N!&4aoHza=n0Db7ji)7AM!X_qjwnlJgpOUD7L(?J}}$@AP+<_=qf1FDc6!
z7v+oKYYiG#C}VR*=(6Bo?0B?br1OARBM#CpKh~X-ze7E>`{k@U_#g$*j`p5Pdz6zd
z-0{(VS&f6ZedZ9(KlU(hTdmwt+EyQt#VKe2U#+i^j47?gCElx?=RNY|{BvUcxxcwM
zH+u*AQspM-zxwU`ecQVg*&~w;mD#5<(1EtFE9;qO?E&^4tK<IxY<sq8d-fXe@8Lsn
zo_LgIxWbQ!zJvV-cEQUt_-a0=d7SXJwO-*?(RfSJEK#RG`KFISaF5!E>3f2*P0maC
zOX3f}iDEI<_pRhr$a_g*uXha?qFu?;t}R>^q20c`Vhie9rky^7EN?@W_aVm<ejX(~
zjU3>A*uH+-XJ7MitK+h-$jTJ$@oai_KQ!~t<}XY*e|8`ZA6)V^kj6LP()|NzoXvp0
zGnl4-ve$eX`&aF|7xAfyKSEpcoMRWsx_E7}a~%3#KRRjtgmC*sXrue}@Z(Hmu>w69
zONuj5evG|{lMUHj)$@4<XO3^zRBvfyZ<OxZc-v%f2H*7*bLKZWSc$gT*BQliW8MkQ
z7ZUgvz+ZEdVfb%O;D3w9fAdcn|D6f^+u#omhvI)v0{^o;{`dTp@qb?e{}T8kZ$t6l
zp1}Vb9{=q>W&EF>z`q9mjE$lAe>#Ex8$JG?{wd>+-m>{3W5N8IPmB>es0REW;WzL<
zIHQSkngaAt%g-Ba9)W%ev9(+_C+aPYZ;AHAH&6DTEBMh{`}=65A9QYm#;w-28{GA5
z^NP><xkDXWS0EifK)Orcdd+`Ndt-*^%bzqpel8Q?qwg^%x#q9^8N#UuPFxQfrwTTt
z>E>AM6Of<i_R&56{dVTBV%Oz7{DAfwTci2&s{Xs1SAN)Rt(~io$O}oAjyArMZhDq`
z>#1wjYHzyYHani|?5F0e8`v9Jp5@yywX@f^bBFt<qUrj_Uu&|`t<pF7W@^jl$NyYx
zA}h(Zwk6v73T=@ex8-Aq-8wd;0$$Kecx}AH*><%l8t6Ae+ll97+UGX*IYj<j$UhhU
zAhww`KVl~q%USDaC-@t0?9;6AXSY~iHr`0v&BQ;$UdX?tC~My}Mf82>clv9T-*Ry@
z=EpV$y3u>5|K9z~_*&u=KA*d_&Ahc7>=n<#XBuC|8g)m*?zjAZD?jw7`3C-;=tn#(
zh+s?;<J13Zly2?mz3ASjU-H(#_G!RN`+w~92lCilgMm&k9$Wfl>++43(tWwN|8m~7
z@893ad&lE*1$)>${Kgdy|1>>>^NRh7`|N1$`|Nzx9=_^))%*gZe<eZxXFB>@x^Q(o
z7;8K~N>9Q&>iT(>!zK13XggC@D#%I|IpI>g$>>?Oc!GUrVe=o+m^Aa#B<G5YDy^k*
zsTitHx3WHlni<<m&xf`+|55&ZQYO1E<li(U+S=k}_v>DENjr=mr?Fwa-QDn2<@QNO
z?86@)gwy!^EqkN<@U$Ui&P|lz{Jl&#Yj4?GekW^Jrv=rKZD%tEv)d|b9H(&Te*VLG
z_Rf0ToZK^>#~Po9j~Qj3)N%T9#kRmXv#oQ7v~_MqTa=C4np~k@>U&nd)(&ZFZAM#^
zjoLDPlpUQ%{@}ix`Rg@wVcqXx9Vg~|Q!!_2E1ja93#>J6(cH>U!Edg({F4*q+f`40
z7aQyA7{-U>BtW0mG|wZp#GV)S7DQ*B2>xX7;cjjjPmV}O(e?)?bB*J`;ChKaFQKu^
zy=$MW&E?Ykq;6Ow#uuDv<I3jf@*^s;L7Yj$ct36CcU>HHNL?FK!MgnX<-{nW*aY?S
z)RTW=x_!#gAPaZ3FBpv;xN^yFnT6Kfo*!G)S$B@U@ann!qXx6#(nYt{w#1lYJ{8aR
z3fRYu*vU5c9n>$R?8OU^g|@S|$+L5bxiD_oD^o_#TEDS9?SzhdO~0Pa`<B7|a6UdO
zlzKb%U{5JydXIbb-zd$ycdRF`l<LC?uQ%o-R~@HA&|9|z;6qu(Kt#7>Uihh#mS27%
z{mkN39i901Z#6z=<}V7S-$S2Of9opw3#;UV^GvV;{C$q*U1Gdp!JR9biRU)!_wasn
zJe=Yxa3)rPvptvJjQzHlT^2pam)u@ZMP4W2mzNX9O%U6{zsb-w8gt(OcJ!@Z7Hskj
zHglrc{XsrUzcv2m7S;(zsx}rr;l_fUMRaMz|6uO`E>Aj?-yB>Q%qRxYLxy(wvuYbd
z;6Et=|CR*&=i4}p_aewo*_=D+;^;c30NA$Y4ET1ogVtauliV+mS!WY)sWS;Z?Of?)
zb=cSAad&&wR)?v$y4H22S2hLLS-;Dn@TYF?P5rg}ErWKs>-D0_4ds8)@hJBFKkD^S
z7Od8C``S7ao3n&ovGOD4Z(?`Py3Nv&&F8Q`=^^XJ()ov@{KsYIABpl`u6)0~l7&;4
zfz$5|!O7AioTfSV*XbJJw%p%z-@}^Uy;6QBYQOL6cMsz0ByjEfq9@RG3&D8-|7)Ip
z*o`Cm#+KW`nFmn!h0E*q+hA>C<dR&Y$=Kks*lQ*(3(Rj8xhQ`*F?(NL>u5F>|7g~o
zpG<nDZ+jfycG%h|^EufG;_=vCY}Oa>=|<U$&;zFmG3;2DPj#}~a$}Kmc-)w#Znua`
z={^U2spIy!;a{|wYxRJwJ*g%8c0_yFCUf`V<1}5LwT7p4`0{?>Qdjf82p`>9Bgla5
z=YEgRfYWhs%<chCFi%Bi&Od*JZ}rnYIPvlZem48R_UIgJqs1X$okgF4x9UDE%4j~&
zD7f~uW})-pjaRSl^UB5YfydsXcn>Lcr9-tx!2Yqqd?5D-_KdVWtT}8=+hX!YYuRP#
z44d;&*WQuy{x=C%TfA23e48-o_CdmzHtTqbZTmXXDcu5Xy{4OMlz_uEcbVz2J^GKI
z;r;=yZ$t~`w)zGETqpV0wc)~d4Hj39e8RY2(z8*W6Yw*7zEd&ZV`Fw6MU<BJFu4o2
z80Ie8<PyxG^ZhC0yu*CI%sh@udwkUo@l5uy`{%Fhuk*IRzsyx3X5Hc}%(7eOWo~Qd
zei~g=hRb}#0_}6@tkrq`-O;T;tNSl;^ixa%I2*#j{~?5D<DYbV{WkTvF5ukB`72bP
z_f2jL*|}U1yq@>jxNGd3UZlM#=9wxFF45i?$%xqr(i@usi}!Rt^x?d0Ph^7|A3BsT
z7X$MR8Xs~o4d%C|_f=Ln>)eE-A1XP>9mD4bpWqiR$whQi9Ar*0fSk^@#P{c{L#+>*
zT>O%g>3DuyP3>n*$6=cArRm2NeKg+}JdDojCs%Z)t-=4uD)4u~_kHkv0={!KYK&j}
z?{m>BHU?{+c9PS=N%u{6oaV-<t=-*^oYs(sCNa+hU6>a+-S}=7{}O%^MfmcI?6G)r
zwK{U!S<HVKKfdl`qz@^hIqh`4Pv1tsI>;(zG#{I199h2~?RAB4oq+cmb6frR;Lce)
zLHWIXoQJh*bG$0D$iJ=3hDe|E&{1!GOSRi`dSJ^E=cELW>z|3#q7NR|LAg%pc;-yd
z6nz3e(eun7**|D!HcbXspr1?N&K2wVPdoi=XTlDlb&~$VVY|)+TNRgtO-Q#n=Gsi!
zgww>oCory>e!Owlv)PI_YrJ`#_q$%_)!aDK8Y1Vn!fWYx(TI8)|KOLD8PPl%OGEWl
z4Y@5Nw{_%}3z^lv?Q!jeiR7wL0X|nexBpcq6Z9o0pH08ouKnn&SlNbU{OUzEnRsuL
z@)>nZb|{yYS?LH{2YfJf=zBLUZv`)J1#fo>Zk#o$$P?`vZ@B9@FW#J7!Csf3TOGQE
z(2Yy$8XDKe2jDL2zw*$v&M!H@enO{f*f-qwVWRQ151#hGO?7;l*{FR^cXaO{-^0^f
z8oKRXMl<>!@y+NUzqf+iv|L}=d*$ZQN>kovq*FVtOx?FL;p>#$U2vuaw+UWcoQq@S
z?K?SS^}K4a8vgCh-N7H8<<8Qkzt{oOckF+sy=r!hyZ|j*(6R_ExfJ`<-oo>%_`Pdh
zX5WAW@B7y97<;;Y1zymvEFWEaOwC6pe;~GbQ1K-DA7Sk0n!lYc=jTXfCwkCfNWOI1
zhQvR^SH!22_$DQ7x0=wV2yLp+hD)@Od`=)giZiL5-~@X^v9b32j~76vjPIcj0mttX
zu)Wq(z&WvIt?6Lh=|_2|V9+OI&tyW+Q#{w<p`PoqBW1Jm$lGN1p~o%V=&Ae`V-9@m
z93H)wovehV`}c%x_Cz78VGVh6Iy#E+5hLeZz1yp~**yKBjARR3&BwH7?2PSEQu+eV
zP3GQOr+D?V@{KRy50Eat*6$^6%8z62hI0T8Jv{@rf(|=I+=;wQ8r7gtIiU-|OLEv~
zVq1V=G_QlB-bokUBcF%%6VR;*ZdLcqo|hxj-^P>A&1UnYO?x5jwcssR;{micI(v4`
z_Dj-Ux}DKK9>V(y?I2h95Oxk&cu}>QyKrMp@kX=pKcCR&RqeAHvX+&mPeDG8*<Rzd
zd;`gm)|bo{m*Gc&cjN-zJ3Y|yX(4H$dp23~<zoG!_bT!Pudiw4CJoPXu!A%r*tXWe
zKc39zY2pX}J^Npq$UzmD73$W}RX!hoW76`ex7Z<Oiq2KMbq$xrNvNmq9>O9r6i}b{
z4ZPR!xeWg@c!bQKI)m?;t4P)*U**e?fdcKSEOkwe%fWuTw?^DO)Hzk`hw^o%IrlAh
zr*tLwpMO?P?;}0lftM+tX?daF!d1ALjPtBDwFs_@7m*)$z5rK#q-0X<iB49J^!Y>1
z4^e)E#{<^a6{l|_Jo@cAUPQXY+V<mS^fi9o65%c!h@}s0a|<%OhzxIItZ+qp_H1uY
z+4ujrr+*}e%+<!>_56PInY^v|L#JPD@isftKTewtW_6~m=60_ryZvj=3-eob#_vO}
zcInRv^G{x)e)Rrwi!)7L5EPixo)gT!kNUoSlgVAs__?>o=LSdeI<w^b-;q}%uMxgq
zLbl!yj{lMN8xDV)&ljWvk!6hqo^P%KoBMQkG&n%oZBwi_+$Z0#W9bJ;J3Qt5je2o3
zf5boE%(M2|b&sQ;;aB;!$hdIskRIW_jWM*~``&Tu5#zvCEHjcr)lbT|&NwQ6m4AeJ
z`Dbsj&0iW#U~`#Yo~mQ9iC4QiHbztyyj9+O8t&m%Y<n2t=JU$YyYq$ZoY(|kv|r5X
z7(DOav>hJKZ$h?8ymN&kqrpM|JUyc;ZuQSv|2A4Ho#&gYz6|AW_0QUmX>pI3Zmx{A
z?cfd7The2a8^udZZrZEsxdDAfdFeC5)8pKz(I+nY;ro-JFUg;7`FzGHGHm)b)~Cu3
zeSST=epvST$i}kzJ#YZ-Y#sUZ&s}ty^keyi_eEOH26UxMu?6saGTdr-m>!K}NcEC3
z)_wb$wdT*eJ2oxDCz?X1bkHefbPAVZHHtrK9*#ec9m6kbySPpGGU7JiSpJ5`OL!~R
zB)se3*k+E%-q?rkNA|l)XUzNtI*xqlJ+lug8&L1W@_IHF_pVvHLuY5JT)7W3FPKGF
z$LVhe$JXkwjn+m5-1d6h)W$Z-H<|NBv=twC7u;(UL!pfZ@8ys>1;$(ipJ(OqJ!tGV
z*?R3uUzy+eR(z+5AD@)dd|GwOEnqac<2xunlh!3@U5C~owB~}w_DzY=xJR43kA4Gv
zNqxaExhMl)&-6#U*SG(Q2^n3LPMXaN^<3atvdZ&9$JL8;F8Ub$6EBj^RoNb8MGrmu
zyZN}ET(eet&=qqJXWmmiFJL}%{fXTp$Ii|*$SZf~ANOvNy4(d*w308}XmJiA@G|>;
zoW3Vx-?gPZk=(|*4>(GT?7#Ri@@Hq|q$h2DFFYw@c-O$Y#du>5*Pu<Mr{`t^<G-02
z|Gs{s(66icsAS!EAL&uvW1XkxNayh!>pZ1LI#186@0rdk04oG%(oFB^z2o0~dRXV3
z^stzrJE&*6sYkss{8!wmo>8tMT>9yz2a>+vYV~O+*6&4!UnV{!+G+XxFhiFqKkio_
zpIBFtZ@Q576pzi+g=P8(Y#X~h`dy_x?$Mmx=s>=7i|NQ{ysKV|tA>7*o<zR+SEjos
ze9lPbBL6Rzx4-tfl6$87rv3gl{vQ1pkU{@0og!Uevc)~@cpih}vOX)n?((PU*D`-y
z`J!n-v>#Hx=;0T$>qjzYw8K}Ky$~G&T-&=MUoU!2`g>7Y(&vlPQhwho`Z}g7bV=GE
z<}yKfgVT+7Ro%Q}Qu~z`&`+m$nsYb1{_NY`|FP8HHu#mDzhd%(zhXM}*}e{U)5(!d
z8l#OKbpq-N&yY4IosMU0T3V(|Yo10u(<!P?J=5vP*U0xSvH6J2Pg4ET{LuclMV(AL
z@wAgG(j-&H(zcj3^=+})hXS~jusah8pE8A$`G*gK4nKgN*n-#=SBaayer#>`_534C
zc7eOulM?$}WIK6p&<~?;$=e{_9X%OSD)%u*OQX+jzs~W<@8s77(0Sj=I7vU-z5v05
zzKv$zUfR5jcjK90mE0UGUR!IENBS&%kS)NUac9RbIDR+Omje9z0rwuXf+q6Qt<8`!
zqMzur%cTvqPifm+aDI@{9{dJm?OTzoffuweI?=BIU#OX&e_ds~&F+C~5ai?YKkCre
zmyP|OeV*3kexCV1E!URSZ-GNaa~$Z&T{vXQ;fK7x5>oe*&Rz#EmMtGc&kc!1rfqcz
zTGXIpiFP!vq^)SY$F^HIa4D7$=~R=)|2r{XQ5lUz?vbAo&sUU(oW(v#6<wyjH67e|
z9#Y_)E4Imcj%+f|u}xNbWRq(Suc)4Ev&p*3M7FvFT*cc+Gh3Z}4_$g}i|fnvY&<_{
z`uR!IaB;GcQC{-CqJJVh+Tg@x?ed<fzsNV6to$&;KGf(t<5O_VHmh6)J{G@AmMJdp
zqv2BawCH5CRRUjdn61;Ef0nNr&t;U>LZ&O;M(aLoE<?Sf9eF@=nF2m$3;()^f6c`_
zhIl;d&G_w-S&PY3^c_WyF{AUa+;}pdmVDDix^pQOBz-e94%novsGXj41>*zQwuf;J
zxI8ZgvUk1wxvYQA;<ua4xWtWH$+p_F*i2sjHufZOE|;Z)pQSV41y8<wCQPpj%|9#x
zvyL7W59mjfHrXL9f>+h|CH|k*0kn$FH)zwR5c;)9<D%`cg{EJ#k7$_iw_<%)2CpW(
zME}ZGTWk+}h4ZXv%-!O(y%dc<{@~V@jF;~|$MNzGuY;>z-UORx&U7<<sCk&?u||U+
z(j(wlfVY}M!L!kS|Csq3k`3eeS5}C<rDdzf`ry+Y4uk6f-*J9=k^dWkkIn!W>}6&4
zk=M!2>whnhQI9$4uzL83@%ISJ+M{0gG2?6J(0%ZAvhf(%%MAG7)%`%C+y`7avooU8
zKln8=o_CD)Y#pTW^E=(Xho9f&-v8F$|J<klxqtuP?%wtH#%p)Q@v+>MXPM28Y{!7?
z{2O~GG!K2>WxGe_-_M#kv_Ck6_RxLyyV-QL{SEMaKt45AlY5K*hhJyTq7AlBYb>%4
z<!23PUvspG_X|Vt(Dxb!e<E5(8td}?%Hsp}@Wgq^H6|xh8`QS+Zw78HWKG{5TsVea
z9w*+rb4c4s{7z(-*|6Wo@-o^9KjC6~k?)(9vkg}cuR9G~iwgpG!&dqBE_RTHfgdz>
z06ER-=fSFQ#>W2rMvE(@>uUVZej~eI-ECS^&X9TGqL{elZHstvmUyBwChVU*S@nj(
zi*QfD;yi8JWA&h5t%95OX8|vBeBRSD`;j@<Nb9qTTfbOFPiSNRm91pZ4O-hitX7cU
zJnFwi^fqi69F;wtZ|;y!t=VqTo*?kH80Rq9?Aw~8j>_||L02BXS9UpiSKn>DLignS
zRqyfKb)Cifw!ge=w&<!;Q+yGRSzndS80r%*r`LG*Woy=MW!%kzpRLW!xHZH9pJTVT
zQ+3Mu@n$xedRil~dcW7#Io&$^gdR+p_sW0K7(ri6mbU^YYOn0%TmC={W37i_b)5|q
zZ3cXrPpx3zYS{iVw!e<;=Q168lfxaogU!`95YG&{pE_=5@{GLZTc(G>)7I~zeGj=?
zogP=Z#qq#L{Ih=k3pmnw^-ptq^X;2Fqmvp1?n<Xm@{Mf$sL41#!5XdltNg{pUW!Hd
zRR=$%BU{2z&$ec+G~nAF^sR}xDfArhDOGN3qON4%DZs3d4j!C)5`W7P>D5QE$4L9a
zTp7nJ>3hXLqwhYVvZttQ=;p1~|4;e;H-XRhdt0eD{~loJJ*k(ayFCsz2WpegrTId-
z4cjZOH7xQsWaP^x2sf?wYJAunb46I_<dtFB9&ooueHx#ZwkyP&Cp;~x*gyI8W%hDT
zXs!2{<!ioYW4+n$Yb?8;b+Q}HDK%$E@~M1}8<%Qlal*xr#)|ygt`$s<U38tTv&kMY
zRsxIFsQ$~of$zRAkPPa3*<{|xt8ee;-RH+ua9!T^UL@KOy=<L)$@ML2TYWcr^52rU
z4`1=)FY4c%-yg_*SihXEsRpJm*b_UyafR{O%$RSmHZzBO+g^hn|4dUXNAWEBVE=g~
zUvbc#+my~TeA(HN?+bra#{6J(@Pw0j=cBv4olzb-QDx1B1jFYF(pB!8Uie!^1~jI@
z$#f9!HWnv_k40M#RqTqktUi36rM%TI`Z*0_DSEg0jLw`;8+kv5dA9%ODeZ)p$58Tr
z)bzjE-UvSFrdJa0k~^ELYK{}7w<38arYyPEJ_g;hV#+DGwYi(-DG@C6l>T{V?;St)
zTY)CiQ>+nV@48LREs^Q-B)1uBcxl@t|M(K>_1NEay8jmUA+L<-aMh`Ozq8@@FAdsj
zx2GvtPQFlh8UCrhDF*IfdHf`7nc0As`n_+IiG32D^Huu(bz*xqf8hIx-+X$m!L#0-
zePAzB;idWVDd0_7gF4Y#-imGg7q?d=S*G#Odkn{A?LT=bAH3nL+!oCxuD;#o5+m1a
zjMv+o9S4u{xAWTjIr98V`gzFS=*IWw&exu+1@hS^7Id~}=Winanjjdx=l%WsmaE^r
zj5V}x`S16;jz>w{Mdz;eLM%AhPUm6stD<%I<*|2-Uh(vtXeYc3uH-gJccXR3XtCpi
zz5M7sJNx(~`*S7u7U|F1pT0`G1OK2Z9bo>!p6<iftUZ<S;rItlcYn*-chZga+*L+$
zB%LGLVT;BZue%d@sq&m5%ckf0?Wn%V!YBH)@^B`*ulu6Oo!Qonw0*1?&k2%cqBw<U
znM~JMk7PMYZ@lgcmS$&dKuhJ%?^!`Fw+CY;TGNgFzY6+DV{sAOr8AmQ>;c)9KS#d#
zXS(+i<AwM6JC~f#^d(1A>5@!(RcPPy#Qw>R&)oR(nzei{7wEf(#xJ;ak~jvIcXVvs
z>*kC0tva&c+Gp<eG3<2c%G5vR(i_*f`+zU0vpldViX}Gw8$5ci;>jMzmFz@BpYy+C
zKAULOI3ImO`p7wq7wBL#pQOzu&t-fba6Jf3j&PlVpC`M&CP41M+iVtfM}PR~oW;}y
zr~JlTnSL4{u1mCY-EsTINo|y?@(HRzY@4Z<^f`n>CcRU-Hufvt>-1RcbMP&0QVz-^
zp5GTZyC|PVZHT6`r+fOgc#dezvz@<4nRxA!wE0=eR`_Q4V~&5b#=HCXOou^r^aJmA
zYh=XXrt9wA%6eX#4c_b8QY@h!IvW|o+U8*EU&ovB--bTeO?Yho-lI*E2ks^h^w-7+
z_lTC(pStUxp68DtBb1M2oagyB4a!YKuc7+j4aoOy^uZW<hYJ}SYmDE&r@qJH*ujBI
zPmUkFlsMmGki`yi(u6kTjf02ulAa&wpO28IIg`pnd{-Jc<n`@{<{(P9c?-|lgJnF-
zC1fafJYPN^-jT0ZcB9RGoC~<Ne!#o<rFPe=UGe7^{9aJ#ZDUL2kz@JU#9Qr-Kha-%
z@UU%c^@j8Z+(cvbr@?*tQeah(>lW)RJe&UIU1g%R{nj4NjaIuQ_QM6#kMQ8VQFZCJ
zk{<GXivE8v`Y-I+J$)KE=vW=?^$I^r*&6NcFgs-bLa;q0f+ZN_*?tu6CSyMB<|^$K
zgpc2&!gE;kd)1U)BYlzj74{VukYD(aJGng<(~<rfFYZe4;x2fB&5L;)m3cy<%o8Ys
ze`{qz_)+(8emPO*mycsdGHg+5tjotWdG<7SvJK8(*4W3duF&@uI_bM^Y{%njGkvf0
z$Efw=oi*1V*?auL?XPe?nc086Gxu<NFV~G(`KVk!rZJfQa^`k?^J`-kJT&G6)8RM>
zFHTFqiqm2^2PUVtx_z3X^##^ljW;IS`Zm@2<8{pc-}|F664^u3k?>ITh;<}7&c+k>
zp?YdHSxL9y{kup;Y>kdKTgYg9hD_+>X2#RmwLQdd+J&A>etS2CtWF^ZEw7LD9Ku84
zfo!M^eQ&t+1hS#?ENNSP9xF0NI)042IWb1wd^{g&KJrgqwo@=Pu5Axk6F6LVk*{;W
z^(>tt*e~I168WyS&&}(W1<EWIdgFI-pVd5-@^|qrU1M@}e*%a5Jr1t|2g<1*2ivX<
z>0gTjl5WrO__^Bcby0pS?};=g?~|q@se7AX*6=le`=}6FToB}s@Gd)Rck!)+ZCK>q
zqb<>t@juJF+VH(7f$v2g-(Lv=tGnOTo$Yd;qHfvwHZi}8=w8v7xrf?__f?0EE~a0l
zYofLeB-%RQ+q##w+9$`?2=^8^^KAAnPn%8A#>s%zY3Btu(N5fl!wI;DJ>2~cuGv-m
z1Z$)2WF@B63D<^bs6IKr8-MJd-<Z>TELZCi@Yi|x=8p~WaZAW{a^EC+*l7LI!TqSL
zV><aZf5*l8qj7D1F7%L}A710;JNA6<w>fX#zL!LIF7S=T#ntfif4EWeZGCUGOgD&!
zJ!H@PuaUj|XMgTf)W$7|HtzX0b@2bMAtv^jv3KFG--M0SH=2xxg|n>9_x0P9k6>vV
z`e`O>(6vF^dY(VB<i-bnboagE=%o|Hq88{M_}|>GXLS0A=I1`|xv9KYCG!3{mG|95
z-oK~v9-YX$D3$jo#~p4jQ5ox_qwD8V<^DbaBMtu<iM*Gl>U}1W_nlN8K7sWaA7G&E
zBdK!O|ClDPNaejbk#}h-@BT#IwW++EZ~MAb+oe>wi+nl8*#M4n50B-}`fwo8)_f}O
z>O|g`Qh7%cd2dYRG4|qq|7$95I+6GGRNn6<^4{Igi|2gR)VJp8Z&k2IjpKYrrn8Hu
z@cr1gEBhn6qrQgGx_(*qg|R~VY#IH8tlRuScP@Q{-=A;za;@B?)`aZ*ijCCg`-0gH
z<8&A0>)e6G9+^OEr&fkFs;~w;a4~xXZX?h8QhXN1II;5iz0?yN=``R7hlhqvr|R9-
z+5_~B&y$ZVn9$Z@!uGv~{zuRpGLO6yowk*E%_8#}uIO7H&g$Y@lb<ks4h^A;Vl3nt
zy{Euo%6+St?9<5n1%q@FeJE?RDPq4u_UG}gv}H8W_ducvaMg~@6Po{L(I<Dwe-eF~
z$WIa3;UdNq??1A$jJ2jzIXV8YG2~U>RPj8~;(3#MURUJ#VeWaX%JW-%c|C{jc|73x
zHs&%LkO}IWUwDtpJ4N+(lJ{w!7xI3(hoNT=V_l19=04GXA?%!M;uq2Tnbqn1{9M#F
z&!2G5cAoKt?m4f$!neEUncm;!e=gwtK45HeZLh0SujBG3^gQ97A6DeKLAh<N+!|l5
zOk7AhOKVYKk-f<a%$Ec1i@aC4@ALPL+asklMl09y=~Y+X=8MTV*CF_^jq$t>o^UnV
z@T7#ktMQ+RDb8$f{{+Xh#%)deGv#Z|y79@s11vVg-C_+*&XK93PvPZ&E}Ww-dGdi6
zmwTAM0|!{(KY9wXTwpA7$(LlE6Mvq0y7V4tnR8~*A^Dw0M2BK-4{?#7EFHSWEBmHL
ze(fX0bIDf|+T$BGz}<8kxZ8KwRdki}{U)dD)76>Y{q}v?=!Oe&^1+N&^}gL0=x^xH
zcD8W{->dMQOJh-XN-?F;_K<I$&wxfJs53_$uB7g7=$|4}#It^qHsDM2P4ck~+O+t`
zMBR;<0lBz@GUWAb0Wwm}t(T26SpiRUIR7F*R`^aaIGWOXvY%?>1ox>2Xdj9}-#*ax
ziuPd&8g`&z85(ja?%pUc-r9^e&bYF+pNKu$@Aiv}m-$l8$pd(ipP$~!8vlM5<Ip+y
z(OUNQvpJiBZ=b|NJ0Bl@malj6VEeEoQyxb68DNx#z(}Mw1Y^v>IF+_dE+ZJ1PUn;D
z4d9W$&tRNzywmqro6da*y6nK@dBI3E{JFQ^7~z|&KV9tOrutoI3{S_H2aavr@8(N3
zZx?<={~s8Y>p{a3{B6VE0(N`p^z60A<EinU=0o!*sP`^|79Kz8J?l3#ovYKYN=nal
z9NkQIB_GI%eb)=V8t(&RyO=z;9r>ywU(g`>&R=vS7C3J4Tl#0~=cKVW(Duo=J-R2s
z!N)|vMLG!IGv4zu$NG+N)c#=Ix1X!M8T~lSu=HhirvUw1jDsS0a>c&D9c$J`Yb4P*
z4Y@y?b?XBac-mvko~QlI_b4Wy^XjSZ`&|JhX${i0uY2G67570~S?X3@+loJTdx^Cy
zo}+kEv@hmi6UhHA_g|aU%9_tWS(RJX_p}c1JZhNS!XxUGm)t&J+4*Q*Av#Am#dD$S
znA1?-=KPgJ{G8{rLhzOSgP*c1J3oGscp2+@JC?)L+QKoey!wb<)w6vIUUbjpD*ncz
z_Fnt>_~8f9?qg57dGvImPRY%IEQSYe$v&$8!q=VQGbC<Ug4cC;9l}GdD8{Y2EiRo?
zd7Irw_8zu-E`OxgBb~hfRsMtR?5CY$VzGw<55H0S0H)t@&+gn!7w0s$n|_Dpju~>6
z!9V#GkxtI_w#NQPc%mPRwtlIcPa9gULjQ-AD<|MJeL0_&gg3htzW1E%(>OK#(L{d~
zPP(&s);;`2TYvt{7p%W-4U&1IY^&<Yuc}bK>C3-5RbF~Yy0+r;KR1|fF{;meF`Ir(
zcvpmXjJ;_5#b+l!@+?~q*Vx5{ujXE_wf!M7&<0M#|EBgF*3YUJ{Ji|u@7Nq2y<%fY
zdMqA0?+WvLhYoHX(_yx@1dXEnXuO{~$5<$9{J6ZC>hd}p0%BX_$M9R&)gLqLP6575
zIKDg#93sC*Ya0#5cB|mm$C`fpa~BT{H|}~qRrR!nSz$diaB=bw8ZFaJ#vAF>!7=6Z
z&~h4apr6w*v@x^D+AKJw+fLJUp6@4w$FjEXgr9ycGVpKNDQuWxFy0r}_x<6w@Q<4G
zZ3<a!bLY}p1aqGFUtbm@(ODEX-yEMKXJ-JYyy$^$!?p!>b`s@AUtEmK<=F>j^TDRm
zoo3^j)Z;QA`Jx-+F)ldMg0s>4@ioeENmq8k+w}8CJr3w<wPUgethovOpMgCnUq$ZO
zd?xs^xAq+*`d++J-@4UcliiCWn*`6n06xAW_^e}3h{K({;OZN5+UF`An)z?svbUEu
zei(->_{|mBVCc%Y_UG3<%Z*3Z?+jg7O6lRI^Ji7Q(F5-SIMlr_H?=iqb7InGcRP93
zI?wF9;@iZ3{|fui^R`TN$uql9)PBst?{ns>>`zr6E5O>~<Y~R)U+@CC4>W%^n6fz$
zOv<h=JHA^PY}(K`VA?-y)31`77mE)X^Z4$@XZ#K0QT&~f&Qzql$y346U`J85lll9z
z$t!6en*1i_T9TtCWw<o1t;`=$rZQ;D(_<*|FSK7vvepgUx|n^FiQLHM+dRbQ**YlC
zN;6;Qfxwq7pj^7``7^u^v<i$#`4Z*fFtT9V+#fu<(jz6l)j1QNMLIlBKYOINoo|}P
z$=V9NO!+c4cBs?WgN)?@F!6(i%5wpEZZRg%f2ITfeQfRMpPp^|&kT<%9UdFY{=X_u
z{vCLxvm@Dy(Ses0aOBcHI2+d=KFgi03?3ViJ<aFMHYVz6+?yV{!@-X6-Q@Pc?)dD<
z$=qih4h9=rkc4f|S2_J*a8{D*bpI;I>0g}fzEA#l+T(my_U}k{O-BAq@X|)^2>9FD
z7&00?uPMUcs@o^t{R_X=%-z-i{`{5sS@tcCJY{39{KBOmY(m$R%`X=f!wRaSr*mE`
zZO;~#Y|pX1zs|$s9{ermrqzH^0Y(+x1kS&Y>JIe}GWwd7Iq@ub@{Zg=`ldd~_tAZ9
zFa7Fx8vj?vKlvj@=ihU59@=Ib9K(c8ZK5|Mzlu2mdt)nccKFyi7H4$ntot<+|7#eV
ziuXrv<SbRu6geAf+(-H|+_(R8MYqn-cm{lXw5Jz$`epmam$kS19R3}g!P|=C?IXoc
z<hJ{64~u&mM&rJ-&Auo5(HJ{hy3F>lM}9&q!}K{{2kt03nrGn};V1na)ywp=Gx(P~
zHSfNo!`7y8>)v-xe)evs1Csc4p|kYi{3b`Qfjnpe4t5@K8s4zJcK^iFhr8-5>+4O(
z{U7Fs`>mHEBcDJ<E=0%ZdaQhf#r(`tPz^5W#_}lt<M0_L#}Ckk<}mu+*JSX|oK3dp
z7f13~M?Ny_b85_N@Z)W${C*GI^5Av?yto>dFS+@`8?d81+dT7M#X~<2d~846?Cq2L
z?<V)BIX(^S2ma)T<9NdC2Kd!<|8<yEJfG*o_|MWc(|0cInXxmz`~Tt{edZ4Hkz5&#
z8SIlUud;q#*IyGa^zl(y#m{ChaqXDzK}<eMCys8ud}JS^cj*k-*V*WdhZcSbW0hDI
zc9wa^na9SiTHBf2e&#{9Hdvs%+M=B7JiZ)0nx|Lz-k6Ts18OvzNTiwWu9|Eo<?6IL
zW9ZKrLyYh4pQP5!xAyCI8DHIZr}8KJ`9uAkL-0Mh4p2gG)$n(wwANTZdx5yF^sRlT
zGKEjKsJW2ee+Ye)7k@W}eX?)9a?q^h_2|cLG&?v`!cV>$nV^n*@X+m@v;A3?HU$qu
z7YDO*6*|rjFyD^xV75hj|EX`^l-AJO=xVDgzJRaR6oi}B?Bf5gE3YBCESjwjc3qt7
zHcS`g%}?twzV>;%(9s&#vg`6cm(OY7{S@((E$)m8@fq9Xa8lh0eG5q|y63n*lxsAd
zY>?;XO1$43I2l~1y89yM+Sxfw<k=pisgvVR44`G*<r`emgkN2CdEQXueB!n8DF^o{
zMe__h@2=uxGHesiEAR}Db47h`)Imm}r*OA)$Ad^WYc3$Yk^AlK_8$SI8?W1%ztH~6
z_@0pVV_t7|yq2G=^(o`o#ea-n?rdM<V!wy*J&CmU)WCg+4x2(YJLse`I*F@0iT&Fl
z-Vt{M--B(=e3OlRH1n?o{0aHgCG`*4$bnyvbMQ|vexRS}%%^)<)SOMSNWSg$FD2~n
z_mMH`^Ic)SJ1ITSS*G`5KlY>ht4{WVU%t`NPUWi5j=N-f_5=RBcgd5bIXMu%8}9IY
zuMGP4dFst;9ut+P9qFHeIv&1!NW(4J=C6R~e&|9O{4DbQna*Fo$If)Nc|!LA;JzK)
zo6s_ed(+8Uj63h9o48BQEyJC59u)4<!QBkpU+!=pw6V^I-+6$s2VW$+lCQ=O;g`vT
zfB#kOjb*+yr#W6VknOZP1IF$xf3LcG9DjPtjTV2JK{hh&X@*Z?bg#JY(yYzh@Ll~O
zZ6|v?O#V4@Nb+}{=KAo&zBlbLK0=KT(&%fHrvAorN$}UZ<Vxot*msG%+gQ~-bn?yE
zFga(8`F}QwXBqxLo3WJgPt8^Z$n92OG-+!e&-?J}|KKc(gLZ#AvG47-kLO3e=l85U
z1Kd<z@`k+5e}eriQJt?7e*-^T?`G_%-25Elr|IJgPjqw^thml!CffPSL_3-@14}ko
zF!enDLVPUhmaj<QfZPq>@bXn~_{|4_!&_Fsfw2<z;j4*0d^OPr*5Mcv?hL4|$64dI
z0-w%2fUNan`%(PSzQaxO;VB8&Pf5VmoD?|7tcykRyyG8FI^L*_rg-FZNqXM=fZMQf
zQh(rM0>5bFU(f1)7qcJP0x!wdOmAtg#V7U!`yV2?+vM{iIkNTsl>XZ4`e?EyK2IP^
z*rjOf=-hhwZ8o<3n9h{{9`f(!kCIs{!#g_l4cpHOrotNeWo%8IG%oFjnD%~8lE<<;
zHm>1G1Nz!C^4p+~_WavU_9UaKFMDae-YNKEz%)M^7%pCu*aP|AL_V-&cLw%IzN();
z)Lv%jDB*7OPmZA$V;uZUXWbpix06YW9re&Jf#(hNq>}`LxV_^gGDWPwrHOaKH@b(p
z{9Gs=_0!}BsXdL~Ox~pN?%{*N;|O=dg}TxM7Ms;`#l^X#M@>gm(UU&S-t}AsH<bln
z`5<~W8|l+T<8Eto((tu3U#8{ol}u&gTS8Xq$V!N;a7AnRhHum1*-%>*?CF<;pR--_
zw>!Gb)}f=?6HXP;y8jKEr2)hEz}@tJ!Jm7l_o!cbreDSfl`jIz()>O2d`P6ld?<LI
zw<jEd!+k)<e%|TWVREMQxo0c3yAV7f7#+j^n`8}n40+$po|GH61kWsnw}19UPYgz`
zc*)wuv!2w-U2)Z^n@+=je5c*d{HGUfe|YeyFdyvhp3&2PFwWkdd)MCW>u!BZ_lDH_
z<*D~OQ}0_+?}t+FyHfARQ}0u$_gd<`lzMNc-V3SsX6n6?dhZRshlTrZockY3XA%E=
z*kUj`K#T3?&bjaQMW1yCP9Jzr=1G55kjW}C8Mqjk`MVc6e|M-HH>p#kPE~pk|N0~7
z*G1M+f>W#drpo34A3r;%*sQ_(T?fyt(P7gl-@S6pTAQOy1o_+%)=?x&Tyy9Q(=X^|
zy*DU_@0dNF(s)qT_Oxo8@GO|}%LJob41#1knd7rZzdRjmKh1Z6@v5=4jn9l34vk-u
z{`X^>a<L6a)LSjT3k>__`BnJ5ob}w`-hCCm-*-6=y2CjCjE@y@kJ4?;n{t`3jRxRS
zgny^k&0o-1*ZR_S{#B{}mzk~*egCJ2&0Wv-tpM~kI-frTens-(`Ai-28GL=ysnipl
z1;hO-ErUL7V1&p^3piZTdk4{RnuAIA>=*+F?i1)9+Z)OAK>X)x{Wv7^Rb+uU>`RF;
zR}yi^ZLS{!F%a#8ie&Isd^h6eilIdHEFS$>x6j(`{mAft3*g=Ycjzk`Yu~^@;Z55+
zwD*g<;XUV`(|8M4{k!a7&&Q0BO&b%ZdVH$xoS&GtjKyxCw!D9FE$#26{XA)0jYCV?
zk7n@#!M3?8utk6E-7wgnbFi&kF}SQ>zN52VOfI;?clio;O<I1-VrcGPd3sj<A?y$5
zKU}r8JUN3;g5A0a9<FEXuUB34#`=ca7ZLq~OS~BweGD;j=n~O+avOZO5c&vj*G_&K
zI!^Dh*fOy<7h_SZ?q=k|%2lyPR-TxhuQ$yeJl|gYKN;)q%bj0t&#!g5raac?^CQ*1
z_#-$mT;eVDQFPS;`exDnbL15XICpwD%%`G$=sO?x>~X8gM^4ng?233USiTVb75BGa
zeujQiM}4O5zR8hS5T8^z(X$@)+1~^Gmn5ni<)zvjb8QZ@x#22f@8{@4=9v5P&(@gJ
zI5S+c#u>Q&hsRlyaaLrURT*bo8{~t3w~=eykFMm3$JSZU8$CjMf#tLQr8TfP|6Z4G
z@uf}LTkYToKaJ6(erSB{?7iu<F1jv;wbQ{;nWSFJhw$tVmYCb(C$84UmowUcUU3_r
z&Thl@e?)D}J6pW5)nAKhtgx;lx<vgQsI%MQl1%Heo)Y7-AsZK45BeefeZ~rB`S#!+
zdQ<!OraSl;lWW%6ofuD;yDn(#=RQU{bHObE-{D;Jr}@UqW%KIJw~)?_=5z^InfWPM
zfe(AST)7u;jtaaIzcT%cDRAr{V`bXn(p*t{1QdgtMR(hOu4eDDGfM3F#x-t!j{MCO
z+&bKV{VVu2)*Zy)Bnx@Rrw!<g2KwYQ*}ur%JkinCd@Ie}R)J}@k@Z-OJIz0JhKS~^
zsuzzn+LzsqV^4M9w(VOZVhPOW^$!N}GigzS7G-ErhZbDy(Q*4u+X-4+k)Xw7f)>pT
zTF{QIH#a;jPGry`^!D+$94+kJ9noP0ct(ehdpdxlou!hb!La^i$jF9(^9Fj%<sYLs
zaE7muQAe^Q*@)_np0Bz?=9d}uB`-f}n^D~r+bqDx7JMwiM=s>h=HSBH_T_@R^R0-j
z-T_Z4{-5lm+rEaW-^tq=FzL}Z>6Tt0z2nNS#|}Cj!MF|oFaKSfAGg(%ztjew5PVwT
z!xiC!?Cy~)8Z6|%&YA+(k$2pfldmAW*2or?oga6KbnHI&tn<?B92@G(XP(6d#eLdK
zUDAcS_5;M}i;-VPzb6883^C=FzvJ`iJ&8l6Je255oxX(hg)52|&?g&rbFG}UeQFC_
ztFCRW$7p`RoZ79u@gB~}XYgxpy~NrZ&+*uOi;pY+^4Tt~Tw!c;*+0T5r!&N2n9wbG
zhK%Wy>m3ahpW?e1TNjGHSHh;cIY{X5b?Aw*Hr;}risLO+e6l&}(q0s=CeGsO`g{By
zx^jwTgqQo6Qr(v=`gS_*-tGAGGWWxN4#Yi<2Oc=v{l}92X7V8|;}!p1_R(|lJK%x&
zou_%*1q}Vib1sB8{@M70Y((#xlSoeNy`0OJZ};o;k59lLy#XBtaQrW4**RF&-lO_u
z`46#!4gIw5Gv<@pCr!Lh@~b=TX}~>(58v%yp0t@sgC??AL>8;aBA3RM<hd(ZILZ2%
zaOIkBuW*LcN_*sL30Zt8a7)aukQ41yo11j^apolY)-4`mPoZ3!daXp-Ke;r?g{@Nx
zj@FDz%w;HR={g63bbA+_m9BD6W_{0(O~#syu||cM*Q0$q;A6CZs-wNh{ohCJsSRic
zY-_g$-qjq>oIzc1@O5Uo?6I{AUliLuMQOWz8gk?JXXb-%_h~x&RPuYkU|)~bZTYrX
z191C37ifq7XzQEP0{x^cymD*b&pXFrn2Iqso;T&v&Sg&!IBn<LBTMJK{4w7TaEN`3
zBo3cW;_c6T+y@?Q@TziGo4V^g^zXXsz3$(2*L#b5$+d6w^q$81^9j5^@A3Xn3U9sF
zT#VFWBsFj-Ild|OB)x3&sxooXBK_-;Ur`!&<+ZsY{@39D)vSS3;CDHtry1{~|0cUz
zcfMk#%^B3uYP->MZOuL#TnfNvABoKim0lFDIj3@wn2+y!ESr=y9E+as!jU@BUa4+T
z^pdO{b>}_mT`-M~gLJj;TFINe*yAvcj4we8tAD`$SFU)o)fb$K>ih3=1e3Onmj2oB
z*s|p8m(n~gI~BW1yeDy!ep5`!x9QGcX*&8uKC8j0u>NUl0DT#D-?h5;m_C%Vwme<*
zJbx{5oQTIMx><hB#d%`iDUcrXF&5Kpycf}H@LKlOzI9SNp0-94+7W$BW_0J$_dSAd
zIx`8go$^DP-ew%|=lWlkkVnA^k%uPoun#)gyW>T-uJL$)bx`&b6djFit(`UpV(<9s
zrkhUb>!#s)yx&)~)etOQRp;A8&l)?dD@@v&f^ToO<7F}cU*%Wr`<VEwf^0er85;%K
zuF$Toz{zmjR>k`T%A=h)opxh+^f*ZGWb!q|gYFLEtjr5VPp<q7_0>M-k5#4fY;Ew}
zXYba$WgrdzU|AaWQfVeD_%i<=b#EUhSykP8pXzRyhCyruwH1;+GlM!JI;{|$2uW4Y
zJQv@>=p_+#q>r&<#xQ2uWRg@2rV1q)yqGv9B*BR3;>BxuW27fRCB9VwJ`sJ$rAJAe
z_`y^uL@N<9b0aFb0(HN?wbwp%s-}7v-=5F&{Bb^KzplOZT5GSp_S*aGlkQEzIg%Fm
z@&tR8efs~)=V{Vxp4MCPsdrm%-;*rNzxi6f7W%&9@j5pY&YCpeI5%DT&okH7Ma#%t
z#ys7C<~&+s2A%8nL_geFG;~jLG3^DM3F5xreb)BiEVs_3=?*3F!p1^NxUrU*p8%Jx
z^=CDe->`3YFfX3(=NN7&=<!=zk53lTCg%qB3b+>SlynYVb%%8Es`*iDPAt<d&m;aH
z>V`1B;{J8SU%2k4Z#sJy`?w$4+Ic6z?zr4_2)B_*(wcfJo_f6E@w&&Au6(7de8c0J
z&84J4r^egY=Ghi_whGU-!84xtowUA<HvL<v+Z`P?PCZR>Yxk4&DN}bFMmPv3y(_La
z;1_no)izcuey4B6?yJU!de7AEtAb9kz6zGr`*P4hvNvim&HSABE&0E)><lYQTX{Zp
zNNb7)O3QdFu6Hfih*k%h2zT4_{(3<UzRp}u`r^MaCR86h9>t@(6|)!me0;p-5%SvJ
zMjd(NvAKVNbnZr!owp<%YT<D2iRr~BGY;>mlq~!UJ|_F29i5ZW**2Za+<i^JTkV^@
z_5sIdOq;Vy;HSGoBTfzve302d53|`~dhitwXt-8A(oN=+Um4(IFqLO%PE*DEl;dei
zHi*ah$!L5@fyS2v8drZK_%jxtjjyB}=6=~jHs|q<a%|(gOk8OheAAmpb6&p2Ab)6m
z*(t0q32S}1@glyj`M=>Eaq%lZmqgt9+2`G&{d>KPXieN`r#HNCKl^}o9p!sD%ZJ{i
z89e2sWAZ$$StGy26Z^#Y*H~NB{OYo5v^%vxyHlYZb*f*7c7m_A%hDsxYtqzqP8acl
zz8<#rQhHIx2q)5vr+R0|Q-rU$wG;4*Wvp$%0e+z8)Row#SL|;4ztg|%^6h1sg13wQ
zX}+;AI&MC+tNobfGWmLh3;FmcZQZr;3O{>D-u@))32lFo&Wv^~KTq>HBc_`!rOv4C
zm91_vHK+Cpa|iJiwM`xSM`XwQE&MC2?>qf~m*L0#l68C=I$OFxK4r|ma4^{DT30M}
z=_l_eEU;cg{%oDrMz%-`>$^4V_!@e+jt=HwUf-iJHS~>GU3$ptCMvhacX7y2lX+cZ
zag+vetUjiJ9dj>u(uSR{<*o9fsm-y>PexDDjGnv&OKIFGWqWvM)I(hL;+bRF38Jy=
z7p?70{`?=QHm>`US;k5Wx>cY#Z<8mbOJ^y)&3eiDTBpBb{FHY>r+Mb9RcOG&Js$SG
zrFfw+W%m=tF!GZBTRo;BFZut~W7_M3-C<)>X^jFLg-78iZ4{2uA{_M#IB7TjORVr;
zh|zT5n9WlTb=WuX|BnsV8A|s$y4O+d+?p^x_y!@K#hb0e-`|A4%1c9@{U?hx;A;87
zJ-P=HKYfDjYI~^I_wZ_k{|dW3_%8f0Z<w(2(;AbD9|aa~`Ib!X7f5@hr|lh#VfpE7
zELTeQ&&tKmD$ZQ7^a1<6bJKxv&r5a&<Dr0?-2tgH!M`2$^W%RkSAnB@D`hV(YHil%
z9!t^`moG+f(;GG9$M0bs@am-SpJZqi`0er68@;EhjR0?dy)>=6Fs+R&qz$cY_@7IZ
zN400)W2oJ1K#N<TL6QE)B+&mN@LS*vi1%6HbQ?0FGw%!Ni>KZnzIi==I8Ezp^Vj0T
zwfA0scm3V)ciZ1SR&w3XcqrPj`PyXEZ(#a{afB|>zE$sM*hf4coO#<CfH&he{Od#i
zySVI_^;#d7PJox6WPfX({*$IMcD|nSc0Pl5q}SN-+hY7y7`r@L@Am%5c}_nAKhZ(x
zk!mIILjDj-ho()@ok#x-9IFdQzYBpD`W9QVrn-551ZNxiXHN1X`hPk24^~Ul>SOGa
z*$%%VIv3UeHR|xlk2+M2yU3NUd)KrkG}wBR)=WKK@p!}IZIA0cCtN&U;oT3o%_k>K
zS8s<e%5M+;O%vA?%@*l3<xz)lZl@`(biq=(^e%DJyK|&>gZ%DWevt2BO3BJHY5gFh
zoGTSfbV4{AF>%lRrFiF;&3Euke%GP?&j&sQ8Rv}5tNGs9;hD_$gUrV|IsZoGvhYn8
zcQ>75-*s()k9TtZ;sW+jwhVCBn0g%itG=ghV@><p+F#Wi)cf_HnBM-lWcsK7zA}?O
zy)rYwlfHWJo_kM->wWTHg|PCA&y&g1V{Ouocme*?$#3YMhwik}o3}$>;pA_-U;6^S
z^MIbQueXVwD$98l&KcIzKYGqJ=v$L3%FIsw-MOXaTtPkw%XZk%z;?Z*PC52*E~_U!
z=un!!%gRa~@-i2zjE_TPe&P>>Ul_Yq_vfe!PI>v?3~{r+4uU&Rp7&MHtCXgvMB9kR
z?;oN4SCY5jduR_JtAbe%b!Fq*9WI{MEc^QFm)>B$Z`)_<P#)bVU*w{6u;K~wsW(sc
zU_l2f4o({%fHvpS?i^*Pr!l905Dm56qHXkKOtZ0~@-52yxX^x@c(Z?odn?_xiM-uM
zTF5I+KNWn6>4vx0+vw+-iutM+$HHVq_d3DDY4E+XK<jzpqdY~g^zIDfYtsSx*rv<{
z)LD&qhWYQA;3GQdTtT)#AJwl4G;3jJZYFNH4azQ3c9UrK9rA#uvc}(b*uOAYd%Wkh
zfpd^Ddg=kD@a|QT&4MePSsV+y+sS6_i)^R@|Lef8vIBYz%KN#a-$ved0f$F=H1^l@
z?LE|2p7fXC$Pb`*Mes)a0G3WU%A1aLx><ekxJw@NFgyAyv?ChTnVS#!w|P+pXK1rS
zUYrwDM*nYDT2hch)}Gnbg?~<vpB?hL7nY`<MOp2ESv~ILSZoZ!vKMUsHs%-Meh0WC
z^SQ}=Zv@X(Z)+{snYUMjediiu=fh6t4s^<boJ$`piXU6(x9Bgru6kY?c&`5Cx@H$T
zeHUw?+CX<@r#M_-+1lbpV9oK=ogNkjCh2DDFHyebJQDu2DOwpXVwr}@Fec*nf1Yk<
z*Tm;kKG>-LSgSOGJ*Io}NT0U#S^-DRgF5T0x6ZoT*u081E+~x68$x`nj?|f?(Qykr
z8$&(v4*Iu{z_UASEA)4PK0*`QgPRjQNTZzTt&}=SQ#nsFoJi028|&N~*DEDyzyHgW
z`);q!+2@4$vF+=?GImuPdoJ2m%(qSKd9x#+hn;T_Z|Sq$wN;P%mYO@ptg{w?*8pCM
zt;S<}6Ra!I-=b--3klmff|`7cHx2e-X(#eSXP`}2_UUUjNEcqOUY|~<smAq~_Aj9Q
z722PteV!(=*1VDSx6tM;=vwx>jay+pvAd1wo7sys=3CNjE+Ngvu--gFcN@oY?ZVy0
zXNtGb4S7p`_AWa^WPXtwsk?%{g+Jh2mrW?yGT%J=?cil?YVD}+k5#VO2cHV?ZVcg#
z71qUq4R4Y=&mP>#(||86>a+*<U}on_E+d@-KBWhsaff!w!QT*REL~x`1{mhw$@~sx
zWJYo{mcGl-H-o+n=*z=Ao!`Be)3#QiZQp6zH`_4KmNcWS-aJFJjpd58rBC8Plmq)d
zyF=e<*eo~Dx7NUBGX9A!l(+f%X!>-JKF!dlE`8#OXWZ~H?GcTBWc@mkek})Dn5|2H
zOm@KCWJi5K&TY>2K5b|ecztZ3%l?@#U$d<d?)9hMt<|8*;@aNy2kDzCh5E-2WF?y(
zfdx$4H>1wRt)Who8ylN%3FXth8i&a9d&50Nhqc>wUSz=gnx9EiI30{>gLf1AQRzf|
zV<oBEo=HpmLpHjDa^mTbtWO0TdN(uImgSq^teRx}H(7VkuKCTM;eJK(o79hbXYv_0
z**e<h-4^L>bm%hgB)1p%{{nM|_6=Gi;|4fK)IoE|Qx|#4kSCrvMw$!AQ~5_IPd^Sl
z7Q(oQax^3xrw3l-X?6I}2x*&cF382}hGjwWXY)J#4r36T^rORNWY^iZwUjZNxc`mt
zEr-@Sq?t|3TXVG8l+y3M_7zOial*ahI<6&N!GFhZi0_vU<Tmni;&*QfYb)9a`!}Jj
z>Vc6yYmA_eh0_onWM7dM=@7@msC*CA0dLi@K5fBXLT8)r#q?)Atn2CTI^;8+D>K^E
z#?WSrj1AH1NIJQLyrsxn8+qfAA6RoZdT|eSL>)S!E1@mvlZ$6Vr!n*95nya;A0>=k
z;IS7xX264|s7HU~_iTSQ$fN1axrf%xrqF!bFrSNhG@UBQ`^JGht)+v+=O}|idhi3G
zUGv{`(IJwD3U+9l2fAy%*F0rsk;~-qRIhfqX}Eoby&iRs*;w6RV~y$^vlCfIXj}-s
z+Y{y&G(EKpjw$_0SktygWN}o!z$1=*TL*tX^JF>9{nBgAWxIFtM>kh~Zonha*!bMh
zKL_FSlF^Sd>8|^Je0P4|+~Rhpbt|k_hIqHrdG`P?4q>CQN270(Y(1_v9&mmtAD*l!
z1E&LL0hy~)PC8*3{=fs11?pZWe$0k4c9wTc8SRDGnh-cofVbv1GdP-$x;ZSr+tvP6
zH`Ev7cUa4;X}gWuIsb3+kGsKyZ?N6Q^KEjnz&HNwWb_-yw+jpO7Vm4&TRchw?bB%=
z0|y5D4SOA7j<@l#xxkN=0*rQm(M*zQ-Rlxzhdr@E{WSDPK5VmJ8lh~MA0L4aqk3|b
z56FPl0Hd~oaEbHJGm#PP7v%HfOhKPXM^HB6BATZQ*x$>fg>T>FqsVpB#Gf6d4ULRR
z&cj}x&LfSPN478rtTG2|V-DcqY-4`MQu849=Xcn<p92r@6Rg~}ZmqFqAl=queah2c
zqYL4~)(k3FTr=DYuA~joVD7;^?8};e%IPo#O+*Lw5Lruz4rSWu0BaRF;B9tcn>*=g
z+x<wh__KmtNIo(>9nM+0AA$P$nyMUhj>(5;HwU~Ldz~kLf3#bZUbP>>`t{!i^b*|;
z-<#s!uG^B?b?7O4inI0|?ld%lr}WG2qq6;}_wauP=F^FHf85rbcK#E117BY7gEu<?
zXFF3){?Pvow3Zg1=J2;P@TV!iT9EIv$>$DS*_&oJwkP(8C$={3(-x2EVd}*>+jvk7
z|8_R{>kNEPBQh~7nb2K1CKI1=nE<BjR<oh(T<uZtn>J(@tjX_pFjkfrD=Ul@p13F7
z+{Ju)BV(l>#!7LFh!$gY0O@H_2mIZU`Dyd!3}<QTd>fl2r}Evb{3Gmn(Qn4d<SXFg
z3t5wW__FYQHt@|Cr+?FUSZBd)yp-8r-4@oMixcD*;u`06AMq~gBl~>+5%!aoNw0t-
z=}p3>n>q!aEW>~KKcc=m==w_IR6JQItoaG+dl!w5V=qD{N{16Zwc`4*PrlMxK_6tA
z7YN(kYnl5zdZaBQH@8!cx8zTJlbo6!;Jz~L4>b=G=Nn+9S-$$!_qg)=$_LJE1^+2&
zV|C^K$9yT1Z`%EX`%)H=>7xIy%wBD|pyz9A=y}qQO3$lYQP0Z{Oj=RTn_uWwWTaJ)
z5yBe3rU&YpyBp*ETch~bn7>*h{!8NWGsN#5q8(;>hc?UyE8C%kT=c=Mg5AJ7tO+DX
zD~y4`{e8+CD<7k{jM9=mrR?=+j78f@XTb9RwQU0j$tLBhY0#ruQ`(qpC=Z;9b1G}t
zye|fG%=|uTLw2Cg0`!s2Tow;)?1lM&yopy_W&YhPr9H}NeXsA=nrfRzdr?NOUkmuG
zf{)HrY)y`tPI)v&7c1IZ$LDYz`si{$vkZRXdtM)(fXP8Z`_ML?i`Mr+t6Ps*AOG25
z`#q}LVQy{&8+{*oQ2HX;+1Kt3>7t$Sj`FOn&CbL}IN;@S;N{R7uLW!#tv%bXpk4iI
za|d;vpzoH3*MXY9GLyx+;V!*?2K|qC1fL1?da-;P^dFv;?$LMLUBjg@74RG@I~~Sh
z(I-ILl4H?mL&99z^*&bCSgZB}f4*1Po5sM7d)9gX9d?*cnFlTkyptc#_A9|ra|QRu
z2HRfYtsYLbry9b>%a*=bVjg49R&+n94vY%)CM?=+tm~V${<>?cL59Zmrv<Gl%)@o&
zVIKKUY-|YD&cN?D=h|M~+e2FKK=36Q|EXhsN8}^_?zQNL{MEtv-KKm}ea5bx;lUpI
z2hQ|Rf8uew!x`l^a8qxCux!kUuU#7QSm)$<gq5ee@MW*$GXJDgO1bQ{f%7h85BT;S
zFmIKQayOP9%g`f(9u4ThV}2ZL5j$V1e?iuuZ3fRe=oZ3{yk8Q=srfJ7uX^w|4Swy#
z^BDuFr)>@Wnfx}sS(PEKHmY+E&E{op9w|dSmQkHiyVdL*#+mZ$?3(0Wuq#3CbJ^_p
z*zD6c`8HLi4z2$!)Q$W%U#NTv<j1smVA(nh7?ba0-T{W`wikzTX8TS7>+-|v*;=6p
zOaIhc4CPkQ2Sr_I|AgWUmDwRJ@N~Kj`6vsp4A;%T(m5>3@8mAmY})&V?8QCjA-zL=
z=^fKI7iylYAN~z6WsElP?x^WncA7M(Ls&G*+77=S-bI?)IIFuKjP}OiXmbg=QM4W_
z$7_u14Hega)H_TLe4LDhcLbdpWkGo7dk;VEW4<Q*IcHrw??GD7@5p8SN2ibTaaO_h
zVIMfV8U7nSLAIVL8Q1tAO|)1gE}5I>ZFY1m$h7QdodYqxxnG2{#6Q?PQby0T(K8kF
z3{R7`hHy&)4t57dA9=Zb7<Y|3;gxcJq=?ssF?i+UoHooC3%oVu<^u3q0k3)R;)&n3
zG;d^Gwk52~<j3H=W1@A4oqGV+xE9hG0n>F8^>Bs=JR@CAuDj4%>xkQ>%epommauW`
z9LycmVQnk=8(&l|<qQRn`2-aog-3hBCFpeS(^_`jKv~__W%Gyj=ZLQo7k^Do53(QU
zX=fyk3-J~Gdycp5KV*(;M*ljbkuF<1TZR{equdKW<HZa#p<MQk;e6>L^V14$Wk3(>
zXB!?)dA(0lZx{0gX&c2?!TKH2po!5=Ws}S7zc|@fLK`_91zU3}>$V->XnoN6x<YzR
zqgLok5tj(x?DjI>zVbbobk+2mF0+5lONY)Ve3iqdtrHZ#A;fc9NQY06CO)FW?XDtl
z7|N#~G2iBZ1?JJeWsFt4&#wr5TZI=xdILC-Kasa~W|H*Wo_OQ^rR?DcZH>F*P1rw2
z(>8ZV=WT!T2W<OT+J<h;xj^I5IoW(iJ^DY#cM(Yv_IqoT<uSfr<TN-IJe1yMuAcLC
z6K6Rj&$iz|za-C_nOkifIc;=qL^jzdY~2lpz6s})WJ7}AcAanC0<Maev1creb$pq2
z39F9Hw>K&t?47utGdr^u<}%G)RoR8W(wZvXbFt$S>~qHXZ5bXnC<C4v)0@*En`XyG
z`L3Wl+F>l?+k$uC+(iymhjC-Hke>#7PyhBbT}Ipa+RI?$)9C1Xi`Q5^!Iv)yU#$6*
z7x#h#brv&x6q(P#4S%=&9dQQUQOjT-nBXs4Q$A6(F?Jq(B>ma~Pw%gEne>6d<=sqx
zA8EzE6vXF^QHE$=I$eCRGl6fYo8FM_iL$t{?Q@pkwhMAqq-Tpf9{Z2e7Q(7u3$Vq5
zxc)L<R-bgz@_fOp<?BMutN9rM)i27D;8M=y4tnMHQFwc1;|m9)CvUzdP~V2=OMdpr
zda%*bFlN&$grA?sI0)~EAExg~JA*#uW9Et=hdN7Jm2FGC!*oAwDcyAc8PJt*uFs_7
zURJkyG0pV7<V>)jPn`dT^u6$Z3$V6O27DIp9)_XwEM|ka9@YF}I!g64PXc=t+z-=_
z-k(T|TtCu3TQ5mJ{yjQMxJ|>mK5rhiWoJhId9YTq^X?t;muai+Hj{AG-2|#f-;bq#
zcJGeIk;wq(cY$+{f4{lGVbT}T#{Rv#3x0}5ss{{g6du3(=xM$WNtqxcl*t0Fb~k}=
z-v-}eUFk8>no1Mg72xtVABJ?B%6WZD2M6)eXwXLvr`dm;L55rwqiiUBluqJ<!Rtsj
zp<B=^oN-x~{kH1Uj%WgW+cWj}I>jS>zwETwLRsNa;|=bzkvDzE?*NruM4H*iyn7cx
zvw6q&B5*28cWWPoa@4nd0xLJj%g1Dew1qL{`@k*a<>lL69)IppkL83q;4w6xjKGh$
zR^_*ea?o&EW`Vb&W%gpHW0$l}pv{`RJ{o>iy$$D=`CE$ZFNAr`=D7vN*7@GP=%7BG
zgly3ln>%?M&6F;gQ@Us<+DrCgI&qW5$UDvV-ez^0aO737y!h(n%@0Ia`eZX>G|Hpo
z!S-d#1)R&Y4IVbPZXt|JVNaX=v-m~yW^7k>8s%)CSnY@&lKZ{%cX=?r%??Zhj`1vh
zY3B*0Vww30@_2>!qfU6q%U6cymwesfb9Hv4c^18ORJyDsp4_Liz{B^hj;^PW4V?oL
zPgoy>aYoqsR}n4T=R{hrlllWYQr{nlUYp{2im>#Q=FPlcz>p0R?dq|3jjo$ptn*s5
zgFbEoGt=C~JM9MjY-b6HuM!`cyFBfT#N~nbN*9>{-sFb+4cArTLo|$Kct`l*8zcN+
z_}$W(a3<Gi@y2lXpXtdOeQn_@jo;xB4zl3?p3!%Bq}d#v74GsF<;gDAlEpJo3-Dwa
ze>r=m%|3R{GXG-ZA41g^!VkiaQTXx@J_$P8zsi(eA^fi)eX36Q7d@=>TSM5+13Z<r
zStrP|{Xg;CkZ1pOmQ1U?lsY>pr!|`5*w1z+fWn${?<eo&p4ZqgUHz=XQ23CyRVS>y
zK<b>Vu=E(=P5m!TKQ<{%S6>B;`yEC~{<nz#Wr(lSw`u<n%FomZcSHDC!GAD>k5PCd
zbxw8|D))0CZz?&?&e>#dC2tNMKo8Ro3&;cd!P3BCQE*A?rKEw|_D8*jGo9!q;@KOh
zYkA1?GWOaDuf<+|t(CX@-w5qKF#(TufTQ(QRtfba3$`BMt{LWR9{jMs#JSV|47R7q
z_1^~kxa-{D?qhssPYCr*uR-gGx9PRF#XRQ0hYIr`cv}8D13clgp~W5HeZ~%poYDS{
zg?;fO!2UUd6V6aAqZfYq(y(vy>@jVAwa{i3X^fsuP9D(jO`$!}ev_RAEzn+P4d~P8
zy3lL}^{v7BPksAqhXH?^HH|f%y@Xr5c|?cYH*{XWX^1wQIU1r3byiowGs+9`l~s6h
z2jwgeTx$io$Nakj9*>Cc<)NJ9(bkV;$G5|qX9(XNlvR2KIW6{in)Er+6PFFjtY}{4
zZMY|w1({L0a7TA;JmB=Ihqaq@=~z8{Bf4lCeyzRuwRoEFxjBa}VsG7a5p$x}8<MT;
zzPjPDPV)aocsz&iqfU5t2%8Skf2T-)Oj??*YAz%^MSrRnd%D8i5H{WPTVAG4`X4g3
z4}>;m+Qet;)7iSvchf<C>M*2_9ERz$zjGMUS^o_f+X9SZh3APO?<9r)r<W^H?pG*>
zo5Ao)$=m0!6_#BB-pAAl|4Rs)K8tNC{fv-)titaC)<+!A3h{podD9Ae`^PG*a`I&X
zdtFL=b0{~{AndS@Rr-H~^kWo$A$2bCI?|D`uhM-#@8wkgrIb61a?67?n9bjUOPb`*
zzKfLHz*9T#_B{Xo?8I+`Z=_=SPXR~a8ue5+#n<Tjini_`E$l<|*^}j1Esw^beSh?!
zfP?ARIb=?E_q*M0ZNAs@cepIaHviMpmqyax<>|MNq<_ZK8M{O9`Ei`#ylo`?%bt$D
z9x8uXNDt$9l6wy(XVZ24ux>&}XMf@KvH{%$U+bhy`jPM>>VU^N40sUrRPmh5kPi4L
zWy{bP{B3_a(ntD{w)VRpc15^x7RS<<L&PsjlYXS!ZF{Nz;F$hg=XGX+9cAB#q{s;M
zZ7)o4&!vpDOCPVX@E-kJP-lQ9F7Y`)`jK`_Hjqp6O%!2BKSmg*gtCuFC(dFSOwp+W
zY(4a&xxkxeh)%Z$_)5#?y(Q8pC!HAgD-Oe}5$ZJ)`o_F1Jt;eNP5szHKUUC>b@U?-
zI&qK6Zrq7YFPR{m+koWhE`~MlNmv8c{u%C}M8D=^1(=%K1>5Fr=wUKjNRRt_vRl_|
zZ`Ag$fqM;F9)PC668uGUkogzL8~R4(rC~kJ8lfJ)6G)yM?CH_|8V%r+**p4HpElH|
zp>Lo`vp!i~;Tz~ey2h017W-!LZGw%BEgWTItBj4~LE4%$I0DUw=Joyv&6kc$bL(@&
z!TD}!5m!(9-tj8PuIK??CIgJIQ5i6~DIY;@=6}R}=rA@?#zvd5!NYkATf>F#y$ZUg
z#dow->7&8DGUh)Z{g#pRrzEB6g|E-h*K4OPUf-DB@x{sM{Cp3z5Iq*380exgJaoo^
zb3L-zZrK~gj-A;duDK|DSC73(eQ>t3AgeycY<)mE(Yd&eG<jA1N`PlR4dSZ~e?{-h
z*+&=5Rl-vqzFlj-6?6(Z6Pm<vW9Nhfui^0gz1I3!>#F?B#y0w@^Fqj#`S)wU;j#Tc
zV74_s_qjjG-?|fCvM1dZWH9&;HO7Z%#<>u|wDTYB(K-$4uH{p3o>N!;1m?A%Tl)A<
z4uA_d+1?&FiTCm~MEPx01FpTTylc=-Z_3%anQ*oe^s(fqSns-6?`E&3cdSP^A8Uzp
zwSUXJfQ&YX^TcoNG{2e-q-|?oFgnOpJIIyJ9BFPa*jwYAjc<v1i~9dwEBKjouZ*3E
zIGwUB`T?BmBYvkW@XTLDy7iO1cwR~L;LKs5M-86QuWVa@(epmVb55c`v8>Smn9ZBP
zRj^fF@vZ(o5cYkIZ$&z+sRy;^G~kWNe7~Sy;qUi1rvaDo6nUP*JzD)(gKu^5aWLn~
z_p`Y&fGI!ESe~!ZSF2wit}h<vdn1J9D;k{_hT0kR<&?p*jSj4UE064h=wFMzD)S36
zepjxYTAyA!b*1^5YTj0H-X~3MNhb5U;A?V8TAW|=K9Azk8PUhZvDpti)m$F^66T*&
zIy})glX-f@&tJ|2eIOd;`^fmmqE69%+F1Qy^dF%IFl>C+L;uk4(<dhDb>BbhhvOJ)
z=#6%1mhm27CgOeZUgJ?447qe)B=b+u18rc_j@BVZO`{t8qVF0*x@Rl?b1~l+0iNiT
zp&JF;_I~vCaFu_f=Xu${u2OyFQ4ZL^r=8?|_m}M7t+`GfqgzLLSj6v?HSp^m89&KW
zFA4fVbB)ctq}f`IewdA{{-D>icVqog9mO-R7yH(tUS_%nJNSF(*Br9hg@+k@<%zl&
z+kQ`);;R6z(S8B=ee@`@XEd&a_H7@6GL{x`p`6`YT_(Nm<67Z_u+Dox7t{51U=-4&
zlY$I)O>b+@Hvb>!SCZjx&S^t!YMqgnxzurMGj2Nlb*o8o^-7Xlv7a}~&ns5z#OuU)
z@8i8%AzmTQdmr!BHt{y`_T=ooHn;)bzR^@)4bPC4^NKX%mGad08gCwbkCgMOJ4ly|
zn(V2Z##PsOs``p&4j)*iTlx-H?}c0*g5R$^klTE0eh+#l`zo}m0k;B9Df~d5ZC{(T
z>{!oZo-jY3{6#8D+<ZeTgLuB5>iJp^*uLx=3;U^`@jb*AeRwf-`vpCUZ)ou*(#SJ=
zPH?~}+M&8@L$+G4J#o3c)8z8)C-1##`^nr#`hezq%8OT4e=vr6@G<t!_i6`syY{J*
zP^Z`yX~s)~Gm=M|*_cHd^<37D0LR9!;MD?eO(tk3#?`*Ym*D}=o5a<RxZbM%>k<BS
zVY+-+_u4q^4`^$9M|*vr{PlqcStH^tTCq;+BS))Y@5p3fE}UJ^Sk)bTVQkgM&nL_1
zjtm?c=nkH!I}DF9eNmslNBqupSvT}EyN~a?YV4nWAm9_vl50Gh{5-*BrUpG6hUs|X
zcK?vlDq)=Oz8yKRIDG3c9~bvJl`i>EdU0>GOuBd%%M%y>?c5@|Bfty#s!5r{#=qL|
zI-;SCofhSI3}5Q(_+xyt^Yo8$)>fZ4I2(SXnY@jwOSydfQ+|=VqlAy`kx*|)S4g(H
z1wG=j_I>lMLtk#bF#jfdsmtE1+RUI;OSIK}#Nm#wQvE{y2co>dXYn(}O_pXD*W^o{
zquiN{_Xl;XU+_HAJO1yWc-A8RGik9xxmtiHn%lW0wJ$!lobSX%*CY0SbS`h<Kl`(=
zMvZ+jyv}#Lpl=wL;e8k{X?uv5HE`l-_IdMEFL;D;^mDb}Y3_ULcbm_we>df6{`;kS
zn!ozHdzv47^Pc82YJ0F<*QIwe7u_~;C()0;`LML!zrWe`)>GxZ1s~DB|E}4Ob_VZP
z$%7Z3H*NW}Bm2_wKUm2B8SX4l{SOxMbvFGOZ)O~E=1zU2jp{r!dJpeyycc+j=agA`
z0J-6<b)tNJYGd+*UP*VW5w>s3ZEZ!Fb>wT@+u3*E?p_J@=E}AFQxCgbd(7$G{dK|{
z*|Yt-(sNJ9&+aek-yFH^=HGfk_Z>Z8{=3sd^rJtf^Puk#Jwl%K*YbbW^FQeHP`=Z{
z@;~VLv@zDs9^FS?#+IGaT0ES+5kIq!2fb(Wt7rx+n_E3BI%-~Tw$OLz><uwoL2m*_
zcC_l8{uXrLvY&hG1bMTxIZs<a4r{ar-DML=F2xhwEh;`r&&M@J>BJLCc5Y{_atmQC
zQu+hti*kU|<Q-v}Omv6?)7F=?wd22Vw|3vl@>X~~`PE5uT6qonEikV%m{(Hf6(0J_
zon+7tx@jEd-`LiG2MnVja;>n@P<!%(7ujpiZ5h^5(y2z%J~VwL^r!{jlKG^uZHDsY
z!zVxZ%m)6kp)!9I%IMtQ=E|VYE806gFXZLtoq?5~cb)}5#qmek8-L}Z=CA@jb|!Dt
z%K<x{XR|YTjgT(CnBks|;Qp!5c3c}yyp*+}eE4efB4|Hae|n_;?Orw`J>o#PcsGvp
z<hly5iZqpNK^wsj&ACR}jdD76oXm}^JtChw>~SvejdKfplQ6gB|21kuvvNqUvObVJ
z$u2b;R^eEF8eBTaKnktAjGZCMs876EqpZ@syxG_EMQ_={^5tos6%N%s5216`uz_0i
zp)zcT#rB5$<!a0Qn!-2w>d}R><~twFcOQ1lU$gzuxeVO3ZZ;irFEnTcTjsDaU*lUX
z?!U}LC)!rN$_|&)e24Ar`K~jj!dy2zrrD#iIa2i8`33$b(+afR)Mxw?R-L$ZR2xlT
z#xkPw&cA$UHr#_aX6;>u#%*X^K_BqYx7?Sb_D(^5Z62zHHa8}+{jrM@{!7Aps86(I
zxG-OY_SWF5wMlzz+AGqO1?3TGitmy3?4OL0Zin^tJCdhHu&EQ;i2jsE=%?tkyDL30
zo~IdegZhMDGQh5noH;wfnF8D2TR{epO&c3?jGdokJS+#Ast<Pdj<?x@<Vy#H^*nRE
z(j#BNQ}wF)h7CGL9bkLi%X}kzw~yPp%Rz+6dw(U`3tyhqetc}B*&@udbQNup9?OXr
zJ2v~jfNm@NPvbWK7tkjDt5GPgHGsa2Y?8j|2Iki<>l?i~d!oUfG{5mrh{yO)NHZJP
z>#HsO*T?2I()Lx5dEU8gtn~$P)<i+)I6drJ%zFyB-Q&2OyasNh+qu#Rn|JJQT*Ksa
zDbqgB(uIKsv7Ek-Sc>Z+;X|2NH{z$VDwp@E?|ou?O+H_?z0dd9`L-@1f52nH@Xzcz
z%Gw%9`JOg$HuXDhqxW4NK7Y78m_0Rz{e1^*L|It|4!E71Fs>`^^ZW`tQ95bOIo@*t
z=3)a`Qe1sh{to6W#-Q<WyVn6$ewPzvBaO74uyQAOxgCL@G2iF~%%-Q`%Gl6enby_#
z$G`!+)lc4{m(c+DIgT~jQXTADeOt7s`Ne5s>ml;Z$J+^Xp8VGRz&b*|F42Fw;`}<;
zW7V8Bc7FXXdUFcB`2aeGr}-50=BEpG=mPfWL7rVaH~KfjpD4)bCtOY+E~Gt-%sz!a
zwg+Rk4LwAcM_mEGGWz%w#!jEH^Hyk6EUPfQIAvQXXXD~|1=!C+?q4`#x@5m#Lbv8S
zs1sp4+QW6^R?nl+hi(5S%`4nrK$*7lY5SF_;iY-2`5o%=oY0_c@j>x-Fh*Ew7#?pe
z;PF=P_br9ATlkOIzXg4fZ3ai`3dVN)nT8{HnqHuN(+lLCsJ8A1ZKWOh@>{g|TMzGH
zej2_v6MQzj(qXr{N$<CS-9ql9U(|Q{8qf7S_4mJ#*ncgYCMj(+x1gI-WH_clU!~dn
z+J;WR!w1H<Q$C*mk+ZW_7WlLyo|vqY#ylI^RNFC6z7FLnjsC@PVDe7fbkQZ5<yrVe
zg@3Zd{1?Q3bi8I(Fs$6`S%c`DCvnqBO7DV8gr)E(ETxUYQd$vKH{iK{Z;&Cuh`h<u
zfT4e~#PogIGZszik=74Q&sN~y^Ci!uw`H@1G6NcswhQ~FKpXQr(vQ`K+J5*7>uXxF
z_kK%zh&2djRQ$gz+fO=l0=(g0X{%FDuUG16{4YyQ@>Dl_T4O5C?b%DaN&1g2D|a9(
zlp8&>v?=D_MShul^#d8(_-wEDWUt3KF+B#pQBR3h8h1LQB;50K=%sYgtoadOF7Tv&
zFTmN*Xo2y*@&547B=W4i|LN^LhW2*3y~x|@)@fU~>-jV`nP@AR(8%twUIC`^7~`B1
zn6<M3pC&Fo=?(5?LrXR(C;2gY3Fii7NZThl5Des?S?0}Sw6Bm(*!F6x_%sw&ofbCF
zUfLxtn%TOtLHyCaS5!vdFW!M~jCCmO^aNjJmykc{f#(oj;8`WEvvmq@3wb->VaTIS
zAwA4_d<T3dWqFqB+>ddm`_Zm;_{?d7-@6liS64q9_D|Plvt&L<;cE98ZlR41|EXUg
zp2G7-8}4ClECU}n)h|#7{w@9)c}m-ie)tG$f%iGAL*Ay=iR(xcJ%KOYSHI}+M*6*U
z3ARU(9@G`SJJyq~HV!yU+S>Vf*SGI3=+<{Lr>Goz>WecYZ9EWQEmZ^y8T)T{luTcL
zvrzw=uCLbv2Odb5sZ3Mx1?J21>Em;P?lWI^0axzyV*I+DA{-RgTm5HlQCRz!`cBo-
zMc346HxtU5KA@fWz4m;Yel#dUT3CZKS2I3rokyDd0QUXrA=W3@U$i-E{|0>NYiJJ{
zd*>ac?916OO_8zcPdks2P`~=)MgE|N1lwe9ZwLq3n;OU->mrr$^eB5fU*~;p(#AIb
zAHi7#`kn<Ha~e5*kINF{!>bDAUPZYw@MSL*<VO53I+AX6-dw2jX6M~Q)E%i~JXAV3
zo1KJRVfLo%Bu_K@G19j4(7JhKHTubQ-tY`)Wn&S%><o4m_^7<6j^r8cO{c{UXhogg
z)h2)J9WlPYK%BIAe;R24Ht9>!AIbx+#)@pjMON1_Z4{4?9?w7dJmfg$GBAS-2nYIf
zY{FfB?PS*cTaQH^f3<G@4f6*fpPSz7y7nWDke<>$=^G#N^v8yD^DC)*Oy5Jg#slR=
z+vLp`maN{S*L!zkc;EHql;x3rPv7cg)&rwP`V4Z}aQ&@0fpYo&sp_@S!+*w`NB0`(
zT&%*T<Joi7`2gXvDq4~r|4S#_n(w2W+8`YEE4^Nv8(tpvyeBW4D47mX+4nK8q`-PP
zdV_x%ZFsHY`y|IV&O4qjx+hQ4zi+$7H~WX7=s!=JU1)ic-&vl1fPb4jxNg&x4(~YN
zwa}>z`aEu~xRJb+yc-$oz|;SPY%lPoKKBss5q{c#zL~W$a`sZrlZhu8=_)@P-sUe<
zeA?swZeHYZe>bBJ_qXXd>h)%IZp&fr@H+l(ULE4&#*A>VyP_(g%!V7VUmAQ%3Jq*L
zzqc@+--`|Z#w5r?q;H3D3E%8HTJ@{zZQpKVYj!CcKYy_QpQPtFjpx#Vylak*Fp<Me
z2L^oE@G&oc7d)X%l=qFl<LNhqbi-%K_?6?6(<#z#$?+5Kph27)B7HS4jOEiK(YXe!
z6dH&YqDv1wjtyyRnvD4Ez%9h>TTL%pou{no7wsb9hK!p0c{tB+AAzqO=gR}b{WG66
z^Y_x#rJ&<~sleY~3OXL2RbuM_bZ@CDea!s!7kA`i$G(Gkir)jNarN4;XJB)DruM>I
zZsP!)bNMp4cR3{-*9FlAvH7w&IlKGpk-1O(X8tl872KQ4#6`mjbWwZ6u}K(T%*D)Q
z^6S`~t}+=kD&))On(u7_GhZWADA(z)i{C72{bTa~#|8TQvCn7!6*>uKv_%y6zL`(7
zOy90>8BqI*_s|QUuLPa1ap~p3JM;&5OYdZ?bo?98t@I0g;=iecPpo6(yhy*jfi{my
zf-X}zt%dS4jKsAD%CwFI=B9(;{IbEMU6nJMsvb18Zy-qDp>vmc+C%giTk`Fsfs5uq
zeS>5)x~)K?+nh$50!<=sb6P3g>l^P1@a4-@8;g5G8#e!atUWXiW#<at>ep`>!p-of
zZ$<uz?&EZxzFRiDuP@+zz2p7b5#Cyy`N!od@BscnAN5J`q8!_PUGyW8XZ`~95q>C7
zGOYic?~b(f^xRLUI^vaV8TvECE6YPJ7JxTXutlU(=&Q!Vadr4|h`8D$uJ&x7M`M!z
zcs40#egAx+@1LKW-k4ry{?hFI?O-!VZVNEtJ&@LCwH0kB8$;Jl4axEEyKWg7J4JY+
z#g3i6Uhwe~@y%sL=^Y;ry+I$JK)>vMSn!MUsN_O8EUoyugfaH?q?BxW@Dq%2#@LON
z<vDv2dem8m;S)1G1x>QKyTiDoFV$Pyhsj&@Qe=%jkCP>%<%m5k-dVcvUmnpDKd9bv
zo{W_<$-kd%wXqHDYz*B$pdI>T`V@3s^}=L!=zohBzSI7<c=GA(nNxY5<IgEKv}g1v
zuD4__{u5PuKGx4q7G&v@^qDg0MgFZ$nekC^J@GGva{od(m&x?`E_)w9_B?IFr#$Th
z(&&fgdfEPI(M|()dY6~`TE)s~?l=4OCQqLd%rG|W&g@1qyFQ`+kE_p~EIE2zeL6ck
z31yaCFL#41?a0=!UAS9oT)#KG-P_z$3Hd*)xz*%cdaobmk~p_?!B>4-a(o$g#W7ZW
zqVs(-x<`J1Gkm=LO@R-8BR&A5?KXzmD!^Tg>tyUQyXQ+~(OJ2ziLSExyl>I{u7&SS
zs@e-u`9s+FkLRuMW?y?9Fki>i?z;K&XD?o#8JxlT%g-V8=S%x8K$r2@_w2}$&Pymw
z@Kk>P1^7TuyLQ&*Ez;~<zTWN7|7MkUp<mI)%fI(iS@4nUX?-4X?mb@nC+L*6>lEUu
zyYV{b^E;6_)fH`?7WTrj7X?{TTCq*}91IpRWwP_@1s?o5b~PIoL*<>P@;h1iZx+gb
z)90#jJ`wOaT3^dhd*EljXQ!L?IhzOZJ$HR<Xk4X%p0?L*<(&5i;P2N4{8(|`*f$uY
z@7`9LU4=)hq>E3zueq-p-ky>&7IhvyEhVa_ay{xuXP=my>SxuT0G*-z0pw|ccFu>E
zTE{_~rSo0JHiL`j1v~M}!7t(I>G^|v*@?0P<u9^+&e2cp{Zjuhe^QzD1cSCl;Wp=(
zL#T69zM)40$H&$8x)#yAzOD|PE=p!+D!k<@sKbv8x!ai}Q%ZY2X_TwpOWND%3w>I=
z5PpGQv=wZhs-ZOG{50(PclsJN3w+#I33k7o$54IQpk>zco^IpgS3Xec9k9Dk0}seI
z`^RBshrDgsAg;?dzRt(XC+f+#y4hE?PhTH<zp1U|&I@?-t^iNbF>`&l`SA4WeJ&5;
zx6$0oYCM8#uaI8VIzwsV??;f+Q;1V1+9CEW)o2~rro}o9*Qr+)#^;r;Q_;Ci!8V+E
zQ!if^bUiM73?4cf8Sj0H^-o%8Lv=od&hhc6xzPCdEA&UWqKnPOd!hFa88}ID@N30<
z=8XmViLMOeihDb{A%CCfg56NGGwr^Ih;yM0*=2@nFVJ-92A>}#KV!;i%@f-7KK5Mq
z@38vjce6PS+|17*9Hobl>nOMRokQf=_e{vy<oU>MnZ3Z%`A$*iA>#M$q%}wjxX_kx
zVr)R4DcRgRH$zvok@9W5?lYLC9oDhEM`Pa$?xpx<SsPd%cSM}MuU(%5Jl)oFZP)pA
zKL=s$1%Ai|5wFZw_)5ayrg3b%ao!be*XkY4^CZXt%kDsH>X`rkt^i}44VvRyXg~7G
z_P0ro`+CAhwxP`_KO$eP(J;~#9U%XJ+7zB+@n0Zs)#)AA6;}^rr1{ICZtwY|N$(S1
zT7^Em^Ev<dzGjNPY}vvt8`d`M8!s*$;l&DZ@m}{9t%V=yT3_TgPm~RKliSl*jo8z*
z{bo<kp3t7ra}v)f{#N)jo@eu@O}lp(IkkUN5x0Au6yF?V@q5z0ny<&`=luM|LHxU#
z1H7-&9Y&YeDb4-=e>Wo69bZQv)9IhME`J&AL|QwnGmx$5UzI;Thj)gr6K*N!$Xn2n
zE#?@FlNM`Je7LsvR&47--q!uJg$!%l4*9Xa<@xuLuX^O$8CR9<(*9G>EA`T;X}!e1
z*h;6eAIqLF-w12G)7R3|&kSc@sQXNCHy@koW{3NzY^+9jjT|2H7JKgncy{Ms(`AbL
z)3fuzP5rD4`kB*h7wPkZvNi{@rm{DDw0Fbb?O~pbJri=YXTZwzagL{rF6eu>LKr;l
zY%6K;+(#Tciw}Zl=b?3WXDmFk`KadhA?1lr=XFSzA9LwUbY`dUUwP7WXV#+Z@q+`M
zWVAm(S|5E4oP7(tdE(x_g<lZ%^pz*xMSrC7%%5WGl#ni2SGv~7E7+bok2BW3XffZ`
zXa^f#eK+50U*{=^_lc9X<EQw}V}$lP6C`;R%&~l!8#((5zD>>nHTmvN^oVn|`Q2#8
z&Vwz`9z3vffTyF|6mKKL<QqOU;$<G_XM5f)!lbnm$`HOz^B(W^>4kkU;x->rZllgk
zE>H)(Vle5m+DCqQR;P3>*3Qja8DDD>mLFK(wcB}F&og@Ufu(qc-000?W0~}&vj%7O
z?R%fU4d-{p(y9ZkQqD1P7Bkg(%+`Z@)DNv;bUsXH9<!3`kAEoWkAFaa_<i~+E1WjW
zPt>I!N~|lIHDCyizCq*uGSSL>MxJ&Ya%Ota<M~<EsX)ix<@nN6Mz*KQ5YNk84o%L5
zCcqR8<wuEaEpUHAP9KBq^p@>JoHJW_*&S`h2WiYJiKX|Uo%A7ZVA$PTv2ESUAYC2(
zaN@^MJKz*##oJLF*us0q6@_+$yVg22WV=%0&R%pGVZ|4`ABGEY<Syv*7I-^6TT3h6
zb-F;`SFi8pZAn%Gu7!JwRDQ<snZX7UUDHtC{((ZCtura7ea7Q~Y4#Iw`#&i8V`Zm>
z>{O5&9-ZS=A8dSJ=QjI<_3RCF8JsD(mN|fP$O-l0+1v%-G?2lRG@d5oRbwsgH4CQg
z@sSqcn~kb?!}mmyRsEwYy8+r#f8v9jB~kl4$A9=TlV$sdm(o-Zn33-Jcy0yzNPM18
zE(>icjs7StTLN|=Zs%F@I5vJC`O(@TPs6WIn$pM8@A34zN56N_Z=NQ5rP|l+t)OGz
zgVz7LU*FQS|ERnr##(}}1wT)d`K!q}LrXtY$d^97k+Lek+54&R0nOjYN)0?S@GPW7
zJKktQ`Yq~n!IxxxrJm#>%50WG56Z$f!_8z8ob3!oP3LKXZ^_yOpM1QiUG&;BI7cFR
zZEt&twbg8q&SUeDuZz-?!hb$``oCVw_PlJ*dGZBk=I3IUC~M!Z2*1p60Z;4SQlN|Z
zoM<=qIrRrLi2N0=tZxh8Asj_h(zZ)?D87Ua_x^#m`P`S(cjmF&)@@NvWmcWm3PVfv
z-Oh?w9&iik!8YWaQjN0IH+xWavC5p!Slkx+BHP_$Gi5x;UW_;zZlwKw;At!;IMp`^
zKWK`)S3l}?riW!^$DgC0`i!^Jy&dr$d6$k`#Ahj+%5*jDMA+un7Og2GzrOegkF>s@
zUHYQ{e^iF5*LnM&DotO!-p>uv?$TQvpD4o@IlVqk`5O6K!B2hEKDypv{Tj{}lCQlR
zJCo@&wY9Zy^?ra`kozsbx)2z=?H@8K4^5*#O7qsEXQ1P!XjggAe$i<!TP?zs9c=oO
zHcaLjx5+I!+t5g|=Tw5NbGzF-%-v@D9P&51-{PzO-s|tKzt^yp>>J7(X>Sg^gxf6R
zdYN}0zWon;PTLrZbI@ODl|Vl$OL>z!rDtA;aFu_Y1-Yx+*>8M+HrI#x(1?2Cslo8N
zwvVN-;7gD6eGHAre?Ep<F3U3mdP-i*zcNxM$2-Dx-O;2C;bOF3Cfo)$z2Skz)L98U
zlD)4q*;bTQdX8TaPLFRMFObdUxOd%m^s#S*IZ-;p%UHX8X!`-ufN5uq)kZzoe`bfX
z|7z`y!AX8V*_zcG63G|e7$)Idav2yr(xdv0*6!#3-xa?D4*bcpvpOngZOQk<`JKJ7
z-(Dv5c*Em*_nEJedF!9xRJ=^P6wcBrt<7A2FS7DvXklenr#Br5x6{CldYsP<XA%f&
zEcBkdj&D2e3HSn2Z7*IypItVI@9Ev>=K|v$?rJ}ytYBn}p$6rdtM#pMPK&LTL}7z>
z6Zwp>Q9WXF5$zcdGT+;JPr){Q5B~gH>7#VTh)!9W_wsKjlz)T!^S^;j3tZ`Y`DdEM
z<;yi+&C?6zpYG-VYNR}Ivp=MJ&@0lRrpqIaKURS8W0buJ99yiP;IsDPt(~7Ll=&&j
z$o5x1Mszmwcfjk_h4QbaJo>}ne5sKBCGZr@;hUX>RhTyIxwCN2|7ZQ2Kl#lID5G}g
z;Zxi14fuJ__jKf^F5TI?)7LKa#rk_F@Ga6{J}v0c0zYiOL$D6HZBIDP(@L|m>YlH)
z=sbJJcBVb1u_k>EHp)=i>$OgO4d;1X)>KyW#U<Hb?ihuo{83m+E5hm`xAf0!lQ=&>
zL;F5KGT(4J^dkCBIrX`EfG~JSSEXOjy4LSUzVGf*^U<X9m@F%-@vZj^Ww+7x$zPuB
zy(9D?V~$WbeOuVmwfO_v%hqOXpEv5^EuFK7uQHvOsOLK8JHX`$`$u8CncjIzJ?ULQ
zp2j5kHZ~Ri4t{gew2v-$^1C%Vd?S96#{Biujf8%YF5O$zzmo*NjXd#fX?oJJSK1oz
zANdYK>C`hlM0tHr@oLTcZ}YkTPS(dWfv%>rh+n7pLF%n~+1y?w{pEu>UEk>~q1#z^
z1UX&9Hds>Ms5fdm$kwuPg6`KkS8!zC$26@gdsoxn)9wj2NMWuB>-H}B*rx2KncW6F
zjrZs?k=<f(<SPFbg8rEgUHHWDEIDVs%59u!;_9=?c-|0PtE)1cLmrgDzfRkuZAqqR
z^VXTdy<|?~XuI3FJK)&4$3C)yezdccgo`#^RdkH7DvqPW5*~-?Xmp0*mm(vd^DzCf
z?{r!Pf1mfke7nNq5bcm}dSrD_Zz!K~(k+{T9cg9$PJ=~#!=3RH;l*^l-L_=ka%g_A
z{SW0=!B_3dx1st~;3@sLkmCpZjP=hKbnDNfTb19Y-c-cb>nx%7v}dY($+h6MJrCS<
z52>Z4{_bMO9ddmyIu!bm<IULzgEx{d{G&bB{0L*B9B|V9wZ^K^$>3c(8|MA4?Wx*1
z;DeNTK(s`cGar}!JKx)Vgft#IFUk9f&@JDOL!LAz#Cg1_wtOBp+*X2oCO5NJNnNuy
z^uEEzSE)e1lFy}oUr76VXj;RzT=Krk-%nigvcbO^_!=|JffgUhxAV3ymyEDKRs4?%
zX(lHN^s5f7PdFD_yupJ%V)T37GHdfTYjb=XL;j8EZvh|qb~HxhZ)x_4D-Ai2AI|)4
zAM*K<JR7gd?+(_zx6OxjFFHi~W5f4Kr=ic9J5H)V?-Y7d-}WNNGk=ZXk$=2oR{S8I
z>i_VuZnrc&(<ZMG^7Q?ejU&o6!Q-g?r!D-ae6QL>zsI`+^0~c2e=7;FSo=H><_nu6
zH4iQXfABuxSq|sY8wvd)%o<@@=Uf%vPkyd9tz3yYCY0Mmx&7#R#cdy<A7Bx-?~Ww%
zw)Q7|EFb&u5nt2xldd_{)+L<(mX1%~^<&su&r6!G__6Sf;wyq2Hs3WjpbPbKA5{l9
z<NTz^dK3Jmvt%oo9Ds|~E9thRKKV23s}R>%&cC<43OW&Q)}fK|>hx7{^_h2?T%Xvv
zMdi_V&NI)N-iUFX=T9kH!<XF+bygZ7zUuLPic`Lsg*I%RN<7^R&83S7UpEu-?7z>%
zSN3|`-(%@{0dzRhKOtM_9`wm#4_MMG&__1SkUu1*Z42Xg$F|Y3;8(2c<$`|0PtpP|
z|FY5lVbke}`sn&)@z>o)MW2kGs;@b<3_U8q=54lchquDWl0DceyW9TF>r2Aem5tlm
z#eP-CZCvWe@22xIO>h{(vk_#$?hkL5_!rawe)z`Jzk6(lGgOkBtdb<ic<}wGd?sAE
z&xbXU;S2vvzRAniV6?xVwrnqkuzl0P+jy?L1@>LUf5D?~Lv4%Jl#$+OF7sBnO<CS1
zQ;IJ$*C~zunV+ZOYm*HH9lZe^y@fG%NfzEkn_B7EBDrm@`0Hf{y~cb=W@p~$b@eXR
zRlHbN@nYR>z%`d+a5UcTa@(;rVu!^zFmpSMvSx?rEm^Pm9@)8pHs<r_i{36bbCgR4
z^fXzq_3!og2Do1%ErqiJghe;ob1XwgXm4YiwYKShPXphpjlQBWX%<#q+id^3{s*b@
zrGLhTJ{WujaemEEW>MzMRwF--G5a>B5Fee>WzWkO5$AZx-r$~&dg0#WG4tUV{g>Xb
zhJJf-&~Nhfm@lI*TF_VCxsLnrTNC?^fwYxX=&mv?%CC4i*;1sX8S@!?A8DI2hqZ^+
z{jVDOkaXM6P@S2=eg^TO{S42~_cMsc{S1TsD)j$>(B9Mf{UqKeY<TYt>0@=^C@pHt
zk1cdWZNQ7B+E%<$nqHqU2W#9B$DZIF_W5nCF>)q1U%x-LFxDQ+SQ9+aCj&3)>n!<L
z+?LVL8Fov9xr>MW1KabIj5LLh9%yDdv_lx&gsbgs@Q!h7ukN}?_b-&mQ@*F!-3;Zh
zmNXx52RY^L71^5hy-Z3!JuF$af3t&&y=%}x<F4iB;A*_TI8ics{7IqTf1<f~4g0J`
zKPw})+1}6>;kk&;(!1#I7q4@hr#QElfz<{U59`33m$E%XGwEMDQ$tvLkWI-Tyf7Q3
z74(<UllElSG<mD-X=tVU=|uC5Mz@iDuVTB<LTgZKi*=~#NDr!g*%r12r_H#>FT23}
zv&!#}X;=3el4mkf?CU}LI)i+4=`T<3fn(M$97j9v40cg3{@4De0}dt+v@ckr|FSUu
zoAzhPlU$gLl%c(yWg$(p=!Cka3&o!W;yjE0JIrg@g|xE}#<b{NygO}CI$({waBdCR
z?!%Koy>Nfh8g=45Mw?P}N;i&g+kc1N$l&j>UJ<_ZMP~u4r=iz@e;7~yA81P-bZ5HR
z(}d&Q<(e~WUR_4^y1rji!A55M58Z`r`P{qh-wW6rMq0cJTjyYZC~%;;jX(ZTA>CrW
zqqe{6;Vt<xIjb>-e}=w|elLm5oPW3R(kbS$`uH`|$e1))mhY-|IDeVOY<wO@TlOV#
z_(i#$LvFjsZHC<P=$wMqB$_|%E&=|lrtnF~LR_2bZfpDB5$X1A?_Y&7c3;f`;TAlE
zH+F7UbCBZjROfPc;P27c7+RN+Z+@{a&?nlr?|DeezUJ%N%L=;dGIX}!Ap<5Osw<iE
zwBy_0xf0q;+d&>p|9z+c<3n@P>CJq9Nn4ZpE>>-w<!${&q1<nHTXAiwHi~Q08gXm)
z@U^Guks%*eVI4}HAN1USwX5}pV6_MRpRUvYL!tlqT2g0187Ef9&pYV+$g6dxLu-G*
zi02@r8`P&IhkeN3RZm}mk25?eXH65%+n(;}`u;)nY%XZz-#;|_r14z5J~Oz3y~DwG
z5V1`0I|xeyUOvwdjy8pzjm-1#&p~G!=PI*R_y#*5`#0z5w+cM{mUtTW6@@P{lw7-Q
zP)BLkLaXdCUiVRjx{q>ssIdNr&UP;}<)fWwG$C*C2B!((lPFic+~YUXPIc<a9&-Y7
z%+wO+p-eXapwPx2cpLM9?((s3>OUB0yQDB@AL_}ejB}m)gMTZWH(rH@j2q7VjU8JJ
zZ0F64t?HO@r@WP6y=6GPq=3^)4j(VlC8E_>TWJ?MWvzcwG8dbU@1loAy9FL-6z8~j
zen!5J4Gr$3dq3@znb&0Z@U}B0ea357x+1LoO&_9rWpi5{$L*8`wEuS9<ZkGjuy4KI
z&alpZk+Z5iPvtp_Cw*>v=2;(Y&rI-a;hB0<d**DOlX#9jwmtI%-cRCr?*As8__;i1
zel+Agi?HF@=G$)Wk(J)h{yVrYpkwBDhI3n_RsREg7U)N+|DYi&e;wj+Eg8>2RlgF_
z<#*CQWwKj=)u&#?&u`IAuaBHpcb2lxDKF^F>@kGPl+zfc|8_4;gR-oBY^`(bgyE81
zTF>caxNZ;i_IJbFDn7(D&7{|nJyQJ?c!7t;jn@3x10(gaHR|=K7jfXegM41RUGNx>
z@eTuE+Z_hHZI4X2m!aW*PS~EV;d+QR7wB*A{$SfasUWLQV*F6o)+^v=VgL4D^RME%
z%iyrNSnVlY`P1QTdkKnP<Z*wSFJ0xO8<oGLchEU`zrO2h`-=;>UCch>yYWl(Ts}UQ
z7~hPCuOd7L%r;}8!+U`z@^1+mkeAB7QlH3I|LiV`vh1OdW@~Bk?0XCOvg)KS1UNQN
zuL8&8>k`IBcMzA4+I*{D!as9QrKGWBdf=Z6`2REbKMFjd{lvqZE2q!NUC4HyHh31F
z1iS(rvSYk|x*O(aRgZFY+HEJ({1-Qjk)I6d_I=WF;jWYd9Lb&e$@QN|U=+)i7EdT;
zC-LvKt<2}t(R`kLIj+AONp`KbdlBtQmZ+b9H^iQh?Gp;G)W4ljnSMBLs&iWAa|K`N
z6_dRa)u%ze_EXfKO%>079Qn(G@u9GIs<qs$r%%q>+GZ~7(^Q{3XzLu{*c=9Ioo&tj
zhvQuzq1W-Ae!G`n06sRY{PsJ%e<sJCZhOJY&;`Gj_9m?l4+a=TI@&#cv~BZ#gelvA
zv^XB}xpEwDyzL@P@kaG+K7BrI`uH!scOu;F8}-45h-=S&PV)(SCBRRf3m=)}OeSv&
zKEwP!RP5!Ly&dPRRgdrWH*<sKH~h`qVDWl*OP<EgTg%K_<JS1ldJ!Jm8fF!KXdF#(
z-wFTg(m8p<xr09X+xrJ&p%QqT-6cEXJnl&Q@vH0}#TTOcpo!?BIZp3PwCRuruf-p&
znUXD>!)p=dsrEwKQEnx3%`$l%$@0kms7W&)95A%@4`q-))?M2lwJFG$m$AKSXrne*
z^OM&Yzy7fG^q4)H72q<@Sbu8ZQwera*i#Afk;&Uu+US#?`kW{F5kG9sYxvv&?q-(*
zQ?`kX>)p~fjQwq4-DUsl5uK!eC?}p8J=Jf0>q>kqk8LeQU+S!Pc$)pN))nrLMPF90
z9{Jwo)lV>6A^E%ZOnhbu>p6u-IEi+`(bg@*vzgG}4RxO*(-2Q9A#S!4<xKbRR@=w(
zn0`{+>8kamea}eR(ex#`8-J4O^W?H+GQS32jTX?M68tm0-#%u&>f5;p!O7q+Ys_ke
zHJj2i=VRhLCr$s`$mJ#xP5nPhqu*@Iv93Ib4T2w4ZO}KnPhW8Du9!LAsdyW7j`lU=
z|5dq(zMtp%YmMJk&UPo^%vX&%Ji%5el)Du?l{e>pQo(LB7m{XcCB;*ZS9mK9?=4^H
ziYr~^8y@e{=LOQ0*T$b*!wzo|=2?XvLuUz!Y51DtAK$mEIh${Rd8^No<8+zzd(F<?
zs-M#n_wax38DyzOyLG*hDf=Fy(6@P)B_9XjU-NNX1l<|_u@>s&ys3}et2{S;-QUz+
zBz`&dOKa>VxCo!erO2oLyG(e<mj0P{+4y+Y>)JExdFH>$JqtYXeU``dewK%oUwocP
zT+hV2KOXMlp>4C#c-vg2_$qu*yx}(OA?b?H$I|mYUW#kNCf`GCNuF0vvv*(Px*3_F
z+zmnRDqOlVoP*Q8p{*CLlU!jdNN!r_p1TJ&O<v|)l?m->tWR7w0j>d-)jgBC9b_@W
zJVCGu_%@7o_>36?w2?f#v!wm|e9dw?<;#WoQ)BAG8{Kbg^?!o;y+VDh?~3hDkExHW
z#r7vYP5o}6J~}GwSwIJLhHTWaI_FO0W*+^y%2?;&F5W#&_VG9uzbEW@`8Zi9^yT-!
zWf!!ll%}U7N0CPVM7r*<7QL6r=gIS)O5TmWfAm6V2fY1>uT3<6P<DSk#BFWpaqVTu
z=PsGB@G5W$b@To3Vp<%d)KyutQNgiU#y`Cy)Q@Xavx$G{4Q8X;8ni=s#-ire#SA^E
zICwISY<|``F45C;K56RTM%IVfbJcgsKo9K&R?nwTQU9)x*AM;E9=&vn*>QdJ#j<pJ
zX*T8TcJ{eY&f25A>Qvu>pOG@Ew@*5auyB*!%PtLliF7<7E#|1Vz$4s5ix#wKhx$f~
z7J0~Vslu7Nvf6Oo39lO{w;b>n5BBp2M&wBmr^9e<fomG@-ap5FYlSd$lASa34`9;F
z&au40y@-YMqOGu|9xTXnb6axGVKN=%vqK+w%(mGT^zx<y^!2s$^+wW{;Gg3ne%ZRA
zOB!`nE9@yl1CtH--E1MFr|^Fi`8VDW>gQvl9nOne-nTrjJs49t?H8a);_^RFJB9cW
z`3fF3zjp#&CR^~v+WQRcdAi}d3!E#-X6fbKZQk;)RKfY3l(Rg|*Q?Tt)1|-p_+SjD
z;Nvth8}pNtUj`O37<2@_!n}U?P7fHf_MM)k2mXhB^FV8>FWKml*LrB(sTvbs3G~%`
zyvTfzkIgcDoS{wLW?OXBHf8vCgrz0WQ+Yi4ca#1zGgSAG*S#>@n{NBRDt|998no$Q
z*+<%|$@7bF*(cI?8CrL!J#6`*wxpkq1UvKgim>l2=oG<(f2LDD<#g6~&%(H|ev2Om
zMFXd+=2FEU0QZ>pfalF?FE7k<(jk(EsAu899<6o6tK_Bdd#+%|5ncih*+)U&HIlU7
z|7Gl`@Aj~>nX1mgAOAbsPf6ymdxqCp=#h91%4pGsKYj4yQQu59@1t*&v$>*19#5X9
zxwecAln(qOrvjte1Rr4Jz7p!hzT{)1nCA09T!))Kg?ytMaO6)hKPurOOpR}iqaw^a
zZ7rB7^mdqQ>ZS$g)L^bnnQM8NkM`teTHwu=Hg`=PcbxmbSEskUIjN^p=U%SwZN#TD
zlc_qs<2)`untemsqE9@!M@6=t?1(dyV-oq6^;B!x<NRLXcWqqQH$&yXyTKk5azuMO
zewlsjM}+He@aacfYz_E5*4t6j|3n%*W6oUEpey!pll6+uul4RdX8mFtS>dgJ=tzFk
z^W>u+Q@2Cil)7zr!o$3XJ?7s6@jjg~rtk04i(bMwxz_(B!r7{RpvmIZK_)e4Ywlmn
zhU2m=BM!p9Srf0Y7e9TUt!bCK%nz&g1v{BM{64w^K(tC^kEl-8z?Sne8#m+g@%**>
z<MKs2w)fY9UuBJLKZD&u_WO)$;7Vo>Bmrl9cs@=kUwdfX&N=u?*|WOzs}jnntaPBY
z4ZZXAVHr9`8q(+dzu(k9tn3fMuZ58@l=l(&Z-XQ4Y3|kcjT4K3uF^N6*@gvZdb{)v
zWy<K(K2MFX9)-~dqDL>`O<FvIW4x^u@)f4cn)28JNAzT~F8U<jJyY`Yr>`*D7T4V2
z|4!&R#%PeI{yHoB3$K{oz3b@z_w+-DzZQ+lqK(T4bf0`xMfXzKnlkux$cOf}SE~Ca
zT7Ew3^XHYM+eKTmv5m$BSp#nM(S`pJF_uwb_%YU)UkdWoEc3l9XWQWKsqj=|caQ#K
zZELzGi~nQB{4)H>fX}0IKg|WoFN86%{RAJQ@Hl>}y8Xm@kcU?A1FIj~pRgh9Q9cvB
zf<K_iyT`MjvXpC<p#_iX200lsW`0<BoUnoM*qv7Ux?|}3!lhgozcpwA?-oQ0`YJ!M
z`jq#XG`q`aGW^@*u<<?WD_Q{FGHc2?d=Y$~tZ``az6_me(1~XT-J`u{qkmbn8=*gG
z%~mM8aNG=bN#DLp(Y|Z*9QKHSVd;EZD|^h+KSuf-dZB^rk*_(__Bwv;zEYN=2MTGE
zzj9yjwY6xcLpwai_rB__B}0ty26Dv1nIxkbeCPZ(a@ZNH?MqK}*ub*?LGq6Ciga@C
zq6>n2N$-s29q>HYO+)pzdR|5K!km)p=Fu_KfxpFhj`C4QZ+dvL&N!~?pWWu4zxl<N
zmwxWPlG5?HKqpVXXpnB@kr69D71GyiyGGmK^L@?FE$UXJ3j&SBGwGN!ll6gS^xbTp
zi^5zsL?5TCbXN5cYlTtTZhgtLzKJiU$9Y~lOzU#3QKSDiw|^F8OEBJmxBI^o^i~3%
z(O<d?yw}(>*WBKu9~(QoThbN$TlMr~uQb`57|2T4-@?Yb>^zfA+D}Zc(C*?@!W*8y
zfIMJ{E=!vKcnfBxwFBWukJvAh?Pcbf<T$erx1abL^KsZdWEnlIvC;wVJHZ1uJ)RxY
zYKw5&*G3*@4DQhyqPKwlq|T6?L%poRKA!hcaE#WqAg2@8y3IrSkj+z%<8sWHy8xPQ
zLyq=BXCCuaRVMZ{+oe6o_MTMpz#Mq87Hals|JzA&PmOa=d*OeYOe<__+p`$|j|=j$
zkufJbK<5RoCtqb2|1^|+;<$RR3@}ff1?CKNnPdKDY&OwHHaB)?A6k^u#(#vevsKET
zIi~CaWqGvUn9e74t8*T<Y8O7Yz`qTSyv;t~y{SE-hp8()yy$D*@%iwVy4z1>URb6*
zp2sqN%<n-soe%xCwuo<P4(JeRRm4HzrT4L3opm~F1(w!jb0c&pga2Oe=WR4D56)z6
z<(x#ij`fxN4A4ns;(5)OXMV4~*B#+c^`(RL@?kos;WmTmje!k@jxd{`^!dtoo8Sl0
zQOn3>R+tM~=+<)h4oLLckwG8cqhm3yt0k)%UyIMDoWk%&-;COMy;)BqE?@cL=Ha-$
z8<k(&{K)iCV=&hTU3_%kTw`r9AI6#PLx^QIwu7ClxiL?Br1gf;O?r><Xf*bJ>uw8p
z#y;EHW9y5pe?w^(y?Fe3!uaQUAGn&UWTVG*ZMaJj9Z}S|3-F;q9Uj?rN3<nG=T6X-
z;*G|x&MNone$GN^bx%u3Lr+*a%Gf$V`3ft&51blto?!2dvGqFOR+xW#SB1T~-W!iu
zZ}ST8Y<JK}rbh%1xa|~K;M~F@`b%Y_9o<lze6zRTxNiN<o5TDT%d_tp^4s(Qy7e0T
z-v>XB$wy1L2fd>?WbzB>sugd$68ahU?QCAKc1WlF-R;m0V>)T1q}771RU0XNs($mK
z+0uum8DmZZ=KUdC-uOB?E=T!_Uih!)tqsHY42%?B^T>}P9kQv*eJNL_zLw&Q;@b#=
zpX`@(CaEXiVy<j?-z!?jhPAcwZB4!vT|_=IM&6kDr_e5I-E(5ww|*|%CoMfLpUmWq
zJ4@Le&~qO=R(s`#@a;_0)8mf6%5<LjbGjx^+fVyF^I;bACmSpDJ?39KTg(f-plidK
zuWph&t^Z(M|1>v040eTN$;Mhu{eEbjzSr2vT2f*2X`yqieCy#oTiW=Sj+=IW677K}
zHnQzq1{^3$Uqq)heSbCN`unx*mVZckQ|B@J^tTf9=3-H2W+OV2_#^4e<Wr{w`a`oJ
z+oYf~W0|7P%+nr8XZGoL5`0yx7g?)}(HE?tdUejXJ#p$vbd32D7>ggn*7;a7o%k4f
z?qke3=QO*ebDA>~=U@|^gKfk)(#gfiH=S1MeRk@~?q45!Ws~~X@$Qk1@BCEW!G8-Z
z?75HifYk$54_NFEpVI?YPq1h^T@7>T_7iSMHuN7(x1adrr=s7E6MW<>z3y|zJS}_Q
zgGri9X4181NcOb;t+N(Sl6R*S>N6jyf9XN`JVQUaj9DIy*?89=@^#wEGW=UWhakh!
z?dicc+c-}5Ud9@PZ?Vu*6K~`@FZi5($#rf$ywkt*xOA8DzvJ<CcuQ9`ufj&dKdSr<
zx1E)&+~s+9zC79I;dI}oWaVs6|EJ|-pNG>g9ZXhk^7Q&-vd_btDxBHd9nyoIq3t^d
z=Llq5nV%`4OpCnLAbapA#J2_Atho7bR(@|<wxr6&GGq0SjXCI8hmO!?to$5JnSvaS
zh4D!F)&@LHf-ILleahN8`;lP%p!tT&BhaLS45r}QhHe$@U+}JRHsUU==g@WUu9R#&
z`?L!$S9tQz`6d}&h#%(vY+={4X_U;JK1lB(Q|MBw_sij|rG=jp&bXES{J~P`JC~N4
zubZ;(se9}-!?(?G&nVn=P1~JCXlHw80f&zSSfw|O$HB(bTKh5M`)U3O^<~u7*7=Wk
z$6W7aFW#)VLT5#cCZl+@0$#nd1I<eJ$ew0=uZ7F<K*uv*pJTR}#y)h9G!Tt#kD0e<
zBOHr#X(o0juKeZD`Mi3X{o_@dXOnC0wfS1-ii@~fnU#?;D`Uz`kCZ`w2^aO>Y%<=$
zrTT96Pd=&su0SW+zr9fJCUo>o$E<%+MeyzX{;ZX`x=`kSxqLY-E&ql>{_X<ovkU3;
zaq@kdi@t~X7d+Fe2ltDfezou#W6Rih8I0ZDaoBEJ&+@ju^Pc$0(@Touub6J~&g#iv
zuBwmNbq23E{u-1WvCmt`LWMTbTdup-P5f!_ZAdR`@5IK=nRnUvv+(x2F4ve74UVQC
zN#m|k=_Sm6zW`sL#qN4(cJkM5DD~bJ;yQz-^mG9|`!@2s9*0g%;=LEJcZ6-IcbvP%
zwp*qzZTeE7FFdA4K6A|arC($X)n^ax!C+6H-UxT0n4fR!d!`q6hB;^`{efkZuiaM#
z+j=N(>OIrdPmQTl4RxZOetILhBKLa=9`sb2=Ds|ADyA24ifM!Ty_?@-<B9$UpIM;~
z&8ch5=Fi6meU|OHBs$WjrSn$!_&UCUHy>fGF8e_H#|zN10WDK#$us0j6)mqBPs{2F
zkuID+0EfJvTL*p8{F|rWOnQs?zY@kr@@Va=?sZxXXws}+b48%vAgx!WuIYd;J52`k
zYCaI#8<aOXK^vooXaqeXUsL2j@(}kz4x`zo!Wqobadx=e+4;VVNqAfvwvMQw!?q#s
z1suY99A1K(jc?u>V~6=VsbhS6{DXGy;f9v>Vb{_pgK@34j$-@=eSRrAukZT&!v$S<
zULpNA3+cZ&NH<;jvOzqzV@ByVHzH##_t8}F9kwS~|FH*=BCqrK;^arHg?Yeyd&rip
z$>|gQVyzk0ixb~IuavPSIAZy7sAGE%v^iPQJYS$+>SN$L;5W?}IE4H!Vb8BHS1Nqx
zgL|%T`CR#d_t-a*lIP|Jkhwd7-9~Sz4TV#9OgPT(`bK#E5c;2Q3C!=SGF{3q@P6Gf
z>*tfp!kv%`mslsA&v+v5tOprSytltd`#TdM{IsywBO87DC7HfOVXa~FGXD)<nbJ8#
z)7PIvUt<%D!$V`y<ZhYvd34@s-&_dqOK7{}_gU>FybR5WtGxPieM{vAX$>#0v2*eI
zl<~yg&NB4<I`m~fY(;P*yv8uR+gjn9^wqiky8V<}d_KBs8GMM_8IeevL)443K`vBQ
zb>weTd)D92dVeYROmMNe1D;LJ-(3=)dOHg|+quj?q44wSyeef%&*1zOah-=w=h$c1
zT?yyxA|Burc^Unpr@-Utwu=1|O=||xr}ynA*_qulp30fscZKH}gdg|*_Dq>4rj_3|
z2%qw=oOgdhdu9WV@_&-Y@IAMH@43iWq=o#Bkrr1FUXYw1Z@hz?xXhTGxXfIF|D_-!
z&<xwCQcvIHG^2mUN8Ued{+r%2xZv1vxmrUGB&#~Ru})`Y9-wa?N6rV~7crLNy^1ma
z1%<m?V%qDGMfQWwPRi_2{aCW7|9@B>cxe1(togP<s~DE;s{PwXZJ4TNl#S`q*VIEd
zh5unj7@lS@7w|tK55~8b75MhD<&bt>A?-ZZ7pl{BT!1Y&QO0t8p)>p7p|%a5PH3lh
z=fit8N`8NPd#QPlzVIw%E*H`zZMWaP8tgZlPyV7F&f<N%fXl~)3;O<(=a#ZR^!)n@
z`S+2(O#8cNBg)_X4*S_IJLKKUc$2Q$I+a|Wu6yuuJA(*)O=qbt;UJr(a6VCSlTUcC
z3tf`o6CKuNCos0rXRA{tryumT7JdL(zc}K{oFTnX-;Qt4`@Fr-=k0~Dw&MpJUk`hm
zV|3D5`X^g*obE2*bhq>2#sVMYLs8u5jC^=F*8wpe^+1fTr3>EaxT;)TymOd@hhQpR
zgsJ#iFh5g(nX#TU*b|%M*s`_a{WmZVcUg<uo=5!W%1N9057)^rP2O{^>E>~|I=d|i
zGJRTsR;LyC_jYI``Q1XF?&RruzdW4xE5>8LVtlQB{j2wDOM(6#&SA!Qgc;*&!93>s
zkd<4!|JM}ye@&tPQ4hQ~=mCx4(YbL=IefOmzO(@Q(lM|<<glUhhIY6gPc+v&BKy8*
z3k=N#WoU=ajJowOJvyQ@O}9R)fXlPM<xXH6rS41{_#V}s>g2ljDD~*m3wrck?E9z-
zBYi&+^4Fy0)rC4sK_;WFkM=}v$K3Y4%fW_(v*Y*#^iFG>4Q4&uV=dgP<3mogKjOCS
z7Hr#9Y};+D4|udUr!!Yg&JM6|zQ_8NVmrxiKPO$Q`)vw7spDUKh30V6>%4=kqtg{O
zIY*x}M;%d@e=PJb(ki_cyX)3d>|BM?WP@qVVt3z&&a#IionId4Y_f1`K^AUZp3eRv
zth>w(ufbzI;<MyK;W&2!TV;?3TZdV`(&%^E>4!AQiP9>Q;k>ukF`v{NcO~nez*(S?
zXkc>Pk`0B8&;}2}n^^D1Z<1sFb>u5=U!A(V_t!&wMen&lZ~J%K`Q)?qu{)Oao<Ya5
zcG&(R{^_FoqqSBZmyaDJ`z5w#->J|J>!NASGB6hX9H8zx79I&>H1+#h++NS?3fDe$
z_xiXYY&7gDy)bUdr1RwWl#lSmWa>5WaN6yLM+Y8iy=HtIH_kT}c)M|#{??Ct*Bg5@
zL+4Qz<cn{d(pUyJ$&h3kA4Qk`%T5;mgY43m7>9PYFNe(tjcu*<NaY;H(Upzk1DRxe
z!pn?ylB*@77JmV8{yDh)QLmjUjvupsmR%=+Yt$RjMoj73^?jY259^uR2#34wuSdp%
ztl0Rfg)%n22!GGx>!Zju^=y2#crWmz(2uZ<A;sGsS9&d!wQ)w+%6M9{OdijsijNV(
z?dASD8y|#ieDJpM!P~|M@3a#5br=mQ>gNi)H2DtSy9f^QEqYwMKCGFgV{Ko!DC<^k
zl5+5&2A<w0>zm?T^`#*19dPG4YI)y#w)s$xDDT%5<o&v%koQsFQ(u03Wc#W3OjC3R
zZ`(^JUB1&8F0H>1TdRHqzY%jo684bN3i7n|^wMI($L$rNAFT83JG6AO-KEbMW*zw-
z*IceW!42p<jp^opEOXDPhmU8TKH-@4r_2ALy&c^z`+o4_(HS?B?`nXZc368aA!qN$
zN1WHOy%=!bJF7OLAJy964i{_hi=x>Yerfrey7Vh!&g0Q{1v(Q%dDa-+(;D!S@a)P0
zd~LbRY91hLGOIMkn8~ryqI|UR-}K4j*?5J^G2vClv+3P3`n+HGb|uDxjt*y*DQ~jf
z3T+IPFQ$#uG2aMv+a1P?#)QhUer?ux^DJJ04Db%?GISqw4spu%nWv~@^Aut6Npa=3
zlaPNM?+k~4>HnBd+3OPE@ZMK(+Yb4Pejb}QEU$29;i&KL9q?iaUaY_ip5`vji|hjD
zF0ye+7QSIqm^n3H<Hvkxkl)W5(_TNk#;^V?>vrX>(&x?K>S6f|ZNARq^pi0A_S4zr
z^i%1y%icJ$5YAmB{PV#26w6^q*?z+LfiAL(BzxxfIq@6Qy}M{*CeUX%@8F=VEYxKT
z1=;zk{L$RU`UTE~2!{+9spCypFsoYUX%5>!-bJ35;@5GUZLacgn2&r--DQq>n&y~E
zU_<9_a{2a4W~SIDd3V8QXzOg<7i{D3l(UELsCi{UFTJwhGXq}HXQqDv+x<v}N1&~(
z`O&vFZjV2Auupry`yd`kE>(x{t#z%<NV`3xrOXYwpGmk+e)jJCTiC@_-IW~XI{AN1
z|NO(w%aeC;mqD~2OY%|k-T$f0lEH67?+)$ov@6~Ya0)b>UiSdB&SKi258D5%&hX7j
zY;&aV(mUDSdM-oq$Jm~e^TfWVj6Cgvhw|?`I+-*4vi~2+z&#1$0a`@6{VJztil5Et
zk^6+8h0AN6m#-n@6O#NM$tQGLkX8A<%vZrXz@sgN&E8_1D16Bp{?E5Kj9p>uaV{s9
ziR!(sOTbfdY4V|Sp|LFAu+CTD&0hbmcn$g3$UaSWS>Sh+X=F3py^+@$FUKlpevg7Y
zo4kG4<p<f6ZM!{bOkcn7(7K6-Sw}5DwC*;-!YjvhFJ*L&jXdqcYQAgMki*pBWatda
zD9!2sGy3IvGw|W0>zN<8YkY5M*1lEF@gCL#*4JN55^H~gIU+9y+%Yh1jB4#SSFlY9
zYyW#tcessB3()f>@TQ!d3w8ft!1EqkN7=ls{I>J6?eZsD`Tt94d+=R!N;%5g+;05!
zIP*i0TaS0S6DaS~FkU8SvM=X2ANAeSOGaDCp3=}6N*mg5ihHih%!wIuVuLx62i{ES
zJXWLZ|9g32K?gq(TdJdeF;~e(A#8nB8htYxMQQ4fmouK$3N{L1v#;;horMMaB*vL%
z<u^BZp{&^_<k_6X+u+jHP+heZ(?;sYZ++Wkw^h`BCBZ%{C0e%_ye@pXBnvnzT%7*}
zTWP?}=l_`Y`jPoxd*8}i^?B68?Rr=vS>8Ny-l7bT*-5;I>?DgrzgodgBCPd+*-7M^
zokUu0Cl&K8-R+~=h<!w!{U@P=JlwQ>ygcke9`+&+Gspvv$-{E^W~;G)z1Aot*Y?+t
zjX8Kv8{xZN;Td$-Yy&;T9CQoyQfQ(2@)wz|ro8c%xB49GRQb+c<#qmju^Z|tEV%$i
zqVJKfZv{Bo7nN?&c)JCg@HW!1i}b%q+F%cZJd;zENlRWvw$?rPD((qBTFI=zfInsK
zZie0tXIA&AZk`TpYu#vm72ZcJ$CN!xj+X;2Lvmb9E6TCjO2ChId%@*cX+=3!-7Yvv
zj$^ne$1$xa$1!c394jx%v4?XxR$Ox2;mu=m%zH?VEgo=|+?u^#F32(YCdZ`Za$L-}
zbmov{+GtC+g!v(x4!SqWiOCl7A=yc9cxz(kB^9oF`6y>|E@!-@Yh(TDa~_<&7WvT`
zj9Xgd)g%}HhrIWJlj^MR{m;w}Fc2UMEV!^F3`<0U>4y9%5<z!FjYuQX+}zu=S>>3H
z5jBmJi*#DCJ6Y+5D!-Ocep@POn2=;0(@IE+xfp17M5UISZizR>)a2e>lQbD^YG|rk
zFIh78{rNuU%$%8>g{0ow-|P3f`(ilfJm-17&-eL0-+#~d`JQv`Y0Z1^9M|H_dpLf5
z!12Sa<WNU>W5YlC@TB{u&A97(#;-W^xH4D2o<?phHdU{CyB#eGWsdw#F-Gx^y`v=5
zpUk=G&hVP~uIN+RjNwDd&bOW_fzP<OZ$Mw<(HAN71wXBCd54y>JDh7B6XKiQ$UMn6
zV=hD8XTH+_^}*Zn4Rroio#Q*{{FCGOPB%N>$^4NtJW+-w>m{R+oQlxKy$p_ZImePE
zizTTYzsJ+TyIeRIJyaI*h+<tIMh9FmEcn>da#gP$>ZUC`bBbdI-$wq4<)XZ@Tsi)p
z<t73v)cFpk8=H75=wpZBz;&n(bTrz~_VKWsxwQM(N3GjV<(gc~?w4Hb&f<B|@<>dt
ze$8b#E{)(gfDe@8+b3aPnvW2N`g;{TuCN@aVp@8>$;NQpomak5<Y0I^^sXS;P>27F
z#N*ws-65J~i?J4aufoJ%O!~~Do%jA?vXG9oksr7Zd2TaYuZ`eZc5`R^5}Z5!fv(}T
z@eqC_^uR9E`|_5nVsO{h!A)r__-lg0c@11$N8zT<0r$tXaP7TK=z($LU-faKPU1xP
zVd7Ig>tlSr7(Q3rD!iV^^)<xYHo>nP6=zUxO?Ewgh^~F~&Jeukanv>6Xv4O<^G&g&
zKZW-66Z=49eJsCyfHtbnu?B{&)oyhVJJ<WNx~W@6e_jGC&Se)eT4U=Rd9=M8JEz}H
zc;Ld1*fS`Wt4n@=HW_?-i2M-dO5?pld#@HJW$)GS0GDjet#izWVvM1lw{K_(K4TXy
znm5T+funH9-ZbiRAOc(!2Q}Odftw%Tc_>0B+UQw0s}sT$oDY)wI|R(2Z`04fY^ZOB
z&^IY`ViBFlPdd?PnPPqh#E-<?bwqx<X2}P+*YI5!`u1h$r1*i>CiJcHO59vHmxFl8
zJ0m)<CBQkySO&l|C*IdSguO=`JcIQH@a$egJf5?8GhazCQoy3V`SZFKKj~UWT@MG>
zI&ytV@e=M^+(h^D!TsRakXDyNt6)!1&#u_MAnTPyW%o?9*$d^Ah{wZq{VC41PD*)8
z!ZoJo)nt45k=*$ijy^V5pO36#KF>Nv?The9Cr5+jWan|Oflg)4E9DWLy5$Jt6HdZ!
zSp+|1$l_VQ@8Zg;WBcAkhqvJx=7p_|;I%dy<8nL@jdNLU*t?i#aIV;dsGg3NS9C4U
z`wj(T918Mxs2A9sWY-sDYk7Yk{E|HqjA6X-eEk2wcs2*)NeAEO0yne25gfz4row*4
z!SBNt$j7POOHuxyzT;(id<pa)?R9PIopa66*ZvQTN&D@Q{?SL4hnRxT3NN3XbZ<BM
z@)U83ZoP9e#XGy4&nX>dyz%$=Oau7J+?Ou9m*Y3OvG)rU(=WH)`iJg)JmWrVQMZOG
z>_`9X5BR<8XsGz8bW6p~ebPr?aGi2CuM+<b%iyQV`Zp~5xbrQ;9Jg!%x(D~P=cBR2
zBeB=)%HSPo<HdEsGs^FlS8!v_`F1I%OU$NRRqbbz{NGvdt@Rt!!A51i5!MOHPE+>T
zx-!;unLnkhn{g}lrsFckuRJ_GPyd04JhTSq$_FTf{h8lWL$?~=!F+|lClOsgIgT&;
z-iV%h<xkza{SO7S`eH;sd@-UQ>S$##@P7&H^3q6~rRX|n<9syUg$zGsZ)^<PXjp^}
z`=JB;Vfl%{c>(*JYI=8$I?U@SY!>@r_us{yo9FUa8{zX^<bb}-jsVB@G6ip#^&GMZ
z9O68D>q={cPRjY|8!x7>Unh^)xPL#=kKn9ljt)fTT4myi)seFOlxd7AUq!jDJJFAR
zF#Z(x_G6=c_AkO1B=^aQXx*~W`T6IiSFY)G)5~I)XWTe6SJ*#v!LZGp#eK@JW1Y4^
zHUquLTv!b7J1)key)^lqT7%m$7sOtGIp)22(K2LSYsZI%sK;-aH^bg#{rC{?ki$MN
zD*u4zJdqP}GAniv-m2K?QXnVAh@5a<S?kf4Y;a}07haDiC!cn5VmV!*{d{|b*WVuG
zyZ%n3?03eO8PhMUIRr0uq4wJvtR45`pG4xL6<-d#O@DS*ZRx}v$kw+RbEIs#%JQ{k
zQ`b<2j}Wb=c{88kpWGOY9~OZduoTyle`WF$+OqAm*SYjj*1>XXFV-&BMl?tF1m}+C
z<duZirkmjLZuz5Q)-kpDub&O*9{Mq9`Ws*k%p3@w>zD6BdE}%&<+aYzvFNqhdn-11
zNxc(wLXNT{UhBLRW4|Pj@gGIz=||`(V8*|F%;E)FPnaHPP$%~Cd{^hG@#{48+~?}B
zUpgL~`1LoqIxN%2tE1fHLRoT^GhH@e0DGhHQ|7-tm><SucIZks4`xF@=|fxQj(ehg
z#h!*`$X3OkhGieGwWk?<PtESR`LF1!>l&1wh7Yc8P%aynp?m;beChNEEZzGV_d=dJ
z4gMidEpuZD=eEM1v(C*6A+J{KN6@eA2l*K}##3WIjP4Ia_~3zvyuuIl{=n;%QRP_R
z_u4a28hb{*w{Y>`KjzQY(>$9O|6}s~hWOrDj&i?RM|-;!|D{YjezsoJc{=z;8RvR0
zhQ0+sZb$96i|H@^uX+xe{n`8AlcAuGRM-dep!Ud$j%It15uLYt<h%h__ONtyP%j@`
zm$6YQ(>?9^3+Le6)_cKwUwm}DJ&OoDjX9I1UKx5mbYDz(sh@_ltdHk)j^1JLp-*9e
zJwDM({Xv68W%htLui#2q_K9G8S5u!p+<R5gG1PPKx~8qhGC(`VVfi-H(>rY}c9Dl4
zscUs8C$?D01yLQr6z<tyVLd*;c}RocTyX>C92L6V-hk1dlX_l21MbJC@f;{eeOuGb
zQ4YJ<K=*f|`@=PSH}RMO;xXzc92<H=xCplN=$P**MDcwv@+_Z6Tp$<Z#17C$npi<j
zWyA`~(EH;-9u>#RoT?vwg%?!DcXQ}d?-{Xp*#(i<*%y8h-af=!2Qh+Q3gneG4aeA^
zf2~&vKb&wu(<RUee44(yI>uV#GX?P0dsXwlnz*1am*1a6zHJyC)BakUi3}t}y8^MD
z0`J7jcMBJ{w>(B}*26#2K{@8j#z%hFQMX1@n=n6D@3uAC4<HXYCnF|9X?I>^KJwx-
z#%+0{#o$~ywJFa3o*Xakh4NSUd&}9Vz;8&aA;wh~*9phLyiF<r!}zXQb^)FrKxdG<
zAst>29vsChs-tszM|J3n={n_NT;Vvwckx(GPS~~#Ul#>GfJL8*&x@DCb`5c_UlT4+
z&K}=S?F8=yz$${*5J!zceOy`P?ZO7iDJ$mXQ!p>X(j~fvjzgjSCvL*M>`RQ7dx|k-
z@~$3nE*CpXaerrUKOMQB4(=DFKZ5(5+q><$q2bSf!%;Y9R&WmPmXoueGJg7YdN}s5
zp3y&rU&9(h{+;QBfhynG+%S&u)-OJOp~*p~8+)M}n&ijvqc;TeTV@VFfL@}m<$rNB
zoOhfDKgQDtKYiOV#6kO03(4gu3<P_xbvD!K*Q#G7-7MQ$Fu!UX+1~&^=WF+FWH&_{
zY*2C`KEC{W@q@uHy7{!dILa!t<J;bvbM1pM4-Mm%79Z<`K9cWlN0*fNhjWWJsw~C2
zP<aI^OSyXud3gZ5>vU!XmvXJoFmAlvV4!o;=-h5}?q1|b-zaBa*~SYF(ytm<YAAd!
zZ$QVWu3G>u!@%KJfX}oSZ8nEEz2Nv=fgJhp?qd#~)~6<G+%G|A@vz0khd3%GPR^b7
zB=wFnbmk<zV^4Ax<|x$olPZt;lDZE3Na;hHzYX-mPx|!h11_d?4@b@Ehc6%|!O`aT
zW9+$8{ta}ha&2^eFF(<s(5>>blUkb@2fm^Fi_j-d;d>g*YVv09u|29=o6ZLB%Fdb2
z5)RsjusPlpnd2x;8|>GG?+7aFFPq-7HCuD_{VNrp?yb-Y+E=bG;JTBsr|EZyIekyC
zk3gBxQ^%-(uIng0b#3&VVYwY|bPmFNA6wgf%-Le|3IC(R(|BYt=Vj>Z1wK$1N81p@
zBSbIm+uqH7C!2PigMMl!o2J;i&WC6tA7AIpqx*&-JoKCN(d~FZM?KS#IUevMylHDx
z+Gw6_Zkn0nXJ`ZL@SQNlPw@N=b%=+U-ywM~e&Pezgr<aa|E)hkchf$U8^Q8#2*y^^
z1~}@crmPAle7BsnzwwQ?&mIbF$S%iU$}Q9S1>Mvd|D^Juh8=w<4}CWErLmopmp|^_
zpO$HXZqzSOzn;$KgGi<auu<$sNRO(Hd=y*jOwl_ZT>t1WyN9m!Ob1fW&Qp={ygRpN
ziTvO^obOJ2j1BPTg&%ReDcv#5ykWbH$96c{=~*Df4$N<$4}4GeJ?|)AQ6A+T!{e0e
zub~b$y@&1a(S7{zBP#FlGW`c$mV1ia5i@Z<%La6FD6>%+y&612efgeXzNIhsLgxW^
zHpNl+Z9+ca=}Mg01HaC(<7W<Y%r`QHudjE7bvvDBb9{~bXJD|-C|r}cKs2e3iJg-N
z+8hrwq{-W`1>c4yYoH0g!UwS{9|Z4WpznvOv7&HKLo}BhnUA%hn$sbjRM~%zmZO{8
z9y)e;Kd=Qq1syow@=f?YT+5fBna=q}wD}@dkJwNY*6Zjam6q(-o|=0W`f{hkjF<Z(
z>-K))H;gy-^fC7igZJm$_nC6;-43=d^9gVQ&nrD}(wuI9f4SE9^B&j2aTr?t9mgS!
zi}TCLw|a1NQhO@q9e9wk0RM+L=N)V0EVy^L*mD4qEAHF#55UEDB5#A3iejShUihql
zzJa5B1lfp1_&B;&JA3a#u8G`*U?1s*2tBjl7t-@7y#wO4JAmQl7o08s;e){8+~y8_
zSo$F28^#BHYmf&oerS*fZ?>VkL0pCUmG?)Si`FlR*6{k@9<x|Rk#S2Ohdib^l;2q4
z70$b6{h(FX=4T1-B0QvW<;$sD*C8+cEHd^L)p??i9pRk0F_Qxl(%`LbU$H_1a;b$Q
z+g{tR;@c&9R_bvtzUQj)YkLaC_`c|K0eVi*XtM0Edxywx2fmbSX1N-(4%Z>}oYn@)
zHE#CDBp=x?Gk4TI#n^Qn);*PGT-0@WE<xQZTwU>7WzCYJUNDyIN4P%(jkq7$e>+Eh
zDsjE=e$;me%gleMz6&CIIOxx3US0-nnP0vsdAY~;A^bl{X7A&^%8THGzY?AoJ_T>H
zUent5@lNiOdrS=5=2<di{zERn8`#PN8MmHCy#PPGn?m&@FAo`9N8`sk-8af^eG5L^
z%sM?8wEf>f4_hObgYo7Wubo%%%eDmHQ$G>WHz&|Hs+WgGha&5%pv>}q*t@ayA97T`
zzLJepjNRm702?zLtewV@Gs%YkXg~v$mD!92w!_x<!hv6QX^=CL3gW|S7~2r{Lf&GI
zZ2xIl$Y0gDE1hOseuHviw%Ik5hqCDdGt^7PAn#z~VSDE9TsqqJKK39_A)M0@IQaLb
z58(&1HR0aGkw6}4WBCke>IFKgqJK<gBID3IPE^KN3&eo&MRL&K4(6q@hiG^%j?C@i
zsx1+o4Q*}YJxO{$l44BwRV@X+S9l27;kxw@@?zubftELd>w}`bx8~HR(Azp6mYzgs
z1?LsL{a~Hmez2;yPw}nOdVR%M;-;@Iar99v!k(KD+#+k*Zq~G%n@$bN%oovliu>t6
zKM&Ba>WM$#w~C$QT=9&Go#fhl$nGGYljA9Lfqgez=Pw8EFX|3#g8E^s=8tKfb?w7P
z@VxRBON>u;JB*<$)bmu&!W%(7Td$VkfB4?YfTeYQOy3BkT)bXbz%l4Yeo1~qV6!(+
z-VIJUm*0`1-WZ$BeY4pEq0P=an+^V<%?`(F^{5~2TiRNKYx%2oPdF46M_|p~$+>=I
z)<H#RYWQ)aOf)vWyCuSRx4?JNIe3ugZd2@U>peF^qInR1wDSh>;%@xE9KIhv;(>RF
zF426-(C@F5VJo!18kXDq(I%SP6W*(o)wQv_aP<RyO;)i<VVg=>T^q{*RzD5eRLbhw
zh_;njil;FK@$1N#Pkqfj)6sJE?bsgpjQ8YSRsNsJLzLItLr>{CMLpfCd>`|4Xy2Rc
ze#Mrf2UTD8DOx{_Kh)@4o*Qs=o2aYrcr#B?d^a#h<Hfwv;_Km>xK}l<gukivWT*Jx
z9C5BB<ED<D8Q`4<l~|JbSJ2%2tL{J-a5P(>@>xG{abn3n<qdUS8Qd9*ecOz9RqAEs
z2-J;lfI2^KY-|BAh9he`{5IJG)8PXgbzWp_ogDeq`<oVbf<}@V*}L%mM8<}^woXW)
zd#12XeKOd0J@`+=Ih{Nf4)VO}0PVs(mer0YG{>1|plz9Z)Ga;99*Ooxbqy}rKM(Bp
z=Yt#oJrlcL{#vt>^YFUjv&~4D{D<Z6yW5YgEC0C3D7J<9vA!M5%6SA{r7QxgQdWU;
zPwT>E!J38lyI0}^MaI+@Jm<tQ8egl~_j<=D`v)%H*6_bALc80b-4OK1X`S3)|ME~k
zKj@W_d@>&Px2#{*LCFIB8q6O@VE*`J*B^Ttc5h+i-olq{{Ulo^S**wk{1V-_9haZ?
z!)HExmPeoP)B9iyfAAAbwF`MCT+4)ZF!bAW|K3hwll&%#zc!J7pri5+Qt*WjpDiK(
zAWzw_*E%Ur*)GbYYv?cDvd!fHeA``nrQn+THr~IAjQ6jgMH$+Mw74^J@6Lc0<vLo>
zM-46PegoSv9xePphYUGBf4y{Z`M(h!fIgB{+e^`T5gyp+c%XP#eh}Art_P|#pCDSb
zQbzrHK2cdd70BHGh|uAGyqr{SqtWi2k@9y^j{jigKZun7;AM1JzOj$@zgZ6*_uM#@
zbFOhBdtUx9a;G>L*M%*CPjGPrzl&c^E?gG#9x9t};vL`^#^Xg}Ju7Nsx;xV5?w4)f
z#_IaPm_Ho3|KXRD2jC;|dWci>IU@CSoS*i!gqP{UZu(8aqZ~~a!o%)7(1qB@$7y4+
zj&At6eOs)eL)3=340$K}TfB>Rjrg5%#!#axRF|K4VGO)*{yq{J%SX;Jf1Sv85&2Fd
z-~8kgG1o16X2$elk>^eDYi}(^^!R+nRpvhT%(si^M5FWn5A?gnq;;o!WPLv)s^gsx
zm21rJL(nS)t@tUP8rs%S_sOTd7utP8^Ro>)b>fp~UZIyipZVly`f@myJV2e}{3d!%
z?<J)Fn!VO+!tE*E!#&BJo@K_b@^o#_Qk0Q{0qC!vCtK$`9@Kfo)_ug~6RGU|q1}v>
zeOxy4BdwR^?)Ma57kqth)B4-t@T4p$Tou1?xa7RAgM)l^`Bxf~a-LPz#k;4%ac6&h
zoIDESHE36acJROQ4IV<q#KRw&?3;`VZfUynFKpi**jZxvswa6ETetdNjj{KtaQuX8
zt1&%9e~&YU(hCzV(0euX4QjO=b5A@!0IfZ2QL<6rRrujtSgsFkG%xaPWDB!zq7To-
zBgXiGe+NG;L;g-dll44Xq2tTYhWBk0SSQPmC@eq^eF~UG_^6X3=P8{Jan5yiiI+@m
z^jvO}?yD>f58cR|?#?+K(#iS?KGQvoM@Q4GIaj9h1Ht)2IqtvAdTrorat>wL6}j4X
z*d{(?@36h}O}w*~U-FNO&F%b}zgKLw^&4X^Yyb~_rXPYn_1;RYElvMzARpq%Z87CF
zWQz31(cWdkxxS|@J?N*weFOK)y3c%d3U~HMhTu=uiQ%)Ud2sY!4$GYVm<A5&dtp9+
z^{?T5H(rg^{}orJwXkB`6<G?;qp}p1MP(^0Gg+#}4m0pgrQa{mhw9~G$rNJ<b<TOm
z{teH2XaJty2;U9Rp80DSM_d4n6+;}a4)hAgmf7X%8J}Byx4wLQAc!G;DY6gTS$j|W
zeW?`zEw6Dn*>k;`uS8J(@nEcs^YMYvx1@5m$K!PD4XYHpfbVP^G3iUwAs(@(x-!j!
z=1%-;d=LX}fRAvuwKLaR@A`NDJIvw4bI+mS8uIJ|!MrISU;(^~4>0cBfWPYeZ=1ir
z9)JFLhO@OIS67eEQx-ECT@@3~A)lD;gGW@RHHh-^$P<-LU~ZpFu+}3VP-T@kcS3R+
zg%QqQh1c{xqfW<Tf>|@CDbHI}3g$lN^rq?>U!d!BUPPYc4_l7iX;&7$AIQqqyRtA=
zVtJ!OfsDh4%EgjzWxB8%eOfMmjD2+Xy(JGlTnu6-=HFtohSAGI=w<dq&=+p4U37L`
za3-YT*%EznK1t`=6X1NF&JT0GpT4^3zZ~d0jv=4RmlGZqy9>(0XI(@`v&lys51QSl
zj(rnyAkg8|@u8Xd7UC(&_5K5Er!~}m;CH&dtsUp4`y=g+s~zQ)cF<jOFvech`-|Q9
zK;4Xqc`+N!x<a;8b}zyYw(n8lE$$m{S-n8dlmi{ax1~$Kbh&cl_+Z`G%p5k;b8!}n
z>uz!J^h*4T`z7wD!sp9B)BTyk_RqaqNaS8k@hiM<+Z_wv)NOeashhr<TsZ9I>Yu~p
zn)Px#x6t!)-akB1`F5+tXwA1L_BnJldM)_Y%wv!2DFIi{leg1GIhl;pE4=vGNvRjR
z^}YkIKzyBV&$LQ6+B39_wW<B;%Db-&_AvaS@+j=CDs1R#&#IBjG^xEf!P9efva6|-
z>04{-{S<r$m<N6a(~rUoo@2P##lp!Q$)z6t>P~ysdP=n)qwB-e`Nn9h@TJe%w>e55
z;(6kaF`h3mo^)h9#b7`G^^Rv=wV(KZem-V6^pAr>|Gy&+bH>48&c6>1n%jHd^4Up?
z-qI}@sqo9f^c$q_lU4c(P9vC$-YCqAt1yiRFF%X?koz0X4?dakqm{!`;e6gxZD+BW
zkD!xwDvri?-gZv9KysK$X&*3<qe~yrdl_0|`&P%?J?N0***4$?^5ZQWcD{wl$*)%B
zXH#>O&jWa0uJ*5ZrqQ*5OfJkXd}A{CwJKcuPSIaE|J=XK^N>Za@YkQ6B;HP4$oM$7
zF<e+3L(01yokQ-c^xY34V^~%lgV~ZsWBPxqefzgUPvm^l#+X<7L;2U?H_CP;AE&>o
zWMA=Rb!0ECTK4`hPvs-6sSCj`&`r{VrVIX`Y9AJV={!5>);~Jidhc7djpffbO1q09
zu*=RKXgw(#c7cb@{IS-MIo>q^f4xo})c!_w(4q(qnu8asb1<$R{zA2l?CW{=0Df=M
z1<K7UeDQ<sIe;&IAX)f5_EWwUlwTW^f1UDgDZf2{Dccq9-wa^y(z0dvAZ2`zZp926
z)HA!NcCKE<7Di#6CvWqzX85+7dDxFlmmT7$wM!;dJ-7UypbkD$rH=L<6bCT7vw`*6
z5WG0w#R+WBt}NbUeUERjCB@pBqxja^aL?*=lOvVq9@lS!U$u_axsK+~B%D7ZoF32P
z15#%N-+)c=vu~g8cld_>VfgO!c~8Mpk|W&*XN}WvDce4``Lr>;^E$Y%K5ajNYxZjJ
z<;b~)_U@am4PwJX%ux#3^9$z)I`BM&y)VOP*bt|1T)P-or^8KoiSntSo!ir(+;A8W
zPIY@po%CCzUw+YkUk`sc8k_?jcmUJInM4En7u_rK433quVHfMTH63eJzLu|?(4hX9
zc{;>A1os-!Bp=*QSKhtj_UP1xGT9BaH=2|i&}57pG?110XDv1`*8TYQ3tY@aGMjqe
zS6xol0{WsKdq#|-#qU^qguFFl6TG#_@oD|N$)~tC-1uIb?iGXQgTD9Gq<<+iYXE<4
zP)|I8?Q$_<>e)HRMs2cx=ALobRKzCGE}4t;^(p$&x_N;cm-ssVANjUlC$RV>$wxG~
z8(_>MjxX~=oEIH_=jzvR<s0|HsZy_7F;3UNaG9%f`2N5U@eQq$BmMuI`{=C0yT{>u
zV2Cl%r>zO;^Pc~ceO}`FyhnXT#x#bek`3^^mwH8hTE~XGv@r#*?8lc+lm82!Yo8{p
z(=rvhh4)jzea(sL`|et~s*0I~>&Axm$#fO#r%-PUpl=3(e7>(gw%z;G>KOSj`o6E$
zN4eD3|8{2>w`%&E(O9UHeb$H-JyXBls*^$S!&Sv#z0CQHbifas>)X42nsIQx=#b(&
zbvkJQI&K(zee@i^XdbiZX#7+l208%F-Ozr>bh?W>fo}o0f-O1J{Z!6;N6R;r&NsW_
z2k*7=KAkK)W_!HB_XGmnQ9r(VoS<RldDac+{DA<kB=gxx|M0xSL+iRsu$JWfCVi82
z*mAkd?qS=t=czf6{X8d)JEi-fOB%ZHD|9=%5$3KKT^O_YKcs>5cjzCU6ZVkoS%gP`
zt$4l0MeN55^Oz*#^*V2Y^p(a<zpN7)-#4F@`EGFEbjW(z)0g2*-&%tjoywHu(El7m
zJjUfgqfcNPL;S(1hCa(8^r645%J(ydt$*#EMDu@?%hS-W+7G=#{@lPkY;d@zhB$We
z>mHq?crG!dN&Zg9>-BWAam$W$!!Mm~k45n^#bnf0<)%}0pP%XUr>H*!pR_cFnMAg-
zYp7Em$8Mc+@yR!*gScvgdh(N4dx3+Kql#W{P&fNW&hFIXZ@yr?T-W=e`{6O@6uv7o
zq))iFW_hpsi5I~$;hM&HB3c%iFXhY1x72=*bYwj|y*tEW&_mqkcPi!b-xR-En1db>
zUZ|8s;H%A{6zeJKTOJ^Dr+i#pn{OGy?{@R0{_h=d=XuZV-HMhEQD3l>gQ&Ktv~uF}
z@R@raCd{upMB7vF!{Zy|n-k05P@eQwe61|L^eOI1FU$8*J;Bp`;rATZnWEz>JvSzP
zQvHUu;d1ymc-NP`=WD?22Sewn1@zjXPPHR%6Zn?537za+JHX?;I%_1ew$@bMxz69J
z9CPwFb^ggz^3)LTNa{pB((yaS&Cwj*VmamLDa+9mPgL^H5{}Oc-Sl5}u|vTWKV*65
zi^`NweyTGl+u_P=uUfLjedTl7Gb-$x*ckGR0s7clbK@4v%T?ccj@fL(pSwP*IviSm
zW;DsWcWd7#upaoz)fG)bc-aQ<wgV6RZB50|avzx!Kd^y?-`4Xl=nT){tMOUhBxM@c
zp|sO~*l#zU0rvKoXB*oF&hx>!o<Z{6IX<(eoWgKis@rh>>-9eKuer;l=?lEXW6DSM
zGqU{+=BHV-a_hP<XFQy%8v5ZQI{T9|yDz^+a6|m;odezUo2Os;FL{iEYx9YU^kHS#
zRM83?&--k3{kXcFJ!8MMb`BXId#j$G)Hvu@v`q)}?B<;3;Z&ZA;ctnyvWaE<=f`fa
zXP9g*jn3ov4Q7+Z+H5`RS5SZa3OUUyFt0ldOpaFzb~wgd<Cw#P$nARI?!w;jD{NqV
z`@wAkFa>*nqt1~H*(1g3b^Z9T)1_L6*!>i|3k??Lp+O%s*v}l?#XXL;|2)J|Kk>Nu
zJve9HEZ5ldad@A#p!S^n9|4Cl>22vc={V&$nOqM5i#{bY_Prrpr;%T-CDSHLDf$WO
zUExs={Lq^&PBA20cz0=;qvogjty|X4hoBYDm~}$C--yRFF709ZkAcqy>JP!Exu#ah
zPRNUblYO54Ivs7a)?{q#RUw1J-d^D}m3QyivzS30l}&%&LYE6eS<3sI_s}rB5xFm&
zXtarz1-3*qakO`~g!yla#NukkVBfdjAQ}oEx5v{^j_cRAL-50ffFFwRKzGn5v~Ec`
zn%bN%hBn*_eWWn9G9jS*LiS|+@4Gso9k%(<JhS(yw&D%FBTRFy{ZHeO_3(>dJ+JI<
z<)A$}!}#PtwY|mPG|z%NN;$B^C)v}$2>M7dC*iup-cL3_9ex#jcG6B|^ex%)r8kBg
z9FsMjr<td2j_{C<ZcMN3P`yw#!ude9?|`T5o1@~18lKu%g>8A&k@k`;<3r}4X=2>`
zdeajr`lg=6!Ni9}hs)!hD?c=Rj`<xx-qXl?4teKSD5Iy#=nneQ@zAh4O7<V;CmuB)
z1)7>}`F<Q-JB}_HM^}oL#OXcLhn$-}pf6(GIU651*t49Jg}%AblyL|r`OZ4pc!~GR
zkN@|=;Z!3Wis!+>bSm^+U)87P2ffVtE*G10XaTnPQ_vj$<kSMjH-y}9eTXCL8u#4N
z2F8o*6w2`5EAR+M@m0lVi3k1(bENz~$yw$Yy0H`eOkMGO<`i@GGJKul*cq$=IQr`y
zJo9IGo+RVPT1~f6SN=z|uE8n-D@pnO2Cz;Cu&5)yIGYW8sbTnM$oWzRU-25+kAV+9
zR>n66jnC8%@+qF#w8_CLbTc066)01A23hup<wxW^?S0!38MR~19Sv{K(a-#f4dDLi
zNS;HtlXvl%z2BJoqPKWVesSr42Km|?{incvLU7GdZNj={2jE95%enUW9If&<OgHOD
z{mM1)?OZT6nB8%0gTBSvsy`-{(T&{J%j}yK_s=ozy0}M~x?b=sfz_$IU#9~~ADwW)
zg~XDi|IBaQ<aw!lt$$<RpL%cbt^$pz%$VK_Eof`&I*ux9XjArskB`pDBNP0T4^jFD
zU=6AMJ*{u$`JOG<eCvBVedmw?VA-)7I&rRf*^*>lxVHF2vzNS_HH&ycG%%a2bG@_B
zhd<y4=NINZf0=lKqxfFB^j&)@F-!BMBe)d)fpK(>GmcKi5sjOmx3s4s{4&r^`qA=3
z1g{$y+S34DWsY)nxdruf=>*=8<#l`Ur{l3jr}=&+WlgWHj!8x;<M|Ndpgfi!_DVnM
zD|0>l4^`KyVO+572=ls&d(?S6ANWS-4C#c0`$u!?$7plE=XsOjmA!x6PYp%xe~mr|
z+&qLlTJqro%1o~}=zCr({j7I=EB0^uLf~QTbOaCED>(-Y!+(c^!Mj+TEHU@tc$V;v
zMDve;_fX!+&f^>x!W-g+ntSx4ecVQLny>;~*8unTg6EMBQLhY+l4<5d^bVghH64_u
zuHeZ>RXyalpd-KRAG&8l!?-~>7uLs2+RYB+t)9m1z|wr*l#WeL1#>hInS)ixM!4?i
zrZ0YD=IODzdGtjq$Cowpxre^K<@hwzN7_deZYIwhB?t9mm~;xfG!G5#wU)S7boUGf
zb%Y~wOnvvfg2g9Q*4E_Nd=02hpa(gZ+%AgnWkY>3gdC>OCq?uLKkTT*7~6BaOZ^G*
zvj&(i%3=%P=Q4JW^4P7EbKVf%0^kh;&j%hqTLUR}@ZNwInxPfCTJ2x=+BB%2{X9Br
z17m~+g#nKIGV`I4&etOo;^pAH&`FtoY3Q}V@tZ%DzPVqK-2`oThmf_=Giz!qIYQS=
z)&9#jgL^*p$Oo_7SMJ)2&|`@D{KEHdgfi@8(cT5Y^YG9v_>OPo{w~Rxiz~(c4qsIL
z4l!?m4$%8vRHpaX_~|-Z+)aOZa4FNqb22KP(_FhUXalV)`tzd`E>Lb?fn(IBH=Mfx
z<}O|9&sO-L4BzkUiG}k&t{y%I42$iwxL8aTPTtwv+<El*0DKAGLv#1edyQW-f*#tR
zk!)z4Sb+cKqbR;sFK=_<h4B4aMw3op@Y}>bwC2fMfek2A#?RJ1ygM;mlL~&`b9A?R
zl1=qBz<gkDb#!&d8Bb@Oz3XN?TK{t#({I|Xt<MS1=!}e|oy=C`YgfPr$cXUMa|Id?
z{!YL%5#4I<TFj00dFt1#3j$m@N}oy}S*+oYpjRjKTHtiL^ihRhIs=<J#C?9s{S4>a
z?CpP89aEgtKLft11I)q(@Em|9-$GY(Lr>`n(U|*{_X7@4mwQ%UM}A}84>;`Xd&B;Y
z2mMK3$d(TQgY&|Ej`|`075h{Mhm5OV(HYzycPv-e)s=pc%~l^i=iueekz1ARs?!6M
zRr=98XY<s@b{Mb9h738|Bfc>|Z2-EYsKe3xU+Dq#g><CZAL_?mKxRFB!27X9q3+h)
zK!5Q?Lp@MG|G)`zZuR~7${a5MpQZRy4}-%3aDeAzL&JW|7upRz!9CN_T9ZVsHP1Gm
zMd%J}=HL#!^F(6}eS{F6$=IJq;6c+d{T=51et2dBV+-?M)L$B!hyBvd{K-zrJEbo~
zhkIJ>`37PD=-<{YK5`S*mp-PhwV|$+r@^-z<gI|K>3G#wKh!Z_jBELG75p`>GIh(#
zVm|shEEk;`&cg@M8Hdov%aC(^HP5764y`VC^tV_`ni$PK#(p_C<iHJ{wr_z%t_#9l
zzZCb?o@ZP1P1zF9x)`myxyR3ct_r8Jj(K;rtS~@5eidGoOo&(MYvF$0(Uo#B6aOo;
z;e88wPQ>P-lXm<nFu%%u!D2qL$7s(z-cLXt(M9HOrg)EfVTk+CSN7KYPwH3fq}m1j
z@;=0BzdsD%4q;P6yUsl0mpEC`d0=DBCeyFY7x-(w+}P^;UiuAvERDP3E7zAJ^C6yL
zeT|Q?L1*W;8LvPS|B-;EL7%E;Jhp)`Z-8!w7koLux!$L*=eQ%~V`#OXcKaQz3JW;r
z*N{Gnfedip59q=CDeqHpJiRkC^j9kLD?K*M{6yQ->n`0}5b<I5S7~qbYDgFQ-%v+;
z=D>WmdU{zo^*ih8N9bX6lI-TAbozmNek`2t;2844nDq_g2<NTgJTq?%WpzKY>LaUp
zWR+j&M;91JVJM<AIX7MyK<>J+r}y`~KEJvi{y^0qk{)rsdZ3Scg1O4o>PNG;$AY=%
zp6Q6w)w*T}%g|rHJoks-*-r4JuTVdPI?MFL4Zs=-@`?@thjWWjYmLb{@3?n7qrSvz
zox$7<I62d^j>c2s|N48&B6x;;Dmcx0R!MMzyu1LG>|uzT*`0`f)wmnZ*${J<V$O=p
z89#iFs%_)kY}?N27^1euXenDm{}p{J8bq!u`ql^U@o2arLW8ia&ltmVlg)b)S?p0b
zzUV#0V`|Dp%djo|N}u=<TC`&)UN0?#v(exu)p1F8+t{zJ8~d(m9pj^J=%U|nb?o-s
zYy`Ioti7*~2DcVnUZd!0zM){Hm5V5Pp>NXO-q7a{X)k|Bv7T{xpmVHWE_#|gb)yTH
zxivwB#`OLA>35DbKe&guhA|CW^Y0ZMiQ&IQzuk_87E5VRzY;%aaL-`*ZcZ$IKppc9
zfmz_(;$ieNCLXqfxsd-|rv53;IV$F$^{V0Zo@LeCGvD2>iP!vH<hkSeHQo7Wtr#5r
zotM`2x^RdXD8Km5=N-*13-Ir9_}Tb@tFhG6+-S%?c%yrnm*DkN#0|@iPK8cj@H4->
zGw>S~mmGjr!|KbekL((m6aQP^9Cbc!-?W$g)w}4;CUmckS)7q_t!3q#iY_MC-N7~R
zG@qvH_PBA@!?$<{_3F#Be;HZV0(Z>)C7z2X(Dq#TClsR+?Hcr9bmbjGy7zBd$7=1z
z*wtQZSn%-tM*K$q75~{okB9mC=ixQ!wb#XK1L%kJIbtGO|KNj0c~<_l&-{mF<LaJ&
z1MEVIxnbTz*bQ}2H#p}+3v8NV4CO#)Md@R87#C&so}}k_Pf!tk!BMtebCz1Im=XIO
z^>X|&@coFd(}^!KL~JG<BcG^A{>`L~(mfn6DY|zcr*8ZJ^Mow|uI9`58N4!2P;ZFm
zH9hC6=sbbGQC!r|I=<GL>N0OK-%;Wj8sgCYH^GfPF3Fi>f;lH12(JL6&@GwaN1H_h
zKV=>95f}g9+LcR}4I5uBOHZ!JE0phV@`T=tJ-OP}8w>NSoxLERK3^?wUs5fvp;0P$
zW_1V}rD}bP(t85Ev@;x+aN#*2Vk%L*#q%~+=v6P9VZM4;$J%Mkj9>JvuWxeL42{oG
z$MzMBX4q=eFNg4%gSE<kLl>oK&wZ!k=u31~edII6n6g)$wf&|VI-~<S?62b$^mJ+i
zdriXUap*CCzun3ECpytJof^X-U^!dkeYAj#lB-#A^a^=N<1E2XVZQ$*MeP4j*`6ci
zUZQa02a~0Y+h5y+?hx*UjAEi3yQ||c-A0+plPP$P_qtnL1-vvb@wS5H6Ez%Ht&H6v
z7z?}4lE=Zj8uog%?`nAbm+f5*%Wp_E>-WycPuCs6b@YC;T=jKrI<Oe%{6LNjw}@Or
zJ92JLBV)?D+2!57`9LguZt?c(j&t6W)4k74J+A!n&rl!!_ExeFg&x?Ri2dk5OwV1E
zKFzzwPsb9O9Q&B)17OACKfKxQ(cbbeN<Y1BN6)m?u{r5jOJ*&5TpOf!;wu-W<Cmca
zRtE2nJBnUdsXi{u$7XcRcs`N6i@M#~Q+n@=jq|-3x4sm+ll&K8Zg0ubUn<3;d#U*C
zT{FIOHT}+QIy#Ij-j~cw)t)NXlTLGeir=ousqWD)>)kQ>mM+io-rhAUpQ7FGcTNB0
zmQ?p^d%9)~A8t;?S~FLx?Vc9qX>zJO3Jp$8?wX$3q3;+h#eYO!{vNzD0bhQH`dI44
zb{05SeeI=pO<N?MpB!H?980BRZ>HV^o>ylKi}0}zEJ-r&yoU(h1-}oTj`?|XR4Sg@
z@<(UyR4yAjWG-W1PV$p^hwZDSly|fQjY`m_1kGUal{`Q2nXVRZ0k}>5oQ?U^)xuwR
z`(GHP?RVY`UP<t3vHsKXJ?hWlckL2r|7PLme`eIa4-K4z=18zKr{Q%Eb*AQGQ?sX_
z$+Y(ER{>MsI%GeA_XxyVvZYun&mHV+p$;}=dny;-lU*<healmcDNRMk?BSQlo{mk0
zC$Y^<@Z6mVjhS-kpgoki@0|Ft9qqioIJ<vzFJt#KKEd&Si}B35XNRs+ZxJ8vXer!?
zzI>`_pT6gCIkc4yOuehAHANY?x4~27WO+AX18*wi`R;W(*5+MyJO<uvbd64EdNs8o
z&^v!^Fwq5q8QWJ_(X`L_8hQw}`Uv5RpWjd)M_eC#H|_@E4gC`MiZhiXBD!R*^OBiY
zVl%NbGvx<Z*<s4ACl;vpI*WE2M#;%#{@$Nz5#298Th4V&`{kCdOE<PGI$OSrZyoRL
zn)Zn=c3t=%=5@{Zi#=Uaf8FbvdVS9LZTj^)I}#Jp%-xPuV!~Q%;u_`cX|4o|HaA-P
z2JO^F^)r``I$W`{nM-0b$s1lR+nm|%tr3pGIolcdR?Lxn92*Dglgb!|@b3)wv$;iQ
z&+>fAJ$pM66LW?ua*;|*+|xC^eTO~s5#mOj@V@S4_6K+r9bD^o!1_&yH@c?zd#-|)
z;GKlNi${NZE<bxVO@C{N*>!bIot2}{bk}r$Fa2HLHT`DBen|WDdcJ?Bc(+h4?^HWi
z{{m>}->7<-mq+2<_?~Z+%PsKn&U@iY@}yf=B;dJ8<yLsU)o|chT>rsQk2#)Nk(Zx&
zNt2-?lAD;`ztNK2*_4#rWDa{%BRH-x{DN<#Ivm^Ah*#vth<*;Ydv5HSdI9<*wFbJZ
z$!44O8mt?=sn`?iE0o2|2S<~`^f^qQ@bJ#;A#_jDo2pzM#(^w8v|W71`>J<vt$hv~
zC-rG3I_yej7L@mj)<s}Q2fA@O`4n8i7wpWhkmtkLQxD3H$Bz=<I*MN-eZDWubtRU1
zv@jeyS}3CD({XHxw-P<yg5Ki$h)>L?zZUTpNA@DTOQ3h`GSf%*w0`5@HOXaZ^v{CP
z<h)bpY3#@(a>BFsNnd}HdB4lcWW3plRBU$k6_p*HeVI2YkDXAg_%G25(|~)CY(RJ}
zTj8D&Jx%>n(z#yh^74$?#0S_fNi6zT&i$s=Y%6s6V0p%-r{YH@l}GmwD^1+GBQ`&C
zIyS#+{+-j{jT~+Fg7d;}lwVsYomKSW3x(4{#=$q!XD61$W@K+A|05mCFHFbte%q+G
z>B914y;s8j!%=V1i$Py$`udgfjE!G<?MNH^mf7L8W*7rH(95K~3E3@POTlY;GdY>B
zmdG7u58^1XlcObQUV`Q&Xilyl_5xc0eN(5L4uW^u7V3Fn^e#4V0yF`?{6+rT9IoI#
zEL{Chk9w`bHDz)fyXqyrWxWx)r)6(rdH+9-ddC@?&Z*ClvD_~hv1;9y$+u^mDUI{D
zWsm6Rzv}ptq<_b#cl)N}ft@*B`7WmH&$-G|e+gf$Mn`Xhw^qq#@X+<*ohPQU#@JWr
zVGR?9zeeG&WANTH@K_f-c9*x(J3EZ-cRqCCP^``T=u@$_Q^nZaWr|rdHr8TuGryWo
zruG111-~qLy+`;p^V`L5z1M~gzlc4Sw!#j6DP13)4gXKe{Jxi*NSr(SsT6#)eVU&}
zrrsqRzkTwv&;{9AIBysJ-Ujs5tZ#iebB{Nplx=D&9l<tvu>)N*o?RjNE9g2GZ!d7K
zS-jo>&C}j$=Cn<4R1cYI%N+EQT)&?-Up`O}9=o9JDeP1^jVy4!SMN>u3j8-k?;4r2
zk-mRfzGf<US?=B3e-6L*q1LWBUh<tUrJ8^7R`;78IS<Ri<4o?&5AG*8uDsQ?xq#z4
zU&k+mbH3x$W2xpTs~qg`7;Up~TNU3GLA~gGoll9>X^x!N*Q>uy-IZ#dJm2-NzV(~&
zj4KQ4c5top%Q#-%m1>^A@zS7d>U?+a!k4Nz&gR_a{BK5Q`0pC^kkNhQwZpro=6Zbx
zVtUS9eC2<Hd)ZhUdWYQ7+B(Lk?DJ+14~tLRO2|P8elNlACHTFBOqAgH5^_<3?@RD~
z3BFGqcd{>@(EB*V6K_t(uXwIJ`cGXmPApN`G}f~CT&*FWWNsV9AM>_nukaI@r$;B{
zf9Aa^9z#Fm(R2CK&%BlX$31UJ!aD))f57h_^@cs~pYY?RO;{hBl-)g?ba3S#A4UdB
zUgmd3<^R!l)33R{e>gANxBm(05AUCNw)TC*IM*)8c_&hn&aU-0kHW`ZZqfR9&ic9@
z8u_s{)h&7PC5kt0oSd3bpe$@_?c$>zzPiKj*r><7mN0gzwpo0du)g4@n&UZZcb)1o
z_Gx}Xb|;niTC%V#*0!uUHZe0dr)TNg@V^WA;e{0PsebXPCrW={@9)pPkkb1XJ-zeJ
z;QXqeP}}UAUE5`;rip4Vyt5zAwJu9GP0V~Z-)i`mNAE|MNp3y=d)Rwmi|*9dIG1GB
z<YR?R__M>_)04_)=czCJ7kob1tz9v6;7#76yc2<Ai8>|fX6E?ln<tiFUuSR1d9yk4
z987Gbaup1}cLw-<y^5dV_I!ZbeYsZPwF$q|o_A!!KRz)5T|Rr`eL21Re%|py{OQcQ
za>+%nvc6&bUDMkpW`8%A%*Jxyb>BqIy~czdyvUE`7*mstNxXzU#_u9$m$LlNV(^#a
zt*{;AY`emX{Y@t4O~=mMzifN_Z=^G^Lvy-joqlNJN8g=$wt&3g&q|NB7rcF1OF%!q
zi{SNWUY$PmdMf(#zot!}(q_8aETj#&@0B+6Gq%lJU7OZK{K?FJ$kF#Jk8aGpJI8l`
zCTH)4Zook=AED27>ziwI_<>5F>s<R~x!9%f$>gqC+aKDv%S$mI4<VNmB+p$l4lF5f
z%>FFhDw|{apl_Srr&654i)Y&BZ#kiUvMam<b~jbZ$B&}hC;BPROLdMeoJpM&b|Uj_
zFCiSr`zIILdzST|*%HyAIqmJhmrsPc2cDU2`iC`p2t)LB<Joah_P>ncAMUldF6)yO
zf&t9q_-qC<nTCh|Gk$%YuFAf3TT*cR=K@)}BkyG351A+Us73~6;%Z0+9;=lBc+B%}
z2zc}#^NEu0?UNkAFNy3AipgauWNIbHq<127Q*ol;ijQO`W#{$0v%hy6dMWmS)~8}q
zGMA;2OH$qmziXSfgf^y2UgEqtIKOP0@n&in?`?&rQrVby8Sk>Wm-7;Qk4%`1q7M?%
z2jb~V(JzwqRMs1ooK7m2;rXY$>>RIk(W_@uUDIwx9^Sk-yCK(_O{V5$SB>&aN4!6i
zE6!Fw_qOoujuv$3hk|i_+0jXOW<Tm^C0Ufrs6WY|a538abwJzS6m6Q?!Zj-X-Vw&X
z;<C<HS-VWY$2*%#r4^IZI&s%zbVaOi8XdB!$@B<5&C$ZH*h;~UJ#aea^alEaI@x{c
zq~Hifw7vK2rkZ-2{zdTu#gI<(vpyzBPgU!AH*I`6m6WbXuE9QhMLtM6m1;e*(C7q>
z7NHLoA^*}Bl6$@H!t~RX5t{s3ElorV;T`IvO;2w_*X_x7HKitW&3ZE5HS4>x+fVV0
zE9Ovh(|#&mL^iz4+)=)xj?G)jd-LIy?3;4v(cz2Sx??!D;ezG~AO7L`*&8mnVfIxy
z?|$ZLLf5pGJ@=N0T~3>M|Dy8fitK}<i7P#?H*=e3-{}i&3x0Dl^9T6&d^5@BxO_I&
zHS2p9Ii0q>RnJD*xYp#IeR-;CU$S$M8|G5H?Rd`V#_X9ie2$HIG|h8C&PMpxZmYnN
zTo})=PLv!p;u(!wHg-um;P;D<8NaJsePPdzq|&ZG|4P|d<OrTOJc4p~FzMg!<U~9;
zrrowtFT2B=Jv$wnpy$5GL%RRo77smj-$dzl@jCWr-lkmqQQ0HSGjWY4SD;r@lU{o=
zvvAuSboTxJyS90SO>ydOhi>0gy{GAWZsBy(O~8ud^Uv|qS|jdZ-n8!9g-tp&!^JMK
zQr9etL3?6QqpWY-y*$2ict5t9eaQ<)wZ^-j_jXTkJRe_KGWbssd)tAWJU_c@))Vg#
z?*1>0dXx9Y-k1HXH-+`qzS8>mzL4JoS!(m9A`_dSndD}1&TNA8N9y?_+o5q%cBwF)
zO<LgWLun)O-Q3i+G2NtRzb0qqq?4sXlu0L_Vh!!Z;!Za|mp}(&--7i5_ie3^F1ocs
zGkT>wx@6OdZK;a=xGb<A^NWeXaD1iKZ0PM*p`WuM*pAQ!WDXZ2HiWfEV9TWc8`zLZ
zW<!2-%yhoP4_}rwrEK)3%er#`4tKSOI6Utq3Y*Y5r@fVhq~TIzuICrlpm*|`cW7R3
z*Oo->8a6E#KQ8+^4o))+r|XV2v}=sLn0=dUn_|OzCo^X&OW;vb|KKIMvOd}?*vuLB
zuBk_T8I3PZqhnrqRJL|gd0_0=?yDbLQ(9wt{o`s{eco|(t{P`tP3f9(X-pd1`NlMw
zGrsZv8#<xRmS<KTOZt;mdE~m{7kICVk7qz1<oQdfbZm7do#ULCLM|4ER^}HJj>M1R
z8_dpZLk>>S?vVVl_*aRk@eE;X3iUqk#uz^eO=oAHQ2(*D)<+;;(0461XASz`rxjUS
z!+f8PVY}o5W51H#t0s4x%hzQO;wI+tY38vl^CpWCBLC0bh(GlzeJ*7l*SdN1Ud-N<
zn}i=V1%D6t1$4@eWN8O@wle3`r(FVhn}VDfuE{iQ{`nZWPPOZ@?4PVMzBhmE2glG!
zdnfyIDt_Bt6~FBX_#z3<uYu>kEuL>GA_GqsPRE}vERkM&Lp*YR-X9#7M{0Q=97^C&
z0;dvql)$e9p68T-&j$RGsO6VJk~z_MfNAo#wo024_pBf8`StBi({5ATwK))JLwSjE
ze>?pwQ><tEMZA+}Le~#{)-mLCeW7JSQL_4l8)loXpVo3jdfwJy4=T<Q=x=OgX`{Dq
z)0|w+cx+g(?n-XV-=5gC-Wzs0Yxrm4Uya-3K8Nod%6!i0)s22mIZAC^v+gQw+?yK~
zOu^gqDPp>ZV(932L`Ofn7acWLM}IU8uM^LqU1=CQGAqAh)6^Vs*1M9MmVt}m1}^l^
zcyCAMfa&B4S=bJ5?n4J}&%T&W2o7rq_CfDL*WOjy^x~@FK-b<;(X}1vsJ>rWr|(~6
z-Ec>yFa1XJeaz<e>1T}Z9qpXHm(9v{Zgcto9bkA%FBl!;U(F79vyrzKQz`ZjE+O{$
z&2oB5DmG6zXMa*m3TI-&D`oqslLFUy&PHh+`NSMQ?|IS_sm|A~n3;;r$o!^sPyDNH
ztrJ7Ok#VyLPOoU+BC^(TcIvC(4Q?gsA@^pd#>n)W-PlZ~Ke7s$eu8`w9q*gwzvr1T
zIx;&qq=nXG!2ApNtzJ+3b6uT3-3C0?#Qz=M-sOA>?BPx5I@zU`&_8eFlP`K%dx^h3
zNihKQU|aUubh3^2rexmhDNnO)Nj$cAV*%d*-#)*|Yn!l_{D;%59Z%+x6L#Q#e;&OI
zAES$;L!X|v1E2K?`0_@|ity#G_`Xz$BV*9MS!yHY9x|F^z3kbZ@C4%cH#Kd`$M9Fc
zd3&;rK1#qse{lW8yzHK|e3*$kmNquQ>%ah4_TAbh(O=gr)|2=;nLiLNO>I-~t+S8h
zk{g$QZl3CzA9U>9z+f#jm}dU>B;j@J@*WSlIl5@CH$1$FwSOs{41Ij99sCjKnTqdY
z4U{POO{@)e5i5^t&vu9Z<t|S?xz>007Q9!(^_xGLxt(<)rL}~A<{9SYuEfR-+lKw(
zsAoLgJW4KUL|)rHlUF}6>WPp1U8}$ey%5Ube%kJEdl-r{Ll5DtSkX%7YkD{Nzy6Hl
zkz_pA#GWg*W-jahxtWhJ4@vB4J~r2Xw96YS&pG&G*EDpj`A@{xX2_RAR%Dx2%6Ag}
zzWgWjgOe5S&dixyM8?g3I^blbp-<;z{C!<xWL)bDXv<ib%M|ul>+I1k`~!H{^x56p
z#sAqyN9W-yr2X$hqk37m3b@!<(Ju9bcN2Q;MU$JKZS$m0F3YXPZ+?`0;m~iE9*qZa
znRt)z#&1Ywug{q-WgVAL|C+0=X{jBV`;oOn;CV{Avw_b{d+B)jve^f6rbpF2)cwx(
zqjT}G!@e@eukV3hWGrLs-Nzlhq&I5p-6x)@X=nQL@h*4*y_r5%b5C+__rD&2MVWu?
zGoIG0@-H%LSGD@HSFs1<{gdJs;Qf^_mT57}TvrWDgEvxz=fAwlyD%3cR`JBV%#NI`
z#o^D{;?LB5M;7`&17D+G)Sf-pQn6<h`o(u-^SKtYLq8qm9mHuqF!I`V>G7^vPvo+H
zkZWP>CS5*^j=*L=K~6`5^~Q-PZ)&~aY;QP6idjYJZsU2zjVEe<pv??;Fz{W_FU&DE
z2>;#LPw`CV2=n-x$B^+7xZwL^Ymi;qct6FqOfi4a^G=4oqI^O4<c{p-QRD~PmG;)a
zt4Y7(nD=`0rM}IIPM;9!+Iqbyo!K?xduxbC#iTpgBTQ!HH=}dAW_)+HY(wb(vc?VI
zpo^Qmr_J}}XuL+-%r#!Jgbrujo!gR+7m&XsIStBp*rD=Uhh8h-Z!D3%Ei@w^^wGA1
zbt$?l^V{26@t@l=hk(I-WN9LKENeFX_a-kpUpiX0ZO?4~y{ygA0nDWb-+6w|Gv31T
z=!?>S2U@*X*~=^xHpY)`e7`q)(Ry@kYpiXueEhw+q<CS`Q;G*{pN*}18W^m#pO5=#
zTg#)@w!`1MSf|Hx-U7FV*EMmM308LDvRL!pCi1gKe=qxY>{mc5?j?w|OaSga<Y_MY
zRcjt#KR<iRCAqzeTD^UW>)<C6<Mp<yzSb~{p28k(INRF3g0*rhzQC+}0iUw9-Ole#
z7Ir`%?3306tapepJh3<Puh8a{n-|dndjwAtPah^;_4aLw7p77r<mdWlDm1cK-GVOo
zEm&uww;7XsHpv3}(T7bhcg?`(J5u4-XG6V{o$r~B^B0R}Yxuii{Y-yX(*NWtFSLn@
zc{TJ|p1cblLuVt)riVVgZLH3?wyw_FW8Nw+Q4s9>CT!&&3#a^S|38g-e1A6Y|CepV
z+T#2Cb$5-0^-2|1D6^a1yDi~=utC4=)D7{<9D~oAu+QIZRlnjV|4DKTZiH4v=4e;d
zSHVU+TJcwMqGkMOBY&mpr{K5X4`u%B7<~8SJ@QGjciOr!53IcZ;xUv*9A3h&cmSOk
z(fy`_Zmi<DY5%H8e)loxfX(~uV`J-{*7(I!RhqM(pYTtMhI{5o_rhcI{3d88**v9r
z`5tl?Yui|iIsanTpUwuaFNyayK8AeZ1Noml=4k%5E_YmfmpgtSxZWIG_XXESg5$e_
z^6A0#^T81~;xl+t`dV?`K%YLV{S9<!yw-1+x^1j(e(U^NzoBIt`_klbrkJ}6=G$1p
z@tGX`#i+@V|KCQ<7k=IP?l;_8qifc^YYNcT|J!Zm-=&r{&At~tAr9*0_oC~NWq+CZ
zaucQNvYS{NN`6O<xqcsEzD%z54chOm@fU!{dg#vcr<IuXde6nIZ$!S=c3FM-3szsT
zt{M5b?4Cao=z+b|o7q(>hyMjRL1!91Z`wwTm3j7>)+k<!E}5sj`{USjr(X{%C(ial
z&89D#4^QDQ!3+2__Remj=R4=)BfiTk{Zu*Ar^$sllpyb82RbI1`{B*_o-V(FvhBJ~
zeX0DJFlP?AS5A=S&0$;GEdQ-2pN@6Gx$@?oa(l|^H-t}n%OC8S8RmqNSG$%qNeP{q
zYf3gZdpGioSDaj?#D^v)(Z%s}*W6zs?`_AL!h2#prE6n5=Axgwrd@emfphXadQ^9z
z=k5K_<Yv>^*ks0--ywfqdbLaWfG1<E1^V$n#+;q-c63c!`<}vy_!`Tnf#<9aIq1Tb
z^~cfDr$1OI<XM}NQ)zjp%}uXDZ<lwPi?3wt$l)Gr(G%o(HKiECJFtn9OF8dSY}>+(
z>%AG+k%b?coPf65FC{l;b}1f<WlqNn+`oc7(HZ27E@VHQHAB;@*wUlSGkH0zIUD71
z?sBvw);<}(`gYAnrVw8O9<j{#MyGboz4;nwL;tZaE1zA@lapgRRrRxNXA9tWQRa@b
zOZ-36_^FrhZdV>V_26au9{dE=_y2B`7+w5Q|5xBuUH>cf)8uS^ikzBa(@LIweHEYL
zRnf@k5z;8lI-^3D=ci_t+8Ru@nq0)#pO-vu54?5tqE~-6ukUD(rx06~_#AnH<lp6E
zx3d<z9Xd{a3psOLvqrY#U$KY$9&&!Zb?1jK_$GSh(2OnVCg~gSJ=D6)yPdVD`Zz_M
zT@$o6%4~s$EXVf{`vJVS(B1((oK#=rzZI5{zjH|Ev+jMUYsMcPVSX2qBg2{sTFm(7
zWNZR+^%G+HYJX}{?0>LFo^B!^$h#dH%w_Gjf_C>6(zH{XS@$oY%{9EMLv;TI>X9q)
zlNtDjU&#!OPTunCuU#s*f@$;=p5NU?AHzw#XVl@kYl8A?PZgVDfy_==l5A={#I@<d
zv^N*Obgqx@qoeql=XPJkKAfLt);peI{4J>qn7=K|+tu*!4e<0&n8(A+;S=!q9_F=$
z`FkF|&Uh=8=fqs^gTK)ehnd5>rm`Qce3F*T-xv8NA$520JLQGBPLq)n>4P@>(@B}h
zL5|bGBJ;D|o+--QZaGdfp7oUD6p!RMJ^#;{h2C80dFfJM5YKvUg>+^?*SV&4-dpR|
zaf8msQGS}>s2=OewoHfRI7#0A`9QOWJyf2<A#BNOY5M0}IZpWG3(Cnk8@;{cH=$d6
zzLA;E!6$o5zw^mN7kja9e|xI=itoGMl*oBl79Lx;*BadSIKJciuFW)#Z+{)X5YG9I
zvwExeoUiVs<J6rPDQ}IOpAX)fCh`mczi7QVb!AI~`%5^!^$fXPkEWWZ^HZB-aJ=B{
zRTwik@0!JYUphM1|2n?eF3W9VPj1&V^OKq-&pRgjKS1YTXO-VnUk6^Ez#eBZ`@2Qu
z$hMW>;}U#bf|vPL@6i(cT!Oz#@N@~DF2U0!cse!J$%6QSyiMYP-ivQedkdfA84Jo*
zsB9X!oap03$S34Cv1d!3`Lo3q@|%+RWvpG`FX?;vefSSY{U7DR{H96%Eu+dKm;~%Q
zCah=QcwUkBYYT4EUd39vW_(-uP4ivf@#|gR|8-`xZ<pT`t9(0PNzU?{lKv~oZ;F%O
z6jOfFB>y|ms3^ZcIX_K>B4rzYD;+~_kKzwhzB}OeRPvi9`Ru!ri##>VMOGW~n=GeZ
z`_h7+YK|$tDd|6^x{Q5Ou|;`+sl-vePnG;8axg9-*QbcQdQB@z;eIgJS9;t_Bj?j@
z{#y3-bgO(A|1Rxg1E;yzV);$v{0MKC+tH+aCBCT_<Pd#~oEGj~RW4tHU1hwq-{aXh
zMR)oukbAu(^DpU(h-uEuZcW24hwu$7ujwL)a8n`eJ&hf5`Ar;4T$d=%v{84~_X=9?
z;X~oiJ@4_J>XrVB5YXjzO!7aqjlS@mma%?l#xD$WJ2=-^!PW3fDYql#*0z@tchoqA
zAGrhILS9E}j=YZ7l-KdKuIbk<&i)d49lxBOnLX>dypEk|m)B8XO<8C<3NAC*>wZ|c
z)$DWUJodSpuDQaCKc3;7HOe*1wtJ6DHi+5oBfn{4*R1CjZhXh*yl0zZ`<TD&sdQ7E
zob9RYc8w18V%l5C6>_nj0__Ux<NJtj?8)AdBYV7QJ9}F_$RB!shx`EYs)wiI$IMyS
ztb8Z6_j>THXito*(%##XeV@e_tsVXDq2Jb4^87LzbKrFH;f*tU(7pG}Mn4~5J`RL!
z*&o}JnVw55%f+vNS7vn0`s;-ocg4wZYFdaK&V|nCZ(=eWl^;gl3D@X^KJAsgJ2xd2
zzq395TX$*vif3l>UW>l->*AO3JB3H4;Ng>b8XNdGX@BL2>tA~!@$JNkTB3Rd8?(>!
z&zrWfU#dNW_?@MI#^8c&Z`zmr-l)N}{44qn;I0r{#<V^AFX)YWeWv^-?)$R>S^7@e
z$-qysrS&qfHOOz;UMmB#_x_xq{axu6c)6P2^m{p%-^4zf<u|<}H&JlW0peGFL4MPX
z+e|ODK1ELd+j6Z-Qsg&1Q^{|d<j>#cWb{aY-)~m&Gx;R{#d5FK;;R8$GI|<$AfHD5
z$n1@4J>~e#Jl;%>-$Ohz<#PPseRBL*Cubk`kc)2;Z~iv6SUG<9L#w5~$ngvGDY&{E
zKgy(M;VILvVLPY0&?9flIeqk0RUc(n5|a{LEN8Oml2p#yjxN}jof+trn{%z9PVqk(
zjCEzs=0dc{e$kCrV--%qQDcOL@<TkoIiUX+B5k&f-^S)_DCp<cBW;M$Xnw+e1YiAx
zblmi5?M1$rA}<MFGm@9oY<WpDD|tz8+UD|-t_$*#-YmO0JUPfqx`@1_xz)U+rfbk=
zbGxQx!n~xfv3@*K$xC`~gS@1#)#N2zgx<u5)%^XW)qktgk>-bje^mebpLO@}h4oC$
z3dy2)5qc*5+uVGMp1N1lZW{Xl-_9u?Xl|A`Gj{cwdkak~)u;GCI@14*ZNzr=E!^~`
zZN(|6Sg&*eIh9k}SN+yq%G2;u(gC9<X2Jt0_A@d!>iLw44(LG#9IxttrUW{mH7c(>
zSI8b#U^|p+{iS0`vmMB<>6!qxbP?-o>7F8ExQXXGT|a5*(fqdyUK4#0|DYYZ3w=W#
z;>KL7bYh^NS+DGvy6K|dO*4+&Hjb;qad^QvUb~)g%(QXnd6JrO)WRM!jx^(t{nHqJ
zficJiR>t7q+8C&pN_oZXo9uZd?1l&a2i7?J<EtJ1vK2gobg^(S9gh#QBjMjk{G?vj
z{Rw^1kMZFQ<_Z}vrM!LY!_Tem!)NB=a|HYFJZCfQV=MAr>>~EzzotBE`0UG?bLpmf
z_?f@jmh@xCfV+2wA0G{E!Cu({^nB6mz<b04<yQ3fUZY*M#ttwqvB<nMumi);&PTuH
z<Dnnnat*F!Y?N2&==v}^(nkHWZg;*$F8*}(eW9%&KAdYJ-vyqC^20%%BZEi%HMQd$
z({DTd!b9peMZ8)3V|_;Y@|V=XNP~Nhn7`)#vT@o|r$in9+nOi#tbhO57<y;#Yuwgf
zuQuPD<bP|G&9Q&MG2}VE5B;5xtk>+LzH=3EwkGf1=2+W3#K=Qm$^Qk-<F1R4H^a5M
z_xU{Q&iG2<hV0$s#~536-*W;!*M!VJvnFu+o)i2>R|P&WcAmb`E36;cXZ)Q2H`dJf
zROrSh@NITst4_@hbNhJi?CC;Y{$fC{N-m(D|8jN3n_+$B0y?~)9qo9A>S<&Loz-*=
zI$*9pWweHdW9IS;t6Yu~^EqY?Cqs`}+f$6;sGmFL1^ah1GBdWd`tR7r{#|U6d{p$n
zi#5Le_0TsWhZVX14f<-tH@Wyt{@i2Ug*iP(`ov70cS|ZBkAI(+?<v}+?mPOI{(IQF
z!7hn6%$ChOR=GBN*lzRJD&4EN`~iGT|DQzj=VuCrVEa3Q@(WkF`|!He1GXIx2S<Dl
zyT0R?JAP`FJKh^y|E>Dc^ZUD6tiO*2F=7wD>a}qG<HSar3i$OiwdNPSL`$u?YUtJd
zj2FaMrde!7Ft)Dpdft+b@r|+1z>lvYm-e2m1K&y5JED0$+n(iD{A2osH`uqsrs-H7
z^*(>Ff8E`ETVF`@teuj$Wn^9AzQtR@e~B$ywygJXp1IY(wPW4gi4!9SmoH9i9qCA1
z+fVI-TNhuQm`-c{Z6{z}xx21^aAf&y{fUQrj&DyaoztJ7;NWt#T0ZjQMBiXyUGLV#
zBahH#N`L=4Ra4=8Q?I*t-2Xu2_$v=T+_Sm;%#_`mp9QVTb^C$U4?KJ3$^-3ZUb*?^
z#^sx%^{ILCO#AMWJ*%%gFsA&#W-AW+TDo@kv(Fw_Td7`O9#pU364pO?VCk8YSN42D
z9n`ncy@z{FE<Lce@x3Vr*6x0#y^E<>->~h{-J6%XyVdrB`E1Yb&GqF`d|aPr+7DdW
z^Tl)3GrVi7Rq$x<`TQ7KsH~n2DqDL%SRH@mfz1r{WEEH4yZOooPR=~j-m|o)w*2@j
zn{VFz?3pPCAWlfPlUKg-qvK20UU}x^=AJ1hXTGvDLR0GjSoCma=}dZ@`O1|6>8kC8
zMNsGD?q54lKX!xBbLH;UYkQXNer5BSn|qEgePwOp_?+IYTl<&qo^s#fMA)Pj=GZpN
z`?tQ(F(;^fd<3BxS)S;av#!5)F?zhKD^V%y9egq|*wMSLqaWzpU`)HW_I332cJwEX
z_b%_dc3p2r-^kX)&Alf&5X+s3j*-M;*G)~_vTo#&#0iI*6$a<J2aNS6M@~H1-;p@k
zzwS09%X*M_ADk}u(+_s2sH49tG4<m6rp{k}vE;jb=J6?s#eIXl*Dmj0yoH1SYV@5*
z?4FY7S-cp@9W>#r>IJo#vb?`{uwQC{UhW<_xGr(m;l+I~^Z~zrU0?6=#MXn4T-(2H
z3(}8d^KbgPKI$$`Fr;1(UEYf>NT5K%=9~LQ1`~_>Z`+c%cBFURVl_m?^sO80NIV8|
zKpsqt+yX88HO!!W@4Eg(&&lf(XcN0r(>DrgIqGJRJAH#&)+Y|5u07~d#SUbaOQ~(`
z=<VC8-cR&B0_s6;0t(_=N46gRaR0gy__TNH^Bt(NUe}qlR&PKcn-wF2VV`JGpNx6r
zT8Mgg;*tK|t%F|2oZb#ct6P@$4$evZxOXtozYa1k-m@j~qyEH?`<5?H^bQX8y|7i)
zpi{I9&|%z~J?3U>f5(qU*1<vj9UV;Xpr*w83FP}p|HU0=4E&ki+m@esq@Q<bu7CZA
zH^RfK!2^r%MNRhsW?~&^)ZoaNrNq0&`)|FMxZ#Ey5>wXoL-bqvUN{I-yucu~4#MJ(
zj4VF5ydRsR2_AH8%!J+shb-?K?C9Uxzs~c%KR9>>=3l(L|4i?R6aCXW9!;EBJ~AjU
zBbX+@ZtXuI!2w2tx~>guSgpu}{=vb1*v#heK1fNs!808Q=%a~~eUD6E-k+!yDu<1A
zxiv9;WL<}8YWnLBXmaMq>-swStC&SPTYRuzlH9*;-3X(Jwh>>QzlqK9BZDt2ex&zI
z$Hiw(3<4!uwk{|$I-hjhf$%3DXrGdJK_u+$7+Dw4_!9mSYY#Y;`@mYPYU1W8&-QHJ
zzCEE^o~9}=lkM9D(DM@EUyJ_2i|TPkvi2`k`3uT>>@U~g&sA7$f9VE)x^JQ{vi;xs
zSE2O(t@M|o+r9Z_uW#!u-sYao-qzl&-qfAfJ$Bij-}=)0yLwh1Z$BUxFjCfg?TN+x
zx2UXT>%ryA_i)dfTK88WYjEOun|n87FK_9?B=dBh=jHhkqV@iY-#hMX`{4(E>6%rK
z{ln}(`{t*1-*xOCE^i+=egAb|`{5P;()^+C-*<fE7Z<nqv)1FnzjXIEdXAU2=D+fl
zi~i>32ltQuaq*S;4_|j=>i(HOe%G(9Iy?B<(N_uw0m<KmqwaV~+#SE@j`4qX#~I&n
z$N#jzj<JPXdQ|U%H7D%2@E?C@$Ns<g3mp?@CZtz$eA8_+U()ftm)`gY$M~17nfhLi
zle3H7@kx%CWgdKTnU)%cr#GSPo*!Ly+i`E!<`*9M+;@+A$9{j}Tjt$yJbuMjE<W<p
zLi?0|ecvbFa^rW}-~VS1`~Pxbto>8h-|<}f@K@S@;cNTuK7R49wAT@JYCTntgUFOu
zPVSz^5jTT~d^%m^FVqqFx<CIsf5SiLU-SRRf2Ow=_g{PPg);|n1Vs=p&94|7Q+3z*
zy6gJ;{(0`7ul?}P+5YG4|KRbTymIpJ?%j#qn0KgAPanI+#-8aI)a`NooksSsXE|OK
zcE1OwVQ{d2u+qMfEgji<Vou-mz>Qkm+tKTJKk8Y#Sq8Ezv2<SI;gip{Kird8+V@ER
z$ia^4z24;=X99TmX<HZL$DUc-KX_tY-*l|*nZdiao;cIN(s%F{e3}Dt0q{c>_sbWT
zBVO%e%FHh&UU^`*IqA1ve04(C4^wk_Vzar`c7w%o?{aw!cPIKU#z9K-ZMBMcowxKY
z?_ZDpN}Q0Bj@vxg`$)gt6jV93V<6HvXn1wtcH`SZFjWk^Oy{7o@;`{n3IPwSUCS~l
z0Zks*s<ne0n_gV*6I#RId5#b<P)K3=^f`B*34nk9zQvD9hgaL~-g+C$9ij?uWFQ-?
zXcB|dama7!>tDP*T0fuw^_HGIkT`iap5Y_%!@;%x;uHNGv_=^0`>+kXcip<)yKCB?
zjNVBc!*{znq-rfp-7>$rimUwbLD%D8$GU?jIu5b`Id&|u`GG61jN%xqj;7<xYgSH-
zti$8&z*p27Xq}@|hu9dN5dLStU#Bftrzo6&(Z=sGLdSo5pEgNC=8@hL@at`TC;G!_
zioiej9FJ|j#fm~twRX;b9$4#a&03w4H#F`u{l=+h9$DNsa%ON&uht(%^eViE+jqZ`
z2yP_?4^E$sgAY?(dpGODTY4465>G$ON#Eg+Q{ju6d21iBAX(qm6Uz@G-(xC^Da57X
zrz;U%&)YfG^B&mx<kpcNZ{>Wdew29L&A2Q&&g@-&i;h)1zyCsi2f}%BIxPQaVmfnY
zeOgq`t!1=Mk?`x@862jO??1XdVfDrKgNcW)oj!PVqWvH%oQti5Ng5A+KxIhKw-rIJ
zWfqn#j>DImuT-PQ;3NWyk0uT$jIfFwx;a?9J+b!S)~#Ab9b}oO6`8FFE$m^D$0{7r
z>DhH72d9fK8-l71tA0e$F+r~?KAT5Oxdn?ev`mCHV}Mj~se#dRuw&%#=KdE(6u42i
zM&mm%qD3Q2a}J2(z>~HW2sevxi3%zTo%tW9U8qD+neeKGC~P@P^Y!Dk5opLJ6?-C~
zn9o7tvi&b;sl5&ch07nQjtLxY>ywTJrzk%7;;+ch>k_6_+KxLNn++sEmi8(0ADe&K
ze96tv^H=hky<HIiSIx>b??%ZkPfR&*^Gj1-+8Md`Z$0h%;-7oCM)ueKN4e$+{3NxK
zt;qZgMzlrC(vc1Z8Bl7_%*-BRYM@MU20F2MWXpZmEf(?CdxEoBMmqQ-glIt>mCI&_
ze=cx$tLZ@9t9S)lGzSXmU01ocR?#%fCAVts1#`VNoa<;iH*u@`I;wb>5e&3M<p%g!
z`IUWJpG;Ir)eq(9kt$!vN=tr;qB^c72o{FTEC^Yr&(CceYBWJjKc-~EplwJl9giix
z=={AZPE{Ww)Zjq_^rEx*)w-s(PGTxx{+hoAaL<9m=8*_Zs{Ly`2HdH~H`YHetNQv4
z(CzTHs!15*kJagRDcr>){fdKj$O5AN6+JVDX8GOQnS#i;Y@T81o**n*rPndz&G|Oh
z5!#9`sNZf*N42&lZ7d$@OLox=SK=h0+U4S`2K_I+dwNBZ98?Hv^0ag6PXJL5L2y;B
z-_)AWri5PX1F0kZOgVni@IK)D-U#AhKh-gYbx%I~FiV?gi?MY@zp=OjKCD`YLljyC
ziE-+V?Y}YHVB5pSS38f5=P+8ob{@x@!zyhw-r7EbQAE3nj9K+-`>51!%r386KD0zJ
z7s<IRVzo%W(zG~C75$~_s19Q(hAj|w6)yz{Ra+f+c4jT!7?3KAzyqUO0~0mSth<C!
zU~TH~j#>{<>sTUKRyG)8#hS2n6RGP=N*!FROW&Yeo<NxeaCe%BN9y)WpT697n8BR=
zt&y$RMPXax?}>aSpjF;z)Xp5mF^x4>RXtcU3;2qg9dW8|o{hUo*D>`g>(HPhZ79g`
zaVn6_0tNuZ<-d<vvqqPaYTkuCxw>MMbVcvgF;b=KGaa~i`trULeI42_>YYBFF4aq|
zr)}DLoc8iX<*}VWFP;xXgf{~m=9ynjzqYU892@!<b#Cb;oPaa?aPN~WthMCT*fqRR
z2B6It(_m|yTI?TX^D$U8Uu{u{D*b>qD3+)a8$$OH8DNJ|bg0%0EOsp&kDsj4kuBEB
z){>O($aL*`Xjtqp^^f09b)Aw_y>ONCy6cA<s8N5r!dru&_h_BjbrwHhD>xfQIarCK
ztUI{XD7=_;#0g0acvN||hHo?xw(RJgZc!L5PwUquv>uo5*0T9U_;E~|s|m#PpLkM)
zQy0te^qdDf4j%P=CT{N8O{xWPsK#rAG4-ePoIH7s`o}|Ts+f#BCUZ+gl)KrX)cCGt
zF+4{kW<T3T+pCq^*6PYFaL&gWo54F#$#023tmTiWJX@REn&aYoTyxjAoXv)CQNfy^
zN;h*$RujuRJTIY$KxEO5LTOx25rgyBTlzZTElr#UUc%5@dRbtQ-2qpm9zR#Fb{KMR
z#;X_YcKmuvuRGs30{pH!&p3i=HPFocs>3g=SA*Ud{A%RX_+bi?#x5)=9+e4arlWkp
zTnE5wi8L;a2uMe<7+bF)xG}iytacj(H>O_An0gl9*1xW!Z?OLn>1m93l~Zduix9HZ
z__^%gIblUndc&}yNX?0eMFdb)hR!>_fSi{pEdFm9Q^V=_d13ur^s#w6FIo{jb3PhX
zV2y{?IsLV*7P$|6jKMK>DH30c>b{Dtm8r$=J3jKrBY3ASpwR{A*`iOfc1~ZB;GLSe
zK$=1o%a?1BJARum^j6cbx^*FJs{oyF*5FV>OD?Lb?I8H<WXc6=i7RSH$AP~);dV}<
zJ=E%wF|bcA?OFQ3Nn~1)m&-0zq$a9+>S@@6sR0I&EywE7p3Jwc(DdP+wVya}<^N*u
z{zB}!?)`utyXPjpsymrFVv;((ilW$KN0G<2ERSRPpGaMC5$X^cXrWch#SdzG8`NUN
zaG@y(wG5$%P*gKdLA@Ap3a*)gD(1nYAXLzU2#1gmK}{YmDd?epToCS1L>u+{TYI0G
zGtx*-xTUz<&m=$XbM~LL_x|j?*IIk+wT};GWV<J=N<)>f!)r?$<MBo^iL7U9p4!b6
z#G{3&adq#}9{t?xYQF7uxl-6jUAXlQs)v4CY3%DdtPPK~8S^Zz*4cNjo1X9Pbh|3v
z$Eyo-d3INwhpyeogRO<RzV0`vmDH8JebrOzzB|pf4WDFedt5cF8~rSPb!yAEw!6P)
z-+8kK3wfqEtPNW^xsbj7V7NXWT^oKpml}Bbi{<_)J9%<xG#b8rJ`Jx&*G|@>#H#U)
z^MtV`P98j_LOyx$SO@t}oo@P-jh5$gX#Ov!yFIxFZ)bW{-DekzyF}Xg{J?$f)7W8m
ze)BXY$06)1%NK?-fvN4<e6*X(q&)!0)^zty?PN-;{6a3>QEu+$Hgfj2ZCzQ+VP3i2
zKh;hX#A?@@Y-VXR(;g7kbDdUdrXO~jw>|c(3w6@lY%sY;+*~-v`=cEa{;+@MoExI$
z+TP74*}viZ$0kp{Gk;ojYa6cr=k7Wl9?f<yk8+*oiW*g0X`Z=OUHZiE*yEpMMXmL)
z?_%1Y+bsh~wR^a}nm&)&p2`*4_4vPrS1;{L$KmP<{Nt@Q;#)sEG~Dy!c0;|><iSVN
z5dF@c7@l9Q!;u@ndP1F2AbI9m^|j0uzyI;uwW7)tx1M|~jq+4?dANVi^|{rP3+KMq
zEpU36eu2Mj`o|uS{;_-0|4xa{Y>XE!*O6S!Q}Mr(&E8l}ui+i{H^(6T$gkc$|IYdS
zlOBajD<9t;=X@MqJ$o=WU&FK2DLg&;a>xdgX}jN@^kAr?vT`c7_jTh~_eKkiH#glG
zw(~Q`ycK=5d=BIF{kL}QdT(FOuV&Fb-L1z>?aci!y_FZzIx<>H*M<|-^3t-ZnU&Th
zxy!7o6>TXeMbf)Z8d>F5rcfoq>T(+~+?}I0pDv$s@1|I(iz%BpS;utZOM8;v^(_y{
z4j1xR{ZQ-nJl^cVkcNw7Ws6B;sWoBOI}RtNZ@(wcMi#0ixt%O^aP}>&<`gfB(L!TB
zkw&*sUH>(%U4L!g>pV*(BHd%FGE$KFm{WT^ihZ@uwEh#5aVP4mZ&$$T$(3t4Ns~2X
zT81Zb-L#2$gCd1O+TLqxXKpOakJi`roEYZ0V_HU1NN3da_-dbDn@NX*8a*}t(Utk(
z`L>R>Ul$kKLEcKQrsvzRP3@})gTYp-#O8T9s@~!4X-9gP)H=52$rFP4mMwmq4$5^|
zw>}TG(($(WrqasJX3|s|Q`1(KX6`%f{H~ps*?)CcEt6g`3%BPsHg4o|y7Sc6P)EPE
z>g3vTGS-<oHnrE~J+rVhIF$#6r;ZN>WnaxesW`3;Ke{;na2UtRv6dGGD@WTP^A495
za-L7-$oKT?UKpl3@zRBi-ZT6t&+{|P8Bpu_=-8g&hr{!~y0k03W5(l^n|Z3TbnVo9
zW?fu6G^}E4DPy{a;%#K|oXusD`eVr(hL=Xwv3{HmO2dDi6|MG(40or8!l`qYTiaFk
z@W%MvK8XjXacoo_9Hus8dY$*IaeD4huC=qaZFs&dUmGpvl4?0t_NaFG!Rx+v`;ULh
z_8%Yqs&!&s+_vvMU~7B7y!l9bI`s*~)b>1h-`XXgi?4b!rMb5b%?@dtIzBu&S~)cu
zwpH(NR6B$HljDBB`Rjb@cVg=BPOvwpCbf^Y(z^G2*kOT>(#@<t=elgTJJMa2Rww@E
z8!O!b`_%bco8WkDz1QgG-!+}XPx^r6JZMeFX)w;k)K2klSN>Dy|E-zS6uMe;Ypva~
zZQHv!-#y3hP;M>zG$wnyc?q>^Y}@kj{tZrwt$lv*{2kg_*Gs2A<Y&7lop)`2+s7S_
zWNqrFr_ycD)-&QtEnBuN&uFRCeZsN)6U(!UX@^Nu_w?1bwO_-@vCp0UWcynl-!|y(
zjAODhzs>T~7w%;F_C8<ofQ#4i4oVHzPEY<nNYOK#U%8O}M;GVkPF$Q{PgMDkf;0DJ
zOKtqrxb@ZL>}DIA8uYc(gPE1()oWQ%)uNZj>0Ovo=H!WQclSeezj-pR{#1HNG<D3=
zm3NO@v2<h9^-4_l#L;l~d)Kd4<@{*s6F1(i8MDm!Dh$?B?a1ep%(*|zLzNUF^-4%z
z^O#h(s+?|fUY%RoSiW_Acy`zMR>Vxs{ABAJ!?duk<+kqnTJGE1J=FfB^v?$Se|G!U
z_4?RNAKX8Ut<rUMK3T=;$qU2UnAGYv)2J&Yy{{%|9NV9bX_cSWyf~;E<J|KM$H~}o
z36Fo7=ctP-DW&SdjA7qwyS$R^tiOP6oNfuU?;q#U&)Q7d0TyzlUv8Z%yN_$*QEJ9<
zKKH@6Ju=R+UB%&0C3E@m<@{UIzn8Z6_LomtAoaGEKu&^%m3&{gHgkKtILb{=TG^Ku
zs@1WTi5cCkdwP84zqy!Ks}^skr0*xEG2#63eCx-SHEktVS$AD0Ey47&X=Q)CL-$U)
z&(*s-smQb~Ngd(Z`b<?2>MgI-5;m^&mrXW*+qC4z>1%pzZX*@u_Ucfk&)jG=;1k2j
zQ@dwjgRG${GF_b`srC1Q>9?2hHzzmmT}3;~S6w;Fcc<{hnQTH;tS{7aw4<vxYw8cb
zQ|o!ae2c4#{e0=%v$nXhG)b<jm1aNFR-2P~+)j$hN&D4xr9fx?t8_-sgq7^%snw0H
zK+m!5%7<3x%gt@8*|)KW+8x&NI0;u9a21%93H1xi=cafjt#Qkv(fqi(%vvwlGJX4Y
z-n@MKVDEBz&@Q!i-mBL;Q?J|l)}1Krh@|h-YT7v#E==f0^X-13U7BxQ9KSW(U2`Ne
zNj*CyOCG4EZqo|$31?rwY8TLOYLR3_@3wc_a_L{lB6&eCmu@TWx|jCaI_kP;>(BXC
zN3r$qee1QO<C&Z+3v=H;oFkrP4v&|v9iBV9oR=DpA6{*JNKenbHC(xwTxFd4_1vgk
zVfUoeULnjw*lc&FSVv(gZ_BOEqy;GN-u)K)-}Q!0rZ>64+gjyf?$j6Crq`DA-HUhM
zx_&!v+P-&v|Lt9Q0l78&zgsPYeb0l`EL+BtC5mEvS8|7jxv!g==dFVqACI!HE8}{h
zu|1ib;JsDtiR~K5xm{auX*KPHlivTevm47*(av9GkK6Lx;U~Md&E1{Z)r~#}{gZd=
zwyO$-tKAJ^cYxcG>rRaBC=UkfbEB2yIO%$wTL07vYMoUm{_uX&M&s3V)t)rsY+EwN
z?LJew{Hk)Q`^~UC)1BYTGj#!H`?{<AhqrTO);6v8mwlDm)8G5HlT1%zWwP_WN;jBK
zUx1n~8DZr?gXNigI*~{Cdk!vFd3$JBUf*f?ZnDP{>&XZ%FXx{ulY6C%%DciRhMOg6
z_u^!|m)ULKcw;iA#^nq>HEdliyU!=O+soWm)eY)OwxpjYcUGI9f6{$k9dADNuW3i?
z@SmvN=+pSl)VP{{a&c`um*M=<#!Odktk!$YS++9$ncNL$<2O!L{?(7m_se}&UiWz2
zTgO#D=*yjMXS?OQ&v`5I@k=cqsx(t|$O$=r-!$4Qt;gQKefH|r_jc{?N`Uml$hn<D
zr#D_3FQu^P-&v_!_H5hv6v<2PRCY0}lBiuGDbPMSzw6NO)K5;ItAh1>^26_^08Lx+
zg{9S-a|^?BKl;)4E+2pN(I=`)`cxA8Qz9*IEN<M)9pUNJ2N#EJ{?zw#*P6Fz^GbEr
znI?o(0_q8PUJ7m3PFIP_t@I!z;iN-H>WS&^)J+;xmi$<1Dp`E6>sWjJKJRfIYv12K
zcJ@~_{`#@2gKCX9e>JuHEc*UC$KE@8^|AUbg%lMjZd*+)>+f1P<}YWSetjqMu{Lcm
zUOSqt>%QJh)6B=IpVVU4)?$~UrD|cx)vJ2YN~4@9>$%+XT1+zRnU$r~T>{!wY1+)=
zG#M?fr3wAr_B$5+{Bv~|JvDpVvVK}$4o*+4+R9+?hi_l6`<1oD%D6`}eVNtT1ZHk0
z*UN-)&DZj)zP5BC-~0MuB)jr6-)lEEzgOaAmWHH{F0OspTWwX8x29KVy(jg^ykUJ{
zPhL=Hoe}2h=JV)iluWN4=S<S-D<|oARb|+u(w*9O+n27MlfB5~u1+#pu8!b*W!h`Y
z$v@NdmS(~3I;?$5J4fZNTN{_7)*aieQCr(PPBlJ_S*al9ZK?<CSGxsCgYjxIk%d;6
zZ(l>M%e!`=^Qwy7o*dhoJElEcIhsp(dSmmfusPR0w&R-vxsm-_pWIkYO|P_bk*v>5
zsu}mz|E6aNWchTim40>3+g!9CzqZ`Hw?4_(x?_>^VNfSzEuZaK*toV)S;L?jWomeG
zY31g6PX4YoP_?MmbeR0K=~k;?>SC>fR==LAomTZSSJl0T@-E5AHgBu*wl>4g>T0VC
zSBm$fm2K<xce1`(Vpy-l4c}|8VWno)>Rs&(x12h6AH~TzH?@v!OK1A7*0lW_w9C$K
zw#)X*bdA>AEAyRI%Vx9fxvxm=Ym{1h@{IIJ%msKOdCyEWh}^Tahx)sMmPB_A^~<-#
z+LgO~{|?1x*sXEubj~@LEB$I+y6vYV+R@v-U|qwza)P!d^HfsilcQzasnOCWbJ?_H
z9O>bIXqel($;W=|fs9?Pw#1eZRHJ7K(LsI+;^z31jgu$G-IOf3|6rfS<b0bXbnQmh
zu2cET?u+BphLa~R)m`@1^<6o2omSgMX2y6{1tf;M)9$!+zq)a>ep_R*KfAN7T@5Vr
z=fdw=u)Cc-RPwE6vU;*rO)AYcPxhm=N@x1EaWNU!okrI;ux-QU{FPH?^Ec;jSN)At
zMsju51Bms}FYnH4YIis1pImo4WiHvSzWu$nEJv%=RC3pw40vl=wWF7C^ma&OYrd^~
zp`W{LM{P?LC{@_Z<Wfo^o9*Zq(+;xPLY_-Ktrl&WZRb|2PNonYrm(7K!)a}<wv80<
zx7%rXBKgx_PmY_kyC(=MOY6UES9uQYV$P-Y)V$lrmUezWVzYADu9Qj3_1dA~+<Xe%
zoFg@3=G*t)rS~82X5K2Vy1Gj%x^^luYPqdT>FzmlI<)K~MRA)i_Y>X2?zDj)UD{Zg
z?;b+5X=}@)Ju}^YRUSGi7boebEkC7f+m6fMpFXkkn<Z6%u16&0U-7nfoXTw%Zg;;%
zl4mzvPJ5^xq-K|^ZkG!ELQPK7Tc%&Xm0vx2|N47p_w74&@67R8xP3IwM|MhSFvzbM
zoc`eS_fG%U%=gzevI)t>*XupQ+P&e;9JZOPG!>$j&bIX?+si6%UwZG-xARj=kL8@a
zXG^>E&z(Mgx+>nauC}%v)4KHj!Tsm2<|nFdS8lOGQg`on*1xsP!CSX>T>m?H7&0j>
zlIiX4?`=n`r)p2@puc<H{k_;7hm=GM8{75jNn_WBa__Nt=hi#lK6vZu&xX6t?Rf0!
zzNOZ?bBb?Qy|oJGs*={p)N-fp06b`2kM6jxyN}ntW4D6#paV8J@2)L&4-UKIaC*3P
z_NAXonl*E2_jzFIzSDm>wpEMkC&o6X(a}-z*))ab$B34P$3OTW^CYXN$E-`^%{k_~
z-&@-K=;a^fj(RCwlG2K@`*hw;9xp6)r)84LeOt@i&!v4QztOZgPm)X-cIv?9-9)Ne
zX(p`AUt1cbZD&3=m@`$DwW|13>5?*_uBBX;c?o^%(?+T-UG=uR{?nLQ{lqKppS0?<
zH{i#oC)4`^b~6*KTg>TfaB%A6$-0lM!m9m3RXq-D33d%tIXwflTHQF-Q~OFT@aSEC
z)6VtzuF3cO_(h>i{k`(@y|a7Q_s-5gGMH@_^b_60moon0nZ2{W`$vP>e^I0Q@q<Sn
z{&HS*98{di;7t49VDR`4_s%XR?%b)dndbq2ck=h@e>zjC{F(S${P+1y|HNzmWbbEk
zpU?D1;UE3v-~Hmi@2~&em;dn}4}SV*;>g%Z0-qg$r;<NZywu0D8CJaB$JaBgc(IRf
zW?1oRA5Ujk@p2!}WmxfMAAA3I^7_Q{eLRz4#kcx+GQ)~PeH_TJ;<Y~ZWms{rkNp`|
z9PVR2!-~Z|7BZ}OqmQp;Sn)z1-^j4yl|G)zu;QgYp3Si0^*+9yVa1Dmd^5v}SNnK6
z!-|*tcrL?=H~ZN8=d%Ba=lggj!-{Y9@nnV-hx#~>Va02G?8~s?U?2N4tT^1qe1;W^
zeJo^H@kSqC%dp~wKE9D*#VdV0m0`t8eLS0C#p`{1J;RC@`}k&t6|eU3bcPi#_wihY
z6>s*j_n&6}6VLbYOokQT>f^}_D-QK>Aj68+`q-CY#lb%IXIOE#kNFHM7W-Jpu;PtA
zzLsId3w?Ye!-`k>cq+q+m-=`%!;07Y_<DvFFZS`x3@cvk<LL}5Uhd<$3@hI3WA9(i
z{wJRA<CzRAzSYN*8CD$X<3NTLul2Dn!-|7_?9Z^`a3Av-RxI|hkYU9eeS9s$iWmC$
zMuruy^zmuGLGl0l^soMhL9X{!dmQ}Xc<=1+RBRSLJ$}9Iuj-s<uU|cX{s9^Hr%k_i
z(S3XRy4laq%s%|x{I*77damJXJJ)H?OwaTg`aD0`pKQ|$f9uTb!mDRyU;GDWW*`4A
zXJ+5{O53+*GHLH;VUu6~H=En@<>8N;bGKdX-!t8f#$6lwM)vRXQ^(|?{_~Z)=9~UH
z%$JHIH8Mx{Obz?L-%WahBWEUG?-@Q-)4OeJ(|)I4-;sOf+#2zxS>Nx~`ue|T|K!N*
z^GA-%ekHMR<;d)-dyiz=F!xx0Z!*hgV)(iEoawjZ&aZplhX#W?cP7?n^7#*X_dglj
z`Snk`&ky}H<MUrf3fP_(li&Z9<lB3W%pR$<9_<pmknvy4_{9rHX0J?*KQs7)!SngP
z>yaz7&-~3RvtK=bWp?)Zl`Q*%L7Okres6ST)AGvT&gS?p{nc{p{+<~e`Ta*8`N0o<
z@W>-)j^sbNHhj4Ido1_C6<_|v*72w%o><ySv%Ww4#jWZ0`&{#VR{vhi{{8vHR}!C3
zd@1pT#P0u*@-T5A@o?g?#OD%&FWmXUcYo)hhyFspLtpy0S7smihgW6~BwqOMS7!Hq
z^~&s{iT#N$|Eta_KgD<a(sqEH9rZW4QqrdXFZa&=#YE;kxAVM@Wd4e7-e<dcKR9>%
zXKh^nPoHib-tG`rx}Q%}8}syxS@(|H@X7X>{-1w)=x^u09+#-LlFG5Z_}!fUiC6yh
zAGdKeet+_az1gy-Grr>GKAy|4;&Xo^|Gl{XxHs2Am*@SZr}obNQ9joW*D#k(uDd&T
zUaQal^GX}{aN2qPetqu`$-_U-aj*Dd7d3xPuHoT~uXyqoIWH1v8XY{GIFqO&RKvZA
zH~-t-*(bi+T^~<e8EkHUrQweN0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1pW^@bRYl#0002w|Jn!%4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~qUp#uQ`0000W|JO!HaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!#-
z4jl*p00000`M)+of&&K*95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?(qcIZF=00000$p5tw5*#>i
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?utNs|00000K>n|dkl?_90|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KfE_vz000000P=rrgaii;95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=0qoF$000000FeJ{
zBP2L*;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4q%541ONa40D$~o8zI4g0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KZ~!}WAOHXW0089w+6V~_95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fdkl~0|5X4
z001EW*G5Qi;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jjM^9S8sb0002_zcxaG0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNq!T=s*Af0002U|Fsbk95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddDy
zLk9u?0000${;!RY;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jedu9Xb#I00000@_%iF1P2Zr
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxiJ?9hP#00000kpF8VBsg&3z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede
z;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQq
zIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?
z4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!
z0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`
zz<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!K
zaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)
z95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c
z2M!!KaNxj!0|yQqIB?*=fddB)95`^`z<~n?4jede;J|?c2M!!KaNxj!0|yQqIB?*=
zfddB)Xorqb5C)<kfKIg86IfV;TtEpaw(&60B9g++6gj>t*m#FG@L?E!^#~9kK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0{;SiN|LVKeMru^wD!$0rHx&-W#8uK>+xQ%>#`5yFRe_qPIbJM9NK$-`T+VV
B5jg+=

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/flash/flash_loader.sof b/FPGA_firmware/output_files/flash/flash_loader.sof
new file mode 100644
index 0000000000000000000000000000000000000000..27b2c3937d49749fe6041c9ab29b1c0c03784f4d
GIT binary patch
literal 3227565
zcmeEP30w^C8{c%3<VsWwDufPENo9&85h)SUp;UC~qL3kXC_+f&>X-Y<eTC%6kt^iN
zeIF5$@Si8`{u{IH&ZZi*@ALWWHuFBm_kF(a?9Th$O&kXH;eaWU4+)Mf`D`EN9vm7L
zf(;7x_4mSh1^Ng1`gsLoPF}$wzJURles>*x9X-r4%-7EoGc?k}^t$VI>7v_3Prp0n
z&=2eH8|sBwdHRNuv79=bhGao~y#d|ydRz4AYTUJ#p|zC*N0MVe4!3tQwCH0r$g-D}
zet%~N2Vd_1cR$S0J*Wq7ycc!61E)txy~khef7BhjYwHed3O3_Zkrt;B$BnG_t3jb`
z@vjoQ4A1pAKYyQ<`z%{%P3DoN2TwiITfq+kp7>c~j#B9`#=*!V3C^+W9XJ}Cft|R~
zzy0v+=@mlu<Lcuc;-ll?8$ga2A5NGM`(nq|YrqKSm+}=)jzmj1<lK|ua00_ZgTg{x
z$B;~i=#KFt(_H-m-95d6b;f%7awe|2w`xReu5pty5577K`^M>Y@~E7XrF8D1l>Ud`
zm^<EC>eWd0Zhf1a@G&Wadlu&&#N`f}6||lmq2dv8DgQyw+3mv@8Z=uS-K*u~|Mq2E
zm=OJ7YA>JFPA^6eF=;fucRTMH>fy<jk2W22Rf&EX^(&yuivBJpnmW6Zrg=3#dh2jP
z$eP0!);~}8ZQi|L=Iv1TVbA_sbZ~gUtZNUy=g<Cp32(jV%*=<8n{D1mXRIx@klH@2
zjm1HA<MU@G-`OzLIb`U73$a(sb&?B-$3vgJh;xv1X*#*7LgO>tZ#w%XsrNp1{j^5p
z$b@S<vR*7dtFd~+s=T<MM-kUgMcm$Vb-3S8N4uwrLtNWi{ipX~lkQ$!MVAJ@nl+T&
zgXt$u`F<qgr0dV&+dn)uxNq8dLM!ixw$JK)b7=6X-s3K9TK?2IC-Hu++m|<*=H}9N
zPp*tm4X=CD+1FpqvEh(ka|1i#3tOm2Cf)5d*~fWIKZ6d<`&xHje?8h*eZZM<4l9lh
z(ixUF?vcF5l%E|G+ilL9w^iG9?&Qx0^+L~Xu#i00YVGFnsoNek)Ll1s#;EB1Up9vZ
z7TC>9h%_>BJ^M{@O2?Qho!0d3k}9X6;r;WW+UqSvzTLF@O_lc=p0fA;;s2W6H{X#{
zIR0>i&T0Lw1ID>6%uLXG)n>dwX2`SIi;lGTNMxlg>KoK42~V=I$oRbX@ujHAhXRkj
z+P>wAe4B6kzg@mp=Rm>E=FwqaRkj+c6itX-`#|PY-aCDTTsM{bX0zN?71kd<qc=9%
zeeze8On<%p?^>SP&?wq4>elQAO<hi1G)ph+(@|&a=?MD+k^6}55vQ;I{Mx0Z`VHAR
z&ul^yQ?ANJr-Tmkwi)ZM*FMv#oBGlwwy_hGeJr$$_l*qy>e>0M)EOt^BZqHZUuPE-
z>Mxry#3G9vNq6gr?cS)Ya9|fX+Dj#<*Bn3JRx)>owKG1{P~kws-utFY9Be!qd!L~)
z$6zRf1eJY@@|?WqW<GKYO6ze%DInVUM~eB&PFCCM%UEUJ_;2jKJ?$^oX`P>T=+d?6
zr}sPvTRml%sjSQM?!@VkTVbnv4KuYSPo|#^xf`~6^f1$Q<jJ}GRbRIo*<Xn6Yv{K*
z)h@#J%SgvD<2U#&yAWuXJJfJN^S9?y^zV(h-SwGe$HdIu?q1iHTW#@c;n08SfUut%
z_nnj3uD>fU=fE?YZ`;P-i+?cU^-Aj%nrp|kym)W;P1AAO5ABbt4Q_Ps{sFDqgQg~p
zn6b&GNPAe$2EC@8UVj{4H>G~N6JgoQmJK+y#?{onRhoO=r`N;Zes}zIV5{8bsPsE#
z=MPBS$W0rw^qY+1I0xf;L^su|CMjKQX2|aKOa5%Ra@n|}aVbZK>u&Jfm{ZR;H-#Kh
z_9chZhrj>q|KrA#;v@fkz1l9Y=YdFz6Q;LEypvhs?sRFCv)cxjV{i7hv)may^=i_b
z{o|hhSNHV$xDA29?vrm%x%cqx$7?N~`X<L_soyu78nt8pw6^u83=6zDwbQT3lkYz|
z({y*{`>pO%^>)d88#Tmm^(1Lr_jO24!o2M-KkDaRe&nD33cDY*v7^iGHB+v6Mr;_-
zX0i0K?N2Ub?&#k#zFA|n)SexUy2PFNvg$*teC6GpJp1fE`TXXGi+hKrf46Nvs^59d
z4kM4(domSksr<I&t&sEkt<bEFptr&hKTnP+`Q#cD95~i%bf~Luz?eYux)@e62qz(M
zR^}Y@333nhF>BKX3vl=MB7gq&lM(JA@CNPg6%gtg?(P@nRhn6n{ihEL^_m!J*2dn!
z*}>J$Vt^G^_6-{AYvJJPFmO;W8@oOOF@4P1%Fb%Ag`>?tJ6D_Dn7(0m{jOaMjPwoK
z=<=|2{{-MpTNj$+HpQn6aQlRLn7D_92ExH)cfU|q7#!p7VKUM;AS5(63|exBn=cFo
z`;K;<;2Y}W8W8B|<?8JfV8TDB4d&<T5$qluVb-QhNiJ*U<na0_ryXWomcjdjN|6~e
z<?%-n`ul`>rSxe6cina+cimCsZQ9dA*Ea}~x*B<P?dq;?s9R<>Iw65UqhT?~+wWU-
zUx&xWUwRz3%=+(MgCxlpS_3w&==VH%Pvb^f@*$4?OS5)K`vm#zZ*ZtX%CGOQb|w|h
ze{0-(Z8wMPVapz9zEuBsE#!N`d)xY^7Fm5}{d{@Ad7PSLYR6gg3ce3Kv;WhH!#Vl7
z3D$3q1)O?n8SUWHVwq%UgnUo+td(tVuhhPGE@t$HIicOIHj#-*?6hIB$xr_;H{TR~
zluP^d`JK9oO3vW$;?>FDcI8O5x}=)-K=S7J&MzM9JTW**X5QK!U9L{sy7}yhZM$XS
zqO4ozZONUQet3fU-T2INzT2*B?sjS1#ZNI`Tj|_iv+dqnw?QjqntoK#dzXH7kW2ks
zJZH%C-rf`Z-pf1e(>tt~X1cG({!eqSzy4+Z=F3Kl=aI%mF*_x5FYS@n{k3e(la*Sp
zzwTWz+P(F@*J&&6PF>us*{D$ye)<{87!6GdPwEyoLOU(Hv7_#L&x^C(9-3+sVBwM(
zJXBXb>-2=;j&&Q{mUAs^@GYUG_LH6`e`;;}vS+{(P5XJ43Tdy`PFnslGX1km!zK@t
z>Mh%!H)Q3#g6~JS`2IIxqTh}yqa5pKPqwV9cGh--S+iBIl5gile-Hjt-11fSVs+!`
zUw3~r?UmK-OS4&PEu3S=zm0dUf30Pp>coXRPZTtNw<<Z+X57f3@i|KmWe#7yZ~5*|
zO7E;YVA^T2{--VLt?MeW?8Q+Tv(CdMZx*;J4VrOy*oU(bMEZ1B7oQ%3qzyyWikH;i
zS(K@CYyGgqI}5jVRFS!HBtQSfXYW&6b`@+i_-<))+qm%$i|+oNm0MlDe0ju#oth8M
z&5O+S+rGd)2lJXgI8$%q#f#ba>E>z!Bd2WYaZvs8&2PO9HTIrsTa>>z;it-%XRd~e
zr=HjRvFGPxb2ZnC^Db_0_UsPlNIzoUhZ&iXrzEm^*q&V7MC#%g$vErcElUqKzA!PH
zb9V8u);A(Jo!xR@w46M0vhlB5#d1?QEv0X$4>)vOxoP9UC$bu(x9gR(<>$mvajjc^
zd-0&}seHG=p*}6=Y?sv?c5`%eyN1cPEOIvV7_hIE#>F`O9?j-%8~nIc@t}{AzD6G`
zhpn8ou$g>>Q<wK$UvBBRrBRn*`(u9HQ|NOwaDUS3uB-Y+H+1^i>~+%F&EIA(-_Xvp
z`}VCiQ+s?onil83VWjDm<0~xYezmZ5INaB7BOZ~o>gK7Jp<V8!I;fgnHD7bLuWLZh
zRw-t$?Y0MM?TH%r=#-wD+bgprD$8Z`I!~NE^jfrgkLL51?mD6?pDFqD?p52mOI`iP
zG^yLxa704i^i?Bd_7|-Wn0#%^65Mp5cAM$jCdSHS&+a&DYf$9+-X0QRQQhZHRUi0M
z<x{G5{OG4?ZrwW%zpvWkmX<|5>si^Ot<PxR{<6PY(_TYep7b3wG`8*dF1;))A9Y_C
zH1zQ7^sah+Rny<6xIdmVAzv*v#J3<u@^Rb#^P-y!jqiLsOFMG=v;c+nw^K7Nw|?DT
z&1-a%Yd_zFcWrlgrN$#WBGdA9Vd1%b{_W)&B<J2xc)Cb`UxbI&x05TPmv@`zd}{e2
zlT(r_PTy*hn;p?({^=Wiqqa9{BJX-(V`{wPl*O9|eaTYZc-f)V>)Zyn4P<pA*J%A(
zJon^>pLP7(#Mo}0r=i+$O?Z;wM8DQCzB9Ad1{_i;+B_{Rc~skbKJHU@In}d$w^(BR
z)JRX&+qd*R=WJYNnVu0gZ?F=lKUOE})XmJfhrXR~IpTG3epBT`Hxq81acw2rROjyZ
z7Wtot4(oO5M2hJO52E+pC8IY)otbRXT5?2e`sEDo;hBw3Hg=Qgyw2~9)cpSS8?M`Z
zMJ_tz#eDhbPa!I5TU|A+BRY-tU+icmy)-LlP=@W{E*VmeQ5o8s74#*BaCX_B->x;<
zFnIa(@T3)Mvfd=jT<mLc=XzY@sBwM6=lI{8v8;FCqt{2?Hy9^@_q+D`Xy5s{>$=sO
z{pO(NYs1Vs=k|H(DIPQX+-%iXLnDuz`+2H6$H(dq3fi&f+|zfT(jL5RF!g=HqdAu)
z8YNo4Od0Cea_+^p53}mIjw<{(Eq>1q|F+u==l4G{f2K*4<Z#>6(Q6kr7^QBzAoyWa
zTdTH>Ct8IDYyW&C<6hsxD^YRnfSDgsB;VOj%xXQ67+j#dPpu0!$=AP^>zi)%U&gM@
zS2TQUGr=?>wP}loquk7#<!#lYWG@ctb0u?I?1{9HFc;I9k56ZsDmL-h<YThrYdf3e
zC#C9iN%Z?rXO!CARG--8#@SN!7r!r%-05v|<f+;DW!@)G*{a61D$*PC=Cpl7tY_N8
z8HOrEvC8&SdB@%A*E!qZZSXwRk$1+{DT*;ndZ=Z!hx2W1{rAq%iZ66?3nYxLX!J5Q
zQ)}P-z_=%i!+SKCa7ssN&d93)+k%WnoHpnhIiN?B!UV_bO2dQCNnM#EF+crNQMXe+
z+zjq68ntJ2yN9dC99ZAHpvMB-bS`cxAGvzwq(cuE24ugVGNW0OhKe6&UYoBlZ~Dor
z7UmhBR5Il79j+a<)tfA`%QonuLuS7G+QYZ^#>UeoHY%7uf4=Iw7cxK29>8o*HoG6F
zo|b;Dga41ZXB#9I4#<feIq_HA8fE7;J&!Cs7iHkj8MR!y_3Tfbf;Zd!C{`G?Jh$~g
zz0WG|64z}kzLU6j@voi@CiUDU^`>W!n?~!WfAcr(a`ols4G$;YU!!Pp@7VPfE(;nM
zNI3f~Pw8>p<CJ6X7i}z?H9RyY`;*m++bcLd8f0e$CO(^&{Wx+(WaQws*%t~Low*Pj
z=%jz@ePN(WPTKR9D-IO3Y-V{<e&*GBcSGNeIWMWPvC9(ufZKaUZC~7N?eYdz`i<Y(
zJ9X}HezeWDRmn}7cJAKRKi)(m;MGdQ$<a|`ope4#&RG*D`zEm4F%QL^-m42&JU^+b
z+%G|O-{udqk~X>|<z8G9`#Lq%GVS1=@#;6)e-GY{>jbFjwk&#e>vVeXI?cc?n@`y$
zKkdEM$7yNi-Se?dJDTiR-FSTAf`MTgGaf3pllk7PM{Ai=o$VANBK9^OE0_1^N&8m;
zGIdXN)=YGnn_{g0#Or}wYHK1Ue)PLJE%q$&vkTWujPLT~K#z5qox9DwvR&C&dvE%c
zh2)QRkZ_^SgNEItg62veYdiMB;N9JCFZHuKANQEdH8RrgnwYFsf16Z`_6P2!9(Q`N
zeYDRvXTy>IX}oHZQvYLbukN9q8Ur@m$yYNm$$YXbW1h{^OY7_5gExN}D(QISlI*7M
z^^Y96^xvl^?e1wdZQ7#n!O<pnc6*HYlDyw*SLUsOGiByYY}K?y`$tn8eca}_9=7b&
zPrHvs!&5<>rH?h=vU2;zNsfmCFUVcdU*++|vXgJ0HmYjJA1f3VE?x4%w0}~k-9&HY
zxDS)RBuZzryc{}d=caQ(ljhxdlxB)$r#OC@zj1!SxC0|6swsK&yyhRjG~t=co;w!~
zE!r5?+~jKNrZ*}v$EO;Mx)M0<W8=eLH1>=g_Sm%H@Qaf?!Vc_M-FL$3w3Id7Mm~tU
z-aEX@sGb|=uF>q+#@oH;0rxHQ&aPM)cb&7Zw{b#`=^K|jw7u13n&*9`W$t$M+-);1
z4area*y{W-VrtQ`=}n3?Cxj$@ZIEZb^2@hfUGksCTy?!3`806Dn;!-Svfoed-_`YX
z?1syyf^N*NQ(!Rpd)qZp!GXpX&sfG-E4P<?d}70`M&t5+t$Z^y{)g?)<f&JF89!Mv
zd4aF-s|&N^cZHhCPwn+A=+gSBtL;pV26!7L$o#le96o&6f*%V{yLEYcHSF5kyGmNY
z2B$VEkG^}?&2Z(_+ZM4|2d3V5@A7$LL|~hT8?W9QIeWSF-n*?Pn8y}f_3N_S_TITA
zlN*PbuCeR0{#aq%`{o7jCeH8Nf5)%q?sZ)^C`c=ePwcX!Aktx#L9@W+h3*61D78GV
z_|WkAg<ty;hK$Ma3%Od{E=qHK1Dj3zXMEM4WbAtB@*8E{(K9wbowZGSROTSBj>o>H
z?eIG}%)Q;BffLjFIXr3nF)Mz~m)>b-u7pl@&^fF8ZARMa1kI`OyEn&-U*+^-O0HXo
zQ)~BtkWp)8w=0_tw(?k;ny_r~@V+zR)h~{bm~CP+XOQ<w6UWAc(d8Bkp7}ohG5e!R
zuv(`KgXf<gkGFsC-(bFc$i()~f)3AFHP+AR>RRV7y{zsm3;W=UbyMy#r@h1QHrviy
z)@|tgIZxX*v42xMa(v9m1D|g08+NdF^QFJSS7^PKH$SR(TgSkw!^f?!LcLa<II`4n
z@{^Z09Q(QJroHK6TSwX2HCYR@S~Em$m+_b4rAi$>t{PG_@0$JQ{;o?lY#lyj#G)m~
zhmnUD=1m!K#WC5_bxG>hL*(I-<3X;|SA}b(EY|SK`EX}mN*$}>b-lfYd?XKxHx_#Y
zpWpm^f6}Ut%?e@~Egf<ru;a>)37=yI<ZsQ5x^pqV`1B8t&DeV5-0;oVgs?QJ?r;0|
z-#FyNb|39Q?{rh@hFdxOTsL+6kevqIpX&Z-<{*7|U59O)yp+y8H(1__$m$W*G|)GH
z&lK#-?u=2&Mt(zruP3Cod6_u#Lz89d2bU}}was2UPU(~S@r|KpH;=VAeD}oTukwyk
zAL?eiSrj`SYTsr5(#0CPrVqV6-fc|Jvq!V-^OjC?Gs{*V>>26&#7|GsZtk7u2lH-!
z7~5&e%L~Vv^q3!%JG_(m>NRWjzjL$A^cXTQaaGG^-EUpnsyVRZo;_#0@l*4L4qbij
z%&CYccB`Uoj3yje741H+XuxrUW-SZW8fclmSaT}+%j65e?_2MmFx<CJ{ozY`xz2nZ
zu;`fP*P+@42}2K=-S#%z)!*iw)5VMy|E*qr^|blUW5HXF&Rz7V`yJ1Io_Wbh$<J5+
z*V;BMr*N(6h4<rq7V3<<khP=Xnfnon8E!XcZ3wv=`N{2ogR$yG!&V=keT?g>{>jM1
zP$E#ahl%4-HLaIzUghb&O0GBk?f8*ezTd*99JT(Cq22O8>xb!@yQD|me6g+Vd156o
zdg<OHhu(i)SZD358DC<e18)u;qaVAd;JE9l-HET8OAonu(K9G1tM9Dw8-|^e>#}Q%
z;^d2k(W^r)77mH3r?Ya1^uq;PGEWV9yScTkzSouPJ+DR_Sk_uCQMvxxwj;BmKXPV_
zJNM~@+|9+hDKl0SxExO!ZZj*nQQPL@UvB90vE}@!&yJ-{YJO^ud#lX%nmL!I?MT`i
zk@Voq25<8T$}6SYYmc&cbJnLwYs|zSO~SgZpBU`tnX;|b!+?*kn#xUxe}1LmJ1y7#
z^6||NL?7O}+<ex&`dR~2<Zs*N4*t~GMtj$?EnAN)-=#3RamvT!t}FGHn#L~FTRK@^
zv%ltEC&!!3_AR;Zpn7qGw@q-ajYG)$h69fHem}Ut<<x1HM2(~|N2i6l+YIQq&S|b$
z_pYw4(HnLS7`k59?1z28op&Ce_RRO{WU#{^VvyCXh`2RpW=ucmUZ=jfMg78%{u>Xj
zTxL7yYVQeou~&*hq!xOg*PW|*X8n7YhW64Y&naEA*}N)e@IcprcH4VtP4>Kd?P<>E
zPj@yq?U!?RZ7Z#i0Y2NlMXkE9ZiThd#djO6R)u%<H9Rk?yJL-$N%M}{g<B<#*P9n7
zH$CJ0%~f3sK6Hrah3y)6V7$Tj!7nG>^X(P$DcF3xQ-@tUwgnWw?;UI~&ZNLXPxW*9
z)aOYZKg`VjawzzmY1cCgl5-SS%-AH=U}?-7zxe&1#twEKfAq>>iPuwH9iD&CRM_mc
zujx!_n?pa|k25<lJ4DTI#+~ujL#<t1j0?0h7AEI@9(K+C@co<q2Qngq>pHji^-E&9
z%GtFK8^ebZ$|WC4ILUK3Wj|b^d<Ky;VnU*Evsv#ybu9R{Ii%s5t7;}$pF7pL<$gn^
z&H?{tvoxdMyyz&?%pzrlYtKfrZ!Ns6xS;h~qi&XRM{`G9Ue-iu+wrIYY9ENn)6Kqy
zY_#7tloQ<fa^}0j5HGh-yB*q7_YNGs&Nkcg1y+B6Sx=76s^rT{7fGHw`f_4+pD5|#
z^zA=P{deUxR4ckwH1gn$_XYjFOQrps5Lwq`b<b%QD;sw;AEKJ~Xt$zy=t-==K5{xC
zKUr$oa~Y+>oLoaiAMH?1xV61}L28k#vDttu|C~hc8%0C*MmhVB{23AT)BCaCyH3_I
z!D^nnvIwI(jV~*z_vVE9hc`Ad@3pvNO7?%#C7-lAd2rg=<u3Nh-7dv7xxGY6OEzu#
znGR!rwK7lNEO~GIkYLHKeWJD~Z``BMAY0!4@c8^q`MV;*ZyS%h@u*4oLPM1(JbaRr
z`t;#@3*wS2bvF11?w9Pj!Taj^RJ^~QSzq0L4dN#~ELdD<WUCoFWAF0jLwqePx9kgA
zcz(Ot%TagaB%Keb&w1SfZ!r0lwQW)C)}l?9WIHHl>}aIBQhmGb=XYQ1?>#?e^h$ki
zmb&xL=|r=xC(LtIKmUwy$unuS!~A127yHXrjgMp$AJU#@IrQ<2qbnb_X?Ezj_VK{R
zw_Zq$NR@1NE8_08uNLc9H~2ie`%jgFXJ<>iTC1PdGR$;Ee9r<?S&IoaVZ$%_^=_BD
z&nHT&?ZR<gL)t_qZ5V%9|M}xI=N&uM#&c#X9&NI+qd}kBWAu||y=w1OH~RZ$E9)U%
z`a|)IkNI&{&Uj+fn`DhQP8L0jTA2<>8k2v;CMcGOjhZz_>a2{Ew8YVQoEGnW<?}ao
zEsp0LQtsTg?v1Qj@t(bwNZSvSc(?8TVflNBTMwRCmAGo+f@bfZW?oivJ7{*K!>7^O
z*EV#X(?2Uw;pmUy>rcI@=lDSN+TwQh%iaw4I+t}b>}}^RquY57>Dl{{znp*amPT{Z
zp4qQiYjfyC^L6JQ%qdP7_w@UbbWLnq+ra@(4m{L&n7MfGPSsBJeAPC#d-p7Ke4J^<
z+rouX+wrM$qD`}+CA$7P5x(=J(;ZDi9nMng;H{TGH>}?+B`kJpt1~YhSIB!Def9jx
zp&?FweVZs1zqd&0=lE>|eotrrJ?$$-&7EhTeLXts>s`~_xBIR=E>JZYbY;QB^ZBZi
z9D?6{Eo!~uQS{Ld%NA%|QoVTLo?e#Ro1dec{JIPdzmSz|G$pRPb79+rok6Z9nQm93
zV%m<;$+vnue@n5VL8B=@vwIsVKJ)5+U%SKSk(=i{)cIJv$QxTBZ~4w_MBkn95obdU
zkDF!uGH!Lk)FWz!_5GFDzLg)F9h`sKP-|=GwU67(`n(!wbZ&)xr!#w^maq5OmbJI#
z^S!r5_01aPo)CF-We1hrE)%CMn<=L+X=-uDW$UryaW_Bce+}DkMCQ(s4&OskY<jJe
z_fND7I@fV_(uE`AOlB<^`R=Sn+MR)lEhILX6za{KF-U?Kq@H~)G&NzVV;$=kdEIhV
zUpxt3rr-GKdf6wkXH@EVZ9Hv#p<%vpfxTMvtou7WcAPBI==y8gw6MTQkBvH<tLG9q
z_T0<5%{=|HzPaZvSAO!%YE<s}XwM!eCA#})XSFOIf2&o4PY2yR9q|4sopQJDzN%An
zcjT8%3(q!}9B_TW-a9?B-#_ZnGVtR{?YtiMw$*iNoOi44x|jRM|2J>a_Fjs{C$0}U
zH^1)L^<C_gx_(O3P%#?O`PzkDzEYR+!k6qCvv7)M^WZmaq~GQ(s_&V5+N$jq>CJ6z
z`~6&X_5FuQeHK}`E_#3Lx&7k8d)dYYuRh$IFl$)<q45urU7o1gJ+o@9MQj?|Z|LKq
zDK_tv57!IZu+Zbx)dxK$4%b=Ksjta|dyNN-%JRGM<Ltb``^_BUj`cgVuIZkyTSg}2
zu79Ded}?Etxca-2`*~Wu4l&!aLr%JWyPJ{&jKa4})v-QqKf8Uv=kI+!^(!8uJo5B~
zxi3b>#)sJ~s;4`{?CiacN9MKkp3`M&vtHp_R>pQ88b9AX#&@ali_>Ett&p2~=4;*D
z$6jwuR`&JZ_T%)o)2F?D>|SBrP%`Q0pkW^x_I=~@=HcYIM#slHURt;Xe;(m@s$;PC
zj=ft==MB34LjC5rbJ;80yS9C$y>5H6Jv*!o=bC246+PM>v$1>9RpqF68gq_Z9lFA(
zL+;hM@w3Tq<CQ<Pw|#DsFL&$6!^k_<+6UjXH>khT$7jOnf*lbJU9H~MUp{@)E&rX1
zZ9BZN|7omI*CY1MyCGIeyB<&0NKo(nwxIujR@rlWJ{V2E+RbXkw#CN^!s6R*89pfO
z6LDa5an|~E8!t+RFI*(~EoSTF_)mqMGG0xQsQc+alQEZjEl8eu^@l_syN`7|53P-T
zdN6#BWaES3Pj4Uol|SXymLHjBEAJS}_BR`@Bk|(q^|ohaPMvxB_4E4uh0&8jEnhcw
z>lm86W=zE9)|=`?Z5p(%SA(O9-`nk(?6;p2S<gg9wLoECQiD6)-K>1`l_j$J%$PAz
zImIb0;)_OjC%?lJQgT)qJ?Uc`(B-Mti0%5%LdFF&O0hDWVsLVq^X|i&n|3{yaG+a%
z=Xy)`I+7n!rbfw|KWjK=Zp&=DH8~y3<|m%Cjhd!BF6PU8>utlA#GO4E)qm!`Cw9Fe
z1C}Xy&$+KU`qa`w>s2qV%^J~OzhB>1tM4w)X=n9lIIeS~nckPy7d;XVOqO))Fy8sm
z?hgk>TK(7Q;lV@2od&IZ^SNM|{rOQnS{!ctL}z*Dj2o@nZd%ZK((|+;&p7GBrx$Kk
zPzZDDbU}UW<$j%~xlDA|-1(rx&c-s^CH6Iv(bfENt-c}_zPn)q&AxMAG`ga>&bIe)
z$=*FJbPcpFFP*42!zE^kl1}T9mIr2h_&!Z<=BP}ih5bxbPTty*P<Hr!3pv-(MU$q=
zSW6!xPAph_LNnS{CP5);phAG>#k|ZImAjpqkL+^5Gw592*NnU|ISK*C=A7{U9i-E|
zc(uypW!<7Lhr0!BQI4PYW0lE6mBaGOM-Tewm*^ZGe|koI+Pg&aUB>b8hSxT<c)nwB
zzlVAGn_6zro~!8b=F!W~p6_1AYp4YrH~jg;W6QEJ=5trZ_E#@#zo$j2&D%!<^QMh*
z?2&Hn+duxgj;zMgZtvgJal#w<<#x&$)U5Bqbvp*9TueK5!hD<m&V$64$hVDUF1+==
z(*N_iq1$uzHd|BlskQ$j>oqrink2+ekxYzyWNC6y<xrvb9F4>q6K43%9(!ZiV!Ppc
zPhSq(Kk%pI-LHx6k4pAlS|xigkGdSr_>hPY-H?cYP#^O5H~#oV3{NkQFmLYnK`zcA
ziD#9gzV3LjW##M(z0x8sE_u`;qmBI{C5a^&UuTZBuze?AXQs@+$y0y49do6TO^%1h
zv;|v6N*7p8_5N10O1bN{<5TU_e{aS{|9>;~WVDx0-}iyqQy;9}+dCoo<yngsD<h&f
zBaN+EbsR0bc+$1}<ORib3m3Y4A3f7_F=s$WTbHO*Lv1$&Yx8~PPUf#CL_YnZkoNP_
zPqR4Fsdb~%wB5R$xDlp)Bpx<p!}0Vc=5?|{B<Hwr{8eQOU{iL+zCpp(qIMI1nZMod
z9JqSuYoi-QVSC5_xcT&{>w=h#gBONBH9qTckuZ{R`2VI%r?pK?^MVdJoNw}DvhugS
zKk~kzrDn$Mpgu7wSa#i(-Y;@KrVM$JJ#J^eBP*=F_pxiLd2-7<({V{@V{fce-uhB9
z)H3wW(<T=0gV$s@bv~9pFV!bsa(CdF?AED6YzI0w3~v4Q`my@OamzM%+fQBY7P)xI
z2Jdr8LAh<rQ&h%<#3d@-A-7CE@{fCdkZ@9eVYfLl&!NLs3E%7A6T+s&>jdZ&ZdsW6
zykV@=f43q`rG~8eo|9@jc6L@<wJEdW?&WW4*Rsw_ZG-kU>%BeZI<I@bE&0~N!RJo2
zTGuu3$gKEXc9)Xv;%pmAr_R>Oj=Y{9DxZJ$lbY1MZYnR6LgqwwN%7OQNDtU)S8r&m
z7R@exdYu_@%+%-6#I`Sd<|HSpFP{GD;r;N)>(_c2-+t8NZ2h1QeLqhx)=yK~l=-P;
zQFF(qQK7eN`tR;o@H6?B?}Tw5j?Y<nS2a|z2|l<$Rg>`7_;%mXDMAH5llW%sxo`D@
zN6+ts<NH=^w!ufg>63p+r%&4RZd?3yL;YX$)M>Fp;_`~mb`J*zw7mH_wf>=;$2x}R
z67G*V_O-zRwWg85XBAc%nCXR#on(G=?<@PY&6X-W*4SXXCtj1YaKFXR&#M-g;u<~<
zua7r7x$e$j;=jHP@<N@us?U&WzNtm3VruFTm28jw*nOpeZ_<MM4M>aAI<oNKsvU`+
z>uzb-?rpxON5EE<AtNq6yS=oz!n^$w)ax(Ryi=#mvRLa*M`b#V4j;5QaHxe^DDf@Z
zw`r>+>92ByFRc4ECH(MSyNP{m2(6;D*#|mY{BFZ>iTTp->5JDbmNf0<C}poFogZ@{
zCMDzZ)B7%6Hz!>xa6I&NiOHJm=MHu6ZMBbF5v(%ef!_M@+wy#FIGtb4aZ+$|X?efX
zyes$Sp7W57&uq~4y`FF1{>SmpN9Er}v>0;EPJ3MA56WxbOmD8*TD3@Dspsr$nM2yq
za^qU&H($9`bye$?lZQU(xmWhVGKuZ_R}K4}udimbO6$n3lx<6iK!=R4!K)9fxpI1o
z-kIg<y65s_3apLK8knxMU-8SM$F1Zo_motJ5+~bs&wO6g>ATUkNuE=BE^zRYnG<m%
zHvZrcr@L_&RyftV`_j~pYb3fIzI$lM^gxq+3#Z*Yv+VNXqT-it_gsHmpi|#5^wjks
z_D!PJ8*SUs{)bEt4TH&PO{2zK$?#gg;$ZVJ-6annPw2RM@Zj)O3Db;@Iv86O8YFl=
zG&jn0%Z`d^Jw`F#d3@%8s8jQ$*7WSMXhF2sur0Q25_5WgjBcYfVbSw}tEPF%$Q}IZ
z*ZPFr$GF>Vj+<rvggxlhVwKpVo#StfS$6#V(~*9oPevMbeqe$P{`Iuo>bvbVBjYmE
ztjD>$+@UV7e5ao81J#1TJBAu)&hl$ED%q>GW&eHe4&TXmHCr-5UNyv3=DclCqS5G{
z|E&n^*LAJ`HK~LnAJXDigk98%>ypsJP(JMYOZ$d#o1-Tf^p%t5$eor*>fh_=*5pRU
zeXMs}311tZ)oHZEdFuve8`w3h<294qgDT}~6xf@}E;zF0^r)GiZG3*#lYD*ui`I@t
zi<|A9-63cG_MrH!{@ou8P`$R$^!QoZNnQKyYioj8Z`}Q6uB&WD?6;?S#Lf;D{k{G6
z-P^En%7=po3p&_5nZH)+RZ8y5R=yMR)dwaVNs*hlX;0%5V`PlGO>h6h@SS6Rdf3_4
z?Uo<XPPCVe=$$D)eN5C+>Gg*l3@)l|>651rFi>Sg@SDb`26;5@kQ!}mGAK1BrjJuS
z$9A)p6tB9PP$=oW$bD+^-6>gZHS!bJjvw>n!`mLcI;Cvtuw#&JzXXSg_H&x2JMOix
zCikGuFPq$%so~sW`Jv(mW}P}GEa`OC<mS7%T06Y<y^8YaJ^6inhqJDpQ<9rr`#xlQ
zug~_OO}1Qn>XxeFVX>&a<hIM7FZ{&YzX-kBa_pg94+=w?|LCJ=fA`_n1<w`~-sogJ
zZ)U?QBV!#xBa)l6l$#WHc<96?W|x$j{?yUBo#dkvyijYdd(5V#6R*Zx$@skoeU(2i
zXJMmFN$ZavI&$dHc2}cMavrIPy{vR5N;OJsN`9*Q?BWi!nR}jVXM450@<Gzd#HVw|
zSWITKg*U#Zv#N>1{4u?^w|Nz*KgH~-ji>XhyUo73bh_x<Z$#l;8>Md+u3kA^vvVvn
z&6Z7*nYY|}m`S_S4R_vt8hN<w(vc?T>qKj{$aT?wJFa;~Gy6%>o88)fspk|dKhx}d
ztATT;-+CNAVn{>$&5GD3S1lYjd5<lMyEI4UK~ouZ2gh65FGF07y6bOl+Iy00#^)!x
zv2$_^@8nKesHVMU$%&zwv6n6V?jPQy7i)X*E2rOAS(P5=>czd(idyzOx3yybC%MPp
zJ!$q}_R-wHyX!ap_?X@)S5GQ=jX^A?I=|)32RCEyKWgyqN^|vr#J22dQNz8=EeA^%
z5C6|^oO!O|ckh_UlI>@U==zgn?wpBztG09P{)sU}n5LzrX+4L|xmQvq>+igmvtn$B
z^P+)cKXw>mzA>xw`Qjmo10`birA3;h=N$B$>Zp24!!>VT(0Ql9x6f<;H?!#i-L<h^
zbu)T5NWJ#o=zar7+fO{#&`00-u1;a<kQg0}ojY6YIl1l4CClOa4k!(U{pZ7ela*Wx
zHsv`*&ezcxJusmEnfSqvoTiVA&~<y%YxrrMmmiz%>}Qjp>7u+^$7q+svL^=*{_2$4
z_4ezR-5fehdh7GZZqea&`;>-S&$sbcxZUHw8wV|&3Y1k}x%s5_8m&1Y^~cq5Hn(QV
zIyL&Ds`+My<bI_un8NC;Tc1?bPTV@z$8?EBzj-<x4sCd`c-;ez)nyx91G`bL@_ibG
zcOJYr$mXP`e1b-Cc;DrVM`dcLeV*7=e)Nt}l=1t@jRHnTPBxacRyU81R@IbEP#YN>
zbnZmp+-Ozjkf6uTYIi$zKky`PakQ;sl&#v`3oD}&FF(rr1m`;7*q?FYxpT;eZ!OjC
zZa&@rw4%42@reM-3;OoI_n|lHdB421rYPf49Xsumx32!ntYr1yJ@TEjyWpEmqlMx7
z7xX-MYxBmXm)qnoS|Qo0sbQUN&0UJ+O|xVA$lf|L=cVS}QxeWzk6gOCscXbv?3_3*
zRbIpU%FqrD`u@#s&E8gL#LDbZcINKs7ozkNtz1vs)6q5G`+T(LqqbvwT$hcVzGd7#
z?R~*XP6{r?ZF}#&nAs!q`r20)V^SvS$Y1?-+N<E%(8tfB2L-wYzm0kA<iD-Rd5hK|
zsR13j)IXj1W9s?_u7etK(qvUjcBLGSx!Enww9?~R@dGD+-?<Lnh>+GwCy$W*pMg3A
z`HSUp|34RWB&8(Lo6`^{e<xjvBk}tO8D3hU4k3rtnZs$r{ZUf3)CUN>u(A&FcP|-O
z89Y9)5=tC7jGPg&|1%&bVM!=q3^|dLt23RzFkDWl&J0d#_(2vbtw8=zQj(IAu)s@y
zK-p4XnZy4_{~rAROavVLACC{LfIQ?v3?K#&1Bd~{0AiqG43Hl@BSQ=z1}cF8f|-h`
z1SC`fF@P9A3?K#&1Bd~{K#gU9`&UhBYy)WGRl)$nFCwZ08x^fG1|+JiGAdkQ28ar0
zqC~_1VgNCK7(fgl1`q>c!$6a&>l807EmL(6sB+aXfIiHq8eUOV!~kLdF@P9A3?K#&
z1Bd}e46yVa3QMqzDEaq-;2RNO42P*P{{1ls1hqks5AMHs!Qq(Zz+jXMQW8oT!NFb0
zuuxLWje!2)U)^AE!01~qxCprGghN*8s$g(Tb5Iw*{8fi!fyNwGU>W2rhXLtw#;bUk
zCD<zN3YA9;AO;WvA~HaT7+*=@EWuXN>`@uS04oe&tf2nhsj~xJ15s&$L}(A7hG;s4
z9K#`#=D=W-3qn;=qN!!(uz)D$MnM0f$yUhVt`iO?u#}`>@I-S^WUEa1s}9LRjaHq^
zz#xm_fB|HP0mJ}e05O0VKnx%T5Cez-#DEwwKv4#zN<}ygG@U}G;E+ahU@*!Bp(-iS
zWGmF6RVT-Anga&J+z9Bu+GHzzT`<6hRcB<}%L9jKSYy&Kc%nF902yKcF@P9A3?K%?
zf&n+N=n^%F7(fgl2ADHIQ3j=wL3lPZ{YcSGAX2GH3dvUCL{~6^fIJHQj0*9)7%<4B
zIVj(@BH7A_T@-{EKnx%T5Cb)v0Su;3xg!eeCyv}N;SfaGH<9O*EfD3Nib1#p$Bje4
z0p(WCO9GD|V-72*ikSFl6btX$PlCRHkVUyRC`--*;kVYmFNaEm6<(_LN2rl4=0TgX
z<ii*agqp(dz;swfMe-3;n!&9=aS)QEmj?o&)Ddn{X$=8C7{dyvfn4P?053Tfj3rnW
zI{kMb33jH!5-dB-iiAqLBMQydBO_?HPI3%~Oqv6OQ7%Y1yCp~xYRqAUma5eOz;*33
zqIR~0x<U*f25KJzJVnX7`!VT}_Yng3P6|of3OJl_9R!^4KwvXV9pNTHm{4N|E3}Ll
z1kmVb)H83L%B%_jnKTCuqg)XBrx*mdA&HUEs*_m+WKtY3fDAE!7(fgl251bx=ZMG<
z1Bd~{0Ac_!P`eqRC<Bm%jEtFnq>EJgNEv}79GMxc@H(|Wf~zPAXcg9&k@3422*{*4
za2Vx+AlV9RAVUlw1`q>?0mJ}e05KqlfpkGm<U<S~1_U!e6C{GeNiR-5nCVBlNTrW3
zmaWWT$@z)BaTO&2OfZtI?MnkO$SAWa1f0{Z5*$XkAoR<D0Cy$BLP=zZ0mJ}eptdr=
z=q<DIn`a5O@*6=F5d+o70PK=jFqU9h=#&*mj1^Q4OR(%T``4&6LBgma3$hjF#SE5F
z2emwit0)QRlku*E-^IYIfI%s)p2gvW3!*|>7XsXs3=1WZiOK-{`(qZ2C0G_ZWd{;o
zdMp@Auq<?nAQ1z#odNg~;kOao1N5`zGl13n7TD~7CHh!`Ws~W@z~-k^gqNe~6iDGK
zX$bJ}K>p&}R;a@amh=C&V@MK9<0?u5x@V*xvC=^J$y-YDkbraE0`gsB`nvFvAX%Vc
zq?cBm93#jF*O6Q@9~eL;Dg#YKO{koBmS8Jq@~8@805O0Vs5Ayx`m~2REKzB#qC$v)
zn#};g&h%M=WvAJ{M&&0N1Q!KS$V@-dMJj!StAhk%l3wPpLQ9E3fatOnNa1%e5PTgt
zjB-KHx2?biGQ<F405O0VKn(nw48ZLj8Dao2fEcLZ4DeGb!dqfNw!);C!J=<l|F0+s
zppEhEir>Y+tAIf%?xzemoN#3;eO(A}S28S=M1~kZ3?K#&1Bd~!V1R%dZq-|K)k7cz
z!~kLdF;F=S@KY+nD>KuN^zT;bBU~LM9FvS-2Fs{aEf3-<N&@<<Wc^5A1=>hez(Oa;
z5Cez-!~kLdF~AxF1RzuPO~R&v*CivkI~^RN;r>h-22V6cnOzboTWPm)UJ@h=G7(?}
zl@SkL8PZGFMQGnUrTHu%nMJua`0tHyD9(Rn!6VQZ!wRe-Ce9$TPXhjPF!*a5dE`U5
z>6He`lA*@rBOP9#r12_H9Ezle2T~GB8Q~?Blo0g97*<db<SUl}yj)L}I#`0O(w_eL
z;-$CO>YgV{u+`nB=y<d{qR<lQWCZQj30Z=6OQkn%B{GbF*s6qu`p9Y_1L#Fu3l|l&
zgczum4AAd&OxnaCh;k<-&uMo{9HJ;9l|I5tf>>dOL4Z(LVO7Mz&v)x1v~j){17!hu
z%SBlQ3@TGbxJg1GA%Gbyqf#gcF@P9A42T~C3gXu?>bTMvK%%wMs6>Sj1BihtW`M6`
z5Q>RG1VyKi=lmrNSHKXEg2NMKgqH*!VTM6~P*`DA#KDhbt2nGO>Jc%37(fgl1`q>?
zftths{30AO!~kNTVhmJ3wvxIL12Ccb5r-&>NTrW3m#vIp0ae^hblI9rQpWdUpe!J7
zxhRW|0o{}lZW1^IS~BTn1}m@(av}y01Bihd&H%g<vS2L1vd}4l<j(-yuaSw!0BnX>
zFqU9h=#&*mf)!K_OR(%T``4&^C4<na7(`HX3VF_7(r^U~0Vy~<QAT)4;1OmR1PFx{
zRz)2AqRUobh400{f4R!8f*S_OWk+~x3=W~j3|43v6u^gpAU<Q&FvJpUHFWlGK)~yp
z1!D=8g-#J9VgNCK7^v9{z#kVvCK>~TXyKI=Eefo3Wr5b%I(#LA&~7k@py(9xoTor3
z4vOl*A&)Y`O9GED!ytfCojm7N;5r~k+)Z@ZN|2QCy%_i}7nf`tn8x6VGQv#)hd?7p
zFEdzyWstKR1_qTgUd6*K!B%lss61i-F@P8ll>wGM?O_R4RCZ8&l`(*1YXzu<y(<gG
z5-bayRstkn$sn*UPI@tjpy(9xoTeXfh~f$u0#0yvqKxp8z$3_T(uqNUP*?~OcN1N<
z0%LqH2L8)cb`{((NG?0VTVrqtHD<6v%b)<n0Ahf31~ArVfF@7{4B%Bz6O}{^AO;Wv
zhykVy;AEg22YuVhS274C5rYVdP9e{E3Y6lYs2&{hC?mWi@CY*u0w~qVb6y2-w8ww{
z2Lj}wSX;HqRt^SSQ`UvM#*7w$?={G+KtKs{jUfnGtz!UQy~q#)hyla^Vt~$o41EZV
zAO;vRfWB>INE8aISq$)%3_@GLAcCS($a9K*r0FICQgC?sQ;_^tJ>U^$7z7A~6;?$Y
z{51L*HO=>8;J;jyRluM+WrUkliLi`Hp&-NnVgNCK7(fhE83Wv#8vzK6K6mR-8i+v#
z_eMz`5^yeX-y}o-Z+v-4kSx%c!wM`T7ET<xq^zvaw$qjQEFhUh-$rql9EX|!!n+7?
zIH@XFs4eD}4%91>k0A0vF!}?|>7{{cWJVtO;K;&LnF<t#G3nufl!Q`7ssgrTHt0!I
z2H;9y!B~Q2q0@f{667xn#u6+Gor(xazat7QK)zLD5CktD-lrMlvB2HZ@B1-MhEeaS
zyd>}lG{&$3s~~61WdOa1Ywp^inIi_oivb+k6-_^q2?S*EZi=NlRQgSta_{|H*~%Oi
zCMV{GLH`u`nGk|Q(4Q9rZ}UWPP!^wnJjw_!2|U6KhX6`-@|;(J>wq9+hyla^VgNBf
zV?d8Kf(8%+hyk%?puJdkkD9Nw4B*fiR~Zm+!o&y&qUaRz9LZK-<=-$2rh#PZzp)r-
z7Kj1F0Ac_!fEYjwAO=VV6c7uD0mMLs8NeY^G}%hZRRXfAS++8Vg~^GzVbH%wvXvk&
z0vxjbyclR-dlC>uS$z5kF9~7=8FN@cRge!cfEYjw)N}@Lb{b#_mYrr1Dq^5=7=Z6-
zSTGS_(YLJ?SRdE`vtTU2ve0QIK;ls2Po*NXE&&k~<wBmLZ(D(tf5R}ChDfp%5^#9>
z^J3sBP>Q4M;uF&#uk6VGf5jI(!VHH1N_Fy_1`9#RL}efyE`sVemSC&DQI-%fc5qpO
zWv5w$iWoo)AO;Wv;>7^$L|HJFU|Hz25+HG?@uy@ET9<$bicTTVk!%H4{td%m8luTo
z@*=<?>(7gUrXLB2qAWgrgqH-d0*x`Oz$(aD4g)wlvXv#+a!5eKhyla^Vt_3MFm`}h
zf@P;!go+rb90p+T%7U>3%R;A>0Et75Kb4B$y5vTffC!3mA<wH=wlar>$%(mP(7$N1
zl}x}P>(7gUr$8x=vWt(tZ3W(tAqEfwhyla^VgNCK7(fgl1`q>P!~hO;DT0Iv5CK7D
zl?$9#v1}y~2!Ig|3sGWj81!FVvX#%e@U$+Ib-*F$&ufrZf$LyW3B@1=5Cez-!~kNT
zb}*n)JK8{9AO;Wvh=Iyt0Ea?cWkA3Q6C)r<xPGMQCIF!-sj7knATc)#`lry(gb*Bp
z{#+HBek34@viS57UJ}F#GaLeh!V0T`{D=X>0Ac_!fEcJ+26#6&?mbH=+y*j&{;57W
z$gMy?3CcaS6hwuCfs1l0=O%$epfQIPSVlaYG>V0{J%Y~yl36%pau<n!6WYqsM{tOP
zB;m#wR(Pq}A0bP&XiPrRVSN=D^-KOI)({v(J_z!dqxL(CSApWl11A@xB$P73OM)=L
z#u!#`8RRX80eBIzU@XD1(CNPeiLo;kmSEXwRuohmf+=@Iq1oi$+9x20a_c0|>Dws!
zjhi;YOM;35jXA8qGRTP-Knx%T5Ce#Ts%3z7uVVy9xfhr2P;tnlIWQRIf>7_ql+QsR
zOsLVSlNmT<Q5-NJ=0-sOe{Ow*bHZIG972Ip(lB_UIe0swlEtUcUsbR$4`he|!~kLd
zG4Lk?>3<HObHo5*05O0VKn&DA255qWQHwO4LT2HRNpoN@$_1e+DI{Bgn<_B^s#cYL
zq^+@lRcF*4_wv9Y8mg0q!4t&+1IQ2qhyla^VgNCK7(fivR0i~F>cr8!5d;4M0~BRY
zDj5XN3%+QhD;Ew2hcuc4gHbLBRY{2^TbaWGqL>>2{fj1B>yjDVb;2RN^kTr^nC7Uo
zZ(Ete!aR^61`q>?f!fLdyw9>=EWxtSDS|`{R2BnxWfc;w4ok42O|k|@gDhdeSb}At
z)5?IP2@*y{Y3h{B!XcC9z+jXMLRC_t$yTUCt4@yLGzScbxe?I6XtEVDxa)+&36M=1
z22V5xMYhV&)`gb@$wG}*oy@=>i{gL*WTG+v|NfW-V+odpPFaB@SV85m1j|md2o*7a
z7(fgl25Kq;ScN9el73_fwn7xKn*`c}q6|uvitt&{bPAb*LmJJ2!6+Ams-%!?1#YUu
z2&gKWY=za}t`iRFr56JR$212;whCBvNET?!VFi{!&T<%#E@!-ohgpKH;;vA6!~kLd
zF(4uXgoyE#6wVTCCCwg{K@70M0LBU`hb35cn*D23njjHc5!4V(oswfXWYQcMjB-J!
zN=h`@${ZFD#o0(nNkIRi$yUhVt`iO?%w;S3wiWoQYJ-;xGQ<F405O0VKnx%T5Cez-
z#DLf_fWB?5l}k?Q8v+`uHrXoR!wN<OGgHfqN}(Xc0Ac_!fEYjw)CLCJYC{vK2gCqk
z05MRB4Dgc-!pqaXR3%ezNTWG080CUcm6T}Twn80Rb#e@+IbcA{je!1<Y^_yS0s6MJ
zRxKyD8F-Z<Lku7WY6=4wOq9E&!Qn)h#gQ8q9D*nt81kI51)}`J8w|oFIBtACf#xMa
zh#+GQE2xT?_$a$2X7^e@3Hky8Ta;^qvgAAverx^vau7~8V_4y(YJY?p*<v2F34d+F
z7!HIQ`JY%rU^*<LBKZg^&EQs`I0#A7%L9Q>>IgTfw1$8mj9~@TK(6u`fR`K##u6+G
zo&GzJ1Upk<36`B^nWC2H8`>RFXto|1LA!O5V>o2e92kspL8u>m@ODd(B-EJ03N2N;
z0~oPcyD323AqEfwhyhj^;3-Pp-H*w1C^tp!4wYL0hYI{}u@FjtyDDL!zPKBWeny1w
zTNMH_X$~AlxghjUF$i!&5+kEkC$k91q&Q#z8Dao2fEYjw&=`Qv5s@JV5Caup0DT%!
z0n+~c6i_6{Y9j*_Wx(v)R+0uJTmSKEfvYG9m?x|;Bja~55Rgf8;4sPsp<fOJxGNbJ
zN+LrHAO;Wvhyla^D-0lg!wT(H4O-p$CcUZ~LiG^?wV45$AQ9RuPDZdGTbaWO?LZ6y
zxQdd1UK#1f_N9RsWN^PYCl3iYr(GpDjB-KfmjeOrN`{4!$PfdF0mMLUWq{FJX5}}}
z5^Uu+f+`{gs*i!{7Q3aLu>@OvyjB`gg_y!B4PK-|EWwI2$A2T3Ag4hSB#frUf^3C(
zF@t5)K`jsBDoO(SWV|ckcQNoPU{H#yXK^^;f~e5eg#dRY!$L`9qA~#g{+I=036_OU
z*@1+Y9t*}2EDN0?NW=hQ05O0VsJRRf6}nwv>@>_0EIZBq6)G^rPpJqmO4BKj!dKD|
z;NgLwf7=RlRD*F9B>`BB^dnXp2tRpCNgfh#&RamfYfS$*ftLiy0u3X*wCdy-K|ZJs
z7(gZ}15HFtsGN9~U@K?xs0v~LF@PATGzKcPeg1oNmSF#W;-~^*fHejPc92<uWvAJ{
zM&&0N1Q!MA$%1TU4l8*2wcm@AEs8E%ffs%k1HspU!zdR7ecK9bRJCDM4S?z+1`q>?
z0mJ}e05O0VKnx%T{zV3G^1CyBN=5iwS&*$TDQ2+3r(e4xK;Ux~B>}C%8Z$C}7XtyA
zGzSi&ToC%Y5a6z4SSX1MF@P9A3?K#&17g7d0l(ga3^9NhKnx%Tcnr`43C|<wfSG=z
z|4J}@g!@~kg3x$AX0W_)F+SibN&+~jWc^5A1=>hez(ObDY?wGVUweCpw?t%!0mMK}
zVSs>%Qua;4W{%e-Be**q9HQa=Od1AHG)I|T5-D40w{l(*BnvVTU<H*C4__J5OV>qc
z-#exGEFhUhxi<Lkjc_Q=e`UcV&=|uCtRg1PAhJ&a{&O(+Ya4mwL%8Xc2FjA5#^fU%
zUZAA$Do`AXq=yGm5=t52C6$yA^u!oeP!Z%SmjS$7Pn9}Yg00e?{`umix7X^PCrhx^
z-KI!*gCLrAM-*Bjos6K}Iw4EYZmIOftwe?q5L=b7P+yD<s6~btKnx%T5CiNnK)=^9
znF|I%lshSTPP<#;5JeHG^buYX#0oPE0))Z}t0E45zFQxmjq|-2C=1A2F3KukP?<8q
zO%e(T0nA_-l|n&?0mJ}eK>Qd`5WkjD$B2Q-VF0#E$Z8z}=tHJjx1^;F@s$iho5di4
zqEpCo{*s0(U<gRT;fXTBO9GED!yrH?tgtHL;777m999|ih!{W&AO;Wv)x|*j>H<PI
z)yV*CNvqZ17vYd01`q=kW1s@EmDG(GfC<%)I7CrIDt&~xY-J1!sN!y-%hqI)GQJlB
zWdV81MOl0d=%$QtlfWU+l1VQ!Sb=4b6ET1oKn&Dy2H>5L1!D=8g-#J9VxZC(fXxsK
z#u6+Go&GIkg_t7#7PVseEWuW6vg~G&;)1Va5IQRiA}BhAJm)WIxB`ZN6dax?BfKQ=
z2r~=<gu)7|A`X7hWh=14_hR6`TxD0m4TI#eBfK>Rhfre%E3^y>;KM)=pRsBfVhOey
zI{P;u;PuUdu>{LPrw9@;fEYjwAO>nM1Ms(%L^eX?j7mvh3AR$^UcE(tDZY|H=rk~h
zpy(9xoTor34vOl*A&)Y`O9GED!ytfCojm7N;5r~k+)Z@ZN|2QCy%_i}7nf`tn8x6V
zGQv#)hd?7pFEdzyWstKR1_qTgUd6*K!B%lss61i-F@P8lm4UzbwC68UOa8W(s8dDp
zhygKY0QRmd7)!7$bXp0Jd?kaxx;W{@AcCS($a9*0#370+U<f$D;fXTBO9GD|!$~Iw
z0YYIRNUV)yNOai>jPbn~_%B!4RdB-~x$FpUjlm(*n86AyQ_BO0>h2G(Za{>G7(fjC
zqYU)@N9Tp6g&05#AO;WvV#9!RIZ8z+0T@J3bP9RSQ=k+FMfF%f9%Y1=1Ri0AK>(#X
zdCsfAbwH3f8%{P~t+JJa0o`2saX8_wF&qmuBwK}2gaQx)hyla^VnECokP)+f#iU)>
zv?4<cAO<SN0AI-<v=jyr6rDnz)AS<_QCtB-zzGgdlo4JMc!U`S0YYJgRS^e2lC8CF
zm5Ex{5o(BJ07on!1}cF8xRE2P76xb=7@?>g$Ozs}hr59x#|X%zIdB*)1(BhD0!@G$
zl7t#_SfQnAeE<#}QdU-I%jwE|7Ld%M@2R;<jzdiVq3&X<3KoFG+|q%1Me-3uJ_tsC
zz&X7%P>syUBOe@Dcq&tY;xHyXJdl!5%1Bkfmdpk{iOK+62`m^(uq<@???8h5Wx-g2
zWua5%kT_ib^gE)^0_0mY20@U{`!s_*7PwpbeLu#@FzT(GmjoVx#u!#$mD=xw6-9;^
zKnx%T5CiNnfCIE>`jJc^Ad7cXEZw2fZ_<=|@88N+=CCk1F*gkQr_j%Y5FCR3ycl?!
zCyIlz_ypupMtDi!5oS09P^y#Xyb4?g1R<+V21;Mo)d`8P5Ce#TiZGy8ktCFZ7(fh^
zeo};psBH{X`-e=hX+>5I4B&vlRR#o{FfjsxC_05aN3s=I`8N!MX&~A9Z!89y1!4d(
zfEcJ!2JkAaj*9<gAQ=%+8yTo}xuH-SSwuY{2C9hx9B@RFt)yHfAgh{XD|1+woR}L1
z{fi`93GyPqA?weJf%dg00a292r;qTGAXbnuhZR%>`Kp2e^lfWZu!?FT2FhaqFV9i6
z<1E2eZBwW^VxVdnsP-@Oez(ICY}ImECDkj&6l{Q5FqU9h==5(PNpXQgjX#x&(7FUf
zP?QUK&fwctDT<P+Dp;7Dm>UNDQ^;mQ2o6Dit_n|qQXFL$pO^-DWk>%1E56_nW;g^;
zs*~q5SO`KUDg){4Xit`4MP;YP#$)WvoF!OxnnkFH0mJ}e05Kq548Ts51!D=8g-$C0
z5{DXpN(P~I35cNR6!M&bY^5rxs)B{diMe6Wzi6_RTn!wu{#+HBek34@viS57UJ}F#
zG{&$3s~~4N4B+g@R+eDPAps2|1`q>?0k#;xDh~V?shq#bt@w;lCSssQGXQ&67K|lW
z7CNm2NE~YXsZ<2lB{#wZL{O9qd0xe`l{qX-PRtF1{z0)Y*N<c{PCjTC1Fr(*Dk;18
z=-XD{t@asQKgbXRhyla^VgNCK7(fgl1`q@P00TJ8fg(tlOp1V@vdRU{8OT=jOTs`@
zH5djM)g@c`e2T%-x=eb-A?VL*kXM20U{VRiAO;Wvhyla^VxV>~pi(>9KwVH7fW0y@
z!~kNTVhrGr##IIcoG>v0f+`?esY<G<V3~AK%VRL;56RYAzRIXQ!~kLdF#rtUh=%H7
zK=e;kH;_}Kf2vOoQno;p4OJ<K3I~I>D7SKM5;z1Jb6A08#KTFWSa{nb_$(lqg+nHH
zkq9`Utt@>6hd4+QZj51tm#X~{vSf?K<Rcx{SCLV_<bPrffkEVhAdfj}zq5E1D2_aE
zazRQ$DI>fj2or3KVFi~#-f|d#7a<GA5-bay{yUHuJ5yl^mYrrrLB%1Maz_-JP5!NY
z0)i;FPV$_-jr#M(Ex~`cR8kEp3N!_d1OWlUVFi|{?M}S5H;DQ}3?K#&1OGe&f8PC=
zO_*{oF5RKxkV<o4Fv<m?-WDmJgFu*2qg5v}aLA%KU_i``fd2p7g9zt@yG}TS0;i;5
z@I-S^woz32s|pt8fvg%CD1BX5BO-!A3?K$7#6Wt5vQQFY05O0VKnzq016ZY0K}Cc!
zKocawQ^*L4OhmGk5ogsIL;zS-=|}qF(?&4Bhf9l*@w)~w$fP(Jl|n&?0mJ}eK>QeB
z{BA3L)S!+L1OFBSdjHmR&}<L`HH!g?GAR9mO>hVBMH@}0kYhNc(Ht0zazUs{O0;iV
znZp92m>U88izZv^k{R4}!Xdr%V!+^-=BTu9Tg$+v;{a7IEI5%>BLnE$)@mdhK_Lcy
zzt6J31H8Q>Lku7WL}36ICAjipS%R&+2LAC%AWK*<mS9=vv@#%Rf`m~~nmQ%3aLA-N
zFc{^6C{dJ@XtEXR(5jPTIL!eAVr~TVPa&HTA>4JsAsWag4TC3|gCbjHXzRjDf@EQa
z)2fph7-Uf#Fn~-{2H@WxvtTU2vd}3jkOV8J9F}0&X%?X(1`q>?0mMK}WdN(t#97jh
zEWuWYB6gENdr*`?sZtR>E1FIrQ*cP5IWQRIf>4zdlC8i^l^6k4MU$<t8r*flA-(is
zz~GqXpvYDMs}9KmjXA8qGRRpD1JdP;SMe}QuvOd@DvuaI3?K$XWPlJczLLUOf~}<4
zqcVsARv5roLFKRn%TBX@jY<<FLMwtAqN!7I42Mjb1A|d62vtdmCR>@q0-`t@DJco)
zUo_bY8QgWk;e@$t{mXA#8N$Mx#M$8Gf($W$7(fgl1`q>?0mJ}e05KqT44`jYYvq!Y
z`i6kUs!g^E_^^Tz!OYY$qf#gcF@P9A3?K#&1GRwxx7yGI>H#r;7(fhEA_M#+gYfdS
zFICAD9MWhG3`V&iR3#<ax2;fzR-GKfX$}|=b0eUCBwK6MRe-*2tyRm(Z3bSY$PfdF
zfttbq1{39OX>d3ZW^v@k1&1KY28KMRY=J2M@CJi$362||PoQ~85F*H!!wRY*CO*n;
ziP^o@PlCRHz!v4&pe#8Lgx^~Kz8r+p%@|gAsoEc*Mz)v-ZNgvMFopx6M*iQ~5SR|j
zs7OA7N;9|>C=NoB^zuL;lsdvqDy<>l2V+<PHIS=(2H+*fg0Te4LZ|-@B*D&9Sb}Az
zS*EBZ`i6E#6q>C^M$m4Z<QNW_GzSKwToCF9AH3ZXBndU<utH1K?f^z?)@}+=cZdPR
z0Aheu26&2+clTp59m-9SyF=wxz@Y;FTP%bU;I2wos4wnDqn{BW{8oj4Oqv6SQ7#Dm
zQw##!ki^Jn)yXUZGARxiK!zAV3?K#&12hKUb3|l_0mMKB7(ky!RDiU9KLr#Cvf9W1
zMHw*rww0s-$<}}TTHq>50_F*8%*gm%3<PA-95{?}LFktQ0q#nMg_6h+1Bd~{0Ac_!
zzzPFM->^b^RfATyzDcj@hERRPKy7A#CP;)fi<1#7$X4dCLOT$H0Is4WpjSrvv3+SE
z1{vHh&dEap&S_T(4x?NU`sF}?yOLp{Br?PRVgNBvTNz;VmRb4DvjkiDji8E%f$C$R
zy2Wm3XDq>1AFq{$R3WCYN`n`v5KFKk&GFv|Cdg^f1PP<5u^?MvUd&(_bx_NLxQdd1
zJ{j*y_+1RV3K*2)>RB94xF9ODbs@lA$*@oonWzlFzdvTdSb}AtQ+6QXrN@G?1j|CF
z2of<+TNz+{W3H_PpuWU{0ir@(Vin5z>!k8w8^HD&8IJ*+JmRNRcmd@e&~yq!@|83M
zcz7UH@o!tFwJOoG8aN=KeHF0qe?>{a38UK-RvHLDc}qzi5^&C2K)!2C|2Tn{1jzyo
zBfYfh<QS1o{#7T6Ltq)?EQf(6<&0PHaJjH~75W6Uif4<;BL)xybOz)&4e5huL}Uh7
z+Le?C3%6C$u##u=gcv{!lwp7<b6kyw<-(>baQ}EvHO}T=hoUG0MzS7AWI?u;fyE@?
z4Vk-`?mB<W=U=D1s^^E309=9y04u#s!J%N|cQFu<LUZ6S$_1&CZ(EUU1&YfUR_3_o
z9wOOVbJtGL%>Tbd#sq~SUrk~_j(3y&eT%J0b4PP6mjUT=J;+gW8Nh4q)X~fZG0;Ge
zQw)7L*)vU$Fyes)*$VUG3p>sA4+o<TYH<)o_Qq9|1oT<evX#Crl>m!mD=b~DGbCGU
z-IA6xgw@Wr#Jejw4*J~)cCP@UDi(n8et_NH5jtW3F~CVzz!3|7GEnnnEBdze&ow2_
zk!<BdO3fa^YWDO?XOCp-AIr%7rI9~|(J5kpbq3@(7Oc<V-<tpdQ=;sfgv}AJOGbbI
zrF`yAo@3;L?tr%h0z6V2LV|uP$H2uz&Xx;{b1U%X0|Vl1Wk@ew7omLYl;*R5WESPx
z;89H3lHpLCGQvv&k3eG#E3k@~ID^PO3HZ;!;ID1ukq_afR~ktED>aTW`A9E)t??>Q
z9ExNF52PfNGQvv|id#M`_Iu)7SfQ0r06zwBeuGs%#u9ARH})?hz&k4o#u6+Goic}1
zf>7Sg4c<!Ojwsa9$q3r56SBA!a5&+A2L(t1+?5GS{)RtgK2TqbjnN|h>->~loB#SG
z(fkkthyh^06un+)7XtlWM+@OIfWa8$PD-BB?v^-2QEsvH5nd9+3Ns7>Xs}Tn4#fdM
z;%=0!2II?~@5Mk_K;CjuRsjRLDI?q@M(e;2R;dp8w|giKMx{{DKh6LFpF$w3bqrv&
zuA>^(kU|yA7c04^S3zM^l1&B}?+4hNWVK?~icce|m9ZKD2D{aoZw4hAs^<4mnH^A+
z0mig)Ngze1keU1?4OhSrP#cFQ$_OtBJi-ivfInep97M8}MqG`TtsEp<X^UDL29Rv6
z4XcQH5DNw{&J3~WlX;W1Lf;_S`sadIyS{;6ghPfHV8VdGZ`s5oRBU1@AX`b@hyg!;
z>PMaer8p=e6^A^^2rmgd0<ApQ83zd*gG?^0z$#+m6kWC^lg#kF82B$2muwse#o&oD
z!c78)KuadQd|^+Lzh_Kw2rPq~HG}~-nHn-tG)>VMs1+M}(ORzjXn4b8!ODZhnEhrm
z3o}NLf5AX`%l#K6#WM9T#4hZQDr$cLTT#dwnpYvFh`(qS_P`Z1qTD>w3bj#gxti}F
zUpy3LfH7^UB#@$0$V_0D?%)a-g7k85c%qE(lE5R(FbJT*qF)lG^Cr4%g&KS>2L8)c
zb`>xTlFN?p))*W@jXx~<C1Ih&F$f4^5K{#q<-($GTPuZamP8^;u$4j?Dk3ri*zX&*
z$ayH?-(f(Bqw;$)y?LKO!2Pz=(Es$wWuk`tRBD~foiS{@sD{Iy4Oz)9RAd?mkuxeK
zp#)Zv+=73=$a>PeMU~>1{;rP^{eB;a{WHl8U&$bp7z`pPI)yyvDNu@oqIz)1qm1y9
zz$45sjx~o9(U-$nZmGn*qe@6cNvL3CCf0T(`gEAfpy;xdAXE8X4E&divc?#|QbxE*
z;1Fm8=~dY#!GWKg`KfX^1_z{(za)&8%tu;5q6u6j$ST6Xpo%2@eGUmrOjE{w7a}mY
zHcF3WOLtFjg&?bm3=l-gto1l<B|o`Rmiv~27Pf?zn)dYnmnf$%cL_00?~*o%-?xUE
z*3v&SU+zn!nkPiU5+(Qa65RjaL*cec8bOZCAm9jD&0~OjO%YP?hi}3D|BJ^22P+vt
zPZeQ+`|ekf+`q^H*h_My%Q}7<w~_=`wsJT=W!|H?ZZZ8?q70yScvr*VK$ziV00u!o
zBCw2;4=`Q@iUU@I2ZBQ!WrUXm9zlkaPCak(399>q$#Y@rNJYv0o{yv)&ig=-j1gZW
z8RD%AmuyCC@Ybp9s&Fe1P=e<uyT)!9xXO<3))*W@ZKYlv4gpbq7^lewj&w44$Wd%1
z@%y^@A;qZ!u;Ok+4I_XcG=49ek{&s838|UC=dTIZ329Nkm;Cn$dagkX5Jbt#n|wQ#
z{~vpAA8J{a-G}Y_>Q(jYnsU$Uo}N~X)bZ@@X^9#!k)JGKT45yZ>S;?YA)9g-lOaR!
zlM#{v^G6xm(FpXhyVI81!6aodkg=o0HDU-IAv+CDU<e^xMuQQ`;0U8AfyALij1m$P
znxG_u5SpytK4<TD*IQ?Qy!&<TId84*d+t5!>$lc#pL_P+_r1E0#`14d<qu-@$49*>
zD)f0O4B%~vTRkK`)B88PTR%e+%8zs=Jx+>&$L91zEQ&DA_wrhNq0dudAnsWW{ga!g
zZy49lsrU;lo%ktrqqRl`ux(x5IrYYUz?e^ecTg`rY4L`2=l;8*+ckftiyVx2&_Gj^
zv3SuU7EXAJr0o&CP8pbi?Rp%!g-LNe*syKIUw-_EGYj|MKZV@(IR29GxBmyH;tmbG
z>n5HWPU8~kZz5rERAL6C&5W^yX>inGsLJ0zyJb9nga5_H?)>bVSPauu(*Kh1@<02a
zIl-l+GA#yZ+e!uhX?ozNt^WV({-#;_CE-thc3SOdwH*V_cu%jw!f8Q&s?K1PX^g{>
z4oC0CSNc351{~dVZ=Z&n_~|2>qQgDdhWmZ!BK}BcLM_dr)D6E1;IXmYd-Wa-<?S2J
z(I>>_`JNfS^0u7?S=Xis{GcYhLyydl;Z}U?R)*3Wk2Rah^cV;~ZT%qC{WEk6e)R8m
z4fNk6Y?sG&dL8Yk;=!Ft6)W(E_f6U!(d%P+NCVsTIC9x!+xj0-_?sU+GGF}WOU6Cu
zek&q=lkm6yuYa*$O#$SZOB$C*e-j^r7emb8kz#m^Ellikh(Rz^<y(JbVU|e!Ir~y~
z1yM-M;Q#Kobg<PlGk5S4>yNgrj(&6LnWt|(v|Z^KQW6)A4?f(VhO_H?=-8N2|K8Jw
z{I|YFKW)YRA_;B{B>hu&qQ}WFfZI1d_NAF)fr<6JtK2``J%6b`@6N9G5jQS2RaWWv
zIC<cWVc{7kN_y#WE({LZ9^}@=5^Fu!uo9q957;-5nFOx^>lXA1Cn^pUFp8_3EMFKH
zK#F45hD91s%$8(QlY-!16u{o0Px7B%9-GJTTo{L^2lViGfsZ9DUZ|KQsDFkY59#4A
zevi69&9Zl-?*uhZ;Mf1nzLbF(UL}VF5?q-k1tC#UmI3y8^9dTeC-6koBoAp&L*Xx)
z<Id3O^>{@Fa3zc&Bf*Z)>ES@)Ub_du&?cz2`qyc^lVuN;94>@IX{Yq?cyUY*ix*X)
zTeXE#<k;baBxPU*HgP-nF-;1Br6_>4&X~7ok8?tGyRL5Y0)0h@Mda;Zz^iL5c4FPT
zBiH?-43A+v4wn@T?#1f&5xowgZ`;Vk1fJbWjh0^Hrm!md)7Disrt|vMk6B~>YnnEm
zy>V*1I|`M*AK#i}Q|TCRcmh3XiiM&k9u8?z?B6sg12ceg2lp@raAlel1ecmDf0g2o
ze}FzYeEp^|FLnPS^7I=E^F>77xp&{#T8e984?HlkTN-z8x_mJV4;LF_k2t1DL9o>1
z{1qC_qlZW4%p3EC=bpzE;!hsl>8_i9^TRiBaoSoIwI3P-zv8H(h5K9PvHebSdP*Nc
zc;o)(zRGvMCwyt1?N9Y-It(1qE#e;iE1a+te&y&MDnGy9*Z)Si5lp9<xm0?#VI#PG
zpNF~mv9klYj^Us(H3p8{@u}^K#?yUA2RwSQ@x}Fio+1rc-H|+^hg*C)yw(F}fR>HZ
z656)j?7r0Ho;6?j)N`TwubZ!hXZyAf&wA)@VV8F*Rbm2vn8z$!`!^6S5|49cNE;Y{
z1Xrd>L9o`O+qV9~!koJsZ<)W>{YJ#;AM{@la{O}tZ7;Pn*T8PkBgQ3>4Mj~H94=oB
zDFZXGG4_aKniK>}P0qhc?oYjcY##kGZCm}VaHX95_3q+4ihmNamPPG{#=x)8)#qtw
zm-Mro_z%(jN4hGH&o}&cAcxlMHL3^OR%__)8*cn=rSmuF<Il;h6;|rM#xHUEcIM8>
zjfKUmansScHx@VYP9DS;*ZJ8_t@$IGm(R?1P}!#odKsox*S|^8%&&xouKU>T{hoCv
z(7wUJhFE&jI{&-fm$;L{1tlH3m9cR)DD*HD2EtEU{n6s~7oI&akAF0j?ce!Oc-I>H
zp@j=GuHF0PdT{(XR0LW;g{Mbd=)L0MMbET)AqiZrWMBr&dk$WKd$=;qm0-JV>#xzr
z!b?hY|KAF8>fL|YZ(HB~zQw{)ewCGRNo3bp@iaaTP8g@vQArt?fsL_89MhyASV{ue
z^RLs-&9OUu??0qpQ+qS)XO8Z^VU8RkZ=Jpr>cMN3DKYT(=$HAiJ6%3?M89?z{<zT*
z{TgB?&Q7Tntu--l!(iJAS-SK7wth}OP!Bf_W9WM<Rn}#|tsA&m9AI(#cIE^_drVVw
zS{Zp#K$4<6)#F4MSl-9iFnOx>*!3mjIs71p#x&lJdy_t0fq@O)5@F?f1*lcm9v1)5
zk^arxDSaG~#PxS(`no2Sb?;d{hwBiCo9Mc7WFDWLc#8fWN53TO==VuKcQ2Ik{;9#|
z{>D7PkgH$==|BV6!G-SW(Ig&T7$b`pJ((#3Go%en7y`I5O$tJyn)t<w$L8(t1MGtS
zDf%-8|J?HQ8^(G>K4Xu%dT?^h#iD;kb_*d6PM0r+;o({xWA72Ss<{|rSZd;a@Rm9L
zzv)VN?;m}@_<#0ig8#|S^%v)Fe{*FKRZFGzOAIV=5$s<A?0;@g7M~|<PrvbE-2JW!
zd|4^v{Hg9)kLxgC*9qD@rh|R+0lr4yYxI`)#=L_21McE@#v^>{M9(S{V*r1p3V-F^
zVKl?{8$LFt$CwT*{R<rERHnv&?+dmxi1@*4SpPcx3}R~Ic&Xm-4kexI*GRqD_Rsp%
zF@Wjl>ViAo2m)BFp@aO3XX#VnKi9qflZz#s>onK=NGt^+z!=^Mo*qr&;RTK@Ui7r4
z49tK_$H5CA!If!J5Ue%vN0b`b&)<LQ#Q*-C0Q|*2vBo2k4Bp~}%Eh=Ova6)f_&7LW
zoK{CAWnc!3f~7|oQI8i)lY(F=N)P)WWM3{8zW09huk~NK6=926)R<wwh4)CtxH~n2
zwPx{Vg8B%?Q)Lbe_@nSM8+zm4);sSU2DI;i-mf&3h7(K#Dw{H3H%+i!{2;8}e%B-O
zV5404{w1uwRJOtZ)~+MSDy)uXWdI!PacAIhQk6KTfm;i2Qb5vPhZ)iaCfqOK$}}k`
zq$nL$VPAnGDeloz%y61uOIfaijfk-5labxhxP#N>i(z=U64@A*Hxak0xfo+uYU1Dk
z*t5U2xc?441M=k4$Hvifst2#HwS+g&6dCY0j*l^<p@A<<u>-AHFyQHZ|4w+*lSy|s
zf}g1>FlqR{_{ZUE`ls57*1f`jH#VGMmUiKl9_GQoD`-P+!1EZ)*u}rVZ8*rUnfHBo
zG1=u`*T)u*bPsb#2S(!V59d|!@W36=;zdt!%D@b4*TZ*G>%+eE{x6?I*bmV+344^0
zU~zJtg?P2-ALEkfhoUA94wpwIWnhLxHb6Y$m?j0mQWFOUWIuas%vb5FnILz5@zTW^
zw0f8#1HX3vzWF=`m@btcoMHo7vt+;<hkqg04QqD`kWQ+Z8UysN(BGk1BdmkHE{De+
zzPnp1;5=n==8gVcn^gK@stk00PNS<Ht1gu}Fz`2?zW5;G*XPjCmV0o>hnra1bV5-R
z4+pkSq4Si18PWzO+$q^kYJJ%AZ{EN7Y3sYTTQntD6nD+VqJKtq3n30pmq&#S;P4oG
z#3lOIhduks#V-j9SYTXh32&fDGVpO+8!E#L;O#O^S^8<#tyLEoI8UEM6r8TN>FQI{
zmx(Yrb&`@zwnH;$|7UaAoEn3wqrhNq+5Xe)A=qlF`8x=T>n(qFU;rt~Au<k<$B7tO
zsd4Z_P+b@-T~__SJ9mg=u=P~)_rO<Zyh@KH#`l?~e(4{8!|@?KJpM5_zCnj1WnhLU
zFh!8y$}}kmZe>}8MZ*3QD<2C_u;nyr%`kvB;RrGk><FD64x}BS6j~Jk){g*v(2%%&
zIaGMHsfi{vk0`u-EM6cF3C(u{2DT&%u1u4HLW<IX!!GI1EO(Rg>5;tzTgozjo1bcn
zOXFOzc3ZTn@n9L~Zx9DtpBA<b1NP;0qOMO2u6j1tHMP#>Vob3l4hLbd&_)nG8*c#n
zGGS(6fq2cuqkj-&@uK<87RSjU3PVX^aS(>IA_}9BA9Vy*C1(HnqZ{Ta%JqOEETW>p
z;Y4Ms4E(|AYf~*<>n<=5|F%ZKMNNBRV7WaUyTx4Ft4cF%!T=5FN%%^pO_Izu)=#%H
zi#3wUAOmhtI|=1Y`n*sj&j8yQ^gETjceIFo3K<-X!eF6|Abcma!M63^{!`{yx2>Rd
zSUl8|+qN!GKSWp1w}u<Br3P-q>&DTE%48Y%ADuD&<;j+>g=ZMhsWn5)q}BcnYw_0u
zRU`vmswSd2UixEv)~qtXfE&>5RCTt!?59{ptIUgm^A9fk;_LJ3X{+6^odGtTRl&_q
z>`qDN5Gf26+6cmTQdiryGT8V26z$5sBb4g^z+j=c=Hk)+)wZqpX686f4&i}aV=P_^
z14hHc0uWCB`mkSJ+&Yf1FC#C5g+gV53>?36x{PJ_7gapf=gBfaBN=|$>U2oAH-@<3
zjUXezj?n2fhCHI*H2)R!AExYUOvJWYck3sz>xY_4u*Xl+jo9luc!1GMObvJpsW$i+
z0ITA4MZmhhyl$$Q$64x+?F^b%AaLY67t_6+gaH@{gzu!Twrxe8l>ONcTl2NQiPHgC
zXs@|=^nbPeBO-<_20LhAgCCZ!Op}5TT$LKEchwZ?kYND-TzCY@z`E5^?COcWz6t~W
zD$d*U9SL@O4QM81U=9p~zy8<W$lWiQTkiDqtefG@!Xfmg@puZ0D7;V^n*nG1$M9!$
z%i`^Y9V;gqK>UStlGA&1xKEGQab|2dUgN`h1c?3P<_x-q6a?$Z?K#@eoS5IiyYgqv
zV?(dLg0<8sEw6tAF277C*IcmEz=e;2a`b4wg@IMJPoZ;1kC1^GEVL2C;O)gUjuhr!
zKc#%|DG3z`H*@v}A2R-@Z_=*pyN~YC`T3vRFy@8tbLK<8cXZ^Jne}oh^9*esJu$MY
zP2wVm<K*BCvPmos!obEjKk6qQ(Ittn?|$_q<Nhg?{MLUQ(w+Yw^aJ%9AEAr$ubXgb
z-6~~KTaE#GqikO=`eh+lTr<n%f}VfMTl4ydPjEe&pLv$9toO{fcp6%j!(o8Fl&4AX
ze)Y!KcnRDKqiW2LkRG>Vl}R!XhV#hSH;)G{1o~l)wUcb?FpBnDFQc}#34k3ej(1<W
zam&%O!9v(rV^6T=^GiBWIUEMOp^36VFm}n!##eaZ7yjgxMbzl?It<u#f{HPI*^rZ5
zo_8OhJpT>7Hy<6-r%FNm(N{k7wt4hl(#iW_%hjo``w`bTmLd*B^g9*2%nQ~jaO69e
zl?=>aktl)~#4?Q|g?TOPNAap42>taB)A#lKC$w#)KV|e73X-q=^BZRIoBx$Jr{8$i
z`JlSy2jV~Q0D>&I0R2r8$H~FFzZfiD3j-VDTjFv+kbMc)RZXll=KF7)-ukU?K6~W;
z9Dd;?L|FTO5$4T1kIl)?;?nvh0A6otVRH`*ot&N=eW{9rQT$aJ!Qc5Pz4)na@a|zC
zf96e6ENGO!jjSj7&#kIV?#ba!{ATtFo}*!d`2P0Wozd~Ng?WX>nO4N~zU|(`$)+#H
zV&JqJkXHD!1>d%M1ky+^XtuvR;H^2;Z~F}3P1gJ#JEd)_x#jFi86L0WwpFLr6=ueK
z>FM6;nm&=B`>c3Bo`og3|Ioee4sG3-ttj>d1J3+uI%&9lKJW0YX}{TRTYG<Z^v-j)
zPR*l*H}4<Wd*)QXSPl0pT;sS2I(oF<331Crw5LZL5Qo>oV4;m5!Ifzo%ts$RZu=nN
zJ84_<JO5|5ZC%i~(*Li2_2nDp=+^1!>9gNBb$-!*NP)E1RcJUpdM9@1?nctx$MC8m
zahx3dFq9+~2VvlYKRoKRZN1xs{r&Xw^3Qx7+t!bSpQ!&c!2TWjLZ+u~pPG}OGv>Fy
zLLMrI!2oSr+Y0&Br|C+>Mfg)ISJD5ApPIj6o)5S3e@V9<+m=kdcFn*YOTVF16-T!M
zJbd!(ehtFXImS91K7|)52fzSrTXFBMNLnhNE#jva{vC?B<?#2&-lney!TsJi98~tn
z!1*xP?XYGWwq4db`crsE=9a(EFCL$qVNPELm2bE}E@Ji7?ildKztpY9s~A3h6O%VI
zl)YFy+wdd1a4YWB`ZP8Jj^1qzi>A{D&zW=c+ea2ZZB6p-bF@49E9UOveM^%o{?djD
z-Mq%%w&ItB!@O7-kE55dZT;V#JMwQYjO$0%y+Z@})<1COxo<4|<JZ2WB~b-u`eu(7
zK#;|Y=6Px8Vn`X-hZ|to(<6X{9WK*Yn2^okMNR%WReJaLPVq~^F65#B`|Pvk_%}cJ
z@=5q5;Wv+(d#Hg;)(-wBCBOQtH3q--@>45U;InkuxP>_hza;GR9^Acw4r5$f-(z;b
z@jkWiilc+2hkHv0mS{K(IgP(>)=<vb{jhDNUljH<#!HHzZR_znIDx#<JzevoMgL$V
z&4^Hx<Pp6c931erNE0Q!P8pbiro-?yB9L>sU6QP5x*%wgs3-|GhWp<A9zBQG_;U>X
zA4=~{*Y+uLlt#AB#OG)pBQFQfIDmM~u8nB$uq2Rl5hM)@f^Synw}1oetz-JFCFkin
zxD|XC?lk;64Tno4eG-*Tb3F_%QkzfED*pB0t9Vfry8FR#i4l2*9uND7n1LDm4YDQ>
zxN=Pl>T?vHek{SBgwOQf>wQr|sOQFcS5L3kr>il5x7-LqzaXr#X9oOcc=WT<Y69FG
zg1m`i=kM_n_j_Y;NG>?Jwt@*RP{F3kDjjF!A*N2!IYbJBg%*5=ff$}skIb<rkFuQk
znBC$RN}o2z<{d=%V~<}EKBj+Vb$&!Xxa(hQ377f!3|K?&wdPtD_L!EtFNL!4k0J2|
z;K%e|98OFTK3MfIG6Qd6U0W4T@78dewak^&#(d&2j*iUd!3Ae3qcX6d!Fs->0{0{2
z_0u$L^!tbD-TltL=Z@~1+mDWxH@tat-?b!~y^omdnmT54aeSZQT_Ow~`4ULFK_(4?
zp1%L|S1*PM0U3Gc6?!xN7c`*wK~4{Q`lWx(96$Y<x9-VPi^V^QKaS00xGrj3^o;DL
z#@VQZrBFYg34=qv2$C7~w{7>2%Hdj)<G(?F0P^hbQnufx-wEzu{qp^%%+c#V?v4GU
z8|J0OccKE7Ltwz!6W>zD$-{p_SI-+3|2jFnyBFV}doO*(z-{y3d2{<M*OEwm_QC+&
zF5YMaa^y!J{d&_cj85qjMQh9>gwwM*>F*slSJ@8(!#hf6Jf?w0p<D3j_nM;+K|{N^
zZ5A$sc6Z;m8q=uTt{FHoUub~{Z%_NFg~d$GFOWNi-n3BPPWR@Pj5GBC5eFdjHhUCq
zpv79~n<8-g?SDu7HQZ}$7-?t8fS={iyIz0TN<0Ks=y_zhf$xrOxebSH>u*rimi9TZ
z=qJz6Z#MlRojtm7+nVl99BtS388ldQk0EYeZNSmdBi!=hfW!>U;Ng`(;L0@!y1QKT
z(<7af<PG`}`A_^FdE9#cG+qa%f9=mu;op2|;ohSg^U=e*51P9uK~3C-`!FNBsh>1X
zaVROuBT^U~v=Jn;ZT+$(A4FDU`8It|<=J07cIIclzx#<g1$^P1zhlgubNYnhefoxh
z-^V|bRXGd>&gnCw2D$xP^vS+|gTCMU2i%4G>$Fh1w>)~<eBL}bee}!m-f`ieuSR0v
z3PWL0V!X{B<3~4!eg%eBQ)D=%nS{=-kPXRHcEf-(z9n(*gd6(8ycQxz6-W5w_?Cmt
zUf~xQ;XgwGLkA(RH&lUHoa7cgJ7Yc;=4(2)^cJP_<2R0uES;+Ce}A(aCLLSOD~azu
zdWe6A<0Ws5_s7N^%w>9|Zf5IDzurJQmnL!MeY)+s58E_>p8UGI{hL4kG<`~Z^p-jO
zA=i{<?oP+lphc6o$HjRH=UH)Nfg_&7oiGv{GcbdPR|0`6*C6QbS82mp6GsjNdwl+R
zdi6_x)O{w5AH6R=K|dz=dHUybe@I_adh0_?Jy6)Z1@|pRcD3Dm<dMcH4khV4B89<0
z8$smd;K}OVwsfpX4}1FL=!Z|tzx#u49e2Ox{f>Y5=glj3e&5`%j~C|6#jB`D<p3CP
z^wZYnGP=L4{Nz(Hz%D*>0~gcDXUxxk*c`p(qCuZWX5iGEwGRfZmhk5HxGe<f)>}5b
zb~s*n0Tx29{UH&$EhZiq-;gT7F7Z|Fx5E9LhInye?j!oy=a1d7KQ+IkH{k{{_vUim
zhGgj{H*b^cbAOfl(+B@Y4)5cS9ea9KxiSOmza9KA78X=>>0o^~3;Pv+k9X^9^uRY+
z(!cVGds=#ZJ!P!{vg>o@)(<s3?1`ZdlWw?w1%IhEh<)crPie<Wx9E3YCWU^RdzjHM
zV_EQnA#Pre!qL$Ki<k7ldd$EKo*b}H?LgR0%EA<b@VY7lYn}Ov#{AJQJ|AK2n|F`D
zc-K)qKT4b5TMt_Pg;o`4@(yuaJURjWO_IiGWmG&Og~34^LBj6@GL47%6X$g3-+VaF
z3bH@G@xyPJ8#KV(HR!zic4Iz$PE+n<Du(`d*>E)!7{I?j-nKN1X}sh-2F_YsPmq&4
z4nL}09^EkyUJ4pLti=G{dfOIvrG!+$J0}Ri*wTlFbbL&2Ui!xx^h)Jm82HRpZk@Dk
z#cjR22jgBGR=yYa_k-z53%LRV^bUPMp9cHiU5T;u`Xt_#SM>UFIt<vCeh9@bjP*2<
zb~=UcsZzfdj$JEi<Ddw8`Yz3^=l_fM<~MG9wa@y%eE!s%Ke-WoHU^t?0!P(jp0f0y
ziyzZeqrlO@mne?=$CQB?JULu|Y`$$ZKk=g<Ju!dwqYHEQAH9s+9qb<)^W%T=0lz>!
zDi`D8K}Os|6p69DBc9Vx(o2tXag{h|)8LEC!NYuISo`xYo|xbIlyMa7>CwT`FA0Zw
zpisFg1NeP}5o8ti<dd`zezNF>l<ph2(-`_CVU;N}Kz~?e@Sm{i9eB#4YEF;M%gcM+
zy*=G_?;p8IH#K(gBfTdg?4lpN?#8=9hES~7^yR@bK)(P%;tsyfX%*<lDL29X?;rS;
z)e6EGo6pma3YItSuNtoPYq24zvH>2&J_S*@2?~RUC4p?PZH=(!^p|e1JN0KFbr1V<
z^!9y1Utb&V)Ihzi;;3=(z{qYQBaKrWN{aG`6b1)v1i70Zb+}ap+0S36UrGCiA58zY
z)gvmv>b4bB7-Pe6YKPaU;6F~kB%G>0(`{?wV!|)nMeX+DrM{Xh1CD-0__fuKuU%;6
z$YC;3nJNRvt3!Ix1g3eF$ujU@sPZ4eqDf`444hajtH0<&1O0Z!g+J@DywRUdwzusR
z?kG*z86e%tP6elB5&IOl#|#c9aZBTIl0eu_%EA<b@VY91{jD#4;M5$wcx;|E#v_6<
zoZLHq`sg*?wt^00EIkDMFjOUt)5@rLL<xg~Hi8sBtbkipkp27}+P3~}8sL+^6#O5(
z^*_*`&i+30*nXXgK|Lx{WZ-2g`iD+VZupZ^eDz`Yy9-PDt|s%7Q|v}-W(?5n+^s6Y
ziN04?DVf;oFoLMr;y@pL9y>f8c^p;t&Vb*-y9v`Y$*1rf(^+WZnF}X+m=*&V&i;#j
zUWt`sft*A?X-ZT~?Ztclz&~fc5f<1Nr7!6pL8^2Nhz&^-F(YnU9SZ!lZ#yw(U%4M@
z#hp0R^W=xSom9|X^8@Z_>@$KUK87v^k4Rx~&_<ALY+EhmqhAv4hLT=;dI0v+>Q7ri
z1+f#36Fi)J@-0#ILVw!Yb28z@#mO6&C(^ho7UQjo=`ir}rR5Uc=#Ly*5KpI<T~z9k
zl+B1W6o>B_OzRYQW9lTaI0(ba#O=GU)mhQ31R=O23HFS<JUqX*dxKiM#;1tL>*%4v
zS4*~ukoRs53?N0aYeOuRJ#sr7a1qFng{3GF_9JxVgzUFE_XLaYp3wJeN6JHb@|dP*
zX=$F&qb~Grc>*u`<xTS{J(k^@<{|?#JVPD{B)BroI<S^t9sN$Q#RbyC+KYOiRJk$(
z?#dBc2^a}>E45EHNqFPzv3lUq9XG;y2kdx;*Vk7t!O0o1%EyvC#MFtX(rU?c^D!Vj
zeAA2=gP<(RlB@ytEsp^_ruq4tR2?jRZLM+0tRp+=^#u*^5|_q>te)xMUhp!3SMSCe
zExiago2by|sWNb4{`_(O=gNNasiT{J_S@)J)K+A9$F7`R@0W6}YvCjC7biv6M~K-n
z7;rmGAX1Zp`Xr^NQ+q_1fW7-O^k+1_(tUcEGW_^=>9#e}H@NhP#_V$%r^G3_vH?s6
zHux49nI;CoP?ZSlpZ@_`fj#(c1km4?>#v(L+AafDWr7TJ*UNu<WZcj5&-xc%#Py;w
zT?US6H{&sgI*^Aji1=0BEr>V9)8ye!?P@Z7(fjJTzMdKbtHYOG>$KVrBbG~3lO+m1
zHm|TjWG7SWXzTS(kqrkH+`sYElm1sqS4g2hd9Ttj5Vs6rXJA`d365-^LXo&gq#<oT
z$Z8x8Op}6Osfi_rQ^0=aFMIFknZ!{BZ}IBQi?0a5>9v+gZd=XU@0!IcH@m;s5U-NA
zmbz`7?xh?S)3gr0eSh(~?QaiVH%}IRx@~FYhBmF%x`koGXqA|$GvGo4?yc26+==Ob
z3b3lZj<2V<zX{`Hailr58^=!vU0AVoudexV@B1768ScjH+l@15f`ek<oc?X=Bm8<J
zZEn7^tL)g&{zj!^V2y1nk!KMM64UmGUZ))>GsNwOClBLrV44&JOHml?Lu2m0_c8cC
zzVoG{e{AW+;?0lhPg}tVB#lcXyHgjAkI6Q8F~kfW!D+bI7+aW_CI-P!l*eQR?AQDY
z3-ibH)7F<dcN;Q%gWk2YZGC?4(@Ix_9yev+<PTpm_PzhEd(-#H?wL>0t0%Z#R3^!Q
zrMD%$KkdTFK_r{Xx(wh>ID+)BmVT%T^sqPcv5v)KXyiagyFMQ<0~kt=`tH$VvGPm8
zP#){FN-V4|8_*ZtXKNz&u$~6=nBJC_7Eqpa59lTC%KBDKyskAs#OvC!!Cf-JKE!VI
z{OIWEw{9CWVDFv$g!v+U1)}-j+I7t<kS=n}SRP#khVY_AESxY#xGg$*KvD)~z#A!n
zIQTJ53WB9377qW@zv}GC`^V;uKm1gHfBt*vr>$S7AJM(}SNa*ZmgXAR)3`*kn|e;;
zv^pv=gGY*FSRG?)VOrIsF@~Wkfc@Q{zKMTRMeou-{tJk9^f*5K14Dm0MSt2_WiapX
zFmKwWCBc4rfzdV2{X5~ua=0!(VZO(Bx)JXZf9|=#;|OvA8-9tOD)7%@9P!3gnK}dZ
z#LzUlB4M}}&e1&k){0tRPKtqeqxJXuSGXh7m*mk5t1?{%((uu6rq|R?m~W@s*65Y{
zaVn6o-`W3k^^<04K7D_jsty$u7kOYTY#Casv~a{t5EGlD2P9=+2E3yZh=U)~q##&o
zV&M?8pMT*4VOl-@g@yU{ze#@_G8$@Gu7f>|OC-D6v?q@=POGC5Gr%D;#ulbXzr#rk
z!t0`VvSwlL{=<cbgD#6f!dmiRt*DKIim?6#8?Kg(Q8d8;F!0U+)SxA7m4PK?JBt}{
zUsu_Pfv`^5D8pL8E3iH!SQ$!Bv#wn$s|Fno14AQtg2kH(7{Ds@>at$c)p0IG^sqLm
zm!I;abK(4-Cau1}+Hr8pP^89@)xrZe!L&W1*J-cA3>b|B;^-u8X*^C+5Kc<s$Y}A1
z*~4FcG{z&t*-z0S8tCQq79t{zOQgSvku*-LqY^WCq)3KHwj<@ar9-0M;Uos(byYYl
z{_-Qq5&g>d7tfB)Jx&07-NjFvfS>Hj_w=)K&%Z`u+I?yD#DKm(FJA_@r%hOVxSd;L
zyZictJK1jO6Cc(KGHBbnva7w&>nmkI88|owblb{@gl`$REq`WVTHU$ed~i#XHZUG8
z4u`m<@i<9AIH`$+!w{@)TQ5<!*KI2nH<!jGj`5|khELfwcy2Mk{kHYTXpe&vT^56d
zNy}-s;={Jp{iklyt!%Y;yVYzXB<tR;T^o4YtIU7_7e><J#!KU?8=TRG^wtiLyF2mO
zD?3O%(Uf|DPjuj}L)o9CoAB%II&|9JBil0A*0|t^^-9_v(Q9JYNJHGfc(NLY1Jk4+
zSZZS7AYgxiU|-T-5@zJ3afxIzYwl$5Vu%?$qSA1&QLr#EO$>seDp}a~-dz}vaKNg}
zg#q`8E&a8QxezjwK3umRo=G>_M$do_>!nK}PHrChrm5-Uy`x1$oG9s~$2l@syod&e
zlOE*O#S&`^u)l-MBms%m2sWPJ`5FrifkXR@;wm4@7X}89qU3r;jO^f8ciFBE+y8^~
z4wgnWT~O6jGk2ijT!Q*%=<$#qzUd2`m%ZbQ6!C-}hCXSBqzugPDp?XpaAlel6jGE9
zO9>mk_WL0&iyNoMCc&1ns4dF?u7nX}B-jx;-4Jq%L}B~8Z?WB{A@oGw6ODrk81OiB
zQxm;tpPJ}aZ4rvAB7K@cuTutQU=z0^H$Ii8AXtiW8P+d+xGvwOBHUtmQBN_88V{6#
zQ(P$BMRZZ2yLhRuCdoi}i&EtdZ}eWyeSD?QQ)FOq{;_9Kw=?hJ2RFT(F5*~6&GmkE
zXrIk~Eqr)5rAe`8R8G<`q`5cTIfW(#A!AKEIUK$I-QHMZy#Gtz<><Uy8+`5f<f0yE
zuen(C&&X~e#KGzE#lQwI4Hp}Hk2t1DL9o=s!6CseyX`VEEWh=cqhx@S%48XMf~&EY
z58^UXnH>Y+uk;>BS9aVw+`i$@wg^b~V%&bCth{rh%A1${i9LFUJ<(s}z|@?cqI2ol
z(foaE7AsHWoifCHE1I_mVLTZVd-JZ@K!S21i~H{M^!S)Roh)ASr}nsi5-~%Hm)yze
z(c6ZeO#fs|$`BG6$_EXV(LW94QC*z@$6Zd?D0AC2I~%ybr@=rRLL1BV_V(%>IjTo`
z9=Q~Pcj!EA8Cq%ZaAf-wI>$xg>A?+X(LoCkzLVM<7RdwbYj;feP9_VG9ZI~O$`Iqf
zT`USjv59^tYU1E<c~nvcW?+Nw5yvzs2$q^SIHc^W+g797)*5+Ju|HXP>)7$%AXB03
z;Op$Z6S^zYt&H&~g+IR7Z~3un8HIo?fu7K;iW_neWim1`-DiKf^kd`QW!=8dM=xOC
z4PW4G>G$r%JbKctz%PLG)kGPfxwQY28fd_p`xEVB2W8Vv!y#?jGBjaOl!qfd6P+ae
z0wL@lan1~B0~4k}xH3%&LSRt@?3?uMl_Vj<gAcF37Srs^h^`Mqh-r&T7}>SbJViM;
zVVqV+Wq7#Q7<<GqO$vggBodZwTR(77Pbtf;Z2grT{{C}%y(_SJ=Y6um-|Nq<oXorJ
z*>{KAMHIJ(VZ9x}hMp}`u9n6OdpPlHVYs!THVztqJ@siUFJ5g7v_=9kh^ekMl4(d}
zz#1Q4j{7XecZ_oETA)}ZttnU^tt$htZ(roH;a5yA&h^z*8Q9>8#2R>Ak+84Zl<ON$
zJ)d5W{o?M}1rWYN4Pb0_rvhD3JgjV=Lgy(1Go%en7#7SqOp}6;u_hi4Df^8t8cXLP
z!~gS9b0-<#wSVD%`+5KP4AJ6@k<HAR69@g}i(z=U64?aeJ>ph17h?=dO&lDCV3)UV
z-${mAmi^el>6BzSPQhhZTq-J?Fkm+cUO#paHr&`lPWqSVDl=igQy=}}dYoIxOnB5b
ziVWx-qe#zGjaZaVRW9bUy>>7TtlevmR{<+l=8);~mI1n=cv#s!h0fCslo{Brhwr5J
z2Ai)8eN=_D5Z{oP%bB6jTb__zREB;m4y;5dibA8|;Ba|VSd+u`dc+Mk2}@BnfX!D{
zM1;}OLljIpPY-U8nmnvUG-I8S3BamY@))YD8aV9WP|p5kB-q3GNb)k}hg;d@O7&bB
zPzJWjfZb}g=42zmV$M5EIo!$)ldtPp71nnn$T+ZmgihNaGnI8}ha7Bi4MkCCA?)G6
z7T0t>yrp4_{KA?Z8H=(3Y`(H0B8&)SEkFSgyA!F&!#ZSOtTQs3uHZ~%A+@mpU?oCP
z69)%Y7M+XkJ-k-y^>1F*Tm->V69<Q@!(M=}SX9;|t1X0F6y*`QYAE$4U@f8<>%s*d
zRaq^duPk16)mU|y5(7=|^eHu@wJHO%WdQeOmDw?X8CyjePzEN$fJ3Ehaotk7hZ9>|
z(|N-#t+1v?#+rCItO1*^tcDouV&ev_*qumC9@ZfPW1V%?yqF!V47n{1tVAek;^4r_
zqH}@a;l=8eniK@znm9PD0h>TrEGlaf)&g>ocpR8PYVxoa(Tw%&Rfg0m%78L30S5ZJ
z$pk9Z5)Ye!L->beyJBe0z3qxK&D+X=Z*^3^=`r9?GFx1?^x)ydR`+z?uuChf>5;J}
z9u8~3<}0fq2D{j&Kr419Qj>>u$iP@<T{W+I1}j5uivueWikdh$u(Ie}V0d`3dZi`>
z!M7$34r{<B5EhHdnuN80TqGU`W{{dZtVJ|qeS4K5wTd#J3@8K2z^Dv}37}fdm&rq}
z21qI92a8-QQ^?(csXPY3wI~HxJ5bLGY^ky$BpDsPHBICqou$XBq12m)FPn%3>(T`=
zCCOHXprMLO$;kHE0h&nd5Eci?<3uzfH4c6Vs>}MY4#|frtHQo_Qw(5;xk_*HJs?<@
zF6&l?)W+b?DZWaNB~G8AM_uTTSi|ulJv_ZOFLog*12a5<F@gkFrb$6?E6e(@2}D*_
zh9v8mF;CzWTL`)698Eu=M>0rF0hVPGWQM%RU6kR<d@-hE#DzM7j05XN=(G)TAC=j*
zQnu|i5^US7vF&D?@||{G4o_^}>GXvoeb>H+nN2Trj*Olj+`twGCO@eluqYeA<|`{A
z!nmXdYoX^&b|N)-SVvho>x@hQR%J;Zva%Cb4O9nZKp9X5rpQ3IbC^cuVy<f{o6W_T
z6-XQo!eF6|Af-tcel-!<DZn8}7%a3A*5PE>1(upvI8d(RG?CG{oC<};A#NCU%avVB
zv4AA;IIx1CsER0yA}peWfvp+}O(M7|B0EJ`L<s|f&ATABDl!*^h~bhNi_H7445%u~
zfHI&A3^1@9(9K14D7|6EP?;SAO&?^;u4`>b8JHpiSa}buznfZ-t9xS{B89<18yER}
zCzW=A2x=0MouV8fg~37_VI59{%XdKAA{I_87oD>`VYu-LjYFJ(wa~I`!!B^EiG>5p
z)oob2BP*zuD%e>nltp535C*pAD>RAVs)+0qVG$(^3^wnA*s91}6e7k#YAiDEzcQez
zC<9YwKo^Kp9=&YsxEZP_1Ij=v181#{6ZD&NZ-+1(?huL?y9TlTt`>ylzFgfK;}9tf
z7TO3RH+v3d1XZO3>&vhX$%kF4uvEH*Q*6QEgnqw??FmQOwq`0rq3dj0TYtxWfXNKE
zp%PS6k_})j^0IM>V_X6Zw#RhD1?A~+aZ%Fim?0UY#**7GYzoS|Ahsxv$vRM(F9xYm
z88|!!{I*NNJ$K&Hbj#d61y_Q_-DxY*C-PfKw$&t=7WGq?t+G7zWNw@WMuI)un{TEv
zEaldbk>2GcSi4RiO)<X7YYeAyWn$UiRH9tn8{-fu3>Ml5a<M~*8V7Up1tzjnaLOPT
z`w`^FB8YT>r6v{*F_*&$3EnFfFQP$e9L%C*3vCQ?I2m?<r6v{*ELR`l@ytr>4do}6
z3T2U49E5=}d26@>1T~4sPEi(-!oXnjE{Ls)%taxWJ2@@%h8v9o%;lg$@o=xoU}e>)
zVF&zk+Yw|O*oUp1W@ft9@T>bZSJsx=x4CWGYpbxh%G;zgqqk+)mDk}`wyTb-d2usT
zQ3etN?eFsxqAw1g0Xx?cN4lqv1M3fV6!Vqgh9Y(bO?`-kIz>4|3WJ3<g7BRb2Fk&V
zpe7O7Das*I7%a3A*5PE>1(upvIIvuF&h~`ik`o$-xM5h9ZP*3DHL-ADxw=#1VPFM8
zQ55vRQlTsoi-R!W(($kWq|hX+MQMV411W}S8mz4PW!;|gu@)>TAS)p5sL~rscb9@L
zu`XQTUKCH(!ODtJdE?EzX_uBJSd86P<-u07Z8O>7R<_M9HJ37=3<w6i(CkIACTu_N
zuU#VMypp(*ai_LgWjh5QJ9${l?63&G!`ypKZTE_nz*=B^^4{8uP2cTXD?}tJRwkDH
zBK)!f*FRFS#WkHfdPswXHiGb-6kF57ttc(9Cmt!_Y4IY$I-H1-EwnXp<Y3{%a?!Z}
zks61%VOW-J*ag8Qab&b`V7Z{6f$?}|B|=dZmI`H&SR90b4SwM#k_fJf$W9R!QNqAr
z@AWSJX?o#s5}Cy7s<2$PcaIr7&Ou<IH+KEXY=gxkZB=A0w0Es1-706(bg<JbTdP(E
zlmTU6OAKJ9RGA$ESWBrW1KVZ*%VV*)ZUPajdx~<16b1`z1mQa=w(N&nRYZ1*aEKBH
z3vGmTI2m?<r6v{*EEk=#Jz>~U2#rJBFf7Y9?1JE$SU9j;P*61<&#WLQs=`vCEE0=@
zFtD9fp-BW+MP#Q4izs1Wuz456Rz>Eb5HS`~W085^m3e@wC<DrXGN24x8wSqz+Ns+s
z+J1Z6YioxE<`1hJtwtHxlmW5+Zb~Ru_r^Fx3WJ3<g7BS`Zd*&7fw!7iI7D(CPI~cp
zp2fCR{wP)U#x5l6Mw?`vZ7Y8F)gn71y?oI-_(vDKuF7C#`qS1bZ_{(I-Me&pg=@tn
z2Ac0dr6g)QPzEgOViQ2E&_{IpcW{c+fX4}mn7KT(D--wmz$eft2)-p*AJ!HsD<KBk
z$LYAzLi#-+59^A7_jb%FWlXIEl{iEGqU0(=kiaNr3dYYZBuy}|Yh$<(ImO4Iox(;C
z2NYIW6?XZ8@o-{1(YfqIYVxowTe`5fQyHo?FVf=)Uf|m{Ud4;5&>yje;}TUrLyw1j
zM9jbp{svhS2wb@)2K6}#PaD8S5LsCPuQM%&3MP~6L~8P|iIBX@+LcuUGY+R2{f^Zm
z!Q$dQOxZ(aew@xng2ip~a0PdGIU`o<JtGe`4TL;H%P290@F|K-D!YVrNG?jY&{l;e
z5ep~0H&Vg$`YOHQM&s!rgB-M5t_<l^=EZ=WS3BB`GBA4v<P6c$a++h}tbiak`9y<<
zC4uDU7`RnsUD$kORY-F1a7ry87m4gdYVxowo9N01goZ<KWVvFHpg$Ul&ny+nBJnr~
zgM&7LTr4@F#>0%DCK1^w$|F)39JB(&Ld(d8q9zUwEEk=Nv5*>%xcyfKR25}F8Bhj>
z7{KR<bCo&wHrFwmR9{#IsLYE2TFUin^=bBnC8mmCprb{szlGnBLay$~i)|d(ejtJ5
zw{}A)LdRgA?ad9ac^3gOpzzS87W%h>>_lqvuq+$vDrFfcM5sJ8ELU_9^hZPSnWaKm
zBpwH0aL`7O!qyIMRT0@K!Xru;9JCSE<7C(cmYO&?uv~O5#zJa5;)Y>awqX|p*Tlhr
z<*G%fT^UdYlmTU6#|+@EtTH<W`bFK|`daP{Y5zcn(i>LNDl=t3EUv44I`WXKdr~&+
z($c1Ezp(krs@+nd9!{)aI+vYDO&*qI6J!QJfEFcJSqNgA9-vj_9(jneNaqnL3=Y}|
zA}<FI^R8hNhy@xW8;X*6D&4^$w%~C>BE~{$Jp9Up6kHHol5AzAAhjt2%D@a5Xu4%?
zzt3@C-S!*VQpUrrY)cJlnr$$ECC3Od4(#FX0`rxv#grXkNC|QzSS)}KQ!<qu8&CC$
z^><Sba&=E(xJZP-BVPi^Z|&e#6_Fhg4X}BaDkM30IHeYli$r!JHF;Q;O?2f0Lc<|A
zvRvIp?9z4&9!<hhp)3-QgD^N~<DT#Ca0k1F^{8REGFWQj;1FBzI3W?86ne7=xat@q
zrX~&!mn*9UW$gIpwj;<mu*?3<IYPq~$Zc1axu;jE*w{P{tlhZoT_rf&%68SU=2Zri
z0cBtc4EVK*v};9e95fQ_I5T<+TiMDSMT=#BOGdf6M^wWKKEJiwDQv#77FZ7_#uJ^(
zPNXIe%d&~BQUC;KO*|Y}uI}{GrUxEXvE;#0wQpPH<=_FgYuE&0fyT&&qA2v9aB#qT
zBMltA7Gohbp4=o;4qBE?kQrRyR+L<2#h|?L`MhbDmT_PmE`o!U!>#Nf>C&Q<ff+G?
zd0_+@2iA_zX&dC>R@PR(dhLS&zYh?JF%oRQ%9r(wt|?X~7T48svC5aLds4EE!|)0|
z?GW}0o3E_eErohGv4ZJbb|N)-Se8wY82|xVlw4)TQJA2=m?|1YS!D1q3WI|-f)sut
z3Ad_<>=fY<B@7PQ2<ve&>;g+o92{6KIu~P6=*=R*RmT`HHF0pbRN2B<XjNv#fS*-2
z+Ke)w3@8K2fHI&AC<8lUz)@bY>~F#nt9wK>tl;xoyPd-3D{F!EaAG{sx$H!0@~|wM
zATt00v?d-7EEg1(9&FPCk0xQMP!@^DK^Ppg5kzkGJj}a>O&}I%jBF@s;@}Wl@Hin6
zV<9yjeq}-mE(orPgTtlDaH^sVC<DrXGH`7e@R-(SDs%2_rbDJ}DFX+=fLMPwRV7#V
z6vj3VY}K7W@>{!|!saV$f%R}oE%ft<>_lqvuq>M(GXMg#CLRtfSBwz!M?>+MrP6IH
zM)Xj&t;X2m(5Z2X4EXNzuPK(UHRl;{d6QZu&wxh<Y^toa<ZhFPSPhWQB2pMuRuX=}
zKfl})Y^gGoT$C@9b)|(q7b!0-N{YP=FN#?E!lhUhjM>V_Hdt{v<9jy;29QF^ReB_K
zI9%f6f+!gCvH@(qvOHY0e0HE<vN_mUCsLD#m8^?*1M-(8Q&|XlNJo!9poMSSctVf5
zob`@Rk?X7USfV77lz|zZAxi=Yu1u4HLW<I11K0#2Dk}kYHsVGUOcvRR)Z}3kA$gaz
zE2{?%d$?isuC*h<;w^WWvX9DeKN>;Cfwd!a+75XNS1|!p<Co+yIKhkg0RWyJ7a&p-
zgWy(_C0W;njUWyPY(|8lD0eQm&`&wC6RF9=3f3Kp*iL02No8IP_<6OX-6#XIXF$#e
zEiGF(v5AAu8>S0~I5vT#AXsW*;jjj50%5Vut1VG5RpC$yGe}JyR<gdm%23$w8YEas
z2U!+*vnGdIvPddAK(;1X7dBs66RaqhqAVhrL2B}_V&&(Nj&TM>RagOlQ&9$#0cD`T
z0Br$hD|7B`wu3gM#`M#ODUDWJt+rcvwK=QTR2b-X6@y!bY6}(~Y;jHJY<WJsf_I1;
zUiQOM6AOnmVDpvL5QAM5Oj-vEGe}JyR<h2zLf$4}1pqFJpg$Ul&$29X7Z?^fSiMpc
zgWy_~bzvij2LdCz3JC|+0&<a99GF3B^00z+k96Cq44G7v0cAiLPzJ_gK=(IeF~3vX
z)uq!;fnsv}BHUc%Kzeg?<yZS!>z9OSRc}EZTiw$+Tb>WE;2q+Im;JC5WdqoJWkp07
zv856Plg`nD8>A)=D>rJ4OaN9TS6K)Y^jFh8CJ$K_DMj~|lzi}|CI-Q^D38gyE^Gwx
zKwxA;QIz(7zF?6@jE*e1(WO`wjJe9Hf$E?PC<D`G0JoJ9WF%PJG7nP@x3a_J>v~p&
zCC3Od4y+rY(>BO_Wot3z+fcXdH4^OMeh!zZjOHp@_sjKn%XnBgv4uLFvyFq;H+h6O
z9ENuru++rDVGY=PWi`ZL7X_2n!NLqulZTb8v#yZ0Nmv2ho3tBkL4Q*^Sr&x}42xW=
z^_~k&3W94@)`U$U9te!=DkL0MTL`&GXD=HHy?OXDSi!n<K}=PKDys$!J3Jg#?^-(&
zEdG)6Vak>(>)z#iZ*?44zxO^{0S~vb)(+H98Bhk4fmt%pypCS&-mjkQ@AXKq<ILzS
zwB{?L<?-N_p_<jggDtM<ykQ0J5I4LJf~6)F4r{>XE2|*}yC|5n4i;vRnmnvzoppu0
zO~MKQTsNTW{M%OF$Kv^7DCxDpu<&5@N=*!cYf(H|B^#uS8Q^eH4};CSAf_mIPl#Nk
zvxs5_sma44tD{Gucvy>)tE?E5H$KRlc4-+2_U0~o+9>zoR<==F8mtT`12qQnE3jJR
zM)q-F{YEwKGWc*S+hy09`-%);eK&%P18Ya<v<<RY+2EF;nAedtq-3jmQa0?;5Sv-k
z!%`AQMhk~EVDptBVNnn&_9>)uh++n*$-_$4SyxS0aIUhzkk~+>+^Wd3D1<dR*wVR0
zX3+t%HOZQ=h02;>MZpwh5xHtO7n%aBVBI4f;|z+btQHX9ki=KR)M0WAG`-U&*OeBm
z3@8K2fHI&AC<DsCmKmVs@!*!B3S;5H7T0vnmgmDOc!#**eGn`)v2a)eHeXo{G1x`H
zq;;?`gVf|<CF`s!<ZTjG0N@~=9)f-tsv^sx5P@Nlht(@JF$k_zSr;~fcpxyctB`PD
zEg%<(#eo^5CJ!rE_ei&u%8*(`8Bhk40cGI&FmP+et<Jf(84sJbrVNbDz~GjlT9kzc
zTiw$+Tb>WE;2q+Im;JER#KK_>*nDL*#9$W%lh(n)3{sPam8`R_khe)#0f37l=#Pft
zvn-3;1%^cqR<G2=Ah=d#UDycXfxyVFLc)QyfLtUN2WF6(Jgi{dBi(i?Ga(o9smzCg
zBje`NjCK+kz#T+ot_+9?pxWri$%9P;{il!~k;34h?LltIPoO=_2&&2etVd8d^sq;K
zx)Z%w1h5$qijq8{91adF7oA_89!tGhBw(;C+c0N{DM_|63UUZ!7*G^t`2u6ItCu3=
zdPX!-Xsrkd;|8$#%Bra5a|<zmA?PZ-4G$Y*UAU}Y86uY`?-_bLq=#?%lH+CX_##C-
zp@-?emm+0ghF8fUfdp5kNkK?dl;!%c2}D#@L<~my<6@#<7|=8`NKGC#5t4Ta;Kf6(
zvSLudh$~?P83*=sgihNa_fc6ty|xv!J+E<K{q`EzK_-Ws7;}#o>F$n`qR_3{!U1oe
zv~Zx;DFZXGDa4T*pUP7ZEJfJ>Hi3xBiij|t(Sx;sTqF($W{{dZtYm$Am047#GA{;j
zrKu<b%D`k8aHy2c5G|#9II)R?&ReDnF@dBYWUPsY!y2#&gvB<mw$kz;@`N%(CsLD#
zb;uC2d7NyqGNiLOuo9uDiGu?xi_S&&9$u_osYyZbt%-xf8n6k3#iFt%VJ#pRiN}E%
zq$Uq*5zScNUS&wFq6{bl%D@l<XG6-F=;qwpOonLMZP;m-uhkDQ;JY2kfJIdkX26Bo
z!;vknTUzpPVyk;PZ`h?3*7V3&6AuRlOO-dk=3Q!t!7lbG(2CuO)Z}3uGBDOzSN$Fe
zPGuRa3?UW=Rw5KNad2Q|(Ye6z@M85!O$vf<O&lE7fK4DQ7L_##YXP}PJPyntHF;Qz
zXvX^XDnn`&Wk4BF2CfqWxSbx3*uyDBE7=|cSgGw*=vS&{D~HnCVcj`qGu-wNI&mn1
zEv~Co(W>6ViLLJGykVDCSkoh8Q8s|hS5`!X(a}TfQ(zFg6RF9=A}eQ|k=gH|;FK3f
zroqY(VsT(4LQxV=7lDJr<%>aJczCgTr6vWzw<MduCJ<IKDyzyp@?b3>7m3G#8Kfo;
zYZ1*@-(F=%t)dJl12bm8jnmsmuuXUBQ5ZSg%0{6>K?fPw`)0SRVkB6sYYtPgm957V
z)@&olIIwnvPTL?emASC%p`+ZXKvxtGD_h;udBZNPu%<`Gns_)AVX+-4fUwwpr-F#G
zh<ys&#qLCE8VJd|luPQZ1C`le3P)CAA5naAu(F*NoeK;PuT>`fo0l~gL9o=s!Qtw#
z7a%Mal{Lv~3n3Rpc|@)nSZ}ABk1_IBWwn4<Sv6?bVVS+B5BqOPI}$AZk@MBXT|MN=
z5$jc!g|S)7P7Nc$jx(dTFnPF@wN$S@%78MU49t~*<`q68V5EEcIIxzren=<z%4m7)
zP$?Ko8z?Ah;^Dv+*L0pTFaz856qfzSSQ8HimYvQUVDm0WSQXX+azWUhFkEs%lZSQ4
zz*uKpHNV{kDhsKN1pq4uilR_C4i2m=Iu{roUaVfJNkQ-}$_B6rgq4iSs$$85wSZhC
z9tUQSnmnvUG-G{xl_B*S;!w{1WhB_=_upwF;^9`-*nqkz1Ioa94A}L;HjNqy7IWTV
z%HdXan0#H&s`{nizMCHh*6+K`X1ro$4r$op8j7OOLfFHBt?uc(VV71|(<5V1Hh|4n
zRz!pmp<<r`gV>!&O&-=E17n?$*>nYGE5pE80I(9FsELCED~rxW_a0uW^|GHx?hm$5
z87i#GY6~G3MR-K58cMw}rdES?P#KLj;8f<tK+`*YUM*`k%78MU3@8K2fHI&AT%7@0
zYCA-+^><4e4=1)zr}Ktg8sACn4K`mH`lyQ7xFLe=3B!&;X!5WQ8Cd&_%;v@HU}Z>b
z0l*4^q9zUwtSmYg7#?1%Ua3hz@U4l1!y2#&gvFw=CSffg7m3G#8Kfo;YZ1*@-&$oM
zHPWjn1ImChpbT6K2JX(d%Q^Qp<6+a*l!37sa43K+u3IYdaAK=_I&ave71s2~SQ8J2
zHDL3V)ewVS>{Fl>yA!F&!#ZSOth28AJrtbEGFTZxEDo$hC~D&1z{;X?f#KoB>Xn)l
z1mBuCIIIDiKv*m)YZBH1a*=o(m_cgtuolsb_3c&GF$4gW`7l7&60R4Oc`?v@51Loo
z*Q6UU0aW|`GI_|=04c@%V3BKO3b|`8Yc7J|T9ox+FF-sH*o;_&B%`}chm{u6%w-X|
zVkq_I;mcqJ>(T`=CCOHXpq0W>#ie9q`|JQsq;?1^k8Ghe1eaxfSck;Jm6ajM`rgff
zOOf<qkfg>T`7o?teei99_`KvQ3lUGz@l|>(f%HsJ)eiJWtl{{O9-dyC{(C7>24;9d
z4km&GSEflpa4XCDun9y~R)!?&nK4h`6k7<n=p0Qyp+_=EO#zl=6J&<G$X%3NWyPR^
z5f|zRG7hX8q0=_VeN<-KO4+v8NU*rG9<JcN>rft>0H7!eeILDt1Djsx{FEM^9^Akd
z2PQwMAh0MKz~(C}BEq<&2WtVjAfgkg$-_EiV5~DT0a%qKc??zNtC8w3IR=`ph{<)O
z1uFydWkAjlExn3afr1<Yg~37_K}wS@{AwbyQ-DK|Fj#0Kti#E$3oJFUaA3LUTuy~T
z;}ACt%d!o-Ah;$L4lGw6;qlB0>J8;5mI`H&SR90btr`kVBDg9dJ4IMT2?K-8yCAkI
zG8cu2v5*>z%=@nls4B{UGN23$Ft8lZ%|$im-sUn!lkUS$x_T{skbxuP2KB0(Gy_<9
z53IkNdXlSq(_JLOU{^u-PKte;xl34w<inM<z*;!5eF~kkJz@B~PG}tBhGAK@VHX6~
z#KM8)>LWa!SwX#_{KQhBEE0=@Ft9yep-BW+MP#Q4izs1Wuz456Rz>Eb5HS`~W086P
zl>t>n8Bhk40cBt$2K-343cFJV+)lF(BtIL_%|&%6y<z#QGE)Y``n%dEmiuybZ;V5v
zFj#0K2;WIvZQHs5tV0dMmBCUJD&4{%w%~9=!uEutY+G}cp*oKPD-nvKwEm9!0FxPR
zL0MHcfVD`@#wCt%74<QB;DYk>xZsIi#|+6JHJ03lVN+1v1+hhWOxD55icxA*29$y6
zGthL)+<u$mz~VM{m~yz49VTDbvnn@E+atkZHF=nlt<0@eZ&=K)6}eH+IIw=Bns*tT
zt88H`!HQ*nQz>$FZ;V5vFj#0K$i)sJY8=c6Y7&v1q8uWH!9puQ*4q!rT$G#b2}jws
zQV|1{c~W2Aj)8|J5rk2cMWiq=CU52GM{rd{c8aiw5(WmFcR_4bWG)I3ofLY*s5`)j
zAPena@i0_nu(E2@umk?N?Fcds?86Z{ZG+r$Wxfq{+g>BVjx(dTkaxJ1wN$S@%78MU
z49t}QyH;Z(-P6Z`^=nbIkDyFtq{i}CEUueM5({;Ta)=ZL3vC3En>`0Jf|^8RrznR=
zVX)9fScj8g7g%ay;lOgy`JrxGJ2E{=W+g&V6ufO%lOT-5;vfucXO-a=K~>oR)*|^}
zWmQy99;^l1hls1B&>Kp3h!a5;+AUXxlxxV%HDb09G7jv6EmXdn6o*^cZu-@%%78M^
zGvLQzVkFpc*554@A8utW)vM2b7_j?+xr{OrY`@CCT+IQT7b_Es>uSN+4T*(1=^P@3
z!9p8B_)dx~`{7oU4PYG-4_8)%B%`B;rAKPP;e>?k3B&zRXdL{8VIv_07X+8Yk<r3|
z<${9tV;;|}ASkNBQlWAZi-Rz*JzwD`k_fJf$W9R!QNqAr^Dc<3ip)hJVz>&uvFlf6
z8!WzB6&z$PT!%X8Hjy_eCp)QXwOD098Bhk40cAiLPzFX~0Lx>sxNfRNtnMkwAyODD
zv=M~wq}Z|_ZdDQ4DZ(L27%a3A*5PE>1(upvIIvuF&h~_3Y+F&3#erAm!v4m?z)FOo
zDl8QUBe6IL1KU|;xJ6Kti0l+)5h)A|Ht&Mis>oavBCZmtvB<pl$^fXM3@8K2fHH7x
z7&xDCr*rOY#>1wqDFdT3AlBba70K1TF%FT!V4;m5d?%&b))HsnttJ)@kz9w9UOb+4
z+uE}+{4}j?tNyfgcoe6twcWdP+D&Nnml?pVMP;rGSTr^?>t-8%M9U%vD_b7XIa>nB
z329-@jYk}t%2N<5C0QS~R9Oiz*gj52Q84K|tSg3dp((*yL^IYInaEp}TxAGcDXev_
z{oFzhAX1g9v~U?3>pj5cD??F5S-vnZTofTYk(xZLVBMhzHnLC@C0AJpdXbJ#@Cx6y
z@hV<ah5m>&9G9s28G1bIBVq<-@HfbsK;X(XF{sZ`c-jCqg2>7Wc%5lER4|!jCsLD#
zO@!oK)~>7?m~lAG=y$9h2^JUcVagsV^W$_r5^VUP`8XXnpoWQAOaRruGxA{5K*%$+
zj1p6boXQ>GkgX~kz&a!sC0l5#LX(Jv6XS`_uhJWCG@c$Z$U(c!$_T27P2j3bh5<L3
zO0`gBKp6l7a)xN(C4GbtX9WbY$tM~-ED0n($H1*B>%!(Mt3r~4hf`_+xkzLuQj>>e
z*+f@9AT%6;Bg++o1pU!ad}gWoWue3n^~z5%Qcw{t8rOtPAQp)j*-+HP!GZBa=U3^?
zA_0SC*+f?k{w?C*#B#MnsgE+C3|w0V@HygKWzN0Lb<8H!7baVkc`-msxqhuaufDE%
zH&|9*+K%-*l{ztUbx$!3EBO4@u8v6_>%!(MYk~D}Vw(^;mz_vW9+qVjT?IgZ*2Kes
z<%$t()6<P~G!>p%s{Uf|@D~OLZ3L0y;$hx3Yyz=BV`M{769<Rbg2xGo7z?TK@GBEi
za6xcQ92_oJRtr+QGN2471IoZI8NgjxWnK)>oR7uBK4rO2usvfPN^f@0eJk7^84&C5
zDz+mJxw<DM+c>aQcLK?8?RE;AudE77rF%G~7WzA!>_lqvuq>M(GXMg#D7nf)kf6Vq
z3dVc%5M`0h(?c2@v=KyJ4jyJ?tI7tj9?3<?4%(V{D&4^;w%~C>BE~{$Jp6`XS+-#p
z1eYXRSt&?u%78L30|uIIncMGk99XygMz)mka4XwVgPLX=4D?IEZKS$Nj&WeIygf|G
zSGE>YcAPFpg2j^cFeOvjvGG)|SX?*tAXoPk*04*<Z|!ypo3E?|*29VMMCY;-sma5#
zY=X=H2+*2%IIvvZM(omd3?5CwQlTsokApBcXyY#J?r;aYhV`gnxH4F3;@}Wl@Hin6
zofLYr2)ODPBc>(}4woyd1!e5`=e8rrIIv5M#zD%qE6d!|cisCquy)sNt)2gHD_grI
z4O9k{0cGIYGGNE)d?eU$X7m<{GnI8}vFvZjC|CE0YFNSNw{|;)%~#d}>*2(BqI21a
z)Z}4VHnCL-fB>zDhXc#iZM-gRdf-tNOCBs$`?ghH4jyp3hD{(AXpC$qib5B^g9F|K
zY2fI!7z?TK<R+PN(6VfT%-{mIqU0(o2IY;<=S{n`j05X%5geo(Ze<5amlmZA%!mQZ
z3nR!luy%w_+aM3OvbOrwYaa~weSk=ekzo5(zN}|-O|deuxUQCqRlZ!^lag&5hF9=u
zhp=DRd}Y;cDb&M>6-?){6RF9=vTTCP00_{c<SGk6g8pKvXcT3U!NVvF4%!G(_=zOk
zsv@#egh!MxIA|lR$H}k@EH!a(V7cgAj76b0iv(94W5m?N!QoP6z)_hS1AcA|X+O$<
zGN2471ImChpbYGa0kQ0F0urlxL^Z77^IN-}!saV$f%R}=Jkh!AL~8P|ESn%R00Oio
z9u6#5Hwu?FJ@9A}mI`H&cpQYmK^u2ga<k`Q-Zg9ju|Q*FLs1h4huDJ035ggBsqyeD
z6H;(Na7`Q>E>+e{W-Ynel>ucy8BhkMz<|fJHdC2%Z!;Y-ZA%$A2nNLZyQwO<x~DL<
zabT<N1d`v{?G!d&SqrR(Q);1~M`R~blZR#51epO4pf&MuV7X$1pg$Ul&n%U0TQQ=C
zvTZGnn;Iv|fS+jHT6U2ESG1~e+6;J<&!);+Kkhbph}8h;EFy(rWhLPk{PW8_!ImmR
z$wm1xSyx)<bCL4WqNLc{@S=#dFI<XM!I-U#Y=ae-Gro6oU;rtkT%|`+hr=a4E{K9L
zFB`z-E6c-0%V!4)CYytubs{x+SjoD0Hz0pmGL?m(hjjG#16ugDjVJV|%USRE6uG`i
zk0nYXNg0^o8L}jh;L0>9D5NMIHh@haqOuZTXCrPz!DNx0NKGC#5t4UVyRv%Vu!kE~
z?^-(&EZ%a5Df_4l_oESH99TO-r&oj&6F@b7Ngjg}yqF(O$<x#0V%n9O7zDSXEXleq
zYy@#YU^5~VMY(gig?`GBok&d{R<Q0+#1<+Gd5}wGRt)r4-K=`jW|V;$Ga%=KmS!!S
z*u+8S4bz1~9GgH=5G*yZa99I2fw0)-)s`rjs&FWU8Kfo;D_P%OWhiWT4H7J+gDi`@
zS(C#pStJ!5AX}5H3!AU3304$LQ5KQRAT@bdvGVgs$2fzcDy#s&sVD==fHF{EfVP0M
zl{xn|+d<RDlz}lBuw#NN_O2M{b`^tLhAO0m2U}dzIa{6&uizcxhL`=Y)WpJJ4cL5T
zHN;>S1(Vjn!VFTAhn1|eu8_A$SOI{GBIu8X;<GG^+y#b34py(!#2~m<WnI_^;(@@(
zu0q0rwSZhC76)dKnmnvv-6P$0Dnlj}Wk4BF29yD1KpEH;19n@9u8;@62sc+bkly@U
z`PIJG`Xymn)mu=<R`+zymgmDOc!#**Wj`!M*#I_QSrHLNY^g-Sq;vG(2C2!z%8eQ$
z6M$98RTcsT{nd1j$wQV!O3}R~B_DjLi9v8J%44#w3mZW^5E$7|6s7&2FIeOeqa#ah
zbSYK^W3IAlpgJf6%D}W4z-?s&83`7*%)^w!t?V%Qx}H^G$uWYA1M5cUv<-60mH9T*
zZF`Lbi;cozN~W@Iu9EBTmL@Em*g~Do*~UTan><1s4#T?*SZZS7um)_tvKnHri-Jk(
zU||NS$-_$4Sy#y0B&>k$cGiuypuZ`dEQ`VfhDEN`de4O>1;Mo{Yr-ZF4+KVb6%r1s
zEreX8vzHBp-aLF6tYBTbAf_rql~sd=9Ucy=cdZ=>7XQfkFlEb?b?@@Mw>l22-+P~}
zfQMUIYX|D53@8K2z$_VPUPrHX?^jRu_j)AQac1-uS~HcAnwH0dTZU>@3lFxqrt^js
zyhGgZJ_weYSU9W!o3E^f80?~8(mGg}L2B}_l6BS<@-_)80C4@rYmI-~>M2&1MM{BT
zNy$e+YGM#vi{i<;E^Gur4u17PQ53u<hA6j)Vg{+n!y>DrM}ad~i;}CX7?d|Y$eVU)
z84330E_>Q2_u*EyQCk|U3@8IN25?UwLB@ggBXrsZdAOCe)vsQAVF2s95o8=#J3^;z
zkj2Udw+zL+j;tXiTiuhgVV8#3%$gpSk~lJ2IIIDiuM7!`f>5zfA)P}MGe}JyR<h2z
zYPy1Rl?8^x1`6d?MV3V&tjWQa&Mh*F4v?)$)`Tro)&wgGrYMWZRl~W^6krAG9_bio
zP*i2LfB=Uiz8a<ulVhOioj$p)v|wdG8Bhk40cAiLPzJWl04<LPw+vMn3lFxqrgOGD
zA6~&b#0~F*V5y0P!y2&p%4&$gE(#{CgM}HSCJ!rFXI&w0ldu8+7xy=U{-$)YED94C
z7P(lxQWJyVT9tKSBZvnABfAO-2i5{|kysp<L2B}_f_0B{Td52jsVD==fHI&ATptE*
z&A8P$_cr5U)7F%Mu^AZLGE|GQ@L;QZI%muC;T60?-0-p=mYP^NtO1*^tcDouqF~ZG
zSeQX-^01P1))n$L2`d0_Q3U<bP<)nUk-NaK$ieEBnivGvs;mneK|Bx`*;Pn5uojSu
z#NxmVQj>=jtb3%}PGu(KLOzxGFmPnte45ctA_KUCsLYiCF#%K?{Wy8BX#g_?iN`@0
z9JD>iE&1<#Jj@8H%KEUS%4)EWsB{M>#uJ@io*qlRStMW+G0Qg08DdJ3t&D;k0vQGr
zMOnTuKodpC^^9nw&{`1^#tmTel~qyA=N4iBL(o-v8y+^sx^P*)GDI#>-ZS)gNDtri
zCCAI&@kNSwLJ!k_FGb4046l+y0tv26lY)?_D9iO>6Nsp+h!~9Y$Hhd!FraB>keWPf
zA|&q;z>9}mWyPR^5m&+pG7jwN2%WY;?xV7PdTlFcdtT$f`t3EagG>%NG3FjG(%l^=
zMWI`@g#+F`Y2iSxQwC;WQ-~usK9#2+Sc<X%YyuIL6%k=PqX%mNxkwxi%pf&+Sjqaf
zDq9$f%2ejXK!4TEt10b98JI5v4y~~nqNP_4CpK}=dCPPmCXf__j5YCaSOYeJu-N9+
zR$4wpo=}G9L~8P|4jE!LkCQD{hIAGORw5KNad2Q|(Yff}!;94`H7N+bHF0oQ12%!M
zSX9;|tOevE@i;Jp)Z}3;q8aPks|=}ClmTTx85m;VY)Cm1-JE-y$q-Gu4Lj}fwfX@D
ze77SRu&8Rn47gBxII_icOG_S3Y;{lP4ZF0$njRTz;^D9cY`(G@Vz7&S3bbN(A~ktf
zhYXB$)>XfUf>T)rD?^CIft3hFO&lCpS#&NiJiJ)FQj>z<TN4L|HDD76i$!Hk!dgHs
z5|0BjNKGErBAT(jy~>bUMHx^AlmTU6EC%dYz>2#w2K)&78~T;1*~+2xhP9W<JQ;9k
zi!H9JebTDl!-=i#>AYc=R#?*`V^KDM%~w`LgwfGM>{DP6yA!F&!y+qZosrq^q2QDk
zN2bBb5Mps)B|=dWPZxoM!{v)XV0d`3dZi`>!M7xvz$Oq@GAgUeJ@Q~JAQy?pff=MG
z4{H(4Sl?b{NUfp_C<8NQz>U+}NU%+J>QNXu+{#9wLqP`_!1`_k83`8an!}WAW$Q78
zHQNX>4y+xa(>BOVWiIS`=qPt8&=tkQ%2xMu-mpt6tm%=lCLRuJz~(EfAqKnHr$8%q
zCsLD#b;uyLG#1*J7q6=_P?-%u;TTi7plUb-M^+XE2@H=+tE1rGysWthf~6)74p)c0
z0AaDsOODkRLN2Ppqm)%csW$;@5zSZ^F7T+zY5}pbYS6I566Ne)MuNpZaz0Gia%Fa$
zE=PjJyXY|Ga4S1ZzO*W3Kp9X5_QL>{u2+|l?&;&e+N<-kr-*!Iv^;hw0*s|S78Et{
zaA1pTI!_sxf$e$<YkFj?iH8HrPUj7<c^4$C3TpwmAYykSHF;Qv42*TwRrA|zpt6wK
zSOBmRp(qNK<KV!`qH}@a;l=8eniK@zqHF-0Kv>DBtSXi~SPRHS;&EUGsma4yL^Ia6
zR~b^TAr9s2Uq*s`e*c{|A|7sKjSZ-qGN25s$ADcgY}2TbU@_+%rW|f%hsoFVtg2rM
z?z{PMVEw+^Y{n~A=8%RhuAwLjErdNB*y^6n8+K`hH9ayGWdqoJWkp075i0g6Fo@lW
z)Z}3uGBDN|nN3%4wlWNi1pq4%ikdh$u(Ie}bnoG{T5stmlJKpGgTvKf3zgLngMGDy
zkc+e)mQ_QkH&*g$&<-l2(FUB#yclSDr_ZZp?M4|;29yD1Kp9X5l!2==Kuc|hD7OA?
zN#o(f7V31~uuJ1RslCDGD?=Yu5gRu|usvbeQ3y>Q)*%CHpOM+Tm>sMPi7fzFK~U7h
z!GV=U=K{mSi`6SNDG0tbad21zHi58MRMsS{1>_>}I530M<Y6tM8S7iCETl$y6=gsf
zPzIENYr(+X8FxA7-ex>(+L|&jHUka?u*G#tMIKIUbx-FFyR^cZ9vN%m;jjj5zOou(
zu#0^Pv|@K6HF;Qv42*TwRlkRVQ&|QpLx{zJl?X*m92{6#bS^MFyjZ<blY-z|69<Pi
zU=s+7MP*IGT0kxmj{`GEO&-=Fnz6pU$~uMspfVo@=vu<{qB1WAn(smLYWtdWBPM`q
z-(MyVxf&p)m>(>1txO?z&1KC+5L}D0KI{dE2LhWBi;!e=x9PCbLYlcOB3BHh-aLF6
ztYBTbAf_bQ$`G_tSgN>`jBKABpo!EDVdar6w1(iatPksuc(}4MBw63PIdCbGUJR1d
zI3yp26|4`wO%R`#TxB8RDLTGNk0p?v398zG{)jakAJW6qYtw%(MasYoPsqVUkl@NR
zDF|+5Ssylm$jZu)WIZ$H37ldJAs3ya=_m9^2B|5)vTTCPkQcd&lB=v3R50Q~9YMx{
zbt81z2Dy*QY+EVY_8JKmch<ud+;<(yV-o-rMWOGb_i$j-3!R_R!_$Ks*y6zCClv%1
zWdqoJWkp07m-JvQAQwb*A~ktfhYXB$MkWBOvLuh8%6v6a9VW*>(-kqfuC!ofV7?5<
z8KR|EF)L7zL!dBNXd_5z(uH45M0N^r2oeShZG?3=8FqoCCKe7X7oE$gP-q<DhGAK@
zVHX6~#KM8)>LWa!SwX#_{KQhBEE0=@FtAlap-BW+MP#Q4izs1Wuz456Rz>Eb5HS`~
zW086Pl>t>n8Bhk4fdK}V1G>4W=G@y{#%R)g_(@l<#Sb!YWZa-$m6K)wEAN5zcT-Pt
zb#J<hL>TNU2;WJuk27}(>yUi7vKCkiC$>+abG9c8pVtYEL)<Vd%QozS;F?%Cuv~qF
z$1^LaH<X`PDwIWHaS#T!=PNXc;Hrr16k!o13=B5!g4n9aTofY4LTW5B@4qsjswe}>
zfHI&AjKqK+30Glv%7EKx_JQPQ1G>4W4y89Ne^qA6fLMQ5`^0izuI`O-h!h43Z3N*v
zsjF>UH-L4hVYo6_ibADZIK&nlPDt3EaFlIpt};~TabP7vQIyu-aUWnZ!!0PQ$_B6&
z$=SHXF|MLMCJ$Uto*oxG(d(EY8KlON+c0bj%DW)8D38fHSXnVjjmm&BFntD^ZkgL}
za~xRQ<_=R1x3a_J>v~q@#%X&bSga-wQ?ix0wdxIv`L!Z93K|F2Z&dRxgL9QFj3rpH
z>~AVXuI`O-h!h43Z3Ma4Aw-RX89_}VvQv~pq%c@$1;~2)0hx<(vpwM`+g2)KpfXSD
z%iA&V&?JH|in53l2FB#AJpBl+ipWk87E!{$VDm1Bt%}S=A)=E)Zy0q47!hQl9V{M(
zsti_EjT&~qKeru0#({k}LZ@wzTdvHvp>Er2B-n9g^cM0Cx3ZS%)khgn29$xhGGNzg
zY@~boIIw;#iuMtduMEp$vAAw3Ni5VU${|u1EVL0sZuT6^2x=0MouV8fg~37_VI59}
zU0|t+g#*h)=ZCs&4TTzyl39sR6a{Y^)+7icu{a0=+gW9}MNm~XfVD_ISXmX-lLu?T
z_95abDfEWY9pXfgg?7u8A>|r!bB&lSgp33GU<;M+CdJ`awwr!6t1_Sr^bGiMm>3Cm
zob`7L#fMv2OZDor9|r7xU@oJK1lzCjFIRH_=f%pz;<{Qec0*#JPCAE3VX)9f5WbUQ
z%YL{OWdm4;#KV;pA<5|IVd;@ta5y1hd%|!(6dDJ=Vc1AW!3Du3ab&b`V7Z{6{g}ry
zD+r3JuvDm=#Nr?fY|mHti6nxnBC=D2MU*fw*t`p3t0Hqzh#0OyZ|wS&*#?WRRs{!{
z3)i7ex=rLw%E?ZuS}j%?PzIC%Wk4BF29$x37{KyaEUues5vzNOa)=ZL3vC49J1Ms8
zhg(%dc8YL_5(W!xgmpL>c7dfP77i>IowGgR7~579WpTJ%8TL0G238^zRbi<>7>UI}
z7}(A#!!3fEL}aHZi%4N$uz456Rz>Eb5OI}AjYZ~tSLOk#q6{bl%78L(Z5TM8ai??c
zZN|f<ttkVeGa%OAO%=)2y)h1v!eF6|AbcmK+tw0i;H@SW4v}1klU_WYb=%srG5j>C
zZ7a19J{uWsMYR)Uz;^G_iB_*=XBfb(MP;rGSTr^?>t-8%M9U%vD_b7XIa>nB329-@
z2R?yLLC9E=^<hhul@NpN<8)+ekACLzu&x-2y)mX%f_75brNUb0+RrWI03sE;HijD+
z8tXm4<|{+pMOnTua4AxR>_lqvuni+ytO~|lWg+lIIzGWGeA~vWcu^JlBi3+SqUvYp
z@vx7G8JNM}AZr4FE7!!JK1bnc1K0>6D=Xl2rsYt<WRjgoO&&H8l6P6VvT9();WVS)
zv3ev}T)c-Vd#KEh)A>lShrKbx9bV3e)d4yq4>5I;&LL75EVOZ!SzTjXS}wq?C>y{!
zBp$A;2ni!iA{NiF1&0$7F+EC+gWoVL%QozS;G*OzLpqgtF<|G_j&`FA%$@-`L$tJ<
zK0=7I0)iT*3oK?meD@2RuMD-+#KVCVOy{x_sma5#Y=X=H2+*2%IIvtXB92S)h=$@b
zOO^T5<<g1>UCU1~JhaHxBx}NYBp0y`+7@weVm#5g7z?TKh#Q7w*@j&ZToVTema7(_
zc4a^rxYi8dbHusIoO_$=m`$oLOtvcXVt|%%Sb(d{ivcXF2iD(BP0H0hg*EKb@>{!|
z!saV$f%R}=n-Dseok&d{mSq!U20(z;#KVE*iV<wn(~WdA6`oltlttok5C#Wr1SxFo
z;8qopogzG<guy`@VLeWUU0|t+g9FP&=VC0R#v^VRmSr1uL2ykR99XVegxZw>Wk4BF
z26oH<?#e2&V_@I=o8{~nylCi9dJ8{LxhP9t&4~fAxUM$m$V0B~N!hSV%Wv&=3Y)L2
z3QPQWI5D2+Ty`Qgd03WBkQo30T9jO6A&6~yfL4`z<RQu;okyfFIA|k?yc|5tyM|35
z7HEuYC`#g~bO(png2xGo7z?TK@GBEia6xcMvXzyB)TRt512bTt>6W?uKF5J|+izq`
z84tIzEj6fVw!r|F93#j$u!p+~%vZJ+Q+9+QCCHIru>d|y$y9c1Jk=}K-%UNp)jfsb
zA`u3Ud<i7KwS!w#M0P|pz~)`5kmTUulv+S864{B=<Y8Gh(UlJf4Ts>!a&;TAOWQGc
zGzm+EvPe7*!r-8dd%nBF9qby`qlV$iV5y0NLu|q0ghX^w=*=SFs$-0pnm9OIuB;Z6
zvE!fHjv(W}F8ep<2n|;tw_RE0o?fY9WAiw$cH_EtmEdqI+f~P!R~b+Sl!5s&V8>}~
zB-n9g^cISXm5F74OGdf6M^wWKKEJiwDQv#77FZ7_#uJ^(PNXIe%d&~BQUC;KO*|Y}
zuI}{GrUxEXvE;#0wQpPH<=_FgYuE&0fyT&&qA2v9aB#qTBMltA7Gohbp4=o;4qBE?
zkQrRyR+L<2#h|?L`MhbDmT_PmE`o!U!>#Nf>C&Q<ff+G?d0_+@2iA_zX&dC>R@PR(
zdhLS&zYh?JF%oRQ%9r(wt|?X~7T48svC5aLds4EE!|)0|?GW}0o3E_eErohGv4ZJb
zb|N)-Se8wY82|xVlw4&YNYGzQ6^)`SGI$t;!9g2A3O|vATUA7MitvaM1_y0~^*9-J
zfu$x64lEa)i?Jy5W|82kV~m)ZI5=FY3^*!tW5Ca?A?-&QPzIC%Wk4BF29$waF(8)x
zO+aFGkEn(fe12=UQ`mfEEwCO=j3+vmok&d{mSq!U20(z;#KVE*iV<wn1CJ(QsZbV)
z$3Ykzv=KyZ_B_nHhD{(AXpC$qYU1D!Tktp`5n~}W9)4v)3N8q)iG#zX%5bWp3@8K2
zfHH7x81R_ZW-4>;ZKgw}Z7Bl>!GKtQH&rE9_Y}r94s6w(K=NC=ox<iTYk~D}N-gyB
zi0nja@~|wMATt00v?d-7ELV&W^hZPSnWfTgD@OECwyni+Q{zM#@Dr_D%PunDidHpF
zn*opV*;HBU$K56mu^J$qMWisStR(z`e}1_q*ivOExhP*I>q-lKE>d1vloWd#UKFwR
zg-fw27_*g;ZLs2U#`kUx3?PM+tMo|faJa<B1yL~OWdqoJWqG)0`RqW!WOJ~yPNXIe
zD_Ixs2IMbGrm_(9kd7XIKnvft@q`|AIqMytBG*^xu|!EEDFZV+LzV;*T$v^Xg%qX3
z2CxZ4R8|7)Y{ZQym@Kjrsma48Lh>$aS5^-k_He`MU28{z#ar$$WgnH{el&uN18Ya<
z^oo#T0;t9>$zyPW7xTj@d3t(WOuJGOgWy(_C0W;njUWyPY(|8lD0eQm&`&wC6RF9=
z3f3Kp*iL1|cGNgY2K*$e)}obx>&t+g4_dgeaAFe&oi|Ju4smP(NkOpG#KK_>*aX62
zn^#++V5-8Q6lRc`Jgj7WdzGQE;WbFGln$~i@@7pAw`7r2bbxG4vMy}CvL;wjFhyBJ
zGK19QVa3YNBOT)mimI>z0H>l1C<DqsfdSeA&Q|8!+iV9-8&d|xWWbIIuGqU`pxadp
zZW*eO79MPIP3LTRKD>f=h#Ow^!%`Cqhc#gHmDLb~T@*}O2MaSuO&(UV&bmV0CSe5t
zE{dQ(8j8=dEOHkZ7CBhGQWJyVT9tKSBZvnABfAO-2i5{|kysp<L2B}_f_0B{+o=qh
zRFnZ_Kp9X5lmTU6$_(Ha;pQrH?rpAPHnqM6w+!VbXjO0F!B+Ql&X(uHD|m;v;blK8
zMcDv0Us(|mM(`sFCY_@PH%Lt$R<h2>1YlKim4!e-e>L4>@{nbbQgm-g$p>F*Vh~)5
z@|dja!bT7e1V%O#MQQ)%3l@3A=*W^AU5Zt~n5(QBs1C}2GB9lha9bHcMuNpH^DyOb
zD?3cSu4h$Pa*QD3z`7ASZG+r$Wxfq{+g>BVVxw@FlBukltK|B-r3niswos>Yws8>q
zCXWz@!|-kcmYP^NtO1*^tcDouqF~ZGSeQX-^01P1))n$L2`iwxopqxv=x<6V%c3xW
zVUcUK-gBWzL2#|gny?AP1A&oUg@nUu3n3Tj>}5ltHxFM1D_EB<h^fj@W!0czhlj)J
zU28{z#XoXBOxbc}-Mf76t&Rih_ugkK;Ne!*+JX8h1ImChFiQsTBY-Q5zjDM@0!D%z
zXGU*fEL$0v8r(8ev;P0=ojsBqN3yL8GnX8*v1>F4V`CI3gh*--DaP9Y^--_@3Rpti
z9n2CS%mQW!wG=Gn`IlXpC~uFy&dRFD%62!a>`wnX$4^#QL^J^~kfAo$a^JCokJRPQ
zK}1>>NLT?|X4XQS;)bwzBM}v_o-(XeT}?&bE>i@6dwHO1{%&i!)bjQFqm=IrMj%7+
zwVt_%)T$+kS~bKucOc<A9|c=Zp{8p5OqgEc3sk9q^^{@h8s$|XPqb<!X4Rr{@Q-rn
zo{>SYKiqSsn|kk;*-c}4u`A#Tv=k`rz*>d3#mB&=+eqKBdcVx>IJCEZs{-ur2G|(b
zFksR?$SSk!k)hf*N_1+ecK71!IHgfr*wYiKS(IQPVFhfN84asOsX3>JFH)rf)>DSH
zs;jBG-oYhilS1YI1>L4uT2i8h%#QRq(Ai8tw=P==TVd7(YY0nKpz=EK*?20jM)gEH
zr5TQ<T@#q#Xp)*`p73-Ebp511-BeE46>tSy0aw5ka0Og}jTMmp1du&4G+_c6YI803
zYI~mF!AI)y=O7|23nZ+7Ei-E&PH{t6ypf0sSWg+&s;;J@Z<i?oz+q8dMt%ZKv$Ukd
zU<CRozSc7rk=nGiuro*kL5bajBteZpFR{Qy1+1qGYgA9P+k_dd-CO}zz!h)>-j4!5
z9(dFv&vxL)=A*d+qZP;=8JeU58ESVg_iB5d-@!-f^4oqQEej;9fGsm?Ax?2aSiF&l
z3Rq7W)~c?iqHmWe0>I5?<evl8ua=gi8;n2?#n*b~B2t^S7Ip?nASkh$kR+%P=p`1o
zsDSm9VU6mEcH1yJO}*&nb{qx%a*D?p#wVE-;1k5{s0x?`pgHJolA)G?%WokQl_n7J
zUO;}dzkyDKDQen!*q7BN&#VReZ=oJZQaZ`~>*cXFTcCkjh*h_ZnF&?|P+{Px+WDUu
znWVz*XUrg#(W;OHZ-6Z`Yoeb1{9qp7RP>hF@{diaZc^4Wqw);BpXBvLUa9LJIX+(!
zf02rB@;Y7qU5cfH3j8h!3&@nJJWCOcs&-xvyMP#GRm3SM|8p@zm;ghofc2DN7eUG?
z6L|GfVpc7x1bHV6uraV72Ta-r`3Pp0<+YE{c3ER!({=;gp;P4j&ofUnUq0QrshWIL
z2NEb>HV*Rr(m@5(5)vg%FXc-Sk*eJQyMP#GRYZcH<fTTSmssSY0@hQ8wW@E&>=8f3
z4Da?p1$d{qxdN`h(<l&Os#b^|>WL(^aL9ena$y#brHGC#OC+p-T|iWA_ik(1KFm5n
z!%Sj5W!OlExm)69LuRxKTogqdEsG>5T5@luPh=^+*0U6m+p<W)3fKii)xxaH)Clwv
zOI%dIddjeYYNh&i%xLZA3b+EUKu&>AIp;xqN1p8<kLbC_2+vL5*=H0;FDH^r#9dFU
zK%BTwSGBqB87YyZcK34MaZ0P~>FL<AM8XQ#GP4%q6gTG-yykRbJ!RNP2c^22>T-r6
zscu<jlmsq{B94|t5)>`DHyDX5#n*b4B63?6Nmv29fT&uSb(tE0USf%h3Rq7WHc+ip
z-;Nor-CO}zz!h)>Mk(-h6tLsoQ-RCse@_VATmDGZVQnw7u@Q4SrUH?%)aJT5r|jwz
zNosd5_Z_FS%ATH%Rl5PU%&dw?Fv`oEQwW&TiS?9W>8e#%Vs?Fs(j&`^-hqpvh@)mn
z-UN|^*KY=ck;qbft!F7Bw`RA%E+C3B%$oMAWT+A7C6>6Tfc2DN1Jz3P?U>Qp%@uG3
z4y-^NGut58u21SAitLx!5IGz)s{s4E0X7Jhea$|t$ZVZb?AZp`7}zji(mu!nvpAi4
z<Z4eU_^OtOs@=WZcbw8HdwM#yERnDRw#=-BIK|C51+O`sSWg)?(!m^Q0^YeV-#0D8
zEKEhyb#4_WSI1>aRJ5eXU?e(SKZW#vuRY(3h_oz{@OIemAgZ=|%W*xz)Js?-s9XnX
zvl-YxwNl-rkkPbj0yDE_Q9j`eoyXfCSpJgpK5b)WVa$|+VEHN9r|p;7KJ{`|u7E4x
z3hY^dL7(YkV8d>oM3q^DHi|80EF3LMB&f}`+%FweK%IIjdwM#yERmqP%Y6rIIfaHz
zQzOs|Gp7^lDZ@rODAm<e0Cri1S)2+3S4DAh*DgXQ5?8e3-e4rM6kqFEipZ_n4X_J{
zq71X91<6n&&`T_FQ32~I!v?CA>f14+^$Lq)j;(`W|FJ@$$CT`s*<<E+6j$KgDiFp@
zJ_wdIZ=bebX8Y9ZeX_c21s^^97})gaF}v}q%pz^n<{C%UWFwqNP`i7%?>MDZ_VjeD
z+6}N}W>rLjl$vu20dqRBo-%BtgHm0I+4T-CGNX6kqA22MStLQxl6y0KBI}xO?Y~Hp
z+p<W)+hHrrT8LBpdW5N$coUK9Ky5Zf`MT&1%y`;vhf|>IC;f0!`#`RME8q&a0<M57
z;0nB5fk=tkfA{oAB&m(M+;^PP^hxSruw`b<(KK^#qe7htnZ$a^u#tQ<z7n&0Gn-{b
z@4!V-#L==yf}$n&1|yNB_*&0WL~hF>2`gY15LFAaE>k1WODu6w0qZHl2C9|nn=zYO
z)85S$a0OfeSKwVJ@biJEJo0P@er!IPD==Dt2m!UZ?qQTjQoDP(?>MDZ_VjdYSt4Nt
zY?)aLaf+LB3SM(Mv7Rz)q=QmjO?5d#kyN)VGfDy%MG;5KA_<C?+#8HUmf~wYOA)y(
zizKXoT|iVV%(_gCKrgYxMFp&<3>&Ccs&B`P)^0~r;PSRR+F0*>p6<_}_b${^&Tkfg
z<`n;t47(c;r&%8Yy{?v!pEFDOTtsTs*2C7ARUsu9|1OuS5ng(UFUadUP@650s}^FT
zx=o>`W<_Qc<rvqRN$g)4nZz9_n;%l*#tdRTkvxjpwjMUpJkP8N``;hT1DtB!GMoJw
zFsj>>)y$^CzsdD?d7VM}X>zqL@;|XA@r%5Ye1E$9yA(?Y75F9zrx|2QRi34Yw7RW_
zT|g|eI;2EDolf6Knn##=$vs1Vlh+cko(in$X2hKO(z|LUX4RrfkT>c88v`2$Oxg$e
z2xg&=%GOzfVEa~$t%rR}zeuuLcbe7m@6jic)bb+tALW(gr2}ena4Ih<6jtp9*fO&!
zBEhq~)Cly#%p}%RhK+Pksw*)8Y}#2evdo&5p73-EbiE^<ZYn423LIAfyF&ELYE}g)
ziWHhaz&nG~7G3gMX1Ys3q{svU-WfJ>lTRVivOt3BCHHnIG@eLZ9#(bBr%>FoK!WOZ
zsYrZPgf4;l7u5<{Vu6bZs9i&4NQ#?gx=Tf%$^;Z_IfdG$*<Mm&o`v-UIzOHnsBW%+
zE8q%b6gX#mM{yl_wxc{FpTiZ{mjajl>%K@in_CrN=bhPqceS;<`_m~>X#xT7yvf%m
zDfR12(wb(vOGTv01Ona}Hgc0sA=0uyg6bvr>P$HOzRq|eb$M9TEuTVh%K{0i*QFxy
zRS~)b>R(hVXo&?bCZNuIl_4o^n&~bTfhrSFu;mnLn`V1SiFp>*6X^VSW}v#c0<M57
z;0m|`uD}y3@ac)Ux2W%BHnzWR2UWoAzngQi-M72@(<xGE0s-#~qEAw9JGR~c8{v>=
zMx<&&J&-Vu5V;XkXTl-J))F(=B`%60j;i(k8TX8m1#OY6X*a+InycqBKjS9qSIOWF
zmE`qZC;5Kvumr3pNLn6tDJrK>TeYte%`&T2dC(Pb1)g7lu8+*^#~cI8$J{<`zs&Zj
z*ZX7@$BaD)mfhq&ZDVHBX8!S$j)6^&AG8y(#O!6QGTZ*Hu6B2SIz=i?AmE)rzMl|g
zPb5rHmznNT6{$3VfY*SmI}g}i(p#Mgha6jlM21-s_v_;rI&_&4OsWEvCZLr3u`EBu
zO*7r4B2Z-l3bvd=ZPRQoDKV2&X5*<xU`$cKn<Y=6X<25?s(b=}-FASDf&DUI(mu$I
znWa9|t+NKfj#<%r#M>{k9`>H&3b+EUz)=+ls|FkNnLY+Kt&->wMP+7ekM-snPmh_6
zx)enUO(5W%LF{2K5~irjOn0e@RGL7*JHtk9@+m}G7D!ON<bJQm)`{pTL0M76Q8j*S
z)Q|`!7Py!IZ<Is?kb<@pHSGr2K=UlKCTfxlHA1+Qn0HBKHmFDHOi{qQF*91Oupd^`
zY)~==_Kyvi->1cXncZhz@9GM;0v83+7$pY5j@f_rNW5QWJ?uT_F$#poz`RBo1bf-#
zzh<+8`zkZDxo#5Xpkg-a;)_(8K)^eL=#!M%_LEk%8(<@i^USJ{5{&W+@>)iS+=xLZ
z@J+{T_JA}OMLKNEjPqEcucC;fX@-_m1gcCxja2zBk`y=1beD=il?f==atgIgv%RFm
zJd4U~>iuiGWyv>LkzjlAKJ-PmOT4E_3Qxt>$+`lrfGgk%xB{+#D=<g_w#R03-NnW1
z?xiYHX#xT745Cj`YTHj*(@b}%h*X(Cz&pc6Zt^KaS{6u9z2sh<38xc<@kHwKu&P@=
zh2oY45>zi7!Y1)m5yH_l)e2f-fr|;KlT~F%ikoJ-OGTi{1QcvJh1#asUQ%M7h4lnF
zKblzr)Xf!e1zZ7F;N2+j`M{GNdA0*THXqFu7_NZXe|IsmyZh5AQfUGK?+l_(Qhsc$
zX@+hs3na|qMs6;a`0B^jiyHYaPjzgS5vJdb<VSJulPVBieoCK|z0)ozz(<SQQ56Ub
zmRog;1OHpLMUkl59?8Ah0@(%W!|8M8H_%HF9c#88w#KZ6IK_UGtJ-^9R<1<!Do~wG
zDRotJ7iO=B^{%yley|UaR_eWxA0+pz9{^is2Jfn!|CxC!N`;-oddjdJPqxa6V2RmO
z_={Y>@g4u##_xR7H2I%clX!;pPxAV5shB&cK>Djh7Z6glXD+(*sC>Brb_TJ`DtIrU
zbB?ft>?GDxhFt_Hr>thyEG#5^Ecoy29t6vqcc1nEW@*gigJAc4Fys^7u87SC^hq+z
z(kZ@3r3nPQ^D1+_$9T0}AgyXQz(yM9nN=YP$|4f@I*$;!5i`r9^+fXWu&P@=h2pA}
zn9<JdSPFz=jpNg}0*6<?t`I#VFTX;VR|SeXmJ2qsiQLD+mYKn&Wr+kuSnlm4)>DR6
z-HezMAfPQvB&c3<#r#~Bj5$#Ks#+C(>+)(x#MJh;7zr=kx@;wEqPeM!czZ08q;!&d
z^DL|<QJ05R-SR0Ew=9yNdbKJ%?h3d9?^*$Vk9br&@@z+aW=}O2i>=$S6p*bP8*sN{
zDZsWmv;XcI((dl1tmBkcKHA+Cw#=*tHj$(bA#!ggv7R!l>Sn~800C`TB0=?<E7YOq
z<w?(>%2(A2T4ITd2}HazNabipTGLE-sYq0rK*T%4CT{X6L|PU}P`%{dJPYed)a7AS
zw|ol4EsG?mUabm`y8^C&E8q&;Sphzk-43U~qt7?z!zuWEpuNmC{RfrrwEVjxDPT6&
z&EcYC*xkK2J5FikqupI$%gmavqE8}8=_L1d66-0$s%}Qi2@ue#m6%OM>d*sP(|(l<
zLrZ*#N)w29XAt{#NQCbVyMP4Hl-M|GmV|mFVICoIBW9k3^(6A@f>cr{u33>;t;l1p
zfGcnS1-d>mx1VziY}|g3jXLg^*+v6;n=KSz%Q3*l!0z`HSZ20LsW9M?3gjSIHo*I|
z0<-@)CE;uK-(54<-My6YCNY6TzXhaxv?Hx)raKiKu;r8{q$DJgmJ#SBW+$<pGOX%m
zrb-h+$7M=Xy<QGtua0A6beU=eEwRMK1R~z~%=dGCf_uXzIOLfTX;~y;9wBifW+ti3
z7ASb@Gp43xk%ZUGT1AC8f8BO~je$L1emDmV+<@GgS>ZFi!Q$rd7}#(#?|U`aFSC11
z?0sDUSHKl`1_jb8l3`WV%|(M?$E@f*Y89CM<rJmbZ2NmU+TA@>9Xt5)(eAFWWoA9F
zi6o_y+}la4rwpsQnWNGK2x!X^398r2!Rytbhm58L$xyBOkFECYkbt{4>;e)%Q)1(&
zn*2;e68PCz9-Mq{o`v-!NwZ2tysDcKb4nqtY9(gXqH^#b<<LDNV_+k1f?e8vne9?8
zC*=wpNCDP`0X7CU44AYJa=*;__<PnP6iAN%u^5A3FS~rpXSk=z%xtckblK(G-Mu)~
z!6CncUrq>*g)K8{PAjE}Bt=;6?IhMyhE?5+m=hqNRVy(&MJY4#S6j_NLrVgQpb130
zGf3sXNRrkx(_JbORVEPe&ajD_d<v14MG{mmxi`<EGFza*Tc0sCEsG?)V)o$_@VXsJ
zfpn;8d>B{26>tSy0aw5ka0Tw9K$N~_+uwy{cK1|u?BL5sySu`cnf1UXl9WzzZzr*y
zGOX%m#GC*DZCN5g_2MZ6ajHWP8C|AYK}#%gF@cD82C;{|MEKsY3rGM>iH)OWk%W1K
z#EqDF7S@x<s|!*|p}1v{gjdYE#cVbAxGUfaxB{-gGboT))(&b%p6#HI%*S#CcA<dT
ze|NF6yL%~92M4w5UO>u6ySu`cnf1UXl9mxJ>xiAiddje>n-OyY1hi#|1l4P<F!IlV
z>Q~jukF7k>y&PLlr%-)#9(+ax(#!9^o{_q9E-MhrA&)%00*MLKQrQ|Q{#`Q6Za{p2
zN)x!+Nu&?@_m>ZXtucdg)&3*Vs}U}}#QADdQk^ZoDN^H`lqxHNMP?GqGOl<0?+=*=
zC?$24iKdauD?PpoMX+o)z?PYn;pWJ{GK3`-iK|JhrwnUVH$M&ZuUmoHRP;rziT{BX
z|JuekdA04+CGl^P`n$Z&P!d}@sK8GWSwN;#<ynfR7PZR_unUM`Rs(#Ai8h9?MC>Hi
zQ-)mxDW|Mv)-KFv#Jv07-a)YZ$nDb}!HmzN0X7CU44AYZ@*}Bc0ch5rB_q4QoAm*J
zB(Luv)-xB8R<*N4*TT*q5d^g&;;7pHz8>MS<k(59rwnUUkC51ane;&<w}UBgdDk6m
zDj&xcIIIG8J?I%Vkfat4x$jsmB6Vs3S&E3XERe7Qb^%ef-McMASXe};sDSm9VXf-h
zF@sos4>Cn+7fVaB)sXp-0!_^XbnCLUuw`alu!gWy1u9j*ddje7=a*=wG{ey}MF2QA
zSHKl;1u6>25%92f<k=4U(4J{9|82xGJ*_^j;brI5m+V>3qQJ|kB70<Lju6ODn`^mO
z+w=SmK2n$8_7iDYAYlb;nOO^QiW|b>jYL$yddjd?bu|@zyG#)PZZ;$T9H@S^v?SeN
z1bQgG)-xB8+O)N>Ge`nKiQR-GL5)B!vA{(ItfvfXR8O?qh8dmQTme_W6>tScDd6Xu
zQOe&BHw-x6@CV_JYCD-N9aUeSYt<hTmR)^7I<>o(d$m2!@8BbK`E5Uus@(uvW>!Tc
z$dSqr7GIQ?4p>ha)*jT9m;g4d#B3@w@;BRkl?+QuoM!qUPW|w$XD%YOYF{O~7Ip?n
zASkhMRIUH7F9iCSr(-F1rc_xGEHP^qdV(w93Ou(0e5?$xL9l#e?$h?mY@d3)PgZO>
z2G|(bIAGE~$TG84N~J#3t+NKf?)Ud_1!l5V$-dw2zk8lXAW3c1<z5{e%(*F161n70
z8$?<bNLT?|X4XQS;)bwzBM}v_o-(XeT}?&bE>i?ven?-QwvoT9ouwsZ1|!hxn(t@h
zS&B$)+Dh03B!QsBZbFi9J;KyWeBpJVGFu{7!5Y<V3N=m3F>4m(6Tal#_x28g<u5t!
z(>7-I@>BlsQOCfhhtJsyxL;<y6L_90;0m|`hg6_@AALQ2y1seb_k&=^tmr+mmYK=+
zID2Ghb`4~x&9&Tj?BFAH`EwAFmIV@4z?PY{5U02yEZ#^&1+1qGYgJcM(YMPK0pMO9
z=$gOVnl80`{r)KBdxH_kP<*XtE+VyRNupK_an2n`_|8YcmQ$#y8b1@Jm-qrzDquZj
zSh_}eRmc;qT8UY;s2u#G9J*&@5bO{4oav_C`(<|1SYGT3xB@K&$~&-D<xTN1u<0hw
z_blEovwKeMz2B$+`?~=)1~v?sv=6e%EPG_A_KgyqTB_Z>I6F>h)E4&iL~0f#7)V$F
zTV_VXs!?jrDdLM%setvAVXf+Fs;+l%iP@x(IY2?TX_l6hs3Ef>eGYUs6VR>8R>D@8
zb-^0KQWdDY4tzGA3an8*(N1ZGqiNR!CODd;W|=2EodR7y=}$M66Ltk$0aw5ka0Ofe
zS72iWWP6-FGBjZV8ESJa_iB5d-@!-f^5-BTEej;9fGsm?Ax?2aSiF&l3Rq7W)~c?i
zqHmWe0>EKOUPgWbO|!J5#9##aD8AM+7m?buwXict0zrx0gd{<YKrgYtMFp&<3~N+R
zwA+Lkt=(J!SHKl;1>TPWKOT70BhPl=$L6EC0;3hk9vPaX0vT#|FZXJDp5MVo>hjxu
zA}tFftbi>uYavc?Ls-0#hzeLw8P=+<rlN0`DFVRFX5^m()vuP8q#KMt55?Dd<|0y?
zwib2<Ngyb(n~)@^5$GirxTt{jlwpnPiFVsCJ59al=XM+g{&I@P8OA4>72p%Z?WhWv
z1)w?TZ<3*wfy-|p6O|?q@m@fFw7-E)gehv;df1oMCeN$|`){EhNm4q={p;niHd~;9
zT8LG*jhP8n1W;k%sM`6T8JVQQ?q|#(mC>q@1aE*XGi#!r{`_Db;8gUM+47G~scur%
zGo$hhy`SXuMP8}vA2~i>5`U43Z}K`_{#}Ztg9`jE2@A-Ssys^(jjDED54(UEW>v%~
zDF1UYLzn<VtAO>CVHZKlDHC}0Qesvusswo_46re<9|ug@2l)tQm*usO&~{m4VAFO3
z+@VvXC(k_b&GPBaP1WS1I*`DR&$4ll@0SiLpq7v*X?iJNiilM02G|9}FsmXG{3I_m
z0=>i{7ZtFcGOSg7J7xi9ZpTu9cbc0k;0ipA0uiQah3KK4NKy-j-1jUOW&v4>=-9GE
z!V1_0MAdfhwwCR~tP?cMB-T@gjdYm1C2lrkM!Ud8QN+=*NP?mz_h$M;mf~wYOA)y(
zizKXoT|iVV%(_gCKrgYxMFp&<3>&Ccs&B`P)^4tVE8q&`6!?^L9>jO#*$(oEo_mb&
z-1MD&MuGHlBFRMD^~4IqiTiX_o9mvD5=m-zFZUg%w91~Ijx9?htbi>uYavc?b56l)
zPAAq=hK+Pks;j9kXDE{DmSsjs;G!tvXjvpd(UN<Ek;qbft!F7Bw`Gxp6|f74s)bpX
zsS)TUmbj>Z^^{=))k^j4n9<tJ6>tSy0asv@0$~)e<K9yNc4`kb`6E?_wY|*7M$GM)
z3Pi?Io9pJBva3%dsolNYcbw8HdwM!n?FQH~vnnFNC@*tPAz)4?)>DS1t5#i!c{xLo
zRJJIgEHg?17ex_A&62zcA_=eG3<e{SrTALUQbcaeZh>7u6lIt-?N`ZABhX7MaZv&5
zDZ>V;mFn9uqqUnW;0hdAfjDNiL9kt))I${6FS8+XIA~UZhaYxdSPX(?U$ajuGFzt<
zd$s{K1~v?sv=6etEKa8$x!RKozN#gnYIiU99jCO)o}P{^OC+p-Ei-E&PH}Ti!D~(@
z)>DR!bTCJnfOqc8_f5+%3scc_om<7p)p3~;6)h<;7>Q2TPa*x^YtQ#0A}xy~ydCyC
zh^p=0a$Juv^%52dD%XM9Yz8(^tyDKDWHjxXz|5>!lutNA=kYcOmcQh@PurMT7&GM{
zSbmE3Y5QfiPraO#E8q&a0((|q&}aG>*s$9tQDqjPjbh6g3rEWm32JjK_e%#AP^X^C
zo}P{^OC+f7a^C@4PN8Ab)Cly#%<05>%CM0RN_90AfL)elMrGilDB`G^(1|1{T5@kN
z5?P9`^(;l?R_zAZ1w>JXS<`}Ks1fKTmbj>Z^^{=))k^j4n9+KLMd&=<2EqR0@soBU
z?w48T0G{RwxB}}G2<ysjtr`T&nzv8eFSC8>^*&i$wt|lyehh4S^qAdvRc4VkYIBXF
zYO)bdB&glJ+;^PPDtmf5R_zAZGP5coK}yXzg@8GoSWg)?(m|=N#O!(p7n#vJa8VR-
zv@DXKXvw{qK9P0JxAtEo$!%FA;q9;$W-Y`iem%m}OT3B5b)YtzqI_L+4`vW^a|K)h
zSHKl;1zZ7Fz!h)>-lqbQvDN;&M~6g`+NjHY$0<#pq#g!aX2u*%GY2;+)R~Y;tfvec
z$yehmF}sefw8%0e5V$CcI9e7-P_*RUU?j2>U+Y<l$Zc69VFm00qH1B*WoiU^i6t&7
zU_E8nK($hRJ7%<Ya|K)hSHKl`HwyfG;7N}>+kqdOkLC)DRv<z^ZLWJ5C6d(cUhX?i
zX_Y-a9b1-2SOHsR)<T@(=A44poKCE#3>)d7R9917&QK)PEz69Oz(rBS(XvQ_q9ykR
zBax-}TF+8MZp$JGD_|E8RSUB&QzOtzEOAi*>nXzqs+H>7F{8DcE8q&a0<OSN1<V4_
zWb+@%u)6_qn)M;j>uL%4IkS|{MWj}3J#39x6;gun?{c{s;iZ@Og1oK+wb>H6Y9ThN
z+Z1YQR%Av|j&ZG-#Qv3$N!*dL`5`54%plei$)l)k>tQ3!^URvC|NX%{z^Udfv)P{k
zqq<F5&1@?Cn_PdF*BPXrCRghs{}XExzsM`e_ovIhOR;oNfp3y<nn9*i<yneItJ`|m
z1;jF|LrV11>GX}Hd4#E#+%xnyc`X6!slcjkM$D-%y{lGYRxPRod7}=nF|cvKq<xT&
zU>5qQY@Ia-wr|zgdf2!0izKUcr&%rk9(^K7EiZEaQC>-2I-oWOr}CmgVbyMcEi<bk
z5<JUGjX*EVOkzD{*hmMZx)Kw>rky1t%dA=H39f)E;0m|`cU8cy5It~aRgj`cp$P=M
zGe~XGC9h?syA(u<Od#N$VIw#B6e2APB&c3;Z<j*jiPYs`RkwT!#VrdYs9u+f#8*Y=
z5~zPst)L|qxR`+2HB^SAxM`-lR0OI_K*5$%sBN0<B_-xrSWlqy<C%f#<_fq1u0TeC
zbH;ZR*O6yC$}{pgTme_W6?l*WX8+xVYj^jjQ>4-a0^S)!pQO~UGf8Wj=`IzKDia8J
zXV}P1K7~lj0tu>@+^aL;^c!5`iPYs`RkwT!#VrdYs9u+f#8*Y=5~zPst)L|qxR`)C
z^HqkVxM`-lR0OI_K*5$%sBN0<B_-xrSWlqy<C%f#<_fq1u7E4x3b+DKtiY!y=H8-y
z<k?!Yd;CEPnEiJXm+ijY-Jed8N)rfpXApgodfTz}2G|IPJToFy6Y7D4d4$M~m^u><
zIkuLV!7g!86me9o_s_Uzlq_hAWKFvPHqcx>m-!htQNKzCZ>S`%?>fo%bB85hJwej)
zuuD-nh1#lpm1ve(waSC8fGhC)3UqyBZa?N2SU%?VY5QfiPrcqJt2k!tL9py5_h}n5
zn>O>0pL7gtdi<cBh;?RW+uzmI?(R>gNTmq`yfeu66T<9?gemGW(_N|}l_n7I8jyA8
z0ozM@t25z{W2=zJG86x+;}|-0nGsB?0+lA9l>D(QKgCTm-K8Q>WdaJeoI-8WY%eJ>
zlT>EosYhT;QNWuePoQa8X3eU60)O3hfQ^CuGGNj^$c>q$KGdzV2EmS5(R;+(FS8!@
zp5qF*0<OSO6$q;a8}ykz1~#pd=n+K)X5wahY&O?jl*~q5sv?yp5b(|*_OKTTQ`BXq
zyHrIgO(5W%VIw#B6e2APB&c3;zuRLgbFMkI@?)choEn`@fqo{SPF4kNDQemcuz}`T
zW=+&28ES-ZDKYPo%4|@N)S04ycVlL>Twy<~sM(-o4D25pFuzZW{W81Hyx!Fna0M<3
zr1eVNQ2Me7SP#9nvU~r1%WSL2bu(Ml-HVQ)Ko~Q|AlS<;f6UBP)G9NxxvsV%$brpl
z)WsL&Wdi~43}O#^k#LnD3D^y=k$OWp;B8rygh0|fLgYpaI)QKIfb~SedDywAl0tFK
zq67m8suvD9k0rh;ia464T3wz>pvnZ)nXmF+B%6@g?&1vDfPyWjP}?-yOG?b+s?2tm
zV=J^X%;L+xY)SNC#{1`}wv*YyQT6q?Tme_W6>tSy0aw5k*ir$u$L2uN1z>jfQWdE*
zfq-`g`KV4(YTHj*(@b}%h*X(Cz&pc6Zt^KaS{6u9z2x3ZQkl&jLsYj-nZ@aRlZ2tB
zh@)wSmQ)0)OhAoP(3YYuGu@>sP-y}Rwwyw3(`+v(G0(z!0-Ybu3_v$mz!h)>T!D9^
zz~=)`dgR#}k1aOh&m2DTY|s2$4#nN<zq_WhyZh5=db^rHpx+FlPg2J^wpM1d2c%h$
zie~86vOt3Bb*V^vRVV99p#DX*;!%nPE+(KxsvPYoZkp*X6@e-fP_X3`YMW+zNr`#?
zT2G+!<C#tWA3>nqj-x<$`6)flKt2fy@X_*U;}hwqwy)U&GOGokrTf2SS&1a6<wfq*
z7RWA0A5Nc7i8{5EFGWOZwjQ>|tcEznev_*qEWSkaD)8BOYOsN7rMeQ6zD+AJqwtE@
z3yo&C)1M#g1Ei|XGLVvc)(?O!GlNvs&i~9jE~&7SSWg+&s2(Aqo-B^4m6%OMzsU6)
z-|??){LVK`lmCe|iDy{<B(E=*in)Udq`yjZ0U=d;=AuiF%9k5pXAsM*g7*?S=Lk#4
zPGUV}*hP?X%4%lK!a~Bwg8$C$L9o1e_h}Dcmc~pz2$uc8er;Nq%>vNm`$;m?GBEYY
zZKGZ<A^&5S@(3K=nzkPH6lrcK2fR&_MI?}<bdvkG%*F>zl9wsko|!;(sR<jmr%@n2
z4O1uT3b+C&@Op*lQ)T%T!n|HlrWT($kcccG<u!)1rmcl7GiyRhLLzAyfnH*E66-0$
zs%~bgG$C|crbN|iE;91Zf$CS)>as1g7>2L?Eyhw*g`0ybVHc1<BPBMDmPHbjPICX2
z*#Zp|tm<Z_isbiLBuVw^soFe;H}p~M$g>^wnfY8b1^7MUQSHdH9rc+#)m$vLZpTtU
zwsM!f`orc*4?}u9&|YR^Tm9-db~&j`f$GKX?j^lr2VXwgRpI8~TG%qPxpVDnBB%}_
za&ITGo-(ZJW~Q0|0c}|#LG_v|)S>6)Nzb9mSJmqBW=Q0lK*T$P*u!2Td~etVB!H&G
z#?i7!!aPFaM$9}5>q+F*1*xP^+_Ff*Yi6w?kGle{!24C8`_uLbCECwyd@8#gO95H)
z**rYb&W{9pFxFmX3lE;#;U1`f*?%{&qh#3Ky*SmuLG8L1kn+*)uCQfhO<19xNLog?
ze8SmDtfvgCx*0JiKtQWjVm1{S`Kzr6{wgm+OMFRQHW2a7AolH$2-B@;H^3&E8_E%H
z%aTx!B+VlvZp6&9u%1L-9#(bBr%+t8BC}f2ePX<!k7`Gr?WoV}9n97Bk-5DNV_@U<
zgKX4szsxoo(A#XGz-24AMXR^;7z4ZC6|>B2l~Um?&tkjWL9lFD_h|)Y|8q*h*KDr4
zX0W?^DQln7BJZ#S!b4#z%;3_pM1mqL_hypHY>@^XM;etvP0JDqub90&ZPkj5E>o>|
z#$t(!2}Haz$j|2OkO<!!b^!^XsdpcamPHcg5fV3IW|GQmfdU1qy5%*are%=?)vHxe
zj`P=T2iO?c^Qv{~5%O%!jCaQX8v`2#Oxg#zUuJ#$J<Anv1zdq+Dv(x<6;@T<Tr>!F
z%!=NlR)N`HPEo4O=DMe&-Q82wv4b~<y`|``uw`aFu!$t4lib@$tfvgCx|yTW1PEx$
z5(%o;%fai_p@)p71<6pY`j4&l?T~=GH|zouKvQDlsG9stL=yPfSRR~wZ=QwqBuTSM
zMZBt;5pzl*t!gD^)uM9nALY<JBV%AAZ-QOgewpo3E+^#*97qAyg_U+g>9icJguS6G
zbl2W8TQ|s6Vn4I1BLDWCDUim@I|%l&%O5jy6}8IDY_6-V2(rt!yL)k}g99H)%Xwe{
zv7Wg|((85$><kitP|WI>5|z?K(lP?Q#Ox&2Q-)RDjF@RcXkALoPEjh=kf3#$p(Ry`
zN)w29XOPN&ktD5Yrn^)ms!Sl_onaF<`4l28izKLCa&MkRWwt<rw?1QPS{6xo#q7f=
z;C-a=hCZt8WVUoveSI!hz!h)>Tme_W6>tT%R3J(-v+eH!FuQxI+B^7IKHA+Aw!*9j
zHj$)sl6x~rWwuBIbqrD6jF^f19!n&tUOa^$PJ>2f(^M;Hi6t&35b@3+_OO=-Q`BXq
zyHq7AO(5c(VG}p`6e2B)B&c3;Z=QwqB<k|8s#`vV;+91cRIfLP*=p`_SHKl;1zdq=
zP$03XI;b6aw$>v%@ME2J+pYOM?h4$ZfZ1GkHM6^WDQh2F?O|^zx+`p%Sr2R?N$Di_
z=GdC?lwnmjBjyAMXv-1_s@Ghh4n1UanQG<7*6BaV<)4mGDk88^J>XSu0~{@jB&c3E
z0vESKDUe=1NDeiV4|9qGH0b`2AHeNa$bHS07)LDtt@+~LB||L(e7cJTE+%lbw@4rK
zLhvBi8Z#(Y?LQK|8sXAQoN7sve_EwB+nQy!%8Fo-nZ&Y;>mC35L*@ZWiF!!+K_Z=B
z>G54Cf@Qk_w#=*yH%I=JAuO>-Tuov<Wmv1a`Dvhk-3rX6qAzky{13GF*EYV%t8Jey
ziGP#S-{p0NlGxHg1%8sq0y3p4&r&qCs9kP=T|f-88sJMzv@wJwVkfblGVCHqIb}7o
zc40mv=H2)94ua)JZlCrDW_%tEuraV<z@+_<A4xR}K(qcV8D{CE%B&9nBqA4(kC~->
zE+VaJXNj(Ztud=Y68v91!b>mlzh$;aBef74)oltjRm(DqFCtY7J@|YITsAt-N8A~^
z0`F6S*DFMy3W2nFQH<P(bu1T=y!;wNq-BAG6|iMyEyO8q2#YroQ32~I!&=qVRP^mK
zMF6<jvU`v@So~^fNvgpJ)GNN$GZ&HCw6(A^NCH8L-Gn4TjX*E4z(obDrwnUUPqf>H
z8J!+$@v(3ZMLY6r4;9kEcA|hBv<_=Wp6##??U@E+;dVQg0^w!n_0XX%yU2%PJ_>9n
zvvF9kzu4>(A&{na_j0ec=lLCcq%ObhC(^P&!V1_jvlikMH-yC-iKu|}lws{bO-)7L
zE>i@6o6X2S2dZB!ElD>RfgXyl^~^=2Hf=5J43a=lVmBd4P$SSwEO1c)>nXz;)f4Tu
zVMZr6SHKl;1#$|!Ea$n%^ZWKQo1br<|K0R@f-vBG!ykk@s_kU9bX0wPu2siY+0_T6
zQ@eY)SKIUa4n9(s-}V!!+6}N}W>rLjteA$d_@caYz<SEC_MoQ31h8o(W>cY&zuE4q
zWLR3_G}8xh>W6PVa}lXk`zq13uro*kL5Yo{YW;tGA<)M>9ZR`0rOJw6iCMF7^Mts0
z$Ne-s@@)H2*_pgi0X|j+*dSOwGWTiwWwuYf-X|-z90P0&Y#cCYA7q)?Dy32%>eg9<
zVE6lbxB@d-t7PAA_uoCwBaoyv>T<6R4(8mHDEWU}@}~_VEej;9fGsm?Ax?2aSiF&l
z3RGrOlvUC8%wC?hksrEE%f1=fd_M;|XNPP;lCTn1%deE|f;EJtDo}YH_-s5CSfhHP
z-8RhVw8FlusM(-o5G;Smd7rj1vzMRphmSf2Ha&dKUcmh_>z%;!Tme_W6>tS+1=9S@
zW4{i99kZhMNLyg`;?5o!nq31K*SmY})%Kk35wAM+SkF>KZp#7*D_|E8RSUB&QzOtz
zEOJo+>nX!p)i+}nAeR64HKs`Ek|bbhiBk=kA1O$helBwnfvP2mu7#aJ=%L?zII70m
zGbeeVN(HQ^44Z$`E6wO%wGy*xQ91ZWIdsp+AlM)7InzzO_si_2vAoz7a0OZl@R>fq
z#=xclllDRGmsuZw&w7Xg?C%EH7}zji(mu#4v+R+f+BZscYN>Yj;#Ax7{0^Sl!a0aY
z&7uSY2`gaB%xG9OO3gV%e32>@u%0rkRb5Th^$spEgV>5=D^-@3IMtBZkv<2C%>;Do
zvX!tEW?is`uv7&quLGZrrvjUQ(<{yB-?VE26Wq%WSF_F&o=t(SpY&%N%K5qiu7E4x
z3b+EUfGcnZ1+qtmCQcwjZLZ~BZO`*N_()y;97LpLfrJ&XWo9kJDQ*ahHxf|+>nX!p
z)zwt=?J`9GxcPiz<nL-{X-S#E2=r2Xt!FMGwP|Z%XOIMf61xdWf*OHdVu6baSWg+&
zsGexI2{SZua|K)hSHKl`KMMSK;8Bk}+kqdOkLC)DRv>$1Xp#zKsNKEXtL=Gy2Op`+
zZ~KX~ERe7Qw#=-BIK>TN@kSylU_E76tGb$szFnpW05_YFe-2c?T3V8BFakXkU+bBR
zNNw6$*cl{&pu}!MlAuPQmssGU0@hQ8HL54tZNrRCZbwt#^0qtLSnquvK0(}$s(@Jl
znuGo(8EP3|r4UP8Od#UDfc$9x;8Y?^QPbAL)|j<m|1H!bNlGWVf4w}`W(zb>3$f~!
z*NmE)6`4s<q)=htsM`6T8JVQQ?q|#(mC>q@1aE*XGi#!r{`_Db;8gUM+47G~scur%
zGo$hhy`SXuMP8}vA2~i>5`U43Z}K`_{#}Ztg9`jE2@A-Ssys^(jjDED54(UEW>v%~
zDF1UYLzn<VtAO>CVHZKlDHC}0Qesvusswo_46re<9|ug@2l)tQm*usO&~{m4VAFO3
z+^ZAMe4@F0x;K&JqdJhpkI%AkknficDxj8-C~0~rUy6uS?FQHd#4xKO68t1DH3GfF
zA{P~~o-(XeeJf@k9`QrW>~4=#;PS3}B&1`x0<OS%1tO(th3M&(NKy-j-1jUOW&v4>
z=-9GE!V1_0MAdfhwwCR~tP?cMB-T@gjdYm1C2lrkM!Ud8QN+=*NP?mz_h$M;mf~wY
zOA)y(izKXoT|iVV%(_gCKrgYxMFp&<3>&Ccs&B`P)^4tVE8q&`6!?^L9>jO#*$(oE
zd<<7$Ukaps(Q!80C=jPM(^YM*d%7o*)b3vHJ5FhpJv|*;mPl9uTV~cmoZ{x3g4di*
ztfvec>7Z0sQ(ewbB-Jg;jFP}bQN+=*NP?mz_XZ=8rTALUQbcacA_*&C7Z6novo2F3
z&`T_FQ32~I!v?CA>f14+wVNy83b+EUfGgk%Y^6Zjs?i(z$RDXXtnFns_FitsR3I{z
z+FUp1lwExyN$u|CzT=cu+0)apYB#`^nN<-9MtPZY3ITIEv7Rz4UA5{;%*z>yq_RZ`
zWtmYDxG0J^YL?_p5J`CbW-u6uEXCJ)mLhU%b_?tRqA0_xX}?N_8i8J7iHizYPZ>5)
ztyJHR8Li!10axI_3dAw94TA0Zq#mNkewhuC!$GqOu)iB%gJ9X$?9(=8#-43}je!jV
zChdbPFpE?5bXA+{$=$dl;%av<_Z_FS%ATH%ElVV<fGsm?Ax?2~PQhzVC)QJjjdW0|
ztEnz$D3a=yVHT!}>8dE!8@)s$Ulc95HyDYmYrg6KUVFY55ouW@;q9>BK~ycwy6k#{
zsh3nGDz5{z*$ix;TB&YQ$Y|O%ftgveD4%eK&f{$mEPu&)pSCfxFlNd@u>2J5)Aq}3
zpL#hfSHKl;1s<b7_dZ(D8T6Sx1~#bC_jFTcCfnl(QxsdySU6giNKl(=xnDY{fI9V5
z_VjdYSt3Dom-`ObataNbrbeI_W=<#8Q-+OnP^zn`x_{g<%%;|-0Dz*1qiRAYlAvhG
zy}?LiDZbXT6p>rC8(<d@MHyyI3zDHmpqE(Uq5{@ah7D9J)wg3t>lGHE^LQHs`;W&@
z+KISdW}O3gnk(Q6tWzMYE4#I75G-rnK5f6u_NmwVWOdmJK6>~uu<6lbcH>o<McSy%
zHIAyuMmUk6cK34MaZ0P~>FHRt8(_=Ks)z(BHRlup=5%5`W!OjurMeQc>m6KV#)Am}
zD2g~*7D-UF<lao5$hziR`!AB@wk(qHcGwED7UC4Y9%1Sw-bCa&P@7FrzAm~0GkMy;
zxgAS^uAlT{jqKC70<M57;0m|`u7E4>b_Has9jQ|L@18b^B(+hO`;JqZK1n?cw#<w<
znr04eRH!rIbfPexGHj%S8efUoy_wB2qj3O05yH{3NP?mz_XZ=8rTALUQbcacA_*&C
z7Z6novo2F3&`T_FQ32~I!v?CA>YFi}TGQUm6>tSy0axH%DDd-vr#$j(2Yzfmnkz6`
zfd~P$x$a?<NK(6dx$iioRrd6BY*`{<1#FpF3vr5@a|&K_I<cNIY@~xyT}^d4Ly=Us
zEHg?17ex_A%OVMimfRbRM3&-fJxdX}EsG?qfL%aTEzG)1jX*E4#6<<HrwkjYR;q8u
z>_s5}+>WDwyq9>txE)J@?$4lOjr~rhF$+L*?*B-J-3^G-tPg=+S4+sxr`MkEMWj}3
zJ?wXo1cF)-tB?|mf0xVE2+PV9sJsf)W=rHMSfjd4p{8a<W)xi!TNu}xN$g)4nZz9_
zt3TPwXcX6NJ#3_Lo>?7IqW}FN^HvnUc}Uh1X`Y8Qs%L*ps4rWI*;Mg2x&AJ%Ge|#8
zuGU5VC)Ol>kyn!MPnUm}V(Fj)-z4EQgG{N)vlNk5xAm|Kh-FrXl<23^=^IJ&2vaY)
zXXtP8S_0NnfmPj%m{VVRSFOaXT2u-0Mjc>dVB>&E`yd~|Ec8*?I%^OtpRD^eK6fMZ
z)B=E`YVz;VClb{1BKIHVmE@%ZYIATZFDevP?FQH~vnnFNv%J&@^uo*})>DR!bWo}*
zF#&AaSu%3WQnS(%o=$<Tcf`|8<%C^<<0@cRh@M%^svt#?LK6shXOP;WOJ2)NcPWSz
znLxlh!$xlMDMVTpNKn1x-Y$j46RFF?s&4rdidz;)P`xe{iLZ*#B~bsOT0u)Ja4`Y3
zYp4uKannq9sR&e=fPyWjP}?-yOG?bMu%1BY$1?-f%@uG3T!D-N=Zx<tt|QNOlxOtR
zbEKzc@8q)z{N)t0es?~#0_?mq`|qxq?C$>b@+L8Xa1EkQQtH>4_k@i!&ok?R4J4^^
zirlL+;q?1D<B8PeVO6($3dJo8B&c4Oio{n%=n|-ZQLUgQ7Py#zI`dVAq_}COyHo_K
zOhCbwQ>bm4?Ik7VSy)e?^W&L;>gEc#0<M57Fi3$k2-jinszAJJ_e}Fo8Q)P{dzp>x
zuiHTtF#GT3oNV{)?*4R&RGL7*JA>$x)Z31&H^4?X<e3qvnotiU%p*i@#MGH^$g#D=
z40ef&qKKnvy?@3%qhvu_Bx~9Yuz}|4xy;YFiTYJCcta(5eb-68pF1o8>j{#Uhh2)w
zDb!Z&t3<QRs#P9z1zdsWSD@=7bNeyJ!16J-PunlEed_f-S;aA94}xVkxlb!Hi>vrf
zoB36hHx-S6O*e7AXK{(yhf@$(v+eJqVt4naQ>4-a0^S+q`w3z8M8XtxndvT7kxCN?
zcn!$9^MLIoz15j;$gx#OWSAv!zdnwkLzfxBq$*Hp0!qmr%kop)G}B!w0#zoUV9P1g
zHqG{u5;I9<HlBI}#uNp-S@Hy$mSxtg$|vyGZ3oyG*e?Sn?StHyS?WXGI%^Q@m=(Q8
zy!|rkVedJvfGgk%994m^YOq0{>0@BiDv2IZRA$EZ*le!5D4C7AR7EOHAmE)r>|rkw
zrl`wIcd3e0nn1ui!$xlMDMVTpNKn1xey_(?xUM?3@?)chL@=?y#RSyJs-P`JO}ha$
z&^*hmiJBxsjSwy+=3P>m4eF6PQxx!S%#4;R?1vRK8<dQJ{bK{>_i3?TX7`!bySf6d
zz(s*HMu|bNWA@)Y67QE;4|~sfi~`{?Ft1St!CrRxui5P2zRJvOuA788u$hgz_#%}i
z5b(|*_OKTTR|%4U-2fY@&od)Zvnatp!aPFcMr`=8H42F!FT;%USR$Y(;%J&0^72#y
zRVJX$e3kzq*@Vn?7iY)@6l^(#+NRlFQexgEmD%ocY=w4~+4L`4Hiz;ASHKl;1zZ7F
zz!h)>Tme_$XbP}BHV2ZfA<gbysv?yp5b(|*`Xr^c{iHR`beD=ql?epAGi>B0pF*T%
zfdth{?$w!a`Zb>MMC$Ues#`vV;+6#xR4*LDCh=7f!qGI<3R+@;iwUTcRb@zun`XL8
zMWD(A6l^(#+NRlFQevKk^#nRUo*Afau7E4x3b+FAMS;%;9`wkw9r&^NXs*C;1<d}t
zi;>;kpH7iV69{-`5Pg#JV{1(_bZc24VHP)XbFsu%Kek@f$bWgZW9#(0k^Cs`eO?9l
zDRpxNT!Cj%AV4&?>J|t1w`_|dQMEmid$k3!3(|+v=ge=Qmm)gWY&~p^Sq*WD{U%qn
z_qeQFiRe|JI-64Js^~7vUJ-l2z*)CHKiCIIg?ew~2gyC_2f&t@)hCtc`Jb7$qWJA3
z)>DS<c(SXRO@+V6^&8*uuWkI!H%*iOi8YC5SpOuiFPDnBg9@a-N^}7sReR>5OOMKz
z8(?P;%dCR;5<2GyOUO=QJ!RNMkaEguX3fGv!pDOD&hA05ym|L&4`7zYOg;#9-v>iJ
z;q8jpd_bQh!z`WRi&UCGz&o!p*L#dt+Xd39b^~mrah_QflAtUifv@ujksC3yJX%jA
zFAuA_<x?oGT8SC$+*|=yz!h)>#wlP|h#oG>uMp-{fufG(g3W9q_pz{LW^id)B0&+B
zdpn8slwnmjBjyAMXv-1_s@GgGKbIwA4phIYR)ycXyxI{lwf!wd!b`U<TM3(JZfYam
z9*ZO?o#fs;3+qYL<zZE~d<w-aizKLCtqPC30<OTjR)F6l9@UOK+fkp{Q_aO<>vlK=
z*nqnoQ312L?i$kW?xn2blvY04-4(XXtOqucq;!&dJBjs_VO2LH<^%|6%MuBy*Ic0v
zJ!Ev5YURh)#*sXr>06(1&vS?*sVCS|<vFf^E8q&a0(Vrv&o_4zcU)^$@kiSEkzfzT
zI`V7}meS!$3gk{IrQ8>PlrQF_MW|y3Uq0H=plVT~YhlaGs*nUlpLF?p3Vd_<gtL=a
zPZ`#z9%=oylS+vhopdYEn)a(?7+T^>RGL7<JM*>AB@w<i>;e)%Q)1(&SrY1zgn5L-
zjhKCh8BZdwE=VPX;+hqi)rvgk3b+CXP@wB0bNe~Rz{c$d*{I`wnQb(nx7k90%T{oU
zR&VJs26p-#{#$51EVs;Tl~Unh#1+sWST?}>v?8-4e9iv5YX-BIr%D|h)Olb5DIe|b
z3R`B@1Di-%M!5Va*h#FX46C{sF(*JkTb4*rz2*ud{~V}(Rjr^UmbjQe#5;rhoS%TA
zE;HSwDp6?y5$_C}xXGswX;~ye^^$utNoBS`gSS3oYFZXac+IR;REYD}Z3oyG*z@Iw
zbHKn2$gP?2?igTWV8eh(`yltrtdGBExdN_$D{xE&(yFn-s;Zld2EmS5(R<V?GK*4e
zw*5UF?e3ncjvajYXm?lGGP54oM3T};?(HPjQ-)RD%u#6q1hi#|1l8;1_SK<>jHU(2
zP_6opt@iDZfV(&B0un$|V&kZq{7gg=_}N$<oP2Mdh4my!vr0w0s+$pWN+GRkC1%y4
za_}GJ&^;q#U?XpWUD|$`?NTl$<q8}~0oH{9HU>5fn6wXazs&mhd)6ZqNRI%q7=vIh
zyL`)MxTng@Y_6Mh+2z~ay*SmuA-{uPP6&^MEi-FQE2W7fMOg0bB-T@gRo#r36Cj{f
zD=|AoDKqj{Tg^d3O9F|Y2}HazNaepslGZfST`Ce)CJ^z?u!);|3XzsY5>zj_H_xIn
zTcE*PpD{HpizK{a_Td!px*bY^bf{^37+1g*a0OfeSHKl;1@5Fkl)h%$--Ts%_f&Q4
z;LAt5yTX>4^}r^QlumMQC$XL~tm<aOoB#oBSt3F8!V%=94n1UanQ8?svBbp$BHkIq
z9`+L9d&4du0W>8xj+R9d<`EJ%V&+*`Pa>}_NF{~hmPHa?G2_<F6>tSy0axJND3Dmz
z4r)i9?Vyj$$8rUBp@7+ccd@d&dnr=~2es>7K*~qEyTX>4^}r^QmJu%Nh@HfG%CM@N
z5px0rv}K6|)oZRW^3Q?lSJldotvu1a99vJPP<?bBd`1P*%kRIQk-Bp(D-g>ek378s
zi3!wF*%~SST{6sWKzxBp6S&$*q!0S{mk)xiF@ti|{v*+=5iY&N`D#;Aoh`p9QsbMH
zDl39TW)jOXu6O+J519ujC3TjGrjg4lJ-!P?uxvNLmYJ2|=E%P?ge4Y<t4XY<3~N<4
zKMnM+TY=eB^hK_T|A7|&+Qv6|we8a-@o$p)yS&a&5?eZ`z)uocK&DjXS&F6>waX2#
z3y5J>1AK{zHioc7>?GDxhFt_Hr>thyF3e}dy!+nXL9qPD?b9B?jL)M1HU>5fn6w}A
zBdKNqXx5)4BfG$x^#On+ukRq%GZ&FowX;Om!p<NO1hpdKsM`O&9^ta&*h#FX3~N-6
zkl2P9BDoz)fpn~Kd>U8a@Cw-Vpl9Sjl3F<AzGJzF)TsqzDI(IcK*9>x1w_?$@3stK
zVG*IC0@hQ8wW@E&3}X2`$P}qvEG@}aL*_>cG&K{@t;^QJmYH?I8p2W)s8j*#DZ`qb
zU!tAT3`f%x0pQ$R0aw5ks3;&uz{A>+XFKded#1tsw-L|uwEDP)mz`H%vS&Su0xzeE
z?2(~4LLftJuH{~B&+|L@NL_y0Po!mmgcY!5W-Y`iZU~Dv5>Wx`DZ^UT)l~HDGDQHm
z*^K;ip!(I)l5~R+=%M&p&s;=m)7HYyAPEE|b`z2WH3GfF0v8pqo-(XaJ<)C(W^{6M
z1zZ7Fz!ey!fS+$hDSubo>#fsWf#&A?LAayZPG*Zo)z{}*^@oIIS09j0?e67XZO`*N
z_()xT+fSrwH^7#eRS^ktq%wrX7v-e`)>DSH2Q?)ofK4kgn+lEm&30cU!_pF`nLdb9
zKYZ(%i%6~7SBb8Lok0=^N^Bfe>;LNufj;KxSjwF#RaOK`%$kLs;0m|`&#eF-D+6p0
zEFYQswEZ&Mr(W-q6<dx0HU>5hn6wYF%xslXsSkDQtU<8*{XJZPnXFZ^@3;H!p63xr
zQX6%-R|f}kZc3CyF8R|2k(LD#R=}2-wGgMcAuQfVL<Ov;3~N<aQ_;7}6oHo?(wC=g
z<nL-{X-S#E2=uz<``LJwB2t^S5_SPeASkh$kR)7>F!d5&cpa$BmdI7GMs=G)P1ADB
znnn49FM0R9y@O!+OV0bWjhVgtls|mbF|g_3bM^x6ms#%wp63d<0<ORz73khaUr(Q|
zZyxvkAlNZ0dXKDSX0kob9vPZl0~u;_E%zNe_()y;97LpLfrJ&XWo9kJDQ*ahHxf|+
z>nX!p)zwt=?J`9GxR(dI=I^$qOD$i&KT7%DU<5K0U+bBRNUd6us8vIpa|aT>^HH$n
z6l$u*&xGkEzCe`<SWg+2u2EhU@<gjvVpc6G2mdIC?im>b`@=nFx~cbmncXy&7rO$k
zKudx04y;vqQ+y0;x{32Wi}%ayo>P18H!8sXZh(z}4Fe|agRC;k9vP~AqeQ2cYIiTr
zj#C=7g*`oynnei)5>~*LnbELnl$vvj_##y*U_E76tGb%1>m6KTHYsEdP|$6fr6nb5
z$m~d;1D(wTbnCK}uoY%qu!gWy1uCxtpN*#iYgA9PQ<~vu+BJa*jwY#D<_S-yK-W+D
z(@o`sT>)3X6>tSy0aw5k*jNGC9%qjXO_)H2+FZ-M+Mefk@R7RwIfzKh0tqW%%gkDc
zQ``_1ZzQ4u)>DSHs;jB!+hvLXa9EO;k)J@*EG;Q97=b>Dul3ADq&96W><p4XP+~VB
zNl+uuODu3v0qZHl8r2i+Hep6<H&?(Fa0Og}_oKj%2OjmvvmN-c`Dm`dXa%xIh9;>%
zhT7fBz1p7Vckq$A{I;J+%K`~2V9U%}h*R7U7H=e?0@hQ8wW_PB=-XwA0C2Mz`R73O
ztEDCB1|!fz@wJ}0h}5R7g`GhX2ukcGBnfH+dWi)tDquZjSfhHP-8RflQ!o0t9Y=w`
zoZ@kY@kwR{_yln~ssd&KXb$?DWT<7}@>|G6r3pm57my$AZ=e%likh|__GPunGi$;A
zTc}5plumO0dU>qP7HFUrV%2S9W`Y#~R2Vp_cK&BZCaJLd88b*_v??UQ8(_=Kny9Bg
zKbQwN6}@G){9{w9o0Rp;s60dOCwYC5SL*slj?b6GU!>xjyiS*YmtyIl0>4Yb0y3p4
z&r(FAs-4%vE+B?k6>$p6|6I%vCcw}tU_E8nMUZmJ1YW(Am{p4^LEZ@iYz*wj0h9JY
zK7!e0dF>;#UDg=bwA}!A=oIP6Gf#Z8e7bW}HTkFxB=F<2Y#ikKrGpBnB_v9kUdopu
zB2~Kqb^$TWs)z(X$xDquFR{o)1+1qGYgONlS%8__u@vB)=H?2x0#BnrgsEB~dZ;Io
z)WRY6J<EkzK$appwk(mb0(JpWwcWd|W&1Ge1PwEZ^^{>F9p-L{n+=)KE^tv4akMOw
zplHdxnLd%F_*&0WL~hF>2`gY15LFAaE>k1WODu6w0qZHl2C9|n+cBfHn=9Z7xB@u^
zKINPT@f~@#gFK?=9wR(AeP^FhAibPOG7)z@u>x`8K3&!3x@V+BlG@$Nea9)SvZtqG
z%MuAIV9U%}h*R90Q}CM8iS?9WBOR3LYO2c_iln+_nNbqBD2g~*7D-UF<lbN;vJ_wI
zS&GPQStMZv>;j@{Vb*181bT@jE-GL>W!ONqQhhsSw03g^Tme_W6&R&J7zOOO_f&wL
z+CxqLNY!C&FSD@`b33L2k+Ia~x;dxp>Jv$7cQ5xHr?kqRo{m+!0k+JnibycZ%bZgP
znA3^%lws+rRaatO&QK(kElMcMjFP}bQN&TRByWO9!s|DK!AN8&zSgr8kz2D{U>6WY
z8D>rURWj5F^b$*4RKR-5uz_l&`gY7{?dA%&0tZ$gj+t!`Y}Y6C5JmROY=|5VnpNQ8
zhus$zgJ9X$?9+<O)+xoFZGeq|4Fe|agDfzM)2T<U_N0QZYKf@Y-OGK)DXp@nr(??!
z2`gaB%vy+3+?-SJn$wB(lwl(s%#kMGo%`~A(=yD$R5V@ZR&jE5T&6@tONtCeqSN(L
zNdNcR^Sy{j%OVMHhy4zsYP+`_*CR~5ghhhNb)YtzfelnE)lCW+O}i#AGiw&*6VA|i
zybXfoFFEhiHf9#aOgRXapQ3%*ewpo4FK6WnxB{-go)sAMnLY+K?Dk1inMG)$*mB0g
z(XvE>+FZ;1(m@5(si(51r(??!397r?cfgiYXxKD00=+PEI<cNIY@~xyT}=gGmt~nz
z8Mr8lII1ReA_<C?+#8HUmf~wYOA)zMy8(6qQIuiUv>+L31bT@jE-GL>W!ONqQhhsS
zv|eEmI*+$Ou>W}cq@9TSW!5=>r?~>Iz&ZuOy0TlV2EnrC?bG(lY@d3)Pga+$;G>5h
z1DhT_W;b4yS)`5HT;r&kY=jdDYIiU99jCO)o}P|Xy8*V$tcpmGQgcorU`{92Q-+On
zP^v32yWYV?X7mnR6h#~@izFyoa&M+jWL@*E{TE4cTNX)pJ8Xqn3vr5Hk1+KTZz6IX
zsLiG*Ul-kj8N}RN0aw5ka0OfeSHKl;1zdsmsX%0Gwg2wXA(5mu>T=(4O4BE)hryPa
zF-OzP!Ho)aCS(%pDZ@tc)%Z%xu45}LvdjnsE{Y<KmPHa2Ex9)si7ds}dX^$`TNX)J
z0lR>xT9|d28i8J7iHizYPZ>5)tyJHR8Li!10aw5ka0T9t0zV&k(j(7y;K$~pxdNjV
zh!9Yl>mEjlB(=Mj`;JpuWlvAXmL(Eaz?PY{5U02~r{FcG6YD9%Mmi|f)l`==6iIc<
zGNUALQ512sERvvT$-TiyWGTMZvlNlrvPi-T*abw@!mP{G2=o$5TvWh%%CLcIrTTWv
zXzk_-xB{+#D=<_6vj8;N{6{kEZa|!7eF*frT0(x#Eah_%sa0DKTVqy*lwkb3T&_lV
z=_S4(uj@c<wnVO4h>hwtg_@cbnNgHuTx%w=e`RD6ccg57NQoOWi1kGBC~Dh!*hup{
zvnK3+e=rYls(H(7_GiGTZc|n>n+pFX*WcxJ2I;5C)w;<4#G1q}@=Egk>GJPVEFDzf
zn<SiOkSSGpmLk&XwjOo?vCQg_68&^KeIsceVd^FK4E;@BOTc<6u&SF8bLva)s+E{k
ziz-3hr~_;aY#cCYALJvLg+3}<XAOewTQ#;G_AUJ)$!gtcR?ELfpGZ>6i`;*dSCW?w
zsLjEtyr@uEwHsi|%&Le4&+<|u&<it@SWg)?(m|=N#00QuXUWJiYgT%KE8q&a0<OSa
z6|gHr51d&Qq$pBo0s-#~Qd@M%YnkaT1(6~X2zY1M$W1<lNXr5Vs+Zi`rO<dHb$M9T
zEuTVh%K{0i*QFxyRS~)b>R(hVXo&?bCZKi=l_4o^n&~bTfhrSFu;mnLn`V1SiFp>*
z6X^VSW}v#c0<M57kWt{A@g2o=<k^n$jC>APz!h)>9;ATTe|O>9-TmnlsWgFrcLvcX
zDfR12(wb(vOGTv01Ona}Hgc0sA=0uyg6bvr>P$HO2G@8Zb$M9TEuTVh%K{0i*QFxy
zRS~)b>R(hVXo&?bCZNuIl_4o^n&~bTfhrSFu;mnLn`V1SiFp>*6X^VSW}v#c0<M57
z;0m|`uD}y3@ac)Ux2PX^w$|((e~<!Z|J}r8yKi^*r&FZT1Ona}M4zPIc5J-?Ho_s#
zj7ZgldLUsQA#x+8&V)mbttDo#OI#F1998T6GwvBB3)&)C({6wbG*{1Me#TAIuadzV
zD#`1+PV)WSVF_4IkhDDPQdCZ%wrXD`nq^k4@}Mi=3Ov68T_2g-k2waGkGXx?ewpo4
zulLC+jv0FpEW62l+Q!VL&HUph9Rr&lKWHanotfG8cXhS9`_m~>X#xT74D$ViFnc0l
zin`2nm#Rpm2?V?bWZikd_LAP}OgQA&DkQSZ#Q*9zh7Mh31e2;jr3ok{e=N&Sannq9
zsR&e=fPyWjP}?-yOG?ZnmDzae5g1bx@Mg&qXj+z8vnrp!U$-4#V_?4wn6wXaV`ixj
zb?dA_uwz#A9`W|etcShlxB{+#D{xc=zOEW<&}aG>*tANbM--Krp_JKNcTqAMb*YL}
znn1uigV@7fBur74neI{*sWgFrcZQAJ<Wq>WERdjj$^CARtq@&vY%RSR0{ztVM#+M<
z6BDXyb^~mnZ<bjNaEc|lW)FvNnGNbuUX}4p3h7l#63sHJR+WQ4ltcH7jDh{*o+I7V
zd%w(X8q14a0au`<Kx!r2Cq4+4HE*A`UuOH%>wU5cW5yl?%Z7KKR%K?k{mmITu-V;x
z*ACtu_9Adqf+S!!z((o~<$$+kQ4#`4N+-D=er%0GBFM`y<J6M~D2h0mriQ#cl|YpV
zsFPLYzeqMAv)#oRvH=BKPNBAGwwIKccS&V7b0$q-D%DL28BNPDi!cAOWwX>1o=So6
zRBWBBE8q&a0<M57;0m|`gB18faLs|Fi;LOaOI4)O1Ona}q_U?ct!bvaR79#wAmE*0
zBRBaJA}tFfs9th!PAAqAsmsHvZuu07TNX%Ay>JM%boqJ;d_zW;saDVu3tUV<ovbQD
zQrtAtT`B@qCZJ%;DbzO2_L36wEUYKc`O(Z0pl+^!E8q&a0`EqF&j+6L$g>^zvH57O
zz;Ff3{=18j-QAx~kxCN?cxRBx(T=pHneI{%sWO3pcZQAJ<Wq>WERdjj$^DLxt->zJ
zOH;(rG&LlGi3Khupw4^+Z7J$9(_N|pl_sEI%PG`0&GwQK^DeQTK<CFZoBlt7K)W4B
zf$;KEdYplL5)|O0#qFpH1O`(JKx@)}%d!$lQp=0nn?H?{$hz8Fe9kQ8OA)y>TMt`f
zRzsX(zsdD#gyqi(C8Ae>>TF7>tD?Iwdqr$vjK5-key|UaboJiI4`MeTb5RBF61o9)
z28py%%r3plU(Wx`ycH$gPGUV}*p4S#rgVvvm`&kd<ob>8_}4am=bNU<|HPWaGpv7-
z*OyDh+(8A>UnRPLkg7d%(WOV_%MGwIh-Fs6dkLL$ge7Drv7R#QB1k!9HM3@6A>m`e
ze`og~Sl+z*v<EOtV<sO2%YI<L_7A9;1)$0IlVqp`ij_hvaxsB`cLurMW4zifkXE%D
zU?Yw5%&L$CWf2K{okxh=h?(WldLnswSk*0`LUGkf%;@cQECs@`#_?%ffx|0cSBRdG
zmtP^ws{%zG%LSX+MDAl@%go@?vP6O+EcbR2>nX#kZbr-r5YUz-5>&6bVty`5#vG`A
zRjn@D!lgr?G&_?0EyhwrP19DwCK{XCh_}ZgNlGWVH_yU)5_Nf4)h(YwamykJs#mMR
z<F0@!@U9i$_lQTeBhPl!XZBQcvDmsDO99!+v0HUJmI7?6GyCtZA?@y7%CbkAM89PR
zUq0HA*0i;-WoAuCNk}9uBV2wI>?GDxhE?6nR1+YeElVV*UUP*y^pMeIsui@v5*HJQ
zcxRBx(T=pHneI}Ns4{_wcZN;e<Wq>WERvvl$-Q|N)|05q!>Vri6pC9GNl?976&`m5
zTme_W6}Ynk{Ev&>j;26*^g!oF13nOMFSD^9cRQ#8W^>(~GfIZt-HWs1lvY04-4(XX
ztO+anB$AX)a&ITGo-(ZJX2hHT0j*kz*;J$sJ)kx1SIIE6#FwZvfrxhov2TY&_};J!
zNB~WVjiY8ss7Dg!5fV3I=2=)zBCjq;C57Ue6`9qFJmw0x0tZl_>mzgfImf`p?FZSY
z<9?ZKG@!THLIJiM18fZJeoujAW~-D610JbB4uWL^yiY4I`=3)1zGna3HG|#VOBrtx
z6G-%1K*~ou(wb(vQ_%riPH93)LLzAyfnH*E66-0$s%~bgG$C|crbN~2<skOzI7UX7
zsaDVuOI%DK;+@ZYKj$a7H*A7Ko*9vrMH1!_5;tOIlFDp>g10_nYFZXac+IR;REYD}
zZ3oyG*z@IwbHKn2$gP<bKGPd4ZVr!u4L9??SA+dByVu0t*A;LDT!Cj$fd2&Wb_;JW
z*`i_)>?(=2n77%Z$PA^-w!hhq1hc!x*|CE!AMI$+w6(BhW=%**NF*tp<latVJ!M$c
z%}g}`0@|`fg6j2h`|8j`M$>|1s8-MtOI%DK;^mFS)b{O=@ZKAC0STZfv2j#Qs7Dg!
z5fV3I=2=)zBCjq;C57Uum6%nF%E9TMhAD^d6&V8?c@yl?_RDOSaycni;6Mtn$_%hE
zuwlTYeUSTQ*2mwo9-%;b1c=2L1bf-#TRy`*Rc2=Y-K5Jw#qRFKsSXb6Jg|V2k9K#3
zEi-GvN@*f#8R4=swv$*-8CG>OVord7R;|SB6s63_Uu`u94J`>If+i60&LEZlB1u})
zOn0eBRGC1;JHsY!@+m}G7D-UO<la1s%4~rKZ+*tpv@DYFirI%#!0UD>1=69W@nKv6
zSHKl;1zZ7Fz!kWY0{kZcv+eJ~GP`@KI(G2oqupI$%glOU6G=)Zxwn&8PZ?HqGh$AF
zfVM1=pnBneh&uF;(PgR?w8Rn@6Nq?c5PR55gzpWzfCSK#*f?4iNtj1S+=!WHVLgew
zx*(Mlidz;*c*TrcH&?(Fa0Og}ccVaJSv#m5dA5T-G9Swo*o6XS|J}vP?(U^b9URoI
zdjTmQ?d}R&X4V6nNLog?tRr?3>nX#kZbr-r5YUz-5>&6b!pJ`ds$W$rKeqBj_i}7K
zokI1|dGHw(NS8ll|BT$7b5Vg<jCkPr6-bPrmde&lk$-^L>;}Xas5F7AokaSee}DNP
z*cvk^SM5I%y&B=tOPsGZCDqyTn<6#7NvX0TSY#%#EaQ5||NfA9fKpOtnP?ihywc;l
zPz1|%18kXD8E%gJD??afk+_<~ddjd?b@S6e|GE{JO+{bin)n}R@vm)slULh5T@wE$
zslUtX3?;Fpg9`j4kp*N*Ri342YEiq~0K0$~W;MW<m}p}NOT<oMJ!RNMkaEguX6?d!
zM$EhK?HvTmkK8`(5zP2J8en5!!+=TqA^#xNEC9{=vt(o!c(Xoyl*}Zr?;zGQ7m-%A
zvqaaz&L9y4wIbrE+W)>D;j-k|Nvx*~YgCVr*oN67eu}G-d2n+D(&in#p)24D+*1L&
z9`v9ElGMT>_Z`bcq)sg$OA(Ql1rk=kE+DG5d$(l>3yTO96|kN%tW|wGW)REoL8eIU
zVrfaX8ZtjppsAUFZe6w(w#=*x))1DeK&1*;PZ`$i{1WYyW;mLr2mt5i3b+EUKt%yL
z0v^_mJlkO(+A|Ht!tHh}1;WeD>sUkiG%u%$?2(}<j=Uva?e67XZO`*N_()xT+fSrr
zfdsXum-`ObataNbW(Z3~q)G*>rwnUVS5wiq%M=0NW;627f$CRFOVSNSpoijXJ#!JM
zO<M~)gCr1?*iA?h)Clwv3tUvdddjdy^+daEn9<426>tSy0asv@0>6#|cHDa^a9RED
z388!Q2jPxtJDDvWRbQWL)gKa;U41}0wY!&lwLQ=8;3IYUZ9kE!-2hu=Rz)Ppk;)Jj
zUzC>)SWg+&9@LbWU7w;QW)NHPUt7OQm8B(4Gkp-Je)!fi7m-@EuM%AgJA)(;l-M|`
z*8kTR0)5QWv6MSgs;mf>m^BMM!4+@?o?8JvRtDH0SUxiMY5QfiPrcqJE4Ca1Yz%B1
zFlirTnb|6(QXlHpS%Y9Xr|r`U%w(;SeZSp*_Y4t8QX6%-R|kjfkFA0b<h2I2%#4Oj
zGsh#Th*YV7^^{?)>Pk%dc9|mZ@<aOaw2k~-?JO-RGZ=wh*L*)4&r(Ec(^kSRAPEE|
zb`z3>>k+12;tQ_>mDv)x3f8D@Q>bZLj#;xPpYSE`zPEP}EPu&)pSCfxm!I;7k2(f6
zJ$%ky!2L4ooxt;40aw5ka0O-s()`V1zYc;Ov!eG%TV<9#GBmpeGSuc;?mKqyk-Gdj
zh)Bx<2`gaB%vy+3+z=LTB%%V=Q--ywtEuSQWr_fBv+>L$H**HxS1n1@(h}#~frP>{
z4us4EbZc6YjJ2?3W=&Z1F@(hzs8j*#DZ?7o6YbR707unI%&JA@;2-7CJtKo)f4JvN
zH}&2xvzx~9VpqTwXeq#F`T!dPn+8nU2f1Hnef&M^Aqud+8(?E#!+=TqAgj!>M}}(O
zDAB2<+TDv&ZO`*NcxnshAR;x35)34)fGsnlVbv%#=M?cps#L&w%CJ^-HC5L;xWo)%
zEB=r$RhE`G)sWedJ_m};1a#}Nm9Q0NU9g6*R0S%p1D}nj0-Jx+E6wQNv}*zrT(iOx
zTme_W6>tSy0aw5ka0Og}BP)<SGBgJcWT?%x+^g+*eg_|^%b$aYv@DRY0=CSog*e3x
zVev*HDquZjSgX34ioRW@2mm*mk$(<Uzgk+7ZZHBp6kqF^i%4zSTG$yRfuO{0LXx0H
zpqE(Sq5{@ahBc}u+HJ#(PHwJ%E8q&a0`EqF9}hg~k!L&bWAo8mfzb+Nj|@#xfef{~
zmwUB6&+p(Pb@^>Sk(LD#R=}2-wGgMcAuQfVL<Ov;3~N<aQ_;7}6anC7GxE=Y>Q_rk
z(hWwShvI8Ja}lXcTMIjbBoLI?O-K^d2=o#QTvWh%%CJWDM7wR6(aFsfa0OfeS74|D
zW&voj`Ass^GQdh9mbjQe#Crkx(f+}yM3|zct%t2KYr+0os7I2NPICWxd92MAXrLBi
z)h(|XH8m?TlcGqW!oX3r^FK2(Nrm0dm_aI|RUrx909$6(L_Pia!92jJ=q<D5ADdF$
zq^xH~<r#WE$?J=}QrACne7+?9A{F1{b-Mh!6iWvc_+1hfkSSGpmLeKe?Ytg#0Wr*~
zh*MDh=VFF10ftrq>nX!7f|OGx@am<+tXfnF@=h3FV_-iHn6wY_5zH>jYagNQvc|xs
z?FP74C!YC4bNO^{BFRT}Ac-HJW#b^<FCA1sEg@0T^isYQ5vke@unUM`Rz)QENnUCM
zdWl6YDquZjSgZPW%pm6G3b+EUfGaRgfe5r(A$qtZlGMT>_dUynSwNN|I<_p4umW}g
zQMKK>t!4W#>jVumiS?9WBOT^$iJJ|X(JpXN6mhgHlAvhGy_r6drTALUQbcacA_*&C
z7Z6novo2F3&`T_FQ32~I!v?CA>f14+wVNy83b+C}1wQ4R2k{+wwu3w(AHx-J1zdp#
zDG<R?o9iCnM3UOw%YDZwt+J=5W6Kf=D`3maT8LBJoKx_c(~0$zVIv)s>T0UX8H%L3
zWtmYDxG0J^S{6xAwB+7kB(fA=>sgA(ZCNB?1?&Q%YGKx8Y6N<TB`zvpJ!RNHwNiaM
zX0&#51zZ7Fz!h)>T!Cj+K>kS8VeQDX9rmF;*<caAYIEHjKz8+sB(=Mj`;JpuWlvAX
zs@(uvW>!Tc80BToDFn>v#CpoGbk(XWF)wE*lFAk(lx0Rq;G!tvs9BOXK_ubzo55ft
zvJ_wIS&GQ5*)6aOh@uR$ru`}zY6N<TB`zvpJ!RNHwNiaMX0&#51zdpxD-g%bHVC%s
zlX{3E`(-vn4hPLD!2WK44T5D~vrpTY8GE(?HU>5fn6wYF$}G}DZLV>&ERmpg_j2EH
zN~`SY>DaPF!V1_jvlikMH|G?*=5%5`W!OjurMjBxa)u(QZdqoO1TKmqj+R9d6fL<o
z7>TTFzUlv7d%hPDX;~!U?XcfLR4vT9?0ST$msBMxuLHH&3~ZoUscurpXxcS_nOU<a
zpKylG<82Tuf5~~DwlT9XX39aZ{1ole_RDOadO0gsz!h)>9;3jot6&CwrjLOQt0a0v
zQJI-26=8s4%NYwt%MuA{b1nBv2Nh7Kp30t{jx9?hsP1y#0b5R?VbjzI^uo;P#CpoG
zkq%0AH5GtemSGmB!oXEgoZPib>CIp;5?vHu>sgA(t=bK+3y4v&ibycXON~G;vBX6M
ztfvecs8*_P$Bfo1EJEk;HVF0~kDs&?algzu2k<mkz!g}hKv-9HYt<lF*1Ub%ewpo4
zulLF7vK4&v@MB=pqsQ#Vt1^qUQJZTVRg;ZyB0=r$<-X&TR@u|jv1&KKmYG!%2~uj#
zDFn>v#CpoGkq%0AC1%$<xX6qL697;YakMOwplHdxnLd$q&A0YnB*|@AB;oC_6=p5O
zDSkb|{NFSak?TNhHbwcm=nl-}X#?kWECsrL(vLN=PvZ)>0<M57;0m|`uE5(BkpBb_
zsZ#szo;HajwNaP*j#HXGNj(g<%#1mjW)5yts59YoqA;E^Y@~x4Uy0ehnawhTS^z*1
z!qKuwf}$n&1|yNB_*&0WL~hF>2`gY15LFAaE>k1WODu6w0qZHl2C9|nn=zYO)85S$
za0OfeSKwVJ@biJEJo0P@er!IPD==Dt2m!UZ?qQTjQoDP(?>MDZ_VjdYSt4NtY?)aL
zaf+LB3SM(Mv7Rz)q=QmjO?5d#kyN)VGfDy%MG;5KA_<C?+#8HUmf~wYOA)y(izKXo
zT|iVV%(_gCKrgYxMFp&<3>&Ccs&B{aMIiv(j-!CQmw3Op9ZP}k&!A(C{Z6Ja3qW)3
z|44@24T#gM4}o4+OUTcs*Pic1q*iS`?01j^f?5%)kP?i4m&?@%%gPm~yb9E2OXMn8
zqq<F@re;NE6kQQp7}uIf>|Ys~#2qQCKiSG?6xVG%Y@~6XSshZM|NSBJRusQ^NY)c+
zo`*H6XMaqnFI$P(RPi^t{w}XGNIy-k)<ym&)+BzBSCa2fmw%UH>7WANB;hoJOsUGV
z6p>c9^{@+wWmboj=%>@^8%gsBQ!lw^=x_2`0@hQ3Ro#r3Q(t;lt;DQaR0;A%9bjW%
z<A6!~ARoaj^ikP5YY;4-toyYegj$52S^#iVP5wRlM1opg<o=_)lDu?4Z4OT5MTNqu
z-2hu=Rz)OumX{iVUYME0ddjeo4oY<;CV)*lOGb`aY*u>0(<#vPj(EDMoUki!Tm|e3
z(KD-A6{ILqXaWK63{qQk$!nSEE(MVy69{-`*vL&jg-FW+396Ue+ojNWB6WFK)h(Yw
zamxY;s@J6=@l_GJ1nOT@D`<%YE+(LM4V57&Zkp*X6@e-fP_X3`YMW+zNr`zD))VOb
zcxIrwxdN_$E09s(obesSb>!KO@{FE(j`Y;*oqSe-zno&$@6M-IfSq?{|J^l{-QAyF
z-Xtavu0ixkO8q+Xp0JVTd1gJZfh2WKk$ZI}oPJ+tJdwIQtm>9ep}1v%1l8+Ok@%_z
zT>|wlsui@v0v8idXTHji6gSOumx@4@2`Jcd3bjqMy`;oE3+oAVempZ!-CO}zz!h)>
z1}Ts(i{c=7hrN#i;XZB4T|bpWPaoOKY;1qs4yu6Je>dl3yKi^*r&FZT1Ona}M4zPI
zc5J-?Ho_s#j7ZgldLUsQA#x+8&V)mbttDo#OI#F1998T6GwvBB3)&)C({6wbG*{1M
ze#TAIuadzVD#`1+PV)WSVF_4IkhDDPQdCZ%wrXD`nq^k4@}Mi=3Ov68T_2g-k2waG
zkGXx?ewpo4ulLC+jv0FpEW62lT9H{?#dq4wud2MMXbfz+iSs>+OUyo;g20+>e-{<I
zyFZ;Gl_n7I&LH1U2(u>=rl`wIcd3e0nn1v7K-QfHY%l4p&V)mbtwJKhEQ$N|aSR>0
z%m^k`fl3olO8!`upW>#O?ott`G64l!PNBAGwwIKcNh-7P)FUvaDB#VKC(yJkvu0I3
zfxm7$z{bFS88B%d<i^ZWAL`awgJ8$3=sn`?mst;c&v6A@0axIt3VdBP*r3n!F|cWs
zM2{#cGeaq}x$dH5HtJFpsWgFrcLuSCy-1j%E;HSwDpF|z0q+bOxyh#xX;~ma^^*I&
z9$P1(rvzn15l7WZZ-zjXn%*c`(3Ya6-2fYCo@LfVO_Gs49KK~Xs7HBK#y2UXS1n02
z%dA>e4)RaK46re<e+-zk4|2cE`uKa6E8q&OR3NRayRmE#ENk9AZNJR+sn`2t6~>G`
z2$l`+KCQ~kZ2Oxta2m3^`>q|lK1r!P{XJnL%?;&%w`EZh0!d0IxmRbx>GRNdB6WFK
z)h(Ywam}Ix0|}}Z4mtHCzA8dEnx<MoODu3P0d=yf{1-`zn`XL8MWD(A6l^(#+NRlF
zQevJ(Wj6KxwcWDho2*E%y-xAvU$*Qj_oSy$AUq9IC+Z5g0<M57;0m|`uE0PA{t#@l
zx$fd)cK1>hsWgFrcLvcXDYfk<t!bvaR79#wAmE*0BRBaJA}tFfs9tif&V(b5t&j>_
zUNeJQBA_VZXqsw;U}Axb38<4*L0gKt%ygHkK&1&N*m4TBO|!kE#Jo$aC(!xP%o3n(
zu7E4x3b+FAMuE=<p7hAG9r&^NXs*C;1<d}ti;>;kpH7iV69{-`5Pg#JV{1(_bZc24
zVHP)XbFsu%Kek@f$bWgNW2=lX{ca>bihG|_f$;KE`lRfgc0mC?THKDRKwz-ks#_fR
z-?A-=MAi04?$s8^E=V6vpEJLKUW({gv-PkwW;Mhq_M2SQ-s7@zC8Ae>>TF7>tD?Iw
zdqu2wt^M<ZeSox5?~VK*xo7<V*fKMCSMB`I%v(_^>?GDxhV6K=RaOK`%%;L$<ob>8
z_}4am=bNU<|HPWaGpv7-*OyDh+(8A>UnRPLkg7d%(WOV_%MGwIh-Fs6dkLL$ge7Dr
zv7R#QB1k!9HM3@6A>m`ee`og~Sl+z*v<EOtV<sO2yYGYHKX?{q0cbv;Pm*DlPVq%5
zO(5W%L9X{0ueJ-MRqY1YNaH-SDkMQ!L;_#u5h6EYW_h%pNM0URb<3wvT(uH2db=G<
zfpDyGd>U8a@Cw)!qG#mgR|xZ}KvBnX!Dcp*`&igAGq|)Yk)R06y`98*%CM@N5px0r
zv}K6|)oZSppUaXl2dZCHtHN(xUhRmO+Wr<J;iX%bt%OZ9H?<LOk42J{PI7Oah4m!r
z{(pP-&Lc^d<%!*^re7QkdTX)6K?@DgcB%AeC6GXCG%N{<L<`hLDT&euB~n}4#R?QC
z%tvTp1d1b4%#TtZVMPiAoA>V-?iDwWz0%`ho}Rzc2#>V;I_Lg8BJ5gbW%hj9ZngO#
znY<Na26Ss}&CpMPz*jAh-$#7Zc;vl3>U;J@?JGB1@mK=wDCaks9_ua5ZgQ-iIe(v9
zw_fV$zRlS2l(zh6x0UhSe{0(1%J!t4GN^k9Y1efpwPiVNw_4fNIbo7+#gqZvT9+B!
zL(j)|`qH)Xxmzk_wV3i!I>xkKlB_)1W!Pqv)!U3Ivr5O9)=Szc7xP2XvlU|obZfQi
z@?O-IDf8yjcB{<~$>gmVGoV{*YleOT1PBm#V}bl17mG&|nBIFsAKp9RJLbEWy`BF+
z<sJ7e)jJB5!}VtFv5lyw`_{PQDQ)@D?oHD!SGJk9`AiwqIkoG$liISJwp*=Wo)aeN
zYAjWDp42_`B->{Ep^YeIwYDiUOUIbjOOpEKFs1vg(_WJd$<|?~VJ)Us`j`QiEljy+
zQQnK%GG*L4$jXpRUW>)b)+XsAK;QuccKyhF{e2#jc6|MfywZyITiGjZ&@!(fkR!(d
zaZK9#eF|Kz>?Wz<fVZ@zJSc4r!1oyomHpy0wR+3>d)FT7>Ap?N7fI=uvfeex@}pgb
zZAMu=Gj^n19<rIT4VW_Mx`nLOqVA-&ET`>OE4!M`8Fsv!2X<?Hd=UHOaV#TtMYmMS
zYBA-dbc|`eJoEi-eg|)zc1jKNm8EAZ#tgV@Vai2|vXhm)4Vmz{?{VgA#h3w~R<<>1
zp+A4!_JBAh?T4pt&I2~Qk@B@GTlks2QN@e9k4ZbcxbC-F;C?H6s~uaH009DDf<XQV
z;PYen{3)+7<Dj%R5xvHKH`iFG?AueM%CUcQxeO?$`!w!2!7o4BWr5AOHSKa`n<?9X
zDT6wvc3pQ;Tb9#ytCd}y6DH|aOc~Iv_3^Fw<e?`cHe+Zbx}{Q9izzRqV@zwlu(Ip=
z<uIl7t<zqU49V7Er(rc(>0<_5wlL+QMR_l3%an2JAS**Mc{P?QTb;DrdH$zimb>4o
z=a{r(z6kCz?zghL<WdxY2NK9#=72aR?Qp<O_ockw%J$W7)O!d_?~$bDI4JGYDZkcp
zc*|;K<@~)_ZXQ(X>Ap2~4-Vb)z%|M8quraPU9N01ZJRn}&~*z>C*!)4+OnLsTdiQ8
z6DH|uELC<I+qA;Jy40n!l+`+>be4`Wt(PP#e<GP-n^9J8Gp5Wc9b;NAX{TJw4@u8f
zj2Y0a)vn8Xv9h-z3w-W-oH<)DX22(veRCSpDjrH;dZ^vl3;_ZJ2oNAZ;Ee?GM*!v6
zzbjWc-DlR06a4a{-J7Oeu53@*DT6wvc3pQ;Tb9#ys};<1!X({_DFeE-@-C#1?x80m
zc15>T%4#v?rF4vGy(Fm*dsDjKI_)*dkZc`x8n$B0fXf!9T(l_fMQxcfZXIN0NG5N^
zm;s+uwi|P6as31c5Fqd+2u!)HJ!m}g-X8QVvn>L5AyCfWyQ-?E`!=n6aOh6m*Cfl2
zc5j+?xw1WJrwqDo;psk7cT!uH({`&B%yYsd-HIs#y0tDd3jd{J^>eqB$JV@~_wv|!
zIt{CDoz5>&V0!wm?7zg?)x0P$F81j7@&%@Bp}SRX?P<(EKwM4(t!>E6((&vhF@4kj
z{^dKRU8^i5uf{*O-e+5QTB|jFawu8d+x(%Z+kP3cT2(q1D{FnT6|b-OFTb351KX7K
zDyJ+u=H(NQpP|yZ94|<_T-kEEOV2;d6x{m8^mjX{Ez4=Ediie1`s=Y!*?H2B?RCok
zfmZ&tji1`bc6|Rd@YikVAKS-=l+@z7Lf7%z)^kmA9@@2BC!LpAdwD_HYm!pgTEdTg
z&88IGdg@MU%W~Q)$nubzE8CtpKVqD3e(TnQ(&k(4KI1(q%g>_&;+V9<0XyBF@=qCB
zZUCF}KeQ3EH~4aY_^yqd+Q-jHYRhF(hONej)_ZH(OOi1ex;tVTR^x9z-NMr?r|zV-
zET=8%V~Ti%%Gx^b@m-v1#XAZ-ebv2VMyUu8c!5B@AM9Cd$e`}V(XMygF2>C3ZXnl5
z>Dh`Q18zurP14QXecCDow<^Yz(sk69<+N4(^(sqY^JkEA&)Q2ZtBvk9IlrYLi<TW^
zwOw&*+U3f2r7Z=wSwm)a9kpdSZ8`Z(S*|ln!)9~^B%L5YfWV4Cdjx#gc;vl3?3?x_
zZ7er#@mK<b-(-5MH}vCfK0Z~<J~C`>w|z-`a=LHV-SK?>1V3ip{INehTQOunccyRG
zJJK!>$%30v3T`vT%<4L7%W~SP-t8*u?uxE}q`O4nzjUmAu4T31CC898x_WENWm1N2
z#;s{DNv34zus2g?K(~dg)ndp?*HK%R(-!q9%e_uzSxFEeK!Cte0)IFvvAl04Fnm1Y
zyxID53+F$Cd(^m-y-knmYhO40N5bt?KZLG3-M8!Rcs_rEA2V<M*q@%&ctP6b%2qR`
zGmliI;MO*_kG`X}ET^pxY8_@0ZpKn&=ZS@XbGbja5w)z=Sav_O#{SK(Etg3dx*C6O
zy|<>lB$<+-!%o9$?EmWvL)IzpPAz%okkzWvxm4NaL<0yA__77^W95K2C~baZ-e=rz
zW%udzbyk%l#{qFn+VOy$?n}8`*-cW@zO1i3>Y%iFP`J-nsI1+q+PS};zxQln$e`|^
z-mbd`hw|JsWy+YB`KOKaY{ifPH>6#zY%AlrzZBeB$Mkd^wPiVNRqu9{b$3Nqz{hXW
zkMDNj-?dyVt4%98hOG6x-XBWKby9|I#*JyONv34zus2g?!1FDf*J^FUryVPMn=-ab
zTh!~2%-M{&$~Gs>5BPDu`K?<IN}Ipre4p{km3{m!fA_5(lXiOdeeO+ozm@IXfpG)~
z5Fl_7m@dC~-_Hl7J?4(ShjyW|kIl1>44bPC8POfC+x3nU{Fr(3&q3+giXj7TNV{Cw
zR>pIGDY&(c>FGLZ%W~SP-t8*u?uxE}q<ebsy5aA(PHk>2t2LG!Lu>5ch1znNl%cCJ
zwccCPUXo;u{;MwytC27MIr1U1x{lhioHnbD?PJ9(y{oZQ+3KX_&Oa@8y=BiqX@B{a
zdwS8@_gmSEwq-H_0$Tzfk6K%!UcLXAw9~8a<FyvN-^yNVht_!oft>FSh-1<Y2kdlT
z%GJtd9~oBH9b4~t$?kOD8h1RUW$wb6K0RwOw$32~Zb-XaSr%N4OfAnTt!>P#uA{ar
zr>*MUu6BI|FIASpZg_0XtXfuU>^3>Or5}b&E<4C-yW+;QE0yg^TMBNohRl54@k41@
zN&6a)t)CWfPWSPfD_!ED1a^I=Kh%zGh5!Kq1PBlyaGSvFBg5uWLq<G5-RFAtk)}W7
zj~O@r9F(4|7&737w9A!kWjyznf?MmDp01;|ET^sN-LA6kuILI#y36xTd4SrrTrI0j
zD>;U&)zw>DE|W5JGj2_LNirovhrO9H1G+6_trkOGx{lhioVKV>S?*OTi;*BefB=E7
zN8ncvywykE+XKICwnpG+f!Rlf&7y{k=uY?Tx;viFpWw&Ln?LraXDfybxFPLwWm_4~
z{iWd6I;N-Vs4dHBt9rMqth+0^0+Q|$h5ypA`ni_XhL;>e*68Z3Etg3dx*4~oy(F2E
zp~K!xnE~AvvQ~>BFI`7%Sx#Hjr!4n6m1QOIXaY}Pc8|8LuYEuH2_ha<pxgj9H~RN&
zM0Xp=oub8*m(nq&^(o1(>VG&jr8|>0<My;`m2IW{r&juyL7h{({`B^^wznY*bT{H|
zwRyA5S&PNW+N3cPyBuj)jSqh}!_;Qf^Gw;u%GOp>rt<}9mn+-Mdiuw2${To|^f`N*
zf7?3sGUWEkGV?>q`)&L9v3*Rt{*mJkPXmA7X8hDXPEY?X#dU?Q<Bx5?HOYBs*K(bd
zg;wLk?P;$`N@c4V&z<f6T&xtFj%>Q?s4dHBuOQ1q&dFC_mMUAFw9=WcgahK3wBH@D
z(|sx5qq3*l>%M|sZ`3hqr`OxSTdkD${9NYsr~786_M>{ppnUsW4-W0u*A=>s?iMn(
zVg0TAIw?J?@q)D1B&D*|jOqNoeRNyMS}n%BbRD&2Ic-&ct;({FcsPNlueyiZmkkkk
zP=PV~>h2JGHacZccjIW+du|uy26CO06}Mu_fE&_YlXP=;pSG^Yhl^9nC_AYw%W21~
za9M52#Vb~p<%Ya;C8l93#ti7nYS(4=Q$}_5)|Ts}jNOVc18zurP14OxWxJx=Le^?A
z<)!PWEz4<#%<j}*ud*yH2oNAJC-D7T<Abz4^4=cgEwT*)_a!jhS2?PA9f9$@%=xuD
zT<=+Z%AoFa->!E&rLCOlv*K1v8E`||<;u1)p8LylN?Oa)No`q9J7$GWz1!8(GgJnx
z$82SpGUTNzF%4TWW<Xa~yDmAVjOyyGE!RmIyA@*w+>rK~q??<{c15>^tkq)5OV?3b
zmeUTI-KoD`Wm#GfAV7cs0RpcjFum47pRrE+PpTd^?qzQ|dx^&s7_+VJaJ{+DcB-E;
zs5{-a>m5&ND`)zwxEe1=yIk37#&nMDqdcdiqdc9|mgTfrwO8*jpPr#IXgS8#HCtJx
z40-8FOv74C?TcW{fKR^|N{%U`x_WENbyCKz#Y@s&lXNAgvd#EI8_{hcYqgm2(sk69
z<+MX)cj~WKS(X+A2t2UBc+B1oO1tYP^&uknTiGETlFka`e0M+`ls4y@`;1qvEN8X@
z;+V9<0XyB7a-p*EJp26G9j?#K8!uD(yVHHU-tm;Sa;DFUTQOz84QZDv+sb(EFV87y
zEl(%4WjXDb6*~29S5MDS8MGcVl?~?^=hv>p^@Tq6j``G;)vim9DWjg(JN?H`TYjFD
zo~;-&;Pcb|oTQtZ%67%`Eu7bCv!={^-m$i~l6J`KPQ47th|PFjz@@UyN%I3fq@4GU
zgVN?NIp1fza%ICYyF4guzKiZN?zgi0^imZ80tDVi;14&YIp}BlF=>aJh~8t;LS?PF
zNsXx>V%KM^G;GC`0o~!cU0+w|I=ZKxl{0--+=?j!y4BnDj<m}|vfyTPTgY08@^n&L
zmeY<|p;Pa6m4v%urn2cgamZ^|;<<V4W$BBd<e0KbS8r{(PRiKTctP50k|Md9F`YyE
z=(doxT1<KAI%>;u+99($_1CK`OWzP<%6b1dDDB_A|4w&iyx+=pZon`C1a1=;ZkzVf
zSqG)fJ?}o_ek;3AudlPJr=#F|Z~mCH(|d1ocfQri#w^nvuG6p@?I1j5KzF)t*E^ol
zR?hTUaW!6$cDb_EjOonO@|=>6@^n&LmeY<|p;PZLcYOsfR+cwrNP@1!G;GC~0bN<`
zy6k?+sOR;r{fT78ZpD}ZpPzQ6vaO8g{^wh`{F&yIp64BFd+SPmKIsiAYwvc_iN_My
z^_~7$Tecel1PBlyK!CvK3$#B17&EIofA3jl%AoF`-mZ5%rS(rz@0NDCvg~6s%7a^G
zbkBt6CyLUtoOa9#-S#`o-G|wk%39J^$dCkGL21~EF$21?+I7h>WmH#hZMja$*sT~d
z;D)r<B;DLpwkx_VWUUrcUb>FjvYd9v>`wjFDjT!3AV7csfv-m3cMrVNN8Z~5ziqZg
z;Anv{1$2k&JrzwE)Sd3z^^T{sl{0--+=?j!Zb-Xa*;dALe|b(xYk4}UEz4=gtk9`<
zyLx(t%Aoa_tt?Z9ymTd|VJpTA=*nu>CC8LeUA?vCIw@nfV$6UW(q5Bvb5q%_=(dox
zT1<KAI%>;u+99($_1CNHqfiov#}Q~>OZj>ck0r4CXV7D9`zzT^xdCkM`=8s0dKzer
z<^C{at!KB8-<>{f`FT=?uEy<Ye@-$bLw849P1!ofziuzjws5_34Vn3@V{LC!#&&6o
zdL5EEYq3~aCOs?cTJhRqt?wUZm|F9gY3uLo%GNS@J#J4sX5snD)>F3LfBEIimtt!#
zZ&Ga;v-o`4qCWd=lKIQARM~mPuiNV%+sB7w`t7-C>!tmlSZCmm?PF@cK0W=r6xS8H
zj-T3q(<RAyXxDO`lws>}d)jM~TG@Ka*8BbG^iu|1ws2mnU1!rjwU28@ZCOd%tyVD4
z>t^lMSgLGw(n@E(P!EV>(vAo0bYIH%sBG9*%4?50C~bbS-f#S}l{Til?go&C)oA}7
z{geUS?WJ9R*FL89(RXx*gVXX&B@<WU1!<QnTg{lx5ACDdLe@%@oz#})v}0E2)H}>1
z+>8%xM6K)>AK%f<*#>-30++A4FREz868MS*>K$SaM!74rNn<9Kjv=j=Bx^U_jN6K`
zdYdq2Qt24ddPzIxVtz<^wqnSDZmo7*Z-u30%)I%u-D>kgGI=Y84CvN+nla^bSI|?(
z`loKGl+|L$OX=uN4J(_><jp9nw;4lbm5wg$@{r8kjJj5vQr?T&GGyiVuPj*w0RjYO
z1U}5PJxbFf@9k0Eqc3_N(-&R6;%5cEJ&m*N8oy|PoV;hw-@EoyPxq&fUnHetc%Gzx
zlIngt^DWbkS$w{-J!yvw>Yh{Db@xno{vF)XGG^X<+HSS^A(^}tLk4tfJ<XW%xhv?Y
zWBpUNRLW{G<fU|U&wMMJ%;e1|tG5|LW|fXE?edV!-Hf_cn^NA3+A?J2_pdBj1pxvC
z2pl9ZJ>3)!N-ynO2z>kTu<;g4FRl6gQpW?d-^<>1{bv;q;Qdu@p`5=r6>{9Kr~A`s
z%*@g;r1g@df0FvV$JQ659aF=6W$9UsR{D?umo1FBXwf|r9`e|_R9UK<^3s)<hSk{n
z-?-06F4%@_GhUE($l~4ma(Rz8v;Mh_$QRVqK7Mv;zrL(+?Wiq78#bTzI%#=G=B~z{
zTkmXTtFv?xAn@f2?D~=U`rAAvZGOz%XWVaP_v!U@Ry7{8?Ss<hG<lz~SlM_}y$3z+
z9+P&uiRe8hEmii-X=v%ov42-d^>lwajhR_GhO}Oi{QQJ)X&KX<NxPz~-e!%NSvrQa
zmL#`557f2V+TAnZA&;%Ch?&Z!*8J(?SR8gm0c*2{%q$(9<gb?bGkG)0>TSl5S*4>(
zyF4UwH>0lArj(tm>@Dy5m^5Y5kk;Aa)3F(|m2J+NACSLpdq5nM_QwNux-aD`S2pd-
z`r4xoN_)&5eGlIKR<@^lV+ar+@TdZRzG-6z{Y*b5?Q|2-drVrWtTjif9IkhjR1WHG
z)|i>4V@T^INqyKG)167XqO9I#jhR_GhO}PNj=7j0lAf&?GN4<lUEk|t>qpEfC3hvJ
zVKtV%7>3O1c3&hHY%^&yUXXUk;<J@)W}VuI*@wf=*;`5<+sDfG%a9CTjj8p{R<=58
zxikMX%mHys+CLqz(|sxLx3Ycp8%2P?jRMn+^IkaZptQN?-DliyW%udzbyhVTv+aY@
z=D>TOv07O<_HXVXPeb)|zv~3wKS_0G`nOCwX7N(;kk+jj+khd1I;VEsJrkaP9+s9d
z^XAibtIZF|<h2-E=a2#2T4`ucJySk+1*Ks#x}{Q9iy<$iqkFPi`4h=Z-i)$(n=xco
z>FClf56RrksB5(;<-J(hTle)_SDP(<v#JcJYn{fAzsa;~x<Oxz!0^RXs!#$12oNAZ
zfWUzQe`>kQ;d)m+<#gX>jhR_GhO}Oi^iNXVu|LB$qpaR$jG0wBhO}PNj=7j0lAf&?
zGN4<lU3brfM?AKss39+XW#hTDDIHyjY1oWzserW@@=`jwC#wb9OxhJ?^)_qB%+k@N
zT^^FTn^D(lQ_5FKZ5guiyH}Qkf&c*m1il)9A0Bw8kG!`Be%ow~z~KVr{JpE9db&TI
z#>^}oLs~CM`X?!mt!rj++lnCrF1TYZo?^;pkF8G{^Pj$~$5wyZI{z+y*{#FJ@6s=O
z6RQ7IAU|5fqY4b!*xX%ral`-Ajzwd7yW>&2?v6n9hV;$phtrgK-L3pODLrd(d)l?i
z)-s;^{=U7If?L~^-e(;@l$N!$LuPmC9cI?ujHSvl@mXPe@3sH<O??Bi)OwXehRnU!
z?~r!6vJ|x%AO3FU?P@dXPHM|?+M+(Di0++D!)h#5cAoV6_WDzPm49vHkNL%BwEq+9
z4E&I)f7?EOe424tq3f9bs`XxzWN6=Vne?>A%BL5ky(FoXt>pXI^<l2y)>U^>Tb9#a
zL6(QyT-oNtg#q6!w7+rlL22{Fd!O+Rl}*R&{GhbwKQupP$2+qAZN`)vz~;p7+lcNq
z@N|P8GqZFIX}u(=xAHOFnY0-%NIPcn`N}rawwuV1L6<FzxoA;tkF{mYxcRi*YV$)f
zc{OG$Yd_Pnws<Uo@v*jJHv}GDpxz<&Z29_I2$#D;ChfRg<S;vB?E9u&t}L}|#gqYE
z!R@;4q_!-l?N%$8=Y&bR6;lRuYh7ks-k0l$OULTxZmFkZ;dO-}Q)jnSe;4CADRVaC
z#<WuwE_27U?ujvjI;VDB-iz8YW!`++ZngO#nY<Na26Ss}&CpMPz*jAh-$#7Zc;vl3
z>U;J@?JGB1@mK=wD3{Z!cr1Y&t7p#NyEa)*_iftjBh8fct|$2AN4pH$j9b$#SGJk5
z4VW_Mx`n52g}Rg4vYfVCt?cTYFiE#!%7AXI%Z%=!CnI)6w^Yh%G3BLnjA^|jS$VX}
zu+1o|w;5Arm5wp3m$XwZ=7*$bE5;1y)@s+~y{Iiy=FO+=R+}G^$y+gIK)2S`4E+QM
z5Fqfz0{K5K7LO(Ho742(8~X6x3Ewf_z3gpx$308+&I09dy_tV(BkJkCHSTyyTYj{A
z)3nQ#ZKiELQwDWT?Yi!ywk)UZRx6n2gh{#@OO>4`bq_tswi$nDBT8AVZOY8jF{bsB
zq<%R}>3-|9*Ca!-b=YZGi>Z}9X24|&Q!ZMR_oB8;8Mh9yG9;7NVzIKdN%{y7cmRQ2
zKQdo`pU0#fUw<R7wBr3%_DUPH%xehb$Z<d%lQzfO`;6tvZju^~+2uiLa{#{2Sg7n5
zr>WIj&fmNCP*3-5TKC}4Jr7)yEI-=4Y1-w=_N1LM=(>fcZ-u&(+OnLsTdiQ86DH|a
zOc~Iv_3=UMlgF`)*cIJUDXYblm(nq&_3|G7Zhi-EopwqM^OdD%E5;1CY+=epi?WlI
zy$zZ0x$kl2Y{i%XpH{XtX`w%V-S&VuChdo(Z_WcYypi&?E6Z2M0dY*);eeg)OL@PQ
z?W^A?0t5&=ra=A(;PYen{3)+7<Dj%R5xvHKH`iFG?AueM%CUcQxeO?$`!w!2!7o4B
zWr5AOHSKa`n<?9XDT6wvc3pQ;Tb9#ytCd}y6DH|aOc~Iv_3^Fw<e?`cHe+Zbx}{Q9
zizzRqV@zwlu(Ip=<uIl7t<zqU49V7Er(rc(>0<_5wlL+QMR_l3%an2JAS**Mc{P?Q
zTb;DrdH$zimb>4o=a{r(z6kCz?zghL<WdxY2NK9#=72aR?Qp<O_ockw%J$W7)O!d_
z?~$bDI4JGYDZkcpc*|;K<@~)_ZXQ(X>Ap2~4-Vb)z%|M8quraPU9N01ZJRn}&~*z>
zC*!)4+OnLsTdiQ86DH|uELC<I+qA;Jy40n!l+`+>be4`Wt(PP#e<GP-n^9J8Gp5Wc
z9b;NAX{TJw4@u8fj2Y0a)vn8Xv9h-z3w-W-oH<)DX22(veRCSpDjrH;dZ^vl3;_ZJ
z2oNAZ;Ee?GM*!v6zbjWc-DlR06a4a{-J7Oeu53@*DT6wvc3pQ;Tb9#ys};<1!X({_
zDFeE-@-C#1?x80mc15>T%4#v?rF4vGy(Fm*dsDjKI_)*dkZc`x8n$B0fXf!9T(l_f
zMQxcfZXIN0NG5N^m;s+uwi|P6as31c5Fqd+2u!)HJ!m}g-X8QVvn>L5AyCfWyQ-?E
z`!=n6aOh6m*Cfl2c5j+?xw1WJrwqDo;psk7cT!uH({`&B%yYsd-HIs#y0tDd3jd{J
z^>eqB$JV@~_wv|!It{CDoz5>&V0!wm?7zg?)x0P$F81j7@&%@Bp}SRX?P<(EKwM4(
zt!>E6((&vhF@4kj{^dKRU8^i5uf{*O-e+5QTB|jFawu8d+x(%Z+kP3cT2(q1D{FnT
z6|b-OFTb351KX7KDyJ+u=H(NQpP|yZ94|<_T-kEEOV2;d6x{m8^mjX{Ez4=Ediie1
z`s=Y!*?H2B?RCokfmZ&tji1`bc6|Rd@YikVAKS-=l+@z7Lf7%z)^kmA9@@2BC!LpA
zdwD_HYm!pgTEdTg&88IGdg@MU%W~Q)$nubzE8CtpKVqD3e(TnQ(&k(4KI1(q%g>_&
z;+V9<0XyBF@=qCBZUCF}KeQ3EH~4aY_^yqd+Q-jHYRhF(hONej)_ZH(OOi1ex;tVT
zR^x9z-NMr?r|zV-ET=8%V~Ti%%Gx^b@m-v1#XAZ-ebv2VMyUu8c!5B@AM9Cd$e`}V
z(XMygF2>C3ZXnl5>Dh`Q18zurP14QXecCDow<^Yz(sk69<+N4(^(sqY^JkEA&)Q2Z
ztBvk9IlrYLi<TW^wOw&*+U3f2r7Z=wSwm)a9kpdSZ8`Z(S*|ln!)9~^B%L5YfWV4C
zdjx#gc;vl3?3?x_Z7er#@mK<b-(-5MH}vCfK0Z~<J~C`>w|z-`a=LHV-SK?>1V3ip
z{INehTQOunccyRGJJK!>$%30v3T`vT%<4L7%W~SP-t8*u?uxE}q`O4nzjUmAu4T31
zCC898x_WENWm1N2#;s{DNv34zus2g?K(~dg)ndp?*HK%R(-!q9%e_uzSxFEeK!Cte
z0)IFvvAl04Fnm1YyxID53+F$Cd(^m-y-knmYhO40N5bt?KZLG3-M8!Rcs_rEA2V<M
z*q@%&ctP6b%2qR`GmliI;MO*_kG`X}ET^pxY8_@0ZpKn&=ZS@XbGbja5w)z=Sav_O
z#{SK(Etg3dx*C6Oy|<>lB$<+-!%o9$?EmWvL)IzpPAz%okkzWvxm4NaL<0yA__77^
zW95K2C~baZ-e=rzW%udzbyk%l#{qFn+VOy$?n}8`*-cW@zO1i3>Y%iFP`J-nsI1+q
z+PS};zxQln$e`|^-mbd`hw|JsWy+YB`KOKaY{ifPH>6#zY%AlrzZBeB$Mkd^wPiVN
zRqu9{b$3Nqz{hXWkMDNj-?dyVt4%98hOG6x-XBWKby9|I#*JyONv34zus2g?!1FDf
z*J^FUryVPMn=-abTh!~2%-M{&$~Gs>5BPDu`K?<IN}Ipre4p{km3{m!fA_5(lXiOd
zeeO+ozm@IXfpG)~5O_#|-RJ1%yPuw4yx*@6N_)&5eGlt$W$k!8`^d1l>W~rL;ksS#
zIKhvZH~$=zo~;-%;D)rzm2G7__m_fO>zJOdqqZ!kt?J#bvhJ?v3P`$-Z|E(5w{?1&
zo6kSLmF?Fh$B+?Sy|v{sDMMFdYQ0sXHC|T8fS>E>(k>6loYlzpL|Ln~4Vl$-)RyJ6
zS#@k5E5)aGHI^z{owVHfr{%7<>^UgyFW+)cFIxM4D|^wlOeR2JOJMl~wl(ub{l}!8
zUR3j2PQKsD-g4L0{!D?K?+%D#(hdjgbYIHV%4Q!KR@WU{?|I4Ybl)0xJf&ss!kIoj
zYcaOYAp>qmyIffoT#ZaE&nc~K%&e}Xwk)Tu>fNq(eFZO7b`~lRP$_paYFTYcx5?Qp
z{V-(ZvV*L)D{f4?QrWJwrQkMe$js**Ka`f0v_*Z&a-CTkHsg5#=X6<Q+MH&<7bmdm
zJN=8>m4XQnAV7cs0Rpcq(2mEmj|`h>hK%SA*X_DHp3k4)$IP354oc5f3>k1k+U3f&
zGM@WO!L4;nPuEdfmeW@CZdX}%S9Ap=U1Dk<g+CpeQOjymN{%7xboJJj%cKn5j9b%Q
zl1$0aVQ;3)fNl#}tHqF)uA{arr!DGJmV1@Tva}#TfB=E7N8ncvywykE+XKICwnpG+
zf!Rlf&7y{k=uY?Tx;viFpWw&Ln?LraXDfybxFPLwWm_4~{iWd6I;N-Vs4dHBt9rMq
zth+0^0+Q|$h5ypA`ni_XhL;>e*68Z3Etg3dx*4~oy(F2Ep~K!xnE~AvvQ~>BFI`7%
zSx#Hjr!4n6m7UIOWj*mY0^gp-$JvaXTm<qHL_DfMxdCi$^zYk<?l$oByO2|6mX0y4
zPf31Ne+PO>cP4Gd?P)*WZRRW6O8ZZ(^f7}vr*{46?Qv~yLl)?6#NBGITv^LCCSjK&
z4Xg3t?`D|VjC!6a8(G=fYRYuJAnkHxn^{l)_)U2O&yzl9Z}V?kr(TBKURh>-NO`|)
zA3wH_Y1cn;{NZWf@7s)@+Q;eX-=(;&&~^N=4Y(#b5A9m6ld{lie7HUBHA$&#HRHLn
z{hy1Kg42;rcOA85Iqel>dB{2W>dR7PtCLnb^ObNw9Fz9D19rME<$F~2bbH-b(Cdvl
zChhck8+e12#;lq5e9AAbKizY&8tq5*kOBGjxgH$audgd~9o;QtY{U9n`E^oyR^tU}
zuSrT}s~OYzef#LPkhNNjdFeW8%W~SP{(6-SsZ2bUK)%uh0Rmr)z?e$AJH(#Srwr<D
z9PN6~?V{X3u9LFjR!kXiL)vSSZtm{W*7f*saY`9wC$(ic?U)rVt4+Ch#mchWke9B+
zG;GC~0bN<`y6k?+sIK1Ha-Ed1TQO$94Qa1Qy1A)rS9Dv*S}mr$bRD&2Iqi_yo%-ul
zmZb#&0tDs+zMpG+khVwO+k?DCU-mYJFS~rz&j?H(pGanUG=0GW<GJ?pYj?Qbv!yA6
zy3>8T-tm;Sa;DFUTQOz84QZDv+sb(EFV87yEl(%4WjXDb6*~29S5MDS8MGd=m1WA1
zm#)M#Y{i%XU0LnA<d`z5tGBjXCuQtbj2Uo4+G~<-ZYtXq-4?P|izzQ%M{QY7J7jjJ
z{(6;VX+eMh0Rl$}3`ZrF_bml-QhV2E|4G%u#=Yz<2Ql%O0%Nw-9j-U`*-rIS26d<V
zcD>^%ZRJd#6<6a0X_qTo&6v)yeU#^vbd;x)+OnKBtM=+0=F>A&1}(?fx@IfOlp!x&
ziD_7iseKWQ8Sv>BL&-5^R9A0pxlYR1wRlO|Ym%<yRJIv^Xd}8UWUUrcUb>FjvYd9v
z>`wjlD$CM>0D%V<7?0W8L1}mWq&`ICek(hKL(*A+cYoOZSj9nUbFR71Sgh<eshrsk
zh-1<Y2kdlT%7x0t^HWcItxqaxTa78b-RZtv?|4dEIn!swt(Y?4hP2C-ZDl<7m*<qU
zmZy{2vYd9z3gwYzNb6<Y{CYEHDjUv|&aaoH#&gq-m-E1`tTw6Sn6lFIcVYUEpSJuw
zDLq>;X29pC{W(cDclVLw`4-M=wJN5R^1NehZzb)J*`0bBk`bHnynst(o0H}Td`LO(
z9|xt)Uvj?Bc;(85V|IB^+I$z?XWVaP_vxi70t5)$v%o<=(~n6z-0eHDTG^PgBX)hp
zO2bx68PFZB+x2yYuA_VESvk{Z#jTh!pj*9N??}5mBnxgvw}q^gC{HJ~WjXDb6*~29
zS4p@lW-H6gAunBtX;_U`&X@sRS?#*ym@=xXx3*j-W$bFaAni3tS8^)bjG>L_wve@2
zOnK=#YRhukA+tO6*Q+c`-w<QUdH*;l?ccutPIqR!-^zAwz%T*?ZW9=8oA%OK2c^wD
z?>^&xE4xpxud}MBqu_gQ{+P7Wdv9}hzSYXcEYlsX)36%tAUtJ2ce-!aJD$>3&h%Mv
zHC~W*xw6%a>CDvfoRW_6bW&TE(~eo8Q|~Z$eFZO8mbHhxbS0)?E5;1y%4*kT_ftka
zuXpWFBr|p^#tiuUv@4ZuWjyyk-@<vV);gu<dB@t`x{{wydW*_Zm>@ua009C72oNCf
zbqb8xc6a{X<1l4VcTjKFJD$?|C#iQ!yIfiJu^HvTEi<}j!tA8BET<hazT19>x$Cht
zOUzc5jv+5yiD}r1F$21?+I7h>WmH#hZMja$*sT~d;D)r<B;DLpwkx_VWUUrcUb>Fj
zvYd9v>`wjlD$CM>009C7z8ZnwJ@8H+d2bK=w%HniqXotk&>gP#R5WE!ce-!aJD$>3
z&h%MvE2a#%A?<QyTN%&&<vAs-<>{ohET<i_LZ{yC>ggFOgVtlVvP>EB(v_Hotr#<)
zE2~|X98*Sh_12c_q>SB)F#~Q$dri{KO=Y{H+d|fAG3BM}s4dHBhs^HOU$3$(EeH@G
zK;Te;as$|`=AYY$dKzer<^C{at!KB8-_6|0FOxEKHEvJ4R@rLG);a!ldwI5nk88EI
zp?y5>Slio_vE7ZhsMjHxvlfe$Wzt;5Ym2qMf0$uv&10rr-lQoPWh1p^%(zV2j@#3Y
zS$w{-&9wjW%kl=E=X}oI>i0lVuS0IG>^$+;?e&lC<3lq2_T04f(*94ZGw{duF|}Wx
zp8j2m>k3`RPi?^IlH@$JYq?I!u=Th-?KMfQY&~V`{r+_NDT6LsIIq>Nv+1AO$F-xj
ztfcK$E12hXv-WB%Rkk{5r88fs2gEUH#{+h{FXekwHtZ|qwMQM4cHdp&wKw}Y>x~)Q
z-FG%;w||d*%AoG{(yqU2A5;72JG#TcY5As-iL3E~w9A#PW=!XY_R(!2YbDA~YRhuk
zF)MWH9cB`4#)mdywzAEc1`r@XfWVsy)H}qUbmgwlCXJa`I)=1flC0fyGj1!&>TSZ9
zNu^^*>m}`&i}@kx*@__py0zMMy%m<0G4tlrcB{<~$>gmVGN4=QX~vY#T|rMB>z}%%
zQdWy0FQub9HLPqhlQ*NR-ewG$RXVz~%R@4EGwNDxN_j78%aE1dzp`W%1PBnA5%@6E
z_9#t{ythYrkL-g00RrzNP|n}G^48P+=`?0$=@`;_Nzy+_b-$gNVVhA_Z!^ZsDjh>w
zFKNeI%nwP=Rty=?t<|o(XTtOE;Fgv#^XAibtIZF|<gFMopj+!{#+1)pK~Ej)pSq<|
zR*NAorK5Z1TiIkLZ$??Y%@{JPbaZK#hh*+%)V11_@?O-IAuGRsWyvZC5FkK+0D&)9
z;QKGQ_N~$%d2d^L*Z)oe<@~*wH^=>Yx<8%9%q$&4S}#fZC#lbSY<)r6F*VFrmY&sU
zr4Jc!*}|BM7Tq)9A&;#~m8H5VFI|agSdG2^jr)w`f^En);{|DlEZ)5@m-l!x>z~_*
zd_hg^<7cP#>&pt)j@mM`Ve@IPla_~M?rQwG_0CqdI!h-30$;wst{<7Nzs+OP=EvN9
z#{E`ypI%>QRpT++J}7NYllK{~T-o_B|Nc8YChhe88{L_4y|Qxb-?eHz-JeclW|od2
zt(PP}KOtON#&l=Wt|+UwSz~6Fjv=ij$!*UAb*;8`_e^-mV{0p7wzAg#$>UfYc0~be
zvxdwp9i8N_miaSzGs^01#*kU1qf5IyBy%^TuGOZLoviFF@A{ZDWzvw=+2Yf&8MBpb
z&YB;PzixX#9Fz9P19rME<ttY<?aTVwqYg@Y%pH9X-u+g#r+Q-u5FkL{xxhg`(~n6z
zJ>U6V{d&E!a=6}AdpW4LSz~6Fjv=j=B=uo$Om`;jin4l}HD+e%7}9!4JLY13NP4zn
z$bfFGcKvXVt@*a;HW{!MLtaWp_hhwTn@OATg0w>xpRH^&>(oYcTNs|El&_MNy`}Uq
z^U9<lt*=~Jmb@W;dBdDnm~u?oKfOZbZ?nYxR`xdgwJHGuPXg015(lL{=KQ^f_<k$f
zQ@t_oBQU&AnoqMFl=kVA|7kUMaJ^btIb3fRoCmgYP;YHxW|od2t(PSAVQ)<LYJnM$
zctP4R^XDr|&svPFbI5?p7RFq(IQ+47Y()(1qg0l*DKA}#Y1oWzlTYu;kXfapd*)mD
z6Uoh#v#YnpVYZ`7yF4UwH>0lArj)OemA$>mV{6Kut!#5Y1`r@XfB*pk1PBm#Sb_3D
zvTLX1bl+x;nOQo9v|f_*Pg32nKf^YotlnmfnN>Q5v|iGVxtJf4o~;-%pj)e5ch7|9
z-^ME~W9H4L?N*x~lF3^!WI(sp(~K#fyMmrN)<1PirK}c1UP?#zWVN!%Ox}#LdYdt1
zR_W-{E)U7v&8Ta&DdoMWEkjm*|H_h85FkK+z}F)1!vk;hk@xn%Z=0<VI9#Bdzjsws
zPxq(On3<(xNb4m@|0LzHb<HepTQOw71$WHFQ%w2nvGqw~{*%Ync^9n&2oNB!ATXqT
z?ykEq{&f1Mb}Smx+Z~VEb$0}+H>7V)Kb)q_>u%-ON$FXO+taR9wwCeS_xJ6!6x`aT
z^giqOp|q@}9WuL9?=Z9OW-L{fiO&lASjOgRr+@sWzJZywUgeM>bMN&#q+PBoMXkn%
zzngix+KjrB+OnLssE;Y4duP+I8cUU(C;h&?{*+(kU)%U&ez6(t|HL{2Kcwp4wvQj5
zW?WY2I;OvBz1Jie+P7RLJ*~0w=>=&oNor*)`95}im@Bw-)t%Iq<+N9j<smm$wmETO
zz;_GnZ`^!P+I;ceXS_pY(=j_gDDC+V&5zmf-mK*YusQMjHln)?Jl){O%q$&4S}#fJ
zt$a*(CT+$G(vDetzOv1<?Itp0&}9o_E?Sh^V{I8TZa!_d+We4AUX6vyvb1<Kf$`Bc
zWIqHRTcF+{_U!liTL_oCLMH9FUF0x3W$gQ=U9K#(Y{irTUBT_T?xeOXr|niNnCFB^
zx)oCfbZcE^T;7-Kh)c)n=WeN|W8rm$Aya3!RDT!aIw^BD<Hod87A|wgwC;&9gF2^n
zUEYh@GG*R;+HSS^A(^}tV+M3<ZOzb6fWTKRkl#mq)Oh5*J?eXAUjzsccpHIoxZahf
zp6=VU*+-fw>s^y9KiXy3X55-~xw6faZNQX4*DYkN7Ii1JWjSrPTG`cf&amU<Jg{5q
zGO2s$$%tLiEtRrbOnE6CV_GjsRvzs#Y%|L0ZN`*YrDII%CGC`p`621qiZKJawc2%g
zFKWw_dGl$z)#is}@>Yx)(5<yKLq7om1PBlyaQ^}y?!UyFD}3a=-Hc-5>k5>^_2%+p
z8&Oa9t#QXw+VZ2_o2Ff^Y%^{1nKGzzYS(oqwPiVNw_3qGCrr}SSgPzise9;2w$1oM
z8&S$?ZBu5Jjxnv5B=yT-O7~l*y(Srwt;0^kT1>6<F#|4Jm~zpgyce})%D8oql_8nD
z7K@dwP0~kzzyk>E`jPqi`#dJ?`1%`pr4{eDvRB%mWnM!dM~(yHn6x?G-e<gWWy3MM
zJSc4r!1o!em6h}Nu07P#eVf)jICReg*Cfl2c5j+?xw1WJrwqDo;pvA)-AQd(PTQ?k
zFwY5-bStI|=+?T-DEya>)z95hDXYblm(nq&^^)Xw^E=3-T~StVv!=`}9b;NAX{TJw
z4@u8fj2Y0a)vn7<R`xbzfzN%9GiNKt4EVINtw{_0`Rld^#4%|<JbiN>u;GoAuU%Qb
zIu3|q(hdjgbYIH*t!!WYMiC%DfB*pk1imVPKRobmA9-&N{I=N|0RjXF5V%8u@eXTx
zt&$#jZ?9!!9RdUn78nlB|CZ?=d2es&W^Dol2oNAZ;8TI|ZvV5OPb>ZW>qp+(=WCcj
zfB*pk1PBm#c!BA=;TOO8=HGvpzkKqW-+cR@reS#g>GW^M-+cG&e|~B_{oB)jerl<o
zc2WKNr+n8>ZC1<hG3{lA=~6^Z(rWoQ>RQKT(%R?q7OyFD)ka@e__)Q@y(R5s*qFcK
zarg0?)3?)U_%^kE^FN*b_4teLo_}ipXvQy2-&`8o)%esh^J&jkhxYeglJDnFZPqV7
zrfrFa(|6<PH{U(Wm+YV9I_J4Ip0BoE`jqXe#dU>`TU_5;U&K~A{m%vd&G27+`1arY
zaLnK6cwWfCzy96nZ%%)At>Irz-<<v;2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAn-;4|Mltje|>t2|L~{N>6_E^{ps}Yhrc;Z-(A}4=U<FJ
z{$JN=AG^Oh{m=Qu^wWR(_Vn-m??0b@_f5O{b(;Q<G!3ok_qocb>0jqp*HPD|AAZrA
zuM^Ls&P^G;bK=ZeGfltxfBy2Xrf>egzx>q?(_j8_`rS`|`5#XEnyzb|zP*%sZTh+T
znWodf`yapgc|+$t&Ww7^rqA5aYV|X9%`87N>io{lz07<C{q5=We`e@^+de-0roDV0
z<G*Pir@v|+AM%U#wK>}~Gw~~Jn(_LABxb6=i>4XEDL>$r;@jbm|LZUN&c8l=TfafR
zt=~pFoA#|WGwPP6scmJh`h9Ed+vC2qzRpqoSJLyV{Xa+l%U}MR(_j6+fBE%?(_jAb
z&G#Sv@*hrr^NLL~-yrYbbn}L0N}XA2X4Jl>-{u{=-qudv{V)Ifsc-sY2F$EAQ^dZe
pnYC_h`tMFTmHn&s@!y|+bvpgA{V(_D-?uw<;y35R&^Q0v{||^e_b&hd

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/hit20v3.cdf b/FPGA_firmware/output_files/hit20v3.cdf
new file mode 100644
index 0000000..65a518d
--- /dev/null
+++ b/FPGA_firmware/output_files/hit20v3.cdf
@@ -0,0 +1,15 @@
+/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(10M50DAF484ES) MfrSpec(OpMask(0) SEC_Device(QSPI_512MB) Child_OpMask(1 0));
+	P ActionCode(Ign)
+		Device PartName(VTAP10) MfrSpec(OpMask(0));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/FPGA_firmware/output_files/hit20v3.pof b/FPGA_firmware/output_files/hit20v3.pof
new file mode 100644
index 0000000000000000000000000000000000000000..ead9036f1889fedb3eedb6c67e637561bddd0aff
GIT binary patch
literal 1450250
zcmeFa4V)cCneYE}PtQruWJr1@LpTYT)R|0R5&}610TN!4n#lxC0$EN%l%R-1h!PMb
z%c2|PB{jo{1G3)XMK%a71HLS}{`Us-Dx#9%Wxc`muY8off}o(XyZT>ueZ32alKXqA
z`ka}8B*3cozxQ*0mFeoL=c#(?sc%<TSNG|2Qa$Y?5s74ykJlnz_nvbuzT`cBW~vvT
z|E{+qzUaJ*&w1Co-hQ!p)7vlpv-2-{w^_98$VEq%P0xGIzi_iT=Gd|+FI%{H@xsOB
zMa#_TYs{(VU-EXdYV-M*psd6)1tu4j*B)K&?LKMA(j}`-mj-Eq?2Yff<oru6eEVjZ
zCK<9C4F0JvAHMOHs8w3bbQSt=H>7)BJxnMw^%Io~U%kqHN=$lgKT4`dfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L
zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@
z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c
zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq<X
z&;+V`PTsS2&*}$P?&&%BXNPQ*KeYYVVDD!r^BlHcya@sOALZLW=X=#(giZ6h--Yc9
z*p9`v9ovoAred3eZ5Ot`#`X}lN!ZT7re#$&4V#wv0Je`|Q+)%rQ?MP3?Qm=>E<Rb5
zf#%P}_D*aQf{cYdV@ag4EM$|KG$dY@ov3_8&X=B0C7F<`Rgf`p5Y<bmCaG(Yu=t0d
zB3~%vyjY8>PJ{I^qF$tY#^wocAZf2#3fh0&jxM9P&1{AQk~V2?Z-+!f;wvGM<qg<+
zOV%c8IfU^kZ9x4T*N~OoAc8axq29~mcDo^O;Si`S%zED@7E@Q+eIs?bMM}k}u%Vcz
zv>{)hw>Ko(i?-?o8m+znkrqLfP)xJENLp0~bM5Ly;Nug}*^rQ+8Pip(S%yE=rzn!E
zGZjLNp!F))&N@p|7-kd0n8vHe>s6pN^DwTSN^+ZOf1F0M&DhR98<B?U#4t{iYket^
zOIIU-niGpx6<pm`UZYk-v)Wc3YGUkFl6#>Jjnh<HB#I$=)0+cnU^(k7ugCta>rnIT
zH%EG4BDE1}ZrHHljnE_#`POP0h&NQL_|xLPwNMi>uYpzUWkPFu7;3E{AuTdk^bPs(
zR;`|OmfC{P-}qV(%fkqx8bU(k``^tqx*M-S&6#7WT7|EVj-nN5gXVvPnxms%NANYV
z_ny~V6M6VC)jayx!<xWw|9*}_Il|^YtgHHe+R%TAB2{as5ndPAe+Z)Q2USf|+e7o+
zypmR|6V5qas}hwz{|yo4DC2C^%a1emtNb{Y)fSq!ry^LZeZC5!e2%rbSkLSOL~elQ
zrC<7*-FB_7&~3ZdB4u%OU;2$0zzo4!XjZN2?M2N-k&o!X*0w~tEu_5@Tl<yQjce^x
z`0+y&-t(&{m~27t)oY3S@A27M^b8LC0WGH@yH;c%!Z<wORLw@x4S^4+5j+T4)r{3p
z|1z%#HA8b_UWA&p#-#<5#(5~d=Q$Uwr3gM%ODLyt0UjN2fbRl0J~*a8YrZM%oNAQg
zFTI~NO{gjFK!GdY>np0C+FHLv*IYBC&0Zt-JFoIJ``tA|urpmH-#^FCkoO~x09zP*
zKD_i&*!vjrx(52Mj;T~r3%Le0l}1gI*L)L1FTLcntkDQzyv;qinejD4Dc{<}YkFQ=
z{t1cP&zH3(R^<Ns@*@`PjBicud~0`YyyZ2o)*APRqI-#JnsA(PARZhTz@N6$4%c(_
zfC?c-&;ip5?XE9*YXbvUBY2HZpn3RbyiTKmfvX0t`oIUYh@KC62y^XK1CT=eU})_?
zD0c1ggkddj?Li$e?P{~;r*CO2s&i7i+FCtmc5~z<n*926K^yrR-VGJMqK3+hM!Ckj
zsC}+#&EMqy`L1eHSEJy`M&#+IwF<)U#Ng`$O<j8v!tk)#+yt9>7#<GdaT>Iyp{9Xh
z6p_QM=j2shJFY?GU&<AFJXP}@BryG{^iH()o7z;UdtWr4cYWH=u3NWOtN2q2SC@hq
zF^X?haZLkTV>7nbK&Q$Npm3cA>OmGXsx-9;)^k)vcL>^!vdqtiT&g?uV*r{b17S$c
z!9U$0KBqfqGVDSa)6{GFwlM$tn!XhjZC!|H&mNVI1&Ce@W_%r0tPDY=4qNVDF4diC
zMzFmYRO2*088l=5jnhNrYv%sFOyi*4^P<;{(`a*gsfXtwU|t&^M4qc@RPR+y2$=ma
zU;a?!v(swza<Rx4c8!})v_|*prl!@XQNfte(q&&Iikeod7(w&nyzsI-@<sm-ifT7o
zKfW<IUCY1Lz1I3P)*iL;e~7NT*I~pTi*e;&Pu+3VCML&*Ymmni)ql*~L;EqVoPV!?
zDR-aY<$c~~!PlwSUz@Mf)E}z2a;$9oLs|R3+s=C~*?0e6F<xKq7~9|2dA+vw?dC+y
z>uK}#%nQ0){|^S`_>WKh2P?DM1Ol%%UiWwS#|-V|V7`v==*A4a?$qy7_jNb+S}N=X
zg^t%V?aM1qEVxh36F5$+^Ky%?mUpjKU_bibr|y2tzC!hCQ^=kgkG-IH#r*mT>lC~e
z0?Ki0UeF_w>RneoSWVTA1Crwog&)Sb%8L#34qFJVVrxmik85>bKK#>KC08#W)tZDu
zVU(Dl^L1^#9GZ3GeF`h$F`wcIebH*Y^}4}u-XCvwLN^^ajO(mE+3|&H4&`>>T`tD$
z*Z)-E%YE_%vvK1URgC^266c>(Apt8^cV6UtteFT~=3~u?(GD4(^pVwi4h|rpVS>Zq
zxTysnoJdEw=M4F*6?JXh`SE7e9R3ho*mPG9u!xTe>adI|jKnp4Zw;~y)oZcp(PpUU
zG^f>2Z=_xo-sqodYQfbKVegdVul<7#)!;#(8<HU;hkP@wtx0QZhE}v09KenaV`5`a
z5&;JgAM(I{ucQ`j$Ihjw?WrY_*(7VlxI^z?Y6yR+>5#l`c0F8g)w<vnJL!l8rnN3W
zL245iwZ6@9K0yg<t>`m+^8GdgsM}%Uc*OWl!(wl*{-HYhjW#Fxq@D5Sf`d<~pety3
zq(hs9QQM1VbDy+7LvU!!r`|-{tosBd>I(kqK22$ZnN&S7@JWnX^)(QWjaR4<jE@D~
zS4YPUdZbfqApksr@2VHqjRrMhTTg{VUf0{r>p5uroM1wcJcipLz@gw%p0E3aJj~(G
z`8ZdHdbw?1*W{YouD6zO!J9Fk>hqA6@M2Rdo9}(&xkGt9)#T#9akqX{=~T?{`w$qr
zPUTkegQ~fEKJ-diE~)QaJvEltn`}(G@6`BunjW7=_Em!mCGy>?7T<S)af9xah3dnw
zu2N3h|H@}wT{w<oUADi(>n*=OTmOl5yLEoluouSl@fJ$t@m>l}(ElHn`2%!EIsJU-
z|G$2_eKfr<`96yOZxNgO_SH-}Hoxto$ScqEv4U<a`JXBEM{!HX+gJbn_v_{##j)Sd
zrQg5yUe4vue0twz_ddVvyZryH8s+r2^Ik*m|3KGF_ZphoUy<Lp{{C#gn(o*CtR)hM
z=oR5x?|X%4q9E{d6NP&j)DsK*{yDT;Z}bmz3}35L8~ocWd!O0&$7}C3UTdp=%yPMB
zuY;p~9q!o1eHY#zFRhjAb$spH-d-1l`zyW=o!f_ef>?cf1+%>$Wjmqbt7QBepnJFT
z?0&8du<BmLa!}jXRBE4v{>xW#)n4puxL_aEve)Qat=rYtP`*}nA5GT8>eI&Kkel#$
zqNW|UcbeX(QLEZ<q5j}woXm_%zv?9TilL*G^X8lXM5J^5IBR=Lx>pKcCVE-+mF54p
zNcP&%KVHkq?yi5FXx~lDhFlQt?KtkObWIj&)pD<Y|ElA{n;bU`_ls|DO1p2T_M@s-
z`qtO#$yX$l?aPCExnRHZ(72Ahvfh72iG3YTnZ1_vk6(>kfY)%J|3N5`h`~S6H|EEW
zhps%IL5kU`Rdpz)o5fCp9&n?HCcLU<#rgUw^mZH)ne~NgcJ=C8OC#xOBc_53f~uU(
zj7X#rHt!hn3m_lFz7`5dK<`6tBR0s@>_g{NX|bu%MEi)8mW6$TN8-BI;HyI~`12W~
z(!73N23fTtSqwp!rfT7ecX~sGT1ULx*UFqSMu^pTZm&M4LR2-uzYh3g$C@6ElP3Ly
z!DUJ6-=^2fYB7s(9K30jz}0vtE62fq^)A*v1ie8HdaG~YS#`}~(=Z2HQ>cP3F2vq0
zME)IZv}xN!p7Ew-D8n}inw2taJ2h)OL%b+iH;0ewT2RaTUi;L>gUV9)ssXW4pQ=7r
zD&a23C1@32et^zct=;8yDCqZbRcqq&EZgW%Um1S(Z@ebc66m9jQv`G?T*nPE7V_8>
zoJfm7b81%om1<yU4D#z$DCtNn*I2c46yAVEK78r|O_o=L$^*}0mtn+Y>%~G~9U{?h
zS2Um;LRT7tF#;f^Wli{y+T*eJy^q_}k*o=R`+O*1v2!?V1|P&Uw@ZW9LGNJ9z-Qx)
zhO(m)gHwwZY1QxIWRe(Dd*wUD>0x0zioJsZx3Vpv-f#@NXh2$A?hDdgFrzX(>RoYU
zwH-ZQl8XoM-H1V?3>uIu1ps9b;i`|wbs~*m*P$7G9UsnUTgZv@;Gm?)RFTFoci8!W
zGENgv8MvascPk$j_#i5hO<pXfQNOZ<Fd188v;TBT4~12kRzq6n0t>%f42QIEH)Og;
z^ES$h;y6f@Moz^jADql|w1wlQG84oQ8Rr#9seC531U8jNEp(_#E4$!4l2+esJqKCz
zZ-=T%*etf>+D#%y{u(I}otyHIjZ1rx@*4}*o7cS22pv+JXw|@%@#nf8C#x#$qc5Wo
z%4<2Cv(8|T;B*c^P+ry0Gk>@s!MIh0R|i{73NQ~S?=%S!_6{y|YZk%OW36ASqRpcY
zf;Ad@pI~0=hqFSZ*4NH;0@ticP2CM-l-tbfRji?A9z}hyp^ea1uC%Jj`{4`akr|)S
zw9N&+Ud>`ItJ%%7wr;QHEEFgc#N%YS54GY3#jL7TFy5vf2b0$eO*@nbVVpS?xUo5X
zyaiQ-nziy4k`l_Rv?fDRj7GU2-#O3q{X;bqVzmrBtT~R1Qwf6e@pyx^QlWWO`)>DX
zYD}iNTAz)k)r1zb*zyo?`EFS+%K7<p&6LqxErTR{^rCQvha|)re0A-^xZ*0e8X*{s
z@^d)0SUn(gkL$Blfd<T(^?-9y?S?sH{+%KRh4H9D%(VtPrwvw+K){5g8W$SPufJZG
zXh)qv<Oy1JGH<7(Lip!9P(NMko*4tB>N>D#FxWy_&81dj4LH|*z$f}45gYgzm}yga
zbE<UMd@wMDmK;!clUk<UGUiWYCj`|ud5K!~uBct>MR{bx-eFg19W&>@e3<KS@jw?U
z;i{YW#qTUCA(&WMBUF8?YaJIF^LcSP*M;D{HTBg>O`P}9YCiEo=i}VxJY73(K8p)W
z))UHVUj0ogfrj^Otj&NQmk$K1kq_3#uFemh8HoI~s3gu=l-Fa_1YoMj`;AlxHtf2B
z+!i$-+KjxY+v~$RRg>$mS&0xEY#KZZy+r#k3Gr@C%}0ZuTdo}32(r08b4crk;PQ8b
zjAlxCpR`d}bSf-*StdP5duL$MBAo|^tOivXo5%>f^2JnG#pXR5bF_$cnlY+`x-XYw
ztQZwojYRs?1~%CMaVeN{-Q&vOtq22s8EXtRZ?M5X^(4(Y5JRV%y#V`Kut*r6v1-w2
zzOUY-Sme7Pa-p{BV{0JD{SPd^wi%LF58>G8>P**?HPrR<&>O&z8_g}5u-7{(r^y;W
zi{u1BO`(N+cYUH(eun0B*%iii;@1mx_d`)XCc!p!nl~s9PPr-M0uPIQMKgJD*c)vA
zJjPzMjs_EaHCAL4Sq%o8zi+5zRDj^Z9A$jQkITRC@4SV)kFCZ|9oBxT0}dO4(a3j9
z6A0*|Qy+|Ge3(E65~VN}YBp7(={$_o665x!mbOS}+1k2#V^A2~MPhZA&xhe2BC5^8
zv3i!}C4!Ie&Ztn=vLX1XAtYVcnZ512ELB?$TOEid^L~W+@PbEG<b(Qa^R(`a&H?qH
zzKL5o#>d#YuKs48Y0%g75D+=>{RxFqiCkbiM$uxeXTu>2g%F49M9Au>mL#MtcIu7y
zBJaZZ<Eo_$wh}gNLDRLCG;Q;7rZ$kSg<(ygjy2fh{!6o-mG6XaG1$rnl!-zKjfar-
z#cDFm7;GKb5L{TB2TStlZ;AZwHm|51;R?zaNG!Iz6jI)V3D=1r1v`k-e4f%GAz&WJ
z?=?eDEu1v4RO@$~JDrorEUFo7H9hVnDw;<y*tD^l%2>>iO2g=1ehiSU1!qIbg)TVl
zL+$$NRT`mw&7SIgh@IbAi=DwA%7lQi(orwvb;bN%$A+UGr~bO89H$+ob?VowKromw
zeiwy|dVpYkT;H48WMu1_NPVdVpR75qP}Iu!<5Nr5%Ao5gp~0eDt!-q%&8Qf``Zxfo
zjEQq;&0?O#PTNE<`BuyOJ#?m4Lz(1dt)4w9&+`I-53x6+Qk&<4!&=t&p*HT3ui5qE
zwfC=mc^~CtKzo<>8%2FfBdXWyPra@R@{pT0n#COEf)C@%24W>GkOysJd>Eg{GYUUP
z7+=7Tbr<x(4m{H9lB?BMxAiWicC7NXSxs$fiE(>}w83Vv)$3^*!NAU__Bz-z<NIv2
zKrNtMtLei0#rP`mH)~=)Ch~P>R)N$cPGHYiT<?pLji_u*u&!%tgKLLF4@Oa_jH5GB
zh2i;l=G2Xof01CZj$q+a8PAq7tQV0rSlZy+bvmz^HVE_+H!v~SNmt@8hv{2k3<mu(
zKI}5R7q3WWJJB`xlj4~a{L|^hs7qB{dton4Nnf!GYk*ei#u_afQDIfmXC_Oe>#h-G
z{j>~wRiq6zi}HGZlxaWFr!L5JeX|rhg9cKI&Xv%A_-a*$>yYh$PntGx3rE?{wWx0o
z`T8$Z?C;6ip*8R$0wZivQP#-YylzF}5!BH<JaDqnn+(tAaMR_KuQmexa3rn1qguWw
z6_;W8rTQ?(cAN8&FJfJUr-fw{QJu_?Hq!z3*CD+KI4fwQjAfF}*IG!KqO-mqYD@E4
z6Kyzy_1S9JGmv0YU-Y+x?!vlr7|A}Zc8<u-CTUVm5M+KHhCLgu2W|NTnCjwc2Z}fg
zQ_30*!hVmn&I}n{*M<v$)0PqxEaF)mjywn$i${T0XTKKYQ7^?WCjESytQ={2>>ezP
zzlzdHd7C_BS|N+lWal<1lurQT1EkwT5<?d+?UDz~YI&fq8~HA2E6$YBXK)lox}~9b
zf;4pDS=i6}FgDJSXlb*gTc#ktMeNos(va$NvMFMoFH7IgjYM5jB(jN=H<t0K<_Sno
zkp>4$8y8^f!g-KL1AI5drN}RpsG7uQ3|}jg$~)BG;j{6C@jK-X^WS0nj3o!RoN?2P
zWP7$<&MUt`PA{LHtjktqrxY97A1X%j<l@Q6lNUE7Uwfu0`PPmZ@|JtANZx$!+U9A`
zPitw|Ju`0l;wcHXID7sKDeid3z*{yRJb22sneo!+XBWyppOxHQoSOXL`6=-c8;?$o
z$d=fq9aDRwjmzW1pK44Ff2yT${>CHXa~@w1%_}ZS4&PWlw3N0US}GP>CJoP&gN8Hp
z_pXQ0`~O~UPQFu4TTafV$;lXpCug&hw`C_J-R0A9e_c(!oi@l@(kOYT+#nB?o8-Zz
zt@1S-$e!|C=_#L>O#boA_~6~^lGb~h;?|{;6WP&NkYXWOxv?ugedGMZR2!vhYaIWi
zI5l2YoRTcc7R8H-OA4*U<Kr0{rzCS8KOmm-c#E9#_`GD^;|mI<jWc5SDf7}+Y+1{C
z9h+|EO&5#Yati!C!!{)++sVnQ;bL0Njsw@DlatG{lT}%ttirwUw9LvW*~(<4%#(-k
z`9O6i#^laRlh_;~4W^K+8!>U^-bG2zUGw5^4K*b*i%DT}aZ+;QXfgiw=(MCLhhm1G
zQ;3F(u~d)8qXtuGO6L}$tUXSL57N0%($NDF4Es2%9-)3MpN5IH0sU<#&P(5zWr@XH
z(=&qe0{0GY#Fs4ISnf$q?wbeS50`ICl$<V;la=^9;*4xDp42W$4wmII8PCE`&wAqT
znx<sU$mFCVOOp)GwLdr-C4WDf#;c1nlPdZ@V|ad2+&MXpF&#`RHX?sql9gA)Vip%#
zWm;U!x{|aQ71Gq;Bd$m$7t>_&#->7(Ybj(dl4SU1SSh!6VBuLpD$b6Kn{eJnXt&)B
ziY>2^)tHOA(ZROtObqt<GGw$bmBeC>!D)$8bqgj4JuY3+T|5eDoV&$s@V6>`#dDK+
zn7d19ldLN)kkZgfDdL!9C~uZxZryfnY|`T}6<-S7Cd|V#<J9Qf)GX0P_2>rm?M<K4
ziTK_%@GFLYeenAM_%|GPyEXA@_!6U^ZNr%CT^tW#)~S|lf(_T6<~S{PC7CnWy5cl#
zi^KDWKKN(iQo6D*FKbD<yA~wty1H;(n~d_SWoxk{W!&R;xl-JPXZfYHitT*(Q;l_w
ziZ*s&TeRUpk@s$cRCc^ClBJts%;bft3?*%HE&A9I-y&<k*`lo&AEIq46m3sjv^FlP
zT$+;|kn40=bPa`~iwni#QH5fL<0TEr4l^eyE^RIpr3JFMkYYUG>QgA16!kY1GO#FC
zkbb5)etbBNH^NS{#OR;eUl|wE^$n@h&(-E(i{c8--OP17)`OoYIRb||9gUic(on$H
zX)qBx_%i_CdJ3uONz9-Wu9u#|5O}ID&VU+p80HuWC~xf5Q1xbuZqPpK^9$cc=+SoE
zfbj;Kn{+629Fj?)0{+(N`fv;E%>hFs`@q}4k0BeUKkmWd0Aq9^wcRMwiUJYblE-eq
z4@oW7jD8yD1a=XInz4tykpVmt(s>)dzU5-v<ivt?M!`6XN69nrC8fCFqyT@R@LP;@
ze6>~>mKKaPTx3ddSlk;3vk3O2fU*|34s1zcqQa;ew%EE#@FCK4BR(&ITAyrn0zi|m
zpyk)&A=%$(c|dt(xcFtFQ{$xTIJEm_>xO%vLnAob#r7GipJzH8xqFb8DlWO3a1BnJ
zMCfL*giCD`%5Aaku6f|l2p&xv+C)D57utergqag=c-t|nAAj$yzqs(ZNAw$Gr{3_^
zdzyAHzx|h&e}45#hd%l2!W%CC<=wki-1@?WA6a|lF)wc3^^q&?`NZxkpLlWelc!y|
z{E5zEZ@>J8e_4J13wxfub?u5{o_xpKZoT~5d)8k0#GcK!Uby0(Ck{L1iQnD$&eN7Z
zvc2=x%V+=ci9;8?aQThzTYKLl+Yi0{!sYjz`T03dEV%W37ryw&m51HBdEpJGEno4-
zk+)y@+b^xY@{><KJNw3qj=@YR^4JgI{f|X%yy%`~xa!B!R!(JIIr7hpiX+A^4ckDu
zYS3-Wk;R>v%-o4I=An)F3<|Rm(ngBqHt3smd`fd)EUU9Al666+dTcvXr+Kx5e02-<
zTRR~K%IZ>?(Pg9w0~TWfdIMSNCRZ`5Rd6KrW6CNj1%L1R6cQ<p$o@me{?&gFZTxCh
zuEkmMl@n{F`noW@CBeij)<B3&*Uu4>7F)1pQ9$#lo)59=bR6pN&jZwLf@uudrb6V(
z-i}pckZUzuQ&3(*7I&-l5lvfUb%&o7^tPID?Z8?c*GrMPP~e(?A{t^-Lfr1pE^k(6
z2BVWeoJ_=yxmYXUniU$vGgXzC80$5Cn$m}Sr^AGTK0xMshNp(65dzgmS`EF+gI>GT
zN9{ye9^0Zx<YTKul4Q`293+h>SDf`w8YDDAn?9|1*MTSmND+L?FrqC*UgFpL#vrYm
z1}$l@1wGCHowE>t$?D!amhZK7tq`nxyA~LY$>sXyton>#uvu&xtdD(U)feR^4VuUN
zZ9-YiO$chI8YHG0d+XDB6KJ(NwO}=2G^z#X6W;Bb@2PV8)!#!AtI3)HTeAw;NQ5ZQ
zYtmWGqE$482_kaZXjHHQE?$GkWchf6(1niMnlAUTCx4!+JqY(`aKIbD99!#0)|7<S
zODGhH(Xt3Sa$r}-V}49jkNl`b+nS0s!kBB&lH&suDhc|MbmCC8IA6ex8;`+dKOW&q
zuGdnDFRJS+SI%0m_qkk#w2>ZUP$Tv4JVAnX^tV;h$H&;<MF|XRlNl47z&WI&2Qys`
z(5Q<h8!hE}eW@ig8*m?%V#8Sy8qBbkr~&UPq0u->cWB>GAMGNAApx-u-9FCJB2N7n
zgX=ncrjn0iwTAVr@217P(rHBcT9B{e3%hXrF0Gm*5_M@oENu<A!+P54{c8$LlB^F^
zk}Mv`D$Z&Z9h<|}&)-p}t`Cd|6bY`+V$frUGTCI<fGU&0E}UMN{1L5zB6YDW*7tGV
zjGqw0bfN8)AV=8<_tAY8>ABb-7fnMwg2?nBLK$bU*MN311A&Ik*s$KPn$~k{Se(R~
z2|-O|ShjeZ;hF^Z5xTJ%40~m%M+%3-DEOT1P#I~9dXNlvB-o7)AwQ&|Mvcbu%21uL
z@Bx#f`8bR!V|||CLz-wa&R0PjXx6({Q329}+J0j`Sx)obsPS}2;yxTZOor;VNG~=7
z=N(2pKZdjol(tqGzhxD2S^!`8PSUQ-UoD#TJ-EzZz;z2wv-~l>j@8Y6Eud9Q|Ht&+
zL7BoZ)^*seN0d|(oVOji2E|8#dQ1&`M`!f7<D7Fy;_Bkd_v2jBHD+c@-UTqm>EG#;
zapExUq%HQ(gK+J@H6H81fuyY01^oySZR5Tsk=@#Uga;Hx%qaXpu*Ud#1m_io^2#JF
zSqwcWx;s&=jCC;r#+||Q3LKsoryTs7k8zIcALgc5O{N&P<p_F+M{vg{1vh9>Y*;B?
z;&7sX3@r6V{@lftEH*{>n}#K9DuZYw)_0yx{|!?3NlSwWyp~zHLs_(=5sN(-IP6E$
z&TKVAU~loBm$5iMDj5A)FJx%Lc1YFrX3-2u+z1B5;~2%GIu0y;iBzw(t3}SmPJP$3
z94K8TPNE_38o>Co0I;JUc3ZHd)v=n1>oI}@f;9B#e5yy#8a&%OS)@D*x=3^hF0D|T
zc5N({(fI`k5m09b#Bza+vU#yALf35x>vB}vje<H|jYj@*52N@~zal5YSab9laS%lY
zPpgJ8*6xxNKfVfE7b9A$kH^r#dboCzPlo1|mmj|>vpx;~@h7O!k6mglV(4^(Y)CUW
zPC5p0h<tVF@a@a6QzhEPn!N-domx$gUj#f3m3u>T1F-Lx4UlV-ViSkwQ_2wM39^%s
zMsRJ2P&O-pS%VjOKU^Dx7Cf*+NYJ7;<ibuY?7Gw$!ML!H8RR20pLW`K7%GUoTu%wv
zs5yxYp1K&^ZfhMMVpQ<<(|A+`M!7xv??~y2QG>_jQ$BJKC%!wX#~(I_IByU>;54)&
zuxY$B4nA9-QQ5i(Z5wSAWl<SN7iBt-1_zu~A<R%pxEADDEfUg5Xf4g^_{F)4n`R_L
zDw++R`D5T0nmQIC9z~=Ey$pMY&0y2wF5l~5P?*)=nV)W243r2?Ba8BpCJ<oE1Zl|o
z_}4$wT_3h=9wL)(i3;-ZSgQ{aW-UoKS)>rUMMiwW_~VSzt3}Th^%?Ez^Ojn0&(u=b
zV~Fbf=smWYu7xfn(5}<Gfe9G0*dzFP$|7M)UayBD5*>F2+k~KwqfF#gMo&`jPq6Ck
zhvJxL!Xbbx)CqF5frM^yFgDDrC7<zjFuqU;27^uL8(<jg2c$yOiA19B;k>X!Wn%$t
z7|iPsST9U;O3x}Vq)buC=x#?y`*QkRAT)(G@rN?C%9!KuPz3s5OfP2WGd3N3UFf^Y
ztJtY?8p`2%;ko1f6_b_9@c<mLE^ctWb>5cI6D3J|A<u9uYkXl66}%InqgD^V7>1=;
z;(SYbq~J7c>CqYS^`Ssnr)Qvc&tZc|i@P)%zz)|cqdV2d(IDzq(Uir+kQSBYcXrma
zTHk601}oTUQ;1ZYD|{+MR($h5gTh8&RD;2vRr@}fcgsN$=2bn{t-6UwL!WO2b*=wX
z|1+;^)h_53<Qk(ND2M_^<9cYd+Egg2@9u=j$auX@*CRd^q6`iCl935>cU{-w>PaL9
zQA$t##QS2Mj)AOVLJ<ohWe-Pti(s)CY{|{|4BopK*r^P`bR$Y9zVBc`*=gB8*I?}t
zENTS{7b8ue(IAZ-T+zQgSgY3;8-{~#Kd$#DvbYa0dBLb#Oh{YjY%Z+rwC&J-@L%Ny
z8``k~-$F7NP@n1nI{0Pkc_ga!OzLkcEb_sGlnv6Dn|*UC*Hna^5nZcBHos%_1z;CT
z8fXx-%P6`*b9!Aua6^a^WqIpmn#WodF*c{A^}O)qj70{a&uLzL)yC~ucYQgP`SQMw
zX7mYy_to`DtJ8cQ989e4!#SgQqmeg<IMfZ@*R&oOxDsJ!f-bdi&mbSlCddwIu84%_
zhTt?Z!F=s}^*yqA16~cYRtq9n%(2)RY`xk)?0s#Ey*dL~FLn-FEkHDu#}uRa@c!6Q
zcOqdlhY;!UE4wiC9R$XR(S2qSX-LA(8w*B!?TS8;K^Up&Be)1)MulM@`=R0UHE>Yn
zd5a{Dn4acV-H$Zu?-MbN+Nz&cq}mB#B~)?NAF5hwT3qY-P}|p(%B{B~vC(!BVfw2F
zlpWBF*1_E3G~JDJ2>pyo-cTGa^Ligr3y^zNp0DUW({cI#T~I5cJ;=-WzG%C7-qaHH
zvPkII8V&;gxvQ4Jp9{8;(B?Zeim{?c&ul0RNBw1AbKbszt+5vT`oXDE8}QuKMhH#V
znLMp(hi!{O)A`S0AC8l+sgXZ`UW~N$>kX$_qY-L3L_YK&E`f9CLxh|Q&HLkOe3{f&
z>uN_+8qzMc=X_eDQ|-e)Q43|HwXV7~7W7>mAJn$dl#fspWjzL!?HE@{g~M7J!TC5u
z7P4VY`m$qe97MU#;ob&$hq6WuDgO{qVXRJ`bWovymQkIZ=)4X7x!g<t>?AafveJsp
z)X#I3Ak5VW<1vY9-BbbW1UI|`FsHpUst|F30`AW=hmy|EZ9e0I#Aqqy_|f~k7zV6Q
z_}XHj_d)j<D7p)thrC}9Tcpvt(S5Ep@B>>79?m(P@(_%VYr6#Zr(${?>gU%!lQ#i-
z8Xm<~<BvfQY1Zi2M=-j~_X!_s1n+%F2eCuJTEOBDbD7r8gAEQPwY<*RetI%0sa<@~
z1~R%?i|ecnOltnfUc*=Q{!@PwFgT;n05n+5hw-ZCj0SxCrv6$@k765d*CLOgZEHnU
zHDK#Ahy-5O=V4T<N)nA=x>jfLokyK<jn0{4A@=9L=7+{NqN6MiHE<z|3#~zFoG@R5
zU{M{q<H1=p9<n~xDv+nP3z08?Xg!1~$Gqt@VKwsQ#`dV~i;t6grJB*3f1`h)p&-}y
za2_Ad%lKW@;=Kg)*;ui7)&YY!-rZQM<71IWVF%xnn(mLENg@M1y53f`&`WF${IzX3
z|4S%biSafA)~Sus;b2D0K(x_fzedbXqc<Y4AIPmeB3nx^jL%u_QrB!|eqKVN8ymRU
zt>UluRrGtLQ}DF37eZ|hb*#iVW`g!zYU8FZ19w}bY@vs1C<hyBB<VIds979Eop`iT
zfZky0DaOMPr|Lv?X*>x3Cu0ra610}|`olJ?ZRnZ__684FEXj|Nm&8f?QjMi;3;ff2
zM}4+X5oLKb)=^FpeD7~qkm|uRLjXd1xDbHd^rQo+Y}87(irj+4SnS10q=3aBjm_cF
zW2MJ`hPGJxkWXR4qPzI7&#Dq<t~c(7Sf`PA$i&WO&~Jg^MBqcLHf&#S)*Qh{i*k79
zY4tNezSWOxOb`(6ke(EWsS{eP<KqUW6^%7|f!K_5B)tS03!ikZ%cN-t>8O%)K$7T1
z!F5Tq)n^2#hH)}^C`%%XrZK*a?F{$M35Ke}Q%77-owoT#>pJm+lJRJ`bQCY?lo24r
z5>z6Cy@luCuWO`8iWff$k)S<1B#BFCHG6(r%f{!o;dw*vWA{LuZQYi%Z`+p0Xd}-1
zxpK(TOJphDPm<AAiAQ0fSWb%NC5b#!g$(?P#iV89SxNO7@W$4B>RCz4A%`T{&--vp
zwo2iEDT9S0-d!ke>l?_n_Q^o+6uElUk<({x#Pi9m<z(RP9d@9x5Er+VPnx-{T!{M$
zGO)QIEtfAXq}!Ih_&%^m`eJF>yfjHKU)oas_3|l4-TVK_Tb6!9{Y@6%eSGH`_nv4D
z>e}A2=#neswj0loGk@MHmo8f@f4Xy9a_cYFwO{t=hW0ZbU6Oo%@qx)lp7^t5`SZO=
z*YmTI<DM^Heam}JXj%5Jo6|4<>+<AFPi!pQe#P>uSN!%}gU6ipuELBHuIRb-w+q|8
z{M79Dgac<6cKvR7;qTwtbrSX`-GB74g)c3cb!gKGvyxrUuSo9Swjz1)qceA$C-Q;g
zAD&-0uD9XP8Mn<!Prvtsw0Q4Za0|ZC^If-dnJnqLEV(3|A?qvKWlz^SnR)&+yoX~X
zyMAV}?Z=Yr=sz~O?}4L|uiP?CmOZ{v9(iGQ^39(dkUaiER5<R03*@h^J3cvhq$I`B
z%aY}%E*!l1qZeHLmj_%>xNp(?_`bg5<PH6^vX8dUl3C9lmfY7kt@n_J59)ox#_5HR
zTs}vRlc_T0nJLNCZAT{8el)t~C%CpWkIuPza&L1o|F)?u^V1X4=<bt5?rzj~i;~6V
z%Voy4i<0WL3tKkIESw7o-m7VoD%M%+w=PfSj82oLM>ZuhcQ3(H%|h~}JI+aFw4Ntj
z<qMO(UrbBx`^BHjE&VH#vs_E^#0$sA^Phdg)lHx2yt??APWh`}oRRGM@CotlCoIoq
zefh}j{xjbo_l>j`uFn>plzeZB{m_9Y7Vdm%QsLGkW+vBuaaPiN;WS*h&rrYa?Zvo=
zFQ1wmZ{M99FH6(4a(wcR^Eb#*8}W!1p8<hta<P4vT>3yq(u(t8-A;Vk(v>Brv|faF
z>M;C&(wAKD%o6!h|4Lcz(q!Z4%;bIL3*D}}8w$%t`{FYnxAMN>mU!2P7sj(OM||*+
zL)@qTXG6~?+@zBhCgph6Q_GU&2QDo94c?Xdl#yh{y&ZA6sjwL{Q}S6U$h4hP<kMU6
zywu?A8`1OrqxxP^ym5CWDcY7op|7!!jK=XQTaG2#P-q)jhtCJ_B1=^Y1#8=ktS(?>
ziFa<g3t2fy`nDc{Y5TZ1TH04|JFy_$xkTcThB!JCbNHF<a-3-|%zUClZow;4>6vA>
z<o%i4^Z?%DJoAt^c|+NK26O#&c7B{yj*R8h<pTq2+ht&NQM%<O`1U6C?Wym;zcYWF
zB%MPAIdnKmy0e|KY6#Q3EhLL&WisQ@syxsqNqonetYi2sBG+evU+KkV<v6^u(v&=G
zF~{QbvyT2YY!TFv^!MTOwCmT)QezW`mTo=A$W4zdc1u2dkhn`)<@!<<x1_OKkakOR
zcM1R3)l%s&YX&;9gW|>rpQfkrh6nLtkFHyy$IegA#WVjoa!PWJTZwdsY)Yra=cWh6
zbIhFh9O;pB(e9?GAzmqSpl_33%`owg(l=%Q98Dd5=z%!Cqa^kRTMKe-beQ~e)Dzzk
z&6Q83bCNqM*rM~|k45X`W0>RTM3a(_p-f4pxjS&Z)6ebaMh$L}9OUM>nQqZwiz^LJ
zb4T|^Zc%?Dw!?-N4IV4!j>PaZ)_0!n);HaH<Rn~ZR$@O*&P_}4xlxRH7po<-)AMk*
z{Agt?cVi4X*8qRI<&NldY;E|D2k{PHRFpg9JotPSK0ATkZjn10H^m>rGxve40bZ8y
zuMhT0#^HG#E+*NW5$ld}b0oI<Y;umwbpoH8T{c`0I|LgE-p~^3^j$oBZV@i&(xdM@
z9sMIr|1yL@h(6e7uzF4V@E`!29S~f1u@|g)E&9`ed+;7ylMLjz4#abyfWBH1*LRda
zk;s;nP98AURaJ*FB@~U$k%6j3D=5>5AAe|_6UjLjn?yUd4tm%aMH0_8v0yMrw8CB_
zSRZBs=fJ>N(0865I({r)OIhbk@H0pZ3?Y@oy5x|G1;ZE#gqE_FONVj7x~xsy;p;OD
zK0K~L$TBC9K|lNz68S3Z!VMkka+bdHv;^}eASH*s`0R?CFFNMf$IrX<IlS|<=a@a4
zpT7B`duD%q`|W!!|JCX}%U|q-{+GMHe%`HnE_`wA_GA9#(9{2F`#raRWBU^?ZGQ2z
z?f3lTu!C;D=!Wln^Vk>m{L^!5ul)Ca`Q*E9-+tq_Ph0WCp7(y~rz<}H&d;y?-ap=W
z>1oG4vi%*qe*3nYx8J{g&%18C;<V4=ou^$t-G1Zt&#!p;=v%k{+l!BEKWx{tQ*XTD
zp4pGAxPALe(0}rG&n}e9MpxlDC;HCQkC95wu}35&X-N)4cg}rgZgQ?&m0UJrlXHgz
z=|-G0Ey*U6;vLWh$;qQf6wb9-;j(9>@Xo%paPDZ@HfJ;&I2S|YJlRk<SCYaUyen9;
zy@h#L7L{z4l#C>E@Y~vl;l}UyM>iHquCq|;+U(2Bd3eddGS_+a(YCX&C`k&3kG8l)
z*>rcbD-0anTNqf>uIp(HsrozR8J`B{|8UUbg~K)$%vf?_%1zAfJEtbc2ZIZtjr1Lp
z%f7AhRPW^gLC0GNx*A3>_-bhn*4Vx1P=rCJvKV!-M#a0$2v8mhXDco|Pw7J%3%40f
z*vGNMxq#Q8F$B}ZX=#hIT?=GZa|m#(2_MR0y^6Ihm>Cr&vK5up0~Ge<cXW%Jt11Iu
zu)fqJ&P8bP87j*AF^)CY5bP!RhxfA4SZ+=WBa~p@X+nRIqeFXv=Z-j;q~tJR!vs!d
zwNq(=EC7QGDAOUB1hf%^L-BH`f2ZkKT(Vqv6lroDo~>KhG4O5_uK9p;#UPdEt*BQB
z$UC)&v13X|Sl>}NiH4!G`5fonu!8H8wuZP7b#T-Sc6iqgk=_#MF37SfDkCHYbrAH$
zK8Jm=j0oQs(8H*0X?ZQ-aB#pNR#%+Lv_Z%X5NcLS>Z=#}zz}g=kDDBD6L8a-L0-YG
ztk+V5`}%nTcFxz?s-8fmO>1yPCz!iJTA#EWp-F8{$K&DNps9qNI;z7$k1DPUer`9&
zsn6a)FmT9Q_)*p}rpKG=O9!3rBMKXc@p+M}YEg`tQYZY=0cTMWJH2nzWGzJHf|q-j
z)bAv~FfbTtUl7W$rH8_32Dg<OA1HA&B8d}aVj)0V74IbK_u!fYQAIiti@OO$a830e
zH)<22%^>nVYY8}8&&;c*e7RZ~J(awHMtxW0qk6^iq08Wqp*=ilZ|p}qT^4DOmF^bY
zml=bW@VRs*wgLBPnl6_!*J={!OX8}Q&G6h)A02g=<}PIQOOY1-W!Dwr*y!*8KfyI;
zQit?gxvqjEE)L~-k{%;1{kW5hhtM^L4oU-xWY-$3A+$(r8-Wn_^(Z}DiSQ+-IB~Gm
z*7Oe;hpBXQ>XW#%rP++2SzG|SBJ3^RnMtLL(r`jKp;IQAx50|NE{RRG8~4Y!m5r=3
zsN5!PEfusog0i?BN5}gr(vO3Js>Q?)CLEv?dc2j0+e3f8I;Gu~;_F-phuW6m4hW)-
z%%$zvi`WrmtnUn?WMi7)U3z~Cz?B%^nFyad0s{sH4iBioMNF}9)ky3RL8Tg)O8b%2
zyxOhWN@LUr&!Cf5o!Fqz5M?+tA&D4|5pZ`<#zDaA-6%3@^v1h0lt|HpH2Sg*{ZFyR
zX>pp>V^+5T7}|zcpg#u5H~3e@4IU0BksbvNIJj^t6jM=y3VUT#tu-O3r%H1+Xi9>+
z-Sslmq4NX0Kh#%=wM{)n8VsHe497`a(XL|dF|gHcFlupLSg29Np=N|cVppN%A!YpD
zmB>ccrX85q6KQjqZR%`|uYy^;tC>V5)r&)aUl&FV4r3#l$BXk_bKv?2{x@2ibV<|+
z(+Vib(#XPA$54djde4K|U^b&I##f@M#<ZcEi88d9+NR(gwvsKU_-{4PgSPmZ^dx*2
z1&*b7&&R<U#>I$q4!~WsEy<*`KS>8u^dXjEtYI<8@X{X^W!JC92mla8)rq%~P}vN%
zNT2j#PQk1*17{Tua@liQ+>#99&^~HoBYlPJ@5IiG@SYO_dfGOcL@fo=VqF(rz{d|V
z_^&&(8n}RWpIR1UMvn0!8gA2EQ-{8K*p}k*UB-8{r1ka^Y?vyZaSqS%?&EC5T%<0n
z)_0zovnC7-7bjQ2k8->Y2dpnOO^unU%+w(aAO0?romI6GPr-c^7P$VP_Q?UwvaBOD
zS=O7mlQM67@rdYnnyYZK10lj*A}i0}$~lZfu)0MJ_BOkYWB~6^b?WOjt}$twQHX8p
z%!+I=s6QW<s$TF$GiIif?)6gC^CNDP4RAG<B|T~1n#AFLq@xoDt`}w97O@YvWnDPQ
z<K4{|%UHeOnNuv2CDsdg`?7-U{1e$AbDLuvn#9k=Epg&{TVxA-Zf}kvw*<bTw8O1w
zv%$F3bwfqpA-Uvd+IfS~vQfXWoj^W5An&>m!QT$Z@#0sTFY}<DLP`L-Sj0j%j7}Ns
zrKN~Nk9vBp#<(U}9T7<5Q258uz6}Ksiub3et}@s`aNg{JI2LLih8*7J)Am!GCPT=o
zDGgnE^_c0+dpCj<hA`iChUfipRR^fWX0Z8?Vvu4SFTrVxwHJo4HsR}IPARBy=tC&t
z#-ssBi_I5OGbjK*t%0l=zT%9)@k65!;!oCNTcBLu@nNJAYvC}ufpf;%-4bCI(UpUP
zE<ZV-LtkOo^jTaNF=azxEOy|6kU}FC39L&Y)Bw3dvKuEELU_WDOOOUIN%7BL=(D&}
zFXIN|#M?z0-l}D>sTQ|t6ZMUi-ZHw_1DR^!<p2@}Nqj#ym6bl}x;s_ihl1Zbl-{7J
z5${s!Fik~0Y5-wV_#{r-sT$Prmr@ajCeamNNUx4M34<tNm$*o|E$V<YbPDhK8KdQc
zD<W1|qZWb}gO|^Q$a<?r#~PsJp|9?5kOg~Q*#o=As8!#(_d*YkmqfVNMiPGwKx_Qq
z&s((+mbFqX=onjE%YcQop;PFFT7$32ZVwzy6`V@s<GxR}?wl7kV~k*(=lg`oAOxo+
z6PxG!4yrpszNgmzVqV-z0A!#@JAGA@)c165c&}E8^blAiF!=kigK3AI7__VXN)OeX
z^y@te&Ihr0zgGno6;0$YS!oUvi4VSam>67ak@qgw970}Vj8UwXbPr<+1`(Qs0~RuU
zqZijCzf!Z!7$K0uV$vr_;?IS`I2}T$Se+9f*OCbiltBhT*D%^4-#&CBnvI>twcmZP
zXf4(jyvJeK;97$wA_y@p>O7#|hZ8GtyFtbWt3Ei$LO@ZQD$6h7xi{L4(5rkrTIAJt
zbl)HeE0|u9@DlXh;jL(pKroOwsC!X9LEeg;13VV>t-t%wv)92+VxSEH#?(s-O(#+Y
zZpJ91*9$e^Ln6Z=;o~f}E$|2Kp`u<S47}0ODlj&rk<>F0t6rphKnX1r0vu3A2x0i)
zSfMUVz_~ma?E?OW#;T1eOSMvAuZC*_M_0zk&&T%O!y)hXwJ_vtKm4_!0%C^^t@diO
zzHQxsgdeLujmTnixU~*>%v+}-g<9i-LB^t(7SeHtw1z%>HdgZ~I9|eGi}5e7KZLzE
zjMby!_W=h=gO``IDNR|YGNs+>>!MH+$0JCOLW*@EIAft^;Y8J+7m((yO!3PBfhpXy
zK?*89V6T?FIYdLb*b8E3olybY_RVX$cSPe_Ft9WNe?kY9HA;J9(D=O=gR=(n8{EfZ
zG=C_uBI}dd_n~0g<wYS!F`Z|$xHjp7^>GSnO%aUvv4H}Z@|vBha%4ED%2y|L4OWv4
z@Et`hGTvxIi%(%Sf_yj{a3q`uoo1W}X@q=i`gDF8`vYvXO$V_y?GGEOA`RytNL8Z~
zI;Ie$>iwuq7?9<m8?|jMgR6ki%e<Nh<MzNG`J_W^^KPl%sHMiEL0cckJt70TzV<^T
zwhsDy1X;0Kyu+y@&ifXpscnQ1!TESx6dJeapoKBd%ySAk#0a>;$KEPTY6mswc*e}7
zNklsQ@)Ah+m4X_y$lxd<_<DX#qdBKhJs$DBg8&vaIE{=(u-%zI1_(nw2)j^3%WCVP
zj#GtlAJK%L0~TN6ld(SHMX@2VdP%MH)=jG#U-!lP`H3b&(Cd?fA(Q7@vA6yYx0pzG
zTOHp%Xf6F%8V3ej%^&042ol^^^mwgr01J<ryRpgFU2#wFU)xYM0!F!)C9!M5EQ?G*
z#d<Lbp+O77MI4nhMsh&KxU?d&@IDr2bao59vOyPmsJzgOb?Pm?sp`!jj`GE04g$6v
z+K40l9)N#G<S#GMlz{@vF}*@0IG$MFtJGsLIuZG?X3-S>^!!(~ZxZ!X2C_)tHdJ%|
z3pAdbFXW#chz=-RAwn4NJLK@EF8NQI)J`ypJq-ESpc<O9etaPf$D9^ay_VNa-6=tw
z2d!X2eG^2u(P%(3kc9=77VtH5y`LMPwY7XT)RWjjnzy0VeXyFaXj2mB^juLNywZvh
z{j(6DDT6Z|a_c!Cy<UYV7yEM_p9jTO1@OBU@k*bDQjHludG;IWLL+%F+RH@noJcL=
zuxdeHwB{hn0yVBx&iWCgYCG3yJ&3W_gu#)-B@dYpI>hzCQW;ibf4^Y;7=seSE;OOl
zTx7i&llN4cK^b2FReit-;~%AXxe2nD#X4H@Yl_!c81Oy8x#n6dRyf9bg<k!f<Za+W
zp~o~a`cBj1_+69)r%a4BC~A8Hc@;6pA!KrDhsLOGYR+M`^XVAee1VA(9vg&!a}2>?
zb6BlS9EvE@qvcB2)QAbDP*8n{5&P*vv)Z!1f?#K{<>OzwpqqXkHa-~b1FR+e!7?6@
z;7kl9%z*A;T^sQ5)VEG#`mou&lSm@q4#bCw78wj_Jd=~SvpKH{BL?!kT&+ZHuU^I7
z+K_)w=VyPbDa;7Yt{KD+H%Q}RJc}AR6=h7jOHUCur_iTG?(AO$e+yzy?^z>F29Bg|
z@VG=4-C&Suu!)NY9r`o8KE=qyM6Dg3(JYA{@{LZK4bDomn{^1D!(yiMJwcUn{Ppf5
zW&Un`=7$*#MOsV=a}z#4*L7GKV{(D1V*1BDV}nJvtQgbMBa_e=7-?V9*veh_90tmy
zzun4UgM}+uf(J=*a%*f2>>7);@CEQ2vKFk9u=9)(fOHjPaL(c*44vCXAwvam2U@Z1
zb8+4T83v<7NLy@i7CB7qvGvDkzP|JH%@a^-IGLB4igoGYNQQf2V_{w{Kpbt7-Uj?;
zlOzLhIFsMR;-(22n1sjr2`nYnosJe<GOEX;V^cx;qiV%g;g_B~S*NuP{`*P}y=+-(
zW3<+0@yHLiuy`s~>JZ$IIj3`Y)gTEq-gm-Jx8tZ<u|1tOb4|FNk7UaZ*t7V}8vhwE
zE|>;$MO6tb()S~6Wuysb9*z^nRW=yeO@iO=$4Qy=9cIxR+0vEbZTb$}6^B=tE&Mey
z-Rc$T(Zom}%6PU}xhD$GN+6j7(fUe^)EX>nMx3!(xi#*U20K*3(`kL1LGUEEB>K+H
zrq7@`v{5lT#GU-m2htPXw@^;l*5y{Noa9!moFmJ(&66eXTY&sw?tupyhGs53GM)A2
zBi$Vj9X8te!~S&kM;0Kzz`eb%VRYM%&KaG0`;^Mm?@k#l|FC424)@8_mIAisE!%!R
zr*hn*#!Z?sNv2LYta9AWKH0X-$fV9mGN}dm9mbxpv}~_>|0LTmI4QmSc_YhDY?HtL
z!6f_8?n&wL-<H+ic8svmhkno?%imMpx#wU1>ur~P<r4#YF5BgHUHavn+q(`QyyAk%
zAAfGy)RE_wt+?&U<EGyB<ckN~yJFqKyKbMc{kJQ2{6D*w|M-?K@40ODj_u7S_U?LY
zs{QkyUUb5)M-C`1oH287#rqF)E3SLT*?WF>aNn*AXFj#-ZPRz}dV1N}&wcUO$`?K~
z^`sSN9b{Kr{)V&n3@$u%`{2Uq+rNBJyl2_rXK#Og>Y5k7cjz&@zW#=eU7wph>%_|!
zZQS+fZ13;oBHugl<HtOH;<Jkex8M8U?%MO|U7uUAG}*agX=C!j;Rlz0H}Bx#KR;^5
zO@Fp*;b-2mY{p%0xp($;vzw2(?RGoo>-T-|qtD;}#lN`jvgVe%UOaf}B`dx$d+V;=
zx3w%xXLSA7YY({jx$73+u;=|-H?R2k<n_mXqTy>-d_Vo}_U{)?J@#)8c=LO{c=Col
zZ=JV(&s*o5dgA+!ee+k|e{Aor8HZF?T$h~s;=eB0c>IssldpXE!0Zdx9oVvK$E@ZR
zl|}mQ(C7aV|6k!(o?Z6fi9hK2_`<&9?|t`{MYsL?Qp{eT`kR|BoqWj7D=s}`__8gn
zA78ko@vajdpMKZnJF?r}H1EXgzO(4a-KQ>^{+U}AN%4BQZoy6IU)*#2@PYsSvp=2w
z_|G1l@za01yLtVIzn=Z3yMKGgqo4iaynp)aviaXVWy$hyOh4eLjnfY~{7;_#XhU)P
zj@f4)zT?>HzdT+z>0iD%$$sI#tvKmp*Js(h@6AqrxAxGUOK&@&u<QC2#a+u9T2_2{
z(p~?wdKjnpu=;)UwRozt{on(J7Z!`d3!BV!@0+ur>wjE4cj@U}i$-4PN(Wy^Te@1C
zZabtsx^2gohs<rye|OT4FY2H7)CJiap0AYUwp%V<^uwd(AOF}<U5f_3w5agacixb!
z`Tl{eXC0IrY`^m1w0GHGcJ<8r=JE}PKfZkTRgLDU+u9fO{N$(Y(@%V=rTHt@lurH0
zEltfUZaZMso~EX@KQFhppWC@Y&$JBh4Q+h!`lAmy@#}N#WXu(Jo<CFWoTqERwGQjF
zuD-htu55mwxA%j8x=KFO)Kb0a(L-$e^@k2-5hnDZ$#Tt~&XK0>a|<7erljxPc*Mre
zZ3`<$9@kY!`{(2N^werwQvuK9la|lD`3M(xm1JWyAKwn0mn8bt;twB|Jv@4_e6@Fq
zbJ<*XXELYfgKoZU%9_*k9~$0uGJfaff$J9bKXBXpp*#EMXC0H{_Ks%Mllkg<aq|QA
z^3B6*Hcg(^x9Nk^w%Yav+0Z`FJ#bSzci^Umi?gVw+}?ljT=`IUcl@F5tn!Y-4?JtZ
zyjZRsniLN_&?f7f4{BdOxv=J#jSJR%{>{f{MY}93Mu#^KCR3XSm$Xaa?+(wB2c}$$
zdzWhmMi*z3%QLcTa1FsU*DSr$`d8j|$n`6)Yjz`p9oLTZAGNcf7X(w(cb-nZ3n^#*
z^cXRh&XU$8pYJ_?iF~}Y;PXx{zq#KmImVUdT#XlJrsG+D8|Lpex2RZfva~&mPQdhB
zoGz_1r@O04)7_2b^>`U;x@%oJbM(ZyXOA9OE?z4|)N5<*{Z!k`(f;yG*R=KQQTzhc
zXlq0BC|;NwSl2dFK7kisqQx^^wsB@0Wiwrrz3?sk{{nILj%JCDTkoXY>7;VAv(~v8
znZEP%IhV-vQiRvVx)&emTp2ei`T=#eSfaj9qI^62YIiod8LPn<&se78ptV=pWcpC6
zi0jTUA!n#lZnt+zk8_Kfdsk=e)?{z85iYc=TGa=<s*Bs(%+4Qe#fLQb0UgMiU1YFj
zxafhOzAzn`nY$(XIXL1&xk_6}(wSDuCK<wm`EC@!@9NwjG9spPNpiPexVB4o)QO8~
zhL4z*=yh5ikedfHvq{#O4Px=AzBD(+S^(vw;G#n_Tvp&TK4OZZY^Y=g-Gim|1NeO{
z{d@+GLE4(PcBF0?<*iJ2%NnpIE#dlEnrfx36V}(;Gy+#i2e6p2sln%I@-r+mnw_p0
z4X%L0C^Z)Jou^lZO1JgTZA`9O6PZz~ZWZFebPj~8GSiHkM%#lc?_u~or&5|dn1n;J
z=^V5ZC6#_$aBv+RT_n~GHpGLUYQV3|_Sn&@;-9|w_xd|dm+L!EpT&0h{ip2t<kSDS
z;)bU`f9d1@jNfs(eeFxfyl~#Gk9_Z*?Yno~{@Z77J#G8)J%_FM*1Las`|h9J`od3d
zJ#G2&-+glXN4DRyYxnXee)sIIf4l#ePaih>_U$)3xqA7FFKzzP?`Hkx>Azlf>y<Y?
zxpu`9zkSE;?^=G(+m1c{iI?z>({lWd)2_GA{?_*USG;i1jhC&xAMZRp{p^YxPy51(
zCl=m%<%Pd_<jRk{QRLefeRj70ohRtsD%0)S`v9P?qVEvN)wa()R>7KdO(K);SuOpQ
zYw&qFUe%s#hOX&PMhg`qUzL&_EOpxJPMM@{f}{;Y3#7QZ!*#v0B(nyb{z8GIHo-fL
zvCMiHE5re;Kt{#Qa`^P35r?(6S<EU7y7!B1juLyo^~PciV)1b%Ze8%3jn3fBo(@@@
z$Qo3U#NmVNeym$d$czQ=uS5`-F(FbIaxV)QdHV~trmQDwg4eUh=gA^}@#XPVtc(l_
zU`Ut4gJgZj1OpA@%3_U<WvH&Uy|V^M+nA&l)4MLzt?LW-K?z2*KH!^z0@+Fa4hT1Z
z_%sE1?Ra!EB7D4tHmoL4RQg0~`QOhSEm;2^JSxXBB~F*2o-yrC)w{8_9n$0Ete*0C
z(Bym%@Jv~)h&6%-Y!>f4{V(?3KTfWqO87qaPR-=bWPm%vfRh-YW*A_=xHcGlql;MG
z>BJ7Ab^@*eQ5zQB$fJ*uT@`&1PIo%kL6iog1{SpwQRA;Q0;^F$Isr5&y1^fh!CwRw
z4Z5sR*A*1y{hqoL#C><4&--~l@1O6Px%XC`I(6#QsZ&30Ro!aX^2IUVHUtZ?0?L=F
zC?rZ{3<7|Mtirs8*q(yqe9}Qk2HZA*9>aGaBZJ)_KILTw)R9^2R%R0dh^=U6>3Evj
zS+an7A7^C<F}?lk@x(Sfdh6L(wH-Y*nngixA^NZop3UgCo0?qWoT3Hfs92sN+U~*&
zhtUU1ZmF>ZEbqes$B^{76RhU5bLbeCN<TQ20huOq5-di_72o?MW3m+;Mi}u^k_06_
z3>ZnPeE>@^nI}yjQw)Cc&|-fKtW0mClgfH6A_VjYn-E#W@7)TgCn`90$V6s1i}WoA
zV-hBL-?P7-m(*Kn0GeI@Zx9j5Xt@kcPbyPN{tA2Sfe!&ZiG~S}1O`t0Ky=vJ2O0B4
zd|QiyBA=#g*!W`nVoGL{5pruEoyl(zFqJ}qq*1a2h62M7)_oiSvlK}R{ajSd)1bsc
z7g~ot6^fntOJjl#EmINbD2gbsU^b(WcP@2}IPgO_h%z;$itz@)dZ;wyoJmCjyoHjJ
zVG~eN?T}Y?ATakuStN#nAwk~T;f%tW9xWrc2^&IfugKk4OqMjTe~1VZ9X`TmI>KI=
zM1oNbI?n{Br{#hddlHjAx}~?e(|StsBan?X{R*4?9V`XOR`_DAft|~FIZZ>$s|?Bt
z77XHA4tfdfKe<yYoJSJU*I14^HO%-MdDf|?%6LGe)#`8xDEktj_J)uoss<V8Ses&f
zF#AS0tB~BWmuS{S-t3#QTnsUgGCQz52kg*Ic5ELFDdlSd4aHQh9eNAX41A8=HBD1)
z`mbJ@aMWdqjyTPRY1-s!8WYmtl{U+&4Vo7ovGUEL!$f*CbD_)rEY4DORT+PWHF0WR
zg`Y%ZAc<!XeSz+PSUp*<RW~M`E?HvFv6r-_gk+iBgSkAhWxIJY^+;+d_?rK@?VHA&
zYzr8Wzj9C0PspHe@@h@NNf-s`yUbajB}_7v3TBxMnJ}DkNe!5$URD^87$(t5Fhew!
z8zsn0Lyl;gx(G}-LA8R7vwvUm5N$|_K~NYxLZt6GG9XA5KZ--QoSP@?OTtZ7@&RA$
zu4G_l>ST!O>wExXZgqk2n&C*XyM_sBFSMYEs25H(Cecz61%tC*CPu2ImXg_OzT-_6
zRaU9AMCz7lKeT<Lbw7n2GZmDS%B8w*$rd-6441Oxe8+ZFJLL$Xj%<~r5%L=>pQVv~
zvhIYlX4sOZA|Kj^t&CWwF^zFkx6(Z!sk2r~ykuIAaCh`tXO+|AJ3U|b3-Y0~5lA!b
zXPb1;SJ>I9X&4!?qm}|^Adyk_?RA<0=bUfsy3B6L*EY8q67UIGbCwg8(55br`B(8_
zd3W4YY3b*o++-JaD%G-Ty;GiChlK;!+9)!nyPgscS4s23O8I2Ed%o!E87ce8y{^mP
z7#2OIYVL;GIuq#)dqyV`RWy<@W9xS({?N%RK$(r!Rto#_bShIUnms}nq1GL&mpb3C
zD_!%1zlOHh_xz#F6cGkf#=%q&?6Tu}!?KOJ!bUDz6J@WT30TbMHptsXw$JhXLVe_P
zww6)8GE$#P8lq{*_1h<1kt3R}yQ7;g@ph^xKLhtMtl-Rvq*<dGX3)TXmTZJ6-JB*d
zOv#P3Tt4+#Qd{3XcD=AyOtQtS<{VBqmYK_&FUQ<yUdz|UGdCS}806fvy0Jt7KvAwv
zcz;Uf%IuZ2R}3k2J;s=ANH>?VF;{Dc+-H-neZ7-&x|0k28RR!O=9bc&=}2)Q^o>s?
z4|ID%9a}H+m^$P4jz;s^h-z~t_i8zb=MkOzJ*;M2X@?EsGcao<UVTovz@TIG&Ri7E
zC|yIWN@}riUM)#t)pVNr+O{wtt&uAA+6)2k{GsLoKx%Xq&3h!kKdR9LEM!nBSu`UH
zQ-!>Oqr{x2G2x<?!v#&wMWHK5XHCGdsB1_pI5nwby3D6a*~d9fm>JAPqz(<9#oV7)
zBPEC)XcA##e1s3SC&O_L*sP@F+qUy5d;|Af{^MjA;l*&4O2guKd)*7j=WOo|d~gp8
zAOcU$OZDK8p4JD}W9BRLqjbhH9r(s%N{u4x%@UGwna+dsmU&zh1%06P-ApNmfJ-ap
zABa>qQaK!jxlK6f_0X4RV>X{<DVj5|O&4zZgI!c>y9|JBmfD1)(i7@)vj7sY5bT&g
z_Q7JX(6~Zygh@1rhlCc<3?Z-54$0+x4nt%F*aSmUp7Z^113yviG&TfHG>`oo<2%~f
zo}}rJt3+Z_Qn<S^5lP(icJ_NMjvzj&u!oOc%iuuWoH}FoELdWXL#Ub52<9z_TgQ}#
zoCnndZK`s$PBW}Z2(e(UF)w{w3irA76htOGuUTCsBmz3JHXR6-W<rZ+i4jG4S{;q4
zl@$lBnD?kBbJGGKlQk7B+=-Fe?!7sFhDu1kunQhBiYIT?n4_xMYLS?Y+lqv26$Q?g
zsMSI7cn`lF2T!rB$?@r@7{7=|=eAGBAZTQzqIenv%>j<C1lZ9v5LvCdvkiJ6zNdf{
zCRY#xAP>r;%DrWIYvVz$Hi8ky8$2#khD%4R*(7QR34C`NZGwfh6(nv0gfrd+A=*v)
z_@gySb-ZPPX~~<mEIk8sn=4PNf~FGI3kw5{_68~#XT;zqcr@SyPB(uiz!yD4ULl7n
z@!-M1NoY-!Q0o%{C`W`q8VJT~uRSf{gw_ypCgZk>JbI>3!RSKpd(%mL3Jr0`OAykD
z_yjR6QkhG+Aoo0c;AUX9kcLcN9DTOXKN!quaTFmC1PJkNf*6=K0oEL-9;SJ!Y#<EU
zngyhD;W#^B`K;2gKoB~708CMqLCF<AWfFNJinmb0n~6q;-MsOO*)bor*dF*zGBt#;
zB@s{gdl`$>y$CJdXdwfrAAm-B+S8boDCS8B{<oiqp^of(TrdYz<3oC0q+%!j<L8EA
znC~MctKLO3Z=H|vN(qb7*aOP|qBJhW1`Dn+Nl61wG@#bntI?5UvmRMT9<B?j5Q8y@
zW9()!16I|bFq6~L9C!Q87SGs`_bE>#OJX)sYmp{?@)$9xFQ-9;*fnFrGsN`TYPu8Y
zbwCD`PY4xA8froi+n6d(dxQbPV+C&paj=RkOfJ*qcWbe+!QvF|#7yWm3V^mcXB!~Y
zLJQ7tfnSl|NZgC>sop}VDZIlC8z}&bND!06V~PmyD&m?9e+Epy0BgkC5c9A<T#UeJ
z(^}SmM__AyeENf;##C%d#>zC3LD0_HF?rgMD7(hgv|TiS#vqE}JX9g7jXR%rh+%+^
z-R4r@w}LInB3X!Hkn#8Y0Tg;Fuj-i-Nx4G;cOvPmA)~H&%rUTdL=eRR8LlX_^$`Jo
z0eP2T1C9TMgRI!-rf$9{Td=ee_Rgz<iwU<F85B`MA!!i+u5c6&Eglx5D$eKw%%d>z
zY2kS7`>~ji`HNhMi5TKN9{rHf&CCG={5KAI$sEN>J24e8#T~U=fET(@(2@9`!CEUd
z?_&ExRjx3FYAXdX%m~&3;yF(*yBnAH#$^=Oln>lZ_z;b(Eor1>y+7i47ZZ<*enu&j
zBE^_3b30;@AGPys6_-I6<W{tG9Agm-H5Y=z;)lYUHE>7JgT+gEWPE0U9vIVDnh`v#
zafU>2fVVba4m?lLP^)1=#qJTJD;SpoRNB)d-twkDjW}9#e1J9WN;5!Cr_4VPY*Yu3
zs>wjjl*A`BOA5aWq%>@MNS^sheEbZ%niPfJAcx*!MCRf0gL$(g=5Q)~W5s_o;()C~
zr9=T}Nv*OQP@fZTj-pkJ;p8ZQ2qeJLL($3@qll$7QFG6M=UIkh!B|R0L^;*0XSX<X
zwLVT~LJ<9ybRggfU^f0Z#JYCS=Ox7%WX2E-H$}|>1XnjDKOPU28F$j+>oEE!Z=Onk
z-i*ssy606qYFzkZ->AmS>_{@xb5wg)H7+z4!xFlYp`kT0SJFuBX8r;)_JF9`o2SvX
zxsucq1KXL491~|e2NUZxZO&7mFi2b|SmoMvR#lu~-$T~yNfsjygtw`}Dd<P5hOTt1
zL2Tku^V)ninMO*J)OU@Mcb2V9xC+Q+)Z9iwW_^HH*PN!9*&^9%%s&%9@tCQ{2CT>r
zSb8Xm*l0<(AD9kGa%)gYKMM`Su9}9Ng_|B9KF(Z{c%~AH6wPaWLSiY>h6anu=pUJa
zA(8)}a5&})tU#HKhdSC({6?BY+47)_@^~Av+{Wl_$;vn*y^*O#a-2$d;AuB{Ky!G*
z63%T7#>|;;*%LN_TM^Y_7y}+kG0=~TZ$?rG7_?aXW+4dD$7S+}<N9;f6<^sjZs<rG
z!zzU}GRHA)G3-r@hgDO$Npkjn&KL+$Rw5x<-rshFOvlb!ZJ&<MmL#0hz+|u6pY7~O
zz14A66XhGMGg-r4R*2+X!HX)bnLBG8t&6E>ly(^7MjUS&Pi^upy>&?LdC&#yRPHw6
zv%@Ct9HWg1W7*Kih?F-4Nw%yYdSRaH-TGqWI;woiGnmQMEo%AzV~0FdLdx6VpU()#
zjZ4$5v1DD+Wri2li#J<o=4b68X^$>vMthQY)+qTt)Z07{G?QcFe4)88guwg5u8eWd
zYFZ*H%s^`EWO>5(b8bAz8VL&{AtQr9ye;>#*~!&Y>Gx1(UhjBW&{C2w^S-~+ay&GV
z^(8^Vd0y^(8*;_{W4FHqM<>u^x#dzrt};87#c$+0RA!Y!TTU6?<)y8GFUe%LVh3gP
zc*d}AiSi~tP}ikqc}aKS%#pJ;?r#t*{b8vfo4jKnPghP;Pxh#cG-ZVw$d_jo>Q_gk
z>N>D+i5$+Ee%QIR$h@7<RiT{l((72x*b@r>J@JJo+rum*=erDQH~7)Tc~udp<b>ZG
z$YynYKA5<(f=~ITmgRwoRD+^y;p6G?ReZ;ob;>Kybx*<#DgDWnL*#r^%6=jFO!^ow
zKYdim<>rAb)Q$)?+;n#iNthWw)V*+0`#F8qZt_2a-QK}cvm2J``73Bo$94UN!)#B^
zB4&z%q-W^ucfMD@yYp?^7p_}VN*YUhKi)ae`|6$RCl_9F`sBdPlf8TH_;~L}8*ZN*
zIdyW;Q*Jr!z~A%+_AT4j%nm*G)a=R6eD?33*PGg2?Ul2kqmIswUUc-DvkzP_x$3~_
zdRXmfci6(C&wcHIv(~)&z-k@L4#U2mw(!;Gted>#qKo=&#bG-5^~3V#th;!8=Jywe
z<jeE=gI}6Ax%lGYMJIfwcE^`@y|Dl7*1YcRue{adJqPVozPxK-$NgjP-+tZV`?i1n
zW%u29`)hC8G5^%J?zr|>U*B={@a@}veDw!5fA`FrHjf;B?JZY4{d=Dn{`cqXJ@l4i
z_8&U&*=<*y`|cetJ@ezgzG~soJHB-5D|URTSAICV^=X?|b)Mh3@76Vw_dT-a_u0q)
zkG-G#{42iyjz7L^?>qke+`VV-dBxrrT>p1_UsHPP=7-l^vUm75uh_Hl!<W>T-*VaN
z<qu!>-Ie#g;)PH9w~<GG9L{+3r}-J*y8AP0^7St`&E)<5L;R+|CqFULxqajNw6yBQ
z-D?{EtCUuswJqCs)Q(Rt-?ih!M|N)x*IvKv`DcD?$F`ZnuRkg8-ZFpPQ4fD*c;2=v
z&)cy7&^JtV{&Cs%A3gt5$88?cfz6dguh{+dE1$Gi-|)Q2m+xMay<*dvA6<3mA$x0g
zF5i2|o}>1T-n(e?J)bOJw}0mmn;-t$b2pDpy=?E@|LaNpuWg^KZ@BET`i4hdcHM)u
z^2<NEbmaRV8b9OvJLQZ!R&GBPd%V^54js9lm-ZJtJkmS-HS7I7VSavP_)6*c<ezu!
zeAa>PH}8Mm_R84u?P;UA{o|jzX~)&S>fExdmfiBfr8lnq>fz_=>9yl}r$0Kc_w#41
zzpirY^Ln)#jyZ77Edv*yKJdcs%HKV|v-8wd-*27#vOm4;))jlse&}!a-nDtr?gdw#
zs|!B7pg#M}7p>_%e0FyKmX+O=51h2=&IiN9ooBzae)7h1R$trtt8cO3yLnGOy0@Q>
z_IK_`d-7WGy&k_Flq@m1RrkNBx2q<-Z<MvW;MLOE@~C!_*XNyIH}YOmTdo(@rh3_@
zxA#V-v@<QbFVkacooUu$&mTJQl>P4e%dfA0pPBS+Evas=b<)lEo;<o|@9j11w6e|1
z#@0-RyIBO<9r~O5wcXh#7lrQXv%{Kiuar*vj7$cTUCG$!-sFMm=2w<Neq8*$#x=HY
z=uM~az1!H>=*_E=+iq5W<=W11BeiWa=Vr$b&t@O?he-d#Pv!mLTWWVteLEYOTA6RU
z;KBUeesLIF_s-D%kNN4)+NN9{-uC{9iKE{?A@A$U%#r=F4CGa|w7BWR!V6Bms($yP
zznM60`;!;V^wyty_Qmthc=N^c<&KXo%=SHHGQ8;4rSgu6+a_N5*=M^gA9}KDd~(gi
zd4Dy}Wc$?rK{NW%M@O<P2gX$f2S%pr=}BpQ1#L_<vmd{hPI{b?^iP`HAhoZKmg&U*
z2mQlIS=&pf`r&k7Y#<$&dPz3?KG&{J9Nlid_(|>NE7P#yr`9PPQs3yBA^UW{?E;Nu
zH#=+pi{*^Y5j5B%SJ3DryFSk7d;ZB&qh(Ddszd(z{^{wJJBJr!jda5&PNqylYbYD8
zjJW0y+jp{)yfv~iyV&+T<<HVo_WPsOd4KE0sa%=MYnslVsJ=1l<-D~UR=2Z(?h)md
zoWC}gAMGB<+slV?=JYvwC}DPMm}d6!&`dVvJ4@rN2MlE!o;s3!>(wJ!e~O=d^Yb#f
zrIS@ZeRJMEE|;Gi7qZJgG&y<4mU&rn;(|$i>SWH^$>cqMU(Rp-#Y^)Ke<<#0y6!$S
zmyD!L<0p$f1HU-H$UtVE+cfJ2siB;o<#{z@gc|5sx>18wWZ0&Lj-_AYY0<1#)F~%w
z<GF;z5mcuPL{*5x@|yX3Jn+X)oORGTfNawC5clsA*}joA&w)vcBaZQhmLR0(R~Pp*
zJ@ymx8A@z<xWagQP?}yrRu}?~$iS4%LD(#rCB?5<AR{IttDTM3NnBKzD51AY+&n})
z!ZTzGq&0H9$i>rOA@N*!kN&J&u^4p_$s*>Bx<sHn2OUr3vST6={`orJ&v@S*+Fq3*
zpN143<*aObnqG4=G3<PmhE&b<zXOIJ>(TX@L3a;EG1Cnvc_muq$`%u%^X2LjQX2?M
zug^G0=Bp&r&~eTLB5?i=`<sxyUzM!-d<N&Ek9}Aq6@8T*aS1Gc^i5xQ^pZb(jbG%E
zQ*F=F{#QNr$fI9)@Udt9;a@-S`Cp!P^25J;?BPfM@Y>6s`G?ou_W9R+@t8+{`o}+B
z`rg-FdfI(IIp)So|M0$hfA`3r{{1_zz3emp@{yNb_t<B@{Ic5~dF+yJK6KjWfADvI
z{efTp=C1qx<E~4e`Pd(i{`J>Rc<w(wbklc!@YsWwop#?tFaOL#Z+h;%58U+DOMdr@
zOK-dFXUAOk&~xAL*aJ7c<&rPlb?Fy>@Y7@d@t40l>fX<O?^4?%^s*mwjM~?J{p5T9
z?y-xO^0Sdk-tJ|It%y)kvsYwk@1t4b&y#LRT(gwDCOa@t%hsKj4SUW2DGgm*xn%qW
z;f?*t{GtnacYoUvp}t`-?D_H-%|K}+zq%olJ9iGQxjk9hy_5O3JNVT79Vh1F%_JS)
z$v#iNF)SL~I5I(4_a}*L{!k)oc5X=*-Zkv5+d1ra-vEv+WRq{Z$xVK^nVY<;c{`fy
zu;p>Xu$9acpo_aO)B>3n5B<+}U^KkWg(CRBy6b<1j5t%ve;@jvquCykU;U!MIwvv{
z0<n|vj>p2&ns*YKShZ-Xsqgb9BB?HwvBZn}7<IyCHZy+l6pFELNyW_{Wuk#Keoj@9
zcZj~7J?`jKbfctGdH3CUwnFm~V{D0eQ~T+e$y#1^tPv!92)!tkcCM2l8O^)YMyhxk
zl5j3B;b~n{HrTXDo(yK!li=0j<TboYv!2Vy+C)g5&xAc8fjXHTN%K{1O+xQ9@x?lq
zy}7ACKcT_a^H|Ob)NUOMgu4+>BM`s}zh_HrLj-HS64#@pr?N649?14I7#3$Vw0xe{
zlOe*VV1xKp|9M03HO8nCOs~IZbgf9`gL==<T}^ZvN}tXQih6>A9U=qde?u}1yN8-Y
zsCrxPb0jA-nQVYZe1SBZNT|#Fo^xO(g%aV`$<hT>b(F@tTi{~=*$y_YspbJkhPhcj
zX_v<Au3TH;UC$F<6W|3^AP_QSOSg4}S01^>W?$l(LzV3Y%#RVvb>MSy!n(Ov!t8}h
zLQ=|R5EBj&0&FNYRdPhA-O*1fJ#WEj^!s6?&POdb#1#9~3P|&YjERQ0r>V|bau#A=
zL(;**>-N3^2k#^aC5d5nqyif;ayLs5WvY;-&MeAegu$#U(j1j(lVt}OolMydgAjR=
zkXdYuEiXfDi)d`bNy~xGQks7I*2LbekWT_Svc?h(=dAIoxFBWI?nqk|c2LFNk|ATn
z2(<k6X5~6jUeXiS5IcelF%rd}I7Jm~wGfpGotjm<Kq@?V2@grqCOpL+i4l~)fc?X<
z!Q2C#7Im;6u(vYFOfWO=iI&X{74{&;83a#~J5CdO0Qtwh4%K-vKm!SjbDkhf67r#>
zLWrpjNK`z<4}`SVqn1>R2mjL?+``-!bv42a1UQ_BL9{g`WqXt7{Vs+?DtOvDGnC92
zG`)u+AI)r!15u^Xvqe3T8PPG%vv2k-!pO%S1yt~At`+zeDOz|#5|7s=Eij1fws$X}
z5A+3+S_t^8g3`buZ=nVz6~Sweo)sZ4kHil?zr3qfPdox8M?zqt1ume`4cw<0Gw=v#
zLQIeUbT2-8DW;A~zD2wyqoG+cWS>h3GkcMV?0kDrX7-{gw0>9@n`afNU^q;jqrHp5
zW*O&0VB2F8p5jo976R5zn{;vf(y!U{Dmc0KakHSnSjyM1Z?aI9b`#5tnp-~<@>#+w
zWT_7oeMsCdaxdScv+r73A;E@iNFb|ea9oSmb###oGi!1_M;;+P;i56e@ELb~t2Zi|
zwL4zY3OrfuQzlh5VVb$yWU|P5YiAURNsza7Lrv!E%|EJ0Fw`=qP;0C{@o6HYd>lmx
z6*dj|gfb@Flfq9aoHl`V)AK#=!j*1y)vVeqZJJV&n3avm&dY~naMEL^5;AFwBTuq0
zOC8~Boy^mWG*@UnS(eL6<{7gz?HcXOu$2yLIW;!Gbw%=H<$kmI5Rja7$A%{vSF?vl
z0<&4tFP%3*-O$lt5|L{K28-Gk@CdS4hFT-5%wS3t+PfcPjgqyg9Ws@R->E*xMZ1xP
zG#tgUOjhFT=IJ`?p0f6`-Ra1c%w2_?LgH}J&@D@Al;0h$w<(gir;^#Na5X<JHe|NE
z-cI7H%8f5v1Dnv5w{<;b6lPa*W|cZGH40Gaf#A1KgL8U*vwJ9$Q@jM{?#6d=*zHe6
z^b8edx5`Hbs)HMSXXsQnP&H<S>8w<o?@Eh_Fe>oC1fQCe$7W=?f~zooW)6+s1zE97
znVuf$b~|q5ZlRTclN0NlbeUB|X)hxK(kH9FBxeQ9vc)Z#9F+-_7Q*nD3|5A;@|9q(
z3Z3Q(Bve-9`p)b}D&yI&v$ccb9Xibyj*<~_Rd))}1T)Thdff+~9>Fex{{GRtIUZ&%
zlBv?5mYtj_GyLd$*1kH_Y0ySPoe3o-yZkg&T<)M%@S6j#W|j|n=YgR7Y<F!yrpUjB
z>`*C5-pM#%;9V4&`l=2kt0k$n)h6DgMLEmJ3)vgNd#0cx6q|BWiT#Kc{f(jw%p2hW
zqcMF+ub87x1MV2qWo?5EqLQLDAhp>_HCGYLT?6rni^|mSreA8RAv0Povv~_FAkYzH
zc?T8+@w9PMA{3hw1AUowJVa6cwT9xI#jFMA16@Yq>G!Pbb5oHa=iA%nEKliLGCS=T
zy2eOOX_p`>8xaAK2e-k{S1_6e%kpkXicHmv#!k(%z<w~@{qxUbEKHR!Zt!%JD#~>!
z<xOm9M_VJflvYRx_Q4i)!?0jnCL>JgXq>tv@k9b5u41+qr!YCqAXN$wGbus~35<@G
zCJO;<piVn$H$hq(N%LM~f2-2PGt!Z?4W_~6Az*qN#%+&?38)&=vRHk>4;}hoL&BIp
z*%ne-GTukhi9TZsmw3bTpH_>0)Dl<iSc37gFiED7T6(b<f|$I)%8)^X$GtwKONM^H
zbT|J;u*(NRDM<NvBCFAOKL{NVEJ7d&h!UazMJbRN<Fo|k(@kTZYM~AY>6;>Df+2c*
zuuF($9gRqt>ED7+<kSrWp;oh#(J7pmp&P-ljP@X%c?cIs`Hx`PGibhej>u+pF%>l=
zt#S;XDt=1_riQg!+nB}-ge>4s4@d7FM?_*fJ4ryv4=n~LqqGcxq?B^c;2g>*Lu7LL
zJMgQ~8uYk)jB7sYW9WwMMw|XbNUQ=T3d&>kHVqD#*P!W&r^|e~aEY{}A8nDKf}gh#
zjTd*t=n8xk7Bo<?l_X;I4_1g+JU(w0!Df2I1AL*Gf?v#4vAQV5@1@gx8`WGiTt;$%
zC#o@2PW+2GRu$>P<5$>3Y^U(2O*`zZ(lbfBmKM*z*O#g>8T)w=uz`R%xiM&uhu$E9
zk9X7K1#}2bp`y@cQ>ES}rfv8b+t7*|BCR1x%7%b*Pz<gp_teT<lywiY00!e@Hns=F
z-RE+pOyR8Yu5~SOJ(PF{l~^{5(M*Id-BZ)M3C+oNGbXL38?07DPz!?GOVUYmtG|Xe
zdsQwf%^*6Gl>Q|^W0$-WdW5k;3n{3eHR45?hFc(E6~$l_16VqCMZSS%6_FzFZF<C+
zM~m=2qXIlvbd^UswtJkE5^LBLX~NU~CzK{V(I_UNsbb$~0nuKI@qx+4zbDn8fu!-I
zo24wWgqOk8{Gk(LrH|X|<sJm@#~3ri5GIBul@=HwyuDU>`hG20lor*9%prhg;sbJt
ztgu}VF1{?_Lo}kfd}uX$l%rqm4%gTh-tF<EG(5_~dK6%xo#~L3Q}ogl7c9|WaZ3>K
zh=~NgQ!~4XZ*!KosUQt5?j>{lZa4_ChV?1;WM|8s<Na2aD)Gt$+4zyWv9J{=Q%X~0
zOw9^2m2ff<Xt;mRfX>!AQ*VB|05#Tg;O*(=Jmji?ClDMAiqFRh_0Q-y1}-9+G>@ke
z*=oc*ew&ML^3UPI<6$^xZ{;r#bAkT_PUnJ($A6NykYkRbNNN0u^iLo!NS}a+bb<T%
z-=#nLZ4s^D;SrxvOM&`-a-So$eVkGx5iv!Y)*{mDlIuBLI0^Uw@T$@ExS9%|g**;0
zj9RB@F&yoXK`5{X3o_yi1^yrqW{L)iD0J86P{YIr^8H2pIr%KK74uQVn<{kl#n)PZ
zh_|@h<{-KX8+R~_kazQ<@s4vUHiYWazB8aGAjC(;5;vW-xh-B+Ggr@UcF=?tf|`6d
zyCjG+@d8AtqO5LKDu%HZ<Dd$u8O?~Z4PC)pNeD$UF}Eog<uX;ZdBRT<Y7!9pu7joI
z84DW{;P{Qg5i?(CNh8L_d$YVpA+nks9d-$b1YvEM=WS<(G0{kDVl!hfW62YbX4W!C
zbAV>L_?1w;e=<?&t3x5BwJllbo5|3&3|ELtG=*=r6IT#Ndy~xll`M>8A+kA){Cv`e
zzzHRf!?5PZMoC7D6`$!TH74b%f+e;Euy2-?YHUCxgfucmrr7{tfTcJ2;&lW235+Qr
z+z0Z;G{MXF6VE`&l_z7-owV#}Is(+Ia)+4z2#P4?CpAJ~NQoE?5XV2!6?s`Z9c-H6
z&yWrWOC=a4-im_l!#!B4o{NEGU5nt@w%QOPggJ7;0~b(LZh^ioN(~7bEt-4qbHXCP
zL2_K;p!MdMi$j=oe;QHbh<>o3FEGw@P;XhNTR%4}oysC>4-S{lTQKx8Rj_5aZnOx@
z(_7*ON|&KvErGO1nh)x=7(ODvYC;BN!dK$k73Bp4Mpr>&QY6DO5YeVPd3wU9;@|)W
z?+4rgddoQ%7SnEqh{R4ws=$-r98^pU<g#RnC$*k^H4z0T>H;fGMlzQ#NYBf7e;pE7
zd8dQ`dC%_APA)bVVN>=rhp>g%c$21&UUSVD9v`W5_oV01P2I4lCO!ltZ~9R{rEKRQ
zfFoMLNwd1KHp;+Tz4A23Y=)<Z?;}DOerhnikv*$V0Fg9~ab3zG>=P097dPrweJ&l7
z6Hp2K6)ti?eHLf_s5@v>ys<Tr=CWQfR~(xt1*?UQE;$BdkIUxQ66RtPPs8Hyb6Jz(
z#i=bTsKTuoEh(!9g2dt+u9gVUV$085TZ~vt#e_fr<MpIZ_5wpyi0ra=*HJYGbt|bt
zq-;-eGl2#mcvv<FN+H8ZqZK<V6U9m*1T2du!I>2Yky8^SsHCCUs^YRRgVgFj;XqUk
z=1S+`o3Wh^U_BS$`9G9tL`x#tMD=m)6FZA-vY%3P6JvOf*)vy$^jt(XeRiy!N{xd`
zuxIX+;vMT0TEc2lij}(}9O435)d$WSCjur;Q%`mX$XqAzEb3E2UGmJpC9%keIqFkS
z)G<?^=>~`|6|vY^tFcZFP|N&?l@)Q&THTN$fj<!DDn_J6NV36DavZu$n0FHD*I?R<
zIIsvnzO62O?F4J!(M{qM+}tkH1Q(JxID1^)EXh!F`Xs;vEwUWZv_VR$Pc|7X%PDO$
zZ)CwDQR(Q*Qr@M#`IKp4o`8vF;JB>Tl%mfI=>_q9Hag)3xEl%C!nGL|=H`)S6g>lR
zn=vu{0@eI<OFo#pn6pM>p>JMOiX__#PB2_xb+i|`BL-b35n{d+4x}#z`sg{#%}yN@
zAmSpm8Q&9OuBBJQ6-gwmCx#d9w0LODLS!%*#fmi`h6U~+2Ag-TXw}>WC=cU8?^+<J
z+;a{d$`wbIa~d|CJRumLfuF+_<)^z0SMZFJS`K`gs$r#V`G4g{jjO>FiO#l)niSVM
zEm}G&gS<vzm=X9OFpYvV&q|V}y?~DgFp{jN)e+a@qU~TV*lJWCTzS&$Po&I-5Wv14
zl)#I*r5WtyxNTT$iG@Q(x}l7hxnwJ?FdEW+n8aU=NhV5^j_IKg!8inJli5hHf^j9M
z3}HyZ)TZ`EOP{I?iLAmR<h15P@Pj+7(39o=Nj(zKyuwepIFK!;EW|3@k}*!5Guh;F
z$a(MQ?p!i4mwYaVKu%3fCDE28*vv-9yT}v71ww+%mnJh!F>Ue_*oj-+)TvWIqdgkJ
zKFNioJaJ-h+3+TvTussp`M{dZ*AxXSp3!U|U=X#swAxv{E*wkYhB}&6t^JZvlVL>z
z!Uwl@b`O}Z2of?tQ(E07E7H<zrMp>yxq}QN8hNVpT(2VH$IiM=<f#`5<auac-bm*^
z<HIk=w~lT4lDwmp-4n{o^gY?av^~COO<q50YGiipC}&qJyZHDG3)9nkQ|`FRAyd8f
z+M1gR%Ql|B<c2C6yEeUZ@_o8wXm;#*`k8Fu{Prn(^27J&mwdXm!wlZCRa?i1JNvB=
zGU85Lc!oQ+y6hj{k({(P-<rg9msDq0^*$}fEu1dWZC}1N$`#PCfytbF8^>bLEjYHa
zViPtpZ1b=}GVo+|4vv%*EK3B2!Q`Y>)Sre}Jixs6&FNhHL76eWeVTp(s%AV9;xphp
zk_b$XN=kh4G$+@;S&#t*Zt;^+dPdN)nnWh^fcr2<GWdyo88iDs=Z~zrAs?i7JDw@q
zzVrj}NVY+|bl{3nmj!8#^@h^xIf;b+nl;l!Q&Q@CgjjJ>%BS|r(}DIh4SHRPJCIy{
zVrYD8qA3HLucWbUAl{1XN<MfEW6d$D@aXZpiq#neoj+2@HKsQ%6#43FI6T2!&b|jK
zsiGsq2zCQhEMqFd3J-0=m7M-QXrV=?A=Hl;%1fJ9BcmTnZQg{V2V58m3?o#0GB+@V
zAf2{~5X_bhP7f|VC2hgfO=c;pHljWW-rjQz)+JSYRkXbW(_qMY>OFYn&tQrxRHNT|
zWjdUX8Jc#0bPR3tQyZzkH9?)m0At}nYr)z;>__0<=ZX+|N|m;%TlLe8G!ZYe7NC|=
zLf&U%A7*%Osmy`t@fS}*wi*aWy=(F`p5CH*q(SxszZsg&Xy8{;$rIkTq=d#0S|G(i
z*GgO#R&lEY?%Zq)B^53o0(bH7<1;QBRpTPQVU5O~tW_AsR#=FMEG!9F;tE!ILbue!
z(=;5EDuoT4gM*-^!z3VpNo`x}M+)ACsuwXl{YY9+vDyk{zuG1V5+Dg?r<ey;!c9*~
z^+~JX6ECKxA3Ya0_+SsyF1gT5@dy00)832oo+e8b1o830+XyYQF&kEvc-aBLehhG=
z1u$Y~2e|QO14aaBybOgnz#5Q&RHjJ?B#@=gSB+z=bi+7pg7>gYV$iV6kh{cDLP;R+
z))f(=G0?}mDawFOp~Yh$%=vM9YQLS8UI4l?Kt~aZXRwS$@YYrg;dfMgki2z)pTe(D
zjN_T*8Mts_e+F4R^W}X<nOjXGa}W+Xz^T#CfzCZ6=@aNd!`I-TbWsdL_{VRgHb+#T
ztZvw{a@)M9Jyml&5tQDt04*5%!bdqrM;yNRSZqbgrelN0MN6Y8ScNTO6v0ot7v*i)
zEG{3%HAYbgdoW%gD+T5WnJ_Ydx6*gm{Io%^TboPG5y8&Y`R}1tq!ggw^^N=E!kbd&
za5xTvQ+PY|5<wv->c0{Dh~pLxX6tdpT)~8c2%bgOyh-|(<j_8mZZ67S(j1hsU=o=<
z9_NXa2g747y9KL=3o)aAwwEG^TKHdr>G1PUx1bPXd%F+pHU#US9nQ4j3i#*Yr<r1R
z0dQqU(qJhoZ4#pm$MX)_cKZ#o2#(zj)O_QaP~B&2ZxqfO=%suR??+Vzq&;;(*q!s0
z;#9@8hmT8jc09X6{yxz59hxTN#0{;`WrGK+q`Zr!fwviTr#PNiLW!C+o$}*q%V#K`
zJ|pI|NF)ky#{{cFHZBMx<R&Y@q#YfrtWGCWJgGmF!ilqqj1AkkhopcTprcaQ-ltH(
zW*Mk@ufjMLBEqoA%msd{mdiBF-SpxIXa_<drlWrj(6(v6cmk&5ui5-;8omGj?f+8^
zPzJzR7m9qcii2XBD-?4S5OD`R|M}_W5FtKeaZ1GfMQN#p7D<`wf6LJb4${8)jnVgn
z+p+S-qHRuWtv!SmvudHj*)i(GLpO@$^;4hA29@N{QMF+Nko9b>EANB>KR)2iaubgU
zjt=)hr_hwK(IAUV2T8YG+T0Tw)<e&gc3a__r&EN>kdq@gD}g;Ej#`^-VJYBSjO~&U
zI?#%gb|Uu4Nt^1GUELQ6#&TOyv%y%JD90|<V5-3nFo0sjv%ag0Vl`+k?_5jYm+xDj
zdftkZF?&;HthzwYzs;esMf}~t6kFy!vdo@HgxNK$Ofp#AW}VQDYwrf@?z3qbpKMO2
ztrcSqO($u%fKF_)U&?52b#gL1Lfoft)HW-KN}x><s;@d3LPmq6qrtgQmTVCT<X%BJ
zNu}eiGm&JubgiC(vDW~qDo|$l<~dZi+msGO`7SDY>ds(~Amb(8GB%NxxFb4OC)sF1
zax_MyX)$BCSw!p(lRiTwCmit#Pt?>ahJ}&@ws(vn2=iphBa==Lc(Y#G_pNjWdM~bm
zrdnO15){T8h67lFXtIg9SH9AGE0EjNA{3A^#Hz@oX1e79(=wo~K^7zWwr-GDtO=ZU
ziDyDOk@GE>^+@dQ+CN$WdVH7<T$Cwnd?`#JM%_KW_Q4};zl~fO$mX>5V8jPvFm$zG
z%VhxrE|}1CktOdfU{c0*V>w2LKS@tV6iyUYwM^w=lY!pbTB<Y{A|?~WB?FFoP))UM
z($fMfNZ#RsC!mfqFw)N3A*zdgG&Hzb)+gG?a7esKKq~e!Vt_`-QMc%nhzEQ~19yVG
zrDr1p>YIp`achGyGkUiXe;l8tK~wg;ngr}?CQ@!~`LWB15V#E5a(Pw`Sd(r+ja8Ct
z2Agfgpvk6#&dyo9Lp#j<WqJyAd5gV{!Z7I}1mUaUlI?5t%0gyV2jmdxQxt2bhj3N%
z76bo9kS6Si9bZip+<vyttF7hZcKEj^kXM*@&aY1c2U6NZCbBZa**`fzc7%*gxGUbK
z<+}QSaw$|ViqI@cgtlk?i!&m1Ir5*xccFE~K?zkUnkEjuFqM|1dmKCmihKuB*69(^
z8vZcr^P}=~&v-476UC`mJ^})ba1Nqxgeim@(pj{;(Kmz!$Ppd!GQyXU_$n!X8UvVI
zOjzKxB=(o9$ONU=U_sr>B*m%ZdT#YEmaQcata3@8%ZL*nTGLPoe5fm=7d(Edx>;>j
zZ}IIkgN6a+w^nEUO#I;7Xd8r9Em~;9agfU(tmd7JW_5yUK}zUs%&(mxV1)Nvf=^9w
zr+1(SrWj-h0lcIhPF>Kb%FEq#C<rSRrY81|loEho<fa#{uweGZqG81Ij`RMp3#$Q4
z*V(#S!z!oK5S~8Zp)j9!mN!IPGM-d<mSA8NfW*}*ngQp!5i;CK6-Jf=1xXgDD~WB?
zyOSMcnc4A;@poo0mn*ik(ZETrS#@xES6Wktsz2Dse4m(8MDP2moFLt_(NVvi@1gv-
zV+wvNDI&XvKwgNA4Aj@Mv6|Vu^j8({Q{RwRQta3_;ssez^ZBIetW1Q7l@$;|t*$M`
zF+On%JSzSLa2woxgNA$~s-$KQs`t8WYNX4lX?e?4y_;RZCcuQ2p%q*=j0SHTT}2+q
z({`SR=14Yu_2qn}mNG>d)T76&TOJ{aWJZ0Cb|)=MN&b{j7l2<ikbFtn*wvsIpYIn;
z9#6gGecT7Ph&_v~I%>g=v*9qa&wkBQ57CLMJrS#1Z1?RPdJNyLd0%U&wJxiY`CdM~
z6sv3#-n^(qsZ|ri2xfsv>79WG#h6vbNjvZ!55WbaqOvXv-q8p@Ta<HSXJ8iO@1W_&
zSITR`gwwJrW$(RXP6R7G9RZruP5W*jI98GRD>6SAR2I4X!+t(CO8L*;DcK98*=vpL
zJI<Gf)tb6ZJ{uk>%lL`cO_UkrA1@>JDxAA5NxN^~pK%O$g;(?;M)_;y{du*M^Madg
zuInXX<7^loIa05LDCui9d#qH3Ll{Z56!?~dc8_BlCdaNwzf1=&>(Ww2rx}`9)rd%&
zc6bb<Xwr98<($%t=g4S@XQ!R=Vsbh@OHV;wq(v!7v~pBsFas`jOp3O+paCk-h&Rh(
z1W`h}0c3NQ;40j#qT`P+BiU{oYM!=SW8AR>tBYs@7PhKOG}r~FaIzE;#bC+8z^+}Q
zGR(PwE%gqfo+k#+Au<F>(qXyPXeIH+Dz4M}wn=B;#HW-*9g!IJ7^W^d$6dmZy#`HK
zYF6K=xl^uMHzFb`@*p*7Fn5XwG=E-dYsGTnkEnOk)Z$T0+{qFI$qa$zGB?eyIG+!1
zmRa^}`vONrOF(>D17kNDj9)+-25dkE&tNTg6{Z;7Sp-ed4@{Uy44E1>LXcUzMWAIS
zdX<czHRZ!ilJ~f0xW<f~@D-?w<>Uil>^3JPS8n2|g>KAs5QlN1XHTLXDi`J>m$R5D
z@ij3@_HK8$+d0yX4^OeifaGaM=}j;vLM)iw6URE0-L08GN6zPS-~x#qDbl9`!>(eb
z>@8sqv8P@+CNLXDnvj9Siv?m`d6~4+5KM2cy2?rk=}0QX$mF6&;|X}X8TeWdwVuGk
zJ7ShrCD~Op4Uz`KS>7Z&IfiP~CVU*s43gBwJz`vgPYa{K0}42iE6PnE|5+1h6r2H{
zO{hjfi_7PMhLj=mIP5HS=-Y;vKBhPoL+xZhkIM=s$r()m$QF|y$Qo0$gwbCSG8U7b
zIY?p6w22%nKUPh~*@%iKq#_CtlGvOum4SO=ZTc`n9Ia#50K!5i@%*_by~JEG`#Ftf
z^k7GaM@J&H`0PP2iWCUXKP;n|Y_ot(DnWdtvRg5Hji2`PQ_v-5<){;uxxmHlCKkDD
ztB(~Ws3u6C6zM0S;LEQ}M={HUSsjEhrn*N$@EAJe$UxH36-B{KX>qrZ5^OLdG?4`m
zCC^P@9&18kWo-PWKrF{)d@5XiJTf4fDb6RX^~<nFMra|MwK&lkQx2A30XSiAXZbCD
zAFir-3y2imqLM`nIz*2o5vW_#XG^hQPq3repnUj%B;o_UOb59e*lUFIPSrfX<EdyY
z3^J;;pt*~IOuR%a9$%DrL_=zck^jW=RP*g68znqB_ReR0dQI+-+9of-#4H+TBQ`2J
z!^na&#_>?|xre~bK*w!lgeA{SeX8+U9fO>m*{MVL$MCNr5;~ZRKSP{4vFU=5$FPA_
z8kzrQ+{FgIDUWbPx`Y}8E{#$q(!>3q!J4a3>Oo<X!d>pFv}l%1OAEl^xbyJBz9t0p
zaAGZRu3S@^ssTZ*P}tJKu&gCk<iRr_heH%k6K-il;0?%|_|VgAf|?Am4OZL;`%DPy
z#B_lmxE2ZZcoN0<#Zbj<b^t|e5q8JS28$5Tt*t=J<s+c&+|No1hNEeq2)G1!ym{=O
zhT0l7eK*?=081IYSbmMH0Mm5=-X65KgvPk!*(wR5Qx~2vHLo5DZv}|~1RnJI_P{GK
z-*ACx+nDq!B!qGUZob$MT1{>g8q+H=7Ix$atJ6kEL!9D{5D!=*9h1lNSLBBeSd(cB
z5Aa}^Xql*+SLaU7v@pOr$C!uId<mU_@wc}MC3(SrMI2zT_LW%jPXr{wf@2ECB=KsY
zT`oA{uHtfPoe<0+<bz?rQj2H#y=F(8wXlRq5#~<Qm?ntM!P<-j{0$<Jm50Sf*8$=P
zX%YyXCA7e>=|$&Q1P^XFiA@R>bv(eIw^5tybS9n>5kRawDCJ<Dm;wkR09Y8Lub|YT
z>b)pIrpGC%gAJyxFwChtv{f)fNWi+;XqD)%$V~uiIxV=@cv@7~<>|dFiD_CPnOz$t
zfrXBE8mtBfQ^m=Z@-RBlV0S>xE|>m0F2k3(W{uGD=y?!m8z_3<0h_N#ve3avJLx4*
zmt#XUOB#%7EE-=(nQ%pvDK)3~KWm7b<otMmF#sl`Fx42bBfb~u7z$gzW#GB^^&1~`
z(X5t0Bn=vi#1s_>q&$t3i+47FN;#PCB%dv=$iy3ZZW>YO4UjaEDa7EPvQ%lp$>N&b
z+9p@;@sM#E2L6ir&ekEyu7%$~p&Ub3X-uG6R1J^E&PH4N#Yj_7nltqgAvEkbXQIc=
zSn|*uY{TIw%CwL*F3{UZzsMixfLn5%k~HA({L}Cw1JN;H!_C1IC}M^bzcrC+c=*K)
zE#{`xC11hx#SPurTZi>!*2dXTC&qjMPEZN_<MQof;vq5G!~&pUQ>&FXH#IHNE?Gc;
zmp%U*pzX@AZM9&h+#ptN#<T((HIDGIc@_&pS;6@jOhIIRh7j#>3(oXh-h|V0MVaGW
zWBEF8Fz|NQ*ow4#h?FD{b0E@)p%6GVv8`-kP=-QtVnvFW8L#k5Iz~fgZJx=bG>>&^
zeWMwS{sIRr@&sCxse{<bG@qMoiI_PFG}O(TG`JP#5~!Y3ByD)(J8P$<SE78@LIrDe
z2*^AyM13p60zC17LE5LN1#gipegw+Zem}&%BLmEe3$2Z7nnrtl<sZPnEB;e`Fc2Hd
zASNfzn6PG&a3J|2W??&C))5BycsHspuHdDrJhc&Jcp=V|%OpB@HiA``dQp-{u7m>0
z6&jJa9)-tkV3B1R7aUA<y8@lC)JQPkF+t~a5oj2);~4-oEi*yFS_{J7ixI!atr)qn
ztP|M>HmX8qv5l=IHdQ>)09glVBixvF47C<wMh56YBv=C^<pvnD;DE=g-6TIfkc>YI
zkIj|c!84xa_rsOA&JgL_B#~d@)Ao`9zgEW6K4xXw^we+{#`(?3vciaYdG8PKF4w(=
z+=dnGRY^SiqD1y-J~Do;jJ7Q~YDRh_`Eh*o(^FS3%V^*F^z&u(yflgl8U8k(y47(h
zzhBUxJ~63;&yLI2kd@A&NgQy0FNbKJ)xyR-t}994P!G>Wq?!5_Kdu~^zwSyoJ*=Vz
zxbC^~x~Yj-Hg#$(Pxp1qUJ{R8q8;K)=t4P?-76}mb{8hEuGeI|H^f(db$Nbw9%}=6
zGNNRK(qdLlXNVj8-;e_<v|Q%NActmMAcIdI$7m<%Po7VYF_jc{7wlZb+xS9!>Um4Y
zGv6Z@{Gw$V4(I1LJ*r=;E%+QEiJw*ULt|HyE5vzzqqOU!w=Q6FX=vQP+)w03ixtm0
z-v|rJ<FneG?eyd-Mw1OWy-8%Iei+<#{e<;CtEmL&FCDR?Xv@;uBPUiH&73j{j(MI{
z!^sxk<hN8uP7b4cqCNS>JzlgGE^+lFA4b9Tmh|MjEeo@1xt=VQ+0f_HyTv7z@1|BQ
zST7?~`0;&7mkhCcISuwHXpVg=Wgn83Om=yH?&sTWhI7?y&MHjsGdi5C5^1nEiNPZ!
z!xq5R#7VHx31P;R#tFR+u3~!d_*4LnnVtP>Dd%g?a~kZdxxe})*xK5&mQxEVA6fsl
z?6d<H%c<+$+`mcZwO(@j`s}nN7iXugySR1x&bPH5xczoH`k9Ne(bB1{`<JcPo9{1Y
z&pG<k?6gIv?z+Exd;j}emSsnM;OOkRM<2cG!2NfvJ#gRxJ?hEF$RP`k-oIyG`PG*k
zxTv{d{$cvu1&6Ku(}Bv=nv2)%yec_N-_|^A?OQglJCSsDzJL9^{#DI+vzI-bC(qfj
z_Wp17=k5D4{?jhL*yL?}R`_{^T?6vm(#7XI_h*m2<qJQ%ul2j_FX{d9z`dJa_PY;$
z><!=f<+dM>J+|$!u|Mv4?6*JM`pe(m_uUUY{kD&7eEOxE-*?+{wq5z$7hm_@qdv9c
z3rBr%??dlDa{nLy=@sAo$nWlZ_-Ehw)5BkT`<ZLM{k@C#UcKcd`!<ff<e_ih{)YW8
z_}&{icj-kB|L$|I*!h9Go^$p0&c5W{Uo5!vYrnbrvS0l0o0t9J`)9u8!S8<VNe_SX
zbMx;1?T**o^TX|H@4EB1Z`%7WzrD=l{oopY`LlZCTR;7RU%&M9tB$?*!driQV)u|e
z=WOTqO}|q9&ixNR<Fog7KR))>?vKYFYW?inR~~rRx8HNc^27h>_jext#g0C0`Hsy`
zd+P2_9rYhSzv_^m?7sFhD<0nYp2K#(=sV~9e8Xc4*Z%5z7hU|hw_nu%Wb)zzf84VC
z;a8t|{3Fl#=92yIy>{8|JFi`)UtLx2ey=>a`@Uvn?}N?r_wP9K{72ro>{SnLMBcrh
zds6?M{?+%~zWu_xes}*{@4e}fx7wL_w=Y1ytG3SHv9jm)e{SE)uX{?PcFO$Me@W!L
zuRZ*M#;)&vy-~aP*`-~z2XB7QulN4L(XCgXb<D&6=kyPEzkTZux83uM?{=EUo%!q&
zUO#{2!q=a3;KR>c)c^636K_eLF*@?B=e%(Ly|<0+Z(g-v?}_O-`xhVoKOb51xzfYQ
zvr1>5yyazU-+cdDSMC{GboM<9+|J*gc*f5CpSvXNojqsWp4l_^-E_7)aNz8tr}}?;
z>C&%0{nF0c!m)cd9T=G2U~7WsIg|U2#ngj4&RSBRSMU9Pez>r+F?@X6Rnw!JKR7-5
zu>qg$UfkGv;jybOI_IxerCY_l{2RkFe{<n^&sni>`733|$%Aj)`^qD}xO;f(84r(M
zQQLRJ(9oWb9zV2p<(3oHjBOcs_`G>fet7Ed26paz*6a6lpC$XJhvmUn51+Sh&pk)}
z>L<T)wN^7f`=iat&d&P4y}QCdxMS&xdUMALJ1_63H!z{~>0|$@wBh5=*3ZkWOK<TX
zpuztrwQf*`r}mWE|NIBe&-tCc%D<u6{mefn`?tR~x!9j9M<t~bA3W~UerfAPvSju1
z^ycIDow()ZqdM3B_II6gU;Ot=KYiRy;q-5bescCl`oQAHp7qa*Z<Cky?(Us5{b+B|
z`1z|wH*t>3mUCqB*6$`Sz2*b?i}t)%YD?G1nOnXhFMnjuwa?pf%F7<3H`%jnVBhy|
zzw}v+i(j6V<lU1u$OdFfOm^Cxt-1U3LY<Z?d*{nD@>0Gk@8t{R*yL(?ags7uUoI_9
z%i2jd=nX^rI*XT&ZSGCoG`s#8-<-Yn8DH0*PVVe}FxxQu_WY39J4fHFtJCAU)6-Kc
zPuim^Wm8B_xu%srb?f2T%F;&m4c|d)pXVnhBfZkelOKJ?$+P`$?eu%Tar-~Wq+fKR
zFOAeM<h{HuOV8TH>(yb%*YS<gtlUi-dh@!H{KEuuP^Dg}luvo~m1@w;h5YDECoyMw
zJblQka(DCnr6r|7cpRUv;d|f`;bEo~CTG%o&5TYaE?+t`kxwn9^*^<$ODAOaB-`t<
z@ltKUYM;#}vy#2EzlX)WZ0U4~A7jd7X~O9x^JULcUm87n9`8~vbxTKc#Ifd=xfZrp
z2PdU(RTxhA3D1#g=~CL|Sua5V!pCzbT`zf==AQn%5q~Wl=U7e|FgB1=yv?8q>$6qs
z5}MG{WwOY8KBq)cN=q}k(@|Hli3-BU=$3ZRQkcviufd<#@P@wBdD$LH>3E#nSW1U>
z=N9B;4$)|q+8mf>zGUxld}#EoYlwu5rRnXGroz7MJotvBrB9sY$2suA+h``R0JV6g
z?%SbB$}V3*XOmB`Tt(cISm}^WGS>E){UVx^iT=2sVD&@>SQm#wI5IntT&FhR<J=Np
za@>b0d?!MdS3^EIP-4JJ*H+HRS1$khD)O-=9g&w+h!@x9ELw#B^7l(mWpuMcsewK<
zqHulK>)+V61TRk)Wlf4`lJC%$ap>7g!)fkVde$?urTQ93=gZiy5su$IJXa3!llh@K
zI(Q_jMQ(a%+h5Bf&BFVo@o&Gr>rc>LX=nM}_G^B>^u}L2_Te8qaMd;c@|lnCJ^l-S
ze9bps_t<A1d*B1tyy&JU?|$ZOk6iGbUtW6J4?c3(H~#fEzu0}k7yj_T_g;6}8-H-Z
z>#lqBrcdqu>?41?;5)B7?WXUY@U#y+bko;XzUdEt`p_R9JNh^O@{#}Xz2DySix+(H
zkw<^_fnUD-rmuc>;NFLBdeguB?!ikxa@zxkUGvM^Uh>F8zj@`?{`BBwCp_}NG2i^<
zXAk?qhyL*`uldbgmwuF-eDifT9(C8J?t9}~Z@lYL{Rc@}oM?$9s-2z38%3fs*p4(9
z+U#S07b{zw7t2o;vUGSJ_$DQ<5`w)qZ27t8%bD_wr1E-7afw+6v)|?Mj4=osk9nz{
z=#3{wY^{~g$^-Klv$9fM64ocp^OTQJF|!wHD&-$nG`m*%Bbi&y1U06Q<;svgw<8;e
zkV($Voo^nI6k~5gM2PYp^!&eg25cP3F@^tIWP%J(%iPTz1z64b?_v2R2g7I!0X~7S
zH=j)@4UC;h=Pki}Y>Nb@b=rKF(n~8$ky-87&2LNRrL3EXpJ6>$_)=|>`iYF9qki?o
zK(IH-EWbu&uttm}EVMD2%?aoIrn>C(89Bq|CT>U+j32Go;&3ugPswF-O_qeMoU1nC
z29Sq?^&sF^mL~=$de%T_pr%sGC$6^al0(b*PM=bi6?4<5%`in=OMAvSTi`~zy%sOD
z4ci5C9yt3k&~vl?iZol*CH4o?E`k6<Zu=^6O<B1nblq_jEeE(c$14Q`Xiu9oe{r^M
z>YM}0tCg>Z^QTcy$t)|E@;I*}9DRjkrnkR721QimDEh^Q=t^2t&+bZVBkdfoHvg8K
z+2p25kbGb%Qg=(T#8+*HqVgM7>~`=tn#4D~LCh<(J>G-Byc16*RwmNpl2dH0k0Y_z
z+c2?tggLk~EH_@7Ucn=55C>1h<{g)Tw<o(n5CuuCZPmcoJ-d;^rr4KFlbeEeT)ER@
zv5E4ONZL2!7>C1xtY0GEl|1j<0AbG|M;h!fE7p%ko03|23<erM+YYX<Iit*tHq*&$
ze!Z-#MG{`7j|=d{MA$9Il=g8Ih)z1*NLlc(tz9d_*sS^TbXI(bzo+Xt^h3Ial%`1t
z|8=sf+-H6OSrY7zp0X==8@Zc$VI+z4=^j>12Qf2g5zFyS=A;)>2#_-Gz*%0-2U3<T
zOhm#f3q$+qt5(YisTc7Q_A#fIx|DC;x}<8BK0J}nXgU@qh=qC7f}29`jm+sTMa<mz
zmB<G#zmy5Qy^76X<>?wsrpbzcx)J)AKye}yOrbA<go_7*5H2r;P+@hGg_`Y$w0PgA
z*R`IIIqiHa9B@g{#C8Pn#?MZre5`I6h6SALec#z$k)1|oOnI%6nFLz%XH*WEp_(e4
z8ZW!@Z9WQUs3+hItXK3Jaw;0m_q2sT^<>hzfIT<~g&Uw!H<qvCnZR?uXr7XAo$DLY
zLzWbw$P(}_sWw_(10Csd_;vzq%4EZA_T4bH?@Dalot+fefl8}m@+aO(#-No1_>d!H
zQEt<+5C42gdxl%qNeM@qAXB2f*_?&3#o(zT-tKjmj2S0#+{HUH--?a|jtZ%Fl9UJF
zn)DnK5ZM^%xGGAqbW2>cCVW4nbT-xCp|b$+U6W>-tl0o5Ads4lA3D#(29qkZzOO>B
zka}@41&z@~AQ~JK&ja$r9<qUk=5#x^4USeU200OZpiP2${z0USQ-W&2*>OgP)47hx
z5!(nuc>=rAc09tC=$6>pU~-DLZCbBOR;nPI{SIk4K&}`kDGtkkvCKX5{w4`>n&0D$
zk!=WLo+`4TihyE?VI^Yn#>q)|s?LealYW6PZ^!=gG@vW+dA0z3I0YA|4u;Os&=C&W
zHbw@HQ74^|43^aP7|C?obPSZb?B$ZDcu36K?8^w-nKIY#Nh<kT@*(Af0P@zG35hhV
zwzM_d%GMZM1nm#UGkw&MiGh0f*w}euyTm8u9>?#&=XcbP^*KqX^x?5Y@>RNz4i2}-
zHX7_a`2+`fR<nG!X{YJMUoB5^uE_AXBF_REemVi@^Ub@^Qbh)P-M(}KB^iQR_IxMi
za+<i(pi_mF&5Ko%0G@sO*q6>uyP2Fe%cE(X2e);!<hh5wZH<YNV{e*MN+6s>zEWFO
zm1@=ZX=CykS<M8XC36Nlj!vL6JO$F+_B6fgX)$#IH=$U^M&1DSICNvO*`h3^l3<gp
z!e&DQtTqJlC(je_vsz*%Ry)Uye`v~iN8165)K94{KU{Q45b<l=R(YCC_>f;d+hnP3
zc9J)YzPOv^gJs$;rQA+zh8$J&M=bS0m}liyG9w$(+bwC`S{=vSJa3*QNzm<ZeW$ea
zP|{W<mz`{Q+Oi$o@P>vhw@Y%O8}RBn0~c1WXb`09;M3$l<+BKDS2d~SFU(eeKd~nH
zXRz`bTeSbS+IQ0wGy4OyY3txju%Qlg(4nLyt&X*4jzzXawQ_W|4rX#MY&GtAdd3Ol
zH1{VW#StJ=Cr){y9KT(dOEfpUG(K(YZc2^dgAFslC|=lm9y44aP}HTuZ!~B%g^%ZJ
z?R<6+Z5W5wTlxSkFW%xbr78SDl;$F}AmbUC4(N=Un^LtJ04_B-mHr5=7JOoz%@WLA
zrA=E92m_M2TM<2?Pzv!euyLA4FI6^H7WgV|qqk3Y>8~uZeUmFb;AA}#p{|J=sZmij
z`pxIYScK)nguqg!4(jHL^J5s2d0LXe=;?WTlp~>SiV1vkN7Fy+orFTpq6>5+s|@Qh
zZonSSPosF?oNAcMPdg;Y>CMIsCTJPTFiDlY>@y&&N3#Z^FNr4+Q(2TO5acO-WC&Kv
z1l?;Gkf*{6put4<GE4j<J4<*OAiZhqHw1AF(=>kN7NjNAQ;124)^vlVK$(R;rs_Dz
zm$9OsfIe7&CD`PWo{2>?oOX3OSZLry#5+fu3C5Y;o_U*P07#|5-TEabTZxLXajTG>
zm?3P9Mg|#pi-98e7|BCsZ3&bHDT&fDi3>#`m@|e&FXhOWv1H4&CQ=z3Q-X<2bYq|i
zBY==-VU75~CNoecICvbqD;g5rjg>=^_=8~t12*{^RiG#{mO?+;Qy|YRf~VrD-l!c0
zt!N6n);o+prQpbU1aESR(v3WxFZRd_Kgd&rM|tJqHHDA6H<y|T`}n!jRPp<z!O#&%
zObeGc9RVaDojyJTs(w(BuF8j#j<JiX6@?Pj8!0--EZaW8O&eZdVe4@|4*vh*>|NmG
zs;Y$Fbx!Z9oNg+~=}sl-#5U}%R6-#U3J4G(!0x631qNtha59Kc2@OUDwP65*AlX$^
zk^%!1AwX0HDi|Po(Jx{?#K*-VL?${oM9j>f3}fH}UjvFvM0wx;I@M9<yZ3kR?{{~1
z?Xw?iueJ8tYrpr|M_pd6{U%DhU;v{BQ&)o85v@PZPqh`n@5TuU4H3?ihb5mBdP)7U
zG5Y9aTU~XM4AI6r^|1Pg&hi*epgLG%$t!Orc2w^~Y#DBJ9mf$8n52LNg(&>1W^1n0
zL}4k3)w;`jyDCe|ZiO1(rNI2+3J(moQ)$j(@pyu?W(5V#J2O$&mf%=(;rJ<on5YP>
zlAwD`I5n|BtC6fy_X!%Ar_h5?v4jz>`9g1yg7b1IBYFJP*yJ(VsY%*SLrshw&!bP`
zY3M*jm?y4d)NhriDCC`g#MI#}LFN-237oRdP)p;Jf*_tb6jAV#OCU(6{!ZD9znv%E
zEB!LzdFIcK=YKPL-r>zAK_U7sEndxWx-Q^BYq0hks}7yLcKC5B0^JZwsAG4G^*r<H
zjvAhLt9e!a9IBc~%_X)%G{|sK9op_BD`e_%$U^g_a(CWnP=W(Hu#)xaw`vi;wBvNj
z6DJ&oP*S2oS0&tz_Z}pUK~pVC&4SI5P;$x*>@*U&1sXJN)<QIK4sn*$;j|ua4`t0W
zgeE9(Ifbg?*0kCt&<5j6&f&cLBo6Hfy=DVIjQ|AWs91C@#$zu{+)1#t(5WTP|7Ka5
z<naJqIt+39aZFyZ<5mdc##^1h5;mTjB%!8I6v$%Sr4Jf>FRtd)DM=g5GpJ(ald{=Q
zGkIS~VS*90F%}TVGbu}+34T^;U;&?ADC&7C3mel;U5R0yuB?)(tqZFPh_#AwlM`C@
z#3b)b;E!AfrwSDvJYDzVlEl<KC8T;Z-Xf{qdOV64Q&)=+#f<@#={RXfHK5}Ov_}Vp
z`Z{IelhkT;{Afkwz|#pfgp2VV6gni4O5#rhrCv2jr?3cz7p?Ou4cY_HS;8<05_Rma
zd`jK%vl=%ZOB(!Mi!>&Pe-Ff8jDlIhH^F{EJ;En|oIb@T4^l$h`h>CuYb_Q(^5=}{
z{7lu9P~u2~H$l|V+yC56xFwXuB`!p$;)I2K5|&st(SAzZ5yNh++C+fDk2l#{IzdR-
zcnw9xX+<%KFxBOu8{qd=X#=5r5aO|=yOhu&P$mUQ3q*TGS|Xc7Q**GHPdEVRs7*2s
zOy(D4WeIWn4bXL9I<yn)&h3v=IfKh4^6|(aiK!`3<dJa4bFGs4v#~@VH)hoYX>!+j
zXui_KV7v@>>9cd@>AF0QYLah|F|=o>keFm^q2tVGTOc-Rm^&fZN$HGN`_Pd#kz6Jr
zp-!)m`+4)qu^I=SG^j9I`s4AIQ~{w03Q}5&oNWT-I=~9A6+*|%Rk4n~5*W>3LPQZ*
zoDNAs$>Rix+KyjTQ<s*p8b@=l!G<({Hmb--%8v)wFyXgjYXsaP^`?$v5-*nJodc~s
zp-v5C{c{9$=qQ9{ui9~R<P2<*)C1d*MPWR<K?jV=@2SfPA67q0gh_Ot6A^ZQ8nR|&
z)CH~D?oKLfSJ8Myo)FNiS;d{yPkkMcjUXa*yGircX=GH7$6F`8%&Mc@^fXEyAbLA;
zriP;Lpw%^@gefmcjHweFuf)RPG-|{vBTAoS2~0SojE}HfVrfIeaeW9BAW6nHkWp+w
zV1d&lO3U#}99~>W>IrTQiuLT+zULFCT8Yt4N*yr@;}u6JJjM-y9RiL3tASbvA*ubi
z=QnPwS4Wo*h)e5hN*KkO$l#Sw*C{&25$8ZEZSV~{YF`4_!9;MfK&?L0Y2LL>P;fQz
zM$&p|I)`UaL&!L@X~l^Nbs(pmoU{16fW>vvYMuhZK<dD&F2}EGz-e*(wTYmhqfy02
z^FxWdzm8U{n81c-k0dU&I$?ctSj$Yps(MaGjxw!?{hVgnF{>)bdQ)jg&d1Hrw!v@v
z=cK;CiAnOe>qo32m122sjcyYTgI$Q)WsA2=p%l5h>VdX3lG~U{vOGn4-peBXUfZxG
za<|~hxLMAze9H%p*tM?PTUcmv85tdGSTluf)x3EB3OPSzaZ^}xsH~A2@{Dnq%-7ry
zZ6iW!A~)79{SapqP27ktt!s`lrcLhiO)tws_|+BcNu+;{@@Pm#GtVnLx@;BpjwH=n
zIMwos89T;~k!p_ay^Hj6q>~N9rngklmvME@U}{60NwaAaYU9BA8?V;N6yTMLXS}c>
zJlTkiWZJ2eCH)n$WWz`Nz;f9XK2T&x;j_tL#x%&6YfL+MC%rtPs%&T!_Lfb^Y~Nbd
z<PEecJ1kfX8teH`gs(aF?XR!bLC;%{T@LmmcFcwLAa2<yo1(#z%&9*<G8KhwWSi16
zI2cJiU1p6tZn<Ico2yaYNSW!j^p9?W-<!dNaI)JNFQI3H-BG=sYT$}Pn=11~5%Cte
zHfOUe<sA3SM)61{lQnzE`x@4#H4o&Dexo@xE4<CbtbR$EzDAmZRyI_~su^`*yJ$A?
z;nVIxBO8~NGKK=05oYRcDNT+IX`l|zc<FIca`l?@45TGwYoXLekt8I~QW4)%ouFrO
zHho@L3rY7ix(e%j*P3<xnU!M;GAplX<@T;?9niitI$^=3h3tZT8}F?=*7~x4ESj|N
znrPO-?R&mb`N7kzy^lsyvkNnmvY*}8s$B5Omgko9CEZyA2hP9i+)ZPnoJ*<1>HI7+
zF?(M5&V5VH&AzhAPcW1DJ0t2J8#(uhv60NW)TGARIX(R|$5v*tl~qsF)=b*9Hr3TX
zYyMRO1M@$#^CpvS?{JffXFT_|^4q5?WuI$zJv{yL*ESvY>sK}%@bWF+zIf<656^n|
zvaRp^(|@(z`|LLx$6Wr0^^=z#`@mr*JpAzN!+yW*gtvab{_e}4+0*+ktDeaI;p#g-
zclkTlOuS;jTZd(j8$0a9<J#*=uP<JA#iY{hTTa_^`~UpZTXPm&wezM&dUmawe}3tX
zjn^!`<ML~F4jl85?2}hymOgoT{KTYxDF6G<t~~Vde|>TB<9l9QymRJJA3Ar<<E!`G
ze))&@-F5jn|NgW2E4RIG(G2Bx+voU>+>H-i9UWQR*qA)%8;5P)yI|7yCvF{hdt34N
zKlB#gzxS;E>BZaD-+0A43%dhXm^^=E>%g~KrLP7*ePVuT)t+K$)%wY2zp*`2TD9-}
z?b)ji%g&A_PJL$ay8I<eZ~vFmO4I5+^E0KD<;;)EZu-z?cTNZf&RuuK8SB3=Iy7+R
z>}>YT*#nDjy07QoPb-$|8=pU;e*6DAqyB~ICoRovU$tlbmFMhPfAo2Kel~n4FF?Je
zXNMNA;}G8ZovZqD%SRuc_wr8)ho1f~t=8g&+vaRu`tamWys+)C3-i$gSJ{-=`m3$e
z-def!n5J#@wzB`e^@a2vlX@yUZSeW^Gmro6xwmXT?yYZ}{h?P5>YdWOak&|}Y5PS_
zKXBA#i@$vMgmZ)Z-#&3$wtwgJD@v}bSaR2GJh>cSzNGwx+s<7YeLddOJgR4pTzKud
zJMM60|6rvopAJW9ZJyr!_vNRXmz}da{@B>o{x5&1wQ>0_k<upR+jb8wjc2E_a&%n^
zGrOw~&v>D}U~o%N2)0bMhYV)x{iP2NEZq9#=+NUYdAQK@3#ubsPj~wR_GDOWo8&g!
z`PJ+ZnH#_U{&PP!_<?JB;|cAqIT_b=Tg4rE8}BB^;nG>{)0Uc2TuP;)()9TeJ7K3u
zSUfF~Bg+hG-R|b4(e8Nk+C6g7GHT)bsKZa|xuLi3ViB?J&RKR$wb`F~G>*Ct{*ynT
zd(}=`*uFDYxOe-!=;rO_;F(e0zE|eumu*VhWzmGq19kK7f2^A)TJ=`EKI5}PJEt$b
z_lZ;`F839dl>3&hhz6FvBJ0n7s=n5a)NjvU==!q7Xv3C`X1#fx#(Md1-xbS-XReLh
zjb>}<*{N5XYIT05`e@PpvsqQ%nOdd19eD^`Hs?>0>ikcZQ@X||^P(yKPlPV3hnJ-0
z+i1dkUJs9sWL#?b?p&%GZDQ@qg!AfpyFf;khU@Lfy2wrp>cLr7`o?IZY$+3UxA=nV
ziaMtkXn*SKgQ1d(r;bU6{ftbhAvXj*42NX#^;5&e*Ruh?Va<pHO&1MM7?hLJ+d^N9
zPv1yW)ipPgDRVQKu6Bv_hu!g9II}NoUAhAX?ZkS&&7|UdX5yxBUjJ^%@7yh;g@#?(
zYNY1nC7csBY8Oh=EE<sXM9;Mg8+oN=dDQ%PpZH}tXW4!5DcdlEvdau+C7UXWslHH-
zgJL-fN|B#K7rN($OnuSb$XuAsgz0PaHRkeg;0FAnvBl2JE%oItDrdu`<@AIRJ=2t4
z3V+#Q-t|sj5vMbY7+1?CD_*Rz{gUD?&W0HojOsCbGw^ivIA!$JJd{a|6B*+1DW8nv
z8}uVKD0;?Y3_9p{lGQ%?1~wtR9kw!+KE^OMc{GqXRnpBH2J~?8sPI{E527uGeGv{9
zMT;2_l72`(ju?&T5^mb)nWhW>h>R^^O#EV}^n-eoVNXnvgjMt!*EGgOVYMxx?3F??
z%JkA_h2D7)VV=HrQDjJp@e;M=y_x4Eq#Kuw2hasJVcTV+{GhTLW{q)*Qw3v|4pF9b
z_keOp14ek3f`B1`B?y)xxq)tbQQ&k>S<f`RMPDV|u17{R?El?_=G1A7znt^!8jwx;
zp;EuN9Sce=ynE}>;0kz%Y%^cxutRxKgO75t&wlErVx=p}mn*L3Ri4f?Jn?b(X|2)W
z921^gE|Bjt{xtXQKfUzkkMzt_^8M0XbMJopns1-}&exuK>97aSJfU~jL3h9V(%q-8
zzVh`?eD4b%edxqreeI|3j^1(RweLJL=bLZ5^v63+edzVKUi#+g*S_|ngZ}MjZ++vN
z&pz_gcV4>V6DPj$^MlU+`R{Ih^U0%su=<j_-#+n;XAk<`GZ)?Z%V!_@r`50B{fQIa
z_|Y-v|MZ1hufFEBf4cUMU%cqVr=C3F{MYy0aqU~*`{1<~@%_?&JM*Cfemd`q*XS9c
z|1-y#r_&#L&$DyyUTwKp#s~Zg3@xS2r5hR6zVjh6XF7Tb6Wm4Y2s;$X9;xz<!=o5~
z-FAeRIrlkpBeij`++Pn?wAWWRjx^@fQBo7FMR(T)r$nt_k;`&-5U<-2cD)yS6Y4g}
zndOXy_@tEy&Tt#%W~6U6rGI$I``(jFQErkO$e{v9phaPi^1EjN(#-UQ_3pkdTo~1j
z|J}I%9zbsXVv-?Z$LszQnz%at;C~DK|MD_k`)d%}@jz40<{b2&e~B~U!6wYQ1zv-c
zC+fV<4xdJPL(O&8%xjvVxZ-Zee%>h3Ow|8^t`szEk>TqQ@;b{%e+>mM60hqG3=}im
zfGbXXHmhjG*OpOsD>)_>c*%zGnL1vSEb+V8!==G6Um+oF!bpm`JCAv^m$kA7n8;@A
z0_5zuV-~NOCi7DDSc=Yx;%~P&<Iv`-#*rU_Vb3n*eIL@AX{k9ojck_rfjQ0jUiK(?
zS0FrvF|@U8lZCo(C1x)jM4a<A>zHHU_hcdF8hBe05}2@z?U$l$A=&8_1I?z>%btd~
z5{71{nMI!lflbalt+^hTr~boRnl%CmU8WSVf2mUhz7*$48R{$&Mav6EmQ0~$LYspK
zJ&qJwrnd<om6tthIZI_nFSHay7@fr-d|a3F!n%f_=U#KlW<eZ#o#&Nl|9lM7?AzOv
zMGhf!@#;L6q;W704~@`nOG?5>Ei`cA8??=|BLUF9Buxdjxc6|v)+w<OR|`f=Gy*)P
zzH3e~N-Hlej+csO8V0Z?3YD6d5%Lxv0rwC=ZfXc*0cIjlI#q{u%}TDLk0)~m51DF?
z$fAXEG$zUH4wTku7Aj(`Mc*bU5u`s#-T^d2&X=gn<q~L5>P)Aj00<H_pvh)w(L)8P
zkZ;+Lr6<wDHnKAgi7(2^*dXR)1<4=-ou~74ICgInahvMmgb#5($ykWqd)sd(p^q|>
zm8y4)DzZ@!Kk9YQwFadb($Z|0A5%Ou<D$h&Pef4Q<!}$}qg}NZ9u;Z=O7vr*ZAF{~
zs7u;b99j>@tYNE|fFs_5Ok9`|8>@Q6(~OZ4kqD0Wc|1v_Pp@E$t+b(M+Im*xm$N~W
ztWhS!Ox>S4B7-^7EBx}EY&&@|^fn?E8K`7wR+-F)!*u1DiqdXrA&LFM2ux7$!<rd}
z1d%Ps9Ne266-rL>x#SuHgaL4ivadL8texw^zmcpv7F_PZ9h2)?s5msd>KVtBIZfEq
z?vz~EiOC#X*RrJ21+1f$7}26cJ{I>HVSN}z19;MvR!0ot2uI=?{AnRUvC)SZlmlJ+
z_ly%VmS<l|w6=}}Cz~X%4M~;_z$Ycs$vaGdh5aP3;PlKr&;1dSO(pVU{X;{6(DfPL
zxffCWMYsW)^V{S-Om3;MOkuUUlASgsriG&Oc<E(pq8`=w5T#9Uk+Z58PZ^k0pg4gY
z%#TP2T9-g1PR1uhh=l89k*CQ>vv#5;4zr^vbx`>oEHnWFvzi`{tosV4MuV#|(tPO=
za4A(}7{6(%Vl~WKq)KI?n75LukLHp38hG4PT|f-y9mHGklb7CMCg3V7p2$E#1TDsQ
z*69PnFLvf0@i`ZOJD23g+M*+Z7wIhgO6>GqFJJOuT;vOp$z554+J915P-Lx0O)$Ep
zo^hmy&&m^xa<^qgg}1({jv-;oXhpBk?#GKmFS8nA+m=KQ=&VybW~b9i4wqLz7(P>R
zy}qSD5oJ)nwG>Q{&zfO7m}}_a`VqGTac6SzgmTnhrd5y)EwThY(}L&7coe{TP`7Sr
zmi<>^lLx!mN_%FZdH8y*lIs{}YMT&_mXYXf2+8tF!!k6~#U4!47?l;|`TlgOLc`N*
zatMQL_!?wNg)zv{V1y;o&7tq2nMxYrA)T*yVR6MfeQV4m+Y4r+w5MB&HCQQT%3R8H
ztX;7qoNTuenlvl0tg>=&Yl5ipm(^hABjjWbhbCnKa!xs`ja}~?jZTZq#ZL!o<Wxw}
z&bTg8Y-|U?5K<_*a99uWAK3<2st=g5ao0zUi5VI8TBNA3YhlC31ieSJ;N?8cjI_+s
z&+~p^PgBxosfJQQE5vZ_#QD!SB_sjKBy{pC<HJ)pNMg$%th*AeXf)+wnrigY3>kBQ
z$m#XSHD$<qJ=`{9cDfpDL?iQZgr8OlhL%es$N3$~%E|kj47Gi+8Y0il((0+Z>=191
zp0&uk+DVkkv~(zEg<Yq%pf?36Sl%Q_JLC4kv*T^atc9oD$?FR4Y?im+(<W!0em)Iu
zDFjStVc)2weP2LP2yF<$!l<>GC;(lO)=L@;YMiI6_zAa8VF$d$mo$l{p<={vrK@p{
zRj))eq{d(y4-fR6ZABi4?A6q0Lt0|*3%ETIkx*(vuCYm@1Db9_k|ziwO=5V5(c*x$
zQ2n7-XeYZ!WvdRYlfj^>F&GD0@K}Z-v}2&aLPUXM(E>{i^@esBtAjt0Ptub+Fo_|F
zp3PbCio!Ms8s<q(_4X7lJXDYKfwf8c3UAehLxj-^C3X>8d6_H9q!)Nm6IqwYQOYDE
zy&@#qH!Mepfbq(YhN1nTQ@vB}6CepZ{5s@VBQ1yTsDKIWWUL7Z<fWs6IyQzh>L)zN
zBaV<vfi0L#h;dr_N~x1|Eie~}pJqLw0e{>IOmY+IRS`v5OsmZ*YLdMkxG1%g!-`2^
zrAexYIHIVJ#AKb_PhA|iyIqm^G)k2W{TMf`5c!W!C~N>DfwrJkW%w_~hGM)}4bW^;
z7=L9L_bS1VTxn=ptqk1>A|n@?rzl7J>C{mqPRnYP9$n#_S`vl;i;hPaR;rAsNT?%0
z&c|HBE@u3vlr(<az%AFw#Zt?4a+@^s!0>u&2ZHga(ZQJ-4f9JhG0Kh~{65J?MQXHk
z(4b5-T-Iy3Vc_1PYQsu>oM=vyLDXuHp2PX(pVWmh+I^`Z-gt+@+Pv?8i!WLNBB}^y
zB_U&QNC8>4bgX3p(kc<l4+8-Cw2<tmhSxyGvIt6{lmSc=5!Wn^vZd*QzO>CSURnWc
zp5O=_%N&t&33mJmg?jSXfsfKmY*On}6O5zR;_L{4vbG{#oHR06xYYnk66;M|Er(9y
zC9p{(w-#;`*Ak2m!V!SrOrYaBTyUHg8uXt4II4gs^OO=@@_XnpKnrE<D7$#5lUWt%
zJLktpH3Sm}SQ@svf@u$j?G!FSDLuG-Wbj%)9@LRY8XkO7W0idf0~j*^0n{<v?Z~1-
zkby~(KamP}2%{V@9#Oa&4x>W@tGp-r$^$>h1Jf!~tQgDBVS~JtL=w&RgE1Wj;*{i+
z1+6-@jzhaqHKc$d85>W=hs1HKF!Zw94rZP2GE}5?gqk=pz8H#Z8~2PqB7zcB<C2t=
zGMC)*R2@_pt5&N&@UW%sd;%Rwdz=}7hme*BON(e~s8;KQ$xyswFiXD7cy&`gDZRK2
z+CZ|^4E~Y~kGBW}CWfg%6GWQLB#ViIDobT!GHW%gU+QC^^(4`bk9phvT&OO1F}4DJ
zNeorK<D$PQtJYdYU+hHUQ4#o#wn3E}(GvbaNbjgM)+c`6Qq(ppDQ-zgSb>P*pz~0S
z614GjjP)+w@8+rJaIU^WnRNVD72Xj{dgooI|ESZ5Tbvp$qWNVk64I)7NcRjeowurf
ziQgw61s;h(VSq1tGT{i&WeA-e(wZe)BsJb?yHZbzj%iG2fl%W}8j7A1Gzn%Gs%SJk
z@uEF7O^ES|%W5W+Ju~7ot+(DI6hjdJA9`YdGbp*HFyctiL4+UpfCm!+FI{+WtI_zn
z!?OJJ$-w}ua9EvAs^r=`&H7Mm#HcLa{vab?tAm}&cnaes;S3uhM({E$?HCU~Q0&yj
z)_5R-AR_?^D&8u%PeHULg8<|Ei=juTXih+H89!%q`sTzaM{tsuyaQLvQawBZh@6a9
zBq6TWcqePoaI}{{J!eQ{Vl1`+GcU&~y2yYw5kGC8#(_+wo&cFZ9iFZ2UFr~V2_*fZ
z$76}<%&ftKsq)M5_LsUb5aC~jprTLp@l{^BS$plJLek`Cl?UI^1424&KoW%_s$VVN
zIkXXLn<{O7fhF@ii9({9eP@MF9V^yE4a6#Y3{8k6u-nOwBtdB$qsH1QaTTq}^y<#8
zH6$Pp$swo!cTa#{O+rGFqSf@Cv`I;JVv}52gqTp@AI8&qq@l+0gIlL~3_quNPFO3B
zLuhbFj2e$8g~&~h0*(`xmQxg7;7N<edq<W@(gY+CZ&Hh`5~5szP_lZ4<oPqyouDFF
zts_CJK_;LF1~i~Ab`EB_RSJxX{UnWtRv~#N=o-p9(c>3;QUQ|!az*7ZHq{OZE<!O5
zAo2qnWq44NutU3o)2fA;Ur8Pc=#p@}Zk(P{!DKZZ@#zK+8a$hXCRU(PY(glcO_(xD
z!*v>rjzqlI#(X4p>#apX2`+|nS>CTvthBPqVq*Fen=%1avx-LOK0T-2%T5j_DmjaD
z%OA*(3zSIQPkO{BIxWJK`12Z}cJkDRL|$#^0^}1n-S-Uyk(yTB!h+(!Z%M0{@L(Jo
zou_#xjTz$Hv36^=$tsc8mI9Aw=?Y_gNgo)W*orS1J16aix5$8q$a<1sR6KmsJ?w=*
zw*{EntCcl1$^-nU9VXbEgm#=uL#RDj9HU=?2E50gCoYfZ9UK9urKbi^3QCRQO+pd$
z2-#93PE;@So+v*qe$BRrc86L5uljoIKLTyL>FanXV+R9>8{@d8MAzk%jN-&Z1$Eg#
zyi;(eQzgidj~qqGywN$5shq7wuvj$=e0&SyQLpzFpV6=G@xOUIR7H{uzoh079IY|N
zi3if5d73?tsOfx^P<bDhWfB@#eY{U)pv6duCW=b>M8pYY5XKG{h|Ch+bEcEc?Z;tE
zUe!<k#ds`$@h~Xe?@7q3<rtnM4O4|>cf(e<(unjN&NH`ZAvj<#x`xnRJ7&|%ug7;u
zQoe4(BKo#9GLqj_TNkzLP0=oLXQ+<taKehVoHSCGI`8`wD`bM(G!EEMW=cD_%twpc
zwGxYHhs2et#1C}kO1aU(8OwSq?8!DbOJAtS7H)W`HQ}Cu;AZKZc<Ep3PIgjb7{E0o
znWI{$MxI>PSPhH)L8-huxg{*q%pd7%lk;2vpH29~*sNiBMtXj+&G8M~n4MxNSsA{>
z5F6jvKij(&0AXzl3=H+gVTmu~)u+k&MYh~0>46Jch-Chp(5{ej%}njLRs~zxDfy7L
zBXj3wM@@-&&16Z;zWWjr{(>f_Io~Z_#^@|eM?)8n3_n7_t^JTPBb(YoBhoDusc&uL
z-KMgR!=DVw>Dm_=?kV^(6nd0%&kN&Q@<$Y$@0lXDq<ZU(KgCug9A)`Rylki%KZ=ax
zfN<sY-b=Ijz*q9+Aql2d`n7(>-W{<fniJg|JBT&nH9Oqeks{x=VE-eW)Q)+L`v#w9
zQl8ei$TqJ{Zr76hZl7KtXH=V&xdmpKyYmud>%&G?qReY$f*lR(WI1Gl8WtkUC>cEp
zrDm#eUtV7^o)7#z%UaOC#iXNB?A|BUVfqH%Tt9f!*5XqCq>&=as;pwIy;Nq$>3V;Y
zcim66l=r|~8Ch-?b2iYY1Akq{u~0Y4g8veyZ}a%>kxb~sX$=liaXCOLX7`-p`#-tL
zty!0xc^YA^H8Aglm6`AFSl1qUY~6x+Z?5W3FI>3gxgFPSd-SpEHqASJWt5(^u(|oM
z>sp&1eXM`&@e5`8tXZ!-ch95S_TKmX#)N4nxCtMf_QpLgE`Rmj=a<Wb>3`!Vubupv
z`(IuDnZ2)6*p8UKYu$v&pLzcGW5?Q8MjC4~6WVLno^r(YKaCx+cWg}7O_<<n*QJZw
zUl}XTUo{ri)~5IFc&uyHw1s1v<{z`Fy<=VaoVPFhS>@&X-_SEezu_Al3*Wx%hx1-O
zVR8GjZ@;^H_1oufeSOQjo4)_RyYY99|GVt>{^7|@g~PtHKL4o`8{b>~ZsY&_)SLU>
z|KP3Lj#_x!!^b_e>dplZefEa0zx?T^?m7O`JO0NX{{Hc=?z?c`k*|%ua^jWez54Fu
zm+kxA*jVn`@2sAC<<D1t_x6XUeAhhuH?Mx>gezV<<j@PQd~*6Rmwo?_SFD&d{mLuv
zo_^)gpZRvKc-gm$Uq1J)OTYHfNB*Yr;eWgGqJO>P%F7SC|KhQ4UU-i3d(3B$@2AYp
z{x@@tm;UbcX)k@^^>-To__Y%o&ulv;+I-dzvztG=V*UKda~j7_zIXkcdCxQsTKMj^
zdl$ZE-><h#xpVOL<NNLQ;xGQk`#*Ny@xMOl!`pYx8Q%87)IS|G_t2LPnw#JE;)s3Y
z_ha)PN#A<Vw?Dc0n5~CKf3x+3!iQcvGJWK$4`z?L?B6~%cIDj@=8t|eoK`uyZ^Rz{
z@K}Dvw^!VB)*~O<6yJ5^$tOM(SFXO}%It}UaNhE;6ZGuR@BbBkkGtf|#rKRp>ArNx
zBj)S>`QdFR%=!HGL!W(p;5R{G;H#3^c<F_!{Fgs*&HBxs{OYE?%Qo9>U%h7j)|>zK
zyRG@(+4{dO|6Xa@l^?!5T72|Q^NnKrmcjhf-#NH{{r?f1cS7&Jv9ak#EZH#Y!HH|j
zx1WCB=;g)V%qhm(uDmtaSNOLhFZZj?w(FNI|KxqsRxSAT+7t5MKh74<KF%s%Ykwnh
z(>Gq7+rIz7;Y*57^c4=ue7i8X=wdXxCtECK297HYFT8io<0}uhXEcsn7Br6d<Q!|4
z?wen<+ctfx_z!o!zWtWQ$Ia-ShsXK$=jWJubnns^4qn?`oWCV19AJyrPTV_x?9|0`
zD^tgEUs+{~?|dLvd}4E|XVcdY?jIXCmy0%5nrS9n6ppM&<z`Nixi@{tZJF3U@|CP#
zzV!>O;omm)&aE6$nl$%lQ_i{nSOj0w^<2@K<Cr}zN-wA^{#eh0=Ea+H%|qAx%BNqL
z`9yll%(i*7Z+H6T;zh^*I(%T`$HUg*OZKh_ALuh*J9Rj>XZi4b_uXqR_`u8M3s0Uc
z!L$qGuJj?<jfXb2r?aO_YSjPD)LQ?1?zSJ_R2s?lO?ujVbJ8pCdv*I<b6z|A@a19c
z(LMdSUw(e)(HlS4`&cS$oVKUfsI54=ZFc+~-qOn31<$g1^w>cc-Xohg{VFr({d48K
zIdhwbZoI);cSB?DoM|#)Xxhd>8|K`L;k;O0h!2vNnzMJcS3W-0Ub)B2KWgHZe6f48
zOn#r0?i2R*RS&gh!#o>r_6N+o-iJ$;pFH>EBZktmHuv~R|0HAE<7~LSXg<_`$UnZ-
zcm1P-Zg;B7ZC`Wi4POe~4X2uu+A=cOp1Whdo@p9<T!#f_N)XPCbF-pmKAXECKl7v?
zN_@37%X*q0j%)4P<C81-C5t6H^9U*Tr)~5twg*N^Hrp?Y(qCME>e_)u(cERn{&m*U
ziDqUgRa(zt=Q5TQXT~xxFt;#sAhx&P5W4IXDW+%0<otlSZxVN>WIvnjFQ1c*%I}Ti
z><nLt4;ae&NwMvj!8GCn^*ue;n`lX6Z+`gt=8C><wj%lit7o2Wo-AzDE#i==j#O!C
z^~WVfvWfTEB3DcgO_GZk;jZV}Sjm)WzG<8LI2OLC&+)lb30*0g#iCL=roZjePNHO%
z#-((6hVdcGpQ#=SF3??mx~dtm@9XwK+8T;e)|YQIQohma$Wi(v-^Hyhd*hGyk1+oQ
zz(hUWSvT`@CX8n%V^h&HPun?dO!Z+LnzD?|+6-LSZ#2$Iy`)30tRtxxZx;ow?xiJx
zZdPXKM7vvK6S6yfit8mjsltM<o6=r3?CIKhVUo>jL(b{w+H9Y(8=kF@aEcRgrX9B}
zLkUyTu|9{O!iXWqL^CEMI*4?0Bw%btKEgI<nxQ{DYz3odo{pc5!>RB8X8d1=#L;tC
zhM7XW7}YCd4P)(1m3Uib9=EVm_7xoai#51m97Som1^KV6h|R{aM%Q4mSeFkK^qjFZ
zmyKMvWh_pY*!i;kdXJNNK*t>}AD-OPx8eNN-A^C=%<GrD_9JdelX)9fKQwvQwLgFR
ztp}fcckY|NJn^ZwUcGzQiO;-w$rpaanWv9^@7veDdGoGopLu=si%+h;_U-#8-~HBx
zCqI6|yYIg6=9wp6`Sbfe^2}Se{`~Y4I1_dE?@oO6nfniW{q3K8?9500Y4!H+ymS7m
zZ{Bwz{tG|xogb{8`@NSBeD&GarvLP-cYpelH-E7D{x7~T`N3x&Iq?UF{rrk+zVoBi
zbKiV%@=xA<?Er*i^$gMQ$GDf^qu)GJvWulLoiW}KjHLRaLFqrp##4I49~p#<I=Wqd
zZ`AC6JaYZM%Ux}|?2Mq_eSm`byd1zSsol|4E?UrEh-6aEl+TbZH`N+@VBGI!uI+X+
zhK*fdr?rkPoz$G!F2(Ve0{K>Jj-{@+88zcR|9rN6eX+as`KW8_42HuqT7#J{w}$0g
zCbhHMa@X}X6oB(i@LODnoDX=;so$!lrL70`{<}fLMSp)W?k~>7r7Hga+x+k3{u+@(
z3E&a>dgf{PXX9~j(=x_#w+>N*4-|)Yxx8~uLcYc2yDrHwiDO2b*M(aJxXAg_wy*UZ
z!Rsse#odvqy7%T~Y2@m17KhT%N~N(dFX51rGX^;c7&nc4wBbj>%cZVDsoVo2*?6{N
zm{&cC&fCiDr8DXy)pS0lg{y~jm{ZM0?t6pYQ?j_QmDa_wcy#AdaT}yyAf8LrgZA!x
z7?-GRPwQG~CKwtuvWeV;P6DsfiN36)?RpznTXCn|smF^#mu^d77|UCe%-Sq(BCn9T
z4@Sj~k=8I)X3I~%bQHzYZ<v6NNwzokK35v9aNfxs@eFhO;piSK!nI8jIC5mkRIe`L
zt6W(D?%7|$ZjsQej2>Z6;(V*-lk+k(F72=coRn2}0$qWl6^g>Plsuowlc3;%qj7Se
z9Uh|jv)1EJj9JJz6xj6erN()%%9v+)gY4-mV7|r54Vj7zTR?SY4tc<Qya9WN_deMA
zYwG;G4DuF;rbRWjz@sOWSQ8evN!TDos4!rZkmYhmUR8I>Sh08-dZq3~mte?oGv_2e
z11}6@E$ydinl2M|xzPJM?V-&jFA5pWEG9fuZA|vV&`23052)NKXLLf@CKzqOe8+e(
zewalLI6)`<78|u9S~z+M4CUzEC>Td|ZF7g_v|2aS-c&vTNHt>i5)Adp&_0tT@@R`6
zmZ2GXg%6$7x!?p%Ya}_lv_jev#BGI^;nYXh_xccJz6TGQQWaL1O2qU^PXSRJ+rZ6a
z(<3FyulpqQRb1Z0)4emll7KOqacz?q^6ye=>+ug=rQ&$R;hy78*^<K@B1xoTRiGk1
zFDH||z>IXcAXk9||GbX_^IbM9j^Qct3$oB^x1VCCz|Nh`O6Cs#=n=_!m>oo<;<&J6
zP!o>dkE2+ebpcUynsnxrUtr3LiV}_9tB*mcd8A>Zu&%r+8s_ajvf<j^mbD>F1|{Qx
zq<l#QMj6WCWeY<2KUMewRj68?F;80?Q%JrUIx-!jl&A_Q;H#aZIAS#K4ib4(?pU<W
zg3pDHy=%$i_VeH%#u198%mqm8>%HiG@s`xk_lx7WdA&pxZq8Jh=#DlY$^taD^%2gV
zxJFO!5rjEwIl0Xp;lsqqwj!Ok2(!^j$k)=<C0ueD4sXyyJPz?%w1CrETK^PsFgcGi
z?RGGM%G^#P5{XCCHnCokmdI*EXuW)yoSS;+X$Oc$7!^U1k}CSZm!a&vqa5QfrzOsr
zCkN*#VYLH<T@nz+$jD*yTO`)%X^Xj>3@b_#8H7O*{^<D&7IMDrDZjv0z>7FBL6zX_
zQ0QSo`y5ksa9_}pbkrr=RlNl$^w?<8ovKMlhe+ai(KIElSn4-~VQqyN=Merk+Js<;
z2#hD0P*5^>vdCom)I{6_SqH&kt*yv10M<D|LXo|psj<WaNa*kakjKrrY`_EyUdRso
zAC5Ia_4Gbk;x-X7+^}^jtpyottt+K$EIA0Q*UiU(GmC!EK_a5VVq>C7qB$Fa1z?<D
zVSv7djglHwqwd1dUSp4tp6ehL6z&f!oD79}mW@J}VDRI%pR+F#FSWjUSyWz9s1+&8
za6`4vm%7>+wr~tw!1jpPuSj1NL75h<pesp!1<P>TIGG<g8(*C3cjPPe1J0}!$*7aA
z+9X&k10Qqy94j1wryTojzuCY7Wf2*xWM3Z9CEJj@Q(^&SwP?FXh_MB^KX%dkOiJoa
zqBEg4a2_p#o8U8vo-!;no|ZZsD^d4YfwZw*HbK&rv4Y7vX+M>9amvTCQxDEai{G%G
zdAi`kpeY5{W7}44&2EXea7K2=C?(hB^{eN6A8}*NYAyUwBbsj;GH4WeAx8-sB%NBn
zZLh$_S!WIS8!}Ca+5tuKAS-oqQLZT34fmz!@%|tbZ<>ommdPz8SIDP>wr^4og1$h%
zS1ZDq#Q>?Q6lCEIXvYAH?VEkQ;y8mzDHUB)cK#w3N8dEjw~REYJW*ZNbQ3ET2`aZt
zEQ;7xs$P$OtS=;3D<duQ1LHmS&&@QRkI@ZBvVsG~-usLn61${-#C0)<xsHY4DDqvk
z911;HDLA+#=lPJ2%*umT{u~0eV5XObrEPy7W$3gdF@c^jp^tGMeU9~`Pn56M?<vOK
zCcPno^+2TI%qHifQ}}2i)#ik}KC~8k9u}m5RWA)13!!*mqhkW0VM^+W<Go9}KbX9^
zAfiAJ8UhAIAP;w9cL%L;D6Nd}HU0xe9PX-zqL!eGT{o4-S<pg{?~q6xCTba4P6g53
z3@sGkJA_-r+PK<_H@O1In2>ECP%7&lVDFrIoTh@TRnijV)gCua<raKEeJzWnKM7-B
z^@GYo&`yGij%wmO2(|6QfXS&SyBr?iI_aW(&U&wIc2<%+AQ6SXt~zXh_BO?#K9#s%
ziPa`qz%V6E4FO%2^0M$r`yhb>v@Is|z<JS!!6m4ewkJY;uP2yQ97z#U&ez9a!vtP=
zauk%YHM|;zF`Q=|QU_-fdr9nYGGyXHPLYlD0|}atK#S6iCkmZ+LzIbEV2mRPs+G8+
zd5=G=%Al~zl8uT)G}5J<7F4dzD<qv0#ere{R%hEC<1}5_ks(D&ZaSK{%&XT6CBiB_
z5%AqsOH`{I%po6Xn<Vpu|Jj6LBBHRtJXFLLKw_;j<WON9SK{zu93h~!JW7a5uTFN_
zesDfP87SmUQdx}iKqLft>V^rnQ+|kF&I1YiiW7)tv^~*+AxZ)A$_b{bmR?U9Tq>jL
zMhn9r_O$ov`?H~w)vRf#mWH0gdGJerj`gxLp-E~L61`@J3JE&(nWvU^$4(HXwGP-$
zs<ui1_RtQ6C<!IzclzOe=*@S8z_BlC6k`ULBnK9B)^i}-TP<GYicTw8cA%BSufT9)
zprYx=$-^FFnPdngG$3L;YE3*D!}!i42e40YxkOL%GU%o#J(*oWhK>e2q>oBQt_r9n
zmeceJkz7%{XDVzoz_AS9+4+S?VwCZ=;tHMVlbTamy5DHjh{Yn-GCJ@K1NRRSoJ7@m
zoP`?F^&Q1p0Igz3$d#F{WI`9=<sVow70E^bkV=VK9#{*$0I#Mcv2x<oNf>9Kx{75a
z-7)A`fw-g*mPALC7xuk$o-)`3NEOf$KctH|m@;z8D_sn$O;)0mIxAyXmY=2-9gHMi
z<pSajEoFj%aGFeEB&dW*t%ZCIFO99$!b?m@_G!o@bZj5Ca<xzlB?}Dom6Vh=4$1*^
zpEx;@3;TK+?^F{k(TUNsB?6C{g(QI4qau+oIgmC}0z5v6VMb~tixaQqKqamRG-A^x
zwG}G|fs;p&RE=grMuX{HGrA1dF?uGn?D)nS8*B87$`jdbcr7ILkE^pEOc+X=Dxn1j
zy~H0{yfCY2F>yMfOqsL;Qg*^*h%cL{(|WIA7A8y*phMTtAs=8*Wt`KgWPl`woO>K4
zOBseOT=d0`2N=Yuib_c9<RR_&aTB#hsm6c}qq02Z^@N`;q7_Q3QX+vQiBl+wWgMO`
z#3G)*j)|>>j+k129eLv8`Qxy#4;fEbB8EV^natM{!9XEpD1K{{Pc@;#n#0c}#i0yn
zxszT20CPMDFgV9eNIOFEP+@TJ+)uBFlbRd4@q9>CM<aM_M;nL+AZd?99>ooxwVL9#
zI_^wxDZ0d^4VXF-T*bDtTw_Xz?Zhf&uTIIREd8yW#1%Kr4_ttAOCkY<+t0qGZ$u9;
zo`b&~KGSlN`U&q4_X=zyTjdd;@O7SQyjq=RR$W%D#6+z`KCtUFPYAdZPJmY7n&(MS
z3k*=;nyYR@z3sp#JU9dX=qCsp7UL7RB)%;NP@bOkg$p`eRH7t`SWRBS3W&K?!YgTu
z(>PpxR&s$ifrqTp@ysm|5Y1d2U(hI9;0aWMCCDjV9h4+`dC5vm(3w9GjvM2g+8AH-
zHfpA|OPQg`yfsNUN@Z!@J<O<IqcB$6P9uAL5~Hl33rPZJJh3(@WGfV#)1?kf>|mvW
zK6`NES8dj(xNt+GQ(!?yDKyaY>%@C?l6@1m#A$0b4ohH>sjNbJho@s$)>2Kh%7pfH
zwu1_4iJ=iql2hr38PO35gLK>;5|X0QJ9vz%G*wB8*bfnpP~eQ-)WI#lVU&N243XBz
zZiGYf5KqUX^bCo@b!24?)u06+{G>XGI&h9<LDv~3f-20j1j3V|)m$R6UR)@G9|}v_
zJ(WO^kaPrV!|>N8h#Hn$Ymr2iY*mvZc_65@eNG`k0>7#?Xk@&pInIgG&M^7b8BYML
z!Wy+m5_<6D5RVV2=L`=_IyBz4#dt{!2{2YIz6WAa6+*Oca~h;F#RQ41@4x74QEEK=
zh0c-ELJB?5{3^EzEGRk*s2s1ItHEk?Mx&%O4hsA;p7zjWxZ^cq*y`(^M0ld~Csu)Q
zJ8xvTm*gmvDLOs48#_g$2SP0ni8zVJFlq8U`f6B!xR5HhKR+%x4@M3<_vFW6+WED_
zdH`}fmBj*2yvnQ7bUq=#gc)4MvY3~ED>E3b;lT@a%B7Cecr=A1K|`Gq*et{x4t+UH
z^G_tpL;55MBmzj{wHgqrC5DIPIm!<ur=7Nulj!C<lk}FUxDrrPr$Q@Am*^`n5|9O6
z9P8jV+OouvQ#uS)++dZb4!(c_mR=Nn#TYNiJavlgD5c#Y)ehcqKOX1wMLPU}b#ts!
z9ml{|Up>i(`T`D$YR*(eJ>L#cA{JjsBbCqgVz17`Xgd*hN*eyc1c}zL@z_od>2)n}
zYOLLB3O$`zY^@-1*u>S5R#ymQ7Bz&p2RcbK*ht`gXi^h6<s!`SlK`qzmk2uLljI#~
z5tDqoZuS=ZytC2YO>SL1<BcoZz`vF?rIt9pJhymfZcJ>wkm9_Mqxj6|%uKbrIgiFD
z+-U~uDOZ+?9WD6yCF!a<-~5-X9hQ4oq&UON6GQpzEqyM~v0~JeAMfnVo;3_<70<}7
zJOdo>Wf_~L%cDtbR0OH7_^dx-L3Md^R_IP^`IJlx9?eKI3^P6MW>jE=wU(5(=E!nR
z=Q6UH!uP{9TSQy6XqNZ+S5RH^WopW#curvJKE9H6h8ke`2wHHcNwefwNrgUKLC4J3
z!+mv@%w92MlgUpoE1ZybyX<uZpOaoI9L+NROz|fl<?pknWh8VGZVT#WIKRWYvx>A$
zwC?koY-Q+~ruwN|FOk}q-x>}Zn=!~dlPSck!m3#;Ka~EIUyv$KG>)O5qexG(g=nMH
z9dc;gP#I+q_b}VQT|UF*s44sLoG)-_a8U#C2SuiLyrVZg+F`cd=X<`N8yaEEK2^#-
znzweXSx#HOlK1GlcX#<$Oj!4QA&YzA)G#)!gQ-((l%NoH$$*p574`ah8VOf`f8Hsy
zljSRU*IJ*QKO$(@?Ipeh(RxhG#+Z_t8)wZX&KWSZ6uj|`BVC@=?O^M%H%Wl_Lv~bl
z4%G73hq58=Uqh0x71!mVl{K2yzQNnm(OP=Ff~n-|#bF6Hr=pYlx}(7~tMA;2u%pk!
z#!u>x()|?X#k`k#jO1G4#Vmc{8$#1mLcim=dPsA@z$Kqu$Zu~~JvsBVU|``@*@5F<
zAN|4iZ?2qKUAJJ?2@CrNjz3}FbN|@YI_0tJ8VAl=SQyy2@RdiOd$RT1qyJdA`F|d`
z_2%ibw(WlL(QP}Q`++~~A7>RN-!|*jjax2wwfWoyenN_G)vcNQ#+|Q>zOn6<i`r}N
zpX}GJn|y8m>sNke!SBb~>(+7RY2AclAA0@LWB+v7-#_)(hEtw;?79gH9vHjo;Ri0g
z=6Nc_J&*0^>Ob_mSM}!~S+)2hzkcoUkI1X-^H)BoXNVS_bKJK_`(J*i^xkiMbJ<5e
zv1ilOAOEkhKmGmcYtH?~Q3K1ae)qdyIP8!A{?ns=^2E8fy|Q)ne_i??cVB+hch7(E
zKkq#A!k=yW{9!MC^2ASHdiku>N3WSR^<!_`ojviLyAD6=ox83$_>JjDop|wypT2DC
zg5JOV%$@I6Rt)^{g5N%J)Yb2N;=eBacJn=-eWZEdQNKB%dj322UwiJaUcT)!zxmy5
z7rgQEAOCJMYx&3BIP1KlZ#?Jk-??wrhtEB4=$a>{&%3OBpj@W>W|tm!acSW5pDqn-
zKB4@PU&q@%d+AxL1`avunq_}?)W&nW?uiFJcy{}vKYpeCw?nUNzv|RmUcK8~75~%n
znVbIk#p^cS^}$6eX8dt%$APJHcMJp<zIL}+_56WHU3J;i?7^?yRvEnL_zT9iJaYKC
zpB(t+$3HW0>&n;Od+7(pZak{+P~XI(9*ny`ec!|X^SmG4GxNNCpSoq_7r(16*!R^d
zif8N*d8iSsICg#J;-77qwRrK#KlY<TSKrHxzx$GVp89@uVCg-yiqkWr0|$Qeg;o6v
z{(h|Y<L4A*##6;p%IE*-v-y3?&OfdiA9&2>`Db7C`@*T8s@M+}5Ag5VcT9cN;eR;x
z*?7^n&r9|0xM@!R3yt56KL4e;U7wkJ>Fi$|aOqVSeXe)WZ)T1~pX{4Dd}ZHJ!7rv9
z9b8h}6ui`|U-C*keQe(&Q%`;HYsIs_aMQLWKm6h^m;9pljjLGdnyP$Vb`5&*{v%h%
zQzSFcJ0gqAAFW)n_}FR1iG!CF5BSyO(f7DdEuG$YJUio%L3+>c7vrmLv;Cic(EP0(
z_8*`Ye&DQ)^WS^O;Le^@P>DX}@*n)q%S?IfLn|is1}i4|(%f^aC)fWY)pr@VpE@!u
z{A)P(;ETGyKVx6qEbQ(tMvp&y+p-n$zTiLlw=KKu$V^aaE<S#5e9YLBHRKu1Pu(|Z
zaPm!=7o$SY*5@)Ox89(odR5OAWn^XR&Y{xYhfC{sEO4z`GG}ewo;kbn{IZkeoMl~X
zov%B5!=zI_@bZEU^IrK%eD9snK=YRa1KXb~?3tH)--d;K+vW0?=1b*IGH+y++%)CR
zXx*H#XicgzGH=e)OEPor%-?&j%YUi(tt$tMU%zPfQO)^#Q@{Og$-aKOKjs4)?>pva
zFF%mG>gDy@?BXri1?jo7Cx^1~d3gJU^7hn58ht*E)*5PAo2t)Ao0Z>*Mp`2yUBM4W
zhU6X^-mPKK%K_XuryoJXM{8=`7n+;%Q=-S_o)sOJ9_sDgW=1#3*LpX}`jOMkrcLvs
z>#U4Sn(CL_aQ1JDrZkY>yjd>J9lm?TV9`cZk%xZ~JRG-f-PPx>TbcLP{d#MCWoYkp
z(LEbWt9Hc4bLu6xbce{D^F@9g)&EZ1B|ehUnlplOc*ZH+j2$XdqeXNUU2?;`$(5dI
z5`CGzYar8A*pLY;6EaT?%%9~8d}A)IJ`hCDWvaILM5+=W+GYH_ld^SS`?EdVtB^KZ
zT{_+>^);&^89SRbvR-TGP0Xm33G}G7ZFGNMw|DxsH*51Nv$b&Rw85i2Lzfi8n%<*N
z9_c=s6`GRJD+lGmo?(%X{4d4;oAaRwY>u^OOJBMaS>Htu)|D4`c;1$rq3dV0&k<&c
zQ#iszmuK>9iPPbgX4WNNxQMJ0J_4wIaT`RjJv)p?SZZh3#Vg|+-O+c{7y)pCYnU^%
zFf1JFWoEI#l{WO5`75QAjcbzb>Z?fCv2A0Mh1|&SuysB2)cXP)=qqNSaTR!B<W&|a
zwN_!#%QxaOTn&Gn@m<78F<;~R0R+&Uh>vYLy%Uz9Z-=eRr?R0^@4uZ~`68QFNCMJF
zaj3zHlkBNtV2rdgtYxu+{*4Qqgib#$1!EE{3DC7AEV^fGINTMxK@Nfq=i$gfFEM)N
z>2H6z-}jei<q3Z*zTNvnijS&%%$-L}V5Dct3yOJjbzG0mEl$q#%f!+5*k0jaUg>~B
z>f%UtHj1*|gE=<MR8T%vMyB*V&P%0XtJ1D9CJBW&S*&NCelQnTS8L(dp8do3?mGXW
z=}*sl=Jl7}_~|<jz5e35yUzc{VNV?P^FO}z>JQ$1<k>kl-}Taet@-D}zWDA-8_rz)
z&W{fIn|I#%#vT9syPv-M+gqPp{m4)6KkV+`e(?{#`{tYP{`QV1SHJV@{U7`J<#+t<
zQ;+=gt>519^6E!E_{RzFzIE%Te)q_aR)6g~@6LMY<?kKy?%O~4)bAep(du8^{qnW{
z_2l;^zq#e-t3LVak5=D*_luM7_}yy<KY9Q6uD<pgKUjU=PhUK+U{n%5(lbPZ5vz0q
z(dJB4Xl0^%!%d3^r{vjpG>mvMfyvR;&c4qCoZvG)gGxRkL-Nl%T-PP1mUu&JBskRn
ze#)fUE$?rvX$A#j-7MdpGpV)LEH-9%-bSuu_SY2#8maJ5Yh_++x-xNof=PWpJ&i9V
z{~|m~GBfw3i}Gl?&+kB_666Q&r9EW8-&zx_^;3h2KWd6{t48_V#V_o5)sFwl{g=@H
zXBXAruMECU0Ji&ccp{m^XZME@<oCP({LCdT9Toq@*m0-JcfY@YN+)M?7O$WtrCh(X
z38~x4B_nLUGL!PUv(o2XK~me8N^hyK+R&=UwMcrbUE2++B8>T-j2ynvdiH-^s>r1l
zEHrd?iMxIntb7oz&ea+G(dfeC2zMg4B~mu{3|>$RBX1`Z2{m(=T|3<gFG$th!d``s
zO)CCP+%|&@_nJ$oqf+lPOpy(EzCf*SKG;?2*(&DiF}2*E^mW4pbm5|2rVzs{BE+ss
zcFm<7<U2hhv8&62FoR-zX}N{zvz!s#q|_;ulen3}a_AF#xFJ&&7_Sz^(~L%JXd4F1
zlxW;PVJIl=a^;v2ub$1h{8!}S3C8WAT}q>O&j^6Lf*)BIf+*Zgdj$59ig^JsYTC3X
z&gue>((S0pmL(k(;X7ZwEos}>LKl&t-3o@w2Tq#0%0Y7^v?<~h=T?oxI1ywkQJu_&
z>Wj5S656ITU{R2_mgr=9Wc$7Nt!6D=uk9o$*Jz4-5iUbuHZ_CNSFEj8qGWMg>4)=W
zV6zKoS9=kQ)un-<99~M_#HTl*uggO|3UhEO@tU|_tmn&<1Y=5SX&&myGc-J#z0fsu
zhcrzR1P8z+&1>EoLR7A&Ed&-gADFani|dh`9x%y!=Xv?eTdqt9q|NLaWY%-4#~hIJ
ziYsK2E`DQ1KEQm++)$w$BVNFjjUd*tcM%84>dAT{8_3923<+FFhDB=D_;?9eCEgQH
zj~#`cisNed^;p_K1@I`-hAF>WV)fJ3CX;QSt;--@q!+SJ)d=O5Vkyr{z<@6&v};JJ
zBjTK%X=s>BcsXvRI7{jF(I0{Jx)ciGh8%n(|MDo;mf4W+$|;QsT+1T3cQTd)=)51M
zDPgDT&PkBiF70(?Ju7nFKagaX)mIQ5+-AkvVZQQA<}DE@Nj%{?b$R-)s0ZEecQXp!
z4{FXp8G_iVgVf?%p@iOxbqplMwFqZXfOEb+L<!Za)<C93_0)uz8ryQcu;k(U0LrTm
zOj0p%t}9lID43Ch=yFLPfU`10Sbr-g_fQ?+Q4cjxO5(qcuB#c0Gd_z3Q4h3&1X7%8
z`$ForG<^uqj2A+#T~^vbsxA6S+)9{iX-R0s`N6D7L&pO^D)Hqw9vKWHc5G5Pl-I>1
ztgyT|Z0j7aHSk!)mJN!Jo12^?CtaoF8+krZ&Q!*=MMP5-MHf~%E<p<4%F3YE90W9M
z1u~`Bk_J!mY#9m~hDdat3>IonlFg`_fmy&Iv$5yZ@1&<HzHYr9h%4d+LjuPb4RY2c
z9Cj;hD+{P?x}5D%VO4qRW&av|))3?xPv^uH&fsvIvT4>;K;WuI!_!zivtS^xGOJ}3
zXgPY(|Kxspe9j?Z4huLA+$jt2>zss+hX+p2p>fnMbP1L&h+FcWG&#71N@1YKSWdgh
zym&8&Sy3q14CO?ORa7d|qR?{iWNDl-i-XxJ<7>Y}@x<~d3W$J_b&)kW94Z3ZvzQ|U
zy3p=~6@<u?L+dt7wY^Qp5Oy}l>hw^ev=+z_puW-DZK<$c-t99a@avSBTo3Uwtx<)|
zP4JbrvhZNTOKpyt-&Nv*MhOlk?v)sFVKu7l<=}zMHMjLot--FD)3d(Hc_><@e(9Cn
zl{36#yUD+IhF9lE!k${8?;Io>`W$}VQDsaFKut<ZNZ~451~=JpJqwKMVfT|u&AoHl
z&-4{D-c|ZS4wP^z%L?30l}XEaNuUzQEKA-_WvAP6Y6%&~8HTM(jocHuWc71ImuWwa
z9>;P4dE^~Ja9UL2vX;pmBDsv_JiM$XQXY`HmKvMMoQxa1a;0yA+M>O?=I(`IyK>SE
z)tYC)cqk|!5F4VGrfNbjgZ<|Doz65C+jw@d7{aHQJ)!B#I9F(be>2wu2ZRL`#`aXH
zQ?03vpcvh5fO-<90RbDz>*796qMK^Vc)(d<4aK@zs~fq#0N0F3ggev1HQZ)K*<%7Z
zc;^b8V)$%@$`YIRRjjs-*ISdWxxlWX5f3MZF7R@A2#HeFN>?9!g=*bUA?n)Z<EUox
zrqYwz8UMkuzywyVcWb+xRE=C19xqcF!qB4W8ImV1qY*MeKH2Gte7}P*e+e%oah9}c
zmnLLH0`&+L4uLXk$LSNWyv&0cI4?Tv6}Ci#cI;3^_EC4J1B@*y5E@J%2#Y2{|DMDh
z2UeenMLJAdEsV`|o{*H4$d+_Tuu=ACy~MTg6NVEI$tzuqdet=4Dyl?N65=FLQ{jd!
z9WlX)Hd&J^6G#i=0ZDGDK_R<x<d?dg7~NomU5|Ky)V)H1UA#aPtyZ8v)AVVLQn~)*
zY7K^$ZgI()dD}VsR$2<*;s+k@bvO{J2V3##57Z&#C23MM37q#judOZs33Lvep0`@2
zEmGDz{T}P$YE(~=JCb(3O9MQ)QR7meW;W@_zc6rUia8waw2#4<Zqm6V$ABpfc(BRd
z^au=uwnkR0_sW?Xnyf$Pd5{}=#6&3?W14N+4si)I5PI*FOP)#w%m~Ynn~)<W^iag`
z3u!JiIy5S`dlzeVHB~c2^`LD!2viWtYmJ``q8wu-aG4Nnj`2HZx9Y@rei&+rw$4gY
zeLiGdAY2rjc*$-;1B3t!H<Ug`k&9HcROxGA!oxy0z(jbBf-MYObxc#!6YUA9ZBZv|
zCq0!Xf$c&_kmtamI0g+8Ivo5u=?#g8WIxUXwJI3#d^i(cI_|DMOMse@Bn}RELqYwP
zUt~6@e)}G{1*;3l4iH3Ta3-d$cKE(~XeO>t0+OsW5-!*#LJolQaqQ%&DTybLlVj=>
z`5emu6hOVs$U;_XXNE}tI?_VVGzdFH(N&=}v4<VQ=NA>2fFw-a;=0s>j0asZ8XBtM
z3t-l1aFUWEm3YPrT|-0g4U^fJJ{Uj1R-4zdgwCy%lxIW~z&V`~TRx5is$e2r1OS|;
zE5t{LzD1;Esal8FLMMS!my#DWN=wM#s;f6Ku$aVU=#K-4(6887WqJMaWEohiU`{Gc
z@i;VqA12h8B=-=~u?;1vT&mfDVk5f{of!d#w;;d_sfC#XL&RB&d$^@`63@_BF@`0F
zEYNH~Flu|Iu|ZwsUsEmVNf3oSPSx2fJBX$$9ML<7jUVSpSqV=Xh7?&6C!r$)K_0(!
z`zk?doM>v*XRBP2#KHkelZcJcj315wN=z6gU<yLp0;e87MTEkuo;b;Muz^I4(>4f_
zdUm9j{%60etWwNlHEj(SEx1n}I<CXz5Tb%I$}m<R5>~+P<8pF3k{~4p&bHRN(-L<9
z8-$u;mgqb_P1n$ds>FnYdq~tz(~#s;qn%nEqcNDOV+I0Rv3{bd2xq7%0q}S%=cG4~
zwZ<bD4?J3^sWc-=>J|=ou4`SR*!=$ZSgb<itau(_J^`i>l})r8xm}_ui+#9x+Q6DN
z&X{p>2qFi^NgtuNyQ<NY@i`TBVl>y^5415*;)zMlk1^fRd`rJo6;hR{#W{`kWT;CW
zL1GI8;wbNVY8`+%5=Axg(1Xw%aG2|@WNOqN=V8bY;Q29@!#D0pLb9?Ew3arojfkwq
zVM0I?xc`f=cY%|us1pCrt-jN9XEG#rCPSFS7-~A5*ojd)A!1guSlwyD5CTj>fXMRb
z3=y)35+Y(y4Aq@ZGQ<E)h!By5CPY9!>lzio6(5}k5I~m5TOJZofmIhUD4-zuf6wi(
z?EZfL|L0#beQ!NZojP^u)Twt}8P=++_?^a9)9J`dViP}(yezWdM)+G^6eTo45)?U2
z!G%~YND@EhGjSVW<kHv=s?|!>4<~9|3&tg28a+o`^$ArPF?{cus0V_hs<-)a;@^6(
z8UKLGDKGDSDsfp59`N>w#ad_zTL?krw2q5!9>7YVH!TIFK8`;_G?fjkV)Ri$f~+J3
zM?v?5T1UNYAz&{V`W_FA(}!v;M+*OKKtv`Q%D*B%H>@^6bhV-+VR&k7f<d@d4uDUL
zg8;SHd1KcUEz~!8mlX(bYj9}P<d=}C9^(0FkkN_>oLa?T@AYa=T<_|*#sNmUBtUtY
z+L~C)$&*Bqf5oGME<UUN!Q#$22MR|MvRYh8_FIIB8IKbW4J6*XWu>$jla;2A0CeJU
z4-g*8u;ve=x}+~8uqF8xb{8Z-zq^#BTLWZ3%_hsq!7?JaK!$HpzN_7n7{FRblq(n(
z1dvaU&5$a*b~GNOJ6u#0YTAS(opD$(`dwX(>VQ$hlr~^if@0!L0eFyWphM}39Hezc
zjZ2=%BT3pN_c+~#J~h!qy!EJ+ZNU_iYOOq}D?4Zt`$0}`5UodIumnGhGd_6>B1WGb
zJ1K`D(<o{`U|4<8RS_U~Q0-ckA9r4VHjW){;^~W2!XBkA>0;TWbl8D#KvgPQ?=}Ez
zG$gRPFu}Qmgc#19ONk>K@8$sxz-YoLTRIoYQfgO=rwQ{tX=-=7s4!7rDjBL(0KWtj
z+P~EjLAQqR5qiAE<3vYus~k8eZLf5^RjAaUT9h+rSI=Q@8x&l<8@GZ=PWR#*_YAhg
zsa{Ek%W{rIfJY@}4}=_e#U2=^56ds?bGwyPOuyEAfLv8OsPr(BlC&!{`9#NALK8oL
zL5?sa@rY8AijfLl;`mv9WBGaM^A@HOiM(r$5o9hv&S9qvl1V6sUAef8R!<G=c0}Zh
zlsrJMiSzQr=YJy*65u740>|G@)mla*29~4+ye5lbM!<&Rik*@rqR$%k<KyiT`eVg)
zK-1a;zbPpnqi<?de7wFfA-{%V4?UPIa_AusnWo?jJkfd#K}vyDoLO~heUG*#^d_kh
zsA5i@SdY}VZIR)y4)ar`7FZ#Y{<!KufqNImz=qx#@i?7TCOAzz3`4fgX@)UbehF@M
zXne=7Mre`^LW=M_RMJ$VB;>#^HIARvU*g$PE*_^##zD;IYa}?ReF*r4j!}LS&w(k?
zg@iLgC%UsqfT9f5rbb~6fi3JzSlUI#YJl$3`QutFI%O$Yrs2H86}`@nbbWI;Uf5|F
zqWn1NOY}If^N~_x|H-;Jt$Br>fv{-iOkE~jjco>6YP&|p=t)hGIp*Dxj!rZz?n>9Z
zOXIooce8Q7P!9X)I~FT7)4bKp64o}mKRsNFJA&pM7pJ|?^!l-UGNg?;AIdhJF{hX>
z#tSkxrkcL#OkvrSxZZ8rU9j3LbTX^LP>>tthGncT*zCB@iXqnYV#SUN*88LB)DITg
zi^2BZVi31&={)*22y=z$!Ph!-aO{+EHJ9()$@NE3F(dai0>1YaSSFq#y|=M%dt}m_
z%q?uA-ueRSoh#OshBCK2NYNZ3^MV1mwB-Eu!3<cBQeGaxJx_(=V4n*;HP&A4_qa2~
z@JSo^21mBa`}zwkG_96tom^|wygeQcx9=76nTWeHgy|cp4`lO_zE8UD>5G>~HnVXF
z9|!3S<AQ@{!$TY{o{8k_lHnb@;BnZODS#;IXUUlYmV9GO|8HVCxZN_R#Ac^mrl%5j
z@Xe}f6ZI9Es;kT7??v|v!?c4J$o4-5V^S6BPj5$5<e+J7sf~l^=%8q&tI3hk4{Weq
zg$~_=R4D}WolFjI%au_cm3Vk}X4+tHEex&}cCc-k8Z<4-WNDTX%*7+F^>Jq|qdj3e
z|8djL>oilC)2Z^yd5>`pLg_gl9flJnH+iVrNoARIl${UFGHO+i%<z4>=jN=*#5}lv
zkbZ5dI=FgWJZtyLF}ZmweYCcH<AR;5<5|zGoVoahm1_s@U1xrA_s+QQhM95SgxPDG
zJ6A7!>E7*f-I&>N-_^5sEdO<3&ky%5k@sISLB?M{;o-r%3w!FXmh0E8o)C^-Jz@Fg
zy-QA*wQqT)mKwEbd}`Dp!ctQ{zoM{a;;1XH+j-E!*?(F-;^J3VZoh7I`}R$#cA0(t
z@+q?qTX|n?b$c_usl8+NzLiSvgW5l+J(BA9*V!xgtUTyj)wkQeQ#!{llh1Yj{kXfH
zUN~X@TMs>c$`fzxoA9%z$36Y4KaYF%Umjk#{C78>H2Wt{opRTnz4P{O+h@MC_o9s#
zKe}x9^^dK(|5uL=J$2k=-4D<Iufxv0eoy;JJN}Y8b@LBCv3T?C<G%Rgt1f<Q)t$4y
zQlEat+t<z<_2mb@xwPjYx!|?UZ!JIj+Mlg-KUw$b;{MgkKl81V2hRM_38~_Zcb@pI
zH};))(`Rr0%8lo|ewfmG_E{qHzBBd<N56dN=j;0>etXY_nOnnK*B|S)`hhY3{F(bt
z`pPluuYU3epV;`!m7iJoi@y&peB#H;JHPj}PmFy1?rQPLKfhhP?$MX#&3d#v?}#1e
z@A&1m70r%)D|U2k8GZlA?cqty+vVcg?WL1`)fl_*SB>1KF8)jYl97KYKd~!6>ZFHf
zj2gYB_u`LVG5z9G-u(X2Pk-sPPc8d#t$W#zDhu3`=`)Xh+LYHnbNGUw`rQ*&=f1zh
ze`MPibnnp4S6GACEuUF-S$1rxdCkAdS%?0(RNhM~@yBoPd4B5swVQ9=xxx1zeO>88
zKiRY6uDm>SZNBqcuU6Ne`^z6KbW5x`YH2<S{4W-de0uxB^7IR2Xz)mLZu$IE&h7qk
zI`h$^vO|;Rj%m8Sr+i`7yz15qKJ;kg!Yi8cmCKv*kHyTVkN;9xO!5A3*}UC;Wn<%E
zCuW+5&y<I<OPaeUe$gJW`ozq+wJ!|soO987f7C_c@9&{^v3rfuz3jKlrFQ0i^7FNJ
zes9K4bI&~RuRG4XYU9G!zh^ctuig9etW@12ul+vWWuNR@%+cGnDbjhwl_wNGxA)WY
zc9dq#`&x6#2D7zqaL(S2#i@FCXZ+{$znR|pk6U}TPMfye&z+FpIQL7PTNkhBn!I@V
z!``)fpT8|L>Eq|j3KyQU!l#RI<8zJ6tN*;^w6&j=6B=!1%`GSDzM-_E9)4M-m?>-C
zKhQUqzUw`g`aQJ;`0l$;F8Z`@6ppRG+J5ff={t@)`pw+x;&tCyUwr1~5B}k#<rAY*
zf8H1OJ^eGkXzbL_zuiA?@uRhaI!4|<zoYc>f96iD&F^0M^ZUn*T079$b<g>3(cO!q
zXZF@l`)XV~c6i3C!3DJ$9dF*0I{22~OgU)l3+Loc{Zm8iEn~ymR;R+v>*h{*voiU{
zH&JG{*%^~=WzB5q>WL;^!)BZ-R7oyT+BcRvOW#{6UCRdk7!DSnZ_EqBj(IX^V0&;(
z=Cu=wXPMIU$vs_nWsYIu@ciqCa$^^5`Syt3`@0OMe)DT<AL)!=;3($JW6$yFzH<7g
z`N#h2Q2y9&xwwCL$G9m~$#i(v)=??gftn1=GV!_b*CradbYdL*u)jF{j$m@zn%>V#
zC4abO>rZ~JvqPQz^lLWc7VQu@o;je8OF5f=T;`8kJ0L^<k*WS$Cf#p-Wjo_1;?8l`
z&#d0o*&j~5XY2gj!*&=2-kh2)XYGYc!>MQ4_fMS{Z91%2+mo4E-n{(cy&bboDG$sz
z!S0<gS{gHs{s+ky_XM3sl}F6_$kJu`f4*SW#^O@RujXT;sdPBAaFm;|bLsG`LVD87
zo5J?&YvJ<z6JdGO=S046W;x1ET)xa6c42wy+JW5Ejgh#^rT@_)^giyQ8P8|K88tTQ
z&gF8>(G9uQu;Z4-X6ml6BUiLsxMXXc92?8EMN4OxY%UtgbO<d4Fw-)rW@k_Fs%<@`
z<%?Go>FH&{*v!e=*v<4a=2(09+^}Tluti~e81xJ+s$^-6miDvV_54r{Ul^8V&h3?%
zb9#Hjf69iv$9361eUKX$Gn@)9&Ix;)ODT3bcTvt^>3wt~E$JWwSskkunY$a5AvzqJ
zlCGXK=m)J?<Oc)hF1IzJfG+Dluuw_U%c1+3x@05~cPqv>g3m^@Fj>?#=OXB%^vxtL
zUQs+X>SAaUv0jzuhO{<%gm~-cy=({tVOyD7WN6+nacPiAr=vg7Lo_kVVmi*TZKut9
z&x8x#v%hPb8_Dk4u>Y;-Ku}GTn`GUFPt_xPWV&zQays$H#yR^j=!3k{66tcY;$Fss
zXoomBOGhqaYF&*1#!zX$X^!?~CZ}p$Q@HwO%pAXE=$+Re(tDiV);&+rM_5z5<Cy*L
zJoow)Pd#_x`G33f>A$YJnmtSVU;Noque|Z)`|rHrudD8QXw^^mzj*Ss@9g{a@Ap6b
zxBcIE=!hepzGcok@4R-)JLlnk<g@$ldis{p`&V84>+@FqegApS{r&W}9=PR_yWY9#
zk-xw5^xNNg?v*3%I_CBB-+JS!&+p%V->O&MI{T8l9@>A&Tl*h5|CRj@TyoxXzdPg3
zGwvAs)*Ekq;oSZAU2+tB-2c#P|M1F-&t3ABH;!3#&OL?xCod0g6!F`257E5G^Z9v?
za=Llb*?!qIXBIxbwju*BR5AniRPDeuJ?_J&7ftnXZ{+cHE_e01@`u;2l}{9%S$1YO
z2hY0gl!XjAPGOhiDIDoozo~!9j%xhDg?`Zo7uM1_!ZIi9u~Wa?Sbo@fUM|{MH};GZ
z%I4$~%GEQSeDF*!*^l;{?C94d^V-h1{D&ZZ{xy2XM=h|E&lXww1?}D@v(#F0$(|>1
zqLN_}4+`!7c)#b91SsgcrX@!2y8iduxcA)tJ?ne6|DB!{$Y`0Z+j;*F)W+>zEV*3P
zdYPwtOsGwO+MA#{w2}(s(u$3?g{gA7KW36*Vp;yR$<FoZ(sZ?9hPl+Sz=bjeoT02`
z@1(@v3c&$BygZ#hX<8XBd&ZVFWE?%0&y=v~mklv%*g~WGRwk3;$AgIx=?QzH{F^!e
zjZ17$l<^)?d*c-%UYG@2PuID>QIps+9&w-!eTO5Rx-eWF76w~E57S?U#iBa3gYQvp
zj6r6+u%EuW&vmwU4R*#Mqb%#k$b71XrL>@Sim)+dv}agVs>(s-K<1e$pGDLvRxOlW
z7^D1b5IdKFo_VAn%RLb~j4Z-h<=d&Jk(_pI$vpUXh@)f8auX%qW4RbZzj=@tFQg;z
zg{Nt=j!ck)z^0|<OQoi$f#`h8Hl4wFAadn0@cL}1TSqDYYzlKlDZ?i0&7zkuBO{5X
zZpPc}P;;I%lsM8CTMZezc|W>o(Qj2odoE<5DIPS0JLpOc1>{DdGwY2*Ur81g5+Ih%
zIqgjMp~9*e06U}x#(I_$#DvaeZou^i&Y6Y4E8PPbs73welbIfG#A*IGHv?r6%TyWp
zISk4Kcq3||m%`)Nvc5-*0w_Oqiim`_MITYV60e9p2CLi*0V0=$fxEy4vpjZW)cFk#
zMuwKNN=`<j#KFXxMp6vII06rh6R$7dPa+#Fic=U);*pA+rYT4A`yQ$C3Tv{0#myl4
zA+Fs$v8)sw$HRj--Iu}^_>wRK?Ey!UrLvT8QgndydU3|Z^}cSVh?Z%N<6MCRh}G*E
zA2HKK+VGyNDpANb^En=!Ek?6w^4*rnT<K$RUYw^g4zNAP@q&l6Mm5rOpv}_;3GyhD
zdKf_lHY!Vxm$<3(X*Su96K?~Zva|#@qM(eO4TPTDddnJyhggWi&s40kSV;sL<2+m8
zoavIbW<ofWSZT|2>2h+{Kn)2paiPf2RT!6jT7G>c!SYq6(m^7unww@uh|^%G89KDX
zrKOli!ioz~wuk}BC%@_XolCLSGF72RS1!e0#m6Rhar5pA>Uyj2lTl!;2L(b%8Uq}n
zlM`DXYf_YE5S)&Th#LU0X@K8^QddRX#R``6Gq*P1c^xM+1K>ept6JW`T75cvboNQ#
zgU~>;EmOq@S;I|%-0cz*qTGQ3nH8nAE=fiA<2>|jvK6FI4Y%ryxKChgU;$l>`y_e>
zR9jP)mT?jWo4M+UOa)|9O+P<Rwm|Jk!#GG(*)Zx)GVn7_S4CN(GU%~Xs5e&0sb}Dy
zSZBC*h!6!TGsDvQWGGS9tZBWOv=FJmpdL`SuokP5BDW~ingULWrNqmt);vWMl0}31
zLRg>$Cy-O&!*{8yCn1*XP(c4c0fhC+eMlmVm4tNI8yB$mTN2A*fk{I0qx+<R(qW&!
zL=8mF#A3&pjFOaO5Da=_OvtyWJ@BD%%42x8(ice0T#Caw8K3O$bnNG{6nM2p47SsN
zq)IA<{Fc;$E-6P%@!liyf$r9=b_Hc5uMGqgNIYNyZd^i8Ln+Y8&|Kt$*!J(bpE3`s
zrLYzulfaa%Np;KcSNp*ZC<Rb=d90LIkCk)?U&2U*imi>TK*9f|b>zT=!>I^@>z0hA
zqq^$b5U$%##X+g=Vly$4=5C0it>EylH@e(!IRCjaND~clz;Kx&X)fejrP@@Oc#$|8
zpw$N0j}lW$22EThC^!~Pgc!$D<IO3Jx6F&`fMkzhz+TEw_cR@Htp>$2pgkl36`*az
zf^_i>$xU&r*2|ttd&D1^8zkMFAG?61yPwD9jXeXAnU=RmieXQf?KaYbB-n-YW+kve
z8=Fi`m&=FKt?Ma9&iRBl-s~;&#XB)sXSwLx`o1E$&E~_PU`r1pI0Lav?dM3+wB_Ws
z&>ZNZNrR1?TaiOp6^+8#;fYYpoL6W}ooydo<pOn-r0JCN4q?=m$=1hx4Vtm+k$a4o
z{%tVyAaT>Axjv9|uha_4SGwz{v6)l>Q`RpqRQ;fniJ|yGZ^hD<ht4L8B-^WK<4;=G
z1U<(OkrC<Q52Jfb?%s}NG6GJ|16x&<CxB21x%?%D8m6iQL&pfyq~$^ld9~A!i+5@X
zt;!)~p_eDc-3%TelTBURn4Z9erp_H-P@NbL7Kv>XRlv^QV9VdNDKMy*!S@LuOtB&^
z)H&^tKc7qLo`k~$2cAi~7MRkg3F`cFz$=l1AWSA>k$Oy!5Kp4olH2lF3ASlhBLuvz
z;Z7etMRKB+#DrM$q#HRYst2uva)yD%4|vo-&dE}2gjdV@7V!yRrIerpT7xNIg4pT<
z9VzePIO`Ob(8W+%6~yW@uwHpc`wBIbtkn!zgn%9l+6jh%wPqDM#WOJ$D2$QKC~eYn
zK?7Q`5D7-oC~7b@!Qlgr@Q2ote*m!S>UWa7U%Nx(=tfy76=V<2DgbsZR$$`5k$f3d
zYowgSA!Zx-&}0%bQ?$~Slu@*rK}8V2(J<7JGV<aLTVequxON~0FF%>xoemkos64_^
zWfd_bpuV(-L#IJ`La}&sv~+lB<3w*UzeLk&8O@1PYmvC54VYJF%VZ_}uC+wHal-yk
z1lc8?POF2mNfTCMG<irS4V!p{)~Po-Ps<=Syb==%icfW$Qzv95hE8|Ol00(<D8~`j
zTmF{ppbxZYoyX3iimpC-H_vHInh@oY7E%^xxfLlQXut~3(6@X<9L@ko_>FG$a{S16
za%baw;%C$|x#ubQT%V)Qt}vR51Uo#b2PB(TnNt(;a}dC5SZxM6AjTIF5~m^ZA;(j7
z8VoF}uq3_}wIn74MdGb4kSd=oG?KQ_3g{r0E#cM^ti2cxPw^{>r`!@lx}hUVLi{``
zqmIB74*f*AxdY_$PSg>%IYFN~EI&sy5;S@dEbb2%BI`W<7(~n%xD@6R$PlYB4*YpB
z1cR9+Ig5=9Zw6zDgrL8y1Y@)hfYCiqpKPctcYu(|>KKGin-fn`2bdpCW0FwbsSm&n
ztpzP()#4MoYSBP>%nVG+4}FBqE~|^(Xn}D&XlAi#I(42M;D%;LBI=37sAe(E#E<5a
zA*S{?Jh_deoB)9VnFcX!t+GaA`y1^6yuOt*@<mOHWUHnaB1f2TK~-!;SOdX9*OR9y
z;jLlX=clk^=z##QZVj-wiILWwu};C10^gD-;XE77xSFYWFGWMN%<uqZw;bIAWKqe3
zf377t3UH-73Zoo}sa~KD?65<9w+aP1L7mkux;j!8-FA=^SXiK3sIOOh1|$b1WK{I&
zK@Nx)NQ*1T03JB_7kU?HO)M&tmcDD~;kprD)7+D9*g#vEmk{{K(^btQ<Qjqjby8jH
zS@9#CMqsWpgrPn}|KawrSPO8Sw4AnBp~u&iH0|YBJ=9v>Y1#4Ln_EPigwTr}W>!K|
zh*WkxNTDWF9`v>D9-1*-i^W)#;Fd-`z<%OjRQYNOga$-Ppc>^^b|-mi<pA!h3H0Ih
zk-Ti1wvjgR&#B+&A`gcf-Y~AU;Ew6Hw~P}*d;?{qq#a2BJ$3}dSVGt?pSTs;YSE!h
zyl5jAlPM{*XmFL5&W}k$C;?SSj%VCH3yrHbu{EWtNm`bS^HYY4@me*pB1qjJMPO-o
z`CO=GZGfNW7l?6ybZV(%^odL=4&y|(2mJewcqMARL&9`|m{=CimfRBN$)1x!OWCzT
z#CZj1J=GSf3#1itO4bJ%*y!wPVvN&JrNt%8O00>GvSk?CEM*MFNxwD-HEXjibWTDl
zr6`A5CXgmB2^`<*!Ur~Bkh_IReboMUixyr<n7S>$<k_-NnA$mW_<=Rf4WM<MmTg%*
zlH*|n36+9m<5mrBYJBCZ(t-sk*LuT%T$4dzmw4;e2dj7i(d1jiIUsSV4$!+E)cDpN
z$=%{TY2y*)Y>VuE0yXw{uxZC2Nj>Hh3|7JDq6Ls(iQtlkGfd%U9DrGQiR2RSGJXu>
zJz75@)u7QeHdH3=oJ*X+vRXo6q+u=WPL<jJFc6^uNp_Mx3XV`C1$d_u)%+f`hhYru
z5=?X}fa(<&mXqjEEuJ6OAv3;G-G#|0e`wVcp;nKqYLA*y9w5u!g37aiZ>SR%tLAP4
zU_RON^x`))Gq|#eSMo755yyW*E(j8n=cy2y77-A^HisqT=lNk+mTTDyP}5-vqW__o
z8~hSNbHD^>AXLsr@l#GXX7HejVj#6v&F=-)x+EQhtBZcJB1r(WxKy2@yN6p<te?RH
zD%U7^7$209w~ot`Z0U>(#il1F$#p;8nG&B2PJnnYkC>2HHZGBc&})XenbUEIjpjq$
zEfZScwHzH}(WF2yhP;q0K_^#mvBeYvX?R!y!i>5j-K)bV=JDXasN)^roL=S+2-E>=
z<Mj%vW&j2hcss=&IJlB9LxU8uL%Snw6|4b;teL`}C<G<=MfOU57p#gst%kO=KD;up
z;`I;m6O+IzK7`0+Ma7?14+z&vEOsq8sdK#m)`SADepcq7c`ddE(19Ch=}48*SbdcW
zstty;Y;s*xkoZ|GRG_m-s)SnwVr48zmueWOtE>-|P{doC1hV<x#w#Cx`6+eVgrHV#
z+yNN!n{Y^j9I<15*0&0Zq}4ZR>z!Kl1ZiUQ8-)Z?X3b)Pq2+Br%3Mc+A?NXHrNzv*
zvm6n{Klw-J*~~J6A-<=8rwT~qi}*P8)pVor7V81yBy3{sv*ZnvR4+<6Kqy95)JILi
zeFGD;O`>bcyY-JgV4eYg<XL*N&^KM-6Qf*!3h^{X$@C#{!XWZ^k&1FMQ8~iVPQ1dK
z_wv;BhheQM80IO$)k(oVsQYx1iWV&6$f{f{N4gRRpIsQ|rpKEzt`?jayDP(tk22jd
zFo_A_hZ{EPHBp@LWQLO*N1o*zCEeIiph!7KT50m3vwjycM`m{wY=J(I-D(+5#_^ku
zvj^F&(wpY97EvR&wS06ahwO#uJkxO8vp^QE9Q*)KPF5@F@kvrVa+q#uoL&ukyg#*k
z@PZhXru0qfy4)_#OYl5%Fw9I@&zRfCa_)qV-jVwG$H8prW>yFmxSTLAo#lejEw`S_
z@x4KD?H>}ec!3Oz6yIplw_YB|22&yz@czbuXtH(UxiF^2E$;bAE-ZDJ;hs#6(3PIT
zOn>cI3MMmC4E>Q<rsaInZf{mze&>Ba^>t3BWUL=JyelpY(htfk?(OJAV%p}$a%A^-
zz9Kh#Olq4dlTbW49kk$c&Gf%m%Jqv}m9aa{zjPU)Mb3q#Wx!3bH<qR9DqQd0-oMAs
z`=y=oN9tivihDf?x<=%e4umsOK0J6j6kfi`R2FmY(cJ6`J>9UgBE`WCmJ`fwFg`+p
zy$*Sm`ld<Kq$A1<L>b@Z8>b;dGedI_jAufr%cAy1eOj)hU7VS1^QJM-=h|&)uzO?J
z|3|TGN*y~Gmj)b5%R#+BrA9xxC8%xAgRbxOjZT-5FO;a+%>6BdR+HuoLAgt^Acp2H
z_$_%Sc9KnRq*Fd@;<QW;Yu*2lYp%X0xyNb$W16*raiyL2u5<T3vaWCT1uMtResg7b
z>73Pa_r0t8CR}_`@B9DpqD{a4#ZF(@UhErt#O(Oc3uiz2>hHI2`p*ZOe!}TTbWON^
z_S=8jyJXv+ep`-4y?;XZ{t1V!c>2}y@;%=x+fg^XzpMSS@#p+<W&Zq!pIq+SM~#wE
zhmNurtjtfoWF_}H9XHaiOLyfy{KJ*mbKhJ!x4JGZ>t1ZnrH@!X?WaFpId|tD+IKu~
zQ+xBRmw%vph@QKFQrx*Swfy=Y|8C_Qhd;9NjeSo%`N+_ny+1waU%Re&``Pgi{`kSA
z&t3HE+9yBu^mUtGp0N4re>~mZGUn;qe|LTN?XORG+wZ?_>*h-)Kk(=qx1V<1D?d4X
z!~L_*z5T}P|8wZxm(O_hxu33l^ogIAAKmxo#pfM0ch+A{e(Ho*A9-rwibvl$ZsrLy
zKlZ|ZT>rT(e>~!(bB;T1*4}%6ykf<_J-A}&{rgwUoOAOhd+&aHQSt1*f8v}=em3#d
zhkp8{z26`DfYSRqYvKQR_v2p}{KiiTiyzrIdhr`Gu6pwmD`(HVX3V&0&))s1+5fWZ
z%F^XO`SsS<&4?d=T~7bu=A{?Q_31k{eRK2Co9_5!Z{yA<pSksO6TY$Q@!!T9_RXAj
z-Tv!7ylMOR5ktFPKYsZ`+b&pi#igh2y5-w_=bc{4|LMeQ!&guKMq%jQe>*OF!tRgW
z{M)Y1E%#5Dch1Rk^M8KuhliEJ|1=kD*uElr!jg7#<dgZ+FZuUREIj$&`}f}4SRwND
z<8<%PEk#D{+aDcVbj+F;-~PasvtODj-(0-$yD#LgzHmiu<Gz!oeLw$v?;*dv<;TrM
zN6apM;keu}Gk3?|pD}gQ>c`KGuXy40?E0I3e|vq=mQ6ppaM^W>Hk`is#0~T0V{_+c
zcIMOm?sLcAzAG$k8aHOvnX8}ayYIf=cRsnNI(5a0{M_)^Q!cpq!Bb|v{?s}73-|0^
z{Cjut#}_V~+gUt&>2ZUFQ+tnl9C7~j*y$G(W_^C&G4n_49wTS3Tw7r+<i@Q^ch^;B
z%*@f1p$ppg7N1GU<x#twmtVJWD89KT!xr>vxLQuyv^gAiU2|!3{0Z`J!)<<Q{?MMG
zd{5EltI~7(*SW21;mUGtMW5SnVm$T9O9!GAL*8VL@<snw319!kLVMw(i{dkPy21Ot
zD!GMo=61THP1t)>7~V054IvNKyI(%))y%&1o=h>b^f+qOsk(1y*D{d_a~dba!IQUd
z>v-wS;h*31>gK<^b%7hZb5eQpmLJ$%lSkP-ZD-r(xBtcd{?_vc#LjW=FHNdm5MEt<
zyz1j+x8D?>_Uu<OkEKgfx2Lb1_HXt2><?Xcff?R>_0-|bN5|{S8~O%%n<JMFooa4<
zp)bDr{^5Aza~F&}_v)L|w|@A^S-&6Y^S}M+1u}Qd_~?bZ7uRpT`N`gR%u=Q8nX^Uw
zJ&U^HMT7H2_AKAL=zH6Sr){|s+W(;(Z=Y%Fy*+lr9UOvge%e+S)f}Im8DKQ#<Xffc
z(vUX&q)a^R@S?qK<}zDJ_stAz)3amh-D^v}Fg5DkECXG$qG(x|Ta%V_e#df&&srgy
zhQ#>sVc1olnA>&uM7!6R&Ui;xpF4;acYGXf+0Zr8=1P5Epa)R$GtHuUZ(Kg;R2%x(
zW*STAj@d;!Xtjc(Y&)7+>P?NdzIueNtSt${yXpAZj14&DR?g1#_|oC;=eK}7p+4zT
zoJt!v;5L}DG4G3uu1@cB4~=<L6B?6dDK5qXee(*a&h)uqXeQ--@enRYSv+oJ-uBoK
zBvsp2=5CTry<KrsnjdE8AJmf$XX&1%E8n77N)Hy}d_32pRdaDQKPzq!$1Jg|95~BD
zEc3yHY46t%Ky#>6Ru|!*U+08C?NG#z8pmE@H8i(z+~j1rVV8rAIm^g2{&jjUr-sMG
zW}AKQc<xP@2`;)NG#16<Ce#MXA<YCegHBGba5Qmgp9yT529GSa>7J$zq%_WFZC?km
z7O?`B%>6eUr1ym#P!Y%oI0=b4@7nx>vW&#Ua#pvq$uOWn7ETn|ysa;Q@T}?eLD#Z;
z%;3R?oX!g2sCTr{w9RE*R-Fbu=AM|7UhHeKDSae%nz#@eXLi7!`O;a-_d98`k2dv=
z?y}G_i-BvkS)zNIrhOMs0p38>|Bvap_<pV;l3}-dxC@$@T4XRC4a9cY2x??-YCLwv
z;xKmkc-GW$uy($u6D3_kLHxE0!evqDYJP=`aWN|oC(`d;bjN2%a0U{Q&5eYeXTACD
z=l*o=YtQPQr!L*|^wM{3*!T9Gr|tjnb8n3L(L)!W@X{^M{q2ue9lPp|zy9Uk?>+d&
zl$SpC%eQ{Zx9fiT?Aaf<{*~9R`sX+Hzw^RX4}S9X2R<_AM_+m4n!oRV_MI1=`0OX|
zdg#T}{#UO3%_VQ#x9aw%_kVKVFF!Kztrx%X+Wzm|cgf+;y?n&q9{O3~uP<J8=G$*Q
zu<Bz^pZAeFjz8iPfBoGzmc6s@53BC@<;$b)dgzj|&%XGL6}qQs7UTM>j=yWlb1y&l
zc`GY|cugTCUkd_CJ+MJW{5ra@YZj$)!-GK<minMu>ca(N+5BRIJo6E2Q}rsFrs=d;
z3RqI!JkR=7o@*ECa}l%Dad|T*Or4L^Z43G`F<2xO278Nrsd3KRL5_9EQB|%?@Gf6v
zcL7U6VTCSolX*F(12y_jBe=d{L~BpexR26Xq1YLGTgpuSw?Q67{Cj?6Bk?-mV~EzO
zFz<m#h<&i-cK^fsJ>>rr17dLi#{VzacOCDBCT`tB@-Ho|(xNJ~lb9EF(p7>EYrT%T
zYQd7QCO(p#c`uzaq$(w7?2lz~F(*Nm-XT5w^#Q94j6|H`4WM{!9Dj_xu^-5aI30Bb
zzShQfYQ$Na`uEVAGK-^B-lNw`Qxhqc;DeEN=Fwee3LG!EYDwfjxD`qYx1#L=*;EPh
z?1~|YvZTy{tkksLm0#_)=$0~7k4=hH)u?kaCoz^+IBOouebhnWt{_x{RMr|ZC?@XQ
zAy)O#m6DCS0_!u@iLK70B#DgvW80>bos-ZDU)Ge`oDOS;ys$6jFj1xyZ7)H^M4aTt
zsX<jo^oIH!^hmv|Bj3@=*FTIG44b2BffFh&xI1)55T1e8LaLd?R7SH!d~3Y!yRyCB
z5-cY2i{KmD$(sN*ghZ6IjQe8`>51`K-ywCi#-TjVYn-(sU>JL4yz`(O*1TXS7nfMz
z^VDn#PQVIXSPd985)g{DmUGJ?x8K!UVwSI4R0lYOUmG2AjbnVZfI!e-rQxfitTbGC
zCeRf78Ohp^3MxL`z3{_oGvIYyE|Pgbk{xM-?`o<HJp;bY4N=C$7N3&r$tU+Xeeo(>
zsf7A0EsV8+47yO88jJ-cHCUw6i!}Q^3+lL?sO(V&<;d457l%&}`>uonSU}>zR&P$i
z5{lH%RC!#Bze@!W6-gtE*MkF7V8K{Q$Z=6J9^e#Tf$b7D6jU6Hwz5k&$HQ<%k2lpS
zq2=-b+A`;Rs~UTWyV9!IZ4=XkZEO!1&_c*Wvex86DX~YP2`L>NN<b8Nc78b*J8&ss
z-8Ja_wRp`>$;VN{Kx`aVLh@{Zs5N;+{WYhVfD>B+B1YU^WRi*+N^mB7Elg0cz%pAU
zC_?=<gpZTGBE`puB>^>%KSpd31183dbvzr|u+ju5KuN?akCkxzdZbL1h=~<SzV0Pe
z&@C-gry=An<0R;39h&_KFu4kzX|%4Y{)o%4x&*c!i;To}20(3iS6L<u$~Z`gDK9S>
zTN5@ulf$n`-ukUMCS>wfv#3Bd*=iwLPf<fJ-2`N>u8{*9rNo#SX%BqRa2xs}Mw9SE
zx}2m*5*Tn~%8Ruqfe%Qf2TwFnYXSy^!A3Dw9>isx_i$ljE**Msj7OhH2h*(<eT7=+
z2r9~x3g;+RDB3Ex%ILrbu#~}6oEY7Y;}V-#?{~$HD~F&TS;g4U$@V}DJLh1eh$jVV
zCPsH>;)K{{n8OV@C{HXBU5RL7mZEFuk}>V6d)Tyw`9LVzVQKeZp)d4JWfA6EUJg=A
z(Ry`KQ|X5&N^rtB%}Y}CbQjfbQU$LUD~7~TtHzhX$wG>C6uJcwv@72R#(~Qrg+*#=
z&JM?}iAS)MsIu53T0{XF0!XOk#<$W)$cnWz8zEJcl^@*Y0lqid59!f#0j-T^hQ(HX
zvl=Vc`o`iJL*N241*POgVh7;^ba+RAG&B!v+AD}T3ZxhxRiP%Pza|YAUpd!K^7uNK
z$O0b;2L+YT)S!>WZHj_n2cN^<peB_euusm(;OC8_uEagNS&Oc-EsE0VE>m{wuM6WU
zjSsTFlq(*QPk5qp(cWhq(nYZi*+B^P^l9hvF{Yr9Ylxpk(==!YDiZW7|2+CUtVp_!
z6b-wmDWhArAIM;Zj7xmvrKYDtTL!HK{V1V0KOpG=iOXmvYfYb(C{uJ*7j-peM%KHc
zOef4yiiAv#{OoA5DLEOm{Z?tJO*Pp#?(SyW@1Q4vrs<kvW8c>i;7Gn*R~UuO0?HhV
z^!g6k6~3+Lgf&(D0G$kXg*=^Zu64Djd%*7DYAws|n)HosS%u=*D}JeABC%^Nf)Xq>
zjspPRX`y#9dpM_Qd{?w-^x-xPrguc~NO;o6;lS0%3P*o^?8ivRdGWAOX)7di(h@DO
zN2dxliibMah;Ne$wPG==o<bepzD&f^K#6bWbi1cV>$z@8jcx0sOr>iFj94S-GRxOx
z$llmxZ(TykhNJ1|R-Q++Wn^D`YZGw*pYPJ$AtSVAnSR=ls9LWZnH$Kh-DodsW^#W`
zAkHn7u*#gHLxc5GIU3ea5kt}#JE(h14*eO{!}&o1Qn@7Lg`v_LUC|i8uKb?q#lcs#
zVmuT?O0?8m8X9Xg$e=F6XN9(&;Su(LghR`9R1%hC3-Sow&d}?i%83>Aa1N}3o;ET%
ztEpnF)f9O11KXu2YLW_lixRopHdGv~mXp%K!(bzHpa%qrBb|8g@aTYm=ESPr4)>@x
zamiUmt)}jjz#yt%ZzbLW$U~`tf7-$gTM~-`o^;Fv)1!R5V}e?tI27Bm5vaKaIF9SQ
z)E)}@wuxmDHpDdXOmgQ*5v^I&=9m$0yoEcFlJD?IFC_LTcqe<<G>?S$E&;oSV4$Ce
z&YpuUu(T$YO6PUYQ%$ObaYY5=E1H^!j+Y0MRTQ2O?Uyfb6eHsWYVobgJx#$UdGO&N
zc6CWyl(uTj3bjSsvoQ^NteD*`R>N`WWJTU0%DZ6=g<NDyQ3a78M0O@nB<pZke#RFy
z3Tf4y;Ey9vH~SQ{jddY!ny}WMr-QCgTVeo0=o90WsP_y9ds+@S;%$^O>ax@|OxbJ7
zNEAs~o<5;LQ`Lf09$=F6>Bj-%NF~8eJ|&>@rqMMj#w&9Yqy0=GQBsOKLEtoi?ux!J
zs>Re{s5gmGVekj6czFt%o{B{XLXF1*qdZWfMZ1h^4~P-4(Nk!b6aN+o3LAi5%P(lf
zY$U-Mhr3Pp;XLpM^`Ie5{FA3o=;;;jgJcPmKA=&oMq*zhWegxSzHuqqW_wc6ibYoH
zKqvv4F7mD!0>(>)eIo}<+5=q%#LK~gerVC_=?nR0QG$N_lpGd8g@+>YprJcUn%E2;
zsg5UoSk(~ipouGE#b}T;^g+$()wI`UNZzW4lyddfZb;)Dv?qRT2?hhi`XsJRCHy4K
zBsaj2T_r{nYO!BY2Tr_t(5oSF(y@exa3H?>3+k&27-}3v>suDv+Vi9i^of$D<zt<r
z)UhW;MxF914T;-q1|^i?lYsKnulKmbDPbt}Y6~|WRb#@$UzeE@(-gi7AzDWW@RR`}
zimnRGtvWK-+*wL(FoA{gh85$ycq`hLV`x`mCpEQ3N|9Ha<~8KWReg!1qD2r7au9nj
zth}^{Q-ERe1o8xxRjZ}1&1y!LKunQ<I6<1!dxn9bp^K~W*&vbU@<fth$Cc~AhY}6I
z6_2n<0kbEIl9);Yhn!3Y<Y;n8)nZtz1*41SfN_atY#d~hNMKuJND@HHt>F$G2m~Rh
zAf>?zqMd+L!7PDCGSpD%_9kyyJ_|m68B(NGR$uKiQL(_GF6}KW31J8Yhg187bzsC<
zRpp);H8i3E=EYH7P_1B^MlpFK)}CmE@mg}wlE5YpC{vkJJp$n#UI%FfNlX9+7Y35g
z)HG3se@5EGc>)XkoVNK|Z?Vh#L>_R86Dyr=P(78G!K-S++d@;$s@3cPB;hUsLhjY!
zsI8blA6=e@$wChC`)uMTMA14e{rXUoCtP=pC4(PyG6CL`6NthkDN6|BPcXRzuWdD{
zV2lHq6wp~B*iq|aPy?cdt>|hZpJu8gv3i~W!PBHS-W_0tDxxID2T`Z1wX8f5m`+g;
z?4I9%S}=XyCGR94DWMAG-_#GIfm;Q{N>y*o#?HTk!Z7qgCTTG&Xnn%Vr&!yP(B&BD
zf|$~v^pkW*kpmc_W#a%jkSbOWH~ud(2vDeiwiO#&%b>_p$W|-5gA9%A6)w;=1)FA0
zjn{`uFeKM_t6hOHwIpy5TMM?1Ekzb^9e^lz;AI2f)6QG{62QU0B-u}*>x0`Ongn7R
z08t}!udDTlfJ%E#LE>QzZW#^HtatiSLK=?H1LVbG)k2l`L|ekM_awfKaH(pRscxCX
zt0lK;t*8V=C|@f})D4|vBk=gb@5Eh=Y^XshErZl7gk!t9iJ1tD8?b!jo}4+nDwc;D
z?xQ0;xC%xR#j0vgml&YdD=__}pdl7dh1cqyn84!4zA79wD`K}N!PwNiyOUg5tx=`s
zc~EkF`bOB<PGf_dGKmzJO49zCA@P1C!J%^rz-qIWR~+03H5fhx)TAGa%^oa8FK(;)
zI@MVGV^am&>a!&gT$@vWjeyZTBwt^dlygdn9n_kX)`Up7$;+t%LaMQ1Xj`3AP2>?8
z!jx8hCGv_@nI7uP^Gj;0#;=1c>l7|Ys8x&6g*fqZicKTx@HrXh;|TE4&;%KY7$^E6
z@FU@c)VdNzV3XiTtWJT#g5tvEL!ZTMaUC!TG<*e_?NO*Sa|$-`MGEvF7(KOQXRab5
zT!Sn>HEDiMxt>sx(2tL0;{%ZhF=%swl#f5ZNc;PNA)G~63P#`dzaNeXU6JM8>f!W}
zJdIb7MKoky;XOY*oWA&m9n>Y{6v?WUrG#hj=w<dmhvpcX6344`BE@3M<JL0NMqmJ?
z1G9q!glbM-z*@pQNhpNX9}VL`l4Dqa>2Z<;bDYfK;?5YW-oP@Q1TJl38f_9}6W=60
zHrg}_z6O1YMRgQATM{Z1%!a0um7^p^je4M#d`2T_HKbG^2A-op_#_2k%KskE1NP%~
zR_(z@c{t_s`&58hz32)$5nqzUB%MwbPLp6z4rwl7QsNFZCo}=?8jcKT5b63PzGb^L
z=Z;YkiZK)!qUWW+PFbh|7LX?l3DjXRTmuMvVMs8!<X0p#lOR<eMWX(SGO<b{$!4$D
zwi$HZLSc(9s)gf9t0$;fTV;sW1I|-QK&hPJuROEZ)WzHDa{zlQGa_Yd@RZAUJT|J|
zfdrP3(}ZO8)qOa3!O?`@3e?-<)6tkXnk>sTT&b%&AM%M8KiuT(A6vD(O<xSt478Ne
z+$-MYYW;g=qEKtfs7kma-#r+WY7k@gc#+B1`FIXxAIf#+QzDJgmzP7GmCH`$=7bTP
z`-wJfXYMQf?JkvCsrPTRDM43k4~Osbm9>)g_F)@s%*wbZ7}(7Kw<ZUdZF0qKM(nhB
z*yqw89U5#l!+O>3mDB)v;UhS5ezRIZ2IJtXbw5Z(D%6f$o&l1K**<4lL#9MobE;ua
zb7f>;jQ4%>5)Cq#H4bIzo5+Y~L^g*_>9NgT;kwMYD5}PTT`6mqgw5J`WV?Tt#2?V^
zY#Y--DvFogAu`={7i6-G&E=60X&cge6fnO__K(pg=)Kj@z4pPl$=y}%HA;DAerIH~
z04cB7Y;4k3qPT~eot0g#yFK1yy=S&-+vHR*mpM9l(lQ_I{f6~$i!0sR2Ry2);d7l~
zknT7&ZJIaQ%`~Ggxexn=sopk+TEDVEKh~JRcv7)Gb+|z(G^D^tzAe*}${gG;(&VbC
z{%yBPFf))-z3UCO`TmeOuwtsciL#$E40%D%V3Bo=GP0&8V;mEuKQ@bt3_WR)s;p{D
zUoIYWnK|oxhu?Bf?=p5j(}dUs!^GWszZ<3@>)I1U{Ud#LU4wE!io>>$B5&|$h?P{y
zuo!Tfmt6W*ByY^%KZxux9UG<VNG36-hV^*%#cNhJA6S#tJvqA%VZ-9Z2eY@RvaYyu
z&AM6B+AbP@+&8D4b>H2=j{DZ6HXqTu{Fw>kXWsMcyLUeSr`3=2o!&ch!$adIy#DIl
zg?+EyxPAE0O|!cWU4wi3`TJh2Er||2czo@O%MN<y%{}G6z4?o>8?|Oa<2w%>`=ytj
zJpZkgdzNoscl@a4Eo)QDFJ8R-BP+kOe9h19J>LChZTrgEi@x-gi+{E3?$ztsfBhT2
zU3bKmWuKZIt^D22>QTQsbj|C{L)Sd4^lqSbE<E|M7l#gg?A0Ug^=HhuV)Yg0zVf@z
zW?%VjSMiE#PI&y%YtFv>eLs6~)BAq*gUhe@+ASwNa?KleJbl`XcOE!n%&Oym@ST@W
zx%1nlb-foob<H84dwImc7rZ`t(?x%J<c5phdE$l-9dYPmpL^lZN00r>*-w;TeDR4%
z|M9@H=e>Bwv*+FMiR<S*`u*$Aod3y7&O7Qumz;aVc|HI9(X+2Q=8`K8{owZ=IP^2`
ze71VltH<vA%$GiJ|9P9**MIJrL()UdL)Ok!db|J5w=vFG`@?x>tetSg>eZ)xe5XHs
z))iZ_%kTY7c5dZsXD+;KQ>yEI&o<VMcy@LA=}mV&oa$Y3;a5*T<);svcH9xC+;ZB7
zkIVk~p7wQTE?O5}G&FkSg0tE;o_fI(W82<&Y;$2%`{Ng%HR_O6-+u9s*|(kj#6=G+
zdFsn&oq6pEkF37l-TsN|mmL40^A4VL*r+dl@$S_03qEVkUzIv^^7(5HO}~EMZ_a%6
zvzc?A>iFt~C-$!%eEr_FZ7jarp?in^`~uDD*!0Aih1%iQ-e-Qb<L>Hu>o<;kb9eX4
z$L&}*bleT?ZsD9YH;*6Dc4v0=y-V%&?Mvsa{=s37ubXt(>sRdj_|Uxzr~i3yRM(H>
zvdqoq<gW}Ja_|>EKjGo&KO9x~=qWd}|I^%ghxFca$g}y&Ixkyv`G)qDXVk8qJ#*sY
znQ_B+4%OElbjjSqp6!i4u<@`%e`vmP@VJp*9`k_-Cn#NGZWB5GzH5$K(XsK&&D-56
zyT9&Ee|`0)G_w=oyd7K^agEQcI@pgtqTh_0e3Q5tJDP6BuI`&xH8!q2{0irWR&UP?
zj>t@$kjl7>Ie6(%>X38iwP!|;`9P-gl$5m1-RO_GFdWXzw(FyI8`_h)+R7J>EKFKC
z$^<=`&cWJEonKnp(HU+CJ9E7~U1uGV>KZ!u(!(<!H)(TzA<oRG^hOIR=Cc!wDZJ48
zw`ZuAkLtdn-yRQV-S>CZAN}UY;o3LvJ1gAx^}#dR_iTNz^1WLxtNeN7!1o{PUvSNH
zGQV);@Xxn57ap@#GWS&W7Ynt^2CfVj-}K9CI=7y3)smqF7hSb%`<oBb)7#zq^L0y)
zJo2%w5!)YIHhK5xz3qi-o=NZe#noN=t~|T<tn|tETpk}D{pQ5(=*7nxBYt!Bt&`7s
zY_<=6dCqX^$uHl3+u$kC_Fqcdnea68!lR|wPx}4vo=HE-^v<$d!u&@Ym#r!1?prf)
z<iHxc$*tMucduzg^V`08%0IOQi$~PP+U{^5D%2vgAe`kFgtlDRTv@hYY_q?)<|Ub%
z9(IK_*?C8{xwGef&7OVF!9n<BJagpFS-;!8rogtTF!;@a`N7!>2BSIk&Eb;z!9M8A
z4hMY~tdBM>zbCg*7Ezuro(XNm_QjLSY)2iougooFZkaoT-fUJS$Ey5*uVyyxG1J}8
zGqYICcw+;TA8VHuqnUe)^`UZbREJAVx~bH&JX%!$`13PNJTHuQ6h$VM>B+c((Zij~
zzqh0~H{NTCCgvltrIB{y7+K`!76;9XeIGt~d9>xo*(UU|C^QSB=l5hf2Aj8aly+T}
zc8Aoh{l$2`=W@Yf_RNIkJ@f&M(>+g@e~HfH&>p%XI?|{H41CN&&rJ`sU@Tzu#w8;=
zw$p|#0?q+~|BToyE<w{ktn;6AQDP_F(T#LQ|Ag|kMS3y=#*|ae1QXpv8T6(&mGv;-
zgQ7JyDvOLjF9y!BjmNb*K_S6S>B?Ffh#;5(T5u(OV0@%g_dK1-EJM}?VqE;ysFX|!
zZWR~N(0gF%-ML+!E?~CPxq?J~1O1PF;x_3wv8SNM*^yo=2#*Ygp2lZ8?eR>}xEr*W
zR_k++#C?m-b;V=J2}@hFdE<fX0wycdC2X=PU9f@id1Jlqy5iEsfHjKB!anPJC+Y-4
z(*&fM?0Gu;UMv<&|F^09A6}v9Vl9mgz|C4^DR?Cw$DDkZV?9m$Kq&th1(`Byz0+LI
z9y8n*FXO7%oOH>Odas^4bW7ZDb6I4Vs_B$|-P3f}rX+>&sqs<nj#utH<L#|Cy#2?0
z$vscw@A$7fN9}(3hQGYM|M+)~c<aS0?l|v_M_zvAhW&qh{rFX{zxCn`fBXBL>)v_!
zxwkIdfBdSS{`CWw-0;UcUwi0{{cpeX+VPj%@rUmm|J?7cdGVoD&+UKttyfm<`>&6j
z{q!HNS+f5f?u2@J)g}A>aLZ@j`t5UPp0SVpQu|*%<BmV<f8YMMpZoGVuRXNtXK#J(
zBUgWA|N9?${kavZz<v1BuN;5F{&zkLlahOp_Maqj=iguJpqoiyWkP8f7rogjPS%B`
zf%eqe54N{Qjdm_&>M_|xsnnQ_sS|emkSi;u)!O1&Y3X(CL49?5PvyH4Os;&08E;I_
znt}^T<q2|I{*GW?-%b66JtkAwok|VoN86mVi!a<86!uhu;piR{&Ddz#_L!bpVTZds
z9<WnwuY`LyN~i;$CtWc;D_`uAjRobb?$KJwBuTo94#|7w|E;hC|6Vw@L_GeN&;N(R
zwfv+1Bl!PLf_@*yYEM#MSPq!P=7rnUhIDVvgN>HIb3vO4xmuwAU}N!*=U2s0foxkF
z_m6sjqR}>=ZOV~N%LNFocTl=rhmB2GWiW?e^~wUN4D4dF<_Iz6Tz2>Nrrpj59<5s)
z8E(p`1kJulE}*`z6q8ISI7w!#qEt7-5Lw`}!)<Q82&zfUtgsYStqa1AM$rb|lHsxW
z@qz2{k#9rQSPFog?F@v@X45jxI(X&Pw#bmBHFh7&I!NB(0_fHoN$d{6BdjpkE*|IU
zewDMRU}rND*5`Lf72rxZ*-JVYiOy)wF{Z<p__$b_k@cX=H5nP@Go~){N-{;OZ?3YM
zC?z%=R8wD`(qQ`0s<MLHeI}!PH4w=0yO3lH_-4hrTGG?iJ(7&?&4%h$7uJ9jDaVcO
zoR?JSgf+34mx!~zze^-1b#)Y%bMei#&|~ikQ;bSLMfO9h#}mE0JCj7Qp|#4M(STAQ
ztkvQJ;4X*92(@XvK-uEws1RAl6i+BkteAr|3)Mja!9OsW>C7HR`IES>E)h5ntW_MI
z%cgYdRCdf|z6`V7gis+(iaRTL@1#Vwji426$qNHJ){dvRNc<o&W+B-zV<3THSY|zi
z=MRT_1?Ah#%RpxajN=sx+LPP39dOlNqf;(Mf};@+K>Fft#8YRJ%WP(Fth_P=vcw`<
zCLwo_(U9lcAzji_w$>H)NKo<_PizLO)~DoF9j+}EC#I?y7i>Bio$5vKaYe&(Sjo%M
zq#;wG0hMLLgqKE85%E4UoBNS^rc10FXpmRsjLM^xJp6C>q~vQk2EY6%IzvVanh<*^
z)I$?FQs%Q?(mCu^=8o(5_S@BDfo4}yX^rV|EYV3nmg~*<kVu%UbTBTr;A+s`z_)MB
z7MeCW-#52Jwq{KvgHCKEi*M_G9DA@=ZX^^tnFJ1UBIm<W&8<$h2^lE!Q^GoR5*LBB
zLV|Hg<`TLaqL|DK0>VKgUEU9u77<LIM`v8OBW^?1gNRKzws-z8Kq;9Qm-{6b`|PPo
zuBH9<ls}&&M0Y5{5Jlp1=%XGcik+o2bCDy3j((On3{hl=U+)HTWFy}Z?(sO?49PVu
zE8p1J{UjTskoHaQj&e=u8BS(g4b493DM+ct*Qcb@VTHCbg-52v`t2X5z77TO2^TYC
zZWe+=NoyIhA(8qADaHwibWhWB+}(zDw>(T(hl((Z)m0?JOEDyMEu;nTWT3J)@zhBr
zk62YHF{?hzFnE1agW@J|s(ijC5dsxu*wO_Bzzp*l+)#zvDqcu}t|UO0)sfK|>QFoh
zslJKYV{s)84BlFnAtP$+-BvtGXb9=V;_+7FqSXKq)pMt2;?eVdv{EcJ#@!??lHV4D
zGqr~_LW6<a)TCGE#ks`IqbtVR#aV7PiGf(0xRedAwxYV+m06Qc!z%1Ru;8nu5U^X+
z8ROAq0aX+Ra=mjh!%>bW(+v!i$N$141tJT1P+O9~#l6`mQ{JWdAvXDvRJ=7E)Buwv
zyz_yDL(O<?w?ULjp@n=fAQo(mk*c>xny@0Cvr?uP{RKS%?E!?t=pE*eh76#${Br1K
z(p)#r1v}U>B;tHq5W4Dm2+1~=yWa9%1Yg2@R&zrZ`w?0(MOl6@a-6qJY7Z6R2-^W-
z>zukPECiooy$hM{$Va&zYH8oD+}e)5u+PU(V))>0Bt5&POF8OsVtW0qrmiVy`vL(H
zNUdo@Zo*dn7CJJAAZ|f}+U7d^P+d|*I^<SDZ_UFWSN(uNM`pQGtoXxxCa$)05!;o*
zQoJ<U?p3mCde77Kr;~;^*7amYlO-#Cec$c!ldTL_$%6cI=llkx290skicN8?k`FBH
z5`vSVmOKcI&pBV@OyWo`rTQqCBXQSS(kBIfln>CEE}+?V><~)L_Z3)Y&|l4s%Z3RF
zH#T+Y7|kwOSr9;1Q*EiPW~IS$U(`|RD<zZ8@W2-ho8HK|2dC|EUF<pykx2B`*yLG`
zr^ynxCwz4x^hSZr43_OC-;jROANubiL8RN+yA64Wmn~miO?z?BkIv}tpml?UxEyu+
zgBhNboj2&5UgMgbH;(!iP|@PZWZ7@zD0x;k>6`GD^!g#5lpm2tf`Py+BvH|w+GV(}
zuw{}KpBP!qeu>bDSp1d$J^af2fEPDelW!S~hx8Dv+O*SIn|LU#9^27Qd_4{;i6>2+
z%VHa_p;t_8*fDj4Qi?6qv29^iw1L7}et4<x@IX&wtOqZ3J_L;m4c-B<RR^{VfL?7p
z0D*Fg0N@TZ)0C|~;dkKh!HUtO65vktu>3S!-^v#ZTPucOz*m#NNOpLO<Z3{@u5}Xl
z5QUQft4ePfXFa;pD=XQ|mIxTlKuA+p1tAmk$r=g)Ns28V<ETP8lN!uB)^KT{BKAr4
z`suibzSVky*2$&dv7Q_v-<m>@MCsjt4o++?48<o2xR@{t(TN921o;GnSdHY>pgnhy
zCm1h&XiU1ZSmOY7<FG(iT=t8Ce)LwSv=$1$hk>J5T&SFM*e$C%#w-S#IOn3aO2S-%
zc4x_6i$=mQR{0t#0tuVyK_Z%ZpX(Jga5W)NeZlQC2sNQa?zGxUuT?#fgbr&sjfOt+
zSl}2@)KEUo^R|>J(B3C#@Ssg22q{QnngD;LgN<Vfu2y=GJjH9T&{9Lykx;);ZD2^#
zS~)}!L&0J!fBMgcF@rN_brDiB;IY&JnqC;I7_5d{Xh}>^#m8a=))cXpsG!|R-a_p`
zCJF09iSqoLNcTL=pxV-PRDAg9-1Py&oWJJVDr}^|VgG>;7rHR9T7sy}!1)AgAowRi
zo{*BlC_1ldBed#lnFJ)(4>o9W+CkJ<L0~nwsSh=JM~Kzf7+X=QlQLFI!XDgCt**tj
zR*88_VoB}PAmUTilNh14X|}B87f?SefuV7@w5s8X>|k2`TCPM7^<!tOVM3L5)c+vF
zz)GzE{Ar0<2S|`H{pmn?`Il>PV#tpg(n(A|4Q$FZ)J}G(<V@Xo6(s{!s5$_bXqG0=
zf<i*M($X|e0!OUQ`nzb+cU~~~M!jlFsYt>%2g|#aM~$RYM5_xbkR)qm;z6V?vMsUG
zv==AY)$j8<L05Q*xOInwEmj&*ufPhg!~`Kbfs7@ZQVb^G4Iz=?7YH%*AA{Qwol1n;
zsUmRdjq#2Ok8h8IyF^i=TLLkjpHo1!BtCZRZmgKVg3<dh3YzLv)0m2vngoebmPARs
zG{nW;DO+pC%QEWE0cc6Wygqwf$g{_&1UXA#h?XnmoPhGM1cN?+^{mJRT<Dm%m3L}1
zJ%{G^YEK@ZQj}6AtS#Z0YF4#aLjh<IENS62jGL8-Fe|H1O9u5#QnnM9(xOI{6fs+f
z1L~`S#yUi?Nw_`&3jn<+b}y@M0VKT4U_uOqCI7?dTH3pYK2Ktem6zXs3A;A$F-D1T
zxas*a0urw6@wl{_wv3jzqE(?&5hZPzDW-z0m#GF`j)#X14GC-N;yh-HPo)+Kt+bQs
zthm&ZkJBr7HbJhnG`YyadhuQZp)bq;pnTU>vZPik-Vw{IJux_v)Dxj=r3pm^Xhd|?
z&>*RIldeYM_B>6%ql6l<@y1Ynlj@`vrHIkI0HEopVQk^|sGPuV<iFhVY+WFf@bZll
z@mi+d+B7O^HOeTLZ`l)HsDSQ<_v)9FliJYkY7+A4Ed$YlQ_rS8FsKd3D+$pzvANE>
z#T%>`?FVVxCQr2`2|@|Y1|A1U3TjD+*yQDSauh^UV>f=u1DhD9*gdfvPRp-llDh?K
zw&l>5=GE~|%pgzCZ#Z$e*3%|;ahb#g3BHA`u7L&8NK9lkSu1up@G6%l-*_NEU#gix
z-a+E$4)Dq+u7nARtrcong;mPcBn4g5+*2`qOJ=zxG70kp#|f=AaRWu={eSp+7eJ}1
z>hXV_bN3AAUM_I%b<nG!?imIg5cQ%&SZI6Z4tPb(!LT%61EQi~qFK>H-E$dWM6waB
z=<$t_uqe&=nwh^|3=frjBx%3QUZUAo>uYH*vrPGY)*1Nr{r>)seeayJ_u6Z(z4qE`
zKhHY*;L=X{=m@#YfNR<s8r2!T3y^{!1C0lp_HWn~*M>umvFC1;B>$|GlmrdeXbK=S
zQymCYc@mB^i32P{{PZ0Q9EJog@gQ~5b^I(QY9JE`Br9&DgP{G>V8<IOy`1{-B`zdG
zNZL;5)0;KMfn~VBR=?h$5BRH(<5R7No<a)rW*sHcXzf(M?=%>qy(8$gV96{bOUbec
z9l%=YG?B!2;9?P1WUeNQ&baJ+G7bTyyqMQJxS)Y5LGfO@<b;|d1P;#FgoP%JG*Lv2
z?gGrs@^i_xGqF-3IBh;D*4j)li5}#eqV)Lc#U-Sz!-wdSgvtgltSST0N^&G7VNO6)
z^Ny8an{;|;RJA}%M@2+Riq?P#Dxfa;=Gy(sHED7Ts<z;g)hxm6;A9g-)m@-g5)Knd
zCjcTD8X3IMN!YO+5dj@cB-&Bwww!GVc0{A(%B~}Dh0vFIh3N$fT=0>VI#cK3lj;jR
zUWfAgPMnSz<i~)g_Y}Z{yw1Q9Jg;DN(CnP4hTlRmNxq8!_~1eg-nDnv%!~YV+$2p`
zj%xrkBwKKk`c9(6BYR{_0%wJ(?S6OVJJiE$sFB>EfduQFNY&SlbAG=k>v-7KWdBQ4
znc#%Gx`ZCYHIxWZMq6^ycS$sD5?$IKV@yo}K@djePW|g>!oNBu>Dp5`8naCR1boM%
zV?yF1G5;>0EC<4_BMM}z<7*-lPBv&_%cvpM)H-?L?E2(}1~Ovdl6VLONvNlzKd{gl
z$&#Y%&qg~&O^{sK)X+dDJ>%q31d=q<4phnQP)R2`tadojfAG`Uiyxuxf=k5BS!pTk
z!0wzQrYF5eRwnA^(k~3MDJK^c*YJq1+ZXPWOcS}hllKlqJ|S+C2?r$KUtz7JJwwg8
zo(aafcl3@yJS%IpHa$qRBtIYrF+c0|7VD`2$H~C!cJ%m4QSPrIw`j5D-OT!c3cZ|4
z$63at;9wIyg89qD9kl4Bc8?pSW$Chc$46|eacufE>U?x<39USK>8c!r9Zf2na62O8
zsX-(+M{#ouJG7RU@7Pg=zqsXL()ChMiI-<mekAG%c1)FO>^9kWQm-_+(9rj)lylC3
z%I4*cw6M>mbv}5Q+iZGV`(hOwB<4==rATFY=XX)Op`y*mR&b3qO{rUHLq#aNDWubL
z@cORu0)2exC9@$q7*DV#SUMtdPddIChV#gK4Eyd8+h*(Irm^U5mF})#hVxN3>GOU|
zElM%pE1R_$+FGd?x?FxNdb8rNfi}H9Q|00Otx_9tM;Mf;F)T%Y!`jf~uvM!~)$`+;
z=mp)5k@6>HgAb*+cwMw7XKhr@@Hm+f$oH%pSe~Ec&CN2wnV>tRZP(d?k+X>xS>w8U
zN)*Y}DzP<ET)n-QmOjn&GZP7H*!B{-FhtPdFq@5m%ejnL<LyB~NJ;6Y<^*x*rrH_2
z^v9@wYDruA98#hx*7XGQQ!igCG@4A2SR0KFhX*n<PMv87PWRO{$vIC0@wDODnc1g*
zNru*hatr4?9WmyJ*_qzSt(_|;hmWo78Mw(zm~e9M1I<St&TZZKa8LB~*xm^bjJr4U
z%=R;DzuoSS_<GtzYsOvI+`4G})@QOSS3fvzm3(5{1sk5L9@hLzHB}!q%FCK@hYkF+
zdhWo>)%zd+@+dKDM)gd1wK{I#>gp+e<)|IujiU}V|EwN9;e{o4qbyzhJG<h6e=Isl
zHeYh^k0(C%+(n1&+d8rTG_@f*`SJf;^Rt6a+xD}e(Vv)q)?2O}yX58@FFE|leJc)s
z^3lt0e(C)eyz`4I$F6x|+XbK8_s9_k_q~48)tg4$HFnK6?(JRk*!<ERA2@8mYw4c8
zdp~OBi$h<S`0XQa`p{1<yZ$p@KI^*XC$9W{-)kQ#UiIYSuSZXx`}O$Aqrbf7!MANZ
z=_{8W*SGIu$Hgy=y6mjKedq&=*35bRlzrFloBP_OUpW0M*T)|aY4-j0yhF}>c;bcG
z2QNJDkQ0VBxB5T2*Y}TBey<MZKJ?l4(ck$(^XN6vr%t%`eTUq9)3jebxh?;bCqF*f
zJ@B2g<;G&qc~AfI9lv^d)%*T>!(Z2Czd!D-Ijg^L?`f+ao<DHMAK%));}U!37vGgW
zchhm7UB2naJJZi!_N&TGQ!e<?rZbKxJ^QYsHk@+Q#;cyZ{&QD7Ik)z~S1SK&>>Z;<
zFaM82Mql;Hl5v9{>VLO<`Qo4FUwiv6j(Tm>cTfJxN0+|9UPblcS>K%gpYDA3<&U;X
z_kL$_QC~XjeN}CXZhF@KHGHPo-9LEi)))NW9tw9<uaa8dm;o7o?L%LBb9=(MH@|uA
zSqG&`@A~v#ORJZp#-8@;!Ax<doLxTd@L}`G;*!!WXFhVy1BLtiC6$3sUU}K8m6zhm
zIeYB7Jqtc&!naL4=B!T*-0<#OE~@Q#(>p&dS1!7*eB-$Tmwj{6nCc-%j%gh-|Ejsa
zo%O^OzjcpHJMH`z^KV)#viskaub1eBrspmT&fFRQ`<9_sZhWEk%DuUf-488%vTydt
zS#&Fb%))%79{$_<!Q5Hy{!%dfz2VZ$W6nNgXFU955DeVfH@&oWePhEJJ5D-m-mh)c
zyl8r+f1;T-+E?<$^<la1ttY(Le~I~K*WEL}w_ua}G?;wi^8Rdb%Au<cpR(XnQTOIU
z&imRCZ$0A==WjW2_xUy1Fr{z8EHmkpN1tPGF0RThn3O&IkG;{PO>ukoJ@Kxsw9a$Y
zu4seo_|<(f_t?w@54<}w@W9P+YUq(nJXC$_)m`WGSGz7O-q`cdoX?J}&W?U@P9|#1
zq04`S_m}tD88SW`l%mvr5sLipODmPyk?*P8@YvXY?>^OR4VIYlMGL~^U-Sdh*FBgS
zJnz{%E8}nOE!BUJ-gMiICfE1UJ(9m5BX@mbO5x*kQiJC&sa4EX-SVmKyK8a|ytS0K
zw_Fc@wFl16L<i5vl-?C@u3-mS8~Maxg|7Dv_H+$wsLegJ*xhqO&wD03yJ_BeM{wTJ
zDbkk;!libvU1pne26~w4oY!@=G^VbQfrAZk>7a1~BZRfu6Uq6!KwR(YiRv$YwP*Z~
zd&Soe?s|4@#%;Od9%tS)A<m>n1*?Lr+&cd&6*HLWI&+h>>(Rm;*u6i+a<}iS{DxcV
zY5zq1SyyYk9G@ar$!dRg?g_U^hWOnqm)ME+?EK>C`T0A8KP~xndHLRRU3|%Da{26`
z`tlh=^+9|7_JQiDjY;<0^7rhJyj(2?ebu7N6^gybXZva|=dwjUnRC??v!MG#8@RvP
ztjT<LsC!ZVs#(*`#fJ`V%AVTSdZ%03x~dYlrl)Vcv$#}l3zphe)-Bw!sOyk;r-*Au
zMYVZ);w2Uzk248t%i_ik$u)=Quy@M(aJy_0SI<dKrg~0J@ux~_+OQ0|E;-qB``Dcx
zFI!63_Q*`r#}mkNoV91WLF+L6ExJS9qIglkbx$XJwLO(@(R_G%L8^8+UHtU?keuCE
zB!wJdTOF8g7s)q97CHL&sL3{6JjuH1`l{{qRdy2i@h;(V>ffl%(;X`rwk4>TP`2<y
zz981`VbrQJ^VGTLVa%GAfU!ghgtNrwWe>Z-=yu&Pnr0Y!7mY}(4DQ_-X&fH%(Ky7=
zBK%WEoyp8InE??Jc$NHw&?ob-vgLfk$k+u$7;#Plj4~L<jt-i-Hz>yorUZOvh!!vO
zt{tc6JiVc@|F^5}sspkIz{p4o#bR?lQ%tu6DPtW5D6{MG4A0~^iJ~ajs*N4UO`$C1
z)CQ)A0~O~70;Wwo?U_)Z65(otFEa;MH%)Dx9&t?Qdu;lWpa1Q+Kb<l2s5g$<_}csa
z{Mfz^zP9gMkDu|axBcp<jr*?q#=d<g|NPQ#t-t=YfB(Z<wh?~p`k4>E{rWeq|JJrQ
zzWnsQ4}SW>>;LxDQE$_a)?N9QeXsxR8y9Z-+oR8)u<hcXKXK)@eXn19%S+q-cIvi6
zUi;0q_h0|5r>~#%xqV0e`TTu-uU-5%!aunFLmOXu`)g-xJ7nMO8$a;IpC7&M?Hivz
z^3NCUJLk2xY<vIf-}u3GUw-PPBOkiRA<jy-+7KPiime=&u4*kk#(l9rC?6G%`bn2`
zRaS<nGk0$4nmbev)}O$0=DTw#dHkT@h@m*h@kqDI2tDJJp5RmOoF87?HLttc#nZB(
zOz@VW{@#4>#o+cn-*snkolGv?D3fkm6HE<iqox#_VSdgIk*sH0vPzyU-jiFh=w8{9
zy(PG-Z=`GTg0?JO^s?M`RZTV(eQ-Nm{x+M)H@PUkKiyy3{$F6#f&UNJS!{`T;yV@9
zQ3KZjby6LO=!Ep@{^k8|h`RNcQ2JNw|3Cz6J5jN$G%i(88<W#F19E{i2%K{sEYsR<
zaefeX)|FYrA&G`Gj;#>(z&%?S<JkaUYFNwpM^Y_}Z|4Z_SuTVO2W(B$8)fNZ#Tqgn
zZ4G)fQha&Tt(yC&MYITC;a#qpXFXUMiTx&-SeANZL$^RkLEG)^t%X)KnuJW5+YysL
zbb!5%$j~r1oe8gw52-aJoWgg<9~aXO+N^Iv@AmdE&CImLr!nK#hKfvfFZ9;4n#5j;
zDLmgL$guQ+B0F3`IA<)BjL%KSD3#2D#ZYE8%;ra7eiY|91Qk(u<NNJi=j^ahZ26$d
zZOsYzp=;}>vQyp^EH#)Bw}tt6j@LU3K3w3TS7D{NnH>^l#ikr094AkX=v0{Uc&6xs
z(&!86*`{MYFo{G-ee1`)@K{H}B>>4`j}lDcfdwwKAsaEq*YfmHBAmD2xq%q-Hn63x
zD7)oP5RETM&*VO%J3t-|WS|dQCc|1Ln>@)OBQH4~_!}o`kQ?|4^^gZK6t8~Y@AqWk
zrndxwZt`bC7a|Quf8&7!l#P-SrF9j!?5Scm40>u6^OmgDid&@^H?!v!K}gXX0iz>a
z3T1~g@eP&h69u9m$m-u}_OKS1xaq|?VyH*UE<n6Vw~d@dcnP*C@`|rlLs#rJ=r3_f
zQSrrr5)Xt*jsFIFOo=ZbJ#%{HIP08b`ydE*mu%YZ%i#lhZnG1}fM6{aGoAfV1t}Vj
z1&N_|Rhk|zj^hu#-fk0?aT1)ZR#m&npC|5+_50Bx>v+9|L{^IiuOtrY%2O|`A{mdw
zIFF9PuLDbkK!mepiR%g_+-6fL-&Su<hGl`;iqz(SUk~#n0#0@)H+AQrPvW@G$>b5r
z8aNwRvSd-seqfLz3Jec=qX(N10~O@etL-ena@H%4HP}LhqLDgTOP<3bAb?Aowq7-b
z#UsaOqzpPq%#YO4ml0<KZdj+fMm*m%sWTH+X<FI>>g|F!k(^XXi7B};c?9AIv+cA=
zM(cPHxp)sBQqM*MZr&u~!%xxHJ!vXV^Nizp5J{;>C@(TwN7E)SEkGC?Pe1<0Gh=Hd
zU#oXm^tVEiI0>w`&a!I8>VdSrD{f)h;<jta(%qg(S=%XF$&(Q1`$%Q{crUQkBp>ku
z{_I{bV9wGDL|v8+fZYHf<ZMHS5UcnU(k`{oA-F1WR2Hm~xAWF`;q4;ql!K6Z3R^;q
z=B|4_=;m9iUWFM1Hqk+1Wjult{*&JzcB9g6!ZcFZ>&Yk7ic9tSwq+{U&{Wv7q{&E`
z^irCtHHDr80n8*L9L3_`Y8xt)7cydlusd!<OwH`DbfY!OAkG7JW!>~HET`A870J^)
zqP8bXs=rOma-YayMI|HJW@E~3Vwvx;8dAP&uBH<arD3T%q=8bCre~I{vgnlNB8iM=
z?!rera{5fW#ko};zl;ujA4=&4W6W-B+;EFXKzbWH`*P57(hpv(#jAT}kabXR)MeV}
zmX3(g6BJC+ko1BAbLNt`N*q_~&OxC79haAht>pQ?P``xR9H#0Vg$v3=2O@RbwAi@{
zI&AzTJ}OnW+O(?_wjP)1x4pD_IC^N%^`pmVNjTDU!6zxlaPXJhAZ;#fDrk3pU9Wr_
zk{q)w)pUQb+Cw}aIomwe&7i+8=CxnJLh9DoFAa>PU+~&~O3Wv34%3^Zyfj80t?dH{
zmo<=eroCiU)SMI2q2^4`?(27Um;4pp!d#mHBNI9|WuV}7fa=XtJg+uS>>(FDR%cO9
zYN<nx*7_E8W}KTAw{9YSud6zlHsE`B5pVg?bSnp0w`<GcE!lxhy@`>9O-EzrHW#jh
zF6y+Wd{vtvN&MR8lB^BSEUg!ra>brj(6Hr8Dn=jZxiCxoKvmK{<(&){-+F`bwL_*$
z2nRP*F;xruw$2k9`cX(cEO4X%MWjA1qrrLaEfwK-^VV-@#|u~8jDBFPL8}f;dThy;
z=o9K#RjsthysO5Ffp#UPomvp~&6*Wjm*+T;*qws7t=SMrYrEt_CnY;j!RCjldx6yh
z+Q85ko5VKfJmlogEW?4Q+(@SvuNU#m9O%kWE>nfW5gST?DGT<mz96k@#3_yq0&n#3
z-^fgYWi%dHQIjw(VVn50&bLT140wxFlT;D+S}-hmOX2ky&M-O*UD7~OFNxEjVK<ZF
zcnM7sW0DxNJfH}GK!CzXk{yA>!Z6WxIzSJAL(Doi%TS=WA{FhMxObk5)hTjG99Mn9
zr?rbi><MbeFU3^e!DL|3fsPBgaWarfiv$Mb5cyTYD)2yUb3XQcD7LZ`FF<|_jRg4#
zQwf!iwo-Lmbq3I%OIRy_9{1*>QW8bQ2Fb(emL(6T>50#fwS#2hbXmv0o-A2s95BS$
z;gl2^<(+hqHwn-LJf^J)c=DGxXQbUgPhF<Xu4X80pg{_*=+p7K*fL&lanVrnF0*I9
zR5KTz^(lhrDZn`6#U6wapA8%+DiX)6#XDD#AV(M%i=!K+al?NTPDT;56j?df2UwOw
z`fv!5tK9w<dkG<5Jc67P-vY~&ln9Q*Dua$gI0A+<Z4IM12|(py2^JKn@wkt7Td#Ku
z5t^S<(O8Y5oh2Skq|FG79`%a&Y{F8Nxo?}iEdww>%`stwyikOI{)MO#3Ar)KHJELL
zUik!3qot`4fd}TD!rB!s(9k3rf50WA6E@f?&@}sJ9?Ye*15}f7k(%-J=$b*|vMOwb
z?xGT71ca!fI?dnX={T%T*CpRu+xaShd<W>r!ius*TBeMA3)ZRETI_mFKv-dP<jKRZ
zKmi9x@@&dzFv8%5FFsJ$1gtkyspjtMTu7Xhg)a;BN)3P(){!!ZM}})w>cb=vCnH`F
zmF=eDkUFmyRR)Wm2lNrR&X^mD4=b`8(g`;j;q*c{nN2W*2(^J*Ap9)qnm7~<zTzs7
zF4tiTxa%U*8Bw+$aG2Ht84j#ep7!gJ6K8>H{po-ixHzjSOR?1EY2K~GNdWh{7rWmt
zNzGsvjcPn%$&+jfomfYqaGvzHvQ&uann;W@(&eLx>f?DuS?@UQGrW2Npz2tIF4s}n
zyU)ACTEr&QrIhdsPhN&Az{EL$N&Q!sYC4;EC`+|LUY%56L4~o3I_aPq$@&Tc2f=vd
z8;Xt#?H_r71p%jJC!;t>s8}zf^^xfyK<5%29Y>_f8U%H!6MADwWsIw6-6TP&tW>X3
zOU}#r)W6}OJwZp6sFjdUV$p4tX`nQ~!C949l~7`X3VrZAa0(#pIBMg?S)TwIiw10G
z=x{tz0p_jNr%{|qMa$J|XG(2wtZZ5PBu{?>2C@o>jl5SR^g65cqv)N)j(n9$;PPBq
zbirtqv0MW_S@RW`<7khj;V7`&cS9WM#E^Gf8CpG1N$t@qWtZ|tlq4|`AHENga*GRO
zcL3NClZZ&9g?GRuB=9M>A<@mi!<)%ZPhha`)DsuDI7q5f+mZlzNr*yQVL`1@QwFVC
zK`>TnMpgmv;J8?3(8`cAN{6m!P=Wf-6vE*r(?Y$ebI)d7qf&yBb_Nj2M=YAGjJe@>
zae$0;#<#f+K;>8o0}JPtwJ}RtG{^-|Br2IyLlST6M`5>9j^HBMob2b$(3S#Gm6LZL
z6HZOSG+{Ab<Y?}yr?!=N^g=dSy|AK@dXLq#bWKc0Oic_b;5CZb6Q3cDohOp;D3!V7
zIp(%kV@2D%S5HTlAN#oaU<jbkQAm|7xiHXKY`0aUh6ymd;#hE6AK(dzt42jKQuU!9
zz^s&9B;~o#oS4*bqqr><27el971j|>&KXNIPjR6gkpVek!=+5<2qg3^Rxdb>WZFnN
zg#l6nGNSMW)_D3;;-zA_xWIE|2tl`mo|ZbHg2`1+aN%x~$x!lnObbqvYL<L%KUXfP
z1BI&u=sy#94L=+tM=%Mrs3NO4;+B$cT>@J;G~rP7^5I7{rb92uuiOIB3<Hc2u?twZ
zDmmvoAf%>>N@^#Bxg!%s2_2*1L7R?^io|#Z$f_frITc!?K}Gf!I(@{$uNSKq%}4)v
zm`<=94C{9e6(5i)mp3PRyg2WY+uWq<vpxwV7n^XBQHV=K$VOQ_NNSP<7AR!$)IVhj
zU8g_M6ei$QY$7Q@GxYIX@I|{KsAQc1-zG|i1tjU233-t=k%{Bryud2gt`knqA9~;v
z0?K7X52R6pK5OydLJ2H4oYzZQTZ6hlFQF)U-6}Ckt|=YInv@BOao~77RcoF0mx<$M
zwFrqCLIVmnXe!{!6t63Hy2&J9trDgOaE_~Hsntb317(e8d8_R55G`@TP>w5j6)(v~
z!KC(4Rej0@jo1Zrah7ySJJsf{&mjgwJj1~Tu9{VnZ$DH#Dxx_m#3jXb&T25NOVdH(
zaWK%3pb801DogTOE={W-nivdq&UrfbDxh(wqKXl0Cv}o2f<0|rT?qxy$(!oavM94%
zeprGWC?cS7O$h7V`owQ00(Ah`meP(ub3oy_b&qHUN-nJ_X_(r>C@x-0`-Bt$oE|UR
zLl?}b5!IdPlO!hu2By|J;}f`Kr}8LL5f-u@Kj~ZK0T#HPUK}KsWQne3ONwFn(|(6#
zyw;!#&rSdY0Fl6JvEW#tDG5E`Jiifs38A1$zUmSiyr1a26i23-Kzn6%$`{UAE{Sk0
zARjvIp#r)wYG0Ygxult{Rj;)YMEYe^%K+{H=<jT9C}{y`pqaoJuBMkj^O@%Gd7JQt
zengEj;SQ2|<RNyN5>K4ho24fg&#rc|O9=%Orm1ksW{0(aWiC1>$F|0fM~gTWZI!#0
zsv<295<a@tMw{?{XKQ&KcZq|Y!_pq^rn6kLq)l84Ixc&Fv49BX7`lK$`#czgZB!@u
z{y;gDy_-gA#I)5;=j)v3VzDXm!&}DZGNXz#m1(ZZ1|XghFVBT>cAz>nZKdUYB=ftL
zv$4@zuyPC5q3tT;xWo(2W8Wi=X2Ui64P`i}M(hblx+#s?ibi=-!G50C=&h;Pb%XB+
z>Q~qxf94yv$-#|8@2YQF+~=YRQ)V5yyKPK~X;o$rBi^lda->sSkLsL%f3x@*!F`!V
z9By(q?8>*Uv7yb1$utLUen4heEh2?T$<|7Hug~;0E3=+GEZ{7pczV%nci9)N@~8#N
z1{YJQZJE(0*^ImB&B&;f_wt(ou{NSCh69k6CTCX{+G$reE5;Y5ms7hI#Mx#XWfzrQ
z9QH5G2h(}CvZNMCuG+3mbLGI1`~51*$LI2P?z+I<`Qsims~E^GmSx9>(I#uOI;wn8
zFB3*Q^NHr&?9%z74YN(>hhv``yH5JDSzFArClVSfJI2t)SMvz<1m~aSq(sKN-W%MO
z$lmPoGPvb|9a|`LDUY#fJ948$-nAiGC{nE~$QqxnhnyzDs{px3#+0g=N_A^EBEy;K
z>xxe1-P1x7T&Z0}mznILB>e-em&1X;`2Uc_v&3gs+P(VLZ5ZtRQCy5|i{VFh+#?h6
zz2)q`S1b$Xz{avX_8+N46GB_dp-H@K9Bi_COqHGIKJ61T{c+ok7bDeWg@R0$Zgi0F
zec}w#_R<}ggG!akF`-?@6pE>*Gjm*@>#}B3Gg6zIC$Jy0m1mHu4DWbo=Ndcv?|&~$
zdv!&7$Ja+a`|!?{g*Wb8G3~q4Ry^BYx#oAzoU$XjV8ZON8%~=2><c?bo_*nu?P%O}
zC-;8#h}oN7sO{YQ>aNR%Pd{=(bohiLo_+4N_R?2hsqP;4i6eXO8h6AC|9mEY*@{1{
z&~u#XW6wWg>8meSx2;&QeEa4#<94t4#JCq%yuSRz`#$`U`+xBKsNJjAj9u}u^Ov7B
zd-g|u^Xrvq_uHN675`keLixSwFCrK3e7-CG{_GX*l{cQ)@yfniMs{s{-qkl=+w+07
z7i_-vcW+uZ{Nhg<Xa6uW@51@lJ#fW4{^OCQ<Ngu3Bfi_X|Jm=~^vIv?`@+xe`rKO|
zzw2|+C(l28_c!N%c=y+){I2o6DG&KifA6UI8{eMZ_5D{SyL+!6yYBbPj+=kd``+~8
zy;qFgeeV?~|8Vvv-hSBZD~~HYV=ikwpE_;r3%@_(*w(Uhd;f8I>HgoHKKHrjfB%lu
z7r%Gim>E}|Jbco7XDYv!J%oI}_RG`CUs-fY^>^Rts{Y}lPuO)IT4vYnyTqRJ>-WsR
z>K*S{_tSMFjo~dnDV=lrugbT~|5a~$+?|m->fT0uZ`7!NX?CHqdUUjVWOQ_U`NPro
z7M|2tHRe5yuXR5zpE#x`zw&FxmS;Y8th?*M!j_X>cvJ5c>)!sz>fjx_H@VBl&7M21
zXZE{C$@9Uv^0(9pJ@&(A^?v1R<IJCex#fSP=B74%?V8l;JB}S=MyI10^U`WN^vRDh
z2;cDQVrJ5{?{v%F_EA};XSMzGoxH)iZ|$>RPk-szb(!9|3yz+5@VVa!tA#hx*B18X
z|5zBVzI@Dig?SsVn|8kc$hr%A*B8QftZ(ePdq!j3h^(E_8?KG-S{$u;Y3BS-y)g5+
zdxj_47l%j7mrlBJ$-Re;o`0`TN1y)sb?L43_phFQ&)f3TKYp!U^0iA%>9H$h>KPx6
zwnUfrzIw&X&08lGQZFvKJoQ|6lz(~5U}5h1kBIEKTKRteH5~UiZ_gb|-&MJzs$YdH
z+;>6#uj?WjnY8Zi{n@(K{09o}E{{b0<q=xO+4V*8p0#H0d)8Kb|584mvE?jt-IC_;
zsA^+4+hD|Ma3;<Ck?6YNm3)8tmiBudS-a~x(^oyk>B=N`=$q!`PJer2gPqY^kZI}V
zTi-T!sP+Ci&n-QE$uotiW+**I4qJV?+6~1Qip<E$($o@}W#i9YWuIMpc<bfoucEz8
zk>X9W+~|j1kfDdqu@ereHkLmAOILaB3Xb%+UA7-NBfjm2N4l5qx<V@HiyKRC`9S=O
z#;$?IJwG1kA9erWCx<R{n`d5K*|O)Z!OZr{o9ns{wtLt8J$PZo?}HPs*ejd6j+JFo
zKR>Cjbx-Ouw>_8Le)ICm;8zFwUwGrZ{=z$E$Tc6|@Y)o(_|i=SGWpS2vh}yKWW~xK
z!QTx)rz`I=`r%%gcq7BmXT?rfA7hufT})M4b5>{VSw}3fy>pHI?n6<d`sa09s(&ud
zI=JpO^!x3DtA6+l-<IRa*!G!r%MYf;>)I|}=Ui<6xG1i+HpiPM=i_gN#(eI!ra7qg
z^7K9HmQCN|FOGw!j*nNp)UcM`YkA7Lba9YJ+{|ifd`n<^*<KP@9){exa0i<*AEI65
zYQy$r4CG_K)iQ@P$JYz?OxtbcV@7hdT}(3;i?qhDa0$%3_9SWh&A~OyaSDoK-s?UU
zjPRD*AjfK0hMqJN0-qTS3YkLI#WN)>bE<hZ+z$>cUx1H$d*inMeAeC2oW7-y38q^{
z|5<#o;_<VOe}8+HRPLE}*O~A%@Po3Ar{pD`R*<R(;M#2;wbbTGbO@UcD6Z&~p-6|$
z3g2;*a@8*i^F-S2nyq`!OyoInEc6`n^0wq0DM|1nVRyp@;&McUEUsFSEL`sC{hfHR
zkn<H%Fr{%1Sq3#*jL#HTDoWFOQLBVOZy`XvEH}0<-uz=`E7iqPjo-?ID9%D%Nd;}v
zCpJ%>P*XMs;oOVMYaQU{e5=i@R6-rleA!nU@$lx&S!UdfHjA?XBYlfgm}Fg5A}=YH
zCUH<<hFEUODl2YCa~KW>h8rv&%JUse&u&938?$b(y7to<LMaOJ6sA7NK+m%j$6i8L
z>_kqGHJt4nFAC4*DUZ!8+oRO}%c;%N|LuHi`r7L~h_<G2;RLt$+1->*mRz%=_n4Xt
zWL8uP<(%8VAm5*7hW*^Bx@@CH7RsBBk8Z0}-I4*;3;C_KjVXh@xsoYm3d?H)gVJ8@
z<7NN&`98?bR-30^eU)bp-@fpTW1rf0{ddmTcFy0YeeR#j)<5>f$$x)+<F~K<&gWh{
zcHcjjZG7yylb^cujBmg1Z;!oj+|OToaoZUupZxGk|M}UEedp^hPJa50WuN=~wr@Xt
z{kDzo`^L{tKl$%(%>LZI3*LD2xJx&_?{g1caq`n|%-p!|i0_|q{ivs2+<3)>_da_4
zTQ**K<fl%*?%l61d-{Fn-~H(IGk^a3<34@Hw&R|f^z?Nf`^Tf#XU`J(^y&M?{c`fQ
zk9_PKzr3!O^Fwp4!3IrrhT0GrY`e`~Sz3s?nccBZ;iML>h<XZ*uOC*BbNFa(kr`1C
z+O~|fzI}sRTONqorbp`1Q;6!((%(J9gq_7sp7s$%1I^x4)bJ_k_4)*s3Fg>(ukoYO
z&W;Xs>4&Y%fU^gga%-N+pfYi*n?=>iP?nkFV(h?=Uyn3f9Ob(>WzwzG6he+);*?(+
zP~!K=^?zLK{|NoR20Cf~pHT`|)!XmTVKD~+2k!oW2UYr)xBqhd;lIL@%R6XoaoI~c
zQX3O*x~GmXt(%{u3XDxp>TAf#V`*(n)iw*e+I<p#Ue{)qmqa#G^1yFkJ%yFHp^bqi
zvUsH1G)=z6^M`7aDXU{uKY~4h^wKiyfcP<^zH)HbV%CkZ%oe}dQ<H|566`>#oTF^D
z5ZtKOxm37E^4^3@zb##A<Y!G7kY0MtEv-bbKFurH8Q<e12uxgb!Oa}nVQ8aL<C|-4
zWS)24ntD@_O;|B5GJE=EGu>b@P0KdLK4)>e#WF<pI~lgj9YQ|E8fQm%in#zLOyCTq
zmfKj8=vp%)J+8-=V&BA$h4meK5-PX96jZFC?L6Q!Car}|Toc+R3VEnmf-*DO0^G7c
zW<&M{z}a7Mq22FUPd=de?w}1_x-|m0e7Et(OWsRqHQNmtkUUT%9-s=yziN6>2`e>S
zX9wOnLk|fVetHxSmZ=3*{JkC>7URA4f1V8BAn-DdF~qA$QnDqe>z#yq&UIA+rVtg$
z5MohvWEJ_5kI^7Hs6C%oWYx!#WLw+_DkZlA`cA!$XAse_#>XRcS(Ok8#EW##^Xe->
zjKe%vkwWuKU8t89nO-lUQ@L8vlb=|&YJ9ooP=y%{I0{V=)=@o`rHO}2euQ{yYF@zB
zH+`vd!-wXi$IzSON3jbgQ?G*G>PH`89y+*|7j$^aNH-QXWlI%G-A_b@8KfHbl@Sm8
z4b=3@q|#sv1O0fkm`oTE__Qbmchb#1Q%eitQav%rZGdXJ&US;5yvS{#<;>e+L)uo$
z!chW-{w35Tg%kj9ql^oSoKnSb0$0#KsO%g*b=dDvaM$ODIWv&0Cm+ifC2;d34Om=8
zaV*M;e&W;~XOE7LRA!qi+TlH0xi;7?ULyWAV-m`tmwT@%YQ3nYYjg+r9n6GTuDI!r
zk5nW+Yh<oN6h7Gwk^)3-m3k<32GDFW+)G*7HMVw|HFybCU%ab*)de*t9I7G~F6zn(
zVs~D=$U%IGuO(S%vY${<1Fke9J_<m2D_E|huw~ow(v~o?CMR)C<|}ty6oK1de_(~k
z_ON7KuB|c&l`?{8(VfV0BLS<}hUtZ6@Y`&NTG9uhwIj$~aA6m67T!<of_1Wu2(&E7
zG4(`&2ErJ@gb+0S3q#}-i5C>EX;jAF!qWbpgbeMSl$<ZsZCz5Ulc2#rq=#LO^7E39
zRf33}#uZAc&E!n-$ZNpEh8XY1Ti@sU*yEW?wT*y@uxtVS2t>-UlLfstd9r(()i{{t
z7b!DN=!F#02=zJ*Ho2t{MyQ^6%mUgJ)_w31U}UH@AIFZSidP+k`f^4q2*wxy(#SUU
zz<rxwi2WsN_P}UL1eq8N0C8GiFS~$y*E#M*f(b#C@L&c#yb<k${|e|hEAn!s?GY$}
zfHG4q`H8mwmSQFJW8ZKzV^|8>iHtQDE74LPZa~Iy4N9&>XFnpG@~5?7ZP1RIIgAM0
z$o<r9Uq#Io(<rL-X<=+fK*Jk)eFie=UT5nL-CC9QE@U9reCOG~1sm#EmN0%4lxZ_U
z|B*bpsEstj?8>08j{F^rpt^E@AE(#p=~AQ~kphDTr;85OqORUbYarLiQ@J6cR22?`
z=|LM=S}o$N7Z7j1?`{Wf#ON#<IZLrFGlX`zu&r8<SAKpwBq3e1Beu!~b!yi~$4zIt
zQVkW->9GqZNfoO!N@UCJ`C4E6g|M#MtNqcgP{rgG$Er=!8P7ng)v{;8mmBFT+QNK`
zZUNNGJq!aNjkjIs-EK1yrk3V<5P5!{FZZZ2_qxgH-H<D{*$~pB7n}(SakwNzEgAjt
zNZW^Wb=D`(f-E{bqnF}zS?PYxqo6XUhjmZc70m)^VV*);mN=C~e1j2lYMBEgK1k1s
zWT+(7aFmy5t<X_89n~GZ8ydKvF@v`h7~+T4P&X#nx`;$3Fa^;rnwKm35rcP3<OUtO
zpYJacZ>h?<m!O0cKc2yWXegK=Wh2RXPB*s1IV>3#N^7wMv1gdz3*TnaVGK~aNt~i{
zn@A<M6Pu^EQp@lYidF&DYv~&tUdq|>WJF=Ki8xA@AjrH<gVDOgK~v+zW0!471G9O8
zI3pv;6+DZF!C@ZsZ5vemj>EsUw`1BOLA0dZY3^NCOX#4WP+2WPM+eAiX4sRZh$Gmr
z4X1qwD;q9Z0jlsM&4FvsEqkF68kne+l?o3!hv3FbmJTa%4EkD@(2CRnC@~0mf~17+
z*^GlePCIL;%qsFA9WS(egLq`9&UwA2+xyS!i_~@p6m-*uvcI!}Sej<7lEt=*OyGq+
zrAiq4Ws1W;xoW%vm(H|=M;XTEb8_M#8u8i!I%ty`K{w&0ADnaeM0)5GhLg?oTn1p`
zycFSMe<0}DqJzH8xrT(mQo`f%p-4)dqC0dYk(CY&5;`yfDZnc;f`o$xQyjNT^}tJ6
z2~=1z6N8s;vBRuYDQY^}zCz!WMMU&g3L%x=4fd~)>o}$xvcFmYsNBAL5ovw$xL(WI
zLDOsKoa|w2p*CqBkcGShBU!5I^IQ>6KZQ)ZzA6)Sga;HRy_gOU>QM&+4pr~Cq`w5<
z8EJYtAd1pKB*<npevb-CP?+8kM4~MnR3#R6kewQuszmgWI}R3h(H42~tMQ>FR{NdA
zrBHkIz-*ELWaEWoUehIFjI4$OXGtr{5X!_Izsk|_Q<o!x|5F|!SNcIOU4d1D7M)Kx
zt~j;RfmD}+n1(3~$t^g6MNaBe6P#2L9)W^FBx9|tJ0J&Ur6QJINl3*{YXR47^%?|v
z(+F_j&PY&B0<^M)Nx#wGiPSW3D@Z)4kfcGIo_3%LmAHC+e@zW5itT7487p=EJ(tk!
zXUc(rK*s`A*Q3;P&T-ZHFk#l?Rou4F1%?`puziwgKgzYgjVR5sRiVbR1jVpgR7Nn(
z4KCEV<Z59pR9RmAY$ps{m7dk0)=1PQ0e5SG!`mEk(%ge-(&^zWYU`YD5Ol^Rah^#t
z;|_j!+d&n;9Mvu%q|693A)mAw;sJYZX@2Ziwj5D`cso~vmS61ZVfH}0OR7|%CScAY
z>9R9*$WlJWsZiLuQ|`Q8;29RYv)oic_!PQg7{?qjaR3LvND@$;yrow5;GqMhpqOA7
zDU~!D*EtJEDMCW8Wju<E4`Fz#*(I@w9nRF(G$>LB8Rn|Od<AB-YjZw{QT_s(cuk_M
zUhH5^+1{c#sAIdtRuiAsT{0aEIypedt90^uQxG>#2xs-8;X%^3=~L8?i~5*+=1>oz
zx6_Ax3BO#(L*r3iL%tRDIxL5+E-FKUo_}qB0hHAGD@hlk9i6<aCg_Qp5%D~-jgth@
zCnJEJAj^u!M<Vb^W$Ae(bbzF9x~}&+RH(5o!Iomg+FVDanRHkpr;;Xfx)Pm8fja#U
zV9zh<(-1wA4zJyj1126G$!EWEHAIiBRj{s>9TMRn1EpIAhO@EG{|)612zkRm9$1SP
z-3Q&X4In|<l#_T*m_9(A@ieBYPM_2{b}cD41c<R644ZU+3Y?~VW}(lWtJSuZ^wC2A
z(WC=igxX#uvh@s;WX_%k=m^bes%%~9Hl!yX#7L@YlS(XPq2Mp>iblwp6VJR>8!jHC
z;$u^d2s=c?6jY24c{%H{ziGTU0!(}&<4{q4{C8yCVa-EUD2`SA;g0LvtN23=DpUA?
zCR}@3bmAAU5ZIAW72lFD4+DUm)wxZQnrSNfX>eLwxJrV^dTwt=2E-?{Nh9L&T)Zes
zlG<@k&bMpgA;7;H1SACqB75{Ab9|y7i9boMKG3Y*yS&qz6Bo*v>chnzwv}gf2fL7}
z*9xPpIGyF;oHu%>@o0WgkZ9w7Wm{5|tX^<N^|tqkPC!%Q3sl(ZPynszz!kN=t%3;q
zAaHD3;Ww%taO0$@&DaCV9ngHMeC~H1?E$+AeHe|BOv+C2O@curQ78!1Ep38OsM+x^
z+qpWt4&3toVJd(pNfD_ouO-)bVMy13jIIMRco?b@3>B4TWIMT$TBX<GTGV(Z-Qo*m
zYSoWRL*9pD@a@^(kckm%+4N2dLMU=bZ9jG55*H^nPhWW9Kv;XKX%dd?M<a7ML&2<2
z&?Gm-?5{y|gh<Aw1h@mB;^11Ia)o<gjQLdvj#r!nOK&*ql3Q|#*-NwdY?3;`J`g!9
zE2$T+D$!BRK%j&PM8J8^3WKy`8dT0H5)%+oJMI?xPKhSv28NfiGjGP<MZn`BeV!W-
z#Y|kt{6o8ogmjxM6Ll@S0OrVAyR`|L-vP%u!gWHya?LC#2J^JXbxI)$LgGB3oXaN_
z)H#31hB}#JJA(Q;;1c45!M6IZ<AD#I(Rctjr}UHhOM--x$)O9RE`Ege!vhfsmCj}n
zOcMw@G7b3gpDY!WlH+2zD}Kmu-6jP~N}%ke1QMu7f_$eb4MPlyVRD5AW}}iV`W9fE
z1yKh%?qKnJPE)IM{5rg;W_S7@7N~TRo)~qElo=9Pl~Q0W%;Lgs8!#ZYm4I*Q0o%m5
zAc>=|4={sZqMBr(a(wSvVRV6A4ySP<H&{yA!8KA1u-Fpbr}0KiA~OaWDt6eDVT)g<
zjeFxO_^ns@AO&z?iVKcMBsRH=heymmS`KYz+e(4bmR54_T#ByqvP9^;&IM)4o{>oM
z4w2>v8p^3v&~csgPG2qr%qA3Z9{sEl&^Y#KqqR+^JSqYbu{WsSTYYW8H)Mcc0x%=+
zj4zw~8;@|fSc14VzbK_XHmLNbs7sU!t6t_kniX@6_{Q(xMZPK+moG`R-AbA6&;v|t
zp1kinZP-}vrFRvTW{2ChJ00}pd|MvilMmL^mfMPDoO8CV?`-*eUwEEt`N+>_sO~G*
z1KV<DbyOZXvJQKT+icMszNo)p{M0f!H+-A)<skc+?Go)W88bDX@1Lk8EXagv9q!?6
z>++R$xRqvqRkBN4Cce)EHa&fwtY=8Jd6|`$^a%Fc-J3QWeM~cBuwvNxt#;o>4?E;r
znPR!rTFnU+7_<gUQmJUrx{;AoKKzCDhGNR`t?jkqgJ$Y<Ii+ZeQQXJ&OuQH!ZN^Ki
z(=pry!I=#X%TCR86U)`{s(Gc4q>5U(smZ)F1ctQ>g1%r<SS$}#>{s1zI5<ANurx=!
zAro<G^K|e(IQY60mGbCGyDOjiQg%xz+*}wcxpllMXN{d?th0^u67XevA*={$#I}6h
zcxSy`BEHHX6pE`$xfRZM#Ij5bWYG1d3)TguY%Z#90pDe(^?Dar*RDF9^tedAst<UF
zgOq9AW;h7hPPna>mbqdEvs-zeDL)*RD?#6gEXqv(F{({|MHw1@nVFc~+_sjTA2X49
zIMv!i^A&3!iAM&4b=9CcBM2tP7k_nwtMULLs;#l^GnF4P*)X<0@1<QXqhYdYbYPZO
z;(?x!!j&CxsW7s4n~`eK3U6bFj*n6V1Jx=M$FZRV$H&!o4hM%ze{s;RpnX3c?>edJ
z(2=0Z=9J&LEBSWa7f|L3^55}r>ZY|1{^+Jzvp>A-zGMEm^x5C6yz$wc_um*Fd+pM}
zX&?L8E58XI{M|F*g9GUavw!;KlV-ni%?<be$20%7eSUi5$@x=epY)eS%|(CtjlV2E
z?#LtNkDGAvKbP!TQmwvx@vd=W4(>hU69=zY^wWjE{mtXo)Ygm}wdx(`A2MUvKd$-a
z@{cUP|4XN&c8xkDwQ%+YSC5~u;_CZ{?j6-$^W>-rA3Wmf?_DzC{r3+&G-}VzTSmoq
zJhD`6h~{y2{Pv-DcP+o-tbhLWxL^M6+s8fn!^dA*_rt;aN4^~&^Orx|eav4UYF;t^
zy4K_qkI6hJuYC6T@K1lb|BFAHHRYJkel`F3w|?pN?`^pE%c<jLUvb;PnQ?FW(5-*?
z{zqRq@$k?7c-d1QtRL4svwZYZC;VmEr?a<Sy5Ow)gPrd#2T#2Dy!<)&|9$jp$NuFf
z|9MvaC-1%H{3Yj{b=#MJcF^PRe7tnXA&*x+aM^1!fBEKjUG&q7eldN;rR%2Oe(w+a
zDr@WWl;1=5iu_`H`U90SQU@QO`a$VuW1gCNU(b1V`HnB%+yC+3tgVcB{j2d~hkt%^
zS8&8(&)X+|cFMHuin%vz8HC@K`L`9V^7ocLcgmCrgQst@@p0=9jYq%r=-E@u+KM^H
z$mrYp-D$_<22Z~s7hkksjuUsn5_iT2uQC5Nx$@rEW(M#2=p_5fQJKu8XPwo&;Ag>%
zu03{o*So4`9sRAzubQz}9iFXM&bjEb(j5D<>74rUJGC7u{ZQmp)4yoz1M9A??A%i7
z*%|Hr-Idek4ZQb9%j0Lxdtd(@(%y4a??=MPsk=<})<5mJ_|`wgm#!Mv+KN7M{K&++
zbI<1n(wEv?e(J}MH*(^8WMbc$&)s(C<@T6WN11VN8}!GnUEZ3ynL}rOFk|5{=k&X&
zKGUAI$}Pyf_uy;n&{emW+y_#*c6`G{@6Bc(eQm+?bHA~m@BOX*eLNGnX5vGGFAu#Z
ze(HoB(=Y1sVQW<OS(^4d<-2)%W@@F&?ATK>BPYz2_CTs$`so?Xa%HHV>ECI*J;j9X
zL3{3!)wU>7-y>aPE^h@}!mTNv8=T0yW}|NrdvrduM;j}_q!sO+vrBHcHOh=>73H|Q
z2PJqX+xhKD%hT<?<vq<a`#$qtx8R`P&8$pr^)Co3slJ}w!K;g}E^fK>@jy;nNrROs
zYBzMmeIg4E8V)kgynIJoeYNY>JNNeRdu&3g);%!!YunA_&p%`)zud~_$6K>`up!S)
z>kckH#s<Yo=&F96gm*99%mFzjKmK=a@|cGtZ(oq?Ra+u+;@^ko4*X}7x24|vl$RJI
z*2d+V58`E#kISS<+o!)Pw|AlW_9t6UtnDto^A2nO^q%9xyMKD-<&#GiNBORgDsT5J
z74e6U4(*B2@fElHp<5fz?Yy<o3gKNQgiHj&iy2K%YQ)6>W^m(+;*Ke`?mwn`L-s44
zJ$f%-+At^e`glHJirggNkyqABl?iovpxi6n$I`u&ERV{pVNcOY&fDmPf{EL4Muvj2
zEDG8Tpk^?r{JK9Zm{6axFUlBSdH6Fhp-cTSJP`Tf`hM4B+}`9I8x2zz?jSBNPO3I*
zo^9r$yVuK<bl}HK7KT{6R2DIHA+KzH`v{{!!C4bA^gI->#TlfXP36LZ4dbF^QN_IM
zY*`$gE;c{bT6>Dk+jH#H6MtZ<Eml)4$ke(Pg||1e&2TDxY*>}-mO)n-u$Iyfvf1am
zYuO#LTy2^@Ex2&&Tx+X?a4K-f=wD*K!T25uY*AL{J!0ZzD(eb5hp^Z%r}N^$4Zx}O
zhvJza79+#jXBy?SwNUAZ%&oBiQCnBXydz*k-Pu91u)0!lmfC3H$?BM@dyg_uwN9kE
zkPx%BS&SjW;=$M4<KV~ZMH;*4`wN5%GkBIUkoEH;(<m`HXL4^=!z=6VB{d(`=Y^?q
z%6PNL_L6>D=-VO>_D_OZlow_#HJPxAqkk?=WhlqNe9OYft}cHfbzZK!-U&=cnIiX_
z9cJXvNk!R>>`gr#kJnKQc2i=SaOMM$QsttcD<#vUG;Z#2MvCn5Jj78IXJTA5L11lS
zFPdQS{r|e0+2TQPzO6Sq;=+73L@{%2?+dIo>rtRDded*TY$;?+Y`MS@TreC@2*kvd
z3j82|Vt&3k70WXBfuA5X&p??UMqqLA)nhikvFvY8y+NAfoTnF$+W5xDwq5(i<kw%n
z@>f^Ryz<4Pp8m(OZ=HVK$@^Y^?A|N)z4YSOpW3(NTYTH@@5|1(_sZ8^I`u8D?|boE
zS6nyqrK4W^?7nS}o&NT}?_09%_iw-Vw{IV{@ekXczJBKKubc6?Yp?&)@4x<*jTe9C
ziEF=sP1D9Jue<y7Z700`{I-w2$hYg>vhkAR?!Iu_hhD$r=@0$$TaR6L?=S!P_HR7)
z##yh=eENfGBlPAIMQ*w9l_UQ?bKg~YWAoCIoaD=)$lg3>S?2Y#TBbWAyJTSU5;@$I
zQ<cbM+daMIM|<od7w7}Fd>HiPHwS4klMXtyOAe6~=X)I^$Csz9i|cYyUtMiLZP1mM
z=&)vB50li<DKjVPpJACF8ardKE1S!^T7SMm%Lrw%%Pp8(E}k~ARds_~<1+`Va%N`I
zT#1$6Un20qUAxCuZ?7O$K_^for@jNuCO|^yFqNy90}idX2mDF2W0$+*v_brr`|kn&
zUr;=VMIF5!fBy~308Fw=q7PiuhUDBoXvpiu3F;G>RLQmB*#_CPt_3nt@IZW#le{88
z(s=nXI|3T=p-&srYo#t(&lXo?TE|1G?s>#QEDuU?lk0&DHT6|>z8KxblTf?KVh`mV
zlThg$6@-p0axX*La|H23*G6S)B5XMnlw+3;?-66H*Zmm^Va&*P11m@Pfc?*`V%U&1
z-W_7evRSE^MSxDrV0<KLKb9j11~I`{9Wzm``Z!!Ug;*GL#!*C8q$H9;n-eX>RDxy<
z6$#6MU68V66Y^OjYrwbd7il(%>q9dX^ywE85LWjCkzZunnsFIwbZU{TGA+I(f?S{Y
z6bXp|ZeyQ<a~C?HQn)D1kRHc7%})Z$+S!>p4OzsSUQ*AcyTM=by%K<-NxW}K=;?cT
z$F^KIz8{M7MGr^?F}T}Rb9_QNu%QXt$jbyJ6>$g^<${%W7(|{Y1wjz>7Zd8?3=}1(
zCiLs%oSSA!LbY>HM*_1VyR^)X$to{gMyzmHb~q0~;TaF9eVO%kq$l&U9*0M3gr=4f
z?<f)SVg!!kT`hcmp&aa$5>i6+HrXGhBQk+gQ3@P&VOLJc4}U*6o>IBiun<RcN}O|n
zSbPztaHYYi$VvM;3vJEE?yW<n&c~NXWBFlf#)_832jUeMdT?N0w~#HXByymC<PtF&
zX%w0ZTlA$}B5lIAkxEla*w`*9?>$4TcBN=$N%^P`deW1R{?pg$#)7x>O$7Tw5S9`%
zBG`tISru9E%|%k<Oiu+`7VL0k+Y0;hUVIWG##uLrrh@6f(1Jy_?Ye?sM};|&AXi2u
zrNb6;i<`5u2)2_l672qxxY+SkICeV-YF9r}fJ$O3@<}+;#9p#SS}c)`CES+0Ksf-W
z=f@YD+*;~qwCxg~my+>q!swg}s!p_MF=JsrIZ-a(?ZCB-d{PO!jeD?IV>=L}0^D7|
zwPwx0R@q`@&j?FC(|bGk*hP?6$Bh$TvHEP-C-3D4wslR37{*I6-ZPbwQWxQ44)!gr
z=|TKadX>J|nDHq9%cLs|n5MEx?1!aaH@nYvUL{1&*-kox!LTiJNf&^^+O%dFdAkA$
z+8HNZ*qSYM7CTxHC}PMar3uAYD?S?v-#4L`2()U+ckoK)Gyuh6+2UyK5E1l@5y2+k
zU5g5=LS@i`6fa09f~-1FNNKu=(u8GM95?CfXwg}vBz}6}*}@d8t64acfbOO@fbeEg
zcujA)+$?zUV1!Gxs`H^~yFJo7lC`R}bRJ!bAHX(*;VZE1W@v4aT*8)x1L!;DL>V_8
zP0M<PaU!bqj%YG+-N}$sKsgA)hoVUhEmcPcX=_45K~9KT({e(bHiaaTBk8=Q{zcp{
z&uhGFsLDGCDC<<HS!$h(I8^{9(vHLs2p#IBIEN*+d3UY@x|w`It2DZutH%Y8QK1|!
zCa+|IIK@k3)`wfoh{_RkO^s#IU_I6BF-y}`8M0*IX_f1puT`z1Tw?lmNj~AY0_nnY
zMh*`|a%zNzFo$?08c{KpF`JsPzFhR1yLx5VA=y4D*U6$w4w6EDzqg}T1-)KuV8(kJ
z^gkzQlFKwJl`PW;<EwB}>j~_9l2T?l>^7{}0`C{kvR)5w@HMoZ<Ev<5!5G*a=267W
z;e2J$%YrmTjBRN>EEbV!6gWAx*Dv%^R^9J~56Oj6!?bcQ31s?G09Z>+EZM%L1uc$o
zy%qQVaMmoN6iK5s$9AnV4pg2ykBH=NR3FOhDZb&0&mQFX?!~f6f>zwhdtY}l|Lh*-
zh*RBs-5Xr|f_pBgNZ0xS7ukOCt3}F|iPxx%9PeEKCspH-@qBT2!?J|dWT{_RDauH-
zb<?gmvgo)~ML2#~_L{6s?NvRT@1^dkt04`DL7RLbuBVH9vox2bzv`FPz1=?8aW(?@
zlwTz*34n+6!a=AriqO=eXxPhN{FJ`2qRQ%~bLL7G9(vx%ZdFQFMr5I~sI4LM1!2$1
z(Djw!c)-f4{*sZ#seUB1E}rEjK2Lg5<Pr85GbxBTKyI+=&PM9pC0iPy^Bg1{23U*v
z<}c&atqhO6dPxN!Kj}0(^(0y*^(ZM*Y{gS7+$iU{(hcDN^><Psyx28F9F=9fgV+HV
zN(*m<U_whf#P7jEG7ML=AmkPJn4z>t;!sP7yzrB%vyctxM(c#pBTBB$=w+?mNu1{c
zOBVW?AzdR^?iR00ymTOh!~N{&5>eq))tn9)Pbg?|nP=5p6%VeY7*=$J<&_^u?9bcd
zQMqm1prBHPaF>K(5|YpfuGrSAI$ub7y(FVMJ0S6%ep~$w7109ci{h+P0GV)4%I3+o
z1gPjFt<Z`_mn6hb5nVb6>1v(uu$G8=RnxYb4G=wCn{pxrXA@$EiZST9&&~x`Gg0UG
zV@*x+Fq|kgSt(sfh3-mXZ<wyPgcI_##a&j>jpyYv<f3OA;%b_A(+1d;N!=+#B*oA2
z8$eqmhj#+$og4*7F78X%f<WTDUNwt|UQ?a7D%YjI6wQnGHgsJLv;obM#;XvjWUHy7
zyyu|;f`fl53LnEYS}ZuLy2i!h*D{8V4rjErlwGYxWAY5V;DDHDxlI@f6@Y?vD-_2`
z{F;x&_LT`bBBUJu<vj7Kw#f*g=e!7C9<=c7Lj;r%23viIzQYHFP6%KpstLs@lZgx6
z0m{bdbmhQNTz#Dc9g%819S}nxF3uqmo)$Xo(<HIOx#27Dn+^)X<ghIU5s{$aJlU5B
zC2qhbSq0kvW@;UncI{rYfRrGDH|on9wzG!?IE^StJD3!zlY&XEk#fS2vZU?AF}5lz
zwgpOD62~o_B$WS+7lxdKWgRJv)vzQOT1!p?w0<SWXl`u`Wlz$<#aaV6D?S<89P|&g
z>Bu)VDj2p2f~?GjiDwjH&yd}b?FeH-G;HYC6J|XEik*{ckyeER%`meQo0FV@MX{mx
zjH%-8d`07Xaxf-gO1fAMz@BEm-+n9#EJL?N;YwmPiRV{Tt<pXnY%m!oxMJtXXiPx=
z1q8xuKp}5DlJBT&Tj!aMu;r&S1fkC+{syZ^K7b{gq{Ih}uD0}B6j{kR$cgpLwV1%6
z3xPQloQ6{aRU9?T6~^@OtU4+(5uN(k6ZVj`8siunNbbA26VznEdiC%`isg@`T#>sC
zG|fb&(|5a0k6V+#qD?MLc<T#Xo%k4%K)LWJw{6Lt#=KaJf;6lBPVF5oWnV<>6fTZm
z9C(HVU5EtAn}PsReWA%FelCuNug*%t^7PAN;g~@W8&%X$t3cS`8mW2Ri3{5lN#bm*
zgE&6ZN3WC&8r~5twV>s^s=)yVG06bIc@;dtlEz!h6f#ht^44*|NP^Z0GHoMD)rp&?
zV>y|`JB9Sy1dgz~)aU0b%|0)og1Z`ADb{GOU1pKA2}v}>1{B;6Ywg2GoKtjM8)R;l
z)ssTh-?78l{>M&Ph7(8!TNBc?I-d(^>bWE)xr`tfABrX5jA(A^MP`~;$78usDEL$#
zcg|(7G)L5$biQsC+dD~AmMM%lpG?63K(v!T9;KlHubm@ZBy+ADa|MapT43#SQp#k4
zpJrV4DnCntL|rvQ-g0&95-K-F8!tXmSRD(*Sg#>_fNdSKbDf$1+*0mU<&$DTi#`Bw
zLZIf1Hj^&G`<=0gNA>dj9`#mXlR!NwgSh=OS1~GQrQ@PH#ZH_j)bW+|hTl23+V3n_
zk-|D*=k*Q^-hl9iY%3ae%DKl=a$-7Kk%)0PEC!_4Y`J(46aE?Z@O$`ZlT-&QRgL}5
zCNeK3SGo~`F6r_lgap4TMNjAjVUp$kWQfK~6{&!N^GPYIi9`vqw}G?hm$qn}*NZyP
zf&MF;0I3_rjGp{1L7JYre49%_d@^$3Rap<mfrD&9fysH!#@hO``zvt-B_*0UH4{r|
z=N4l2jixDO{<T%Mv>zUXb@&#`V+6mSy@2&SaBGuMpLjA;6eaJhu<CLI*|VY|NRF4_
zzZ@T%{y&Vp4VV<gweWwsw|D7X7VTXYTotuu9b_=51FlL8F*U=WgRVLdG~|kL7BPZi
zTonz;MXebI9Sn&BK|?<7bx<@U(S&HOF^Mq)Ld2+7H0Hy6iAGFJ)S$tSM1=QudLSR~
z^ZuXbU%S&?b?VfqQ>RXy`t0ruA;ZsV)K)E~mQ}}1an50pD3t^e32ttP3%tgR5R8Fn
zNetCB4O*?DbLf$icQiWn7Ri`Qidr0w8(2cPE-&lk;IT&i@ud-Kt`2tE6lRekGNq_g
zd%z_ydWK}wVvXVeV#_LEJjv0mH!)73WEb1ACPAlg--@4-MC|X0*V*u5d7NuAjP!67
zy-+@*cP@c%qQK#g`)OvkR{d)Al)f<e!t2OLk+EP}Dp<5V)I&U`BV2LV5>xUJUg1+3
z-__t^tiJNmV?2nF*eYQ?e#M>%0_kh9$on7cD=x;tgQ8OBU`v-HzansQgbmX)AwPjf
zNhD(S(d!hYpzVOchfLLes8d)xcaRLdaknF=a=hX>dUS{d4W;Nfe&I`>sGi~&Ll$Ai
zcjBcJF)-n~xR`OYct-g$IuiI7x8C;El|LKsmVS+;D??Jo3n(->d1{8^8p0xal8CHC
zO2G1yv5}!B9kr1(5E-TB7Dfz8VOm!Ur8D&$2<d=mp4ayR%U!afrbSt!(Qm|z>O!m`
z*k!F$G&}K4rI|%s0DAwZRW~G&uXD<cvdrCbL07rrYI-qx(K;s{t+r(4WdpiRil`BQ
z^sdoHOUAPvFi2ZN8x-zT&bx?JXF=<dRz@G%g@97>>Tp?*mE>I|h0f8=HJ1LuksWQ2
zL_Q6`w+?j3>+%yO#I?l6fmm|oUq!|ckm;vyG+%fKL;4a6Lc8`zaEuqWeeoF>$Bl|j
zfL;)_=d38xieSh~+Q9cPo#Y9e7~|r*qFCj@RHa3-kt0l29?Nie+TnAivED{FjL|}=
zvna!B%HcZ%f{CM^P%B)PAA_wJ(IN;U8O=+3izFSW6CK1xBHBYVtTUxR&*2=ZX$$<2
z0o2|&q}=MuF&i{or|Yz)bLAbZdwbPGM^dg?Wsdcp#DP`m$h4JmC}JgvoXBeo;xk%T
zG{JaNvcp}1J&=Wt!b~fBuKV`wvU)9V`pG1C`Gx<u^q4BPEElBH9t3zv@n^ii^CsAq
zzEWj_6jy!Db3ImTAw6n(A-a3htg>y}+2UHdCV^j@)#ypsZW$lcvz*0q>Gj(>Hs(bx
zbft-YSK!h;!R%5Aj>BP3$x0`^m7(zs=}n+6tjpQ$N2evM$&YQer}EPym-EexU|BfV
zd7rk$gFny0gfZw#=6hwEt+lpHD&|#7J<mk#gZV1C2iwA6!G?qcskz?DqokPMns!su
znRS=Z)djgkju-!CNpP0yH_rGz#mlR#1LxJOIB7H8!#S_i@aqM?(rKIw4)g9R7ddyt
z;HdJvA9R=3GFWC!uBR4Z7lX-TS@5-ukoS}Y>rLI0VeMNx3bsyL3l8oPmn^gtmBla`
zEs2fw8L3s&gy-d*^D7sNtX<a<<o)QvN^X|#Rpr}>3GkAY3zJe<C#NM_3Oy%E!cJc|
ztL!NEpf}bo73ZQB&w4!-@e_AO!)Zv4%5b9tbE)&f?)G(UW@>A@8-_4VZ_oG|^lZJd
zv@JK?r0IkFwJxHl<#f~$dPY!*u0!VLqcZO;@%qBfcHTK<ZBUyig@xjeJpePXvik90
z+o7qb({_)S|6p;+Ws=O6XXNz57kSCrBfXQ~dwu@48y|_!Je>g1$q)8l`t-w(4BNDH
z>5Yr0?7F1)@c%jSg|&|?{Zsj;OTTo=3D-?H{O}X^eD&&wU)Ztf_u*~Ve6aKIDWiYB
zbMWC8*6-N3;*blbbRIZ-^zL0(4DQ-x2FI*8{GiH>m$oc<W2iX)=_`uWn};7%{p#hz
zUitL9LkniVer4&@_F<cEY#BFs&Zma1{pH`Uyz_>ZgI?VDt&x+z^68-;PFXy(W$Dym
z+aG@TpeaY3yy&nWP8quM;iV%VcxcBrH|*JRik>0*%`qZhdh%xne0uM)!#4cSmd-a0
z+IaZ)Px{#-Cm*rpXD3e?d(VcR9pB$|$7KgCymiK?*M9D9`})qtZNICJzjMXy%a54w
z`Du$@`@uQmcD{YZ3A6sX@rWgjiP!9Y;A^KW`1^uMul(<$@2fmF<D`L~ZJaXj^NUYP
z-0_EFpZL<mlcuk_V#@g|7kuo!k!O5l#eYvdZSjBq`OGD^{C(<gw|wH#Cm+6W*x|pp
z@bJI=*X`N&w!CoZx|`=s4OYE)diu580qJpD4p)BpfTMirt!2l2>4s&8-FIhcV8fk>
zIo}_ayZ_{28~Z2qjBB4XW!#tNt+qY$zB;Y-n=dw={Cdt^@OXK}nBSD!Z@6Urv^!s^
zp7Tu4Rhd!!f8BW4lnrL|6tm%D<8M5}pYZl$9l0$R_Lwcdo+4{^9Atks??d_Q+ELR_
zU;Dv1Egu~=##=DD^K%cM(D}Kk*Us5;`jLxQ|7rM~TjriSu=K*Sc5l36(l4Vs4r#BA
zo!Pl+?0H`rcIE>-^SWNo4lVwg$oIQ%8U6hme-><OeZKo??|FamFZnPWUze({S@yL_
z_m;j?>~1|R8F|Adta*Of;;oHk(JJ25@l!eB<L3@O_)?F(yV3Q<DYJUUCwHydc>S)9
z){oD>|Ix)`zCFD-tF&_A=8~Km{k7|W%+KH7mbqc$oO!FdK0d1V)CuQ2cv}DY<-vjZ
zPnUAZY0FP<9dm|%%&nIWJn^gloTq%vF0(e(SdhPaW8QSPWM@X+)a<s>8Iwf@*6%c~
zS`W(yA6;$hKe_5BCoo%?{L4i>4^)Q@rm8_^?lgP%+_nq<d!Dp>AsMxtwn2ikwntB&
zn+vl&xw$eBtaN9}%C2dF_dQmB#`jCKw38Pp=Q_<}`GrSLADTR?)Y-dn?P$C48^?*c
zeb|6pGGTV((!dT(Tf!-U<Yg;uDqKB?^<LVsu&tDxb4wyYQ(ddw`1{U-!%07r+~9AI
zlDQAe>^!Dsr>%M9rCe>=MKWpUcjotP3BDcWmJOUZ?V{BE=cJ44AGy8%ma%sa476?;
zDAu1zuB&V=et1UbtdF%$=-D)Cu_=vR5Z&rMI^}0uW=wfx%g^Th{;@MtHE(gTXU6L(
z=N;d*D)B}C=Rduo(R0S9%E1{|q;4ur{_&F=j!gb^#>D<F54YJLe~P-6)ymtkd6ED9
zjJZTMKhPa4d)6OwOKWij^L8gPD~D;D9&9;kLC}!!hFs5ppSwePr<Lo~%{PWww>mtl
zbzUwCUd)-w=AKQ-YkSTOE-lE|GcclOPI-8{oigL8X=Z9>;kw^%>ST4n4$6#T*F~A?
z%1x4Y{!gBF{`Bf}PZm5{cKOjuodi?m5clJ$MYqX+e%2<DafdQZJ<Vj#T52Zcqct^|
zQELR{D+*G3D)KU|VmEH&@t_{QUOOh8nIuDn-Vbl<3HkUIkKK3mCUw{2DJmfv>?ZSy
zT$zhn3zRACtv0SJw2>L@ot_Bn7c<o!li2!{k)6h)C(9IrkrUIaAI&pBGjdC*#W>IT
z*{6!GawMx>jWBPw)_rG(q)`t;_w_KFDTN|KWj*usonsk2xI&)cj&mg!1*L#4I$GtV
zRYypc^Cm{d28=yK2R`Z|8wE8Vt{LkWMa-mzn409e3MD@mI41Tw*f5(nTHENdLa$;Y
z{}2Xel5(X?onm+e>*sYX*g0FDmd`LtYLR+hhv!OL#iK5f6628$-!b562*NNa#Ng|h
zryDoZ9kFXEr*n+iGLkK&iwp^7a<Ur4K@&*N%--_1Cxs&z*@UwSj4mVy`U|epSP<AH
zXI+OWS3rGLHj8CP+~^?6>tGowH~tLzNWS<w8Qj?)WuTPzOI}nA``60>DG4eQ3+^tj
zL)>J}M_eJUq<CKMTCea?zQi}Nr;V2o`N-u|?l?X3)b|FSa&zFPuzxy}_@|$h!_Sny
z5Z=1}b_quhKD}mhz1;p(x0EXrc|X+1+fRS$UY^fSyW#h?baxbu)V&t7IX%_MMd_e(
z#Na^fiVWv9Y@=Myh<$csZg|)}3muwxE27htlg*R8A6@YFci+AL*SoKK>oGm^)cMf)
zZ;XHK?b~)PdFzZl$3FMcw;tO4*PDOy$sg=l@`b-#cirAUeCu~h-njXXC;fWQl3$;F
z{VC7hb>MS*p8gB(aoW543(uW$-E)6<<k!1D|A+Ihe|OKqpI&~-kA8i5%WwC7`N9j{
zdhGgZZ`*Uqp69-L<a@h*Q9S>?m#;tNwpUO2(Wl;SfA-E_UvuqWU%u}8cXu53<tH8*
z`P<j_Ui03))35u`uXh~r+>_T0qgLga7ewwnP~;b9zk9iX^Ge$`@hdaZ<@B;}f|QxG
zFx)<>H94@sO9n~Lulmb63K{3;zSHoF9PnHC^5~AxwKAqH`3sKq+H8NT%xc?oWIk|W
zGpS(c^OU@nlNI4if12Ys_A0MU)-3hDW=p>34KgbAf;E%3O7O7bV0uvwUdbL%ZK=;8
z5GgrHw$^xaTh|OfCsQFLF~3`SMCO&JQ`rC_g<8G*tJ4^qZ@K)_aU2Cr|7Uo=59q(U
z#=i#%x%l@FMA|Z1s25^vlan|UU-sqB6r`wUOrH5}Gs<<ki9rItmEt^@uY?5&OoNfD
zbO&g+6B89{j(Lwa3EpWe<;d7l&@ht9vzx;nKeNbsdMgAPaL~ujFHJ2B^dN<QixmBw
z-!;DiG)sf>Y2F-|fz6`Xs`I%#bIY1n5-A$&i-X`cxKCR%Er8*&HH9xAOdcIdGPHCg
zbe5Tg$@oHaMW6{lZlBHu4rsSpYX~-cFC7%Ng-$D?!gQXui{kZ}d80enA!j>OPKI9#
zFkDJ1roi0?YM+m`w+jpJ$<{90euGB0x2CdYk|lank%Jq4kA6-W+yWVd#)w1OnfUCE
z&c?~f3p%B@O_L^tX$I$xq}$|JxTu&$yi#s`*y=4&j(V>_E;vT-$`!<T51DQA*zd8j
z#wvgdTjfEH506>REGMLdW^0tGC52@GlKIq>c#p%8RI*;38;lv2lSra^(e3LjIS3o3
z;QO2`Bc9S@r`m**LcCx{T-#Xc4Q%p_T?HGjr3nbx4cb5TGN;g$o%jJNY-T6Z`J`!+
z(c&3u-|E|O$qN#gWXnDDW3|LjfswOE)75qNlm=^cC2dt7pUB50NI7vu8QjP;NG(BN
zl%~;2UOx|rI^zS={ccgVT;Pa5)mUs9IVGrVpeQbgz`Ua%NDaVohK?(gB3^HO8Btq@
zm-AYr3LDZ;_E{$+c^#@&S}gj9u08{n_I>K$IjC8p#kc$Q5rJ7FB367ySLqz{7zEm5
zimJcx2Bx>vxKj;K@nDfGmeP$`a7m~9a?e<lJ}%NA*9NHdg2r;!c9qe4n<qA|3)I$F
zPfKMV`7jr-4F|ECK5pp>7qR*dBK@*K)sRDA2t*f=8T;p&m2|rd)f?3CqLk>{Odc_X
zKRP%^L9Bs8zbK^*T5!deYEqdW#aq6(RTZXs?a1C5muSiHNFktFUJIlW)(u5*ozN$&
zLAt}hM`A%tkQyd^WTbo(x@xo*64juOBoc~UfHq4Y{$dBU!15|hnCo+1+LxQ)xjksf
z`NQ+#&x98H!0ie0PzRdr>V}AogIw?g<nNnCOHNiR)FT{v<HaSUL{Sn37z*1w2cQ9I
zw5AvkHQ$xhC@2lqeIjM3>Dc~TE}n^XLPX^uoNUT?#CmaY9c9fQrOP<t>f&4fbfK(h
zIwCq1f+bia%2kc&wdt5}PFg{SH^)n&!PE9>e3im{tZWWlCl{wO&v_g&EOwFB!6S!%
z*{+r1pqA9Nc8d=~aYif#TFZeiHu%I+zM$3cC>WifA>KK*;A7F02&u!Sc!5pv{mhkw
zsDmcVJyEd+?`q!%$3o8WPt%dUKoiNZi9V;_^`S&9y#x%oU>(dMaFv&^RXUV=hdpRa
zrhGXSgILm{5UQu&+=<ul^Boi@r^pI1An98JPi0){CD!yNt;|HK(m{KugBFHqaGhP|
z`dnWfQZ4XhDCa06c012nK_%>PHL{)0_$~^TNzrAdE#q7~>G*({0pFWGM0*H>No#an
z4j%`rEc;_Tvk12Hoyq|#k$@N+qNT-TlDV62v5W=+lUQ92T-Hx<$Z4geJBW~@3#?&1
z(b=h^v8g&>Nm=SGV7EWrI&2Yj*jGYy9Vj?tk?Cnp>Y>+WH)T7G?t{y8Xs<ps6^5-D
zk8hTgL8Co#=@F_>Tn!eG0X1NK)JiSG`|1>lLiwdmS%VBS@Jkdf)H6?)J%+D7gCrTH
z6NovP_g-@DfS$&qR|q=pLf{?UEMS@v4?N5_dYE))0+Clt*cKMX%i|G`7-;>t`q|oV
z_;tS~t~%F~WN?FovyG0GYxH%D!E=1u&hao_i_|(d$yu27z;35;6j&!U*kT8VNYsfe
z?Hs5}u`FJLCicGoC)Wed+Q_?ltoVI9e6cEdS2xi-UVnOEp_Mc`w6<D@jqTF6rd4LZ
zjdP98IftdzRSnPM-|DJm-%m=X<M?67*RaK_+koftT(aG^iyLmm@I(uwfVMfWO{zEc
z6_5Igh`4*WL}Zzn9dD+y(F!0wyCcXOXH}Om5Ops5T$qfNKMtk(xH)YExK=7Et|#$Q
zjw90w;|bZL1wpDyoA_p2d;{o*37>qNGJwe=LMK_GG{r=AW1tyf9*oMxAp^ZjO{9$!
z&CM~;!D>cSltwWZBf*g3#&KEkkSsN>K}&hn>9=!ZoG$6Kkc)LqBNXU?Xk0)cG~7(&
zxB2Q-GH?zNYaN434|z77wR$$^;EVPJ4J<2Nb+K@rFIgp}{TBxil-dEx(d@Xyyfri{
zJjx4TU#5}8*fpAEu#70kGPHC#5xfI7fp+sg_6b5b%!A$-P<1$R*)E&?z-fMQc_G$x
zkt-?5TtVg&tEEm#g2!o{<{GtIY2hJi(s=qx&e&P5k>&!RrhOGILH6v;TT)rECT21v
zbaPgGleUaO?J5zMM1P#N%o3^mWXx$`p_CH8$rlzo4LvKtD2RCU8x@_M!l9>~fb#AF
zm1|Xe1Z{l)c)6+(blemxEOOpmRmFl15Rwg|Xru8}=_^US;_8O;fI&=Kx$ykBNQzX^
zXxc+$l?8`_stO<@$`(5xa4K|2sYz2g(9RTU=!?~0Y^+F?;1`E6shXFCJyTXHrrD;f
zqB<Tims%UB<memdtD|BAZ5d$>RFwe+8!DlCV`c-7pjUBC&W*H7-PiFsVbuwBAn3b?
zvNu5&X1G||X_goxag~MKVX%p<-VV#P;*||a%Xq~m>2S3<VnKD(X-(E?S)wp7ngLr0
zN&%45{u@|_swDtx#Oe_a&q|O7?g3L5P1DM4Cd#Xam?i@bAZim!(+$e$7WND@kUc*v
zb3w0UE;gZRJ4eXRLN~7j;iH{!9FKf`i?`1Lb8+6`Jjn>vV^uR+j20m_SK<tav7^i}
z0rck|stLf<#UqB}+_#Io|I;eQE?!(=g_;wuWMylh@jB$tGoF@hW}hAvSC&#7K`C;K
z6Jj){5t`J%2EHn)r808LlC3z3Vu5Iz1|NO#>I4+B&p8qsovf;(?n0g8VFOTVg~ZM(
zlZM^RLO?j<q#igt#@Qw<#*kUU<YWzyg0Emt6xm6UpE|3DmsAh;g=3%+9&)G%Nr(xl
zcCZkoG<BSl9-gx*u!w`(NMC7`$r_Bfjw&Gg#zw`otoREcr<odxX+0yYge_t8){k#o
zB50}UMm{|9LY7WUX@6{4Q>!!LN;+({=t1Z_qs)21G8p4Cin>|q1XN>zs)yNZk$WsQ
z9}wyJ4@t+3_$nwY2sfo9)>=fD0YU??+chdC66-lx=B2X1#ZV9ubLl;$IedXyUZ_PE
z88L|_hOKK{7Y5V`_OmQm*uVsNB5S~~=)bdQK4SC>gvq3=DTznZMO(dgJrZVtS*K8G
zUZG+&q`@SGz{M$5mb#kkbk-QC5J2z%a{H%igD4`Xpo_7C50neua9kMH;o?~XcMGlx
zO66pU&S6iXnIcF!tQH<!&{Ss~DyW`%Tm+3Xnl*QZG2+2C2r+IBaO_c<F;0&Sh!x9J
z-UMRFL%})XbpWecfs2!HSNhtVGz00Otg*F>0ZIZ&mIAnD<@HdN360a)1~8mcLPg6`
z7kN<#uc%O~ZF9f<S6O~V&*JIhZhqF{QU1BB%d)WwEw7le`@->!c*3D2o{mWctp6<p
z8d1Ei5;G0VSe1%$nBoR&_#7(WbEj|(Kzb*{6xGHO-6sODY!#wKVjGe)(6RNFie_v;
zCY4jtB+dyckkGO+c8_DM-lJA+z&Nx2LQ+DG(lsMUtqK<QfvizlZEm0Nt)j%oM7djj
zI7<iK^oeKokuduJPMEi;ENdGSGS~#~L)YW(IAc8}g}<sH7jv&B9J0vXQxy(0hV^e4
zaUiI(@s$XuliKLbGfpv~pVmv5S8+65jAdfKg`jcj#gN3wJ2c=Mkm16i8yePr4p&BJ
zBjU8&P!A$YT8(jVCv*YU)3K7)fM;m9ZA3vPE|cNCA-ZU;j@podapXvJ<U3M;WHg8h
z<6JB|%Pawe4(AkR4FNKUWOH3Gp0v{*nfMW69Pp{+sV*Q&0hC(Lki-D}m^6gRj>fS}
z%S$I75R{|o!C2Q-JZa%CrFLcwQdY%qP-@m;%v8G(&onbw7l==a3O^8xW=ei!U~C)7
z`26@qG$n?cz%4)KflS;mErzgxcj=A6!~{~)LdGr(5d|S195~E4Nn%KwB8w5G^Bzz2
zSiN{8cHD6e9OXEVmMUWexod?NvkfW1Auxi@G#Mvx*v)>84OIS&MZAE@)4qWC49K`u
zm}{a%;<IDFV~;_492e(=o7Mb{3;_T%pK#z%07FQf({LE{*#Z)B%;l_!HCp4WrpJ}z
zYuwkB$fdVrAt}Bi;PqvU>Z7AO66f(%c`aLfR+{ER1P)smv*FY6sIiUwMn0`xXX47}
zf_|i75c7syn{|m4fYvmq1ZYw8Id}{Pmb+~d-w^XiO$3ruDnU~*HPR_5zM*U_??6oR
zsFtB-#kv^DzyXFL%vwL88im2Z23r=?#J9{Z%oui?c&>+HsYswqS`PLTY@RK1z)~!4
zRtY=(v0TB8)`kp}UL1%OEA|SD#$*YbIVa^B#C+1Fd*j0S@jDpBC<(yL@&**5St2-8
zi4&}Y5L-s4K^90PwqvZzqm8JbLL~ui(8B_;)<r@J?F!U|blg6%sZoHo(_(2;cR`@B
zoD6B^ZsU-ZVtm)O7q@pc0A9>V3~yd2s^^hh>p5n?Yu%S_T^vRp225)xvFduf6sJTs
z={cM~pMo!L0{;9k+~T6jeCt};kl|HFZw)$m1o^BUDM^{G<Y?E~aA9Re==?r6r!8`I
z>{ZwvhTDwKj(+NE6eVjr^GNW>dQ=Y>U$08Ame(0pCT|ZrSLE4ay?rR!-XaI|n!y`u
z+7Q?20c|^?TtCw~q#qec)lW~gO=pd2yM?oRd3La`tJEm8yHwpFr?I-$;b#-ms_VB_
zd8bmaV2(|QzqVMn&hhN=9I41!pA&C2zX5lVofS&WMNCk;iWY#_Wg~mTe6;8S%IG$v
zbF4%3-XuJ&i5Qosjj8f!I_9XE3<HF)W|Ml}XQL#Nc99CII6wT&$dZ_JINv0M{@Ji0
zDVx#-mF0tj)B-{{^M=Vo#ZFta<#SAIZa7C!_uKn^IpJ~r!eTn~d+k>CifesrQ+lSv
z195IvFrFsnNl)jLEIPo3bx?FcKAA3eSDm*ytcG<Sghf7m$vg!tG3c5Xn5(_Pn>&2r
z>7$LZplG9Z!}F0Y?A%@oJHuR&k1mYKxua7DbUSEcRST0dmiI6<e!P^q8QL_^h0OiQ
ze({U0WkNAy&*)jrIU^GU>ubhRY}1qSb59>r+32%?WhEg!MZZ__r>2}i8cdTW*>d2*
zh{sslH{{wgsHwl2c70Z8&#B6MDW|*IBbkzIi_Gv3ByHiBCfPAgzIRjFb29x@H=;Lv
zwM}-k_f$B6=i5v)JCXjeiH<3pXy1&ROSgY!ju(e*n;d@ngV!#YeD{*YJ0HGrn4Zb$
z{pJrB&YrMj{tL@)zVRnFKD_K#2Rt-o&9M(o`P16puX>^UaH)FW5vL3saLAOm*1r7k
z3#CVX8lHVb&x#`s9lh(@FK>K3b=gz(0}mY2dFEM1JTrgi;I7wS94ak6;IK;gWUyrW
zuHxdxQ|UWD|Hxr?yNieIp1*78+Uf5M?O6Kcu<eiCe9+{9C5wMJd+`-p;G=QI(qU72
z7Z3fg_dgfU`XJ|BAAY2z_wa`neel!A7B`&u@@Kzv`HSbLk9%>i@_T#o^_M5zdCzAH
zcfNVg<P&#1@u%g_-}A<Z=U*8*@XZMulCQtAJ9XLP_mBPCd-INabnkUHJ%7yIQ(jE&
z?)%gi7Wv=1|AhBlbU;t|>@lkoyU$-UxbXbD$LvV%%Kh=o_tw4Hzq|Tou<q=qMij;j
zUiM$+(pf9b4`yxH{KpaJ7T)~WVK?vi#I=w8{?r{uJbKK7Z@hHsS1x$zlMkNv$|v8*
zy?23M<^3Zw-uh(!j6GNV=H8c1Gaq<<pm#*$dKu9erTlIPCg!)59y%sk_QMh8l(lF6
zsbk>>hlc-s%;NT+uC52K4<<V=KWyHCkIp&Dd-jP>EZ_0NO7Dw3yZkSY?mzO-VM)1s
z^@R2rV^(Jt9#+e|a!zC7i#@mayARv##s&|*xGUKo&NwV}aArg_VP$_|!o>cX{PF6m
zgIms;vhn$I4_p4?iJzUFIrBH;ZaA$nyfMz5z5S{}^ybM|(69FA9=~u(Zqe~yx#*jI
z_x<0igp(c6#*g%D(aGb!bMeqOA8({z{pIuB7r$DW-8b~g&eYiChGX8mCpB*StNjNI
z-MM7K)Q>Kl@cQ4*y6e5y<|JJ3qB-x}^!Vx5q=yf_TK(aapmxIRshYf=>V2OVyck|F
zZAblg!5_^tx%J_D$xzk|B-U?lo9J!7s5avDGiyt07Z<)=J~e&OBWLw)nY{3#_8rB~
zp7WGlUwto^?|k)Qn#XA6>+!RAp~{#)%rj4Jm6o&rD`@F>f~CAoA6h>?2qqs`AGf&U
zg(uS0pA0TMAk#kJ4~_X%aK$S-C+z)fy0v#$dRX7QdEvziCv?94jhcCv_I5*0?xq6*
zJ`r<TUB>iR&6J)84t_A{y55!a*j+)bePZjD{I`#}+YZc&1}h)$_15qP95cZLJ1(l`
zYF7N3UpTOKWqNGo#QF5B$>GcFF^6sGf1-T@8{UW3!b;yp_@1igih{deUK>ovn0cmn
z`@Gxl`Fz(mcYL$!*e!Es_?c}V?I@K3W2U#t#LwpLeEGPG>aXA3Iq&&<lEv4@*TbvF
zSIwfA)8>WsX_-I2=)IcC*jMhk^AmeEmp=X0+WhcG7vzUOv0lQT=gpxXS)R^LYDE5|
z&8eA<b>?X`ATykq)mw7Es<+oaT2J}W>*={O*B&FTuLN%`%G-@Q;4e%yHv4SR>0GyZ
z^xEivbsdXua;!gC7PH4E;4e7SRfC|tdTJDuc$aXU!;}4Nz4d3{J5!r*iSul(TJ#16
zl6K;V%H2=T$hQxywe4r}!s_`FblzHsWKx3fsLpfl=ZlQ}RZVAPIw~^fpWEfOGTF(d
z^L;WSFxgCx7_oZh>1obX)Tgt6+h*zv=p4hqa<yFCRJuc+_Ka7yrc?))p=8=Jj%3Wn
zV^%3=CD>p^(hVCLn-IexrR{ak42m&cJ(Si#(>il|afJ2iMiPv6>(jPuZ)ApzFNMhw
z*z4Z9S@D$Ny(KQ16g3Ljz{&a8<j+mC(&KJ79NLiX--uzHBS8r(UPF{AX#mkPPk*|U
zVEn0gkF|5hCG_K=106J>KH?%rx8)?thc~GVz&D0rmRNcL&r4RslhYkzO9t~}lVk#d
zE&%791ig*YSO^6Hb(W*slDfOdB_f{Jj-mo{a=OsdY6Z4SNu!k01{~iO37Hyf^e};O
zMJHPi0V2<=g1gJ{1eLJCNW*I=)ZD}*g7>x<rrxb^!B$LQ{oWhI<z$Ab8Xe2EpKRkP
z8%zh`a+aIxaOrPmz0O9iVVOMH4jrl`4rWZ}ghkP<j29|0A|CLWtSuCoQ@E_KI@BWx
zzr|-@U}uS*Gk44l^cx?=LGhO-WU8*0G@YJ#dSid!U+&qjY&Qh$e$e_xB+gH_m3!uh
z>CSH~tW94i^0yiCxfOG%*DJ$A3VqVCX2_PunU0PVqJez)K54DlY6$<G>A{ZN2hx&R
zlxYk+kWN{~ks>Sf%+qmWD0#=|MW6WFOE>@S@*i#aW&dq&E`00By(j+dwXgpCvbUam
z{Mg&xTyn2|%kKWK{`bPSN{=7+?%x)!`paHEQTO&kOWxS=_&4{yGw%ma?tSRxzdZ7z
zSAO;8We@G${o)Uvd}z<hFWvE@SMK{M->%!e@XN0~bpNw&dGEdY+|`#q^w@P1zP$JF
z`+vJ<BH=}sz5CnikGk!(BffjVp3H9_x@~CT-(S9N+?QXx;JeSg{i#>Kd)v^G?|=0A
zqkg^j0$VASm~J>d^E7`of?<@twdVkr>vRr{FNt$wS$s+J39gd$D&V?1SBLLgzru}M
z-dSoa3rEy9m{h$UOsLeE@jDLMxG>dTO;0JUm(Ck%jx|7&sZyQQ$`n~vtDw!Mk_jdl
zk7d@oqMqpu<3)|6n9i`?*@%J_+ilNT+ih#qIV;R>w#gC0i$UOB;|kMeCqqlU1##6W
zzndOv)*=*9PNxABUOe^uf4hIEh-$(AjqCQMW8n;E;_Ls9iv<TI{debUFy~acGe*yt
zoHY)T$rkd=hcc{gipp)9CEQns|EDvgaDgOr1n6Ytwmi|+A26)!B3RbO#HVFgS`S`W
zx6B2MTtk7dRc^D|4$rW0;rwoE!xf4rrmtGZelS~K0bbWKEQ}F3vC2GFthEo+1I&?o
ziU*dY>qSfQ!EUh~#uMWm%-cTdk?W4OdzJ>T3qYB*;<lwaeG<dm3Rcy_k|1?!Me4?~
zrmGJfTSyk9Jl65Fm6UpBCfN+IRf>s)aGE{XXqIR5))=``09w~-;x%(q^NjWVs1>sS
zW_+gUKfbS}^=MU+H1MB839>Fha9?%v-68_?JW7hJohqVXb)sx_Q?lt`9~`Sp_{2%R
zuC@`wi9eyT%feTceGyh&fV&_~uE;HT1|$z7p`7y&08<&UJ#}Aj9nSb(w_+n~1neRS
zCVI*j0L{9_m6sc^vs@-Y`#e<$0Y7pWF1l5g#v8=4x7XqsXka(%T{Ve`$EA}Hu+sxL
znLw4py13vzBBqLrmerCE+GUz~)+r5U6vZjXK1Wtb&COD91{^>)jaPjv(`SllgWu`w
z3e=G*UXn|<C99gtXi<Ywdn2-dSMof%-hHuUkNNTjWdQ`T@f~TIBT=cGmw^+%WTl~p
z&JbHsiwkav5GZV}^S%eXj=)6i@woS^#2j%c?S#-Vt2Nu$4lf21ZwW|HlfEcrU5`G8
zLhq-*v4+=Lb+xkNii|6)NQrz#xv@n0#wuwaw7421DL&N`^a9B-snYpB|B#CB(-lus
zV8UIII!VGaVMp6xS<pf=u+8&0cYYGowpbtWWa)g3#e^!$ILj~axoCmLi_sHl1}_bx
zngUMQDV>v5o&<5u7!DI7pz^Aq{CAeUa2O=~o=k;0@1<oa@=;OPr60HoMiZ5z{?|Z@
za?o!JX~lw+O)4r+9aBNl3XrcUYjn(02(eBA6d9%RTAbpt{92W|jAb3BFAXmUBo`Q;
zV?lM$P-f@%@Hi(v!=ydiWfUjRFf3G27JV+90OCD#;q)x5ID$U17z^o?3V}x)Nx;b-
z+Dk9B)Y{nI0uC+!#0Q5Y!|I6XV~eN{(p_zO9_POKiU6N%y?Z40#Bb?P5(R1@5ahwa
zqoc^QP)1xzu#c{WTW~7x7&MfM8uNs*a_G(&OC>T}2Y`C8_<`QRBLs|0Ko6Z5)5oY#
z@eM@8A`R(5X9-6Uy_R1@c%IP$8R9XBG%?U<T4Hsm5+*Xrlk(igprqSp5Aq7niI>-^
z-{(x&5e1-0!!3<LjzjHUTi8dS%R1<hz{NcS`7lyr?3*Vu6O~e+C~r0v2JHC`$&wrN
z#OL5@z*!Z%1w!;Mu`BXwfe?W?O>CVDIl&pAd{O+KrvpD1Bf(q+{JAVJY5F4@vIZO}
z#x08Tbz*ZKYch!z8@V3m^%>`uSt;~mjbT=nvAG=e(-YBfY@1D`>B`YvV^TKT>9Nca
zW|qxKO0d(39zJo2qs10Fq6(bLI(~R)K~bp^xmie%X`AsWlC5hSThr^^B3|bowZ4tB
zp-173guJ7r(3X~p>8R6PB9XLf;Z^Lx1aV(RE2x)Hj_E9vG1yUEm2tG!869jzB~M+Q
z(buZoD47_9%<a}(P%=jRs*w((jCFEg%s9{+GFM-QaeyoXDrIFXkQN^uG@{Qg2ep_A
zt*I*286A1*=q^+)E{L9avVAE(*hu?r^;1#AVG3a&>tI7#EVz1%iZodx1^*M`w?qHn
zNQ_*<9#nTVMSa-S0oBf^y2Vwc$fDW}h!MtaI0?q{M*AhP?WyVF4>0uqxR#J@TVMQ6
z^6K+9duNYOPvDnkb6-S)3DuiuG|6zJ@n?d5w3SAqg|RMrL-vjJhi^}{2`lHu%GsFk
zx}zde^n*U{aHkFY1Uz%7%hSFMCH2A)zNNlf!~_laO+QeulB-KwwbbF5w{(l6U!kRE
z#46|0*}I4)V^2qVPF`%gX)b;I>2T(68rnotrR<j06LKd&3ZFR6bRjDI$Vr7}V<_?L
z_n~gF&MSJ1OVC$Xgtf5N$$ppM+(e79L|`yY6RKHM@V4MlXHp2niR9vtQ=6d~`!V5W
zRGf)re8^dG7$F#nwn7P3kZT{FgaQS!Mdnmgorr_7qU>`{%|z^?y57h~Z(JB<5h4Yy
z%fLQ<LSDrHKv@(gqx#$$D}kcL?hf+ADOKlUkIGed+7&Yx2wI~sWrzu|VT!U!3+!Bm
z^7Y{%(BuI>S>%iYG>brQtCZcM`to_PddK4F(zJ{HbZKn}0gHMQu@yyzEY=}~MG|A7
zk?^fTEVLP&fSjUaMr|lSetyh4H{S{Rt#wIh7-blIzME@+cuXSH1-uh3MZ&qT6La9S
z4cjJXz^Qf2SxkX$FaSxi^cT%Kgn@vS3rB{a8j4EY#q|hf<u2C8)nNHe3V>9%|6eW(
zkh-@Nx2O4HgEW4q=o9)@sLK70VMiRHhSwzV#ucU60Z;G4^EDTz-G$H&9bcOxtlFrf
z`V7n}VWWiie>o+tD@AgsqjT!RQ7y{4t3v~)<*@iV;`3Xvc(^nL6ln*L@U3Fj@oGV1
z!)T}+C8AYnxx}i+JsH49K{0U#inb}W8gaN_G5LD2*YE0xa#pAeDN<}t&*`lAHBs8K
zOQJ|7j3#jNO~vW0#TL8{JW(<tmyp(4v;;kD@_yG_g&gT!;FF=+MIk>!je^(Hp?P~m
zs{>+;zGq8a5)nvQ8k$-v3MpxXEvq+Fufsx9_{=^rk~@qjlMr@Xoc%|ejfsd#MSa#Y
zjaUX4Y#?y8Nv~-bVBnzMR2;PG70jNrsfVrCCUpl9I?lK>WTU=)`QpoHeXw=bK40ND
zXSDb#OYgK8K)(SU<V7+lIj#f=I}W7cEPwnne<=})B$J||!6A{>srZ&0v>`Pe)~1Xh
z*W}^@vTYJD8c{D)f-XZ$8b3+2U~wDi#!H4xk_yKWMhzJ{0EIwQCxI_+WQ{n(&+@}X
ziRRtK8Q^!Id1VEv6|w4(9_uN8zE-wo?6_$s+;nVS0AdFd7#uc%c`NbjJGG>~)fSZ`
zv#cTBg5l^ef(!AG=4fB!W<(WoSDENGIA~mAgJJcNf|$!F+wLkJIBW<BT2?5l^@*`P
zi4%uGL*r8kM-z3c{hHA)yaCFn#e<cUB%GtAdD04bsmAH;tto08;TUZfzLY%^(+h~j
zetOoTtucMyz;81vvVjo8_J#z+E6{m?Mnj2WGM0AqvtD2+k(kZcIosV$p<u`JRGWD;
zGRl!`8oALV^u-m>wmw8CzqiT~(vFQ-k)r12r_myA%C>ZwrZKlbtYN&XrapxL|5rz9
zRetzQKmw0~^RG^2tvoaVMW;R{+*a>a=<_|#QV(VDOU(7cu-mBMYM2lN?y+@-+~SgR
zg%*q|JsW$tLqLqiN6x879jbs(8Uc(HV?b1O<OM>Gpz&=?2?mYx0g#o<kNGp8<q0!d
zkWr2(FNKvQ%C}UA&Iz*+#gCTbas0*3rv^x(oFRR+cFH2hXR4OOPQ0VLn`=3!xFH2;
z)nSqMx!COQ59}`nVdyc^-XEc|e1+$u#U`30i18X)4qzTXz6=0MP~8VpR-H1e8PX~-
z5(Y@%#8#s|;{|Jg$6>mJb^Ew7z5}b(Fap!qrh}&07cWb7?2`cyM+E`*xXjo^hW>i6
zR?h{*v9V%$ae<v;^V(l1VR1ANS!?2&a2j&_k;qU+TZjS3n{rs-k>;U}NC(Wt0kCb{
zV4K>c%4|H1ieJ4IpXXBh-gIuiM`Z(5mF3-M;mgBSLP4SB;#^YwNm(m_dT=VEu;>wI
zRkSp1y%3HqOq?M@4KcdCtU#C~sps2<G^-U<ZDL_HlTI5$w3k&Z6Bg>E;w(l?6$B7*
z+L&~l8E0k)gx2a(N9zQz;hJlc50W{J@AKqvy!^@g$=U*pDN=oEkP!;0(rS+wSOi_<
zZ%D|B7+5;+b()#fnu)A1lTdF!8Nl&*#}F_O$XsvgAu3KCAQHoujh<%a|F$M^Ns@6R
z!#-nFPhwo@hzSBATe@(H5rP<(CN7K?E3!4{8YI{JuqGhFmiYL&FYKBE3Z&K~y8NL8
z;vCSL63aDKEGaU;T$M<x#jsN1=J+#!A~ebeNB^CMx1wYs4ZQnZQFlT#-hz>YyzewB
z)(%3(mWgBE0|Xj)oV}~`s2bsTRWT^a6j{?KT7lImkt7N8_?Y6*-H?A_UQi$yIH(zb
zh=u%)=ZEK9{1(2TQWig9V{*;2IJdtEnDqND%vEErl2>QRmRro024l>s2AeSsA1?Hb
zw5i9UhZ?2BsHQ{x9REttiZ@q>HCE;)2^xO;>TH18ibIBLXUshB>0Xl|gkT&+up&i5
zjG25=sz6Fc!z>eWF`A?g4^rgHEoRwju09`j5%$e2D9gJO8r{q_?Jx*VLvd;AMshm-
zffQLZWT|>_j+|ozxac6>0;{HDjx6~=OZ9cmRrvnd;yg^3b9910qnI-#<gn05-zp~D
zIK*a+$`rxmg{rYMR%eJ->RQ*a@=<2U)TN5*SWC_{JXJ!NYFNECIbM%(4{WpGfrBJA
zxQ!b<nv1y=V_Xqr5yLO;_8cDKEW4edpO4{WY5`LT@f(Sij0L6%R2fw=;^7A<+ReGZ
z(m?T3@i0TVu#`UGGQWLj)VX@SxQnM;R3FaQXDO9^R0PKT0w;cAN+oMG{^RuidJj4#
zb?g3NM$hS7(}pj7B*Iw1u#SbZW#fw$P`1P|n?)XK*u!d2OPg~S%IslLs`sNGP4sr%
z5W4h(e$n$x=nW)hbLOhLHtaCn%ZwFsA$!HQhmP`gk7c(ZKi4|f7cN^y9a+=v&ZKc6
z?E0feC;g<1opf4*P<K?^z`9U7-}<?6y&NrF?L9LEK5mz7r&8bdNb#NoTshMo`7=HD
z#e>5Qk!{$ZzPv!;qiU~LZp~ZUF=>9f$f0q}h+ArHfkHN-!nT>CqvcCIi+Sl|;dZ9y
zyR=!+BH_%Op@T^Wu8u6n$}7gVLC+QR3hsE@f2*xnNtW!GA{j?AeV8{O`Qm1{jOJF5
zvojkrypzCks0XLAoU(-ZeQ<Kxx+&GkhHj?9In<V$Yqs9GF(o67d%nvH!tCj_XJo{D
zv8`c6{Lwr-#41(BM&sJT?R^Os1)*o|>{#D&NMI*Qf){DH#)`XA)UBUPM}2FCS67&F
z#{z5>EB?Kv)3FX3479g)_1%?9pfBZheX^~zeY|vcnxTlL-11FTvq{Zkxl_h;uXLMg
z@_BFha(lZ>Gl#F~EjJ=#Sy%Tyv)&uKoTuVOhn{U~Ny$X12ZQAiFSCDZCm8GTH47HK
zqu>S}X&K1s)=xoZ&TQ=pXSlNh!%;M^YW==hY-X?he5(xDDzCWfDvV<Bva`@(OUWLK
zK`@n4UruHPa<_C93xzrT>pb80#q%yY-}2Dw#va<vBt3Jp<XCD!f)j1GCyk{yFP%L3
z@AJPu`P1{abJpmEr+$Cq>?x<rpMC8I=fCjw!{rz5-1zY9(WmsT`Ph;%+jl&-bms#P
zXYxlJamYaQTzJj5Uw(M!&h3L?>k-`pANub@-oE!6nRj-+Rg}}t9_bx;MECB$zL8k)
z>34=U-gtBCx@iX<xMb(<;s<A+KeX`{&NSWlg<*@&``gg9s}~MkwDGIMwtnG}VT%jz
zEIzpZl%ZFrerA}Ry0mrihZYx<-}#&ycz)``!+Os>ZqekE7kur3L;mve;y3o(v-A7A
z7JmAa|5<SFhxWE^xPHe^qU#c0-+khx@BZneR}WqP=9_QVe|Pmki+=Qr3%~Qwmac17
z{`ngVSDtsql&g=NxajKbGw$mA;fLQk=0_js|K#tldS}t|SN`(4myh3d{hwPNfBVlT
zjQHg5uYT`0Z(qObH-G)m?m1hIPtQ5?ss|3=d)12vy?y*iKYQ&X*Nl4Yq$MAI{i+i_
z^7_bkuGw?an0bFcXvyI(jXL3wm(EdsKQdQj_c@nLdgq+SW~RC?eKa-c(zWxy|HAy@
zy)OmnBTpKi?!W(icFDxs?evL1IqIa#jvSga|5@|9aW|T67k{_^{zoSEpZMgA30=c~
zKd*GgXZo)&gZ)<=J!4&X%AxC0KR6?~=!L9V^sSkVzy106&F}pA_{7zJoe_NUKgaI+
z&b7y_-nsXT{yEdH`u4!Ik!uh7WXqkS-yYe&`V%Leu=;;La>CTL$M=8uQy2Cwx_8=`
zkKg-|{-d|I_K)~em!2JZug;mm!WmQFiO!gm`cv)L^*645Vg2x36GUE|XCAuvPv+zW
zlKMb8WBxp8{N@Q)f4+Rl75^EXQ2&A*b;k#j8!nqYZ`VcU<0oC6op;LhM+f(OH65%U
zD+^aWI&t2r$Ie^vR^qD0{fXlnUz|AD_~E$Y!=Xp6&LuJvUp(~n<JSG=-4A?c&%4+3
zfBdTMU4QLQ?|kFFc~h3X9rZ8!!>n2Vby~|azj@-MC7-=-<m7YjJ7@AUM^0RF%cY}I
z<F>C8*<Mk;Kf(LQi?^GEnQOdMakWb=Uv(6n&j(o@KieF?puYW%i?&ZVdY&BBH_x0p
zY2r^MI{uDi`6mmKtG3P<yJ1|IymQ?AOy@CPF#h0-962@}Ou93@u6^x!mDy`QP}z_^
zzPi>-{mzOF{q@JwfhiWc1|~M9tse2ju%0>7KGJ{9l}CN2``r`Y|J2fRrnsep{k7u@
zQ*Jq4^xV)denlG_d0*G$XYV_*xS{Qi+*hVN#tTj!!;~$5=Y;Q04TnDGBz^IqdGm%A
z+xDUHsov^%6Mb>o1LvGH&VDB`->#Y$%7z{5?C5bTULJa=I)BlJLi5Sv2g22fPC35A
z*~R0&E`@Qoe{JU8n~Krb&KTNu;unXu9e=4@b;h@!$zAYKIq$}joLBPA=sPZXW$_}J
zT>GBwx#iU>|0j1r@jG-y#dBYnRXpb{GvPn`(?MnO?K#(9hPSHnZlk$$eRr9nY0H|i
zH~1#8e7vNpBZf}u8<sw)#h2*y&`w$u76noJ<2-Y9iz!~&=i7c>E!fWteP<$TH<+7j
z;S^_P?k%P_j{e5b#!1U%Qb$RyJi{eE*7}s06Ev(}?~`CzOV2H@7apiRXe0X{#k4(-
z;pJT3Z!tGoamh6@AwSyYCdnUV!+JMslgJSl!(~00XQ-W$a-9{kpz(O^{Tccz3Kcys
zl`e)42~KFQH5|~AYGfKxzppAc7^5q|^q+m0Ruc}T&Z3*|2seDALxygtxmlx(OVLfU
zkZE;dKRvNt5~<0OHg#zYva+mogKRmN5yi;$;vL5Tag=rcamA1vR49H+=TTSl(8D4>
zZ7O{x=raJ47}!Ac%#(D9Ctep*zqHlygZNn9J{^51KRBb%1apF-uU47Pq)*ZepO}Tg
zHSrv*Va+a2&uN21UjhnZ#5f&qwD&k^!9)LnnFpPJdX6ZZ<wd=%Jn-C}R_Zy{8C{g-
z9U{hTJPZJ%62(i&EOHEZO^gNPjGlSodsf4x%^5#y0zcr0k5_`j+JRamnavJ}?;V?u
zW)oN~`5`ttA`WUf$DURp%!hf%um&XGGgflo=%Kk$NVV4Mab7C#4u+jV+97C!$eQ5*
zy?-s4AZ+={j1EC<cBElDH?rNX&G~+G$#F{N>1Z`OIL>FX@h?u#JpJF!S;=S1)$I_r
z8t3=ri}l9jBFh%1_Ema0zZFXN^9f&;rx~&wgN&lVaAhf5lTlZO-b9}*0y}R$gT?Nz
z*oL&{tSs$6Js6R!W|H%)f5*Iqd!E|^*-kz4bT$@p_gjzcz3bhV4*dLcZ+p)^_}uQ-
z-ne|viF@aL>(=YPKjQIIZrd~ON7rBX(B4zNwQA2>U)%cC=ib}#-OEq8fA1&$@}=wE
zxM%Ar&%SffFJAl5eeYfVncEgV{qhrg_P%%L-s>)SYwulyx4m`WV^8dPcMoTpuK(_H
zdlJ8W@3z6SuY2{nanJ2K?h8*|cm3bq{PN(LZ$EndQSZHa+~+U&?%3b{&zG-Qxc7<c
zFZ(gyt~>w!;~u?!@1kqpe&Rauq(xTc(XB%K-lWQ;GP3V(mEd$S%NlIyl@fAdOHvm4
zCU^$4-g*MLqe{LhX8&k{AjAA<MvELhJ7rEb#>$Vqg#C$>QV*j=2_v)myw;YwtYDqY
z_WNPfyV>NX_n92&Ygb|}S~i-XXR67tAtN%-7u9mcj@V{a=T;^of4RB%Eo!Q@VI<iY
zD>WI1Z2#f(%+tR)^RFRv=>P4^{~Ih4#1Zb_qYXj*{hL!vzlq+wHe(%w<|F<Mkp+gj
zb?t`lU~)LHL*on^)n+aYvX}S9d%AfFuvcaq&ke8+<)bv5L9DJzoTqK?AIm$1tiNp?
zjZp1Zpd8gAXRX*qK4AkZShGH*&RPhoQLfAfp+gxz);%zFyn$6NoFZ}Jy8QJryx*eR
zKyb$MLVUw{s)_--nwLSELLj9^m9-b;fH?zikhS9X240n!XHof$945w-IzsM9I^A5g
z1>l}l&KTYrjAfv&=54fE&_yquIay8tvqsM}@EEcUjgdxox24e=S!Y1<!0hcar`8Kh
zQ{bobM6U6fr<ScEjj)gDl|}Gr&BlY(R#Cisq*rNk8gl$5z_&WfDUDu9y1+TCS=A!^
zu?qJbAIMfx9#O~}knZ0JPkli^N<?uc*2Xc^0jV7rIA46rOOsOShgsb$3H%uu&2zj5
zAav4Z^AIAsiZQf`W6R8D>42m>pCFL|$5xzrx;?&EHwl>%XyMX@3}Q=ato4PNV5iaN
zlX>JTFeN?CfgObx-x$e&$(xAD*pQnVGef4D2=D1RXM;(SM65rE0q{+?cYx!NEJc$(
zmD2oJ9|J=YItXiuLctrlB4hjF9)SH&`V^vXGP5Mv)dG3Sr}$P+VuTTBqWYri`dXlz
zh6@Dqeab}<#+ds%@oM4)*-(lT5+E2*jqz2=>ZOKO8}W^kTGm4*R1Jb~G88XANo%{I
z%%N8Vn@{?1IL0v;AV2Y`Gj7uDWV@fBL0DPGG6b`;{SI>0M?!rZx{wN0L`jnxY2#}X
zEvsx;-aj2Ma1c8Q9F1@e@wXx;1G<)qdji&?LPO8vTrx|5&!lTgaGa$#qYq1p)SK%H
zst&mx-AKjZH%A&LzNbDUQgO9XR{WZlvrRiTMX~`Vmom^mpo2csc33TF)ksMh-}a=4
zc7~tGT*H2b;5y-v`r5yF=6i-L+KuKJy8ss0A68L|k6<HkA!AZB?KoeNA3GijHAVs#
zR5T5{j$E6OeqAA)rYpi>z?v!YvG~F2iH~%k{;@0QRntKnEH-;6uZ^l23fjofx{9Hq
zX$E3}StJ!6tX?!ph#|ierC}4uQxaZ$9_OuVHG;8(-=;wF*C=!nsNwL1@wA}ID(l2O
z+*l1Yp2L&mhYOT+k}Z?r-GplVTF?dP&<e;8PL1$(9R^A|S{ea>Bm^bT&+>yI>F}Te
z<rZ<64@|@ajgSuBqs-X@i#Hv%a|PGI0&CgG8~UV*Qu-N62nI)L46H`f2sCkiTdP*H
zi36py7ci`jzx34tkcqeFI$bxyL1@B~qO{yZp`7NT1*Qnub~Gi<lf#pmAJ23x*E~FJ
z7M|iF2dm>x(?)KlNJrXQV+$+vl28d_8DmE%8^-}!9F5CFeB~+Ty_lLsS;;C59XMt*
znu=GqWV1IxF&Mzof34CCDRNp0!_ieQw8o5QXB&)>#2L}5(REKFya#&%dW(dimqJYu
zNCP@8O2LaCZSBj@L&BOPyWnI__PNO*h;<3_a9I6zSrNZ&iN;|*NY*aJmUgcUFVPN6
zi!}~X*+U{qB>q%Vvf~%YteW3K8{oZADi+ZfZZ#kp@e~91n*tPrw%bwWf#cZ;r$$0$
zOnY|DPB-+6jxwNGBWOlhJ;$eGbLqCRh_6J}-~19;8Pk{Z{Mk;P@Ka8V1jALICcDOX
zBz-g$(<4zAeB}{9(D_kkq)2>{mY*yHlR1sRnGt^^21hCquBU9R=wx~+Yw~2K40XZ7
zuktJyc|0!akRp9`f#v^oB`Z31qDK$cyuY_Gvq98|-mt7E1qxzjG2J<!d!-c9Fv)Vy
zU50#VEvt;N<mRtP@WL?ZIRM_!=+GM!^YPvm^5h+aa<JFN%kv9;Uy;DdYR5~$NrD~_
za#fa>H27ITPyd4_9x5j3`dR)p`EyxFbAwKnf{QIz)0pINrf<bRmECI_1nU?zx^M*b
z?Tnr=`8jLO`VLAqhaG9unfOY(r80P<mr&%mqeqqEXyoElE!4q_B|hQDb~8Z*`2z}1
zQBfrwPg#@!k{+@FOf%f?_<A65N|FepnQB~|1NovVz9ZapMk6Ro?Dmm}VT!JF1$m|d
z&k~4A3Uh!ulqme+k6jRBs+W~Ky)-jay3Rl$qfv_EX@ojWN;KC=;v)#7OoB>AFY^ov
zr){)mo6bomo;ey&xvFba6MFOZ@yI?nA-J&8;R{WO-p$eN04T&Icf?3=6cs{>D4R!D
zG(+5KepU4l6<V}~T-Rw_i)e?URy1}=?G|n9Efb9_sv2}Kt&TB`jXeQafwop*DCvo<
z4X3jvK<UceVI6eW1|O8K$$;vHstf~EF=?7Nwmhl*f>RqKC1>%g+izIaPknrya*;&q
zQ%0yoB2ebirOW|CyAY4>X}f63?XCZevn7&6RT&M`Kp)8gafEQD$&(Y~ByjOz>(-|J
zQCT(q_Brz}cU2!KcwUo8r~)-MHYmWF&XBVYb>_{H1DDb-j&qBnW9_*YFY*VCNXlyT
z4#^1GK@xMuIYik<FH3VJ*0*33=};6?ozrU9KoihuRNbs-m)^#WqSh(A1wp)0Hw0+=
z@I(oUdT(|HBx%IDsQ`8TtRFb+Gz`O)v^#tp2D6YJtLJo(H-6N`(-*|4b7I&VR2PRm
z%R68+sjnatcddcnhhb2?R_8I2<<>>IeNN@)B{U2h6j3EAUXx2uXoaT8E%F>FK0ml&
z1f+MYEe?{rYfF7G6PTM$ZDroRw%;5F8KgtB@&#?t?D%~~y>Ti}5h$M77iR28ahdfv
zYAVp|NXA)mp}BxVq_dzBjA@b1`KqP-lhSEf7`?@$0S4rYf?5>4NTka06Pv&Qi{pbE
zJ&wn<Dz#Wj`8sUY2$7@Dt>W;;;*|}W8Cj5t!G|-7rQ8srb_-l=i7ZsDxZ=E;6K@_E
zU9>Vlnvpf}(1_Q6(}P;ytgb+%kE(4rv7~iDNy*WvIK3L_AwldMJkjQhI(oq&V<76Z
zad48kER_`+B;JrG5`%I~E11guQn{=lnd!ynOoX^V!%V4~rQk-hsVI0-oE$(#a(;!}
z_{UmA8B!TU++m4pp2KNLX=-aby#y4qK%3%<n-sJ-!9-%5@)CF)xdtId@k|)cfhYw^
zq)S}n^Ur1$BcYqxuFy<4`Uh#k3KgqVnV;dsE#rr}sDOL$`dW>KAA`G?1Da{vW6{&8
zws0a1`QqW9cGo1L61TBeNBk0Q<>JVnbL(n9n~wNW6Tid3O6+BPpok7p0KykL%ydlJ
zkx5L|0~=2UV}v($A>$>I98G?+s&J!B?Q3drz>5u+77P~?NvX%|3*aY37RwxCSgHb$
z)drx|rlTgDCXYROg9!DYVPj3RVzj@<tE6JbUCaNE+Q2HdX@n&uNy9$;C`4H1zP})N
zefq*?O4ICw9YN(^@9K#6un&R7pQ;<KL^tPT5z41|Vstbg(V3}Ja{HXK>H*0>q(HWY
zNN}XV&&5Bd>9j+(zPsyWNTizSsmr8{hTo2+U{%)pokb4X1;)<%hcZD%s}A$sl!<eQ
zED<wqHMf#rCeSE-)gzf$K+RK#O%;o62#4Z;s=RdhoOOL8`X4(NdvxOF8TD5A?Q@R1
z8r;-=K->k#dBw%4DuOSF5vPLyryjk;O<7DmW>1Mo(%^S$rhS!-7ni24I-(gSm4A}j
zm>$<S>;N?*@UXJ)6re8cTvkh?&cs&`RhG}Pha9$0k6P?bVq7dVaPZJ=k?lVB0x)$B
z^P7#qyo<Y;+df_MpoiPv3kPvx3SUA6)g|I97h_|eM;~ZnpI%DM@m%OZzX_$_N{#kn
z@i>0_9Qh`k)sh?0IIbQND>S*0{jNvTt3&0m?|AspJObY`TYZ4^O><mUJbp}!<E8;I
zvL%SdLzWS!BItY=pn-zgAO-d4V9F^p)H5VE+=f?*dQlSCsVtg+T_m9zP6LQ4aNP86
zlt^f3oSxAxO;;lo4uej0OF*TmLx}%koUA>j(OxpZA=@SGMj46OQ+-zx#wB+9ZVDkD
zyeMevm%3v$iTHSeYLzp1APk>cEV}GMoG@QdB3c8MutR1{>6DNfL5`b<jj&qEHBOtR
z<Ibm=l#+VYIes*Hy=s|6&*A+eO#m(SVBpLva;-#l5@=($@^j^2q~Sucm_x*DP0W|d
z8D=!f=p`;0rNYw}3raz;Yj;LbkR%BMKm@eh9<<cw^b(J4x$Dz%L?rMsJ!lqAqvMQh
zT!7dc>dsTs8Szvko!vYa)im**{E|7f#u~VW9J$E|(qX>P@6e+NFcJ@^R2xujjlhTF
zjHH3Fc(81XU^!Gs*=8yg8171te^tYrnmu3@1vg#0s$v`QP9r+4W~1#{t27>lDElik
zT4^-Tj$L&h9v1}0s6bVBsD6!POEoTX%pd8S6|Y@YlVQ3hbE;D~EEz+NM!kyme+YXY
z_^7Hg@%!AHo8%@8<R(TPG{8w5alojf#TISUlQ80-Q3p-kXt6uksIf&iwX9_=>PZ-2
zu&9Hg#n!f?Wh?92Em~_`w|@pj8x^;47h6=U(P~RuY^g;J8s+^yXM*d#zu)_LpJeVm
zf1dN4=RD^*&-r`r4O!@QdE-OJ@K=+gqv0@=0^j9@SJcOoU@5ooO1`|1OG1c%P6EuB
z7N3l+-5|^pVHio}ONua-$8W(k6PX0Kh?eC6;t!M;4`?NKlXfp$0yU!Ha<-(}nKGjt
zLv%VuY5p=07^)0CcvFEidr^si8d04ZT%a*f=QC#UTxqxt8huz8Rjbvn4@$J0)4786
zrzon?$!MDtL$kuEn^jdfypTzX-=#FCQz*LC^F&@-K$)j_I9?}Z360JoiOCHbZwz&Y
znSu8Uoorp)SdAJa8_ADnN0Nh|<Y}oj%3HZ*P)8|E=QdM?cT>XZ0!tGdn@hJ1)Xer;
z&59v8bl9J24tWq2{9d|AN@M40bp#Eie6S4z3qPm~k6X#N8p5fT25}?O&eikI4q~ck
z#r@pbJhqK1&?N37sVLUQ3r}NVtNpDC?7R~UvWm<5s8*Dy1BR`!HR`6%A#Cq~pm~$w
zJlJH_nm!}oJ^F#YDIEn}L#H=q=P9HR1j#mKZHovx*w)n7caCq#Pc0BxsysVpQK6*z
zpXOjDWj*pRUQDdp6x*o%iK~;X`ur-E%j&deld^Q6>N+`<X=d4MtA?IRR<BSgPAMgW
zRmcgJCnsq2b5!y|npB`!C!|PvK$X)E%A3V>beETCzKK!YLTVzsEbN|yy$))^uy!vJ
zu4+@!ZHOC%$@Z$dy}{&>ZH+-QqnuXWT^9!FM2hog+RvdU!&R-_bCO<lZIJcbcyn=m
z_%Hs(AXDJY;Ppwx=B`S{hW$X@$#?gfCWXZl!q%E?EH(T(Qim43vN?fmVe9Kc`9yQa
z1C9AD7xA47t#2>SYi<cd4<c{nT?V~RD>ZF}+IT^~iVxNXYF&*QDb%U_DnDpzEbG0R
zdEqUq+<TnfLcNYWIEuPftXN%M{mkl<PVJv{^3Rrqqmv(B@mlS>D|SrpXrKGDPbS~-
ze!C)9y=6swMn`*m+Iagrjjs+K@BPgSTc%HGpZ@LkrP1$N_e8H&g_CDYX`eQI%JPmq
zsb$UYXgm3|+V+NqDa)qs$t`c$V+Ly*YJ=LdYUj4}XRkZ?+T4-%ey!H7{vrP5*;A%3
z$-c2_b&bApb!~ilM^DT2Q?n;N{@q$Lw4ypYW5+FWhA4g%XPzGaZSBB}x9%M~ZTG`t
zhwon9d&Ah*H!pkhjo$8EKYwrX``_*TyFEYNxc`NFm%cLl=gU5I-;W<5Zu^!yZ<(|9
zPltBQ`t89#d*%HfFaP!O)5f>H*DyZky=gnk`+l(KSARTe=hmx^TH5jFPcD6B>2W*H
zkN@4+w)-2#H|#!t>2JR9iGyE!{IhdT*>!Z!@-KXK{QR-Ym!C5>?Zfgfn|@RL%Xuxo
z`Qus3@7_PJy><UtvF!fyuZw+nVYc><GlbvI|A{j%r4K%P-Wd-+Ja)#W?~Pr$>)~E+
zN5kgkzkGcpeE(mw-5b8y+wkDM8)rQ8<E5>;ez5GxS+_jWe9Vu2mE825IsNz6c5M4&
z_5G*LTD|mBix1s<%AV@IPh2}~XKUf>%MbbEaUFBNJ+rxd{UJ*~wdA<5+ctl7Py8om
z>^=M6X7n6#<8gDEo<3;KwYxrl;>pQR?EF^hAC||)PJjD?$1fVc@yYr*hdn;;C*JsH
zV@*FlKlX*MpSAp)JqIf_cDS4!I(H>!o(5l>x9c0fJ~?yQ`^RL49{TAn`^ObyUmZBC
z_xHPwt*_p7N9oSj?&+Sjsblw3yN}zv_Pv#<>;sR+HoP~Zefb}zBx<f$RWqv)EE*k~
zyfgRcNjsXOqqC=s&***N!?Sy@e(%(QgSWS5PaHU9=gs$Bxwmimr}iA&@x|U#Uc0cd
zZdZ5Qbfkkrr)Ag9NM77O^7ORPxld=eca%*}%RRlnL%SCZ{rS+?9j~2xOg_`OVB@|c
z`<owO0VTOY_*TzvswqA3{HOm|9=&hDw9>aW@2ER;^RWZ|vg!wJ%pSDqj>O`BnV#qy
zZt1?f5ZirIc>Bnn`(|Z#Y^rS-=x=Cmn)U7M8}GGepBSCCD9lxFA8cyeGkVSu*)8`k
zjIxh)&fT!N<CrHp;`je@)57s{l8g7QobuVd+2Ksji=*k(f0ojzLQAH->(2+Z|LU=+
z{ZqO+U+pSq;HXv34GmHM9rMfQCcd`ed+p!fu*x1kDOPB#^VYU(|L2V@*(chUb*xIH
zHar=w+)@f_Uo9-_?<n-vef9hOwcGB=toqi!b?Eku&8hayse@m*JG$+@e9(7AJ~rnI
zMSV#5yZVm8y{hk?n^f~9>(uuiE(PCv`0h;l!+-6L{qnoP(3OE&@n*Ow+*P{&!d;tN
z{^85B<FWS++O+zL75D$$SvL!B&(C6H5#BR%O8tXv?Q7L4d%6m2nnRdas<p9^t?eh~
zS0$E~9!?a(Z-@Co8-|aSlKuDHzA;w5y}x?rs+Mdbe~M|hVa+|o)WI+3+c~z|o=)0K
z{;pefRK8aol3S@RD-EV@E38wAhwl!joWCMA|B@f-qFtxev#NAve`#a=E~^p`7UPL~
zs)p0$6>IbTcO=wP&5yn+qn;suihoaAi+Zq$kCdk}kJ(6#sHB{E3QOxA;CbZ@YUDpR
zhsW1%4l{MdWV*CLKdm>1Psy@>SW=@mJ(BG|@{w#t^IEY&LA|=E7+!wTW_5b<5%pI7
zM(=lao$AXqnhRLf*z>>!RUX-_mSl_UE<chkCm%_h`-?&P)uQT2J)%x8M8U$X@z|a>
zi}BH28%mwuYuQ-ywYfq5?t=QYzIA(-Qdf7-EmW@v6-Ud|2m_5R`Ba#-JfChg1LmSK
z>h9LEE~)&wvU-S7S06u9D)LBfQArm$8WwGt-$r(K{!JgLeyfVAY>V|JTU2>t)ob{-
z*(m(C@@+bpRo3%YSyis$K*T^%1;aK-uZ3P2KlB(12R#hu)5zYIi!x%5MK+!v9ooPb
z*otzdY5V2yn=^6M&mO1d3GVu1BP|<b%5tYSkrDBvVfuY9(lUfonO3EUiQ0-u`VdAo
zjF>vTur*+ZhesF^hE#o!P)s1|4^yG^lc4FlQmB+aFVIbb!50(xjWWZx;$i3RMy-8u
z*2EdpGC<C#XoxKp-;c2X#U5aolrv3NlLF>A;0(|IKhU=Iv!ORT%;fC4h{+$Hshylu
z)z|yUu206*Cpe=~^%mJ(t)e3t2<mcVS%HVLr{-Ah#V9khhgr$CAUG}`)3Y8?%MgPa
z+8p@v!$A21*|AT)zh}u?&wg~~Y1dJ&?7RNQf7pNQ2d_6gc*8Z5c75uV{a4-g@(rK-
z;P<yYdhy>HcHR5Z`+c|l!}Zs{@YCbo`{12h7CgM~gWb2Cd)oCc+<WeeeCzJwpY7j&
z>1|h@`rZpaZg^$<wrBqS;g@dc_~s4M-+$?{<6e6AhtFL6;8Qnz<vaLa_)5bI@BHnH
z<8S@phOd0{D-E|^eA=h>UGvi74}SQ}4PSZbcMbpj_dl+EVdl@TkuySndrzsapZnJ2
zXMga@m$hHEwuZsZA!`HVZj)ZFluVS{3O_Qn$*9jJ!?QdcduoLrSWj1*P!~=NOLn8R
z%H~;|<dG*Y78X|6OkoSZVO1=m9kx@|*`Yx>C!%f*ro?Z&tUk=Qt|{kLI1=W9Y<LY@
zr1R^%8-p+#M{aRtls#WX_jCq^vD$^<EMwFUP2`uVg<t<l)TL^^3H&WS(*D1K)c^m6
zqIl6w2mfa}DXr+3k|;Cr<Mw|A(fyBug`to92l8+Ma)#vCr60w?fsET3gw-8Cizd{?
z_|lq5gN?rA&a|3=CJ5l$y2F%jS~=7LJt5BEk9h@dPi<wq?ja?IDD5lB>6r!KaD2t%
zV>qhQ;)z?8)k(F%p=s|T+OAhp3&<irO8my8j#QKJsq27qfp=^niQW*ZHS*-^MipEN
z7pzB+H!ZeTna60u2_7o4QP4?L6K9Bm$LbAlJyHHe1l*xo2YET2sv<w#9NnZfyXIIE
znY|ua7iu=FfuO*}p9jA2gF-MTteLF>(-|7fxK)?2JsNM8Z8rxd-Nl?Gv`oNkP)Zp2
z=v&p@lRBAYiCiarqk_g)e<?aL@`jL=$VH5UW#tE5q67$YLR8|!hBq4U(s&FRVM)~I
z;HgFvz)VM_AO?Q|-1sas2z>n0SjSbQw03coi>KPG%0te$VC(phy+TI>#zltZjobu3
zo`*F!x8lh$=b|z;ux`{@kxNZ-v*$6sFHoW28)2maNf@DHkoqvNWwl|^QS&EIR`XA=
zHp6nj5Yf3Vr!PK9T-+|XX~zc+k=sF^k{}?q8QaD?mBbyw3e;QE3Vl4tBmcNB!l4`q
zRgFyx@pj_B$75NK;AEo}`E9khTkE(~=tvS)37o_T8&pZ^L+}kh!TBbYqj4FocY;f%
zYqkUgKz}29;CI&;@iiLeyYyk1K{_e$!%hOx*fwfVl#299@Pa|uGG5?kn26Gkh$iX!
z%F>Hhqg>fy$v|)?7E>Z+<M1nbtquvoyCEWq0@#3$Um5hVsv;6qim5t{9d||0V8E=b
ze*ytI5(dp|l4$YDnWyiq#?crhxwaN!3WfvDLTkJnGPt!~g`@Z-W58&ag@?1Xvfe0u
zPK<@VCkRG#FdxSFZWMmvB4+&@4y4iLSoQRUV|qNdz(6<%+KX%ql@~qU0)@~wrqHBS
zY>Fgjq@b0hA``-b8NeqroB5n4XYFcOi$WxgY?4vhut1+I5UB*$HfX^oT;*60$RJC<
zM)HGDGl8BQW2&Ya<>eXht-44PQ%_xm%!^2iFDizb;6b8K7EbtZ6-8mT9Vj!`N-oUF
zJr63V{pLL=f^|>TdumHKhfV{&h|=jgkuha4TtUjQT7-Ov35!!<4{8#XWSP!n1tU}z
z(NdwISFTYt6h+Sdxa90ssbCJq$~V%Stzb*rYCXcLa;TylJm@)EXb53Wp9NM!%OeYZ
z1oJLsB<_f521lxneJIOH2$aa8j)kZ|SwEPhGBGhGDC_{pK_^271Dzzs6htkHRds4m
zjF+=pDqpI>+^Vb)_nJL;!j_0eAayn9^YQ@;sw70>kw=~ssq#stiE<!&Qo)FCl)ybQ
zKt|?O$`BwjtjiGWvk(>8dd^04s%Wj|`?6J-m@w>WGhxxNz++|=e4PLjVZq0RDXsF8
zVT97?Mr2Ged2>@*HP2LPnAN5LMs&dbE;s_7=n#fO&xR^ajm{<y$L`YpY^K<pQAeyn
zf6Q8A9k01WVA&ru1$GXrtI<h?kbF%-BoE}0D$jUq4d<v*KBDZ-7G{fJXfj#!AlBK4
z99UbSVOZA6+C86_#@BmC@<^~cI7xSa@I*E>QJzBRLYov|z6y{4<yOHUPx=RwRbFXR
zbrRjNrC78l)yV;$5@kb*VIu8iXgOXxh6X_t&~2mm#BX?z4gG}ZIN-~fr<W$<vPC}_
z>cY{ejatP!*%##80zZ<MhdZs8IV&IDH_fvqQtSJ`V+G9)rJ+1K3{rh6YM`9qP-Sx@
zt#s7Z1X6R#em_IwY7aYEP~^0bs-lQPK^5OF;<?5>9%X=wGdUR7T2j?Mo@gb^Kps`J
zDGpLjL2)oBZ497G)x5RCZ}!StscaTEH>NyN6zGE+VnGqYW+7{>o|;E=@}Rg%l{_u)
z^|ARm@CMOhs~+TQg)CzkGo;!yO1Wx5z48NLJ0M$@oU~G<_JCI)Bo*I^l|l$Rm;w~T
zrj1W$MH8^qK2hmbBBC2F;rT@#3jv_Bk+3H825wASAc3|RCeSg(2vur=Fi81QP1JEf
z35;{omM3f%7`*q*h$cF9ve1x31;Nw&c)-(WPKnWTDKV=MSB7k5bJa>RhziJ=nvm##
zMv+BN935%L6aYIckH~681EvY)aR^`NsNl&ZBjq7=1qyPj_~2BHDiNqFr?MuH?2!vx
zX^6m%5C-g!YE^;7p@1ZzKD?EMLnpUC_YzD&Kp-6ku>!a&0O7MRPBg4e<7irlTi6J&
zhzj|VqJo_5A_Y7dS7lP>3Lj@S^UX@4a=OAp9+Ap}I@Y>A0jia5028eYlrf=_5R(Ou
zLfWcW3IimF=!-OS4$}dxvW~2x)q-cqFF{yLB4X|Us~>tAPf#r*QKhu?sArCbw$*?S
zxqyq9J`9HynLx8Cue6IK-*7I`o=H_jB4=%Mldpw4uZDy|KmcqG<|9fWMlRNci9Y^h
zFHQk>x?8Fe)+L^Sg=^Qa%Oqu%pa^IoD)s7M*ajAd;a34mqs3w>Y>5;`qy%_!Ef`Hh
zFp>pitVF6=f>Z&QEgcY6ItZ+4wGuqRzcIuTCy*mIYqe9zO3t)nCufPJpgy=scr<+D
zRC~sS$^c4aXvHTGkh$EbTF~tT8#w<5$W8~T3erTV2Yo=!;ROFIslnmj0jwJ70Im4s
zq7Bwnz`dH`fXE_guJVus!X<afIK`nzIz}OG4^T5kc(j&ifj~HmWH#@L>`Ah&N_UG(
zWDywQ#CXkll_ErwfZR1%h%P$t@k{_?F2}j9v`YyUjvPCXV-Y=|?~vet5skac#Va5;
zUFmCGsJqaW$m=u&&uV2|7{;{%+VR1ziSufe&pSkXdC5-usQTTV)U*zqa?&vhq4T6v
z#2a^h%%!D(!qEZ3l-}Y+GFnT?Tx)hL^SXQr$0$)irro&M*We(jD>G>rWGZX;5r8Q1
zX$_r;evDM2uwtW(bfWkL=x7{yVq-2WCsq}-K;<)<N=5gOjt?=x=Eq=%VUhMNImnhV
zw?0T<1$0*8c|EbCs1;@x`R6bh#Nr`i?aqY}V3kTV=TwDF^26nY`HBMLDc~nDVi8*U
zBX)5jUS(N%IG}rS-r-!Av2w-dAhE{2_^M3GBtIilaASnFGqs_?o+UsQqcaGC14Kz)
z&g_c;vvq_Tc<{8GeXkVVXxHWiUos?PaUmpE05@sLxgaeS07Z|Cp{rdfyvWn8KN9?`
z5k!Ew1HVkgX(dY`EIC@aNYWrFfdrGTqAi+MXftAnyRber*Z`HLkP|S0?tDJPhYmz(
z(kt?k`64+PBx0#x0n8{Mvi$tNP#SszFx<C%EbJIOM@rdUStSl7_FCabBqY~XBUcsn
z$vp+SD}o5MQn{*PvnuHq)0BB;03tW4XpU>ohLSc`lUNEZPdXrjuvv?zMlOI<xHC?;
zVMPX=(%c-#omCUAF1>{5&`!A1_+XXCrzBkQmI5xK6n;UxGzKYSUB45&R+cbG#jp_|
z&KBGM5tvA6E5wjoAk8!MDGM~LCr(Lcg`(9?me-C8O#wpxH%P}P^aWd2qU`bR&d@}r
z_#c&od>pujYK*wuMI7otr1MN%bQk@ExFu2sK!DR>(&6LZx-hvQq99FqTu7@6CjNhb
zR&zj%RP{tS^&oB2Nsl0N0G)D+(=nRSxP(-tc$S=uBf!Tx7*rEgKx)MMTB^xvCu&Jx
zC7r7}$<I`>HR=u-U1)v+TExn8NfRJ?3y9xHY7P`8z>t})GFnKYuS62!OqS$Pfk-TD
zQW%3RDHP2)BXk1A*XT9rJ_cX`S}wj}iI4ukdBk8yd4+p`<d&x%l$Mi~V)%`;E+c(L
z(&4z-twa6jlE=lGeFaG3vND(t7VStQ-M=(t<r_iKgrva=RgRxl(ln_l0<aN-+_ck5
z4W@JzfQ2b3me82E98e9RA6P;e8qwR!S)Bhq(eW#JYU)iW14d1BbJ`cLuFw&S6q8Iv
zdMe@8bL7R<DZ#;XNMgg!<xVQb;`k=O8ZrlvlF&&~9)JpDFzoDUn~X%!H{<M#!zCAM
zrP?55DZ6ULq*-Y(yc=7BD<o~BI5{Q2Y}pD8D@B*;;A-S*<wANMFQq_vi;W7{=V9iV
zs*oVmO0$kIUbI#~^Rq;1$;l0O<H<@WT}x5os0z{lz`ZXkd5a`M3TZLBXq3tb69K;@
zM0gs~!W#yJ;sj~JeNOa>%YY#k%2^rQ72p7W3Kt|axF~Ezvi&YULQLA?tOQmnhd{6>
z2S760ES!7<5{`!Eh@jWE5^i_|UTaW|;Isbby4kc_zL9u=36DrY9#D0Bh!el0iL6j@
zK;F{7aavcfs3IeB>yl8%Re(-g1shf}bWlm@Xu4sH_yZQ<UG?G7bni%u>J(Cd=<DAR
zBA`{5_PAr(;iZm=C{8j%jU|H&)#GAaQb}&9{W5nRN+PP;Yow)$sqoSuW=QQ?cp&@<
zk|QTh0Scu&x-si~aEU-z)EA#oM^;`7CLUTfa)7L?0a&sz+ByNW;uS-U6a?BDjqq4$
zI2BA<4{7K{vt<xq$v#;jCekxf7NR9P2e)&T)0<)uEN<43REgvhYh7@LBqR}_gOV#x
zLB@80)PbDCdHqGA95+^;ZR+-^{cPua`aqtV@5*IsWO7s24UG(D$z)Ku#_S~9=qw$l
z(St!R8VPB#1>Q!_`cbpI=+x6w)g+bHEXwdWU}Jo;HfpdGE>X=U?FA<^T4SPhHVB#r
zC{9mQTq6ZG$)rjzQ7aR?-=UsCYJH5Mv`(az-|Mv|qgxa_l+)}_&uygYC|P}?)E88X
zL9|=L)}aVu%|UApf5=+i6dCfefFy^;Il#k%Mm)(=%27GG`KHmhUUM=grYaZPLi-O_
zRRwF=lL><wUayogawZBJz+#l<k&qVEUQ)VL3ar&ptFi4WscDNm&>Qo@`@_z5c;PXX
zF!rZwSS}B}HeWrWYP|b3Vnr~ls~|X$HJ!jgU7kk5h2Bdr*s&nXaW%^Vk4oFFG`tzV
z7!O*kQJu8n3<Bld_6bCxsPy%9dL^=_vx<Ak;Ge^w$5d1Mwl{@|Gw5U=>+-6nz@vaF
zK~IV9dg=Mu7<<C%FtvHI*4oRq#GJ*{;aqIDwk)hPb7riuv2CMD8uADScwDe<Lm1nt
ztkD!RyAbN^@|5%v#+y+`c7sC0EDKXdE@2rh%7ypWt0q0w#tzd_zP`@Tx;dXn!!Pxd
z9N~>LY7-@K8tZ4{CbkN7jcU-pu+BusCUl;$f7o17QG0xH)RN`|_1)AQSz<wS^c__=
z2pgH$s8}D3_bw|Rly_&I8tz5v(>vzAcK-7<k8Rmfn`~M7PlwIzIOVn0h4UVJ{JE;$
z!#kE=6mRMH-QXMZUi(_-y!f}T>4-JNr~hi*tF3R{_-beUj0;X}pM29{dw0CPc;t~c
z7l$`Z`*yzerWwnMn@?DF`(CZ4O*_1F$LfaVy>F%dY57QM@TP`_S8rL}Ft_{Kxu?Vj
zQm@|psmbL*TRXRXSMrp*md$<RYhSN@<MhAPMpNb-dwl!e*;}4@y!MeZx4%-lX#0C|
zhG_32O1*c;2h(r7;HT5yyZ!A?zjgax4}Wj!(sRe^mL4~B=lE$u#qq;mTeElGLu<Cr
zduPhk$K5w&pyA0o#y;_6&89>9zO#4IAHThK!Paf#M{L_Re$cl2$8Xv8lf4c5zV=A%
z*v*gBj;<X)e0=SA{Zs!ncGOc(kJWzg+~*D*zv4Fsz3}w)hd%$zhqW)?wYPfRhSBPM
zH@!aj1Aec(@|)ThU-__h?A*Oa>^psL)eGm|QTx|tAFkVV`1W)59KQV!;rGJL@_6Y_
zPyI&Czkl*iw?8oBkGJnRc30iNal0CGZMPQ354v^g_@_7BxqaU5!I86mSJPMf-p#4&
zp03^0@bt<@W-Ps9@4Wu$57lkmw*2s|TX#>|_R!ej+d9UN8ect^Gft1xCGQ%mPuw-$
z^wiS>M?ZDZp40X%=$bLs+tsjR#q~!$_w@2ld~3r%^}1ruk^64i1;4qv7pDJb<Bnhd
z<`a9)-a6~AXTN>)bI%^q@WSbL)ZW@#`h-%OzA9&jp1x11M{hsxu>00!C(Rz*wP<$n
z>E2z@8}*wGd2>pkdFk>(^_=CUwS8TCH}qYyJG}DT(dg1CYVu|i)bH(C8}6A^j*ZS5
zzJ13hMvA*W(HnngNqE!4%eH66J~49V_)$AHjZfWn%)m+3_Rbt$(_6D^&Hc6GTar~f
zKdY*r+MsKnGJB`xH}oC6=jJo(#%_M`n30?Bs@eY1H`;}-&t9O^rTO0-HITl_J9*t;
z=487m^H^B=BCY7C4MB6?hJ%;(-M2D()T4tvGsm-w4;c+Fy<nGm^{PiM82!RpHR=_E
zJ>IS<soZ$IHkn%=8VFZC)EAqwHx~;x_Ya>q&^r91z24Tz!$%B<JC5E}NPc>J`2J6A
zeQwv0Wi>YI*|@2;YP33E%=p7zX7<SH4SM_IceRa=q+0*Lhcd1VE}OM1|GOi{o*X`A
z&+3eqZtQKNnI+|1(c1Nju5yj(UiZ36uiIUhKB#xnm%JmVoigdlPn|S$Wxe$aL45s*
zbcUa~IBcAD@t3^T$#t>kkNHgPUk_in>aSCxm8XQkn#I-O(8ZrpH-6^YI=ekH`2593
zw5&U2R`a@3*h6TYyynij^Op?X^yR+6?_V}}`+``oabIxk6DJ*_pO||PaWfu{-RIvs
zxbB3b?U0`@>~nThc)R=Gm3laQG?u<|EBx_JmMDHgIttG_X=uqsr+D3$SZ}c3hJ{`Z
z)~CbhGtI|))k}}B^D+x>{?Yt}H4oH8&5h0Ry5m2i{L@bh{nKaGH9r^D6-P4BhPjO`
z>!McWE%sQSpVn7b`0^6Z&b<5f_|<oRD?BN2)5-OE<?)AlQ>RvWch;SC%-W&)yVneI
zD0VUCw^hrTChtb2HisuS@rzpM7qUu+d>u4Hzmo}~wHe;alZ{9Hs)Z45R?Y2X5ZNh9
zcYznuL$w4gjV;D{bJ*ONLmD$DX!JU$lex;vMB&=GDNHVl;aJm^i9{IA(xF!!Bnwu>
zIQtt$vr=I+IS8BUa-nG)NT@?o%Fbc0ft7=xf1sT$uaINNv7EEV+K_>qdHU%Nc6SR?
z=rKGakEl!6ktL3NWp}~w__m3AF_W#!8f-V=%^B@!HRX2C(3zP4{y7=llZ&E_hAvyn
zsb{5^kX(oPNNaJxG96%om+16i*e_w`qvdVGq17@y%+Xh~NY$zttwxNF29V3*dN-6+
zI#JE5M6@qt+_&pi!JPC>s=m<4o)Vw;U}hH8Eh2iDu7evN74caq_G6miR@x1zeYQb)
z#w{7j8VVy*O2~$4B4FGy*r>V)WRZ(MnUwMh*C=d<l+CC@u(VBR7P5g}OFi6VG&sB!
zGg8WeZ+zx0Yl9<IO$}9gY!H-^DoMEPu>f-B>9mF7^5ydX0t1ncfv2bW>3*uWGi&Vn
z=rDs|yQ=4A8gp@N+(!iFHrW#>ZjLR>XlBq{42vsUQ|xwlae2&F>F)mZ7Fn-NHBZ(_
zd5=@|6bTQ5qpFMHuU~n1>Ps_U+V|)8p50Gi$FI(P`0%GseP!Q=kM7(5=NER*`1XhI
z-Z{*->#q97%h&&G-`n4Lbot+I8h-eL4_^P~{_B7C!W%PwzWZ-4|KVr*#&`e6xu^c@
z<;&0d`SROddh^tMAH4C(o2UK9%YQlOgYnzG_?Mr(aQ*kc`N53$pZ&|H_q}=BvNwPB
zryG9o%A3>w<HDa${owoWUw7sHmu~pMcP^jt^NaUSd+MrJ_FlLDiVu%_dH0N;|MFdi
zT2Ulth%V;&o1dTkw`ph6DuOj-Z|EC(QkPX#;bHNxCd_fHELY7*zFJ=2Lydi=jsblY
z&5n<<U?K`fhNZf)ZyQz3rn+XOr>0|J>~xPeg;#yQGafI!Z0dC|%9^F|H>#Ts+r*O~
zvs$(>qI!t2TcKf7oQ*n;f+P!hFIGKRU)WGn-_GO8vB?kk;YzQ%F4pF?7cPt1C$kR%
z2)}2%&nfs!it2YkAHV#cAs>&Oa5J!<Xl);lB<v%w6E5@ta5GvXS`1Wz#Pu;S6}K-p
zQE9+B{G^;Qx%w9_giBp(;9Wcyz2S-0Nz7HvurU(Hbl6z#cQZPr4XY8JRhdP$1}QW0
zPuhTY3-CDIAUJ&$-ZLzK2W2Q3)<6QCwalcdEt#`#85*nz15U?nJviDh`X%ikre>3}
z;pr@Ym6f%FVCbo`C(YKLr(Wlmyjw+<<(8^M5<d`Q@So!lg2zeBg)m|Le3(qDg94>G
z$w4u0RJnlGXH<!Q0x(da&F?iyeNashGTtru%z&b}w=spjc-U@3f0Q;@y{XC@`bkA(
znPV-2Kz>w@Zt=>@u70lo%FZ;^_l;}PT5$X`waAqa*Pe|Ur2nYGomO<GoV~E4ymf~8
zUQW_zWmn1kLc0_NP$Z=)t5#*A9{GBOg9KS)89%B(QsDDoPD7ny9pvJ4CpYUQh$gSe
z)K91^6C~yrY7H;Z8`P3YlTaSHXU0HjZnPeEkrc9Gih>ztPrqXQB;3vBbyq3CJY&oP
z2nvrzHy**AazV0UFDXx#N)C}8N<cx?gh_~lLxDB-ts^o+4jIrxp|Td@`{aq0N>iC4
zx699vq!#21WO_N{nIMBf$QX%8f-6og{M#a#sAg->H<u|jU0}v7Vym&P<5B`y(Z@mX
z>5f7kQqdl4kHkfSibJ}}m;gm09`bUq2#`Y@mV3mxX22*v&#g+ybI}gBPnNJtjtwG0
z^+~ys9+~(u>u+60DJ=O=Z`@oFoUrIi@@hWphl*`f18J4+F-jjCa6SR#Hsx)l4{Ozd
z9W0R0gGt*ZYeX#5%U(X-ELjL-gtOT=q91&TtLF#8vApk!I`0w;klk4l69qy6=p-Z2
zrp>Zcpz?8=j|9slQuC3ZybguUbay@qk0~-EZ$qw0LM2x6)`}OnxTcJUt$WS}N6@hz
z7&@xXvi4Frp#^`85;RLPEJDYqe4h;@GNL&|##g@45O7-(1e=0*cr8YOe1Z(i4ftHA
z#k{jM7Wx^{*~kXvTe)-kf-8lFHgX(DQK~EfQ*7iL6_t@2TEQNf<scN}5;CXC6~SEx
zVH29;VbrKet_fuIRT>FPY-up@QVgvKA&HbX?#|;}M$1g21b`e)k(-i6L2=X(hKrR^
z3c4csXlcg6LaVZ;bH*lthl7M9AlX!IIPNB1SoZiiK*H8q>fDOAiwK%HE>Srn+pg3j
z{FoMWTJ8ih`U%huBt+d3P$I0CA5Y3^ZVW*!8JL-!SH!6cN+V4LJyV>fk$i=toMYFK
zQ-KzKS_3WuW+Jqh#N&A!S%rp{m<jM(aX=36%ZLrPp^n5~Ii4r3PN%myjEPHYY3V13
zz)2_Pm&psNBI7Ud9vHL|T49z5bU?EvL+j(~q}Z&vhPUuACaOjX8H`X9BR&=uIz<~S
zt}0emW!K+{*>dV!(Lb<aNswagha#a2s@}^N19hC3J7he-kr)-F$xR;86NTa9sBp%q
zU(YWhSj3jIWI(a%qd0l-RG09iqPTQinx8UlT!OP0)91a=sF+oOrO|hVG5SC;TfWp6
zFAv~~IHp>8Io1IgCwVB*({%-PJ_bf)g0h$@?y}FlAb~v6&I~A%P_r#{Ckj`r=haHw
z8PYVV#q^UXhq@@1qLH1WtE~=v!|S@GLUd#`?O_|pO3pm(T#q9PsDofw4MiG{$VIGH
zC)bo37A9+8dLW~so6aNJv(fQKB4m_vG5S9D0zp@awVjl%LG@YA1Z#Sg0O@8~3c3WX
zHPF<7>cfDGHYD+fdD%2;WGd6IkcbUWB#l}?-r*pxGYb^V8ViREKa}4_{d6K_t+p<1
zWxYum_Du^?-?l_;2Zv#k0_qRptLc7nYL@m9Lj%})=}Kv#rR^g19A&H0o*67sEviNx
z*_5ezFv7S5k>N%4K~aWk^N$Z9<0lT6@}m>?gg4LUZd9)w8lt^y^h8Agh$$myOjy3;
zBKle4pEzr%I!zG-e12;jNgP&0DgcHf;%KotS^-Zh)#f6l+9d-OXjbL|!W}?I8|<Y3
z(OPqJbY!Q&2zh}Rhx((U=%b)Z-tv>&9m#~aMc>62h{qbaD$URLg^t5>0rZv<>f$QN
zT?!W`_{tKSH}Fk3ZsCTl0{nekCPY;%5*4e^=#o%h<o3=g$)2X;61reI>q^#EycQu!
zZ$ahK0%Ph-aZ3h)#G-?Et!%K<1z18NH%8*YS%-w45l`_AiX_n$uyhYlCBnM%(S%B)
z*TP-7f+9B1NG_bQt&mE%yd<__TNdL&38NY-xbmh62c5#0{E|Y=fs>r2P>uD$ck4YX
z-HA}whA>Z1#CmwDiM%Yn4H8J91HR`cewJi4#4vQtXpGhbJ$tBQPgvAG$+2igZURmp
zRUmZ_{h-waHVY~(+S2@`AY4c)b{0SuCQMjGwvm`wErAsXCp3+MQYsPTgl2f)$^Mjp
z6*8t$Y|nQ=R0P3*m|m$Lfhv9^ld{VH0br%gIkh0qc6kUj)(<4u<mKi<(eSNJm6W3F
z!l+T6Bi<_hqJ$~?xUfSUSyk2~AfhEAn&7R%DIv-;6rDRAf;)%vOcx$sSC~uTcEp)<
zh|Lt5GUkUIDT&GB<Ycgv$bscbH)^!>`w$g=@PlAv9YX~cze2$sKtOsXUBD-up9(D1
z?HOEN#^r%abvkB^gu48NB_R$kT5jTp(gBC>ETCj_0O%{oF{zZ5kjU_!6u=oL&$TQm
zjU0r8o{TFnHzIf;z!)w->m*c@!U!uGo^i-sOqPimnghs9@@g%>uV>m9$eE@u?-sw%
zGDe~rRge-wKq;sYgAeg%eG9n>`mQh{*`g|CUEyIp?V5~MfgvIY3Lxbqtw@5(p;Y38
zMn*f<47@98O`%R>=NzJy%pG-*W6s{n1)c;nxDzzA7)Fh;0&-->0ef8|2wFk_qNV)W
zxeXk!nCD2-hv5@#lE{q2S8@~uaA8~nd8>yA7}*LigLQzf+R0S1{|Kz{HL}<zLlae{
z(kTl8#^9t2Qc{|-oOc*h7OaW3X9&e;IKNhgKLNwD{9p<njxidrg$O@QfqFHiCe9G8
zCA_3@0mg7)0Zs}8Uy`G;c`ke>2W)2xJ4xs^J3+95fEBgaIpZ3>%}5x!Myt@cTpkrw
z6Q8nTR}jYmpjyRm@k3YK<n3&R&m=1m>Dh!-@UclpiwBa<3>b0K9)toxO_i)%ytLs;
zVMq#1pW;Mp!W!}@OEL!{%WI!^PRb&44nh21VBGLK$F0&2fG5?7g60q4x$$~de8N1u
z$^<~5Sn*q&v~ww)hHouA82->x0*ST!MB;&Uxl>h)6_tQ5=Ry+VHsY<&lZpXKazXd3
z+<`!B_uUo2N@-jm_27~jKQtDncv;tW01^XKoE5U<kK3g;ID?8)a;C<Nq{$sXr68iG
zVow~$#JMw1g%@z>&>D9V#c=>tLo&;6f_pa>R~k%#qE%{WB3ozLsJJFHT*IgQ8zq?<
zp&(>G0&PEXencyhL0+ZpDIL)8U`DXGr{ylmJ*Sl61Su(l#AhU$a-z3f1Ozv34A+?W
zAmQM^y@JI&cOv{F#i0X`>h~wY!4nj26LiHdAqONU1jX<ATS*1qPL|`x;BmZ5pcI6E
z89@t2I9<-%KL!L%9Qm0rb7_f`ahOZ2Co;0+V8|EU_^30XWeBbV5s83x*NJ>xc9j5o
zKszf46ER_!n81fL8uL+t(^X!IK~|k`4KFU4$;fzQ0)#>MAzr{72oI<?Awxsq5i<~6
zbQKy_<>V`EMpq<ZJ*)uTr_hYGCdIajU)H98laA#A72~9fTcmF_4rS#G$w#1#Jand5
zQ!Z3WAhtd4n+gK_$aaVu6WCZ~%q3w0+%cPAi`6Tje&U3AnaB}l1)-AzQUrtG0_AAT
z$06X&okkNc|ANuU50YZ2tyB;Os#RBH1!>7Zz*JZ6$j9IcZEHoc(tveNOQe<6Tj}&G
z8HVmvry5ivu^O%NB|qgZED1?ck*Ay>P`)OWFS;VY6G0A-fs~LWv{_WL@{Pdaxf0~U
z#UX85^5zP-3euVo%4Dcgrj_J4Q64CGR&uOlLxg}e6a8+*E6<?1{>;hQ*(lNgG#W4n
zMWl!q>O*-)LSDJ+It$|{gw@8OxdjQO@Nfw`HIBTL*%|i*F=-xoi35Zm*Q6_LuvG%6
zUltNQ7f&madZf@&ZX?)6(#ZRWWuUM5b0E>mheyXsqJj^msc0JQgXbfO&M5Ww11^QF
z;8Z4y@GoS&ioVKHrvs>J#H9Q|)k;9<GZXZ!(y2;6B{*cIRFb4bLqDw{#a({3a;f+U
z(iIe?dYqe(5Ly#~vq&fS`1w&^9-hcRMEMIP2E*rx?*I`oN6wF3_6RjZI1^11Pm_T8
zi6&T}Q<N&Qj(8D2OU6=K2OA`g^o9_r+&W4m<dk;N!V(A$z{r470Yd}<CMt;Em+YNi
zd@7W4IJYkmXB1e)x~y1}LXPtC5L2eLo<$)Qi$%+dYzrz=qGlTBP_rc)==0)M^eRzi
z?627+=TiaeDGEF>(}XR)GZ2-6cy$;qZKV9NhP9blb#=O~PvoOVtlr#;iDDhLv2hCq
zE1OJvHmI{Py_j=|*qlJYSrFJDXvNr*l?_ye@6#c3E9JE`9^cDmOnhdZv8ip-EG|tA
zZBC)YdXcO_vR0B%lT*ms7?rC*U+NaJYdL$9Y$NxCM})I$Gkh_bBR9G;4765lkkG1%
zwYj;f8Hp&&#R8L%E+-6<@KanUMi}-EW`~;g4<C^_E(~rS6j`phN<?Xn=n8xs_CA%=
zCs2X~cqsE?q}w`|n%o*?<f%-rz9&&_*PxH_Xl)x~)kvQ4GAfZ{8J#>Q>);_z4XaXt
z;lo4Z)Eq<jM$M5b%#d$9jeH6?f*u=_oK<46Ouo);HYh+4u}D|;Oqe=7%AjW?3UX>i
zAyf;|Xp0={SQC(BY$UEU3c1Eo6fTqM#x$g)?c~`+GQ%pS)+UqaXCgn~wT5BJW3xh+
zh$l^y3<t8Rt`IP!qtKtJ+m@uG3ThChyxSRfm|a9WLFv<8kkla+XhPOXcp_Pu)-V=k
zqOEF*uiFqSvR}vg|G{A<o>~1h0<aSlv@SGFsd&pkJicgIygZc8yZ0td?`Vm)%!!xP
z8x3Xu_89J#_)q4vl<k&Id+Qr3!<Lrmv6hyW_3BmhWlL2UI|W}yyeIocYc_g<cU8@r
z5sNK2ES=rsne1OZZ~ie2!Tebb-8=SVGub^=fxn_5sIQ&en;DDF?j6sjt5(#Sn&WC?
zi>~io)H{~VcRf~H?i{L)WtR80FX-(x-AXO)ddv@Fr!I<hU)wu;&fdNkZ{G2G`Kqy)
z@LSln^VQMztw--#vi|VlbN2Mb`+j|NX8oQ^GY{<v>|NW&(pT<;!9ScG>v(xuJo)a-
zMN4;1UKD%wigaw}g6@lV{=;2;FHA|N$G*5I{nVMJXJ_|?@9aEu!HYXSVg76Q=wjl9
zV|%V$c2?}1KPL}9=gDIlf3@?ttFC|XbFnk8pB<~e;i#6wmYtQn_R-H~I>(oHpFVco
zRShqF^<1>MFZSW}ee*xOy8Wt0zdSs1PcVG!SiZb!N1x-jWA}#P?)B%71on$NW)84D
z@b>&n&q$EjnN8T`V;j0#c6P^>zuXZndN$X>$%%B&?*8s2JHvGUu$S)G!51Q4xT>e`
zg?h8(4@dVdA5VGH$FE=b;I4Cf-x-@9W_I*6AF}KVJzsco>Vhx)!dr0lcvD~1e|;f#
z$yFBwmwch7<@#k`2<PAT`OI}=Q`5(f#rjVEhJVX;_)WccW?#ooE^2SOZ^4cosrc~N
zC`vebg`6!ao-<li+&yM?JTyMAW8+W4-kzO{MmkiFozwh}g@;ED4@UOJVte+?j*X6f
zF$}jIyr}2-W410|G`DxrqJPTV^?F@8_{pK^#G>q?#G)@5{XF|1Bfjd}p?Y(}$==-f
z<V7QMRL?ad%et@L@lP#1BMnOyja<;Zbjq3CxhcnW?^+&iY(6g=(^)S({&UA9myOM%
z#k+6r{p@Y{9_Z>F+1k7Ish-WtUeJ#$+o49kWP4Og;dA!O_Iu^8ZpbfxD2#9Q!+~W>
zdpk07MtYh%c64+{*`-_iV{_lQA{LFFW3v6xqU>`^({r9%)YG!)LX&x_$7I$nU6i|j
z$)a>`s^xQgvgwY|6XLn&PK&39uS*A0&gstQmbPr}TiV<-(yMwRlRUV5^^$>+OVYhl
zW?sa*6?VtE`tQ$m{W)0FvMaW6>77wx&!e>2COKDhd$J>FOm@`R?A}#up?qok{Y#JN
ziS^v;m3wDYmv?lO=U}7eJTRvxzWw3u(EN34s;9%GdRk&l|Ck7xUhf&6xg(J|_F`<y
z`l(?}F|Gb}F7N-D8-!<JpC<*42|pg!7sRIpA<yo{iq&B|FP&V%nbXg_Q>~``1bf_Z
zT#!CwlD{aLRNvCHAk619yloQR9=K5ka=h?QZB7)jn|UhTEbcC4kEm0<v(~5!({<|j
zv}sn!bjBoh_NG^K2MhmZng`~l&+990J8x-;1ED!nA0|V;7#3>Q$1~B=-r#FV4)FwQ
z3ujbs%hX?N5^eER5G#?#119$PNf^e&?6B^hFg*RCC~-}EaauRc<O%qoCZn5FdgkZV
zfPPNSJUuuLmx<_tXsom=9LSHxQ@X5P>>JsjTLy}`4NGk%-Mt~JdpD@;_F^_QV8`@p
z;c)6Tn`<_PE${e}(x~k(kJ&kUmYd+A+_0|B4(AdBg-mmfb&~<U(6OX2M=c9Cs)5+b
zsIQ>oiBhgTr<Nyjtm@|qI+a|T&`X*A^s7Uvm(?exd`ZnY!~`9OU7_as%jo8ost(`q
zh^e-Fw3RbYfA}@pYD~PC(<S=PU6EGH*5`Q1MUDq32BHDm7|SxGx<8)Fw#Rc(dA(L+
zHVUGrbGlgQQ{^ZTj1F?r$Idmj+!2k?MJ+7^tn+R3*m91iy@cvt8?n#Chv*8MRGFi!
ze~dN7`gzAg7<NQv?EpPf<oAi>;42l*Q3L5X<A@jwKJ>(~xx9f&m55g1_FI+ur`5Rp
z1kY|;>Fn#3(gf&u#2X_iNz#hnn!qh@d4{+In=6_wl*BTfaq|h@^~xO0(rwy^cmnwe
zw9s*Jrei?HG7j07K^)(2(GpwDSk$UX976*QEfZXsq?xcMFe!N`C$EfUno|Ke^R#XH
z0pI`Jvla<e(z-xxtneQ5WxrfCXQ>1B-srUbW=*HefI-%`y{z@x+($!DOwPqMt75>R
zaTW1K)+y|D#WKcPp)26NT{n}RR|0}#_kGat;tlV3JH}tyzx%^y_g}y7?bYA-;BR%q
z*SzxfIQ~=j{iyaE%imo&{O-@kmb~-w_1EwF{Tbg_{?^LjYhHMN_q%_&;nDr?R()sr
zE5CT^nh!qM{kLaNdvE`{tuI~kx5r<;p7%bz`{rqn-tcbKzSrNs^q1E>b;FYVAIy00
zy8Q?3`^x)^pMCd(8@{*y%^C0Bu;1Hv&HgVhdFPoM?%n_UhOgi7)}%k&@XD8$zk9_E
zGxxvVKyCL@{<xeWx?~pI52(|_RGL%sWo7%6$t<(|VSgqpEL~W%x%@(vQ;XGDa~P%@
z8C$GdvLIL1XuPrmjZq<Y`#_<;Jj?boPFm)5hyCSbp>0cDITvK^nj1H3Pu|*EXy4+M
z5}mp9^2R0M$<Kv$=IMc5>|JV)4==HoS(P}|gsQ`vW#_PbJf}qk1O0)zx;>#%40YyQ
z0)v4sLKc3zpAi>>9C!O)7jV!o39{}ggK+VDq-^3Nsc6mrH;DQH)?Gh#(I0c$kGaJu
znyUi2RDi*iGVGPmT8@5@7^^}VJBo@8Ddt9HSz;Q|O6_Un3;^Lga}rp%Eox=t2$L{b
z6dqU?$ZOf|vMgx?Gzg`$JbYu+8bu9gMwskh79dOl_N7>O?%HCZ6t8^GClC@rL3RSn
z;!I@^-m!wfNklA=C?}dbl^SLc>E&r&apQl+2>)<81tA)cL8p!D3pJ)j+A*^y?`d{Z
zb)X;T)Pl&pkCkK3w>d+Bh*zzhjqS5oRf43vAA@y8*=kfO7vlx2+%Ku8lwM$yMztBG
z<zqgwpNe4?xgB~9C=7*-#dfm)<)(YeT9YYh1p~@3U`MVjjw6%EATmC%Ep!dc28hH%
z@UkpKYTHOSOC<c~Irqg#nMef6lNUq?L^ji%m(;!?$gf@p5x4RJqAR_lH?f%R5@{mb
zN1!0f`f;e{b5^7>w^l<{B0D6OS4taxr0|S{@V`<4nuC5Y-8z}+yHaI^JYmx-Xyg=Y
zl+|yw3MDZCe6v7j1NYe$Ed)SOK0n;Dyk(4dK>{+uyhd6iO-Km<J<)h@id?ro3`NLV
z6_y<p!O(>YW{sp5=)~G<Xj?8q$c6KDEeW((bwhgSXt^4_AQ%vTKcOM7zy!lcoj4rT
zHmHie*?<7FGUWiNX-lW1(w#z7{z;03$%=%%Ard7Ds<DeYqSDYu%}mr!WerF`H}OLV
zOQc1EVAn@!k1Y>NTo-J!rL?%(`YFMUtgdT=KU}PupkF4zjbpRKY2}sRg=!;f2LUJl
z29tCY0qe}N3}mX9MuKZ1IV<ua{E?+5sSyd<K;4>*I?)YS3F>^K0{E#mDwoxkG?Ilc
z#iM{l%hjg25-bshDAkNIdq%1G&8n278s$8ZPkzM`b9>ggP}W3a8++fdsF6jZ>I`6+
z#8EH^>v0Rd5kIYvX<wujjhzV1@g=ssEt$u4C~J>7U8fcC=!tDgYa-CtOkD^oxS(z7
z3T~O6f|qDk9_%rwF;(O(=Ts;m*+8j2EfT?gc^bJ<$~K}vHkx8~u>%Jq;MtlS9e7|C
zR>dsn=r=__T!=Oof&_FT>I`2B`yxf64n@W@wu&1x{&{halB|^FXM}ziDa0d?=fIcd
zUXidP;joK@8OaAW06voz2E+IbY|4;Aw<@iywu*O3Xd}V$OTZT{z^{Z!pkE_#us{NL
z(JWPXu4a|vFvao%Q3L}9r_Vi)%*mU7(`2>8I3NnqqFF$?Bx!V)rR>I|=sKXvto1Zp
z0ajV#qYG3^m7fVVf~)+H;6P%fvz~xZRfUMLgjcebN<at2ukm={JxOWU)|0q3D&FYM
z<~8jh&XCc}^Qb<R-4q0VJ=`;dfoUHSg9I1xr)iiajZvYwdxxleV2Vm;^$Z!MEfvbR
zOmuE5sOW+Hg3A|OT<Aqz!a}vmd0AObBBCcj0Qik$Wt6W<ks89xL=bAQkkgn1&P%8^
zL~b<WzpyDyU(%tYDtFSc&gjiq2%tOaZgiY-%6ow_R&~;Ls;YB@W8E4#+@maRzDeQx
zHc{jy;f7QRKR8(N9pY9I5qcNa*z%d@iIQklKP$TAKDr1`QH9+S&C3F!LeM6U8qdUU
zl7y*dmevuARws6yF-o8&lO{&l?pwec=!jkI8aeZ1i~@#K(3H(6qqeYgA1JM3HX-j!
zgh`7ooDg_{Im1^QR4Z#H^w804)y317mMY~bIZXeVFch!`?aN;O2ssygy$Ts-_;%mC
zZk3y*{IpU@*j1iYG`)D#JUOso5eBHtDtJg7#5XqKyD2Ie&MJG~TSxv%<-#+gyiI$)
zmZuog@P=H57^1+Ep^r8x-X>QzI_O2+JUW?Mt5jELsJ_V=AGNhULdvwJRX|?QOO~Us
z+Gml{5A2X-uYQQSP+8(@7@4%|K(X)_Ehw<miT`XlLz4PW)W%l}wT2j^DVI_!z=H`Y
z48H(g%guBWsof^Edr3pqC}Tl$9pHTK0#?qSkc3C5yST$G&C!JjO>sB~s8uwt;z`KO
zN*ghi0PKK1kh!m_c=)9fuEe@W>g$rJQwQc~=6_I)DjB%3wxXKKm4>V4Cu20)g1V0z
z;aawi7|KbG(tJFdk#KZR-elR0`I7vN1i=|_1U{B?#i=BUb1_2EDvzJI1h^Y_HmBu5
z=jV(j@dVR7k%+TBFjFSV+-eAotWqU>#I=#Iat_CrwrXJ{AgRGe`>mJ)|Ne=5f`XOP
z+?C={ZyLoGpaOY1R&p{jj*Ak)kg_3KBg&31r?hePDH5`VeDVp>5=Nx-8e$EIQU(hq
z8xvZ!5=$vzFsvb3YQptCe9v4ZDzYF5B2wvcRldR|0HJIsSdAZo*5x3<PKegF;cQk~
z^6a8|q9a5fpO}LM6ih}=o(lSuCW`|Q*YhIsaakG3TL9Do{j_l&iL6vAqXz}^6C*)a
zFd7_u2#fO5h6`ZaKjIO#1W)q=aB9@hPydh3iv6!-?^uw6y1qN>u&t!Bj&|TfmMHQW
zLgyr_ES{V@D&ex{VR3M>$}yCkU=KqI0RTA$!~hjZTj!P`mT{%0ZMI3Cgo9=Sc=iQH
zJMN6q;&GT{-0aTjyeT0@E`T+d0+{18h=D-h0=Xi(U=D?5sdyr^=vyze6clYl6L319
zenZb{3hQl@AaT{gw6bu+9;sAL17w)1GZ@q$_+S~jZN}YDV%$IqBhDdR$?GE-h~(WN
zTa{NgLmAKzHa00nhlIch6Pl)>LFHTOzg@x&7KQ#$<C+)1Go*Y4Q%<wV%m@-iYo?`?
zWP0W*gBgarY7txvB?;&Q$q;l+2>^0%bl_WLdGeJmP?Od;yP$lBXCa^VPmo+BfoBH=
z&*yhArbFBZU~$Ev<!0m}f>2r<!UPxEz7<bO2*45K_`#j3L0no|x^M9bAjp!@Drv=I
z6t_r+3Te?jQ$S%rD^=zuPWk19KTwm@lVq2zl+lw=mzg*qPyuoi3L>j2>x*gwR&&?l
z;$r0v%cNz_WF!nn1!xN%ePGhl_?^mHi8rB<b2wjnjnEt{Xp7Ia6v<7%!V0<wVQ-e)
z3_qegW7)r9?qu-`Awz1$-MUgV!UWJcY>V<LK6eETFmegYGIIeWo_-yokg|9xK`z{p
zMOK6j2p)dV`EU!16$+|eSvlJx{0gmnV6bO3xIfMh?S)`z1r~=!=9-WoNtl5ac9sjh
zgqBE0zLPxKn3WKr)F3}gxa3QGtHmimP+*PnV2y~y+vSR`2kzj0U<KbrRnC^+r5t2M
zMBqgGQFKlfB_<@sH$ql9jWyz+ETPs4H?*kae&yo^oq3(*KE-fxU`6a&oMeI_c7d3b
z2_A%BXKy6j*J2yF2n5>QESz<U%c;0Hq+TY#^F;opq7q8pTW)Bmti=#-kZ+oMB_l=|
z23$>Mv`h;xzI9!{Ft8XTO*FK?Cr+&wMk;=89|5$Cc0QXWUu%6D%WMMN_tsuwNM>F0
zWIY9vkqEE?UcibaeS5j$O|7ilrRQ=Sl5qgjlC_@TSZ<Z{jw4|$(hgtJ0A1u@xuZB@
z5|mgcU+xuPz$c{h#-daNX(=#{Hf6~}vA|)tNDL5Ik%RO#?%^k^EdTh4#^s!@R}%)Y
zgHnCwNZbH*I%K)WRhm(^!PO-fDM+QN7`Td;%mB#*5@JOmBSRS%E_VS@kCfPeS8jIx
z34M_gR4{~r2{}o6Wh@s2L3lyqtmv0gR(Ume0V~>p^k_*r7l0;75nPB0o3sn8&{fnC
z6x(F+Su>b7jzPz@$RAX}qwJ890BDG%s1(c5BqT>YldT7On%NYwR-z&+W2op7nggo@
z^3c-+ua&H8<dD07!J3M)3orJ7z<7v<c0$%zS`mblO?V`f6z&=&oypJyxK!epq~(mr
ze=?pIeI)xD!vv!s{Yb?=)Pa<V3S6CWHWPO#n}$8QP2K{lR2hGYtj^*t06UI`EM5{V
z?N)ho^=+F-CW!?EhZ{W+>m;tMOz2dNB}}Fx+@ue$=s0&8q-Ax@LBh&SE8k!SbOm>o
z1X+FrYq<jnku=pS&=yH71j@Qg?%HL~)g@9QRoF?D37`##vXZ5bTzmtQlCkASn7eWb
z_z^7iXeF##((_A5l;+Qfe*#3#y%`LLC5fa|iqWHA4lIGJzbM8uIDmSHijDOL@d&n-
zY`9zeKqY_t0vrQKI$ll1XO$5=8QOm=bBWVV%XB4cCZ*ONs^CD+SKkJsjbBDc8sjp7
zK;=A<@#~68YnxRNH(;ruVVok{N?H8wTS+Fg+X(T?cq$Ph3&F&1n_Vai;GUx{s7}Q#
zbWm4OVC|~NmntiQEsqYm^g>PtMtQywIks-aj~S5*MiEW3$ma@hLDWb~2bK((4Ew5V
zCiqkUuQ^bP00$|d4cu4>p|q8zQ`VG~_9dA*FkA&!%<Lc}ft*~(N>5M|^^gVT&WcPN
z4k1GXJ2F>H=#!*6K-c1O<+Vzk6CqwBu`b>>)@A5CCDuh~J7n&rgUXVt10&^A+Pc;y
zAzCiPlh##DPHu+NHP9i<NGy<&dKdaye7GTFyCfmdVsetUTF&Xj-jRg#m+Yajcfss?
zif5~H^7L0bUmbWNv`s@CU;-&(uzCh0n=orj5F?8b-V~T)%i61xh28{qt~Ly+N<nK_
zVmv^iT&(D;BZ^gvr3u4J&;~D6MQmqa6$8o6t%+=Ka**%_JGA#nr7j3`xvi~e5|$;;
zgP3{6v-5)40nd=J@Nr0}zP&!Jvh@rw0^ZAi5zRbhyDS}1l?v{;zk@>ZYW!b??E%k&
zc}W7(Ml}_NjOy~jQ8klI?M22Mt&oZj3yZb#FG!kXn=!lvN;S7x<p()G(rKdO=0*d<
zGkFyR8eA1-!XIkg8rGMp3+>7d1!_y(CG-8EMVLIwq}-XOnLW5<R+H@2K{-&0hsxIS
z?KoPt;e)fRrm6f^c@evGQ)H^_0=3<gR9dyRVv8Gtk+ZFp_hEMFl1j*u)hTKR^&IF@
zD=baU_j&TPZ*$D|I;k<%pfvhQ7clfM4{%7a-q4~{8z<!3Y?CY*u#^?VYjTE4%WBik
zq$a&KY>WKZ-3fRY<|Vk*o7t4&SxRqi+Lq5VtS8wnc}}pkca!Qm;Vz@v4b!2>l<KV)
z<Rb6xPj2;l2RF7&GGV!Vf-yF*D!Mf_<mIpzU5VU!Pth+K<$XG-^K907_3Ql{V)U+1
zT|)-TD0Z63`yq1Vw6|Fn%yk!5q7-&}RSW^GRte+FnVaSxE0xEf_+4E!<;Pd7o_q7M
zWpj6qJyIU}-YuigJhOW4l%I6OXa4k`Mt||A)#eGlU3bVs9r2pv^757~E3$pReLSrB
z&8aOlcXgz5uRfm5jxG-UQ>MpiZkXQl+N-ZFdu(q~)t-AxP;<+aMOVLl#q!*qQN6mM
zA#p~-jHR#fExUoG{mrXZH>lb(8kS$OC)aW5vi_}At7}JAudbbY$yk5O%#PmepZ|5k
z$h_az&P|MEgx?ovEu)YB$qN&wEE?PP_Gx3!?)}asH;*)o{^q}q+wknZe~&-A@0<Nw
zUVdkI<z0O{{_EX_k^lbn>K(ry{SLps^qz6u<n8lrSYs~RyL!j`oyYW^cX92`^L94$
zZh!el8@BKK`s+_Ds@naF>t`<Nx&FBAJ-?jM`}^@j$1nfz`K3?oowfIworlkT=bh7b
zzjMuX$xGjxH+K0&=U+SXy{hXkyY}zye|7m;$={DxB`^Q;q~xXlcJBD)@1MKu@(<4y
zeouTrsi*$=!?Vl3|FCY~FGpV<o3dw2O&^(6zPWr{AwBl#Fj)2<ncAObhR=9l=c3!5
zTamr>?aAgBqu=G%+Iz<SXSdHk>51<7FW<Cv{_|h!J#W#Z9p|-FFM9Hr)f=AtpsMeQ
zg+J+EJ#B9GkYAoQa=}xxmR&x+VCV10F7K&&`K*!0->yr&^W|eUz4Mi$m(85_kENMk
zK7IVC_ZN;G^}e_J@h_d<|M+zaH(h@J%Y`%UTe#=)w=Q0K)UK&=rs=ZHG^Zy%7n&oN
zhhtlps{SXi=}+Cob9Xz}6`q~*?M(MW>-#_R{JLdZf4!o2+xtH-&+a)UQ@yjUF!;Gi
zJ9<8IbB}p$Q}*#!b?=jx+_NM7tJ+w4{n^8&`O4m&iyQV9ulr<QwCL)sO^c@X&VQw9
zBz@PR=`%Jg-d%myltt10GdFGh)>ry}aq%g|)!XaRkBywQZ1i&rm%a1i!jTL1oEpr(
zx<0(@(a)O8-}`3&>b`Jns4pFMuSdGYe;2-g|5rBN@{e^c3mzNUkuPMza<?&Cv#s{@
z>=A{!jhi#yN~Csn<zCxfGdj8>*!=J1V9&p7OJDrO-sb!jJDNu}XFGe^wl>9%=$#)s
zX-9hf6`{#4-gf#$%X*vQ%lAZ!a(&Ux#P%njZ_ExoKXt3W?uvBv?bEg&GLSU$2j=dc
zfA$s0VDjhtS6|vQ_W!W={&7+jSHkzXckVQoVT3#5fCC{~)3(?W)-;Gp43E|{t!W6s
z2HAwD8yh5q7^B3nhBYWPO$#mIaa$#Z7~f5c#E`6;MdKQF<0cIvl4!C-U85T}j!KNb
z5{VMUi12<-_29budH3DV^ZxywnZCE`)Twh$o%&t3Zr#eKOZzrG(!cMX#{=CrH1~0l
z%@cNv-E-omu~NBoVbAV+#`gT=lp^&rjw%cH^i+Ch)pv})zWD6&Xxi#a_w+Vz8`InT
z%VAOV3(n3c49`R__DxMK{6Rdh{DuwrXC^P+{;jWH+JC}#YW;=2!9~||3hvc+x`kJ7
z>ao9>==v9bW8dc8Blcxx-&R~W^81^w{e5o!@sniP!orf>{fjGWChnRk(M!kMvwzww
zKd?Ao<=m7?-^m@WKXrU1c>GH}L05A_ymbKG{CD?~{Pah9!ruJuaOn$@U$$|YoBGH$
z*H~SR`fiJ4;oeNNaNwTknPl6*q|Ncb)O{Iy!ar`dw|!@J|H4{4W8r`-{EKHL_<V!?
zkelma|38*9lWwz{x1CfrcmCP#bTqiE?QA|L`e&75V487Y22zEeK6g&^QhD&&&+eUY
z?WZ?4``4V=?ECI2o4xq6=Y;27?ACN1U?5Y{Jx~2l(JM)5uqLIl1X6Y)FF1DcR$biK
z@IcQqvCJ-4E$`tMXye0$gOOuAk(dG6VeRGnm`U~7V7{rjWs`P?<xP8Jvuo&3MLL}e
zJ8R7#n%Iacchmzq`A{m11ezJXxwhU$;ls9EZZsD+Is?{MVYYKe%1L^?+%r#PN3bSo
z%9<W4(S<IsO$G<MVY)!~Jc)75-H|KR#0=JK?_iatYy+w@AZ)CcXpl~3z%Z!Kn(`LH
zo}rg%?2$sF!hOAw#sD<*!iLQ!<_W_bBx1iaVO23(oQVgsCTcJ^YB)Lzgh}Mwrk=3l
zwq?-JHx5F(Jd!nogB(gF;_7R!K_^??5(>K&V$N?2leiIvMX+;q&l3|ao_}!PMK{J+
zI?Cv~sC2W^&Y0JTWCHrIex@aa1)*#X%OE{iA5UZ!zM?R1LmSD5)dlpUMeRzH)Q+q$
zqDZu3YAVkTqvOXuh)ugZ!mH?!Sk!a3s7S&jo0-g2DtyEX;h`hWe}L|J`mewf5V}r!
zc5y>NPvmm8XPlGj`#Yi{@dq%|Z)iPOr%P9J(y%AQxuuy%mn4GYQ6w8>_<D+%x>Ws;
z-!ajT*{hW)Soey&a`@###Jy9`c{10E9DIA`p*MbY@b4e}m(zam<Zs{JfAG<(58eCr
z;<b<b%iG_0;<tz2*#FDR5B=!rOCP-P)jxghi8l`)+W*UQfAq$$PJHm6R(=24-Jf~#
z(EdlS{?XkJeQE8FSAFBbx4!hw;k|EPecWpgo%jzw{Oy|${%+M<hrf6D>SOO-b^7SH
ze)H&OUcK_kReyi@(-*z=`Lo8p^_!cn_}!aNuDau$gBShq^3%_I>oY&R;*~d_zGnX?
zMZW*}doOtL@^8L=@XgB)*N!gqnHzO%m^5?`(fSc3>X4kuxsh9=qXrxGFc_!}8wjv^
z%z0bRweK8oYiifBwZtY#d3Y{xm1bU6Yre#M@h<6pz~$zyZFA@GVYM+qr&I=*t@gWm
zP>LGi6H%NhB|ZH+$8I)p@8FJVs_0lcVC#;{xxk$w<ilwT?6793dZK&(txQPo)6$aJ
zT5|2KJ2D)a`5sVxk@{{<`XFBdP?s{(0*ZZWzRvAG6^~YMq_l}`dERq%jh4s02d7TY
z4r?4iQ-O|v2Dv{T@wM(|Aj8J6)Pic&^ywZG7Z`E2kNxY6my>xUsh9C@8wHzlHY%ev
zQVjFJg|!Q#LSWz-*!e-1Th~ZAC;T@-g_C72H6`Romy`*hpe)vS134>BI+{*rGmLL_
zTVTDv082xZS)t?@{c7&cH!=J9Xetylt0CsPnhOm?ve6ZqQJj&q6;w1%-z~N@{jsx0
z_=M=MYkS>UnyEzYNN?cWhO$XHO<Zhul0|$fCl^@s+)ZmHKu$<sM`zGDnR_l`4Md+h
zuo_dfp&J{~9LV+wMd_R(vZ*5@BTLX9MZ8cKT>`b+y|4<Uu8mHR2{g}ATnze4!%1*d
z)COmrH|F(82Vk!=dX<9s6vT?t2_#%R@M#q3E;HrJqAx#7R`4;ENKAz$DB_!bP3H+|
zn)IH8O~w^C+C|3j#sZv>Z^e8iCcGiyuqmXTee69pG>%1zK%z$MpjJMP9!E|n>R23i
zhHF!uKpVfXh9X^20}DoFCuoEKQv5!qQ(`%c0`8dAz%Jyj(9ddD!dZM#iq+2mg%oHz
zbzRI!{0KP}v1b4zX_J5*1U#kWv#%Q?t9CWc(EJ8dorQJ16lEbQx-|RU*aFj9FRdYo
z4K+<ddU~iS&N_))JP<aVreS;Hq?jp`P?<v2WR6N2I6v3nCEQRydnk(}JVFPeFavBe
zlodiF&^C<GTxe>UBQb|6WgUb{hQ-Klwc5lEyE(wWRqarY#A-7gCxiXWzX-NAEo7g-
zO_y~h$QUarjn7mPOBv<y=Mf!wM-+HH)ON!=c$zwi`M31gK?{O1Sw*r7BhEJwKJ)Hv
zo!(*iqOaxbVgpei1Cie=vQWDql=o^<M*TBQ7P(1&UG3jGc$!B&sZ&T7%(;YtFSz&?
zVanljBE$=$JY4D+3OrLsI1y;^gwBKkT^vp-pq6}gV&v%XB`~-%lns_*+9>!~K-weX
z@#3{az0%ElLJq8|r)4u?Ehg0blo0+!6-(NP2ddH{f-7xE$mzx&%cBU&g@;DS&4eX4
zlIRvU<(aGQogjV`M9lTY7>{&$jc-hq+$aWGP$YoNSiuE9x=5aY(@N#U%~PDV?l4dK
zqS`>l8Lu&B*`3!tPr0=MjV38Rn-w*b4e@hxQzN1kByzg^Nvx;?<-M65Xe!sK${es1
zZY`Km!AX{{>6X131VBv28>3Y!8qi&rb+8PhlJA;`RT>qe(s`_vQ^s1|oNhMZo(eQ9
zB66#Gl17F+j^c0xSXoOMyG6C@)-fgLSslrGjmh?M9*=k~+7Pm-8fi*^*g*GvN5-kZ
zyh@uwTKj0HLfhg_eR4iaiUb(G|E6f@dP7PKC=Ek|u8ecLGl$O^#UZ0C*1Ja5<Ob`{
zd8$Pf;>L6745FlJhOZ+gs!)a|I2^V!Ax3bN;W(Dz5b8fin=a!{5sBK$E~6|nU4@D)
zA#^wT11?U2a5&`{cf?7J72Ualk>n)TuD#aZZp;kON%7?z4wfs6Tfoi~7JouG<a;T)
zEZopML}Z?m;Z}@Bbrq7Et*U+^MH}Q8>q<MHQEkV+5F4W>iMEb(hPVw0<~~nLz&zZI
z#IXKlsC7Ig@4&{VIxZQRlX1aliSps8m_6^bUT8CXTY-vWW@>qg-MR%j$`#rwhQUE~
zeI;YUIPJtGx~FN}K{PWKv4;A)b1CzMZCRDARjND3t<hDgN>KH6EvvcoXpb27$~%-s
zYavksR%jEmT33MK;^tVh=6eIu{u_=aa~!D}b;fRe;@}(asZbnx*?JTfI_=m#8LjO-
zdki&uf>NE=8O6!9v@M1fexz7yiPskxS5f9&Np}r($6QaLAIGZ*2Kgl`;Za5DX-Ifp
zuQe0OIY;MRuEx8=i@Y7Ji7aQ1^q5A6Ys*aHbXKwldsm&%GR>wT=n^X#iqdBGUPZjs
z(d%>r4O!D3nL5hSFmrr5!gx|OKw3M3rhib=`UczGyHMRds7BLXR7;v(^(Q>JK|OUT
zB=IK9<sq;^%VDvg!)eu?0MXnU%LTV5rZC|=!bACKukFhxmV=AMr}R#<qvff16pBP8
zF+{cmS>?B$C_0kBT~?EOq_SfpHr2=n=*5a}n`5ie8j)C&mXe~4&NCDeXI+76>k_%5
z2fv~%zbF(+6b=edSpqXOb3(R+i@3%r1iL3EK60#5(GF2sTcA8(3R3s(=r*$!n4l&T
z;0ri2B;Wg5$~f54JA__7oSD@S+0bc0kIU<Z-}VuSuE}_Wky7_?B?Ct!HC`F#@GZOp
z13$!gi6>F}A#uG~ueNg3Bx*UgUKM8FN>Ni>-N*BM)T;wit7aCTz1l|bu}YHH(!i@B
zhS&qNL*8fY0L!Qvf&FBW<IayJmh*?LOvEb{y#TO*w?e1`yGZ*`W}J&e{_ZQ9W@YD;
z%z$Q`?Z@YA8N%mL1S$*lJE)bGf8Uj`>%a=>Ccu+>w6ZrEL)-wo*$eg_P_iNOD~U_s
zg<2K(M@mK~vIrVqaFY-VY76f*54Bhw0nz|D!9xg@NtJSzyW%JhdQ&@Uez7$XAE`T%
z^I97Wh)}Outy=0++iR_q#-TN|7d~3QHxX<g)kre$L@pZSwA{fP-D`<dBF89h6Q~wc
z;cC1d-VcR`vTEkw#jgY0kuwM!V;()~k7>8e@U&W6;BPu1a!AyO{${ypkFSM@{zZMQ
zFkFgO{$YTF)ek-1B%q23`%67U&{Oi2LkOLR;5yp#EY5kvXZ&htW{K`W(QweJ!V5Ws
z*Km|W>&+JMECDHLi7XtY1n(4eRzdv=mj8%;62-i^6{j#ug$Ml9sNLLEYtHZ`o~B50
z9cs&mo=~?A+HRvF>Cg_~8FNDO=D}*20a}%pL`hM{J7m1(5P*IT?@$rY0)Zf3i%BHz
z20t-6C^f2qqL{uYgjSzjrlr$Udz2R+|H8Yi=yoR}L{|L)Va8C!)bKv}VTf0OB&n5-
z;F$**)Ma-hLWc-o#3&uC8*Z#qqXqnq0Qu;Yww=rbe7U1x#R<O5O+_dRT<9K$n{hPx
zDZ;}<2>$6*qI#dj;o7-EenczNP{YRUh|#9l#!aJKIm^|(+nDgyn~&2$fI@~Eh0-cM
za8>j}cur+(fI*;R8ygrAKfd>>xPnh|Xh~7Sw&D`53`}Ig|J@qUsayxLt|4|bNn!@q
zW<2>&5CKkzgT=HAwOX%|e`tLzAypP6A?dOx6yeaH2dAS?BKl#D#~3!A8?~8LZ!BiJ
z-YM`z#l$EYnVO<hs{jRi)RrIntTJVEpb4g|X~DI4fK2O_h{d5z0BvpyrE*n->aH;z
zWtA)J#5g*JfXbwG4~U$nRj1`gVR77WxFLr|@~nK~;Mp2X*dSQ1AqpTVfk}ff(h_JL
z1S)#LpVg~s;el@k863`gB*GE3oGl@+QivQEAQ<3c_|^DXqUAhSYN(HumZ}CaaF@sh
zz9K@T(BAN}RelMtLXVF8X$?psX{vNs1COQ;LblpkB>?%VHeK&(ZHk^1#3W-ec+yH`
zRe&F0{neYtsi)JCpGJkC@Vl25F<d}#ECfKE*J4<PkC*o@Cr7>Tu_0p13N~T&NIx~>
zA<H$bE+P|TGupCDQUqZ1LR{nkPA^5vCDTG^HBxV4xabc+w$%vP7CCN+lyg-b7DtOx
z_sn`O229|IorVoHVmJ}#jjgtvyTbe5y|nst&l;Rnye_2RDB}zRu|{Q%v(Dj1AD7dc
z_6Dj!y=7`ed2I?hVzVti?*^r8#S?h6Z-ANa90A{3IMh9YXc-CSOlmz?+L5s3@_mIm
z4O3=<BhS+5yB}83M>+)^jyOfAo)|YW>H%q6jPTeNhVTJGv=!{r1PNJeNOPd+^TQBD
zy$jmbD8#yl<gM*0#i-Q{4+@=^;BC#^5N|;VTa}*yi-!A>0li5R<h1%lI9gzw#-|b}
ztys4ZUuj5#mRRaOjZGRFqf#ML3zhjL16=fe<f4AUwY!K(v?fojHIx#>GI<4QGK4#V
z1}qm+o)KSN$#%(Uq;?U5MIw#QI7ii0O7*G=ll9)O7foA^&Vtd48ebeas)Gz<;I1iw
zr_+8G=!D*S6+;((<$N$~k-$2dp|03tbh?mJtlF7sawKEDcq=@ya8(L8E*Qmh6hzb1
zXRtdaR~Z`SvMnQNS5(0-)4?g8U!5Po^d$0WQQJDBx&uX#8#3yk_R$rfX)u(X;0%&1
zb5nSGlk*O$AD9q{{}ACmjf4+3i1I71s+{rEv~8{>CDiI~X$eh|;*J_QgD5bhLI7MX
zP<pF7ys(=xC*0XqP^CmXg*^YdI$XkSL&YdD*6^Tq<XwLS4a>s9s>i(B*3y$IBGSix
zU|Zn%WKa*#Mv)Q`IxW&eRno+P?q$cTpuKPvLIya>3ypOuWR4IcZ8$w>5_-*i43#v{
za%l`LEdb--{|rXGHKQi-mi98Vgi&C|@N7XLu&6<D<G`n+rIBe-YD7)1<Hnf8tE+Bf
zH2{}oEFPqhu6__Gpi6#)49UwV-cRfz`2-{B3;`avMZx4!QKB9AjqZ7(2k9vdP~><l
zN@2`!9*?g5R149T;dJuhyb=THs9NikElGDfhZ)pE*!ReI#}Kf+UhVbGf{S{jqt3pe
zGIoX8?MZUOFD8*z7O{9%f-KVd9fQs$=ntgyy=-TYv>QJkN17<lZY!l|cd;vA-Kmp7
z@wDwbNq-!)p<SHo)UxVEpOEct?-y(CBhdlx3{20u;ooAVs-08No5o^J(rwto${M@2
zyFgD8*`<>s*UfgS??g38v$>{!dCUuvkyTq}+IKW(q=X?<#cF$1su`rmZfsDs6~c=Q
zdU`UlE@r;fGk4QOt==&$fgygrKsTr*b*b9&^nD@)7i_7?=0b_L79p&W^!4QO-F(z?
zd@m)QbxkH$L3c+`U_UK|!i9}QuJ4`H6=X)z-(1K-Ozg%~lc2B6`V24Hvd@n4pOeyj
z<d_xW)=|%ok}gi3k|0--En6KEeA5M$x5-JjXLVJc3JZoZ+_jxHxHAfqb{#AGhB2A?
zY1_u(=_Q$2rUbd5^IGZdIw=ZfZR-ftcAb+=GQe|*LR+^zsxxL@%q}n*75fQmB}FzC
zv-LiGUXw4`F2l-WAEJ{CYufrMj0vwRIN{SyVc1U*Am0*JaAz{6%jcqwc${q6b~cv!
zU-)ZVL#vDPg-Ga1to`$5*R}rJb)ULZXU3s*^?$qBHP^10R$n=7S~6|LVDqQ<OX;<>
zy~*^I<H7B8lUMJp|JD7y$+YSGRz8+|fi3=%x5qulo;kj!cl!Kf`Dd>v{eiP`&OCN}
zGVa)wrTxne?AgCi<o(BWCTAUcVX}X@;#}MNM^%r0|ESJof3;#x=}*h#reltCM;|jP
zYdOb>U%{;%wlg_q*m#p$*(oa*>~cFs6`Es)Z7u!dk97}G*R3MY=JVm!<i2~imJW>D
zy65dNcbES8oBQ@1I9=xb`!{CKd;6w?$v@q(!Hpd=t$xAD%j#F1wRPWXr_|-k7d_VX
z;RkQ+nzsF6_o1&XNY1_Ns^ri`SCxMC<&E;?FF!Twol%$WIe7BkJqIV2k~x<z=>GMp
zCvN!n5l{W%o%Fu*-??b%@~el9Y_7WCl0ApdO1clNvdybLvB<si(OJ!RLVM-a?>~Rh
z72zfBzKc$F_np7gU3JdZ<m(ryz8eqm-8FMXYESZk8@K%8lGK*DD@JZj#$I%w^!m}(
z{^_R9()qXCDj&YF>W1Gmy}s=2W%W<a+P3HI^B$9hA9cZ$7k4LT?X0=6N0*YNGZvM8
zdcmUPPZvEQ7hLw#yjSMU-m{-`iQbuG<??)Q_Z#OP=zntJfv%r@Zh!t@+wNumE1Ed(
z>N7g_{Mm;~-8auE%2oNL?yaEEJlsFH?1N*@FXyDg-B&!v-Fv~}<`r{A{xD7V4!!zo
zk@L&lvclbS^FCQPZmZmO%T^ieE$_)6Q!D+UcSHXlmM!nUXU(m)<I!!+^KNg{`!|)7
zCy!p>vL77pjy^lG!|hHhuf@qjBR9FLK5-~1pKj|x+he6K|JjA5;wZ{?M@b$UcHkG^
z`Ku>pe0}a?-PO_)$!GaiOm@V{GvfE<!wWyK#ofAKj+uFGx$<(q4ga=OPFBtuoXs~2
zn}79*-^<eTJIXVQcd2gf3#<f`7pUHk&0V-+>fB`AQkPWzAbmGB+`P7>^%?WBcILd@
zcHy$fj$2-}Bc8q0w!L=Wo<-?R$yM{BdhXou^&r0>376TVG_H{RVqPrI%-EDH8o4LD
zuK1K(Gwmt)?9vMpJ1!k|PJAKx`m_W6>vIRr+fXc44%pq{v~WxRB<X1Dy=t9Z-bCl0
z=9kU1mzK8BEJ;E4JT17Ia{^Sy`nChLuWtG0jqTh1ucwl2KkrE<o-bV!IezW2s!jIo
zNy{T!CnOIA@xa7u>56%_TzjG@8?VdOzx#KY<m<ULoUr%Z<d*JP_Lk|3>_1*==cRYc
zo-?+HJn?r?_klYz-KQRFlCBSYxAgw$-z$xt)R8~)>z#7uq}i@_Z=u;aI#v7EY)9=k
z)6&iNO;6?DzfyJk>uW@2%F2^JmcQ__C+geYY$o-moz!=t`|KV$sZbnUur{&#nzH3U
zD$q}1#<wwi8su??rSl0U1sjJO`OdbKxE_A#C8f#PIkvunjs3P@*)Y;QXhiH?9m%F~
z4e9IN#2D?4ybMY+TOMhT-)(vKz8IRV3@}d#<pJ8=5i6?p1JgR>11mrJ7Yq(<VdC%N
zOFytC{7tzxa2w-ly~(*h{krF=*lxzzYcsQHZJP_uHuWA^?O1N9N7dsmjITvf@ThCh
z$E9zWysab1I?IqNEAb>5=vW^oZaqgFWG90AuH1OSv-*AVWc&-JJNZt7eP1q+hTItS
z>6-SOc|qI}_B7}#2lRPzXa0m{PxrKJV~6P+8Fo#|*ft|!F6Ym2q8ttj$M@Y9>hm_<
zsO*t_al7o1ekpZEj71D-ukw&}z%)C9E)FZ|OQO+z&G-hId|Gdvm0+;mjzD@}5Owms
zkwCDA)WDg5A4v1v_XUoJagOj!CZx0LmO&S?<B7Rv1dDvdG#bL<i{<05_!*>SE1afQ
zWxvs8p=yKEJxy0WF7mCm_(PQr$uVQhz>jBgF*kKF0g}ZmXX6U%CJZ=)$5a~$reSnb
z1F!eRQN7Mrux8=rNDI0kMxl(j#G+<aERRlQa?W_#q$_m8Xu!LRY&T0dzft28q02I6
zD@(IW$0eAnkAz2(RK#WM(FF%%k*R_1X*&NGL?O>=&AjKRzW)y9M7J^y%)MZp+X#&-
zR=%~ckd%w2Ndf{MWdvu?dGplB<T@-i-zviwFw&&&9?P&TNES8s<+EW|fv3tBW|Q7>
zb*dlVb%rUOX%&kHKK=F^D_?){Fucd>o~I|i^y4=Ue*ag8f5f-z{^{vA+nzZ6R|gM1
z`WLGXy><C7Z~2QKer)%NPaa-*)8T6lJ-O<bKfUtyz>}xHb@<>-tFAfi$tyo{%hiAS
z>d#g^dFbFxE6=+7C#Mhl=G8Yo@GqyobIql{T6xi*esax;zgqt0gCD#5=~X9xbLB<<
zbip;Fp4|WD!h^5<`>G#*<It#o`}{TMy|w(8pFeo_)vL~Ya{s7roV%*+t;IiHrh9~b
zw?X7rpMPWc&%XELFH9oYaj7qMX9sN}gQl}C<=P(B_WFbOXWRKSQfUMW_if=5bJN4(
z_A^TH!26P3cXV5m@kqHqwgzl&33~HAjMFezT;&~(Sl33nx&w}RkFg;iN@lUGR0<x}
zxn!6eOTFMZY9!8fj<2VaRLN8*P4i9EJ)SXL&!|K`pKO6!H5?PEzK1`p1G!1kY2TB*
zmJ<E{1R=%Ze*|g=<;VRey7$H#a+m)T0iORV(*9S1Soe?|c#oPwHJ7L_u_a4sU_2<>
z@zbtQx*3}B&8?>33J5bjl8fbRo-8MQy@@?q^`q9gYG|2mvaaH&(445C&)V9PrqS>c
zF`aRYDs3>ZUKl?+hVPbHt`6&|MPxuGY$Kl-R~nr^Su)(2$cbT9#DemNVMNjtj&qsR
zBl20T!hu1S75norbdL9|&;ymHgbVDVTvt3Wo1ydYtTd+7^RiS~Xo~rTalx;dZn9D#
zy5ZqAZHgoBV3N_~U><f{5G4E$PU&VutgoKY7|n+T*gQ9RqRYrYL2QKEP60n$?fUU6
zG>rB`3tbT4E~(JOw|-R(8^G&mph&E?5BLB|8dAC<m~}CgclzQCVA)Bk^By8-4sgZ*
zZWu%C<58anz<4l$U{hFOQALzhPvT4Du#8mL6xuX~00rg+oFv;vqEG>DL}MQdc$6kP
zQ9QW>@fJ=7ofP!pHHD#HBPc0pvp85kb{Z_nW@Y5WStF7bhe^cXj|@#a?(uZNo|To*
zDF^N${5hQjyPZpO>t?hF1dUa$wGOsK_4PJ~DLZjn_GmT{u5hD?Xa+z{3E567c5JT$
z3-4N}ajDlX*1FGR%&M2>-5NrSYv~`#tujD@Srh`}`udQjQw?1t!r2`<LnJ~fTq4)f
zCQWb@Dg!<TXGkMs9)6bDRp=~h6`_2^2?UBPHYmaAJLp;{PzokFkZ;lBkM$>(@)=d&
zr*Q@s7hnLOxK9d+(5Ky+7d9fk^yH0(Q=**pj@D&Qm(e8>+x{-@l9M?<@KZje@8bS@
zN6VzG>;FWh;r|omf5+qhYrOxC-~SQb{SVad4S&}?YvFrip}!`9_mA|dHg;4cia4W*
z)tYnd<|B!5^JGnHxtvZ{jFOg;S=<Inyj|5yMJ)dlQzBP&Erwai`}_|2JNt}O6Ps*Y
zByF>@J!HB9)lVyRUGja5BcxiM*+=PvM^x<^;re=1Dcz=$g0CDel=EFI>Fua(4QRl4
zIu+QMDgvCQbYQv@yVV4h5^sxb6jNxoJK6P9;$%#kz!C5bD62+v(rt`aktgGZagNOU
zc^t&w3M^HEzM@1Qp?nL{7gY><Fs15z31(iTRgsEhS>|a*q^aroj9bLM$VNVyoMPQ5
zNm6RVx1NJCUdE-J(N!~AGf+$a{5ow6X~A^ufJF|fafO~k;>r0qzMTb}Jc~>+ss4QA
zn5-DGC9t^^db9jHoM)<4iALwe*2Ij#CShI8Crdlg+1aG6Pgs~rswD|$iB0u2Y~_oa
zSg($#jL8^@B4>EiL~ECp9Sv#UAtTmAG=2<3Wb!d4Csqu9wi;-X=4yK|;-sbw?;Vr1
zt#$T~YCe?M|7fVn-8(2H<(=*Qi&+EUOV1fzk&8ECWq71%bs3tHu*d~{;v~sSCCSs)
zxldatCjFe1oFK7nLjEn<QZeA*F-tq@&gw94<A|;cTT=)UheE@nT#AN#GHw2*d0Um<
z+xR6MaaO(mKm2D4xc}@W6aLSjAruJR|M<lxk3=L(gi@hU3@8UVT5ilQJyqTlWk)6W
zvA$y?pOtQ>r4-;8z^#KJ!=180u_t58>Y=buh$(P7zOsXg(88CZG&r&9p}N+kK{=t~
z_T#67NKu#N;2TL&GOCn;IU7rn#<UE-leDEqs78h#QF;6XBB1NWAGLIif-dx+d});4
zZY}_0f*j3UpuALus%mwbWkmWy4l)C4bfi-zoYtzMc$}mPm(oX;o6(NYk`DOO$sIEl
zmo(w$7ygl`L4YxBYGZZL6fk75v<YJIw{t<5CJz-_Rl+4w&Vx6)b|`bD8uNaQr`9xU
zgGG1Qg7I+qs&^(uWCfwcLs~s*k|Pmn${x8Sj|>D1%X6s`iXKW6l}V^~scb5;PYGE^
zTS{vX4>zJM1Q~AAw$Bf#oEVJ+(hmL9hkKEw@$pzg0MO3QU{lLI5_<-8kkF_^d8fF3
z39Cei#F2UU(PMIh8#p)uJj7flQ8!FTlcg=dhIW*Op#Bz3M`*oA_xl-Kj8EduglSS!
zJ-Q2q!h;;X(23Xbgv5xYuQRhLH3>#6OU$k?_&6z<W>Or6LzRiZ@n(W*#*%$(|2J5r
z>&UZm+aNIkI!rQ(_107NC0v@iHj9)TB}3C;`CUgGqdK?xRXdh)ZQ>w@9}`W`bDr6E
zQ=V%m!o=0~Q`FH0zeJ`wh-eQ5zI?zz7&uZ?5g1~#Ag?M)dRh-xBoJ0Hh9RYmtRb~Q
zDngAgO%N5?YA0w<Qql&>azv0DY1wPUGYWL|Hfrh~)9%-OvS23G^%kJLq=8Y|q{)nn
zh=ut+)sAp-{%ll;=SU63EY9dgKBN#U-+o9J+N3|Fy$Lqp=a{HWWZ$i``6P{!k1SBF
zLn-!IUFQ#%dP)gbGib1+pVFg^kD!$F#f3grEK6MkF^Z8c)-=?q|B~kCaCFA(vc)b4
zb6S83ao9=0H{ilOT#n+W*%VlkxL87iuPVG~%^kN|N~>nAh(F@jMbY5cvvdO-)S(sU
zLhw+N)bT+^CG+-RKF%t+hgkRY9p>FefCk9}nku-~kVESh!iJFGlg>&a7Kd`>rs4%X
z$YSYNw*ur1r%kN|ZF|teYtrz6Ll@1&ipE1xCJ#q~j_`0WHy{(tT}|VlJRqip<YqOL
z;fP16BHpDwq-&)(;x|Oa>jmH@qB<GHbA`$&=OLi@Yq-z<Ayn%I1xYdnpGKB`wc7`u
zJ`xqY<xfqZ_m*rv;q3EH^>EBh%n@pDOQ>ASXtfqz%N#WrQzMLjOl~1+(ZJWLiH!GK
zl(AZ;6tEvIA^>%NHR4;xcQeg;EF{*O#I?Lb*W8gnhNoVocSA9nW_xIlVAS&-H_o9V
zqrx3OtCzS{BJkm%9(%BqJ=NC?`7C>fG>$*q8ts*X2es=lbQRu&>?#SgzVkIL5JTcE
zPLfiCKilEG6h(P(-m9<2#5_+_PbiM7QEj-e)4(%ktN=HWJilJ6E?6#95j=m#V|*yB
zix09x={B7H>=CWY5RH05OZ#a4Bc6Yh4bRrmIrLTmi8aV*DQMKNP5`xu0u5;+ajF}a
z7K9<nnj;?K`snKSNNs7A*n$9b-{asnaaawuIA{etcT8ujXX|vjt3kyoSB*`xXYlWC
zP@c5a5R>9AHMN1XIS{&igI5ov31O&M3E+|7SFh1%luLuZ%vEvt$^sY&NwT#*=M(`m
z%avgfKJCKs&~+Fngz;I(NZ-?1&<f-{;lqu^(he69=r(<}s-Mg!4JI&U<tx+(PlX@8
z5phBT7J#2hjEHaPcHv}I4t^HLO+4UZ<JPoUco<ye%az1fD1EaQsS5N`>p`onSu%$Y
zT5C89S$b?ZG*<fnEhM;sz+d&^!%WK?8f5h9B+wZNlt$~3Z3RYFm35q7>Xqg~z-p($
zJUfOM5l_8|EYVDjVzIG<KSjsl1y6LRSIVR#o@c0YTcajnm4q$fp$-OVe%YCCv&`Y3
zRj~9<t+pfMg@Fq5*pj}`zY|Hg|HiS(qmm>M${XxNOoFr!;byKXRzq~S82WEH)~q%P
z<cA3r4Ooo?Oa$@wKNQA4YJ;!=7eX=)4?UVP;nUkfVfPsqYLV5L8bHj1jf!e_gI8e$
zrZcf=YI-!wI}4t&=y$*F(D7{A9@Qj3DlPf8ELnrs!2*nGXW$)#(opu`fflK{6s+?%
zE^$;)LHc8?-D9<DXGuHaoGy=cT#GpQSH=VnxrX>kziQ4)HKDOBDH&&^qLiM#u{4F#
zOGm%JIvLqi)qp0PP(>ogjiIC7{27IJ_^ONV2-qVIwJ+fORWBCSR;^^Xkn0f_faFs*
z4KB9(I&J_3U<lNqWUY#%NW(AV%?;k-5h?4%n4;0UmKAMRQQZ5jah%4gJiIJS<ZxLb
zZ%vSe*n{3WExNo5=%6n@4P}Ny4K4G4F=>^d|NZLUWYlT(5?lHKC=@M@Tc8ad%Pst2
zH7zZ2LO_s)<K|y&!B5NO)IYV*4a*&>{yHPaA^D0@C?v{DfmA7xgj;%aM5rk7O?sTG
ztIsKaC9oQZdnld?#|Pg`2y!^9$j0K(@W5~bB5~*>p|%|T9y6qd@~|v+Ie`t`VIP6k
z6QuIocxtB!5~G=Kym;$HNvL#Myp+sY23dY2q_xk0Nf^cJ3`D_%@SX@SoPp|Drre~h
zdif0jG%@>>l&hr*9vK<Hi3t3!o2-O>-PhBoR!119tvy(-WQ)=(I9Q1_>eK>=%i?U=
zTMH;S<xZ&8K&O(`3yFe5p8lIwi-uoQ1j;G}ZGtRQr&0Y{l_SEPRj(7BLwnw!BK5Rb
zYx#2xLWclumEw?F+dYlkx`Y$GAiPAUnetR^+LSs7<}t^&N=Uf+eY}Quv;=vli6f^D
z-)3_+>Nx_$^kBK7mO~XNbkE+8mn%D}2O21q4|0(vmeIT63OIk&a^)G(q2y(_8UXMH
z(5y}=Sq%)ly2ETM(_rFX2ugz_*b0&@G(gZqmxhvSUvLCE45XnA5k&oa7l@WtSwTw~
z)B0S8r5#Xc$<o%$su#Y{8@+p{Dg{_EX-b||1yvbuM`pAwfQRCNBbqbyZy}sg7rooI
zFs-Y$R0?XxLpQ1`v|M1o(|(I=ttsz<wFU16Ka@Gzt}H+=l0~{IUcSzQ;A)f<ee@M*
zzCKLRjaMs5h6ba)W7BQ97^_5U+^LlT!0DGs964wep{X%67x2QBwk_7y;?EH}1WwRx
z-jP{?A~VzlZjPTO(zR0Bx{7r|e12_Qm8PmhI?k|0F@V;&f|N<D_FK*#v8q;|OiOaX
z6QUJhB($xIw!r{nBsCN)4cC@jwexy)21sZ9BQU)Fp@B_|CzMBc6}5U=>6$HpQJa+X
z{F5YXN(+dcMH;NVMiW}4%xa*IPT#D}M^O<f*|G3~DMjiClB8zH+t{>%LBQud;FM4S
z-p)IGKY|N=hk(P%q-lrzXyZH&`~}N)80}UqlqnxWxfiv^Rg{u?P(_B~d%wCf1oAGt
zRky}MNaFK`HhZ|iLXPp3MkHn=y6^FG^YEnAcynD;FBC{@QmoAB2I~@+X;ugGVQ*Jt
zcLyD`D3hC=WfpOU54R7Oz7nV6jzCN6?B0{iuZvWu@^$H`9B|}a*rZ)I>3Fj}_BPsr
zUP(XYLg(TMVa5)I5{wM0r4g1Mq>?Y#v^FOk;J?K%+_ciqC5-FkFpDmYy}CDYmTA^m
z1FM>HxYJNx=jI(pyiwXjnr2v%3QgG}uhyGX%Oo)>9%I7Z)d!f%G=5)5`4-%oHdE_p
z$T<>~WT`Pr*cDQXqn?Llvyn92S`w&mSt4r}3-&lCefz@A*lwqx+?I;b$SHl4HuA$p
zHv6Fw{ULb<BxRO#<8np9l9Wf@%qAzwU%C`XF>WjD-YPB%W-FclF00H=Mf2;FtDvKq
zNOft_?Ar9OOzbb|CoX0d%DwJ{LNs0)C7D)?i_TPf^Ob^)ZLzl#X>E;qS++<$D+`k0
zQ+NYEYM6)y?mAg4q#TN^MU$5Hez$@*s+ob=$|W|O%Dc$M<ni}q(z*U>lsCrq_iKhr
zSY~wDn|Dj;YOq1QF)0(V963N(y;&X@6Bc=mlhSCz<DYcB>uqgu<iyPq>V4oQ9+l-=
zUY3%Y?+nGc@h8YSmu?fo)KJS*b}feEyA$0tT0vuIykyPNcHI@lhFHemag?N_KV??L
zrclP<9TJ7Idcq`GV9Qg2Of{ascSd=;g@-Ptm&alG#PlvdaFzYVn!naPkhgDOcC!4=
zOPaq}`=A|My|#Dir7OmdzjLbn$^E~z+uvN>yW+k}J1?x9HoyGb{q~vr@9$mk`>ErL
zQ%24&KeN5G^qK9QW82OgKmNFp^OyZ$VQE=oVSHTM$Y{g|M@_%#+4715&kni~mk+C7
zIc(Upt6p9_{lIgJW%aq=c4u5WEMBp6>7*5(TfFz~2ZvSXtsW+4E?pL_Sg~@=qP4?h
z(fw`lw5iKG&-l`c&5Kr_c+0n*Kir)9#+Ovz=Nx08KY#us*;AkYcIW=zUKH<rZk0Xw
z+;1=Z<8Qw``vY$d+jGI2t9w>Hvv&5>9cyPdf3tS?3oovXmc9P!_}mu{7ZyHu?)nwa
zJy2Nw^0^l-fBB+^ue|--T~{`a+qvj-tJdc~_qpnGFP}K_?axivf90#g=3jIFG1-e>
z{>1mb_~I`oEqU?WN!L8{k#p{T`Sb~Qf9~`pgr`3K>WR-!dFg`clvhW6I`@T-q$a-J
zcIg#A_~6g4c>VI(qu=<;WW!#s?+-$rQU62r+Umcq88)!|nN{nT4_<WZW52n7_rE{;
zT=UW2e5G*P4+dQ3*|V#Q@BhTZ&pdPD?EY^JdpI}mxSi!IKG<CF%twm$wvXL>;ma4@
zJpSc#Q{y%rXUA<Cb>@tjpS!aE<;&0iPWj66Z7-d6=9Tw<>6Ycs4SVSWFMp)?ftNos
z>#7%znYHAFV>%Z-^O??h7k?(|d3o64(_R=>O}~EJ-teV!L;HGLxx8$~^-J&m`|24t
zjVkQje5T0WFX>**ag3j<kEQnR+<DsO_#c*B)VX)?aQ&`L?eY&7pSa*#OV)H|_TEvu
ztFol`+9kW5dg{uxyI<U~cF(rPSiASRlb(u}e5CrJ=ZB4(e%CkiC*3vb*OM<E`_!`h
z%sF3tVb;hmoiuCB$1Xna&e;pktAxArAD_1_zw3(cj+uIKJYmQAOFyyWnv;fIdd^o)
zo77Pov*uGTbliE#fr&ex{j6-REHbLs**q55b;(O-Z~oNF4^+=?zSG>g<S%OTpFLfq
zaawhBd2@Y3xmqlYxsxS;YHz0b+wol=|8`;F*=^NRt3mP7!FEZO9A%TjE_Ze1O18ny
z?3VI}#+RQvX=i5B*y89#Gv+1b89SHWHR_2E-F4jbGi1q6&3C)E6|?8RaMTM|O+2=i
zx<qQJ*&VfyuOGMj<9AG4YIo!>DKsXgKe2h_qK`DPFP^<)_6ujfaM`|zyT-lHF=y$G
zyQsNybRXxNW7spZpgri^Eh9L);Jb6!;WzQ6<v%LSv||bjXSIE5S;z1-`Lm--FAaW{
zedXlc6F2=;C9|~ux#~yPel+vRTb73N9xksbmeY4m%!li<&-PC!KX>u<3zl@<`9lBp
z>VX|Q^Y*z^>Xz%nXhl?s&S)EaY1uRNOBW1298Oz&<;3j86Ykj7min{Y1E21U3ujNv
z?v_dAO&if|iRw1%uNiAi`%YhJ*`|vxbYb}LGu0hC|4^BeJd?jS`APovJ+A$_CkDfr
zvO8Q~V8qnibo@Gge-q7hGplVII(E*S;p``OUF*s_q>;|gDA>w#=h)R3*A7$$w!F|^
zt=hgq)7~COy=@H{7gW~Uz`jsg-9JnE*5qlk_Rb1Yg<=q%Q`~(v&2wVy_F8ATa_jsZ
z?92TF@4H)jYKLundiPz@nAM2PzulfOQW_(VZNI~u6StY4Zz+^_-DU^38EIBrG*H<(
zx$*0LIkR)InCo-xbax`#Y}5>kHg1mSm%$Nz?%7NxPGzlIVys(i0=FYRUY=)YvWpL%
z?&P<~gf^dFv~}-P*}79YoQ6&6maTTH^zLp}wk;`#jZ2Mm+g>T9rt$W7xmL%XqI*p5
zxSf4IG9si89o*H38WodwBt^%h=BM<Y6(dq%2=$0`ZP`Klz01h<j~j7B75(kvcO$<=
zj4yUrQ>{qg?vQ@B2wa)p#qfF7z#|IH3!q-2bGlwaM^Jr{n61z9V#OU|%S91aX3wYP
zsZ2dwcijvL=5er4H&3&2RywxA#_AqZeH8d`61ij^-MxbCuzEI!_GvMxN`i@2DhxY<
zkSI)Ej1JwhsH$5Gc`jD#m}TuNmB>fVmi1FI^oAB9gCngQ&6vLBjifA&vI(Umy^RFH
z1yUh~F4RA_3B!zz(IlObK0^%#lJ2U0oE*6sy^8KJO)&(B%er##KS0h!^ES}y^%u&;
z8=4L2f0ieEYjf5Vq-;|SDQ_<&V^2(MZ<FKV216r{SPX_<;asjdrzzW}D;ZO^(TcFB
zdr14A2hXT7WC-z%%kLfW<X`^qkC(pwGu>m_dE@Wi9KQScr{7%p+LMP*erxY>w|xF}
z&dGcFol9T;-KsO+`pvg*S#|fdyD$3{{#V%tde5+LUjE4TnP<Iy_?2J&?5s0i{O!fx
z_}%OGf9$Nc4lcgwowNSw<!=vra_`%pKlikUuF3rH@UegT)dx>_YyYE*Kla+ot0w&T
z)wAyY?3<@PdD`1wd_^~({`l1o-neSj<ey!Bc;CUhUp#!rTd$1z+C_&0p1vizXY(%~
z5&7EHuYaIsjMTcSR&EQ=j`GQfnk|iUMN59VVN#Z2rCiOglZ6Xpy9?#5q;1_&nYzyA
z_`Z8iB-k8wd@ShBFP_n3+8I#JkSOdj9r?6G&5lZcEwG_A9Uamwp^UgKs09oAZG8L)
zv40z;%oamE&oxtRDY?0=JxmXne0iaHn6FQ{Bxa9gR(4Uu6ja|=wrHJL>it|u$9sV>
zxI5w>Zdxuy=+E-|e}P!TNSlX9uZr;wN}BqI-0FM}7~JkXew>D%r8wxGzQcZ91%&cu
zI4n)(p0>TtQJ?MX;5O_v3?X)jY=RBp{-JD`sIdC@s2DoxVq)v;jYzkuv5`s>avnj8
z{RUdvaRsMKd8Vi;C*v&})I0gYUkw(QZqQWNJWkp%N!FW6-=cUPBW{sFRyG~SSsk4T
z!&_&fF7J@JZ%J;UW$xyP6>{LwT>s`^C<X7g7Oiw$-^?zcb-3rI$mv6vc}zNU*D}!5
zM&Nm^n`0$1#VA3Hw6ojBW>BNU;!_=YC9E3zM^7v_xGk`@EZnaj22BsM5pf*WGJgP4
z6I;h8?MW!<<%87r8IT+Nw?x@mj~ld*Hf?eg5;M9r32Y;z%&~Kx!1*vPDSpn$(c*#u
z2_!^n)<+GojS*+13Nzx^iQK$epewOd(K_j9<lCaD<Q}>D*@)u+tCH>=aE@rw5P4*H
zhIUP3p}s?RbRx%15-?6Tfou<G-3<j4*qsD=gF>4^gCkH%3?oJCN!QWlTd<%#PM5HX
zyN(981)(%M#T^e)=P8J>dUbk1@1Wm^o>hY?(h|YozgrmZlWBg>^W<evvu?%Jsoet?
zphoxrI>0XqVUnYaa(~G>xsvrARI{P-r_GDYA#aKd0myAQ3q*DNin!~H0QwVgRZTn0
zYaBynQ7nP?0O383>?hMA+_>0qR|zn!<ncBn3<FcEhhZq~t?)pavFyPjM3*o{xnquv
zY6WX`ijH}ei$i!Bg8q;xpxc9;VaQwjOqckFcVwW7`k?c2Ays-4T2ZLsM0->APSrE!
z>17hTpu=eR9u*)R`_!#a=b*pBdW?ZPM7P$SC-TE<<5Z)rh*U{G;r)*1G92f^#={7^
z;vXFv9@ccEEzzr{wLoemkJqrxh_a&lh{lr?Zi-tyoS;Y&7vN1SBAr%EwW?Sxy_k_%
zn=NTDe}y2x+5tyYnpS!{oTLqkc3IIbUn+GMS=<1Rcr|ej9=yjPn99;jVdiW<0%JQI
z*1QMm`&da~MO}U4c?kJKsmY=Xe8Y33sk*lFOQ45`HROaWv_dtZut8&;zULWKj$&~Q
z)&HC#)@7ujbsb=jknYEE%QbQo%Df09tn&eFiSovtT1<?(olRUHegzk`7_bi7KDUK2
z8ka~F?<K;|)nT=a#R0p@jq?GmcwUP7)4q7B{zr8N86CuUd&@jmO($?f8ItU6sQmF7
zt`tRaMs?v4SSV{82%<)zR$7Vt{vf`+Ot3`-#ZhFt1LXt+p;boRR!KeJqvh$0++rBx
zQCc5uYaem2_SPY_kVn%=orY#zKUY;m*vLU6XK_+t$Sv?(LhEl*G-~6g*W=^4V%>!r
zK3aakEzym$oivJVIWbffmC_@hbP;92Rr+C4@<%@P+j;s1vkg=?Hp{2!XM#$Sb_ENs
zvUYLkxwT1rQ<t+Pp9X<y1F&aF+76J0n2mCptsMNpHlU#CLMtfC?*@92&?a5|Qep+$
zPy>0_T6*@FutKnmvCV3btZ~TEw5kr};d$IgVO|oGV&sS%M92=7iX>tO$?=Y=)E5SI
z+U!bNb?GQZSqc^_ndFtqO~Jy(mkCuY4vsFma5G4?I>C_ybkt&Hjb*S)vj9$_k+!YP
zNSlN<SEYkmZEDc-*mWO)?Yigb;S+JWaJ4jOssjphDGVC*_(NW|1Y1!-|D63y=o5hp
zSR-?^qu6;uCUh#*(#q*~GE#-4-=%dO(F$i9ifqbkKS4IzhE^=LnT0fNG=NFRIpklO
z*M|F~leB5NY&1^l++_jrc|X)Q!u0SG#^{Uv3eYi~@|86?DmEz+7-2xjof33LhDdR+
zE0Jr<hM*d|4^p)~C7SVySG`}KyA<6ljL>6Roen5zGJqFn1KOY{60@41Dv2_5By9!k
z7h=W{vyOpsDxaW04l4@dz=NQq0lLS8G^luV4AoPTK#V4eme^riB|Z}7a0lY_5jZ^^
z*1)fz_YPf_1uX40L<425iO>Qev@q|dVmY!Fj!J1vLa?&NM@|f><T+?8pwZHmAO)wF
zq#wHlWC^||ez=(`^~B-^Tu)x$-;$vBI4_$W0{FL@E)DeZ)E^lC*r{T{t33#i4t>y~
zFY~p40wh77cY7OM=bdV|lYgYn-Xd`$cn!ck>(o8~t+z!r<wx6V$sgD#OV<kL>FE+%
zQbJ?6QWDx>;hpM5OI9B>Zjd2fQDc5Vg&41*36+Zh*=m@u1pN>d-d809ooKYc;(%46
zeFf|szGMSOCE^8Ll?r!-*4`Y8J);(aD=yc~9U6Ec4~crGJrS`!TrbXrnl4Q(cu&(`
z#)Tw)YSh4osC=*NwesnT1|I=642Gcb1Y=s|u@z<+CG!zkRojA5eo#a$J-kO!pf$~*
zlgRosnx+yFp+!#rP3(;FRzQ|I%Y<sU8RC^H(|~E6hh2@h0F<mK&}b-~<)R3{`KvPV
zF2(X=IXW5=X!=1l_<1nz%0wv`@uN2hbX&h8Uo<Z5i}W~E%n*t^s|ip%K)SdZ+d`@G
z0bC3OBQqMVP(p_8!)a&FlcN}tXG6-W1dZ>3?Obsm-j>Q3K&6MyXkZvoR&?XG4+W6~
zi;xj(pr*_66KS?uWjaSZMpBAnx3S(@V7VE7bT`V$5$}k2lL1A%rZODkIixis{tG~1
zv<+*4fq|rH+lFL>QiQLgOvaJP>O4ikdPTgGi>}HK3DsCmQQBOoN*=V5AchLZakzjT
z3iB<HBGi`GU5rEH^Asj9Htg4ccc0mXR=r1T6~>u&llfk}ccY6{hhaRVI_OI=s$QT-
zx?a73HxhbXBg@d(t7`BM4QEIuBOOmSUkcnUF*OZJSP-W{HGcR*Pp58zfh@EJ69QH*
zt-Mp|IrVnwMS%|)SiQI6DMO+us0i9;B(f)$eCSq0z>73SG&5X_ucZo5q=$qmF4!tg
z?MH6CUFY7aYmTT+gF{XMQLNwZpe$P!L9kJ`(+kd??v{(5r2v+u9;_4B)K)-KJ4C6}
z+PfPmN1ECcEl<uP{iOsUQUkpib>{U_XwN7IiTJ6iLMv@Fu9go)`q0vB92MjJNb^PR
z-2z9pV3{GKs;!it68R)Kt(xAY%#h()(mk$K5kcoQj>^+M!{LOZM{qq-@R`Ch=!H8;
z<WAy&AoAk4d1$IFe|e<_C}kKLobVuN7C$X?3%1CR7I?{jH&VS$i5O`?Z&W(|60JXn
z9^;{ng|!E~@OzgRXm2^f?1~m!rEHmz)<eg}9y(gL8<jU;LrLRg71XFKoG^}@C}jAR
zW8Z|b+0q$9YWOA6h#;lI^-Ctos8#*bxU6z<UKs-5F4E-ZK`DW}79WQrAe*_Ncdv^z
zCUI>n&#Eq_6}MF`{khnLTBQY)E3TF|v~V$4%bPhzkn|2m2pn+sQR`#MqmRH<!85U1
zU=*~8gf`SClM1Mh)wH>G-VgmEL`ISNS_$=d5T23oKE`>(ank91dSUF()o@XD(V(E%
zf^Z0qIy@jc^i0y2)#?m}q=a{vR%l8YwxV;h{2V`pNJn&rdN#y8q8>0i(x61Io~Qae
zWaG%+{dtdL?nfCPPRG+a_+CSg#HdQPsKm6$pp7~;nE8WI4@vQIjPF=l67{MzN@1vt
zWrM6$uj=9<3|rPljL&HUwyxnvED&P#ZrfDiHhxiPxq8dB3Xt0HKS1kS>>mmI2QF~d
zXOC?fMaDz2t$Kz)Qv#!*v?l5$Jp-CT<v$d|7j(Rk8E!|kP|Jo+{rX;%h1%}@sCt39
z-W-vGlk;^%D!PZH6_s+?C5{SCvtm?AF>a_CX_I(A$w?lhPEVX5kafS5aSThkjryIE
z!gc~~?!+&+z~R;dc5Pi;PM0VMDM$oXf1z>kvp8Gn(cz^Rr#%2-Lqc5ZTb7g~ucBo?
zY$(QJc70tGG8QnoXe+OsBrza#*5KFZN5IHt!m%U7T6A>|Gz412h=ZL_$Y>mX;4Fw9
z20Z=?kzRO<H%3wjbPzMfN?^$m2g2_i``0!KB!`9B02P!4i>bt=dO%`|kg1NL4Q<*g
zYkHnOvI!?_VaT1HL&sSj@U+tAC9oLbu}-PHi7FxvrpBYW^whjdi<i;*im9AWkD5%O
z2UV~Ok{S-Lit#dzgu5ZZrj;i*5^f<;tZIiFiF(2RACa9!2Yw!cp}W;P3UDR)+PqkG
zsh{Uitu6zmemtvj5+{9d4IvBUUw)++!!f`b3vyv$!>I}qw92bGVej;&{54t}Rn-eb
z{4Cs!dRkEONicXc{YIl`YZHRdlxQmBo|e4%Dw2Q{OmwbclpsUr2@l;d$L1UZdmmS0
z(+V5S8Ut<!347&?u*m97O-QX&;mS;UtPGL(MAh{0mQIVi2j!@R3QjMPpE%>N>cj7g
zH8k+bqh2!9O}0YCZBRKLFgP=?p6pNvH;b}J=LV$xS#J;G!U{HL(+%k?;-b`KXY}x{
zuI+0|feC36M>D~?kkbUbPMtN@FvD`IB2b#M*@-*`s)f82-0g=@#cozQtmDB$SX@@^
zX~dz6OvnRQCZ#4S%lT{?yTq)4b2eCMl3Li^!y%hYhl-)3Qay1QvKiPpDW1`nPZu1?
zG@Hl_PN43eV5r`RwhKZ^Gmj?8Mi+)Ijd*Qr!qOCP`b`U%BIS5XV0aQWjL6;Sqbubc
zhEuQTsGN+5X7RMPkMq(y^rI75TQ?oar<Q6yX7%|+7^O;aXkC~qG3t)9_U5TZ=9OJ6
z^J3OrS##>C_ogx6K)2fRvTxx`(q*oe;;zp(KEt$1^U_VC@}pi`l$rH)3|@hp;O5!1
zTLw9~<aon_1zV;C<VY#EaYB&HF7R+?nu9Q|&{!=khS|{@63LcaRvNsB!2A5;3sVt9
z-n5z&GcHM-<zaO8m?Z4sA#bkW%Yu<+6y}zt3~jRmV@%bVWV4kqrO27?(AaD9T~_lx
z9B(QSmYhp@#a4L=wl+*rwKJuaWeRO&Q`S?$*cTp8w2KOSkEaa{Eg96AN+#GisuRO8
zm`z9&b%Iy&BC~#UnMX|PWXi`a)`)pL-fNR!leWh}Wm=rn`#ZXm{Ef+Z8%T)`(Ss)z
ziIf>N+&WE;W^@uyn||4X-j$a;)x6^RUAl*8TK3H4)23c?RWteZu3GrLHN7LxoI3vG
z=_?0K^QNuEL#un{OdUUd<oKSw<^2zq&7%)yqtWl{l<`;HWA=aY58z~2&vDVP@yA}7
z+5cCsnf)`}uxL~?tY_3UX8-wjm-j8M4y%rGYsZh85*?U(RrRr}c2+i=-b{UU*py`D
ziccj6mZjPr7`3DAtD~m%d|}0zx#cS!__A(|?LTFF@2M-sPrdq#>7#zS?$<Z}G_~ir
zU1L<==@%S2{?>bLnYMEDebchn5AI$u?2m7*So7HT7Yw`a?d-q3apJynU;EmYT?da|
z`H^3DO~3h_H-CT9Yv<j!@rkk9#{T-lo1fnQ)jO6vKJBubUis3cBVSte$~}KP|Gst4
zfBCX+K6c!kQO_QgdUO7VpZMrir`&tfzU1a%yN<pmwdc#fzU0b}FAv{2b9w6J(>8p3
z<tbA?_`?q!{K&rdy)o>~_Z_@s-<1#Yj@YVsi$8U!`{IjE`^-O2&W?Jvw(;KPocifM
z_x6py@J3&};YU-R7`=YV^y^<(H}#l5zIp4-8~*veW1jj!=bv5*8rSStyY%s=M&J2~
z>yKHy=7C?na_aLJ+_&Z73$~r~H=o@1`~6>?@a1!k&HVN5t1@GL|Ha>L*?->NF^|kR
zXZ60Lt~}-OQK^?6oA%fzW_8{8*X6c*j(fc8g=6>s<%aaLUz$4WCu4H64xe)CtOb+D
zoc=dQzj5xeQx1-rar8Y?=6`DKb0TNX`@#iVlP`Wex9aO3e&U9o%7OI$H6pLA(Y-}0
z)~;zxJ8kc{?BDJ<<5t-fE?vFh_}#hsi|fDjH!t5ha?{}A@4s<$=alN`&fnfU`qIlD
zpZqufuxG}drybM3ZS7ZQ{PDCmj-K;vJMQ_OE7E(nFaN+((;olm{J-7Yd*z28IlZH@
z=hTU3J^nuTH}-_axGAYy?w3=NFW)@wjd6R&9a=Xrf2b{c&f~{k@!^v%H=o-)<BNTp
z!#{jzeaCC8m)>1fz0R5=a?Pr{FP?t;U_4-UhS%OU7*6WGr&{|~<vVf8xu?FiX2<ji
zyLx9oSnb+;&ZhRw-{051-rV}P2YxWnpPR7en9aA}eD3V<j;=TEDtG_hu9<P?weF+$
zrM};v{$Y7oF1@2S{Nc{`H_Y?z8+_YDrHk*7!uL0abJ|{OzxRD{enYq@aFso6>(bqQ
zTRQsNE8(K<`@(%k-+SY@b7s7ZJuj}z%%0*N*fQeL>*C21Ke5{^9Y$Rqru&M<C!C>{
z<VR1)-1*fB)t}yw8@uklp0PiF(V98eExoPdC(mZ5?b)#`zIke)qi6bdnLlUv6}7_q
z%h&g|vy)(;Wajl=@yNX1#rHneH+%fS#)96(@i~hY_s%~pj8@(&)$G5W)^Xa6BRevM
zPFavy@8WaH<HJwBFkgo63^#l|3OCeaxoE^m_Uh?-vdfOW%Ix_hUw3;~w>c-$OPWbH
zq$77jy8XNVy1Q}7(Pns+Z#7CYXF6Q!wlH`$&TYspqyt#o*%Q@%I)7xaoNc(vqNF`v
z+ELF|N@lri=o=s2V@946-B5TulKCO2UdJg;ua%rF?d+afp~(x^$hdM;w@YkIJ}LQV
zyUkZNW;pT5$;U=cEAQz{vP;gVV_CrLuU+>%z4HYoa!K)Xsh}(m56p=cTz5{?TZyD2
z7sefT{d{<MgB=K6fiFfQZXnK=>mwVp?+R}#e>O4sE%AizyJmIYa#t94_NKcF^+h-K
zZVPK2Tcl=_?z+8Uo-1!VM~ZiHbOy7Y)W&&X$Hpb+Omv&4tSR2OXG|?za9MBa=*uD=
zvBY7%GAGU9s42<Vo^rEz{O}h`Q)V?5jOqApDHkso$cSY+p?jVlx`8IUF7*XB@H*+&
zY1@;C$NJ#-r8m-}Wtn4bjHAYNBH6EpjAR&c)bh1*owc=%VK-lDp<iJ{x-pExdRRyp
z0Ee|O3^(%5Lp`*^$I|1`vq$L6UlcNYs`ggqR*R`xs+caN7GMp_hlW@zYS;-O{i}7w
zuuHna1r-|>ofXS`B0)-<?s<CbH0?XBB+W`O*qZ8Rd;%imFwlsOC)}Mly2E-B_4Y22
z@H^lcgUQB@f({@2sI`%@vQgJi=1DclSb2Dy=)R)x)-h?R<>H>qnmp^+d}#_~Z)o%N
z#GcgbE=@$Qu+#O&J>BrENX!OjKI{cc(ryD0o0bwOlw;`whd}o{ZTrI!-+$a~qxms<
zI89RvtiSby8BJ)pH_4V$U`k0k!_cV6c?J%zNs_*Np8h`hc-F+B<l+j0(!?|nKApFv
zrN87Hes8OXb<fk?_YzH_Nxy&c`B8^1zxOK#PdNOCSKd5)_|W0!|K+vI-}vak&m4Yj
z<&R%IeCXf*`09@?e`ED4CqDhBgI_y*=$eNPJ#^^mH@<!FGf)3%@9VD~y8EHSs}Em(
z?{l9&{qW&~Uwit;Z~V)lg@-@${fAy%_4L74Zo1}2hd%no@$WqU=*5Rmd-|G{-#m2O
z8|NN6=AF;HzUZC1A6j+gHxHe8_}oJ?4&U+imA`-e<yBw$;o-{<pZoe}51)AW%0u7(
z)ipnQ`_0R%38M~nAnG2X?YbtN3ps>2lgsu+^_}e#dflQ5lcXj8H*N0%AXiZ({GVHW
zr{_**67EbU$s~kO)0u<;0f!JEW?8K6bixo>Xp#UyUQLW_L|vl-vMviXohBKws6&Vl
z!POxfSX5TS!^f_yHX$I(;);ssijRo+z-9eVSwwmLf2VGD2z<Ef_x=C>GjnfMojP^u
z)TvX?TlaSV&aSn!xGTSGB6sbCWvzcGr__C}u3w)r{yga)mLqH<u71kr`bKRBzeygO
zg{#Yt9AcMll}5zR9m{kMX1u3|Y2A>I3yaprCh4zS+~uOCc<G%yEWL+U<usc&z17VF
z3v%o^9eTTIE}9cfUB7u?i{0+cL2nk`d}@Kp`;YH$hg$AnaGB<~y>oH(wt(tw`8+!*
z>NTw}R;|FD`g|>T4fJcEvXl;|%^1J`vlEhZIIm}(-nv975_VT>9EF$Ix#}5ACL=x-
zd6GosAN6`q{1sNl-4vOrE6K5{-0ix1Wg!tZN%@Ml<lZyDl7PJ@rfa9jow4jHV`pRO
z33YPiS!v8?5_Epf7hTdb%&0uHo2~HPt#X8#wLsg%i67=uPu6V1&nKJsHY|=%4dbTC
z+@JHzUV3DRzQvOj8v&hB%o`O5<XIxQ#6HFZ5(6LOFS0Nmm0oY@4GjDbEPH827A3Iw
zDEZtVEpcT>zwbk1^&uzs=$?itXiY{7>E3~4m{wLqgw!wq5q)F$)kP;ah3~&z@=0jy
zU^$LP8`V)^xT!{LyhFKmjg$NdtnpJDSpg~(Xb}u_ri`-6;_#*(bx4z2?3nsm_R||Q
zQRC35&aTtaE(eY@R1zOZ(ew`SIa38a#S804RTa2oFqZLhkz;r~;+^oZt{&0`$-JiB
zqZ?*`-i%it5#-qA(}>JnK;*+(jn%7%GaIX<CL$tH85L_LF?h>!9;uA!u;wQcF9r6=
zmrBwkMLIa-^VKq>n5^b(#JK^deoob}hNEgyYS2;y8|#l`#vYkCp~VNs#yZ%~@@kKv
zkK!mQ*+;aE-FP@9W#`fmoJ2Lx;{)rijt&JK(T7Vh8e?7KP-Wk}q=Dn1tdE+8&hQA;
zJbR7UMGf=hk2K^?_Ky7;mL=zz1|M}qpJ4S1vNq7bgn!%DN1?=ka=ye`=5`Gzc!`Hc
zMH(ZVrJ3N9kX05gB;ZXM9}|r?UQ}YQrI!t7M#(z7RFC6gT+!+)CD<=Sz9&=(>}@oN
zZZT(>9(0HNDW5Dt=b#6a7IZRT@tByOg(Yt+gNWvYW#kXv$9YP}-7e@+5C7;UXOdB|
zq>XvBGKx^H8TEVOhhkR32vn2}7gSY^qCcJ29XsE!&|5xJ-#=lx3ywaRilY`v2oNNj
zf@qM$OjtNCV2Tjebz^myj}|IRzF2=F)aW(?MBSiyjx#=~ZWJQRnv==IDiWZ0gDuaE
z`A%>OG9N{CkG0yI4%3YD)SlCvN5cMUSA*&>jJ#^fR0k@fMRgz|@dkRDj+iP!6IP6`
zF(d<Q4#u8vJ|^CIB=%%phz6+!%M0y<9bdRiZOq{$WAa68w<j&6Uirj4tO`2*mmg~u
z-jSHvqSkXm6*7eHLQ3RB|HbWgLAzdZ8d9kkcf4qh@G`*ynHo6Xokksze%nV&PTALR
z^TtFrTA{NRK{%%o!gh%|+y<=}Kb8&<8ke$H<09u_=pq7q)W~tanuo*nKu!Q456*ai
z2wWnyRT2PJi-XJTOihiC+*|U8qX((!I8%hzLV=DIs8@?)+_0(zh?8iRbfm^<eJJpd
zctBl;<;r#3IUzq1<ZoJ5{~$JlqZA@Pw_SPUq|TDVgQ@G8ryEz2w$xyvsdXw9enWIX
zx@5hvr%s4=|LKSu8`U43ObYCmIzE@2OOv0{zQ^xIJZ6pyV{FaJx*<s)8h<>A(Qy$@
z9?1vH3N%l*6&JgvruX0*<db_Ay?RP(q`|Kh$nY34MWit4PAyYh4rTRKrl7q<bu=Z(
zEszaIdu@k^K#%Q``+NJD*-9QhQrPTm63yo%r<QI|k8RGUPcIa5IR{%P3`H_dn)F9X
zlg_fjD=~?z9Z@6k(y4ZO1~`WeBh3!lv$!};u`OO|2geJSG0Ah-6EE6PPpPjY^Wi@-
zC+++cGB5=A$(xGH-FW{l$<z5HnupOdPkZ9cJ83%wi8_X9faEVUncJE&)|(pBaZ`^R
zJvb3z5X@+YOyu(9M`x9%q&JxE=~iNon!>_IoPMWVuH7@@C`&>)qwO&*s7K-np5M$|
zN@q(R;^qY<vU(9;@yV1(YL0f%KdA4>T2=v(jz6aNc$dQ4%bO$`m8*>3F7#>z8%edn
z>4UL&hnKn3?((n8a^1AA+R2H*6lenJ;eM2|tSL%i35u1ad^h)$MoEVf9=Sm4<Vsef
zd=s${S81V4m4z8#R3--*a1~dGYNFch$>|xATRtOFva&#+H7<sxgL#EGJn+*Rl<sj2
z2zvD)9C0oq#;ah7rzz1MgDFvuiU>NG&k%+$gNn#R%WKswq2_QJHMCOc)Xv|7AHW6B
zZ~*Kw5}yT3HNz>-IuVRWOdp~Q8IrUTVZ8A2lwBAAu}%vU1>!M+n2tI$!+_J39e}98
z4TKm8;JGNNZq~;pH8vKfh<*qyQQ;O1XPi}Dd}?HX>UI66)u%~}I7%>X2}S8RVQA(M
ziaBykA`2?kX9I2UR(#Y@PGg{kRqDL}EimYWvvI+zo4;}P3r2nrOrA%3K_nX12*t{W
zQpd#j731L%1m4J2Mv&Noyasvb4ta~eDQle!fTMDY)?qb(aRdicJ=T{YmjJOx?a^jQ
zhBix8n3g~!<N<NWPMix;6ULH=6)D?L41QV~Iur`C0ECj1U)2qXRc~*vD4ymIhptwK
zCSGw8d9lHRSDE@OV2v}u7g;zXGghQw%jLPnv{B6<7@Z|mDw8#BYS~M7Q9XznYrH~A
z&&!~XkDf_yO4`R5sQgTV+BRqwkrHUO>H#c4?*l!deXC4~k_tDln!65C03I@N4CxeA
zY2+47WkZa_if~CMnhKH2rNJrcK$c|)9eGz1m!%!oX2clh3DfU}VJrqEO|EcG=hh#p
zPj&~<%2>2=?g%&&4jbr{LNl)g@qLKlo{iZmmqL$Mk=x}PXF{0{GM@q!a1jzZe8?D&
zfeXPd`0~%OQ(dr%w$6k{g%W#}0ierOgUHvdhA2`_UClDHLHt<z_Exha1ltguc_j6X
z-l32OXmX&AXjqn5O9t#pc7d-?aC2O-GA_9=AX)P7kiJn(1vZ0JC%q(MG*I=!05w6-
zRnVH#Gf(%ONc<3{-_BGyLlJn;!>Hefd{k1kBX7Nqnoebp>5x*{hDwy4Su5bhBV?zO
z30;2JY?7%FWNGOK;KM$VhUam4O*jV1I*lPwztG+_=KyuRdn9aw*8(tu<QR#9-s!5~
zhe=vvP2yWg;nsf90im@V?K%i4jg~n`?7T*FSq1>@^sIw_<RK>zU?9|;dM)_`Mot4-
z0bYz9C7|bUJ~D_0P^I;1j!rqWm{@#{bzNW(7&`4+!fXz%3Y`v~*i7Q%4ubQ|GPvu4
zX?&DSsRRd>PCRhbn**&O?Ry!L3GB@d-<ZB8lu`7l15Zsv-t>6J;%%u_k6H^4xQO+L
z;`TC0db_0#nL-h*SoMtRY|v%t3DUV5Eso{#T6P)0i?E?fQ6$|E4oI}?$eDl=D5Mb&
zh#4<c@B08W6CZ)bDbBmt29E|5oa(w&$;FHjnb8F(S_faIA(|PZrRHKSDhm)X`J=bD
z1a!udfyxsCK`&0r6C~FkW>AQ$R7jw(7|B*eMWQGmynmJK@R<<G2{aAMM3zVhGN2O!
zk6{MjL%I4{A_!vDKTl#aeCRt6&$uiMx|fV#NgtpzRi|@VaSbvEX`DC@g0M)L;WeCS
zz@Hu0P0}R})pMLGqBbaqx_v$rj$wgO5Yk|`H~s~=REIRU7px_Lg{;@+C~%M<WU3VG
zI)xz@1W{^6Ht@$g&ShbR8LJ9{Y?&%7RRU-cD&jdG@5GYY6Q=S4qgDnM7GUYIoGP@O
zamVr@lfUBv#!y7?=&h9wpDI0qYX(er$-psRwILtoSY$Rpq;gUeb5Py&4aqdM15I4$
z+3=<+EfW!{3$A373hNbBHsF;>#1>gT1T$U!@^%775gJ>z>Z5F}#^4m`F@=`I&TH15
zioxsx_}EX;p(Q{Jd1SON3b9bNcvF8t89Mek%Fl4w&a<7C6w$zJ64;<W_@VVdoQS+Z
zi}&14P(fHM8}V6dAvmJGz$S94+e}tpBTC{4ogC-X%ljjV;}ynMyi%$x>bl^nAJDwu
z&d=Ohi7Zoil~j=kGKAA==IR5y-WaI$jL6C7;qONhUE>E(g@l5-K*^nPKQ&H~st_wc
zQ_3z=n1+~on2}iOu862wGX1buV8<2{bZke6gRG)=G+Yr+h-DOag@nR3ttZxzTM$?&
zGLzNWRUjO|E=XMwX1hT4#l9>m2<51#0JLwP6?rJwX~8OAGDJ{oWdLfmQa5I0P&6aO
zhk|h@VnUq|_UiKXo7J>I``iubogzj_r@?|v+3y(FcnePZ@O+@+2E?l8{r@s}^%lB^
z22tbj03pk2jdiISp4Vt8X=ynb;p7UZVS+S~;O*Vp!*TQ?V2CesQHA<wL#*<k4#f2I
zT7#>+3ZTdN9I1whb+kO2ty!{o#b&J|%$bS^r6}lU)u7M{u#xn4!rm#~8>^A1JBi6t
z%L}3nk<EJkm?frlYR1UmRI0j?7%nR#t)bL0&S{v|si4v-SjZ@a76fRwRn_AUbv7LE
zVa^ssv1fD(aw*nvwZ#u!Em?rjh@}DR1S>8CT#G-4P>j@U6mUu&j>8M#kk&+&B5P!e
zl_neIVv9ksiiehQAOw(}QK}UKW_s0*!Vyep(t5Mvyu=>gDHPdDWV`SOh-C)|$l<8q
z8NV}Mf9RZxFhc!m;4O9G8-=6h7<R1`jlD1ziNsq=j6%$q=`aD(lDa&POzA>`zP;6K
z5ZNrT4$^Ktr?dZ`kmhba>bD?njAPx%ySUrgn)ce`W!vm8#8>5?6zdt~3%mtyB2vC1
z+BrtgW~Lb(qsGh=q#Kfvw4yUu28!L0@ipl7OMMzwYROU?^-tzw*X78twu&c3X<>8<
z->vBBhu-+Sugt1<7Y-d(ok5ZOjSMsxO$KCUe4}Ac#*etVbPu_t7;mt>PGkYe3Wu13
zRi_-PFYxm_?1B_0K3Ex@NEX@c1vR@>g``_)<Gd%tuh07V>={P7j<B56Nrv;}-jyq_
z@^*d9h?Dvudaz-$CKnw-C!Wlkw<hOe*)P8Tpm_dhELDzTB@?U>T*0iD{@ef+6-E6j
zw2Y`O|BQYMwWfus8#(0U#3NnB7UHz4akm#&$@fa+XrhJiG=nUYwfxjx!kZ|=ACO5b
zCs$Kh-tmK*u!&@3d^Y8?$#Pzo8^Ippah(hgCUGxk!x#gaTlvAHs8Oa*iIai-*-J=F
zG2sJPMa#zVBz+#*7o}s%qt_3Tj@L8umV!@7Mvxn^FrU7Bxnnz<s{5(jV`CUcJull9
z=~mg5`J@s@Woznke<WjrV_|SQa<C&wIuKc2hiGDZb5qP%E#KkoElx@ewb&?p$W<n0
zkH@}$7*!cL#QHdr18gJ8#psoE<8mcG_;v_Y8zpt?BYwA5e~xITDV1V=FYb1cfBFI<
z(Oel7i{<ma@}d4k7yfScqS`ulWd1|DR-cyZ=fh5Yi!OZIvXu+|eAgw9{HAZwaSQtv
zFTC`=^-B-zUH`pPk~!ZyE<X0yWACe-eNS)t^t+SUXHV~*GJE#)3x9Rq;)M^@>c{oZ
z=$`WI^y&85i~i)6ofqcJ%z2%2`p-SO|Dp8<EqZpi<A&iGlG}FfUkyEb;k-pVFWuC0
zb*I1Lsm?=gxn%X^q4O@>6y11Gz2~z_1{OX4Zk2aoU1WRD-BXiAw;i`?__;qh>$V^N
z)k*JP^O@?e&wu?n`(O6171#g8n}&}#I(P9k7tdWa{PZ2Gc0PU0eZB8IX4&{f@9RJE
zdyB8V;|Gf#9zJ8`!#gi~??>f#D?hgFnbYSie&MfY-Tczbn~(n9`wqYB8yClg`%mkx
z|Kfdz<^Q?*4;#OD#OM3IxBSkn-(6l=b?MaOAAWJ_Uz?}qe82wdIX9pE*-LLa<Bm%|
zQ+jrVz4zDE*UOEk&oBLW#!aXG?udh?J=df19{B{{9G~%DZ+!jA-|k=P`SCHUC;sD@
z)x`_`qk8>cy#1v93nwlA$a^N4=(quQ&EdIK!%uFi`e(1(b;w&UzV8d~eEaoB-aj<w
z_8(lbJ3afD-8)Y{y*GXG_&MV*uKeiyXV2KO{Xfn=&OUVUai6>I;%kfd&)Bm4f$}Hf
zZPVuEzg#`0@BUdwZ+&F(#!J=>Z~D%Aa`)z+KIyMFJ~QX<XYM@qrpbSQ>|xR4D?S;$
zxZ<FA$F%*H{{6JUnNRfGbjELv(6d7q(IyU^^wgx+pZ((l&UxtkV=AlHyzkAkx~I^H
zro4Gi@q)5De7W544zp^(1?G{bF7DX1WKG<>=G>dVam2Yd&)zeCdBrVQ{_yxuk9t^s
zd6fUbrg>Z5JU)2+^}TDSFOJ>qe*fIfBS+=pZPPhFy|8n~)-5tG*&6M)ZQ}{4xvJ~d
z59W@)>5ys1k8b{_&ZDN>deDx^g^rtV=#Or`@nf$WjJF>A`pUn~J$(3ExlKbyN1a^@
zqmyorwMG4n%KhEf(WTYbc2;NAa;vw!<H!~1$dS7?9DnpKdwj9H^MbB&bbi<Fv7aCC
zaQ|ZmJTi7cyz6xr9MyaM12uHFcKSr2yi69a*f?IEb}d^{)9Zf|&zkkOtFE~DV+YrV
z8eI#<?#s<jznZgSA3UZpduQj-w{DESY{$~U4{v_m&B^%d1~*?TgN0GapSWE%PM(mP
zCjDD!#|Iwn&@)Y!y%&A<-xnQz;&*z+y0)A!>#m6#)BeXMkh@s0ZeHi#PLw+PC;E~_
zPtP)QH>^GQ#@dquaqTnvr<HlNj;GEl+?HN?%VIgWZ}AlaxuIht^SLQ+%N^H!aIO1=
zuD>y7bq-y{hv2#w{@IoN>G4zKsXfV+mzBE?Tw9Litn%pCLnqJu>cv;(&b{QsDY^Tv
zI6hgowmI@Z$K6xDvw}V8bDlkx@9cHI?#TNN>{)a2nWxz4QPa*@v{7YSqq1+JFWktv
znlbsOzQWe~3%7|q{1a9_ZEP~wdv&t*mSW$rg+bl`F8+;8zx08%8zQOIIV^gfOeE*k
zKRtUWS=c?43{IYu*p9#1cF=wPfMb{WuEG2V3L|XpEYA;|Vo%JK1}Aq$ZubZL%0{#M
z#7cAI#OjrWu{TR{{gfrMryaRu>Ez-`(TF>_f63B#zhxpjlboJ;8oU%KJ5EgewIiFy
zt~k8V{eeOMfiCeIK01`tuY53HzhcD2UB}7Tl{`rsPeyLIg8jkhFqs%7Jlda(kG@|v
z6qyQ*E*QCcbc**I=8U{PPAi)mjB~f<oWFg}2ovT{B=v%f)r+xd%vx$q+?m_h+Yxn6
zj}tTf)~@Ls7wOK|{7Lg`@{Q^4q^WH1EuYm>IeGrwJk6L_-_%_$OrGLpl=DMn=BMMy
zSZ|!H_E$*k83eArk!Cf>GKl!PPuy1D-DHzExpLGZW07$!W}-AVDUKGq&4!|@H<;&i
z<P!a*Q;z?R#K<Fg&Ngi{mHHLNbzOm28}m{(`!NABv9ECCE6&^8^n5(Zv%zR-T#`3W
zLEe1Lig90my+~=jiAtvzBcCrWmD;fDwfgRL_MInV50!Kc<H*$;#Wb1Xu_jS4zWaWD
z!*HFc5m?t}`$v}>^Q(R*569!FFPy>%J0kZNYK&<!#mA2Q_MwjI0tV{gRpncz&m)yY
zL$hkhpn&T;#T4^~{TwTeVkNgHU$uh_<(qq*pFS?eO*vw0&#-hY?33>=W$w+WYS*n?
zHf#PAwEZ&ZnWtAnUzb~29(zcIjx;V`aFon(c1sTHogH41bg3QA`IIspGFa>HZbtm_
z_Mqu=!*R5oPauq~<>U_UlJvXrZZc0M@;N=)-htk(+7|O&rk7xQY&i4utjMKzeC?%+
zAN|?8zWuIeZv6Lye)y})KL5f?$Gvp^rXQUA%wIkD#+QEcj?ce~?>b$4{Kqc;?KKY`
z^V0AB^O_$Xcl7TrTluBSf4k|yV}AI%wRgOD+?W6L^6S3*u1CMcnWq;9Z+LMIC!&sc
z>3!e)<~xsj>BadUe{s&|&-`uA3qSehd*5~3bC<vVhG!1^+z-FB@`blPy8fMaJbL;3
zM}K?Z9Vb6?#tX;1wEoHG9=)8?A#%sLpP%`k$MBt}JDz(nj^`UU-BO{oMS6xPF^#p-
zQ<#(vbk}5V!_LA~3o~R=GU<Gdm@P}E44f93xqZwk(%R<UVt*2S`^a2w=`24#j<1@w
zKzwvy`ayHH?@IGq3j_H<A6?rsHvBY;@mWkyu~FG28@rO>x!9s*zRJ{mp@|-1Ej5*S
z(bQhHhpfK=6S$^#jxn<aZg~Sqrkb=7T`Qa|p;lf7l^1vg?&VnZxmN~X6P4Mo_>5E~
z41h-d2yoCSB{TF4;_;SeuVW1sCZ271J!8Vm-Lm>E$Bqp%j|q-(8fWrold}k^xSErJ
zW35ZZnVjXE=$;35n(CX4W6T_(;12$*l5E93c`_TVD{o}pOP^sWF3$qSztv%Qd&Ig<
z-WBMI%y7EB%JIF(A?74XXTDqFVUld-u_T$WJrJR6R#Pz(=xjrQ9wK3~n%7lt7dT*D
za*#};pqES7;f&?YQP*<t3reOp1{d{?G=`lp!qm6?T%<8Qt?Q<QC%-7>L2-HsTh4~x
z4=u^AG8~=AfPO8uzh?LiZ4;G;G?%*WY`D?kus^tSfb>#Sp;T}8*C8m9m5f59bgZt~
zUkTcesY6w=ZeFBUbDJ%ci3E^~EfMEXywbu`w<WsSjUvj!#||Q6t|>0zC<!>8b4M1p
zDs^oQY16@TYl+Y5LeB=6xAYG^l`*js=z;~e^5EjERGlquwq?l1kQpW~Ly<I83N0R;
zQ4y!xG`UBdne=(7!BeqxTV<7hDZipgtgc7v72KYx;cN(V{b6rLoR_i#naQmW4*5f=
zy7{1V$f0?14I^1{Xe7~ye0Ccc&6f=hM|q<wtSJji9WnjE9x<`hiQ_zjNmNORH2J*-
zpU*d{i5%f1T5nyXWiZM^Z{tG8oc5!gVajS1J*$+)PCYb)vhHMM8qoUm=%Q+Pm>u^@
zH_xPdV&ljpf{mIUnO6`NGs%ll?wT3NczM(@07krSS&3a*3-)M8mXcg1b+J*^jJy^e
zNa==1rgj_TjQJiVQM!&c)hpoLfb$~um;&_)kYc<LdE4c^16e{A8jbR3dbQ{wJ(!Rc
z7sn!C?|=qtT9tZM<f~oa-3Ci1=CuM~z`&eG%V=?oVA|(gYHH*|i_eNC8_5#GqD3pc
zJmhWatH~DB#i1L_R?i1&;fq8I^6dpW&P*H&D#!O*aFRV}mib5^A{OJ`)jLRNl=PP5
z!zvj*5DM^1;yRv+IO7md|9NeuF>(tcQ@E~C2$M=*&T9dj6-wKUm<HQaVUlE+96L>p
zpfeMi7e`nz9P;RJF|8`qb0=Dhs(>oymM{C52nwim<9hgP+X&CXy>ZfXNy2kL+3<lJ
z_YO;|D)e|1=~TwGs^j8K_~c3|M#Ouv<7Wqa5S;uq%E3vkR|y<EY=J(-r>2O~t7Ddq
zs6mX$jMV8CXhfUD#vSOiR)*La-y^*QJsc#a60JX&)O`0CWUwaEKuO;+9*gcK^0N@0
zDy3L5+4+dF>RB@BC4DhgQdLSEQez$BCo&AW3*eNkqtEETmvtR{d`I|}oxWPgvl&He
zjacU<TJ4KHmrQ6)+dnBZ94(8dAB7hkAva{J({Yg0Dh^8dkU7NSQ%sVl+RX?_ASmn-
zTgj`AIb-6SjP6Kpw*;od+aF_(A~lfmM2iv{jB<Pe_KXcM<ePX~BM+s>Ri|uRq4BYC
zRV1MzvOb{iJTWfz$b@A$BOm#>%Nx}($xYm>$9#>!p4x3ZWE}pAyIkrWQHJtxtUPEg
z&#^Nv{cvas&_6cF`6-<eJMxi;Tg+aEDhc3lq1-wq^${3EB#)D7Zw2kim>b8o^3>?W
z5M%`@GwO(0o<u|9`l1uaKUk`y8;uMuw)FjQA4>)n#8{-kj|wiBEJ>rcA1iTH_E<R0
zS1ObXZ%K||F!kc}Ow(QTg_5Ix^RwgT80B+Yyo|<!DqOA}_d4w#>|kA-6C0l|<1QX^
z6T>xrUfq`YCG~iG2HRq)VxFmqHa}M!&lk|M**RD>zA^Epg2n!vbPw3L30E`O#fMsv
z!#c!NAj4Q~p_JGh^{|4UyIeqRaI!UF-@F>HNqn8|v74iUiG}%QbTZIo#aHEles5$#
zYTY@6O3Yxs#vyhU^E~=rsmL0M%p982$Wcz_UL7sMcm~}(#<OZ9OKQa%qjV{mqxVX(
zCl^U+7Ux!aM*3yec7v1@dR)>DK4G%hxTNH|;`5CmoQzzD#Uzn<8;JCb$-_6{HG0-s
z`kBp;6zww&5~+<-3q?ht?_J_YeCCazAx08btP(loXu&9rQydkJG7yb8r?l!F(i$Zy
z86cq0(4!~;l$A#50EF1Uh>dvzQZ3DnF%uwn1$SZxcNo%Sb-ee+AvpgN8Ulz?MkTkP
zYF)fR-WCNrbt5!9OO$><0CDLGc?3G15H^uj2E?T#?(dg|b7F04n81Yhf^o_|<Y3_h
z`FlR2rBcS$M?4KsE?zTX@}PQ+{UA5&PfA?#JvXE2GntmDqyd}?!a3Mb20eZZq_#sm
z``uZ&w4O~l1nPMg;^`jw_v%*>d`;`iNJSejQd)hegB}%EV`)XlYc+4Fv$g=>XW?fx
z-V1gpMupVpqh!g<!p4zwN)udMN0Kg!k5u%v-B1%^V>JL`c%dkCa)5>2S*PO`h0@M_
zP>gFCk#SDHO_Q_ars@v-s0$Pl$uzLpS+Sj$t5kadc`6Wq$-ey(i_=Drj_6+kcxA-u
zRUBfqlj@X1wdXwIM_vhIoj6!%?-R)oDyGCbz$gp446oM4AmZp$T0~Id6^BZd1aM?r
zPj!<$04X5RTad$L^j-(40Y$1%uLhSP=qX^QBWnQLa>>s!fdqV{X?4;<zZ-KCtC>_a
zM!ZrO#8HUs<)QHs$F~PGb2uaM2nP$<<=@WjDscQW1m{C-_4yz%F|dhf7-6MCz$%7p
zv<@j)D+>^I2&Re;jHK7j>OiVi*g=iSx)2P)Cj6E{7R#MiFf!6GP9{ZI7_#(QgaD&@
zFSbjCUnLmz+;pr{SmzXpDVUr~*9Hbz`YhTjCFW7rwxQ1;ltYVoCbx2=M5tXw>D8GL
z+Mrxqv<-2z6LDj_y%rj+cTx^9fjp=bQq^T)vgQTAF|u49CQ)3GeSmn3Tfvp#mpbk9
zG?la9biUkzqK4a5reyKBikrogGQfoAD3WXIM^RS07J5ka14XVu>K-Tc8UKcI#ov=L
z3HPK4fkFszV|>!wv?R1JvHU3y&7In&V{$Y=8%PK$l>(!-9$5uQZyl~Po_nkQc_OCf
zpsi^y;Pp)Oz2b*kSUrbx*i6k8!A-DQ>`)s_Ob_IEfT)0!X{`!T21ZkB^W&Lt?D303
zL@vm<n26-Pcn#BzRaDlbVR$28q2Lt|4nY$L3Aw}H3^g<yIwK7$OCXd`*ry|`DO8<S
z@pY#ZIrIxaUma1;61^!X2VH4l<M?p5IEE{YX@euA4VE03xyGq$D1QYLa!}ux)eyZ+
zW~G4<i1Rg0DzO)_Y*`jUsnc){=eCb(luE5#i(^Knl8DzEN_Uz^5^My|cob4<6vd$D
zkAxAK|Dah?$9)Os{j4G~aEQQ!vK<(uWSSR{6&6oaZRMs|GS{Z4K+eT(wWyd05|2Z5
zc|%!v{lZj27C}&DqzT5j7>fvDK{|vfiwsPQFv#wppzoq!Iz}pJY$g?knF}Z%?s{WT
z%PNd1Z=0pv8=FZ)kgk<nPkkupr6o}iE0@^^{izC>amPcRfvv|cUYt4{Pz`#v8VIs^
z$zmiFcQ6yx1->w_ZPAt7wHUJJ(e8mVbkLf5W6LdDC|5#BviTKLbL8Eo@v08b6>`&8
z(P*c{0?}}Gi%TJ>C^X}O8#1=g25=dHrF6_06RHk~!t|OsLIyOqVb}6g6Qqc2Ru->i
zL%4P>pfgA!3$BS>E2u925u?%?i9LwH(3kP16Tt@Ipj%vBr?@EgcmW;c6f&XkSg~Fa
zE!l&MAMQR#P<KwF!3>6Qkx5QYzhu#Zddt-WnQA5WEbPjPZ%ubxV9x+6_|RrMFC<eS
zqlVQS6`UTF&f1?Ns|;D~A9d=BYfW_mKu=LrR9#%_m=XPp@gd6Tq{WE6AShw5ML!U;
zoKin&pwL@@!Eokj@rT-oMB6GRpIQ<AMH<wh?vf~YdJfW)oV`l&u2ENxa0|kW*=Nb@
z)rxemQtJxYdN`^QhBc-QS%vsiyl<iCR9xVJkQw-npfzS(HO)Kp8|}DsJ~k?bm$4L+
zacjp7v@sBPmtoa_T2$5{j1A~G_F%WLUD$1T%F;4y7X{iN$GuSMmQ$*IiL(fiRZ~a~
zoeIV@f^i9>*YomWo+ddfEmI2Lc@nq;O0y7GnouK*7vBE}XgmQNyzo%$NG3$~h@~wB
zIW#NPxw?b6A%&O7;td63nl4SJTO%0{7^Qo()C5bMm<c{^o{Lp7cg;p=1Ah&-A@%_u
zf~kxBV2fi8OpA}seB1Cc@yj?vq*Yo_E_Q9w%(a<gGARhS48cx!lo_kMoFrl<5aRXB
z)5^O8rE3jKv8OyS@0V#dmZ(grDu({}8D*v2d5!T|JQ3Nn$5T-n2zMPl%tQ#PQW$+Q
zy>(HS!_>FNv*M$!n0Aayto*ZiW?dB$8nlyoO&l4*0rK!45lJ|*D6ZYX^ME0Y^I4f)
z;FL+Bi8LIhWT7;wgsdA56dWw|8Xtycmhs4$vDHjQGmAiQ7fet~5V|{)MIdu1hEtFG
z)W*OFZ{%_;k=8X<Nh8%)dSyV*>8w>rX2u()B=1;enQ-s|V(LbHy|8|CDX&PPm9u(d
z<^&^)G30pE^fMicqhW6?O-Q#ubkUa1t&JF7A(jRY6Az<woaC_w$C7t$zi4fZCUtkW
zToJplqAD$+4qaiW-w(1XWcg;ind1|=(lW!)`JRtvitCD^hPVoknA{ppb-CMi=)A~l
z8(Cs{O(pHUS|z7SJi70RHZX4*3bUy{;X|L&Js$n}dzZ7b6-kG4IUS@1qZ+5UmT;7c
z4n8T%CnDRxC-&VCb*(mCRd}!As!c1VreV6Bqi*$sCvh&B#TdUPPWqyIc_E%(H|fuf
z9Kz?t*)>mW4XW@vfjfVKJf7MpNTqkxFw0k7#7ny{T)T{Uy6=t$Hu~O4?8m1rozm4z
z^TU5fh1!W>*)5${uoG(Ocg1_Lt|mQAs)$ye_=&zzc5jDmw;4EkR6C4V%o6iw6^Z7h
zdFk}L7_qBd-C9feHf;y=kTj>ti6-e=RAM^b@YF{xzNM3_c#ABKWZ_OJxj63PQ&4df
z^<b#ZFDspwkYAoj?=`*HR{U01;H~xksJokK5qg?|eGfA`NKbSu_pin>3_oO8**M}%
zBTh>+=a^r0V*e?^UQt31%i$yFq`JE*#?;u60y%tws#JfpF5VcGnIPwqWSRajM-gj{
zd>@aZW$PwAlk<|AHT~?e=!uQHCSAGl4YQARvyZ)`wte(R_iXRF`|tXXJ$8Nn>_4sj
zRGv8gG5f@l{yE3?^-q6;d~WL#rEl0zl%)57>3!2@A9dHlpOkhk+*6Vc4Ievq;o|43
zJGVYvlg`Og<NYS*7o^WtXY^g_MmzV58vE^+Tacc;{usXFbVa^niO(OlWY+Xc*Z*n$
z(%PoZ55C23+HXmJ_v~LEK=@}Hzn0t3d1WrWaD1W4`}IvcN!|EJ?vfAx^MZFAc%47-
z<G1(Cd3@`REx&y<T5$L;H!c41FQ2*O)ZZ1qbJ`Cs+IHdRPW$BG?bCbz{2!a&z3+{0
zFTds3UNd*ms>e^eW#Pmzi@Tm$`~B*jgXgS%X7{l&_TIN8>#jRt>aEvZKI_TLFDd{1
zg8!Oz%5TqzKDPDDb<KDGb-L**XHNaE74Mw-eD4eUKfeBysqu_U-hBSD<+Y=hE>FJo
z<8x<z{L|+ic+*e!8+c@Q_v?;7>a6#qw|s6~<-Ouwk-vTNoMTqsziHuFE4Rs|Km15K
zXVK>-wrsl5U;pmAn%6&h*Vk8fe{OJ3dd0#|7XNeFw)0;&b$sgYqw$TGCYz7!JoSP1
z9N6<<`h$xm{_4TPvkMQY-gV(!XMMDB*;}^Gf6t-|zxiD6!f!t@>+xeg7=5ww?l(Nz
zchNxlzQ64H-u(C1K7Pj;=|3;L#NK)F+ZH{a|Ivck7oD;C(!qa|!v_9s=&RSP=<OU?
zz5m}fHoxU-J2oDC&gti^5UIUY&klY3I!tQp%&Du!Prdogt3GgTVe*w5?Y~riWtPs)
z9r9NnY+i74eSIxmarEx@uD|fXul=U?lfA!QX}<M_(rLYSx_`U$+P)9oGTt|K^Xm0G
z`nGmH_?}0mTxB24A8tN5vUBmf-LuaevuNiX3y*keTK(kD{_5RwZuK_@Z|nTY!1Hfe
zGIVFUe#uGI3-_P1;5$=a+`hEys@r}qk6*m|FK<5btJP;#)(-xsJtEiFe!cvvxxZiX
zgU*+duI8q)mBkGHMpW(#-rrc|cF+6V+EvB*CyZawJNBj*Qt$Kh@13PXZf{f?zyDlc
z{i!t<{o6qKh+kgw{HeQZU+vgk{_qJ8uGm!CeaMc!TYk1N{dwsV``zk3wPg4F-Q6?X
zH=|!2eoAud#Y^ntxBHnhsu!le-E+avKis@#;NFg}cYSH){ipo$hzkq1uBplCd<Sal
z(%;wbJMSBx+Pd_i=y`KDo1|j&+|Zxl+Y&!k*eb`)Z={DDePP;_U)9Hh#GYxD%G7E#
zzN)+2-QSlt9Us2JbbMsXnuiaLhx@u4!(ENy8oA|t8%oLXQ8X);>$}NB)Bh!XY{lCK
zZ%a?LXC86&y=SEN-?mW}<*qeH7ymZ?__7D%59Ott&_a&u+$`TKZ*Clx^e;PmU}k*w
zn)eSSxnC5L(;kq?=RVBLRAuWLVVA*8W{-W|+*S2O#j{rQo3mC7(O*b)>V}!4t5@%z
zOGjR}tkQeP#Ve<6>sZ{ke`%;XsWPqSj8%)f#@D<lox1GGs&w}DZ0k9r?>6~j`X_SB
ziq|ndd|^SdaI1TyvPL#m*2(_8PxKwI@cXRaro>6PyR>{-^QO)A@j_QTx!7HvTsd*U
zSIuQZUpQxaWuQ+g2bVW<=;bYk(Tm0lbGCA9^vl90qyF()IoV}bNVD*bRlE2NiTd*L
zgUi-@eO<G>(n)1Yb<gqB&Z%~;oc)dBy>I^JeU<8}-rnn7e(K0QrepOfZ<_XvQ%-zu
zsWg8$sSenYRsF*wCeFRdojz4cE29;wm#;|O<M9f&!Mn=TQhHLMr*C45i)&j3AEeiP
z@ZDwUtMwn=w<^8BuTPeb*52TD*JRT7`l3R-&~}-}Z1|4TorjBz)S~3UnnWYb_pVGH
zD);s~%kz;1rZO=jLUy0jy4;8#SaL#Sq_o70@8_htT%uFoL<1}_D|mCYmoYHyEtF5F
zuP(j)h%xt;^i4_cu+ErQlslt-SL`WtFWI`sNpnr9?5efLoJ+SeCM4xmHJ)zOyfh}p
znKB%4Xl1=Mrwp@2VdD|z3d~j*Uux1dy=J-|-on-fTQeutX0Cqd1eqB%`^(~}c^x>o
zvlOyvb8u+-#$r6)$DyaF*wmjhG8NXIyA1<Zu8FP1))&2;+V64|p20Xx+Qq%sM~(w5
z&Ma;1khmzFN(tB~(&>`Surgqak)!eQ@LyjbkL<8SZpaPTLmVfCCAAE2>`+KkWoCG$
zhgyToq_MI_dHnZKmqTK>RNPp72b3<EHF+>eR?7rOm3?BCQ67rgVaO+*l?*VQV7zCJ
z#IHdq%vjR6ag9j_20FW$I<e%uZ<(Sy^85n2F@4dR?;iB%Q_ny5f}VMrt!JLTbIg~2
z_52rKc<JazpFVKQ$zSUE-a%jd{fl>e^|EK4d;YpD@A}gI-#g}o-#vZD*DibU(K}~6
z@~&TB{rxY$@WRudf8mYK{QHYbzI*vIpZ)3^UwHoMYo0vrng8{f+z;P*{oP+X=HD-S
z{D$Y}Jo6uiAN<3gJ$KJnKmXOs|JTO}zv;3`-~Y)CZ+r4L&t3MJ8!mnQ4^O`A4KKX!
z(RDA}amM9`fB(hT-*EC}2Y>&d=PuDRLYsaea>Lm#cKyrEKm1Gky0uMz$PuNKnIi`W
zolO?X*rYM0Eh!4^mW6VFxyp>12j-6F%n^OO0>UgaSBjd&E^&5H`uqNrY2~UV&AGdy
zbw^s+R%CuLzgyPs_-O9gf9UJ{&W+tJy|LnAc`|yC`T0}q`&}ZdB#xTsIWd+eee0&5
zXuCT<QoJhHQ$&>m{n27Ol)KID$fZ{0{n*)@Rv=&B!5R%y<9ao)BvcepOz41D8bXtz
zDEM&arfdSd7Oz&6Yq{#|Ww+Opaj-2K*K&DQ!er|8d~-4Y)JgUdZJ$@clKFiJ&-<iN
zI4_NxTl8IHCsM-HhB-_&pSO$XvUDB7*(avZ5{)9VF3LK*#G}j-`z>Wmhq-gYTN$dy
z=^D;DGSFw*(me`}m6I=Jk=&C8(Txt9N|m;!Np@=-fH0Dix@m~FMX{<OmyXzBSF*H#
zda|7O5pf+%7HdALZCmZcSQKf*Hj^$dYurSSuCg5eiPS!u;!9kE;KY$=!l?`;_A<ab
zD^Z>xP+(}08W#od4rjQ(&!vlGdr^=<p973bBO#(<J+VwrW7X@&?+*c=%H1pQQAV}W
zh^|9*W_TT{BLYp-IJ%Lj27mSN*f@2LB(XkhF-|ySMwD-o+A`xtX2SG@hJ}g5FxXR4
z(a<YLZDg5c#isNUm{Wmc7O$dkCdgQ&cE;mM<WmG!FKC>|I$w5QaDil??7D1qlEig5
z4M2l#q%tJ#M%_ZwaFJ@WvUb>z8iNN@%CQ!Jzw)cN5nkygS8HWZSPzdnV){9Jtnpkx
zqvC=)QBx;Uz5V3R@L8@{w@hlOg#GAo<d0L;BCy_cD*;M?h<t0fy62_HAQ&zJQR9+h
zjo45v)%YDLb}vB>vDU)LL|}cxJVCUI0jDR+RHdHy0N#eOViJfKQU7JK7;Hs`V&dOq
zNg=Fh5}zU{P$VGT%SK$N7{v^8A!0ogKoO*<AqSR*2v)0}f6ro<C@>`q4_aNv@@U$!
z7}gklIEHEiq#lPwy5u={V5$CI{Om*ofKc_}Lco9W-$eeDekoxrQtPu`HxQC#(&FW{
zBoUuR16mB!Kq`tx>1{p^eOikGd=L&FK+f|bC3G5!l%qAGXO0DQ0Oh4?RjVqntS=SI
z&5>+Cy_zUfj2|ctffz+2;FN8Mh?F)Wt)9Bnf?ADq6MAon4804YkzOH@ioW4&BLvhi
znzA@ogu8xx1gP;G2ggX=;^bUQil7G&3Wh&&)!bvJdgL`iu;DpV4zz*|kDD_7p033O
zxl?OJty0C>3pUFyd!{iAIwC%(yreWeTAv|-YsnJg(1_w+8&D__Hstv-1yWOP7Z4+X
zA~R|mFyV#@w0bj8<593Q%B&<+Ww94p0T06VbI;Pn-hyaJXX(^v-P$HIuvCKjYa!^B
zEJUG{j08=!YD?pyA$E{(`363EUUY(LAmvBxi>dWY#vHO47ZaZ`im+z%7&zhcB4v%!
zw>O0&-`uKJA{<kq%bAj?Ra+^1bhFLz7q{(I8+{UpRViL|*8+$Miq^W*$4=zr^{zEr
zRCBhCw!MNPhMtZnASzjwO}w(Fk|8FYD`&94DOep$#<{^EKxp~!i>%F)2k|k+5UJ67
zI6`GJMQX?torpf935rx%t6ZAB=51*uBiO6l{y~wuzZUS?!7xTDQOsu+lr9)2oorHZ
zI`&nisIg9x^N7TwB?L%`cFt386g#a=hj@dGOWryhNhY`r3g^j)0rY$heTGCLqlAVj
zxT{!ZTm00zfM*h4AIC*6$l?{lIRI=SLd04ql4D>hB88R}Bv<61MF7oXsrZI9=M^21
zp`#;S#$<4*IP2Kx(%?9Qo!b8(@>k6S7}Y>TnOI%2*=WIp?iDFey-z7gtU2*Qc`CIC
zWB?K&=}98LaUtBkg%Hh0UBn1v8fW$P2f(%PHgki$X|AsV_BGq=f=)6Dzn6-+P6ln)
zhoDxcL6n!F%>|5q8SAY22Li%#ca%8_A-(NQ1E&@?JWut3!s?x_oaK|M4YqCimbx^)
z-KLGzfa>l~zN$VVT(G%U7Dz>QZ2_#3DHy&#qC*w1m$k#o4k_U{<g1Ci_~C(!##abi
zE&v)AJnFaHhOrGVrC<Sy(_FI{uW86>!fC3+JB<NqTo(LZMm>%Y1;7-gw?PE)US)9V
zmCTZ9(VB+Q)mc2g6&VhPX8Adyv+ocq0gWT%-^5G)UL9>biD7e9b@xC?QIt2vF1>37
zf&=ej4WHq%T!2%`j^J$tH5P2^W`dW{7?)M~{x>jUtqqx~94~`YuO^FSB-n{&<JDFz
zo;E~TyKb9BK-(5Y8#(M0?QE94wrN6I2!Mdm#@mLH#Ye-$@gA=u10b;CMu+T4sk3m2
zY!-nNc=FNEcN2xM8AMsqR;akRjSuQ+%hq<=k*@8*-PgYlTI{}o|DXK-T^?<j+iqKg
zr0r?Be=uHkvEs*p%DyVitAno<zc1f?{jW~@>hSQZ5rkhWy?qV3HtN;%`_i`k`_i;=
zn*P=LQCzCJc+)?r_rI;zHcuBQv)k}K{@3!l*FwGu*XG+s+m`2l;@zg-*L^iFjkEg_
zyoSG>Cb+7L-!O;R2i!jX|68y9BNMh|QF2YA*K2`&4dknFuMWRPlK&Q^vLx%C-%Inq
z+0H)wNt<Y2`4#6{5w_*->%10D<Npv|<JvIX_WZwa?f;N=-}1h?T<xT78mqdv?VWA(
z-Zt%8m_L+W<86zk?fidHwm+1g=A~B~ES^6^+osvqRoS%6?Q-uMx7V+_xbKm@!F@fi
z&dcr_iC@F7rcn~7w|&6w<KNf2Z`wbGX5X~?`uF9tFaH13Z+q!izy8;Ili8Nf?Zy1h
z9{UGK+#kTV(d{y{-8TM@asN-!47V8CKZfzEY0kOr6&TI8%B8MT-2uwqayc#qjZ?5(
zH7?h3aRO-i^;~Vb4Esvk8g3)^q1zW{Un9PaYSStIed+d%-xsg+`-U~0LfdV(rFOd-
zB2Lrj^=eR@<tnW`gn2R#pIDhVF#4ED!TF4DD?K6Inhz>sq0A~T%o)k4l+jtM6g*hq
zV!dzGUkp(mpRPHSd$wo7rd-gs@*aXkL^qJE{z#A^OB!ijFT<0+c-fE7wl3I&vO8S8
z6xz5f^m4tn!~43LztaC9_(O58&ST&7uTEo$)JqOHOYg4@kALzNct=RD|66#q41b7^
z+R0wn(iOaRFJd3htK`!dyH9l6`&u}S`(x#KE!w>@KJp`teg*91yXt~h;Qyz9rn6jo
z)9;f&@olhe&mZBod9__pnf~>kUzu`m<jZJQjO~DFd(^dU6*~>R0^BP?tZUnB?JFZR
zv{!v0D&p>f@3n8bX8zrW+i}LyB75~GHdsEA2U}~x?=>h3ueuBJT5){wIfO&H^@?TB
zca?ZON1$l{FB7aaNuy1lkfVG)))?idFepupC_3)Lq32efE<a4%1Q!pNg#`HpWN!(_
zU~x?qKft~YBC<CXg`f&y$H=Rw`9(SHi<ELAvYK9_c|5|NfR>}8X?8-U@0|?bC#N{>
z7=~RlC@_umOX!-NBbGkP3tRpwLo+-?Sce>`>TVTBw-7b-rW(zPTk~&0c)85B0>j8`
zTKw7s?aI<LO4m+1fgjKyxn^-?^#H0rcq!DlycW%JeSu4<+q^WW;KM!eLB5ycZHDK*
zk3~|GFXPo0k|<9VRkKn?0cp7_a-6GOr`n@vcs3Ch7h2u^P*AY~3~>*Em5+sRf%`C5
zw)-9Ij&B2@+W=ngt&KWMI<I`yuAC#GBdqZiZccp~=HJ3j$DeU9JVw&n;d)bG6E)a5
zrtN|p&YOVd<`FH=J@U>tSZe$*d<Mn0>{=fMc_BdvYxziJtytp-P{Dn@u?H98TXyFy
z64i-zJ2eJ=oPZ@5$K1q9lWc6JER9AmE{#%w_$oi2SC02+NaYM*F=<rX;lRa_2j@Z}
zJgL)noj09>mo{eO;F2(M!54T?O%tKY%HVkoH$<@o&Tn$@Tvj*-ipPiibjP^PKOwQ*
zu*a1W7Spm5-*0MBdZl6w;#%FZbOSZl$1W)%MhUbIT}5z|xF{v1^iih6QE<jfLvgz^
z)=~tg5cX|Hl{A2Jj`UncH=7-~WcPV+t4HjP^DAVohzP^BMF&X>R@EU^ur6wH20!S%
zNjUA8Xy!>HlsV{Uh!f)$Ntv~j{iXL317EMll=*>_k_Kfg;@yNqb&LQF)B&{~x$f=|
zXJG_8Ue|8&>7h`Ee4D~4scdsn;`uUG$u_9xn?SlfIS&7_q#lAw+sZW)DPu{*Z8yV>
z5yZ1mz(!F#d{gjogJ(z0bGJ1lL0^fH`&Asc8#Qe+tfUw~lFmga9$%Zt8Vjx(J3n@w
z#JkCa_q@X<q*j8_CnDB4ypH#T>ZHQUYdua*94p}k5{JTha2>_k%kpysL$V80)KeK6
zgOn6liGowz4dt3}<auIsoHr2pXurPLK@Hfb5WX#O>W`GL#vvRmLJY~I1UJV~S!oJ=
zsZR%Z)3hTL*Nh>Ii>wsMhKJN{>Yh-SL$*vrPHjk#vW{-~+5_DK<&kLIYoCU%#5YGn
z@$vJoO*AoX=KZwrvh^}liwbjj<mtVd5bCXZEq#~sKZkq>uR{Frc}dw}1PyGYNN(Pe
z2X3FTJYk}&8ZZ=LJa(MfNStHORcQcz#f8JsFw-Btk+S%KxYvoZIYf7GN;i;eZ^eM2
z8(qV@)1-;li6N4Ij#(cvJThKN%y0?i$N<z<hv!_q!~3$-`GzZv+1hXr#TQA@)OYqf
z!Wg9tg!*;Psq$h%1BHZIY)ZV%YJk+lpAez`ItW2&X50_QDSfBo584qY2fJp4to6w*
zKdfU%i%`Z|rzY@p)UQvljf&Uter)!*zDBSqdtMBwyr;jr{~Gn6T=Ne?SMD{fxGFrU
z5{}L(vK$WyR+dmMx~Tbr6ui^T3ki`$vXW6N*N-e2uRRuNV&s)Uztny>d!sF^OBC-A
z9nQom%)+SRVM<?KNUn~La*(wloalQ$yr>Z=)dJaER5yUWTmF-u;e{%Ix*nDp(0Ub|
z-dZ>%h(OpZ#mn!Ef=@=pL`|4wabToEMQKtkB3{oqDkr0OwKIiNWV1C|2q~tgy=H5t
zvDj9YnrRrw8f79mT0#gs5|{DjHxdWN+wJsY4mxYNb532TALLP)P(Wl`vw*mw#qtQ2
zmN7Pzro4jc31I(D+X-Nm!!TZ|l7~5y;FG;ue$4@Ryk;tj!|s$DJOa=WfU}s3i1Ugf
zMhA_GL}aBY;|!$%LJIJzw>|3SMQq4`_)G_}x>pfpiU_GLY1{f?J`%^)I>m>o!(Q>i
zL`!0`1R9PryeG$qC!z4z7p&T!IQ_TW7*T-;qL{8T1jy569_nEq7|#55A5_chS}yXz
zCIBcWMrs6FcE&fN*6=HRw}xnRL8qQct(j2Ksl^3PX*}MTp$o?u^(PVB08}PO>@>tb
zV7aIlJ*-2g3*BDu-7fQ&phc>Iy)l``I9iPtuU282SzV&z9tur+$~Y^f=d#K|4?VO&
z^NGD?4KaXA7U~Usf>j)#?GsYW+1VB)VIE^yU&+#Hl_Nx`OGpAx3J*)oBQV$Z$oJc+
zQ8g~IQqW^hC`P@)2?f(74bHc=s+(+wKzkS{2R=%Rx1zeOiyEw7&W|q<fj@|6S~erG
z6KP1+EFMGD4st6&H^g+x5vQY|Le>wHUaQMemoDTMcxtTXYPo2h93~6d;s<N#M7&BJ
zNNLwz@oAkqz~sT<Kv$P^R53tBi9PfKR+>2Fevpk!eos`O=Z?5)H8@O#=?&-}QkUV0
zQKn9BVlT;TP&~0pSNCAG%<xiOhoGY3SiO8m(4xOsEzyNq$(Siq#_9k;&GhqHJ)V!e
z1f<QX$}5sN4(ulojxS-OQXlFu@8*V&y3_a7Rr**)l|a9@#XP2i<^-7yN`Z@yd04DM
zayBi|`VEbRM98Hhj>jPzilR3~Ywak*ju7<f4bM<DDp2Z(Y6<Xzi@1JVBgBU&=Dg7B
zY$VLmz}s<plz`Map*~`-4ph5va&&*ToneSL1U}0i7IEk)NRtU88tJsl0n~!)nNRv~
z)ieV5a3`6E|6V|i4TwnVvyl}AjXJHFR(aI%mY2vxlLqx=ESb|-unHc`pn4dt!#jFT
z13+Cn1nmz<J4)D5fq3<X1|z)0^=eqL_cw#Y_~@cDlh+bxFGc<iPZGE&3czw&g&RXi
zns`014)31RNJPA960mx6!9LWN7B#54{Pq_$3^4U}>Vnf`>Nv0dCUt@{MiF~0(rT1L
zHb8%Z3F2tI(qdi&Vq&!qE^A&IYc$tE=sBCBVD)Tf78Q-Cj|5Pl1n*k5U(LQ51>OY~
zyR{^ms#NBtSj!cBKHR0EuHmv8>r^=C4cftLYFRLcIW1KoqL@VrE-+GJL_lw1ye8KM
z!=gm8SfwqQMo_rNZ!uN<!3eCxD~YDimV_I0x%8?)1cwj<*LGj3gaJGQu6W-H2_y=v
zj(~he&W4O#2y&xgC?dv3{}g-tZSdM3glw=P6?!kka<B}vLk;ziJ_GHItT=2ml%h3{
zA0jg3JDyQF=vCVuwC2#Tnv;p)MNnfXwF{2cGyuBc)B|V=E@fEbYC|m(qvk+ZE|>vm
zO6f_kRr_hp(&>$7$66v)RvTiv0*wXKZUa~hLpyE-W?Jfy@AzJ2Xw^o_!ngR)IMaq#
z*~pl=6<vnJUJ|bhUv#338(a#G%R5b4rN+|IUalZx@gxRJqGW(^!@=d&#5#uH#6OVb
zZ1L&EU?+~dMNAi~F9acqP1E>xMe;%<0$Pm^RUq57fv^xp;EM7c;-^atT)gmBkw-qY
z!xjX=R2vqq7?2Bi6<>9snJBn$_xcX>$HEfCId3(8OShwTYhcQ<jj!K@<pyoZlcd1g
zAewSWr;{>}<)vK}33`*RQ5YmLlb?|TCKMU2aqSj>v~1Oa`ooClvc!l*jCXOEsT#Vw
z3AhD@`kci{w?!K7AX3nuDP>lMY#IRXGhzp&`m&5p#E+0n^^iZrU?(9zUMvn^o610K
z#$^mbZJ<;S3a}1i0h9{x;ZBZ(L;vobV#(Fe$CSdi5B@28&PH1aMhBrInbKuh>z!3<
zyVx9N)F@@mKYYU#=wsiO45DysP5Dsa5M~_t`MbasAr+?=;6!yr20jF_T;=1ld_p`i
z5b+nlxpCNpjL|6>xRBDQE@JQ=oD%q&PLTsdST|rH_8|#`YJ${7)_>9_G`|+#Cf)%q
zja9s-!PbR*fX0~KV-}b#h%$E~$Qu}dA*ZI^6%wQNdeTLBVaR{|O1u!I4!20I>U#LA
zs}TB0M@<B@6g-{`(7spSAmUqb9&Q#^A#X+st6#WgA1NSd4@Ad}P^<_aS8v8fe>t;d
zb+B_*M|tvNtA8{|hMyAf2ZIc9#G5i7-18b%TDS#YQ!H+)#d^Hj&j{Thz-Rn`K<U9F
ziPM?0iVJW2T0|3t1V&BX5C)m&uCivVqETf*B7G-6cZ|jX-uqsOy_fpx{565YsJ31d
z)b))~hK!yvg2l^xQmh;LuU&8Ar>=SBz24>Oyn1&=bBTC6WntMzaf60ea0p!NSyh&S
ztzFH;?qb^6;D=$NGi{^BdLnYX+TI=3=9T2?ocLvCc-^_~G{2-a!%k44X1XkmT-D!m
zR(XK0WO$#m=a0Ho-sRH=22*wp`||PT<@v}}^5yLtWFVB)rP5qiVXfkIh2ecQmU36$
zD8(8anPf^Rsm6!>q8-?;<2{;)wV_L{fEGLE4@KrLD6*x}ksRMN8)Xail^~0aiEs2q
zV{};qyvxy~J#_PYWUNa{qtX$(QNPrcomurOwR0mCsY%Bw%eS&&s+|R9uDb3%qA%Lz
zi(<+)9!r~*Zp#7ho{6tJYUUPWo6O(%=rDRDx6M6rq8yx0Txv&~&ZGaeY}M2!e2;Wg
zMZB5myAK}gu}%Dg(VnICG+q|j1(vB}Q@Ualkalru)LP2W)PvWvU1_w&hkm!{kD-h6
z%gNQ60qKoVGzZ?RuG_zbD)tRYmikK5xJtvAu3;wO4&&HT;I~$4#`8h<id4K;n-jzK
z?HCUIt6!CW+{QkyKXY{gMexaV<J~e_%nM3@hS4>hJIxOIy4<(1?wFOi-horhQsSH#
zw_%DGKcB<dqnN&TZUgp1On$v7y4cip{#iM;ueMHdJHk8rPv6QzmFai=d`IrVdm7*t
z&EB!Dd(Oi7KP{EM@|bjN=<i!tiw|5l@2Am4_dIsWvU|3jbK0TZU3~{VBX|GovGm@%
zlLJ>3{5gGVo>?`1-ec8!e^fYg+Wba&M(2ww#%u4dKJ->uK6^iZ&++^9F8}V5&hkTU
zL;2*TzH?LOto~|kM*qX^-WkVFuFKE(#KHONW{<3?)$iHRxj}a2`lrmQ&FNnMwvF{&
z$1nbE<L33J@0h3Wz@Kmvz06nMaquJgTZR_hJaOX%^NZU*xqaGCKfUIt`Fox@=4W>u
zeau%D+<E%a3#ZTc^JhNRx90b~tJd`1c<QFpj`()x;FnJ|znFD;=?njy&pms2ocqP^
zSC!VC`S5wqE&lM)7rw9K=)1mq&Y{=8`MZZsJ><Yi^A4S{U+%F3<tMvl%9-}t2VXw#
z^nphfoId%pz1MYbwI=y5drz|8r#8sCNlPko-v8aT&kUUzf9ZkS559Brf`h+s-OYdZ
z)G-^ktGowcWFPzN?L!Y<G=1n(yS8tCcKO7>C$B$p@Y5@%{`9G9kJ@$Xs)2i+zHZvw
z$B&9i7vEkfzJGCFZI=J`-=8I?ZaDw?Z+9Jj+|}~)k2TzmzK!McA6-_ey?sULPp_LX
z|Mo3Y&mVqn<j@6wwffLgugdNB=bNWaT5|k{+`wBu?q-!v&n<S}%59mmwENDZmrnkc
zTT-~wMTN7jT;l%m6FGTg<V<<v^atz@f4<;}ZxturcKg-4=ZgGvyT1GW2G%fh(){S^
z$M@7fz3TJ%XGgE;7_0Q&_nmL`Z@TsLjpp&&i{<;OOE)h2=(L|c`M#se6E`1SUN*IF
z<F&s}J1_mqsebKkGu-vPQ_JVvFwI;z^Yr5UfB2U9(TOfD{_To<@$Bi7FS#W@`J!b@
z3&(F-I_0Rh^~qQML1gjN>tz2aOWhm(^|Zszy|sMkua+0(2g_qQdik=Ul?%#;s$8F}
zh<vg6Bl%`+t{fY0$-V#U*P3DX)9o~?xpy67%TIrIhiR<0^<7)@SNwANdN*;OEE`)m
zTz}xRy}RzJb|jB&i+uT#-1f@TIlt}=UpI$uTY3ITM{k^W);H@i|5%@V;mYx3#oP|r
zb;ne5QFmT)AI-}_^Onir(-pbo&`S5Lq&oRXdrx<~=bOp<)~pyZGfo?N`&~22XFhg~
z`L)f(*UOJ(=TK}uzK%wi4fF+lFTRs~%D<1|!mPMaUtRZ;*gBltIdjJYpFN?r?7dgI
z&F>tMv3Jj2c=fl24xN7fW;?cYW~08naP8rn7Va>cuHCUaJz%&pf08Q=PM`P0i4PBq
z`H`&`NTITh53$@+-`%@mzvZiz9%5Gi-PY$jqw7C9HJ2=R2R$)5vv`r6F}hx+@&(?L
z=KXnjW#_bMX|5-pzU2PV{T&@bkga1#<oqowJIw3+W;ftBo!HEGc9-+Xy9a6`#~k63
z{}?xg^Qx@U%-~1158HZv+jhUSzux?5-+1G`h2y(R+oo621A5cl>*t+t)q-ef{F=Jm
z(&dNtjO5F^tb8TEVa3u96_&Z@S4X)O7e;Z%xRb-YE3GO=vVLtxyj;#YyeuPgr>!xa
z>CsaD*Qo362ck)%t9FT;JI=UQcO7$k-O>l{%-2tPmbuC=7+IX1{4aYpnpqR3@b7y}
zLDt3+KQVv9V=Oxceq`kMwPKF=L@oc;TTJ2M=JfxEuQvgcs<`^bPgURUxibuKyQhH$
z305}^Hb}5pGy@W-ZW?S5LxV&|VzdWG92Ip`L{OHRW{?q42SR*N-#2MSg2WhOP@_?!
z%_1-E<NCS8hy;xbDxy(#zTc@HjL-jjp8uKYduus$&Z$#Xr<Pl{Zgs_i(8NDK6d?WA
z*r1*32CA<HjV%0geaL)#zc(SjvuEb(sLVHPz&Fn}1RC;R1?n#!DYx$XI6$$1A@Rbj
zfbWF|$hRwx7vvhGi7yQIe{Mf|clD~%ye<>Jf1MYYrJMq_l)pnVd;wN+nvBq`$}N-v
zGM$%{-YwndiX^ugNlpq!{%w|SV4c^ZnnQtjy-ZKsOQL2Sx&Jg6cwv#qzm77czsVPN
z8Y<SKzr6bQ(tUno$g~zDMZ;2D^oVpO#Yv{IP9&tHi|&!7gL#};ktHzzpD3trBFg8f
zpowIIB)Vvz!_OuhnqjCV*P(XSXB43;;dl0j;+@XaWErHM8}K&H3Np=v&SSg=b&OY}
z!RWNoD>$wz)>IOcY>)F2R07`?$)o4gM9JT|&B&KY3sVS`43CUxBGxzLPVAIxbqXXX
ztsspQvJ}7&5FNiJp$tuTQ#@~xnlRSDf(em^uo_Me9UWq5qCxkyO&BVq;3Ix#|4#19
zWXSqC><7^G2X3qZ<O{NIwUI7WpVPdO$A*${)Ow+7Mi0c8q3C#_)~>@TTkS}12pWM{
zqjy#=!#!NF18>z~urXWH8o5+BPDO7@@H_b@KZU`l+tIYN+Lec{`u6Mtv)|vhaNqMs
z!MA$T6@RIGYu?jeABKPNp>HpIeDT-o-n#y``xox}a`D&$U;gi1iyvLS|Frk_FMMd~
z;-?O6xa8@Dzxv?7ykkcWKYHP~rw&{){)vXywjNph{^5n+T{-UY&oA*E`0(!ftLDAC
z_{n2SmK^+icJ#o-cVBvB)ALJCJGN-t<BP7ZKk&PEuU`1|i%Xt<;^OX)U$JD^k+Dd-
z>CB^J4}8@9>8q|sS)o4eBI^HFqNf)<G$=20AudYVn>8`5l~a|>(L@KiH5gQ6^D_Nl
z-pOOc74t-Uf6B)yNRg9_VQeM>)H41y^;op0e{eKCI85XF8|f@vAD0#LXQxR|*iJN|
zr@t{SeZ>Z;`%c8yQ73K}B^8V&^P#vm5!3F8OTm*W+WJd>t*?|pF)OVKii+3-*o@P$
zWyXJ8-are{NCI~Tt`=nQ6YTgQD0uV_0~imhUN*(?<lo2t08?3l&i7HM)7EW%5Mrxv
z+0XNq{};eT<A5Z7M|#H$L_07^T)!Y@Mko9jDQd1!yaw9ZB1)jK*->FlZDgu}f{aPj
z_ksc)nRS~X0mgd%9&y9m{JI67!VXXrqdM$A;!~UfJ#s8nl&ZM?<70aGhzXK~i{72E
zhT!a}mK45PVq|I?-YGP3473UD4rxj)7+IQ|F@nTFr+#L!J`fVk^b^geq?4;mJSA}G
zlPsZCQyOg%H;L1w5){Ewg<dTnFNCPq)H;z5j8f8YW=WZBoP4Svf^E`~$gIrM_%<1H
z26%S}xtUTSUlIHvg<(FDGzfaF5Rqb(<`P#3q9g|Hl*v(?(nQ)g#_E-X!;yexlN?wg
zG6rUV7eidaA`Qq=3L3$IXjm-qw6+qVc{*76DuV+K0$QV%zK~)C34)rC7s-M!U@sc4
zL33_+mrRMd0Ez>tS(bnd%18vp%!%d4Iv-YR3etfJXd^$i2Q6PS(iNi;i#iFQ8(pQ#
z^jAXwJn<<Yh{@uZGHRYFC5UoK8r3R69H8OBLy4*w++m6uwu0D826hlpD%KJbc*V91
z66x`Fc3UP1F<_!Wj3?Cqu8$47;ZRA4ty&;=1?QSn5eQ%hPHrn{Qpk+LN}Hpwhk&zV
zx#bmPLwz(zf!Uk`8Uh$9Z!njGuhD7CLnB~<<z7^B%!C54^T04ec)rJ=yvRtd-BO^w
z3*(fSdz^yCD8w4=M+qCyqGqj9h82PExW*C`#gUo3;g*4TND_pIaOHsvFK1g}h0)8A
zLK0107ma2^9<G2y0K(#UY{n8{QzSmOv9QzlKuF`eDQJ<<W~&o(gd#G;Z0$wkPzhv+
zUf`2g7>v|-o3~V=mI8&{I9CDQkE1C**`=P00c_2=-AuIAXZ<WRiw#wxR*}RBp8(+C
zUt};zgcMZ<Jh6-iRD}b4l;=#Kkf9u7k~axYUktkQRA)L=RfAmPNnRQ{rhK#1xG9W5
zBv|q%e~e=gBBLaWR%4XGbHJQRpfs#f3f2}1<qifK#D^qqpBN_cn%xHN6au>}6pn_|
zsFrBMTrUKl$PRgtm9zjR8i^#o;+Chm4w2UR6f*H+losXvjG@p=Am1_%r(>K|9KtKE
zgc2oZgb)s;S%=Q8j9o$DjKN*?qKzyUyJ7JYe5WYuOs{6{yoj%yyyVk+s-=fUuibPz
zR|4c<gOg7I6V@ml%5Xw313DRg2@)>N<z_+QiZlS^1NovpA!`+wg+?H#7@L?mPeX{?
zg7P2{1r_Aih>=bS$#fhR0I^tu;A>CtVh~0#yVo6+vVJngQ?TL4i5ZU&tgbL7B6CdC
zODVQ@9L_p}SkSB1nF7op$drwPhc<#rF7agaCdObv8u5d|15gTrj)U+fAyV5Qd`O6O
z{L!m6(wiQ_M+|6Zs8qz>F|>P9w>q(i)JWgorMR08Q4y6gt>l>yw$$vE!kiG5&BL)t
z0WfLP2{uKd<~)=mXBuJnkF_=P(^hQV<)CiJU5ayqF`0q=LN}lVe5j;2l~B$AHP&yO
zw2)>UQb<bS8o7zwp4$eoYP^YpZIz-@HB121l$n4mg`h*oOk~<^MIctNVq+H4gmtqd
z;xx+I=lF5bhn9Kme--KrM?K;5WYj}?sLPKpVnJlCyTBI;tL@tB35{k26dc6hnVPbo
zs;UT^-!wE?r9y#v&Fuh%#YdhXYtV5eH>Ng1An$p)<#*6nejplldSi<hh0)XGIIwAT
zKDNY~3aBN>i$*5!%@7p%(iTc%=U2>yu0h5mTS&(shh5%_63ugVh{;v5wT<Rd7Z~zv
zjE%LYUduR0PS0V7s5Tlk5F(gnDlTQ>+1wq|Av=F8S0G$YAA*Xbu{Xu_ZbQJVpXtq5
zf1_9eVh_R8-@!4C#ReUKy=#H_S=orR!pq*`f<wSTiXt8?is)bzm|j|o65i;!D`)}~
zVaGQxZfc;YZWe}ugPlxgL8J5=l}=W*un78&3@W}4nrNYipm&WxEQKnn4<MC+96&<$
zW&xF(o@Bp)<}74@q439u09>&*mA1g8C`vIKh+^PQp$sThP(-n1kb4P_E;2!Q(vnIj
z^n$ToTr%X~Q+g)M{Uy@yzoW{LIi`;QWXUtF;K)!-+dN;6AT^FwB?5v4X8`krA2+lC
z4|J8WJ6c?zLbh@=DGd)7wN^rLR<ISoc)Zic*iHgrSP$R`Y6F2XIJiMBKocAa3^ZX!
zB1m@bzhb@By~7BIQPO}~e-^FConsD751E6PY2atzjB$1W>$KsULoKMRNSqUn;TSY`
zDjHlm<>rwrK=YNifM5%sXV{=ZHb-fuKvG)^%VI$RX({sx*!**h1EQ^{8K^7V?b9?&
zei0!_a&{O6T>)^JH;i36YdBKFXM=1Y$AJVS0RgOSvzHuQE-nm=Pz6-DXoSFE2WOJl
zghq2^0XDcOjTi=~r~D<LEEV-b|FmHsjwS=A<$^wtf%R&^gZ$jmaiS|HSDLI*<hZa&
zNP|>75>eKm(0EJ5p#G55lw1k9FxH2x_^}!YLlO;}0|yL*%?Bjo0W7EhFqzN8o-buL
z0CR0Hh670WXW%NLKnA}8xcq+rd<;569|z~PW(0+Vm8>^_)UaO$!%GQzs$8;`E{M8F
zOFll*oI$3DlI&1iZnngTwBP1LSz!%=0c<Hysj$;Rsi+aW4<|a4gOj8Yfg&oRs2K-}
zEBUcQ6&qdQ@u~zFN>wY?1%qTH;h@t;`GsV{aG-K%7~feO@F!S%=-Z0S4*;dYCPM=>
zr4S8XHpXfamegUjawft^X%J`i?FSZ;5DtVRbO~gzSOkAHYObvYD;Nt#p}GJ%hT06v
zwK<IP5sE85s5)FMeK{x0F99?U^{>R=X;9f_##i`*BJd-lCDRukB<He^gT6sD3kGv;
zaX`*On-wueG16MtJxw>nk$Kybph0_8l>&GUMUn^vXc!X^VScd4q~XFK3o<&0G&Y74
z5T+eGU9%urHnb7$mdZh<2=T~4!|!}v2h}1OR*uRkzy|f6TQ-uVSVTOh!7Yusn*xde
zo`8~h4~jq=WkeOk!OgX#VvZqvPTryo295=rU03iU@G=Wz1_L()!%;3@=$4HVG9kGE
zli{z(T6uxOV#itiOh^iZP%{EO7s4s5Td_Ep-F1RiKm;9HJ_aFfNMl#LG2|L+e-tb-
zmG_ode8ty*wj%Pv6!Y?QmP1LAW_hc1Acc4(lrE;hS0O!j6R1$?_@`Jr%?V@pp;$C-
zxZ{(6kSz}{BnAhC?>1#boMR0uK-xN?;AL<OG=bLaX!ZewqJ+jM0)#cA1E4a+cce%4
zU`GZ&G)c`uvp6;%4nCMjC_;^cwS+7v;BXSOGld3Kf=9EBfG%-*9uw}Y*`yF?DS!{0
z&@^fQh6<jyt{PlWx?I(mvFEvYYj44a_l|7-2!U`bE(`9404M{WVF#fW(P^lN5+#dR
zZuXjk;X;-v@08s(8P-dbCWJ_Ckc<Mdq|(-1L^=rO#ubq^z}E<NszJln3V7HI{1DIs
zbmj?ENZUw-gr3Yx;IR|&3O37t3!L4UtgE?-5&E&U)}Fg2j`bO?^AYNRCM<v!f3lUK
zl5f_`5SL;ZoFwnGlZG5)12lmJ5o8s(0jt)K<)o0Oa#rj<oOzEzP+}Zb7Vetc5lf4-
z47$vrfC^X!+#!I)umMq|XI#z~KvRk1fuMkB8w>|?BEhPF<lw@n7M(~HIo3l-A{lN9
zKBaN_0Vo7<Yk{&{0UGJf#LNhB42n}n;Xs7|0}I@I%9|oPc_Gw|csp@ZP+>W3D-vjg
z2r?80=gO>s3!w2cpasGO_Jc-}QDNAth>Bo`vq)k2+M3bWxL!W<2S$UC77zeQsycnj
zh8g2<u+<<Qik1aHOR-_(*ANQ>Xzo-1N>Cs0W&%bji_4`hAvffNnn4QjvV;Z%97k(h
z4ELwNKpjIIwcr;km!K>{cOWMH3W2C8$3ZJkDR{sXb`WU+nhf8VgjAk&Lo!fp!ws~{
zxq?B440qy(e?-KI43fa3;O7p|Z|UiB<uObmW8+}O3uum{jb(~-KxRnVH8e@vA<c1N
zl#PKf*5TQ`I@*>WN8r#SHs1(P?6vHzcmWoK^{qMEHZxqtq!ENGU$7Q|i)Oj}>=ms{
zMZ-iH*@{F0<UO=2!;uUyq(}|v+2gg?kR6K0f|fh*DU1q*{AS=Z<mUJa{vHh~Ar%YK
znsgvc;{Y%P2Nku%l-3%-9H2CA+@oR(fV~r+d=Iybwy{JI7y?@16mF2m0um@yuBpn!
zzyWh(i_KOQ=;ho1v$OHT+VWnUslP0zW?>Y58Y_(D5YpxJkb#-Rm>Bayk)utx8y!YK
z8dk`0C_AyjP)@^|LSM+S%-#+~b@|=+4E%`H2BZw|Z3oMUq%bG4hh%{t18<#_ER$v*
zVebk23gPJQEFj(iE-VXhU`ANynv^l<wu*#fdnJ$|C=}FLlPx~HbOL^w(r6|ME{i1a
zbx$met%8~4?t&=qhWu1RWEe$bw8NPJVfI3LTtGGT#3S&Q!QhtabmOM{tY@IF(MV`o
z)daY;$`_SJUBIIsVb#P5462tW6t`!EJ^}RzLk`4h;NaXsgn<I|rbLF*K!Hf>ictP0
zt4u^Q3gIm_qNLH0kkF_r2A{K52m$ag$j4JR3!qgV%~@X`-GW%~77F=-<2az*6%YVU
z2y;;2nrDE}MJusz_|OIPhj2cijloq;5t3-+C&@NIDJtfeB={-#Ih6&dF{hf)&9hH&
zPHeEH3K!mx<2Wm&hF|eMoZX+m6$SGIzQhvj8NjzTu<WF6?b}2dLo!nxjr>Y^G3Pm5
zwI1EGbS}#OJMR@l{K4*6c5J&S?#>N_R?BE1iuEu&NgAk8dVL+A_S}JZ3=#=baso9u
z8(PJnY&3+yYC>vJatDQbR;hZ5uhm<U(4t7hqBUJ1nHeDC^`LWSIN5t+RIJw-gIcF$
zA`tWyuXZDNCtEe7f?aN=aF_q7b#Y#CSova=CZfV-b@xP6<2}?+JYw7)-ineO;$=nK
z$UBEnA(e1$c0z-&B3u3B_yl*H*zy(1Vgai8F?l|gu03aIqW#iZn!XBSm^te-IS<px
z$kD*)gLPDm`H!1O;`K0mixm%q#0ja|gvp>*dINi)6{@smU4Fa)wL4NnElw+5mi3;Y
z`AH>xat3%QtQS2)^(uCabX!_R`Bgyf6uBm~U4cg~8p$giZt>DILX-DGj=HES-EDiU
zAuP0Uox79|#l6Ot%V)O5u+SV=D9m($s7a;jo$zH-22>8gIr<p14v7S1>VuWk+x3Ad
zN$sUfWRi@Ujd(<Xu>eHv>eYvx!dhK@8s0NjSU9VGMf%+#sNk!jE!E`pRy$0J5+NN<
zdu!XOGFUV6j}e!(xUsLI(T!@N7jmoJN+kz{Ja=V-#=EP%BVO<9EeZMsx$CO}PF1e2
zQ=KRw#<)6^a0=7-(<gU1j;6Mz&@N|1@6ZsQi{Lm?s?dsBA?n@97MRfojDNLORsOsD
z5gI=kqlC2vUGp!-N7Q{PGHT&veQO&pGpTzkcu!8`^q<b}J8IGV-3$J-b#?s%%Ok_b
z)%G1WX4LB+y!1+`{`TdOx&8Xk@P3iq_0McA)xWs4);Y0HBs^~PzNX)Ous6SMGj$tx
zf(&$@c`&&rwXf;^)T(7eedHh4W#-5uxr0qdf}8!f`^<oDzL~WLr(HPeaBi!<-KW*^
z@qKC+UtLpsL(^2}HQyGs+(%;;H}x2ERg<q5mig5CzSfar^IgaEYg&=rUo-ZGkDm7)
zd-*k%_ofBEJ8k1<|FgVx!F#=)I(TsWZ*JIq&tqK<zH--jM}NKk(?1R0aNTczzGm;I
zyB@6F^U<dK7Y|*q=r^bD{_vLHZr}63|9R(kzkTiK#d`<7@YkbNcRcy!xVjH-KmCm!
zpIzSLkz*HT?|-@b4cA>zCA|wScy8gpPkedGn<sAm-OFb_^FL>vRr$@oPyS{2=+v{<
zd^`QJCj$#Q{<bss%9u|tc<t?%^S3{T{TbK4zwFuJU--xU?VVArkL^pZ-}KV(wx)lr
zV0l|U`D3j0^g9Bre_eaW{e$<O@ZYocJbK@|dw$;9x@Xmf1-~Es*!{PDRfzoK%?*3s
zoc!ec-S<AXduXpMiGk1Wj6VI>ZDVeoTle_ls=Xs;jcXs4pZvnY|L(atKl_49<MlU&
zhkbDQ`S*PjcXnSg>!p>mM?C-JB_m#$mR`KMcDp{y`{<XwI~HHvL;rj+Exhg2(t=ON
zKJ(VK$v5UtJgd)gw3Ahf2c6NeByrs$XYTraL#XO)a~IJcm-61CM0#`KH<Ol&r*8Q}
zs8Ec&R=ewsZNIs+#kv3aR;t>(W2uUU_pTncYvQJdzDP%+Z@=DgxX`oi$18e|Zt7NZ
zeq!)n_BYHr`L0D~z>aUa_1->b_}EGQohL<l9=vu=+dqD>d(3B7woaKT@7P@z+WznN
zr~h)o1(&2BzN3CxasAJxy)iDm@``_4*^QQV{d@hM@UuIvoIXCkW)8lFUB`00aSB!+
zu2|Of0eO=r(AZBJ{_|I;Ze8ku(+iFp>?n+0`r6Xl%tm_Hw|#cMwfkvs)i=47Yg@d&
zi93Egy)E1^_U*y1w`_iH)|^4r1Gc;(r*HGq@GECj4Q)Izcl~pJ&Q!knx6h}HT~Cp%
z(frWt+KlYGcINaeZpob+9x!mq^MAWY-uBkNhW@JQt1DlP&Kh&hI)CsC-M#OO8K>(1
zo{9r>mvvK_opjF~>+%PGb8v9m{+Xw(CcNLud!9!3-ZgJT?#+{no8M?R!O|vg<+|bC
zdw)9l<ZTz5%fi={mcMhLxcc1Jw~!v0ug~RUW_~2sF{kg=+%rSA<Z)8^?Nh2&-+KO#
zbGtq4KWoTHzpe{D+C16&y;~8Uc=Hv>@j-9ok9W!N#!r_gZ#`pu@`PX?|KPh;I4bn{
zV~@Q3V(qxzzh3Bzw2WL!=N|6eFSoGE{J)nf--2v8mQCJ?{cWQ@)rDcDUG1B<ZMyH8
zUXO=Wvs^Lqik9cMUD4Jnw<Ymk?;LQ)H|3So4at%98>&_}CCrRea%E=os5R}q{@uq^
zS1k`GyH4o$pg+8;A#Nt;H~spIKaY2M{5nOChpT;Z?y&Iown*uXKR+C8%&$we>Z<J@
zMfwamdS`OKx=saK7DlVz8q+`V^53FW8^MOmPqVz|Y2(xQzE6*l&9gU#-|ctzw7W;P
zrQQk{(KvJm^&VJ9lLCd%&cJH1Ah0%6H?U*)+VwjqxbtS}(xcAn7|`b3J-h3PtJ}}=
z-mYn(_^fTQy|ESHj^VeD+1z!TFLN3O6m!=)%f`0SE2n=hTAJQ&_QHQR6$7_b$1i)f
z`EX;&-4k4}aYFwq2KtlBk`Jrh>mKV-yz}snQvVeWJ+s<hvn_GziJQH6pPPRbA6U>O
zYE9|a(?su$#wtoxF`HjO9f^<Kx*3~fA~PruslwO>g9dltTe^1k6G5|HBypsFa+K4%
zXYW&m*EX<9wZ?AuRt0VjwI$KVsotb6F=ALx)2A(&m*Ei^;|$zJ&IF@U>7CJdFgUCw
zTpgUyGg~|Tgb!rHD4~W7+dQms#O7u-qSO-ZpHka;Rno|l?)CPn&4p73)f*?2QtBrk
zwAGX0<5;N3d!A<Bhp|z?nTQWcm`S>tsDxpSsWe*24H(O;q>jjBcZ%bvVl@WtUIx21
zFyI%PN!2E35a@WAZ{g!JJeCtQdWfj=qighhnD$^06CLj(vC^|ES$Hm<i$t&~+CK~<
zhGbtSCmIO2)mTsHqOq1OL>`mC#;_L=qCdWY?NVcJLz5v-C-9!9hr1v5{pUXUxjTwb
z8GdC*>Z)9IRmchS>-%tZA62^M#!%1U+2M{%I}IV3ZgG3}h)_0YVqF4m>`WXz@5-j6
z81A&4FcdG6NxvM@C+-E4ndyIAaSn#I=+CK|_dM;q6fV5C`oMv2Zh!TvalW^P9NV|>
z(2Gas9k^ooT~{2feCxDh`wnmV{OIBXf2??Q&e7(#9zC}I@TMz{&inj}@dpndUB2Vn
z_YUlN^yS3|kK9}F^qzlgUGSG9hj%~v;<$aEpAvmy_iwje@zjwcdmf!L?%?N(#ev<&
z>aY6Ci%Ztuy{O;gN5<A1*!^_<6`Q_X^2KkjJn@NRr-`>8e)`%u-@d%$lDn^*`t^JJ
z&idpp$F5%Zm#db1^!681A58a!w8rjv+R{#Re?qlo6RMyqGfuL<(=$UV6i+tD+E^_<
zJ@I6&L9GnUZ5x33ZM|%xL8~+Q7lL@45LEH5)T&xVV|oWBgw;vUsdiLm2OfUJJ*tm;
z_s^}44srad);%lgQrFlT<@O)xxcLYTQ68P9c0`l4^W$?8s3n8iNcPVU8;G^?!Go03
zFri2l{++|Rjlk}n`Q=jcth_^BEc@&gBS%;$cA}pA5IU;_k34?>y6i^tvEboq(-{oO
zQ73Jnz5KvQhH2SB?0={!#b_93a=PQ7jyp(Cn#PH8yvJlZp5tp5y9Ll{6f{T>8Nry}
zOA)6m{6&%qv}Cw|#zHYSgJHMg<+;{4j(4J>QzDt1#A_l5#>Bc33+7cC3M_-Dtixm;
ztBl@crj3b+!G(%$8u6H)+B^y(1CGT8gJn!0VfICM?&;t>a>PVEgO-i<i-}LD1WbUs
zID=(-mM?Dba9X=MjBkJN%w8KLcJMhuqE^@g?7M*Yc{h(4R%@jb5up@xDS^mh0CTWV
z1~VbiTeBfB#+g=)X$ym=5%AZ+O4*f;8o_(|LDlZf**S-xmpIx!swx<=?ldRD3^~IA
zW#UF-KFqunVwpbcDXu^nfV?$Ben(L}2?T&@)r=_c!%h=PwG)6PjpYCrCeH}hpgl<e
z+x22(vs=^|>@G3osZ4*wAU{q4Ge$`W1rngd7goLlQ&oiKvn_(M?hvo25P_98W&;5o
zCq_DnbQni*-XOgzG^o3puqvRiMv)8vlL4y^2=QFgf;&Is<1zwVs)*W9OAPA)ZiWIj
z*|AqQgQ}94n?Wrh2<WeLQ(WFE!}W0hRvZWq{-7xc%HXj2?4A^&cIZlTwqnedS8-sy
z5sxhKwl(t%oXP;7x5F8`Oap@lw@_MQQH2G@zjCmHCkH}EYU^W06%ovSgR9Fj!!M8{
zR=Kt-KPf3mb2K6mq{6r*OL!oTZbsv=I2;D_%AhGvl`h(k?hNS74;Z+5^0$2vn^15n
zfhj((JlmZ5z!Q$a0@Xshg6l3eTQM($08oLmkOr!=(ixjdB(PU_AJMMa76(z-ydyO5
zHX=7j7}N-B?W<{`WDNe?3-W}`OM_|pIw0f})g@ie%YwBt3>XQGMvWq(49jIi2JH|Z
zTX3nuHUrHC)COeEY}c@{R1>au9ax&Qr<k2nKrw_X;j*AnddhIoU}7hON>2qftlf~T
zvZ?WW65Un=i>z&IdlWpZd>_{Wd=@lqP`n1a9FPi?bj>vWhA>(xkQDMFb8XB;0lSNf
zWgU{(R~Cf@!>YeT35YzbjN&TIYSZM)f_Mg-rciersdZXc3tzN^glL}u&HJ`=GpIp*
zD0hYLl|tv`bDWTMWSoZ#dDK`fK%Z0_@UXfJ;Mc1ZJ2amE8qLT_V^b6%ImcxjTo^?o
z7Gk6&Rhf)pw}+~YaSN2lK0q}d*K2lYpHyj>Ya|rZj8uXv0fQmOz`m8+y%YwxEQR4c
zJyd8Dv`v-yd;Cxd3bg<k;GwPtS6;Ltk%vlPr)<sAK2-@`5)FeKq_B^AG%$ezz}8=g
zV(TV+90)uM9HunFcxjbJ!G|(JddA7K8G-cJiina&Ae7NqKr`K;k=hZ{nUurz__Fsv
z#gQ7R6gGY^wl?)3;4Oo*F#;Xq;6IdA3$p7q_C!jCl#y-K_-3$2bxm<v*_yUCjC4<m
z8V%0i4yk&|+pzl<sjI9N<x1+AzauKf3UJBKy6~VLj+W>Jy%<a-BrGV7MtRFN(PbI}
zQ13#qv|PECoIFzD%W$f<)LJ;O)({RxNN=150`OQX31UCXwYsqB3Ker$3eRqC!s83X
z%A1**#&RQ!0qSrS<n(?FTgC68<4h}wq*Yqtl`n;z`^Xluf)@s(gl-%CR2%ugwga}h
zJ<pkJ7EaA}G$K&0AvH>oo}78m%ipBQAePd+=ZV4vWCcUn65KEsv_*l5c5)g8-%O73
z0{)PO_$}#y#w%89r#BGuWC}W<{SeS;g1<`uI|Q)DDuuoMp_X=JLqjgouY(enNtGvX
z&Lf#D9@D=b%9j<M)>03u1~Z5n9ZIE`r@#d&iWF82mu8yGMCf(U#wX-+DWB1f>KoaG
zjZ7ejeKSHkj;#2-t9GVyEtPAs#NUc`Z9lOx+C0D^r;S>tqY@5Bo*dX)>f1^h<iZsS
z{e)?ZC$O07;L(C~m095EQ~_n>L~Gp$l~|D;_6<3npZAbV|0B}T7MWH9a2G}FCvY?z
z@IZV?XnIf|N(gyj%Yh5W19SivW6@X>sDc1=EUmbqI%~o^iw<zgDLJwXd;p%804)Q5
z0OhY0r%S-69d4TC#18CW4}=+{XBrkXh<@(^9)szsAQei%e(?%?p+v}qBq5Bi(3b#5
zIwg>GfoQTCe&kQ#YWRYLEbI?K1(=GcltqQKnsJd76cmoN<Ngrf;AaF<2Bh^fnR2Mz
zoAb?+?A82_A_1r@b|<3lQw$y$OlFK|GM(9Qb;8o5b4dpqVca;+JYMiwGHs}rAg?v9
z0FAbaTaq0L4qGN#Vyl;i3C5o?2sJ3ba%nM64y)Zr=>}tnN5V983x@-l3dl`VgIT~J
zJqf8HBD~EcG*Vh2vj&a=IT3~AzzQ2k7foVp!g@e%00O&XTt^`zs0cOyI+JiY)o5~>
zL%g#&TS$s(z+LS3c9k^O$0xcnlQtwH)hxK1WE57mLg%Pawh6eInIVPRg*@N_$dzyQ
zDiz;iV9R%xrk5RtZBK!%i3Q{xAUQo6UR<#cl|+MPmMFs!5<AU`hKE)N1sJ|CbKU8N
z)AGPQgP&66Xljv~t1_^-$Ssb6rY*~I0=#4lDmK8Do*qaB>@okS#%mOw?T(O=qRbt1
zG|UV;Kub6VdPGu(%Ncq^=dU@fRfPtQGN287M{^MGd0K=MS*d|?3TVt#Ik?C0V}V_a
zF;QxU!-^b)RMm=@29xE10IvUm$|=kOHS0gYWl})lAlUCRDDXo5HTz^kvqHsTQmo@n
z2-!OtELU4-tZfhrK`F}PE0G$k%bmV876^CRf>y%`L}{8_CA^@eu2O8703JqDT(8)}
zTQQM4a0TFKTTcdgY#)Qqfl0s?FO1ED6ctg;)EKl5$-K>jCd0K4$J?l~UJ)x|344xH
zo5dwE-I%sQYXEa_RQN+^3}YM=PhSMEAK<Ds&3B=s6{c0O5Bmskv0~%+Q;^a@5;h{C
zkWKCv*@w*z<xm4RL<Cu+${_}xAmPa(cv=h(=1yzK!%+;-pdP?f@Q+3T)pNItW{s3K
z1xCTb$C$ih3U(RYvt}=#Mni-Afky_*4P}JJ&Rajqx@I+YmNbeH5(Dhu!rnm=lPv*F
zb2xKr(_FS1KL8{ejF{eK8z42eLAKilIOxL|1;8Fw!v;%$xMFk42t?)REaI(!!@UfK
zB~t9R2--S3nQ9I3tuzugCZ&M{AJ4CdO!?Q$A$ax%UrW|jJ;Y)|pwr3(QD=?=Z)ZDh
zdyJ*SIpnbu?nsXBmO)AWGz?0otcaEzY2iPFIs-r+9jFjmcLr#i0hn?|1woC!?`<V}
zP@V|JI4=V|aIVvjoX2Pk4&T#7sE%b~U|ll^Rw+ZLzq97hv~tpND4xgSBWvGd8BU|&
z<sVle>2wkiW#XQv%6t@RQA~k|1|IAi8jx*_Irbrqj3EF33?2?CGVB9rOUStE*$zdy
z-j->A0jd@&hA*~0a9X&KHGby<E(E{>77Sd2%P!1atRqDFc%B)rEHTRuj}^pXSzLQT
zUR1$`Sw0DD-q7$W7KoFSb@}@SvchY~q`6rze=tXR$nstbM00cG@sd^uXF$A$Ik#k7
z=GLxp$(J*)fy+f{!PqN{37C$bqJWLJ0eo>K{2E!n)Tq)Z&RJG+BQDFy)mmd}ZXsbS
z1Zx=yAUU9jp9V6XhO!r+HD5bZzy*7h!EHT<boSNU6``Hlav-geaD5M;1wGq2EjG`&
zS@tv7JizMn>oAB$af0CSNLw$Td>3e0t766wm@jkx52ppl2M_)+Zom~@zO+y)T=8;<
zAj1eL&2(XU2jB)jvtczy%VotyWo#(Nm7$qZL>hk}gl!vESeP7DmK%mh8QqBrJ7f$u
zsn+9?0SgZYQ1;da!N;oNKt-x-*TC8GP9j+bvN+?h@X#3sen32a77@ESea?!Y83*GY
zK}uLtjTmJ(EXee1`#=I40=Ym5Maz3c9>1NDl;!~N#Cn&PMu5c6*z$%0p%QZnQc}1Q
zR|*JS<Z#fo&^dEqiMRrXAO>ONhlJY3!)40fY0Shp;4A?zKUYxjC~H|gY#3p-U>xl%
zZmf<N#FP69lftVuc!vrOE=-_upKn2=m*S2Pp(qYl7PDihFGQ6JK4@RJ*=W*`2a9+G
z9wK9;$YsVx*>}8jq=e-)!Y_1^<t;<LQ&|L(l0!S06RC1_fneln)IkUd;c@)GKMTS_
zSs5)6*7Nkct+RYV?KUvS0PtrW8BjC0OZ+TAL8vE&AT*;Kr{!wv$GF==Jw-IY0S?OA
z4X}<nyI(YBje)UUe?hZE(E(4fs63!SlSDkG=2iyK|9(#{+#tqlWCn{In)?!@v9u9`
zC@Y9UMJbn20C7OT{`fLX7AXanLq0}iCp@rk*1?zKZU_;;VAI!$1cj7oGq<?XcGE5f
zjcEL~ZAwmS_l_MsgPmoHQ4u4dsNKd=9>I3Z5YuoQ4G(@;gpENElZF?mw5KgLlor8S
zJL9;f2%8HRpI=O9DGH_s;VRaQK+dXw-O#v~!KNP%w=xjcP9!_^(uu$~UKk+cO7Wcs
zBvKvEVh0D+@Wtv-SqImjGRUZg&O&(fAfh&eXGVhi6nF~|B@91$4_gNCGH6Pn=oLG$
z?#H)irIs3ZMiami-w(0jRnRL-gB*(#=fRHfAfr(n8smLBgZIIet93g{<ivVBIZ(~w
z{m}f%QI(EKC-xvYv$^n1D-2gaTo#)gZKqr|VfK<y)ke#798J-Ktid>i9tae127%C*
z3R5YH8tqg{ofma|8k;F1lwO7zoVSa4H`iJD^O7>c^r^yVy+8QEHsv$Rf^tsGb7AXg
zB;mb}8j93JmZC#a)5Ybb1Tw;k+SsLza?p4>o-*0fz1ASmWi%WdFMJB>c#G?t4vSDP
zv{8&tb+B4vfhpCN@{s7v8gwTOR2R^p6!k)OG1^@kWu1GKs2NiFDuGSZ&8fLGjloxe
z+(GC==|>`&5?HKqDA%nI;-NZWS0jq7%Z&~Kw3alX+Zhk4WS$f>zBRks3vHC`2|rHO
zgbkQ6N#&{)Y+fK9s`4cE1S>o?FilOAX}hZll2p3d^?DmQI6n(2H<@6ft$L8rsGHs>
z!flXBxdN2qx~Z|&SxQbEN5404mu^n3c112oLAMJQ=G#)&;Dv!^)XiC566p#9@WOU&
zGn$+adN%20m;j6<qusbR1!b~B&d>@6a!eoOR(h>X9qD1gd@RMfrb;~eF<G=Anh`6e
z@ubKNHkGimtE$S=QO_?Xxy__ffsCrkfL?F0pDHxh2^Z&d6sSkAj{9f50ju|Zl#KM9
z$DO6Zo)zpX$8bexe_|wx7b|NignQMz=jN-A;UvfCTG!X{!tE7pV;1E@4==o-^udPZ
z9Xmf<>iy-X4avD<=9EhR=k{Io|2y8h;HN{vCyrV8>gM;m?3?uAc<=mveQ9jJe)}%|
zaQxo$cc*e^_3N4IHtw{2nGaJ<3p&yrle+iPeY*GT$bFT%`i2g7bGm!?j%&MD<o0$<
zzjo$zP0gX@6>SJ>s(ZKJthyVUw$?4LD5aNIOh5mIWVUupen)O=MJczuLe(u!vb-;E
zz@E36ulZVQ$DY<<KJ|6n_Rs#W?|$yPy>0KDyQy&C-jTZx{Bz6eFMU~j{idm#=s=fO
z(??J4IB@9ny?^`k#(lZN6JDM6<r&k@`1i^3+BXO1E`9mhYbO0`#NMV)YxXuB7_oQI
z`)6E}eQ8!*eqT*QZ~4jG{V#X9_TYPia|hlJdH1~N8#e!6XXIyId`8p!?Y;gz`qdNb
zz3)ckBHvs;ZT7(vrbQ3-{;ckp|FOw`@)zfS(&K|)>^zm_?S<u*%jbX6>+&1F?0?Bi
zpPcm3%1=&ey5pVebFuB;IXgexCDs0WoHtjWa?YD~-TP|K1E*|~9}aE*Y|G4>o_}e4
ztoDnGWAl&Bme;={OXt4VCFX9I`TFNVyE2ESw`ab%NS^nPS^DaKOk6$lrPEel^Bjfx
zyfSziJu7`5ygW;O@NTUC<V$94nl<~PSmV~AvCCc?{K|;W=B^v@MgQQWgK}DSf9Syl
ze_FQm#y`<3=N<5`8vSXQ_YR%95>@BC&wO6pC%$iG=-xNOeWH6`?LaO%u3xjFPkhU^
zP(FT5_Lgr0=X|zTx2spZ`^4Vq-N&v;_Z-)B)gMl2injka^zvhqLN9I1UUS`tr#0n2
z=oPAK?~&{MX!x4Cmj^aAY*C@imZs1z-#KUBW!uMHEw<ytoHi92Rq)mCyEWXjb5)P@
z;EGJht@v3}@L(ucf4GLK)`gnu?#b=HeCV<Rmkx*zl11O+T{g*c9(?P1qHnHcx!3N(
zm_X0?lb);Z)lD+mbdFpmy=1qTRug0SKKXdMXFPq2$>(O@npiz?L%ev-LvfkCuR%_`
zFRrfLG^N=8sVUU(^+fOL?fGQyow7Z*I~E*;tzNWNQEZDYO#CPIp86VSmM>3od*D|i
zUJ9(5)}9tvobKOlsJ(bAt**aMYIVOfiH~Sq<SWVhhHkqTZ|n6Lj`n#H?OgHH=)K#E
z;il>L!)Q{MuLj)qvuP`Tl=Z%;?peI;H)Hl?^(}hi|BR=PA8x$*(Uy;MO@E)VkN!F(
z=Kj&SM$Z}YT>g!zTdEFS>`gv8GB^E|-|S4z`ZN)n_Ce!CGcK;my)txjZE(o5s~2^9
z?$ztM<eTOmTrj$;zBF5N(an=Z|IKyLSnWb@*wuZe%V<@dy!3{C!TW!NkMuN+pYV1*
zT~XQCvsdhnjiF5w*TXo_nJl|+ch|t#D=W{>-?#F7)xI*~+w;3Y<Ny9g%H><D^+RSz
z%>8rb8vO`$Tz>HieNlc;aOP3});_yN=5E;07xHDF?LUp0)4yDwoAt)!wdvATRr=@M
zM8|?Y9jVLi%hk-e@0Pk?dR8_#vF&mZUt5WH$|mQ6!I?9I$w`$e;p>t=FEwq#gJ-9v
z4f~}pI_az+wFgz2ym)5D7NYth&Z!B6C+pX}#_7pW?3xoi-Huf?Q56f+RQ1vQW$$dP
zx|(DvQZ4JKWmC4&Nl{Ha7>`!_<|ub~gHv^Pk{W_dc=>o1t>26XEZ2Ay&4bd(4;~tx
zsQ*>O$-g#C%sBZKaq2^x>ExQIyXDRkXh7XCYM6FyP`##vXgoPQuqhfE*mRLl!z3(f
z00V<)L?rNqkOfsD-aee%EyHb3W%oSw4^?`;s^&RW-DrvmxllSDK87(XsHTj{VPH24
zXF3KHwhrYCX$;77q&6r0v?_r;LQSH2IQdl}$?F;bmDsszfHF0hdo&AaY6wq4`g_ru
z{$lRZ;Ub)Sw6fUd6Di*y5``F^9u9Md4HI5G$y3NGA4Q|C+SQJJPtdT+VHi~i8fnna
zqx)m(n)f{MaNdh6H2n}lFdkalmn69p@#ulOD?|XW$JVWmYxpz|?G1(iBphvrl;~wC
zH&U9MPh+=-mhhW2C#udPxs;nknhL|pL%AGy#3Zf5=pq)AIhxUfR!oONm5?$UpaS~R
z_desaILIIGquc2ndpm*mJpDhAag{c0jR;TJIH%4_YRoZNS|>rVa|G2~T)PFEp{r?j
zyou@~6E@y}@gNoy)U~6bjLIQ?=z!E1&(y}&VDjk+oa1ENu-g3b>iFV)pYsVIcF)u6
zSZ!Rm?}}sd-u~C^U%&iq<$?9@?_Ky`?=6{k;9tvMeetQvcQ!oz)x5ipEgAdvRTZn}
ze7o$Of4zV3+q*v>d)l)@FM538UzWWy@4fx=-o0w^L(l%J|I>>eeeuS5M-HF%?$NPd
zKl?!R(7a#$bIIZ(N0+>R#n^|=dn)?&N586HGVjI3OWytFlqY_9?Aikhe>H2-zUP<x
z<n1p`IW+Yr{SVB2qUp%KmltoCO>}7LLxXVU)ZRr0KRcSdDIoS0I740wpYwzh0s?t*
zT9tvKXcwOFuBgZv48e6Y<fTs{sdp7*$+;;+J=~C)O2f60A>CJouy!7D`%@_Qp$bjA
zHGvbK21_^YBy*0!$%T~H0Xf`N@!s_<_&`dPvOi5RulINr(PCC_kMieDqxjV#9v|hc
ziS;HCpEk`G+q4GHb1^Kg%wj?*d;@I_(~uKj<wf&ix5@EU@}(1$y(?qmF&AYtWb-(b
zm*G1@Z0k85Q@(4y*$X><0GKFhcny9^@~!-E2VRE1qF2N!n5p6$FfbLgLY3ME*}XeR
z+XgFY5S3>Hp2mc<!iIMjG^Lib9*MjnM#?po2em>tfw8+ZXiUJ5DxPl>TDM^-Fq}lb
zFw;`}N^%b6=x{z$1kjyrj+FAeG#I%2uon%Og+|M41`bdJM#dCcS;Q;_F>wS+X;9-u
z(alWbSR}w`(G$w67kIY<$CQIMQ0gHVGE;tU6%!r-);#s47$zvxltga0OoS3Mz?R=b
zcCZf$O(^Xnt+e>_NUdrV!~_~9|DcZq+=?B%vJO#rJq_>6^WL1tFJ>I(=j5pwL^;|5
zf(#s5CZQWr7|fP|WmK?>-4NSBY07tow*ozYFeGCoP#{gDH0XjiXyG}5#*~XRb5OXb
zgkykAd=3giSwNs!U~#eVstv)4L1^6Ul8mzUL?e>RhlE0u@!;2Kr0``c&t&4vA%<u?
z)a3n0Tx3j7@r95X>?e$9IPq|a{8;zaM&X@3kw-SyVz)s7QB<Y5d4WVTKi+3+%21<m
zf#F5cUytJeR1$%lAhuI<yp%4=^^q|xUr1<C1xY2dSYbtSuLN7pl$Mg`HI*?W(72v7
z0|Eb@h++-F)@syC<b$(fW4LAlk8`MOeKbTG6Iu9i`(6^DU|z&nqTr(7v4JMNQXwTe
zJWkJu1>E2;=o^{5=0M0`8WnuN!X!xJo=5G=NyJ+j(0PC?%1CJFUNfyMXek|}IG#8K
zk-~t6#Z94U!0QO5?BpJ`80ZPqB@I^Ot#x?*q?E>4yaRc!$XopEj=?x61Kd?1=1HL9
z`zw%6=<10an9_!;O}V;4vZxe#6#}59BnyCl@G-!2aE1yNiAbT+Q&K<ZR6~BGD0*0G
zc0rgGhpnW@Qkzj2SomZ!(tAQEg#y6oHBwHvfbfDm4ab{LSmHqvjj1XYLw6t<xu%&{
z#3Z&G2&R&wE#Nq)t(iQn5f9<CVU|JON&&z!hmr__5YRBMju<!#kWzc@4vUgN6z1k&
zqYRK7R2?nT=b0i-x~W1Ig>+l7CP7#y(}-tP08e1G7H!zcWD)2Ja47gRWWl~@AV7UY
zCD!qU7a|QvBS8_HZm^&xAUQbNwP1D-8Y|MVEJ35G0O5d~YY8(N01=8{aB(56UE#x>
zb)hwtxH%X@{W(A*Oe{3k_NXX45xxM#AFxXYm{{9(z`#(g(sro=SB00baD!cSG5)cQ
zgHt&W(sR=WlYax-Sps>SJ%tF3H>t6m5k*RZD32dlg9!V;NeZ+&1WjQd${Gz1%HS&H
zmOvdIWIq*+;hx}R9If#ihFqf16{j^!E0kx9kVMb&BlScLdw^Snf;Fch=+O+sJ<mD@
zz}_irEOk($oplgLgNVZJ0IZE5ful$%6iQ|dX~UM^Nh#{%4>^7Vp}@{5;RP;f3@ADE
zxUdwkrAjnOXSf%&ot@Nj9bw5x)PwHuE&c+~@<HeaySz@tOJO-K;nfIKzt<p{Y+=HY
z=@KDmN(v7jsM(u<c^6jZrOWj+idx$tvxe9l85N7lN@T7??vFy~UD3yA@-|*3Z1c|I
zt6wQlBEm2Q8{e=u$Dy7eRKmxmf>jhq3STSmsaYz1daGhcje+Mdh0J?B)LA>AY*i_P
zuA!9ncR`7Gc|v#BOx3)n>8&h6c2uO4G9jV|u^F`q&yJf7q)$bJ)26cPvFegDcox*7
zWCklJM>fhcE2*!f7}n;bfAY3`j!nE%jSQhUd7GC^lTJB=V#DYFM~eME6}`IIDA`9T
z@_RZTs*;XSO0TL`&3@kw$E{?;(v~?RMLl)I7zuM6kR(k?(X%9`huxHN^N9rLLls)i
zqLteMk*tHZ=mh=7T>(wbN4-PW>kJjflz^75EEzOpS+_$LQ4{MM9nyDVJM$#2#924h
zM#XrOgB@q2vE*Y=6jWL7(nF3&=t+1>(m#VR+~y;S6o$zrjuxzb1VU&r;YogQ&`4qT
z=7c9hbG+#lIwM#^+!YEIH4`^tFXQHLgDtTOt(q$(w1a#S@?b%`<$Dx$o&lW7X>m6J
zcwyJs2zmK(h4r8a;HW7`$HH5XOc4+B4eBQ^io#RHA+*-?(6||t4anlA2@q3?xmg32
zg&(pSmQdkO<Hv+K3_s>&a^S^ijLQ*dV(bEF%~wRj#6l>zJu<jDDyPWsCJZ!P47wOY
zWu--HS_%X^R?=`F2FrzTSm3=o6jXj2-XNKl&4|<p#|e}<+?BD6U`|jhnw%0_=|~cU
zzz*U9ke3!jNp>fh0UqM8#ek&=S<}7~?|ncRi?2DH<v@xcrfDR!gcrohIwbnJWvF3Y
z6tHp<RSwnEXmGn(fnyq>41Jk>77Q&u+{k^abc>*@+E_frYGBGPG6V5A;|`wQU@)vx
z2B{@R#fZe*OhFnSqYyEts1dxsR7pgGN)fh%nX%#GI>ven%>ybKzO)ec{m7kGF=4m}
zkd6i5mIP2}IO%erG}u##P&T5_XEl&CFyanEpbK^bf|?C%B@(fkIcIS2zS+E+h7dL&
zp*a{?#YJr^U>F0kJO=0K!$ik12rmO{6S8HZq%m;7IlMFl$v6r^8>BhewLT6ZkjB5!
zJFweW!f#0Fav0?2jA;Y{M|sq)wRI`*WvigL`2Y;^22%!sG&wNCSg40BMOqCf*5O}d
z&A?ki6uK}}9!Q7v0DN7B_vw^{0Zsh#RK$*Kj7^$Vx&><MB!tF|c*V)1ifM56%Xi4B
zAUgaK6#xdq#&R{YU@0KT;*^8nhJc;%9K_BBp16Ue!UcJTK$g6)-tR9y4z^=Luw~9t
zBcv0I)X0N0T%K07FyR=Kkb$Ao#4-XDj4&AkiBN{#dd@lsDH5v89IGW|(OCk8dY#d1
zqX3}W46>a*HYt#hMVEH}*b8r=leD=NBtTXOuHh`C%?Qx3r!mTbOt}o$|H2NX7z;)z
z8HWkAP{!d7n*pEmK_<}Ap#$db+ydW<2umXiC>tAA;^e?IR)u9EjHfBZ@rom%J`S>V
z4b6fyzvT}BG%gxZ%&06fd{T45Dvkp*b2t*?{S5^)^u1-^^oU~Sn(HL|oLwsl$EgSh
z#o$6>2p7?~;|&3L3YaPx+!;91?sqs9?@c3tCW>;X=eDw!DWc4HDt42B7xA1!*fiJ*
zRB6iq#)nZXKC@D&16C4)2*L&iNG9NN(|n~oUo2mC05sN0%AxElXy}U_ozRI1f?Ub+
zR2g97jENz$u;50y!8wqPK|w&IQE+lni)G5^P4HZZ1w?w6u~83s^2(bpkqAS4gFp;X
zdBhB`(xwn(feFPpX{)mS6`;Tv!Vr2%h6FPm3>Lp=wSFLH>@f}qE)%oCmTXx-7UpBF
z5W%vb$GZrpa(tNr^8*-rwZqpG*v2e176==&G2&7zJ~ZIAK$(mRyMyO#VA{+z7X}M%
zgBVm<5L9q57PYd53>@$(WCQ6k@F{L|77&gh#(y*obco1i2^$JY!<dOOq8P?^!-TBX
zmBNj8OJgR5M9>@uv|1;7nF-iw^gEI&*=>Uit_`50aksc=+za6D(`-qLPIZ8djb&YT
z=0$-yz@~%{0<%2!Ls;%N6dam8__cr;+Xt|;#pICY9D)>bg+N%YPHet|BsVgF<iKb-
zZb~{!oZ}tFPqM?h(o$y1Vj!7;Wh<d<wPF<XU2sA;tZaj>A%PnM7qZD%r&8#hSxg26
z(GkNJo6u=5r#J9=j@E>D{A>IvIJlugr<Pnf7dAbRnL#t2ytYUMmj&j*@^mWNp7V4I
zL{%JsqCrGCn$wm6n!+DITE8Uq43z`Oa5`(O6a_R11yM2_rjgv%Y6WVpA%Moup%^P2
zY87o@g`h+UL#P0vOj%sT+>}Is0vf3(M?t<k>J^-p3daF*EUI-8@G)rzZ3c}3k;n`W
zaU262E_Q>AD<RM_;1x{Y(vu2l1PYlIXG~{TqZODdl*4#VoB}QqXsqJGRR;KZK*S=k
zZdt3^p5wH7TN#1lQgIGvofzEF7cjcAye&nWEQv6N5JW&pCdxisSy2vTum!=VXmR-<
z9)4+82Y_Qbv6;_tJu?FQF-W8&atBY0<1JqWhiyf0C|l8jHe7Q=Cl2;EmFaN^6Tm)j
zzB1(P6-hA_ljR;1xHtI_42A&PQa}<#MzR+vg?p-;?s#{O1g6|I8-v)8#>HyWC}SHW
zrkK=%=}v@j9<UZ{(G26*BVWOr_dKCeAsD2QTa0!&S6a$R)k@<HRlGoC0c$#ZcPpWL
zEI=t6*m>c4Cb-(z0U!?#O0Y9=7so>I2p;r2#xK`h2d-wk%i5WijGzHXY?RJ&5OM~Q
z0h$ejw$2|8K3Ml4j`Bw(1LZP~?e7r7)>MHSvVznA6mQvqm#fgp+Cp?tJ<8)YQYcY<
zyat4*sv2)IdS%mSY&r~aHS7U^J4k~&vV#!~g8@V2mGNBGW8IHAlsi7<VPTEgv7eC@
ze&sFH1}?~q{*p6oJ)o)KC|QGA4w<Bc;#LWZ<Zy;HY!#tnXI=`q$RZZ2oR&6%SO#Xp
z>aeXs@%O(Vn?{$+VTp2_(t_#~#(R^5Hb{at0V#lmp%Vnc92;&;#wRGv$qK+idXOSE
z4|q<c7=vJBxS|xL-FjVS&HTCFX9P@mHK#IZ$pHq1H4y>{lZMBtMFhy9y)Xn8K>-QE
zSd&3C_F{O$h(}&PThV$nT$iv4MU#1-PL9q|T&-Le2lg2l$%!m~i&xbRb-dZhsen^~
z!s(Gnv)L3$<k1TahiJLx4(d*!<bVv<1RQ~5I9{vb3=HRlfs!EJK&8DNA&TnW5S3?N
zbH$nd9JOGY7oseb(LhdE(X1Hdw?H-&4~9gpuY||nDIU(T*c#6tYZAk9n4oj<RZl?a
z(v^l{Rj7J66?07_J)YNX3e0~NmXZe}Qz?BnE4!%c(<tl~tQ>DCpiIP|mavyY(-J$R
z$wp^{lExDWxrI`X`3eb<fi!V66`j^qt5H83(cr%7gQ+uBDvc8RZ_;3br_S0R$>Ei{
zY9~;B!3N)bgD&+~#Bb#a>}$ts6-CvGITohP6nSVPX7?4EiX;+_6U3t<=)&*x`5?tR
zK*v*CA|$(Ey{QB{+TX!uFL#pi$CNh^?`*~7)$qHtd|4dj%GElTXyKM!h`Y@=;^70R
zKPb;b2>7zT_$?||p`55m&S=7>Jna^hD=Sd@9zhLA)1)Bwt|OJAybg+`TvJ-Ju?bjp
z0t14Il`=k=j;3Hc!qFHAO+%qnlS=gnX=+Bz<hRHIsz0LLW^Ad%VeERB7gK3X-3*?L
zI|5_aObiEcU<|vPgi1GOaKfU~FEu?j4C9ILPDqK@QvAU+(v2ZPD?aqeX>onjvGt~2
zyeB7dF7~;k1TFq<YsI`jEbn#An8x`t7S+u^`r_8qxBuMS|NNsrUATD6qWLrL`5<+}
zLtDq!^&B%~;RR#jqwo3P%+VV@m=rmw-_Y#Xem}lp&(8YVuXaXjFX`89bVa}J^WWZ^
z-@k8fzV;{GPZ{2|U)AWv`_+Pr_v!`9yLVsEt9$p+b@LN9-Z(#Y>Ag2~Pu|hJ`~2|X
z#HfYy6Blh=UUA>@n<_rOeoXBNBgZse{?Dy}SzDI}I>!F}eU>+V8qp^|-|9R6*!@%I
zj{Eegc{N`wdGqOajxGLj&#6a`>{)X3t35YfaOjUqCg1+jq8mnhf``bTU3KM`pI=w|
z=od>yFWrC2==P6)JoDb8i>|ri@Golr^=0?kk3KtbG;nIq{rtkZd%u{v|GO_PxZ(GE
zE+6;QH{BO~xaZvY^@q=$|IVHZpLpYF#py5aIpy>rbH<(i*f$k7{_n@9-T3qu-RD2O
z=fua~KHB}0`eUcu_{QO(zj)-yv8TWB@z9QY-uW+<_q%V2cKqbnDNQq<zJA6-pPe%I
z(a%nK{gk&Z+;ID$3BS2>|3!D*edMyt*?&7T{ri7he9gN3=gzJ<yyP!S5BZbv15;xg
zJ{>lE;IW^k|M1eBYu0@+DS7X~US9pe?!zmNUfA@;ku#fKIeJcR`O%3@&werU^n>5@
znwCF0-iuy&MsmWD3y0l#xX*}_7oR@j`Gu#PzHi=%H~#uSY{A$)C(OU^i|)hUKHTf(
z`X!@((f`S@=QTe$bivXC(CXiA<h?^9(C>bnKX&@!E>o`BzT=XsO6?b4_~w02HvQx7
zKh<A(cl(mdt}kA{@Y*St%)If1?w5Uc%c3j4Te0XLU;iN=`R!*FgCG51(Pdk9UN>{r
zj*7^-mNOHD$9|c3XycSf?V%p?+oyEP{_d1>8y^`wapqEU-i>XaR1Eqm*7MSQEHvuW
zDOFD_xcQ{h*B|aR_{xPn22*3N(@)rN<$||zBX77mrw(1-`jfds@F9V(b`Pz;_M;&e
zofu!dN?bg((El;aiytGFd+=-RmpfCZT&1>5x#ZWyhVG}GefPy1&VC};Uh_n5^zh<E
zG4oxcq`#jiYu@S=t6A&!Ry{RC-SI_NB@Xr&zVy3%PW<%T{L-G|V>p2=x%2_2_p0H6
z)Q$`K>FD{PCOtYJi$^hv_@u(88-LQ<43~Ayxsi2)?v7P9-Zk7eY_XX1=Wm~!R5|du
zU|sy06Gr6}THfirZ)o~N%&bRz+t(fP=7W(T-~PGw_qm&^nsav!`nv7<QMGM1j%u$u
zukyn#fyQP2Ve^ZG7b4GhMd17?vTJF+tST++vtijeb-!D7ZtEkn2ARFHU_<BRXzrX`
zqSud-v1OGbLoWn=7MbF7cQ?##Y;B*tAaEPa@3uuWjd?wv9%6Q$-qJCpw(qhjS60v4
zHmQ2ww%+%@x#r{{udbQQvgrY^{F7IlRsFNpNr?wuH}0lfo409t8)ScV&;_f`uKcj_
z?BLGINOHqBrAFoCqpFUEsq@0aj;!hy8&C@0U`#l9kMWum)omP^&&P6CkXn6(R_!G{
z=<I$Cqi_Ji@GQyV)%p17ZI`IVG>L{P;l@&U!4&d6CZ?$MdWssp^Wscn&u83(z9|{k
zH|2*Ec3zf!1hy%A^Pl6bw?rGR*)|E!f(-EhybYgW+X4xVh+=G(ODJrasg!YAU6IF|
zih9rt*vV?4WV^`YEr2?TQj&6_!OjPxB8N|`HtC{h!hlT+g)!sJpj93uB|%%!Dy($n
z@J3sSa&B0T2cLXkhwxeqPA_i8S)cRqNK8}HGCbITZTGMsk#MGa^Z6X7jXwh|g*Ww$
z%wg7-#OPBYq=-Nxj9<aWiw(GnJo?Z)dJ#=RC_zG@TlIKL0m75u*+gmB>J$MS(uVK+
z<jm26UA!v=-Hy_94f4VBOAnNqAW@ly;Sc7(r{VVzC#kJ$MSd8M&>wj+`TA;{JM|7?
zVg&zE!hCEHQ)%kT{W*a&^+tj!ta8RX;K7K6F!oVA;^9XcxHDAZU4abVYEQ%k=#W2x
zvj&sMEh!90b-?MH#9%r{D05B86d6)>OytiaUbq3DSI|_WAR-t#l|5H`Dn@IvLEgM;
zig>!%ll2AMB=2du49A<gX&Q#X5&Gr-e<<A36{mmuwJx^gfvFtnP@rvMeqdfwTm&2%
zF;HVdro2IpR7R3%^--+9Xin5%jw<OvZ46Hd6aHtRuULrMFfyhpxgI^V8>*E0=t=MI
z-E-&w?|B-+=REDW65po#?$FVp?;gJW@%I;tkAL#+;W@7zSu*y}=l4E7^-$%<Cmq^<
z<*$}38T;<yipRe^c>AQM4jkU|U&qESe*5Sd?;JUJ?}bkvIeg`73&$RMdrANIuR65(
z!bjg*JoLAV`yG6FarExF$DY4%-+N0gd4JK^gU>D&Zy$UAqCH>3|HQ(nufBLRc;NH*
z>yJLPXz^d(JJS9COdacgcfhf$d5_TlW$*pNB&(`>?{!X}?m6Al45yohG!w+#Jq2ly
zXn~`Sh8uU+6xcHirohom@_Lg3$7C>=w956O;gMZM&CtUSDR9&YCXY3UI2!ZZd5Iz1
zB(Et3lC%-RNQi-G%t$cdz8CW%8so3%`}yuuH8bkXANP6QKi}1T_K&sKUTf{Of1Y#p
z*>&)3W*@xt`{R$^^MmDU-+O54JNew`#9VSV4<%T;aGcd$S;ksse1Rh~77mZkF0k!<
z_ATl3t1ez&UHHhfTe$HKS53R=1($CsmiDdB&I!{a*V5c(9lr}PHJk5RynXy_H{Fn2
zcF+2=iZy5O6Kyle!k&F2Ymd&Z*<oj_yR!I{n`_;b+nzMvrTqe7Bd>AJ&$sy5iF2}<
zwI4{XoA_W-wX5ceb<+1$+gPQ$ag0ud<W5chM*y5!w)yz4ka1JyqCbPX6hp_I)GHhv
z+TH+;1y1CzP7(qBfle}r4ZWcz>KhTXH|K2^D%gtgm|;#FN3@H^%}>>ZCmz4!!p8Tw
zVmng66yCg7Hc!`6PpUZ4PB}eG>f2Z`y^*!z0?2;GJ;50v^_GXKr}eWi#cjXQED+#^
zgL}fne3A7PFRIS0<_VmZ@LM>}Dy+<laoaswFIJMBO;Q>080{7+BU-tlbke7l7u@GG
zN4#ribBsgA2+C3sO@qOUyZpqml#p9#lyd9IXzrTi2Iuaj^YHF8_gn2QZhVdws-lsZ
zD!UunbmLx%9tE$aZ2g9Cu}#etsriuTYp<2yM#wu~oG(=lz%7k?bG~?`IBOiDPUnQh
zE&{npJ)cLR2zNV*I+AU&;5c7og0D<T2glH7?Q|tzm@-q!0^Ya*!8OWM-L;XVG*3N3
z^x{y%iRW@CESgdr@@Y`<_!Nz$O%nL7kup*#7N9G5zq?8F34;r+amQ17;2ifH2?Gzh
z_Qn#Y=XP{FGEw<(bK>K$1*+QRiM2yYI`u3THSEfJpzLjQgMON(b`^F&P~b)#QDeLq
zZzX7^$NeK!?|64ddpsaj$lhY>i}(%!o(sy2K`B_ud+VGUb=-gP;J{CKvLwx;GKeG;
znb^1_O&GdSmp7z=Y_n~f5dE+&f_cX{!h;1eJ(O#fiv=Jjp~=uPOzb2UTTR!KfX)<(
zXNO6^UX37oVuPegbC}5J?nMF<=a~_8vpzw39YqdsagGzLki*dpDn{Ub36HK1Afca(
z)*Q(iGptR!&1GoD^ezQ4U-hu2JyK^7pk?4(VbYU+#@^X#n$($#CTNR2ka})eKGg7v
zeB!Un{&iKMXi>Uu1h(+R$sOT9two!na%E1{Kjma<yqJ>Vqk$kzqL&d}QA43!FqI0Y
z7@|W=w`q9=CC@TWFRsyhyv+;Og$mW%IF+V(wQUE}6%U6zvLd9iIeAW+Rbc}}Dfo%=
z11VIRXK>+DAj>={flJ_`Iic6wM;Lo$0i;1rB3e@iBqQ39)=&!)@q8q()HAD~i=+qF
z#0J~|x5a8kcD%g;F}C%1>?&v*{n2Cm5=H`ks=iwoOYL|m#iyCogPlX0X5kWSF)+?!
z7IY~~7TBXixP;VdnH_kN$m!;Tm(~DA)vK~XhX#y~fq=eY{JNKy`AJM1t_s1jggiVf
zQ_#+@BcmM?q<G(Zj&W`=IW002^P0skN+)<U^pkd$lFmLMQeZMVH!pkXMM|kBycQDd
z2Rq9GZ<7_s0}UY#8|D?)`W8{Te8d#Q6ZT;jwwMJ(Fx1d#noxMm?BbJ(n8Ay&mz`Vp
z5wb;PSHT144zaC1X*;zU8#`=QlI*597Ci6Lm}sv{<``Iu(CSb-E>xGy!cAGWA<05@
zSti2Xi)4xg!c~}}U<%I}V%DLY`DLlPm`%^Juc*1r>=&R3MF@pY=1I5Yh|^|!T2Iy@
zDPKy`3QOr=P7QTV4YA6%i9zR16evnfIL{LfKC-*r*RAF&IuecYc(cQ>hRjA)=Hy&;
zri7xUbn80L@id+j)l*IEFB|W0Rq{2WEOtXqdJ@#HsOfVEWs5$ZqsP{TKqjAUzxTbg
zP?}tT4>tDeIVQ$&OiJ4^zlHir(OSBQ#!Ky=c1kE7(3r#?iP^D~FXjA9nCB>6ABxd+
z-rK1Qd(RK-6-sH-^q=RjH{HUW%`Ec72o_LNyfnn3{NhZ{z2vo)d-o8FYMbjabko$<
zR4~ZpS!$y^G%KzyMt|4bv@7z3KGxjq{G0PrY}K({<Ndi`$L|&TWPzSoWT8bXZs<)c
zPh~ILRCKdZr`4P1oYYmB;Qc49G+thxYpvQ{<JlJOm$>sgJ*``1!Fm%Dm9&Q~P6=T$
zjN9Y9iB6YCsN>m7=YPQ_w$Yg!^)cRrPgt64WsCeE4v(4nC~&pU2(7ANFnuk(mGi}n
zCS_Qlpwx^UL16($MrqoS(PMn*JCameB}`ci_veVRa1hXb^;1pIqjUuIYxpBK4TS3K
z6sGdxN9~T!I#B@1A|sp%U!*=Np{MG~14=%fS5EnDuy9DsH#0(@<pt)Vyqj(kqnH+d
z>r<f~47e|Y2Lt4yFsaj&rja&rIH=5}QOs7vA9_Cza*F0fILeg6kS-dtAlu!zS-}z$
z6hvt>(G3!!)NcicEZACYwoDuY3_J89w_Igi>3l%lK3IfO=@`6A3Ic5|Y-!%PboOK$
zl`cj-ij)rGEGsy+as?EYpwlZ^5R%fTe?qTZt_Er*<@dn!I`^oj&Q)CM(bJ_Iy^^Z0
ztL!M65k2alA2MoXyiLd%Bb3Y+n<KD9CZ%GkGTSHgCzEJ1<`wjy0Y>1*wWP`_M_owt
zBBrgUvfVRRp|MD`kMQUzJPz&=q3;=13Iu6GgPNe$Q7~4-tao%!4)mcFxj3xjC1%_6
zdcYsgmmHgqCH`>@E&?&>dK|LJ3pR}lj1wg4Rc+Q(C+Li(-aZODS(c5M;>>cHC{~(V
zBD@HjjApEa6;IWn?=*H86`^I4)*_IP`}rujzfdYbZF*|6Buhe|{g4?#O~~BIssU@L
z2GmRmJ4Y)0G4fnwfGTpHpMy-zzvT}hF~YE528ocG#gOKhm`1!@oXn|;CEmPm;0A@b
z22`H1I3jgnB=b0EK_`%Da~B)knDroc=ogeymQI`%Vt)=?;CBo_N5FRk#^@XRz*{)x
z=v-~51Rr}}>VHUnv^VJk>ylVD@i>kI^@}n1=*1E1wSY&};AFCkK&!Z@PcZKY{m>B_
z;ADpYKAI!O<I+l*;@a})ixna@!;)!P)@CGL80s0k%A2stb(+wZ6bqckO*Ty$R4@6e
zq}k{e;yi)jO+jpQ#Yv*&VMlyJN-mTZUF1x-JK+cA$nqAAB9QFlu(>UaS#V4nNQX##
zB^5|Y3m9k`X-2&`p=m{_$2Uj;b$-I0O?xqGB#**DMcXaPFOAJxMrVv@{rHSa43d}_
zMj7o0M#5u^iA%Oa9~f!FLCP@^zXdjMm1WDSgqk7)%J!;Eb1^P@Wnc76uihy~P~Qag
zP?9j}d5cBk4JHBI7E#O|LEt<`*wJeogaBiG%GS{_7t2)Y$UQwNx;*oO*7Aw@9z&ot
z>efQE^CZw#+@kE3b)nVypJl)3D+!Ppgb^)sYxIdmdk9yjp)<L}Ok<P)y;hiS>~e^J
zfV_ZUBdg8eQ@^O>^zY*Zo)xLae(DZ%-MYef<*k?POGAgVBt&Iw;yW~%e-q7d2*-ni
zQ1T=Gj}d_IVtXP;fdQ0Oz{So(octl*6LAX5&ZV_t;D5{ck9bBV!$j#e2us!ps{WX)
zVHPEndJRdg<XP*h>zI0okd-4eOK;#F&sExCAewAU0mmr)F(rmLccNlJ(=MEjQ60+|
zF(o=q0%Zc3PlPm-F@GZRKMbqPkrK8F|F}?PJyxzbunO}dKvvo4?>C=-cY|=S7#dSs
zjr=7iPD=xG1~dL6NKjC^k5Sw--d?#=6=#ALKm<+X5+IZjqk;}W15INwykePC7ONeX
zLFjlf8l+|7;bY~J0d{G$MaZ%_@0B^@_9S7np#zCOt9V?vxKatlqQJV)DB*RB69op%
zKpf9uNe>RuMwjt@ka3@83EJW!kD>(i7cXTQ5^;mUvFKO{*g(@bSHgG|vJ-DPBL$Yp
z;+V}N_Ao6KJ#4wrmCbTkFCs*Lj#~@H$SA;()v2%<C5!?k7A&GAFcB3{^eLfM-5!^;
z1{B=nq>4j>D}l_aDhnJ-XGIDqnrK<V+@Hc41-R^2en&(S(;Z|`T;Ni*qhsI+X;6<7
z`57S&qm26jkxDuSD5vGRkb_3zB`0laa8x2ijHv{Vz!J}#oa(@j5#qsHz>9h04<N)G
zL{Nc(9tU3rF?lQxq9lzGI7%DlVktwWn9(U2Hl?qy=VJL6!HLercJki8jT|GId3uhe
z%}7bacY|pR^=wX6Ni6N)jgnc}BMYy_8sMIxQCg(l{!d8s21~ar(51E&L<CO*Ethi6
z56lNXXTM#U&bl7ZeDCJU+A!-l)@ooEnW+)TzcD*@tmPHrMk3llrVhu(sv2v%vJ6{j
z86x!jT`qbGjlgjymcX2x$U)_%hdL;bAyhCT<#_Xz9SV^I%>Za~<*KfvidZK#qlT6R
zlf8JTsQ>^v#6Wapnh2gjp#+QzP0XDy4R9)!M3z{MYl=Dbof3X1<kUM5Bi@;{%@c|_
zQDi6&JD^pm<y0*)3Amn1J_2NiGKlTU^?+kw8b~VniLfj;odJ~k(xX@$)_`|WO$M{L
z)yYHP3v-V9j-X^5PhTY{we-mkH5YFm^sP$jHR=pFK>|0q5Tcx;XG$&QP(`9dESYOr
z5)vh3b2yMiS9yTo^kPo}Ljxz?KSX|(di*q<qD@CWH6(eBC%9?+QF<D1u6l1GT}{6%
zn{ocPl`Oz$Ocl)iGv|XyOh(Bi8$M)`Me`8H8@JfAR^re>e0X99b>IRc=qMAwA$Y0W
zewBz$l9S7oRzU-@Pbkb2q#w~*=(uJ(P<)^Y%K)&b=pada!m|X1O{)-tn7VWdu$D^#
zFF*s~5MoR81QFN96Cen|DN^wXHA+cQBl2st0S5>X<&^=(e2+~GpbNVg5Y}0%Y$tEJ
zOzHx9OrIb@{aKm$5B%qIV3dQ1AkxNHxue9^_#mV-8xpj6UPg!S7R5{oli*{zpO}|k
zdJvSbu9gV}&ZAWc`r<zBS?vuFc%2M!LGi2tugD>muSEKYkgD{>GVG-ZVYw012l@FE
zpLn7k;jxklbK9(90Zp634GP9?<?K|RdpO1C?0dgx_EvV<6i$da@ePA~DbI3=mLN@I
zVPngt@?soZ)P%-Cy9K<Q@+k-e6j|V;Tu=ybG3PKYiUE}pgUXh~-s4D6BhqCx58kW#
zAreTsXa(G)LkT!JfW*aYfe1fCP(r!Bap)LTE~(opfB#TP!PiX+kUYn?L01q=2%qj}
z%(r7U`Y5=1Y=2raI7>lL@=_7*X%U;Ch~lSv3p1X+$$eVxp|jM<1spVL!$4$7+Ya48
ztRs|H!KR&pR`;m~aVorOHb?Ix7xGnHwNHTt34oz-G*1YsqpP-fj^xNHebgPfLrxEq
z41}(u(TK@hs`7vRAz{n0RePx65qKONG@S5|H;e^%gl0P&hF_nDm=X_z;KwtLvS3Xm
zOe3|Yz;&TX*NcGmqXA-x_sZ%ID330q6(#X2ObNCO4cpiXmN*ZtLk7rYvZ&ms7b|q3
zxU`7Ed(RPgDce^)hg{_G_K{}|n3m}RI%qLFZ#_me1TKPc`o@Ut)}6V?SyHi?O+?BU
zP@N7z9=2`2)9jpw73Rs-o`rPeW%q0=dQ<!U+-?o|=e&PY_&~mXzBBze`)^K4CKldu
zUNxz2J~E%IU;9@dnHzhvzxBY;Y}ZnDzTdpJw(;)zY%kfjXZCl(#<5+eY!3J3>(_Q(
zex$gpap2GA(_JgYXyZ+n&Cjh*w@yAzaZZ}+jlJcGY_7ifw{A_&-BsLG%DpCAxa{Bo
zJ8S)w$ek@3QLl~nY-^5Cd<rU^U%!!1MOv!`l$|dPqahHl3JE+>dOR<5F&|%SML!9H
zgl6fV7rnwx!~TLWXi|Mq3x*7r%II1P3KYoYL`9oxCgz0T1!xHjwSu{7y3Gek3lq|L
zLw1i&Pn_xJQ^CgEM6*-XX%=_!Luq~2r)}R-v7+g-sdVI~$t<t&KDjrR{&rfu+)fG1
zi5vt_?Ry&T#V%!^?M3N^Y(AUK8XfYEBzw-OHTyFy8`*yg&mfv?2)a1GMXFD=rqYFU
zvS<CJDSkC%egeHNm0tJKOn3hGs8`Oh7X_^ztu=0zz4HRhp<b#cBq(@pw1S_~jy;wx
zdcs<4V|7|7cXPf(WN8<Kn?7W_v1vlPR0<D!m2A3Y0K8^utynz~CJxJp&jyI`>yG&N
zsB;!b6-KAEXJru998qC=(2mX)v29Y)HeC)(fF5>MBOv{|Gif%VLDAE{TIdcpj>2(x
z5mMf3_enkmjKREW=kY9<hRv-xmcZvvgnNUy8~C#0$7{61N6-OWX-5K`k+=Y#8nv<%
zpd70sW%F_Xy^<ko1P$+<VBQA}PbFXu4?6O7pw@=O&XN7%U;%=XVu~TeJr9T@IZfOE
zo23SmFpN@>nW>5ENfJrCLNVVF?KBV0oZcX%jFyfL3VV<O(TyT!0>6Uw0EhJ<V!U0{
z<9tX5a5rfR&I=Q$e&hs#veUs=lIWP)eA%+Vr@@)8lg?`7*c74n*VD>RUO|tmxJgm(
z%Nj51mI|)%WHl`f#u%GwanLl*{G`kS7z9Yg6hvfP3gl@MvO%Sskkp|mL}pk<g~76^
z1=3Fqk(Ki{r;OPiT!*17^E#qounPbrnY@~ykuPRJ2+^^&Qif1R@q%I6iOkz&<)n_7
z2w-izUk1C%Jb)$n1EP55%h$_<VLK^fvgrUMdI*bw&=65F8RiQkB1&Wbiv>_r;N+CF
z<&7e`3UlmUO0g2kvRW1t72|kgR7x01RZ_EL=f%8ckslRsqHRPq)T}HEb>SG!hL9Yi
zfU$D}bhLS?aY1wZAz~tlK0_bauB7sjB!6j1Ig~i`g^lNth!d9+VhEBu3?KL5J`^wr
zK&SCdFiZ(C7Rya2QA3k2het2NAQ_L<l~x7+0fZ9ou$LcvNF7Q+ELz}97|wpkKT;3u
zC<)DoFuKkO5c6XN`68mIC)z}aL0c$mPY7V)L?LCqh?fm-R%aQ2!*{f|$g=}4gg6zS
z>3f#f3K74V7lU)PIOXzeNz(%(f12fL!)cqVlJR3xOe$tz_#MMhADpv&2|srQGd<iB
zo)OM>xaB5nljl^tDq~yX>sD~u+idEWn3OtUn)aM#hf%AI&(^q6g){Qkn5Y?8uRx-E
zGn*jlGq$)P!)#$;?w^Wev6neUDCUVw@B9+)+04<*&23=(QJeOYg{zJ+V1&ZeQp!BW
z=7F>08*;`Db3U6%s;cy(EE5owFrh8f>&CXbXyas!$ugF2_Q@1&I?*coG7#b={CruN
zvT^t<h{WUk|M35<1wv%E{Vn{WcKwGr`yY-Hqt!%k1OG=nr#5*a6k)K`QhidZ$3VSz
z0Dc%4bQ&6CiHViJ_8Z5OX>(avbUaZV2@r4AyY>Sq9}+tA*0%7{?H&>fRjZ^;6U=S5
z)bT;=Vy((Y|9P>&di~Li6IZyi%f})~Vq^JOQcs&~8fd}FXW8y^ii)upsS=3KL6tG$
zszJ6wjAv~ZP9?YYC+;VqW+Tpmv||;pNRR3*CyQa;R$iLB_tQ_VWIx;Nv^hIRx3QL7
zW8AdN^W@<cpN-ZMgrx7Bhfh}Xi~<`-H8)zbEHHZ`IJ-Z2p{Fc!^sQ`6x@bx0HoCj%
zzgemW9^U&?`GLEmAzSLE#u~NCso<mbQJ%~20C(C|?Vw??J$WVga|k&v+kLicFj}Ak
zr#|0fePi?LpI9e&OHj6Id*?F`!I;BMv_x{|df2BJ{E|ulfxR=1Jo1U2Uag>hlYQ*B
zu#TcQ{?w6_l~IxfvL?Ok3P>goR{F)BU@}yd#xiYFi>!%YZkZb~zu25l7WNvuPlYS&
zH48j~`Y6j6HkW9wsfzLdV>)*2AtOl(Bw99~&hhylOOwnc9npB6O;HdXfbTwPSLilI
zFs=KR3ub(eOpG{|ro4`wa=fr;!F@KaW&JGsK3fz57;z3dQrdhb7cu4DqR)ScGLbUf
z7$8$0^3ftmiNbou$%M+tzU=i1Mp#Id7%Ak8EV92PX#LG@*HF)kMbgNlhX7(!a8VME
zAH>QU70{WU$r(I@Bf?9XAz=V(8=G)YX0}7wJQbupZRf)Pd9<Zb3amAq0Je9>Z5~Tz
zOC}ucUi?#U4JU!=;8}B(aB_ClF_)N&mENNV6@2`dHEFHnA)`YuA=u6{4kV*QYOd#y
zlI0bir#TCLQDgbp`ktcHIw|Z$EwjEuWe--0r%ipX8{ncQAPgpmZWJXc<2CfbC)MGG
zIZwl&XMqMX1|4N*_KWZ1!7O^~Dgjssne&cW6~zRe#c}X{96zSpA&@B-FomAZW0wSm
z6u?t|Nzl5xFY7S^;7Aj6k+OO!CPt1X4JxQBC&UG$`+co=hY=Lt;*pmjUb6Hkv<BL#
zaRZ(exqN{Hd0NO)yfYctz(tyj5nxO-rN$Z?0NMCgZc|8oUFv0C2`+?S<sQUHPxk>k
zA(~E*ix8AX(X4}CjiRY#>v+=WU3w_0kj{rgt$c6U(kuuYzx`2Q8aebb7j@|ggS4!b
zOex@la;g(fjXK9;)V=g<u{4JlA1bTxKnRR13Y-%&S;bKlqJAkpH&&LwCEt4EJ|`Ji
zkfS!Pb~;IQ)L~4Ok&i|(E3Rctl@$Ul#Wn5?^59}1aM%_aP`Y__Ot?!x;9B8Q*l|T0
zpYc_=D#9*T%byA^SfBBZ0y<&!c&|nTKE_j>tzzO$Vq&MuTAXp$AdM*VMvo>+JMxkc
z;S_#{LZw+yOD>p6ftkxJarj6GE9+>-bA;0X2Ur)`LMzdJG(jUs&r{Wi!a_E$e%z-@
zdC}&;4{vaGlX{kTVA_s~%_1+uJ`IfWg1*o$K2$F}p)EFvJ^^DDvrURbpP){%gf@6Y
zq>S}s&Fx&Rc|$mdJOa)!O+CI09q?(R9f!|Y&P3e%PYP*lu80F!-*zJ%EyCN|ppucB
z>?Y4CpBWwV5T|fA)3X^!vV4;*+6`Uym$n1NZ?xAIwzIp$DjPji3Cn4tXZ0o@ON6}_
z*V_T^e6d}$b|ECm!i^jcluwzzYk$`D%(9_3LFrJUUfAy7d#(M@&G|qzdf(G1u$Yf#
zEwu@o7&q4}K38Nl_Qk92L*`XBzxB_^0KAM*kUg_WzPenn`*ku&dROP?!XlwT&J?rf
zxD^|vj(j%Z`1)K~Y|8nhiQi1l?y4E@uE!?i#~8plJG3=J;)u7}-O$*?3N^!Q8h^j^
z#k`X)!eU_XM-?>&&K;IfB4h(U_}GP&Ohvh@DeICL;FNk7yG}_<c!?&GKnSF1IZmjK
zgesRpWHWC)k{$JGBVliRN8<=1Xhw;VvzIm?U0}tP5)cIabE+u8K9|5nY=Qu78%D`_
z5J4%0`3!H67he3k$iKjE2C~o+B4m<^iCt=0q@oN;R+eNj$|DqE*xh3!3l0(GTj8WH
zRDRQyW*_|?A?I-_T*2avn);3=uV}lwHPWP>r%M4$9r45gkIpoK7>-Vwj4>z1c8~34
zvQR;Ll>p0#Bm}~gHreZ4k|cpDpx=8?zJPNqhJ%73(nTS(JB!6kxxeCmGS7rwpr53E
z*2UwvG#C{$F!VVN)Qz#efIo|hsvZu7?u=f%(XTBF=oKMDFqb2e^CA=;Q3XU=`LJT6
z?<*|gY&*_u9VeCD)?XS2KB8<`Wr)W|HO+$#oG}ycphm<_8WZICmIBrW7hIZ;GgT-l
z=MdVMz;8#ogxXE0SpF>dv{v}OYl^5re#VJN7^2&e;b=ETG(<uAfTOIAx=XwExad%=
zC31X5oKaAT$2o=bl9Wwc`Dehy0bHgUmKj!JLdK6klAbVR+Fp|R)6{=#Z1va-9MJH}
zfc^~g9K9eEv+A@;Xx{VXi1nrd+FEQfdasfBV6KbCOQHds&hq<<vk0lhkzVRXP%=iw
z5VgW&>=sCfs6o0T5@#Drgik%rfGzriQ2c)h#~Tg21zvN0#f2DAyiwYwD};02(_Zq^
z2q(<jj`qbRErL9OGd~#WC@3LUA`=x78PU$vQ2<>lWd^kyOhv&&ORGI3KbXzQFIi^_
z=_ywc6q5Y-TAFN~SoFkMPW`H{l^|QbB4)Er6s?pnmJE`k7sMxkmtO)oj+BjvHcAHY
zQ~1cS1s^PN($-?{bZ($bs@%;o7t0k`_<=c98K`BwV>l`mUfjQw)grzr#Itl*wi5_e
zQgbn2zVxCCgQ*e6TLohDkrg~|O^-)zPqU+g1w~5;^qyf@{yHwQDF~$wXhvQfT(tYk
zsQ~qurtwqCOECeNig0dfcFhCCy709Yfl(L9!jR0WAO$djM6S4)OU%WQRg15YN|_GI
zWt5q=<VQq>IH=WBjrK>9K>6XMH9qt-H6eU!Wx!dHNE$*@v`A8l3fDbm|DZfJ#i)$u
z6jmoHIV>qqmNP`(D^59_mYi@CLnW~FmGRRwDggmoxFur4W<`q)Xh%{n5OC%iqI9-?
zgaqf*jy<Vj6~HH1_z<-%3Zg1F;G>JPAX~#Ok?XM<f*sNvF;&$(_dlK_zHlfO7!b*?
zC@o4ZBTvX+5bMPg*BY=!prKoKAg{}feJ={0_n1Vo6r(*v;RGYluGbJ~C?}VTNVC3Z
zRp>#tkE)U=w9_0S)6|G$0f+UhFtH?*0jh<FWx^rDeBoDP##s57ieK0Yq(`3kS&+kJ
zw7WrLV}Omxa~ot*;8e8|@-X~TeHJETB@vP>KlWDyFq<F?bjDQ184ECE+H~j;mkh+D
zox@G=2aqt{f*Z#DT)v@H!ik`*=0-Yp%VUiS2{11?UuMe5Pg20+U)1JZ3=n30Pi}pW
z0WfRG^I+7zppV5C4pkxX!Ms;Brx^(Sg9V=v2wId2qh2KhLd*P2kdXVhn1KPL@n0GH
zkU56~csWwf(^n#$EfUKT9J(YRTUPHK5(!f&%M<y<lDV=sOa6igfbx4^297c+jE&-E
z5Q%rpT#W&engJn^Yo9ufJedwk`;dTL$rDE{<!F_pJUJ%`VpygGy~<Y31M&3@BDAl=
zQ&_YjO&8?B(j~Ep{I{k05j?MG-XUFOfK_P;k-}KH^jj2xM5U+EsF5ATaUD_U<01Nc
zDJMjaoMk%!3r0HWY_!)sMO<u3aL`gwgBab}E0~yL+=OK`mUM7jUR->bCKz)NkL5~<
zRfH6o7kA|-LBxYGLI@{^xkmL6;SOWua4Un@P&1|0xm>CQRh;-@Of67QE91676Wk&R
z`h{^H=|ooY?LgyI`Ru33isRgUnSRVJo;iq500C80u5CbGcL?a22cdryLPWUe&f_A7
zM@}>rGNloV6MuK}zW;j|Wu0tIA_0B4cS>c1Aj|q_k5Xer7C|>G+Po>H99IddJeH!R
z_Hn|Bi;qf7^>S&Wkx@cSh)@Ld=@1$~D0L;~N(}16P~M8hieh2mG^Nw<WRl1-h}?(R
zZR6WsMY+mH+?fk;2p!rO4g$uW6e@jn&VTU9P<M3-v=faW<8jTni@`{NSOD8+$ctzB
zZFrS1j-KrkxNx@{OW;8g!Yg03!&8i_$9TJ_BpEdnMo`C&V{YPzQ{mE87i(L&qEnAm
zo_d)|+<`6YF9vX+2nshKS9Zx2gPmN0Q%WyH4}}CyL`b74CkqM<Mw5d3g`VO-5Hmno
z&}9${dgT?zL!;3Pi^~|m<!E;jKkDP-AcFD6XQ|8|brNj}o_wKH6i>Gq=(INW!?ikp
zZbKhz``k^I{CcIKK`_wQl7k~Y-HJ>plbr^GYEV11e}Yy|yEkS0I>v<AA?_1inetBV
zBHyZ^o15}B;v_v-cdQY{#*HT+f$_4-9vByp9nPKy!P?^Oza*+=Sm;rQ`#4^SFK;)^
zHT6mR<ihRFYq`0O_Pu6Iuc7mY`m@bE&Dg4(GMw`TIkz`qa?XXDW}M9&FyHSwefQi?
zPjfyScVUV}XvdlDooMPueEZ{R6TLVluj_5kOz>^z`9YNYAvP6-GfrQz=?X6+XIIz-
z78PdiQQyCW`wnFyn~hZXVrpu|&cY<sIajv~v*-KkY>zebvgIHDA_i7_>eWYV<RA;V
zal`&|HW5-S6D+uQ`H>x6o49<M`HUwp_JFlFRh-rodDRtR{6eZX&<s*b4~<$<Ww^_n
zW#{Z@1a+=4zKQk}KB!X1tW`zyB+X%pT3s0BEeSGcyZt#%b3X$*)<TH&%_Gwm<`cX0
z1!Zac_*-lR6~cO+-SJo3zTfT6Giy<ZZGneW`K#y%6lA7jyPK2rN&0JcmaAX5fWQvT
zsk+dg8HEM|E`;9dSh~bRU^M5E+9pmJn6CF3Rn6aBtkU(Cylw0<Zp`}0$)NEp=>I}a
z9w^QTlk4oJzFls%|0JGG6)Tx9bk^K&{EcaFdoc~xx;H#^(*5JtZ7Rm!b;gk!c8@l0
zcwn@+`MOQjk6(LXuXV$z&)x8mR%6}I&NR-wZf1Gpfs2lQymyn`e8!o6V$&JhZ|-%M
z`>R>w)}K7XZaeeB#-63#b5A!$yN{gwLVIN08LO+^?7D5s8;{=lf^|nnC(pQM^@+?~
zdhJGk<BjY3oi&r!Jp5d-aLcu?3gKg8&09Y(wy^Em_1E5V;m;mj?T^`Cv`=%lT)Rp7
zesC|}=zjL8b*t+xT)%1Ud;jkKwY?V{{_GdqM=tq%yD@(2*Bj#>etq|xKmLdAIp6uv
zH*S0O)aP#d<f+SR_x*MCMf)x|`iWh?bM&tE{>BY|_u1^`zx$unOV4@t@}>Rr8fU)r
zbB!0i^6#(ty?39n{MBFBw0i5NpYPxL-nV`0*2`Y;t?|apbC*8jpT1~yd-JycalO0w
z%|G+pE!V&P&@I=$@e|u#clsx`eg4(E_CE7-yY^nY{fYYOOZIR3y_dM3`_k3+n(JRH
zefPH5dv)s*?|NqU&%NQlkA%@p=}m_lH{Vb{vi37|KmNg@G4atm4jsJf1-*}d<n>SA
z`UlS+y6r2^FQ0qo#^%Jmt)rj#$hVHZXv??#&HH=xy$4sCw?1=H^O5|Q8@Dy?Y`pjK
zJHGLi-+a%}k8k~@{z)I*xUzfdwC`QIy!~63{+C}3qdU*~#zi~+lY8yE7Tlvdu0Hhe
zmnXlm`n9Qp4?q5fgSTwHc<D3OjqQ5mTWj_|{L|0e|8Ty`9=&SReRe6)nRu^%#H{(~
zrRx_SUHzGrFuiHDRb1P+{oPy4-uQP%ZeDkKcVu$6oA~Qj_SS#y>y`Wk2bRaPUXk4U
zHlN@B^UD*r9crHZzE9f8@B7E?Yd`m3^WfNp%e`!(F>-LCF|m5dHCt@c@_6sU#`xd9
z&2IVH&lkHV#)?~hcl5dJ1#kPtmY2PLY5Z&JmbN{&-f{d&b@$SL>1DMud!v6p>uz4!
z*1T=oFF&*OyJP#;y#1a{x30c5zh%c;kA%za(6@`y`;$M#C^^x3zPk29)!Ex;pW4wq
z<vw<E?eYAwXn(Ce7;YZ<Km18ghWf<&dK+)f4p(n}!GnHc>s5{PT(>;&z=O?`KJ%dM
zU7Gg!JFCrmnwK;`@+(($R|<Q2(Yc*l*1oQ~ckYtr<jyxQU)prbqvKnu`5$ey+pa#f
z`QFuRX-jiUKKbTLXZOBwVd3G`h2G@5F6)iI`!b!E_s&)N;MV%D-G9SpE(yu5gBF&z
z7WVG*=x)8)n_u%MKFQYm<h3V-<k~-RozLzK{3uMwww%ACb<%mygzDpA_p`s=-~G^b
z-+5r4ZA(}A@f^;2Xut89TXw#Gp}*;N*Xh5()x)UKnpVTt9$CuYaFMskxutCC{O;uM
zesT5I;t9Wd%k6pR(%`b|UmkM*mpsQ_De4oQ4}Z+;X#LJN9!-9Wmx1q?F4E<>qJ2RP
z-L8@DMXP=Wdn(t58|FAF_x!~k+wXdotlQD@2WR(=y)x{+aeLVP*;iTTFUNf+WUl{U
z?!sqIerEF8`a#=OU+}l{GeDo2wg+mrSj)5cd)3+AzgsUNgL&TX?|$>0OSewmw36+9
zS>H~r*y=ZadnGL0wm-Y=<Fk{Khx%c3w%-{$y%%2d(;;kL;(ia^#{P2qVYC1Fa<sH7
z8E=>N6cg+B*h-Cw?H5Lv+kY3Dd$`y=u=#QxZ-2lhcI@%V(#3pN41M|~AGZG$L*6AE
zl5vA&n|YhQd9$~*ud$V{F<C9no4;l=kH{YN_Q`+Dvvc3%>{kz1cFjk;%|DvwbN|@4
zD!Wqc29`TlSbo<(n?LybA^VAYY8Qdc!)utG&L_l4U)m64eIG73@;I9F@Rjx&I^1t`
zNIRU_#2&B;_n4=i;{N^Sev$nN)6V<3Gb8WV=Se%lY6P16aAK!F20eDD1<Hwz*0O&4
z%e>uw!0f8OAnhGAD|~l>*}_p)G;c5bSy%FS;aP59t|ZSDWW1EI{xj6>S6{G^9B%4=
zfL|m)dX;3YDqKfr{V}8Fc2lzlf(2Vci#4amF2DoKpM5CMYs%$`dkDX;+Z3Km1m<6F
z>G^fd=J3QR9?zI%YA9?ADb6G_7`q6)Wa%Cc{+8CMn|x01BI_)(`z#Vu^PY(rnucR3
z^Ttm>N#V`^3@?CPj0_!}_4lLDowc3b_MJ|C3F0@?ciN!`&SQ&}Kk1HBna|VwjE2ik
zYlL$%js)9Cze#qyzqi8dTG-lq3ja`=?_9~O`OxjwU7F0@()3u`nVfJJ<vaYt-O1~|
z{#~8r7k|IB{x*KU^p8IK{da!hUrzq(NB?x>$+JH6Z`Xb32k&|3cb~rTu}AMcdG){j
z!@uqP@GoEgo-h3Rn#ca-`5T^i$v=Gm=@0$JtKa#^zr5y;{{8tIpLod^esIm-Uia$f
zANjAR{NSsPJ@~Fa{q7HTe)zf<KL5zeH+=Wm?>>0x_rLvv7k~Kb7vB5Gr`LS@tAF^b
zzwzpSzy3Eqyz}J0d*szq-+t@YfA!Mu|NHg-^yI(3<U^0%mwfy8{^1?Ze)Fr>U;A}_
zzx0vc|H;pM><3@}-lre=L6K}2@d@YY(2*X0iiVlqFhWJG^U3tsvVP@uO^>a$?bN3e
zsb4!W?<Z1@3O{YS%3*KDQC==<&If)qr+U`x1vX~WzT@ZIt^TFGWb1}zs9oSPx54VW
zMqFr|;<L-=EW2>tMtd9FsBLh!&Tilx*ZF>TbB<fzvsg3DciEEN8}-S<S(2<|$yq0B
z$ufFbvbqvZ4J$0>88Of`g7j5G`4MnG98Z5Z8r!m`IaBvsKL)g{6CgPu9E1Lc5GN21
z655og1R>BasXEV13)>myb+(#~)ZT=B`6)ZKZ+^2aG3PSv8crAi=U6kc7Uhe6(tI8+
zqZ@lG!ooPVg@j`=!y>w?)P4v3nl`+?F_XlHU7iF!<Vr`2HpyDSB`{a0EHku4*Yayw
zLl?fZN_7u?ksiKiY+K|OWbj#5c858iFR*=MpEzZ;$;HBw)aUtoQG!x++3qj`FMerx
zN$<8swasD4!Xc<%wdj<`GRjwoa?x6DIrC@?Rya%crOp-|kJ6@X#cIvKT9yIAF&NUv
z8QSo7hcx3C@0#S0-5z0o4&`gQ=+SxgnwmCSRJbPzvd3jtnxz{HxCr<T!8w=EcobRI
zquqG~J7OsEbZL^YIkZvJhb}=S9r>?xscNavv3WI;a;#tsCduW_5JDx2EUilhm+pTk
zp36oYZV|wEPLe5V1R}G+BP3-r=pDCGI>*Tp4<Z(y1N;LIauzk3qf4S&LTkZ3R=#8x
zy0zw>w8(-Y=^QwvJ9!ZNjfheionMRP85?KLRlwkzVZ_lMl3lQT1>z)&?J;ra38Z*g
zHa{3cQP46=Q<PIsp!b2>@sq$I>6vN&g}y}ZcqLLEOqZk(v-OFrO$&aB_DCB-<4D0b
zMY<<bWoZwS^d&c+ZwJn)D@mpvDwqk2;OUyQn4}7cQXus!xgVeI<VZ%PD^M@>aSoiq
zdR=fCn|rwFvcy?0n+>ANS8<%LN};9W1IL1oTh+YBnhpxU_2lN0n~_yh(WwxG!_L{2
zC>;1B;zbqriv04633#U{+D)WWNod80UfS!?lpABV<jyVjQE^1in7=>6M<ya2L5Rms
z;Xnb5cCWZlF#$Zb3roaB12|L)ELTvf+D%f4XWfvpzMxtMG*Z=DAgNG&d9!}7BWmv<
zz-Pq(0zKN7ClhZnyz!|G+9WPy!D5R;llYZKI+ADVxsmszY>s}!Gf=b^q%(+Ovj`|B
z8|Uz|q(nu!6xn5*#+}n3Jc+4I%R7fYg)zEh3-G3Ek)lg`p8gY~jj<q*Hc@Hk@QabI
zFZp_rs$GYeNu?nx#V(;p=Y62Rpc4|xVr29nr3%|}3dO28zS(I>I9sYMM1ceo^Fb&I
zA*si>>$fT3f+2-vtcrZSVkMPR<>;6O7lZ<8YA}&OH)<Z$5L0s$fc|7E$O<t$xfbBi
z#`j$0^gimK$cmgmit?XQhH(cFlv|t0?1kUKfyRp^=0_b30fC5<jeW|mA3BW~p5%$t
zMcF(P@!MU{DMWm*&(}4iLlAD~*@(E|T4>;@QL7ju9xvBvoY4-=geWl4s=6fgJV&%p
zF1YC3X`epnj0ZL<98XRx*-o~$a*hPb8BIiURhWV%J?Cmz()x@W*a_Zxe2qEG!D3py
zXT(G^f>p9WJ4NSWh3sN3=y=nBTfTU7JZM3_z>zL=N0MmAUP$f19K5RHXFo0FQI##&
zZV?8?GwzKoh|HQcJElENFX9{xPdQ`PasAQ+?)FIISSPJy877x)C|?^>hD91f(Ohzv
zJMl<u^^4@(w>a85tt=^OiAF5G3hs^Q_i1giI%n+;_Q{Kt!X+@uwBIBn5Ik1dZNSmK
z3s~;7<-in0(Hq{zX0oDJsq>9%V(m0bTPw^_6V+g8-9yPkCtoGtGtOd|;9N*cf>X1p
z#s_tb+fzOLF0y6&Ynd8fV9;T|B}bMg%}z@e;TL8`5`=qO;a6PSgjQ%4jVd+UI%__-
zqts7Qbrx11jEj%?fK1ODD{cF8WzTlnWAZPL@dGC}%usi#nt+jFD8&<hc6~9eP)X$#
zQ9^^0d#uxAEC+%G5vB5kw5(DtxGc&8JQd`F^<#CF^bU~{1wdXh)wqPTvNh_MVG9v4
zKAg`ma@Ge0TH|#=T`{<+LRo!a1fm3y?5(k+z;W>8h~P^3gi{14k_Y{J_$5M=LOp?8
z=aC8WVk@poeZc#FUIz*FQ1WTSJgv4$?BnlnhS5;6a4ncy<S-Lj5R?Lgm>h$~zzis$
zxyQur5UdJUk_<d+5uJ;u!a_X;!p?R0G#5CAcyu3&Nsn^;mG6}!8Jae%QU)P+3NgsA
z)*uiNn8jIlP*ka5ce^;|^p%u4ZWcwzzh^L4eMKn8bs+>ky6{h}?1z|JX(PA`1d!;7
zu5bk|YFy%D7*Fl7{zQqWGa1lKy<#rfBhCZx6^d@yae=Xiu#HNtOGO9xvWA^jY)Swk
zX5KncXNClCS&)qj?heWU9im7&C`aT)e!tKhu!w_5%wM4pi5pf!*;)b_;HRohDGaGa
ztjAIiX@SdIaA@KQvO2LKoMnNGaZyab!W4PuRFH0yXaq?4FW1dOOn?+gF2+4>W`Fc+
ziX<-T!Hf{B1o_&h10-BhR1lRM24l*xB(SkHI3;V$^H>m1uz>ZXjz;dHZsx+kx^V7l
z>~ti>bb5=<I(8Ofe*&*Z|DI&=oX1l)kM<502m(P)mh}cK#>5?(J`SUU!m$PWVKHc)
zNyMfl;}}M%_#a%EHefqQ!y~yAFsN)r2i%8!Kce7CP4m8ENEd{bEpJ#K35dtlrB6zp
z#3O?gJ1L2H+8D?~iy~;YFXI88{6hf^0gd3^<C80u4`nPjK_Iy3VPHQjdqfNjO1Ku|
zgAzj&h-VQOoHsQ}OT7(&sv+o)>E>c<Y=CPi0catA7rt~81TN22LXf_xCxUV04bz>%
zC%`}<Hade0=+Pe}#suwmIFp$Jd<oH~>j>OD88R@#xQl4)So*TD4RG{upD3)WRHh6!
zV>~*UTu0_X{-oxG0T_h@KDszVr4@H+81PG2??y%4z{iVq><IwD<G5oQ71nlq_QBYs
za_7ogiU}YXCcrqQc}W9TrmIXRK<+$vM^{2i${6tB67$&7fDlfV#L1RlI66?t5*G%k
z1FwM(ivKtoR+|J$h~_wPL>G~VJ_`hX1d1-jXoEyr2`W|?MhN)QzClyV{{q14rtw&I
zUk=WZ(nUA7sWM;8KTnu<!q5j{z4LLrCn&p>HY5!j1Y&8N90@rhKw$p#@*{OuZ6_QX
z7gCJ9KjzCWh(>Tw4xq>``3a;A+6rf#K)@6j$ruBq&TwibhtRIf*@}`B9v}#nn#RR$
z*%6gYdWilB1|Z&&)Z^e-%2T#^Vbl`60)ve3%6vxD3ukF`kD4_V7|K)_@PlExBoc91
z6!2vT`f2eRf|8RVHTUF$+qW`#xJVch4|p6H#KVB96;jytN>jKJX(tL1O18Z26J=sJ
zLF)i2cigqaBuy<PV2vS=6b9j8>M%*Z=Yl#iP<RO5+9i3L{Pa%;rB@;=))IUwKRWnc
zgH~@44+D`dkTM7dudogK(6Ro&EodXA3>-8W3^igJAu1O`XzG+6%O^!jTY!tuANbMp
zrn}yRrB2L0P}IdePoI1TYbYt}1}yL~BfI8@9KtYw{;9ARbJYe+ET%dzn%`Yqgi8}Y
zFr*SnPNAr>{!*B0SSxYO1<H9j$8D(m0@|#+Ks;A^FPl-cT<a?(<?^HlMM_bw9s{yo
z#0{MS22K&B3$nrG@lT{C?vvxWD~m`W9=IZCEEa2rR2Hbhh3WrXo)@OrBFQZ!4<Y`3
zX^ePWvQEbQBSad+gQjnsgg9O~GnlmpW*XXx6oHGb9MJ<Yy%l{&G>IC87$2AqY`GG$
zER?yhyGns9+}IG22E@X+lIH^PEU+>kENF6q-h*^n<p9h|(j5iFMR_5>p_Mt}nb!~)
zfh0nV%ZkUmYL0*gMLlojKa_<hzc+z2B_H6Uiz7SU@|B2)t-+_XQ`H0zqASOH9CFG#
z5g(&+JlAwUxHQ2Rh>I_IMTTfsp7frv4h?z`Sl$DRwkfBCn8g!TX@)bll49u?^SvTK
zjN^MnA`~GTs8GiF!q}YBJLN)mCREUexcPtsI4&QX3;|2!I4?IAB5?|NIkcx{^ajQz
zEcp~yWm6^8?8Pq`U?V4z7OD)Inll(<FA&Qnp=^&;s)1bUas6Nir!oBDK-~tnpr?hw
zwVlM@7%F3URr1``4-TD!yMkPObPRzE_+1jOV2@2kNh;Q=La#FAJ9)3(XA9LK;wn|(
zb&Kz`r|%-nYgBlIdO|Dgkw9XtM@dGrk!lZe=A453>7RuxdrHkIq<fl>)h%(SBl;-e
zySae*9>wR`9Y0bP(mKm67xeroE=c&sD|K@aH4so??-u!48^r7wB5*GfC$T09OmM;q
zxVBo4eC>6`?vss0%)Gdg#(U*OcDA;`7qaC~Y$2r6b1)*HV-iQ@6R+{kpznG98}x9z
z9PamE7SCAPO=JDn77J@m^RCI0C*vP3%{ss7bEV^inB4B}5#JmrU@&(8k#%b=YxU5=
zwx06!r6#gkd~(nTuKDFb|25k946k*11Wxrh!P?8vF9vCrsBh=>VCg^coS)QdJrA&}
zykng7;c8DaY6tcAEInH6vl+hogT{7%qdu?@On{3lr5&V%(uGr;jxzK`)5cuc%v0>0
zur;j(A6uM*isLwN?Vtz2o1Vl;ah@sp{zzw!_T;?ec`(^{diUP`jlR<UpjGP2cC}yb
zxrZLK8)^?0V;45udDZ2|ZRx?IbF~M%)uoxDa$)gYvHIoyTzDY7Y;0_HV%Mp6x~0W#
zwZA14m#<q%CeEDAm#;W9GwZ|2XZ}Q<oOx#Ps^#T}ZMhNBbZzJ4bnTsIG?uo{Uc1;|
zv#>U-$=7l++pg2H##I+@PDlD{ijm?~`L0imE$n)#y|^~CE$LtX^naDU51v8M(`3B!
ze}%{DmA`tOuRb+>_|*?Te`w~3cCowo!(#W=kA**Y<^vB;G~aj4T=9zM4%A3n{l{-5
zPkp#wx#OSvcOUxl>cs5xcg%frec?u4-0gj2>$j$k{Nw&L-}ueyZS7Z7Z$7tn$K2|B
z_Wif-U9#GKs<y3taqYL)JpPMcT3cV-ciS_UbWc9IwR_uhm)w%hT($i#4liwA^Tl1i
zbaQ>nX`80r`uVYEU-a0XnK!Mp_ci-3dFTz&*I&+K>P;(ez5DlichrkdoPv!{>%aBc
zw;!tXe!uwOuiQ|4@Vrxczqc~|#+!<Jzj44mu$&a99LmBe-)h}|Lw|Ss0Y7@z1FJXr
z58ip;>7VWPx)WV@!HchLwNKuE>&~s!lc&cHoqX2?cO3ZhpDa#pUh;7I&dm>}&!@kA
z+xFl5(#flv_uaO0>yeY|Tf0BKbL}m*f7css+_v<F*VM+pbn_FJoc5~8tG?MO7N74N
zOjg3|ImUho?H$_x1_tv@@4w2Q`Im?N%q#!KvY!lY^8B|~U%B;7Me_7v%N{;#6Gv~@
zHna7)r}s6E9O~@gr^>Dz@p<>!zH^8BbJZJ{68qd8cE`Jm-mhG8<bdCBWbZ+no!_(d
z{@#`T{sXn0(=B&qF?RHl?k$&Z&2D}7*2#~YxApN#@2W5EdHL4;?evmv+PtK_CoJac
zw(Z(+^R|UX@+VvVpiMg+Ti4v)-oNYfY)en<{3(9866<b?dRy`Ayv-h7<Ii{|U7VR3
zJ=EQ?u{v9OX?6T9rxa8Dc|X-WdueL&YumEyZ=UWns*U6gYa8Q-7W_)EzFYpO`{x?<
zJCZ{`Gad3X3tQgMS^Lz)<WJo<F?&}walc!>Vt@L9twsB(OS*fO*B0v@Tf5`t{;nej
z+{pIMO!~#_uC0%U(~f>V?L5%lGwJhnN6y8b=WE~4r}=)pn{{_Fnw%fz+r3_OHMrvN
zbJqFo+e7E>eWA!d!0q|#I!V5{b07`myMxK2+Zpq(>!iCLJ8Y}nntkg?%1?2&M=m~M
zQ?;+~eav&|N%`67Nws@z;;~>8ee<?sw@(}Ude!Q^EDKX_Gr_lten@*y1-oe^tUqsU
zxbyCH%r~FZNGsj$q^`Gp>H;_UsVbvg*PI>g_1wzmNG`&s_I&{Fw17Tg{@!k9E}I6=
z<)-XYy>4dB^l)Ib3x|B?z}Vq-vcp^J?aOw1?QNa0rN2&3THwd%`i0%}SV%`M4nE!0
zay^@Ohl)Mu-S){wAKG_b8PYq}_|)$X(+el_5VgWMu;LN)i+oQ#dGEp@uF){vTgMue
z@pt4XXH_QK4?|$*alC4t*~aSG=()jc>48uzaJ=KfDQq`NtgCtCT3yiYg0^v#l^|oO
z_jX9%m{prRuWefAotoa6r<ONbs8%do-~)FKp;vKMeS3v8=o+j`d*@kqU*Ec)dd}|X
zc(dRvd}`Ffg>SZ2WvBKu{mri<iVwS4zcsD6a1Cpm4OXmwAkOyed<au+DijA3>YKFX
zB<n7t-vW7P&RtmYW7Fs~Zs82#Ga#-(k+<_`Z>f*IF0p0i(B>Q)e(!eGot`4hlMg-S
z(fd=F;Zt)A=Fq$o+$Ss6zk4SP7I;`oo(|JR2O0R`Zuj^doTq;^(N|6qw`$_8)FlH~
z-sAhg#%0#lsm=3)*K<O%G-V#a$8*Fj<K~9ArpMAR@ywGk!<do;;yRitw;;Z+=DoG+
zlyQF5g#gF=X`;&tmr>gzS<7^f;PsF=nD#Wi^@Aesq|5+uv7p$01ZhTLM_t`hk?6z$
zb=g_irtcclQ|xieLNf2MsTI}fxQ+<%8N=D*D^=?REZI-*O)$$sHZhM%7uYMVGNAa|
zc6LV7?1F_S&imu%um0wf-v=4@JguJnr_X)wzF+(PJx@M;@*ThN&XLuh`qS?`d+)!$
z=jGpi`o=phy?5;s_dWUTr+@$F-t*}vD{CHm_M10sx$oQG`^NA8=b!!blkeGl=lAa2
zed(v4{K3;7{NAhY{rgv+^5JJ6d+^cwo_x>F55MPy-}&tK=RWlG`yPDcz9+9gn>|l|
z^o5rvPk!?Y@3{K;&s_hp4_$ro9gn`}ly86YeOFv}-<Ipo{=)Z8e&3_-8F})aKaRg&
z`m!TDllr;ujDP0kAASdBP3<CDLq+d*IEG==VO3}Sg=LnW%OO~kwVtCm^M&W?2F8F;
ze`(wGruz$yj13SCw{oCAZ#}xqEucExIqNj$tXC9`J=~ABi(;aM&`?ZJN%LBJtlV77
zLo0m|b9l<dL6AO281KJriwm5^(Dpey19R<Z`tk}*<CZ03El3|>?&R;sL60&4?w(>(
zR5-|iIQ&qvU=4-55(ei^5P|Q&DN~d$%ZA~B?|vj6)Mh0R;t09+klg!IWh7$HQkb1A
zkX3Y)Qf490Py=zV6n$8#cQ~UNI?Z=L%lwzmb7&J|7iIQAszF2&i<}6dOA)A#2nC-)
z2BTF%VAf+y;tK<%R1!PTkce1X>Lsuag!_Uy>X4dGLU$>kM*M-YC9-#@Z8|8UO_61}
zOJGBN^L0Ah4t8h=^w^O25eGVRaBlEQgM7Alcp-z95I=VZF)&BG?b)91u|Ew(WRwi>
zX`ZYwwAcy@_S9U~vW($K=?i31eqU1`&x$gGjij>cD?X{*$PvUcX^T;faMCG}Vpk_m
zf@(I3F)Y|g!z52a2&8yrMp|6<TbkL1mfkmcjmH&(%IMoh)|T#@!3VmAAYgJt2FQKO
zw!~D>HKnm*WFeSyHV}<$&u6}53SvQE0Ah`3>y&;^hXZ8hD1}#2;PUfmfnBBQ2@qmb
zRBYF5%cfI{WwP3LmN@vRR#UXea0Ig3@BV8U4$=)0g!zmnL)?do?NMq!9v75)^0#9V
z(8sb0P06cl)AXw(Q_+lULChPhw*w^!u(K`*fqv9S^(XKuW-;$^$U~bFGQyx-Afbh)
zb6DPj%e&nDPczRENhIqbb1lS&aKI=~L3_;a0!_QHl}+TM?t<epFjTVaic-B;E4=WQ
zjtH2CSffV9ah*|xp70<fIhmL1A>B_qv=x^c@_<S(CymeL35H0$rxE8pLM4;9ALr2D
z6MM+AUSggQ90F}F35o!LYeWGxW#q(4;`A1(+Z*hWYMq+HJuT8|zn1<BM{^6(uwFK;
zj4;)xg01n8OZ!Uh*bRuxOz{Ne*@U20p?JC!(Rwp`cqSyN&sY+H$I8ORdQ{zEeh)RJ
zPWd=IpM(UMj#7{P03R7?idAwtnt#=@i9&gS8vMM<%{6IZTsRqPM&*t)4WWR^8je&$
z5;Y~13!+G;ze3n^F~@tS>4EVk5k(Sh9JxmVP!^~K`B@qp3^uSznO#_K)~B9>FK$<K
z1(Dt%Eq-ntR2Lo+zof(;huoHVnqG+|a534V)skB@S{{<49WXHpN=v}WS%?k3t)Mz=
z4L5G*X4wMpy2(7g3(kT9CAeWg{-6#!3S+QL7!?bd5j<s<SxZ2TAR7L0IFO=(&n}b!
zmyF%3Abjp|@wKPv&sfUxRz;Y=1$R3&SH}u5uBk~wKTXn;WSu}eVohX6$`ZDPBauxa
z+O38zV}8+3LRFk@p_UP#Exe2rDvcwl&dANH-P3|n^8`?yw82<TV|FCeh0R^+NEgle
zOry0Z8Bp*LA5&_QXCZWLa-@Lsl@q*qacX0X>!iTB!RVtBSm0kR($N6%=tYn~Q^R)}
zK=?v~cDmLfnSm+|X$KY()JT2F4W+e+#lq_}G1y4v3@XvgkCDWhmv%}k%xaDn5x|>i
z&(p-86QFL4<Kew^E5_+hvm9oVBRRPJ(?!;;xO53AuHK1+HhJF5=rYM(lxvXDWe=%5
zbWz#4B%xS{&N!eZuxF%3dXW{Z*(>M*$ze;Ia|BdXL8J1BrVYmBqUQr%a*!dCeh^>t
z7Or_~$|;d_W?N;VeJssZFw>%M!HMVn7jS!l^!y~)^<dg$2O_3`F^|#Gtd(I>s+Cj0
zQ)JQGvj*z1-3hr%EUWL=I4dRi4DSji;8TlU+xC&26*N}HYD+W+erh)49U02DHZi}a
zyQ4+iWAYjY)~OCHW2Eu13rhij%2PQrpORmKfH*hdBT__}a6lIx5du#&6>xGWHayU)
z%qx_lKy0`%7-W9^p9s^Ps6kPZks^Jut}%eC9I-48oO0^rWnDq)Uyfx?=~<u{8br{M
z{{i%w63Un#VoTX8vh@{E5rrXoqbj;iaj6_}F!ymr(cYXFjSd(NG?&D#Y9c}ouLRM6
zW)R2ap`e=)VW4T?)3}Q9sscu7v9I%p5<8CCrH+Iyd_9&mj(&rmnJC#xr&w#0FoPz|
z$SLtmS{jn0FeghzS;Xo2a?#93pAH*bREwyyEa0)xQfiWtWwC%TL@6c3=M5v=6}RGG
z9^cNz<!~}Cu>b=VSpy+m0DN2wFfL{46|vn36ZrSU{eU3x!pg3l%Llck_j%)xEK;4(
zDzY#*qXXc2#WEb!E3JhvB@6JOhD-~L!LVj?F-bF2S@Xg9<NA@N`hwcy1ftfGBS?LM
z8`nnov~HFWY?9Z#4++@a@mE5^?_P#7$PWXc1d)6?mWVNRkW!{wbKqNcjCU;G06i`J
zV>#jwFeDZ#w6lO8Z@vOl+K2PTbHNBj9J5puE7{Qir9T!Y9%4w&NwI*=>!>()VnQqo
zEbt?mat!TC7A2^?m05U7WF8D~j7A!0?;%3fXXHt2Og~1{VVnu`ib7HeiP(BF#wr8d
zt{gL0SxmNqYb+6ODG-7*$p~9eE^}NvN}ZjkfFQ!6Qf3f2=d~VFKm^hc3IZP9%-+gJ
zEB-^#lAoX_?&zwBQ-ic*uz$?F?WbfzkRB1@$15%lc&s{O>7!~&Ow?Aynk(RqLKo3E
z^ZvL2GfwhOeIzT@bq1u-&FJ17#1o-XdZp_l{o)Ws6s@CLEe4N3Oap`h{14iw2f@Bv
z+-@m|Hrgf@=`#Yd27`((^C}K#P%O#Ic#x;EMkzzyWi%?Fq%sFoj!{h?@CnW(em$3u
z>@-jcf^+iZB+*q2kU}HsY?+Tu0(0s))c}+#v#XJmKw*+$IO<mvY!y$n?^pW9(U7-4
znn7b`$Hc0Yi<Cic7nGS>qd{4b32Px8*dqRnt_Ixlomi<JiBLOlUIF@jM7ZcnFGS$Z
zX9N4YD9apUKX{Y~BH=&r(+mm-j1M|;Qc$P{VXXR+7DhB*=gbo-ZTXkqi(F_T<OQPj
z$?OTo+7~ir8<c4>5Y<vtqRTvrd*a6-8k;ETtOcS^snbYRPG}2Jl1E?oLgAD-ia>SZ
zgGfZVL2{fISt)uYr;-Vwl+;NnIf}*nWq+}(BPuX#Jd?7JdSN0=S+^t}#Hr3KIgWA1
zf=&b&yR?f7L2*E4;tC4GJ&*gx?)grP2nRS19;s0&m7q_gET@ubrxh`X4bF>}3lL|P
zVkqoGj0B>d!A|Kc`-lx_2*k2#Xa&?B=#{2P1n%+40*h239Z#+Bd=y{m6Wa=@jK%S!
zH<BY4?HfNxq|8aK;b4t@L^7kLgNd6p94zVgUJ;5C<oc8{7o<bpF6lVWk~>!2Rx=Mu
z3he+|XfnPwB1Yqj;G!G!(=yh5w8V*vlqkVPPh)^DyK!ctp$@Wa6D1LDd<X3mZBnxV
zZ9HSAhW;fL1JSygMg9OGf#Vtq89mnUMK=Jl9s?R%fF+k_++8__9|WQ<LuRE};{zsS
zw$NNm$r^n<SBa2#QU(AnqO%YeXJDfqE-FdP4TrFt7aoH|TG1@O_Yg=HPCu{W=;=N(
zB7RK$g~)7(F87dp_Spd!vz{eTmjDs>J<?^+BZq7vvuw&Ci{XWpC%{iK4Ac(PjpS*5
zF59$=`im-p15arqmj)OuA0yOb*#`B1SO?Y*6!MY6D)PjSVM8c=w1>}hg_cgvSU?$c
z3F127JZxa49<e|q;tyeT7!Z~-8^RzlvvLZJQ*>!0tytsp-4$Dk8p>$qv=`@zGb5X3
zz{|XJhaG+IheTD#6z{-D1YpLbqmYzCZ(wq!e%vTZ&uo(lh#$R3O2)D{;A4IldBqZY
zwNK;u{xGeat^&JNlrAP!E+9L`gEwrB5>+EFwi-~QDK#Ty1#-!k))b-P&7{$08oi0j
zr6M?4H*N)uN{~gvUxX5YM!YI0A(IlZ1e7_h$rO+Er~p5{gi&F^qyc#IMcG$m=Wne6
zg-9>Uln|f1U~}T7EN+wq8gUT7e}wwL4;T2-4092|E(@;(XI6~ujBQqJSMn`NKPE-b
zCZJLpEiXi0G&(c~Kr-}0S!F8sfD=AzDUuFnMd@yF9K|E75wnyO4H0FQLX2{gqUwyM
z2oAiS@(Kn<P38yT1_~qG%VcnMN{_rm438ksrQou9+|#rlTMi)P#r~ihSNM0qg{+u$
zo=GCJUpVU;5UyMUK_ikDM|%`ijzZ$@dWtbH39eGKeO$vsZ21i~+nT6YV^qf~^~s(U
zo4U>#q$L@zEP^@)a|}Chb6Y9(>}Gn{9mj^1Lzdre6Q@k6dnd1D9CCUS!ml3`Sx^}c
z@gOYtVhT&#LKa!1bBBj|!S>R&wI;I*uH->6XZg)|+9&hc#7uU3+e7_w)((70JI!<P
zgrA1b$9Sk}6}8`l$6F6^<Xlqa`3ZI`mb_an^tRd5_fnmG&kNoEm#_B$u&SyS|Mxj_
zW;inpaAvsBK!ffXu6RYntByD-!Jf<2HxTBPM!#s77eXT=B%iNH3HA&ZxDx6ONl{d;
zN@`kukxEGkE=Y!@Wo148q*9TYkI2kNnh4*|+UE|~`+k4FHFM71d+oK>UVH7oXP<rc
zRp+1sb=7YfnN)@?Pzm*!tz=SVSqBJbGRnxXo(%$1hSQz%gc92I+nhp0W;lbdn~h1T
zHjE^XD%ld5Q{`FAkLnqJq|XSNjl7PMMWGN!g;!)DRN)BXZM*TXJ=*MyRF9^=BL{v(
z#zb4ck#|+R6Kx$X<i(a#a<nfdg;8_J)}pymE%+UftQ^Y5qZlDWK^Tg~Z%*W>iA9}P
zUi07q$~P_a|Dk%PAsU1z>nDqx1?30rtp8Kr3(eZq%<JhfRcB8#ZG*B@iBRW#s)oGh
zWsy@xqIQ{~1k;=S_NJ88*fCh10@W@PYZKl?^64vC!8_HGAuUE|)J8R0x2o4?rHe6o
z;^OXn<-FbjvL|N)n28fxr|<o@pRU+bv;5Yr6KAzd@90eA+jgv}4A{{(eRyk2D{#%Y
z-~BjWJ7w9-L}zQ`pqAl_*X`bz`%$HD`l!~#xFLf^?oY4NFY%^$di{uzyM_#!cEzN(
z7VeKqsd6xAq#a!Q(fO^Fg^Sl!7Cp0aP(yCW^5%)Hixw^!*|~7RklKcwV^%brHE~||
zwG$TQzI4mVx&wW-DKU85tVzMRnFoTMHHS{xvGc8yc048eer2svzy17g_W$;(TYs{6
z^3x9-Jn`v==hyCedtU9Hox5v){qQrjuRJ`j^N&BDKk-LDUtGKJiN&?oKC$>V^XQ@*
zx^8KGX4a-z&-845{p7Fvub*tsdbR#y|JC}O|N8NJF1hcFz0(#1qlPXBzA<#);O<Yp
zF}U%Q?+!U<#=#+7GZqhg_mWuy4_-29$hR_+27NnoXyTRK|D3d-d(nXd7cD;U{zd;-
zUB2|d>hi^}s^3q!E4Zir-L|gfZ+)@L6MdKd8GWz1Y4yP?Z+iH*C+@m)(aAr$ZCvf|
zcFsF)&po>b{AktgnrDlPCr*E8ap$gw7JFB(pIEza{o>`7zH9E>v0~QKKPt_7_Sw=?
zC*RQdvy;Q{H}$#HOZ78TuaBO0<?AQSoAYLHXXpOlw$3*i3jh8_UFF}m-n4t>yEi>O
zbN;}^S1%f}=;}o63HfV=r1HNR`TOn{CcZgs(WBS)e0uYep5L!7cOAHK+y!?858k{l
zX#do~yn2%A{iN)9I<Qlzxr25*Qy8^l-?&k~wTr`Nf@iK;eoOJhJMJqE>0Y&ah#AaR
z<J)>X^KehwrB7uqpY>F0OE88?IVKyFZccc`p<}Oa3dcX&6xE&AqncZKQV*w^roBF{
zG;QbV+j2W^E17+&p3~XtYn}=In0rS3G15b}HYY}Xd&Z<=>t`+)S)Y5HhX3&Jact_@
z^oi7vZ+=4bdSy8~K#sZR;|q^@XzI8T)7ut>v&t{bQ_Il1cXxvsw|hwUw=3S$4<wtO
zzCO`*&c@*K3-5d8^Q$-R9$zT%!!M^Kysv*ZQQN%=y>CBvYBn{pWtVDA6nxXj=FVbM
z{+{bw7B=*@bbew-lq&jPNEg-T7QWtj=d}H)mhRS};lg=-anWAojozqwM~`nvWpe{g
z$S$l+%?O63nin23dP+yb=qdY#caHqF+A?xp;tm>|O3J>XkAFs~Y^~aq4ZLr1J)a6z
z?~0N;H`<_7c%!lRZe7dUYi~qdo^Mgcj;!xZ=%18l);;}T!vL>5c7WF&(Knefy(=zi
zOh4S*c*>S5{a-w|I=J{Yqb|PLgctYC8GC)%B)a<E@V&lw>k_xz*l_XI;f2O^{8&w?
zqdi(-g05Rq9IcS>>r=!18yar8r?3j$(xTf2Ua5|6er{w|d7HTYTL-Pr=Yu<XcPXn1
zs$`SAOV_pb?ghSA8sESoMe@l_QSzsEchaM_h~Bkc4SjRXsf~Iy*X<d9_m(T`D&LCK
z)MdGFYTrd;OMPET_HKNGUnzPwSa-|n;L>$BMz8!J(e7E&$3{=zXVldDCeYb+@H*#v
zh5B;GeO_7iH2v!PbpO%xk>i^wT@|tyRr3=$=@KaiCL!HCD!M@+^y(T%tT3uxrxIS9
zW}G!)lZL0j@3xdwzz@v(@&ghMgfB_|3t3CM3cU9AX5R5AZw$}CV+f}+s&}Ibq-Uj1
z4Z~A;1S@M*kiPd6!^zO}^J!!<=+=+*eOVywEz4*nd!BwsJ*7tu85HoyL{26f;tJ40
zcvGa<e8f2=>p;LO&jg+(eTFD5rOE{cOWX&LnR3|^tb1^?n7UWv*S=b}R+Z!+KVD$C
z{2(VF)c{4}F#HVPc`lw|P>Df{e?B6Y^oUck=jlSUQF0u>44GmxqhiQIidNC}W${Tq
z+~_ZKrx2Nt`3hruYqQbrxCE~`3|m<GUI&E^Eac=f8#6Jw$%qJu1)7zW`BxmM3vxON
zG$^m#Q5Xn3-Hc7zT3R$ydXA<F^B71)#^uTFdD`gql#%rR1?m5R;fTk^7JqfvFeP8y
zT+28bnYzZLN_4C8^e|`)Jb!xaX-pNvmYi0@vua(-#-N0<>uS2AXk^F8LD7|k>ybIA
zVftWB&_J<4=PC3r)%lG#%sX_|1n=Ou^?#dx=xMj->811D9{9|d4R0^rJoV5Ouk0Q2
z()_o3e|GZv_vYVn-qIx>%wM@}@jsXEAOGIFSFAsO$r9oZ&%gQU^CrD_c>ntICQW$y
zPg4$GaqE*;O?vUr{9FGr`R)I@YT*0(Z=QYGq*s<)vtjWu2mZQ$^aoe`Du3Cwr<Y!_
zVg4}(E}P&TPHy<(f&<Sk`SOOnLms_!($K%K-)hOWshlyjcgSN`Jz9g}1=&M%&OD|5
zfo}Q6texMuqm<<xXeA6}R}oM3rj)Jq`m#yYXBxvoOK|SGPXzXn>9n6DlOC?(>p`KM
z85C~JhhAZ3$O)Rhx_eB$+PpUiS3Eq1<Li7|Hn!{jQwN7Smt-bZ=lLCerLcCS%3RbE
zwM-ivv|P~;aN4JulHrt~NkL_1VzB1;EHz`Nrt&7WniyDvI!g52KaR>fSm&%D{sov~
zeHil9K<PtB9s8*>l%w*bJ-91ISMRnzBsH-LaQuIQ2#E#8BrV2aJfmfg$)bC}`buXF
zG<l`z%Y#HXJfO|^n%0UIbV0bL%w7UzRU;aCwAD7+WzehI!SSvvqFNFOou*@wW-hC2
zc{%>wi*%duG_yDM*H;wH!EysgmG&y#ho7Ut@@SW47b-!eX3#$gLCOd@Ue0G=K1r>R
zRub^11K%T3v*C~36%Gj%vuM%5Dan*nx>!t;h%{>Q_}RLQIAjIZx5$`bk>$4C&>vaN
zdoLsTH7Rn!a|CmKdR<b{(9-9LEJI`V@4@risR(MOOTauNk*0JtOKv(K9kDANk(8k_
z1_Q<=Nw0)%$AQMtN?F5=M}i2lA_%K{-J&)G7Dfc6xRZWSQt+)!Lg+i$Oq1~wCPJjq
zJBbv{pL;^auG%FJGHM11(Dw-h0hvk4P$Mk9D_frgv7J%$XN^J><s~u^l_j8M1n?0@
zBEC%B5#mSIleE#FFD=wE_Of-Ua*bHS?d*~$jN$r6@e8x+bDoB@^0WkJNKnhamTooc
z&T%^R%YqGc;3+Ss10$hIx7<}m!{h)JEYB-!P;^CYDO&Kp4^uzT=X%-&us`yx<W+lq
z1Nlq}dkqilA@T!9MCGE!3xm|hAn&}`+87-`Z$Od-9zDpk6_yMhGA_?`M#@}M;qfru
z6DcN^^y)mGXT_^f%sP*%gO5{rUBJ;AM<2xTY!e`!$WWzy+hB?8hXPhtyzu3xBSCR-
zrlrIgpNA*4^DlVW?Ijq+7XU`&$vEz5w;!hfjRUFy@3R7Jh?XU8gj7_p8?*F-Z$!GI
z52(Hsk;Ff=a+A!mhrBESx=Y3BF3MCRt&?3M*q)Lhp4y?P+m@rtr6oZrycVQyiPX+D
zRx&Kq0;`0kMgrCe)ow3?dyyHYoz=2ZTLCRM!$no#F2->hDx=XK)Bp+gF?D6JLIeUh
zq54F1KbX4R$x}g5rSdLX;wjqLkG5{TC^AV;`?4SB%Ui%O1+mJIdLgu-F(QzXh*O3=
z1&I|!0*C}?F>z$xn4}<#Tboj97k=>yFEX?mE0OFNheLQh@FouqXm%?lVPGYoNY;oO
z*o-(4Y56z^sjvtj>1)Arqjic;kdiMb09po^WK_vWNK1M_w={6m=W8%fL+DBM?pI#W
zh6@=eCqO+lsw>p(1`#F6E=(Q~E)5+!1f36Cglh^?)neT;6=DPe&sOCTh{VQS1_iXz
z<)L771!+OHGJ*=E>flwCGW7K9l55{k=DvY!D7~_Ld#<$QlR{%;*kSW$A~1|Z(xC-8
z5^qGA8K@v{Bsg@?l$Gupu0f(hntpF5%DcklOERRYJ}w2RvUZG=MbY{+HlI`U0xS88
z{2E`fp4CF=kL<%WbOVe{*hy@`*AE%7C)}(eSGbcJ!)l+rf>n7(1GSip#EjY~6oK0Z
z6_nX8#oAER75XV7_|OzMoQ^R@0+hIQWqS{rgpApNUuN72h-?=-DSLt>93;grs&49N
zcRtzkbio9?H6B@$&I^P3He&`E==mMO=x*Livj2{C8spyxp@!X>zLhGskdrKF@;NJc
zORrJ|i>2|NuDonJy+|~sR4>C!pn4cGEQKlcdtsx?e;0(!eVV%Fj|}Q*amd8-OdXU_
zW{7E4Jiq8DN{X=rWO9($p_-&DODM?#8I-z5H3kVw2D7w3sroW*Wr?oQwk7hlZg7tQ
zVG}*GYBN6C8-s-KYpR@qOa+!q&sAj=nCmTJ8A1dC;{}p2TI8VJ`ofi1e5`~76;dSy
zth=w8gTt7EpqxYGL_IVX2dnx<8GP7PbmImsLkF?DW5Q}Q)zy(1?ivlX3n?EVKH1WK
zGDaAsjKvEx%0X(t90Bpu7^J%pz_HX*kz!$hRZz;J4PT)+(D8Wb8WPsk<Wwbv;Rpm4
zwlMxd>?24#HmXRFilwTuu)k#T2=uwsurT6`v^aq_cXxYp4)81zI9+XEMJv%*i+(a$
z6A-~^E(z)?u81<Vge|98M9|{1p7dhka~o(~N}3+a^@GMucWk`gk4UY!Ih~!rqwiY`
z5kLVYoXVU9iM8YhWPv@>FabFy)OTq~$c<^@a*1WRi4$<s671%ZW?^xOj2-8PLp#rh
zZs`yC#TzFnHlUu<QI#DoRF$6!N}`3rQ8BSGf-|l@$}1@?K>^>i(|X)F8w~PJPdDo5
zSYs){{-jXK63`ZI@=g#M8iICQP+DbbGmfLzW!edXitTLNg<htw;*UR-rHiOVq^T-;
z#BRiEx<t8Y(cf^%v|qr;&6Atz;u2xB?W&5BgrNoF_|!lNX#4_M!{Z=i&K@*$O3B58
zw#e&)By>YEXrF+9bfCuhWFO9Sysildju`D?+;EE|3tvGnaRTD=D`0~Up&)Zy8Hufe
z#ciI+Y^@)GbR#lkj1&eZ;Yg%-tW==*z+7BSk1k^o^HE2RN5HtdL|c&+D<W8#T~&2V
z>(FyvxoOFh121+EYy=HRCV+l|{;<e#{MtoV>9TRaHS1Up;WOPP<`2b|e`fq<{E-Oh
zNrPU;`!C%CnW0hxMs5NO2<T4#rCq2`xG7jJBcAGLAA6lVr<};pT)5&m5T%{$YPedX
zNYcw9k8cI5U}86>b$wAaE$MaR;)yBHD+VKu(8t<2zr%qt!YpRc1cWBvPuQ#sQBr<6
zE(fBcj=jn^;&Cm_`3MLt;PV@wAK=CsS~#qrmDep#CvMLZPOlb*ks{pEl5E_oH4_ut
z&v^>;POdbKP(kmDt^{1(0^GpiNs@*w=@Zuvu{!acmwUF<ub_?VaU4^n)>@k4haj!p
zBd6)laA@hf9gr+GNydSHy`zVQN;-1D9J%3f*#IRjlb(Je&UXeFW#iXk@YBgSD%&PB
z<Xb{mPO6%Pvg{Z0LMAZQ2S3|+;~U`*fl<f+M2uX3ad)}7Y`9Pfxz_pq<>pm!{W9g@
zSebsS#dE|e10`7XiPQ?xq%Wqe#`RMe)6#p!V5_bu!@q!a_y6~;ntqi8QT<$*D!mLO
zI`&s-L3~K0WL+@-3eF(0eS|9%TfY58q46^@CB-O(DF+V$)+cG|gk@q+Fe|utGEav4
z6Nt?q^hbW_7mhF!S5D9xAsUxwrK-tnTofF}?4}Y#$pnWt{zqkj(@K3^(xx60;-Y2H
zYN$!XNY&uG2gl%ag`~Qw5(QQQG3b5|d8~SKvFn0Hm;3YKuztR(E7K&2NP*Q{5WBFd
zBLHwtI^n7$K^SLC=AeLfcYc%`HXHl<?*^_TnmFYx<i6Cqb~h0rgr7DJbjuBZ&N^Bx
zA#1o1@5xR4?M^qDYYPO-;;i#=Yhb42RRg}bwi>_z?|v(&AJb14hxsLHiFfLn7<FXD
z0jUn0M0`g_egc*Y*6IzlMT8NAczNt29qU5zEpWt2OUR`r9%yzxD4r_nsBQ?1f7=e%
z*+i`4)fjQAX_DGedgEm9c81)<;$tqMmV$_JI#xMGCM91w_E+ybb~&F+I{S-H+J->v
z7-xmJ+>FCpBBW4`>Jn4;rj4az5H&0}E!Y@DQno5D*^e~+o@z?5!ug}ve-R<78;R?d
zo8@xZZIh71kOVtA$hD;9&L7&v+k~71ss#}<Kw7Qogk`)B{eD}m6=Fb=5-7!v+(A_f
z!hN4Xa{lb9yrV=%eOkOSz}fyh^mhjmAs}Jxd~s?e<La8j$n9V0WumJEtzFx|>oPAG
z2ik@E$9;N`l9lq;A1WhB#_|W+2+z?3EK5a3a(EPy#`)c2P2=z95zt&Rm*Zc+t$W~B
z&&zV!lqDht7j2v3lnjYknQL-RLD7|tN?2D+R-(j4fYo?S?01Oj&GZLk9L`j2)=8np
zcx_^j)4(|G9HM`pbCpb4(WO5?HcBzOjZ0hXr1AHI%-zk0EE1$#&K*Y5&|Iv4#N<{X
z+h7?dQ=&wuRH~}6Nc;#`6s@We9Yu$7_Ru$XLdD#`p__wNdx0Zl$4y1dBxgLcs(|lA
zJ`F%jmW@LtuVNfWg!!6P4-y)A{?1xXt1!)bkR?T7xkQ<Yh8;I8HzRAvIE}W(q>z_o
zeFH=^T@|x3|1#Mo_fZJt4!RU*_lnYKpARf=Sxn@LS=vz6jaN+ud1{)f38&kVB#_Hm
z+4h9JLa7UgvAm73HQj<z<WB6KSH6UF<1VSMg7bM=S1tL#(_?sc35gDv)u0?ck>AiA
zKPEBkT4Cik3ry`AYJE<bsn!=;uHZZe#)}36cT|&y4NB#fx8gOU;RTYHbrW!&Mt^ed
z+pJpUbPV}Dn>rbO`uYqsQNVl>y%K{}dtM6H_$nA@MM7I%?%2o@AF)iY<$=Q>MMs_*
z3@I8y!T|@QFSa0xj79;^N$EyQ8CWYKBIaOpR6e%%w8DN_8cbGuJkeq!D@#MPeeLHo
zuFP*`N1E0=_dwH_<5L}kWF<XlRY}T>m30h-@W`NX5|?7nhoQ|t;Ty7VEYCpNs-Q$V
zV8gz4HI8<kq<7Fp`bKbtE0i+csanBQ49``atsV0^XLT+zT|u4f$%&4cxTrI6&7$(M
zN{yM4^w%BR92O>bq&Bv#@%JpVz8a7if5%5A%zx((=}dXFpW!D?>h2hj826U$$iFo@
zk+nC4gTw1v20ySVJ@=PuI_BDCV+Y$Idhl5-I)BgC)A?O1`v%(qg9l$TVx9i<*Ei{>
zrZm@CaGPq=;oPR%_1<Nfy2`TJ_SCS}vD?n+Or1@&{QVSvK+D*=Z*S2Tr52sP@QP~(
zZGCXzpo#w!ec!ra%Y=0+J3hJY){do%KK<6%ttUqf8;2a2riVPb;GG+`PI_ldV&1+#
zoqOf{KV3vzuHn^Xr_VWfMqbT3<C^Jjjp<p?epBa(<!{Yfz%~A*n@=C}QqALIA0LpP
zB$vKv(Z@HgY;J#N$Zy8KHRP%BFAe?Y;DZCs8r!k#?Yi%AZCp8H@Ne%O-mvf1ucWvX
zagEFVpw!{djj8|V=f-$1+&f|1qED=CSaj*)ix!@DaFWyarp05|t^D57Ez7?*WYPK2
zxf93F@HeI=jNLf)in@h2EI##}<9m|(4h)}maPOEaC!W;ozq%|x=HQr)#&?fThi@el
z)9<-y(X<DCkZO3~gw9V~(tFLAmzKRW`0*i%OE-`gfA7j)HoP<BuDW*y-!=Z#n%l=8
zI(OQ*@2y<pcdRJ+dsmd&58gWgT}QR=yJeI<bnYc%UOh*tL!Up_`{(Dg^)v5HG^D-d
zetPsn?fhEUC9=0@li%_2bp71q!b|teTX<pZm~kujG;AEOcl<lv-m&l0bSw>y_uG><
zC8njnmYuU@<;I3-_bKznaY1s+=$@=S%^y70OPp&*=f~LNt{J=PewAEv3qQ0qt}|>;
zEegh}L_=j@bK{=AO{q<FZ|OBFRO7_nQ`N-g=Ju^aXN*k{_jc{bx_4JD4EL?Lx_y4(
z)Ny>>*e-f~=Y8IhH;t@Yc&Sc)@xmScDc(6_(xX40xyDQSZ`C|MWmC=bpGk)s7p8CI
zT&A^iGv8jxvgd$~x(C{WaZ!6FQ#dYDm%O7VqmI{CG~C}~esW(=@{MFqWBUo6Vam&$
zoAOM9YU^0AX=N!~^AV%g)aBKw;}!)I{bqmdz)Yjz+T%Z`_N`FizCuoI?d9@kw9nWj
zdR-e_U3+ce-4)H{=cY&J<)%kq)hyXpv}f@2Y<|%63zfI0ma{3&E2!Me0$;DUsP5Kv
zT&AXzuccc|p)1H0j7r#gdnH?S8nm}&re^JDb>aD$jkRmj75lx8irqACui_W>RC-=e
zmoUK!4l$}pjpItuf61!V^uV8=&HCeYpHg$U+8@sw|J2!PTK9lv-Cd)TxsOM8pj$z7
zTYVQj%3xOgYl2HvP5GSXJ{~<=@N*0t#g=udIDOBcFkx!up_erUQ|KwknRlVN7QGm;
z)`Sw*81%H7-gIlFH{Gqm+_b&k!s#5bI4|HNqsHa*bv5(mieBia=6ZTu*8fC+UgLeG
z77!P1M!%3VLU;?yy9f5A@Rqh`C#M^-zWexWmFaU^Eh;mk`ifFv<ps-074&HI*%fAh
z1+ub-e$mW=ug40`tFY!Om-N}Y=#QVv6P{0aF79;Df#u``>t&&#zZO|cpRKIx*sQLG
zu^;2AG8(+Xl+fjI^Yq_F3tp-2ykR&)F6(ouB72^`{7Zbw$U=6bxS)5Vk3=*4S%o#|
zaQgyy7%QS#fwGc5+r3PWQaSQq==jx46LxLIKM((O<*6iocnm|5YP3!f!}!4E@vg&x
z)3rPHGyJIxesRJsr3=^KpX<V+fy|o$+4IzL1s<P^`H2UIRWem|P~l99EMH&<f-PhY
zXV}|p2t(-`FvkDTe6~<cz=(hrF&5f7Vce=hee1A<b-WxZD@_J^7(}%yh(@9N_xt*B
zZqL)r1CIoccuZf}<)<H^yBLQtjxUSe%xy|-YMNyX4SeQ6em+}tyEb@0uW8TQnuM&5
zj#Iq}@;;0?YQpQQ4Fl_`jOn#iWmT)}dAfBW_VN4)oa1!tn)44_@WOG2-<|*VUk*L`
z{@&L%pMT(^FC2gPt%Kiv_RzMM-<iB-!GVX~IR52#58nKjC67LR;4`-`J@CWb_rLh=
z+?!upvia#Re}2PNzj=D<86O<ld-J7}-hTQ^ZR`K|_y2l!`zwSOFWEfxODDeg$G^{h
z?Ti<fbgW-IY4dqYCck(2->>}OyYDZ3c*FcpumAa%j(;)v^5T7OKfUDs^;ewy#CdNI
zdh!0l*Dl`tl_ltQvQcGBvB~Wrnt2*JcV$&k&F9_TJ6UCS1kWw2WXb~%&MeheXal=c
z#kYQ?ozu}8-U)B1*`ro1%PI94F5Qz-b;dU}J?!zwrQC1QP~^d~9<{5thxdX#^Hp6>
zcJ)Amy}BEt<+-|+W!EHwn!M`s^1)l4QN;lZnZoVVHppP#`3-w&-qtO(T}qV=VN;Z;
zO%<%{d3xvjE<|?`gB8c!#N!?g1M#`~6ccgRuBteE|4pcji=hnh#FYuBR{RdCRWc6r
zCnzBsqul*ph^n=iSzOsDch1wOQy|Y6*WipW*#3nd?d8G(+(ZTP(hgrjWmN+K{FOop
zVxJBY7I`JC40>w4Ng8#Zfr33NRANm8eU(bn<_*mWR6LDld(s*S3u__aEMVE^5+-Rj
zfQ_2xsiDqG!tQymp&ClT<STe#%_?6E)f7LJ#{>pPTVEU>S`-WDctj%=<W=BQ^D?sY
zgE&4QP<5dg*w-Qxpznj)XnLxQ@Jlw;CP@alhMVkZdi@~+L=aVGwu=-^FT-yq5>NLO
z89GoIYE%~jrE7@!@#rwBHxiDhJW`y*w1ZH(BCS1=o*mKXCZ+-~D1@GP@$rOK@+@6%
zsLJ%fgsGeHqN2u5inGUrh@lEd%IsUPAcR!p!f1Ja>^JI!$ctkoF5`qjiI*TxkD=#M
zl}JzYC&prOUL&C*aIV}OXzn8E93zU#YmI;*(SwVMlNAz;I3p4?!VqPY;$QOMzy>KR
zc75bL>XxshtPP1-6GwYaO?i9($@v=soV)_FC(oR?eWFo27aJYq1-wWn`M1EBj8_L6
zme=u5wqeeQ>bQ<L$1CN)Kp^WhRA(M|T<+vuZH)x2U?X3$<{Muy$Z{)ye2w9}(8KN^
zKpBi*abaRn4bYNxLYkzy37cvPd3i0%+(B2x62;1)b;isK&Nw+$YT-9VMjHBgh$IZi
zUXg#EBLV8LL`fBf)rg&>_OPZJYAb6uN<soyz#u=Tc0iKWqMjT<VN6MR2nzF|pACJ)
zcr>oOn7<G1Dx{oCVvNl^XReS0`r~4|us&-uc{hfVRjbO>BvOb+Nm{wI2&vxkln8Lv
zuUMFX=~Z@sH3Z!|Rf`8O@r_eA;R<Jq5lGw$mM3m{Eao~%3AFoij~TpmY>Ur2SrRE*
z2z{SA&+h@pL@aVMLn~5CtjB*!tDsq$pa46>0mCej%tmUs*!b5Y1qWCg2o-xIT)ixz
zw<Z%x>?Ij;)>O+?(2lnN0t+Blm&METEEb{aO5I|{YqivYI*B1nS7ZW_%6hyJNroDv
zl~2AY9+fd5t*14sxJ1MSy&67|FC~vh@Sc_=IT?rbE=%T=o}k*+v9<$b+@11g@}v17
zUK5AmDwC2YA^dDIsHqlDJ9}+p`3zvck4p?PQZn6gmtWB(1=*9LTW|x_M|uWX0EYq^
zaV_Y6)375>T1lDwSkapyCQ!Vg5F0P29-|Z04GL8hX+~X;lrtOWX==VEN~htlstX$}
zqrkFMIT4K@T?$;IHte5OJF&~uXrR(sHFhB-sLS`A;K(2*tXPKfaWbo;$~;1RQxN!h
z+600)Gp0SoP6M$+#wJ8Ixw2lqfsD&9=%KkcS7JTWMJ#EA^Tf_dcKujI@$$i^x<Fmh
z?i-l9Ns#PjjcQjs&bf|TR?ab57tbn@`iRPR7>m3p+18@w1jChY;F;>1l;kc`#6Tq1
zSXR*tJemq0mx!^*HR=|rrzD)W{21I?yuPE-^ju0~MfNk5@w#)KRKhAVyF03jP+aX%
zme1nlBtFf6YfysxMDrQV(3{ahY86#aD(?;}d!dbt#(XYIMF!0oO1?kO%%keEysG5`
zLA6HdX3mi63P?EJ8%D=n(4q`Ad=p>0cV&>OM#wb7=aZ9=L?Wwt^Gz*Uikk9HQImDE
zCJ+W;McMo&Rbvrl_~G%C4|x=HPfIdaNYiR$BX&|68nv)ZbPU1<j`+-YDwVXFo~G!N
zF90o@6H-kGS*2|ahp09LsT^U=Z+)(^UbxEe{D;A04@u<#;gNxCnK0oV1si)k93%4d
zk$6D?P%|V8A2q=W!f?Z2ig$Nn-lM=b;+iaR`Xxi<hf<+pwM!#%z{Fq0s$0^luhS}z
zkY-63-q0l>UI#)*Lov!Hb;st=)ti4L;GqU(@_&OP(SoOV+sO$&*IyG>ep2ePfN?rO
z;?glf4W}h}vm!494k!Yc4E~a{>p4H8*@;94&SS((s@czq2m!_~=eneg3rKFrI*pI#
zIO8k~O@%nAwgR3IU_fngF-^V8y1}Y$)=(p8hFz^JEgD)=)bgz=1cr!^fyly-vN%aF
zKoC2~#N*5w8bRf?+yTucr!{G(uY`=uK^&=yd(391zDN};6`-o2v`FFaS6>oK6CA{N
zk%3bAbf;BGQXhwcbaD~U<Pk5*dF?_;Ym`G-`JBpys!Zh6D+|J9KWXr3E@ff|yjMhm
z2F2w^6-|pG0D=1#RqG{;0i6R;)m7H<=*Vx*JCr0Wkq~xA#xtCL*iGRm&#0(N@-8JB
z5HjH0TpnU$VM^l(Sx7<xzgLM^!)!=uCVnSR494n|u)ER;wD#H5BS@9BatHdzp3qsR
zSM_TH5@muRAib@Hz#8F0QM$b(KG~=9gKa|bFQ8q>P+?D~=G;?VAf?9=gsXEYN2EYo
z@pa41f#>F4jILNis}nRxNtG7cKYKs{rK<cQ&p<(G0ak9kA|TAW+&fM|`c--@0hlyH
zqY-Ag0_eH46KwGTO@uuWt*r!I6s`yit>nRhRKmC_X%`j-r<#k8m692J-2FHb-Onp&
zJN|BFGe&H=s>>xn*X1IR;aAfQG`w!)a55x)Q}xA#Y4};~SUVZ!J_MAVOxEK#8n!hb
zij4hjV5(+_<H)4x>(8>xG%yMOM%jKO9RyGSCyWBjHq+2p@w+7<@h~@VcaKSwOCvBY
zEVpu;A$Ve-v~3*7BeT6Ksy|laF%$+)43Or0tLj|VoD#NQ6}Jy3FS)9MTQ!LNwc=2d
zojr8ifiuDpG~AS$OS)t~22sawRr}Khwi?I0I1tf6G0hj9cxwdUwN^ZN=Y>^jfpJ<l
zOD~c-(iK=&KZKTSr?l|$G=`vx;FKf`82SKFn0gdyLBvLpal%wP8+aUu0y2S>S&qo=
z))vvOlw5qKR}^6!vc@Mu^5hUG0=ZSY$&ro60LhSYpD-bkx^C6y7CDuMgO^UWf_he0
zo1pA1p+OV$sSo{Xsx~409}wr6x)8HtCJ(RXohVI8qm?B=VtZp|(URHXQP3t<*_E?I
zP`7P=qaa)n9pV<L^bxir65OJ#3bdP-(HF&#j2-ss_HzV!W1pxZ5Rp4T%gr@|NXYmS
z!eQ{%aRD@O(I#ExBNNz3m@Nfjgo0^NNd_puooVPA0L7)H6$u?6wtRv*R#gRC@HGho
zu<DZ7m<Cs}EbAGX6b)%>rysxgL>yt)|5)*eR#G|w8g}G5BRd2NS8ZUAq(}rpw5bwQ
z9isy$PKgHaxXO+fD7zG#7tSLAEvi5oSR7@XRPl)#E=tVf=0#3sHAcIDaa2b61&2mw
zVUhWhFBy>BSgsg6ZNNiG<_sow1>)2YTb{@2z5qPcf>hQ(=(j=VhV@u8>7OyXh*uhY
ztA*<7k|#)#w&Vs6U(TWnM2PRjG4+veJUqh8f1X@-GXV9UjTs=z_$c7SAYN<^?>NHk
z8eIrF0H=&AGVYQR0PS=izr-o)+LYK{M5Hx0zzq<-b~Q^I5VU_`sU}k`eDENeaD+ra
zvL#}5jhl74f!Px5cKOxrJ8GHJDS8EW{?L`|AvJ_~Trt9`Q3%M%jfCS$7N;Bg<2xJ<
zOnk?2y_7OKMhKP8y8sErRZC*>WY`lAAZ~C(^Ee+aLNZW=qdgt;+9BiEc;X!+V!X_5
zNeZYY03m9EiNn+eeKa**QfTnehZKm6FkAPp@x>EWJOKHz&ae{Du{{hpXN`ViNZg0O
zBT^H#vKME`-4d{taCcZk#wA8B%x|>voKNDKTrwgufK@VUxcZYgVh<uECS8?LjgNZ<
zVzh8L<#f?E{ndboK$j)865f7rWH~~%igB`Ie_kA?oUNv$g1$f~X*$Z_I&f`Xbp0^w
z?$-dM6X9~9U455+j&!Y&TuRE#VYf6V0WB%nqy3S~3&MS|<0)Tt2GPp5suto{FrI!e
zP-+RtP%dCy5;pF}9BwT3tSU>AzVZ!Za3Qk2iZ?63$8v<?2nc`1H%I2RhH%)Pae4%C
z61Mq6^lnNbh11R@^284q5;o!yTJ5sy3S3Z@X@C(=Ji#-L#`An3^?hysMIpC<E25g*
zIOcLIgn%=r^BW!#WLZH=QtTy3i{+$I=Abtgq@`K<fw3O=lI+u|--$kL>h=I_+Bq5^
zrCa-mYf_Y($ZTh{@}Um9!+C;l?s5~<Zf!)vGAC}h{P4>(zJW^X#44#`Bg3#kR)U(_
z^(E+odAgKgzNNVvrPXd0HUdxIlS4FJtbLBp_FX<iMgG}6<~NW4y|zhVOKA@Sq0KRf
zX#CNzlzO9xN3txy%Y>Z)3rq=>fYvHcyRz$}3HA-MGS|&Y*VtaCO@q?v>I8wdvOiYw
z>jHR<jRKxeY)6#9z8nbSN>bYlHfW~4G;LCnPut$6t(GM>S3VHcc6ic7b&D-en}Z&K
zrM4F@9jj4-em<OCEaEK|+u-;7p1j~WBt(0R|HCL4V<~Wp>T-UfaWhdXk3VhHSJmB3
zCCI6}RZjDR5-CsZWVJl<{l2McHuc`~ukbO>z`T-|?#y4@@=Aox-6@i(Q9JUDWRB^X
zsH?{zaRxh|CBJ3Mf*T&}(=<jge~clYB=@XiRTzmP#)^D9St4ql3hYip5<^u`M*bzr
zW;H9cIe3fB%C@OCwsC%)&x4>Tcj^F(H~I_JjDRQNd$a;9Z=;pJ!dG1h-_y1vW8bcZ
zbmW1xAq0q3r}kMJ$)1}X_Yi7Qoe8zW``Pabb>kM#zjpk>mljpJmepJ_W!018t{%B)
z+(|Ppp4+x_z&*V?r;I!H!Oqsj#m@b+`)XdFZJ!)`soy!VslD@^-|cyF^C`Xgv7>7)
z8T=K0%s>8C^Sd|gbNL$^{_UgVmwn@sC3inJdujRkbWQK_AuEQ|UA7?gd~WFj`>sBG
z--?0v4QL#A)x0-O{n#}ob$Qo{0l!~a7<5)LzvzsK&vgD{*^dUiI%D~OvnO8IDf+(4
zbM*b~PYxJ5p)hg(2X8FlTCn$&mw&qFl#AbA@Wpi>EcoK>ADMpAnp>xzbo((kZkTuW
z!yEQ|{J^EFK67YP@w)x<`_ANgV(;H}zP#^mJKx_nv~T3L)B3JG^k;A7p+DEGykgaV
zermz0UtRg7dw+D@Mfd*b?CaWoee%+_U!VQg<9{<`KiBq$7o5#?-Jh=7d)gna+I#kO
zr$04h$>~oGJbdroFLKrX=k^<h{O7hCK6-e`FD~OcU-TVDZGW`m$JafU`0;greP!Rb
z_rJ35j(w-R_^Hammp_iKKfm&{+dnsb&`Y15f6`0;`S4wDeEz|^-n{P6r445v`s%9F
z{yM+!kvC83>;3I>zrXk3FMhx5u2YvS+&XmGqJuxES$XI^Z@_|8H@ELub?YS;-TUi*
zU(){TPc3b`pmyoqzdr6SC;w*1n<xL~-wuzz@`9h=_-4}|u9{!}`>Xb~efmFE4E(}>
zJazoR`{!Q%+WmVk|Mf99T=$O+Pha+j1;04<pG$r{RQ3-2=hI3(HvGpQ{r-d>kKX&a
z;-^-8rT*{wSF3(Q^*b;wcyj6V3wP8NhfQ0%yK7otkMmD_r_KLbuFZPk+~NffG_6{{
z@4~)&cTF|}AGm7giR1RD&M)mzEr<5>`42wQHz(<Lee{Y?b`5>~llGF;bNXh??)}Y~
zpY8pPcmC+-hlK6VpS)G=op;#V8=imn&J*Txef7BPF-v!42QR&1`qYW-&rD5xrss?S
z!+R#*-?8fx|9#x9i^l${cp2T!Wuo`*A7YQre@rXv*3%NZQ`djD_?6<&9<MlC)fQ)m
z=j^CU4SVv8XC_r1df+N^eYv)w<~eUw&A}ag{==L4)Wc21wl@=Y;4@eE`5QB~yY3Oy
zJ?nQWJa6>cfer0z2afS~Ovw-3G4S%c&mA$HEARcX_Hyr+ADe!~^z)8sf94B!u-EVv
zZ*KSZI||LOA6GalcbvK8(p_eT>>Elx$Zu`Vc>cO!6P}-P)+6Ri8J+o?>B>kq_f7vC
z`}c>thkx<msl(ewmduyG7B+nS+Rm1S#hooPymQn&D>Cbf?fJ)BhN?}vH*9!hv+w_P
z&gzB%(^mWXoBp~t=8WC(Zru&{wj>7KtCsoxFNf;dk@wP9ewR%+bH{eQHDQx_Y~_t=
z=|^r1-fwEFy{<W_<`mSL%rG_M!3ibhe#)nQtAAzv)|#>O$8Vap%%8bZ=ytv6{y;dq
zs~9Gt#Mit1iJQ9pYeux}TsWfTXDU$py}*9HiA^rbq+5D9^M$Ljc(tGGS>2GoJG0L8
z`s)(j4Wp-dgGRTMd^NW0`~UU`<JH|tP0Nq%nwKBDW6#}#)qu9as-{WRj&Aa5=g@2Z
zvYF4tC)l9OH7uOyPYCbuulACGT$hAKm6cXj_B?%&K6RW%(>#}F8En+=RF}G-4Yhrx
zzD+lmV9K5fJwMgZ<+u1oHG%&R;y1!kW_xa=RbQozJyZ0V^Rx~}5^ouUTAEm5f~H9L
zEZj65Gp~QtFC(k24B9FN|67bQoy}39onE`a)9$T>|7W)+!&?;5>st8W&2yExtn7J$
zN1napl73i`mu~KcYa!VYyIbDqS8$VDi@D0Ay$AOluC-jdx%kq)jr^%uTx+;27uk0@
zPlH~@Ngf+Hq$T6tcOsgU;_-!O2ZnpNdcE_L9ln}(Kl0}>pj!zW+4BT&@KlimMMo$+
zRUr@f#buQ7WW|SA-X)TP;7P^D(pA4h$ObQ6iM?@VVcLVRorvfbeE+InzoMXI&l965
zattc9$%7(^{x=zk+~XC>STILHe%tPUg0EHAJZnYl9v7!Gd2Q4bUg~8VvJHOHaN@`8
zK3`;|<^(#Kw@tjLQ4Q&EWS!UE-KNwPL1;(vP@7rZRuhb{!MM|sMY0;0#kP>2|M#Er
z<%OE%&UvD=7Jv8Y!(-mtKl!n%wtwuk%h$iZ|5yB0-FvSeKJ<mnC+z?1hWGaW{pU-!
zy}0q%N5AmTJKsEh{kwl6JmJ6YyYBI&n?Kn9r<V_1b@RT-+y8w3+1nSadH<>j?;m{h
ziN#9~{dvsj?Q?H^dFl2S51p}n-;(X0JMi!C@4fXaf1U8tC6BG&d-AQX9J-9~)vs-S
zcIku{|2X-vr4!D4tz*Mi_P_n?lKXzZUaT)XdctdCHoSXy^LdBsx>QYPSA#+4oa`YQ
z^SfnUGT%5*>yd52Agk7#qk_KK)+`vY&Wt~<q3z+?qIX|YUk$(a=Ow%6jI8@i-;|ms
zt;&DSwxqlkGv4p>hP3zjC*)P?l!Z2zro6^u?rVCL-<k4Tdi-DJKjv3vKcst`f2TR2
zpl_EBl55S)y7v4}>TD(*CEJ76G3_fT>lLL!{n*>&xx7uSpmI!E$TN_4bQwnURlG{(
zegukC2LfK8C_<?rQga<jTp+OA`T=1vP<ND9^|Q7kO#M++tT?*r&s5zHIbJ#roWPh9
z6I$n(Tx5y~+5=sa>@gt&h8dz9)DVV^JP*);7}eOuR}CQ?Bq4VQ>9e&mOa$$^e66Ub
zJT;b{04?7{4BeY7VhMzK!x3e^^FQa>n(}jmFqVBzwONJ8aGES#B3yDM#tGK&`akZ6
z40G#lzd2}Dqjia+E{qumkss94=?S-?NvJcm%30EzhWaRKmhrSh0%BidtmTc4ET1Tn
zV*VIEGX(MkJU1kJnl&Pq1(a319@DOKkzZ)V=ZeTT=pP`T<b*P+Q-v{TOm3|ayDj+}
zSjnT7zNRT--1=0A>JE!sI-CsgKx4C}zcVU34}qR6Pf?`R^zRk|bm!|soyQyavEG84
zPF8eW@M0!d5N-?je8Y_t{7hu)RG>wA$#vAKM&8YUfS(@Pr^lB5UzV7iI?shr@;nE-
zQFU(4F9idGu&7Lq-xTrji<wBz;PrbeB%j6yMqUG3@d91K5whE)WVIP=sUgbGdR$~v
z3xRZ+kPws((dGE!zYy>Z5$-+B*!nI8Ls6KuQL(Faf2k&Pa`cRUBBhPz#yAWw^-<Oj
z+we$H7TLEZO~hAid$5)jboD*3<OH)&AM<#OV!d1A5rsS*tn#hJr<L!81vrsnC91ZW
zo7kPPL<}FOLN^sk9*V8x8k%~e0t-@0ASE(%6m?VMa^km)P}m=0qW~>sM$?j#2RQh4
zb;4Q_psp5G<UZckak=}T)hI5lxfvrb=iGS(9>I_t;wWF5jSlz$RRW&smc1f3$w=%>
zmX-}g2CtadN>w8VkoFm*8fq7NQa}Ny$pSj@ybUP%L75^jvMOld)++j>%40CG1A`;x
zHE?jrARc!BcwM-nGD0Om<HlOWsya(6{jW%T6iI24BRzDmx}hTLk;1`)Z7)1B9pDHn
z?G`XA6*Y(VnrO{7UU&`VL$u*qUbI0T*M|ot%hRw&1>l*H#AMyy$Zyc|H0sr=HrbEn
z8`YbY6$7baY~#^cAqi0E`k*E9>O^w^*<H!nyyUXW;FrslMeJ1xvGLdTfW-)6R%*%$
z#P}jiWOECsA8kZ1q2aMyX;u%A6O>^|Y72{yg{PQ6T&RyilC4)DtfB3)S%Q4T_6$re
zt}=wRvfR5cnkk8Z0MSN{1=E&}%GauvvRWr?M3O?Uqaf=WcdLM3TC3vRdbu2pS#*T(
zN^h(>EVY<3V?_vvHi?v#2h3UL$#McTmavG?5}E0C0$o{PJ|LGD<?Cz{M{SD^T9AR<
zXamv(oPGg*ZGB0_xVO7O#M|&)2wo>PW|X;rWH3}TEwp7*aLeF?Ss<ag$&674lFvYA
z4H~d*0TYx^RBJ0_szB~wOM8Ye3K|g?pXrutFjCBbX=oCsHcWI!s+Tj>3>tz)t9pyp
zuCt+i0!G@YVkKD^B~MmlXz8DtRcQvDq^>OzXfmhxg=wm!QfXCCeQZiIQoB|}TVOIi
zbyzC{yYc+`pb;JMt9+Z$HFaJ+hZPhWd!1_ZLvG~hG;=f^b>o^8!g`E{U18Qv57v9K
zT~SU@{3N8sAr0Tqz^?97>c7Vk&|O4X9wKU$?{lE7>4t<^Zv#ihwxVwPTn_@YZ}L*q
z*ML+nFxJh?Wvi;1K%G~ODGpO27t_uSms^n9n$_7Ie4!fjQJ5Vb=XZ<LAZ7Uak1B(u
zq-zM2mu+Its~%?hI3?MYXB{h8q1wR{&um(jM%6I&fM=+*hTh4hyxx`y`AMPr*f|~_
z&roQHqMM-g(&NqLQR#DPeuXlPIzY4OcW@(3yn*J@*QQh!sz4c`O%v()IkZ(5c?p}N
z{mI^J`(#b;Io?#6vlt{duv|8RAG)<+32o2-{XOvXZ*!EoOrEO3DK*?Z85Lx}5wMaw
z!Sy=?cyepRk)#FCqL#ZW;R<RwPHbTK=Msp!0Hum?P-CKAPt1;78yT>ci!`ZxPN<+L
zQ`DoSL!=`MUZS<c$Pc6=G`@J^(ilj&yeNsE%?0$QE@X^@kO+&sw6;b(c&*C>cRASk
zD3BJUVl}6gBND%jU+NNP36-haj~;}s7uBeIh7>4Wp>v#KSJ&-lLDeb_+H8r+WJWq3
zB68ftg?tCvPlOl0Hk#DM<0%>;em67FmUbr<#8KhGCn0$moT3Y*9Xc?SG7zXbAFY(;
zGOk1%D;e=TZ5UZ44I-Qz%~`M3DI$m%e8=i)cvewUG&f1GARJ^da$`@#en@$nBhr8%
z?};NCSj*P}(%yWg4S@6qRiKemWq5fPgT-;<V7DY8T8Z7Z{94eC$1)wNBgBv@K=;R;
z@efKs(r_t;Rc>%rBG|ts7~zz78KMM4B>F3xHcmX-Z;U7)I>94R2xOakL7EW*wRLH5
z2Ot%G<~>e^pitO|HZuR1XF_WjEwN31?iy61aWdHDN8jV{@eR%@kuN{X(<fC_@<kew
zrpr_83#GRE2Am|`%Y`P6Su8C$fO!r*fO>669Ha+Ef`-w75NX+`6Q}7(4b>1>)JF@A
z3&f%{%V35Ot~ACV#>T1?geg{yXaP@iQz|DtS$~e4Txy6Sd5ml&ra`KhZw&3-g-Mu9
zSxpq-xj09_Iyt2s#FIE;ND@gxBc*91*KVS%X3&ArnG*hgKoL@7$$>yvwVS0YfSYDx
z`n7fOPGw(^L|3<Kb!q7i1;<k^a>Qe~Bz3Xnv&Z9gU8toq3z>nrC~izsRI#kIc)6+>
zz@+^r12{Z}m#pAWdeY#`DLrvk1t*1G&bfFeLkf!J7vT_)Xko8bYXlmQAh<j$Gq!jt
z6}aIXS^;cHQpS3#gj0A@U`Wh}LQb?{UMdSrfMo{<U5?cDe*x>}88Td110U>hE^&6n
zS*mJD3V<<4V)$eXbFl>}cTzRPxg^JeAI(F6&>aC+AOR}(fwHtisjvdz_!scvk(N;&
z!&}LQWM5*OSm~?QRRdOAPve)Q*>ULl8!?7hK|?;%;I*PEAl!^aR_@&T#l_}x4B({C
zbulP^q={%@wH{k~IS3dUdPi(7wGF^r;y@o3<6%w)Gb1Q%X%^l1l*ziYq6J-48ILB6
zufQhlD#RYAVT)DlyN)v~u@Y5qwqz`ie_}DlYJM{~t_%|HuMqMjjXm`!dqAWE&D{mK
z@oydS$jzCqs*YIDmwKZED>Fn1kPy9w6+V}1XQL9flaAUm%p3*X4M87GH%FTwC|XDd
z>V6Migo|XUU`7TuErIxsK4LN}ju*A~G9d8*l<Q*z>G*I<IX9z~Cm}%_WE)8$O8_-R
z0?D|?Fv3(tB-tays89<qDzL5X;&XKszJdhMM6wX?c_PL5S==QgWk{I;On9}pF;vy!
zGZbCT2v2YUa)p+pNs0)`42~{Tn<9uVtJ1;)Eh<Yk;-rg&1p*`7F>_0(wa_^#QWQG^
zI_8$J=&H08EE2m3J1ip7s6)wWZDTGSS5{(-hA7^vi$@!7B*MS6ai@&qz{fP6NRcVP
zH{#t6ApuGf&`RZTlB&V-3Y@%y09>5Z+sZdwSXub!ERbaTwA3pt-I;*fEZnQqV43bn
zYS3!##n>x%^>wGC^E&<fGJ`W|Q1Kl{t>%@kk$93sHOYfhp}&x06y2U}kmsp>(Bh$z
z##}BG=S#*U(Zb-wwGNNv;x2-PfgO^PPEg?{7(<A<$#EEpZ1Ru2xi?6xwQ`pqQ*&w+
z#P6PltoTTWmIN&xF832#%oFkEJ-OqRJtWOfIWKARM&D68V+es!R@LHWsj6-9hH@|t
zVmpYY<S0lxR|PB(<0~U7ZXv8u1{yh96nA26K^(`&+y@VuSmJ<Km=RLYfn@-S3j)=o
zQ}AT46ry`#ONnM$!cG@lYq&unY5Ad!W0RP`fDoXm5${Z5BrL(ea*Gpp2b#H%bqTwn
z1iSakXYLk%rl?~MH}E)mx$V26-<!iDIx_<kRY*hZ965hrt3~8$lQp%5cmYYq;8^@g
z6>xV=fo7&vyJTB~idC^9$#6ks-Q7i`q<S&A5R1q0ieAFtk4KfpYU#ou)xav<B!mE#
z6^A*8kc5FTVpb6v>uloOguRl!7Gx?a(Fcgxtn20>hNa8VNngohvwIl94xw-2Snhz1
zo3?5aU!0!?Qa1*r3>a#5B-)5>hRX@IQu@>@vEvP|JFJ1iI-e@gV4Wl!l8vFhY8VL#
z4s}viY_AE#*~8=VgDWUfaD~)v-Mq6Z$SQVt2-tqfPMl12(njeuxGuuojK^r|TO#9c
zZLx>sr3#Lu(N+`3bXA{afYVt=q#0105v!G1n|@~8{(wa)c+po`9eW5L0ZSlPRZAQh
zXEd<}U3@a?+J;&>PZ+Gkh>ql$|3G$sGhUr4F^MjAg7S1J4JNo=)w8~!>iw{F)g2IO
z-P(xQG9T23FDb8#{k(1+>VzuT3Xko9Hls=^Dz~KElCZYeE2F$(ceJL46v~|U&|;!6
ziC@0{plL>4s|q@3p1NBWUTxG^i}H=C)$^?KD^{L}v5nt+&klq!r-{O5uMN6lS5E1f
zg@85bFh~?#J8CW(azHh@+*%pT9&H`rc6#b!7<t_^ty00LK&gyrks?%PI=^|zEHR3t
zmH^>x)A*8|2<8K6rpQ5y)ayDw(3bBd8-_Dv)s2eS%u@<V)YY)t@I{NI@jT~N*ds&t
zh27%)V_!IokKW7{(`CMH8=;zdgJ^^-X9wMUR~M9wGOAS<HA}V1yXQ(9)UF}Xq12c?
zI_#i~zTT5oy(3h6Z&n8>j~>5=9TVNuGCu419p!7XQ9VDi7nZZw(j<bWwJI@u9XP||
zHOU<3sgLSLez_0(U7tlcI{qdpHCez3cPT#!=3;f4ACwp)>8s8ug}kpmv7{`0iXHag
ztsrM{zW4Q7t%RK}rDb7R>1D+hrkvC%=qMZJO{L}xjagwk-X!_O+Ay4xm3qez=0BiP
z*(mJ7rX|fwg_N&K=cop;n`d}UTd&b{jo)Gv>!g<ImiL>p^7e+I)Kt#9>EC2e&drZO
z#4G(hT~F36T)Dlrvvupt313)z@!oI!ApiEzhuSuA&Qp5W;#qJ1@$Mg&M{NIWOY7u`
z-}~6dCT?DM@2>Q55A9H+wtc#F)YegtM{nmhrT#WM9CB>y#ADBxxah2xb6Y0<_uSH`
zt0tyKePrCeGyi$P2b<qoXqSC_aAELk!#2;lbkTt`x8!!+dTXs6^3y?`jkB&jYt{>k
zo|^JnUFoj>HNNGn!Qb9GZsu1GH2icx=E)n!yp=qBm*|_gmhXoKK2`Tz&$f|^Hav0L
z;`LA5`OZoIc<r4#emL<<qqZM>d(`%Q&t3RL^P3;sIdaRWA8y||>drUcx$`@7AHV9c
z&h*6XuXRk^zGMFfcm8<Ipg+yua`L2!TTkA0+_tM8+x_mC*Rq{wzIJBk#}4bwqy9AR
z&y)ZC()Uh#f5E}i-d}RC<F#`h{pGROJi7giVUKQ`oZC0)?>*Q4{H30EkNxqIgU7yh
z?V~S!>eQ`g{$$##<JbQ$u1lBv{E}nd`oiIli@x*6vZiw8&r*9XTzX6Q`tOcdyy1Ue
zd|>v=4Lv`+bK~pBY@d4dG21^^x$xDy{`tYTF4|IiX9i22_WTdG9(;W1_icLO6Eix_
z-0<7|AB=eQ@lpSs+H(AT$K7%A_Kq8`y5)s;C*5^UXUCz`mJ?oXeSFlP@_(81=bo>A
z_wfY>A9;NI!3o2&_q}?Vf8gQCxdYqpA2$Dt)1oVX{M%3e^Ri3NI&|5y<L~>)Wp!K6
z{#kfv{B3Ig_?OL+AHQ@ZTS11&-l09bBDnjM)n?&^<1Su!ZsV_#1A;X{ZN~-IEdSxC
z?3kN(MPnux(qZ7O^KSm>mT={|gELpoyyh1_7<Ovss546~$(MUZeZ&9lu!sCLAN%g0
zEt9{WSU2ghp5~4%XRaG{{K75czA^oQ`QOOiGyk+fl{4O(y62>4GaJu(cE%lz1HL$M
za_1EjCcS^ofwQhN&!6^wqVw3hW;IVf{}Y*0hh*M3>#UKtu<Nrk{MF^}*1kMw(U44d
z+(#Ox1j9D=(hv5E-s$!sS_Kc>mN&Ndix(+>@x}i;-}8&xwq^^reeas%?^QjcQeT@j
z>gJEOw61UNY<;-0?yMgqo700j{o{(A(Xf^&Tjt+6ee?Y9&fa{|BlTNOUO#u^S+_N;
z4nLb-*Luz=TTWly{iU=2>ztnSrm5!i&7<;Xw2sV-eeKip#-4TVw<o0<?mOc|wP?^U
zD)WYHSd$tuCG;mBJB{Y6W#7<ue!(ZW4KJ!xQ~L2#m>jCr*xPI{vd?S$$a`LN*LSp6
z9F(q2JYdWt3r$yf+r(w9yT&a`?1`EaCEL8^&UX8kZ{1^eJ<!qAJa}VM@)LIr-4-6x
zwAQu;erIE#Csx#?J1T0-+HSx0<Zge><h#RF-)?I;@pr$dynWk_pS)Qr-*Ni%Eq9!L
z{c~$yXe+HPc2+Ws0@J#>MYrvAkGG6%9(T*wr{*#;ooLmKtF*dn6}lI_@S{alUrf?f
zGq(<WWA09lTNWiJE^EnoiRP#IFy-lcia%P{Ufi|YnCPCQ8qj=9L$K}`y7q`+qcy1M
zcp;q7`a)PYsKaYJHW$@?_5?M0*a^|sS{j446R=iEuRXn#T6_Ahb5V45w6>ybM!le>
zs~3N<)7bCTDs{}*O5&KY7kRn0&oO7VTdb$clyum$6XSY~U#H_*URH_a3=5WCY$xF&
z9eyfm;WdW}H&T;-$k56=??j2`_3N1m8s#A(3L8s)c&YLt!_JQaW8V%X4>!u5Pde5{
z`g!Xf@acg;5N8=PXO@(F@NK%8u$3w*;5mW!Vqq6nG%d2H=?}DZ<4a#F69%-Q>EmbU
z5xvk!V|xH05|@rA;BG!WhcLRSG7guwiEuwyA4YQgj;AcO$<1ZDwRQWUenMEv>p=wn
zR`H{D_~qKdH4}+4$})s2iz_-2_Uq9ikUdS4gtCnb;8lgeFyh6P%Vr4)YX-UKOS}%U
zR@TRv8xWogT_6<f>M#W_%)$<xpCv9yoFQa*(bnajl?cnIW?BU2?O{j2aRdQ|whygC
zdeG?rNq!Npq#BBAWKYu%kHZ%@ElKtNAN)jPlx|9xeBnVjv{$Z~n2&1rHKnr!tD6!@
zRr_7Oh=1g~QcBmAo7%ccYN*lSNf+=zJttTM7gTy*tg-$M6O5eGty*5V{DDuBZp(9H
z`VyC@QoS<oCbu8lclbS-iA<C|PcKZ~@c!Z_E<OC{D}P<O`Lb;vd-seD?=9Z&!QlxX
zEZMO6(#P+7_v8-_zH{s0L)%_CX~UYY9=>hrr1uZ*UH{i@6Q14v{_TsO_|7Yn-#@f>
z{RfjbzxLQo8y0W>;I+xGE&1O1uTFaV<;Om@{<F8feCf8AmyX|Xc+%#Jmwe&H{ZIVI
z!2=&G*}maVC*OYF;bHGBd4KWZZI>>2^yP!cu0Q{=5igE=?W?j!=xe@G>(77xV=s<*
z?V57q=G?~GC|f>hOD#Q;7mXNF2$m08&acFFZK3x}w?4kEW6+k~Xhb+g&zyB}I(brY
zOWk*@9p<f2iI$>How+t_{NW1Kx79|UJ9AxW<ThiEd5H5#m)ZQhRX3DQ`ADKv)2wf)
zxjWc(S~@W!ePv^J_>Z92P#g5sd)YOmX@l3baE{ZlFRRv;7lPjIMB%OQbbbT#58mos
zJ3`U-XH)6p2j`-Oh6_Jjxa6WAJc~~nE&u)Sp{n2>b(EXe5*r+0^t4oL-&NLrHdnit
z&zXLNub`Le7qd}ojzC1yp_K;?XB}GhkQ{HS6iCmv(Q^S-tGQ6CIc#KCb-jWrTWKT&
zgBG=sCekrSHZ6Gw3v`i=sRNG*IAOzjfh~KgmoCdUdb#bR{hXzhfjQKwP*8RJ1|vhX
z%Se53m+M)Gq)}^>x2(se8k-`!FfR>R8$RzXYt@&oL@FyP_))Nj->0FoEFiJ1V3=w1
zetZ|IhI~<A5!H<qaMR8btZXzF$PwC>e7dPt=KQ`N@G3h}eTZ|}qUWg8NM4*)1{sm5
z?FiVLFVoDaD%C58ax^7;LWWapQ7x>qniFe{vb-+uTV@O|S{A|xxIIt%PZuwT6LHtz
z<VJ>+--rk=iSDfPHU(}~gp`R4<Y@*Q0$vtEEk4tkX5r6kmtN@s!vvpvDC}+Kv`KVi
z<Y3*hZA=pv>Lv~@1Y4^qSOJXsyt08EP3jgMu*)XxQpkj%6Tnf0s)9^w<m&}oxa4l7
zt^iWP3}Q&a<0H?YsKyRaULtCPY7fWLn#bd-$I>@eXfbux8P<|{77zmK#Hc#q5i11!
z6<(eP1gQglMNjJE&EJw}F0Y--77bNSDVwy?ZxYj9S8~y;3RE-|j%0S_O^{UDN3a#%
zb(S-Dp^XZT5}a1c`1Lf>?6o{|N!pgYGJ@EZYM|4|K&n|PET|@Jgh9(q1r^5GP?<>4
zrE&|cVj%MapP<UCl=S;GtUE|OvBs!2>GdIDX(35{#I_KyBt`j2gq*$M3>MiwWfw|Z
zvkaXK(I}H67{6)EC<YK^c<)8zYROa1gwk^PjoUVplN_Wtk|<|<SV)ed59<qL4*@i<
zZmB%0y{s5V)u@W>6*=@0l;lH9!s02Pt<z8p`|cnCMLK0!WeGC0ELmCBqI*&2(y#@x
z-Xv^}E@utvIt1N&Ex|{IZBlF%h~wR|2u9-vtd!bCbh%(1uWuCgLp0kLG9oO^8ZCyz
zz69#9jt;Y9@QR^GGpC}AZBu%keAT2$+ec+&mXsA5o&ovcVDOd<Oa)I;{IfRwO{YF9
z07Q}{*i@c)9!fbpPS!31%8oQ*(6NJZS_Q_T<@aK$`x{h78AB-RHR(65j!C6yj2Xuc
zD~l)KqGpJV?LDHIY@W6yPvRT|)%SLWCH9uNhRSJ$LE_+zsESl6SBfgK4dDewV%z{B
zv3<;5Ir+y_l+{Y*D$Ry;c+~gmX)}g$A<V~tOo&7p4GY2SGQ?*rgf7oAKhf;f@j@;2
zvxv>9eoAE|fd*<*0H>#XWldTtw(>MTj_bCoIz^@Pkz;8f!<+^J2VD`BlDUy+FJ_Y>
zz`}(3kcDVad``({bB05*;cX@g2)s;@NQ2kz5>5+YXp-(cvO#-6YsC+wMf6G5B8a_h
zp}`RzBTKy{7%9c5Xf0@E@+$ac(Cz&n%H9V|uA<8Su6yUs&@&EjXBcqEW@F7Th9PF%
z0b>>sLrv4fA%@t*7$UN<i4h_jP1L-A8e>h<gdy^>O^lKsy4Z$@@y}`&*ysvEGa!WU
z$A~N<C<M&LfDy7W8wiB(`+V#61lZl@d7t;p-1>9s)TvXas!r9dTlcm(DNf@ON+Lf$
z$ZZnLBrMVnXe3Oj?y83QBR?{jVh)VEGUcSpac15qd9Z#FtQJ7ZST+tzTx)7Jy()Q)
zGxumKCGFE-%|+<gvkv!DkbO#Rq)Mlw?_m8ptn2AFRFyLlnxJxSB;UfG36qD7=ajpx
zt9LSV*)^529M;34&$S(C;>a)kUBIQ*Q!?L$)hlK>H()TUG%bt)ixp;_S|_Ml^%Oa+
zBXVOm=XDgRnV@mejFDupW|F>K)x}Pzz(0J)Y5LQ|B8cqa<aMS@YOcRz2lAXdYG-c@
z!7$7&i8X~Fdky|{u+=eq28-BGM-OD?sA-Q*&E3+HTr@~xLc7F?VQ?mG!^GRum{W3a
za3#-gaSglCwtQkHMUo{x&ZKMM9uM&*ME6J!3iNT^nZhJL<lNy=Iy3+W7P2~S!Kt&{
zn$6K*8W-)t$XHs*b6Nq;oiulnl=$&YA6Gi)zInFzJhro$8YWKi@krH-P~-y^`-^n(
zMmEO^iOgZnY&Z@Y9x5Spc#DwJ8&R_<m5EyyJGwCE%C@xiDILuVbjIYp%L#yNeEAQB
zF?>`u;DSR-18wR}vO1=zmyqnD0I7N*?9t;8n4ovbB2x5FwpIj+IZ{M#%7o=xc;Gb*
zNSkq<m~$?$q_fjEi4YZs2#*}zcj_L5pG_B<Dh0IFoF;JeYM-&y_&~LxtdPH*Io}SN
z7&78-0tT4kwkgQq-;~BPjF8+9mY%D$?p!RrCFc<i0^nDT3O>Y~LF8g^LI8;=C>@JV
z(fa37bpTfnwTMFnC#EWbArT<<;+X;cENNEOB+NHKAq68Tl<wseJYJl5SBtxBFT#2i
z&(<}wQi})zsZ(t%F&7YoLKTomGL;;eVx<KLOCvaN{|D=^<qJNDniee~TW;hhg8DRu
zf`Nk?!t9AZ2uIwioJ2BgR30nj7(krGq}Lzbq*y4#M--jO-SEcr&2BIC1H?8|2nNF}
z0MYS?^5<$HRh0sQ7y56MYsZ|>O$~Mj9;Aq88reAXTA!65^B90}iBI$ROe9uJ*gdVl
zP?O6T7bJ>M^2H?zZ#59tm;)zD@3{@Pfx8L^;FQa?=6#452f{Y$YLzKYM<BF8yt-%-
z)ytW{Fc2aOQ6SMdoZp^82(|enjMs`t0ZQ~6@Dr8o3FvZZT!U89G|EiPfJtgG2sD_;
zGvPI}pg9$+`jx<Ya`fX<Cy@p4xJ)J?EVq#<#8sZnLLp$sQsZsi4t(f%aMIi+kO&TT
zt>H(4)U@;|TV`Z5z>CBxqSa{z4ljZUDaA(d;-jDozMM>4S-wcjVC?W3JVMV5`V+49
z-a|q|n)2{PSRmoInAYKkc{5;w<H4}1Nb!-Lo|JLbGsYldL(Vb0sEkEYF#_lqX>XZ;
z8xu#^02aoW+E8hTgKceCJF8kCQ9o4)bz_Rs@;gAo%OZ#oppNS)vmZYc%u?487TDm1
zrO_CVAdC-q4Fj*djf~c`z$BC^oR>3J<RPrlc`mhU%r(@=nNg}9lsSo%rF`cBX|gp0
zHS`iz={ER5P!>Qy-(;T5Myy8%Jn=BH0$yoj0NYT$4MV$8s~9GjvBAXSaU?^;9J8Sy
zf-V!>g~>Hbp#ubpP$R7&1hkj4*yJ$Th=t>#){#aAdJ9cmO)>rb!h8PHTotk;*JXu4
z3Va8#E>B2YJP}Q%MPeR#p$h!K0_~==B&vS#)0H!4il8;DjXZdW`3I!SzH{EtC;^LD
zVM%9ND9;&h1D2Y@%w;VTFd<)2MIjs0g@g!UD>pH5Uj7)wMwuHVgq%e`pfa<W4FhO%
zrYt&_5Oxq`?1^|TKton_w}BU~hXrN#6BH;}Za(;#L!s8`CaVEO4KkH&8|2`RQ(S;+
z<<TfHd?|n!6NNlt7B4_nlT5sRFw*5e9o<L_Xb?W@k^x)C)tDHAC~&AL>H@u2Fn}r{
zlVC%UL<nR=-E=eMi@|8xqzr1Sl0si{#?f}dS*}dD0pj*`yNA(+Lr_!Vg7pfM9OMn)
zjy4OCFR;qQh>#$|JE2hzs#keHaI!f>2_95ta9k*dtSnKufFwvZ5VDMh;;qmb*l=%+
z3;dPVO4+>PL!M9_tE8Z7a1pJP7+DMYKu<kXxMHjY(U4pUVsaV-4@uhLD<hdKFd*GT
zp8Ajkq^6Vw2$MqGIXob%&+Dw(q;aPdEv~HsK&Ej5K2~<7Kjokp>ri{(M@+alWFDjU
zp)^szLQ1DiJg?m-J!7P#K{+6*t*jRyb3_K%IunKFs5(<w$|^>5aa-1QkTISmK_gB}
z^pY-syUpng$t_FA;`lxk8K?=evNsf@^HxD_@WMz)7mGpc0>0=$0(lbpv!Dp|>WgSq
z5zTi2veTzLNDD|S*_9INAyg}u<7x}O^W+a8ydaBL@Ev2Cn|rF~JPB4sS^@@4BcuQz
zeOh59b7Scc<Wfd(4zY&@Lsdcxw1Cw8N`WloaFGo(CNMUxL&ik%Wx(P{dhB`E7{W9o
zX3~g_WLZPhhpI};p6y2mh0WZCZa{GB=gk5NYQZX&$ki3*maI~a{K{b=jKwBXYJ!9Y
z(l<iT=Wv?YQYDP4hlJYlXp;c>#Q~0LLjr)eE>o|<^gx@@D~Y(5M{~I_FeQopOCY5W
zLF91~A9!oxB!(vNk`M~?rpIPw>y$6dxFBG*jbeu_8&PMY+hFUnKF){Fl2`%@q~`~+
zcl|@02_bE=62nUsJ|J<jl0#pS1*m2CfF&CIDy2K+Y(TN$H?oQ<=;BaZCuaapwt)t%
zah4F~)yfB8&VNo;SFtE~>@W<2q(^uyD}07@F>*BsT<pZV!FDJsIOAb*BN;ue)`@^c
zaW0ILAw?sbSjh&ze)uu<!poDu(@k7~{BMVl*SZQDdXh2sTnnqLEj)r%or+2geOF=l
zur<S@lM!Rhl-MOhD6-pZHNDlc*@?CXs(M>$jj3)NiTg}iol}fB5z}QJQB6Em!PYFL
zQHFZs++^WQ*H9-e-639t?_7!5LO+RQu^A<{x{8u5Ez_~MbB*Si9wy#u^n}l)?UqF?
ziXFh>m7(Vad}N0S<#{uSW3dBtAl{KRMLcQDr|Wsr;YfW)l+SHT3~vOcN9TPQM{!rb
z)!FbO3|jDmUR?=k&>1o&(n~uskBj&f*@z#`V*`qD$OegYSq%-<Z+Uj8%+%rV>7yD5
zQeE0olYO2ulxvCYN)SQU=)pOsyMD{(t4*z|%F`rc%Ed)(JIi2`Vk*0MQq@sX6;`R6
z&JWVg>GyC<(}h%j9`r00<NhiPxVxdbP3r&#0|M2q-$bEru?tT3V0RNI`Zmfh>H%(7
zI?mKfb!M_-eaQ^EF7tiZ>ETv8wLvm>Z12L<kMMlCgdilnBcdNL-tY5Tl^4xrVA&Kj
z!@^dn4|V6`2&Ts;<PV!V;0E}5y-9nECON&I0fdl|6m^C<19qmpwbw+>F)(}-=jIH#
zCPU(YnRBcuzSZ_8bIfG!<9I)ix;I(+4x=Wbx!o6*&%3m~xh4E|-KxJ~ukV)Sm+q*a
z+qAX5G9Ebfyi4btI{wT1wr#oW;kzC$pSy4T;_JJnjC<H_8-3>dC+<oooH8wWSNAD<
zN>4w%`~03e{W%j(8Gqb_wu8HiJ$rWdd^|nluaBvII(gfQON*cV+3uyK>JN?_=dU>O
zh|>-%U;64x#bWi|!;Y-2TyvydKJO!+x^(yHcb8WlIeJ%f%Z6K)pZwmX-OKOYcKKmT
zIxlPLp4xTlsZ*A{=Y~Cn<6rvW{M!e9IRAjo5S@d)dUX4=k3PD0+Wx%<9zSLGfyb}g
z_rQ}s<~nfwzdrf=lmGG1f`|GZxo%6}BWw38*}r_>lKu1deSH5n_I&QyZ|uI{w3qi@
zaN1-0{xItVu6OMF#Hp9;`$XSoUcR8vcl!l%j(Fz>zWm;4f4XGS?Mp6Mdg}|Hn7@C?
zIUjq8>pRaqFz52;ei!}oa~B->!<R44{prQekK>xVf8#&B^VN<2G;PI{Yv0H9nd|pW
z`MYoIn{qDlF5JC+ey8O9`4?Fe^i6wq-}Vds;Xe*MdDHF#5A|+(;K>tr?0WRVCojBb
z-S58p<V9EY?cIEC-`=)8OJ2EX-;!4r@B7fR=kEFV{_9G|pLXW5<4=3`;2);<KmUih
z{rmpo?Ztg>f8XqvXU)0r;5!SSK-S(LeeuhaZvWG#=KpNT7t>dloYT4Jh4+v9&U1Gs
z-+BH4^XKRGweNav-x1Hf`1y<fbjhdUS2q6Bq}O);(>uR7_1e#`n0oCA*YB8e(XBg{
zPX6ikNk68`eNktJe#f=@yrI>5lcCPNKWx2i>8{rH3$|bX>503qUNLLy{O`@H%s+qr
z&Y5SA+c5K2C)KxJGqJMyjC*=}dPf)ZOsa2tc%ZUvwDx4w{mJXk&z;{lIREVn&HQ(-
z&QDFtr%xNQ$Blp2!sFVTet1D~=-C}^=CgMn`I(otz3tfjGj_at<odnuuJwK9?DY#j
z)A9ZP9AEs0ZR5M1-8uct{X6HrRdVG|rQM6~yQF;f`+Al=(3)&~pw+*${kY?h`-TZy
zXZ3VfW_@q><e{5(EF3!NBnIcyWb28@{n?9mue{N1+hUS!kEb&iA@`y}M_)Am-OJ4U
zp1HjzzBm8b6W=v(T=Jo1$8~-5p(xjLb(A~dlY0+4@#OkpJ)_S|99;eJi5<1l`5#%|
zcYgN|R~8F9FL3VJm!==Jf9I^h{ag0h4Kuc#`1sQIo$!^<{LRdF{O9<|f7&*FXy7or
zo$)zM=ZfC_3u6xaJ{j#?7>_G2Y`d;@n62Ju_Dt?>G1s-OG;cd_R^L|>m+m^d@0eK~
zeJv|CnLUs6ocZCq;}31TG(LUfP{npHO2-eZP1>T9lSv)jJ)ivh?xvDGx@XjX<lALG
z!V4GeHo4*&w{oDvthDovv-UB!rudT~Q~0+}+QP4L$rZo-Oq#ZC`+9MB=Z(dWlq&9N
zWSb+|^3#p^{D3*U+}E~pbzj_7JB;PQVRlYyi&>dlX)fD!crtw8!M@dJ_f7ahN8b^1
zkozj+OXJgjIuxJ2p|esnyOUCGd9td*Cf|=viCRBgGp!#UvUz{FE%VD@{kGOM+4j2@
zy9n7Xnq=*aHal?TpebNBr$1+tYd4$Zip@J)in(nqMdPY-(o(fxbf)R5Zy9rTYL58G
zfVQG@>oB9`qTv}x33KU9Ep>YSWrnyc26hVRdzhcBaoXWbE6l&N0a*TlZf|pI@kdC%
z6siiBEbUeZ&i5{-b?=!`#b_P#7<`IWXNHV%ku!B`jhB7qn#crE;J#oj^F#uQY+)@>
z)tRTWe^0EE7NOfl2+)?SvV}EMEe&_vl*-W#&|66yQ8+e~C`m1IOB(-_?>HeB;Vj=a
z{3@5{>f>6(RpYW;WDRK!zX%J83t)rGc~=mUlf^-}ujy8ptNzGpCfp`Mk$2%vL-)XJ
zwZXMs+#1SC;O4=VX#nGU&^Vsg@3y9~!W5?_Fy#WTucBXt*Fk?7s}jq%0Agtu$Okv=
zb}@?;2agdB*&=ns4}6iN7pUax?dLeLRmE~MDKc?+|9<eQWBBd5=k6j<F^4JsX0Yy!
z@uD-^<AsvPI#*{I&I~_0PD**>z-T*>XL->ngE9Ak>9!nVrJQ++63UFai)PSrD#2B%
z#o<y~=-OcZT4$Qxez!_UC&$V76Mp@|w4<Nsdt&#BJ@@H5Pp7W_^G*Noz>aV2Ie62V
z2QU8Zt|hA%zkKuW{`ka8&#(UdicR|$|Kw-OU;g7`7yS06y*KmSr{A9X);ktI{Hy&J
z??15jFAsis)1Nne?$+(U`O8@ce|up2&5Kvu{OsQywSW7ypLyZp2UqkxwS3xNo}Kt!
z;$Qglp8LN1&es-CyXo1fC+y$*+7}k@dvL{fUt9RL+kZdpJ@-xh*8VT;`}^1acK_ZZ
zZ+&g*d#Lw-&JZm}t+$@Fsr9pITdzxsW-hDH*&Dbe7#U|--j*t!#<AM`>Q1Xy6>Q~h
zZ_3-)6STRb1~@{#nvWJdd}nv`FC`P7Xx|g33)kkWgPY@?o}BSEwId~NT=OnoSBQ+=
zo^<xtY_IvlHnVD*Y3sF|mCUnhoxw-mw(~nG)x`ACbFSJP^|o&8FipFYwiD96rW5*{
zMX%wv_WtW5wEZpG7z|)T4<|^M$Y3mmaY;84E|HVDN$5l&{y!XkV@<gD4GCFJiq4RM
zwN>AHy%3esC`SQkmDUyH(HWDE-5RhUc_rT?1p~$9qCS)JO<L5MrkYOu2o|pIPMo8U
z_429EAWP2FN8=7Ud7IbJwUXyDbKFvI`g<cw(J}I(G~OGdiGX;HI~&jQ5x)Ey%Jc=+
zdZaj?unFq=Na?nSI27yC2C(BGmGehAdV^{9>@F-cP1dvDvDM^}P0L?Qu4i#P&I~Fp
z)`h1>oYQ!xcr?Q}cBZ(B#QyN~s1yzGT7Yln<26ZaQPmLl75V<$sn{2%Z_Ke!j?z}W
zh|HDKF9-Qy^Ih<OOH6v4Bs=vUVhC8^lnS;~*|O3>O0N<`0`R#kR^dvff9W1xhmDS|
zrFn2H$zza}g=(_c#N(hk-%4i$24p&mTmVaBAwlzUv^5SJlUSZ1!5IlS5CbbHMvgj*
zI~Vmmc6pQyVH3+sDiE7EcDS%ILwWqf8H)B2)1iAXWI^tF3HCgogoc|r{aQH8;V5d|
zan;m8V(7V*ltD&EiRE}iX0;RdTym5+b(`T{64w~xLrY-9j62p!DnT?*;I&zAjhQt<
z6n6D?lSpsR3=%JJwQ_mGF;sjT^@q+C6Lv^cqKK%7Kw{rjC|gfLw<f+iyp76|K3v5N
zT5>1!M|{-gO#qi0vJ8K3lZ8AVr*POw!Rn9n7%;ZeIb2xL`r%YzcNaA_iTQ-{6k(c7
zv!_K9WUGPq2HRu}Acf)Z*up_Q=)w1RwFuxSB5<WJXF55j$NZghCS@wstx?p3Z%Us2
z9KJ=tdoxx?(l{MJ3G_wI7zE(-3iLb_u$0wgq7HMho`GZ#BOV9w)cQj3L&AGt+U|WL
zSy+WBFLL<9=nh$P@rXZ$G^d(#z`@x5f~V7YPxm3c3E^`tjvWUEj71qkz1}c{sG1KQ
zm0r<~Ku$cOw(wgPp|Y1ID$kph6sVcjbKs7aa$!Kg0eXpazBak6k9ntu0gi$>s|fFy
zvco`N0^_KdHJo(u!a-x@z}Y(Kv2BEiW0d#eD}mw?Tohc_AaRz$Lbj3E6&NvC2Hv?L
zSDbyDsAQt)4h>s!Ifj=pUiqCVn{XcInR~&27|7!QmcOt%vL>w)4h4hf^t7sElM&s9
z(+muC2R;v7now@h$3%6VO}3)!F_AF9hoXAblORYmTBRD@HTy&d_k#d%S81ltOFY2J
ziO9!+FKDV%%&fPBuw4p^_m#Gd{OS{NqFUIl@N34|_I|E50%ge?M`4*{BmC@FWWH%4
z$q}B-N)lr#!Oa}UfmHq`6H{e8wGKq=o0G4HoR0Dm^26ZrxJ!LSQ1)gz{Y;$)uvSmE
zSR$*RzW;tO8!T+}Al~!f88(;@j-b(5QFE`MsVU02&LWST6Hj}jNwJVriwNqgoB*3K
za12A5Y>8{K>&#~f@@krCGZo5<qoRv)57S}LOcYsf@-6fQYupI(O2_o$gmpt9SMut9
z=xfBP9%Y0q=5w@3)p)zsn#yr>M>oXS>{Ai7{3>*8N+nAk)xh+0*AXJ#NbBb!>9P1b
zo3@pm_ZlU9S@r~KAA2Yn8oqsy_Q@GHyH-J-B08i*%6AsgH$X(^CCttmLFY|jV7%rd
zgzUxa#~P*yJy}`M*nmkFj9SMwoj2(^H&W3(MfTfu%RWV*B^Phw!)9H^vC=Z+Rio);
zwF)JedY7lM(75p&bv>5FQk4!JRY>ejsj(@Tub9?$taMa2=OW{zk(fha?FqxFg-V^7
zF2X{`uA~Q$rt@-4%pg?e7j`A7mopyD#>70`QR72b6c@MJsE;QXJqW{eVzD1Z#}l6>
zwy8MHLMPo^?d6w>9n&#2_BJlvRcT6-PScE52F##oE%z8p-P_bV7*?3wLRvr(olUD8
zrZCr*M=utV$iuQ|sfpM5u4-Mj)J!Z`orZSlP|c0RBlh#ZrTLsGw5^V5ytu__45AFd
zss+Kz9GiJQ$!>OFMF<7)Zz(B2(&{vnX*TtLke!k6P7z{pWZ~?wR<b6MXBs4p@2-XH
zuw(uT#AS^oJ`DjE{nnkpsUP_e9CKh26Xxo{6AxIU3FA{QW1|!XR0km^bg&tO2wGgo
z`7BEa1czloVq+V^b<`IE!BHuI>XZRxX%W$?)6tSjw?!(B!KQ%p_NfOH>QzaS%<&{%
z`LWTI$~4U9xu`k~FScNy!wf3FkD#I6CSkz_O@(X$EN&7)J|>UL)8okA>LqJ|GJ=58
zQ-C^Ml;m8GFix|NplTWGWT%tkx<o(I43NiRMy-kKio!5<_&^*Nz3OK0B5MM8;~DRT
zDOn6VV(6>n36SGH4t6P~K_%of?6INz1i~ziOC-ky#2ig#6{^V8pBhfnc$uxpB4v=p
zn*h?Qf({S;(C>(-b~O;Z2+*FCK){$Gtzu&?OSuDHHHHwCQ)UDc>Bw_AgV@$2pm7)`
z!o@XV;}EeJsOyl%20<8D&AfFRI8)Aas7nd7@NkkSH11mz_mRaFRI*92oBa@#*8l|2
zAdqW?^%Rd)6Nc9pv>w-_0`TodO9??j^E6XIXlK5L8IwHdLPp5=c`n=@E@SGL0V>>p
zD4covw;QB^On^{`DGp==8Kuo46l1oE%7wU>yM{|=gB5NflSdV=vv0MHM#Mbn+dm_Q
zG|OM0Z>Y+VRlOm`v{N<4H?)kLs13qHK%HC6sPh4#KF|PhvUEVaG8etsc$jGsr*#f=
zsdFaan1KXvGEikAfC~XD$(hHLrc^;}F*yx7txHsfqRbO8p%4IO^iG$>bf)Rsj|FsK
z8j&99=SVYfR>bO)1o~BoHw-%QuxosXz@AmBA%`{5WGK2TdWJ#o3k)gS(*?;T2xq(T
zz30UX!=T`e7Un=>@>(pY{<xL^;3Tx-0Oc7^&FI9Qz6sWb&QE6~qa&YJr2xq)4y@BD
zO_U*Xgh}c2A_%ESn-v%k!Q4nBM-jN4v??7{VS1mFi$mLF{UlaYg*n~dDGA6W=P}OG
zTmF_X-JYX2p3v%&Bx=AUGOA$Xx%8a}8p{%NT=X_CuR#%f*U0JMkz>0HAMjbxgqCVr
z5&LRLptG8eB0(!AbRlagP|)CGv4|NH@X}Vq9~1YOEhU}*0OT(b@zhJaf{cNgRj|QN
z$tVn)%YrUsYa~=nyf7x!i&8@$*`1iTil6>j2^jbZ3%rFIIJ$1^NVFyc%t;=CklUK1
z3|7^xhSXHLY|&ePDj1pu@XM#R5rjaX{-7ER2YJZfkkN+J*Bx0eaB5M`i@(khRQMBy
zNnRPk&Z7b<n;F65raV!j2a5;YM;OLY8Y-ynjR?^QvLjtElXb|HDacN(0+6v0(A43A
zg=k0{)*E1qNMMU$@q{=#2Z8wG2~p;vgj~Dr4%4OZj?z6yW<$|=Tp(8)vvc7r-Z$P!
z`;glz&C6ll;wmsjWO01JsVa~~iU7H&4|+Gq9gHXHU06608Uu!)8w(pAQ+jjw>rrkV
zgK0u8uQ`b^XMNTkLniB?jYXe_FzCVsv4zu}s#988lN+EcO!l>~Tpf&LWh6A3Ge&LL
zoB@#N15%lokS5m72^}g%%jHS-s4G6x1XP~Hj9&-@2E`Cm-lB<v?w$H&`tJ=A7iwp%
z^9=+Xm62fpz}DjF${-Gc`7F}#)F_fLL{lFqK-fwnU7fq_O>#+Bns1#6;3a*o$HiDl
zRnN+6BIGn<ZM1=oE-H&Ef&_(oltH)w*-bVPubKj`QJ(F<&;<xORLI*#8f?PMDI_=;
zOHAWMX}MyRPuxUaZUB2I#7gtzjOW{5B1u8*{R8mTJZ2Tv8ImE5s|*r7P5_{eLO|5c
zN45r%`UwVuJLWXVLP^{KIWpL+v|&ilax|ugx@t|?8L(l}tB{YR!){1pVwxkJ(Ab5{
zx85TwVGk1Uk_`;h3cydEv#10VQ9yl8t_z0H5*h=nUs>T`kHM2Afan?4dbti%d}y;N
zvnHYnbE0#Bn#T-?)ClLGaY2vAzoJwG^k+0A$tS{CT1Y;O8D>FKF4*CWN}PL1jHr8T
z!jL1x(GFavi=VfTV=>l0m;%HZI7eP|2UsW9S=ifRLU2fNz?nYMoC+^H<2|S}8$5H^
z-y)WQcP5rDJ<*QPPh3!v;(+r(L5^UI0bs@>Sr9u^<0!Q$^m(CF7;wl;8q+7yxySWP
zPy*!*dI&Kbj@EdxMI|AY{+jzqPk@1$Q4O;Nq?D|`LMqTLZohRQ95fkf44v-gq3OhI
z$`5=DnkAI=V6axjN#_|PB?c2g8?qBnr!<G!n4s5;5%LfLtYqtTHbms)%{VlmT%|+0
zA4?=Np!XwlW^Ll*F}w<iC{j@4>gev%IB<qN+AtonH<`(8k>9$YI1wXH5Mic*DpR6b
ze%e7n$i+i((S_tjAt5ZZ&OCkc9T`oby@v_aX;r_rz`Lt9;kSaS@afX+@lvLhS~pKj
zwcgsy<jbmOc(7DuQX44t40%5+e&$p*GrE$~N$xJt7vOhyVG1vH@%nh(lpYcZL;3?Q
z$7*|I6&n}qs2`g;kD&Qp)(ZSSPWM2YDUE2OgPSgtl^bANpd8=LnlLw%jwJm>#4nq4
zqlq3c4^zhzc@p9`uN^QESRQN?c{QsX#)I!%YZf7Yi)Az}o-sI6k64Oqp-tRux(C8o
zu1hy<3p&G^S@U|qRnalagML>-n@w{a{hIuyIIlcpO{t*G-~P@GY3GRSGOsblbUP%M
zF86azq!Z2CE&K*Wx=M$3SfBO4j+zaSP;`ri5;I(*i}kPdhH8&kHpOz4y0O=|GrBtJ
zBioEQ-J2eAL{~cJZX&(i^~bGLaxxs8_CHX-8HJob%(UjmDMpVvdM0h<d^+9aN+W#3
z{BEDd6%}B8d(xYG3;R4nNqY?)$EAl$s|H)l#t~(8Q*!3fmA&4K<DGh!uF0Kj(13~V
z=FP|aO#P6O@8V%my`HZ16J4<wqYL!0_NqcBb~3Fyx7lp&kB`%Y8u!7_Y;}%t&}DH4
zs6fHzxGx!;$7^*7D$iTWbY^%$(dB5#5&EZf{q+-)sa|8o<k97+c9nDAJ)Xv>7RUF_
zFmUqbz%A#^Te0{2{oC%o_b{EwIeFTgnJ?Wk=gjS+qgT``S6p%O`1xInZks%QTkV<h
zwjHA@Cx7ee3Fn=>V*IkFcaHAbHaeR7!Lbwi+uPoGNo`Ag_jg7|w_Q1N+|c*FIeynm
zyWOR`?{wSCZAaWaW5$FPFK;crv>V)I&$o??u4-Sg^s#{@k8dtM`S2AjJOA<OBTo6<
zqV5$B?@agI^>oXE(eJjLeD1RTY4e6ozLDpM7e0K~VW(WT_`tH_rI#L9|HRu4tiN~3
z()E8lD0z48e00WR&s=-&?{-}KOVXZtY1aeOcaFTUW#>0vcyj0B-^|#1`$IDqKl{{l
zuK5Rc{eJG!e|YTNFWh$jLo05%|M>$ynl=8?XAgX6+q1jU?N9F-f8L)SoB#Z|cb$9i
znJ3)A1&_~KzW>#ao-(-P+?SvE^}s889-e&vjQb}XxbBxL4&MKK$~AY|WfzWn^w<A3
zZpGt&X`A)<A3nYJx`!qni?UZdw&aT|9(&<kq)oiE@2QVnT-vd0>-H;7m%M8aUOQvn
zzON6TdcmWY-M0RzuRgZxTeCM`_0SPJ`>$TL^Pxv)%=_E3(o65Ve!}u+_s!nB>w!lv
zJ^fb`#;xD7<I6wXGHcn7A57Oi`}1>acYdjR*R!t{m!JMv@kd*><PUZ}KJ(z_Z@8D9
zy(ORj^~(Iq&&)pWl?6}Cdtqox+m0>2T(s}~FSI;*?+e9gr_YLa{QACy7eDr!cV2wm
zix(ZZ?x9Kl)^E%gH~;wX^Uhsz=E|>rZ{A4qfn#R2{DFsUH{7bTMZ0Ui9DHfuiq_>*
zZanKi*9ShjVY?ZvJ@bo}+Pce+@qNFXKKX|aZP}H4y5*(qOSbIZ?(SK-?IH8{r>Dn1
zy6E1v$vdx~KlHugxJB=}tGKxL&f?74)$zKE&YJ%H&99#OT<O*Eix<rsw>)3&+;`EI
z;tk)wzw5H^7v?|tmWPhG;D%?Wudsiba9(-Uxlca+bnn#sgS~Uh4|YAY<(}!hLeVL?
z)_s)s@xHQq>Zt=OTYsK@AUU)0fishp$KAZU_wsn4@1ZDN|I6toCp%hi+kQmnEei)b
zH!qAj>pL!w-}!~<Eq#mrarMyTr;gc>d~n?2-Yu?BdoVqD`~N#`+>BqgJnwE}P4JO%
zx#(Bp7TvJf{bACU+z%!-cRsYUy_2+LZg06|S=^K_mcKIYxy|>_ym<Bl3!cpX@}ej2
zy4TKn`u^#kWb}Xk%B^izJ@%j1PtQN_$fB#Ry2iCXxZW7^O`R+1+Awen8y4GrYkk+Y
zR@XgpRntu0p6}~wKB{|Q_;cMuxnC`DX6wOouk8B!Q-*Ju*I$cgrLkMkUrsmWYU!VQ
z7i_({Yg_f6n}+92-#C2H6{XFs_b}#LPWJT)mzvG1rqoZ^QrOymPhoSty>FF&pm+Aj
zcwT9LU}2h0pSU`Gynn{3nYnz~wY!hTx%{{ZrI81)OQs^(=KTuuXa@#rR}OZ$EAPB!
zDEFYPPj33@(&5=_i&5v~E<a$q%{6Ct4o}%Sb$Cruzb!wIt2Irq1I#Ov(hu>ZboMds
zSF6?yTfR>+z;9cfKGnHsO*aN~Ufs7$8NFszI}b0gMOzoPdA_Y+j_FJXXBMkzq1c%w
z%c^#Iw<~w|cg~*Io{nqjOwYUu6Sa2Es4;)@BKJ+MJR4bebFo*;+|Kjh#D_WQD$HMZ
ziSH5SDiQPc;9Vv+ShwEy51GOBtbKMue|Nu${@t3l6in^RGT(?8%K4s8SQ8!7#g|4*
z%^kryt4`dJf0hYrmf^(tJMXsnVV=sccV=2=EWo#Z@F7kM6sDVKo5|<q@{V!dI#!)=
zE21H$k5Zj^>VBUr?BEEt_+)1EjVA1l>YGauI*)2e)a<>^o|@=)@Lx&Z4O~pbgC%gw
z5<V@Gf&iEwjFV9(+!Y(1D43`c*>El=bvlogbU+$)kv^083{W`4%S2g#MeW=V9Inr2
z2q<I@9>-rp)I74<n17i7BK1tR7A;s3psFU^#9NU3!!Xz79RASIiD0@_qgb7$9=PiJ
zF~)krv`Xqdgl4Ui*JnD*o<&NWQw#yQGjl59IQG>kvS`-uxq#FShBBdmE3+1{PEjLB
zJQ8L&p#}QR(~5yC{6^Q+epPv6e4C3tQul89MHPM$jJ=R$HJ4x1hbmVlrFvzs+P{|D
zB5RJZ(E``*om)7<#}esM^$o4<&X;?}CH<wz`JB1bdz;JqK6u}zGf)5NsOgBAIq}u)
zcN~1-#jm}z{)zuuyyuC7EB0UVlYO81%L@<O_|)FzH{Ew|+N+<q;`&{G`OVHBKe2!D
z>JNT-#eGZ8dHKN2SM0p;l>>`!{pFWm{?n4fUfcESd(T?&%E4VXe{kBt`(Jp+E6;!R
zH($E_w+9#h<<Bejec-iYU)k}OFMavq`&UeR;!6|uJ#`21C%*8dpWXN63!Yjs;U`bM
zcJ^x*-}(j4Tdla{iBEm(H&5;P=>APlePQ{__pP|#iCrJ7t>@X9sn&GnsYnl7zkbjx
z^B?ky<2!wS-(XZiL5phcggJh5y|RAzZgY=`cpwm+YCcvxnV*!~<t<Mh`;(=UKg^fX
zeqk0Znh`&H!nv%829xvr`^`JcSDKfe$(f(7E6<s??k<<)?=&~%uk1d#p5{(o<;<+M
zyG-ZMneDqvjL&$1nOy#=o4R$_e0Futtl;$AvU6t?OQToDrQ+fdn=VGH0vFCa{b7&7
zh%bnu&=FjS;KXBr|HY@<hB45{dWgFGCR*-Csq6m+%KzWNs#CLV@j6c^oEhXk$-_ry
zOeWDUfJt>0vv#xI8e)JLXZzHX+tZHz&LNLrtn<$7iFwdA@Bqm}9emJ21?F<kSTSc2
z4?U|mC+T!+!ZD&jmgsIo%7|Lxer~4w`(sM8&gw}ftpRD$=EigKhfqzM!tH*5Q4=`Y
zRbGtc)J%;7GJ~Lb^m>Z(1Q_k`?KzKBW2X4Xdc%(tGH@vzh&owsTi2O71nc@wQ<@#G
zVmpQ<FUFPSbYv`4X@#P=d+FCMgSUmaPJg2iB9ZYB6ihlVUga#GI?(>4;|PI3di$FX
z6UPv7*HZ515M?qmG(c429)UZE4r^Rpv~}YK&B;EoiU8I`xH&yY%o*=a2+w08<|0Q`
z>oQ~}SLFsjaD#~hk@V;CHLRA8ni9jWoFqXwX@h^6U<(bO7LiIw4;rW#6mGc%S;d|_
zI`u*H&=ow{TvTz&R_KV%ZzF?qymCSA78uYCQ|zqI4S30F;t~Y8`b>f@Ph(0itlwjv
zEcap@!E%LegvF-@v6-b!@gRofbszBnQfoaMC4>ggbaC3mVOejL;GFUDt@Qf+tqLaP
zJ`+z497xBS=artc_tVQLna}@<>udx@!2q|yCw$wKxoaq)VDiPrkC;HjBcCQOG(t)T
z8xsdhV=XlN=S;-}sYz{ex)E$I;5g<g4`Fq{wVNT4B0Qk#a);-Q_jFo2Bo;NW+y(<R
z(gyjgvFRLCEOeqgAwBJZ!;oC!{jn=}Z#vO4+#-;irKC^l^%hfw&>C*(IK@y`StOeg
zNP4;5HrAO9Mda0&i0F?@tOMwbRls*H6&;YG6zkc!QY4ncaStHy!HYwT?^!hvbdAt&
zh*~|Hr-HiCucMW|K4k>fc;iBV8PG?jBS(jyBe`kKBVwdS^t6gnR16gfP^I+PRJ?vt
zj)dWWMBxe5z@|rZ7OR97(~MG(s)f-$z}Q6`dKq4Bxa34@aU+NWfENXqkHKw5ZpUAy
z$Id3Iu7?Eya>WQ500tI%1$~e4KAM4QyuOuG7Ea(z>?($8(*-;%<CwNkH|Atv(r)VD
zQtA1@Uy>O9jsFfpMd+L51a;~G+s=fmYzcp+%yNOS6*YQ23Q2)Mn%Gvj=@#Uw#y7b<
z3aS#LM`aJC8My9rB=I4ul~D@qQrDJ?wme)&Og6+QBk^t8BZ8Jf+0%$j%&$jjd}jS$
zU8oi5vtu|Ks1-1#PXEpg6q8<usBuF6nu!=d6a+%tEb_$0=9mn+dK`$zYh{BUPnTyc
zlx>SqS22#fHADwUR1&$GgNF*(1MvzYLfZyoYgvE&>(v2;V@<9ru@&Pzk?FKUm6?QJ
zJPR^V)3^>#L@trs3wNzU6POWA5|0b?8b0S#Pm(4_gl$D?LG@dxfsZbCMVc~6hX*`Q
zNs1^S(IDFjB@hkvbkOll#UoHv6*d?gib2sV4K-yL&ps4jx#HMjO4GO{iJhl^`!sjw
ziPPJ=5Wy8Yd}LcYE^=lt5SNC@kPLTtd2|m}9i}f&i#xt+ZQ(*KBDmM$*~as3mzgmo
z62jU(eYU}p4TxH5SUNIU1K(la9kVDWJc6a_V(r}o4eVnHx`E8Z?(UGw`KAl_Ml*HR
zGPEW;!$wzI-x2AQ!z>@Vl_l8V$;IQlL0rqN1TkJY+-56h=gZEd#n>^%(=Hn|Thm@H
z)28tZX{cA7%EmLA6X$k0E3;_z?9`NF^EGt5JB<s+I(MQ?(6%-G+6}&n->`C?NrPAR
zTH?;MFsQPVh%>p~40+n<MC@qo{2KfsbL=3^&~+KxZV;L3QJ$9RHz)VXfMQu}#A14K
ziuPdY=*=mFb{*D*i6=K$G$;2T*I!ZA2<1%L2;l-YFC!|@H<SpU@cH((COUq+;jeZO
z=djwmYp7e>VNS_j4$w9cM<$D`K}YnB993!nIuvPQ=H|L-(=1;s+A#QMm?64T$UF=(
z<r^~zcFU4Zfu0&26PZt7MQmE<E0Pi27=~02hniA9APKJ6AVk^38J1YgLpe(<Re4;o
zN(*#^9VS=C!czw(v%rP!4KoWC@gl1}J`%@{%mvBAeB?~xB!TA=A^&FBnv!-@2M8P6
z*AhG>=`WHry%?;>xTB;ETE79Qbhl+MWobE&Tx{~G;Ot_3A?`Wd%{c<931-UEN5=qc
z7GW?C@vOj6h%t1O*}}6#azwk}E%qjYyGA{ol;oNmsLD!GKyPzuu?JYGum@YI2;Id6
z-;`33WyG1sVIWuQ&s5`;B=wPBsy04wrDqcc=oW#wbe{1MHcZ2baS97qiBX3r4vm;B
zsDNt9agrINgCo41Mm}~G-L+f+f(DV>s3g28&Nbq;4I#*i;>L=^<WWi^MpiG<3`D2}
zPL>_BZQ`PtLgx!qG+{|}$O56$_JSEi9^nRbXeS}y6f>qEc>#B)IaEN8cao7)8Zk&`
zV&?ReHtH0PLM4**I0{*7!Fea7<5HVRh4eoY!?G#FTRo|I?&Ym|iy*hb#1?-uY*>X!
zTo@1-<AfzLlUDMLj5#F2$A%Pz6ORKpIcpNRhsAP%uBv6KHvySpUUxm>_8;OR`GS;D
zmY389SjrMuuNvrI;4n035(vyg2kHtkD8F+`$$Du8iZmahjx<k*@sMePFk^QxBuWB7
z;1@!QXX+sr0iReOhyn@SJ2o!U5QLV?$zk%6n}Nd<8_xw;g-Qx}uGzcf54c7YFX9T2
zO4r$9t$|1?jbS8}Wppt1=po$oWmFAXdFmdAAVIc65zP~d_zaWtjQ|!YVCotEzq?K&
zAT_e(f{eQ&>Q>SPFgD~H>6{KE57Rm1!6l@8YRD|Vmv!-=0Be2lU0@Z04eg_R;atFl
zRIi{MQN$*X`$h;|c&zQrB&z%4&%U0{aVG4xa`q<y8|>@Y?YvM<8cs3>l|y>;A(UlN
z>DGJZS>y@ifzw#XXCqIz(9?XWQQ@&#xIiw0Viodo0`v!rH)X}FK@LemAtF4^<JX}k
zE@3pc1W9Nc-2qakFi4On1E0fOK&*Jd8?y}>ysQsu`U(Z)!5o6bm1|ao!I+$y`-mtc
zkS;%s4PdrFQg;ZSr9#K*%Vt~yihPcE1~wS6u^3bwM6oad5;;^R6JHU54eprg*eA*2
znd{@UIcp**LDFV7epxE6WJV)cw185&leT(7)cA6S4>5-^jBS<>gz?HxUGPKPkk=CS
ztW-@uS{3ggHOMyud91<i2SY!W#7>J31xr7USv3l}d|?2VKKq=Q_(#wuY4ah*5g~^m
zZwVMX9N6(XTxh!x!J!^U!6u7Zv5|OL7m*L>2jVj%5v`ENfPtA=1FtL;&nmFW<_a<C
zF0{$;8|Y2sdV?Mt3@AI4l|_BlhQ|3I4oaw!9&VZ%^i(elH=@+d<GMpBXhH=tW9ZHt
z0fGeL&woA$B>i}$2}qWl0?&2vwoHEn1unQraD%Q1dBpYMU)F4llMNamo-xy1CL%+c
zQIi0)q>y|4E)qb(7|=^>5+b;Rp;)mNAYYbJK`>=eLZ?!)VCW;SN6FxJ#>$c9%2JFE
zeqV6M5?nya@ndxw6Nx(10{b{<AgdCDmP;bFCP9pnV&n<3S|_<Z80?vpZnZD~350v@
z5JEj(fl1T(#=u+x39S<DxFa&aDDY|$3CmzF{|#_Rkbuji6;3w~hrkmesZke40YGpA
zKO5pWUjJk~#I)J7h-Cdo8pA!gJ0rAsSDC~c1!VPu7u;YLt>|sI$|f#(qMq28UNY|1
znJlAH#sG{P3updVuO=4OiBQyod^WfleNb+o_mta}>2g|+Fhr=f4~g<BhtvQHX5J)S
zB9u_-pO7#PnNSG?z^{cs93J=BkYAci6ngXe*)ZF(o*|`C3I#Z<Iu|)qgxA$if2q0<
zCfaBTV?FB*7ZB7n@X$C9m=L2bYOWTOIEbD2S=bVAF?j=jWmhQl_gX^=AywI2J(1wb
zBB<NoXJ>`5P+nP?e_E+~*&(qtB2~W}9#2pUOMp7b#t6jC=MJgLRt{msNmQZ}l~miP
zC>_aXScZf`hoCVgQfd@%naiG)BdTd5)hr96Bo-#k(h;Z;5H9=^_e2hXQ{0EBW+VOs
zc-HGP6=I)Hp2k=(9vMGR6n<kPmRNwC9t$80H<IdJ*78#cs+{glGntg#W;{qB;6UWz
zl_>JoeZ;^K3^pOGuf@)ks$1@%Na-`GRE43zSyy7@;?-Rt?wdVblMVdl4mVh>BuB8;
zXTR1;^g=TlNxXW9>gYJ*#?P9Q9!p5g7NlX<(u#?+qlAq?2H`|rkFubL%$c5oDJX-M
zh)58`Gg~|TFh8nujcV`fea7`7OBv4jD58yEMg>(;ukpGYvZZ)!;*UygFKKn^6c14z
z!`PZyI;sgNTFZ`N+P1(Zq#HXCNi{=QZ*%dWX>yeB#W#Y$n*JIpE62X%Eb0VGtJy8M
z>_>zwdiDc53Gq8A)@RBZ@X{yieRP(XeBLLiAJtyjAir_P>>nN7p04L9Ew7%0x;J$}
z;Jt|)DtBb$m))B^O^6Hw+`96jb5%FL2*f*BU14L+Q$Qu|2-^)w)g0~Fs*c$>(H*Gw
z)iu3NtWhDcxPYU9R_n98=#uKb?y9`;z1Udrrqfr_ljG*JrEJum7#`o9u<tRV>eWnB
zH&2R2Ec&gJ=KIW=g1N@_ww9$XFtJ%^R-@E3_R?1YH9`wzZk08O_rBZus&y!fr3h(d
zof;rL;`>onecCz6dRBoT>D026^Uj_3%`1M<a^G+2Al)NhH)i34N9!#QK3$#o^ykw@
zlfA#2(s}(alJ{RWyz=fJq|4UaHfP?4@9<qme&w2D-v5cCADwgioKG*CTI_26$E|CQ
z-x1|kPcfhU&tpa>G#@cKVdeJd;m>U}H!nT+f~hB8|GDc|?l`f$b#L;=*5&z|sz)w(
zYxTz3y?5^O3wz!d?;H2Sdycv8it>?n-C90=-4_;o{G?OO^lz-YyZN%CMweY}%wIO1
z+J4IQw?A{l%D3bn`rW=G_x|p+2UQEnTX^C%d%@>_UcLBJ|6G0Y!9R}Mbk0wzU%&T`
zHIF`ghoAH09qVV^d&ltfv+lTN?%@Y7-`Dcu@WFF#c8`4aJ?4?)S48u#c=?)rpV%}s
z_nzD9bANO2&V$qUo&9&)4!-@4=MH@L_7y+<_f2~@eekufJhlGC;n%kR<<6JtpF4l~
zGbi0}+C7_A-;w;}uG>fNxc~azCB2_saN+l#FJE}Wt(6OJc<+rbK5xw9&%gGg>nGhY
zI<5D#{NulW@z}k;fBDQY{g$4%qrULf-&dFI`g7&+`!-#5)AT!j@%4LuKK$sT)7C6~
ze43ke*SDg%Gw+Dz&U$5d$NQK6>cAz}6t`Y-8uA`Q-hI*b?YETY-TSlA`S+~2>-h`!
z4F2oV<?sLJFYIc*{oujlH!a)K{OVU;vHvyvT4_)HVCj-=FPmlSPV3wIm0SC6-f~*$
zj{Cn=Te9)f`H342*3SRIt=lhL_uiI$|6$A%&%ai=?MK&+oI3He(q^+DeW38-*=G8#
z`?@aX`J%gJ&Gkp`F3$bh&2wf~ZcOcY&BJ};S3WZ5U;nmP+%~Q2q|R?tPnv#R$1&62
zbxr5&<F9Ftf92X+zV06V`cK`XSNvOg-Mv!}8~OUC?{uBG>Dps@UL5`4nggR}6>fi~
za>n)X*Uwmc*jI-)Exg9vw4-am?f1NO(@XU|U-{EBdslsH-Fy7o%BKxa*m2mZy(^o`
zx7=76m^y3ax{ogyau=Ur3V;54$##I}A0tQqOV{kLJ)F*6|BRVw*YVXfv!=N5`(1OM
zp4RnEH)YM#>EF1fbNZByW9Clm=$n@yUswK~D{iabQ~qgj>R~sft5%<MPUn=H&PnZm
z<=f-W#UH%;wzyoldbC>j<`rx2x#>G!-Fiw(%QHV+nM^%6dREuV`8}&{t-sg&)wcJU
z2`jIOrnR(`uU}a{ZtBE}{rHT%U%9_bJ6F3l@%@A!7?Z3zxN>guZOMny+swu9?=}}t
z|0{E|TR&%=yD>fK^oNE|%Fk-P=X;Z@_k6FvI?+xy69)?JT~R#xcRpSn-??(QWw7O%
z8SWRwwma{PKi;%2Uf>tHcl9RaQ?R(5xm<5&Y)UswJl5PW@x7z@_S(99yXAC7pU>xy
zsIR**=hm%f8@|49LI3EK8M#_p-q+g7lI?*5+!a@B@3&ie*170CT??mQXBNJHt*nLl
zwkszC`RPXwoc_?Ah35CTdVenMvyLlY+~|DaMCKeb=sS`-la6|Sdz!1CVb1ppOvx<E
zzdJSVJr)y>p=Wn<&(NKNv%fv@*x0q#7S!AAI=0|r<cn()&AM8jsrB4=Y`Nd{m5{B3
zY}UCW%+)V*Hf?2(wG|d5u1gDDW>##MG4(l*O2W%AYmvjIJDxZ5@ZMtMY~%AsNg~^p
z2#00VtPy$U0x&o+E08#>on-xtui}(hH*uyWG0uR?)-EMljx9J}BYhoPvX)HXsG|6K
zNXu~vlPp~Bk-3cb+hv|j9@GruMtZ=b%XkjHgFjvXrn?4M{Aet4$oGv9tbh(Da<3rr
zh|w6>u|T*D$SNzGuHMYgal0AfVqguL0uS&hzp4Dr4(EXt#?kF~4L`Ms_ws{a9|oK1
zjxvhCfYY9d)q1GPPx1M{t#2afS&(Wv2y%_}ClhhmYbC<Fe|jv7(^DpA5;AZ!2x0O`
zL?-%+w!x#7?3HtP$r;OhDX!e=hXTm~B>Rjxd;@{J_G|t>zz#l=%YE3kC%)p%8FRy$
zsrfC`q2ls>_-OjgC~pa@GEsBUy3hw)GTgEQAr_=P?wKyuI@GG1`jx&r?W?ajhB<L7
zW%3GvS)2C%KmYNUvwk!6)lEOT{=gpdz#o4*_Y>DHzGc(>$KQVafrn?ExoQ90<L@}I
zci(H94qo@-ujik2`|sx;f5+lYn?82&&z{`z)%hR%$%E%i{MN!du6=OY?FSZq_2IK_
zy6=*SuWi3|^~a{(@%#0+p7X-K-~MLPYde0t`h}aO-8b#EN58b`%xiCd>c$sVuh{dq
z_x<?ReV^hNR5v}b;|JF*ziG++6JNXd!kd@;<fcFU@%z^=-*f-{D_*_ikGFm*;gg@v
zUYgF?!AHxGJuzjo#;hc;n&0&*^GUQGQ%K&O&Tjvf>1w&Rxtb6!bea~^Qt3`^yu7PY
zF~!sQh!)*%Tv8hBFjG5@W;xl^%}Ihv!fA)A^UhC1m-Ed@{s{BdxTQBKe|=qFeuG`f
z4p$r>(HECX>-&zgwKFU~9kJ@`Nxbse+OR*t_VrHaZEMw7`K&j|`DU=Tz*J4-={o@=
za{~?y6~*ZtZvuZP781r%E$HM>5=<lYSz*FZdOam{bK|o#l?{h5Kn8|`7btC5&6!m<
z^6|D`gV8D(seI^yi0nhLzRzq#uVR*E<=26|O$Won(_DYgFkOkBZX^jj=yA=?^fvbp
zsi}NVK-F*YGMYs!6l`p>Tw{tuCOT?Jd11pBEc#7_Vk*=|bu-RGv(8-YRL6V}AS$Y?
z$ZGB14VB}7#E6nz2W#H;E2(OfJ*!~YThl^itYvp)#55Osohf=ViD4_jnsJ?3=V~s-
zhZl9%r>7Qm#oEZU(6|y0bJbAws)mPGm7wNHE(JE39`6b3g9Bahn!Jxj;mScMQzr-O
z3iP`928G}k!A*<|Of1V?_WdS?4**$G_=qng0Vd}oqiw##A^?R3u(-J>9(4FVT&(Vu
z4?@gO$QvH|NvJ50IJzmV5;-4RlMHrtpsF;ImYsM=1JpXQ9vjFF3lDmX9p=TWJ`!@)
zxYiLXZRkN}z8E`FQLsKlg0<J1Fai3_fc55^ZN_DrC@JR%T8vFRsr?Se)Tlz9WMvP9
zVj|(;jkgk$1XZFOWJo-}Gnr(1+r`;!8q%fFV=*B#L1Ie20C?>mA|IfNL^)23^>|ZM
z)JBMiZjQ{jr~Q#lDa(p@*ucyqOU#iQdPHpck}jUfIfTeMs$*}lgLV?R6&r2?J$-U0
z6hwbi8`_GilZB~Pu>gZe*lGGGo#`fB?YhW{{)&mia~3B&IW?^<gQfs4RjQdQi9OpD
z31ykM*@NH!nS+x$i%T>HdQAx|zp6wf2rLLkB<MnDqgrE=77_9>C3x`wVsnC1cS{WS
zO;VVPX=n{Aou|2=ta>wzwJ^k}j@KNSo?mE-V)gkXSG$FUnR;qkk(9jE6P6Yh5nxN(
zw(~xVNy|u7r~kB{-4B7|;7@8sJvW>dnIoQoTRIVt>%*zV9G~!J&?IH!IC}^4*>qrQ
zdN3EH$F8cGSPID_xkTUQVGF81@y=S?(nS@_?8xzw4Oqim3jYB}>Elj$nsVz;=l~7Z
zxCsU(Uet^=8PZd|Sc5pS3g%Gbj3G{_oY-EAOq1;Hh=ZDpHE~*K%8uobbFicgEQRI6
zQ;9^4HF|oTanj@YzfmURY^hawBZ|V$Q@V{DH4L8-K}<_;FcEIOxeN0*EXe?V^_mu<
z@3KA7VJjWNCEfG|Af-+yJ8HMR>sb{tpuMFelapDFDURZ~MK<A%-C#$W9g(kvY*bY#
zChDuBKb<X5%)=10rF~Fw1_bEw!*o}ca~m7T%r?Y{r?py*<F8yYgCugECaSW|2y30F
zitqSO>$n1EX6Hr<15`*w8P7it*)2h1%I;2FTW>ZuA}o;WUfmXXQYqRit_3jiMabh=
z6l%vr<~`{7F+T9a)RAIulVND7GzZ%4ApO;vd#drA{=+FXPF8hxUDNHF)8uFo(K%au
zS|G$c1H11elfKOgI6bq=6$WT_a?qPmckU6>k*VY@IZKbqnL1sGKFkmJ#4aDK$fzX9
z$HpApQ#5`}Z(^x=lczIaXBK)A6BE7N1L?5o_Y7Nx+*12(wQqrfM9~zdL#6ot5VRa-
zk0Q)OJ1=<k=4`V!u(mF~+nDGCgA8BW$RmY_j+z@)-|FLASr0GD727M3xpH$`tS2_P
zk-JT7lc6o926Lp&eaKlyDD}jW-el1rBeGofQGfcDa4u=?&y|XzOKq-dB37Yv*lyy2
z;?<@+!~j07#37AtKQ!#4-utLk9Qp2^o?;)3)7RdYi_eaYmWU>vVy2gKNv)&Lj8+Oc
zH`os`=bxDTHvFHVU-Yrf<690lvuiO!D2fWC#T|T6*D&LqF(p1>xH%c<LKtU_@ji*0
zttnQWu`_5lv)L@&I?<S=-fr^)CU<T)E{5#Q$&?X4Y~EsgoFA|j(fOqnS3S1S&oeG#
z`j~epw)@0cX$#pS_gCg5jHip65cqJj&eBK)7nkb2G;!T}&-!7Id<@mITi>2@ZB!^?
zitMH)xg^I_Vrm3wE>VT^A;-+aL@h-9rUWK7*?mt$8_+pTshcy!fuB*wL7klL_LkBu
z2Eur<ki&;nhRmJ?V-xfPUe<tLv27n9k8@Vke3q?FPO{LC2F2G<VgfOBMT8`YN*soU
zJ>03gBafh;vcmd?3_x7Np+jaz>Iey{Ng8z^F`3+Gz<7(*QYfZG5y^059EeQpqc+4W
zZH6cgl;<+0!r5yEf#wi_&DfJ0LxAb`4lZ5hHQ=ffB?fsRR{Z}DJWs|q(ucBCVp9mc
zE@zplS;~l=5v*q#4Z0Amvp9&z#pp6V3vf3%XgZy60vm)3O+qa3%2*PAM}R5;PR@S=
zb%h2v`JVBGmtZMM_)K-Egi7>Cuiyvqhs7HZ^WHvF7K@k}+k*34kOxrD5J*5DvTKk8
zF+}1h!QyA~2X=;mmO<o<5(BH?5Qb13U0~ag!FVv(O3{FqjC4>_ZpJh~&&UA-uoh5a
z7Ry}e%4cX}EaE^fu4D4>7C2}W#JZ0FiVteYGC{WuLbY#^_n?%~;t3=}=v9sYJu)zk
z2n+D7eCP{!PShZ>(;y&*GkXn6iTXDd5+>Ck8=)|HrV^<?#HgChcz_egJ5&cDJhn_e
z5FX=+UzN*onV9#V<Tt?bjah=@>7W;k;UZ-KU_5}Q7}i~{PGvljDAX$yKc)vz0~W_*
zX}*FlJvJb$BB323o;KmY)QMc+8gw0@TDlb_Z%D!64LjVDw@ki}N+5yff<AylRQUBO
zV&P9%*|)N+j)@DTZ{2RZ8HhJfPB~h#_U&dKm%3DcfemhhFcsPbOelmn#Wi4PEYN6>
zp-le`tPg`r_BR9D@a2u+B6^9_+5@JI5=o_y2B=<MDN3B3A;(HRB-bHsjZ6&zEzw{v
z#tOT*kuJP~KCGG=$V6T9jY2f=kx429tL-7~kai5j<4~+oX2ux2f1Q=3{7^SPCNVif
zpR#YLGep>=Hz1G?9AH5k*^7lX(~RO$QAofSgaYtASC%aVG=4W12^uShXFTo@>6o51
zp9FAXs(Tx}sxZVI9&>i!tNDxcF4=B@=xxwsAf-D2?PO^P;{qZ$W9o@WErwYvV;vG3
z?dlcTCI>lHH1k(UksueoiWhH-=eZ1AHJ1zUY9Sy;^L_)UOP~k>WbNJS8Y;qf{54c#
z0`v+OO2HP8nd%KHVff8tUN|lKlLFticpY-X*-wp?uxDYl?>SJXWVJUyZwme)Crm1b
zVl25D@{XY>-y%d(8AC`W#!Ca#zCV4Ih_hh{8PM@qD#g02+%Zhe5^`K)G~{<#4M7Sb
zV|%kupqZ0}eFK$wS>_fzD}-yvtZuFN82GV3gHF+8jKYO{LOGW(2RQD1Gbm;)mZh%|
zu2Ba|Fe_R`f_(!o;&uSXa{-NBkwt==(OPo3vA9*h$pM_qK^Chxm}NM*?Tt1XXcVVe
zQ$TeAWDowBL)#?6Aal(zj2vr1*b#jrh?NyWcm;F`TyQgo0@S{r`vcKN*&)GY$z#N&
zMpPuJ7#ym+Yp{jUA)Io>A)bT|tRQow&zOW_6b^B00l`CS48n?QjE4|xWxvJS34I7c
z2@Rg^b!-T}9;aC5Fh?JSBovHq!)!o6$k!oDc7ZOk;3;$47!8S4P=~-P<TBk36NEMl
zzd^$BSQi>A5L}tI409D>p(8H9seuWHsCSvUtz<Zv9ZS%7`D45e%Q{8q;~`ZPZ0a=9
zSyW_4wK6m;Li<krUKanKE)>|>G45mO4O0@Lucr--C1?61ms0_N)}*S0!?Rokt}%FB
zc42h>Afr<T@wQw7O+O*Ui$e7XZm4ggn1GjK(VOG1Vdg_`Ig}Wr5cjMXh0q%qI7<Qr
zJG?^>gL3~<4;BK@p+GfN0Nd~zUXT`kucI5|HFjZ7tK-cj8RJDOt&pkN{O<rw2GEGE
z0g)PpwhvuNbs|aQ_vUFLXf|<)dsPLUoDAYawime^OENitJpKcuF4k>JwvG+OrKE!Z
zJXbFT^`d}Eut*SCkd8|b_%Xs`jdAio7u)Ri49|EMmVw#0(1sHkU!Pq}HvfVZKUid-
zFd?g$55p@UoFiUt;0an?EMjF2GtNPHW4-b)PZnS+6p2!ouE;xFfJj)j)Bm&HBEJC*
zd#qTPV~s<e#8jKI^eSE`$r4b(KqyC8RFHvdcsBEK2OB}%d+3CbNW(fFUvo>g0we-x
zbSPczJLN|z#tI#v)bNAn8WAeP4#w*!E5V3kNCHW$B-&Np7=UwxLtRv<F>nOPo_Ktq
zwQ-9dBK1a<J+V%;B>V&K5DYSh8%LtX%fTLyZbJyibBTV;CrAeiqDIDL0bGIV@3=w}
z;aje7lhe?7kUJou#kbxBh{V4E>T)H8J(qT)NOKCa_S5dK9m#A`Xz~&8f`mL?^&}wh
zTt$l`aKSy~1QH7I*>Wx5ZI-Im=nFy8Mdt%?rog0C--ih8n_eiQY%UDsIB|oNJD#8$
z_Tw5lROK-Ape>;xu9~4PfNNapNzRiFjTch9l}(uhp8P;vag_sahnI*B-*SnzDZ~`k
zd&o`!Fk~QGut5z>ra?vGKw)tk;*-GzekBhw6Enm^dY%%M#k)qK_zke~#|*r}HdBKo
zW5(MVFT4OnOV>RiB8TTVqT)X*QaJ`gsx>aGwUs&4C1ADp&ptL`8&s5Kv}5@zfd~;C
zJndM-#09w5vS_%OCa63rRPw0tHGWsVKsY=M$utyFtpk~G56~E&Ry*CGhzC31WH%#X
z5{SqcKof^Bg(%JA(SBp#6m48%IGHV3lZ=Xou09J{VXUZ<kjMK_c_G5yg}x#qh<mww
zD9z-B*d_;@bL4yjbh$={*Df1jV1UahAaKDog_g{h`^NlXdjk>1#(R)WBKoWy9U6Hf
z*bvFwH%%&;S!$3{^O&G-L>nF_-jPQM1kmYWUI;<M_iqRjjF6*gEDgad=^909-@Z#l
zn@#6Y>`ZTnkpadnMS0E?@bpmvi$A^K__8u__YvZ)#utfS#iKaB#Mn-ocJ(I4qlAS;
zUd+Dn2qPAfab0L{J)1#p51%5+$~){^d-i(W|0V6s<LoNR#P6rhJ@;~YN#}H@lXSWh
zQnzyxZuTaG5MmPQb{cFJoo11JxxuJW0i%O}3?|iW2OEh_6WInA8Yc?KI<hJxToHZI
z@i(6gZU};5bX;B$6j>BV=lwo)ZbuyF_t*P$pHo%OR!=>(o;u6b4IO`K7~0NF8bXWj
zM~@8j@zp?BxyLTQ)OvJW|5hk7v}i!8j-jxZC`mc0B6duqIuvr@t9S!a7Q+Xiu(!t{
zt3R-z<#3W8W=(;J!b!GQiYQnym$()ddpE>*b4=%1S0DOfsT7sl$@@8UpV6}C#OE-w
z-Z{kmW)BrTo=}U+BU$0T-N8c+1gK$(V@hm=Rit$rclpUf<Tx?$ky2INThW=fv{%}@
zRr_ElTCsh3h)!Bdte=SK>+?1)i9w&`2PNV$kTgKk8}SY;vn_e+8ba&$?hVjX&ynz+
zfFGemrLcMkjkVYD5Kxp4Z|(J`e0-ZpC$jj#^~-re?{hBjG1}p7%^l_2DfEDmd7dO6
zM;NAVB5ZlDGa#B}NO@{nC#|xPbe=xW9ZNaZW_uRObrfFf6~pkE$~wN6qYb6W^XzVi
zlSAO<X$fg`*g?5f(+7I7U7v-ww8sdH3zqO>CXVkVxo{0>)jQA|pz9jME$SEX>I=~H
zZ+>z~)K`u+92<N|w$jbvn2YeOA<{a;oDZr*T>FiVji=>$!_+Oln(@P_T<aO^8lnwh
z+#D%5k<X}2=;a=T_UU4tcIJr>TZ-qTIIMP^C(YkfoB9~b;0aX$&sZ-yt(aSwi@~?4
zJ*7zOHu|oi{^wJ#eY9rUTmnruYPEi6tVT@ho<J_;J%s_De!-`@A-aOrxK?`IdHATh
zHZKEwu+a~6L=nFfTiCNwc6h9b*O`rT)(yEXCpEs2B^M=LHg!mQjsEW?x<GR7(%d@#
z5*s-+9h)xXR869|rsGadmb!{u9GR%M5#OGGy?h)}Zlb4+@El{!$g!1*oY7d3CumxB
zTEs^fsm!|>Z;;P%G$Fq^szl>a!Br27oLxd5_(0o_wt>meFN!Mi@^;kXkMdlqYYbX1
zzi#8$_Vg85F;p@4rjdI&FU~DRc5@~x(A&L{=^Q(~RDMH!RF~qZRbs;6-bWl=hk0>(
zeXpr5q)j$ae_b>ins~GWFM2DV_SVcFuE-^(V*af3**ISPzJYu^W%0K1KJ54>Q;{A9
zXRq`NDeFzt*DY4&`fjtdR*|m6a4pU^Brc4NU5@<i{FsdA=gH9Dgh^+Kam#b_q-R!(
z*fmM0-#1}1HT_IGt@8pJ%PMZL4IGaXW(ajFXUDyA*`niQ<LW+fXHf6#S4X>7%Cy=_
zS>)Hrd4rLh*R)O+%vdM8H_sH0j_74Zhdmv#z~|)B!6`Bh{Tm0aliCLuv+<q0%!sik
zktLMr9FB{r+is3@8Fjyca^1@hT#sQBWjdo)iJp!sazh*6-dY=pT?PFQ%%OWy=*P=B
z@H`T&lksWqmXnTv&Uaws`5rO9X{YX?J0pLJj+FbSSNOf$NXF(yeCdGpT*c1a70OYO
z`zgo$!|UXgrR*0T;Y7BG)*+kv6`5LVkcaTizO6>~F6o!wta0Lwn4oj-yC$;B_sYKE
zURmE%5!+ee7pZBZv}d{3N`8#HtbV;5J-A+WHs$5dv*{;?L0=Ucd71jzBXW>b<gmdH
z%a(?UteV9WGh6WErF8xvZ)K^k$QI;3CwaMn2WUpATdx~p_t6h-Nf_6P(luC=k4HIK
zJtZg052t<)ZVC1K??oN=41T75*CKNXbsXx~P`{CE*7{x2CmYuuDJjnu`O_J{f4EZG
z_LSvzADQE}u9HOz*U82vetPgco}k=}->9E<>|P`}S!;5#iuygB`t=_`ezVq})~{f9
zn;bzMeS~&-E=4|RStM5L_fX1R=IJn>${F80o_1T2C!@F2Z;yn2(^SK5<o8j(4^LYs
z%a<a%gyTHgY?&c&fc7KD%WL@W)$5Gh7xU1{+(_JekUux8-$Jb-+kGz7?{f=Tp3P>4
ze;f2mId-#lCyz()&5P9U&lWrR%@O!%qJH}tWNI~$8>!!2d97dCX(#QJb%WPAiLodi
zE1O~bul2i^`hA@Gbt}=mmI7-#NB#ixpF-c=(qN=>7WMZ}^x@3~25J0oOIarScgq&W
zu^Ysg8&cL27gGG?V&q|T+@gJx`sKK+UcaR^+}B=B{r2$<*Zba5zwf1Pmr-t=M_tMg
z;^cJ3=9P@+{mWyzG=oluK9swXb;nA+g+~81JlmFA$Gw_$;?Abc9ix6hzQzv@VfP0H
zjr_97Npzr-+QvluM(B=mIqkm#a-46KYJ^`nIMw?vW7Zg7LP5s~wN^Pjs_-@s_1hTH
zKj5iSe;iuBXCZ%ztc#{$OCR?-EhfnG&?&cZjxj5h6C)?{rf{uK^R*UwRr@dPl>Vvp
zn|de9hn-xw06KkGKFG0(!_hxE4#%&T4I6o-#mOF>gY;+=DnhS?5?SRVIfAxRq>id-
zMV$6sT@UVHd>v!_gfib0<=)0v{=nEfupIgV4E-VH#199NoW|UJR?;UO%}&x|F!Xee
zdjD<lOc}<8F}9Ozb&rDz2>rl}Wc^qB@cH!bMLc#BuWaEXG+F(Aj&Z2T8Tki}$_mQ8
zDfVH}>-0XVM61zt=Db)oLX#Q7!wJ|uP-ZPsW@SX(Qm@S>=lgRxT?+EGOXNNE$Fay8
zSw#KXCO1^WH(Ix$ekG$XhG#LptzvT(oX~&6_`IBNv{~|j-U|I+q#}<;6<MzJ%c0-*
z(Hqze)a@+lXASLE+is}|9XkK=!5p(uuijF57s-n`jyfQ#U$G>rdT9OfP(%%Xk%!i=
zTSDLEKC3Jw?@KwHwh^_Fbq2=|CyN=wDQ+!1w1vz*zQN&p8Twd*Gd@>!eCFOeuF*vp
z9nHd5l!n3e@+S2=(iLZIM`>I`#5G-q*vbl$mudY@>XY<X>R$T_{WtcBwD_u=jWOD!
zIvLhO8F~;H<shp@^fyY8VavGH?RhC3s{J>T7akM&{prx1;Zt?UG4^Wzi!@Hlw9-pF
z5}qXDw^tpH&p_vhM$7b1K8xxZt2k_<P%bCC={$ZO8S1!H?GT>iiB9qnKNz@9UT>p+
z^RTi^gMKgTt37-ro_aeJyQebuMm#dZ`-Yjp9={T6gx>F*3=-c?qjlQuEe7p|UQ;_+
zbvj%a@qL~4ST@;+dr2gqDKs)R7o3qD=oxLV@PiZ)59LAU7w%ZiX%?Xye2Eq4c5J+A
zE>)qO<0R~K*fI*2H*&e>Cv3O!EOxh(a<MO4EB7E=WBlaUDo$$N@f|vcVSSnLT9kI^
z!uP45J1_L&BWeE3zd7<akYfitmUXYMNO5qz%)!oX?DU5+K3nK<S+xHvT{x~1@RZXt
z5cwGTFj<w!2;C`1D`ih}96ZBj;nn*654!RMJ&dj4Aqf`Qc%UQ^VJ~gOg~M_Er1i_>
zF0r@di;FyUOS!1yXtyOvUzg?ZRE0#uzDy)<M(cPz;q6(Qo(4keN$K=2eUUl5&Y|lo
zK~}*hVm#LtV2*Le(@Jo4<RTXaSY^musG*~dALZ=z`o>0-3uX_2Bj;#0ay(DeF_gA(
zkQ$p?png@po)@gwN>0AUai11PZKGd>j!~~)mfmt5GV_aI=a4YSQbe+qm}7@$sVgCw
z8K!hqF-lg@5S4zI4c9T7@<*yzw*D$nPD{OG&H6!XH5|;Zx^@cnI}D$N0lI~TI=(@M
zjqMz2{vypJWT}@$>~~XkJtir!SzbVX?r))c9S1@6azLH{i^-bo;~*|B7!6BWCQ$~*
zTmxR}GESJEBMi`S#f7|`()EqcDAgGKf>Z$Ldi|TnQ6|zoD)6EI!sEdOCho8}jVrA#
zr*R5t;L-jo&~2o>4ZP)_xX%3uU~QeQR%-n#PXO(|3J#15kxWAAOn^?qj5j;Gz*LF)
zz|(&@i-j_(Wenxa)G>}t$ni5r#OZ&~tx9;3j2T>tX7WlOo{(31Rf-Y^wV81+B5Q17
ztOsMPWV*pyrE%;a2-y<`;M$9}#p8qIN&hX0+&XK5MyP}F--Fwa>QTBXEOXd^)*Z~6
z#^@IKbV&XB76|%mXd!)dbR2NvHL1MX@`5m`W8!)!WFFVw)eN}c!MD(z^7L>FXrvAk
zviQS+a;oF6^iaPx4w~u$A)q@1O;$(J{VGBv@S-J?(S8|VqMfQQIDAI-q+H-_ri{v)
z`AQ314hGT81FPZ{=nr1wRuh17PRN0Gic_%rIkZH72mXIxLLTgI>=60l1<;(*t)AWj
z?k(|p)b2-Nh$?YL^Ydz$I!SFy!8p<r;4{qx^;`oX&=pbQ*w0RJN$dw5`)o)NnUMaQ
z0%p{}!pQ~S)Kk>0icENNe{-2&_Hm$VmVJuDqM+KUU-wI8xCx^sY?#oh<BeC-Ojxpb
zt#-@NpsG~|{SO37*!@5r#*tT`d(CkoFKa9#G>Cdx!Ml*+WXYnAN9BGOOo%E6heDuH
z4GJ%8;Cr;2i8xIGYOf2ia8eJH7$K_@C=7Tj553Oxz*9rWsZREo>g6H~wav&Ys?u;M
zWOS$PR^wU+70|hCA_(@X4IGqRXXHHeDjc;Or?*0llDM9L(YdXPHd`P!8&C%Q2xXp7
z8?4f`7BZ2*q$lm@nr)TC!WhayybkJBiG9{`s>B_7!UiwFe(;8|)sdw$PKP2ZK`zie
zh2~I8Hj2w0du%2nH7a1S!Hcn^m>`j>)0AH2@Rmc2ML#j>8G_1}MDtNvIKb3F$7Wy>
z^-G^S^i)k)JxO6zp7-bmWTV3xzh0(oxAO47>GGQ+Pl$S#HcO#1mUv)>@Hut9(p{AH
z?bh5raH4F?pD1o2YXa7UOD;TBs?{0NJ7gv1STe9qF0HV)#lGBD=<_a|5uID*J_EG;
z_8wWvy7kgZMRs4wGmO_3Wb%a#(rA_5Bl#zKWFgm+r<+Q&`+Eg*({%-DV&5$)H%Rr-
z9w~l@J*=Jz*ADDIK3b5QuEY6j`sJu{zm$~T3q4&gXWRAB%f0-}!n>&8JC2j~@^P}9
zx-a(e?WY~<<>ayTa&K=$IhnlgYL@nI@GjCoD&-^jfXA2C%XG@RllxV_$@fNq&fe3Z
z_{mnTm)_45WjcF^JEa#taE)+VNeq4x?yq#LKUJbDtW5okl{+luEaHbNV>A54Sms~I
zdx7iwBX>nf^4m(Xv<JG${Gfg+LhrHK&hf)Yk6DWR=|v;E`Jklw$y~_29M;aZwp{Yx
z#!n0yXLDcX<stP0^!om!`7!IaZ{mlB2AR&}u-r-XoB9+PGq98fP8Cai<2fmeQfKKp
zsa9Op%%;&Y2J|Tt-5m#5Xf9z9w~1!z8eq{2wv%Xv5S6a$$a$d7b=b+Zs_9f5J&3d$
zB0Z|_y%?@*j0|X+^}4|(XAyi<jIINlQWLd7-!#Np_^61rIwJ;j`zYlge|`r^juI!!
zp%;6RV|wQ@L#o8BW26{!?1gYGO^L>|ob-cK<)Mil!(yg+mQKWPp_<$rmS&&g7(fSP
z?ThV}twDP7n2E&c^~WuBd7}J8xEQL1GqY<&WQ5pfKv{`4TJjpi9&q!~-A0Bru89Y?
zk=Rt%0bTt>cac?=vU`NChejYA^gR4vr2!i57wZdQJsrkP_9jw~A2=E&nXo^3<@@2$
z?_bWqDDZCuu>U{7{+&E#W5C~`{|52D<x9EtLvY{z)c#0Ny+5U%2(3^9t0z43ziAee
z5&!qI`y2FIQ`uK`^&0g54*x^7CL{ZQVRwIvpD4{+RH*e{CJ2Aa{=cR4{?S#({Vk=U
zjYnM8mWef6C%p|gs_q&WMdaXg#s_F$gfz{tTi{2aSkUm&<%4(KEz0O<e<pHjn=T;9
zBV09@2GgwV8x9+|IPp5*V3hq}WnkBnQ=TZyp>XIuEY97b$;LJ>hg1R!I<=dNS!P{k
zu&&2lFH^4LPh?DWY0QROH-wr7914Ic^msMR4@H6E13GjX8xe%G3oU1&y*XH7%Zd9w
zx?U-I;s(>y7{>t^%YPeNZb~RvK5j@@aWFZZxJ5kIk7do%$-k0RLE}S&6TGp@LTu3K
z*IA1VYGF~Lin`m1CvCwfyKaptX#Ku&8WClU<KQ1hG^B|HHk-}*C_%OtWhemZDm02>
zCDvgqRB!NsQ`88a=usI>;RBMkLR2jGC?oV_*N1Mu3TO0U{ZoNIyLwV?g=8oTRR@*9
zK#pFgt22VWU=hW4T#HokL8Sf*i{l>XI6!j@;5ge}+ODs!omB~7HCV|BRaUuE;$GvL
zA>eQn|GcIdl4^p2=BaLRA;k%KhE$0hF7up_(IwGXRFnXb3mv1u5`vFZ4||iE%V1z|
z;XIM8l(Mu33nyjeWNpwZ#)vLrRd$q6fmajJnbq&oO9HBXQfZ*Ug#cwy0jm=lV_lSe
zn5;aO&?WF!)YTJLu(590{k4LX$8zt05Cfu+Y0MSB^5hlC*T?ki!ZaoMkV%%4qYsBn
zLxV+65T>c97*`x#i53><8P4kM^Ki8cvz9sP!}<wu)b*(J@dhd7#|D)R8I%beX${ax
zGZ#&1(@+R)sjf!%sRJ~!eA0-T3Qgr`RIEji^%N{qw?DMqigC)#<jp~f3z3kF7#qby
zwTg3D8?$08IAOh|=IKjLDx5@`$Uyrqw@l!-Do$4}iPcb*D<stKA4EQSW|ri^4!#K@
z@J3Ndi5c*7E+x&FHH;y5+6bkhsi8Qt&v5S!>o^h_(yIp*^#hy;BKEKy;;cQjg>-V%
z9~y<~z_BuOYET?yI@;w56@-lyn#SltYOfR4T;Yw??3pka03Fkyk#Ip~Pu>&P4OX>{
zXg%<xbT9d8u1_ru(yK}ZC-PYW?}>nmIID=l5C>n0%gntBIf&Vr!G*XrCSay`a;&I5
zPB*;i$CkQJ#1B?6!Qm`*h>qR847q&>k_<Iv`8-^l9!aWAH5p+C6|g$o_0vvxDW0Yh
zbG_^7RTDK5VPFhT71q!g)kcI`;a9`7ed>1s6|{aEPuJWLa{Q~mT#Z+Tl?vVr3CqdM
zB&-fM-wIy}zJM`vp!1^IbUZ@8)w4sR?Z-5318JK~wS%gK>8N;OD><-R#T2Z!8fdZ>
z#)HsHaib_VVkHZWxzrETMM};<;;Z*onF3IP;Da`H4@Qs)t<n1+M<NI|bi)*rA%5ls
z;vg3X+eEOEH2n1}q*r%8i-CueVq<IT{dNG2XhFHr0j=hVM&xKSEkh*3cLoDbXuK?#
z5os@L%@XO;oYE?`5Y*e7181XojZSJ&Fd`KP8D&_e+nnk%I4u5*z>-i^4tZiYj`#L$
zJzkAQY=hDIeR2dDC3D?SqsOHiT$Tnkk}Gib7<gLva(9genwnA&h-HAA!WHOzVv>wI
zFh&PpufE`9ssHX{pc+_!My^^um2MAl?2Q(6xKNi_A^M^$Q%_lA^`vk!30{QzJ<kcf
zJ&X$xn9+!4jtN>?`fn`GX@aE4f3@?`FUp-7epQeG78Gt64wITE&yMNXRYoThf%XY-
z0j{DZ9i|4u$#gqK0C))#Ut)&UQP?Z00q^$k%fXU!)Td4~oEhF7^$-U}X>`)-S+r^=
z3s8<@dz2Z1(OcFyk=9FDd>ps!VUTVIS0NWamCtLCr*9-rzF;*t>|~Hf?=;`ftDdAc
zj4g#Wi#?6virB|spX!CEx+<&+$%9f{9~TvoTj6Ps$7=tO$kkYpMzQ5fkF=gX$ozx~
zKF~3=5H|>YJk|^f<Tj#(qBzcJksLN8vFj!t>O`}1m=(dGbRx*5@)+&E7x}LsOC4C&
zK^7%NRTdzYJ+59|F4AdAUDkvmzNu;W33tEPeJNDAPsf6Q_nu2ZhxSN^U)--_jc33s
zCC(8H7EN-Bi<G%NwK7t4p+eY}QM(GB@2+ZWU@M=u;FCLEhhFmZUX1i=5tAH0UImoM
zArEJq(D(Uq5>!S``i)MWR%TlG*OfziRS!*a7Cg<0s+@T`h8q$=Pj5~q6`y*1!gEyA
z)1Z!1jsumRc2d)}(lHi(Ny||WNsoT8$r=4T!lm!f;@j+ZpG=5mf|R+XN)%BAN3Bgj
ztcn$o&ltuu0=RI_P8BkrNID|ir`Dw9aEa#}t4k&T?I`sj8H$zZGO+_^Ak|qd94_!G
z#`3Fr)Jc{O6ki1oMcIQMnEwW}7`={@$07xba>mRo)3BA=Y_P?u#k#;N!9#O|d72A(
z*A<HiHhajx)-2Gq1~MW0EE^J<kB(EeNKTCM<e72DPSKfX(H4mdW@!KTpWs2TGgi-A
zQwV0NgMJ6XqrYB^P<LNv?GT{b$2N}16-($RL!xag13r(T{>yIDm{>f+Z!;4@Wa|te
z@SKCGSf+oPw$dHWf6dbe3`lL)T4*42)GQj#I`2=wM6AxLXssO~gGeQ%wL7fu2WwVS
z9F9Lj%>K=L<6%^_ps6lT5CBcyI#8L)Am*XeGt&XxlJ-&sX*miRFMT@jf>E$!r{hLI
zmeA!ij*<$2+KI!xA`|vz)%g)uBDgn}F%lWToyl1O!%4q9h+c!7M-Nc|d;k~fF4vT$
zMg!huJdqkVQNtNs(;y}EDBZ-P?OIqgPlo-tZ=xm~t7|d}KYlkMIuTlpAd#sKZC?$}
zb|@j)z>o!1Pa^@R;5pD4B8cliI1;RJ8BR%|H`4erh&1pa-paV=unq--umwGE=apDr
z!)7?rF2t;o02c+VS!Gm&Q6R&6^aTjHXmPXykab8SRmX!w-%wyx#k%@-Ayv1H`D{OE
zH0ZanCpxII*=-O~PRD@IKs?tJhP>_^<B_8eVw2)Cb<K3E&|Ct>nR?ecL4BenVMcec
z?(<T+;1bpsfioV}<iw4QfWr{eW0^c@=L2NtB>*<+8XG8vvv~e8Pi8IQujPXtt8o=c
zyXysG%xYDB@SIUqV{MQqhH=qn?I$)Ntz>OhN*!xUdqOiNcaNEt!YEY3S=Gf(qgLG)
zXGrFJlf^ir8whp>l_ct;#fa62QX<tkMKYn-OVUaji1`jVKakj;YM*1|<SIt3h;@kI
zAE~&gEiY(KS-*guvj1Y!S`+6~B3RCui_r`a%w$xnY67r5^;HeL{%3=#*7GmErQ`{~
zIG@G63t?y)Sv14r3QP(Zl>HCj5xR^7ek{-;a*Ne+?e*BxI?UN?G=Pq5q1fme!o)$=
z09tS$W;<U?9!eiDjHQ-{uP02I2y$vsD5=V&uAbKKgDWrk6e3T=6PZw#YIV3QtDuEs
z9YTE>t0{+!{z9nMSS%$)X$9-Dyd%W_{>1tvaJYVTl;+8u4{%Od2{UswF=0&Ih`z|<
z?OGtf4%R70MpdnGhp!XWc2$n9SWIpSu_K=66nHJ1O5-5<RtS};T>9sfXF$nzzf+tV
zNc*d|K}c4gR-+V=tPkoeiMkp`EJP#LxuA8(h0H&I4lZKC)sG|O(7<x=w3a8sB<*KT
z@=|Y0nhAgy;2$ND_NlWJRj)D^lAIW7%1A1?thkIXGb{8*oMzN@R;eu1IFTl>q?Di-
zq}1Y22D%{+exlPdQo*W8UE(;xX8MZNYkejnuLu&ED&hr$w^({){Yem2sGF=B&<QvM
zMpY>!XM(+{v04Qov+!tI%|dn!4&|3!M{F!yx}ku<777Ej2H`ad^;+ywt{bATo`*a5
z$c93qo?#1vCqPRJgb9Ioh4!7HhP~ny${bE3y!e$lG;p|ZF^{I~SDTbUY&h3XUcE_%
zq2Poxg+Q+;K9xabv#Gez9trIzq&cZ}PkA)tMi+8quYFgC=!i-LA#K(($kDh+#J!o#
z*>41f1*n5HgJ7#F(aDR^hG_mRB&~;OSfl^UF=RIZim<`^0prDH6r({eot~zK(hMj^
zFe|9Z^7i$dbujP&uZslQ1B|Mh)qxpc98=$Gi6&HqviC;XZzG<)=4`#X-6BHes3>s)
zpRH*_J`SW~G=&fFdeS0s0Z3@+vKo?&j~K)GN8ENK!yaU?MQzncXin%*H3?OuMp+K0
z4BfHy1gb_IRS5=x=~kplvxh`J+Ll-V>fGd9wjBt?^M@T)1GQC5Q6t@+ljr(hWi&UM
zgdywD#p<d9Ep!+iTU8bylPs$=&8APB<3Z`((wI;VJT)3RAKMIGSbwBZYf@4vnh@aW
zAOzZB+ehlw=-4)-*idj?a^zHLpSB*cWU2FLRp|<(U5Ge#7xcM5P{FK#e9KAe@~{&X
z(cy!3sS-GvfEHDoMP;69s|#E82*A_78sKZMBahdtGjWPJXeEP6ur<UjO)V=NNtP}{
zbrz)Z;<Pvs<7)<K%7s6Ls^_IhL}Af-B`?ir#GxS?BL=W+(=l5)q}9Ud@v|cw%?xlO
zTt;*U`vQ;hWl$ghuh}W3RU=uFAoZFE-I(8W&aBa5lhH(3l^5OFz15y9HxwyXrYfkd
zN0C&5Rt5@);^1)qO%ZiQr>jZYiB(j%RJ5$?L)X#;p*Y6u{h5<yMYv!4ox6Fy<z(e?
zS|geHs!xJCOQ-__`iUu6NVv{t1|z7=oRp(T8IV=J9`#CLq(Z<dSBv7Id!4W%6qTUp
zuot##vn=Ad@Q{hilHnyMm4+|F6KKqZKso7}t$f}cABS}zDuEvQ7ARtH=n&-<n*kUg
zjh)&M4zlB?2DD3wiPap1z?NB&Nx<rrfNK$qEU|1htdpw<hARxpKedcqnJJnDawL$*
z%AsMFYLh7;KNONxmYXV3%K)D)Q^9&lVjuj+6bmh=>?X*QllJL!AWnPKc<sMXGqWsO
zMC<w9OF-%a>l6B*1S{gO<)sM`$3Zt9^@Nr~VE4g7dQ9lGq#@w1;c(+bnS91erdqKE
zeVHr*8iA|<n)s*xvn@++2IJI4db>r&5b?I(z{i-_gNT|*Iv8Z}M=x;&eZfEr=Cf6)
zGNuW$&%`{)a=>Nzq`l}DWNDB1hX<mV^0Nv{YMHNN)fi4escFtSK>Zs4f2AoK5*4)}
zij)43%2cSG>TPGdCkR&RnvGqlP+m1wJ1s$KK`BRf#wJag22>smtuAzSs|X)h5Gq5l
zL7dQNJ$`o&s1CS-;Fn~h#*Tq?f4}2KoB9n`6VgsCA#u+nLFh?^g`Fa`!W5C2ppMI+
zFIa6!(7}Tu<&LDrLKz49THwq|6ns3<CbifT+CoKT0|RKys#wom^(tcqE_Nr4Lf3D{
zGv{(c(#Tj=6@ekMN<FB_(EGe*qT_5G>K-!MqI7ImGn5+oBXj1Uj=BAU^(s&==37kA
z7ar;|VW?Jpq!oow-C9fj42PCHpzAXL&TBbrW=BIWoO%rfzbc_5twbdsuKNOy=IA*1
z;J%(T25SbMU_`WE@C;cGuTs6Jyk2a#uomiD;J9_+mAhJhJi@u=Hdk(lBG=|!TP)S}
z&92rlpJ(2iMqC_w8RjJ*X((4+s|+{W>va*|vrNm9^A^L0%P8J$dFG5))S`l~^heh9
z+95IBiQzZH)V#EK0C`T8bYproZ@!8Q(4LrUQ@4y8bW9|*l)1*TOe#oxQ`t+o(GQ$z
z_@s9{Y*yw{c`(u!rAEX}lh#qQ&86b4<p&^=HkVyYG|(1}cfD<`K8ZawGsF!6N||`a
z`h$;PcwJ`}qnWXkdFZgQ!<w1VXcD#4D&zQZyqp}4Tl+d{&3Oj;yqRZ<Q%%}O{b^@U
z4v^AD?j;mD;t|Tr9UEOzM^QgME9s>hZ+<uGC3NJEpHCO*;l|iO)42Ye(Mszcjr#Fn
zNBr1mRdvzwCGT|yX^2lBQ~$(c>1c?DeW@)Tni094?ud#nup`3_8gj#fT9@~qO>D5i
zcs}JM^p|w5v!2h%<BDl$NUqlXoobD{n}F*{+Do<|l^BEjqY<(jrj$_3NP&6|(UKYN
z)7UZWs}Str<M45@Sk#GljC@PB=;=YWOrP@Ws1955$>WVSy?%<fRWVXMMB-7^MJ>N)
znU~I-S#B&|Xs5oJ8>{meSJS~Hg1(238uU)~ILQxro>*Mcp1P4n55i01?35Sj;{3A4
zt90%>H=<iGL5@mc6thOSnZ<=nTuUuKlERB`hQ^XaQ|TU5PPhq4qi^ZRr}N+^gQ-*S
zSxku!jpSg)`q3O6ZPAQ4Jv=u^tFsdGI*P7On$7kU$NHpgD94*??Mco{ciQP01o>Hr
zp;%v{Em7YIV^uNdxG$$SRJMU}(V`i~EQtC>Q&Ub{Ass5yByy281M$Wlnge4{tGwUz
zc^ZnbVccN<it&9};b(V?ynBq+W>@k-DlxlW&CmVlhpv-zKlIr)zv7^!PrWpJ=))iE
znzFGnW5xGYw9kF@$5+o?{oluSmNy)`?0a7sF8%OpUu%E(eaCm+^2)KDk3aFX{CA$%
z-n?t|2fH48&uO#e)qC2TUvHaw*TD;CKe%{))2UB=Hb4Ai+w?nLZff}4p$!eA$G5ew
ze=2JG=a(lXyY6jB?moV4+K1O2IPFvSAJp*0yG_%D$Di1?zM-q_ySwH#eEw^58{TEQ
zwy*qcQ`--|FmKWq?w>np=5M>&R-S)sr~j8_`Ja4YS$_4JW7~GV(%9vmSQh`}szc(P
z?`Z1!#v}8aPI|g6f87t-;+rSW@6z%%zbSIc6K(Bxe!1bw&HFB2yl>x<#p55Jd|2({
z|Ma$(PH(#S$4`CYf?XGX;gDSy|LBm-e>$gW{7={AU;WiTmtOzX>_wNoa>~@pesa&`
zmtV_Id-JueZEud>cEI!FpO}980}pI}_<_T2*!9NJ*=wJkJoU}j-hSYluf1>f!{;3|
zZRcfk4w!vmSK}8qG_~z}Vg9N&URb)M>y?X}zxc`-$(C1UH;un??4-?q>}uG;vF4FS
zW^hb;=AO>U&)l<e()ivvv&Z)yGJE*v)6d@e^A*SL-21T^JNKS7Ys=TCca4Aju+HB<
zuwd5S2NrZ~d1lMx5B+pY^XAvyHv7e2AJO%1&%AB+zx{mnEG_Tb&*z)hug&Tje{J@s
z$M;>Z`0R()&EI?0M-HiN$shdE)5k8^{IO#X+ja4~x?a6_(wgx@a{2L#uZ+h3>mQc9
z{+(mzUG|eH?Qgy^z4fy9ZS8#X*9UZNe*KgA@$pYiefWVng@;dEmb?FrDO2wM-Hf(3
z_pNJrdEbfg!<Xe+c0PQ-v@d>ia{9%O&QA7S(A2zd*W~1pSEeLuUpcJ#L$7_XVe@Ni
zlJV!3wQTw0vI9T<$Ptr1{>ZA1v+n6^I`f{lHNNosIkPvvJZI(?woGf9wPpH&JNM2y
zaOW?(X6?Io>Xh+&r%(C)YfHNJ{(8x*EkEsS-uFyb<M^v<nzrm+*>c~HXV1L(=UuaB
zZsMN!Kl6_0#a%PUFP_o$_*v(g@x=>@<C898?Acs?ecIcXUHZ<+GfqF|+iUvII5E9*
zYZ5)XQj+nGAGW@9^4TlzeeHk)Mt}YGboAyav*zVbn=<^;RV~|=e{@=N+S<ANl^?`6
zJot|M=fD5S181FAnY!(zg<U(|abUdq<t2rOA6wAX`Jl9|d0|R?U3GeL-6q>oI;+rj
z-!)wgCkz~Z!=t+wHm`Z%fT_<taQNhF?&*?i?wLCE&>!U*AN=ECX4mJ}HZA#l*Q^ge
zuy*#1U+A1UX;$N;S<M|YAN=jAX}@`3VY}SeG^_o__8GH3-+9B%+eDsdI^@77aw}$^
zci-x^pG|uAoM#tbV)<fzS<8OuJ1gBMe4wM}@iSYd_MhG~cf7;dXFKARm#(<H?IVY_
zG^RJ_a-%mlnI+FP%>2rc$0f}tna*v0xT>)HpeeHaJ?qk|&-}1l{j*P|+g|OPG5q5r
zqn$4=YgzrvxotN*IIFeu!Gqhb+jMZtb+#qh@s0&?>8$PpPH<h#y*z2YbNnFLIeu7_
zzh_FEzlXK?H4B>WyXKIYYrin1;m*%b?|AN!Rh=JxWKH9&tvwx+u5O#Pa^tf0m77-N
zuDLOP;MN;EXUzWe%o($XR~=aMhs~~yEbDy!E349tUtTmVEgU~j=(5jK!p%2{oPWqw
ztNw8Ar`EnyD|N5hBlCv%!HS{wcNFYVmH0hBIKJ^yUt8VT`H7zPj(4}UjNJUamQ!~(
z&OFYy&H8WKQ5xe-$ukc=c*@A3C$}eapERd#YRpY*`|Kf8+Wxcg3cqgo_XpeTRnKjl
z>FlGEYIb8wyFL7fm-2s__P)xmro6}b*0F{?=8Bn151iTBJ9BxDOn&d;_Su~`9UXUm
z<oK5E^|?v+>^O2p?f7@3yU%)i{;{{8-*L6fZ*2KPbMEwyM7iPKVnc1<poZ#IcE<AK
z(@7WpbeSprw45L9ZPIzrYWco<EuU#<{oLw5_ikN%=^iuhYr_Xe(UJWU4SbWIr2KZW
zVTy?xqiTESoLf3O{<X7t<XgSX{k3<uzJsSsHpuneWA?JrnFkLvCx?#C7|FLB(C^mg
z3vGW~G^O`|o`%|Vd*)zw4--zC+tWP7Rqrjtwph3*F1G%nV%wjqJT`sIjkY!<@yuCC
z`M~?Q-21Omt2wY(Z0`KWgQfd7Y2zWc6eiUM@(0x3^^U0h?MF7UAW1&+kJadyO-Dz=
zu6uTEVD4;dj@))(WuS5ScUR_1PnL|>ud_brkTYw1?r0`U2B-I(I(XT4BoTYlDyfzi
zFkyB}^muoJt+8Hl3#7e|YhC6r`{WXzI(}KsaRE{;i`#^+uI7t5r4F&@G2d?Ba~P;g
zw=U$@qL)f~vUqVbN7L#gR-3#re-f`E^zpbwEox0K*LgT;lk*y5v%XXMFJuF)uT#=Z
zJSKN8a?Fc{4{YS-$Ej>Ie)M40Wap;Huno8|KP(q8KOV>2*^(cK&YK#W^9uYPY25QX
zwI_wh=~t#l^@-EOYk7fWwbP*1NdBxdxy%Y1)*~g>K$eM~qXyR=)`Zn&%Llt+@z8z=
zegkcOjPg|}ukIQN@_d+v@)Ey9BDcWF4tDS#!@dp6y;MtHZh_|D-2saNrg-Ak@j(N9
zLesI6(x(Ju1_&(tmi#r%Ii#zG2VG0Vx!^}`|2=?TV*W|6ZD6ru#YkVw3+MP^BZ7(-
z`Prz*4Tq5>D+w;|N;ViUgX?aJg-213jD9(SAobQG6S4BvGYBr@;t~nRW)N0ArazA(
zrk^ZAnave^?EpTq_QNP}x^h$YAi)k{G~g&gn>52gY5J6x+z7Y_FlrSUz=BEB!Psoo
z^0np*o+LPjfzfE}#p}I4^@p3IXRcfOsB4vNHp4lx4%dz*d0~JSwjGu@6e4V`8K<h!
z0=nSCRL&e$i;Pdmg~nQ?fB=lF-k@^m8F#VNrTQGc^5pEPwSbS(jKhnRl87dudC)c}
zt2mUK)EhBA@qFkgs0~tNsErY2dY~coMIH#!Y$=Ui3ieF!L4`xj4z~=rTv4d0s8vi_
zBj!UjsYMA3SW(rn@g$`pqntxjlb8-Ilrc+?9cFo>Yh1wUDezzmJ;z(MhB9Ihwdb|9
zr)sC>p<c9{N%9kepm^d_(JHTu`#~>v*!_jp5xIa3=N_WL4=8u+?x07XQ3%)B!H)=7
zW%rs>jmT5?pZImzwDi8uliNe=BfkFXIbYv(@zQIa|Ip1Bo&UnmFMaCOr|ua4=n?mw
zcgB}L^7x%U-tyF|$LwA7+C$fjZ@KFqAHVaI4}SLLV{U%_wcDO~{>2AA^3?b#3%0*`
z%mX|A^PwM}|4;Xw@igiCe{{i@zx?srPWkTZ*F3xL*B8I-{vUntfkS_K*U8`Ae9bve
zzk0$$`%YQ7bM8-nfAVRsU-u7B-+$sm5BzB9jUPYb=FMk(<LB?(e(xDyzklz-SzDgI
z<Lr+;^rH*5KYYd=hn@D&?0x%gKKrcOPTqXo7k<9@zMtN9*1k6$IsNIoPFZs87mhjq
z!XMmv=ErY);Ea9yPF{8Yb;qvx*&e=qav|%%2QFH8?K8*R@%Xv9p6+>h`TV(bdA#$R
zN};WGzy_JwKCdOI<<kB?<=AEKv+)Wyr@0!Z9XI9DCx6v%wtdIVz5V5=d(6>Q+u9`G
zGf-;&gT&YWA(!60DT+N;vm;|BS~n0y)f1?H+DvYZX=@&slI!zaMpFwjJ}joN$(TiH
zF-ix!Q}ZXBJ|jxzUNt99CM`$@=9?t{Q<KEsElU3t#X?&{+~7}(_$5Z}1l?MYBmbqL
zd1_=D)^N}5w$J9GM|066Go9gXd(_dqJ4)SPlhN{?GR(;L5<}OwsClPNOKW=q9PRBb
zNk#vaNF%h`ID`PezB>4N$YYm4hSyf<H8}zCTLi#)#cTG#gpeZP!q7nE@4>_w&QFjq
zEOecTbf#${#pS!SKrfy<f#I^%6R%pXqDP4Ia^%TTi!~V8nT~5w!|=@J@~F$6sUBKq
z$4aq6<mFV};hTqy&3DHqAp{gE^LXaLFdIj%Tw&SiB7RLUjtAMXj``bT_~r*-^>mc!
z=Xqz5|JEEaFX~PP^K2GC>K{_?SeenwjZjSRik*V*lO(^X%Ja}hWh7aoZ_co(I?NTe
z=QE3a<cFAdN!;!ob0^-f_L%r2BCz{KB4Z!1CV~{;aglEl=_qN6DR>}`9y4u>08CPW
zr4+^7ARi8I;kL&WvHWp&dymWzc1Kc!m~W)raJ}4(Pr}I7EN-kjZbiQHCd)UUXy35)
zUTuxzi$vYJ-OPZ*r$J)2G8pFD^p%9EVd#Z#l=9#U72=aVM#lQd1_dcK^GFwKB>foB
zEp$6(cxPelsB+5cHi#A&$ZRBID7oDC#h%fPFIcgsCa9D`V%sPx&pWoVOac>ICm<{q
zMs_Mu<~2*o$ugq7ao-@gD4iCIGh;-J<&^6)%Ba?`P0OB3FRvGX;$Pf4N|o|nO3bek
zf}*hL^~^4kli}l4imeKrp$7ZnT8WU7>9d}p(qbnxzF2=lD#1~)Rc~W_C1e)qBW7d0
z4rZjt%XuP}MM_CC7E^;UG-H+uJl@K@G*|IZ;O2gbBWh_${D(KsRfkUXenHGW4ppHq
z(DvwCnqrK@D65Mr9MW7AuLY#YJA|em;SFzvb}iIh0GH$^V)%k78s7B-*zZwB7g%1W
z2Bpx#EB!JU?TMq%FHeqO=z-Zges7FI*U+qQFyx%=l{|Y(T5Gksmim4BVUkRJQOr!}
zVso5OmZ+jH7oc^ykv{0?!-7(3J)r^_RXOPgR<znNsLeV`XJJqB_@<1HVi5-kLj@ab
zNs>!yVl1+VQne8bQVf-#yxQx=jF+PY6PauqCHA19TV)*J=gtWFkq`c=(O=n$R4J4t
z!+ko)x{#Z)+hd&!62{7{qs?PrO}9{%2452yHWo?89a-ffKT@8IC{pZ+O93p}oCc#}
zGHWr1;v^TExEs{npI{E)vwPWnj*Tc``43nh+6OW2?`!d^juZOhf?P2c(SOV0!EoTJ
z?41z%Wg<;H%%4l?;}R?0@|Co-U7D+!z%7z&NRoc~f-3bSjb%wgr%>qM=%vk?4*inD
z2$qCvf#bquPB&x*&%hQ8)O@SBpHfR=dqfw7rc7r;7khyG_OO8=jza@p51ZFKBOe+%
zdy4#~o<b4FU}{ISNO<J?ijaYixoWXBH21I<Nbw@y5D4@v9TdgbP&oab>23jzw#gVB
zPHQsOK5dN|3ze>|W{7p&7~_*Rw{GGdhCNZY^bzV$Qb)*kOQFvSfeM(|IU<%aI2MGO
zVO71!`n5#+RD1iQ0iNfXCypo1s9#?umy*^v7;JN1eMkEM0j%_NJ*F^y)F;Yvp>0?b
z;j%d5-kX=uZuIVixbKj!Q4}85o9=+m>i4I2t9cQBUZPc4p<_X>GN^fCI+&YuhSH`M
z##4|Uix7w%87C&~&hCI)qc181fPVxYkKM^ZOn=UkFU*=1v~;jUL!lrkWhyD!(KF#I
zcrKP<keJLuwv?FVKSvwB)i}+^I1K@hT$Pe3gjKN@3a&l{ftrMLA5j1q&+o=sqIl7Y
z9o8Z%(-7xstUL^CgIOLV@Hl@!$>|y3(wZ*oFgrjy`iP*n;quX-NrjASz>|)cFtMf`
z5jv<2&OS&f5BZWAdeSciT%(SO9+sYr#SG|oN%5C;6vR}6a*xPNk`|s;9p40Za}Gc;
z95oV#X`i8Jl;NGO5AWlGshydGOVEA_6;T3PwzTnT+}zI~mgb}__psU4Uss-Y!3VTa
z`r)bC4}6sB^=s9ngOR@cqk#1yk49|aSBUg+D4zM3H1B#XV&aOaP+FUPJf@vS!`Mfu
zVsR(aXp1p3QbIcFz%kZrq9z<A<VP<V@T;;3e=w|;C4E#LE3|ojNH><1G?#)DYbd2|
zxcbxjb@V-*5aWeAC=72Zm1uib%ELyVDM@5)VL&g{=nGn`QIlAV?;T6VOpJNm*i0aU
zX2|c6Zo~K9w3Eq~us`_2^ybFMD~X1b4M-E0D;?P#Jjuw<`yeGW@otW;S*StF+Nmrz
z$v~qO`fp;p)5y{1x0Bg6RSh%`(n^o#ehS7c(RB$v5I3B(F*4*ah`voD(m6jC)R3u@
zJ~bEkwCbRwK(xZMJMskI9Atgzb3Ef~({3kY(&AZ2{jeG>GTQ{>X=~rnrG!C^jF5N1
zRpd-+shdow2YQ>Of5!<c&bXCp`MxU();>9j^{tE3*fSionv#|*Pn(Qbgbnv39TcIj
zny3HK7W{y@+f#i7OZ%!2!L7rRoO*DdP_W|e`Ifx*w76T^@-d~ZSrgSPQ|ZXn)(%~n
z^g10V^O22xVq5i1B_O&b!ll@sq|Ld4bQIgL1AVm0n$#rrwVZ2>;+0QTQn90S2Igb$
z#8s+NYNvfvc$lPnpiLgD@o7sd=G#ZwF)XV{6!QcmK72eHOPET~WyezPXnHM6K51|=
zw=aq+R&Ce9v0Pt2q^}II%o0~Z)rgZu--quaZi@8`!7>m=lc=3~-fbJ5rNMh@J94HY
z?Tf}D)>>7O53yUPzBxhWBpo^c(9Q#bvn_L?kLg(f!^9~w%~$9RBRE5=-D*;a#Pkgk
zN<vK2Kup64dQwEN7nGw2$}^#nH0@GloOXo(sj<w3%0>TH@M5CT5bEk39aYTi6B#Q=
z6h^^8)ystssQ}&R)9f7oTx-}Y$4CR7nRP+8b|?ik-t*5vhQr<xIMRe;kRqpijQ+Y-
zs40cI)sjGyJsbmKkw*)B{fcgs9O$H~b0g!KRT&0JyT5!)ESh7$YnXx4NhN@4214M6
zYMJ8-@Y7*NltMvzd7m&4qA;9<=`6}}3U#X{?+0H`MP9B}GgWnOo$A!dHZa2msG~Ds
zN@*;tVXx5B;OI?hLz(;;GZG4>z#Uv2X+Qy%1!IWl@BWsE(c5iCVl2ueyfWBJq$Bn8
z9g8_yCa-2GRB6;&a?*WBG6_cFNgKy0094%CWR-=M=*V5`!=V+83ZAAppcvMDFhy*#
zZSM<sY>m}Q%pwh_K!lBL2q`3EP6g?_!%;wR(#S|3oP(M(gIgdt{N^)nRfUm~t8bJp
zr~3zpxqx<oe?l_}D;8Xe&Fb4svlDMM?uEl>zkKFiq5!VI<*c7@J$a|SqWA5wF%8|D
zy_{eI815{C#!gzCGcl$r#NOddB8~;MrIvgj7G}>ChCNw`YHf3G@Fka^tQ1MBnqF0E
z9k1D9TFlW1dPI;1ybIQAf?fHnjzBXX0)sXyOTQ+tD#)PLGjMfNN>*qTW{fge%^VmY
zFZP2>Z!h_jGR#n*(4yJiv?0z(`xTB3<4zPuZXoPchf;fqA$ksMB5KIKr$n|2UR(&3
z1+d}lq!_};7;R(PS8cuc_==Q5qV~9KsSw&s+#zk59BoiJM)edRy>pEFMz<1ISyY5y
zX4kxf87@{UM!UTu=vG;)`Mw2s&X6>ViEK?1C{EO9%`t+;MyTq}fOJ9Cgq#A3EP_p*
zZfR2$gvaGb0%L}v01+DW+K8^{G#w|-hY(R4e(su-k>QHUGb(G_2I4Adn~9)69Trzb
ze1?gXnamVmcd50RVWf))2a*LD>j#UW)4P=ssD*PT-v=vdj6s=asS8#K;xpYgutE$-
z5+Peff~#p5Kpi5+a;kEKX33R}MxCCFSg&D#GUw5Hd_r#l-fO=fkhUk&k%{Ya2+(@2
zgK0B96LaBNZo!3GtdLtTqkeOs4uHcdu<H2?7>WRo1cN62VTzfcIa0y>%A(E)tn|s@
zdcj>mQQ?|hY{-j#F9o>S$%Wl%KJ^JM%g=iqeSO`s5nfcyRJl+y4ng`_#=$fMA21xw
zmUF&mG{n_bPaznLNb8K|NN00(n7u3)IYDFHWVpsSN;<Ic;X0yl(}g)tfCHsNmv6J6
z`1%?_5{g0+sOdT<K&F_e)6pzkk5QM6j3vSrU}Uun3OYV8#Bd%Y(yK`I%H4XSL_HaC
zzf55X$A2E9F|Oc2Yo7@3Y?7!$Hcyb&wf%lTN$j!|0s1{h$h-bpB@E=QYgv~y8D(yu
z#sd?c(=;>>Pw1y19gNfVA4XgC(10poWtNHQT-cwK>3a@MaicVla~KsZ8olWaTB@AW
zB#Q?G(&0u978x#xNGS&r%qM|iH26tpGiN2Ss5e&am)LTumyC2&g}>QG4)KzzKtgEX
z0K!(kTb#6qM3rZ_NQ1W4(gHjMurg%I45x$OV?$a$ACDIJJfU7o=_CWCTLrml83COU
z!Rm&#r6?8AEm;<XoJvl_Wn5a9TQAVo5}L~(D*8dm(UB|zl@Qef@U|Y&yfkX-3ojaF
z{aJtgC{UPAL++NR(I_i^$@c7QHMm4ur4~Lc>+(d@BawH(A(5BCGPI(4n<^x(V2j{1
zqE!Gm8-nn|ybf~!$fJ6mXe*lnM^SRj^?(oUTtlnuWqhTe7h9UP`WT=?Ufly|*EBF|
z^9=(NIAe_!)j&NHLdPeBx~tV4JcTe*P#k#rmBs0a-Vp*zG6<5=JAM2Q(&c!RAm~!=
z{hTVLLRi5V0G(gX&?M@|bW%W196K<<yl}0n(L~<<Ud34^850yJHXAX;XkEW`1W`_^
zBy!{s#!#;nl)1nvNzrz~>Ew!q!7OSg04tJkB@q%f)Gkpaa>L#csG&B>xS7EceQ{fn
zjuYmMgaT8Rx;|~kNX+A`IBHIZybOFj+|SE=Piv0rrDPW9(UG(an;Wb1S`EGCHsK2`
z&R@Y1t>CSI!Dl_%t8B15;36k$T}H$#bYyBYj}VJ}Ad)h!SdWHa#AGS8&Qk8cZLHcJ
zY7=eNFaj%R*%`cyB~<WwDp58Q3}N6vhw+FgOe}G<F2AXw0S3YuS1D7r?jYYti(*}%
zg)y-n`)h!E-NpnC9e%XI1bN5VW`+?cc>QgtZbeS`z_BeRRmL2e%YHKgU3oG^6pN8K
zR3I!NB#6SOh8xJ7G5q_8n{1?jJ!A|?RpzwhfO>4s)f#g;f2p2`J0L!=D_TJtSu4Dr
zc-ClK;3tX6ecGG#9~A*qC!iQ@l9sTjaSAE1#~>*Odrj6~EHoAZ))O+!d$NEcqBDUb
zXOA>%N(&05!7#pSs(65Epmh>qP-%CH;ZfVrdNEk+P<R*QiN}L&G??&^2G8_n1C_`q
z?Z@dlfPCHpIzj~#2`RNRjt}VQ>X3Aps<88lz;S>|IsP&T!&&~MtedM&bpk@ls|Axu
zB<uds=B6x~bYa%C8HKWD^REl_-~u+BP~`d3)k>zhYSm8}1RM&hnrAl|hP+``(6~+6
zxB{=4TFzNjW>i}c$L~pKLg|lb>*>iXcc75MP^+OvZI}qsIIg6KW%)oSE2R<=prxC+
z1YCHyX-Gye(DlHNTD>kM64byb)^Z~7a91s{*wbh@m?dK?v2V3dALITf5L%B7EnTEv
z%SMKG?pAA~Fu~Hou}SZ5BCirGqJlvhR|xH^3eUMDmWSM6C_*qu(q}#RAr8s`m!N46
zXNMA<@tj_i2F2Q>>EGHM!-9zBsNlzJEkrVh^yub_8&ne_&7}^JhN!m=&!*yY5f~R-
z7}3rH83t(0;hF+T6Izyb0vw;n#;OfX+L2F~_EDIDMJ<+EDHKB%>Kq*s7cqbZ%h7Jg
ztPb9awP<Azl5?2T;;fJOjH3VzkvbB+VT&t-K_5~>fm6Fq24x%hdXzDDkf=dH{f;SJ
zyDl-TTG1Z<CDMBQ<9pRrUXuB0D&>#%D`gr&OI8HRH-V2$AJ(b2T?n-W_CVJ=(GxH+
zkwcQWl#KL{gI7&92u`r662MDG2s8N(&2$1lsfv(yX#(lN#MulCkqXU<t2%-#i_v(D
zgkx0#1kPAviPrj{#xyH-=$yvu5J$`ffHv4rFydYpuM<m+(2YO_f1;hJa@r7Paj+({
zAzYfGDx-$nwXu^i_u<5Ap|p9=%owu5n4rmr!fG}ECAZ;Lwb<A<fk=yrwuo-kNCvpz
zzLP>!g>1s2H$JeHyJrEcz9*6#w|yCG@uo&MU7Kg>T8lLuy{%_X>BzZc*fIc2vpl#p
zpw{KDwF6vSosd>bYDS;5EEMt5%PmY^2;sTVs~0dl#GauimE$@F(sw1?bk_XmC8iI>
zTbX>iqbhZq8r}o%7@&AjnZ8tv%Z>C=t(@<7NB-(VkV&O~K)XXX4>GL1TC1!h*Dx^1
z3)%kevMQB^bE&;N4^z}ujYvr<Ds<tO3|*x#z_YVaukeb7FP`9wITHuv9Ztp~U(x#D
zPN9pVLV2ugliD)fHR8<|ntCyD&gmQ8QPdyfG}SCKxASAF1M8B5S?;r{-e%Kn)wHn8
zqQ}S4m9;4n&!-&vghVral~+1sV^SKhX`3{*m!!|I_GG1BY8uwi4)I0tjfOHXVExyj
z)WldUJGfoVAXeGdD&`pKK+I@E41KJ_m#vf~&s{J#mYAWb^s-W93fu=84Xsn_a>cVe
z^O)<HIV20_q>bz?WX-jZ7+ItJB9%&Rprbk8UtDHcOB>fZ%2Sga)2OcG)Kn{JG;;h}
z6c1rAchRif<$S3wDfnBO3j+-1iOEZ9{>)ul9me|L)oX{9O_3j1IUtR#q?<?ki{+6K
z78pD!LQ&#@&<}U7PACfxMZ`=yJv?SS&n@H^KcQ2hG+JLAPOz67Slg2+bA2SXmldON
zL&)b!cTd`2ag&j$W8!;n<xLuA2V$=a3GR&0m?GOQ^V#|5-hEp_8>G5EWlQ0im4Rxh
z_$9VqPjZ9QtmS>oPv`ZG&UO?Qq$cf6H%ViEf4j|>W{^W9z0F*KY?EjXvjiCkpFVFX
zH`3cSw4RVB6({Z1f5|pV^Nb2QePWBF@|)$>#<^Bf-b5wq3kMII>S!?@ZcNQw`&Bnm
zLILG(kdaBlb}Z>Hbr^F+j(3Qf<rDK33=NfZ@|f$m{dA9M(04-4JqQEYcKF`cc1+s!
zz??~!ozYd;xUO^Bdk-wEdG?Wb&1L$|&#_%?KfdAGxj(*k+Tzt8I(FJ6A3S#2$&W58
z{rD5xOAnvlFy*q3HBA|~e!D&DKew0G&NovoIlt+UfuC+)cGCB@FMFZ*T+{gCV$-J6
zzBTQnr-$19W5+KV7tH-d)28<iO{<>q%@x~r7T>n(_J2)Ye#aG^8~(w!edeOMlb*eI
zZo?(#Hx&NygAM7^7nK%2d*7EA-+unT%YyeGE#La#mlyy1h#d#*`p^~0#`CXCzVqN$
z7XRckI~MPn-_Z1p4_(o8!VkXE{OYw|X})Xj(M|WCe{0hTPhOo~^tH=l_s1)jYI(o)
z9B+j^xjo+Xm%}>8_jR`H+P7-n=09H9w0TR{;V(TieaovqKjNHSZ`{~4{>F?W#^30g
z_re>~k2rhF0ZZ22HTlNPFP?Jf<`+&`J^sd7P2=|+v|{yNKG=QUU*1=^;I3mY-~945
zlh*$3k%gE3?#6|$-nZ_+cfRt;CC_fTZNYzR`S<P%-u&F8*Y{qz@Xs&YI{D8p-qCW*
z-d{A1?;SSdAD=XN{9~r+g=aq0^rv$^z3!ncTW39T&K*<t?cEl=@VkF*cwy(g`SHCw
zr~K-iPxoH%#;+U3_kKISZ|@b;_x<iJ`}{*Mw!HAji_^y+`NY%@?E9A4xA(9EUwh>*
zU9aBv^`<u;dU2AxbY-Yt|2)rl?mcwY3vV1T|Jr?Bi(Vg}(X!%?O>@q^*etsL)gxx_
zdTsXFU2hyV|Eq7DG3WKYryV-J?~H@jemvK6!HdVnFTF5*=Ibv`pLYK*%)IfPPq%FT
z%hV-H{?fHz^NW+$Y~K5}hVkG1U^2&nyY9Pj-uT{y$+P?3H}5n1wywS4%|jbr-}{Tn
zf8O`slmGncbF;?x-o9wppSLa<|JY3n{@)`OFC2g6lS?1kGAVc4$LF@cctn2c5pQl=
ze8G!%OnH9qm%H}uyeYZ(<gK|skAI@`8+&ty?fuVnbKm&ICl7hyp~+ouKJu^mH^={<
zma|{~MBBb+&Y1Kk%KGZwKQ}!8&_A=ze_OY{_wv-2Mc&wZM$4~0ynX)ohYwhE&gYhv
zH+LQ0aqZ!==YMV0l($`U*V_)i=#I9=v%3nVv!_g(d(7>f#nbPcJ$Lh6H%?l+>)K`C
zKm6pwA6r@I{{F3!eE*i~<(S_cQ$FT*vztC}TUYdfuYP7y&zfrUd23qA7tJ}KbkUqI
z#NYWpKWP5(|2Zr-^PF4lnWx-2_rZt#(g*L$H=Z}?=Gkw~|4iqdFI)NQ%X7`X@v+>C
z<6lm1`p~UCzgReT>a!QmUHZj~zkEdVM?XEgd4}zHcJZ9Te>7~J@~cI^?|gaV#?hC5
z+mL(tw_B&*@SbmX-LSzlYuU;_5IJ_zD-Fj^nmh8VWm8(Fbluvr;)aJ-@`Q5w#Nmf8
zT)T5hZtWv&^Iu)Yjo8+<HK*_BJoxk-vsZp?)uC%wJ#co%?v>NhCs)SJ(Tqa*v0HnS
z(|^~QYy90gcEMNP)%}65_R4u{4lLijW*`~9<vZzn=bUJN{Ou#;@^Amsqz`=cCsSvh
zGM0bvz9o|$e0ct%U(IPqA8x)`zWU}B#XH};rFiN&JIua)ru|RnH_W<e;b6L`d{_JF
z7tfvF+*+L9vL;!uWxSL=dBFRUM>m+{59PUq&Wrb~e)YGN=)w2RPi}ed(OutLQ0cg8
zJNJVZAKLN3#p|zs^|#+{yY$)9noc<DTkmFMEIrSt96v5?tE(bC>s{kT-`ducxJq+}
zJGv`5>FC+++uveZzrCg4hIj(`M{S9@qGk8usg27%{jrvh>^``3(!h_BC%)Uiy5s0V
z)2Zo+4Nt6`((skxp|{DRMT?GqzdQ7^kK38?Zr}Fjfn4$VL)RVt-fMF6(+0QDHawPF
zA>Yhh{@7QSx5v*dNb}DvI4W10zv2AH=FHn&i$<RMt~~hqHd%hcZ_1aX((=SrNi=VC
z(LwV@hx6C>f2rL5+=9uU`?s&mKBA{Ex&L3d5HEgf%IWK))|aaD4qxz-E2c$fPAO5o
zqL#1kaUXA}$_F;Bj~A@{Uh}lXeY0@AJ9>F?<k8ms@QlK+8<NOXm!DvAJ*P@*VRX^K
z$+Ax$Y|nl2)<!q5u*H3|Z(9G+)%pGDC+62yUe#E-e33A(A6(ful9+GSmaN#_QhH%v
zZux~C)4gZ=zb}`DZF72zZ(82(8^7ZDCh4T#+G$Cp<c_neT{&6kch};v*S{U#{#5^R
zo;$U@sZ4%pbkDqbqmLDaM~9=kot@Es)1!+%_iyi9G(C-5#-{LC+}vo!3DsWn()ux`
zbw5)EMlKUC?Pu1wb~80*L%+f`j4bbqYOLLMTbI<hAbWHzPmnGUvm0OZG2#1psSI>u
z{Nh+@tRWxcxU4L4K~HL4p5H51a|O16S@^NCmnWB=AQv{Y$)X;K|6{et;|mK(|G}(I
z?5Mnx4Z-u0DE|*OHOKJSZ!_;fY-`~T*@`GWnk|uAY#iMl$JJkwZ*^WIb8Y09T?-p~
zdgQp$kbEWTk+C_@isWaa;xAXQn(DEvsFs*&akXQggu}|YT!B{g6RaDg*<bBhSc-1U
z>QBf@jU|XaiCnSZVhLZ7+`WQ$kGLB74xk%_`e3&Fl72kKIQ9p8FhbfF`Sn<M?j^mW
z>{tLudV5u`*GV7F<(;le*<<(v{x}u>Z4J`z1^NOf@5En@hm$R9>%K3*i%h~}$o=qD
zdEl*|x=`PHinE72^nIqINIUFN`_CmF_27TfRqJI_`@)^5rY{=Sn&IZA7QTKBqVN3Z
zy2I(myu;<I#B3oN7}8;G-bh|~OKct~rklJ0!!pwq7J8z(J;^gm#8{9S*1?Hmy=nDI
zMpu@jK71Zn%TLk|vrZq0Sy4)b?_fD8M?NaDT-s>iO(-*gYiy6lMC@@y2U&dy>*O(%
zm80|ko|JO11Vgcsj|)evykldD_Lr^Goi&?W^nV}$aj|4rXA=wWvZy_x@BHY^B%G>s
zjVe~YA)4(f>Vi}WHRG-5j@bfb>Ohvu5>DtR;3+}l1yvJhBFcjV7!Dvx13g1U;uNiy
zDcH-YhhxCRMoXQE1UlFtuZ);M&9JY!UuBT*!O478g>52b4q0}no_H`MJYy9;(DDsn
zryLNmxquHW=)layBN3?^L<y<h{bnmE(7C=58j_lsxzG}O3n(MR)Qe}mkDbj3WJM3k
zV#G>;e-Jx8G;aevGaH^vZ4Z88JzVrj>_A~wID!r;KA;#NXj@`3{fXTFVF+Sb#4E<g
zB@aDw#!ntN;UPJ7!A^bW=ge<Bd%^vWobkx`PZr#G+0!>)bmmu2{=koKeCm!@_bt5U
zvVXt%<Yyl_dF{0~9<z7Di4Wa4zUAf<e*WUgOP;vqojWf)<F;qc```m7@4M^bg-<;D
z&O0tV?T(-Qf8@Ojd}T$I|GW0i&gq?Wy4gvmA>BNzlRn*?eqq1{K^v&VfZ?GA1c!%6
zWKcmt&_PC!hDrz+m{tM;GKzR$V5X6$%1fZTgX1{pJVb{-DuVQQXA~a@&ioY=y8C{A
zwNKIwS7)5hfByH*{O?M3?W$F))>^gdxocPLbNcdokALcpZ$EI)^Jm;~*0FcI<B;W7
zJ^s`k|8UDaYkq$3OPu+6)ACOq_x<(%aLd*|zGMBCL!Not_a6A<ao0V6{4Kw_VA*HS
zc*{)}eB;?CkNcOWp5ko!ExSH@#!bha^Ycf~xM#zg&)Daj2X@+e#!YX1>e-{;x8bU<
zzxur6Z#(gVGwyxs)@L7GcJ-6rc=bIWy7?VzmfwB+)@L764a{@~<^zAkeDFtS-*VUE
zE$Qlu`Hkt<2lv5wqkFDuq`i+`+S2>B**7F_Th>UHJi^g{{Zi-o?XH98<@Ujb6(1Z;
z_u}a?89Xdaj=ZnZc4Wxd^2GX;s{MXhTd}FN?$g0~NZyub`=$AAd6NHA+Z*$*bPne8
zR_<h<YW-;XtEsPceY5T0eBeFfRyqEn^v#crc5S-pLOba#mP~!vTGpQzidq)fzcXr;
zAzl~`arTOS;H(y#H|xEY>~k-#7w)*ouB?uC?#(ts4tJ*K(`Vf9hQBPr5mUv*EG}Hx
z2vn_L%I{G>;}<R3VlkuSHc;Jr8KhK=vhGDRRiFf_lxj_E(84Go4TCOfdk_WHj!1_`
z-9>~D$+yXJO?>kfQ_%u`3xp=lsYz@PF0KfJnb9!D^5!JdnV&V0C!J<ubaZ<B<aEb(
z=*2rxoo|H14{>l<QA-Kst1V}43KqP0o}_sXWm#(w>pF(F)D5#kkU%oTy9J)K%dD{?
zHEdr8&ttXv=+LlnSYvXMd?ns&afXr7MRU`nm(GFzw=Sp>6QB3p2*s0jj%Ug2Nr%!U
zsN2=sdvY+!+TVC-=Ru#0E%DV!7p!LrW6)qjv`K5iViABdniL}pz?s;04_Y?b8yDPB
zjC^@4MI4XR8UsccEiHs%P<q#HRZ$|=NhlU;K;_Lwthf&Y4bE{qX=kL((?OOs_z(<B
zGHEdHioGFE$+v6;l|3w3o^d9FCfI0ulnrwmaH7z;fP5InmIYb1j}?uKJFj|O;HI*h
z{0a*ebDcgcq7p!TPamFSe24~9vzEYiV0?xG>e17BAfR$JPtjzl7p<qXz`Hv6Mv-Yy
zJ_{RY1_x@9;TXaG5>?nBo&?@gXoI(!igBuCl@MlOamSjS(c{xw@+Fc9MmN1w2#~U>
zM+&5iLBA5Sv^W^Jd96T7XYvv(^gDc6465UIDPfXKB<37t!~72gm_i^6JPIhEvKeLq
zBW$rO5Gbh;%qBOG48LjS#M1gbR8^;3#4Ms>+8UWrE}hPt7dOrzPNEMaj<|995bqJI
z6aklUqQ`kWsj*rVM;?_Oq7-YH=W?*Y0HLF<BCzM5Q!4?<V#+G|!@a=S+sS{zURM(O
zAp6tqMm5mIc>qX9RYNRwIv=$1%quE*TBb({7X6cS^b&+}mXUIh0!>FcrrsLF6le%Y
zdrSG!%g32Z@#R&r#$;DO8x4d!Eqn>d`_U+=s*)leJj+SSR@$&2WrKBQ9SL0pMN!4j
z-2>1}uuB<)d0W`d4Tv+H34}W}7h>pXI5E?bB^QzdXjP18CK*{E?r!0nbj?!f!ycF#
zgl4^Pohpl*6qRnKM_I6o>1n7m#0#d_H_EPR#(Br7!aQ-{0_h|HsFAIVqN4}uCJzn^
z52;F_D!)R2HV&f9a9jUSJi#0BDo0!3#UvGyhQ~bv8Q`o!E8>}f51#^xn2J&5EyUC^
zGP@yD3`G?rO>o4qGHo5{)R!S-Mb42-mw8Mq7}4=J7=evN>FexF8Zhr&sgt7trw+Tf
zC!?CHusZKiBDHbUf`)ga)DBWJGZ!Bu!W`L&Jd~eY-z&qCPW7nX>L0R)YM^EFJZWPk
zT1DoREbV|T`;i5tKstQL25hR9V8-On^CQV;G6F%KItr;GE2f^TKt2W6C6_~;QbGwz
z<VA%jy^ZVaX6J&#pJ#)vaFi+FtExm;phY2)IpoSTo_glVVa$&+P8H6c1c4+Zh>}|!
z^?V?cnT?T@v!^x@U<Ra|ldw>?VW&`yYC~ieR2*qi@TfNo8fdwwaK~_W<dEM25i0!r
zIkWd3N88OkX<WxAh)s|kMzC%H2cYO?V+y)VM*D(j9gYK)x&CGufXgP_B<&Vodg(BF
z1$a0@6)tACax580J^fKH0mmOlW$5J+%<8DZi4DNNP56UQFcLt`Lr=do60^~0FH}=^
z$NoxFQ6ab1f*0)u9TEg7jJY{IR$-$caS<NDZ6h|4P-%laDJ$n-=*yIC99U}dAU4Dh
zb{rpQulTgiLy}M!HA--{BUVuYAWhiXB}S(xp$w(Kp)k|`2sIc{ZZI~Lp7BoVox-Bw
z=|WOsV<hE(Lk+e9EgDdq_0#CPCC`^!vkprd#FG-v1;-M7)Knq!RPuHgEZ~<4eloV-
zcfS$+(zab_7E!CTptiE-DI1E*^Sn`F1K`>{6d)<hIX!Ao&KnTdTeLd$?w<OM9g2~T
z1;LYN(SggmRZPIaC!wKNHi~pvSK<h{2}d$EvlXMLdNPL9>((VStc*wUk)a?ieRKf!
zk1#9JmRf)zO~`o|W>v=%Egp6@X)Jh%UWPB0#piSVZq8IMsf|u9&&H?Vox95k4qJbp
z%|j(eY?9ie9XBpX7v)r9RPekP%X^bFK<K?Sd|%QJ+98#RjifCe>t@=*D0VRU7|(8S
zj;zx%Q=fFW%(YtzAN7F6p&e;zV~oCDrQpmDWn&{$W9&$!&s%8JXCua{6dtB0$F1|R
zY~p%t%!5j6w&3%`3>!@!x+JIS^AP(_j`XY28>1m;61=2p@ltWn(qZll)bDI>9=Qs!
zgl(T-_KtV4gHBz`5v+_j6mo?f+Ib;aol<AiJu-Sd_kbGd0`rcJjkMK;ndgU=^z~#L
zs9NJ7m-~Ujs@+4?5JqfS>Jl>7p`CLD8eG`Q8z?u`f<?Tqao(3{MT18kbsM?MvYsm4
zMaY8<qbu|^Ka1*EaNZ?JtUVj+qn~$4XImh*B%myNyL7hC^PRS-%*@7vN-4dlI$#r|
zoamlvAJ0@kqshb@I2J~_E^FlM&N43^<iV%DGk<$QuM?6Fv-)x&<yCi`ZnAv}^6s?S
zJJB_PZ;aht^!sy02m2|L8+pU%ZT!-aN>;_J{w=mBI2u}<hRpJNa!Qsgf7zU6*?3!9
z9UU5u;V{FnRJlr;W|Qe~n?K3cEl%KWG@~ihDQvtI-Npvkct+!<TqlWJal2Va8ltng
zBW4>v$dId#id;UST<1fJ6cexwLMb7VC@C{C(8(LrixG%TlZiM!5$HC`OJEG`olcE;
z;la{$v7rqZ7!o3Z>ZmyCM0sz<PzRW1Aa@#~&lAGqWM3Od+(0L(sIVz`>y-mfPj8-R
z7~%_pV+q8>dX1R+qyPk-@}(MU{LY*M0k{4XIzX?k2klZD(ZG^<dLaOAfR`gE_00Vs
z^_Q9-i{28CodT83V}3poP#$#hQdcuz2N$qfwkZYKM?t|WLsRZ`_3tGp2&lP)bg~Rk
z!P|XlSmjsslbT#YRF1drBm7?4DWGD0C9;<8g)Op373eW!3c$;;xJOp^+$v5H!NkbZ
zF3OL(;MI(Q6C~^fIE1=P;co-Y{bB;faNjDQQa28PNcnJ{V5FxVCF*$@oE`ZGM>~xb
z0jEFe3bGz62SY^=U;b&L-gA>)X8sV>Avo5UI+&la6}g0fvV>QVA1GYVjVND4pK59p
zn4x5n_TX16*x2o>54HAyqbxvUPJUc(oSe5#)t6zy9wb+_VbF~+lu|#>1SLKsQ#4vg
zu2Ptfbqy48t(;bi;8b5qFD^wGte;lnC(M?8lhhzRR&v|}V@I?lewD4jqoY(0T+(7-
zvSDK(#Ow&=#hc%MqkhogLJ+}u-A0tc1$>@MCZNA4%}K~v;xeHta)7ABkbJa)NuyYM
zWB*gi@_FK{Rk50d>lWSUl!#_Th!Io*>y>SyN)B#FM#Pj?ia-f8)6+VvAzYbHuu4Ja
zh)XA~gyo<lT|6N#L@so2%0&~B==1JIR+J-(VYR6jpN~K|Y=a_X0sv!7Mf;RNgKy!y
zrSuVjLEK_l@@QE0b5SXMp#c42X3UL=OKBT*S}B2gDNtuYx=&H8AC^2p&`nup*{hB$
z&<T~51e)Op@)q@1+>@Gay-+*F!`KPUXq>pRe)uRh&Gp%5H^IObAP^z1M_vYHQH5-T
zzS*TtABGUb#|d9r8qR5fUm7V7KDtpq3+RXjr2>i)w9vRc`$y!Tl*2gTP(%=<s&ZM=
zcW2UUjKD}v&jES_?g44$$QWT5cLzy~Z8^$tV>P4*M|^~g(M`OoWhmr>9v`)O2z7lW
zkfolcUS;K!jQC71Ew+LBdgd04u6Rg_m>`EsU5hdqXtatHwv|wDD#y-E5~qQ7TzV;x
z;6}gL#H55lP?J4~8NqzN!p9mLq76x-lt5}sQU%fVtgAJ_3o#zqD$)r}A5Kp3IIh@K
z`NUqCJmy0JHTVe<Yw5Q%Di9TnNSPzCG5ik6MjwfT2Qf5pRWeJ1W_J<1`O;&~X)@bH
zCm~bXP{tLRi)1rd1r4DnP$za0rGG-<G-E=5G)iDHmF6jl<N9>u2PKh$A`3X4Z^Jl3
z*wgDiJqSgPeT2aYuSCqCFjR~gSxbv@Cg_U~J!7H}f^EmbmJlZ~UbELA1nOk*%+H+i
zU77}9OL(9Gx?(qA9&e(sNAc*1vRh;6%?#mchfY~@Q9<Ss45T2e%0(G=Adj2oAW<qV
z5TZ+SiLHr%%tQHlZY<)<uN;Ec7iXd`IHHCjywqxn37SsVkVZ2jKv3tQvGauJWByW5
zO#UQ24S|4yKv{g5b{s|s(Itr|1{+p9)jm_DWAZ_qSG?2ZV8Fu@J#rM`#)KuiPV(t9
zN@^D+jKIR&Fa(AMt}I)UMHPgFmseabZX7SN_>(-KqoLtd_FC%nQ)rq1*Epkf@W<AY
z4D7-6QFW=*dQz5IBv^KwW!tdPKw{a3gh4bRdL5RONCto=>;**(po<q*?j+-Lk|jvR
zCbWjOzNR;bb16EGCJ56*g>)go2)CdXgs4c!cViS$P~jeq4E57TId9MO(IFwYu$+<)
z#s0*wbCW-Jf%Fb#j-V_1GvNi!F?LWd>!>jU@MF3?6O@Qag<3508J}IpTPy;Lg3+N(
zyON^(f(H@JLMaPUrx2RJH;jhl^^9STy9O@lXOam&3_(^xH`R3zjL&;<DL$v3ze$5I
zKxL_S`hf5P4hqW-v3=5Jno|+Q1T>Tm>WSN+QIm+PABd!;=EM^|Qm$RE{E=il-gMfd
z1ZQQ0<CVW)$j2Hehv|Z)@aI2i&%wtu^lefp77;GZWttZuQGke7$ylK_t_TVQGp7L5
zF<<h6FZID)r^u3od$5qOCfyg2AuV~jpkSphnnYgGtHW2UFFAz(3K6<8xHMHNan?|{
z%r`zs@dMaQ6*OWe#88m)A$C~K1Q~6Dy?2^fMcqUYnP@F|9C=50mlBlg%<)}bfNh{<
zmJ)}CCASdETCwVT!0};0im9|iL=#c!sPAlgazfKk+GS|TFy?)uBz9ip$C;znsnp62
zI)IbZu@*d7!6zXuS$Kl2tTibzf@}6vb|=AhXFQV>`dCsEdQz|H3+o2(fZx)HpG@(V
z2XAdS5MRdPIywqQI$=unXonr_3Fggu5>SbryGad;s3KTr$p~7JFHGTyhc{X~oCpqP
zz4Cb~WnAp123Ev?i;l+meCX9^jvY1Pl)!67QMiRZGfzABA_khZNLlPv*r&>kJeG!Z
zK=yNk5kXFxlhuUI%1bd+6;hzj2>`j2z5Nlh&##Ih;hY{##1JDZ5pG4#G-&S#lngw+
z=|ae%ZA5ZCr3GRv<|C6ld|(ouhCvH_bW7Gw{)9n>+!LSpX^FyX02H6JT;QI`drD0~
zml4qvDUP!S)MysSe4N*9ihKrLOm9s<aad8l(9k8RT1TA{XQxDCpc`|TzSv7e8v1oW
zUI@A6V-#@YStp2Xz~L(Yq~)EAItAwvLeUH!kyHxeAoEo`Qa2$!kMYt*>{M^OQ(Xsw
z91;Rb8f`ED1|wOujCJvq-6DObaGHX9JkxXDyCTL#H<TF+3Mi{tkW+FUXKWn{U`LP@
z?a(u(=$Seg&o-c*2S>bSJR)<Y&G7*g1^PSYU%X3*Okl>5mG(G*h!!H@%UQT8CjnY&
zA10BX3<Sc8;2t%rEBE+_mD7BhhOda3ClQ@QDRl56iT#R`M>NDIa=i@;Ma5UTzTTL+
z#1L=9my*>^n_t<ZFnm&x072FeyQoYIM+bqf%x8$wO8!K-lB18BQ41;|(!;EwdPcek
z1Ii=Hc^88oU6lgx^nR?&;)6Cw38k9`*YuRMYOj~xKOHv_D^y(IDN#{an2t{B(o}^c
zqb5!QN;a|MRuu;~4M`lUF-eG~6guFie2D3F!9w3mW@HGyr_@vv=44K?`Ee8ZXDU)$
z4u}|Opn1AdItA(qQxT~yG0J5r+qaM+eAJ8bqxV8O@&)4EPkf4-YS1awalL$d0Jib$
zy6B_`SNTms{4H_F9Ee$uRa)FRni6&K#t37c@vt4FMtp||VE_iMx)hFw${a#TqX~`I
z+Cz-TyC>l+h>QfSa;G6az>JjHW7ed^9wAah=RiLAPV{u1<!zNZpRnn`-flXv$GYQP
z{QgRZV=h?^()^xT_c&h@Q--KDb1o-+M|+yBrZ2Bo=-k=^*~%-Eya5TRtFGoz#4AHY
z_2*fCTE&78FcMS8+*u9EgAtYPmN|Ea&3Qz*pO>#YNve|3bY7_CJq`Cc`lmtiF$(=I
zd<pWJq-bsE^dxDqJs)DsjCUikgc^&&*idIJoP>zP*>SF7?bp&G58u&cuhVGi=rAg$
z*a%G_cRk4_R$2OZB*H4iT;s$}i#}LpyYOj_{xi|Sl3vSt3;RKq4O2wcfOLRz@)}Qz
zF<ZDO^{mHq)R^;AL9;0q5qot$up=AP%l1jk+uqW_Tc2$H>fFb%vwM;E*{cVKZDEl;
zylU#;`dodw#p_}H%xltX>m!EA)p!_yeRX82zS5F8vuHGYzBW|ZBSQ&l-Zn;_`Q$HJ
zef(<-xPxHq!uq#J$N8)-<1tsDvOdZdvR?-4=GGa;;XcJr-L!_>#(J=yrz`5K*xIl_
zM?dr0$?e%|mDeJ#r^B7WU7E(H=LMk_@<VCQ#?%0*)fHWN;iV=$*`b|TXOU7~3^zyc
z%~C|ID0c3x=PgX)^RRdmyU=#a(`pYd4}FD#?n>xp>YB{<<t?2F`tt57xQU*;hcAG)
z+G{umgh|(>%h0cjGxL_L!UB_BTD9X06!V>h)sRi}#yOTB$vF8p8}la1TroH8f1Q!n
zTH0?_>-k(!$%;zR)2Q-N(0Cu8cD0^6Klw1Pi5k9Y1$i${>S*z6lPimfmfSlV?%s?1
z54F%PW(7uwf)~3SElylI&|)>dnoJFOL-x1TbRwS}dXJ(a<_B1M5<O~4{_~2p_Eh|t
z+0tP<n7XTeW29CLGp$(26QTdOb+=Th3!WbuYH!PmLDcKbJYSnym{$`&+F=)aOMFqU
zYah#0R_R!G*r#?58?vQ31M?S8n2nr%T-Ve0jL&}Xp50fz^mnh?x&F*y^EO@GzVf>3
zvbNPfKE7++>4)w-zG26fM^|;XJ$U+IUH6@yx1`5^q54Ge$=(M~pWSue{``*530JSU
z{hL?UHmqFUa{u0IW*zn96}#7deZ}J2SKi!m`(3xqxo^SPlEqJ6vE=r<Uz&aG`o$|(
z9sjLL{pfGa+TpJHsn@-B_m!)T_}-2mc+2Bmx18;kZe26Ja`idK%{%#!<I-<DxZ|t8
zedT!Tfor~AS$67)_TsfyuKZ-rpVv2@eo5Q1(+{0H_Q=(X-}u<Y*~Zh?&A$JHxx2pY
zTNih{@$s=am#yLq&<?X_ANBaGY{TZ=_O{J)_fdZR5oQl=zBqmG*Om0Vk1W~$rLC3y
zU)u6M_tMrEm)&#0)<f=j>f47txV6@@dh1!~dFOm2ed(Ofw%`7$uFr2cu<Hxwt@++-
z&Rg@AMK68mRR_HEt^@aZaPz%OZhc~>y|=uyQ+3Nruif+h%^TAVn?L)Smi6Cg|Lpo_
zcH6k-=L<Kix%zeMw>-7{!7UFgKj5EVck1$gKJK`UfBcR`8~^zH#as7(U2W@{b1Q#-
z!nZEC=Y*3k*s%G!-8XLje#_=xe|7e=zy9Iut(y;WTQ<L?`ua70T|IEkg>K{Ko>s1W
z^X41oKJ((GJ3RZ@&+W4Lv-Mq`+A?PcuGw3^J$t9ESM9LVK3nJR6`rs3DZl?n@AA^~
zm6j*IU1@oAtL^_kKeA}`hqwOC(kIS8Wa&Lm?bLR_iLY&Y@cAp-?|c5@_9xEyX!^pM
zSEn0J->YxK(O>91>zp&vm)86^ed*|(cYo=ePp-Ur^Q^r$Y;LV>`Psa^fAh?|#n(Og
zi9N6TpPycI*=;-Qc;Nckm5smtYVUPFyLi$1=darL!Dm0Y+dlue@VMo_SU9xtJ@Xge
z@$Oe8-}uPF;;94AE$*E^veSk&U*6}1%{wmIy7{Q;)?fc{*5=J$ZQ1zDd#YQ0`7XEd
zLyO${{r-^rp2u~-;$J`2-tz2IW9jD4?omAZjnDNwwdGG{J-OwQSzEu|dfAIlwd~Nl
zZ?Pk55eMj8%uUPr?&F%fyH<Q-hn8EvvGY!2*Ua1TrC%<2)dA<F_3K`!?0f4uH+H@K
z2lwq&?Du$j&HA0wxBv2cJ*yu(V9~Y5etgljC#3F)FJI^GSyk-Q*ne`5#;Rh^RgWFm
zI`QG17yazm1&f|O_13-aSygk(R=0k5)|%EgU$*AKo!70|Eje)U!bP{<xN!NccMa{b
zY;|Lo-<-Mgk}tiu-yZ8<yv7~4_jRjwy7_PIZ9^xw9NfQTr!9SR_rB+AZ(Lk-ylYX{
zF*o+M-u!;s{J`8@p8aLLc<~pvw%zr$6|OV1&${=7_SSoMzQne^IGYm8_E6q-dLv&$
zzoD|@jnD4THU6WWc1rKtb*D>v(#mx&jPJkOS!4U&x+Zkp`jMMjCf6^UcjbN$biMtF
z*R*}-$xHKVKX7((?T3D7N4>k(o;WzSbshEYb&L02eC00}&VTTihbK=Db?*JMGc$Mf
z{K{Te^MkvWo%*pOXPsWOOdQ*_=frvQI@dOi+hy(N>+QX(ZN;(`^WU`bH-B3F(v|~O
zy?XKM+^bhEEcWO>x#fVN+D=c5EP2&6ZeF#k=dX4zd}YZ_pTE*tzjSi)(_eHHKmNtx
z$vxk#EWPWyr!M{Cocf$EzGZp7`HPE^tuHR=`I+Ns_$_8{ol0NT`Q^$Eoi|RU9T$za
z+<J+|B^%!7h7LRUiFW(@W5?z!%)i`P>$|9XLEgDz=OwLe-Anz>lP6Csm^`RwLEoE>
z+oiU0r(FiaTlQ)lo%_0Z)!TR8>&#1bZu!={j{M@Tj$q5$zEb>6{*%Eac3bP`(pP=P
z+F$?OBihG~{(AM|j!Tl;ul!!i(|`5VWbWJ3C39`zPSzJ{#hN>7hp)K84nJ+*z24k+
zP4C>ZhN@2={5pG~wY_+__389GbFWBy{XW)v=90W?;q5I0yLGi3@zH@Lk35v8lRM{q
zk1WhrDSs1;QiX3@bVRGK^trHeZFH*r#!==%%n9~s|G2&Tai1Rg_Ak?CU(K)W%+K~?
zLftuWMB3dpo)kkJ`Q+hwzVB(a+lsco+r{5`*s^&y&8_d*I=*w?@XvQnzTA?ytJAj7
z{ct|jxu)&u!AtG7&H+1NbW{7z4_)6rdGus5*8Romx-0)I`N>x<O*)S1=<DdHugF$R
zWw!TZw#$m1?xFe>cIe4{$=s92Th>*I?xz!1yJmKpuFa0=U6u8&?kjq`8TJ#~ttYws
z!uMMDsLLKb#8!NT52e3-%It)d%o)5@I+GzDJ;wPe*IMQ<hZ=LeVQYPuF@Gw-uZb9^
zfcM?STAtX^CVbkkwXAC}1Sais%=sSIc&=x!+D)8AzLojox`pPLMA!{;c?Rdd(NpQW
zm38(hma9fO+wIPUY4L^jO7We<cRb4FJJV!Si}eig7^inq!+lvYv5F_fmNZ+)-1g8V
z42<j)XI!;QyZE>r7sD;1JF1g}-|Wja&Ch(jFD)inZN0J22L8S~FeBj*$`VUgKva(_
z3|b$2U4xX&DCCk+Zs7`?cC#twA5%2jDezOfaZ&n&*`?tk9Un6Bem`iDeau{AGNtr9
zF;L&1vl0FxeWZ2ZM$CsGnnNwUlSxqlZWG}K92!vRap93pa9lb^#1xj_c`~LM2)&YY
z^M~!d^9gIdgst;F=TAm9eiki!Qd=-=eouZGq7Q`=HZzhocagt2r!zgT`>BeqMuT(}
zryZafNz+(=VWEeogn2h_D%n-2MFl<Jl8o0%P@*yXjvzsv&&m_Xv5}6G^VXY*j1sed
zsMAq3nAH$c{!qJo%(#94pDoO~D>hNJ5KALJ#=4Q0vU>=#*(e0rVmwTp2DmjW@csZ5
z*|isl<NYJ|)OJA=g((I<?05=*Hh65^?hNYvFr&BlJ3jNSf{Zy;1_ipy!6$kkBsM`1
z8RT7;JX$J<@$tb*ISz`=6bIClo-LoDWaiA1&rk%#88nV~*W|Bi5#vdc5Z9CT8`F8J
z0SLwEE6+;eiHA!!?NaNLb%|EI<Jtz=v<JF{d~gxZYXE5QxN`M(775~3jQm1UiFMY3
zFdoEs;tI}F=-?92dWMy1Ec*#Hq9Fe)HboOrdWy$ZC}RAeDcAuQY@iRW36C^tM?^8F
zjSgaM0PmN%B9wagxa<;Fmc?gS*-po+#wbrR$!~f}>pDWiN$QC5F<!CwxT2i~5It-c
zgP{8I3RGu$KCbFT9#Y)XpZ$xoPu=j;n>RdoWc;0<pKZPA_)~6w?2N1L;&*;F?{U?Z
zXYV-j;oIMK?se<Gzkb8!<)8W4NA7*=mOI{d;D+^wZoTzG4}9jC1Mfcm#b@94`g=Ze
z*uA$Nean+yd;L|9Z{2wI@&}$g^e=8a`j&5>dcakOy}0pP58S)?{kPq^=H{c;Z2Zij
zTkrkW9UIo1d++MacN~4e)+Z0U|L)^%+j_zMcdt6(*|(i||6}jJV)OBLY&iOLpE=`#
z_2(b|lcV1M*(V-9@ZL4A-|2!A?|s`-KYwhGPu}(B)Au=c<E~pTxar8Jwmi1S)z==n
za`8F0oN&gA8#!<E{Hq`P{-L*>{np!_xZr|&k9Qpv+MD(149ucmQvBDkH*Q^;b&RL{
z8gs@st8M8nA#0xqm9B|7m16CO()89OEtXzVDc0Q<s$qVz`;yj1v7+sBMWe09F4@&u
z@@pFNTyaD3Tx&~G?Jinuf0tad%b)d5EKYlGoJE!0n;#|HoLFPH)A}wdvfAE7(!Fbv
z+%+*~U!OCPrN{Ct`GJt$Kl!Qjp09Of>4NsQ9eeDMu461YDs=8O)miM`a!lHLpif=p
z?sxa4L)p@c4z*d8dY>KXH`$}<rLB*qmd&ZK_4LweKDpz#8?B_R?-=ThHIe+rGe6gU
z9#2pxR#d8lN<6}hXBrXjYOnk|ahc)tGK!KBsA&cPKaJzJ0F0UqLXl<D_$_3iiG!h1
z_-3%YIg}atT>?syuj=8{#j^!ldO=-FmJ^S>%%<w0u#-G&$3#nepHg4M@PjaNxPndp
z;TlUlh|Kq8HrY?-KpQP4>AUwR&g>^^oZK8pCg?VJO=p8j*Ri5lJHYog;M*Uw{%|?~
zx{(frkt}c3TTf4~TroaeQRMG*21=uq8Z+k`lq6lM;FaT4&ET9vB+PQ>c!H0uc8r3g
zw7~0qB>i@NgM&inVMDJQK}TK`7|Y3QopoZxxaHHo>g!>3$g0p+M&Of9Sd|I%D)j{W
zNJ8czP3cNH$jl%ZN0^&ecT=;Whpg8+T|Un@QhRs+xph`u_%0mA^iaelG&=k~c3SpN
zc!cVWx2ufx(n<0aY1Z>xa2UFIJ|_+d43~l2_L82M`lLgFBaLile8W1ahbc>RF6932
zC>p#Jl&0uRM~t<>z}Z;iVD^F>MMp@;deJ-TK(uBoB4PG447xrWocff8#e}Mpv3n(V
zwiedvBr&ov<%s4^8R4`Vb`sdY=u2;4Vd!$$kzE!!M2lfP&J=3Ic^ZCDnbT;-RBtgJ
z_N~I&YJsxz*oY0S2E>oMqplJ+2s3GLHU!5|jt?<Uine@yzp1{c#777lcQk}F#jm%m
zF;JUgf8Gjo!*JN5JFi)rm&E`Nm*g~fW2i<*nTA>hF9?ZBDJQd`;FtmNg{T1e5D8rT
zgnMQKmOZS2mUxWZ=HhMuylJm=#>3JUE(pX?1Sewv@M)VgEYI}()35RLIR&FGg`4OK
z<52`vV36uaP00fZ2b3mXn-b?8u9pCA-j2C3`ii2987tV}u1tL)?P-d|q43AkO1d7O
z7I~6b2pFe}B99~q`ySyus#;<rjyN(i0eyq}^gn`(7^kGlS5}t`IIb+gNwqFWgBziM
z5sBK8AFUj|g8us4KWmW<NN89vr<PJ7?}CaZ;9y5;1k|df>VdSGG5M4jYG!B+F-zz{
zm8nw+n!9$<B((}$JjyVU6JrXGwi6Y^?gR1Tq;MfSa|^rFCN#;2>h*RGI`e_S3@L!8
zk^~s`Rv$9gpr3Kw4m3Y}pj)pMzKW3ccnIQ;k1&d-JEolKDp1dkASQy&gqX~N4k^c@
zNJKq}RkE#cs>g(*g$AU1)SCws==}obr);TVLmF+?n4(Q--X5n&F6o#ON9sE!g)4Kn
zaoQ^=xVczZOsM%lX+~1BrK%pnrtwqzWglGr>>=o2-ZD2F>jpuTNF5H->@2AwFomMs
zhNvz@5-8M^98Ss3zHk|NAbZXQ3W5n=6pc`)JUf0xAz=TpPB7F#v?ph%K_vg##3Uh|
zDVWIYAW@XiUi3whpx_j20^d{<Kddg7!90fWCTg8Scq-;1Pap4zt?g6n5;|qi(*|`R
zkRe#PJIP8&Qkm4DiG>k9X)uHq3D&M>q<82@L`_43bq3zL-iG8(R{T@QB6#kh3v3e0
z*IJy40LTuOdvLJuH8Jt}{v$e4d}K5r!a4j+K0JpJ<%t#W8zH!pgnN}hH8bW<V+Kzp
z1cD7<>u$@A;8YahbQHqeBZA-6C?$ZUz>>sN07=lV+R(tMRYqT<4{aCJ`KW{_Ntch1
zP-ewMR3K+zio_)(BtxhpCJT5yfwr`hUQs}#257Jfh%`RJxbC<I!ILVbZ%T#~;jDq1
zSwF7lu`RV5;M<v{Wf-@DDzSyRq-8+n3Syr~OmyrKN`#-JV={rB^`sXP7>adN#Yo_-
zP0xb1h>No;kw-dgdM9rW!Nq#%7O|IyCEtBe_eY6T?T05SfhR9!Cpky!wxc{v+&E3D
z@}+yM8EyCAr8<-~oY+A@)h6qi;AxdKy?N@mQN9Cg9)-RxTUuwH5A)rO{*)IUwl?nS
z?M|jRSmKbri{%T|c9lNKz22MfD&S&vsrI#H{j_1m|CE}u7-}+^_InMufe&fqF^NK*
zj{NeX1A57%W<cBecNXqkRwWc)j)Q4Q>C4h^O)_EqPz{rRj6&NTCx`tmpgFHkCd}~F
z^08K2b$-;9DmsO{7KS?G2iPIk3IJb}Ltd4!o}M}hn3P>F8CnH6XB<u@WyN)-ZXP%b
zo(vw-;c2E<JHquO8Mb2*N;e^`)g~!}KJdQC-bvWH9COMllQOJtHO@GAw1Z<2?3987
z49@adfyJ45vGQ0t<ZQ$b*`=*@dN(X-BMyOCUqGWYB%KqMeE_xspL)FnqZL`U4nBA*
z`vg_qVB;TcW$Fc{K?eYXg~7GsE%Lp!<I|&7V7ZAoW9IUPy4*?M<sqLW``r`PatfWy
zuqCyL*b<g>8$T3!X06CDPilh~!@+C^G%%(TEJL*&LS5+&W)FkNe6Yq+YiXNf>B)@L
zEmWuB30p9Tts6De3}5aZGX$##(hmUACNk@8=Ve}+oH}Ls8^~$nBKD>c*YNEOOUX^+
zm>QYkgNy@?JZ8=YweAAYE?adU1e+wdCj}d^A&yQE7Y0dJm^n*AgPx^7WQKkjm3Xpt
z)ChGj?@M&7(4|?;=JO8ID&v+-(KL$T!e+G(rZ7h{myh<UwWjGIwB#DR+pMaX<j&7?
zP>+(TI!>hR*lr_C6g6RKJ;L^44w=+in6NW;4^z&Llagc{2=Q#eP5kB-8Ayfc1<#{m
z4&%N&h$>*`fw;P*RzhN6L{0?fy~To{d?&;uC~;vy+^7SO1cHR2Y5@}=PNX1(O6(a>
z$%E1g#-j@|w9A*6Q(EW5F){N}NeG-I5f9OnpuR4E4+PUaVKJ}7<B~{qpY~s(^y^$v
z&lm%PNRUlOdOQzvsf=V^5*BC4(v%D$6QAwnc!NpIdwo;~ib&_UF_in5cRDsJPDZ^E
zB?^wbL@`le6!)bviS@>8sQVGP072p{^$M3X8ckw0gN3HDe3M{=?}aRe2Fp%TJBIMe
zA0)09Khm6-dZi@*FGnZ#6&Z~I+fw3~+em~^sc&#RI*vHT!vh${CCF2+TcqNwEvz1*
zPPiy-u&JZCz%FR!7$g&lm;lWg8#vRc0`Q6;=r7d(fYhWG#}{w#Au7`kyrCNw;HLkg
zS!O<J4GBnZA(MyXg%cSaN=Ufd2v@+8(tex%5T^u3gyZW~xIx|$+pPIAkVI4^S)dfO
zGFgt_k9P_|Lgj9oa&{%&sH4!OE^?U<c&3=AC@;M8g{BW=;0{wvEe`bee2i?w>=TeR
zWr1aDp^FmmE4fkt!I7YpptL1q$(2q0g4kZJQqRme%pts5x}e}_WAxxSjwgzJpNFE1
zmNKeXfe4_jEU;WN@REVk`m!LJlUWK3YNBVH7n;sJWM!WigL0ZmvUQkdPC=_PP)>yR
zT+ovrbnupq#Tc_QWp|MTToHH)0W=G<A;$}QuP{czEsyI*ANo6CNUvnzyn;^7HgNK$
zMt_MDLBunGd@!<2)5!9AVn&(WyGhYdrvmE|#7rnSMW__^^!J!EgV7l6P}G<ChR`av
zH-szuuShNeB1#BC@e{XIg7|qbKr7gUvNIF=h-Vy<X=^Ojm5Eh;EImxe7wM#ummn+C
z`zy{jg$1V}6&}J+_5CuPX4?jtO)~EyK8XZGB<#m<1n5divY;E4$fr#b-{FLsfnk=8
zrQGBUhJg+LNST9JB171n9Ehb;kq11=QE2jHOP?MTf;1I)Ihh<rx;6`e`ROz?tw^QC
zr}plMi3`)!$d`9GpoAPM<+S20A?QXb{++zCRrGjEVi<=e6l)v@g{7a$@sw{%kC@4#
zKMTG|>q(prD$r2JWvw3TH=*++JU(|79;D$z^>HzkETAy+D9_DObGk9kA^~|VF|1BS
zR8BMNPT3BO7e+XBA=x~1b6FgVEG4FyS5eU7pa;AhygsUqtcdBK=?=zAvLz5@kyM_d
z&Wu|9Zxd2m!a5&mk!-;sb{cB<d*O*17!3{(sq&#s;asGG-a6`1n8IZyklTnl8#-7Q
zO_tyd3Dc^SY{5ZEJvgxuyMD2+XO3L-1c}BsMVWKk1~B0PIVJ%apM)(9c!h$gbJ(>A
z&RwdUMhGF96g$!BR>b}0DG3r16!0jGJsh?1P&7>{J0N2?-XH}|G3*t6QID9AunI-9
zG}nx(lNCQrCpM^!>=NUfp{5Dp*HCiaOIl1bt_TwFdNQV{MW(T{@OX(-OQz<g6Esy6
z0xABb(?lq&h<KCaZhXNGS2iNCVg#PQZ7`JCcnoC`>!M9(>JTwX4+F1T69V_9s3s=r
zCtTu`Wz8|7xtvyosU9_)WjeFu!4n_PyhN`Y7ky=^I96(;Z$qS14K*;a)CI<z*Ex}c
z*;xia=Mg$74k8c+9D&5^h9b^gE>CRqaqM)2oT)~>A`{G^iF!G>GRQk>U;6aK7$rof
zW)>oTkg;6j6w35U&lIe)gvU`|Z;DCGO+YaN^kWf70tMP@P>&$ic*`XPFBJVqTqJTq
zY^Uc9icwq~q4Rt`0Vhm};}+r{^lD<3aWyIAm5M-#T@YpK{ifrIOnPY7+OVveNS(}&
z;0i{|TX`5P`o%mcACby9SccLU-OR)xP8qAIj>efM93&)FS^nz>aKJg{nqFS?jmniJ
zDum8Oz|}e8G~d7tdiY61H%pwHb>YrHj!o#dG*{A8DBg-j%%o|3y+p^m95}FeSM}Qs
zo>2w53yMCPD(j7@WiH8+L`%5J+z1U1mqdg57@CZ3Y&qiJv~)!NKO9!ox5JIb>^osf
z#`55cipMxbVZ)>v?~w>y;~hpJV$mf+#Nx|>fl>#eER;r5Q71E|iyzS}#T3n{3Nl2Q
z#Z)nE9J>a@q_m?sMh8W!EW0jLgd<6q){{DgVnKL{%jw=UVXPR`w}|nOA+&_pPdJ|2
zTM0*`)13^2EWxWRwvLqvV}MMQ(-LGs53lXO;fFTiSzXxJ800B4Kwmed0Cw}b3$nl*
z&tlHCpJBY5+eAf_wfL`R)hGui6aQWXl?6VyU;^m+#4}hWC=h`e&$JODiWlPnPgcg_
zVoF6YY)YQassM+GkCT*vLf&a`77eZ-Q#z*{v0T_79ky1R1HjRzN@@%u$w>$h#G9~J
z0FUmEAUdfjeDIfWLL8;@D&}_tNf49X4%q~J#2X@&KZkI%h(iKc$pA6dl9`GPVVtaL
zO~C7k!IRc0MVUvEptI5m%Gykes>eWd0`B&p0-`$!rlB2O!c3&rE1QfEWDFvnt|vgR
zprRyvnnL#sY@CKB9-qkCobZ3jCCIHm(#Rickj6--RJwE3c)_Z>WN`P2a@(nt1P~T>
zkrNX@&`E}C{jzvqtvc@$g_Bc4v@Y$(tJkFsO@c1jJKf4qo#c|0j75x`pdr&G_%MtM
zfk^0U795m>Wbl3`pUUx|C&5I%h4>(p@^K!4cm<w+$;)Cqq%12a82|AAo~u*|Y#`(!
zqYjk`UiCVW8Nazf7|k5p!L~hgh=RRi6Ph0CS;?{x$?@`&B7`G1`XX||rN!JN9gJEL
zEJc&f%TFk#AniqESS1y8O^`mSbxi3_y93*Njuul#a2oioWt<d)j?<Dz53!2`3=^d(
z@>p4*6*_ij^+-V89G>#ASeOvxCVa{WQnyXKS}Dcil--(0*i0mKqjD%EP%GAN=GCai
zr2-?1^GP+*i5M@31*m-8K}uIboLu<Cm02xfIY+WMnmfFYNC`<-qS#T;;v_msP0Kz}
zg8(ck8o<Y{RX%7$H7$%|A3(i{Noe~jis?zVgAR3+JBqCYQma-ogpXU9CBpq+$|lOX
zG2swtqiFe~sc9zwiQ@B`S73X9?-0T>jZv-JM@U&OM6`YB3A)AnmgR~*5?1A+x{hXk
zI)hmN<+xC|yz_nX8E6YlugpPb7stnl(u9x{v0fnECm1FWUjlc1B|u|^Oh=Hw45W(a
zQ$@2tHEQ;dPUk@OyUnaYhPvFD^f|^a(Ob*DwrQ0W4fQ81aX+WixiqEzZmUmVkI!fD
zZ6C@za@LU+Ghd$NoWybF!P%T*!l#Go5Eb9c=wd%=cjmjOk^6SU;z}xs);U~1?=8l6
z?@X+xJL%+=*c5XsousQfR@;cz@H5Wa;Wp~VHP-D9n)SInqt89o-jEF;{>n52ny9t4
z4%m0|8-;SKEAO-^{URJ2X82B<TcN3%E7I>svU3w1m}`o<FoAUrVyB%fY)d^~E#ml#
z%Yqe`>MOepz2)pGWDQ$E31hKP@Pk-`^b|Son#P@(-^JTno)g)qqK!HfmE&t-<2;{a
zMYW~HChE>8EIXys4^OzjC$chr!6oTQT+(wr`ovW+b`E;8VMpx?9enJaw0E{7Mwlk#
z0;%lG+1?&<H}h<$x>y4>IFYwhX>ZPkdRmJ>*|}a-8kJ@DyHxU1)Eh_J)8wJrerDVr
zfyP7)syvIpo?BvhZXfh*85|a*b#Il?u$$E`ntL+ih_^r^)Uw|A>|>xUPw`HqluMU`
z>AsFO;fs#qm~nRVwNPdpF3R`q$h_qHSrzMdP7fj8vNz;@QMK_^^MOcPn;ez*SNK_1
zRw#1T(LD4z_{Ltc*mwFlbnU&1Y(DrRCze+WYB+7sXU_Omeyc4=(}|FT{2wvncx$^Y
zu)y3dIIH*P{{z3xVRFHn)*Goifxe>0RqXI|jE2#veG4r8QZ^lqT@xd<(QMp~(F~Ig
zV#g(X@vPhXqM9{^;^3_hEm0oS$Iv#F_c2n9)~9%R=B%Zd7-K69r9d&aE<>nIO=(>U
z*2~+fJ+qUsuqi#Zt%@Bd$w7S%hVKo<b34TDtFOpZW?ABvCw4gB_wA>0hI;p4qkWX3
zUXpLJ&);IaQwuzY^;I3;H92ePpT6eYw@!B1J=K*u6SB*xyQb$JvS8ukH`vPS?jBuw
z-feG6&;9UU%|3MD_?+)ouUfg~^f%32w)(G^{h+v~`u#t@a?b55k8Szzsb5=u@N-u$
zd5j<a*iirV?E6<7viu!CxpKw3AMf7%vKyaiJ7DSQuP*-P69=sN&L<Y1c-Q_*H{3X<
z?T-%m#H#rZU%CIE+~2zNvyGdU|LWmKc6`@@Z!Z3u-rCAf-gnc=vnKx3-qU_<{V&I_
zU-{WDH2B?~owIi)3-YlmzPRYy<99CJ|Fpx>(|$ZVefM`>updp{S-Ja^uf1yBDaS87
z>r;<pAHCwL?16nx-Qk4~A2Rz`^7O9BYqDD!hs^%MgD>o`W&Ol{=l?S4@V`7FQGUNV
zwCf*k_~|9}4L|*E_m=h7?6>7lp3KibceM5Vb2~d88`|}K=l}AY<-c0JcXi9^f3^p2
z`Mb(XTlZY_{`)?C!}<3ecIg4X{PFS)FYL2y%MUyD-15UW?flZ#clLhzw7atdf3jEK
z0Y7<9+lCijJNqNIt+($!^9M_x`sWk(`}ApRI=0^T%{d1?y?Mu<KD~L53vS!rHZJ;D
z{rUTB<@5KgTDkSU%dzh#l6yXV%gJB-^rF)?F1o(H@i*UHy7lRumtXMo>tDU~nH!R4
z?>jbs&kGB7{eu^7-eu!&_Fek?J@?Ij@cxyvZ~nsn*x{%5os<8Znz{APzq1$b{8;|4
z_e{>;@|lM^&-zh+;(wIn%I|fjoUruPpB}RMpMKg_-?Dyc!R@d9Sa!e%51M=S2M@{~
z8#-p`OPg=&{eErt-Yu&aReyEaCHC>HN$(!tnVp{hLW}+8mn+<c=l-aD%U9dl?)iBe
zXM>J#pZ(c>Z3q5z_qGH6uMg%Qf8qXR?^}P4J@w2^3${M9Q`=>y?cKKZ{wI_5r+lEc
z{*+%-E?9p~zID-j_p3XL)_>ji`qp3H|IK8>GnXa@KCmd;|AAX-8;N`UZ@QLV@Uxv~
zakaeo%%3ICKDQu$;|py)&%dx=&w;=B)1~)rxU+S?FC5+W!2PXlpMK%k{A1qisXK4Z
zU%c~X`{I&ET8|t_Iu9M`XG}UZ(Ycs6-+M{@9ru2%y5+2s_TTcMw=P(H(nWUONe|6g
zwXT1MvnKlUb*FXYPaoc9|MS$uZ8>#*w#6<<Uvg{H%3U|MR8}|I4>+&rIN&^6cFHey
zOIQD*y}fH)_v#(j4Z3}wKEd|gbWGb}H=kgyy1u*mv$gv#eR1uV>bvKctXPsixpJqq
zXIGwI`&#>x*K}r=y}r}_a^mu~zYL+{`Tf=<&+m7A{wCh({#|3V^%t8yJ?Ds#PqqEU
zx_PsAUzg7Q{JKLrKEG}v|LM~$`5jMxan~0wy()iktiSC?Uq7PdtKT{`A%A<CE$>v`
z&fTB3es9?C=kHq7vi0QNJ^TF;dmeC7(z<$GGH2C9(tgyv57q8Jt<9eJK&$=g1K!?!
z(l;wl@Gza;*f76(ll|uKiFA+iy6fkEvpw(q=E2EJ?h^Lp9g*+*@ZtHsQ`aQBomDJ7
z?E22OXV*U0_LH@D^>j5ZPZs6F+5EMC#P!GNt8PBJ{_)p$)-SZH?85wO>hJ7d_q)4y
z2l6(@U7ua{n$eCAZ2H84MeDj2lDGEf_iK>9r0ue&uONS)Xggx$iwj=-)Hg5r=;Mcs
z-tgrl-E*Cu0Ic#e$3pfWn0@bxqw=oH-K<j*_r}4z?~NnN_B{Bq^uE6F`klM{a%rRc
zjia{H74<o7*|LxA)P3E=ZkO)3t}nm-s^qlU^IPlft@AIpIc>i>xj%h$u)puBB3b?R
zYcA?sJ@O-7J<X|~>GS%(oHE+m{lIYBZhKx~Uq9tftUmH*m8D_t>J3(_E}7bQk^SVV
zWnW-Purm$StP-jZkJnok6nnCj@=xtF#^-_jsP@+LLi^f5Kj&jT{ktao!rC9&bJ@v#
zlZ^b=+e7<)EnVThS+DS(JI@}@ztExaugu>V1K@(a8})(Fz<Yl;tDg7Gs<!)VV&Q0C
zqwn+G7qN4Hr!Zn;ZcfpC>Bn}q-G+9)cDGG^E3VHv_h{*!zbrkd^@{vW`E#dT<c0@Z
z`3}lo+5Xo&)VJ@*9oZ`1q5S2~jU;*Z7bnx*_WYE+dE`^JV&pYU2~KNS6jt}9Q>&`>
z1GdtTzhW#nyVzEoHtwpO#W}WTacnE|zBw1?-Kjh6I~ET2`+cmi1#Oen{0BXu<8T-3
zU0f%-(R^iNvNnrxwlfRag&YDgJMw6q`PuOUjF2}?)w~PdTZ1Q&q-%g;J*e=#j9EOe
zY-0S{lraaO#|o|b?LnT2W}6#k=$mAc>-U;vgL`X~b~aV;gx@{r{5)@SFd@G<m}m7d
zr`RMh`wS?}u|fwkbjEMZql;Q#HXCRn781Lj@z8jGmyw#m6jzt=E-LhqjwxfD3_(29
z+DhsqJOq~pWBMkZuBP%)-nv-+2t2HXvA5+yyC$jgZa&yB`j_7X`qDXgl2hg}Xk$O<
zGW)n$1Mk#gF2|(ojh1|+lpL4>L>Oi|p6+el!)Lg;KB$cd9=$vZd(xN#UKZ-gO3CkG
zJV9CTAOOv#rW6@x93EMP4Z>fzsT%XGEaME1Ib_C#Y7eQdz%|Lr_b?CqB+*h(#A^mJ
zg?Gf2JOcUIgr9#vXMQ*-4mfO(@0GZK|8nwf*%&$uu239n&G9yA1KgPxYI;Z>IaV#1
z4ndms>p83~P>#jy%rncg<U-cz6XwH-Qyf$OhVJFMLw;z)ne*u&Y=WWRDwcL?qjBwV
zEpy4F53D1<PUi67C(Ct?*73|!cKOJNl(ThK2|V0T2QXh|gsr&KY9O2?jlljeX)E~o
zu-TozDE&U(@<cc0lB9DeS4IB-#%qdS?s*b{MGII3U!NtMObZTgHKOG!3zW3tqAvsm
z?Zt|`g)7q+%uNNJiw_ZFnV2o1Mi3pLpx%4ii>rLb7^j@`)ar_q4$LgApK`z&Q55bB
z5FeBmfww`$r+B04`B+4wXF__`V>qM~-`q<Ft`1QO#1M?n9iBiwxB)V64_98shw`&U
z4cS2$#}x&MEx9un)0>ULql^{4sZ53);v;5kf>N1{K}4pAMGuFa9D+RA_QVp`6Z)f`
z5J@Bj(-9vqU|5p`@fcnnf5+#7!xV6~<wMIqbKd*zKK~u}KY7@v?*4}_{c6oEcfbFA
zH@)@T&prD7$JQTz^Vz@Hc=whw?*7Oz_dojH??3p|`UB3n?aA}sckl7v-*D9O4R`(h
zv#&kp=I^grzWyUm{rqjq?|JYWcf9+%H~+z!&wb{pt#_Qg{1Y!de#c*Y_qG#HTz1uA
zPu>0x8=rr2>m9ov^2~`pz5lAizIXdS-1hv@&u)C?u$#_)=5tRT_Q?m|dh^z&Zn^u6
z!)`k6S!DmqT_@i5t0(XH?AB**ddH7H_XqF4=i0|t-n;pZ`Om!X-XmYU{STI1eeGeV
zpM1mvyPp2Q`V(K|$A~swd)UgGzI*ctZ@q{4;Js%r-}uB~i(mcCAHV&WrHQ?HQ6ht+
zI`cEo?ydI}m;5k{W~aDx#}Ri()ejzGho5QbSFf>(TlSU3yInI>oBJTEBYoq2?Bq(a
z1HRU>+j*8Ob6L7+s9u@3@47`h*V*#!GW)1sP-(Ht_jvPdwrr60U8O8XZEOig`>KzP
zBrOkKLnyzn)>2<wZRZ;V^^n-pya*k{{C{;#HCY+V-Du;r8#-$3S6}0j8!hSR2p5{4
z$dVC$r(iMN{Qf;H)@V=WG={9>qjwhVAG$N)-4xB0r^d&tW=Bu3Ms(?Db_pdqT|rgY
z%5Pl#&<*gaJ1?V%=;){i)W5(*7e~xu4a9oWINhnWY7U4iFZpL6b2DB%c|TmT?J;zk
zp$vQYyVBd_?@K{#WeZ5@#mi2$NyP2Ix6b&Td=*{<>G2;<@ppbABhP{bPrX3G>5oo2
z1Isuha1@;-zrl-41P5@ar(Kl3A6mkIV`U(^u4pzTMk_PVpQT}vVUwiEU`IX@w1`fR
zI3&k2{1j>T7#w9ajMMv%q6FG_B6oTVIE1udHR6V8oY8(z`T*Lo2s44$LCV#Mw2bF8
zL#|z;VVecpI(%e{<&o7gm5^NG64&PVT1!-&9){7=o9)X-PRVNvH5H4J#i2)v_!5BQ
z2m~_(k|I%eyDH!q{ds1=Mx5+F8$D!5558a30D=AS*Nuoyiau%#=c0~EgCfv}|6X(S
zL)OsGeGmrY(wbKQhHz$eM$j?IdUA${27|NrV9K&Po*`8$%gz;jqC2@I?F?enNq}F$
z&|AMgE`aJUuD;W!j5dMsu^$n!%==R>0xqLF_WS{PHkpyIUpu2`t0++2vYLvH*wh!T
zqwGUUNPyDmh^1r%1#vvWBeOuVsaUppTfh+8M%kJ*pdr3Dn7P2f2=5d$GZdvt*YWtl
zz#UECH5RIVp)jdh3LVRl4;waE3sj)jlZXL+GEIswL4ehez!IT(6sCN9P0N{ZaN_GL
zsxg5^F57SjsPhpwhGdBzNWciPamBg#k~fORh?F_&yiPi@Eu)vBCbNx5ZQcC|<oF9%
zeTBPI*=d|!!8j$m1*7hGsT)D(wJ!TaIr5nYRaYK>Y?NYVy-({@1j#1iKyzzHrsJOW
z^L;K@M*zV;rKqr8B?Hg}mVTod`xHMT7T!R_c?=U-mx2Soxj8@?va*!fh}Co$7-oJg
z*FXY4AXw^aW#{H$H10=*l?|dPXXg*aFi~ofF+1jhUO*(m<>pxegoLe6Jst{X8@xzB
zza+^gKr{Dus<+M=)eL!YB8n#g<C18;3WXdoMqc1Ytpn)MlFWI02(q^RD7=>nM_Tlo
z1PKg#WI-u*2upjhKX-0!kZ9sK@uDh_!;GR%P=R94`|AbUn<D{{cKZsmE10#5SDaFU
zGooYO<d4wj6)ibZYC0z|%2@@Q06yv&y_y4Ylu2!Vj2I<z#FquCFn;SN>&hTAKmh{<
z@m<JPQ2|rYEgcv4O^-Q7V-MR9vC(wp%rqs7Xb7jsyHo;<NMa$Nr1IZRc$kYBS1E)d
zC9|UQ(uJJF7LJ!>>ZD3-Ld=`E3zQ<>oFUi6Ko;{NPGLGe;^la*SgBJCq5~9ht5?a3
z1Xa<HYz8nvXHaH>_&4P>6fLEv;HS1xpHU?0#jq-hQUmdBW-#JLVmX)P6u>wl`?xog
zL=A=JYUY&c+=S4)Z_f|ZSQEY7ZJOJ5s8@Q^S0YSRbQ;36hx^Nzl@Sp&tp+RCqTVjG
z>=m;e$52H^iY6<KH!~n_obgaN+t5z&v2dqxEh@0>0DK_mNY)ghU}-mTEPsCD<+c~W
zGz^uVD5HrR*In`?X&CWE%u<LLaLqh~vfGd4colO~pyZM`ywC-15&D|?j5X6T8}Q92
z!{cZsv4#24c4O-95RwJdsMxsCH*+~Ii-V)scml0Wqcq#Aa7EHZM9NeY2wa{^;POUY
zWrJRW<(@Z-!zr$$QCCx_s)%K#5>bqiN(i7oWTa%?EKLA1AeBQ5V5|TepV2~Kz=_F-
zR!NDeAQdkXC>~x>J;%*Yw^zk+_N*B}AcABno!5<iJ|B@9{1=*ZmSXTYgp*P{rXfv6
z$6`F~l{qWr7+ZBve1IR}p!hx^z{CU5Xj^1K2=Uf?o(OUHvBwT)Ox}oeMw&73ebl$a
zl|yKpa70=}1w6@gT1&lNllo{GM54R&<lA(3q<NRKp;B|@Jr1hWhjIKRg$AOU2;;xH
zdO<*sz!VxUW=3y-M7$l0KGW##AyCP>*7(MHT!}!7T85X73mG_Ki8jCk%5{)7&^SKp
z$GnM8*$~0%STjf26^)XO2W`D_d|7$Ch!uvth%srYtk~+PVmW_s5`z;VsBKk59`gb&
zvr#!olYm>!FClXa!c?2gGcN^aI_hDff;x^MStb1HZ&_PxDqW^_L<IhHe;I5iOv(XD
zw;k3CCz#=`zzp*eza70|w+Ax$TVaO7c6_sKQW%}el&Nei4w5k~r)@@q%$y=$4sIse
zh@LLLvVy^`38e<pEQJisn6e_5VkeP`imojAs7a*SK3!8Bo%oD8Gual;a$XRV&ES=p
z$(J*U1aee<A6z%xLgU9_Y{H|tY~@r%%YIq3+rUkGOBsGTT;?+<wv$1@>hh@>D59dk
z%gR>$EP6@Qc97dz#7cO%u%vsYc}B^7x^W7v)B+#><qL93t)?RhPmxqvDtN^zXxcV3
zJ*_c0GMecl4Gw(#bc-Q4>2SCLx0fqj3iPFdM7pM4BJ7q^Lf=gLLyd9;Pd6ni`{ZfD
zm@%{hTy&?MZEd<a5mEWo&x+}{liBS1m8xmnfOmQm45k2HVfAe`DI=Y3+e2vf;^nAU
zj+WcS*YHy%WeF#==L%ea>^hT=puqMpxh)WL5J=n9E#CB`H&dkBc}ON<XO`oJP3In5
zvl!@;iJuniF?1jZ3~xW-C)`uk%x%0QgC>`lVw<sCh*GDmRmS2v`GUq!DFvW=we(H9
zGX*}4(EZ$f`R0d~PJeH3zc=N7ZNit?_kW|RrJOzg@OO()8I<6rJ^xMbzmH9SADZp6
z|L@WNd+{YN+4!>Kw&(jF@w@*B@qaPe-_Jh(xk^vVeED5v@b?F9FUf5m_&>xyo#%fq
zJHId8zsKi47OygR&0qgV(zyQ!@qaVg|CKWMx6{7v`rmDeZT<cBG;X`V_WteA|Lwf5
zw9zZWzb!+*56y2&_i~(U{GN}!9QS{AXnVU&`={^IIe%q%8vmbp-zMX$_whaDkBav;
z+;5lUemnaAm)KX@>XqSF8s*=M-$t+UIA_&#*iCzW$6fKd1TMP&wVmH)hu?-%E`<NL
z;-+b~zso-j(`l#g(|Fydaj(2@A6L@fTIVVD$E6=Pm~&--2iDRzq~|;y=&C$AH{+6$
z1hgL69S?jnP<rEA=n^-r0vuSd0hc9swe;(!A0R_Xi5nL)(P0LGR}7>>a}6dw4}(ie
zCZ!HV)ZuS$Ez|jUn-*N+_IkR!m$`D&fmhsr7ycDw|67AE*ZY4>)W5~+cgLN!&g`EX
zlI-OCzYM=yuisCRZRsDO;{GmB9{;<;+fOn3>)*UG7w(ma{}034%Hlsu3FY~uH6^#8
z+w{tRM6oRIqbEAsZ7*!DZkKVtwOVXbm7WC%(T&*B8#_U|t`eMXdiSBOQGHa-%{7DE
z1lv|=Lkz#n@nVgrZE|O#gM9ECY_>nGZ~n_6tfG4G>>mTz6yZ=YF7J6OS4oW?m7fg@
zyeM*|E}@xIKDMa7mse?!=pXP%4%)dOC}PK(5)Nn`^CGn8O2mV%8htXS+y=rxHj>yB
z_k=v)%F)J!JOq5uE18>$F=!m)jd%f~%W!`n#OnX_`>zH;V!`F5>QXZ1Q4uKTttEO2
zH`?Tx#_%M&W}+wRnA>DMh8+6F_n6wrL;y(e34)=O)9{t>+6%9ZM~*@`!UErPl=V^$
zi0#TNH1m<MDjaD!F*V-QLrJIKEvfukFB3*E#^tebh7OVoAhdMEobns*6Ji?J%E4h=
zvHKn1!Ix?^ZH2-S5xA*jxlcox4`064%@99YVu(izWH$-3fu;v+$$MM1nBn!xh#=A_
zMN5MSB}rLo)+li=&q&NX5n)D8+6}e4Oj*A1aAiXCC3cEnG%jyMrt{jQ;MP`eruAVP
zvdovKp12uv`xuSO?y?B*8jrfOhK*YN-bJ*^?>j%h>rqj(RiRzcY~S9Ki0zny*68Ye
zs)K>&9=ObvMUKxWsW+lbAEyk|&rE*WgHP;Y!qYD{V_LoN(LY~&DlHnCQ!p_HTy$~D
zcjngcO~d;#g0K__5R|WQym^<BuG#(+Bj77zK}?(i0@~z32BD83hZ{1S%nL~@?Jwm9
zC_LSMz4I7HAGaKJDuTo*-h+a(R3ruFkLHW*uO4}%0ZeRv1}Wr`G5#_$y!-G-X=ah8
z2EbhHmltf~k=!NTNuc5Y=^9~qw6VT@dV1VD>Lzox#`$d&z3_{5mA#w-+IfwiO(9Qu
zC8ZbEKH3x-uXyh4Ce0wzhAUgjK7^SFCxVQwMsGlj92GVq1MvHa=r#yp3L217BM#cA
zu#4I<gLPht2T|}Y(#0DNzvnR(6PEAK#mmDMLwa6uu?JQRyC<cNkDYal*Bfv&ua^vw
z1Zz^pcWmh}o(K+F)xeDH4#YOg)LXB7Wt9;f6fs`raXqmt^p4ecL?&WPZw8TIn5|Rs
z4Q!VMg4&uMHyChh3yAP0Im9`*5pek6b<AQha71#-H*lMNWvF~nqaexj+8r$`O0Tgj
zRwRBDMCE(W6@&%B*ONz(ixNK|n2o`mUyRO^Dky8aFSbqiR7MXk5(kQsL1TwT=0h03
zFCo?&W3;!fF2jp(U)PFOX)=*zHIzl&#EDek_>sRQBZ>1lD5&!Oq)(RhHclBNa1SEO
zi#-p`Cg^v;a~33WQ4Y%|AB@<*o7tCz0s^mV*$@%N@p~bXsbtJuk_G}!U4>VZJQ4|(
zj@o$a$kYX?G#*l)k&pC78Q?5wWbhm9<j`$E6YH7c{BEY`7VX6#%l+^quGNXdBqG`H
z;b;YPvYU{1#RL*dJt9Rq%**M*=D5T(kx)K*5raY1L$IMPaWa98O+_ndI+jxR`Sfpy
z=IxmBdU2V~vBW8l?Qn3tQ^7`k!+J<_eUXAGV*5P{l?RqC^kxm}m^K$=n>gx`jp1i*
z#0PcT%xV%(6-a!Mg>LN*DpEfvo%whRRthR@fFEDlQ<B|CyNlmzbcDzu`#0VH&DPrh
z$W>H{{^#DQ?zuggz@14aOhSN~Nhfq5U=u@N1)*lr36qd$6G8|dLMKK<5eW#%DiCUh
zCOaVRo5b+3KK?Ku0bP|v1maT{8#XGiq8I@YA+WCEx{JWm7<|em?|16<1a{y5%=Eog
zr%s)7>QvRKkNeeE<UQqfMEkCF7zA?EEE{c-Q5ql5_dFN{Tok#Q^cr4v%=65E4L@ER
zR5uJ>l-u;G713^v-a0&>H1w#y*OQh$*F;wzY1Dh@P&Ja_k}QbQk#x+}T<8K9I_G1x
z7p<OBWCK;)PuL7mx><=GP$7KoQJ?wZZY<B-3B)uh+$FH3NP0+<CISWs>$5+m!n4oR
zZ(Q=RtWtF?5)w1&sozzCB?Pw9<yJ2y=WJrN&p7InY8#YD8anBo3(i2W+QuE6y7cCv
z$n)V*%ZDJm+)Z-0h0CEq+)3Y0O&^sY$i>%M3`fw8ag_O<cSb3{VJps?stoY5&JdlK
z4XgEf!h6fXy@E^>KpUDq55^-4Oqu!tsDE|Xk!;q3C8%C3!c}-DvD1<d4P%9cqyU|~
zJAXa48i~s(Z<tpzs-tSxk2jgPuCX~K-d9d%#*$+kV<(F&=h0OLY8sio9!>_kJ&pjC
zq%=*tu^JJGUm@JkP`C7B3!WIT`pE#9DV8Yok$aPxqquS^!`?_u`pjme(Q~ftZ)5f$
zcUm}EFFr<ta3`^owa6LP8|!0`(%0)$J-~%;RihSoOFXhoNqYN2UPrhxIx6nHo|IwJ
z;0PP~Cr@fwo`<LOYCbiZap)A)j0K|)A?16K?U{b6r9mA~7r8+hc+1^sTMZ$-3!gaI
z1NbP^3J5_(C)J=2Nf<m7oTFL^W`wNBPrM^Q#Kr`S*KCL*JPz8G7)D!+qJR!JGByY*
zwcgrKjf97#Y8p4nTYsuSfN+b1l>wZGO7*G)x&_Dxi7Pnj#J5CgLvnchkPy<Wac~Ok
zLt%>Iof}Vn_c>N6`=uixW3mIhgm$5NsP>BRstmg6INHh=$gQ^DpciRbQD12lOXErt
zQpKqGDSwE4PR4lBkDwQAM%Xfd)w=uSI>NoIs>YGxG%@4CET9F6-_$E&vse<-5LB`M
zU&yk0WICN3xIi>ct#w9=1QcJKow1C^lQkiL`3Xd-lIO=cd*y0KYFW;qj?T8MQn<)+
zd@Rcn*vsN3OjVcGJ)sd)`j+(;IL@Tv4Hz^c5?i1>c^sUg8;G}xBoaFi#JrvqkyU}B
zc%4^dW6x6C2E5h87NOT5*o-r=A*(ZBDJveD%wnpxj&CJBYl7wpJu!=Ld!jN(U1mFi
zAAXdBm#n-5dAX<M=s<?|Qfo-I*x(5xPNAv8b^5UCjSR(wHHzvV!g|ovx0;^x35wMw
zA3*OJ=TkoVxGN#`+_l&QRU_2!V6+wO*FDfE-8eWfOfXWLSIH%(q*-=&j)M*;8YO{K
zn^%0`L@48!-R<r5>mgzO7mHh~RKlPI%7;0v#%-Y@G>y=$tq!MFvEUhU=(Aa*q$j*A
zrVIT#b|@H<)RP+h%!K!uJ;EGQlgJv3qAV<7^zy6@))9@p3es^02!-RUW1%p^^XT&q
z#P*%=FhRAQat!ah&8^f>c;6G#1521MC+Vw)Rhvw%<Nn&rBGOa>pcL!=2sBiP*O8`9
zq>CTm_zku0w+eBz^W?W02}g1|g3vc(4LI#PRRRdk8bl4cs9&57NNp(27_zB7NK$ap
z>EX&dhcpbRvI;c;9caT$Mo0Y+$Crq2)$L}D@I<<{`&t$GjwnV!ydTgY{;#AI{6cev
zIsc(Ct9-A5`F9)<A4<!UV9_FCnTA$-LrBd~nwfg#+alxb1B$@3g9@=)C-~r?2ZDU7
zkd%b52{F|x0O<<B=@y)ChI+jB5>PY{7kGMO$=3oq9(Z@$!@!{++!vIkzns15*6Gt_
z{4=EqB~*5Z4=%(*t-<|OtEJQC=|uG-SF5}jph-kwG{dV+^hK{V&iHFU87b&la|W>C
zSmx-d2dVNjT4)X~;CX^RR(h{7m92S!=DRo$)vns53blZz5yz`RqPk8&wUa1}KLtbo
z2oxx1;ZE3TGUL8B2~{~jpb7f;7KT%&j&qvA54R9#TB+V@z-dKg5cDOUfgk5r(>Q7P
z2A?H`qgBZ|Idv`noxN9cpLTf{D9DvAY=yED&v1D{&N+^meK3cKiRdB-$Q0zeBZ(VV
zE11vl=xNKDNVJxE^<q?CvU)X(4eXe4vToN}we?I1Wunbf*G14MdmFnD(CoadDfTMd
zl76lhFjDLQJx9;*_My#t&0#hBV89FMO=Xbj3l$EBxQ~?q)GZ*l^q~*F!FaT`Sq`1M
zgb!N=X`+KG95Y_w=!sk7;nZr)VYUMot#q2H5_x_!{FEl6kIs*bbI9-{@u)0E1y2c)
z&ab5}5j?2M&_qhB^C^hXKaiw_qe<QNBY27pgn9r-w`lGOjs~WRbmR3PE_6&Vv{_B?
z9K6bns~ixeV8Su1*>D5EKoE_4Q7uBR&xA5GAuj-D&8Fk3gUG`%u;C$MEn2E{ExwwU
ze}%;Ms-Be43ZIq*9c4<;Zvd}{K#W<k0mBl{_)wED4GG|M)!hPzz%ZB6^l`8u@D34N
zZBAK%(lNtIxB6^tw6<k8un{$y6)NbWF{e4gTqK;ScdK!w3w5s%z$wdMc8>Z9U)4n|
z(E>_S&Pb?Rt;@dmhLrtdKQZ-<?*<EspDN%&>kR2$1qEGH1mH9Kgmpu3#9dUN>L;<2
zlAc46VF9g1IK4|Vas41NdY$`dJI&TW^jQ_8>`4zI39{zoa4_9S!G@zM=9Exr0oa>*
zNHb33iY74r<QXxzjdCJIYk^MXl|ZQ&_BdyZETPa7qzWnv`Aie%Jc(hg7IfE01|h3f
zD-Z{i9oOB5sFrVBC6<{gJ@ACT74hmiJm_pt%Ty#o>Q#>ZR6vZwD_8;wr+hS=f?zxn
z`Ui7aG8wJwOczS*=ogtqNTX|Mn$rW|#^=<qv3eP$1r1FKGe{*>-l~ITP8H-?eaBrL
z%y=2`tTlAhM8^+R8(CKhk-(t?KcoH~zpuRL`H^!H6LMPqGDiT0Z5h*uX-4dIE*cUz
z)UC+<5m_7&(AkSq$qOE+2Rsa691zM@GpkmHa0rB6m6?=sSx4G+y4S_I#?SLp&`Gg^
z<|P<3)?#?YMY{3A8(7}47cLl7C`vd-LpU<!;H)k@#RqPzt^&V|UFOtPF{^o;4>iNa
zgZd@t>+Fr8=zUM~-j09OkW%5~;*3t>W<D^c#P7gJ2xjA``bqj?yq^GHWZxkrG}_Wf
zDV(N+08?ICYi32&*K3NU6`_>INA|D7G-mnRF9E+`X*i%$sxK6paNwK97QDK_0JfDU
z#L3f3g@RhuN)D&s-I-VSiMSS?TGvqQQV(^2AjJ{1MtAsBBXrLA(z{g00DQHit|Rw5
zT20ldQ%g}DJVKt%ar*Idz<NitPi<kLgH~V9U<gOxTZQtWoIZ@7YN%8{*N3kS8iabh
zC47S}DA=QVkl%<4an%a83O=Z){=mz0It=OB(tLx1O^G`KWHcO|K57{9#V&L|eKkdf
zAU812%_BeDeU_~*1Jtfc(_a8w4~$`Am5O)mwo*(#a}taAV1XcnR1%#^1`Os*T`ZRo
zhDPO&tqUo9Y+RO$YuZLjjOO+<36&uczZPVoYOo4QQoSyu_;7R`Qo$vv51y0ZD`cQ<
z^I2J)>I)|05+(qxV8)I-mB5ID8|E;c%9qf`@u;NOf>9MMw$rz2IKml_<}_d2^h!1s
zTjvPyf!NT!e8@w>AU}nY_Sa)KW)X1?)x$QEB9wt`DPdh^#8&NvwBVaiEcQa8&2VG-
zmBTDJpfzj6TTU^&)T`@R<|%!TCq(OYoPdzP*$o6ip$<brID|>nf5T;|j+4!T)T)P(
zuHlqat8YI<y5ap_Ao#N+!FvEMoX{ac&2UX>TruY~9aE?^#sMnm5?}R-C+3LXonghQ
zLcx#>++pn2R0Ye=XGIOPMAM0i%-R^5GhgCU&x%lS>c5>v2*%kN<7f&or>r!>AUl-3
z@AknH0+FH9k!B`Ysdg~$bpgxE3Q||a2jlzeqg2bI2T_6OF=E9u%iyhJlJ4WA==*d6
z_k6eF;D0EO9kY~eb};1dyrG>>2KsremKr}xUAAmNkJt=S4Ek!xTE3E%$mGQ2`zy|s
zVrM<P%GRZ9Ai2oK1KNLCE>Q{_z9!fd<hW{;Q#y+GXfD+1sl?5cSJfr8F>{)W%^5zm
zyaUHWglS+fxm$<Mu~k&Hbsl`&WG>%_M_6uyWs2H8N}X|BtDu{4T^LGgY0^gdOu5AU
z6ucC%!AN~McHrG6(Gab2o}`nSRE32W^QOM=Sjq?*^%R^Vb62IOB8>vQZXyI1rV%EX
zt3Ju=rn|mZ#aORyPf$)<VqcV028v7J<izzQGLP33D}QbMY3zN8@Rmc^BcD#W!7>1j
zjCRc}>j<xO$#K#L`zR_%x3>^DeYY{TLK^hV<amiUUyHd&iOSTAy&?7oP{D0u!xK&H
zh7P}9ht8^W)dUMtVczz%O;6<*=WMaV72)Gzd}lw_GS0?QaX*}ik26yH5~D-$;|O6a
zrp~2amw3xui3W>~*FcKw=HdOWQb`_<E>ClH=z?3qcD=gZ8c5|sVm%z$3m^28ZR~74
z9;;%AK~@%&Z4Afj@~KODy)#o?`ljjlR%na7cUUKJZ^{zEd&RfSbkgXOE=%)!nmSJU
z4Ey#qStos)^_4jueX&v6EVv1)s24^XqP1uTI{N~_3Yh-oWJGU<XeHjvhbCDs*$bH|
zV7w?Qkw*Kj>GB?vjG`YD=r5ZGwL(`to;0Gk&FlE-B$t{`h>iNJ^sFM9H2d>9-;3jE
z*rqADb&mMm5?1zO6vE=TBj0YvY8~iQt1lTjR9?-^)_2=pP0hdQMyCDwo*OT|ef_qJ
zcf0E+m7AYkS$nQ=)Qjt{JL<&Mh3@j&e_r*<@=dwt@{OZT{K(+SZ(i}lhaTIxC->aW
z-R9P{PxO5Aq$eiU&VJ4;T7Hvxc+L~&fAjDkw$;vgdddfOK7HaRW!c2<th?=yb<1y_
z>~?NFY3;Ahow#xCN0wba@N{v_**o(GJpBHPr#z5bc6s!7`OD6}t$V?iZ67;-e&eWB
z^*f4gc~AE_^GnN4zh!ItAy=Hba`2+0`}FR{#Gh@sIsf4Qc4uF>y8pa^Ezcaj@~6+0
zPWr3I&sn$n@xzwacAM(XX7T8#K4I>ce|uo<$?wm)>a~e;-D^+ewY+=(PUMl_%sK0k
zS4&s!-SE|odpF#D)m6{jamrOI4qm)_Wnpmll<SxNY5nKq?e(8?dp|rfu=m3^e*BZ$
zU;gUe?dQCB-kzr>pUv;>3-(psUjLVL_r_0`cWnGq^7h7ai*IjyG2OUxnccYaG<p8A
z7gB!3b@Oj)yL|og6RuhFvBewLTzuL|uTA{$`(B-};H|GezG(e7UOe^T=cit?;rT;8
zx^m?u7cO6U(dsX(A35ia_1_#g=MRUSb^h-^bk-eLo-2ob=Ek;<eyV!T`adjMu=fu?
zxaiye`hyR={pU|!{E0u`xAua{jdI*EON)C?U)r|ur=|A!zigks{+GWy>8jr?exG||
z;`_9`>kg&NubR`&ySMYSH|Cc<vvK{`K6BMG2Yl$N=MGr5`=E)3zP6#z`KR@#$lLRO
zAbUSLvS#l`lD@t7o_fXJx6Y5w+x^suFYI}0-rHAwrS$g3f5<(vad6J78y6q&_SHX3
z-@f|X^piXLD<|$O^t?Ft3+7LkeIcpr>51n(d~SS4{Uc{RvS#&JC%t;`2Ty$arBhD%
z#vu##eB=64E_nWsHQQf!|LHHU|H@Hc;5TjkUoZIJ`lSng@ykQbeEB!$pLza;Bk_-}
zd^~>Z4~v%X`PUuGPx{w|pSbc53oqLEmnmys|4V-D!<Ej%-dbmRHttL&?maz`Jr`Z~
zwTJ(`y)^xMH|V%OSKse@+pqBq_eN*$y{|B^>%Kxd{d*JSs{2QlH7-bcw_Xr^c=xN<
zFI$!WtX*{GP{*Q!eA`uT7A8Ef;fJ62K&f-Zk7hkSZ`JpIbol|lcd~o_$N5btKd@nO
zvSM1b<F$eA=(Xkllur45vodSlxdWBvt<_5NbH(DcW!=Ajb1;4`y<zsv-P300E6-2r
zu8p3);$uChJ#*3E!pfUV7reaY#?!xWw>j$z5B3+jYu{^IdFk{8Z=SQ_;`^7F<oq=k
zcD?Gq=l<}(!j)gVE9zc(>EigcCB9>m71=aaJ@$gp24j-1XxYx;dmf)yBGD)Rp^$#y
z9}+ix$HB{|@95~+dN_;7k4BfTy*FC3_SKQn1qbCiE;u7M;i~(S!c`9>JwKXNbss3n
z6|3?chphVkfywR*p6uMc{-Rl1HWZQvj_dsNYu%gVwfM1g>6@!7#oyPHO7q3RO7n@N
z*u!_hdy;rcyrgH!;0uSCb*m<r%B@RwT)FhL>Xl3TcfK;XKz`rT*74wuv(COdH*x2{
zP}`P)XHKsyseNqS+3v8H>m!rSU;S^Vz4xw#XMgIhu4&J$E_6M&y2s_moaDc5ihF!x
z@_N6p_8MjVpI;Su?HuX(#Mvp|Wi6*8@>Lld_-%^!I(FSU`Awy6?&%p=H`g(qe%w6Y
zQ65-zq%;@Lt)-hQuWy>u|MTYT{<D(Ri;|`Fs#`vBYJdLf6K2fX_TCF-H77l~#8plH
zA=f!8TC(c0ndc?(oK=atF^$(e-??DT($0$cUS(~YsZ`_XHR-OM+dXNk3{1MTzH0MN
zR`uL;O07$t#c97{*Hs$40siU9=F->xs<VD;*NMyj6dlw3>B8M(k94kk<*P|gtti#g
zs)-wsei;$R7a7;wC{sSH<=b{8?<#HEnl8Dk87<*cqhE5fld-t-Sjv}HDx;58>T(^!
z<MD35&Oc)1;DoYUoZ!l*rD@OH8*e_o_J4-oUpp(ASx=__%00b2J^1VS+zIc!Ab0Sr
zSu&}swqr%Z@J7K>|DipXeUHy@5B5AR7akwm^2AA%$0v@NT=7@kB{q&rACma1XKd+q
z)yKN~dHwHu>%6wVb92h)n^~e)D(g<H*kWg6^=sy~OaGM28Te-5n6}?`mF#PsZ`Qwc
zNXo*yiYeXoO(!E`j)~Afr~GP>zPtF0Ybf9F-LfS1hC!F1wV!!cy-$ZLpw8eo;JLjq
z4qwck+UMM=nB~FywBIrU(YotbIH|9R{i-#*8F+3zzT7%j?~bKj;l9G9_cMsS!V<-C
zC9uf|>tlP2kMGu5H^Zhm&AZM5;lZYpP9M)JH`A@8{i^KavDAxY{#RuiW!<NIR5{l3
z##k>~;nft++dO=_w$rmdOr(MB_#6Opx+bY!o?!~8Z|1E}@ZzIU<^*2WSz*<GqT>q+
z6+*I(HNF+db-^(ralOQpX9fu@&})WyMnt^Ngj;X*_Rf*m${KRk7`Pd(qZI>WW{lVM
znggHC^-Qrw<n9<6bYIs;JoVlp#9qh`-5Z1G!&HE>vZL)~jC|H&TPvx(5M0H}owI%A
zmDM8tY08M+DL;>l0Ld738`UWyxsglSK-r5eGecpHQwO(>A8eUA=(~&UD+FbXv{A~W
zx;W$)70K;G+>GM-Nn1grcHyuzs30VVJ3kss&POBWGyP!5dtKG(w;%@j6T^HcA3NER
z(qIauz_Zy!!JU^<o8x{}ClxPo4b7j9d`Fcj(KB7DZ<7h5k6nI{`J<z|d3oG=CYqrv
zk?kDiYbSzKZynTQl+{y%-4gaVDYs9DV;D2v3WY8IDME$}OR_jk^xeg0F;5_UnhCFQ
zNg|l!sir&v02t$wt-fPBCTLN>g^<QHkW_^AjMk?K2&;H#h*_<-Kn#ym!$Akf*<l8Z
z!mpDbfPQg<S)SSs$Yf}UcNg~~mYi)G4L7!EKzVSegrH`yltQ{28du(qEC#ia;nI}*
zEGTN0lI`3zL92WdaiC%MIL`dg1C&b3G*%kGg`-5Cn;{6MsGVy5z=Lu|{F?lshSo-=
z)_A(05cTho%x@gfO2uVh$L)}re4NH<fNKg~1xi}isP23uel;Ow8<VDT_%Nk1b1jCR
zVkL4LvD+I^`U(dpZ=AYq<In&7r4N4Vk)8ibYF~NiwNt-#<zMsu;4OR3`O3p*eC4LS
zZ)`jJ$$wvQ(HEZi#XmlL#aHgwd*$}^e}4Up_iWky<i5L4|MvE)FZ!dtKltdK&;0X4
zb58&A%NM=xrd|8C?|IM8T|eG-`RTuV_SDZj`+>jgS^nLJfA;#eU!C*Y^UnJ7v*-O{
z&vV~?>&(};U;gvooqN`wU;5xrcQ60$zB9k|(B-H8?)(pZ3)v69{11E1eEp`YPyO|V
z5B>c!*X+D$*L&XDaM58`pZ~}6U%qd}$vba;^5V;X`j^T3uKD%(zj%G+(K~N?^6+^-
z`R(~vU-{O`efRD;`Gpss+;-w=zuk55m47^6YJN6_wfZjKAFvRytSj$#Ly4=(=6JwI
z@c<pBCVk#vjU3)(xkROPn9xgiv-#zMIl#}jaHn@mYEkzzM_o?2Hr%aNdpep@W8GFy
zJ8V7O(R+Y2?Jwic*{*@dOUsux?egWmZ(v|#R&Dfe(|C3@o#vcf!Ru&~t+y5j*zf!4
zfHN;Hf1=1*(+os&`d3bp{&Y)Zo~IwX?y1Wbbti+z$d0&X`z7rf$(gQX*<A0spLfoU
z=py~rkzDMX=~6FC{@P1^u)S%{7Dp*E2=6XFK*Q|egkIN5Xq~Jh5N8n$64o}3A9r{a
zZ6Gw4{on{?Oq{gY46RKp3k6!RiKeh(9S1)ic-Og=CGzs$Q>};_Cmd&tjF#N-l>g^E
z;#AS&^&P6svqEY-IFc?iv9F|6FP+?cjGl#ZFa#nzJU!nbbZJ){3H~{XNp~tIW*y4N
zHc983m~9pgGm<{r<Hp`JqnWkJ(g#`5RYr_Ux{;ie(KV)B)P*-83vWuDLRU=sMvKg0
zN$HPW=;k={&X^(3i)&lqxscBth*Vd5%D8G1?o+ZdI~{;Q@adzDv%s}e8mONxooQX~
z!tNN|M@(Dne5Zv{I!k6GuE#RwixoaG<yjry>6=khr9}1M2;_)1&$?Ig7B$m$SmxLw
za&~&`x<z_%R`?E2Qj}UDPu!j7D+_SeI`vxCVG@Z{xpK@%7I&s&*sp?}JYP{V1uKuo
zk7EYP-rmTk(`rWYd?;FSdiw>W_#(E}fMyck+AAil!Mx2yC9V&Q_N#p((YpJ}r5LNL
zms;?`R}hkLr^_fM3WneSU$lwb2pBC-WQCTEM#P-w0IvYXmMa9>B^seGiFZY@V@wU=
zJmVSUPV1Jo>Im7vEDs62@CRbgI*NWUQc`|C#&syUbac5SEi=OVMz2`trP<lbFpjAD
z5O~<d5>vQwunrq~vW`HnY8H*lyERVCfiTo<5|PIjG9F!6bo6K1M|dTvvyNBid+5Ci
z8L$Wl!vfk-Q8@SPPI^YitiSPHt$%W3sN}UiV+&hCK*Tpixa&Vo3sZE4!RX~M7>R{J
zs8OM_1H#tF0=Umuoyw@pG@3VI|GLm8cQzRZbzFvU9s6!UX-D%%waC)0CDOXvJB2Kz
zs2Dqpmg=65W<UWtnI!;_)0;XffYPTv*snoK>#kYnwOmFl)d}RS9!Dh}5N-()bWS}M
zhINfyN>#3l*Z`p*LR%2r^IL_6R-sb)&Wf0N4UtDcjKRftOruIBy)+~wn>H7xO2HVc
zOvukq&BGD(0Ci^RimB_IEOr{#B6NFW>5v(Ll^Wf+Vng02Zq~I(I1t!T4ljMgJU@x-
zY(kY$X146U)6whz%oh3%$C`k;4eZzeOq#~(E721VCqreAgNGdLweINyUi<>6RBJ1g
zjaib&VJVijpioeOVv7th2jI3Ny+b}8#Qyp;iABkgtjsFc+_R6PCqSF;iEbQ{rsr83
zodBou`kTsxdSNw8g(HzwkWP=7Uee*iE#ppeA{)h$o@5l)iUx5NwE$KsSj{pODmZ1h
zP{diJ=h;QfCeYoSBb(iHE=6(Cm?(HXBn2$uG{1Tx>ZaX~ie-B=@;RZVEebhf)LH>n
zE#hKiEKPM;b=1`PQ8Wu055IPgowbn#P)rtvhq|bcq{7gWUJu7eG!|flIss$ieh%db
zyDBdaXOf$Adu(8$Ba~GXM_w$m-yV&1hNS?NF%5-02z@3mi0G#vgo23(bSSS>#)6Sq
z4J7g}f*A)OC@T?`tXkdgFFUCTrB6%4jUb*EJCk3#bs89I*I+5gN+qTsk*tO_Dy4Bm
zAW1tP$cup!uqmtGltIwbv>^`+!hzBQHW`kHYT4<I64^0qz*z~si|8mcA=hcj)+@<=
zI6{UZM^ag4fP>Wl^nC5lY2WG};3ELqmY7xBEK5oG(4Z7NWn*Vt+YMo^TW|p&Xyyl1
zhD9lS5(-deOFC;R2C{%~oB>UX68sPqrCfxYp0HbkZ%p!DTTB0SNTcJ#uh`S!0^79H
zY2SAm1{`U*txz!|qV-$Fm9u4t8k(|0hZz3Rx{Hn@F~dDQ0$<7N!qLrkHpx_ysgSpT
zGDj@4NeuqHPWD`a^;vj=Ek=(?8;Mp621{(4wLn%O&~V{#sqCN%gNkD+11jLjJ3<}|
z3#g7Yb*sY~%j(yA;VV=H89|+4Y7w#O^Z>p&X`*~8eGU}m<ZF?h_RD&TjxajFduY=J
z-QM(x_=My(ZFpjKi0fzw_l`s&y~WP*qpD{-HYrYU0|n`4F2OYr3Ok6B#*;<lvvCd%
z);Bd0<w}vokuzU1b?laMNddc-S3RbJ;}Lp8WIeXky29rTG`x3+*8XfP%93WHbO;Ba
zU!H7}UZz7$gR_g(>keQerHMPLlthOwulImNEMc|ot#I^7G*pfAj3;bzKqOtWWDS}{
zv52>_Vz|}qN{E!sgt^j|Bxz%7j*f^kXtLHS<uN=?(`moMqWu)PEE5;BvHmS5W+<}a
zeW+jj3pXOOLlbdbtdZ8@3nSC!9;0oQ$;qb6_2JV6^cXm$aUF-PTAUiCrN#1xTcKgI
zr0+U3(JHqHyJ-MDB{v_s>2;^&tvVjiGdj+gl2oZQ<FQBNSRZ<>Qx6JP_;WnzY5TNG
zsl(yxlyjZYI+`l^JP$ibSMQArtv^I7BY}h`Y9wd2)Q2o4$X}0dW&%}F!8{04NZQ7v
z%Kj+cScX9Pv3#+&nog8vb!tC$yb)xKcX!l)+Q;N8cs0o5;xvzzJuzN0XL_mFQX0EZ
z30CAloJG1;qDs`O<5ifRMCq3xP93)j6#3R^oTnklh0C?cwmaI{^fC<yN;mb<0bAfY
zvI=x#zEGw*Z}e)kyXZNCc^5T$d*L*^`1&4Nv^o9m6%^mco!6}^yEu-AP{2=y)L{T;
z(yGqUcjj0@q~`O`nRG^l2l?VL_6F8bNhWwkA=3kJi*Y&l$%2p8=HanhwFt!mE9n7s
zk<<2S&^z&*Nb5_xE#cHQ$LNjV#87vMP;UBvAW@{6yr72k5rVmLMhu`H(O#)6N0I`l
z4nU?EZo-FXB%|7n)tj-Vao}i^?_|P={0D*5eW)=~jXE`x-2;KM9p@GFQT0{b#KWau
zTugSSC|bB`6}N5yGg2pJLvg4?ItzD=BfTtx;P*pALosfj#$rTc@MmZno??ktv<cCl
zVZ^G7h$A`sstNC6_oPWU(i>HFOA#w_Cn7z@Zy5!-sy0nFpu>%t{Wzh-frZfHQJ4mg
z1BQSW(7L<!a19~2#Gs&Ki%Ln1@y2QC^{J^)1&UR}T4BWmCMgdnlYTP8nUMk*=liNg
zI-9X#9Oe#5OxY++WFexeC_pH@D~T5(U~y!e2(%znS4I3Vb)Jg%ni`bQ^vv1>(s%%M
zyexo$7v~h^gGy9l#t>~&Oku4$TGd^_@z)AtHynpmT)?>OwnK<KQ}6op9E~hbIPC>>
zDE@*|j$bRkBj98GVF+X-re9G82N+tbk~<SwN$wxWYM}v!%@AoDj<nv;I|KdRy223L
z47dI8-GHn@!41QvO9mtF8M7(1*4^MeNOcGmGH}K$dH`HFa?mDb!YIC}Wm~Iz!C0i#
z%QSb390|r^DEhotPC08J^idd(;UYd0V8OD=(qmZ<<O@KHqtDlI&)8s*bK)%@twI#u
zV_Y#RvJ^xHRxYYoKFQ+jq}aq>nII+Z?$bb0*ErxA*g(^2tcZRaCqTBmpgq>a`EeEW
z!|O6-MGS@IP|rx|U5Zg2t<LOJCw_r2vHFZ~+0zX@SPrTzg^F^JBz2o{2ccP9;FA#y
zV0c_n0JfSfwVXxX*}LsAZ2^_Y-4Mt42RanGL=S!?BQ+LXDYVLE`GIH3p827ZW_I_a
zSsmk5lB%uhXcrc60I0OVj0G2}QIb;|Xae7s-2-_@)eJ4hIi^(=<>Fn)5UUPDVKCN7
zgQ}%-o*Y=|gG{Fd*pkqGb{3(Y-s?$4t?*nDC#Bb16x3l&9AJQ;J^F=6Fq{uT#$T|(
zc-*<5FdUkPR0C5qj<a|W0`ZN+gL?>h;MeCe5xylUj+{6$d+5w8Isid<0_YFu0aDoL
zNkO0RVa07}3ewNd@}rX+PK7~c5EO_Z(!4SEp(;V}L#Z@FSf^wnu4Qt9_l>b#^P7;S
zWwtr?(Ocpm^7u9uXf~w7U8`+WxvTg99&RYXuvuV^gZB*BP<t~78gH3m>V4rER|krf
z`>^vQGBp!D11*Ju*%2Q!Alq{FHXzlfE2I?;g%JWK)HD+lz=s0&#8ycu1993!VCnEs
zI!<cD(m$OKbt(okbXc0GnuByCNM!3qDcu++iiNKTgN;Tyy&hXYa!^ov>NcmsLxzy*
z^_YyP=L+6u1WFSJch&_}Z*w4!sillS%s*ubMhppKdd$2nqrWHJXmTLbQ-dF+G}aSf
zj+s@?0hXA2?Qc~v9#S`DPn3&cTFe09*#Z~z4t5dSkhot9$Vh|`Bt~`X)qX0@i}zDQ
zh{!nfhO}(8!yF(fWsct~*ItfR3ANw^A`NGfG=!nFiS7qah~_R*V!!m=5EC^*iVa&X
zfoH!AYh~2lp(A4^NtkbrH&?1FqX>+VW+@HbBFM%j9<HK&%W=xUc+QE-g;>;<r6>-J
zW$eN{0USlaMYuSNit0zxu^Mf)c$M9fKb;w5gc9AsoIbG1=7fR3O8R|>9ly*(icQ2z
zejGvX>5`GK!Z*!~5XoN20teQA(z{-%TOwnN18nKqI>}9;r(>qj_KxuI36;VS;6qkX
zp7ayNT8)geuYymkRRsLsRf)u{*NW5q41hd?L=(9#%MPlmEYXGJM^6u-u}a6ZvELZ4
z3TXkxIg(e54{Qj@LOs;^SsJ<H%$DOwjWcaZfzL9BvmR1ywc5Yn#eX(|hRhV34r~xH
zs+_W{Ixu@hj+IDMib^ZN>XY|Ce~U6!X91iVtgln&$YKNqt!~H(dD;RefLm<!<Y_UG
z>N$f5(hy<Of!r?BXn$f1q6J!)_bdpJY;PjND_i|cAdEDmhangNhW!;z5MYluF`fv5
zx3s8;^lS6EUgff&!~c;QIH<jXy5QhA9DxsTH%FWKbXqe$)p{_dPPR4;WiYHKa~)m7
z3<Q3I=z%P@6!q{fz_nO(!g-oxC>zO*=Acs~W5O+`x-J%$c;2vN3`#jI1N1aj<8;6f
z3k#YVGMH}|N9~!rvvNS$a2yQ(O1UcU^dwpym6GTu2W_JFWGi^?=?tB|-(#~820y20
zV92xdR*P7a%4`#7{XtU$^pIO&s-^t}<KeR^AhPw6wn65N4uK4gT9=>wHzoI|E#ex|
zg+f*w<SNLpfb8??u$;+Wzyzt}(A8-`0eTAMHA4WS3kz(hc!_MlK}E6;Iat&wwMx*6
z=6(p@qRAZQ-Q#{rtZKk7rxQd=uvdZ<GfwYFPlm9zQw%i36%ehE^yzV!qAJSkNt)p}
zOq=K@6sHbaB2LXInw^q)6`&2G6r{QlqJaap_92`dy!NVSNXzLdRE}-T*p&i}Q;JCW
zVX7^mc?66i!h$@_oSpX;yJ)Ymk@opwtT*|fkAbP4^#EvzGBrXJ#<7gq5JryWmgP{M
z-DiU0PNVQnz<5B@3kcL9u72OsSpi`hRODis)Rn?Rfk0K(^8?C+Y5!=Xz7p^fPsTJM
zOcaZ&aTL-h6mASpMIi#%{YPy#?}BnGI+D%EW3eRC#ZoE&fq{E)nJkBi8%^a-BYjyK
zdrQPzOEh6vDF&#i;u#Ebs#;NmBah|WA_`3-ij3MqVZ0=*Nf(x}0iV%pCZlFSieidn
z3f;`2!Z=6zMqm~-f?}}L9_F*;>}Wl6&%hz|C68J<Cx=y*iWUTne)Z0Rb^K6EMYc?>
z!Jw|Eax_A6Dq4@Xld+r(aMbSlUx97IfXJ)Ym&hU_m(+ASfWFTt)E81^plY4$2w@8!
zg&sB_gZ)E{+r&8Ep4^?OHb5lE=gfKn^S%S*_t+)8AcnF)78YbW*HxDrTq!8!UC}eY
zFvfF6E8T(yl%oxN2(aa<rtk!n-s&l|ChrI_)CCz?AEI2yhBqWux+xYCfh1<nIMAt(
z7L1R{0go+4_ztX6t31GIE96t2$hH|reF9o3+Bn57(^tDERiQli1@7bYN!F@)3fhxu
z`6<vgB5@wBn!zbbbD8J<XI9~LAL7(bfD*@kt!I^xL1?+Hh7;^zwS!RZ)Mf;<gHaX8
zLqwsyy3lq)qF3hvI_qI|{3wYTFz?gC1)bQ+Cl4{tpR&>;*~spLCM<*SfGBQTBdDrJ
zH~{iPt<cUC?E_K|Q5Iq}wEbByxDSW(O)SY2!^Wv!MVLnnJXz!8DX3m*u@q0UtPRJO
ztk%a>;Tz4u(TR6T0_X&2Foe=5vKp|C0}F=mN)<)K*+^=ts+Kj10-D(x-+PU)-xSUn
zKhaO2`bkz(!nGxI3J~cz7)L7-sPKLZ%&0|@*sIu<W%W6b2Y5!0)FkhHyDb)+3GLgh
z^4&d?a1Cf3nG%`kgSd#XLZ#Sq3`4T3W$z^EkL7yAq{UxaA5o7hESJ)EFd&QxTXbPl
z$4wn8C6{|?oDN;5IDG|+$V{KU*K=;jh>i@vFoiDn5$N^ugy}NLA}{Ic(S`bmRkJ)p
zxDCwfi)N)VW(E)C-jqROHV@cr?pm?B#^FXxuBkynZfTF4mjSM=5Fc4i5!)KF$uYT)
z)QR(IuS;nwi>`}qrTC_rTWaRS(#OS*p|V+;wvCA`Nzxu)22%?20dCm9rg71;J~M7K
z=6a!Q<E9*xo+IXmwDr64RpA!P=|hE>ZXbolR^k$1xc1obG3Fk|fAxUqpF$gtlP^&v
z>XW1RD7psCqmh_Vear=ebA!tf4Z22L?~tlHrr;asD18=1X3+?FAh45~%o!&gtOoKq
zc7U}mZ|2@|Q*9m@ym@MStI}1C8`>7c%^ls^iw#y?mOh%^1DT-}#L{15X0s4x@c(L=
z8Gn}(?0(-C`g;%CqLEu6{zx|4&6u~98Vd_w;+k!e$Fww3<JYlVIaP}q@tjnbiOMEv
z=EdLWL~iZ&Rhg+}+ax!fMw7GDL$ynyCDwBbwiJ6Cre`fm4S1vTkW$TX=NfHh&>Q^(
zHZ93iYa`M%a6>#ir;lb#e_1*d@0c_;9GguE@|{`nRkL}5PZ}aavUW#pA=hO6RWj@g
zGaN&C=Z#Y^a_@DPdq;7@l@V@|uA6eh#7A-$NIueQgmrglT=H{<TuF>v&&NQg^z^zh
zSwti9)!U5j^K+ShR^(~Du9;rPP~{Ex|9XFTgqB?C=<-Z!*zoJAQR>E~C*ntKk}j38
z@ZfY)K96}LE|E1ESezMJ`}rBe5>2zzqvZTS*SoYlY&vb!OsLMm?wf>W%zolizlJ*O
z1>G>G6gT4CPyDp|-#@!^O7o81i}ab0bC3GPv{gd~PkCYcotNBxOYhYu%{z5vQv2-k
z=Wf39s9oFde9t4L#j6fD>YvYkY{~;OcNOoSxp(H`^B-BZ_?+d<_nJM!514y$7oYm4
zqds=Y(@)-9`o8~s@!rNqrhX%L@qy_-e}4Xs<y+?c&DNu)-q$$lkcSTX{QT>-ZaL}N
zn`h3xr7?5rLko6J`FhvRDUUu<nt1!}nMZAX>KEPHPTe`_2TQjd^*@fj`>2yHKBxFE
zgXc{8&6Wpd{;cs}`z^}~lN!qwbhkbCzvmpZ_3JYq`eEVVzTfp9y!D0AS-;u2xwL)G
z;)5T$c=5p}pC|IY7e<f0xBX)izIDmRChXm{cf#J=t~|p1fBW8}<$dn<JsWR-_}fR_
zzWunrdi~|!e|%SEU&pTJzA<Un&XW&%?v5*0ZoKEM+^&=V_ocf|zWBmj_M+sqJKtLP
z`sY3~wD)t@Jn@-({v&$s%q!ck`pv%6U;E8}O#05Y|5&!YxS{9XAH5Yl{G&^HpF8uK
zOJ-bmjs5KB_fERwmVJ}97vJib^3sNh$Nk`%uI)eASJ-~t$>n4B{v~(Ve{MYZj{n><
z`4-X^E&kNur4R1=^l|xX&bn#uTkRY6T^gP7#J3AOpE$Yjvt@s5KkmDK$!&k}ugq~T
z9%nY}`&9JZ-&}d@ANO9}{*k>Ka)*ES)4BH_Eb`XNpPszo<!dIN{DVu6-Fx0!=Usl-
zhYxSwv7xNxz5Rr1x;H(1!dbf>KJL`L=l%J>UGpw6yPiAZpc|e$y!)AxKm5M8?|DOB
zJo(D{izjSwyDC?j*S9TNxa+Bl+Maysnzr-q`9re)pexV3?Tz2$zVpT(K6KT#pDx_K
zb%UAz<4;a}_{SS_dk*?k`xiHF?>O+5?@s>qE!z)zIK8ZR(93TX4*J1c6Zjo;_)S;J
zANO3*e%L?mDID~l8xEfI@`hwl?$_<_`RFwhPrhiwA%EO;MaSvCzal#GiQ{r-K6Qdw
zzU-F=&cE`S*~h*3{^|EVf5Mb2uDPP~gqM#yaPr=>a>wmGJ2(I2tB*Y4Ya$z7{`7&z
zy>w;!32*&p`+d{@Jp1Ug-e6VwsT1@*#a%c2-LxNl_IsV@Z9jeX2OeHIxM$w`PTO0V
z-?Q@BZ*?z!=D4Xp`qf-{a`#)ScA8Jg(~XlOTRPbMzSQpap7ag(=aU|hXYTz!xu@^l
z-GA=q&MCb8xjPmfx9f|^!@D*Vrd;r;u1yzQQ+O!;s2rQ$AYXBx>btLcLdR(PA+x*M
zmzHPUw9wwW*;gLg_19g;zVMOh2fn!a(0gAzrtnWs{X9P9(PumQx1EtJSi5R!?t@o!
z9dzopLUGwp+s)Bw9ot_%r}(M!w|4e@VxF1tiA!_$ym*fJ=&ohO!yftmv^!3kUV8nT
zuTB*Cw>et2i@6Vd(+w}R?Rw<Y<mE>`F!3X|{c`!9vG4ZCiW9nuD~^-rIyPVW+A9~x
z)1#lM>>Qodwd?K~iyt%xx+hQiihJ>-d*$)nGm;he{xSN_^)GyM`t=9SS#R1F&fm4K
zYyJg)n0U_x7euvt-;A~~QXS#;#7Da?=C|+qVw$!;njC)94<)~OhfL1TNRQq1FX?+;
z{Fk2g7r)*yxqWJ~;EA7ipEBpPo`t`zbsqb|o73Anth{%zDNkPblPRZs?<a@O|3#Yg
zU05mi)vqW`{=hMZ_MO|j_23i#dFx@{+1zvb`8VsBGXFIz@+U^;51)7Q0b|9>?4o!_
z)crR;?kUJY$H)_H;;V6Us5xP1^M_|d(J{$z?}HtiN?)4R;FjgBydQLaWRAQ`(i4WH
z((!<NzI^KrGjZfP$Cc-wbhHoESKS>gUAe8895z&pKYr)6XW3y>XV_X-D*CHyqdg7x
z;Pe}!-N_eZ_wXV1SLU?#{?4-|$y3QB!+7v-#lC|_(pMZ$c)17Nt*6|0?UHEewXV2i
zXnN06(FqeyiN9EQwbU1FdS!+T4HTk-ubmK0D~ugBVKJA+uRTT=0S9UMF4@eab<+rQ
zh>y=0*wmaB-_n?xd@eai<k7j@kTB_AqUt2q_3>VbD(A*g<(#-wI)|;8zLX~&x})@v
zEsR24QaSel*VZ}O@Q3-K6^HrUqwT{(ubkV6RvkE&b}nK!uhU=aW=C=<_s4xiM*T;w
zN{c>sKUW=oE!}O;4tGubwY=0`muIJ!W;Q<L2gUFN=(Le@ZSJ<tdAa+g*nam=v#T-W
zCO<Y*EMC`k?7`m~wuRr=yJWcj#jY>8&vtPuQ=#MfyE>A>gNF@$@xcO*Wp|z1q=j;)
zLgx<ME9&g!X6zYargvGHp7xI(;+O+ayN#~8Hw>?n-^<obJ(cNQcaL^DZw+r$)HUAL
z4-HB2_z{^r1Dll?b(y;806yJWQ#gy6#xdM8$}kTr=F3c~&&*44m5r`Xtw|;`{U2mr
zl0?bK)S;wP?|eSZ2-Tc0#q^AX6OHCOoq^VVB+Ruuw|F#`Fidhe%l8d3^8ixI{3-Un
zC&$~kMLe_fA9i$0M^Bq?XG+*kdo`*+k3RD=e2Zr3j4VvWGA~YVyq~4xrO+G`iMNrQ
z%M`vy&o!q(i0;!@Q_dbM`KdZ6vka?|)`uQPTOFoNqhDfEaM+MJc|U2OE%|dSk3Bie
zUm;3$psZ3y<F%Z<NAHwWANKGZ=&-0LdrJ+ApCxe<<^o>96Y_>!MR?8yk@C+4=3xyH
zraoj7GWgL2Nw4ZNKYwZx3iCT&4CPgvGpxs~HKVi0bhRx-3seJ`^l_bD=UA*<bRUH&
zPD#IkU08=~@-U0xX`M7ljzFn?#BHHuRrcO;mYY@(%rzOTFJ&}MnWLHsPBw>JGAeCS
zcq|^`?p9W5ZC1-<|K@;rO!B-zwv6s&>Fn$tWfkNXCOKqrdkSwO4$l?&s83=p!;AJw
zPP`e~r*Z)G(kmlhmHQ=H%9HIRg=c=&z9M4v9TLnALGh!M{9@0n*hipSU?@XHY2HC8
z4L7b@FHzbgAwV%K!N#*`#Y&wL>Ys@3MF!^}BVjkeP+6(P-k!TvJ$DI`$XbCTz^)85
zdc8K%i*Gidf{vQ1JgnwdhC!$`4YUgjL->&Hl_sQt^ej%jq8)AdQB6?L{MZILO6<ws
z3AVF!JqBHXb{2!9oGpEd>8xhapC%c8L?W3?UJpsYlmi;$C)5{q%rX!fQiZHHt#s89
zVOoKzNnORM#5kCZ{KPyQy$XuB4V~r|5t-&)kfUoj2Ytpr>~Dw?E3>DM{H{LpGiO92
zRvvlw$XoXQc-zJozV*^2&wXe4KkT{U$e$5E`$vyF`^lXTp7WK`8Q*?+?={=b-u10B
zF8TA;U+mlc?3Z79`;zS|UwCB2(L1*;dE>Y<zWmG^M?Q4U%dek#<Skp5d~N%OzI^WQ
zj=1UNefMs7&n+*W`j3ad^tFvYzVD`uFW+<ezU|Lm^3dVSes|vDZ-w~Rwm<vvw=Vhd
zwhbS=@1?VEesK9e?mP3yhc5Zxw$m?q{n<-ye)|{yYx}cD+_dkKZD(Hc`m<Nwa@#N7
zzy0bXCtv)=_6>h|{fr|Ye&)%G4?pYM$6kENL+9^%{bwgUa@(mhXTJ31^B?5?$9-??
zIdbo=Q;)j%{4bx;ab5YS?)cxd?5REjbAd0%Q|_{b;b#`aPd09tWe%O~@+)UAnU*e&
ze?Pido)+8DH1^cyytdf&KG7XTR<6VB4e#U8s3~K(v7!8o=zrKplY?wOX>DdG-zT5v
zPNbVmf4bGjmk;HAsa;mPDZYQIsYb<3rn}T;R#U612k(8+$q$}N&7z|#>6Eyh94pNz
zN=}pEi52Plp_Rj{{ay2Nr=>I9F;V*xD@WbzWadymOTqhR`tz(TOU~%}#6T{3zHMgy
zSAY9Z@87pEqCTFJe_yoCj8u=+a)!pMCoS)Ou!LwP|1X603R)Xj3*JrUY0_pqAv=Q!
z&1*cze)4fvw5<OM?0D=)_$;Jsoruk1*>RlVf6wmUA=;xJN<nGs+S|PNqOja=6!h7H
zlFDxWJ?qF~fi2>k<Msi0dZ_hE$j;RCdRfCbX^Y%c;AEN`^3aM)dv$j$x=i_1z3?)R
ze99Fm`aeGRy3l)Ki^{x7UL_Z-R5fo^Q`jWI&vh0I6A-e*X`X39f#s^m(&4Z(#gHmR
z#4wys^emoDJTjz(WYbqK#B-Hxlo$kN(ug3YEx9X7*Rp6=r$f8BKKSfSi7&`J(sj2V
zKfabE#(fZM{xX-Tum_Op2;!&_Yjl4NhtAzIXlP|b{RvZo5eV`zPLGjaA}tN&oB=-_
zEslYAXT<iBRpluB1T+|vT%Nb=D7*B~Fs2P1*v}hgTq3>wQP5j_hm#Lu3m%G&rLj<A
z64}uY_kBkeP6LB70&iFrbf-wY<1j@po9n_8v08U$p&%-@4WfkF3#X>#=9vXmoFX;y
z-2F^->7_z+L1)e3V#|XPk+?N}h#gxagWOkFVHPo<R8i1d%R?iK3Wac+m5cB9Uj64l
z9SZf+oDjin@fze6C=9$vR;x79VU;O)wQ3%$wiA*_HYVmdB6jIAg<L_};*qF0d@U{0
z!8ca2DCKILUPD0u?D&rv9INEF2xMq8oCBm<x2PE)FR`96Kj%p6Pa8MDjj5Jd6z5@+
zPl_?qDOFxI^Qxjg)PiKHUv<1e89D+ADU!vvhwDBt?rq9+WvPROhxkOo35eLKMC=>W
zvh_(JIQc3_4N!-fjwF3a%g`2{*P4glMRQ~8P&o}U8%k||J)sJ9G=`;SD3em9rD>~;
zpY~=nBxxC8-bbI~Ob?*}gnlU=bp|z2h9wM-)+E)e!n7sQG`Qq3M8^t#!S{?J8kV#!
zZ;V4*{a45&(4y$0Y&&`;m6?S?Dz^}N^65a1`s_2O^pud*8!%okuh?Fy3*Md3C^t^G
zhW%(vuW^TULO?8=n=l!dO(Qj2cY#9Zgh2*AUm4IH98~lpS`--1t#ioJR*!~$l<xo>
zF+>i)ssY19NZ+s78-yh$w$x5PWkrE(u9Fr_Bd7P^G6|$Wc%#Gwqbi$fd^1-}loRO|
z*+!q~`P&&t^G;O~PjU&;isT20V$7}jMkSsRH$~@o#u2{QxDzWVxdNVmFbb$hxatx`
zb*aG(DXH-(*oM@a@NsCtPzsjX0TMP4wR{yLy)@cdM=$_y>rri53EWNE3yFF?q{MwA
zno-9x<E-9-V9Om?Ay~wL1<31F4QEqXkTewqBJp@A(;LdEjmJZ#^usty?VUiGy2zl(
zJ^wZxjP-*Xy~P#uBtsu|$cH^s^klS+^#QGjA;PLLDX=ym^7nD#=8m`mdlPfPO@+YU
z)rHP#Sh~R?bueRxd#ctuex*cn<LYoIrIjuoi|dL=XkKfwX6lJ7l=OPNcg9!y7E$qK
zU+R@^h7UM6DR)ssy@LxF6g)cq(Ir~H-+n7#&?4nR>#&-xDC#+-j0S@3+Nf_>$gm9s
zK@~5<sx{6oAKnrgM<v$NJZs~zK#V&IQb`{sr2hk+Lx=jZo{qYQC*VDNK<n)luunXc
z8b2-bpBOc6;=YsOkSVD`Y6<;0{JxgMQ^iG(=^R+~MdYor@}Y^YN*mg?aL=9v75$5A
z%*wqG8(mOloI(jWc*Kv0)InQ)YQZ`SzY64SLK1-ft(vC>L$*F+EIP12P+kmnaQFD7
z)dL!(A4A_ziO94`?g$uZ#|%)`9_E>Zi#Q4qV*yyvRx)Yulw_?Ufcl`Uf<2AKa%Xva
zo<)acLLiYRr_+d74?ksQaS|+va1qFF3kwXb-?{i+1@s=N(Xbmi&vH%>sq5t7wqd=$
zHySLBIjQ-;T&vOY0jOaLn@?mjNP}RiUwV_{V;`7d2VWf?gHJcwHT+<6km1H}iNEAz
zYTED)D(&QLx9PSA+Sx{x6N83}n9(rjG2;A*tNJK-uEY)n119bxN_;Nv)eO$NG7rzN
zhk|TlmS_QECnX)9P+Zc<O{--cjrxt_Ip%5Ry{0X^!!eA~5Tr5+UE-~=DvU>MY-g-&
zN;Hfv>$=yV{UVvYk~#=Cg3uw+HR(3Cuba&nD$sIkjtjP<eP|oW^HzOV9y7z(OuDIj
z#&NEh9h2{gm5yRW$7@j@)7nl3v80K4PNjsV2*c^*1}jvBlc<v>;YYNmhlbH6n0hGg
zsC43o%N8vk{WW(!&?Y<7htpghw)B@le5n;rw@CV;uK8YMSyKSseuFJ&TEg-lL1k<y
z41TzcT8sfbPZ6a&)6w92J5$Y@=%#Jn%dzI*$$k)NX*AH=i>vE!>bU5_@d#Fr<oJ$W
z^~J-|ud`so+%P@B$js30^)XVt9E%x-tnEq4TbR^oL%XXWg)jZnf$Rz4!=iX9R!PgT
z?`)Q%{5`^~QYX3B>h)j4pLQvF!GK?;>a+Y^vQ?T=1qnB-(S3k0Q!nLaB!hA9atppe
zJ9eIVt94P;F+1$m>10n5l@T}~Gdf4{%>7BMJ8SGB>CAG9IfLoj>aLvRjZJuh$BwBm
z+HQN=7yG*?!*KSIF|={RiLEqJbD?kVi@EN!S=~w$w-5EoT*L6@9d2cf$ZS|N(`r(*
z?8W#^yf80U9<9}KC7v{q=&otpd>;G6bTVDzBD9O&(mk>Egj#KrqW5#Oy^O;Fbq!In
zafk_cbU_~lqL?F%#f9dtsZzI!*Fvfd4T-`fZX7go6eS-fhw`9)6=)6N+&WOZlKnGe
zCxq1FX%2<X*oCUhvNDV)l7<W4K$+oDPw@&i+XT^;)s|sg5N&io%Rr@P8W>9tXklF_
zo93ZyM~rla9mfz0J)=?%bV_YQsC5XND})<bPyodM)QnnVMc|(g*zto88f9fs`E)G>
zo3*rzPdvm6AS&>IZ(z|@WZKc<k3+;UY1WuF$Mjz9Ax`V=_C16ouIbTJhz{F5p38_E
zjkxd)Sc{^as&%;8eG-Fgn^n68Q4kcA3QhQ<SQcN8Xq=#8EkFE)*8=b#<_79h7~d3V
zf|ipdpN_2Re!1P#Z1vhson_QWOu%auI@uJngHOxBgT-_k%0t&7=dg`qWsiSTCO}KK
zs58!a`ae4OOky)6>j77(bRMm15)=gq%25!&>6oNV43v(1QL0V~PX?-&blhB^YYne~
zXa<ux3*)RTYUjLCIR^Q7DYF#VC_CG4#e2c)!i=xjmejApP|b&t(aDG>X-L!Q{9siV
zJqOUbJEbgK5da`;Q%SJRNJ2*n2o9ZAJFF!X8ID-Ah9EMrz30>-q=tjnb2u<Xic}QJ
z2EIHlZy~|6ISiS2A6fFklT{yN5Gu7$`|$|%8IanJ6u3V-FbWZM-y-!atjzmDegmrz
zz-u8OlbaYfUX_Eo$V<p}I62d5Pzs5$nk#F1L>y_T0Bml^g`Ax7(Sr^Jq_F6=1PC$K
zy6%nwv+sBo9l|qWI?C73R3OaBQHZ!!yMEThA^=Ij8Xys)Zi}%}RR_3^5j*@$7iLkY
zI<0r5H#%?+VUz%Bl>5dQ|IQ_l_J?_y3w$%yV3nbTp+ab&oRO!^+-tKy4Nnw+CXPlm
zO^p_TAMm1e9Gd5VkP;No{u$9{!qi4ngMWb@2<mA-Uk)5Q0t(nnoaWDfoSsaPbDRML
zi#W#(CK>=-R%=mbrmD9{uJW^r=ghI;I6$Anc_;&xpJqf8aeRTH@?wIZN3T7b{IP>G
z4j|Y)a3ZyXG{PaO2RFB6rB-WE11K*U*0a^T*}vCJ%3s0wOsd)~SR(YikQ4qU>dnlf
zqZShj%0<SU;xfD*;h=JOMUJw?{WxMOqs39{`RHE-oE~7%u=``GIp&ceuP9tPtngjR
zP<+sm0Z}7X4*|UQiwIZ<_ytO*r%D<-$-t@(=nrqND$WVVaiz85L)+G*K(&rQRyJkm
zWo|~AI`FDQi61)ZA;{AJzDcp3UmFcc@!BJGLDbe4xPlp{cddL-S#7yAL#-D;x7w7t
zH4J#tMI1Kb<Xcbm@Ih9pC6yryQr9*3RjSmCDtp95mXc&WuAj^ZNyUTmkO$^^i2Jhp
z(SmDq&|3j`d<SXFg@>b{MKwhMofJ}?3W|gPUg4RZk8=MMfXeVk4w9g-Ok%7f!UUVj
z3V3a<sz+d;ea;d^YBtTTG6(edAH#m6f)9ToYh*)y%{^i{;IJC1OO2mi^U`fVAdIc3
z#<&#Xipv1=Q2b1x(2pFWlyXp(0l23LNa)Mq6%JgZ8m5jxAp=4?Lb|ua^%|7=MY3{`
z#<(LUtb~da>EqWELW<OUlsU-q@QRf0ez1n1<IlTL4qG0z($r+fjt{5UlRIQil}SnG
zWjqG26f7~o0l~8DH#lvx8V?dfaQ}hr%Z!Z*Bp>g<Vv21way@oO&-5ohL#oP*X!4E&
zwr<r|sB7#G$}4}>#i~9<?bB8>DR;(UEMg&f7i2nWKCdiWFm5f2OsAt=NUV(~he8DV
zdr+bLh!6Rry0!sr^S*`mIv1hL!|EH6pJnD+JLwKY#2yQ$41)3@h}M}xrdRiyGVrbQ
zsE>8G7bwFyD}&K4)tcNuuhMNMYdkk}t>VIa90>`?Bo0cBHw~xnrSNcgCxb@fcQRRx
zw-~nCxTjw90SW-+#i#+`YRRN0#Zeoi8F7RavMTNsZB)i9_wbxZ*F75241jiT1@7bv
zj5JKWk{ZVU5K~RUPK_tp&o9d|2#sQt6F>56>>U`%<hu+*a+Wb8&B_nT>yNg}J`DWA
zk`>H;T_katU4|Wcjf2&I+9$GliYy0(AcS*)pHp+IZWxd@A2O59IdiX;r2U|D8UF#i
zX;73CTyx?ofhw&y<vA4AYyo5GpTfU_=D~?*mvLE)CZL`!Xh6BpKC@befJmb_*w7~5
zRWhHJf-=gQfQeKJ3?z104^>ft)zJh_Xwi<Uu3CbYAqZ=V^;x<l3_qQ7c=eiPrE`2X
z0Lx=RJR=&|Mq0{2g;F7|!-l7ahRn(!7$huK>V$*;i=7Hkbt+-hB=9cK^(=oOJt$U2
z1B)m(-mOrRbcM7n=x#$q<NW&hjjGDyex0f3;G&Eob$aeZK~7;h53kIo9t`6{IB``6
zMJWSK+JYU7ORAABwxB2IIU5RD3vn$CE>Vv_xG;js`6@~%IRlAOu<S>Y)v{Tl<Kz>d
z83#NF5G0MGv@DR8-a&`EQAoDoS&++rj-m|a+Tq98P)44UF^ef2hfGt%hwy%xt-6B=
zkZK`x+OFWpKMpnvShQ9f`Eh(0&svd5r11)#@g(aAvG=L<5ExndQ`RoRoC!8j=-}kQ
z_v>759DE2M=-tI9If`0!*9SpTrh>?%0=amR8NJ-ntu<aD+c;&GT8OwhP@<0^7>Gt7
z%@!r}G{EbDlf#cF363psR#C0xsv>QynUZvtmP)8UHF1D<c$C41Wbn{)fJ~h#nsz#E
zj|$oRI}Fb@uTd1FnKEpUH@}#eE|Xe7sKxQVr$xpt&d@Bs6+5UgC$H#9L04eaEU2<u
zvx%VJ=s23)08jU%X}U~`P6tp11r$^pfYOC9Ucra{3O*XrlolXf^Q%Yj`pwj0z%#(o
zIeZ9v7fu}X6)8QLsqL_CqKAj;$5XX}crg$M_>BZC8^9V<9fBQ02^xVwUA@jNn}Xxl
zZ&-HNFyv%<!`zaCcUNoHq{yWZ$_c3p@eHl{=`6`X3uw%$HC3KU(w~lP%1a^e3LzWJ
zlPxpBD-oavE!BQ-T0$~2l#thE_=1gS2`&o#^@Eowa!?O+R%L}1B9HA<k+`3O4c#pa
z1n3n+g*qn*h`3JJP~tSQBF^)Z05qsp!-tOp-3!9<BhPppS2X6B%Lz>(YIx1-BML$x
zwD2unMyI6VUOqTze}znU<zh~)5eWqb@t{<N2dOm~I|)oYr`BlM5>GzJUr{_hc_dC}
zddo6|u3id4Gaj1k^<P^c_9lyF3lw0~%p|uUGkPB}?^`=zfe?gikz`e*D)6sB9{2_3
zE@P`kq!DLn(ld}zwHSGgDNv(;^_fh4<Drun1v|UiG;6bgbv=sYg{$XEs?Uj>^nGD5
z(2>OVvgVM+rKGEmkO9v{h_3YVmJ=PcTtW3wdI8xg=ysuW+bPT!*f9+Kso>=XUDMX#
z4DTCgOBl{@eJU5P)gqzQBr9oMYuK82B^QBsy$F3}MVzAvp|hEcKkjqh&6Wt?$(n^e
zTQ@$M!Ei@9?2}RU=!dFqOzrOJ(396t#*&K%rY6Ik7mB^s(a!U11IKn~m{Rb9Q)$d6
z<I$AKiTKOo(d#YJmaua?6@Pg-c(jYkHrX<TI;k-ewzQXda_0y|mH9HUDe+Ry!rT8x
z*xvUen3>JU!A8mIpy7R?kG95*!bMDNql(uX9`Pp<-xYa^HH=`-pE@9Kt+rzm>05Y#
z#!1JBSlio1U#EUckufel-k4%nxowQSF((7&)?7DRx5JUw9vt^h80y(HVQ}g+%mL5#
z+1X?xJo9tjH<hQ!d%4jiQP(mW%}g;(Y08$Rd_u{J>~!uJ=0|Nk&YQSSe@3UY*T?ao
zY~H#Mou;d%Bgp}9mvyPrO8~w?T~yP^9zU8Ja7g8v@$Jq>)-qmHLw!nPfMzkfMkbm~
z<o)RJiCD&5?tJErTZ#M~3FZ_mU80U%#~AaQsN<M)a$3jXWXnB^SxjLm^N92af2YI$
z^+>NVsWh!b^Hgv(b;D)JP1Sox7A5A(<?f;33Ux-2Wo3u>kD18xjL$M_y>&fh&%ire
zIsl#eI^(n_^7FcI;d82Knffywex$-{vrF`gMCvhe8p3#O3XKNqtI!u116a0WJ?xV7
z&B9l>MH5kTZqg?uYkW^^gbfonZ%yCmTv;eQI3~FE?h|3u6A#`=wyo4)+bk*c(;`Qv
z%l~EX-Q(;ks=V*oyLWeXcbagzX<{dYSlu}Zhg?V#17<*^`s5^>Bm|l}CO}R?kPw7$
zkwIl3)lI|GU|<?V$>6O)P(%@AxClsSA}FHFL<UibTy(t5pn?xx7)6u!`>VZAC!+Jt
z`+lDP-p{+bcU@MkT5Hv+>#kjUpXfRU-LUTBIrw$un(ODjGG+;9l3^ZXO{Ps)<2&`v
z$KAi-p!3o`TFcexr?$lJdw<LJmX{|#-#&W($XPGmKQed9^nYuwO}=Tbr|!S|jNgCk
zq5a-<&G=(aSu}pd)*DCWKJ$@>rhj7jQ|FgXUAf}xH{LU+>GA7}_gwMK<L=(TJ3wE%
zzS#HV_4BX2V&l@g_xR7FhktP6j3<6DaPXII-H_ff{ha3SKmCz|d$&I`@gMJ-K4HtP
zN2ljKIPh+_@cF~XAKW-=@~w^gC(Y07U3>bty`TExN9Rnwt#R)A7kz7Tx@6&T4UZ4*
z`SE)P_c-LNWp7__PTxL<O!@sDC(Rum_pWoyUWc6X&3#&q8ZO@0e(&^0c)#bNIhT%~
zckXu&Xjpj7oJTh-*+=F5H+uP*+n+pW%kux+bH|o{TeD-!bL)3}^{EZ+t1r%d?#2r*
zdG5wHF5R-_kkhwpd3Slo$G@;)$HyO?_2Ty)KIp~oJ-TScOCNHly|kmY<E1~W-|^C)
zkG}Vbe_uWF#2c%BeAo78Ucc+5XP$rhjlLJZd12rD@9sS2-V-i4Y3HTqEO_<O^$ULX
z9~bZWM}9EpUtjxqY5QvzAF}<C5BI$E$kRQiU9_re<wdKC``o#zW6wKRwLSE!Z*ZN|
z@u8m{b?9Y3<pqeRPdaY$(<dE!&#C`<$~`Z9<CwQyG_T?COMl(8;q3OQmo005``lSi
z9(efNrzRb~@r;hS8-L!p<;=qleE7_bZ4aJ()`54P{ROM?{^yIF@%-Ld<92MnYu?U#
zs-+!Yc`3c@tFJHfTV6f;xd$%X_ojco_#F>@abEY1uO7VS#mNsY-0|tV%2z-0h02TH
z{oM4)FMh~=>ZSLY9sl}=rGI?!jrI3G@o&*Bz29hi{k7iq3x4^%!c)sHEWG&ih3UPg
zY#2BHhaZY|Ub=qDtA9Rg!K=UgdGq>T{eA1dZhZgbmv*d8cRtd(VCN^tFF5Vu@6B9!
z@%P5>bLaQk_Pq0?!s}<9(DC|DPnh(fm%rU}*^iz+Wa`sLxP7iUqW8<+T@*d^=Wlk*
zz4Y#>hhJLUXJh&LJ^y|~d(&Zae=z=?r*D79qZ?Nj9^H7lz4pw5u6lUcjOGVtZ7SV0
zYtO&adoODaHRgqz_Mi9ai?iPLr(1ux?E6QZT<tvZS?1+G&i?wfQ_YD7T)%qa0Y}vS
zbnAP%f3o+ZAAI(m|9t*W-tqh5*ROqkdhOGP_ucf}hcA5o+0QQgN%YX!_g?ejTK}*A
zwZ{L;y%)Uvj|<#WqZ?a0uQ<kbUh%{Q^RHRiH}InmnH5)kAboz1gBFw@pVvI8Y5$I^
z@AF(o7Y2U%<DNrqTiG*p`Egte?W7rRmTtOp>+zG%sJh8#{GjcSTUQ=7`<jIl54d#M
z!~_1kuzmCApXqGh@aw|dI}7cHU)2;(Os{O}nSM>rC(l2^e)^*0dnTXx{+{9)9O6Is
z@WSHtCEH$Xu_qs2u5L~$%UODKsO%Gq?dI6h_uQWj?p^n%`A60spa0K&qdh-MuDsS2
zzy7Hv`}}u4bL>sq?(crt++lyx_`n7J+ZUYYzdhf)JmL02ZO`d_>EJQl>EH=H_g>X&
z=U=thJ-^56>58lFn)K8YGdq_qIy1fczVU^t?;SM*tACshto~VX>hfdeO?|qrH0iUe
z(@9s}GG+4W(UT{yKBn`KTi-+3`+8<v)SJw>=;UPc=bwl--#qFLe=P2vduQXk*+Y$!
zCk{Q<^vR1p(*Ei5w;eEf!*6@q&$K<2+54IImb#3Yb#*D8F{x1aOgnR>DgM%OT>ExL
z`Kvl-B%Ax1XEdB>?itrU@3yu{-9IgK7M>oM(mmwwnD(``ZQ~|(ndGaSJ)d(!Gd=yL
zHLh=<>`pmgVegR-F0KxZUsL{Odv9&Ylx~~0bZ@q&#+RSJa9P*Mi#FDVn%~#qA2#O?
z@8^2wUopOO#Lcy3*E_AD`Iv@u+>)uu$IjSiv~A&`92c9FL>J7gxP!mm{L#*PR`pF8
z{{6|-FTc{+x}kT-&WSc1*w{MQQEBd&@!@j|`+aKMKx0yg_dj}hTr91OlKsbD*%npz
zZtkxR&o6v7EW_JXzAy3IrofA*$u(}T&rW>3X<mGA$8BxRd;gSoV;5aNZ`yEw>pK_L
zqA3%tpZHZXve%rCHtL(Ql+Ubpr<BUQ)pyP;^NMJ7N!(rg=1tx9nq<~yQ(4yE*Bf`e
zXUY89Q0smjJZC<?;||k1Kf0vTE*ftaSKGQ;1{<2A_`oD>Ydf^+3;PW9o4+&76HCrb
z{z-G;UBjK*I)@K-tzTYRsGd_9K5);*R@=yXMoBc>`C)g(9@m~>8s5Dqo_R*Keb(*A
z__ohS*CkOkp5K2Yi+(?WWk*M(cYc}(X#zEEQ>-Zr&ooW%KG2)i{YjtB5yn8r;pARk
z>vpUcxG8O=&n6X?XBA^SyLL&!v#^3b`)zb9X{PWS4vkF5$?44Z?_yh*<&dAB8lJwH
zmId%Vfki?$LfyQ<cFtzB>5ZrJm@LnWHT?~052G-XQ!$IJVV#yfW87laM${qezoPNi
zh0oBK@$qcadbMT81^ksgeALIn1No--$X&QB@;tMy=^YSigwv+T=X|J>Tj}Cti}h3#
zt1se7#9FL|&j(@Bu5in5n$8$8gG*r848AYBD7rJ2;|HvplA<x2y2y;(2sd!HQ0rgA
za#}|Zjdk!mFDxEdVHzahSn_Ed2*M0_-5MHS)0&4Xwr2QP>%9Zlgyy7uf_IA2V<Bec
zf(=jxAKo$a`0=1+m!$+N?l3)RTDI}%bbw_CGW5>R{Ktgq=N6h{DBL1wJ>|{qyo+TL
zXEs};G(a0^EvS`Wdr~Ny-nf@sJ*?4Yk#^*uH(Jm0)H*(#bBs$Vw>FoqN3Aw`N3R(k
zG{)-Xm}?Ug^*9WM`pLdkJ#LA8H)T%v@le(|lq6yOX>s|;Wudvi`pR$&g#uaD|D$Q*
zlVK{wv_pCv<)IxmTGKihxr*-LMXuY?NunVEi2Bh#gID{QO`ap%i0+~o+cQ935Y9p!
zQIyt_?x1qum8Oej8>LY|wwC=1AsuwUCdOxUQWs3kC(sC7aO+ONDnk@I6?Y7>ylD_*
zA~Cec$y%&2<v{0cmTaOtTOKv(XqGNl6%iGjp}92px@yWFh$C3$3R(K2(C9Iyh!B8i
z25c#uk0e_rR{3?`rM(?)9`%&q@*YEz2kLr?M$D3KoO#@n;4z4B1?gFoSP*DALKp0q
zdIzp<r-b`@>=2o513L12;?hUzWwZ=IPzW6gx-5uK-T(TdX4}jM^v=&d(CxT?`@_F~
z>5fldy7In@mv4FLwCg|i{9RivI`q@OT=ltQpM3PWbFcsCQ@^_PyAR*EW8(wIK6%%3
zXW#VEr|!J>q=#R4-)j%7c>dAn4!Hh@Pu+RzcR&BzU(J1B<@VQ}n|c3tcii{I7rt=O
zH)nnC&7GfnWA2vUt$*O%Ke+4tKls9pr)~e-%13v8?~q4kJpHQ^S3Y{<QQJSe;`8_a
zZsvWLZn*8@C9l13)J^vt_jzO=w(+&wF4_3ncQ@Sh$jS%bed)vd?tJaGRcF6){Dy}<
zx_wUZ(m$-)xZ#0SJMTJv);%vQ-SECkKfiOs*}q%4^R?4v-T%_EIeN!sJ*D1x*Tz||
z|9RQxezJGV#P`oF#3$aQwr-N4Xlp~<bbU+H{1NlTkGhVLwqte5I*s?mcF|U|?TW3j
zZ@wosSK6p}V;tQ=HIAC@cvDhpJ>(1%FRk|5(S+NgD`uvbZ*Ff{@#NR`Dl8nZ{<?u;
zd{uuMe{)9RJdXO>={K2{;>~f#+AcG6gEzNaakYuB=r)I+Z<`MD#`NtmY|I>fR^v#s
z|I9RMDDi#R_RGzI2k&8`X%!PK_&n(wqM1M0!$;GdS=c?xMEC6Jo1;U|ilTLe=Jhqx
z;2NVwmG|b$Xg15EZqwXlv&KVh$7&E`5ZX`{+buYjyer@c(lmAftOi2Nn{0engLD}Y
zC=;xj^Q0qz`Ac|<xX`pirkw0AbL@)QJbgE1ys_ckg7Oua*g(<1*$8fssa@`Jt?|aR
z)^t`y+X#;P+_2e7CC(FdQ;)QtVK(JmjA2km5*;Vjbi!~9ycty(p5$q8aJ9xxu92B5
zF{7SDy58RA<akK$*b-+?vmb73nDM(5G9g*{ylK^fY@}F@?G37(jL=$m^Ujy{VluJL
zn!;=)F%rc*qe-+uF`=u8b63`MXoT%01*V)^WlWBpi3X_`c05~S&KhF(gw!Z9+EZmx
z)DXa7b&$dvP3Q$PVpvZpJ~Bl(HWl&4TPOn&A_rpz5>p&WECUAPh0ckEmqbjXc6zRo
zk$X*zY-rISzTyMV7#x#vv!1n^uz7*(c90F%GVrI5g)RPQ|0#CX&6t93Fp<v|tT(au
z%wHNcOQCLIJsC-fS;Pi8SmVP#+rzPfW({^#`GS4*B*=vb(mg6;wER%HQ{6E%I;xl1
z1$hB@VZviS!wwO=4bN8rox19B(hIqS!vL+7kq?z960JZOXXD-wA;EdWM5Bo<*h0*R
z0T|xPG?yz9AaTZY7f=YRLpKmirj!$*_V_f>nB?rFnhh+lhFF3OfVF)TZPo^nZ#BjW
z86`aK%1jaF@)2;(P|+rG1X15KSV%D@IL>?E1Px_-!pP$qQJCL0ib4m9co8mRk3@Qs
zs#%;ohk847*8*sbl!RXyLJkKfL3OgJ2Gu7{C9E2;>?}4=?b<k=r*#IJ6_VN3cv5Z%
z27^b$3+L$O(MnAq2^-!X9AJY>8*=0(Qt+rC{mVY2fQ=~~HcD8VM%i9@WF?b6O<7{g
zQR>itJFSmwAGv!%&Zvi6X$R#@3ymsaC*`3C4rfpcJ_>AU^ksx2UNSkIo;pW>!m)TZ
z#wU$K76!<GoD3A6mmug0t`;`28&Y!=tNBQ}C;a??X)hMND9Nvff`FG3LUOZ)gsIp^
z3-ff$n<CH}ScFoTkwmYS*&d{r8db*={$Us#@5K@h-o#Go0&xwy)PZL@3MTL87+cVm
zB}rGmFZ({~w~LfQc<1L18mAMXxm=@Hs~fiJCvff)_ayW!leh-Q&%hd=9Z(!Jly4ON
ze!%$kCLIU@+7n-HPv|XP&kJ~wVo2X#56o&cSRq3?mEqe}jZ2&{6~-kr7TdYRjDt8S
z+zzUCg|TT?DAv0J<kE<do;+kK%7Gy;m4jgi%p6_R1$18nnM@C(qgjE1Y#?@`zUitJ
zYLSJBV{ejUA~9Kf!Pwab{f$xpey<M~qk{=rI!c&*227Py;6VI9SkHy>SW~jBi<=e~
zZCHhpgFR>QF|kW<Jq=T>pwPe+&iFcv1wm_*TL8D%+J<OTOeWW(aVK`1Tw+zP+)>|q
zkbZaC$3TX$(2P374m_#`95i|^kucP#3WTGXJNd9vj)+7EU;Q<EDvt{9)LV^RIOt@5
zdI~uqNwaO^m>&q)X8JWKBsQ_6cvYafn4XzAnS^pTTiBx*d7HS`Aw3vN!@v;JR2;>X
zHpVYNpVfm)!IV0BEJ|77lt2%4Ss+Bz;vrp2L@zC|5bHohK%$-Pk~}({bOlK<f=k^E
zVwwasMc`F)#xd13H-&U!>X;Ef`$T$3#Uwr%>$db)>W?&R8`Gs64}$sDg7QUX&q6w(
z%p(NYi(Bguyy=m!iHxN=LUN@9xU57NmUf&J8uV@r)lzY6*cXS;m=eTM%AgCtAlWKq
z)0vlNqmz(SMSO*lu|gShB_+N714P2;)j)6BluN+(Ld`%Qb_!}yzU+6n&f@Npdb1`P
zF~-}p7H_Tag|~{KM!EM(Tc)TFNA9umGsap9>wS24t6;9&V=aA`OtqFl6f<21ngPBf
zQZn>G*T*SiKE9ANWJe<XQf}1?4uxk*aN668#A=VzO=hW)ktJP1d2WFlx)<CgZRyi`
z%q_9QbV)L?#~WKE)$%en9u;3K^w}~&o;5l*SfD{+V#`DPQT%~ofoI6*s`qZJtugX7
zPAT~Ih-M#?M`ugT8VE7DdNozl#-jmo<JOy&lLXcb5Dpx`(EwPb5!FR)?bkg!p~;no
zm>y#bjpvm+Ff}+b7~PU=VqUNW%S=^mja4@+QJt)g3dymci&r#9=^S3Xa-BTNvAp3y
zGIzAr*iBJeb3=`&+nn+eBTzWDfka1N*3zRX?xUHbM1@tn=Z$WWn5_j$$d6+{)o)8Y
z)T7v@e6Tm>E0+>7?(fJ7u<mNMRep{dOO=dyIk}oDF$0}bI@i!|qh8)V!8C<Ir{^l^
zI%)J|lFsbvGJBWl^*&4~YDk?LbxrzFM#!YGn>%e7(rp`HVp>XTDfuy>Lx7}m+m^Q)
z9+piqyu5Whb#B#Iy_wLwsKder(e##5q3>qHz=)<gZEVa8JCc|-8}pq&a2;Iz^C&n!
zGiWN2DY=qnrq-&NVARqJ6()p;H9C)<$UK2+;<udOmZFnh!5CK=^d#6GDmCejJeszd
z>6Q`SC4BLMDzJuXdfYVmg0mxidR}czbai7~qhl<c$4g;}85g4(n$VF=x`?}G>pi*N
zX8L_mtH!w1G+0mPEttJxD;*&1c)7pHT)~*)qG{H4G%Z6+vbf3E&7*qX2O&i}p=QjF
zK8P|Jt;#X|OzROO4ND7%!jjn{l~{I=G#H6n7FigINc8G7z=#~aXUBYC2MA_Z0<?D4
zE=c4urpRl(A)qqVLuB+I`{W?s;^{KRIr4KO!?VO-nlP0qn{&{?u`tpInJ3I(eltOU
zlstQg;v5+QTB@TJmQvKo@>G<QWkR~m)R8Mhh`EU7&$s&m$}5Wxv~n<8PL&tdg*+O&
zwDPG#SiLLabEA0GBqA(#TMA|3@EjLX3m!s`WrGG*<-|c4_hF(5tX<M^^To#S3O>RM
z=5ik=O+;Z!5ozZ&86CBA$PV8c7AXuVYM^d3q>NG65K37Y8awI{fp8~wjNZhKA*`Ng
zO@mpDA8wx3jSD7_W@L*JXw-Z}9~{|7on7%XtP2_w%K)GK+O=(=ONs(X0!JA+#ixmw
zC#`%9XaUGkuGvV{Y-_c44mpVWJYQrM6Xshd;514}n1y4AgJ4OBZh$hz>3oT)13`){
zjqQ<2_r?;-+jAVIYIRtFFXD_i2t0oQg1HGH3~@=l9IP~mOB$2Tc+Lqx&zhwuDyo%{
zjQ(Xqaiv%xcDR8);25)2cfWps7z~sa+J|~vp-F7(C9tF>D9IpRM}}lRUSZn2gKR|9
zsx#;W8r!1~qTE8kzB|NuL(fTxq>HE{iGSw6C{vq=C0_|nUgT=E;!|bn3mVGFo3fM%
zjlh9ZSpS16AE8iAnaUF6YDNXn)|<pdHp2&oDqE4bG0sGzP^8&ylk{Tkj$@k`|L_5|
zOSoZnA65{S-&SMMA7fitki!Q63TVoxajDQ&IMa-W{IYF;Z<8%D>%qz6IK=eh10;o}
zO|xx^Q%iotfec`AD-~e^6uvZK%=z~+rYag)m`k2_vB&EV%UDOKMut`s^+aL>QKRvA
zDhPED^L3HHFf{7jMoC!?{b&g(T&*IqANd2hQpF;aIwTIDs2J1Z8#RlN$SBdRw8)%B
zCI`la!Z2R};ax)f)HSo(r^FcyvFPAM3X66bir=mE$}PcU#N~c6G$}G@4Typzp#@n-
zsRRXxIvIlg+(LjRr1=VMvKKK!0kIdGP1#)vX+_8atH>c;ZN45?KoAee7*XB=33~pd
zg1}pxpmmp`b-TF)p#s)*jxI?lh%@XCn3%X={srO$P$z~8)Xp^_mFm5!XY#eFlX|bJ
z%fPxkkj(%*SL&s<I1i;Wt!XnOe`G_AKqgXZ2Cq!0Zmo=yON6qfD`)^wh%@wB>>9x1
z%II+xHBs|;X_tX~F|vxP@Rr}$lHzr+W)K=JbVG7LGvb9_MuIwK8O_2>g@K#J3<!2a
z;@+82gmTnhU92)<4>E`z*0d_GP9@Pc&rTt@$yV)zPC*4^HboUcIQ{`lV-UqMHvrFp
zYP5w|!s=xXi&!D*AWrD+i1%Y~vGi%;m7`yL2QZ5_Ug?=N4j^>Pzhs6Bh0B>)bL&Fr
zX`ePRmOutJQZWp=D=`4+v>FD;Na*GPT5^!D$xKu+%sr~(1K>OeXDWDudZrjSiqvwE
zZXI4MM_LD2NhXo3R#@rd@EoihH^kPAR*Cm$@CZK)7V;@iWK9q$eW?t&xpLGCw_IUv
zLu5ARWfl<;uaD9Do3nHVsyam2f-MZq<q|K*+K*0&A_+xF!G)zjuVjI7Awsk-Bv_)s
z)&rnqJ3&wm-;q661XLYM0;>h(io*sPk26W~VciidrU!4T%O}6evfU;z!M_E)K{*$a
z<Ywbpcn?G`isj%(LI8nIrAZ^JxSS+Yh)vnVqosG?1eVKj!J`sFRuPsZ+2}`;Bn5Ec
zva%@qm$5|zgKSuF_{?xBb1;sKQ0Ah<P)XH@{uv}m3C{(~r2Y#NUc9xqP$IRVbbwef
z3$d)s?3%eI%s~zoRtU$q>d2Jni)79))EZ~=jM?(t1Tqt*o6yJmOfncK=uy&`^aK_1
z<yNj;hNp7EzFN|gcrc!Zg<yUV3MT-0X^XM5KI6qbrRjd#tdM2{l^YIEl#LBI{bp|+
zG}6|asNKa<_6SnKdfF8f=S>S^TnLbebwH0ncxK5!uX3UtX2E#b63k|dlrjcHY$m`3
zZ-^8!1UukbZlA;AMkwZ06(U=q6HwY;0WBLbfrZvyJm`bOj*)rILU4&utPa`ck$Pj6
zE#RdrUwy!J+AhzNXl4{D%c=)6PSF6EU^rU`hSVf+Pv*rYFCx{ov&qtnS286ZhPpEj
zMVN#cARg8b!?)w4BM!+h)R>TiUPuR-^&v)|Y{}Rk>hj)$Fp?vAuujeD&0D5)kDi#N
zM?=3+trTL1S^$oU=a>ald~O;<X?iR^pp|8ahgf(@B{EM6MFt|>nVN#b@w9stLmgG1
zm9m4{y1-f}Pd@oT;EZ&!iEU4i5~do7W1B6o7je6BxIiEIyPVT4kAPN{1saGjSV^yN
zAB_RY7rv+`Is|2OnW^|CbYZ276pd1|BmtAX4ygUsF!(Tdt6T=&Rz9P-Y(5yI5DldO
zmtr~f=3oWUNehZizYKvaw`W-eiZrtLgi#?iBa9I$s02tO7f6Z5>6f<gQ0%@yAFR}z
zt%T7)f<-*Sg*|GS9&A%9j#D?P=mb8v>M7)M;MDqwp$f{B<p6P33yvUUEYAr51<F>3
z@VG>yTY%Vy(YCBeKc%6=6Ov*;H%xPV!ksPXY%~so0%2%_+!@rL#s}6ewt~i`kX@xv
zz=c>=Aa<u?wRNx(5@vg43`OF>kQ#|qGHO-DJBhWd3|gptJMw6T&h^UrhlYZ&ah*JB
zr#>&cs?+BzMOFuAt=OBeepIsoth}CJ0Y%m7K}LEf3c-K)12G?pgF49|F=s+o&)yYD
zmDmqfhMzB12naIzomrEaObwOWeT_v<gh~(0>k$ekq!lkg<UvF+Au*(DI3c;zw#iDX
z%jcVbCM6gnM0moieSNLKf;`Ex$_jhKCTo|7eZJ4?$udk5Y<;GigI*$C)`7S`^U5e#
z$HfPF#8wpE^oC-1VnK4BN&$pwi>t`jPKt8@8N?HE<jVmo`iz&OW5rzoUCCNc;0#x!
zg#j+mp=79?AixJbLV9MF%vfe1u)&EThv*9Q$;Z09Zo`nA@S8GdXvIbSb$>pL8Sy0`
zGCHm?upI6Rk^G*EFwLHZ@2$`>6Qi-Gn5Z%+e!J&)MC%st3Ij+r&<0~UAzWhW4M%87
z=Q2w|g*D^AR6#XP&rqGG#tur0Bc8qT0Ij73xDF3eGO$1*Y`GB549gZMU9OSI1r!`&
zypS(gHtVE9g}U@1VC2CR22iUE8tiw6FdBduMre9qNEu4FZ-K0&n4=HVzabL@kzSrP
zt(L@k#WBJ<<H^RwhpdR$$aN8}gAakX2p2A((!&(YbsJ>WW}^l9CZf|jKh~7qztlSI
zNlmbem=gS`1`FOd;b2j(zp9irJGzP9V$g#L>&(@m+3>?#jvE^*?r~DpaXkt|#0_=D
z+4xC3yu{U3?!3Bc25*__BGb!G9vzuiV(c(IX<Vg|7gd>X7|n)R%+BttCPT?IQ;t!j
zT#6>J^JOlG`L%7++D_kVHItIj@v)iI)9vZI8bXuwbe6asknmZcVZL49Bjb)aB(=lu
zwUJHPu6IzetZwMizG$<#ZaL+1aktkL+lrC+$)5r0qHVb`-ZoUPAlXbw!aYbw`^lko
zbxgh7F@m(VP3Ehw<C-dt=R}^YNxV;iujQoiA!oG?PNS;WmrVD<EApxfUwHA;lEm+C
zsQ{z4<&z?fCPt$Y<u#3?mHmV-cxO#~UEJuC*@;`qbniKi=c(soU}g5=0klT1?ygbw
zh4-|0zQG&Eee<IcZ(916IuWTZzi=}|qy2GrGXvP;sz&;1!sCbreT0q2JbLPKBx45i
zSlU_qm-4n0BMzi3g*NJH2BT<$QQ=b_@s}e@w~kzU^5K^5MrPb}u*D^*>t*m*6Y)&I
z4VYfzDxJwwoomc2)9ktFOx*G1#C#x~6URl<yf5~M*YPqXXK-4Y&6ntTR}mX+Z|NFX
z<kGYyPFhY}V%lbzuHm@FaBQ~10Vpc9IqE5)P(_Cs)=?zO`@Sw}n$5<_-dJ*ibA?hG
zbuH$wIrSMGlcIARaje)h_i;QjZSZ%O`Sg4>E^IcDTd4Cmjl96t-dJI3O8es07Td`e
zOX3qtn|T5^oL0O2lqj_{!p7DKoHur?fA;)#F=}*;oW1siwVW1V>+v8n^mJn~I55YS
z%#>zRw5h4|@Qf&qnq=DIg$Fv;x$cS9*qPalA3lig^K{W%&GVa@=1=tnRNSQ3NqNrd
zdYU5h80F=;5%YAzfU2rGe{|w!s(L4cM`-4M9ouV{{(j`#t8eI9_wFBVHEZ6sHQmZP
zJQIF@%N_@uvvA_lCl^j#`u01DO*ei%;vI!!Tb6w5*z#kaDLxh5(Y<B)vXw2%m#tX3
z^7__d|3_xLYmX(X4q5)K73EL0ca)F0zGK4lGmrk`oU@jlz3=r0AMw&hCVt_z)#DE-
z)><|m{r#z@xBc7Hf4r}&<=v0GqxrJvJA0iz?mKTA|IUN<zwDv|OCLDvgmJ5v95Z3r
z+wPsS;(_Vsy#1GpI?^SJnig)lb<QPoZ=G}3>=X7$*Bw8(JaGT?Rh#aezH(jf%J=;8
zm=#An_2mP;_o;iQ-?e6S<0ao-J^tvYwiS=wdfh>zdvC9(yzl-6zlZWvVS3AsOD5b=
z{h8VF!_)1Sy}xnf*SDX(YR1Z+A2;KrUz{}IvfocQYSn*L4tR6tdk%Q>&6WSM{ZD7E
zzh?Eb>zBW_&uPowOix?&%jDIIe{<pi*St|X;F^Cw@7!yCcEij^KQv+KMHj6)@uD}o
zc3k|%)T1ByMaQcf&un~i<LT2cdHC-;Hy(cajGecg+4JUYr<YbfveRsQ;MLU|58OCu
z<3VTbv2o+Z*~jhq#_B^?{dC%)tInDG!3W-Z#z`YTKWx?0@0_*b=}V_wu;&|RoW13u
zc}Kr;?zB~}{KK?U|KsO>*Sr3p3zr>m;bm_>;DZ-z+;Ya$o$JnTy!h*<A2xUK*@rD(
z|G<TQ+?lD$`;~Wbc6I$l)5}}dbl&m9%W7Lr{!nSh+g6%?*}i7_jGa51W*_>SxOK<5
zEsGbfPiDS(?s2nso_);Mw{JLX{nHm7|H|?|r+-@hO3U%9{-N^AOMY`y(>2c?GW)8p
zbzgSP#eM4^x?n+-vYvL)h5PQf@QuYA9-P*F*PE|RdvoV68V-H*ve^e;a(e5ZZ+o?K
z=Y78@th(=W3l4kWjH5Qb^QWba@BGcARfnEA<Iw#sopI=@jeCA*<%QEOc;J_(pZd#l
z+EzXNtHu>i?ALhV+)KM&d-sNU%U=0y!>U()J8RX*rH%XCG5P$J2Ym3nmFK>G@}D2t
z(7t`<+0);>c+Q-2p1N(1CI2z$JbLC*z4!8+e>CQ$^=B7{wzVb$&+cvRDSWE>>*0rL
zty8~vM$@PMcVR-yWl8JQ1*aXkeR<>3=Z|f>_5&OHHhuDzO7+yw9=r6&*KPOL7cEV{
zws86E#-GiZVZMCEjLO?Cn!V`ygFo=ZMWqit{*F0EwI0-c<Q^9uanakqWd45YJEGH9
z?0ewqRmYi25Bgntaq+zP&ELK{?+1ULdB~FEZr*>{#PiQMEjg!lO5<5Q%Rc$Ou4SKi
zxp>LMb=@o9w%^PXjy!AjiIp$gB}>kp-@9ak?R&+3XyT03JsV#6VEcw2|DtK}Esqpi
zyMNP_UU^Box%Q3~D%;de{MOC4OT`VF9xYzw(%S#N;WO@@j{j99B~7OOM{6>5?c}DG
z8L5A~a9-sm*SG11?`_+(;E>~+K6URYODaDur_Y__;%8R2mTy{Bd0#SZV{0W@U96;b
z>5*HK4?KQ%T1gMuYjJwPe(yCunSSZihY#vH?QMIkUhy8g;PE%ogXaID@Ppr;Y2W;>
zZu1Y5XOyC2|6~0r=8V;+nDYzoDsG6EZ9Y3bbmG5vA3E{QaSapqHz!m!%<k>|vRTsm
zlW5uIA18bNY-8c<AOCav*{_`6bYk-Jr1$nqP4Bh;ySe$wk(1lH4|x9<|H+u6)6aI5
z)BA31E`9damY)p7GZ&?c8Mlu3C8O8q%LBD^lHIR;dG|@}Klw~~>9vpDpYHL*!Q&_O
zuNfE_NcLyrpuhL)-B(86>Rx>9zyEBVeR)R1ZHv<QzHw>X;oX|p?``*=(bCh^-O^+K
zIqtlBv}5w5U!Q(r^JkAcc;dhb6V?t_8h_l;Iqoy3R$E85bu3T)JF2A-(@^|vEiOKD
z{PC@Qdu&WkDqfr(v*viyH|L5!b`);zyy3u`<IM+7H-+WXM*13~_?co`#di;{G3J`8
z-{bO@!rmX@*AL$L<Ka1TFEZx7fsZvF__e63Gx|=K9ld3tt)$B+-%^#&uNz=OEL~g}
zI&4~xzkj^Bw)RjpebP3kpLoAt@Da-myy<sO+9%Ajw(;t|d(KLJWXuR3^1PdAr=yLP
zj5)&E(uAJb_f6<Y?no$KrE|*KeNLP*uVG?SVO+d+xG%niWzQ|!CR09Ukiv%XrLT6I
z;veFc;&<Hp&0|L&+*-BoFsBte(rsrB&KqRSdy^T7ujeb(!$(`YjY;Q+lM9t=3&U%e
zgooOqf%G5E$I25X9z0S=_N09C{if75yx5fX@@zSpa)RmD!x{fEcgiS5>nilNm~m(D
zHq4|ndKb&(PZr|7G+LPOo=@+)n6~yUviPf+!o*TFno?sY)y2^uQzUCwGsW?)5AO=M
zwYjLnrOCt^=M4U#A-dsY;(gr3EQ-u0*72RXo+`(6+3T9poJ?@3`NRb#>NvU4?8}01
zYE(5-Ij_KXdR^=ES~{79$K+boG<Ef+dvQMHdTU~E=}p#}k0UmwRwkRow9Gd{SKG$X
z7HbB$4T`@HZm94sG>VR5!IiFH<vnDLof5H#e2i6=0odD}&szM~U6l76mT9aA`MQ%4
z&4OMQnNfB+cV9?3wq{!QW{pR9&>1sSwZ`zjX*I_$&x0pnOz+bg`H{~`(-a8%btw5B
z__0Vz&O@MsZXGnFbuQqy(4Dapy5jWOD?MjK$oK)SB_<iQx>w-68SHvJ{^lNJb`u9L
zfL-(neBP}xu`%vy?j<(GfA}4!0tOhk8YDxGS=Rsq{(V*N{8-x@o0@f?N{s<8de2fc
zQo#%febADZyW#@t`3lP*o(qv=xdi(c!#hmSlEMvymB+o;R-+I<$Pl(ehV@Pkzi)|&
z`I1rWbfcEAeB%HX#1J~<#nDjGsQbrQE25x)I62~+d*G(M(ZUeuPIyQbDdbHDhl>iv
zsr{Jr8}ASj<>RQ?n#7YLHe6BoogV~o{)KXcbwBG?2S(s6R~H}Mj9|$<pVBRta%=ep
z#9oR<T$d~A2si~`DJRe%2V?_Lue`lV01@M|zSI4Le!m8Y2EcfwJFYSpIRg}2XgnT{
zm@Z3Ke)wCw$Se(&Epf4>^vb)HD=}WF>PW`aL>znTcH<8kh|o@|n;w(+pm?U5X`&pV
z4CA25z-RCDNMSct#&jG}onst@hvUvn%^Zli;DH3sp<w)_j6{l?79YIaPA2g(sK|i^
zZ@FQtg|O^2N(l8b^Vjt-T__wfxQ9s}wdg5@oH=UCOXu=iI$to`4t+!K{4Cx1+_^V>
zb>-)O|H2_JoxAFRzhD3GiI+Y9!t;0SxaiPNp8L{$E1rMt!~-6BVdbx8oWMIjJ0Cdh
z&DTykcl#$--1gr0Jp9tR8y+}z=K~j?{qYx8-nQR+9(-=&tOr)U`MDJj@BHq$kL-8q
z7f!om?nifQe_-WZJ5If1=Y|*VI)2&4PagHh->rO@-|>0moaKK$?d(TCz4YUctbAn0
z35PziVbvp-ExGH3rEh#<`{6q;J@l{*N8fqevR8h%;iVgvp0nWx5AVHm!<`$K+;QrL
zM?bM*?m4GEc<MQ?J$llcubwjZ#ut~(oqpVd$Di|yM=sg<>Z)0k_F26HbJPX;ou7@f
z(i;{pwvF*fd5Y<7+Pt>6)K@Xp$F`cK-!d&N&s^C%;qk?t_Nub6`*x>I69@Uxt;bC{
zD#xSEHz(EVepC0ncd={mWi~sz=@G?bR^#LDh@{u_G~H~P$L&`ce^4zw>igv>u64ki
zwRf@BHGNGwxp;;<FB#{Sj_Wr|XU$7H=ADsNxz(yYv6m^Q^GXfX87-|ti%d&nKffw8
zZCx+B>U*c7(T22d{#k^Vz1Y3~hA+DA<+mPl;IjiG{N~_DG{-u#|Lra+Jk@2Q@_}8A
zOOKmbS+kJhX20X}+zB+OR~l%=3>i5vfB^ZUtsM7Po)^h(*epE8gC>(h)-<z-`uy&Y
z?9QQ1lKJW(aLYy~8*olN76=^G`K)3&s0j5izN1TI%yTST_<FbC!8bFaLB2lT#JPRv
zj43gB+{6;VYVSnQh;RmJq+4}&YvQN)d0SJ8=xsa&5Dwn<_Q;t*!mtf5fUpV45ygbQ
zIY{3x%+s!ye~g>b*mDpn6o~zQarG<)kX(Tc5`@dFlvvXn2tmTs(eWE;T700xvJ;6h
z47dCi&Kv*$`U}mL`9H4jBdSI;MvUsf1{w-#T%M>K$CxWXlDiU@`Gww3*%<!x3Qv0+
zCZkYplfWh-g#ntC25ljZk$7uh5IM)lW@BZK1}%fFXJEt#Q#26`ae5$T7-3_<!cv1V
zjF{?%kQ=v1#Uk{eIiOU*)ePk1bE;fA>#8KzhcmfUD#}Hkn{)Vo?9b#Yuz%7I6$~ni
z$qcnAa`7^&f|{JdepCpL7s?;PU49T~m}^Nk<R6JTEE3t00Kq7VVloxNeactrdFcb2
z4PBni7-`IFFA*KWBakW307b5v0#T?xIT1m4_VMhL8i7eK$2rYlsV^A`X1}W2TMNEZ
zM)jt_@}oh@$1z|PI(9ha$8mOnH6vmq2$?MWk(fAPGGLm;7+wu?`k<)P0^lnsbaC-y
z1Qu#Ncooivw2U&h7CFjl(b)_j+?m2mO;c)qd(r)aIudBA16t{5Ey6#Tq~B1>I^z`d
z5Q!y2IH8{lZ6yhPqE4)ht%<OnvUjs9ltfCP!_f5D0Wzu&qN-c)giPd%5@dysN2m*7
zeG<+uYvl!y1c4ks%+ruAlTanJvvFbpG=;Y`q{EXTPWR4gouv$Gk{Pi>i*6OM!Za+=
ziN)!odFw5t#582tf)F?dS&12hRK%8xa&WZPu|~1Yp+aCrO$SMFqlszu@KN6OOmr}v
zsW>G->tLe>M_d_8xOL#*0ZoR3x-d{ZbPUo9tp`~E*A&XwqXeH@VkD+efmFRO5+4ra
znl4FqSwrvy?UGoS(4N&N6KrAjqI*Y<<?YtkX}t$UoK}znq}^6=-CbxLBPF3F1&9$J
zQas;cm~G6+L1b+yS|!r(b1gDr-thq;ar7s`Qo<YSR6K`TL}M?r@ZxzF=nS;j0raai
zf&n>U5$IT<gs`~m1~Dx(Lr^tYCJdaZ5ClPM%eJ0Fh4MvbVtj}+SV~EY6RU>@uz7wo
z1$c`gv9Tk>crI6fo>aC|-k=Z(UU&=J*b&H}W!Og6N}5$;Y!jB{qc_IsxK<@GRkEPD
z64Vq?$Z~uvi_-4dARh@4YDdsWemv+4rqK~<&g2FgS(PP2({@;WsHtTTg*F_rISmIA
z%g_wH>haniiOLy}h}IJyCS36%lys@Z1U1XT1a!ATl3c_iOWs3+a$w<rC_y$}!Nmrp
z18#SxcsXJ%J)MH>4pkx;7~UjiWyZ7m)&V*h=Pgl$D3Pl{y*RJEFbjC_C9VKfI;EHa
z!y!kQoI>2AngXpBKCz_QP{IKriFD)SS@T6W2ztD%PzjI56tY~P3mPi&Aw~fpFvn{m
zxAe0@;)Z4yOyY<KMrs{Y6NPcs_)J~1l;jYknbSU9H<ixX$wCG&62X*p27gF$8EG~V
zWE6546^7DK&z<)NtShuwm~!~B&4G}PU0!~BlyYzAgQnbFJ0C=|gvb=9zjmNRnE^?9
zs*dps#@hs)20&5IE^7;UfA!$RCD=iONs$c_(P>tqzg8(T+wTAwv$dCH$rE7MsDnA}
zA%s={k8$cMUemT-*Abn%R1cSfXOpyY8nAovo*FuU1q*0pL+%g^TmId3GxE5l;#6*a
zmY6%wZb(`gT0?*3i{m_8lSPt3RkLPDW^UE^&aHRK?uQE#j2LUYWB^7|=&u^LmBqx*
zz#%(3gpdePMT&;}xMmh%Pk_=<$1;&JXc+~<>UpKoumVMf-aL0C+I>z~(AIGZbiT26
zs}?D>fQ30v<Ko1$re)HBK^vh}R8dML^~XdmEupp5dI%{)#*CPjaxiw0eB_C|EXBX6
zsOY6ILTMVXF6A?Dc1eB~Vi1;scJX0`i|jN!&&mDRhMA7c3;AJ8N}ApI!Yv`i3=f2S
zFmnWkXbrq6q@v3J8IY^Zj5ZtVJtbxymO97dG^yBBg~Leb4majvT4CH1^H%GCQ^RNk
z-De!BBRx&>$S{H5;$Q?wC8BC0A;a8M#V^!clgPV;G>OO2JjqWlNq5hI7_U8{ZWYe4
za4jSYqV{S1CGmAu<gF$qGnN9psZq+FL}mK@w=v=ugM!^GKGeUkRe;#QYYZ4>tRk6W
zb#zWE&m&BUmg~O(FMMF&2*Ceu0_Ca$Emg(Lz}5qqk5z+ETuPI%ldqnU;Ah(R*Uvfz
z%v&9sBgSNqowAIT(Pimbd`#agP|qup-i$7wWQ!2MCnLm;kZMA4TA>IsfnyvqeVNI2
z$re=r+6o}G9KIc+$Ou$_6OSO_Z$rr;D!aK01Z1)<G#y2|c4Zpj0VgdX4ox;FOZ#ms
z1*x%{#1vpNffOMM>U)$fqK(>12}b>anWxD0y3o2foW$nXsz#v<GB#PbhNpOio2T%7
zA1p90BOJ3$Mrk6UBUw=r$i(_m>x;~~*;K2K5EzOlDi4*V%_>{W7YG>3V;2>P0kQfu
zc_oDYN)AsbF&3V}v9cv^C<-yp^2iIXVlte2c>zu*F(Ixph}v<f50*7*b>;aJWLU^@
zV9cd9y@pFNss6sPR5CQ_I8fG>d2TLkz`DSi5YpM&!=9E%mPU+6++pOR03r?_lrTsq
z$;k;Fqa5lfQxFt$k5ZIl#Hs9F#FQW~(OI#Y(gK0RhKp4pnY<DL2yd(k3mRZFgbsvN
zmmSlZ1q~pJz(3?sT%fH{H-?e@JXegPS`d990RbdE+2^ahB0)#1kb*u0j#QP~5F|@I
zAjzUmVuzbU7|!bvC(X1<$Ur)n*k%#z?3FvsZkL!Ay1FA!q4P>eM(5hKK0TcJ6LH<d
zAxJsu*eqUmMd>3PF3}j5`w9!nnI{qa2axdvfnI@aa&mC^bzVXtAe2R6!93cmBX7>5
zo)~yZ8C_UGUL8XIfPiZEgnAhIw}Q(NyC)5T8`GKaKu#0t)?x=zMPJMDGXEGo`YO$#
zjK^2_FY2#e$hz+!$idbFxv#u+2;ma3dRgiTyZLUnu!4S`>bZfwn)M~7+fX@w#lphY
z?N)|*VRGAVBi)-_FerR=S3U1a$wHxMe<g%85&~=Tv+NnG@X$`mySOB`aPL#sVHbKV
zq;5M*%#C5PfNWI9Ne7m~W)xp-Nb0Cg<SVW(VbsCb1Hn)7^$PT*Opf$czB;6i5W?DR
zR=+(&b<YsMW@VIoDYHuov@IFE__at`*#NM*LVl<n5dkz!cse$l-A}&jb%i`vH|rf`
zQkDea9)EY}@x+*bhlR{#^bz#6OdsVFgnI1C<Oc+_gCT%;Prz}Zhn24@=S4{9zlfL6
zqfWyTEnD<??vs>90(Hf?9m|9Pk!96Dx$96@PI2fxp5yYlY)}D|L*XGVg?Hl+@>p=}
zDus2S(zbH-1f{`~7=jKYpyBZr{9Hwz1q++O?&<^?uAWj~*ZyTZ=tn&poAG58pV^57
zrGXxUt<<A%!CnFT`~PCJxoeEzErH#2c}vn?@O^9A|54oU%I$Uq|Hsh(ovtDC{~Koi
zqqNM9{}0IiN0Qy!(SJ{zQ{`>aLC8iru=xANT=7+fRQ|dR>|5eQ$I=uQ<V`b+<gWjV
zSQc@A1NXO3b=mc_x5odE8_ZuZ%p~zpF0|>o-2c(HIfeLz&hxiz@m4;v*Djkqy+!GY
z*VR%DW$CJu9N=%AG5iDEZ)JfnQ2Mda%#sG!oUG0URDIP2n@mvN41A9eb!})AigS0L
z>Ee_qbNj%N#amrRaA6({Y#fm~3v9TnBte>NlaqNR1_)%Z&IRS)5!%JZY-61wo`HqU
zGO65Is4gw?#C4Uq(9PlH3Wt#C3tnC>g<)WGvbr?nWW}P~SwEO^tw?RgTKAd+vpp_+
z<A$@Gtm~PoNFvUF9dxY(GHI!q8W;|n#0vLjY{Ht%5qEuwtQHw>iNTBQLcE+z11oHN
zxVutuB@H$<EYk^VY3K05JmvAkhH~U&4${CPCu83t)KQd^jj<6KlTA?A<BdtmH6aO>
z4t!SbdbzAgLb>Y-XVOHLOUe~SDOi+A2%3zQD=Rk-3F2^jWP4RMl{t`!O)w9rtWIX0
zL?BiythppR0MY`M94^DCFk>Loy#?G`;vwq)8u?c!``0wW__v^~eG5WSaADn;CrL-$
zts9qBi-L8CBSMtP<_MSje^nF`w9cvnmI$VJD_w3LQkBBG0{3si|75r<lMVYoVZM0h
zOF}v352?H)D`n^pP6^j*7pzDC&4zR4e5S{w7F8@+0?whIHe0F?ijDDHGzw*R;da-8
z6S62yIT>1j77JD>4ll3~#@`wQX1!7fB$Cd}H%%^dBjI|v5Ng$^O$=Z5ZXLn!4G<5#
zCrkE~5RRo;QtTYq1Y7d$Cb9;JVSmIEQ39--9%2V+76dR{S6Euu92J)H4#mYLD;Fm6
z@Q7o`l%H<KOKB+Vzy@jH8KA7!qijhF<wl^aYl#Edd_g>8j6Q9ITe-wV`h5T|f5f4z
z^_LjY8Ik=KH-O9ipr2mJ5Kl=F8<fh5m<NM2O9cI#{ILTUjtHRb2%yeJ%2^=*aM>E2
zVoR8nCVfbA_)(l?3}m`*^&m448DN78c~t?F3ku_V+FLzbCktbAmN6tDBa6X>EGnbJ
z!|q|M3S(AgE69430u2hM85uFLk<F*BRvI8SV-=nW0r3%IDtM06F&w9ORUcUnOF#hg
z4C*2{YC>7S1;(%l$;AvOJUWvN{VeU9OZo*eCm+L0Moxww*jUI#Ha}w%?lVGv7;B+%
zHgDD-s*2VJdfh0B0k;SiPY|S)L8@GkW(HNG)0&bNTEWZ60;%EkV?m}twzZZw<bV%P
zB|SlvOQe~?1jt?}8siCO(qtmo*nm(6ChS5atCQCsBoa1W)uTj7bFw0Efoa}m#27&#
z;d-UoC~L$BQ<}ChGl4l9c7H*@LTnsC4%x`f^bLbe*oTa=Pudi6GG8^0cUE#TX{#?@
z22H33frpI`AxQ#yP}<8n8Vtoo*<GD%n6ywIC>%Cjiw=e1!4XfnK@$^666JDuHCXUg
z3?Ts{CgqO3#wC#jHcD`khF>qY*(@x8CO~9t&O(}q%;9QS&-Y&;OJPwBY;Y{efcnXY
zzm<ivqHvp^Yf1n@ffL5>x|gSJ*a@W&d0VlWZlVgt40(uj63AHyHOAPBjP%d~<k_4o
zc4{30A6#NtG$Xe;GGui`>e7Nil{J?(wj}jg4l<}*fR$6%$teN^Hl8(`6c*@)9tdtW
zxQs~(2~m~@J}$(Av-^MwfuM(iNSJO6_|F9Kpw}Gs8DavpBHYl$6aprnEZ52bTySy9
zyCR|d0iRoEa@|UG;>`ECF+(f}+Lc}}&{&$!(st)$Gt^(Yj;M-P`b%_(*<H9X{>2QJ
zm2+46e;3NhNgm@cCd<DilN&2jZV|lflT{+jaSDn~1@p4)1-}x?jOKfo1bfEpq@jtw
zV?~gGvgyQ*z;lJuJovk0BeQM`_Fpn0{J#NqH=Ow1AifTs*i*-$>$dlx-wG;?wt++w
z=;TnYZal|jSb;bKMS=%#kz|^<0=Qkgb4+MpK97W3LE2y)vJes_Lkxq!jAz}hqCw>#
zN4jP0w)d3~q&$v5{a!)oMIo4jtj7m*2G7c`;&}We_%+h$%RU#Vx(I+UPCDfCR)&(`
zA%Y&?c>=vGQ3f)(CDlV6$Xmb9PU^V2Z%HFvptP-A1&323X2HQnLxBgidtTYK4922f
zH({kV5w;34(z*y=eB}%3zL3H@<k+lB$3%r1YRV;`&^GEK@Q9H?YMh+1*_i8Aj%jgn
z<D{jhPaK#%*)EK}qw+88ov?nm-}aTB^!@V+Yg?b}8!i;q+QCUJ_jC=kR`zI__iSft
z@=ssyy|O&N-;TfK%7IOj`6BVQzTwrkuC-~y@XglQC(ZPE9c$BMQgva++EUY`^qvC;
zS{tuv=)H1XYvY4g_BO=_-E13ff6_hcB-ai14y`S<a`bsyq4eZ%B)QV73BBrakI40s
z+$)fq>y>13TN>(m&Fgq?kbCXGCxTuW#Hh?C?l4Ar5oO~y9uZ#Flbd_kXGlh5s<84P
z3zlSI5su%xP<<qOqmbIv-J*jrRVHS77Kpt$i=htI2MdocPF9}Hyt-VfYZ$C!1;1Hx
zrI*E*+)%fU2vC=sRW*ptOfGsgm6XhpXXTe(CN3wPs5h!IAI>@2A@5D8Jj~BYt|=}`
zTc#DdtxK;Sj>^1U-P;z|lEHLw+dwzJoEY_&`{+y2funt#AnCTI`Rc;6Rm+KxLdR-9
znDWYOchZ@r*In10G;WHz%C*6f&bTX%dq&b;UvbsAqpQ^Jh6+hnDYj|bHj^w$o7xJs
zAXj>&z1NM_<qrAbpx2n(T(54M1i5v+>T(NFSI}z_%d^1|UN6t}!txZG_w;d|qvTo3
zwh9C%i)$@pwayUC=W=8l!uQ~lf;o?1qLq^D9&u5(f=U&~WoX5%mCLtGUGPGJ@@}H9
zTJjBA$nl5Zqy9gbi_{IUSay!$gEy8-Abf%v<PoSLc@QHZmODkrxPnU5Gor>GSL)-@
z;-v=bwZ3S}$}4i=JzfV_6L<@43vIJVmJ-(>c!OL$dstt}!a~*O<Mv(>NDn|hEpIIm
zq=X`<Xni~+@z~8nCl(^$ADTqdBDWONNWq7uVp)?m5TOjPVqLwfzSiZdGu_LEa*7VH
z9%qP4834%^&f=SeS<;BYjP=sTJ4GND;cnoO=@hTxqmgI>fEP27m!v5P5>>lA!_{&=
zW9%G>5RAyrnT!(jju{I4pm?b7cT>zz7{Y+Jkh@Ipp*)UfhPlMs=Dx$1{0tbory(nk
zX>JY6QOoOLBHD}gMCST*Ye9L3BSiv}H1Guz3h&762*!#7oMg))CFBQsPOO`M_<_>K
z7Al&cdbqrbo7ERFlUTWc3&UI{C-4Z^ut}(ARbEm0ostGa?-T;)=5p}KmB~%X)RfsG
zC2b5WA?Q-+0VE!0H<0~&B}>;?rFy*tp>{XIde9MwXpeXna=k|wz@Zk329-z`#1@Au
z%<Z|ZU_wSG0ZwJ)yT}ABeMHdI4R2mhw2DwiwVan%ygovy6R+l?jd+I-O<Kc;mz9TK
zU&)7?J}{2Un*_aiUz3R9yu?@6UQL^#7qa<YY3A4`gBJ(a@UiMK(0EZdlq2N11Qf&g
zyXz?dl{r2S+uX+sHc?dN>s25JF%i(`Z<nvi<*FzQjE$X?qYkP!CqBEwu_m|0E~L(j
zly^n*%3}RHqmG0px~Rwu>vhptq7z;=nRn5coo$vBrp`c33OGn}M*#qa^<ss%Ck{^Q
zL0?Z$Ic+9WG>QhWxVws);c$f(X#Xt}7^1;(yMmeAh8!WkFA2O8_9<<SMvaUPU0jZH
zxlm7B*O(GEM0Qg!i;v{!dP#MLK#(@bW?%hg79&2)8ho#UIeC<I_sOuirNFOapw<Q8
zmK$^OJSc|?X4|dwd)j#dy|XlZ!hVFL1<<l*_C;`7XAdu-9L|`#Z_hNe5p?U|JDoQ*
zD38X}67l(L(5i4rnXkUkkL)7mkadZf-3y+6_P#2~%yaK+VU&c<wedP^Y|JZD6=x%P
z61pD;o_VrQ;~I8sS<g9bXs%`ucnV)<d1KZGPZH*3DKj*W4P(n(hTZ3({|z=ZA6u>0
zb2*@j-t$z+E;R?QOU*zRVf4-5)ge{|v+J?{-~a!b1x}$we(V>NO1(EWv{78a*gjK;
z?Q*hI7Z9S>6{c!3I)cE<dh|8cf-+o^5gHp3oRAqO0un6<S!@Vqj&4^R!60Kdd>-_F
zjVic&xVr4OO0;7_TGJ8Y-xo5RZSELS-_n4>j=kskjZesWo$f$1h$B&2InUTYV1RC4
zgq~lPh!#(VEx?q=dvKY!!EO*>Yy2foF=Tfk*fvr|a%PYwq+4WEj7OfqMTR3#Cjn`Z
ztFcBfYzaGs!Wy@u5OYHn6Om#tW6z)W7b--0Ok`y}{bVKY{D4{14O{3wR!w;$Q(5#}
z0*H(=F>_QqFW17rM~rPVjbqgpF%e2FEA}cKzBP@hem5jr<`lGaCeq6b4U8!)hmuW{
z&?YHsg%ab8<UmAjryJ9-A&T6h3WQAKLly4<?>;F5y>ygNJx+2#Vj6$UG@<KVuYwlz
z>FHJzG8t}j(AijC1XC<1t9Q19X@fKChOtc&l1XsT;Bl_DD^ylxfN~M%r%Uun>4<ud
zd`vcB84K42S`&LoaNQp4E&x@m7Wz{Q%I2p;eb)RvD4op^csa#TM0CobJM*ayAk2M9
zSWQq7utoF0(&Cw#Xh|LB()t5WA?gng&Bzi=kamUU<8-5q(;sMX7UzLj`am1TcU6Pp
zSUiX%j_u<S9KDMp5v|;1sRJw(88DEGRoxEQfHDo>I;vzWv~o-1gWj&0dfq26iS?Fd
z!7TWSxF^n(b>C(k3P#3^ibX;7N7i2Uh=zqoM<|tdu<VD721K;})`{94yV&KRD;=ws
zpG<*Y<V2K#C$4fiYmyj$*wKI0g-HM`xKKI^3GqUXPka^+ND**-Mfo>7q1p!(hA;UQ
z0-}y~iEUEY271-44UHkIRTDLtaSmjMr!@M-McNhdu%4G;iF0N5QM8bxg|BxBgMH~y
zB~e8DsgIK1R@9jY>K99#Ww*d2bkgj%nn-C3<t<vWcYEw+!KrkPRf(RX6s+x(#-^eK
z9>8(FJjj;30HlTDI7cR_Cvhm+a3m{`01SYkbx?ygLxkT=8x~tZ)EFBBSA}u9ZD4I(
zlv#vAFe<S);b3<{!K(SZLMFiSk6fSfb|V9cEh=*(3K%LFem$l?Jfl+tTa%w#VqD3V
zwk(01DS(KD8U$y-0u5d=O`8sK!qbI!8n%%DYw=N?CcNJo1y-&~&Zw(T$-x|fF!53_
znr({4AvLvL+L579lYG4$*Mb7tG4Q6?<*6%7-fPV$IC4&O8WSUD!CRA#7AQJj<7I^<
ztS4tYqu{)VjTuETy-p4#V^W!1DqorE(Mu90t2JcnZh&~uB)F8{k*;v!<*H3W$dj$A
zS1?Wr_|xDwpfTP=)}inIuaPtyJ6aogw#ulqEwULO>vz*AxY55r=8|CKQZ3RZ1D>Wu
zH;@)|mdpZ!DslTV`P~}oe2`8^9HTm<7(bw7e0a3MJWUEUz6)s+*0sIj$?WS#42=|v
zJ5!{3Sd!C^OjI*Oz)Si-1qX9kn*~B_qP|!Y^bb)uWDmcPJ0gtLKk3A8_rbGG$mnD0
zYc4Z-I%wi9mi?)zadvoNFuqMAhiRlUpdv^YZU0CQgLpoTh*h0p#*2_2AIY>dNdqC}
zNk(MkkV9&L1xSc`bIw)t@?8xK+hH)VLu!QS{{K{@%VOP5YUW2On{p=3^p}&dr=8C7
zqe8HTokambgw5;(&b(kv<D{04yb`P&`i$z=E2OC<Xfp`kf|+Rz?J{W0P%K&j?S=^?
z-Mh6nAqyX3Ox$_&ZQo8FmADp|6$=&X22^4CEm+w4M(ln=#FlY^zU^q0y(aylXd}#S
zyi4P?QCkuXXrGrcE!Yjbr!cKf3O5*YV4Q^E!<e2n7w*nN&(1cCvO~n`!=_}Nsah5!
zDpYKd4;LO*RIOsu8%=ZCmfAt3uZZHlGIvML@O+`$G`QC0r0jT)W2;pS^}!7l9i5r}
z>!|DTJ^V5jA0Bm<_lfnZNd>m8_zWcVOMXw6cOINdXnowWkoxsWR2x!nZ{RoXT<Y1?
zO)XQ~+F)kFaBny7+YB#9u6}PCimKm!G^kXl0K&Y`UKP3LR~<n|{autPGFv^%oS{);
zw7)fMoQe6~gnrMU4O*uPHR-`#W~i{Ks$b&qnc<?u)wFL@Wk&GDa-Z5nazPQ!R6FfW
zFIV>rIAe#b?`(1?Sx7y&CQPB9?uk311)g!*rz4g}=&}>a4xoLv`n_G8^0L3>Bb>$>
zN2lVPhb@<<4(w(6*+8cj=J0!76b+4A3$uAad@{UbHy>Fz8BCJx9F4{Zub~gc!UEBF
zYhw|RcgPtx=*^(QM(ySnsct*?>{F8Xs0=oZPqs~c$`H3ZUrda-5?$bC`ATn;6yj0S
zP$JsOuR*poB8ks|()6R)bXHAw+~gznV+-9=PVQptzCoXc@bJ)Q7Se(*cQ9x4m;tZR
zD(&hT%EspDW^Fh#(Phe%zi140GE%|2_<DUP%vBxh>yj$0snpK1iBJFt_)bX8m}ky5
z7|q1w;@|jgb=-)%62&4diDWj$hIBB-H;m^9Q5KCbIaouu7p%kb15x1g*Eewx)WKqd
zga#_0h~%ceF>HsiS!Q#xRLVv_QnQB!Udv?1wxHrZE2bi<5wXcQN#6w4V0l>Q(J4UF
z+B6S|kf8%=$~qhZA+OB{4O2x0QqoQA!pdBhP@;Yc5B46%BSkX!1>HnxgNg@DV}?8s
zR`tyM6qFM;Oi3RJt1*)K1qWp-agh*X)**r!EUMQLDL%)!@OcbJEaq~d?$l*HG40$)
ze1LEohlBt<xo^=_`9@h02@tJOE{>F+e{@Lj(K|Mx#rVQ@6mb+t69kY-7q=N=lt2y$
z3#OHT-NA-ol=ZT4qvXxNi8tc(!@7cDE0(F%;DL<%GF^(9hz?!F_llVA;F?i9Zy3JB
z07rvYfP!ntLmBIkO6Nm%kvTSytLUIaXTg*VLutrl9f3BYlpaHn5ctyuRe?nlSq;zB
zf+w0WP(VN)isX&)sB*F=1L0s}(k!Wf<<igk;zz0a-3g32CU!W^jx((?x<wNS%L=4p
z&cn<=40NEY`EQIk4+Awq$QXl6D5<4ZU6vOmsv0#cX~Ho>5P-26#0mD9ZA?v=Xc}1P
zLz^Zr%2kQOyRo9DR%?#A&sidox@IP={fh(y(V&KOc-jyR6^O8kVzv{-DANFZ&_?U|
zdPgAWVP3k@!xT_c#e7!btT+yx!Rnn06sdvsPU(9P+6xR+J|tNtAXZNdRd_%TnW_q?
zTO|qn^|&%58Har36*#KVDWIM^tUyI{v9(@fPRPxy1WIf3pc=z~M~?#Ywl^#LvyQ78
zgPepha9<iBY!x3HZfIy&L*Tji7Jx>l04gau=NZC%gz#~17+muPNEzCFLVx7<%tNXS
zz<4nRs9;#32%S(k0)U#A4Q)4YSJpgFtC9tnFDkgqJO%PemjJ`6aIc_~W4YM()%tx5
zXoAFIS;^YG5CmCw*o=lIDPVpMn8JX@TzEKm?-j#e%gY=Hh?!zy6$14nT3Ftnz))|w
zl7&9$7*GZMyi+J!;!RW-vP#fIl0YvCbz3}je4tMeB|(*Keh8aG;7)=!s>i~O5}APw
zK`*Hej8$>?2nN9neDEj+fjER2p{xQns1i`2j}VGv$swUo$;z+KSf;E<+@g&y05>mi
z#uJ&L5ae<)t`&_OQA%`}3!Hq*<ylAJM+7z33Fkvsqu#ubsG1F=Hj@`{kheli_sh7*
z2j_we`TE}lv?sS)ZV3tCa6_k8gM+|Y6H|eKOV$^iBPBD24Wl11KVs@uij7Px9k2lk
zFnneZ*|5zPEaOOOhQP-N@oKi3T|y--AV0bp^Ya7ny|@%*@rbJqE+pBISPpBaETzy1
zBg@Z)dZ|;(%I95ne<7ZK2?-6M+rm8qC(o+oMN%OY-<9xV9=_F76u@fGvLT4$HR>o@
z=9x+CAuXzPa+@Y(!BjI+*i|D4Il^kq2woaH+zgxu)x!X$0J0KR4Wn6JWNhHD4}Eq(
zRJADEzEaq7xs11(7I6lJf|=GxK>teLU1P;7TmnnhJZ~Hj@Tr)@x)2Gy1dKI`2TgFC
z$rp;^N@|TXGD8w54Eu^B8kaTV229$oZF1N^4;h4v`?*HoH;3O%d;LkYB*~iwxoSa>
zC<oxV#32W6QY^ukVms@F#2oSfa%8K|EJ|Ka2sHs0+?;EYN1Q}ixFwl{EO+Qcb@}jQ
zSPpYKYFN=ZE;5BnOT;#x>pIj|XPoPf<{nkymGM+i5YNv2EEcF8?0trIco`>UaG-;F
zSwVta1zisgU%(6YP|(T&dPLquJbd`dj^S-c4TDM+3R1koqCr~X0=g<;2nc0GwQTjv
zt#_8`E660>Lm)(f{5gbvxoNl_%?T(%;s$FY9=y!xGCqW24I?Bw1!E9^=1+wrHyi17
z(tK2A-VM~(0LKNrF{LZy=0M{C>0v`d^H%eCATqrk3fDyo1{X%7Y!$A2XlD6I_nb1&
zyWsAU8>aT2!Qd$icYww)D5JDBYB|iW0>&O=9G8VHJOUe{0f;cc+g&k2Q69r%V8=~;
zz(5=70LAh+$q0#5xKS9>*F!^sKJXx~b%E4cvnb#S+1+43h7VZwW<e=s6~xJevhs+8
z2-TaNfPFjr5Ht#`NQ&wX@WGW6soXZG?-W;>*aipz9}3S{;GB^8xQdouyFmXJU+)4~
zRdFqT&)(UI`-Fh|gcC>rVb0+MPZ0Eg!2%*oVx-|=8xSpuN<`X%NJXn4?@5d_T52Oc
zuJswM_`qkq;#-K+-qKp@qqepn#oODLR-m^kD9`_I%|1c<{lD*9$=-Wr&6+i9t$FU*
zGjkdRrTm-(X_S_y)sEB&k`}DIB{?vKr-&O8?pYA^E~ePS0fI^#PdFQ{NPhMnguD6f
z;Ys<6e8Ve&77R(cd-ns*0JSv^l-!6V<5?J)DM?-M1<-}3YqXT=M3DfL=;OOq)RD)d
z-GXr$>lh@oGhKEY$Dq?ilLWQ+r9c7H0i#@<v928w93UFT&|!HxF=b3`;#UGtxEz?+
z5k2kpKqHoksU;brxtNc?DWoE>7{#He4btP_apN8dqTW!`TzL2SRqcXzqoRUAOp-<n
zGGYQbF3PA=MKF$Yn}i4$2~qiaoQwt(O@O@b8obcy0yVy)8DLbg__VVpq{QalT`)o8
zb<Mf6j}^ZIugl0&Q@V)LpbD)=-qTv}$`duL<4W1kc%c1%gMwu^ELK8Y=8DNZJW{8{
zO?8t$%AJ7y5+f36myw+o;&_;A90}wClFyh!W*`)d932m*A_GVvikju7jKw74$7-5~
zP~-B9<fH71=<@JiBuE#YHxi39W4{z*BOgIr`wLFg()@6s))too36yVz0Hp5eZpErg
zNjul#ObwC#B9I0GzmOrDtU1wfJu)&7Drh97$p}d>t_T~55|aKJ<>j2yA!3$sMmTJ&
zhB!0M4}q3cxG_88P)-X2&RK?{8V1G_jnklPfh3n>_7NfFlM#flDKvS$kqJA1=0WDb
zP>)4MF=*r?EY<CY$ijlN=N$$nzHOF-1BsmEL{q_&HPVb{m9NDsLc%0I$T-%oQ&NLB
zKTaj#nww|ZBrGR`-Tfco0z^m{32is{lFz)LI)4P)I4t4HwRSJ~1mTcm<snQQXfR~c
zmw>2l?BkeqN<cuAZhDyy|2H`5r3}EF*ns=E;hZj57&s$K7yz9yJmW1kuqLer{NN;2
z9^4GJF~UPE^#vH`M@66zVw}gl#5<SVw8|QaTdYbbT)V;91f^pZ&K$xgM>*_n=>kur
zISNMhEOe_zG%G&N1IB4Y2)MhaCV$0FM$`qq=+!;XI?T~qhcB81mYY?41ut-Szl%2d
zI=sZ@$YI4VeC2V|2yzY|>B-k&-2wkJ;aY2nO|n8y$C8n>y~Zy2!oiOs+g8364pSZK
z;cCL8yrCE=8HcMpOudZXi!~g2G(Bp4jy0wCnfp0vo2ep_pgSarC^s)^khUAs%<~%q
z5j(6S6~FRi{SfIEafmj*o||)aG+yYJs!Ux#n_wbjpvm}FrO9N9!gi6d+2@^9vvxol
zlf3S%*J3WqR9K}uAsQN=GmtZimTzXp_tS(1QF}hEX&4}Fl<}3!AEh~BF|rx)=Ddam
zgPg(1)K58<vI;^SxE?>OjJhb?k=MK272vY|m72+o7SofFit5sQ+^}<##zL>BD&sdw
z)SdyhvX;#;I>>dj;4w;5+o4r8rdg>r>*eKLGVIq-++mnvL?G21RferL#I4JM24z9X
z@1i|Q)|v*_0_9sFf;jALB%|baVM(d32&yKPZwbr8_Vie0C)1)QJ$r_JnI(5gb$ypn
zo#uM_QC(v^tI4|LeRgeU&SZ;dT1G0fHEPZ9aiCd-ZC-D!>M0bVp59pMG1jf{O=Dgq
zGGrR&C2iOy6$%<P4{?dly~M8{M~dDE^2MjDi6R`Lo1lN0b{|C7d#0pI`YJXEn8uMx
zH~WF1eY4ZR$myx7xm=F-JcD=b4&gdf&b5Qb>4y5I>0pLZJhkN9B9G;ol<j1wrh0W5
zh*UI!@`F5KSf@3a+N5o$Al7M+z76<&4=YP=vL15fQ!+~E45QoLFJm4r$VFWy*>1y-
zcm0gX^TWDbFbh?c)l+pxz@hinPY7@IK7|F@f|(OXLy>6eYV?|zVM<$5Wy`hFZx&y{
zC`>0iRg&L?D{Hn><%dOdSJb<*1*6aZISnb=!f%8}=G9KxUf$VbdmsBudcORw*0A}r
z%9|Uvmw))cLnjQ}IC%c(g;S<KH*d=HKmAVE-2Fg$_;U-V%z6Rb+t-Zr-v0F7^a~3o
z&3f+AN&Wq|$Le)&kIarge&LiCj-6NZ=C(-x`t5SP;ji<0jy?X8;>y>`Yg4aP=D+rQ
zP0#TU<`Rn*l%IUotbVoMf1tYN?x%Fk&?!yj&9lzyv-PRm@Y|jlKK$zW=k~qil9{PL
ztQl6b<AH3=L-Ws#{yzWQ@-6>5C4JZLYSWc-r$!GgnABw6{>0m{?#f`tg2t-RyBhmN
z`%}R{jyt-0SEA~+`HfW<k!8Q#-;ug!QBC6ZgEf=JA6mA2)5}K|*q0A{NA!K*jVmsD
zeD~^_P2ZU{X8fVO%RhYXAD3-Aykx<_!{1%@%p0p$_d9ax<o$cDs@uP3+F2idzGwOS
zM@~I&!=}~Gy|8Kd9sQ21o-%OHm|2J4JwJK)-K%>aJhFP${@Ke;>$iJ+-|@Sb9W!vx
z$|+<2v3x@1o(o6z*tP7`14mYkIr7of$K7*aasTTNEUOy&_X!i8`~36XqmQgQ`MD!2
zPTv2~>cqi4E6@Gpjny;Xe`ER5hYlR*d*sN9Q}6oMsxh}cwd%Cb_Dnc;$BX+bFIc{!
z>VgBKE01hmcIw@W$6j#f6Jx5{_MDdZ)r<S1)9&GS!uCIZ+|K<kA9v5*v1gAz^xXxU
z?m2Ltx@Yec(f5Yk%LnZ~arKxBcQ3D*aB$V~&klWf`Dd#xTXA^Pf=h3GW681CADO@E
z>fNKh@!_6Rzq<duJy(6WdDgPAn<kXLaQM_*zs<*g?ZjP6CmsInu%cBvLT|;9+2`%w
zd|qzsM=QL6d#)aF;-01FF5Z7?V*E$rhmP6PZ|n!NFD%>q>*ZC04$Meif1s)NoR3#k
zEjqA#!at9!Jm%`1t9$+HS1YQ1w&#R1uX<xl&AdG;M|Xa{wEvNvqmRF3?~3Y<#VgV?
z_sl<Y$ARa<3$~9Ru;cUb1NIylebU{BE6==j&mixH%lcQn_u_Nmk9YAyTH9Xix$}h=
zd)~9D^7W^0oSWPDlgno+wdfN0ZL!B6A65PM<DZ{=%At2pJ!Qww`_FlQ#pElRFaP=<
zFTU!6!*lu{7p*=sTz91IYs<d*?Q<@f``vGBxcbb|_g#JNvZr=kb@@||d8*IuC1J_q
z-<`7mD-+IIwq$Vc(nn?#S3WXxRDNsfEBRj}N0xqT?lGm`9NPPekA~=xyGD+A{+|`;
z&;NOK`sv0i2R}V|-l)H?UUb&H)vJzuZb8!t&n-xvT=|2#s@t9@8rODRI`#B*-<|f`
zznIeB{^guOhi;g8+MyfH7}Y*zXq{b}seJ3hZ1mR9=E~ILr&Qdz`;>~c=MSj3^S!cj
zYu~!+YNf7h6y4O*w9k*99i4LLZ%X^D+%mNG@{6ke)Oqft!*jmT_{WQ*0ljV*(0ARY
z`IlTW_p9dWZ%%LelRo?W4OiF99Qj!B^rv>!9nVi<O&IcM@0lNdrSGC;OQz&ASD!Sr
z^pSjW^lP=r(OWOlB_AEr&mUsc$lY`GqCNRxl@E`LUi?>-9yn)!H?Udx{uyP-=GnD_
z^9x1>pDnmz*vJ1`S>5piFC6yp#ktz+@{P^2Pd)1ge~F3?-B6x8bVHAH^u#g4Z~H?o
zd~3rT^;To1?5@A~ead#HitjvsVDZ}bdQIy1Lv|WkE&50+wfb6mtKCuY<aIZVZ2EnE
z<jw85kuN2*8Qd^C@2%OEyWzgB+`!iQ%$944PM%k)^P?x_biSpOT@m$}IlrBg$-U!e
z+HWlxY^ID`u1>E^winTAdwwSW_sbVmW-d>+S5{`i%5k%lzo@U@Iz72%jT!v+wR%pk
zC%+k$J#}&a0d`KmwSHJqb<r5F=;AB<qWUZR{_l^=H}uwJ4ZTe&HQm&fUGcS|<Qy|0
zY33!H-mf{;`X}_dZc#12_L-_W(^e)^_m!XYPTx_<8G|k#HFZPtsI^gZG5Up~-@VKL
zbgUT_Z7c6PwCnfdMyA?zeq18c=(Y7%_x?4~eOk?;8(JriZnr}?q&ls`DLP;7^~yKS
z`14?W>zs_bHIr$7ClfVJshky_o*!)K7D6wZZf~!sw`R-`HCks`g|ytVOt95vYPYmy
zQjKdHnkI69^3*4b_^q`1u_=FU<XwDWQPJts(61@eqpPW??c~WP2EBD{FkPooi|BST
zCB2jl`kUrDFUr(0Zdu&Nvon(oDoWmxi3T-%bxCgOo>9Ys$$I!&Gv^q3rqc7fD3{kL
z)wSki217xk;@dp~%}A+ZXDVAlf5c$N7{ZFluz*FGJqI($qE{<p$~h<x{WfM6vw?3E
zmMV#KQAtu0Zrr>{Lm$>)us-?9z<NP>JEvvqTs9l}CVLypRADNRRO(xi)r*2K!_VO=
z#!sq2F2)oS=~jJu#JRYK;qa4m&nNK2-Aq)!Seg2Cmztbr0HZ@?=(mGJqb*5S>Js|z
zk_wfdSZShq`d_(Z?7**~8Fn|g9XYaBv`zGu|5k23!<6!J6*Ms>nk=;1@ZC+q-8DcN
z)h2E&v<3mVBJJM0h^rdPV>&s%TgJW375K|=Fx3}KN2fe?L<X^MFpAZ99k9@fWPHb;
zag!>|uvVF;>}BE$p3<T-e(2-_g{Ma5#ck!?e+zm?TqU3deB^UFGLZKZf{@=u`=8&t
zFimlmi_do^8mTP<3l-S=F#(Rq@Gv%NwN}O;s*@{<|9J>o>o+s%QsMR3L?rP+hn+?w
z0s^^N6?KYkp4Q?uA{gU%<d;DfIKz0|ht$&|Tnt`{p^+9h#!J~){w(WEbHr#QKUpKx
zCcz%R>?=hkgdYOL2LvNrqEp7N?oHcMyPFsaJ|*N0PA<sB^Cj>^5T`Oi7d&6kh*l^N
zS*7w^F=)a~tfC+^(d4BWG2~8|#22f@AUtvey3_wki761@<ta0Q(Hv0P=jOxg-#{}I
z=chinj9=o?a0zzn(G_ddNH|VyeL^LNbZEId5Qaz-wR3d}Mg(><(&Fg`BQ$w@EX3t5
zIy&fnda^Lm*}#xv@Bmzx_;}HZJ<bji<kMygsu^LdAjIR!BkzM!Ut$i*;F2&Kmzicf
za>75t7$=Pe(d915Z1Nh><G5+{&l5Jv@1pI$knA&BJ#*Cw8&^(Qzhvo#otNDH=~)jy
zv+{(Eho?OF-EAB8t$ON{?GK-L`HLG5U-sY?zx>CNOV({X@YvJS{&DEwf@ha(+r8wZ
z+jlJ3HE#I_pRQi8Z}#>*i%+`!-39B1EdSu_Nkc!~e&mV8C#>7KVEwr5yJk#Tuy4xt
zzg_X-;eFp(KWxFSb0+Qo^s?=Hu6S(IRhK-wYr$Vu{o#>AU)y%*iieNPzGUN}1%Ekb
z$A)*lbNjyK4<Ekjl3R{k_Lo_I*f3++wp+KI#4xpD<$-;Rx9^@Y{_ee#SHAS!0~Na#
zd^&sk?sLZ9^U35<PoMR{1rsLnyJ-6spZXsMCvQCXzaPBw=8(L~xBsOGgJ$G+)7E(-
zYs!0M!>7y{txu}nI$SVjzJE^jJT+osZ|j}qzgaY*=H`a#6E>KMeq-}letFU0>TpnY
z_;Kenu+9H;vZE%eN=_+`E}UWd&8auN>O8Nss8&rren!F!Zk!jA(Yc|#D=k>&^)qJD
zoy~#wrdO$L;%YCvdhVo`<}|4G>Pm0x;IXPbKQ}Rxdbib^re>Cm^!f}Pk{GzilviFn
z(`zpp%THqt_3mnJXe#HOreo_^FItvK-1=F0)NfIJ)aC2qS4#5P_x5tW)8FeO^{@Fs
z%icv&t_on3=<7ho56i>E&VRe>qdutwUjmEU6<40Faihfke*kqzYC(4iEl`O#THHo%
z%0eJTQFxj!cpVkm71N_WiSZ?nN~%<L88=DCk!fPE^Tgs|g@pV*(*P$gH_t)@*oe72
zfrQLtB<f8wvC9bMCAdp=8|0X=7CQM4)Hp8wX*#IQ(!ypvn)HOq*pQqexmKYojr@*)
zg^1T{X`YP=vd||-Yw2kv{<Z2!;ldOof~C{&CuY!5-00OW@VzeO>A(+4ng~_4IsHD5
zAYH<jIS<~%4?CkuEpdz05Zbm#&6A)|8)WIB=(D^qY6y^zDVb)O+fdr@bEZ!9=?V;M
zo3-YlYT8T_@|6s$a&x3CSELUyhHvHw1bt+qW`5q(DGXn_k;YKfSYm=^`H)}VqBO77
zYIwPl6`p*;GkMqC=1Gph$g3DIFwi4Zu|{AlV6jDO{v74qB9^7<%_kw8p8wy0@K7cp
z%1PUuax&wSyt`vMNGl=jT&Qg&zM-?@!T;BCbZ?>LSrb7rehQ$|T#gIRsg*g0!8YAE
zg0v`W>Frcesjwa@yAs+xjm5lr5zVUNye38B%FslH2+TO)DIwiJ(^Cc3<h*sF9sEca
zLp8}$3JLeX(^=&O79j;-<TA@Dt-Y+$pd^}gc>sqX(6TNdr4orC6BiR>ArJxh^v)ci
z@{H0}ay=kX=6<|Iu#k8{6H}@-Gf|dGFq#1q6^n{W8F5Q`B8yh46S?@YTz;;eB~?<?
z0|Mnk4N0L`N2qiFDv(TM?}Al*JWc%8PH=Hrq^2QmfhWJo5EW7ATv=mq7V9f{w`YVR
zX&6!1g<OPSXNR(^XUU5=F26uq-$RL%Y}jkHh|%KuU}cSlt#IbvNl_#U9b|n7OLBpc
zE<HZPF>G~fkxZvhK_Kjz!?blQn`TVi4O%qfMr?@M#4Ms}#*hRlc$yITVIG4a)a8`z
zR#2@aLPm(EUU5Gg!wZGM%NRWh<&(Ty&?}Ns7>!gHh#5ypi%}<p&LvOfcTtRZy1dZJ
zSlnG0MoOZ9QBt#HW>vT%X@jH-=O-KF9;o-(P{?l+3Z$WqETf4homUydz7(l$o-%c5
zr7SH-rR2Zw`xgm`91C!INJaDO7~l(rB#h{0wK%;j&5BmL|H*>)M+wzjGGD7b669Y-
z4)TnDu>-9%8d6}uSwVB&sp*t)YO8Ok;sS!Un5E?2Ldh|(K_1Y7-$RoFDC+7pWf3Dt
zfYOP)6n59YkUY2~in-F_=ZYPP#b+dsV=0yD5X;jl$Wm}r5#e0Qgj?|@<6)s|cxsjR
zzTiYbz9xx_AAa<j6rU_XsTl<p?kG^wxR+rRWAt=DgrQUp%DiZnC%tls3<SeSz>7%B
zj|Yr27EaK1ghWFr5-E6e$qIVQ9OKNINaT&7Jd`8j`pNrYhe{hkmdY>@dotwpSvh4r
zX^Hvd->IrHme-z;K1NgeA!y`P#m603WGy$IRcNMZLnJoIb(D80`4Cc~S#8H_f#mNQ
z{FW#zMUAYyooZ;UljnW(YgN{(i<>i272XnrK1Z8SLE$eHJ%dYS<z~5V=9i<i#zDhM
zQ%FKAmzAs%w?M1h@-WjBO@0td;G%kNNI*>xQqN!`o_M5P(#~kEt>nya-?-Y#>we5K
zZy{<_Gw+X!jIvgmKF3G2Ot7=A+b4OUJ4@w3Tceb59E_)x0HT<{xqOWj+O-YNZx|p%
zTAa`{Qz>YL+sOT>3BL%;-4cNquoeXaX|<ve#`SjiCD6ro&3C!Yix({MX-+VBXj6q@
z$3zLhIxs*Q9f&BnJud)D!ZNEbNr-iQD=$S_e32Eihc18XZ^2Jn;9irA=jogw8{43&
zhj=>0)>5czNIUQyt0IEP5@V(QQb94TiA_P`EOz&(zlLgtNNnaP3EAbT!iR}OGM2He
zv?Dq3KroW;FVP6Cs8L~<_OvBpGlMJM(0pyB6@#84=^?)}iLdG`E6^jXN;e`}c8Q!~
zSKXp4RD3nlr@wNkN@zYASj$!{!lXTl(p18TJvfEBC<hr3Kg{|*A0`6KlULSw^2J*^
zJ$<RCGs+j80_G!RC`WR9($=c1wixMP3y_ym$^Fo8cN$4$)UHJKQl5IVNX?BN3Ni>G
zboJ1C-t|$xDDXV2=zl-1yHZO@Rr9Xx-&zxfrEPxHm1S#R`v7)5`$lE>W&wNIwUb4p
z#5Itc1`noQhm;9_l2W35lf^8Q1HQSH{3J4`;Qi`#)O&0o!xlvIJ8YoUT%3TYRHA7(
ziyDwKFio^XT6R*7^o^MGHkuLa>6e6+Y&nfoGo3*TUl_54^#A@V<bbJ!ujMOX*BQiM
zav?L^n<uTE7JDT4dS`ix{XLr2iCP(oVbX-UB|zLjrH7WOb#$n6T8OQ?=ncC(a|0<P
zJXNb2a*C<6#;C-bhpAi(Z`+!PtvuL<lvK5KFanq9G`m-2%|%(?hVTkB)83ovPts)T
zX(MWA;+ncLWEzFH6*k3WBJs&u=62xK*_+{Vn^G#vC2=@6jr@7v>!Z@Gto@`kcQ*Q2
zIo8~3@d%wNWMLOI&PL^dUzQ7prVWflYn{xf0hQ`|*u5htZtgO=iWn;B3cgv|r8MqP
z^;X$>-z!@ikelDnd7LOB1?i=~lJsqT7#*gmTDDM7C33vyhlgZ~3}q;;F~}2Sj3<>>
z5no0Z0)osqmzAOugFzj@$PEIE(BigSN()M2SuXJ%jYQ@c-h7Ob&5r_5p{<l_p?P0(
zi-|qU+lJ)*7oeR}lTSYDznf9EGsgJFjf5$6_zhPK4XW5-G+uHHLpraB6(??Dzpk_V
z(wC&`A5Bo=Nam0jL=9xNQC%Qp%&2)<DH8w@q?z_iM#sz~LJVp5p!Km<Trs`IWnC)T
zZElnh2iB8-prk;kK@N82p)bkRJCa__N;S`Q$jCP|TzvnJ%^0cs0yfq=zLE|nFGvhu
z$HFj(wLTF92WV+q1*FqLFF1*Z#@5CcJ_kCj^vS+ZfcItTB*QadNq^vwI4ze0%CN!V
z!c|6`lrKX)aRL{sHuuy>p>3JQj6gx6PH_Y6a`V&(ejU58(pnIrhq4`rER~gzCgK^K
z#EuLIo?7!1=vA=4XqeDSS@=1??J`py^<o#X9>7NmOLH6r7USZVyyTWl$X(8)Vp}ft
zHX+lr&L<dwRy1`=NH?S<S>x~&Gu{K-&=tRNt(;YockhoW5C|V#aEmUY0g^gER}tCZ
zC;Q?KT7o0WK|UstyQjI);Hy9!jMcm>v1BE@lf(0QvaW%Y=v7>MB#B0<8s;8~Ye_Q}
zKYq%vTEJSB%LuK5NTar&@l{iCoaG&r1{yvs@bI~$J&@nvG>qFsZX9l4jf>GIJPmgd
zhUBbs#L4A~l^3N80R&6C#ZnSB%(g(Q@hIIW99xMP1C00#A?{G#he?(}tP#JY1if=u
z*Sb?)X+Eq`%B1KHC0ONLi<QNtF>Qkp?#h>_%_3VE<)wU?B590V)8`C=B_Hpk{bSB2
zuqxvsK^1EuX{xZ50Rd0IG*P*PqmJ9IC~vh0Dj+Xs0wl`dOWW&tN;IdD+~mqPJC-=h
zgs?+6X-DU5V!_QwLkbSSCwIfm23B=q4WklT;|C(^9`R3p<JIDgR44Z~=hP&rWn@Wv
zU<si>Yb&v^nShbrSqHc%qZD@hA`eYvchW+oxnh-xAQX|RAsp32JGTwXN(?7$I;Lk)
zhXvCpXc}H|6A_RoU|hW(?Ofo6J6nvE&EZ}r6tWB2J-cs`=|Tnsv}V*k<6eq+Th_x&
z%r_Ke9SOIBLnAY_Ax>QKx#&@$ur8b=m~nt22uq>R5+dW_xV>~dM08kza|*dTon|{Z
zEYu8k#1IsQ$VGSk3+hP_mjr1p0jbL>M+}3<62*~`DFwCI6HNebjX6SvraMLLib(|4
zsx5*RIw)CjqQzkf7aB;I)L)mXaIqAUCMT(m8j>9n5<@^dho=^5Jert{h~q#b6;6hl
zq+*;V+G&b?3#KH7%|*4EP^JN0%2<xkKEGZo3K^vEHA5c9q>vUbyh863pcG1w;h$$6
zP8pv9#tL3q_b<Q%#){A7II^CITfX|?7i(G-SS1iARxV9V#_<lUYZ;Yri-mOBDAlEn
zLs{+uG_&sAq1~~tg3?*~DPbNa8@W?;oZy;v)bx-(GtLI`6z+{sN&<$<HJQqqHgO}A
zjvuOA$D@y+;1_Dik(5(E<Xz@XsRq80zAqgsBd1LQ&KlyfX^XqHps55&v0^riYTyzo
zG>+Pdf>usQ-t2|caS=xo<<PYjU1DdET{CEBpo;beAG!|XfuOOhhB*xlwi~>5(xUWP
zYGJcI%2(FHN@oNVbD2;YW&?AP5?(yBjyaXaVL&?gG2a(p#UBE=)(*6FoLpWDk<6ie
z37lTsjv|G-KoggZOO$vWAco=}&|Fr+(VMErup&~tB;(IF$UUaw#n|x&(+&6wC`kBN
z?0}gNEt~{|i57?GppA3I7}nHz^z@*QN_Uid2AtuN*adJ6pLHH1atdvD9jtPJ6<V)T
zP+GFqN!w&0h;&_?I{L(rlqvwQa8tC3Xy~0^86)wsP0nYOvQFYSOzxTsCZ4GmAI`W8
zInV!nlU6KWKzmXd>jEn*kPocoqMV3H1f<?3o^sBd3$(JwIewFnNZsI?Nb!VpcwRSF
zEJcnvFU9o>JR(YBDnl4u96hvr6k#&j{UU>eP_W~%Gg1{~aSzz}M(T~!5b6R88)LSz
z6adL>k#<i7&@tFBp_N~+$uBP2OG#D?Ymu|SmlWcTm>@vfIn%CjrNt}YX>I}(vVgy%
z;CcvUc%zJ6N(DyT&}a@Ab95{wB}OYs>Z9>+1Sx~!#^DfvSPhU_p59Tic(y+Fmhh77
zCc+?<p&7)|@qug7@KzQ*!I;wS*g|(@eIsu#!X1#jY~Amig&RD09qTSFjj9fbd=p8H
zv^b?tabV;ws>gn!k)jZg3qn;d>xc``B62w}F;Tfh?Gh0kR~x$^0;kSEbz6`xmeLTe
z8UHl6u1jXKiO-A#j{+E7aO9<k<egn5uCobzNuF{cFON=8Linyl?{DFZC!X4kiSbGE
z%Rovd%ETj}h0gO-I_JE?#d3MhC%5L1Ld*J75|J2O9Y@2A7KGK3I+B=f85E;+$v2?8
zy=*F!C9zjbrX`e%TS^|%mq;f<sMl=);SoIkrcwuwz+O2sNhEDup2Uoxp-PU$gNwNv
zZVnLDWvV9J)y$ZjFsnM89N15CT5Jx}cJQDhdNCKj$x}p?Jd>WWNin0>ExQX>fsLQS
zo?L)PxB}E!v9P?SIv&247cVUxi`!*v25Frr?h-)ef@GizV7!uUX4+{U%OVlA+#F6G
zbcXUk0tbPXN4Ca!<fc`io23_zfrLEKvcY-d^uUQDFfoa<0p3vA0)mGuum>C)x;k{#
zv8lD^0^q@a!ATB$x#i%ivBZ{g&G`uOT@tXNN2}D1OUKD8E&2R&XE(^Lq8!VJjhhf*
zGdH*ErX}#ROBpl;!g9l|h{16QfLOptA&pIfRF06RcATv0u3!-2mVY4G#f|DqJ8QVZ
zO@;xQmv!fp_Srg@g<jrh4L+-d9*2nN&Nve)`SlJ5u2SN6LbW=vl<F)5w!5c{n;nQ{
z(~@G47r)4?xf1b1ILZtq@MX(71hl4LLT9|P*aIu=!pqvabtEp7aW&N(Zz;@TprC5$
z7@WTwDX2ov6n9Thp-V2~;#7J(G=Jc<7G{!+#Fcz}m-%>tV>E|kN~f^Sq2v}1mRyTp
zNDRy|5<-~p<^7YC{vROBtR&LiVBl{R8b~7@M-z9qvlU{1hU=&SaQPTOiU&`KEgeF)
zkRYVY0ba9&$-qQ~k}*Onn&#tY9HAgNVPsM_lwbi9HsjUG2$H5i5-|9?>!@|S$WR<2
zZw%saDbnvc(A?z$jJwA-1S*a3Q9%Nug^lrOrLy@r3n7JztE5L`3$+`GK(1O{yC-&W
z`bVBsLEX{x8lmtc)u0_V#yAB73s!UirNt@xM3$}*S3T!N_;jO*(pJJP)v<%Rp;cvX
zc4Q<v$oVknC=yB-oNUF8CGF7kVWvtmX)OqisoKfgpfB<Ain`E@1hf~NJJ!T;ZM4pu
zu4d<|q-AEZHQIpSOy{c}h#G0#qh7NjlV)|TmnV1Iz4xPLL~SVhmdA=Gy+z%gMw2MP
zIc97f@jBb<Nh3$nhGM^t#D5v(qg2|;1nW$l)vhSFk!OgcwN^EOu2=7Kl6Ae*iG1iI
z9UsF@I29huck+^>G|htNd1p7t=Z!F7S!d!!qtbL81AM*_qGh!TYU*h9Jk~r6;4M@K
z=?3Z+Q{=XhdK+j8U=(QS!)5Nz$X{e|@kRNxAZIYF$+d9eVi8t;vn#8q%qSgJ-`2|c
zpsF%8GcLhFks-EU7EJSq+jORMtn6D#MpL~YJxSFtc50^il`oYJ-2Sa~55^wpxgWBb
zp=N-blH^Ca)bja6WemS7#L%x+2NCB;Wi02@`dZm)dHtfOVS#Ll<Iu2Y4jXYSS*liB
zIeR?ZN_3^0<WyWrp}s{?+*&oCWm26{l-5Bn#;z8bQrfF{h%+i0qYlj(MXD`tgXz(h
z_O2#XT*mmFB@;m@^`p$|QYLSUH=<WaCYEZOYhyq+O(m1`-uJcUWTle1mnJzpRx_M%
z?N?K<j{TcKwo7TP(nh_akSeULHu;>+sh~;?>m;ix)130AePh(kO<JliDx)6y%+Nf^
z9sF7RiJRs4HD*33NyFU7DU*(hRWzz|XamxRDpiw88S7R4T7|<@rhy6;XcHx?QhI8Y
z)M1FVx=&RYh?6Q@q=p5<i~ZgpLsb{1dQFwStkPCChf25nDF|#t-(ZrdUP{q@GC>!F
z*|KsmKsq!g<Q+>UBpdUx=i?jixvx8@<t6Wa_9xYgd)|?H|EIV2vCpm_{Kuzntr=f4
zJGvxsNA%${oz=g)_0IITg<p?G&wp*&{#09fe{`#UZsF_6p~I&%y?y)J>AR=hntkE4
zNfpm6{6*Ej{&lyW@%rug-PMW2*q%GQnHSueJ>#D8aX)_SvPmxtU+68WT9^OtbNlsq
z_qpMTXVzcVb5T`!?f;xGGrDF|_3*=E(!)QQ)Rg+~#H{GRv%&CN51p}a(b98Me_z_8
z{HOnF8@_X0+wc`jFNhx6HKlUPZRb?K`*dyfnA3VhwJXo8n)t6i!MjggSiEugq^iBE
zC-rFBc5U$0+lP3YPnthV^xd|PvF^6*(TRF~k5w<;K4R784I>VII%-7MryED@z3a%*
zy|-+hKYsJcsb@C#P8~k5e9YkkM-r=6e($1HE5CBlvXz69%T_+9_HTac^23`izx<_@
zAM1x!e4P5_=Iz(*-`wLzn|587IK1nLo~zE@8GYyM)u|;DPQCi$31gOSANS(PyT@(+
z%90OG9eVNyr=I%Lm-`NQ_vPh1KYsc0;h(--RdZzNh~su%J*MY9n{Uc(-h9*Oza5%!
z!N)IGt~~JK9lbXF<BoxQ5A3*L-}W769yxTum?JCe#_W0i<jMm-I(6K)@9BTslFeUF
zT)cT!<r1#F`(E#}Z{O<!4{iSH<XxM;K3ViV$V>jR{j2-0+CQlO;Z0%wkDL3auiQJq
z>)Lx#a_?Qw)*O6!U(LbI{eufP_YPJa7?fOfq<8W=E04c?;>u&{maRNK|F4yU@}Ir9
z^zz-$-gNo6g*#IlR_>_Xe`IOZB|A^8+WqH8PCLBo`(qZ*m=LU*Ia}@9G-l;@pXz`9
z^4iVC7oK)k`YRs{>i6x>2lapV&g7VVFI5ct-_6I>{O#GZy?ZWCCZ1iIte9|j?{Paf
z^{(0XY30g~KdSiV@&!Ho!`plGd3O7cygl1@c&k4x8gt}Oj}iOs>YqRGSZ}rDiDQyW
z-soMmWOM&;-{wJ;e|oTIuYHHE?R8}H>67<tJiT7_y>t#%YSsQ1%2(}wvG=_Ht*-s-
z>`|#VKb=GUYaKQ6#(S53ZA`j(;%V9Jy#KvFd-w;9m;d$Ub1wSp%V+6+H~wVw3rmw#
zznpchcggI=X!j2;iOyefadh8Z)uW!e>qhVTr4Lu_FKexR;Lx(sdq01#>im@>ldrs7
z9A5m*_3Gk<$DFpUa`1==PxcMJJG{c{J$zK~*2^ak_*+?e#q^7c&TqOXQ?c(SnX3Q1
z^R~*b|3_3ddvjCIcYEe*UiT`ho*Z4#zcZIQ>EnaHuW25atbC?6J>Z#lMjf{!nLO_P
zQN8<pu)V1A^X0wIy>eV~+WlRuUp?uk{d%2reaX{(OG>8AIKFu1Cr?&0?nsI54KEMA
z=xfi9%YOLJVZoID{Yu5+jrDbZ-FQ=e=#2+PM>jsw*gR{*h%K|S`S1K7;JTuD>|I6C
z*t-Ug7`il3)$j79Rfj(+9rpNVqmP@hVrp{61wE1%&pj!7@!ac1EDNrwIL{lYdk?SB
zCl62NUwN(~|JIYoWZ%4KaKqd4>(eLwD6Dz#`B7@nGb#1MHBrUBvV8j8Abn*nOb&i-
z^o+s(dFP$QA0K=tIAw+xJ#&AuVn>=QnN03F&^z3<z4x?5waIB$)_Or{bq~K^wg1CU
zj`!F6xwxow+lKzM*=qDhTB$c4rPtPWq|RGbLOvDER5#_H@mj+Byc<WGOi^QMh~Jn_
z4%AN<zmUIqeJZ-S^K@k={~~RRZXYpL4M`3z>yz9VnGt#KrV;r>MgIMUi_{%e9T#0+
zGrjH-)i`28<-By}AG7lx|L1wpw4@)^Mdw6*G7<bnUz++xrame;Yn0db!!cf;7w;{O
zs(zu({4^g_{IZ#A`V61*=P3HtXXjQlJYOH){N%*czzx~OH?*^&%+?JsHwDqWn@TFi
z-88Y{+!1SoDBGE8Ttln8<rTFhlgOiArReu`nqR%hGPzpo`}8FAO6hzb@0H5?yz4?U
zv?>=2^+%`E<#eiisO>COse9{2*!o0L^)K_5CD$drs`6w-G(D|Vl1}SXrKc9<i$+B3
z^ZccEiPt>hBy_*;<KpPz7hg@*RXr2cRppa!dx_w51{tUO-%6L9{te}C8&OemM-AUa
z(khzdF~;z#>Voph@BVo}^^mPey|!v1Bd(HR+iq_-@1AxwQFYY?ldcKEi>~o|*4|Wq
z+_VwZQJCdt!`5_!WvwmrPx2pT&hO&)Y33<`NVT(qh=p$L1T_anaFvWt=Y^uOjEqz&
zPxr)oF`cP5ui6iq83}ZHjP|Ro%BQ=MSx<#?ln&-Wn_~oGh{SNVEUQ%_EAPztH^Yg|
z6r1_1V$qymi#0itE^H94wGd<THpE(!XDl)<Mc>SFoS;E9vM4kdFrZllOe@O?PK;dw
z74Y6{WzBM?tkRTgdD&&O))s}MgUZ)l6@|)@Mn&wYrk7UwPw2CZ%a=VrN*N6&aUp|)
zp(Ko|jBk{YvJF@*7fLct&8HPQ!e=mpE{~_sLDNXE7XHnuC?~u|aIWhJx_@X8N!=_g
zcr}8RyJ~s130;=p4xS*|)A4iODe#jpcp7;U#_$0L9&iBfO<KO}p%{$w(6Ln9&$<vt
z_7F-~VlhqvWY3RgR4U^^tNb*BG(0A<&|<N`Y6d2%h?izC>LJA&fa+jXfNJ)eyTGu>
zk2I7Ksa4Wq2e`vzo=Bo{a7Rvt*D%wzMZx!ec>~v7<Rc>b+6x%>-j@bd&;dWiN!7|z
zbFmaxMrZ(=!on^!m$yb_jMhfRs^(a2D@U>fHySlMeiJMu7fo@oQAwh;Yetkrz^TIB
zO-lV@h&UZ{L5bThghNFUB}1@AUIlox1Us4%aY;T^at}T100EXx3!bXLr3;t1WISrW
zKp28txR?vua#^n=&9dQUw>sP<Au>v`Dl%B7OX3%=(Jpx@dJeSQA=F&0c$`=W9kzfE
zc!46iyoMUqF!+dpPehXs=mm(CGPE9wR7kJ}hYmdk#s$zYV(ngB#`1_AM~Or<Cr1cd
zd21#=jT6{K%oEleO8P<=@Rp1Xy13xrql=ahd{~WedHF$4>?AUVL9+x9pPO4Y!RS{-
z&0KG~)B{g~3+X$7s6rfS%xGN&`h`z_^N9NABhSj7pa1Mq>h_J>A9?1}4Y#a1vVO_c
zPwbrh!kyb5+w|!pw;Y`P;NtV1VBgK1A0B$?+!t>-y!yfE%bwVK$;U5Wvi_8%AM7~1
z;Mps-ZC){S-Hs18F23O5PgYLYIP1WXy+ijN+P!}7$`59od(ysbM;=^!>fQ?$Jp1YA
zPt162!Yz{zY(DG7BddpQ{Am8J3qODHKNf7?JpK8-E5~l!wS4`OU%a?u+4h&GKg|B4
zibJ#3pY{5NcP`uZ>8yu`UH)Rlk=5(J`}+Q~7rcA$kHfEA`oRSY4?KI;&P_8;_}xoW
zR(^Wmv9lLG^69LdhtE0TH_uENC3{?6W_|0CeM?SY&(El)YkfO?z3-1+6ld#btdr|?
zGqt)y-EEbBTjEx=HCz{D`q|8A>+37-of|bJ7A4mvBJZ|0eKs^?Ra1rb(x*L?UVPR4
z=@|<jir$=(%SXjzRggDtC#I<_Wa0Z&Pep&at1}ul$yc9*MXDq5kZP&=Ox5*MjlUY>
zhh0DL^Q}Goe2TZGwOy)D*MEoEuHIpB@gfR9lTv@aF$!4wq8s|D^bo3hV_2+$Wvbzf
zp;ko$*%W*e@9#hMqL#B7gIhWp)w3NsdPSup(YMz+_PK1Si+)r;k*cJ+K}w52p*-NC
zFvTGKMFEbwz98!k>Smy&Tmmk-kQwnQWvzQ~1KCa7jdD-z@K)S$+H~xKf?oIl+TH(u
zZl*g-$~(I9s9D&JGs+q`g&dX3XFF}dCk#`XrK*?hFbG;isgIAr)5>y;ykgrI=ccE9
z_GNk6W~kI!)r&|`DV!SRpeEJO9`m<t%;aOA$dfzVk|UFz^?3ikAKyf*Us-E$QMr`~
z|G?JRR(|!p-u)O*UBgtJ@cewJlho^WuOX4~a<n0a_QUeF&H7mFOklh$RXyDsK1P)X
zszrq@%&y31i04$v0BsS7){S7<l^RHc=t)ClQ8S&T^D~6_Y8`elhCN7w#qT-4Crt~{
zn3KxMk!0dg_8Pgvk}oYrgEF{ifxz+Omb7JE%8GlAPuu8{Rb7^L7z-&*8EN(<ZqJAv
zPtE-xE3zbPnd$(qve1|M*;0>RAeu&d>!XBgc9~dgAQ64D`pL7>Yt=Cq0lg=ZYgw?Q
zq|=kUEp@Bi;SAEU^*%?dW$|G-xdSp6r@3WGR}n+L;!LII)W#>!Wt8w%8M(z^7|ujm
z2bOTpS0-BIL!woZe9hso1o&~&tpb>EnL6LGs*}ux*ZtBr!^Mz6iV}wal6a)1rxh!`
zG(;+m!WNxGCW|mRIS^6?SOhp`odnsQL<h9|XFU-_0B)|3iQmx@>S>|$^KB@K8H6no
zc=#l?Vg%F70|#a&gF;#GEHPYPXGw}CPrnK+@$ktFIGuLOb6tt57a5VT^$Zt96ACE{
zHRvhW{YVhyfd&hUu%ew{@)MT)$r7q;Iprhr9dnm=bKe1P`K-*tf#{aTYCNnIke+DS
zYVi50nY$`vZF_V*d(6Q$s&dt)Ri_OYt~%gro08ewq>+?M;9=W@UrGinF+|D)^;EHI
zrT3PEbg^nk{~jmV#66*m%1{sCPwru<*u0(7r1SSWU<5W$n$b*~(UMH$6|?byT_F-Z
zhBEii29vOuT8fH|13HKb1LBKc3olAbz<x52K@S<#ve$|vVcZeb!7)^?8kH4lfd<R1
zt6N<oc^@@4rD0`|7vA_g$bgbdjOxrVM8TXyHVKJF7{d=qmaG&J!X{}Kl$8%dJXMN~
zF>nmqJm%K;a9N_<Ms&&xSqDg<a(f1L-68do<B5QP$@suR?<y&W>bvnV=@9Bm4YO@N
zWS(u|E?;_Hr8rSivXTRY<ec3_03qP5!Nnv+njp^&vIuL@DzM53sZp@x=4z3a7%H0E
zktaGa@l$`)R&y_r8YN5sQY~nelma5aDhXFQ+a)o-S(z@7#7|4OBx0eB0TIC%{;U>v
z(8Xb|XrO`)9kdNoKC~{b4&oudacV)>TZ?poT_c8wOK&?miHhi6PJ?Sovo!4llh-L1
zEta?ijsjA4c+Ze6Matr5^FEpsLOr^IGc;I~pvja1N+3W<#_7XQ(su>d5U%QAVpt9p
zsEqM+QYv(tRFf#M-t`DYB<N+&Pcv0q+N@4c2?}?bT@wU~nrO~cuqF+>Hw$hwR|DUJ
zW&gM^kiAJbkzKWM7*kVwcT{B2R=H0+5Gr|16Lv=2Gz~ljleXMQoi>94OdMs|n<qHd
z_&LiV04Zdx#J*3^5>ca@XGk|JvAE&X0b9I?AF5$mA+pOR^?(-`0<<5{7UWc-NUTNI
z@A(kOWw-$Mn^7WCBVkC<1)bCb?M0N0&}fBlErOulVtizZN<;(U7jprnvRXojuey}j
zGz#0u0h(V8j|McgLdy+qW90_O-4wcD+9C{!SzWg<%;z^_=uf2HSmK3#NzUW7kr>6k
zMARzdk{1#cYIi)HO^e&bkLz#y`ydP#k|Av(uv=WspjtLb%VS7Qu_5qg8W7b?23{+@
zg(3kq1_p0NC0j{{AkwFRCZu>eCH-bA`I%H%71(uc%p1tM8%?`|Xl;~0m`J+3q&aQ@
zU$r%;Ks~99^k_u))OD(>S##o<;7JnjXcT>Iz!-Hd$FvDQ{z(R2p`TNycN({iI=W9w
z6mKq3+a+dxg!1bs=|0@~n5vobr*jF(|0K!=SvJg>F6bhXE|CO9{z`eXud~HDFj$z@
z^X6<>qfq&#gmfwF3PaJ$@jPRZSDD9Rb}b$l2w#c`IgzD&ff9k*72|Ki*9NH@EvkX^
z{AmG2<394OjXI_RMswJ@j{G1tAY0K4t!Y50&Ts-+ahb2$>htVEPOIjgP&E2wrV-0s
zA9zKg0i;ydQ>;?`cVUB0rK}3HNo)1cmcW;Zo8Ua9n-$R1qS{NtOFESnZOj&tfVx%^
zu-~m6YqKxAz3Erd85gO_CZmVJ9k7U0*;%3(9hJAUKc^w>+8RyUUuKo>YnD%N&a<bo
zLP=J(u_MP2_f5CTFY;#wb&YKZ6^8jbk=W!^hMns{jfytluWs@@4oDqQswpzoS2k+G
zisV){(Nr0>$%K*_+IbC<sEAsp2b3gSizsz+Bw75B6pMCaJfZNgk@o7|Z-cQcTg_sg
z_oW5~>{;_!l`oxBQQ)zQ+?>Ihdrql2m*`r_p1)tHOed?>C4(h%4CmtUiZ!RcPK*#q
zNzr_iYKXit@;3^HvAMdnl%bNwj+RJiug!L74}nb7Q#Gaha4;g3&lpAutqMs<BXD~Q
z4*!+2_KIjO^Bq#GD0q~Y*xcgdr!=`x$Y)QQ3+EPDLX7;2gC|2^ze^!|0osWmAP<S8
zxd1rFP#>dVVBDe$8>1`vlm~5PK@t^MBz3aDL_<Rj1Vr>$!YpZvThhR=Vkj4`!L^Ii
z6mHt-;AtmAliTs=yZY-!4SB7Mg;LnWATAL;mO1X)+!;Fs5?W9RG;#wHCiZJuC@u#`
zD9%8cUaC&`P@eGT8Fj~;38N)GYU+A)g}Qsl=hj77K?Kt8hywwII^b8!#I3xmD3DGD
zcF;*UDuLJB;(a6H0^C`$;uzvJQ1^1Q9M+KI#0_Fm=wOUQ&kGeNB~EG*;f=ieTA~2H
zWon3Vdo))>$cb^RCwD+gdQQNCbr_t)jiZgTMnh*}LPv^|euSo51|pic02XZ)n_F7*
zMs_MnwV~UD5cArQL}Wlg0?q_D31X9;%kd@~zj6pM-9M?3z5uTRB4l}+c<6ydU0Aqw
z9a<}57=pNLTR`JU0kinYMwS6Mhl>CYBGL7^u14@W4(z0zK%`EecA$}8)DDz(CLKw4
zsdSs6ZmZsYftaM*700CrD`lxfBB_9p^ngNXFuj_U`dK3gBTXQ!h{3HT7S&ty*RfQ-
zn1^wSg^vYYLI^>iOYytH0v15$E-@VafLO{4ipatMnnF?3F_D~pt7-47cu~vUyWG9V
z-LYulsZ;~qk$5S?G2~sCuA>KwLA%O@+czyv20=@c=73GF%oGww{^dJ9c~7u)TnaSJ
z*hJ`kmDI5`C~Anu`Vp%zi3HMkaqrYt8Rx<ypcS>lh;a0dSisSWSF#2>a#0b;HK1UI
z?u@cxFhIsQ0<Fm8qC2njp=pQL+~MZ1m{YuN&(D#Y#XK<-wipyV1!Vldehx@h(z7lD
z9mY_sNl?PMd<ilxz!t0^l{e51Rk&emXF%{mOE^5O1PT{%S|t+t3Fl{>r;vD($zbu|
z6)IPJnR&-Fl9v1!UjZC}xX*M5iY62Ng)knLL*_Iy=KvG9xxg}04G*N~CJMS`F@eY+
z1&4pa<B1os0VS%A4nVMlz_@(b*l*-fC;I&xRB9750!w1ZjaRCBOyyE@P9t|$`wLaA
z&7p;ubifs26tJhg6~6{JuLOxj3h;QRi?v88+l?~t(6P0t`>Iv&5+e_LEgsUQ)@z1N
z&d*@WA?4QH6m;tbQK67^^LHbB7lB5~!O_NwGy@7d^Hw@;aEap?m-bPKom_@^J!ok)
ztAIowQNgkFqYQ>~;QXxdj9(+5l08U_SX`>YB__-msR!hBtV5lPD>vCf3eI=ynW;jq
zLjs|}!7U>H;wUzz4%>N}xE*#v#%Q?<Gis8{l@Uh|w0C;Zh`G*_QrO+fK&rb-m|rPr
zwTA6EP%Z+jLuDC!VJlFyxU`QpUT^;1W^&QhUrK)*Dt3t#WdXJD<!w^BaHA}5nuRK_
zIy=EzY7s!gFOe*N49uNvtc=|Vf~gGYMLY182ZTl*T5h5~VX;*tm;ny6!qycEFCd&@
zp6}v`$7+6v(s6R>60L;R-AIrCl}BFe*uBUQI7WKbc55vOi9l)9=>($RDnOgCjKyH^
zq`T3aMF_dUK0bkUalbC>LJbt1LS;B^;M%OXj)Ei`tHU6;P8Dm0ZsMmEX2edzVe?8i
z$#*vD9Bg%~s+Y)&;N0E-swh}d4-3W-CAdYR2VDU*H3l|f5UQ>CaGc2Fv9WHsw`+&2
z=L~ERQ4?g8RR*SMcz1)OAqkMMqlr_cuDJ{}62dFGbx%*b$Cqz8@ifQAwUYU83kvPJ
zq$0oZDD1Ulykm){(7tJ03{be!g=32d8)$~OLT}>q3G`xNiJKJm$m<S*i83t|P_2k(
zq`4H{2oqF56gC=sGzLmyxUho8@QcA}NxR!upu=mwK&e&}dqf_AKz|VhF;u(5cHdy8
z71JsBb&RvPjHDh$4r3W|)Ddpegkxc1#1;|%zd^nDn5e$$HnA)g3~ad-de;V$3Ltsy
z0JO5Per{!S0qr`&obzZQA+i<=AplDR#E#V1SOSeZ=`hAg<OzagGx8|(MRB5nz-8j6
z%R4^E#=iLB*f=NV5}=`SiAvVds~5nE`SMCQA&>x55e0AxIYDCcKv1BG2O$Q!SR<!3
zVK$B_?Nre15uB?85Q`g#BjLbY!a6RR5+d3~buu=i)$dNs;y4-w*2YoBTpJ5+c~}(W
zUtC-oAzNvU;+U@KhK;nwT=aebt$?hv75)yi<YoC(ml@zJKI(Z4<|uzBfD=zxS0b^{
zXh(11sN{V`p8Q*<pGHZ-9iegd7mq-hj166&SMDAxfH8uR29tl!>f$c(w-*dW$1PrC
zd9w4UuECKBN_rnLBp+)$%3R?Mtt)0D1hELQv{nm0$BHQO4^OH+L*^23$L|4J0!S#!
z)S>5S@Ols`YvkQmCG!o1O$BHSu*J15u49fmBe*ybadktNNFqZm9u9b#f)JjBXj||p
z)N=_*INuYcrEvTr=C9N%{7SKSK_X}@0Rsd`MefJn<czux9A^+;fbMoSb~_3~u%bc}
zFH31%L6p>viqAKJxSx*Gb8+2BBy1Bs+Fd0Lv?ZXM?x;*|OzR4{1Ov`G>Q!l5l7+ef
zwy8V7(J&&`aCYiKuN^YJu?5J8Jw^z&ff6nS857C$mw@}0s_2VjhL)#*=7PxebOtw|
z<tCPM4p>UPgSDXIvM+vQm?Q`RKdw3|8+$!LX>J(Lfn=ACZRAQ4<4GyIjRbbLU@9$?
z-PU$*oQUtl;Nkjyr!^kU1+@Hy8|%A`c#c8<iy)GG?gkONgUiM-5uG!W^Y{c4TS)|V
zojMQAf<Y&3gWrM|Avi}s@GwRKI)8%?v^)cAMJg%&U;r$`=M2YBe1eKp8-5ej$>2i%
z8>FQtk_#1;%T#B~KgKv~t1KS=1I*4tM&Me^QRW=*BvF!V6PXAJt!gM1ic-Q`7`@~q
zoQMsI{AUW*3KyW=-Mfd6;wdsNB&W1U<mQpUwn}^bC9q#|BXQ_yLHJmzSXrjwXq}Cd
z1+0m5GonhrC9(;)BqZG8@uhPcW}FqJpNZ=f5dy-s+`BnRK2H7wzwpsi8P<6vl!w;}
zj&)=)V^Bqspo2Q@khn(C;x?L_12?8V%HD!AH1+=%(2<Aw->`*L+yem}3p`?bgy6EG
zl@%8Yi5l=Dz)@&C>Vh-N6O1+vW4YHs8*{f(3bHa(HsGBK+{k{nn*uRC>+sG@O6oT$
zO2Q&W5M$$5F+Zi-$pGgjRG>?Ux&`Ciq+X8Hg$p;DC)Y#8+Bj;Ju{;ZgkP2?_y5GDa
zUB68{jGp4O$o(&amJD}^I=p=8v}$70QRyti)-_R~9f4cRo}VZTh6bKxO^LH3=pfk^
zNcqU7L$BR{C}-toG>rLoCRCX3N0-tdKg?Q1FBLN<9m~W4)+(>y5F96$-%9Ds$xJa~
zFbwXpNhaZmj47l`Y<Kyoda7$-Vu=4=7$aB9R9%km?6|K}ZlzeFE%a&cy~M9b+>0tr
zFrp+hWu=eSkLJiOlPYc)T*}e|tr`<y2XB7F^lMszlB~~On%g3N$lD8gZp~I+G}$0a
z183E14j>QO*h`Vr^}aDm_b=P3<P^Aook)|^T8*aEj<T{a>_j$S`*XWk*Vq;MHq5HB
zy2vvq<T{J3QrUC-6)DYoM|fSpx|(rlNIo}arCuX2-@n>>Dh}Wx2{b6??Q|>rrqT%8
zeBF#SnnaFc(-A8h*XC(IhQS0YxxOz_#%NBNa7D@wY%MRGBB*|{lNE(2BgUmIi}N!4
zJuddygo&^^Lt)@^hbE1nq{v=G>tR%*s#1#(JZ^|GDU%qiUbmjwV6y>YrmR=RM;$Dv
zG-=Rj$aw`rl3KMFmp00%TMedNq`347&@2iXrMc>&$jTlkoh|O7=r>rgNOBk_9Yrnp
z18P`Td$NQqPeoqR54Y;X`aoxBTqDykI%rV?Jmm3>UW77~AyXXGG<cEKLD7I>l(0d^
zL-Kt?R|K|aCMdqP*ew)JWa{d}2I_S$KASv>uzsxx8<D#;Y9X6g0Ff$bFlmp$g0HPq
znT#Jc>6R=5C~YX_LsLPMCuPdRBZI1HUwtpni3{LL(ZQ53k-@pdMO7-Ciu7nMKdv^f
zEa+6F18Cpnt1`_-SnQW>VG1@lp3EAdrHKe_B`35Y#G6vV!d%cw=O%C+*`k!?qBf_D
zv1!k=hRm0wY-B3S2Vl-;s*jO9Ayelo^>*N8fB9Utc;HLb#aGV!VfmcNrM+A4zQ6j9
zo9-_jKi`X*8^gX^?)Yo^ch}yZ9=7Y)s@yLU75<h7hTppN0sYdMQ>$_dzkcpHzib;)
zvgOyk#$PvS_MN+?Rz-hUmu=X3-KbvQobSERb79e<KeT4P`iJ(KAAYnju{piayK>TR
zQVZ|;FZIKhhliUUU06DM(reM>U;kzA9uulh8uaM#HRJhxq19*3N^alyU&9AJT|9ik
zrBkBgF8zA>Z|=PIgxQa_)ZBGxqH^e^->;lK@Yd>ggIlZb8CG{(|Anvh>pgwVkey|>
z20yH>PuxDNuIJ42T7$1PttmF|9bYc`KDd)}0WWNgHhuPJpH&|{aPq2yT<;y<XVdJv
zQhRs)<m|og{^X)f|9mt!eB`v;;SY`<{mWlGs2|_?e029C<J-r-zIzOpCQKjx`O725
zy|!o4u-BgW>J5*Ke`wQZ2admR*YmX(?s}~D;Li_@*m>xG!ksHW7`JWZuF;!6+jIQt
zUCU29vi^x-2OfKH^!7uKl+8YL!|+ur?>%kx$|uIGetmJ`+plk1xcSf>V>TZeR7Kc`
zJ@f7vv-7?GIQ5SQ2TfS~`m8f%UwVhP`oiOeuU=J=I5MyAxYt)4pE!0<(a1p)jvYVy
z(*DQoT>W2FZ!G@lz@2k{I&jB|2NUM-Nxta&*MBJW$JMVU4*xToU;W9Ck6HE6gMC*V
zKE8a@yZ7qD`!<d`eB>t;hd;}X+`o5E{*P;)jdl<JO8)T+*Vo?t!Q<IY*FF<%di|;B
z@R7^Z{x|N|qhGtHWc*KePQLwwp~0rl|5kkAu7^_>?s_hD_~-ZPBZq#R+Hu-&we!%!
z!AqYlsb2nrC2HT8Z$}3<{-tc^r$4To@#zl}mo0yy|LVm*9=z%=OUAAI^Y+9~4h<Ud
zKL-cZeB;m!J&#=aR`lzG*Hr!by&qOD*|ojqcXRuPD^^t$FPq*sy=&g~;x|@Y;~h8Q
z=at9KE=v7;-W{o(tLuC0TzvX9@2>i3j~!QjkGAQCQL^u4{9Jz5Xmx$>UhQS0df704
zVeOjo^HXb%dGe;tiYM>5Ke}@2n(US5uL%xLJ5C>*_JjOG!&~&D)iz&p_48%^)el#W
zeXUrHom{17JaY3_&iO}My3emCmX-giZ|cOKjY^+*#zVCOe$_d0z^@LTJYmQECr<e7
zuCd_<mk&7h;p*J7o9CA;8?ave^Uu`-4*q>u<*Z+=&!7M2gEeP9)>QMgM}MwQ|HHBQ
zX}`a|=8XaEiJb#V$K5ltB=^HbHx2L}T{krOXv-;m2HcbHTYFPYj|Y19>~Y_*>eln^
zfHf<=*Yk~DJqG@|*Pwx-+gEleb?3y>qq`^8m-Vt`!TIC-?1cl?(8sPxKlPuT`75uy
z9{p|@(aQ$W!D-d`wb|lm?QlElsTVtS$)e}A=r#7kMD*Frbky{ZH&ywo<zD$Oi$edo
zhnt7}tTr{E;iYK6tDVW|k8~v`?D(Xl=fiVVuMeKA7<NWy?XsI|QvbZSMt}BLHap?B
z*?woYoszz=`kdZVANBeytNd?O_nu$;v*W_*pQe5|pnmJcx$m7{KCa@?WE9+gOzQL<
z$A%@TA9?D5-o^fXewm$7RCeq6*9N~TIi~oHl6#_KDsLQc(zlhmyW#Zc&Z(`*yU)Mg
zd;I*$9_>3=JjxjzA8Dno`JO*5eXXj?{LEXr;mn?kZu;q?I{8X4enz|M`@0P#O|Lfg
z8vJ^Ae~(vGXVuSJI~NUXU(>gb*Lg~j?HqDV*z4r+RYCFiF&na(^p9)R84nhZ{KenW
zRTs@q_p7N+pERkV;=H+U5C1%z>V0}+ke*w0U$UyKxGtIdeqvhlTgOgnzUDM@-K(Qa
zqOCUB_`TZx4O8k)Y2KPYu5s6i=b9&m)^!CHb*IcooL)Jj`j|<!=J<=-N4H-6+cBA|
z&mJ>!v>Fu+@%s)O!pDmlYfrwRIP4J&zkbByXRCA9zDEZ_krn;y5Bz5Ii_kCJa7NE5
zHx=FAoV+d=(!@5eH(N`l{VXi$^J?S$;p^)Den0g)^P%d;G;5xIyi>ER<Cv2MB!l6#
zrv&3_9t;M0*Bn#baIzY7>8L1?p6`vVGsQFYma@;fn$$;?Q<JNr2Ru4bmDIM^w0YN+
z&T77?%v{TPD?LkUy{Tu^(lyqdGG}c#pz+e7lg#j5)3&yaI(=lScU_dq7T2lV@fS0|
zSaEhDv*Lo{k;BZG@{#_rr+>)4EED$PGv$!BQHDW3ht*WFWJRgQ^SihcrHC!6bnBd%
zCBF7cLFO1QjP+UgpzO_qi>*4IabF5*1_ZLy$QBpLw-I$S=Qyy~uO&)z_;WOX)mM?%
zlnd02>B#VTt}Kd@-ff0eikjCGFBw*ij)E><>394v(U$S-ZPR)L^{jRX;B6~-|Di87
zBvYmt$7EUPGD?M$aQ|W)@2#~-y#-uJPtM|nzKtPA*KsP<HiSVb!|6877nb3&r)LN;
zcqh~J*yHF?8&#mTT8{w<F}NfR>4%$fg0tu<Q{L!oz_ROwg?{K31Ps)t(t$@H(>y5?
zel1T;|Bl~k+yt>Ak&a)X74tyg_)P55*eW9)oUPE1y6T{%xS3)TG$^Q$p~J=ua9h5Q
zG!AAM!cqZKOXBEf^3al|V)cAj4UMc>BK<({8b35qub=asf&oVc1^Acc-v%w+=^4R$
z9bmNJN#0XwjWhxg|5l`w{XIdYQI_{>-v<6e>_9ez5)#iqN38IO63Q}qVzeevc&lh4
z6uFWX85PrbLDbPCLCC{UjL}xu+$B61;xxb~)VvRKHAXV_w^^iPbmi${Pe!Prwi*Fz
zDO3RCFf|o##7hUvc`eiE#K(Tk*}}Ym@Kaj96S{V}$toSOeK)v0KX~#agFSI+d2jy$
ziU~kSWrd~~2PKtMNH4@8qxEjEpp?c(y4+nNS{!`&5XB@)AzYA##H=`+;amVo2~D%$
z#8CkB^N`rY3Cg^V1Qp)rJfmgg8Nt0U*N^%ve<9qu_+4b9HN2~sXokpE0@_0u*+CO0
z9S~RbRR%p<(b485;7jR4jN!;7hYhxn|G0AE6Nu#$nus|)tG2{;6!!9_6Q>~#E}?2+
zSZsO9CBQ3941^naK;!vZ4G5YY+I+zS^GjukL1d5%n9Dd2)kF_RJZZy@$<I9fyNA`x
z6W#CpOy2*_ch<c$`{8GHY`EpJS?d>1J@C%5r*>?6?3tBM-141S>!<HOGGpvBcmDFw
zkhj?LvuFMEoqK*a_MRP+H)hZM;LxT2cy{`cJ&RAceaGbW)o(rg&Sn4DxP0dm(_h@T
z<FfT9{o&ym3qSlnbiE5;WJQ(#f9}mqPj^oy+=R>!5U|qpj6IoQ2;&GN&q_~#FbIU<
zA%aMQu!|rt%OVO0Qwaehi*9%+>of3&6+{sg23KH+EV``gV|)QCD7cE^svxeQ@)&-f
zZ{5y-zu$jP(sip&ojT{#sj5?TA9e4Ke*EZdN8WPZPfovU|Ns2_QD^?<+O=2T`}eoJ
z^7!DL`+xg)$85Oo+O?nh<MFrLcl6-38xDW+yc5`OboFD8?t0(L%NCw}_-ED~f7=hw
z`uJmOFWUd;`xd_PjM8tt;Ht;gF23l5TTeLq?7P-IdfQv~y85xTH|=rstv@{bjJuBK
zJ3oWiF4G>E)2G<;^O^IOO<i|s^}(*mG~FH($ec$oEGw5;a{(vU7g~AAJ=VMGgTW@J
zc=&6?b#%3GKws<3H_so>(+6!~<q8|>oy~?mI)2&iooQG&?<eKTTb?reioeuCm>787
zyUXcLzqRU{DwlSTS3X$Y?n7nU`HCdj>w`R_x8QQyu0AhaxGJgSS6aE3yejvgs>_{y
z8c+FYJ*L)GNjkFm$#$F5j_qlo`^$?u7j*faZQj17r~h-Dj-_emWM95;S8t1scO894
zq?}>(?qJ<nukCe8(aNgtNB<sDx_<<9CBVn<{|=yOleKfEMb|D8BVlU?#KjcAX(W-k
z)NA@zJAdmTUKtJ~w=!&dmq<}>^LW+CfaY>AJv8ROMrZX_kYx+)oc4hW_SzQ`lrQLY
z3K>y5#<0*a^QoIjuA4&Pq$|NkIX~S`BI6u7D>ycSGQo7l*N@l)T)4KvDAT;qAeE$*
zau(!onSyvCoadkeZLX&^t-Mb1gEY@Iuw1pgIUUZxdG3(mNIPH@cj_I0Gpxxfl!q{%
zg(iX+9AGZqo`elG=y1%_;{*8WSr$yG=i;C9w5j}PQcYZ+TY@v|5ovs8ETslEi%@*l
zFcQRn4E=BBA*1oa18~bkO)+7P?8I@_@5vYm(QQ&vevwIo$(bvD37MmO6*s-cyP|le
ziJVu$Sn6lW<%OJAt0N>l@5qy?LzHFePSSXV!?QIb?Myk37n*kkN9JkQSRkpZENW(-
zs_pJQ4_#1piph?J25Nxha#u7T)V7*Ec2EdE=4ECH)m<~LD2eyfEb1vA3Qxd=gUC<_
zr=Wn$C8g+RS$;T=cxpTB$)l*AXbQfdPHh?i$jO|G%nn45q^c?u)E*C}PV<Sg2-DO^
z@e#69x(n2?#{`bS6-;G0^}Lz5`f@uqSCUzP$nU2%VykX3+K{A9&06^kPYc7M0MF71
zVwW&8r0m;ec>yF*Srq|K868k=R(bT`gk&4Y^o}@VCcREmbufwKdFR#8NsW}NL=hTX
zdFJ7k$V>&yG5au^rT9tOMl|cvs&`*!LQU#eRjN!*6th@DU3o5EZCedC9FRkwq0|ss
z=1CyA^$C&|n@`zE6Y?%8;KCGqD4qxIXDFIbi~*)9#re)n+bDbkv>?j4=mpA-ox<xg
z0%;a92`qQWBK(uTRO3Xo5;$lvfR71{pmez06*Mjx-@bTPD_u(Yj=seL4w0T8Op~OO
zZf$mq%^nM114Bx${!?7g8$)Z7rbDugzDNhSG(6WKQ|;uFBo&W8X*I!L9Qfe*r{y<$
zLbTVL7c;L_eBv~w6Z}2Wt{7=(X$3k$%1X994$`y(O*mWP)jJ?rBn0bFTT4gD(ke*@
zDuk0`)KNc~seq7cPsq(z&80h_(?w;*ZRVt0;+ny-Pgvq1p$k|)-`NfvqN%lKgAC`$
zXfW0|XdFzavVg{|)hs&{Rb-v0kWG=3;!mbbk0<38Ogz|p7E6pU@eL6xtfhwWknqHg
zn?@~d*Bm2HD@XW6o8cfR4WVOkO#^zTm<Lx%q2TF!OB#>_Mmxh`s>6cEw){L?2oM#z
z)^mU`8qs>;$Fj-`6?=NXc)|P>_?DyD*}XJM9*%f2Wt&`G?-gQip#>?XVMjSKRa^nO
zNDi4UpdnSJ`w3sFYvI_WJ=JH;2Xv>pl&nHx(wM2L(1c;125Jp{mFxzT&8d#;<B8NP
zZ=Iw#PSrwbcL+w~o}Yib7<c3XX-b?X4{TN>`6jNgoVjAp@@C~Yk{Si*fE}3#g7oz^
zrq3~e^`KWOkKZ`mD|93?L@B{j4&7+qiB!|jiu*j^h=zGq4<H#+Aq!SH!b@pMFm7hV
zv&0f{huvJDEb*}=;EzI;aquHpNlIIY^`;BM9mw$~0eYu|%JGf58ieF#3StNJPS(Lo
zL>f2L6k!BmdasASQUo2t9hjA-rg)Hn<8xV&9URo-;5h)k4H^$J3BdU#;3!P9w_IR;
z#sxSZeRy_~Bh%z21YJ8$2YM<oF0M1V=$=2tA|K1H<HXdDM?#xCm?;XMFou+7$`Tc*
znT5?#X9f-VChPCbe)2<b`TUBrU{ei^hrpP0M$;wWDy93WReZ-ceT$1JhU+xPAl5%z
z(vvl%g}l!Bk9)#wVxfZs^Uhc@bqU*zor*-#A)n7DXVR+uQxZ=@!GMlTDU*#|mfB{j
z1P<53nkeznY@sp1cG8ASZY_Rky|0`ND^+IABSyh71`-v--Lpba9u^L#;p)bf&;7Ep
z{nNDGae!MMHR&jF8pzk-!`OvSN>|OR@lER<PLA$AHUr7c6S{{@BP=C=Ti#*Wfka#s
zWSR+d_gNf~??#DGDL_ar(wrJav3ew3(nXvsYy7*pA<#|7mTx#|RtW*>-7y4XsC)nk
z=b0svtVeHhXVmw7g)ZdTlU5!U-<qZ~PsV6Eu{@<tZk9UtwxAs#-)xUycJhCsf0G+e
zYuRM!@Xx5+m_bPq3^3ac1l|W27TUU8%L*P?t&W6Bhm};d8S~-#ly}#m=n!6g#F}#8
zb_zn9NT2NKYj%W`hQU&St25w|%)9SV&w!unpW<c6v*ud;*0^2Ygeqo~;Ks9jJoI`l
z!=x;xDR1Skxp>lDCt9bQag~6_m}!O0#Yn-7IOs8x_>P%QqdkJrqn1~wQ8HpDe-WA4
zTFY3{drw}kl@4@#t*wbFc>Y#icib?l)NZG|JHWTpR6WC)L1QiaBfXmUDzNE>y3z!?
z(o{JjvFk&Zjn+R{K1z9KWMqxmAeKUB=O;7!XC45!l70B)Bx#HcK{IN+J5DY-TkU!p
zS@{Mn#}c=YEL%jB>L&2^T2{@I#RE9*pta0?_eoNtN=X9&gBwx>bo`_pE7Gd2ldf@y
zm<vQ`d0!NqD;29pNwjUV93u`yvRRXB0yK3+D4z2V#KnzPC6tn+H9}#lOOIJn@SO#r
z^W)jb1f1G8fI!{U6AFC$r}%3i3@edQ`!tLbW3&_MBdVz6iSjGhM*D!kxnapbg#IxH
zP7&{EV{^z?DM0z?7@uLz(}{>9aPWwerNmJi$j}(9bF7?5O9eqziFFOpIknY@8B#M&
z4<70~z>XqnyLYzviYhSkW#5vxIP=hp(XN0#+g1_Ja!Rs52Mz<OkRw74!Xu7IQ<AfQ
zjv=CWLxXZbj+m6ck#-=<td6}s#|WW)<S^M|Es_%M9*otcS!YQJ)WBBt1dc2{doJMx
zaN0v8c$TJF#E=Q*SP~o@8jD=ulj4{U=t!ak&2UWQnTMRvw^s@cZ_Zq5t&aAyxVg8Y
zSesd71rNC=^5UgvDqQ!Lwrz=sOses{`W^^_n$a<O`(n|e0)@t_@N=-8Md3iEem=!~
z4to-Z5k}{V_ApE2ZY8~th3$20Q>kqgm4>{GE5xi>60kG)Sr@7f7|wvi1S7T%j-xr%
zUBjGlPPf&$Oy)S#fEQx%#hH1D0iE1PCdKvBfeL0g)wpXodH~ZtY(Rw_`2((4(g;U7
z!lZQbQCFT~5M+U_+N30=kb(qohefQ5!m?h{1)=bT0C3DFTtbE{f~(`|$yT{GL{8!%
z;F1z$Sy=`u>SEQ^;K<9kMoQOoNQt~jNMcKYfVrYmY<1%Un1l`6vzV^Q&M*v>AQU(@
z)@!a4NEIf~IVMU`K%E6TIJI4a(q4N(D%%lLp;$0L6QQR_PkCt&aW%@1%t?esvswnd
zC%(1zfjKZJ4W#A?QBhZh+nNS2fKxK?<1P>2Mdnab73VzB&(bhHrj*UqfTFmMhVhW5
z@Ss!#Xtx4RCT0e342iMA!E9X}f-G1BR}{%$)Q(Y-?nAjGB4P$7CF)YXO%rP~r<S+c
z){++5<9yh>Yj+hg%Q<)s1)b=FxH~k9M2uoI;t6^T1ULmzyk}}3vW_-ANYsKd51iyH
zrnXLX9Enl2<1g<~w6Kt>ku*g%DWWXQh&&LDK(7+VP&n_1Y6n?>aexn6LP3I_#9(xB
zz7~->9>9Z)8euLb;#p&i5qL$MN~v4(keVJ(u{5<htbEKB1rRGR$Ag{f9-*PlvY>d?
zbdtKZB&_$WcYM^MZ3>UyK)-0(AQIT<B-6JA7z^(aC$w)NLN=QdPEjSuDH_Qu9%&IG
z7D~fjSLWn%i?q~?97dyzh$J7Y5XD;MPTD=v2r1Lqh;&`8z}$ffxdEskUi_PrL)z;<
zl3BdM)0R|^k~>#G@%n3Nw%7{Lwjp|aN@`Vz0SoVjCM-?leu%IsffH+Anu;YHbm&>}
zllUJ?7RHM~6!p|~BsP1Sg>{1Cx`2(6qoSNdB8A=+Q;`{gRz7--wTA#U<@Fvpj>QPF
z+ttB_(#J|xg*ea`0H=X10v9M2ECrWRszn@-aN&>{?W*3$>NN+YH&X``F0aPwB1t@Y
zK^FBa*)SD2STATncfo{K6DXf_HN}e4{=~<%w(x*MYKRId<&7GOZg+BsM^LLc)bWI<
zBp!P8)vEyeG4jZjdH7VR_|;-fXD!8oDy4#gvfA>R_Y})RW`~h!8p##Y4XThSB`{Wm
zR7s#l@pfZ7>xn3Y#G|rf)WuF&BwNLSu#lUy)4p9N9q0^X(k8?sT9F8}O)NklGmS)K
zW2=>hm5wF6a9XgXT=2AnG3r6k8v{ot(QZxy;t?nTspDrpB0_QOGz&uN*Us{BMHms3
zaxufu$H!RS3<ai0yCOja9cM&de5QnodMZ*}?nS5EJCa3hQcqOfD?~9dPijY~VRsbb
zgax7I3#2QS{S(k9aZk^H=!cc5v7xJsb1>oOVnGoNQhcY2oFsn2qg{DOd8p$8`K>N;
z<w1df`yJq@?ToTwHqC+i7f6mUN$6r?tHxlM2vt0Ah=A%U9_B2;Iz#CQ?MQL(((8(L
zPCS(9<S`F(24N5eJClj0<Vd1iMG9zN*g>m8emMzFG^z6tID2)>Y*knpZSVziQlX9E
zkd|wNu0W_%sHNiB3@cH$V8c8b%gBKU*a#Xm;`(g|_hB%sE+MqJGTlJppehXFW337l
z54AoOWARjmm_Uo5$WG(d8kF@gQ{f3682NCTjnQ$!_*|^cTsbQYUK*uYAXIEPUXwE)
ztqM=*UCc;?3O1fVgrh7V{~X7nN;sv^juv@-AP|Y<uux<G?hHe)K87)(6{wVle~1XC
zs8j{yN!viIEz#-pEvUW#M*wFD4sZd+iWPXFUISdPB~_daTRHSP=$PlqjzymMDD4tL
zlp!5OkP5g6CQ0YXpsKKsJw2fXrL>Sv0T2{K4BxIKnwCq&$`<3dYpr~3lykFz7(`z4
zl2`qKnx!E|VsP7Lv!DGPQO6GpB(;cc2cGw@q)`}?jRZu92>RNDV}7E{Yrz@H4;Gkq
zH|%t(Z45LQia@-)_$3ZR<VT_n$}e<vTV=A06k5Wx{`2h_K$Ns8^%HoQ#ln#=;v8t^
z-6oGgBh;~shNTm>pcKP-QGUX-rWE{?PCfh}8jie}*8tKA`)q(iXzS*MD}dsT;`Fsb
zpTH^F2))r}$S21jNZMRT&BZv`?bEeTAhb(LNm-9B3abP>3D|0y0_qAvD9&0Hw^Z$T
z>l$L}dwjH`uzetr@QWI0iK2Bx7Xxe#icA@$4bIJ>+6BF#x}-A?I|Pkt3efndSaXC0
zU0ejW3v=*H5s*btDX&XuF;&=vvZ;;mYs{U7MJjbk{4p|>M2u7DB`IwOB)n#zh-rJ=
zY|v(l0!2M1sYi$fp<2fK=%ljBD<Cgn#`8)50nRw5cDxmj5Qb<gH#gT8N>JsZDPZGy
z(t?6q@Qy{c22)bOp>1RkYd2RL4}IH7awINOLJ3;|2Pc+)1(A_3p+Msw1ZwAh;=2og
zO6#YwRTNfg4zdtckM*O?1BT-XktoUgIU=fn#u#&Mu{)QsRX6X1qW?QYlw<iQi$R5C
zElUF83sb~pKA5)7Wv5DcsUbOSQ<L5baqTOmJ+(_ay(Sf3<O)lFXhTfF;z7(0O6x2-
zu~V)mbh>iVztG3D6~q!p7OWMvacxEAz*DfOHz!YQUIQ+c<#bbSDwWsb$}|jJQ$#W<
zvsyF+QSYbZSPDqXx>CgT>~X_18gGJv6hn`)l#x*F>3RH;wqmg`Yh|vl7jh}eMmx%N
zS_#~Q^|;oyx;)G~o%AL`%?jFePCD($LTL)k;#=GGy4bR-b!y?wE*f4w;Ape7l=O9R
z+no!Wv>RJ<rm%HhMJX5^K>w+B_H*$*Zq0L}CA&GH=Z>X)t&vn3dYjkjd5*$6&M7=q
ze?nK&%kw<Gm=Tmnl&2dxpH}cmdpLE6ylF#Yz0|?4Y`6nU4jN|VE<Vn(i(|_OWe2?f
z04GiPVtdMJX0sKa@gNfxD9<)69hQ|R%ibBUk1+H|7jhFqYlxK%-Z+}tfP)sIuunM~
zr96<7tG<auH`N{IX_-AA+hNo_ka|4In8S3k9344t-EY}S&x4=iLr(aCj1OLOsbe7B
zC7odBl#NrVw^S2%wW}~@>26svIliL5*=yB7-hXSMj1g+>6>05HKgDD8jG*cz=z=j$
zR?Zr=`<UALDBb!C-kk64;RO*4Cmu+U1ENMQ&3iJQzZp`O`i0iPl&xFEr99PHr^!Zp
zxtqz(oO-2G6%D7Q<yFJk_9=P&<<Y*Axe}P1vXBQvty4A5Gj6oi^Ujv9@Gj3@p4xF8
zzVq!E#(1P=y4v(fwl2{wSinuEG-Br%Zx_MGXA>>~>1h|4w#2)8xrxO0cKj+R($W&1
z-8Da&F80>9yzKAiLLhHH9D0J0+~i(;HsIjMUq@fU0y_6K8|^5!+$5fHn)Cwl)}qEt
zmCI7>1JB>k{2JnH{LS>JeAZ8`Ks2|YX16)2Bz#}lH8q5iK>|kuSJV4T4Np$;CV1nQ
zc>INht*@<<BS?47?K<A)lxo0DR(b}vO@|t)<qa;$0?W>%o73PlaiP&aG?Dry<71X*
zS($wEWYr*+g;r16q7)rGuAM;iOoUpi`eO?l=U22R<bciGGkfZF`8R*rwP2r($%1p=
z^6{R=>GP{AANtUOpKkong1yc>WI^NX!>i5v?^^JOhj?!Oti#i<oOST)?*HYdmp^~Q
zrd@A8>(HIQbmpP+$KL&sU6*|01NBYI58r0LQ~!3sIp4i%)lrXJQeU$8jQRVVa(HF^
z`48=P>LXX}wdog!Rz7t{XXCv0J-o9&|Hq}*|8cj<qURSk&K-Sxhmo~EPScH@%TIj%
z(&hWKj_7WUKF*%dZ24QieouYhQ!8oXq(jn^Hs840!{6Unz3*=isWwhIr0T;*+(Cc%
zXtr_Jf2*#3*P3ec4;!=L7bdd92Huqp{`#cS*bCQ|p1<d9owN5GpQ*kla>e1R-}!XD
z>FH1Ry#Ix(^3%3V*nV4HH-En^ukZfj<A=QE5Bx5;^`iL~Jo9Avg&!YO-tw`7s%Kq(
z{M}nVe8|1$J^h89*L~-{ZJr-~egE^PKEBsI-}&1GpL_am->~0z-n;F7PyhY4=e_*%
z-OhXYnR(k^wB72R_T6s#``&*<^{emOZm%tmJ-qXlmp;AUJASwKZpZ)b!rC5Nw)F0?
zY181M#~xmO%wrGRc@KT>-TLkK(uwu`UV6N~;b-?YHau}><DzHxT=xEF_n)`nPj^)|
zeCErQiyr8y?fXDa`rLQ-v|l{4XSU+*yGr}teP`+TyO*VhJ^BSZ>*s%5wBhG>F8bv?
zhjh+vIwVnjm;9aCpAUO|&z29rK7ad`iJtdwx!U%7sk%+~rgZ+6$I}Hbyi#3o!S7C;
zf5ELA=D+aOL(`YG9G-5uV$E*v_~yE0=Y8|8?mztY3p+o5>RTJnAG)3U+<$j3zU?~)
zE$;uq?#X`7yf-=U<y#l;@$%0X@3il=Z{GKWkM4WlOIPppse8Ux-SWAIS8RFdp%sUH
z`@+scKDm469-B5+_t^5M-gTe&X!)2;52qVGGQIrb=fAg{`Yylt6DQU;+<33s|H*xA
zr)U4aZ7zED*5u_6{7?0jU;U}N?*muXE_&dj?z!)7XaD@&g|^?VSC{txk8MlGKYA;B
zQI=(AExWU{;Wu}dHclLZuR1BwzL@Xf8ctjCvHtaE_2%nuYbO6(`nDbQ)G_6+{QQ{m
zSAV{3`SjWclXd^t(Kz|1o#m4st1LL`E!%W|_B%Fk-dSJS`=P-X_dVxBYxX($%uf5p
z)SAXGuh@3^$8N4<zvyl3J=mG<z1QO7_Ub+O2s`=7b+xyhdDPOky{ojt%pNE0b<90)
ztN-+rH?H_ZeU~?%^W>V|ra#^ee8<D-lKp<L!+G}{nZN1Eyk6U~Zh39f#~Mw)L;Z-!
zJ*)5i*|m*5pXjtVeX+BC$H_~(&-u3xb*=pRC+&y__Aei{bkEX3PrtEr(1+{x$8(;>
z1H98zH(tzW-IX_{>u*cD{_d~?ldBJ0Te;!>gOktxykyt?Ye(m4OD@SyuZ7N&A1jwz
zKh2VJ%V~1%hr2t@8@zS#F>m?x;&Z;e?SgZ@&|Ut<RH^ZeE7lBr_FG3JAN%a~3;PfF
z=KRJ16Z6kGbbe2IaEGf@HaFgOXh-9Lb%SnpQEllb>brOSbmX0{JLk!cH=cacL$w3<
z8!I39j-I^tTmO{zUU6mC-1M<(bIZD}X6v|evvp!)&zXgdJ%5%p-t)c0-t)!jZ2hGN
zbglolg;mx2hzIT~&-?Jg$$8(o%<gE`(>t1fTl%fzI_NLV4x7I+?VkU|%T|@@BhxFd
z&xWR#j^MJ6T5@1Mwny)<t=c$ji+*ugw(1wn%F*msI-z-`z5j1|c<)bjft_}F*56uC
z?rt61dDN_R+5@v@Q%%cmPP5h5jdtvF-NEUO$Np!w<7pqaLr+;df3#Jp^3LdV_1GIr
zgI{0&#<QlMcth8*2hKnI-OX%t{kBWXtxK2MY*&w6x<k+FPa59yxPe0#tskz;tF61T
zG`~0NsOG*p;H!;#QhjswzVGEnz3+k5Bj3NVR=J^WN1gp&JK9+@%gf*L>5eZPnW}!z
z-NL=HuWe_?%<IhhI5FX~b)7anFh>2xO7)~~NuKm&L*obRaq@)KA6RD#XFKeoB}p>M
zLj=s|d@LyKDtoK!=zQ0zkd&E*7VvylXEv2~u71S2_jzQvd!PQVW&4yv=Yl%-(pnwe
zqeBDTtA|?E!O7Z+6}Q*+ddsm7Rt{f2)m0wqX|S!7rN=>;ecdnEW?(AoJ!yRLImy=-
zpPct}&FB20>V0`2Z*IRT`PU>H?I|B{nw3wOX;~8L)seGqTW&kg>{Gs?%eua~y?Z;R
zKA7cm>U**SC%?(U#*ev_bIWgBLi<%Mo8@{6Yo;5R%p9{Bi;J9_2zop#E;&GHVx<3A
zr{kKguTPbsV)pf&Omt<|V%%mOOT5b$dKdbg&1Vfy8OJqm3fh>SMDWbPD&?y@)KF!r
z&v<7qN!#6f+s0dyJQPT}dK2@n8?~_7H@V*Ibv-O=us*BNVOS%FUSq6T>Qi)HVk?p4
zIA>tfx~<e3StE?@<IVoCh`7YrB&opBCix*Q0_%uTc<Yf$>dG|FI;a2#!o^hP6QL^1
z`+>R!;_((5l?#@5rHLBL@Zc36R)r$OJe8?;1(8@48NN<LKj*0*N3Ftw(y-w(9*U0g
z6GAV&5?;_pROR5qtAJUKH&_xnaE^16xTj~;b)+JFa03vex^^%Jj&*aIU^7*-%UwmY
z=A5Ag5>}EJ#^@<hoM?@8aDp5!VTg*5rz7r&B=!w;6&oSL(Z0Mh(=51jUFtdCaMF2(
zF5^|OihWWR{STzxG8!Q``0-QO*>ZpZYf94SCAlt8h!uW1?ovxDKJ}TN&h|D+q&(qz
zcoI6NeUHtmPou)o?D>h8wI&#Ur~((5%mL#sMyYU}EIKW=%U~9*jRLHD6Pqz|R7&f=
z7C+?|K>3s|Fs>BmCxpn5L_n#mPH+wy%Nkf}SgivOSjYS>5lM#rxeU?fLEMw?9oe40
zIpCBfLbQ8kvvUbirDkbxFcVCGP(8$!PS2_rySC7dKh+cB*TS%rCTG@pCw!Z~c*I1)
zA-Gu-iWo;yr^mi5ix5$b17VOzfg_SKt`!$=z!MQAdGNv@ID?32=f?~brjFIn5>@<p
zj`Y6;@gQE5wTS`MQ{VCF8Y9Dl0=As}nTxl4_VL56dj7~;Z2hu3FMj4T$DIE356}A2
z#^Z0<_@ia)>G{kt$3A`Z1sgy0=;t^7X}4?Nea2nK{rKsl2fy^t+TZ>2k#~P`!`XM9
z_{!679sI~WYrn8@!!3_Ly4STYyz<P3y*Ive$bG9$_|0R7pZ?LckN<Mr-5Y;&_UD(J
z@SCHKf8pWd9)13}f7$q+Gw#~sFP}f^{LlX6^zUyx@?ZGQ&%H~|f94$rzxdEuU;5+m
z<PY9^=JCHf?`{8m^yybU_vpUR@4MmnU#)xenG*)Ddgzd|mmG2TPOqH(8PabZ{Qh%m
z7uUac>j`I`!G5D(y?5EwFCX%T_dI*+J1$yw*M)lwok1;&JwI3RkV5atwX*x?f3?AE
z!fNvzPpv1(juR8sy5vDS`8$~EFf88e$Y<{Vpv^QtWP2>1tn6{)rRDsl1In}So+@8?
z?k!1YqqDk~KOkL|;qHeoZKPq6y_^5opO4(iSf8-cxy|yTR@#~Q5Aej{qQ3OJnx*e!
zh_#r`4)_FLJndQP@-^kv;j%pSi-ywSywP)nOO}ph=GGjs+L~`_WVrt~wMsm*lF+_A
zU6bDI4W3;hLmlh@t?|m{+tb!B%-(*(LFIS-;hnsQ_-fZVvyKWCpgljo`j5HP|90Hk
zjZB?3a8ea1bt!;;@>k&IXvupG$esOPkQkoXBH90&Ne$b12=K_{_rJkwRd8leH|ZH6
zrUD~nEg!|pGVLw+;!6<Wu3Q%MTIY<RJ*-;kGNqHSq&Gf*$&$i6<+GkKP7Sqdl=s(<
zTjHfO0(8Vt+YmEBAU(zof~nhiq2wuY68-u52?)GCK2mMYa`_NZX2DYL(YQV$Nifs2
z&NNS!oMBgFnwLw?+2{zP+?BK7lNuVk^@dv*l@pz9bXvzCOAv0R7rQO8$!Ia_apfd?
zbA<=UOEu3-k~!QyG7#KwzF9XmU*gZr=gC0d_+;JufmTnLBaBXpkfU@RB%$6EuCk}e
z1+Z9;ZDSmgAve=ZT})?A6VE(rGF4E|>n6>f$cI9QC5|LpV5>`;>{p|zDBSSYfgT2U
zyB#~Qw(>Z4URH|B%(7Y*?EvfUQQ9EWjCkzjHtUj0C_z%!-_&-W{GLod-<<PUO<u3u
znS>)VPmDI=32uZ$LsPDX@Sa(l4EX8z)<7yc44#|ixpWkib!R@I0a4JAI)!`~_(Ae!
z*>7P@3q(&Lpch~pl`Bd&NyhzRgr36A2c{sV{4US4f@R0tRVAx2Av$=E;>|PXFm*tJ
z%G!YMWmyB%V;F-n4<-|#K5h=lG>@iUNf`T#<Fs>`3q&TECq2i08Ze>1Qu$!X%>k4J
z{sih{hFec-C<kBa$I2@O3|_&$mIcINxCAww49H3;iwjS!67<O?cnhyy!J2~$>rzmx
zw1GQDVO@53x&deA%aift-m%yS<<xc`pD)YNH(B)2Cj?&4$^mo*pdN4A5D68fsZT<X
zi@RDIn@I_3lVwwWAQo}~#1$WteXLiMjI(IFs4v|(tMI@TI{TDP)Spa{yE>ycc%(pX
zll-WvVKc2SMwG-fD1?z>BISW{Q2e|q?cIn^EG{n4iTBC4^>njEb#&z|J=mruMX`Wo
zfifA-D3esoQs2Q^*e$iJX2Zh~MbPqoP!h`1bWfioF1G_SRO4Uki_F$c1{@QtK_G#r
zjpaHIPL#BC(cJO?TMLCUz`$V?rbvDzb!&xsZ|YSeoAFu)T6qADs8oYrY@<@zj2=o=
zB8O|t!Fk7;+Cu=#FFh730I?MF_CSmg_~JV->Rr(BWal_`wo*{Ou2@5Tc^V`v0>cdq
z(BSugI>RK~ymeEm6;=083sPp6NEuT`IUfR{^e|hj$fPI1+ux?gNC-X%lV)NxwkKsX
z;|k%9U(;N}LsAL0g9$!ROU`K_&4~h#b8y$wST0mCQpHC!O7(fJ-8P}49b<7%i3ByS
zDuxE_y&!4^6NbvkaDtF2Mkgxmy4M3<QvCpaIIgtd#sZv=%1nZet60x5*Z}RrqCFuR
zy(yX{$Ev8OC(+-;p6!(phOMM$NlQf+o04&Kvmm1^@B^E19CRT)^F&~Rf3S4iY6pAH
z*SyW7Fk2by5{kx5U%XLx0R3oESQUGI3{?b_O15>B$wo*hKZ3dhYH_tWByrbkQ_13o
zK)SQ%fW6Zxj6lw$ij8=*N)&4k5n}lcDcW0kI7Qo-$2}Bzi!`gNkgCAN`AINHire%w
z4+Tf5;JFNr1M@x79>O&07r6{b-2x!n3QiPLFfD+w#e?3>)PkxO3S=|r9E<k$dDjr8
zPJ%DHM8l5Ft9T*rC?v%MA#qV{dUjB~M!<Q?WZoL>I3~WbtB<ZteZiR<PwjSI>!v(a
zI)mR31>jGVuz*+(C22z^6a&O_u$EI8$Bnn%T3`RxVie8on2_5UIuk8a3|Z(5O@|D`
z(Fk$R-sOts71}BEwN#z00FgL*FR^s!E3vh=AYLP&!(^Pm{D>uWwJ&2RZ7baAV<f9`
z2s|hr2s3oi1HxUyo=z}^%vfDXggsU|Hc4F2=;+D(;&F`u?tzh&NZfe;;%V^$=d3)E
zUM95qc;*MNuV@Xv(JqpWaYs1leHI)<OQJvT^~uR<&k)eJnl^ir@^V~Jd<%sy(<hrE
ztTvK>3+;8>px_!%871JtQ`&JOnz_c!naHF|$O7)f**bMa4RZz@y))cSilyf6o0F7%
zRMH_nKga$&bFktqY^r@0q#Foi=5{$}+8{%L2?Ix(KMi(EuvNOF&00FhX2<OEQN~oB
z;tYJ!NBN6Rqx4u#fSNO&o5oU1|JJ`pAZ)oZ^J8gr8rHlzEk$rXTjFy{9xG+pH6DAo
zvR>R#zO-w=#%C$GD)m7dx>3&=O8KH&R#t(b?wUx(c-k)w-pXNNC(`EUzbBsA_Kq)L
z@%sAS;GB(2PtxUqDefJ~D^3rgcNTAd`cZw%5NieUbH)~j`cfV<nXd4fLaiv&7JZ$m
zE~Q}DvfZEbJ<yMp7)B?9x_-*)*#RAD3d-i$wpF)o#IvE4A$AjPWf(lmweD+@3Q9`n
zItu_hIP2`}^=Wk`=ymx%n=)_d3=CYtHYV>HG@GoMUtg?H^28_3oDJ2?dDVV|eIATx
zE1}fQS#~4qs$}UbV;D6&9ct8g3T0PXpk;oVchUUAxYvT&kMJdxVAct<2S@25voxkn
zS{t(N7AwkUNuf7tAyKm^EA|<*@!&|uP&omVlq{EwiG)PZ^n;C5nD@f~!7CKb>yWA#
zlt8XK%|$ee2!e!~6$$Jl2Uk3;&XJTj#4naQl0`uxaE_gUQJ>N~%TBB50`&a=*N#(^
zj;Dm^0mK9jJ!B*!3WRK{PK4cb^fymLqfeE56<C)>>O^-y#i%l86SIcMKzrv{A~Vm5
z2NZ3o+SN`Q6~aWAt72^^s?J!8^$Za^8AFwzjEWU#iAb_(Wu|S5aRsu)w~sFs4nmf~
zp2qM2_dq2Be=G)MM>H@-lNR!%Q&4U8newAPAYX;3AYB@7Vde@g$el`*2*e07ucIrc
zs{><+3`eqEXXOa8Fhv;nNrtC`N8_OZ5ihjrlXtQL^w}scdK3o&0e#v>h74R@{!6{o
z(EuMqHvFO+9x2nj1~sb046s2yF|JQYkYTBxMc>dvj`l=)<^k~D6}mx0@u*og9uLq(
zNDFLK15tEkyeEJeo!Mv&Tk3IS?}dyI3MHHyf<Gt!bNF~<yC`#x781@EZFk2rg*;`;
zA4Q|Sx`gmPpn?oQC&GdxfSh!XSWA~e9_nOLT0IHl;&sgU46{ww(^N}h#&etSHD$yg
za`cf)a1ipOfTrz%&G6IXJU|SfV6iS>V{1GX{?)w2$37u1DCz3)G=zqU9i7tDAsc{=
z<1f;wJk3V9gCmf}!7Eac3WZKe79g?g(WY?OMP(dy;9nqeo;;Omg?4ow4Ga<ztH#;6
zs60)P#^t1|Wl73JHw|_M9<h*9f}aIGOsxhIU(BhqUS6Q8@-(~y9l>jH0o9?0QhseD
z7e4T7wiSzeen|T{wTO4bi8_*5I?GAFqw`RpO%#a5r=P&L>w;%ZX?S#rwLqn4zA!fq
zG|-E99M*wH{6@tEm#KO&VmJ&FtCpi!xHwWg97mY&qYEo=Fc$A3P^8cxa7@JmIph^3
zJji?rN|!Zuo$!nanw(HfG*ze!!<SfUorG#8J*OHY8sMl#qBHuv+METHj~qu{8f7_6
zqvDw)tpKl7`7z)K9-LDo<=f5pGx{Y-OFaRHSDjL1rh<^t`tTzd;u!b|AaDVt3PK{v
z>QK&YGiIN|nT!RwE;ApE<rLLi=aHk~A|Rb{U^0qFanW?{^bx)}=%fUrA~hc*jBN92
zVjV>zubc|69AI7`DAZ9Bf2@q4XyC3=lDHy4kxWRQlabxIfFTbrgxJX!1`WThP>NWF
zY9x}v&Jst-h%bf!^~o3G^J?w-)P3$t;^3o7qQq?rA;^mM1-Dc@>41)Pt8zFy@*MPp
z8;+}engmUrF11c@Y`0Jet118nW7~j2CG)NhYD{>T;U^R;x*`%H|7xK%??}Ru<VF(b
zq2fxk6TQ{xp1t<O6^aMxEIMB8w~|BTovu)pOE6R3=>t@1DgHg3JWAnyRGjG@N$-sF
z{%G+itl$SOpfh4EC@3Jt6hP@aqI>U|!d;QnsDZpBRa5TV3D$d5ON!!i29dH6=!ddF
zgrVY~PFjqS;R4YPc^|YU2&21}y^eLc@1iD!&bStm&_wpdfD@sv6PN|ftV)QY=nqN)
zY$~=wmiRyv#l*JGCn7N{m6faKXw{*1ibQej#WJ#DTMguwQ%8ORjx{h4>TvanWJ7d7
z?}#?p0vs%H{Ik}mScs>&Bn`kbcpVFtYRixBsdNFZ$W+3c^Bl6w7YY$i`9)|)oXtk0
zmto5z*a#cMyz%xrm{FY?HHf0kl2F*7C{I<V<`ii=XSkCWZC@xzJaG|O^#+8PA2piD
zhNHVEJ`?24Pev&O>MasMiNHb5R}k&gt~eqp%5Te(M2G4sRh$SCk*`rkWQLD)#375?
z*hs;fSG`HmA>~LbPE3@K)}U_?Ml5Nqqhswe8;<r56fXc7&N!9u(fzavda~%i<0DZ+
z(d9v5P?{!{n8G}sV-YL9<8$~|MN1n;fKVVGs&et53ZZETqM@o(YlsDKlnW{gOeAr*
zlJKCDbT(p%3fQ#gL3$RFfn;?2a|)1d1C^4%kcI-Gbi^SJ*|O}M4Ef(UqLN|JIt9>1
zHDg=>*Vza&vzD`@QJ}#j>YIrxMsG3FxSY$2M^aCwickr3E!2$lDJCxW8n+|IuIU)=
z5sD-7J*71oDGwJ_l1uW0A=a0eBOwU<96TbVj-qrV)G82dyo*QNLoRy$6Pkr`o<OC8
zQb6E8t!i9;`CCepCwYZEG@3*Q>k&)L6IF?EHV=uwBe~oYST2(QAsnOy#M7GsH_5xI
zbe<L4UDp&us2>~xnyE~Z2G60*z!ftSrxAfnOdD+w^J73~C^k1asyQi?s_To@xsp1Y
z_3hr03V|i`qNg?#gq{>r2DK1L6>m)MP=6`=075M~!;k+E`CBO)Yby>nK)0!!b@DUs
zBF4<QqJZ+_2+$!D@jwEJ7v6bvb#Vm7iNh7X!ilVa;dOH{$}nuEJV&bu=`{`T2I3(b
zFKCpbj^mVM*CpZ4v6n~J2m$>I2POVvw{4Et1T6{=rOmH}<aYXWWJKuU2=`-S!WXuJ
za%*E?E=h}N<}jHq0%fqjAf(Xqv~)~(jG%~&7CU&vMpTSp7}+kCm0f}o7D8MLtBt55
zu1&}`h&%KRf;OAsLLDrs4Ad`_4Na1spX$S}5d{(T$e?p75ARMP7lmq!Qk+{|jAx>r
z$4iPH9bbbHDGSc+sk^R0?+X2mg>pSD$`vatP4aUf{?1Nu?P+3w6q1*~QVgB+qqU@o
zq7m>q`~^q3a?QugVlT+PaV{lGWLaTzuXqxJB#gl)!mL6Pp7V-vEC3gkDvEHOu?<up
zL>C`rCnTe9EZeLFA8Fzh3m*cyL_dcl?odVsQK<PmkJriya>LKIbqFdS<7HhR0HPQ2
zMEFS{7y4+Ktw86Beq$@5xNgIlN089_Rm)6gS;#|yc$c2!*2*NhNnLJ^Yi&wD@Zysc
z2Sr_tfZ9%Sh-C(%B3|4DWhXqZ?IG@1m{^O5)GVN`gPX%7X^Zy*Dg7#}L#}`_fgl-d
zXGNbAd#3W!67O_fMubEZLry{}s8VUjwvN}L^r8WdVi!1ixfZ#$S0P~*d2M<wCoAS4
zvQiI@3b*GVPy9i)4j>b>3=wRGaPFK7JxGidJUj6{0@@&gx9C%gdRpp1I(`Hhf-G@~
z<4S@>O$j5&XON5U=yFaNHBICvYymNrX1l<Nr~~OB(Ggle`KVH8(QJzk1p$*oVR(wh
z&v7OWYUU8;A1|$ZQHSDve2w;`pb-XLPti#1iJ(l`Lv2+;as*i*@car5QoCX<DUIaU
zLb-({xz-t=(GLcNdfEqa><vn(z6^Pr?(#OUXqvCzcyqXq`8#qUxjUreJr0WC@@>XO
z^q@tWx2)Mw=8~c3sgwyUw>I}W2gI9a71{3cAboT6?NiHS-fyqwW|h}DZ%S&ES){W+
zChu9u6A)2ndRAVU<pnETB}=@Gb=XYGb-oPiVX7Hbc>=$ab%Yyzc^8o0db-Dk9^k@x
ziiC8r>d}*pbT&D6yq?V!_~s?PWHp(FdzianIIVe^`#YDcVQjmcDK8u~l=r2jHJ0)z
zA2iK*V#F|8xmoiA6ttsOH!=4&1AH(WR^q!erIlQ~)tao)|1I`_B&C70+*+ar>#;Yn
zdI;SERx6E`WwxH(o4Ypq(}7y*C&n6MJ()Q->?|Co9#FLwbA6ibYLl++nVil!ps&VZ
z!BnSfWD|6#F}mDMtZ&k49lg?QxNjNTRS;p_Co|_djkR>DuD1L-J;hC7Ol$1oQWo>P
zOwVI^5ICW0sGO&v^9~+tr0J$J+6fx8m`OWm(k$?*ea|Go#HNnSl7zbojKf)+)s*J*
z_y(G+bCyEEwxu)X-1fLEA!$<-p!SJpxl-;5`2@yVINg&zNQ-+|2Hh{SzDhq-ZpYrN
zQMxKkCNZze%dKG8e1~-4lwL}W<1hUJSI<jK9|>2lmn1dMyG;_u1?Gy?*_uQtx&g8h
z?k)2kGhFGKRi?c`eaYm3oOZDLXUg0#ot5hCicOZ=WL|?CJD{@8rBsh^Kh?*&*68*}
z{dCe+`A4<8O^w?C`lPOG%lrtPuji5~KB&^Na(Ab-lGJsSliMvj*}=^7pCki`)do^)
zaj|${fR#KS*yW@sNvb2(GtaJ=pfBMWCI>sR8;?wVVoUAj8x~u*4x#CCU#p}}%m0w3
zEkD$qUUI*c2h;jb52EMwYgU@!WtAUXd~Wxn=_zY}+#No(>wN7Ax#xnNt+mtfJA8AG
z?wx+Rai?uw+Vha~-L3i6*}f|(k8S+Kf<M3c;Q3FTdVF<udgtVaAGs#^>f{02{CVWi
z`Ct3~N0$Hbs-5efz4Q3_Us*6b-#@mf-ke^v{5Q8By3-4b58eKed$--^lt;F$fA@}g
z<(F<ebiw<2`c@48dC~sMHg+!UzvF;6um8^XcYfD}$E5$UvA*lh8y7GA`{5JQcOCYF
z>Y7j7x%AOHmhAfGU%$0_(%VnmX3gq7cK!Qn?^?X!qHWT5oq2e=_V*jJhp*e1y?kb8
zb@0r?=dXM5BiTW-cXjQz^vwBtkzRY2*(r}*oqb{PyXGz1_00JfZ`wI~>9Ma?XCHf^
zTlGEnr=J?xwEw4f+O+@U+i%(QQ~UFmKfU0kbN{jW{&QbnJ@;Fm^6$I*_359VJ0X2P
zzn8vv_=2adId92Rmpy*lJs<h*XWxJKi5)Mz{QB~rzqj4Wn}4+3UgWKK@qH(*y6`K9
zuiSFaVS8<P`FOkVnWNkhckZ<KZFioq8+rTg{pSy?IDgCItIyx^-PJEXQ*!sc@XCq}
ze|kr9;h*+N_kQUEyIt_|Z`~h$a^4~T^P@f1-o53S-7Y-yqGfyk<+i~SpS^GChL_p<
zbMKbwhL>;Z*znR_$%gmrJFwxoU-e(~>#tYe{p-iO&boI?@;?m!Eib>AKJ$}T=AHfU
zE8AYM>2Z7MvEQV#KmASo&d*Cvf2woSZr|#8VgGG<_utgL;GWMM-f_>l+mxtt=Sy2Y
zmRxtsJ4#=9?u61y&z)F$|Cc{(U+tT>+n*o$aQf0W{-OT<TX!z~_{_JZU-?O?<Ed|#
zYX5yrDZB8g6Zid}PoCJn<=zwB#V^0k?t5jPee#R_EB^Au9lQ5F_QXBjxaHF7n=ig}
zpYt!icK(IWytVqumO~a?^s7e41wTK0{tjC{Fu2zjKUDjl6ZWjWaM63KU)^%ziuYZ#
zV(A5cxz}y@?H6hn-}|BDy+8S`{psaB%Xhu}nRNd{-@SChiO+Rh^y{BiF8=k`%NM`=
zZTr~AsqYD=m!7%k#q_K{J$c!0haQ^$+x5S~o&K_<eKC(c_Wk*fJ#u9AJ7ZtY4;%Yv
z^84kNRnOgLQFq;4o1L;GBv17W+i5++rLR2MQ~L9-%w|9JuY=)JSJxg~x$R(i<(k2n
zD@(PRYmc$b+1m#BrMEnCNaNSvs?-{N$;zkt@;Cp_Q9Id}&pmY6?zc2|IscY5^XGr;
zs_OiY{b>G4OO9AJuq5eU_xy>~b${49-R<G4)7^eBoi6_T$!_GPH!XekcY7~;_AeI>
zZg|`I$%f%K+l4QG)t&#`R~sV(KdT%#@a5!!=e}s?y!55)8!LV`?;D?cA$?ct1#9@<
zBv0*iS;_3uF4gUjAFF;7z18DpZS4-vCr@4Qu-&nI(r#RGsnv&OlgA$ENT!m+R{v_)
z-uEPr-R@(Zvmd^?aq!BH^ueL#lF^>w6?SD>+syXE%~{2T4_{(SAM9WK#5H_GHS4U|
zwH@wmKkEMFg9oL%^Ki)0$Bx^jW7AdDWJzD;q$NGoyT>Yn>;7x|%JL(xOqaiPJnh&N
zs@dnSPHz9p>#Dc^?%2U~zr4WqWhJ|M{ReHY^;7QDo36Bx%5>#|pX8Nu9{54>o`d_l
ze!1)SItE*hR8IGgCI?o2fTy%=f9uRP(t^L*?FSvFFLXzoeyz*?dwNg*RNm9G*>CJP
zr?tlc?-+XP5f|I=8XIQM?sE@!JTh|w8%Ji6FXwOTKK6>)uF<L4?kO(Vy>2KkufOA}
zboXZ`>_3m#zWNW-iz<Wnq;`7$L+K%QbbqCFfA-Gbj@j51zI0t^&R@&k)((41SJySi
zR^Kx8uvHJu7rT*a`lcP%)^_S2=|1?mW4hjT>VZ4;-)yftwm(nb@poUczT@(G-aoRU
z|DQ(s?VYLJ@NZw*`?AaaYlrUS*<Jd-_5JGUe{=qVwVO|$XV1p-w;t8+k-sqEe{ecI
zeY>$E2d`~%zi6y{bAE2J+5e$(L2KO+i`?G~@7H_Em><T8Klz!S>u$e)UY^g+JCfTo
z+kfK9?y0F+)>O^p_*K@w`>IQ9_mi$Joj=SM|E81q%lbcBI^*VJI@ji7?3bO$);wtG
z`YV#o>w;A(iC-}q4y|U_bd^Wk1d|C<&!O9=tNOaq9sBtV&P~bc%AI|$+u<v{%&F)&
zc0<RiV><?i_ByE1Kkd8R&sJ9M|JRxPpC@iFcexwNt49XXwIhQar>|dKaYqcWR_n93
z&$1H!q1is;jycXB$tAbmpiiEA^Uf}1Qo3V}+0BQ9eEJY?lcgypDHeE|x00_Rlew3f
zZaAA|ZNS_gSMOzLng$o$N67jzo-N>BDvJqsKk3<0V!kVNR^=x#><RLadZYVq+YxxW
zL1naHOY%C*Q`=Gbx)>OozwW9PHCvRizRRtH6IjRor~bgaJ~`mBd{;|QJKkGK`|=d}
z>qEoyxVc@{`v%qlM9pi@&%fY%S%6};oRx$l?#2l^5L-pgA!esBuS+Y|TM-{9oGUG4
zjVB=)+d-)mz8t14Ar`?g{|mDEHmZhV{G!TAu!JNX_!g0c08jqvaW$TM<qnAkXmiVv
z!+j9%Q85U&i!ynx*1<#T>j5I<M=g}6^Z-XeS>N%Qw|A7OBzWpedrj(IE$bi=&A6x|
z86lHC2<c?GR*-V-#!~>41*)j32G%m=5t=b1;}jQNM?K@26dqf31}|5`R@ZdWq8*T{
z<tXeI$OIO&Zj1UrLvA!$*-<WDPs@jW64)NZX>MlJie;!nkQSnXZd;S4-YMF%1QT`C
z3m&Cnhc)kp9^={h50hOB=A}z~ues=zkm-wSJhK*97lWzsE6&leb76FenzivE|5`**
zUKmsp1pXv^QYThGp&&=vK0$UG`ww@&y>cU>pkX7tr*|dD5Et=?kcvk_r8&n{cZgjA
zv5sMyf{ytrAZCRO4$^uRKg%W*C`Kc3agK#MMZ8wZ1!z4VA%&tN@|bXzdFRU%<C;>N
zPJ(17$k(u@pKzX$7_Wd7<t5S5piU+(mx$Vd8sKNF<>v%OJEdy#B#3vB?}>$?Zc^64
z+AFs!oMbwWcQL<BGhFs0odsbB?AX)q(w?9GkC5W5=lK&(|K#sZeDb~D-t_p|hc+Ga
zFVDZ{?2rET#9tjZy6K^_zQ6JKTYsVN_-y#haSwj>s0;t_ksp8I#<%|F@pr%YrxSmC
z+tDkox@PU~e*2?e|M1NH?>zCvr;k~2_cd#8diPImegCh&`lBuSmd=Zht^NFNfBD^c
z@7n95YaiWs<lV14clJ%EzWmHP&e-&$iyz&%?(X}JKK;J4&v^2^2jBLSwI9FZ$S=I|
zr@{Nqe*C86&baTnvtGR8_<wojxn-YzWy6!low4b?XaD%#7k1tF+!@=QdG=lBy!eIl
z1|PlWj5Gh{*}Hc-bJ<<TzsNU*zI5*yyDs_3Ehp@_6W{Uq!h4r}>7_Gn`kRYxeRyO=
zwdaAik5bo=Y7fj4z5V4`Jl1AxaN45o-dVny=Ethl(I=|ar#db#-_9dk_KyC3n>lQU
zDfgCib5_j`?z67toQ~}kDt205SN8AMyghqx>R9`;9h<IRxn_BC`*36QD<h4yPi1y)
zz29||cHoRZvAtVsmR}bR+u6cfRwv6xR(G76r5Eyu;28^(?swL+uA_f(&`uZMo|&KO
z?B%-|+i!PtYAZf>z=E-*^HSfx!n&us%7fQuZYVj>1}cY_=k0Uqf^GIGRT`&cY|C6=
z^Oi4nJD$XMCaUx7_Xpu7_ncQztImPy``18kNx--^wiq44{53#UWc@Yze@lh`pN#e}
zc{N8JRe-eEx&I#m@{}>x^V?C+QNIYz?C)-D$J>Wm=;BRTnpYZe?}6p>Go}Qqjx;)E
z0z|y(cjUBb_*QMkP(pIA#Jx<+$_%^*oX_Iv3QCFF^|N>h#y@q>1NWrIWQB5o&daGV
zu#%+kIC3ssJar7(B?<l&iQLfQwA%MPU{fJar|f_%U5$rjW6Q}?)-mln*-i>1A+ri!
zUg8l*If0%eb4_M^Bo$BdA_|A=<am<lS=uwOBNe^nmw0}dnIxGCi+JV)ts?fap&`_0
z1TIaShOM}mu%@Z1ajTu1eMcoVPL%!99?~`wQtz2NLWiDN>0}W^fg~N-wu4DI<<h{o
zF6|(4hT3GdfHUwc@E#McP31P8<d^FSPA;6<RplFa4#E}<nI2Y485fp6Qj>ohy8J4t
z0<g02v#_11x>h!8Y0;z7x-R`Z*wKN-s1$XbDQ;0{-^i^eQtl`mq2o9$lc1hcYceJU
z^~CJ<VQ$^TCPoH-;v4u>a8m>{5|<hrUz^bktP8vj{Qx~T6C=YRN=-YQ(DB;@9DCAf
z{In>hf={846^z34D@%vO*r^-@8eyfRvk%EBzFSoQcppz>ACr+ouwC%%5z9MfqrW#F
zX$hQ-A`L;5pSJ5zl*>If#brzh_V88?G5*q?9y<UDUd7akf^39fC|kwUgYQ?93`>6C
z7e!?(_tKPPjR#{>t|jMs$5XE(-{`MHHn~#VRUrYFha6kUgQkw4t9Oyr*sPi$Bt{ck
z*xqcM{7H=iLD}k7cC&qr_<gM}oiAqW0ihG1KBLXJ9upFEZtG)g(T`|JdUZf<C7)qU
zIw^f2o@L8jgR<fYCgc7V*sL$_^Bg@(9~zRp!q{{lx&!@DS0I@vg$I&AQ07aQ>}iUR
zrD%ng+9Vb$!^3ko(_7LBBRVw`VF(u18a=x`YiA+DWKo|apDZ4&g{4E4a{rYo<qG*k
zU4Z8-pF6<T-um4WjMjh*Tf`t_-1SVNe(G8(bt3`$Q9NBG8O3BAF5g`^tianEBw&R3
zp9_7?+qOI^4s^i}xr~zDJj}#i&Kd|dA>L7ndQ7Gef=f2*GFi;#Jh_|=%u-g%dUT^9
zo8B{aJ&Hi8<w-M4dS%=oL23LB$n{?)N*3np=%sI1?pa^8?dk#<W04pAsI2`cPI3vo
z;}FKgJvN;A28>Dd(7-Uvo}ktYnwufR($Gqa$d~>E9q}oU0Lo74C^?CvVhjuRq!WV%
z7Yura(-V>nblD1YMY)g6!w=+uGEkxBtVV2FWrt$Tn7u&+%L2`fm&TVmeUM472*M$f
z1)mI(wF&?y!KIKm@kHxRyM~B$%qmo0>&@v=sZ}PUxOhvY5udZ-nkc8eIcqkk_^5%X
z9RhGkl9Ufc=IFtIFKkShF(Z}TDF~wjuuhNqia(P@R-9om$UO{!+2}el3|v$@atX@W
z#mom3_e!`ae{A;j@6C>!<?U68Q1sfFkTqi5E9B)C_0(BMk8`7>U2aa;-$#~tY$FUp
zN}5c|&jG2Y4$@x`_%$f$!8^`g`F<B39O?lT!g68-ZEbxf|02+{`bCa(XpuRd)N5uw
zS}~SLI$F*=WR4<<vxEbR;D7pcm%^ucsAmu)F8H-61gUrO%uKBWu25@EMG6R+j_LeJ
z?A@>ssI_;-=#88)n}u`0wb+cnp$&9BC-o_(b4&*DP!NaY1_n#)ve~4BrAyF`SEEJ2
zQ5-#{4cz&3Wa6sGaBd%pd$K^|T4Gc(X#Pp#=2Y3?UN9m5^qKfM7jiYk5u=dH`UF{T
zjZz_w-y>fEZF!9ygo&SV+~Nu9M`(mRWR@LnPv>yXS;Jb?7gtQ2<pJOsBz^Q&hVa)^
z^|5lV`YCyR+=RG!1`@1*>&E!B1-eAW6T_SfHKInrrc0Ivs#wcTgWQHK>7Q;PPeyo<
z;sZTd4JQsCJ-JQ5MHtn^>7IL<@Dao`peW37KWPoj3`F^?WllpcX;sljxxCYhkZT`_
zlZBkTRh*Clu9e}i9bBmIF!y;bsj!hdbv54W1()En)PKorl!8H=az+`;o`0BuZ-Ot7
zRdX_#f&0;uXZcLxs4MLpN=y^^4L<5%=B7~x=vt^=z%s&N6>PiS(t3U_np+l_qZ%;4
z(xekT8$+3HRfhIO({VH%*)f@-C@PW|z{Y7=(>zd~@k5y<VPKEIns;B6z<E#Dnp#G>
z^)B|;7@8p`AM$4FXL_h$SGv5#$4GmS*kXrLU)7;oaBI2H(3`X8inG+U=J;NQeEg~Z
z?k%6viKgf6^r6GGc3Ie*puchbkXt&vSr7SMKFgOg$Fyc4Q}1vs_WvXxy4O^v=I0%&
ztD)Rq9_~AEmUpmo&&JVq5t<I!9$NGaa9Ii8YchMw6o@*C<4wMQbKVjB^}Q(~HuIoC
zuv(U$k|q9zF?Ir3+Cm<y5nfJ*E-hL}n|5lRwH7i)@rT#jf+<H22;*@~)bf7z<7D~_
zkUha>vR0tt$--op?b#F1LWvAoT20USWiHKUGqdfd44X_Rl`)^7a9@6DZ!$UNdQT$H
z<*RgMBGKzzdTpk&%Nb*a3kk>4#RGlsG_kvaUd%Uv;;3-tjqhPgmUmgJKP1h}@diK9
zU`Cp-yM-MT3ktF<9&8D@*qJJMH*3zT0Er=WBiutQ52`VgP-9+LP}pQ7_BcmMz+m@G
zCkz;5WvI@-(WmCT05O4V1<YmY5@iHYvSx}!T$CWuf;O^U13qo53@2<6P*Q#omcrFl
z1kjZepekP`0$jE?L9yqwXVg+3)u>W1Pn;YPv@MGQ8LcHVP@<1N*!3w%TDk+hu`OLF
z(mp^hS#;+)02LFN$%l|HUZ5COf??<4F>caIB-dFMR05t=I6*54p0gz6qFKvquXw%F
z5>M4~^SIDDrM%rtK8qDGQ9DLKbJD?r6W<64ey(Daflljk(H6_w5cB0m1>|CqQH(th
z{R3vQo`Hfh8yH8(g{SAhz2v~bk#sV<FVMtdpP&=7#sW6;3n+uzD_<o<#%R+qqSg0_
z4YO}Ai?Rc~5$9HdoaZ1tQ(YJ14hhpJEK;fH>2v(%0CtgMd{HC#-Wi-bRS>{J+7~?|
z_rzGAaTsmaH8#G=JE$OqL`}jm$!wH$JmZTZc<fx;R`93DhJfbf5ti6Hq&WYUO%OzD
zghq_1?f(5?FiNdg;7qoFU$Jf-r5uR@#&FKS5TaEZw657KQXF-m!2-DVwW(*xjEgdd
zrxM^Q7_r<TxAj9L<rA1)V?&@><VQzjdg&CkysEX}d#T8JaK0R=uGAAmm83)TElJnO
z8ZH);)gBK@mu17EOc@4V2@YN(3J?Vmz13<qkP1T5dzYZQ66huOQ-JDdHlt1xGgLZK
z5rSf1&RB<W+9VYj2a}1u<Aa`Xp=IdVBGW<0kS$g$;uz-a>~Yd3sS8K6fFL`h?rR|?
zeN-^YqN^owFUV1cD=XF#{m8>2ku27ZR3;n(r3M0UW@;)WfI!w%JUEmPW{9gZHsgu0
zgoylf-V#VdIyxSY1wKe)kU?PqAqr4D3+A=1l0e3fRwF=EPmxHcmm3J!&L59O3VK&4
zYvwJM@hV+VYspYhD=QTFI?O?P?vKex%ODGdTpVP7w1hHQP-56fhJJI3O-BSx%(<Bs
zA~O;;5TfD}MV^E@VG1>fQOEIUWp$wT-4!yS6I%{~_<_N;?rkYWhQd*P^ljV~DmxMd
zZz6*7Z8K&ccwW({31c}JKWJ}PHlrwXy=r=)f=J1aOTr8c3_XW}yDsL%ZX9KSl%Dvq
zEO2y1k{I9=WMT(NQly8}F$z0M%^7~i!lq`D^D2ZQ3P~~6Bm<D{5gaP=a|HwVkzlM9
z4<<@|*Kf`no{*m<L7{X}d4JuUtWsQ?GMa+;^THL}AbQ%ob~*S-+g=P1V2`tK<;2BK
z!VDvD<t*q}Rx#9zRaMkeM*2B;1}97b&__}$bjahIQItiRj5rNv*oX#ILwMnR%wIvc
z%Y>pHUHqlw#39=@4fw`fpG2-1g^TJr*Qqr8_<4R+1Z9bH2%I9R*0H(@07*=VQq2N=
zRZ*!HV$Pg<@X9P$#z;GG@winb@!^dYF^sa|8LJ?&+^0Ge@;M9yMq3*d)R_ZW<L1Z`
zVDWPMeI$}i-2&_bY->pr=z>z((4(U<ryA=a5>6@7&~Mdj7({qA>GVFBkYPdr9EO+%
zXWDTN89yJCW-2E~t1{o#RX9~Nf}RfppC}<=F@uyN-UJ=upBn0WGq3~;RqST2C`AFE
zsI381YIA0M2|*?ghR^ZLgo+R`D9QS~7%ynt)~+CGJ1dB@e5@_7t)&>m^3gV2rtrcD
z##x{scRD7>^~Dt7Vw#}Hn4aSu@d3OTk>FpwMW=9rsTeA+U1!lL8Tb_yAfmIx2(iAr
zEFjm3EM!HRtT|FGcqTMB9|Wl}$yp~SSQ0Dx&S+fXu}_tKDPonm71W`aAwzUNodp_m
z6<bK!V!Cv9Q$Xm7gD#50Z0ppn4=l^Cb9L86ngA2#Y(mkgEfel>JEgY5DKXZyH9bSj
z&80N5wN8psRrR=tih77<G)d;{5l8|uBgC4Uv8MzJ<A~QdM$p_xnqTS(BEY6N&V9>0
zNFoj3BHBgr82zgt7K_?|PSh#lOkL=N?qgd!VHAj9hzrLNeW#eIxGUs%boDN#3%vtz
zpjjLU+fK)AZTqb`kxxu%+4|QITugIFJ6@X;4N>H^=T&m&sxuNT7j5rZ*OBvDP+Pv~
z$pRB?o)xW3m1T5bm}(U{(P=p0ym2V<qnOQ>2H~T1$Z#1Y+T|VC%^8;A^dQW2cD*xC
z01dbZN&6VbIrD{&<+TwZ4&bPQi!{0<6kS=nin%kMeSoZ}sUok1f^l$3crCVw^U7W#
zzMbJ+jD$AdnAgr~#ABu4HPuG88+1aMzF8n$K{99mtj)X_Th8WkZN%aBRH=4>9=ZfK
ze{5__d~|sf@a@IBQ-a>;2;xFiM_{P9^c3TH{4U6*!(u7TwCMnN{6V`m6Bx3nk%xbj
ztk8jt=ukwRwdv`(ff-HNLE#lWj<5h94|1h0PB5WBJ8v0L&2wrCdAZn$qvf}<g%%=F
zI1U2&ngWt|=q21bm%^m&cw!zZOLsusEcTHi$;qfswd5@FQ?H8jO+{i~h!kN%-m`sX
z(2t)JOe@F>f1>r{Tr=hU?OBS7ayK=tLB?a?$W6l5>I5XjsY!2MY|kK>>QU0QC4i^=
z;>upn*u<KrenfZ*c^w4_(I|h8Ev&LYJCP@tB%Sy`oq^jn^L*o&Vt|VwfuD;+0}QEO
z1yD|CSfl3uVejqZt17OA|F!4rlk9|mCm~=!>zy19ctEs~Qi_z?NeCLFZ6hMZ_XDCA
z@h$pLM5H)LqfexL?v02_>Am)-sQ6l>RS^|a>uqW6<E6H>7Ohfkdwc6^ZHpGY@O;<o
z6R`KW_xJn%_xY{l%$`}ZX3bh_Uia*oz45ACLx9`?z*&u>rl<=He3XnlwLJa?95=cu
z3PaR^vQr9%*P+B#!>TZS0cOO4S}<OFh7@4nQeTRq&8JYXT+95x7u7!m<mH3EBA-hm
zhQ#Jklr<?%&85kQz&Q1Vx#*BdLs+q)o(7Mq6oA+NM4|o+iI`V(Xs%c)b{Z-VEnS5M
zseN0;OqH&%7s?dVrfDmZ2c<$eltVdg3?!A(*76=u-T=bKR@0?^lI)jGQ7Jnbh7Td~
zQricp(1BsCTro}y3efhbAsh1VCy!jDcuYmv`_vcih4EX0hBOqNdRgRF9GEmquQ+ZN
z)D4b?yoM?oR)k3zA#SCRyb^eo$5whKSn5r<PojX<bS1L$NNVwW@=SR}KD0*Y^GH$Y
zA)$ac%utn4r1Ggmakvr%Rv+Fem9k2`%C<)ZjRIL$SjA5zbWnOqi+ZY@U?^T4Ez2QA
z6;}}|=QJ*j3G$2GkD$5+`|CN8AMxDO+WED#7iJ^#nQcc&+4qYrPGe3?SpY14#y0V>
z>75_tTIOc0-&o&LE)p{kS<gk)SZ%SBc8HDuQgL6-SShxPz(yNXw=CclT^D)hs&l+>
z!m^%^#M%kSrsBhK-2iWMM}J-?$n%>P<8x@}1ua`LAusJ9wE(<jH5Q&Np7aD+S1fZj
zLgmoDTiZi;{{xI{iM^<@UhgtuU+$H9e?8w&QS*BdolCUxEy(gZvAwJ+cKa-N-m{z3
zt{%7+y&|;}-yiBHH|!jH<hX$zgWHIfK4d`O=?&Tbyl<!#Q>{B@lkQ$#%{IQldN?IA
zz9BKx|0XjDqx1T@D%K;AhXS)U>X)@~O}rtLh0n2H!~1N1&S$07k;5SB@W@7Pj0Yl{
z^y`<7-KMyjmt^v`7PdL|Q)w6*x(2I|F?_RW&kJ}QHerpcg*KEMups(lYq6o9Y8vAL
zVb4^UFDjurwFn_4E9FBoN@+YL$U749zKo7t`czYU#ZU&t2CV8^i5Kjs#Ng>Xi!7wp
zdhDK|%{IrOt@rm5uXPw@p$`Sp)M6QJ*vAlL0ym(H>7u5vvV|?6jV1O<AC0xSs0>Li
z^g+I+Xlxdp5Y@*8J{GV>$Myl5-&)dGu#VwxdM@tiQt?(tQZkXO$;E420TcNeKWLNM
zriSXc!R6ep9v)f>buJe*7%3#azgC|qu(c#B^{uAAxSIVYlIhPQ02_{Ki+4&t)&gSR
z#zCIsPLs^%UAss-AP%%KO_VVz$F*)S;wHvWmB8n!lGa|-oE()c@=;c^qgcx)DGtsN
z=y`dS&(wBVtxnV{N4--WSJ&zpmz|G8p!=-oLXLgp$n4S|elA`*u5+Ypo;>pGM+(`Q
zN1qUv#&kwIH&4#aTU&^x-hYBjFSnX`Yg)43Su?qAOUDTZO}~4VX}c|-S-7UEYQ}8~
zs#{)gV-`L);bV5Q49_2ZUd^V}3$oqo<G67>+wjVZhHd@Cf-%z{YZ!IR<!vMW`8(rl
zwr##RJN=N(Dtks}!*%aYu3x`-{HW;*+ZyfrCz?I)9#yyQ;UmUxT7F_?<C0nChWxbb
zH>MSaKYrz`WaHvtnWwfMRlW1Dqv9i0ooKdvnS+kcO^Db3XhM9;1yZ$jW^;A_{NC*9
zpK<(Pa&t!Yefu~p_QF82acQ~slB*}nioN&6b0559w0rQagO}ZWUi-3}e>;2IV{gUV
z?tM#^J$iA?vPa)cR;@WYUbXqx(afC}4^MXfwra&!Tg|F_znfXU`R}V2Z~j5m!u99>
z^Rlt8{_~V?pO;Me_OFv2Yi2jTv*x$;GiNL{GiSVGwrxFk?A9%>jeYcY#~<<F?|w1y
z8;^Z_{4Mu>E4$^dmrQ;1uX`FFd-n@dAA9!~^?UccUAuM92g#PbOPaUreLuQ)$rYKc
zOa9GlK4<pl9zN$U9ebZUQdaEwYxIW|m)5?vVqbFSlSj$cC-+Lz>l32GUfZ3Wv2<kP
zJxl+T+xX$Q=)Mns8uVT84UsKxl#?wVKAoJscX+hw>g%Mm`F!KP{Z{pogPY@3cl|oM
z_pwRx)?-J-%RVz+mOXKYTr#CKTC%yP>YsL=mu%VjX5Eq_W@T30`#rN{^YLa$?g!@b
z(-#h(xAS+y8@{q2X}JB@$vf-MlO5~-C7wB>J2Ug1KWDZ*c5bryvDfPEKL2=g|L&h>
zZvJ|8bnG|&aom=FUzmIJvAr$d?mAx3x3F#fiM2o4d1~#JZRcjDU-Cio5sPP;dpo~p
zzJ1ODIrh>&$*MgUWcKWNME1;SmDex&rP+4>QSsJ&d(GIpP5e)<?=YJdjf;ybzgM;K
z!%XG@^wo1OAKS$+@S#t(+_x*a=yE>6{SzNg{i9>>_KnMa*dcps-jcl&$H~f{_QaQL
z8ZYe)|H7|5UN(PMG__o)opk%xlCifh7QX8u-Tv@+e#8HY7q5vLr~2|?>qfSZ$#442
zn0&*cx~|?=<(6T#xo(PYu4|dyJTUUNHDBLw+$YCu{LPs9E$2<XcG$1urg!H?kD90L
zqrDA{U;obPT<%BR$pg>7nmlmRXOk_LUnko;za+1({6W=gmn_Tp&OapUKYfbabo#CF
zVM|uZ&LzJw_xyRDnec@T=Fa20WuShwoP7hm><d!6?u9?s6?gT@s2yJH4xu&wCRW||
zPJ9aehQ$}Xd#il;6dTQL=*hIR@owP{e;hBIzevW8+aQx}7rCUx^J|TkH(VnftjSNc
zw=y^tOhdzOBD1L^-D|!dcMVj_q2Aj=Z=2n`<%WN$*)(!dO|<3daW(g}Mpd8w7hA>p
z$D{W9(WCjCy}qxvaQ)iPM-M#zRP6)Tj;!l%yT&v<ccwY_Yp==c&vuL7`h6Y<&XL2~
zUNbj!UM}00JQeTkIK@2hxn4Qyb6v82qL+b8eZ2047WCWEd)tO<eSX&*=_>OcXPWC9
z^lP_2!Yg^V_Qm;ox~gn>N7j`a*{An!v7K~@*_h0)8CZ8_GHLMNlPS6Jk*&QrQ|w=0
z%Ikct-0vD~zAH1m)SYSg$~|#@%85~~_p(TClc<>6B~w}!NWX85*WJ)wHL1U+Zu14D
z*k90Qd{djbXU<KHw{_Py%BxYF+?I`RSaWOCkS|5KU2XL1hsDK?UuUNmi<vEU%Gd{M
zKYK|3)89?5S!<H&$xY+^MW>GMAK7b~MjjP4HBTFz6fXOuKm9Jbe$F@<vwfl@UvIRf
zO*5#MGD`KE&z?ZDeo>rX?HGfcbZw%uTKxqh8;^@NCa$i$?rX^;R~nx87bMe@`YPN1
z%ecJGHI{kXeK~LIr@O)WDVfhR)?CO~)yg=xDJr%&hMZPu>OHx->H2}{a?|+XQ~v6P
z%W0Q0G`}ll*Erf5-Vb2w`L<6_U43zUO#>e|%9R(!Nz220T>bBdS)0#T*52=)aqF1=
zz6HtfKFi)}IlOoA_YO}+#v_|}Yh3Q={8U-=TI0a!ndo|xiK71cd~#ix!O64kF4;2&
zMM~p^A#@<JxdFzY?vYa7l(XJPHaxSKp03ZAUt*5&v$}Mr>0q_jv1{N~Y~2z!nRQjN
zrklz4fWVje^d|PjFqau9Gh}ZN>D?rR+0E+V;WGn#<1evOS+^=HJ!7b^OG?tv&n(XL
zGIwI`kuy_`*iE%2w`rJkG0;n+O^|0`?3T#;O&RhnB=JDj+cjcZ)^UHf#!C8(#rEfV
z3%|OH$|>(KPiledYDVTwJw9x_<$RMPTlqaxk8-`p(MpGZfcef^u8qu$Hu0Y3?d<v3
z9<za3>U5$ZyJ*WTq{}l*?<hn$P18qs0DSm4uBMCDVx=XEA6ss!k+9z`2c7D^3H(~-
z)VXSGMLihs$N-;wMp`!2O3N<jzDB)cH+2pfM9T^LNeeqfb<*US8Tq_rrlolie>hr#
zS7?z)HrW*K^U{nL&@(^R>LPEBY;rouvIHDIQd<doSVF+3GY{2}O$m}XfpR1vm0jFq
zb#=N18|F^w?V1V%|8R%kHCl-=2PsipJ*I?|n2>!hgv41KCT=<1nxN23=LyHA@mfEa
zLqVHk)sk;+#yM=I3oV#!tmh5;P&?iH1w+!~s)yMWFaF%WI4p^t`T4_##Ow!>d=z{X
zO3|y3K~!}DP=8^{4{?dy56A~tus)=SZ9p*hR0-Ji5a#j@e;OZRTW~2QT}sxN1K`u;
zTa_xLSDUt=iyb0KJt{**RrP7H^{7W>RAB8Y=hUMzXlBYI1r~r*4;RYC525u;k1};B
zk+R$$mnWb<1xEr;db~>BPs^nN&^BU1Kx(zr50&cS^~Zkoz}p6`0<p%8g$6#@A$A0H
zSxH$dun|Mqkv7dam5(qGr&T3bmY|WF{xauV^3J4i=4T=E;+q~i=gEivGU>*Zuivq1
z<zv74{N}Yg?|=A9N8GsbgFEIe-}<vvo4?cfc0telynV;K#rMozvh}9Uy9z(K`&TPJ
zcx29=2j))N%9);-KfU{<iy!06&)#{Hw!L@B9Wy_;d){eVZ+v;*Bg;O$?H5ZPnfbx}
zXI^>Fjh!DnJm<-MS4?{3z6;-+_t&jAat3J5W81EnbmQAs-?i$mdtT|>{P3Lnw_S0>
z!TUbA>y&5qJiluFwlki%?+m`<bM;+wen{Ty_wGD$+iCZo^(No(dGW1zlh!}pdGWDl
z-8*;RrH`ER;@){jtp9W8;d;hp!7$GJytnL#^&fT~?$-M1u5msy`qt~Qj?Y?u->B|f
ze|>KAK+V*F&BIFmI{NJExF=sXvLOG|kYD5DO{;svZplTqoRjJF#lGiy?#+BuT;omC
zmK{mc=7GAVHLFe2n(d}((@&~e%=J|h^ZsLF9`j>1mIjhd<$+|t^u|epk9#h^-fZgP
zH`V84(%_he%LkJFDbFRVTY9TjU*+Sv8EbOM;x)O|y<cfuy|cHme{q9sEY6W)O;4u3
zsVBOn&dZFYUe^8Wdo1^Uh3ER;kN%-$(2U)&gStB)s_(#^)Q{yqiC1_1BD6iNCVvY)
z4cei4Krq}7rsz=lD&GCIYAF1XtJdQHk^1y!=r;hZp#KE~`u&L@_^5wB{of$dI{lx;
z7rUQY&xPDb`MM#D*SI*g3%e*@3nfFT9pq-Yo5~N+!*-SR+4!6wXU;Q>$^vK;?Lei>
zuc;ZQ@+^W*Gkxw5&f~IvLaWS)i;TQO`-*gX7@0*%kEwV{Aq*jDC%^?=%3QRKTds`Y
ziqlR9f#?7fy7^hcPKvs?!YJjCELYWn*!Z+uYzw1#(1-bh=9PmXTb*<vgp_@Z#f*O>
zMg;3vf3Zl(;6(4htv@Q*XrLFX45&Z=OWer9u<1#le%STm3FX!(F;Pxs3UPccNvU*T
zaf%xV<ZV7>rQg2LY^6YU7O#v!EWL(>oJcy<zm#2|ZS0F8jpotFvUrwf%w35bT+*yr
zu5;_9Ig|kLsHWm+*{UQAMd+`)q1qKe9PtiLTzaLIZM-^gIw>i4q^$sT->9*$A10A{
z8KCXz=BiYPNVE6|pnfu_;WUkhDy$U7VPwsQGWEJjmJ(RR(yTNLiGs!2PVJ_6epV$?
zfF`(&R`E)$81$j?41K`Er%XKcE+r?v!WS}y^hNZ@KZKTCAGv5|U=TJmL(ShQPJyvQ
zvvMJT(-_7C9gEX+5NmEDAS08=DIU<EmNO;7_@c)P;4vSE3PoOFC@P>x(v=Qh&Qt4I
z=hN~kwRugaWq19cN>&nEwnR`1)wOMmP+CJ{F^cf~Hu0l0$?>2h*vtp5zydC~C3UZ7
zDL3lYI0{r}D2fEw2#FSzagJDEl+Mda>T9g1no08t2GOQN6p0+%bi<$ufN&zm&0*g&
z-cYz@>K#*Ak3pdYAkub+uK^705@YB@k;<+BZENraYHv74Mbl~6L6p__ygI6{_6Si9
zi};Fk>`BK$xuBDS1m=!2Kjb|%%tWy|ft1*h1(e~--8tJwo<!JBs<EL$6#az7{tms$
zgs)pFz48M(R7MADZ_`PW_J5?6dK-j)>pmpqoGg8ahDrEeLt5X`IQ;)Dol+ps0XRT;
zz;___fbYMK4Kf}e`fq(hbVGCM|CX>4F+?|%?*ExSwaoub`(MkfyoP9pt||Y&4Sh7v
zp&0*BBwU8@L+HPaAHojN4P8?_v_97I-TciIVWU3o0jR<qgq`Vi+HPo=RbuS~>b<Jt
zTXIh8CagHn6glbWpqZ|Y4ZD?jf0yfXGQNO*mbRep(U*9Fw)Gmr?Di~)B4?;X4P}W3
zsCBN$4$7yjFrFnAVYFM&PuI~r4eRhFvDd2rO}x+IXum;kNC-%*n^QY@-IO%9QkkyP
zEi!C7cF{;@lK}=(A1A$1kXHRz84Qi?f#zmbp7QirRZhjri7(dFGsb+^)45G(pCmSN
zJ)w2=G&lq%Ws;nP!fmEk8or{eA|5J;+QDL$WVpUJgOe#GYn<Gn0&AsjXAJb3+Dq&v
zu%o}Fxr4_#JsMpU_POwY&oFwq7(2;GD}4jbm3<?V1sm(w!7Uis*0+{SpN$t3NT+)i
z*&<~*6FDFvgEVF)7o=p}I>%c(;||9HM$}*}_md1dZ8dQ(Jw_N?TqxgbcTt@F>tr9(
zeKlA?3Oc>scBCw@OCXQ3nd>NDmjSccVPP^zOhF=tuJj>Iai)VPsdZl5_(%qmSo^v|
zk*B>EYB)wk$#z6F#WmYmf+*0_#%)?CJ;oF|s4v*m!~;|$kLFQ9Umw;(kz7x2U37+_
zsG*#TeGBE=6(cMxDc`IU*VC`h3}Ap29q59|IXkAe*ECbUXznTSh`pj%L<%Z*tA&(4
zI;o)=$w)722c&(Hhii|TO>S)<mCDRJHO5jq=vk-qP-G^`pUgvmyRkzO^Nhe!zElDR
zxOVol7BCrX+ofaB>m4)wq2qOL2_sLgAU%@j5sj#2T|ebZNm$8();`~rU0jsNVh8b#
z63aF;N5z3Ys8>><>HAep4u!y$b;6b|?37sF=XDTg+R;g!&~1N~p)Ds}ox|eZJOL^I
zpzXJddvWKra{T}B|1}HfnarEH7gxy9_<3~=Rf~==AZV&g^*Y26il~WBc13s_og`)Y
zXeMh`+d6S{P&ySedb?ogW`#7gKS1LY^8CC^%7p-q<Cjv{NIO*<wePxyyhFE2Tp`8*
z+LS{`MGhj?acQok)CCBaG}9TRB$^lbS|ub&WVt$ilHOO9)$3?HqMxAWFdn}Si&Ft#
zxmvx_^gI%0bL18vj(r#T_aJQu)60fy<fD>$Vxd8+MvibVK8!&~WonNWi#0`jFwj0$
zDK!Gni&GB}>kwdK?_gsz3cV~o2Pfr~T1*EE%}xO-kSQyVH^$-gh5}J8oXPx;AEaC~
zb*48R15{8K$cW2E*vud^@6_!8X`2K4m;tjwqU8EaH-N8Pb48Yj87P(51mrB$4bvZx
zFYGL`;23HwOaeG$3pcOIo(klKv>^zM=c0%5Rq9l;6t7(E5UC*m=rIMIoAVD-rl*l@
zVd9QYaYjn&vG^I1b&pBn2uQ0|k0EJz%MmDrh;(3c`Yvi6!eOmbdJbXYz};3#!B)Z0
zgLC`>djSI|F%WwkWx?yQG*K<&P6wfYR!$XQ*wKJXgGQ{x9)6k~w3cygsPcVX*PwMX
z6tz;5c!vXM`&}B&+%h7y3`3O(m9l_snRRbYLY6e&n9&uH+{q;=W3x)-jT>3IwE{=>
z@a8s^@ercmgK?-=NI)P91I_hz)h4Y7ArWeO#9}OGEXqhn$i`ULiu?u56*i6wY|37*
z024Xuh=`+zeDLU3t74r$se#hH&yEO!&XTe<<cwHiZeue<R8po?JB6gmO(X!F4`DhV
zYw@{YZ&5V}DkkbhHjl@2F_NN}`oD`@bwwgw#63*xQBIE@I^?5=AYT=#owgdqY%WM`
z?m>|o0zwHiIK*gX$`v!w<HarHp!sXqX?=)@Z?j}XeUhm#%!Tr$XyY<BctdTMF<5yT
zGe8n-EKVJfX`Wl=NkUqtW!6YLZ&&NhH6o4G=uD7xu%v!?cW|-l56mcSy24trz%Cjc
zN32VTv>;h@kRsZZv6L<J+tsl&Q-=UVnGzFDCaBgz7^yiD%7@W_KfMd}RD(hxG<Q#$
z!l70iNt;^gAa2%pm<Vm#W@T3*dGt=fa^Z~*=x@CfI!j)#MG_MDm`g@w<zK%=YIu^O
zQB-;FTg3M13Ih1Jo^McD%DokHwlL)6BC852gQ%W5K%!(W>AG@_9Ih3|G#^VC_<1Qs
zR^<=9S+nWK8{XNhvZ{<9Yc&Pd4Ae@BF%B!`TJ&`^6qyx*FtOUXOD{aBzG1E2lUC36
zy~k>wz*L78ky3DRf);{!`yrG1;Dp>2tS&og4(UHRSi%(;&NX(G047k<A@Fzx9pufC
zdjAF}G6jw3;A;7$0DFax7K_*r@`xn2Rw8VmGOiNrBABA^_!Oy~d4N==phb#+7Mg&r
zbSZ;s*ZnXWA$%od#TH%gA25@x2npJUC~TAFsjdwud_H(m$EKG)J*QB~GsT1(mf*E6
z#RONUI)SB?SJQrUf28fPut-76c0UCAN(}Xoil{BUW{8#w2ad^6Fl1_C%?3y<6cG>5
zv7j@8hA1mhsu4w%#s{L{3~{#PT(LFJorfTewOm>%s5Bc^;L@-oA72S2T`<skOQr*`
zvz~1A=0YJTru7~MDOVa(h}rLuES4@fM>GQ+=v_r5T1QTw0~UzipT;!MM#zL;;2oHf
zBbMmG`8B^vrs))d7+XO^-1;C&osvNA!bMXCE2@ScEncTFK1_r{9$D2-yAtHnvik{3
zRu#rV#}fFYR-zpbG6E4z3WZe0)E`_|)(g~rh$Ns>95Px&t&}Xds4`EofygRT`qQAj
zI@+1~5U1H!2fSwK2`SWN)2qtiQg0xK1OS(Ml#vf8WJ;M3wkgJ?m;J6I&r~lG(+lb|
zO=Y7$g<gK1pN63<w&NhTm7WxVn}U-enTFb-QVr!#EMk#RCF0^WT<L$*oAwu$Zke1s
zS52#lq1Ajj5RWG$8&WQQpv+Fq<D`-;hIFJ&Qz)(ahfJ?rG)#@5Q}qF#;%J;{Sv#UN
zH>=qy3VJTFt=9;EFhfji^$7$w*Dmnq34(?+nZ~Oxq;-tN8h}a*7@gt}PUD9Pg{cGd
z{jrTL9tEoo_fiU}T<VLf)Fn2okf;8Xoz*}eFU!!6m{F-6Q+zN)BI^MlL$4vV9eG;3
zpm-04BE5&)@zc}SDq1`cx+IU6DmlbwXpYVpPXx;YHdKxvn<fS-4U$Y!aOow|3wwPl
zoP3JaG^&4iq7wZ$MW(K1VEH-qgtOJDF$x+?A<a=a@>BDuwJg614C>XXqd>b-x*!Nt
zF*6kyP&O%>fLC7oA=uugx$Z}5dbM!iV-M6cY*h9^)Ids%Lf~hES5v6Zsog%3Psl|_
z3B*&pO5^wq0o6^t#^DTs!_z(#5ZG$Q)GyDajp5dE4Y)L|hAKS0&W|)7bxBo`xH9}y
z=!nxiJri5fRqCC_DLAag{L&$+Ca#QC4zI5;!>gg-YUSat(&we$>ssDliMBxsr3)!r
z@VHQjp<^aw`2jY#Ll^3{lR}CLaWP|qSd};cf*k-m<i*TZVzC~COG#Xa)Be;3pJt7(
z^57Vr3dkBtC<I7a2|Dz%;Pj`U#LlC&dJx5{Q=yIUcz%IlKvMy{=Z$kpVdW54p$~DI
zJa8dWlmbxm*vgd)W#}b86l;87Z7Zom_DY1u;<WSg&>kopMThQ9`(cL&s-V}rpbJ3$
zLD&$$yqebWXSwhLuv9ox+dVr3D<ueBtYN24YPOJB@WxW*LaauLQ(Oqfl{A{;0U^`$
zDFLn}vci{8kVNS#9a9J+|4^Pvo6~q86$4M;6;P=Y?jN|<A0o(j#Rn%Mhj<h`qM|5U
z(gwVGts(-lf(mkg3vzJ<W~jpy%Bnt^FV-*WB?J^@2?3#niS(o)b<>^|4{WucsAwVH
zR&rIMkAOZu*YmP~E(h=*WII6NG^{cxFxvK|zSLEj!w9SdzZzYMA_W5$t3C`MHsI3l
zU*bin$nKw5rQ-_~<Rf6Eu1(d}Y;6q=vHJ<qTjro#NUP&@+H_4;%K>fkh=dQnQzl-A
z2UROYkT(gO2BFtL@N-ouSS<I3$1{#zXMdg|KBX}s4WvV9hDtuP5evRI?H{CFdo3V1
zfy!wx6$6W<3WeSxSYE?}X+Bn``sk*cF{CVBlW{jj-hjF;*QeOJpi=D9&WI*vMU5rC
zUEMVIKtf2D;rD|lOp#Uk-Tmk^C#rzPLmx6MYjj2(7^@RF>Y3X=y;%uh3lyyIw;?`}
zR;sR&2Z+-PJx1chrU7+%kfR1&to|$&S<_;TRCII}h*b(*Ou{V?0Ox{Ww0Wj0B=<NW
zo+wk&0HhWNYA(tw=Bgw{e|W(=yp?W)Ys7jp0$215ISXB=>3}vB9=Aok&;`g6ut|&e
z8qz!z;H?uhSSv(Qou*~FlzLLUx&}l#=Zi_j_!tOC=)-@UDp_Hqtm-kR#p6h<W{M(9
zBE10(P-5B!SKWsSRQj~EtTeSk?7}5=4%F@BfgK{FA4)Z&^iul-7gDZ)^GA|aygDX_
z+n<8c>e}Z4s0bAh_#GaILlqwCQ$cwV%S62bsgOgmf^75^RFDEiZA!_7979}6;1sW&
zUd6+kEESXH8$2qZW~WZ@SK@Mtv(lz2B4-6$u$$8Ha~1luP(8>Y!d#fq*Ne3_m7`Lf
z`ebs&7%6pHh&COoNuS;`TJ@zx$tC4E#5r8aw@_($+Qn;yfo;Ov8kb1&91=|`_14J6
zhbvQ66R1pqnCS$0w45tISVeZm;Rdk#)gow_&}v^uv$Gm&HP6bV+-biM_XqM2sRSyB
z-k;FXM)ZGpu>~x_dyUt2x*tNT^aS;>yc#F6IDjQ>@Zh-pDh(-FX$w)VOGVocHua$q
zzCar~E?wjVEd7l{>hr-3;#ds__y{KxqTn1_7$pL|QzGh;O&>Q9_Eu4q{PCO6kK>6#
zxhQd135B9URJp2TU0xcIQ*X3V*4(vQq+?G^sBtPkbR0Xx7YH>d-f0>Z`YU6!mgA`N
z6$faBT=cgeG!Zvq`#TS9V>)W4Gxk8{iAOC3jP5i(g(1PM4dEg5M<R#xN>Ra86kU!z
zfU*^;$|Z<5<v?`sIdb(wIP0LXL!rvG!o_LjQc#<qOA4mwZSa+Y_Fnvcn;+2J=z?rW
z?Sk1wse&}YSMkF);GD#eiImhysoZ{_;s9Nt4ZwJ->AHf7Nl%Kz4Ifh2AHvff<O*aO
z{n04d^*a%#?W-|VEg#}_5gyPpx3W|_R>zLe5=v!hc^&aO?G=&|?@0o38VAH(G?)V6
zl62%FUOR;x1*;L-D@7B%-d`_3c9p}036TvOJzZp3>88QgQ7y^0H47VKwFj`;9$hsK
z5+aP{OJ-u>lhy4iuqMJI3t;(h8Gh1p&DmPx3)*$Sr&}|OY;SQ`(1aSB^ew^&4t#8y
zog>+`xsCL15skha$EH=vqdX}U+QZy>9kWWWor&>ueT~v9j=w&CClrmLR>!@_7s0Y?
zka5Y%YGQa-bENO}1Q6C{y~anoVoxjUGjpNSR@Ol@D)pPFj_)_eu|qcPINLdo%-I5-
zyjsq#Y>*vUMdwDQFPtI~j}+o?Y6I@N7)1MQ)Et0Z)~D?ie-Y+sS-$dm=m>ese3y>f
z2@ei10md}!-^J_9(Q1V%TNe-0T9!CI)mn(?Bf3ysIVUxBjm_0OY^kb|MTG6>9L0w0
zQ1f8UQ6oG?k~vi}s9kq7LJBoh0LrjjpN<?vCq*Ce^uS=k2D&6eb<0Q{`tr0)ycG`)
z`$7XlFTw-$EPm=tw#qVN^Wx#%Zn`7tq_5A`mfdJ)$R(C)FKzU>Per7PtxJqYGQ&iw
zOstKLX>h7YSUVbwd0LR|D`S1%hA3-CAgESptq9m`9-Z8)JZAN*dbjY*+C`1o1^RJM
zlSEVD@95ztXV=PaW8Dkgmx-%o?vdd8cpBrlkAYIpT(~mkdYXq)RDo8wM>eioeXU`2
zE6WC%EaF7{x6(G?=3F-8bc)JY;RmR4%*#lHoc!l<naCB5JUsp&J%jqpv#{bFwc9zz
zdg!#~;Y+JWn#JQr*A9-JI^yMr3Uy5jvSUjpjH=DAxv6U2wWF%0A2r()&&}4>K6h~P
z{7s|dEsH)kqImHvGylgo#Z`UT#;udj8#(>i*|oV}-PBn3RHkv#hSrhOC(q7It$Dtx
z@Z+^3j_Ui|@F{nEu4!r8Nu%xh?^lgjdyq`tFkDI<$5)kR{n+@M#%EssPWIr96Tcv(
z{%7OPJ2zxEUwe3V;>9OqHa5?$y?yQ4gI<4lL-wJwvLk+cai;328?LQ>?WVr$lOI1a
zv*o;a*i+9{jkxLhzPf)LKYZ8&!;{Rw&fd7{r&Z!^92w3SUr8?$|I*h!e)WyX%1@mx
zD?gR5TKUj9BR;(1yqf2Ke(_n){e1jsTdw{~&9VD_60O=eCRuUM$Lij{;!DGiJ?!|^
zt9G9ot$6o~nHjJAGPCkGKOOb>edjf9yl?iXNw-|lKkdVRJ?z-?&uyIXyW>Z9?|QHP
z(EI-`o^jH}!;d}btb?X~_;$m~yU!ba>_5C+m^9*<LUR8HRj)pKe!T1FKaZFG{B!Z%
z-4~30^_y?I+6Pv}Gmcskz5DFE%<CU~clcKy`b*uUhkhHs`ptdr6E9tpeP!Q+@iY5+
zs$T!#mo@kA`$u{Ek!iB`uBy6ezj|ocKYlo-=HtIOcGR|CjA(d#-;?4V`MdC)#2-u)
zx#d5ONj|*#$YkZg3(d+;9#XsVp;Lx^c*XGA=YKZ4X6IjO4teM56OzMTe8#N0CmXG}
zFN)s3qNaA*%kyeh?Y?@%p4}(LGd}p9to;4|%x**1dp5e<jF-->nfBMORvr7haWdok
znP~YNuVts-e?xrONte|e_Tzu48U5u;<88ZJtB<|q_PF+zYvQ{5KNY|F?5t?l&rgf~
z{EKU%y}PqjOP>5eH0gmUa{2=k;&-22ntgrWb<w>K-I~4kp*!kMeDb~ck^g;7a>%|1
zt54kfm8xg<U7vmO&96lJ{%zWb74KD5PkZU1_#gixl6zm-?6>`EZ?tXS%`}KFik>^Y
z<6Pc+@L{veTy{z_bLk=Gq;H>GbJByOWM1*h$-Ifv57}|Y!loB`KFfQ*kI7b5O_Uu|
z$0s|c9V5q%7!@5mX@0We+{<Le-+wYY^`+w*XTJ1_+~x_HQJW_m9!>jQMy7rLe~dO8
zPaSP0pEtVhf>Yw+o0rGOzHw9CvA=&UdA|5!^n7t^;|#Zb^jP;FRXcWHFYoL=LHx}p
zX64}1;@%&g9^LlCVPg7E&6@u4+1^hz$Wx#CO7-do_YI$P^dI6ScVC~qWaF(h4}RwB
zbq~#aI<A}7AYYq3&P@B)QPH$#o3pCh<{ET+_3vtKdG{!E%ha57{RPr~!;$ngUoi6~
z%7_<wRy6Lo;}gluW#`0I@p;jXX%|F0rZy+@lG(M>Mnutyzb_77aqh%;Le=<q>I>&q
zZ!Vl6n<rc)$4>fOGVOQgSJm>FklKyS@yr)YRow-T$YF2XkQ}!C_GI+;XVu<Rd{xG}
z0huxQpcLOcSa$4g&6W=yC*^~Wj&3UcG;4l%JbE1+<@;OF`>gn>PtD4%KKk47JrDNQ
z<bRlpF1foo`^nE-A00ijzqa>N&&PFh$3@d#u2<cv{;;ur_&jdJZ+Z8IX#K0V$=8l=
zU|cDVP0a7ZliW9~NcZ=rHO*hlCdZYh)kSm1jE*_~AGfsE+m^0+J1~}ACykBz+%A6l
zlbOQPg{+H@j`O}d%G=VgVq9pP*w@~4_lWt~-yb%nrZjbC)jhrKBEDo6_))bNNFkXW
zPnK)0Ey&Z?o|;^8?Wv|GbCP_u=Je{ZC)H+i?R7O@>l-nue9hMyH$>YTedbIloP1;)
z|Fowrcf;Jerh&Pm8gE=WdhL-H#eJVCRux9w7yH_Bb{(5R&K&9Dxjm(Z$KI#k88ayH
zX@jxv{Ikw!8yS4)kR=NGJw2kSYjJ6Wtc<Go_)Ak^ExR6DWE5j^y<NlW7NmHvMc#PO
zN#W@xaW*k|9}UaLaa5FKWKCa7QZpj1S$tSFa=egXbuUKad$9|ci=4n2nJDh4X{~a@
zT~!o4do5E2UKsw>q!6t?sXdcx=X(y<*v1Wg<=lqoXL{${U|X-3_`9>~II<Zx4b(O^
zu9f<=lO@x4q>BoT17@JM1s!bsQhk!0+mk!^aGGFT<Fhi~M}3{_lFGL*<S?$v;t_i0
zHj!?|{uX{Y-s92T5XTqcFJ%}z*#&T>k-}o+?H0@aT6RVlu8h+i8V}<Ws%$)+8`R}B
z&MyZyop^hY_4?*o8(C>)ytJ}G7*BmJV|~PVQ?mBU!M89Ouqe#wV7?sX<qr&q+l}-L
zFyUCo2-z*naTtwtW8d^DiEQk39xIHsd`n2`7c*I!j@X=IWfmaOd=chUdZzZlr|^dN
zv~-itV)RKo<GCV{oiR4}i)x1v=s`HgPw|V{_tP<siBT-<7z{dwc+VV{kFH2(HMTVo
zKhhFb-j?Kc77lu}kOrN?8dCv15RrHzDo0o3kdng;Cbngcw%V_xwCE7*Pe;OmA4>{&
z@!P@g9e$*7xpAC9BCXRrSi~9t-4}aVo|!mJNm`f`cM)Ggv=S*Ca;0Z(MVj%kJ6IN5
z(#N_lDnQ%;ts{*%5^(Kju7cjWm&4TwYZef4Cu}9+A8`e;V(fH&?lqZst1C<DK^!Z#
zL3}}jOsTxqj?^~nhVsGhh{_8)jAFUQk^r@W9R~tCmid_>DNKzeo%K4k17rZ@ldu=U
zRmm-DH9R13MzBQy=u>#BE4^C17)2+V8aWcm3cZA?gQs5*SEKX%()hpwLM7ris92Qd
zr=a^Fv@n^ITlJ-CD@JJqMMS*%Y_P7{OaIl9V3jRk^+%luS%eUNrPBD1&=A@WuuRug
zsVjgVVr#hzgIgsP-XR|e6iReqUdoyvfNCXbg9@Flu&dXnI#|3ZC{2h_J9%md7nM<e
z3h=k;gr7tnUti>PbxRWjCym#T-m-_3P2Le@#04x)OP%ttA&5`ktyGci*uN;!suSR}
zZ~dxs{lll+E!{_jGq=Bg;AfYtdFYJCwtexa8^3(%9n0oFaO#q65AXcewktk<<3*R=
zar&MIPMx&%rW4;T{Ex@JxtH*ZZ+&sn!)s5xYw{KU{>sWrA30sWqxbMjC*D6*zq9wP
zznt;nou@qc@Xs%OsPL<QpL@blKi~PmopYYped>}&e)G%w=Uw^0ji<l+@SMB%eesBg
zHazq8*(Yqh@eA*M=Zq&G{>74;-#qcRS6pz<uR7P<_~MbfzjVZ?H=p^pdH?&K=P$YG
z#?Fg3oc!3ReQ)3K#UI{#>LoYb+&O;3$#<Xi=2efJ@d~o7`BmrrgkQS&-bc=P<?VSN
z7e0odXHb9eS<c+vwd~`C1{?jpFK=Wxea9!Frb9Q`+M=<13BEm-zq~yvR!OZbWa-J;
zY1QquRqgSxVj;^w#69!8)+Fv5o|)#e8Qa&&Q*&2S`?#%1PAX7fEPuy6k+tNwJ*t0a
zFkA2Xs%z}E?YY{VYZwrlv(<OTW%9kX?YQA(cX(X#6B@sNP1V82b7S2zxKw^07pN22
z*kl`}rGAPj_e^N)8yRP>IV%?*wWuo|C}-n=h?53<MYP~t?JXJZv}ZNeMI(71RZPDz
z$UQNj`ffRxJ%LlEYI_)huw#vTs{aHbNu||PqO|G)dQk@L8t@;jHH!G}A+!cfP+`5F
zGFG1pK^y$RTfu}1o+AE}t2X`5;8TQi@xpMn@1nOV2pyg2>~dLW607}TD|#eN^sn3&
zmW++HUzD*lV9E?f$2d=U7ZBIsNJ;E(T+C(!ljI4quazC8M!gIk5W!s)D<}0O_D+f~
zhi_ci4V;Z}WKt>^h7Jh78!6A*>!is+pEJZ+Ls}!srjNT^ad^~Nu(P}{#5>MpOE!GU
z3J%d%EK4PW`ubrH5$}cwhShub#?V2)UZQN4vBxr$T2@s|Zkg^c&38d*nJeYUf-bau
zJS$FR<LM+~4iKVk*Z>|kb?f;Q7KuG_(Ah?e0gcE-=DJhOnV11W8HjPFm#3F5E_hF`
zV;O{?8R%)(5v2dA9M5$LhjkaCIV3co`l2ga$znMy7k4cP@w{ZkiuBUyvK(sp@`;|y
z9Qm(E+l-bqQJga+33ibMQM+zsNddc|4;&q_453D|GrD%-Ran455xf!8DgBI1F1#Kx
zEwezO#}=p=Qs1JY1zWajgsCG5Q$^z<US?ur1G7lVec0G11ej&wNX*;?KhXmk1iWL0
z6>=6h^r{aD!s161S&r1yC{+x)g=>~;Wk`(aDhL_Enziph2(Cf9e3yDi)&&Khe~zvA
zDSi0s%@p$J(KSm2`V5tx^iG4ZZjn_`g)xriV6<FgeiX@M0YK3Wg+%!QMNss8gu{0l
zn2LH&HS3|SSgN&gKC;w(GEim;<e8S8Q0i2>c%(dW5O{>J5e{{bYSfUkCXj2{QdxC6
zq5HSf9Z4FNX415A)|d%zL5*Dqc7q|Wk$@mP!zv<dq#qO2tI&3#YU8S3WQruP>43Tl
z*~*qRE6Bj}(mb*x*4xxl$fBhb_Gfvm$^ju0sUYx4$~}RTDA>e>tA`b$tIn!OrQN}T
zZPFYx<h_PS$OlH8c%rS)P%sRFc`h1m=0fAghe*wV5xwY$Kpuf=U&yzf@Su)Lgwg87
zJACL>qh$?$jZ)}U$HyLNRUpqF5$c`g^j5>+(;AtxS?yiu8N!_elxjF+p-oGx7JJ49
zw%Yo6r}=!GHmHa|S)E9GBCPc5d^!Ej-uW3QLjj6u^Xbf%Wn@RZ33XL-C+ilis%%j$
zA(bs6UAwY$Lyea@SH~1YKaZ7W#YGc@A6<p3Cm$(LpU~4$1`!)N8&1+jAk>;VImz}Q
zn6BFzvMGf6owP2jEXMXK({Lvv76HVEFdabPFRq_d4U!=vO>gugrz{iWm~PEL^vi>s
zwX@zj!d>c+o27@Vw_XGEHt;HWIx<ZbP!c_jm;U?&@}a|LKJLX_6yj)2aeVr?AV2M*
zM%-AnSZ@^CQbKDBJW^idqYNmam}=m-ji{1(qFCw|Sc-8xTJV}NR0AHlD6Fp_lVWV5
zEkb+k6g*7<1eu2K@Su&fb*RYfKacd<NIhr`w0b5a%;&B0>P*vP`jC^hb7X=w67_4%
z)<<7MotKiRq#`($Ki8WEc#$VfK?@U;?b1^5u?`^0%!X%}oN$N;Vu(R%W-GB(1Z_VF
z)h4c}1tQLpIqwHD9-IQh3oMBk2=UQ`d>qd0YaHkyun1%cD0TQGcUe6uqnB0(DXYX9
z*`!^iCocs}?+T#_kv^w7Axf+g1lDa90u@@_q#@5)Sg*NgV<k0ofrW}M6GbdG^rjyV
zM>y#%=7d;%P>_@Bi-9BEsHT#7bwGz>Em8_0ZM6XPl$IwB-hpwdlb!B`0Wt&%;PHhv
zURI^@yxK<x64s%#ptO9iU69HqNzp`u3_zMf59m>E6XW1cm3|3R=nDqC@I)e4EWy&9
z6w@^W&M}%Wa^&$6ugM*9C0fQV;CN*gis;BV-iwtHja{Y-!_~PSl@F{d+$goYA}nSM
zEGPp;D%YG(WG?Z1ct|G>$rvv|fBJp47{pPYFs5?04SHk?MjE7fH;4<3aIzGvm@c1_
zamX8+Yjp_)@cBAN*`lDnUaBbN&=)!_L&_y*+tWc4Au{b8k@Z-hBj)=+J(^ac<%pC`
zs(Sf^WfxsN$s!pR$-+<*kiFJ7Kd5^kIv6;#0rI?wgos|NQt)}q9imGcI;B*=(xHsU
zdXtHrH;4lm+3+-%C>&1_6AYd9+tTkjsuCr>S_`HNkwu<!d}*nchiZ`%>+7U_Fs(Mz
zJdYMxJN#OxUs2SBy_074dbF9^mfiv;=;Fsy?Z8FVrzNtqF_r!ti(2hx^%W?Ii|SC8
zmnbsSTpq>8ftREmJOjdHjO-)1;Fo!-Aw-m*R$H&54DWQHk;EmaqgEKkM2(MY-D$Bb
zyj8aaxLmEbrnjr0O}<vy<_%|QN|yA7<B5GFpzyUky{AMdLKs>HV`q&<;-wK;>8@|V
zYKdz+l0LH7EX70ULN_o4@9BpvY3X9MBs^Yys7ehsx+SS`rja$FA|c;!(>~ogU17*k
z`=n_CI3bVfGI?|M$dkTjI8zCevB*e_3~2ci8_#V{OM|ce)<8!KsL?eT(OD?+*?v}s
z;wIPLLEawb<NHj5+PhVgb01dXn}`eXWFtc?kkAX$E8}s2qz0VT2u8ahFj~JtppN>d
zUJr_7G|M3xy=K({s&reU8aaTiTyx^o*M77~iC_RL#iep+WUN(^+Rhz{)i8ieV3jqN
z#0cZP;W$}rol5C7MkAcnYX#Ehuo|F3!w)fyKah*6s)?OwWuZG(N5KY{>SL{@0SbWy
z)NvZ6u1broQ=oY9C<^fE7{@g+d>>K}H)L+ZtXgC+P*jM~%=Zz$ANJ#!X`_-SqM(sF
zAp#Ic%Wm1v)D(Kl5Gk4tzzxk6si6{qa~4N>5z@LKo|1>IO7Whb6KPYmYb}A4hiYHn
zmCln)P@ZvH^^UFh?cBC8kZW*qNTCj3tO<hQ)w9(Q9Dt~Y^p^Z$P9z(B5^kV@v#-$f
zaK(<zY0z@f41KqzqFaM9^lND}Sz8%&X~0Lk*MfNdxnWZ$j~wZ@+<LSX4+vw0!~=#`
zYiM+&4kV=@kp`%T>V!9;6KjK1`Vt|Fd25`;=`<9HVgiA}(#J$(>0yNH!i5)W01gg;
z2E1|@n)Tw-w4q0Z)#tBLf0{lhtHHKF5Xx2p%bay3aB2+8pI4$36a}VE^YdyEWKbJ0
zyl7De{nRSj$tlnsK;E7ddo>W!XcmDDQ&;0aGi{TojE97d9}DxO!3RX}f?h&Bbr!C1
zB?hDo7RAGK(&;4*w82X#y=zG~ba=uD%nT&WMA{=(udU(~LNV&ff+JwH`++3`W{}is
zq0LJDxYDl`usKyiXKn?8j-S42Pzymn&S2>)0(cwxD(4Bsfoo_}tjdINj_n=+N<<=s
z9V#10t<w}hEqpzeXqC9TAKO`QF3q!I%5dgq`3Wf=H-HTl#HpVFC|uKYR`TNX&W)hv
zK$Npd6&D21KGHC-XxGfYQDgu$9W5x3e*~pQYN7mz9!RCJPNS{3aMg){LO!_41OpgG
zC{+U^C)p0oC5;fDCax3+NK0~K+6AKhKtezphv8}?+|~n<hU!=fM)DFlLFT@YAaxK@
z^Uyu2EdR6(#lV9%o*9M>FdiC-aT(G1i$c*P45&~!jSIKn@;5*f*pNmg2%t)ln14+M
zC;lxSpN7M92_yjXFeW`v#+ru*RHSL5@K;H;zd*bakYNS#VUnlhsTF%el;*0?7P1Tu
zf>|X~z9p9ut5jA|j@~g83SP>8dME?TZX~a@rJg#XWVHRTwxD^XvJYJX3oWok>H|_c
zC{dTiu?}VyeiaBGJ%pEo(DJ91K>HB|eWg$ZT)0||(7V$#g5ineF*fTZ-l{60Bci<H
z#9L6tIlWt8YKBE4oS11hfPAP=g4(<Wl@^t7O(kn$S=*voG2;_){M1}Sa>pcRAGFf4
zpjsKyXfH909Ca!+OQeaYUi?%v@qE_73rw7b0H&()GWH3CeAFNyB{GnNZil2w{t>7w
z(OHj7PD-jTVATPf4Hi?Jju!kY2W1lS*ZGX@-={lPTu4VlXX}v$O6tH+d*7CjmL4G5
z-`1^z2dzLmp5O~Pm*|i(BA$efDL@$H^d8ZIASZx1TIfkNoJyg+fN>f&N}=_`@=IHj
zQN1LxAur|RE0Y{vOC;9Px5u7S>*NqQA>k0qP_ICs8xV4)1YsJI6At1M$-hDfhW^AV
zZe}ou;Wa{)rGP*bWNQ6Ll46Puu6FcAioe22%krLQa9oHbM?fbqS`t3=33#{zaNO*H
zwQ0J<1xeCIBBm8{;0H&o#<t2N$gKQoZDsC@znver5)>Y<AU~#4?pA{-1nW5M^etps
z3-R*P=~AvHm7pt)1rHSV_pr>Of*dCBw;@(*rb5N$UG$4q<$}EjtHKV78pT=74hK-I
zQc($Toiqn*#c?7h=xdFU9>6BC3vJ&gkq&%mgy$Mef}3XT6p`vps|AczH*I%Ly{Vw&
zOs<}=Yr$tKA`w=J6sUm(y&`}{vNMvKn$RvUdIdDXFIFB32$y<PUfU>bX(*L3^~01D
zGy+Sr((1P#PzOH>A_|pPbygvV1cK68r<EHG)nXc1Icj5^lU^584@`_Fpr9()*yE<)
zW7C39b4^)r^XN37$!JNKhX~`yD>QO~aIN=bWQkxLGW;C?OBDn%h+W@4gjQ4-zVsM+
z5Z{m*(1=RuxZtyqO}hh~8G}km5ZR|>Jky^7l5OItv`i7K^nz)vNP!}B6q-=$gw?AC
zLfKgx^sMk~bgr@_OSDrZ!=OrltStK)c~4@>fs5Kl!C5j-%UXi~cg)ahytdnP%1Ed+
zL`Fj?Ei`Q@7pP*=I8By<CHoMlC+xz%#Ye-{i^{LbQ*fjm@{5608X`v}iPA{gn9?lL
z>ZUifbUF%_UYs-sm@)6N+_4`3UXH9OLu%y?P~X~c0+kh?=+icUr-3@2DINjqb=wBH
zTgL@pgM~&`Sq<=xG#W7DoQ8VEi48jCH7bRI&aMlp=n&Y7M+Fa=yHr6%d!HI5_{l~y
z?Na&rO%R>v{lq<e8VKN273D@#lAJ>h{ZGHYc67J;f{t8WCIqa7H}v|ic1(3uDUk}=
z{sYU;bYDu=u7pDXg|i_*k)<9Nf~gA!wKaiKz`|2A(yX;iJy(DR!{Z8x@~#8n9kvAN
zQ~=Q~Q^PO;9R2_-9qQGq;}F&w?aE<F?S_N;y(!U}E9zRVMhPHy;UZ<~2qEp+ahs6~
ze+rJ)C2e_R4kCzAv@_iEBZlgOu%UOgY9;I1LcA)aU?Gp3Y{wUh5MCrvSyE4PI_Yv6
zuMsvyBLJ;ahYE{PscE>P`Fnn(RmIYB9La#1=osiA3HH($SXnNVx%DVnq&y7$tmcq{
z@(Kd^fU8$|fF9@6g4%8>wALveQu<sGnBlgBo=qJxKu8r%LX6Thg{+Z2U~$v`K$Ua0
zLT$AmiD?d0gestGhv|JhMWRyKIm$UM<h)WiZFO1^6s$VD#?m#zh(L*8B(1nD;zMG*
zDVR1jO6V1QieXt)8IuwS$}(YQELlL%SmmciPCJ|6LgSR$gC-w!B(iCGr-2Hj7)wZ3
zGLr&I<TYwg$t3_SOQAE;!u0ATkq<%$0}YuI<M|Oy%mX__uDX<vhgZm*OA4CCF;+$@
zm6Mc(dR&P2?Qj5V;FV&AG!D^Wo@9v7ZqkFICI!7Je88v(J>ja3mJMAtg<y&30)rI+
z_Eu^}!pgkW{7CPdhN-_WbRJ(00?Wd=gq&a$?hELU9r=z=C%?)AS`+R>lnGHo^~+Zg
z*`lnqc!+RwRB+p?0W}jW39A5r-T_$culcS=+FC#c-5jEM%?OAieWa!m2XK9X1M>@G
z(+LLr6m;kZT0KsfNwNDMDYZaae5Ev@vP1)xq9-dv(gzY14EI)grsuIgYnUjqY}N&D
z0L!ETDC@Xmk@XD@U#*miI$~FOeeh;j*_TaqG*A|tlWHd!OvXf<si3xjU8OeqnKM;K
zcy+i^9$U}`n}VkEoh1(k*XD&6h-;FJKKBmmT<o#vGK)`$@{~+z1H02E3BBkjx4Nb(
zX>1g_j+4YrbWGuuyv@3#Q4Z}oSvosdzi0ZZM`8OHw~FKCA%?7TJZV9eL~hIES^gI4
z^|1Wn1-95V4tZi{U2G1$C*tD+^qh;T=2(lB`uR@urkcc+O;kcG+1@}pHtQBC@uWI2
zy;!<QT1#O;Pi9#km3?ETTla9Z<gr<QBG+v))Qh-A%8`wn>GvfbjF&UH*<y~s-p$d5
zsHGK~xFl|fHb}n2py941iQ2UeA*ibHJ&~iEl=iP$b4)2>kBHW}Y;C-O9AlGXSZ{D;
z2q>F-%F^~S*++dCro=sn&qy9Cr0Xo9th;iV*$8L+k2*u0(8@(;d_3=DB~J=uPL{QQ
zOJ7?&&N0`_wUwOXFqI5;w7R@$XScB0j{^5n(urro{6$*N-6ZFDdebh)x%O7E2JM}7
zgC?@|?EGM2QZktu<H=3tbax~?YHpi-QqhZbi;p{0rGF|Hm4yCV8|vbu%Puu6Q6DO&
zrWN@7-j}<m)4k3x@D-)MV9a(~;z*cOF^nv*wuz@dhQci+y;Gpc)%GW?mP*`|?{b+q
z8K0Ln<7^+MK;y#TR6crGbnL*8>bxYbra43AN$wx$ww$^3a_u4en~QlPvkL#q<QhsS
z*o*9O+=cbnf{>YSsSeV|R|H&s7*p{gf@h3SWzUPa$IYAVY_!(SJ$gE01ylPZ3f1D&
zI@5q@5Yg14jf<=_6eQ33s;O%CG8*-fq$;1|{l#I-Ysy%9l-x869}}Pdho&~!Hh#9A
z`8o6B%r0L)Lk4$mYVY3m@$<g4<V7hiIdRV1-G1~-)7Ficx%doIyy%S62dAxRT)KN8
zUU|_8ZPQnt(B__NSoF@6b%pO-G~ad?J51M}H51z3U0-<TqO01rESW!M{#9#cmUgb6
zym-PdJ7>-;%4LVWFk!)St0!FWa7Xm`cgoFEmpoU!VAXRYJ~new&DqD^-n_K)MbmuM
z3k}yzX>R$(!*`CKzT)$l3$J`J^ZM?|<4@sC&k>h)W+q+mj5&Ar<Kw=0^W*l>OKVK=
z;?An))@&Pp%Acz2dq-Z7x$5HDk!{aCT)677)kofY_~L^;eaw9ab-!@a<Y^y%@;F)f
zNu&DS`K-uy-ushm+INcU-n+NZz4y;{<=z+Ptlay|=--^Z&;6O-hpT?l`QfTR&Y!vG
zCpF9W{PD!a+s=4x`Qumhbgz1$dG4zBo4eoLIc4d)dp@yy?+1lf_r7@eU$5Hv>GzlK
zIcoW~SBmrZ?kk>l><f0xvB`uh&tE+L%4MD7pV+%Xp4j_p^yN$TOull-it$&Uy+^KI
z_J{lvSN?n9i7T(1y7}3+O5c9@t<pF4U6p@g-v{>7e|>iNg)cr^bK<^z`5F7(&VP2_
zG0`XZeX#Gt@%##ZeDcEP-|Rb4zVPJM+|^IcIC{?$OD6v5$xE_V{qfk3UG>LpO$}#$
ztW9>0YEym7ThRAcXSjDBIaj(rywNWG+0BLJk3Unra_@I%eR%d=^5LrY_<i@R4^RKo
zL1(W2W!uWVf9#lk--)vPtxqr7apsQr&u6|Lw><Zw!<X)PcglBedG7Cbz5Gn+uVXtW
zzkkM_&o1A4!{?@d`1-K3j!N=Z&KSsFx%;W=)1LoB_Mi8@+WgSo%O`xM^Ym!qvYo>|
zyX?CB)n~sb|9rw}Q=T}Z)js(08{-~(<Bh`~{MQTZEBns1|Ko#yh$jBWkA_{a@0tAR
z`~Gd*lRJ+#k3BKQ?0I{8{`GxN*+1_4g1KwoiRLp;PMUJgzKtzE{ASzu51#D&_?+vu
zRbBPNTjHf}%pS+r(%bc1%<0p)?H#d5T2@STEh|1FbAJD^{K{2dt$)AsPh;Nb{Lpp(
z!$oWf{jQyR_Ad{ed-l5FGgq#k-MysMHEp}BH2>u>vv<wCwR!&XrVAREZZ6GTy0f`^
z$?~e{rPYV~2c}Q<_pST%@)eIx{PK)i)A60vcKV-JOjw>@GU1^~-Gv(`FK>Bh`tk{9
zP54pWn8SY`o%0lBykmttRJ%kj{Onco%ge7ck6r$vWIld^Y53Uj*-xMJg~BnP|ARgE
z(o5v{bDH8~|9*z7`qJ6vkk7nq-hE%jU$!%!T)F;`+Id$$krz3yI($d(M<Rb+H~q-&
z=_ko$-P!CXM`S0=S)HBm;gajJ@3&nmOX~`5>74~Pchz;n=C1nj=jXrlY`pxIZ)BUc
zO>CWiOJoNdzg@Mf<%WYB7u_~)?xLqAv~=1`OGnMD{;%yiy#H&GpWl?vHH|fL!cDi?
z({Adu(~DEg{3Q+X6UCMZ|6H&W&iZ_A!k63pq|feJXwG>xZyu`6*@q@I<Q`qv6TR3y
z&eT^wXoek>Ge=zVFU`kX#OV5Wy>jlQ898=ggE{+4=i7#Jjx&dx^FPgL-$;5-ez93*
zpA(tUSLe(d^ki?2XLsoPIs1nf`Zl`W%f#JwS+y;n9Epf&IloOVu(fh)e^XMv<m8%C
zamoTWf60Q<<`>*$cm7fqUtY{DmibL3*?V@bVQZIZ?`k()C$|@0_)A>eyeYC5&5|jn
z*2YV|IkPH%=Q&j;FZLa+O&gQDbJKJ8j6Su?UOC?`Jaqo}6Aqi7i<Xb>%Fpp`Np5@F
zPp5RW-*)btcKLn2-fmoS^7_7$<h9L@M|po|BzJ6#<eGJH!}W(&tzEKV!eHm)w)57<
zhu7Y|Wq8xyeLHFzQOr)^Yitvi#v@g~d8~rumamrFF*k_&{+MdHt)9Kk^*Rn$ceNi9
zM+}?4u9cc{a&nTJe%Se?>E`^>bN$kC?RJ-3-o(vEu}MttnKrlfFouYB>8fu}cKk6~
zylF$6pE|OdFYsmLHAdW5r7D`g?x5D`I}Ym2wa?iY*EHlWNV27w#rT9n3v*9y>u4+;
z{lctf>sxQjEo$pMrLN7cn}1sFYcggX=b3N6zJu@Z?nJ-m(C;Lp4_*8I?hP|ItWec<
z>yL+-+qMr&CY>lvOLj#Ki`>Z3^-t&YOwaP`(69JZCO7#R!#<1AQnaI(jOeJ$OV&HW
zRYxo-Gjp?J+NEtG19hpj**8SioYXG)MdI2@%*mLDn#t7+Q(3Dcd5fYhWg@>cYi#>$
zQ(83JI;KO1+73R0H$2x~nB6MJWu3GiFQzn$H819mx3x+WGgLMpGhbsojWcXa&zx?S
zGA(l_=WT2_^T9a&a8=UQM;Q!M<?T(vW{_;I)mKStf%pRR%nj^1DG;BFq=jDq?j@K9
z>zSVy__3pwpiZuw>ex4kzB(7fPdXPn_S!Sk*Km7<hN~V$s4IZdhZ(HfOeC6lMA#%f
zz|~euSAn^T{+NlfgOhpfK}I;!%e)IbS38`k({Pc}=e@v63K>Rn=3j;5#4OGs(=1kE
zW<|30D@<@z<_z@E%ta4q9Tv78`~Xo*asuC&iOeE+i_)h*>tp?n-k$Yf;1Mwiqd-LZ
zo#FnY6CZZg*_#5aEe5gdRjdm3ioA-(?F|#r4kzNmea#70tkXLt<G>9;)S~GDJC{WI
z-oF;TnYJG3$ZC?th<M*<5ltyISI0b&36h4!g^8J^uIbEDpTAp`Ox38v#$MXkm!O)e
zYS!u9U3f6mPHtXW6&;gd9KNG>@-c)P`^clNIn7DSGff>-4t&X9`Pq<~0P$YAYrSB)
zt1&FE5p?|FhI)X<l97T>)90W;Qca~01y^&0lQOF%wdLxRM$_8BsH7-L)EW~(3{BvH
z{zLpB2tbmedWd)A;lr&i2~x0{M~k!(?JFoMizQoK2qB3gi^w=dlu|+Kh%g7;pTt?A
zy=eZ>pl3>$YO;$OB8U*0irz=0p}?$OgON`)=lK$GBt2k<ahgx0+>`-eX@4&Gf@5*>
z>eHu5O|c_AH2fSt3SI?Gx#7`@GG5F-f%w4#8g12)i{Ae2s^x$9)#<zU&g0C_q=#0%
zeb=0hw_d(v_rqsAx_jRwJ<~&Y?vi)+@}0daF8ujLSHCxB=Ua1U?EZ7-+f%>%!Oa(6
z{oWaTM{mWR?{wa^^vb(mIqRsKckbJ_?7}^JJMX&q%6ory+Kd}J_x<j<#~$8y$z3zA
zx_jP*dvEM~W!s!5o;+vCljC1`^USNZzS6mVFK2$Pp7hYg7rs63s(sI|+WPPr-+JVn
zB{yDr;cu@#<LzY^e*3+hAK!Mx>!YsbyLumdYwi(0eeXvXFFpB#QTwj`w^Lqxd)`r-
zZ(cI~>QnAM>(Z;=JB4rf9kKb9CF7@EcJJITfBKO#WJRQE7W53v4b9l&a%pPc+*)_R
zhB_(TNz6*DRWefYnGyC`GuACnq@DZu?oumV3KnmYk&CC=sJmr>DOqj_^R@LS>@Cf@
zU}1A+S6(8!%#63?(yT-8$<rek``ubQuI5l`CcnnBqh>$F9~n)OF_RX%noF#mIOX8H
zHQc7=C$-7e<+s^lCX=l_$3zV)M2>0sZqikKytJN}x5r;5Eu(k!%2hog7Y_5y&4<|L
z?nTD5Y?e&RxSnXu7(0&dh?vtqDYD}5yqHnF1+&gnQ452@s_*to&~FG_Xig>#YE!M$
zsiAmn9}0R&JB|?ie|6gamLlE$^tZVGE405-4#gl=MY0s*k?#O}RMIYSX@sS7RA0eS
zDD2BZ?w9nr6-`-}b0*Uuo41p)uv}Xv+$ZO_;TN&pVzpT?Fm;G=V%zCOj=%%04xe&z
zrYIBCK&(<(!nVe#OLKQV6<nW1HVrZyWZ6QY`}X0_{d3~&MdmsWEq!TD3PvV4Lto4u
z&Mc3o;BOp<owImsc$Km9mNO|{bD`YwHB!|rKth<z3vBo*No%!+xF1(Xc8Q;um137g
zC1umf+g-G)XB@R|f2rBlLShhD&+K&nAGY2Fu&%1k_g{NwC*29B;k2YR)PgJFP!1)O
zfXGw^nRU|Ba{7RVQV^uj0~RO++Uj3X0n18^OkmJ|^j1e1uZH;-2S%;vbr2OhK^ZTj
z=%53rC=dU4MjfvLcdm~SOM5@x-##a;_ugN!*W<T->-SpE{X9KcLRD_N)uHm5n7K>g
z()9Qy6P)f?3XOZxpR+)~5?77f@4>F4CzZKW!?aY!scCTY&PQhGWPWsRdawzbE?x4$
zzYDWe3swT}VW#ykfp0vtEXl#KY-L=P_-p9LGgptU>83NuqNIcwx!P{}qvT9eY)6M|
ztIA!Hm$@D_1;S&#iU6;~a2l{$ijzZ3KsR?RWy6Qf<j@8catLD5<6Rbb841<X?no6a
zCZ<Z3&5vc>tEw2OCjatjEDgR;D#k)Mt7geV5hRw1%=TKXdz_Z#D)PW*;dqsKZ;Z88
z7;yD5l7Js=3#FwAdz6e@3B_}ukS|L^-~h#g$uxr1<W1dV;11zN2+SJ<)I$^$1%|#z
za>8XUa_P>6>WY+i1qxn%YeJa_y4-+tp|esQ(4GWnDhT$^eT>wFESX?DRUK<gJ`qAJ
z1VP09G<vn&-+Y;zK}N`<;`9m6<SC`Jg)_rq2yBh$elCyEW$Fc@!g7v;_I;jCsWmt4
z;Pd<$igcvu$tii7Xg>LX(p=kZBxyOxTxbrMAymeHfytn%OGL=ToGhgEK#5~K$1I(f
zS_XOa&nBp;DrErO()I*qw6>d`>y}Vu&*Pl}%qdyZJQ_sdBSW>8))?X*J#uvv1JdU^
zx75{K0v`YJB_N69@;SS<C>k?i3+A$=4&_9zcF%YJzimTnDsMtgP)#_I7kIfaxIx^(
z2E+05+FaynVgO}Qtc*b-N{Z|lmlIv*fV&v&y=V+nd!9`aDewJi%(u33xf_qA!GIX_
zi8JF_l1;-q!YmIi?y+|Ua^$;w%mH43e1;S%C}V+yizyoF0z2c&@_PG&hL!;~!Ju#q
z)K?wIfvs{+!J{I%dN$n#FGHRwRD4wlYR}oi`-!bXft#jK1VKmA2@UkN@k(9vE@hb8
zqo~qI7VxJ>@@;V-ESOtm?Scm-$+2_yEp39b#yuHKmBMDNB7X$P=TuBgZNlz|RK}6+
z80WPBVYr**$ms+@L>!Tj&)w5Qbq-QMm4e{mQ+#F&{e_1Q1`+bZE0mLn$fN&fl;aK3
zw7jV#B5M207lPO%`-C(M_>WBEHpxi{brZs({S#|n)x}{T`yFq#28|^Y3?*nOa2l{K
z@j(<!k6H_W83jQY7Z5W>&YLvHixy-gLJknXy$+eC>V&p<#Gx!jUTzl;)x(9e?u|_A
z!lpIQ#a$z+6wr>9^LT)1IF7Z-%sTr~Ke1(a^6qM-RpyCxGID>xS(W+EWK13@b3DiZ
z!mm`)rUf#fT&hC!qvs_`=HW!bAg_@Tx%1wLAkzp4g>Ss)RJN+(2q&wd49r_z(FYaM
zz&0dA;b~WzGZ6HXf;k~MKns6RBB<XO_@HRQ^!gIC$jP!P7pct=gUdT8-xKuCkAzEm
z@BYGP5kgNgrZtVTT)KjTQKG4Le)(crG($`9F2BI(BU{`bq9;N^#fTDmYp;u9nH!*$
zyhpV_r<{BP^~k49<yR)MR;wm%(hb02oplNNzsqV+(iV|4cfC|E8`Jm|uIYMYG?T78
z5$}cq=n2UT?U7h#>kC=d$a~6q;hGtTVxO`b(jLT<p-s>^4NB&i7KGJSqsGx~B!P{i
zDt6KayzAE<65MxAsJz%-OF%uQLT)Ofm6Rw?F3#7LYh0|OVmS_aH{i{TK$k`jfR|Az
z6Ju1>TEnknkxm@rH|b)6V0~f~JEYfx_mMKdQ$N(J#kh*pPAaacv7WiNe5XaypH(0f
zsmphpEO$mkiuM#~!n0cojL^%4GtIQZ-LZZ>r+4%Rs0HrF1s}cIr5zjhvFA-=I{P(T
z6+QP%^WjJRh&v)^<-#AG^}xNcey@7-+~TcblB0byolKpJdEY3{tH6Pw%^ppCr2NP{
zo{I4F1s4K)K${m?vhXxo!_*V!%R)@!$kv+pvO5usVJZ-Z*^}d(wCdcn5TC?PM9Jx{
zvkr&Yg=s+r>L2{PY{-0XgYxnBs(#|WsV5COr|*c-T^WL=G<Q<D8@1WQUyO9AG3p$h
zU*mu!M+t@%{+L)u*|Z3_^Z`<|eYZ18dLqe%zN85N!(5}94xmTE6c5mZase<+*XJ7x
zUDLE4zYpb&2X7dnk)XHf+>=`@=|T}%hzE-fg0l=ykWz=4&ukymqGW=NVNkA>*KDoP
z>V^$xd`M{)5(EoT1dv(2AkgmLMGmce6lAUk`ZU{+xfHZ0i#mtJ!Xe6AtY8}Mg<U4h
zTP+pfX+rXm^aRNkFWTMohs_K~$O672CBIqUh>9zkh+NVT1(r!wq8L;LlqnQ|PfdK=
z7OgCYpo2Qj(<8lbv`177fG;$queMkT-4au{%m~ClP{e9Gc2KURNSaS|7L`DSj80Ox
zqU8{fw(%rXBWj`sY*~!*7ShyZ>;);(_C$~<Sj&Qn3~VMOSD3|<2ilT(D=JV0nT1|;
z>eRQo!El6S7nMBBPB7N`Mu(kNE}AxLPdX|9V}4Mw1uZ^N(@d%igTOp@sJziih9VY+
ztVo*9#?i-?-2PA$xy)mn(%B;4su1Zvm`(-CS}a<YAh{U)$so%UwW4Y&09vlGDrMfy
z`(!ch&iuM_0}uvC_;{A-0UwK1jgyJO@kM=4^C@LM@cok{TZ|=-TFRMLOuJE@7b3O}
z6;vP^1>NxUL8}{FD)B8okZ4*84IZ;#>X%lOFo#pnZn3hGwv)60F1C4(LJs*W@bA6#
zG#15T%QS*jfS)p9i6^Z&)1c_Gp>CNm51VL7wPnKc87znNBB7VXDn-(4)06ViK?+V*
zY@rf4wpm2r+7MbjS9%Uc(LjKR*e0NWb$%9N%`7@J9$Wit3}OJ6-A(@=q@fr{q#|31
z*si>Hx}9P&=5&hSkb{+yZW+fQhd^nx*Vd%4qD^kQp2UNdu7y#`2=tP;=&Uj!Yoa`+
zMhHcHn|wl1KHFGUw~%6r_*PHmO^BikdhCKI_2L{%*H#@O@7xR<LZcvUh!!)lL6{<J
zTQF!Srq#4aR9)SZVp~QCpQ0OBr&1M_xhxPw4zc2Y7D{MjjN3M8?;-H~M}jusjrO^k
z<mhmm>|&A6qj6x9C}bhfQbm^424w;?(SFBg^=H7_QW}jQSXfL9n#V_so0!>58q_yH
z!6Sh(@dQEEffHp2E)B#$u&_wbi8YC17XPXUv|id)GAJ-zgCz#x=#?sj)3!l5t1S*K
zSxRVU+9I~BhIJqXl_EjvTqIHtnrQioY)cDLaGMhKq25kqV;kZu6VaEWZ)*fkfw!=|
z#2TVia!B`r1ivdmzreO=xWj|OPz(Lx_#(|@1$fISj7p*8VNqkK$j;(zn_&aa-Ysx`
z6a(5FyX9AuGA<LXx-FKbdm7seiB0}tc}v;}Ku}SJu*R(6RHt(y%`2Q$UF06)b@no#
z5<%Y0`2hf4MS|G{iZqp(ueI`UcaKB{VqQU7hzlTrBv=$&DBOIAo0VGO;Vsf^wWDvl
zi-f_IlF7|uL9oyQujv9P2aiip!ZEGSg3^WS4*ejUJc~u%i0pa_sc1P=WU{r%t>tjD
zrAUi+3qrw_%I2DA=w*cebpy&}afVh5hHTH`A^O6N(a>;gwiGK61+h7TC)<FmTAAgc
zyjNhLZVDWxj#X>rlc|C<a*G=()8FW87Q(aD!;D^*71qIzDgf=&qEN1=Pl1)OzwkNt
z#mVsL4(COoK}{ZQRkr})3OQocWu2fwN=$s#)_@GMeIcZ;Nj7jCf>g<9c~8g@6q)(r
zB#0JBN^uftWYR2yH4vbVE$s|5(dr=dC6ybqL-uk5-V3d^Z2nKBW&w%0X(Wv2C}!fK
zF^~~Kaeb?;Sg=Nce-yeES`ukgYSWRc#h`-BO4~ty#Dq{t0%t?fSVnTx*ZFGZO$qv|
zS<o_rO6Dk{7QorwEGs0m<s`P)87&;hv<qY<5-dB8AdzU&)i5t0q$;ggMr7WogO^4v
z03DQU*%>rhcp-p8qtdyEne_r~`uifCMk<PRi$TlHoSH#Z@V05Nu$f8$Qll43-;xTh
zXv-BJlu5dJV34w46e$aXGu4QKm#ZZ#wp{L`G-&lEYXAy~O(9PM)GY6&XGg%H?*l+H
zQk3dh&o;Eyq?Sd}x*TMtw}nk}aNCkLN#^Djm8FTbjmri|x9K#3EL*r7eBqXYqPWbf
zKC(LqBNnUz-dhG*CQuF7qK?*LJsi^NQzCA*2o-s02Q(}U78att4-%ghe(;pQ$f#8w
zTnnRgv<xZw9U+Cq5}6iL0T^4Qh@)*JqeuYGe>jo({JWGk_Js10m;{dE9Rg5Arj2Y%
z%U#Wgz{4p~-IC3<9<&bC6E9C$i@&nEap?JLZ_?#1gLeBAx&I?9uJ#1Zwu_=P8z}TW
zj8fy;e4wx5OwHQw{Iq-*DD?$_c~W_t0-4pZTu@j{0G4kB;ZUsPA$l^A19J$StEx%8
z%CW`^lLqAiDFg3P;z(I&+gsGMQYcj{DBL3Q;Iatf|A3ztqSe_8S=6o^PSv_!Tef#W
zzNTpcx**NkBB{Z9%fhqxdhuhqY$y*Lx}@UrNEN%diffvrBIWdL@68o7W!o6=Fg389
zAg>mG&2l!|%NYF|5lV2oO&OGG={h)DTlm0T@0PBi&DFL|snzm_+CQSLNIT8H-cHa(
zlR6%`RGDfJ`4lLUDh4B01f`Xkh1T4b&#yuu5`$SClnBu|{*ANP1kz(jC_LfG;gq0A
z;Puz8&+4G0SN&qyNPHoL$)n`~JKdzd@EqU`N^f06D|bcjZUYs9<AQI?H!<#gyhYXG
z!7K=(-84S9DXkk6!VoM~m2E+xKv1p$iN-{srZ7zf21dp>OI@_Q*`y#<HsP2TJP)ub
zXSgmUqJkEfP_~AJK#-~gC@+sG>qC##gVsk{(}S~sLON<ny0zD|vOy_p*Yhc+j_E=T
zo$m-nipavyPQ$8z)X&nlQ6{UEL9d0da)}p0rWTsd>MwNQkYT|S6yRHW;PWVc(3`Uw
zt@0vb(vGBb2x<!S&d>LCz6#jzjQYXFu^<Vs;MyL3x|1tE9>kCkoGbAD4v*7SIf-cG
zUBkLi!N;Gp{^+hT7lHF;f*8(K_|mLRaMfCl*sRO1W-j6jbth8J`He?Y2^~e39)6&!
z>gf!8#w=ushnpXS1JcSz=+#!GWIGS3a6u(cW8O1(D&7Pi3R@USHCO&XlbVU^8FQu7
zUBPdXg;1VG9&(m)CqhD*4D_v{N*Zg_ZKC5qHiGPYIH<2=ffKKkF@!YdCe%ssZ`oD#
z9hKmH4mZg~cwQdiE&{oH4gBLU<x(f_>?P)=w3NnAq{n%*f;$-yd44<w6QXm^lXb*F
zaprxr>j7R=?oLLl?|`XBZO9$ZedA~Js2d6`z5cyh*Xb74S)lS!wdM8y;ha|!xh*II
z)H(Mn$EK1zuoLVtMqQ4a97aFyN~QAoj_;M_lU|wz-6Y`)vmtdyN6JHelswMs(aN53
z{tz@bdz>%@FV7PSA-GI7_2|okA)6!ZyZIu%ejx}*T04SxL_&LT5i@CGQE>U9gd9Au
zC-qmjQeTH%e9pSXSL}kucj#HnC5F41P2CZhn?Tm6<4cendU_`Ybrtoz!M{zLUGVK(
z#J8+FA-}_2n^NxNB)-kY`7YAw%RPNQ)5&O_(uZlva3aEhK?_}Fr0}aXYLFsz^h|KU
zG?M`@bj{qUGsCL*Y39y&^2%-}(2psHzB|CF>V4|%VQ}4Qm|=OLt7LJKCYURx&fVdO
z9zo;MfNXIo<3V@Hv#go%es*?8?(Tgp+84dgXA^a|F~6i7dN1a2=i}d^cS44?UgjE)
zU6MCG{e{MP54^s4%h24$)}z-q)-0@4dmngRe%89n8rAF18*#@jbmx8SbiZrpU7`Q_
zb4MB@uNmC5xNl(Dl1svwC!gDBT)w-q>T4hN%l4e>mL0z`$^YUn{kk<D@VyVs&4-qp
zn{PSd8$SEin9sK#e^Tjz<A=^#^W)N%MNd@M{C1D;J>&T1^=qFC18bh`Sby6dzkd6K
zAG+?6(Uog9mq*5bd(}Db-_v}<V{1o;-h9dEwx^f)_4B{rhpt^+F6~%<VgB@o{razc
zwsP#Juido##nt7fcRDxs>5o*Fom?#~Dpm8#_r3Fq%O86C+rxtwzFqb%dG?morC+|%
z$bNZQ<Gg+U(cJam8wPg0=HS-tui4?3Jp1m({);a=@vL1>q(i$lj%<JMtJiLM;hzWA
zE&Kj^HZ8mL>-#r7v-QU9uY_IicxLhTcf9+u>tDFlE!**LZrR@NcP#tl@6zqtf9SUD
z{Y|xT%AZ%)o$}f0vK{~EhOR$&!q9<dN@pE-vb1aOukzmgw=Um)>#nUkZr#;5nX>Ia
zd*$M**FQ6Q&H87SA9>(s!|PxC%rQIGyx4#1H(y+S>(72w-tqUR^uKuXSLeNO^Os(K
z-iu#7=E$cG^q>2}k;Cg=II?g1-=9+c+=z3h9Q=8H_Q78c9sAUQ^5y$}-@ItwlWz(8
zeq-&s?1g9Y?3Zt^t^1c7YDezddd1lfeW`i&t9A@5ne*bcOAb8N{kBaHZ#`?*<sC!2
zo?UVE{crGRzwl3P)AsdOZrpzG%3C&FwsqI`pCr59QM>BuTi;&V{=x+VOMmqfxAe2$
zcS}C|Ka=g-zgye(z_;`3Px*hV*Prq?)uk`axS^}R-!ZiR$<p!z-!1Lh_uc%web<z?
z-+CbIc=y5P$y@%pW5>^aQoiPzf9T(F!#@nK-+y!e`WL^lV8=IqHhgo}&&vPLJwLhl
znu8~luetf2{;O}kXZXBded={{p8c&q=Y_7tm%ni2^2=X$QvdL4oICE|^w1f<yEk9>
z)Pd^d4;<aR{DIYP;R)5Z=)IVs-AAvk?0$H4*KNNKtHwW&gv*-OHqQOmD;hnoR73jF
zYnRVI_qyea;<nQ6epmX~4{O(N+!VHKeAF#|XlHZr{r@9bHt?qdOO9J{{CV5oy6(K~
zPoKDK{iofsbDl|hZ~MLPo%rZLJ^#0Az2~ufsI(;?;u|_cd*9a_+WTIg^&VBtde>C1
zyy&{dm3_AkhrPe&xUc!ft(R5bxb57q;?FK<to^gKuJ_K*^!I${SANBkZ@U#&KjTUV
zPs~aO&vHjL9?DOd{C#=pV-GG~`q-zdi{5#qU-ZuF@{2zC_!Z7wd#%0m^OEd4KXi@P
zYO8KLF<kV(STq0jh1I<4+-qG|_twhpu`s+azpnJL$y#Zm;leZDZ4PZ3O%~t(eA4&O
zRn6rKAKtd?_&04iZ~Jv8uiE~N#`T*XO_rYXu<M=p*MY9v#{81wkMs5XVPEaJBCnP@
z^QGr}&JFGTs4w-N!o$;7GVlGwU479X`Wv5ovcIwCz4_3m$NU9L&)<5^pREt)ykSM-
z>c0Q(y1wy~e8trd=PQ={Lw-SXCHDFJ$jN)%oW`$~rxSly9(-&%pTBc^KL4F>&azhq
zs!UkTUowmRb|2H{y3Z}&SuStw|McWb;oim1H-^t@Hr?lH^}(^7ZhK#|`e>ied*1p|
zSJ$KbAj_AQ`~3B_<8FSXHgL(?SHCmwUwv_Y+Vgqk3wgHWELUol-IDD`yXsH=F3+xY
zt~AK?alf27_&+y>(j&vrqO;x5=a0#+C|%rq^VOpxgKv%<`P%-x{+@cR-cfI?TT$9t
zuMPR^%F}!nKH{>GJ45M?v)mlsKR#jn*KW>te(5@|<~^o67yISQ&h9*>a!Ti`vSVCj
z-Y2~KlY1unzHm=IfAL%_E9_f-A^YI+U0a9qd~o!^splIHW;=t={1$h2ZQbBhGru|;
zu7+$|DgRnCb^lTAN<Uil?$qSCx2!G?TypK|ow>)p@tt{vtx~0*S1*<)gUtueANp^3
zUV1b6YR(yF%ys>++A}{H>Q8G!_fI!gXQTeQ%ILt-D~5eun|ABI-U#bzjceD{{Oaph
zbNV;P8k5H0IR7l&;c6YM5FI`H-3i}#-X%*${At|#SiWRQ&+CU?+rv*S<bJ_zjqKDf
z`10xZxHCT1iFr#$H_fo+tgxb&ZzG?l9CvZxa6WV~S)Iu;|6Lq!I|`TITXya~zA!yW
z`Sd7swY;lZV{K#&kDO-To#ZKLcYoqstg%k3jJ;Mh$x6cAPX2b{YF=`Cp!Eq$H@NP#
znd4=};IH*5m#=ep=0kz~0P7;`-0~6jB3EXCWN@Bx4~}(`w}oTrcotxcfr5{CDdu1|
z+Ryt(M^|0!e;!0b$k^JX>z$wf@)uy_I2Y%$nsZjE4ZQyV2eF>_YxFxb_1vU$?q1R2
zgZq(l2Rg8Mk|x?vusL9jhH{$xy;4u<B$3^24{~|1E>5q`?L5}!^dt_I#TtHi7@fi}
zkNc#KJ&<dH)0Zs#CC;-~2E6@iH{w&}T_TaNaG8e(Tdpa3O&4W$wW7*>0~NLpr+0pK
z9B+s!c<QJqaG;SkFq7=hh6l*&3@=j37MvZqq|m4wCNDV3yy|uzjVPKQ4ArCSBDNQw
zU>`+{Fvo6`5J&_28tiH2^T%>Y5KCH$9U^fvQAXf(^ti~Q(6rN`n?DWX9w*Qaf?(9t
zKq#UzwBh@-1&3~Ozzd_!{llLtRaX^iNK-*!k(#Qg0E%D9<bjhwDsmX4gnB$?5^+XY
zq8tNJv=E?_9kFl^=>o*xOD8+55cAk4213&xM=NEFyiyWoeaC1*p`#bB4Zg)KfY5Q6
zrXC9cIt~g4l$udiAh9Lw&81LbM?jAe(k<}B&6b|fq+~g@X-R0&B<3;vP^jQr=ulKs
zmBaj?QXN3y=UHbNbIL?42pq9sDH<<Chss;$)U$+2NLbL@2Z90jgOmPF@BDm~r}<R#
zz>_C^=!UiT+_-w*GjF=<3m4qC@7*UodHuI|$7k;|yPkgN(l2ef>?_Y4xRv~uH*ULY
z_m4g^blH8+T)*Rs8=l>_Y3Z{cTl*{WPuy_IS1)~z-}(9Y$JX34wE4b`=Pv!w(+5BM
zj*~wA?3%wB`q5{U-}c<z3%;`N$sP9$t^d_U=YIJ^Yksu%pYPlE#_PU_>|N*n;+Zuc
z-*>@%2RASMD)|lPzVO73kMFzmvk$!SQ~&uO?;BmqZw!6>si#lgck4;7yWzSoZurp)
z8<&3k!)tCBdhRO=Zuswick{s)F52<=kFB|C=+gTx`^m5P9iJC}d(s2XuDz%7!_Pdi
zX2^A4Ua6U}dIu)wXWKZ3EngoKed?haO36Te?7+_c{xDjds`c|bK1pd)wtD+Rt5!El
z^@JY`94M8t6MHM6dufs-KJ@aIYFAQvaG;|!*qQKSJV`Z8I!Y%sJC4=#!*h1k-V+9n
z=&22qp06cCBYWJIo=P&OCnUXjl9U!5m-~*>^K5;V&mF0`lh<^0<TGC=^{(nGb*<su
zhw;GU{qsD(g4?Y2x{l+RN0#y!o38uiPt)cfFTZZd^RDdQqaT*d+|xW`w(wE)-T~+S
z>H<w1E>Ylum%WEW^oQq^hVoD+Q+Fsjo{{+$L3@Z9(t^<LhvY)LN@$n27#_x{&`0G_
zfiEH@|2H_KODmQ576s>YN_qFWBU%_m=)vkw5wj!ZdiS6j!81MS=V2?H4zh#c5kRlg
z;t=G-@|dfZt7u0Bt;n_n5SK&REQYJTo#Oli({mF%>;E`oN5dyCCqZLAC6nvkvdu+-
z*Cfkn;yw8izgaCs9(NF;-Wjm>E^;L#&pKRlOxP+1C&4A=5=iyr>xdg{x~ry(%h-2_
zX27|K4kCycH7JzF+05C!*2EMHaGDEVg^OH1xSC0yoKJm2O_FluAXDAjnTgXrtO%?Z
zIAxrN5qD~C%aZd$J-=9DQWk-l5=}VZ3T$`dfzOx+a!EiBJeRnL1}-Ah+7`Z(6i>_h
zlAM5VJ!?3qd(7lt3*+Ftr?ggHTcNy8ffu8+j(>=;4>LNg?Y{kX^3?Mc#grq5XR2*6
z<*I>!M{@)gI(QQ3fE1V#OAUd_hu9|y>hK_vCON#dz0pIi1(C|=7?r9hDWxLUMgl%<
ziA%|_P1``oojXkOT(UqH*hvU6uW$$N*&Icu{}3UXE}G2l28}^#;H$b)Q$XT6)b9j6
z9A!Q!D}jt>FW-ts*&{m9+hMHaT88Yp23r;NKsOlFksgH>klxd#ko+z+sDDQtot*QO
zIkw000T2{K1$RJGK#}10mZXc;33xzGVu1Q&`drWPLYk_PLKvswE2tFXZsFC`qZZvH
z@2t?<S^}X6p?L5juSQiUppv-zquChJFwZt*wD)w`N2?$+xa{Z^6@Ux$J1Ia=5E<4f
z3dueUpb?O=1f5d$iYj*-715FdNl^cdfz45rvoxe#T<(i4P!JF7^@I$01tvjE=kRc|
zSW^^wniQ#!@02Ow=}l>?MkJpO2<y_O<|7~*^lnUvn(foprGtSCV?6T82T8kDMdJoq
zFTu-$!DpewgNDJXn*%zcpHMBInBLh$>-)5#h^8gvl#N3j!RgXxJ>&PFAehm|cvbCT
z6$E&68k5_|1`gh23$geekSpdWuiodpOCz&ipq?NZ<-H`UZgsIL<$-aZ57*+f9t)S2
zRinfeNTI7vX&TFFtX3-Nhn2cTLP<z{jh6><w=#m8gdQnr<9>=Y6YC{7?P?3~jECGq
zBt@$9Dz6gqD5)t#c*#^9mqlX08yZ@%%zXk8WLz#Mh}^=jXn!1%E7WVbR~6=Y6(m$}
zp7F?I^O+A4(OKRJJ&>Tk392jCkc4RcBe?lKNHl21C}(~26VlSj?zNv!N`)neqWM5>
zm143&30)u-oGilbf;`t)PB}qfhDbUlXiFo7Di}9SS9p@0saNk4@LZ)*4X=!sy`7O~
zxXnq$?=+2lO4~ywJ^+=Zw)paoEUz4c*1J(eY08BQR16<l(z3GJF@RD_wEV7W2tnDl
zhHCNwuH%BBIWvA*<222<)+R`$i0;D=TWJF8!#rb7XEPS6)%-!>yBcZD+dy6z846i3
z+B2xO1(-&?#B;mAyN)qYIu{{RU904iB$6)blK`@y1smr91s>1csT_865oMVxkwimy
z1vfD6nNIYCS_x+dsAPlV^JC7t$t;i1$qjL!r6-7#6KhJ{jQL@{#FWDbp@BFDSB#s0
z=P3r2g;*3jKCDK{bNeVsjCW80?>`#YZ~s9<iFFJ*cE<}ZaRvM)23iKMX_hzJy+oLI
zs?OtOf3ZtPNqN^#YlPH&B)}kv$jzTGFD!d(6s7YRC?`%dupu##J^hQhf<a>nlF@8=
zePDDVcO$OTWo)*14Rs3b%4wKJ+oN&OV5LFcbEC;02PU7yiQJQ-vR0^M#u$kq^zxPb
z7D)xml(Q+<(R7J-5JdHz&gvMHBQlwI;m_%rG=gW2tnpR089eCV+k?{v9CmcDjs(o0
zA(yy8YEW&4073OSF@)4-TN7R12vRe<mB^^i{3eJ-(kmd!5?EEs3!IyXU7D_WtSQ$8
zfjkXNwO&o0`<ayA!^n91mf0y0FFJ|}cuRzdHuS4=q<UzY`GO=+=Ad~5+<url;CR(s
zHHn$8`y05Ztc{3|<d$_XGTn^pI3x1S-fwB@$p=LnCMFq%Tv~D76Qsj;=W&Cb#_OFc
z#}7#%0;x0%Q1rA9mLro*wMz|o90QIM_COn>khD#kOolco@QO~B(O%}|B&oQU7TDFN
z;e5>XJP)(z0xWFe@eFe9{~B4(^YC&56n;<E;Nrd>pEuonEO>9u#4mLg&OcpOMbs5!
z3ot*f8bMS~l2A;oP;4jbodewR&p;(fXN<1o=QD|ivLDR52YIb1P!w(AK~3hkd2^{e
ze!3fR-3?|G9%+FfcYY+MZs~NxW%=S-<#yNwr28^Uf7Cl{iSslFlB*Oor%{LfIXd{h
zd?%L|nHQV1ca2MK;`X18@|{G<IJFAMZWr;2Y}n;=6nx6dg~Qrdys(+ujt;sB$8P|M
z7$faBR@f&s$)W}ZxReMR>mmgOk?E~cgTNVs(FA1^4)!})6d}ptB_V1Qc}Kqota3!L
zKLT1{#yI%H(bQ!q#Nur@3MM)F5^rj#J&hr_7D#~t+8V;ZOJ{y?mV$)lmi&r26-104
zB<044U6eQ=5s?KS&p<4=(w~eH|3k0whv6}j42WnJ_xff$`C@e<Q2?x3o|S0EOX1d*
z>SDfA@16taz)I*swjUABE+Xb=pD;?iVM41aGh3$^(q%om2-J4RzFsOBWM%ZX?mRI;
zEb&BzJ>HXS13yq@w~M*+9ojRgl|f6DaynB`)|kfxzAZvafYb#6VeSzV0%=W|0&N%o
z&5}tQ$F%|<qUxm6lzF`;@15JmYNnAVjoG6mdL6St8mJYKmF0N8%qVayg+cfc1)c-?
z$-;T15fhubN>QTHHq`A0457}fl|_hlk;qz<*r$#%c}v~J6R|AtHvdd94igZ9=$S-D
zRajuMU}#zll>T9z!elXeiC0Qqe2KJz1!ZEZic)I3rSEMaAYgj14D{593N0xf1|HAB
z8wkG86Msn(yjw7RC>_fET?}_T7nz@Atw(Qd<Cth%;^|05mnJz|ixPICk<hW{#9pPC
zY-);Cbv7)D4ABbo@dleBXOYYe{3{!1M1zsgN)%bsKC>N1!JJ0c2G1A8gr4sg1RicE
z3<qK7Vh*FqbvA#K1!0Iqb>->`1~{mq70Gogn4LR3I$HljU0;+C(yu)cE-`!cO%ke;
z6GA|5p0Wg;r)2MfeEdjc-7DNE!m|-sYW85RQJSMk#UjUC!+JeyM?s~sqP*_bh>l5n
zTJ_s<XL(5j9%B(r3}AyTugZG+AH|5Qk=fNBgjoGqCPh}niP*4gF#g&12BG-si#i5C
zOB*x@gIN=b0!iR&GTwz~l^X2J5F#LsRK_~znk{Oy!_q+Br7pH+2<Z%s0TmAEh8wj9
z5P+95?NVAU*mNUQ%2CK9r1qRvj#~E9l<@GP6D$sJ5(L#Mpe1vFYDF_eV@Y9)R%DY3
zMim(Bopx^JeY5RqPZ}m(1BmaH`9t=gkoC}3`y<z?o7*<9%c+@2dppwwPnpzeuNxL~
zF$6^t&zfYVvz+u{xXkB~i0>Z*g%6Yhd?cvy3zM4O42qbR^kl__F=+D=Ny#XHUQEVo
zUNvZmLx>rFh|r{^c{D0tNY}Qg1@>7M(14VSrd^?-ZOFiBI+0b(HWkjd6Nn7vyOJ+b
zgxddNCqKG9YaqH{1*W%%Y#5JX-hdG8Mr@ZFQEK9&nSC3w3`tMSmyz1{p9s7h(=+a}
z7~p>xjLo!q9!6kEJgf-KsYJWkUXe8R#W5qes7+RgBG+I11}QTMwb=KAQuW9YI0}%1
zM$s~~IzduwUTuUMMR3!U36L2raj3rd9R}r;44W1)&7w{T+7Ohs#;|#il-kI*iltnz
zw3Igr?Qgu<ItVY$ttjv`ih;>#C5eJ`6P3wLQ}U#OR?`9$i^8+P;?%1^M)d_qLYFTP
zoHQP$vEf7-ET!qPT4Wl&WlEk<e*SfoOEBK$>;O^TGR}<^?{CS!5mYwa!Yc#dlJ-bR
zV}Y@d`Hb~I5F81DS!fDpZDpuLAu0sRSuBM;$LzQ$G&6!>!pOgj)SjqauSyM_6{#*j
zv3?Sz$<+hnHDg!{XxV-Z4t87eVrX$dSZouercpa5Jd0e?H15L`0`=_t*itKy4GuK>
zTR-ewBu~%C(FmkR0U{&;2;uX8t$lFOoT_WUc3;;VeUT$X$7q?>6&lUlQHr;L4WlKC
zFF(nkq6CSERM-aS0_~7#+`jzZRN9G7rW7qv+z4;e!n9B}sAUh62M1M3d{%D_N{UMn
z&V5>$m_eWzv+Z2KHPlQfYq#C3I^MxYGNAt702*XU$RW`4n)-=CSI`$7zat2NdJ{x>
z(}tb`=i>RWF7%h^;H8N4u(1lkA@-5tLRMQx6$f~tN9L6=;<gK*Eq(+bv>fE1(ZyKP
zq)jCb0P|vzK)%!wKNzrx+gZr$X2WGYL8Q>={t_p)#>gzNz#n1^$#7^X<{E0tPkfoc
z%fwiQJLxvHe9-EulmjM~XjGZRyGTSk6!fXrM#<wb%n@pAK!Zs+rtx8lycr48%;ZR@
zV5FQB70kVC8D@dA_F^u>WaCpfEx5s15_3rFl4dk)4O(Ffpf8}qXwj`%=**RMQ-pLu
z#>Ja}`z$a0Eomg8hsH-@H)B^T3l)?X$T+jZE71b4*sCr8g;%T#U<Hi2V*eB=<nbE=
z>s_RRF(je0mKFqy3x4dywW(=SwT78QC3_!t?t`BdZE@y>6|HI93n_lk<y|69qc;R$
zAZsd`z(T6wNQ%__fDZ&gfn>8@(2TAxn0rVW6c-Y$f@oP$KqvYPf=LN*tm+;fd3^vz
zr3Dmniuv3$@YLf7PLP^<ikiiKzkNYloPY?wa#<J1bfzK*ngEU}(k*9Gy8thG0YXhK
z0_oRS<@s~GIafHBG{7ZuiwQ!JP`)MDR5f<RCWmW*6!wTNh=?cMTRpuCeG1^w=*WuS
z&f*CZ$8}sKgf2yp)R%I~bE4H%V8{S!=l?QCKK#FcX{Pz4P*JwEMFpLv>(&WSNMk)N
zrnzX%86~wS_aZ7ZbHZxva?N1^)<d#_G)_X2Wn3mG5Ql}HG%_4hO3|euVJ!<_z0h)Y
zF`EYBLPVi+TU!XCw=x3cqPvDvyEy2qUjV{z?`;-WBfO9R#Vl>bLO^vdCPn2~2zO-?
z(o$n6QHs;WI!bp49pqkpY2%Ne<#O9|dP;OqReS?S3v^|n08d0l^SEep@1<7(HeUa6
znhdub#ly==k@?}^V&T5J^4e}44v}BbHfyvy0HWkss<qKmgJ6h6dy-I)MoG~X(`&h*
zT(P$u4K_S&!cncjVfCZZrW95(TG?{|ToNyHv%)Jag2W~yrD3lfFM?)a-k|FH**p(l
zssr#ZNrxb4s}YKP@aEBUB3hnY0Rig@ZD=#D7ieM!XN7QE-6AUxb<63RtclXJsbs_6
zi&e_N>#{?ueJbcZ*uoRpZXqEN%rIP@q$J5Rf))D|q4Mbe4a8UXOMsyFME?6*lw@VJ
zwURX{G68~NR}$#wb&boO0fa=}Ao0+}WFvD5-vKLyG{S5K|G4Z!T<WFPKu7S?EUFb3
zLf1+rzYzE-?EVn-xMZ-Ox6E{1!zJ^>r}f)JU4iTB&M!_*o6c6|uA4VvSepTQa)W5q
zXuLa1WKfVvWf<x)kj6@csFSQ>&FMtZY<XURrd%m6NSeAm#z(h8lQ)M38QW=j3l8*G
zAPb<GXL?fWCs9nwel8~DO%Izgm+jxi#MH;_?TjloI4Y`JWLJ%<3r)~YK_ATECJaEp
zkmR))(!ug<d{VYBAb3Tn>f%DKJJ>^{o?_R>??m=fH%(O5lczzv*SVCY>j~u({X8b+
z^8ADrO8G4MiTVlIdG&7JHQ{nv7NNX-HBWc``NVE%^l#-Qeu)4cE~+ih`YNemz2Krx
zJRi-3n1xZs=pcKXe1aOzmu(zO@{Kw5fiNu&S&#EPnaP@|FWb9Mm;2*DGN^Hxm3drY
zZo-;e^Jo_MHl1q>;BRdLN?8b%QC=8I0t-_<?MkD1o+xym&nAL1w*EQ%W<xg5-AVs&
z?n=BhQp@V)X^#v!h^NwAcOUm?$&AijO8<c`v+2~_)J3<Pt2Ek-lxHgSG(xh5vW&$v
zuh5QZt%FNTOlQpyd@Y&Q8EF^Io`rc-x!2n55!V-!fNM{1GpX;T`M77~>N9mdspgWh
zI|KL63-bo6y7evQ187ed!ZG8HR{=A(a$yRhnB<Oeiw8L^sw`lnx{vg@*VvwSWwyXU
zqsHL@CK;M#`B419A`egcSXVda5-2Lau9Jp=x8CL^Jh6246whpjMg>Kvt$Gd56x`(M
zrv0u>;~5MIy!ky`UU%%TUw7f_{_&WjmaSniexOo2drxKVSwBBIU3YE&yf;1I7xevf
z!7+=kKl-RMf8Kq;O}mFWFM7PMa@O^itXY2j<~1Yt_st!7`a_j7x4wJD@*7rPkiOh^
z{K(7Y<8P{*|K>A4z4C(a^zO>)r^`2PonBeH>D-OU=(ozJzx7QQEn9z}(*0)>mF}A^
zed?4ezO|vJ=l#c5&;D5D#J8=!XxVk)ob=|OR)!Y6+<E<$N6%UFr_DysirsxDZ~kQ0
z$y=Li^P&3MHBV1<RlomK*A1^eZ_S#;Z(G+h^1ZI1=RVjq^vbHn5wD)xbHqhYFZAbp
zZ{g4<ws!aEot_U|qj!Gps=j8T=bLB0viO2CUwP<_$L@dVLigi`E<9u1m)4&4*jLXz
z_TYmHjy?F11%1ExQb*q}zIw!s``@r(*Z$itII#bRM;_S!%8|SFU$%DF{^!<iefgDh
zw!VDXIZHor+0V}Y`*;29rURE;eba%rpK#M}FS};jZ{Pin*WYx*t9IU0n{(55E}nDd
zciuK<*9*Ij{L>e1JmrGto;qdib06;A@$Gjk+x6`WmhF0G*D06(=Uu0q^wSr6U;ERa
zExY;U^Llr@ysG!+UvC<^<=5+$-S~|abKm@p&FB8^iMeYIK5_K6=YDYB2|s%J^5fS(
zaO}|L2aa8K>r?s3w?1|3(E9IR{->M&>ziKv%*&@N`!<K{{cBe6SAXZ@+g|<bUE7wu
z;r=;ifA#eX&pxm?aU4q?JEr^WUmktLqJ#bA%YQfA*SGidqx#-|>cTbqZ$IkBTTWiM
zYyXAk?b?4u@2>s-gv}Qox%J-{%-Qzx$L5^&_dooTGk*8V88;m`|C;3o-gV78Z+zyO
zZ3o_c&AYI5`O7!VIrE?DC*1U3-`RQg-Wz*Qd1(8Qo1c6CvUffA{!@0Gd)?Aq|Fi>p
zuRdk_GgmJ=>8IB$S^Lu+OK$%6b9#4tdHu4Rf88kU`t`aa-|^FxbFcg9rE?EH(Y@`(
zCpNEn?&<nf-}>=}t2TeKciHCOo;UQnr@Dr|@<iXVOaJNE<g({_Px|4@>zDn-m)G~|
zy_epvaPR5zZ*D#I*+;h?`?=*^i%!3{zVP(BFLdtI3vc=5;?-{d#LCM4<C8@nctdu}
zM1M!$BYW!Uzf>2z?U&16bM~guCEI`g!*$z#UK+Y3Tb`cw;3ZdHx%Xe2SMGiCsxvlS
zcFmdl7tFb-=j6&wJ?CEKKk`4$S@WLPcPxMUb;-_`*LB{s|83WtF>&6&+YdaFE<EtD
zB_r=CpRnk*W3S%!(ivB8`;W5+&v<{Y-+cAv%IY<5T$X(E@+C{Z^Ufu&oN?^cub%1J
z(jV7fv-#?Cu3EqQ^2&vqT;-TeqXWM=z3$F^skii_i+a1ByXZAt>vwll_S1LgY+B@A
zwRlx+^GmC)ThPZvnA1C%itb75eWoA#dj8{2XT6`hGd<!1ce?riQl6JRGBt1A(B#qe
z%Dp|i8nx1{M(n<2;?AC1vQPJJ+xwR0w!O92oqg8BXPkZ3%#wGG_-y%_v6ajJ<M?w1
zAODAu=37r3sD3ZJ{mlK%6K>k?mUJEXLC5h2rsllq>t}V1e!cU!Z4WNGdfWZ!;2Dpk
z{*1>q3>-0XY1i5{BfU$%v1Qq!_YZI9^6)jUo>_as=1;Ee-2BN4vht>EN&lvegD;*@
zKk0X;_pSTUMGLdPy6C8`%};eM+x*1Bq25irI=Hy^;kD0qJ$%Va8!A0LuV+GbeZTb1
zedk7|$ScYl%cq~dvFEJ5(frZUhD$#<uP+%qwVe3Rl*7Y$SU$f$ymR}hqZ=MMakTOH
zi6Klb|KQ4r2N#^YW%2p>&gBbMC$FzB@A%wkdSdm$kXOsY`SN*#eN*RO*;nppuI}#0
z%cJ#>&kGlY?jw2{)mM*=yZQ&a9<Oi78Y}$h%r*TZqyAOtPM<Y5oRdB8<{a^!(K$zr
z&+9rWp1L8M*?HQciN(FIiuK;o{Ow`xiqVF9ytnF}?DCV>RI)pl43(1imGbN(HCCV+
z&sFfA=^EAz=5N_I^>x|jA91IbA4wN~q)X2$_J8kgw<3LSR`YX1c-W0DUo;h}S5MYQ
zAFGCoe{kYxnEZ5S=fqjJ-B4M+G9NClY`*92J~wt^R_^Za40&mRcN1mbx41mm*VoZZ
z=FM>zPbU|LvCdVY`>0pD(yQL%D%m5q)p=3)iF16p+QGN{nisfwGx&8UWX;|=-S2tZ
zlB33tpEEDcJ*{u%;<p|<!J{Hm^{!G{Z*+HDUUQGL2YGL)8vo?9(!>%T%y=KG(Vc8V
zGlm<NSW=%q&U-T(H_bSA!&O*1Gg0TG#KE~eb)Goen8XNjH^==O%YHh9=Dp>S=}DH`
z2iY6Oz{3XgZLQ)wS>tXeJzY=3B<abzclSS%x@lhNnGQ*M9~-O4KI$bDm|@!%iSMsv
z+HHh;*-P+<Mc&VHJ~+bOW@jxd-@<*PdO6KU7PGFWGkmE&<{pppg!FR9O52^L`5-hE
z-u&YPudkZ8MLh7;UuCs~F7xcG^J7+_y4#dzqkZfevIgi!VsW7==$#*&Fv7VD>>@UK
z!#F$3kv*=?!HE}}4>!q%c#`rs27h!P2ge4+MS6$ME<`Un@&?{{`?z&vFE9i~R}!Zi
z*h~6ejw;l|e)x1Ax}9K`<3d~xJ`d=GK3hpAJF#~VdB?G<@RV_si8$CS$QKMfa1nj<
zs<lqygfBNK3nY+nzYyWaQ_em6K4AotytWntXqBNcC;OEcb;C2&#ui(3PnJR}XT#nX
z?4rieBNd*~FH^(uYgR6J<m(d2)KB1&kWO5ba+Ifg;3FF$<0mMqX@<BeO-~hJ06K&T
z$gkuXTUE!tG{8{b-2fsNUF~axE(>IR-QCG<ZE>D9c#g@=k+e&zoAdE+l}<%oZBxAS
zbMx<&0=xoT6C7nlxzv?$lPb+9@v6qK*AY>l11<RSuiDSm;9ql1NW8g3#92x}houS$
z=@^KbmNA4<XL1A>z!n}>7C4teqAzhiU@%-noOW6QK9b=rQ!ZjMjAK~AClWi;k%&Hv
z{~<~_^mMAOK`7+t05zWk7ven_yso}wIw;$MM6m~p8kpsk6^+s5DXBh~N8%u>4b(pJ
zRq^$wPRi#S1+~pRDk&12zu4Ji3XNg<vnF*@)Dmk)D=?m&JFUp5{s2kJOf+_SmDt9(
z?7IBEFTC+f?(tLXou4mmaPF>OZ~oE)zghO7Th`w5j+=Pz=HGWe{ng+8=A^&eb=^G|
zyy+KD?D*dPwJ%oQ^_34Dc=4VKZu-T>o1Z?g=CfzL>))Q+b=?;)czN%IC;jNa+P~TU
zqksGUyRZArrGI$gjVB#=Zu{Tt`oq7yaqTaj{L#S|Z#?PX=51fx@yxH@amg>9T>pm`
zHhksabK4G{@{cdR@#dGGT>FQ;8$Pw~nQec6>$mtFpTB)(?f=}j;Zp~HbKRfay7p(g
zHvi&@?N9&q(ogOB?pKaEc<aAzSpT;dZTrKApWd<K`}e*3-GBJq<{$05=%i0PwdRIp
zPk!na-T}JwxdRt1{lpV%ZqPd}Z`#8<KR>(iq!0gi&B;l<!fe)AK69i~PG?|eZbMf#
zZ$5PWFVT&D!X?Ce-MsWMmz*9m_ol5py2L|h<)LJrf18`v2zMtJrxQt7mL*%aI(PZc
zuW~DXkz_}tN%xvxHuJ_WLNYqinfZFQ;HKNRB>av~=b3!^;?!>Mj^JVLqw;#~qRAy$
zlcQrzNREBpB_EqvS$fmVp5CMWI_sXp<$%?3RsQpIW$8Q~TKi86hqK<tN7Kb4BSZDH
zYs;KoH}}ZLT|ReeMSclq)brDHvg=U>c5}4O=<k%hLmzhTHIJ74N5WA<*a$=m|0rmo
ztXEpsDN=13b*2`{AEk<J3@UN6{WlHd{}1qOjP=WQCc020GbRCh+=MK=4BCC28oq^U
zC7>3x2}uU!+54jQsVgn($ucXlyi71{6g5VJOGY$cqPu&(w_&MabGWUZ)gj><;!&cK
zVRtvoCeuMiIpY@<MGZrbY@ud2nC$!#mvTzUYU(KPoE4WFfydh<mZ$Io8yix-ypvGB
zpXc<gd{X={A?X=a;ptlrG>du;6ts(htH;6xXgzaj;4!jFmasAM;Ls=WeTb;85)o&<
z0c6ejh}538$*@kC+tNzw8I?K)@bsbc)yWA}J6fW1cbuy%h@;HQc!<1BzC2JfZnEL`
zy-^>TOzghS2$v)PW;<eGn&e`h${^@7Kc6rEmwPDW$C*dXyWAP%5!D9eqf{Jp3vG@H
znN)Si9bOnz)vdjo;wCDUU8KNO9J>`ODcaV)l|mISmp}?h8A6fD9bJ5bghH1{S@H9T
z%wv|!2Whh`%=ky`0g)LEm#iRdg3O8wzn)t8sp1KN2Ol^FH1ij$HaS_H5<9I9O{k_k
z8P+IRIJ2`Tw))W6ii>NxP)hr(g9zT5rORCSsERXNH1U|}q*vA{1YqZqiXT>5uUm_m
z&#LMR;{ic2ao*Djar`{$xBO&x-Khfsm~mAL@)hF9uSjV&HaCI3M?ZIggzz#+Rge*P
zrpkJ~pFxS2sgWXK6W^mB31ea;BhbQAhX%;3ItjX@1V;YcTttA;xV-TqkiyBAqSY42
zQ=oL!#ToN(#6g9uNs1W2=<tCccLhQs=|nGzh?wM;P|P&pQr8@(#8fk+cabeDsK6pf
z#7tk~;WTJ*f$IzsYs`p@ce#o}!@|1$m=gZArO~Gx>17c{00XJ0)?lp7$2Ko45Zny6
z7rb9J>Vh|nGZ7M$`yfy9W;)V^)sb3UolvKU!D(9I$Hr~5FY63yC_Lrdm>ZD^22{%<
zP6xcxxU<e>BNP3(#0clSM8BXIDqal<1Q)vu4#t-LIG_}#XTwBz7B-_8;F%euR15Zi
zbJ2e1<;~nv^i3Et2jGh;IZdrCh+URYuPVFA=*I0fOpK260lh2lDYi|#i-RP+yCakn
z5<2KBUOfi6rP7Rkj*-bLZiNHt>KRi3T22#fwLTWvkup6{v8{mK!kA$gP$P~&r;Qln
zWon8vzM>NZ=;=!tBM{o$_4JRyL#0xOel$#a91nP*s6S0U%y`VFl88{`Xw?Vrqw|iE
zEK*<)Q;+@;JtOq3@7`HSM(8uI^py(Oa0|tAzAlS+B_OR^EnM;52{P0w=wqQ_M<Wdw
zV_P(YWJj>jE+L<n0=fAFcsTka+yauW9#NqWQ?+xIdiBAK)=4Eb^Bw4~1g@t{^kno-
z$k)$eROaEGC_90$&>bo9Jg#p<DLJMqs*Qt2!N|nJW!ph|l4MXUNcmTTO+^ymImvHo
zWToZksU%9K{is0`;l)W#R8>#U59E~aMueJFb3DZ0(gq{O`5IEG!vB<=YM>$?IY_yZ
zi=BP+pkZSG>7>|D&)89eE{$x^<(?#vNSFj7YA6jCy69kO#M0v;44BlKFHIl#I1LcS
z{~o7iPzDkkOblBvu0+UOHr4u|tvI;B8k(VQq)ZS{$(O{)G9FJ@;&f7i?z!3pbn?A6
z?xc{1ED_#1be6gqXTDMGEC#)p)+Uf9qU~t-;F6{rr!=}QkOnbV`(FB3k)wGwLeIK6
z-2_w5=q1P)7l*XZ+{T@~7^C;x7YV^-Q|DrgDto6#k@955bxro@a~i?=my1E#dKX#L
znK%bT#I5f6v5~C|U_)k=;pRic1=$3sBt#}GN@xm{fy3hA73Pu=wA1*dedqV%@FDkn
z8Y{uu_PmsiHRJ+*eR@(F=~udPf4X?(<BV-L?szRheEvGXqk*Kr!;ReW8^%K#`Z1we
zP=bGX4jl%}Zl=IKeF%h?EP}Y$v;0sQlpl1%P3WOU5#kMrm-?K?2iNU~A>wVzjGA~@
z1m(I{n=zv#`9epR$T|@{-@`u(S&GMoxZ05V;6_l$P4w^zUS3J_y6>J!OH@Raj!2w!
zlr->4F0HXM9q{3;K^3^tqe2B|MCbnHPf2j0MiY8;%+KSsoE;lY7W=)|pqX?rFyX7A
zwPJO#p~zFRCEaHWej^3r&A>I7%%RksKd@chJl7G^Ad~x06#EB}$bZPnu6xk+gepH!
z6gnp+T&)%;sb1+ir?Tg<(c_zPzLhQUR63vTJ>g_CZK?Lgf?B<sH~w%GowbU8sLizz
zEiCz}M>?FXNA$p{>D<kc$f4RtV5xm$znedrIr?`be@7SLSZ8_uSoCDkjAz)UC!Bv6
z*7oaPiNkNN3;ZCY-qNtwD;dkKM%U-U+&46N@=Q4xm-u@-%aQqH(S|JXeKcs0WG?Ql
zc4-(z!7jcjNPklIp@jR6lichpyN%rI+q#nV$aWWg;Dh{PUd{$HtMJxhk~JFi1y>sh
z%;&vLen)mI-%H5?=NKA5bW@X#Qwq?+Z4k#$y|}tjAcCU6U$h>koS+<L)FS}Oq9s7m
z`9~}*Ydxt*$Otc_fixq$ONFwYK+JVMI80d&p`WNol_R0(0!|Ikc9OO%{YWu{iBS+z
zmkB^|R~|`FmKC*KqXAlo7V9`kmep@O5VJ~}91-}65b1cx+_=O?sss`OSVzT{&!Cnp
zp~cL_NyZjJO~WRv><8r<>;zRR*@9?cCT(?k5(W%2B?&4D7{KK{dIpeK&3Ylly>>yH
ziEeDtZQ+PG!eDJ{Rj^nX^)*h;blz3AD~o!*rv=8;dq$tCWBe2&l_BA!fqguo5a@#{
z^hhHmkYc+LKJ6UI6*%WKCuV8g6>GHFg_^udG-)%I2(fhyVm!4ZB9sWGNMb!<#-XTC
zQ2QjW{D>MZqg|*yE6p2qMHmT@_U|=KQuwQF(@ylFhB5V470QVOiL;VO75m_X89M83
zH%t~a*FaS$lsWTzP&K$0u!7XUSk!VjSCb&5C>;4Uh9CmkUx-01NrK>bC9tBDR}d5k
zf<%<YXH36b<8q}gCIVs*Y)VfVrA0mp*)|3Kavi5W;t@y~M5QH0*aA5Jg?P3eWBs(E
zp9V-9a%o+Jhy2CsF0HDqNG%e<d14M;C@8?UrGgV?oMVgQ%rW(m<N$|(cN+i93-I9Z
z$O`SwWDU%&5L~2NNfo9NEmnZmk;3+DgaosawvK6#;7%>IZYo9d@+#SJ7zE^y#U$}y
zjSu;N(t;895$yhBfFbh)tP2~gP#HkymYH@L?ETgW5flKvP|Q^<w|AP}bqu93Se}3`
z8>OA{JODyPeR*pZCKIorAm5sjc*M$maIv)-1S<>CqVZ8*^vI|xfjaOMAYelInIP`G
zh?^=0lju^-jUm>Bi2OIex71ddD|v$PTzcXHU<9%ND|i}25`5k|E-cQ;x>ptGKorLb
zu+bRdBGq#&ng(JnNZpKj9}q1JsLd7ZZe>(Ihk;iH7!L}m6N*0J*0I+hpJW7D{}Xm&
zEcu>J0MLOv{IR_Sew68+G`lU|@bfg=u}sVYme>p^Zs?swqA3o*sLTQM!=(H^?PIuE
zb*ODDC8?R(xeY;yI34J@5sm`Z-zcV$Kl!jp%?XO9XUj#a;YS#Xl?$>qr1&amQi(<&
zemogNFcH`xK$T_YFD;>I8nl1SM$A7TfIXgoNr(G09&|=Iql)_MRm@0=V<Z67OR@@i
zrDMR)(Hu)&y9ir;RVGiz`-wU&1HE_rS0T@$0~%f-AYuBixU6Z`u`B9v5y!@1wh$pC
zMR_J-qn)ytXJM#{It9d5?1=+p)5M3sctD=bfFq`J;^vKHf(s;-=m~*nM20k7GMrIF
zIt_ebNl!!x^t}1V4Fsvo(FP|*IT}RW$lbt<t41MQ-LZg1VZB%e9nrZMj4+>}fQy!P
zCgB7$ye}f=4dV%OwO$Lnb5}@k-HmHywy6jAQ*neo7g|(F#No`e>c=wF&4osNN*pha
z1cKly6{0lgi9Lv0*G@<?I|etwyQ*S9y+E<SAS_bvVmU)*S_}fa9$>R?ly6Zik6v}A
ztyP20B*-Vp9>@FR*q6=D-%`!=Qw)@~I<$Nap-^I!Su((UP}(?kVX8Hl&dnX6T`s)w
zo1hkn(Uc!!9W2~vWm)Fp*EBd8>`|tvEr0(G35h$6H~FZ!^^YJl$+p;x9bR&3nBDER
znxdczXdguwweS=W+6hSTL#uT`Mky-@hlQ5RqD9^`OGroSA5mAI<Opi`Y(Nn_qcxRl
zdhl{=8mz04vVznSv}ys7C~e^i%xp%y5Get^D6)PW*o)!?N(-P@CZwzlh4CDnfj|qi
zR}3{t08L!tql?O*jd;-eEEAMzGnwtdO)G;9*P=w=W}HRv%ThOwV(+b5@N#AycH$BK
z{9?kw5k{X_7C!h(ZS7KBZqkXBox2pJ7!r$=X=};o3ygQM$j=&kcMAh;M6B@Tbb<vD
z@rf1@pj?ji)k^RrBSVprx<b_qB3D|_!4b)2hEHvtZu_Djnv(8GC`^hgtyQRGh7hts
za=|FU>YQmv%+UvK7Ne1295-Ch(txtU$ozKljB}QO7QLcc7DU#VRvB{>4M5}@nAYY%
zqlzo?3P$MLc3XrNh!TuZd88L*>V>w4bA?4_pO;PS*&yRrdc%lSupn3n0&5Zp$JAt;
z&_mraKee`ecsJMxp3~JxQiRqE$|-)WQFj2zlne9~4CB@#J3NOeJxGG2hoF{Cx-4>1
zY@)%&*2#zRMqPL|w5%PKbB!gmUJ?{yZjerHT;_6a5GoV{V`QBVO18nf5zoyzRdP{C
zkpNMF&cFnT0tf`bXP(y*VK3g4l(R_>x=vZNbD1CsY>|bH{jsPxxSAS*U}3>O()L1R
zQEsC(Je`(o#lfH@dpeAElZ9cL;Z0#v<pq(-v85g!sm2r<5b_R@t_xHwfd!t&bTW8@
z7TD}%bA-5Mdmnf1w)a~J?4?vJh%z1y8nz5e#`7UW(ixpHMzj@uP%!L_q=w+kyG(17
zflt+MvuK&%#%D-KIUq*5I6O(2&Sbe<uQ285r$8H0g0)1tK30IpVLjPmpOyJ459AT;
z1%dLQc$&6`kY}(^vRG5O!%<cmH;RN5Ot@}9GOChf0n;YHk_E3;lFqEks+3X?R0}97
zIX@ZLLnOio57yhi=*bI)Rqrt7K8z@D{T`;;>k{EFAqBxgV>(e}TNp7yl?}Qo1sGc;
zXcYzJ>&6Im-b3>XCM{GD618)d;fR*9TnuBPkYTX{Mu9{D#nKas3~g$ljirf`*;1OJ
z%4Jy1M!w~og3vfB8R3~3X}K`4C?5w8h*xNvT+5>NM;cQ6t5D)x-O^rLL7nhqktiYP
zB5oN7ec<a#-X&hhqPhlBCs`m*2H_h>O*`j_;O(Zizz2B~$^#P_!63G{;2rb^e%fW`
zRF`y8$1$9M7`-CrLWJD#Ac<oiI4dC-jwXk&P{>mxo7i55G`LPr0pE2T!^lXoP)rGE
zGRtd^MmpgccM0LVU6B*H+VRv!EvG<Eqc=o#JtYNdBXL!p)h<D8;k>Yt;nu`r7XZ_y
z;S@}nY!YC*f-sJSRgFvC#M`ABA&nrvouv^CRqR}VYjh4Rl%G+;;Z5XAmE^AtK}t;o
zwO7hTo7^%o*eYDwsxPliK)^hh5gi7;y#yIU<7L8w@of_ZOSC&ziv_xHz11KVD;cws
zvcpm`T7mN^WX&RNB7)Kh+ikiq(ClI6DvS!s3jzm)sh7zZZGH~9i!;-dv>+%hhiKkc
znkr>Ky5=EE6C}Hv4A(eeLzceeruCi(%i<n|dFE$`JG0DBxv6|zvw!qME_%c@V;b{S
zmCU^!8!|>kVEyNtzBCMPfw<1$^AYs}2&ZGr7T38#0~zg`4T+)4{Npoj1f$(m(XDci
z*9KS#RyC{Kz=$!7%bFQC^Kjl1hBG&jBEOd_UF=H&=lFB}lE*XW`#pTdGuv5p)16(;
zg;BOuPat9$u82sQVtT2j@tiHrt6iCQ-GZIDTaY{=A7l?FS!6F5IT^R@t6pYh+nP<>
zE7@7bbE&$~JgEjAi|q2x_ip1$K4wdDH!~C5*i=@BP+!FhE@nyRN3JBXw^XW^)%~(^
ztk7%$h0s}x(@f?fxlrcu<*t>v#_e+Ve2#LA&(Q_iLgqf#x|3B#TzSmHeU;DpPID^;
zMq!OfaWJ^@hznz*p?n|D0l9Yut{7ICbIJ~37ndt89a!f2cY}@*l>N>RHIN$O_@3b=
z#?)xrlPBEP-66W$=?lYj%HuiB&F+|(e_GZb{~_!~6MG$WiibMWom@#6;~C2@;GSuC
zhK<oZ2=fQOIgyI<`OME;4V}RM?!L*8W-i;ZGN6uVM%+jm-N?gPT+MyL_;YwIgaBKU
zMI+qoVEPK7JpJdM7V>H)ugj!ryY7X(@o`Y;Xf{#5lR5dd@Ef2_cZc%T5A*wtfv=4q
z%nhuLes_3eVq_$5&P(D{lLxX+g~u>GXn<eWsgq{UnqA5BOvf|l24467C@szPe&0la
zTDd%xRI-Ud?)o6`(XD>&dp}p#+&bu9s>GjQoPRt77ryql`R)?WJo|d)nf<O@GG4`|
z@@afWvr#T3%{=mQS?LQm()%ab7NqIW#XGamIX{Gm%sA+p=WleWyRwt^4!D?G$~4=+
z{Js%x^zqVG%*z|N!!n$8#w|4$(VJ_^{WGr};PU#++5TF+6S7j)ta0v}4@}?i@rMR}
zbxZ$0Klt+_zc=-@5AT_K*8_V_zV}}*_+T^n?p<G-df;_W?S9}hKmOQ?ySCo{#-~TV
zvG1&B#~&EFGh6+K>h-IhZhZ3-_x9elZ+c(p+)E$2e*LA7fAp>gA9>=A`@d5;>C!L1
z?}kgCf8@D;um88ZKL5g=lWTYFIc4>hncYv-7k>2Ld%tk<`3EL$cz8?WeG9j&`RM$f
z-+rd~@jb`Cv~KI|^KV$)z3`h4?Ah}EJtx0y=!Vr7Rkz-L(TY1Cyyc(v-?QbR8~*W4
z`3<Yz^tGw!p;fm{R}S9rZ<jxK?&`}&zW2GxzkKk%$_t&>-u#Q}uRU+e<saB`&9hV2
z&%9y7GqU%%CA9pe51fAX7vJ)S-`;uGyAC|``B(P8;TOO9^5_5L^3T8Vul^TdZyy*{
zaW4MPIhm{{VZkM?7?F#UxM0A5!J?v~PSypN7%`-15l|P3iWpwBzKb}CD~(8P^dd!T
zHCj}(fYbt7YbAQQEk&!=Ds6p1Y_%6HQ189IwIX~!&zz0g`}^bfBxladGtWHFGta!9
zIWuRsJ@AK5_doi?wV&_Xt8UreIjwyAiVZ{dZG7zceQSTX`~1cK`;Uo>H!a$;ckD@f
zPCs@3>f2trVfAgB#_d_VY4`T0kG}rikN!4y`-gij-1qBKx4yXf=(&3?KJWg0r@!&*
z?Y}(fhkM?=^2vS=?QWd<&@FARZ$9Po4|a`RIB)NoD;Ditb;Z7SzZmoDS9ec+Z2#^7
zYxfTuzh~Fp%jf-V#Kd{4?;0>~S4Hcu-uy@9!u|g^Z2K4c7rgkz^TX%;?c|BO_uoG8
zrTglWd+w_k)V6>3^&gz~qlqtGbwm2^S6!QafB)`&_SBh?<ahWHe4paH^KRVtL~!Z8
z^+)|^-_p~5KK7)kE&tqj!1IrPdg@Oe{mwxhk3LcHw|$=-chL3~CqFzmc~JW^$DMWe
zz7Iy6H(>F>AH2Buuow4ymJjy4)bFUZOAbpsv*f^2{<-Ij^S1x;`n}sfIwQ6HqX|>?
zy>#Hw^EMy9b<f4OE`H{}`aZXP?EL9_-o5{$iH}G9ranIRv}ZOS^}?QA*H+Ehx20~;
zzTejEd$;DJm-dbbfAaaTL3{RJIB3tVG1c?_eo129t_gGIzx)3A-@WHpwRis`&D+0t
ztM0`wo^6=-x61}Rw*QvtpWoM4zxZ}t;)VSirmQ{pr!zh{Zba_;*R8tf@B8m;<}}yu
z<=o4HyOi2@?(JEfS~o74p7Pq>KfUtWM}PXEz3#~W>3iZ6*PZw1(XF38dg`O!JwNla
zKW|_8i$^9dzcVv&`Dbd|+Q%>6_DuDH#V*nM;<8gGx2}Esh}N}-{bg}@{QDi@Gjs3N
zb>jxBF*61)edhh`OCMU@vHs9+Kev9`!&}|FV2K*?pRJ33Qn);E_mzq6MN_lx)bc%_
zT@&rO<_kKlFBZ;nnYxRwsmWe^&4_GncUx2Qnz4hM9~soz{7!!0%;`5AH*@lctLi_!
zu)6-!TL!-J$X(U{^L}yaOTYi3>TiF@kN=OYbDJLCdO}X}mU)A{GZ&3WUQ}DC)`LDs
zkDioGFZ|u1<oL3Re;%;J4nO{Z;lq!f`h2oF+kSq-1>F;uUv^8sJEApD9Un&9My|c;
zSLtIm-&Q;<yM5gu%~KzJ(A<`2uU!%jd~Dm=bj`gwnzemtxOwo>s{T_S)puss_YIr$
z<C#iVQ#)8Cv#lN9858PJhm2qOoh2RXFIc?iv(%tjZj>&#ow_v~Kl0**JH{l}3`?oq
z*QEAblTJ6kGb}xGazlRR^ciz5Ubwrh{?qc*E4yEd{%6e#)y?-$pZfjZ4-5ZmYewI+
zwdTa+r$0)cxLT=;MqW`?JLiPfpZp=I>NDoUdR`0AJLPv7dexU_G@2<jx0^v@{#270
zUcKu8GiGy;dQC4&{b_S?%!TvHkEv*GPcNC$bHXhPpBvTP@!^F#qp9PrN%oub<~%*~
zhDaZ{J92&JYddOx$Gb<=yT3+HEy<0oxNY<C70t7b`?e_#`#jRaRwdOp78h%expnjE
z6Ncsc9Xh8z9CW|27yj<-3Dq~8@ND(-_3q$z-d#E5*ac&Uy|W@!@$4#ncB5_{d&uko
zt7oa|rJq@{Sr{?)!O7KkU2(<B75h}zgnhHmS@-UrzoArW;Lhrc?1*ZeU-5FL+YQSY
zHG%v^K7T!dF;g1PW57Pxba$z?@1{)dW;sO@wQo)-yS7~aF4=B6R`di9jLBAv>G-gG
zNZr&UUzlB~X0KJ1_w(aLGgPsDG4D0*SiIw~Mt9NZo0e=2%Wuospn2Bmw;<=&Y-a69
zDtm9SHs8H@Wlj0)enBc3Hr~zo?losuG#qqjdumjhJM#p$YT>X2V}gf2OSLy{(M#XS
zHRle?r&oSx)B0r_ym@zFSj&%FraRTLto#$xrCzN|?M%IQyet$CX~<=FhT1l!`4zqf
zn_9JAsXG5VKjhvqg}7ghew2l{YZ!>eykon%*Rg}8Md>lDZ_FN4RAcI#PF1Qjzqh38
zDspNz<)3}os+}K3>QM_1hG%7sT6I5Z7}xt(C^tF_Z8tp~Z!H^YSt3YU6)?AJ&KY$s
z^fQJi_u~^Y(Udll?%;%Wt8s;0*8cGd*8CSU?|i^S{Z}&`+Q(F;4U(-&eb}awb_LU&
zrAjYgZc!Mj?Ac?qK6|#&EmLf0tK>}2te>KdOas;QJNyP)KWh@4%oXY$ARWB&X{HNY
zGBL}qlsTGG#>sfjh+X9Z!#pLj#CI`mMh%iOTN2=)hKcDV+%b;1l~bW|1O&lI28qg)
zvyfd$-UcU>)#xnqoxD|DBbDkNt)kgEgwa2?5O%~D$WQfBK2(j39GA)w=a?EUVLvu}
z3p{(aR9a<;N>5R0<shYAy{$Y&j#PS3nLkRunMD^X1ju(ia^}a+KvXb^Ieh`~bs_1O
zv1i2URmha*6$>x)c6dd7CW*|stG!=WYw9_?*!-uqBvsG^f0HDPa(O3rB?~`YJV$YG
z%&2DWc|AcXZB;&u9Qr7K7#~@AR8k?24IHHxK~g^QO4#9NtBRK8I}7IVka`bpGl8BK
zZ|925s41Tcu;H>>AYtOn+;T`k^{48=mC2r9_dpGiAdJ<5k&p)o5eQ_aMTJKL5!L_}
zjR7r*LM~hgWxl2gzFK=ek^~yR1}rH;=7Yq0l<M$m6A5V8rV1c>0xCq3cU>BWN<An1
z0c<Dh0*yZ4WS*;ui{s&MxWwE%o~Y3H>2peDVJkFBc(9U(enE8(Vik56;w&-HcyPVx
zAtpVzNa7<duczZKc8CmmBB#OA)Pc3B5LYhmG^l4)w=`*=Pr=Ho<7lyn6}EC&>|`VC
zAhr~?e&O427dr&l0d{5RAtf$$khWz#HTk2}ke7m|_IAkP4OjkL5QZy2zaVwVGjDIb
z`{`GHuBJTtOZlCj7uLQy@0Im$yua_f4>s(+;Ng8QJhknEyO+KG#WNrO?U%b=dhnau
z*KQkm@3O7C>wm|YpZyQN{`Q`2k8WSq^x&?u-+yb@-=CPa|KU$hdgaZnzufiO-@e%W
z*b~#<c&POk8(-VA=G{O2ZSt9GfAIPn4}J6JpS(6_Q`;B2uQ+q<AEs_!|IPRJ|KZXN
zZ4-8HJM)=8G~Kax+CTPPdFjV<UwZE<e&^?(pX~j7#J(>sJ$CL{@11kzqaW|txA*zE
znR7osc>mwuYn`xm^1M&py!7Z<H@tt|-1(oL^ZA}D7j1m=gEg}*c>m2C=6}rZ{9HYp
zj2<dyVAlOj&iq_`bdT=n+@kNeCp)0(_HARbhgN@BP@P@3kFQjzZ!b1<3@fusB6r7%
z<lPO|=oKn>L95Cs#ZdJmp6I{ySD6Z1tWqBo1J|P-RK?`VzIxfgsp8J^=;fY=s07Ca
z34Kh(#FaeiJVa6IjZt}YS&(!yf-ODN1sb!RZ34YzM)1PR|LLqgJt`b%3%a@xsQfrp
zS1j-Du9%Tg(Pc{S*sOL=7}wJiHL61M0zL1e7Co!o>Q~Dz)3XLYt1p_~lb*G*F?8b@
zGtM!?%g4{Ctj$gGRY&rB<rsRp<RqyyC5RgeW$ynyGLEIx{|}h2hl>(0Qq^KleE(PX
zD>46HW?!Rp)M@**uy|3&Ly3PWq+H2kdJ%HBq6pv}@!&NklCuSm?TW+n)~Sr^p_dJt
zX*xLuXCRbkR5^BHm2H$T`};{$CUF(284n?P6eGOzbXM$Eu%L{}GQ3-;SeiSmu30(G
z>&Vk4yI4WWLMHbPYb*SB6t(VAXzpCdCdHT_rP?908DYeGCTbGGt2zj<NgK9Hlw~Y3
z0b%C^YnKlSk(^*cfW|cYLNm>ucw!}jf!=A+G}RZ6m>WSwBFIorAj4=XYBnmPb`X_H
z_0WGuo2^<EC}$_MM5Ym5Hl1n_R?75fMissSAI^4`F{j<B4)l}WL&j<)?~?JU7F@?d
zIr;VALX~>C1yu-*3Zl)^Q#rh>(9~hZp^Bv&BFLTx8V|vAJJS_aOO|MpcUjayJ@(9@
z$8Br)#ZGI57$;O3JY6?Kc?XicGE5m#l(kdBm`>i196cEW)U7JvRDg|0jhQ@H$P8<4
zykoafAS0V8Md0<tY?01>DBVF%>Z~NxAc$2(KX7__W-m(hz!%DpDVI|kiNXT@PQA)u
zk<b{{*@O-V`A^6YDDp@|U9tSu0TS?eX2c|jlTjuoWPtN78Fh|sS~L)un!(dj`VK>N
z8^NVgy8kRs{c^;|W6&z<#?4sLFj|vZ>bCex&>d<M^K(V)kJwIP4zf5H*tB!63iEg=
zH~iiSMQ;H9L8v!3C|Su_=cgzR#!h1E(BAqyLHPN5N}bEyAYG<Awn8QS+b&b^Wow8~
zp|Ma@vlhjj93JFAGQpu1#rZWF3-RY;nFHaW2(#Sspqy15WFgXZ4vZ(0J6Z-+TKHw0
z%c{`2K~gn554nk%V_wP<M3}g&&v66#iz9y62P6t@gc1qiM>*q)75GUR?^7z<kv4T=
z=ai(Wu41AcL@ls%5%f}H#q@#65la9YrDb4_wg`XXFf;X^wpVaaNcO16HYIN<4NMAB
zB?QDZ1|g85j~iqu6F3W%n8*?ju$>tUiLIh01wP*-U?N39OU{Ll=8NYU?kz!WMqZ?q
z3fdPxHBzZAB89hPnt0NZX{#J_y$_Z8!EV@t1)6-7m#i!>5^nJ1;!{x5nOHoQhb(oZ
z@T!nW7=T;M^k4-E(158p&druU4!K5fD^;b`TEK~d(9qzcDrz?Y@`o#BT&5buD<=@>
z8f3oZe07$DF&QXnma0QJ=lS8MgWSvwuFl%n6Jp}{tF4u2%aXW9d$vd5<uh40q(_*T
z5ayfdXMJ|59}YsDBuH9GW662BAxI^l%)-F+Ps$5stA-mz2L&exnI9(51y3sDaDf1$
zQJa(zSw^+8bKF-*qCzf<0*#UjjSsfU)oFRhC%qa=rg*4ZstU7s{*rUy7AH2`9o0?t
zz=}^I97ukJMG$~XNcnbMD*jro6<&;l=;6qdWCzC!3Zo9tgFvBYFJv+$!5|XWV<Xg)
zK2-Pj_N)3g$K$)tjFbu7IL`$taEPxW|5B<xMOZ5viV#StN?rFPa^tdsmwyj|(<PrF
z(#nwjfC0l>6R&egn&qjwvcX!?wJYP3usJ~)G!&jncfi+9Qj(vz&lj=uTmmi?7+*DG
zTS8$uy5XZjH6<^eZWN6?s&`K1`<4p!78q|}d1w?*O&IHIIpMG6oIXPjl|vx7i2$<{
z<3mgVTG30|W2~Xaq9vc-08O9Emqe6V5`_4TGB#!sw@xD|CBlRA^j6CEKURYA5w5vW
zIq_RC*sZosY;PUH;FPeDYpIT`l@=NX@Q;#)c*@Lj6|LjFks*cFRh*BwgcA0Q8Z?Xe
z-JO-E!I=8!$aJXg=a`jR(gK1;E<+(*Fy+g4->8sC5C|}Za@P6W8l~|7T9x%MmWpOY
z$))eput>plgTmxaW%1B!k~}ELe9d+QMKXZ-v(zkdqXLI62PCuF21sUCs^q~{6`_HF
zb*5AC4i0-+(G0^XJ5I&|9^)#sax{{>lu=`al$J4cta;l39bf)S>6EL-%P+)9Hegu8
zp2i^A%0o6Vx&MH8-Ofq~=tH4f4Vi)56-ZIZGdQ0SVaT>hl$E!_)#Oy>fMFt(Ng8<~
zEZLY$f#VZPU=L?9PO4m2>F~vIPO05zi~cGjUAcCWRb&(cb&N?3P`cBlYN%kyW*1@<
zgh4J9aDE2UVL4lCdAnBViI~3GtcBU&oMt(MmxQ#EP}5rSTIC%5ipm9Ynxa#6Fn&#u
ztwvI5hw_@MpmKHwb>UVkrnjPL8NDYEy~BEupCe1J)RFC!(p^Un$(y21se3uqZFS&;
z)>44zjXG?%p+loz;M;eBp`fWZG#8U6{|{)(ijFLb<mIPSWOAG}M>vPB(T=oE1v`*B
zgOwm`%6Ao%9fds*4n>AfA**iMao2^FddLyVgP~_NH59xy>WBn$t9Irh(hIgwQSVnh
zbyCCxtwC2_L3NfJQ|EGjJb;;K2Te!^%28VHyJ}UVhAKy;Cm;5R)-EXpOBO^-k2r~b
z1*JCbrBFlXBdL890>vV+Ux8JQK->#`iDm5)c5yH#H%TlYuJvANC$YBTg7q#Ahftbm
zkph_7_QV6Gc7%n}ix;Pc3uv+aCbR<70qPdXqo5sMz}R8A1HKoM*tqOUmXdG`AWW~n
z_wI##xdCAStyN-T<?s|Fq{5sx0kt&n8hSmgkMgoBMQNYO$eX*HD8pY$-4+w!dcAz+
zyaeP}$}}DvC6bh1gWdpr%a>rq=eP`)l--D$65DuGRI(fiU!QM$fY%A4fNZwg1jC8o
z4K=wzl4^&a+G0S)z)3^&s_0?DKtB^eYXi%q$Lnc~B~^W@E>A>SM`%r-6#o=KY<yu7
z=t`lJ31kLx3vCHXwkG6!4<0no@L)pA0%Or7vW{58<sqj`0;K7NfW($MtD%(iT0*ur
zgZKqPalBd*r?(7IwRDNePC>&v>_#ms)muyDVonMeIX)fROoCbI17fhkF4$b_xLrmX
z>7jTP&f^Wq1tMk3Pz5mEk#W=lQNgMq!qtg3o`s+V_(3`FK^&<0NTx~FNQjR>pb_0$
zsko$UjW<?2)(8y+L6;2k(3Pa)FJ+&MltbZ26d}RKqb>5m3D`JEAQ*vE(MPIUv7%-X
z!egD-ST0nIF$4`1#MhJ%#8T6(NRCH6$*)Kh3DS>~4-kMutjLqzPD12Of+0^%h9L{D
z2_?#CHH?6)77G%Z_)*a*Rcon27At2&2&C{ATIFKe*=bV5|1pBTFOFqAA{#<4u-W*V
zs?EXN#k{;e;5|(T!)p-6azz86zFpkB@YRMY=!Jr@TvA)TBpDVp2v<skcWpN#?jd+$
zHh4&a--^!&ajX=*mh;9W!te)>Q&kJIzz_hWHna;hc)6%0{w}D10(aak7a&#BLx1na
zI^mTTEUA5TYOx6ePe=KayjK}31USBo#7~+K$Ch{sA|Z~nXCRm8Rx+_{B!v<t3?I;2
z@slK#jhwGhy~&Nx0X}Sa&<rUYLQ-0i#~E<&N=hjH#Tu~m#4z<45M{!+;b)1kgur;P
zaX9N-91cTi3B()ET3O-#6}k5sp(ugn&I#t&NWDnzp_JpJ_xk+x8j$K;=ZK4K5g4i2
zq6pcJa|oe?B~K*<jl{_%Vc{b=m%Q|X(8hVE^$S`MjBu_OO{Ca?8IuQ#%MjnopL)yw
zmN=@{)h^CDaz%WHr0{X25xgjYm>rXWSka<1T??KYz=3RBN!6bY7wBe=DR<?RlN99L
zXqghwlC7zv15G-K_F&n9Q(~k}D2<D~I@FbDd{?GSDdc6_QUHPCEj<$%vTFini&Di6
zcs^o*D<Jn;#;&-|^QmA#(p<U6${Im{G5oYAT8rWi$ARNR|J;C)Ts7BwFOF~7RA=eR
zObHqEz_7?<2E|A#T_)jDBslABX*_>zp%9=5fk0fVU?mF}0O80v?-l(W708n?4tgZ%
zV=&xe6f0eV`q~&>YAhgYB}P%+Igt@V7dNkkmcGe)`EiU_G?YgM4;lr$(o*)2W(+sE
z{08-m$cGprG?XeRx&;o5)K1|c48+hv6~mY9!P_6lW=k=W7t7_%YVZKk>KrrcTKx0|
z-Q1L{eRxGm*`I>&Bfv}HS}y9Hkf{t;Y=?OB@BxC9vOIK;_;`{t{%&!LNRnZyK`^mV
z4FbOeOI8q50wa1l<3oZqwui8!vxFo$_VyzKUO;HPS;Ck?f<hzEF8*RzXC>f7dugvI
z6L-GKIFf6L^k5|~+Ck+X%VOTBAA^w_an5q5|0P|6DC9~EKzOesTH=X`Gg*rgapN$M
zcT2SLnUUEPVEE%(CE^8)$bb&l4{ox>T4@Ik&?X~jzC9WDVbn1n77kXlvmm;`#aNz=
zyk8y%jTIv2x%+&?F-hJ!NTvt{Tufj*_}|}peuMX$7}e{_lVen>yk379O1(UJvW{8F
zWDS6uMzlbUIR133kMV2a5cFpho+VL4Qnw_||E`+!ZI(a)PwS=l(!ea;KE2pTFzD>V
z-jNKFKX61~2<C)ADJ?k9AVAf~2ZYv$Ex!gvEU2}Ci>L9AnXwd4)m7^2R8E9QTe701
z^=v#Vrn^@9I+-tvSv{LfY+GRwaOT;F2O6ITPb(}W<f*M??*S!^=6t_XXh{)Df6u>A
zNtT=hB#&`eV^3b>dkC%b<EfAd&~q^}{#3q8??DpfN`CmjOWLh9UO2l42uM<{*r=iw
zaWdCZaE6prtgovj#5=-*6TMuWauOyju|9XuqP#DBT1PDjctgNwCE&dKHOG>Pm_Nyh
zZt0Cfy2CFVCEizh8C2@zaiIfDjE5@LIE+Um3%*fOlAhs1Iycb==#t$H)-#hxz;a1f
zAfw*15~czd@jGzV(;%I70O<JaPz_bpf_G98CP9urzQo_a1GX|IHbaTO;OTs{xV}dh
zkB0~yfrR9awrf<_sH~qLstgNAe5N99RuY@4&gno0rB9m)C&{q<yZ{Q&CV{mtvt;uN
z@i`|h0N#&l(&hp#$7KcE3-mD7V?81iR~oKMN)g0#(q?Gp%-#uGWJXSB5$>NZ1XV6p
z71|QLGBEKUO=Fb+Ttq5gI=%6vm2ez%_+nlv<%G^5uR)OJ%OP2&Afb^A2wJ*o&reuO
zjK9Z`%5ir-AK+sNy*JX+b;h{R`N^y>Fw)c*PFtv}q?YDeCH;VflXUBNk*8grps<J)
z*Gj^GCoKu8HpHHUh=3eeOhrDzT9SzBk_AJ!pm0e*yg+E2zklUOIkt@JwNES$Jxic-
zy*^k9+G0Hc(V>jXayf`(6vB&ai|eF|@aGeiF5nev!__W|K`7xEW4VVuslg|Ck#G#0
zU2(?qQ(aYGR!#$nR6&vC{M;ZPM5Vd95Yr?O0S{NB{4nK(N&iL)Tj^qkq6cqO0f{!^
zp_|h!U+E$k@*0=E@0sHK%9np!&Jyd_0no;HCJk{t0$(PWfTc|QB1b^J1b|KgRy>T`
zc?()gwX+cMKE_ue14RjhUJeq7#e+C;Hjd&Ahxg<}lFwv3Q;NmOj6v`KNsaYBDd)Yb
z@Hz>4M?3(=tc`uKOPvfwq_T0?TS&ZOsjze@I;2uh;2gMEA3S83meng?l1QADyXRn>
zf3M^Pl*o*TOS(8-$N-V^uizx;ZHH~e50NymUdfT=DJHhImuiUV5ULpWwa(ClEH(jB
z){c8aNtpO!u-rV~K#eitkLVw`147I1Q9EwJxGv_7FMe(>`gDd+uU@F=(~_{nLTKe_
z#~AS#WpT6O^&kQ;h!IJ(;*ZfKH;^+uFPC~)Lpo}v*wS*fatW|*&R=c5qfTX-2wOfl
z*B*siGErzct$&WnfmGHRz6Ge|p+dLoqG~Y8=L?HaE7<^GjJk>Z1;V3(`E97fgYZ`k
zk_W${&v}tNB{VON>Qpfm6}_^ovPxlWrh$ZwNvBRPuaQ@H#biZ;D(BMzHrk=7>sFTA
zrT5L1sU)9@=xGQCSlFeqY?wg%;uPAaDR%{S1Llrp+Sa8UY?(nY?iWJEUpgh<<_m(Z
zq)SL;cl49x!5HoOb<@9+1BPFtb`0v4&7WGTCUa2hhVfOOaELM{@OHn2uc8;|1zmKI
zn#sCCqiSsWxlDm7IMR}lv7N&>Wf@B!l1eDPW@%)4ujy~~0$xPeAu5xaL3t%vhmVjs
zQyr)3YE@Vk248+3V-7rIW-|c`<;i4CE#IdNt5TCX-y}=q!T36my2HYnm+P;9Q&QHH
znP|=cjX9l5JGyWd_YdarQob}bKF0@cL(S4g=o}TnrX6<DO9QdEVv_~qVWel3whMKu
zPRhy#sqin3&wwfA^5x}xnA0saK^?NJcK#WYcSkj32*L8wjPgt!rMg`YolF%Y8J$+@
za<*DviXu_@+k<XYW}s#O3)Ljs#XFR2fZCzRYMlHb<r0RK)&||~LU<;Us<{SLQxo{M
zT$#$hECV0*QMyRqTIBT^8Hs9b6gpMTi6x1g8LB%{H7@gQ)tKMO&wqxhJ=FmJGrwW-
z%AKtiGm&qoH0c#VxpiSGG&OYt8=`XEQ61=KNk5n&p(0S)l_`4}@6qVK!b&Bk4f4m5
zpK!=Xg#~0x%h&Ls5H^`)rzkx-3~h3TDzj+Rs!V9gcw<&WIu)8Q&{ZZHN=8VPHLP2N
zwR$GXGQ6v7ku3zUAKo<Qh2{3R`uF8b$c<MqBi7Zg<Tut`HvPDY8E5zX%^l4%DqC%0
z>8R$1?x{)6n39Svn%HXZxUD?5d}&SdLlvzn-fRB-#BIwngEp?rteR_E$Bbw@D}PV1
ze*CM;&G|#loL0GE;e=>IYF+YWHF|aClKJ)Pljoj%?sHF-f0o|ZcV*j|x2@NgjCi!U
zYQmM-jR&qD*>c$W^0}kOomW+JP}6|E8xNR!_{PNCzO&CCJmIJ3RXx96&pqJI<7$pR
zdE(UJ7fx(FZP{_d?mK?y@b3*Fe8ZX7oqo{hBMv+^G4#|C<ENc;;rMShO-^LS9o{ke
z$YW>z_QVmh&T70)XU<>v!guV#7dA?M-AnZA8=t&*(8eeKGX2yo*9|&#%bezmZ~L$2
zi|;Muem#9>?$>Yb%zyGiqWP2NDaptC?rnbjd;fg#iES5df8zYzPw$`gp4tEI?u9?y
zwXbbM+q~wFZ#<^?<4=z{aQ)<_e(M)Dt^VkeJ?lRl*H&@E_9y>s_q~_=+rqYO<qH>X
zd+e0yr#<#e?zFSsn>YE43orWUq>r1AKlS7015Vy>c-@F0hu00*KJoAawvRvW`y1Z6
z`iC3dx^no>7fn6-$wiaqf4u10MIX;Q;qc?<opj*w^S&|v`Wr8wJO75uN1S}s@gq*Y
z==ifnjURR6vEwhh=+vtYxq9F+hunDe=u_rjJ?omu(_eU8oxk}Q$?v(dsJ9!(TsM7V
z!@TLIHr_b>)Cr4{7xz1=`QpT;+^=7Ku=&5Hugrfk@$KeMesxpx<2Qe&dHwgUCa;%n
z|IW6{M(=;OY1QYmvI|en%$s%c$~_bR`}a?t|M9e^4(z{hOXAMSTULG)v_1LJu-zlR
zSUzp^7t0Slbo%IY-@TaukKH@DaqYdi)5g!ZD0jxk^Cq8g*|@~1SB@KS^0BAS9QMTN
z=AiB42OqevY0$3^KJUag?mVyI=qHEvAMwkXRdYWcUcKnGky8%&#zj@%KYnJ_{2OOn
zK7Y}Lmk+5vXYi>fX9q7jHrxM#E5|onJh1lgtB;;}{EZhZm_6@;%+Z5B?EE$*TPf#a
z^2;gTYl=rrx!et@KBn`EbN;#XV*7B*?Bqco&T2kn)qBZ>o%7UyC0FDZt3TxzujooX
z+_|vd8!O+-FD|~6OZ?`)qV)3%iyM|rnf}hQb0@#|$EPN~{b7UtXqHKiZaXR2aOSkm
zpZ@mT5l_ER=(}d}%)V>Ry{_*^72%lQWNq1pbL;`{&KW;q(3Z@S4V4R0qoSz?-Jcvg
z<~M`V2M#H39sB3Lm!I(G<k%%YO*T~QS~Tb4|2{ukcy+oxa7c4@<iV$;zJ1S$Ro`B^
zu&Qk5!s`l0U!<!>ol|?zvAK~$`nTnj>g<rbUHvhgPM<3-BwsVmJ;yCLcwP6*!B2J9
zCJ*`Sv*v@k>ylI45z+L{EAxw^)AB_%*gmWt*AM^kueq@EJNb@hFI5Bn<Jl<P@zV5n
zR(vw~y_Zw{_J8=~#Lv60O^#N>_2`-#i^sOV-8pK--snfs)Zj-!BDrA3_`V<VUEsn@
z+i$_l+>k*%vqs$0HM6Qcbxf+i8rtxFOL@a3`RvL6Q*q*$|A~&d>8C1v>rYe1%={?N
zDVZqSw>;H!;LR1)m)<gZz@<Mbv;_YsRF~~F*{X(?zgLa2ZAXqO==x(D{O|bu^){sn
zeHPTr>{EE)g|hlrJLTg)wb32)f2!t+Xn~nkzu>4sXZOe&*By?YZ3h&0+G>*@A1#P-
zxm;A!SLg39*IRZ4sr=5Ru5wam`;upC+B+}5*mfPGF4EaVqO&LAI;sy?*HJw(6TRHF
zY|G^AvMqzkChMtH!Gc`h;+Bj07FR{O!3-!LdhKxs{$O@y#9b?{8+F&5IbnJAJABb?
z!K}xli--L9po`3m0aNLvTS60U=7j6E+9StDwFAc4l>;ii@xW<S{Rh-88l}xbNCqi$
zWK-iV`sOXXmx)sO+UnHQAw_0^PMIQ|aSz!`)h$r#>Sn2rh8Maos;%iXebPO4FdyJZ
zWvmOX@aHmD1<DSqQ1<<bRL>(zT}Mx6d!p5}>r>lobV@jWDf6;oP?<@j`<XC3k`INp
zrE^_2&Gv>@m!|uxEzjy=X0y)BN+;K^ijof;yR-b5hR@5Z3p1-LdKNIsEy!y1P9b4u
z4oRG6Opeil-;OaEoehuWaDTaNNsJC`ch$H_-KQtNnc|E6x}kxmi<VY1Bv&<^TpV>Y
z`RlJ|Ri`Ewlrk?flWF1p3NO%z)s8tsv5`kt9<JdnW4Lj|bE%%b41V0TVr&hRIvd|~
z!Vv@Cnb?T>9}Obhu9Ukua6Fo;=#?@Zy-D2n;MUB%?*VZ4FzmgUXaMgj*9BeCs>odP
zr#{_gr)Hj0!R&-@9q(Y?Y|-KYp6BmS#p)i`GoB4qcBWx`Mm58h%s(5IuhoX<R_$t;
z9p>2QV-hCM@LJizq@sW>{&#$q(;ihg&`?9k6E|hFQ&>-#9xiY)KdXbO2j_FB4YSlx
z5JQ-mjZ^X%=lmLt{O%xAM;^kQKd-V>X~&F4QMmdA?wh#?6UPop2m|<6@J<|@;Ujiz
z!BLjEwIMvEn<s*oiC+LMW|W6kv2n_Ry9pfk68Kjssf^5Z$bwasJ}OJBTrCvO0y)z&
zxkxJB#v)Ykl;dpKJuAS2NW=~q167R#8!Ve%LzJ!#Bkef%19=h~T6$&|Ngm^ODud#u
zwJ;)))&6^8Dl*K^ND4~q2c-CR3gWr9gpQf4k8DYz2aGgPqIiGN$S5a4s~Q?CPhobD
zS4Z?C4RTrT<;MIM_Tbp{;}^1diIhrr$Q0MJj`SIFrswT<d^kiCM0tBTFmgpq(7455
zMWB)SxQ}y!MIqEJJ#z}N_IgTGQ5>NZ;c*huYwbmQ6h2W!;!E{J%+#nLfzl@tg~X_J
z1mP~qAj6kS7T!9b9!h$l5fb)G7<8010IC@A?#nGT5-(VJ=E)+Ox)DQ}lhX1PCPrv<
zXi%q>Sca110B0qR?=f&0$)hZl2{+z(IeZS)xpi`(pGA_z*TJ=z3x!m~f+(xjPJ#uM
z#-*`JdVERj5J|uU5+q)DWQeyCjKOfL6>k}(O-=N<5o8RMl~+i<TkThIiC1!_=cf`O
z0ibREgNvF!cx&Rl&$O;l*9`w<+ut92CBOF7McXz`d*qWVhrhLN{)4T}YbVdSclqnP
zpSk*|JKOd@@yhFKCqMf7#-`nw-~ZyZxtl(I<Ly1?tiAW6rU&b<e*djAPrUQ>{ZCx=
zxBK2~dT_{V@4tHH+B;u-dt>XSXFi^{X2chde00XX*Y>=zvGtKnXV2M``C`r9m!5fR
z-oLMJePsWqAN=y@OLkv%=~J)HyKm#P_n$a>&W8CnzIWAG`zO!2@3q%QZ2I`pW9R?<
z!E-*}G<nX?o@knX^kw|c&;AF`*}wms;TtzJ9XaI6M{byV;}fm>AHM3SjbAh!IrKY^
zoIm&I4cF&pNiJQjoPjB4oW)@I96v(aSl&H6$H|0#A-{kd?g*0|J1V0D>j%rtw`Z?c
zSzF$d#jZ1w>7wa3i;a8_(lcdluc=5c)_uEFvD{IX#iFUt6oWn+bYtHJ?IOKW1%c~~
z(uHLDX}(#|eRG!^9j+?NToLst%<6lnQJqJoi({xj(E;m>4wqRIwU?`=o7If6Ax0hD
zpi{#(SW|JB9&+Hh>HY`)E}a@Oq;XKo5Pk^uU=<v(o_e3LDN|!irjKbHGMcfeiskdF
zhRX0*mQm_$T<6KA<aej9X}++fZhZ+R_|p5O$9?JZp8pf1ky&c9k+`oV1|<SZtgXcU
z|AYG%64H8x7OeRy=4;x1g%qEUkcI_hxsuWq@<c4>MpAEpke-3TKs#=<IrjaHr){u-
zkfg(v06X&fS7;h(m2$Q;8rbR;aaKyKm2&(^>rMDHu|ts&Aq&Pi*va8h`m1*7156R}
zz{)sHcj9nF9wQ*bJkO$$%E@X7>UKq{-s0)atksSs5W-Vv@OT(7hoFPaE)!Y44-yl*
zu#3@D6Okb#;E0sFSg%7nu}q_|NXh9I?prusLnl(F_@##)#nMfN1r%kZ!%Hd_r1(7|
z(#pWdd_=Z5v3yswtv+po*Sy;L&Pl7LI_#)}FeS2LU^tP!rHZ5nql*ornJQ!G)WFv&
zMnR|hi~bP#uh^>&eqWij`#ghXZF?43F)xcDTBPiL%;{^NBgf4McUVzI3~$nV$#9TT
zqYOE7@}9i^;xG)YQp!3~jgce(BOF0T2{V3>WxUFAgB>HJfJH0=wr7t~Jx-WdeEi6S
zY7v7NA(DiYy&-}?r=;MLA04z}V1S$Ri${#A0I}76{jre%pH!3-5I6W6+{i$IELjPA
z!Qx9h9K@+$v=)i*Bwf4G(PSwrpiUft92>?NYPt~*3HGzvaehG32m|H`)!m*i@2QmP
zK}HCjGQzejv`iB)BBqnnDJftn0zXXpHV{BrNvynJ!I4yeBuT6z$fN=S53toX_Oc%m
zjel1khcq3i#8@VgQCEz!IXHQZODzrVFtSd$9C$}al2pOQDbv4`u!j`#NYMk0=pw1S
z=D5Cs6HN-q4r`J%!iRt3vARak)C79tls(1^ftq;XWw?Zs@!bbrt5yj;6yjQ_Qre|-
zL4v9!u}t1?LLE?Q4vEg=OAY}vvl1dbBtYz{GB48cyHeJpx@f-A53xe0(4~$h!>xkG
zALbbMjnYL5L*DAZF`%hAhg9|>`_hQiB+p!dLsqB?6kR1#4zrkcCt64zL`6!~c`v2J
zH-E;X4lG&PQ?<renU;8+aVoK}`qMPRQudYy1tjCaN-$B%pBdn{vr(I7Zk$1^RD)ik
zw0M*ellc}9I?K9d51|yO6dH3g1fhXjOTr-!<{|(J8rAT)Dnr32>}NoZtfPh0V5UY3
zpcKIHY(Elw$^~%+a8BZA5IL1F4Gxu6oh-?U?L>%l#%K*tp-C?|jb(H|zmOHYMD*GU
z>F|Zbv;<+d!OQ+_Wg)^3qzc`N@&ag8#8O;kac_tbEc}QAr`m;$3oZ622USX;QN|D<
z8VCn&tu)RW)DZv~3ewm>;w6<A9?@qNh!6<?@A=VKs~(;X$hTAig_c!TNQ_fiPs+Ox
zQG}K6<<Q)u#&$`^rjF3#L;*`@4;h1u=pko9L>3qseO!=gP>O%ArdI;L<Dyb_@cx;V
zZ0pg~SDBr9Z5h`boh6-6r&U$_1VRD@d}c`qhz-Jaiwq;dz&2*6U5+wskudw&jqov@
z8qM)od6*G7(t$hvJg*dC`d6Jk0_`m1Av+O#ZF1Vdg?KVWdeoBI3{Qpt{_)G007SRX
z$cUtatrWdvK>)oGfJU3U!8xjv{GP3JVSo`=)RCKSij<OkK0Xz6OL|?Dm`=WaOWSE;
zY>=_F+K~sr3-ekfos<ujaMVS^SRC>TuvS!%v9Lj`lrsH|R?HRn4KoqkV!f?7^nf6)
zR5h+J;W9Bx{68B7MotbRD87zSVOr>G8>M_@FbGxA@ZyrkdJ4J4TdhAVAj&D#qw(?c
zlu)v+rHYoP64?Nd3KPUw11CaZ6usuG_(>)`n3dwGiySpwLpL-epJ+<CN*!hMLZ})=
zI?$kQCeN^^4UYzQXo|%gD5+J>t6&<seTF)6ywO5H8OihkR%TzY)eam!PP~KxJp++8
zWwh9#szM}yqz;y;QH=;_Q3n|Vg08XBaR&lpJ1jN}l+N{V*i>HLU=;b3LXFa@)6krZ
z0w{k&%~_S8YIRH7s-UX5aB(6$Ur~)XHYqtG^Ex$3g~coZgI;t2VX5s>xPTGIs!YCt
zee_i%qHDuVtA-+Gw)~C{zx!h|1=7(pEio;I$;LpkA@4E)gV7fAZm%-T9!YR=SVPtX
z&y+Qs;_^bH^l^^r<3imnA)_8}QWSyefu~gEmKOSx7Dr_@te@a8|79pRhy#lVjnsf*
z7cY;}Dp5<M70a4bt{~s)pQ*Es2M(jMoh@Qt3*#{<tQeZ5)YnvvTA_+HB+-e4QXL!{
zZd4&bsuuF87qqToC5@DMjE($&r>j`g^v||Z{~T?F`qHQ}Btj>hWA9Fd%GIbsBk8e0
zCsb+p$Vf4is>aXvIu#P9hOaZvBKe!**X7D0P>%bJlYSq~R6k2abh<8h8G4$QcGME%
zD(JsaHb5zprP|lkNqe%2H-}U;v$&<Y#?l#iuCB}|W1m%%D-2T;t!&f~<y&hRkz{Z>
zqJkIlRY`_&6wPqiyg@c&*+D9~oZL`6mO*m}r2vh;{JD`Qii9F$b5oAC$jy&{(!zYM
zOT^H4==83^t&8V@%#VDW1r>@ze~u%=2OwS#)L&O(g{eVVPtZG2{E9HJ=#i4fNzO;*
zzG7iX1PkF<QbtBq14=+pvB(Y|7DS_VC0vO>Q7{4+#7I*H5=lxHzIh+QG2-!#cqq6!
zxf_Z|9ULhZx?mhNN^gw`q>B;|zLFIqVHi>XCCOH1P!jEH1<fZ;AP9iYHI9Tr7^+5b
zfOHhE0m4vnW%v`m;y|j>axO%^pj47i(dwQ!`$~0pgGYhbF}-LWLFnJ*2?8ND=H`i@
zqZWz~B;>{CGbtX2KoLtXO#L;2=+7?-Y1K^w6=r_5M>OIYR<c}c6<U!*a2Y`Z+Tmal
zdKLkc?FE^;)fpsvv4U-+_Cq2<5$lC}Z|pSK_%1gul`0M?jjG*J8|dXdR`k|ZTp3DZ
z1CYg%TtVY^h?S%!BB_h(s}b!<Ym5n7Wbjb6@YfA>qb;?XcHamJ87XS1#VZtF+Bf#V
z&>O%{{GcHukf#qTft20B-}eDJ0D!Rk1Yo?(7Bl5hmB&(KkUIwxd4v@pr-INZ9~kri
z#T+D1>V8&G$%BEUE2DY@ZN(`;i*yDl=}UAu{aUORsV(%~LIVqO<JIBaxL_pGd%Tcj
z$Wv}_xk$0}^|L+sl)4bfl_}l1k(AP~u(PywCy$|Em;<0a>H}6BphlT|l~}-|u`vll
zLY50KAj+-uMJQ+qH-d_@>EmS%^feIu5n%-tI2<hkRi!UVXNd?UJdlHyDt>@QZXypI
z<G13ujA@r>4R}Ja3bO|vsPfi<-;aL*w!PGWiQWd84jdq7MdDH+Bce)d((y4*WxHtc
z-k)|T1GrLaNU5R(;pM>@mOpxX7m)!woq(BW1Q_q)cxH|P0WjXh@UDSTSTOXXV%tvd
z6@E~VF)!PQ0+a}}Qu*K<Cr1*%92htD(>ip*>nRj*oecvU$IF<57I1~1!<AZVN@T{f
zlyJyol1Np>1y^6tN`5uai|Aq{bOss-7m|n4e~M0xam6GAz>B*hPL|R=xYAvCIve<q
zFytA`2Wa%9Vd(c_tdB9c!rKG6=<Q>K#+2+<ka9enOISf{$(fT7{`h+pN;`rA)Gcak
zWXOXDXPv)~7Z)pT_96DWpamK85NoR9b_%AQtH33At8oCzBW#SlUw1?M^-#$#R`qE~
z6N`u{EL&D2`Z;u#KGmBQGUNU9*WB|ur7ic^9?Wd<$LRws6Efw)@nA_0h;B?S1+0G@
z!o%FzL6(a3F3}4`ynZDmDLlznTy>1ZSaC=tmkp%;NCyjAvOzRIuL-{zyk#DtG^-Wn
zUm80a8sZv7DLe%<3Ai^Z4-^YyCDup{e+L9-f=Usj;yY%svUa4<8swI`=K!0aW|;Rp
z<QWbO>WC935nmO*hh1v7r7B^-#zy=aUBGgW0GaXkuN-0ZC60U$E^)7=f8b5tR|r4T
z@R8QrD>aO?5|;F0KNqJA^7w(2^EdAZiI_g7i1De8-moNQ$biWA%buT;3|pZO40Xwo
zb5o*E83T?`Z+bjDA1KFam$jDhj=oJ&8YMQ9UR?OHz)Q#qn(`rD<dlH%NYsl#67lL+
zMg;ME16R2D1X3H}>WORd0u08=FAoWo5Qb8g2l-Z~iY>|+Ls&Q=+*;qn@W()<cMZ;Y
zMZuKLbvWTO#8Wt#qz)BLVlaNv>f(S%s}nE$GO>?<Mvg$~EACzv(=sjj0^;zOwMJoE
zrR3sK9hZ*L#_H4(=-|@c^(&{2pr?HRSNc9DDgY%}R9?rdL`I>KJ&8BOOQ^Tc!3)PQ
zFyc`;?}`*@w_ZmRwJMYVd=WV-$>A&*0n0#2loP+<vZ($waPScjr0b=_UunD+F>&aL
zbeG)XQ;vB46+BZZ%NOO{i5SNDI~k-sncA-lT_ICf6UW1nc1ea*M+sv*DF`PNrGoG{
z$*&bv`K!zjh)pGTEd-9s`pe*A2dCnGT*q1G=4lLfz>k3;35_x2JcxFHgvNhy4P$zH
ziWPF;4EM=eaP&~50q^7EB)Aku4`wTZHt}4DALWD)hQb5z@_Ng#8-(TZE;KY>;;r=E
zy-+D0H~_Z9!}?IKQ&)-={?-UKu8a;@5{!$@=N(;RPM`&nB2xMhu_+K)7Y4QBBf{1)
z<&d&GhW#k?^MaNL-|HylBqUCYczlZx8Ad{Jr1zJ?%p;vd2xz9G+(Z-2g`<lG3313r
zXhH?i$_dYS=>=~I_{<4DD<Mcse2c^QOC7c@ekoBXdcl_hsRW#N#bMf9j0;kSb#S$C
zOBk;rlXnS~bd}<+HonjUgv$a`&=C>upz!qZFo)$+#+61}<*dZ|H7-$EhDu@KWZVoT
z3XHB14`4k;9Pg<r$P~a3^k97ktd;=NO!_2?FP_8k1NP*s#bYF`mM@)@=14Mw)2ipc
z**jGr%0ryilVir(wJ&?@Xk3|V0-d50UJF~%l_u-(LF`@cM4|OqN#aCjGNzaiXTKUa
z>p&1|l+JMzC}rDO`~{tHK2s${NDo>&<w2`SS~-K?agkhZL9b!)d%)-ptz~Ku&zy`V
zY?bKK;ajcP9VqRTcH+mbA!u7-8q?DO`6wI|K`$qLvw-6gJuO$Si-!|-ek7DAFQUtv
zFOWG}jZk`fNXqii$H!bsr5hVWG$hUnxj0ds@l@^H0F4FY^{4g!c$g?i_opnqkTu>c
z-Xd9|oIksD#RW<c;lsj;b;$zy2o?HtIq2vYgkE5oFb@6T<m1V+&x?~u03c((E9FEG
zZk1qx9K5=@OCG%ecoeeWdc&Yy4YAZu=U|D>U0hD$;aTdNLM@$KIT!eV$9Hu<aYEmR
z8}w3nNn;#n-}p;<Db@<pzJHU1q;HV&kmY+zAb=f&&fo`n$5JXPY>d}e^l%votH5`(
zLQfzPX5OS?8JQ`N9!1Kyix*{}aJ;OxWLwJB`3P?X;l@wQOJ$UBCA<Eh@$r2O-HCwk
zx8jj3(~>3g0(Ac|C5d^sseNQzj3=i6A2E^}-wTpk++M*L{#<C=r38$y6@?&)+adz8
z-YSmAp{O7NeR69c2SSTevWZujpySGm`T*6Nu)&v8L4ljsn9e~^y#Xc0R>>ZTvr6@d
z<NWwTYGLo8!cY~gjRTPOKE8Q`6J~yFjpK18tshwmG0JyX4&K&><3|z~`ziX^)2pq7
z43xDop63)*U7!RVa_Bjw{N?6z=0zFFLM+t8lf)>hDa8{<9ug7{h@k~g#RQ?W0s(J=
zm<U>j;b>8Toua~0>B=o2LIuv?l?$+P4&*P3d}Cr@?AnZel{w>bRQdLVO3hJ*aXQ!0
z4DB7dvx|DlyR(&LnWg^htZTMvkk#F4u_a+gnBI{?z!XCnNSo1WXH=V%FUG}PU;O2$
zf;x!3kec@vlCkpC<M4*`xiPpM)VzojIQ@-MpXo$uCQ&__WiO@OQ^c><ipR0ZVTNbO
zY8AD=0*+{PsaBOe$s}L#V#cFWoiD?`4qGiDWFe@c${eaY)RutX<KpW=Vr?<xhuWqs
z<rFd~$XsbjWZ44}1jIqXQW~GJ<mjGt1SUDFALTLG5@$#|ftK2lR!dXr5IHKu5hkhZ
zrax~N%WhXTnP-iuEThyPc{@`>+>(NnfR&``t^zrh6GS;>Y}|(@FSGdox>VN6uS&BD
zrqb;A!2&i_*+@R+nV^hnD|>McFeK8c77MRq%0t^^l=fw5?+260H<Bmb2@K-X=w;7g
zXWyOB&hk324=OgmGC*QDCppRHY}5U`RS5I`x5u9A$U0SCYr^3=O#eBj!cJ(6GhwI7
zbT+}AcMtxBkBqSw67JSUHPb7sj1sBPqA0jqYSGuJ6~9s$)v1)5siR`I)`OaC&UQmE
z04&Lg57auX+7rW#%g{et(vPL9bH(9UN3Y0|kNepNoHjIyT&NqdZG*D%j!()pc^a!D
z$Fio_0XL&U>Y~-_kdKyuVQev}P{u+ickqlErvIXKc>}S5nQbh1HvN=0@n(8dSWqy4
z+iB2oW{gdytCEi2oK5Rz6E@6}zbB2VyV<7H??_&$LUX%3?;DQu<WzZAqJ#2bWF&75
zb^sEjfd}jQ<dp0k2(y_mI@XM5hO6vMiPYJ?RGF5rAS=S-vqz~^11~F8E!|v|;r(lE
zDk#5joKTXYB|1v8R{O^_&oAkz+`7s=bA<n$pZv}<?#_?s^ZM3};oK$9^qHHi&%Zu<
zXW1vuE$bMub>ot`tK01B$+_zF=Th$Et;e|$&y0+wJ=qpbo0#ofxtX7yT3cRm>E8P2
z4EsUn%JJv0Cx2yf%A-U2Zb>~~@nLRC#fMANBPOgK+IPa}sZ0NvTakRK-|`Wc+_q9*
zn`tiIapANVo@)AQ=E~$JeJ`1HM&GJJ)Ay=QPyF)QGd~$|Npem_)vTtz1JoU>Ytq|R
zA31h@#iD3J#pSxS{EFqR^=9>%6Q<U;oq3&|dh@JAYcX@`SbO8xGsjJP;U%SJO}+iN
z`J*rV*4TODPJew<(+5+Y-oM*Eed%sF1M}SW=eIA}bl<>^U)=i2)=lSs@ZyPEpWU<f
z2j72m@4tWlx$SS?-L}wP_~H%AZ{K=@x@GH$+uL_8TJ^&{Bkz5FPruG_Z40*@w(s1E
z;d}o&c+={?Mvv`Ubjn@x#w0t}?m7IQ&+MuA=f3j}|6u1?yWj6z^!6+FEc)$~MPmow
zJ@3u$O<%j~-cgV3D%R{iYyWRX?pZUsZU5kDZJUw<=iPJPpowR#xjwi3)G@j3Bj$`;
zyJ_^;y?<XY_VZ11#{6Q<)#snJ>BO;zm*-Ep;Ksv79zJ(k{l5JR+OD|yxcWs;%^$I7
z_0b~^|JIcEu25>;ypsmpxage&Zn)~cbnB+m=KS&A8{g^Kc!@9HC5xWFyJOSg+qT}<
z=k2XO_|~N_p0Z`b+J)b}<%2id`#iV(t?%z#Xvb_lZ`lc3&vPd{H*orE`xZqN`}*BG
z>Cf}rX>AM78NKhkiuc#;x_9ooFSs>p7Y(>|-qXoP$?uqF{vJHJ@7%+#*?Gb439A>~
zH|fcR?Y~>}^uSf~?)~1OYj-Zc>#?2g_V+LN-#&9z4;k9FY4E_d{eAn)d-L8y&p505
znsNJ%8<yW!f7F~kCuPR&dvC$me{38&cK_<3Q_p(zx-l2%DbHN+o#@dEE~%{F_r-$Q
zi;B77i<Zwjb)=hrGWnhN7xKI4DShg^`%~ARa^JhvZHu0*-nDfnkF|5<Tujr?4&N01
zu<09H@4KpM>!z81`PI|+-1@7h&nW(R@Y^puaN;dp&65WFTl0UHjqY6ggUy|{b=<nM
zd0G3e=I3tSX(oSvr&0f&nKQ^{=7bOCv+0K;TRCdc_UfKR+rztu)~9z2t*`8U_b2z<
zvg0R<yOw6sT}w^BKhDhkXyDA;cbk4PbHmKXX0ELnzxCg^5?9w<pITUVZNC#vT=nyb
zr|f+A#QdIP$26}#VvNcD>H3WQZlBTLzw_Ipzkln@5qDfWeApcq&l&iKD-(m4U;3T1
z1}|$ls`<Nzw4IYyZ3D`Ntk`86`5lpWByX1=#*^eG`@^l9KAM{S!HzSk+pcJQ@t$X2
zeBkc4^q=p&C7J!foj=Q8);_ZHwu8gYe(s20J)I6#H$S&|r#ffxyDB^+KWSNwnZ1Nl
z41<Q)i#mR`x_MbZ-qg^#K|6*f!|u%N^pAHua?{<N=Flli%>hk|w)a1AroFZ4v6(-g
z{gaswn0FuPa@j3mq5j%bzW(~~gqgPM&=XhvWMF>v31jkmYKLVz`_D9X$?(y?T~Ryw
zw;hF3cCI^W#2uGT9k}h<nFIgu?X0oC%lGNG#I_Ac&1yTR%nZ9@)CfAKmR&}vA5yOK
zr~k44n6VGMJZ*GhK|j~|c#)>ubIegc+j8P}8~!-Yy?ae_SGKOaqfhbZ#Tj>sYc6(G
ze}j{y8OEdxyMgj`4UCdHd{Ot)-MX2+cUG!S54`m-J!t9V-1IHe^OIY)M~Sd+GLbwZ
zl9yh|yKXXxvOfA($(QxNCks*k>I2iwm38Uy$uYV$S!Y_RD>C(`uPfBs&(yWao$AnP
zwj1}Epqrw*bw0TwGyBkgmSro))YNshTzJh=dtqwOJBO%|sc#%puWGNTYf&wSo<RPr
z<ge;Z2KLkmsj-8qv*)Cr{48M-3yY?*rDxrt{kPm*v*V91>IGxkDqVf~ia)y%?xEs|
zi)XrqXj0NJmr>ysj`r@TOIHp}>eTDHA9I(y9+I?bh#u5+GedOFPT!nso@`GizM4Fi
z@nI>;jH%p==Qm&$GwuI(&H(h+2d9z;4^QRF1}a|4Wm3hcP(Nv%u0L%HzpnV1I+St9
zrrL8&eSV&cDt=+=%KMk;)MqvI9g`YoyGc~U3H?<=|6^-wwJ}2&3iUNSTC`5@p<iV(
zXH|yh*wHP@tV;!E*<hts-)+@$a^Jmzr;&tp>qEZ1ATwIV?R1$k1DZK*D}$J0I~UWK
z^lYV;Tdb8NKF92$uU5-XXWBSOCDO~ZUYuu@m9^f3m{6wgXR3Oj4y&Gp{zJaN%p1lq
z?~mE|Px&0$K)79<R@KN=%bdulQ1(_0WIj+8GM!n)-iR6%4q$k#`Zn)-TbVPom{h6|
zqG5(lIHB8{D%-+(M_3)&gE+__p9rewQmL_MIqe_#)L6phEci2utCe7v^(a^DVhCq4
zurMq02j&Du<|T>^?&OO+BqG9D%>g{7F<PcF*dS1<$Tfh1Th6>n7PXdbW@<*<fM(^w
zqDn0*qATI59Pt5p5`UNDl8L8(j90B;yfhv*pb`Y0z6{~(P}}h7aLe>S<Ppbz&cRdO
zX@$(gINR<YX{u^TSEEwQlb8j`nV+ZT$)pXlsd_HiR6a}YOhWWh<n-W=lq)xu!_Odd
zEG)~GSNsVs=u{Q?#w1#v%Ti-`#;sOHSx_`zdA_guPl;Df?Z8GM_Uk6pL)y?1@_F^&
zQLzqOC;FN|_?m$BA^a<i<W+2t3Ti`_P%ZI>^PmvR@4#LIjm^tCt*W$sy|&7bb`lN`
zW;~3^l$~tuX;JEbsl80?YQ2so5`2-%aUm~2AMpZOS!e_n6O|Bj$R(3ylr#_ocpE*9
zfm+N6h$k-|id7}V!&KMA@(D;Z0m>*?%sk!`bRfxr7eEKUsGzj}ScI+t*Mp1>A1hW?
zf$Zl2I!sA`1j@uIae;rpCM3#~i75)>sONk<jw}vRDN-WG<0Mw9nB{Ioj$}&$rJPAX
zo@XTvpF{|a?DTTd7{pGspnO{S9Uock@}Jv;e>*|pqZ^3_&5XMQaUKYUY6kH$yf!wD
zlsM7PP;fRNAYUC$!9gH)y+T4~U}5B>!iU5C@A!006e6SceKGu(yI*>6--Jisn)CY8
zt?%#q_^2;-{r$n~<ad7VUO#P3+hxD_VjtoBW0U7>U-tT%Syw*tR@?k1zO#ML<ax`N
zHSMmy@{y0`&fhSNGe0BmUEZ{2<#~@xKXVReemHk?@7|_0^>3_M_?zK(Hog7OH~F2P
z`MWb`?mqv_f8IIgjlX{L{f*z6vw!Xx4=$Rp_N_U~KWTk`|F?$!a_(6Vww}4?)p^T5
znfA!WZymK^Kj)3+esK1pXSTgD;+ZRtI+!y(SM6VW_H~bMYq}vb=@$pjJ!!-BZ}0oo
ziJxpc<H-7NK62xwMfn|{tFHfKd(&gHzV*nf`H@l0_(6`mx`*D}L37t?NTOR+bgpZU
zI#)&~+EwkQvMZ`dc5R8;+8dLTE8VEv`B7a)N0m``56|jO&O=<tkKJCiV5lAFlrw6y
zN+#=6=g5LpE7{AsvZ|dShiAntw$|n-0e+}djS1SDqF{@Dg;EJsj~=S>iG08(E1r$i
z`1XOk{H&;=8>;Vds{T2r5@)DDFKDPRR|IKOpnZiwRNfK<&8;dm+Xkswl_n}5X!N+c
z#;RE+NaU&>OpF`6GWEtvrLGvyw{XwNsNn3CQVVF^-t}jGO7$Q{^t!CC#Y>wW5vS>m
z`#*R4f5OWAU&NPTsb>EI*ov_I7u;6?6MLzlC0{8jpr)1pHHrQjXm!VrzZQftBTb-a
zRyk#?oIQ~CA&Vxe!sPS)wY3tC$RZO3aSXpF$8#@_ztUgRzNN=9yb?&HXLm~5aimQJ
z4q80PrIdq~qcS}YFk=wbb>gTTZ$BOF*??0nSuO3;NJ=LNfZ5e?ynqnxh~q%5_NPqf
z>!nvn6;bO%7%^WU+EO4DYIeW4+q9+5(`YNPDIVRWV^Ia>dQq+ipYIR(K1S$EQSt$B
zWP(|N?h?_eJV*B{qWw`G6E4Bu$e5EaEG9OUFjj><XdiKxH57jLCzLPDdrqoALMPu}
zB8~wV>8XlWf^06yVP_Ukj8e6YwoH0MlvlM_8A1KiN|+fz^M#I{RLG`blSl>fJ$B_B
zI|w)hYv^lpge61R#ozGxvfH*AA91uEJ}?|uP7BM(R6_VPY=29_iUeH37wA!;mb;Y^
zoh|3$_XzTrv>DYUrQ`(5JcUlZ#RXx8O|C%90FRM?h;m$%P?8g|CKNBcjofj4;dy^N
zP-^91Ae&89h8Yc=FGLiVCuX744{+>zHjFWhC6J{o42jMf6vV^&nrDH<q`GZkOmwOU
zK|4C20cluJcBGVOudmZ0!&h-Z1;awtIq(b(U5(;sxRo<UA_Jf369u(8E4m?@!5*ZK
z42+`pAz>hBa3VlbP<G(GDG9J_1vnKt_6ovHNPK#*?0OAS;Qg7O5to4>Rb(>xoN#n9
z{F6d+N<dEIeQ7*oa;961K|EVIsv8^)%{VF+#-_+1Wqy;U5{RVdyjG<;4p)IFaH<J1
zVUZ{owb*_v5mXoB`Le)|1mi{E@vNX%fwHNQQWB7|)0c6!F<wL#p`sagrQ5&Cq=i(#
zdRF2gHF}|L;Q1(BXN5rWN@Ai6nXvphxPXI7`W3@CV1+`x>`X{F)m>C!A7TWT;HGSr
z%I0L|p+X5OVX=Z$P}-XnDg#P@HWbDlv|@+2LkOReH<nWFQMw>g0@|hW1tH1kpR8=}
z@ZjY8VQ>@k895V><GETAuph}I31K1eo3#JnaEqt5bWeC_)j@3_6$6A3zL+|Y5Xxv%
zl~rL&k|KuGgf44g#n*s*q&ShzgjP8f3y@?Yshu!BVW@(<S`oUsY|K%RJynvDe_8Mh
znR?5?6mkcJld>$xW~tkS@;H<`+W8`Nl&2_G%To{Eo}g+FzW`hM?v0z#DL=mpYD5Fo
zVsLEr(zvCeH1d?1Ee^f4*hjz$ZOYf}IyBeL2##izcXDDys5-1aQv$I_G~&`O{Up<J
z2koToF-VJzlx~qG=bXf-sun*jEVq&r@Ts}e1v87_S-6D&&wdhzrRcH(?-9pRO^gKn
zwin)7z|NoP>9YY*qDG)bdCj3QTmUrUzlpe7CsYkGsuV!_`LLJ(G`qhbh<urXDU!r+
zho_BMNIv?2aNcH-z5``CRCSN)mX8?lj)AWba1=pW7)_3n;~aY@nZ}a->=HUVKHP+q
z7}%jN8DYb=zu|MTd7GLZSiuX3>O6+yGU)cVaaL60mDI=3f#n%GY8Tz<ohxuiZV0Om
zF@zy#9LxhHx)b*AJ(Z~tl}v^8=)Sa*BGEK5acCaaXRw>%KwdZPx};!F!eJC2387J_
z*$yM7A@x%AJfHyWvP@FacObi@vcgz&^MN71nmQC1xJx`YPJQMx%EBQ4Vc{qncW7`z
z!Xt2vwBN*f{7zFSuyuxnUJ(pr(hZgj1RNc~c8X<nRe5;`g*+UE7KNb<q!i@`i#og@
ztscr&8cGL9ZqABq1W8CocZpoXPpmjP<dw={YjbmVF0Y7}Zbw=i=F=;Jp8GrLMQlN&
z(yBOCBA$Uf!Sc$<1~mkz1$jQ5fe&a<ZYXtV1t)F~bkd8nM~qjmDlo}FxhfhX)gRuY
zgAS@WEd2-6<O~*dMQaogi%e=zOUFS*)-jYjRE0CzHL78E71{>s3yN;xB#Bbh>3WD%
zvB($Eumj1X$*J}pIj?5fwrF@Fc49^&{cm-VF*`)8QtMQIkz}Krd?FNRP*OrpOqmK>
z{vUJi9++2E<^At-auS}#&^ZaAQ!e683>Ye4z>38|W+x38O2JS%wUmkv6|hBaDl%LO
z?uLkwmsdkYL`2@u0R?5SgIv{d0wN;b3L-+e$S}OZI5;9A3WEGT-?h(^rX6tfecwNR
zD>-|wwf5R;uf6v5oabCJ1oPLLHJITs%oRg2Xj|SUkoP8)b}wE*hrn~#chn3t@aLMa
zf=QusPt@YeTHdsGMC)_-$76dogI1)SgSJqu-T}G$pKjq87bQ9)lKEh-e%s2LGy~F4
z^03^w`E-}U$2P_<vCE6`;CvT$;X3c`EF!}q(zu=3EH^<#F|mkTBdNPC-72FpnhE)l
z#uWped8oFnmXg|NEAO(KGemQH7Y>Y_>ukT<?|f|M2hB;xoddNyo!?2`E?=+lHk;SF
z0Cm;1xAr#Be4C(s7ju1t>TR*~;M~wIIF4`Y<@vDd>4p1_xeSKLIG(|XeLZ&L;U1<?
zS;Cbfwoh>os*mas@qQZ@u(gdPs1`b0K~7rDyK<Z{+YWyeo8p96d?Kv9`Q$Q=QSI6!
znHlV_!74Y2;xZ!A0>VAv(OrcLI&2zjZMup&v=k8^)_R9f=1%cgQd|BDs=?#B@lK|m
zm}SkJR5V~_y@A<t<5PrckN_KTQ$>g!s<ckl3`VM!JISc_2_jb8KdWTLx{cT)fl`tp
zra{9XPew><_(pjy_IgUmkU=xjTL1&gAf;KZpalZ(W=^Oy(FGEu+Ga#Gw_VI8q}i*}
z#!7&Nc9`u;(uIYsvS|~*_Z3z5%oL(zMD&b2(deb_#PUqujf_q4<cmm3fKKA_5!>|0
zOZ0weh{~fS#KQxUGt8~#A)e_qzHQq1kXc&(8Ab+$+HN6~r~7)XVe~U*m>yrt24smn
z8WbhV4DK>EQ^L#9B3PbYQOe{ACY+6wAiLzR!FHKrFqtCtrwGs7gr)jsn&W{yNlWv#
zm6*))ySYyI9+dk{)GERUtiJHXrN3)#_J?CAfWg(K7iDltPybdfFWX(<NC7;X0H#Q^
zv-k0;TN8(j=7$Er3?s@4a?TI*Cd_ayiXVlU+0OdY7;dO}`hl@6C-uaRN{h!G(b8gY
z66B#~ry{|EMRIrp^hQroqxC5()ntlb2AGuE?t{l;u5BJ&tLqoLQZeDW0(M!>-03L~
zGg?=4vBxu&Sc?YdSSD&k38K~Ct1Ah{aICD`R2;v^a8J@GoB@+iNj{|)A&ON%12N?>
z9I~84K=007FzZZz>=(~KMQfWi7Kx$@dCv?qt9vu2!7__Hh}CaQ2u52-&=}q|wgky?
zWA=at)L@Zs(d)4Q>jmWKm3>M}pmRVKOb%IeJ6Y2BG}<R2mI&E{L?%usnZ{{8?VU82
zsvP~79>rz`9We8t(N^{3$4KI6D*4(8UJiPTQ@H|fp@M<%eZs)XJDe1`5WNy)q##yE
z;p&z-E8xiRz~R{k5;>EBa3NT=BN71;i?!#ipl0QcLP<WN#A5K!j0IIsmT;Ocf|~$W
zS@MN-PB72RTY-9z!3LiZ2hGpcDIyfD$ter@DP$O0vLjZc50su5+7AJUtWl0$5eTZg
zc#voX_lYZDaHMSG5ECj;1K&ezf_!e(iP0&65L4r)K9P7u#mgY`Kw!qnmYijoj9xr}
zw?<h5w#K@sF-@;@V@<Phe8snCxAwbJ6lvsDw~<O8dCno|5|Wo)w)ayyAPw*dm=_B?
zMh8n|N>^xk=pYfXWGrozkp;>#pdw8j91MVgJWhfpcMJ_t5dbZ%0FT;uXv5h6;-L}r
z8{J(gZ-E|HgF&kg^*~2NqV*b=bJaZ$@X4q38L;djKnH3pd2xGES2btwV-O>f@`jY6
zZ+7W#PZ2<uD>9zf0b{7SflNEhkQne(#_XCqf0($=QGv~N;}B+pR|`cfpxb+ss8JN!
zlpe^(B8R~$+pFXFO!sP~yp%SgB-IGueT&ZB^c$gwbd`5<rL?M&7y|UR5^;l&s2E(f
zr_>6(g<Ayq$j&w+x-na_gY+bww4cDjx^ko1!>9_<;EAHALmh(!!J8~1CLa|O@W{I`
z05{X`oS%dps_G4p$I|0SRZ63%kgOnI@`E%mdQ%%Cq-@a)XO_-GK7pws^CV~{d+<aH
zOAv_SRE5|VPgCEJ9YIE8@4S@7EWoSTn9<Z>N&_XDgIqR2QKGaph=e+(fHN-Da<ZME
z<%^BxLnCzLK#9ukQCo|rZcYaDS&Ia5*o4)Ular+g890=lG7Ni2&9QQFvPiKH?7{L>
zM1W!P1m4Us+WL%7DY7vzM+9Q@Ko&A9^br76@2~_nQ=Fi{=vtB&D==q!8DZ*7fM5`@
z9wRK(O$JR5hy<8<v=py!2Aaq`DSS+r%S;9`)fYwDw)spFN;mMHNi&qgM??8ELFRQt
zmFR6wSDe1jrxG$38){u{swJ6xrF0#ZleBIy$_B(myWug#WELczs*@P@ou6m7v$Q}M
z5m8*P4G@}H7LR7E%$%9}q12L;FkYl0*csB@Q5=d;8$^04o9#Uz5$0br8B$RaSm!l2
zt1R0SizkTuN!HO7gUk(Hw046DvMKe}{$l#7F5`wLF~VA`&@{0(_^D3vL$M}PWDp4<
zY@<DzShe%D#RBB1VK%-VqfAOMNt4(Lkj!U-@kfAYY|vE)(Sm5<l;1EQ;}QU4+W1)@
zlK3XKxhyS`@aR-QX~<`uSVh-~%uwRM;kDHOMl~+K*CO<PV!EaVgP5u;Lz^a51=C_-
z9#h#SF@wo|LZfa9I71H&f&nMA(v`SaWqZc3Ni1wGA-T$p!c-mxD=^4;M88>vjVk~`
z=GuMmoG)2HvNked*)qf{r~(pVZ7W-Z@dI1*<PzO5ZP?sqvljN*yLU)6>+@PaScD8%
z6Fdm!(1Yb*Hl#+QzltpnDFQCBvCInd{7D^)L@pHInoL%qNXEnrtbvnLKX^!tHNdWv
zNyn7EnW(@L%62Bg22g(O2Imgh8r+MKD<G1$$H?F~`DvRVilJ8RsB#%wEUK(khQI+t
zPe4AjvYv_%c<vn&lksO0n4tvlqHqgB1JPWT$w%6tb;1>ls6rvQA_if(AMz2lRNyRl
z!!9RuEq#^!e4-(Trffw`!B7ILpVi%x(P(ip&t!wm!B`a$?(+nJ!&)sSVNt9-K`{_G
zG=W5I<Kz=<&@)fbF7K#n2j6N`kko(xk|iRhNYydO&8RAG%G0HXMW%q_1yKQP-EZTi
zs|Pz}La>!rW2})WrgnbM-J~My3KuL^h(A0L5UM3Rg6jZUBZ288m9e9GXuB$w6jer-
zOwl$EYPu-3`w~P?z>%wgME6VHTiM;JSisy&aii+Cmc!90mGR1vx+F@=kEEQ|jsnUX
z!^Tja%<S99T^VX(BNi%1sSypaaY~&}<-iJE1ZG|Ui<sICzCZ;K=NzD$L4@9(x?XJD
zc7EMQ!4P?axulrD_#7EQ<eGPDrDR@PxA9EM3uWQKVCWzZ69}~NM&*EWo`IU|ZEk07
z$(1J1cwK)0h+SkBXN)w16c-c3EdkC53r2L9VbG8gVRKb`;#*@{VhiPZW15w+qJlC8
zE)I#1=WI<7m8pt$xj=nFwCjs?lMAH_#;{+nNlPy0OoAL5FvtRtW6UaRekdZj^s>9@
zU{{C+<pIy!psTsTihxEqG(<fDI0>7$){;ttHYP<Hcn}%StRen{XdsIONu<`o`L>5d
zxsCHpE4ML`l3-*M$bCNLa)Yj*(L6oO76=nX5N4Mxqn;wI0dvjnw#RfXBrywzA+%?t
z)Vy0i<~?fP`8h<4$V1R>x2}BKMY<A%*#mAeUP$+t!y}ZJdo?pcz3!t!vY4AF$Mb+#
zt$dX6DxLds9H)yi{7&G9xvox8es)=2$gQlgB!8&I9hvy_ek{$W3-H<{x~(FUk-oMf
za4$)F7{4&Mq0!lHC=cWAHXqtm4=#v~t?QkPw~@cctFmFt^_Rs8#^&v(sLlgJD?-E>
zp>xAr6ni(cf-}h-*~JaeDMp!N+WfdGmMzLycs%#dq%N^`l7$16VT9*(c0tws1=cV;
z``D$mxY^}ZVK^TQS?k1|>`BnMfH&92n!juDg3?{<c5T;OydzWMlHM8aJgy+{ES{Xj
zL-*c#;25p9D?K9bjc!He+)(E8UORd08pj^8XHC8I`xUjE-+eI*UM~*a1tVHqHcA)g
z7M7wlbaUegkD<PUT4b)LHt4A~_s|Z|91LdHr?$Lr9hj~z)FN21+~u7V+1umG3B8-q
z^V8k;{faziid{>0@oe#MoA*9AdU3qNYe`=OUe=b*(<N!%)Km`SljVASd#UYI*YB>O
z7-q*<BD)xr3godItMy`dK0K_>$PeW{mWxAq5%&%H{=ko(z3w{R+t`V3L-6!r7YFd~
zXyM8```nB=i;b@bcgIl3$GtnS&kwlBnn7Cy8oO!2O;C%H8*GQ0sQm1sT{$v@ryiqt
zS1<EGhm78rzMr4gyj!3Z1T$ke%G!43g=6Cg*2cNZf>Fe8B}06oDX+!z`ukB=w(cFu
ze4)$Ab<ULw4|EH<V6Nfn0zcNeIG@{S`kA}2mrn|XrCYm}>u~BYZ<f>^i;1T5D6h(A
z^kVLdb!&p|+hD<5<C!QHy4pZ+EC$7lY_~#vB`fO0jBK7K%VzfDkzJV1xlq}@LhtNj
zW3xcdxE%RmBy5h!-?8I!uU-9jhkt(Uq6Oc$#Le3Gw589C_wKl|{pK*V<8?zj?Rfm+
zS(om+?}<BZ?A@O4{#-P++xkl`p1c0Yr5k&PhBt<L#(VM&mt1jk?eJyu&R)9A-E*-&
z<^CP6-|eU)7F@ULhy}yTK6lLr9{Ajiw_Negq31tv(8A#dKX?66LmMx9_p_}BzVz%4
z%THhWxf@rtZtS?_#@ecV*LSX3J$&CIM;*9q(Sg^sp0N7*9nSjj(q+TF`y9FCz2*74
zueyHb?!Bk&G~BzYb=hs>7r$lyxtH#|`w53Entj6Zk1RO!#-1Ntz5Veo?Y>~y`*%N*
zXN@k~<(=WOp4aWV{0P<euB++T2X24Lo4SS$TK>{yPc47>(kGWJ|K??3`8UoT-uS5}
z7jGPYa>pf?{bI)>FFkJc8JGQh_1iAp<&?|LyYsZm#)kTSxbgYENABO}w2k-Ov3ldZ
zlQ-Xg=3QU9|M?BQ-+bh*dEb2KORH~r&&kW5KjN{Uf9Pk6p83$vPJ8~W?=5@&te>6z
z>lc1@+>0+fc-&dv_}-UKe`@2^54`x`1|2Vb<AKhXzOnHwAAb6g@0|7YeV^X-4-anp
z_CIWV`&ln8JB4HJN&Eb8yW{rx;p^%Tz3%k>hh}d5^7EfP?N`rV{QeV8|KZ=9aQef4
z^Uk-w{Kj{_{l$Gw+Wm<AKXT>v?>Om+pMB&_PdsvV+p3q3K6uq1-=g~NaXa7GSoNMa
zylK_4t(L$1nWvV2<+D#MUVhoSaO4$t4R1W>s^u?SFtPl|o$gw`Wc0Yz`(3nT_3HB<
zTYcGi51o8jynp<@`)05I{`ZGYyX5vs)%R=n|McXs`ww0*@7lYLoA=^|q2r%lbl2+V
z4?6C-4}EvRGiUyI!IS@d-|FXI`rfjezx?3J7yskFp|hU4=dVt9>U*Di_?rK*^q-zu
zyY_}_@7nX>Yy0~Se)`+Dp7rS6x9<9f1%G|kAHKEiyI<@-W%X0bPC03x@BZzAJ-_|h
zqaJG6deu`q%%Hx<{p$JgGfsH-y>C7EtnY36y0dQmn|GY`+}}L$(WYHqzGmnhdpz;o
zj~x4>``)?#s-Nuqo>g~lrRQE={}T0G*?-cTRt=rB{K0STGHZC>)|N##9>7lHj@d76
ze`j0E`77F5E_!D91AQH<ciQ3H-Z1`n@4&1T<+J73yk%?G`~1@A^R@NWGdWHA{bf(~
z-Ld0ceUIGZ<}KS0fB*Y;KX%&PKbsi3`~K0s-!FA{pSIoj1M@Du<AJ4@T>t3JJCv(e
zfA;ln-}mA(_g#J0r4P(|&!fGom$hf(5BIN{Jg@zfeLwfQRqK~-w`%6$%?Hlh;n3dI
zI~=;}-S=<*{*V7)$M=8ylI>Ql-{IZ!+h=V3#6F+s`pP~(I$+oDKDeOymeYD)v+#j|
zgO1*q&2QgfyMrF#$-{U4uco$lJ`(od=giZZhhxjEj#l=3ZFi{dZL{KIZ7t_rxBS7e
zj(0zhclQotvwFkGhS}e!U0Pn>5;cW#d!t)@WbK~S3-kN>E{vf(e?geHY_dLY=}0*3
z?r)8(yqizcJbC*y{`dL7^Gh#S|K#k^i*EjXvG<cV&v(oBUGwp?R{!LwvEI-*zOwW2
zY;w}AiWh8i{BH5hgU83FRXYtdt(xf$Te&(Ox@z_QwSzu8yyHP1&)&Uiy*vHD_4Av*
zIK#c+SGx|oT_3o;ZP#1Bz5V?Czt#1c6XF|QQ}*xPRBqL~^*j3yY<p+8rR|n)j~#r=
zV?(X8_pLLd+A}dXaNpIvJI-Er;q144p~v<1y5SvtcK^I@wa33b=c;wP9re<)Z728{
z<9Bw==vcVtVZ94xFFJqDj>YVu*ShU%`{(E1In-2pGP>=q+E89{)yX05)_HX7E$;qo
zYq8<SpXizV*2VS7^R8H4ewKOmU9JAn`IE)J&gh%J;qaEf8f`ju;Whd1m*2egy!y`D
zt@R&RGI7w#!P{C-JMd1w^6<C$-bF9^+HKdaY&-9~z1F<@OS`P;>}~Tcx7WhqPy79M
zU=J|s@!oakZZ&V+L+#C1ye_yaJL<Kzj-J}VwW4)<=5-c|r@V8YWGDXZo$3>#t?mn*
zuHyth?7N1?-5uFjwl1#g*!}kF`;PH5-10rQi<i!rKk~+q_q}m$;l4i?1wDC3@5-j}
z^J9o(<7IJidGbY9%`L{C>{%1H?-~F8_Qg1NbI0*B7Q12(UT)v!pI$z@_@{E^g2~X+
zGRh;-*UXr`_^R@LUJ~oOjvDG%P+uCF>chwRmElG2hfedo_qWw|yI{Ay)`W%Ku{PG0
zZTDQQ9?td0xW~Pp@%`TJi<{<k53FgvGS<t9&xYB>?3UX89qemn&EXlJLeKoTvpGV3
zB_YdWuJ@kqmxa8$T|cP0UD!SmG2}cO3g`ZMn7to2eCRx@sBv%YqvRb7u7w%R4$n##
z5giLBHxIbbvH^V5QGy%RK1?zNulp(n;q-71Z?_LEpc!j=#+D&x@4k(GcfH<i=dOny
zW~rPcKl!rg%54}J+7uh_j>5IS-qp7GHyFS+h-4F-i^m7wZFGR)IVdup&>(ZpP3{{A
z^~<uIk~Kkv4^r<H93@8=Ex(4Ct&7gB^Kmwyo~<88CwX!QASZkDPVJU)>J*^a`Vnd&
z4+Xqpjk7z3i+x>Gel6q~aS^MZFar;VM=IpG2+?Uami^el-o`Zza;iN^T^#)D3HrDu
z6xf1Hl2&+^Jq;h6>~0%MZMq#gNSYXW8&B625%tVZJL406AN%w^_>uaGu|BdVW?v~>
z72*taL`h*US6h#bYy?}^V-HDgXlLgpxI<Q3e_q3wk5LZ~f81i<@_O*uF6vrJ5pmZ%
z&VPJxt{ZxoSIyR)8N{ZYx?ty{u7^{YTE^B{eyObt&Tik*X;WKt^b3zFSIi@wzfqrL
z+4W9lE2yt8NGx!m{Nz)`M^%QN`MKV%|K=VVPEGx88juAWB1XD`+U~^>z_hmqa*on9
zVMY`gVAO@UP)3UhJWMV%AVa#sgpGh<ke!UV)5I3R8401%7z<WT8-?lHPP6MU$=hXV
zDV<jIg<39<QYZHI(}KGVbW%)00cWR{E>k=@2H@#DCnAFlI-Tq%fzBm!4V1&|pq?2V
zZCov_&ywk3qzm#!z==u8)j1z981VGMNPMn{q=Akh){M$WN?@X}2wzyN?x?&qlgTNi
zk<M1x?2|H&Oc%!hN0ly?^$%j_FL`#+)oyssOZv{w_zOHq_{Sq|x$#|dKEL{iE6*N!
z;o(ER_Q=M6zVYwh_`i-n;>u;GeeK?}*Iu^ZmvayM`akoXpEH(zZSirxd2zuF`yRnF
zKWE;w?1eurp7Vzn7yR>ChhP2BS$}iG5r6pOk~uH)9iP>QU%mYBGd}&u%fCDIjrxwy
z3D5uI;?v*u=>>myZqe6yrsswe4*%tmt6nhrAAfh&oX?+d#FeM6`qIOPyzuOze}4I_
zH@*e>T?c;s-m`h$=<3~0|N6E(^Rw)ruPr|N!3#IO{e;u6e)kFQzv+md{mbIN{nY0d
zoUq5CS1&)|jXZDk@{;{7`SgO_Sp{5tnP+~!c<P(hzO>-&M-7d(a0O__>}BCVQnvSt
zVp*T*`6iCb`WB7yc7@o%^tB`2DrXPJ?N8&HeSIlTKg8|Uy_3sN$G5-cB<4_V^O{@d
z$>ZTr9vY&1fMdIf;NHGIxYZ%H?E}5?ajuYs;7$qL!WUv~R|dFm4X$_6<@M3B=o%g#
zV#1%X_2g|liQ3T_`f~T08En<VWclRyhSnjT`q;lM-`XEM;A&mG@^)8uOxso$Y(1k4
zZr3huP4D79vR&3T^MV9U11Th1lc~OoF2LTa!jN~Zx)wn-Eu0oqjA9zAfvWSq5?|@+
zoCeXtszXgzuZ~rLZy*-`7nRaQS)sm}n0l#CJ(WZtC?m34=J!ejcyhq)^=}C`K_*yM
zvEbVIj*X|Wy7LPy_edUksG5sP1d2kV5^3g}2$Br%<yyg*jNmQgLlP4V`;;YF!I`zr
z<yoUk%cS{KkoS4FzYyO%!HA|9T`KY(j2vrvUc>rZaIT&6l+DGYOT`Q&2CRU{iowRu
z@)Kp-ZAF`hH_xYG@0okV2veq%`o$m%vYlCrxu1H#k>$C)7dwx<pugUN4RT)*YZGRF
zM*kLMnJUFI2f7a-_sr64rF0Ih<UCN59uVw`ovs<hK&`ERZ=#cph@6w>XwF*ust(gp
zC}A&-;JhX;5P26Jz>Kg0X`j2->W#tyjwiEw7KC+`IhHc;1H#o)Pu{-K#2atC%W+&X
z!KaA)Y@hlHcd4UwSs?|zA*Q0hgBZCphFK%pO3-Cl=2DY1Wu><{-Hc~xnRIj?y--9t
zV6v=7XciZ3CNOjM7<PLzpAd*B4uiFv=geFgec2nB$-U>PDRlIkVBY3)C>;rELuFGi
z)J&;)@Tmzt=bHl*ES}|dYchJ947C2j@<-ck9dq2WkVk>n2g>y>?v_P)RG?@6fgz4_
z)DIocMFq?(>tPZe8tCWKA+?=K3+9y9%O|mD@e<+|S*;?$>>pxOkvG?kwsK+#pFRf$
zWO)%qmzl=p{p^2>aTh!(0GjcUD`IM|7SLoZ@{x2ms${*ts6!+@nb1dSm9taC&*Z0M
zcxBPMRH>Goru2pGluiJSl0G9yXU`ES$crZMMG+ka)cPX3L(h=(O}-a{LO>z4$ZK1Z
zojL?j4afqoG^!>H#&m-{Y`%?k(K4207NJLl`KU0NIKViFY;x&5!M4Wm^<rLb%$X1x
z1C^D3U12mAx)=xQP=c(-8jAtWAGSMBwdfFFPH&@iNlf<YrxpF~h5%a?n-4%d6zY*|
zN7hRV{aLQjo|co2TstGPzZ@pXU%Q)g=l@(%D59f8FrF0;X-c4KoQU8lxPmbS!PJ37
zd_Y>2=<#n<W}viCrN+#QrUQtwdX7{=umoK8m8vwZJ&ZJ7U6T?4>#osI0&6&3{BBo2
z)OZ&3yFADYRSdQZ_#;LTG;5B7cF|k8(WFGHCTpN%Yoe!yrJ2x8dLRwR`=lK)oFwt+
z2UU#WJ;Y<0RfDN1BJ>m#uAq-8HMe~uI4Wo&IFsZ+S-<Eq=}!*ErY7gbmTmK`BvC-*
zfac6D;iRXWFp3YH1Q*EEuTwcjD^NRE`IJTZ1(?wQP0FaF6~*EDDTJXS0r?h|fy!*H
z@ad8Gc_SCyF7>=1TL}mSl%3>^swO8K1qt6*j6hzKBbxF+qkIX=o+MK+N&3x=B`t6W
ziYd&xa>EKs(;i=a)hBhvlVbcX^=6Zd5Gy4%m{Zhdi0rFu>{AACYP$(!?-Yb7S4^>*
z4fC64YUnUcYR7H&FtLD5OqfjfM)oN5(eT+U9+>S!bqu6*B@8G4_^GqzQ%h?;V2njV
z8wFVp88zlcY&8cNr5;nYxA8~8-p0MkXl1Y<RW@;mE|J%8#{#dAmDGN$V!SeYi^CHf
zG>`S49_N;c!FU}fqVGh#S0wl}*Pto}`0`tHArMG*sxcbF#>Q)tHg8sMzE&+ua!<kf
z5z~EC35DgWje-j3?~M;E6cL(a)wO8$Ro{+cnDaTmq%MI!g!<u`tP<sy40@nZvou~)
zx;Nj+USxC^Gm@Nla}=4@^-1j-99mhLpp^+H<aI6P_bs%F_Ar=X=Yc?4d@8bVgODih
zxB9w5d4r3D2{PB4B;ABDMqS7GAiDp6b_hgBdxh5JiXa~s-KH(3`cW<~^NXa&sxl(j
z5vw6In^iWoablQ_cBMj1<yjfIrh^Q5fk+!fH%A7Q{NjUNQe<%oh?T!k<qSyb^TAMW
zp#@FTaM`<tASb1W1e>a!Q?B+?dCgA-*Ws0zoOF6}lgI%TIh49-fm`Lu3MhOKwF8dz
z+y517<|MbbXMqiI+rJ&3WCm)JQiahfKlSqGzOOXV34$U5{yo^A1C<S%bZqj^t7Z?8
z?O`L;T-qQseH&N<{|PHpp8O943#-8FV2n)XA>kWzBcaN>$%6<q%5KR1mpCL&m3On`
zEqRS{HWM;p^OXNmX4o>vNzZT2(Ilu<PmtPAgtXS$nYRK6O5xE#SVcrP#$dvYp@6<3
zm|9nHMvd_io%ow3&*aR?Q<ZDYY|4<N(#@XAjtGmg6Tnlq7o^29;p`r57L=S#1KJk}
z;*?l4S_Nq@WZ+Xl@KjU~&k7bU;~UNFmExiqnQ&vEx*;#rWihcg3%yS>KvJA1m7^(R
zH^#<FT9%s)1=ZgK11=&2T^Z)wXMSv{JhIMQ1vdtXNG4{f{ge)?@_?v>Zl+jlfT5ib
z^3zrVFyndidSkVU?w_JkBU}3*!~kD=GmT8P7Ls?W7}F9-C`bE9jgkSp)+ulg9yq2$
zpaAORD_$dRFtmUGX}Z<KYRhM3?^L-GG4QFxMna=KW2G*WP-PV5S{7pkF(<3G0`0Hd
zkKO31x@@pwt7fURm_}3v8YZN<$DBYW#DRiGCf`at$sw33T|~{Dk=8;He<rAIIyO`E
zXXbq+u|K7!;m23Xw<S-0seH3#(tk_;rTHZPr|jOmK>7H|kp?fdSn{EGe@-16Wi{+<
z(65%ip_5I)X3*eo#@vFKu6v85|6~73&z5={b!n6_J$*VpJ$<_0r^`&or^^dZX=;OS
z&S|76ekET_x2b_omz$1H*Co8+>sPYnmGU+8Z>eWX`oEKt?pKm|B|H9HxxdtgE#+UC
zRvR3u3w-|t8g{*spZ<$5jE4LxrA_BGe9&l{>1hqTAtPFP8@i|awZWS%+sOa_hqy7P
zBwO~|>eX#}<@vr*zgN$<dCH$F|4Qw-C9gqG*E!wyujKRTvYT7>-&3!oPr0V^Uk#tG
zeR`kTTwXr@{U4{x{=dYl4ajEpPS-ErO}FRI^;M%Cru%-n-v1L^Wy_X7*M=?2_&>>)
z#)8`5U5`%J*Qno?yha&Yrcd|b^gRDJxO6t!uc1ffZ&`LD?Uih3*xQh4#IGdVNPD&T
zFUg~F{}OrU?zowK_1sr0Tl`n6x6)pzp08HE_<y;5D&;SSKV|b@u5Hu4L3v-P&i|dx
zSIV>bdeG3I_L%i-qns`CO{Z1I>9lb9xWS*^4&sUC{+cP6J~uY<>RhkkyGE=G4V}Up
zvce@Vx*^+;YtR};4Lc;K<JCZN4VgwB$xhGHNN?z9<Wbznvt`_<r}8$^#B1PN#?>{U
zihWHlUgN$A&f|5?#!2FAqBK8vtGB&ij|$@pu2mXj`sT+dD7RnhJU_tClW&3vaKm48
zpcJy{#F!IU3Ue*|7$rsg7xJ$}b=^*d*}Y8ZMAa^dGIo`sA2@?zWm7EB&t9X%E!a@=
zdp+sgxBf|d&O;?<hv-*=M!Mox1NmUfd9oqf$geu<m=4p^RKJG3(`AG=@+tk54#|kG
zw$!nut&Kb+P1Scxndxc5H^Ha9@P@6M_`;6AYC7Gpb2@L!a#A~Ps_S&WZ7C}~ucULj
z{#U}M>rvhRG^h^e-}k3wUOn~CwXb2*pDV8t8+l&6^go@lsqV{HI(s1IPs_hr>Lxv#
zOZ?y3*U<L=LeGEIp*nx;j7Ay%T}&NglG&oR755d^sOoa2l{`JupK4-1tyMRf98~i3
z5~kxyvkQ*8Ihb<(<_ntZfX#*MMvzU{Hzg1`xRx83MMYL1^SDG8h$>?e2ZnD9w_<92
zRK-%|k`8bX;gQ1?ns4&ZkO;0NFwern9G@J)o06O^77C(;NmGq)l23uJ73owPO?G`+
zHP+l9*~T2vxX(g7?y3l{sj`daVIHGoNn1jVt^%>Az*m@l^eeEb7aD;`6eM^Rhk)0;
z8q>;4EW)TCx-`#vYn6&$1R<N=AtgO(phjNBg3SHH6)DC?x~Idq_|RI@+RqybKUQhe
zqa@Go?jdpWXt9M2T`F7t#zt1qWJ492&8aP{&Z&@q5ZG9XEYuHImEQ-9LD0z8pw;%)
z?Qlf{#1l03R}Gs|9Pp62#p*46w4uyRP__9cM#J`oz!o$LBrDw<<W_syZ^D%ey)28e
zsd3X8sO<$5H=tp&XxTKq{ONeA!`Bb8e3X`8$XjfQn~y(4eDYZ>q*#)|((mJjhy~;>
zAZ>|I(@Wh%ZQ`o1$dLro4?RHym(|6l;X`T^N`q}VqxdR4L8=XSfH%<?f6yj8y>C|;
zh`gam0D>`S4Bc);+0tlf-esVkqfuTO(=Li-390l{4{^yiNwfv%mCFV-U#arwFxT_D
z%T#$13F?d70Wa{801se>3~9)*`-57$o&eAb)GP4SeN6W5Te1Y_V&ui+{F;~FiE8^{
zB)D224MT%dYiT+jLjkjE#D0p)p%NslcC;H>qyc&zTq4Jc(fHjBN-t2Aec32%^h8*J
zgZrP#JdM3Rv$$sfCNgb<=;f!#fl;}m!`>`sAO2uEZ;AZak8OfTd*&fH=e;wP`x7NJ
z=;tbFi3oSBlox=NE+~R8gJx(GZTCv>0(R9>KcNYtg=C@K;gXdm=NT1K7)(==s6u9`
zGGDw%TlH8BCyg?ZXPQldO7l=jiQyntVa<Zvx!36iT(`=jl(a1PfDEs-B8zS^WIXBD
zC$CyaW2rlQ4GOpHE+HtY()y#R7~@_Qdv~>;w4cyO=f-M@c2SfjdcC2dF*k5dF;a84
zPSq(jn@6z8hmh2djW}{~3ju2^b~)GvCEw%#syY@teY00+H!>#!58beg50{zmb>1=s
zZpEYIK!cDinsR$34=4~SAH-O6iB><c8<bg~^s<xLX?Zs{$Xj@4GTm`VUVATqN4qVL
zP5L#H&rV>+gycQiT>9MZEJ*pqix&cfcN0nmp(YorlSjLKdC;}<fuuYSB#{z{q6=g#
zf`g~CG1#fKlL90J)(qT76~K{TpAa0v-E9=I&4?H);XwpYJcdS+=@N2oOP#=e-u&PZ
zv_gRsy^WYrZr|vw=}ooV0Q{d%BNh4c)+r%G2Jf2Pt-&KQ97C>&!Cq5w00;%#Nl<I)
z!YDQsJSY@GX<uJ-vZ*y%mC|c1@Cm>z%w#CQvbEgZe6%a}qCRScpk(=`^RSLgg{1Yp
zXkws5t85K(Xzsih6@uW7CTycyToDhD%6t?%WPee_Sg&*YGc{c>ELm>n$w6p8MilMl
zd9<ZgV)r7YqKh#BpHt&*m)fzQJ%@tZZjvz-<q1*+-U|~;t>W`_ym6n0t_iGln$xaM
zskz<%iO$iG^ISuqM%+w_p$rJTg#eihQ)PAEC>@fMeQO%E!C*Oov}+&W1SArqeo+gq
zg=ucj7TR0;!^|wp`t|zivlbwafraf4J=>BYl3OykZtp0s`Zmf6YJ$SU<VlAzYY8!E
z9XE4G;MznNfB5!df<V(#sR-&(;A)<VMl|s<F7J9Lw)ZW8o|z*knSLaQW_pJvJmqYQ
zs90>39cLAKqqR6KJv1uT(oyR;iau5wp}$HSy2~uYG4BQgSz*`<^P*k}5|vqSwA_ej
z^^SI)1mt<J&KQwF8SrV8^I;{gcXyhvJMyt|vad?@KIYhq2wo~<^nGd`pjm~GWriof
zHs<Qc2fym-<7Q_^-fe>925=nga%kAmJ;)K&MAWrMMw261Ihz9b@K|$H$Kgg6xO;C1
zWI=-_R2PvRH)>{`=fmcTEe+0vYQY}k27Y6Z9X|R6Nxh+%A&A736+wZvV3AnOlJ@A6
zP8a>Oyn|M^O4713DvY!n{LD?%Q!Hb9KP3x74{-bk@vz4$zFiz@7E^|F9~TxRDK|M)
zc!cLo)*2eB0S#4hsqU9l&#bgJN;7(xJ_*uForqNb+(jhpg>f{BHPA>(q@*5_k{P4s
zPKew@lDm}%1pcCsOo4&!Rb%WVP^_b>Urb!J-F7D?Joy2cehTmu!J~nRN2X~P?TP@G
z%|JB`PLLy18c3p3@(G4&8qF%c6+OggWZeyEj4@+Ep_l9ip-0AT2~(V@ej}aUst!gT
zfGNoj8<qkFfRI9gwvQ<<eK38-LhQ8udlNC*^)Wqd0rCNY7E#G4G7*feFx}Nk0aA(6
zlv2Kje?CXxNV)B;e+?n|(JQF|_|MR(3agyhNKLU1#A>^RHzfw476s>{=s^x%jDlwU
z8^kKc#E_=uqQS8@azNO<Zvhj@lY1CyVD+B}PGn6^atu<6&&Br~>d62GbDmp)wAW^J
zTE;Od(10lc7(DYVn=6Qo5oX^5U_KUK>14?R#eydACaExGCk)Z$VHQ@aSq#W-`#gv-
zwL#%{u$l;OV~vhr|L`g`Worisj<rwvt@s!XPsPZ?sz|9o5ICy(v@3;K&PcL0L>lQ5
zcbO+>K<>`k2Ny->E6yk}I4dS_?F2!o8L)F~O2XA9oHtuM?$5F{dY58E&;p8_>PZuN
zexh)!lWZysx+GPrdy{SPDI28+&M&<4LFv|x?ZkzM=<2Or2+-p^#sva{&PYUC)0biz
z#V#9%*P>KAb0Rl1WwS#d>{h}wSeNk5(P=!7aIE+#s)a&k0Jdp$ZuST=YoLReQ_i14
z5O<N1)e5mrkRXb$mazYj#)lM_nxxqa6wDD(leMRlkMr2u)TD$A^4fjuB_$;WP<r7*
zDg=3l!wR3f3#4k8R3Dv0wHrz8c=G{{!Xi{ImZch2jTU;QPf03=;i+eN<i|Q4JY=Bi
z=%{yYQkrOH{U`9qVKf>73?0(~+6_Iq_XFZnyATX<sUwFZYOI(N`ch<}SJ6owh3_S6
zV{R<h&PYi*L`VLT?64)rf+!3J5t%2TWG&B8ae}gFm|}efX5fe}cp@XJNjo`>qJbd`
z34##XC|5zG8STL*VelW|nRy40D!xEEG7d}+L_lPJ5QrNx$*E~}l(f%0;S|i>Q)qI&
zPuwUm`em_4qElFudJ;cEP+r#S(;64ef>gLCP3c|;{M!`)gTdHE6d?$zjzQQIYEJG=
zTxK@irf;Pcp{iK4JldfLaz%5Am%QyeNVIgN1<Ec$ljVz&@M~D_T&`+LC~$mKfo-=_
z1>{3Fj1s1p1_W{hD=NAPF{1+4988N9M`kV40V_#t>SZlvZ5=aJ;^f0DC`D#PI!|V0
z4OOhj`X6#ZUKLQL!c0vfzOLf-Iq3p|+dzp?q7$M46Qlk0Nd%zCT|QtXG4_d>%8c*S
zmhamk;e?GD)I?Fg1|FsXUMrvnNeWf665tRKR%|dqKz$J=4Yyo*sA`*GeV6!~XQ-&e
zWhG6JYb#C$m1YpJLX&m{Q`bL3;ToHHOKPZ_as=F1WkQ|7Xi#JgtD4CFtah|p@EN$7
zU7uDqtfaPbop+<qL2@G*+I^$Yrc^@KCq~><uJUt+3)6z(DeJ`vHom>hVicgPs18a3
zAujtPsNBa~Kvaf+u^?3eoz|8QFM`n+<C2%6LANG)`r;-S0EPDQE!tvtrKJlp6|Pvj
z9u<(F!c0PjKx3%aisIa4C6un0iij>$Jeh!-eQ0K;z_^YLmY{4v(N`f<2aMM33uat0
ziBiZfJG{kIo=j3HBnmS^j0#0dWn^LonTj=B`w~Bp3y}&utmvXwXdsb~t7bqR6mX;#
zBciOjmfebh9#*SZSy1W$E~eZx6eXn6@Ku(klr+tozL?bZNMs7w!U&{I<MO)K5mcQ`
zJC|gLG3f4TzoMzjzHNzUL)N1^crgM8N<&%(m;^+7ACjgdkG@`88oY_?dbjVuWqHuj
z!g}qJG*#8>_IRm;2eT1Q<ek~!^FZ+u$yy0LNP-}LWbJjU6fCYI=`k>`)Hyzau#cUp
zqqwBUd^nXUs&!AMcH^h#RYHb`aFJ}z`bbFgfd|_Jq$4&&L=C3wnH|w>3=&30NRWUP
z>0F3D*?~UtG#3+=mSiwzD-+JK*dR3Yh>~YVQH_Xc<f(Bb2N9zYOI-8A1oW!}Ef#s_
z2B>T8+6@g-*9isW1#0cksMs`5j1(@Kk(22xM3r<so*;1O(ODM*ygmpoPSO{rPz01P
zZX7;Smt3o4M1vx)K)}w-fc8HyVGhlJ>GZsg&4|E^H5S=Z=KWZT;j)iZo8<%cC{yG>
z{Tf!GP&DUM8ZiQ0)5~MhXqoupCGsjEmdV3un?H{3s5Tvmu9H+x+k0Z<k}p#a$ClJx
zS$~_cCCD5(!vM7u8N}U-%Hdhu!2p6^&w{IuG#p<>@&xkhJ(uYn?xstZhp+)l>r%)W
z9RxWOw5T0Fxwi;4gia_8ij~x#GJ4>taPnBO=ojRJDc0PmbE=}^i>o?Qax@llMi-PX
z$R{iUNqJOH362_DI}Woq5*4zg^jbQ+PHl?_4{J%_8gA0(A>Aa0H#&r=s<Gcr!#!d<
zkF!IfPobbwk}6vc?FJtKg$~2SKubMXY@45$(5x~^dBTJ;N{N8x2rkGM0^I0aRC=uD
z2t|SH6+~4{$rYU@2DyY<3iuvqcb=MJn@WZ<T&VDF#YxgQYyhm#{BJKc+Got&f)r8`
z*W#-2s#3j&)0LKw3E|W-dM<Er9s)j1GtP%0x5XI2T%jN+aQ%iv!&Q|4=2dHoRVa(S
zv8k76<&M$^j0I%@f`V8P)%=j>F;iBDaFtV13AB5FKMEB#vsG^Ax_RaDl-v+#c8uQy
zUeS<LOhKry0Mj$QsZ3vwgw_QcMnn~8)#79~TJfTjg&93S;5pz#vQ|)Jh71s<CZ&`p
zp`IjQ`8_L6u+cVE<M^043?ZZ?A1s63cYEvS#R+P}qSy8PYn^Yq7Vf-mmbp5aqUZg!
zbZO)-7^GRXk)O!5nzv^~K1A=IC_>&p>3l4h$(5&^Xz|z={U~blZcT|R-O;`1b&uNk
zqGsd&8>I!-_@1ujF6Z2B!FP^p(H;!!*e`c~Hxx+?y_#Lu=kB6{P1<BPS-5aTEk`fx
z$TXB)fVbXdZrhV*^m7K_CiZF%hoWyq{&7zcuDkQ%;X1!F3<hQqI=3c#Kj3EZ?&44<
z{dV52w2l~<F{z)}SfW1A=UR{(5woMHjXp-xck;I7;oICA=VBPA;Kf5O%;oFE5xv7y
zr5RHqiCq079Y(L_fHK#{Z-D&U%Imo-cJ{505zw-aSJ!o3oUeent)~)s09%vy(eE<;
zeJ0mOUf5i^Jv(aXDi6%r1h;fbFV8@C*Qh?qnb@4#^2blm<7S6)!nGca2{jaahjdce
zU3XF;jP+%`$H%c_#m}L~v>*U^)*G=nbD;?Cs*6Wm>^U~~a(IgyTNmZ*qF!_R=V37B
zeg=6)nRp71i()>IO}ZJro4zs{>bzR3cizOLx*?}y^`lyffeEI!TDh027mp5Ln458a
z>BnLSgE%E~_d35dZ)%B)*mJF;LPhS}hT%26Yr!YOWS+Upv+)iW2l?z8e&OAcdDwH<
zb&iC^!^3<LuISDB>*yQhWyjd#&T${lLSWdjmb8Z<`z^iOQBhW}df=9bju`bsexx&x
z2bcSCA8GsM?t$US3n_ljA&Mm)=k+WU=Q4=fan~Jgap%NvEe?z+KZBu2Kki(fZ_gKP
z1FgN7CaQI?0`>>`8Zw<Nlp026yQUn|_=Nlivoa1k6qbEGE!Z;`dz&&B1LZ8rx(0Ef
z{8kJ9@{l@T7~YwVHbG}Ndgx~(N56mLi2LBoqxA0E{Z<{Z_UPKowa2aB<Cy)fn|Vyn
z39q@Q_xab{(|y4=cmBj)*Y14H%GP^&|9$Iwj=k<1J$Kx&U-ON-{?%b$TlJd5@;}_z
zGydo|=U#i%d*`>Vdf)s-FSJ~7z|)_&V$KzRf9sqp-`^h|SbO8K_mA9o$MtUxf4t&j
zp$>iY0~g&m=Tpt^ZTtLZj;bGc-*YQ=SbN{HPi%Y488@ss=F|i4nRW92`0=boqgU*F
z<R5Q5X7#_ntK;O4Z_{zx_SYZt!3(cHX5PZBmgEO+wP;|&7k0kq;+uM&UH-1aW-ol#
zlHvP5<`39-uD@*cJ3qAS;DZnQm-jk1xOAJoJ$lZZe@WZH^N)MsktdEn{g5|=(|`Cr
z)%Ut1{`2qmyZPGRa@=tC3qShe&!2zO1A9FG%|rKi{>yiN;fP;-c(*&Rz5B!mzdmu|
znYTRsh3EhFfybZ!;;*m$>Q{dHwXc8WxAUId@9rNy|MQO>@|*XKANkey{nN9jf8_(m
zops}Hk9+aUKR$8wf2{e>TmJ3W&wS;p&u)C_r`P}RrJv3{@vPt7aN=iwddl$+|McmV
z5C5$1v9Emf`nP@ZGmFl6>7Ks*URwLXvp@Tjz25bMo7&&{p5MLx)SvzCL;HR5GaVa`
z{OvYp+<((f97itt!IfQ0U;D&|KDh9Ad!G8xO?{6XdBa~nvbcHCLuWs6^7sGv^OFzx
z{LkO~wKwwG(A6JlI(zkpnjX3LM;#}=u<>InkGN}oICFTu>if+zPr6~*&0o6V$eVZh
z^+#T~Z~h(syr1eiIrH~l=)dNO=iYqHllvWd;(vVO=>^}re&Xj3?cM+L=RdjOn_vI(
zTW@~m>mQ!?<QK;O^Z9>RbI5OYS##tccFCT7;EVUpdFgkLANS&8{U^S(uK)WFto!M+
z|1z=Rk(bu?T+1<Y^^MP+c*#%pI{x0~^(!C#>&eId<+|bHKKao_OJ6L@<6j!y`^3-v
zv|MuVmD`+s(-ryZmv7AX`{cF*cO7~CF=sq<{VCf&w0`g5AN<2M%N~Bb@0ojV>br5_
zzxp2@`S@ENdFT%J&~rbm|8S3QpS=9FM;-Q^A5h=pKiGBl>JQ9+WN~)e&^`;VT)5AD
zk8;=cv3kGnUMnyC&ECBio!WEHti5`k`R*I)pS}6s`e%QB?=HW1?Acv@ar57I_wVy`
z_fa>_Z4G~YeQW=Aw?Fo87k~A!`Ja0H=KEiNz|FtEW!;m@RvmEH8M~}l;6HJ}(9qaF
zt=N6To+}QXzvr=sKXJjaw_JYex?gs7t~+7=qrW))KOXzV>Cb=akgmJ;I;88zJ0HFJ
zH#-lWwddS9e>I*T_gA-VwQR#}f4BYJ7j&F9`=-TjoBhnm2YlzJ9fRNbRQEIY{^YIe
z7JuwR%NCyV;bq^yVAg#HAHCw<cmK|9KmO*9W#eyt>yn2?w^_3AhxH?OdgH*6m;Fb+
za-Y)~<%<VYw_V<$`i=dj^PY=;-1*D_PaMC`zcssypB(IY;i)CX3v=7|uC2W(zxC}s
zbB1?ZJaf1_*?so%{zo4h>sf!*&0knQ)^}rm>-xukv8?w~)T@1gzqt9)`Qu+*vHR^`
zJ$9c*+mC(VUvIs0S=W0X{blLCbo%=IOQ%2GJ+Sc5?&EvI&Vw)3cRu>X^?i?>&|bdn
z6X6}T4U>Pjbi-}47Ix+3(u<GYX7P`1KWxd5#`7~i(UGrPoPA)y`OW<c7UuQY<G%a8
zgS}sNalL8#i;sTmV~g{hmz=+*e&l6O4IH`C@dNk%-3q2H_lc*xbMIxwT(bCkUB$ee
zR<_J(Il6Ps_VrHJdPr@buN>0bHS-O<<;5R!^ICT+`*s*yG;fFZ^&HrCY}?hl&*_e>
zI}c5qcfio(4+h+tANXC)X}z*1eCZ1R?Az<*_1kroTfgb`1EaG(Gd$k>nZ4F--8>kZ
zetb%;dx^VvXO64iJk;~PCkBecev@z4{IBH&&F8e%KHA~(1HK*d!+uhm_|VU1x%LfL
zxa_&h&kx7G=KS{cTe&sc?CiEWwP*N_8(+6!a>Fx&pII`{Q@l5SdjDJV;ZJ{YzJKdm
z>$7{doqPY$Z@p;4x0vr!{oclXDd&v6^$kUDc}+2=ylU2*@|sT9_lep*ZccCenmcNH
zvc~RHJ~>>D`@X)irRBi(t=eXc&&(rt62$R=1(#1A%hFZM9dVa;-s*X&|65{y;kJ{m
zxcQv$(e`r(F6jJB_ovEiFuH7Rt?K~3v^>j=@77e?t*?Vy26(j}>&OM}u+|#O05@K+
zhz!<xyINYtV*LtNUUB*D<wY|VPIhcni|^Rk#bf7&qGj8qMR;a3J{}$~KTy`oZ*>e!
zHhpK@@BQ@Ho?Bfp)V2Q?LL6`|KWO=+b3g9^bDp>CxnnplF8C<K<GI`Ja$k1L#0LvF
zc4f8N&8=?==~6>^8!OWn!bF4S+e<5RmPa?)=VpzfV`QM7jSL*M?SKojW_drW#YeY}
zciT+{*F=r-FLE`YJ9pc@p^Qzurf1-`az-{BTsWCmTV2m`cn9e%tgoE>H_r-jkX1Dd
z&vyMcHjTMwIG=t7n~r5k{3te4<>C!&B5o^rzZq#;@k;>v^Xwe*zk$>ImiD-Y4JCcU
zm8wsh-d+5I{{(ZhDWjd6&)6;%`sAvvuJDyQ?~Z5NaR35T%H`b3b}nh3WGy!`_u6fh
z6z@ieN7%we%8I=57P<Ddtz1LRFqjQEcY5%kjP&SZ;%>MbTsixRW;yN_iRrhl94^NY
zGP>!E?S`kFox6u)&_yKqkqZ1=l3Kjk<W}J4CfZ?J7r9Om-Bt*-N1Rv2>@E1A3;9vK
zyZE%1z#QMYC~G}IsAFf%W`n=N_rxA>=yojToXyIz3&NxJ`5e1ySp;N!V3R_of^WFv
zCxa1;E?ig9%tZ%ZRRTMGrc^pkj=Vxlb%6pvjH>gaVW5rxn|SiFaj)Z-K^R4pPKA=u
zzKCM;II1fLZHd<ckG&-4p=5U5`aiJ1Z_er6#Rq;^SkzCn0o@#Kl#QwttVRPok*Acv
zepe8!RX}nM><~jTbuQ-whjqZHm;%Z}E(#5}uueEq$rNIGQ-LOx!CN;8BbuT%%Py8}
z2$gl@0tb+B+=k2~5->f10e4k6?=$VMNi%Wmh+yO&PKS58j%dFh>cquTN9h!f%Y5pj
zsNhnv`N3h3rN^WrsGj_@`L7kYiG~VF!B2!TOX-u!Uy$y_qn`2ukYpqh^*c}9+F9DH
zA1gK}nUIz4p}eFiLv{f6W497Y_R08(6x|V*+Dif=l!fiEAzg06oE!A+;@y8EhIcpq
zcFw0yI`hg?PkQ0u1#7Qg^zS!*_>G@_>dY$_9rxvXPrT^*Bfk8FUw{2GfBe;zOBTGa
z_>8r`-T03^r~l)_C;rDxi#Gmh@!PJue!(wyIsNLN{PO+0yZBd2<~;M_f-4_?;NKU&
z{};Tw_*bXC@w%55+;Hjxzg+z9U;fF0KYV4;zdZNwiC3QT-Cy2!=GTAn&OiKW(LX--
z@NqYN<a_`7)FZz1@PcQ4yXYTZ{@I)xpqCu<rF&1j?xiDsdE-xx`|ZmoiC%o-Jr8Z%
z{kfOkxa~*IylKgU*Dl`Uo=X>;aLS=y-}bCCZ+Opx|GDI(wU;h9=Geope)lDH-d%jt
zsc-t+Lkq5a>)}`5o4>c{-{s`N8B{iZ=uyI~$L+FbXLiLJ^?W=(!P(LPi6;kMG+WQR
zuX1n5k8|xUm(#y456*YFEY6FWKiQQl{ypT61>AoMXLG$=?yfsmj~^{2+S`ioKwCC&
zXLEV-ch|TN@}t^b`_!}5S7*hN4Hta$<k9hhl_}fl<NG(&?mXA^j&&B@|1<I?v7@pD
zlLPtW<ZXkC&R<)frCU#T%-z!3-MnUYjT>NQ;8mV^tDEmOZ2wg*&*#PK7Iy?X<6y~j
zJ8Q>@mZ#^_xJ%X3x{9VupMw$Z6*<*c?QeZX@if5v2x;=vs7ld9GaYgbc@wn0sU%Y<
z#4DHv>id<t2G=)`&EvR<WF2c*7dCMXi&M%NIR+j}&e$MyD#^_9ES*5J-l58S{?pIA
z5*cznOv<kD2z7KHp*|z#OQ*4-e;mw>qdqx6LId74yP$cU`CAO2R@;%&U-BT&TFN>6
zp)o)(sJi)>QpB8Lo!>KQm$5%w=zPHv9B$K6m~#UcqMoFQUW#ksefK(9hd!o{8Cq5h
z`!eLbXx_U4)@s2x$0#4=feqjzL7Wq{{!vO+OoTA*lWd%%aG>n=DoM^6ETRymny8SP
z@FU;s3C^48^sJy<PhiR+?V_Z*D!>IvJ2x2-%kw6_Vbw!<!^~!$+iF8VU_$z-ICpM3
z-P<V_b_SW)uk6IHkwo6XI|->}2~SWC>uQWHIq7t~)SYro&|6EE)VxsJedkIg19^(P
zqJWBVhaH+kslEr%76YkC7VSb+6D7Z>c9$#CNAA>yrYc~XW<<2=`jU(Mj->bBQYY}M
zMnlY)<6~jI0S6Y!XRb8}H;5P_TM?32h7?5)xr`bW9)k8$Vl3Tw86w3L$R{Y52Fh_4
z+G}}(*%?wwkU!K8Ofy<PD)2>&pn<~=;cP8Jz#0qXVrs$_e%5OIA=M};2NeyF(R{q7
zHc<8`jmmlw&?JR}^yQ|OqOWu_)rhWH(k!U`S(ZiW1i_JK!xYdeR1Yv%%ym6iFgekK
zDP6i+3B6Ezr})Nq7#bW}GQIN{sOifH7y(fX8AnY11M&LW<&w>#Ery{NWx@?CZgF|H
z%L5zvy3?ZB%3#i8z^|TcwM-7<AK+eFY~(sB34nfkKi4O#Be(c_*rltR|ALQ2DCbg^
zS<>M{CqK3FOZ`aU=JJgzo~_`bl(soub*Keel~P?Es=~+zKRTcvGsvnXw%Ql<#|h0p
zGC?wflG2_|yA@c`yBMO2(Y655;Y1spX}mk;!os5teM%@SM0Mbrn?VtwhH5?$dFYcf
zfnc*VF3p0`T?!+|P;U3UuwjxxUiPZb=jcv0ve$c>ds*KF$?)pINXC<O0zT}v#<*^s
z?kD%Sx6<A@Nw+a=&R*Fq8_)|Rmm3Bn*=7mog&`XRCu3Y2-z-b|gOcciD%oQiiRjC@
z&M8MoXBST;;nZsI@%Bsb5$6%pevA18j7glZmCgZdDp?jydus&=wL)42m{Yo=e92`)
zfieY|G2z*skCP8Zjv4H%Xf}vC2MQy5F|$l`12kPUc{Dh;F4)g`ri*ieS!TB~0A4{g
zt+TAFP>N(lf(_z)W@t=;&h^xpGrgLR&S8~NN`VOw=oHIvGRJN^|0o8uR|GN-uT=Z~
z`V>e{#RIX+J0p}MAiWVt5q<tZ%}&iWI?%{};1GC?(h(cEenJduvTTuNkufvH$^;FW
zQh76eLEh+5yumclZPCR$y<<5M(1#dwOtUmNgUr<ya_DrY=wfpg&{NVgJa&_qN93s^
zv`9PPaLSjjp>UGfBIg0DMw4=l8yQur0nw8+7!{a3^?Po}wxZ-d<C*=tC{yf}aS3=q
zyBp}S_EwTKqSLIm6FzY+5Fhgg6-%P#Laes<K6jbtbUCpdwmJa=h;GG4{kAbO*mqb!
z^Ohp-v2LMyc}pa)2{Tm&E3#al{7I0jeGlYt#Q^2X?v6f7nmwwB`8Qs{)_@UQP!--m
zPXn-SNRWDzq0=zBBHlaKjRv@w*yqh=w@AgoLbY71ju<o!;)QPZ8qXb{w*E2wOgcZ>
zLEmv?aLjKxRZ_0p-0IHr@`o=qV4KDf>Efn29^OHla}$Iu<XTZ|-x8q(9y{q`SC}zw
z4WucWXbHN~(1Z&(VWTt}T2ow;bKwe)3~!9T9sM>(&ZT_^l+OH$f|ek)UK(p-#-)s-
zJT@XAx}O8wGX~G8mjz>2PB90S7h#|(78L3+74>Z<9ON}NcY`f8up$_3%M0ouq%-5i
z{#HN-RiOAjg*C=A89IW~5My6dDx+)f)}@QwJqnH#*V^`u+!agy1hnC7kNw@vE=I8i
z`Crq`kaFFz9nQ*#riI)#;x&?)M=zwKc^;DB*%tZ$zT0hoDP|<*Te(pm>5HS0DH7YV
zp$;B%a^tyc&qs?%Smm-%=<~+;?7`TZ7ctL0l`TB`-kNXQ|El8CoUe>=^<{K0_<S(X
z@CBQ-!GQkqfVSWr*l1Zhy34!RD$_86N1GgT!@vw#-|TX#pQAInPT%SMSTV>!KKg(3
z&ikiv1p5g40?0@=DLu>rIZZR_TAFvkxV5^rcPI^oaa^`>>qE42<$`)z_vm&psDF`1
z_Tz*M`@#s0Prwg+jFX+XN&ttS-rR)~u7@Nfc~S`zk#^CYn}yON!2YOZn}BwE#Ec)j
zY9T8#x?qz#&+T|0&C|-F;m2I}%yS?x-*u}*d-fm*q5snoN&_(2Vg+VVw4bi>E+q!#
z7h>S?nZqqbyS_nc!ewC*Y_I<Sf{z<{NYgT7V})AyZOIMUn<CXkq;E`1>34RrHxzXL
zgYX1J5n!vh8hgPs*SNZs6bDs^LE*IhiqWc+SRoBDh*%6)LMg?yc<-=l6T}LoS2Pmr
z%cB{#R)R9GAqFZEEtNBgEnmA3&NB!jGCPVCpvQS32}EipR-TwxrVuoAQV$X^MAXc>
zbANZM;rh0T*1c$}qjx;g#+aRObYv;9n#(G5>cUkJ249Hg?m<-ArK>?`=GBfOGQpF9
z|A<tZ1Ou4^mR>HIYK=smLahN}WC{YbWmG)YD79`?^k@`Y=c+0K%|#q&v8vq(TX_P9
z=g>3(!19Vw$UNaPNYP!cDC#ji*ra4%j%WBJvP6h<SuF?8M!gFZQfI<3<=~t*5K@f_
z^qdx2foLJpUI-&EvGP%oTIKEZ4l@w9`~;|SJ{{A#nzH6R;OO#Uux<`Ps1xK<_sFGj
z_x`m?iW#M&ONIodajR`JxEPv*t-O&!qf=v61z61rPw}E+fd*y=kB*U8S=QE)EQIUE
z#dJlFrhd~#Hfs!?hp$?Tbmuq`K}7^nU?OPA!z`7m>SADDSybOV64QqvwPcSAma3pC
zfn7a6%441iRNmaSsB}IW43ZSJj3=rE=i&&>2rh<aSEwnb#=I=o1pR#BQW4}+P9Q^q
z%VVlN5Q}aFX0zAELp<hmas?~IX<H!3Fb6bG3ZwD3T#m<QPWl-Q(;Qm8(#mlfT|FqM
zmjhXL?F5VH??7|gB-q7k6|6Z(5G+&`=@(Tdv2A`$$%tTw!3u@Z4Vx%#4v;!3p!z=P
zh~kj!(HT5=<fvo=DNz(aI%|x_p2F@(m0<$YOx^~JgCrxYW(iHrEGZrfi0b!#5;^6{
zFiVXgA_O-_qNOTNQdF3_szg0W`It{;O5RsSL=QF{CZI8|n;{;_B*-~DN90hNZJTLr
zb+jmDfJe;4)nQ>P4?toO#Q?m5%=YXxwzSa)X!Ul<lGm%GK5&ENBH5iVG1bmLJjjv>
z_~IWSM-V5Ok-gc@_tc+^UtB@#Qxz(f(d8ALaIsZok19p^IYA5NqNFT}uXanR`awnz
z6eu5)W~@-#!-{B}ZdYQGV_HZ#m9BhV<E(-XGsgrpqB)63g?N_Z5CZMs+)|DS7i>CJ
z#)cu9mPMO~@*oL;ykdr-+tN5!QCc=G+PRU+oJ3XS^O<tBK|=>|lx`WrFC5|%GTjF7
zE)ITrvywC)Qee#!2Mx?pJ11$1F6$uzWKa~6wh%?O2l!1#Ll<jMniFUREpob)vOtr?
z`v4A`Lz{!t4FXgMl?(Wyt7srcPKCNyo$nh_(M&?jJ6;v{Y))K|U=<FUU|=!{KJi^6
zW)iIml?}GV^2%7N(`hFIda4W`Ow*So2AAUsduN11IhgHTxd;@Z<|d&L?-oBtt{-1T
z?21GlUf@{oa`KQ)j;bDWymxK@Uh)S5s)(RbQ6myLp?cbmC8Z;55D0Z&maZ{|A}YUz
zupsIPTyK%Sb0Dl4i3Mp01l#J4CvvI_lA|R)F@oWvJ(3Ly1gYxj*#gnY+NqQXro$#^
z>p~FZfyXI@?1Helq{L@anLSdHX)#0uRGN6ip&Rl}MWj=PG{M4Gnt@j+(<Bf%fF5J;
zrB|<Mk3`K$^rlRSEgV87QiS6v54xLSptK4mnRdPSa&J%!A)1rJWD6>ior%B6q$yK+
zET8fwNczA{FXm3jV)XgWXxl5F3|F$*8mvZ*;zE_r(|j~45L`h<VWkf#4^*piMX4ek
zMNA!eV0L!~K4(<gUW>YD+?F>Ic>Zi3Ych2UgM|d>95TF1LprSoMtcZA?hk|du%F=~
zU5M#ifeRb8EXNW`6W=R{mHomKRGJ!O8M4s8i9L-`L8e%>_vxTIn3r@Xr)b_Y6JP_(
zGtIQUK_5QSyhAMT3Y0qtNx%?hVu-Bo29=^>YF}xZJZU<VR}d5wMN~9RU+CBNq~b-y
zLgv+FY7^M20+1ac5@OCVT<)||w705u{3)RdEpbHo*)SCYAn1u+ZTZU;4atT+UokW+
z8B9Gz!C8?KRWr{#s&ordRR?>-Fwhx6I;&^uL8MCYa9LM@m@@VX?<vM?LKUt-+eEBQ
zPsBDXbaV$dfW@icR6kKMTH`d{>#=EYk%z1ZD5wB^_$C%+{H8txLrcySC_SrBkqPNm
zRr%)(y@<y0Q>Q`DK8S~ro;e1(0U7vI=W8@fU#cU*4Y4YwUKJ}?U1cNIj9W6}POGAw
z(nfKjCr~A|Jx_J2gYaF(Yd2uqg-Hc;M{|(rT#;$8B&NKXbHgA*6e|H<Gb0=8sV!l6
zUTPErh;br_<jz-|fQfOF&JpQw!DNJKz4BB+(4&Ae6HJg4ttQLW#sxE^ShbO0NUw{K
z<Ecn2kU|rND`k?cl%gUSE&oqiTBN^JQe!YG$UPq<wcR~g?7|*eq{vNLm<Y@rl4`u-
zu|4mXKuWjJJ9{Qo>Z6(h`HU+0P5vSUAtjlGwdi`hw&?JI08>3Qsbt<3Qyy?GQYVT{
zDM5UzW6CHxx68@Qi{PS}0lZT?fAbD0&4V+$HFnS=@Whrsf<$U>5S2oLo>}%9YU80Q
zwwB$Viq{mUtCggC<0w#l*4RZLbddvEtZFa7Etbefmmwl`QHkv#Ci|=W8A)b^=nBM3
z&{*?D1&#Y;yHBa)w1Hk#39l<1-<y>x+CX`{8D_?ji#S$zkyla(HL%F~tZNPt20F#B
zHAy~eh%h-sb!3BFZ5GE<T90h-oWE%LWuH5f-V{kU3sh0*@SW5KfJRBuBMaLLagoj4
z{??8sq)9Px&0_8UBW4u@0(z6#SP&b6^9wG&3TpC5-B4{YWP{g)DTs2Y2bq)^x&7!{
z_(2%fS9E#ZrVt;*0Z=7Vz4GbE&3x?#ArnX>;|Mko*ukQ%)u%KU-Qa|w$m2VYU{1QV
zi}-6eyx9d(gvEqa6V>#)590qHW$y!LRaG_o?{nrb9>y!rVZ7RfrfJXhg4c1dD^X2E
zwC8fA%Q)(l&_+PKBI!tjp`oII?ioiKiN_{F<0Z1IzoEbfkqq%qq*p@YHJ=_cEAuZE
znwtOWQPU!QziXd6Xg$Br`}zIW%-MVGwbx#2?f?6nv-i2i^%dy<FCeO8gT%M)S%F|N
zV57EL1O~AThZBf@x>HI@BDG}7ki<GuKpe>3OPsM<DTpzofw=}EpFio-u^}pqpA(YT
za*d=Zyb-amIuJSA<($Y<JgbREyzpVZ#mJ{a{PZ5Fn=lxgP-j%6kMRsLFiOvCQi-y=
ztBt~aGR1|davC|id020pg4|*7yP+sUf7gLp)W!2?%3mcTy}8N}2`w2Sw^5EV4ZQ4L
znwgLqwQdnv192|+-kQ#VdKJ|ce2m?RM~=^C4B=#it8Bhe4NTCKbwepiu+<??iCBu@
zm^2wEFqp3;&kZW5EQLG6<DGIC4olUPd2a$q(4bQ+k>3!eu{JiUtkoR2DJg%5UT_il
z?oVk;t@Ja&_<V>>@dWV))hV!x0D-KM`BcpghuCvyLz7iUbS7N??niy!h0+OfL4OXO
z68%ON5hhHi<JEv#7%A(qm7`P5;R#+4Fd2A+2V~UcUYEhe;*a6ogynwLuU{C+%}=9e
z_(8`OSrpeJObSBB<9Ai+@`m3)8VGck%cECG8lJtffx%@|3xAgfP0QPhFx>YL1RVsF
zU$#;TRJb)P`k5q(WRwcRw!M-f+2mVgWXU>MHszx9=HVdGXE<lJI4HZa8%U^@+oZ?Q
zNTL)@s4Zr*G>JwvMy5fnPFPFqB1-=oDp4ozkaD$2=#ogy5H-Am8D7ef9%f|2+J>rN
z2*He{6vtJv#59Fbrc_{l3spY_PoY($p;0b*J`bl6aCMnskB$)T*0PP1_D}hXzg?bN
z460#ErI!fP&a~gAg6&j?WtR<YqS8TKYHq`asOGa1YD-mPq*8kg&lDqmnizjVewwl^
zD&S>}?_|J{h=O(bKIElk7^Vy}QBdzCB27UJ%AFqigLC*Wou7z2Ezgsc3aP(A13e$5
z>L+7^m*8BcN*_}4EM&%XIrGs&<`8&<CLirnCiPA!KD0`AKh&>wje0&cZMdzyXVz`m
zu1Ra>64xATn%J~t)+5>TC;d9Tarh&@TE2DSt`(ynPpp{q*Jx<#(PPZj-*4{in3w83
zd+vgs;Y{JlP20z0&R^V|IDba6>+0dA8?N5DYj}xiZd+nXvu=D-cMn{D?W38FT}^F0
zQ@SfVi*uiE96vqt#pXoz{A5@4o2EF}*cs@R&C@bVlEpoZscd3)e%0{NO&=eg)O3Ea
zQ76pj)~+2s`t*U}<C}tT_MI;k=QTY!ke)I$oY^(4IJdpY%xHRg)uJ)i59FpN3iBkt
zKjk-z6HhlznVvlN#P$^jUYxe#iWjH7^Q%|XI}iLkH~$~+<mSKm^yMple8JS^w=P(4
z{@Vu@od3s{rvGEdmdpQf$6eD_-12Vwid%1KI&jaQn-1Li=ceBKzm(|x<D@Z(H|{yB
z?T>dZIPk*F3l5xfcXQ#5+nWo2x_#I5f9%{f{f|3NUh?*v3wmGOanD1;N8i2o`$w;z
zf7yYJ^Iv^s!HNTu7WBOOndYw79&hgY)6LCY?JJwR{$ok=iZ{64T(V%>t|QLccJIfI
zIP0yI$+O<Qa_0?~d|_wv*%vQRn~z;!Z#{O+u7}5M-1W=R8`~cHaMP|=KRo4;?$1v<
z{U@JKHNSLd;)Yj0DEa*zH9!67%g>tr^f`yMuh@F+v=!U7O?$|`s2=_9;@q75H?%K%
zrFru5EyuO4n0`V1`TL)1Uh?<-SNvnkmho?F`;V8BcmCIbWp}^Q{rZ;Q%ztUurAPMu
z;v)@hzx>jIwtWvZcl~9>f+v?QUhvl67mqKzFkyW0&Cl+*d*8Yp_q>}~u;@ScFIe)#
zvU?ude%jp|?>J#s*YHd0=TCm=^b5)#S#ZgJAKTou@8;&>e?PdOOHW$R_0c8G%l1!d
zUa@fH$=im{Td?i>hXhyd|8UclfB4MK=JL_sYrgo91!~9P3xXehblvjm2iG6?$p@Qu
z?f=ZWwqG_+n_0ay_w>B;ns0dWgJYWCohRpBMzI{3K6l|qj$3fqmF*kv_nVsD44bCy
zW$^jd=G@Z0Uw8McdZoMPgrB$X`c3`Z%l`e@<e6h$O`dte=B3NNwL7_@Z&CaH?>;+i
z|DJtwFMHyVWcmKekxjqpYi?V&KU((9rDMAO{gJs{*Wa|D_^YcU^P5c@uf6Y;wmHuf
zvh%N-GQR7ZM~>+pecp!XyI<W94LrAT^*0|HAO7zpi9NHq=FA#1f9{Or;?bXOp7y;d
z&C{O!#Q3JCyN)a#<25&L(_@-n$RrofJ#6dx-yOL=c;|#laF;%^IQ96{+Kw5ytrv9U
zrY#w}HT4(2c?;i2T>Z$uef-*AoRw@m{R5v){;X$O@~$>^CT)|vmx|vW(_LIYCc9?!
zxu4we*u*)fU4PR2)7CfSmOj{DTDHD^#s2<a`TpN7Y`E-|2O2KibzWoeV7WPYO@E^I
zd#8tsc8prk<qypb%@?BV??0O?zUJlT><*?Z8=N@4xNX(=;&y*S>ZVN_Qg^Oezk1cy
zjn_W9CU_`+Qev><i_Kl1ozdKtJfwNbZJ%wPc406+v2fD(=+7rLH{W*nnC3r!ELfaB
zE?9iTg3ZD1i9^BF9reYD<nLoqd;9FV_O?@_?WyMu-<5jfv(v{s&^*22{%5i`%=}HV
z`Lw#uHM1DQ)K6YwaQfRyu<(;N2jMZ#huM?s6Pc6t%x@Z(i=tzqWH{#3AWVF&vhRrW
z@cxcUu&8sXNhFpg6W3K(M;KopJJHYd_N(6iwa;X(shUjd^U2Jl&82YcFxxWD4Rh&t
z!bQ1PnhH&=U8j2EXO2z(Bp<Z*CxR8zljiK^z+7-rSeUjsn^}6ZF1M@>^9@6Z`mQJ#
zigu5)qh@<SJ%e&-d$42OjYsG{?}*^$o7Be5>4rzv-{d!szKZW@96K>ubL=FOyeysc
z8tR+-^XkE&bL!Xh)RU`4lD~J}U>FV)y+L^LaV#Ad72C|jVj`0aQ$9-pb+`)0jjdRt
zhxhpt1LNfinXx(dOrq!y`{i)Azi8a=nfJ(>zt1p1uz4tp&%EPj!YSUiu<UJRS{|G;
zuHoj>XN?}79ja$l@H;kRzj9o{6xRfW(I@ImM{BO^H$-_pj9Op1DID@<djtM%4+EHV
z{b))b6Ggw3EyObAgq_}1e!sskom9s*QW1w1SZ4(OEPaFR&_%0?s&FGy=NIJ6&(Dpd
zIi5OXKvJJ!29oVOB}6ytKpoq`Ov`#?>99&2UXD~9^PtakN21K3IP!gyn^=L=?N;i8
zRd(SSzSF#qNvxjlrhHH7vDb6EZ+T3~b@*$n4w$bScWZT3m2E?>MJjquCC2X#RUPY#
z@e%27ilPtS#B(G+R2%&Go&Vt#rM|{ZbR7$Yv1!>WkqN%GTLo0#`mtrsrWmb`FK5-b
z-RWTTO&QzJ|HL$wH2$~BnW3vpI+|?Q;}=-<Q3Yr@^P}9R!cXCU^wdC2C9jg-$z0>1
zP30=F>}cfXs*x0jcc^gpfRd@)<#(K6Ayy?|C>uO?<tY~5#JELPpHgku-yHH89HI_4
zT7~;40|Wm)%0???`4gKy!Szk9S^eneI^1#*9?K=N4_CT0R%s5|V^f`$xS?;tchyZ=
z4Q1FbVv(;r^#ODQdEyO5YZ6*H^Yg0)u+ZxuUwX7GTgaQNlLpxX!!n34`I6na(OS!`
zSEW%kQiqX|<*qVP9#R+_D>v+67|q(t_(j69d1yCJQ?3fa$sJDMkRPew$hA?J^G3UR
zYHTzHGaG5O?jg}^M0t`SB~Q?mo^0iP40WriQ`0Ck#)QG3jy5&cr`;F{L*xjWB=csm
zpMfxXl-Ci2Aq5omX<`5?j-2_~eS%U3oQwZZP#_!-m+u;5YK>WttYfuc5>hl;XPM)0
z-!D*Q(pvOLG)$DR!+dcK8PQ6!3@j^0koW`<T4Fsew+%vBuzoH9*>>@MXsHFN_(W+$
z3h0_c6O6$+FLrro<w*r;XK)HT+;;_>9@I)643{utmJ{e4Az+7g<p3^P_=j0@xlG40
zWbl*Qf2*uym^fMKJ6Kioo!EBwDu&bnb|xieq@0{umfOA%DU^XSa(t&nC`8L6W6h;J
z_RmCY6skR#h@(f!fg1(Z!?*34eT!NipZWRi_m$dkVBRhFtZcn*#VMQKT>j2ei*Gpa
z_$@nE9(!Hym75-!zwOZrZdlj(^0d=_blp2&+H`vN&2z5UaG>+{wv}6+TJe=TW<Pz;
zoT=A8*?If4i?=+w@{6}$`OGV)x8B2<p3E6r=FB?oy2s_r&pl_pc*nHg-m>h>>DSGD
z;+5GydiSi>+ozrM^66*(?Yhoq?s?>ed(OQ1x|L^by5yw0pSt{pU9;~(_Yq6Z+BEx&
zZI52Td8519IMeg)mp08lbK9efZ&>&Er>C8{<;;~=-ZA@`d*-y>u<^kq(>}lD^pzjE
zecluA{93{vlQS;6E|xPtZytNYlMhZv4cL!2w5d@a?~=WaHaR7%Cb{oP1nu127rp+b
zp_3^8(TRp&bl6lb_7|T&A(L#kiJ(a*#&BkI+M<)9reL(6%;+&;In&7A?Iu+WsMf8A
zB)i(Yrgk$rRZP?kMZ>D0ZBf`<EQiTNTaNn_?&*y>vfHRcYA{e6+c+Pv&#3W%+&3n>
z13jfQQHKd%H#C*YY&74?IFJaNHnxR{br{GajxY=p(W-2a*kS$DR+{F<tqFDHX78|d
z#kwZiNQ$N+`5orgHZ?fV5IwE2tFP8HT>Ej2M%sZD=U)MqgA6Xt#2lmkg;AP(+#LTU
z;=Q05L9HP9k&q0$?}xZcj!=RTM11Q4vFlLh9JH^dU(SU*&u`8jOls5wo^4xIaeYE_
zH=bdfw@gEFPYd`uECylycEL;B3j6dQFYd}JvMf#LRo)r|){Hjr3va-)Kh78kXO4Sm
zDS+ru3vVVcy23p-rulkoWO#^}V>RN!$Yb(iFvmAGcQ{C+W|0tBRi~6uh@~q>SR2tC
zMJA8Y5RO6eJf}aW-SEbcG)k9UY#`6Ehm{Ocfo>rQ_UCzJ>!f+<=1>`9sCG75GQ7Zr
z$!uZf`ICpfw2Y&o$0$FC8cF9fRznQYDZ10bKpGE{n<&#_U<s3e+9np_<-@-gN}fn`
z^W76IKP#a08iI28#G=oW^Qi(v_$Hzp{BX#~$nU<t1@hD##OgX71=b%>%!C!fPNJfN
zfy?*K9e7$YC8S``5kTtQ*oY+pCRBmNGGW_8Wq~*W5=Q?-!n4rj@&V2kr?TU=ici&5
zRH)s+%mHW1V=76cjLJ}V;v>oPn8~5Wqd)T~eU#uTX)`cI@CQD61UMByR1gi4lN=Xu
zv07<30M;2|93nwKkEPmXT!mREq(PLCdeu%p2bo)>&W)q%$fSu7VeXkOY2CzcsUU#E
z)XEBD45ipZMTW;C65z~<jfpa;%B=4aI^!rT(+5eCNBOSU@@NuuV{(WnLmkw_oy|oq
z1QlKmv{@Hm9|#nwyBiLHLu4)$9xn)u-)D1z)9=(cd}-=%3y*P|2(Jb6xHONVjLHhC
ztT-y31UZ%@cpaBKXEUUf8gW^T8;3+Ib_r@c&y%0)Fsv!Hl_f}6h6u00V^c9MAf@U_
zC9!lBVS@Quf;Cvm{gMi-W!)qhq?rVDrXVc_N!AG))gSW?SV%_lOq|BBYMdSUyc?E=
z^@jGRiN}bVdaZyo3o{ABr22#)sByL`x}~CD2F@n!@*aXStZ<ghl^yB;-{2@^Ng%8u
z%Fy^=ftQd4iIuuGQcoe#@Pfd)g7B3!M2ivb%)qk;gx%Amqhr+CwZsa@aeKi<2Pdug
zRvY;dh%I49o+aRM87`l?^+AMNG+0NT<9AR(0+Gr)<KD+l8dc!r{+c?`L*Iifp+~-{
z?ovr6eaj6QYh`IiK~gLBk`vcY8ObBieic~h(+1jDTqA89{aRG|t}`@fS?D>#l&p=x
zr0>MG?t`x`MtL#}k+5X2g|@EocN3nY{Gvz}12JQ09ZndpeHqZh=m;h1q-Dwa+!w_f
zx?{Iu7EnjmFoK{<>?fXkzr1I}NYaZ=NU9v$(jKH-pNDKEN>;_<8!jm=pdu~MIMm3(
zL&IP(0nx%DXF@XEen`7^+i-%YPejn<Ec$5dkR?wdhSxMQ{#&hx3u6;xpo}%~@Cg<P
z2e!)ei6*O%QNf8pL=YPWjkH+NDRQ`ccqO|mi-bXQR7eHT;Bf>BQUx6xCzMz~%Faau
zqS;evA$GXhR$4+rwp_+zcoBXNcIr>SQYn!sgK?HIPaNDtjr1`;FHG0CF;EugXqM6z
zKG7Psa!aR18zjdNSjiProOK#xHm%+7#T;TQy<CzD(18HYVuv6jWWfzrqtY5;fkUT=
zH3c~6QgMbHH)BI1wn;aj4CNU&WOx8+$bAGXIYX{A`?!8NzzGZ*amkI4`*E#nFRWuk
zfl65T2Rk^R;VUh1nzo0hX7#~9{{yA$RAD>`uvO$prUS!@)vrhhkg4vgY9{L8;T1<-
z1<Yjm0DT)NNvo7POpbME)#!w~S`^2LQ(l!r6a?68?QSK}muAqB;Vq%%=b_Tn1(ik5
zWgrxX;%&iUy!Sg`qj`EL?+>)Jiw47i46lfMtHb&_;yKabp-ox(o8bnZ689>IA$NXB
zrPj+&N_Chr&7JSt!6!ve{aI!&<NB`?ue`~`jaEE(!MCc_V{(>PyWE4f1XVXi@g@Xd
zwDsHw502t=GW5%5`?597b^IwMVM;Z)eoK8Oh><wRUdX6C8Ueg3^bIsX4u@9Gl?;e3
zEtHR2rGD>*4sVummE>u))gcBpPAhZnNInqI803}F+z_%-QFZq>)aSH<!}{AjW7bi?
z44@RJ=Ia9?Ln!7^&Zv^tySyhGqx=afJmdr;dvjB2KxLRfePvZ)kWbDq{$(Yz+NyS`
z6@b;DucZM~ObSh!20OzbH%bTnR;d*Q>WPT(D#wmZjPC=QrJ0Nd<w%Ch7<gv`67hUX
zV{Zd%_ZFR}o`U*12w9c}Q<Ku}JR9ctg)pT}hascu==G!v2WMcd($Z=N$peEF0{}Mq
zhEqUR4bLch@#|2_cU=0=A$!9N(tLH3HJ*vm^&$yYY}ZWtek$!DA1;auK8nd^Sj<Yk
z`zTP)rE}R<00ti>K5N)APw|GCH2Q=sG*TwA;)n}OEd&z~s{xr9f*2#)?yN912rq52
zAx~S*pwBo4B#Cdu5uhc-?FcLuVJR;eiHLLJjj%CCsW>ILl#g3*kihUCk62cSadVSu
z@?D5NsNHzyI2|b+PgilY9Qxw;pfI}xw)Wj#!Zl09RLLKn7{w3qfmkUAr=9Nyu#H`y
zQY#zCqEiIo0I_+l;gb?k4m=(E;#w|bOI-pK2w*`x4We975Xn{yns}K|T7)f*cSR<(
zj{;v!l1G{E1E1j<&>~mr)}<0tIC=+Z6m+*{iGQm?6OrMP8!eb}B2fU1@vHzbD2ssy
z^XzPsBh|u!A_=>I6<(ooQcrx>_Baky6&j7w(7IeaLDc#Am?0*KT8$th(~W?$har+m
zkCzb0=E<@E?LJepGuA9)lT3?%c5a*rOfWn;0jMAwWwIdjLZOT>NX>z>oH4TgRzBVk
z`JlYD#&g-L!}nkmJ9MnU7UR6i{STlm-3>>(8kO{QagjLfl3Q#^3ui!wA5mWt0-}vL
zg5i-#>u{;N?Z1NLG%%IK77#{Gpy~`!E_24s?u3NXX_fc^rG&$Me+k#y;{pLqsm3Bi
zs@Tc|EmoSeB=7>JUTj2?xEh*|*f<*%A;>>`zRHM?G~~HxO(;dI%q@9nEDD4HK!9}!
z&U@4xWK3YcBRW9gHlowz6X6<M+}I~24B+86EVtu9A91eIaGe3Mi80Q2n%AQZ0VjDx
zJ6ibnYE+A_l`7&PS$ZTMQ?XAQ6i)3piH*Ux_*#_VqFvTZPN$HZ&4gkj{B0FJO!nW<
z2f3UIl(Lqz7GJADOC#54W46GNF~@<CrLcp7v_&}CRK;{zjfq(0`x)&rArujSq3(*E
zgHa=h*p|RLk;PyOh+MzuP!?m%uyh>}1jPLg#Bh<u%i~K*k=7D($@g2NXk?^tgZ_J(
z;=GHjGTn!GrzEDTU^upSgk4#Qc99|FZH!oIxuA-<PFqE(e#az{F?gotr=4BW1{}Yb
zGy?FvFNBCVdE}mhNFWZ|SWzvNv}0$mk}>DK!maz{E5hN`%1CelE2c+M&p?+rS_Kvl
zAS&k8u^(DT9&uPBs)7p`i9Z-gU09cZ4jzm!kN7?X0T^*e#OlxW2MHQ3wn&Dhnu&Sx
z<<Q8JXe~|*8c$;6V&Q`;&#pA(PftRGOk75&4s>9h@0^-!T5wGu_mPH}8eQI(XoeHS
zLPs*|)Axg%$O%a4bh_NhNKwnBC0$g7UBWR3LWn<v2qP$<!F^o7B^v^fAxZ+8OVW8<
zWGN`d^S(50N5~N661kvYz8j}qP?8@9cI!7KDAme!kXuBwbV!WT;*eY)o`px~?+G$+
zNFGPh8kM1r3aqHkcKlAZErW{+u~!g-W5r$##f`afOojPR6KA-@wc^$+bEV=^3a_sX
zt}5{Uj(CSVFT@r>gojTwVU}3taY<O?vObc)!K&IPAwY9Q^J5+hF2G6>K4*s^rB{xR
z0Ub<S;b|?4Y%B6>Jt@-Qv?)<5cDeeH_?*+=6h|G-hBQ=<MXTHqyYy=*6ENQnx~lVs
zEFrm!v)wHY0_*bb86E5JC10*CuRjY;$=^X}024dn1+aB$BvPY;KQ}DWsTUa`0+0a8
z*x<oI0yjKLU)C-|&_`fIT%1Vx25u?TJlCwaglw%CpdgONBU&(5@;sMRzOjx#9(e{S
zQJy$4hlJhOWo1pN-9rx$;UVf^QxbMbhVt6T9ETkpP8}oSk^$Bk%wVD$BWlHAh`LeY
z9fwxNp(BpA=AS8y8`xXB%1-x9E(}R5cDXYy;2f5oalslFRDF^f)v?XacV#U@#X&G1
zK38yfVycl4sl+$ZZ%HEAHLN;~NUP-qUuz;YRm(ET<iQ2@)#gD^uR{nru2?M#76;mo
z{n#a7#41Y=1okvnoR7GM^Mnqbse|3Mlc26<N1E7?`xy9qL#U#pIRYAyGW`Jzp6ml8
zIdN4X#2{tJeg8<1#}^JA$)syyvdWOf5yC`*$PhdR>5BzIR)X>PT#JkOVlLtL9GV^>
zFrtj03uV_RS<a6TBv8X+o9+8zkYyz3Gbj8H&`>NFISSROar-6+QR=ezqQh}CIgID8
z8ig>uQNXzY)(Rp8A)}_4!<16Xpmpyh;18IvBuW~24P@QsfO%NZxUUE%P$#8exe%<~
z+BQxrQzOz3g6u!=Xm}%Y%)y9U%#WDb4N0v(M@Y?KvPH6n+qDv@TNjGY(Tb4wSqmC}
zD2Fyo7G=6|7I<ZjOFKSE0BCgPM=;V59s%o?P^5EH%LrA%4%fK4mIuKFIx-ShE3mk6
zsvzSVh%9I|CZk(RJ^<KcYy`NOGvrDOzU^V&Xl_u-IJKB&^pMa2R%4zPgon@-@newu
zA&dVQ8ftk(L=09wk|GjgNBBK18PDar0V8?#26)Ftke(38xC$1VXH;0R>^1V^Xvo@i
zp4hH}a7Kf$YDo+nk1g+|78%<88!*}N>*632mbIaVDla{h1re3vOG$}=!fWIAVA!S|
zvw>ET7$|^^Jymic9Arv+_dpq{l?I38pid?N2SyI6*cca`#>$f?0qb0)suZMe2pYxM
z!N}?{T7XOc;YO!V{a?TcqndWxK^DqR6L9w^6=Z6uXU1Iy2Wcn71%$CShB98VhFc-Z
zWu<g-qMz=q19hL~enE<tzQ-lmwh|E7$Av`ZekYgo_3A!}P~^&GL53y3#PMKtxwy<w
zl_wYkqg2_FSISBG*zX&q`UnD{Zw}g8QB^1kg3@XTSCXJL>c{JI4_t&G6?-rng65?k
zmxN@oNgi$suEle-EEFU1M!>TY5kHOegIM0kSU@JS(#CzNwU%RdJd6YaGPYUll8~GK
z1aWr4E<R=Ld$|!KjfDH*(ZYvp79D}`W!>OInxR@c6-Yh)cf4kTSD>S28p%URFBN0s
z8P!No08*^XW!sGu%(PmlN*ON8mFIF?)*&)lIC&CsB$s$(vZ;;V#7Tx+JpKq&K(w?!
z0|Hns%3pYey#{V<)7ljj^@4m921JUcvCsu143Ib3^WwngnZ1*#<FM1^bU0>%7^6pI
z!E%sI*j=71o+Tg`P<83vW2C%BvM$>+u*Z*^ozQiB&m!rpIMkCD`%=(aOXm<U&edAi
zP+k}W=n*mx(J^uR?J);#AD7jEe?Mim7(6HEL~Phl)=_SNG=UnERh2n@hCPyu9N|o!
zH&|_a`iYF@Llu0#lH`6=jUCJTK0cJ1D@rDLcXJc8-N<aQMs7X)yy6y>B~-um*&nEQ
z>`kN!q5;ki)gjErb;QTGivDZF$mrT4LrE%X&?;~4Ghtv=y_WVNXN@r<_#9)woZNW%
zMwwb_M1b7q%DbU#l=HI#T1Vc)6y7owmil?^aS?-hi6@g390OH@XJ`tmn29{K&{B66
zF=}6+8*Wq$Lll2>o8o)&{3c+5W>Dc;N<3vvzhskL7>?Sb7P0#YVe~E5bC!1>Zt-8H
z&yzycv;E}x!197nWcybw4=d3+-c|9AhoI2Hv1R$3suTp7(9}jp&~GN7CU2}{Yb+lr
zWok|(e8rXkn)Bg-B7U?g8Gj6Ig281^V;Q}am&A8tFWXQ6smqn}d@wbe^Q3Tu3Ft<X
zA5ESklt19cYJ;BeLwOab=T%^=GN<(OBRl;n7-FOo+o+z<Z{(X?Qe_=n0h?_5L)B7L
z^+nbmbw`Q)A<v|=B0nX+5q{)dCxcZL)zz?J71_w8ZGD9Nx|v8w6KD9~4_4+Ut84?$
ze!auAYzXi>7E+2oByUW?(Zf2`Sk<;48(VNhUIV&Sw+X*dR^<+@%&AsU*pf%xc*Ii5
zc8D?TL7I0-g=0KQb*;<4*88+hWRy=Cr~&xB-ITuqO2%1Zs|@IrQHL__NU16(b+;wH
zk*diXbv4yO{jI)l6xNr+!Is^T7Wrd+LtZ#~)kBM|C^bXg?G}yg%d3XHjIm5-t;F|j
zVtJHYsQ7rEQ3<gNi0Y%np|r(tiqgn;kIi%3vC5p@$9O&`X+J*kd^r>HayLqhHTKAf
zD+YGde=$@1cE6haw@2)PoktH&T(vdqnY&gM=dQKU?MDxszOyA;tb0T+KlBmR`MoqB
zJ~(P~*Ni8!^JhFBbzc8H<zGL%x$VSx+j~!(ryg9pQ_a0<$L8KIbyj*$%$GaAxicL9
z&7GTvubi<tv81D?;fd?Zm;dtmMEj(UuyV>Q-SfEL)A`8cFgfb{RQnNM%=XM{%!W@i
zcD5eBBsKMjC2egd&dz2}oL!u}X+o-X$D~B|)HB2E=Sphr?Gwy~+b1+<&zP6W&YEXl
zyd%?<z9Tb6UwnS*nDb|-@z-Z&_Fu1U`LEANe!CuJ&~G?=%AN&({99)E*ZwrT;`(dW
zEPLgd$`#vQSDjBkX-|IO$?Aev546qSf7jNzJLhg*@V$AJEAD-xa@;HHH_yNHv9SBR
z%LnK0|I_w~C%%67aesPu>T!R4#vb>|=FR`La(MIfS0Bn=@rRA-+*4jJzIfJuZocQr
zs|TmQ`$pxz&e@r5KkY!a=hZiQ7Qg#O?~C7kIlTPI-t3%TO<TU;H*L$Op7oOMyzGj_
zt(RRfHT-*1``pKSdvE*4lCG(LTr_U#yNix5er3U)hA*#3OnoB=r~Y+L&pq$1>}vhQ
z)UM7?E$C{!@XCi;zx?UbH-C9j(+|J>iNp_obSZJ|>XPUGF8O`!5~WVweDSnk!ScDo
zy#ps^miK=#vG7lS*V8v0J$S+W)5FC--K7>>^!S?j`<~i5w=!e%+}kGW%fENOI`{Ws
zIRBg<W#?abSGKtC@6iQkJ=fm$z$Z3m_nw!VxNrU7;6=A*d;hR&^P(5FRu-PIsQCQ#
zCxyrT^>*EQ@%IP!tXOBJe*T8y;@6Kzl%74J`21-nWxF5gHS>SjlbZjF%Tw*AT@m*D
zwJq&`rFVSm@{?0bAMNeh_18Ix_Lt{$r=DFD`EO9a7dIu^|GX?5|L0}J?XNFu&VJzX
zru4;MO0<6JONoYy=Qn3BY-{@At_g{|?wl|t`{B!}*@xxa%kPe7n#g{+P0bmz)ta8?
zE2Zadu9P15n_6-5I=kY;{r2Rid+mZ%2i64JUfr6!_3_Hgudc1k{Pp#=>D;#~sfpj-
zT-f=wF!+A2I_~F_E608PbKAR){$kX1?&`|o7oXjn{!?Xh+cT}%wg-B9W}f$2Pw+{*
zd3y8i!7FBdujlz!z3lH_&1I+l{Q91$r(BY4{ArjSfB#APqEki{m!2}A9R6vtZr!{v
zJ9kZYw)^KjVdo#0hMh0f_q4usZcppqClschGp;bcrKi~X?TktP{0mXT_rDOeZfY!~
ze?PV0|K(GXw>oZCJC7Qu%OAVzV`@%Uk1p+P(52_^R;pN1%exAy^S*?d+qcb{W4^K`
zG5j-~A6TmM_f53R&!|`3dK^FD^2yD?j$5~;Zhw&Ph<-ULww$xQxb!GpT-rIf=s=Xs
zR@*nX?VVc5R96-KomI6gs_6FOw+7o@y3Xv|Ke3oAOb+#)wZ+0q>%!=Plg#qMdD*#z
z8R3ijKid;-TdHRFXT!PGo@}ZbhQ+@uE$ZhkDrWaxm`%TRTF^duMW`!F!`A&v!=9Hu
z8?`Pj^Uc=FgLL^T!T6=c<`xFpW4D$YT82LmrQ1JY2iM;;I7Z#ZV0O_<jA?_Xum6Ev
zp8A7spL&%Y`1(z1L87ub8g;Dp(_af`KlrvjdGp(qf?8Pd>lW(z)=Iu>-2>TZ)H%8O
z`g4{xY`ZKwx9KiE%gRQ}BPU<fdHr+cL}tHQ!zSnc{Do8eQ<k%bScmCrW+YmFa$zRD
zDBo31yxCR$%$j2Br`n2s<K+5i;KniS-}&jx_6N`F%60z5WYuM+^_uUS)(`$PuRidL
zIevKgoSVP>uu6aX5tCMDm}}G_rO}6eMQu3iXH4~%f6Zq$zk2d%(b|t*%s1h`s_dZ2
zHncMbsI`(mb^3;{=oREGd&E`BuGczs>;qwA`fGNMcc`tu=J?RuHc#a_-=e(d*kigU
zJ@=}rX*j&2J5)!dRE150{_?D9G~GPdX)F${Qf+#QSykVWv|WA4&};~OUJYjZbDZ>S
z4Ajz9i9AOpJN24S=MrH!Zf$+(@UdgY_g`8cRi8^lW+E0{#(|dKsPO8enKO>!3{fiC
zZ#kMgkXG3v&WQT#(dtn3MH3a~@zl2Ak24upzgmB~8am|j(a?1hY%p$~PNuf8P}n@b
zs<_iMM^!@aY^6@QMhD~W%La!HSCqHUMx&Y2!_TUE=CaPnR5;J0{KMGvcx1lJlBmM@
z?@E1mj;>FB)2QI8aw7Qyt&-=mV)L^;vt2%6RK96!IZUtyjQY67@<Z3>DnGT4OXfx9
z_|cJ3tBpyo=`;S<XM=NAyM7@xk}s-tJ_;8aHR^MQeQib$9%A(Bb4{yvmGKAvALTcE
z%cwDT82^y5CBIG+t}}coS<dvlbT2b)LvXnAgI}mjigVH9>a7~b>XK>J$k`inl~v)1
zT8$zn<deN|6@EX-ve2R)%Up&xwhw5&)s7_0u*Rsy`XY$t_r|@HvM{PL%P<Y5eZ?9w
zG1+jmU6xCvIf^xO+W7J*3sEXEqQl8B!K>1gy4<_^R+h%99-3XMSjdrw{<1%i=5;L*
z?%i6yQ4QZvtR`T*TGgpTxM%N()W8hoe&=WHbswEhO{$PZZ7`X7fX!&^uScdQXMR*0
zm-TSug>xSpQ{;w7w%fAKlx2sn^2CwG!b7OQ%3pk01_hWFSTDnBQ%me<7E5_BNhOOg
zo~LQS<<FA$Fwo>mjcyQ`k#BI2Mgn|ga?~q%Cg&5OI31pKKGH;>Xp6BSLduAv#TiY`
zC7Ye9vG98#s0mzN5GNXN6gcI~51?z8Azz@9F}G1maM1z5(`YiR)C|8{WR;Qof>^Wo
zE{VvASmC*VyYa_1ClL{%n6d~}SrDYySh9Oo9cc;3icjL@jJkYF&7hG-0$3DpdW-Gk
zxd$<-_8fyEl6b;$0hDJuo}?GBWExL+jHDMc!T?mw;Ig#~&v2<6d>Ws%DwvCBJzfJx
zfrmAyfy+R)h~<iNhXE4E5j5CQ#<%bV_zvRq7B=ESb+*%_30jH9cMhH0BM<U>NCM(Y
z60sUb3nqDFuQ)dy2C`|92fr@H2xC<I+fyg5eSP*8Ra)$R=co9$M=w~rYu*bxPg{Il
z?}?i(Da!BoY;<RSenoip<L}J5dF`W}FK5o+cYdyXb~eAI)5>q@Y|5Ov<*D8;-Z5Lw
z^lad_blUhWoh8R|?q=H~KjO^Kv+m5#;_DvgjL$9iT>Ro4ZExQ)XIATVof~#MvgO^g
zZoa+kvX@Vv#hITCyPnu`&&r#xTQYCcCA0XQpS8OlpLEa4|2SgFiJLB(#qa!VSoh!(
zbh|S@vu>WVc<rtSCuA<$a^@0rKe6rg*0l#ZZ^4#W_bb0%EP0eOFwL7e^K<JZ$0pd|
zrGpIpma9CI*kPVY>}T<mG3sPWZH|e;l4Ve*_0P}ATSabrXk+pjhyq1Tf0w!m>no&T
zgg)6*s+a5Jimy(-(GOd>ze{_wLf`VZL(_A$YF*Aq*JC*X+h4C*t(O>|@ly@-fA(JS
z?PuuQx&NIJgxNYqjKhPVb%;bh>H7oKI#~s)r5OqTS}thmN>HB$J;vwu?S~+fIa>LM
zaZQ5eB>C-{gOS+|GW1WN4~ASbA!&_Zogcf1sDbw$Izn>(NUDD#+V?_~hXY;n|A+Ul
zb~y(7KiK}2aPWE8dlB4t%GrWjS|On}6SzKBpuosn@ERS$P+Jvc`BRb|uZm9{vbQlK
zM=PNPToHQ@Vdb}V3dG7Y33#;+D<#FA%ZP6=q9;^Me2#;*5QEQWDSS@R1Uxz5d5R-y
zDb!FsI^@zC4;5%AAc6a1L`X$CggMK^sYoDmx~QV%aY&)g9g_|Hk{Umnhs=I~c(Fy3
zo~NMesCU0Z8)a17;cq0bL?cak%qIPE#M9XUEq+c)RR(5&*(-oYN@@t-!^a+tXVX@6
zASH*nM)|ZqlnJNux8o@HI1?KC*(7U9Gv5&h7LF4`kTi-=U!CNh^b+GK-}7|%66!>%
zRWL%wKZK!~57<iGP2^Z^Nqf3xPvAx`<~|#GC1k-23^>=;c+{W^Qb8<TRN(uerQW3;
z<DoB(4akkl4=VZ3AsMS>Ru-^g24TJ`BN&r0ONBU!s)8H?*^!EoPqD?36pW4Hg2^dm
zVlG&=BN-Ui4|fZQkwRc<@M2u$NzUp(!~{kw&!QJV6bYgCNeF<zpb?VH)^aH{7CC_l
zoCSs$r(cA@>2RCr7okwnEIPRnfz_9w<^npDcIIhtQ7Ir@#m7$3g$=ZM6brbzb7J{M
z3`L5?*2yOB8ZLp+8Z-3czZG$D!*|;Rq#e711im}-1EZz$7?|aOxFO75Hc>MqxB$ux
zLS(Zok0Vo=GL~Sx5C@fRQvD#BRn;CO3(z-ENl_T-mk1T$@s^-z90;^+dL(Bg>iJ{2
zhYAOV3Ip=aEr<pOh^qaJ4$l&OAtjY{G4du`#~7~RlAr$xeK6q*S!GhLS{W_<(^y$=
zxE{{<GX&PcWt22!Uu?JvvxULBhkvyar9Fx)Yi(TOv1pM(mWYWn$j@cN1Plrn<$*k8
z8Hq;sApMLzrmg{t2GSC)y%aTllrMJ;%Chd(WWaLPS1LVYlvZVg&`<djP4&6~K6fVM
zT9H$QUsYH0GRq>4G{R&hCdD~ITBWIDuESFP8M@d~XS7#a8VOn2xkU>WD5Z_<7guwU
zVhGJaU$W%8)PXWZ5Q_qho*0Z88o;uH5C#Jo2^d#2J^V10$;o06&}uiXZ;8wwW5|WH
z3GG{i&gi3r#KN4kWyS41T<9T93<l4r4vp-pGSsA`))0YNDz7YMB{wft6(RfHPX<d8
zHI_D%6~yB*h`ZTkQz-FIb2iD{05(axux6I}H_FIaE}a3MLE}>5`1%Mq1*i)vH$p!0
zFj*AEA>J1dMwYbkw9>?ba}`8~*pVj;i^!HEDwssb7fyh;1t-ejZor4+%+K4$Qy>v)
zxB(#B0#ez&&XhWG#)YeVqs&UNY5uHH)*aL|h5E=qb`aL(jGgbKO2ZQM9E_EZM*&w8
z_H>~@Z3H@3KbH2H6grJ38gvK+7Ea5ssV|a2A*tlGDNnCyxdderlN@0c0^D!x3C1ME
zcU}eSbHO2Tr8h_-Y1d?ufXh3<$R8X>iTSnhly;W!>0KgsKzPxk#SQ(@l$l6j91^gq
zpNqMcIQbz!`d&(9Sy`Z*V&TrqxHc=izA<Rme6Pt8BJ5nbX`|pd8XDG-D={e+E%C@C
zB)O|6RFwot?lsAq5gc2Dp-a>&V?4ezX2Gluoi3%NM@w^h-)cX~1*Tu|dPVB@uKUT2
z^&7OQTKTA&dRW~UsY0EWv9~ZbWZ-&OH4af;=|Rmy4`mP@@GRZDHd7f*0;}}H9tASE
z2T2_I)kYQ*+xs=$RLY(lslt(ZrX8K~M<+FfOu3AT->s4J0;kOMI?L``x{Z_{jV)MD
z_YAN)E4j;R^1!=~Txcmx4!T6XZBfN8GK}(oG0pc)sP5|vW&adVmhlhRD^;!3DlV$}
z8omuiFYTbs8-ooMq;k$jtTYs?Oicb^SEG-A&X5$nqr#}f$!W6AXyxjcGNb9NQb7qO
z8jTdXsx+&72~mViIW(iy(JHK3p1q(0Y8b3R8#3hgO;l6K=sH4-r0{1Yw;DSv-(H=s
zm0y*HA2Mi)H;UayloM~?ij+5^ss)esR~Cct2RpQD??uTlAZgS(We;_&Qvx5i<YW{n
zhqQqRgQlSkeYMDLZ6#AKWiR)o@y)W76$bGzrYzM)jgq`f>{!YeR8^zo5W|NW;K;&4
zx85!B3)YeRN&?I&wMb|7l&Hi$c<>^I4bK=6gQFGS(a{mujmMDtv<Rm>Xbs7{N+e5q
zvV;x$OKCkA$Xw{d<IyVmRmXU((zF@(9uZw`1}n|>Wlsn)vi-_KXSAM%#`k_0ssbq@
zV9(iVG({*j1Y-^DZnX4IUl+<s?fV9^ug?2}VN<Hq$2#C58N(<O!)|a*V(KWcq$z>(
zoW^*DC4We>v{5#%<XzF4BR!s9MPb$$YFnwzYo&aYnu+>rL?>S=RF<6KVUqjxY35kt
z(XRb^$QJ4-1LDqw?7fFF$n?803KEr2p-A|1P>DTPlu`tP5;l~EfM((65K2P8l4pt1
zQl$>#=O7_lJ{>8!5fB4_ChQd7NeXK6gdkAnLX@eUPZ5&zQ6TWC<VeFW4^%o3A!vaZ
z%|#?2eG@<cFjTH#yumhvC2mBUB|HMwfN9@|Q8ummLnja+RtVI<`_iEsA`H+3M4sV7
zMg+p+PdA5BV;Cb5J{RbSX844{+f_$*j=|kq3)0ISMsfphEj>kuV7D*L7vh*QzkU1#
zka%9Pv`D&?L9W<i;~7Ns#E{41J07@NVn=M31XV115B@0-lTV1fAfDS2tUKi2^=CYz
z7>H{{LC})TR1O41v|V41*e4__j`9tTrm(bf+Qdr6L0ngsIFbbj6tR@3QfmwpE4lzm
zhX{}suB=dM;8IC8`Q~Ji8q7PoYjHzngh_d(1<?|Y`DKk*75&Z@$c)XzasET|r7i9U
zi4zLn0Z4@tW$@rWOTr?<ieCdvav7qLmPBa)!Nzgc=_9EjT<+jolB(fbaTL<AW6)&_
zislNWZh;|UM&ZT{f;}0I8e1*6XfrMwK8lPoh8luSb9EincX0+YWJd^!%Z$e%^TQA<
zE)N0a63f%>_u=A(D+6gPNk#=}`V<F)0vRJH<)lIA*Ho||HL!*p`>M=bCspUbE#goW
z**J_#5-oxRT4E1M1v@%MLaHERiN}wRp#c7><F^tWTN`6>ani<Az1EOCE@PCzi@{iY
zl-JaeRs=e*MQLCXVPk?;y4KSyV{wfO&q5X(LZ7K%lrTw9RME8G1Cb=Q8956wuyZ8B
zI@J;1T8Syfc{UaU&Rib@4aS0%;}EWvcGzg#K+Os#h7mt3qlvnNYE-qu#IX{xDk!vo
zSR&9_49J(35u0Vc3Ph~sBP%taXuzPdZgfA&qa~s?9Q(%Q+sK`h@@fSl@y>{dHyW0E
z4<<gqa5<^4#_{-yH$qMXj**~cT|(l(tzb}#V)~eXB!d_5oNKUC3SAWq4yugMkFW7m
zB^xz>Za}rLJHrUjYAevCW6g2VAwz8~1DdsssZ||3BcP=aNJ(_UB8TsoSCndfCN?YX
z7A}KTVFR@0##NNQmtS3dPl+a*>;j7G)AD^`bQyTn9#t>6fW|;E*^YHllK;@!z!>Sj
z((?=ypb85f{TA2O^1%S&x&|*v9lb&vd7w$ea~612OM@j`(`R8h2#B$wf$#e15n^rJ
zb^JU{FcP0bFS1lWas(JT<<3Dw8cl*xv6XI0^dSx@rSZg6@y&bcMV|_)E>2Joh9m9l
za4MM5jm6%kstiB`a$>ww8?R2vacvm9T9y>xT9XV?6o>=eA$tEAn7d*^1+`XCY}ew;
zYln_IahSPr`?y4{9Z3+C9i@d7wedz<?MMUSTDfYnGweJ^xAM8jz7}jPSf0!9XX7%7
z<B5egLliNArRC)i=oZWdnx-3C#sk4Q&#vNcazGXWDr;WO5(o~G#pw9f6td=$#kaE&
zMPjA1RAdo3ToMKck-iC<3-h~~kTj=1wL}>%#uu$)dETjn1rTH%f@2&)4uD4J8g^PR
z^jeLO))J?=M!-0PuE-c+!K+;OZvK+;7qHAP+F`M5PzL5eD7MGZogF;uiupsS%e()A
z<I14IxKT5}80@Xq0#1M!<HGO|=fDj%V8R;(+#v(PGZe*xn+vnnaS^c;7eA6-79(q5
zlCU&jTuq~v0=2Na=0ngEIReJH!YB8TaYz<cP|A2Cj8T=M6Pd^Xgx>+bwMNJw+=+@c
z(hbmsG>TyKK^4ABFz9r+S)+qA2PGLqFpl$O$N0nOv_0V$(|y7C(p0KU+G|Lm2^;>o
zM$+5<ILl73tN=!U^kS?Y33q{5(jFvGN`xh~8wjOtv!u78LF)3f$0XJnf@cLMxsz!e
zE>7VfRzor|#phcj#)B5p`K>uvobR!d-}iu?Czfk2k2QQyi?R4J0y2=Av%zD!8&0Sa
zF(obw@yST2ajEyf$Il5GmyMGv_p2i9J+Oq3VaOcgoz(FNh~aTkX~fo!gplg#S|`Xt
zbP*CMV4NEd;|S9PsaIp;At8=+Ec8=nx+@gK0kv=~n)~1wbnKb;M|)1u2u0g$jrX6u
zq69~nSg0Q#N5?l$l#LO+o`IT{x{l2i-)M2!%Zp>h4#V1;a?gOen<S02Y)vw8^1fSV
zAl4u_o4Ko|#u;G3k~{E@47fyMajDcKMdUh`flF$JNZO&q1Je2h^n3Rh9>IEqJcM84
zBAT%Y8jLc1)IcO#?ADST-{5K)U)`W8G{6|=IWrIuMp}s25>I+QA-B(9iU)>WB2+=8
zFO~%rd}LwP5=(L9q(~V7!FUM7LuLnL%7`9!;JlA<2dc@$aqn|k^oeq(0kUxMECU(?
zJ2@6}3@cVZY=HhAY<pO#9}FA}OZ@w6BVhO_ARvnz2a)Uh4n<I$G850y6r$D2(EnID
zy4AYoIUuaou{%dAD~~1t?ZR=K;4<Dul$|ElieAPhgI84oM%FYAf({7@myQXf8NrW{
zPRvX;MZ<EnG!jaK_^MDf=`h|xqq!I(qZt98kP)J0w=V#@HGyElPe5?`kP(6vCoV!w
zoHjI0d`YC@7Ag-EEIX%&tg+M3d;_aAQ4?nab}ebGawHX=4MMS4%AOUah-0Qeu#}YM
zzd_;!7#sZ9uZSmLXk($&<0F5QAgKc9d!P(cE@UM_D|Jj{n8Ddf<HWkO)^S64A83*a
zyRFf9pcQj<K)@yffs4dYfg}Ve=K(I`C^%XWBlb9c$qI-so)gj%W8#vGNi;G;c&30O
zNDRK}lxd81T$3D_TFmjWFY?_wBwwT38r`Tck6`w!xJnj2Y>4$60>(WD2?Gl*;0!d}
ze8*tLvnn4A#(B`B93Y?Xhq&v*cB)WCLk%QDnhTP&=^8lUQm&39?SgS{2+fdUerfZE
zyl-xi^*j(ryLR?TJ!d{9v<`7La2@QLLU7=$w2oi0Kod>Nj0FbJGKr^)Vww@@HT#lE
zOSG65>$0#d1h2(AYMxcK1uJj?#^NMh@24~Y_O;@MZXIonXtJfaTnGTya3R(R?)rB;
z`-x1AE$>&Q@~-rRGX^@W0Lgvf2Q(Pq`m|}3#F{_g1RMJjFU3%CREbfNlo0~fDgi)K
z;T|+2m1!YZVzs0qD+Uj+)p#s%G^m*X;t3)MaBBiV;D>I(43}$1AXZwZh{F_1P|}1+
zIR`THWg!Y!N^~$0mCE3$DL565T>M(8Zci&Kb=<EKL!(r*yvG`K9V2CyVFCrO6_8Ag
zl?S8K4TIY;b?^>FYU_g>(U_nci`XdNYu&LmG8wIHVGaB(<!t7$lCi_eHy1IF1?+x2
z5z}p|zmK0-X=)6Dwi$$5FiWe3<fyQ>d<<1<848bJ+GIjI+bUB%0y`36LncaX?&wh^
z$r#O<cP}~BvYfs`DeCRThGZQ}y1gowq>z_(@H~pgD;JJYrRZ3?Mv;Qi#+V1u*P*g$
z1OyjF+1>$T$f-tT13PJWzp0ez2ovoVpB6mjI6SQe!b6omP$`+V&4f$H$Wn>C6Mwr%
zcm_XXmyJ}BB3MLv>117O6|vi+u>25V!`@G7k3G%mY+>R&&Y^gElv2wUQQy34laJ%6
zAX4pF^v)(u?tl2M<PITsglp>Y%k}igWoJ`jVYaAMy$zyFag8!s+S42aTB&R70c4Ea
zU(FR#i1#$|29N`t`VB{m%>DtjZZ*#zB6v?x(W0Tin!E}ItIC!~>u6v*OP(V9)P4DC
zF^>0fRYvCvp_NpBW{{U_Z;C)*DD-<qn{e+#5jo%)=9-ZALMG@*CW}K>rE;_zQ;@Ci
z^q;imTON_G4r9B+km?E+vP@eS`g_J|wXaC(!+8xnHszNGGvT;`(W-(8<U#z0$Ck)Q
zajoj(>p8g~^d916@KH{`rskt^nMWs8#_$)}6z7>x-9+0dDD@$%*E{%TJY`e8n%z4;
zQNCo&Rw=786;I|CS(?EEj5*X%eMb3G$-$BEELFPonyA4-x1KUBasSlx3so)9-?YkR
zG*3YpV>@UAa?U!HCI8%e>T^khhNuh0WUXb4@Y7Bvur1b5roK}9GBk{Km3b{t6<0-h
zt@d(;XVMZm6Y{_hvAno<oyujFs3@~UoBz!jpIP+R9g|eFb&~EmgZ<Hkr&aj+1U<B4
zf^O@0cxZXoJT>$>+sa<gRHEYJI$SbO4L({4R<EmM!jrzD6H9(pUO%+GF!=EHj6VOw
zVC$q=<#63ih18=vgRM)>Pi~%YemQ)4t%)94tF})#KgfOI{AH;}e4TovQQh{1C53_E
zNvZ7T8_VHuxc$v6F~N=rfv%ga!WpxTeSMNrJ2NVrHCF{E%;nrshA)O^c>FOh3OnX1
zL)`OgrzpMXXY`E|BXfNwI`ZHDp&HLzFZq4>P8wHJ?|+)^Czs^r{O27ydi~yr-|11s
z7w&Ce@%Emu^z6^0HE;ez?cMoAbl}gQR&Tv=U|`yc?+z?q@!jp~-g-)xcKjkaFwF+$
z(~o_8%#yDh`QXZbO!;>A+nJ|UJ~8FE7yfRZfAZa>*LFSI_0Y;mrF&jpX;%E>&P6x>
z*SC6}zy02*|J7r=s(%_<H2$_jdzZg@XlBEvPfvU7Pse=dxJyqmdoG`)r=Iu8-tM1$
zx|BZpLtTqL^P%MGOE3G--cvp_)OymV_m(gHWc2Yj+ltGUwEF%zUm0({bcO2tBa6S^
zovb>ayCU5C;1w$W+{eQ3z-OZ5*`A8->X7_C#psahD*sN0xqZ2y@?%|E|B0yUnjfg*
z)!TFPe|4?yzAuatkIqx((L<xRZof{w)pwfRHUCrg&iQkvB-d@%4-XxPf)A}xds73^
zwP*fOn={YJZCG-helonhwC$}+Gd*u#9yNS=QdmrEN=|?2j$qkKhnLek{$A{P^OvRm
zz26ESe(39Z>I3!DdN#~VuD`0B+WVby>DoCHqOLPra*Z7y$}V3yj=h4XrOJtmRsa2m
zr}n=5dE-x?k}4K*X7UN?)Y2y>meMmXEtcnAWYQgDy7eD@^<Z^!Xx_R=<sbcGN<Dp)
zO0M8(>F?X+T+Ff$((RJ3Z;6Kf{kLk}iqX+f*F$RA>#s$nw*OYiGygpoy?l&X@vE;h
zZa=CDmpvA>Kf5Ipy#Ca>!Pov_2eyAF*Z$~+!kCvnknFtk-Qb2h@10V5eO_Tq?}z6X
ze{fINwGV$i*LlD<&Ap$TKmYuB=7!5oDOKBE(5o+LU$O6Z;}_lZyAQX|S#q!0@YhuD
zYyUBQ(M^B;NOte%Cl%_C{!pU(Qxk%zADtCG_VQtB)%OqWE`H`1wfel3^LsBiQ~A$b
z&|P}BXd3^!se8}Q7AXJHE5n{Iu2ij)J`xsx%x?SM4@=&jnxz=&?>#wsxM!t)^s!rW
zLp@*9!SeM{Xx>p>r*6rq8wYjru9G6O<OEf?xFcHrJEf*<e`;uO|Mr1_;at>H`Hb%U
z#l6wvySi0k>;KACX%Fl6{iu6y?t{fK%U+zb`>mhqRd;SkJ=xU|965hmvN$@cR*l=x
zU0!yUNl&@FySsg=YCL~#&(Z@QET`XW2&<(qTFu$JrB|lZ`12+dAN$eS(dx>_!s=n!
zQbS>7*fr^t=(r2Vho#=GsIlA~R^Ph3)PHq0G-p1e{OK#Z%hRtYwcg(Il2&T@M)Fp^
z{39y;ho>@Ki&h53-f2N`)?L)*xJ6yP^E2VrmF$Q)K4*4~HNmWPfqCf8aCTd^UCp_C
z*}(QsEi!vQ)3v#}H@fWyXQ;N{of_<`w6_f|x?;+zrI*jq<-WqceGhgGe&H5XfA+tX
z?mT9S+1q<&(O&#~a`hK_qspK6sJH9`MfI^`P2<_umok^18WqofI~C6Oph{nQSfsb#
zrS`pcXQ&>_mg-+QL#d-@nBuvci`l35M(H1Rsq81NQsvo)hU!mSBLC>)8-qV2RIy4v
zr+t#T%u4>YeuP;d+&tO$Uzo_`dYn$Q9L@caNB&xPkzP>AY#|rryo~CZV9br1!-5W`
zn9|)GjcA*azjGiQsOTuW{mV+<H&g$<Z(26{=*5UNivo6N{{B}FgnHEdjO3%3LXJ|M
z#Say;C(Sp5W<tr9v|3pBby1(dJ)OCpyXVC!zxAY|ev!Ga%>F8Ky!!n&K9JIneV$)a
zIyF-3+g0blmZI9o8POfgJ=?X)&siO+^ZS)9tz(+!C4ZHhxNQNq$D`<M!Tc&qzV+lJ
z82Gm+-21^G*mXz{oO*oFbZ17{@rky=w8E6~lp<Ge)ZP2637YmyD^4@r!4$7OXv-I7
zKBiNCuD<)oQog%BtOgILfYs5a?gvz5{sL7FW=6wdG1?#Q9y%<sD)PI{rWX^%(%Hdo
z=Hyl0n(p0wtGgF|!<H6S?+g9DH;WJcVYqvCOMR5jU0ST%_(ZXD?ZocR{G+9Xr}l^T
zhjYT+<AZQ!s$R{!@Ty|w;iJRO=0l2|&8M0Cj6I=x@PX9A=ab>WLo;gORUErHbX7xs
zFxAjHc%({ye`c8du_dP|IrEc$mO3?G%jDGY;S{Z>L_zx|tDC&}ti`4U+4@xQT0J@O
z+pAG^{!HD`Ju}x|<VQ5RO+%1+K<U(~l2TudDzbGp+-<qVvkTSCp_`2I9u9YVXM1@z
zM>1QN{9tSMK2L`WRY!55U0>qFOv?1lfWNLgpXsY|-o3kQ3k?g0qEud4<)1MoG~d+W
zxkJg~%;-qN9eim1mkJ+TKQqin_3EhZAZz9aiTs+0#ZKB!e&Z^BuF?-XN9XvCb4B@E
zgHW#y8Wye&!u)_c({lv-k;Ap&WUoO@j)Lx)?18OB0c$U1W<~s#K$KBODYZqxbz@YB
z0ybNx*=-cqK%L9_c$6-&N(mByR;Hv*QmmO&dwW6ErRp0eDwaYip0s50p|_j`sAieU
zseeRAe41Xde+Ouk^5Ka=mGu;>8dkjd(VUA4^Me0Yac6Cq3_S^_42PvyY4X#Pyht1D
z2<2|e=ho8TvEwYvZ!B;|-47d5tUcAKO)Nxp!;qHS(6BQcEoXYRTVi~bVd2ZjOG;T@
zaU&qk`(GZj#-iH^4KRGB7{ELw+*Vn#g4EEFi6`_=U?s%8V_@+6NoDaz01-&y9!E6{
zU>V{JR}4;~7Tj|L556jxT!7{>T+R%wM6G-SKIRcgBOqpKQNxW0I)eLZ5!Q1g!*bF=
zj<^n_!6`Pzb~1K|0v)puuPF?X7=N?`lx2uA+6oV&1+F2IV4NOdF}t#os?62GWtDb9
zKm`n!e8Aepmz}n<vsfY>Xc6NP!^4J{;_M8-*$i#oC(Md`vk}VWXA5Ue9MyZ`vsV;v
ze(L14J7(XiN-zGH@L9#1U%z1Oj(NB2JnhBryz`}J=MrALcHQ58yz}D!_)hOv{yO*Z
zZOf*v-T30mnN$D%oh8S<!Efoj$(f%QZ_S+g!c((aZ+}M4)vSH;#al9Gyzum_sc)S8
z#I}p>-TBljw-TN|>+Uz6e&Tz7`SH#(U%WT-+gldQy89m|uibUgEu8teBQxvevu54>
z`j^)3`1`%Ye=9!oLwMcaCZYQSOHO?D^e66l{n)kZ7B4~f2jq8to_OVw*0t+iJR03{
z=I3+oeqVGyNO;Q}Id4SsCYL67a-UL5#)6jk21bdEB8FO#PY#v1Ri#@-YHtvg)aWQ$
znxN-NhdEpoD~IWDm^)>YG>wLPuNx1G)bOZMXvP=>7?l|nHVwmD;Qs9XF~!6L6j;i>
z{BPVM9#%{oF~LLw18np<Ood-am~d>pNeuWVb<8N0;-^ldQ5nOT%pwyQ_cNR^IRTlo
zf?}|V5n<S4zfT?alRm==ZCul!x{y5@9X}v0Q^y0Ly7+x`iwcX{s)kuUkq#ukU;Bxm
zS{%SPv}5TD{~v*_Il^fjg3kAW7Tkz40tn~-|1Z>%Xi0ZaVJyVaV)Xy+CfS!ozFwCh
zxY5$+Da#Hc=2*IiFAr{jQSLc`+-LIifN;G^sIe4})0$PO4ruP2sI(brHI$u<EtE6#
zfae<!P5mfet0Cg4_PmOJXJ9}$0$F_r26>U3x|H}*aTJO?)esnZy(iYh{Z8Ul3-`73
zTie0&jYcpB(wXBSldaFDW}Q5NU`Mp_(^7wqGiJA*A(do?RS3^Bh9rcek&m^$tw3lo
zLKTg&$Bx$I!a`#TcT{B$VHom=*SzaRiDVBnhH<e5OSE(#eA(}+hLA`;e8LW_L6ugj
z0zF{plZV#w{Sm<DFt(=flp)E`%^=#zkvs)`eNuNXJOPz>UuzY~l;9DJT>TMXzXMWp
zk(~)uph2V|*yTNK1g9LOt^-_(UTJ-*Pyt<*Ga?Syibp&ToTN$6w{#zCxFTIv8au6M
zl#krBD(vC>on}uxhWUY~tIBhuHs&G5peu;WoKUD{jMSYNT!K{etI!eWKsXI@GWeJQ
z8bh3eSdJ9dI&26l6iB0Dx!`#6m|Cx_<M9=7?0Sw%hG_YrV@hA@$%_zdL3j#?bFl7=
zP+S!g?GYf>z0VmG98tEB_6H7|^2l38gTnMMZHa=SfN&_yF3fhQq^1!(N+4Dxb+>sA
zT#}3t=)L^GVIWHna*&O^K%E8!T>zC3+lw0)mlzpCAUq^35tLIkyjE5sT%^S@eCh`r
zK#V~*vM5GjlYoGv6G$7$1x&Q@BELW6v&UNA`(=@CG)<X{<cM~NGFE&ToOPnnV?~8G
z!eFT@Beu}aRSm?58t@%fxUDk^Bpk7)7LC+c*ui#*b-vig|40mtF&wnmJv35hS(1~K
zj0hO7B}SZE#AcUNw~h$6PGHO<ebJI#ftmtCUeh)@@GulD`9@C+DXj`vZ~bj;#CZ@0
zxUkR7rM&7W@xx-8pn$XxMDYW3BXSK5!(*X|sYns$UqGuMfF!NMwGdHWOAJDkRwy;3
zcWu?B_F(3R5?n77Osmo$;}BKGXl^tVbMU23K^UZ{;@5$KTdr^*)@Hy-?^H5V40?_K
zhrM@!vaBlaedk)Ws#sNBz^bBvf^KD2QQ#I4OF&Pb9235(E@Afr*gTT7Lc#`GX_QB4
zNKT*lVAk%k*|ZI8TEzAd*%DA733k+A%*zdp(x8DB2@;=u5)5h-P2&3z?(aX>-qnpU
zj*NTH7<b$;?pL+u<D1|7Uh}!uUJr?jfQ?b>GLKF*4C{gs>!P=+3T&~Lt~))wWiV|}
z5g|cVB#{$o3M9({vGd)PCDUA8QV7i$r=;7qVt{S&`BEcA|J7;(6ih?YQh<)f6;Q^m
zkz*3=f*vaK#j!c3k#G~kC_?Rc&8s7g&{DEn!Iz2`TAqMBGzce@L{;cQh)L#_v`p*^
zqe3z+it%!Qb@_&pDviR+bQ@k{*cHlZ4&JK4M2`mh=vpQ9vqDc!M+}uP4s;AeCHNAz
zWE9wavV)6#r&rjmQbuvLFzLelDey7G5wqO{ss)lMt*JN;5?DoUs<%H_x%vnd#7X}g
zD3_hA3ZzZ8mNOlg5C>K!l0*UEHR}K@VNM0641|;i)X3dMdm^SAc*Ts@4pAP*Yg6tV
zCL6Gci7|R2YbVp{fCw+wDnB@vK_j`uyq`k)SsI0`CrNfj#ioFB*>R#+L5O30aDkX0
z#PP}iP}Up_i~~qAh3)Qm&4YJFpS5zlx;kZ{oCQd|oRysjsn(7$sQ^LFQ1WmTj##6Y
z={8SDlS&9A%SVBUThI($WA>LRK2}4TZn{mK&4CM2iCPWM^b}yr7mw%~B6m#=oD<6x
zk)M?pRR~@pY`^j9RidE?OGrYvDL^xArE`%{xUoq$1v|AP)JPjZy*OS&jXWe&)a=zR
zCV8}+bCHN0WYgy#U&oi(-y8Gs#~EHNs5v!O(t=~g{F1V-V-*rr2pw24Q=5q5Udan@
z3tET7m}A<~;0(h|_V`+sFY?Gq+Tz2<1))41Axi>#!OY29B4#Edmb}@epIRkN=j?%&
zJj{kQ{V%4_c~$TSIX|tDg~6y)_Vz3cI(FseHr6T8`oCzf#RZ6C>V`KNJ-5x?uEX;;
z;>rArn*z!kUt<cMpMT4KHRR54@db@O;d0TC8#P#R)x}jY)mEEp$h+vxzq29N&y^I{
zAx*@Xpe#_9y2_$RrlE=SwG4EvWe&h1M!QzOom5C!Wu%W7exwL`8$ihMr&u}n{ZDg!
z`f9kue_^`NjDm#U58#Cwa_JHrU`k5aUNb1|IRrk2Wf0}<m;Wy&#SX~!sRAR5IJpAo
zYLj|Rt^0%DKNHhkW=m<0hSJL-hSn;rjyVDkz3*idXFbcimn_1*LeEHu45$*F)Gg|f
zsH_!n)+LK>iwuqSFN?}ZVbBD$L<s_2Qtg!S1SKVSwcjUh?PVQ3QUGZ@XJodBT|^t+
zDh<D6&6K&b2IgFtpf3awM+k%|%mac-2t<*Yvata*rW*8iAC+5bQ+}w1qR<yZR5yfR
zM0Lg<CU~a|0ILua3K~$x5mb&Bp-j8pIQp25%CC>$f)G1Dx7lZ<DwaXYlv*|%BQrCd
z4brC<Dd?&`(M#l<Pu1|6i5v!dOZN}Rw=_PyNQiM{N4qNSvWdJrdVz?CW(uyUhq4Y8
zA%;j(3@#4JTOY(-2*gmtdqD$HnI&XQx*73|?e~UQP;<Th<GdFpD%dY7Q?}I0ymakC
zO(IL^INwXgH6W0SKhyJbcr36*DZ(U?I^SY;LgmOQT40d`3fJS<o7H2%QUEdYirA<p
zN;N@GBjHingnKq*HU*;a-Z}mwc=|Dk5HspdGBB~2RggOOKH6?+e?!e)SMA=+8fWrI
z=wnziQx!nVx)z)WDKmJoz3V|RGv(+gmGL4e-D-N>6)=ev0wR_Z=1^r6aAvKGaymsS
zLHpBNHuTI8&X)!MF+}KpfCP;F2W&)iRfzl~&i_1FkVi`YMcQUb;0=u_i~5$RXNMEr
ztYr6qDmL5A_-+iY3r6f?nm(>XPd6u;E*~SgKZNKsFu$PO)2o-j_VEiKwdyPWd8i4|
z<rT}iN>qAsKuR4QrlVVKT^~iIDbP*Af%1L5K^Y+VV}40P7q5^pr0KE;eQIaG$1n;B
z-DHfqdSSCS5P`hnC~B63YIgOBai=RDT<l6q{Ylyj%$FOo-s2^)KBl;2y2}VzOC})H
zcT^3Wpf^zVc~)J1A6PGmxKb^PakSl22%pfSLFkft;ClFcx+Dlv*@K5sEF&%YU<87s
zx9*WPjxICyHW7ppG=Fa13_?;jk`oI;4M{?D?TknTKcDZ)P<?*kieNERJ6^E4#1KmN
z9!P#yPDJgW?$MO75A4;0$}P6BR0_I|)f4MQ7ZjM6V|)1biLP)y3eJm!1e=A-g+N07
zfM+LiE!!p5^WFMJc?mNPy{*wD>|x8;5GU|4RGYxQi;F19i0wQ{nJ``f{vRgrO6`Lv
z-#~ZAYm2&qRvE?m8n3pW|3kMOO*CElNZwNd+O9u*T$-SXv?3B8hJR2RANLA^2~qk)
zu_+k5k)1TSo{W=~17iOBKP)r<2f`lz|GTVujsJ7?!_VdaU(NnMvC;n*HOCLnCf$7c
ze_r#{Cw^g>d}+V1<iCdO^}%08y`L}qFQfZEP!{&*k#;ji{Garh{mGU7MP&B#ME~Wy
zeBO9$fAYu+y>u=ap*Qfs`K8umGAcnQ%>s7y<ye(T=x9U{dJ|FE3=sQnfmpPyo9S9r
zFcXx?h6+4KS5hEZ!b}<MjFF@P#zDPMZdFJwHM;L6_bH4DZODnB2gJg93PVOZLTR_i
z0AJEls(Cc**9<*LViN%tn#V%SbnTKf4<h9+f|U_u-TFN?;MFD{KfFgE1!k!2ImFF$
zpqtWhliKo{oRj#$_mp%blM?aNN!w{%9!!uAo6_7ymraoxdM43p1<3f~GcRcnYNFOz
zR@_xBNt2%1AE(3(M{!qDARjz|E>yrWZi;+V5HbT_rE1)yh^)t^w5!==GXq&q5-i+>
z9Q>l?0xXRJYc1J@&Azm|bPt53d#aF05{M|hCkYlP3`Dz77A1qKBqBo^c6;x-WCo$w
z^gwO$#)D$cO6D>_I!5RwtegE$qF9W6$Sz?&0i{Q~_~=y9p_l(<F(&lrmiYPoDj4ak
zoA<=B@Rz}oQNMr)SxYj0L2(ZS*|VW5)4JH87)EhV(#7>uj4fB<pg8;(C4&Nsu~(8)
zJD^-IbYiIUZ%sh*ZM3fy$$2zMTz%P4>N|rpSv-XVr#lq7WDHlS9IMN|z#)|%<%q+`
zcXha}M@Cg2wGbKAjVM+LN=(VRL{CIOW`vMRlPO6YRuy1|qtca@EwPDYl9p#d>G;FU
zYS<_(iKawX;dtFab_H-^p)nD!V5#a9$C6!={PPOiXt%0kA604sS!q|-Zljtp0(*AL
z=Qo@JGAiszh%w-M2@`_Sd?e!0NxA?_`azj=anjHDTVhj^p^I=4LN}Ivk<7<L$<|w$
zk$$OZA6=Rekfu~x`rVfv0s%-r$bC#hAVMPoS8;)app+K4juf*?Y$91C@3QGB9883G
zDuURyVoLoD@G(PR-9*Ha_NAoqR3Mg#h3{66n`L1WXW*a}XCfo&f!gF1*D4n{<o7DE
z^y@V^*Fj<pwWM3t)lvHGh-9>fClkR!Nm}Y>r6+b!)D`R<)r(`}Ig1N2jtZ_HX>H=}
zb7PSOYloGkff974BH(pEuAI_A%8Jbl@gQU(jnatfakeHAI7&!T6S*g+qia{hl>=CI
z^;nGhk_c&@N<bNw?umq@U4^Mo5V}XH3CpGj#{ml-z=}4J>0Mxml6um>_dsoO=2^X5
zYzOq!(&!TSC<dxAWPL+tGv+bcNn{+vakdabWYT+ePkV;HgGG;x>&Te^zl#vAE?IDr
z<d5x=NyDx*3_)7dJ4#c@6bCFqWMgEO6eg|7CPmr|zgRHYc3glwfQJng7D{O%1Yc@i
z+SO$fXktA}2AK9IiO8^7l}m;B6-m>ak7K24R~@1r8@g!;<xk(Z2Nqm=MPY*rWL|co
z^z@H5k&s<tBR2_PEGX9ti|Nv#S~E~2daZZkiM-$qJe&oHDXSM<HZYC_UHw8g1Dz|k
zUtL65olI#)Z=>8Ji);eCO&UbdE>6-+InNPUC@>D07!i^rpgnv{OvTWL7(o_rrob!6
zSsMd!onr|CsakiAflS#rca`-j$^uanq0*Qw^>PEH8l4hHD5U|<5ecpAT~Xm9*Yj$u
z-d?uX9uRiHmvJ|W0;WTWQ|OlhC4jU<k@Ct$5izkZ$o)Qz<gz935pPR*6<SaEu5F-v
zg8JQxr8^>>XpK}fK6DGLqze(Rz?Z&W%6AiHB;XstcjMmr*v&3Qz49eQ*VbOX%SU#)
z?3#b>q2slrS#p&7sGocfe1;>H`o93WydY1ae%K?rc+$Xd3f(G!#QI*Qi;G%4t3|CW
znduRfaUkmXG5WRiJ4#Z}mG3grT`<Mne76~5iN}Trz4~N)iP;y9m&wq@D2{1QVn491
zLOs1=k!1S)h`PzJA4=)+yg2sjX%$7iu)~xQ;5R=*UV8QfG)vZ|h#<nH<&qh?*&Zps
z)o5rgb#1kC^aImU5>Qfv_m=YNWW8e&?7@-yMD|cRiE4{{3R)Ox_7;l{M_#o+RDvg>
zJp=NAU<6Tam3>j-LWg{Wgph)^5g!7fcq)xO`+?_F-YahkO7ml)?n}NIx<`4s25KDe
zl{{NGe+Mt|`W2EWdSdaa;r=7mTs&~=@kjc;WKUyw?!dka4|>f_3%*v_-C9`i%WnO2
ztyL7S@{30deRyJn&-;c>dTe}n?wy~U8JInJ?uhEDE%&`A*0t7!xAo23ys@?5&F^-{
zoH({2-)(zrY(r(>h~|f0eBW^Yb@_>Vis83>Y|B{#=}X?{`|gn3=~c;RtTofzP|0Vh
zE4j&u#fGR?v4OA041H)qdaXjQ;jEM^y>?rx@O=w=YRHvd`H7E>_vB{iHPBc=dzB!Y
z?|4ie*pY(ap=CW(0q`Rup((i(DOoxfpY2qxpPx`G#KwL}^@~8G5Cd_IE0Yv^{vb=(
z(aZ0(c>Ar!8=D34L~#vU5@kYCucwz=BJ1hZl^f~y1^V0o(Et6{Dl#OLdc8a!Iyy~t
zgHGtk=46D2d)fX}xW8<qxM*sY8$F6iZ~4|%l4jZP*5a`$4~m~Ul1@&CB3WptZZgra
zMW0OiY%qkJSEh2O-&j2?=6T<kukgLW8*iM<`nM&?Y(4AG2PV>Vx}DF2Ijg4m%#9su
zx@@A7`g~;1lH7jjHJgp+L#<>Mxie8OPU0ljB@44w>QzIoM{cvL7te17-f7S$n+o)L
z9Lr9<$+^X@UM|7*5<cXTPA|QGtoBOcKVP>j{X1i9WjF+FBS@Xqp~;noM!xs)tDszm
zH{45phx!SswjfXvDCK#^Z-Xjn#Kp@nEgD=jCR7ZldMjyd9K;{+K1Q6cc2QJNQLQ5J
zCDBepPjG>tCUVblBF`hBt0=s}Sm0b!0x8#iglHcOmOa&k5e;?QoQQc4$|_GX%8~uW
z1Q~(J-2DK$f_mn`A(sCjnmVi^AJAmuQDoiss1|CkI_(8)EO%;=wnN@?2+&tJQ#wSf
z*@7}9E+EL0_QYmUZbTF*QBN=gfvj)VN_SMn6D3scOV$QGEMkUxogxH<_r_%R1FukY
z^{I$DwX#xA&iW`i@>%+g1d<58j7$+hg-G%uctUs>dy*b2;dMFICrYVGmzwX4jCYCR
zT1a}1a&CAIGHF`GzKHkLD;d{Ai>VmY6ry}jPP|CcD>f3Wb4#baWaqja*TcK&)L!pw
zMRM{YSA`JcvX6N($+WYIa483B^DpqOL1^T4+Yo*fcm?Ll^Upx+<`Umi4&KiKA64In
zGLquYedM`#PvgHavCCp#5Oe+`n8FUU39)f>Ax}&uXpJs;DLy(TU6bm;muX%s%S{TT
z(aoUmzGYq1&cFvHJO}z15&H)3(lQ+#Ae+d`7uuhA5dlE~`K+!)2>~LnWIdAa>l1^K
zUoi!ro{O53fj%9aK|Te$3UT0w3~FcZcJ4ZUvr9FN#Ia0hp8AoqWx|$_l#!k(a6*St
z1)XNbqST00fN$xivP0*9T?jFrpc;w^?IR+lRgqZ$j{AY_BM~;RfA&gr4TId`d|Oz=
zK0A;aKaUqqd<5*HfOzT8b#1j2{ylx!PlZUL!g!y$TU5#`kk589k|UJMcduR-DY}l*
zrr<w<$Z<miA9_lm+mt*3^a^`%L|PaB^TJd}SzQK^6iDroQyD8yHL(jET|0v*-OKzu
z+bkCL?#3!Jy>OyTM3SBy14sW8_!!0@@hpKGACk}BaWj}CFhjIfK{LqhUuuV)nOh)R
z^*r<W9kY=@`d0L0&vP#e!KR(0k2OEoVhz>(QOGFr%<cVC+K4>W+|JeTv8)55q`1&^
z0)|dsIA$`q&RG5PIx1OVJ9(yC>+;4CLn8B44HA;|Wu<S_Z?yneVy=25_lK?}|Le$4
z;b*vx{h;ps3>i-xPx6f48zJ{_!gsp~T2stFW3DwvU&3J5;u64ZRrFns+!sSj-KpnO
zfL>D`eiz>MF>=9G(qj7M+{8*|A3WXMm;V1#|KIe$&HK*(O9N>69-O~XDeGm+IK;@8
znO_<v&nC)5oWyRe)U&{MbNdM|F`-+qUzF09>EHW-djEeFbnoQPX7;0w`v`9?@d0c<
z!@Zo5qN2QCYOFconuSq@Cl)9dEFMF^yfJ+`v%Xf!oFPe#@U|?qY4#C%ey#(}@+|F`
z@xviM1fXU97B>sl`O|fJUv;*}fn{vI)S&?qYRYj}5d7o|56*cF$0B2VFF5RGJCk<6
zwJ7sOIp4JrjlQOpzmRy;Z8q|O`_xS&Qa;r*LS?2L(rKVBPcZSuO11>6sjuz)g6mW$
z4qWps@IjvC<|X4`YIx|kxlW;&``yC~&wNr;Ft0sIRlYBwClrlc5p6>W-}H0j+q}C-
z&ue_T<Y3_3x;0dUqB)Z}+ezJo=@OmLJ5<QB2Y0vW>2v1cJ^jw#R)t!A&zMhhwcpfZ
z<UsBN_K}G#mU-AEXyVM1KN~;l_qqgsWm!C}MT84#KVWC{H(O(mEy240j)<w4-__0Z
z`$jz9!9z4UTLb1_kIm@96B9VCRVq^BI)-HOp11^Q>~Pg)R<<8#o_3N&u^zo8l1|Sc
z3zQ)Gb(DnK&qL2MUPdxVj$+D8i9~gRQe04jPUY+u>(YrL8kx7i#3iD<Tr6V&KNzE+
zHJE<EeVeovxIkTLIyxQ8Il(|h@kCdWaeEXXUDqvkDyw!2W}H2tdMP6Tz1o~R(T1_2
zr|n|<i6cG>bJ49J)qa2ZPojctWGBNs=?L%%BsOxehv&`w?yychqQKbx_w}-`2gP%;
zJi1DvbdNhELvy_wqI(Y8M_)FB0pm~J<EaiK0SQ=BBKFKCU9n!;0!o^dg<ZumA<!jw
zBcbs_)P+DH7f+&FoXYEcZgU$uqE>^TyeLgW7^6&mD|LOs#n#eKBb$|TTV2(oVbC4|
zpxYW(Cd4Oo$ASn{rS0&iC!EX!I+@Ts88hpKRIZvq7-R%bKIg|`b-2_COo8W^)p!dk
z$z7W~{V0{b8HeB|)zFyhf~PQ$9vjwom3Gk`($UC>AT<i^2m}#^Mw2Lqkt6W3+T^j)
z0g|f6mZObn7C$xWGH-5Xf#17jUi4dRer)n)cocg=PR)eM6-fF)f-Bqt%+>v5FPK2j
z=X;b<**zkO!jy2<-;A*z&;T{k3##X#y_P8x1w@PVRCKk}$cQB{nYjZMPk2u_H=^B^
zkNU$FObJ*BznP$B2}!7@!C>EOermHYFya98R+%_t^z?WREE|EyLkZq+xj^+&gW@3-
zrD-)`C<#rrhI8CxJefmj^H~EVZ*uVi!5Ny!7SREy6@#?!A=7B=ojUhrfhw|Bl40ZT
zHMQ?wttP`{nFg@dPV8M7vgi)h2%aKMOKQT}oL&LYmvqp{ZS}LR&hSr?q;46f;5Y>E
z$*?nBRYqMN^=@?1G_6VGi^&F<4BBn^z|C>aF6I)MZ2U!k<W*ff%1DFAFm@Q_vCIaj
z*GDoNP5f}2Y-5*3IJUA7@t&k7){K@*a=N+*Gth3NE2jOfPWAZhv{`s8$V*(KFbQ?p
zFkbL^Du-b(<!QdNLb8>V+i#mmr5Ep%p$t`PGkn&7erf5lVhj{J{4gv#={(hbcv)nG
zt_`)wh{2{g1Z()<nUOHa8cWJ0oc@FIWb*Y)Gc2+0P}pc{@5>9V6miz|i%Cc@oVlHE
zy76mnIu+8o<Ry!c@SW7c8xP7ZIJ2CWKJfm8e0CPuW4hWWhVi?GUw=PuhNyr@67RMR
znAN;*YjDYIH<0MmpcqA=j=B!=C^0ugkDlhW;OYkq0PRtVEKI!>TBapC7{bNFL%~of
zvZ2&8KQxiC?0#42=UuCo7|e8MwfWrK#{LB{9pfriVVTjNCMg{;26FtKhv~F^3p07|
z6kW|Sw+yEF0B>{Roj)h~@dE>&Hk_I6B;(Dzn&7~o3DYXodmEz~AG5GTS01HFso^W$
zC3;{U_f0XI14G}zZmu@Ma7|EuNjjD?go9D&YpW(qQ|0`iFQ#S(&@Ha8#@?kU=3KH8
zq73(#+nRV<k`<}Q)xOAdL%ak7uj;a;r74DJzTrJY3_i7?u}T|{S9{#CVik-!97k_U
zT4^JxYmicm@y}0S8ffv{2gIkRR@ikGGXuPH0U5eMXzd*=w7=o<I{u`8y%gg2(nRjS
z)K|2`M^^80m&Nbm;S@||9MJLd%pJR8S-cwB8C-Bv6xaxF<m#Ww(*wO)5iUv9e81kl
z6xt~bh=E48wrqAqv5@%a@{z;__)=Oi?CCo9qfFoKWk)cm(j85D`WBbs!-d4{Fvljq
z_VU~)yI_X^S9J6arB+UNPhGf|hv?VQW;x$qu|?;md8)FKX3do8#26Igo=5JH=(4;Y
zrv*KaI+IP$&bZrjDKx245*q7RLB~enSK-I0WZd&<qlrM)<;{w->lk6#%e|v5Dr`~u
zTFbl}ncypY=4pF>Q8E{>(bX3+|IVu06T*z2_1>qW+TF4Uxf-HIi)KjO$m+z61==5#
zigh5;EZLpUXIpsVP;^7?>du%4nW}3Gq-i}4H^5h7LO(A+ZcVgaJmk)QuH&upboH%8
zGBmTu6ryXRkurXJ3whX<@*y_rvT)=HEEj196pptw=&OpJYU1q@I4R<@8WF)_L<yaY
z{sp}_Fuyr_S>omvWND(!F}IIQP(}^Vq5=xn=N<0|sV^9PIrT0}qHE*_A8D^GBdHo?
zt=4<EdJrFMrKRAFd}NRUIx*x-;y9F`EQptOaa*CSiZb{j@#ujD$<&M{4P8T~w&Z}0
zX_P7X(X5~axtCreLvE%Ru&`jhk>ROkkiHRGZr)cB8P|y5GUR)93b5@%ufo%u6iNzw
zO16PTE{X5A1-V6|Iv_tAA)pa5l;y-OaWmLRJqD(<EEP%)sylZQbGU$tv`0olyyG{w
zBi`|D2|17VxJfp^z~!yDxw{bwdM}FGOo2EukQsTT_&4$qOkqukpcJIo&^1_<j4Yw_
z^nr%&7742*4|h``q#_D)F0GeNHn+i*6>)g1GTUd~bwo$j;EcyY=Dh0@t`T=Irc${J
zwifk~2CPXUvB`w##JiaiM{U*sZ_!?P2b#=M4_fC9Kmrdpr9?#;K{6X7FAuN<MUxrT
z3uM?(0fuH7F+Y70=SEKwx(6sH`d&{=u>mM~tC~x&sLZPE-t+=FDadg^(|3y^rNz)q
zl#zI_nxK}=y1-cTUR9j)Q5_~Y`AecIprnI2-n^yse$a~Zv`fuEW>5_n6iI1Zx=8yA
zN{QpU<K&z-4Z6%HNQIEanHtT$Km%Ad&2Z%utf5+hz|r-cG)=wXwH%vMl`y9(jF8N^
zCMqI%58ci~%z5CsYUeI6AGtP~OvF6gLL$xD5Rw4mT%~EL=K*HW>0IZ^>OeG$kwSFG
zt(HHaV!zX%GNt&DsSR_((hrz&Z9IxN46wDDMn`ZdwiE~p*D$vT-Q8{H4t|+Bk80T*
zK?y}tiHQ#V5GWQx9X+h{Nn|Ho7Wimg`Hm|Qr3ze#VGQV(p-Y=L)apRs@Y<hwNo2uI
zoW{nmW2ginyf+3)<OKzBB#eDRy)p7@ce#pwMggE2kkTGehC85aD}>UwDJFp(4SbWl
zGY7#xohW3i5iGK#_@*ok181UMzo*KiQO&E#fMAjXrVHAu2&S!!Nit!<-XazCCK27Q
z!3MAzfiGE=^t_f`!ZddYVq9A7=4wt&9GE|18$d`}$E>3=8$I6fp!Xv%y+^dCG`hh<
ziXd+Z1scdMQ9G~r87aw&I)^@&aG5$Et%HqVGTd3cK8QC2p7|(o^_Wl|*%{otk}*&M
zEt0|O;^hk&#v0*LLvB!+R<w;~q*4?jmLn-zM1N=i=uLE42)UoA3)O{$2~)|E&dtG`
zZpz|bmSewBX0v1&JQ0w_zaR=L6AYkahNM?kK>rd?E8HZT+afiZk72|ae9+3#Mved$
zvDM6BVOI?`36N46lmHMo8?o&r;UXSNjUxJSfY>c?0Ks{YT2UWMyHd)67)tf3kMDDg
zd9Ck|vEL^lfYS*?SF-i=d{Z~#NE(S;eK|syl-o@DMH#{~uu2XYdv%RB<I0?;fCjA*
zbph4fz@VqMHH4u`21Oug8oQk5ybn}Heok0(L1p_vVit1?@(R$7>ppe+q$KVz+JcHr
zah6(tNEpGJI%e=7J0PU(qKAofSK+qmmGVYi!Z67-xdkb~5II$4tZ(E~Ew#C-mYo8L
zA_C$@qU^teY`X=a5hK+yn3-gVI2lkaWVFg@gF#jr1XBJCDS>e`)YR}wJ(&`WTzac>
zK4virR(#7lL8XG>MlpRL#KKN+-+R4Mu`Nw3gU2<AE~;m-t!1JhuGs-r87_5T33%6k
z>Vrz#9G)YkUD9Huk%Y#yz0j<i1<%P9D6VdaFfiFh5EG{ru?Ns6{B#_Gi#P()m4_0{
z3XeZJrtFeG48uwWksB{7{14rtoU5qR7uBY!7YntN0IU2`d@2%Y*$7GEi48(+!#m!!
z8qEK+6(@oe0CcBttD3{}_AitZ&f+DiviXA$UIETAOB7EjU=QFuQ7xt+S+Yk6ATYlK
z{z}Npr73if;3KL-OO9l?t5@+@tAuC^8u02)uE)0nWdRzfG;TlpLnTX^qGV$(b(7MV
zk<O@vHky)%jPtc6H+wk=s-Ov~Cs7#AO5?Vax?6<L<L)A2U7ezQ0^}qI26JSlWL(@*
z`Ye@$WOXN)C{_ea+m;%Hk~$-Sb#n_CraV-t#Md(DS*86&;whl8%V9}FU)s+FEdcBS
z_8Cb;$3*vHG}m2Ko0o^@sgbgVD>dCKjx>Z<p~Zi8TL9lh4?ZQaAO{E|z_5mxOH>J9
zS}HFQnI}O`c892K9x`99_2f$^xn=#TWa>7q1h1SxZF$ySf}RxEdHyh|3kMQ=O%<~}
zjN&mF1udOf7j7mCnX*9Zlmp0Hw9iMU&&eteEfDYiF<AMSjgjfmg@FWwj;^XoL>)Rx
znSv$YZIv;-@2tj`Wo7+d8k4G#iTEUr-`5RJ*;$d@kjFPZMA}6RN!t{bgH;9K#mxIG
zJ|hsn62&kSr!<D{&H$epc>xTl75HY+J^-OkwFDB_rY}M#96>dm1_z)i+oK|AQrb=(
z$^e$?1Okg01$Z%CGEoaMGYA5V>SWyAdz`!P2W1+RCq<zTF4UC@V7wAQ`MU{TkGaq#
z=6mPl(~NvHUt2ahf^-x=)2<#sWSs;9s|QgU8ZctZF72`q%WUcVJrd8MKqYe)%OXV<
z8p>qiuG)b1f`HCx6vZ$h3M%(5wP*K4RZfEIfw5w0Bc_uKAPc33tEGuGh$Bx^nd6nB
znJKwRlMj@X&PsYjW?V}tVUdD_q>ptY<7f}#DtcZ8gCX`G)n;tOVld9|idJi?x5x^x
zv`z$@c3HdB&A_=S$aA`CgpUxW;w^|$J0wi){Gx+NjV0_5V$Um!nW!0+vy_0Pf=uVl
zZx#wGjC2nYX_b=Ws&{wmN~RvqM?$it)KtAobYdc+Cb3ZEPOMaiLNG$cu<R<NHMchd
z?;owHq!xK71;imC*<7m)CIK>Rrw~5Q9j)%xg*=6{OF)B3Qp#~G5Jd>)7DAlOUFbk~
zB73k@CDI3bgJYdFA>wbfL5T+PBfztmgOE57igvW@S7b$F`6LdG{J01fJV+0^bXTr4
zRU^!dCtM;dTs_3W=_#V$)ZiH50K(EkJ=xA;L8^BA0Ov7Yq`Z#`P1I&dEVXV2cJAJ3
z5SE5gV3sY28~Vh{O3bK6HcZ8#i`Dcr52C}Eu&E`9<$TV_D^N1X<fvWNLGdWhT)>`N
zC4>I}fBi=oDe9q{WSNC9BUkz%)}^pp&UI9Z0`4LbpO_av!v%_?tT;SH5D4TOY>U4~
zlzl<_Bg9Aw@>CY0w$%5aKvUI9PLv4|gp1(aP?fwfoJ&JoW)yIE<@r~7e+b-apfM+}
zlGed*MVf?!;TItKrRJ1UQ+?T9%LI8Oz%_2BtR68!xDcx59*`(>@xtg^TE)F2(!Eq}
zhuYl8rLD(ckf*otlOnuE?mfAdc${Dx!b0W_^=2p5x!WSE^D!zaawEcp{D|Q0bLVE+
zMecnQ!(;WK{;6i5_5vfmXop+#3w_=kSvTPR!6nlybI+-}p||48tYcYawn&qcv)RU!
zhb?kEW*$o-TX*WUS&__5PFGeJJ`FxkRxl$5`T2F`8uN3r@xHcpZp$cNn4dD28lR_d
z>CBBTJdEy*``o=pR9rsZ%Jb$<H@l7TdvwQhji{pc@9=}&%5-q5e%}G7F+TTH+>MjP
z4AN(d=_v*`zo-4HSFeA0dQr&37(YDD(v@4qY#->&1>^9(8taaw>4?vl6`Acw$CDKM
z+*vuDpw8uEri5407^zDi;BJTZ{J1-`TBHYYg0fKfxHYE1#@WleM(y0ucR6<7Ilnd3
ze08h#Se3Dn&Fl`>u^Miz>zs8ueG68eTlgnCZf^4I8rReMe10yzc01LUi&v0x>DiVQ
zZ8y@U6HHC4bap>F?Bu7nHNo2Nn?i)k+yTSMNQF_EF49dic5gMOftJq>4;gV*%(X|3
zVLZ%aZm#a8oSC&dd?|!ZG2n;Y5u7h)$zt<<!@)<>ua0v`(@p933oh!9&n1>kw41PO
z@NWD%v(n<&%v?ej96Nq;i2f38VqE2TyH*)$SZ<D8(CyQ{5jt|0b8~#7BqS~kR>|GJ
zWOh@n7JNdzIeve7U8ebOrjLvJ>9luQe>EIBnz^u>x-77~;(z8)S1kI_<{GI>ivgD{
z?wOlO*0^-G0rQjd&Y?RjX=6h5LmJfP4&8$WM`o$Dd4$CHX@@<J-%&}^PiB~Ge3d41
zmAzRyFj-+N)NJu07AWKK7x-oM6<l1jd!05uuaDDKXV8!{eTPfx;4-W6r4Z*w>E8*n
zd6w1Q$6X}DwcLhKS>x!jN%pZ-H)|smcBcAn*0u?!w|J)P1x{|Yr!FsM?tPn^`Si`<
z)~U-|Exu2-v9sOn?riV0ZzKPaKO4Vl_a0ZDdo;8@@~dO*+m30qt6#|5%`b%3J;!8?
z#oOQG??12UcYnd%ciRSr`kyUMZCJa*?>%p<xp+Hs$vwl1Q)|Yv4Qq>q);%sfesjL~
z($y=%hBedf@q3tvM)SthYsW+O+A;UU&1||ytKqgQ^DxC5H*Xxx-RiT$;zwSX^W8L_
z+AfAOzKs^{ImRu1<W<MJ!L!HRE6#I!zB85a{kCn{>hp4U;aYoQ5Bb*AaPf-sWbeQJ
zcl=!2e)4c})w1GWes)3U15aPw`tbLD(z*SipN#MQ-d8#|KmE)TKm6Tqx30M2+wP~|
z`q2}Qe*b5!C%*Tl+7;ippw+zeVY}ptr&~Kd`pll^{nbylSHAVgC!hN9w_D%%)|Gp1
z|My2)+rIkDWB>T$j~91+^@Dq!`tj8(w*A?|>sS5F!{gU|?@!i$^6BfwSN!0ab3gaB
zt5-HZ`fKO!`t!e9vGoV1oO|z2k6Mv`>6G(VJ@zN-n(x0n-}S36%9<ZNW&N(dI;FYo
znJXWB;9D0YfBejEt$XTwZ_2klb9MEBub-JWKYoEd@Yh!kKk?6}Y<$~~PHDd9ncuE{
z?q}=PJ@L$&j^F&Fs}E{^`^-0g_D5&R-q$kER(F5v;0>Ssw^N!o{`Af3A9(r#*ZRye
zw)l-_LipW}*B*cR7PtO;9~}SW(;wXN#O0r`fBpVv@{JcBwfoDjd6B#0Rae%Ynmlv7
z^4IUK9)9v~H@BYt!QC(a^7Y}aZ=Kn>{r8@B$6xr@cJYtT2$S!_FK>QiMgG1MYNs7H
zJf8o{nd@i2@uGa&za3S5;KyIdn@`=nZr5dZk2n8u`T6&5{9j}FXFh1F_IxmJp7^5S
zU3b1HZ{GUCb9dcw)bO^8&z#%!^)s{Px1VFXzWSVe+t-h>2flZTYkvHab-VuTH-~q8
z`09;s`_rrO!|Bxr{^f#o_Q7u-|F*APo;4r7dc&><&(ycWKG(<8vHR<%9KZSE7wxz)
z-?sY$W1rkHlE1^b_n*6C)86sUtIzq+j(L04`fKLD6!z}@tvy$M;mzY8Tl~xQSA2YZ
z>y8y?b)LFqp;hfXS$q5^=kK`dhrhb#l5fAgwehE4-Sdv$d{utOcW>PD)u#qqcYOCt
z>%aQ#zaDGe^s?$xAAETHkFPpo{U!hW{=9kB`t`e>`C-vK`D^DsaLecO{QIw8x9cmf
zcg?e3UETGD6SC$#bGGX_>s<4&*UYW@_+(|<Ex*0{v|pVI!~gWExm|C1m22K|tUWM%
zg4=feYd1bH{Mz9i&m4T&IX^vkc>LGStM5AE;%k4OZ@BFG*|NFj2`{?rv&TPo{gy+w
z<kQQrt^a1(zW$Tv>~wqVo;}ypwz-kYy6O$*Z40l+s+}`V8FaP!c<r>KYQ@)VZuj@!
z@ageR{rKINTzp$|<5l-}K5+P4*s;RZK5@yoYhE?H`>89}<#${)T)p@OcW0IFY_q4X
z%!<lKE~>7&@`;?mKDTPw#%#E_ySnSV+2Q7+neBSRuxoDk{dKzr&lql|<JDDv#M=J)
z*|}B6PYvg<@2~FqdOx3<n45dx4^GIo^}S)^0}E??^Pm$p?E3FV(bt#PSM4~2`SI12
zRWE!^o`3L!4d>i`a5nzZQ(DvKV4FMao8Gyrnblml@vUPoUR>i}bI(Zar~kZjN9XT<
z6h6G|htnTA;mJL}{pYu@$UgSGvE<2PrYB!*>#ykat#CgZD*EqOw(|Xr!FAu{j+4bZ
zA0A(*+^}+T;4|yL`Na?C;o93*EUb9@@r@Jas-JE@wJlut?HvnaS5(r0AJnV&ADg>(
zZyiq#`;;H}jZdwsZuv%a@i`O4!sD0t^s3L!t=svp)#49sttDH+#&j{St~<0@4KKT9
zeBp22^0jpAbGz5S{Wtj*)tkmgw*OW=ZC$voI(*?ntvl;Cedhc1S8xC3o2t8C@*+2L
z&S6+}xa_<82~z)S$3xTiz2lGO-t(cB+ws(m#cOx3pANVD{qDtW6Zx$zpB>n)Pp3Z!
z=N~(_;4b=Fr#SG*q3QH5U$DLtp1&eA2ge5e^*;UJ!?rgc8S{^wH9q*o8!PF-6IGk~
zYR0AT71y>7&KrFPvA^l_uK8#&*ckEyr@f$RV}CT|whq;<Ykk5uX8NkOw=d_pw_-5N
zPNl4|w)q<_J7Ud>!S*$mrN_Tz*tR^6{o*yX)vXKa>EZ=>Ej^kY-o?e>ME!~_Pu4T{
zI|rujBNv2|UKU(f;m_}IrgaAPeR!(A@dN#xjo)pCy+3%F3#W`U=HIcL6R)jd{-hJR
z1N4Zn_a)0Ge>jw0xbcRQ+EbsrHm$#UnX7F~UG?<k3nxGH*3Fl_=o+`~g)98V8=f<9
z^26^)uKJ@}>T_Q&!d0go@(=UXcPI1LzB{-F$Nb3;^o32kkFxJ9yJe)kc5G(Ts)P5|
ztINa2Wy{C%GY|XI`CUitxvaXyz471yH@5aLH-FkK?Rxbv|Hfs{?bOyD72de&Icc@J
zynfTWkL*15g&{Y;YR5(Swb#^FZqD7N``qkRvq^pP@A34)s$u_~HKX<UcOO(AKm1qS
zcl!>+Q0_7?!jIR|`2&VR{e}ZtoA{)lyL`G`Kj09z_qt`S{^y5ye?3<`4p`o<U$Lyc
zZsYR3Q)e`stvw>E_bqet4<51i#cLX&wl;BB9etGB@bx~wX?^P4+C$rKOb&N1TYY%A
zs+vw@Yd_}Z`)+B@e`<MnO?9B-A34I!Z(i=m`>QT<7mb~{%<UDwwFeg`R|m0mHr>#7
zWOmisL-vkUIVoA&sQJDjck<dH_p-B+_Q^v7A?tgtpI@`ge`s}T(`$mawKr{;@9T4a
zF_=#O>2aBb7ae9l+}!8vFr8b3nJ>1S`{|Fd_xdBQDe|q}j`|f}xU-VlwW-^)Wqitg
z&`s3*^HTQHd_s0d!?cCj!fnHA2Aq9jd!M^wc_?0f)6CSGH1jja>kG7Z->|J3O^Vgc
zV8^|K_n)s`u+QIDaF0N1-Ljk6i&orB5>meFmKt-uTXrNTEJt#lIMZ;uvRPL>$lJj~
zsXK=IPu2{&>dafcXZv*aDo)Ztx2?(c`(3Vr8T_U7wQP`9hr+KN%JZ|i=&*Xbd3W=q
z8*<4Ms`|m}JyHUDEBADboeJ|U;4#HmaX3^K4<fdZK+`2`8!4}dCYCJ{yOg6)qCA&3
zE`ZLIi1Lgu7DXPSWQ$)OA#xE0$T+-9bhbQ!4t3!Giy@baDKA9Rg$ZKg=x_j@BVO>8
z8e~KnZCD^tYDzgTl;&11$~iBB<qRcJAyIHM9-%4e%R~Hsp&uyMPqKiIIw%zs3~)$+
zpc1LT9+#j29~G6TND`DY0?z@I-cuD0GO1GaB|jM1666O}!cQ3yzS<v5D11n{==d($
zosJK6>bq&{j#K`;JMa1R<KBMR+S`AR@20KUe$(gw<euMsf%0cp?|STt?KiFY+0<Eo
z`SyS3+ho<d&i#Gzf5x}SzI54ZKl<qB?>_fewtq3^AJezVzVP&K{KY+gcg5{fuekHv
z)yKX4^L)GPwfFq`Yd*?%(UgDX7v6vNPoDYB<Nl2AqW#9|zj*r^@*hL?-(9};_V2I0
z>r1ahw~z5%v_r|Cz51@l-i&S^L-wKiF52q5&gGkJpZ`^4>$_-Yf8p+P`A*szzMFPu
zPqy-}`r=;Bp#Rjl^1EqkZZC%3H#W^j$L1Hmn8*i(``Q?%_k8nZaj=%n6~(~rL;RSh
zQIo-1a_?v{w>vGK^qfe(WYG1kF2)Bsd_8S?#KQYl<mrQ9Wnc5i!nf&ZbjjI;<$1b$
zXk6bYu!(Hb>~(7@ZWCuY#i8&^s;Az$rtVG{;{2TETi|Db*A7<tCs*g`p6%nOCfv*U
z0#1-7hpOqd+#|HRn4U|A_#DL$-_3-#PL?K@S6q8=oa;u)SL{|!a&LonO`fMiv%YA@
z@4(Gn%S@4;%|wS@zZ@*~CV4`jE+w!S{_>zl`^%|fsgGfZA^r82fTyg^p`Q6)1AU+A
z)_>~JYEno#JoPeB><DqHnGX!<nJjVZb2rvEzRHiK6fgk(E>CSJovmlMxMrK(K{#R8
zxSvmEDwI#Se(nvK<<djbxxi%tcPjVRAd5Q=^o^}}4`k6dl#T}m8P_mzHYc)c8VsW>
zw-INi>xJW1Bs-?v?98IOcSroagKu$qcRKuRJg*OM-9cnrSTk;441G2d??q)2n(iO2
zSJPFTu?C*4sZt^2+yibcE?-CY%nXGh^@b@EZm4OOEpYw0<AOWQr8XJd+1X$nL->uU
zV;lKod#!H{R@j&<z$*_`ckfxnYE)hG7OtTLW|}@%ZRE-DI4t|}gtPUUxa+MC*590*
zztuTE@Q`k%Wey8&yu&@Biy`q`&&X#QYdkK_Lz78o*t?m)jK&3<>TcwzpN5NybU^(o
z&EJ8+*z4XuWUd<A-J6_qL;c0dY3f`SjO!B<T+0BN#c$procl(V<Emvg*wEx0@3AFf
z<rwgWQHDa?hJ!E^Hs#wc6#>f9R+Ppf{48}TZt#OOWzt7=Mxhwc91NIqUNK*XjgS|M
ziv6tkvjh_rth$czmnRe8I>bDskXDlrg-Y6-?p-$#7Z${_9!xbkvXm@0!CHcJkG`QZ
z*HLfLobDDe#Vm7W9;D}}vV4#077+FbbZUZwtX{Q2mzr4$3b}J!V1t=5(FCqPMX&+q
z(J}Q%&nS=NtkU~nuFCItpaX2G9GS@`w~RdWd840b(WB=i2(HRU8Hrnz7{FZND}iFx
z^C<>_+?M2t#^s4;ksfa*?f_>V>x_TyEHk$Zha_o*(iu05N@>ydtsxvjn)c!|P}w}&
z8JE&@2aU&GUQ1|9DC0Gq)6)2PEb1@veH0iTRHz$i(w672qE2_3^Ll&ZHGChJvN$e@
zx%;xHX9K7c=m;HW+^_3#^Y~l_0}@F-T~E`>ct93c(G(OeUNf}#SO~Vkiz*ZiSzbvp
z7lQf(fduiJ(6n=H`pSrU7ZQV9OPA<NC)J#~|J*?mxMs?8Vip2ad@lo{1ioS6EH5vw
zS)fwp=G&=QjOItqChlm)Qm4<2FNP#AE;Y7to`+!EN7+~a+y0}~_8yh|3;`EWg)UGo
z?q-7b&H`#O4vpW4Y7`D{Yv|29TyrCn6?!J**FFx*J~c^b6q_3pEMKE7a{R~3a7q>p
zGI>n{iWkA^v<|2-2PeeuV$qU~Sw1mcFk;#`<*=xV?x3BlqrYEH-?|GH>tNtfk#)-s
zr!G4fTil7pf%Uf;Wtyr67!MFT=BnACgyR{T!X1`Ot+YMlwy>>C=a|o(cg<sKsIPnD
zY?OVqryPwuR2wS}SLqob@@%z<@YAR{`5(UC9XRLC21(sI%cz8UqlatXv`{!V3%z!s
z{iAYqUEHSOZVXh1C<xUDUA`(!i0H?`cn)BPS2;?I_t9|KsfkZ~LB*u#hwll)&Y#VF
zT_bI5z*p?ot1}gi2<$e-5xUl~6$F9iEXF{dx(!XFOGhBMq@n`jnec}3Qx><qV}lDd
z%_w<c)tboEzR!ORHe^RQU(Kx!&J3<&N#Gj2QR3Ykjvi3~2f$prB&Ntb8Qhe?+fs8x
z@p@}cpTOPbDaB}ls48R4tKH1auzH3}W5B!IYtEMD0eLH#6VX?Gg&FdpV*DpER00?)
z;Mwjt%oXo+#D#Nd)<zsmFjxDyG|dBb1YG4`t*YZN1C>)>RV9#VMNw3aM2oa}XyvP^
z5?^5~RJ9K%xux9T;VRB~v`uP9QmO9OPg5^~XrM1xq>N;ctBLtpIk-k&ti(@)Ql7I<
z8j`hAYnn#^E{1dKJ<V%$dR_MRP`OzO8S9K5NHhWUK?O|U7laL_JPJUZr*u$Ck4JBn
z=K(9S*uJm+HS$fD&TmZ`?q1jDi^lYK`jgU5b&NUMX$G6CEt-VqIc$LQVutd$L*|Ck
z+y^<r=o29+?i-b^X`3;tQzBcHw(H)}C<jfeuewvY|8U}LS6f7Jru$m*5m)~-`i%xP
z-e8prG5EeHMni^=fZ*~|`TTI-wQfF}bN-O=sd4MjgxApY*pjYE{Y)|y&e!=V<U9vy
zX$Yj|u+dd3`W;I>5*g|->-AGCWc{>Pwc)($@3>XWZ%q}m8+TdohVlt}Y<5&DE!7;B
zY+RGR*k)373HJA#FYm?e)qx^ECujQS+9K`ZiSxeDVnL)Y<u)&oX);pn=i-j}mfz0!
zJ$_)sM){D}>@r$$e!5`Xg!||}7t+q}rb{;PfWeCg;e36Pd3+Y8&ds~sV{WXempEax
zOJYZ?&eFryxcvMC<I{o4ItVWvrMSY2tfIHWO9SU=e+NpF_KW*RYeV$zVI;Ksit(G=
z8t-1>-1H>=q?fjn3Ak71vOdoWaHOkDH>(M>+<2Rvnib>6IIFV(FdiZ)?x1n={{Grw
zX;F1=Ns9w>7hZWt@Ud6+xe98`d9(3zXlIS4p}v=<XD?rnEvz$ygOk%k!R2T1IcQ5#
zKQNA<1KTUjoX>FKRx}Cb)(wvp?hrlVxs|p_s17>gUf{HbU(7R9GCN|o=OH7l@Z3_6
zn+t=P?+dK|TtC5I+2NdpG2GiPPG0941AS9`#jlewPjBtOVz_^DjCGPR4~Hbj72X|(
z$(?~tD}4w&r&&d@F`MBfAWd!r0a%@VuEss6$Z1;UzM|N=c_<%a;*q~jbkGm2^$p5~
z8LCaIxnsBS#<o}1+%|RUiK_c=vz~-&vh^FjukiJ(Z|I;pF9rB3=X|hHH(5L%I?U~D
zE?uAL#t-Jr+@08>Pe!P_=T5jk#TAI5CmBe7`<9G22Vn;qrK8xErotIb;k;4+23y8{
z6cXoCU9ZwQQ1%>Hx)XzsbP6n1cb?@(;EkXhpq^K!v%nY+z0+1{Sw~N*ppOpow7+r@
z=&7~-LFXD>hB$9G1^m*Rnh4m@5u%77V=l@1X<KFlp){8-vI1Cq2D0L}mbMgA6k$ZE
zB6Kr+o|%TggDjckqjVG(fzDD?P3d^DgcNRIjL5WZaz;wX^j2z7XP&WCPxQOtf_n79
zf#^&4aqix5D;=PFjL-Oe=YoXH!hgmMv`bg1xKP_tRbVKUT0^89aZ15FPVS_w=Ik1Z
zvG9wsZD8UWSf_Z9ISa+IJMuYlL9>;=G(9v+v6WMgx_m&TB6^$TkPGoUfb2Nc%E+RW
z4RwA<Xp)0(R&f0e1oM^#5dYCt@Cb3O^VEtsKXaca!`6@=#MLl8NOdg=dgbY@RIi01
zX?Gi3LpI8lp~hmtyc%n=m-S;jJ7DQdmB)-@b=aqijF+fqhp;~cY?uwva{<=WJ<N@e
zu+(KWm-H9S)Oi=!pq2Ngc`>Kl$5Wh`882UiKA7+hJxZ9<Sz#)qw1<(($TKqBXB+5R
z^#4FE!s(+%oU84AE6$-2i}mQ}a_`JXUAx$x5t8php4fC?E>cG1fde;%jB`{(^5zTK
ztdw9DeoR}XZ%lZmITgs}=o}mMc$QN-7>b|gz+onzkk;udgHyN}>PECOf*>g-0wQ(c
z%t%G9LX|+a=+F=Nvn`;;=~R=%Vd?BvDkeUK86;BCQ!Mc8aLUNZp-T`|3Q;G~@K`BD
z0gAJUeF`dwQ5QmtJ?tI(Cu=bugK7!e?Mx&RQ=VcsASb}4jUlE~CyI;mDJo0LXMToX
zC6$4Z80mVAH;15}3%J47Twj^1LMPKkD3|I%tP)?8UIZcIN3zmMj5N<Yt6uL#&-Dyd
z;-&>*nDwJAgv_&}%zV(WozTFHeSk|X6d{|UfJ};EuBP-_%an=A<mAD{{jMt}m^@_*
zvC5-&f>#}#n<p|W75;vw{?3Ix?w^Qw2v83KH(J`Nyvvw@M5mez4wB|pk+o=&3d*_P
z&`*4g`(|Pcd72b;=5nX}j5NS6%u=zOA>bC^nFXAf*O6En2C0B~1b$3r)b&D`<~Ppk
z$WO8p?*!_i4KhR2Hgli*8#PCIfX>p{+G)EFaXhn(&vwOL2->Z29WByKKB=$6GozXd
zzSNWQi#YVOxg@8#db=c884=Dg%fK20`~ibQ37&-_bV*I857sTfeZlp?kaddfk~R}T
zW!#{HwoEFF+{k5CA**%B63>u#oP@h*DQFWJ<Z?J!;eAA8ME#_sr;#RzZJ`=waxFNv
z3o&dm7JN)~8Jff-eGQ*LjlkI2VohJblhCG+)An3rAR*6`hV6~=)of*#N@ge>)o2_s
zhJhSg-j^Lb1%e3)@X~xLX|Wsg2vJV=xYp?+v8NU76e`(-VtKr`)2os;a3>I6^IZaY
z@JKgfflVBKiYJAIS4&D+pfK;4NfJ)v<>H9;@&h{__7Ji_e;R0|chnW-ea0IA&M(q1
zxqFfvL{WoTPr{7ND-k5ZtG2~|$Hp*biu(|QADDilqWGaZ3zc-im?L;sQ(q!_)#kqT
z01+vCtQS`}<rOI|6U01x4|N(`HP%Ws77Tpo&EIee<fF0-m_9cEN27k4_&mkS8jc96
z&k^Dk!0<)n#&A$RD=Q~8S3$~Qt}P^Ma7oWeF{ufBNQW?&&v8y7MvLr2nUmq=<(3K;
z-r!`=HaG^oRp}9IT?42(RE3SJEnlJiafhSAk#Z!2MqJv=7=@qmp1(G7-EkvwcvU86
zBm%oHqJ7|_7g;Ppsn3RbKCFpDQ0VHBEBT{q1Thg1W02=nqGcvgT+YMDiXhUwBYm_P
z;ylEqXjOtCwn{!ipg7FIGeE0ZNO@{UPxY1xE_O%XlvNa>u1{4rWv|vK+r`15eWOZ`
z>1vFOAQA&-)ufLJa8Z7nln^xquJkH%qk%}!EF&u;5ql*)HME#!ffzoTcZBKz528e#
zp^Ip#TFe;qU8L)@NYQKk$Sq5f7<FB3r3Vt!)|#thBZuH|7l*QRi;VSB1u7P>J}Qza
zsOW7jI#4K;i4uBsrwB%pyi{*y5y?A6B1i>Ittc2L7UgAMlO8BA5Xu9%zBDaynK`%D
zbKVVfOG{6YXLi7OxK9QABxdLmXw^gNC;<a68jx+}N=O6#_A2)Jr$_s0)Dpbn03RhO
z(_aKj8LYBXV2%rE#OnVgSVF9Eh}U7TB#YiC1S~ZRv|^E=R1l|*N(8xI3`9YeL@3LZ
zTto;Z9kk6zOtU0IQ?#hAJ%+RZ)RuRAk)Z2l;gFDe6m=o8Fwy`O#0Qpi`fhC>Ekbrd
zDgtBDOsR35;IJuyk{=<3$t);}AZ$08Wp27N<t#wo#j>K5LSsF!jAQy%gr@8_lD#rv
z8NwlYAnt-ZZt;nz2)xQ$ba0K6a&u)uWp36hE+O<1icxNw`gNywJM;vlv(6vWp~VeU
zhH$PKl`_dA9jJ4}u2G7K-P?CHph%2MBQ!UY(iww>0Fcv1;=V1iinxSRD|$LK(RR9?
zXX20h!fZdL9#4}O+`Y%S-`+`LHfG^Ul?2@+b#_Rs6P47evD}-i^GYYFm8-S(WhEFF
zwMdDCkRCx*-_5cU@Ns<LjfF^oL1_A{HUYC>Xr@7n0$k}Yc|kV>FI2%elSW><3^-T-
zEtuu-N&tD(9|BXGIZxgKi9lZCfO=vdA*m_~`W=walUBdz78~NjzK%L$6bph_OEoD4
zh#~EsTTl*fnZhbW5s2bmpf}>ww>@*3r+TS}MHV6s*q#xmk`PE>Xp|B=b4e|6`@mw7
zws_s!VoJQgWi5pfFj4LNEGRi~?Q%b6vdA;vP7qtHjV6Iim&Pc5pA=Lvomupy0YNGH
ze(*7Y0{z8B7GmXysSz53%43`jEqI6fypw;`!4pbDiR!Kb21Zbi!pm#2QI=F;D47xG
z>o}wYrzn9)61;dtFv5&7)u2Rl$z(aP(XU0D8owt~K#w8_Y!<);2gD$n*4L+1Q7AF+
zN^xz1&`MF-eRM=`=H@i?tZ<$CR+>gCO)NUSzlgatcXK`65ZVDH^=1_Vw1<b9S|w3I
zgQmiFMoK>iGWFPw-(YR><WN>;4F(&nNva<r8WlW(y~Hm$hAUWQn|tV`8$fv{J}{_E
zZt{JWQahj^4AaO@vw`?|4pP)n*2>kB9Jr2f?6R#UA-yR}gIVs0f>jMYW44P@P1ep(
zZsd^X64=HD6-5*Ju#cB3+Z@>iKL;AN81(@&RUOE5Dpj5a$u_QlmkvZ@mCN|542zRi
zt1c8^*`lJLfU>m4^X?=7?bW&yn}@OHMGtz41O7PCNU_I-`CxjXjN4CFS?f8<30@U=
z3xd}Mdl($-VB%l$TE!t=&{N9Y+kP<>RX0BK<6h@{O_`JP3$elK6B3bk+=&%$iJN74
z9yLA1^()Ixby+a~7C8kC=K@;d>i*7Q(<gFi``F;z42yd)^lDGie}dm?M-QB=+0cEJ
zoHaLFFmBbT;O(30LvR?~JT5)QN7uC&vePJhYq7nS)n|9V9q)MzuB|Mx4SCk#+^g7G
zRIV`uf3--mb_M=!oz51DdhR+$`@luf&h>MypWlv#ZDv}p7s;EmRA7auW}Z`UH*h28
z#MPGHviM@Wo)+nKzmhN1^!rH59XC5Yeoz|RgxgT%rzAO_^ZRLogY~bbSsK2c-<KBj
zm3-q2jgc09I3J=Nr>DOj`nk5f!*AKj{Vqt%^9%jIE~M2E)EVx>chmV0&n=ySO>H)t
z7X`1&IF@ZYBJZTmSu#-!oXTZ<H(xBIeLRu<0>7Jcn<KHQ&hPw-2`w^I_`$7)ru2og
z(xwl|$~By49qJgRZJ3m8`OJ0_DcS47g^XwOdW+$$-ij32*+g(RqM+9E<KiINh<6~t
zH*Ux*Ue@BL9iP3_h0Ru+%x_pcy+PrmJLoOzYpv>H{jAt9vjv`aV~23&%eWe{%!b|B
z#f?mFF0@@5rnv8g#^<@7J$b0OJyY?$IP>l!l_KkS_WR~i#%y>CXU+?5j!wYE3Ugy-
zfvy)C!G;^1!W}r|Uf`^<t=7ix>XXBD?|j7#wQIi7K!bVf<4K%Gm^5a%sME|IbeQE{
z873c|w6Tdf%!ShRO;h0V$)p{(NO{BK$VEmq*A%R&8&+Ju3qIBLf`{lHs>O{*%@s3w
z1BHh(ewjLwF+uqly)#c=@8+3BxseF}z1VBmG4HsGU(Oz408v3kCY*U1o=?1|Eu}!l
z!Hb6cbLdh!IX^V3gE^u&zMrcZp>PKz7Iyl}^i0U--s7A<b)n`y6s~lCo?KzocWt*d
ze{r+57LTzHZ9BnLU-==c9=Y8bHyvZ!-*b$+{Gi9(rAIz$t;cV(?KdCe{&)3LZuOeS
z?a`Zd+M{E)xjWaL$I0Ub_Qd`7*b|M9xW#pA`K5DJ{lQ1?vGtFB$lbOsamTFdv*G);
z+xUIk$v?<3V(y_)d+?z{-21aji`&*+nqPX}A$I8(M%`_lOWkcRztms8_LV%sbG9um
zKA&U4U%q-dxbrOB)Nf(&dH#i~mrq}Q`Z>09%M{1+{4uAm^2cvlW_xaasqNX~?ceXZ
zOZGnYmw4ib;iUS%kKa=J;k!QXzx%c~@A=MM->ARoy?;3V#OJ=e@!uc*a`EGLex?4%
z!@Fu%zU>S3pS<^x+P~azTK)ddU%BVv3+~?g{V#vB_SUx_;2&AvH~RHAedYC6Z~BV0
zZuxfonNLsD<{r7a{=`Gi)IR&Alk$Ih??-FjJ@e@Ln{Pg;_S0)$vhl8mKV19c8~*LG
zzqs$;uDbk|cWiwB!M|gdJaEdUZ$12GyW@eA>NmW1RdL<u#Ty?v?_#^{;Z@bm*I!cm
z>Ma*v`qWXs^NMfXvg&J_A3nDB=`a1}#;3pX8}r|~{tdss>jNj%|KO2JD$jiCfA0L&
zBZpO<dGP4kcmMtHjlcHv0ViI1<qJAD-Ep_<J)U!$>EHU>i~Ub`{H(TT`y1<zwSK?0
z`>wm|PiCjp(nnraKlh7w7wscXso($DCB={5`jo$P>+^~uu6fGe^ymwUvmQ9mpLYKZ
zwFggss{Ys)FRuOgw?5^6cJ3Ek`1`ef(hjek|KQa=f9UGkXCGWuJ@d<ND=z!QN&eU~
zPO8;sj;`GL$&(6q?`Jm-Jp9>W-QWFTWlQHQyYrE&SKe{|)z&`Xr24~eA1(g&^XF8q
z|NGyu#Wk<3zGm@twO1vpDwk|uRV=*Ykjfd4JZIkh-P(;qkFA<s*z&6UHK#9kM?Ca9
z)wH^5e(-N!SUK^**G>B$zp(NTKRl*(?F0YAxj*@+o_l%d3hZs~o}T~aNk_WxeE7LL
z|7Lte_?6+)=im6&)c)e#|2F+khkVvvpKhQ2!BI8$lOq@Ae|GIP_M`mq`7;l{+O}>z
zZvL51IeWu%Z<_!0<vU&9L2sYF?U94+JI}pf)8m8Ns}HRho&Ufe6!zgA#isvx?E~(O
z-2ZpRr&@OY^^2Qc^Qo#k{=KU=z3YNYtu_0zjqiW!to`xzGn@YChF8|^JY&tK559ZG
z{^WYw^wc9m_P-xW$Dg|XF#pwC&fb*1cZ02a*M*xNIrzW%YmYo<{M+wx_P5uMt^d@n
z4fSgu@GBqrWM2P7-;``ScsJ|V(^sr=_g{RfZ5;izons^K39Wv<XTmS5>)(0K{JDo*
zY$5UUb8e$u=#H5_=7^)+{O;eI-tws@-KzVl(=S}>+}E}h^UpotWIOBBqvszxV7coo
zE}y>ch9mON4>#sN{+z=7c~Q&{95HIgbQ;rVFBHx-TARLnAp3|fpS5z$p|7)i=yfZv
zxc7J59oW)$;5pm_HoJ1*6Xv$<E>`~ITVH8UhF5O9>r><Y$+y3J<?Jo5Gq>ZyO*g#T
zY~8qDe{kz8_x#Pp%BLFRzV->Xe%Z@CkB&@_Zys`c7O?H0S5I&g(sx%bYkbiTyk@H%
zdE*vFYxYgg^0hdACpQgzyY@eJ{B3<rYrt;GKag)<cu_4)&-C{mcbyH7&sJBwo7)<;
zW%bt|^qaP0&4%ju-``gJ`i>{(PivlPmxtl}J?~smdn`YH`g$HPJ^uc;<$t_-Rk8Q+
zOX{zFY@N9?LcZ|who|3?9#lVe&*#j2`X4vm@!$jV{}+4jA7EEi9r~|x?wQHCGm~)U
z2XGSt>^qsjO$d7PLo%Y`o|_5Y3}A0U&;it50_qTcG%C_i757XAoCK%?L>p1t38Du4
z(I{&D*<LX13;yU!Ev?vxbyTWA)t6UW#kSh_S^JzjGYJrXy!L&+f4ntw&fa_NwbovH
z?Vo3#z0dvO(4W`OrI)|pt2^R}xBq<GpZEN{e(uBHwVU&&#gE+L$~WCKX-@l#KaodY
zdN_Whqq}_km+v&MTK6gQ?T*)#e)iBC$}hU}f60w6+xQo6W?b06tFnJ`XT^N4{W2R)
zw$`*aXQQ&_Pm=yWOsbP#H{$+ABKP}ov2-GX#<?ZO9Im7E_Lz?$CDFvo>T=szGQQ#u
zsuM{o8wc(-L+`qqG2k`vnmtusi=JX`4*pc$6StNE+s%h!*O{SryhKX7*^f6E)nxGZ
zS;M|oBKx}|()i*wcOa<mdSI`Os^cZIer@eQbersY?-#^8%m&*HUE6vZPC_@y{9;LI
z&AJ+6{SNu-ft<Jv%wBB1Y+AlyKDzi#a?>TRTYo<7E{ZRdOEz5YOmL;?>kRGBjz3?&
zxA}?&gXnp8Pt_h7{XqHc`Ge+)Q{(Lif~fGxoZbHU+`-bWV50D{c02s=!f5-=CpAns
zQR`oDQe*qe7P{?c<!iR9V7K43(DmQZKDqtG(OPmrZ2Q|cxbmi!WLsCuZmc)C{hYv+
z`vTkVZg<s#tx^Au4W{PW`wFKAts~dAMg8w%?7R0O-u?1othG(H&zrZKIguM)HzeD`
zsHgu&ZTsW^-;a99F4NC(^1@%X_8K{5y6{_@ZJ|<mSK-GzT-S2j3a7N$!rzMMnVt`?
zrOtjaw1syM3~=z4J@UcilrS7KF!xJf3XAO)6Xk9B>R`{}sle)2UQ6sX>OYW6`m3F$
z|G2m=^YV84xp~(=nRETS_F(UKNBxx?FWTqJO4d9%t1kWFLh1h+?y##@+gfBB6EgP7
zSq|t8#I4J0d0xwKVF#0P60SmD4#`K@QsxH-*q7hwrgpTrer6g4!ye1l>Irq?`^Vz)
z;=kHy_=d0%;`$$4P$)c(&L^>_sXL7K^s-ydNWBm`zB{&P%?0!X{dG>~zY6*`%P-<q
zI=2n=>>x?|C^dwgM>g5mF6EO;RP<5lI=5{wS-mVe{E9F#^TWU3Jxj%I?6P&98_G<@
zY+HDK;bkn6-5y5u)=oa+KR?%Z$Je3~Q^Re6+OSvRO&hG)=*+gzS-E+EEqxvQ#BSN%
z7KP>LB+1VkG9|uqv7Pmlq<5$;W9!*NT4UNYDtlVn*2`(3jZMQAm`a!1$BgbXTog4z
zo<HKks}?Pk6~o22tE)adFkpFaD9O5t8Sb#Xa#_Qka5ZIRF=i#ovD3q$kb=|Ok7|0y
z4(Wx%9L)nWNDt_P>tu(%|G-#W{zYQ!<HL+56Ib^^AMlGLSy1P>EVub2BLmVQ#buF#
zAe~hE$9zA_O9>lUe4M&!M+JSb^SliWFayO=6|?vV`OM?NIWB(>2qJ{8MYMhxuz01y
zrQrPCqkLA&JgEU$vNQ2sz9B-V%1vuIe0m|)XFxMu##_(QA&8y0r&MYO4S1;g)J%qQ
ziqkZ5>J&-7t{AVD!*zbSL+#XrA~~@dc*kaL&Zrk*lK3+{pZMC$nIC_q$DjGRFFW(|
zu%4^o%+H7XnV-M==)-!B=7-HQKb+~&@cXkfKbxB8YG%&ed|=b(=AQZCOb_RYX3qQ!
z>3O5MXMURJjX2|TJ!gJ~Nc&9A8#T}T=y@Z~^vpf;GqkjC;}f%IejfGV&DWgqFM8f+
zIeGMFV7_xWJ@X^q+!EG4*VVdh>xp82a=h3do3Qpj_{R68UGvOadgt>z&Bt}v$NN9K
z+RS%NT)U8pytX3tjmd)A#;ygmMPX#G3!{;qu3-C~B-nQ8;`#Q{YFw=qqTxMVQfsS)
zc4$*<hufmUp+~6xG}4KoHaq|KrI6>`B)<?64}i-JNv(Y-8Xg!5;tiF+^m5Lzeb))~
z{5ryX=e+Wz&N{yeS$!gwZBGmZ=F1`H^H|3k{qnr{GaJNwX+vnfl+Tq8-x4N=7Kr>^
zm@{8nr{yYo#_4S@r`r8@t!W;7g`BNVGxhbT_+~J5?UBJ}2xVe5Mr+eA0ee)uqf&a9
zQIjX|Bj9Oz9ueyUJXGr0g7bC81egZ5g`;a~G-K21cwS6`LeO1iWrXaHu|CtuI}ggY
zJ_;QR8D9n8%GuBn;qiD(?9MKl70Wrb3D&~8E9@^bb{-!r9hsQqnYLc-42>>Usb)#X
z*xlvcu0X$48TU1EoU9b)E#P@QWJDUBw^EL8tJ{M-o}M^ilEqziL}wF~+-dCai2HLD
zsg4(T4$U!`vh_Q>sij&Sm3j^NrA-whZlx^8Z*%C3?k7?gE3S*h6RA^$s7Wq)gADK^
z8e_G6e2pWZzhl8H*=WUh(=BkqGdTOdLeB6AODlQC{&<^yH$KX<1T?Q*SNfvP(a^>n
z6Wd$Dq~1`@dAuv=3JW*qi?Jb{t|a6vDlQ#MhbwAXC%17P_*_>=#w$F|OP72x7nbB9
ze*4Cv-0sA3zL%m&3V%m`U1W(V%$3TGadDS1GVH>5H!&>B7yX%@N591?OR2W8)}?u(
zN7cH7^(B{g!r2c($RsO!#-n<J@?!?bLIwn4@Yz~K1<HnytQtlThZ4mWf=FkKV#(=P
ztF=yycJ4qY*<_zJw$ar^WS9ZQ`hyI$Dul6GY9#F(L@bX8+gqR^uYQk{F%y>E3FUYa
z_6`!qJf;#-5qPB6Wcf^dEtH@%6sBvMh_a!$gfUvd=nb80MaD?Z@kb&NrQ}eDxE=|t
zAyuVQ2m`eZG>*^dRP@JxLdurJ2QgI;ClyRW8gaEu9oS(CVKNpEx=^lmQ0fAq!l=<Z
z`Bpd4U41F|btgo*z!)$g6}Zue;&H?)ga~Gtj}*nVI>qQaFftKR{eaMtZ|aN@%@SW<
zaaN4+?NXd71taR0Ew3A<VCDn;(k{U^_G6h+Hp$pPxl(oIOE?%axdl139f28f@R|=;
zmUwI@S>q%_jrAp&BCUnFa=gNYR%$F^k_L%b6r+lFCSjK`W+0LlN4?ebJC|T6=9RqP
z3M@&@lWkQDY8@3K>Z?hok%0h9O@!VC93QSTXOs92eq*A8DnPs3h{>q{mL~yCOU$T9
zX~I-_?Y_c_rE~&AA1}Gq2K9=1qhz!@EWifpT-k!;%z_D8_|hpgTiY@8oJnzY$rmPr
zq^lN1RCU^>CO~|Z?H|-_Q?In{lD#Amcg6KX6PgqgH>v~ej!rGs9j{R$#?H^NB>_8w
zCDpEy)(tmCTW?@6>Uof>a%e^3M;iJY9`d*$AKKc!nN_v2A?R{?Cgfu%uI->)f3QKh
zVwN%LFJZyp7X8$qfC*_kNRLK|WEu^E4iNtsR4Zu=6^+E!4-%%%nHo=CvB{xUBpZ^u
z_kG;?_5JBhDvfOQU{-uIKi(6F9=4@3M;@%~6g5H>*M?ZF4EEWOFm`e%S}QuXw?kEs
zVj^wyr($?t;HxAL4=5dmMi`D!yiB}RiCUD};hWg@*bp4)&>M&w!p12~>hB-0gi12(
z79rkPBBE$`L<Uq}dKy6-`^IfQzaEY#C&Ub+Vo(ama4+%kAUFD#%OLLJku<>G^vyQF
zE@WBeQ4h$9qqJ+9uz^73^7=)w25-D5CWgzY68w(^UFaknXo`Fo%?qO<ZX5Z?(Hqdw
zJ%Xa9PB=i-2s>9>l*6A1Ir&|9d?u-HfrO3IsjP8?MN6bd8>N1zmbz7l7S5?bk^$^6
zH}q4S)qWZoD4F(|MO=c}X0mKuHr6u0#wR3B_n(*Gg-t2}*tGo*h7O!fT!)b)66;bi
zmiH!Fyxta(^+@#c1T0Bo8ODs%T-sM6SB*B{5KIbTz#ehsK^>n@yd2NfvQmWr1B-_S
zg<u}mGd9?dIduau85ns$eVTXnAf+ZiQ=aV&LeSJ{G%rpVY4H%^a2Mx#L)#_6R4t?*
z2XBa?hmG~j(iVI>xh#n={2nagy1-0Qh?<8fyIV)6^mVp@OdR|41tR(j@}#MxiQ=YR
z1*I4AO2)|a^Ouq%=gW8Fdg3A8c3GtXZkJmgm|AGMri85*A%a?HXtc|E99rqt97ejY
z(pZwxH0q5UZ=zUFf0<Z&kaWwqzia6iF=!#zQ*{z1_f48lC-UHg?r>y#HEeu{FtT;+
zi>N{e4KAw5Dt-c>ry-4V#rUl~#K+<JgE8^xb~pOi%beK{zg;B7iBU1zPUvND7dzns
zs6x)a@jNS|(L|u8;2jRu;x~0jmrA4sYEX<iivC6%hhPfUs9hX2uV$%syW0jWW%jss
z1K916%Z1;z;nnUa@(|UpLpx2NUPfU~-qjHqhpi|=a$3_1fl02snN3p3a2!_nI2kV{
zE@!R?Ev?MPV=-rP_%6nlJZFaBn4$p%jUKxfWEgXZG$=b>L{V2ZO{ijY_+*G9le`2$
zQ~snj6-bqFMqE|<1x`!mqNxoMSQ(ReXOScSs!RGiKc|w0IAgWbP3~)nlJQe*d@@J1
z@{^W+)5*f%aBO9<<S3`fW!gqDMotb6=mb!Pk_8Mr%K{Q(Sh+nMo8-_?+<ONW;9LEZ
zvD4uT1KeXa=B$>P9mFbC=qKW0ve|tx=G!B#Ezm+AsJ2VR<XVl}#elPyPDAHOE!3wK
z-Mx+7VNKeDKCzlha6qBjX_%8HuD+6?92LURoF$i<n<*K?76Zo850}r0!U8`}q^L$1
z=3?e12lq;Vh{RF)P97BAsTnygr)P*;q9EeOk?3cc+r<mTj%=hIjbR|lyMYZczlmRi
zJp%l@CORk12ziS)08*@@b7+KT=Ink)iyL5Xe<1NaUzCpDg(jvkSxHbYF7-;_@^NU%
z_*83B3cGEvPkO9;J<Lt8+p6A1*^=9M)Z11T)LAoop-BCz!NRyO9-w}02xd%yUFoDi
zrLc<;J@qZ5<SJb#2~DEe1v<z8JOFhbZJ>?#SOsA8resLPR>Ta3W*lpisffPAbGd-g
zlW5Ku>cK;!eg!?tsE}YIFG*F<BysJcZsp}%-zW~L0%+#@9jEf~isPdF)OhUmUPIWE
zst|xI!xK1Zi)4`^EdONNs87X*p>z1nXlPsLhgoq%UZ7inDH7sSRn)Di2A%XF4^(s~
zJQHd}Fa>fNISS8Z@S}Vw#VA%>k#^?AP{YpfDAJ;A?@R(FLki)f&oDc$Xzw9ChtiXM
z7R5PLcZ#PW6p6ip=#RM!q4l9fTN-gX<Qb1Y#N9Xq7(^He?Z-g`=vhGXaLnPO0iZlz
zPCV#hIyUW6b?{Rq7`B}Zz*$RGBL;3B>tJ(vxg|7-YxQPx)<>0L0irePT1T>o)(mT1
zGQ_wI^h&P6_Zn!wZ59j=ji$s*+6+_<`TW#K#9Y}Vy+jSBWDYNpvj86IL21J}E`leG
zN^-5tTPbM115QNtb5q12)@r?qVC&_5GHf$2j;s!?wX~CL?4WP4w(m0RqxM(ft^}v`
zl^Y@ahsJ8ZkJ}ceTZG3+L`gMue2%fqYDjGTAFuEpuoLyv7sYfu-m7Knk(3RL`kB`h
zB2!k+cuGbb!c+NRBkk{H`U0mUVx6c5#R5hnK<WIBOWZJHs%NfFio7sLBE~0(jfGAL
z4fRp|jtd}BKOUqZ?zEmJXeQINEci~ZWkc-|xj+^Y2^fFJrRt+jU^Senq1yVe;%HJO
zZoZ2#8iW-s(Zy=eS^6@g9Ga#RLzkm|AZUQ`fj;Q8f3O~}{g1I0E)bTOwlGrL=&YEg
zRRNO%G}=&Gj2-tS2R_dOn+h}ZeGtLjhsA(87IK<try(&Pof7%QTa+#I2yU(}p+lmU
zVqKG>SS&4$fgec(r$*`IiD2zTZJ}usp>wYMKm<RHnP#I!1QtRiQb0{S&g&r%0u&az
zmBPHAS6cLP9vxNGv6fqp&yoi9{GE?S0Hr}$d!X+6-XXLa#NMfV4FHZyv#Y?lJ?@T6
zS!vZK^YCy`LOTmqCoG;LmEOxFIaGAw`&;<I8%21bJE`$LS}|lB@ObDlv<6WKCm`jN
zU*o`83uXqOs9PsfAe6`Y+*5WAv-$uWNnm7vNRi8+K$rr3#Uy(gr}&O}AG*=$L9aj|
zQV2~=RBz>&6o)EEVNzs4c2$&?zRpO4)YxEB^V;RItf;0;X#IE^CxawFYJeN}c$BT#
zFlb4IgE#D<Qw=C;iw8ge-Xdu!1R?Tu77=DeXehvdu~Y&>gchZ*d8inTsU;*Z++-a>
zC@_LvOFSmYAy)@7x-rMiQ&))rs$s*bg8a5<UBjG`;xs{M@$qwq+$)yjo^?DHVn1EP
z?+iE9SNnd8Ps7&gv$)n4IxIYj=iC<eL^p5&B+WljzV+*XLH-P3$K0F{nwL7gSfvis
z_C$K1jI;%LF)AnnD?!;nmm#S5DfB%D_u8wtS)-U%t9nMXPjL>>A-D>Axo`+7B(X!7
zKJC)qC!^LQQGn?_&_@=mBa3LSOjNigs70ex3WsK0Ul_8fJ0dmB0koQMs<CPHvb5<~
zElafopgpukgiuku0KfE@+AW{Tjb)A1=Qyj8ka-o<UWgx19H0^wS<<DxSVcf+I;~Z5
zCN-90Eb3F!S?|$qDl+tPgef`j&1cOC6~@0yt!lIjQ8wS?;YAWboq)8{mPdIm?x0Q3
z)$jtDBDF?SSOuZg@>QU8eNG%wtp$NDK|sjss#t-du5D7&C9aLf7Je5~dsBaQpzBig
zO)7^`p9f3hQ(n(ah4uPob?-juRhgQSR#Jz<9zg3SD?u=3)4X}SO{106X7V%^mQl!3
zvk~U?WCp}|u$ill4pv?$iB>dO-2LFHsYGk(8+1gP107mV6x0g(eBiy@LU=PpoQxGM
z39CYeD?{V0X()r#2x(wYnM31q?vybwn(xq8*_@k8Dzo71tY1|ZLyBGvT7)JYhN?zU
z!g1^H7?9R6#%{plAu;hVOMw#DxSHxqzP#Q<Ti^fU(RR6*GnWvOYwonCjBFHZsXeq2
zM=~mbPoJs-6@9b>hMQ8bQ&Q|aJdQsPCop-!Gs*>8q3Q?rC{5o`l~pyRr>Rm@5n`3n
zR~Drw)~ZXb!B~(|R`mOUqEc|yWWEX2J@920=muy7!=+_j)qp;1_>u~UM-~AOB*K5@
zFQu+&geGnO@F<%E4smf%r$H%1TbioT>(JgjPH#mNB=Jct>n2$5F|HZTT$U1i(%SI=
zPH#~abq$_D!t})!ul9mIRqBfdt%caA54Ehpa)7Z0VIiW}M)^k{O{<A76peLo<sbmG
ztjDca&*F`^h~!Eli=@6;YZ#=;fTo;18tRadLM3aQ8lq-2wA)chY0u)UCK!*S3ud$6
z73dZKk{~+3r?MhlhV?*B6-l)AmCYVhX$a|{q%nkaEbxG%3_2nzSbwJu;v-7`H5xb6
zaey%<-c#~4&6{yeu8f&6Sr!>F%G8AR&{@`od=L$U*w6-bG@7BZ6j)Y-RJ4kx(b_VB
zFTqd^TvYKw>$>g?ZwAJ@VOCf^Fq1YGHN>R3^d9_?;#jW{V=zea(L;P%_fgNMYZ_%w
zA!JwUj~dM2104T#RU!p1O|xm57}X#~I4q!i|858X6b2J0JVrw%#F}!sC&Oa`RU@=M
z?9G!caEk}>(qXe{K*6L74EkjwqnWIyG*%_-XUUqNO;yb1B|b%^6kG693Dgc!CPUJx
zPrDfK6+%H;!T7j?aahWFeXx6T0L_@aM1AN|AdtS8qaig%F(u%!40c1SXK_j^wOT-_
z32S<3<?2a-phL|}7LeCfgFvT%MoH+;EI7tqsN)t`vu-GrrDcPxR7owz^<RQ6iFvuN
z0)aJpi?={EhIHfu^v+p%P%b2*da#`0VVu|szCKM4HwrEHUXH6cTm^$J7S|by)Zs}J
zVjkh8t2~dgnvjBjvePyNsIHFE)OzhztTbmHK00#VQ93Wo`XF~zg>R-H7+;C5JwV?y
zDN4$xN8}7x??c3t_h@x%YLhY{kmX**LPXO`jQV@6-ZL;wPt|*%^WX<X`WfWGZ<Je=
z8>N)PUJz7(24N>wMSGZVS#~6z@(8E#yy?bGA>r#R>6oZt7jzL1plfC~3PP7{1gS>L
z`Jw+t`lL&BsDKT8|6o0rm4+&$5JT?kjPF^RN?0EkqMcJ8xt9oOqgq<FkDIcSoK^+w
zLRUdp)2K^iyqBBFY?j99<BC=#Ytz1)nt`&_Cb7DNQ}A{%hMaklh6T+^&p2r+fv+>E
z)HEBac994h8*UKs6I6zAhFIsvb1||+*&MMtjxZn4Sr=`Rn*v3WdNgO+q$db!zvY_a
zNl{<KDo+Ypx%?Bow}lJTRw<+^c|S6l7pV*q(1|nNUX6*%+J^)*h)6pmShRiN!DdPn
zH}uXJTITmN7)aIcQyb;o!VcST^^On><rqv7S#N~xqkIg!VF#lfB6S!jtM)Ei4&!#a
zF#k@b3Z0VcWN_kHpm)*Vj9Zm=yMBJrO1bTJtIO&f^QiTKaQTa(Ue0Pfr=?4-3`*43
zjfF7Wv?7=n9=IY5?0Sh*W76%i7eRkRz*ZN&KN57FP~u_JO{gt+^y>`<p_0kYfcaKi
zQp>ANL#ulSOn%TN4?@O&JhTW=u3o>C+GHO<;6PnC!4}2uV3rGx&zhIQmu`!TUB(aB
zrXu6{*u<|7wwO*T)4&PXlRcPPTtQGOu<HcRHZo%D#vrcqN{VmAG5rs%-9QjR7X-ul
z$!lAy_UjTs%?<UF0lsPKj4!5%cw}n%3BFb&Y$%-yD7%G$wG!5OmNsV0;pKrh7}a-1
z@qTwF-BwE=qv42+2ivAxTT)FH1+tYk-yXa!*)Nyyk!N{lhzYvM-->WUBf6QD&GIxI
zkX8n#Wlh;V$Yz@Xt$wx5`KjbO?Pe)Qmo^$Pk=%1i_+aFE?qE!~Xfj^3w6B+~5VQb$
z6a8<8v`+Qj?Bu{r@1<qh9=>zF52N?h*{~@+Ls}bSzL?ji&!T*|iHG}^xVM#koqLn2
zFRf5}@`!gT+Wi~q<z}syJS&E_f;nPKm%=;tEi{f`zDY`a<561spbj})Rho<|MMF#P
zlb(J%Flzbk`+#3uwfj%4@%akJyKRKpl6@JK!(mhjZl$Jl<g_`CjgU}{c}o)4=jHUh
z!6XE+88Ap^fjVNCh|EOHHX=TUmTYt=fqmn6Sh~jJ+JLF^eZY(2u?5@ovu4C^Kv`?t
zLoD*PAj9TW-+g@cSRQcel2tv(4_1~YRB)kOdtk~kKw+4!y3{EEDuf~5E~G&ndQW0=
z2(@j`b%ta|-!V`t%O>VR0IhZ<-yowU89RJ}++2F4o(XyAxzzLOo-R8+enB#xys~WH
z)y?-VH_7hZEy?c1^UGHbcS}!o6F<?jRCbTAFH6TJ(^tJjHr>;gOs-iv*;l=x+&6Mz
za@Tk<x}&FW4RQT_*HwCQyRVPNCRg_LU6EgG1~(+(9cRhd9jjOLUALiNqAN}KcZ($a
zT31}|+fe8=mzB+5tv2D`cE)}4t}KM(OB1t^F8gn~s=d*xd&WL-=HkAKFD=Oh7fSev
zrODXt;vRGHg>he=okE;D8ryBeTyRyvEWA)2{JfC|C(q<1+j#|Z<$1MTyGP1@d(}zy
zvWw2v{BHRn4eim^<M#i~!WWk}-}08j-+#|r$`8Nu#KXV1ZEgP#Pk8IWzn}k><k4T8
z*!Yv5ooFU^{oeGaZhC9^#t;1I;phFsFDBo7?bWqA-?F0oiyy5!{K;!BT=k0^Z~V@m
zyz#~rSN&r1<7a)Fz1=@~{^7U%ujiMx{^99Qt^WFJ`>*}?tDd_5yH}OAzUoZ}S6=i2
z*?!|29$xa}H<X6{?efRF|LOAnt1rIhskNI=?%ev#3m)nIZ|mQ@^%d9dU-{SP#y`4d
z?IZWUb!q?58=w2L?yFwA=gEhLYWII@OY);Xdd?%CyzM1jPu{TQpYFf0SDyUH8Bg8+
zC+m`l7ykDCzy9o7hoAiU4WGXM-`-TNU3!jv|23y-e)H3m@1uYCJNqvm{Vj9ou9K&~
z`<_>sSL|AQ_{Pzf%gzO-9{&6Jr^r_hzqawge>vT_v6mdad*``*XMgX;>6Pz4N1nR=
z%-V^sev#Ck%r)-(cE$Ytrmc^C?1ruV*Z!z-c-22#Z=U>4VY>M3g~`@~S2b2Yu&%uI
zsjWYF-cQd+who^(y?W!DWb414)F}SAyQliETMu{s)9=aE7c4&byuqkv=%F(YbpQ3z
zQgz|-53k;|DS7hB=+V_zUB70?3_aX^#+Jg9U%hJhV_#lZ_`z*gKeG1LbCV}8J7fC(
zb<5*@pFZ!Ym7l#l*|qPK{eN}eIkoBO^Y*X&{*~p2uV;9A!xB9g^V9!Hi`cwi;i1#d
zetxq1)C;y<{(@JQkAHh`=(+q3$$L(TroUh4NN$~XYU4HI$IJO|kEY*uYgGQqZ@ud9
zPq)9&Jo2WILmwL6+VkeGpK*BJ=AitSxy^?^Sbf#vNB`r-N1pf3+X^>+FgUPw{0td6
z^|VJ$+<#i(FaLPSBOm+0c`qE<P<^VqvbBHcTjBJ|hqolvw><aX*S_qU71v&n|H10P
zE8~&sjX&soAX-uV#)?O~51*D?TYT=}?%ZojLyxu}T>Tf9%a`)u;rnk{Qh4&#wnx^U
zHejE8&(PzYrw+x{g}u{vp4v-S)Tw!U@Sl0da{pbqLreI4{^X0#v9C?8P7eLnvcu1f
zPcX>|XC1n{aHE+#<&4JiiR+~Lw)&wD-D+gvAHA{h<10FnN8b=1dU0)$6xz=@^tR3H
zd0Cenc%Pgd9lUVCzpt%FYu<cD?Vmg4O?|)j^7cpW{6t%!`p4mc<3HS9c;p}34z0Ff
zvUS5yW3^pmw!XW!v3AfT*KVjkyxJC4Y~4_w?rbnedRIrIb6aaP^uxBNI(MAbUyYX^
z=<E(Vwm#JM`2B5_cqG5PvG#qva_v;d<16`i>d49GP2c(MAsO1a{0D|*!IdJ1KQ^|g
zHZmF}uU~oF;3I2}+r8)A@22D0*?0ZO=(az6^XUGEpDLF(-hV~u`omq-b8fw3{~e#`
zT+{j8z?>_;J@We<|9#@L#cwODzVxExI~~Ul|9;23{br(AUb>?eRifV>o`^5qV+u=>
z)yHj;%GDdsZ(Gs1yZ4?q^sN5i%T4`UTP>YpCc=-eNxDCHU8!<Bn;8llCuMS;biU+V
zQ(4_J-1gSsP`EisI$xgje`ns(;pKade?-`P*WEc#dhjm?h9}-Nvghu}*CnfO+E{w<
zHRs!S=?XVCf4S>kyjt^j{vV1=eDBW(;tL-L>XS>`J~6rSuD$_&<3wb~uzM-}ceTp|
z4+Q4pJ2}+ycMndL_g7@$O#>Z|H3o)V+i|X*{C3=)?~2bF4u@T9%O|Gg_%+YHsa7%*
zmkqnHeYZ{8U-&uByqKtH<vGD_TMGIX?qvtn)af;2Wq+OL#)Thb40()=Ru2rgEt4Y8
zfA^NMJh&v`kg2oR_t=H6q|arWZ|^AaZl#<Q2W9Cl)@08zSDEBJ+Mdp`?C7-m0-({y
zM>{)K?+=G^uV{!|@*lLjg%1Q%=ia=b_V8KKxPNVr`;)aKvZ(a%`Omq%@w=yu%D<h}
zWj}a!?a+!-CmU~FTb4hXxBt+W`zH@xecaT+-#O03=kc2~-%ToCnSY!-mdj7|-5vBc
z>S7Ko%tZ&^xX?szZZ`)mXiFv+&a3UdaQ(K9gY(RR8(QsD`>E#811Hz3)%JSh(vbI`
zC(HDOFSjF?9M|*srENWuZ;7^D$XS_77TW1c7bP~or*Hbgg;zX2e5)M3c$`kM<8@DM
zeEYViF4>hle({)?u@-s!YYPeoFL}2;_>CO{Q`H^$$G`EmxUtY)F@2{c<6>TDMLxTN
zy@D6Eo_yezd2(n4=o6QB9?G3iKKRga$yXkqFLK7Zt^=nph#qGn$bpegBg<B=oPPBQ
zD-Q<ka`4-Mk+|I*T)#*j8_3naazoBU+efDkykK$PqXXUM)^FrY%Wz;C?+Q)hujZAW
zdMIbAmjuSOhh~~@$4+mUC-vd^MYnJ(VSd}^%1+rboVQaa#WKB--yYf!$n<u`{F7rh
zePJ8)T*Eu)4+dKs8*h>6>MhBE;W74$#?n|g8BOzP+v$xiF@-%zgR{bq56sI?U(DG&
zXda~$=Y5QC<9wz)-aEV_Zt#Rx-@-(q>p20o;9M^6J$u{Dq#Vb*Y<{0zF5Tae?%v5<
zc-i!_mL6B_HfH@m#g-QJ?%y~nkLQCvxgeKsRKoi9WnDe?`Rtn6oeKtwq3mZ%PI7US
z?6bY}dU@Gb&AG$F`C`&_lT3H>lsGYO<wzk4_(edzvd7FYKOFAEp7p|n*>fe6zyX^)
z(uoZUVaMb(u?%lxjup@f3YCS2*)tTP<K#eBGE(R&9NNI#xYknrFwaHX@{?id(xBZ9
zhXp;;^Rd^6jPR1UQP{x-x0uovmt8oTZJpMM;j;cNGKSxANytScGeg#(BH~5rT#hT^
z@{oF5Gc=HTRAdUo6JS|G<?G|G@xC+?jK(V}RYmViH<i|^WArvF%qQ#fU^POVzbiK3
z(s`?a+JbGQ{3<r^>zsorY4cub#;1q@oUt-Dy(}xjDLTCq!0-|pCjnDb86XwwqpVkm
zWOdEQq35XTTF)*V4SG<41adg;GH#ZudG}s!O*<HgT|GnEl+yp+k)l+N;VN=j{T-jB
zQ}{e8Nci2JpK#{qQqJA{On>Jm`yC(uTRQqXKiTj2=$W4{_}}^Aw{-X&pP4g1+3)yh
z_#gDlPxd=LXYe~edIsp9v)}QVJ@ey#$LDKLeCnbn)8F|?f5%79{CvUx&X4|v&?o)}
zXM*l~FK2#k<ad2EZ9VhzBEpx<{*KS*PUd%hF3HXtok?1H=I4_C_~1`8Z4JLdbvrcr
zQq8PC1M|e6)4>O=i7YvAr<{dnbGS~Ho>-{0vsM#Udy?^RkzLw7zxH;j{UwfFMY6a$
zj|b7Wa}eU71j%c7uzG1R*mGbV>-C{6oQ83Sf~fjfu5IG>N}Rmi7{WodvP9yQmA1l3
zl=W~B$?Nx8zJJcPf{4Qwe9UQ6kdJeXxZ2K|LiJ$V)TS_B&9yF!^R~c`ud*wvmp$aI
zYz=jJez1-2{)a)G{WR5OdA{~n3F5B)D5lGt$n!AWxhRZJqAwU?MWjxx%0SQje5Jn`
zN?kJ()M`Hm+#LTgy}ERy_0t`bifRVkGXM=P1?wG?2A<_U(++~839K#%*bJMKcbKzT
zJ)oAq{1#Hy_pm3PwvGh~9(<#){<|%fwjl;nPZgu%?W=O3HmOF3RFd0wM7Av~Ckw;K
z@Z?yo@%-E}%4Zuk<;wR^cI80q7*EnICX@wX%eIRLL!%oHcXw~JtwE4%Lx)3Qv@I7*
zR=2ZJj3Hs7n@xrt6<a$Oh2jC$BzVMZ3o4F*So^XmzVU3ritb!!*(13M?cZ!`R3tu+
z@5x64fk9+r_`M<<lbr4okpbAsmZimwlDt%S_05*4bHVfD8?`Wur;2z7NoQ9eZlUAx
zSyQQWPLpDMQph?^&YLQB@ha`gALmzalXESH5Nu?-M?={`p3$Nn<gA>{9{EY;Y7#KG
zx36bUqfF-4X=(S2?2rwP`cxR@yuyPvw8=z0*-KiR!mt#NcG3|s!iX8xMff4~3tVe8
zb|@9H@WZ^MJCO1ftoZC_kL+!ssj;-9$+(X2ke1!|_o71^2w5tII%Z+PX|Zw6Hgc}h
zl$ldNCwWCvH$D(jIL@$t5aJy*t<kn3yxiQVJzdCo8{w|oer?@SzNX>d4cJ^RUDAw@
zrLb;Z)G*qKH;~^o5LYO_5_*giM*%c+HKoncna9@YVkF;WWcjS6umSx;*^>MP<<>zu
zoe~(SM0ESnQ^SsKn=7y~p>?X>sWSzj$H>Ntibb~7{ODUEzn&%Sj+EGH41!e)+gK*7
zU4@|zr2Y*A`%|hC70N7d#9M`W-iTNuTV6&9HA{{C=FE5)c)Mi6f}j>yZf45*O$!ZB
zYBr;bq^lgyK&*Ne>BbBTfuUoOk~l}c*_$OexRIMc7(DLu&~h+=c@KE9Qj*Y4Qr1*t
zf2QYa`=CLMLL8FkAY`9rh*XhYE&vg&4PxZP&>{vzFgV4D7hV5frGxDnhzc%rtwA{H
za*-_)M)g|DxV|OkjbfBjdF6=I2k3{(Mg19vUTHDfAw_Z>LRC{OGwhL6tt6-MSQg72
zsyDJC(Kb(+8{+j{x6?eb)@q1|4_eMp5oEy*{+wfE28<O75aUio)~|!xM45uX`Ya6L
zM_^19$A^SAotRAE7vig|&Bap#8r_?OR?MLClB&b$&Pg3d*`cjD@>YLIJ2iyU;jC}D
z95D}|Fo2(ZX@ND4YJM6Ez>pfU#J5>>nN%eh>ResB8vVrtbOx3FfIw*&KUv|W1L-;`
z&v)r3tf471AR}-8@)_)E@H;eN*SYP(@9U~qJ@cb^AqDz0EU&s`pnVCJp?`B(rYk8e
zGIf1cdb!|bO_5iB6ef<BqY_*Y+K`gnj6VUZxu9Zm0MP5(kRmOLcI7KS9%s1Gj{MYb
zK&i15f)<VPb~BgAg-G!Ebh@`xU#8QhSgtq7CX@E$(8k??sS@&_dGzn;G=#$Zi!lfc
zbZZ2CuG-OIX>P<d!pK_nkcP$^E*chLSRA&&@jzZp<~2<mLJh1Q;?xe70D4Mn@RYd(
zVr&Jpnth}cAqP~6gJ8_RX>SUFaoWlzVf0{Wet6j5sjtC281C9%$$-)F)+}v$gT@2M
zbeh(TUP0)~SHnGAS_u`DSgW3{7Y8Xd`aoqs;-C@rgm`cAOgM^|Q42QJWHGKGfE<hC
z<ssLq4jNXyOI{$aT!{#++9AM~ND(@1i>imv?S#fBUGrgXk)v)QAV3)4!T^MN{JnWI
zsRugWW(kFkn_ikOHA!^<$eZqRGh%%(ZIhZfZP13aVV^EcZ9aZ7W6y|%_Sj(rSuOx&
zxRl;d5mbK0TW`V78=QCyHwD_`q@iAu_9&P%FWycBV2d1TrTv*Q)I%>%ZK0Qf%I9?G
zg`X!m-2kcSE3D$m1y;Sje6?!q6~;yJxEZ>$3Fe5?cxTYHlIj~ej04V~6E;IK?U~G%
zz;RVI;Uy9z$KwHQwf&w+Tn}EvxB@r|5s@Rq$hInMNs+$EB8Xr703-8h%Vl`t2a+~p
zjJ~7tvdo0GU9mh$)6E**<0L{|u-!R}o~Bv^FQYMeN&6QK8ZOmMjZS*>w^BtZ8%`+F
z(VZG?wCGXy@e)kh$cX8Ung3{Op{l|oCn-5n)E;ErXaKx5S|giaq&|k9L~Mu~bcolf
z$BJ=*-)qe=V9E^>vU|=T&4j#XW2wvxKw?A%lgFA&X(~4n_O(9YG!TBZ70>pxU885!
z4A&q1RPksJqvt1?iIP?kiO+J7PBEVeu~L1C)52(V!(ON>$RRQcs*4A;Zn*{SE_Fkz
zKQ5<Wmn^Y3Ejm_DBqScln0$(AVghRyBcgL$2?G+2l4Mj|9dcFjM2mVs=(ai#MK)BC
z35HPX$Wl@bYZK_*Ct;P!?o>i9ZlO%uT%_~?^}TKz(z0e;B4Y<!B12Y8AaxFJ@mohl
z`d*hjPVw2cUic#`;qhYn4T8{_<Q?T|*uE<c#6m-SZZg(^<3ffp?NE8aR38l@&iVTX
z{CK^kmPgKMDwWV^9VjVtS*GG(td+KbStPV8EuMR*@6;n!LxuCmaWcSbr!8VZ#owU{
zb6P_>(2M5n7D%Lw@&E;*6N)~gb*D=%VEiVd6ZiE-;qlgLF)J*nL$nr;KS_eyib@fz
zL~Farz~Uk_r!sZkqJ6N^oU7`K=8wk+!ix2j^buhd^rT1lo7UhWZI_m#B-B-{El8EX
zAj8il2?ztOcfe^eyELGa>xeA05hf`QMUjSjG-uSwn)+3qf_IJgs%<l{vOM)!B#Xtb
z8qe@VhVaa=rIc203Zdl&tbkARui(;~QHOw2XErUB+nZu+$Ol;?2z;CN(>V44ng}k+
zSlLh{AiF6z?9{+ZjHMf&1?y@3a}Y=^yBG0n>4y@=TdOu5Gn55I5lzu0L9cT*+se0k
zNGt<qf&rz8)nIpEL!%KSK8c@a(lo%GeiZ1<=3RJ^!Q0y;XCsLQ*d?#(gyM|T-AEw{
zD5MtP@m8l%v|f*?IUhU7-8dCQHzy|;t6GZ@X!@x5L@G7Xoz{(jKXG_0mmcOJdOki)
zp{tL8RSH5bsi$qx8fph47;!Fu$U-Sq<^*cn{fbryx#-Uv*>P^vXWfQ|)&tleWNamM
zqam+>^l6c2Fl9VC4XGmZ2}zN0rZ;j%xeUK?Txrs`IQ41&^Z;pj18N&c%kHwjhT9A<
z(whJu`EuUjW{rR5^ubt+QBRA_!I-F+CJfq$JXj4HWO#LQbRitENn{|Uq<l0!1t&&5
z<0+|fP7<t<yu%gB1P>bPb4xE_FVXdlY9v7Vsg^JZM%9`e82rM=3No1*QgB?MrJhB2
zQm`S_nxM(TRn1J%&nrDfr2<ayurDXd8%L4>2+C``TahHfrVB7u=s(aWA`XFu`Ygd#
z4FDjuFH|pO?=xXEfB;y0^DX&smL+8dl+bXEa*-4%c-O)M7_A5NlS<dpf19E*h*APV
z>WMx&<?+_bGTxucR+-f8X5}E{Q{iq?DyI(02Ua~95Kif=&xq=;;QT#~goj3wRVwar
zFLxzS$-T^ed|mb-<<={Gj7*QKd*k^0u|5y@Hel5!Vyw;du&Ls(GTX5ZZAp+6Q$;cx
z5=$Q}hB)vx@CrGDmuGe-MrCB6r4X1jK;CD3DFzXM-V(-Tg|v9^BUn=gVneIZ=jUc`
z4c;(k(Vb=Dd_GfNrB#MVAP1b@Z~{`8O#L%=`a<XwjNY^y&0nf-20~)|3ji>-mQsgS
zg$Ai{J%30zD>E;tsmV+SPppBG`Gl;%P{z`UC<_^7g~-bor}1gL<WfmquT(j!JuT}X
zFp#PT%bh33U^L4u$~Ye(6u0;2$A6mCvwY1y-ji5g@sSYvU`FlJ?8M&6#hn|Uda|0Q
znX${KN}Ls~HN+&OMi|}_p$v?=y?WCp@vLk$=tT~y4`>?8;dh1`4)xl3pCOlXpghOl
z^qSNJDcy{QU#$9gB4;3rbAG>hhD|%XCW+QB34K<ZT4}CSAvr-^%0~SyTps+sHJjPq
zm!nmMnV-;8B8%J^PuR?c#XgGHSqGrrzCrbQ=oS1^wrU9J<-wtnNxde(C7c?KaYFrE
zx~I|Wu56Lo!%CefojJ8R3qlpL(BXHf=v!4*HUt{HTDlZyYDO>Fs9-KyuWcG$5h~w<
z@$q=U8pXJ*F#SA&GEb>B#(3#7Mg^hF8g?{b^&9*Fm-heSLvsf*(zhwP#}XeH0#+HG
zgXiP_$jyV}Zs?0}^h)!j`2w<9o(9x13K+|#Z6ehz&6)CsM5P4;KM12iK-=OB6g5i2
zN^I3bNkFW=aScTh4&t~_12zZ@jy{y(=)npPMkYorf^JQN%{w$&jtZW<l(~u+6{C*7
zXN92^r)giGnrBKa;5juisxa4aLKj3g+N9Rv3{@-SQP!Sss#(RrSs2q<h%eDhE=Xy5
z)uk)*(Dp#;_GV%4_@s=(-#pXr(OysW86VWLynwxMzACFswUaI^dvHpoer%dzP&@0J
zK^SmN9kS>&gBdaLn$MX`Lo?T}EIwRAe)>OSSgV{VfmO%fJduX7L{pM1O7RLl6KdUN
z7Cn~wpkHIsCQ6QUWk*BV@S4_t!VYy5kBm%FODIiNS!|ZEOtjKya+b?*%>WY^D2)LT
z1Y%~m90=s-_@kh_Dd=dO!9?>3FQrken<ZokB&G8Xc$Z0mU(3?|8@G;>MDJNPGNw6&
zH6z_BnQanUWze`T8kurw(q4$g1D!@HPHDh<!TNC2e4Yd?3p}9`&w@VJE0Y0bg>j*S
zGzq|JHKAA|fPlYDTdOH(S_-6P#i<WlvA8j_hC3%2rS&A-pf6>-hM*M@!{tJ5fc1BO
zGycwNU+-pp4M;~g(*&PMqw)1}X@pTX1rlOp(3z1_{47_K0A-B&{Vf$c3awLIdPjW9
zh9T5LxOXXTrmxcJf>j35M-LI!p@d<^Dl(;0FTJcfQjtg<1<z=`SLtTucvMp>0ygyr
zDL%bpZ!-s>UK3cKNCzqSFw1NX6yW8Pz&Nr1tBL7a&Mc$@V38>OQwX`7dH^kdFH-}N
z(Yvo~Gv>Exf@ws0PxGT=8+FHMiq1!P9t{}{k_re-YX*qZxvj|%M0>B77nEnnq?kUh
z%tVuIr?J+g3_g&0$+%}%THmi|b+$^Jwi(NNz$UoB|NhG#Z14#1fqK&ZQVUzhg+TP_
z10}uU79@!Snzt+=x@7uiH#-k(=8^f3uQO{h)l>uHESx|l2FDtQST0@5GU@>7m^70^
z`aY0>Bgq;`t5)1+a!LRg;-bGxK?UPe>lQu6h`lL|O0{qLjZJ+`ds{fDFg}9@Kh(Zh
zQ!0O_rG-|tV639LE9hgg@Q`RUkU<{T`2X~si=ve*%UjBy6~D@=a~Up$)P~p#zw*oi
z&t7&mq`s6^K6Envv?o{VF!yj)T_Du<>VYYtg1_5zQj%qr#aE3%nvTC|d1%_kWA)~^
z(y_y0fA%vP5JvzDbT;j`tyg=rNn(pO6Cb1u;~8Iwn-!zaX6E<Afu`sY8E?vyk)(4;
zJHt-RASR21Qv2zYA?R>;xN4ev=ie{*_pM-|uc!Tq7}Z6i)sfUu93-lAs<@}|77L&-
zhKMZ5G$spx_6C><I;eBTqp4o0N5G|A;Gr~FARl-dQqYF0_MQt?&w*TVm7;8l?+LB6
zIQ;4FjHexiCF3v#J5*T3cCrrME0$#vOI@~p9+8Y$%9$3&^Nc>XEXUu+3*j!;Cm*AN
z@y<0_Wh!EwmED#%;i1*4V3$SA-Uqc^_DJa-hfFmY4T~ltqb50<<;8Ys;c3plqhZTx
zkhE)7oPLeRk}C&CIy0}53)L`=Z?}~wlA+SLK6Nl>UKv+Wb|}CK(P5>Rp{S9zufQN=
zf6S7-!#?$Lv^kCkHM>QFe*W<$=m|=Uhtgm6y}87TSCXz6rd_t^<?~L>LEF=5+6J%_
z6Jb5u;WH!13QP${TqIINjuT^0y`&Co5;BBL5EJ(q|IUkeU6YCLGeklUrFTPhSo3WU
zJfG92(L}Rb3+U<m`K^zC7m_i)F{f=>-+dG;F)1WbAbvwZFM{Y}Eg$p5KCMUrEM{=(
zp^pfye|MuHPRFQ2-5*Rkc}Wx?lOG{SdRS8H3^;<KJ9x0Ii7Zb8*77b&*JXi0G&gKq
zz^sI$@%88q!TiB^pRp3XKd?bmB>w}_rsN0-RCwOT%c)y3I_bl_CHD0e1qpA9mm!mt
zaSd5rFK`hCa9#lN5!|B1DB!7>!2`@S%klD_5b=((bd(K4&ww#TGc3K<A*0uDqoQ<@
zez7Q}HZlhWd3?(id*kzv#Jws!T^=J+-|$i|sEd#rY~}Pb`TPW|au8PhWfB@3BZ%yb
zjPjRyDS2XrtaJ527WkmH(J!X6dGrn6xEU-l6BQ|H^RW3Zhf+Dn+MQXiXF_PA@3e9J
zPS#!5Q|9N(`jM~8hU#BQ*F7z=YJ9#F&kw{bKPY$Hv(zfi<Oh;s$2xn*_&wlSq<H3l
z6gPCsBjZytIsSgR=ghn;Ju|k}-D4YWuT1lD(_9ePfu4_3=ta4EX)&2vTD1IDlHIuZ
zL^hKY#k3S{Fx+K>Pj^`%9a&KndvR#}(dT=XG@{RwPCn$K$f8~=eSK3!zVBTe2&FXM
zE4GKQ&6%QIvTlMriCbcdj}g8sC+~jn{N%Bb%jIiNtke9)XCL>i<eZ70+P0lPt^M(r
zUurM;;Wv{T|M`=0>Cbl;7BBdg``i;z^3D%`Q_lY5pC@nm!QXd%_QUtspNzlXUb*wN
zlc)b6vOn85mHfwnqI~<StGmuRGq5X8F4bQD;g8yD&b+Vo(~o@n{GSc4z3vS?J4(x5
zxuf=}la~$O`-Qdk$3H7q_ua6vcK0jSR_}dJU{}AQJ6?A3YJ2}j)@&$!X6c64-*9<#
z<Sm!W$8Rl`?*0A}S$*$u)iXbToL%+#r6W&7z0<3&TvEOFn$ykd@AsDWzPkJFH(Yo6
zXP>z4v~91CmOOP1^<wp7OG@`n_nH^{!)m+d;MU}^X*QvM`?bD&yK<jP&WUfAw*22D
zA8wRn!?*u6`JIu6W!<;`g>NAKnZ&PdNqX*io_zNG7uB{-|6JN`9gvGAUMrs)U7GBE
ztVJ$fwm13RhjOy95hOQ%WL!!oFH2s(^lp3g`#+FeZ>Fm8#V01KUO8GFdBte5>f}<P
zwDfuQ{(5Kp#B@?yH+(|8>{cV)i&s_iujrDMFFGrZKX2@&Hx{M(x}vOpkHq(0CU*5F
z=EbGG^Q7xuDeV&@tFM?>+E>rX>VaImciOQ3tF?5{&Xd)$<hnu4@3fTetuHaF>tWLM
zrPJiJFP|=QaJ`<3Ne)e1FOQ9$RqHM-kkg;&NEY4t3H#!m`;*DGntY)BiewYdSl3^W
zBnxl8MPB^&k0kfq8p-p%x}|pB`Nm#9f4cVRTc_+<JMZRWms4`jZF_5v?-cvJj%fIX
zn@ZL1-?prfU%!_3<XyvG&G*XR<|&swiT&}#tA;mhTxq*5cwTjaLzj1698@2A*Alt&
zUAcJYM_TOtpO31go>sf6bIC~jm3g-NJ>kA9KVzoeaPQKIee-+W>I;^P>|8JPI|n3w
z;;}Ay{dKELJ2!Wl?jVrUf*ck43eDTv5qyvBWW~h1nQy>dn{?T8W$ox>atEhLKalT9
z4mpw6><yB(YFYYnC)9Gh{ki$ok_<oQ<kiJ`VyCRUE$@;&@wBXI8BYp*OXS?0Qg|wk
zsxN16e7<7`&$wZs8kFsYjQk_?99>U!4(HjqaN+rDhU38#IkwMtREI<RwPaPi;rUCX
z`xA^EJv<w;=a$a`nyyZn*zkFAn?BrET{ab&RrGy317q&!TN>wsP%h-B^d^`tceR-K
zUZ1zN9~hDHD%$2j)0@2DO7=rk=UJ)FlSS2`WEE4u*0xs0k_B>7sWn+OpYPvAzePX1
zp!$ON+}err2a~1IW!8OVX?4%}gYv#>x~;ipo!woU7k`2AzIX2^A5Z_Lom%$I>Zg~T
zSpQD6-qvq@uU_#D?|++l-!<#&X5=PQ|L`BgPqn<!y)T(EW-_P;d)^oCd43>E*0dYb
za{+IK7Vi7Z_<q+L-_8aP!vPKxKY!&(X34@pitk|XJ+NxxGkYf4WR;V?Xr=2LTv__U
zD*{SPG=JlD`r!ATnUglg(p8OCiCk-qO={I}qLpEzLrxB(<fMS9jcbvd>xfs3%};t^
zAD6H;HnFt&!Ukt=9tdptz=<;U>ZS3?<}&HwA#$a>O>(1OU~lxl3oT8y&3~S3x#^RP
zai6q|j5hfJJMMlsFCO_wWa?21Kdj=IE9@whI{AINPhZ6RVwvPRiluyX1$lIQxPFq+
zqZsE4`b@e^I@!FGV?V~d3Cf&*yIZ^hd3?I)!<;7dD~I{Kp82`qM^Hz_ptgz!jI-#g
zkDmzT%v%NuYlbRu3lEg+s!Ym3TcLx!V=G2&VR=3rK5ZaZ_|vE&3+79qf4&T#HD9WK
z)?uVIZwk`hTlm!c(0(ZYdV5FS#LMz4tG8URGA`{LiOaW@;yo>8xhqJjg<$u{Cb^wc
zsAcwyhVjDDWTb0;=e}FUW$N9dVQHc4;rl!9t?nZJv&;h*?q$EYN%rkxN61}4SNv(|
zj6XimU0QyVn6pPY7|rA1YU!NV6?MA1T7vk~9eoookYee+C}-}7!iK>NfS&pJatodg
z&XF4?1gpqj3)4Ts!zPFen#UCb`Yn0c?gCl-oFFJXH>k*QT~T48T?*d|OyN|f7j0sy
zg%&=e-cpa-Mk`ge99!P0>o<dfMU8U2XkXd3MR9c!n-^qNya>ISyYA~`&cJto<5T30
z={DItoV1kN&PMl>>^n_co_B2lW8JvKcQM02Mg5)-^o{u4w$tPyDNVK{9d|hs-{pws
z*GAvfD)B!_F}SP9S{2lLBK@>`S@ZhnBuiOa(diBXeX*(KutD;GPEDi970l71+!7vF
zBIbs?#~5|e5t>atEPaL69YrZ8COL(?^0mV4XERedbE%Qv4(8LpNP#Ycy*+`H`huRs
zNOcb)a($yriRe>Eliy~jUP?biFK9P$osF2VC8*+{g_KaY6!L(=XPDz8GDFPL`g4Xv
zB(kTOB;F}?KkpvfNn*+X<=1d^4;QNn#0MSdVD6T%1c`#4`Ps*aLSLv!2pU@N!jZZu
z+WRB1Vz}mj5+z&?PUdzB*5A=7b2G=OYoX*)P%aM{9g;LD9uYh?y{nfAvI?I8rLtTN
zF2MLZw@e_^bM<h|XwPIMgu%b_Yw|af^>l{2=EG9pC?qbsa4eSxlR7N2&SXI`I=%I8
zr3^hBKU4)OjraLeVJSFujK6&R5kf#ind+}JbCOLB>XG!q?0vTyJqJ>*Su|?_%l}2s
z{LH^wsf=)@=MOmJbA9?dKbt<}&-9%4{!Pu_`Dy-+PxZddzsI?oKh`rnSEpxw&gP8I
z&j~*~=giM1`!2qB^ATr$zVQ(a5AnM`>6xDmKYZB+f95CsouBM?d@gDJ&JW>Dobl1~
zMx6Os{tnLc5Z<h3eqQ8%=ZCcCocTF^PTKs=&%Lkw?jz~%_;BV&!<(gRDwYLfJYTs`
z&%p56%T{TX7JHKm?VZwUj|;`>TBd*gc`zqy+`^<Q=uE1-Y0Qs_ecn_eD@~7_-RQJ0
zb|=^s6LcQ;wAi!z#GX|@-d1<EBzYIfk|1Y$2gGjJ8Q2XI?5DFiOFw1X<_ET2A{jB1
zTajnnpwpg#*K`Kfv`Br(bk*A@d8{Y|Xpzu&iD~al;O(pjhQ5iOpgjmV;1`%tVeGMi
zsnb^Xs>)@#=V!tb*g!}-mU!7ddWjiuKEE@;V|mQcky*Vt0v#L?`acU~vZ&X;63nXe
zXY|8!Az2|ottG6`t~&JGNFsOVk{97P3G5>6`JwI__f5#^UdNGfV>MaU<!byAuVL-X
zf9Fs4n68mff~aIa<zUM#u&v-ukK&Oi4hjbP#Q}TJZ!&f{iyLPN>)Vv8#HZQc<Hu?k
z@<ps9i$^8q9W`TOXxS2!gpNS4#j>`c+qbKvKtJ3viGr5?o#U{PW#NMN!x|s!`n^@_
z@C_4P0-{ck1do$A5Kw>Nna?z-S39Ig>U^-2@sTv(3n5WYZ^YiyxYgytJmY9!5=XZm
z=ok2lj3;9B>nnCtapNq%NS)Jea&Lq@ty6hjTh?DRM5fjEB_Qz|(njCDObvcpf<&Qo
zlSS18j<7T)eCJ*wcz{6M2+kNfbp)hIE<?ifgA*Ga`Bfs{KkB~2NXu^QNyOX+T30Ld
zga+q?Je;JqkiaHm`mV;<*l2jU@cDD2HC`33qfU=g9sBr61r^<zEM_&v1o@<c@xPC@
zsOBle#+PfcC5)B+9O<n|3vrD1>}!?dNB#LHD^8N#*qSfU>m-!9gT(ViVW1WcMveqf
zLQB(wrT-ucWC%U*Sg?gWeFcFks!LpyupK1b4R@qN!#u>Ot|&;~ovue?R^~aZ?MV)q
z<A@R?0Vi|R0uty*Y^ga~6-<}3luV`o0xf+9-_z>i<2U35!sdR_GBlK(8ABLgoG&{j
z<PwC=MWrNI2O6SIQ*xu68zVH3h=Ek=N4ks-PQh|9?~6kXV6;}LXxaUQedkk}`H;u6
zJY)uOfrJ*K6bKu$L{8L@FALRAA@t{;z)>Mt@$!PnCicgAR?`R~_T;!w_9{y-s7!U8
z0w^gmID1K*w*)-&O3`4@3Ehd8*CO&c!Olh##*A2>b#kEXa&IDGzp}PJ6NqnnUM&*0
zh;>R=)}n@8_0f5eCJGpw20RKWCV<{ATzP9k?HSWJLaGY$L!*TUrA1;r8Ta|tv_(}U
zgQEFT*a45ac`Ay6eo;<ib#Ez9(pzX{+~L=p;d(G$AC<`O58z~PW_+9@tO}_cTKU`a
zMXu)ewPNb8|H3g*&kCttsV>h<ME+)=neAiI&k!HO)8ubjMM;~uxolayX5?7`zNT6;
zG?}a!)t!$~?A#R7iZjDRC-qD^5bx&D{3hO~>34({T3$c-&@;+Cg6<h9o*n7yijST#
z!_y7*H1^pP&5?1>Vwxj~e$~*dMsT=a!j;9FUqW_d^lUzkrMQZowbPLj(va2oto$;W
zT3(}#Cb4aLep6R%F;@po%ny#glEB$~J{x(H;@Rww#UHbcA^T}{I7@G)C>`U*Trg>1
zCZ3?<nj20j=G>o6$0mu|$u$E<x|x2yynIZWFYa1iXI$H)wu}+#pTxtzBV&vcbPW2a
zt><z%%Vg-)6=y@s<Ft}lGr)p}0q3;G=PBFauX9PrAK;|c4`mdDVmy|`2iyo=nP!y7
zuRMOkbl8@5^n^o2PH?Qi5RKQuWJS%Cq~|Lfzj;Ae(^bVoE6%{B?|NW0nqN)~5b$hX
z?{tjT6d8Rc#B9`9r)j0GrzUI|l5@P~);V896mr4n5gCI_CD1`#V<IVXm&qPf%>XXO
zUkMy<K0&!Yr3-8+i{4_W4OQ}srHo0d4=gHG;;~NWkhy-8SqE_ufzS%<Xy}5Ud`0A6
zUqg`dJ#)ZoKR4_&a0E%3!wd_(Q3_2}b(;%{I~rPrC0~F{0Y|6ikx#>#j5>`y;_e6?
zo$L_=8aOHycU0KZ&k>>qpUtt;Xyy$LCk3*l)HQ!M8Pef4Wu$q_B2q`AkAfqqn!K|_
zzCIqMs?Kpp$63ZQ%I~Z1YLdGwbzEI9QD`$FPCW{(dia%R11(6GT102y8q~U_EY^tC
zJ;EhRy;pSt3)1hOiTVt69F#B7Msw$7Iy<tCh%`xk5VM3*aI@v#o5ec>`?l#wpv2rW
zv-7#J7w`K8&+NF5r((Pbsw9yUs|xgjwkVgwHC(=3x;drH4BLWN2)V3!oF(&woX>;*
z&BK6<r!!%lr=kx)OPPTpKA(Hs(HY7ttBwh5%97-ml#&%|DiETdDy2_hH~>#|hE)Ab
z8lq89M)AJ<4*pPmOwzrgO(QC<306J+CS#e8GOH<8%g(BYy(=#C9`XH`63&Gn4M5_&
z&xBUp4!xmYLVTJP=P}0Lxv9r;xl90F1>^7B5a`QNsa%Ro<unOWPE2ByHU-!89O1Ht
zXfn&Dc!$G9%2xCFjNqDB?LS#~)u7Qe>t_b1dLnQJ0<GXPkZGvnjPuC3c{vEiV@-+;
zq*KScf4{|3u2ac#Kr2Cp$fVAR{MEfj@E#HP)n&}3oSUJ!_-FLHwDCM++<y+z9wEjM
zQU%ijviP13N5`3?NYZ+66tWpSVY|qdH)-gYru?;x)Rc{@W!{7%5||0h*5erz409`_
z^3SH9($9vQ(vRiNmE5G8tJ%@1HEC!#v)*6J*Od6{>G=#vyyd(jkVnYVvdds@Zc>z=
zS~a7OaG%K<M-Ut{@PEdAOwmV2{u)UgVV6wKGvSU-Vs5xuW{R8ZpG(v9|FU?|vU%q_
zn&kf<xU=nQZsK$GKGHtAIQ**sHEpI`W;{=0G*83)dWgBY%+>kVlaf-;mE|!yM*Z|X
z&nn73YmAP9N5awJBV&&pdYWFxCO>AZBlhWbdOBvVkSu))^x5d<;D6<eHVJ2XBvtL0
zFejBG=w|R*Ublbhh&Te~XvAzd)j{v67EMb(bDL1UnY3nw{EEJ2eveJw)F7prP3=hh
zTs@90SNR-QbEb~hXLVL`+Dwlv1unq(yWX;uf~VE;IV7HTZYnd(O(NshJg%Q9|6|&A
zmZ~WyYI?-Z_<p%(PRn$&5`H<~e=fzdTl<+U_Me;jvq^JLk7$}bb+vtcYwy#j{%dr8
z_BN;rJi7&-rrvLk_)kgXS%oxh>-B5aMc3?#(g)OI8v)KH-!o=X%WHM{8KaKLcNE7n
z(>`myj^h4*!K3Z>tnEe1>uqm7rooP=G)GY$oz79w{{_MS|I`8ZEV+9oTR#)-S=eXL
zN7^=%pyl<-=Xjd`+m`sho!*Qg{tG-u+xE!te`11KUf<g_Bal)w8c?@6KYDumYR(v%
zTJd@wo@3cRs~w)^Sah0p2FyjCjdB*R8Z@;~KAnYWT22Gc2u<G9oy!Zi&+1KHf-*Pr
zdBjr84Bp{;CjMxK-|G=8U6z0KGJa{=O+E0Y>gu@WY3K6$SdY)<mmggr^7Su!^bry=
z!r#=fzbWJY<NM7maO=HK=WRANEoY$6q_B8gGmyE)yRKOYsShrTX*RcJy_=muWdwc_
zHK+21O-`+<CL?M(O`Wo^=WWKhqmagjQ=N|D%P40Zmw7XRN9&}qGb);lw&|$sIf@*?
z>zYKFYmN$ML6zMUF|%&(TpFtpCiTuLk%l`mbkmvP6*nu8!r)Exc!!qbt2U>khPQr3
zrc4y+6-B9i^aS`Q{XxLn-w-z5XIU${%g}j&j(2L4ytytXyZ}-@Biu+T)dN1m`&Xmd
zT9@)l!}nN8GRf<vBtb0S>g0f==kvUpaoxQX7=unm^)W`@A@ikrY1S6l%3(OBI_Vd|
zRhx*5cXf`7lRq%S2Jg7nDb@{Y+K1*OFkU|SvAm<UNCeFrWez9kOZZf$EGv<dh#03F
zDX$UqGHM3$#N{`>>26Bp^Sq%|ouW8$4!uUv2MGp6Go3Jzq}foV0xop&cHoBGRxexm
z96G_x=72OmLRLioQJAl0>+w`R`KWf1pL`W{EOM<&bt2$58G!QbHPQAuMu==%^ina9
z`U`^_ya4vnM4~Va>OIK3Vd_!2DnP;4P>hC0%OBPBn%iCj5CC_JqrBdOUu~^6<E}cX
zQJm_eQT{Fg5(7!gpEMOY!A0Hyc)3CtxonyZ#j7^lcmZjA`Fmrl!DBrNkn$QOO!+)-
zR{p6@%8O(z|5=@!GI-Ej`m9=9y;P*W|MYp$#6#Mg<_Db|L2>`Pox8`8qlf|kJZr6x
z&p^~iSRgPG$p|A$4mJUC0VF~)4$vVHA;cv12?#g`84?mVf%odCySjJ&3_=3wt6;ji
zs@|(NU-hh4W^hzGr$C8|XR^$-QijiK#Kb>Jdd%QsbmzzzmuxYUAH@4S$M53%+pXQ@
z^;k3avAkwQiIXM7Ye|)tXeDG5kt)&pcY|`vy69=_-4v7A`qPm$)sgbr%gvi<E<^1-
z#LSfU&*J%N<8c|f>tOcs4P+|`+kdt1d*=9@FRe|z)2?Gp@x+erXNk+N-(;KeWpIkS
zv8Lj1%r(*Gxm+S)#MZovL!HTqx@fAE$Js11@lAxfXRj&0ioLWsdsDt-D?gXxS_AT@
z&ZSmPINn9gH#|>Q;xcEAeeXj0sm+bm=1`4nlTR+&*&16kL+)BzWA}TWh;2kUbN#)H
zJ4fz_-PW|<FV?q5`bkZ5{~OiwHN~@(pVwc0Zrj#xfJdfjtYg??8Si!U^WW~#XM2`f
zTR;DCc8z;de+%xhJ=gvkpVu~&dB@!QmFs=(n(uYLXRT(fX^mKWJ+_Vv`xS~ByQ%rf
z`LDY!S(kI}&q&Th?i`=9A9>q3=iSmWcZ}DX4!?a?CR$DNvMM{}&)1sc*xq;6G1Ol^
z%eDT)w6C$giOu`kq#tkcoHOs3yX76k$B68&JC1SVs%gAg`fFScor_(Tmrku_JpXI4
zYu+Ba%^35QD2999UfCL3Pil;8b9v5XxW^7_=GL$0pXd0+>oPRv9oCobQcT?SI`(UB
zx&J4zx8(n~)?Bi=w&xhzpWACOx6F@ubN$`-zn>4QpV#tG9owoni+zes{CHOHdj4bV
znDpFutm#u1YZ`M6{T@3Eo$j7aemuQ+7(E@A3y#aGam{+p#|`p2zP#Vfd?s7hthtv>
z@*E$3D7WK&%Y5s+>v`?t`~9Wgllq$f;`NfvwR*?c^(?MMU7sKG=IXnj-kc43K73wt
zQ9j_;9`Zh)XW!5NmblD+?wothT(fVN=Jsp<?)~2EmOL4AOWe4opY#3U_RnjN>DTdR
zL9er%<B#?KnaKT4oX4r(x0llL99#aW=d9QGCmTwqo<h&N1m@gYSln!8N@V-pApS1l
z{IfNcl_h#f(4VdIVYQ|fy4iVC(&3m(%F9~p`PeyE4=oC6rPQqXx<(&|mDycq@-E-Z
z{qj4~x_i#GmbtfQ^Y)K26|r;a{HYNjK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBly@V^y!|M2;tw})qk!`<Pl*DpVv9$L%J2igDRo0qR1AM*Cahw&1f7ay1LZ@+x?
SSeCcpkLvLALnJ$V{p(+^#$&|*

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/hit20v3.sld b/FPGA_firmware/output_files/hit20v3.sld
new file mode 100644
index 0000000..75171fe
--- /dev/null
+++ b/FPGA_firmware/output_files/hit20v3.sld
@@ -0,0 +1,24 @@
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="clkctrl:clkctrl_inst0" name="clkctrl_inst0">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"/>
+      </assignment_values>
+    </sld_info>
+    <sld_info hpath="clkctrl:clkctrl_inst1" name="clkctrl_inst1">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"/>
+      </assignment_values>
+    </sld_info>
+    <sld_info hpath="q_sys:q_sys_inst" name="q_sys_inst">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME q_sys HAS_SOPCINFO 1 GENERATION_ID 1728634208"/>
+      </assignment_values>
+    </sld_info>
+    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>
diff --git a/FPGA_firmware/output_files/hit20v3.sof b/FPGA_firmware/output_files/hit20v3.sof
new file mode 100644
index 0000000000000000000000000000000000000000..377c904392cf65807a75ef41883e9567dfcf319e
GIT binary patch
literal 3434231
zcmaI61CV4v*Dc!Cv~AnAZQHhO+qP}n=CnC&+nRR2p6~l_y!#^VeHl?Z*I9e*tjatU
zmAiHxB{@-me+};E1qdMZV-;Ks9GzX9@Z}vXY)tTl>}>2UtW6y8RZSe7EbMIY88~Pe
zXzB3<T`a7P@mbmE@##6}7#Zmp=@~fil_c?{Eu2m8MT{++f3yHV00=(=GSJJg&<hKQ
zGP5%av5JW(0RRIO|Ip;BtOBBJ^7QlqjM5rPvKDqu_!1KMA~uF5#>OVbKW}emWa8vx
z=ZG(2Yvkx*@BG8rxj5UqICK54KtbW3KxIb@dutOKC3}+}frzuYiKDH_|B?s_i7@;~
zlq}3_4Xp8%4eb9X^oJMvKk=eJ?T1&fwX(Hyv*n@y;QG%5Qpm$zKi6oMa#_mJUcp&g
z01yH6e<tt^_X7U${hv1b&;A1V`tQ~M)q=l>{lxt=`hSM6AMao1|IhrN8WI5f|IqjV
z_&*2`ASEdSkQe}73HX2b|N8$~V-u&JN$Qy!IGNKLTG;+DJnV#-n}Jbl)Dr*1(0dSO
z0Du_(Ab<%t0Kk7&QqT0~);iIdTR1b)yE4&Q8e0IkXCG->+3m9<fA;nf?mw7kf=B|k
zP?_MHG*T7-JF6CLrJx`JXM_?bu{(EW;`Ob<&c+Y(Ye3E_TSiPjP2AlPJx{yX8O;h9
zAbXFn3e@sJ`hLqK+NNPVVk$CG<w`i6U~*g|kAbip-szN_D`QozH)D4du#U<KwOCD0
zqEPv?sC>BYd%DAPOH0A(wzKwDkvraKUYq}I5v|d=IUkBd)--li%jghJL0kUoKwlv)
z5lzHp->?1U+xMZdWdZ)_ni{PkXo!a3>3|biI*ww&b_9&wh;5crLHlrte+Ma3`a*3N
z#VsS%lzhO3+&4<|j3#Y(Pt?;qR1DgerR)oPzlE==px;HqI8?sdC5-_dmqZcCV-+wj
zWgJ2f>nM4m{+VCXZBLY_j{7EAO@XP^VAU4+E3|3#Q}CMmQM02%8c-hNOS2aylVeU3
z#ez4ZaVjh2m|3Alg&3+4HI21;LHSTq2doP;){yOXpf<5m_Pq#2!%2EKOJ&8i^l<1z
zC&aLnty=t$B^Vog!{5vU(iFLtJ;b6QaG^g#&2xgQjk)bslznGl=Yjs^u_hP<l%F9&
z+plx<4Tvaa%AAAszP-GpBn%G6_?e57@%Ov0?p-G3YUYz@Q*S^3hf!UGoerP$xNH<S
zg2py+1d(tyfTv=-uruZBYZy_@wMql#oW6kISK{|;3iBW3%)01%D#{{cN}+`9xS_vT
z2rKF&DU+|XVU7`?_Ch0Z@W>i;;cK&5sh!rD`xabrA#<qaP$e`Dn^LPOipY{msli9k
z1L5xTB~w`jRFw+|9WSxj|3Cwh&WCn(3037vE78J-z@NxUXX@mIhJHyS5%LNQ9fcOy
zkVH;ob&F~!5|*MLRfN1E84wjtmtoD5cEYM>t$0snBZ|tII(dmvK+0&OydqO)p(PF!
zi3@rCf;x(%rKp;64N^g|tgsSi1kusLlL>Z+;&QKdTOUnk9p3v&iIpS;R7nNa09oRE
z$*-<siu}$<{Bufku4)Um&@)zX2(r=&_Huj}4@&QymS|@OA75tZHRQ1n`79OCjyj^}
z7%A@a_fZqxJ)aB2Hd9#V2qW8_&f&J?BC)%DV(^a5cH+4JU!OIpqiB-}srhJ=KU_W0
z6lF-*&$1*&6INeC+UpwfvO{>s3cpt>h6z$pD!T{ZoWw67UFt0+eC_4RgJeRqV$+5t
zbxHS_wdIDzm`Zxye{Xn<Z|Tmn-(<gdL}GR+?c9f>w5s3Ub4DEQt2>JPfhA3IGMuPt
zq+Wf>QNMpnXgJhmH{06<1zh6V>?l~Wa-?b=_InOO^MhH9ud7;KZ&}|RRe^hY9zV?*
zKSid`;@FOj=H@>@@L2&D>i-?JREwwBYnJ{gfB}^!(zSCjubGm#C)Uq}+Az09;*c;W
zDYF;opSwsA9l@9l47|G$#QLTm9ok_A6x;t|{_zLT*-_{$#j@$cd=Pd{s1M>)Q<Xh>
z!3fGV_+*WY9!Z$~x5g}0eC97yE&3S!beq9xiXfhXBhA-*eSUXI4uQUJv_41($GNp%
zmnS(5c_9nAqCUK2&zsyma0<~5j2Zl5*~GXy(qIM%h<@HrkGKn*IRU)bsIKE!w31?2
z7R~IISw#W_u;0bMErUJW19}$UXQ9BJwb$B4ab0E6P7e;?W57h)s^H=c2)CAaxlcQQ
zkJzif7EiDA-^{kSv7#M-fVgxHsZST(iMXQK)4EY5W@5>^m9}wKG4!7>4QHQzjcxDs
z1cnXQG33B(#}3LO=Z46wPyEH)f0V6r;k7c=x~cZ6Qmikhe=qgr&h%7mKG&GHG!yCK
zrPBPYHfJ*vvC2lN@la*%q+^Gn)mf)z`(<uBGE0y1x|nDJ>4&>MLWN!I!KZym?;e0b
z0=dHqYMn}fMCUH>Kw&3qmP8oq(Cq)m%tIK<gv}O<zKddG3|`zYx^!&};Sia3@^x@S
z0(pKJpWbA9f6J(POv)HR-Xj}eiX*p(<MJr7{;kUCtmFxX&<e`SaZS1lDXnRC_eyOo
z)qV-jTnER;a{)Kn3m8mL%}W@#N2h+_gb(c*!K*%i99_Fx@&vdvDq|Ym_V08o1E<G9
zTiv<B&?~aUbA?ce=;*0bfULEE^PmrIjM(P@{nKJ*BhOq*0_>F;ra!dQMgnj9>N;5=
z4~)y>nD|9u!8}U~_#D3%NI!RdjjxtttCvyJBZiJij_BF)u^xA^(gm@)N1EzcirU0;
zt_`9`%@NsyqJken)sXG++qSCo30-T5@nsv1(4QOPz`mre$+EpP0>+kHS{jCuxOI4#
z_c$BRQys<PTHAAAo3pBfWY417C6iatt<;j+UM=3r7W}G6Tm?Ily6wqX6}#h(P0sP2
z%6rurkMk)2j+Pz;tS3vE6s&JG8w=0WXeB!e?GOJjTBljrYKIFu%?)ycYYag%-tlN{
ztXx0i)HnRSv-L@~O7UE-*y_`#+D6b0#HRe;9>H6kdZOD+<?Rvz3Cs=eH@08E>N)-(
z|NCxC1o(g1jh(EGe|F>L<Q>@{di0SSpU6_Wemoc=5b5wjM}qRp(cxl>YOLkj->v0R
z-tH7Z5uqd0d!typ*-A5MJ8lYkjiBq{=NZUQ3cb}casan26(LKO`2rmSmC*VFx=<wP
zt36rLlt@6atHyY)$F&7#{fY}HdPuc%Sf(rqK8%TgBD~4~H%(*EBzra>owD{wrsPsL
zwEKsYps4M!iKhhFV-|t?Qu-XVMjWLaO$7~jR@mtmSUgJz(JSahPktDB37e92KCR?D
z+x;1#H8dYV)}~!EXBjq~O7RvtD;;50Dra$WzmXS?5l^<0NRe7>M<P|VvjS01b1D(<
zECuEw?d?9`L86a=qHF-bQ$F`$KbWQw!5@5U?oVTUsz|pZ^3wXznwOQ2y0-siHe~<F
zY&?;EG9g1c3wyes#bab<Fkxh(H=r}HcGmm3)-yFQq;;~hH?pubwfkAwD;_PkBKD-4
zPpW2*bszJwcquX;?$_82*M)6~%j&D&Y!AZ(`NYyj`5nbvWIG>!Q-(*tfWZO`IchSJ
zoZ$ss5|mXc6D526KD9G<F*<V%wEA$wbFKmXQ%x^IpI$Zww)XE2{tWcd@;-{Df~Wl@
z%@!DQ_0g}8df5oDe2X+YpA7Q!1L(y_&83iJi;C11dcWHJKK7f2qviGA_Vf9GptW(U
zcyo}!&v7HRf2;WQ_0D(;j5bQgU9YU?Z>rU6sm{ObG9*?~2?>1>(CnYf`3=nL8@-Xz
zb?+c{?n(^#`9+=M&C8+TwIL>xLArEn*6#}-r3EK_3b?$$08iz8Afm@!88!Y?fR(V-
zrzM@TcN%x6U#$IXH@fO);K)Dg=de4nbKbPhpmNc`^jBwic$<J?^d?V*$sdjFldt6Z
z=t`x}4IOn?jng^CtXz+~ycFCk?2gD6lm_Kar|)(PpeG_v+$+>9KkTLGg#pN9I4{`m
zK=Ec|=tB`glmf^ztimn)bSU_ohPqsc3yqj9UnOHFR&=OJ!>`@XxNc834VcrLmD#<5
z7UrSkSRPz44etDG^p&VNzv}H4lecnxYE!*7!Ow1kRJjJG(ujG3fV0r%*E9yBphqa>
z352C~Cq<RRnWQ!mg|sC0vY+HC5xPDCXK?N@=3jMlpy7EjBvHj?VB7IN`~e6RhduCb
zNFX#{xcn0#9QV1u^J=*K`&cdTzLCWpCsnDT>-dRoO?;t6uP>H`-dD4Ih{~<8!|h73
zk3~!xylO62(!5=(v&L61-ZgQPoE61slARUi)}@@5N&OSf?22HET@!{myhHbF5{Vwe
zcrqSGI|qCF7pjkOvF^iuyqeUbNmU*_^G}%TtN_!9`B>)sL>+rUM?qEiQcys~v%7SI
zVMPbS>l~6`+^0Z8D!%BQ-yp`j?xRHPeSDwJv^hh5{i!P?7Co=F3vU*-7v+wn9=Kfw
z_B=Qrx@}0%INe{s@O}Gy?#0!9ESc1nilan0MOr4@9oZ{aMP${A{TFVaXM3}UZGmEE
zeuI20WG~Uas&cO+ktS=o)oYn|7#1icyE?~MINRWH;&BzT@~?Z9vA|o|bxxL_;1|7S
zLr=iV%3sgRVn@19&{s}(VKa+U$6})k416c4h_LYiSPtN;f=<XacHYac)nL6np30rw
zv6oqQ)~q=;DepSC4tmmdDRpjot%P)U;UD^*PFy*0p-^a(zgkN81WBwxDX`FZ`PDoc
zdH51%XsnuSZXLa-4{vKZtry+oJDTph!R=V#t!k=Utp=mv3K-$8tL;)hhb)tTv!tdt
zsm+DGR?6!8tjQnft&he-;|e(ONc-eUzjJTNGak0UMZSUv!3Sr?1t{S=;V2P12sls?
zCv-2*maV1Wp!EV$ed8T)g7NFq^aD^oslq7jt(S_ycjd;O^I@;`Sku0S3H&b`;UG|U
z=75x34k)R@1i_(MF-Ll}9&`45#kp|d!~dB3y7lzO>RtwqThKhRT0iHVdyK~m<CMcm
zYrUf)w)*HF|G6s3QD2EN*-~fcTEx*1U4!<V^WzJ)iA*?GK7v5(4X1)93%M_r&%aEi
z4%8#&T`9@ioAzNoGs@l{i$`&NL_0Om)rMCnb{Btngq08wPTdPt+%vT10JQW`fmg*h
zJs3H&xS{``qIN+zp&c9@&qG*u<#1kN6xOEV*T;NuVGzgsEdX>!lsekc_)5|4H=Bq7
zN!<*jONiyygEwB-6=d^?vZU-5EQAZk;Geb;Y$)^{ar&qP^-RC$OTj(Xk_W>Ka6C6M
zI64)89!U_b%z<8D|C~c#VDAeP5_DL#Z?$9I9Ft6RE}@j-3<KExs0kdMRSB!k_MaYb
zt#qO4HU0{Uvc(O(GB4`>rDDH*&PjSm4qS1bS)sc>pjJ?~@T8JpS#|+`;Oxq<N<*i)
zbPw8YuQD|(pZ^k6=8a&b>@GM8XcMF588#>|$v~W6X7!vQzCC(jMl@*tB@O{a<{oml
zDJ>YhLj4;GF7Xy0GDsKwaWG$wI!EU<w*4NH!yNOM!v}0}D*Tur_Dv7FYNxW|T{}Pi
z!SQ+cq2O)F8$T~a>O=|y{;8xhE?h^rcLnLI$gR}GnAL#b{R2b(Ls#(!rA6PbZCbU}
zi$rgJdQUjrw8YdRny`cPE1bpp-jYx+#J2wB`CS6e7tCeJt5remFus7~b>(GjxClhJ
z4(zz<`kw5kI@@!*ULT*4JYblOU&dydk7V0jq3|H?%3ixD-EZacOnn50{vhMD(|-If
zG`dfsd7*-gCkG|qw{WlM3@^*8F#dkx0n$*`{(hJJa2tLij@Y|+iboJAAh}e4_fg0=
zMTFDNfL{clWCj7C<8+G7k&)w~%FNO}<uB!y#|g^s$+e--9Pu8+%QFkh+&I(8mrNDz
zxwYkI6!k9*#=>qz1JYg!JQO-`l4p^J9Mu$MR-9*%vWhq4i-p-13bK~CWmaHkkphZ0
z#6nRC2C)cCVw291ro|mb!!*9@<_wGa$~V+gI7CA^#ipft+0G(lwPbEhn-k6CWGqZP
zNX1lO5<Hu9p;h@|r){9d_;?8mHvr$kz<N*@dts+|A4CTf_j1fkLpue`0CffA17c!2
z-p5Mc_dvQrcVT@HBhH<+0nO2Rc4@J9--6B%^8~_Uw8CLaHMCszTkC^Dm1Nw-k%L0I
zkZ`!0f3d=Rzb<z+byqjbeiIRV?#W}wp%(oy@uOFKd#IZ5&DBC+s58t95BGp1tFmu|
z`e#bFqLp=Jk9k)d$;iCOtX_Rt|KWQqE)BL8#0IAn+rqT*qOj@(x2n`#xyQDW%;PC|
zIW4O&L;RC$oECSdkFbts5C>Rln?Om|>Xdb2neq}J1u1pUIZ6_}chRz>`{y@H)34rh
zn|*k!GpmJL9L+NmGR+knY>qOGee?PC^~fiQRB@g=rkN2<eh3}gaZ4kbUAms<VcRDq
zl3v?ph}QcIM7=hOG+Y<iWa~i@ogLhc@`gx#2jViG_V$)Yf0jiXrHroS0nM7h7D^yl
zvF>#tf-PGg<9MF|5R9cCV1FA6$=bg6c52R<6)Sk9co&Ldbxsr%lp|d~0JADKW)K`B
zG=i0ZVrPu$3?#Y+q8zlQ&oTg032958xeJD4r``~18pt#V#wN`$fMIYTe<y1CBL~az
zM_?5&F&?*tnv|L6V2?kh4EowG?1<H@l5NC!X%>j|F0}aoZ3)vw#P!@OI7wyRqh3cd
zQ&58A(b;Uaf$JgWejLH|v;fETjL37K<$e@Abre$7!hKsAw&j8I@zS^QIHi!|XMLV)
z6Sb9r^RcqG@;ud2K5pTDv>7aUoNEge#KQGN9iQ_$)zBBZDKHCwX$i|kup;Mqq^>Xc
zJJ-}7x-B#t%(nC+TKf@YL>pSd@gzaYUKE%OV@ksDWc>#+4pi_wT9dNZgyl|v)SVTS
z4HawzM)mS|^|VIiB02*uFMB_#D5dQ7IzvxwNUI2XV)Q8vT18QoQAuPHt6yCM$vW)9
zBYR@IbJ&ZIPSBl`p|}Cw-t-~IYV4(NS&dOAqIY%t@(0)+(E$LtrM(7%0PK6x0RYWn
zVANu`>|fsPny(yD^b~J@pGk&48^R!@6G^l<NgTN2C=QO@xig7>r$`#%#czNUSLf~8
z0!Q}MwS2}`Q8Ij9S{)JL3gC~^=V(r=G}!7t@(~6Ueg5T;RbAbD%HfS;$;RD6tC(RV
z!z0~{@@_{;^)V50l|;`k!QMovUc}wjBKs&Z7_)6ayRE{?`dK;kM6;1uPj+y{#&XAG
zGBT-g3it1ucqFYXz6X?Q$f4!|Dus_$t8amtsFGGsa9Bt}J+j_0y>W?XlbWZRGfZ{6
z-1uTs(tIxA1yZ&JN?AyCM)%HkaM5=zLTUTvC%HAXQT0We{XS0YA)xJ9j}oXF32mHH
z-S=M4AmL<NtMxBa>ZF)WgR3pv`#qG`N&IU6V(*L%2Wa2SNYlxlMu}0v4`!e&rI0ZG
zFpo7B0yn2puY}v3SUf5*mDs%P%x3Y*+-9Qep|!{@Y}j~-Cw)U2Rg)po(M@Py_*-ms
zGR=Wg#~0>9$h}L*j}a#}`K}rhQqk9S6=#v3JY8G%VtU&aZMx>^d#)&%c2KSzpE|j-
zLXQ1#_+Qr2drddG7~vSy-k3Mx+4sBjb1$Dyk36mDYu~mt2RdS?w>^6X%-9g-tt~w~
zbojDePSDa80VB~-I|CW_WZc-91yeUBdBnalzk+ei_YZAckrnfqUk5J5!`YD_hO|N(
zbZOFvwWkkH=G95@|D;UMPOkXJa`9l8v0s~V$5C67kOG_6s*_RGkwVvm?IUm&gB%@n
zGZUm?o8Ql=Hn!&$j=w+AV!<?wyy0YJ$<4vf%w93J2w{nZY1oWg5WoosUD2>G@&ezt
ztc{@oof;Dy4z|G?QXJw!O4laG>0}IB$W*<sVaD7{0-4t)#S<es&f!Wf?-63%m_^f8
z?RMtEBQ|<V7%Xd(ycb4uMICY^2WmxsXWuVdYaGlCa*;lERKz`HkH#Hc-@Tswd8Ob9
zhBCvPANP2FYHx=%1rLUFX{S4{{}Y)leo3Aue20^u3>i;VmK^SY|B6FSS6Q7A+yM~L
zcwwly(V#KzzrVTKVxTr#)xa1bNegD!A;f0reb+-m&31;kYm&A)haRM|*go7Jl~ki7
zP{(p5X$M^i*DES02-JI-Tl_XxRc1ikPo=xBga=oN9iWjsS$l60toS7T110GmErOL|
zyaP0fCu^U6;8S$~hqvJ<sbsQb-OE20bl{JR_U)gGI}pp8vg^7GBd^j7={KQ@>zN!;
zcI653Ci=dK+BY-S!7|e?+wj1|E~U(fz{!d~jxWQ}GE0U2D6%Y$Ft*`9s_ZJW?Clg#
z>30>L+XFBP{ZM6vmqE^}%i;a|xbMEg`U!fO!ukpzs2rHFH<L;0s`?E*kL}oCs3mU!
zA{8b5h3%l0-~l5|*Aw&ecM;ytu)tCKs8wxb(&a-w3Sl;2s2egHvRE3{EJnN{<_#kk
zEtX-ZT0t@xn$~x*b#DbDtaRvAIGWar*wuKN)+nBzbB12K7J^Y%0(PjH)^Kqvf>F})
zmgt(sfl5Pjgh<($A*dP+6%ytNkg_mBQPTGRTtj811tO&EEYLKK7zfjWQP#o&MRSBy
ztSpc;jEJBy{~?;@2#FNt$eYJSk>x{CVQ@6Ryq;fME|>Pl0`R*v2D3(BG-`<HM+?PY
z_b|;Ns(K|!NaCD|4>hBf6QPi}m37<-#L{G6iNT|adobDC;eAwoM=G`{;*zOewWJ=h
zFX6rDP!8Nl3Iwx6g9|B580AEd861Fg=$LZl#?_Hdu6}W+JllEYHW7WEN~g}M=x`;?
zUOzEuaPgiHNTKVH>d+>gDje&>BH`fyBSGp)c>(J1Dq%+<dySmOrXhP3<om9UIfQ`r
z+yq1ZdRwi}C&Eg)4mWZtO0h0rxIXJ|GwA4Qr#)J^LcKalv7T+qz!_HR_NqF-k8n!w
zs`&LDvvR{82PPVDbh$^M02HJgnBbucLanA%6laUj175+<c^Rzg3y$^tB{c|E$26M4
z*1`rC+2!AO@%sERuYIgX>hmT0PFi4N=M@&7_$jPY&H19`5)X;+#!h=*?0sY3BYHn#
z$zvat28^bTCals_#|sbih>c$5Ggb9h;mVpwI3eCMYx*y&nq@;|;&20ux0peD-)sG0
z=C}(>2Dh4Gq6IprCL^%)?+l(iCWkV$Y^J-d5*D)QbKRwyCepyU>*@ie2K|M2<~11U
zDdcFIq|haV(j#3BfWhX&4!2;72{Z*knbA@_B^nGMa}fzsY0i?Yo1lnA52dU$Ec@0M
zgMCfI>&w?o4Xo8=8|g&Z)IST<fb;jzP)+lwTnvj3WwjL<AxZ-Y8q9vd9TQb5_`hXx
zy~NV9yb(y0O$}iim(v+QNJ-0-O&uk#GO`s(l9UihPwH6xR3k*uv$7GflA82^L^!0^
znK;^H^2-zHIsQ&E!jqEC_7F+S_J$);I+?&T{)`cvibDFQD0?BTxESe1$5uqE7B<kD
ze2SU5fby?oA*9NL(+z~mzqzO&+K3qY*vMe~oJPrrW)>IbI{)6C$M@>-x^u`3z{#&f
z+#cxB^{)zkKUEX2c}`S|_a;Kxw~ho(x@?N_>No-YyU_<DA<7*^c>w1Ei~)B(1!7cR
zkE1_mW*+DseRk*`kEI`fXiXCSZvM%&DO)^AS5GR|gU4f_O7fe+V9|jfZ$*}?2PY2*
z5AH>}5ADGQ9<RbYjl#qT9MAs=2)xs(6_2dQ9G5^CHaX#UK{VL3>R0~R)0E>$xw~jc
z#V5=KRv!{n5kz7Ww;hMMcrQ{ng-8b(WLgIXd&o=ARXqWlpgpg>YFYiZ=4Sl12h@wg
zna@2zx*puXH|?9+F4gFj&8uQ&Spb%3O^%hU5oE5W*`EnktCQ*W#zN037vPnP-jd&Y
zQ5eGg%qAhf?jUFRRxAS-<;)urXvI)~r(SUT9hmXwp(@?l6&?%R*c-Xqg&iHihLVcD
z;g+zrZpH`wjR64v9Sj2i?1KOR7+G5xIXhbae@b&2T5kKS@V+N%<=icBcO=t^m$+d(
zOXw?Po2gQ*9`^{X_?FSXCmlOK-ebK1vB%&OZG=4Ujjf1dj<I5TXVDHG;zHuCA>l0g
zX{$O5RS*npcNJLss%1xOlA_K}JV)x)#Zi^=peGo2ff%~+(^OXboIw9poyIcSRb{xb
z4JpZPO`WgKPnT=f;UA<WAuU0@07Y37FYr-vR_0ipuBs9f$~MNr)7(OJ03xL`2J^&0
z)f?g|utxFlOTEJ6WE=a+wJh$S)RdZ^M1I{Z{&_8fE7R(Mu|IkrPFa+v7mDhS@<t^5
z&D{YZ<vHj)is<A|0U@`?N_x<{*y_1b&(QkLGiEEvJ`P_+Qt=&f)39&Es%A|(o^3A_
zbLH62^Gu|;YK6wqQ)+Qi7MiJUoF~TKL#FE!`WcUIxst3CY%t!ghQ=M3TaCh1Ob{Z<
zN?}!MHE%8HNLRB*nT+AIAMXec&9Vw!zsz#IKrHR~yc(gB>YuPH&jb2V7ww7j&;-v`
zW3|zoty*N|W(zB@W%E&CRU^=KH+ky>pc@}3RDYrQH)zGWd4_i8x8?>WjtG=)<7ZKT
z3CqTi=tDm9QY_G4)!VSrexkoiBsAUmU+4YnVx6wor+I2GPJ<9*fzIRDT~!D=)&qH9
z0dn+I`7?tb9QjJtUi5ta38$FQvIhEk#rv1$Di*RJUPiGoSbxA+VritPZSj7`3dL)#
z6BkUKDOZvOCeQdJPF4hV-l5b81rlT{57P)_d&h~BhldFgg8YU;IAwPiFAb~?17bq+
z9!AvOj3<P<p&8YY?zVDry_~7dq^6h*s=OcYMP1Z)eLGHJ>cvps;K-LoHn`wJvMs=z
zirvk9@k+YJTbVm+%SN9#wJEIkgfTO3xtd3>cYdGtGh$lkO+(q?#lMQUk`_$`_HQLX
zMz4+Dk2Mt|4tE{H&C<(WnFE@BN8R~bXApFGop0n)v(4`N=(EB8EAqn_HT$vF^V6=!
z2;`}Ktv7=w5LoU7x~rJHGns~{!B+-09Zg{m{#XUi+_o`Od6gmj=r{(M2KW}2@ZJa`
z7(aJWMS;<X05qnCUpcTdA<l!<m}nS^@t5q;6y5Kl?nE?ebwl$Q(wqiwrPTe;@HXL+
zgn*&=nLmN_2yF=jO7d~#j8DLSXNufmosi@1jV**?-jfO@W=1F`ZHnIdEedq=`Rpl>
zqs=B&Dl7VY!1ogV&Tok{Rav^G$ebnd_u9JxVj;TAzI_8wEvzgm@Ca&;fz}51O1@Sl
z_v@mmV(U#RY*<STB><RC7*1wNPy*$0y(9xZ9KpW6ovvOT=G#F}`1e(i*&aP8I3}TU
z98x=>?vx>vO$i`loLn32;v?Q5cZUTgVfQ%Qa)I|b-EN%dvriupZ_35JEo!hkwWWo^
zun<sqbUhYvm{72hVOxM9*hkQwSYuIYtYOV;2j?Cc74Xwt)&V&Sk689tmanDC5ldw7
zW^dHcIT|o;@v*&Xo0R|AmCUZRKRZy76P-Jao}NkJz;%uPXgeT!MS%PRoY6Z?&Ow!u
z*r|-Tw%d&2mpjF%kejr)kZnD&?3b1-K3=$OzKkE<XP!(l@w@VggJbVbZ{(sT;ob}%
zS!)Ism`JowZ1~x@n+a-cME+N4WWn*b>I&62K<RkIy}{PMGmC$Z+yDSj-~a+R=s9^f
z{qH}3mpxuiMdPV-Z{J_YoIFSje?_G`NdDA1<}7x};qxQvbVJ4KTt^^bBnR7+noQJ)
zsdyac-uSLgf<VHH3xZJ;G@BK!2NJ7&Ir2CiU9^3F9(ZiN98VvAIp5FfX`)T*VQw3<
z<Gdz~`F%0kci!0gzV7sWAFz2a{>|-+<(cxzm_dz+c)$F7Nb8&UaQTutpz~wY{0vun
z+V#zO9rF9S|I^#%_xgz!v-369<rZ`8{Cr6}m>9D%7NvUd8D@I$eMXBmm4Viq&X&8i
zI%?0U(f(Du7c2S&l-qd_%IA^K(q9+#-FA1aqi)yrr?=Cbg-(;^<*(o1HyfYmHkACb
z`z6d>)97Qt9XAfm*mn1xtf;v0;P&qzI^9hSer@+AfJ%CM=!GPgKZw{Pa}k6D*`sz*
zt7tcWzn%L!(2U&f-3z2qw~N@`uhibKe|bBNN!|Qi345M?pQ>_wIBwJXgXGP2Z~Db%
z_xK*fmFv~_iTO3GwmlrOjr-Y~PO~TT5~X@N>+^!(i~I#`{<=qYY3B`PJ%CHpEWrTr
zBlZHX_tV*%xeN}d^~N37z|p5O#pl3!k&E_RJ`RGHy00OeET%G#^vnZqA@#Ok=`xjL
zXZS$(XLA<7y{sv9-AWF=UY<^Q=_T9Hb{^1Lv&(9vexeqbT!y*n=*O}65YWM|41I}k
zrWQG$D3(CR$@PZH4P=qHL2$`jz`M~TyN-7$V)HcAS;*n};>DH=^Fy%LD-wgFe@9}(
z{%-jKi|X!qAQnPG=1HU4D+bq?lG_MNwVskCd8c2$H+m`{)=0yD!DLWD>8yQ6I=wY#
z?joK;IW*xWWx6Q{uB|G3Jeu28^tvsZ+bQ&vcYPafFfoi|od-!!*8_q?hS5nA!CY9?
z%IX<G()i7D&zPNL<|b~+2f-A3v8UC6qa`9SU2s8mxsx}Dh+W~AlebMz9lO<_g1pIw
z9!m6lBWHmQb*}fm{RL_0{qjB+Pq{6ig4~ELsm;&#i9G49&KJ{d_ceFXIs5g(Viwsx
zZ+V|U%uUVraVpcD(RHhQGmq1|{^bPnwR+}!*^vaZWWW>!h@-y|zyTN}^9_Q&c?TqB
z_CWS+fG}g$U^Wj~6Ngr#he>z6PjLrG5}_oW$c8ubQO91f<WK7z{DzSc6*@XzlL;VV
zy3L0wr)zZl+4Fe(%Wf&%D+<(`#g1FrOkQYC(2r5CJ&9mRz^s%NV@{1&B2?U1pDR?<
zSmhMmIy8*cx(q**8xmij<IY*IyW!o1(<$RZ<IV!BsMX#w%i9#vJX))ZKP&VKUPCdv
zjo&w825lJY^%pH5RVUF!B6Z1c(W@A@p|x&|?a*_a@N3xweDvaNYP@1A-}!W(fm9JA
zfaoS`jSzoUJZ9X4jMPHNl~01~eT3LTA@!g|$m4zj9jPzwco&8;#g?pFKHGtoZLnA|
z?NE$b{kdp;MprxTP6La;Ng~SMQCxpbWx3IFAHt6x_~lcsd14Q{;9V~`4DKK#n3<JU
zY|!Iz4L|2*Zo?;0LBk8*_WWxXu+ItXPW{(ZJv;MPAQj-nl<^Qn7S%jIGx-%_y3UC@
zK&@yP1Qx+6i_$9<!8Mc~Gl80Jki{;M4pdtqh6O4OHg@$b!+uTU9q2w4OmxmEm>`O%
zV`bU;DM~w1VY2WmN<9nnAK@9^hL=-KDT?*;&!Vdv!T`8{=oD%cVG2~t+pn<FXvCi<
z3nxT#<<P4ygBwj*vZZH73&XVPB+U`P)`|9;-?M~I-AIs?X*y)Ql~Jq)5wx&}{5-x=
zJT*k%5P4eZ8eVG^cItBl?^BLbn6*yurcNh(k9J~{0Nj_q4bOG^>l|kO2cDzxF-H_{
zQYLC=!PmKv=d+giuY&{cJ6>m4&Ig3Ek2t9?aj&urJ@lHo^DaTp%1qySS0m-pU)SOk
z2LXfn65wD{-u|kvZ4gYVfhTj-J3H3KoUvkG<-}IJ$Xqm8QqHg(tN8!<L<Z=(Lh^Ru
zcrTz&p{D_Q@=sBC`r2If*Aeb?l^kj{IuDqKE$84BI(*`3;6nSzb1GW^I;${q@11~e
z@@)KUF2Iiss{X1Kx9bL++@`x|i+cjVed*^YEa{;~yA@je#TjrgpN{!()*AcR>Q%M<
z>n@<K8fyA#Kb;Pr{&w7mKxl#=KL-rqx4$E%;1}Q#vwt>lrGfE)|1y1}e!nHU2E9H@
zG_}6;0zxt7IXbYa5DwQ8v14pSZgyn>MRgeti1HJ*?y|i#X!-Uk@h~Vk-Z}75DX%>5
z3J6p#G9_fJJRcQ2ArlyfTB9<U_BF73Re<y-2z8YdDuusN8g(8%=VXm{zr=(JJdZvK
z?vOH{{^jqN%>BwO{kDw>FKagxcazG>>Q(yR0FcIH4l8h({BmVgS)Lg>6{&&Y1P0d!
zg;hY(@XOg^&#IsrUrn4<ftNFi*_g2MYY96pkf#`#ozboK+Jtz;vfNVGx@|>|V5P)M
z3VEG5n;4k34Rc#cPrs++&0C4GSVF+gO*WV9H&KE^TA)34Jkg9$=(i)mbno;bJ?m(x
z2JI3|6m94wO6BX6h!EssV2?D0Dh6uk^0}T6SwWPE41S$>owp?LW+zvnQ6l#&AJMT-
zI#L&btx6GAL*$8n<>!bg18dED(W@^Z%OG$?7OR5<MVtd`?JP?&mq>L=;<$c6wgp<A
zrmGUPT0^03yIby@^v%eh-0zq75=u12q7J!&Y)x<&QFDGH@=Z3(+p_NNS&HZqG15l#
zwoiIGWIPq-JQb!q75-5_8p5nDXh3?!TCEzaLbkJ1F<9VzBFPGr@DnM6WU3kl<;kG?
zL(le_xuq$ZMop}VR}Cxao1cl<b6C9>i$-_A@JZZ0+7+OdQS(M(XpA+zYvEkva^N|=
zs$xnmLF0Sl5u{_%`$nDlCgq#at)4$$D2Ifm$yQ%+@izEp(%8hBlE<TlTb%TRZrg$a
zy|9W*ai;+kVnXeYC{QQCmyIBGkr!|iF~+tDCA4ke`aP|Z&8|-AaetR7WmKV|;OvmL
z&j_jd!Q4LDl?Z5U&xEyzn=!hClyIUQiUO&QfYQ?YsGrqfnrPLlpHcKsL}~JKOB*D0
zDD1`(jTF4S*+{Az)@QTk-*{W3mDi4?zXQivG&c(vnAS~`r5I8)HWh?8a>g~vmVIRz
zamS==`(aGrlDJ%3?en_x#z^>95tIvFV0kFVyfRW9peeIm+mo+pxIz-0jl0m)9O*-e
z`AB;v?iEJsT`jf+A;7-mvO*W%XuXKwsN@O7;g6XD$X5iP#Pw0l+}*DJ6lmpx4eQdS
zW9N@tykcer+mftrj1ZT``hJDnn%%otZ>C)Y(3QzgzJ-FfIt4AI>gxpQhf%64QKm0}
z6NMy9eogaUH0vUB4NFz|P+}Vmj+FCZzYoPYYnQd3u$>&2_7J4vk%JKGX%O@;)Zy40
zc4e4`XQNH{15?9zFBGJZt3dq9TJgHjP~tu%@k?W8V}T$d+YIs8g5qdIkgC1B18uI*
zVf+R!`GcopRKwYj*ZOnkzWU?!ZbEE?{B;Ig5wT-8<tK}ul=^8e;clTX_N#@;mqbE+
zr71<XjgB`|Usx$I$J1G@1kS~#tK&2Unkty*vLck8<bz=0xKnK==NNeO@n1S8tTaoe
zVUA=DY?T!nVgU7kUcZ!Dq46uA{wg#?%3FrrOMIuf|5<--?6_OF4x?q1jD99Y@rdSv
zRB=Qf;rttb7yu{;hu*-GJhedMu6atx{7X~tLLQFD2gf4=`#a1Bg(hh*;4hVi@xi6}
zUGg*AmsTDv<{;ZDUQypmpEN~9IXDh7!VG^Z!6u3c4)o553)3Iv_zrb3QC+}av~@;w
z1D^qt;jsoS4ge^0+tN$Tw3|S77+&z@&E<XsodSe=PQh*g&q8FaNpPAI-~sJmD~$9(
z3BJXn_@+?&{<XHXeA;Bw$ED~~TeK0C;4d+N=9XCRjQp9JApBuDX&R-FCYcF>2pdQa
zp5aJ_ztflMIs4Kp2?c|SfF}6CL<bax<^Cf4>h_(J<b`l2^a}tBO$!uTE1*a<QLnBX
z4wCsLjD_&%)NS2gF)q@b%;JpPq{z>z8spU}Ud5WNzHl>g#of+EukV(sABY=|D=H9r
z<(xuCl~alaXlCyCJKIe2UfK!=j{kH#kQHhYNoEdwH*xh7)fqLKT~#yHdtu#u!CG5P
z7`$9q7<V}2S!D^R#&FB^fYU$-R6)*R@`6rtg3dK2#88hdNpBIMSO1A0;w_K_^Vmm~
zeyEvoa>-?_n16}3{B%T1?P@CP`6w)F>hE+`-0D@7*>^yw=Rp3hk~+^U0%t6~c`A!p
zG%x+P2{+EyQ4Ho3#|JQ9*ws^B%~Rg=a^CgtEU&2LS^Vt5JZ`smLnNR4iB!Vl3w)8d
zk`hfA_jv5j5V(zo0X*(0<mKBaV^xS;(?3G)DG9F{36jtzs<TOVX1DCPBehw{!mSL&
z8V6hEK1<7FxXp=hnU?~t%_4eb9D6Q)c8moX#)5<Nqj}A&xy(c?HvLi$6$!CgNXHr|
z&DR8}f)}Bga7Ihlef|qgd_WHZ-=(eocDIuPyD2C$-?_ACbW<Y0o5<Y8IQKhW#-9*g
z_|N*s9YqOU_G)>$t!EE6On!SKQN7$9`l4k>bOK<M0Fn>&^zXRPF5SrK7sElO`+y`9
z>w}h1nSnCVZNoD72bm?T?M_pssrSKcz$l@=u3WfTCo3uk(^Q+Ro`aL}tv*=&a^91|
zC<?A3_g=16*SdV(137sE4T?ZTIn!wiatV8kmMq=?A20p5A15&fOw+2PI-ACJDr88$
zKspZxa6B*eUmW9Lu|0M^3RYe6KJTn-83OII!?rz(pm{uz?2c)<m%W_B>RP|CufpmU
z&(@sCvTlb)bG>D~M&1Er1qppEK91x>zduaEaU=O>Kc1uxve>fT7bp1qEPT2l+@e3?
z+-@*ul2*}W$&l>Y{a0hsD3%!Q-1&4%(Wm`<Y}#W^&dfQUF~5v^?aBBb3^=W*bG!Zc
zvrxb6Ib6*Q5>%*8&|n;j6x|pHZ$AF;tsG(Qs``UO?-JBoO5@e@YuemwH;|HHoPGND
zkzKogP#Ubtp*Kp4nmRgCQMKJUR*{=cI%el()$5|dJ>O1vxfTSuxFZI&h{!Fbrr3ko
zEWTaBS>^jJ#BlZKJ7;OS)3-x+IU;&c!=thgqwc;jXZYqB+t(yT*oxQzV|zJi251LN
z^`}7Kw2r`*fr@5{&kO6M@wK7pmk(tQ<yBLa4(P?~)YI)6y(E93<lmY74*ssyUxM>j
zg;Ni>`7*zI<bu9g!@JyrKJ-@+`G#7@j1NQ&wzb4l6Fn^_ayEYy>%qz7%99J@6+aLc
zmOXBX$7&#`BQ^Qr#NeGSO*(U=jl=EnfIhW<^WKXssP|&X>xC|O@4f>y`3ed7{-XLM
z2JI#O)k>oU+t)sO9q0E~Y(s41N?r)lTRWNphLWp4y*GNynAf$hMid0!=-`alTNMcj
zigeL0o7*c1{a5!%-M0B*%<&E#z*Nw8JIDmcB-)quLvC4<T7;!xw1mb`w;mGlebQ1{
z(#9FOZw!wYLrzEB7@>6_jYht2H|TX}lHngQ1MK8=o9>KV9f(IhD+YQ6s4o?9<uuc^
z8yEERDC{_^K;E<I(y26czn2Ps#(mM;{53jT$!a*Gg|evF?{fbdk4ICAInA5bhzO>9
z7}77pxOk#?O$^ZHrtE37$1db?w@{KlAMEuoO9waC7uke!n|P0XEE35d)O+`sWHA0a
z;YlC_pmpYbfvFkWzkPkaIB{+ar0v*486OO)8KJbZ?{4EKd$vSVjBt$MPiB;zPHvf}
zssoMwqSaAhWb2Vfu;&|=&qrb+SxR#)9vL6bc-z@ZBMx;=LVGIS!2qu9lR2fr3moK|
z4zOSFbnJYbRg+#Lj@ldfozexjiMWe^*MU0TSa9NU_!^ELvJ<!mke8=`V7wnIP-L$P
ze|&I+r*LDu+Uk&=e|WfE&g5AJk!E66z?4rPO3CEMd`A5BIquEg6h}6H%iY5Jdbt1d
z*e@-OOEZhZ!Q{s1W|7TKH&G2v7YBU}i?*{2nZqaG4F9*_J(EVyzP&TMeEZPht{J=)
zb*%Ckakgk>*ngK%Zdu1YY0s(!m=whE<n5Oip!wuNk&z?lfHGffjz=8tF-S5bG{(UG
zpRWUuOcksvgVX4veFsf0XD7P`?}}asT5sfTZw_d)PZ=onI~VrRW$;bH(QqJK&m@ts
z(ql`)_?@1+^kXA#OB}Q99jQ82Bn)Sw(KBs_J$cK6Xf^XnJE&Q!xEDOw#b*XK=a+pV
zH|5QBqG~FWvw2dDN^+5T7|M+(d-^gzh%;BHGZhyv1h~KVCh}~jrd`zcX%>&GEY~|%
zTAKAJewM(5EV%W@)@#z%d>OQ6LvPfqQ@QDB=5Tn;&;fW4O*{K94sVGs&(AD(+IxRC
zC*rRN8~@VX0-SY&o_B*r5;;^WVW)Ovg!=UQ(8)aH$LEjtFk4UY0^V?HzE#OE56JDy
zi1G!f)n@Sd9&qye2ISZns#p^;;f2A<ZV9%H<_l!vw6cZfY&){XnjMVu)i*hOa6}U|
zNra5VcxjF8_?jF8e;fN5oY~{t8ZzX>qxrr4;)Q-jScqUkv?lw>Dy~R)Jsi;F8Ysza
znhXA0ZNOD;8pS4d!_KUa3Qc7;F~9u^5T#AO2PFD+-s4|)yi{+SzA^Vq(l%vtnTo{X
z#-63?e5)+3f=b<8Dw^u)-s&vZfb%EvmXM?`Z<8V|EZ0<A@-HqVSXoD^lp?Y;w_8W{
z<Qap{qx|sn8y~7dp8)nBS8=gX;L#i8LnR4u>Lb;ah#K=t{Vm6Gd4wS<Le{EP7#&)F
zpj^-n4G&4*Yk45|>*_+gL~|5nHgXXTpSTpRR7KgN$fpkN-o~QXDfsDmLtln$-k=fD
zoi+`Q^p8J%L6Cl{o$gFIVw=QW68i|1epbsb)=kGil%?0^z5-o<SZ~)=T(1{6PaU9G
zJrFFM>V+&R{a1GM;~6sx96dGH$y=U;!{+FI`yJSY?}i?6B)H|NjoB@?T7v*c!31AJ
zRQ`eeRd4>G*HeZZ4~NT+`IXr&Z49VTLp#|gEsaY+e(v16;lMG|;A4u`n7|I?7JKfn
z-Ucls(|Mmcc?^}_R8`vdA#aIV)@sP}>`(ejA7<XTzyq6psim=DU5sQyWn6e1@-_%U
z!p;k=3*H3+^38X5DGn422yD>e)plzuf0wzb(`RswdGXT=@#U_w{WH9ZA{mHFo}_W<
z7mo^g^*<(b)f1!C+=Cc_CP0&9dkbaAcB1Idv+;ikUVHiv(5Gakcf0YAE#Phr1fti4
zmX~{^f9kkQa6P8KB~#Gp?#E=}aKp`yyw<-yNJ`lj<dDt0=CRK<2)}!;akKTe*2Qg^
zH2{N$P3OU-&6*%susv9^&VWzm>0sB<#<t#Eflnq$6o^e4xqzcjdt7*DdOrrccmilo
zcAVb{-)+b_?l@Tb%pX2;HuRbocF9%k2sjKK;CvQ)>hwz$a^NE6z*WK(=-eU6n&H1s
z#BTHCDd~-jzsGFQ&X~>P!A!nVzddL?s-V-A>~rOb`0+;dYM$8S%od)gfBXm@VvoI1
zeNys&h`M!)tCObFHvNAxYh}J0jYsY&&6%dts8B_6tsku#%GQ4e(}q0!0r$wY_T)bS
zuT0P<CQ=`8VHWS(uBe~0&aCgXAxeACfQ`B^F1)VwU}X<EaX8!?r;F>SY`9#fau8hP
z^nD3m>MIRFLjE5qHNS`f*dHzj&Wv9U`{K<w)#kQ6p$!@(*YU4s2$7YS+leA&FTFMr
zSPCaH4YrWx=WsOK!l@}@6&5f8qMJ=2F?j&!@GX#p)NUly6pj*ONukfkJy+L=@22QL
z=i<QvC8dWXIh1R|kuE%eL-gBRPCKB_$oe6H$H@JY3l9uZ4AM%Rj_erya*~3((L}I7
z7>o552s}HlAUesBL@2MYdCEh@9o78hL*<p%5`<SmVkyhyX@FJ|4u=v!BgBC{lh1NW
z*co$~GX-UVP!SdCBTr?xqo6wDawHAYj~?@CJ|NZo4I(p0A4JL-ND>^{_us1s`SHc%
zN1<%_octya19C^8YK4fDqm)y`B_rGTA7u5A1slmO7;{C0fYy%!v=q*#^d^e}#e!Y0
z10pF;Mc%u~F<z%!X?<9`Kpi2kSXo>)WG`%b=rS=eRdwbh9~9}|bU+%ouL&~VXQv$M
zbBuwA&cX2p*)e+&sC)lJst`#PL<7E(PS-oNCTwbB@#Xrekv>xmXU|$&Ku2$&$!p`j
zM%k<AtH36%sqaNl0FwO`poYwwfWiKauyy4^sVTkpV&(Tf4iL%3V|o@VgYMFM6<v+g
z6re);3I~TZsLX=`2S-MUx^!$>Qxu7z=}A8tKvK&Z1Rn(#@*Tz5K-*5Y<uhXuzj~G)
zMRp@*n@mwPBq>k1s7U(geZm+g$P1QCKUORbnxp4x$xrRy{Q13pz&-QgAB{ybNI_`9
z@heT4w8WatX#wnbGd~Dlt)Cw`DL7z0tEhxM=7{QdG%$7jzB!8hA~H}Wv9zA$rBh~;
zzFW`$GHZ@8lWyR=L<^4+I%l%~<?tOa4_6V2mQ@qY%5ee*vS8N&e5#XNo-FarfKDu$
zIjAJ7#h87`(Am^QL;-RsNk86u1Sx;Nq?`Qb3Cam<?cv~g6%RKKY|#8>`TAD~t^mCB
z=?ZW{m$q~Y(5O?FV>1~SpkF>!9=LTRy$67=2l%g_0>{6<03f)Y{Qqy=BgkvO=`Q--
zW2U)^SfkMfiPLS~oCV|zmCTxiGib-0^;8fjD?HSclCo!i?rchRPPs7sCBj#Z*G-0;
zda_dTw1uLWC_FDb|00x#9cpHdk~JrOM6sE+d>A*KJq}JqymjJ><fnkic^fNRCum@i
zpCMe&QV4~!pkSZ7Ss!k(If3d;U<Hf<)i9ykXxjx?4EnUKY909Ss-w}5g>>bjpfn#*
zA^4t;>Aj}ptWk<o)0&@A84V{hFN)|2?&};P=ScNp$MteU@=13E9?FppXz1@y0!pKQ
z;1l+e1|&lmTS$PCJ+5*l1U?UIeb`%BOIs7%HpnA?lSz8zrQ&Lw4=jUfg4HiE%m^mW
zz)-MEY7b&jLv|yKFE<=uvd5XkHL%cNc*!mT?zjf40Gj=xte8)6>!4RpJWqdfmd9$b
z1@GB%#P4#six3}MAI&oW+!#)wKIeMsUrV|6sgkivbru&OLnb-2!4SY@KsPSm&z!Gd
z5P|?p`Br1iaoc9D9xXG0s0@`T6WI+{P7GD9*%%UAP}7Obr~jmgDj*U&pQLa+v;aH?
z@VtAJI6(ahaH<gtKz^OXVx*z(PzZ@5U}D289md|cW(G#D0FnMjMHtlG#4qvY=LUyO
zVD}s$Hlwj`IlVcvgqf5Be#X*NSaS&DW8$X|P$`_lOObY7ZepyE8SdKzuh1ZEu|qVF
z5r;?lVCWB(RT^?lEL?ITb%deJ2hODo7)IYZ0YiKP_J~GsFp{?mW0n0Kl%yUKRe4LU
z#wLbzM_IzPOD0Y~gcAc`Xv-Jhfi6jvO#pKXfZD$@TWGT(QK$pSnNMNOooroL%piGX
zA~fIA((jlAnGWnLR77H>pe~$@3`Jd07*=mEZCq=W6g*o3(|a!eMWQOiqekrjfEdnM
zIWZI33sNhl<f)qdI$$MoieXO2`inlWvD8^W1o|l{5gGJPWB)#Xlrh86P`~3gR4So=
z!enJ1)u}&LI%QBj(46r5Tz9Fty1uH({F-+IqV^K66c|y1f<>YHevJSZYIG9NTgJL6
z1l2fN1KlYP$Ll1ja3L(VwgB=rB6K$bp9qYKyt984B*-Nu&sOq0VkE6*BbY1hI<mNR
zBl03MGcnZK12e1GBtGr(X-SHWZSs{=MM`5JkBY-E?>ZiteGNlq!H`0t=PDXxt+yoR
zV($X*j^SiE`KS*5J1l0KFo#eI#8IWa6*;1gFR6SKB03q?hi>ALk2}QCDP>i0sZ!9u
zctjv2q52S1uM%gZO|f5TI3g2oBnB@aQxZ9nNp5^{^QqRmE_lkQKdAzkAP!bX?9qzC
ztSG_%L)$qAclLE_KDO<oV_O}kW820zwr$(CZQFJ_wrzLP$>jIGQ}^DQx;0ZZHB+@~
zpS^dTzt7ogJ?rx<XeU9<pG;0USdw$G0z-lwpVEnu>g~Wa@St*re)#p*;cW6pP3P)N
zjfhuBsKHh;b@C?xP>l1~zKq4ut$rC!xSZ>RPAIhklKvn@=9j@GK%Fv^e)8k&zsAf;
zvHp@i-ICysfYrZRDVdN|q|GmxW%s9YEej0AvD~SK+Ts4-dfCJ2Y+j7)zHnL0sbK93
zd3GIWMZ(IX7*+Yn+OxPWa|*A}ObjlN+fl}Jw>`qKd*5%2Gz4$W4uMhTX9nkVh>Wpy
z3G{KkEX^#z;e=Z^Cdg_8WO~g)*I^^SWO_l-Pxn*O<Hv+MR1_VP#q*lwARGvU-|nuj
zhBVxKtgvMx3ve1pMr@yz7%PP?zcq##eniE#N<zun5MrUf?S69+3vhvthkj^Lxn$L}
z6XU124_=C<I}r{W#ZJh)z`l{TmCXdP2f2e~*<7#$GOG%-jvU7uS+gy^NU0Dwy78t#
zz0xbTH)24wnRy7vzSxH-rk(e@sB#rzQ;bzGGIkO?J}ZJP%9VOA+@|p=;<!FDrEg}G
zEI*>3JLn@O5lPBwtc!bA3Rzl2l6eemeP-Fu`ylE}QdfxXZOuSBI~ja*$exy{f_UN;
zznI}Ge{^7UrgsVE2s+m@$zOP2<hsOg+Fv%<*`%g{YBBmYU2|!RlB^@_{X$Becnq?H
zm4^5AMpOlfe2P$#RbFW47{cd2M$cfwysw|=?9pkO$T%%c&?40i!Yn8S?hs!XWjHbX
zV+QoOY1m=I^gFpAz}j3hC9&$*u^f$mUgx2eXe{hhS#Pda4NDn|>gp?k<A<cP6U~D$
z#h4TtL0rjlzd@;Yx%P=9VpfeR&22^$P=OO3a8kWOjXo>0G>Q_mMtD(Z4B*%Ny2g?~
z_3Zr7+zMmHyX1s77nI-%d3=9OkT!p1So7m^922LzIdM<x@yNui)JY~nJ=rtBEp{Ch
zi`**}JF*cDXLpDP>J~K#T84y~bqq%#vPE(>ZDjp-75w%&8#|FWBUKA;-yQBLEsh?V
zK@x5hZ@>^D9oPbp9I1#&FGwqd5a5}6Q=nfIaH&D77bHPTo%~}-<%8h8WXC@rQ4*Uo
zXBS#hAuZxp?*ze@y_iw>++H4oF~f2}3%%8N+5u2l0di79fB1a2G?QjaNswN7h~G%s
z)ttUPrwrVjF`~Fg+K#d<8Jx@>Lp69l>PCTxua1t0Z;KIwQEiRZ)mUw8rCN1Jh{WU*
z&7(=BUI#EcMzbP}52J{H>LO&mBohS@3=zNpgW@&F!!s}h;&t$}fuEM8BJYo+93{W`
zl=NT6Hdwm&vaJuWB9`G|rF_$1e2FL|R``v6U?;Ix;ZFQ&r1)M^Qfw*n-7=S?2DnpH
znLrz;L;8E;>Y8{gqSZYUL@p#O6#0TVc<&K*sx~F4u3CeFgncEe!4aiH)GNxU0mg<B
z{q$xC1sCEsS`3q4P;}fNCO;M6`+GUF>Am0F^ZYuaC_?&S!n})6dH^w1xJo)vCWEhZ
zgUDbzwvn#O%IeBc41eSsaZCc4kW`r(5#)?D$vRwqA_M%=)|$vS<OLD!n~=VpS^5=k
z)?CNcPDR(m1k$c;-a&l8T#x2n-xKkm2i1O!R}|Pobd}1ErKqIv876}>i4*gTx*E)(
zMbNYHGP(>PUh!d}KU=an<|j7O8X&7Wo_2CaorHOkY0x#g!<G!V6rCzz<x&Z9fk7^C
zKKIq&pMqwRLly!=q`<-|a}z*xp|6Myk<sda@j;`gfp>@|DoJ-c+N>eUjjZ-dwrgN&
z61yo?lO*n5@z+B&_RNlWmrm#4kO3bl6Ymk_bz@QODNC?*GYv8MKqcpjoK4hW$l<G)
zX?Mg<Ubx=b`xvS>@+^a4R#Lb>w%1CrKqrH|@QJC&V?L0zX*82;A`_jV(>gL$l%3cF
zNBx3|sfvJwm!!7~!EKYn7)40vQ~F$*v<%@NiSDXDBuW(+nG19<dUSr8r~DN;h<kz|
zaimV%fOUe{!cU%49*Xf$*2l!C2iw8`goV&KtZ7YOiV*hd@rTq5h8Js9i0GIA)>xz$
z1{+C*23OJmXkisX%3T#9C3%L8T=8(a@|0YH`VEgTQLX8J`cf^#fxLuYONld@sM7RI
zY`ChVRrK><3G|Bz9?dx?8!D;F*l0sa2BpA74F`BxKJ*8Kd<9(DYWNHs^`))PyztaX
z))2H{YLMY{xoNEnxg-@p>xtWop~#SB1A~sTdJKmnL|9BY!8DrvV;Br=2f2F8sHI99
z#RF%^^yLF}({U&@=>apfj)bCBQR3@OJEGV)MqtN;re1x>FQ70GX+B&UkUR=ps={@B
zjAgq^`{t@s7VCTOb9Zx4!Mv~`U(AkIQ1Fns7x}URY@3$2GoePB;Sog7pxG@(g|T_6
z>=l72b^iD>++-up%G&idLpwe5KSV>uB$7|t=+f++|AYvO^~*Ej;X4y~<#j?elHlj0
zNPsoIh0-QLVdQ$i2Am+q-*{SI{uw)PSahQ8<Z!n~gy5*U8c&OYx6}^!>GqCKVMdV3
zM~_9~<VmsAmIWJ~5=qsanqeCEnZ?uIh)myB{cQM%o@e*YEO8ycY1glRtXqc)I>QNC
zK^@7L2ss5m>RWw%T%^Xb^3Hy6%hP>V8T3~t)spAmDd|EJ+iv|A<CAf8=qs;0Z54#1
z%GcrR6YhxiuEI7I#`XvN;m|Dw+O3O#k}y2ah^$n!2d}^pTm~vxD@T4kB`*&--<}fA
z_YA`r20yC(9K)EsYzFF@1^H7ig}b+ceVq282a(}WNC%$V8!r{6Q4qJDiZoYNNNtrY
zp5KAo(kGb_G-z&Fw$wHB9S<_Y=qyBUHq^(Q-`G%zVGe`Xl)DnssKMo1$^Ll(_l~kx
zPk9=RKhKV`HvEh8_gZPtPPb|3%Py_u#+U=WR3{+)reuHbmBChVw}7h3ihn@vb8-_`
zXgXLS_IH~aYFRmDgonJw+ltUZ$Gg{xkSWp5LcrDOA`ViyeJzHUw~m`Mc4S9Bx8?yb
z?8_>tXPaB>XT=Ngv1V;sTCZ$~T;rK>N7f|gMz<%W;7=dH71NLJl(+R$2JLE#)z6Q8
zzEC)HXza2!d>ke)Ld=7<fC&VRi%q_7+l^XhddLI!>WBX_95oNOj?=8ctDKLqw%w~8
zi&g*TtZ?P7aIK7z{d<v1F#LTEK+68taW2&Q_ijlQ^!pVx))!~p3$On&w3(23YMpB$
z8@ayckoWKT_%~w~CjA{h9=%Pq<GXNVwi-<kqJ_YZ$e1&nv;DCXb$gj=5rZT|jhify
zk1*IA#6i8wh?Br|`GEveZE-uk=JxaXwYT5Lj`DWrdArr6?3ibWh&zAh`EEYTMsb=R
zu45a!57%{jykEo&FdTQT2z&odRKb3Ze-11N61^P;Oyi)s9`^KM7QMmtz=BM^a{nQ>
zQMwzC>~xc?3~d3Ou0EU&W%;Uv45<YUd9%mU?EFqaHhGxge)&H$iVynpLPWv7TF6@8
zh5!(zjVBZ_<Jrz^dSP=43|%TZHQ1TVu492j*^s4EBeku}9AFC0y>2P8r<Z261U7G>
z4H;jgU0+i%Wjik0oT%D^!f1%@A13#gzyh;xYN|Zfj&T>vYX&8;I|*Qd%Au&GMjbJ^
zRgNOGTz08T|E~7e7RbZZLswO}Bl;50nk;G*4<beQ4cjwB+HG+K-Vs_XnEb7kQRgXG
z$Fsk(3{V=;>hi1DISM+Vefc>#P1oeOTtcjoS+OG{uEcwS=Nf~@!4KjlYo8kpD2_VX
zP}(f2bA(n~!q;d0D{&uJI6UQO4}ZPpMzG|T;s`Rj7piOrcT;(?z(c14uX{Hw(>6d&
zcBQ=}#KALVv;7uH;X9Bp$A+EjZa$vf-M~#2JqL5R7RaB;kakOz*z@&jJe9|reOMD+
zc>RkWX<I2QOb`ttW2-z|nUBI`v!WyTHaH_fzPs;Xh4L@chWLz{GvXi*V8)atg(har
zfxt|~I4>D51&{0ap5ky0wVz=Tqx3`_2eF81qF}^R5b(ZGf^k|`4UNr>s{2C0Cl(`3
zm=?@X0g94*y@6rNOx;0NPyJ#82{A5Wod89>k;x9x5S(wCd?m%L{-wIPU6j`Wx<Iga
zM9h7|q%#xp^z-B`>y6Wt&uz$I#!J~S%6-Nwi-qt*;^^mt{lAtcQ=_vvZ~AQ3GG2Z1
zrdr2Fo)Ej$<%py`bT9GzUvU&~{=ZuR{0M30JN$3{Loee#hc^L23xul~TW_%+*5kQA
z`E+Xuz-!wfttA4KPjo-yKs|_9pc^bh4ch!(0PPbZb1E{%`*J7NAT3qdQ@?_^q4!WF
z_uM=o6ETtIw{hL|Qe!dY7T*lBJHwo;u*d?}EIv*KyscgfM?#Oky1M>+X;vS9S?TDC
z(c0Wc6gmaO(<BQ|<Ij{};unh<>nMVGC)zcJ{h`x%6$X=NP(1&d?`XGZv0WEILYW3e
zrmdHA8m`+IvanvD36oq&;I~!v*)smp!VngT53By5vPH2#7u!{phonNw;0K`<xf7X}
zR#`UQLdF{wM{d$1*nHbh1qqV~Adxp9ag8{9<e+Ni{|@ufhI*vAUP|;ggi$Z$%)Q-|
zv<V@=R76r)g7zD9K(GsNx?LiQFvY0xr90i7m4M*iA}KQ|?b44+!+9*w4ShN)^k2e>
zA{wZ*0*us~aIYMqEV$~UwrN9l`>v%x>LE+a)njOr4Yl6`$hM$Uq)Crd<Bbh98{kC?
z@x*Bi*9Dx>l)7ih)q;kj6W$fsnKQ*5Oy@`n43ZB8mRYS#=cpubtcZQ>Y5l9vHRd}-
z&4<ubzAxi2!d9a=VM)6YPUgyAbJApz4QRh6?D51Cq{9(}e+GamI1N*6o&LC(MAUfn
z7mcE?e-AL;M3#c+PR>r~O8h~6sM>O=Y(PKons?{aFp8#T8{4`6GA(&MfWEbt=z1}T
zbk*MIC7+`=lG$XCq>eY=Q?&lcLdK0bN&v?r2L57_wY`#l@;O}dMzhXUgw$|He=5Vp
z$k>|~Xn23g+X!12NdlJ)+qjq5>*xRMkn&6CrSu`B08MQEo$2wkNm#YF#dh1cl(`Jx
zbp21wDp4Wkb*sI-@>!NIMh{4G+`_oP@n7{g$gU}v{QT3d;7c<m$c0%3f#(a(;52UC
zsn6_^wC!g4?IJ(%Gh|yeS(TvH<)~S9niBYL`GWNadv6|ZeL{z;+q#2BVHN2Th3n@`
z?rUVcR-J-0$zzu^({r%mU4O2d`lgH=a1XCwLXr3qRU$y-bq-3TgYC~2s7!`zNG%nz
z0rGewRR28E-(&7Bz~$EFS1lT^Tc+3sX|n85wZB<Vj4zM4&stp1UXxhFZoaWiCHGIA
zcDI~({rkFov0vbgP{xO|@o<91pNIUG0T!REfBDk7XnSM+z9n)r1X3kh;NvyI<85<B
zj#m7JU7MW3{o^Qy9osGDTID`FV0Suw;&6I*;g6z5FpE*LS{~lO#N&i^Bu7xfCdfAQ
z;}%m}t4#8b(}KG<@Qz(V;0a9VGn-Gn-I2yHSX|WBTA>)NAa^_)EnX`3ODG#O$H4p7
zSRi8mh}1`0H_U!`z1b&Mde4;JNsulDhYKb_y6o8FUcM|5rrf8Mu$|Bp4Tvs}yJN3v
z1cZ<hGhqj6zzM1#?MH+5Z?J8r(?orZ1$)E`T0CeIvayMj-SeJ|y0G@TPp6(Z#u!P0
zd~E|`N-zJw5i)==LHAqp{po7P4*IP0l!MIq0GI2>mUs4K;@;&GfM0quq~|j!Bl_&H
zlKVxH)A6U9+I9T!4~VHmm50q!6&Rzp0F1qcrzO2Quj7@)=-LQ~69mjp4k(c9bneG<
ze>0vO9||Xe<lSEf9jmQz3fo@5poVwjxSvN$0ONgl1O0veL~y@B;FX*esar(aF?AvB
z`c<v|S26U70`~0J$ZsV$y(Ec^j172M(CE~yxjy)J+u{?05*GEJ!itNfhsgxmlbmz@
zcR<4_mObIGpXL~Kj6}0+Ap7)~O8zq#+y}MCh9+NX?kQJTitJt*qA~jA)TXD@iTbtL
z^cn}eV7czI`e}56gCgSSt<yiqwH+CY-#G^JYRLPJ<*v>CY{A?ox$IlCp2MxoKYWvn
zBY_}+e38cll5Kz+b-pCx{^F%2QIMWd1?~*F6_GmUI&>K`5!HKDC4Q92YS)0U+MZ(w
zh&CUQ3UWx|OehzSFgmrvQS&}Z0J%HjC#iS#`gP?-o3Mx@3+GxazonmPH!cxjnl(3g
z+k8Qr+)p5~)N8UHUNXYGsA`%`JFD(eDnk0r8{txeKpDBmTO@jP`l#Zwc-qDz*c|nS
zG?`H&+hd?Iue!mb2A&3oY=6gZ?JYH(<NmCjHgc1)SgmZH&;kD5ygr_$d<L-9AHp~J
zuDayR3cI=a92j-XptrVFDEB!Sz{4<Vi|5|xl7)adz&XS?2QFe1`ve+0=Eny61-K*x
zLFg%_DPacLStNlSvVCQJ3PsnM_oJlW0DD=yBJi`rCjSxeqW1n{mnF8Z$c$Y_8GC5#
z>o^u+{(d~EuT}eeWHN#0J<<7oZrgNEk>-o>uR69cP~!}tDh?dnYs#nLhl(EGB$Dd;
z_BGrSdat<XTU^%(#yBy6nhAXXGUo>n&GqKWmY3PxWLWANnkxY{ioQlJgI@c1KoS4u
zl}rZ`!~Ln$Du#W-%EHP}jJ*vbPg_uaAMaDAf*q9t6Wo$c7+%=ofOpUdJ|4^oVpq_S
z;UBocvtOw6!_{u4P?iX`4PGw7B9%=@J~}hUkslxPrHQ{-T7%(@iOU>jjO{zCDEl6x
z2}U922-rn4I{T-!=}&w_+3czc*R>uLx~tzP4X2AEG#_47XKc6aZU7%23}#w0-SMH8
zI=!8Z9kdIB@XQRQo3$EEyL$%6Kbfj2?<R`Yg#I$l18$u`*(MmgJ~E+vnY?O#R4H`p
zPj`uVR7mRt7M{(G4u)SK%9VdELo{7E1AecRidfgfi}71HEG$1r>BQBMMYz|Y;gg}K
z<mQPBFcA=Tr!x*t{;0%%ViI`Nn|$BkJBsHUz7Na(dLJF|Rt|uD+UF*rt`z-Bhc5qs
zlj@g;Q(z(=r1%0H_$6=YhBd8w&HQFIliN8PxK1tSUo+xB?zITwn1ML1$r$gNGYs^@
zZy=6bOiyQ{{8z!sPkWj2<$9Pl<pR^x9N4f_xH!|7;{6a@In4~ZGhHAQBG3FeNv^@m
zqO^nuxdZbIuzTo;>l<Qc;}ryB6%(9}vh`bYROw`m##_Q%i~}|1EP6dZ$&3%S%GpLd
zO3Rt4Wx4*T<=OtJ=kMq9_j58gAU&1M*o2k1EWc4YP)+T5X^yv~zmn$N;uL9dcPZJM
z&B@>VwqmLWE%g&DZak91Gi@fvexmS?^d_NkvIaK#^q)IBL?;y!0$viSSFYTcR9HD6
z)=oL$wyvI@jt;BR1A{|3HmwFOK5EQ@<s+3&=f$bjbq`HpCmSZrjLPHp%nL-qZOrl9
zUn`o`a&(~Do`U-dzYVoY#OERkT4b}+q~iaIn2+6Gv2Zb^Je6C9GC|Af!6N8B<UsRU
z=Zd8jJ|XCFBW}F%d=qYIo)b25h8*pZkBSiyxgO0Ov(ENw6Yw;S_G{q^A`J6WrMl62
zs+dabhRs9@HU1;DFuYh)%7bKzCJ(Fk@x=63d!RFeLe;msK#lDBs~}Aifr2^u%AO~&
z7;>G1C9xFP80<coy)$>muD@_e#S_Rj*xQvzOTRX1>s{*?t}pLirmIH&z<TwH5%RXZ
zzs#A-9(hSY0;>DQw`9tYn=y*T9mrfyz_1nL$;9uXIHFa5S2dbhXDiWE!D{haVz$6s
z3_Q=S2VV_z+}@jB4NP*l<TpI?@aIcNYbB~Vg?=hSFk9<r&*T45N}p_MHWzU{l>_iB
zE{EcySvB@t2t6Hpq}0yvwp+WfxFY_M`0)|W<q%u`8Tco0M%(N<GW^Ct_x6GRQz!{c
z>@{}BE@eG)c89l<q4!I)lo2b~H&QqK!8ZDBAe-*<&32lQL*`Gfuccce@}~{kAf)&~
z?$>clems3P(j6gG^^oT?p*mgfh=i4P30nSQha^ge1li-MjNggS{mTM={97bq1mQMK
zV-1@i$Li~dcww5@*>+Q+6T?pFoJ={1AQ`}gQuL%^ttWiG-9p!9A^mmH9ao`+g9bF9
zSM=@0_jA^qeq%x&L549lfx#n^K)JFLW||;-8gk{>=wG2BfGOL6q@-~r(w)YDA0?<S
z&k6-ZH%3qv#G|T&z4{#On0ln=AJV5gGH(=`pfN4aEgj6wy;+c{JA;&SuDjMv4aEr@
z=15enA)+v8dk1eb8L`aDc#l62$yyO5F=@yJqSzT8x4~bhGe~ps+?L{^ccRQ!MNqMC
zjckVDlePL!rSa1ZO9f)D+;4=E2)I#Sz{~7AsXwi(@$>A%hyCMa!dh%(YWmAAU5Ff#
zBm7AtydsB$;y?&lfr|C-L|MD~#Jo6CN&->4pB@G+li;BC@uCvaiV12-ihMJdeN7cd
z!b=M!e@%#5Tva5O6css&;I~#4oi~3JspKldn+vhI{0w64&`XUJ5#B~+P5eWwbMhP0
zmKl;lfI-&FE>zc|SBE0JDw+A!=NLHQw@u_*LDNJc3{`jU+VRYSnZ6gZ=GrOi&45L8
z{9D|-LKE{n#|MRm(G$tOVoA48#O|y3gC4)P9tJ1!^WqD@pT+Q>4L{qnlFOOG@z@Nn
z*0S+hyXj;G8~2OV-l8eL$hUhB!By$$JTv+45H~m%*MEQ{^1+oYE%w^LAvQ!EihsZ`
z^#GEa^Y*>h+K=@M?}t#`74PTKS}vY(3eAk$;-$+BUjNXTghMTnBnh=Sv?rg&S{E9^
z4_^DxiA!7gp599}q;6Aii&Z-MoA$I8RVT5QD*v-pWBthmS>DXQ*?O@l55tcd(50m(
zXW2=n5zysd6H?@2c&jn_$Re%ymPA|;`KVgxHUQ7k<9Qz{!)yA^(6dWe`&s<#_4y&X
zuFBq=POk3CUX1OfK}WSx*QZ<g(ChZdqf0wb{1M9*k}`|JC8Q!PK}-O2pL4WmBd}aF
z_rK)oih`H0y+;7eZMQJf9qQj4uj>qX^(2+#vis_)gczXusDA|OxzBhst<$oGpkgx}
z`EXuFnL&p<m~r;C-l1z6om-otz<wmO6o?E7FfEdbxgYr8+PW+MRk9xET9#S1=J0FE
z+un$f`L6D80`y}8P5m#Lbqi81ommO>fsj&De9)FZq0V07Cd}ss!l$Rim(;tzfvCIR
zr=cIbPIoD|l~@b@hm=1#ve<lFgo${ABq3KA#wMpzxg@uGiU+g*|4F!hGWG-ABZ>dF
zcs<@BbPXmo8c}~>cItP9q|z5IM+Tk&LihqMg#!PO^J$*A4FAmT|M?%<wSAJ-sdRrp
zix8xfO8<531el(LuV2fYY$!%1C}cb8a{wH;G$;<bD%M_J!OlbqsBdJ*@M;pRU@_5J
z(b&76WPx7=nO0Z_o(q*v-+3`@Km=YPMd4IvF=PzzWjzvS<SL}VtOJ;UeQp)@BuFHx
z%qbMLWuXDrQ2cPuH~2{U-U2#xNnHTa)xbaQI^G&FXe?U*56lh5eEFDP>om&z+s|h-
z#g8h_k`xIZX=*o_(m9L_RmbHT?gEubklXkoCENxtXcZM@Xt)QiZcj<2KHJ!wJuKc+
z9hnYFXFN$3hM&XlmT=B8DUBpBK&r{!gQ04O*-E)sZhRtr3*I7@LlQ;$K9s~SO-sJW
zHbgP<I`An0;ojpt{n1)W;x~<;sZ()uX+!m+lZnJ<6qM#GhI$RNVB>CW+3z43n8>n*
zg8X1-G$z%mblR5c1bMFJ{#4%cU*Svgv*=QIeqaSL77dO04E^eo{~PrhtI%)QALAQw
z4)s6kLZ=l0B1u;9Rht9mU{rxH0M845&UcrYuj{LtD5!rkBx@`4PJt6OEL;%IAJPhR
zp~a#Ae`IN%W|Sq@8|uk>IXtA%LJH@y^TSq-vbHLL?qRkl3n&1!D<SHhWAo^sDkMYG
zX)=bt<Y}UcTQ#OCF*g%Ot2;5bib)dGu9%mi+1RAqNL8c(fO}T#hj};g%kF9#u?mG2
zl0MZi{91uhTu6IPCV0hA5*1;(23d2RYa^S$t`MeF3)T{fpIZpnFBE}}N`&`e7{BM^
z336~v*|##|V#A8cqAVj0V5{2YE-qXZ{bL$I$#hVdwuj2d63(n}3@srM+0%UEEN>2H
zh5{h^T_1m;ZiD}1g_a<IS(J<_bP}Eq_7_SRujpcywLL5ucXezi$Ljx$eyxMrGqm3*
zlOA1WD5_TI4524E3XbGJzI~2lLn3^l3ttfW-|5#Y{Vj{HvX&hA9KuTxXh7cQ1tUYA
zxI2E6kcomw98GIj>UkgqOmp#K>Q0TIx0PBf<D^@2)_uf~^HIQA?Xyj%9fB&k5U-~x
zcx2s3M?7F7DOhapm(2zcz@P$lx4pFFA*W&m&1>mE(!kSV`Yj|GsI|H5uuTXeDmT;;
zi&p!g^L-q5nhWVb3jDlvLJP`d%O+e{zNGvJQq??2(HV)hgJwi`Ok)&j;>f(H?QF`Y
z14U376+tznnI8%3tuY0Q`2jG@*LAB@A5lG!{i;o@LcrgitA()oSnP#{-g(Z(G*M%D
zR;PLPZi!~2e*nAWgFfOAiGpt%#!i3Sfu?ZtdV#R(hkTkQ51MHEm5Zbujl;Kur{gJ<
z*GSu0PM?->to$v{%Q$bF0cg=^?GR41Hi%VFWnpV_2?|!&kbzc6X>Q?+K#1zCvI&j-
zG-8Y#x@J@6WH?5dyZPncMNp-&Dok&y^=R`Fgj8T;s(dicu*6Ss2an)Gd@p}e+9J@`
zQL@-rB8DsNh1t;ZUPC?8$nhct#0=`P(KEq?>vZrzK{h*O$l%m*qkcBvxyr*V(w^Ba
zv)foN?~^f;Fff(}APh?5#+e0Ri8anM1-g`Gdx6nzbMF?6!!93Cnc0ZUCk4dXXQ6oo
z8F^NuYmmfhiS#7W0%!g1US>)le|8bFutlHqs5s-ygC@H{m^#|xWh~qn))x9mWMK8M
zq!?^Hot&PNJ<CA*PO*aB5j0aUO25*xV3=aF_JzA6?NU&pW{4V_#jzD&SSRN&MK_mg
z;C3xpS_#DID_VK_9dOKPu=Y?6P;y{-f`t=mLKOk$h(}EMfZM=_OkB2tVVLG|^_NBQ
zMjk~nhKm$47j;DJ80|cAGd>DZfsUf`2vWf)DV(aU9q?b9(IRu<JqBM6YyMsiro(o`
z15#iOP-N$1vXab7sixXftN4+}^eLR>sbuosD%gqSmJrj$=GB#zr?W1XfXgN4O8mDc
z`=^SfIY#q#pWtn)Cn=7;kpfl8e#8=}F^fM$%2dZ-!oWqeQ~O}K^0u~fb3ndWI?tg1
zQFLX!Gw36V==5^m5ozQG(*J7}yU#??;J>Qag1!=`-tef&Xt{>C>^a1_W?}|tA@OYB
zlT~bC4XER$^^B;$%+`<@C&MkEK8Meo&L(F;!8ZXsOmM0Kmn6xzbdJVbY3GKlxFfdM
zF+{IET3wAL0|md_=0h`<7;&Tg>mt&f-G~>d=bI<PDM5#(O4!yyU_8PKgNbNJU{gG1
zd!%}PaZK=m45T%y_4pCiC-awc0DEHp|533y*=A`c*CEx31+@Prq1{TFVIoK7`N5xJ
z=_^COLP(E;OY}M0Z@?*zt`5m`>!52>cq&v;Chp&HHz76-%uje$%;#ehPrTA4zo07_
z#A7?sRbuLA1Mr1_rI(8B%v6v_Q0f^N4@6F1+5d12(^YNfn}i^*rLh0%YLsJwNP&Li
z5>}MPdn0L6Z7SOaou#`#VRYuGEIYLbhyjL{QW6IZt4Qw>gWaY^Hi!__ruDxvYaPNl
z72MZ)OO!3tHx}-s_3Ct3pnZ=V`Eh|RdaO*|ig^mx!A+fC9)|x^)<;ik2;D(9fdsF0
z*wC7>7Rl$+>jS3~iYnEr9N957(O{ZZ6ly9F5>m@FNr|KqTIQw#FC#c?;!KR)l_&2M
z&}V#xj%Ca8<j=4a2lN_tD<{HguEf|owdtguUePCj$<rsvd%9?s0#H+uw^WCd2~CBG
z8Vd3>dF>Ah{ro3;e}9h34mt8WWoFc$E#a!Jco(OCw|Q`Zy`m6}4T&Z}D?%P+k5ycK
z=8Q(QN}bg)L?})L_w<$cnZ4>DvZTR@E0Xn88w7&wG`ZZr;7IZKgX_g$Xd<jg=G{6e
zpGj2z(|!aJ&z?U|-|wt6(YX(`*hmBn7A_D*moCR-xT*xd2N54JT7I=r|CNDdC1%d<
zww>S{Oc}JWAp>!=2?bs75|Yb$RFqJ#+DaLc&H$7<%T+S!qO8quE3DVMP$&v6K9PFf
zUW@VI{1HApCLmv*lj|HVfJMH61fL*9C+OlcVD00B<}09GtBP!gI$Tw$(?;^w%lWaS
z*N)Ia*W*Ygm;W0Mk|dR>Z_!SnJ&wJ)5oaBPFcw(@aE!4TQc96)FtdhRY}<^j5POZ=
zX%wX&a|&Xu2h1pxY_cacOx|Vi@>`R|zX7Q+Sxq!2Oi8;LzfzCb>)WMgBW_d#&i?l?
zJJrr>wGFV(KgD;c{Mg{!5KwklIbIJYj=o%PCk+1>EdcF(xxLiv@wi9tIWgazCUlQX
zqMc`QbP+NvwsTl`{U-+2)_}-C&q`3zII=(f4%uY1hnQ;Qih-fgY~?eL#6j&$LGm$^
z``1XPW^aav2sj|Jf9eq!wrJ`38sGB%I9tN1|NT{E;2PoDcFb6p{H3MA7Wb=#+PY+U
z#Jvsr0&u5~nA>HF$>r8vXwceHY@NCXw_XCjMyMKrP6f18a*Pj0KbVpwOaL1s0v`_E
z#wSy<LxHV*VO*d!zX8<hzR`aN?f^~?n#v`UJlu4p@;?c%tz`bzJEX+A<6DZ02=iOD
z1CC2r4Ai+^5Z2GA^xK`}@ks~Ze-mJCMC1f+<DdG7rbLic)PL0Gmi^G0h@8~RuOoHO
zFu5526mBC-WzUuh5f<5!5}({_3a?LhWkkPS7{9V+%9c#F^LRWSGuaKEJ%Dqwo*43Z
zWB*EZKY*RMg@yh4tM*3%##jQwN~;CW$Nn1#`1%F{Vk0*4M-s40B@`eWRdgcer-=C;
zKIv0<s&9cR@z(?i)~|O-t8NWsra00pzwGZXWehj-O7V5Orb>1`;yGHovCqGFMsUbq
z_ChAc>h4yAlQRhn4|`~jXILja20}mgormM!f*V3?WDh8m)%3lP@M4xTWl|ZK#?Hhw
zKZLNQKZXf<VyUKrqadSQZw*!d=)f4aSd1Nyrr7Kf_`2$ypamX(=6zL<w{^|TujAlG
z_ud=AdQsJ$_5{%XC%mO*!x<6)1CTD$buO74AIpB*-b^D6n6{#uB#3ncwS{WK5W$_{
z9!%h5&qRVS2x`=iddk_f{d7`A9sGH|ivOjM6Xn%P|8spF%_{$dPb-HzL(LH>3H;3F
zn4v2}-y<VNEGAbxzjWgxN}B+Y(##DJ?)6yV!cKA<tz76+JB&2k0<^-WWG1&TUWmFG
zSXf3o8tFekEgm$p$8S&z1oxL1{r0*=Kf?xIBh>Ee?4;=;=pv)LaI}NTwej_W^mNzy
zCsj-|wVHRIpg60dfqoa4OZ|kvwYG1)DUY&~O|?8}EMJLYGBg~t;J($DJ;-!LI1}PL
z_T=zElgsJxw&9!N-#D+m!rh}u1<ngw#lDEzK_*$;+lW{0j3>P3K%?XAQnNQiNb~o!
z{i5mlhMQK|`519V@I)pli#f}oh7ySlLZxE~HS}vX8E#@dJxqd&^uTqy<b@!!WX~25
z{4c@B#nOoS2D~JDm)AIVi>PCz@<x~!tA1BT^~c|rZv|!J_v*>-?4Z%620Ty}lR}=b
zm@SKP0HLCZtONnJo;Cn%z2u9f<j1<$FW=6=A7yMB(&JWtywbYGE%l17qn7KnaJV_M
zvAj-axmkQ4+ZskIcP`nqvh$Qk`_W6jjdR?`Bo)jaTi>leHfk?&=VQV){cwanma;wj
z$KGH5$!R|A3B7;&^AyH{QZrnWY6g6oKqa<qgE=|dZqpaJz3V`%M|Zw3|IlOG+3D)F
z(&?EEilVmns1g7$R5fWsEKg2eTvS$0y0D;Lydzd0Pfx#Bq98ZIDz@%N>*i#Da~<U@
zRrB<GzU~RJ$7)Txgr}Xs`+NQ<kz*z*)z)kis@Rye5}{Y{S97(n3C$|+s^|XcN@eqK
zP8!kKk??4ZW%{mf<zto$X7q?N4QfDcyT3_Qw^mXv>>s@);7PO)t!3rP^hAwokuEK>
zz2iZ&*<`8jT7E9mQqi*QNHjt_uthhD+wY8bu@ri7e3ar=;OxBg=eAxL15qz!!+ykQ
zA8w3_qt4c~PU~RA<>CC0fWjyIN%ka>wnrzswQYUzJ)dWcqlRiHrt7c0l)4J}ef&Re
zHkfrSK`M>SkjK?k_6iLdu(TcEcT1s_nREs!mD1BOI;y@{+lSsSoo$}Z8Lt+SVmofo
zZw8DjJ2(FI{~UNLyc=K{VRqj*^xU*Yok=<MOa;>F;AP{N<m|n4zPUL%X2hKXv#i<9
zkBftQ=5=vJmtuDqebETFx~<LDuqu-;2$ONov)i^rL2VmBWy8C!@Rdw&M4oqNpLMOA
zeh<?vOXUIjum{z`uGJZ>==1KSutqZQlWx)PksRc-ZK(_{{k_Dym~*dH5JAd*!Lg4y
z&FdERvgP8pWvhtt<ocdr;vQ5<KCR!}D;2<#&bpS$2Bx@e+4g;jzMiW^Kg(Nj-Y7N>
z4|2T{V`oRn3BQ~?wP!lTXSit;k#bks$?YB5W}Ht7lGb+isL}pdw0QL=dV~_Zj^Z$g
zXiOtR>O|1z)-X{y*uxw>{<$^uAx61Q1x;#P_Ro9*3O4aG^|ic~(pB~XEm&D}>l7=b
zi4?h+Dext0y4M4cRnZq?qUk8wpqmRYX#eGjvkpDbczTepB^K&VRwm$D&%}4S^*L7$
zT~5aNU8|YS4Y%&uNtXZH)wZ2fVyLp^Z1SXbuJwv2BAmz2Zl7p7#{A`ZVk^z$-JpXO
zf6<2|!TC4G3pt7H3&hJbVoP2ZJ^s<BmU6>S%$>r9NXO{~rmObwAGq?yn1l4JYM%LP
z?qZN+Z5=0|4>;kTDJ7F@bMMd)Xj#H@#Zd^P=WYlvg_S_DAdP>=_3pyszT^{MKh<Eq
zJ5&rP5H&EVIrq?A;ITg7v6^nDG|x&{WzLlLmBXyp2-Q?aoV=oVb_bZU*@vESsJSD_
zM2T*jed5c-yWbL~T2X8dC-UEuR-{v{s1K`JT5anm%bwdp?a`-vip-f(E!kZ6yuU<k
zZt}I7%opV|B1m5G+S1Q`kvgLND(GO9@~nl;Aa=-V8E@aJKK=QG@((IJ;oLNPy?<74
zz;Cm?Oz_Ky>W$T@icH(@eY~Y8%ND-!c`PvV_g{A!J!-U!F(`_~sL)Vln=AHg9#8NP
z`)g^o78(9Qmt`x=clSgS8D7I|4)Xy{^Gn3P!M7~}F$d1MWVR4+x;d_(IUF;=VI7=r
zO1P{zI%LBRNX@{-aultL^_{n)Io)Y9o1+~9m1lpAMt4M9X*+!~tewP!PUMjA!F=}6
zsNm#NQI|4#uA4g(PYQE%^=Z2Wh?^Utn>XIf7&Z_4F_sdWNvsZdQY73q_-4?5>b^N`
zkBs-K?VAyv%o7<&10!~i2hbH)gp2#Uj2LAk+?9F5VJa_y;fV&8I*tSjjUUC(_?JM8
z+;&}uej(q*c+Xd=G;phZR@rK8^vHNz+`oZb8%eX8oLog|Z75A0MXj~Yqc{7zy^uL|
z;xq#+-vl?(cjlrDYni4zGmQ%bJ6p2}?V61~C&?14*BzFOKdo=wZ8D@S#q%LSt$JOU
z9lHsue`Kj>&0sE?COG`&rWsxalKnW#x}?@jEcTZ;A){{7$WJ>uz^g7@e=%+?z_dq$
z286+eo#xf<&+7@~k%N|ej6&Yi8ZV~qIUSDk>wknEU)f0<2)>=j>BEcdKfYD+=SyX7
z)iYw7Pco&g!ShzsfaQoOp<~Mcz%W9uE7ke<dlT||-Pf+P5PdVQPz{4U3Gd{dF;fso
znK?1TMkM=3U@{JhfD66^%z$s!eDlcm>(Ty&+s0c^I!D!zdhl+jA?{~=)3zRX5FD8B
zbl8Xbl#hsTz5!u41GVj~>V0aCI1bieh6c(>n?rT=Isy3m1=0j1m>E^bB5HWV&@lqn
zXya#M>d0e;mtCuepTSNRNc8j|^P}GZ_?P=n6W>3mzJdf^e$x3Uv^^4vr>jFKtPK`=
zY6<|IxkE+Gfcwt1kT@5c1lZkWHCtw{UtzFB-glQh+CeLS$j0-;>zmxw_pc6BRS-sP
ztQZOAq~nj5ID!}S!XJW(P?YM>PJ9~KB(&5RHNG2AHDqKuWloz^Vt*`BXY(P0tDIT2
z6nG6JL{P-7HY9F?SJx57tfCZ9r6l*q*YO^4m`ag=v{UNPYL-8)e9>fomJc-~Z@rHS
z+lHY4k1i-29k>d<51nrC)a~B?ew15-PB2DRNQC;}C<X^8HiL<c_@Wsl+L?>iRw7CA
zkjz-^B#F0?oaVM5`|1%}EBpl$B}a7`Pm&P?recBci1=biTq?-tPRY*!Yw?DuNJtTR
zs*tY8g~e;Vl3R|;QhK~&?^L1IQ5hT3Dmkm8t<x$!J?%sV?%~GP$I6<>lNsf}uP7YP
zSnGw1EKes|M~Xt3j#DIFP!yXuJ_`$Q<<b2haq%2N7CCd<W-JnS;ufi*ubCvi=rhwI
zjuDiumpf#LA=4MI8_LmT1Nux(vPli|9^PC|Sl~pm9uN1}pZWFY_GaAEa4A9Qaj5S{
zhnHAKKuOulkOHg7jdg+?ttLYQIO~#k1Sbd-X13{0Vx3oI*zSfgOSF|n0){*wN>-v4
zRu8ATp@>!#7j-tkrRhUffID!!_^HLv2m|&if*M(-#X3K=LIcp@XclBPo~NO6`Xmdp
zIH`OwduE=rz~!Z15fNr0j1;>usgbQkEi;Is;RHt@^pQlZG0?{(NoM;3KHf%>vMCi_
zC|R_P$!IZ`bZ!5hl@M&-A7B0~v%sOm^$I2YjctRXcRNhD?P5LJ0;J9gR0(^*1-6>t
zMv>s16B|ffgZ(wfl$~I#hshgc(ssD$EtV3{=!V%+<xq|EG*XSBACkVmX<2N(tQ?<e
zHi=11Xx196_U?iDrJT~!*|b{?DZug-F=^!ceBBhL%FKJHPRyL-1rx0eFuE)xql$*w
zK{BgsZ}uAGS7^GpvaQk)RB$c!$V<k1sno04{s8Vii|*9ralo|A4*(MjKvVTqs@x`f
zg*wyWyUMOK%%Ra;p@cm&2|7wo$;}JwT!51;ezn6aHCZAmK^7KX>+0g(J`jEQE|fBD
zrf<M1gt{nbq?-9Jt93-aP4+N7U8!KW>5ObrxpkWr4V{o)!%9J+OyIo_$D))qBohEO
z(^0!HhqqCSTIC{TRaR2l?C;y#N`uK~9AnfS+mB)AP>Es`i5G|fveOv2LST0IvE{!6
zj>^B(a9vxqQW{c_t>(xx5(=)XnFodQd?zT;$8pna&!C<$Sd?sFPqXC3>=$^f#*^ew
z_=)!tgX4hjl&WH2#&eky@*Z31=csYJr@JgHK2JEC?90cg%yLTx$)eLDY;uVcjDE|3
zy*F0p!Z<z~7Ay$n5<7tn2$C;K&YvYzr}NEm<t>V)Ry^J5oTh-slPQ_NYS}4__AP+J
zdZi1)F%9P?H}?=(h0=;sB)Lzvahtzd(crYBD}#?9MbKlrimmu%(_l%N0BNZPEwl+C
zNWmZ4x0+?NGkD)(*eLO?|3WRonW4ek>JDx+bGlKU(41)K#C5&G!ccKrYf<vdlXl)9
zLNppl`fldRZg6!Qhbrdc25md}>n#fUu(0*uR0xJe1ejFCTAGkRvPe>G!V+{zVO5fJ
zcuqnM3I8ChGS7_raNFFvUxK&yh*OwD5exxjU<8@GIsQ`zX0%w%Z66VLHOk>=u0_$S
zi!Ylum1`}dBP?$Unh}zi=5Fi_q?D#;D886HB+mH!V;|72<b?pAr^x-<aY)50>Jb<4
z)}h^j12$<MHrb>WLsm2lQ!L38CyiNt;UF?02|cb^ybeWUt*5YtwwMa4t?NaZTDPg9
z=m3|hb`*gkFQc-AhzTfZ!K=(9mP$RMwosEkv8ptdvPvIKF?bLrwkkHWOxIv8N`raw
z9>;T5RM#}YfuJe@`76KfA|}aBheDsO-*K99xpuvvYL?W_HQ3If6!Oe?O05(D!47xg
zN}H|HZM&V8gP@_wVgt~T#8v+Ku~;M*?o=IPK<L|kyEQ+m>Y7f|C{<{|rj$yaiqS>X
zZB)ZkN-?u0jE<*)xrou2B(AO)yV+<C-Nx+6K0TcjS}PKi^ht}TN0aSej3TY2twAm*
z#Kqh{E6M@*(oaXLE_AIp!dn_>Hj}+>L%WHoz`A;*(*&TP#YQvI`0J3%Y;aZ3w=6my
z9wB#;X1M>RF9r)I!pl9j|7jk|(n}sAE)DvLjK_V16wiFp<@6T0$bFx{u2g50?nDPZ
z^6Q*;&AUy^JP~a}6XZwjYU&y@o=wNe*h%cAjil;V5>;avLm9o>%vycwNg75NSUunr
zg<Hv33JrnB$}CZT2S1gK#xp?Y$?B*4vF@LP%R>Hsb`Pm*&4w++=TF69uKqLR7D^jl
z&5Ek}a_jw^@*J`v!108n*!m0mZJXugUeE-$K?J@w1ZZ5-f$pTFW_4Iet*}{Y3oxgs
zx}?-~la$gq=M`Gx^PPB+l4yq7iWpIL!(?|Cd@XW^Imt!jb7%u}>2yg_%(AS)!LdkX
z71a^j)^Az*?3#pQl6AmKL&C^9B0%YH*2MZ`L+7hwhj?<cVP8Gp{I0GFAX%R?4`(1=
z=)=GJBB-sQ{NRUXsdfMJpu|K;%_J|e6faK#(z`%wXG8G&dA?DMcN8AG>4m#DcX;hN
zj153bZxeM>t@9$G?`f6fDWlXnmDi?S&UOPoOx*r~t9!`WL(6aeaKYd-p%wiuEJl|t
z36bC=Ochh}$W(K^SxZ}pN10RU`e7f@l!l}3w=qO$AA*q<U~Xx;M7Wl;61mDnhpbM=
z@^42KT^(10^$8MDgzLlgSyW#ZuA9}kE}GDX<V%t^hn}^oOG~y?y(H~-3<64&RBdx`
zQ+3|5l~h6fR^1&GvN3|2ptCiiB@2KjuUW0O*|?$JbjfO~u(`00w{zCgJF97>-t_3O
zXzhr`yxgjXZ;fuPp75aRK<Ma*HiaFnT>rFtawy)=I~ze2EHiswoYAT}J!O149k4JA
zXBem=4~Z_^bscQ007Kwe@Zm_2im4xx`&r4Zw=b4^GcwSKjUd-j(=;F^D_qMOGvpqZ
zJc9D`NAEgk!3&%+ro^L5Yc{2gn+S4FNyCcrZiNqmzwqn|e}z1_HJ$t<O%2w3rX_VW
zu@CUPEF}+Q<Q_QE5}R_oRyZ}C@;q(~HKMV%mLgj|7&ipXOw<!yo&sFq8A^q$KXNZ-
zk`(E&k9fjLltb`v{m>TiFdfBh)b`f&i7MGG)@JtfN!!CTHHYpsHFst%CuSN8*w$8s
z=Qw~*=JGj=<od_^hs!5{lH13Gk6K%$-7`uo$#!-7N6Yq_HG4aL5n#)vJCxI&Mowd;
z>7VunY)|7Ge=97_23cGx&8<7ndC$J1#K2_fBQ?YTO;ET>rGkp~KSI@R?};44syHGe
zTa`=j6%99cRVHO*To!$#N|&f_kw(y1CCW;t%lf-JIQj+&5MRqclMxIF3-IJa&tk)X
zIjjSDYx&^R^uvw!%(l}Y8rE{xc~zx&q?o!J&R{LDa9D*(d^%g*XKinu%U`)(7)0)C
zvpDi|O-eN+XE-V3hde>zidORp_&+&Hc6G}0z>wt{m9kL8K1ThJdC}kCLuHJQMi7#^
z3PKBzko|s*FBk~;lIA<Wu>ZzPAVF^??#IV!LHd<29jKInm)0FUMp1fdKb~=loY2N;
zn465uF<ljmjAvJ#77dFBL}ju90x7WF#ubMM=4Aar;MvkXEI;O;gkV?4%UDvd!T5_a
zT#FWG+Ej}lJ?Yohm<I>kh<Pae%rPwV*2=?jG}Gp<0t1a;!5?S^@XBILDk4Q3`EfNw
zTqF6VYIi{A(HC<+87*u#jR(L{w|infe=~wD0h79crkI(LQ;LZtpH(m0N;_oXsM!(f
zJpCoR24)763YeSP_B}(HwX-5?yMjj(OO4u!M1K=m#D&_`!RxY%z{ku#jZm_m4&S`j
zJ?s1F)2TO{P7JSp8DM&<iYK{z<%AwemiF74TsWHiBWG)PQDoFtnH=_JK2v454?K)|
z1~X$x{(;N@zI2iyB}>Vo<>h4|lh(_1sxZDJ@xo=sT<-g#^%k7S>1E4-=gsALj4At(
zb;w&{r_#*i?Y4^^W4wj3F-~Q-oSW<GJxfQdQY~VL6f651p02bwB`f4`)_lVaFn63D
z=V>-i<8_0G8y0J1J@6M7@_K7G@99^;lV@G9qe3M+H$+T57p&RWT%u(mdmVrVchSaQ
z>7V~q&mI~PIZp+Dm+p@<>R@eq=TpVz{d@3$#FNe0$;WO&iqQI=VprFh2hdb0+~ro>
z8_~IAoPL58m)rIZV{m;A*qSz{n0e0?#O;V_=#W_^a^q@zsm<VNe3;#!HqTlK?t?gz
z9D&RHCAAf=V~PV#7lzK)u`}Xr&KTYrP|F8I<J!i?49qJ;9-1*zPdTIEqw~4uoo!T+
zNZZ8DTIoCJz?hjcB%`{Gecgw%!4<4$JD+OHoLITF#lVM7E#<}{@3y{T0L<+3#zWoM
zq@~Xb@-DXTdyc!i`<?%!8zbjcEdk?UO+sCrh5(=T?FD63O&bHZX4Z8Bv>fmzs@Qvh
zd_MK^>bAzaL!haW^U0;|?bH=5MUF*VZSSr!$-pA~OVC}8DcVfW^}bNOhYlKyl%2!z
z+xvCehWV<U<+0Ctf4K*oRl2c%`EC-*K>mrjX27fY&ZG<i7wayTSw{$&$-!DRFK6o{
zUFM$>9TL@_7~A3c&=u5`U^ib%@cH{Eg+z&$Jw({9ZZXk1){N50%)83!iAA%*2?$$?
zu7){tbh8EISHXUhMJYfBx^Nb^gu`XW8nI6Ozm^2$6()cK<h+5*C+y(_GAD5}k%VU+
z;1)uA@pi{t^?u|=_%l9lJxnqL@M!t8i`2jTt<%<J{Dpk!sVzOSz>Yw4>FdMaigdpn
zKSPHkh5ihHXyx0lfxx2mP!}5xKC3|>I=5>sFj?Dk_iDq<+I6ub=4?^8+br<5MHRWh
z>0jgdw}m-FY#y|p=5);(s%${r-NuLW^*2or)It+-(5h#2^L&c<eW7?=SN!I1Zgw_l
zcp~mM7};LI0GiD0WG!$}jY@ec*9f=P4&uUsmy?%Wfqw#qh8j~qNqgB{IHnR_pz*gV
zenTW%@B8!cN{w}H#7r(BM#%JW+2jnU31%mt;mTc%a&s$(n>AR&cDK&9X5*+3%AGL3
zqxV9^6vVL=YY}tAG?>=yaM+8sp8pz_-<8mo<lt;>Adj;W!7XbB0@IhCw1b-;^NjJ^
zM2DytB%}Ur!=}>%8wk?!Rj|%|cf?R)@Kd;nF2GlLL!Kl8Pf1f-cKSz1tF7D#kg!<I
zy)evn$@7Sjn_PBz*R=Cr!I6+nI--_fS`m>~sBeS)ASlVD6Qlb6o)s=nxkg8GP2^y{
zIS^9M%j;wGpz4qIT3I`Hctb+%tRk!-Keq~o)uA)32JOJ7$WvBhg`#<7I-8xuvbd{u
z?MNwS!IWK#0L{9<0Blb3GI(804R6LW+Wsfh2AP_SL!r)${$=vCWzU743a%neo#+Z2
z*MD6rX>wxWRCy{Iocor>P;W-}=QHDM>G&x46fU!3!u>U!d1rt?{B{{%ENarlkXou-
zXktJ(G%5ZETW=i|#}oXE;x55mgS$iU;O-8KI|TROZUKV3hQ;08-QC^Y-QIrR`Q7)<
zJ@@|e*{ZIto|>B4IXyi+RUH3#W&cz^L|zVSXnuP_erh3fC;R4B7(jQ{L06Fbg4q|p
zA88lz6AAba;{`EW&6!yw*Xej9grAi4vKxA}myyYE43gHp^h_&!k=x?O;zy??+vMOr
z7|I<fpe-kskI`;|HH+TJ#JI7OAS~I~fR!G9cZf{8mUID38NibeOQeSnzVI!C@Qy~$
zSXd*xG$c<eq(hLP2V;ZuHzDjOC4v`9C&kXU&U7%#nDCka@ji~`CK#%ZvR&E;3NB$F
zZL9FrM;R}d8p&9%z%`)I#!#g^A0k{>?5|X<W%oB=ukhlmo8*y(Ja})4*Zw1mtsB&t
z232W3?eBA@-FVS5Sy?%&t?C?ELY}pBJ)8#;Yqqi1u1CF(3Gmbh6)5Z%?y|9zhuvfu
zQC7wQf3z{5!k_CSGF4Y<_<>Rcu_wDSeNqfgD>#TLv^WcwaeVmB7ZHJD{n;9bn8S!=
zw>0%Sxl+#i6{qQC|GrnzBsPN}ych(*|FO|(lAQ#yScETjn0o1e3TztmnD+etQE5v-
zbh4?82Q?_|f`Bw11mFH+SyYH#>=@J?_Ca3^Sh+QT#^<?>%%8RnAfNbaps}P!N#rS>
z*AIf9Vjv)+0D;jz-rEhWQqYZ}V0-r5x<UA_!#<XH-U5Vp`uDEV$`%>k+encJzT3#a
z@c$?&5cEp9?zh#b_58h(=qX%T0FAygOdlyy1|7*E=?efjC%Nong`m6dV?m?2f~dIv
z*uSU4?j|LH-?#n*%GQ;EM(_Qri5UX&L||ka9FcaU;YbHz*UQzb%WmOEANPJ+4s>m_
zxt>GjwhGY-d1#De?}`)B3-J+bUC?}?wg0<nWAtl&JyDOcSbJVg**#ZPXECH)>yY$$
z*xF1w=g?B=k50FV8^9vrmOAKX35kRl)o3K=EYx}|K(lSfRju~`T#MdP7lm>y$de&r
z;Hc$+KAcaHiTC=G+V0xSmURo6{+04dZ`_X;NTIElojO6<Q+$oV+PbkCl4fJ-ipa7w
ze2T48`FDY_Snqq8E>DYuMw>9(L2%_pwTsCES=TT}#DP6l7Sj1TZD?igs*_pw0ms(@
zM9Lhb8ls*8wGyMlj}PI7?gJO-%pg%yd1L7(F(ppO(Cv+Y^g9HR4MPJ*)OZCHtH88`
zfM=|fxff*z*ys(d=w80+wpXW$2lit?*`(J}Y1wAOX}SAF&d;k=*TptBz(Xa#qND8{
z@BXrO(#u_2v!kuNZWHi<<mIjoY6o=(ENEX<`oVOxRf5`=)UPVfO5J199naS7EIsVM
zoxr_P8{@f)aqwugZ@;c5{x*N|$MYWlA~c&;l5P7<pi-WTZrQX>(oXQ}*^x5NeEqqV
zMDaU`CU`|5as9P@2j0^M)(H(t6C9;B)}{2&G^O~}0VJL`=B9XGjmh6u1F54;Ok2L`
z$;@><zsZh%7-Wic+Xp9Sj%OMUqxHal#MgIZk$4~RCIQGA-H0)12|?>)79Nf|hJ2@u
z&FtV+cJ%xh*Qbr+|B*HV|B>7Ok!6Ay*Ov@E=Wx44UipcFYyCA~`j@ysIyhGJo-*19
zM|$0R{G-g@cBK&Y^vft~+NSBQYv@G6<6XFIbi-ViN|mS_s;p+}GY8q$F2R{AK9{VI
zP#x5=V%4p#kW^=4r~8E6up~D^UPGa)VYzi>{t7eV##?8*;0f4`=ihvv40hqU=#*Q<
z>QSX-#3tMJa0;lFb4U$q7|69ltpXiO@|FrnXH@2~G61T!wV|geOMil9Z!;i~SavcG
zSA_{}wVpRlh<5wgDNufh7~lPliA{vVr^mMj=l|t+&Ipmo#cCF%McN0;%6Thbr4Duu
z{x0V|E+lutegMzZ%mZh&|N9dQ>rN?b{3|r)Fa0GNF;m?;i9H4f=BM-W4NZSC!_PgU
zY_oN&9r?|>m^m&p?NgdpaBo}AtuE^OFAvz0aN|h^THl_oEXV%Lo*&*y&~_UKp{_;f
zOsFI=JEsWlKOB2-u&T*o%n#I<FVVC`CeyyZ=OdKYI+-KvK+YZt;s$6Oa$aAHL(AnQ
zIrD>&sDZ2N{|+!v>n76u68gQhxXu&v?@h3)x5%A*a;$zW{-X4Bc_kuOO3E0=UR=ek
z<q145-com_c7LX@w4LCnD@V>h(IZJ*yAe#QgU>7j3fz0RKP94{v7E7TIst6Sbz+&y
zn=}Ahe+hYI7l&MS>~W<eDZEO3E~r+3?!KnRj``k;Yz;M6D|LfCb7LwTnc*qjhmncj
z*IfQXnS;+r<~ro_rib)2(54jWQqRl*hc2j14O`EtV?%pG{rx7(X;+~Gn7g3Y!;Dd%
zUiM@bsNsCjDK~9hxtap6GlBJXD{NCd7KiMLSDVKq$~A8`9NLPsqLf0Gamr?@3JA3=
z9gC9(2}?l21+!siSG-$2Kq$Xv3fa{E&$fg5GlNtSK~fPw=>KA6L97ahRRc*uo&Se@
z&t($z1t|!D4od=3LOo^MhXwU4XhnKa286yBgTx>WA<%(Il1!vXp4g%Cu+w?v>B<Df
z7I5pJ@~y|UA(S~`7z2v&6Ox71;+21cmMEjdY$^*3e5f&o(=+L)httddgZBSm{6AQy
zgOvLIqr2pik}!WOyH-Nu=@Z#AZlS|Vl-ShOej^T6djpYs|EI=NB{F<mjY*L_?1V5N
z(AGvn*tAC@fxNI+BZ1;Spb8lpY~;^C(O1$%#p4Ry8wIa0w@3gvvXctrUVuE6B_{wq
zEqCEwS}aV0BdArPxvypHIq6yw@g*4WDt~jho<2#j*+AfD$4lghmj58Q$KAZt)e2}b
z*}z`5lJG}f0OwMN^{8a&27~J*kCwBUqCBoF*ppwn7GmMxb}}qKagd3q0Ups(4yH2|
zbKoZFGvz(Xz&GGX7k3DXToj^NS4DOcV3z#hhF#j1MeaI(t=xNrfS+F2mmT@P0PS=L
z1sq<h*D~Q!6K9kU4O4xk*|ZQx*CSq#(GvB~rI0G<&TgAOmB1fyNC0_fQoPpmLt!=-
z&WQliW9xLtlIaCOSBF0e+h+-j$8Lvmw9^;kX)3vEY3zl<P3#sj0d^LXn7Blfu{OyU
zf#2nAt3EZ59{=(mTdNd-^#2F0kG*AFvf^8xHg73Oj3HG$Oj1sNx2kPT7QQMlEpR)Q
zbo!m?JUp1P3U4(_kN<A7SZJr8b$rn@4pQ@+(L=f>l2SfM3SjMaClyah5gG);O3AM}
z?L6dUTX^KG`diXi<@rah!Dqt8wDiJ8|GVlh19nnXHv?ys43)QZ=jFuJrOZCye5ZLg
z5Tt~}(eTJ=kz3MG^#fAA!e;`{()z+?Qdrf-;I6?wRBYzY1Q5fmSl+huK_tZsX2ISi
z3d$<3U?e|WR_g0-05}+ETd#MXXdI_ip%(tEp%qPVVF@TrVo0?fP4Iz=F~h#iv5guk
zW2tUV2{0@i$yZ8lLOrfqq;ajj@JEh1<k1OWf%Ijtp$dhnOI~0%qcRVZ;@e!3dD^MJ
zb(?^JI0_V~Muk}kH47Awn5Iwp597CZC#PHFQcsy)mGQ#uaPI}N;4qW|$qZB+S}=LC
zEoN{r-Bz#E`MEA(@h&cyha;R)n`E|P;V-rNE-+cvw=pzYQ$Gx0I>%Rp1h34=JlcI#
z3jf47ECs}L!yNBfuAC6ZO-mX7e;@penFer(L0d&(?6XD#m0}|t<(SiV37PTWUcNw8
zHsL8ncNv)Dmmi8FU;;unw0OCwrQokLtfWbDaWadNlzj#96Urm&#imwjY;2LsDfIba
zYKWpar*>2D5sH8?C0#@|*`VdtHPC*m&w9>QcIv2OrgUi(mhn)mB#~$88$g2@?sqli
za2TrxfBo<fMICOV8*k$uXl#r3>o#%vxqvj3(A#l`wTG*eUXflcoKW%zj92cpUMo0S
z^2WD7o@UR$MlWCgHrd>!7XfAlnjNmAX!sV$0yuQiRjSRX0u-qWIze{`+&M=$gW;mP
zFehF*FFbO2C$ZI}0Xy!0-U&RgG@SSoEZ&^c*WV3#31Ww1pbmPkoU3&!v1}0~hwECw
zW3cL<OE}jc&}QAiNE_*dmB>30gl*ORS*XM8Sr^(OnpB_8zXyC|K<%FTGY%*)Yww6U
zSkx#i3i?L-P?oC8?1|EsjY|*yuw5!0Wx^9}i3uq1gkGV<CiSZ0jExkRd3E@yYfi(_
zxe%N$^Hh#Kz0e6GOXt$ST>ckfqh<D(DN(|`grgNzrr@oZoVSxjYT<2wod&B@+9YI7
z=~`(ElLuN6UT&Ip3wG=0lj^P91*oCTU^$PhMxf+~Jw9z>kcmA*BwMgBg>2Q$TvbiX
zj6EZs>7gQZB@sv7*IZSfqL4jfs_(C<`JE?ezJkz7DcHz_?I>cu2DH@4xcNq#B1P)&
z;VIivC-<M`ZsmE;<L06}pi$e>K!qj%#^9Y{X%p$Q31qE_=__h@097lOBbkCWCH#%T
z*<(SPKbHlO$1>(z>f&ixIwcV*F(pY4<3P|qEP2wF&RJUPWgHmjb4}zTM0qvOn6;t?
zd^0oWqRg6-GUv)@8@G+*EmRh(zZeG=hmV5V1)htHK^Akoq{(~!O`Nn9M3tOZNXS_6
zCJry2Qv_WbC-#h6h#GZp72Z1SyHX>(L*iTZjM8<z>@*@9I>EXXH4pQ;7dvw<EYlP%
z|0^T&I^ex&I8!0WK8YnY{Qtw<t?_B{>dNLt8rJ!VCe~&Gb=pf0iH6pc>~-20InAo{
z2kaRLk3H_wAB!Nut!sQ7$hN`EUPpW4Ex}gj**P|T*b*Lo&nC7uX&V_?Y-_GMYa>i&
z&UGN3kOT6*^vU?)odZSM|J8iY%FT6AU-LRDu^;AKQ&>4G{F)x-ckdhHwsgZxHDFtP
z<L2@wBi{fr6Sk$%m7oA|E}Q{?+^u5eLXs%)q%7`22|DxqafOO`G1{T|Q7`kl$}`%Y
zc^Pxin1YT)8lx6mSm!}kxo;K!5x!|@@@B0D<{%SaqCufxoRT(yh=z7z7T%b(f{CTP
zGJY5WT7qP)qh(Hi9|yKe$yjjZgnb_Yoq@1emT#>(czg!vl)@_z;$}gb5C5;@Imt#@
z>pVdba~RUgo`G`(8vUnR1oShpIhT!$V(77owYjR9i+tfs7X6<~5i6GzP>kntw8nz!
zr-OnE%goKXkV@tUPy^&$SAZfsP=k#<gYzbWuR%qyuEdbU8+OB907N{Eft)h;0TRYf
zT2QcOr2H2+_?3+0|6jbPI9clrfULFzMZ+yQZ5GJmF`$l9kZ280YyVrk9~OE!qrQM5
z`rAS3O1ql3`JD<V*vH)2>q<!5`XRhgK^7EJi@MNq)|Ife0%wmWlO){pI9g>3XM8|0
zFNrmiG;UiO$p*3!qmWRQ{w!^xwXz6Gl|BtL=5v3R4sFhgS~Y5C&}CCLi1;tslTQ9~
zzUL7;&rf6jeTMA95+Z>10CLEn#|H`v+Yhe!|3xhP50PE==SJsOG!Qa0JJuD=HZ}52
z#^w%>YG6AtQfl^Ws!WXHN2Uszv{$TXQaDAJDjm5r>c0~7zxxg{;uI&Nt8{46C`D>w
zx1n$#{=c3+aRdp*AmP2Tom^?RW7f2bSFrU(+_Tye!|I|OJ@Vn23vbM80(tH~^xlBl
zhN?g82r^Ar(dvhRdDozubod%@r$JV?V>^T`VrxDGL-TdO5@Knt<Z?9|TO|jIB9Q>a
zju?!yAmGJff-?O8^t~;v!Wk9C&FDbNLmK2>IF7+-p1tygOr0L=O8WCJc_F0g4>VUx
z<)Ckwg%CO{gmH^TUeo$$(EZksMD+n^t+1l?+zN&Sh$sx%AAzjJz6H7z%QG!2!DPNq
zrKCy&UIA6np=89ENLwA`Ldim1xqY+(2{jv8mG<AhuwF+9B6^)Rrqs^RC&1YE%rqaD
zc(7llr3`uY+LEDT>Iy^pXY5aZSR4>6p;Q>~ct66cvNSU5SmQ9laehTAjnz*axfgQ>
zUoi8gVqN~izrAA#jF>`Y0Tk({7=1QCa(qe_y9Pf%gjbe*udLkSWk~Ia0axM}Uz-PP
z9pOL29B+!;oM&UDw_*q1w(;0Ld+u2_mdqs|`j;7MS5_XJh(MbvO!-0|StN8`AV>Yw
z=|E`!n6w#&HH%1d%{+P^^K;$s)j}GJrNDrqdFu`Z6V^w-5NwQ#$f1)GHuT<Hd5*@;
zg~=>fQ6%vCk4Du-s8Qc5SiZ$yZ%jwF{naYe{h&DV9&O0j>pt*GAO6z47v;ETDQ^>c
zilc)fY9f62OZl2#(~J{{0E5d2i2i&ZPMZL<l#sU9CDX<0q>XfL$LVFmHLl|n;*-CO
zkiU#|k|}JrP5P%@%QKF&<>Ux2P=st)P^!t&7KGfxJe_TyNhzfCHm(|1Zr_iJoca@0
zAGL@^v>9Rg8vD=zDTMMPj#*Y>U%x8eVt;6hxzC&njqwNhnSL2a6_*|8w*}a~n>_f5
z^hQ0!UBO(Qlazg7pzB@k&(is4?#f;_Nc7Dx;4?_fN&CIWcDz%X^R)=pf724Fl6@zz
zzBj}z@3VZaTaSX6VGhkJu#=AIt7a%g!0w-Ums$JOVpPrKgzOejJgv;zA23;^Iu-AY
z$6~Fid50`0(KAuuw5Qzzrq*n0w}xwDR=nHoA>3130Zry<)PFGDVStRQ{}if^Ce(eR
ziObyBs5L(S+_C;gfF<6;<sj8g7_gDpHaBD#{wvfrM4U(+g9tO>8|1>=dx}CZJQTb{
zgu*iLzvn*d?pls6(PBUOix@@Zgxe8Z%G{dl1?#o96Rj}f_6C3fH3zAISN}|eq9{=l
za&ZHl;h#yE1`Z;mmB1P69<8MMhHT2WL@y-v75!k35_#K}-x(D?R4xq~aWnf#c&Tf4
zJm}adKl#Txq)$v8kOf=CArJt6-33~}sdP&r{0|%VCVpRE;j|dx2~4rM;)?9>q>LaC
z8J>Knlfu6lbuVobpk8;X2#(`!tOmaVO;c~Gxw}?sCygUSpYp5ns%Gd>3Tzs43|^V`
z-EOKwlHuCme;v^n@&H6ODKYpgEQ<1tN5Yh{bB+gwqjC+ESj;o<4fN}c<#7qi?+6S6
z8E4?|BEUE-0hkfr8XPHq8?JiD1h3pa)jYp#!vFzMWB5sWZrcDdD^d=)53hfNhFQxS
zUufDA3e{P`{Ty8I2==m=7Wq2zgBHFO`rl#WUpFKWlz;$|<&}{=JqHJUO+=|m?vXu-
z6fk9l4<42vm-*cAhRpG!rmztx3BbTul#KpCo%7FMv`LdJRr>=D$HhaPFbJLu55K=!
zhJ!-L+W~Nw@9*y-hB!3fG+n5PlKIJH>EhH~)M|;z<CRKy_yZ4$;9)d9^+}R0OrZS7
zdgNq~Yj7eq84rO)DZ8y=Rt$Xoip<dN5w+KDJ1wXrg5Kz<r|AB-ZDO7j)@lD3cwYed
z`Sqr55u?*Im3|1#V(?TgfPAO{E+*xdO+#>Dir?LsT12YB1%|~ms7gJCGx)oUoyvE&
zau7-D8$U(7(WPx=nM+=j5vWQIXh(n%ZP#JmtIZWt6cG}m7u*$&!$fkuCLh<P3}%@{
z5aiGwMd;B8tx9-_2x6(D+caF`%pz)}i)u{VC6Eg0ahpNBrQf_{AQRSNM}_~cC0S>@
z`{TOmmGF~e0ZPavK)@kG387LLo)`s@n5#y{piag=@?ABlcr!wW4lQR?IAOg(M)dD$
zgYi%@P3;3?ka(6n=?|?^WJ=BJ{a8_~T$<wG(*A52Q%dLc63m#<(<0$=D`=U^2?u&y
z75lI`K+!KZHOCMq%XzXu2$qHQJWSyiqI`4~nbLeZ1?7@<Q@1EOu#$>kgk}j^Ehj!n
zT2hrZNqyC$qb1s1QmpG@QFzK}HRpJ?ZwKxPGCMS-aiz^NSZoO^+NHt&TIuMvS<L)L
zF4)X+r7k#5<n6<dT_9|<(c*aLl|tn?yJ(}7eTPa2V@r8UBG1$)In#WKtmQ^+3LrLB
zvD4NsRk5SyKUFo;R9o8UvPU=6U(_xu>581()diB;$`(u3p?{2=qa^t&Yu;cw__xw!
zg1T(0+39H$8>|%tZY6{jpul7PEja`)L>s+=Ny<}JB~W(^AEl(K(^LzQauiVO7LwVE
zUz3*k{&!JzR1c-t#w+Do)^*PEUt2UA<mjCDL?t*~i8z}2y9AO}<B5YM^A2RqH!A~m
zQ7ATJAM3L3*U*#~fzgc;F0{8TWG7MI3YS{>bC)sbAl7C`(BZa5*XRw)j9kR~3#!Mb
zr&PuDw@*qS%r5Sv1%WgLoe)f(VS%1N8sP+s=9-A-`2^fO0nUFR_0&J&$2VeSn!U}M
zwCN6nFfVr!Hf}Wl48{NE6CK`EmTqW+3bXg9?{9JnF`I*^$(~nIp*NNKv9J2zF+C5t
zMMKs`<dzFwXXToSFpZ{8$JRYdg6Xx~qKZ@$#CJY_uKaOa2#J)Dk%!l0aYfE!(>iSl
zeCq_hJkUD8`iaz@MVq-p(|anhYO;ui#J2@nQLUpyQY_V$?jR-GcWR8*(5#TrwMkcQ
z-j^2dCpsXo6Nq7n6evYk2cj%Qp(nEpCogJm6UcH+@1me%zR$)J{*bw(GH+3SOf}jO
zRHgJD7`4$!a^f9jPDtF)v2Q0=1-#Jia35YJsv*XSY?^TXEIkrV#)v!zAN<2mqLWx7
zoEZNW2c4a`@rPmkpfr>~+f}?m$4=_xB5hXpQr<nVlwOE)eR%yN%^F-~<WD(;6!gZh
zipXCf%$78og(wN^6BRcLwyETJzJwLTUr7!WvRB9Iqwuu)EOc!XmF;Zm@-4JGJise_
zb=YV&-Sjalr98%3@yR&;aV_~kIvM$piU~Y~L_*n5E(1#Mo=E!0q+7btOZB7;Li=WV
z4fPe;9Srj-Ep_-9HeVwwO1gcM#F{YPMQyVymZ`8)DS2?z8jrLZbV1_-q6ryK`~#fP
zQM+7j{e-g0_rz<gJNL0tXem6unsj2UTfR|GG0NW+wM$z25=j(A{zqC)Id$ljCJzD&
zGB3nfIH#j_Roq(`<<(G04kU=~XLO-bc(6{8(scVlYH<-Np}J-ywZUXb@mUc1rmrzJ
zl<PzBvTaGXytmw_V|Kapb}Aam<}%IUXR_hy0r}CYS`t18o*14$rM}zJ^RGfrMPw`5
z?HeqnM~&W#versHTA}=VU$d2pYoKgFQc^a0rQv0%S>ZL!9;OC*frzgJZ3vAiQ2h}N
zvAj5Lo#F`_GWJ`LoA(4MU)C}+ITd>@MJ`MW+XK21pPrDPA%7%*IJsr9eUS1ZzjvlL
zt5u;%s1plKQS(d2b?LD_Zq*Ktet0RM+X{MZ^-+EocTv6<>DL6;P8E@ug^dA$$SL{o
z#3JE$H!4&2UwBtO8c=f9R_Tbj9HLmXg+;OpBES<(dTvzZ1|M;M=zZB(9^M-(kG%`i
zb_d9&@L?~~tclC`;6=nG3NT`r5Php;D_dww_2^s=Et(RTY-?~L-fA(z3NtjB&d^R6
zimMi1OJ1UppFafng5dVC+;W7fWyhxt7|7V+ijUeD(WRIOiM-?yq2}_IfHfgng76U#
zD_*~%bbjeNm5|m!117>Irv?=`f1SFJQ!$tZa&XMSM{F(L+cK9r`fgDP-?V80gQ}uu
zX2Z~BD!p{*!AciJ2~D)T-!C!n<4F?<Q%{aHrbz1#tUJL)-DTU1e8yCua0dJ24V(q(
z!@jL_fMyxCNCP~5Gy0Lz{yX9j(oQG!00Y>IxlR>X#2&CdmZggyJISBHsrtl`lDZR9
z-BJR%U<p*ptk<7j@v+b*LW_<>qzH!Z*~ICZJb|$8N^T(>UAJJ`<+12*_18i<uc20T
zI~C--L&yo63vyvYZxl=1E-8Wqe6rpoQX=4*Rw2hah!2$r;kFZ3{;hzXW>G|WQUPcd
zE8Yh{hBK5z(v-D6Xxr6x*MpFXq3wB04H@0wH1)5$7swZ8g1|+R(yN5rF@d|XatnRI
z<StBgOzkST4l=B8^82+{>{rStDT)*r)DT#T{%K#O*r{Ns;5k!oO0kInRF-HNh|J`;
z;pb_tX2)J8_;D~8OogH%*T<UF+v#Z*OoDqIqOA+h`95WsnAB+IHVI=?{`zMpGrSuL
z)ioyp{9sbxQ4QRWlF4d4c0bs2YvBzyg5_Op1{`wZp6YJ~b2YLKQc_aO&O8*EL*<2b
zB5p+ekalisMX!HQlDUr4FO+60`{34cZO|@Yli*A{2#CozQO1$sMh~eZZTgDIw4Xv|
zBy*6b4`N)P_Yr?RypxuTyNe*4MOJ+)4l1A}M{z49F>nb}Qaaji__<wV)>}-d#Se^A
z6@;S=4VZsq2;V9*h6@`EFeV#0)q{pIY2{(a%{ANpgZ?Em+xFcA*N#~YOp*~-#0?|Z
zs0<vkK9Yx($o_{01|gyaBW{}j;(kH3aQtMaKyqjtkhq&AD0TR-74fS)d-#Hi8u2^}
zDQ46syy)miM8yfBZw&?Jo%+xY<?=-LSKWmSk;^Vm<>|I1+=-WCM&OM0(wt?n=hRpM
z*}lXn=eHnKt;QY|Rx(PI#N}(*SelD&DVzH}*3m~A{1ozDFy|^5gzFCc$ZgBfP44M1
zB+jAf_i>n(qavmt(t6*GGRxicE`ElQ@;2=L%4)^NHOeMBaTa(p?%7K##EYIH#%rfT
zrWcttpm_1YX~^*B-L`_FABM7ix}*5}^gDaU1w%8iBHIcNsq*{{f@pSTIr7@WoC?KE
zW@E%56MOdT2&Wj{D$3)+N7{yj#Bchv;Q&Q@yVQGZdgfN^k`q}l!G`!$6B7H<smGOC
zt;wJ@<+D3{*EI-^PViHl{qq<)Pd+oH@(9x(4h&_k7mEVl%@M8A2G0p5=Wa9wPX5V3
zD{N51dae#$zo&ZidxL4mpR@kcRB=sF2Z-MyRq&VHw?Re;c-uN~9Va7yf-O5;>yptz
z_e2ex1G#PvU<PBt3w$kiq(rSz#Be~5X^<E0o0{9;DQ*X``*D`EWJr3Pus`_lW<~^+
zCNkBYb#O5HuQvOu5=f*L;6vC92$Vf}^2T#ZCn*#0Fdp;imk@01=d3dI^|SoHlsfyj
zyER}nt1hvHk&9yMIROkn)Zdg*9cgn@z#)F?IaULne!lv{0lwnpb{6W0?u!>!_kkND
zXrtdXmSxoDrX)(~F+<o_t`5#zY{RlC=Oo0c{=Y8I9k$br8jUi4W=_xduMdYGE#v-M
z==;93dYMeWH8r->PlzvToiL1&kMM~vfB+vQpS+_D8;Wi1Bx?yxxzf{o@Q6c(^TeuQ
zkuVYPa&%W9$U22?tf0TGN{pHEk+=@^=aLs?=B!O@1kLFl^%^}yY<QAyC-~RjvU6}>
zU5{E3V+45u_c!V=jM_COTXeULbQ_g={o}~ve2Z%%%da|7$S6HkvDS(3QrhEiI!L*>
zvjFR1FzbWY5^Cn_`Go|{PIu*rI|g=}rBj)U>ai8NH!UJd^;!%#oth$Asx}utRXMl3
zmW5AjWyqi(3;@?^T!fJUB`GFzr7-YG1^UoC5oO^f;(x&Bxaf41)iabb%|JC(nLmhV
zDbE%xX#pjdmS}{6PNKz%(Zq-r)44@Rh}hL7qSxDJX1OJh(OP+f-mVi*6ZHJh3-yKB
zSd-ndRHtg#`c9bz>F5k(<6hW`&pjG{xv(Hpul!1T=nItwgp<)rjB&ZAOWvgf<iE;Y
zuVqlyhbdm_NtJ*q9&Fa(uqUTEFB12RVVgKOB1~rV-8w|(&6JgcR})(yu!Gz%zUIr<
zuf!e=l=2)IIiuf^0{hBFLX%if+c!<v$Is!v5o`nWhKv7A6P!ucpaUILZ2w-TZ?kfP
zxvY73daB9Mv?=ww@l@?&q3LHB;Y<y@)K(nh=S)%<%_Lnn4!X^>e<LA4LKN}MHQmH2
z6M3YMtZ-~u;`~#^CDcVp<$r%Ox1x_@+JQ|Ghs~s2MOGdaYaz1Q>~ZGj&CPDNyeE62
z(`n_Rf7jT<y#gp~6N~`AXa$RJicY<DAVGh@XP(v@Ls`O<70muF@spBLvfp&UE~9m%
z(yazCgtU=z*(AtOoGMVSA?!0z*~Bf4uV%fT-vNVVpk1}%1UX7i#3wU8bDo}|N1Puv
zV_N@B1r2#jrm_;w$7Za8Ohf|V8@!OdmM@JQX$7&J$(oU>`qH_}K*+$<QHbySiU|L~
zn>)%MNDjthYhNc_<B2=6A`I4F==wHEp@Y#Xx^wQG(ihv4Wrz}REX&7fVV!M^)Zw0Y
zV1deNXS37$OT2n}jdRH5f7st{$ER0ua+vN>iJVe94ynH~g(f5u)@aQZ_IN&DbPtU>
zBys~J!)I<9T6x=+idV<*Nkj5{b&(3L3VzOC3PlepKIr5gdAqIKNcI;`0yrYfKg3PN
z-9LI%S-j%T2x&<ZE#1~g#8@+jZc-=nb$M~W9>zut3P!HGeDR`-g1TtJ@w2^S&F^Mh
zZVkFPe1+thI=+OuKE2R4C8>i>Owp0CuV42a5nd)0^K)Y7JURGZ9$jXIJX29p_Kr<C
z(wJW{Xs+CN`Lx$1{eoT@B!Ui_g=FK)t$Bn5W)RaJsYT!IINsKHH>CZrf1(M(due#E
zbqqk6wS2tNS2^j2&nQ0o%#y_BAlW{`OKQ;e%h1|k?os`)JI_fX;-DWRFCQBC#nK#0
z{5su@!avfzI(>%j4IxVJH1b$2vuuib94X*n;eeIt^v%Z`oIyiqkk|@>a3ToW<>jBm
zNKQK$@W!6{t3UZ!GxE>p3&C&n0{jUc+V`<cex@Eu9ieS_-{{b&-!9S5%<rIN3>O9r
z^pCoFN6k{j(jp;+{T|%ezGo)C4rj=XBp$<7$Cq=aih|INca<c65~u!rTpl`9Oz8Qr
z<xOKcGWEcjU>}B=3!D4IMSoH}ni~SI*W?g1168)a+3KoOl)2`u6zw1IrjVDGN+?;a
z{Fi1<$Gd`KUs<~rz;`saHt_dH?6{|?0$C4H8oT)<r(#4;#>blSh_H8SCUU;Ja0ZNx
z$-r>J$TX}6p46TdZS>#)-j^Z-e-8B=$=aa2Mj;&h2`&;ZOc0ccWKy}a8B4fd=M2x#
zV0AB3+t>gBbYL~{(}$yW_`7A=R+O2b5TDLrftld{fL|eF{<p&xhWTfG+d5;7A6G8b
zq{aY`v*s8iVZ44rju(0Y?GJnU*n1&vkq=2PVqv}YA<NqtIs_Xm`hpQ%oq>s({a1;b
z!XDF40iA}G8A0NUz5k#fJT><52CyP&7YoIjfI8FX@>q{>u0Y*)09VR`M`uD1AT8;h
z5M~*VHq>>bcsF-&%z*~OKQ_GgyEX(vhq}(;qe;*AYUc6M)O7&bZQnrpnHyLHSZWit
z2Yzg5J>>_x?VZa=HMJkxw<Y=LE8jQqnxU4GCsm-m>klncv@FoH&dy(Gd4!ad(Fv|*
z<N*$vd`|8JR$p90byI}Amu*f`Hx|vNUf*Cyj+%YWt~y|X(m9{eE?OY?`!39?kHY1s
zrY;(;x7xmS7tv9^yI15Ny-|=P1G0Lb#(W$@bu|rn_0HAr8M*+0j$1<`-yro$Z(Kx<
z_CDQRckK^MqK|iUIS3{CUSd_do%mXH1HZ#i=ENLcIQsb-ux<0K@h=twVkTf%V4NLf
zBW=!Gcr18Z(qne295ESyb)Nw3ytl#Q0Gm!>_d4`Lc1mm*-aax1P?5u-lI+-@j)j5?
z%driSp2bFfOHM0EJZpo03RZwj*Q24$^1O8?x2$u-1uDXC`ZV_lN`XV4|9Dn^A2VMn
z>K5=};GQ$3Csn8jc3E->`r7)^g$<W|hw9xltzRbh$ERohDe#NY;tu+)66&Slj39tV
zv=`#^CiZhKldSqpXhl(6L#~76U%ieDUHQH~wsyRc;1Pif=#>(*BI*`!j}fju5D@Io
zMu2>kZ)Cf;zP6_FS3vO}`5Ih|BeBB8Ct<e6UmC5unO&=ci%G?a%$pROmtF3CIrrY;
zI!=H>=*J38dRu~?mRfqQ5p5?pm~K1!92^sSOgy$;?TpXYn<cMmKTmJ213!K=_UhO=
zZ$L`pmf}#KL!vHChfr7BzDvDkK#wJQ;`#6Xd56mI&p(H`nx<@o59->vBw^HvKNC;_
z3GGaVeOa--Ge(Bn@TZFjnSTrgIrkH%UFCf_-&cEIlN&~iWRX0C?UW0pJ*DOFYy~dX
zxyMH#U3ziph;hzD*w$ae*$cz^lIT>e+@isjj74C{Ut&M$8rs0EFA&!SsEWgx!fcG4
zGUtzMOFM0dQY?MUkZXZu{^E@Xr5E>Knf<!~J-Rk>U>B?m?hFwmvE6Ry!X1#GbRtBU
z)uy*DpCrm1i#;X@4Wk-`X06}BBGLQ_gsS-Dz}?%mawIFz1V;sJX&C5rjx64fwd6Nv
zO$$fcXLx;LQ!zi?g?$aGvWeNklwthM0F4hleBJD?`OeB(M#3%DR=IWIH*_KUu`{>1
z$nl|dcd>X@T8(W>zC*wx^P7)5)@-oW%={ADWL{Sj_UO&MMCz{gAJxrn0RF&K=!bX?
z+sc)rBH}z`?H}g~&6JHrZEkM00tsYa+u|Mxt3(a|8J7us?<hCgPTPpLrXunFwA>iD
z+==a+QqCMcLfVz80`T&IM{U8eY6<AWg0B^6Ff+uDCHCaDEHR|)QK!n=%gVh=`jr5p
zEN<z{CY;O8z{_P4)poQ5l$8q8-?x|uFLvVd@AU6m-al|z{4A;-M)vjUB$_^Ep0P^%
z>Na{Jw;L$#-UJ_e3TT!69b<v}mNNgiD5a!qxi^VXx5xHdu#EO_ysK-jy#6_Dv{Fea
z&wLJUoiH?2_T_#xYfa|Yb#O~@?X^BwwQKm`Cq0a$&-;B2PM~~_`t{ATS|D2-VS2$C
zbPK*fZ}syXEORKdZ^Sc8ncLSLV(0Kb;yevxY6(oE5X^Y95couOlV^_yd<;h5@e9=4
z9ex8<G@n))G-73$k6VH0OlRNIV_Av#V9<vy4LiijOa3k21C?-%b?M5eGQWA%hGa+B
zan=^IhDgK8yK-ig(>3B;3%VRn(1=xAW-59Ay?EHMS#N!VVetZwFnR_pRX|PAucU>u
zELXI&KHz;Go#vEOg<xqO>ddiGzPVP_(x#b~)?TC$I4-#|>nF7-tmbUo)Y;9UHd^NI
znYAvUWYMIY#83_CPO0I^5KZlrQIG6h-yny@GPgc37}2s`@@FuORYme=E7DW`x;*e+
z6%#e{f61S-8i4iU2$E!{$-&#tv9AxLZ*z`ww&aHC&$l1rYYk4vF)_N?Q7%hK%ByxI
zF28Py3Oty?9wpKLxAxIv>$N)TB~iMOfGfLKo7Q4N@24@-xI&;)Jd=zEGr%TzLH5@8
zl7w3i(I<HOG?HRGN!b*1spDVtV(y{Ju=~aP<&N3{3zUDTJe(uFk1)rHdO1iDNJ4)V
zP$3KR;ZXh7svm-XAv%t$TPS#<6y#ylq$S~uYGxR$gbI0@60j^uU<3}84)2iqQ|etH
zg-vf<v1bZQhoDB?<7GSm*Wyb!|E<CCbvN+x+NH`E&$-(6<3^T!$YP+q=9GCN?S_j3
z1BKGJ!z@t%kG}&Y;NO_;qyzJ4)!h&c`%NP^+fZ$%WWtV%2Gf(gCr*su33J%g(DR)-
zHkC>wy`gSdhXMhqH+s!uQ$fy5by9+`nK!rJqdyJJ_SH<j`L%%1EE@Ef_kHfxlZDbn
z@s|?n?9W4;#_k}=wQ+~JkEd|)YB>697IuWH;3!mSHE`@+9NmP#ZYk`!p^9SdVLVf$
z>*tv)Gy$riAGX5Nm}ost#3xZLIavPB31O5h!}l|>+&Qwb1F_c**;jv;4Az^9>J0Cv
ziKP{FTKM{8tB|T58?XRr{@I*q6F|HyB83#&W(_T0Coc_!Ai^FaK-;6Gpl+_N+T76E
z_uP(>Q^$^Q5012)x8TjjRYm{t{703)$JFnFC$U3{FkDS^VbFq1c0oNp_h5^5+xO0r
z@a-RZmx6gj)V=*VaAhvaf{H*P8I(XX6`Ko(OOu)Gjt-H-_o}1hFuU6U6vSx7obTxX
z%^S6<<EjpCi#E=8@jF+&Gp#7Jkj{W@*F{fUF+_;nu-#q3be<de^|2Iwg!)a#O&)zH
zs%>$@HztMYsP62Rt8&Ae&3AGZ$v$~!h}ejjC;y~LjwntAp3N`U_Ah#9Ma!wTkT7Mq
zPTzNrixfHVuDuF_A>A%awr~)}H2D(Y58TW$TYc+zlkMt<b!~r;CGXlBX!4El-v7K=
zWY%UjUcFeXI*o876YlsdG_V)LAL8qR!Wz37W!9eQcuX>|{}%|c@%*3>9*g5E4R<ME
z@Jw0DTKRh?rF-$Y*;@L2hNWx^@#;;+F2A(Pw&a{C%L_-h2C-$)-SNWWK#ggxf{v}3
zL}0RjHL<!0x~hb*sT87Z#wvDf$iq$-Ya&);OLwL0yph>^>8u@}<k2B(>GiW_7J=Vc
zLRA}?Yt!;^{j|dr6%oKZ!nX;RKVK6vMDQ~vJ203#aNJh|;G?`IMoKWz*bp5x>U2hu
z)0DS;<l)Kj=HA;^7S5Rki6vR*E<AXH52hyD_->wa=C();pFIgpj0WE%a_yQdgit5u
z@KrVmwniGLGhV8($QozgSZ;TP2z#`{@ssAdwbiH6JMAOmS9DBv>|!NP#z@LX@)n=)
zI7M6255?!^*jFN6BYJ`L7uyf*g^IC<4YK4VL`C#L3_lW_IlRqtt}Fp{VjBJ|LpchC
z1@A-49dBT{N^cfRxwgk$^2ziz6<mb;FXOgP<OKjVg@ROsQRrnSD*XiJueWsh73Jpk
zVgJ?`S5eT)kbcp!`VZh7sCw`;prA;5-q}(1%0~G3UM_NC(U=-Lgj-))b;nHkH_fQa
zxC3LlQ^|YAWX@rI?#&w=ks4b`&lyM22~^(Uad0{%EX7guVWpWc*F5PjWEj@Oyk6kH
z{uv!?&q9;5Eh$m&e7yPN7a(Y9w-XQDx=ljb5hgtDG`%Z!5h<6&Qqb2p<*Z}2X7Mn`
z9~#Qs%S@*$rJ$lFoPOdoY5%L_=1owcQQ~iI`~@D^)$ZYbauzx2Vjr-aKpUHL96cxi
zX-faRa2UlAj(A>Tuhsx{z4RZ`%d1zROM`!-T`s1q^W(3_*@3vKjKcc?n=54*srBfy
zWdX<~pt76S+e=hpdpU=xhGd<=jFN!DQPgtY5aYq!OrI0s71Pk$fxYDR7%NGP@vX6d
z#)5ZJ{0ud7avH}JkUUD)Y-o<;kir9E=q{itF%0|&B0gcqk~Qi5dBPqS0x_@g0p)Wn
zP2OmG+jfI9CMH`T=TUDM(pvMuzLVAegNUl-JhsEiJ1x3?BhbPw+Rh$vwcdh-a_s)8
zO1<5%)j+Ks9afcN-z#@7HR?cvyPqwv|Eq5tH{198p2S+^)_$0%>jC!T#h8Qm3r6F{
zk#Oe6rfgU4e-F;*O)vLuHw8jbz8TR#=ed6?9CwzF0_h(xmtX_0?;1NanVXVAA@jGE
zyDwC911`_$VUk_Yi4<{W`1TGV{kmYgr5Mql7EycE&L)CJytI`tY{_+|h?@En*(nMu
z+XjSa;CPnDr^XCyR0}N-N7bNu+~~uI9x{*+>HEbE^KHE2M(0yOJyJh18r?|tZesV<
zQl6=*z%IH`5cn#p{%UVBZ~P&F%X{(qwkgt+d^en?5PjU(MaUcntDiQ%2{C8*`s`vz
z^ZSg7G-o>-THC)!clpcU&Mmnq4uwf?@Vv0IhXEgH7c>WB0<7k&amB{_m^6HgpiBF7
zV&!~dG4vMv=3T98=@s)*I8;P_monYHX-3uf*x<PM$eRwwXc$MYN?l*E0(7l&rWgAd
zaKfIj8FWMLqy8zpf;l3+C&pgsV7zQ-1FbNrupA%ae_DBwhOOYyYLxQqs9tiiLp_Q7
zG5bhbqrecQvmdEdUwD#Ja>!#>96~h-l>wgdJfOzFJWO%y*=!6}%K{PmB^y+^g0e%D
zF&NS>G4)uCy*xjwb3O=Ib@MrGS?UjC4&SIFMaxkGp0&0q)thfXnF~7}2xnLtp&C{u
zcmYKP5Km!Ow)<jEzV%YMKu$a|1fmKEbdv{Szt1cRCP=*3;eGL22x;><jNgc1z((8f
zY6X%~{0#3(Q=-IA=SmL57{vaKORm#S--MjAOK<D~7t*wfoVfYOzxap^51$CBz9<d0
zjda>3Fr4b8WP?f(XjX9q=Sq`(DzG(##kiDyWjMI(0E8Sc5^zCu*j4QdF6|xyOmMp_
zwHbB6)Zf7CX2`?9-h8LwrDXerLOm$VJ`~-^17A(XcG0xjt%?@%0?&voR5Gc;$#;p@
zAdTyG&Qp;NrG-zQ#JUlE2Dtk$0lg7`&@Xg_n?r^B=vr=_p?Nk{>6k*>FKlQ(CGytD
zitnUP^^XHVDM=<R_I@j6lUV!jQsuA%q0x>?r)L@TC6^Gbr0$uhyY<MwnXk>u$EjbZ
z=^bsQlP&!SQir;lbK^BisldMh&@**m;bI%Op_ReVn7_+#>&#QnlkGH|`2mUVQFaX+
z7bXIy`E)8BI%L7PysguIrYcTUVSXnX52p+UM&tNU<g_V)lABwXSH}s%a%&xAD#S-z
z!7L{U9<js9Lue1QSkRkU5`TQ37oPBunted8Fk`PNPa>RNDr2rEfHG$?fW$BOg_#}S
zea@39{V7MQbBirz=O})+(^S7mp)M1z)nEVDNK|!-f^Up^Em1l@%kAn6+cR%)b$LqO
z;3@#dn502k>zKLbq-G)}2g~<;b)J{$R-6@_Id0jUpf%jahwH9X*qa0w)>`a79@XTq
zeb!qQGQM=QtKx@0L9mRlHn?S_uT&MK00U4xzij}Aeqdnp2!k|21lS_h(!^w=MM{nF
zYGIYtQ;}-`nnAiqeX8f4%%6rdtI)RK5}6kGDPX8))`!_(bJ*e+WsYhg%+2^1Lr#fi
z8UL9m+7&>K=!X(y#&D)X-mP6%&|a+*S*=t~r&V088CSX@{|c_Lnn+B;C1l^aYULfk
z((q)vNGGahB<_jX)gNjlA#XXDZAt!_rq)2e#IelA{fAXXP62$mqkXvT`rB;Hg5FE^
zBwP?qkxg=pAwcMJ(l#wX_cN`8Ak$lp*%N{zK{f$9J9(-8er<a&fawp4JQH#=FSrcR
zTt!E=2sz|yU=5qGCI3v4AxS`FklTkg5GTz=KraX;xgVPN#=dx~PD<O2KW!<*>$pWM
zpyFlu$QYGn3D@shA)^Ak;2w-(^`gP4N?0}zifMKnaSh7xcPC<{$~INp-y)Bfm)V3^
zLR<{f_qzN^V5_mX>UX{%M&ys|7$%F$3dl<?5hVNg25*~!6wf8Q6oH1+Amj&oO8XvG
zVcD1{zf?a9?x|c(moY_3|IhhB;)GwnydkMbXoAS?itE<y@(_>hrheiX%^E{)YijE2
zOU0Z)`G@pxMkB_zl$g2<nE`UD=Ah~@(+?t2_j_0$A2=@VmMU@hkif|LbJnS0u7(U-
zpp(G(kx#w@FVv<+4yQ_?J5baYtTH^UAFuoB_cDI};?WC8&ANn^o++0tx8f!C+ZR$$
zsbKhamwsoDVNd$R%4G8t9+MoQ--69yqz^4HCOkJc={NFRVa97)Y#0y|w(c$?Xma(l
zM!qeYrrWRIo)B4c7N^~~$f7Ac$HO#^i*=f(ePqGpgN-Xenr}aAgy%zjlkZ~|a_3=M
z-#_Nri+f{#rPh0b{SW99#|Jm2qj`+Q6{OiySKc$?^B^m0ZJujnxKfD-eMsKRrXdCh
zK>yic6f5McIU=^>x76PeEDnVoSB<yve+)v>H9d@+3zEv@wgW=U+cV`SiFLg`9gj1-
zv;<YcRm*KL9~rObF(T@4w%^uy2;S+kErXohH2yMV$QSEIK$r=w2c|nPKp=-qx+U3T
z;{-lfw`_0g<M0_Vta^+qn>FvL;hNL>)g3l-R+y=(dFcz6q(k<NgT*bUXN#*^rs~%%
zj0-`a*<U!+Y(v}MpmS)pUgF&h@hC(J_0|ZSrKx|9rBBc!=ydxNm8EN!ZCr(*^V>|M
z%0hq$mLuX20143F@@HB770qcX^fKDsWWMPm+r`l8X1-<;&Nw@BPjD{4%DU4gV~{C1
z4MsiqQ#gA%Ee>Bf*Kt0ab(M~Puf?WR8v|6ATZ0sZCGF>Q-wnaNHidzj(LBMuz-~9H
zEYvEPB2vP2mvJ4aF88N<t#VN8=yRQ1J6w>K9DRa{=I8Ij3_HY7!D2H*k6r3wacLTa
z3p&5|A<jEW^q`=|xGt@-Ro)s!mO=1uuG|V({%9s`KsGbz#x!rU7W{bDE%@FK2W(u!
z9^&apicTv4-f?=by&I$+bthi*hpXe?&$=|vG*8zROW^0L&qJxBvB|X42SUZlDf19?
z%z(aCzu$F?f4(_tJk!7*|H^=5O6AOF4D$=XA^tXrUB=h$?-P{M@>lo->btZwABD%Z
z1BiwJMPWW!IbKz-Y#xq#wSa7bU><)vs~qjR?}*B`oJAw4qcEZma&%iETs6NeL$$6{
z6c;x*4<P%0p9Jb75{e>Z(XfgdR4Y(jN<o~Rc`Zxd&@Sd(V;=P5BXqFbm*Z(oF6NFJ
z(Pa;8$T{Rm7aJvFw2>{RR4<q_ciqdeq^xwaRQqoZsKhs|$2G76a5`4{{mNLNZk{sU
zvs`J{>4R|q!z(iRJ;!jmxY}XV!DbP_to?Q*r8@ru%x3I+Q9{OkWxV{CMdUB0FN6u2
zFE|AAH&B9IqMi+*@vl!g6}x8{T2GDfDgUQ&IOzV}o$uM&=Ry1H&fY0J@)4(OrvWt>
zzPK&{YR?8`X^3H!uJ8%hnHXyuyKIu{^b^(|7Mj9XKP~^|^gfSA_mT0$4c5SN{hB&~
zX5dLxD0|}-*88wZHB5>Fr8GB(fUVafRYz$2NnJ*|&Fi^6kY`eET(eb)UK!L;tRW|*
z{Y7*dro7{FNHq4V1`ZA5J#@ScXyG&!odGJ$ZD_HZOYfi8iVk0ao-dj2&Z(fE_{V;(
zN_M>Wl<0B1|NEMf<h6UF^k9z@r9qn%FzmY@)RGjn+1gdOiN8_~4wfoF*Lj+3#|WVS
zR-bd}$)%T`y-?07HVU>{^eysLfEvX+!>`r~^FCTDfzn=6B3;t&FJY;Ep2eh#lXIX(
z)rTAv1LlpKAa*!n!gD&tF;u%zPPV%S`|pz>lEv7(69?my$cKC`3++#&p!;hE=IMP-
z2|P~gAKO?}wMJyc<K+r;fjHDMir+l=+adOTZTf7>($j+3irto#{4S@%H8?cq9T{gc
z%0<LBTo72EGfh5dDK)Ix5#%7yPiH}&v*Wpe455DXzsT0}={@T9XfnHV?3SRAvPJ-+
z!BwUGL#gJ&w+ht4Y9WKCCr^Wso(%!aO;N~7PCCHVmO>I3m~K*edN(i<D;#CRWXK8^
z!Bnt)r%A3fovd<A@F;JOtF`J9!9O(VzmH`XGz@QZglAF`$|#3SOJx)))DlL*)@ra#
z#VSbuc`L}uKQ6j6wYwv<10>4Z*>)C~kC2sryr;U`!PPLP3%}?FUOXRvpG=B9&86}-
z47*ckaU@dJ94ENp7W%RMJ?O|3&vqSqsyP&}WLRJ*l^PwRvn^OX5xI~ZBQ-{`yYdde
zmgyf;EPx&mRXmBUaEs*}ogwiUu=<gD)D#~P3-i=yOPe0)<0uli;+c{|YI&LbJ(ACR
zg-K=c$eM{$hY5)KF<?o`HawHL`D7ug=S=?;2rABPn!+(*AF}K@V|W0ph7_&jag<4J
zD1WJ=hu!PKFB1*c&VjUfN~s;vppvBd?^T$+dL^p2-g@ocN!;_|m>a5F@b%3zs064t
zkx48dw$em0_wvNsXWTkW)%%E^I6Ah_L^mnXsCT`EdVt*kZ0zFL4v!=N-9RcGO=d-K
zaO?J{WS)uIN8M7|@s9wGW_$k~GK<%W?$>FG)^be`DqwNYv9#jq-|TYi`wLKqsSSOU
z)sAq2%Qb*ee4Q$5#pQ+OWkd2KWuq)>>#B3aQxLb=-HpiG@4euQ!vgO7Q}OZtA?zK4
zY}vYX-Ktr(ZQHgr%eHOXwlT}LZQJH7+qQ45^~FAC?;Gcy`={r~?3o!oa*Pqt@@>!C
znj*sS{b5Otq<!Q2RY?vM^flH4$^S|Th~Fpn%Do6&)lpP%j(ob`A-9%PO*^!_yXlwq
zlC@o<us9TP=_jqF(~=E*Ss_o|UchjONfy0;0$ANnOA)$_vD0hVjqN387Mw~U6oBvd
z-kQ;CnAIGPh2!_WpSqEMFLg(e3ruy3Ng*h={b(0pQ-q1Tr8U2km|`Tz14(gSR}q!I
zfFXA2Q3j~~e<Xi`t(d>2*?X*PwAcM-B*%xHfb1^4*}qRjk%Ymrbsa3BqkamjQl)Ru
zT($I)-f6GJu9=k)0tbZh*!VJa^fCYeE1c`N#1mCPpucXesyngum-=z|3lP!k(6?vs
zHzl3&{11iyRoRX~aHs-p2z+Hb$!{qKbl;4Y-r#|JN1s`}QO!;UA@~C!dW4z~iNPfb
zu0s(7`z>HS!ytYNEigZdK_@Rh2QqddWe^Xx;mw|@@w~mrjn=cINzyp-kIJjH^Y^RX
zhbr^hemljaRY$<JSnRzSG{<$-gHnv9vcLUM_wQJy^>RIIh8>UhtZI#+q37WF6%LzN
zFCiG#e7Y)r%8@FIn@e+q+pShf6x!bwantspO`cxqJnB6oUkaW$4fB??|2z2!eB6<P
zCrKZkQ;&k_Ynqcpqer9x56_2;_B>}AH)yJN)?6_G@7swtfMVKQv@56)l((S+b&PRk
zr}%OfLo&K=&;4cW&BFdpCAo3?xLq+=>DSWn$W=3W%K&#PUpF|fLA&jwX?u<|lCBkq
z8~wgr>@{Ymu^rq-NeYDtr>g&)+5^nE)ge)^Yeqn<$8F=6H5A9e+4Y2QLl)ho^Vx7d
zUBlh(M#q{R_9LejwVHKShloKv++>3LluGiL5fa{eE$C#qk@I0M%vH^pE;@1h?A`sr
zwSP#@Dt8C{hJdQRWwayQi;xX<c#SV`wuLtem4zqM;|K$Xiyi1C+E{F@dy$lFn0$ia
z@`=T)Rzyk(i&KFVcF7YU#zv3_X+OFVDnIxm7n&tJ5Hn^n0$dhE?m~VLIyk%YsvE&y
zw_*7juLY=izYn=4!d`5eMtPEcN)AcgYQiSds(R5Y*NX<Mr<XLaq%Wpa!Eh9Iz5km?
zDP$pVrdX`TNfnUzcLW(o`4_y9u&}itv<o+B&xDW<Kg|?_+KV^=IV6lJ5FDL_0!6w(
z>xx?-WPbvl6n`bF&P5<uUQJgBzTBYmXul#jdSw5w&nt}e(uIoPG+^!O`E=Zq$J@mZ
zp0*U|RGq!2T}oCou}J_CaT4ed#!DG`lIRfTqY8!airGEs3Xir3)d^-V(ADev&qr=>
z1c5qO<5bmR0gHVKzUj{!Kg@DKiz{gH(KXZMNMxkBU<*H5R}f<IY`BQs*HZLs*`JLz
z33vE$6?S2kHi$jJ<pp&Zl)0&`fUtNaQQhGl^A9?gem*GTe1dr<U{MZs>g6illMU5=
zm&LK&F<=qao}cr&!?llyJO_3N@2vzoM|KGRS&f=Mh@}d@2(<zJ&)VYuS(_FFg23&r
zHC<=kTeQuRR<8?1InbOOoPr{c`0<%Q`_HfAa5@ec<UxRiA5R(RL4t+9hYG|D1w|Eh
z;mRklHPyuxdvK_+;~1ZibmmcL95(PGXGv(F`+}p(4?O_LvJ|qijI!2I*<ZU9@<M?}
zZ*FEtW{{jWH$CW|LHM5mn4BFSga-;%N?;}cNO87drx*EwT2E?z9vb8w9jsUnZ#@|i
zWTY{%5O|~!2>~+3oD3EjdqD<>s*iz!z4(_B9<seP;JBD`u9pJX_;mz-ACM3X&Ele=
zKXBT5MO%ajrd`v_ZZc5XBZhGC?+5abg5OTE3qto17j}B}(B)wH{R^p!K*KX}s>pvF
z0ykVLu1+@@N5>ne_sCC7{6O!3IF<s7>x9l02M(KHNR$z>`u`q_PW+Nus7g0|9uKJe
z%FC+9?|7P$>mz{Vd)GwylU*Qh+!;)SRIliYsJ?%*h10Nb4=p|PwP>>xGY1|Se3_-d
z#5j-(LU4;5{F4;zQu(R&(h>Z-y_2phOCB^zwLQ|6=OukX-k9bEC1O$zG;!D50tYwT
z51BK~6h_SdTsQZ+w8#ovoWNMp#B1@dXpYoGSumustuqvKOugW?@=mryP;vrN)pcWJ
zSUFm%3>au+vw4Qc1hZ65J`(|7?PF2ZBI|mib$RWvY{xwHN?$D`OjyaQ+oQRi;<t{F
z*eF(Ed$B$|7zPnI3t1(HX=UhlJkQK+p}Wg3I91C#8HN3Xhsel8<x0xWm(CCSh7bFK
zk6ZO8`!D{l#0lj+WwVyXbcx#T2a+6*v7T{jH=Z_bO+Ib5IZh<jWHohm+BXUs0+DdC
zi^YyfQ?D?syIqlP#1Bs9W^lq4%3F_ud8v8pwce5x(*~|3nYaC+eYZ)*2wNDwzKjJG
z1@RRw^EA=AuKL>&FP!@4s+@yrIbH9Z80M5-Gi3b(x_RC{&YFA4Vll~eVj=_=J-qI{
zg|}C#>%7>(YsZne!d<fS{NKq$I@|JZF?8{xJ>{efX1y0JriWdSYNhpT109ht*VAmB
zmNssx{P7;HDwGQW0Y$~W_jpFvKvGl|4W(GcNQmgiSc~|o#WH4^4btaF2fo&q=MwuD
z-^PO>3wk6?mNp7bPF9re07Xi9pso9c108}?Rm;XniGMjg)ZTcvkQ;Zk+t~Lnb(f4y
ze(7S>laC~7Oep`oGH!HK`MqH39x{pB+v(w=qc8VTIMohxxv)2qb2)Y3+3gO(Ea#f6
z_JW5Klh7QF`s9T;(}6MDc*EEhUw^ULK0<&NkTiKSc=ZL>J@3iuL^H6sh7(?T1N0;@
znM=*n2`ivfBA%VL!M)W}bqePdQ#{hn_^YvcCkjz6Ld(Ob?*;40go#7&S8WhPV1tG(
z@zQh;yR44h+TiI?d7SK4<#>tw<DQi=z=C;>9h0irHK?T$JP4DCILN6-rIq>{0ULH%
zF(^|?W7Gayvk60>r1up4rrK&ZEX<)EuO8QeEj)Y4rW3;KIL@${y@HD5ldJisJiZwr
zlW&&km&IL=LscKNO&l$U%+{!v7pm_?M)T434$|P9gRCghGz&!$hdHrze5voGdS#W}
z?7mZi2hmG2Y7ob139aQ}`*&Jo0+ppj(uA@V`lfO>kL*^x3+O}>ZF#&Z7V=+_jW1(&
zmc-6Gye!+7Qu#-D>bUvX>2ltPp?>ECZ7}U|Jk~JQ<{p1BeqbCqqS}qbl6on_(_--w
zsgZf$K<6kH{3~N$#O+{0noH8Ejj{yV1fBk`i7xK#hkEyU?k;NIC3bTi6>rc|2f9F;
zJ+i{{QQ+P;s`k4i`*i)cUFk`H-j);4!qSwo1bdJx&_?R|+^hm<;`pR61-g5J^uq83
z^Ky`pb||<IqtX1Zode&j(>>w$ExhPC{;wXbH8irGuWak<){5cFKWF&%x<PqCGT8J$
z<Plmn$2+4rrWu&nfG4XSCvRvwkVc7YveT6F+4qg-U>NfTcx;q>HpuhY%Ei$vI<DRG
z52ay+Yplh*@UtQz7`uJ$Ujj_ux$(Yss8nEV%yl3VV{!JzAryI%T3+oRZfPy-L)~J3
zt<$d-^a?%sji@ebq#U!)2$RE?H)|Lr3?u8O9gK_Ec@N9=0{h$u3O=}JYO;;b{J1x3
z+$@J!iI^W}*eIx4eeAM*XD9j04)6vc4Kli~-?$fAG5sjo+Id9?&x4L%!KOX})!6R%
z4f0GEhAk4?`O;4zuokLY!^G6;aetSmo0}HKuN3D?gR+50^)}VG&mNnDed@A-uOF?T
zbk)6AP>ItR##cn!CmUBaW+$UEo>$h_Q3L{>mQ``^*bOh!;IPp}iK|>B`8xPGq<PL$
z7n&nyXBv+pS|pq;<&H}IGLO)WE~Pa%)J<GGTXKJ_F!@LNlnG~Q`O1&~-fOe>I680m
zSfREkdc~0&tv))hc2zvYcWnPnwfYx@O<%Z7{p6E{7Bh#}+rr1fi~aqx^R>+VjlSI&
zD8{Y#jblvbz@9M1aP8x#YoEc)d+e>#jVd#@`t&Z|i=$oL*Q3{`rQ@fi;ph3<*~%An
zx>)2=PMu?nZ^VX`34d0$w3lMdidAtU#00C%jsUMtJhv3s)>^}F5SecF8DDwCxkK4|
z!1<-;Aq%YorYgo?H|2!H?d9G!2i+docn5>A4Fi?VoA*uBQ6nqTYJO=?cMfpV_i*X2
zV9_6eOkcTw@no9}s^^Wj7BuceI5LyLpF6|oOv&qIr=euigUO=%6C0FpAP<w>`6wi+
zDySV?o7X$+ayMmGE9`&u0NLN_8W<S$F!3T`b+#e7IR@YRmi+X_aj^ddijI2+`no-5
z^a-wsf3Ju77&`Ek-}Cm+IhOsM8jUK?db;n8C)MYKco+d_ndoVk?Fk^luYDxp(g{p2
z);5Fr3TD~{R;ke0%w5u24^F7L;se_;D+t${d<!JA1=gu$W!pL%Wc1meo~8c&m)+76
z=Mw)!=8MBOJ(jdZar`W~?{;RJ@w(X>$|RDaeUf+9jr)8|O3{5lZQ<@5{>7KDaU4^i
zPGVW&y`jUGVY#RPf_co^7rrWSe}V?n4&56MCg0^-pV_CpN|YWMA+JfNRLFIXIQ<bV
z9%b_pOt$ZYU=wz`c)@-#2YHt)ndjwqYVw64J4f`(;X%!u(Ti>m^lXT{Sz3<|$1CpC
zQNig!kB|9>Px=MZ`~QI;ZJYduAXUU}@bct5&Eb{`ov?ReOrJ#igh+Dd%F3d?D(Df&
zLM`ZX*vKJ~P-)7{$vz2|dQT+qVN3tC&bk7gghbv=1kkEUJf$HepSWDnbx*zzi1O*b
zPW*EFFw$F)Wv~A&pz_<HfShg2p@35L%t0kvL@hRQUC$1W=OND@$1TCXDK965MidEJ
zBi_3?bjgvI>#C{2)M-ekm8lg{ha-&l3IUY}5zo#$Tgq38vT(UvxP`I?Af|_-Qn0#L
zd1t&0Hp44);FqDYk=cB)B{Li<|Dwe74`)j8AI`MdFLqb)Ni)iXc^~<U4ynrrpwXij
z=>r`G?fE+Z5dS-vFVi3QrgGKRUVA@37c@NW?{Jbl>zOz-=DUz};PStCsoB1qn8dR2
zXn-v_Wzl2~Y2f>s6QlO@*bQyEsUK`HT*)T`@m0=rNi2|Ax0%;?knh=k&p$6+y=-Bq
zz=Lo@L*C53dl`Hxe8n~$h~^)+KBdglR$z?Y*s-Tx8{gfS2!1iqC5Z=VgvgLd9PJt0
z!iiDf`JuLRcIYt2d@_LlhzAhq5dV;hE)VosJQ$T^CP7LplkYUD!k>g$rw10CAw9$L
zwW-r@uC~gxU|RLPU$=;@AVfn2v47cR9=Y8ehq(S>6EWRNLH=bE5#FPLguJzP?4|!B
zCZw9j%2VV*_Q(^H_ZjvKu7on2ewtf4nf_YY5NSX(i-y~K8T@I5nK)+v^@nI#BLMQR
z#!n&MCvAuW%N4d?_Rwm8k1t~1=F{-2pE(yLg#HQ7d$cw7j9@RpKb=$*!Xloq9vJ_Z
z_%QnLBR-fAp;tf~A{}pSrTo5jS3qfna|pY)vv@wfX^c?mtNm&IPKA@1lg`1%&$u|6
ze-#vOZrPp*{oWwY>`K<ApT!)Qt>6U&(ClV9jL2<<y-3|^RPg@wJm*v#))vID;l_+k
z)A+~T?cGJ^nY`;ql0c7fU?R2M54c7EF_f6CyGB^(ZzDWoOApkDAG2FjHO{wTwvBzi
z_cWd@6e1e;qXgAO_GiVF&c|!`+V7Jvh+TZ1{pR=)^W6|;2M?xW-v)lF@J_x@%4YT;
zR*leYqi?X#b}K?`ngyKnUJKo`X!7paIdjzIk8SSxKv}`~cl<SEjVTBB-(i%k=m{eY
zBx}PV1$NlPqX_`Xb+7VyNKp`=zk9E1II#(0_#qI5MD_k95G^PcJlQ#2+gdXyLv3(r
zQey8ab_{|dROvzxs(UB^EBIiBTi^KA22bRB2h8ft>Si+uAzz6wW7WAy4KCOtzq+E5
z(nj^L7+_5!o?%5W3_Ash_)u_HaKrhqO&<46%$|qDK6k&CarJdbBx56n>SO9_9QG%h
zDcQ3Zwu??oB<6l77E125OI7*y3D$LG6ki>cFV2z64DTOFV((u`0%tiBX4+w0_NRRi
zf7X!664E`W<!)9AL6{KVI!z4TAG&Z`W;(X2a5P9+dorP>@Y1aw{9lFpsHOX;<o=8D
zBz%<)OfcVG_d4kfSy}<!S49}iF~u)g>3anvyc+*CgxF$*whT@ckoat;sQqFV6Y^pn
z{CB7^4a*2+8$1>h`jCOSW#IH?9uiaZ`e%qLe)+g5e%UjN*e;{^-*@8GFnD>|+et~q
zbC&IEh5b{oq#t>k!<-Ji?Jut~iQRM4iEi(Y!y%6<bMR1iPG~YM;aMPR^b@p%l7HQ^
z$>6<MN)gw+H@22UzP=HQG&_e?XPZDEj+)x{e1)I{I++XK_gOvA{MzG83rvVXYUccb
z4J(5;p4bi=+zOy>C>{<#yjV=JHT0H)j_yK%QK!KdFTeCye>$>g|CkeKn25`YY1hW$
z_>k<@8ULEB7hNcn8ho|BybOV)0`@e4(J?!Q1)J%BNo+_p8oKC|Rap%<na?hHb$Y$C
zK-zh@M7}IqFSIsA3^6}xKsRD+hFRbZxqIAjPJv)3-X{zDyMy7ZGwYT}d*vhDN60OI
zLhmIz_Z+Pam2@F5F#vTQoU^d3_;wXTdQU-EF?mHc8?1y2_^vV~>>BuRrt<nt3216h
zVp}a;;OT|>SZ8*NqpMBhWZP;`|Dx7r&M=xr-k|XGQknFQzqN50PhDGjEi(!J;xpm%
z?ZVlV@x>91jeP%v;?mvNdyIUC4QxEE)Vj;K+d9y$38c8bO`*_1dt1fZlc3SmhD(C`
zwq}2MlBR=;%!|72#lqPT8>3fMV0PUWh2qRIs;N$Z9STGwH<`2J*oiL~qUI=bK9+2R
zg*Ktj5@E(2E{Zp5aUUV4<@IhwMgWFyeL&CWig>zPdpm|Mp??JPBw+I^)U26_47n>L
zEk9^ZoBI}K8vm#@4R)j@j6u`hRI_*7&-0w<WQ(<u{-e=@4vxMsVGU>~h7cQ(^8*2{
zzjgKR?V{rN)lSHrJ)vc_!^U7gu_aN2EV?c>YeI)E4j_ri4FWY}iaq4<@mEEX(k-?C
z35CDI5gHUb&f}qB`@b!cf|i=m$7!;|edf@=UCNTmI|y!r?(2U4eotUh(JiTnIs%GN
zRJ{*0TiR+(!%<)h%e}#f99uMG8gUMbBaHBz_>7AwaV@xPkJ{n+zS3v@#k??L`}rp%
zW)Of`msf%NK*EMMgYFHAGnHD0mzAqg$%od=n!Y~*gt6qg0t=8>w9jMw^TcKD1;53^
zp8UjME2f0+M32GKJXZl*czeW~#p@`PS51;L2rV#p@eGs~bNc3Y^sYX8dOdls-NWZA
zxr4is1a#AQTH+nQuA(@AD+peZSD}J$=^ZLUMEK&8Z>Mj50fCO1D_2A|n0yad=dPSl
z%-8$*+*}5}ek9xJe(c%}OVuV8WD%dvtoq=!MGE#D_R5WcZ)_lyQ@z&<sdb5eHlIhK
zo2|!ZZjjA0@W?|IUo3g{g`{akmdASjz~w#JQ_DzOFM0vQP#Q1mpxAg^r{z$9=gESt
zqKiKAkS66>_+?3I-sBj~;fYD$I@fq)!n(NkQjOQy`6cWRD#4jVSN$gm1S7>SNNI(;
z%2>n1O~^YRvQ&rP%K~!{VyaofYi;)g@WW}HplKtfjEazG#uj8e_g6iZFW&U2S%fJ1
zN5LgoKJD3bg>8Ssb?~pqIU(Sy?ScIXRY+_NVTSyXAtLKZw7G%<J5(v^ho|`ZEIY39
zwLE#VE_hd?9nP!t?z1#+cN4SANLjSEP*@0yg7pz-vr~_UH>f$qX#OAPb-})+=+x5-
zz6?+y{i1DT#AjXoU^f)m&W-Vc6=%+!klnK9sblDV6sa#o2h_J4<JhfH0+5aBc7pN2
zMzF3k;~1;w&6+!55!Q|6_Hons95EAjSAG!6t7DP+ZLn#g6*KLgnfcQ1&r=7P5Z5_W
z*Jeg#cH@!Ek1TJ6d34aZU+9njkerO=#8Kmm*3T6fYa{Qwi|h^BF*;KA184k+*KWte
zS+VciOB_KAEw1gY?&-39G^SRey{BedxX;JW7=XzjDLxa|W7XO*I6P9OvY_V=wsM(F
zSz6K~H!JLrs0-@fS2U21e$}X}Ag;mcwP7D7GS=87f8Tg*qd(OuQbRGHTxtGjr){>{
zGp{d#JPq!%p6=8^Cu}!j3qjz%C+33$$uIsVP)XhtX{f*Nnn_1HJc-zy5A?5ah2s%G
z`NuaQvZVd6Qf&*or#AXOZ4;o+*9%;}yLADtbD6FDJp!)x`RX?hH#8h8dPFroi0I>1
zzy&{+iOYX16MZ~0HG~<k|FKMX#Z&WAB2rhMXmVF|?!K0#-9sEi^m_~OI+I1IXf7NY
zt>#4Mw{eX{;}>D*ChuVZ)DCemW%S0eyZxk1M4vye|H+#SKo}1Fn>V4me*)&^`tsq#
z4Jpv-^!2@R8=E|@=+$F}`2ECVV8N~`{4MG@OT~y0^Hx5|G$ar86Qmga6Qqdh{eJ~1
zn$G89pZa0zOYf8NnUd4z>UJv)bA$^22~ckT6QHR5zXO!qp8#bt*Hisdgc*Yy2j8zv
zY)J_JKTe5s>$mvP_WyE9Xv+6fw`1um^=9_wB9POeZ%V%zDu1j2|KGh5Vvg|y1&aR%
ztAvpkS19GqEDm=j%N7^1@x?7<^e@oY)@6wgg8$eg=v?+f`7i3XP8G*IO57m3oQ4$L
zPpvBMoz$E5Ebdtp+-Swe(y2;84m1i78_G2+UDR%t@RmjR(k~P|C|pDZSo*$KC4So5
ztDmy`{%X$TyS#j>#j_OZSqSJD>C4PoX?$_tIJVz7CYXV~pHq-DDAR4639Os%Yw;k)
z=HPNTh$o80c0Ul$V|O4079-@_Q*WDa$Kb-HyGVJ~Io}W76!YMw=jp!ax6xXQW`n*A
z#ZTO5#=N>8H1(wYuv*`{O|i{vUE4N3tblHz@|~}-dByo1+ps>zJ+<l$D0c4DD8mTA
zrBU*%pT$mfi3;6A4mDJBw@!;cm2l08B(DvavhTw3lD0A5-m(_<Pp(M+Rtx29y?p41
zliRl)yu<$l-IjAWBj&caVC-+pn1@8?=~GGsf`h?CE3W7W&{+(zJMkEiM1*L9!KC(Z
zjL{c$(Gd07KBf+54y`GWbByv|$Blw<7_?N~L0)jfnowwAZx>`xO<USmLJh6XWrbs-
z*pprRTPGfkjaX70-y7A!al!{P){N;WGv3r_T(q`8xUcnb*P8Dn${jbZ^eHs0*GUOi
zC)exgT;8gW?l_Cxs^7?nTiyX-LW`&_vkJmgcyD~pKGuO7>&SQ*%EX&cU=C-kpRIy#
z=I@tO()LBnrk`Lm%23cZsA`nc-AIDeBXg<51$7_2MOJ#lj(-W=hFTymERRK^qro~~
z%-&i@IBs_zQjm_H?rC<0FO>Y@j8XXil%jf}cV8-bsIN1LHK?36=r0{bX1R1NQh9ZY
zjWwLpSdR0m_?}35R)C(j(nV~mjF2kDY;@Bz%42+>uCC$=A&txq_GRT8n(d*d!$WT|
zFxx{*k0PbRtNs3&U|=RNF*A7Q*oUbLe*+_0gp#Ia4JNgSjX4)1-J?_jB|B5i)3GwB
zqhPJ8yWt5UMa>XIdJH{eF+_@#{<&gZ$puQ9pTuV}KTAdMnvK!FL*(bLe`?<_YTpos
z+#Ay!K-}FA#TLm84d&SZPhC@0nkK(%!=*G171OZZeWU$cqJ-M>`GlO^IZt`1;iDAe
zOEtlq4i}ShYL-?A;L<2{J;?ZYEeiBj@U7aov5joXx^Q`t?#+lNHb=CXGc<0ZVaUyt
z3UhK9+m+RjI?*_NLTgYk#{)r{c-*W>y<2d2>Go!r<4L{ZzHAoB+oc`z%m$P_)u_U=
zhu)V>r9gJqs~T8a;OSB!w&q@%Ce>0ke0kwd_<UhY<iI(@IYD&vdHtR=Mmd4$yxJ2n
zeO7UDp{(T8tS-`kd&B3uzeVt`gQud)_911HE_h~-h4^C7V;q`E?y2X`CqWipOhVV{
zzS%IM>87FA-Ky?JNrREHKy2E~t5;;ND^FTr4x<eA@&Xdqb!)!oJDZdFK9YK05vZvR
zpzc%}mbP6rk}R8Vu=6gc<>nQf$-+W&5r{VCmK!li{AyXPSe${wnm8TK)V5ZaHHQg*
zcnR2$;Pg{m+d_lpV2Mozs4$#%Phsjt^jJsAfjN#K(EUupvW1S%st_PHzX$>zE#1ts
zf_P0+U1ns%wyx5o9RnYZ6kaY^?z!3|-rM2@-fChl(dS=w?|4W(byqhcx4P8Upg%`3
zGdeW)*X(5sRJQql4nBKnQ<#1lhc3X{ht&iJVQPp6VtLMZ*H#h_Q`*YO{PChWJ@cge
z3Dt^`g3^uU2Oc6pyl?-04CzDwg;bg~djr;o!}v|YqX-nN6eFY{yL=Hg%O)>Ffm?6-
z#W4@uNWiDcgf{y-oJ~;kiL;I-mjx!6H=Az`=9L~30)$H}bhA$X)e)17O=g2hW{XN<
zo0?OFN&0EKd23rT8T_FNI>P5W(P?-YhoOv?o_Cz8>k*VL+C}=p794OgPKS_3pdx<8
z*8h{r#_}p~LW(LeuALDEDA%n1N+WbeiLXw4GIjmd$YHLN37=^(L*&`<=Gr7(8=^F}
z6jqh)N9fdu<W}`GiljNuxjh*KgiqC6)}1|DC#@m~it2&~1+i~T5jhze2N+w!fCg%m
zm@cmYOJSjL8q2*O^3sMjz6Kq4D!asFLGV5`4++zIs6OrUTZ42_s+C@f-R`pZ+z-z!
z?fLPJx!*AB3d5baFDJ@eWGNgS=P=7K@BemmGVm+eaFLys*(vkHk=tzISrEiqhUplL
z&0@9icnNnD>S^Q=uS7zpQu~*#_Agq&9)W3^b;3a>2NstAEjDl$AQhOo*WwGJj_Te2
zp3k*x7IIq=R0TxD;#n`?AOFFt8;wH%9rJmf(_d~t>O4`2BTj9!UC|<zD>DE<QL?fn
z)`g)w0UWaynQ+e3<@iQH@m!=r;qh)k(l6D4@jN{IM1W~t3VzDLM8B9aeYsEj)Vu7Y
z?$05DU2rbLNWupZgWs|tl?w|k3@g-PsbA=anc3IQhREKcFmTeVkfgW(6}9lhHg$;z
z{yOAOc18qX4}7zMV=Ts9{0kJWr+yw^4LhXRb^JaEaoTjmHFh%Kl*?WjY6B?aWsxd}
z^3q!I8gk{qcCq5e%BydwXtqrsh9@vb5r0dT=MEBG_A2LU1|Z`hk^VxpAB)Qj#mc$3
zdLB%kRfqyke4|yWl%W4Rpx9C51KwvvJ13GNC%{~w`*+#1Jw+REN>+{j$=?dnAvm{g
zDd9Nz6BqC^uY`8Ac6?kse@EYDu*26pP;#3)4nqxi`)Wv<sXb?>uDB54Ylm;XKj1-Y
ztj<VAC|;y1uPr8{&eM7*5Q1?|WEX;(9C_Co_ODgF0D1hn1$7pF2E#Q@1tQ*pIEXqO
zU#4dQ*Z5y3s+-i{T?L1bD;>ak10^XKL9dG&LuCJ<s}HiK#d%%xcKC9a)bt7bVQp&1
zIkJe6wqa_iyr)fJ(}C+F9A{L<XSv_RO8wK{;|kA7G$ugb|BJ4MGQ8F524xmqC+8;d
zU$bXV{76%1JfI2N*o!zCur;reC{H4;3o|Dg2r15%a7mGErbra#y4+f!xf6_Ts>{jf
z-U5Od<h4kwoz>kFXtj3vsJz)<DPFdZr;C7a^B-hgpB2$MZ%9)G*?aG0mm|vm<Au(2
zoP3ml8K<QDWjzJBfv@yy9FpJhQOJYlRG*;=ag(N7je_=xHwQohnQ@9_yvtdA;1@^Q
zET820g}|TJa#xlTp}U%2(j_W%!20wou(j#9tK-b_LlU0oZVR>MnGTeO6jEZ(;V|5A
z&JirEIT6py#E3{Qol=u!%wZD_T*l@zkment=EdClBaA{_ksnCI#Vm>@26mHPJ?Ce$
z%<1uD3)O3Y>w5?n<X6s>?*s{&v{{xINfOE(4$?qrsGPiv{~fQ^em7A&IgO%svu`&!
z1z&#Lzn)CNXg$nHYwsHyc}O7RXKG_M-!*ramh6GC!9JNknLU{It3b+KWZ3+BPC?9=
zONUNH6f%sY4e^9f%5JujW9$(xv0}(D32W~!_JMWwOs$ZDBYWhWhwDKruV=~o)V2yV
z$uf-BxnN@1OU?rj?&4XsK{cyD?jOl~-_I(rk$oLdf!qpVbU>lw)BSKjG_u@n@_)gr
zD_1?$u(~EYTskhwhOn(leW~1`VgNN9z*@6jU0v>>HH2C|lzyGaT3;}%Ef2Hl-T5<;
z?}c!7@Zh!kT|HqZA&}Cr0{A!|9tIz@$^fW|Ure>)r)B&Wb=6vaObd)Pp<tdsVi*fF
zyf`=idt9SU=YkF(7{=Eo3%wQF=Kw_s=!Q8jCbeFcoj8@F4CR4SUcSJ3zj(15YCgjD
z{MWAa7X#NOR6@S`AGHN1?yphb%t8%y{3Dj*ZPG3NE5ljYTyY#4q%Malx$^_%*#>B4
zp39FvQQI2D10j&8CvKzOB?nATxX9~`6JftT#6E`S{LmwG7;<uDxEaMW(9N*74$kU)
zFfzspaqgy#GQTLVvwTkdZ#>NC_{F@?56?v=MtdGvW|%2YM_1O{G8JXjOqs+hR!%ED
zYvGE^jCXt4@JlgCJYY^*w{aW5oe*j==!T)iGp5>i@#&ut^#O48T2yrEZ!6^PA?d7a
z8Xb}$xNB#l{xpoO8A{IZ!FnsgO^89-M<hr0cY|bm5ZXWe^2)(74b&Y%vbLL^rc5wy
zfN-Xg&%FrMltYRU$<3QxtG=7s6Rg#tLBrlSHz11=!HVT5hjz_`9H2h5UB+%HZnBE_
zJp)Cq?5LND0f4Bv&|n4$vtZer{wjvQSA|21+POoc6L9o<g@@=1eMI6`jJ?^Er@`XD
z-Z;T>V5QoAy!-Ho;;B5hNtN`$V|l@zKhbQ9W%lq92E1T%SWW0Dv1ZcK@@TW=VItqs
zw3#Pll@Ld|r*8`h38}l{VaOdA#?Am6_y8gcq6`59Q!E<2psJrKyQ4UrWw%Pl5M&P^
z5d)Y9yGI~L<W2-dv`b){2==2^I2Yz-kRIZjiq(={>BtwWmz{?yO3e5}om3}CfVwzY
zqKxXB=U%!6L<nz@k)Hb&X)&J|IoKtc?`uE(6*0U|Kyy^LQrS9dl?;6!Agmp$1hO|w
zU%B3RcSHIk`OrdqI7b~k`+b+1zBhm;7e&Hrp`CG-C3yP+v{i<+P8(IS0SgW7lrJOg
zPnznVXp^&=ZPgk~GFDKUm73Y~sxJqv9kq*O(GRd|aB_<${8NPu@Dofkb;O}?KK<n_
z<7&XK-R4)i?mt(#)8#qz?u<EUYo<}idEyTKfA`38vq(s@D0pPCF+IxpXJ7=e`CA%i
zD%awJ$zRhKjHHYM^E^nCuLUz!S!r$dJ^pyqUsY4!;qPelskjBV64L&QSkLN!YUr*E
z$VAB2!3LL*lP$}g1m~Gf^*S_zD#I$?QeT+_KuHV26lAW#^mPYSv3kB1nFh2?f`<5m
zJkX{jbRLFOW}UX5Op$(R1`~w!Y#&@#O77|qbe;%Kt02ONimmpKa&i+;OEO;)9~=9n
zgHV_BHs#{&nGwW{!%wx?ytuxqnu)%O$<d2mPSxm%*>&OE_wXeqVRb9~&PKUs+Tmdm
z1gvv=2{T1~$LDy)-X@Vz%x{nK(7Oo21J%Yy`C73!>d&*(?kDCx9&~AGokV#4-GI5Z
zh9V~dk9k@`&&#xL2M$|kf8j5^?&tvs1zWsu)(s1<>WfLLMsgrBn4i`QNP{Mx9AMoW
zr-coyMF!W&?i8g={j{#!?_7(v6ahhT-Xru$PnkL0Y1l@CN?;JM9p}FCAa#{yzfkW1
zcp-)D1VXQ*N|>iC_#pmJJv<g!e{22b9Imd`HISX=W`uPH{x!`y#;#U<V2L*NV0RF^
zgLzsg14hke4-J2IpKnlZX$i|o%q^w=&|7izmM!CET%1I4X@3jgVx}wKb3Ev8doRlx
z9gvM+S$}XjE`EPPmmsu6^)Q(xV<YoZ_$y~DD3~yNY~+`{KBBJUuPi^di-r4X3lqA}
zmw`71W*ix6?K+*sBkGA9{W#q0Ly+{&Ve$e|8nDhiWman7<g_ITk()i?Q;1)&p{jbF
zQyp+#<|H6~(c(TV&auiM`x6^dWNGT8&`y27D%-(4(<ke>RZ%WjHbPAXB#}f7{=$&?
z<lYS8YMHCVR`TvT>UFNyzq0EQAriBIEPw~CNGX7=;zTnGR7PyX1);=C1rne3SD%_D
z6cL%S1FJ9jN7FIdCUSTGMTIMIlntCB$yE$gNkc%ERAoF~X_w$u(Gg#3)FptqXE1mh
z!N8**+-wC#E6tH!_LrJW$x)!j2ZgHCV4aMRpTc*~LB~DHyD`1J$+26AnYFuV!#x`;
z8ZN9)ha0IyR1~oKVeCi5@a(I-l)zYafw(eV$D_|v+YPqDdS1r>@i4f_CiM23-G*5%
z+Ci~Eg!+w~7SDz(kIH#)5K`bsp+xuBKHe%wB0Wu8v`OXb9aWN?sZl&lDw-!%E>n4s
zGe1H;9&ijtG)E42D{tJ+SM9O7`D@YRU;NJRjou2*ddHS&Pa-0vw{?hAPbmG=7Zi*u
z*}d=J!(Qqj=-NnR!rpgpTH{xpZjqXkS+(i71xUN*gp{^Y`J_Rg8%~YdGZS~UlX!^S
z>Al$xGYbDxsz>XmRF4CnG1<&NdSt)`{?65ap1jtE7#3M~wBe)SSu>TXL(JdxIogT~
zm!0XaX9k=})7N*Z;m_+ct<to0L5&R|NHrTVSIJpv@>eHj+k5K>iqoXalXsdPmL?Yt
z*7XjHTHbHaA&!NyB`0X#=mI^4tjFuEd^xyP3x6Iv)l`skHtc}@nI`+pGxvqw<Ts_C
zDvOjyc_E+L6UM40tpCBWLq+W~oNkl?fUteP{weF?GiC=E()3(XHJ1fJ?SeM-J2y*p
zgOjY^jv!<?<ABb4wXg{orLie<3hkl;ar9qVGIivC%8~{&*S&DtBhF&qJzX`{HdtcI
zpS(SSrj`{)8|C3vYccz68PX^;bKw@1e-I9h9ExS?%)(RLh~gn7NS?mlp!^C4(Qa@G
z`P*C0GQ*8A_<=UzFr&dXe>wrLW+(8+7Kgy{NV>9RaP!EkQsMA%u(F8>TiQe+LwRF{
z=9<B+T>J^lv2+g2qv_FCFzn4d0cNv}?&?;Ol5QgPIPqFdT|iRq20@(kF@7g>NV;7c
zbx~2#rs8Xq8>=|FiaH^0okLBhNpd`5r(I}ZWu0hio>D-s2}4d=xkwHZ&_kqHgG(;e
zU)C_{JkK#9=t6ufDsDW~nSuG;D2nNOQotf80z^%NU|n!}CabuXg-whuxUJ&8-28s2
zBtoB8V^Ut9x$n^kX^&h5-8$XAV{TmU&A_5LMS(q&v8=LC=QMgf(DA2jdw2g-r$_ZM
zxr?{2pW)CJc%X=;4^C^W;_q3M^C@o1L1g|~LiAwSc-)y5Dzy|8wz{IWIXfl&;#?kr
zes*D%)1tHG#YntOeT%B-d0~T+XOE>n>|e~~PA~na*IQfi`Gmjcs569yHNU(|&z@)?
zW}1Xae9JRn!pBO1@i(<ztPx<}152n<Cbg25FGj%3H2^|-jrP99rG}5Kghk4vXnn<p
ztBJXI6BC-~lU6=wh{TyH?h(zHw#{mB8q#4}>a>7*r2+*(S}8s|e$t1Ey^Y}PX+hY@
zy>J$7Qs|=fzvV{!l^bs8jSM2BCJgsYHdUY!zMIcbM}5^tefyr>k`uqxT>pfBjI=A_
ze*?bOh~8~Kc5J;)O+BJ$3+4i3k86WM;>!VWB*T*XMH3DHg20peU9O=`$N|7*-Ig`<
z0#H+c&;v|_KaOMgWex}t{K9``L^=Alr&T9-(*<D!e6R7d>iw#4+4cJbyXX-G)%5>d
zL4OB)!u#d~zu?pRW)Wo9`#D=0suzCM_ak%{qwZ&QPmMur+<yBgg7Na51yTLm2Gw~t
zLO(T>ISA;GTy>Me-0X*f!cR_)#?r!!2xMl2xnT=jNDTrGyI0GBtVL47ib=mvq2dVP
z^hwqfoPkGixftKvCD9XZgW#U;U}Z_#SWVrxt9jS&kh*72+KJVDSci+_yvhj}?Fa7k
zWw8b7X_S~DnPRYof-0ji1~T6br(k3SW6Bt)>1w8~3;+73<JxodvZ?Fd)zD+9VS7x;
zlj?J0L}F91W4B^D>~Nmw&oQCRyPL#dnOFG53bWc^ba)Ma#ku3P{S<>YnHc5r0O^(|
zQ1!#pHtPJor$PrX6!M!3j?J${_bWvA>s*@cxyL5q5$9so#HK>aux0c!=AsAbMeMDI
z(K|IjWOBU&_!AlewO`a-3qYyqM-Gq-kWAzE8(3^oKA|xUGVXc?8@=z_=_|PBlBeF@
z@T4Be&?VpRyI0qai8GE|?V&{gc_`-s*%N0S9|J{n&EJAX>QY|BZKW>G#+Ezo+(lHs
zb|CHrDn#IU53!H_7Xa30vPdr5uTfl1(MEgxJ%wGMw%GIJiPrIko~^6lTxB@eBNTBt
z!IWSZp`pas{pe+BULR!!RXk?xpBMPgoKHmglhMI2-(AS(0gi8`MAESr{R2n__f%QD
zqXgX;J*D*Y@&F`;+`rBrD!r0TmLto#^Ue$IQF5o4UXn3`0l!zQYn(1Q%&kV9L?X4Z
zJTvNjF+3gTvNNr31%d$6wgnjwZC_i#;{5b7v_giGvE}its9OV}KxmQ0&Q=l8DBUGp
zzPRnhT%HA8;@eVr+U~QX9Q3SEr15sW{uIBPrXO;9adE<5%}m#1@xW#*$6ud;JPeO8
zBt}&nnDVJUyp+iv5LqvOF9m*F&y*5P;VO9bQxUKKRbeTx7iJT<xNWhw7xtwp{C*1v
z-G$EIMK1b`ucwc$w)+-&p&V-nt@C}#&#+`CF<*XqPYk`)${d@&@f|dS^QT-A>1f6J
zB7r?9W5<#KT>`gfL;8+t{&?DW#S4VJBJ1b>qTb+>J32Xg-u5+}9RhF5oExTFWMhNI
zjLrCHu__)h*YQDzJ632!GB`yIw29NDo!;!VWQib-4la8zSCBuy*Z+otzzU!a|1?A6
z5gq5mixFm)xO>>uK{PC>P%SPgvUZO5Y-64@8vqZSDr_bSB~5U0ZeGbisgA}byFub!
zN^1NrEpz<^sCFnCKz6CFEhB$CT)!q+7daZ|Q-dHVIBj%mY&l8^-&U01h8*76XP>!c
za-LR1#bs&DtOa@TnGZDX6e}8Us0`a>M;h}O(0Ox-b2|c;MwD=sMqy)Mu1}8eYnbg;
zq<Ytv^2wl!S;eSKk&U9*Q|Sm|EWhe#k=vn>aep_EIVY-=QDoqwDdHf|&GhCKII?wR
z16)*;d65K#Df~l_Ci;`e=Mg*4%js0b&47b7r2ZpHEZJ6H5KPEsaP5lCC1t7gBs<c7
zfs74t6?5J#6Gm6t2q6f&@<oXTkt=aC2!Rpep(qE}4H+0+<ip)#mr6YsiG&(=BRETo
zxfN>vn>LCei`*;13M3=UCEtp(EDT6A-tokdjs8xkgROS{)Qg=IL7nc+z#6l?u0=Q#
zo|K0UQvHV3J@Zlaj;s+gEFWKD&uY46qju=FXDI%*Ej&NMzX(W%v%@RI#u0>n;Y?s@
zgId{9@vNi1I(?$OLrU3E-BqLA!sZIseptW3jAC!}OT#mItBxMe2bF`@Um#pZwlVcB
zjXU#qE-T&Q(PQ{XQ_hTjyG+QufczF|Fj^it9rB^|T!>mRIo-7;q0*ss2(nyK3j^XI
z#rQ-IGf4T}9i7r{eP?H+N+~Vfv5(kke<$~!p@8vDxwJoIW#u)Knn)H0w38DJ)rZuR
z6ZRwyr4#E~r{&cXnu(AON+~V0;dzv{K*53KotcsgUgW?D$loLSjNJ($?p=&!uj&ea
ziYlt##tTsK&9#}xTRo_wG>EC-t${ftt7w=1PAjmLI-5-D=ti!o`s2u7&1%Ivlpnd4
z=0*qvxPvI`CKOc<-4euc;fk^lBiV$ZUtB-s*-*k=fTTP}%CVt%?U}p|R+VO)b!8>r
z;_-V|peFeTyr}?0m4FN<JXUQmE8p43c29ugGtj50pM8rs&UyS9TefIZHoAYs>%(rG
zKGx55x}V1V4tp5XUS3-dO=JEuRA=W&r;-S@aJoAo^`nUI$JYPAb226<hnp9^h{J}r
z-3smj-lH}YwHEJhjM$TWA{~11^e*_5Ag?xVYyt^V=2`S(&{7`Z@d46c`HML)CHG_0
z^5~>YtcVA5M*Q-0r~zSyjYr=0_}k(AAAoIaOJ*tT8F^(94T%aAh7>%5nh+h?294+G
z0$@bDbZh<$3BnyeSZkJ7*23c1M?~<}9&F*OmH2`d>I6N?n{U{yC&WE%xpMibR43B$
zr>sGf3S*Wu?{v^y7`W1>Nz{!ICx&Fc)OMiyNnL?K@^6Hb{J%JEyhy|II0^x;D-<G_
zccADT#{C9)8Yvo-&m1yMUG&YPwu3%wJeyCpF?_GZD>Nk7R~ErJU!tD&oaF25UzO#}
z>P18&o^D-j@&#a2Z*7z`nwxVO7G}Thz=HT)2YQV3>G{Kmjgx{W8aH2u$ZLs_yO|vY
z278K;8mY~I`aOj}BIQHj^A@CprUE@uC6a@)dmjh$fw5yCXPaS*?zrzCcENC*ZBPkz
z1`j6I(sy?3h_bh>ZH`D0IrUf<WlrL|L#~M9*`=6RsO*$1P86_#(8_*2v?Aj_#cj`m
z<Yo6jjqf>St#FeEMFvRj$C4}O>ae7;vyiLEB_Y*>@R@8(4&{n;Wptvh#Wb#P(~8{W
zSLew|_E=kyE`!=IQL#@iHzbEvgQP<!@-mp@)0h6GC{xWJ4i)pR*V|rc5tQb|g@kj&
z9)IJ$h`h_9$K3LrLW|&6oa5@r@Ih9iRX4GNTC#;2MWESDF{Hhd7QFU)c=E#E(B9N~
ztl|3!y?9eHA{7$xB^BkdbA{&dkG<$0xqnj*$cF?tGGKBvUu}{_1(o@-CX9Z=!bo{H
zcU%GG#MehoqrxQ~BGFbo?7C3x|FLPCz*8V&swX%|pQcNdWf$`mg@}Lao_lpYhFSP&
zM@ijLnQC$TI$_0*Mz#3&`>iAP`JrdKgN|?8DtR;XnYgEmDM5Gc_zxqdmg;NWYm=eA
z!)cE%k8ijAc*DnE`A3qkHrFd}yAZ3s?Z4k&wm{K=odHIT7S3rSAPZOt?UMzAQt!0)
z;JDGi<}uhEi5gJ)_}5kgNiD=(IxA<dmBp@(D2!MSeIk;R!(?2;-0qSJz^e6)O=-wo
zFXS_%%5#+LaiFNfk-;1@4;5NkwRPhwd2W5GP6pQxt>i5_cdc9XceU9<NR;S@Ct{wu
zUbM+s)>AMsc#BL^Ky&Soe3c7dlDc9oiJmb?-$EprtI*Viy%a6y!}uUjGB$%1Ue@Iy
zKq88{X1^C^9o?y#s;q|Q`Rz(6H8XX3NSuMV<HZ#|Q$~S@tk|0grVzcBnl*`()^lYV
z=tp;TG>G8+TTvwz=NVbQQcXaC;SvhiHS-gd4$ExIWaN@cNOv_<cR?cZZ(xq(kc$9^
zAKoJJ`7yu<VT?>F#i$v(Ul?Jhx5<u-A8cR_4;)~}$}ku{D~tp}2iUa~RQ%-!Q;<iw
zf=19Zom0wZ*{jL-Z`joJcp=f!d$)W}70^cNu+M++h1VV11WwFQ3&%*h&<(yt>XMyB
zhTGEjhI`B7C%353V+QfAhn)TWREWCJkIIkLPCl-$6Qm7Uei-nNQnhl=tGC&X&i0co
z&rs{$@4EE~nYqtxd_FG3kb~b7r&469ea3uRPXoq$d{~VCZvXqhw)wDApQB2#Q{N*Y
z*aUO-v*Q`QQ;$dczFXgex%;y#B=Iv>HvjKUax{=zFOIiysD0ODdxWT6AHO|ME51|Z
zImRN<Zvirg$6?8KF?nzIGCZJst!gK0WgJLy9LK|C8Zfm><)4!L?Gj>zul$yNdPB-N
z1P>~JS5Md2R&Qx<4l07%c=YJf8^FCRhyr*6oB;9T?U+V_y#dUE`SAig0OrE|dsLc@
zCl~I95@Z%Eo%rV~ggpV;kOcl`mN}i*Zmh=c=PEhGpFL&He=gWr%m?uH^L34*@b2{u
zA4TxRr>|TvMhwG3fC~pfG(B&02Q>&C#uy=>XD=+}I!G9)GTR$HX@sxox|=v{dJH51
z3|wZcrDv?8AFV1HX~X9mO)2)Zq}dhp7X22jemXMtV{307ymom?Y*eez1d*m+ZtcW{
z8_D-4T7egvCgB(UYz1m0Wp{vmpl01xyM!pD7$=Pb4Wpgw3lu&cQ4uoeaHs2DCquYA
z$B?-*8tVumx&H|pkn_O)D{KJBfbo~kw-M1_5TSbIpD`FRbIG6r$c3Vs+$Hg`v)n=I
zD{7u^DaTa<cYZIW{c|?|wkA@~ZC=4MFT3cd+Hl1h(F9uwP2%?SMZIYA<s&+Hj|bmT
zlh;v~=gZ1^QW8y>w-8ldUa&wRNR6ebFVA3T*4aP&sdB_$!~cb3VEC;F&LXzX*&P!+
zS36TTvdNp$+z7?MGD;dIBYA#R)r?69thpPIoMxMmWp79Dm#RSS*Jo#%4g2g&;ICUL
zJ~F`BqK;(g?CjF>WY}!(Yp9s0<qdR>>j{IK2IHBU9en{w*CAFuYJRZ3=;m3gyiBSQ
z24z6-3+xJAthOy;!Z}Ry5Bu0<aFpokM&ZVk`PK7d?~WcTfZGhqQ)V2=&=1~D@3eOu
z-n^?vPi0+WkJ#RHfvF^9c<7X7VE#M%$2OBzE-mjdm3~`>j1tS6n_P-zAUL>IzTaKl
zp<t{}<g=mWHe4SQDdY#T&J6^&=*hVS6W7*}cB^RIn++UC`3HZaun45@^We>-KJY>n
zvu};^eKk&Jc<zoHCg1<=(?b@+Avri@zhRQu154rV@8}m2qte`5k(!#w+rm>bIUSvF
zzCQl=gO0qoQihAy)6Nnt=$6YVfa+kwoRgg)2RZSV0qdseex4gVz(2>h$H4~MMK7WF
zD}fBOBV9!PnZ8<70H~{GKm@Fd@yzp6Tfy%E3Ui)H{y7^4C~ifva{rY-D^YEv4i9Ru
z{pdH?KlijRisP@e9DV{B<dpFT40HZjI|lrDz(*cunsk{V2SOheb423pr`bL`#d~}`
zH%kHlQ(<x<%YDa)AD1wSk>t`J>uPxK)@|2obNb;pDuoo+3QfzV4a)l04HyeRKDAW<
z6)~1Vlo&Idi|}9K?ZFYE`onbuVX4ubUflEq+z1>;g0-Dh%sq)x2NrLD?|!>R{$oA;
zjk5M9EMjRvw?@<smAgCoY=Z;5C;DkCRN~jS-wae&f`2J@$kcV3?{*{s6&}$}F$)>N
zO8j&I@sxvWc_fsYcK-yu6gsZs-j%m+uF>f-dsdw)8sAD=OID%~^ytIFin#w$`1HnW
zF85^_NAsMQns7<7E%lvOIS&sXcEsxb4Abotiq(o}c_MZYM!tx5T1Twfpq%+^3TU3B
zF73M|FcZt|XQFF-Zz-imfHm!E%(ti&xd6LXYB2+v#-BhLnfNtQ9fIA_FP4~JLiapK
z!~~Ol9G2nviR7-nN!%KJhzS5lYyu|N(xgRHdqasK3wzd(9wArI23mL~xjX>DoMubE
z8f>DRv|vrW4NzO7X#}v+2*@5?6hhv~nD&x$CBOA(pUDOG{t91#4=A|y%8gyXf9&gd
z`AsyB6r;|*HB?~XoCJ&L*mNrhx;agb&DjeWqH8DDM-o*!0n3TBeo{k?I2snj)~P1+
zBI11@;O$#TEmh$8PM>&G&yH$yEwU}8=;e2V^ybCml?JhJYWE?Zf?K=*K`X2xqWdY^
z??%0)N-0|l=Z-%ek~1XG<n4_Cdz6!}y+MCs@ZW=7;Oy={XC$JKtT<r`zO0$kWDUal
zsgtYXabk&pB3&NP8fYVCQ}28H-AKW&15!!lbJX^%LW(G+WKzJlkMREwUGD%KS@eF3
zc8rOWiEZ1~#1q@LlZkEHw(Vr%WP*up+qPcM@ArT8?z?qwe^q@>@4ZiV)v4;U*IsLV
z`?DiE_lTIGN5_i_>M@2IdQA*vg7~d&&Umtameqibaim6jkM2r1VKz{~>Pmh8g|zpC
za;T$RsXUkNMlt!8J7`&L%$@0#1yhKOT=qJFxijj_oFbau4b?bpB>smwnRxm~Gtadb
zc~mh^5%^uLQUoh$52EAWpg+RRRe*YK*I4PbQ~D^nTbvsZwp9#Aj)^T?-`k(HT2h?r
z3$SJn;g7q{@+}VU8Y(tly%gAq`~s3Tp+=}~h_1CLRQV*U(LWX8h>5`Ck^J+Z2!(G#
zM@C{dl~11o!z100w?T-eH?A2pFyWAhC9zDnjuevK4bjw5{*p)>288+kq%hZ*h75WF
zDyD@9M8c)%AsJ8)jEU4^@Uj1purl&<6WkPw9D&cY!jUO5sBDy8L=a7gGgK(f&AY7=
z3rGAkNMpW>aO^#sGe!8IK}NZTf1#pC>MmwmS+7p5h~Kh^j|fJP$0t2y<lHaayFBe)
z3~g**(em_CAxrtHJW2{(c;E51^hlvd4-R*_20V*)?TGCkIxMYruO>z;`Rw-T8hsWm
zIoZ6<G}AJ3*Wpa4!9olCl3gfl{M@IB5Wl;-zgym($h)QONh}^2=p|hR&0K$4bxVL}
zL~Oon+!yvbjxq;o9d$hzTD&F_B|1RtyZNF&>vXq|aKLok&8*$|+q?d9TIl(tlzJck
zQ7#!*TuzBFjb#z%#9#B04#<UrI5K2)wBGnFiwUFjWlhT0_e)*>v~lB?-bQSaj&sZA
z*V2}ERE%$rE2=@~3iWTqD@hG}Gs2#NDFzePmYQ3mJF8H6tgnx=m%9nBm#tbn6}{bD
z&!bH!GlI?B7p=FguaDk=jORnf4(#D8>ci6km$Q<`YhQKe3F0@|8kM&I$w;Srvn0W)
zE1Ya!SNb%_jIqgvv95BLoSyLzr+VSNZFBxci|Wj-;8Ewr;#Rw~*MVOrHsR@y8wbdF
zm@u=rTrL!Uo(Il^fY8^}wK@m!%#%Zns7{<fy9xZ<yTOPtp|$8-oJ?A4P4${b&MI!S
zh*}c@YPPrEt)3AyGnt-#S^eM)$vZb~Z*cR3DH=WdxDEd<g6R_3XdP!r=}&4um72CV
zZ<6C5h1kauO$}<EwG13wvu48#kK$j&JQ`}Z3EeTa6i>KIw*j!J@;eFQFRRKsD5r$N
zc!MSRN4Kh$T4Wu?MDbPFZHB7SQvUA5@!T48@i3=Kj@BX>Wa|GzVc5mW+XQk?^b>}9
zT0{$i?`o1NNYg02iez9R@s33AT8GOjnm2YAa|>lpWCV?=HN`s#IV!8}cD$3$b6Hn7
z%OBO{|3b)T#)*eSNn0dA$I|mMVL!S;ZA|G%4WatJk}&6DIBPhXVZF(S5>fwM8ZV>q
z>mM{$EeDojq%6GVNcW^qBTxKE>xC{5lRMmBG7dZcl1a--HAtzRa&gBdg%>CC-2TT^
z`7+lsMd|Nj8s759%1g6TINuQ1{qmA7!t9O1e2}iFkE)OLW-gxZ{pcly9h9h#GVKE2
zr}wdruFm~t*Fekh*Ybr)>G7vsTrM7rh-2}>uY9FWKPNyI*f#F<9tPkDzzNmM1(*b}
zNBGwoSdxivkKmRJ$_e!orNTxYDhuqA4D`Rf^3nFaTtLXVjSGaF+qi(Ee~|MC2s!I`
zkNkW>)nfv#JuP5`$IE2@NJwB#Qb~d^4eSPx#4(!)VE@2^F2$DIM^NwLJOz*$Nzw*y
zpT55yo^CAs<PF{~d3u8&dGr%-2V&j-AYh*sxBmgbf&_s7;^JxNIj~nits=lX??2ex
zkH5D|^k1)F;R#skJ1o>a2m%?%tDsUbaM(1IEFJ7L)Uzv8`YhCYY8dVf6zG6s<T#@t
zQd@O0HZr0l0*V=p|8^WNEA>F%l5u;!!;k|s90JuTLi@f0O$H}3H{GCB?YpCg&4<2Z
zZ(cJTZIlcxoTJr=1N{hML-EO$rgWQp?o3a7WtThFc61Hh&F}0FQo6-cRUy<UHu~D(
zfqL`p5w^j2Cm19JflEL&OiUISU*rUbswXhNxdEmKq(IvFnsDZ&ej#qzb~EzoQBw5H
zBP5Ym<CflF^gZz%=Et!=r9=W}<{b@3uc?TBVwsl0vh$1-|8%1|Q^v+2Ea12w*2yiL
zU>*Be)V{p>zPbVmU3i1PVyw8M$;Tz0R&LcY_8#?NeWB`iv|%+EjR;Imm%z8?%${82
zn|G+eORHmB>*L&L_*aWUsbki{s?%fV2&AzgRdwZYOzhe^hn{4vX_~mNpylN+G~tPv
zmY7;21J-k=bBEU0V!8`q8Tba6g1Ola&&ui$=swjpYtzFuQ!`xcu*biYNrD1)B{&H8
zcX@)mb5oK4=M!6##8Qe=kK#azskZ=<LN*Su$+rf~ck7iq8aMUnS)KX`#Bb9=_Jwq;
zT9ikB9b{AhpghB;OJX$~;S&F3u=Rg3SRoA^a&<B5<E#7DB?FG&`=KWH&*5339z;96
zL!VH&GS3g)1-0}|k~&j)7BUF%z+yU(I4^DQ8mvnMHNA%9YpwCa6Kq~y^N5Gu0kF$h
z#oDVK|7bqg`}~SEgs%oN*cYV@YYAR4vg6}h&oyG)M+mtm>zH=RcJ@6niGS=LHtN^#
zPLdgK`f;x6s}pb&D%!j5N6x5#lYt=I?9%QbNnDV`VNN$ps_-A*I)9I*Ys}+-kHKYg
zb;$bgrBsD-ZN(JVpSYB~7Oh4$TmJnI@HNQ>{Rf5xtL`F!_YM4C8(!=!NPUgM8z|Bl
z5CRwIAph&;X+{IW+$d4Osy$sw!bP@`D}bSnQ!x-a4*>QbP|n==<&Q`g9nObA>ucI)
zLH>QGHWew-Sw_7#5KJrS0}Szi%q8St2cd77tf|tex~%9mZ1k?NmjEys_ODM7tz0x|
zFPz1J@x=Qj(>8(v#ERmBNhXab!R6D2Cw3Imenis2#_6IaU2BB3fNP*;FCsd--+}_X
zMKFmblxG1T!8X4@A<e-Wn%I<tfdEkkT23^k9f{VCX5xwzwLQb9mtUV#Lmwz4T`2v3
zLXs7y+cNx39ioT&;REcf=ezHC#P7Hk*k?)f+pwsvcKHE22#F27BAZaX)=dM@;k@`5
z{|clbitsA-_X4C`7uz)veU(<8w}VL2S~l+r+U|0j@K)k`j`6;HMmfQXo~r@Xhgz{0
zBe@KVm6%)j2jCxqk7>ruc7TKMCermdUixM+M>HlZfG@#Ts~}nHpuI<RIwc)~jguex
z0$SPaFxce_{X0cJQFW@SGD1t($9DE9x=k;Zar>^D#`f_-T%p>ty<#2Q@y;|!W3>8F
zSPns`ps}e7g0t2b7i54mErXh_BVu3wm<cb}@su^UaP=W>Vg*BbEakN6=8b-6hkCr`
zszlb}Z43xc&$;P<1s$9H&iARo|4LebtbB&WRaqZmV~_WGoDsqs5w6=ceOxf#2Bq^~
zWmwFhxEuEGapDW7lz88WCWpS!JM$FU$AN?r`}FNVrRo;Y^Bmt>7xpwrjF6x}-xQ$i
zJUzu9J^e?sxx83vryNysAeRG*adya^jfCZw?t<snm2XuW<Dv$Hazjsg2S7IW<S<K!
zAYnOI&Xi9B_gm}JF5#+VtOW%a5cQeP=+ZN6>hu^bC$eIg-lcUf|6KclH|G-1XtQLu
zrQ2<?tTfxSL)KxixMYH-<eJX-OU=%1v&&>fWp;h%SBL51k_w)aYciwjRUGS5D%@|W
z44wvg+U@z1a~r(GCw7Bd4>h$e*Ph068jHsfMV;i6@p2iy`P`^W!L+g2rFh_Sf&S|1
zpf7H=kQJA!M}PKUql?g6>QX*U7R%*X0XLGxfc|eyUDQI*B5Hhnh!20bugcOGg-}Ah
z9_iLMqs8us9-Nz6W1D9uk70S75XFT`7L<BE_#^c#@Ru=r#!_b&4cITQE<TBZMk!1>
zQAz9=fxoVaSTqaESSc4nT=qWH(rcF-wiVPmjRzF)FK2^tsW(f7d<o%gIGZG4_~FU-
zF?(n;K3zW~PMLA1h|bt>r~a&DPh)IEE;pGcuWg|<H?Nf8_^MM-RU{(KONO0Hi*V<M
z$%@hglRmuDB%K`3M<|x%_0p(wm~XXeg3sjehn#wx``oB5G-ENSUY`;_32rxJ-tUBP
zpL$+{)v@1(qp_3sF5I7ZTPc&oOV3Txqpm^-2&N&~vZ74Nza()F7P;m#YOEO*cG7Tb
zLHZ9l7)Harc(+U4c*dz!QnPnbim><Pr174V@e$sc$+yNlaHi}qdUQTr9@exf)F&Bb
zTS98og?nNjr$(?%6A*jCC`hsUA3m!GV{vPLpBaph?B|kjkUWuQ3*_#7{n~V%?%Cwy
z<NFBt^mKaOAAKoueV%N78~r^%5qqh}hyPjegzg(|RGl#Wg~}gs`+mmSqsg}(?Q{28
zd-YBbTVQAwWvngaW<#JDHKY^xXCvUI;KEZH59d|TTk#RcGwjD4@23(O@j|mO_Uo<h
zh-?G|HjNhBmMYtGj~UP0v+pU#+rjyqz0c!bfv3-7lNOa(%8l`tvdn{Z^$Nz(ZR{9}
zvtYbKuGyB!*&kT#@6Jo7PJxHVlZ=QQzctJv9EE0esM%8$X*}03nWtlpg&Uh}U@3?$
zJ#gSfM4*h);jRsMMe*5g)i-k?_@@||{1dIZ+x5d|(#fXCVrk*U>EbL1eefTDyvSn0
zU-cX&nvuRQ{D(bvlb`d$eNp)pQTXR&p~;os!;>HBvc|UNb&23dcy9WL07U<Q7coz%
zIWE?N+~80i%-27S6j7L981MW0v&tWBZ*}W#yq*Ao5nIweC9MvZ&SJTr0i%s+>DIc<
zU)-E*+XKzGo7IXQ%M}=H2D>tGk-Xnfh?VRqqz>6mbo4g0Z)rwNa(?tRXy4FEKdPMQ
z=xlZFsU=lvj|BwhhgNYRlfQMWuWLUzLIKWD4{U0F_4RAt(aIeDYVYLl>DZms6&t93
z*JvX!MGG2>#?NNC9qD~C<Xw-}tS96;*!C7b*@^S&KzoO^kCz0*WDkwWfZCta=$fGT
z8A09Hkb|^23ot_F&wV`?rtR^LT!}fLQ4A|o!0g`dk8Wg>mMF>4Pu8|MuYAxXDxlG~
zUKiq~PNeMJneW$uhl>VLr*%hvO}0{sFB)~sIJFlN{2*##?x!B3L>hi8lnHa3TQQFD
zDRM~8Fk(jt)JFMoHYS!%j(!_Hc;(zh0v8ldh~0}1yT5SZOwBk!;@OQ$KJmTSie%=u
zhaU#JsWtU5%i%Ro9i@|x-TU6*9oPN$Zbu@EcOT<C!$=>=EPxa}rRwR@=Dmv$<JLPJ
z{)lYf)3fhrVpBN{=ILqI+t?_gSPPGPTLvY-8<hKnlV-uqy?Y$D-)tNw0Mxk+^&4x_
zeqW$H!<H;LNG{Qb;(LryJkn*f@k#6sYp#ToY%_u+@Yz<9=0J<Eza#OSmblq}q4^_m
z*Z6yQ0!k>xqO}ZjR!N*6iN++yR%d56DRQy3#cS(g$*FQ~HWWu@DoD;{%RI=&iX5p~
zeE|9Mh`G&=ZWf8EKfZ?5b?V>}rV=#*&U<Fsw_R(XF9d~e8XvIkNc3Vgo`DsStk{PZ
z5F{ebiHHQPmD(C**#i8$lJv=Uk&OJ`igFhv0}SjCof_a<JrHTKZ8Lr~ScHribR9=F
zTO1E<qBzh6-Y0z;_x&bic@P-Ql^4Yi1HG*_bMiR|(TVxeiHV8@V%ARHB4M+@w9rG?
zJn~5vtjVPw1)nAgNngqdG1lgh{;&P+N)6XZCHk$|_q@9B$^H`_$EUqo2R+~hFQ<2G
z&fM@Rl_mFXIqOEoQ%=+hFgQ<I=~m^i`vN<}48mnxt2sBnXrn^BW8}mxv%FZNKWcVV
z=yeo|vW2<m@{}(Aq0?O}W-j+p`e%n~qx~^8NcBNYkKY`0JT++7siW3}H;qDKMVs%+
zy0pZ767J+*Hj<si6ZCGQjtm`VL^sr%MxGIcZ4ejh6SOrsI^154*5;uJE+i1C9Y<|>
zcuM6=%CgP@X{|%LdekK)ny7rv?AGI>;nZ88Fs3~Xc*rlK&*sKFG?9^`R{6UE6C0>A
zlK;WDWz(s92JlNmrWyuJE>hg#QiFv0;mQ}GQb|l!HsqVl@{MsW;jfBHtB$QlV&t-F
zJdxFmpV#7A#t}p6t3)eea|^j84Ln@JjDua(w^cSzYvmD)!g@PNK~73DbivONs*v(#
zIv@4SE8W|)kzB!h?!&8=+$jj{KDrOu&Y~M<PZiw_OYn$(7Xcu1Db_k|QA*9lr>C=g
zw4)e58p&|Nm6C}T+G*9((B0}wI%e(l^~2_1NyZbKl4Ck-qdz!je?C6`HP3cVvAlAn
zn-<a<$Vg>KU=sL*|DmZEwz{ife6Es*sIt*bhTM@-_8-3404o_#q!m<6*Kgo^?VN0s
z9yy!w@l5#74iyIEo5M$+v!cr=6D42jHxmA~GIy`ii<-Y?_nSLjjk2hs@gabEHqly5
z9pVF+c7mjO!wd7!K_8pdjcKb)2W+Z(J?g3>y{wt8tZ|<lOv%i^Y|yi?4RgoE&@9=G
z(qf(*e#{?6Fys41LM(@W8v}PVM0YfVjgDdCivQ)BJ`!HV1K~&<hiXMiF@zN6m*Pgv
zfNvfyD7`Psn@7eTkq6Zznn%`RCJwG?NR3(VBA+QDQ6&kxO~Ni#!0RRYSxhA;v9DLw
zA0@i^15C<rfF9gGae2NC!ycvGCCyO@MFTZePC{}YxX*ml;GvWn8%aI+_x-Rq_0+*$
zaqB$$Uh#eHj6)HkY2+6HgvJ6AdfG-#oOpOFWW=2$ZP9fB3gy88dD$V+d-OsvV#Bzl
z$ItP6za3xhul_9;>m@?IF`kKMsL$zx4&);l7b?5WtAH$y_fgsUC4X{>tu!bO`Rd?u
zz6w?G6LsiCc6|8iHLTzh^R%YNZ{!v2w!t0egiy<3z9z_y+Cj`mH%t9VmC$<?0*dG*
zGhKL-2cKP(<Mxse4%Z4vX1l}rtQcn92YKg2216=2pJIu9*OxSx_P30={Ntz{=S;^9
z3^GTEEcMv#F%Uxq7h84azQj{MEa<l)_C6`*k#$QWNYmj3B8@b#6D*q$zfWK&)B`2@
z;uj!C&V0OMOa6&vla;XAZVr_TE{PvgnU25C&KzM02g1Rh3tx%#V*hB?e0GY~RUyol
z+OqKD$QHOTWr|>rA>4Y07kbXrZFLr)k!gu?sTZC|wZZm9w@DWoFy?9KFvh+X+~TEv
zZRIdtGJ*5x-h{@8YEtgA{E~ktHkei8F1LXtsfxvQ^WyAtuYUV$TT(+^#U|X&Y@o{n
zF&eavba4U!6YN!61&Ze}N+NgP)UTZt+|c+`LX8h98?BQT2$oeV6MH0Z*UCz*naG80
z!|!e?68<cRTNCHHEbeJA@arc_&yilb=S`#AR57P9%S+VoL8`gYbWz?C32%M5`l^fm
zxXSqZ9L5;~wys}DB_=wIYqeSn{Vxfj&b)c<)O*nL(oL+uAC3u!IjWeYRhUWUZrZG~
z9`&prqj95k{{@3GX@y3D+Zg_})Q5lFX?DH{$H>nlh-$w}i!m;p&nEa7M0IT(cjWqL
zuy)~{HHc<JGV1sY=Fxu{`=4e>9C~bAAVI#BgB#wqi{!UKxf&7?)CMaedolKK=-lN|
zT2Vo@fI8$+(x92x%t{O9sa(rdhVdl`DJ%xcU(o*bxJ{^%k7vUmcFcAKp>F6$A3j4D
zA6iO@s8U5#%n|zAXvu8@eE%O)530}*%V{*4-VykS8zk10*RI2bd+N9wB+Qg0Dg;W7
zP=6zNR%+R;P(O==+hUb?cHDK8(L-R6S*J7@%v1&`HYu-_rWB)uTM8l0lw=v<4%QL^
zDk<-tvj*XghEg$bAn*d3;GiJ01uR@A1z^8#FQAF+Gj;%2TOBpWy?yldE`?sYl$+$R
zKZf;}Ilbo*#ZS8ybt@j}jl9G38*6VmQ|x}pxr`s>R-0f5FC*eSyn0Oc2fB?WDtav;
ze}~e7dJ!3!ObM@PFwYa<SIBgpDLZ~*a|#f@Rw2o5%Il*TC8QUZI4E9<OE1t3Bq8cO
znfN*T28RR^qWO9S$><#pOMn4QbhiTiiL;RWRKW?Wy$rP#bLiJ&`9&@t1!xE44>czZ
zAOr8l6cGApJ;EXF5bw8|q98t8*JGLX#!&x`{(6()XuS+}QKG#JN4k{TsT@E$z{ed(
z2l%)T0KlIQI%{BoqxJcK-S}93dYdT|u+Im;8}jc`gmEr}LBn2#Crb;A{j@pEp%>0W
zimD>-fR34ap{yz|b^?>Z8%lgV>xKGQ;(@k;f3{SR3Lboca#yt7St2#zK7?HBf6hdF
zO}r=PFv~XltZSk)UG_>?1JSrb@qt2|Wmvm4k!$(?|H_;zuB^l&4S~$tER??Ys~b^k
zz6bjuXkSv~@RD*%{;Q~Z5fwH1h#i;s|0-RvkNuOb6s-SASG6J+hpK3p{hPPaG`8Pq
z4F%jvJAUBU&pqjIesG-J`|_qt?*e3{!wmpeO@X;r*m4NlXxu1svPJ&vEZNYA0|uU~
zQx4>Ovd}Iou<-uupsmebB7~Tu%=`(S;OL9EhaSk5Y+G?*28=inYnuL?Aj<Z<$d1fp
z)`Ae?%cF81pxwrFg6W|ie(1_z*29rZWsuPJqiotKm5}BJwW|>iCXowZw5srNMbCb;
zQWt(dC5ph?+zdGyw28@nrY0W{Q(Y#6McYv=W12J15fOX@+tjEVG%jhD)Hs-f#IkRu
zPZDTDH>KO5y&^sq_S%@@2WR?6JUBmRPVl587yKzMqGiJ@-RLYN(gr*R5>22xP+0%j
z)biPdZA05uw5P&sL#rJq<`hP0JdgS$kMt`-T?Yh#|0j64ge#_6s<?(T-o^1f9#=&I
z)893|O{6u%PnfBi(dz}eL+TI1=k*@k*8d@H?J(~n$gWCd*0j}w+$6;FIy0`fyr`*H
zc4=V)79z{2c_iEPGC64@<T;?Z-y-BO`B@-{GT>5Rnwf}6Z&%z>9Iu6qV(_->tVTDw
zcMvX`pxrD=E<rz94{wpOZN%9uR@NevZE6rV(A6YH2<kwWP*!X~wox>!XRl5L7O;0j
zzD_?Q*<ifbs!Sn~ppj@_J=O*-3Ht)+B%!zrF!J!0ge9uR);`HOH2BqbG(U>9kifv=
z%aE&RbNAC^IBq;q9)6<yy@(cegIF(hs`&9P?Iclyoy|9KUdUSVdytkF&E6*wcW9z=
z#qe+6C$poa$&a(;OvWv?Mm1>{FI?{O4N0GtY2>|UCG$n^Xy+RY?|uR5l+zqjM#fiP
z=ikdzuc2o&_dK@@;@xq|7HoEigVfS7{6J5()E)JDhp!MfmyUrJ^DNKoc;AYPJ-{DO
zoOQA0bmZ$Zy<41PBcB4q<fS>~1sC}^llw%XDL#`Bh8@gk6s)!kLa$XPav?H9b3M8D
zUvXyr+M+E7Uq7}hBif0tT$$e1zcfP1iKZq=Pn9MD7}z#WaO8%FV><v4WqaA=wy^T3
zI<^jqa2^Z$S0gUJJ*&@@V^VL-l5R(ch{ZhojYrx*usF8E)VLr(3+LfR51dkoD_yh*
z{}kS3&Qb3RwPChj!dKAGdacjF9=5TX+!mR0BU&hC;mwW;PVahAnLJ8z<O}CyH<12F
z(6g@~$B<tBb0lrLEc&t~I{N(gz<?+Z1EZ2QCHO~)!0u%3@Ky8v6G7YyofHj)!8cu2
z=FFo;s@*GlGTC`)8_U<5fZ;XRpny3#>v5aaG@~g=tV;%_8Vv8++@rjCcR4XG#+HbZ
z*!hb>8lfB>R$OL1^3AOH&2lxfeY@X%s5@^guW8G0-w6avwALz2Z-@xi%IuCKH@dg|
zX7m<0WCF`dI_IJS3i;UOxAF*{T5OKVAib^gx`h}PhCie>Nua4XkBz|CDxkO}tax55
z3f0dFV0Wzwy8YLtZe4onn>WO~>EZDD#4HC9N}(fVbQ3E}ymZkd`!D7x`hD6Hb&h%|
zxj+2bPjOyRUErl`xVq6T*J-kO%|nemW-gfLWwHS$$pZ;^%s(^0yVUdG*yewAYe$|O
z5>k?dA(c=%&<Lu=B;PG?gD-1V9;gzz%b<kHW_h13Bhoo<*e!5cH{RDxXogm=TCKDw
z_6|+kIH$yqJ_MuE@D70(1v#u;l)T%}5uZ}u+HquxVzF(&T;TPl(kHJebKE{~gDbGJ
zpK7%%t|~PkX8gqTbt*-sjJ(Z9ZLRo_zdO}=&%Gf|i`KKTX<kQ9zIL@JFljF--k9l5
ziS$p=DGagWg(b_p(c9n<QYJ1cI@t<n9a@QKU>8wu!=EbcM+&YLui8Jmfm3jM;?A@n
z<$wF`ejg9@*<$9{O?WSGePpXDYG~1riF@<Bwyhd20Mq$t-y=CBzl9UWm^<P?6X#T?
zT_JsD*7_fu`Tep7T93^Ak@3+JZAJ~!AVBedcaRT){vRFWGVKZst9>7$m?OEtZ%}`6
zbv|OghVv4UZ__C6=J*7zn9TWXKRsy=hb^@K>mQG-{*(7@Um?QD{U2tXHVqd-oK;Vg
z$|X-))ENKrTK*F0S0$7-%x!_A6-`4FC(a;tf3;@_UyxaxZRr@P7J`m=Dl*@L4w~44
zF6ch_CH>UYKPq3C-FCC@XtOs(ZJA+>l!D6bakt-vQwdpM?<-&*Z<N@LDQP3l>zdH#
z+%olO9Gl4@IFl6M2`mS`>Z{yC*mv|gzs}Vuab3h$IYxE5uFmdB<${bgOEC7(=Cyn(
zu`BHruabof;`IqmJlVE4z@arvtFxkEMUsiu+08QahQMw4^T`~oT0IHF8GAM7S;3P|
zuGFa~^Rs+8@?lmzzFBr7FYQt;oq{y7BSYy9b8tK&#1--B={B2koWOL~k6QEIMy)#G
z#eOrMDA&t>0D(g|9vS|Z<ez5YcTl=$K8HOLEI8p|SzFQ-%)hrR_$u8d;aRio$k2%e
z*j>aeEze>N<CT%Lj(Lf;sR*|eDS_JeqqYqsFGoyIrn4vh;zEQ!A$%_tfaRXqySjo|
zQLd*UYo0kh@}Mk8+mNfguwf7!C7Sr$!HqOgmLTdX4C>%Sg%So=vh>;wBKLeFtyB`A
zDlsayBxSRz`(!-&@wR@FB^*d<U1W#C=}dGu;rG9wAByk$WF)v#xC)Tm+L{QCcZFOI
zg?z3o=jF0j7~_=u$M6M8jf10SW4LR5Y-(-SwZBRHR*Cuxnf<brxikf1#8>#2-WOF+
zMj;bz@XK}M$PG-D_kn&fkU~h#o4fn3z(uE)=7Ee%S3*sOSc*dF{4Lnl8;D$wQt6z>
zI1qb&7Tb=BlobCC|7ZWIOpeLKT}vk^0E%3)FmIU0)*8XCWd`fB@bwdHQ8VsN{}s6g
z9kP}YEDs#3d~9fGq(KR)<A(@zEu!UT2xX;3tt|emze<mH^i*lIby$usl4q9~oy2X0
zwlX;N3=Ge8`P80P$`r?HU|5+*A;Jt9Yk?A0(|n^{k;tHR8EmW(iry<xN1W$8#K+Rr
zi#AFah6W~OwIqs_|F0UCsfGD}-CwG}oGk532a+NSel$?Yh_5|Hpp^aRnwGYFKVc`F
zwtQ^%`#^X*XK>56I3Rod`yWE?tDkj^7Zr!I4Be~ROz9A+W-)qv)g14JJr8pPGCfEK
ztU!ZR5>F5W&|np>(i}pE;mdQS+oT^y=$b{#ARhRDLmLz8zs|%|k)Lia@<-qIcdRjq
zh28`wBp7l7`zxqZKnNQLFAUcqLtUo<&|Gz7Yx$c03|KSv2AZpIe*(=_YI2{_Zg@|y
zUAuw!==3XAK4vK&2~8^Ocf~DH6K;||G<&eE78VT6WThwcp-FJTY8XdXwwt<on{^Um
z;Vk=-P6n*SMcbaP4o=?T9>1yP<VxP%jA5w9V~<qHXqMRd1n?6}!o@Un*5%nMFV4V!
zcSvBhCRrG^?pC2(TlnwO&L^ST*={~~9Q8cayvvVCr-Td`mqrL>zsXRsQmV}rqw;&B
z4e!dNAyOD&iO6#vp&GCIMd3`qQV0&g1E*lK2&qXlGA9o3N=czd$dOI?zYT<*V7+8Z
z_A4pp@VYm=92Q`tjw4z6L>{DNRHMS*@k%K)N2aZe11tDG`nJ#1G2!2E-v;8odQstT
z3G7?=L_Pz_J^teAb~JV-hP*?;!#)arf{pl27r-Om5(s_<DoKO9AYzjs?+a|}QUcq7
z*1B5)RyA(mDI>uD9SXQ)*cUJlcmQ5?84q$x&}7mW@D2rBGwciay+aAI><ZFCz934G
z0opn#a{+mxppe)zR8$}$k4L7DjZu|zmcOH4t1`M>&35GWax#Lk3A>h_4r!|{hc+*3
zzw4-R=rMnHEmm9OyQzfx%V!q=eLu`bfo@<|{?FF-&^eZbK^D5mg(@;ffC+<Qayzfd
zkOoa`>-so`CM4SZBn>3S`&(tm^ysqH5xjfIwgq_Y0g5)C0pdpW=vLqJS-Eb$#D69O
zOJ?+-NnU|!gx8ZC(&GhLu=)|<egc;kt>)tCyzM+jg%AxRC1I_@S}OHQ$x&k%O%)c{
zrhy-*KQYFn><vePhdZ%aez=W)i*=XYLhLuvg~nlfV`AVvsK$a_dlv-Bxdl~sgio<?
z|7&%AaSf)sru^N@pH6FNQ@iPij^XK9W8#d>R@aTmo4=5n^iggE4gSb#r?P(Skyk^>
zq3GqGOu5mHY(9z{En1kh){%|pF?;vqy<GCSQ0Cn7KPu%fT<GjHbKX{iS*7>g;DJ1^
z@c+%k=WqW@sXS-WCcsSB{K!rL9Q=+zSF<m%WP_UYuj8MahF*<IBD3o2z95%#M@=c-
zU-^YG<0;EYf%8E;6pqZ&`4=rI?XCgB=P_AD_2b!EZW>V(PzUKhg~}Gj3;VDlG-Ao7
zO&{a+&Dy6i&0mjOQo3BvXB#p>N}I>K7;t-nHNHY0Ba&8TruGI1kwilXp<{Q2kb-ao
zAOZ-H!2Jm&NCF6P32KR;XM<D%2%*7+p5X$F+dai7vWqAs9KF{Pgpk%<6_H3?F^T2i
zz+H3Dz(#$y$5Fxiy3Ak#_HzP=nUHwX?lC1U^Y;<`<NQg31W`ie*+GT5<-+{-Qw7)o
z3HUz8LeC)mh)6zu*I+>egztczP%#U#|DHiX3kW_FNk8Yi_Fs!!CGCW6N)90M<@6)+
z>GmUbDTNStl)?y*7IUpKxHf##3K1AnxW6+JEbzRPc0zk6K6!W6h}nMec+UZyTH1Nx
z=GB8jY-Yo^Tsb;pMwDBobL&MwT;2iUDeZ5Dp&#SZZ@u;ejoet7u&I)uvm6V8o&T&D
zFDgJQMt34C8qIrkk}9@Z+%TzdoamUlhh3uL6KmluvxQ%%Hu^@Qt2=GtG}IStUR#wx
zk<@BiaHo^vW+dcrrYY*byC}cj0Ru%|;U&M09ihb$$p!kSnoCuH(strEE3iwl064BB
z**9c&5#E~@<WDt_Xv}M4D;)z4%cRCbYXx=y#ecNcn#t|7NMPd&800qHjW6yapD6YC
zU6V|^sQ1ZO)<f|L7@_Gv1lIw3O081~L!B3$DgK|m$ZGCa1!GLLB!y?Kab7sD4E=Nz
z4zne;6b-q;nH_;7HoS&7`@Z09s&6n(%;5Wk;SNHCP?D&!ByoY@j&awe$#H=}zM5$J
zggcHvm3*tL(DwzG^it!<*j=LYQ!W)@5C<gvM#)&@2GYLa948dyIxch&XFQy_$v6UD
zFkc-SQP2(04~B&AcMS-F$|y<xpEE+<>(v1;S?QA*|HQ=zzNl^I1)*4x?E>Xf1J3vP
zcs{rj<6plJNhBh6>#AsQbH(o6+J=319E^XBF&+%$I%AaWh*LC2L{&XKXEsjTbu0!m
zJd_zN=4TahcKZns(WI6#+^SKJvSVE&L1S?dX2xb*c-dK6hLo@PYZvsvN4v!AlQ|q0
z8kS$~ElM!YKLbr~tv6mVpTmXf(hrg=cIQTvWg0K?a~tp@8lIL8(0@7IBLsr-4?ohs
zT0`wZZ#lfeAV{CC2DZL}C7PTw;Xl~W?M}{+KhQos&jP%tR?puWNz{jho(x;B5;jbv
z8&tE1rrSs{%iovxMGxhb#Gm1tV0tsbJ2{Sy0NwwB04c+GP>bNuSXdn~hFOpXls06!
z;$N!oWTKzH{Ll(57Kn9|f#3>w(#3{$wjMnLzyt&smBK4v<R*a{QJTp@7pfboV9jj?
zeygNqU7(@pdFXj5G-W@^{-9W1G+S#?%a++>4v7sB8Jn6*Tj2mWCR!nS|3x*DJ)Zhs
zK&#KTVOaZOWHB9L*|Bn;K6ram35bJIA<Pm7Zv<r6x3D$XL9((WFgqAqCh+y@W=-4g
zD?XRZaBIN57UF(FXxLkU7=swofUSVxn}BGR>}a-{HNv{Ff#^2&oe4v@{flZ$-HF$o
zg=q{co1;xFCedYy-++b_e^7u1FjguA7ZD|!_s)S!u?-bwnG``B8_YQNg=`(bEGRHk
zgPTBPD)1}|r+Sz3>6&c->&i=ybO3r_*qXTN#~+!O!jWw2DWixJ!h@}n7hFKZS%TPr
z*l@v;a&ifz3DLc1c(2zoYNXQjMJ}@T+C(^cI)K@K1BMpXdP2&a0(+QNGE(RN>*s0k
zD!^Ie7qqh^R0BDN0LFp;<9F~{DNOz3UArdl-Yw<#E|7N!U>x{ksA7H6BU+5td)lNi
z=u{5VeqmJG^lqT72SYP#({I}*yZ83jC6O%|#$M3qy4Syu|I5S0+O;Xt>0MPOz%Xz3
zYxZka>E7ZKR@~sUiW@w>m1V&Uu&z@OTviV10u6!yMs-xJeQ#mM&Vz&9TF4}(ZeTQM
zXGww`i0;3j30xw<Ux2SgI5LP88(}3qvqRfvTks6F-T~ACYQGN|^6^&S=;qedjf>Rf
ztAgk&fuPg>2Izz6(}1ZH5H3X5#h*rw%csmT6WU<U>Vo|Dem^A$jq3E)!>!^Ipg%vu
zwY4ycn5t<K2tI&TV1zy*q>X=JzYr}yArav)EA@rRT`t{x2purutwHs&_OgZ|0T?H~
zuod)It(jz?_%?E(ALc7IEPN>d^MHBW004mP%W7~W_puOpNy28)fBq&Lpa`bu6b9-y
z|6YqslA7ULG_>TJVVi$K*u&X-H`__t>hd@Cr~kJ;;C79)j~wurS$=&-9P+t%jF^m^
zOVRph9t|M1ky2RK=sW11y?jaGR~<jLu?lUQy!|#wpPpdzFo4mDaLgyD#D4x~`wzaa
zMv<Iczurhe4$C`0V;;m8#P_Us>ou`l={ohN>;oxy$oy%XW;VtfB;28IwB?`e4wfnc
z4TLp1BA=x2XEE$ReLJ6~V10%>x;z^q%b-YZuRrdw=iscoj))@wL+@&kA<!X5;~u~I
z_gV!k#Xu+?FMsPIOh$J^^YaV&X4l*L5^+H_vB{1IXJtLI0Xu5}2bJwEgg$m`bDSB?
znw6~r;_R{_!PZK7GV9=iyk+@wGxx|xJeyX9T$RSk69sHjRhs-KdsbvAHGKm3rr5a4
z29B7#0^>S_A}KOjlA_dQYIG|IZ#xniX_L?rLH?_hWxj%ow}RQGm|kjZ^X~@56UOKo
zbi@VZ=}`saY(GUA>NUz9HCyPKBM}linitOd$%Sk-hgD&pz|dy|Bl9TflnU*eNdu|e
zJe2zhd6QWef+I|4)ljDzOr+;}zPAL+k2N*8>0;<Z!m|bjW|%4hE48IzP&lcCjb<a;
zjxA??WApIfWUz)zIz){@IMV<2vnjYU|09rE`Ijvx1FE;<X^Hd9*N&sYD$3Vb=~rZQ
z{c{S6IyXBqCGtTF1ox&Op6e28VF*D_dexdJ6>}M@MQpOv8+9_1(uI6x-frG5#F>1(
z(ywuN<HBuS>Ac0f#r8Ix^Q0BE_o!&uP;Br8$OU@ErHJg1w^O<LnQQsLyq&zAA5!1y
z=j`=h2-&gmEs<DpSvw_uVT9;Ld<l_~2#~Flnsb@E*NfYp-}9oin--oVi3u$UEk%a(
zVL>VqKfOlvQ_s5y9SI#tBN;E3d&j+uh#eH#1at&;U=$%XD*f`k5oM3Sw?&@Eo$r)4
z;0;mB-Fd=~vK6qH_%~*lpSPTCA9FH3n*V|chEEX(vJ0w<A^rjL45?D25~WJ{uf$dP
zM8IO;B1X**jp|7~<-$9Ryt}-+V&~6*_(=k+L-7at(#sump*f+sLYXHx?wF*|>V(Yk
z<aKZ|D6&!-_Yx=x+T?Xl=Fo04;Ddh?tAs8QVSg`|S^mTN!%xUhXx}FxqfD`CTvW}*
zy>-Qz4e!G(il)9Us;#6Cvlo-s$o?1UoJgl1I@7GLiBaLDiB&b<%J*eK!#jN_eJEQn
zA3m;hx}XL)<rBI;E+Fh6?D1;~5p(22E<450<+F^tZ-6nt7-iN%NU;TO1XFu7f5xg~
z@$R_{bA5^k7T3{I{vZby9BDgP?!>eQD2qj2`m`FaCp{%s<H0^9sf%(2v*fJ(DAwKY
zFT*}&ll$-~(l7$EOIMeWQ?^TjkXrP0_HvH^AEr$^0u>gv{3i%R50I8M+O-LV=fU^M
zPu;;8FBf!6RsDQ&mTz7A1`mD0eZo%Kr;Lr$g*~oy;w!?{9c1f&(=CPf$ZQ_z5MKf8
zZ>u)!v1d5!Ado{iGG~8GJ)>JRW|g_<-at!UJ7n1GQdrp6DjB|@aPHvP)Mwdi-PB#{
zCYEe7+a2?hSY)<-_*++`SVFNB9PhK_X5;%#IzAB+^x*%D-fe;B-V)57@;=%&7yizr
z=-g@&LXLF*vYY{^wqXQe^jDnJAS2JCTdDla|0(Y-|5EqYOp10=ci|>Ipt^uS3!Dv#
z4YAC<g?9Wrc|Daky<VEY7E>8tng4j|XmoO1_bxV--uk=1I{h)<vA5vWopwl_nx`JU
zLyHH21tuB+nn2!jdqQ&KlGj!;Kx-nF6)poYV~Yy6&8+q%-)r2uId_#)9iT4Q3+hPW
zT|=0IDmgpO*?~I8zYMx8%($pTh{fvZbbZupVg)^u(g)rP4oV)!;AH#V%-?=i?$$ka
zC!Meaj1ht{czT7<*F`}*b=gBae?Bbgf~ds34zeyJ&n}4v%t)ujUZI*!5MQwlg1x1e
zlAzr6r^`r2fKS0uHl@2B`Vz=8*s@43{w=8q%qfaeBqzVOYlnduEbtd0dm%yD<Bq&L
zDn(T&do<E-GxOf_-berDo}9RT|4UHiZl-xITr!g)^dj^E_BXe+1YeQ3W&F$j7h}q+
zoDHrFK!#8s6aqFbxe-)m*|iO4(#5c1>#4#dmoD{?3}&N>eW<YE#=^<eD9mEjHBj&Z
z%(}pzJ^q7?@drtR4sqMxgg)Z;Q)PdPqym*vY>2qZK3vX1^<gaGli~jIA%I*+A0acg
z=mugaYE;4U-45*#AU3QI+RaT0xAgsBQ?o=9(AfsgvVFN>at^F-1H$lu1kcJ_7tMQg
ztQ2=+7&|LdhH+wMNvQ7^z0akc8xRtY9o`&8@q3lCsurpat}e<^VY!ewnGv>Dpp+<E
zx!hrkBdI4Z%m%lHQqvqae_>MLlYCe@bd`Z>7oN17)AYw;LcTO39wT1GNmAvEMn2x3
z@0v9uA&MPfZy;~^xf-xb9yJ4!G#)Oadj)+b5LNq0N2wd8J+scUStW(_$KRUm&S%sZ
zfL1txUcJ7tBU_KFsS(5;x3Lz+7M**XrWzfUR<^eT{R&lAO51t5*QOo?+OxL0tLhJ<
z*DY?)!f?l)s4x3+jo;C?%tItdmq&ANZ<9zLqa{upAC%4^N=4tg?Y4XDqaVOpRGOMD
z<=prYSmGElt_&##^pG2BU{==D(?zUs1cbbKMOg)YcTITc))*fB;VO3GV_@MO>^Oqx
zdmNfJu_}C*Z_mc^hihOV&VQVgSh<)t5qAt3cP{XeYosx<qkqn(7;Yfn-;HU8%^sGE
z&S!Yapd;}*ay89jYRE|{;)8+LcBzhB&v$I#`x%-z=_?oiRkxD&Vd2L9BCueqf>k<F
zy}GkrqGQjZh5GT6AbKn?=PL)MFvh^eG*O{>ZZWd8MPHTD*7R@RF~@A@oU7O}awjr#
zcKX?T^*FnVGw+O=*VW@?4!L{bg@kbvMJ7$RYs;~9`(E|vsdn8g+dxO}ROPc!856dm
z8RxmoPcZK-X7x3#PU-#AY1MkmKSb!=dn0&GKUWL!ER!=%g%^D6d38kW%Cc7s%4E!_
z9>Rt=khnsdq_of7KKklN7#>q>tWDm(JIRIo{eAK<8Wx}HjOnlua@5a$OKox?N$x=N
ztCG(FY%{R$ynzJ1PA%MYfgOH7DKk4aqwA9Qc=dj636(4TvXcw_#oTgCB^o`Q*(?TP
zvm>y=Rd}6lYIJ&H)QcCok&8P`!j7Jvfjhy{@^1+Xo6PT3FsV)}_x1D6{`IW>Ifu%`
zb^pam8K?kUiU?K?ht&&?S=k@>3FfsbN)$IEsGvygX*1}zPhAa3)!8AE0rXOiEH(t$
zOfH{ZNRW6I-1j6ek`z-g8jc~GvSAG<_mkL`js&d^%tYY9)4kkIyj62UyIF%=>oV{!
zU4|}2!G?uB9(M|TdGlCNL37xub^VMKi3dNZudd5vSp{r&;hjhRklM<U4+&7NtQQ0(
zHO!!t1esJllBSBKBefkquT*xY#N?)^dDBc}Zd^O9WK=MEO^r($8VeD`cJ8F~6n@zU
z{+^9Asa%`1pH45h>ql^B9y#He;K!q^9~`~My+RcKoLOKc$**$H8Xq0dU%iQ@cA@V$
zYA@Yo-eD9}EohPC?3bF9#{DA5IbKZ~mgL@yS7jH%NFCMUP@CI5pG%(jvvw~Cq!%5c
zJXG1qQmH<_som{x(wH3eE4zkR_&$0!I(;DIJ6=28|LLmn-l`lR!#__f$pB`B{osE+
z_((6)Iz@lcX1RSL@Ok+vzO;2%ja)Yd=5hl5z0M#203&NFBWFiz1}Ar0XLA!L3nzyE
zX`weZG5lp_VQXp!aLc;T)N)$oMDsaPGf(F~=O0XCC2QK7CK^JLYom*EdD};BA+)p^
zO+H|Kf8)CimYyK9X#HK6IO#mpfh)Py?j<fh==O#AeC!_<=IEkQW9fl~eCQb4@S^f!
zJIi00y2T+C@`o5j#+#X#2m^%)H?Feb%-5m#dhGa{$)*aIrf35ALG!|<<pOiYPI=y?
z%FEPEsYAPh@Q|IES=q!7KNJ4%<>_TE<%L^o^-&O`P{e545RP1lY0N=<u~Nr>_zSF4
zssMBsh|Vr4wVpM(J&X4lC3=<%tylE)TU}gwI5z!?-E!JwA<u9S>yh3lMB}{8Fw)`$
zGQ@+R`clLx_U&(f(0C&Rxqc#sG8O@dMCgTQ?cMVX2wv;ZZ>EEr!)xPZ>@rNKPh|d<
zk)lZ5gS;_Wth2sV-~7B=WTv(V#l8*8LmadkuOmP%OyF2RGQdQCz*Zat=FBBLn2YAe
zNAFi#Q)EaNZTZzVfVacfi{qC`FEaWJA*$aoWm*|g34VhhROxyWvtwJsc=*=1SU)rz
zRvHa<%8(OSvGiV9(Hfe4$kdM&8svuO-(`kX@fa&K8svi_{TGF=+kaP3!i1o<>QS-H
zPpN(~UML$CGK};jfy)KM2)l|X$MF(%9G3AmI~ECwvE-s!C{G66B44#u#j3-{-A5al
z_2~uejRXbR9Z#IXGSqYGO1Nm)t((LJI#HRvmtJ(dPMVl*!gF82(uLvW+?d`SxbJ4b
z*NY>>GeK4S2A*?Hxu5khhNYiJ5uKYp;!oQ8sUx|%eaFB;2eDs5ggM!n<v&c5$eyxA
zqK@gzESGpq@zEob?LnU7-R=AcGRHi1Fuda0BSowowOzhJe8F)H^Rwn8`Uh5AhPext
zKeA=vr7I-a={SLCA#$m2E2lG6OW4{w_dxa@X+`A|tc;R{@3RH<d(-%|7~$cdVaL@E
z3b|RbhmkOkP5{^eDv0$#1}?-iai;ERSv&rn@hayrx~dx%E8VBE+#Hpz3#f+fU)j!%
z;3^8O68o^+Dr~HZCiQX+1)3r!6QFdl;7Z_Bqn-iaFW7;G;i21`WJ1)!@)HBF<&<bo
z@q^>RYze}h=IJR9ee86l8|Nz<a-#+aLqpw)wz<C^)68<cTX3K|{1fKaf)lf>z(N&P
zFqPUk&NY++SMbtWC->*3HJAFthSpP<eX(tctS$vTkKaFjZ#J_zLfTLWG4uaKQ|&p4
zs*2&u0i<l^J<vocbP9d>-Qj`Gwl`+~u0H_e{ep&wSo`B3ZiEa`FxO0R7(Iutk;3ws
z=7pH&;c&iLXZ29^S;SQj^)WZ3;Wp{P{B85W?kzC(!w9_j<JZ2ibyHPCq-1IXW6FzB
z`&c@L(h1U`_m^SLWl6&sc*4P{4tDUU4sQH#oOm2>X{6y_85FAhWt1!_MUKb%k<u!Z
z`jGMdf>RjW{W3}$a_eP7<LIjn)Cb*~gr}5+S=wkg+#k-9p#8?PVj+q`BqgiL$u0PQ
zoZ@D9sb{OBrI>SMf6}FvnGZxIU!l`Ie~WTT4H$46{pQJ~btO+|-A;Sun&GY6IA!Cq
z3C@mZMo_o!efkAfC7~rJ-W=Q(^KBjBb#+va2j;vdIGK-~47Yi*g*8A?cH~{gokax#
z1IJ$ui*ZXVjzOfypwz$nRD!~*FsD=PsqmiU0xhr6tA3w{$Dsu;i}+|=1a92uMYs=&
zl5=6^8&r?|^*5+oekc*vEAky7^iw&r9k2F4R%>O&1jXEZf+?!8Hm(DS#Nl2t6|%-n
zg}<>~yXOlth+kDETKo#6Ca*}XR&tICynM8o{AyUqUXD}>Drm26`S|)c6PJVMn;D4;
z80ER<UPbuvaeT_BS`&(j8q^kLGN6!?nxl8xHQ^iFTwCRd&CU;3RAecC%hlScU%2#J
z6UNuId_^gUU)Bl`tymUv!TlR;?gs|bW@?%0`F?F;1>4U|F-$UKU@Ua_*qof|HS79n
zSuJVVoHZ*@$uM9gPxP2sCVfKYwkU@iY(Sd<K=A%EJ*Xl901kRi?oR*9<nW)*^o}NG
zHU{?p<^?<}yLI+kr#l+x!d|l8)w5<Ni_;Ez?P0!i9XyK1mac)Fx;(O))RCH^uml3S
z*DX6!38{H2H7gz*p5z(g6j6jxcSJ7St1o+&+<F>h8Z5{yJGhn>jx^}b>D0c1C!C%r
zpH;7}n}NPYZ#`{EIYx8bvM!v5k0Dmcf-ax0*H@1-4_BHfhBuzIwZP9FIUoL~62nOj
zlROlBH^V?Gj~gq4D4b@DAiEdsvM^6!*B7pPH{qW#vXh}lnMXa{SZ54-eQus-VlOz1
zi2!aqFWgG4=B?7L+zWBylo{nguM$`}s42`3PVZ~qlh`gsiCuekRTdwzA+Hp{JEor9
zM#gD6xbu&1HG}zA!@}i(7nwG9ja#l;EIe>a3_e-Gn@~LLod^`DWGLs|TO2({1j+9@
zxSg9<b3HF-$~V#uNRiUz`nGk-AN?`&wK$dnR+oT=D}-YvPdj^NFC%o#=Y8q#6VG%B
zN89h{9#dHC&U#1H<$?0}gm~eu_9L@`J~9w%8!Mf0FknUfBFqOci4jDbUg(h5!i+@$
z&?tZUVfcDN`_c+PT9=`9B?#Uqxl&p18%d3`Km^<f*j2cf{Cb>ts9fk0sqPMpi46g8
zVB>|1y+j_tt$m`pB}_~>-z-+A38Pkiq{(>FMu-SNm`-{2@|v?YL#W#?o^FpL?a$}`
zx=Ef(G4J}VM9vMk;WaK(xA$d%Gi?Qk^f;^nB;wyA8o8cd5ho_D34UHpeRSV7uO9_f
zA~M#8zcAUHR7<~yqp|3HhpyVfGfx>cE*t?Bv~<0AF)CiMo0ThRdOy!!HswNpeDe^S
zikNDFpr3H`jwVeC)@SAA;wQk%>C__sM#6;w*R;xOi4yW#D&SDhg$mSQnc2U-3F+8&
zTEt6+jF(U(fKtDeFk3GS^N%>pwxu2uzyJ3J-&_4icn|CA3y!r5jmHCQ4fIs;G;NY2
zQzL#VNEe@+?>#4rZyyDHTDD(9o9AH2g!q+0qt7#E57<3@l~DCQ&4;xspIAiz0n+jc
z<oAT{tP|KW`a<Ulrflk_P-aRs>W+BKdNRfUL&T^;!4A0<CsDUFat4p{^VHU#1sw_Q
z7NS<+EVV}IVc7o<UGD%RN*An)j&0kvZSJvc+qUhQJ+|%HW81cE+w<o9CpUR7H!tZ<
z)vC3s(@A%_SA8W1+EMBlW$Fx-HRq#w8#Uro(LS8)Wl3Yqa=LbephIj3#ZX{ZUR2Fw
z$y>^O|C!#&(pPGPfS`rE)f*zXmQ~8uqQ#4Sv`$Fi*a+&`3f^=0LIUf&-D)s+`NQal
zOmi~c^hw)vc4QtgBBEeUa-b8TmLXr^!FhXCxzsg4U1S8aUNKggGV{_boGTV{McHbW
zW<vTGc-{<H8MLv?E=t9UqNxfLvTa*ILv!)fk%Zo~@{nNA`w<HSfueg{;1QX@6~%lX
z(S!5;)n(Vk{?Hjg2;JSk;He@*W&&bJV7H*m4_Z>K%_3M;AtF(;x<F+S0P~o75t={M
ze<C|gDvz$4G_NOIFKm>hRvGpgrMrp_D)lb-=)?h8iQRskO-gA4DjG*?VqYZ*S@aVT
zDopRzpd+kW@sP$^kf|10O_E6rF;b=$;gPP!EC&dpw6era^5Ug-;+LF(34&C+pzc#<
z#GfaRTR^Ji7`1&s2meOB|DB-NWL6Y0ACi)43hNm4Y5q|b^Ec?at3c2%6W+{cq|XZm
z>(Z|7(;h_|5-3t%<p79AgI~S9^r-=nf;zK{<OJw@Ty>r1*zm-G-G&cQ^>c*)*}+*}
zPv&?o)mYZxzG{ZT)Us-g#v3iHh6qGb&_88RS+BlT@IE0xh?E()@Z4}BEct}OLNI8m
zcgTVfwg%EGay|ZA6kzz)yQ^Z(KH$zOfg!p+&?`%!cS!t;O=Ki30S(fzeO6AA8%1&D
zmX&VI2(hF#1tc0PkPC>)iJxzu9tQgkdsl?@+^^;W?p@-=>O4Tv{Oi@^gGwQyU5PB6
zeE@a?`HTp7A}DKoqBsy?eJxv$6Vw&q^WXWr<#Nx*O~nZ&2@#m4;$6@Ugm?v&&lAuy
zoTyL({@Qzyz?ccibtqSb;aqtt(>h?{$)RG-xQ3)P6pS)jyCiquaC4*RWEqZO(SOJ)
z>|I`cQ$6W7`!lK)l{TLB=soKXN{E~kaf@{2Zj^a-UKK^V@o)^ZV(PL@;>Z&&d~$ny
z*3r>eqDn31w#ZmwBCt@G@`DpvcL@$mF!@`^iPQ&~d)^w0V#aBG0i>dc9*!OK$_2I$
zC)TPZB!F82I)_;5Wd<?&DQlJ=NR)l-M7j4sC*Arbfq9Lo*5hb3zx6ZKCUvLv;JC)m
z0--Nu2r&c<c4tErxynSK4{Zo#C~l(cEEwU6D7^M(*3>6j?%;}FD+H-o>KfXARR;>D
z|6k~gF^mz!0lRr>fgrj6VrW2}t_Ub!&NR*D7Na0v1grbdrj(+&i5S?K*zR^UJMals
zdwgQXy?#WclKO54fsC5Gvv#?&?cZE5;SIjL^+*3!!Sb*vm&L^73efY`k--@90+KlJ
z>$2WIuxvi5q`2fHbF9RoXu|Q4F0*?a8BxcgA4aE*>i4gTdxeGPsrzNyr}B@cu)QMN
zz2R)JKBZxb3AZHS(KEe{tXb_<NaNR4lz;z~l7njCE|d<DQ(y+0VE=nj#tAx#G(zpX
z_7&@d!-LdS=`Cb~@<8pR<2d;E>%JuAA?@y?@B8&(HhA$H7TX-{sm@Cqz>aVj5l1N!
zpSFc4>oN=)sH{}SI1G{o&|pe@ygZDw{zLzPI`fbJ@*$Yn12ZqiPl1V^#b=}ygE^(|
zUf+Jn$+|OJ$ro-f1aTcD+KZ}J%oL&v2PpJ8)0*lP()^Fqtn_Th&@_wT<2VyW`qz>;
z#=jh(Rsl>nRVMS=<?&JISag2Y9=<xD*W=p2mh7;hjf)<rZC89WyB$84&MoFRQ15pN
znc)PON(q`<$1X~mrNJ^6Qu}UB99%jnEid5aT9y8FOnZ@LFDW!;GzlzlTW@Sai#~*h
z!PRUC;7^8<AYmKy9ay<1Mpa=12*TzPyeq|ekJBi;?B$g>SOrh4Rb<Hw5yF&`W|Yp3
zg(B@ao*keU$}e@@bT-e|rBazn7c(E74Dl~rBU)nsH$opwXvs1Gxo`qQFK)XI-QmJN
zw;1e<2-wq?m{Uhw{M&%^5~2nIWktAJUxe7?BN3TA586TA^}~<LWJ3$G7d+;=d2;s(
zb5p2u@?J2aW3wdu^8i&uArYK^C4K^$?S@>YqX)g4i-({4l~&}EV^{s3KS&qnjYOGY
zXJX^T1{PYRmXeO9RJkmbXQoVnrJ~p)47VZN4(wCo?c)>|7Cu~Ee{w(~5<_tuSOfva
z5yrcKrxCMquCdj(0<mS<;1XqoEcU?*k0zn8(8Pe~Y<C5Z9Jhs3R9vEBMQ+)jv)uog
zVJMV#cU<Ys5~bQD0}=t}dhqm`9|{?Bs{FzLNdnRacxa1cw$ZB2enFw*`#73>f(3_k
z@YZg&44bhsV8m*R9v6ufd|9Vk#ssugmMJ#LT)YS~8@we#Hge9y=o16o$Mm8yxSsaO
z7T`>f`AC?|rZK?&g+_mz*2oeAAi3|@E!jZxMa~0@6H*ssIOBq6C<__)BE+6UHmmBX
z^08@-rJ$UEi$RIe6mWEhy|)GavYICGlR+m`mXXqZA{2c}zPmri6VF`Nm_?2<LDlJW
z7uUsDiYDK}1rtxd!BshbnbFGXHPd3|bm8aX<osBrQ;sDr*%zJ(Q+qkmAvN~ww@S_T
z3o?W>Z3(8>Cj3(nS*a+Q@dgq;_jdftLn1uc5e2fn4j~mrR*WqvN<Xh1Q;};}-DX~g
zRF`FlmiDAJ)`U^5Yo1`Wb$>gRfleEIK!(oUtkVD6;2kBq&Df=080OO){%<%F1i4c4
z)zeB~Oaysp57env&A{|FHr)-j$Z^Jm$!Wo96&Vi5UevP2h~2jX4<DDdXZhu7kBC8(
zK%fY9%u}I@1Y#wSXXf-%J}woYLx}hiAnR~k+U}ojF$@k66F><4UN{SQlZV41(?&dJ
zAPfKF{4p=avm|NR1_gy#iyQ9cf&1O%B`cQ=h<8IWZn6|1w2dMwh$adD%hTQJI%j23
zj&QHwm;sY|^@Bsm?s3$(K8NFvIwh}(yu`nQ8iNNSo|L-EE;JIDY-eVQ8h>XbD4|;r
z*Zi{Pou2v&W((6q@C_#jR`#Y&mO-jr4X8CiH}DOTs{*@t<~F;Vl9jULteE#)tx{E0
z6n3}Ki+XXLX;gNK<XON`3-rWY{3s(^s+?xx#1HVp3Qee9P>2{4niQLVAeH7l+3v`T
zYCwI$W|-VQswWiJ%{C4B2?=dqc{0xYqv`SkO59Zz+Rdi%2&2c5u%v_wTcuQHy-AK;
zgV>TD3h-#BQOM_3)aE8nT{4>9K<YjJ9q?fXK`Wv22Q7w#%B4VTwyjYJZcz!&X3^rg
zRjMX=Pc^ha6zBGyalXI3-ol99c80)YXoa{X2~9OEVJA~d6|i#o->t-!CGTQC#1w5+
zhrCgQ-0^ua#K~j84pdRZf~As)5n{+GL1gEKaR_GXi#e!)=T!pFE&-mN130??v~vNd
zDE=?i!3Fqe`2SAn;QD*rnf|9CKVtkls(};uzx02_a&asF*UWNYOATD_*9Ab6#GiVb
z>}Yg{q-b*Hni3;lR%|b-W(oSkHz~VM#v^?xVv8TXMd`ouF;K>q3vHqCQFd?K7&b1S
z9hzd{nJop3hyz&{iJIN-6;11I>+R>CKbtj%p^QKcsb~|FaA_;qHz4vS&~SYWSo^fg
zS*J*gvh_3^Qp}T7Hq3m}X(fb}#pQLvTJ=5HPiSvPu!{ryqt4{>1{q&6NKW*W3G&k<
zw+z_b8bV!4(hkZNMfCFEm#<rMZ@Z{2{d#&`G`%X+@g3K3(moDNy2khC7PueqvX^aX
zVRy8;d%HQ(w)lT^pG0yAK+$h9Y8^+4VuSrJ9n`-M3{atBg+7s;oq-|B0a27Ovo#TW
z;U3=ZX3$K(lAl{Pa<mz^pg9K8PIh~Ox~_ia9Q=Lh*t5d;Y#!!xiDk5KXSw}#UaB{9
z<;xuSr-RFv1FZbA97|oUFR#145200hoeZkj5j5!>4esZmG#fdgU6QHET!hF~-Vy~x
z_wOs$OkRqUJLe$elvh*mlQ^YYyV~nQ0x&|vx$K%)@g?nZ=-;fRD{cacY>GqRp24hi
z%F<Vil3P)`6gl;%9P|%Psd~Ixeq#ICZ-V1^N#v$S{4nn(Qrk@dwdbaAsxYYBl`vzH
z(*ij4$il^E|DKf`+u^hzcl0C3DSxUu_FfbCQh(^dDULAAyWev1OmRc(bfLFDXlVbI
zoc>4e`~v7A?Q!C~1nrM*k$7rZt^>JL6Kts_^p84!Jz3sInY5@Ksp9_#pQ7pze)(sR
zbICGSQsoY$ia1F>m;admvt+5s#}caZKjkaQvKp=P|D%3>fH+(eT=C_h`nhcXHs}$G
z)@r(`#`DS#%bw&J@*f02@E-(mx(WFI13~=1(do-BE2o3jM6%DXPbitGh_siOG*_tx
z9Tnb%Qg({O#ML3Kgugo15wIY%b8K=K%k9d^X0AUUra(m^ii;sklmRr^TjkAv5F)_S
zN2LKG25WyVKFrlW&ZmyQjX&euVk+M|GT5)>z`kGK@NYb2KT6|nzE|x0K2-2#y5<gM
z8#~X8o6BOh5?<om{1V<SK6S3-{CHkRxL=+2Vzx!k-;XNpYMu}Ira!;=w|$!NFWq{+
zs-G`<J|C5;dDCMyMb(=^Nv&@97p;EuyxP>KJ8y?N*&Ow(zQ)}5-VZXkF<znF&*7}T
zUn7<QdTPFZ*5&v^p4cv?GAqTtD(3wCet^G!rfd$Y0aReabn*EsWpXSF$MiWLk6GP#
z1c;2DP4T=LUCaO+_ojgAzV?cKN;xtoPi9&Bd$aqgL6kpS?zo<OFXY73t`TzD)E>r~
z;9a~1sOeAtQELp=2G#n0rTYft`nrTk-L%x?Nx7=MlKi|gd->ObZBPE3!}@wThB@7=
z<PPM%j$?PopY65`Swq_O>oxKDT@S?V%DhtN9fs-E^#C5sP{&(@gKw+#+=w!KFMOTr
z!fxF?BzL6=(pv*qEdJYQCuy?d+YZ0sZkQs@Y39BUtJRRV=uZ{vvT+5$+gnwd!FD#i
zCO|ISJ^>?rJ&jRMOPM8OMDYq$z8%>)dOkmZ%_?*G?elmU131^O)MeK4WBE}Cu|G0q
zeA;#Zi$Q1t=iooA42B5t?OtDw#>c|n-P3Kc%zw`sm=l&H?q=@cWH+ZdEj1pN+9w~9
z(CwVt5{+xud5d1#i*EOP_}uk|+UT|YGL&2}$Il(`$CdQy=GM=^1^f2KSV|#Ab{Gyq
z7j+f*yVq)ljCcrTD}+0XCpRmp?GLdh#I^wB8;OV9cN!PZhw{F@%6$c^MlAUCrOVeH
znB(-I+o3PIYHT)?5XW`TwF0?I_bXer%r|6BAsl~0+Ag}^T$Nu}_q)~mAf}XjgJu$D
zJRAA!kBLgOwa~oF2|XgffCLovJ#v}1X7}xJ6dFu0x<$H1m3z>B9FNytY>CN1pW`(r
zA+|sG>{3aG|H?sPG??ijFoQl*$pB$`&#PRNefM;Z&E!hy^*-qxAZY}$`B>(Q**CFl
zx)ld>=sRY5C6*J3WhI$FLi$U~P?TDxhaYV|ahD+MW)-M6Yi-{lt|f%#Y1|34+h!Qo
zX{T2bvW{q?adtTG1|thmrO-qjh&ZG3dR^B6k+CEI<aod*qTMN<Y}yBw!6KdPmHrZ)
zZZR`;U$sx3%z$e+4dt{JfgJe*=w0ukBc%Equ12bH#Gm_YqVXbH^T_vjSbFJ2s~FFm
zTQ;0v;<+vA#0Am<%kbO=!S*Bcm^D;u4HnN{j)@c%jY*1Z9wKJiUpp_%h+~KtM-+WY
z&ZXegbcWDI>U%TEh4CQIa(T~hGtjCN7ALM1M#=O!#yph7>^GS;g{+LHfJr5p1Kw1O
zM`(u8UF4ySyi5}NF*v^^!uS-^;0{89g+*!ErY|9G&bQ3WUBn~`$X!84aO{-!KD;=n
zQ*aqU>+Cd8lT;)CU%~eeij3NsGc}MX>-9w3AzahHK@gdX@>s(PNmOH*IcliMZZ({G
zsc7ysqFwOvP@ABDavVBkzi6+cFtQ6FsbmQh0~6==FA2u6Y;$D*3DPxWz+|7uKH`FA
z8Yx;pT;4*n2vmSYB<F}4EENdJkdnq`i?KlEVo{W_))mMg6<>zts^$pNjRxc=Eb9)U
z8etsW5dXQMm0o&3g6imj$cbXV_CrsWBCyi<jHMuFA084}#4TmGIh!Mdu3DS|_+;V7
zddG0zax|j1s0X&006lrTTijRBC$O7ecIg5CTtx92MWQA;YJ~$$K1oSnsu0kj?L}IA
zE+L#_$VrKjrv-K3q1(`%PZ?%rBy#VqSkhgnr^7Km))nP7#JQ=mm%gat4ax<LQ1-HB
zei{R7x{`Z^15fcFWr4wxD~)QT{NjMnA@a1uG2E6q?9}H7!KVzTAny0Br2Zj<*t&xX
zcJ=w~qAy~1g8K@p%=r0x*vxnk><5*ZMr(E)Esa?z!z(s=#@ED!4pQc2RsgnFW97Z5
z06*qi`tzy6&eA6XHEBZC;*=ctfcY}w-mu(8m22t-S*XLE!T*2|Jz1Ndrt)@~O(320
zVyS>GS5ehnQ~-69Q`K#p13q-q$0|mD0*{v=yn+8!K)i>iC<Hphkq7042CE9p0R>hS
zoCyT1%rgUYN=zY8v5#idN5wH3sSufFR7p}oRSsEN4DzqYSg3@Wt_E28h-_^II1+Zr
z^R9yXt49R{${ZpYNUSUe9XuMXJNzeQ-hU#?zXfM>QLeY4qKXLAzM^5AJUrHs96y1w
z4W<CRs-H!A33%9XSPez(h^*sEb-8KFWH-6IqCr=X9hfBEWWNfJCBU?_a{ZQRLy;5|
zQKx_MtY8928eu7#(rY4+#;az!fuN%Wr8E#3CFQ<@3XWG;DR~WTTI#Sc6nO?IY~_j~
zJBJcd1xM~m^%xb)wtjX&X-PXZf7V)@jT#CzG}S?`&qHk&O?Cdr=Rzmiq}QDs%Y7(_
z^fbFdBzT8#qG(({Q955!gBVdhB=Np#PkDD49fNxbi48=V&;a_ytHLFoZ}V>@8Wl>{
z(h)t!gd<HM(25jM6-4eI*V1fpWnQg0ZU&7-6d6RV$Rc%+?1+0{t(_%FmSUN8NmSWy
zNVh=C)7B~>>opXb&bvk5QQz$R>7yZq|M?c-vW8wkv?n=?s5^hN=8V@bSFP;sQ4!Um
zrKgJMZCZOdbX|!$ZA1+>qd)!Di>n&O!kQS>>(D{frM)XrMWtIW?Kak8IIBHn+gqk$
z%rm=?Vw;lbHf>3niw_aG2s+I>1g|KclbW`?wr9kJJ0tI7-Dd3^w_c)0B-N?}mn#IX
zwra8Ju2Bt5T-<-jSy@#%uAC{5@*AU1LWf?&dbHRVy1-&{(a~$wO0SBxDJHK?1|JLl
z8RDh|6=v}ydcuVk_|v^!Lz0KRze6_2<jH2ANixt;4Gab^c;(*WvfA5GO$@%hq@;m@
zikt!O^n|*hA0r&4*MyGRdQ8@cx|Lu+MvExXtt67(1S+F|Z~0RQsb?AU{u9Fp$DX0M
zzOqSLcgl5%WxD|aD5rYq-ZCdw*&61YU8kEX<%5sYy>>^Jo!`e;dBtKRCB<FwX9PJS
zS@P<I<w;@ZP>hGuiDA@eEyijJRi+uRA*GC`+U!=t_IRP`FE_@$#zA$K-xb5(B3fwK
znZzJo8b~fg-OyC7k}j<{+C}?b_@Q!(t)F2v!<j%q5=x>jQv}ftIey4TB3k%bT>WuW
zxIJ|nGVGD_Lu@{Aqx@|Nwsj`^OJjY%0v^lGUF>($79yC6zfZOWLUlU%%_Zs?glUKW
zJ;YnkBvC2TXVbzLtfr_uqjHr#LL8fs@iGy7reyrHRxzI?r^!);AaNQ&MHsQ(W)c5t
zBVPT%K=vmDex(#ZNKL%=Dq&WIDx}Zsb>B-}9QR8#AVyYiR}=yHPQ;H^Ja22t41L~R
zWNWL5vNxj=a3bp(R-w-PUa<GzXYlq<PjYK)AZzI6q+R>NP(`xpTp(8iKYtT-bTeF`
zVmhWLBSpsBoR)5zV7tPCfM|;bv?5>Soo5ANbGBqKPiBX6j>WtI;3$(!CTD4I42Wji
z&kR)yAEVn62X-#``WQexpto<~W*CBUD0qeXNO{Z9dx@V^_qElhhVHxh>rgT#$>?X2
z-|Sp&NZdn)C>OjyK@cbiT78ihc{(XKeT)1kd0O)bg|GvL-=cb{V{d+|YI97KIPN`(
zqHHs<XmS>QSHERt3&^}(z6jT&ekQ<3QJ?aHi25-{nOZvvs)F`A+N;Skp_tGwMn|dj
z`<`qrNz?c-m<o*4WwHc@qE?VutD)I@HHYy)gf$m?5Vi;qUpV_a^dE)E*^=O~#=rww
z!Pc4NgA#m;#tBNG1pICJwtZV=DyC!@Q#NdnaPjonJsA`;S5pD!7l{D4E<3AD&gDz+
zC{gBk5evgO`bMH9U@IS@%BhH0IH=-bjPp=%L_Z%9=6Wx{V-AD-$?wt4_1!7mgK;wq
zHA06fBzaaB1)2~A`9~(evLdwyr8I=i7%Krsk1HG|&@7fh5vA6<T64f3z@RR-k)$!e
zi-L6H4Y+NNCM=~FqWoK;57W4ID#ltYFIs_x%+Q(?<a5jew}F#7uUqmO^@r=ROvcD#
zV#uG?ZA6^?B}EPewaxWJS!c&rY?f`2xs(x}PzpQ03lcsJceE*<U3lMEv-hA?!GrUt
z)e8*xtes3(%c7ZFuGlDd|3On}-VMt<yc<2d4~$&AJjL~Fvek-xBfC5WO7xZ1dFJps
zX9>=#EJyQs&U~)?&mNw=jP~Rf{_~Q3#gA>-Z&}T+o!Rc1R+S&v4a)C+Q!rBIF^5bm
zGOaoYg}0ezsjM&P@RHtpHCpC-cTH6Rw&za`RNsQlJA$r_#+ychq_m0ZOwza6Eywjx
zP3B*bX2xQTgDrEP#YJ*FmPGjT%RX1TsBT&2{)_KzV<FzL;9$dOehX`!a&gOb|5Q^Y
zV%!$8$p`t_^$~NZYTQ`ww8G{eR50ETVtM>Wy9(%6uv#2YU5&lZ+%ZQ+9Xd<>l3l`!
z_@BFx3-MLpdT{0$T$s&}j`zoQiCn+TH)wiY=lA_UtnBD65X>?Fim8GAOE3AwJH@;j
zWcc$4@V_Kh(3O<tP;89bNbCX8Rw?WH)3liu<ILM|f3fKnR~&XI4&+h0S<Y=5iL*d;
zu2$YIHu3poAZ*lNMr!#-wsF_d7jF@rv1#S!`&=Rap`76s%FZLtHvZhrQd@y!>NL=u
zPv`g*awWeSohFjE+*C&$OaOD)@A^D_=x*S?4XjKWf?RXJcRh(=dOi<tPwKc=yj(u(
z+4!Mch5fI!A@gcrG}B$$weJH!PKbD8>Gyun$G`nFCxm#K&cCzN?b+DIkNI<;bC6nj
zJ2?73cHor9o#n5&clm^V+s>9PK>LvK;=?6q_kH*8c=@;NlH=*p=biUnY{2n?v8q<5
zyI&9+?dP}S>2yC)rRsF8<-S<)wY&e$TVqf4#8Ph+0AyNUkdaCzk3m4wy6<}gE9cms
z8}3hD*RTOK$PVAhcpH;LRoQFfBRbt{l%whfoRbr>s<ZvE>mGMvbT0KUaz=ITVGB)l
zNV8eCe=~b^p6}#att(DqEu2tsU@fAxS)zDO!J?=Upsjo{<U7M!t;_3?wxV{xI9^V=
z0onl@fz*3km-o2S(9vuO1rZr^ezx=i3Sq2a{2FS~fjyQzhI+jtx0GMh0tYi`P(Lz)
zwfF$lcy&NKpMCpB>}lKe{Hp_)qkxr>->6Nj1faAKQ;UQp(X$%j=Ch}9me?$Ae7TQ4
z@xuY(S(6on?B2q<D&wCnn||ps!%0WlcsyPY7_;BT&PQ<hbzZEw(jT)v+qaQSKjZy=
zKeGH10rX>mHWMiW^w&{u2Rom0&k7FQstI8DCxwzh<FWE33w!aCVb?25(E!HQ9GGD<
zR0TqUChs!`3GA`;z1X~-K>_S(ejPwGa^DX~B*+wcZ%$L#GN!dixDkwGHkrp?Sp*5$
zMSPe$GNHFtr)yDTlRkW?2FT81KqDhsyS5mV&F>U2L5d&A?8u$e0pDh{U}TbgJ0T)2
z7Li|qVddSUaj~oOq}gl6oG~t8xshg38>2%owEl*2TPSMyB}MdVv_BevDi4=aig~Qt
z4+ltg0n6AQQNTR00_G-vXO<n=^k#1q33jkkjGbsQ2kfpdvWR9kZytM4HOSu-I*(Xo
z&wsiR$su{5Y}ei)1|}a(pD#`wn0N#-eGf4wCd0<Y3F;h%7nG=eo-0+Z38%9oj;Hs|
z*oL4|w)8q{itK%hNpJ!Z^Tl{AqszH$WKs?SxF5RO7-c6fB$+QHhE~A!qnOerwADb!
zoi!WvtDbZ>Yrl<E5u+d*Tl05b(EB&CIy=8saE_i$m~c3J4QCEnblqbq$}&JOKh6~>
zv(!XBKRLsbdGKCsRhrK~J-kk*^{9f#+Bp<qg;Sc}6=98q{Vshn+ZGxt!*Lj6HgCSo
zIhlCnkq*ozoWQ3iac6YS$)=$d&-*5jgE~fbJE-y>M#AAX`B-!tk5Eo3C+g2*a?$C*
z^{woyFiP)S7A>P$qwkfsLfEf+QZ}@N2wrM>>d^g5$_$*T6rlV5?nGpJ%<$DfP#C2#
z1ok(6oiMUg5_KzvPpi}AkS7bXzo1Q6youWH74Dj7_1Q1)6#1j-eF($w?V>Sqq1?`5
z(`z~#)DQu^O<}{G8Agl$JDB{iI#V$v4$2we$fcadl{AUIgOYhu*&}@n_k+)Fj!Vx!
zFpAq0^vxGnSCc%PBh%oLzc0X6c176Jm;1q(pF)|hJclE~!#mm#+R8J#YEI~pE$pee
zyS3e!3(S61!bT{+3y*K~<#l*BZpeD7M7C=7G14vI^;X6J;y*vBTYWX~6!CU)`@^H=
z&IZq9&5pPcM}G@&<_L7|2oy=|P?d<^{6qu$;r*hJ@vcB8m?Lhn8sP)9>{9orW@a9k
zJBSVM3s9-e==C|wA>bRJ<7}wmOr(TAA}hP4EjOGel!5EU5=v^<MlllQc!<9$%K42k
zo^V#Q`8gc)@1T~S`6<A!p{LFn1GH0Jdf50}ZhLQF7lUw%gSgM4|5is^Z$GKL!#zSp
z(4r77xzoe%nBOyR%F-!*)1a)s#!^!;Ilun{o2pHJ0{kxx%*`+OP#WnXycOC`@1bdX
zP?uHK_O*6c5h6jTqEUC7f~9e;Z+RAL$lZXtCp!M_d!MI`=9xiAc?C{_LE=Q4QbduK
z=GvAvZjr*5f$Y%ut#@CxLlA4tT|{c+d*=oEri_3j)t2O9NR2g7sRe^dW#}$EX!_Ki
zKfx*As~n%1Tv|1QD+RDHP4!L|AtviGkVjE+Q|~yU7+J1e&xbytmU7k#F^5BQtoAhq
z!NRuQJvA<PH1mzC{3;hy$-dw*EZmSul9T`5q8c;9W;LB}Xc>E~)`VS`&(GU_!0%VU
z#%@-Oo-al&)l>r1`h`lynWVv0>b8{as4fSB5Bnu2Jwe#6G~q?ZkgF-lVs)Jw3`k}#
z{8_3702-_I2KcmfX2|()sKOzyp}1u;86xz;Zq%;Y+|-MY2hXuDVAR-GkCOQ=fFr5N
zkqfM)ZY%L%=4WCSO|>&dmFk_}d<eIJD#{`~6_vp|bV7+R`IW%pz{8WsdEK-5F&f|)
zg+Wx1*<5@K?GjiJ6DK}g{3^1^K!CVYS9vp$PMvm*YdQ@ttq_myCMz)2<q*zD67nRC
z#*lPWz@`6rC#as-N8Kri>3<j~Ngh|WFxJBJmy3K9D76Die^#cLitGY)w%!E(T0bC8
zO;A~xck-L6;}AEqn9pP)3f-^J(Bq`9qxCSOM?}*R`l`WU`e)c96yZv$#>3YCD)tu<
zUkwP-en{QCPiG;zGSyugCe8gE8oaaIH~-kqk;{p8nxcqX!p&zniIHM@GY@ph_@X7P
z_Vmtwy^7d;A*r6p+!Tbocpz)%*Z9JV#74V0j5v1zya_)Rf3ZGGkji=Av3<QOX(6B%
z-rnL7eMl_n4vu}nmebKzoXbU+AVvKmMfJfXlP-UyD?g?G@0ju5PmJtl3I7$mu^Fc-
zKbrJAONi>}I{&gqSXTVDRGvAav_@3#o%x63DN<DL4Fw%V1wBOtCz1reSBS#4Zxe3&
z9mz3j7o@zt%vyYGr$l~>OHOsu+fwoH3M}`@r&a}_{+V_g<8q&yJ6W2uo8&r;gPcH4
z(~<a5R9^1m6Yw=Q2mk@Fli}sSe9`-)#GH!>Jf5Zr9;31dYLybDD64RgL&;u+Zzi@9
zNn#!FBq+$|Zn#F!P{b+BLkWm(GKIvN@<WeripZ~oFRCtc6ikN{=8D{AW0UCgN(F{3
zCodahsrsAc=s{9-@rV+*wOn9<Igi{6$vZL{@VCIIX1s1<zU>}8y=PiNX#1f676@~m
zo+2#AmOGGcTqFTXst|k$LBbY#cN`%SiaT+%eOB=ZrNX0^E5Td6fdH{woH>14E0Wl#
zU=GC*sV+V|Fj?Hrkc#S*FXitbL)00+)*EmgzyJ!f%<%)p@ZZ6d&Bz<Odw>8OLClG^
zugOo!1M-YWROv9WQwl{DB1+0-pe1gf1n9BYs)@A7P>`l5;Ff~L<Q^1pQ0CxfJpV|l
zQ;&^K3e2|&TRI=M4NgbMCpHzAj>IRn?GqVT)Ji(@5Dm(-FFGJSytw$uuQ^AIEHcc2
z==U*j_SkkikSM!m!=+InibCOT3FgZz9TIk<gRmsK@l{{YT&KZ(L;dY;|NZ-3y<oxs
zlQH6Y#GME!AlYLc8pzBsSR8HQc76&<P3zvfmG9#Sz{6A?(=#}kG?#8#(dG2DUaHj3
z(o$FhsvQJ)C*&h&%ZIvUi6IzPUWx+&<kU>T@S(8&ADI|+?8(&YSSG5&C&$U9s25)5
z@xQxuKw!xhltvlbZKKkorT$1YjFgJ9XA{$~;hgc!KRe(>2hnn)t(c;%q9n9t1|lYk
z<Il|GHipx%T=tHj&LR#84Dy~%izp{^-fiU${-ByT|A6q)g#-?Q&!wJxrjwvt`7yNn
zOERs8S<<rqZZL(^2m_8zU-Hi`V#cUfP0{IPiXY2EOeqShPxJaPrF4?JacbwGQK%PZ
z_y2t+Usz!l9<%ui;CG4M4gjRt9x~vk>v*kCg08A}eP+>vKY0vx)J)F;Dp;4V1uJsx
z$f)3$Hgly_$g2hPnN#C^T~FI@{Qa?i4`ua#oCTf&i8m+;WHy3Ii(!RceNK#`Z#)ML
zl_VMsHpuO63Ra6CXK?J+r0qd^l`G~10Wu=O%&5uR_NUG!)aFzQ(w`!J1i2ezC}<`s
zq>sxe^GJhoBC{?7h&Z5b=BSyrqlT24=*osK(wie;R3sb5KS&*wO}OsjEo%97iwn|3
zt5^ylXcm;Ma<=M&EY~K`-SPi&ph8wn=`~um0OkYV^{LtVzCN32c0(eb+sn#N2bJ@E
z<YD<PDcWfkVpO$erB#N*O3aBNJ3#r@`^no7KU*+AUoyT^pMeK(E&&*OF)Re3SKYS=
zzl#Nu!VAs+fU-NPyw3_Y@nW~tR#b9R?^WLdEN+xYeCQ_QVx9^liLQa!Bh^RaDN9S6
z|AWL4)V!GDMjS=1H`Bl{bEH@2QjNwfJr#i4Agu65&Xt5>0p+`fN+H2I2L4(gi-`-~
zwq8@h<#q=tBBn8tW8g<)1chFQ!<|(H?dYIF_9p$>ZafpSaOWhmC%**6gh~Trp{io&
z7ZmMDq6Pm(gN>@E)CiOmY>-HJ0ZbMFRFP_)Wo%MO-3PDI9VaRqW#nQS_f~H|!RW>7
z)M8pCy#eH%Km-^PZZM^RrjcdICoQXr2|Ys)N9&LVB!dEE-iRy%sJ)cC_qng$XGkwh
z)$Tt9m37Oai#e`?Va?lVAWaSt1}Ojx#Oy>WMyoe2n3(P|@F6186*J#roQnxU;1&vO
zT}=jL^RA$3PNJEzWlrE$N2G<&!2~f1&czmZbvtF1oJ=tAmuhnGB(EA|vc{3jO-v3V
z0jv#NKZr>LN&38oAUH-tIm^gjoTr`NrIHuy{E%*Mt|mE8&SPGmA68mZ<>Fc(@e=`|
z^@gTVOV87|Ra3U?Ckqi()|itY;EKecR+U5BP?4a>*1VYjbjcsI<d{a4x(oo>$5=8p
zGwK8>5m(|;&3fyz5<SHzqi2I=2y7^6G6=^wCnu$ZYA^{H4nP|-91jaP?nI^$1t9%b
z{oR}gY^z@Z(+?$pd?oyp!PF1*k1A^TI4XH}|FqFq9tk^{42pCctI0@^lahf?X#>U<
z^o__Bw2PQrZ!Pf8VongE$R255FZP|1vI3~67shWk<jUz;MRbb1^IRh9?89t{fMHVc
z>K|dz0)IX^Bc~#meZ?4A&9!&2wVJ=0l+>#VsN$Ce-wr?vScRBaIHa7{?L>W}rA16v
zRJe7tCDFh`t?<S>f=4M7W@SkE+Njqsq6K?qKuZ(>jtza+q#D~HVe+wJ8l>V}Dj3mO
z6lFw#tW~?*#l@>)?`Dw{j7NoOd&u(45ljllkP;G6-T&~NG3HNaNyhyvjfhw3H`g!L
zC`kI$<5k6AV#wQ(9*Geg;%oTl4~bN3!s-q5C17TWmx1d&E3#B^sZCw;aSaRNt0B>1
z+j@beoriC%XNR=}RN7&2uAVg`)Ch_N0_s_wg_QiaN=*DKjj;)h7nP!Y6FpxO;G6=}
z{F*5n6Y^V&D;2ndXkDsu!s*QRtKqKMgq-pEF*^RuMRi%VEaX%y_JuyT^tbF{<dKe)
z;hgVSOmRJimT4vcG32as818q)*!3O;jT3}puUkLTU;q`&EhLDmJ2wK~R&q0sk!;P{
z^b&z@M+0VgtX9mq1i|^B@k5%9Da=DFOa~cRM=1Q8(Zx31WdHyH|C#VMy!9o~%<Mw-
zr_6hYSadZ$9K0x<3RDOysAx$pvShm(C_Bh>r#+MQFU!7OBedWmS^o8__>u6#NmbJz
zJY^)=3EL6eF@j}gHiV}{Y+_P58z_Rvs0b}A$ofh=X-UnUDGP#Px~1Kq_=@cW=~HWF
z6af4n_RN7s+wI&&KIJSYR?iX#HRJ~jpUD*9UZe)3!+a2)NrN5TByOLb;4##OJp&mJ
zB6ZBs#Vs^|C?zyk5KCE;TgLL_2gxLAb;+9X2GTOf(4vxeH%AvF5Uu#fzFh^N1rQp#
zCK;n>*)IGM$^s$NC4!0eYl&7(Z0w^JXJFSgpEM`MGRoA?FV~GlFO5@Sd|RzYnUlz+
z1R+&rgBn3|KPMbHgTD2_d&KocrEVJFthA#<s~tvMlK0=o$IHvGrvt(bnSN&5p&<yo
zvc%lo-L`}4_y5<IWt6!GC%MNY^`7}JR;%)#dqi~(dYQ6dm_-Tf9~Qyr!nM;h-Nq$p
zJ|HywOZ&MY=;Z@S^J|gc@_um+IVj%2PF`G0EmJ(#C~vwA!CuiqwwMyAUM+<G+@PX8
zx#k^&kR`Wy%O*a+^~E}3tYGity5(=G)17w;=-G9+i)|DKD>e}a!Ety44Ex=*d>ons
z!8janL0%z)AXSK&Skzeyux$SE7-3ndG^)B+uB`g&2T0Uk;Z5)8PZr#ZB8s&M?hvcL
z=7$Ji?M4)hUaILY>sL(rhJjP8Rz>qhRip0_p(T&UpO5>+`7GG<ErJ)rz{uT#6jNwN
z3U!R*{rJlHM9l8y(Hhe)7c|pZkF^d1B8U=Gm;@mfnxz{yS<687D8d3JGjiwmecHD(
z2%vijQ1w5_Jjn{JpnT6`?Q+!<Yd)?_$vm1dKQld_H_t_XzMDK%C@k2|IetM^ubrpb
z`o|6_P=fNW3J9n!fbYc{iV2_yjQ6W#?IK%V!JcF7!WT|`*G--REU6s?-zU9KF7kzy
z&LaIbu*&s!E=hBydaSA=jzA17G2rG1u!YPuZz)70x=#%zF`|TpS;|pN0rV-bn1v14
z6wRp$vl;}4kZoP-LgNSp0aGv!<ul4e;h_XsUSV*E-&e987*;w&zM^>SpKUDBPj3cO
za3#9Xn4AJZ*K`HZJ{mNDcpkF&cQ!G@3p#1yZGh3_zbZ<#r)4_2UY{SeZGGBf!wAy%
z((#$iih7LNA4RuV6<XPM3Q^hG04HaxNt)rxxo6^^w$?<pA#Z@QZ%wG4oB%52qrXF{
zmyc<J4`|@oeg(aX$dfGmbtC6E2&)H4S{eC{d7FbpsHM7gk61}_D~NQ>*$tgtBJW&&
z9?*vDYwjjkUZ+=?4V_(O0vT18A-u6=$RoZ<J!YBq#4V57Oe~t)|0xZbB5Y3-;{<=X
zp7Z-(-q&xcGLHaocv4dArOMY8p$P=y$}{m-B-O_j@%RVPN@ttdH_yoC;Ivr-RfF!O
zP(_in|IOV5uNG36?512OsuoUh;HJE-A|2vkI@wgE>+hQ4;tXnEP8T9v8F-oyt`k5>
zFLcr}w?b)Z@B}ArdYW)$PW;LphGL|j9$%|NGBlXZA7~{KHE-n5KnJMw(ij<8Lw0%^
zUuObU4zA0Z^kUw}O-dxK5En(O&%KUY@99~0Tm326qA<%`po7+}gK5$H9yM;TLH+pK
z4CtC}_WU=HStyn0d9e_vqb{8Ew3#A^-8$i7+R}{v{q^ge(HYm4W@}Di(Nr^qcR<wB
zJ;m7k6-x~hwBURfwYDN(O1@qvdlX7no}yh)zu^cq&8~3|Sg(Q*unuuAH`08*WcQtk
zdBMP>0ti{B4xn;RFgLV=<|8ApF!XKK*|WS?TH0Md5?|Tf9R9R?c!}H^J{nf59UpxC
zPxC-Zpan?C3XIeS2TpNWpnAflLU1BPi(tQ_tXjR{Pyw|W2dKusfN6R|y8*6lb1E%a
zvmCH3DS=Y3Y9<x=ChhSYy$ixeb<Bh&o1Pe^#Sw@_{_9tN!fP-T82K;fMmYC^rmArL
z07Ln{ilI~u2bBf5ov_d_Pl`(ohOg9g3vqLfH*Gl=po%?>4SRl^)Z{V<L;hJCZnh5y
zOOr+}bI8oqy>2B#UGX8*3$f3sIIh>xUCwf(>=sb&8rhZjQyL7Y(8fZvR`^GhJy*G~
zQice9_MbF?2!hu|Erdyak#1b)x(jr?0hxvROa8+lUJRZ(R|2DE9Q6aF$+?jm4#9`c
zM@IeV*@JB7K@%7jO**niP0Jj?cc=UPX)p|Xt!w>9)V$kQCW)Lt4kms33ynHv;O#`<
z3L3%OF%YM(z1+%5&a<h>rS3_N$x?Rj<hq_p$FLFSJL4BUo{HyXzz(ws@>KFBDWSFo
zlE2h%UDv79k!_s?tqII+6R1NYItnzrr-3EmpA^}&I*zBfLp*wUcf;I~$fcX~EhtU|
zS*co)E!&EdcVF}#+Dem+1#O#3+7)fHM>+cwzW@hYq=)0PqukwHHx7KFS6g|S5n$)0
z@+5Z#u`QKs$<wYii4GkV9b(CZ=+Kd<TU%MHwh`@y=nzhAxN&z`+DQi@v##=FJ-pZN
zOy?;bI;tKW)$y<Gj*gl-;Qgz4tjwrw_`jC>w5x){I&Rt;9o04b&*L!Xu(W|m7^3f8
zsgoT9>xmez;(?${UIh{TxuD6=4qS}E%bIQ2cA&R7v}>W9l|a#Okml`c`|Ya!<VE1M
zd5rkrRlUqJgKOM(g)59xF)`h7?ZNkiHB%1F3DdR9O|GPTtlr#fbkBm^eBg?4U$e=?
z9{S6W2}Q(&z|fU?9N{Ym{s5}7t8|&u1Jb!SqzfI`0qNo!(s>r{_<wZrYkqG7_l9i5
zdV+9~)6P9r{)ASYE`R!$GEJuaFC$gP%un&l77IE<x^xF~<$|t}F1A_s_5LnOr1RAg
z%BKHML8|QGSFTOu{@<!pz)jM{bSIW0wUE?S(r@0!PoeBgvq%?RPzd}be{I89i*RS(
zLuL?dC7T57BcuN87DRr7&IgCr2UvH$3RqAP9wUN2QZuKuu12Zp<0vJ2+tS@?&di6V
zuo3)kb6q$;Wn!=^$Jc`b`nKg%JO0mv%we9#$6x0U^Htz~2;^@#bZcH?=pb&Z(re)2
z&R$1veRNNu-98s;uJqQBlqPQzZka8q-EU{rI6R7OEQ;e3gR-mtfgmsPZ9lQk2lO%F
zeqVU)UNxtRAa)j~GBTxoZIR`okAWJu$jG%eThq0{ytW-+j3W^S4LYX!{AtSYhKD}<
z7Pg>VH~-gB^6>3V=B@8s-PW^)lksBXPXslA!#U?W%fS9=SEc13>j&5~o>YV4Nu4;*
z{!j?Gl#~;?XSif++qD2e*|7Scod6-mLAJVaQ{K;do=h3jVpm}bpyLr4bc0#0pgTQF
zMYFFHG8#Muo9R|Kl|IS`T3rE^8_WI)suz>wOfB<NmCVGd^}k=HLhXxA8VA#L!&7kp
zx+$&n;|<E=_g7MzBrQ$BmFKbY8Q&b~2j+|q+R=So6f;RwGlop|IJrfEM(%MrQY#h~
zEbe17YzDz9;|&iIPPT_-`@Gs)oiFJ0-)Xc$YR10D#kAKrP3=mvFtp-1yl;(ffsnaO
z*Y7j*!!YX$k~!-X7l?<c2#7%xG%Ot|h~+q>uAAeY!S<3Wq8y#Q_iE;EM$Ppcddti(
z4}W=cv(;@mOeahVR1zap9W@;<vnKG9jF1EMN<mA_AY#DhQA~6ny7C%?EtFuLH|K(B
z$&q#8$@#=%rE}6kXDWe_lJVBj?07~yNb9NKZNa(5Ja7{ssJPSExEk8>&605?xx@V?
zZmbpMw-6`rl8y{N+DD8zFVx7V9!!o78t(guQzpj6DUZ`qljA1F!Tl6HG~QaPytP&N
z=&14e-^al#El&EurCnUBy)ShE-7n_Bk#_z)C-{63PV9p#?)-aq7?l0ki^Bi&8NU>F
zsbfER58iD0^Dh3}Y^(>6PrFtR)X)KIrvsF~=vEbgGY71NF8G|y00Zn^I<ce)5@ShZ
z<i})(G;1<-NG0N)h`^VRBJ1YL;PHcS)fMp4>fP;`K8b$uFY3=os4i1k^*TTLwbK;-
zBH!ZA!Ta$K3)a(*x%Q42i|u`Ap>tpYcCyIS)eM;$ZLzSijv|Opl09$SJFUj62#7?3
z;`z_^tGkk&ul2Fu9~Li>x<R@*)B#(h%6bWUa;o3hxlWBYo9r*UbYxUfqUQUsPKmMv
z`~Ysjt77>wKlr-CA#_n@6^$epaeEYE(b;X@wuhk(oN$RiVtE7Nm&ikBc1l*iv7ktb
zaGmrfJn6pX2(s1O`S)8RUmpwvWmKJQB9xUWpizXSQx+u>UVg<h{fwu~IL_Jlp74eU
zpca*{#RTyf?L|2))Jr-<5d~EfDSMbG*Fv3WMH%wuV)h5Z)y9rQfy*2VtQ2CY5Q>!=
zeTkPqQe=rXC6e^C6ziaQ3b6Uev}GmSA!YpLqzT~zu`wS?taKTYwxtV%xjHB&0xPWM
z1uIk%Shj>7jue4qV2!yAF@r%Am1OQfC=u(C^N7E@k<JFnek;<Xk_`w#;}$S~5~Tyc
zL^uNg6`Y4Cwa*AIqTDndbHt+A>N^6BH<6`69jLiMHOPgPN3*Th%KNjz?gfv|taFt%
zJGX8k_1LM~pw*l|=(n@sm6{Z+-io4224vP5q$cCc)f8>~M8>9v^1+d31gE<&OJ6u1
zHu={`{XDF~P=wfYLAxZt$&S^W6{W?t!?)10@eRtf)1LG`L8Y5g8&S^N`O{ZWNckhT
zU%JIxNSmLm9u6`e7tt)WxZD`hbdclcs9!D^_$!=e{II)mzzK^RLDOG+1aof5sDncb
z9?%+shH(DGl?XgLqzO&p(wY9qrl$E?YIj)x5EYws>TtRcbpA8-Zq{J5dDW^cfi`@g
zUPq=b|A1_yMQ5FmRP=E;;eRvoW3+ctjkE|Bn?NzirAEcSj0hXrdL->_p^qn_oZo9o
zHt|@Ug%I^*c`qezH|M(UDRB?>pve)1fO|J*_v@D$_RaYC$!3DvHl1UWC|2^QB*w}=
z$c0PPV=1a_y-FZ*r%3NOm$g-+6JtiQ#!KNLRj!K?0Q<%nLl8NR`_VvDen=f_*>-RD
z#(950x6=pLB0G}AX@thnWskB@sR*&=dU*fdR0<WoS;Mv5{&V`$^`;F+>&q%{cz9=R
z5Lq1w!xkDgUGRCgP()Pr&H?%zSRYbRBsW~WLb)2+NRl&wyKeNUx;Nh#2}yw2-e?x5
z9_UJDlg3TwcKt%VZyWsblR%E26=T7(r3-mCsLtYtD_8Qc!kND^2D=p^PG-d9;aPz+
zIuyl^jlhHO5b2Ljzr9(zC=gUmnf|iH*!L;23oVx#71^8l=z|nYn$4zRcKyd*C9ujF
zQtU+~SadSjh5R8T*jJe;#4#cv{}vPsOL%;g$MeDJY_2|S2X#hT`v^-d#O3-n^MfmO
z<ZJEXkwJR1z56@3BIY-hIok{LP#bO=HM4<Z(Eq~tXcD_ivtM0SfmoXz?+a9G#+zs7
zlgiHC)^E=blzcY5&8HSCJak};UFbyt5)4aCv?nC`{unw9A&Or2N3NEN8Mzi78QD(+
z4FHZ@8(f#ZkH1cT2<tO)s1G>WPdT5)GO4~NZIY^C{x6b}BBDO6a%ij?rp}*a?ij!H
zUgbIbzdqVAB~lGpUKRZJQO0wWpM1fN%PPIUMYO3v26gDjfVOB|L*tGOO@G`RGOkb*
zmviZeDb>fvF|kaLvXUoAtU5b(ne9L#*N|9Xgs9qV;TR1j`+{?JV6xjI0Wy19gT~mY
z)k~X@)jE>R+GA79I&m=Nprqev+MnfnX}wAt@=+i|Ra3DcSMkJcEcjxg^d0I*b!H<)
z?o*t+N&2f_0>j1ioPdF)dx(;gfD?p4yZ{ILQQsJ`7^KoAwv+f}<CHf1T(DEiPS;^<
zpATlBb~SRrM!`&1Bmiy26gEqK{pL~+Nc=g8u(K(J)SLF!J|&dcbUZgAEe1itax5MY
zslarP#TJq&YmSkaQfQ51_NP-g0Lief7<3cF)GO5X*R4NH*&e{T$0i!aVw7D%F}}H0
z@$^wK{}S)DmvM1U8#`-FVhS~O_nL2vf4dztbcpMHmV#o^hS_C#G`eQNqxW-&G0yrI
z<d3`uh#U82gz)3OkN5}KSqv_sjl6u00^MEoNPqfD5Mv<>xg_m+w0|KZ&~1^3+<qT3
zfOyvsGf-y8pqYR%-uAo)8Hv5Q3+-yrjSM?Wh<&?vxtrr7wJwhG$?z{h5&3J>;-_H2
zNWZ3h8@`s&i!-$@b+`D1yoc(M1X=&tc8W4iXh=?j+5?_J@JD^QzVPK^c{LeyX6s7|
ziv&?$emjzC(THyf`>2+{{uITtf#fEVg@f{u$-+1R8%UDEfZ|c=!3Rx6LLHFb7C02h
zLc3<>vD;JT=r|yyK~F-IE_KqeAEV#TCamJ<ymLGZk5siJ^w$2}CtiNeksoNQ**ay8
zipZO6j_tEmQS?40mly$?%V9H5eeIgkrF!uPL18Ql9{qdETVMA^m^)UK_~-FSaiUi1
zXOF@E186hR#(vAN{FKREDH)H47oVQ<&}q6I7&b=4WT>gIpDfW>dTvl)aH|5$I!fpL
zSqb4chp&RLoTpi5y3IUArKECVKL5hV>F~5idBnf&-`-Ub?dh$djHcyx+eMV#EVfWV
zU_cnDQFnMndeqD(n9$qn?)z-o4?`bD)3P!GFy}{mL;sOQ>2rUCIPvrG(eI-g2>rBA
zPAthC{oRJDct=gcDa<G`gz@X=I}-~`{!$HR$?(2jWHP7UG1q@_-j9RlkQuyT=*Kn#
zc2S!i>XbJM^2bF^7&@Dt#QNKnHo18c-Ad-XSP#{TBSM^d3_2(UHaeP}qU~T*QoNR!
z14;ncKpCPc57*deD0$5fOKyQQN>1U~9i^P0;}xHrZed<PHBc(UU}8Ge@8_!lqbK3l
zkOh>?@>ZFeYlbPWnw1`dANYF)rBD6Rsb9Ln55inaJvvz?E-z@54pv)nS()b{9i*o6
ztTIbb(pO3KL1hlKu$%n<F!z?xam38ppqZI5W@d~rrZF>&nHgh-nC+OEnVFfHVrFLM
zm>tJ#@8rF^cfUP*cmM4<`$N?&wOT4wYo^sz^_0?m=&0YJNfXPzdSy&Xv>hq?Qhz~d
zn5>G5Fn{py0PA4qh&>*~_;QlC=d=g!Z|)}%^m}6?GxN7O-xrAw-A<~?Kg#K7Ts8I?
z(XkIqk~%YyVOLD%qRy&*pSOPpLmz+K(X41zx-PT#xuQ{i5odBUjex2i{e8Na-j2m<
zkQBnW!CS~-qGh4SA0wUS!z9&p91S<sGD9)h{}NQ29c<@)jIRytthjn9eL<}et}ml}
zSEW(;s*Af4Jz3WRlbVeW{DU!NJ6QSmyDOU+lR6^C5rO4f#cW}`D3>m|8DDI0?4hF-
zDv3i*4t+2zO<FSeAjGT;D$I{S{mX74&8`dgOkduKrn<ks-&|w9_F}G+iX<?uwTyL>
z^KKdV#dJp|yIIWi+SOQB_4Yl&{+Ubk@<7d|VK~v@v($l7IQ~9>u56_o!B}H@m1P*L
zW{Oypb|7Dfy;RAl&HuRQ^m|}9c0D+Hv!m|0(9MXWmAUIfx%1{FTCc2%X$G|nW5M|D
z?rN4qMx^A|ucNJep`;GENco9QF+bX)bQ}`5q{gY28pNf{-+DdtkB2o|Q<H+HG{HBp
z=cAA<FR|x}9nSgfs+c=wUArd+AF@eMl25e;j;ZUJGkyf^3p>8WI(Sh7z2dc#&#mj;
zd($|dPpvPHv92$@ew9BCz(2k(4#G+ukbEAa<i|5_q21=fRSyw9D^{iC9#C>Kt47RP
zZBoMf$Wi^dhz>aMxm%ehj(c7V4ItTOXsqE9`O5P&ELE5$dFE?NeWu^5n4hU487MP;
zr4%(S-~G%caZ=*jEp2h3cq|WC+pI!@`ye{n`TW>9X$N`t?#@EpQ~nmW$A>*SuhG?r
zWj_CD^T2ikitsI@CuhDIHg@swZ_yA7MW#fX8RVZT7MJM%rLtVQk}tF)qTc>i6vz3R
z{?swh3I`LbHW94Wo}0ErBM}PL<Qn~2Ca^|0fAdsE-7#tYHCEF72or_7;YN}akeM_@
zNmbt-Jl_$5yw+EvCt7Xw@HO#a$F|%LD5BE0Mm4SKm!SSG-|+INQ-Rv6xQJ2_@h8;p
z`*rT4G{go^eY2m${Yn2QRpYhBLi*z&(+kV4^TSCavI<FJQ4q2`pmM#8CVSVIMTAUR
zNg!s|iPfxQ0vg&eSwdP)B|#%e<=ggpfE92eyrNkCeM<P^sv@bP_;59jdw4je;sA!M
z`sHvojyq)d+s`<ON5^(ez@eZB2d{q7M%2MC!kK=!*+|UX&7RbC`&Mc4-y-<lLib?O
z)*wijvi8v!I9>N=+eB9Jobab<-Ta)@a_|xX#l4ZN<lOkE!A-7d^wDD&;@aOAvaAEl
zOTYIUpY#KXRn(nS-m9>Gna|}_)U{%oHHywZw#u1isX0v6pq&mI+wF7T(eym$eVRxL
zBqLXqewz?n{Qc)>75!TK8f&`^gSaB#l3hlyPh$)p(^Y%&GAPs-tAAa&^SFLBO44(F
zLz!v$-!L;ing7#rJk_%<^t5|j&#z|g*T4I^;0rxRNT)RD>-b~lS4(pNe}mbB+z7Rx
zPRiey#x;YrkvXTHw5TKpFVCE9X|0yDxR;r(s>A=lpbAb~OdbFr7?g44K(_5Q@sB2h
zyVcH(?Ln8v;I`Blg-gr*<L#x`)Eb5B^O4QY4!^VWKQ&h*HnW26^;yKVd18K3ZcxB#
zF6%%Sn$rSC@U|A^%9Y)6M|;e<Svhgw9~8E%8e8a=R9b4^0-?AWJ4}Sgh6)T|Pa<$0
zqc0WRWy=9-T`0jAkqMYmhgFS8U++}{g1D%Wtx><GuId#dFGn}c;s*|>C~|}w+5oV%
zi;DfnYzT4KqP^AvSxl=-Mai^AI>tIKVd8KWVRh=IOH1Qg7<mN!+nKHD`PhJ#Bx*lV
z`6HMoaP}Lar_{{6EhD%S>U3@jnY<GS`~5Qe{c6wrtb|x6X;Ehlkm^8QBu)O8qb)!E
z=w>PRX$e&3kfhbm#9-$F@k5z`R<IK)lGHcq9$@Eo3q?M)<1t7sd1D2(kUZg<5~%dl
z)J^M9F{IToNDh5IlnHQ$;j4{|TJEFWhG&{=ZbYucb;Jb-Jh$aV!m7ImpszoWqxGzi
z-TYHnw|t)8f19z1j!^hi>+&vV!R>%`ot5nU8uQnz+LonakyAN8H{rcRLLf@OqY)UQ
z9F*p+O(z0+#RrXTWm57~;%rq8eT1o$g_jbThU$sj=zROmix~qWhzcnRCqs+9V!$uz
z(Rl7xy@Y3+poDMZs_-WuA~EGH;puG(jrfM*f7O5-7N}lZpeJn^3Lv@~gvK7nS|bKc
z6$+5S1)<n4T=HvOM%WkqeJ4`<=~$PgNC`;O`Wck1(PgPSE;b35X^aO><Er_oI~>uB
zC8f}CJK6g}6oJ3o5{lO-C9Vv`n@C-#2wha3+QEbTLiG!Wi11<B0EDIP12T+*!})*c
zw0IXfMJ{h8qywdW-J#H&5hGltl&t5x>-6VE^sm1q*4QzGds3Z7wKUzTwIs((bB>Xq
ziy-bmOaQ4Zao(_#GwP&`(1Gfli*+&N!x2k~zubTrGNsF}PQrS$^#n1_zc9Q=19&93
z*4FS?`gLXgUo6?IlHk#hObNe|P$8#&&}c@0$yn>W+ljz#_Nn0qVf$0Bhn{np1wmT_
zaiXVi8Tx<CS&ZdTa?{IW$#ij9js!ZX7<!kq;2)12My_K2iOKRdLnK%BLSg+GQ6D|U
z*{?2v4brQ_4r3MJc1S2{m^B3zM5a^)<b-lVV`MV^k|3bRfd2D?Ad|ujE!Em(eth}s
zxLfg}j8=b41&=ZALo8<6GTzkeF724(3U<B?6kWMorwpuZB;A29+ZE)RyHY#VIDQ3y
zRwI~SEM940pieRygO-NyLO<b1&jar0is{!H-kF*at5ZQ<1l)36;B``pG2vM*UBOUN
ztZ|5<@D$}Z0JK9F71PVI@2rtjp;#g<WKB%8?ue63twmuRl!=HoJ{xDwsmyGw@Q_Hy
zhg4#uW_wPw+{Gx&Df;gKO+lbSWehe)=PU}F^5`-Y;)w1pI5ppaJGbQlQy%>mOpKdX
z^$<gxN?xBPfmc3V-}eRfK43#M8v8k&gpjo0o774W3)`oysyT(2qpU`u8;p+33G}WL
z_4fJhcM8CX2y$2G|76Tw5ouNZRIpjj{|Z=&!1BLc97e~yw)2LhCQ*YC*_<^mwCG1e
zi_VD=7%0dj_BYr{m!>`o`3{N0dt;8YJ2|KxT|?+{stQXol~7oOTaX1ivWih?o!iYl
z*=Ga>hw_p7Jhb~R)x_<^0H!MZfL?YvIvT#Bm<e5oA`Y}?kY2Lg4^<xddaFI34yMe%
z)hIUaB2~5I!ul!YOO&FmMS9LfvlFr{yl)bxs1#4GP3>e+HXAIB&IyE<SLA=DTC!&n
zFI9!cHr+JpQGLSqK@F_7w2FXulYEoF6=t*b{N<@=Gp2qTFS0f(eDH^QF6LpPPcGy=
z&V~BtoxAk)A7|9G6)`VxcH{6Z%hVAot-x|AouzoH7ECV5oY{Wrv1<L&#xMOiX(cHU
zm<Bo$b5ij(!Xs~gg(LgW*gB=zBbW|M<K!VQS<qp2!7rC(oVY!X;Esn8qw%W&CbpQ2
zoJ$k8`+w@`sY&=#$obAVg7b#PCH7V!6a^1?e878Ve)bI38V9@aSUfQO+F#-+AV5%h
z8-!HDoEFb3oL$>K&V&Zk=`lePZN5&4;MH-bIoon<iqPqrOZzo0JK8kku+%TzLnPCm
zvQ9ODhf{|+auO0R*tBGfN%rmkBxdgL==T(Wp30`pP`P27P7I87_^v2<+>$<$O}-<W
z0w!@TV)Oq4TefVTqh|%?<oIgiswX<Lv2r<5dClA7>enqCIUl9*z8fe-rHFxI+NR2j
z+v~^0R5)amb<w}ZOxC{#Qle~#z?4A|Ai43_Y-O@is_FJLD#-HKKLA;<s^-2tdU$z}
zf~44cFD0Hd`8EiCR>%(7oLU^G+8N7j?cpD`!}`PeTihA(2EA4KT-F54+BF9GTsrUb
z$g}l4^u@cdgm9zQFQh~&lW<`WQd(^hnBJn*-6DFBZ$?dPBq{jBc`w#kO1>(&>FXA{
zbfPJgIM!c<z|Z8^&eTq|j3hBApg`bf2Z$|<Z*$)znE;0@@Y2I71b7vK#f*?IfQ39l
zi1tVUE!34TR6~yPIxi*%BzUBPStOrfZV^9eOCMxRSh{b&xNQZ*zs<#nvLFfCAf#B?
zpqbG$<ow!{bI3Q7>;ozgg%}!Ssb}`QZL0R^4&#Q1AcpA`Vf2`VR1p()oKA&&Y~YBY
zdG}82XsH_MlXabnPFc4RM8(uaF#Ns&lmH8?QZe;m!qVk!8j!Jv$)<4vf%sZ=i?Dz7
z?yxhI|DvM}1HFzwHf^2fpW2wSspwz5sgkPb&n^1Atb=T|%qAqO8v0<R+fJUCT{1-H
ziYs7`6`u09po<55tKFDg8d9hj2dq)-+#_#^9BU~njh3&4fvYiCJ_z?5RGKLL;hfWg
zbv9mn-={dH8d|_p;LtRLsGzGb&c%nwY4aepVQ7I6E#Rq#f#Q9xjvGiRG4<h@2W~)z
z?$t<R@pP=moqV4*dZOyCLIS1^Q2>5#;a!a}{UnD;iP-~0Q)5*jgTJgR9g#LRAQo_e
zAol~EuQ$3!feo?Jorhg4)>e|Re}}gS4{{>N`;wfFdio7rmqJ_Z+W#oU6+W#a7pUgK
zB_bIb#H1=EcvF$yC5gCAhi(+%scQ?qF?SWVwD2?7{s^@rIxq+Qvf<`(T&i)&Kn-O>
zKi@*Z%*j1Ky|%j)qXVnH^b7WCusEYgt2lm_QKYWBI=>glxVjRX|J%XjEGDLad!gY1
zpLu?;ky31MrEQ!R4G3H70YugdjJP}psNV#N&LKl2GS&8ZXCjk4sUXAqN5g%p0TQ{P
zS5ni{Q5aOQ(@q1SHIY$YI5*AKR<MY;CPPaWWTDNC2Ow47@&?4b9B9e}e>}i%K$;Au
zT#W>9CtTJQ8xn}@aShIMqe#+Kkg8L<W93s0*u~XlEdZ-D>rcn=6-3nS^6n#7H|k<o
zGR9LD(o01iF=op}D&?@Tm{J=~Ry^SZ)g>tHHtY+L9@rorV)?%rhIN8NL#hdFRYB&^
zGBJ>A=HaQ;S>Kwe>n=47KIZS`e?joVk^3|=Uq>fU__m^&?Qfl@rvAFuRs|48dky%$
zQNJds#E`ipBD*?-@|cZr&qrUQ`E}pkcd=g*W=1;sw2Nug(X}H4V9~F{nnm2~DT0!8
znS+9Agln{EP?wo2c*nBZ`AfS&T$=NI-A)f<{VR$6&?7PBl&pPMIc8clczzQ5U&$9i
zf)n&mt`Le>(I74I%w4GvnD5e_8ng$&k5P`kgbj{^Vio{!Ec9<(=X6;VJZ4wrwEhK<
z)s4{=IUmwruO0;Wt>PE-Xhm|s6(4f8J}NIq6sU>f`(K9~)Jv~4MxZ{tHC`7;Py;a`
zp?HuK|5r$ug#V3!?@Re{mq+u5slZ>$QGGkUfR|&g>sJ@{N0{c3l?)w1d6<cOjlt1x
z0&Pklb%=E&?zR1FOz@5Y%9fU<=@KZew)|$<A~EU>zu(_h*Y*tldw(c6W<HKY8pb&F
z4Mm}PYWwZ<A&BkJS`0UL2fsn}W4ohmg};~kJJTYau8YGz+Td+EJQ_e&iP2yb{anjc
zq4oKg2?rQE)lec72Jy&4|L@L+#K_+xnRz1xj^QHdF%TVm2o!swTOF#Kv9}_&VcMoP
zP!w3=7#wsQ$`jSJ<oNYn^$nZCvE&zZpPdO4(}Mn2G#G2H{|9#7t%Y3hXGv7)1T>ho
zpdoaRktoRFV(h~Z)q)hZivC4ocG(}RiIh{b{5Vqo43~iQrEnc)GJA%`hos1!l>DT@
z8n8aqRT2IC8>A=AjG~!n7x4Id%;xYub{au7)t;eP;&aMw?;(!wYqr<xSDITSobumB
z@u6FL5I~@;jkuCA-HG6&m{nt`n0Cr;$YR^zIiVE$OMWv2&8XNGvFQK;i8{dNXUE^%
z5ej>v1DGi{53X$ao)<{_?_L~4pZ9n+X`7+2^b`xjxtPH3+F=3wdXw2>+?VhqFOe(Q
zlE)h31RcEL7G=!+Z=_N&%jxnd3wVbvl*k|Xe}+Hy!8S%<CX=JWhjl#I7~Ywo*&_)W
zp67}Q+d_9XS9pJcOv-0|4D2km4XrK167RKDs}MTl3>}hqvL#;|4J2a|_rN`mC`MGI
zYVEj(T@0J4CvN+)pSL&hXu75@2W?-2vJlnDYQF7iA6D~TBg>BK*dKRbvE_f84s=}h
za_oIc)Dl-a$unzxv-lx!vsF<wk3yY?Ea-0f<H}Hf+G>_t>XE~54+ym|Vant1Hbm~(
zvAoleF%sOQj7q|Dvs8G#2MTeIy{sEng$aaFTXM-3l4J^1qlXMTZ$ls>crm%&n9R=6
z6Fe;Il)Q2em@1%fx4%@|Tak~^f^vA9b29bJBN(3HDacCa&*^ljH`jN9#D<lW)Cisp
z(BM=ua_buJ_E4eZMWKUox_*g-)FaQqT{Yisj76*%$2$%tb#D0-2svjcm=SXscDfZP
zC+cW#)l^{EO=0m)>au0Po_@*1YTCE)3+sg46#WRP5d4X-m+q6=t^JWLy8eyZWuDt+
z?UDb{8kTZ3a;-tndiHgw<uaAqPkN1259l%Ld+9IG!z{4OA=$h~T?{`*k7^4|@L70T
zdW~;lhEIFIeal9;e7aDoVuAf-HPAk<-ty(*nY>o-UNbqA8?xEry8xW^gs2xRuG@m5
znOM<yRD!Uix9=@ty$q_2%-e^gs9)#%Hzb>ew74}>m#iKs8-t=NrfQQFt`-Lawx`+L
zR`ZYDAH}g6y=yi&CH{N;z0ndEf161YAnY&0y3BsjNxXCl=_Ncd=~rsRZ?BczTOV{v
z?Fe)@v!s<5cE^4ojVf;4+PAJ;3;C9P&i8e)+<g806Y9>VpE{Gyypq`22_CK;D(I~Y
zoDBLx&0t@o!MJnir<%Z*pvLEID$+v?G!+G@RR1`3!w#sR8-Xxpa55^8#|PXV(VQ|k
znfC|`=$3JlT;^NSUu5k=Ka0dbBnf+q>dPSp>Hv6(tN`5S{d4Qc&!>|ZSWuv?@V#6?
zjKLEMj6op-(gCa17gc+gZ{8z9m-ifYZ!;eV?k{JRAS(zR!^@Yl90dEv+P`~&zT$Q=
zkGJ<oU|<Rczl`}kl>ctpx8pSCPEO_6)X3U4_Hw#sU}Nw2TjogE_g41KYjTD&zB91V
ze=;)|xzcs#ohCSyN(p-2_nqX}@)N;&>vo+cc+4@B3oOUy5GM!FFGUx*7Qe_=s+<2!
z$y2DaT%gl#BK|(VNr>9gA^w}MX21!3sIuj3VvgdEo#2fzc`RNQURXDLv!&%ZJsoaG
zb9hl$;!)N0JD370jd~9nszkxh16oxB7!Rzp%h=DT+MxH;jG@O|I<S#MHpy`(ljggG
z^*iI$AKVu@sybhsw5=DO4%<}3H(cdn#-6OA0h4|=RpiI4f>TAX+e3!C$j3W1U=xX-
zT~Jog;~Fd<eTk=|a$~&sy*uU<Tc&*Fy~nlpmBoJ8f3#$pGbcnpd(7T<<FHa)jKuI@
zicz+C&`<pm?rF)C^)gC)W})TLpYfaQ1s?kDQ)Iw?<#f=MA4p#9A5|O)*>6{2h}taM
zw?G**rZ|AtAO(!+5}oe)5WbA0d8j$L)~iVJoq9^N?b{0o7T?+Q-W{$nvqm{v6x82m
z=rmdUis8^l`F&%G$r9>{G6=&_{9mX~Z{C<e(isn0N=d9_K}?lykbW<p->)2rAUedU
zPCU#SkKM0Eao9aEzw;(E=Ra162+~T+g4u=KA~^jVyv=e2l`N!eAqkh=zrp-PtRi|b
zK>IiES$L8hMM^m%=5Aqf;Cxgv|BErp=HcG)UHE$X%q<8_)k<`r6@QQ{pQ<Xb$q<r2
zv_FQ)_Ja8jn5oGK6o<OY{7N+6j2BBk!kSV+zB`L4kW0mUh_u$<(uQR@UW>qjF7(EK
z>V+~?U10h+{8r_hfAx)|m80!zsO?zz@WoViSEJx_k-~Nk19xqr$*bznmCa%dN3dkJ
ziI*71ojiLM*NSt2$m<N@mv|3euk#brN;k^DY2Obv*)OL}A%~viF77I))$zVfAr4>d
zcn#zv=t@y{>QxwD>_PfyQ-iq(C}`^F)UsXaU~h;KUW8&k&U)0DJwl%-;sVtkCw@Qh
zfC#zN2AbG?tzqhg57XVT9izXY>z5uP2Syh&2B1i)Lu03NBnxTg?zB;`>rQamZYFri
z8W1dr<q2{nEl=1ZU&=INBx;MUF}>q$=402$zNmZrLH{)MGddF{hi$Zhcq*^N$|}o4
z%vu!slMBbR8~sM3O@1Y__aB(1npk<EGu4m#k4e8jeN*LAA_bxO_RheCgl{OGqJCo6
zG!A9`uNhvE|8SaLRzgT{_{7H+5D8BxHACRd-Z<OmO`~Z$_R*vrpqy%@6uu5b2;-Qn
zK_tTB&X)(Yw!r~NW{m&At42TmjC=$NJcFf+QfYc87R@$<Q(2lW^|Ta>cjS!)H$fe_
zHzJc=PEz9bRZH4$`iX=glKOBtm5S8bCy2xw+Z-E(w<hWU*GM|*+dYIi#4|K@4rTnP
zrZobk<oZ>zLZ_A~UG=6-nII2GE9~d1SAIu(-Y6D2ya2G&iksIW_TgpeOC;;eXu1&z
zjD)i4r~s;rHi(h~f3bG5h@;^S3mob#i{=eJYaL!rFeZloZVOR)iY39}rKHg3_8?|h
zNbDR2K(CyX_)ROsQAUPk0Cs!nm}nC!sCd{v3h^?75LG?xf|d4l-X@PnAmCe}-WQnn
zuMvxwDsqL#Y=iY!%~X|y$D?v`j6Wkyn=Mac%*reR>~eor6xkJes!}e^@J?@_(AY>#
z^S*ebZqp~#(A)mfDLSuXoYgrwJ$>Z>?-3$2Ov@T)%}}W2Q<F^OYJ3GFP~{M5>c^+b
zAS?DL3Z71yx<`lp?ZNjcY3m+F5ix&OWh51U>K37?w}m6V9I(~`Ao`hRoH}YiBr6=c
z8zk6m4fe)Bcgc<38PQ%z73@g5p1|=i)E)e1Z>RBbsDkR`G(1Pl<vHg+(PlvSq=@Y`
z%3L_jnMP=r@>e2XD70y>?04Y-P)x5tyTmC@&@x<GIGK&l?1$cyiVYT(8QXf>4WlKE
z&JMh#y^)hqclBypM6joLav1eS%d9l9mUxD<Wsv0<Ys32N?`o_PT;3|7QkFuj<vl@F
zAV7^G&|_VHdl_Uu;be^eF=EIzq*$In^@pfX>CR0fF3QVzEE`LxLik({yc<T|Dz{~Z
zPAd&JE6sX^Qjeqfr=oDuYQ(bY9DV5|tb)j=LQ4{N%=tnqSXpMu9$rEIca@aGmRVKj
zwFrg$>Qz7se4|dOc(ryyL2=sgzE#0B!|w#fJw7uXX=RIt>xbx1><vmPyYLp;47_d9
zRXP||=MmY~GFC8|CG-WrW@)Mi5(2e%hyu(YK<!yUz2Ew~mI>V~%K-Jo##<Y6f*V3D
zaw*7%8VhCv55T4W6pY|jX|aY<r+r=I>ZIJMBc-+3VXB?<DqDWFxk8`ew2>fG8s^mP
z3p}($p~Fn;ExCDuS`2VF7d1Yp&{~u+PIAexS+(58i6v~JofZQ0yLjT%n3su0*lg0y
zD=d`Yoloms3@mff-d1;FipOvxZOG{4v#eUrt(A!U=*>L~Zuyzk5In_Ot+Lb8s6z|<
z9kZ$sVPN@w`+QR1_7TTAdCNui%Ox~Y20G#D50vaIF}^vZEn(cR_Z%m6(ZcABPA*wx
zBPhbA@RA~=M~V3F<g-GhsS$_By7pG^e^IzpZ4pm%lw=*}8EyNMX7+{1_Zr*dz;B%a
zlEH^FXVOY9{E$r%680RG866+a1nYR#PAKaqXAaU7B?TKNH-~r+9Q_}*zfT6b1k=hK
zW=|Z5103oStcs(~0-Mvf7qnSRqPdBeOTXsxLy#kuOhV|emK9o@1wyyTk%y!i&qPG9
zz-^Er&f}YHvtP}ef7^(VxPk%(@CFsg4!?s`WZQ7Vf%ts`5lRG)qel5L0y#MHs*k~n
z+XE&QG>Duc6?;7cV^cb9krFcs#X~AMTU#F1BXy_#sdoI$un|Px2@j2?(=cFEOfi>X
zP<b7Vf2P*8OeXI%1bE-MWqHdOl^}sh18ovZOCieVrG8YG@*zY5RFJZppy${W@Sw#v
z$lRwZ5vQ%6nMTMu;>jI$(UukJ%A@~WtMV{+4`B8h44PvxgtjCbA3TiNs-2qKSfh!=
z6B?p;sPBibAZE41?Mvcxum(}8KH}C!ZtXjlK_;*Fw?f;WvCVg5O}74;U+U9R5YsK{
zabhH!(x6p~2r%uC+QMN_QIC*ard5;Fv^t51C`tQ*;^6a;uQ}kPBdul9)<dVB<Zpeh
z^zHyWoKG=nRy95ASPfXmS>WBE)x^{}E;m~hNQBd&D{LMGvKOTxJoxkzxvFStAF?B<
z$U(p4*B!(p*=Eq_vi7^oF|9Uim5N(p;b-p&q|vE*rMY0!i3<{z+<S>y0Iw^*7OjyX
z+6-q`$yz0z@0fL*s*>tenyr?i;`RtVZ=U<wn7SFMReM@nIvGtP&hwic@=ozsU;-UX
z_2dxE>Eh~&a@s5waCRdu);Kv-iF#nrRbCo-yrW%UaAa7S+8U$+LtKmlbEDnHpZm$_
zv}vx@CV0z3Y-YLI7gV~0&iX7%NapAh@;t1AHgM`9i>!2Lh$E-|aNX_0>0?d_Sf#22
z0?-r`@0+rk2D1$?EhtOCKjC7s697e{f-HI;`z{JZ^X3RCOo=VUeY#RUq_2rySS`}^
zl~lWT5qjytdkzbNG}A&2y>uHdrBdm?ZUYCQ@3XS`1V);KDZ`k=Qdf1vTZH%eOvN&x
zI<M-=^wv1CDlGPdb!O&skBQ##W9D=~KmE(^4u4ZosyIwz>%<)`tji0IOIpG$O88RZ
zTG%xfor>NKA!9d&!6nK-kq#Lh@#Tc)=eu#5Et|<RzJ$**UVu47)g`sGEil?DjaZeI
zH5(`Z_{>UvID0|N)0J*U^4}2TXL2|8So_juIIMq{*|WS%GScm}#%eC^D#=_Q3tj-u
z+X5O-_0{J!U-K<1a#gjw^jvWL6mZK6$YF?nW4c}ef$H!bkQHQEtG}+-UfGAR<%tt5
zK>&o##6&E4y;Occ3SU|R+N*HuMnmw)dA^B4wggIMBZt9`{(fagpw8Md?jzL7(p4v=
zgW#i7_p#NASuFq6!iFm>xyojj0*hnjHj1H(;~9_3*hYj0K(dx#946KoP>ERGz`=C6
z&QwG8g&~XX@yBgwV?4g*xiL&=UyO;4)htlH6aZ2;qE(p#sp_=OZe8`X41uN_+jPQM
z*T-86Iz-OjckAQ2X+xfpujp*HyqmYyHr$wh(WA>~>cjXm=xh(~=p5N~(j^1$2w~xo
zTcf{Hc6LR#X3f*fMXfT~Z(Pf6x^1@6+y7>hYU`?Iab3}&`Ysr~&SZZ8?bT~PXm?;&
z*`yvZERx!K%jnQmb%|P-D!cWe@-+ueRC*&f#lF6%ad2@l_-F|99mPl!60LUgYP6XI
z0bA0v6MK|l!g$MQada#z@bK)*C{Ve_+UQyi>rF}FS?)-ACz3)SODX2t?g+TXr)5bv
zz5MQ_?0twWo+f{kSKSAECxQq+UJ)u+g0`D-OiJ}O1lZTmaYZ~q1HAHYE*L{_g_AUt
z#lKV0H!F$T^Uw>%J=jSf1z}|2G4gUOxB5%4AyLbg@j*+x=_@hEr-hP9>vN1_<BVWD
zMq;&Q^$~TyX3kv3^>Ma&WzIOBWSV{N+Eo9`EfkNN#sPKtF7}u)@xWQXMHb`Xe{sL@
z3~Rf0%kXNq*E3X^nik{nIeOIkFzwqsb_r4(UM|CiVYc2iU1t0hV|64@&F$K%?TX-@
ztk+Sn+fXNwsyu|nt2$KieI_l#?yDQe08XExHXmLpZe!_KW9eM!Gu5g#zkiu=>d-DI
zgpp(a#r)5)*Z;c=Z}4|yn2%~O9BQi@d+55VCvv(=L$M17HC;YXXgnYc&?8;CrLi|W
zQlU*W(G%B>7Zzgx9VNTeA(GUQ%(}h%Xlf#7A~sa-G*KRslI2wk5+MV$B}hVxk(KB$
zB_P2#GUZ}4oelaL0h%f-ZA!rrA?r35LV}awjxa&qR)>&Z<?b#gB2W?xQYIw^@<k9n
zS+#D@gA6~VK%KG;au9-ya!tTfIuWwDb??~}OORO$Q=TlmA3YQx;az2q7`5v!`%I*}
z3nulg6o&`wZunIA8`|vZ6Xdk5b0k@+gDQ$c9S1Au-N-7&6R9;xIAx(Dgqx&0HTuGd
z^kOvvV*zp-&H4S~cR${DGUe8)p*%E%InRp1v<mY1OeHBDG~$ER3!s3%rwI`stjuL}
zs9c-jz{bJp46>LKv2fs5!|)LEfnCdT_U@&Z=t!cIVeCyw4PUQt3xA~kgg&lDR8+lv
z{FrK}*6#kkIVuysI`UpiK0)xR$e*|h^)BcUH9S-#yzx5QvX?v~_Kys_szqP!^;ko{
zkLBBTX4f3nK_zBP1(nS~_r`a6v|B&VjC<?}dNnrCwt*>+J&S5^E!sxbg)AK7$__Je
zZTxff!0q8bRF+<ta^*j0DLsx!eH)Ob+}S{t%$<~Y8wfv<{$_}%@$U^wqrWG$OkAHG
z1!3`T<?^^muCgS<h-7>Y*qUXxwjL{&{>W;H)_}1)4iYfL>K=IX?G1V2`6BP(dobEa
zNYtb+)${?@;=pWuWG*?wrrz$4;x5>(ZY`+O(qgjC;!yFpL^%I73t|X5_D-=@Luy@y
zSwokYup(v0Gho+r?Da>s@85$9*5%eeR|fZQeP)(}FK!3#a2dK3JiF^C-wI{b!TvVx
zhR7b^b-TZx7OrL)J`tG=w5-+->8)<&gDHf)&SY@5Qu6M@4}llH9H-1YjPb<08{zgk
z5DXEHIQF?3%6|k9CGl7KF1_{LgFV}llvTAwq3CT~LMn4UskeuYW971*USuh-dA@R8
zG39c5NAH0hth62R`iuwQWbG^zWKa<gKr?fxrfppJnZ~cQzU5H#5&4B4cXjo=^c4%?
znZ8!SAhlOha$azglGHqLVX5l~BoQMkD6R!*fuRn~b&Uhd?tm?i%lVtTTEH#-SIC_9
zt)ro;kkEBR1xY~K){QXU^$&?XB5USvhx|47qDJrv!>%7S{D*FY+yWUtR!?_bJpS0G
z+d`@iFi{1G-CJn~KAp`@$j8VKI3RG^4Pvw&tO<EK*r)1nyUKTpRyi?tVfJIFfnG1$
zpQQw%WA}xmi5E4b_>XBL!^~gtxRYA?=x(JFzF|u9{gv8E{~;PH5SihE2EmNm43+j+
zp!)NZR)W`AaNa+-;b&e!5;#=u0eBIe7=b@^>Q`>Eu&8IG`O;pZ-BC9KvRp_=BO=e^
zR0Aljm^Y`${oPli_AbL9avn~-$&^`c6jGv`-dr6xt!t?hoUmeqQ1+iXgpLN_NI3G#
z%1%ZdwGd(Sy47V`ZfUWoia#+0P!ym>xMg};EQMA9Ado>^X6S!DnHs7oEdMKzMNlJY
z)jOYG_Ul0@eEwy`-qXX$YA58&AQmHGPYae->SE~EM}*jdH*PtuZzAa_a#vwYkOvo7
zmc^Zr-l;?w%4nVJ6YffSacwtMW?*BrF<YpOyUwCCEA+`CW|?Vmr6%xNiW`pj?|G|G
zO$X*UJs2@`()DaQLfdQkGJr%oozpI#-pkFhj<oEFi<CEVo(R$9B)5P~p0V`)?<+&Z
zTMdZVVgc!GNp5k?4dijQ;=jw2!JrJ~CLECFMl&RZzat7R?O`OZI)^dugerjZ`zc=~
zKHcFi)De-d<Ma!SSC^rShcGcQw;rPnZp4;4gB4Jv{-A)iSM@R>*mkZ}+cxX?Fq{b3
zBqnuhXZ-Qw39eu>FbEETc&60&=X+i=2orFk(oBxfT?#FQ!m~BS0H^bOFw53|#1*E;
z>X=}R2KiQAV~AO5Gv)-nk2_~MS|HV3F0<J~qfExnsv9}67s%Le87NctGw_U;8i}y0
zso~Agp$=+Aag@8gJP~!uiBBifkl<SSzT_f~-j%Dudh<U^O2%hTQ?%Q%@nv)kirDV!
zNDF(p9`2{jCqTWkHZ`C1Q8SOA16ZKx)lpQsBpN98vTO_lsy2;;)DO|<x`&9XQFR?O
zRM*G$EO#<Ax8eZ$-`VVidB5pGsK%%S5q{#yNrOUIPO9CL1{ONm9*cg7!+SJ@u-ij{
zTx}2@?^<-F2mH=#B>KIl#Hr(C;sh3|71y#gHJlC8dY*QbT*u26c|BZSyb7F5=y-CJ
zN@0}37FNTaHZ_4wl@aCwkPUuANX3i8F0jsLP&cleF~0$P9R)uVZU>0m@5*8*>`lP?
z*Pyd;v)ZTeJ*v+X`6YWxlZPY6Sw%3<dVP+^Acw}9?cqPQ%yT;^R~12o2?OG#8Z7&;
zN`{1&=iL+^)#brAQ?08m^EWQwmb2y5#8pvv^oFQH)l*Z_=JUS`rSdqma^d4X7+5<c
zKM0{leH?>L@?i!1_;|RxGb7$qv8F94#$z@4LCY29rFG_#ts;hIb>P_Ew#bSh!W?S6
z=QJkXtaF(2q6=HF>tv)@359SN4D`g(rcx@xzmxc}1e}jc#gf?s5x^pdi2ln;RFLh&
z79)jt3n4Hs)u_W`!Hemu{O`BC?*(pFR2Gr3&?U8jNLU$&1pUiKsfqQF$l@bC`(o)<
z=v8CTVuW-R(KgBCNpT#m904_?L2b}Ff(V*2h`{~J;+2ECNMXmjd#7zv>jbexiS$ES
z*)mx;-h9-4ys{<%)PmAJh>#Y52-?3as|qq`*=ELi_^Rws?$!)y9q%roV3t0Bd@61y
zMMIAY`G<7=5QvBXK!l7EM2w0E?%p-W4M!gfcU3N}L9MeMQi<mSA%gSv=|m+{$TitR
z4^}?)a-+JN{GLL*KMRFZl%o-2Fm)>^bcSZxsIr(w;z;6z(x_BY$HDJV*Vro}=iQ(r
z(QiYBTjtlgUJ4Lc&+uvL3BO2IY7iL|?muN<kGShOdVd8SblAMpz6>M?X&^7f1ZlkP
zHLDGnK~!Nk5lfGu7=F<i+UKx;N7&z<6qnro97674lAL@TjPM=f$8EG2NurFLh+0F!
zm_!glFWjoh%50ZV=Yn;PuClHH?Yy^?HO|#g(Vl2yn(R!e%I<O*T1;4p`Yc`|ZTqf1
zCp|OWH8hK(ro)Wf7IogMyUVWa?-Vd$2{jJQTu4ld+ZI*g@9Yp(rNDR=09Rq&ht;*E
z%Aqe(MtH$+B{DxnCeO;jj@G;H#4m(!71mC8uj~QqW}sKY<s0O<Qg+v7qvpEFRUvSd
zAvDltqyA%)tCH_31Ng;#1(ffsxdWy1|2jUS4{ymQk8H^UK?!ucjAgz0UMT=deE&&A
zt`pVHulal3B1KfExnX9Tm~*=xyZ@Abn;c$Xle;D#kF-BSwAbG^;*6n-g*y*EcHb=r
zV`T$eCZcOYZ#nNA@n^Nql>_{K54K&~OUXL6iPMf%+z4xjFw=R`5RUE^-Y^ryAV)5K
zh-#yj7;f~RPL57JoNUV4&I%Wdsnc*s{)`pH9%hoV1{WgXU@bIoVyqK^>e@}i=N;|#
z4#6#j?kKeG&xZE^M&8KvRcfbMK<F<S3u4|>;M}D9Yc!Y5Ky`V^vg!mrm1ocv&u}|3
z`lqgi(jkie0o+*27;lc@bPw|$q-QpO*&((JD&VA>FU0_0(Hdb*QlZy|iN}`$%;`(2
z=sPx*qf_D>U30ynh()ePG0>~rmi))~;<fQ<Zu%wPX143||FWH4u;;0|#IK@ucnp;U
zGw}!Q+^44XOHj#VhW%xW#EAEHe=}Z$dd1{nOcAG?V3k*5#%}V&qO^{vFm7askY9Fq
zGUGa6wS3ltL}J~`Io1{-s@8lGJR{y8BElFcid%ilIY`0~F%cJ=3MfU6sTTKNpf0gR
zM>Kt+Es^M<iN^3349pFWeGaAbDG})Rk1ULn=sEGr+vi(kd+pt`I1KR$8ku1HJhKZ7
z8SsmdjTN;W!{FTB(;D{qvV16b&10vUQk+si(mx{c{_Z9ENpej}tUTE!6Jc;uYeB?T
z=!`;=6rl5%ZnRYyG;uh{rfawNje_~90E%yDt}1FU(hC3*&<R{GEo5a?6hrV0xRuj&
zlrTdhy$7gH#q2l_i9hPNKYe9SAB&7(3=<7UCs89*+Z9KR-2g0A+`wy<Y|9h$%;r2}
zMl;53GrOl!hIE?(q0Jwn#*^85Fl-(3uT<|(MD;D!n+vti!6Qz~rn%w^NUB+|FR<Yv
z6^J!jW)3Sr7<W}Oht_0hTzz|u8G>IVn{*@B%QjHj!*Cz$A`^Js2Go}L6ps^7OeTxI
z>3L>Rt1PHZ60TgPg&hP9%6iCaWi=tTY8qnP6_sR}OG|N6=hma<pv#S*%UYnzRW%`9
zHUAH(98~^4rD{<5|B$>5^pKx>ItcE3T)7TkLH#^}`n#^IBohMl?+fDNO$k&XA5=jM
zR3UWSYV>ntyOaBC428|W&WXlTc6Qi1`(=xFc}+|<2RatKwC%k*r5On7L#l>h$Dy4f
zkf00vM)S9~Hyw=bmOheQ4@N0tYr!m@)c@apFs2YvBr_aP`8XMT^8A(G085nS&>&**
zk68XAR?q+{s&iISU-LxEL7zXruT3G=luE|o8}ikXF-^tV>1jqo5`YSE$YzyDq|tvM
zN=u}905draBFmhgAp)ZrCEIbZS_@T#cceBM4q{(S<(=)M{G;^v?fA-IG7v^{K;7Zk
zB8wNPtr8$em)CJ&B@URFNao1HVlHxvh5X!Wa}u`USu+h>cBmPHs@_vegx3~J1W;Qd
z+hNS*qfh14pkFy&v-?uLEs1_JlJ2E5pSH7<Gp^Y>bY3`%j6`dGgrC{n7I5wSPSeFy
zHx~uQUjZoqB;HLQ0E0wB!!a6Ya%2>7Cno058~h9?Xpe_95&Nks6NSvANXN#_DN@{D
z_6HP2*<GfrTUzw;9o^bKTFFZT%3P_4+Z^RPEeqG1({5)BKN6+zijuxeNKJlM5|W<S
z4?6sgkUJH27v!U2tW!~pAS68w+nC=Q8Na?^;jZ_wpOR$kJjL`o>?RuS4y-`X+^px>
zl%Y_Httb&of!g4U1GV7_f?S523)8zq+Y@i*Ve<IQ!)$G{t0K5~O~}#BUNUhM3%9mT
zCPDlwG<3luSz+9O7Ry-Gzc0kQp!hM%g_WI<Z$ryR1!~j<A$GbHutH~*@t9)&j7FF?
z0Nbf1v{3xw$h@TJRPGxl`*5$bQgKZq3-&TBU$N~aR%uitHF9JSj;wMd?+o9U3yK?f
zjU)&50i~w)<JAO0$&vo0BFAQ%RP|E#9wy!TB;)I-8vja{NXdHpF*5toG#4bh*$fwM
z9i3}UyT5$7^AxnLOtuY-E$F6c5!K(i&L|n$CmGJOi+n3tKTDR|kBK;&r@0JX&84se
zS8e%>a@U7S)>&Q3EtK9RTBYKk@n_V{bVb)=k&wXhz<!+&5(jq4R1VF@!^ldKF_t12
z@v6d2w2NvoQx1!M3+<73m@VjVmF5xznBK$=6||#ZfV_-i-MCIvxEyl6DIq7=>%N{F
z-gzxj^qdjMh(NIGS*4Vtl;!aM0VV~Il9ZWioueZKl*5iYs3qdSN%QhO!z>9<8PS=m
zH~@OADF<Xj=L(oQBC-5S;x1Dm3iR{@<<4&n@(T1a{a@}em$+o{)%yJC&kg*G(>{*E
zu;zQ|NRv%p2ogQnv&B?LOQgW*L>Q0|GxBo1=Q#|59G7{M!KAOv>K)ve8If`nQ7Pt)
zrpf_hJXIL86Cw&@VBJJ#Nl3F3d;dAT|92XoI0gm^syAzo0jVMlU0&p)rXoOpMwGl5
zEt4TZMO7H)+fME&)y(>*{0b#I?rG5#uDO}Cl`HJB(+98mDz@`Bn^#BNeNNQL-)OtK
z3~N9r{JKJZ5Gp?cz$xVpw;!zeROE%3a!r$hNtT$A<AuD4*u=0PqLG7t)$#c*sws8)
zTU3M6QS{SXgNK+*dPu<l4Hi{#_G%XO#sz+o+wU}(ihA=XhmB0pFi8XgurbudbMC)b
zli)=oY|MwUNBHdWp`;)tUMpH89V6A*py?(yjvDUluTnUNG^hcI+<QmWbsKge6~`=)
z`*X{++E9Z>bbATep(<~}zIqKiEUpC-tR4s+h;<7DGp>XP!smSpEB_`{on7Ki0&lxh
zgtmffOXub_MnDqCFYVEA`(Sdxpxms2Lt?FE_MM&Cuv0zR?TldD6-jrBfmRO#qJV4T
zra}`-nq=B)1u1yA6@|7U$)Y)^#*u)re3nZ=lLEVgqj)ZxA^J+x%7r9J;xRMg^l6wB
zcprJ9M4u&X61|{wqq2j<18om4H%BJ~>lb)ddYBE`oD)Hzw@y*a*h^)EV}8`!B6qYT
zu2u0280Hpj8xc`P-#~Y!zLPOp(q$PDFaIN6O@iAXghJZ%-VC&e&b0;lW07axL4XFT
zg1=^)@d^lB6=Q2Cm$?emb*U=!Fl{V!Fm1eF0B~a`F~fuVg^ZeuosaG6jRUxW67Ch8
z|96(@$ulboCPUQ;3X&+A8p3VqlNKA<8_MMp>dr??0-bMY(tKr(7ptRe={eq=;^n0e
z@U2YmT|i8ikwvo?=uu=AkXJ<5%6Q%?%A2a{bN&J`E=5m~$ufxUIuBx%1rnX>&9oAt
z2yHD1H>?^VZhX{yP;HQX=nH6cK=#y=0+Z4RNp3~#7~7l=&Uks~Vp-9?T(X9>I8Szu
zRQ7oJ<hgA6=qouZmlK)7P9=gZ*y6eO67r6S(UJ<<`~2h(+9SAXTk=eKc|~|phIY_!
zz4t@ZD=0D%ru%aZU+l;;LE_dmRZTxjjkJ{^n31B$w0H$@&j0{L8f5ES4RrJc6{96Z
zR>IaGu@=xta36_-1nZ3-Lm5An8W2X{+W?YunC&>?kUF%Knd!Y;_dj{Bp%oCtPjUPL
zHHIL`J>v^{T!HgcWV<tHYqnB?_+7H;qb1{~3ds`gC7d13#dCVJ(N{m`PkmL<^~6n8
zfl1G^GGa+iLF(M`Qza#(Q2EKarj2CZ9K{%xKoU6FRb+kV2Az}|FgKJ>{+STxri!*G
zil4goA<sM^C!eoGyChh{!d3>F-s>vFREFD*N0#7$#48Qr&x|Jlz-<6SZv8X{VwkLf
zjs;Bzn>0Co%K5<<^%qDyVNRgYW5?R&Fc7T?d|H9zBa<5BFC+$H;KB5U*^E4szK|bC
zu$4Z4It}7KpR)s1rtno>+yxu-yp)f{7?736(Y4nA+?g3U7(wbz@lzpBL&()?lHAx?
zKZW}LY=EX-mT&uL3Ht&I?phLOPP_y+%inO@i1QjIivL64$H7@d8kiuK<=H?SCXA0B
zPdHG9+x8#<7T4_mFO%gs*t0&=7{nZampl^}G*eixVr=!_{=c3n<AgK25E#UiG}1{W
z_3mbuU$F=d9u)oK=jsc&hkxgSQ4}7OujAGFK}1ExSXi5MsS_5S`4^nn=s^*hzje)@
zdxuD~@g!3waK8T_4yO!Nl_r<I=UI%Ga{5>JM>K;ELmH(t0g!N2RZS6p=s+(`SsR%L
z$`6)P&cU{`(ZPT&_KrnMWAoHtW=zK^RpVmho@a=AWmuW@d#BHo&RMF%B)N(5D7E};
zcNPsea|^7m(PhN~{V8KPdU1BSS-InNB~XuLmN+CR^b*MLdh#vlZ7hhMC;A6D4fYR0
z_L+0Ce%iK)H@@)oyN4`v!%H_f-?};<XFF16vOLVTmbn#c)%={#coLNNBQd;$Kc6jt
zA;T+%s5j&hu6|4xsU}AVTY_|)g$!r)_zI{VgL13e%^q7|#`}5xwL?5mFgnu?FTvd&
z0Yb|b?`hltZ(n5KW`W_(<oO<xAZuQh-K}Hc0eQc-U*K7!s807W!5XpvKhM1DZTbUd
zg}nDGhUWBBjak5+treN$pG@;%t%v^R$72@VZ?8dYc>K6b&EYsf8GhnrX6wfjG>iNL
z)40To2(8@6&qu6*(pRXgdZlYgMt_?jjo)IGek0mIqv>gc>O%Iu_84mGL6TafHJ5kx
z%<$g8=DngvS)f+WE;f@U?F<=B%n(X8%4fTA!OB5TIJs8SGOGz6BVB%F^=-M;vC%}D
zC;nT0Nzlp5KSU+t8Rm96cvv64lS+(+>7u11XZIp@o&A<)4~t~DRsuQPdf2DbrM1X8
z4x7zDH6TeQ@+9HD`n$iu$QgVtQpy*T4bSQFE9{+!RD$7RAH|!KzYR(4xyKJ|%5NAu
ztMFr550}!{(NHrbtK2s!$H6r$?s;JKmbp_BhC|5%knhd}T;3*)$Dw$Zw)J*|e-`49
z#$sZ)*|=oSxo_r7PWhInCRF6)h`PV^+ORs-<+IxOUZXS~uY$UZYwO&(tiOC_33VDO
zQvJ{-9xK*{2q6xo>R{&0i1^Ld81_-yoGx^1i@hZt`KfA#|Hkq8864EHebr1dIxV#F
zsVL<!hJW|om;L7a{uu<N(bnFCLW+Bf{nT+wsSh{+3gkwYeA*tRrX3u<u!`ovcZ1*B
zm$3zz)uB}G$+mxmF3>}gmE1}o3N_MF!)6RS_``Aea2V2GGRk!dT`&MR!-S>oRS=ZD
zv+EnxgPi*ML;#K2Iv#C-45_r&(yr%I)m#(dJ`9N@VaEhF#vsUiE%>_RzlZ$&6#Etu
zsdvD$zH`vLWcqr^{DPlCT3sXN3}$gjzMaMgB4pKk)J>Dqh-*%S4S`KbY|77$RE|`t
zPR3>6i)(29S2f6#;%6VxcN^<RAM3OvSd%3GVRQ9Xi&l>MZLiy9XP@j@e{TW|Nt$oS
zt^(Y7%QgPUe1xm>F0*EcGL?un!1;xclnb&4D09y)xLeR}K29^-I-Qg*-5PP>V+<Uu
z?t%`KjLbhhQoIuP#&!v8T_T~dO2~6Pogn36)u6$qE~!EvcYAXWL(Gr_Cl-z1gMaHv
zFmU=8KbGaqO1br@ZV~hC#duK#O|A~$bZKOmQBQ2|8%<DWQf+(T_@MYi>pS8>Ha^}h
zyOYI6hUzT>c;qc>Ng=53Y05gu>ztjO80k|A5RZ<8Sv>WjpnnFjc`ZKusUWr)*fmVt
zdBVB~laNw`$`iRP2n#I><zItb7}g=5tl1epzINAO?Urb$Qe~LfepZvhfkPJUO;<9h
zi@E6ci<G0FS&bGorq9F*Zl#F8RBonDwD2v|qJT{}UXVagD%m1h9h*B)ad6lcMwBw*
z9y5{908@^6=VAT%X9*3RkT0Eu1T_&psv}B+GP!Hg0yk@2g+1Fye=KsZyZehB6IO&~
z#>@vtJT9V{$17Z0V`HOpfP5ZS-W#_PdboCp^_T3o6s2@+_DoTrCDw@$G*SW9f&$K5
z`YEj&TX>L*Ed^Y)1-EmKewYo0S^dSHP&e8p<@n%+<h0Mz&0b+&0W&mhue2JVAVp@p
zFmZ>HURBmSu?!)4|E<(tI>|U;gHlHM!WaXXi;M#X@Pv^I*kUu|LFkBx0K;~{u_L{*
zCCt{(lIlx%C6o$NB#*eXq{{xF4yLp+r5hU#e;q}AZgbSgl*Wij+W5Y{8@G`jwDPhy
zr8$nLNCiMxSH#A{=FE4Z#lB$$_AA?_8-$ek*Oq5|SK-e(Cw)h{C=2{ehbZ@*pB`5H
zyK05S9is6fTX95~8fWo19+0!Rfi~Ge3P`Rpji?l$0^O>Hd`tN#w^Z;Vy{ZELsfLnq
zSOUa}SS-QrYyrd<+Ve7=6G71Rso2rAhtTwrR6vP~P^<lVR1;xHe^*F$P%{^T_LjF%
zav}-Q8H{`3$-3ebY^;r-Qxh(XA*BUZogx|sOWGl=04t<qs4&I?&dZuNmchiW%a!?C
zB?VBmIwpaWH~%=yK7ae*6Gtk-_~Hr>h2~s}Dk1_rPZi1VM6egpm#835nR2ICla)_L
zAmGXI8aidl@zSag%D<Gij)3z8v{xZX5zi?F%X4+o#VY#_mJ`HQ2$V;hsY!CB+m(9C
zjXM`YEUSJ=-#k|R61n(yK{#Ef9hQE3Tu|v*{VIUI)d^LtJJ~Dmf8*<&f_n?Pb?;=w
zwrv|Lwr$(CZEMB0ZQHiF@{esND_`Dy_TJ~_)K}FtW?#&j)m1$%dj9$u&seS5CgYm0
zfmaPsOuIv63;?Iz{(0rEn%%Z$Zt<1!z%|vNqBvyop9(WzQ>00IaMc3EBpg+yh)OE*
zCRLSi2}eGae!fXS;+DiD@t;+tNiv9KHeUe`r5#%AvqZ&X0ng034LE_49?BxA-3Z_*
zc0BkiwtE3ukxlazMBv!<?9DT1AHh(!NHK1bPQ<s}1RG+JvyNIw%7&21{^#a!(80FW
zXQ_2;N?oKoN*R{s2bBU04X;Xpjdh>II;u($eW<i<>4CyxO2H)ajt1G=3UMa#m*sr)
zDBg)bhfe&|hWDzbO)8Uqlt=qXx(};l=qia;Qt7@KE<Te6mS(R|zF+1gklRCvh@W=T
ziQ5Vy7;T22QMhk2k%K!H<d>?xnv(4}sD?M^Q%Bt@gQ(S$fQn>A#Yuk3F6LV4@^aFZ
zWJWL+OURUg#c5O<ZrO*e=ziWysEI|aDLd%ZNx>1Bfo#g;ZPaP0!JT}G#8g!{<NEj8
z7Ns!J5h%qCRj024by2Fa5XE$E!b(K!P@fPsfC4XrVJPT^A~#HSgGsc;c5qM-1sxTn
z_{7X`w@vbnxyGb<Wk`)iR;emgQ4v>0@#UtMb(D<jSy{-A#xzw0I$>z_m=|zGF0dw@
zf{8n$T}oo5Czf=Ok`qoNDTV2866p?|6-JT^rR7S~Fcq`8WIbp5DX2>NuVqFOm^YS{
zU&V=7nlyxHtRysGQJ=NrS3yd=_9mJ-lXf!bB_)TWCVT}o$YCa?ae5^&2~I(Z8?J7)
zlPYXyr6K$2Gi;Ucn5J>8>d}IsapS3`VTX33UPR@@D=HkD*(iaD##Ckxs)Oj&l8V*I
zs){M<s&1~`Wa`zG&B}x1(`6c}P;ty|hB*={<D=z?_~#bpDK$fdJSyQ<&>9g(CZkg8
z5iOjVDUGa^D3g=5`E8{Ws%d^w>ro@yjaI-)qk7dC@z5K1D^4P0zBP?28mY0=igLhH
z4a9j($fd@<xmG1M@tGl=jTaYJo<V4(`N+q{RBg3J5y?!1ZIF_oHVN2<g~<T5jj-y3
z1gQl%U>fGE11+eB24c%LB{gxThx$wCPV%J2C|2b`k!?~UHLxgVF~gKo<?&2PDQGs<
zy2)pKwd)E&IxyN^B_n&X>E2G4BdHCfl(!VqwZW}KF&b%JGMNFPO4E{CN@LVjXtB`C
z7%8N}giN&!F<ME{&{Oh`7EF&2%;p<w@QsU6KP09MU@~B~@stYnfK8IGPwoRnT2Br7
z8qZ+TtHQyB!Jg7t1J)iiq&b0a8P~Pv=7deV6qN+~Ux5qIoh>I>!%Wp#D$I|pTOs=1
z3A3ww?jeVw`B^obVn#CKcALx{?iG;f)2pl)0+wOaDwAQ-D?+7b>eeg>icdbG0bqwq
z2^?H^mL3OJCEd3`Z4u*P0y$U5i6NUXFQh>D;Gue!sg{?Z7CSNd9_cg{z`0((dfJR5
zIkeV@lYQWQ;X=Ak-V4qi$smqkuW*U;)j2%g2I-k}{h>mq3G;Jr+$0G(9bMAdbO~kh
z^s+|bP2MO;p_5l}beFF-5|zQov>E4p(m!pkmKDlo&5Z_yBoji-xQOn&GjsDq;jVAC
zz$ranMgf0Wk}Ni)p~%d6Yj6U}SA}(qHGICVQLqyUlX26}PFLp%n=h<-fu-H0y9}MD
zlt3}whh+7g=~ILw7JJHckz2!zn1>ehq9p^4M4=^}&L4I3A+DGBl%-(=frpsa{&RSE
z4oO$TPZZZ4GdC!~R|t?)uEW&u7oJ!Pip0BUhlhktcopVlt#bfFIL^O>we&lNZww(I
zYqi|}_BqEXok?wry2VwOc^6>8yS_=v-kaCy6md>{<%5I*lPO^<w5D5zpeAf&>qEG7
z1G|8yV--B53Xoi?xY^VZ%U6FZHiRbi`t`l_DGnWz^Tp)$W7hOuY~Jfb^erkr|4;bE
z7a6wQ)GwuNx@zqnqcD-!9<6|_I4B?TE4LTKe?ka(qGCXI9~f$(g@855T<F&zBi0_&
zg2Mv{ZIKd085t>aZ!?@-wu8VgmH@EOB?7B2c6R07->fbp;6rwM?&0`P4k>{&<OfT=
zx$EwFT0WhPF{I<mO*--5L<wi6v_jx3SgF=#HvxKZ<y#kl%^pZo9T6Jybi*$$mj}4W
z$jGy}@K6WovFozq6~P|;)7Nh*eG7t1;2=#HQe3X-{p_b<B3Jpyf*LpB;u3Knt{@?e
z9g_=Q^;Qxuz6CD}<}fZDyt=?|B3;7#kT{XtM3Jr|?vShlj?~2PZdC+(F5wCZCx<J7
z24zRv<+vJ+r3p!VkW_(zg;%18eQR%syEqVup~YR!XoN9mfX0AdX@P7~pEQ!r;^d4!
zO`?F}#27=e$svc-K)@Z)9FZNn542<*XmzXxHm^hp`=DS*b1u7#&mb$#fnk*+sBCK?
zZu6c{I%W=Cf_svNe%vGOUN2=N{$vl{x&;G&qdc%ev_013Za9~?aXI3u%R0D(u=cde
z3Eos+Sh6m6r=2Yz-4i~6M+{)lb{SMaNkoE>DSj@JOky)GQh%AmHgZSJhDI<7>{JE*
zvZ;$B=8!YZ!?6$!%QUv|yAIf%DwraKtkKsZlU;mR>mti=TMHUSeV(u@J6x@S6f5`?
z+)Ry|@AY2)mBfNDZobJvCq$>t;Q6c%?*8K{7V)?kLjwpu&f73HA7HzJmz^?jFy+TM
zP3RqU3!(UvF`Pp6L^|ZEB~hopn@?U$59oOzyYhAV5_Dfr+A<C7x~CHspE2%OV{Ip0
z+g_;yr{y^c`j9KP>wBjC;wF)Lh9fRNe8-r1HO35Kchu|3Qw9<Qa=^r>C0cL@$a2t~
zN?3Z+G3iaV=nS9YQfXDH%C)_fic-a|Ecvk2p)efd=>!i!Sx5GgcDRw@*I>^8z7Cz2
z=k54|IMZgw&MM^Yb80O&Ptv>HzmDd(j6kPjDM1Ia0P2Ewku%HPcI44tqdP*wNxCTo
z38OwEn2}R^YNB6$Y)9==H4Hk@MPRfxflz!MCX}%xwyY;d$x`0w4P`nS(sVl6GB`Ts
z!Zn7WE^ffDV$bAZUK8A<{^Fb;_8`8QQ>XS2t`;h4eg3%km@aC|bxf1yaWmsN0Y#0D
zaV$ja5bn36?C7H@xUNaNi5GRY0g+sK&@kie%aa|8eAuG>yhorMV0?Y)xSwhGY>*?E
zJ-<B6Gam7>j#<n-Ota>79ml;lSNSsB{X2D<=nt<1+9w)6G*mR$)NL(@FbrD<RdZNk
zuEF-*Yji@^N4kpnz;XZQ!;xxUx;qpT3BxUwd(@Plv|W^#J6`zdjBMc}H0L{nMx+q2
z$xDtypzWWkPcT1jjYc6OXjvTjkFqqBMjH%vC<wbDUaFsK08!Qj=hyib|Fiji;x*Ji
z*Nuf-XfC2DAf;zB0<I=NE$m;*MHm|A=L=OFUFFA~sTph5vK7z0TN_p<8YmX7%_xvs
zo~2Y`U6($}F>VDNOK<3kc)?(_Ag=Y8&<i695%gyBBEPb6*Jw{dk%5EF668k0O<0SS
zswk>=A(e!wU1vqN0eM3v;H8~aqKvQOa0Pr!VbeK+!3E4p^&zr&zzD5+@R?lw5olJ^
zYHL1w-GkZ+vfAh64)A)|<;oczXRdKpO7%hp>`NYl46Tz!%1i+xZ)MosQb?7U<5Gf^
zn4@$66~E%#Qhh65nTbG%3{nJ`pm7yw`8c>cV%@Jq0+Bt(GhaXYL$y}q>L=4MZov7c
z-+R|>|LZ`%bQs*yOMeyK$ne?Om=!|s-&<^{A+7YA?mc7f=}$OB?Y}vBQ{%;qI9ZAf
z=%o%Smx;HTf7yNmxv2Ylwy4Wc_9%=#`>9Rf5O=c=0q;gXSgJ3&^5sepi>?iCVQsyg
zb-b<{Xd>RjkVThj;5F(e*yKd3y|DIb`uK^<0G+kPQ`Fdvd(lV;&}}#F256l0<v>;(
zBo=*3+L`gxkF_nj`YxUJnYIoPICV<7`z8Wyx`U7sU@`6QbCTY3Zsd0q;9XOt`tXX!
zAWKWdMJ!aVvA8CcxHagG!S1Z(w)xpBL_W@U0za{JZETQQDpdRt^#-Aq)U4ZZ0-<Kc
z>ynyYxC{%|!7mK=K(7li5gBS+Tt+Lfzw%%ek&p)_-d}^6LI_3rNnm3eZ`?}k^sm77
z`q!^+#`t&cgtGU~S?>cNIT-NFJTqw<5B@_R@>03MW;IO<8LB5%-y0dL8@uk#{1Bkv
z*i_HcuC7T?CKd!jOwkT{7+JsCAznLgQ-iDQbqtEIRqk((TL06e7fx%x$GW2j=G>iG
zstf$FyE=Vmge<sUa6CdWy>)Cy8)`jPbvOaAVaLWyk-eh_<-ffm%I1DR&#4aAbqh(M
z`U!oeX!HX0Pm8pLSI!86!%lH%P^sp2yx1bp*#j3Tj0HM8`S16S1^qjldwqWb`ICb_
z$^`6OpIG!M55AAOK6gKUxuo51|GrNr)Ln7$gEt%WSoPcYQ%CqG`uM_|_y<!~&i8vC
zRxYn}`P|Y4MIP;1F&2v(w_Xmd9dZBQf7O7yC6{K2=xXnF9==8ClsGe#PkOyiTjgtu
z=7@Z#JWyd8p3FU?z{*X(w@~*EiQ&_quB$k*Wpm*0A2B3VWJYvoZHbOJcx|(Dn^2i$
zrdX>7=j@n!;s_*|1`xT22DTZlRD6L2DW((G_0+|ZFsG9&4)zXg%tyMfcWCt*-|3Iz
z(ET1*)drJgyi)%6f$0?fcwaE$fITeB$2$FuBv94vze4+a$Cr0dGKDiBdVjTfG<S*&
zhrj<KU@+Q!o2fSRCGt_o3dt)eYEWU`ls+(!T+T3Sl_dW8QqX3OOPzY-0N2Ytl^AzV
zC8V2eIC`-0=}VtGmX~Jkh)(4+Id~hovw#j2ADenRz#OH?#AmT0_;}s(ua~F3<*F4P
z9`QlUOoWsjwfcabsV**TYCSye?Bq2$aq{cpl9&xX<dKjg8o(npC+7U^Bn8{S*%?cN
z4tOXV;dqA{E*%)vVA`LsI0fm(Ek5f;7CQlie9QmhNo#s*)BPg9PzwohaRA557W~yv
zB(>SGiZ#r?SDB4ss!^1-Q>H2%mtW-HpojesuE^6=6wUzk>(a&@Dfq3kfh=+FlTF=;
zqvhY%tw097{3B!NGmE|F-I2><%6F~|x;ZL%bS;tHt|@rF%9-Qa(9`<o#hMi=U4S;N
zI_i6UP(zj&j8_o%W?Oz0gi7tH2L)nRy6j7lr7Gfq0rwYe>(a)=fE(Ak9K_a{0XLpa
znZG$3APYyKtNeu8{C2J|3vFpqv?#d4Giz|mW7h;|k`Vmvvab8)<6BF#_}iRj+24$W
z4FKSK{Xo!C)Tq(8xY<*rv3q&`tsYh9`toq2SVaf_ewR;x@Sh+$>@y$FpW=7;E`iAQ
zhR8dOF=st??ZfUFRS?}2$=r!VYU%UaJHm|9>C^nJo5wFIUfHO>375CGG~C9}#Yr5-
zk8b&e<$SlNxwgF@{$3sVEi0nT*PV30rnKm*_}VjcUAD3+#!HRu%e1d`&MNcYV)2z@
zPFW+)(4K6vtd@3gskQ1(ZtPllXXkOzD(Y2d?~b;9Yx&7<wCnAEhXpIE4V^h#dNG^e
zdCTn|r)|5zjzjo9(OTC)bq?;>&6j^BRyw#b{+Sa1-!{ZSeJ_=tnPv@!tF9H_xtZ!K
z?a$(+%d6ES=B~8Gvs_=W>KX+|vgOQCZVeT_VuQS_%aAXayj@||Z;!gm8$<|Bjomf=
z#-qETLC2-oTEmY0aRvD`Y5;C0>YS6B<$T;!^@i#vTV%kdA9G!aZHrR`QThfwGozKx
z(5#_#Dnm|qkh;lA_0)(E#q!iJ`fsB?JskHLp+-SBw83_pBh&UAkiNwxyr@5&hwnUu
zqz<t3&Qr+pW<{nPIIvLDyX1{gdl}n#odpGU!=S5d{gaoI=jQiu^=Ql{vWrKA2ycF8
z1@Ub;*af=L{L!pYyY7xQUZ=YU32L@**0%7FNK`Mrx6v16lkQa_ZrPKksxjF!+wf?%
zpUrOh3U-`~K^Jrq&hT&skK8QQ9T6CMWtvOsHPh2mL%KOtsA57lz(haP!K*d6#Ki=C
z&ZEa$H?woppgI4~=}P}INNFjDX@4V!e}=qB6qjyCbAW+5cC8+H4>O>~L?O;r2|dP4
zhoXkVvgl)B&7)UAgnzKn0XzO6<(X?r?(fXi%flII42*V(f6UnqF*G@O;8?F%3`|;7
zy?!@nD{+$~kCJJ)A0STwTy_<vaCjntT0R;Z+Y5WH&^~(Mpi4ReoryQ5cML%uK@XJK
z$n8YDNU|MsCY8jDjNU!r?5+5YJE*EX^${Y!OK-TUoT%GZWfegfV-687-M73OT|T~D
z$~RMU;nL2v52Q7&Kj@C>hC|i3k<P$Nvq+T{hkweJjws<mu^U<~z%0#@l)0+Jz>U>t
zD{PTk^V;YUGMz<(F{mE~(1qn9jigN_dcs$8eLPv9Eml<~{<fxAg^5*{0YS3uqYSL(
zk1y|d&|Dv}kRK4fU^Bv?q!2>XC%Q!CJSrl?MPK;MBRUyE*IPjK>Q~wBN*SBnfNF7w
z5gK081<*dN_Sb>C>T-5}L_?sDC7-LgGJ9`DYU92sAJnUd9K@(k)aqJFP#vu_)w)La
zUE+3!5dQjbIeaWEq?qUp1fO9bFItIU-fZ*81bYWwA#Y*7nDXPUmTz+@5=7{=JsVK7
zQgI8AJPYG}MZQ|{Svh`Yn5&AA4k9NFU<&?TzIxt1=$unTfj1yoHT$R@1jo}D{qDg4
zu55j^7fSiqL52&PTv9r6)(v-7Zv^4Sv`@seuj6qCTXJMANv}zk(->_}r43c;;fAvM
zhxTvp-jc`cS+449Vr9EtysgON9eihh<+?zW(RBLWFU0vaUkWv$9YWPfflR3i8CBvE
zS1(%q=IDG|(%=BYr(wa3pSk6F8wFKS(fi`YCWZUOkjG1hm##2r6@paXap|ASZY6)t
z=D$N#E3XWee-qz>i;>e(4B2MhYv%rAzbCLb(T64BweEAqFKzX907+vD=e;^87ZB%$
zBwBG8cWIEUfCc2@JyzA=F>yCVyu!s#9O}toI`AlLYV84a>C$XzYVMW1Bi0%(3q2&O
zjx|&jMyNf)6FW_jmfUF8cE`uS8?I}{{Nd9RWr)6PQ`c1|yTeukLn{+8v~zf2d(2)@
zu|onNW6T85FnK;W$y?^6oCwHZQ`XfQ=~sUBzT#f=)nb;`V^x`F>8j?62&R>@XPs7n
z?B0}R%x_Wg=&r-}_vv7~u+xOo_T79GvIR#TZj)kVQ!3Z?z&b24gsCxtb{`*Au}&4K
z$UpIR|5S2D9~@X}l8u^DvMiP1Q-F`Fu1nAeP6grcm-BtB68w8rVQQadyS4?oR*2Aj
zJv)o!=N}pwXgk=gz8Y82S}TIt{vC81jA(~Ot)ZViTXd%rxVIGinVC#|)!@P?>$ub!
z(T;Mf*_{`Pb(>+NY`bd+J@-B~H=4(WwOzhRl0V9%VQ#zL3MhLs^H8<}_;Y`Eg>Hf@
zmA(r+SR%fQG)>KXe%;WuAioPM35T<XQ9<g~g~e_Xvb?KR$iFWW>TyuEIc^H!oDwY$
z1-z>gZeo(y1oSfk!?Qp}?m5vUt=wZ?!XjETZH1~=<ANRl@+eRJ&T#uW3%I-2tF}jx
zS+^|SHz)5jJM1pst*y<RaKfO{ko&fo|M24Q_r(HDw7xX=7g6@n5)|qDtzk2av-OQN
zOL{BJyxuye-|=Mj%Iv;8U~tpKl&885xT=-svJJdd9Nyg<-7Au86A0A$zV37yQ0Tw$
zSebv*(>aR>GR5LQeJKKS;l}1=4Su9=NX5JTo5BvmWB1Kwgikw&?UNTVh_ernMpg|7
zy&ahq5;P#KdOMIS)EtLo=JNPFosGa>ipFgv<Um6jSYlpOm*$rTx(g0RV;uinkeADq
zjvtA?)yl2=^IL1@<v5zq?{s7lrbejscG6`3skOC`8)d$cJbHv@tSRXYMY}eoH4isW
zC0a1<udi&EUbjy5Jgt?*K?`I#n;P#W29mrCx^W)k*6InALSuQ4D(O4C|D4#;SySLp
z%_Lo5eASkL4*_pLD-L(jpzJSxzSJ%9W?@2^PXUdZNGHxL|EhMNRK=REvCw!^-)H!>
zm*cCtwAOIDrjcC?OoTj=OkelA<(pIcZeQ~@-cQpf*Y%5a31a9RpTD-xo|qyqzX0Js
zr;u`vJJs!rHXi8aJ;x2sVjvVoFpaGlsLWrNp)%%Vu`ff)0i4+QnJD7V%Q53bAR4+>
z_(-Wx;nVs*1It4QXSc398jx^%0byiGwV!s2i15}6|6fC7Eh^kc-zlHt@FNj?K|b$B
z+CkJ!;*|`gRGs1znTuqVXm1VOhM2-|lVMNY*FYzv!cF3ZjJOPM(Rad-`X@>fV!@yF
z{tOeK7nZUQWKFE!vM*%y?0hy_$o@>z?=O=s`j*6%$6cwFN@uK7)+6_hwn~mIO^%fc
zXL5L0dt>oa7SMFft$S?B2XeXwP&r!Lyrb4z6_$P|Ue>mCRa-rGzD=I4e9Z|n)=7TV
zjUWs<3o0wYHBd8po84*nh6P!8p5Y;cQaf565|B>ysH8HGjjwuXZ-os}0+!9|sw}lu
zTeg1QyQyLNi9be;{1v!*+|_5uB96_kP$7<uz(5;`w!N0lYqQ710|zDjG{pOEki9d{
z;%se@_qMKnta14m(Vf1ou!jg+Dr?8rRW9<nQ3`)`U2R9tF}@8?3X9TuTC6i>PN)7+
z<Kq#UY3;;!$h|tmyi>3auKKjUth`5e7EjI05UH)vFd&b@_!Fo<fRVdpG2~j`pybZY
zQzRyH`R<$T8<kWm59%^jYo>clxmY-$gbbImH|Tzco!6ouQxp#~3b$Q#Njb}I^_nTW
zq0rki=hqtV%;#GEX|r_Oi937T{@v-khG~WVq{FlDfsXhtoCK(M-3S%kk5y+<NvEj{
zEtMIA{asv9I_ZCU?<pybyQg;1pJ<7&YsMi<0m&v#v0U9w(2>vjVhd7P0Dfj!A5j2{
z22Vy7x7sp}vorY_%rQ)nDHvN|&*kfNl|@w0YOTU*4g^(E`(_(s1{6DRdk52{a}#UV
z!u}0PE5Nu^1$bApYaJ!8Wwq8&{2rUVvDLAOB^4yM#sbO%9ABpD5+iI5mD*ryqO(my
zhXx|&_E?lm@Hs;6E{P?z?!j+&mH@wfy4Aoo2e{eiqe(k&s(Ejijh|epydOSk6(d92
zkzZ(J23jwbcXoeWs><lCU`wfqH|;4X^3JAJ4d;)c98JCMTV~?Yk3HVEF|9jIhZSjb
zZ^yg--YYh3o|v*N9crqXxL4db`^@5m$sM@$`MY&!IM5LUFhQ<6PTcE#1JgAidTib3
z@ds<6g2jzl)jc>r9l5Za3+c{t+xcE1fX(meBFz(1w$D9G{Ntu|I~n`>+&U~v7hJJk
zvd5=>7iQU2?m@8|yP&Wd%pqseuzeY(VMO`4ClkAWG&Xx$P$2OS&2+4;=+2@es%%ML
zkcLl=q;t6Wk!F*#fkDnsch+8gPb~U$O_N7IlYAykQ!Kh}0iezZLHT^LhAq7R%J)uB
znkLRN_xlgkaZ+11_q({jj|E5R9SF0;C!|2OYtU<-dplfL{V|GJBEXLD!17P-U+Tt<
zspSf-&uC#{L~!iP&eLd_kaML#>vdps3#eom4{?xRnP?)`C9Y3=?hSpg;Jin)HdlP)
z7X%Zcx>i};z|HRL3hSo6Ior>EXUKkpAxmw+w<MUCmROt*8Av;ExurD8AojG&exRjy
zpLcIL1<mZT0el0z&W!=t*MLv|sY6=+Ag*>ttg1AwKuuPBii;8V$&TgRjn<e&XX9AJ
zNU4m4B`dqudIO&gq)$6Zi?Fyi%W>g9Be<;gX;Z^L7b<dIdip4aps-G+=ONFmTg`UQ
z_@NffURokkVZFLTw~~ko=)|1oxR#@6;9+pB>VHoUBWyJx%da<cEe-pZ;2?(OJEde1
z_#N#|%W@$?U5zxCiPeV-b!GdCGY{H-bmW*&>>%i`BTCiu<)oNi?Z!ZrjKAW))BXd|
z2f5KlLkCCapUctLmlr!}_vx=X_@1_{0YezW_*x1P5GiM+H}tGEn!f|F6t+3%NwhdX
z)3XY5&lKi@{t2?Z*4uN1)Cbt*Z{&*J7L-A(i_C`-@LnalB>KxI`OmHQ+2C><lg<wV
zALPQT5kg8L0`$pUBEw2!YYh6=jSz%IqAQ%dZ>f5T#qtz9s&)h}c;}3b?f)bQaL=3O
zfCA0t_i~3sRY3GS2N18Xl8coKKd2DA^IcnXtolIEj0UpcS-^i3X#cd4#wK?G<HNV;
zE$G^X`(Vk>iRaj)#l$6z&p(5mctz<>O7qG@@C^q()zo6tNR#Yk{)Y)pi!WU;w#z7T
zUR)%QA8;a6wg}CF%9`_oxo_L9-?L>#kYiw?bSJyzwWv_*FMk%hribujzkOj!8Wbhe
zCZBM!v^X>mcK-^QEq)L_pG#mB04UX9Nd-g3=$v1n-4$Phv6OfO#s~-%5}3}d$P%df
zo2Y}amq~QO8SDzWWXb*I(C-%eTAR|m2L~H%-zA{|g301pf}?wma-MLz`NU8G(G>iu
zp6&WT_}Hsvp+kTe0GFp_hKMfx5MxvvkJb>xm^@J$|LBZ?{SQPemJJ;_{V(`M_L4l!
z-40OMqG^NEU($S4CGTG4u;T@OA-MJJaAFXKBQ5ku)1pJ5K0V*UU_wTiCu~Mc-lE53
zP_w=L#KSq*q7wVSLv(Xif`5}vvYRE%5u!3UWHuJ(9Yz!*MqAX99ZUFry9M-z8aO8%
zXBWbM1+t6Sp`;(k6nR@WULJ<!^|G|~L_HPh`*BEHH-f1ET4`o~&?0VvhXe7EdH_Qr
zPI{KT6@dwrRefcg0XPv-0h+)T1^$$JG-evaYLVBe`qfw%=6Ui063NtbsMOuA8~s5J
z%!Yny&sfvY@0tV_a(SrwV3~3?h7sH;i`}OJIA6>(<%xyD+fDiV^BgOMF)56AI~45W
zo~O!#4I@fEr3Hjcg1PE{IF-R2HSPK;FC{B3`^&47F)p>u$`KU)g+yA-v}91@HgVj5
zbB*Asi5hY-e&lQO1fh)d$a(OK?5k0pXn~umtkmi(8EkE{k}D$bqXz8KB>Dg$6yR>n
zsAiwZ7~CGa%q${RUr_92=(0Fe@w2!F!w@V<=LMuwB~KvB(>Q58+d3TdCyND_DuB!6
z09C{tv8%~fBmg@PXwWdJ<XTA8#|MlAcKzVKXq^tCYe5iMKoIVabc?@PLe;f9{da)h
zX{b<O%^SxFGE6-qrvI&E)(tSq8L)y2<0ZNtaGDTIc5w$rE7ak$4~9%hzbsKvHsA_F
zTb|#^KsKRiZjvV}BZ^Hpb`i_P@)W_9l@rDukFgEO$Rp|cXp6FEyGyU`ykZ2_=G6bU
zFH9J)mDBd;&?WcBBdC~g+oue0x;$?-)7!%6@BDi~6NO<oU$<~R8Q>pLlmrQ_7CzAD
z`6LbUgkug+eZp|2V<7YI7UUhrjpdUMRzbQ@Ggl%pPsSKuUYh4O>osXu@Bl<W-!?h;
z#h5`0SPKvj+=w`FD+>#SKK}*!G?$5LnK`;>Q#gSc+}@z|&_3+&<0GR)mYK2<NomrP
z_}xMCvK9zaRmUrP3pg~vL91K*X?ezJiuC{@y5@WntO{=rAWf#%RW_UsjrQ+d!j{~b
z`6Vx7tED;=bUncxj`&c{BU#lt)}}6?3>_<37LAqO9{Ov&TV~mW3trTinaW?aS&knr
z&_j3`qo1UgZyesUmrnmdrbrF<&8tqq`4}q82K)^E<7)=?S&+?@PUjUIRI@0k4j8X(
z3x(>J@-Pl+78A&#F%G&Tl7>elqeEHGjaziGtX^oQx|gAIiR!7$-@q_4Cr<rr-quIJ
z!Tj&1dasg%WQ_~TY;A*zGE{Sh{^t(I)^*kHdGv$J;!=&?OocWj@JavnV2i;PNLW<t
zE!S4fMabu>i=aSn-P{l;%Op1O9DtluK~~B8jM%8{uvV`~%@G)}s<S}`77()b(u0K*
z2n)|uE;<2lq&s_i`a@8>2UsSJ?n}&}u?__p!Tx6M%yehUSc+sVoPO8n%&cx3rBR)f
zj<@MxwK)qO1}oKxZg6{dFR;<0*Qxcm|9yt0eVOP3-AAL%W(IFOQLBXhlD)$-X%N)j
z$|hht7@T7P;n!oxL`WeLRHjF4x`=j{IgdMu75gvyFKq4vj`V3lOu#$bF)g&diQyqm
zGcWQO0uAUkkUVVCt$w6da0&Bw4*v4rD&~K*Ck#Rq=m(R{D=lBSA7=BRB?wMfl(~mc
zPKxJILOqiN-;Ogjkt+N7^oI=W)vZ*QD36XnB0I8DVEM!A6%{(#fwraknzdnr>3N|0
zZXC|AjOGXqqUU?fwXm$R`wU$mr6~NcqkcJg=Ki_IddGUYE^;h=e)@gqxErU<+ucI8
zt^bbN35^}quqP1skP?<J1-VMvk>}a|HZDge`3yGqOv!+J?mxd0^rq$H&wAxDdNF5Z
zoSi&&YY!-D{{wAr5-MRSJqZ;So?|`j_;HClt#z9S!z)1~%Y(^|DX~#dVMxB$#YEW(
zGn9Cxe=uRuWnmX^N~Oni8(=JEj8tNKg!(W6M3T<;)`lmc<{1%4$^VhF$)AT7p2`e7
zTEy1ioPKR;&wwIlg<^Yj0<eO9A-j2B9+ee9oipEHf>Y%q)Tcbsshjj{FN<2Ux9nM=
z3f_OQdz&vow?XfZ09myv*)w7fqI<3GLm8?TT2X+}fUMIRuz}TrJs_&XM5>2b^tul9
z(ew(jP4WkYZE$wZ<%{1wA~f|eNRGnlvyjzAZT$3)rYZ=~*!CT!k+w+)@{GGtDxxyg
zCHFG83LyXoL8Sg%<8s=chhs2A(sQot>dHQj@Sf4cyE%mZF;>RjD68jVL2-wqFLt~N
z6y|mb19pZtn>z1>M_l8FLup2y6df+iAOz{8hg5~`6r`}G_*?4nm#o(K(#UhS7RD~S
zXIw2t!t(>~JzQ_!=E!&IiWvck<TG^=qSV}JDyAy+2_|87SWp>A*A)#_3qvGYgup__
zL$S4YrngoB=E9wWMLF6=nqXjeqXZLTD#OQ^I0L`-$7q{EI~lK!Bo0`_H$x@H)pkZO
zIHZdzhDc*2d#?$sZW@-wl#c$oAO4Ew93f};&i3ELAf*LX1CjJzZ3^qlze0y{@6c4v
zgNZA!&Y@kH6h`%7m?sSZdRl<BTs}&Dn6KBWzW8%vJiiV8(7d6+S=3A+ep=%v7T4Ln
z=AZmC>qlm*Wv6~>J@p|Sg^qH$(cm=HNpMJ>YrViH_B_7Zk`#6zF5<7HW!_b^M+RrM
z95u6y`gt(8`ds`=OKelm3K|aUcDR|;H1g`<W*qug!H}}|fSg<%|3PB|pUp-OTnQ57
zVqUNn$X_?Cba;PVSQ~#C?Hr~OS4XnKCZ@tbl;+W-K4tGCo9sZe_Kx?+UcB09Z|BU?
z!J$hF6oI!eqbOACh)&meCuvo8|Ea9kuYhf0LcWVfB2f4-VFkkw;fGlTmYuH6Go(d?
zMYm|_&O+<S6ny7X<(U@RpG!RA-><|g*atW_ElX<2&OMgiIk?a;p$|J67;^W%OIRIM
zah*cxuN!Vx)c<UAlq<=<rFi)DaRW|GaP2lSq&0^h?JgQD*wTt3#x#VRM#JtRl4X_%
z^30xjkx1hgtCnK-W3u1Y*`r1o_80dJM-BMHy(077!rzTlJV|9|dN~P3@4R~y(3u@&
znY$1MZqdnOouL{r`Kq@e3$%Dqa4d$iFAJst-Zm$D34IVLdC4V!VnokxxYZwjaPx7t
z-*OX;X)PY^M;`C$=Dv}PS<d-a|CF9LCm*4YeyGVojnsAj*a}@&E<D(t+17QJE|E`r
z?=?ktZ=7VjZ(XgidVZ@*AD>#w7+vpF3$9FUiLrP}@}H1UZ~000UZB*i*K4YdUt|+v
znIuvxoTK{DFBPnI6j>C_g&lHJGbzd*|A1oj_|Ehn(4{HZUrVNbZWCIZ<)~x7l)Lv-
zXjIgRoMQf?px4DMP-Y?h8u>g^yk8bCT02^%$9LZ|<L<-Zz;YUBo5)$RFFGL;Hi++S
z@<(gn)%SnvK>giy^Ya+DoapU0xi1vG{k%2h+Yz+#L&bvWo8VnAb;aoDqvZ<?Z-+g3
zhGYqY_DS)sDp%C%WFcqmdMMj4X^to&)9WQVajN)l>L2w({Vz>)uz#pO6O}oSK4l?>
zAsI*P*qxL&jj<f)YEPa##XZG~X(ICarS&kTV#@N=9WqDsH2Iwb8oxOp<v+0hrGcaz
zfQKA3Qw;qbg)Q~}OZ+1?6vd|%w#g3e`IvhEz1ajnak}+C9`_z$r~S9mO{4wDPnKq)
zO<gNr@arOa$$ZB>C05gH-4~88!<WChL=Yv4nlFjHwUim}x9X!$>BaH_ID^SZAiD{B
zvjp2vnNpNou9wd3YH>SFo4ve}^T5=ZnDtl)#M<9Ve^vkE$rY0hL@E*lMkv~-oYHZQ
zVmxfK;4-~VkB}TYtmRhiFQ97gqDI&BWuly<JYd6q6WuplOMFG=x*$*&{;<=QGTQLA
z)ves@YOb{}dptQf(_g3_u~pXCu!H+Q6p5{E)vI(gr?cNgRJ(>E<!YI+7So~YOD{vs
z@y55}NjA2NWN$IJ=9Gpzp~A5Y-^Wu=)QA0gDfA%<-^6;`_yQlHsch?IouQ?TiKgeo
z=#2+wkKwrKZ7I>9`QxYswCI&-tKbgdS#sqcTOk<mov@=LfepB%4fv?tM<(pV*cD}M
zaU&iYMwF<=WXmQ;okP6H{spSE!q|b!`-`lZ!!r#-d(!3J#b9+HLE2;2`1AxF!h~$Y
z@M0%Dzw_4RA<9^$nP7Zr5rcEDF~`)+ph?t3@MxE+2KK|6z-V(8YvwQw5%7U6$R%~y
z_RLwVeE|P?bLN}*Ua-EX%Y>p$H(~)+F^uDa2MC-!IwpV(=~FK4M;#(^{8rl2d#m8b
zQCg&(MzQR|<F|ib_EWMFmUR9I`j3LPefFY1GJ>W9ck<|W9J?&x_;oI!T)!0}68>&j
z;P3W|KlQIm3Qg0ya9zIf*tJWDsSydQup-Yt-Ju;sM9@w%hi=Lf^Mriekl?z=vUZS*
zkqd|O69|xngV+42evLTQ9f>=EEoSbijo<%G&o!;=w=ONBtpA%ymhDit?pqMR04Xp)
z8D2GKSFUC}^QZV=l2}Eo6e6uuyv{`(m{cl}0;KW{Sy)7bR|wXPn_T{gh(Evf7<1aU
z7!frzwJ9*%GgIZh6!V&mTtQIdJ{T%uWvH9a1L=L#3i6kzOgIluXaEy~jZxa(yxou`
znF(ybo8C*<^7&B{oe-BQ!eWM3jC(D93jK39DP<wTB+<JprwBoc@MD)&#Q4drYin?O
zzMdg(1k5?w^M6eRBOs$>DTlh5;TAFFpKPyh5Xy_N^Ot&np|E_-nk1NzbE?2kjr0YA
z0B`x2xqGNX4~k4YeN`b8E!`=>&21Hg^u;}~V2(srwsaAYk+P(%y4gQ;Va*}0y&POu
zoL8dkT###vV3EN*=-S78^yObYSK;-kIs5BwJE-WRAg4$lRrqO<Q-q&7jG|R64dgkR
zS;&7@DDj^amWD*+zuvoH?*6Cp7~9UE3vngjv>f70g;&D-=d<bvizB-UpkR-JYyy21
z;HO1a0e<Sx^P4oaxTRlL;EqgJ_8bw>mi|+MA~Lxb;mNw-oLrV+VZNL{2M#7sh*d?j
z^@_^=Srst1TIzb3rvTACb#ExKJ76}{2mpu`CFBUivH}n^yoBIX5Qy@8<KKSNW?BwL
zFgh5GBo{W}0nX7tDvq&dw8$Xi&1j{cAdLteXUTv?$x+&at`=mh<RA-H&PQpq`73#E
zIq+T)kFt;E7Z?L9TeE_)JaqB+w&9R2?P7qn4?-R8c(pWP2K8<cXdLw}uPnk0P2*VT
z1am!p0<^uc5&~wQu%4pMB%PD@PHCI_lmN|KV?<GY1~Be8!=Va7<|uuIGD6xKOR|Y5
zD>Tj?4jl}mY#a9O4h>A>ahls?(B<ZDVX!pH&ue>C8Lv38lqd9BnQ^@(Nt3vtZf-OG
zQ>@IWhl(}Z%OWIn7;f&8QuCjNEkXb)Xt>fe@0!1pG)yolte*N=If~#h>YdRY_&zgd
zRgD;*(2{19!4tQvE%fms0?<3tO@T!M?-=RaR!lg*lp;13BjUBjPM7MlwaOEoRy7SA
zQqbOOe|eH4sfEckcP!8oR~i~{`D)N^mfD`{E;0H>jfQ;ovrB4M*gjj#sq9bZ{Z}!Z
z9U3;G`~%aIrNa_WT>*&+ctxNk=CEKSQb;BWdkoga{`chGiHD1q6DY!(_kA4mMdD@j
zLs3f|^~Y=V`<>;}f!xzU(&qsn^iv$;V$gcc&h)pkx$luQz86(5HLeG5C&vcQ4(viH
zGP+c?E$;6xmDU8LNb$?nu5ELlNS(WV&ju78JnSt{Ma&eFK1EZqjfTs=%2Q36axFy*
zE>9dejZul!`{L=Gwz8o%eM^7NlE-Ln{HdRb^6bCL6NG%fd{>t=fQyvF6lIEiLwt9a
z)564Q#z@7H+zbhN0ft{jliukh6CZ<Yq?)g1z2#EJ63^}`y$9N)QFZ5`n6L)_wvx^@
z!Ia9~*oV3v=x%0PySaDnYeR@1u8R{($-t*V{G$mDAArrUo|>m|N>PwCPH>h9)l20p
z<eOwKj!*q<t{xOm4!@7a!wl=Ac602EU07|bj)0UZ!r*R)$5P!(6t!-q%F(TGZVZn;
z4i)B8-B%7};`~?IGMs&ED+;mY%^1{=+SMa-lBAe?m68+QVA9v-X01@65jJhe6|%7T
z->TVCZr+a3A_7ahh6le_PADzoE%xUrB)4Y*3PRH?#U?A=v#`P&5z9@&#Gn86-KFq7
z8d_nM&N`7255;d#M1q<g?Ylx2bBXO|RLvYbY-Rcnos@f3(~t;UL61@bmr^E+Q>FV1
z?b=|(DFCq=QV(d>%`Mqs=x3KO)Y}4Jp>-+I`D?1mlwSZQJ3t4Pc@Avq*f;PvDuiIl
zW|Yv4Um6#Um%_C_y>;NMXz{Gao@{4~pwr$n4LhM4eDT012fPH_&GrZ#=-rxR`zc>C
zM5Ln{^&0n5zQlv_qo%*OroOn2`k;#jQ0)?IIjMFhe0>sqF0)#X_x_>`FSy17u+rGD
zN;%JqjsG<I6F04E>=%xmm3@ib^3p-VEYFczA9edrNKRz1HBBDTvPWK9?d6u(Z*T-3
zZ?djXHNqiZ@nC&dcFHYvMiJ!LzLhJ#C<-M^#><`aNsSMBCYA)(CKIqHurKrliU)xD
z8j#FyH=R^Up`4qA$f3oXg26sB?FX2oeo6XZWHvWv(K?%JamkxQedzBWZM3G9iI<IG
ztkiLdmtnZ(0ap%A86<2%ZSXPws(*_r<uPTRVf?x!{{uv5zW_TPp*1Qsik6PU*hmR>
z6*MkDlt`p_Y`P$t1n<}?!@IxkvOk-UT~A5E@lIgg%eB}W2cV)J|5ms7_&iP9dpO9E
zSuy!!Mj_3Ju1}ti1hE2=R4l)Og?(%KR0t*lLeWOh{l=9E^toFqO3G|B@4h@1l(T4v
z=WZczmok;Nnj*)o<Ib~mQx$1kWJmH9$bZN-34t&lfhZe+$N>Z=g>bePO0r6Xg~_NL
zlak3qKEz}6>7ug9d0zj~i#I!Ar92~oY-D>`OXZxB`LijMb*8Re+$5|`5!%Yk%x7Hr
zH(<bvXza6lb}rZSJb;J0?$v^fi-h%QDk}zkn}>sjkAsfy6qSG!)+np@=DmBd7$<;A
zRyPlcI4kJ?tO3d%HIP(fE=_iwJc&Q^4oZ8e))eWb{*W$N=6BPmMA^8kX%4Izba{Za
z{)55n65nQ@9pdx!ob}!4z4{ttOSV|8`lxGWi<<YU)p&Qq<Z3A_cyd|mG3)^5R*VaC
zcRjJDbQvJ2sVI6dX-O$V?rcI*PD4nZxd|IHLy?dMutrn)5c2k0$m;97`rnG>oofD>
zTqsl9TcPqNpv2Yd`XULiHf{Y=MQJb|czjXou53=|?3iL&A4_F77^T!S|9+9}&gb{(
z@!s&TfB4e06kj%ma7U-@Knk-u)$H|WEwVk%^e!@tW~AVyuk_(gf8p@d66!lJ@8Dr3
z&peA?{<psyyMJ!=H!fYFX|vY1OpNm<)qQ;iuxl9moovrWeTLjD-4<sMgs8vhJL83i
z`J5FN#}}abRWwvQjh~K7Vr?(2%TceoSq`ed3Ontz^CdLp<K5HoPZG~8Lle6%!*gRZ
z{vNC$l-cSe&Hvqw>|2PZXAd(}n4H?iT=ry!rTyZdc5_o7FwsB$PHJ9GT3(A(yqpt{
z1<QIVPe}#KrBlT6=3Q;^u+82TkLS1pdxY(;1d#?N{w$v4>>kbxx5wBg-_v<&@$yw9
z3jMbU2;<+wO*168f!o2NteG-mRSWM+P0G)oTf};zZ-wzMBnn^;nkp9H&9eIgn)|@4
zz`mNLD|hGucxZeVs07)l`1NvkyZ4!iv&0cT`r=@hLMXgI%A*MFw|--XMm76FXo+nw
zIC5rJ&L_nuPc80(?*CVfst!Na=Qq={<w~1QUuwbpK{%RJPN6Kj0%AN<wM2CL9mz<I
z1A0WXfr>|W{con2KGvL(w5`aonJSLK9kXBZkquwGXF-_9*KS&@9u>*3S#LtveSuah
zM(q#UPVDHM;AaBfkEH936?<m#c4@ZvLoS`|3WWnK?)87wszvZcjLiODU#Hg18lw*z
z{$D*0AC6wLm){>pX+^huT-bBwO%~ljYvS?F<))sfzW&(<nMYF(3#X@se4d$N;&(P3
z*faSvTW<ghSAs9N_vWZE`K1M7y2k6H`&S7DRjy3g+b)m0HrWmm1)BK~`Cp7ZamQ^M
z`IW8ue*3!g$jtw%I1uJP7`KAbl%A+5-WHpxsn(gA^7KkI<gK*}zVm%#3<7rhD+#}v
z>Z#R&CCg}Gde+2UUEqAyz9u(yI@$Ce!K%}bV6{P1Lnh%h;KGUho4u+)s||gpvj>^u
z-?1;26I?C0`hd&28Fx1W<Em&Fc~vLCwEmZ1&T96*Lt!TQe_ZbvabP~Md5wL@tam}t
zxBgicPayeE|E*{J#z7DGMEK_b?9*Rm<WJ@+n;C>(Y-NR^Dz;HcqH1v&z6ovHtTQ{t
z<ZvJ&F2$abK(?iz@~6=!H}(eOVdK+MlH7fP8N!9f|Hs$0;P%vm(;s)}R&>c&?9-Uw
z`{U=w3(P0jLQvpSL1!D{iK6%2_{;dRwT@7h&rUp<Jmrc=hM-KjGdr%gRvon8c<GJS
zw=@D0><`x741S?z9O%MOngw$t`IP-wz!7_|_pjNI)cAuEy#Hu5!LuSciC5?z{ODL0
zx+Tr|x-#YW*I1#|9!5^D#n~<cX*KshJ>a$z69K#8wwcLZnjX%h+^g&SIPA9xF#ihB
zDyxt$f5X#0xjLGN%p^QwJd}-XI}E3ISWSx&sr_87{&iF_JReGY{MU}NmqBQCT__6H
zJPY9{1HiTz((K+G07#^#68gL4p--WG)c(3}xxfkR@8<ks_tIkqeLm&>P)FjQm@}fY
zcVPZ_N#U?GQiPOVWni4?wm{<H_sNiVPbei29c_#-Y+#mj$@ccvmh4L#sk}u@+uz2g
z+qcXy0Gq+D%U#oH=V6Bl3ot2HjQb%Ha{oglO1NpNFN!svQ~)?2^(nCDjjHi~v+1nW
zvYQuvGX6hIg2@o=_kS^ooIh)=Uz@~xyK`kpjP%1Yelcjf|8FTGnF<Dj_tL_>9u}+S
zNd$IO_2fq(c%vmxbT6G){0%*^*6<_aJ3c=TuLlxj<VFrbEcw0>t9D#^M!OG5L2mcw
zz~5TOha9O>09GML6GF-w;0$T4N}h!#bEoFoy?+%+gOTs}tNe#eY#&+1sx8=j(zdmP
z2-J$-QELEawq=U(N3AF^-s3d<2U5iUKnk$`g%l0{Z%BdgzmNiO3}X1dlmhpED8=l5
zD23=_-j5T!062H}-G7M>{})qS{P`bDal?x(ySe2R;;MSdL;ZV-TuS@uCpDKHkeBw#
z&X%G|*H*5UJ-pWIN?p@(TB@x7Rabufa0!HuRD7Ee{f$7GSZ^CnoIF&yyy-l2W7p@*
z6^LUv_Car3VMOuI%hun1T0JDa&Rz|+(%lLklMq<vsv=)^U`T{`asodCYB-L1!?4BN
z^7UjZelh#f6uH?m*=(D$9FV7iM!<R}i1Oco$!E*cU)INKewe?FJQZk05QzZw?!Uqo
z6=3N_eb^jA^fQSX5bXY*AB9l)`k#QQdbjaW1$YRi{wJyWe?Rpz8)`ebsf~P-eL+pW
zIHc0sYf1ksUa+}Gp)?&?zN5K`M#5MZB%dTk`KicoM`1~mtces$mWbB9R`^`2)A9M6
z7fC2NUADrjOZOXts<BAe<%^YpQ1G?-`uASFnSu`Xf>U=yp9o=lTxx&ul8P1{!G>r>
zXycVV<y>MgJ)yiIdEMVCvZMmCiOi@D0A64T%`aDPR=w$X&q8S{>rT@!QkG>j3alvg
zU)P&rbC(^-M<LW}@mcZuI{{d?#k}cr(?sZno;aivj0?RR{zVOqa7!fv0uM|t&)Tei
zVXx@#Dz=IyEK;)0nm1u%uy&#<V~>B*Hfuj9s^U$oxW6;F*EZ9hg`968(o>W&%Mbjn
zvUKlk;%!VV^E?aq_|;2#_G!<qTu9&f*A}e*uttN85hH<?7_%l_{MZA;JZE{;R7!BI
z)+fs2JVVZbIugiM$IyrDlx#q0G<wr^PLQ{1{M=+qozv=!9vVweC(mm2{PzjqgQ4y2
z>N8F9vAxqiZ++xg&3<oNU88sgV<mY{?S=iq>p<oWD@o?AcYbUEl)-9)id$jftL+G|
zMUcr&8_3)PV(sEXP%@<>xv=dUsqVrzWnP;IKN5^giN0`XIn66xCF-SkvCG-Ki#6@h
z8)4BHGetZ>@F1s<?f>aOL=1`echNZFn(}-K<3nE|d+?FqF?1Vf(Xyw50edq^OQB@K
z4DcO?p1fhmfP5k&f?GGat&!Az*JD2A)E;9ao0i#!38}F(RRfG7j8qq;zZ;L<wb?TW
z*vG~TsMn#CJ&Bgng;0mTqBEVOf8y=9Lf;{pxh2I%z3b<pBY9`UCRr10QorBg7M46l
zAU3LWX3tE84LmNCg;iMap#ANLFScj+#GN@)_!!npH`(VY_7O#+wr5s3JjFCJzjCkJ
zUdgsGO<#c{KK~l@W|Aq%GUghQKq_T6^%Wv_;(lkREOwjW|AIIcVD|6T^igZ=4`x8B
zd^{?HXQFm4oq7=(-ke&Uepb(K)!sS_W5&TmFzT|G3l|{dA_JBqzFu8dzVR77T<Fa7
zwxze<TzYhR7v-oB3u|W*a9MALpqq(ue@8sX*t!B^!;thUn0RCWoDaWb0Cf!Bf2w+<
zjOtYdb5ywB<w8Ln)EgBm)v0IFsQCwlnUXp`;$P-ia}7E>w>Z48L>{niLDGn&oA>tQ
zaK8{qZ63&dKU>qgOIkkyMX+SmU6AfnW)exX0Qh>@H<8Yvv$^=a65N&s$7AuROQpZv
zrB0s}9AxyxrXm0{y)F%W6>T(JJbeBp{+>F}F-)0?F^>&od{M9yWokn0;YeT1=5K|R
zW)&7<tv5!U%;s&$McOg;H<b2Lc4SYQefJf0FYk{(E;h=&9ePSs<Mp7V#hu5Nx=YMM
zIOiy;0&pMz<t0Kni)R_Y6udaXU;Q==rKzi|PGZ*kPrH0rYDBlCx+JpLlk$)OzD-_4
z*Im}yUO4$J95A&zVbJ5fp@R!|=<eT<$RhDo;+vYah2j(Y)tH*6S0tts`_Cp#FJc97
z!aRQhKiY9ND=D5wA`6~o`ExG_-bpQDYGWZSj{F{vaTZvD1wi5vi*BsNhVEVoXMs!@
zSqc6>>fS1-jxBokMFJ$aySqbhC&As_-Q8V+y9IX$5Mbf%!QI{6T^259W$%6eb#9%y
zRrl@IeVNrgyJuI|dRYCNV|?QqQ5m;2wU3?BoLg76v-DZ=PZV64b$217jyucxBRM^S
zYcfvF>3alm<(Jf^dwe1K?ySR%=2y$Uq{%Q>c!#$u4_1j#8+wW)7*EbcMLTqtl*?s0
zecLmw+0VBn6zOZCyn8mL0Ee+k?kAX+Uq;OE1yI!|Nd5i3@xK!#R6tSV5;GH`CNkxu
zk^2^}uVi=&SQ$S3SxGM31iq?=r~^IA$2Z%Sgg?Bss?i|+E2?n*ROUqgrp1@E-b}#j
zmBy5Vz;W#V&3VGdjXk%g$`T!L5H-CXXE6uq*w91M%rurLwwKP`V5wwv=(B<QV%}>+
z=(HqQFXXD~wL36vql_i~X&zpZ$lf%bZ`uih!UKPN1Qr=n@!tvx$-fm8l@9{k{8eJ=
z_bHut&1RNIUz{u+ENgV;iwe5je94g0cuO|LCZ$9F5c-;b(AGA7aL3%LZ_sM!jD3;W
zWMba@7f~cH*_UWF1S6wOQF?1F5`XhP+&3n=FiC49B*P5;O_o@+NVyXwi_+U2YlCVg
zwm~%$%&>b-y}sWgPA1X}&L?uslBP*xQ!W72!9UFcRU_=-|ERH0PjG-da8Xm`>Eu?9
z{O;Iun9!%QtF^KQc0GzZCbrNX?;l^DTu=v~;y&VPhO|Yx`^c}B7Q-F4l~C@ZQvax#
za72igeab*>3SqIRoj_qn*Gz^HLok{3!1UFQCfw8&sSiIkyyN%t@VX*xJYI+sOG1_}
zkNX!<^lI`CU;_S@N=Q(+T*FTXE{Ba+U*CmW&zGcQj9;id@EV+crpG3_eOF;WSb;E0
zW!Dm|yRKVXK!s=_>@PQfvT#cmBdybdH4`Umw56^{-2cCEN=$LtQY{V7gQY8{I^sHu
z7C-+;SFBe5kjFS5_Vz(0Z1wZ42QCAYSTr;gU$j{{qw^R|PyA-V@lS4JQc8lPKK!x(
zVdbkg6~|MBpNa$4Y&X`sy^K`X3@!_Tm7({W2YprkOXelBgOS;Cl6UP+Rm!fXXYseM
zrFK>G_n(wJ$Rzsh=#HS~R`SrIT3=PYZGgD483l3XFZFs6*^+soTV3a(Z?sncAT)!&
zr<Ood3fI}H*yLry{Dot?2`76+Cy|^7zMRJpnwEftl_VRmT+V~J^zI^zPYI`mYiKAa
zn(yy`E+xho9G^f<be*zRVw&v2_v<8uvk*w4`tY5vv(Cdux6E#BE~X`91ts3nmY3nd
zb2}*oPjI=xbL=w4F!O%qXBFLA#oO|4zr6<w{!%-6V7);)1menZUbYFC+mxJOnA?t$
zrJ(tvXEL3i?xr20rJB#CgorPUMob%U%R3{tp}|7rZ@Q@3s}yeBb>7OGNUu{pc%P8x
zF%$8<IH>D5uXaUEv+A02eM9N1j+_nFqOebM#sx7slF$t?xhPtqQ6D3kaIHtwj1@|Z
z0}PYy#9w4%RIysVR5TBTqu2K<;AJjAY5Np(&XMYa#9*g)+IgEz$Z!&PwCxD=A*j08
zP3Oe@z$mSS;n$)+fcvMgVz<m;yZfUda`yB?V&9=X25S_<T)>$l{PJQQ>aIka4?{`5
z-8D+6r%fKkF??kNu{F|RzxSwZ0*zzH7x_3LBGSccTS$(ej>ug?@Y2s~Uqy$OVfppD
z>^u}yJ7h|R^<^;es3AM$uoa-$p;RmFI>XID@467eHoM)z;VOWWXq-qpIzs-SNyp)W
z&>o!CtP0WR_X${rNX%C6jcwIJ`9Ka%MvRue%n73Ynd?cB=I$sa%_OQe$1mTWcji>B
zQ|Qd*s+-M)7fO};wayt<#nV?zjb%a|G?>M{Hat<#*v(FY-5zAUvy~A)$WFqXj93{F
zWGy7K*mv=Dm!UJ_0E>*xSr*XPLWx@yo9RuN$T-JCmEoSBZg12u&RNrNjj4lHZd(~~
zFnSZ(88OeXDROH}`_e+0hqj41t;d_c3Y6KhObC<Y6U4{l#>Y&6Sn5`b?^E;GH%tf{
zZe~a5K3S1uV^wV4{E~bE%7D4q`)uCQG>l*R@r7Vj%}c#B5~=QPO0xEkUVmpLU`s;(
zgP3tlH7!%v<{{G+^B$SA0_S)@w=SzwC!aD)?e**265vyWu)w<8pSIy=eV)@VR3xkB
zj-nmYD3Yd=-9}gw9G7EPa%*p!Q?oX=Y(Ot|cW=3(_lZy6ve1uQ;71DYOyBJv_n_)>
z@B35ndEeil|H1Qt^PRwgGs{b2r^X4&RkD=AD%%+oUDF_e`pJT*1Nv4EG)!F^^XYb|
z*DC!M*Kq%vuIjtzGrSJdh@vaa+OXhtb@_B7=!Cc2lIdVZqTM_Cdp51=9?x6sT)tSf
zhh<t#^(mu+uenSpOO@i%)yl=C-CjN>SP1HD_8*~?woYVpX>$f+6(FW&EtDQ`wK~R3
zQcrbKKmDhu<$<07d+KU{3@4IYEQCNfVp)``&9y$Q&TG+aEC5v=X(T4AUZI7xzOAps
zE)H4*Nw=#YU8r`?SNo=3AV2WQyx$^Q&&MJk95Jsr0tpMtyn>D8%+B`kb?-r)o%LTN
zP6M~#NjVMUZg`}cAWxI%a*5UNhge!5poC=NOsc<HS-D=$RDH(?!i_p1@seFfqA$$i
zZp$Wmh!FN+AfKBO!d+WpnCvb~NmF?OKZhSWj4a(yqEp~z&nBLukHRh1w>wH&+-1_T
zL?kyEuWo=EqT~Q$5jOc0qn9bBF}<{0{>!(x!SI{K19bQ=oKX26e_WpHVMt53$0MUm
zf^^b(nA6QN7i4!Ly@ny<%h>)4Se<Ekt}1zsN_lEWciQE*`#{I|^O{rcbvbjr1FbIz
z@WR&0TG`-*2VdF9=h!k3y8WryL>Ap5K10@s&G;Y>%yxMh;F*RQ@KpWqC52E}cLGXB
z7L-T3D7(}*zdRfiN61S0boRy{f#<F+e;u}0D_tRLB}9$g8W-Cu+9<4Fs`=oKlEViJ
zY%%_TI`6cdffgA$hBH(^7C+Sr&Z)wP&r0fM4#?a)dp0v%RuERF=h0`V8m&Bg1C`x2
z=oXR`$P14nqeKfZ^J_3`cjv%2R=f<iai065evSmy=ZV(C=cJY&fip~+%}D~3N6uag
zClbtbEMw*1tABc5Ob?^*xmH1zwKbY+S@gDU2Ruehi~VmRYY1zoC>@k2H}<K!e?``n
zkZ>VjqKSb;8oCOS%y)c?Ncpg2SC9Ud%*@^-?WYB$U?DO2=ZeT9AenW&btpJ%0slkB
z;}uj*7$&+@-}-+lYjAp6P?5uZI3^<aLGf>Mp1Ha_e+2}AvrI%1fgL!u)w<6DcXwc!
zpIfgAOLP<EZZ0ivE^%H`V;~2!04ZDsi#2u{fyCtB!~N5zC~z}48h^|V{UfuE3L*4~
ztO}nFYoM*E$Ft}-^t3r+Kt;8HX$2&K{lS@Y4^#LG%v&T>__VqLaB;QBIT7BZl9Q-n
z-;`7*Dux_46m)@e*ir5cuKY6yat3r+Y%}zSuD?YQ&+K^&{eJTqWRw{#_+^|9TV_10
zvlq-EKQ-kam32?`R-SNNhhg}fq<G*r@W~LlA`CNX3m)}8q;30kAa{Bs1vVCX+fUEj
zdL?Ru<$l7@$__%M*MP-QiBA|IcDclpB}HNRaC_G%TutWx&noMt54ezkG=62yK(%g)
z7RF9?;R$ExQwd~<qL*#3fsrr1i&86>(9p<G2e`8TuXWbWXt{Saq-w~aiSj&TZ)+i;
z9|4NSF(IEQo4a`q?`EZZIRBKoXaexLzE~vB<y`*E_XKSgAUPiLhyF;nq%hnsQ*-~R
zQqMgCTi6NlLcosBQS_36sJnEKyfF`*o@x5#6vdi><Zs$Sd9I|@M_L?%%E1QIsYx=b
zu}%K9W{D(tset7Kh`C+61ClrpPbg*v7d<7?_t@559!BK0b2M~D-4y5qa7x(J!6^4N
zFpiVbA#cJ&K=PA%^@m05wa@q{Lz1Yf`^!6naUv&!)j>=NeJHf6ja7>PP}do{G*}rY
z1abr7sa3V8RXk2>1EID}dR_r%pobmQ2~1@P&~(DGWoz{!hj%Y={ju}PqpSNtOT!~F
zm>DX(s}jYc*5l%myF`4LFaKo_Q~EkR^he((knrR{2B*)o<*lris;CySuvSU0+CDvB
z;M)@#Wf}XTS((GwPCMQaGh2otdNC*f*4j_TrMPw){2+{O7vfZDsvxF%KEjUhv!3}{
zv4FgX2CPG!{0WRusKt5{UYa%g3;ae_r6$i0*S9_1I%{Y<pn0*K!?v;4F&Z*!2#e;9
zrKsF!CxRV*+Kj~%`ba=28u5J1+Q11728#hBwlziQ2%7Addz5M}hs9h~p9DHi6M-=S
z$M3O^oO484zsh*@#_+xg-U;RZS@6knj)2m@juw3UHU1C~aR)}tgY5=a6(F4tB{#DM
zxBAJ+yA!ThX{$J1QSSOas-lF5yYZgeJU7{sgB8O%6t{@=Xl9D&#KH-4gU7&*tnX?-
z3J?}EGum+qEX&av`xE-^KHFq~ok!{Zt&#O*LV!PTdWu0%8SFqA$y~;-{u<%84>AtA
zqj2teK9ce`_b|kn&rvBbU|p>@ks?kyRABVvHD)?_W3m+@?m8U6^uRbP8n$w{uOmT*
zXQ!GqllpCXM$BNr$RGP0Uo`}w%Nc${ZCO$apw?ukb3Z+6HW@6Cl!IIbsWbRrnXMl&
z_3#kQiHl3ZzOS%lqT+qc1_(wHl@u-DhHH-ZH<hw0JYqkhiTsMqh|p_M`wfhuKhlIQ
z%h9`*rrc~T?oENkyz&^bExBX8C&XT@FaHF!6!#cY7-&GP-Ou+eTgya&Lv^aTo#xK?
zmPIk?m<v5-_}8oIG|wB`ryT@EeXzL4>XF6Kj0FEv>m19uNHYCP466w~!=!QIbwf~t
zgl>V~#g!p&n*qeuDp%}zyKdg3q6U#3K}M`*-@NEgLZkllNC$&^d~0?6|Ci1>-gl89
za;Y43Q7@hObXjH)N_NC^k(jZ{J^;Ie@EP|e*T-yO)pFWrw39y5&1}**oMC414lj#8
z!l1{!p^@t$4_xjp2#nv5CEr5i2c;ev<@CY@&g6P{M$8}Wt^q`HL`v4rq0N3l+)+JP
zn%Ga!wsC#ey|Cb%f6#i#U)2j13`)oR@rWHm)zSbXk9ApHpR+Zh>1Ndy@4YWFzhk8c
z44LM6BvK8DmeRojY5iXZ+3P5jLV{Z3yOyd~imT<P2EmbCIcYEgP<t!)R(qCYZ<6<|
zsH2(E;c`~D$G-l_;{StD>Ob4cGQ}3sb%vNG2P*nIkgnrBJY3E#X-RES$I6}^tJ+)y
z<)t}z7&xmGGAsPK8HY5olErR<<Uf(Kd&kSsRDN<nXr>45kmoYnUb4)B`8V^whh3Ud
z{jSTQiq07`GkeD27nMl-QP}wU#lbv8%3Nj=E-W<1a>_Xf8EZ=SJQ0CcibP5Piwj43
zIq$a~^?n;OWn)a{D%YlIj!m)k0Q6@r^=bk=l8bQZ`6;S1wCL2pl|`UK;*Ro}@G;Fy
z1OmF2p@k-EwT>1fT^No(CMRomFlBzIo?KRFo_>#AT*oUL+jrdqf?i^%JMhND&izP0
zYG$j&c=5e<45>utrrD*9*0vf+JNCD6wG#v};U%F-9zGI)l*;)p15>a}C_wR_1_Qz!
zE0XJxzeZJ$?)~b&#h%2cn7z)&L1Jr%E`tA$#Ma=tP7!Dh%6wO-i(lPp`0N*<I4AT>
z=)``tzahQ}S2;A^bnd&QhlQi~N$*3>vbLBGsE$5ENto~C(F9bs!opU-6^Irfu`#w&
zYj2wAtN#uG@@A!%iZ&L-8C;$zMF;K6bbd{cK~jJJT$#jha`)XCZ4j)WQ-*e+wecYD
zd(S%h05ZU8;&S<ix>;y?Ehd(`LD)S8FidXek>kU}5WPNnDZa>lQ7XgRUy*CBLufSX
zdhZ@$-S9F*Dvb{Gsih~z!n|gun);&AE5LtRMdrOcNW>9mc*I=o(r>01C$0GopM7@)
zkeIq-_rhVf;x@pjDmP^Ot)oJ<+bs=i3i*l9z3PuwraaN(j1(RiLBhM`3E?U1b81V5
z99^A^#?cRG4SA${wwT)XIgBj!wNSHBX*4yX6$GqT;vQvRhayek+V|kWKacgM*Ie;p
z<PzSnWhkFEEVX$499x(`^|cN&h-#o&Vv{pqA<77<)1PwpQVg{s+4v@SXD(bXH#YNT
zYva<V1c)J6nNsFyv_z)qKTtMkc#^3ab}8YQ8I$i2kqP95!$`t0hWlXxAT!c*1$#A!
zvFWF*JUQvS*n{qT%RJITdU7d7{d-h-g?jrB%}SH%Gd?G~^5L&bMMF8_Yb?c92_$Mg
zl_7fdV7Xzt(*jPh+l<!3Kkf=4IaoC0Qo0vxCHvU%o1wL#gu7i_=Ljgh4^9{eP#Ten
z@x+oW{BGA1_v`A~?2>+Sanp?mq-3zxxr&>e%8hkmW$gsM+QilfFMMrbqT@3m;KlF7
z`izN2F0j>_HQqI^%eA}?qw86B9CtXx-im9m(4L56ZI|nVB=Wivyl4`EMk<J}$C>z>
z(XY30rtCDCbI1hAE1Z@yWwP%2%}5|qkYRX_abz=rFGmpnR(R$gXCN^~kTXy#QC+6_
zd$&O8H#=nJ2g4d_#*3g>H2uMv_pffN>Sj(j^DFa=rziLE*@acgJbH|gPjtnFRVU<g
z^!OwUxg=2ZP1oyaSCsWW_)OlfX-1(us#MQ@41}__Yq8@KmAEz&9{~qhPiIyFA^Nk_
z8sk`nZA8<*VP>pCSRM4!D9$<4!FriM5y=zN`9JB;8pa<s8e_tUFJWrGE2aK3c#+7<
zAUWPG`gG~=;#vNr%JnyYTB8-9dj96f*~$7n9Ax?pYhlhVc_^a6Kt2^(XEYIJD<d5*
z*d`yfAL*+O{<H#&`DU<@<%h@5gahGym;F{AUcOJo+`BsDM$Qb?)$S~nr&dF6qydyc
zbv@YFP@6e5{X)yvXUf$iF72U3CHy^Nu>7zgzYUZx<<V!Eqh?vhNy=J(nzdok>YJX)
z#=s1pq0gngjsahif*xNgdvTah6aOy=$w=OjsLtJE^q+H!x7?Np|3A(xL~fEXRLuY5
z+u|-OM#=Ni{~_poxw*y>`z!9FtEz{yL6uj#VOOJZm&<$k=_mbkgcX2@Zg_aFu~H*a
zWc4+c-cp1%;=yY31q+NOqCg@K4~!x{sG>Dfqmj@B(g4llDvy_Vb|hW)RZ$i3-bk&0
zWrMsW&Z>Q=_H&Ar2M5r6qiNs5@eVnEy5w-${lgQub}JE|#(&>2Z6Yx`9lONx73`C1
zx>pH~q!i-TT1gR+m&B!so+ixgM6TlHP;FdidrCRfdTyne`^MQ<A6kn&#Ny4RBI)vL
zz_gHFGWCQ6!4um}?{|rInv<_Qb1K@r%I~6QGv0SJWK$Ul2xMP8AU_<%#>$4YEYEe_
zF$5;)4t2Le%0-__431_a!i<?iS1(PtMo%hXpuJ_V(D#JxF*lfvDoN39GC8wZSO$zi
zUDt#3F%FNEt~{!Y&MQ?8Oxv%EU-PG|(#G`jSzihk;{o9`YKSc^IHmH#Y(G+hwKzXO
z4nqy99?RW*n!-fJx*aG%`S5w9kfk%LIOl^upj@yl7(T{%z!f2VSQ)7BSs#^2XAybW
zi^d(63x78-bA-ewQkeQrZqy~eeK+xM<GhAVeLJ>8B!8J*|DF7%xlFWyv246k&e>3R
zdRjhegH-W&X~8-d`2l#GoI<JJ>2ez00v-N6k87#39FtiD+*jf2X`Jg@^7UAJz{epf
z&2&Ndun0eyHySJT2-fM=whETNurkwXt>+HYQGgCzGyoS>fDO&{-1#>gc9M#VD*P%Y
z&^#Nn#(M4(or`R1m-*#Wvl6G(pZl|K1Cg9KYUC)2#c5<hzZUQn6C^WJlZkWmt)_{^
zoNteCML3WL7m4l0xtgI9ZudHa_0U&LLaD7Y$WbWv;_-xr5!!LS3|Z^$y&qysiyc_=
z?+Ej*B%ihG9DZ+m;CCT9k{qz4k7GaV*TD3Z|B72|1?xkqD6@&@-4|(^LmSHN$t)Qy
zciyLkQg=UPAR9f=+qi!T=n14c(B|0AjA43F*Md2#UvR+5o;r5J529*bcSttrZAcHR
z^=4!_Y+zW!PU*vq=xEk$-OH@vSiT=lG_So8P6foigISZ676ouSE8f0r>I~W#&`TOb
z_lDVMtbLK>2EQ4g`WUdGSR}E9q$8pmoZZyHqc2BMwyCb~u7&MpiIrSQNy>C+0Z)ld
zt#dRGHiaUML`ddPQ6pAKboj+D#Uf)E;PXHWOLmt#-F2j2#kAOm--_orh648p`4+^L
z3TfPZ?+*%I9#cgrKK_Io0u(4V9z*RGee{!EUyu_!d$%Gwl~A3#R2Pz5%d^1`z@(DH
zCxIa++C$ObT|n)*x~yf!$cClB*ta5R6|NN}XD6|{mD~a%yW4P}xRMmi9oJR5_bNJG
z8WNlQd9(!H&n9)$u9%;ebMGnd^ai=QX3Fj>@}Kz0Zhkp$#%3RFAbCIZexHfcRpVim
z3?Z>wf?a&7f>5T_5uePcu+w$JDXg%wT}**)F)i0t?`Q>jB@~OxP-$;@b;7c4=-<ve
z>15m3K9LJ00jto(YY7E*A%|j(mFI#?e-ga}f_}1f#{4tXk-TG#1Pb(zWPIQ37qQsQ
zkmoc|XVjZvUNckYcfK2Q+l*r;9RG2o0&n|OD3Mp^yVD~AaiWTf4OiJC*G7&yo$|B8
zUurHdmOc9wHXKhScpsY`BaJFSkdu>)+EIO{pPL3;$ulKgILT6u*YwazNYjM5E|~n?
zgHo3tExB`_K8kx3VmC)M{D-euV%%F_vW1)L;UzxC%}LTvm1i!Nm#w=2W4ES6N9cQ>
zvUdIQNO}?8%<Ws`Z3bH+o4Ury8k492Z@o3k$0m)_#_i)Ns}^wsqfeG^7s_w9f6h1E
z6FZu^R;0}bLv}b@AF}gj-C-&|9PhQ4N|PB^`)p6uOOEfe{K{A92O?HGZzp~C7R{$W
z*w`EvD>&EVfNd|)0<AtT_Z6X(D<(+wNPZV@E*0Q>Rk!-5$2p%jIxg!&gWklJk_as<
zLT%8q4Si4*#zb&kPCB~7?7koMs_mwN`y#Ie&Mw&(6kFCJYTJgnB(AoB3XfXWRh2C*
zQK3srx>(bh9s(ud^=_&k+^*@t9sJqp7N5E|-cvTd08=1uPB00T&VyBr`8=+=ypsqm
zeFSJ86zK1LkcsMxNb?Ol$rHoA5f}{?L!#*#rS=r)YP1|`GUGA)DDfQb$Sc>cbv&sE
z#|T$kt~W~K?S|6~5!|c=K2j!qk$;S@kx_A@462=>M@X0s@xcq(Eg61IKxnw4C;}2d
zT_6wH=-#JjPZM(yZXkuOyA{j79LmAC(xB{+?K;MuGgQSmMr+PxAn?)JO7pO%S9MNV
zKYHW-nmsGI8uF7lEF2cM!mu+?!V@-L^VE|S9<s>F&Ee*4lQ-u3?8~xiX$Wl(?-*<g
z7|YU%=6BwOr(`tF>2HHUBd9^;yjAnEj0u=;a)h2FoFH6h_vW&G-v*fZYI|X6e(}^^
zh^;-N<%A@+n=WSZ3#=h3dxKD(U^1;Pv-O?g*M~wJS0I<0>xF*(xsLhD`XZ&qEmtCd
z&GnYw;<u`v^;E@Wrk~X!!>A$FZCT9JZ3a(;!WNXlumw-EMNiERXbY&jIQRyY<;q#6
z^9N_0bUdKrXGLVkgCD;~%aNS#((_Ro+Od;YpIX#J`JPozabHSAqiF%!1y09UmDjU|
zHc_k0Ye5B)?Wr))OY-mJ9F^Zlw$IwrnBk0JSdHIYKwks&aE?v92-xY+t|4?O5xk3Z
zl^9UdLM292TNfNtZSsuWOa@fnE%Wm@ZSs}9(olNTidBq?UZW_H)OlXe6lMg6mCy?5
zbU(ktif)Z)!8jbe8ky-kZ1!@A2Dz7RBNkI)t3oA27WE=s{&ee%0+@&PZ_Zh;?<r;U
zaPdX{gYxgBSH+)nGpjiRKNCUu^0Xji$#`z=Up5vnA)v0%JySZ-XG25VL&VG)qLZ<d
z79;mAT(gU{<=u+(EnGKP?>JRN&?yeO`?@X^=~n|6Xcbb%7PRXEubTrEYc{m9ibiw+
zOPf}(@odZtBtYs1<>^Y0dS`I>c1YLn!;llo_Rf<>VZhS7N#BS8C)MTtpi>aLRj$O(
z`4Bw`mep!oxohLJf#-6)+qY`*9P6iB-F5!PF_(MDbKPnvUTQI2V}*Rh!Bwvx8qZBX
z$7ye?_iF1os=SwGjD;lpnAY&MkUZo>-n2b1bX{N(hk<{gvhCcC6%-J2=sS-8YR@J6
zuuzJ0Ieb%`mcD=Y@~iwN2dyZ&28Ur!km6ZuBwbe>7uRCZ-?fl=z{vuO^$L(M*$c3A
zbt^UAn1P1w^`o;sIKd9p>$r|e`e2;i5UEKjTXeU}Hrx$TK2x4Kb>DnAJ?C)#{h0bS
zf~v#Le5-l+(tzNWE5iuXIBHg;#(vANYXfI3QIh#}ZS*Qs7o0Mx_SxeMDzN0|bC%f(
z;biV`YeHpPU7hU*gO>ce3a_eDEC*1c>iwb#l|2tuPLK{(Tb;w{8Bx&2YVIvY^}bW;
zC%~>PgVyr>+8Z^{PP?lWXqF`M3w#QTtj=wBJsvv|zNOwxJWJnOmxX>0N@NoO3Vwhj
zOXA#2>e<7@&Mdgo<j|hKmW~%L7NX#sgmT`?l##>VJ>PDO_>A7jfkvAf4&Qi9nlW?q
z302aTS^7E4gw>bAH|gw}c|S{&SGx$LB}!>V=22js30#x)lY}96{$Mzko@2Ye9zxcU
zK$J~Xq&4s&*g}~k?<d#gzOf+Z-gQD0!#veJs0pyOtdhZxTn}nZ3|%>!9dH_00fj&y
z8tcM5lS^WuMsSKz?e4O@>W)N*4f$#L`7^FUDt*z&R1VG!-~1#>0dW<fyBiCu6>XDT
zv_D)#&(9hkIxC%r{&X{_cG?ccy}{arcm8n|ItRQx12nrj+B<D@I^65kd{s{2isT$%
z_y;W$WtGsDiL}%SBa;kIgG}`6SEuVb1>`Ljy@xlpB0k7)(jNHvVwfK5#iQOfSn}&o
zCn9Kx1O(geit$>X4b99iI*=9CpCV4agzZ`5pj+-R$-O(?BrRZdS}_flr5U|EDR;5E
zz-Bdk0IQ&VOFm9@eQs|-Jic@2PT%2cGORyzh{gEz!sX8OIW;LDQu^aMweE6J(KV$j
z%cJhgTZ>!c`xb^LW}?N%OBaO?*Ajz-Y@yrl!CjrxFT?qSNFh0L_y;u}bCpP;CWh{F
zB_TBNSld3w0(EO%CEppY=jJMzl;aSdw%SSKWP99kZ`aIIh@0c{`IpF&b-m~I#LMy&
z!-X<@dt^L&3ap<+5i5NMV2NNrwhktPeoCwbE3G?j9Y*tpi*Ok#9ltI7R2~KnP3k`f
zZLe*?0kv+wsZ{pFUHtk8nmo_E$gT)>jz&=(|I>4liOXw;t5iL;CszEdUTVbEXck$K
zuGIR--GZZ1VbyOU2T{Q3Rr~~`Q{pl>M;$HGN6C%V7!^CTDYyBW=~b}dW|~!|1-OO8
z-M64ib`0-thV@jL7UGc9LPPFx2P%dlOe>z;;19M4&+l{pbWf(cb^0|z?KRk!B1Tj0
zK1d%^FdLURCpLY2Q!~nKvEI9i9y7oMo9_Dr#4osXMq{gtL(=urh4G6OD}z)9oK@G5
zshLY^Bxq}cS@)!-PDO=Ejl_<^^CrflzLDrU{-}IPw$`(;UB(ofQF|r%l5Q#ctEDBs
zMC2Oljkt`j!EcX4P`oQPHi5ThKN>$$zIA<ths46%nlI^D#J^+W@|aTPN9N{*+YsZK
z<$^jI!JR3($F*I|!0TRI4NBDX+2L*Z>1fnqYE_j)-QD4DDy8?R#Bb*1H2|JJWsoD)
zN7W}_<%mm;lVy<q%xt}Dx(2AiU|%Mx!u;%}Do12~BB?zINc1q72M_fI4Qd1ivCg33
zh|F{zoFd{-jX)u^*<c>Lh)@7@v%li+O2i=n8I@VscGU&gJq?T^{uy%o@INZ!+gYp5
z@*}Kq=S=~$W(522M9Zc&a;LS7P*%|c#GJOUYL4+R!3#v~oz1O&&i9ROm6HDPV=9JF
zpVa~sLS17ph&8}_V!hP@4F1l5JxszP1HigHQUPH3@B*6PKZcPKFo=Klk<oo)UIPu)
z5TBg0l2C|su+OqFh|{<zK~GV;1g(HYhQI2EMIO^fx56MMmq$ZTB0fuVZQq0P#7vJL
z4OrD4l(mhw&M>5nAlMxe(T#WY+z5AK7{yEhT+f9$#{gAJg2~{PMF_;p*us9q8)F@F
zNg=x3v@F<G6RrKpeN)q%4t>ae&7_|zVUm501;Bzge<p(7rMmPK;YphiJ2M(KSUkh6
zCb#~hAyU)zX-&j*0+$(<fA`qFRgVgucK3}0HoQi|hyb;ah>ifYydql?U!U7V5-bmV
zDL$8_XgqgWoh8eT2iX1R7-<~18akdBEX%QO(rboau@=)OotniHn)Equm$(Ab%zAGm
zSRR$}ZE(4ca~0?F<x>=Ax<}I1D$VtNx4%xplcbgaFlhCd+G7PL9e(G0y&RpfGn+&E
ziF4W6Kj47pc6spW=PMf!+JuwUi%+DGAGJp48GWQRoeZi{ezyyvuFv&8_h-S&BoJL^
zp?uf5WW$bqEJA1=%L@sUrU=FxCUJab_BiHai4^=S;o?ts$$SEVShE^5O0jCSFkkr{
z?V1Eso7%E_GWl6FUv}SR?M1KfL3l)O$*_Is(4YaAy?E-J6RAc2g~Rgb7s?K-^Zie0
z_9k>(z(GF^b?tE+z%x(5XT3tK<oQ49@{AK)5hET+CIV&Gq@xAuW!svfu2*4Lv4dTF
z)y`ofI_}JuuQ<S1`j?|o>lUpkh7&8d!*RmzShzBn225_lGgf@oTt!_M+ce*f1wV@)
zk7n&>T8Vcy=DBK|RfN=fxsPeX;g%RkGBO<9r7=<ug>BGB|IEZlkKb%R{+aNVFe<i&
zrI~hOx@hZ~aUH|S9Qu`oF@$p;DMYQ`<Q-Pm0sQl?clbUm(W@4=ng<aMHH(g!0FW<6
zT$puWiZ$OH{C6eg2t3{)K(RHMiy4e4+jy7zKyKKOwmIq7b)#c`kL|}{?N&8)b63|8
zb}Ls`HT5v}{*x0x<;0zC+5EhwZZ=J)hHm!!e6o?W{ol)=8;d;*U0sW=hfYq${1P;E
zb<=%nTU&3uKv(v?7T%j%d6JrDC3Lg9qcqCP>8jlSStBMZ0Xi8x9X&aLM}P-Sf!;l+
z(oS8#MZz#?DuwL0O-T)3_9E4EP_aJ_r`P!#0x@xE)+v*}KHL_^uOE0Gb&|=}GWHV>
zyTZ7*#!KL(6G`*3ZYQ(rng(+8^nqoC*wa#~rUVJ-1(z}WM*S@EaNTS4`@_3pFg0$|
z1{A>)x5@jL^hhmK8wU19TzCfeRrM#cmKED9Jo&TdT+ovaZ9R;`u->dls*F|fp7I~^
z+N#*06g6_N3oRq=Ot95u-6oaGA_s1Y29-hj?I>v8ENTsV=D{u{&dw(1Wdi}1{7gNm
z@_vtdlU{|__Ij$#YN$_#qX)(0ld<X_t<r+3AG&1?OF>=mJr*|&W<;-pB^QZH&Pf7q
zLqzSeQDUtR_4m|HHH3{YoEYiJlZBTtB`BVzLIt7SnR!rf7^j0#?Qe7{Dd97kOv%*T
z_|=DDouzg|aM)X;McutdO}Z4zZbeO$wQW@%gS%D~lPK*^t-c3Ul}W+a@TOpJ5-S{e
zUvWo%1jNp~l0-hYwvvKc6b)s{x@6WtMzDr5=DVuiMt3_vPc>9VgR5&oix>z+8tLjM
zy|ZqN3|eO$jgh=|Zqs6aKN8C=;fAgKK*~)7@vq_psg|zK^^c_KFOIj4t;O(i@++1n
z0jTi)1;2#ov9BqqOyu!F(S_)tr9#dH9pPu8w+-KCF_7kcLf-!3B`E*Y<%H8+uAqc<
z0qhv>t{GDRc-o;?e!D@i_TZ(f6$%J%#3ee(j&)Z5E!bw;EL*bqe8d)Id#YT{{aU@*
z*APmX0W@6iuw8cp(JDa9t+JD@A#pb(2RiF};pPd*2B4Bv%L}0EzPfHUa93ve&7H?&
z3{P&h!}X;1rIVG~%#8a@;JB>)P$Y^h0`n#p)t6y^jFAAL{<N!A5!>43k{72&dJx_$
z#)r@>df;ifDArRN4;%iaqQK0qYU8ng*gw_6zF<jm{*<?AqWZd<=APyl*mn5>bj##c
zc^ysbOVVp%byz!dua5P^m#q=%Sh6fw;=HQXzl66NCdc->F!ku2d5IU*^yRz%VIZy%
zW9JCkQSUynYI4pXocL**w6wfx*XO*Jx|QwW+nywt0hjG5tiFL7!m6R)tG5<vnmr&P
z@s7(*xqJBhO#4n?n!R+z^%)VW+mN{SOE~&RwfU19J4L-er(*&Q;#$&Ym(}O_3eHS&
zQiOoctn?$;4TK1i;bzFvb(F(Jy;OKOPw;7XVelZw&s0in>4^e_>6tkBOpBDQwRKy_
ztp*24HG1h$<D0s_@mN3eMy372$|8flh8V<tNE|(I>J(AJ8v`{4SeDV3+$8trli@aB
zm{2SIC0s+n2&+*^)boGfHCI3?eg=7=%EY<>B@N~ANP;-oFixs7bFIcDOB|GqwDq3C
z8R1;=Eil`6Nn=8x%{fi;kKH}9{moqIH*TVsU_9TF4SFwGCyh9%$yiFCeCf@;&&i(d
z8eK$6l&8k!+s#ctx6=#O*a%`>Mc%gaj;d3976%7jPptM&?`MV=ENyPD9uHQB?#=%v
zWJ4d^g(y)q2j%Rt4HK3|oW;>O^AK<U4`9pv3)s5dF)9Wd4_9oRuA77m_ui-L{%_^q
z3wOIV`XiYAya*Zm{07TzL_%LfeEhaiSLMX@OZ>SFl?MD@_s?E{I4_&}a_!5(?>fBN
z{#Pf5?p6PAvS21NWrV;QQOx;fY)YJ<px|IBe<IOH?DB>;47*kCZwp6>&Xn(cl<zxx
zL{x`b5oYsxu??L4_qQc})<@`%4%l<K)tY$b_MqT@SVoher7jYY)duaI%MN`URHU0P
zGdWya;lShg`S*wP{ZRn~s|XGKwoVx+@0)H<(I37b%#L0&SGz0xi`nH{6_UnaUcX>*
zL#Tf(Q;q$kiVhhUf>{(W4vFi1e-r78efw3M%)m3_#(#)uyg@P0&Ko_rlR87Az7yg>
zyD!DYUzTZQ%AytA?O^AiMpsd)POILk>`qYCeRwbXFrn7WHxQnYdM|O<oSp`hDD+RJ
zb+8;IUSSC@ipovO{5}smEqef&q8^koRwltv-5?E6P!sjxG4hnkuB)g8(wugW+Pv0h
zO&*k=aH%$E9Kx`TOsmoEB1bu5-25(Rph*Hy5(i(76vE>b6#iV{i**j8ZSbVNbV$ZS
zkP``~ce8MM*4I9-Zr>oNTgjIblv27-C>b5BoGNxjvS&@l?V>ih-%quO>YS9-$IT^#
zm8!eGbyorw7&$gJ;AEBAIB|<4ocnuz>9F|u3(!1PP5LF`0<J>Sv;|}8=KQg-!lA4}
zNf%YAOnFH-zs^q|f^9ZW;>lSUseGsE`Mb)j+uNSKU#uTNwwb%pE{-?`QFB{^tJ=)O
zf)6EE<hxh4$=te?4QJQdd7|#zY_vTk&(SFL)eZxh?=`u9w5&$7nP9HIuD)J-r;o3w
zR*|6iTl|fl3N)oQiWvp0T7g1na$GXCM#NvHEim{y17cb!bb!cTrWN_iv=M)qHktY_
z(<=UDTE%KqDCev?R48F08ahR4Nxml35SBhD&>`>&bn{b`kZXj{y<tIy(RM|x5y@bg
z@fU2a1AJxSc;gh5M2PRHzHemI@J`B222e1b-z?s`Pov6DInC{@4>RsyhHY^EL2FZu
zMGf#D7{q7I=6^XG1ltZD|4?(Z`!Fo>$W{^vreBdY!G$FGY9T)L@`DBtaSw9ifcJ!S
zZ-6*F!q^Dvvng=mA3O)s2d#Y-%~t~#x?!6phU$scbo9iN#SO-m9VSJqrFHO*B1_oH
zOesx}_*Rx~mL_F1$i<?FWulwIS)emo8$w~t2i(>%_MNBM9uneE9891^Dj?ol66J|a
z49fPYbj3S^;k+{MQdO(p_NDrugaaN+Cv}pQ3xP5Agmpg-dlM!g7T2M)X|OD@w?Wen
z<1%9^o-u)QDyG*#M+;4QJZDxeehC`!@DGPDqEFEX>pL2h3hT47Hb)&)N7O_GvjF4R
zE0M9hHNQ`WFUgeiWp;QLc7AI#tRpu}lI2{k#u2A;C%c}ZD2d%BhdAPrI1O0FZDH9?
z3YG@Nf6vC<pnJUEcVsCy$RFLLd_1p+)J^;nQ{>;a+<0Jf+{7q@JiH%hL!#_U#?{_s
z@7IX(S|)t%9R(-^Wjnx^$D;|6rY+(`0PzALwRQ&*fv2;NRe$Imv)`zSj^3U5p;Cb-
zk87n(+6c}C3c!$!AW^B~?u|f`x;q!IUBN~PFz;Wy4p)}0CSfR*$=`!5G0u=DX**y!
zmAWfc?{z7@@RG?>UAF;VuHw0kcCIXMGD&W}Vo$72Q#53K)~eyvxp(>@c`5464Ss;P
z3@i6mL$olj<_ull8B6_R@krE^{c1ibidF7!QZW6Wq~KAqm4})l!RvO&?llwA*;+oR
z2j3X4zgP#^sKE1$RwbrORBOh%XPx*|2y_zEQj~6OJ?<o~+;Nq+2du&~Qjg*@s4l2@
zC83JJf&kOoIv=n>aJ%qhfJP%x8jgp*7!LL(pA(L3-%ONpkJFyV)FgVaz!(5u8R_go
z<Iyhd9<r7W-W4sqE&C*#ulhB;O9)E`45CyJ@>&$dhf(&7KOqJ~tBQ>n7i(j8TPtrL
z7l~aseokd)0FkBqc;$2U@^=*3+so|hLz0_?bP1Uz4KE};F29?U%D;52YZ#;Tm#(*U
zYg&2A%UOL>|6y?RNTz?NxoBxd`|sty7_O(Gt82+u+sad?Z=$BIPMHg+tZd%^J)$M2
zL9nuNV(*+yN!|R4bm8P=<n-S)ifA*Slj~>DB4Nm&`FYU0FXol6CL<9jEs@vnOFUQp
z#1Kz<F<o|4xi%iS!dHO&EJ1ttJi56E(Tq^K1-)UTw2wQRdHePlA3A{T_O0yJ#5F1V
z*~J|*4Gm5@?}S>cUP)C`oIK>n+c-|6W^7i7nN!;Hrg{21K$lJ9Oa85o=@aj$@I?gY
zQYQ8UblMwT#j}f+b#t`bkqd8ZH|ttuwRCOI#+Y#OD4og1?8mGcMyR1AAPJ(DG@~lT
zn8{Z)U><?8&i3|ngemQ;C+{a5q<!C~+-OaPCvKAU^EG_UuClL3-jh*R`$<FsPjwp>
zubJu?oyj5}Pqi&HqjkIUT^BR*^Zuz;{P$Z-LChIG70WOm*QIUb_iMl8zumyt&lV(H
z@K^9h>HxydyJbbq_HU28cP&Nq(&K*{UWr+B3-v!=liGj4CQ}ytT#%+1L4-Mb%C|4W
zyMcgybh5mvUaC-+Y}7j*k1%<g8ZRE4AJrgRx~=#!W^ViP2OGf>GD?~UNnLM>@{>#R
z0g~d~;sODU$}iasn}YQM0vQ0m%XbF#b&k=*&j{9#y00gvF`s26bO7acGyY;91^xt3
z%}+M3drWIE#lK3321THEk=8plFK)2!lKQEAq`H~msM}B~ggZUDhmXjKQOsK@vHl`>
zVxSU=f5DwFJ=0$VfA|N%Z<fe}762m8&u<&&FaII908)0~s`Im5)%%7de2*8ChIeK=
zb#|u<l5O$jT&7)<^TV<&$mL}`%hJMli!F5BZ`_p!n8{nxvMC{JO(xs4VRQeW-NNPX
z3=}h#4l?Wz9J7?xZ^|YrSe@WrcLP2H`>kUbu3KXeryCj@84;&lv9c=Le0<*y8YYT8
ze8mTkrL?tE!;add<u*G=Hgt3?Y$6xkZSq`#XMfi$h8?vpW=)jq>Md-v&o5(EJuE5c
zma$>Z7uk&y9+ZqfPZ9XowN)Tm-ds%BHnM2p*RM=7)w6kes}uQbacW!w*+5=Y$6RmE
zQ;x>w?D9!~l(aY)i^HH>YsU(o-$**Gj82y)1nbtxCae=xugh1H8x;e~Q@H5-Jhov1
z@)ac6_O1`0ea4u@nGnr8g;pC8*EIFC#Wp;2#f0}m<LV+iJLWBMv?pRl4((O0`Yf07
z{20<YOfFz?nP<JozjKrHG<<b|;LEgaN&Ethe9h*C7qW+J@e@9WUd6=J@#X@aoDVXc
zQTfij*C%TpV6miD*x-qS1OZ}6lI-y>>}>w7rOMsExrJI=n2DMNoAx`4)S6A)bDcu(
zO&rRO)qUx@SfI>xf#ag>>(0h~w*Lli_Q2sUw4|q#(Ye)!UEuOD&PsALZ^^Uov74Rt
z<>fG3+5CBP&;U$HOpfy>TaFB+{2mTYy)Rk)f_g#WPt7Ij*O)4*C$e%{lk~HBo^@<m
zIjt3DGve<pXV3k&O}AaTuje=RRjligV_YlP19tOx2siI*c*61icS3w<)65kQo9KRQ
z9&5W8p{taq&b4FT+-H^_Sf9I+a^;4)Hu(7XUSnP#yl#hu?<8$+In}SJ>^X9MBD#R4
zw-qba&*IRNW#CW#z=v4g*R@{x@|V^7&4rJ}@b^g(^<$&xB5jguo;4HfabD<AUMN=6
z#wv&^)?D_EuxTsY#^2WOS|2Lm(qXtHxv$q<%b7oU=5YAEo7GisFRL&|pFR%XFgx3y
zr*J!;z5KlHPYkcQyfDUydh82}9!`dlCMVabu&Rcj`-^NlpVtxeeq<N^n5DY(j(9$D
z>s-q^6Y{3r4cK#GfsMKIs)s#fK&UhJ&vO-6#mNY6-?cRgmFE~>WWDN~C8e{fHSz>)
zDV)Czo}KA9`sTBW1@VhN?ILQO!#>Wr2sGlxdTZM^T?p*HS}yumWUt?EEXt-8^ZIR-
zSjE-$KU!+>T6YOpFW56xG2y9SW(RWf2VVYoeycteYqJ=MrsOr^nRI#wYTgN=Wo@i<
zTt42*i;oWGf@B1Z{z8HQg5+&&9M@+a+3W0C;(Fqff7IrOcMV9kjq8a{l_|d3s;+Vy
zvWz7-j|KedLmy~?AWT}B?+1po<mebchdeu3)-qiwmg?&1c70t;mY%CtFt4St7S0Nc
z8wCPQ5oEy#Cz2O`JLXU5q@Tfi=rC4JFfzsX=&e-5zSQ_FLhu;vMdh5aG7F^fV?Q*V
zOTmAhL7Ls9W|ta{>R?_BbdHCFX2NCqhKSv+*8Yjx;0ofJeF&T^m52>GVcq|*BWMXJ
z<E3D!HE2mHxjQ>!wWEW8%P3+PwC7HczTX=H)BSpb(FxowSo8C-X(CG|z73az>aV(P
zGHa_<<&PxtBHKLDR!;*&myQG=;=KB~q$^Y|ULp?1X=)YS@Np#k@Y#B0y@^1;ka;oR
zdlb2-{`{?x{F2u;Y^*7B!9igH%5e`7FMZ%}AbWQPLA`v|#gF0e#O55yb2N{j42MsM
z^C4*RqI%w~^}%DX5*`s=u1f%<$0+ac%=Txr2=>o?uE_u4Uo|<-w|qMP0&L?ww7cy8
zN!PT(W{^fje?LDwL4{j7^Kx5C^hLn=0$E~cJN8V$dW+-o)cr!XsjbconJ97-_Y5_{
z+t&R`x;)I;(&7j}M#$cJPN<5{E88?**(E-r9ZgXF_KQm)l|^YMtsrAuGE^B8<w`H*
z_SpWkJ)0h-2=B3OlQy$#_JvTlIlYt3(p|mi^AV|!0e6)6ub`&L1u2lkKB8ev9+2!7
z1(hgpeVV%bs;zg^ffw-__i|ZBrgEsqo4UKW&gaZ%Hq0D%ip}~}PN3aaH@{XvTz^AH
zQf=g^A3YcKxWt^k`|6nh(-g1rj#q|zz5c>v7MD!?iUm)Q;jr$B*1>`S(oxEvW2=Oo
z75F!#tYgRHTHAQ>H>BLTKjuIB^<~K=DJC^j<;aWl09uaJYKAZA*yn9_dhvw(SiWd^
zNuGg4POn7}6hJ<rRX4KeH2WQ)S2XLMw<?L*Ecng&rQr~1%EG=$%T+AO{1x+I!&8x>
z?3wMI&VgZ`=S9ACNcu0pPW%V3J@Rs??fMhyQHfYB(YiSFVmO&lwWYp19oIy+(k!Bu
z!xQ70num{J<q&66l3sOM(1v;xTk`9E&IVVXvi<NnK8*$abvCgVJxZai`h!v4F}4Gh
zSY!OKKh&>S|BR|yAGK-b33c8FKIefIwB62M&~SlJX;Ct7jZ5Fgipgq!P!6(Fz3a&1
zm9|Bcu5%r^vzNh#8@-a78zG!nKA?^cO-V_5P~P_+dC?;G?k*L)@AV2C<wi5Rob}<M
z@#l8Kq#u@fIjL#+%rIf{OnwK+(vr2@N2I#%z*I~btIj7~#VYw;hziwR%atO<^*_qF
z$GrbdITxJ9KNB6?yKjLRy(IM&OvEL9Ck}_^2S_<bm0^l<oIUn(VzBYVdP1Q2R8fAI
z$p3EuySF5f)gVf@=PycE?5IRYxy~iXlL_Jn_hl9k77EKYG_daLcQbZ~=O#ihWGJV7
zY7hM2A~RDpS#G+oY=b2_Oul8j>X|QiRc5|B?(0p!?mc&B$ubrF4H@)*A-6p?r+UJd
zr}0cV9HQNtBkV=}@_(6Iy~a(Q_LgPCL-}37f<oq?YAW4#+FC-bm+krab<Ap`^-e`w
zYUGYXcodx|0n$3cE+(&BGh5Ys8oHV)O&K!HTGZ^z)~AAKhE^{!=p<~U4vd7R@THBV
z&VdGu%=PY{XSnx1R&~@Nk@c3|$W*MhjI3vpq*6zygWWSDs3f%_fdO(&^os7z#F_;c
zViok$BdFJvLpjEW)L{VPYYXLBSkwyQ>E@ccAAL@ew*cblzvngRRid&#M1myM=|tH)
zp5La6!VkR3@<rKRMT?2W*w$Ff#ppBjCd*KyrF=Bm3x>-n>TwmtYHfbwDmKxn#aPUT
z|1%VW;^boV7lCzFBIRQBRw9sVGeu(fFw&l13kVrV*|*b_L{>UUr21lL#L-AAVRi#}
z`gAo{+td>vqTgAcvEELPmb2?p)<Xn80{yV1*Ozw2VleDaH_xRuj{eHR>LI&VidmYA
zv7%Gov6#4UvOkdnWEW}cXOrBtV#L_3{R?;+JT$ju<%S@*$TwlrIPB!VHl<V*VW@lm
zDF2TewS=1-59eO$Q+~|)TsHe2`dTx)JV$H~d4&CfQct^ISvNbqXSJ>N7Cc)=;+9=t
zV_W|H5c=R-g6-d!+<$*v<+|m*p3jQi$|+ZJ9mpm!SV}DaToETXNKmhVv-0xeIZC!>
z`%n+sr)1TUt=?hP{k;V#Ct+5zF%StDxO##<%a5MPhu+Wk8Qo{e9>dtP{A1E+kiE=J
zwQnvfxSM9#Jt<rkOYCKfe2?ivOz2U*L3!Veuyo0(D?%Ki3RYHdReS+#Oi#R<<`mlM
zNM2v8Zqv`mUU&RE(=_hvkFUQV#9qodGsjYw$;Nvpkb~KWAad;FEQC%6ET$g_;pkZs
z9gPY)EMTuA=!IXyuy)Wjy}uKz)c?3P_irj#&%U-msZ7bKBgvBDWzK|Rt`wN`db8P>
z@-UGJ?bFH<d|L>p2!zMa2b$%!!$}J)zV2T>CbT#U@VJY$_Ucg*mFh~y72nb`)xx0=
zJ}G{AJv{I^Qe57&dA%DhfmFDm5z{S@orJ|p753;>``!bQx}3Zi_hz<M5!-wE0*K@)
zvoopQ_Ovm%LVc_YYZ)E0T64wgYJPi;w}Eu?tGO*H+&6YnCw&6nqrmgr7KnjJ4Q_E-
z{3*l3svlCs_?UjzpQ~!DLuqo5n0Dcp|9$<fn5+zMN3;E;GL+RNdqfD{j{D~hf3$NH
z;F|UbBMNDBb5!8ghFz@)$_D&m$qLYjYn^@puB93BR2#X*kX|v+>R6UBuMwvgHJ@T6
zDk@TV%ebTjxW_O*p^IHsPgVkaA2;Kx!<me<tcSpv<N+F<78=W)4IiUqUX4-mvD#U!
z1e;Unc+gSu)jdrh9z~72o84w78}|M@&i&_b*~eV`s^@^0E=HVVGkuwfCG!#>BLJG+
z2g-fjOdpo~ZPUq`q%IA*nBQvzS~}00c{z5#%L-B;`I!H!Kzf=O11XRiK&dp40x9j%
zCOZS3NxM~H!exLE%QvGG0l)pa(2NsL@G0s~CaQ-m%jzf6q2NL@_Eq)Dic9-uZSIwW
z`w<@w&8Pg+amr-HT1!ll|HaljM_1NFf1j~!b*xU(v29x&+fF*RZQHhu8{4+ivAg4B
zZa=?yXXc&t{&DJ@Ter?xr;@wYuG;(a-8&sUos|}4%4MpTLgqddh<{#MJIODSCC(Nf
z9Jz?67c*JHR#;5QeBih@8T2}H_~lB1;C@A>iwIMHxZ^XUM-V-MXuO5Vd|B8hr{0QJ
z{3y3QJ{Dus0`=(lQLc;U<8ei^$wA8~u(8z)_8^cC;H|%RqGeb;FHA|(_UK4S%ledW
zzQ1>JH#|ND#^@#{r-3m#4-a6B?*1MaqdPtZ#^|cMw}vXrfR`Gyz^`CQgZ|y>ft%fQ
z?=;x+-H*C?fa~GsDc;fXh4e-u+5=qxlf04d5ch^eIbM$K(0rtMmXc_;*4;71W8rU+
zk?2VT+Qe`)X*Vl@D%a%1g@lr!aQf#hgI=xJs-j93JtU>*m7+*b7~s|&)#gIU$u)>S
zghOJ*%|ge`{eR!OryxeO>CB`hkousO%J+S_r1=(pcByhm5_;daOC;5?z3mC`yQB@}
zX0eLJ3%F-t#W>$sUMU?J@!25T(J<5IN$lb)kli;1iy{WK8Np-Gti-LBI{l)UfS+H!
zm!Xiy1pE6w$FYp)0h;#FW9{~3y76J(Mxn_o7(7%0y3+N{)64A>1(KlRhvQ1DGc<ZL
z*;aayn|173k{wSl{d%$NSR=9cU<SabSl$=HR!Go1_OC~R@NmWuA%bn`kOdlVK+Udu
z@mPggo#6$?2FFVS1AtZ?%vr7+3TI8rf4QB>%o=pV!P2>1wF(kvPR%90D>bDGiuxyf
zyy<hjRB|OMyDcFFK6YGpwCZHh(d^c|$<(24d&8ZJxXo4ogzfz}$G~w>?OL}uIGbDr
zq?PTb5uO75rNKdUy3evb<S>LbDpmf%_BSbw>K}1r0t{p&iA<>UD|n@lbM^>9DVp-Z
zMGlzcA+)YihG`h$+-7MQe$f=e?Btd*GwH#}u!*Q0hGfMt@$AAIFdmOEXFkZf0vjuP
zZM^H_)*Sx%e{2LjZCG8>c3rMI(EM@02YA8Bk<!}2naes&0DYoT47$u)5fI&7PPafS
zsb;#12TX*55c(h>nOJ*Hu|p@qOrJvwnw4`O*XFzEhc8lOpCT=9`3naRgWVQMWRLRP
zOtFQ|De1-k%*V2~Dw6zOt81uHM{TH#>?Cz5^SG{ZoZ<pDLFNBM*9;{(E*vT(Yk~zk
zcpeU|k#I}rP91W(mGfqVb(3gDz$Z$~sFu6Q+Efnw3%09<aDPxs)eg{<{A_w^{PZ{P
zdU;tcyrEUSImxr?RhzA0|CnB+N*OXyC-XVyj~-DT9shYQwcKl~;%g;Sl^Q(7dXTX!
z++Hxsa)&)`mwl|d9SL%fSEMfi-SF6ZHamNV`paAWGPkB`!nJjzi6%GawAs6jraH?@
z=i_?$uXe=ey7e^%c*f}*LlGeANs4uY(l0tj59rWeota^Xpm@wvDl6%fR#kK(+l1Tt
zxLC=sTw6K*b!cBN9{ZCmP1AGIfW7LOx;=g@QHk~mxEbs-A!jYoxUOaBn>yJw%XjL?
zGDCO>8#lol16|-|#;uC%#>U8){V(L@h3B?C!eH0O?>yF&@;*G12MjS?x-u@eQVD=N
zBX%vZk9EV)cp$T0_sX{&rgLK3xLmxaq%$qotn1V|OvGF!PW2_3KRF-giJPA3zG{kJ
z9VbtT==iLkJk-DNUiLOvv}q)tqxYdrmh>ofB}fwEew>VLB((hE^4*?h`E9g<_tYLM
zCWDtkNB21uOinkC&pctTxNk#8b2HAV3w|P3K@DK#;KWQiqv#ppm^6PwWBa0*xKx?E
z9|+VV1f@wk9G>najh#h%mZ%_{Gx?yU)iQ4m`ObpYdY>^-?H281?w6vqa&(foxe1ot
z*rokuRJ#zx<(3D*iBaOH%Z?9XR^)sitGS*n5cjUR>Gg@`<<FH~l>8Fxg)^!(%WG=9
z%eTFa+Uu2Kn?$H`_IL3gsQumk9_!GdG!C0qDrlSo+59A1PR?zAmZD}Gj9})Jp^7nk
z79)D+-*v>3>7UbDNtgsyPk0BwnGpNJ=YUUoY#`M-Y@$DB_Wr)xlLs5($MDh{{Woq`
zAtW50LNo^YuBz)FkPEQ#<Wh$OGa<_+`y)|79X3xl1_U#Y(4DM`p2y@UNYAyh<GLpL
zY2VXDpvGJpesG{IhVzymLrq}JSw4<JdpNtXi8s<08%(+E5nKaa3<=zk2&rbtQYk{L
zxwS9NWyV)v%I@^P&0UrN>*@t%UWF*w;lKn=dt)W`L{G*tkk&d(f}e1rALhdKdZA#O
z6Kd|tm+26FXo_CliA7qMFZKus1d|n6N^ZCYQGEsUL4|N71@pv;#E(n3ZsmS056*PG
z*JT`NNZthTy`54;KJ)|)ab?qS?sWgI`^oIwH-1AfSdwX$W)<c(uK#(>ABP2hMsbU^
z=K#bKPF_z}zuExKjWap!GBec0^YTf%oRaOIc&q)|H@gr_S<~@N-3B>OJlnqe)HCho
z=I_5DE>IwO>s6Xh#JdGEqy@fr5r=tcxo%=2K`()_BS5<Z_RN*S@eb0Dp-Sv2ufpgM
zT0>xz&C{by!G^oi$#DLaP@+|p-AqX}lssOQIftFxqxt2uH|x8Z(%64Kmo}(bwLU0k
zNQ=lBt?fNcD2Rt*ec3z#zSr6FkyZ9sw;HE&VDb+A>X8kT$!BTTJ+SlX`lKc$u-=h~
z_eIgP?|`kcNcubcf;cK@d?*WIS04Xr-knRJX4j|EkFfpYP2NeY!S4@KO=jr-kLQ;v
zCjUS3{0JF&HsEgCo{JwEeO<GsMU!ohet3A6Nti0)U)hZ%70jM`U#rfK3J}*jZd!x=
zzUZ?7p_F5h3%H%zZ-zJgRcWlvjHgRpLCD((&fh)+Y}kBp=gI)zIAf{}=k^DHJ`G9i
zj-I!!02Nttxq-c8I%`RYlAB^52ejZcKV#HCWg8VvGI6Y5Z@y%AByD)?AJxPbe*<9(
zAFA^RSJKv_V3nGC>UL~|ErYB3_Y7}pwlo+1e!`_n0Metz-?);0I)7)n{ko#~wmvPJ
zoIyK>flT;*vr{aAm!~knhY`g`G{o_2EpE0M&MQU!64<$D2D-}|wr0euHJIiV3)wVJ
z>Yh2+&B*ow>vI!dqi!!&T|SiG9lt&Ikic?9K%NKBoiW*_#Oa$kMYOH~udk@JtFVU@
zAiHX6-$B7tFn{~^^LplgXphAyXWOrV7a=~Gp_eh}Y(Ji?Z^qe1SS@DYaj6nA+^iXO
zYs|h3HOf|-meEv;FBbO+S|RwUJ-VGtNJ=HH6%yo+qkRnn+&ef2(CcTpX3#HWZ~gL5
zTbwmTZ?;+1*==5o^Qc)olikO_{F<IAXn|{6>VN;%@g1;GTl-JjnnoL+chn$A+Nk}B
zR?jq*5?_6%6YpPeJ`W05B+9&K^BK<gimXySsmM>I(VTJ3PKn4^*91WaTA?)PFGtMn
zTHb%Y5LaI#gWl^L1@mHX(Y8fk@$#%oN1!_-=jHOyTiQ3%GsvNrfRC_no)A`*#OE35
zg!0FG<CJa9h`sI22VMjHAItZjd(7NGuuiq&O<+~UK@)EBwf@gM6V<};<CqtXKedNX
z&RR;pQF6m~lC0lli}+s+Vu8nGYI>I)sVZTc!E#cUnz&Y~7ulJz6a%~#z<M)Z>cMjr
z_sjw%6Qi%{!3g@l=X^-w(D;JgJwBQ9z`)GpRhb5{UCk}g`i47^kuwe{VzWoOa1ef9
zq1M=^WAl!8Z6fQl!=LRnr+6->O<Cj70zD?o|6h-ZpiC3r<YQdL&BU$rlC;9iIu>1Y
z=!zGf&!69uk=>Z%vA@paKI&^*V_7(NuYnE|E@cv#7`=K%sgt#zH>byaF7g5b|4U~$
zgJ^tS1Pm#{rvB3zYGnWabcWlN4?gy+T!Qm2&uP%E*XT7}Iu!pK*Y|PuAJ;cX<!?`!
zR;qvL)VS=vV)3%urPRLcoaWLZ`mF$R3Yz2&>K-S9cX?$71iPVAcb=Orj^7kQi>1+!
z9MpbKU?yA>Q<Ju)=c0CC)Z@4tzT2UN`ir0DpM!+ye;g#X-O*)w2KA%PLPGqHW`@ZO
z75|&8a6$3^l@;dejg;K}Co3%ee`JM{H2kBfs8YHn;l=C@87ck?F-@bU%y1IQcr{hg
zf6>E<;ZM&qjQxpcl~N(KMdLx67bN%OU_03j?ZHs_;a;7c@Ht^~vishBek5<!gV`ky
zw=x@byf3~yCx<}6x(-x4SU9(psv6v~&v8<SGchMwNi&hY2n$Gy^-V1@Fj65?>dkpf
z^sLZV^Ra65<Uh!oya3^wlL(ICtorGZv=7=J^Z(+1gT;N#X@{TwRR`0&$+|d6Ty;NQ
zC<c|~yw4Pz(1CgSJNuHp!W;Eo(M6hcTba=?^m6lhI(&Ux9Bat1Ddgfga8@>Zq7l69
zXX@(cC9PL!uKX7c8%U@b`Sf(Yt0D66@a1AzuonfYz^P7IP~jEG=rZHxv2;r9hF?td
z{k}Oe8=vC5Tl|xyb#-Zb#f)nuC$&(2W>bKl;e$MppWw(`lYMj6v*`Hx$FOSC(Go_w
z%)1em!)74HX&#n+KUA*W@ChU2@;inK$EA9E^EkfEJyZ$RB&B`*{=%t)X37!bMPRSv
z3{=)AXtutgpNvC30lXM1-AogRh06`3%k3rf^lXl2*D@oO`jK;loS(rW5e^5N?Q0Mk
zeR7rWiQOVma>P}`8M4i5kZ~WH?JIb?J^P0cS9kpxvh-mBaQxq>sZs&zBn4ovM^Dok
z^2DF&^+#w*dA6+2d;)6<U<;AZUn&3`Ke3k$9N+#QEo%CY78Q8~FM0dI{(b)Rg?Z0l
za+dA>g1y%^J#a%`BX_}2y5nY_(e9f1$$C?&3FqJ9+fHkKcE+zC5>qyBb0Q}YAl+rQ
zy1{o}5*=-<7Yn}*+#6jE(A@q59(O!lzPBqj3UN#!`nlGPC-_jz3ROX}NM!#OdtM+T
z0dw=I@D;esyh=JKDIt4f(&lU0+ufiB37&oLh(MNM^u3o%Hsks9^AaY~TfNo0t%W>y
zGVUjQ>L1BahGs+y6L^kO;5dp|@Co0IE^(zcU=Vxt?7kB(a7e`U2w2gk|2>ITr|_Op
zbl#sJQrj~L@BU+>tNSl~-ThsD&!n|wk<;#R3x@|X0bG^0Q2)+ROaH>Dfo4ip_k&t`
zZy!E=4=NwPHR#2Pt9C|B@9@x^scp5=V{j6m={hgsyL9bpp@cDqL~lbW(}Y*D<>yhD
z!Y3U!YWWyeOoP(A<u<A8_V1Tf-PerQ8)efbpW8Gc9J$_=XtaWDiiY2mKRhRhx>*se
zQoR(c<4CbD480sw5;R|UUwcJ<rm3Cd=1^7>G2EZjp@0kjL1svqlQPetaq#J2b=SDm
zt0MQRc^o0P-ozwvbkjAdIy}c@ClQrvc04I-Mc81%Yj?p4d9>xi#c99uN16npo%b7^
z#3694p_J4swv$MdTWFmcsf{Go{38~(D`$!7`pBXddn=>!onqQ=_`Df3JWWmBcteR}
zsSr%_d@_MJP4W%o;S@r2u*z^~Lwi>(6hae>(y0)@&J1#xqsxp-XLmZ7zU~@QSmDi+
z1Y!$3u)%=25f1_w-@ynHA&UzXG>C0TW&#*C@u`4(xqcPmDHJ5g0XCr&P{WvCI4Ip;
z9T4H^zU7*){R_yczV(kmB}8-|24`W))6y~m8vm;oJlMDVTLSP%0v;*8<r$&^OR@z-
zR-?thqkzcWGFCk)1V60CgL!iP^S8F}!6RM5iNzDL=Hck1lSy6O?>?2wKQ3NA+j{zK
zv`Z7!ifVOrU6eY8$d{0=UIE*B1{_NrG$ArA@Ry)H3Mi+WUBd><CFMaSKLm5=CZ;B&
zOp}dv3Ru}N{ID=OSGEbt$6Bt%hk<1je_Z$6+c;ii(>Dy);Pz!4YyZc;6eO3;bXZnt
zr#W2JRCd8et8cGute6(Y+1OfZZ@#WEh~|)41Ftq#M*j}1w9>~&w6?YYT~*qfoj_OB
z#>(-Z8DQ^flbN-47U!~!?S)fy3a~{Jh5C0-D}B%};Q0NWWC0AV^~4w2$00s)%M9~+
zXUqv1ed0+Ob9?|HzV1K;4#H~t3cLoaXg#LBo-jiu5wn?&nMQ&rM3#^nIycJ!X%@dh
zic3Odtnd6Eb9UGWR4tgK#Q5|dq4nP-Wj%OqzLjoZkh4QZXkM>lkdNF9+Q20;M<>b&
z8MS>L%L$>~xWuN0nrwgGH3n4wFyQlzHlel#k4^P9Hui_Llw27h_$~w=j$iL$^n=gf
z3{(bL!xOLoo=Ql)S>62TUjj`B><tj$=0hQgSPv*ljoj97=sw8TMvpE}?qnLxW^Tk!
zid9#4GX{+tp4U{z$rXEiSvU2=vwz)g5~ZA%)HpBwBu`OJzK4EHqAok-Ct&&Q;32lC
zsjKnxCjCf3ezf?oS2V*|XW_`wAr~hpI?a_^6QMc<kOlcr(uEu0+_bq%tgX<8hqvuo
z$K$Xi-p1n0JqSwgcW%M#$YC<`RTAU+E5<cL*iAZV^b=TDXXV$hw){uN+mziL)z?9v
zWn{Mt%k>C&+B)&B%}0^8J^R~?!JaRvK<|(G95Wvc^O&VtIGf{t;d*wUNY`*lJweWg
zko!MXV14OKl+`&un`BE9skXF>fuUYP>8pH?$4{y_okNzFe8xIS8DRX71h>S~TEjtP
zsl<gxY=-YIqtEFM8~k7MJ%k&t5VtKp*xu&f<v+z-32ejULfQ)kzHx`Mi19cbcH6sX
zXyE+4$my?H6p)O9wzfeZiL$G>D_F+obdxW-4g2n^i^2ENdJ|dr&5E1j>E<Fv{7AK-
z$oVO1kxRAtO{32m6K_y6nRvhJ=KWy@7voi{P;MLOGzQ9z#xAd2c!CCqG_eej=W%>i
zeeHIgZ=mdE&$?KFq*qnlpG0Q6R)gPYlM{oilI*{N40BjVwJ7V7k^jWi*frQE9kR-3
z^;o-PD|~pyv1vKawqEola&1_)a^DpFq4!c*#UI4F%XuGPHl2Ss4V@}7>)CaRbWN!i
z&i>3%`8p*iHn-OrJiUt}M7`g4Nti*j)4Dn1T!Hu5wiTIv^L^_5`3UY_-nwRX<6|vI
zDf#3JOplx!Ds<sfrsr;;-L`Sg+Ibb!qSg1N`o(LY0P69%?iXd_c-yf^oSS%MzBEBU
zo(cs!<6(j)lNh_VAbP4XgWw;wHzI2B<hf5y%?3lB$Q{I~3qcv{3a%MZyb6-jAyagQ
zLr8D|4l;CSFPP_YQ1HwOvQsZ6(&V*ki73?Nu)ie4Y=Y8Fj$S$~`0XRjq_r7`a?~Io
zp(ThC_xq1;^@F^YLZXba#A!;hXeXASEOhyr9fQTES*M&xXkhRZMuNs4jv|qkxR-Ab
z`B>oNVBKy4OPc|bBdFXIOgd=pucr_x<b^0vW)NRN+BxTt>IP24@cm%>>#wJIPc{4=
zOJghXm&iFMoll0zu=$X@#}FWxN;2G7ZR6~PE|!(3woPafDxiv{r_|vM?i;X1bg_DY
z&?t;8L2LV#gQ`U#D5q$T$i-2|7QjEa>&F?AKzyvnm!bYU$()ky`E7?%PQs7rribsT
zaTER}343I^LO#;Wis$Xgi=;DdoloGamc8amh6gc$0PRrjTb`$@u|0P_a<}&^P=Xp=
z>f4zO4mJaZ0Q|I6m!k8PGsle=RTFjo%m?e6+GPvGakRv0$8F!7D|G!lu`d;n(hqFI
z>qjCN7RM5m*oEj{k)2f;3MF|(XIckte~J1Ro4%&QXN&cteK9+_*_6=Xv+VC_J%ZBo
z-x*(x?9XP?e4iV0ic4<y{z0>a-ygp}_vZX6Ve|vWF4Pwtyt2~0M{1csPCU4ov&AzV
z?)&{r_;mbuUh4{B-{n!+QqZwA;EzNsv5Rh)B`efl^ePIYyxi+Tu5w;Xz_a>D@)p)x
zV+XCbhMjteZ#vQ*(<E7M{*L2c{1qVZ`oMj==s6J^>7x51>a;byV#w$gjs5rNBuZGo
ziE4%Y<nY^mfYZ1Bp~`u>$F{oG=AyS>TxW`pE#7g=eL2kp7?>F$7ye@#k+s6@n=)Wj
zU!$47_1xF!;Xw7nc1^+!l2)hP+on0wra9fF8|yMl>@u%(6U%pzyX+QU)~q<MZF{ym
z-=e!Hg<8>Dnl^XdI^};e+X<ZL7L)Z4=kZPHnytnX-RNDtBdub$%a`Z0=;yIrw56@4
z#n3i_GnO$VbN7FHBxo!;Tg@8#WE}kphJUVI>*I`ar;)cZhjIzJBun_!!+zsxyK}r@
zEY@`;W93ul)r6t>8!S?tJY@#y5(vuX#*{9mQC|J6TsqMXMh?15dXn8~JDj0T>Fe9d
zz_?8LNYq(3pBG_|*}Wb)<<R|EkBdPmgZFk_%824z^eFP!LLDjY*I#Jy=qM&qVMN(7
z6rRPBu*eU^&~&%x#Gh3M7N-7*^;6xb$Zuky?jys8V(?F?3K2r~=bTQT?c5KkInzZs
z?$bc<Z2Yz&S|)M-X}$57$qt=Cc^$p7<bol|7SdldtD?M}I}h0Q%y*RiZ7K(oL0|2W
zou{nyN8K!$^Tj*cr9INW>jm4A=o-BJPySXB5#`VC*!8ID{t%z|TnsyV*Z%x2C2pME
zcZ}Qc<P?YGfBp}jrGUJ+6xj6GDO!C0Pqrp=_bbe13jbtiHJjd}FS`zlqV5k?7qdn*
zv(t5g+|mEY*OVUTwarY``FLif?y)qDf`7G3rz7PQRCl`TvB}b)6X5Xv%UjL>`jF4}
zI`gTGYIhh{KdUIag`hu%%R8eVn~khl#ZbLUb!T1okG3s8khH#+A^(rIwFybUwi@5u
z0dBEXSU7D<u%M3%$@=ETHgXz3yjb+7DT_*OAh$KG@^mtFO-lWY4>UAFvCC%?DB!(1
z)8LB=O8%sMs7~D6_lk_KxctvH`<8`M?(RP>;n)a^a-0CjC1}FP4comwK7a!^P5*HT
zfFCD{G>3AD6%`{<bWuo^q2?-nCqCM-SQ5yncs`zlK2Lc+XZhkFBG!#}@#R8QSJ{mw
zhw}6D3BT?EGd_hBtyM=k0!2FsrbIp-KYqe@M(Ivpcdr{iL)=auaq~s#I<*0LglQSQ
zhy{%Q#UtR48JpY#llXw^44u1*UDWfwCZk$RkA)`uKS)AN^Z$+{yp_+Dp(BqPAhhj{
zJEW@Rz$5(qzomEGhC@34Ukq61s^EXLcY4Dcx<WnwHwB#H1SDw{lDij5k0<&Tv54X)
z%R6?=$~)K{@`WW}c=~J)ds+h}dD1%(OJ&@1hKnK_6gx4ru4qPQwwx>qjh5b4aaBw!
z$nKO)?Tex*i^PCF5x@AR#q;mw6At25V&W*X)nj8C2?_EpA}Orm>JdhY$t}_td#;aW
ziflgsCj17bk!KaAVzI`n^bJiDk<ZSeA@S-p;%XGae}+saC;ktDi2Hnv&esSuMSm1u
zN4r~;Z(>)@1iz6=T)B&7!F`R)o29`^IGDU-tM`h5aI}iUKN&K$e5JEwEl>`jFdn0i
z0Vh9Rbn^>&oMoZx9(nKuy70Vg9~Y{jOnTSDEtt|edapa(uQG<8KJ+PWhvgEYxLWPM
zb?B|KS&q3zN^mlpH4tP4vzOLdVlPUJUoeyNdoX*Yi=1PQ@i2SJv^&kvd&d+Ae@xI;
zllw1A%VTen;d9r|h+Q$iDJR&5JaFc~&Aj^_ffB#;Tb=})yk4Rtfe|@6@us{w`th5!
zKGH8`y{iej71#gJS^dZ-vj!ZKoQ{qWG?L-OsP^K^>%4k_wG{n11+1dm@9?o1A}P3X
z3^)uQ40;aC+^}O_zdEtRvvZpl!C+~Mp3zg}hb9Q@orF_ENM6(dM|fVOu`Pw9IXqP7
z_s(|bK*xVE1^oMqrJ~HE??@wg4i5ARU<b#%Sy{#2w1K-shz4sI;{e8X;H}Zqc^n~%
z+4PFzS8WL{ck-l~sx0X&$sc~QxCKc3L}0lM{?8C@{)=i%O$QUC*OE}EQ{!fs-!dGY
zr!1QuHCwUR{2hjS^Ox!*u)vC8`EOS`6>Sgy5*$rya+6+jj^X^_$iyf4Xx$xaaUw%z
z_3SX&{QZMv^r*%OezyPc$m58<FVF0+irk0CZfktHxpPG7n`EWHdxmWzriNY7`RrM%
z(*1;VU408*^`<(O%uPT1sKO4jSM2JNi1wC7ItNd4j4Djtw{u78Cb`c`MP%ts@$pN^
z2=^Aq5?iu?@dEzc-z=T7aX|*IWao=MWeH2MHrtV}(dkVeg4gFYrTp)2Ei%kJvOaLt
zYJo2dF`2Jk5vgqHHamx0*6o?Eo0e>v?Mw}#Rjj5i>s(KWDP|S_*61>{9&S7$Wh?~5
z7dG#!eR$0{fBRgm|0a}_W@)hAtk~$>xNB5SNB5zm1RohvRf75zE{E(^7ApP5Sqf=a
zZUCWCQhY`)KdOeYSJ}+k*QMFtzPRdm^YLR){n)0xtboE!IV}lUb;)li9AHYnA8V9)
zD)54)Wncio=Nx>?B@|d~8L9A@@U@GKwiYQWJ!6r9Ux<0=T{c7ptAg~o0GvAn8T=u&
z3yi?(Yjg2v(ZH6V<P&LxmC=&5{+}gwDE$MTTOVhA=gJ(_ALEbOlCutCArtM2pWotE
zhL%rgGKl{r*RTLJK^4R&jTxv0^HfF5f!j~fUyFEhiLNn~Yw$6*S4zpDvYza(muJM~
zjnE@HC(_nM45$*c0rOcs=gfQkLnyMcfO_>>X9DG%Su^uyF$^%`tbv#BCiZhG;iXEi
z;V=Qo`r|t}&rCIzHFCDg^(QX2H@4jpvB;bx)AVT2+LQ&FqvomE{^ET9*PBDnjoXcv
z7G<TnVC#YRE?#`X*$(oq+juZu^N!oOXYMMSbCrl|m}kL-Ti$sdv<+!OSir|mTvy<F
zI{bX>i>k<%_v8GtA?)vuigMVB4@?k@4k1WlVDOHl9&J+%wR)=-Gmxgq1JXHgh!D#^
za(4nuPVCB}APKXn0n*^$scqmcZS6#uF{w+pCe(^Uxh&vb+knxN1Tc=+z^?k<ixU{R
zMHsXtag#_=-j!wQ(-XPQVw~%{w1WHSyze%LqA?|ocP`-i1dl}D8Gz}!8ZL(KloX?F
zPV%$?;xKH>WD=q3fUb$}psQPFPK5OBFz2ehwl`rrMI<_PGg~Bj<Ys<9j@rsRW=+##
zSZ%kROe=n?Poz`F7oS1+_st21ClUu%jK%gC{M=%f+`ci%h=|SZu)$gm4+v_9B{uQF
z(*=m&rMm7Vn^PJ+)R66*AynYg2|x;FJ2h(GfyZechK%D7gma0Xz#><Eku`&&?JgAT
zVnj4Y035`T#}<UxC<*ZnyQL2bgtToXo-p{j5><iGT?ElX-NDNegwz=y(HW;{K4b(c
zCOz@Z>=_TX!Bo7)7NyISsdj)KtDgNklJ2>;R&+%#3ltKCoeCXP$~rQ*?67?ZXz77#
z{~k0_w^B&mf{Re4t=Ik@8jqgf(}b-nBp~1CI?;!#GeQX<&VjAxS~dwjWbfi(k?5sM
zU%X|;fvxP>HYt|8b$w5ews~`pQo`O%ir&DZw{Ie9=i%Y5?6vdmxU>Ce)h}XMQvhYf
zCZA>~jjzwt=&G1e!+@=1bu%e8WbgYzKY8if5$?39@5?~?)R$l8(F3~juq1iq-w{9d
zqkhgj;-ivN@f1RB6H)|A@!6KqVLNCS`T>|dsdCFyCg7Gv+mNulwWr>Jw}gF=S2bjt
zaaH5&3fNS9Fz(F{Uh9$2df29GwGN>;zwj}&MWwJ0cZ|&~?p|)eKz@S~!BgQ}hZvCg
zh6&zqtPop(C`m*vf~Uy!GxT7Rhy}b$@^uL}oWTnwhEe}O7LVoSPGU*Wc^%z)ZYzNw
z5LzgcYi=CPFn4Pdt<Lu@-lF1wPEEm0sQ<T^Ad<nw0qL4x{FgIz?_&dZ`_o<7<ytwJ
z<0+DFpy}*h0pecV5mOJDTV^br{V-dBw{M)ziuAYNhpTzYWp4npW`a=>>}Y6fStU3S
z8{sl$5EfdK5HJAyk~6rXgsKUIqJ)VWWIH2q0gT}F9-Ng>8U*NiY9c8pH)|yrq$H1G
z&%k~<u7NRJ*=-0Di-V0vj!454LOm!ZqG<mVLU&a0A5<}B7S0EXW^_nq76)fdU9o^E
z1Tfvu3?V%I{QY5^n#vjK%#40klEEqBTT>T;VJ4RJnS>>GjL9hjPolc7e_!(UH*UlS
zrsJC2j7jlEnwg>8{GgDN+MkMEdR39OcVaYyYB1o{Fpiu^7GYr-(<G_V`ktF1#93Hq
z@jW?1C=3+VR2uj)W>JMgu)lzVnOG}naBZii=qHn^uavqiDErv>IuYr6D{VsIYsEMQ
z?S;Y|DEoj}lW~2)wTfA`^cD(o_Sy4=c*&dv<@m^aVUmwnbleeNac2+`yAXl`(mL>i
z*!m<F;hD9I!lC9A=WQj;(m^=#g(L>;1=S?UPKjJ75c@#CDdY9SP+M9Wpu%_sK>wk$
zR$RQ*R!m$B=b;v=z%ca5Z2i6`Rw1VZuJuqUZIy4Wq9%vf_HCOR`%~-Qq2?@U*<q7f
z@+Vm?9$qlpmU#1b>*rdF#Fbm!`TUvy2ne<_c#E{3s_2ko)`Br-3#+$b5=8*YJ`&gv
zxp`isW;Q+=<Y`_cFrBE0QW!$$jX=sAITBu^!Zc@U+s6k^N$90!_6-jLh;FEs7*|4Q
zaE6S-VroKYTTdY~>*Otr!NdHGc-b^%y0{=qK{Zzukbmc}TXBXsGV}m)v<8f+Ljx^E
zv|WsW!+c}i0Nc~0U5uf_u^KrwOisuL&h(a}eXT{R0WO5Npd36r6Hc)^PMn{tu#Rwh
zj<=vfa?~m?aX}k{r<jNT9uz83L?DqmnjxEtO>YVK=96<zjemc)nsdYnM)u&ixCF4K
zpoTzBiu+XuFBzD!7er!-*Bj+I@9-WAXxx@p$wHG{35^OVB5qgYtd%$=Nnb$~;8%nS
zi(<8zcRvHhrt3E>vS9<dVTL7y6Bvz(SaFMylEw>90YfO1V4N5n1ET};#NKoeha?V+
zQg#-ZcY89NftsP4kKm<r*PggUDAG7EBX?xkS^H$$7eS<xOFJKmKP5=kf81dV>ac*x
z!tpsIBEVY2L=b<^zu?x5hbsp6<5GiR)OLFZT5hU1_;vJzn1n^0CuW<b+2N5SQXNjz
zuY&dog#iipE{xvL@la#sc6a7t*j+(hfdLK_i4ehDZ$=8xjS~w&l|yF1cC=>5KH6iP
zNbjjD=9zE4#M`%@gP*RpY5BLkVb_Ds7`#mNjsVP515G$kcdInot;wi;6uKY~gmKMq
zxxq+zkZ{Rf&^<@ccuqoaBeFzLG&l0Zc@*#i3q&Tu*iC<~YE-0Qr||uH)i8@0;uj<k
zg2+dZ%(6vRISnUiH0pXg*`-fhknkc=5Pujwhyw=cmjHKh00OKD`+)`8>H7-*isAqS
z^8`#KI7nEbJczr-Cj>|YxstyMs)&!^?-+4eDS60VQt^7?^5HUd9Y{)u`UP4f-5eWK
z4u5l<p>)y>vB6s598XYr34$+Ds1y=IkkW$;9RCVVZYTm)03Dq7ZYjKSOin<Mj3TT5
zb;_Y71fbGny6H)WK(h%tcV~i3-$m1X;eCQI9ZfsQR4dZNy$Dn(LTmi79Yhkdm2z`r
zJ61JB)zrEXL~SjTju+T9YZ&7IXCsG|ji=otV4l2|Da#4jO1a9LQ))S|(7$p74m6OK
zKSBIyY~(2OS+$d{7^Eix-Nnh*GcVW62Ud<|?ST(LSBtF~Cp5Kmr9hVts2LwpF}7wV
zNm<L>s-T{&KAOdkN!MD#+ey^OR70iXZ#g)5_&zb)Dc?%zg;<<WGj3%NSEF==_F)rK
z4*ShU?%G+^(7I7@c|B8BMeV<44Nrb9zF6J;ja@gMdmWFkomo3+y@z`(lg|LQmD1a3
z5b$gCL9;zuVSCsc*NVa>__+eH=ULOA*vK7=gfO)|04H31!(XsL2Y&32kzxWl(v))b
zIn+Xh1`Tvzgvl@Bc%I<c+_T_LBM3jb{$?Zy)alD`DzwxsP?Ce^Z}kb8h)d8^QjdTJ
zc>iG~5Mo*KL-2v2cz(uFN1AU-=n(Q&VA&;-f1&yRMB(@_LPOxYA=rWo4>1W5OS0lZ
z2oK*2?R}3dwBJjTVyLEL3fA;A<|H_JRp)4i3j@~@$J+3R%7s}74X%d<tD3<w)J`Ce
z2K>Sp#}#rYu^@}@N1H+&Ga&Z}hM{w4gl@843a=a^HM}(qCs+I_<0K_)!<&Nv%%orv
z)GmQl(I_SSjL|@hAb}zX@rNu}L|F>up<WgZ23_jK|D7HJLxQaTQnXPr9!V@w5=D|A
z3_@tgGBDpR2$%e}35Ft`*k9vQk~b*+5fuhStp(qvke$)N)($0;zy%^~B`&fMNid#s
z2L>V{KgK|>NP}$Y7dT~%LDR1=mIcm3cpNusV+edlh%Rt2(K|6>Q94}+FtJ9ly^07!
zm%S!Q+DdY@V9lRorvyj$YAlUlG2mKMSP^wIXhNBQBvBMq(^#0zZ~`%i+-%NJ7%*B9
zlz^$>2N7VU?MD>Sbbk+mDLqA^ay*XUfVBKj!EL%x1lWSRp}E%E<da7}f<10#7i1#o
zN~<=j3Bq2f`<7mp;&W8@3S9YC^7hn6-uKweoY%-AV(oS<K8m<CsR*aNi3;~;MUB@`
z4u<%l7!c`3|2F0GZ{bpS4ysWO7gB9x14(qXH6+uqAhMMft)Y+HfDQ&FdAxXa30y>l
zb{Leqkg^n&GnjnE$4C%(nQEB5V%idGsT}YO{LEW&Sd29q)ymVBUR5q{*&n9WE@fk=
zHB!mcX#DNcC0D`=2Y~%!7*s%V(vP_sTFh90Xv)AQp7Nf5pucE~^^XdBQH8`%;q^?F
z9hgp)7Le9ZRgO&>+2MFRO+aF?I8w4IthHRRc&yZYNF7@uo`;@QXi`mFP14fX87G%A
z8MJI`WD~n`&|$Htt&Q%#@#GZ=TntB&F}&2{Rx8|+h_(M_Nvmv4!RB;FPAhjo#&!=V
zrjZ1mMStlRwl<0@2l2R-0LP1ZW10b<K$whBkq|~9Wp&gqm4>(~W##ZYl#-WCS)?8=
zr4pnjXKAc|NqMn@SeeXCt}tk64D{!B9$oSZQ2(E#Z0;)Zty(Q+%4D;mDKty3l8C-2
z@zfvHz?bz&WL1r!4_z9&kYBc%!;_5pPhopN$CBxR$j|=wJ{ASBU+T6Y9wKaxk#3X(
zO7tGh$n6i=!5ET%h-9zGTEv(Pw=gfk1xfHADiN`L{}%M6QqTgCFe@E6X*!)GnrL+B
zfsnz7C95oQG64zL&@w{AhH%uK!&Ep9vQR8Yw%8rnEfu(I0*Dz&ECr~%^>z`$u{6kG
zR6ggB1@(w1LKubIP`Km{1Un>?DzwAEX;3n`B4AP%VmClj`#e}}k7r1xV*s%Hf<eNc
ztBfj4(?nB_brg=d#yjLlD=draDP}{RYlw;;Nv4?}045vl?`E8dvb=`H*b1>vdacDZ
z6A~9yrVEUpzMW2YQ;5w?cfkM}GSQd_0_jlwNh+`#EH$nn{lkl;K?t!yB8v2h*-2lp
z9VJL%ahQl>15gk5sd3T=4UnLomxQEnm<UosP^WRp5yAaM?id9hoHI*dWnv=({%vk7
zRYCkY*`Ywf^Noo=3!ia@SimSvh?`JH#{_?K#3q8~3v=O)QIlz408L#A=$@e^E(m#I
z8mPP&LKIjI2Obke1@3bsj!<DfR-Tq4CJY8Zx{lM?#aDa_BsU+`n1+S5o$`npZ_jzi
zk<~~MHxbH!CbtAMJ+jCWAOt>D33#&YBwkL(<7|ge13%T{suc$T#)wz4AR)%{62u9`
zi>0Q$V{im|3RVNd$7N}U21`3baKdL?;K7DZN+3J*5NMdUe@rRc^lD3%8KLh8GbZ5L
zlf;iDw<*r<bJ_RDQE;C9fI!Xpqt2U9Z)q<SPVEbAS8N9Ur(deHH^dklB&yKMAbsqz
zjaXLpRXhE#{k^T63MLl>n_VUW*I{3UC<6=|0%0Zq9^XxNLJNhI9-bZsEe8raIC44&
zKDV$ux#f1e7+XCNNBBn%6Rvf_h4%Iw&AOG)<d`tN;_nDSTS@Yv5J08*&~Phh1{yZ6
zL;{y1NxQO?qY#vg$uJ~tv}{xq4Bah8Yr1ZcxGEbKYzRXV9`@35VuxeMTIA1K$|8s2
zBpEdSG6vm!`V*6b@tx!iXq67P6icnh3&3~xCRDX+DN`>Ukm7;uDgt~ro_pyYGBrDW
zQ!pBxzKJ1~cE6O1dU4Jde2okT>7Vt?C(#q%s%<!5WHeq*&RFHpQ$xKp2n@E<@7<gm
zK{0EMOu;91h9~Ygq`=O+#a9sGQ`f_3GZAxkH%7J2h1F-MC-n*@LX-LuQ)0@Tsc7+)
zkCoLwRg-&xY(4Oo;IcJ&Kp$ahuNd*~r{J=kJE3=m8CLt^q;3Wt+1A9&^ha+NjlE#s
zSN+pjwLL!tw$fXKc2jkjR%^YKW^4Wc60w6;ZObQ%UNUC2xqYwlskyQ1=b%`Pj{&bX
zi(d8Cf8;K|*X*mc4*b5#rpLY=Ay_!EX0U_g0+bP<`V;toXd@kQA3W%A0tX{cLMD-9
z7%40P40-H80P%q&LHVXZ5Aw5SFd7$%AYBSsu8<@%G(>peF978^n*x3&K?V3fBbNB$
zPwcpa1cN4Y4d@oP^j4fj)Hndo%HfQJ=09{KM~1<cegKFQ2u=BeD5)aDpvwI97j!!#
z^tnS5nE{w5sH;jXKsVKj&#{ahSDBeWIzctd)1m3-d<L)vQ27&=Phg<5qH>|Z@Nzk_
zqCltvO<6`%S)ky_!5Fb9Bj_)V^qzcvMK);|@ID1NOAl#sOA?Z1>6nY*1+UwIyQDI{
zB;@KCZsr1H9JNYkHe{7f!d8Id%fcF|!CB)<p&d1nW~*!KoY5KcMxcCZZTSyC%8%L~
z{wXz0h^LSr<%!E}kmdIw?Hx(7wceN@YK^=cLu+6N%kULiefYupD9t92Kvk4YfIVuh
zYK^@im1OEiD8D5dCLp9qqZNnq^p4s}eNQGB{&$dSh&^hh$-V<>wKt+8YNIok;}}M2
z6$DbI#VfFEHr*q;V5KalcZ@DXcWUE)A%)F;OnH;eo~tTNDtta07K21{vDPR7v!AI<
zCVc&JWmXiz&+pFk%sQ<nTy!W>OSI6}c5Gx-cSfh|$>&8;oq8>*+{pSRR-XH;8Tp7(
znX=I|Y6!Xla+K_<y=$IKtho93ks_%zBYG%ul-DL_cvoU`CPo_T6IYOPCIAT>{n;Lz
zOj*|PBMWAbN|S!KX;$1N#h&;|%>AgsapJi|wqf{!agcW9<wM{ZMIlpE?#0N0`Seg}
zsTzQt!{AQ|o-dtR$Pi8mPAr364m=0RvwqB3vEq8;6RWxRN@mI;)Rmz4+_B=Cd@HNC
z^-*HYz|q2%3$>Ptpah@M{|<cL8o?w`gtXFekWiU<lRd#;il)6T?ddTs3ubrxd*J(D
zq*yS6^5;@!x%a!DF^sKN2;260I|gOSN6JR$6^dF7oI(bQ&S@C&k~2UtqfAEh3no-!
zP65}dj=VT?%H+^c=c?pikOM=G`oxk1H;{jI7)T>;z(|Zb=mDa__d1NC7^9FJ$_fI7
z?LTm`3F<-s^dML+Zz!Q1gQk`PqPH4?qe=u=*RWs@KLMJNhqWjwM5EgM{sq~X4qI(Q
ziKPJ&j%tjObPA9nVos{J-y=y9Q2s4e$r(blyvQWUF8?i7!Q>#c|1DOzp&_lnX9WTb
zQaY%dX`Q;!y<-nJsZeSWb|F}BX4(1?M($+O0bpi<ie2I{<yKp0aQcBi16^7O%E(7j
z%Qc_S+JSj6?M?-fLLZ%^yltwdq{CYcy{!hi7rp6hVz?6wPhXvd0lI+_sEU>JIVh-_
zN%A%%t%Nz{=nXBWqV8kd&ZL|sh}_|Ax39nQB@lJI<by+Nc}DZ-)-rzyv+DG4#XFvV
zgjTUo1t(TBK@S4Weic3C(4Z2(5wENqS3^^~r_&x4xSotWFMNW_k-?(Y6LrwVXv8SC
z%Bfs<XcazHu*hmOI;qjca6l<>WjVghKhs}q4>bL<s2oEZ%2d_T>+Ji=wTuofmEz$H
zO7QX!6?)J}i-9JHoO8UQD}LyP(#yW+cr;2+au(E$C-{tt0NN&@|I9x%4r8lq42R*W
z^orZzf%KBAc1V=kDgAqg*-Qv{G=<KyVmg@3i{P5Fola6cZxjfkR3l8cXqx@uAc;&H
ztc{2h?R)HCs?A{_$z+RTLww0buzcVP1|SK7etslGIL-WU3f{(&ogbr?E^Cc$xOX7M
z`0!9N)d<}Gd}uJ`_#kK>2OSir^f414f$<Y8`^}(Gly%dA4%Xz_3K(k2VC%Oqk}kX}
za5!Fm);L|T^5(SBWV=%pNf7{_LX>k)RE4p@jQs8frTYxz6uvu*=-XljRnPd`_ESig
zI^Hc!mIUlm$dp8s5j4u;VJlXO;_Zq?+*^2~CzQ++3xVhjA~X{%fR>He0sKv+3+}p9
z8WFVksdJZ}8{r0DszH>4z_WMYs)R_&VUSP~m-e!PDcB$^B$Y+>C{mYD0Q-`N3AU2T
zLA#E?204_B?OB6US>%#DeF=nDN)gx<Lc!+#048Mxlb=`|8kvNn3~rPNMZl#D4pxbd
z+yaW_zu&k913)Pb9h1PQ00mB7Sp+!wVyOQnPhCNRCkKH_;xC+l2S!I%LE<lxi05As
zN<u>XO9VX^xR})rA%%gt9Z<k81^Yv+@o(nxR=53k#ZW{F8B6|ylL>hK-@|}!<<DFk
z3J~S3AYnw6u<{QCNe}VA3UdZjB;YX`z$%N(<v0~XL90^k!_`2w;{6br27bb+TG|sK
zxgK`#pW{+<r`%7faF~w=K1Ig+6@#9D-5ze2-FW~*Z<Is|kspU$3=Y{kY)LWu8?`d{
zEqQ-a!EOGnrQ-c>NbWCKY`BbPQHxaiB-XvL6He41%G=}^(UX?FK*Plhhkiv5*=K%I
z^mP9de$rpCeyxToso}qCSC~SmzVF9T(xkuuZ%+-53YnD{2oa$oMU`jMsYJQknhU0q
zvI3|Vlt&W-Lh{&UOD>7FmerZY&Vh5+p-h57RuF+hrS7)5M%hmuq(s~YoiK&p&!kSG
z47Mg^7l0v#Ay#%5{42t}w<L*(Q?H7IV&^tN`85VPoP>vr(H);n#A`xVLjn-K#p5L>
zZy;fWo3shvi(d*IQ=)4l85m5!7ruzU49$Ote+&gd9JPl5I8-9~=NW{8-zy4zM*_u4
zJ=~K=CLbpm5N;qq8B~3PAO02Ye-w^{0*s+7wQ2;19&(FXz%+`SQbu0+^FtbRif~>y
zctcyDU3}A|J|rPffsg~<>qtn-NOwjuAks(}|2?eWyP%3Fc0TzXs7^Vl2Hf)maPtW!
zLZTIo2~jiS3p0237zU!4@g=x7iAo%w5oRn15zdSeJ|@WvP0EZW5eNVSOK%0a&TihT
zxFZ%cfh84PDshs9LB>=FiI!0LnsmZ=eaMjUXIms8eO$uQY7c_iBe6h5-RRNdg!O~~
z>yWX8fh7oE6f-y|M~hGC%Biq9CNwQHc6Vro1woO>0r6Rh2rC3;<k!Fx<8+Bvg@ZsA
zD-%Rqn)jpDf&`<KsPPA~PK8!Sf+&ux@DQj%E&e*<^FPwdAZ0uJ%_w4BK^2?{{(uF9
zEHLCZh%XHV>=jtxz!0ZK1{jc@;hZK9F;efH6``|cWzILqC*+$uRH^g;;B??jNHmDM
zxpl!UKo!<O1XC>WP4JzT5S`TzPVqr15kkP3uoMmjqlcBaZb86G^-*|uZPTrqk-&5V
zHv*g+2ztnbQ}f-iXx)Gi{PhEMK4J`Ek7m2X)#bagi7}GVO<KX`Roek4uf<0kuslb>
ziOwY(K?1*OOXhRK0dcMVJ-vr5!VPpnLJJ2s2^sBhHY)Ue-u75yn{=pBGLI=nYXwpB
zm~`!qrMP;}N|;+&w1lz31phuN4#AB)E<<MD;B3!nggfohUy%NE(*sNj=xQZ<?{K2U
z%moxt!TIi=jp4y;oqCpHhZ;O8o=a^8Zs!IS?SIv~LjwaETmsY4k2|DRb!#8253haa
zUM1Za?30b`g0XMB>yl-SyJNe2zk1Z*B6@t?PV1LVd5u%Vi370Ykk|w&!klquWxLe#
zED)mP5K9V*gTpt8yU46o@Y%3e6_+YGq<v<==vq#t`Q%ls>61^?ShvS%>POjKr`f(d
zOE6H$mh{r9nQ+sg&{uV?Qx-OP2ejVGSyjkd^N{=(oDCS=^8Yj#_;M>*v@7Cu;DpQ3
zmAI|v@2>TZITJTv_ilu99knzyNZG34h=|Rrc*?QhP{wM`mi$Hyu=Fl><DSuVCZt9r
zCmB8wl&a?e>vA1Kv1Hhk&r3h~dmf{oUEl@$ms~tT^69@`r!6zXYy-a9p2*g_K5{Nw
zKRp{C1Bbn_-03Z;bRY#1KhR!=m-Q7!itf-~x;Cuu4`1{ZuqHiDW6u7jc&oqhcvO7;
zA@|nuBx|I|d6&d8@Z-yHhsgO5B%Y!F^hBc@ouB>f=O^R)^~U>rca_zb>wQN!K9Y?4
zaHze2_CR_|wUah)bAPzG>c>ZdzioPuBy<1G%=5YN*4NwX?y2qfg+e-uy|rJTFTUTs
zEtl52yU)kd1<QTE%xTA==JR1zo1dQw+1~}kwhJF3g`WXm%Wrqn>#t2`-tU`nKkZiq
zl-qo}JN3SvZO_7XfE_CW3@62-<3u_&0ywjI*u`Yv_Go@=fA>eLCj0bt#6sPhh#2&~
zJ`Q;ApGKoLc4t3n_>5048g$E?r@FqLK0G|{m$jixEI#i<t{yML(CyiC72ekm1$^6y
zc0Qdy2EX236mH77hJ*u~pI;QHZqg496{x7FK97h5blwHO*vM?Z4x#VOv7_^Gd~zsp
zA{SAaEct)^WXWq~%N)r}VEL<N^u_!>ifq0+yYkf)`#I<f)V%ZbRpn6l;!gKT3Cfxa
z)PWuR9`eGeDaE)8OZw?`(kqpI;e)&#222HR^fxxBq<gyMVzMb}+#`1SGA(U^UH|vS
z`z0Ukn)mp{?;~Q#HSd&WE^j9hG>Vb`9INAG^$3_<+`BgSlQJGn*7oSG&<y0!Hr4VM
z*~MmK%WUSM-3c6TyoP^&-Ew*mcI>--Q^{PNy?CKFzFqI_m-z-2$Cuj=hknRxc<asX
zdyjqhtGpno&YgW!MSS4o!Gx-g5<aaPw40(uSwbR?OT11(sI({vmHXBVv|%ML0efvQ
zy!)8d`LDH|`Q+vYw|!uJT7BUB?`~?J3XGB@!=M`MwHU2e^?8)5nL3Yt5n#>sVc%Qg
z`Pk}0!tQuF-WJ&#RC~|3W7|4YDE^*S{RbN&sm<K%eUl!3y;pcVnK9=K27OoL67s1N
z`TJifXNfujj+I!_E^G|Wb)!NfCr7W}>qrBV`_p)XjtBMc)soU|6lruGE_FwpV7(aJ
zPMll`K`TCwuRurcz5I_lS$|$Jm@+a*#$l?vkN<?fdDj{_mC2o74OhIoUY^-e&ot}2
zVM<-&(_Rez0F}Lo2ZvcwJ@NMPQoU{PbyMirU%f9QoyXn5liVl`SZu%Hu_J#e%EZCU
zm6pC9?VpH$xw@b@RhYyqYIvNW<OEoq!xAtGi;{q-&nXippeDkBGRtd%f&{_SK^Qc0
z!(-6t*pc|BsOjb#>>t2`RwqM&$HJx=!7$E8BA^for;`AZ7R>#bP?-_u)`*w!9Aw)q
zM2@<OUBMxu5*@;`(-fUxh>sz@IVc9#f-~PsdO+i#)!w5B9SjpHingDCqwVZ3Aj9D4
zfP#5in1m1$I}{T_1V<!=_!BFgqm12y)1w9C2egp-pT#6b18(;wP(cax1i`?AFC;~a
z0@9K|P*E$<kP3s_gX2P1(;aTfODMgE_=Y3sX%pHUp7YiHlz)7{+JC+mm{OZ2JFlV7
z9LRH0xLfStONGRq?6nG}$UqRk9W|d{$ORUhxa86)P4_1sS3$-LZ+Lofe!fo?c0rAB
z6RG4@iyMM@Sn-#Vi^YILHZFQAax(oG32<ESCcx#!3xY8&d<kbJXN5u?5qLnIUt+;Q
z8sUD}R}5x>fE#0bD41hq!9W^g6bS_pq7T|P=xzjP!b;-?!k8sN?vO^9@Z;r*Kpldf
z83Wcx(~YU|qFJ%>_n(c3aiVFUAPjM25I_P^hvFp!L-9lRNG%Lu2(nQ_^8>~W0Fy-j
z7i(V`5Jej`y2LKswS=&ABi&t60!nwMpp-Py-Q5k+jf8@9cSv`Gh_rwRca-<L-@p6o
z{+Kz>dCqxG&Yqc_GrQA|fZ!*NU+dl<uxNyhA9b@UwaIUUO&E1T;361v80-%xzvj(O
z(=h_>e)Z*66}OU&2;DbW)s8e~WNe^;`|W#c{qf3MGmaLyh!{L|^Tk$gIoVN0X(Pri
zYf-X<xNVnYbfQ!&da0hXsXX+R1fOh?-aCdC7F7#OOymga&2#Z@+WZVmF(D&TG8YcQ
zFnpX;q@vE=F4!w|eexoBBBVg+ct?-8dOI=@mdwEJ=Fq95H}F!&)KJ=y!SFMOBr;#J
z)2zR=;oUptiQzNKx<>u#9;Y^a@+@u+Bv3Dh^9oMCnzJd;S4>5tml;QyQavW)V<|ik
zV8e~b-4;VfMSMm9otQj3o5X)cfjKhem<nb{h=~j`IdoSeQk+4lRTVZMPr-jh50c_|
z-zxH4=3DrrgT4V_2ANK3AWh$#g~`y&djacd?`IQ&jNNQ#lbo)}X2+cS(Z$C!Qjt_v
zslkiz1QxrX(ppy?cc(@JOE<<-V1(LhKu#tplsfpnTQaq2WPO9qh2i_@%e-J$Kf0v%
zZn*Y&7Vdt$=IS2e+Ldxxpo))+Qha{Nr*I^yYM1$>ov8O942FY04hPz|6d;4w7|61+
zkqB^usJasPg1Ump<S!X%DKVchvjkm6C5&UQ_yrwfPxDMONrPG<7;unc=NKfdqLa*V
zz%d%^lARXdXsBJ~SDZVA?%`+oE!tPqH(ly@QURIq)3O0m7DWlh4k)`cE+`=cuO%Jh
zKPzkmQd2erQJZO`g3NVr=*UPahJvDUE2Z)Lqc!bNYm32IrusS}B_JL7HO79;S6=X}
zsRX{L8>|ib0+z(=C70);7V^R@tT+V0tnd3u^T7Qw-@P!HkL1Az)90^W@l}+)1RvOL
zse$+<BXzk8S>H;ADu1$;C7lbZ5BcN(z>uh~pO9rqAr&8eSW~7#c=A3*KEb?n*0`yV
ze8nRhG}A^CAR5c?z;g!H3WpA8=8gU$g+)`WQBx4t=*ADta<Zftv2)ji1J-6;b)VO}
zq4qSqnt1xih0&dTN5NQK)@B*;)3`(cxs%qVKbU<9S-%L<3X>%bj`~JV)Ms6oSGTka
ztRmypod;H7bSHlkChE5itkt-jl;K=5bsw?TikX6pGLBdm;?IJ)mbM6?g;hVJKbC%C
z3z~wsG-P0Y;Rk$RE18OET<eQy<XWDroDONqr<xhJmnu;vT?va&6>7$jDdr{8k|@uP
ztaw?0VJ9I`nY|pq`-!&}3~qIOi{^Q`gzXOQa%F4#Y^n#UqFNjeo-160bXJ5lfu+jJ
zmqI$32b(U0UZlR&n+(Ws5bAJqVQ6-q;*oErykT0he^_}%@D5>;V0QTy_=lHeQwQ)L
z-bdPE*v1|LGeZkFwv-p8Iq#VUMl;CpRWGZ!mYU-QkrgWEThZFKn9SdZWhkvOlc)+O
z`qmh)-{Ld{qzL(9^MthqZ!p=OC^<ZHIuSO;@H|nnHV8Noc6b@_w)zJN&1(8h3S12t
z0%p2K3VbTTdn=^pRplq6bWoIPNBd%x`D~OLsfFy-Z%aw5>8HffEtZ$uc!mfzUm{Jq
z;q0w7-H3XE5SAy)ezJw3An_KIp3V&fAvk`rX^S-O_Gh(L^C0R9LeQHmyqFsgLfHJ4
zyr!G(0Ba<#YIda~<0&e)efL9&ztP#{u$_l%b8>Ae|7LC?X!}fqd;N2|1NY~EBRwv>
z7_io)&l~e@j!x9!pId1T>O$p9?^c!gQ4L=HsftG#0F8X__{6!%Zw&^w7}Al2R^`FX
zj|Ne9X{c|Iq&q-sA<tSY>Bu0}@+j50C`cQ6bZt&b{N|cEbo!d;hRArB)&U%wB-<&X
zA}z9XWYgc4@HYY7u+MQQ>+;gMFFjvOpod+IODC2z=R1hg2@xqLGy;YF_E2A#TLMuc
zz)_-APVP0`Iu*@h0$NasE=*NiGkARy86FHm+*UaEcW4ZQBK7<2Y{3RGMIll1*h<#K
zs8XPCV`fA-2UAH9;vUS&5!(fU0-=}1fu1r=8au!9CO{vbj0XmM%>do{L@uAAIr@41
z_O20ae)oCmt=>4}Wr_$ExQD^qbXE*ALGON$Yf_mQ{sn7d=FsaMak_-n5-qFToIlWG
zdrHzDAH88GLKM$9-@nsqHfa7mb-2FvUQFVeb1|{z;k%{1gv5?v2D(MNdB6`oE=Oab
z&C!}+{hKlHaLWp_{|+}v^-S6Nip3h%+GE5Qbi$LsNA~r%sAdYZ&=<LdRdSO3zzaGA
zeCn}E16}96rR!y4fs+~GF0Emoyc};urt-T%LSkGsN|Yv#;7=LoDyGmx2j!0SAK&2%
zXIM~g5w866jGL>z2>pubg$(hm#gzP5J8b~|B~~!I-%4cfQ?_gK<6?Whm-djG1&I^;
z@%6L2?tAs0iv2U(=6|YRUSpm75IG!~tI`}TReA3x%hC7#!;jTZBvtu}1@DAshMrT%
z&UC8vP9Q?S>`k1L&$<)xJ_l&yI*Uaa$l1lXaky=zjT(9pDJ#+_!rO*f$hWLoe*`Ow
z<ovkFjIe(FE~PR2Fzur--Y1z)+@(1!DS_oAi?01;aSKf|@GPG_)}?-#0DtEV9p@j!
zE2F--^Op0NCJzSgo86`*T#8`g4{lyaOi7CZR}Fg?n{i2BJ9%kpCSLR;{x%kd^<Y6!
z5XZ1&0v-RrbCYdiAqLhxc(Ws3VSxh99)XL3J#0`wBtME@XICr&%zA?hP87Oj3<4qQ
z+JsxN+=PJ;!9w&KQk$4);@Y)%2ofdRF&M_ioec>7iD3vq-ZYnt@I<K2NpV;-zB!<N
z#35`CYg~G?TZe1+e8B;<tbM8LD1SU8b1V{mXUAWS5+={69Jk`I`eUBqch`(AB2ZxX
zfa0+R#DWKJbIxBOg0w=05jqu~DS#Z@pd!!wtd+6+!i%mzVS~=7Fshi9K>iq!IuJ>O
zXcK6wKt~kDmUGYpXVxM*Sj#x$6DOMl6~hQ6ftgors$RJxAXYL`F=adZslJzy3C6=>
z|M+omQ0VuhRpr-%Qg2jv**PdBPgZCrq_%~j%$xK4Sme7XvApDwATf@yLUvRU$EU2Q
zF!5q#+3CCpdTKKM^u&1Xtm&b_9D4<NY8&ovi8z=!vqN%wa&oy*JB348QOEgZSy4Ly
zz^JIJNJW;@-&|R?o&xSFG2Tx95ZLiA0z2*@Kup@@kQ`lHuPMu$eubQ<9r3?Q^3|1P
zooaz4*MbJS<}_GJN9N`e^1wQpgsmYtRD}m~8kC~%=0Sn-_Ug#@I`q`2n9GUr<vCHu
z!W5p$vaVZxIf?Pvtu0=hP7k`9V_Bl40=`wJUrns2QR9{W*wI9PbmvV7>dA_>`&x2q
zM}w!8jXoOm&4D)|yrLV?5}xVYFFj3x#h9*OdQpz802LwaN6XTpTy=iLu@PG})vwgZ
zisAckzg>@xW0RTDI}5&o-dh_n(jkdC63nZd=pE3Th%k}~S*O3jwzr}tQ+gTyYI_lR
zK-*{P)x{z*l8#x>><8WiKEFO0`SgbP(;<u@LPz1;;E~&;W8akgkZm0D@@^CqTtZJd
zs(@q>`mQa>SOw{pn;Be0s?$#CpfC|G9NjPxUK}`utSlHTKa@Vtzbh-Z6VCqygQWNl
zBPtZjJ&vloC#%@6)^C8Z7D@U@8VrdRQ1_>#8rLxPJ1r!@A>VTW2Z8mbB<Q&AqrhPh
zVN0BRN)=r{ht3|tO(<+aFVB6Fnkc_HO^t{g`miD67b57jX~Ia>0W&snQv+_T&a1hH
zU6Xy3+-F}Ikhx<BA*Co%F>6W0_0o_*4r#0E?g{*+ydx=>JrV{wd%-0v-F2vRqV)~S
zT72?#5e>4=Ng4z(dWTjb&D|6iG17ugB5#43l${|VGw2F*w*j$Z%gIKR+CG$LZ$uOe
z?~}zzs(qzy#bENIlVNxxm_?0ORi5y*fBugDFkX_JI!ugFGP#Jpu2$UjHDV+kJ&qsy
z+t-L;MRdW}l<D#~<T+{5FnAC7$uyX?JU@9<GXB=4oIE>OR3d&CC4)S0tsfsGLdY3J
zgHGJ_q8qg7LW7PqDjTtZZBB!X+87WxYQj!{f*8mVPsL7#gCZSx7T0|;FcqiD4?|;g
zA&`(fubm_-0-;MuoagNj%ONrWw>-DyPh*9}6~#0|KkSGy)*n;zu?;4~t`LXskOyn?
zAH^dLqzz<DqpE~>;BV%KzaWR@x{dz%$oT_VGR5SXMCa=wYGmR8fdJT45;Zcx5PtxB
zd=NDhZ-B3RWnenm*lfy<8cO_<Hz58@pPG<Fil-Z*nr;)sgFsEPy_CM`CbHPju(>lN
z!%iNjIXaL?gTLt~&cs21{gNsm&-l_r6hDD~XCbHv{UZL<oDvyL4iDAynFO|EobfCS
z3FQSUyq~d)u_$%`GQM9YgZR{J3gx488uF3~BAEVOTF$uqIR&!BIf}SA8r_2(BA%Bd
z6k42$6-a#%#LrF=JJZDvuY!(PbiyA)Dfh(=pW7f6Es*l4USfw)5Su(KYeXs`Z?`_5
zg;ML8B-_4DT=AAuj<XIfo7Ds5As;4cjQa>Af`M;nflaDumpb33$&Nv^E9LB&h3!i}
zMyYZXSn&Zj99@hYo?kvAHyn9_FkT*|4Ht+ch8<5JvUnH-DUjy`(PfY$7;lAh@H2$q
z{(fBaTHfPzqA|Gq{eZd}{)e5yRXYEM&eMus(!Syg!9YrT!iq>cpEA33c)f=n6%Wlf
zvs}E3^>^*3#j4=Eb1-eeaO)SYH}SoJO0f7r1>xk<3@TU7%5nsC61zh_j3$;BpDVew
zdC1u?EIYT0yFh*|+-Y!e84zcw{AptdgD%M^4IV3or8red*NQekv!6Y)VW-Ds!myO2
zD(=!3F9q0<b0H1>dDF(4GnPeNm1#HJX#}X*kOnG~8Dj{{n`9IcfD*_u7xpr6(L~jT
z9RZyY!*W2PxJwB^Ng+_c&%uU0(e#E}8!k8l!rX&BZ4AbCB^iwll@CmgJFuyRPb%ut
zO@%O5gDpuaTgKCEY772MO&inUzb2^!B^7stN%hDD633MSocIhFDetzKF)Vw`i@NOM
zvbfVQ5|aSaUd<Tu3Im>m$SMZ5PRiM^SJd}%rzwitl8gq+zYJ_;AF^QwF;HSyW>Xp2
zu)jg7<z6uT@Y~|Lk+E@~7SB?qh`xtCuG2dWFCh(A$^^c_R9VTz6g>hm5-l(lcgWFf
zK8T)<hn`Cl*bR4K{w>i@E*Y-Nc#)G2%4P!T3D_OY(hh6X;lX5ahOm1poTGyx2Xo;j
zHyF7=Q2xlhUP+qia!2tx_2T@185?XGZP~H#AjNWtJYx@@U+&wl-@sUmUB{{@sk$t|
zlKTt#a%tR|1fe-Lfsz3U_L%IFU&kWo7@Mz)R*n?|Gu}7U_}Xrby$u^&$s|Qi{m@`)
zLCpV|C5a{r4?R1yp`caGanJJDPM?Q`mQpKPVR%TRXKUK&oBP42J`WA2fEGsB=tLLD
zkx|fZZh_^Ql9EdSCM0tFTbJ?Kp&&jRof%RZhwC)vBofQJU*5mCV>0{K?Ax{P<X09c
z57UM4>Db@z_tWg1IOKKiWRv1&w<Gj)O}oA2H-D&><TZz%hz^<9@IUio6z)`lIk~HH
zYvb0yW2E*W1awWizh##u#{wZL?ntD7XcLjTWQxvV4yXF$h!|O;&ViKm9w3<NiiUmN
zhBrAfYRaUu)F!7Vj73|a#&ptAKm-b9FVo7Wp{lTYAz5;jrJB~3^DHc90l_SQ(~FH;
z(slxqzP0^&=bG$$V8)8`4V<m(gh}M!r6CxXt-}gQ5zjlzid7*5Fi`nyadSmLR8hz^
z0n1Nu=p4>i-bNI}#x{WjlBT}{r41@kfN;`}5U94Ce6aiKhD7u74(uqfiLy@+wze*O
z_>Gmiu{iCIqbQ2-HZX8zZka;T#>_5%%de!SR_5X*=iKykOFj=T4Jcm2_3sNd#CsJS
z*+CEQkKD#kfQsX#CS4q~P(f7=LUEG;&Wx!tesmCLJw!5WcLQl!*!fpvcJkBiFec&A
zXdD>JMlwz<Sn@L$JS4i68$Kkgg$Evj+`(Ibisk$c5gAQ0g2;6AG?UuTy0e11d@|1M
z1!&VR^@aL4-1#*!1Nr4$n1VgWuNN(yr$ln<dHHYS985T><HS3=PvRU9UbDqJP%3!V
zi5$xOa-uY%-n_)x@uJC+4R4n#z(w~+3_^Qeh<CoieaIHhBz|v!%hnsQ4E*cx?Yz8S
zp8PL)zc?Er1;4y_J_SGaGc5%_<2pA5;Gx-61wV=SW`#~!kWUq&w*GxPuCeufAF%5l
z!_~H%{f1ksv$M_$_dWDf(2-=Q7B9(FPUShimdWci1~!vB_u>}Zq;q9Ql%!v;>(F9O
zH62l6E_5Arc*ni^Xu0<y``CnsGyC?^^S<gHi&MAh>C2k6>DwVuw;AZe7k)LggHW{@
z+3CO^6GgGM%<@ICI`nEqv068}MJXE3rbdm4-^@!y5h{9(EkI=4Ct48u+@}^oWZY+3
zgb$*$qN|LP+@ePmUK{bw#ks#DCCVSHA$=pBv&QFYLdVIekNFsFhM{~O@?(fpa4s~}
zE#|%0#%{6MD&dt2<v^A5y3kx_y%MEahiQk0zT|ehXJr@Vn#fx7#qaYv;?zIab;K!;
zcfjcEp^iB27koW&;svChIQ{~){#pDPX1$E#oZ_IXgvUF|Wk-)1V3+=rQVTxONV-WW
zbDb}qHM`U4L$k`nHh;hSgYbteQNojBI;%hWd6#VzxCCjp6_T`j54E+O$3_G!f{&q~
zAPZ0hC|;mb;WkdElS$Z{9NQmx6fs~AF&-^wyQ|(m*}cUZ2E|OlsSJ?XL6lIft%TX>
zsGbL~n@d|_Ly#vhx=%Y7yO{W;KVTz*QRiU1=;Ju>UB)`yOziqO*kO<nd`(O-HZ9~}
z1WPn#4VfJ@1MPz-6EKv{>L8%N3InGUHkVHt8z<lbr*Kj$(kivDkZ*~V{lPy&%te<b
z!9hDbSdsGcMty3g0CEzGDFL})>;b%s6>b&lVyiSZCv7G&Jl!sy#9&Jl74U?e8e%?G
zLj+98+z=-!e1xTYc3_XNtGl2f(%9VP15Q-b1iNWIhk)z?VtqqY?ORp8>*|h}?d*pS
zpJM{4Rg$ro;}3~npmLum81ZrcbTuO5Jt;8a<GmU;VrM$KGvZ_VLAQY_Z<7lDMPld|
zLZFGG78rpJ&G!vEKK^@u2Qb4Sn+c5WNY{jq?jghkM1E9nGAL=fB82WgU?hPqA+s)v
z4%cU>bll&&{tCUbM_)_J{&XQTQX;HWF={oe=y#MvTxmr#^Iova2nRZz+oogi-p!ZT
zAAYlM;<CenNaKIFACJU$O{RGz801|tC;li+AhlO{+vthH@%**x4c1=vFeXB=L5)6~
z+-IA`m~@Wkw{Nl>AL~hzJP8_}5x6in6t~u(Wx$<AeaV13$a<3rcUnZ61=lh=k_9)}
z=#>rE*~pyZ-&wSrLs=-%c0<g-dxdEY6TT7zcDI(+WTKl1)`O#WpP!RV6ERVIsbr;i
z^TKl9?A2t8cO_{?YHXj$_Ice~J6lo0sEFZ#&#!E57l2^hYV$D&P@skM?V7<Q22Tt~
zO1uK*RbPt|hJ^!M9A~%MAaW)OG#$Ap;MXDKxv{}{1s8SLs&=At(cu#V@Tcr>7N5Gz
zF6v;?>cEuT@IU|zkPzWPxoc*U*5Yjk1j)PdSzJc!dn(-XI#*#=Q9|_Sp@Glhhqu~7
z<vV72sj=@_C@n?jHpS9zwL|@<&+7>Mihw0tBLnA-(7*Qa0G@z%%~;2L03%NUJ3!fq
zvEa_c^E!||;11~J$N;<_;0cVKkphhv!&H=zftQB@xKXob=6|~5&4QU57aKfUS>w%8
z^juq%7qj$jYD39RM*hIzw&|^X+v|J%N}$+>_I1NM*CyBY-ZPUBrFm8L%Iq6(gw<xf
zp{3$n*JY*ToYzGOn`khF`3q<+^uo?7kj1s%ej>q6)e7G3aw<=D5A$Y1M@vxzvtcWc
z6Cg(q=ELJ`-m1Z1{BFA8p@W&-wc-*KgK1s2uNg>Kv~<HmMiM1AjRmHU1Uh$Lbh&q~
zSbu5?Ybym#{diT9Jv&m_+L!ta5W*y+DiF<%cy?IAqn*mbOuK$*t4gzP-k!*+Z1|{$
zX5i*|wsITy{Lu0SgUz^txJ$%L_<{1frObM@Om=GpUAzz_1)J_X$3rD3onSIbpv*@O
zle|HEIx_s!uZS@q-uEa(MA=P2QiW<M4%XhEaigQ<HQ=q{vp*tUBeZqj>$UwByB9T_
zAm1kUE~2jryPTzg;CkA(q9u4*2te>W4O-Fgd^H5HG2CCaqG5Q+w5o9)U+u85cYoUv
z=Rf$glbq<+nm`7Dw8gBTgtSGF1%cZ_R)T|D1KMzr-2b?L+Dxn_uL<eX7cz_vX>n>J
zLI1GYf`;b&&7BtW_-#LvRIm{TrZ~Le^Akx)Lsm>bcthqBvUfYlTi7fI@3)jOIJCl-
z{Z8k@gyK}S!j>JN^PvcoCR(A(T@3Rf%ab&;3pq)7J~nYRXwB8W=Ng-uQoV+FCy0`U
zIB$D~OJiJq%6=wU0f%%Du7qeh(zetQKMI~IXisZwB$qb6>0~yE*YeZa+N^o34(c`h
zV}KIYeocxP)^`3y_s!+|br{E)mQSGZ*}Qk4F^ZPAnZv7jFRcmaqwUWlQNMXlv6|eR
z`R$U$ZpG<w^cNEg{%3hw9(re`^X`Fg`C9IJaA)&wQh9z_ZhHB(^RCMl-G+<yGF1BW
z7+nE|-+qw4ALUsE(QFW`y3*`it$Y*jtZ1zgPkYn43hQKUWmd{`dFBSD+haOGW$5Ku
zA&@&|ZUM;On^$4Adf3@>$Q`a<P$BNSO#~2+RaXMc({lUYAnKaMYQzA;I(sd2=k_KX
zu<xfP49NScCY&J0VqQe7q*o1;ud1hcCFR+wL|VB=bYVvM_J;dA-y6oRLzVIcRO6a0
zN&V}0h#mRpS5xd|y4REJgUVZIzpRA#N;Q!tx(GFqCb)7nk>YtUH<6<IQa6!ed671e
zVtC=X@{pVp9-~@J@fmBOg?0S-OoHco@t%inbM6g0!%_eD2*#~-SA!`y7L4mdkM@{n
z$u-<*#4$M#gl)JPV^?8Q5_C*trNBkFDI0cdd=?DLP|1&7WSo=$jmDb<JqWB6s1YSd
zg#nQWDDEPYYvG21kW(NH2$a*t1h86e?PMFZX=9DFFm7!Ed|?dDU_|A>MSpCYT2yRR
z=uVTY14$(=1mN%4m^M!4ujNiN^K-PRwS^gzjOIhBFf3&yO1di9(*To#0FyTTr;T}O
zBuPfmX>Dq+i@I3e_-8;GDxHC^C#JrG+-V5lR0tP>0lRES0=R)Xzrom&!HsZqG9(*Z
z(OG2P#RQYrsYO-NC#-}=|2rjR*~K&&r^5~+VMEg_X5mGHU}I;45sV8Oj6q7?gy@(N
zLjf8uafHw`zri(*>pSIMT$s0BCxE$n9GOPo&N^v#?c8^Com9mga0EzU`JQATR9)V2
zNN_cgRWgbJ!+3~v88%WUd}@euj9@vPJ`ZjqG>ZU54_u9ltotwq2`c}+hv-k}?VQP5
zHJwR{r?EAL5nT3TPgWBDeFI#6d8>egU*B{6xv<i8O*jPB70bXbO}mOt{}kH>O!g*O
zJp$|&{!9%Hbq!uT)O@l`FhnbK46&QB6Vi#GX~;z#uTY(yM}sz(!;)sfIvH6>JTK7x
zIb-T!(&Aes!-A(R@XInZS^NM^iLnrAhHT4#^73>|+wFYq47@~5+A$P)me{@C-Z>fP
z036f;fwRfv$t>#wT<c`(g(a)E7H2XOOkf&yp^9FbB!P<FqFKJcfGyO_){;Rf87?=Z
zT9yT$fTOy&bZ~4AQXm36o(ZP7DIK~$vQn@B_Eal7l#qpZuT#>pNB=eDj0q-#w<tOU
zq7<fqAwoqB2?!|e)mLrFf+C`%;5)-8>rFKnY8$nS<JHbhlk>uQwP^{3xinG0%FzOG
z*sXO;_^QB<*HSi)wSg~=B72=(y94F^#weWg4BMRMAR6O{(PC1n7nc4K^h3w|X)NjB
z;2gR@xPWtWO$Nz=(E!@?`fKxHJG6idriLmv+v-uvfI;(gG)O9I1FZOv)7D&OC{-YD
z5`_ybMaaz3wpTe_!~eCDrAAs&kq!X^+Z)Z`5amn_II0Uv4Tr&AVnobTfr?q8Ou@jg
zu<>jO@u?v$WCl^M5b?gE38ww<Y_W=CxD@d(*}|iutn~8SoH01<G*e`0P13qoJqVcG
zkxR@aW$?2}s-zlkKgg*raH)W;O@u>}H@V2LQsBxuXQtoyuw~?!k~$&P#95L$0(+Z^
zaYsoyvs61$rz%~Q7K|2V6~)gO3!nG!-uav;9VfhNAFjklWV~Y1f73v_>6yHUihat4
zGk-ySz)L*8eJ8?7IloVG#>QB}bYYB5qk0NvUw!FReK!dXNhTqicX5{gJTr_W2V_jm
zi08Cb-{5Ky1Dho|>J4sMR5k)?_9thvA6#zV4&{(=MZA!Z{t%qA9|TdGpOLwDDy_+1
zGGUU8q_<5mjD5E7Xq!6KNRS<|I7{Hp7~VgXrT>k;c6jj3#y7Q7=tuEkBaJT~+2QS%
zO&bniKzQNS<Db$&dToT^rTg%9;pL3;@B7u$oo}$=-Jg&njSju>^($&t-+3+Fhicz~
z{hywNk`L8xwj=9Tyn^?weD29K@_e^nXm~ykX+7v%!QBeYPuK38YUd;K#O`xSilh$c
zPy~7BAp8gr(oJeJ1d|Ci?{_-y|FXka6c9ybr=39R;@P=V9`q6uSx1tP-oJ<C4YpAr
z;->!&l-xS^g{{^Jh?kZg01bR-Hd+w;_JzNkxsozAx7%?WtdvOmtwXDOjK5-f=hy&&
z(=iEs{B7T^P6npDTgJ)MVf+!rRct|FSG*v}v#S{O``8<)_eGyyObx|HJU$mBA@6&9
z=U%i`^Ww$ENz(~U#arVWiudL>$2&W6zu){8dr_?7luP)PVViE9yli^l@ZC!aie%5F
z%@k2FPL!rZ31YEtVskqh{VHy`MDNx5RT|#KC~etx029A*QypfWZ}2)?EQem4{ibM0
z>e0yvj}-gUsO>9o{>Ml@PVXL%W&dhyQ6oh+qG!HWza!@@(niJ6k4F!ZACHS8k6ePQ
ze;U3#HZCteUhw{!uzs9ad&mv^Bc}4}G3)rz<ICf|%dd$qA}6clzuv}r&96T?$Nk=C
z^mZSAzHS}Zz!wWW?&YPS*N}1|S&OrK6p)7AS{$p?Oc?pL3How<75L4#co3WSh}Jy$
z66s9xjuFL|t$MnQKj7hcU12kkjb%s72hl8p{_4$v?-xY~4qP;e4J(-atFud+iycjS
z;$Lg#$cBozn!rx`jZNC9rTH9bm+8*E42Jq&pRx6%Mn)KR_~MD>(&`b=xR3JOpB-;6
z8*~&kbr|kuJc6lR<{pkPYJ5m=Kjy<)${fy?diq9Q+TMwKTwiY;-))_jI5sgH$5L(c
z<C=@a*n#X~X>c4U7CZ4NcxGP_K9s+ljg<;Ss$$UAjY@~4lzx!w(j^j6xGqKFV;XM>
zfzt@ncaRHOFrP`n&&6LhHBHjjv&}LE>H?Dh^6NHJ>(~e#ryn+siYOrBFUN!elphwG
zi+kCHv=qY4T%*J5l=4Lwa~O@|Of%piyw!``sS6+N>&D)iPMy8%jebYv>>X%Z1Lh6O
z=5Y$;U?B5a2?(eQp=H2VoAsaR$9=~x?ivrl3?wv@j)F?PiHzcCvM1&UfrBSCv!g8K
zkgXHp?O$l3AAkyiMEk>_9J0L;98}6tI2>kC-d?s*@dJ7NP!Dv;C>;5ysc|TEK_ArM
zZPb)SKh!`rYU&E#%;irn)ZjUXY$~ali%&1q0^2)ks(9cpHUE=LKXkb%3fcqmkLGB?
zo`n`JkONwm6V1?{fhf#eh=ElEW-bB%AU4}sRx^tdhVb+cnqiwpRrf-FL~(p>gcc4&
zb9jD)7GkZ3c}77C_Zj;Sh|Qu_iIGuD@XhU7*%<IO<EAcf%#$QeC1hjC%`c%6A#;Sp
z=61`R0q6*byn_pps)13aUUqSH_9~d1E+Fr?DKkW35n$Ce04(F;->G15o<nD0)UkDF
zoJ{L;GZ~6;Q{Aw_7igS!E3m=|bk4gdSm95`!2>T;&O5_^C{ez_gWt%U!>}7zp$gVt
zDiBt5P9Urjf5U1HgjM2iSO<ZyA`t^&9X#LyRxuAAI0JxdaIm=qLhONV8y7zSLnQV=
z;anm%zqFC)_aik&PXhpsIl3^I7(qp%zf&=eV*^5rKp`PZj7VXQe(;ZKZ67bu-^5Bi
z$S!Ui7{!XnGsw_103lw!-hoLWbs`ZX$i{IP0|Jx*03p7;{_C2=Umt^DW-tj^p};6O
z)<LLKU=$_SAe1v8D!&9~cEC6Y^+e$eSpkOBgA9Qi09E8K6}^g;6L7==kr;vu#4tDy
zLfm(~05e<8Au~S!-N4KSkvT&u0RSu>g;B5PkeKgq0REE)Vw<DW4q98qaTI}xOIBdp
zv-sv&WMze$udu#8%O;e<n5$?gIoY6Q9ZY!8613-EabizsYx(?$g<1)XXU`LEL-aaA
zR*tKwPRTEQ-jy?rkgO(~SMW&&!UP;r;(Z{040Yg;5-$c0sZ!vOLLdMRsnRS?_+&NB
zJSSaD_1fq|e}%6iJgP%xstC!#{cNgTWt9F3Xn-8uJkBi$6SZ?*fUU|{NR+UJlxzyn
z_f^FdR2|c~jg61Je?g3x`v{%tiNK+*oLr*niLlp`)i&|#3?a}%w$*-R7mLB%^kc{*
z7}F1nSvIQHv=^0GHVXjg%;!JKOk~IdNi=sjkWKpJx+7de2&i9c=PRd~$e<dJ`sQI@
zu7oO-KPz0)vJg@=Zo)@G?af*emq=41;n%1<M29G`CHqTJ_L17CnYQIO_w|u}X}Wap
zLG+K}bH(m;FPtSOes{d2wjB)*5?ouTlzZJ)XRjE^$6Fmu_|A?baT}vbgkx=zJ?tzb
z#6OmAdJp$q<MXuzB^JT8jX5Tbe%<1*=u-6}{JKKTBpR7bhiT}rx<3A5R${+uwNpMi
zwhM{WlwuH*Y`AJ415Wu3t>jDWh1vies>WGzQcVYdV);bTrj<<2mu6_<5UD&>rBe3*
zn4@SV9c|^br@CtcG^x}b0ba9k)n3_NfFzuZtg(liFGmYC0XH+1p1&fP1qEO+A81Gr
z6f%{Xs)IG|%k$`v?X<fpQFU#B;I;sih9^p8dET%p0se9txu$z5YPm4L++Uu@&qGsb
zZK5qvfm#mmCf6}Bm{R|hlT#kR<gB4ugd0^Gpogq}%YbML>Ix;el+25Gg{=NA5}o-b
zSp3N+<R_od{0Tv)Cg4KsgC<svN_KqsKHiU^1mvjxw$RzyZf#`zl8_(*R&-|TU~z(G
z>{3obco{qCD9OBGHA+<rHpB?^030ANzDyLwVi>TS+5p2lH4X*eBl~z0aK~i{3OuPM
zyP|K(l35Sx+rtTXkZ7fG(!)v<Z3scgbnZg`Wo@_Ap$Z0Yyg(Iww`SvN3xZ9+RhK1O
zDG%!X)45^MVXyAgJedBJjTVc=E3kK?zO7T)EnFypL!{80jPzlWtyAe^xGuZt6Mb^(
zxZz)-0E*=kMY~TlIe&rvDN)C29sqMxpXmQh)Ulc)z-v~g@;6b}Wx@o%)%Q$upAywp
za{g*<=3k<AMF<MpN=%b}so$UH{7V$ePn~~>0w@hnl*;p*VbwLfe~DuFStblH_n+td
zPokKAmbL7PB-gdk1Bn7iIm2E|&K@dHiJDZqWjL_;m#Bc8h*y(p{}KfjdGcxU$tN_=
zr$puLKPBq2_bE}HPl=ku`=3OCMF^VnO6mzOr70ayb;XC>3OX0StjC`OUty015T4v+
zp+glU&^!&4`$|X3pzj3;I@tc^=^gubCm>JT7;gbe<rAfXtz>I<SAFzz*07X;@@_tW
ze%n=lo!U@*2B`v&xn1>?&skwUb?WJO#P8JA_j~(Dn{cyBjl1+e;$d_}@#*&o#wVO^
zV|aEc_c1J#LBT=<9mY@E&|IIi0Th-eN`-OB7XGpNXh8O`R2QHPKnaf3U)TQAW^C2V
zx<IUh>RPab7yGgx;&nCy*?672dG%zt?YIDMxc(;rV%ULMVwhnnm+9<o6yO;32Lok1
zM9#{vwD$svKjKYfdaFi=Ileo|Mt#o0sbI6}Eqg-AkDO%xZf&2l;%9g5th8~a0Bi+d
zY5<r@M~FSjM~EGPbpQiSGn>^;A=}dd_@AgkfU9Q2CIBdpK%|PVfr_CA7%}%`gr>oG
znA#I64A}K|a|diI8(EwNDn%+65X2~!_X59POigW+qOHd%TnVV~@>PD+s{H6ynNyTn
z$u!%3^h)N(_?AXR3z`<So{Y-T%d+^^ZhExw4`)nN4vrcRy@u(wAZGoq5q$+<&M1XE
zoI+gd-Wo*PfKCYKs6rlKl6Z(73b&~yd^9v!oLZB1GED6W6;_9j{=2yY(`ATD)8ZkT
zDBN2BUm7qWOFKEJ2Jiw)w>03RTYxEwWO3kQevjM^C@4iNZ<YxmxL5eEb|F61u4HjE
z5KstSp|~ukKs6nh{AB?XbiHh~H}i2zLnM%yi*T(Kdr)<s1pkjsDuD2}z?9aLdT(`j
z9>0wqR8L^)70OfPO8&2Mp*&SC=Km@e?!U^l0XPBJ{OKB~T2i#C7=hTDa<r2vAq0&;
zIGO=#D-lUJ09$f^Z3URB0j8=DNp4I3tC0T%trU^ujM+Z}R%-%oz_l(D;jP^G-(ZAk
z0LDG(p~eF2{ks{`PRcR)H*r_y{TCt2e-?9}t3NsNH?V+TgD+@R5s*bI^R%8)0E9No
z2xS)0AA=dNTJc96aAx>lBP#)GN}f;;z@op~8DRHol*VG9JU&^@!R#*!q&mLjKmRHa
zNgRPGQ6_&9aiF08e@jrkI=sxMk`Mv{9`RTFm9^dacX;2j2sB$FK5+iivtgyqbh8*3
z3MmfAMg5wqgZd$6L$AJgZ6En$_T{dq$|gs6+0woZ#i~9Qqvy@Tr?>*F^(2KpQJgdE
ziUq4)#%p4ZNFQ19h^MX1G#95}!K!VnA~DfPj)SCl*_Ti?Dx@aik1&xk&F|J>B)q~z
z9~MVJ&-Y8~GPot}E=DTw;hS<;G$AE@;->s85ZoSrLOJx`H6bFbaZuM8eiI5gbQMF4
z0(}^VYR%oM6KpEBQM{lA*nA6+aNA!|#vNoY!H2KOhKl`y)FfEj<H^x*EYUgKIg{m4
z!lUSiPb`=0I|`P@CTdJSm|XKKc88j(<DmKaihWu2F`|rqmU4OwMnDh^YwfD8G5iUR
zY%?y_lizjS3%T2D&b&DLK9Z?kYf@~66hNDR!Mv)(v*6LR?aJ)Nf~}sRVT|e16z}8i
z>*Jgw`b<lf3Y-6?!4teRF@*VrkL#oT@#dP-=34e2pZlJH3U`rqk&gSrJ*&aDN3vdz
zXLOjO&(~>`8Dc8M+B(`qJ0Qi;WC}*!{IPr$&Xa6bp%Q!IS>i1ReVA8@$93ybzU}Ub
zF(OEZ_nd3JMguCET8`GenFCl_`yE;IU-yrF$E(-$xnBI)4#oOe^R_9HOHX}X7|t#2
zj7u9Qg|fUzXDQLLZsPpgt!p^ctZ=7h*ICejCrD1&#k2^qUm8&<Iqjwe1r-G=mk9^u
z6+RgrxspHoD-HsD9CBR^sst()7!%uMIi$E3xGIre*p)7pHA>EFgN=&dE@+R2%OVez
zpPt62<Hh6V3BbuaW_T%BZ)SMGbY797XOOhDjv1M@X!bdb54i?8&D4B9`_p57Wg&dK
zO^LZc&Nn00nkk%aD)46+wX3`<-USU278MAGaKCw9;$Bsxr;6)xE7>PwAg8Lm07e22
z7%<3bZ-9f8q=LRjJ_<~Xw|X;nguaZ;^?s?2nn`}%t-L!~dx#J)QTONS=vc}%K#O?B
z<kd`k)yg;HQk}~CyFXvBhT`8l?S09I_uw?JV~LRfH>8wHY;U-Fd$_*8dYGSer+g*F
zV|@&1H=_%9a6fa?E=3Piq<j3~ag2hueU1=`-X-DJ0ww$S`IiAL_*-fRQex^&gUFfH
zl^s#mnfry^wv~lte(xgIyNQAM4uiFO?+-q3p701ayEl{{yd7^hw=oX#D@abyeU9Sq
zk9-}=T7@P8zv$i8tQ+;SeP3O?dQ>pweH`q_YX9SYf^>I0wiuduQE~QsUu&M&Uip2j
z24kd%N1BhW^7M<3Es<vmx8B!qdDQYIP-&<JdRVF01A2Sco?E%Z`)<VW40MSO!Eme>
ztHN+)M?1`@T-i)UiAL@a63-bUUu5{53yzjAC3z<AH7TMqhxO8RIyX+>^G)89W1?ls
z36+Y5`*khl1bKc{f+|)@cLf}#fYiHtut5Zm+=%!D_xy;xQes$e4)JZ8P^xov_>b*P
zQ<pw10q0!tL|QQOnU9Gt;SxvP3E}h9C_-R4#J{)^#c6~w{o6QiJ&-v&_mB!cT#aNP
zp8nv9r*PRYo7!Hzd3$$r|LO8R(fh78M?^%a13t&siG5-FO*^BL${^3z`x`ca?R9OI
zYSue(p?S>&y_X7abw+)?onC(>Ol(5rRh_k{eW$FCN(%B3P#=&8-rFIlvw2=o@T`LB
zyqSq=tvsxyf{LjM)y3IIBQJBLz<Qv7VI5oA5I;yr6n*S4vS36H-(amEPKa}<fnoTU
zUK|lPU$Q-4z~|Madt||Y9{%gic9F;e{p{>E2IQ+`jK51J^zeOvC3n3)bnthVx_4wG
zN-=G%m5uNb)(W7fgu&|bb`u2*TKzQ7Q6=q#q@3>xpyz~ram@@xy!sbJ!H44Tt<b?x
zoT$REKN7tsJLpO7V@vkyRAjjZe?WpAOP_$>CW?wa{vNyiw!5h3{aplQ`^WG3p|iQX
zjHS9aWWQW-_>@P24LTlf?+u&+KIscj{Cud__s$p#mlMl1uy{B3%;FI(G`@KKrudz3
zRM&IgI|=j)sH|AfVk^A4UV+d;qh(8w{iAtvE!^o2iITO~FFypF{Yl8as%RpW0MeER
z{sp&!SmcsGs4ZdXT*?U<Rg-gA%Q)rv5t)MZ?E)MU^+`U)Nxrw>3n#4JM1j55tPe~t
z!k>L+`88?rC6sMm#HIanC@u-DYn=0N6MyJABkhm?whBY~e&XFBO`pJ}_IUn)E2c=b
z^MS{EOj_;;=eUcdzkD{VfB9_F_Z#mRSphzs@%#x_Odo*H>pwo{?|=Eqc>eNLrtg2d
zv*GCzK-V5O>2$?JsCI_B|Bt-ifB6nY{_>rq?_b}Qi2!^$<0gZym{I_r=Mx_`xs+a(
z)UB&vf-}SF^I)CTBD9Z}d+PfR!%mnbb^v&fSz?$ig%Z6*hTW_Y?u@)75OvQViZdV(
z<vwoG>wrm};tZ|J?g{%&Ci@?s>=xP5CfRH_(SBUFYIaW($CN<PSh!MXBkQ6-QI*a(
z<@el8ve%$@<M~mtrh-N6TjWa{<oC5S1fjHL?kw^ert(xP2$8g93oP<|7V=CrEJK_m
zV<N~Z^{gjdSSqg_-4h}P64hyQXzE#4MQS|~B1RI`4LuSpxVsC3aZ}9ovH~eminaiG
zv9x7SK!&M26R+ZHN1cRWX2tp_Sx3z71iMJ*)1Cx%GJvm+MkAb7$G~3yjiMW-9WYT(
zldP3uPF!{4O4l!stXI#f+>NF8+HnEUnxc;0RAgF5OOVN0)?z2Wo6M>sTPTg)o$^m!
ziaJ>nAdi+HkhM(PPQK4lk%>+3wTFdb$`r%6#6p6-BjyJ{N>7TqFd(ItmLQU~Yysf2
zP-LpH1AOcg_^WNa>;I{ZAIU_qsZZd>M3D(o@AVlVuPa5J1(4T3OOVQ1)>cnDVvWBK
zvl~j`4;{qP<J_vHr6$+oWU8Z$w;vj(1lXwA^f=FlQ&<XdvZQGAhb)CccaMe!{<wNT
zi{3DB_X&h}o9zS}-hLdk9lrf&de6%K!AwG92|kZNgNK`*EvW9$RmjEpC?Jlrph_2i
zbmT{bYLtvb!4M%FDqo&yCKqAwq~vk~Lt5%GK|VAxKpKk`p4}C-d)KvZubyG4?tcl9
zEb#1v;7zA5rp`L}KeYc>6dWNOu+X8^pstlA!j%PeZ`W0Zp}zn&wH^TiRJE*BFX$7>
z2oZuWoW4-uo4ty&Hj)7Wbp5wlc5IOa&ms$yT&SL-!Y>X@W_@K)_K4g{YGw#po5_)R
zMRx<#Hvb*7zlDk#C{$;FwYs_u4Coe}rI7)zQAa1U+8A7SJFWNeZGe&$H?760ix0e@
znh{+4uTXjyMC;<W;n_3Z%ofOO{*=yqef>|#F#XcOUX%<a{Sr_P|MKs~{N)dDE2wg(
zUwXY!A`{uY9?n}l8vD1ZCaE+szxjjzH&$8J%~r2&gr+_wed6FQd5*dk-n5l%tw@<l
z$cpMqzm(*}7P5CK(<L;e`B$s)^nY6Wd;huyh>mb8U=0@1ZDhF5wpJT<gJ#SSfqzQt
zohdgK8_Prz26y1uD=eb^Ex#Mt*35u(d|T^@0`?@^JT_E?R*01Ic|q7e<1b|>!Kk{m
z3`)BwagqM|8Gf(QjEz!^eLe6BD4W!WzS0&e$yXbBhbQ=$nRz7KZaq)jrKgf>P4WEp
z*e!%RFzG&E%(Cj|hIv_!p=*|qIGAj=Ab_fRo8Y5YPy-a(n@FJ8=GMV&{KmjjopRgA
z>lJG35~^kMm@ye#^B=uh<QpImnOUB0N4QF8mV6}pY1|IHnC=<$*Ox=s7SYlMkv1@5
zH}4StDD)#!?GOC!2flWmiRaiq-Dcq0ZovKD-U^1@1oPg2=YSFV;`2CSqu+b#9pbG^
zFW-$_p!HU)x`3X4=yI$e#gx96B)y0K&dc{K<d|r%sM*K4+$e8l?_=}cEqKfRt)L%K
zM`z36OC+3*Nk~WM=fRhul)u58Ki{oq9T71QwH{V^eDHUV&&1s5d(M91FeB0Xys_(f
zEif_}{NS(Tv%*($2OfU**7Hq{5o~SqBZB)GTGaPt7wj{%u`9IZ#L&f(T^izDN8zFE
zWD@$s-xG_gcO&jjd>#>2?K|w3@0jht3sR=yXZ8GE7kjo@aW<ZTB!263b3R8z{8xUA
ze@gBOJcUp7!rZzxA5NFYZf`B<&T9z|T+&1)jNnB+_;@4^i<Evf2!-Uxt^K?MPYD0{
z{_Ce`@5$BO{n*XX{qalF%^W1L@B8x=k(uUv2O8_^fuseoTJwAzhS@%H^u`CvbZ!Sj
z=;%xp*4UE+^F)u%IVe9p0-R67FQq2>iS@=pf2BH3I{G-fUYrSPnCy7CM*7frMhOcI
zkBUw_KHU8n_#SD5OZsD;bAqqKXJNF#Dl{ulWxq86Eilm6_x&qw+V@)?*#viTzx?oG
z8}dYOvTk&(eu}Lfbai#kPrex(3Ul+Z*VEfEaG$)|CFC~GJ?kRmCxW^7u;#<N3eJ8#
zW{Yh{!wLB+Y>u*85xZWn91!IH3uRL4aj=;RjOBXdMWXa2|D14O$x}YNt~pLK_wqjG
zfVFzM#H^V%#{0`ocMkt~`^T4=1<myQiu7gjGNM-SUd)W>#J&cMs#{omL_ZV!Z_fUF
zyE(c;py`4HtyNWES=DM;`nA-UO=dQXwEaE{%Q0_aWAi-^gN7<}RxSc9(-`;>od%#~
z>R=(z@V8}JKWs6Ykd!>UKLWH&T^65OrYu0qw5)<gi<j)MwH|1h0s}&43!r7n{M0h7
zwp)0qX7XEq@u_7x{M0f{23n?Cb6UF9l|ajM7-*SRR{|~5<p0|;rQvI>r@?3)!T?&P
zGy3U#NHE4}x?(wz)*`o`<815ZdJ0>)KKAYVsa9fbA}SO*TdI!UKzpoY#BD#7Z!uBa
z!jrF+x^?Zcx-8VxGxZWt3#|0P&lz-)vtI637W)oU|71pwhx>N33O?i4F$9iY?6W{;
zyJ)M%b;HY_m<%ey)s)lIUrLgYNrQ4k@$Q=3v0@w9-Our=5Z2ZaSPSs(F6@ef>nW_5
zO9FmzqXp87jS6nGi;Q&t&J!Efz1t8Q%J5S}F`PbpN6UG8Gao!E^jIZ*O-u>JZCfLY
zrtJDY)&a$9E8;T77QDq?2tK*OUnmO+?NNq(op%^c-k^QvW-3UT>!zt9@Vm3Ylhd6(
zN8I~7z65Q3Ih`I*o?lXh_fS@XviQPtp21O|{rj8V$U_68mWSytbS{RT^SBK1{Waf+
z#WI=WDnFn#+*zjXP`1B;mo0WnjdTY&5wFOvXrWW6OsBdNY8laW3?#;*U%LOEVWM;k
zTa0O9wMSa;ab@*wX=x?*<?kRddb~af{q?SHOzh+D7xf>+XFs%WS`GkD9N9OJ+H*{Q
z75eQ}J#&Pil6ZZ8bo7UyT4xE-(8*z)y+XtN&+_i~v&;*u^qkYVp_$=#J9FXHI_Z69
z*Q;ou0^f@pywfis$<}k3b7V8)1fRMy-Ksg(dikP<EWcI>$#7nIvpz3seU~w<^kF8=
z1bFN!<Z$2RMY^wg<n0TVi`bhz3dd2gtu)_W?#D2*2b|S=>X_RXb{DY=dlaumJM<!N
z-E{WWcQbuc%^nP5Zr#!WB+WPV?LTC3Z`}f*m_D@Yj&=-iK9aBBdy!rIbOaFYNAiJt
zFPA5T_mO=0-V6WY=e+5IPs;7D+r9PuG~Zma2cM6(zXbNyOEUi<O}D=Qi6v=|d4v}f
zwWGeBe2;Jg_ef+H6zpTZog9yFtN)N%0O5Uv>$?yAl=c{B@gVi}7E54HYzIJW9;9M!
zu@0XQ`v<9}TP(&sU){*t-1^bSq<0S`WEWz)X^)IE_bLK=z6yMgYB2z5>@msyp#=Ye
z;+yFMb;>Oe6Cfaeqe1=gHkN-+tRV9r(sT<1MT{z~L$IvpUQNCJwxr5qFIQ4^%y&M`
z^ufj~<hJBT*<ME?*}DfDwes5vyz1K$WR{Ed!x+v-U1cAF@3UHGDn11Jvs#V-cJT!M
zJb~Y{T6F+zcUJ40(@}+X$=3+qqY8ciI3HD{J%NKKumAv`qY8$SujMIfMty=;8utJY
zxYEc1fbc&cBld)eUTGYw83hYm0WT|hUV`Fqy`G!W@MU7=kHVyA6>ew9`|G>Ct<;ON
z<zF3i&%b7^`+e+zq@WK^X#IS??%PJ5+i}ZS1@-33rYWx(%9H2WSLYtJAJuF$Kjvzz
zxOjYU|6so}zP8Hxg&51tvE!N-38X%32Qn78fcK*x!v+y?YyHoSjlN}J4cP0wQuqWe
zF@njW*0Ro^u@T_R)}HZpX^m~~;#dYufrl7GH-?X$$z#zeYVC}KI3UnHM1i$^xf&5V
z<XLz56PNOaWgq#lGcq&CrPnzvj$FLq%Ux51)c!i(qrBw7mcDJS=HR}#(BtpWW}=$s
zZ~JQ!6*2m?tZcFq9^|jZ&^OFsTuSyZds%O>i=sCKMLH(nZ!M_gMb~TL`+BiN6K_-k
z{l0e!(}ZQ?O^2HqU+1t#V$L+LkkeNb)%>v)ToX1Fov`v%O05{`xu%z&u3xY__YgE1
zU`^Om%(NKZ@vi1z>$_fYy!vv_t!MQ-#z%XcaAfgrc`dcA2$oA%aj0Y0JoAkyeXhof
z%U7Q9<m0cz{m`rL2B~LOzY;^g&DtS^FS6!xEuMZfwtm@&TtN2B51;IJsS3;IPqXxR
z-LB+Xxj)J2x3A{Uw$1KB7-#K<F;EDlzPE3mWZKfdN0w@c5u}k=kUsf(wf*gUj$?78
zWYs*@EHF!%-0EWD@ou7I_cC_zGIu*5=ljq;Zi~hN{vCyU=jDxin~(pBZO2HX#~m-v
zwBH5mAz{>y4z($vnGli4o_f=X`ncm3;N8K*85V=9ZIpVoT`6SGgT5Rdxe9m<=Y(y6
z{g)@09koAXQ0gJk60b*gB$et@Jic~H&{VEzMBo=PttvD$kt#hwX%KVQ(QqZ3TifhH
zG)_4Cm7I#3{AIr_DXU21+w&hUuBysEn7Ey{lwa~>{O};>WyTnse;b@KejHX=@3C5A
zOE|Y3qtQ@Q^o_^ihfYY2_Q)IK^+r1b95>efJ15ZXQuAO4C~55bxJE-Q`LF5>TH30b
z{5QYO+rNff|A_qhwGpATa@VY0p9M*6cPd8g(JZ5y{h)xubur&X&H!bNCNI6Y`2>ge
z&4IIrm?3LUYV*vNONmj5R{YAu3DH19>y&kc*MbyF&V0Y}Yhufb_3&q8&u6Fuiy|GH
zuwP0Zf9RPq$1<I#rAJpUDS{cdeU7!CrdZz+k;QB<lUflBS?=53HvgbSXy+@P+Sq2m
zdhvglddq-1dM;WRx8m;Z4#nNISn=Xe9E!Wc!CeXzKTzD=-JRm@Qrz9XL!bBF`~6AC
ziOfpY+Q~4P?3n<*<Qt$Eowtdfr5!O?#RczkTA@O13EQ+EWQOf=TPS@EPh=8Jk(s(R
z@2BO%F8yM04k1!96?<l$@Z>zG7>tW-{^<v+bjyK9hS0L0(v@ju7R`o7=xRO5<c=gZ
zN!DN_>G#Rn^R+V%*G?l(V#pXv(<Aaf0!qleryh>%Y=W_9#bUyN2TNaZb|&XX`+FZO
zt97jzmT%e*Bu~+Sy=eYzb;k)|O<l+6u(hDi1XwVvJ$-&Lh83}$57Oa6kq5RN8Flub
zzpp?VO2d|+lJY}Th*d^GY@eIEweJ6t+-nOtwC+^wr4kAKBRFR|ONlaWG)sxtqqj&k
z<n`&ea%uv?Kj{&n(QxYaNQBN4VNvNa#@K7!cF_DW{3NUuqHS8?M2P@_4&n7vXGQm_
zW#}x`dsP$@<UL{(6Il3fOGQ!K4rvw_8mWdMTVoN;U)4SiMw+j1oxh*+cSMvXUtfFv
zklg+9^D8pa9~i|?xtzA?Zeo5kceKH4lD4%0zZiAbu8v9}POioi*BPK<iyL)^*B+QB
z*-E+0aX$KMiHCwf6SZjCmb&5lOVHNf^pB?FA%AD&(y~kFGMkI6R|=q^sy#A5YdyK+
znql<?<A%I4aCp91ocQlitth4@|EAjmbZ0)ER+qN5kO@{(97D?M_1X;2+oSWZj+Sp)
z_j@d_%-&uHM2-uy`36CZb^QiGq+xq@$AX=2Or4_q{&E>(kWCVS719h+e_%y?!`vVW
z2Y)yx<H&R)H3Y~lDIAnGE!hwgY`^Zhe!GDhI2WWj)g^c4fry)Nb&-|$vN}hFOzmQx
zB09RJ?H8i74xYoc#NTMMd6NlQkklFUiha&1HTaXL%6ouzbW=TNhZz5Bu&ol(VG5@Z
zmqn)Ake-)^{RKs2s5Go_pfU-uW4lf^@m=SZpirtk;v@=mybKDe2jT$+U@z3dJV)_M
zEGn;a49!p%2%7_>C3x6j;lU)`Mvn8Q`O|VGgFXC|k@F<|{+0o;lmg0o52?IYD%B7_
z3`hhO;QmRxu#JYBKdq$c_~1YyU^X5_tlO#0kQhKJ1Cu6v=x<+FT4*#V$WIEo<#r*0
z{3dZ|54}Z#JWq*tKU76sEdv`ar9EaIQIO3ZgR^GepD0zD@gOe!IqCJK`s&`@T(zRm
z_yn-$5Mio*B1no%%dn>S2x>=1ql~<U^rd$!jdF+BVV)BEa1-Oml~LG~FqC{XMqcrS
zjBeyq#5dNBfA5O>ZB4Nn4rDgF`j=6?`TbWb?)g{DgAeTojhuS_27P0_OrCsuCBr2=
z$fI?JIp{9A@YejHQ4m}?ottW{CSc>uxhrWMA{aF8LJb)*(y)vR@$uxPQ)Ih`b#X_Y
zcepFXXY8PF&lM`9x1K5Uo1qrG%83=oJ!3&iCve^B8Ojj&iUFnhja*kP(gom*>(F|-
zA}XGUd>`*)GdIifH#V+-<wJ8cbd$%02e%KF4YXw*ub(DqXa^Mee=`q*e4>3P%}Ra1
z0CW0k{8ycyiq0=qn9RY*Mp2s4*k4KN%c*=JIhJq_%RW=&G+^x8Fka*|f=+Xkuwdmv
zc>K@g>bKwxQ=79o@uP&6D8UgCodIHK5k?c$%12Y12jcdqOxz{*hH!8_?SZ>~Q{7t%
z&|Zuqg~CvoX$Bfad6mEU{ch5ZM~!X@@$$97gYP$Pmt`^+SwEqBYRKF0)pW2T^9#qy
zr(U;1uO8J#NR#I#TWrX;3|k8W-!9j8xXvi0*i%qj-Yp)#8@e=@cb@y2qLikC?OvF_
z%Qq5zE1b<gQAb!dzN3dQ<|TL@uQZ=QnfkPhlu&L_N;#!&218qMIAXAcbDJDs0Wd2+
zit@4;EH5BXAU4acp^DejDq^zjZOj^$x;x{)nHW~f<NHm99({xgE&jRYwz4{kQMe~D
ziavmgkRnBG)5Q{+jxCC`Q-UpBj+;Nf)EUp3TaQ==n9<P%vGPY$v`ze&NQ{@R_Q*_4
zmPpWf<N*#l$yYs!*-j#H0ePKHTr(ogE&)&Tr0=|-HPVh2{V0`)f;@0qr72&6q>tGe
zRpD<YJC`?RYlsSEM3ISWR2ZDRv&PKAVBH|+SVRZkUe+eX>gOm{6+@z06A6h$I%B}I
zZYgxEJ&ACSPcIw>^gJ8Cltda5ft=N`xWI))-@pXlUd5(~0BaPRit$IC-`Wm)xF~{Y
z4*j?&mnH%n|L6Cz2_Af_uhzXDau^d~D|C4pn(32`vZ2i3PO6f>dXr5(<SgdUwIffg
zAh~nH&0)`zfM|K#^fAPOJaZqHJfYo32-%lr^H2yAj_|lp#KRYgXw}TU;`<CaJ)W*C
zCDBF8XC-6>DVt$U<69UNgDY=}D{rRN;$hSmrp5Ftk3NelsSn<*+ihesEIta6Vi-}F
zTf&`!d_ROC(oL;R`Zt7qAz~zMdxg<WDsV4k(psW#)!;jU;Ck=WG?!->-b5o^H1TJP
zRb~9>u(^b#l0yqfnG6F4*TN{!Yl<C4h`&U)LI}(x%96*vMN1G!Y;&x1^P5`q(IO+}
z$wcY9jK!d#Rb}&(a9I35grh(s#&GcRm?buHa!r>vBsW{q@EP0xdamVZ41}%YGaLK>
zzr$&0OBk+t8hD=6jYeVV?g^ComlYOnKW0a`7y6le!o!p#(-Gx@EgEr>eRfJ?@B|l)
z%>l*mOL(opl62uJr12M|Nsd`%&5sOlw_9F)>pugDJlBdZig-k9$svXKR-2_CYREYd
z-+2aK=0P`KiCCkfpct6Cun~{;`44|=I?vKF7<%C%;woJ)xzr>m3(4~%tNI%|1(pVZ
z;P!4>0KchL-(S2etD^XdkDiHn0|NqzqKO?G$GbAw8I5lcl|Ij2`~z4@_1UStZi`}~
z0=ijsKr$+O3qAyY{-0n;?;6m**RfGfR719_4ur&*bhIeNa9^`}Wl(KUOM_lAUBkI|
zFzG$=Ut+!4;S%lxios^0d*22ax=K3rgVA*6B3%%#^Y!rBZzkp;^%aRvG`%9;6_h3j
zHOHVH7(I@t!xa3a!Pr={gFg=$5pu$9cOy=ldsB(3d*$5g8s21v{cDq>DTS3R&pXdo
ze70D?U^RF0sp$vF$Ovp%c2-L1?Z?xyZ+1mVH10odd=WK+)4a%ZQFXxNEL&)#`iEwn
z3=3hHew8_=|ClEY=qZJDwKg`)n_aOhA6+@?L|A}HD7QgbVgujqJF+ys^$wdmP6cx?
zzU8cb66!m0`{K`24U?t?Nn(t|M=g?}C9Y5gM5zuT!XQ;FQ&lKaB{9x){U{@qrbR(w
z9R07%5hcsQz6F3Th3_yGH9n9|fpt%kb&idU96FMto17(3k_dzRE9>|Y1IvW|UR!&v
zr&oTn*IxfxX-21}nqMVHXk{CZ_s{Exh@;D&`&U14QYsyV3{-qNrZYOOwr|uYju}c8
zG}Bfz^;bJa9(^QlpXHohMk04Kc_%B2vV^Av{C4}VrFkbwR0Q7d0#xs-@e*=J8-kc@
zzeG@Gomu{5xopWlg=f<D{N`wU(I{}qzL+p78M)9Hj#J%toZcT<wT)!6?V`PnG`8(h
zy^UnMeXF&NG`@YCLsv}b#Dig%@`Wl|7q3PY3hFnL3-J$a=9jpiWc-pM8M;1+x<1Le
zuQj?pb-Iv=x{%4bK{dLNb-Ln-y5h;Yy*0Yxb-IPr&5GKNnaO*6lB1mL!<@#$ob;od
zJtIHcJ5`e8x5Q)F%?bfBabI3b<KC%ll}s07;4x`HYdxW_HH(R>To}~w7mC5FcY?*~
zA>h6L$!XN|&}9K9dlaFsVsvZ4Hd4CLirNF)=d<*PdI$R6f#NBC^N?H}0?tz9kkeEV
z_$$dY@7Y~3yap2ps-cCs-MoF=kt!k#TG5UyY7)-5e}x>b@F=+Z5!RB(oK^oWD&U!b
z66;B1?y7(PD&XaT5*tZm-l~5e6!3OHiOnQ3f7QQmig*+}{Rmr0WB}E_xXkPW_Gs1~
zQX#m^5EbKuMxz?KbOEmiCqG^#`4I;{mARPmmDRgS<hJ2WMQ{in9ivaJ^9^*MQiiRi
zV}uYVl6a&hiy0JnRNqM$A>ww~;CpU)fKjm?Dt!012w&qktkW&iU<=GY!RL|np8gY8
z0=@L&shZD}ZgIqOR?R0#`CZ>nnEcQL-c3!d5CB8;t1g&}uN9W+3eJ{|pITy9G>Gdf
zn%D1KMR+8(uPT<mhiIBWlN%sR_#4k3snSvWav~4~VYt;5Mtf+A7|v~qXh_0epAb$w
z@QPpPPk_=T=G9CS7PnCi!Nk=?Hab3MVUm(7M|sj^c2!J0DseFjbh$vO5*^}VaJSzr
z{qguY(pHAJbUnpMA35EVUL$!NzoQaB2_Sgxm~Ns?*cA#YVPn>|ON2$(!S9+BKGRs0
zb@9yY!M|!G6f6NfmcAKL0TA|OH!?<j#HHT9S$ksVia0c0l#SGIOC5{A2upwXmd(O@
zm9=D|;~ST4Q}<VsUr#!Z#lWMvA#22xV$$jVlTIp|DvV!092WaWkGM7VctqpL?>^)f
zhF3bosu3kZ)_aWk2hJq_(M>X9VKg-po!qRf1)F5Dy1e4gVDHK3ExRG(#L1b#GKPLs
z>vIz$^VVL)R}%im_}4!AfuN+<`@+4Gvuh5#pC>_nKX1q8#y8$5pWoH&gR=CWX>q73
zA%zSoTB$FYf`3|1??Zbzsc}>oG%vTVsL_?lVw_LqZ@cRM8CBnC>mjfP&T$JA8{C|s
zM%LF_v5$!D<)xj}PUx34GJtOVxH~R^rwd9RtRx45+*xC_-Yz4(=O)67ccY4J&PMIo
zeKajw+sKnWt#(=$Wuv1m8a~ycJ|%N&=^7<XT)VG(N*$pk)LSW>2zJHOIy6moST>xF
z){^(-fIK1FHKJLougwV6^|{X)J^ESoW-n=NiRG+E^3Gqgd&>=|<Y_w8+4Y0;aBA$f
zqEp`IgHLqauZarlMZNA-=Oftad!98+RCgz6w9*c55pf@3PM%;+K;bhC;R6hzCyZJL
zjpSn%=APHrq;px7b(+0d?#-dkhR)jrQ;p9N-suXvD>mdCW*Cp`1jnLgnc9MrnQE84
zb}2MMElWfPp6ELKEw{0U)=CSqes63(w&b3di0`Q#-huiBJtPHw<FBBnEA#7ZMimbk
z<`R3>1mg=cm(hP`%xw%-?xO#$dA0=`K0;_@p}j&I@fs&LR?&qXGC5Aur#%ebV7prX
zlxQ>YyvFy0MtDzMXNUVX4EvtSxtP!?&2#$G>^xQ9C#;i)N2%)u)FS<>RM%r5VF#Me
zlgqpQniC?N$5v}Y#Rv<d*OApd*X1I^=Dwuvd5#KE&KjSHmy7@1F&NP-cv{E%9?@+b
z_N)p~(GmgAx{5kekqT3h9_`VaVg!QC>lFgwOyZ(!4|7pF#w_SRIF#8x6rHskhdNGf
z&DLLz&UdH=SQfMecN+O$Ap74fv=(<LP3)(_-Run>bBTmphEm8b_;#1mf4Y!8|7=#K
z?LQ_~p=J7t;aVwV109_KKQ;C63k)ebxA0PY%#(9X<gC-7>`fu^q49Wc+vufEtAfpo
zy`^`qaqi^D0@2+quD9QSSGl!@awk~J#02)T>9EV)cMeQ<-OXxY-Kfoe5$oBRWxa7L
zzB4bst+%6WrJ3LpmPO5R1ZG5>f=)GQ&eDcY9!A|bL?qZC2S|A>m!f#KFhaDQ(SsX<
zr<`<E=Q%%+3<cyAVRJCRK>;L0Ale?W%TdjYE)M5-kbY(B9kW%MO}jT&PGoDVDYqc4
zYy#x-L(S2j{^>G$#@jyx?vOY0cvcuUiwyK$k|%B{qY#;~82n2b&!sBSda~8{^@|G^
z!2+e%o=fu#KJi&kEb}v){hs&`s`Mu@iUuWle?GY+C2s{e*ZJU&ywx_n3ZfABJyfzg
z2{x+R_{P;yh_`-Hb?~xJ&cA~CK_|DTbaO<m^2Xs&-C?*_WTjG8F;RkEulo|wR@NC#
zm%;d)4mH_TLH|wH#vF<1?u&-n)D<6V|C6>*TSJ~_vhe3R&H5|z_}g0*my)e+0xcA_
z#XA%J+D!<Z$nZ<)m9KJ9pKMqt2lS;U*p2lyii^Xvh|tnW?4`F@HyqOJ0!okE<_I$9
zilUppYmT%1%Jy9y1agX6hf|;b$s##4I`~CwBD-;CxqsymrQ$>2i3G9osd5hNSjk4Z
zx}MKokXhP1pgt|fnjNRT=o?Yf8<ZRN*HYMKWNwR64h;%#qKRrnPSX787vcCv6>yo%
z%jd2GCVbW|&l>@=vq-xyeh@lVhmQj{mJ0(<9vy72@HVBt4v1!VxOR&YH9u7e|GBTf
z6zH<izVpo?_fyvMQx^17_VH7O^ivkMQy$4?qxBoedBF?1GDrMhLIA(FShy&jyQqvX
zh=kT}p7^o$ZYaB6`mIdx%KS85*gEz_+pDk9Ra!-atD==K=R7X|Mu@yJ$Qxc{{rjnW
z(L?-@(o0^7@g?;y*lf@@Nk3wo{FIQ7IJPh)^&^HYNh$e={mN3>KH~d|lnEpG{h7Dd
z@`4_DoOR0US_tpu&dxbC+POmoc43CD!q;aVh2Uu*C=1o=kV>Xqc0igTiT#%97i^uF
zteRcIV|bt=G<v)2J`KXiPwgA(UxR{O(lL1tM?YzX+s?p=rx5J6Jrc)uh&L&Ks*Jmb
zvh0;!{-C;KMs^7vtB~H`D<kq{eS}{KK8Ze^^=UyQEQD*k{DD=gILV`F8e-91V9}jq
z(cNHK?P6JFeJ_S>Q=N3D=yZREh{?K0GH)CDtiOPg)htGdgMEkJT$}RBAAJ8=Q?uc|
z=QRitdFrsK>)J^Xc6oH|h56>b>CwGevq2Cp#gBg_$mS_>aUJaXT=yC3bOD^N2+~=r
z`FM*>$-0a1ad5T$_QavN68qk|PTaiZo3r1uWAJ0lKzdA>S43%={pl+f!l%wKUw@=Q
zYt1gfA*bvv+u;Suj;WlqW0X#<?0V!9{pcp<n-Zw1N;GkMa0@+bIZQ8-N@K~br`<{!
zmg~LBd`R)f?WYznfqjS8zjN!sC5oRMyox3;L4hK%gCHE`*-|@|I&!V6a1=>#Vxz~~
zZ8rSWTYX94-nM0nuHWYd0nkJKdrj`0d*QcIdf$~OF%|sAEBhsShpPl*sa0|}=4UXR
zuXaf(Luq4G&UT8aeVw#P%q5t`__QnqR7$na^=tDbVlIJyIqYluHH2i<N-aG0w`gJf
zIZ8~tUTWyU<&w}iM0c!8F_YSBk9Y0kFxCC-&4hz~ML~3O4*Ysy^UxYIiqy8#)@@5p
z_^u7RGwdz6;_GFcR5}(b8DS1ZD|cA&0|vdJ<Ox#D224#K{EIqk3;p8=imo1l*3Xee
z`T(-}rDQC!@N8?F<OMZdWQv@60eF2~oFq|q<x{>EdVx^~V|DtSUdOxOA2QSDD{1+h
zY64KQh3%zjDK?+^H2y>&T^nnE65f*>S?}h4I7TM|qe!l<-!IAxP8ESjmWR)w<ltgC
zb-zoqM#Z}(BbRCt;}@BQ$Dnx+WRuGh6IUSB!D3C7*mHYu2*g`CzG}Aa5$)rcBkl>a
zw6u%Rv||cp6g9@4nW4o)iXPu8+WHH@q9=gkd{{H!dWZl^gnD?Rxx|+H^V|MjO-fA=
zT)z6}o*^|Gix@|^M2k`aF^md;QSyvFD>~U#8ef?8AZhZa#%)Stlw9~;MjAWRNX`=0
zT>RyINoVyW$;f1Z+yv7Vjs^tHvLl29W&<v0Ds3Q;`e(TYtpvI1Aw!g5^4&MFn%sG2
znK7|w!lbahh5~Q8Ii|{y{+GCEyfhprXZ6gGAualekoc)t9+vD{<yw`N--UzyYuCNb
z0@~$f*$1&Rk57N!3o`8zoOYJhF5lw!crrQNM|&V8=XJZ&g#}5Dhgl>RWLKv1Bmh=+
zV>aFW8$wuw<|v4I?!9_9S<zZ3e`-)Q&B1(FyQsGXnW6e2dAhjv`PZe(#Ep*`a|NIq
zC;DA}ty9>~=;=CTgqLk5H`rMzz;};Nz-bH(cOhBECd*fJms@VMVNTFKurEsTuK*=u
z2bS6D>}R+Fu|lwa9C+3FJi-4sc%I*j4_2}hLS9B@_I9nGPp6gd4s{|qvsvZyK8c7Q
z(r|rvu<Y(B@N3GJal6{t*00=L7hAF7o|dj2eAsw@w(~pf<3GK=v3qxQcD`9?J#@Sq
zyg9S`*kZb=%skCLbennHoe_VLZtLwcuzi>7d@^ZB>-V$mSbqEIgLPiC!nM@76Z^jG
zkw#g;g3bQwbieRN;O+hWwy-vq`+U%D!mk<h^5xs*$y)!)##<7wyi-u&{qDWLy8E*C
z``hD#XM4uD@OyotZ`&#J{NCEq#@ui$i7(%E@oIr~y{ojJ!oIa{CvKsmrRPh1o=+&j
zr&ZFTM7P&OZgb%~MXyR&;Y@?j&)8+6xCVYa!hY8?b4vuf?tnZ$Md%mhRfYG|HATM+
zfeGRcpk{wOAG`%_k-YKFaDiQ6HcjJ3g?a3w!$X~xz!#e9nkOA2ki*-%NzHUTrnuxc
z=bL96-+KeU5gDG#slMzNHoc1NqPNbs-%^8Cd1vp}DV>CC-oJ?V!gQ4)alKtQUZ3i;
z6wYIWeE8D{O;>tVu54I;4Q8&hBugK&%=kqHf1CV~O+r0-s^n^15fiJQB0_WB`g_gh
z(e8PJNFjNqDYEqXIM&WC2K#;(<%@;iqdc{v1NF{@M@xnhF>wcICGpL&G|QAdR^vOE
z=KQ6o(|}(q1T?MBn!jIg0NmgT%dG1UWLsGAVwVi7Ll=BodhMEfa)0b(-gx&s)NZ|E
zr(`g9V1%uf4*6E>U3@>})xC7&NyPG4F0mq98=z(L=5n*}o$}3WQ)NKwP?O-+Y;=tO
z<<yv1dagRK6{Uvcx1IO9!fSovE5$Qwj6O!UanX$d!4|jAAh|73-Wl~wgIDNQj=~$=
zv*oal8A&7x770GUYFoS$mgL*;g;0j{+86bhOD49$hfzay48KRg2l?06MAn}12u;;G
z_s`Fg&pYG8R`pGp{n%dje7}C21db^<@yzSYI^5cV91J$6vSeu<TmmXNsO)fJ2NOdd
z1`~JYwhy_8TMm02_?`zfhyC8Ymiuy^(ywcekFQJ9?QgM_R#27F(+K8fG~DYiVOC?`
z*ZfrkS+|h*FGt)fb-z3SOwP8``Z@iCD}HUB^*Ar6pCd&kV$(1we#>yq%XI#k_-TZ5
z2Z1ciFL^ek$;@FK$!VO21}E7sM9mGYG0JW9ENIcb%s`;t{pfs1ReW`=o5=Z$koDep
zBblk%Lzc~lERWMW{MCzc*;&vxZGBDQT;u)Ax_EQ8kMD$jqCi%;?-w(b^t>@SmlBUc
z|H$(Ly{Ev<^jZEk5zy-*k1Ua)50#;Zx1QA*-oD|A!hOEBnPuvoRziv?D7BBEm;bl3
zSGcXS4{G}iX;4}{#X=?sJ6+&amb-Rn_7AOG?y4TuZxxeWyuFj(I@>e-WX4`LCK2ol
z^v)VbYu#`vdmU1f$sR46-F>G+Ow48v`f90#4tWXGE3&DtuUubwwEcKN=R6+C?~1Yu
z<%6tV&o-Ui*}ukX_kYPC<#^%AE(cdx9B`e)`20#nSDe}K*~0gArIlp8vmJR+hUAU+
zu|dwoo%=EE?LE0_uOsx!r2gPdI9RC(v^?qN@GB-uBg)L)ZR4O)B&@%aAd+^9^Xxg7
z&ieDS*UlFWucbKdxG#fq<J)@JdO89&Z8MYe8?L~|qla8nT#m@OwDpDy-z?8L670$A
z)?r63z4mMzV$V|{*9DWfbsF_^u6gTIua%eE*ExcX^n%IoXp^U1wjY_}CpV+Ju}j8F
z2|k~Ft$b3~Cg#oCQYRa^uPho3uu<H&Ya#sJOamQbzx~!{Z>Sb7D8{PzX6#$5ZliH<
z-MaLfsnXVFnx^~@b@p#dGppJ%RbGr)<Z)uN>qFs`#KNFfxL7_x#f}N$Y!cxwCNymC
z-kh1MYm|&FviMXLV2VCd6ts<xSHbnqoW;<=YOyuu?WwM{9=Upi_f)M5SC4ca&OTY4
znG?d5onX$Y;9dhXg4HWA{mDsaUi{ih2aOwPM9fqXFMPksD;KJ{;!H7Xifw;_OI3HM
zU-B_!o6AaV8WRh%4IrO;-gyv5&LtRHmaaV?+#X0C*XbxMOe&50#eJJZ@9oWJ{c&fD
zIMVUv`W(mlIdF~#o^~6h@cI_T(zt>O=5g|{S3E8HSHZdi@9W@o9p?d_rS?>>ZU4Hu
zsO>=XRKa6~vb*+{^xtCdC9XaXejY#Rjs1&sv7QJi80>lE$*$g#<o#@~1>5+)KHm;-
zdOyvu%6|2EYREEklEo{?5-kuQm;Jp<*G1yM+)W-C|Dupq_TxJmwfJ}VBxZ6uYBiDk
zU#>Ok4{0?>xO%9Azj=e%CbW^`DOEhXyLRuA|Au~n{4I)32i$wc2H??;O?mQRnH8~$
zr{7&rj42z1a4{v4f5c}TSY{S*d<dU0hY^t&>8NIvfguQ-9GFZ1{AJu|06zYm6!omK
zLSdDG44PTdJCl4Wum_Qoo@#6gRY4&YI3D&BfVT`bN&2r%QC_1Em<ok!Js_)iZ|syH
zoA_u_AsAdP46tV_93Q|>$~{9q-c6T=-2CQlR6t$y?R@9xdTr->+Y4Vudc}vcvy<eQ
z;k9JA)Yru>n6VC2xf~NW3^~#wRUi}sRh6Ymr7}b?`eL25#Yft{uvi&Fd`g8jKnxyJ
z&hRfmp)y1|FjyIaATM4SqIZ1=fWAnX3BdU4H;Jy8V-FE62T#K)p^Bks_&Jbj3yQ1j
zGaQXFPk@55B2Peo^^CVBZARAxg)>S<7d`Q8z*4}^?ci>VGR$ickUu?L*gfPxs+T-A
z#vW%3RD9qRT(A@^hZqp8MGfsEWsOu3EG09iVgV4NK-8B8q9H^pTL6G|8DbPRA=scG
zN(z+WMS+2Dl;~_c0~fTv1Rq%ioMkpb3n65Jk7S*)M8h^xt;fIyR>1|a%NU`}H*NwX
zX&J?g&|q>j^cZ^tQ0OJ_fz$?F0%8giU_VM=5ch#U#9$&^r&{AnO{0*WE!hl~q^4}c
z%oO*rrw(X;sJvf{jB$u!RJg4lUp%CSGidUE0<X<d4ECpk8Y>VqVTDiqvst%rdjAAT
zW(Z^cTdWHcq5zc@MM?2rEI#=P2d)a2D%OQ4`H9SsONxTbFr+;m9=ukT4-_;ng92@9
z1-MkQv@}%KbTkG~8azw%qk>JKBdC^c`hKezs16Cxi^}lFp(5kJUa|DRo?^}vZ8Cp%
z;I`UX=<x-moL(}{cLn1JmWn+DbKo2Ntx}Pn*sFLkc|A_>lcu!<<E(H=jMyv2k--HY
z!he~ce0DI83_jPP9vPT$pdT4568utrPy3yyyLAF$`YhZ2JxUJ#o(078nZXCsZ=4{e
z@0FVTKukCJ{m1lbCx~gkRbd7c`l#hd*UP|d=;eNa6Re3J&0<YG&EI;Q@t{0|ufJ8;
zV}H>5{*Q8%61Wdm>tPneD1IOPqaUU+?>{N@OmQm$(YVAvfdVNCAlk=JMOVr4$wGJU
zThTD~n3Z#asJ5``A-9n#qh#!XafdNNLx`+`9|4hXZ<}_G5G;x73(&`jWNl-}Ai9Dc
zqd>etFkdhvZhA8OX+Z|+TpU{*Lq@4oHM}NI<qTia@J#vYCgaN}$gtn?FIdv=!pOLJ
zKE2miJ|b)xAiO(*z68qxvW|z8o=(g+Q;>Cl$^e5eSU}cs!SZ1peoK^@zoYWr1?4|T
z<DjR48UxuhT<SPnGQfWcWYbVzK)j3cg4FTPrcqfzHr<ZS%I#dp`U7;d4g<g2kwH@#
zFjB4z%YyR@hcfOdPBQ-OLXQ7CCSWx)vwR`)5wu~BTd5Xc+e8PmgxzBF%lfm&x5^*b
z8^d(=&+di_Jf~POm=d42WP<zSuVg1IFeK%|IKZ1V$fmoTTc5XDY}G<qB~NGz69;#v
z>ZuBcb$(7K&L{tM770w$ERog0Q#3ENyIx@#?f1T1CC*>oKQ=4v8>MQmlLF2T*30B2
z*Q9fetr#ShVRQw%F}a)urRD}<j`Bx2vh>e+$|lH`774=|kIstHqP2XvuH&cF8z>}3
z+8V7p4BI&V+?H_(OM<D9acO><DgCniXxx7()FFX*=5COZza58b@U?I|>VeHiZ!dJ$
z-(-f~S3{xp!K<Qg|NP|mg!cMt%1dSD>fqA(bS~@RMk&wt#dp)$7oJB2#Vw`8IcJOm
znsxH`1DID!_V;xBzOG?m_I!jAwM@2+0hl{F1_Ab%ae3sly_{w;uOvc_QBfyFL0*gG
zpnaTbRbC6^;rbEL&lll}$Y}&sce^>fTGoj{`_y!ETn03-<K5Pju;Y$XgfWgA_o7Zy
z{fNr2<3^L=gdE)J{QuejbB+(%zX%e06Lorwi+5Qb>uet+jXMs(+s>qLHsU$h81`Vj
zC$e05h%;E_LI`d@7$8;OYrS({hj=pe3esvcFjFc$6kpBbjvNtB==Xf^;k&0%3E9t7
zRzb}eD53SAD#8j{hmX{`yb<U~_w{@eh#~lK4vX#>9LLZTI||Sx+l|QZ6stgW?2lY5
zj$;sWEElWrKcwD`pe_?6(}c3N6|1mF_-cFYB31#XPeG;$*Gx{h*J0-v+}2Mb)NH(<
zw>SddNdCQ%bTvXsDcc^@D7>IO!$@dUD77XoB_C;P4{3BBu2A^|ziM&{qYGFTQ>Wz9
zA6=9ntuHm9Dd|{Iz3Lul&`%N2FM^oV-P4^kjg4vsh6!JKZzf;eJzcK^5%8CXNR%cA
z^9^#BNdCy4CyBp@p|#Ron_UeCT?hg0{{T`|+(~+#hl(5BjP7eS5{0iiJTvrt9$2+m
zlEvV7>%c#eQBr0z08mqZh{0L*EMthtRLxTZ;{Kxu5Vy&RE++E~PlhzDh)WhwL1zTu
z=mUPD`VH?ZN=p`<B?JTjNU*Nx$iA_syOfJ(E5Q8u&P(`70%J${CN=>zbk`?|X1@x6
zqL8KJz{;wmx^t*K_Ue3S+wo-z3f#@oYdP!})Tk&r6oNm2N!|JE%wujprU-n9FI)+7
zC~ED`_2Gzc&RSNZhVj^$>>N7Ql9k9=d)!NRRyvFW-t~%IS3I(wT@HBOuh`^Ks78)Q
zvf!9ot!-hM2pd$C3-sPNsXuz$K04JQ59*Y6%72~mP62hQL%tW6>?>Hl=ra5oRUa=}
zi#%vWYZ-MDcY|LFhFhb0$(e#&qw?z*+HOsa*^76^QAmco(&OMomU5?)br_PjMRamn
ze7128_-ZUC=#0ZSBbj)N>b6vci@|?r$vt?oGQ%7#o2A10J$&xe@h+*&E2|!J0$@+=
zm<AwZ`eZJ~gTZ^-0Xxy>{A${!ufQD@-oAi^5UfmVmCgWEh6~O`qlXX9h3A70Cf}8$
z#Eb~B00mu~=pRLTRL-6YlplmR1qg%5Pk7M~Btg&-`rX8Va2`(pF*IN0zd>RuLN4Fg
z=#mZ>apdz^hn!`kf<-fea4xH2{scsNr0yc*N(9SRiL(+K1`56iWj-g;iI)c0tDt6%
zw9<A>{lzJ?>LWL_QM&nobL}Faw(~s-;7<k>MGa*w)`bcor6@>d2nW7{YQ_K+6(>-R
z%4*mG51t2atptbL{Vg4pHSM?BigzX|Yv6(m9IjXwoOJVfx<45w<3}TiA5|&ramb;f
zK!z;@-s^lcL~fW-^N1rAk387P8sSvbgRNnNEDKYuv}iO;YSx_QiZ&?qiKdaP5*WN!
z6~H_17h%R*lvp%q%<HWedrm@K%5qpv+gO^fObFPX0$6C!B8xeI1b=VRD0_YC@xJY`
z_G7+R(YCotd<a?06}2WPjtFov1(yl>me>_JdX2a^2PoLYhhGA|eh-bCj0T)2XH$n#
z@B;*C#9S>(T*X`;eheX#DP_kI^`IaK#t}t?#=>^g<uOizTOw0wBM&&R$~h_r26<#5
zkNv1ZR&5FKjwe9KnZ2|kJT@*3OmwSOnUrc?G$uUv4c*tdV7{HAA^*W>^T|kugNzuX
zA-Iak@d$oJY!SPs0kuKW!X{GB+^B^5dn7fZAeqj`B-8M}Nu~ib$)GRgh7^f5VfWOd
zR!A1f%QaymIUMxVTLdB@Ead)~q0x=J$Ug9KVj?b#Wvr0=-U0{^Z;*jP2)2nILWfy0
zW{~Ci9=RqEEYTnXSf&}1{feZJ60u8K{1w`ME`06x8(d^+!m@@}IGqCvsj=J>KL?vB
zs~SyVA*2Rd-1GNIyuqziXI_1}tpYgieE7>!dsRSsg6g?f)5-4Lp*AgTXoD&+2eA81
z92B1E1qV$7>S+j*49gXGXcfMe*mfxL(1Ip?XyIigF?f$4baXkNG{P7FI{T@t4DI-w
zq71E=7`zA$84y5%c_mBx1ilkc>Vpa3C4Bx(3Kx0-gz@ePwbUK5LCF)*YLFJqU16y$
zoVy`A8((qWBWqWMa@^*Zg<vq<g53p+NhE2vpNklrJ7^soc7IeqgGJL2QH4M-f`(%t
zEzGKd0AO8^yV95W$LW?<L4X9zkOLC17C1=2RS^FPxC#O!U@h<-gnt6Y+I(iz(*ieB
z2VhO9odU2(%lyHdL2W*Wl4WD%WU>&aV&;rG@+kT<4+2Y6lJa@JQz7)O5;h<NGf$CO
z3EEr0^B-pZhI)3vZ@n7~ZIUw)zEc`Ke0BDDHf_Q54ZOfeLtlmy7JY!{y#-{Gz5qb$
z=N1iUD1)=XW)vRa6|}s1l;Gx<0ohZOAGZ&HY}7WX9wk&?F`f~4VX`SIDot~azU)uJ
zKzJ_N7XWCvxxfIa)#nQ1CU3y72m!iU%#aCFf=?izn^YNB7iMO+ov|F~iyly6LY1BK
zaNVo?Y5wcE$OBX~yd*%0)H^W4vxf#%s2jBKUBH7Dz8)IT!si_bTKKjwK$`5K`A?HQ
zG$2iGVZddR67B(%Q2!<*c)}uG9)Pj~4N!$d^9q$7ptfLx*B_vc{f~&sAdB6qkaO3&
z`HDPYkEcLC5a^v7j+ePr30brU)z9*Sx`QE3utftWOjek6fdR<=;OGSa;^+bc#1W`-
z)=CfXAdW!8^>327zyNXd01p}(Y2GawsFvTq*G0u&nnBryK|M+qH#eZM0nOz!!eo7(
zu%;hl08l^gVg!vqh{h~`5h<D>2n34$xglHUE4vr|hVT~+1Hf0(q`(3R3NboVIZ;JH
zASPV?rsRnlEi_rP1`xB$8ADDKV?Ik6A+Vkch{+*a-0;W;#DuDhS4IGQMFri<aOZb5
zQitYY$_xjIThk;3#=QnABj5}Ah|$3b)9$JwL`X+5(gz$y5lU0hhCA^fh{`63tH4GD
z5+<-4X8qn*hQ7MOkVoDn3sZ+xY-fW^FhaNTSB6YORfppgDFO${1D|x(A0!VT%!fSi
zLGma92gySW=|dj)|C0wkNFHKH7Q&pQyFuT8FtdfjTSefYn=4R5C7H^Q0DM$`W>5`b
z+M6#(G84EStN!r@jw1BRq$mDr$)tb5`DFvQU{4MXt28N-f|m=&UiA{=g1#&2x75*n
zw)k8~Nb7>Vvu6GAIKkPJfUV9De|Ia4_!p7-XF)k?#5~U;eI+F6wy&tgOflJJAV&=F
zOX5Ss3Sk(*CuHAaGdwpSmrPpT*!3$52ucRmj}h+0n@H-%f7%NJp8vr81O-r;fM+z&
z?0hB-nw`(2L9_FH-s@^?95?Nj??+#nNXTlVLFIH$0ncQsu^>x4lYS5d!k$ULHC=Ws
z$p5V&jJpC3JJ=^kdZ;0PshWb4Lmt<h32pjp=kzo5MhR<C_M8%-EGe40%GxjE1x5jF
zQxCH`Z9+40&;7ny7n_VSpa2R}3>`H=M6vxmfRYr845CWa2>N5hu|OlP^)ce0nE^E7
zSpOSwtPg`kK-CZd86*QK$RNx7Lmr%rpgFo(;23g1Q*)XB$BM_$<vcb-4x2iW>97ly
zClk5@huhDqW(rrz8oJB0NOMwk1D&Uv-BDh+#CM}fP7ZsR*{`e?=-w)c7UJF;j9<lr
zlpfT@!=B2V|2N<Q@8f;~0X|#w0rBI0LMRAR5N^^YcpWvN5X%$t3pbFP!{`*golMIb
z!&5vl$tt}P6kp)Ow~PKo+M=bo2@y$2nj*m8o(x`}g6br_2?5O;Qv@HY+!O%<O$=;>
zmooZ+e_co}Eg`n3BjcDE8tx#-7a(f{zzh}B)an}&lmhrSJSe1X(x0du<z{ZfXtR98
zSq}7hsIUN@DFCT>7^E2CP%%v(I2kfwk4-So2e56hFWh9vAHW<)LBO^}{sXox0s`hB
z5(WtZ))xQ*h6?)ujOPPbUjPUgDl7<CJ1T5MXbj_-|KTpqI1#Pv&9vRy=h$3xx3k8D
z>y{;@Jaf0fV1rzg-%7j(e<t0OcE<U%8S@!CGo-jp4-#f9c%vtZ?*%iY<h9?xPSj$u
z#U0BXUl6?~5_b+@$^?0Rk>{6pADU(5>c>HjB%Chrhc9ahg+uc)2!&x=euHwz-gINK
z(>HNIe}X6-oCHm7FFOa*csl_Gx-6qkP23BkHH0Pjo!SZF$=i)%Ge*Z3DZy6X(0mmj
zjiG&!g0y@|uE}3D#&)xpIuoSQb$hNzb_R!MW}F`jcYBe1$ktv4gU_9@#jl2EzQ0Na
z$vi8jBH0y`uI!!6IJ<E0e(Tqn>P^<N_r9r+VU@9fdrwwINuKc&P}-@wJfn@Nns+Ew
zmvf_yCvAuVOcyvjUambH-Lhyd_>FiN_?T?iV7$IyZ!MD%5&%s6SnW`P*MO97w~u=t
zPE`8m{9-|lbeyi8^07U8NHIClA2%|6hUCw~WEukIOaBVbmY(@ZR6f1`@o~8#Y1eE=
zb>V+@zxI9Ee@Tg4IM^YXT-R%RMJn8Ht?evLBoTgb-dE)nSGJ5)LZ6;}@nuuoo4yHK
zlYQgw(n{J<>Z2trPQ*qGppvVHE^ffRRi4+|tz8p(=`gKYqt+SbA&%bAkvB;9jeZx*
z77+0EN<?(iiQ)g)76Bath)s0&PaJ}Lw!p2jy6RhrqgkKzN+ou8yR6>{=QahR(Z~Lx
zx1v%GG54o8wi64Hw=~jmOLZ9dc8dIquqUTEsM+M{`k@**?(7TA3y&%O+s78e)&Fmc
zA#@2fw0SFMnsC3Mnk1zeoPuY(Db!NHW;C&U=8IpIx33&+<C5k^!1d~`6*`6Nh6CKg
zUf8#xr2re^+p1&Bv1?maw5o{OJ>hkQtZz3(s0>L$&<drEPnqd_9gA<JRhaLuFUFtD
zaf2gAxp6vm+aBHTT)kc1Hb^Eb?I3(%rN{$AB%t_9DYFR9Tz4p=&lz}RfKlf3{0`j0
zq1i<O6+#<=iUY@$>V<T_$OkZf5)E9Qx$y?O)#wQc`$oV%e#aQz6&jiSljI-5FV{l^
z??$;AZ!g`Gd4XL5;NQ@0%EL!LV-y7NkBS5M;{p8WXEIF`TQLCsEhaU1w~ktS8U(>r
z*&*P{%)-)paf^o)UuXKVR;}dkozqGK#+yUAzZAe&fDrnV%wLRkv7b{1{GWVUfT2Pc
z1l*^;h+jv>Q^s#@{=4MAYs1?C<(jTDgZbO1dNW%;PKE3oXrURG)xx?1MQG$nf97SJ
z9-!~YL{YFQ+S8l;Y&CghAAERwTd%M{hxb;@>cIb={mZvBy<Y?LKAU!j;cvIcw<`fd
z$dttjq-vtw@p8s#dkI%Snn1%MvL*(#-?Ui;Vxl@+lOD4MgGc}_5)0OWy{Yjgv_>65
zg6JG+GoPQ2@1^`#rv0mZ&=K36(DdU=kl$hMd@;h<OH9Id)@R*ycy7M8{?de5F+yn0
zk$j%J&TK~E^Q?%wPI)0{MB;Xf@b20WV>BiP@tVxl>RAfjsR7zs8A@eq)trG6=>#|F
zQ06Z+@VNbK5hj>}v@xK6yByA=kWaC%nZF@$Z_TH7v<Dk!N>b$qCc01O2-4LC&X^&=
zd>yeoU+Pcap4atNLhKjnPl;f8_4Ph9gNE6by^qq~nnsv}+HtUo8igd!NXlM?m{(t{
z@2U7HLxx)4R%0zrv!K{nF?f%XIETaC*dSt5k80~?IJgHR*7DPkw#%@nVerUb3}`$}
zWvCDwxH2NSTw<?0@tKNvcBdQ1aMyTSl!uJFRm8RJTP%%RVqtxFy!BgnbiB@+3;om<
zZFB7-O6~1Yud~PN>E+BeFd@|oAHuG>tZ#7crg!)5{_sxhv_K`&{F*!Qc6XsKkiheC
z*XHfV)$MJHY#WxkPW%D`+^c038VMItz>$52E_3qu0_k;#(s4g~<-q%ML(}=Yxpp~g
zeT3lb<Ic>}N~k-ARY|NImj6=nlC-HHu`{}_tnb<^eAr%Rn&Mdpr}~@PL!-kGe`onT
znaq8iyFRy1VT`)PlLk@g)Jr>`21K<sY;$fSeVt8X%$(JmYv!0j?ftP0K7N~#IRc0K
zU<{VUTXJScL+KiKtk?U^|8IMm@YY37A@*vtC9Jv&DUi=&LD<9T&g8uA-t%JS(S^sP
z8y|3a8+v`sEv%Q>E*c}v^K_urg#!Ire&Vi9NLP9MDk7h2dTu|te<->i-c~?cNe5G!
zMtID*s}*~jwmpv(e35I+IO<rx-YV$<EU?P7HD@7=Oj@w)^Wqxus?jf8@+?!<FACpV
z@|YxwHsXygw|~<nJRIep_J>Q-QAN_~Rhp5Na{|$DCmQ>ETvrsUirFpkwy$g1;m8R;
z#+p&E!&Lj|Hf2d*=b~=+(bkF&51c4^_6F*}VdBjEGH^2L-1zPK<T~YkR4c2GHXyO_
zm`&!k!-jK2O+cr!^$kd+@u<b~<l-6aAM{>0t8SB`NeEs?D_Fyr+05aRta11x>smsx
zjf9&c&$4M5e^3!3;D$w_gd1x}vqQO@E8v4?En#jr;D#BUS(x_ZdAH)<?WOb@2QnuZ
zr1e+&U%&c&_78oK#K19`$DMr-bg+@o$z;)4Rll=p@4`gIp=t?K>fr_SgElMadBKO_
zp-O?fP=QMgR5YX?Nf|}|!q8o)G*<ZpjJOPuRNer@;a})7B%Zpw;642+VZTM@+Zh=A
z{g?-TL)X0Nd4TtXa|kfSxu6Vx+6)ayz#ZBxo<Q8p?=FPls^M{j{6S|w3~v1{>wj#A
z$<EQqNjN}5GvY-QiphcX#frCTeLn6RGMUBH4UR-->o?>ee@=^~72wxVGJiMm{N!HX
zo^(4d{w^0yJt2e&@X?F2B3V2xy?)jaZec}^DHOFJXNkXI))CZ(p9~Xh@g8YCA;OV7
zQ>eYW%hyq$WgiqTxZMzZ)2yRKg$`okkCUI6l=XytUN9$u`N=^%Up?$7;E?v(qYZWQ
z+8W8uZBM)qzY2QT^~O!2SV!!(M`u#2G}Tg`+YUKtrk>mWpDWl`T7PfnU!S+X6EbWo
zBl}57Nf9us%#NNA9~TAq4oaalsmn>_y5NQTo6COu3<vt61eq)qd@&`cuzp(t6b<iI
z31z%MFz7h;G48IBDv1~aS^VV`LT8nF9IbzT0%3)7-`=3x4(Ppx>-5Y1z0g?hg>mox
zz1P8Xt%qoGkXN^kj|1a}x~c_fh<@CeWg0Vkd=k*And=#TO^?mL>{iV_JN<918z4y#
zX0c0qq@Gs%d0A<W!@ZLp>2@%#%W=-kJg9kT^Zm<k<b4XOUJK|0l-WtwwWW=n(Hpu3
zoE}y}`q{C!R89^aS2d&1FXSkaICJEBx!8x(w(-pEpvW$sISBiZ-6o#7kZIa<mRwJ*
zl<SS_^rb{Wr_*X?y>hwkv6SodjYNp+ruzNEjU0g<Q7*amAZ$98XFXi6kt%KNOwALD
zwwMQ33U?-o%h}m&RZ9$a2Fr#)R%mH$h9&pzm-JiL>j?#-xBmT=(2aa8#TnV}Um2wd
zw}C|DrCN$$oQ~|-ZSMLwV$vQdJ=Hza-N^ljr!DQW<)Jssk{Gk{SgkSlwt^BN@ykxt
zGDT@}#S}}=f$Ps@D3D+p$3HeMA4=#>jKC&VKO2Dc8=eQ-KPIw1xTe7eRSG>?B6g74
zD&Ts9ACV(=NM-KS9};#d3_jTM_1n#m`KC`?1b5>UF!yYJQpGX4fG+)#-r)OR?CNK9
z0cs&+2@PiB-WQHw!YGXOVRx$HG1L`QdQlT0ND0?_8#TDw9Em8nJM^0o=vPs}k2*?s
z9jGKQ5GEH(o(78VTaEXK@#AE=EHu}1y_Cg`ncha5DA>MR+bH|KX>yJ{XPZmM>5&E#
zgLWJ5X?v3CzZMmWT!anUJH6j8TWrfj#jkw4eLe1aS3;(9DP3$ggv4a^<jMC%(mN@Q
zDRFI8S(k4lzBs-sKmBHwcDEhs8R~6)7|nU5I;ONcE;|w)auR5bHFv6fh0I<b$N7}z
z-MBlIe$?K+J9QsP>CLI#d~<>Ib4|;2$LwstU+w9~GyJpZ!_fWc#UCKX^52xLAn%3c
z(b0?Reu1!?Tsoci*LFCP-R|%<IFcOZD{}8V{ZPx9V|!aqf(iwe-ugqmCa!h_8kU~W
z;z&@Df{!9qBXyR?DL7j}>IDj|oo#TPhg$l8dtQDf6O56_i!1UrP{9(%js5_=UVXqu
zL~fr+#2{uYUaI3Z+b3dGqIHuI0tQ%i5f2kdLgREo<CzVu_-QgRuODjeC#}vye!IB|
z$}Y*$5KG`eYvAc$MF8ENXHRB=Zo#)FJDcKKli*4*Raw2N5?YhpiqTbB>3Q<$MM}2D
zLiOPfv()Q}puAa0tx2OJ^0EWNpO!Q8EdRx4EM?|Kf(xwtJ)Uptu|~bTaPg4*yj9k3
z0hv`<{r@1+5vyuVGF|-a@x-35<&iKF)Df3963o*`t;!NtR??chk|E{a>~`xq_rG1e
z9``(hKVBN_4#k;w8q&n|%^o`-)h_PwMpni#65@_{pQ3(KP5%o5CR`u>GE04y$eIlT
zmihr~?0>-ii_cib%#DOTfO&&}8Taxc#*6dw)>*#+Gg-6$FR;{qz`U{dKY$5+022ZM
zW6cHuOPy?!4&*+-d!*BCH^s3TVqV0&t1Z9ZyCL!QnnYcCIlgsdHxT?X9|>SCw|O~!
zt)zckfbLSu?Y*p=)Zfs3aTM}>ep@)PDgG5|0x$S@P<o$oF09`e?P1H)MVM`n^?K0&
zoc+rCR%=HABz%{(+7}V^|7}J|Ypbffd^0;{lhyC$ShNt)7A4RZ*@?JpP&0AYFj4ZB
zCph@|#hvSZS@?pk<D>=TTq5s0xy)0wy)mWi$u}NQNzKqo+>u*DF#2P4Yz;T=>xQkc
z5f0|zGc)b9u(OyBLc|HjC*JZ`A8btcs|yK)2&ke+OiasJ>tI{Y@+Jj4tj5FqZLW6J
z)dJ0k{2ZCo78%iaR+sod@^1Q>f^q{;d64nD`q9zW9BLs%JY-}hvmxZ?gtZZ~R1Sug
zthzZ^&_GN6r%gKITI5(dXi5D=%@G}jtN92X2@mUjd_Fl*v{?je;oD~TBUw>2BjHhI
zcZ>SPlY<c5LY|9pUt+lDrNOPxs%*$?QX}Ee!mz6BpiF!tVQ%RZE|r|+K7T6=@Dha=
z8c<$wWYq`#i<AF>`!8NISe)$ftuS&0yuP%P42C%2lIsfn$9&cQV}9`;^S;=3AIuAX
zFfaTe$q(i~sweAROj*?fUfVXt60p-vxic%VM=vXeFW0^c%2J*RYzRhkUpH!*kxcG;
zcsdIhMn1aN>nob<WcoE+<Z2EV@jS`;aVUU|6BW=8qe(wV6CO&KOWbv0nLk%%zBINP
zoI?UpWC?E?%N1;V^<SPgzCxdI(WW(1wyf@L?sP_N4(m~doF}-{7!Wno*Szuhdi!ck
zW)T+{6prqEk6-ou)z|5Tt8_-KbPTxg8`GjNeR<txb)~e<3$PZ?Hr*WYXO2kt1%?e{
zt&nueu8lo&n{w&NDX3`I;FD24EZ+myX@HgQ`(2X5UJ^HI{y2A03*L~<<}|FD^#8g7
z*_q?&pQ7Wr+g;3VAw|4+-ZT6wjV%F*)Au7G;1lSMH)l_I)gO$Y58gzytfPFO5v7x4
z@cppwJ!_5XePqcmO|Q(|eNp@*+9#HZYh8q3V~lR9=f2Z<#nlQEEK%{&`<L_8`6cLp
zdaJHofnFCT1`fu8%I6(-71d53&%5uNI+SeIY{#eKT{G8__}AnL&7fy~pOm=tz%Xa9
zXV$?^n06$YUS_U6iG;PDYA+yiw3@UYU<~c>Sgf|(W|Stg2PdoDvl!dJXt9~GJHQup
z21cdmKzrr2h5wx4_G@N*1z<AZFl<QC^RBq7@Uwicc-3kFSF_Qx$xMT}PnDs|wDOcI
z#dYZ4@88F}0rNAf#Atg-^~O{E|JeHyc&fJV@pG?vie$`m4M`dd$xz}F8H$XdgpiOq
zg-Wg@^AJjAkttFrLxzwcnKI8QGnq4l=)ccJufFen%lm)d@cn(Cbw78Xeb!og?Q_=J
zYp=7<*=L`sGgT3?TR)y3nfHj%slDmxu0NnZz<>!i$s4UZf4kws@Js{l?ty&+7CUHP
z7{BJ*)w4`Bv9lNZ4a2<)Y7TOTw>y`PmyX-*dUeCKkW_c!im}guFH|R#KD$__Wb@<-
z6?-;$HCeJ~U0M>(u9lf?y~ZKPBUqch@G7u+f_?xj%@%TXtMZ;Rd-AJn30mz>-6~GF
z&6CftpyI9V-D%cW87w$G)?uC1=Bn1)M>b`BlGwDn(PjAM;%z)u66CUEWW$4Ndjl81
zG{Y<Q!jaXz;`0tWSa!d}-|Hno^YSvEnHla3TcnY6<fzm16W?5x#|2g6EeBE%JM&U-
zv<Mh5c@d0ed(Do7^v_)0?sp-gF5nr7*0yxcH_idop`wqy%$;u@q`j3-u0@~D|LVZu
zYx{hLTP__9c#FAys%Bj5L}0r>ukACl7h*NkI!E_X*b(F$Fc^`$D~A*8;ZXMej#b&a
zI~ikyp+53Ho*8~YpF|g@%2vW^dI$W-sy_8)x7wSTYjY>L?2#S9ud&HvobtvO)w&+~
zC?m=VyByA`)8QFq+Qy$v(nBM=y7nd{t5@WTDmLr-I^A<Da4+w<SggF;)OLE7V<n2B
z>3P`O6Ok-7yB}(8IV$KpIVkIO$N19zM~VcOMU`hvF+Pa#`D;wAcg{@2Z}DWQPh!xe
zQQbzXdf3e&s3~1&hvK=S01q14E^cnVyC=8u@4GRhf1dx*9#Kw@iySq#g=Mrex;z4q
z5$bB&qAW_!HtcAst~c!k3u31j?z*g8KE+d(ql-FYi|A%92|7eMxTj`ea>V`O7IWX}
zw?dCf2yDtlY9&1*s5$VGu09E6-l<;g7bwrXGpt~b&VV&#I>%>GMNVZY8|$uVk>z5h
zlprTrcdb1r-#4XiB-!XZ^tL?q%^rC(;7(H%#B}_Tvv<;=D`Hmjr_}e<*c{B+|7pC-
zvMj7yFT=T1Oq)5kGer1;b+em>O!y_^ix2vdw}ZRPt{pSK{=BdB)4nSq&ug8^B2$lB
zx8+oyYd^cl9vWCPi=3=q7%x%q3KPpa*b{#wjNK(nhpp3gM0;eeK}39D$K4wBHo5Q@
zhxev;@2paIbvqL$m47nxDK!DlmKAWGF68FE!q(YsO?lwEoF7_`1o>WCIrgHan;Wqw
zl6H`%Mx3IYtw#K_NRQOKoAt^`mcc{QCs=m+-*+nT@oRl?(~W55Sy?*b6+Rg97~&9`
z`-)0`anSvk{{F?=jP6e?nRt5+TOuygzwv|8@m|qT+&h?#cT-R%G7_O<L-ORRh~GqW
zQg3U7ZG+u$PA5^@Oee;2C*JOahT9kC#rtw8?Dmc?f@91Dw$Pq<vn#QqCWoappFIp8
zqK%LYh?snf_qMidAWLAb_`G;g{zK)_LTc6ED*@8=h0^I+XWq28R$Ve@JzkfXcXZDZ
zvC0%bV|VJ^oP&m8CtA~vC6TM{N*~jpES06YXn(0h!c9;{EaqMS`?SuIh1+S3JF>xc
z)k1WG$zoR?qde|P-qpehZu3$Pejp`n;gZaE^a}U{vHpWk+iLmhY3eB0cj(G_bMV!_
zZ`wM@)XoULLZfe~ddxehXVJD!>)gZxrTOs@mR|Lf*JR9xDjbvVWM8muK_s$|AABk@
z-IGc-o>=ywG4J3Q_65A13nOQz%bx~bzntP&cDe1=^*QE_#{0r%)~%pjFkUvk*!S`*
zL-^KLx(Q<xZ?CwF)}5JX3##B#9=~ouE+e%)bBfYRWIJUR<IRITcR_PtvCz7RUa`D?
zo{1<YyF)}HZ)U_Z*hnLfN@Gu|Fx90JYH;GrXQn8}JcHe=O1&1wg4-JAxcKMF7Rd92
z`}E1LMrn`8ccy3ezf5Mg5CO;g{;rn=VPD8cpDpjgqb4HD!jew!QJqL}>?u7Qyx6)l
zXmh?Nx>SNihspZQ{p#D~1ZQldP~?xE9mII;(<R=1b$I%4B{So*q=Zh9=%i!TEj_8^
zz(YQ~8F*DG5naSoq=-B=f0#vZ__p@bxbuetPJE6(eA&G}PiFCsu&H$;tODQ~eTS!R
z+lL+GXQ5A(p^eaS7G9qDEb{)8<*Q4>Oivcin+cf@?X+vix_`vFsplaqA9&y^w`4(K
z_SQ4q6<wB1V$a>RNpi+bMDn9jEngfD#*2(tag});fygc_*!@{jJ3D(4obNtSaK6V%
z8X|n{6m_;1&|HaZ3*q@-GZ4qD@cFRyKu?v6s!X^8IGo_uGIj%~le#`Nq8dViTb5}n
zEqm{b1c{02?7HrwapXkKsmJmAN*%mD!cLk8tip3Zmu#Hy<kGWNig$$?ujiBd<>(XP
z_-jd&_Oe-Q@_mZeVPngn4`)2Uymm*>KIMR!B6W7QbW+TmnRbi~wyW_PoCN_FtU$&Q
z>F_0(JS*kwARYUuojv}gtg!N50p-(X%DzPu-DAt8;hFG+S9$STXr`X{GX383z-a#N
z=0jUS8~6kqY&USQYuWnM2xsl7g3`*|9`7^LjFtCx+{<!WsMs_3<m0aXYdd>9OQ~VO
zr9g0$woMHJ5%{VD7Cf<Sc0Q-KGfFHx&9`8_%+;cV$?Fh&qP}qR8`rdxKskk9n4aFU
zAjs@}BBbM(WwBR;&3kqh-<-~4;|h0e?7nR<!L(ZPsf2UPUT;$@WDcKRG59R(aK#g+
z85`rqr=@sE5BoX=e5@SS+!GbmY|&y?{EW&~@euDR<<F)4AA1vq)9b(Bk0ctNbIVJg
z7bMoMKXfcL_PJF$DOg7)E|_{Q(_h_$mFFC5rKH6>$y??XuiBrk(As1bI?g=v&lN0-
z-D9Zr%IDOpu2ZrX-_qLfIB^YKpq}?ma8AE@j!4LqX#R85uBm2Al?BeDLw$EUx$(pH
zO(kE(d8V6q?zmQR`bpg@kKzxgqP+yp$YJ_JbeEevk{hS#ciUz}f$On~$Mv6TJ1G?=
z?%MIxGWuG3a7KAK3%w~6+D1~{I(~h)?v<)i6rW*G=;BDn=ebH7zNlrEvP?tC7FtXa
zLtBy|s}Scy@50>&Ek}6L9PZq0IoVe;^Wlmron4l1dH4>C(H(a0^YagBjifh{r!~$#
zb3ZltB&;Eelib05&mQ8kfbL6&6kY14R$o?kcyFCYcGl;@C2wEjuEQd8_K%KfiIZuI
z4<xz0SQIR~S@cR_zvUU`s3lTm?&}qrEJ*XA^n=^84~|@A<0$p3a*gg*yi0{*Dc_wP
zXuY$1Z846W1Xn&z$$4ngf6){1*?VcFEuX(Cf0WiE?vNG>nKp}S?gKr`TV{KZPu1kh
zki<o0JH6FaGHVUP4h^Tg@MVc&Y0gM+8*XVduKa8;M44urrptb-z|c{^%8{;$mQl0F
z*x-2_<|Kg|6zUh}?JFw6D?UXbFH-pB%UsQ)3I%PC-iZY&(Q$`+VU}%baVq`K0vR<*
z551i-Os?4`ZN?c-gCk*o!bp6Xm^CbSE6Q1Irohao?5IM6`10w!tOz3F02F7SDHl11
zZ@YJuiwiUAqv+@A!07I7@u!tB{0iC#b_<e1B?{8T=nqYgLW{N@l_y`=M)Zcu&65`D
z6=$zp@X{rw&Qf{$_ERS#Dh9>2!?{W%@L`5U@U6f^sgce&l4J4pWDpgxWSz2PX)3*W
zAUBJUrxVMkRP(?jJVShC$Jbj#JDTf?t`J$hxizL4ykD)NoYK8SJeW<TS?Nab2#qs6
zUWlBy!$6Q%836;@<IUNgcvQ9&`X-Bhv_a)_L}JVV48gly;l>GP8*qe|^2IrMbOK34
z3^^oL95m?0?q1aO3#tE5{w7EeH=E1-*no2jUFsVpqjx*JI9_@m^x37z9(?@Obci%h
zHWx)S3ZZ|L>zP48SGdD-5q=Bbz=xB5&X&TjI4^eDQ#2k7lh5+M6_dCNbwq-H+D}{d
z;2mH3Ol46&ge;q4uK;%%iTx2-&wZz}D~0{<3(!~iQ~L`vwNHmk*faLwpb!hj94u{P
zbQP8?_Fl4byU`voL4<b$7IP=05qLL{i8GFeP+WLtmJ_#0&?9y{RAEbq_C_l~cM2@e
zPu{TMolF?BfA4+opoZ4|LXVhm_q#!6c{68biS2~8#j{P7Iul4c455WyDH<s);YngB
zsQHsi#GXm2JnWoxCY7$B2tU@;u1Et8<2Gf${R)}sdkU<Jw=JPor695*q{_r`X(fti
zDS7!@@u;b*eRT@LdDI-;(3AUI3^%AB)SMm>xC`zJ1Qb{jQ1xBAnWTwFgq8?8AIpGu
z_MkBp6)xB9pn&_k+&_$NxhvzRV|BAJ%`+4dqv}8M#FN9o)tQvQRIAV<D4bM5#(x;q
z;%BFrQySH`m&4T@V)dkC)09guD(2rKf!YDdPh{=4-Bl5;f-*d=(uz+J!^L_d?!nwy
zLSAl!(gWOc#wr0~0`i6a>&GU|aWS5n^eBdsdKZ1@4Msm@BIoOJFJ4sB(9BHc)-fGT
z2p_3-et6H@(tv~_fy+8(a4bWj)JBo$Vyp8_gpy<T7Fo^ENw<y&yO`{`nA1)8&}q-~
zrZmm8a8|Xg7owHW%H802T!~Mlif@mkWvWCSy-C~wNmA{QdQwwTRD78dSC$CFwv+2f
z5arCs=$3*HnqS`4Fuxa^tR`u?^MMR`$TPjc`4tDd+oQ?5o_m!TqvIz!=%4rW)d+I(
zc_Z@&lzp32F2?PMmR3H6d*S##L%OpP63Iuhwh{2sFx!PvxU|be4x~mj2h<;hw&HC~
za%?r|HBh8K@!&<tHkN~)*%a2D!~MnRA_^`F+Am|ihpUfXXX^%QfrWTUmK-S&ViK|v
z>$3}@(~lybE?Bn6?IsPYgs!Ry6z;PiOjPps{ES1(pC=|mii4`SXDT6YUm*FEWZEHq
zrMyB4FZPylgYpqM5{>D&t=>$H@ve;Jg*Rm+^aLuSk23k7YHl7CJmg{8c!xLDA;rXm
z;doWyaJ)Q!pu>=)smi0o_g7vGXLGR}89!FIgMmS}x{R_K+C>}?;MD0jsBbNG>9&VY
zZe>ZCzeiHFJb6f~X2Ef@&U2iCw~ik-H@Z?$GNSbIz_u`s{e0WTu2qs~>xzfUv^e>!
zoZJ?AL4l(_Ej<$hx`Ybxi+mzlg2tLjTW=kI{zQRuN%&D4_k)2`7ojbfmx5o4g?nE)
zj?s9u2%p#wcWZ%V4xeWQle6j-O5O!!;x%%~D+q?;8JY+f-&4&HPC;8hj9NwX4?EvE
zIea3hwdt5J)8gEpBZ#4t-ZhNY>CqcDIDgEa8p1b>%TIZOcQLPqeV^*x7$Xd|wAL_M
zTV)Elh+K>TOM*4iUf@yF*cVJ7NOdlj;c(hqG<!7r!wh~kriuwXxyp_!nfBFAmaqAz
zOw6|_C33kkah(j@yZeJH%PU5RbGP1+J2{;N48ismxqQb%+|{2F;_i}HBA`^KJ6LZ<
zwclhhMk2yTpL5dFxjoVLxpLKm*kF=-x@92(j?bc3DuuV%r=iVNuGrHjY~e9)meuXj
zG+{F}h$AxFAInX`WS&w&`6Wj1WKUk4W|1rFH0yMScd3YFx`0B^ld34^6@7-GH?{-m
zqpv-7EQfGn@bOGuiJP*<Jv^2&!{-vx7o%6!Yqq`HrRd>;i7Bxaez<kS#j_p<l|=`(
z+@7qC@Q6}OzPS5gn}G?9Fiy>D;R{wbq{WI$PWmOBQS(bsI(#xLSTVU=we4Yf!}!B;
z)kNlG1$pwO-h+8hlbFltQM>%>I{m7i(b5DZ%vPGVgk`@bQ){Q%5&tQq<=!hx?aM|8
zw~JHem!G||YHN7?sY9`usPqn_k=YJ6&RYm?;^KSc6eh$JWcp7CY<d-r#=U!1&lpX`
zMJ;Kf-gk-5D(t{si$<30>gbaDf~to}JB_BtiVj^kHDa7jFhT0cWV*khk~!~EqKWEw
zcDR&Yo@ObYuhueBW-dl!7!z=-N1GQZVIaY{WmKB9R?IPr(T1tAXh8VT#rKhuGBOhr
z^)Cp;DaEqMZ!y_tF0c50o*ejGczK_%HN&Cu>;n;n#5!`E3;LtSZF3im!(={pxSFG=
z#OvpWW*#l()<x*+){(pEcAkEf;nUK6gk(TBQb@PJc=u=O(@RemL|aZWFyeWfxY-?z
zxlXuHLVjn3YO%M+*+%zxd|ZvYyyh#Lm600O1Qcm+RmNVsH*5l1m&!?G5Z9KcQyY1d
z-S#}wjg;Kx`stkLJ~y|5Q-%yqVf9yx6uldp4S6ih&Fv#|S~71}XfvrZiwEtV@0;kG
zRh4RH2Oki~IDd4$Kh-*7xq{fX^F`%{kXJ|FD(1w?wOU2gOJ`aHNks}K%Zvq+)i6G}
z*3mvPJ|!+0=h-BknsG>zxhvI)!zYV5A`CC{L+9-0X#w2}sgDmIPAz>tc0WAR#o6Gk
z*b5?VpM)5(MWdyZy=)}U7TP3JBNv{jyhe7H;A|Vr?KC}c!2D|F$qvd3S3lnAe0_JG
z=2;f|i1GP;&3)U4?W4I)kk1|xlso<Csn0}DEqkz#W$$i9j~heA(Ta!Im@9fi+pC(?
zEsq_R9-Tj-qiN@PS3~|oYEzrq*swmg?yJ`X?6&@#b{bS<4L3R3`V(E5{0a`;FC<GS
zvC4AvoMQ+G&&NxnJ1<Y`RqC(NX5E{olBHv-Lc8Cu*-M~n-ey6dIkS@Yv9|U@)Alcq
z-bFiJN~w1G(xMtFw|qBT<WAZ7t<Eo$W1n9lY|0CKPf-7<_rvF5dUAzKq1Y+ej?jX0
zt?gyAIB7?Mru+C$9x^<5)gw1S^FwCi8w;0V8!LYf=b6#dk>+pB4sT14WpQyCKJ<XC
z&456P^IS^AO0VJQr9Lf>90HThIgxbbrQQ$MlFWsY4NtsH{#gG(Ysb_{@R`*5s~I$5
zLq_uf!Z&9mTY1Ms1d_W=JGVM^vyho+A6c>Z)PDIq?x)j2Q9e&p>+gPWc%fHky2DXj
zoAP|bg*#D_$ycVyX|74#Eg3I<ImTgqyq>E|yvI4{>}d_{;*3)rl~1>-l6P9;nZMcA
z&~HIMllRoD^VR;YQ}nzxSL1`XYaJ|SCr};|pZxM**e>fa7q4HtX_EP*ebLJhQpLr^
zy5Zi6EyZbXPk2nfv&XlNc$&)Y7d{uMr~y5n{?zxuCU!>(_iX7{J|+#lI7VV}EnR1u
zv3~CJG2P<B2Ylb}2@q9I7j*2fdD_&#Quq1fpliyTowp4quF<lJoY__}+heB3bH~k|
z#L`5R$}U%*#w@7TGk$=MBjrO~t4BbHba8>jk)6{gJ{Knmtavbf4CnQpFx44o+8yD*
zp@_M#M_ul^hh<+-?SsG?P428WZ#9B=xPy~q`@M?~>?*$Yk=I2yDeb5Xw_S;9P_Z_0
z+050&i2Csz+5Wr7GV5Q{77XWHpFH0a*gm?K*&rS)L27T4!m{(?GjbotwBui1PPYt~
z_uFUM&rc3#Els{~vy098xUg&^Q0#nn=~LLe9Sf5o^NY5DZ8>vpLSK+CYln-h-V&aN
z5ZfUbI8hK}sLylJ){0;E>?K=E-HWz1CRSGG4EF&PWFI~jamFuJGvL<5poaZnq5Ucf
zJG#qqLSi4Sv^L4^4{f?!tDfvC%aD67J&nZ5NF(|BXJ#`Td>w;c?-8*C#gr>2?_?Gg
z83=E+#FY{?RK8mpW;in;s*Rs9e>Pmy_si@{A*Tf+Y9oiBl`%{9srcdJZ$o`&n`gR1
zGY>B&eZnk!{Pd(w^osBKy53JOs+Mk>e13VL;OcxrR@93x?`!ScUKB7bS9~gcqHyH%
zQm(k4Oq<cxJw10?d&W9)tM_$}PcL`3bu9^Jd7oc;^r__2V<$Qv<^k)>Gp<oLM15lF
zY-kCRt8M6aR-)vK6VwHq7#WtxBd^WuA`5I=QVuuF`Q-K~z$)1C#vUEc_uS-J&V0-s
z5me=$94Ez{z6=UYtT2E6v@E`&aqrm|S$}B}`~4?+`}yT_CpyQ*@(vxa{UX1x9Q(Rn
zv`gAx>OAvc)C~@8l7{rAyi7Au&kQ|Fv-A)zA#v%pmAIi`^Ltev4l@dlF{@{`#bpf1
zW~L2h)lLlVh}Z9y$Rq19OiM!HO-1$@=WC9CF$wMQd%2U`QdGvoIzZGn|0TkUsVVzt
zWz&G%XV8zFPBZtbn-!dAuY3}I$iU`&4tqncUEb9eW}g+!mGB-CqvYz*m)0*AM4!0`
zXcKfaam&U^^PYC(S`lIf?#@ds#Zum(KvNyulS|C};c#(?uv>=x$#(5g+rT|N{l*NI
zvFhPcMch|>Pc9wVGZ*R9?)m8L@`rLK&lj<K<fCF8c*#FneF-#ltG)C1`~oLgu=1oe
zZEBA+W8Bb@@{a?3kM?L=YTV8?&Rke3Pdg`k{nBL*mVSGEao<3N<@D^Min@>eIJ?bU
zUJ|LlxNP{DvHEqeC;3TTC2cdG`I1~7>+MVuPNeB4+Ll+o5R|q}iFgH=1>(Oq&B+m8
zIiy(f{0ZUty1|~NXkPtHVxt?9{;3&D0+jyZv`(JK_-M~pFIT+qsl6KBgDwpT9tbNH
z40m*&e#<hJm8GnGD%ZjJ^7S}pa=XJfS$y3-=f-wBDVi+@PGuMt?yfxUp|HRIKy^Ti
zz-gTZMhAt9{Rb3IRrci*_T}UE<>U6{BSlU2hRI$C;dyjURckLv<Yh1Epw|p3cktyu
zY?a4}yF?o2T)*g6k2dL&GKqfrHby|{RD$w$u16DGWI;8qqv!JNcZ3qWzZQ8^i{|F^
zqvkjA!*|V$<7__&K2>>M%5Z8|7x9)yK^F9GC*`y59@!mt`px}2{EtVLoL=WYU{MI-
zF()<)Y8ws`d_8I-&v5RtaGVc+Zdm=%kO&2n*s9d{r^-e$s_luGFuu4-DFj2mP@PI4
z^(k&EHINc#OCCdL81H&VycbXVejH}^Qz|RhyU0`}=l;5rh1BhUj+f_+R6L4ciN$y+
z7rx|rr)N0FW0G9}zSD5+WNbmBWlj}|<BNX&+{Npa=jODR?^ce!S=<}kRy%uoU&hjh
zEN!F5t$?S7QY#g$kWy}z^uf^aa`J$vdSb$C+oRB4wfp1E=d(-|Rb3agqq-i79H$<!
z2MnCT)QR)6_x4^Qds1tm?y!4gATE_<uI*7`Sn%_j*7I307CIwW45PX{pF1RdxC;uH
zWH!!Li{(;Z`sjJ(m~=#3Oo58BMp9yeTBGvo(Ve>WTtt%eV_t!d%ctu5u9`$V5Se=|
zDiUFNE;2k#6C`|SkQ5Z~pHPg_3EBDVl8r8%jV`T?E{%;YwGIB$xJx!=k3e!O0VGH7
z7e5yu9*p96rZ7+t5$99eQ<`I#N&RB@{mb$&r#_P2Tuyn~t+on5`}Pcla-A`Ib3pky
zbpJw(t+Hf`)Uc#$sz-e($(e0&B-`<`Tvj4TgZRvZLpd)tS_w=YBOv2B8=g>CekSP5
zIOlaz!{?7mauo)19)CJ;w<0(wMImtCtA`-ThLc1%xd$iiAZg}z;6XY(MmX>w93Df%
zjYrOf*v8yXKYs9$k{0I~o3y9iOP;FqT#pRi74)cqmbo|kvG5(|`W*kjtG646mZFdP
z5gb?)NvzA2@DU?3oiS93{c>Y_K276LvQ-|@$$=gD*H%>VK=V2XH?MHeyqFY0^BRYn
z*Ll@;u8ibe=0R<BL4w@xj2?_1R%+*Z;h{25rF7p3L!6IP8zPC8B!{RY=QZB9U8j!h
z)p#G`NF7<L@lNX+b!4u_d-|(*kqH{_+8ppA12x`-*yBYy0h%3N<b}b4o^-8!8Odwg
zsNU86jJ|@N`qoFGAJy(hmN}O8r=32KkR<8oyX0AEkY##9)%gm`Jaurng>+Y5<Lr^~
z-TVAj+sf@u4e(s3N#OLzA}3%dHTzXt0m}Z65-3n!<5((J6}TTC=!;`O&OD-%_Eu+$
zYiF=)r-o}dV(&b)Q$E}lIyF8w3EJpdvu%s>BFujLDVPsf+j+^;i5?(mfs#X<`EQYR
zYUBx+%j!<;Zg=w{FRkRzKA_X#Nx~&Rz3dz@Y8gy*D1<;OXd=_?yk2DQP@J{4#}gx4
z(&&LY9zTNyzOvW_i(Jq1XPNOzS-sd#o9o0Z^xAJtO*aOS<XyJMlX2_tgxr^2r8Qg7
zCv>V})CDTTP6rdTzm<qAt32n>+JyhOtiVyO^6_V{Dd9-V0PS#2lg4Z1qD#I__5>3|
z6LEIrWPM$#25JqhPF0yD$D%TOw&nI6Nq3Mtm0&!d@N}o{%M%NWacR}L?{3(WyBum_
z9JlTtEsRhpoIT*yF&)nIN(|5N#P(NiEl#zsQjfIe8Yu|6@n>l(gha`4JWHd!w$DHa
z-ynEU?Tb%K;7Oa5mrGS9V&18-hr0GVA4Lo_*^-&Z3R_)08urB6fXhudC1%iA{pKtP
zxq`zJHsQ3)430~gvMiSM4nbnREp36H;`QzvzC$3|krLIzLFL_JbwKQ}sjZO$xcm4R
zxpHwZD2%iqp7m;2o9>jYU0A+C@mu{ljTv0yj4avKu&NbLMN0EIPNJp9Y#H;?ZHF++
zA$^^^bCH>CG0ANmXXf6%)21|hY|cMyI!B`?E?kP+mSLY0f8=D?vYt9l+lPpm>|6PW
zR`Oc+PU`H&=6g;1O&<_ne62Gv&F=i@qosV$$N15Y`^2T%IZyOV#pjLaTtD?(;re7K
zNkygV>Dz&#uZ$FG8&Bg03?A<RpRzNb=5Q$4HMo^$e$qH_X9b(0h?jlNhht%)a$Brl
zi<DG4-e~WW<9AoBLFtU|Y2rK)AU>ldcV=9=nQbDFYgg2r#{Th3K!*J5!Or*n*WExi
z<Oqx{i^O8j@3@phZ5Af#5ikvkSul5Uo``vH?W9U@heB4xngIO%udH#7Fl*?OfajvP
z_Z`Ve*Ybj~3XxKB3Yv0fn4i|e5;(QV@<c-u6e1sNH{R~OqAyfa(@P~aB;sV1=5&GJ
zu-r<afUvVwTCXL@BZ~xtU98e%Y(X9$<Xx@OlI=mB806io(#Rb_ehbKZSXtXhfIQ{d
z*EdFbjBj6N3XkV6l~^vVGaq|OFLzx0y?+6%XnmRs`;|+P9En%M0>yasLa$T?AFce9
z`GMcW&@(CPxCtrQ5GwvQd;D9Q2YiAtF87XJzIUb4x9pw&7X9rGXGiw(Y>zcK=q_h?
z(`4w3w;3t<2-kstm{^mvT#}37V_C*|5v6bURavWa$5>ycIh4y=o^#c!tVL_|Los8*
z(BADD=hKq`qlb`*XhhQd@__`^#|Ll9S;X=w<Tn%~sMdm=`rP;=yX*6|BWK)rtMlpO
z-+FX5B)KsaOJ(Uz9%LNgWiOEVNF85NBoIboG9_@TEacN`@Gbe%9UrJ`2}cA>6LO5r
z%}L1ZPpJ{?SC}el7G!W4ymg7U;enx<xhlW?4Q+tdDQgzwaXC+PnYV%CyqS66e*1@p
z0DY^hUhs&^px0%}vr>3O=KY9Buvq)?z~r>2)lKh0UNTj^+<86`RjO!F`~12^S(EAU
z?n&y4W04vHh?Ih<-F>9E^a{AimJo>uj`Y!O#Ul(wk~Qdnx{@c0x1RX#e`6>BX2J07
z=_8e*SD;F^qyTK{f}-B8;j{Y=Ws2Zv30_m;=u0u@!?D4CKH3R2K9;%5#Bwi3*tEw~
zc_4lN!Tarp<FqL?`qFnl+~q>jvcp<xACEuvIe}fpJCf#}x6@ojobxZSmh;Ttx3kjp
zHOjR&;K6Hc#XC(w63Fr$azQ!aT*<p!W_*qXa9$KqIH`(X!4S+LH((Wz5>Kikv_;Od
z>a4noD!vDUo75fQ6nWFv=p_-3hb8Z4G!^KL#oahW2A*&yam5mmZ1Lc>*1Xdg<UDs#
zR?Xw(!w2!CPos{+$TObYao}9^G9#sW58&K|GdAd-NExOs2Nw^My3@KUvkk~Jf-7pT
z<y77wm>dww|K_@&2Y224!Vxs!3>_pt9Ivg6Utb&RT!qZNK^hb#6Z80Ra|^X0>a!@N
z!&q8gDhj7-@OI(_zotug^smJHq_nT@N!|SlJ?p^H-hR&fOm{Bc>xUfm?dL>PXyqWo
z(CtL!70<RKl7s_<wYqh<&b*SHBJ&NrlP!Jqi%8mmODCMngG;wX7p4VfGamIC4`8zv
z@TTe7F5RO;xA(P2pr~%Cab3m*4l-%Fy{7DvH|{Renbw|YX!U2JAK5O~Sgmw56ZKL-
z;E2Z=db6?<4LGN+W<DVkSC~IP)>iD1MP>G^T3^H1nS;IJ%!R8On$k2}`~jznp5|{$
zxl5+U&yA<0W9-b#kXOTfCv*$;qPKqb;?t)ZGSn*mf~;HR7HhgMu;ZWdFhWKZ;CyO#
zcQ%ZnFG`reEfCa?4mUQM96og8u@Bud^9LqVsrfg!x5f%C3XF9<3s%{o-zXUs|15Vd
z^r4h@`(Q)W`-YWxA4<N54rB#(v3t{*$1ls}xyR-}ffJbo{<YRKHq%=tPfZ<@c1X_q
zsBT{!%v;ki)VuHX^px>Zz+GJ}_v!`CiqhKPqt$j*855d5c9W5lI#=f3pnb1@@hrO^
zX*nB38KJAv?S}7a-(8(0!I#yujcX?vi(1{eWb=0y4Rghz!pl}wIIX4(Q;cm!4)@lE
z4>pDNpQ<YN8902NdOzDuXB|{^6^fcFubypXbk~kK+4N%XbT8|fgO6$tJhV^|x}_34
zDD~yA#bMgk+LXqZOOJ7~+l_LMWuKSyejhTvPy0y6<XGQ*k6;1$8x%ob+{&#^<Q`9D
zYpggM|9-JxAz^A^(Zpcc@5IxZWRJHkqw0AQ&I|GN>J0grcaoFqTmqW=;sZ{CJ?ckb
zPo<?VUPS|@rGh=m*1mX3O@?KS+m%Z(LlP!tHmW8mu5TLzC2S8|QR4q-!5#9f?n0RO
z^X-SZ;v9tT)VB|5WoS#1%bUGb*pVrCC4U=JOEf{8(8R6!Fp2<qlFD?;iZ}-o7sLLb
z<u1JTcZyeuErrfmwvaPx&#DsZ3iab<(Tav<3g#yrlV->hb)^z1a{1ge6Mx>R<DJN*
zR&r*;$MIAiFL&+SvQ*^K*%ZWPF5Lh0thl{@PN)h8SwgtLC;|EONmb9F_d%++mfzKF
z%b+4U5{0KGZa;(G>x!AyLeIJoylzUMP!iiovQ&iAKcf18*pWsl|6N^*aFir^VNdiT
z7E8#5EfuZpNQ~&uz>E-(2PL0ijlM>swEWK5W_A~DP%ZKyi>Oknm@6jq36}ohrX*TH
z6I;P0N!DmiSX8W{G8NLaIPS&uNpy}Pm%LMaQQy^y*vuFBWDbhkX98ptoXI>NIGb2C
zM+b|(Nxf=>+b3fF<{0w<DnYJ#{P-dV7oF+Et|t<=g?Pyn8D|3As@-={62upUxU3vn
zpm6Z4Dhj%!=EO=IlqWZ$#8@?7$>qN**1dlx<Lh}FnUPCY9FJdLL|UhRiPJsw;PF`1
z4AZuT7|#JofA?*UZlwZ5v6#`!+k8yLSG@c^d5QBZ7#JH^Q?gnU31ge%vwZx9DVk5K
zsohjQ-_UXEm91ge+e_u1yryQRN{zG%j)zu+2xB`}%$HXVVcP1bG0MbWGA+I^6^;%P
z7jmgOoqqgfi{9mnczVL`{Yol_JBD8%=w6FZ?o6<Z`hu^QIKX9bmv44#x*H-bWt0|d
zY0N5j!r^VS;mFb(I@J6;Nq|Bx^w3^=vVG8z9YT4-*`J9fW3EnsVG^fA7CCZMK(l4;
z6rNJuamxUb=H|@TZ{oa5?kK33Jb70A!gd$C>$yOVvmnCpo_Q^6)W#7)ce>;F@nHV?
zQ-X2_K@enWi1Wq`RtN|LA+7?jH=V0fV|hxA2e_|jakSAN>llT(b(<%hX{SFt4qSSi
z8g<$F5pIK!X{l!JPHMT%hnB6xd^prcDYHiyvLvg}w{A<NF5;(B?0<8X<9>3%?cF8b
z0~x9%sf)J&PD!7mD7heQcM0i(*2y92v(32$t!1Q7TPH(&2{SV9khs&kr(Fz`e?hbN
z@-@<d9*p~iJNGIrhHy>iui5Mh_pek;yhXb2RB$m~PM+XN|GH}g!7&d%n4WIL^OtBZ
zi{l!39?q1^>hi$n*lmW3B0?vR;O}AxX4^ktW0Z1>lu~e?v`$rjo+cUngA3Z8DfeD#
zrETYzZ5E~y;d3jM1z1x?V!oaybV;l@rGrZDTirgMJzyC9iP6*S-b?)lH@pYfgsJpP
z&hn`o!S}4aPr<&$>-KhjrE6PU>8v%q8~vSoE^?K)1I}BdR8dD*kDAf2!^O>r`Sdfe
zGS92JZw-Sh;t~s!^lsgA)btg4s*Orts@shi0XSuuxo7BX@aPG}{BH6kk9hLExytOC
zIH#$m;qBb{kxSrNdFXR}(#A*`)}+IC8>tOYbE3r3V`(v|bU2R&l?hFQ@h&;K&?H8y
z44DM0%buY`c*}9KF|xF<;c|3y^%yuVh1$}yM+gavoqUHsx;$9YToUo=*_o{;?2&$o
z@6GP*dA`lFxRh7Rc4?cd!P#^!9L1?tszB)z50q!{&!#7`6XI!IKAV^%CU-${?rh>1
zyMnmnSlx|lg4M6s=k%Yripk9zjnx$oEO0o6J(D3xsHco>5<GwAHlCz6o9d%6A6;tA
z=$BmMbM<pZk5BEzOvT~qIo!tMHk;g@ti*QEzI`u^vV60DUA+#ax|BrBO-cIULtKv)
z=m<FilpPioUtidUf6&A5WMo0?bo)(bZ8rM52@@%Kf@d4;Za>(cJC~ls;T_r?XnU?j
zNBquB<=(3SzN76VNddg3S5ENro>)4)U%ogo@4%-mK6lfvWOoE!^^FY<q|M;!Hb2c%
zJW{Rko?W+C_(ZH<E>~rF?AWnW*U#PO9t`8471!K;pqsC@z~I2!qN~MMhr5p8h%A=w
z-tMN7-{eGT>m}WuY9JXmG0+ixk7tS~$m<q)&`^4lV2wz67Yn3!NVo)H_RPo1*DOQy
z_{VB}h8i&`5k1jssB^(-qRgKr7cISo<p&O9YVF?*Trt}swNKe@xSM8S%70%(^Wc?Z
zLP-oqk}5C8d|{psBpE$_a^yWz147&UWBZQI{j6n^;euRa7Z?g6M2V&Xj>=KoApSB*
zr}*5o;hSKWqvsOod2h(ETBnpD==Ls8wQc5JY8tTwP02*kv!*fTvm>T6(J2S+b6rq)
zy7$5vALhnfPO90|inSoeY9^^n`0=R%1)!+C67?hwNibg-0!3^Gl!IzSoA(62aS08T
zQC9spqiCz`!c5hX*Fw`lMRoVw&VXY_YVa#w?^?<wd0NypL-p3;_1jby(d>}~ssfAG
zBo;jO0z1s*>m2pDPq0cWPNJL+#M!6Yy-s?0eG+x`K%6Y2qKGvJa($`sR3<NXC6Iw2
zR|SHciE#e|ILKv%syrY~2<IOq@Qd_}lcih4hL{8+xkwo!L=!nPmj)cd!uNn62%^<(
z?imp7Zpbvez4r4M_HAS&Nra=-A{@9@W85}k#DTNe3R;NdUhafrpt3j@K)$cn6}OMp
z-bocF-k>*~->0mq>vBtUC)t&X*vJ?7a^mM)GVt^JoG*9nXGhhVz_HBWiA23m+q*mo
z9*0JyR+LGznN<%6eWOCh8!AKg6D-?-2f!SUBDG{@X=Bh8VGp*H7F~PcjSS)U)VyAN
z{~C|o104dH>4%~_DRwUDhT6|XCQVS?qfr-FaFz-mIz$>TM~7!9z<zcnf~bMR8_5$>
z!F$Ea2L!Ei^7~OoyNUP|iWBdExg2y2Z*s>qw;p|ToGie%d{J=TlHzENV?gstd_n#)
z1Bhi&4>DdPSzZ94Dky2E$*AQ>M;i!WzLV@zHj9FDme4I5-;#>qjuwD?C=!smvY0sw
zkovw4l3o;?0TS-tWzWGo(tW>4A<h|U=rk$1V1=OL&Uvp;-hTo^+jW&3ybMRg7WV0U
zd%I3D#2wnEU{loIev<xq(CzGWllYnoVNSy;M~N#r<%(O|InM%gRk|EMUuI^=y?y5%
zJTnWh^?qc2F#Z@l(Y`Q_odzahfq?yCWlWNo@or+kJ(Dh*zW;7!TL|EOk@6mgr>{kK
z=e+J2@v)v$MDdo5o@tj)a0g_ocR!)l$LIFuuxb*raJ}bD%I={(OQy|g6#Y_GQp1s5
z!<}BiAi@32EZG@=E0MjS;b;JGvT5(@b{D7EIi~s08>hYB&$QLZd^at{ehPy@&O6ul
zo*Ml`S5=DG+QQ8j-1Ua2aeSdqMVK`>LWzuC`{_Pc5*r8e6jbcOmVMIdElrt;Bq*1s
zKF5?BFNqui!AlMVFQEY&3lO|iK=3lE>aPO9i^ELYGw)ud101|svZ=KA+%ohJ82YDJ
zbJ^%)Ly~OMzr?A*mvE#Jp=#p=aSo5ZTH5NnK*hKksQxARtp+N$Zv$0{(Q53Ar(hRc
zjeUZybZJ`H*q5=Z#Jzx=8VM@8Evh!e*GJ4xagCYC;A9iELG-*RvGQ12A_!DDgUZIH
zeg`g<(j^}DlT^97Cuw&Xdeni+v)w@Y3?Kff+E|LleIz4`_<NNk;@&juOZI=xfusvm
zlM)t7l_r!eP%bH7oI5bgfApZG)wPsDveu<qk4GMdrY_{NMNZ-}M-;b#0Jf9L)$45f
z(A-Yq@?t|}{P3Q%U7TK#vav&CU{{8MIDNEONfk8lo1-t4I%Gnx-)xV?TQCc~Ei+oG
zN8%VTUfmw+TK!ROQSgEvjbhvmbh3HPb2gHjbkgysIv8GXKS8@GcaFu4RqH%E1@#^y
zDx78`QEPp7;N*QN+sUV=_rwIHu*Syab3AmvAw}fMUvH<R6UIv+%Mm+06A{$HNoq@3
zks|6S)BlVJCr65Z&xvj=2lL{@2{yU&m&eYj%F!Kov2*x!YW{U@qS&%|4yLwev?@E!
zHqJyE>P60F83o-`cDOLfw0-ZnS*u{_1q%kz^18~3<XLBeI#HT#2ZFbqqtkP_<aQkb
zlmt-|<oB=4W|t0id|8^a9=&eqIB{)h{6%>zFRi8MSV`@3-{x`yVSXJ?7w*XiO((Ln
z%_ED|{bfFk6{PIE9tobQaS5xjh<xTP=gDQ!y4BxFA9$#eDdcT_Z&&V|@r+E`@a4c#
zS4TgCv*uHSUc%cE_eG!F+Ci{;%g%dG9)3>Ub1Jpe8ei-41+|&yGb7ytPZo^Q5_K1|
zx4r0Rqgje9*ZTC7+e}e#XnBmY8pqnKLpZ5`*lEb>>3hXjReQRL>3Xz};oh$)uN_B3
zh{)iUpHA$t%{=Xz5ITEbAz9&LF>6$$tmN~Z4ub9HlzBTm#+r*HwOgIDxu$J1t}r@z
zrr$bsz13@3If&6tBhTq`U8&&5eDIKTPTaK=@r)+8{?mZiDVFEE#hb32(ataRtbZOp
zCwM>ySzh0+`uy0m<{rbIF6q3^IM=<gZASTI4Z<B9MMey9r9KzRkA$0FE|sLbnSnFd
zQ>B$se6H8E$!OQzSL#<g46}Ueml^a~JEhAtGV(N!e-t?Wx;xcAC!cD<53Ow|?bp&{
zbN!QFRKfCim*2$oc1y9v_c9+>$jdX{i94<2D5T{dSlMx-#j&ETOW=C!Tiw3*<5tX(
zdG&|gI#}9xOn2m4&1$H|f4Ok`x`<9{dg$)!(t7&61fold^T7vGwrZpx9zP$cy~fiq
zcdFx!Oen3cwcu#5%S#e{7yF#~tIF4}#m&gFUDGmqSe-7c<#{fX_~6Y6s>;EO9LU6k
zsiEwHp|fm+f?PK+bxR7{zi`vswmR_INPmZxI`fluuU>}W`Hzfo4r#nmUB|wN%~^L0
z<-gk&pD`bGbdbHu)NL-BNz73bzinJj`^r@wcD4X>+wLoM+1A|`8VKwA5Bgem7BF3V
zVI))}_lD^K7>v)(`z(zI;=H`<uy8GR;J8Eo@Z1NZ3^A(HM?Z44rI6b->pFCWo8|e*
zY!7R1?l+g_ji7!$nQ19z(Y0(^p2*Xv&w61m1G!yk4mD?n@t2l^9?fAKk>{57GJAgF
zh{Wq?ve;#)@}WBRR1$6U$I256OkFHUvy1L@GCWh)cKHs8)aY+Lcv&m_^hGIu`^wB&
zEytH-{Zn1(V=q2Va=K`QwYe#?nnR7V7I(@O;*+}$?keDP;*soiiO%@&vB80TCG2>D
zC1(vot<(Og?&DoTsuR_XJS!jPzl6k3l?hald<k>+sqILk@KSjCW#zT!qFzGt3JK?+
zkoY-QJAH<?3=LxAJ?~SkeQ7)}27RBuyqh|)v=w?vz<`}i06}7hTOq_+{(okJL_-(|
zB%AQ929OvC1rdIW`S*ET3WOB26%A29xDaA>1DMw&ATfj}q&vj6zQKxJqro+NW&4(Z
z{P&f8L;0q@->4SB3(@I8_}}nvW(g5sjyDQ-V~QXoMBc!lP-sF5<V}bb-hgsz62OLn
z0v8t{fnM9dV%KQjWPjmaMQ)_xZ|eJvYBwTblV?){n;O{Ez@`Q^HL$6H-=_ie?_=NO
z{_ocS`hRZ7_TR5__y{o@8^!$pos8c9U$M<n|Lq#sbk_fN3vC|XrUo`O@DI=c#XsO2
z|GQ3cQ{(?#_V~YXG@F-9|2ORP`;HR*``9<R{~!%u{vbL3Ud*34F8=qmZc_d{4R8U`
zm_JYarsPcxY-(Ur1DhK7xdt{bhJUW3KbnK;j~4iAc^jOw^Xr0}m`x3AYG6|Xn;Q5J
zG@$e!l-(@4se%7X8t{iuN+<{-+USL(Gnn;F2>uX+LV_vatHt0Hc>{ae_=Sbo?Pl_~
zYhZ)(`LV}|15z{vE`(x5K@j_zS;6xe3>pI{oABSF0qi5QEgLu**!bvhNDmo}egJ)v
z0p<8{v3FwCNH7qzg%Ah0a5PGf_zxaw{GK+qfwTBuW|4rfZU$?tM2QC%!WWm^*y-Zu
zQ9!(-I1px>0D`>Du!Ra&cH<&W+Cdn&fw)@%0=A2WX>jL^HOsFsXqdd=+w(9ZEFA;>
zSm|JchV$PMV8lNhF!1?fmHiHf5JD(yKpn7sF33aBkQoMDXo!Sx@eiWlVtO$MB!m+I
zL3D)(s8Em?yrcuL-&^5V7;H({>OTdz+V$pvhPh!`08nu99RWuClL3wOpfwGQv4NJq
z5e4Ic0!lc9RC+YPYxYwj5mp3fSO(@Q5r*D903wAbSRrWVs;*(e9|Lf;oA7%z01R3P
z%Ahw`jt-Jo<s<^VE9{ZL#25tc*RJu8HtGfsYm@DJ4WN){T!;^%{2u#*y{#0G9&AoD
zAt6M?1sX*V=oY~S1@^57k0Kz~9~9ms{ka-Ie<Pj(SZM>pR?J!v8VDE=20RECg^hE1
zdW9gk0t|R986V@0CH`Rv<`0wf4-oW?vXmgy#!nb?bDbAW49r-xwg=*$B#6)MO6%0k
z?cbw;LQ>Rf#r`;`!gsY;ulw<l!2E^kHz536kU`^15Mp9r6b65Y5`}`AKpq49SdSTW
z$bTdNxtp+I4V(oxAmF~VaE2Cw+L_>J`4hke^pn&O^rQ<yV7Agi6nkROa1rzeHwdjr
zgMfH3?2!Kx;J7d+3MRo8#&+1h!k}UD2HMi9FqjcOLJat0rGpI`&VNUM5&vu;#K7kd
zD_f5n2L&BriiYz)1qyZsNr>(<XbevXAT&}81D8N;0oLm$2L{w5M9GHxfdC7z-&q0w
zR~Qsra>IVT-aOE7DOeT&6r6lVfDxOprU61J2=Yg+>FQ@%8KT5M5TgXRNeEWxc(Vlo
zudGr?yIl#I1XoNHN)QrRg&i*aOwK0#FVO(U#%jR@w;X^S(J(jcC@`QQ2!{dzk-~!<
zE)OKMb%QMgTX-}1vougB2`q#Q9B=~wp4%W-Z$e;jAXDfjT*Mzjqj<q1Iur!)Lcr`;
zbAz2t`0F+BHS(=hO%Dd48vr`&jR#pUZbgI83SmPg@K+242|yG=gdjkpv9{iTtWB0b
zS_8NUpnnMUo!Heo4Bw%CV+R9CAXcw!-614Ih*|A$VNV6SSU|6CHq*ae18k5U1g>1M
z06I<xT_?M?_rne57Wxnp1yw;9s>1US<QxM@!dJYV5QYuf4@#Z_|2NWD5gThHKdfz&
z`2V2+7nW78lcz)CQN(YD!{X0@4tW?t^Y(e5{BLieK%4C+M1wM~)wpq?Vlfb1AAy18
zZEARF!nLjd4zvI1uoZ~Fb_8F;1}q%_8cyII;wu40{KElLwDz!DkDC_aVrQY)n0p;z
zB1CImMxYCoa1hXd4j9ycfv?t92)eizLRWC&K!t2bia+*gD_q5T^FYHpYn?p`&VNUM
z5&v{}2WtcXjyf8+mI}7bV-Y`0hS(r?NDJ2)N(5{u&@y092PU><g`juv;D-&1+D!f~
z4G{XnHDiEbS;4SnW6lbXPLU9Ls|N&80;i!^_Z%Py+aE({klTd6Qv++>3Jw976dw*y
zKLr#pX`#THV^a`A7)ekB1*R|oSroV!kh+6@@fX2A6}ZXp$7^8i(gRooj8rxx9vBR9
zANFuyO7Q;$Kyl~7Lae>f5a9Y3(EFGD&D}py179698v4#gKdzD$+>ug}0W-$Yu!mxK
zdBIQ?LIRhifWRYITtL`_zexj=sI`iD!4|`eUfcWGCKULhJ28R~jR#7IVM8l25q9+;
z4hRYWTcsU86R}DE6E)x<yE>u-!&V$UVxf(7!eBNr65^XiLYV$rV3P0*?5yZQ3NUOX
zVFCAsK?}i{9^D+a{)uM$iD=Bp!?;wiRrFpVaB)<(Z155`5PY0N)07a2ro92_-BL#Z
z0Tj^>w-#cYS=^zD5b$gVTqt9G81(RH3?M^rCF>Xn1Mk2X6rA~W5Qee80Wc%n@X#;~
zQ~(1CPQD|+h<`e$t?SeX+)EHu-H^AUpu`x66s-=$KzQIePGK;7jf8~M&=7Qk4Ptu-
z&!PeNb-)^QeP?s~7ia+1_?rGP8+RH|Xb<4V!2X5{ngtl*fG4c0hbs#n)M0^m&6`&D
zHq*aS1Hh!~+Q-0dONCf7%1;jheEtRnd=v|7?ubT$S2e&}kn8^cQyH5Kf0_nRuw4-l
z3j2r@gLS~4)a4HfpkW>y6nNPN+;zafI{;v}N5df#HZyE;4ESSrP;dqT>3xSm0?gM!
zFvE}GYqg;IU!;TlTD7YUbiJkhSl0hM6&C{mlL9~hg}@5>IhcVbJ{S}*ASnVuqH%$W
zk+2=HM&iQ2&(*=hb#NQ%7u~~T6wLBlw*EcU0ug9f4ify=4ftK#fC-xbdR^d6?_fp1
zb0Rb$TR8g@0Qd1VL8(F{3Kyb*SfM9t{P6vLF7Piz0=3hCj1~A}BP}DyyaWH=z`%us
zVbV_lR0}f}!e)fu!G)#6urA>%VHN$)PQN<n#@qS2oBWpIenk5%{@;Q76Gi`yqxiqV
zx^~}h^>9)DzekN(FNi{~=l+T<=C7#a|6U!y1He1S*qDleZXzHYHn=bT3Gf0s5|RSJ
zjSyS{q2Y@ntj~iSoCoi=66(R%M&O<?K%l@MWY;3-HyF4$1Q%ZomGJh5uv+cE#Ai?f
z4VOZKKkUvJ@c)McA{wiJ)fA{5%ocRtkV*=_xynJoCD>rIK@cmfT=)VRHXaE!|Mw)A
zzo**&##+%>(|irJKRHBX2p;4Qn7>ybK!9g^tMEN#4Y|4bi#34ZLV-yu5CXn}{W(~H
zJHF4sjSD6CZH+}jY>Pl~!{u&5kSuK3?Xbsg!r!C;SotWpZUak*&e(K=k4Wi0qabwj
z79xm^8BE|WS-mlZlSlz2qCu?V09Gy&!2A;HzE<)z`hCT~4Pv7`#P_inmIcGQ1T?&}
z-c`W)e=@`@Qef5ZzV!}-^3H{Iv;i2s#0u%n;2`;O$&nbMMGV}5yXzC+LQ=E-6sYq^
zh|7Q;^&3`z4Ty&21NFnVKOhXe1KW5*@LP=m1DE`cupv?Z<4kJnSH4O>%^0qA7x>9p
zM}u4Y2zy)znFu;w3Z_-=5j;XA6fuO0*^h#tNqFMg4`IW`{GpUh;;%G-!Fmm94Sx%E
zA);R~{Wby(ToJsj0f=DnG!$mFHDG|HQ0x5Y^~~n>uhsws(ETrg4RoX%bXNE{K{-MU
zY(_9cV$GO1po2wIK=?2j`@9aD`6k)u!=Z1AY-ayM4WN){aD#Y*0QaCM6qXqQ(W!xq
zKZL=0D+<B^Z%BS!vI)!bn+f_iu|GnBcDD(?Qv(>79}OoPfz=?)1wj}z%#Kw!2BQZ-
zU}h6Q!pSE5jT*><{SLspEuaG)Lu}Ar_k$Sh4oXcjB3SVs(yYpm$AG6Q#d_FbD`qz=
zbQAt24d9Bw;Sm7NVKDRC9-D=Ce+>65oS{M~@Q~Gp8N4>vxXSDUZa~0GgdB&5t;Kg%
z12qPwVS8*i1BY%5ocW4@-Tas64wHTWFe4hKBf)?DGGJZ8R|3rNPlqz_BowP`6DEp6
zDOOlV8vrxV81(vpLw+QO&>@;qXiyF_bOPMvzlMTPVc@~K0kaa;TxeL@S1bI=E*O}+
z>g#asC-7U10Rxx$j_?y9{|K_)>SZgq3y45KN*g_8Uid|4HDIkL?7&iQ;9_W;et6>v
z?7JVrrQqFQ1A)tI!k?gl^)3(vth72`djpl|VE_|sIVnOkgeK(07Qu%_fk~+w1K5Sv
z0kfX@(RM>jKN9dyqODsM7^x6Kqv1E+HUe<B=MVnaC#~q!5)@zq{_q?WaK|6!_yM3W
zKOp`l>FbgHCUq0}y#~;$yO<qdi(1=RMg1V9g5+@uVLAej0-}>$<>UYxV9eEf4n#_;
z$j$Vx*TBEJ=Gu2oHgF&aup|?9-8Arc6@~4NR}0}vuN8LwwUEMJqc$;rjt2H4;5Qb5
zpUP8E6gq9R3pN8Y`BC^#bRiQG1M%NnJv1_Kwd8mMtg;19i_ivcy9s}n25yRAfU^O>
z(FGHb<~DE`Xuv}^gn-Z^F5u1eE8yE258=E05Y*sA0cp;H*}=CYAc%$qwK{HsCBha)
zfj_(iHG~2GuNbVGZzyJ>K`EFK-a>G7uq+r5;Qt)~i~WZu#h+K7wql5M2%!hp(Xf(!
z3|xRb>IgwbVA#rM4HT+5kAX{I_-NT6Qe!rB96aGTY2WH=?P!?v)e7IK|2rGQY(E6J
z+V$q~)sz5-flGZyfD!+6FkBzD-UPjB;zqt}1Z!*(PZl1wq7Vlm!dKDYjYt@<PYD!3
zMv4MSm54-bKCQv3<*!fBupgn;>LmoLY^~>idMIly4*UdO+7PqKkBel5l-B!3DO}iv
zHsP<=02&TdaKE?;u!+}=vX1+WE!JARu+ex?z%#KO;wl><c+iR!fCeoD_Zz}*Ncr8U
z%|`OORR-?wLKs&#dSQMZTOqhHz@I=uVecn_CD&wcfEMu`;L<?^nC~#~&aW}QV%bFe
z0UG#4&o?(N4ZN$2gou$8V5SRP2=$G_gO%_+qhTZfbmHpvk4iVv-u|e%{&(b{JRo8W
zizM==+C#zT><C^?c1J>ulOd8|Np~<~7{DaF9G*I%Gja=sEEUG=5B5zIT*W4APy@Jt
z4+Zn?CqzN5C*a%$K+_Do1ZlJz7n){-_;}|jA=s{tzGyDZ3&2hBIUz(b6Y@6(soxE0
zP;f<XEBYn6!<c^y7+jbU4b$Q3)~^EAC442o4F7akSCGFmIfNoTv_Tgmoy0)r#=-oE
zI&ulr&=KrA<u|$sAY9xf&`Q+76F!{1T<|)l7&NTl^-8cSpMHnIz+|{-Z3w=$!F5xD
zQW&`8cLW%*39A}F79tR63>oU@`hed*hKPY8EhsSfs4WocT_Ls<@}UBSn!6`(qDDOM
zxj8Uf81P{!VEdl~w%Y$(%s);7{9$v<2F@CGJ&0FA7Q*0SKn_?>58ePk76JmHJA@&8
z0`G!bP1rsb&j06tt@b|`^N*8&09Q+Nu!n67z}#;XiWfqI9|jGIV8GQecqt1FxdRy}
zuuli~lpB`^m^a~%)d1?7ix%`xMLWYBRM;ZO)!Cz5*fN-{;Nk~^bx<X6MYDQ&{M*vj
zZ&?09Mg5Zf?cDkm(zn!a4*Q#a0lnFlR+U5u>kP9x7ynyTeXGJ>@)!(wa0Aqc;=+JJ
z0KTem8xlAwxDzY^q#@Ao%07P?{Fc@KvdaG(E8>8pc0kZ4lC_s_er8q_ykd_QC9oV=
zh94|<s0InG-X_!obA{1_l3<Q01rhY5UD6-3xZ%@9e;uy;yCSHcjDyhY1>sACe>}jB
zrgt9<NER-vuH*1ijiA6vTJF~%|3b7R2KVG8FzYZE{s<13nFgNY5SBm?niX`hHy9yY
z|3$b@1^`!rf-|d~0?2&Dz$O3<iSS1~He3>lCgjDgpooTd;Of@hb4>#7I$@)$B*1e1
zX926AA$+X*F^n5o90>(<@qoJ!d^%eWtQ0{m0baksx(DVQ0fqC;Aqb(TMu5QZ!8Qh*
zXz>5V3ctc&U@|=a{HK5d9RJ!F;6fNU`Hlc1HUVhn@@mURfdyK4u_pSFR^W%KglECJ
z?Z*M@6R>hHc+83|)JcZetw)9QK&k`l-NS=by+I&{FQb0~*k`%_h6nX;@c(r5Y8MEW
zwA+Y+U<;rSk_ZgOkO)F!V21%FL;=%209_;e)j`mwulXt1ZUDYp7V6*euNofp@5r0@
zf7JjE3fo_TXa(G?@L#FFxlafT3Hnz4U;0-xyj%|k%Zx@+^1{a6AfN$X;Rbns%ohD)
z@;`>U*7c#*PneJmcl}Ca9rdg2Ef|Bwz_*Y*fN8M?21W#SMgbHl96lj59R!9s08qbN
z+F<wpB|*cjV`G4nfLOofM1Q;UUH*3n{jS{q&JNZF;C)7TJy!^*m>2_hpFaZ-=Kddh
z?*k@Bb=`@cs;=p&8I7cx(MSvg(4EnM2N_HogoB9#cSZvq3$5MQ5-U4)T*8<r#Bmh-
zC)md3%xJ&^Cia++jhw`Gg9)oB#F4#;L!3=q5R#|$vROHSMDZrsi66_djz2%GgB|<_
z{C>Y%)ji#sp00LGzV}w$=j*Dv_uO;Otv=_T`~TkZd0r24fQDEt?4p{qWuz`LaCWK<
zRw*@_xh_`A8{V*Z5<y!pds3VZ@(%Yn4fHEl5$1tn3zpn+0QW&d+KQK;rwUluH>>{5
zP;n`YMK6eAB5~kAYlB?hI@s~xO%=C>O`0bxFkNUW0SYx9><NX6J^mg^HPn<eLq@hN
z6StV;u|wxd@qul#vVX~y+oe(Di9Nd`Nk-<x`;%9Q60M_H^29_8qdN>8HOwqp(rx4=
zM8yk+*g0z%on=e(tjmk;#mT|qashmHI#58R`y|p|#crqvx2BS6DHNk3&umGew?22^
zp3;HP;KZK75@M)Ki$8yPi2iJEk4#Ra%`i)OJ1u}@q(S@*I!0(~FyJ%)@+^DsHM7j1
zj8@AfZM;9}I|B5w4I-cI3#B}5D4^D05q#ulU?gvcw&tK4tbsr*MH^{e<W^-F4YR@7
z-!Cj!@e(eo>B0{r0W2<qhS<Js4JNfd&2~5|2B<X641r}#Uvw6aohuqR3|tLT2CIcG
z<7wet$dy1UCOZN%z+5ZrEXj@H2o6RADe3$i3UR^01&h6|Ho?PB%S2jm+n{YwVywi~
z&25l&Ngx3%&o`MMS`E-G%j%J=e4SFB6HO?iP7Ac}NuD;HLGI9fmGEEqWWrtBZ6Q3U
z)u%oyP>o+|L0Aid_Ws=^Vru@(!GpeoqAzAr(4W<lgIPYmu<%0jdtu-1|66V*&^!Dw
zyo0ar-`?KI-=5z);~)3JFq-p5<YIn2$E-;{&t0;R^xuM4^6?++Pia26If>-NN&c>P
zSpq0C{rD?|WE`dF^zmCYKzleBdiGhFeB|A)RNpUI`OL?BgD9oFIQiw$8zV2dVa}It
zoi@{?lgdI<ak-+}(1B#xQ;GWNXbskNX)K9orO~sabXGZtrH29S<xCQux<EOUeq)2^
zw?8Q1z$JmP`TrHucjsbH)t(+H6wZuH_@^=l-DrUw-w$AL<DVy`R5;&Acng-Up-fJ-
zK)%c}7FP^pqt=~vfNTXA*AOwJaGBv9bT!E(4&A+pUIxK`4<8AuZ1qfgt&jpn-ETP^
zO=svwFR&1zaa*#Eyn06TeUSR}0&r&oTc8T^p`B!@)n(Arm)&rg24B~Meu^EVROewp
zlg<!Y3dL<}J))#}q+ibDcz)<ko=A@wNX;jNVTNL8osG(1v?hQdsXSQ8NAsd|csNGo
zun@_xT(r}9vH%$%kYYlm!B{<KY3jRDH5ycYiwr{&fiu%)?O_+K@n%*kt&w1bPgh{N
zh?68>=nu`llhDn*Mkne5JTIv(8dXf{I9Q^NaLgs_73xpH;-U5BvD<Z(1){QKW%~nx
zU6tBa(_EFJ69NqWq+87!_%bjl`Gbc_sZ8Nop!{gEb%Pl9RN$|IRvj&$P_}iJ-jZsl
zWoS2Wg#?0WpqAEKE8oJmJ68lZLzsdWymJFigMWBj<oYcrbFr#)FSJZ;9~z1z{uPUW
zQJK)bX7THBAVle3Z^-qbtGiEh6}_r(Xm8g~W4865HhZ@3Jw{$d4duZ|IZP6M*XYBj
zR--S9GQxM!;~lwf(A#m%i$p$$)uhp9u~92Izpj(YO4!jdS%ZrWG&j>TO-~*$%UKff
z9iwOIYSwK{@g04qfJ*oKftzi8@{ipKA9(^%+4ar^iNDjM=C&I#0x@YBW6?j;m-$0|
zQR%J%*7(0T`y}A!`v+sE1=3XYQo|^*Z7mXZgt(a#$O$y<tXR=n038hILMDOFm~^)F
z*^iiU+m=+W1l7BO!Ehf&4HwfW7%PZG&w^yP_?}cQ%=jE$g`d{pF*?<LA&f;eU1&=J
z$utT@3!5s<w?*HB^$%9$UJ&oZQw%P^v`L#=x?Del=VTh#>K=LdHE?>uEiz3V_f|Z+
zVUPe6;aW>!eWSL8WJ0WjNMRNaFLio>3YH@l)s7e$ONfLCTRvNXWuWrb2KX${yO1XV
zCBZP7GKP+JdXJVPN>n7bPFjT{8%H+8QtGvak%6a-ONk5EZEXk+5M*#M-V~p$U^!V(
zSyGZ0!0-kRuClfCbfKn!nuv*M35q#564WGFM1L2MaX@P+ril6NDgdX|Yl&o-I>pzL
zC2dPsk!(g?<4}E{mRvd{a6kU1_E_Pf6^YYPz?{E+Df+l1S)*7z3Z*5!acUjLK!&Ak
z`wf=5p-N2(P%6*GbcwLgP8i&PVX{lO@}Zh+FG%4|dEr^(Pz}gu)j1TDH^I7l%UgLl
zl<IV*m|4mQ{0V~@P{O4ij0vlxUI3^|_66Y9X)H|cA8xv}+1YDV%Pf>r3kI|0R&l*^
zMJg;yTf*wewv5)1f$67F4F7v(a7uSecpSD!U0G65ljTe$bnk=lTAps%4+od6xgC+U
z`VUA^TqwJtc{)590ypAwAWarCOk}{MqLe}Q;tT*VpbM0MLLiw~jW=T35Q@RJnpvCx
zZ_paTK2}5R0d7wp>HP;>`@K*fw=H*;Xj9s*a$V&(1v&Wsh|EC4Z9tG(Yk*FvZ$Mw2
zV!J+#>n2*;>R)Oap?m+=kboUWBlu+yu`4w5Q&5Sf=cTgVkE{jtYu!Fbu{$yF6o-A@
z63SmI*!<B3)J(3}25}=vvZc}A^({-l)peig9g|0I!Ad4M&8rs2%Op))G3&D}ml?D0
z-q5$-Nf#?!e}iaTDq!u>1-^`c#4@Ijt6HJDOwfQqDK27gwE;;=$c*4>_9b>`8Y=0A
z=9vrZ)Efo##UpDXd1|vS$3Dr5whbt0G^O8urDvY`XA5CF!?cgQVp>Yc7GF08UNBHn
zG5ENSTytxt1+q1~)$~G-k4=!&dfhZU(anJ~ampZ<8BUN<W4>_#4%@wnJP9G3K;BQ*
zqpwMk<$;M%?mmQJ{r&6hu_>EsD(2^m2x|h_CpQ|=k3n4rdzo`q1x-y3M|7=9QWx-w
zI=9@6mOvL;Nx<d%GRn)cn0C~PAqPZZb!cd6HSuCz&MFhih8O810f2>ZGsx6wQqyZj
zQHQhjR9Y9%bvBa#H$YA!z%&bNildei>dLQ(l49IQ;Jua#Er<bTf*;tRQhhhtWZ`yI
zBA?4((lU7&(b83~RPYU25_fu_rs{NN<0-nKt-)mW1(n?oO_98UE5_xO#25<Orqv%@
zRDT{vkmN&jvJzM4>OS?6&+!zez-lszXcpH<R${jL$CiN);cmsi1tq7EaD@99{8P9B
z9O@%(VVc6x7UVXW+)?mtvFZ}hmQ;@Q1Ov$@aTwFC_QvEVa8ep}O}$mh$>uo<F*77&
zj2K<t(ksVBu54m5%G}c&OmlQAEW1)&Xf6R5TBNfB^WiODuo7R{2a{_~*no}8eJUTi
zGn9o_`;vq&c7f-cAgFwPQsmdLGv@e>lM|L`W*l0x;u6anFdQzHd+1??Fm$AgW$0QR
z41<_8SPj^NX~Vn5p&CG<P6rC;s6n^&iyNd=`lJ^uwj+_~5Y`pF6kU^nZ7QX^JSxRZ
zy<$OLI%j0=@z-E<_-Dl$vZ@N((qnjQz*M!~);aRE>;Y9)%wuG9Qof;%yO2u2k6|oN
zVg*vN-eh~DT8n1FM7K#WvUX7H^$_&~&LmAtqvaVPM<&ro-c%hXZq4e42)*Hlh}#)a
z?KN2D5ZsF%OK!^rrJu5E1K?PGWU}&=W{(+jrM1uFlECs_1qQc({A9IR_oxNOZjeA^
z1TQ`FEcL8<k7O97-w=wssTf4Q6m=X=!+O#ULX2R7H95J9%EGqEA_<3PP%f-6eqT*)
zq)sNNh~?imSf9dirhI_qSp}KpAVwJYCW{grgaef;Laf}y=Q3D2SvS_e)Ld;j7LjKf
zz+3jsE<3xfItgH5ehONLT*bK+R_(y@er^Qcg!8*wSsuZ*)&p=?SuThDP_9-Pu2t9%
zmFWM`k;~ge^a|<oc6l@H{E<Y=P7QR&m_^H1{3H127@{TA<Jq1SyIy^H6rO)wND9mR
zm+DM+8QZxo*JU`bSd_<a4NB&D?1ae$9JKZi28+bEuf?F$asPUIJe@Cp=Xf~#*8jde
zl<!{X2jTmSShAuaxkTu(yft8$6%4Vt0L2*+QGslK*`?Fyb%laCff220fWvn9jRH#U
zS?AW;kCb#iUmO+8@|2Frl<w_~Wale5((i3W3wZF_HwE`Be!n1hf2;?Gl)hX~(gHaf
z-m2oa^ian%b*i@|R1jLr9`%`FMJ{Q{rjr7{O67`->OxzKzm4cZUnGyuLQgL-Pz@CY
zp>H&izBlrNt*<KgS8hST$xu2O(e?kUN}!J$Z}btQVcJaxrJf(aYRpEIhi-F>$lcRo
z9ft`hFx7Rt?3~%QO}q-Bu7dAWbgBX<Np0?sFiS#A#F?~AT!cq`i#rQaY-9H=RBiR-
zZYzR+IB?0fV8Q94w9sim)L}u&|63`^qBqy3ktu3Z8sxBBzK_@zXZI{lz=WsZK1zP3
zVEL$nVx2p6R+XhILYg4_Cb(v(CR0bv$WC#b!3Jda7kQ{szUW}nSkgaH!HCq|j26fd
zKFDGgdN#hO!ZQZbvFSc52Dbn=ZfIH%xFBYuF8m-8Fumi@72uklAa;%xH)YuH1rjEP
zs+_~#HE(7JID4^I#_)eAI%9Bd7YfDw0o0rW7b^*DE}<hMX&2g%0BuZXH*t&}hIZ#@
z8&N>A<b(b#7YsxPtr2@*yU@nBy?neJUxXoo*ZsOg2R|??b`J_&hPXt?+49zang0VM
zOKg6%s7MRoWyF>qfO~N|ssVI&I#8O^l{KLg_L0NU9EF|-w)_|}!x@3m`R7#c`#y#x
zAl0d}@xkmz$AZ~!U>f#ozoV(Ts=~IUF}yWksyb#s9@tv;sHqZBsvMNj(?W-?F36WB
zoe<R3jd_yUPug=;yy4J~l3^3gUBNYNQ5Y9Ti&!0Og<qywy3jbDytTKErbgb};gW40
z)WxnQftbon#A1pxPpz)B)EUr^u~npSaN3ped>kqe!98cNVY$`72F<PkOoOkPCq#~^
z0_|O^p6+uM2@Ig&%3hyfSRqp9Xn8X%O)W_5U*Pk|_&$}B@dQ5?m<_&jaASq)TJbzz
znKN>L+H}wcZI!fRpS5p48fc449omBl7>vbtTk%;>EI7j^S4Jy%#!NuT)|2z;H@FmL
zjC`{?D1v<6S^^F*Rva$`M#k=w5x=-9wOKW!g8~AUnnFXcBbXa6n!NwMKmt3@yQ@<%
zi~+?t4tTho$~@i2iVp=qqcs}?a#i3v<bZE^`bY(g**k6ps2VyPiVK?zEy>7{1LFfT
zqv;nDS_#FiZ_x{;qRNdUVPOIb4iBvnn9hVbGHT>t!4{srPzS_L`q9$`^_O<c;FwII
z;#Y;GSzR@(8UTved-H8r?zm%GWVda_uvJ)<->LmPa;Gc*>^Q!1Z)1M5-sJpY#aKlA
zO-~IwMH9P3l4$D!?PK^-6Pj0#ivN9lv~%Pp9QOY8b0him8E8G-(<6vR3kJ|InUfTk
zQ@1%$aBlin1x3W0dU`y$7`>^xuFZIXoH{hP1n-`9e!E(Aa!4!=6TN-dNOT`d&m2&M
zM{}F-5sqH@(*eUl|5+F1W!$D(!4Tg|F%3KLd%ncapyl*iU`eH0(iq;V;<xlvbxe0l
zP=uBq!nZ&E*CwokyTmwNY@mUIYjcyp>6p(hKmtz&f!HCK&qa284F%l_uun3o9F~c-
z-|N9h)0H#FaG0L6kAoP5Ffu5?;vG_~^n=fP!RMiiUYMG$%y+unPvoW^eCpv!&(fbk
z*F39|$etEY-*W~OO>Gj3ypPJVC0K^qG0+u9J(Q-9=`71sn5u6jQK-{m{b3X+P=LGK
zJ#R!JFEcqNuzQ$#5vi4&KfPx`-N&*7AR+2yl)Y9zF4*CG(^AH^?B^P`l)O=JC<6t>
z1vYI77r2VWD5mP51>uzoZKxGIWAd><B08VTu}hGQQ3en{wVVe$`wnAC18BK?28Rt=
z_zW(>tg>w6>|R#OQCW(s86eFx4{5W|6}V6qf%6f?fa}00a?&ah&5F1kh|pzKLR?dS
zl`8^EiV-byh=C1UYSB0ud(jyZ%~F*Bi>rj2vTw_o_IiNVT8R;yLd{V{G<%|bWRX_F
zu$F~N%fM!wPd(gN0O|LdQTao(FK=2q0UhK31`Fl5CtEcfzRNG)ZR9@|oE($iM_hyP
z!~KPEOx$kw<w0m~X>uB0)LyZToN4TPXO_~E$9$0kK6KiDCBECe1Ki)^`{9@E3p0g~
zlkWeK!KM3Dbo2`G@A@Ov>;GV|eszBHKV*T9zka1}zI25|BY!I<`TG|MIx(O6+K=H=
zf#~a${t(sf!F}k@PQNIUZ()A@$QL|Oa<jZa*RVO5@pZk(NpP4G9Dd9J8~7UE56j=U
zR`m7HMKW^}1}p)N10BqeT|1>DP?)|6d!UZ`edf-y?A*|a6xs5w{z89A(IE1I83{1(
z8!w=r11P@V@87=!b@3RWw|##|#_q%@!-x7MT=<#3$bup^xYfjOL0Z!>16qPg5M6pm
zBmD<_TXLrnKYr6Mx(KygLZ5q)mV7!S@HFJ`!y?9x2Z4TTw5_#W2It}#2?lU5Q_)y?
zf5FwK);DR#gR`wAY!0xy{f+XqUyCFCX>Yj#ua~RVdve_TQso~PO#l8KmC6D}o_FO$
z=;&Z$s(;^8xZ<j>)l>Ohi=x~P_3gLT#bepJ2$M_{5d&_cvv7odzYN%hB9`I*GN4&b
z;zFlN46`4S@4{*lV3&ky5Z@Gx--fJI4CIOkRnT#`ELm8v(h(VD$Rx{HfZ{x$rY$Cf
zl}OMwL<P$f$jsTQ>lC*gyVD4VA^r;gwC|47&;R?y0{S+XR2{HRkq|W;Frp&l?VR2e
zRT_#}0D{OA?Hsk6sk*f4Xy=)=iPDu<?L_Ec8ujt#5Ac@iAYT-2NCK)$V~nR01Xi$m
z*n<k$KEjZY1I<=lWZoa{;kvCA@X(Vx!ap3}Q!F+o&{gd3riE(%GdR1)w(}P^&(05;
z9f<mVP#boAMfLC`R!Cr_#nV4$2jmvT>fzbQ#Q)tXe-)<V4!?wovU!uLF`D<2NN8~f
zW+kHH-o~H?A77`Vfg=l{?uIUccj6qiZx=jTTP|Gp9Z-GftO4`%-wk?SJmPl5F5b1(
zm&)O_5`BBUZ%4l0C&_TX*i9Qp+=&lLrj|Dr3RI%v>Y)ZO+nOG)2X`wl@n&SZ-D|Ck
zBpEM|I}VJ-7k5Q;$7>bc*6T!)O21;ZwGx${DBy#R6j2V8p2fobfA}PNr<bGc{7$DF
zDV_y&%~D-!JsGHAw)IYID&7E1%zTq8o&bios`xGXpXo`$&!#$NU`sf7Sc2Ivp;J6?
zbENV5v@gc@t>zM^<CZKsCGfvZO0j<i5-(za;WC>JEad%pdoM(K#H77bd6TB}FS6(!
zVHjvTjv014d3J;1=|VJYH#%LWRJFSn;8Z9{ct9|fod>!Vt@aa0y7U?=dexRZ`i>2c
zvD6n5<;P`4Jmh<uHi`4)F~wen#in%B&f1gG<Io<WdSny&ORh`P2bKn|*kldZM#fl@
zQ5~y{8$(v}siM@yRT`Yckf(HEH3^{n%1XsKsGyD04lC{$X)bfwGDW7)oaGY_)XNrz
zPXbBv2imJet~_LxSqX092kD!pp^fy+7zNm<FQent5WaX9no1xve$fgAgoXK9cZPRU
zY9Py`!VloY3Y8e=b2me`TcBFSYJhbwDFKIvYGA4^rK71eS1I^()}JP9vk3y1d_7I-
zHY-t`hp{$J^}<T7JuncmhY<-|!4Y^N_qGB9<-M5EovblwlY&Q6T^-UcEyL~VM0Ftx
z=ndOGrFMJVWO`lLvNJb}ER&w9t|Y2N$386j@D+EU5j0yiZT-=on)YR3=cLYEFJAF`
zYp7Gv%dN=oVzzbZHRH=n>~56GJJ?cP9hN-L<`=_Og0GH3{{st9>V4`T+P*r+4iE84
z|J(Bx75&a_7on%}WUsm*^gOA=&!a^;iKR=2z8%WZXEwMZ^sc8viSLKt{}SwIFjHjn
zZk!fUS}OQTkL8UDZ0L~i<Mpule7OFb1vJPm6Wx=5m$%+oB_kTfWvS4$Q%VBe);*X7
z--t5vudu|ol#Id<+JMq+C|tjd7`w)ejh7&7K=E=Z@6jNcz2nvBSbolzy%k9Mx6TT}
zeLwA5$R~;4GSXqLEPjfvHlXxq;OVBGNT1n@#uhRIVMQ)!gVCu^G5|Yy!?gHMzhyoZ
zdn&Bfe_XMv73a1OO2x-K>i)Eyt1l|U90w!0b{1B%&KLhp7*tHWD734uJU(_BtnFgh
z9<`GP$rzf{;BJ;Ct>6PVU078D7VTeGCUSIMWTVUdt5P=v_y#e#hYceTjt4SEqHwZd
z?HaD5@W?c8&4Fd{94^~DcqP_HCRk^X{{|*j26i#a5{O)_mO%Pk>I<p00VW+17=pqK
z%*<wW+_0c|Ot()xgUA~A)+tm@y*B|v9NJ6ixzbGt8c<;7KCFRc;lx}~Lul7iFM)mv
z%b*=gSz*LKAI<{_)n8HEs4sBfLpc){8cjPMeHh}yx)iZJ2+K-@qSJ&08I<Deo5?zE
z?n(Emz+{IJ%_Vyd9H~}4WsCrqp@T2d1xpbuix`qpVp;-s>HwA{Y3W^V+>R#(qg7zq
zw?7@+u%u-oPUzHzrDr)=c*w0aAlU(^j$1wq+h~~rnGqG&^83)!;gGO?#L+!&RfP7~
zHpH=n4RI9f`OwP}>9d7ON9gWBm3ltJ9CJn58s#Qqw3?X6ItFvZ<5FA+bwUgjpK`;q
zH89y8<edq{%#a7J+2~1)!<mS`)S5>(bae?>&#WH!F9>nmGSh1j-Fl9&fx?vl877}Y
zL)5Nkg#^qBOjgeUKUgp7m2^K0#;lB-R<A4Z9gjh`o>db|HG$J6xe_TCEC>M}O5wDk
zRC>VyOVT8%1}vfmRo0+b2m?Hv0t|qPM-iQ3(qtJc2g)e;4ZF7<<`FoZYqJO$hqSWo
z>X}lp6prWQvuNmz;co{<YeZ1cY{~&!o`PgZFbE0xm#hM7Vt9I(2w^0BG`kzW8FmHE
z!#r+az}X^K=($-qJdM!l$_@E-drqRK4atO7kPny@ClPxtrG)?@w)CO^c6T4jgatW0
z@fb@CGOG({bpu^4xL5OK5}es{S_Zr9?7Ex;3>Sj-p^>=&?Z)RASE}a9=Fn9jxoiPb
zulPKmteJ2To`Ry|e)N3b4et?;Wh3BbC~PXtI4Pp(J!nu<QxYKej0S37f}L{rpaeL9
zlSjJHTms2Mg}(mVciB>O7;6}Q6WTJ(3G1;s_x$ES9>l2-@o{ud52Q<kOJBK9bU%6>
z#qZ8zKivn@!hPVD9?#lWy734c#054~;105*Inw}@KiqOb-!x$4{2vn?yAq3R-n!ns
zYsR75ZLJqyyy$sm%O9Z)azZ6JQfPC;9Umd{uENyI;{PSHzk20HjxNc>ei4gLYDj@|
zGLK^_=)4a@*q0fJIhII`D(M1Th7Mw=V|%b5o6@X7^y-k@hkcK8KZ2vw9#>h|+shG;
zlmp{bbII!QJ1At|nwfA3Ct{U92C+Oj;0~V4`}?Roi&o5BBuoDuqGkO_K!d2~d2=*S
zSgdY^J?+AWH^QH@P+&&k$X4DSTZw9pxd^8D=tdO4IO9o<^k{RcE*28tsuRnSY=SqP
z<vkxNjs)vZtgX$^INWvwXaw{14O~*n+EJ_MwN|5Q&Ba)&!q6NRG;$LNO*3%zzA9};
z2Ux}5FXA$gmyWI?{-z=tK!FR{0vHPlG|nA!)V2^Sd|3CL7LtyNq0JzW$!6#kIJ_Tm
z!JrfjGha_Y<#wT&1T2w0cWe-hGlSH<%3Wm?Ar@-f=F|zz-IkFW2`q;wUb`GMhSMt~
z%ZLV-aXu=CeWe^=?+Ilu>TUHRmvr+8+8o_k*a%jp(1)A}i;At>o%{ExfY=^`GG=g%
z`C_ZX46|O=;)+Kk92E>su!N5=KA+{9lX;sOVikf~I1H8VNB=pvqA|Kw0kaCegU|+t
z9F-EgAcs-8*-eowwDaffFE5II2R+n#&VsOeEz}E3_c82nnu+wcLh+7X>4!&lL~oFr
zQET$F0RqeVCZISLq^<2-i#<33bsLtZ$%0F<39l}S60rZc-V6N5i%KX+XFvKYZArx}
z3~iK8KZ!$L;zzuS{K=bT9Py5PKCpW9l{g6RUK_@Tdc@oCaV%83Wzg8;Q)wH=m7HuF
zS*AnH&`34uZBe9>G6TJ1T~UIkXEB$HT0JYZ9S0I1e~F=^3le`6hO{L#a^5=?+veud
zHgRjgsMtS*SpVWI<6T@iqkQn1jRz4yPk)D%M?GJ?2R6*h!9U{$ja~`9wzXnn9{WNq
zC>htpPYerb=)66BBu{Pd<y&Y5|E2oAA{JpqE=kcHet(yu4f{)aZTTnQI5FUs9^{Aw
zgkPOIctQE+aE#gzXs@TD0AIvsbiC<c;vmdWUxzc^6^nl>H^MY8ok%HG+-()pW2&xJ
z&!0z1H(%+AQJlKfim)5@QD}19jw0I|T;(<d;$srUFXP~6sj!;!q)3Yaj7dQ}MahbO
zjjb*>jHr1U<_`&6afmjskF^!YFn9Aqay!+dTmHcyFi>eIN>2_zk+Y%|8*@-V++s8e
z91zLbBBP#DVZjce((7Xxi)>?OonlM${R_cz3tp;C%(fbrk@N+~E&syT`Tu`3$i|~$
zX3!yV&6wO*Mhuj*4ot+>Z8|If24FQt<uMpMVOucUm0(t&vYfF3-+(B(k~cu|*5SKa
zZ4ghrr&NMO%?#H@KuYO(l=a~&+=p1C#s=kWI2bmJAX^K0<FGsy&LVrERXk*%0z007
zeoq1z^D^kNa~0PF6(4gb3xm*UzG>jFO0*6|n;}$&gSt!JzHUzBhPEVy()u*NM=wXU
zdPjs+g_-ESdOP%akuf+gAe4>4ye#!&g~X2z`d%3NHY56>9*_6>qQArK?dJuu#C4@z
zXexoEf?>lyJ3EL<zb{ec%52o2DQOi6tI>x~3*~F?8^6e0*;6UJWn%0TF!s_DD*9Z}
zuLK{6qNV9cl~46gO87dlkBJY(B7SYQ)xu+lVK!1+`G91TS&WtpoCBl14+YEnKVliH
z#(~ysi0OjFzj+$^_M5HQ^DcbaWTAiB<OxM#Fy-gaZT;M44N5A*cj|hIc5dVsB(%>I
zW_SJ79vO+WU-Y8hAb9W{I1}j8XhuO1sRC=_Cnm&YvkQ;a0m;hIc_e%8PeyWN&J+Fd
zUg-gSm4j4s$?7~hC}cM#MECW2h4`<g1nUFUwDI4K|Ga#3;@Q)}K+z};fA?y}@nu6a
zC{KCwQl1X>8m?g(SzCI25?Id1Qs%9ot-{}b7-R=eGw4+r2~a{%tzBp;0d_%XKufeI
zKXN^iri9B#Xe`8{l@M*<gxE;V;{*C5tD+oKbZMf`1}F!B86OedYw2nPni&&L!F86Z
zo~F+VJH-fbix(ML>&a}rr|T9oQWE5SC}$6(!R4B*!8&nzNlK;Wr983+=goov3|}2O
zg7_6q@^V^m*v8usRm7`3u#Rkscg)Wj=c|8J{DCgiBv7!doLHDqI~bjHV>z|p=8gnt
zOt#6RkS}UYH8Bv6!)PgIs1&<oq{5tHF~C=bcL^8ZWDUDD6bwKHs8>;nT6r(x{nFB;
z)FMOZ%7~qZi5|9|OpfD^_q_qP0YA@xvRd#WsDh*hEhvB9$?bkq7CQ|E85WTi2J6rX
z?!Ix(##=fapW*V<ie&pGW}o#Oav!{}kyo8>!qj;>)VZ%0(jSIpeKqh$cl`p_^X35M
zKVs&ly^ku_6a_c~+-cSOa-VDiDw0pl!1z!KEWKt1buM<~TsBEfoD8KWTA19)#I7JX
z*4wvl@A<ba%BMp#iMz0>1Z?Gl(tp*vCd<c;_Q-92-HXxIHbB>*o%`S)V>co<CjaFX
zjN%VH?Wz9W@KEKhKak4(7=rMgTQA|rH0<{C=ngx^%rn$5+FK&moxz<ssZARqa^S7W
zflX*+-H1bDc0sFI{;P68{zB1_!=h7yufGG*`P3W4e(V}6$$NYhbZtO#Zy~Uk{Rk%X
z4#}84+{<qt+dXd%BKsQ5*4%!X*Z;al#s6QJ91nMn2G;bW9;OzQyldhoCM&JYC_{1p
zt+XL8C=3Sr*;$c0Git|S32J7(p^m!%IbSI~Ba2wcZNKCVxkEzpq>`YCq+j+QjSlue
zh+MC9q9-e2BPk9}OH@85n5fK6+HeUi<fU~sO0cXZ2TV>lHaT07|LRNMp}W}^Yk-QJ
zXz+Kur$_X_zElda!LyAb7-Yv#+IcuZ%Ty2rE#ZI$C=#=86i%bEor%QS7$zDSu{!QT
zPrf-Ujg%_SRl68x@1cfr&_u{sidc2v)w#P)N<eYK0M*HhQ(kRAO0_^r%%^9&<eYNU
zEB8T3C=>CeW%*!Il#w97tWI;LhG;S~E_M1^0GL>1Cd``Jj@0swaSuMauq*+q&?gLw
z(z3oOuA+fj1PfacORuAxg2Van452~!jFC;=r#!dR!cOi5m8Q7>1OOG;IWY;fqXc&u
zfn2ag83R_iP_z=KL@`;SoLB}!C)jquNx*mzsFRPvkL|z?+wz7zYfhy!ZI+%E`GOGQ
zz$ELM(lMrC4fIKD$>o_zIthk1Y@wZjgBs=bbsIHkh!iUT?2wWxAmDJx25D||q`vL8
zmz*Hd+uV?`@(I}hU&S4t1o5<nAt>?0?}ve&G3v=P81spXhB5r3K}9O-X9IgvVC3Lv
z;N9F4Rs0trFsZkq!Y@FTPalwi?p7>nLm|G{E7RoA5{9@WXX6xULVt8*&U^YoEy1IS
z2`04QTkp(5mc3f?IrRe#vj26j#FFgKq&a<lYOP5vtkr*q?B>7ItI2~~q0xmkp8Pf(
zfQz1rg838Zpw7P>rh2r;M(_J=2?rkWyepSJ$Pyj^^Oobcda`tHzb{|h?Mdl>g!B5u
zC*y^hHIu9v%prF?-75nyTC~HEPfp)TZW1k_WuBa6BzSvP6f}$7VK{^T+f#rxZ@yJ#
zlLw2#`8_`$gjl&W{=jC9N`K+$-0mJ%CXVd)W#+SmoqbbLR626EAM10c`A^(+zEqfq
z)2QMZJ@)=Uo_rGH#=F=08tw{{<i2`iCT%l7wn%oa!9H08vRc-RXeLJHgxlYNkMX$r
zIt%F7M|DK$(3(I_Y=&$OLlh=Q9M%KLR9R%92Rk(`pT`jY2rNkbsBEnN^<G4etjLGe
z^S+0Utzu<q1E3=d9hYy@q5J*luF|#8_g4ZowORv`wep)Rbx(rwYw-#IU-hJvP9p3u
zufg65h|C(U5NadCyQ#OyF_;^5F$=ZKF`hu%#@#W6gEloSxClYJb0-<R3|7%NhG7i^
zFjEVBAGV4t2e0B%;JpU*FS-}D$WqK!e1R_1BtY3fs*sMz_Ox|c3v1~JX0iTI7@fkN
z5Sd))lfc}FJ<MgXqbL#CUR7L;;4~NxLgUC7E^lCsBH6S8lm-YkB(c2J!D!~5uETYm
zH3`_7tCho0hsrh!KR0Eaq{q1y0;?dPU#%c`bTm~!R?2(z{9+jZsh!Voi?+YG>XEc{
z@eJ)*)nU}zUkkz8;O8JOXVl_!f@2JSauCyJY9@J90MykQ41*2r(20`=5f>}$bO8H$
zSl|F#M`%Q0#ymlv3DCn^J$Tu<mxIu^ft{K*<`;}(P}3Y@re@0*$sjfSs;`ruBXSw^
z!9@+qQJ&gSXDwucs@2$@G0_P{8|!@7=LAJtncpqm#1i^9`f2oKD**<Kw|eTT*T%ep
z1MY?&9O{?K6Vxg{epZgIY>{9Z6k0PngJEcZWdp#_MF@vvZBX<qm^odi*iOD1Ns@w*
z;vbu^lo)>=YX&t}9;g!+CSjsqyBwd;I0Q+)uFo>k|JE&{$JWov&L6cBk8JeiC)P$X
zvc2G2eGSGONJF{b^?`~c7T#;mj-;ePumH1HhPH%3v3GuKQ;`;_2BQyE9hT-L&;r&X
zo*yG8wPevbf#!=Iy7u^j%|li`lSn$Q(E9IVNsFyOs>O{OmX3+1W1C!y6d#rJ?RVEi
z!3{&6Uz$^^AKw<p&QTGQK%MyMEI8{MD~f}-kU9Qa|6H&qL0j$P{kC<I4DA<5zK_G6
zkRPHb>7C)uS%3|%6C8Jd&(z&_5f2*ff|E+TAqdo)#PVQ^k`q^3P#(jHmA$a-KMW=?
z>EpqKl4vp-*5|Q_;^3&q?nXZ<YL%sRP+(lg)VP)p2886nDUKIo)y#3Zy^dftr!Vq#
z;{tI9lUYx%K`tr3VP51rLH=sg)%c!*cx6)uc3|-{&`n!_sd3mIYUCj!8YuR(qHeVU
zfPg(TrVhfX78H&nD_+G_0|UbaJ+?<9$V@6u)~ki(I5aayXZP9rTIL~UEX|4BNx@DQ
z{d1HvB!kZ{wDIQ=hhzcb7>HExqfAQ!0nX_#@c1!i+3^f<E5n;KaK(r{$!T&EV(17H
zWUV}4DxSejq+l42OOXYfM{#3gdw>)j4^W6f+3DnfK|W^(nK87MO)VDV22;5C5U`Qb
zRNba$1I;N0q6ACXDE=xaW?P*bNvTU6?WKBxD&flKK+&eis``=|jj~8M7wYW-B%rv$
zeIDcvNugH))fCzjOb?832Bb6iaziT30X)EE%J5?jV9SNxgBF2kVl@KuP86ByM;Fk3
z4NHv_tNCmNonqF;jgaLg^t`%|O5o1BjmX~zlfDj&%gw*yRFyBA^2R{CBgTfmJ8ERf
z(%81~v-L(^gr?N*BZFX&A{^-r24pvmDVF-YlI-<oh68j^>?e)*CwvsdqxS?hKT+k!
zv?k2J9gdXd>EJPB%EUE_;phS-;M@CQO2t8}75s{4^^bbP#pyOAGyfaK&<u=Py>6*D
z*!C9Im6F`_r-8rlr<hm$+7-r+Wux!SUTEd`jUwo_hBRc?$&rPniX?MuB6;s=zKlG3
zpXd{7GlOrPbolVozk+k#ZV==i6z-`G{pcy*=))JV+gdk7(VEjK9~!^0$BMVv$ezE%
zRP^H?LRHwte@=F+!<PZyBw9M*sm>N5X4vOV0oHu3Gu{CdztNXqLXW~?A9xwGP)37>
zTF`rnk-QDm@9Kd;?}j!<%Hk)t6#Sq_7Ola=&!ELTb%lhb#mLnkq#xO5C4L5*p&z(}
zqh(!i61WznDfYIC9ZU>oThW$n111#h-d9F4`?6{APE4jT_JoxlPs4(dNt`4+J}zI|
zgMb%7f#s~k9Qa)zSdAwCc2+mte;F+J%g_Y&2DAgdRB%erv44-j&RPkKc&unEK_JK4
z<I+w_rvQ!eKR}mu2Af*82bdVo0|mjN!3`Y@Yb<9?;UR~YVo-Sw-(Oy&7d#`sr)E_|
zr4U&~cXu$27jrh&Yb!4y_I)81Zy<uEWxC^M7`a^r=^LE-ck~QO;#ZjcncF9F|FQbA
z&r?s(Euk>k%ylwdz<r+X7`8N8Fdh~O7iJPH5*FVE^=wO+RZy0fXbhv?MNk-_Ym@_^
zA5e++%CrR~QmTUh)3se_kN~aIKoffuWg~Q!3jupBAzHp-X^+$?W1-_ah6i}b9G~p3
zPVup9N{k5LV7*%xYLpBd&bWK48`A+G4`wa}8}|-_%vyjnS?BEdTggBKt`MYb0*(o_
z0kMTy_Ikr&C2^W_H)oVKjXrY7iCpBK26ky8R0zri4nYQs{ci3y(^UiU3QxR<in@OW
zGe`^y({T1yEpS~}mVo|PD9Oe}!4lt5EE3lC`mL7j)_;P87tx1|u69C}-SZMXI~euo
zk-iCe*0ZNCtzR(yZe*1tn>5Ech$8wfVCK)j{^O5=$uV*ot@c)y->ZqMA~G~8iVw74
z*2a^{+b2t;x(ylPX6)=r_${6;I0+<Q!9c<7u+Yyw71)KTUv%YKu55JgCoy(>c_8sq
zo-e<J$uht@zB!8{nZ_|Rc&U{ep55Y&es{ghoblCA?9%qMoc1;%wS!B2Vy}kPe&@^~
zoJ}2gvvc!e*__P-Md={H{!nf(UMSa~dj$9~y<3urH=?&Z;3|MTCLIwTSCH4YoaM>!
z_lx()-xs`?Rc#(5PeLoVzhC-}d>V^5OX;!FBQp|MDFpsS8(_gts;Hbc;}48`wz3C_
z;HUaV#2a|upgdFdRBprK?U_eWq2pLIl*hS%ZYy%dH}Hb^>1;+nunQaxe+UDXu={pi
zJ~y3Hfna(NAJyGZmUuIY#{UPxh4}NKB1I|R7KnYZ&WSB>%Q7_MxiNy^AX)qeDC*H(
z)P9q4hMcbq2mCe0qoS)Zx%2)zjMyn){K<+NS!_eCfmCh}<z^JY_3wx&UiN#?<q8b=
zbpi5$5Izc(u%m(5EjQTThJ2xiUQ5%MlVkz0e8nwJrCq!mlQuln!8e$OO(qb6>KE=R
zq%(0k2StPyA;Sy!3Se2Q!K*(Ff;7AEs6i}>eVAJFcO6oJ3}TE4SF^u5P3H*)y0XxU
zE*Mbi89a-L5Jid>k%{RpSZh=4rKTU`#MPh=w$Ac$Y<AIeniBSc^T5gg_{S?LCmFNa
z>&fHNA>o|Tviz^KQi$5*%J+T}f>QBxLyd+G^foA2=cb&Yc7b9!RcBHU*}GuqUMA)c
z%uZ21I7LcV4lvn8P^p1~<*h;ciSf4K&Ym#xMjLEE(*ZzHaO1e;f2C&gVJ0nLBOJ=5
zq~>fK!16YPMGDZ9D0N6t8yQRGO*N;O!dxKii#Wv>F@IOI49f!~dyzu39*)Ok8rP>0
zEdRlf@ept|0=nQNz-da3$0w8yHaz8n7Tg*@IRa9}?2nwEW{1Q#oIW2!!G0$Kpu!0q
zLwySkFp*1f$(gufV%9+4#3UTFcUH&XR={L8iHBrSzVv{Sya0)3(-)87AyF5WB>+jc
z4UlPoZVKoP<1jxsQ-oCMXFyB`MLdGb;z~772f^~@^9E4fz%UP}%FN#BV6t6!0VUum
z^mtM}Fg5-Vx24E=okXOosRHI&RdS8b3I~%t2?h)in($skW+~Cp1xUbB3X~~Tpty32
zF}v2JN~49rSu>m}2N{O(8X9m<pOJ8^E)l0}hFDzn$!6pI#I6ENRvDHhn{5&hsSwEw
z!*)4-U8qTblBUqim~++et2n$=e8xvVWe|e4$QKa~uw1~<u1z=<RI~={O3Do56j8^?
z;!O5b0e)OCP9t@pt2=j4cUb>Wmd5c2$3H;8>QOr}1o?gvVmA2i5FCx6HE4j@R!|O1
zmc`J_&PiMZG>y?FJqCAxP;b%4wSp7Y-c$TZ1?f=daWw5IwzeZi9w5gV7staHPg`r$
z5w=t*H@}-2s?!}NEKFlvQ9-;JZ-<HB&{l?r1WyNHMKwy+`S#w+m>Wb68N-pnaXB1$
zQf3qR<-pF~2IXN7odY|L$6p~!99nNAIqg$0yHRY;`ed6bv1`z1{yH)q=9+4N);1J6
z6U$H4P#y0uvzSadec!YsQ)?uA*=A^qCX@sHx4+5Au{ntr6$%U9>$IA@4Bew*G%*u>
z$;bH9t6|Mwofo&IYId{d+R6jF2BZ?t^#%tHd>)@txEfkLgkt=2n@7r;lcWp251Sy5
zd>!1WS6Dm2PNMfzEF<9G2m-o53Fsv+g81JPN&KJjouW_m`&h1)D;cl!n-^js=q|-x
zssoXHW3$T%|FFxOkx#uh2=7Qx#$Jk!>83$^{Xzv(JRi==_AjD6cH;YfLI3m;@uy#k
z8Q0@m!jgBUiE|Sr!G?mBg;@Ngh!k%}7DSOzc@bXtK>ws1FG0sdbpc~GJ(x3nwYB<I
z=o1V3lFSHN%EmJ<ktjLKAC~VxzK?&9#QxMSNOj1wTkZV3$k~3;EC8*{CbpVYmQX9s
zegUHyu{SFZ?LhDzFgRTB86_X4LA?L(FlLC{0rP|p5Dogni$KKeB6lH^0183K9xytK
z`R`Ox^yUHDFA>CRkr%39_ZRT#n|@g$f|`sBn#Z+)Vq#}_!@gMDdZdJ7hq2tOs&j_q
zLb^W2?XTndLxPJ>(_MZOhwtbcmfXt7B1eW&$YfRZHho6exQfHiJR>@3dDw)@8408M
z6-7M?A>Rg1Ch5kFRX8jQ#pU+Eg)>JL<*KymO)+_QWEG5tjEfjY>A59{V{jASg-imG
zrbB-*C44(?dBDONRV&1Z!68^98b7!!<cbx>L44G;juH!X;ea$U3wW!-A<v)!Pr;Xh
zasw7;bn;+wniS|H1B%JAg`-$k^rX<G!b+Pi)Fdzt!HmP)AR8_QtctuAezKz=i%=qp
zQH!Uu5#|h8i_xAv;`A6|e$|~Gyve|^0w!#QGj=d#q-7Q@(mzS{E202VQ{>wiTKASE
zhA1wJs|!v7c3oh+LD-kSrt%W`WsR4`x2l9R)LjtkVO&8`DziFju^D6J-Gv@w-wXkl
zP@+@Q2^L7n2j+cWK9cfE+cfs{sC>l7EX)TAbG{CZ`mPiOvs{R|B&~-fymho`eNjZz
zvyrF#-1wbCu;mI9o^g%FlX5jI@Ddzo*3N&wYPTM~=o`krN7nbqW8-EIBH1_hO7R<;
zvDIT?R%V}AAK3H9tj1TM$ezW*#9C=w`X-e96EDZ9v^Sy+{!Fix*Zyc*ZP*#_b0{K8
zvxO;@br_LIE7K)@pJVEZX<3}ZY+ySt-vKoG(O%Er_Bl`XKIR3o<t4sNEg<KwzwT^&
zLgP(dWRpTU{Ik;yL~O1<+}qdppVlo(_>Mu}PWM9CINhgo5F_xqE?d$<gNi<8d>wtI
zCtur!@uhcd$N3>MImu<g(Z+(oM>@Eb9r>j2W|spi<xzB7f5w-i|I-!b?Xf!5sg8Q)
zdcm>2avjI`r>trl|9E5qUt_kf!C=Gj!t8nWqZlugS3P_q>c5B9n_+z)O!IJACibK3
zHEd#I$hMB_Ji4ui;6Kujjgn)ihH)^!HgL#?X>^G2vF@8)AzbDtu%P2B{_s)(tH?L9
z*VKhn0_;@^mn#eg7;Z9ciiLE>a8y7yq6LK<fqij(^I)OmK&#9YW#u|z>On!wD!gQ3
zpnKNJfM@H&TevOCZF4^RL<BU%krMv^tk~(=p}RM(JwmtD1Y!*wCMe~~#C`6DGc*wC
zfHIbh@kZH>v#EpvHyBWGbWNc|u`oF8mL!g<u*Am}WF#vAc0(HYJSZgxdLk$hOTNK9
z98inIGO+V-_}IGP7O7RSo&H2u)19G|P!Kj~M;sP<xDJHsBL<@L^bZG^nSuRMzmixw
zFn^bRXoH?Al<A1>Md^(AhBL3rI;zq%eR>(z6xBm>I4urPp<=b0=UyEAx{!*WYQ?Ak
z`YMo`w~t+jmQZoB8wJfs5MpsY<f*BxMKeGe6pzkp;lY?OmZ4O&0fd9dD~Qs<$*ICn
zt1h6`&7>;B`66!vnc=u$Hil913|;}q(B&66Iv%{r)uRxJharC7H+G|GQzAX%p*$&p
z?C+gAQ|3@p0(Onav14!cRR1mr+!;W6v4`)sju=laO!b~JzpgKoGTO=VZqGxPHi$|{
zJq^maD`Q1r1>eJxgOe|HpM~YXn3O+`l4B<l>H;NTWjm~M!j4Mv`E{ZEyDzt~#0$nP
zZ@5XqBVQjwO}9zqu5GHoCA$iJ{`2@CL-fxup67al!h=7)XfGNo_&u|jlXZ#>Kvy|F
zDe|E!rex%OJvIqmE&ir!7(WMii1?osyz@#QEzHeLqu{=QE7C-k&h8KUAJ{w`4gHz#
zY&M5aM+DDL29cisc@H0kL%sN+J42KEw>d62`(fWs+$w%@7(3(6{SmncxEm}A#mSK<
zp1D=#lJ~BGHNFlX*Z9=-K&3a`ea=!>M~?Y{zVs}#&JfA`R`0{|Yv)-wbAZWy_g3_Q
z-yU-OLFD3{uFM^K3{wtoSvM6P{4TR;7n}sjYta(rX_BZ}!$S~z8=(Ha^?J9ivC{KY
zfUlwVxb})2n{`cMO)yj-@AV%D7d>lSBU#-6Z4$ZW)a>O}`j6k6s=#iAs(;mM^JvlU
z9I(E9B7Mo|SlYVwZ$N68ZH;t|Yn`|8{+&Q#p%`QMPpu~deKd+Z@IYWiVu524{iAX=
z;22@Fe;hqZi<M013Hxr*zBOc5U$@ea4hipuj6fXF)eelITp3SW+aRx`Q6>k(kew~1
z{*J#_<p9YhGfo;4xiSH5Bva6YOc@fxKjpEnqn2Jw15vB#Y%7SAIz>@k1yhJ|jFamv
zi##d`3X8VDv$Jm6kh}@T-EmVU!O;nqY!%z-Pl{D#6t^=VD>O{=1p*baPZN!gV-&E0
z0+yl%8`@;UxB_t{3^-)w6~ik>JQ+hTg-OlO=DFG&@!Loi6TH48i~+z=GexDt6Kils
z0X)+V4@T(#ur}y{j12@8<B-yEjt#T~%TP5v80@jHf?l9v|2m+~!J-+sbyVCmEIDEY
z1^TUx_K$Y-h^-(Dogl1_fdhcWkH`@%!Gf)5KNggx0QxL;$y-2SvA><#qh$)GRN&h^
zk((xQu=5#1Muy9-G;8?>o%}yMgH8SYdVcvFRCb%#b}5fs>n%KDtr?cTKUch@$B4WF
zT03r_>jsfqbX#S8Shh20K@FflkMW&`T)<q9U{&&`q)@z@#A;uf#u>&5iuU8sd3jR0
z=9<az7uSaqBk%F-<bT0hv#Z`I1DXZ2c<l6UfFjGc%~dd~hZ&kHYy}2y%NI&mjKb29
z=f#`*hfj#S@dLIJzY*DH_Ka+$62)HPVKB2-pc}etMv@{Hnx3)Sx?#u`Nv1*f;VYku
zvml07(QPFx4eyZR;WLJ#Xb}S;4%O*5^_?7oTU281y*TGij0Uy?v;7jDe(eE0I{m?L
z*8>+TR40`?J-KK0FwW@TcbnL|FaS}EqHys$k!WRIR%O#FOA8xh@sBWDzw_d-GP(=H
zh_m7JFFF>jlh)Fjkx&L+?@d|~{!*$|c3Y2J^NaWb%U3<m1u(D+P{>)4q7aj?;%ijN
zlL*J}>>cttPGtMv#e$imqtxo(B)b=m$<qZ4@$ZKB&huc;qt-V+-m}ju7aEub;{POS
z*2OP^!9;O()2=>QXdr0j!GH#Kaamt3=Bol`HZWO1w^jXn{9w2;Z0YYpCIPf+D5*g~
z7bObdY6*%^8Xc~2xF<cfdeS-#--&|@Zkz`sp=Cb^f#IxU52|G-x^mQ@%ZtVrEO~r6
zXcd>H_%Y5A5YTM5QgKcW`J)}|dRiHx`w&g=>5F?HC@7?eK4%*u2^?`L6(ss8={%?9
zaKJF+i>4RK@&JyI831!F6nYJo6iy$(fL`lig4d|?<lk<WIj<B>kkB9j*Ai2M92o@j
z)w5>uxpW2vWR7_h_gRy6&aez(SSkg&0LiM2Ga*^*XM_{O!VZ$rICC|5+(tFWvJcs4
z$=Q85w|^sOlrfJ0jJTtNoSU8Aa^@N#*DgQ;39eDB(MHa%pns{8ndDjsM=_?f99)sR
zc%TOWI<@J8zP7+6=2zOH1(D*i*!`6`@n{6*sxC0sO9e(C7oeuH-hIXn0+*NNUAgL6
z#cZn|*a2^5^dVPp`$HUHI2w&ove7Q`&4IE6!*OAZRBVQ~h8bAt{sc6iL1R5Bx>Q_@
zLu|qkZf&muNr_MK`+1mcUAPujaHwDGufBfB!g5;!E4Ei-Pe$p{Ek++-j}<MK@r%hY
z)t8{#x-ng>zxdd2^++ZJQDx4eS)UqQ4s+M@7zxA|L77j6bCX>_3KvC#TKWTnt(%*0
zS|<4bsaK_?^O5iOVx?RcC;|NhM7|9T((zrh3q4o=n>M5Z{RG$iwm&g5Eq?M?FV;7>
z0$Ab-ET|VNJ;PhDwDTy&mzhDLXORfGIxRR1JPuQQW=!Jyu*vnjbr$AIq87kx0h+b@
zej2TB-w%W0w!i?#ivecg`-5DZ$|Sn*=ja(k=lO5+Cj3Yap?O-#lSz+!Nbc;n{)sjA
z9(jtDol|SS{DMD+$s0)cY+w#n*}S6aSn;f^$2yzSJ(Y>ZUhN7(hd`kY*623v?lHQi
z=!?0%p_vtwH>)o{l4hUgEIJ2ENfGwpx`>V8$kN*q)Pv;(n0y(793Q3?5iC2tq3ncT
z={LN!0xb9EmMTI!Lt9yU2zy%@qxa~rgwXUd;GKr?KGlhU<$z9fp~#vs_~VLcPyYXG
z=$6jaV2B#D3Dt?%)qDXCR*5jmHgTp~gd5<R!ZGmiap2D|`nt9$MFX<N#&Sl;x;HJ>
zQJg0w=c~O?U0BCC`B8cTg=XkzDA*k0q?@Mx0y2Oy7FsC|RmKue%!l?u;wiYNW}fB`
zAL~jny@ssSJiHF8sT)eeKp5V2v{d~X2LhPIhGoP@H@FLsfX$>3V*O_sZtuJdvHC-4
zi|Sb_6mw-UMjq=8#3t3Kq{{(=@Ur!?4Aqj@CF_z3nJnMD;4)(t3#l16<EhNw*$>kv
zesYOu(RyYJM}_@7c^DYR(kCtUrebHDeIQi5)7y$j=(C!{#^MDh>P>#Bp#rRD?p*-i
zR|`R4U!NW%Q6IR%ZIEnyR(P*`W*ro0#mt5%?yGRNFZz9viFiFMxeKzkAi>ddV78bm
zm8*8C8*6AOmjHJ0<+JeJzHf?u@FENa>^z5q`e+fq#CpB>r~*Eh5-V9y!sf(iYRxPs
zQw$xnZ}yg#>>4k;k2A7)Fl{g`yA8&DNIdn2vE1eXV2~_tKIW1ZpZk#LB4z_S9iX2@
zbX)yxL)MsUZj-`)SW{oDts<TYMDu<V=MTT(9NG8At5camykpPYhHnV=*^u4V<itAe
z6L3ABNXdyhMz6$SMDdiJ1L7?`x6#U8?pV(QW($x7PyZt-fcuamhJHR`H1oaLG?(oB
zX;17I-jc`X)DMTGf<MQUSacp%Qy+rhpByq2d_LTX>aFq`^g0K;z}H?jdLsXMa8N}L
zgWc8-ORbhRtMH3nh53S8VQxo!Z6jGrHfXSa9Cr;Wa9U(Akz3H$CfGID?t_B33w08}
zm;`+JMKFjcMOUOwm;wsL%wr(u1q7w5e<5X1wS*Ev)l-AVKt45-Wuh42<YPNNapaCT
zg&V^t86a~!Ty=N)Q$2`xDwRTiLSeT7C~8wGeBD?KooF$6rEPLMw5#ye4c*sRCcv)*
z?`2rtThq+S@MR2Ml#tTKGLB4yg54U2V9RVgEslxq0wsWaPDSComwZs_2_jY8>>}LO
z#VHtxMr1Pcr8pPBo7P+_9CjqN{S^TxBg&{qi9?C6%v5-1K*3orUFf7?(<@zF5L4-q
zfy(*N1{a`sxr>BTk&W_Uvc5|;mtyW`7nZ^{5Uw+!l$e;BtIjb;H^&WsAYHgORK$dO
z9oX#Y9>&!BI@LYVhgRz)vNUA-jM#${)ukvc<zelIFv9eZ#dpSvo*li^X(cd4<_U=P
z1R~pPxQ9Wstd*d834;D3YIFVdS!ew#X&N!x471F0ICWyrMuu44<j?{4kn|+sGi~PU
z*hg5xU;iiyQ+8XY4(&iSb!K{uM4m|OwI8?P;NN<3u-p^KqgQZsn4Ns4pyI#QGtsj>
zSlHi-MPp9Mu*I5gfe}OQz>NG2X6}-oM0;oM$2nk>5B7{fBc;RWwr;&WkbxtvJg|o`
zfI@X2ycox%PMt<)M}wjWMYlDOag@F>PT(mNww8yStn%bCdiHemu^U4_dFh6r|MttU
z83yY5uNYq5i-}WoTa6vUumB_+xY^bOV;0nCW4HBuCVSMwm$pArwY;2k*W%k&Bk#b}
z`&9>`a`6^7v|l=i!Rfsic-lFF)$2>`WRILwPJv)_TVXeS=r>*uB}^dSQ~bGrZ+IFD
zQOe(<thGHd250h97_UF_BPemthC=_mk0uIba<+BJx#_Qm2*tkKI0@Zukm0tHeXtNo
z<x8Oom3Q;)sbM|_cL@l~rojnZU8tA9c1U(1v{UuC=57TViZYhLiV8B7uUH_sNlUyk
zLh*D!g;C<ofJvg$D%i!73!cU1D;{-7hP^OyEQG2>3L}HT2`q+egHbI~Cpaw1Nbzlc
z84TG$v=E=t(Q`M{nzf1iJtat5*#;hPfe7~u!trbh3LA&1QL$*b<$^Dkxg~u?Fm)wM
z5nU`|5Wr!LRnuZ{CqXIuv!?8463hAb6{x^W(^4>rGl_>97sK*+;WZFFK^M}8yRUx3
z!2pQlrCDTkGKQFHFiqchB@_~_lbuAFE}`74`CX;#+^71Ie!S5bg>CuP%aa95Tt!0*
zqQ!EeI_k*6lbTW;HpdxJ6`Gc;ElG{ZSPx+QFy@dY<|rCs{GdrUL_W1VS+_NoBL(TP
z2ggl2e{a}s42NXK_rhbn!#%P!HBi3~N4aBjqp%HQv3JU`T5`Rcrd-d4u^j@HK4F@M
zH$$rYb|BHgUMu>?E>?&U5H!+4d;ll#B1}4T0ku;fnvm?aCI>$f^}XR0*;(FsqB&f`
zUYiG|WbqoTF&_9m?wo>Z`$L(#0`~fp@9W_CA#1+aoInCB09>61Olsf2=m@$%@vb$I
zJc6ySFU?Dm;m88fk#7XSqJP>XHndvej{57cMgqwm#8TMB<U-;)9n9i4AcD8yz<sj|
zsySyXeAGc6{LSx3aPaNO4ExbF=}&i6#Tzj)F?oT(Ny5<a&1tvQmB~tW)TlFH7L`iR
z`8fVJei+H^UF)^8@NkEFwTZG$+Mhola=9yW(EtYUo$tCI@ALeIG$A586<|QY&G_?|
z4nP(>o?mwarY&JSU+_J9AQ5?IAfu*aU8Ieuaig_pMe!5LWBKN{*pC!rE8dZQE5@;C
zd9yB5kE2|82rck*K$r?m!Qy}fxpltk?bs&=nJ|56P<C;~JL*TzCHrW7zD!_zc4920
zb9*urXNjPYbil^Vvb;0o%7+4_2DbrccyP1@mdRMW>q*r1WW-6~9ppvD=K$kz6w|rb
zj@s70w~oqUv=B13EQJvp2h_=&C@e2R|8YEr5oW=i9z3iIm5Fweb=eT#-Jy{qszs_R
zfV-u;02KgeSx0eMl*+mCU8EvGEEM1f#wC;<zyL6o4nEk~Q8tt)dxHy!#KfevtfAvJ
zq&0zX>tR(J5v?Fi7Mf+Uq*gywGsm4QW4;!w@ZnfGJ00qT&K=|JfJvAAThbPn0#j8;
zPaH%O8d(?M!(yH6NmWav5rdM#J6&r-RHSSHNcO0BDfglYaHfl|BtP94H^^m+INN~L
zNDCev6NHI4S>nI#vH0E-9l3x3ei9}$i(wg+{aK7P8sWo6K^m}0JQtuW<!gzMw1$as
zRu{&k48Em6z30KJxoFDsvSe|xOKP`{1K-E;eKzHB>9lYbZS8^U{<lZ^LQ>@=t1o0?
zrw%WZ{*~;};(t|#j~vN-N~kU9+X<@96||&9&a0NNCMDDc`qhWC8puv{k1P5-l!B~N
zmH!rk%P$Wv0V&6VDPlMo#Z}6dZW?`rK&6Mgj99jovcn}(4A34f#zLTrRMi)~%^^)T
z)vS_)ya1Lr9(-Z&R9u}7R6zy`iMW}ueDS&%k&be;E>;Z2BN*{#1q$$E%9<L(8kUrM
zT^bHuf2+_FNeumty2-x!z$We(FKIE}h;K(SOYmEi^<V-;Ko{yHpkjFvFS-nwhU&ta
zITf}M+1ovtL}=A)B8BH+l22qtMEB|tPG?Ggtu?Dt)rZW_W1}<kO}N*SN_|MzeUbz+
zrHqdo43md?QfL#e6}_=w<j60nBtIP(Sr}dbmBG(X{IMA8PoVNN9!#;t1n7Ji9+?8+
zZsaGZDj)u*%J8E@qY}?ye)eT7!|UMJ`Ms^P+u~Cf>y&gF>eTSBZ9%u?=v8+Z)Ka-H
zF>y;cntZo6@E$o66FFZ=l~_2_3*PoH%>E!Y`A-cy)mkl`R(IM9m91pYWMhNTgr7Kl
z0NdsQvBc)VUGIy;-iv&)1*5-5K9&~q&?C;a1iL@SjT1RtU{gcn$Sj0Cd6tp4eZaP%
zRK&Qe;`{qPKN?2=WAnI-+~g|d#f{L?{2vC!oPeai3j?OG?LidkP=2a;hoRVAvftk>
z`k($SBE1WtRCFHP1*OGUnc=O)z|z3uuDU=v$R(F!;mqA&`fHdr>Ov}k1do9-hUufV
zXazwhxuDb;jv$Tp4@$+Rdl-YizW`%~_lV_}8s&TGAv(jHQSWJ95bG7<1z*LIsHEQy
zHsq!Wf`m$Y|AsPW@hWz+iEEJ<@G67(d#CCey0aY`D9godQsU<QTu_(=M||&f6(~G#
z6KHS_W#Aa7_Cyhm$z0r4fG%dJQiO%5?SL^^u5-hj^{>jzIEl+Gdu)eQC(syZBbviM
z^)@=awEoYAgm>Wv+M&S57~zDAupp141LFIZKAS3_i0`c%`UxkQk|Ay|NI=^TC{*WJ
z%oaIf^^C2?vh8HXDsg8$)f+-y*EsiIbH1bs1vGw99#`lOb#he1Ol3noT)_rFFkvx$
zG~P=Fb3Ujo#b}(-H4@bOP*|s+0ju&soa~+<3MO^%RisLlg>~YiCd%VBq3IO`YeWb0
zBvI3<!lm3q90pl?r^XOGszPtY&Z~&EP(+|@w3w<44LGWA0%V5_7*e4dys)yW)1jKP
zakvJ0q7cqB`j2f1<pZFKuSRd<?;zr5E#+z;)jrt`RVM{_f07ypXzwz|*kO2cDSv{q
zty?G6ze&;=wp#FNjt`8feC^j{_((Wk(eE%-%s!!GMi}|^!D-ol)pY9X@H@>crj!r#
zn`q><qkhtcKy>2PK`*JGce>-u8HxUaYLv>056Z;EjpEy-EtrNqBS>dk*?46l1{dpM
zQCyaoieOjWUtb8j{+4fNfyjlCTdgM3g-EVF4aNHJxV$m(k1t7^dF-}&7hRLfq$3Du
zN>14S1#O!L-zUCl=Wh>J`c3?1bW^<vF~>h(Sa2_v&i4HImy0ovLEiuQXVYTXbz6~0
zS|QWEEE8a|W!>)U6TP9b+d58cYnZV2o1k#ro4~y<TntX1a@ML>ZgU?7kkVe{6@E&z
z3(FE1c=uaTo=wlY^}fsKrY<!VBM-_igkGRKJkLJvGKT-_V>V6(#K;X$+i?ir0lKXK
zb@#?w43hq@;uw;oA72-xqH|!!L&zTb5(Bas<c=%_dL6t9=S{ovzl!KSApy>8MeS@x
zG@7a4HYc~ZL3)Nhi%W4iSWRCR#l&mVWJ|~kd0;>frnrwnq3pIM)&NxplXdQ{(@CHp
zQz*kQ#*o>->SCetQTk>C$_g^F@S^=B3F^_|tof6wvth8;)xlNHRt&8?LL?g(tJqba
zfm{t@mb+?7xTow%{wKVpP?D*tvvZ#{$+*gO^4uRl5{uAlf{#JUs6oMKz^M$)Lg-wF
z==h}fI_a<Ejzy?xw>22cs8`a|FiMxfrGjp&!Zl*y<5dOj*6RW^lR+7V>Y&(1Lud(#
zv#vnk>?~tobvedZ)rn?u9#|0AEEnX_Dsqndsy(LcsanI9bR#fxrmgNqe5d-Nwdl6)
zkQrNUqYQ?SJb6DhpW|47SLutz>euId4Drj+v=QpN-TpWiFNJvZGT=H`UFAZIEL>a5
zUoAD@Cs)awJlO9=#||LI-@0<a)S_^<)ol`~VLI1AGp)=_E~48y))#)so6Hr3g{_?a
z9*@(WgWDhZW!UYvU_AK!-(Lu$kvK>&+lrH#FB+mji<WxR?uUUV#n8cI<Ku&#_WrDq
z@MqevSc^#Ew?nm8t_l37231PWPr2fTS%NjLn{9pMOk?2gcwo_1Ui2_ziy6^@*ed#>
ztziNYzV-z_sJ!tu@$Vh*^>5xBk&Av0`$|82g;>tEn!&SDVOP7YPNPozmh2f}<heCg
zJ$$bW-PU|SvMw_`aNnzB@I&YYhdY@!n4{7FbXx=SPrpOXU7!REzdz%7{h~9r9f??b
zVyzK5t4D^<=r^+TW=68!^RSy_Gn|-h4KM8-CpO)`oVt*0s*dzIVZ;7Uj3N@Y&9wur
z?$q7Bc+)UXi_h>jz^kBMe2KCPsRS%?{K3pf4U4ljphOzT7a!r+n|5|WDwSB86}Twf
z4p!G0qBy#env}Hlo$nTlV(JDdz(apMOk&c(mCN<Wj&)lxJYVZiVoIRT@ZJgn96QV*
zf$TPeC(XtU4n83xS3=u<RKndsu)3TJv8DM2NxI!GrC;?PR5@l8v-l)r6XN`BVND{P
za;T~$Sx?50*Q@hux&Lzl6xMzGz;b8;Y{0?mi-GoFgX&8m6?%PDr?k!*s8<OC>NOUl
zY1LZ`Ywk#+n{@AFnwcD7U^03T)Th^+O9x=J`X9Nwg%X*rB36Ia>1H=Z1@1(Z>BfGz
zXaNIG<BW+>0Xw!j3l~C~3Ko!iML`^sLoG-aKZ_JN@Ua1T&}bH?R>w|*;=DXYr+hes
z;Gj4IA^nC%vUe_jn8qNAWzo716`9>^D=GoG#M%$!E{HhcKm-n_bP%81uu0LphoNtt
z-HIWj@}w?fS8*8_wSzg|h}<LhYLA7(LAoUF#NxC>xk~`DD5vm4@!zPCxPaM{d$;0v
z=lxDW`G0w05(BxrwnW8i&&HQ?5{v-?dL9ac(8|>0(st}de2-<hTE-&bG!a7*s#@t_
z1haO#R9<%|lm$%5;|=nG#k&2>X4!M+7sM;w=2=ET-s}&*hryAXk=L%ma)2(R1#hG(
zTE5bk@$0OWVjE(4+ZTMZ_amcN>34zZNE}XiSVx-ROI43vV(@Vkw2z;=5C@!rlRGVx
zDs$p?81g4(<T>=Hu0c6I{qhxUTGE^hGn|T$_!$gMeGFIlc2{{T$q?Yj&tnzFHRvsO
zA(enx4EA{yQ7^QbFOxGdCcA$<Dz;bBQU*rnmOjZyp|=FxE?ovEx~<W^w1BU)IxTd<
zO8=1OnaTk5l>=v1Rey_rtp70*U)5mXA;vSI-fPlybC`8Pu*IT!#Q~OKAjTO$>pu-)
zUcxQt=;PFj5HX`@0$7-3LqXU~WyB>Sb7%m~A#X$|Er4kW%Q`F|20<H=u?~mZGGP_d
znNKT*iWt*&|9-iS&|rSEVu_%T|6lgrKhBQoI`BMIullLfYM>;wP$To>cB_F#VEci=
zmNx`$H*MS|Ox$28R#;EwL5M%Z_GC4Q?cl_*Pq!M;CM0P*ct)PhOdf>ED3~zHB>61k
zc*X^0GK!bY;*9OEyUBh!j^hyGk3U+16NbUC-*c;8_iIW0>UsVfy*}OV*8OqrxmD-f
zbMDW&m7}y0dwlf40@o9@z{wD5PpuhHlBZ-gpq`9$a`-((gb%B&sYb2{m##`a%A0iK
z$%a^YYX$3BYj3AE`Bp=wdsdJbqW~j1jeC|H@-%rSA>(YMIBmmOM6C*sVo_K(ipq%x
z?G`dtfYPjT+(-Dl=q{+!<@K>BWGta&7lWQYkyN0b@vbS4PT?G0<@~x24KF*=wqtj*
z<Q>S!B3ZZ@<rG=-ze90WK+P9KP)3>LL$M2L2~incd4Yx_$JiQTY;z=I(})<|{su)r
zlW#K~OshB_#k^>-s$T2y#uYERl*x)jUa3nBX3K?1CLfDu(xcnbM1LS`n9w#AlVB%2
zekhggQ9LUw(dz!OYGp;UnS_XC$8*297-w6jTqiY2$7J{@rlS#aAAJtSfIs*_KG_Gq
z2EKHWo4(*<ho)J^=?*TD8Kl6XI}i_hIreH;mUGdC>PEhkMaPeG7VX2=1<P)VRcNU*
zkJ$n>&%&Fi2j|h1-u{D=a`X;?XazXZXYwWQ|8|R{H+{U_ZiHd$xr=sK(-yXuj@`;$
ztPP0Xa*?FR9){VCO)|_D-=eYX#u!K9&2N)da}k>tElNCcFzioLhONmXZ&$f`Ac_Wl
z{`}&M5O1WuWJ~Sl8Twc%-aKY18{g(5DZiCO=$TNjEV>IgDBS!uKiZ724EBYGk>yYo
z)bdPU?r2|cNTpVN|6R&BQ<5?{vWZT{7;HU)kn)q3Lr?pd!=`UHELro0aCWixg|F!v
z=5nOz^EZp;F~Mt1aBXO|--^*|+fiKoZgyhurOrWrMGr0dusAtzXJ}U$ER)@JtkJeE
zCc?VFD&rj`^t*Q^Fkqt8sS0jHNU{}h22e4FZ=U=ihThWr6>O|$bmJB*B`6dPcHNR;
zySJsC5UtcAbdJ6b-+{~^R1FyimT06(wq(+3l2I>9z-RHOv?cUAG|M(>mIHv96DZGU
z>47V=Em3h-%K|g{4JPYFcgd*bbFDZm)78}x3QYHS0w5D(ebFz2{i?j+q4xEK++w?f
zja<Uqb6A#38geXzATwKJ3<cIFvC$g<i&Jr#phJ0+mGIkL6;Hryf)k6694#4bW1%2i
zff>bN+DImIQ%lD$z&yR!C^v7N$*6{S^R}UQJEt8w{dG*In$(imq_&MI5H=~RVMfy4
zx9Tjo+nfzR0QNddCf-)VHA`F-PePL_CbSsU+w8$-))6^*+lsOc-E~1FLwk8jx0-C;
z2OXvwfTBxEt{#AD1lE9M)xwg8j(|l1&KxKT^fy38uZy=0>OT<w>_70ca$wAKuREx*
z@NRG(*^KFZ){A`CSnc+N*?_;wW_g`ro9K0+zK~Etd|*o=1CI?PZ#?*BFY=~28Twt4
zmL|l-AGPsl1t{q>>bfJ}LRaZ(LbG9(uqnq?^0zQY&8}5dA7o2vUxUB-i;^|J!l@~L
z!<)b9Gd(aP^R2{IH}lu*bb%#~{&_C5rq#XkEa%g&V9QNLQ(p}0=_nRpV!!&aQN|=+
zXO-45A(Xr=5%;gDLO(t@Ju~vNxBH;lhPxhQOqMJjkFRVlGi;sOk?2(~`haVv^&jWE
z0C{|$xEp(UFKoRc&X9Ox%U@i`p2NSA?7_d@q)Bpj97NFd`J7DD9{CRK>nlhlx{r<E
zC&ap?OY<1<q4&%1=>2mtdVA``OtF;_RMF&SCt`)!g1RYZ<4VcDa>KxcK6q_?%+R`m
zb6)PhR^mH;qSlhjMx-7LJ=Mu_U2(tJkSLKGItNf)>7BWWjz@dGE(4e_&LfM4Hp>sE
z)kYZHq%}wn=odznt|<cjtPvv8V^F`uro-=~vx9qwV^U57D{2|}@mi9+be130yJ+02
zz*C3(BlOqz%_ovQQjDkCncQX>)T1=*i_R>=283=)ZU;jq<715QSGc||YtWhjMC%RV
zEE!IlTno*qkDGQXJ0mPDz-gG=mbNc226L{ySp+KGDOaM*b)q(kK=r+MW;&DoO?x;S
zGH}vw{<Nh2MvJHh8{_)K75sFM6dBCEVtZpQjwz^9pyYlT4;E%w<{9%Ik%cm{%f*wH
z+8okU%VB%Vs$;PQ)V*DMur>wyneN6WfQdwEsLVLltQuAZEg2^X8@e|V3^zROsZ9^3
z3f~h;Sqp~jED8bB5K4QZ?`Vj$gs#vGsXiDOc}iv?3rC?=ny+cKq&V5qf_)APym>r<
zNRk7#NBGJfxX}WqwF4&;okNPhO4I0V5%xzdGm*GjOg&h{TJS~CM6#&#U$cksX-{*9
zMO`5ivs2_RY80bjBB)bl{do+2eGlF^kl5P|$}pj}ug7<}V}zGpm2Mv9ExSmLny#WO
z>@1a^l~|75tG-xB5Ahuie0L$Jd*{4-9q)+`dC?!)EcbO_t>;boxVN4=!QxH+U(<)>
z(Yer;9{f+bGHkVlV3TcMgNFl;IDThsj<er9Cz13UNsQK2LTJ}!&I2=MGk@c2G4hn;
z4=-f4>SxiHBXyaqH*Efp+G4~k*_nr~s#o(&e?0N658|mYKXv4z(Nx-lG~)DyH1fZ=
zTay2BfzxeYH9}r~feoa`FG20=RE;>y5?ez5g0cN!7~WWtIi17|4z)`5SMVg~<X->&
z{R6RFe37^#pI~yBO~QY>iN*1cWKlD(X;R}OWFvRVgf~)FQ-Wrh*}Ri4#L68k#~quA
zB93HY&}k=lSBsUygCAmx_p6*v`<r`c#PbCYxg%#$X>Q(@&{d<g{>3*EwE;5Xc<Icz
z`lmku>sxWd_rw%COJD|ZwQfz5=ASGQO5|lElbiHDQr{}}eFS<<E5Zs=B?`oEGOati
zKjF|)LN5%U)muubhx9JavsO8NN=2Ti&&8^!Dp2R=F5`<zd$0w^M=fdt%#4YeV4X3;
z7yS_Pt_R){Y!ZU`qO&BO2^1_&&Q;?0QAtv{A0_e*x&hP_HUPaUCM+bgs$gL9cE0_(
zPKa9HX^bO8liavzcS$^%EHlh<wKazgC^(>wYmMcYBRaOKR_k*|NqUIN0BZv}J39lQ
zE{e!dSyBw<i%aPa+ST)s*r<ue@dE;8oL5R?rSbI=H6U{gyB`QJ)(-NmhhQ(aUt~M8
zU5=z<IyXGy9pU}%%E#49ZVp264pck-eWWc`!YzKRyRG4_BhHRx(I-t)>*5%;o=Y6V
zO!h?(r4yv~0`}eDrXgkvEGd*=WtECM!rPG>U>u0#Jf;v}?IaWR06nMffJy?&&v99i
zUrq!n7jr4PzQI#EK^HB_Jl<PuDM&9PA+e)oSn8<|id7Tej1y(+KII1*s!bw|NGQ9w
z0YZHYNp26{c%wM|fU-`ysYk7OKT>J_P&zE1QIVtPT7%{rvPd@<u0AWHPS5i#rU*)M
ze=`~l9-v<|@K_X2@J^QKo;j9m$5Cz!v;Ig;=1nY>;1?D8CR*C|6Vt`?5}j>jwN(-&
z@uo@|eSqNYNN8#9iym~pzJ*;z(+m|#NpyXBK4w3jKRPIS-w(#VF&}WVH?UTA;Gd*X
ze(-GZ_HmTi!`>zlc~RhUs?KAhNx9m3E)%=Rp~(`O-ohbY2j1HZlSF|`H|M}UYENws
zAA`n5jJzC$s!(Iv^En%~#)GNM-&UBMZdCdq?O{*N{}%lHYjh~FJ)rzo!u{8^q_rP&
z%_iaWIc6XL-9vMkOrU^FM94#f#n*<sB^lL`uWO-a?HD=sdQJ3e5E*_{qQahn+YN>q
zRFCftq>hfZ9JnQPqSP{s4@Kf^*!o|uH&yO$a6JBq%?6tZd*!n@H}zx+*$@1`fIMq9
za2GTC|2ZdQn|&eGToi93*4eWHf7KEUM&yHqr)`(12iGH)7YJvUuQbpl&gm~%Smv4a
zSmDdq*YvJctclI|ZP@zqrK^$s>RV-|!UBzVh<n)M>j50bTMh4KcZoF1%1}>Gy=*R$
zxd!LO$SrL;mh70Ery{HYpCJfaqIFaEOs+{eeSj4SBQ=wo3%KBx&LoGxZD?vIM+&nW
zXSsDoMmtm1@f%ysuqsB;SV=$HfW3=&@!P&(=R%x0hT_9PKX`0T$iOq~^mfGop_CL6
zT_Kfvjv<zX2xBju5Z5WZ!5wUXaRC0nRu!js;#CDEbb9dgUD@!<3avvZhQl<5f%7<l
zT&55N=;0t@A%L6Mx>;;7IBJ=!chf?_EtBWc6+*EQS!ZSqn<B@=S&rb?E>n97Z!sH?
z3Ef#XV@u-8>Q8&w9W*I8i7enGZCu@j48z_ipsWMPZ~|d_!$1zQ6m3m(h!+)o{rp(2
zYBF<(By|XcJMlVD2v-2bHjUbOP(QBkfEE=6FvpoEawhEHwP0UE%btFKCd)LZS;<?&
z-U}NehK*a4-YDUm-7*$`1x#<5$Mla?^}_D5NmY)q?NkR4U_d>Wq!XrE7IOuaY8jMj
zpjaPqmsaeo>{uz5ffP56tQi(_KS9*h)XsbiXOC#7*jWcQw?KCYHn2cMc@T{tngUX9
z6o{=8+aOj~D+)df5ZTd?T1==D7TX;t7VzerT&%@;bJ_{!?{jcGzp=wWO%a2yi^Czl
zw!vjBw8Od*joPdPS{55KN!bBb9ljs1Vpo9Izyh?3T}jyR6vK^2V1%2-vECBeRw-3Z
zA;9W75nnW|g}y?d$Qq;t5!;uVO_rjqlj_K}s@e#h7ywk0*UDhX;!X>pSRabTxPa2G
z7bOL|pVbO#{yqg`t@V})h8XK%RhwBB>H?-MYW-4mHdF~<&9jD=0vx^v%h-@)<C;)h
z87eNegQ__8QhO;@q3DJX>78NoOouHOX9N#TFpM_O28fzajJ*ySp{=Jf|8z{U47nvZ
zbqrYALb1-%4(1)0mVnyHU=xd-;AAnDsZTRge6+WTex&(t*dIwBAkL|RcB`$DpewI-
zV;ex#ck=YbQ;bOHH0?(ic&lJhe&$m!^c<!MllX!7zU@c{$WXaYZ1&Q6H!q4$Z_~A8
z+&L$6JeASJpHGeW3ugX;tyr7m)KH5}z_~36-|JP9%$2pt$sd7Rw7u;Lc53E+idkaV
zsmlyPhJH>nx5vf^)sVS=Un^c=N~dC%zj!EQIsaHT+dMS7aP+r+%_W;>WzJi)3EWtn
zFTI=3hT&O>(M{*8eCQJrx#c-d`|1JQ(b{<Y=Yu|a?gl%ZVl0qCWs~OrO70q_=E!S3
zkm&=InK_B_r{5{fc)RE^Wj}WHLwjw!F42S0j@S?Xwr88+WXN-F0~^^AdEh4(*rCd9
zhhwvtcm9Kk4{cuKu_y{LGvD$E`IpmZ(+;PNKh;2>%845PpW_whcZ%NW7^)s%$0A_$
z=Gg5t(a{bk3*WW!HlT^&lyATXg&&GZ)?Rq><bR;E<hP0spC!5@u=X0ZqueDrx+gwL
zPso4RJsVHVHBX}U_2T$T@t-kih?lSK%#-MGdO9at=#w&9FwrOEuIRTni`#4Wx?ckg
zOUbEGc8vUBKH@CA0f7SvGDW<SPc<d!i6={7CGpibc>JAY$K%xc#l+1M)**b*T?_39
z?})edRFS80C3_Xb#Y;U2ugD$)SJzN)5d#ekrlE>bf26BD=4##V>7jj)BI0XF9$CO<
zW0_I3c_#02BuYK8s?rJduwF`8g>=0%gA`iYiL{>Ik>DGYWMq+`tSD=f(&=@LF$-y*
zG28$+?BIeAyjX<UTFDc~q3s9^#AvX|3}IGt-ZC{%J|=@l@nVA|DMe>VCqw!q*gz6p
z8HD3<UulCg#L0ig9cE2toPipmG_afJ*75YXb;fYdTnMZ*Q|Wv{Pn3Cy23wn|p4S^f
zx}-RCiDFd7#aPo>uEQfi+@3TU57d$K=^-JXx1=piUMYxI2EM1qCRV*AjgM0dR~Ge(
znqiT^UTJYZ$M^;LhPZxp5*{3J8Y8U2!{?#I;;P}V2gILv_q@0BdgA7$SWV4;9;Uvu
z1Acoa@(*jHr;yP$%QJZtu^!l&>O<EhR|@ZA#e=6{pC%&P9Lrrb7faM)kIu?#tlTqO
zn_B0@v+|vG5vR%BKT(MtNH;%uanV+}3{jjajZ@j-PQ2r2_PGn07w{7Me3LlDy6~1%
z?sz}+wr>{w)CV%>Eh9=9>Wo^zn?p>L{SFxhJ|lAWqaw|Jv{ibjO)AX+Ztk~#liK4M
z9lgB8R5s*nangbO7k1dCKN@U=71Pg<jqtGqfA9vFy<L{F<;}e4TFsBF@hIDRxAM~R
zFvr3)-%oZ3)H5&Hi<!(la1TA!4||h!VG4%c%V@{~&YXw|EmP@9hw1)fzA?zzsPPd?
zsQ~@ydt_dDJ8o*|!%i+{t08rxPA!q_feCtHL!<XR^9#;m`yO<c4(k(aR?vtQxxJeU
z_E)f_se7iq{OUcaYn{zv`1{O&E+v|!6Y>?5aUc6V{k{(N>hBdR>nD-j=bxT<=~5^8
zqfATpqGg_u>6W_P;+)*(sT7FS9A3U;$U3}PCT7vt4KNNE`?sN@Bi8BQU|@@@1f3<v
zJUw3L?lKagOPW4l`8;;<WFqv6PK8M7&0WDJ>#2#S!~`5~hf>6!76!-(XB&j6{(z}=
z-(&om?v$K;8DV`TwI_Fc=FbH#TWEdAbQom&WJ5g9JFKyaUyxEY5wmq^J-M}Gmp+Cd
z(6dhWDx4+W6S5naTa8`MX9FsO(wuLjqO88WRddrJiN-Y`^|do0lADA8<A#?=<DSO{
z=hBHzZf7G}Ojc9YhRrdpSjDg`o;xA}sJSENtcW(Qt8*ehOq}yL6@X@11)u;rWmXyJ
z!nZ-W@n}dR!sB*3{S5^N9Beh;jr>M*rjjLl3}bIXHL$u6PjUQ5TSJG2(Owcb(?`(a
zQVxbM#_|=gj4BxYD+<}9P^*G)v*|o&j^C=H7Wqc3c4hS8Ho!QL{8{2_vk6=4cN3cB
z-0q(E^4w;oE(XVu;I<i|fwWx9`<=>Mnx)Ub*@C;-LvvP;#afCc(f|X`UP`_n!2b$|
z4D<kA{_dVQW!TCzGK8<Ssr>+X;-Kp9u|Q9hifm`Dt0R9e(|TE5<gtgw<lr|q$FA~W
zVO;B(%`*P$Hca#q=g;jnQRP4N<IXL6mihkvS5W&Yne?BB`TPf=E7xI<6Sre>|4W(N
z|JO_Qwq6g~8i{ZIHx~6i`zek9nepN;WKsfpmUVoL^K75I&QYvwEZ=}<K29~~*p=*(
zw`8*S#l>oEZNaqcWfoQE4zp<E_<rQkL&n<prfX84sh6b&T`E44A?{V!Zk!+bAcb%h
zXO6{KJ!rmA+va~{Ka?IWgky>8LQ7O;KbOvFRF`AVTu=7dD~*&lF*0mbon_<j6@RrZ
zfxb#;GH-X!bHcc_$#cID^)eX&BCn;!vu9yz?{X3yFwV-*BeAl>KYB8L;zy*89_!R6
zEFRF0II(_CBZP2V@U-GQ)dv=mKYvuGOxBg4zrhSL+s@->-|gw7*?N4-?0p!vZfP9K
zWcE<Fmr6=!K0<OC&p1zwZ`!jubE-gL=>!^?L`aI+{zS?T1pa4E0{P7%cUW)nz6dl;
zJ5PnQNq0K3C7E6T8h!y(HQQj2P8U~Pjp-e@m0-Vnloku7)D$xq)nm=3@O1~&!_}Pe
zFp?*2iL;)&CUNX<h>^3|SEn(PPH>;uL?A29QZsKSoUPX7NoWk+oDu5|VV|qFHo`j3
z=~f#jwReC^&G};VBuCmZ?@sLuPtB3R7|#eZ;)h&>CTJCZ3y!2(T$|v#*c5(1F0sR6
zM(^XGg4igo5GqwQ#xxfYKB1v?9p$Y>*)|~vWfi-`In8A-SaD65!%E(TblU|u?tw;t
z%@|E--`8of_g9qh)WP|<$7VIC0~5h;3F-0A@DrFtk~5~3_WIpXBBmyAtVK0&PF(1t
zY6w~`v(j^PW~cB|H9~wBCz1I~eDn~sY|2on3}|iuUtaA-;=}Dg-(F2Xf5w0#uk#rw
zIzfC#%r~pJp@tBr4@4)f!1Iy8IC_4&!>28i)xOO#>pY&>VjyEh7-+U4VM2xaK6~l7
zE`M&u*M9thI0{%@9JLxWdzL0AK1BEGBk4`F=~iF?%^|t1bzw3qU-j*%{=LE$hOMHv
zUlhkfFQt(?F=t9t4NYqlfBx(#nK;3C^_A_GLl;_O{@^QH`EFl2DAzvk7}6p@V?89@
z(({{QA;ty$wnB1F)zimYM9oGdR72c4GP)o&b~HcnS_G}L!`zfroK|CNA|GRgFa5u&
z$@Bxp{XZ{bxsQk3x2}`f?Te-oJpi-rhYssGyy)y=*Em667Pt=SUioUA>A`E{hM@+-
zng4|F`47tJ4aM<0`Xq8$yqlfAt+81C8MBN_UmOf*hS3FD>Bs{z@M%_C-Oz+YcYbqw
znAoWA$MUn<Iv1TU`k~id7YhB7q*JXoNFtx7#vj~-WlU?n^3e~n2JY@>f8p=`qU>SV
zIu<^1L}%%VXtEytpiD(0H;T_^n&SU5@cm?pOFL;J-<P=Lm3lrgLxbM>obRPr&HRIr
zk2l#=^o(qt`>9w1X=}b0B0ng%i#x&m)&{@<Z<<EWl7qSvQD4oIqFr1VFVxzlj$CCn
zqO>58(zepA4kkFnxFUYV_2Xtd=V=9)TMqZIl5~1cDAp%RYP(G}Kj1vOhs`LcK(n~L
zkkG$QU<YO}H*Tagm(KRa3n$LL{FqZCl6u%{NWP)iiOk_~cGiDln-P^zfK_fcWLvs`
z*&ZK~0VNF~dF^G3vX5%sUfCQZS9TcMMa44mHRtVuY>(J=1K@zx;lAmt@~eAzQw4fD
zoJLsK6LHiJZ5oLh0Y24XUKFZ?(k@$hej&usR%WhD?Q%&<WG+o=ldpMv#eC$U$c9%N
zu!aK|!7$8U6S;n1)v&I?*=!RKZ79Xwm_kY2lkM1WEkr2^_+jyVI|5Hv_pYqLJt+Wv
z&mw}{T4#X8B$F@FM^8fQ_uyb)fS0GwW?$yDNZ?4|b$7PtH0k!G?M^`VCg5_2b**!p
z#CJ!nx~pebJDKW4Ed81%X_V|3osjEL=C5roa-IfpB}xlp62kY<CTsje%?!bWUdIH;
zOYK>Y75x77z^Pz+^QDV;`+~(5_lylkD?mvfdxq~W7^=0Ho?p!Gtxe{3AtJl~r|9U=
z#}{1l_hI|s!J-faBcRS2ZbP@q{1cl*KJ#HG?t!f%dn~yd&<&29A%tT0XA}POTa1!S
zf08m^-fD|E#r;@hzk|u;uH(Ff9&a6J*dl6&B|SZFl<4eFM^$sAVrJLzGuU#s7gkY3
z8w^3N_@HcdpWiNrMj70;h0nROwW&7ymuG%|3&&=%@i6=MC_BT~uAoc|g2tl6`Dr%X
zOrqxNp9&fNZhN%3@%Qw)|A@nx7T(^KNM9w+KZglh8s(X7{;&#W4dG3qOf;T^n(`@L
z1GCVro9N%}bI@J0ZTIUzVFOkiwI*7F`9F{DQbnt)pdc-NU<?c2nxgZ3eH4tu(FWtP
zA5b4%lEsqK;%-2}0oX%FWbYy&)4pCHM|V~w6msxNRk-p&+=MY{V~WrN98y|<=VIwI
z%qtd#l*`teY_V-vyl1+Ka5wO#@+d1+#*IqDncjw&vRM3MhC;#y7zaj%v|yP;4rWOe
zgcgnc^RiZ3n=;<Gg}jRN0+GP=hD<-aN|1r9feWrVu`I;RnvW8-P!C|lnNM<ts^(C;
zSpN4JYKpS1%D71DXV-?U2DtoJL8t<SVj6dS8@~Zt4bq4e)X;gM2c<NfO*OhE(UT7S
zARb7}scKn`-f=@rQ<bY~LNkgPZkvL8qKr2wiE8rOfHntw+avPSs&_pfVk^47CnIQx
zm@TFP$AY*fi1K{I9G*MldxwT2lO+$KK+cl7gBHnK?L-3RF9@~Ax)}W;ZNpu|f&4;N
zr`eN9Cn(ywCgpSiKFb#${3VvvZYK5a4vr2Fn8tV~(<JQQon#Z6Nd13NA-<$>MU&6I
z4KMAqHo1g-e11+YPor3Qg|QNf0acif@?W}K(&6_NhbQJ2aO;g4CA}FMcURKs3j{N!
z`2+7QD!e;UtDeO3sLA*fjBjt}O}X?{<XAH5>^)9K&A(~U$&sHF`R0SW*-d`YRvCHR
zX@0CeD$V1&Gci+b#p;9iCi39#@O71Z63JA6=Trk{I1wlEAHT5{J^909;pRW|HkHN^
zhDvki%q8i^%hsWS+8Lb;GtDqA+pu+N2h4uC;9S>-*7z>TJ|EwqV8y1ZjvwG}yNEeJ
zJnDBk8D3^b%fmI%-`wMq_9o$`GsJr*qG>BO_cbp!4lhdM;h^7^wmvA9wz15>boOGA
zZ=>f;A9+I`YsB)Ef9qtP(elQy6^5vB#lVKGu5oOFVXF%f6;8&m)xZU}bh5{G+839B
zzr4psEVGOMNP3GL#dzv9CjJ7LV;XD~-tW}w@+`Wh*Xe3{iFWG6NH?g5i)SZt@Lwm&
z;z7uD1w+|<C-u`t%NxViRmRz<o^fkpljuFdsdAXLzU*9)U6~&?&{46zsyDBhUIX-W
zF?GR9v4l}@<pYG(;0;}koZ}CO%%LGjTE#0~iA9(l*Z||eS<3W`F^mllaTsiN<qL>K
z<9IUGbkVd@OCYz`RLPru#cUF8k3`Chjx>G_IVc{xR)T`zr|gjF<;{|gIVw?$n23E6
zL6m0y^NnFETqv2Gc;m5GC1Q?W6(BU@A>e|$>L^}#oYMJa3O=^r$uMME&DSF{>W@j@
zpwWw11EwZJ5}yd(+H$yDjjK%aGjQD)wg!&iARz<i@s0&=4~}ID3Ub;x1e3T9NRn<v
z>La4=6p9g2RAPPfqb%^uF=^q;`#1%)GlEL6mz=pL^2Vb$1PUkG_~?SM;v{%B7C-j`
z9_t39xKzWz%aE(>1+z~=mXM2^fPxdghA#5rfRl-LW;PWOP#kdv8tWIhm>3UU${z9S
zHv55$dB{@z4P|}ULy{kkB<FpfVTtMJ$z}3IT+SZxat=f{hOJ@0eNe5R9MJf|31QdX
z4ZX3~F>H<IY*X&fM9+KJYVe_Dg~BLg2Zv?oqjPe{FJfmOws8}w3x+buFFAC<h&=ni
zRHSqDZTjGcRa)QO+S9oP+PwbaL=Fv#KmLD?j^?3i$kf6Ym*nElZ%?yuKd%NWVrBI$
zc%Iz2F!SJMR$KAdCn1-(RszFT`E*_m6CLOX&c}$^D9l;*8$ZHPOV348+kt4UkmeI(
z)EhIt_wE(<*=M57`7w56+;)JL_2I%MTfVN4eHBDbg36LTPMiNI5>wYduwrx3{9_zC
zkX+Z5Kwl-!zr~f$`xcZb>gCzr#QxJ|Fgu2cnIdNUsAO31Yz=af@V7^;-(<Q9JZ3UL
z#F30e<LpEdd3>H1I_}Lx|D$7U8&WHrTi61TjY{mVj_#We#~8F^d6Nw2&)p-@@7_o5
zHEX*S)Xwl^I9i%64GLB9xF#pH45%MacAGQ~A=Pk!j-9wC2hr7bjM`vC=&&x5IYjOT
z!?LSHo=bNKL+fl?or&d9tV2<pWjP=eV*TJT#@%Hd>Q1UZQt7Zbd(uHvL2l^bnVZHw
zlZRhfM8V1uGG?2yW>4b?yN68&)%-*k9JdiNgV~0Kl%H7XR&Wo1_yYW4=!N;RE=oFB
zb2h6H`@Afy#Ov=%0+&#&M2!s-=2Su{1-FVAbCPhPur=mvr06b_nF$a{7Z-MbBIf{{
z+!0<NC}fFnj+yi;z=yhLyP~Y(`S4N+abX|qp~$5&q*k>ypo0U(`C3%)zazSfcd|Wg
z)S+f-OXeobwux+pN`l-<p#IRy(aqkPaH36`jvp{yT)MicjJP(!gAHD<o>{35VFt3*
zPTaT}2S)1h4i4F9$nx9@o4a%7;8~0vhcsi@I@QMXel(Vs7|!HBKh5}YYCfKLC;G!m
zs!0=%?O6hJa8cy7s8u_7F*f3fWRK*Vw{}zx!&whT<pa!I4C>|ReQdohYQ-08yzCdx
zxh300&eq2bkXd7=ejVqLi3tXswcc#74O`{*H?iH}XQITHd_21ellfA~(c5V)hggPf
z{$eeYpW|3zD<nV2aasZOa07LIWt3NH`M~RA*Mj$#HQRGm4K0Zhx$OLG<hgfAd{bGW
z7Ot0;+Zw5R*V**^D0TzFFhlYOv1L;`G@P_V+f@agO~P}T8k*^$Gmp@cGJd?3i=Fi=
zhcD*?I1F3mm)KPZ$;=y)<ENwdWpdydWc-s`w#f_E&C9c|#28dduYjdb$Fexf`4q#C
zX4-oF9id&Fzn)j~R1$p#5*wR@O%f%%<!U&dWn;EU*ta9szoLA_YU^4QhOOF~pR^7z
z%4x0aw?{Reo)6`i!UoWYo&2=DXfy{Hi(JfaY@tZ2a`m4L`)Kh^)6<N6Gx=mu0rgTR
z(qgC1`ytmcjIJVf#-{s@C$m=1xGdvnST$&Y5^}6yyTZo-{^L}W7y-ll5|-?$M%$K0
zL!?bhuu<INWt$68RgQNDt>PiWNJZU5z|S<NxT>uEmrkwcU#BE;Jx=z7{h}u^su{v+
z3#&DsV|IDBb#Vp9nJ)<Wsu1V4nKTWoYK$VM5a{YS4lj;uv>Y?}z;2q5rzs0bRO7}i
zA@3MQcO`YkCmL6q{FI+0=2XFDAdLH<AVn>pP8g^;<1Qo=Vq)eYvW8WrrjY3()_D=h
zdW0BO)lJIEFBDrTRx8%-uVJp4fp)Q<E)zW0UTTM-o#Ei^`37^UKbB1`uwYJC*j6AW
zT$~}60+}@mLu?1WQ^z=B?Of*JTO!9b6<<dJS2acCyaq866Ej<=X(3rMC8TzTP^^<A
zA1I5}fWJiXI&>hBVU@@gw-yrm*~v{N=kl9{v0Cee6*+7ia3WWLyv$E*f*)8yeYC!8
zFK4N(+a_Vw{cgmb$1N*_qPB=*2G?RhW;`MX`RRbit%7Ak1nCOKHBGx~mT?V^Q9lBO
zE1=z6ZOn_*K6i&)VTyZTgNLWZf7=WenV{e-!Rm&!bDke&w`@@@5H!+^exail)duoa
zfE5dvYuP<NF<O8##}ZbGwTKNc`M81&TFDJ>s7YYsDz3G2-kZa31=?$TTJXQQlJMW*
z3B{hAuWVjVj_&KQw+e1GU(C48@N-C|kbuRm1GDTDca~;$*1o*xEdZD@dh-|wW4Q7Q
z0n;J^-jdmsNT}4;;^jw2lHE&J=qR?J?n`tl)|sDa%eD5yBKr@5M0xCDUOsby-@Ye4
zc;n?-$O-x)YTQy|b_ljhAZU^;VF;0X^IHQO&YQ(GS@!^ulc9%<>~ty1L>4`7KaPf?
z7Ah-84@I0gD0YgSFCM2u61_iPnOAw~bVdr+rfMWjXYFSY)myksdpIt$NM3DWHsMV!
z?^)>W1)A|K1=?Pwq*b;T1|i(CRg1Y^X!Hw?Z<;1W)c@usJ+8Lq*Q|<R#dpGqytLCx
z>#eZ&cOiN7eKWV@*A#3__4j<?6F(M9yk$XVFIe(&luZpU{VaP=%fxP%j5CBUp0ic=
z$2s|OF)whlIFgB_OqMSoyu5NZ-3XoWX`Uzax6yZ<)y#8_hgr``(D~(h`F@?LUdhSq
zWfbVud(p?A%f#JA;Fhx`Ieu|z2fnl;VL=z#BQrJ`be}}GQk#ykcBJ3kv|t_aN?4Mi
z%s+CwPg|GXYe%4_RvjA;FrM9v4fy7p94k=esHc+FnT_D=@oxEz!cyLRq$bH!4-Y(b
z6+_jh&Zkv=xiEv4Cw(=F{0qC;F8U88eU|m@{4%hn?-#)am^DC}$LefsyI!1oX&}ki
z7b+t^iPT%WI~!p`J{_p!aV%qpccr@Yy2yjyyHw2Zj^tKvYFk4f98+_;%>5YmM=GuG
z+|O`AM^6lRl)iJb4k{}?1!$a|pS9$bq$TbgKQ%e-Wy^!_l);hBr7{~@bYPRrE`M?=
zk6)i;{pJlLlJ7_&{lDkKq;N@Ty^E56O8A74mxr#WM!e>IKwa9_j2GLPR_>=Av2mr%
z64#5~fM<GQsNSw^Xjcg~d=`+LV$;Vhqk3N8QdZgvi8Fs6rg+Ot>tAZ1k<;6;AM<so
zODM;4+_&wmgD%8RDRF&rXLyQhKVQP0d*2SMdv%uLO)_R#O-v;?n5qc}`WC>xi_{p6
z3`$673$vW<7jfN-Ba+l5ze{x9`x2$%Qk!fR^)9R!*sB_9_d$=k=)l)p1%W<FW`)dC
z$>)sAJ&Ygu)-Gs)KN?)Jqbs@1^%j6i1+~#Y5nbwpCIK%^m(;{tfi1MIhu3QDwAngT
zN0~`RgbT`n{o`amj#Oh&hqrFu6y5-11)%hHSYdI}8&8@JsW{7c3d~y!B94P3f1Q0S
zBj{5Aqa75giD-DGVuiv2D|E};gCTSS?-FQFBSH__grR0lb6NBoEV>2@J_P&S32cT}
zVc2?ALY=4Q+5>3hc7pZ=en%pQYvz~{M&`|rU47S`!nlRA@!V{C*cuY*VM*u3Ny=oS
zp?;NY%W-;TV_TLi288ZT=62}_(jAW;m)NnEhm5&}+StH?jElc`^Cb6!@HfE2f-r2&
z7Co;fy;&lfsVYe4m+s~8-|G@iGaU$1{>I)cpZ986&vy)2K8R9&?S5?J#S~z%h9YzC
zrl0iDxjY|>qwMfSUXH!!W&X&1Z;6$#r1dCH9_7^2OIhEGCMJ*2RT_DQ@peR|V&v<&
zpGqqIfZ*&Qe~8(LbblhAVXF`9@A~NKyuDWw-i~{Db;52UkLLU`AC)|N8=tDVQj+KH
zK>5d+-wTD9kyU=#&7%X-cpn{|L-bx3|Jy(_|KWM!dw?0wux5T&l>YJSd^{;CW-ul`
zz{bW&R&JkqYb;y2pA9HE@W`CT>iw`hgLq5J+=V$BM^7*>5G;1bFfrqOD|`3fB}mYZ
zL*Uq^<hCQ1Ilq>czmxFSQ{DQ+dl2$4A5MPn*?xyxi*&lsBk_S-rRH{}bNNL&F-RBB
zz<<rwpC+W%wE3lu`?17+huIFDs^CRX=U5FZ53Q>CLSNXv<F}P5Ui*U{=c&bLb?4HJ
z?Vt#tqg;j}4w$g+Rm~N#-P|}Kb#8{zy`kMjFx&~j2Huix8D|*%4o;l0fb;I8^Ej4u
z*y7a^rf{bjwmMk_{P5Z#QceZOldUEdzJtZ3VIvi9enYbw0HrGMY|0s8CZb8_C=x%R
zBf_}MU^d5@V#H1RT66gO99re`j}*HAqe0^`f~f*0g;0vNl8`7rw335c@*r6PL1`tz
z9tZHa&ERW>9iQGK&cn0dog(~zb*f`GM_p-94`=|aYZr*;44asJ9<{2e+Ac2O_Nilf
z5<oXEbJgIlWX#b}2?{2M9IH;$EZ?|5Tm?BR;<R$h7TN_)TmHnHt}s!gj<Y{m@zS>Y
z?2aOCrSI;F@P->W;4d0g{pR5`Y1Y$T>U%2r#mM0;)PUv56&@<QPEPFf8nqaFgkdY)
z-8?F!YHe%*(d+ce;y1Xd*?%}OefWjL#J+X3o!Ir7uy-+)uekB(duP>>H1$?{<S4h{
zmMG;d1eWKzQs|dNZx6cV=P-pYqCE|pWT*lJs;su|TX?%m+zEKfzd<&?Mf7_+qjb12
zo7k{*@r`G@bC2gN)>(2;Z$nMLCoY#UFRZqvOHWCxQ7@AqR%~>sONaJ|bFW9TIhqIs
zXMa4Y^E+r(7yi8q@B3L{{SFQW=<aizzH5dClR;-CXzU~ZJmbf(+WIZBmsy664@lnP
zh10{c8LO?6^6c<Vw{ZAcFU~Mb25O$<dZvk9VlwEBZ<cK27wArJ{T1J|ly0C@3qQ;K
z{oU`lBR}0@Kl1lB*+9xxTc4VGz80_CPd6%kmDWT_{nJd(pXlkaz0{wOq*!e=!&ks?
z=6tGR(?GKlGi>#>&(vhZbDEA-7P@5^WJ6v4q`zNYzkz98KKY>gmQ31<mQVpX9p+5~
z_5tTn=jgG&R*tZj(BoIo)+W8{X!U+7sGa%A3>z3bdPmR0wuklvv4R%(YNB%dn&Q*c
z0;x<C`;rD^ijIwaWc6flNRrqIWm0R7HQHJ>OxxH4cyNk4R91b;4CC#LA;oTC1K>b|
zB@`fbiNdrtvxqq@_z*iS#cFF2vM7x*cOGjuxy?m{h7<+W=K^-8lXEIlQpyBN96HMB
z=!%RwQ9J#fHJYNw>*9K`fWy*+73-MR;B-}Q@~(N=fRY2S-x%bB3(G2@B?>lRnqg|D
z{JdSreY6NWJC(<4(<}hgNyQKkh3l-&N-m$W$z(D|-ik!6s{zC*!`hCB!OwmpWbvU`
zaRhWjRRc@RQPDZ{^}!&dux(@|>2#jLS{D2>StK1unDR)8boRenyzI3jdkFY<tuTB5
z*$))&pbnsK$;2cGXn6;j(|JR&%~`cH^FK_@Fc{)<v2EJT5Yz8YAt1PLQ#L1KNqnWv
z-D?$B;D4O6*me>OC$DabQ+H9A8)haSQMJxj4k_KujDNcw%x`19Z_nnY#M?$C+qck^
zFP}SHYnr-Nfo=bHyQoABJ4GN$l7koH1>OruZoDqnQo)wno2jbEox$m}MV|j?(<~G4
zOHSr;JGHe3&}Rqgd~7UerG!xi{vUlUm1moq?tt_3pZ+-p_&vXjGJQ;<<`eU2Xa^T=
zKT9S?W}@iJDU$rgg*5Ab!D3*8kEG{hs)Bh|Tce>TCS}>riTpo{PRViXm*Rxa7ozr`
zkQqCsW&;Yj=%GPp-HkA8MZ%Skt`1vYMpH`siD#q95ANNSq-+wFW4E(@K71)JyE49U
zhGB+M&2#wZl(?4&e(4<X2R<e~U$nD9sv+~g&d!{v{hH3|l;}Sm9_6N!kxw#$_M0Rb
zJRj@)t!gs;f-xc^X^V#)?rGSXM>K6uPz^AhBb}?8_W3{g0*5-WN!UM$eM}j)W~ZJO
zx{Q)CY`saAZo)SFYVuF(oZVx!sw+_Ju~?>M!0lS{dSBc~9;Y#&q9{iOaVQhj1_Kc0
z54+Ooi$q^MWno8=im6luxR4&JT})d_v+c?1vRJk-#ZdHzz|e@p0Q{^`ZCiI|*~|fE
z%<)R%f+Xhe0**8`3FqLkMym<8dP!;ix$girExZB70X2v7HEg>rn;NQ>#_$bhnRwvy
zeQT=0F=;Wd%xyh1VFZ#fZj!u^-D-c?=foy;A4I?!`;v@ACZtMrCEJj^Yw0eofDiQ~
z6yGRnjVE@n=Iycp#(@=%qEWq7__|-ov%<n9d|yrc7#Ci;YQu_e1oeVGohg*{@|t5~
zxOij?C8D<l3);?fx~oUUnH+3c8nr2%NM#|HpzEtug338*2pez`2Uf&zQv7PrrOwpD
zt;Q6-BBu`lLnxqwUN(jDZu3@+oM`w9mFUzO($2j0>YK$eAfr?RUX~Lm1tXBAOi&UR
zrpnAhY(Vi1MeD<$1C0K7$tn1|I5zeVtF0&FJR{k}SKpM?n=H0=NVBj8dCsy;bH>FQ
ze?4ucPuwes{@%Qc|7akm@1=!|PNvuy-i9ba8_?^$$om*y`$mM1mmj$wHuo>O3BGUk
zsI#cP2irg@@fU;f<$Sqwq@`6nVfxrsTg4>j3>miCHTzba<oZr{yliYP5|BmNGn&8N
zVptm(daugNOPeJ9(k^i$e~+LUwoWOjU17}X-2x*cs)u`=Nr%a^0{)dpIsH`X1B;wp
zE6vMmrnY?#?$ODj`)lkEGOlDvESvp7q+<LtBdTSN^k)hRzIKu5=f7dP1tg|c-;828
zv=`J@(Xzvz6Mx5*17RPMZOadeYHz%C2a5Br)YAB=i!#?Z>UF+EAK4cuI5~X2lk5+A
zwdmao`yW1ae|X2De2iy$cpM*bJk}FpLR|~WXWwj_@h}s4qCbreuK@clunD7fE;I&w
zm**t4VvQ#Vp-%Pa#9qnP>7iH#yYmvi^fo`>76&HUiTdiI;#cwin~vB?5*u(T2kd~n
z3K;bu#B1eRN~J|~6Ct??PKCBO4bqP^iU!4ArUGJVSs5o02uWR?Py@!uY72BZz3syE
zo2x}e2a2aFwE=56fWZt_b8YNtLPIh$y#^QQY2-4tc&aoRw;;6uK^Bg0YY@`VchWqF
zBlpC7pD;3{KII<yS7&*Znv+JVL<Au0R|h*~WZzzF3EkV%n=I<4WZl5Q#5yVhI5oEe
zJSwCOBAgt|+)6^NK$lUZ?xD|$i!V|Mh!0i3eBHps{#;SJPh}FsCEKv#MoUAdObpIu
z*RU170mgy(wQLAXUK_P0<ScZGKy3y{B2SVjrX>7MXAQk2hPNt$FE|#}3s8WV@MAWW
zdTLf4Oaav*l<18_T-FiuZ@`6c%g(r`ucMXRNL|Z$6WbTCct<t|o`y^wy=kJZ@`Xtm
z+~0W$$kI-lL%{h9l}j`i%T0w$q7$C|Oq)yzD*$|!SnU{MTkN@KBJzzuB6?Y5!t&<V
zEy&RO1}ez(N3yraj2Tg~pcQNWD?Nyn5#z##cQR}Z@3vAQOoM<%%gK?(CMWglm__;t
z+Bg!_Sl>K;sOb0VDDSq8G!wp!63YS1g5PH6IOXr`q1Y&?&C9=ZlHBFxCm@|ZWNilq
z{q^0En&;b}WF6<6i_5#QnEnN4k8YeW_D?OB6LJ>0F0eGqYU@m7#@bX>3(S!#_F)2#
z)KqS`P@*TkQ6{|fvyqO0F+m~obA~!Ro*Wqa9;@E%V!g#y0<T#5eY*<_e(awn&AE3B
zOHM8uw&wnZOx|-F`yjv9)4FYCVP_OVa-wV*E1&8KYsNYN#mV#k;BDBd9LW?V3|q|{
z`sl>F!~Qg9$TsUpPc@CQ_)pg6KPhC$CqqI#*|+H_xxz(vJoy=Kuh<3quOCl2(yx}w
zv-8-SJ=l^B2pll2X+zQdXopUJwIRgz)h4w>Vz%8hK8F2Ssv_h3q{YW+3hrB){TwrY
z&PU}ScA6LiwI;a=s7P(0`3_uX{!?zJ1ED{?ZsoBPwPo;1P&&PSH5d3w%|I1XHNoA1
zRd@7)+nh$u^o*_UH2CGi;v_?gA-OFkL#cw;7jwW1g4tcrvIpOwVf9vxni76i&IT9<
zOcvfeh}8U5pkiy_CKl~LJ%TiC+nE95N2fuYMYwQhQBvU`E_)N8Ib%f?C_NTC@(k3Q
zM(W=|XKAyVFjru@LB*o`wGy%6>EJ*wVwF-Od`G_E4GQSY8%vH#7vRy{(?CEzO?<Z~
zzg4LNGwluLotimf`AFP=6%PCuz7up-oAoTA|4{{w)mCsmM-@1-c?G}TT8Jl_mvGe5
zx$Nc-yO%&Zh0&MQzMjqv$`tE6zh_-2KzG_~V=qupL+PV9YrT0TN2rUrEi_zGnv0dB
z{`A~rj~!pc{Qk=W;oa8BUiiRj>wqj=BawS1@@?Hcpa`hJ+RgOkA`g9JE(~D2ar|bZ
zX%evpHXV8|8%-Iu%9nN&4Xoz(%BdFH@|*-Jzsj(c$fnGR`|WeWSjLooiC^nmScgk?
ze?N`&N#xI<ptEP0I|pumTx`(kXf&(AKV4(B^&+J5Eks%3+iL5ddp^uC#;o$nu+^mC
zK+-4A7JYJQQ<@(Bh`6`1{;Ie0$;h%;j(RVtbh|v2#Hq|TlC+^0^R*s!mIGJhk$SH2
z_CH|ToSxp`8)Dx<ZoFXIOPxVyFH&VUejFD^GQA~ePvBTsZIv6PasN1C{OQ17%w++o
zENyaV=_ZNuU9p!J>2V#a(@NTI8}`Z+SY2H$dehQWt0+(|X%CM&%a`zu>x6TZy#XZ$
z7Q%HFH#r>IscxJ}EU{?hObb_0y?lkeL?J)+uo3z&mO5Xc6z2w$TTOjq)?X)NlX-ze
zae9DSL=SwSEIb({2lF8D{Y1>zH(M|`D|gldwKE&V*rB#PA(6=U^r%D3@K~O<!YF(_
z8o^V<iI?ekbJsw_kVlYWj_IB@lS{Evfe6JKtqQQag!mmYZc9Tm^tQYw=2+CQ3rBAi
z^=GWIS_bSsaEuWQ@C%7lKCjP4qPj)_PjP+WwKD=d!kmQlNlTd{FtQ*dTmsO+VYM}Q
zUCp~7CPE&2E{MAdO!S&dS=tKaCGq^xiw|FjlqDm!0i7IZT41&_W*xr?%%46jL|b~$
zMw6Cr3wA5Yng^*MU?oW>J7mxnSIByL#~HaY%P>byq<4ZxB}xo^#w<A<dh_=?lrjw6
z7MR1ZRo~SMPx5QPz81_Qv~?v!&+z)Ookp4OLX;2w5Yca@U-b)<Azk%8X-Rmc%7p&%
zIea2#NkbBSuXttfTg0s69^5o_4@q|pJwCLU9URbrcC;AM=#!joU`OL^fT<D?Ur#N!
z)m9sH_5!@y%4+K;n6tN&d*P-*80&oO9pYcwCjQ`mieei#`R703Lm}DW2AkGK2Q$un
z*&6%j*&jGaYi^ao_9oAGBT)hRcP#Q#pM3MuIUW161BQNI_Oz)!@c!*+^P?NXR^x?x
z6rq@0f?Zu^P%>rF72p>+88Hl7LDT}-k4%a-AN*yR+{1h4+5Zte{p20g5~Lt@Fjgoe
zpbj}VI{peJZJO{!u|{A;=`FAh<aK5^{`dcw>}_Ce7hg+k@2aHvX7zKikN)XpQ2DL7
zb@KLE^nTy*z$ZHVUA^C7T7Zozop4CmMXE1s^}~zfPFj2D5^<8SVazJK7FHp1yvgzR
z>0F%J65jU#!x0<Z20r{|VMFSakM>N5Cfr%Q@{S=fCkENH<p%usbHF5`CudhwvNm1B
zYWDBw_=YX}bY=?hTsVs~%O)%wi?d4si)~N0E5~a^mX0azM8n+6C<$37!A^v}^Sd=q
zoG9B$0^`<1pBi9v3Lx3F5Ho;Dj$2&QgkDZZ=(aYNFFagqT@UCe>l9)IZl`M_9Qlw;
zWczBeNN0Kr;)F)V3CKW`VQU9Hi|S)A33+>d<B{>YlE04_qMF<Q!*=EYuHfhRsVDX*
z9&bdA)iaS=eM!aPh7Argr1&i)wTs2u9YV1_f)ZfG2I{5XSt%^G3if{kjOq67u<-~m
z7FWXzh(1&SRRN5}00N8agMMpciAj8o(`1OjM$^@Xqv$*~!5o*-DY-Kj=V~_!F^(9Y
z`}%YiW+UhnR{+Ic<s_RGPq9or81<sqsLli;#md4Q5rrkGAa<rFZ<4plULG<xww~R~
z(<*&f8|NP6XMQ=q$d#M_LSAe-K|Rq;dBV7su9GEh$?Ntls|bBoUOUDnY*D6#Xel*z
zy%!tv@eDa;)CVAHwgJeEf_0RRG0mm1;@g1#9uDySBH2nE?M9%&3WV0RTmH3aCdx{%
zJKKQMaKN7?Zf(@*Smz8y&FO?faGsRY<tZ>t_CR?l0;hG2#KK7_&cc&rWC(;RS4Q;h
z1(RqED$}YovCibOKL6WH@@EA^(^t#mSMszB!+Jrc$ll~+Q@+-@YT~zYiWSloB_1c1
zuD2E2`Cf-1p9&qt3dI68t^us>s8tKwdEqUluff~X7n~{iVEpdIGREh%ck6a$uLUY$
zpvnNIWU!jd4DRIT%%c&4ZZG6mM4_miltS!joy_M@nCHiRju}cqMrWP^RFbxL<J!T2
zUM7A_E%-kbX#VCLtRB6Ev=u=;R3cif2@p+jNvy40iL#h#&;c^sMb&F&oaPh+$bC$)
zndYpVE--!LptjY7`T)bPKI4TeqF9YPozH(J#5y{>tKw}i(=P8L;e&kG=;?n|s{Mh>
zOVPd9CUjtTEdIKcl2qi!vXrdVphhae%pavbEMKG{M@IEnK1U+G&&9I0Fd5aP&TtH*
zvT`Ixcx~?VYIqVCK7C%;`|WM%rET@XSt7sjXDZKL!>FUVNpjOB`#4}AIrPz`0=4nj
zfXt7c<AbJpP$FA0P&^gjq<;7OY<7=*<vxjqzxhRLwdEPVUG942A0@K%0#yF-N^Pki
zc4jAsmAHks(>y%``{&N-$%Z+Z+mmMPLtWa&w(&BD=tRFJde^v!e}M@C#O1S>X$qC8
zgXDTw*yV;Ib@m^I>JUD)V%r{js!fM@8Q?O`8M$e3Y)a~3xIEH&eISx2&zY5(PsWY>
zsTHe!X3MSW>5gzzM{e^n@8_5E6|o+=OkSSf!WQrHP?vTI{*Modd|+p+?$$)^IXZ#v
z*b2|J{2~f4n`s7nz}wE4<F#@V#@$3wY>+YD?%-4E$<_soaKv0jJs|7#iAFDDm^~UR
zpYGxIyO(iBq{4|d7|-bo^=8FjEgEi48?>1EDYRu4QF=pw8sDap=|^C9M_C>HDa-E=
zie0N=D@K5BG?UCwb_M<n7dIQpGT*b?fWQHkK@x9kWw9s%U~_ygVr`H&9PyEa+4Vq4
zky_-!9<>mjhsTKqaz^r5no{Ko_yv}Brb;3EVt<50MOuX$yM|<gGNg$gvK?^-xx}=(
z6n;`&DN_5_b@u4SR;%pFuRCB_M<nwBsiO{LSkjd5iV@EdlMGvJRW8?nhSQW%xsC+^
zYGhSI`IW_XPzsT!I8UlVk@wNbQ1^1snH_*AGby)1a@Ot&BFQNkHzMGGR&qf>37TDC
z-qev{GSX4wtNm6WoGEUhQoBgb?Ze16Z2dkU)P_+bjU+jViL8@Fc3&2kjkl}L_d)iI
zL~VwrvTjR*H)r%b4dH6%pQDr~Kx4<?3UXunVl3Y!$guT|PhaR9-U&Hyc|geI#jyN_
zSPtwq?weQ&@btYBx27hvlTNzo@6RhydDgr)_0iuHsY{z=c*&@JN1m*03|kAP7(dci
z9j{c;m$a_{Hj4P}?))1vm%Z%5jzI(!APigo>NA-QTW1-z+B7rd9^*Vx3dx54j-86c
zWELYAynS_%*FW{XOjm2ix+SOXOZFxg=}X6UO0;lIXbAGwCEWPzs66{R-GhI*T3gno
z(+3GlIW1*!9qMxehJ@GVdU)!Ahc0L5^~WWgW@>Y?1~%~3IlhSSJT>Em2WxChBz7A=
zGrsA~cM@SSjh2Y+=ZkYDb;qyQVl|~c=w<ulvgy}o$E^+mqu=D%fl=0ppL_j~<cBxJ
zYD|fjBOi&)24IMXbGYR!x&qSWF)+f8@uII~__g;#;RC-y=g9g>U#^*2iJF7Kb~Sm2
zi7|kWi;1mvIIrm#I8^}3=26ivB(m^YJWw3!CAa#06twqJ<`V5GzEnk|FVe%*I8Vxo
zOwkF7TyM`kVQ9(8rZeJYRV5)MVcUuni70_6L|VZ2t5(b}k=^t?{w&tEWpvCG08c{J
zu0}F=EYRl=!3p%BSa9t{Sy@BD%CgjnmLx@I)WOgeBS#sRvAK|769y+i`=}6xtxn{I
zFcJzVnGmjoC?CF>H)rSBFavt*nvzZznRv4R&w$uDd0IqmxTPc!%n)qp0pKg&$MA;P
zZdOCCxRszj^rs7f<qunIdk}*Z3UG5_9!p0<&<r&VW-q`i7#Md4>cdH0quAMuSODE@
zR^K{PiFm7A8}R*ez{LVPi?#B#0&!*m=N*Pn`K@Rp0W${VaX8+5Kq(S@nARS^6*%Nh
z?HJ40YELu7ITN=*GR%x|@NGE8fxAZ;3+~2(+1!0Kz|lVe>jXcwx%?8I_%SE`pAZ<x
zd~#<p*^V!-F9y*PU?7`LV8h$s<wEPW^#J)tMD@hsR&DkkHm}}dOF&F|jwP8s#O%cH
zyQo|}=z-K3j$-T#Bb8+Y^wj%&_2b$)>--yrS#TR**h<H@)VAhtBdP!S!a0r|jB-7=
zQ|w!jEoTI+kfDzf<bNB()+pNg_Uxxj)jhvrk=H!kz|8d@e}>8HS0p;}Rc>}@kG=Bf
z{M^|Z|K|p~N&g!isiQY`qtQ2MYEK$gTe(KJpDoTJx&kXG?#T<N3>@m>murQ6CC4QU
zTU(c1l=-thM#42P-V}0#acrIqgh6UJ&T{0u$6^0vL&ao;v!cRkt9iPCE!@nVlV$1i
z+VrpgkWAHwy{F!c$sv*Nz1d6px0Lj)v2HZ_CM|SW^Rn9-H)=Z7!=ulp%W>j@#Wq9S
z28OKzd)|s+w(sITI*}LgALN9PKP}c)Q(kD5QKlBJl0`ck51>{cjGB16R)U`6YI-zU
z7<esC29xp7de2K;hF|>@HR-cUBELh?8*mB-d=Ir<V>{OaIAz99Z6y@7ns)3OBVeFm
z$)y$iCC{f~6rML4SHOE|t_0Tgl>IXoQwz5(P<%2Ga7UlwLM;gfe}3KU{g&X14{{o7
zl4!h9_4qWD;6wvvuM<T=CDe&<9iN9p_+np!^D*mX=11g+b5jj_$;*-!Q2@OjZTr{1
zLg5;!OwP3xfzOqHZo!*7U545Xy~S-n!IYp5RQpP>&pHM`sBNn^Z2}%))BUs5k1=BD
z&lJFhmpNWa9hz)jC0S7oh!Mxce;`w8VH>^c^;X*S;={Y_f(yXB1T@RFzu33$tW4dw
z*!ylkTTJUQ#M6oen^z(Pp}<&X3ygvt?1aSHblTM1027MBh*v4(PLiV*j^kGrYrbya
ztyp#F>xgHm$;g<110<Xmqxc-A;rpp0MeZ}&&1>-J!XB6sP{ObkpT2XIDfG8udDW%z
z*u`vBcvIpm33-bw{}@fJXTDf}o{(D1^*CR@kKWQ2OtUQ+R6#07#Q!Ua=acc_9nE{`
zCmqyr%e40#$?{**s{?^q+Z?_D5-L4>@HT9<Z)+f$D&Qo^H;hDC_!<U_CP{(MdTk>A
z=7K04d7L9FFDti;8t0cr2U9;X?f6{aghWkwM=B37+#UL$6-#ZhFH!acgV!&nSE=}=
zgFBPqbN2?r>zB4m{CC$!&Ki&T^Utcj{ho^Y9~<dYc3h9i#o2T8yjz#m*1JqCJioML
zq^-6d9eB6ILoCDI@rSj{vq@M-9xwN$g+dIqp$wFFpD*KgUQ!ktF?H07G}3{^c;q?C
zoO!M$lTTgb9pswy^3s7JUV;7q_w(8h5w!v75mVPT<aAGcJFwoBdLYYFr%8Q3ad+)R
zKG@XcxdDbhhWbIy@IZVk#i%$B&S*5<uu*IY^KH+%S7>GSmGvfDgyV0k%U;@9>>mA-
zL!OhFv@Yy4)z>I%15D!zhT{_O)hy9~QhcYVv(p^nV>a&&GpNxxyZ|ZIoQ`#3wTq)i
zydr4xL_UyR-%*m-Yz#4K1t(BE!0O-D!u*HUlpc0V-o^1<D`eNFb>^o8mhhOKU)U<#
z(<3+NgRWTaGKbbxqH$Q?qB}ZK&}HuuT#gOHm1tBRzYzSL{4cgOwNci&GR2(8IJY`}
zR;Y^>Y`5&wHZn$gb)CHZ746!*h4sZsTlMoVg;|AFyarz5Z_Qa;Y%+^5iE+!cbU<h~
zxti^Kz^<&RHA10&vz#B-ZMp)OHK#i;1sTiee2iF?pIFbgefP!QWF>~Gh1>5i-DUt{
zEf~TP>lF}*TU{J4aJ9H(&SYqOU2AvgB0;sT6mlruX4ws_NT5LFxajVn(<aNPA#%SF
zh<`MasXMGF01|UtD(^fXpXp8`e1oQV$}Bk=OU>r)OHQr-@Qb4|tY?jCIBU?*=w}_b
zs~@%r2_QQxe2ENZe<1{YmQJy?Y45xz$;dA-i@>;OY6q73+Big2%VcJPSE`nnx#C={
zVHrS#UuicW+_RmP`htCfAz6tGW%r?TfNpP)BAjqD97@J&tG$R*0TZNu`C~N1-;zY}
z%QtTiYO?I=B5%5t5AiNa#3td<gl|RKb_jJ5m-JPP{E%Caf1M0?MpDV#f$wVL=?i~Z
zMk$gPd5lyS@YI{Lx6X5R;^>0Tq4`Oee@Ldu6V30X#(Z~?sizC7=yWOK%t_LHG=4~>
zRleI=$=%Rjmi-qwx#FWRdYQ^_RWVL!eG_FhrdloW(b;SfyeQbmU?Ao2<)nRyGc%9T
z#Lj~@H1vdwwAdEW_{uJ1U&T|?!rF)8WN$Nae))#99-pw1WbA0ISVuVGS>5~VEf&}J
zknFq6nJ9+Z@3vNRgnA%Hk)M7+TVdNvd*u6}xY^DftEa0RhONln)@=qkHky7D`?T{U
z@de&)HdmaRNPJfmx3q{_-yM)ywAy3Z`FPHA7zTz|qlW&hqgn#aoTF3bZa^mo%J&gF
zqfX;r2vhT8*2VF*CJs1MWP-->X$u%wVsttcJfh^%qL+k(j)G*M%-vT&kew%|7mdM<
zG47pNpk!oAf}JUS>UZUHzkQ{1+LaNBZ3n#(6z@~xbyN8CJl8nKK^Y5~slEG}1RG#d
z$i6BE9H^3DsY5oy-OMkI8s@EpU|dmB@lJ;HcDVx!V^Ejm-&rh^l8J_8S3>;_u`i$B
zadjr6;FOW4zi5z3+%$7&unjH;Pff!`OqE0wsRFHtl`_5u%85Iuvq8kL)d!yp#Zy)v
zb`e(zy4z4<{!*uOjXag1oo(NU)c=tE8azPWUaG4kcqStp>U=m8Yv_e^MxNqVX738M
zF2rgGZT_wxLn?9>vi+XNkm^VwY&mpOOm-z@*o-EQ1(X9V@pT2Y)c7vm((+r)>eEpQ
zH%x322-<CJ02~;cF4%B4X7y<7V}`9!$^P~E;|ybVtR>&LF&SuH!l>nEf_)TSvL?2G
z;R(@&;JuF{ney9EvKK?pD!@XC_LKN?C$d~<dq`i`0WbGAs?9MW$A{@^e+6;cZVb_3
zb`MMRH9{}j8wGt2YI-)1e%yH<hOOuKz>#rq>ibwjeIACgs+TRiG34^ddz*>elz55l
zqH0`ke3>ru?f()({n17G+hYruWwuFBtR8tMov+*3zV_4BVpf3>+x4C}ZG7!8V_#+@
zhOUl|5$E|uw=%JD?Da*_@BJFV{sv`cUvo~p51WMdM`^^7Ovb%x_?v%=EqvJpp2`gu
zn#y?h!&`H`au+YmA+qK%n!?&ews=4&x<sPK9*>fGo!O2|w|k9-7Uegtqv^GJwRv~h
zI(IKv<smFJ8`UQ~Gh%VPBcL}u+iV^h^s@M6^f}>EEPW2w?o<pQ6TJBlGwu7u#d)m<
zmYCp|8T9+MYL8zu2QQcW+v7-%ye&|0^3AAauW^)2Mp0W^Ox{;cBrf9R8P68C6V2&C
z@zbn{Pswjr7MzF^J$tMc_Q&jVlDNUikjXQC%~;#<HlIi(*?`cqY{3VwI3@zBel<86
zw<&O^&E(F|yunXX+$o7oZwt5qawDZw!)tZn6A7V=#k=fvNxDuBO)k-Uyv#Ml$$gBL
zDWAF$V9M%C0A(y&di(v7>ZGv%31KkX{OQgVq?oF<alA>?<dcWBG6(^5f<~Kd<tdL5
zb;P4u1^Qgm6C_&}HG-!H$8ncx`x=KN%9<S+t_sprXe*=Qz6Wm{P}gR^g%DXKFo`gV
zaM&sygWHx$&0-Lmjah_F(6EI74KB0%2xS#+K<mbf!gk4APt|D_g5HdZgUra)a!HZh
zCGrN$a3*_srzbB9T`i~&eF~$~tAeVQPtVeJHB8WZHfw#-vU}Drp0@d_Yw2KeZEoq1
ziPnm3!@+1CuWJXpU9Civai4gww7_(BVP;uJZKfIkX#=D+$UMOQzzDUSW!rk;Njf_)
z+LUk9r>#?@c`;N>W;=FrrZ%N7*S1B>&hYpn(1+_bv~gQx(^fxso;0P!M<DYd`Lq<8
zXDI8!4kj(AHp!8OoXgymdT*%pl<stnN7*;!HkqC1YZw{FfZhW87e640H&)muA(wjL
z$-|$pVXH%=_u6V}P#w>CqY{(bTDSb*ekTK9IU|Q8n-eEU-sct?7LyHJz-c~L&Po3H
zceC}hUW|hbwHriJ*Tj02j?%u`7UWi@U{A+WoNK^$%?>iV_+abTR%=o>QfF}5W0A^(
z_Iw=4)O1{Hwn<p=R6+Dx7h(^8MvB$e7a9E`&gSfZL<mr>_?X1G)ae#;lCU+jDv8J=
zkK!AopFFGEMfdGYqCdbgH2+1Enbd=XDvO=GfHMR>AcOwlSfySJTir`cMSt%4IXOP<
z#ozRXDkA-mZc^~Ykxcfu3|p=JtAzMyhRU3W@jHQn-d*C)CMF=x9{7EU@hzBzHtl7b
zkx$ds*w$IB!^Ayv7Wt>UC2C$qM``~%eL(5Kc~6|}nB`@2KO4{9n`CZqDr9;^GkJBl
z#LY2+xAj2h%tu)xLodRAHRvSLOKjo-`Ph!Z6vi?%(ju!X;)6&H!J6v@jAXV*X(+b%
z#g;|WQ}g5tC?d|Hx&saCu%qbIra1$USFPA$UuhY+aVa=3T#oB~;IZq8EjKz?>fvW9
zO|I}62_->BdF1empK(OAA<m2UAN}GU&>3K+GoE)m48b(K?FR4ZoxxJ{80};T0(Xci
zm`b}$Io`Zsv^<WlzhN<Oqhaz{0T@;RsK%OYY~(kXG!+_=N%Py=r);@5ZyTC;?B|rl
zA}ho51N?vw*Ggx=YK}A6IdZ9Mu#j&xqUI8cwI-ZlYn|i`@bjnepmK>!17BlK-(CZ*
zT^;f@(PdzPYoHv4twG?*Hnn!12!q@cSeI;QtSLTr;KziF#KfwyE5Uw;Vyg<>mXZ;+
z+BzQhz!h&BkDg%~KzG8~b6QHU-l(BV*UE_M;e5iqdC1v!7f6Qno=w7EH$U5D<iVPz
z`OVp&AMueK|12Y=9R-@9b_LzT{Ks_U#a}!vo<%`g_IOyFH223|mnE9mI7zr*ps}4{
zD@+17#Z~QE3GZPKVb~;`Z=yT&S1^{Q^axh?hJU5A2XnDa!jdGPh=wmVT9c`hp+8Ab
zG`FBveR*e`aY_*1sE;IP(oddZtyB%K3fK#rW?vo6=O5T4zniqI0{Z2_`$Rr^tIxK-
zyj%1`7PkQk3+CXr2}Z=2-3#d3w<DF08&hl2{GF|8nZh<>t0k7u+`BDFSZ!^aTi#Z_
zoFrQdwH8<H_tod+_U5Ztia+mdiPXsroCNjUmm=>YbhN%p&{p~LZ(q!6>z>S|@A2Zt
zX@UD3d>XngVN$4IMFV~70kY^<qa+Q>o+m*6@GcW(@d=&aVX8vDfEp{mHYE9NU}X)O
z!2-N%*^Khb80MeuO%`6ZZQUxfQ8H)UUvYb;jne<m-uuT{R#b<+tM=KaXLnCCvwP@)
zX5>emo@O{R0v>)Pqaj+|v}4O9dcYYoAw&;Ikf@)V@n<kWtZo`;lq3g4?|Ad;K!|T7
zByTk2evB`l+zsM;6Ein=Vla=~cg<__A;fUG$;7KZRASzD)!wJO2d2+C`d|9=>OQsW
z$EvEm*Q!-jtA0-X!l0N#o2+;p%)U?ZcggeUOY=92mANXcZD1Ot2hf_19+N3*yfG!^
zLP1a0j?d21_NuhtWv%ix4<%x&nE8oR<W%|X33NbN-xt<~&Jr(yYe-_x(_>wSl@wU&
z|Js$ltJx<A@USRWwbkVWPW4D8_4lT!z24Y1+LTxCjM;XW>9ph829KWPglH>0+kq#2
zPE#!S2mFn>#Yr|pW$f{4X}0SSC{V);Gtc*6alxyL(Nyj*aHO4`d?`d22!@A@>pD$h
z6pYl8?gGO95FU0O!$b|Jk5Ela1{Sb_33gTq@gAcaXtp6bWhsno_@XpunQ$6gH7=``
zb<p7%t7L%OJqnFwd%qCRKu<_b{i$(LcHr_6FOf404P5NJH1YStNh~*d;h26J@}?=p
z_~@ZbiLos66($EHA-Fq`Z52dk;A-TSt8LDw;C+n2O9#2Etb@pz>`Prlxt9%cn(Xe0
zBJ`FIP}^lCu(ju$?^@&9Y|m*Rj4oxRMnreY5m40&=TbQzayN9T%3(MXd`97Bi@30r
zqlF3S4sTGzX~`lR@v5R}1<-8wV{=-#P9xoQ_@O9(YC*i3##I_BOB(!OU8t6kS*AlV
zVk^S`az)_OVbxGUA9JEwE5jIggw!--by&_ePaRBKU~8QbCiXPj;lgwM;gl6<EI=?i
zQ$+cw5fBhHf~0x1y#!kBL@#Av0j_P)r_GaF>2-3u;`tS?=wFJ~i{QUB)*A8|P(9BZ
zV?zON=$A#I2cxzQP=k{bNJ^lw7K8~Ku$@lFOu_30AzoRpY_w`sDGJ<BqFa6{rII?u
zBTOCLz}3Krz$~&Y%2QFcG=&yPdF`6_H@tJj=Z`Jfdm^#S!>TOAsp~^Yt#sDNYQIW3
z>9D|AOAQ<QrfEr>5g6&7Weox9MA@2Kdtt_n@KBTW@YiMJM^;|z+y=Ecr9<!fsNn2-
zP?Z4Et_0;wFQ9#$HaIL#iq}UDFv%@7a-=w`(`KHZb&c>0Xk+r*Jo6F-S9$_w;ls3z
z-pgAh(*4A0v5d6W_&sIvZyrghu`DQTo9hi;k2Eg)bS|TEiOMdcObdlu9nA2=;TV|u
z@59fb*vXN*@P1@FbG2K>ja+U;{zR-C|GZ-N3OBK{HPWK!(3&<)65la>6h|`0Q{{DW
zy}tx?#KjonYEy<Lw=Q#7{Z@s0CW!iADQ^^;pVVOqQuy(_ggA9PxRt?)XXYfUvO@5o
zUEbH8GNz_CF?c4tqi{=M%lPu!(2#n}6vX#RbR>;NWN0rn`<&J@K4no|oG@MB4(>{N
z+jyt%x3(c|AH*`R-^sSQ6$01c%b%g`to}t=B3-EXj%T$<u*38$>Ow5xQpu6+j3Kcw
zaYlna^|DB6-vTSaIfcibf&ZRL^Nq3b!`Dgc{>#GB2F2_Q!(SUo53}#`l+9G!V|xR#
zFULu1`o>sV-(phfqV2A85`7Vx*<y}G*&&iKklWLD9~g-1@^0$h42jJ~bs$lpC=<6}
z-81gTnUmL1M9yKMTjXDbP^MW+-J#<onVt@FHp9x<w&YmA3t^p&*frBQjlFOAs<x+9
zL^c_!Ug5>x=4AB7UeoEE%Nhthfe?_scQBLC6|jM=4E-!6HIoO33*l6dJYCw#ErkfH
zA3mY>FT8MdhE#M@2CHqZ(h_9yTq3G~=8HCsbWWxZLQfD+h}BD<!z*31#!bay)1Myd
z5dh`Y<?QuEz(lTzh}ZB+Ktcne6UEqkB3CrpctuF3M>;OCkG!IIqo%@uQ#0j6)LzD_
z6nAZdl_k=^q5!UY{{?}b1h>o*g@Byl(AexuJfTeJSi?$4W66kMi|ISfI*nt$5~ZVE
z_uHv1WOJ1$L-a%O@u@WMrZLc>mY1mD?o)%JFEovS=jU=FrOTYwkdr~cI1vxFUP_g!
z+zsGzP8Tlt#}XB?;5TpJi`R*TK^bd2%4HZ0d^3JsAf)X;vJajwzQQh_M5p!ChnhM5
zQ*Azc-ZfXRz6JmHbA@Q`HCDIH>7te53e+w{;h-zj)E`Sn>G4EprxDIHJC%wMP>C8n
za0-s&O6mX=Mk};5JhJ^Dw{0|G5sMsl;M025ctG$=sCk6d%qO>AnAqWLC*jj@7Pfjz
zP7gB-dNZq!d+brKmipT8k4KL{;D&wJc+qWh$$J@@Q|fnvqlZ}%@nFfZbBZP2&nQ<#
z9@wuZB|&I)yl0S+z2_OCRmW(}HyY1QCUVAKA(+)SQeoeW)HM*V3tmCCiqi}1Zj7)|
z>mwr9Jj&q1F%^1AUR#|^lMj;Zl_e_!f7nYpYaYiaM^wh<^i#tafm*siGQjwdE;9^j
z>yZNiefDRz=4$KVrzjb!wub$5gr%Q)HH(`5%HlIcDf&n$jmXwCuZrsaW@cmWe>tzv
zOKBQ@4^8vFop$7oS20g~#B08OJ1WxoHc1<AC(*C{D&@4_A+l`>xZJ|nLND}<TDIw^
zv3*cm8(QlEd)s#kJ!j159vFz)8o<_dkJbOs{;;a8Un*z2)SuvJ=+Sw(CcD=CMO*U?
z5mq$@X^_h$*4tFf7f_C<dAXH$WOgU(YmC3dGj_;`#5yz}fuoTBkf7ZrOI)i4>wpVM
z@k?a`Tc`}2KD9!2d8uJ^B7jp<^DnEVJJ=kBY+Yq(j#lHRXi8ydVpuDJbvTg%)!ulV
z6|pWtZS`}e#u}v+5c?UcPOnA|OrVt-6|L+mY;~J=xo>WIABx6GuanznNYYA7!Klfo
zdC0f|E$@?u-kK$;erN0L2$$Z3?Ug*eZx4lR*9)B`o<`Z36%16h6)_4xuX@%w0v6O+
zqfzz7V#`4@T?W|WmtCvc$j*h%l@q&7u3W+!CUS!eOx|D9H|lHfmxa%VT+nN@C(>#J
zuLdHa@#0`#GFnSEwFK4`P2KG{s<EdB3_m=R=Rsjk<{}(L%ZyhKFq062rD{?gE{2;$
zEQKi!$_{B4&mNLm!zklkJ1={oi>j@qTWoJc_Lm^3*+!=0&ZgGeoJ&adu_Z!zL2Z@z
zc-!Mlx-<u4JLo0$j6E@La|J<vY+^YufCa6m7Z{Wsb1hm?ANiY;c+QhG;I#NW$otGt
z(A;A+_3Lv;qK9Cs-N#DLPs7&ag&yePz&T16SGQDgy+UN0cTp;U2M{}Du;X|2X9wh-
z^!X7)3y5#?u|0Z6Y));Z<FjTsj^-<|Yy8b!Qv2%|!Q<NWuHe8(-j=qG-pg$36mz*-
z{NvOXuC{Z5YpR}1>e+<xW{>iC9aL@AOXr;)9=qkC-Ev~*=VSz`QUmX}#|O1ll%Zq$
zMdifnjY#~<XH{*zn^lZ@C8X0NhVG|*{VLh)$LZt^PPbdi@qeYxJjj5BM$%tLAlody
z%!##}0CoMQ%EH)Wz;Bl66}-#RzP^1*<ZV<E>i{*Vz4&q2Edx!htNd<tbpbDSP;5AW
zKVUxTcr1ukrvZZ6ittlI7hoed%d!ZD`df0R&Y(30q`LSAHX6FvXsOZ*w|fA$*MT+X
zqr)$gg{;!lDDkxA`V=hMFvw>&buAwnX^q259>$Lgoe!Ou?g?BQ(d8pl5kfpoOb=a~
zS{K{b7riFzsd^|l{-kn^T1)NC7Cox0+D&7b1;>kPZ0q1?U2Sv=m><-z-UlHSxo^NR
zdTzUZZ7io`1ybN_n`10yals$HrfRtx`M1FbH(2v(uVBHSnqQBH`2m1+r=BXo$6ght
zJ7=4DvBE6RlA-pObT3zLgH_<JU9ig>S^7w~WLw>08UpJeXb_PsN2HOAti|34zF5Es
z5PDMH*w|;1dTk;##3woPLkZBty2FqPC0(@L+F{EI{9@8Slo@IO-_Esra%&vp1m>RL
zIO&In4N+Duqw{ip8=;6*Ff>gaY*J2zV?%h3qZcR2@06{IUPU*yj7dDuDvE{!rwate
zM^wPpBkp#HS%rIvGMY1()r;$pQy|f9a1LH=vE1UM7@Thhy!2`D3cZu&n-C1`6fr#z
z7&bL;<rb*lILE}{Y*Ko<`5^=8tdqqBkRCaYQ%IS-cit$Q(neb5(Qagebrr*^|A*zi
zm>Aycbvo05(Xg4^KZJc4RXF`>z*F3Qh3vg$>O;QXLVWEh#XYI5O0J-`9;VL|afL<m
zuE}GX${ony(5<mFK2u8KUu15jsR~TCfthWKcpV2lED}yeS;u5q{%K!Fzv=QpmEE48
zy#GUS%Z)Nu&)uLimmC`OytGuR6Y>5J+bFw}5;AwDdi6ad*X;9>e#IDnXdoWd*;eIq
zSNOl~VbKY*t$Hj>>$#s)VHLldgT9MWBFPy8l#=&~I8AGg<-=Q^yF$|8|6$$D_ru>S
z&Svuc!MSMmvdeVOYmac+r(*e(J(q!x&Ei=k%$5z>YN9{#f5fKcP+2EmlWzj*F~PNo
z=ACd(tmyb*q&Iz1oqFHxQ*{KlIq1@e+198=AH_}Pd^tNdwuoHcvZ>^kW?O619~WnL
z!Fxub?~lI7_<`Mwmiw%@p=0nEs234ee~js>jnC=|xblKIc9)d=*R``{X{6^Wi#kp0
zXlR>Pte!%jhFI7ozU#-s9W4O`aG)7+7%~FlCu(X2J6##T=l0O$&D7qAwBu?~Q50>t
z_Vu_r1KHAaYHTw%B=aE~t9}8RYPt!M40yR`|C&}mU7I5)>>N+euPbB)Mu>Q~sfBT(
z;s8s(6x%ENa+p`an$v~7u5pTwBV>$ht!6vudu9a91<8o9T6$(pU?npXme)v0FJtbP
zF84a9dY~c-OAXVbmEI^a=L1)AWRJAw0C64tBysF@!p;(K9FOs1b>f0pwKxo)uiAzU
zKNy5|+l%82Ywp#l+{c>9{S=5;C)L})2*-r)xs<eHt-+^~q)mrq@^t*rL@LU=9K4*X
zH7TRP!N*WWHtM7~ti?#evISHbPIAE+SZT#-hUO0Za^4b|NgOpg0bMLTYg%iSk-UOY
zY_CS~;*Ltd_xKSSZEb>s9FC2t@$jON#^N@}c1sW2SS*{#&6{T%fhgH;z|!MZ39EcV
zgMoJ~*w#8b+A804Igv9{nIg;@LF0+0C!CwqrA&XV5pr<KvyNaj{k?WJoao|Yf;%7b
z&Q{te;@OW{=Xd2LrDIZSJW#tI^MB;nwRo!a+fSK3m*XdG*Kcl3N?d(si4sBob>QP(
z(&ux5hlQ^C97m1*OzEQfp4+H%U!a?;={@~(bcEG{BI~`JV&wck5M$qUI!7tt3&Y~!
z9@yc>K7eMFMoB%Yi@W5Q^OPSMNybBw%8v3*(fWumBnhX?>fy2Bs!rY8YP*ux66;f!
zB6~#gy0^7D9a!u~;#3}aIi1~4oi66~>Qu7uefBzmEpPq+!@m#CauC<sCS<ZTkVFIL
zG=hA34W8xz3uRD8u!QQnHKOu@oHu6D<X=2a>xFDXKt>U{db7`K4TAa?oKAacMJ&v=
z%1|~OdX=5&p`ENluQe(uT(n!_va!f{jWT={bFN>CoZH6{c(;}qDEQ4FjG#{uyjP~o
z;&&(wZ=IKD@f8{)henIl#a-DN^rgT?vW=ofl%3;4{ODKO>7YheU$ri;IXM>4RUKBH
zZOsKjpR0pc&9D*rDfB{BPTCODmr5-%<Jf&VJ+o0<J5)z7To5Bu!HSJ$upO;8@d8~D
zjrgnS01VI9mn1w20fa@oSUbmd;{EwlB5P+wk08{wX$>A-AY8nVG{zOJCex4A<Zv@5
zW=lK7rj@4{i_b4dQ9PeFq8^sV+M+wiuUQAkif7k{z9^j2$vN)@ZCPg}*t>yQ0JFM@
zYdiY*38jJ#0tuXBZ>ojjT_B1lEGWuJ$BidQO|JdoG!4$v*-)}xj}TS{SPi7K?D1*|
zU<VvLS;>nVG%aOWM<BU|yvu>AYLWKEP={9n^|Bulvtj^jWoX~oozh<<^B8ua+O<l|
z`<fXG>t~383fYEC)z`?9N^~z$i*vpmr20q>c9Kr<i9C!|9kp$Q?oS7biu{YgsfT&7
zZy&m&ytlMS3IF<As($La9%$ed=QjsT^pqsl-^@O@*A%f5#_P|RlhLe%<}>daa>Jc@
zi2FFiz9}y+O&KeRakDlA1t#d+Ev)SfUS|V7M9PeJ_ydzEmv8Gb{uQwI_0n40*R@ox
zh_ObkvEFiTQCkPa&vNWT@)o458>B?K;J=D{{HYz{Sgk9Ee`}*rfiERfk{n57ag;qy
z+mPbggA#iJ<dO3kJG_LkCY4hE$1vj&i%e5%2jM!>b>g0A8g=2r+y*+jAxR&sr#@x<
zxMr)YRbDy=&%ZI^u=Y2&Ij+ZjO*C}PXCss8Me*@J<?|w4$@1v#NVy{Nm;XDrM9t*v
z`r?MveDh{X$*&=L+gXD$Hl0|fSQnql;ln<4V}bnE%#`+Qp=l(<>u=&7%w9l6y5*@_
zcJ8vLoq0uw;(zbexvp)$dpp_cBGx{K3;F(uQ=FF{L!<oa<{4So*hAaI2*Y4Y_fRQ3
z|53k1Vuvl013v-tpnP_T+$i(+!L@t5G9swNWr_jaWQC6nM3Eb5<_=722lK?1d`@Q3
zLIA)v29wh}C=Hd|=TPw~@`PqKmFJiT^|86%xAf~FY+Pk_E9!y5R;$E@A`S}!cS{fx
zVDDGD))+Yw7QZYd=9TZKHV9I1FQI)k59nxGORzUSF}b!(H#~q-e_?%7aK9w!fYW~l
zjI`Rh)h=zil1r<SBD+???dOVMnRz)}NKy-TL27KeHmX$+If<`cst4%9f;7EM{tV<^
zV7V|@idEC3Hjh=B(!mbN6PzgCB@gOP(}vkr>PMx8gGCrUz>tN8L97$zQ33a09?RU!
zGvY@-HTEjg1%&E1sRW+^XYr-C*3PUUvBv2J-dwK*qU2h2J$l+R@K8i^WE;jvm~EZv
zmP{XnyJPuBS{|7R_FC@K)r<;~=CJ~L2Crp~Ga*`H#al5lVT$H7MU)(zfc!|Rf{q%b
zU;>I$RZADJ`RHICL2(y~2;Rt@SX*)~X7OG{P@g^wYKM9Blquui2$gSYGpidl{w(_2
zZD^-9tH7nU+Bz+f|9`p3<jM#NKTZ;MASZlKTjdNm`iPU5HEkmII*~tWa{#rqJ<`=N
zWAkA)vA$3$Kki@8%l>0gqL?!%ZFNQtZ<;;LeX?T${Sat9gl8sBTE}KZzPN2V)#aZ(
zKwTdBS-Qg<sNx<+iB+{#WBp|^H2pt+p7SV`qjTFPr2g4d^I%EvB@41B3_{d?KbqHl
zk8;mp8uUjd^Y(TDwRKwYy1|hTM>6@{&0ZegUy0HO1A2LOb0iCUsBJzMNn^w1^W73z
z^WhBiC3n4siO}a|X|}bukACt)?1DVb;wNTXhm&_`-6vj+M_z8E^>&sn`~nB49lV0k
zB=!9UZR~-g+a<l{JyOoh785^nmQCu<M6uUkU7IYSWT<OZ@N&;Can_l6Id3?w?%x+M
zJtu=mjJ1)G#Cd4T>kudQ6zBBXT%B#zlZ1PMAwL7&E!>5hm0T(>(@512(+@>;9STfZ
z;~entS4EfU77f;hxAi$WEMI_!txegO{F)1K!d8#M*7@PCZKk{~1#w6+_cN7%Z71?b
zt|5M#J+;WPb3$u9G?p33_((4NQ?OQCuyin(6a%t%<?GATW&JWOQ(<9!y94Cl0l;*q
z#?h{`GgjBI0ghig9??C{ZU8$ya;Zn4>Ku-ZcZC=QTS<Zg{PAB0`a6L@dJU@&BpL06
zE{+Zh%;NNPiJPA_64_-^4i+r-Q}`J&Sb3C}5yvtni5+bzjjO>PAnMKz>W5>YEJ%}A
z9Op7ZofYK$S%{G*qAY*W;C~*_e<piHjpwuX6x<A?=|%=*I@UovsWA*tN7R|+gjdiP
zHu3MoGSfDPAI~MIi3e4kniogw=MMGgVWEv;HHzh_8qsPtur-d0PPD^~$7>a_-$C`6
zf}uGn{6$?!G8JMx&LP{AitAMBNCuk@5(JwSWg$Hoqy7pW|8cc6uMU;I%!a{T_306u
z;#rH~8OfNe@ZzNIX%6rrL|I)8r7F1l*r4LI|4=qV2L~m}u7VJ^Xsy-*xIfz{W6$e=
z<JoSDJez9C81hK&+;#+ZMp^sX1?FUn5|iDI9HrAKM?S<)Fu5?X1^%<zw}i1`p&G6(
z@MYTbVdhwmT^5brk%mH}LmnE7J4d~YXA?!1>ea8{xm)}-u=c1)F1>yetAK8$dh3NQ
z_x!AvtiB_zmp;tQc@`v8Om)zI{V!OG_&D_31J4itFBf_2_UTG0e|rYhuN{tMeoHI^
z_uMcoEmd1*->4js>SMj|VC)^S9N7>tK#10S!0WaUD_38@x*Kd+dDD!$M%R?DgG{~5
za*(rlzgVVLQ~j|Ah(>>mbrB$@4}8SO)prq9kVFoaeX;?i-%d)u{c>hoe`>@y4f@ni
zx#)oR-u(6JjZAu`>)&&LD*N}0_@m6l^iq&C87*-vS1OtE?+&@7+6aCg)A8b|eSV|J
z7dC0T+uvZl$P@3UaYSu3@BUdjKbw0Zh!gh)Z$U-j*lI-H>O!>E@V(MvXH|BI^RhSv
zqt6QdEE3*g*whv?E_E5JFc!u|Zl)*fPjk-Pgz{5hb$uwq^7V@{i>1DzIBXUp&pC=z
zG|@GgwT^Il_`nvWT`kiV119wZcD_Kf4q6uUjaa>Fw@ed~@za@ccpG4hQsDE%eH6OG
zxlFZ+@E_<=A%&3RL_1my3%P0e2mx*XK7MkIwekA>vrf&H8r>j+d|^C_$uOVN3AMyX
zM7vOlYX-YSF3hFl0GRkjkeC72!3%${buypJXqYF>ak`srv2L(@74|7J+b|=KD?^#B
zn`(RY_0#Fh*)}MoRhp+a(iNQQsM=dmTxT(gSXd)eR~1GtP6Y>hXzCEugsW7%k?~0h
zN=l~w$_Vg?hNByVY!OLGycRw(kHu=FVCb-iCgK!h9qN$YD?vsxDo`0vMsxwsHb;rd
zq69nwZJCG*F&K@=Wxd?c!NYt%UEplfY~b2lDDDQJzGhM9PI|8+im^+b#iM(^WNTIP
z)oiQ6+>!CvU@m3G@){^sF#$ak5Lx?hKo*TJ(N#K=du$fNT?*YkdN(^^&2EtmAnu2h
zSyT&A&c|#R$hr|x+K(es4(NnRou7|dDX2byp(70UCv42JBIm=<hT?Svax7BUZ0AYK
zhB%{A&QsV(+SRVftRt*Kfx3)2cosroV(Q^pa1_<D+Ns!s+<0{$WztY7D`EHi7^xR=
zZ65>}M^_-*Hlm8Q<>$3L5Pd0NfcL54w+>E8a0Nd)HB0PKzmDMAp%y}V97^dWP)5BJ
z4CMEU=i6b#UBUde?<!A4UIJTW5wcb0w!yY7ef!*fu73JQtX7hY3k=0HurobSBLhd*
zBRS=d(p7u63We+t0E7UZUL7bt`81Bol~+xb%yK+KP~vcPgU3JscRBT@%cE#cAz%bc
zoEE-$SRb093R8kW7gUpY&MOg45Q<f(atH<n5os_IOiQbT#VUgfrWF`wwGX499p+_5
zXe~_r>+#d$ew;ERXG!o2t}X_(yXG9b3To99Hq@&;N-<86JNnz4;PXf81r1c|%+Eh8
zJUTp5tE}9@M5|La1s;p;PETg>SDre4wQ+SwB*Q95BcVe>MXcxxA>@ZKoT_A&zmN?k
zLxuop@-{Nu46c4R9y%34+rhfdcS4E9$sWn^r$Gv#;)lwq8IR_b$3hQT(v4EztsSBp
zJyURz#Ri;;CgXH{#8DWY{T9srRceXdB^dF?IYzIh9gtVd%(-2h3KT{962{+dl4P+=
zOQL0IIts7SYjSH9Z~qHEUz>L4qp1mZ)c5kG_NiG_QW<I5YbsYA*&gCN_v!^X(Apl!
z8Fx~#E>?VY?ML$_w#m9tf9Wubk8WZl<J;#jwR0DW?5`tT@v9kq>Lp9X35Z|VEE8j2
znY0e2O#9pOm4&o&oZ8^(%kP%4tAp4oaz8`${M!<7$FCIox@#NJoBsF;TD%_Ml0T}7
z|M<X!KmSisQ+ZkySZPdgCF8|&5;yG*al=UD4gQx~G0c}Ee>o?ap6X!FMXGM!Oqcjp
zZ`_@PMew+{JV__@b8`QWGv71+a3m88d1)FyAZa+<b_=iZ`#sJ;=?kx6F#dfqc*p0W
zhx8(%ST1bWnw>wnEUz>Za=x*tV-DO+t7;_W#-?c})zp<*I<Nh+)9{sMROt9FV&;p{
zcG_rkk#))bKjZTS^$kTr!+QYdsbSA#=d2rz#5~!qZyy-VUL(gjQ#iWz&>LN?hlJKX
zN~6LzI{i+ohK|m41(&bYW>Fh;;Q3n7n)VJ1uax&K0*qzyfTyz7@uR}Ucs;)b&C1X)
z^7sM3EAA{yuk<-Ty%c?HN!(j>(wx=cbx;a;f#e4AS7fROinvlkv4VOM45C`RCh?4B
zxb+drk6DsaMvC_=A<G9MVy7MwSsh{|S717rORBGWtp=vFC}(aXTd%)3N3%>0MJ4zg
z$#%T#YLWZO-|5$C@js29=hq9Q9yZPzG2`!8fj%k|2XRicV6?G0&mA5LV=j`6Dfg07
z|J0?$+T=X6C)4WqKI@Bzed_46YiC;vqDrc+ER`AVAmcH=UIzz3gA_jmq!w9pD-$@T
zspv_VXfUo(mYHUWQ=oU`X}9#@jTJYCr8HfZWLlZ<gMjjmOeuVHyA;}ETiY^Cig%e;
zU#~_#gIDq#jnkUn09`Jj>@SXl65ov|v3zF4i7QXAP%(|n3kANn75Vj37*~30bazzW
zh)#1mTu|6Ikd~)q8cwjtQJT%xoDJ<VL6>V)f!yVfU|-dU(r{73Ldq5ql&drjoPM|x
znS&;>&u@@xvp4sW&Z-%#jR40u!82aC_JWd5_q12FHMLKh1=-H#$KhK|a`d(fW2HxY
zNaDtk$*Mp19O~G2N&J{Eg^k2=__KDZ^+~EtcVvT;D`Ccae4L9_%o(OuWe}q)G!{%^
zMySircj;UfjSD=?;!9-09%bA0_daZ8<|o@C+%>Vaj1ZmweQ3H!k3;Wf)NOM;K~2@x
zKW8D-{H`dScv^*B+@7~IQ6N8>`iXgokDf~(>YYrlYtWJF2woU~fxAvMW;^N->sH0>
zzbkLnRpvauu26e&<7|`LBI5Y#j6=I~9Wll(JQh@^M)UsD#18N3n#kHmu#of8*p!d+
zsST(ew$1hM+1|VoZY^##b+<P*lhZmqBZ=Q4hdig74vkLOSYA72<=QLq#2SyMM(RPM
ziDau>>>|An$v>hj&%v2xd)x0NPa{7^yL>2~8f5;*Q$0ALq-fq6IeL`-luw#i*Fo$g
zbO~Ka*$FvRa(aO}4Rfe^O-1}*7J4jl4ZNy(%16Y~lfWleq!mzg&_X8ylDl7;LqK?`
z_X$2Jbu|!Wyk@Wk1Ewlx1CT-c0E4zy-#!EVZQ!V-*6amJ4aFLX9Q{v~@-vW{Vd0#n
zk`*-4SgfRYNII!_UPUVQX+s7wLh$eguCpNudk(&B>G;%{fiY(Lqny8W&j2&+yG|kG
z3nUByOFUN3J_PMYPVwD3c7QeJaUfA9b%va5J|H!gQJr>8amIRjEnRHyEP_?gc(>x=
zMp6@yoM)to>;hmXR<L$561k5grnKyUe5Mup15&)X#$$PF$SkiVI;FJ6!?G3MXWEoq
z>A50&g|*ENyrx%pd&UJFg95&W+KRuj*jlaE0p~CboTypUo{dM8y*FwApomT_-GGb}
z9mir5SST2^`do;TmmL*UVBV_P=MbT`LTB_F|4umjZdGJ^fwSQe5Xmi-SWsJ`xcHI8
zmajKbP2QR=MAK0$S8;G@NNu0i0TYu}wu}urx!1E#BM%6ny&F%?YDU$_q2?yfZcbac
z{1-434rnI(qWFhOIi#?5jBxKlhJx~mOY359*-Brh8$dR@nHrGiG-_*>-FD%;#yR>O
zKQZzAdC3EnbK+?1>(PyW;pdV8<pXMK<V(Z!Ts?BO>C!k!A09a}tC6Tr#qz81>kLM=
zgabb+Rf!XnoSVP5J;Z*fl7tk7U&%Wi+?V&IIw!UELx)jYr^n9=YOCAwd=LGN7FA(T
zTOm#hwN=J{SNB%Q*uXxYq|J?4cHf3H{{2=WH~bC$8g%43D-G0EJ8>P=f!UqJKliQ4
zyv|gv_oOYiKx}?LGJf&A#1H?iY`wl!`Urk9cYu=zC|7=dgeyG`h4xkb`x=^;re^+G
zsL~i<@cr^o?z<9X7PWOEV4=3k<8M;dwd{e@W8;UDWaHxI`F-^vSBrjrGEb`UINbfJ
zVN>&+v-2jJlAUhr(!ee#my6RRx<S?d3F&-oF!b*v`bK0m#!NCTKDvTRo)L;;wwHvu
zWwZvuZKYOF!u}VPEft?G;Dw2E?d&QjZR3I~3z>MUZ8gW7)&{B0L&_ldbgq~s)&7y3
zdp)8`eJmb_vl#8v)Y<`j9>b_MMWt~hM-8t$RzzEu)^_LD_@>x`Dyrplh7=W}<Z>KG
zrLFTd`7H?dptiPT{}wR|kLTgdE&BADdMqwq>8~cOV9+?58ti&H3`EOA$<AP&I?d|F
zrS*{(AJUi$>-uR5y1swFU*m@3`%03HG*IfNZpRVx>j^x=37(pd2(H+H!&twuP7u-t
zt5U*x?~ojP!!y(VvenI#0~CX?DA3;!@Ph#-KCw7>c)SudY#v*;_|QEb_F7iPFxNpT
z&}frEWv)A&bH+QW+FY;EnQa9lry@(q6nv{p={~rNm~9Qnbb&Qlm9&;HMW76qg*wI$
z0C~2EwzG#-*WFJ3_<0fMbp-$rP<*iVvq2wYK$q=4!RW4My#YJtsNK4N*YLArFV$JL
ztKMX0qw%8Nd!>ov#nSkj!ie4nBgXclFx0@tIyOH}H{F07icFS{$fU5yOgX)jTM%+h
zc{T7wz!mNsYJ#SYJ~9)Jr+-bF>5Hq{T6gbZ#l~t$^ojo>><DV>VtMEfKXGYIuY~N4
zD0Xwj%ivBo|I~YJ%^kTt)`s$`AE~B~KE06}9Cl4}vQM04d!mt0)i(b(HZgw^S;`(I
z%c1wha_mkqv&2bMz^ux<Hl5wzT;6x+0oDc&UsX=N)S445PcQtdAG61|OHI|*<O73~
z-BMZe;niGRbhh;xoo(InOpl-Z%0o!WpAT1cwp9+iwG^1QY1B#mg;_uUL@d#nmwVS3
zfy9O+uli?d$}<PVHJ-*<-kr$VNR`{q*p@C59_caHr1pfEyIY*&a`ZJ7Id|U$A>K0=
zNu*_B_TY%v=?~c+6YB%C<17$taO48ZUb;hr-if_GrFTLVh}t?d`wC*}Fwum3x^jMe
zh|bbgL)D*8n$d>>yJ=8iBolHN@6oR8BrWW_onf}s^u9>Ap_z=6_TG&by)Ao%47vB`
zRrqn{)XCn-#ir^G9l^Q|LD{473J{bLt=Bq2BHl52uv-UURTN<s2a4$9VEuk-$+0rk
zYRW&yFU=JxS)IvMWTx^k%8^*FZigdyw^bk9tAJ*sN--sYDEahomg5#F;8;1+mxuMI
zS;;>eE(p@4BvZ0?gGnRSQh~;k7)j(b4sPw|HaxB5h)L=2a-M+t!3=4nG@^;4;#D_i
zBASK{K<I>btUkR%m1DYKtJN4qS9*9s9jdl^Uc;)r&tb;p)1S*XpY%kKmQgexaIxB8
z!La9Yj#ibqF{!X_Ka4lvOT%~2sS48Krx0p~C3e!G%|$+ht!j8m!?G$yaazXoDx}G<
zXY7zUW35HjA*aB2?}UJD2$_OD^w^f=*_Zs_!61U6MpvxB^&&=ai-je_OFdtwo+pIo
zSSK@8;mzi^XhBf6QlvbO1>QjC<_EF2SE*v{S5V44oXgtuQg3OA+^bN<E5g}cqB_#(
zc9}@Nu~7vwK;TYmGfi(j{nNq^Qva-7!M9_2>2*560%M*9*tTWWr`M2@izKNywYDL2
z4x)cyHEHWDY<9h6xiqyg`tC_#Prt$#4P~AyA)RiS=?)$gW?NhF&fk!q8vH=nyBD^H
z4sT4r_1URW?W4OZl6;5bDm5`JI-hx1qNX~W8sFezj2hh@e>uZZ8p)D>yId&3Nx@Ty
z?7j_BE>~%#L2(6INa0`4HNJc{z4L!*dl#X7`cMK*F4EYk{&?*nJ)*D+_<{*@)jLzU
z@wXSG@&8>GqP%%4M=enw`ts}I^M@~m3&%-K6Fl;+G;)g5_zDw5+h3vU)e62S*L#|6
z^{7=K+BqUb_rFrigr+W@+Cq~3&%MmgYKo%`?fmsUI4Cft`$AQJ^!}H6AV?h?2<qfF
zkds3YRX(Kjr9)IBm9Zp}9kDn&#M+iyf<N4xDlC5dbSrw>#))vbsK|AOIwQ%&Y_J{D
zbD&K-b@3wa$RlsC&UH?vuR@KZVvAbv>ctdal?=3D&M>L!_MoyVUsL|(5YZ+qYE|$+
zQ?(l11+|F^L17wk*51tuu-F?abREHkdABIl0-)t*I<MbDfym&jj#Rbs^3^e&{t47G
znr;5Ma}cN-7@fe*d!g`Ri5<G-e;YastR3VSma1LSG`z9x(&D+9Os1B5&YF-b*<RQI
z4n>31rNO~?VR3Q`M*vD>NP?M#0iA{FcTjQ%*<lnHYYjQ*1_y}%4K<cZj>>nNY3-;U
zi(SES8B^>``7*~wNlUyJM<Kj3Ft&wS8flhR{~hn!PQ)9x6gic3zAh1luF{S`85q_Z
z1eWHg)@qSZ$e&(FC3KE+UraolI%@etU2UGIcOFk|t3owY^-kyka4>2ZB=l`$#uCjj
z$%gh)(t1d$9c>Lik3-$YK<fRgSZXv=V#u!>L`{xBs-#yR2XS^onlgK`R2C9HSWX)M
zWVw8S&@69Hz3j7+Z`XOB0rgiBFV9Y|C>BQs>1TBV#h8t4ePKUkqV5_}D={8ffIB6X
zLqnC>=mYe$+n)XV98905KU1R<{ODmP@B8M~q|%KTPP|-vylmxz2Sxt$3tZLr?G0MR
zwv@)#XGV7Z!6tEMe0d~ti?0j9lh*!=L_Yd;EA?H-aP*oqz2sZkjRG{1efo;<RQIaj
z<S}XNyJJ494B2uOv2+JZ8p~=52UJDAnu*@AH&w9pIUqSR`|_P<F=}hH`@1C;+I9gC
zF`IXZ_*)?8pYN2&9x8|W^xNr3bfD>P__%qkMDMbas@m#zvd-wpo8ZE>Icc;Kh|W=2
zBV*2q`#ilH6|JsW>Kl2_8geglbM>;5^R0~KYHO&!qgQzrveq{E;rrjWKF9>2#BGhj
zNV`F8750vXE(x~IptbAp9}d6X_z%_V@?e++FE?ut{~kIo6Y;!ubz{_4E2C@|Sj-$s
zQ0WkfZfKdslHnd3YUO=8vYSKqs$Xb7*$h&Zg`4DhOM1&{E3<V~Qww)l&NvoDu7iaH
zOkk?OBw<z#W^@DRDGl1;8K}UGQFzIpa#8!B9x>F^f*0QCPDvd{jF&{*9%dQ-NL=X0
zQiI}|LkMp>PX0u&y(K8JmX&W!b(lN_ubpffZ>u9r=H#*a%GdL?N>K~VlpvGp(G^UI
zNmh94l!H!Jp(QdA{)_d#N?NNdMQTAbOtudDz&V{@Wwf4%Hui}H&+!wlMmNy1$DeaV
zkK=(HU4=7^WSW=ITdZW9)_WbGfLA)GfU!<2e+2vL#*ob=!os>`NM!;xdPp9;30kHv
z!%8qUPkbyy$rm>ivBB*P8aWzyxKK!N?vR+J7A%%f{t}+QT8`J(rq!>fu~cx&tjIl1
zX4aK;)VKb#?a*piqF-JdMVJ(z?TJF8#BOuKZx1*t4ZG5@nmr_~@5xz*-jij)LbHez
zr^@CQzx)NT^f_1t`6Je*O^SSVBfFlulcO3f(%G@^U+~c_NZ{pxyxw03@Ag1dKZBtY
z+9;NJVp}JqTxCCOkT7=#?clTVyaw42zMrv>UaE=Y(=MtLW6Ie|gEk%TV&5?$QT><2
zWy8+NgDijxxrESuG`zq;sOj#{P+K{YX|z_~F3e?i2YY-{{I{6@3}^71owsuFO_NlD
z8)Mnd>g=&E#F0C=F|UXZe_rCOx}g%ykaYc;t)p`I*-1N#Bi7vPb%vvsy5}mDL-f``
z9In=9#pMyAfnV~{c#0IR-z0Yq?&~3$HIAZ<T;R(hHCs56=@~8lJ;25Pa=XkOjTyiA
zLwmE`Y(k_xXB(;g4&x3xVb*gO!mi`SDi`Dki+hj!J4!+0E1XgB>0RS;=-*SE2npFX
zzg+Gu+p(swSEww}sLhpPO@Xp0wN}iQ+H+!g<UMIG<wN7GZQyLAFx%Qtk<&%OJ&?uI
zx;eQ?mC%hQLE*K;qce?OdB-e^g*g_aer}63E$R&%*u*@7or}eflgl9*NB5Id6AGHG
z-^Gf=9<r6zk&P1^7+*!oo2nGkz6W5vi-}GBR2tVSbDuspU0&L4GAe0{j);s{E&UxK
zl1wXa@J6e0z}Y2a=L%t`OOr$U=@>esym<IwsY3}=+#Iac)Z(^t)o18BPiu;#;T6rQ
z0eCN&Cj}eRM6a)nfFe5cy##e6Ceof}Pr%r&Q^fL8=TlGZv0=bT{jJ1Kp8*_Z9cD23
zQq%c0N%L*aHiXi_8o{qCM2)<ki}E@T8w2S3S77yZBVuM?db=cbO>B)L1bV6{AW%(R
zv)u*K_%!(9m8!5&W|z^agY!}{o%=195QYl~GXo{eF|is<wVY!G^Qsm0lUvgmf2*79
zC`Tki<xN3ZhCNs<dwr6jmFX^r_nXaD_+lkRkXzHk=R3tInzeXgIYMY3DHb6-q}C3z
z%7uu^x2E1^%B)x<j7LpICfcYSpGoQnC+pL6%y|h|uQQIrDd*QgDe$ml`QE0>as2m>
zM!6_;qs>iBbRGxE4V11PJsJvxW%~t1gJ0uy<Kp*6oYho_YxG*HyO$%0*^<X>tCk_y
zxHza5;C?eQSy*$ARZVYADpObbx5oB_^7q0lQB+4tBfo0oehHvnW0A0)BphY&t0OsF
z?`0Al>ex%D3O_g&`-OK}3Afr%sSe*fCpNt+mM<_8aqzlW>feX0%C6eCqSzZ+-kIM#
zjTZSe^pl%nvg1gvR;c!iCJj|=H@Y|6hD5ejW#%6~Jlk+Nc978D`PU7xl+JhZxji<j
zbW3K<hle5eaFVc5wRQh@nM2d|vNJeIf4kzc-<%MC9aUlL+B*XN+%^iv5lYEpdt!NV
zr<m$d#78CQsp}@F6R3l0U!tD=^w5+$^ovNk#!{|pz3h9bKbsGZNB)!;p|3?@F1MY+
z?!}Qfi}YmU+pPNaHMB`-jzi)Gjh~*>>$;O9mDX9&f;_!PcDd{8BAXFKVr3tIJ7X})
zBZBn{tf*qE5I5%O0f*fF4#Yz#lXqvi5Y#rZwx#p)YJz#sIC05*)K-e|^S{XLyicA^
z(RgF~qdF(FmP4-#vZP;F))lx5kf#{6?flg);@}42?9pB`s-h3*sElO~!*DE5w}lXl
zIetbQQ{R&;&3AQiJXb)ED;mN|VU_DNn$IOYq>+iY6QQ|Ab>&O?9c-Hb)TM#PM(%BU
z_3(_KuM#=*fGwq>5)ui#b8y__7a%<8APq=*kgR6&inj>VheznUL*8cGJwumZK{R6^
zJW4H@850v_FG)Dy^r2CLE(o1C9S<17#-lUrBsk$`sc&Uc9XtWAhEmz8#qb!WU+f~f
z#1XY;Q@5Qaj+``Dqon*iKZ%_SPqnWKdA2T3U0aNLo~@KksA=+XE9~n4iQz+J^^g@t
z3Ut9kci2MzhVdxXTU&}<P;!|`_}LI}fI)um(Sk_#V&&i&3@3!;4Kf`X$rYT{2pxfJ
zbrr^_7h~moZ8)sr*Li=h8#qQYkI$U?^*v<9pCX&&HWp+aFZq&Z&s;ZHM8pPcDrZ7i
z><sriHA#U0Ra8|sUF0X5eJcCWX0xcJ;|Fx4HbVIQl%y=Oj10RX5&_*|k<=A&lyn*f
z%SJz_u@1{Y0y0rf6OgLkI{e@iaL|;0ogmjCpG@mhtrG#OhLT*R-tiNra*!}M5*%uP
zz3ihNA%;fk44N&V*=naKQ%8|)L+x6iG{Es&hnx%0q@lFfp3}c0SzOLN78rx(6_swR
z^6}&ln5w)S&9gWGOZ@}PF4@{XFMft>6|1TtR*j;GUp?;}sn1NO-#dosR1k)k<gVlB
zO5ZvHWA(xY#Y}BrZJ=z78|RX|8mEpaer@r}eL_62d>rX~9I4GJVi%~FW=LJTUm(``
z`4J)`_?owK7*T9H6fY3^18mOE@UbqKnbV=#?f^LhBSWLe?&0we#bJ6SdQ+Wl1&OUo
z#$*IUk=BjG<+&1EJhIZcs+|!qvL%NV@qLbM(wgjW-W&+;6^vDr>9YVt!1#hpT|Zs%
z8gyz$TFjf|WQ^gq5<P%2U>Sm9i?C6JGW0jjGXziM7<9)k%55FZ21_73$H!|nOOWRm
zHtfYtYlYHM(7J_XFH=xqtF^t*BJ$_ivBydanLN)Pb~l<-HP(I)y<>W(T&OKSqTM1c
zKM%0iQv}-lmaW*Hy@ud6)XQ;EFxoyRe=-3SM>5BX<Aa0CtUbywm%GDB>lexT$=MT1
z)5+6W`@T*;Q3<X`a`+Eyi1YyGu8?uup!@dMs8PRv>YSN8%PTEw-$3ylVPVwp+o$Lp
zQLWCREon&hY!nY%{L>RsQZ~=*tIL(|+fZbShrfToi^b9n{Ptn4RJSr>j~Z7iicC0N
z^<HusxJ8U*Pmk}GOdo{XeI}9F&5-}S3;?mO@an1VUmd%fC<*`1ee_)JofUsHmz;!w
z{;WzB_=z89gT^B4VsoWvSnZ3j;N{#Px`4yq^W)m<rdA#~qv-B@ZYUXBmcG^V&z^mo
z$d|X0?GvO^;GOBXq~$OLh8ZY-@wY~7;oskneJCCoyzpmGYaSJ7)E!b?pIAHgD&x$E
zF+(?n7^8k+l4PQxnjLTi<9RR_C@+5}vCL%wO>FiP1iMl!3vuovkI<$UvRC+={1JVB
zz{-IOTv;9rRk#h2Mq6P{C||)iPI+60f&whX6z3t;+>#J<p^Z{6#qd@U1CepKyk>QH
zI33Q1n*sc+Gg364kvK&U14MZ!I#5je*cC`@%YBh7IL%x;M+%k;T%GFM%pc*zx(>_z
zRu3_BF2*S{y23E)DL|Slco9wE@KVze<!P+L5xk37^QQC%2B5iykUnU6AyC#YLo%~$
z?`X5N5bTO4Y^A*5<&>dVT(1dr%w<gk!VDm-1TGYu>hNKS&6GPjZU@^~*BQX)EDVp)
z3dHxh3PYePSr$GiYw3=WSyl5$QGlrXe-OxGx@L@DG>J4vS~Rk><|OQN*nbD=vS&n?
z%eDI(?26B4gvsfUz;Jzq=Si(r`Qri;ThxW=FE3#waLvNMK<8ZN31KPT4u%rPg;TaH
zO|PcFm}3r<jc&y$Ba)UC31>|2S4RO_xx4lT^t7VIt*?P~V&VJ!8BY9vW8$>2Bc1Mn
zA}v$jfYe-$q<n@R=y8EVz=BQ6acN5AJe12XTYTtX13ub&krlZ;+A>hT&Zn}MyQ}n2
z%k2CR49|Zw34P?kx%$HnsbG4ED`Vb@wTkHvl_^PEd7n$@!R_s7E=c38X>j^=Xa-lN
zU*G6ZNSs*p=>l_i@8g=P+Y+h0f$hQ{%zH1j-!tM5ptinC6_}e;Z#pMm%;0uW+rHr<
z7BKDH6sKd~QQ@K^{Dm`xAz>K9;UbT9$uR``I!v3loYW>}zIE3}g6G&b67g)miP`UG
z?B~xlc^T^^y|s&j+A8VnX4=79>BpkBy6)fV?aYx<;=cDLFZIW~_~$l^Yoswwefg3$
zmjio8<g<7Cc!5%q?Lk|$e=w=@X|+&=$~~8-#vY}@H$<ZTv{!y^n>eRQbOxUZoZR#l
z*2g@kG8^7C8U9Yn{Wqt@a_t#3*x#M)oJPNd?h~f8OVSeEHg^;{pP+c0lnOqYeTw}{
z{*1Xt>>cQvgNY4zsZ&ZPQb)V-cj1NFYFcL^OoJ*y?S|Cvf}=a8LKHP3Ra<-M=3MG+
z#CUSKGGOmbYjg$_()2RVU{@^F`tL-}TyE%u_dP%nCF!VD$zcsk6g<>(b%+GMNJWQ?
z5Y5ytVLFF3LR_3xVbUb&nAUK})Y6gt>K#s8)8IC++No__^$ABy{DC+>rAXAr3KSux
zZWzrl;uhK^ClBgh(<?c1VtDqXh82NbsNp;aUIjFv3+hl#Mf)s3N|!}qmbC=X(Sb;g
ziKSNd>a!_1Om2;BvYP`+{fXk~w2kcuE_Cl2PD|4a1qVw2Z@d=F^hR~D*KaoX_OoG&
zkB8U}ri8(RuH+4ym(U?V3_^$Y>5FxTEJTaKeSpKHX!GG-&4R?WlGS;4?qOD+L>l=Z
zf;tph!R%;IbYd^0p#u;hK@I{BYAY(VqlAT7-dZINYc_E8D-<kre7{;ltr%0Uc7{UC
zz#eHtG8RsJ$zvos!x~b-ZI@HQ*W*%->TrR$3|AWuYtEx!S=|WP+WdSG;=14tiA-a4
zYSXqMl%dsA>5q`c@@LX*$#-ikd#!G}MT7ndQhugXZXZD^F_+vN(~}R;Tj&x4x!S5W
zN$WGd#pq&1<byP%50`B44o1dit6sp!PlOh=dP-hSLSY;@RBlO~ga7S3S78mxRA6;4
z$*o}=r{AVTt^cQ%&ZAj%cLplMgO^jy{^O;_)ZSoh{AYs`RiYeVpvY&#My~p&R2qMC
z9%}1bb2)Ty;f5XiiTG<5$lRx2(2nv)UC35z3E$A2Gu;4`**g4GRIA9aPh;=?Mq)Da
zid5zq+-N*>2WlE6tIy$F{eEU!9kZ?B6xVt;f_MtSRf|;B-$Nt%-0v7^UY;{$tRXv(
zjE%D$gT4N>uS9V^+xlv_@bOY&uZHT!svE>T@_FMbE7VqTts!ajkZt<7yEAo<{}$|=
zmG+Jjf5F~Z7X2I3N_1v9N&k_Mb;v1@p*S$xs%op2|E@5~aG_;q+{9~V-#lp|*c%w@
zV=-G`x~FID{(~=OTQ`fJ+a(M+{j$yC`%7`s+C&CB+)^&Fe0O2V(aFO6Qk*8oe>4*7
zCvVEj5-iSG`}VA{cJFxz@Fiwl$D#VACIbSA0!LLAy8@M*F6vyc4oL*NsPr0+)HJ?R
z&yX}-)l_$Nh}S4&!(g#A^bWeESfEmvdSM31T+w2)#>^(R1Z)ZKtWlj<k{DqTzyN-e
znqI%dR8D|GMv*q<N@sAiYQtV}xDXq={(K&d0R!Kj4R<;c5jpB~$9Ad-sX=~bzA=D!
zz>gzZ%iszoE&IIK=CoW8-Rhu;T8il2$b-YfK5D3MQqqUx*WZAgsW$%uf(2h^+$B08
zBE$D0KFAL;rQ4@+a3wp>O&a52v8TOJ(n%>fYUL$xs`c~$F^O{ost46ohea$FrVn_H
zOnENprR>Q&aTzPVeF#QLWB72TN^bxM9GG+bu#Syt?0g1C8P%{ZU(Uiqp$xYAd*nFe
z5sWGsYP<qmJl<7XCa(r*T|<=nPGj|W3yUTk%lZCVI`V3t)mIwv7Hc1aipZge{>LXJ
zD(hNXz(bnOP)O)$%(lkS-wo+(Yd(YheK>Z^ikH#4$P=2#=6DFRF}C-j))uK4ivwVh
za8w%%qfNvBSR`yi=E1d!q1iUJq+46RB=@02iIvSsh`s=Kzj+>^7U$k#7;}|G`ofz6
z?jDZp<l|?uWZ@ZD+T&M82SJSE+v4=nmzlWy!Tmv64}X6!n)}*S@%{1l#5Lq~I@_8H
zl+L!=FW2CNGEWx?yMr&6Fu2d`oGud9d4sM{o~sQ+@`>+7wMBn=WYNl$tyg<ecwuuz
zh7UVwykoX&GW~#H^&>f~H5^iU)e{%W)lPjnf{)zb$DI7qHC{gViL#qRZH2z+*z|PO
zIV#h+v*L8i)1|OTm`;@FBH^sMa~pF#dxvdy&#hJ(&%t2ju~wb#$_)}*EM34H8D!P*
zgY>OWeTD^cvjbY&44k>QY`?A@=_|)1Io`UWs7$(~wYG!v3q5Pvu%UeVXCaT$suN^z
z!!N|X+I*S0z`xl~4;5-_>j|PAi~ghd`=lkcaaCKLrquF(JIQ0~Xe^&+N0q1EmVduI
z5!W&gC%Ry<Gh}QDG4q}~>#C29vPjvZ2~TO1)Fm{uJ4Ec^Irl)fx9^<ES_*}t2|J6e
z%2m#Xj$da(Z)Y3<O=i&<V=q7u5vMjak}zo(q*1*n23pB#`T;mkpE<j^wv(rGD;y`c
z+AwXS++T2i&iEjysg_D9bQ<Ay)-t&T&1oHS3Z%L!)AFO!dT&>$(Ky<<+JXL(luRJ%
zh{rRPrj^)Fk`%L{rs0tMLL|##VpUtqV@NKl4=7p4aY?q?6MLkyDp=*>93zm-@KJQy
z(|$&_RCST50`CQD*CFgOjSwUy_We;W1aYb;dSh#HzZL{x4XM&Q2U2LM?OZjCl$<`5
z3v{YdSe}Ee@I0XaE%CR&ILU+V^8ns8epO=ywN;a4YQ0AOUf)MoANsgT`RR9{ctZux
zjmWHwu)R_PM6G5uGOg*!Dn4bj<>&YTwQ;9M#rojDfcs1K;5XS0S@mf{dLfwD$#_fa
z2Y~Jx-7=e6v{srDEiCzaX<$FX@D{1ZwNqV7ev4Z5A=6@!u=8Chfu5T*FJahl)H+#I
zev}d50G9b$y>*!-5cHNxvI_<%SZagDlv8WYi(qRTX=6v;`DuHc^ck6?*4QE5-e4x>
zD=$y&u}~wRcw0?#daL{h1D}UY)x;-_-#4Cr#h0>xG?I^8#u2gKP0jtfNVwJQ`=iJ;
zFS~O=-h91G?l_JbQ#!?1B0*bSW*oXkwsO=&@g0mssPtTQ=AGOg`IB7D0LLvpiNjY#
zHZZwKq&fBI2&5HegYTr0tz|~+)vs@Agps4s)lGwjh8it59cNf#XUBB<B5>m2D`esh
zh%)@4Qs%O^X<O9=;D%F_XGZC$JTHx<y{)&RYb?^<mCl*YcR+&_#(^fVq#qnh7d)1D
z`tQ70Rv^_XyK=5KUcRZ?OSW<2Gu!h^I1YY{zSF)@M@f=uR{7fE3-sOI{8OA;{_KE%
z(E$XY^dFdgaxA&|qqfw1pJTTMEb9giiBpKO9Zv5wS~`Lh#WxM7M%y37Qv(X{;rZ+J
zypt5yH|PQ2fE^DH?t?S4g>Cf**&dKXcS%^5v-lMo4P9rp=&Lv_8{gf`u9K~nJ3GAh
zt0&TDA^BWOrZg&;)`0+NqX<mIV$*q2ZOyjvgI)0qon99Sl2pb=L4{ST-l{qrKV6oX
zgH{c7=51%X&$<{DXzS^*lbg3bmvj~%d#nL;x*@A4E+1kkJp1#3$^bRS@4rawV=%?J
zUdVvtNIE2A3zMt~^~G3(SF)?i>R#p*rNciYpj;&5gposr5!lLh#_)8pFIYs#>Huy6
z2OUXpheO;%--!cu>Zgs|tya|IUQ!CN*02EsDELYb<x@fJK<W-3ZMm2Twz)j!GGeA4
zM7AWPPnF$Ln84YO-Khr>D~$$o1nR&T(I?2x6*1Jc3N*N{fgo!!yuL0j#NSaYw`BMM
zAv1jjSN|I3A<M@XI{xSc#F9a}Je|R^f+FWaG#|M4BJ|heUVM?CI=!3H4CeX8VR?gk
z=HT0w?oX$CM2PMO^Z>P$vdLy2YGmo&lkc9%zikYU3V#UBAYLhIYdnEk*c}op6E5a3
z=x>{Mn?<f+lwVbuVaS1H^?n0le2MYu9`dI+eM*p?))6fY3iH;6XL?2wn&0xV4eg-d
ze{zFtHNKVKeL$xWrX|}XlZvWa+82#W{eyW<+`QHAV3}=|`p{OxE%)h>`Pv2@tLXwG
zOy7K9Ln8m@PISlPG_E?SikPPd;dRDxZ#J1$ta?@cb1qFz>&j1^O%-hLUHF2u>Kc3}
z^K)8Z&wrCkBGscK7@3(<gkQf5-X1mHUH|#8^S$nk_<ugr$RnTUT00PCJ0`RC1MM^f
zI&Q39jj2a6g}XJn(-#c)Bb#>0X>a9N>1U`8bp(P0*d1#fmN+^`jIzt~3zAAE&hI=s
zlE<nWBDwQ&nX-iVcb{YAOlQK{WaW2fVA8-T2K%eyvFD<+IlUpY)eBjr;ug30$!pGH
z_V?NGd;q$0T5CG=zoLMYZlM;_+19W~_;~l83lxDfj3bm<r(?T>5%>J$r4+R_)V9Vm
zC$5BRv#K60Z5-X;xWTC86Mq&Kh0jqOY$H9Rx3$S3Nn$kyWV-UKHSrU=tXZ2`ay!gd
z)Gtk}zhNm?4eWQYN&pXSf&i$a6L?nZno${}xdV`1Ra9tK)urnV^HwmpmW;9<gjkmG
ztjdIo%Ch!~9fq%C(Q~A`f(OGf%WpxR!{Nx)k$~TeAS>4gMY46aLI{BK=_F3PvJ~m<
z1<V+7IDw=Q+1ap)iD*7B3tzMjI;$%nQ`Xni0}a_^ISX`MC~-_J^2!l7)D40zoF7+0
z?UHhZ1~I&5J3Zi$VqB!8rDYvTnbJUs%83D?{Hwb&I7Ro=f6&ziT23rQ$Wp7LPJ})L
zjdO5t0f@Zv0dT>@&~)lt<LlMZ72KRo3WwrhtfhMvVmZ`SiCo0x4pU99?_*upq}DjX
z(fs@TJkL0`O6Z&g-M-s`n*%a;0yvjDQ|iM4SPNm{G^EdAS)kNMdEE{v5LS8Y(4&iU
z>?9(ZEAT9vwRFEVohlup^o4i-K4#KrU|@Upev1A><xGy9#<7D+=FX6!prnbt-A<Jc
z>uru<3#*mm<5H>~Zp94pSLH3`qE6PN8k=L+dfcg%@xPJTU>T4z()+{@Pp0+P$$l67
zIvP&gDfW=uAkIAba<Q!o6`Lv{S&-Idv3}RpR3L*BCagy9n9`aK9H57BgGaY{-L-yb
z?7Q5JIk#aU)Nx%t+bvwfg;7uZAr0))uxK`%1MR|D#P1(~(p)N8+czTHwScI2HI9^w
z`_#*@;uAgfu8PW;i?6)Zru9XpXkXZD{Zfs+dfqO(;aA0f;*glnW+t|$UNEWYa~59W
z-R9__=?hq1^_7bHt)507guD~#+J{TtqPC8y+B);td7S*v!<RP}OER$K92SW^Pvu(d
zZJqgrB+ITEFcPJ$AgNp&ns3u-Jan$e>BCO^?qTDv`d?I)uvKQarNe_ypth1)&~v-w
z9P5!$L2V7%@{gB;a+7@6nkWAL)Hp()mEGT>sP^&&U9$Q&9z0aqm)bIFYuMWw{WljV
z-u<JFgYwXZsVGdUvPf7VyBk@I<91gDpG8>AW5`8jK1$gB&&*De*6#??<fu#COi)UW
zQwoUN4fLdAM1O#a_Yy3p*}%VJzeQvEJ*r=O`i%ECSP@6yI_U6tAP`T_8l-L%$*W7)
zP*+>-3URE`xj4B8k5;>gIK4}7NQP$v)-I`qy*GIjHlx-VqPJ*1-N4g1i>4_WwB>&3
zH64qXNcaj~+t0IY&LQ|c6p?P3{o4+2(G&(E`=A#1I81?b{ib2B6PvNU8Uj)nbRtE(
zH1da)d9|DXPF)-clcP?Buq~`zY?+#vSnLVKBZR)hVD_AuxYTLWNnH#Zuh1f;rI4p1
z_pnsBYpHxm!fVbW3I&^Km$Gr~kF#yds!#UwGe4_%)?>8g%wdOf3p&c6^gaPRXsL|B
z7s#(y_5ukH&jNi_b7hAb9f1<mR$F~8j%Jbw4bjPoYym4pRGKXF2&rT5TWDGct58#d
zBX?Tty8<ZgM7&%?&SW~Z0k33Sjg^p^s;*p+F#RoaOKb-%=drUZ(O0!MLPk+B@fJ#z
zzDohR7G@owKs}#r9b)a*QHgbko?R9_z@z6)yT@*q3A2d69Jd<7%Nt;lD?2u{y+rlh
z!ij0h>H4j6e(qJxoa-4!(=y7~8uh0y%e;E624#l|!y@5`3vlR<g;Lm(zjb&<PW;2j
z@Mt-Ts4e;$T&jCpohfnfjj9YE$u^i)4-_daOduCeS7NKPt@6RJ-6L)OBd6juUPDz`
z%U7<6Vc&#`*D-S%_qP7zwD_x0k{7;I2-shq#T<?=&7lV|PTT`zH*6jk776QYtEv9(
z?rGu-rHduw|0fw-bwOPk&)#v8hP{WR*Az;c9{BD?Bb8r~xcY90y;v$J-sLMD;X}Jl
zr;G9pn#bB313I&<&c%CZU(aNbFkW80;lC`3N#v|SoBQ1OpTt;v;X0|@O6wSH({59D
zaEhYZX|A?z4V7;4MCE}+`ISW8{8by)CU;L~ZDX)HFc!}3HvjS0WF)&ztJ5FkgY9|F
za@kl}cK<sU;+-v1)UH<K(!kXfX}J-Odpe`wTn!#CgKnuU-Hu|r?A6(Z+A6BH4xQFs
zcSzq$o9()`xIf~xuJ32?e;+7NnN@N_RogphiGVoTI7U9(B-F%6MJHp%;Nl9PE{5_!
zZiz(L2`tow;Ec|%Wc7-;FSZ7*Iq{YPRDf5%3Jy)ePq)4M`WZR>{P{|W<pr=80xgkC
z16Bt+1pd6TsMuI~ANP9N*tf*4jHINV;s`ZL!F=GHdra~h$H)y%FlOjt@6_HER3ycz
znw`JnsW;+Ypnz#oJ4tLrjK#VRVHLi#ln}a5xC-^Vvh^X5Q+i2W5bpsx(=Ds<^Oz(+
z0HCC{YSC8nW;o)sx7$+IDtmPH3?Hs=z(J%3cyxw`2)2}>FrZPLbYYi(rZ7$bGsWT^
zmROB-D5q5>(PlZZn?;$Cb3IUGhTR$9)giHuz%P_Y2ctyYHGcGf8H9qTwnX1ommD4O
zRJJ#QU`sAh?!XXXR5%$zT~^+91F}`bI&2Kt7IB=$8^R0)O7mX_MsWRU9It*{GSyi(
zt=tW@8g)Fq<!#=f>B2qi92~4n;sip=k?mL-@Q#2KewR7l8**<%%=T-2eLk#jD8Dy=
z$EYEZ8WG&;0sN_q?SpriBz!p&(h59u#wowq)=D|?Q45rH_+cnO9g3vHR>Wy^?bjCL
zhhF)sQe^op1vqsm3sjzR8CA<N5JShfx`0;QIbuUCC4MUJo`0?9H3ciYfCj9Cju#xT
z&_UbQVI8LJ2F8m_faF#n+7<Q{z2lX>O8yhwIbX8isT}G8KF1GO*cEIrF_w1Qo!AF&
z2lvs_Pf}M(L&Zx4p~}xquAtm%q+s2NiU^p_=X5O;BNbT!@?KEDVJ1N(N~=kemltJh
z;X?}zGc0PeFdC=<9YM1V-7gw#Em2_`kj6kn^XM@S0{R>>cB4jdpf+b<!4a*-obN8J
zp)K^<AezXtavY0BGB$!^oL4}VtQDc>w<Ms^^~#6*JQnqDgGSuIRaR|x$0y~+W?-aw
zcXzr#)}6V7BrjuA;-+A@u|-J#K79Mrbvg}-DV=)(mUzQS%7I4kAx1+@O~pdu+@?>{
zLNf*RQmc*<VIe1t96HTBrY+^GC$L~?&K1SZ-_>i`VdNj(#;NZ*h_uSp$U%tsbElUR
z-K~+cq$6nx(b}9?dE!D?ba{?_h~oy`9V8ZyuZaGU4M^^c75^&b!ZG3=-nfv5-(sxP
z=-;Mi_+GLV;Sg1ZAIx0Uoi)l?0uEOyU;pXE*wf(X)8i8FMcK;BCt-aH?$FE6lIg*l
zWBFQZKv?4CZ4b0ahG0;=d6#inlR^IYHk=~vwo{|%hKso#a&}I<`ltYgTkcCUaQ2Il
z3{PK#&(o7WNNRGcwc(JN$NyNdyF$VsKYG%GQIg$<e)QZsG=1y7$LhA|{ZU$bhHMX=
zJ|JOIzH4f08evwqy8VYo(N>O{Y*<fmMVz`pB$dt4_|H8%Bv&40;nKwj959|ytDgEw
zt|t2nBU5<Pr~XEdG((|nlF6P|BG>TW)x4BFzA}FZu3W;{<9A*G+lky2bX(u~SBoxB
zb)`LT@kDSp{mZP#Kd=uod6OhFpX0QbqK@yH+8RcPIT7pn#m`$ks>SOKMUP?a29exX
zk_q=QYQ?A75tZ+jgV@A76s0Cjr-GnLHXs8bt-~9WdW-3_Dy~FY!H>vvX{q*)Z8=2Q
zP|52Gx~)$x^4=f%m_(lawF<uwMe<ErZ2#3((_F>mgBG4X2PHeZ*Hly{`Oz=#jV5Wm
zM5mdq^OP!#mZ-oizl3hGT}mS-e2!3SbIvPn4(eqBk}G_=Kb*2{0FiWg>VB#nr-~)X
z+O9r+Dp|D;*&c*Qn?13$Miip*Pb--p{G*iC!l5*`^re7C7_-2FUShIkfwVavoK6?S
zUPtcdlBp0E+)hBYx;Kkz-n$7}>LuJ%?lj(5&BAlv@{)faTP$ThFZTLy-N~EAHTXnB
zsVwwMl#8{3R4><V+)z@R>cuM1lFw^k2%i!a7tB|7QwVy5EiMM%Jqh{~c^wnp+A$1F
zWv<ejr0C4aHH*dINRR2RIkfqlsA#IuwwfFWjGF1nSHvX%qY)m93l0qR=J-(!9uD$S
zmqKg7Wo=oa3K(0^K5XK#ErG|DxFXdh-<MiKqRPq{9TOWaNf3IHqsG9434KiK!)IXY
zS6KX`$V!W)_VRy^+#olX8WH`MEv`E`s+|2k$0j)|#=af&ONuxuuGt*xga@?W0(jB|
zh7K%Ze`U#xi5;|5ld$m-{BMK<taj9s<Sowb;L&eUTce$g9pn_d5aW<$o6tLWo|Li;
z&GraK2<%J4``Xo9u6X9pA#@MirE9-Dby*KkdMm4}?=mvW_C}fiqcDHt{HY7&fis|R
z2J1AD`CT$+)$+liM4n<qLWUbQY7E`M2=0Y$Ao=H6)Dwh0I>*?&;!xyOA=0&Jwfzrr
zx<GA1(z@~6k)mebFO}ng-E{n(nl!W7rYQKXnn+&+OzR0P35V@Ohrdb9hT7_Bzq*0H
zpu%3#vA6h!Lv1zpy)r}yD@(U;izR7@aq7isFaJM#?*nB=aUFQy?$>XoXEaDXqY;ci
zh?-#}9x{f<A3MTeTr&)K_!IoFMJziweh`AO<MomM#Ky7L)Ef;j#;iT?k*u6J`5suw
zDy)-FW}O_IY~mJSePn-pUYU=akbK^g35VmOI6gTF>m&pd_<py#-)JOjUO#WJH=Z|l
z=2cf$-Ky%ow{F$F^{=hgl9`0Mv-f5ra@`A@-0>GK<9b9oO_T(`hTc}(2wQjH(_#m%
zXFfu=&4ny228`St$${U*T6zmZ6HiTcRxf?hmFk2EXI8mVsw(A^L1`GX_1+HNHIe&w
zOO)=GJLOp!E*<nE7>D#Im&{VSkJb<<yX<rwOH1EhtGyA%8JdLy?4<BKbmt^4yqyn6
znxVWs^~u^e4{Z*Ilk=T6-BL~8<<Ah|4jt-O1+&$Z%MbTx=iBArWl6^fOsnOxp5X1t
z5|co|il)j~=mWe1S?l&j^{P&sH|Z#4o~N>hXzN5ZS=ESP20wHtb=!mA{k4b}YO$eH
zB`veG4FOXDPk(&}%}x7~e)40_$6oafCRCq=%(jD9f^={MDmqB%*u<94V5`p?j>=HL
zs^dYwyO5$P^HZ=HbLuibC+uiP#qs!A<g#v%4jY+Nvo+D}S>ttyytIZ^pJ$B4SR|zf
zST=($iAW8E&`Qq|v++oY(kYl+AS@?I9;IWJgNmrvpq8+805p`<EPMEpfzeB;?jv%|
znSf=1<M=4Ho+^Sqb(NpbvOdj<4n4|NCvJEoi&EUhP)Cn3Vr?B7cv^46qXO3+n)*HY
z9F&~XXfG{Lsbh*}z$#&xqi;d#@P%9SRtre-40PDQYMO?|v<GuE8ne~(UBKMI(IC(1
zDD+5nX>gbNF<aeCNax11=eW+cDnp8(BtM7z>DeykKS_w5<x`<TMP|lgSoTCZUZB4W
z+`L5o+hckgp1K}QP2pvWgKXK;TPspEbXl-pb)Pkypji$g`)X5>%lx9$c*Yq22{pOL
zg;GDo%Di1Ri>`@Kv$bL)o%T$o_#~vL@U#VG35I4ee>cryogs;5Z}L^aE^x}>Hl{ik
z%~owHjpp_K5sCJ^&xC%kwt8JjwrGlbUxuk}tpv}VF{fDVfnp=wQZ@1r1>AogckeUW
z22Z1Y^@m>(JO3RTo%2r)SC5>P$nC=*_|-3=fjq&v+B%!*S=5fg{W2DRANn4=9M$vS
z;%uuiRgzx*>LgxMj{~bYXbsUyF!SpVNPO)dOH<ymDd^w-oj_(Z25VW(R(IdaZ;+V|
ziWSUO7mxfRti)`+I{c4hLJleG+ZvZ~y71fkqUop36yt-t+}RNrS$JLDG24n3QnI!K
zdQ2vEXjG4IX+}>=gypMgY^Epmv0m-I%zHGaBud^~+nY$Kb}mB+gJUYjR<M=_uyxJQ
z7p{z`PaObeYcjuq{WqAcNqUxMQ<L`(Md8%vIS1s1Fqyf>5vJkY4Ax|CpXiKdCSj1f
z7_cv3r3t~DP@m4Ya^YXj!CSY-XQ7I2q6c*EnLil@Jf!i}OqA6dC;c_Owud<4V;nJR
zz`R<)ftVJ0N)9|rT`bSg?L1YYXz%2pNCH`$qrn_+nIRf`VhEgulhA|1&HO#NK1&EW
zE&(dRgto<DQqMxQ76?2bFtWPYj$z?Kpw5iLNd_FOp7s*dCDLMSm`;(yjK$A~mSmI{
z!rRs0pn)#X9kGzXDU}i?S&CsKC!Jf08Z?!`6QNyt^u$~skw*#{m8>%+JkQ;sVGS}g
z)mF=dsTq!jwu3>mqsQT-0iA?Ck=78nyxXKOw@HQ<Y%oE)OjdrJr>@%YAw)_N+Yvde
zh=Vj1^TnzR9tER3(nc^IueCxI!}8Ns*vqIpITvn^q0x6TNbfo1LzZ(a^&oJ@5l=p*
zugYU+Dt%^saLOK5y(_i^bTv%6$)Gs~3I6=Px;%P@3t5Ca+fzgmWscn-<?@Asvei2p
zrzPXlJR0=K!Z+yrAUH(!kjew=;6J*n+qRp_9ODp!t-*|!jVfs(>2EkoTzeo}m;3`<
zME)y!+KYU_Cx~Rd3>X#NduHRXu4h@a&uFE`9=TD%>VJM;T-Mpv`h$}Rvzf=q--$^u
zET4b7?418>7`h`&(L8&TN3%D=p~(#<PUg&@(;yY5>erDV{`+^n&4}E1rjBVL(1h4)
z)ok6fCX#2~K*!#y2%2yiFuP9=bdhkF-v60c?){U9dL+}05+`cznu_oH4%z``tC(ey
zcTI38%^h19;>UhevsDi%?dUj3b6~AZeeGIQ+7Cn6$JQ$Y6P-BKuX7}N%;|*EFvPf3
z(RpfnS@!K61F5H$nDxI>%5<yf{K(I?%HO<+-VsI@f!f8wY%7(a<YeeKJpOMPW?Mh{
z$F#m5hsWDK<$KzqoK|>zX<!GW!hZB-YoE4=rs$P>5yP8z+ktuyBYu~RrfR>^NnfwC
zt@?G2y^KKSnOroPWp?VC>7e#5N{WWl0egDPa4s-c!C|)b)WfIE#YRKg0mUjj)tYUU
z<gBAr;n9%Hf7S%y!whn*f^R344B8?33*>1J&Lg9HQUkQ%tdrFDp7<?4m;bnc@wmFW
zi!MZ*O~i2RV&9F<vj{<<h2y~Wh5ACs6WNcOK7&weiRD*G0+|>sd;_0oWjm_9ScYm?
zd*~q4QqyGl7e{yItQIkPUVwpR8M#9nYtKCANT_lsbqpBIlbM{bky4DVp@^eWeMSQT
zcHBi)=Ud5RDU-9<6T41_wzLxNlGzNyYD>R$ZZ62?fKQyP%R(7Wg*~t~;0Lu_KDW}2
z40Vlk7UzLbq{-C-IV=t<42O=LHnP=oHOglFyyoQj&AAWYDsKQ4<v!=VZJi8#I>#}i
z7m-r4DRDhjcC&=Zx~v7}p}HI_-CeMR#*ny(C@yv|Yg9WkUm=!K&@D1coL83W#1fbZ
zmcc{k?IG>cg67eb4fmtY2exyL$DkhiAjT4n%@VdyTGuSJ+uX#`PENm_*S?isTCzrG
zTMI#@#$jl%NG#MPXp4|Cm*Y0Y%5Leazs3p+(0pWn`nbQkaN)clt2NEf_z)b{_ot^%
z=91eAJi!$V&8_aUH`OU4mtA3a>~Q-y!Mmto&u67kQBRP(i-M3G_u!k@Kl4Ee?ZTP5
zNZ1y?{yyk?<;gVG-zIr__aYTJ0+Y>;pU9{`v#T7+><b2J1MlK1ke+cbz9DP!`R+m{
z*XdKI#OBF&wi@I%rB`T2v`Q%N9EPt%cPRgo$&t`qza|;C$)gQ%Z8GSlC>9A@Z?=wM
zbc#xXQ>Ps$e>Si#g34g6B4+ZJG4TBUFy2{{Lw4uoBKN<|`Ne`xvAhU<^>ms3z#$4r
zUXz8?r`X&vir!{BDfV)PtF`z8drCv{*e>O8vQ-~^_x5a&oF$~E1ML8`l?_alvR7Ho
zVYP0DKu;XZeM*LDv7IJq^_D*QKp!K^JLePm0?e+i@htap>SLw;T0Xvt+{w4@%mQQz
zHM-|F>xK4>*N!UwOgvH^l&0+B!;f00ZkKojeOh^(SFoZQk{7*lFVucNxs|;kv~|Vr
z>IeRuWo5nb$V$s4gw)#xzmmoI0Z7Cg7Zwbm3RjIiF8Bnu<UH4^BA5F~3XkN}wZ4%V
z;5n?X06wOB9mrI(@OBv5J_;FJMQeRqV20!Z2?GbRZ&;TiC#(hZ(#xn|Uwvsz?oUW<
zLKn+S767Xx;-m-D;@1h%WI>ZhV>FSxM-r>$>-I-nj8*`)7Cyh?t$gT*HV^o&t;);#
z4Ww;f+Vy242Z(kCBs+$bkk&|Oj~ig9XUOQz8qI)_HT19&+M2G9$=Ayez8pBCF`l8g
zHrB=G0U@>|PA^_YBaSrTPz&z69c;#v7GpX&4MZup#V#S7Yu$J{!!o`8ASh3Cv5I!b
z&NHKh6F=Va6<l3NZL)QAHOyvT3bjXblnE7gY*+@aoZfdaI3tHo4I7hB9^ius>#b6P
zF~kBe@W!1U?hBr1^~(ElTU2s__DkGfN7I%3t8;Q>z}4gz;6l2S(4Dl>O)*yP?vpqf
z<a_nQ1~DrDL;RutGvCxvktyb$d<_{%P725BJ;pP+d@zm_vD?8N*p|ouwk9)Ok&=lv
ztN@~9vUcUkCLY3UZGdZfE($CeOyKvGqB_I+>-{}^1CD$Rq4KfIBANTZos2d8JLKs`
z&iXl%vmfF~MxcjxOTG70Kl84b%fl3Wd+rU=r^AD8XcKdORo}wceW8`h-pWJ*5f4-;
zweSs=FJwi;V1_t-k%%8hGC7?qjgYDKppD%Y%+@_`WQ~HNvV~Q_@JlrHPS|C4_PT(G
zWY3eKqz|0zSHgrnOw1-V*B|daa<`cAKXhUJ#ld;`>oY9L3P6h`_bC4G8hh~NYpiV5
zlZYwS;y%bDjC?$ZQoGG)U^jzftPil>W&F_S`jZ>7yLN8OvCr#k957IBg4X10q+?Yk
znVQ%2D9i};ig71XX})AY)ShplPfSy{RxF%u#OTW4j|ZF#z$qTZU=+nka)a2Jm*`Pz
z6Oq<O-AN@!-pG*UX;eusz#6&=Eeb$e6^UXn2u*0R4^SbjBxq4Hmy`xN(Qcm)?SXOX
z^Bmx+HwikIC7D6(@i3iT+PjO&+#tCJ(Xi~~X<Y@)NuOZUW^ILzDz3sJ1t853%z1n<
zV0lkGJt$VAv&kOAK#>x*1ts-F$bMb94de9G>A;U37#30FoK&osuGr3Dw1yq=qE&YU
z@m#Ebw#Nn-TspZ|)m-`(tC&7U*Md`RW!P7EJW;&^LO2#a#jGbHojQxu#*ac&tEt5i
zT80j#Cw6|O+;Jz7$vN8evb)Q$8r8ECv$a!bRiD&qiU;+!)TCRLUVQTmN@xV_@hX@m
zG)R@cGc=f7Isq5BC1^_+>mr{Oks(c`U4kT2Ucwx!*x-hR;h?k_FuoMAjbHibM@}5q
zR^kQ^Z@KrQ!mU8=yBIKA-Q<&)^6YK3=^uwO)(J7(Z$vb+EkS*)&fDf-1;vX&<N9k1
zE5_i!H(=r}T1^p0?YUOs0XraL?mti!?(SpFcZnu^Cq|NHR{&|6tu&P3LuVPWPCS#J
z{j`Xwko>!5Lh9?JXGtY1$Z$nQ>ry{=px>z3I;KbZ+TPdM4(wJKch|;5r&0{fo|EVj
z;~<dbC*g+BB!4&>HTL%~+xpQ+s_z2j;xiMs@em1a*(ym>8qxTHb7?Cl#Y{JP`=-N9
zV?MEF&=#IN-D;EX=3iLH*Vv8cpS>V-a{r}r?S)?rt*iDho!i}fbu@>1B$M>q5%@*I
zjnYqx>7)@eAKVz6Op|K;w<E(1K8=AR?wjk9o~JD_&Hg~`+3kB6A4q4<N0#W2rKeg;
zYR&$-Gn=RmKNU&6$_PE@5@(eHjJD8VT9!#(lm7J@dhbMPV2`o7IqL17b#J>oVm*1b
zcB*YID?ifc#?*NF)Yt^KqG>$3Zf44M@Ya5+2fQghh}0|}>OEQ&4y!3VH81i4nwaZ#
z;>HOW2jPe=PK?LJAmp6c#?Y>N6(MY`8kr{%jc5@ttN{v>yrKKv(0qS%b6~aLTQwbZ
zNDj~te3=mI`*02IRzL?;lin+&N+K884oCq`W~Z=ZUm<2h!CM@b95kSjl=2~WhV(f{
zOT(B&(-PSJZ)-UZo8puUWtnT4z#efKM^oSH<6v7jHY`cq_pKSaYQGHfukzHBLxoFu
z%f<4;`cr$dEsSB8@cCZFp%V+m;8B`#A%eaQNFv9F0ySH`Wr-nsD-mJ%;(3e5^7HFq
zDtzWO<g*FfcK{DaU~GfB0<Pod59{G#*Z@B-6SN4%S1^t0UcgSt2H9;!1BhEp-=<as
z&zFHrTr&3<Du!0gRwcdBEYV}2cAd_(QIck>kWE=a&FutP5PA$4f0yD8a2B;TFoA}Y
zOrkZ4TQjBY{3>_~=s=z@<_`<lJ1SQfk|pDS^)yw!>DK}Cn>=lVX0s?WI<Vy9eUBF>
zFp(T=zRN<4QQXNCw>@~oqbLkJ2Gd!w=C|<gTBDp@1t{P|4!?a2z5prip+BA?s2H4V
zc2YjV#+!64_2Jz6T1g&|pM$n#!s;80e&YJwN6pq(&(y^Fp%2Cq-A|L`2H3kpM#cV$
zYh_Syy^HuK#7gZf&JA*2#N%7;mH5b;Xa{sKxV|;%G_Qi9euAR|HCr>evJ1?CmR{!v
z;ELYJC8d|?J~@zC&qlJtAMpt+ZlY6kRY!&KX6u)^`E_poVmy&+-%b3$f=H9DQ4VY#
zlIdF|`1+21sr6C~E+n=9Y!F^Jsb9GdW_R?u<_<$LiR}nmHU9BuXQei00zUj=T|qW0
zJ{kgevz1yN`g4GP>77{vTlD7Uo9lvsr@z{V+yHw16=2l)dG-<yu*uZhvzOn&LeHxL
zNvEkh-@caUw_F;^n`ip1W42YIn<UtKWRzpjDiTg>>h@q3oAPvyre*R5Wh;|FYh2^|
zueLpNe>sH#bgpD`3hlF6(Xl$pgxRW4)19e)J9sBrM?7<CGH6+}@1dTp{PX^%Ht3uA
z9pN|r)6s+*w`#WP_#s@Vtd)5qCX$6$i!3BC>X#|M*+1Gzbt0n{JnrCUzcJj~4dGz;
zQkh0z121r$v4nLsq^L>?)$HQk?0DZL0Vne6**Sm>46cG#hBB`%mw;^<aJCkvh{<kD
z3(L)N8sf}Y-rmp4fJEhl+m671Mg0h<C>$uGNt~$Wl=R>Myq=(*ZU#=z_j-rA5DUuq
zMJq)l;RvJ@`WcURbH>%yWZ10J&=^Cqu2VKp-0Ezr)zGR84EFd~39ZFLWLB*@;RXtI
z21d=9I=>9U!76i4b6M@0&I7ypf=<c%JFWG@j@A%*wPcE*6T>{%R!vRSb@l4_DWKmf
zm#8At5M5F395<R@lb>u1>*A)k=PQmGo=V(phTMqNO4SzTLsC&mB;u#oE@!jWC(Au`
z#}sFyh$|n4(|(9PPpihvccr6oeiMj_gw+Lps6r%8LM4=vd|FOoF$<j3kQzTXKnHpY
z$VOKy%`+(PG*Ve(6e-}g;w%V7K(Tr*j|~PGvocxZqG`(fDpVk=_D$%YqA07CAHNAR
za6wRddNDD!w-l(h@6EC@9TiLi*DLsCf5t?=JYgq{N|nEBokk$PB~Uks<IE5wtR`$x
z*Y;L*=LLSUw#f-gaHANm6P^$AI;@AnGDa=dgN}agq!6pco}7iPx<5PxX#3z0{~4(I
zRL}j&9*uC2*@MY0EtlIm961h1Q9Ul`1h<PltDhe51(+Po7wafiv(8J-qq_B?J(E*b
zTnTYZ<lEQww9qx;=C~f%oghgrf{Bk)Vw;|<kq;q1E6xe2!-e9h1rR;tl|~;n2iNlW
zYs0%;&sHUX3vq|7%e0!ZF`hJSo!2;JtbU_4K#QTFRo#}x*Q(15P$tNOcxf5Q*AYhy
z6@jmB;IS4bK&?uMa`>6GMU5%~Ej9wl@N=4-<_>sAr;!Xd>5^uI+pdJL)nYETTuTI@
z9Yw~8R8Dy=k;@V=+}gOJL;a}+hgR7<2_w8-We9Sr?nDtG6Wm4ELC&jQ+;jv1>UTU1
z>a3z?LLUzuLRE`Iw5KJ%RZt2zb=cZ6GtYYcVnA%hTUafw+E#$d4+?V0->atVK@A~T
z5bII~71>cA3a)L!d*k)lJgDH3Bo*EHqoPaIN_lohm%@~~Vo9lacRg6S5Yp_SMN9|8
z$UjN!I-!gG0Aigg<G$|?do~#lxxWKG9t@1ww{i0Xbl-kvEa^sW#`{!`qiI%ZkBhs^
zpbc*&nA1q)y^%KF9Rb^=tC3A~8Zim8?`G|D*|SuBHF7lPyw57!d9kx>snP>1O}y!_
zd9Wjr#Q!+KSUxj8*KAJw0tZc{^xX4t?3?D5B5%HtZ&ZDowMU;L_}ll|sCqx@?yfYl
z4OYMmNAD4|u3%n1e@48g@5AJ#ITQgkAl4&LZ4ZK3o3kE2*hU56dn*f1vCQW8t`GeH
zNl{KKJ%0D^b1vN<n23oSr>DIPn-1PM{oOx_2b*s#mpv=>EK<Pn^PkD6*Y5PkoXT%}
zxKHZiH0o!b4Z|-CrX{Wq$prIg!O1m69=%rQkCJFRT<t_!|DV?zX+C?B$Z6<H+b68i
zV&hH2qSJk5YF!xpzh4m~e-%D-l8el%_(}>BIW-z$(XpTcumL?`ByY{pmYmNO`W!Bf
zINt-&vG0fN_gg8=M~E%!inS*+^2F>^tVWN!oB)c|kDL2dD|vp)Ulz`#)7}yAw5*PD
zR{PNkMWBEMgRDR%p_`Ed%ct+6n0X|{B0CwV$x#SU)2k+f=l>w8kuhNgG>>pxXQpv1
z6gPD|ss;=Ha|o4Hv?$fk4#9xuCg3Uu{)lnT=M^&@B*9H^dS+3h?=Zg=j22scIan21
zXeN-m5G-RBDtjK>lA(!|jJ!2z$j${-Mu5RF8i-H<bu$vXvMS11U#!KZoJVlVtcJ7)
zEm42$e-v|{dKCXua!zF=3PbCMJ2Y$+pzuDC7B`cqZVG7<A|n->u?b|$KOr7Wex;W5
zn1dW1ETN5thLPa=nedCIbe~3Uw!#bap2$UUUHn<Kt)$CcnI%9Qs!`s&NUurtseu8R
zpc#l9vDtx5#p4>9Yz2d7#-h|^Qz6v-0vNV5fJmjZmT*IAFE=91ENL>XSA!%jilw6%
zOPWZt*9erTj4iss_05?W60|&MBB0FK;>-x!x@N==CI%rppm~D)sF1=J@cFD@hxKWV
zUxZwH`r=XlVaE^h>5C5DH@KVyE5UThB(j;RG3R-erMsO=e0g2m4S3$$V9w>t*dEBu
z*7vZ|a9AR5wi3N*tC1s{Ipk%>1c;r$M=0%~3!>!6Z&DYI*sKbU#C`J6L@eLvQ19xb
zpr3S{lV2qPW@{o17GzeQE3@3T_?4oa?+$JHt6S+8S!Ou@cU}$h3F8-0dFPn(eC!5#
z-*3?CVYZeqTSd)Qng6=A?)oxYY2TBm+3NQF^Ew&P&RwTU3&6<qN2Fm7_KG}mnq}D|
zsgU^6b_SYn5HoQrinVWl3i9cOXk9b-x)+C?7nkVL(Zw;nb}zr<OP|+~b;zo9AU9im
z4zrw4$xezm`6dff^&=O%9-}pQZHX50R#10dA@1uA+J`qtG=Dghd#co?$KN1>RFNX6
z$UxOeGezy~tpt_IG_2*go|Ny3PW^FGHGdcM4Nd&+Dr1$7^&YYEHyK6EKH65B`P;h-
zIq~$8E-_mrpLdgFAFZule|SGVsbAZ8A-MJ(qvEUst-mtW*p9T#QyUi6Mv>$>wlDW;
zWcrt85B6C@XFQeRE(8+qyi+FR&!wIu@O%}Z08=TFqJwk{Mw_}Ndoxs(S)z8K(@6NF
zkZTSzi?Lu@{n&DNb*42r#n6>g{!5fO`f?Xzi7`4bs6Dw$c3`$<`+r=M2z`pUN~HTC
zUWGI(5o}=K!A@SSpI<GM?c5hZWW`D{wkTZ<F{YKQu3Ae-w4X=~&})>tEmWq<Eu&aY
z!&I9#lP+dMJ7H5p1ht1qu7R5*b&BU#EJf;t&w}cgl~RTA-3~#IKd#5q$x{Qz6%!>=
z6k}VwQm!n8ehKQr5;a>(Avwnkv<4zvRJIcHEnXK|6=tM3^`jKV8$3(%IFWxU3+ye~
zCi#ZfrY$5l!MGuu4X7a_7|6C2(WTe@o*KS>J5Pch*h)Lr9-L(hll07lpp71f+Js$(
zuxgaokF!yrxc8u9g_K$v%TxL34GOrQmfc2R0k|yQETRoC1(!p@gZr658)QP;is;^}
zDl&WeAn!V?lv_h(RtNBL=3qcG{O0Az*wGX^ZoiM!Ebd!Y!ru!X@@A`|$`vY8YX@z`
zoi!#-*9S7&YG{W=J`&eF3SsR)>i~PAx6+LN5A%S0x5qDNt~$$ugtg&?^%RSN%x$-W
zo&B<nFk73__zb7#Gr<-Wk;H;9^6oIyD?Fqff8MhfK0A5(9SjIxfH^a{Igr;qx!xVn
z*;dVSK{#C^xeJ{sT`TDqJ``HaR*_F4wbOS5<Wm4luj=^$3-xLCT|RbtlqCPigd$R3
z8j(t+HkaCkyQJr_PfV?{6-q)+xAVmf(|ftf+KYk_X1v-%1<anyB&vU7LVGj_`(dBJ
zsr!X<o7Q~jPL`ys<8z+>oJjo%7EespP*U$A-N>N{__|H(<ewqthr@Kw>wCs!_ENTT
z_&nM;6f0UijN<(6dr<QJR0|ik@R>yRevA`@lfcTE|CffXf~UZ{Gdk24F7q2^3aMgz
zi~T;;o)u2h8I>F?heV9Ta%zgi+Aju8`79Ar4*nBBl?j_pTr)OtY#ZC9Klsf)>9^-H
zsQg30To^u)j;21%^DIeQ_%(5piA+UxN?8T%t*n)FJ|{)hJlqLU3_8)N;;c%KLcD}4
z#_=6x4GhLJy=bN-i7Ia>sv>`C``HB*ij(0U85lB|1Zr$C=o15$%nfa_g8#-`Xb{|6
z5a=Ai$E-R~0D?G~DI`VYPcT(vG$X*}4P%zj%6w?0VYquRsOnIMSd^nsq)rfXECyHk
zVQMT=;Tp)}M?ZkV{c=D?3i%~;j;>s9STH3ig`f<Fj%9EJbvx+#U4>e9QAsNMfC2|5
zSp&}E7((75`#>TbjGIVOFmkvOMjGoTB)(5$N0i;pGn^I0k!sV~6SVM`zt*S-6fgZG
zn99+rb-1Y+gle|BQm}mTZivZ9Nn4gUr4*$0vQ+Tu5DlKp8qoA7KB;<?VIHtr0ptDX
z#Q9YMhO)dFJ411!+8_I*3Cn%mB6bV;2d;rw!uTbL3ow|o@hb$CJ0z8-%0!tweYSev
zouH(+P-f+A!Mvx6+!|)rcH}ThwvWqfSS{s!+mV@!sG90_>!dPibhb5+Cm6h~zspuk
zWJMlUiN3TC-d|7jW!&f@;X^--rxpf5o)>o~2Ga_D_`*n<*Vu3-4iARdz0bdKE_UCN
z8p9g&tD7q=yso|Of`=?19W?JfNh<hz)NIWpxPT@jKV$SG9MZ3HkxzSi*2XW2OMi~g
z$4;dU_%=K|pUKgI1vv2w6PTIbrbC=zRbsRau~oD6Z`WGcv}19hal3MBe%#tRblu-R
zHK+{DTCkn@{^?Gpzse+U<17}#-O(<Gu8AAF=C7px`Y%A96!P!5V^m312<hylB1X|*
zOp=>9PVb{_s77ZsFk835JZ4+{X)ir*Mk3vMk!#;i2#bW}x($I%z7@Fr_Vw&e|EOh3
zpaamhy*g6vmpl1j==OuNn&g4QjB-SLJ8eAZ>u3c)2j%>vqu4QX614b}Em(dm5_YtN
z(7Zh`>n?LYZ5NSzKbqh5H~)Kxf=o7tnQdXVwdqfLagG}umb71XBP<eTAZiO|c$^zc
zIkl`=<2;Z&gXJ$;EYP2(RGxcA2G=J}??wKhYy-5e+JqD~<XM6)aA_A4(|S+s-Xe<t
zwgvh#;)fLZHbqqYB`vqomJakN47w$fXt7rT@TY}IUJ~n!X%g=&Dpf!uXQ%v!iLo6Q
zHKlZYnx#@0OL#DjvkFi^EgUPh;XM%h!Da_!u}GNGn3UpqtZed4v4!6K1T!&XRYPqt
z%bTrJ;v^Xk`doyCVl{#79|9$15*?=yO1|<$b^_ITW^NP}+XqPCgq$U$rszYhLS}fX
z_FIXdhJif{#1%lCf?&KAfySgvv;-jM{ET`sIHob*svM0fR(6I6X<0ESwW=ePQ#pRo
zC2EWtFR*m4r%LD!P%Frc<3~zP(*`9IRn@Z!UXvY%4$jkp53}jM(E^xM1vZ0P%af5f
zI(oZgq{0U(12X8*ONmhrZOjqrEVKhxF{eD96Q|D*_mP(sYjjWq!8OLmcDX}S2|u^V
z)WAXzNy>I&`vG>e9mAUwkjPjD?B5@TQCb=cYuAPI!J`?Ly^f@}lP9ze6RT&-0<Je~
zG@eA3zod5zM{GON3mY!jZ5hx)qTk~a6qYJRAGVJNRUN$9FQz=TTXU3!%~{JExi=N(
z;!~_}M~4UYZeuybk#$nJX>BqYe|Wz5m0_#9?R$~jwotM%bebC+`a`Q#As$_4Flkup
zqIrbFw7Ohfx=zBWOCqVhozoFVo+sp`GbBFe5@vA@(HL*hM4F%o3|L>kk!4StC&j+`
zK4X)ovLwH=8QI0F_G}y$Wz!w;33Rx6{%(=x!t3MV=#sz|zIQW@BV}Xr+zA(M<lB+c
zAM$Bjy;nj8H^k`eP3r>BE~{()`A_^J;U}m`_N9^yCU?Q;=L6?J9njng!HAVxUMs<^
zZ$)fBd-j8DQx;9=f+&f4-Y<>%)7Y;Jb`<8+1qeppG1Zg1-_J1L^mW*r$EZ3dAi;1l
zt-CPZE~oGzg#jeie$IKc{S!u;@(ikP$UW=CR`4czR&d(fX#;tg+h%OBYG)l@53s5L
zFl2)5lSbrvxc6S2bw6VK^q*X1;)Ts7ksYzqY^X!s4%$pA#D<YW$X~O1R{+LS4<zPd
zBpQvS>BXi+P@~Bs8FyAa3UI{fH8LXRK_xrohJUI-EwHZTTlT7>8NxAXjt-g`poGP!
zDy?LzZ?W3^dRi=XN(O4lthG?>v853w^v{W56_~d(<JWKoPlHrSUpiHq@WeOJo|C@L
z95a68#3;vGJm9o}9Bj+e?n*+dc_w^5Lz+z_Gh^%M>;Xc@_?&B|q_xYV>*Ab+=7}eK
z`*-hQJV110$`}J3jm7BI6d8@x2l-hqdKCERd3J-@>K21xOXzRRVo*Cz=t2-<l~xp_
zu_$E|W>d3peX1~3rPMBUcgBTHI#pgha_1BhU^a!BTfOqBCa5`4f;lEu5UCu3B}h>{
zTN1&5f({>c4wH&HMf07^i8#H9gz|Z6hX`w(s*Y;tDzqr@#f|aM!L=~<1A$v?7h93X
zUtxbkYUO(TXbt9VG>dy%v67BLEvWb#1j*H<a)sU)Hs&#5e&iH*u$|$AduMd7GV`Q$
z4%kzKcHoF?^fA`F<1AX>$7+%P;244a<Av5Dwdb`<-$ik=SuHnDGqH8xb5<%J9>v@*
zfTYerho4}i{vADRVZBlIC;#MAl-Q=K&7)X;$>(<|!Qm;tyM|%0QU9KsoVb7KH8OC7
zkc|`@5Zs5cQwWI_Ie6oQ*gx#$j3?Uo!T+P|6O}NjMrsu6XoU-FM`1ZX`3Mk7>5wGP
zL0is7nj5|(Fod-S&N7rIwpeS{1&L!Va8Cse0!|&}kI~;>pPTb|p=2hmt_8B|h?tQl
z2Ck6l>mmQoY&KH+ukL6f(zFL-tvov_d|9U<^3mx;Mr>K@&7NBr9gDu`oJold+Go-g
zvF8qYfvTH}jr8vcoUzx*V}<pdshOWy2xWezSFBpR!$Mb^DaM{^2o4<GuV1xMIKtp?
zO*q+MyP@&iDYu6&^{`Fjtx}eAe@G=KATLtVU^De<%ycH>A1Dol?o@*rTf*>Jg%$-2
z?4g=RA=-#3uI|RCYhe!9<5T$fD3e2vS{s(yEPS{AZdMnTQFr*KTy+&H$LEp-AMaYN
zhYh2_^vHSvX4DC%vOz8NuYyv*LMc9@s-F2pI%~v<As(X#t#JI2jb)1%M8?_^V1{{^
zGv0HPHqegMOM(jzqtHp6v^kiTXZfqmqioF9<SVrr3~Ga*O+~7iq7|<~P64$iO^X^8
z-zK;2mb=DxYDLHd4Vt=15S7TvBf~F;vs<1_b<#Vuo}E)ZIFTz+mXs?$1dMALq0}vD
zO3KQRilRD~magC0i8N*vpn%dA0Sd3h-_+)jlOqZsbi<sB<P^(6P?TIf6~u)ZV>Q^r
z(S;G*E|DbVfrpS~-|DIRyUv`bpUR`PfrBe~SZ=KN(FuI?wm!eka$3n)E@HM7^+v7A
zb)l5rYvFL=3&XG*!AjRRIZT8U&xB6X*tIyfM^3$=|0E<nW?O?;E)FGJfS=*(q6w`A
zMg|=dH<~zuY1i^Cf3-5Rjbh{TS$!2yf*S}_<vQ}luwg?xG~8TU{OHT)zG7mG<5i|!
z!`W3&GZCu07AqeO!l}adgFR=zBb=!(up{Dvx6s4=y&2a;qvuTti-cuDZ?1f&@lvI;
ztx5EKxyc;aE%IwO!Do%W^E;t60}Ur+rmckxsi!?8cIVroFfI2=?bZw8I7zc4FQ3E?
zy-BK40+V5E)IOJ$AKN3=AC<NL(-1rD<@-;Vt)}?B_a@kn^L#tf$y?S&;oR*A4ub*Y
zAkk$a<ltmWMf{22ev$CZ=?v_B7m`0QP>#}<N=e*vStzyU?o7;KMA$*G%=kaTQixl6
zqws?#g`6ZTFq3{@(@@xRi40a5QwfVJNAc_Z<YPG6NGP+W?D`i1QL{Cj>ENxdKcYf$
zI}EIpB(yhLqxa;X#}p_ae-+PFHCv6CcTs^jU)VHvnxy>FEEs#~lehbRIZI&urNC)!
ztFiexaU(mn%Qq#TFz*qQ*v;HM7gBLn0SZ`nsu$gv6f)ao<Q(Wz0G@a#N!sE8NAaz{
zKgL13F^&T2kLi+NLmcRuVxFH(T0U-yKoj^3<Z?s3VcgJ;A?7}_)`f^wfC5lG((|$n
zYK`U3)H@-I`wPVJp&qNaC#&u=p^C094b7K!`y)iXR!RZljPE^(Y$8~&V)O!v4dKg@
zMdGs{76H#UkNV6bi+%_%gHS#{ozmc^J+9`9EXt(|;+5(iAPDELz~-sNpjOlgu3)<%
z6cn!%)sYwot;EixiL0K@qxTsYxl$P$xe3|nDL+3XS2r~^Og0se9KT{P@&IKubp*n1
zQ_fSwDV}6Km8O$t&l9ca3nHUX^B>@wz-)c2m@-yINEVJ~Ni)|oYY8J88oYFXmT}1p
zhj5b&YPq3QsSXyOg7Iz}XDEv!C6DOB!&H+j$cDner{#H$?m20bPZvZ%qf6NYb0c(_
zy9QcK<)45mdUbnN;`&k**Wav+$TQaC+v^-=tKcYn(fNxSwy}H!?!8EFD6f;ClBxm@
zYX+X$5N&hJ#3;Dp>IBlcW9*2HgQlD@E0TS`y?^0N<FpR&cHe1{&#LPk$Ph7aT0gxM
zCI>zh%f63E$mDhr)UNpCTbxWUypbV1Ru?9JFG|nKs4gIVF?5!j=o$tkl~b;Iihe&O
zb~nE?7%<z)Ai_<(eX{pE;Y9uBGUxveNEtDXTFVtlvOG**A%We@_K@%+B2T|O=^yo9
z&Y)4AW^lxv*;3+`&!JmlLSEFb$j0cL#cbsa$_`!~vo&mfsN~|C7+BIRthi2H<*(sa
z{o19@x4OEqSuk6pH$O}86Ze+Ia+R;DA^Tf!{bjXv2{6UAiLJ5!g^I9$G?I@FP=o%=
zFEyNhxyNvnxCHfQDXEiOwEUF}rs3aigv}4JnynSg)<-(wYVC-?o!8NoRkb1Bd;%hU
zpl2`(eS(WOTOV-@I*%C9wwP_rR^02@!}Zb+!-ysWo$_&>a8rdE!4HUDLfGRed^=Rh
z_CwPe-o0>2>(#A(%_zZSs4961!7$LTa?!{o+nq3lTf#6e%GxH|V^G7rty_1@cGy<v
z4_u9g7%G*{F_<{h$!1+uWPBoU;-eL16`(+9GZD4;|5PXH3ZRsVQ;x>N&=c!|lO>m=
z$a~3Lan%vxs!VH-ZAf*LugXU~zc7cRzE;SIuGUDH(niSI0KT?hEcfJ#C0fDVd`<P`
zW8<)K0G*{P0;@8j1M{q^*BwoZM->`Psl<-)S+2@@mFrLj!Ky@XV#bHyC|(qa7_R<C
zukFAWtEr}`9agi(W>PTZPs4%E#?SIw1&BV%M0Cu=rAq>nX)gt2aS@b6Jo|Pji6?a6
z(E~innFP5jbfH#*L#v#H{{t}Fs#L>-EQG5pCMs-%wOAR`Dqu2QY-zE&hH0Y>eS~J)
z?XXMgCD+58^d`Qt+LXf`&|`Zb&45J_C%Kq|BW#f7^kvbQENJ?5jzz$XMfixdu<;0i
zPIW66F#M11EYyfBWHAu|?LmuGj53Vf$u-sL0i46H&Ts^K=nciL!XgE7zGULH7`mLN
zCK;lVRpszRkhhOSA&%N@8pZOQRgXel9nC|dJAj(5m;p4&Dil({f{`@nRH2vCUa=UM
zTUD+M!zVL{+)A1gJJ*(u$w9eheTX)=h#Ejq$5sfVp`Acok+gbb*^&{k*pj#Erw{E`
z$5U2&JHyX~Xh6djUlF7r#0}*YBf2`DqKpNc>RT}rZdUK6SZc&XT)--)L5Vma&4+4{
zPI)@c#fK;-VA1tl+QU<HtTm?(3Kv73nY=Wycj7ENeV(ods0oD>0>*3bLZ#U(pskzg
zlHML9(<IundD<>sS}7N$F|dx6M-zlcJ%Kob$K^@PZHnC~C*~QK5?AI}7lxDhHGRse
z^xVmf)#n+<<Dt_mTlg#W3R|z5R*N-QBuxje8o?n%%@6Jzk8WE5Mi0)5^V@229W2!{
zY)#YBoH|7`%BNy5b2-CmmTIG7t6)_8o8p|_tU`+dNiP}>+a~zvd<1`sVPIj@`PD7<
z-}5z&N7kAjOkz!*ks7&Ax2%`Lu+!tFd=4YI+e>uC2jm>`{$-tqW9hG5A^kJk&aB1h
zkbhQtCFqg#iTy;L_p-^mCqfD9u2>h#@Oef?pP(l+gtP}I)gz_ZsPRsO@HUoH>|7Jn
zNui7}`~-1y8`GSD{Tt|U|0j*F#?<ek7Qk-1Yk{?)S21?EG?8Moh5D}z#&Z478oTFK
z2@f1T(_6u_d}OB?P{4t;<6e(yn?-j-+E2d6a2yVl=2M;5C;u{h;s*6tV%Un#_&lDn
zP;uaUJ-Yr-<IR)I$@o)dxnU+w0)r>kRjPA;%LwAsHFS*^(i(jKGfV*fGTQTFj6+kh
zsy^8oMXqfj`Ta0-<qd<f_ZdgCt%FM<|H#ZByKEzOpzO4k_`tT=bU~!ufF29wtB%cY
zqm>|?>fohAJ?=`E8Jgxgc_6&qCoy(>RL`6C5T<;c!$YdZNMqDE#{R1A=Aa?ZpC;Cx
zo=EwbCH?6{hTYz^zhYTm4C`uTQ<J-UoYto!@4{uox&NlUK6PGh`<zyItT#<Kq;8sq
zkw0LpquTC9M;LBQb@?Evj!8m$s6cQAa6xTcpwXa#&T*|HAkJ~|8h*u)hE4RXpbX~O
zi`XMN0XY99OsZp^V==x9Jx1SIg=UoBlr9MBfHZauNDdQq5w}iiqwEbVKENLB<%~G8
zCM?0?gq6$^Xu8O0C#*d8;PPwROF+JwYJn-ahkBSlIvzVXKA=nQt#U&LB%r!+Pz?pO
z5I9%>i<QbSS6AG?c<wL{mpE>9unOR-_Ik-jDy;hb)<yE4bwpwMTIWMMbga*pl%oN8
zCqc;uS|2f6H3Ma+&7M6gUjw@nbc^ayshY9qOR~XrL<|3A8%UZ#i;z}tA-uv&e#INH
z3}49}BvL(O)z?Q00b7q&A!7+`3)CHQv_`D93bUwLK2M?RX8X`IW@{?%Z<|B6L@MDQ
z=65@Ucl!b(2m9h1GSO{If?fR&u&C^aghp-!@sYI|dr+f-1!bDT4Pz=mR@cKAxvrGg
zfWzFRXH1CvB^r~MR&~gP&8KVUM4O$2N2bQajhzWsM|_oZzsUI5Q{}$6R;ISBf~Uaz
z!%}yb(wJRz$#~R!dcEy{F1FG9Z+&d7gRJofCq&Iw<!<ze#F!(a8H*17S=P-4;Tf@=
z|7z@JG-J$G3=-A}Ru4C*NReThSKu_Q1WqAv0Et9DOS694FG=uqnT%>AdHnT^BBo_I
z|98(FtQ-~p!pv4Og7&2Gqz=eow#xi7vCIZV?;G-=gXh>@huIoTU7WbFXX)$6Mswh+
zDV~AJ)c3|bry^aLIQ{ct|JzHwgE3}n#`Vuyk+k}%&?{YPw$2xos`2|Dxm?_rPacw6
z#%yrgdBH)RyVA4ExHmT>axb1?0<9&hpzS0h2Y=_-g2vcF^MWN^?Q+y{Q5wm`Zl5kx
z4E7Dk#_+u!H6RC;l4r^En0E!|7bd2kq?~`^kXg*uGAF#Sp~?~eU60}&OZQj|b^};^
zf<?B!QTh*@S8Dhqkr7L`-T&fIYpFP^m5ou)UQcQ2P&uqFJtzQh_GWs~BwaEr3fy4m
z8$WY2Wfl9kb*GstSan$3i#wKSOC9l2Qvq(#8KAjH!a1#x9=ztQ(jFgJ49las_~OQS
z`7K5X7hsDPL&%BFb)#0O6WQs9c$?4@O;x$pVq$LCXazuIkxhp%h4>X=+%IkeyL0fi
zlQc*WIGl(lozClE_GP6JbmCUwooBlOF`0SJ=@1NO{B*P9h3|>9At`Pa<!6kp4ScI<
zjQ$*sAKYMp5w%3`G5}LeSZo^gI4i760(8l#RZl0-<0t`1?Tf&6wUYITE|9xsc^<39
zR((jfJ4&7$a{gx4Xe;o<*CDez<5wnlO<HXOracCmty6iHa3JHf<to+0+fSN7EDOFa
zS^OP97=kns;rdllj(jyl!H`*OQR4Jw6`&AAFx5m)xMPTZ;OVm`kB+pqq0fNs&1kAp
zbTQ5Lwsopc>&GsfEHudTyx4_dJfw%_VYb4;hsPsHw?O>EYRV{Bezm(YzutEQ5yzI8
z=GD<vQiqj~_UhB?FA){pg`bmJN7-}%k`mTk!9>~Y#YXCT0<HN4z=^SD-5PPf!xwRP
zzIW8ze9sy<XE9reI70uXGjTf)1ja6$1=*Q3t3FI2-+VQn;kb*#oRtyt4}U6gTb9nY
z78I(zwv69<g_z&j#G=t%GsZrwiZ}N5LM1VCYn+=HuwET2%&7|y5HsNv9=YnCw?<L*
zp8|&W3ZMxG{iN#7D;OKNOq%0Ipg8c@CSBQ-t*+<WjM6aNSihg{MkoKbva@<2WAlm~
z|Jk6V)1{CNjhX!FwJkJ>-Tz2Q+!N=pt?GY@8GrP0o<z+3=W|Z!cO`n<@O|}&w*he#
zlmbVvBhw9LDyWocON$_Kk+#_VuhEgZbu_%U`xNE6?=@SgS<&LX?58_Z?tz!J2h?nx
z$O>>V%zfTtxK@hdtKC4Y*s3`M<)+-|*SVR4Ct1#*CGoe`Xs@seM=7AZ%yzXlj|ML5
zn^&X<=uN{4o=j9dvhi-_R7dkWJ;TSU-y;SSN_&2e%OJlN=p(cT@^Ky`X1CsO4;xIz
zGCmUOvR0<h=5AlYN{Maii&SDaq1Vg#wAYl1LVMUR!fdPVsp_kzGAChZb>9Y{4SEi?
z<*DLvnJPmHnp&qZE*mSf>d#?G?PvuZbLHp|?i&=+E66O9iB9%$sgqeyGRY2}VO+yk
zA*Vp3YOKsiicu2TBKjgF4jf&St9_eFp(FVs*vyylxW-ManvBm?4~o@r7^D$es&ZPv
zdAGfzd6>wlh|Y;ArA8Tjfoz?x>XV#Ao1g)!pcF8k40E`l&bAiAy-QHE(bF_JTkDHa
ztUTM=x-p!&E<Y=_57g>@3v&oTS7wO=pd|y&yKS6^W}y{b)>d2+ht$^a5T3x-)a8%S
zLhI5il=8E!uGiFq-|Lg;Ya8wLMYM1#o|~=XBVeH39=c$DH~TPv|C$M?dS!P!W_(kr
zrw>GKT;#<KARTU1oU)bjj#;Ug?bg5*8yIO1t`%J?li52Sq{S`EEP*DPVve4PR>v_=
zs{jQ;iJ5Jc1L+xoJn&lM#-HwJ3S<hiHE^YmB4-0HPRh0Wb<hFkU6yG^aGlZGR7S0a
zhF?K5`Ujb9yvR4<{A{br+^##3&)a$<nfjwJf=!)(4UD4w&UOSH)5;E=rG05LTEK{k
zD0AXQ8Cg=X6t`<(?mebCeXt}oj80d5vLiY$eexW=aM~;JMSl>=mfURBrcedc@oR3X
z<~(L-BANb3AQPJP;%w{4hg_KMr8+#s6gW~moqy$3k(PyEKLZdhK>R=VP+Z?~TA=$p
z<gpJivb+#X9jP-q5iOgzn<89jZ;<hsXB`S9MrUx@6_vu*ug7wyx!4_Ik+6A->1BXD
zGg~#GZ;P`W{Hh1MDW|NbuMdn5Wwy2Cn`Zm}asSL(hBNNY1gwxByV!K;wo*WlOi^Qk
zfplX@n*}*Ihe~!kt1J$#S(Q~!<y?0Oq~wr5D4RwX_$D-uJ>eymv(H37F&Pu*m6MC)
z^vv<ZChJ^fGE12)ZfTxzfP@z^G)uwx6d|ceuMKW8Y4D~*vG|QltQP7X$0>Y%#aZdl
z)E5jSnNcZ4UX7u{Ed<MPuUG3Nn`dok7ZXJ4%Q7&nz)*}L`p~0!>ta+1Y&NggLT!Jo
z65ZI?st2%eQt@w7M;l|zR;T$NEkk3v6Ka{L8Qxxnpq8kwJy^)6d{P$bPT>})*m@ws
zSbS^rF3eVXPpNUjc`qgtY>OJ@mo!x2jq;=e2zne?@qi0vjOIl$uFSArDLhV!YQP=#
zjy_kH1Jh*+3+e>;JDF`=Y;j4`l8h~yfrmr5&S|z=D`KXd_@;8)$0@e)K6UiYa?z_(
zr#<Awa<L%xkZf08k<?6+(7^IXw6bZH>vjm9g%G!#WvAqi9+c>Rl$MZv8PYhV8=DYg
z`FShyfxA5!A-0iAq3#^Sb!%9IlF(JheKhZhLpSPS&&<h@M2C~Osrg0-Y4AL1?ZiT6
zQZ0(Q#-0cq>?|{FC?nhDQ26hu2>W`+K(xk@*BRHE(+*9A^L9gD{Y0s|Ei8G?#BTo8
z&OLAr?OF5kX;VZ22lLE@Wg9d;2@5|e){=s-$RBfBTOS7x{<_G%Y1Xxzk4S|z7N0I8
z3^Vn{n62;yTp3Iyz>pRB^f+BF0j7%64%`e#Pn4ti(RW*!zN0SnhHt#xcr&uiHwB^j
zcm0Vuc%{$2T}E9I*LS_!X7x>#*gFrEA$tKhsmsuBu;VyYGx0Kr-7;G@(1<f$J9Fp?
zA}+#q{Vi4x^RK6u+6m3Js(U0U!o)TS?Mv{bKcAu<LE&i&j)cj}obwb??7$_o6C=Ho
z`q2DL^5=2v-gk~o9{A?~#BK*SmYy!QMTJ+pk3n)BY;6ZMdcx+X!C25LuujaP+4>9I
zkHf`XeQ>^Srsh9=b@<mAL(~;A3Tn3M)k=fk%er=zO>YEfU)&xjHgcC38$8w9FYcb`
z`k7Q7)1(S!_uxXbgR?l(wMiDz-L6$F3E-;WqWR3z#<faI>zW}+`DuC`5q2yg40edq
zlm_i<-b|`ka_97a3Xg(|s5aK?$a<?Xs*D~I&8j_sYr{I+<)ej3G@BKbC$Xw2oxB$e
z(>{~#h;4B(ij?+Z+%UZ80IaUzj!6**QD}XFG0h<`Lu%K!gFYy0+VQrI=nq|1i<}<Q
zMUmtDb5Sd$5YX%bDh#`R9P2LX(&MI&Rt4+LVDczx%L|KH2?+I_t+#;6shX`~TOrF`
zb*v|Vg9^sGFqbP5n}sT$ZsVs!*T6;MBT<HXMAK@L&?R<}on+Y_D1ywa49IM%m|<wV
zSyW|-2Dip&AWxtrb~h+9a{h!2&dSN23;zo=aakG$sWNabL@UzaNYe_^tCj~JorKDH
zR4R4WXMXjz1*fqwr}<m;Xm4yr^~#Y$H8?)`+xVNEbkdq=MFX2cqi3k<^{w$ujqQUH
zeyi7bR=0iYkg=j$*+`xaB-3b1E=>K1`#$-Dh7A@tmczY@p{i+w^mBoeg&|*YT*kb^
zoQQSkjLM^^O8gtzhI)CMSEAY$sgWW44DXh)xl^;OqG<Cx&pvD4N8}j;s9sbUXFaPG
zzndW*{CgWT`O1CIMZYZNFEzKsx|XmlSZ(kwWQo{K=VH8kJQlmqD@y6vOA(+WmrML0
zi-zOd__oG>=acr2^!P<jO{bY+wubWD9juj@u?$?4gZR_qtP9nsBCry?dDnOl&y1dz
zb<_*fW2ABNIGwY36Q9(fV~93hX^S%Iiumb|xY~qL=bjsC(bF?FTjkL1)oEYl)aO-Q
zifHoGY^?>UCh&V(Q%;{aRIWL1w%%_=J~>6x`9Wdo46a^u;W+9tzJZU6*cTAfH(ub?
zXo3nri%nj_Y`tliQzIyLe;Vv1P0vfGx$2%L!^C|q+9~($mGuP~t@vmMY2`j#pq!o}
zm2`Kj*Yjb^IpMtD!m8}i)10K1^{I|w0tCjW*?JacYrkB@xcl6o>vtO|NTG3aT=yOf
z*;rnf+$Zrl72R9a0a%7Q-he_BuD1cj_RBw%0)2!R&qViPTvBdOrApVXu0l)kjoAl<
z$>I1b1S^IXw+SIFO|hKq*(=)5;j^rA^PZXkD+8r8qlim@b*rlDs9=qF&DGDWFG2W0
zuk+70OB11=3-pP!;DhAgnnEm}FPvgzt7tIg2XkI&At;bd5#wbI(rfQD*x5U(Z9xhf
z!=A~kS!GNYM$^B!ein<R$L3?=SsxHO<F8IE4Ka1-TIFxY5ExxAZk3&(?UAv%kOexM
z1}LQbY^c6&2CBTJ<7-I@O&VrvCvd0I5hjXRg565W$!ao*x#Un?J)Tpf)KfbU)M&se
zdoWv#X7WQolH?z~nNndVH#L}gT-Nxyc$`|LOFX(ADoY5krp`kBCHKpF%`s7BsV})d
zgvdC(pPgN#Z%dfqM005o#;aP3XiIWg-m6b&sZ+ESNmBE8@u-e0@hY?-z+!27)18p?
zJiWD%)ah79E6&Qd*3X8v6G|*#oyvL8_x8T|puWcVG+zm=e94=wBmGX#HT)bhi`i=Q
zn;Hz*q9h$oqW$1DwF~rSYryC(0VYtl2%@Afs#9$LOd8IH&AY&Nk-bvJ<r|n;-1W;@
z?6O>iDETg5F0Qg#ckjmn_r+$(G3i<i=E#|7wd?rq$;ZXmgWLeKUvaMf&h>HS!8KyH
zv4G$H6y_^tt4*FClo@$roak(;*PW770*BdZ9;jHq%BIqZjNLK^R^v@#H+?OVo4@9_
zEX(ZqQT>8<Nsw@&u<W~8MvEVRg<~L0@kbrQ39R^Jk#Njx>)?DR@BGL!VZ<U~7cQ>%
zCKWkI@>D|aR^}Ui;~19r6Z%QoSp8O{)qJZLQfo$8H~|M{tz(cY+!e;P1*A@+3m~aJ
zPGv}Y*-~OA_BNmG6XthyzSjL(wMQP{=!<y3WDC{`a$4chRvf(WZDhU23A3$6JFOyc
z?gCI~h}CTMt!Idrro57V1ulN;Y;OCfYH}4y*xUqmQ){+$_s!s$NgQf`G{c@Cnsqj)
za@&ElCh`!73xTOKGAY9BsxP~TN<k$O{W??ioY@YZALNw{Mhw=7r)d%?eYh_IUBqT>
zQ_*1GqH&@348s!y;7-^;f>Hbqjxp&2?BS=gt)B9KsUdKe#S`hYiKq_kL3>YU(Q|e5
zqBd6%_esyyY$ne7#H%dLXz0B8$&mZikbhiE7-aOxVwZEFFukVqH5DP_qes=fj?O^a
z*;MaK^mRTwlPXGJm^fpF1~Zfa!=pqqF!<Vo5!ebkhPD5IB=>o?&MU;T*>fa?L)xTU
z+2E8=meW`~gwoJ!2NnKToiYLOvT(}K(2C(+`K94ROayiHfMES)(Fts5^+p{|@!@0l
z%3X4q%97$;4zlW?AD&c*WxAAcl^pIeJOJU0Qq$aYJ;Z+e)Z}zXP*FMmDkEPz+JuXd
zcG2fOJ@BT6&j(LN7%*-CX||r(9)l>z&t!Ubr#a=`!Zz3=dZk&@4)G1F#AMGJBE5#^
zwt=C8EzXGKD;$P{W)kQDmeY;b1vc2h`jz50woVo%V9z>u_}<ctFhAho%gF8H6B0H1
z6AnpAqG8Ndoo&TzZPk^-5)I3apqWh&oJ9?&vnCZ7v+A}7E8(YD>T;fZa)u(K=t`ff
zeII9le<Kro=fG*7Nq5Bl<qM(Ar+nAwoC_+l|F`%IT#Ezk-d`7x293|q?0uLPcY!tB
zU`Lm*dG(t?9DI$h%FRu~GR#)V%vQQwFov_etym>{?zZAyWT)KPpU2=KY7EpOupb_$
zw{EP9WYd*Ko}Wg;10EljYL#Wl{%Z^)S7mLqkLg;+MVl<-*Y{_x)QlV|A8^HNwR$9z
zbxgfyv#l>QG=t1+eV*R!&=w+?N@=RuI#{ARWRbANZ!fygh<tw?9idHR;)OL#vYnB2
z${iF7qRzI?4@mUsTWq;0z1|k<-&K=SucF=z(?$%OY3i~HN`c6efreO`9}DI?pb3n>
zkW{*D!Z*bEY%6AK;-_JmZQa3as|&A!-*bK5Y;`{0#?2J={Ask40W$i6r4CSR$KbwV
zP_NhYMQm{1sWnBbAVJQJTQyrlNje&=BGt+UrHeLORCK*KKUZ4x$~D-c5RKx@pcH8?
z9#lbs;WmJKW<uG1JoqrHEd-gANSK}fVojds@%T&cnP_s{J99Q=Gl~+9=@aYZpn_&V
zepw~;AzkVi<dYFyrH7fyYJQTU4i`ZrCF?nvs^X+X&1pF;f#IYk2_%I9OERi~qd*XR
zwR4Vv3sw-$E?6-d-XR1{J@dn99!;SPEuqd32uiTYvq%h)s{m<?evF2$31W1#umD++
z*a+!Jr9?zVfxxM&3^wWsSrerkxBdnOP!WcFNL{f)5+=%^QIO`cCPOio2Q4--POKK8
zll>%D@GdPxR;)hHDp(~$Xd*AGE=<O99<`&)kTfC~vB<!jk}AJW(`6B3**HT*g1{2w
z4X1D;-1fYN%@SJ10J*xbBeqhkrW#Ho6;(e*r5CiW&<)HPxh0*<IIE#u4yp2FEqhgK
zjQ6+_E6ECBArhy9>N-WRpxC+6vrGLLAXx+kkdN3-3y|tu>ROHNf$-aDI4L#`_zFY3
zUq(__)`%j|V#B8NoWnFwlW~rK4I$c0?59C+EVIBK4$MMPF5M8Xl^^iZW~9@qZo%hY
z8K{Dn@@sLWu71r<BQk)YnGADPG5%kMyjY*!9-qsxWgZ{ft@pDKyzY2=%Uo$O5kT=r
z058E@<l~|TT?WvxNG4#_D`IGPz2|r*jNFMMjz`pcUr}5ZvshXOie8pt<-49V36nMm
zLd<Eu^mIN5Pdlg~r$!kR&=M<Mt(VTki!2e!OT*q935Y;ML*u7soZeW2qa0im;)?Yd
z5L5s)hBd4v<7fj-9x#RPlc;OeH^Xm{&l=FRP!FIFq{u`Sde0d`ioin2jKZziRZ>_@
zMGi{x&}F#<V@l?u{bqK45<x`Ar-@wg7}qds#|do@j@I1JkSF1Oal+T_Jfx`6)H4P8
zYBci>p5J4ybZ1Im5aq*m{Gy7vC~n85vPxpDD9(HdU(}N59LwpHw|*{AIqO=oE>oz>
zIY!${Qx1{vQ0UJ!Oee`pK_5jyXZKgZ6Cy3il>4j^c><Euk*m2*2;<Je1ici@@0G1E
zqvGL+N~wWa=MrYhadbP`xogm0tEHUYO-|VlYew|6yng#vp>cC%6AcVUo$v!mjrc0z
zHplLapxi%q>NLfM^5TTZ!e|_&%GYor7h<Bi7yM^0V!yKN+jLgd-eyO%NYnF@p6C+{
zWYh+ou0PaNy0|cnu8myuQ$#c&_FurPgB%2F_h5^JpfomawG!{(WQm3KR-QZ~u_KRD
z73QN^dg(&2jx*$==woODFH$`Yto34=yvUH&k$6J(l0ki(b&Z7?t$c*BDNemnu5A1O
zYmfGn#M%yCI^DTOW_)FMo`r?Gv`OX5LLY{KrZ=>HPKL&k0|3H!iq_o_9cm%z6Ufqc
z-w?`}z;zATbQOsfXt))pJ-DDg2;!PesMc<`IJwv3kEHC~7-n?rx8GxAekQ!3eJ<S*
z8-B!}vf?JwO`}GhfICX;0tn?sHX_!0=qE2_oPDQXZ_O@5k`6Lp==e;MiO__$z;BZ+
zR&ZIC_cT~LdY-AF!$v;D?599l?~WjtD}|-n8ODwpL^2rliRuy{>3n9r-eWq-r3;W?
zL{Q0lBfZS9M!uuhR!zvS6I1N9+U}8+f_i<`aF6P(7i9J1;3r7cA1ERNP`1Hk!Z^Jv
z06$*M)Ej8lG%3nw!FZG8ns7n-#ppq+FNwL-*}IOp*y!-4Teiw)590IGLZ;OD-v{(V
zJWxhpF;+TzOaHul4$NOoUMFZ5rAZF1E<Pe_**(fp$0G+a%}F4hImBpX@L4QU<|z7c
zzAE>27x}|i&yXSKtCAl4vII=a?<D8P(u*EK!V~Jn>7^5}Jghgu^{l@@@2FC9t=u&~
zUMxJCXGk^ZB;Ow$PF)8MfY{+EkE5|d`c7wtsJ@)0Y5~F4`-x~maO#M2t;qb!T7P2*
z$C`=y(WQbpM(zV2Sy(KD3tc$%8og@CObEgi3Q8JI{9BAQTaVy#lwiWbi0If$985ZP
z>E)LUvA`W=e||VCTqM7cAZM^%G(QP6Pw(Z@s<Z_e|7fDkl5A0IoHB|Yu>k5K{QH@g
z923%d@Iq6<OV5d7+{A(K;r$xq!NQGF-Yi>gBARhU1xd?p3(m(Xo_RvGW<y?Cxe+S>
z>Y0~_!sl;W%1Ve-QqJdVZ9}vruXGgB7re0E1Dc*ix-csJb0_IqUy-NpqVJi<^Lw@u
z*@^izN6pstuonoMCC3gsaVNu);q)ESltyoOfsgCNIdZpk^#zt*ECe#1>~ubjo6XMG
zawo%D4CTDqbdui>i(^lefClF{$X@oiz#rc&#oL3|M81L#eOsbz$yssvC09MgZ>h=-
zupC`CrD=wr!!G@Ow9(mfBN-oq#up=|2e(iNc9Sn8-MAG2evzdNI<EWVJI7`Fy@_+0
z+B@o59!l=WDdO%LuTkuJdGO57deo|u$f@{V`6|O02s~dthktcUXL<kcXRCP@h3O_{
zLUl)5-SY8H>U#k=W50GLe8PN8Fk79|g=yr#cl+$-Z4yrYM-FZ|M8q_W@$5!%Ml)23
zq}n8W_YI<xr9I(auS?{d+sF;ny5>*-_L-#Q%rzgFkKg=VkwZ5{9zT9dpIkjm`~P3A
zl4QO!x)&5w6n&yXI(Yt~Y+t$fK4B0-swJkPHzNpt*HHuJLU}q$6_rDwahtwR9hP6`
zb<Z$z5m6gCq!hE2fK=BR<xrD*?!;_;(_D=JC(m<mEM^i-c_*?8QZ!eZDaQkHpFGSt
znPKk`DUJDgN-2@c_L8kNW;!{#hXfvMetjh_Ssi;Na{AZj;mAU%8nYn9&@!^iu=UD>
zE(>&_4UKf7X|gQ181;MGvOGn5?DY2dx6N97jX)WWr6NtEXpG$#fmg$3c)plXYi~hB
z`Lkvha`26xDaz<y6~Aoz+HB2JS*6FaX#c9hJ5G#A<GeIogvAjnpU{ZggAGDBGU}PA
zb1;B^349Z9(Gn5qrYE26yhdxsmjQ?~M2u-&GF1$e(VR0agypX`Q@yR_v>&9@*b#~Y
zT%N-%_^tX4zgHf97(Us>ivG$!N2fV1F3+W@gxJMkBmXgDMQo-x`ocE<L1jPAFb}ak
zA;wWsJ+VOmm~F)!o)RjN4pAkJ+v3g~q$Lj*IS2FBGDeg?uhIHANm%O3SL9a`Tvl=1
zvU#33rXyl5o9Dka!a{5K63DFQgF(#NgGXZ@cnb@f2DWw6y24fcBAMZSQWiVxidg6S
z;R+>g5!V<c-e~!X*d9ot0I|-d0y>V^N*R$>h#j*z`V})JKXDy^zJu)muXB`)iLUbm
zKT6D+O4oq<tQGeis9Wz)a1wWx_Qk*gVrSo%ary|C*g)G$iLw((d|NBKs;=EvXlkXo
zgFewPf<S$8I=9d%q*1+^+{Up4gYvz;NRp?0!kIf}<52nQ#?k3pC3c$UD~G3bN(yD-
zl`C)goM1!!Z`br?8=}659#TEU*yYjl7}$R(Wy=~TZ(u);@+C>yL%`cQeGxM=mk}`*
z$h*(yEl1vT1=D@`Y^&S2)r>sN*`!vd>B3}co()=IBhR?~g<{?LQQ(G~l9+#)NZp^t
z@%_;9xxd1~(%$<@?Qv-sGP!A=*^eNW=leGT5a9h1_#rs62DA01>2=X!+q&E{BHqq^
zij8iMZOF{lnWuU^t~Y$=U&ZL-864SvALCay?}+8zcR4Y{2XMft+3MiB8AaVOL4PC_
z8^}#eqTaS#ajkHQmB(Lr6(2O(B+1(rs7&__M1547x$g&J`y+?hYB_V!)><ikd{=X{
zs3qQ`fj@p9#PUyK^dJ`ZdqIbX^naZe^p;<cX25K#d@o-xP7bn-+#GB+b1n#H`Swk=
zkS*)?IM}w_H^L4(OBXoXFC!px(2p>QO44F*FCvONdMl>!%frZf_T|U)HM2B+Nh99Q
z3V;K?juz+i%3}B-oJ?AMyY<TE{zK=c%kCu@$3bRrAdfCBD*{WhU}40c*<zI;W33e2
z_|DDoj?u=l=&RP3<j7V!KiyiV1-5j=8gCpEG9B&G(}%^rrZcCmG$=}MT7bRdixb-l
zdBv`+Qe3+nbLF8O%8x0I$HZ(kS!t*~&_9&E)=Mn+5SEBQu5et~T!RbL`8fz0Mb2u5
zL77}E8WQ14xax;0CYfW0AI|E)a9OH!(qI*W^<0a&RQ!QVXudvYM<=47DwxS1#|QjK
z9Qz~5^_9;QvC&MO!||1$Hn9*8vLQW)z$m5?cZ%Om^=oEYZyQX4M&t^n#0{Kzelk*a
zSsDqlbhT7u+Vr@l(dZ&@AVdbI!cV7KHFt6yR{ay5AXL_(4gdJTznvEAe*9(sK#4{}
z_>zKNP*wBVUqlv27bBiE5;$<}*B8y!5f_LFbr>+gY^^t;G00b1Ff(rAn+>(za2nIJ
zFIJ-n#kO6%)u0mqhX;_EhiP@umKK5US7~KR>|)3(?kS+kVsz1Kyy6db;tc1mk$$HW
zTxvhox4IK!Ee+)jbn!N43E*4M*XR$8Hs4LWhkBWByU@u=G7(>iMiitnlT{ZY1+&%q
zD+j&!YtzjIQXbgEIX^`}VHe43lZrQrJ#xM_IY>hJkhTot9AJEU`QHd#i(cnP8lT$7
zOSA5=O;q-5k+6}pg97LOh67%_b;>6+q=B&LpwhlRafdnnaQ0#`=Aob&2k}4@+bFe~
zC2SGQ)~rpa|4BINTgy$4OPJQ9e7maREf06Ppcf55jbe~W95O?(QFVqPri=OlhuIpL
zPiF-!pUICbMk^-I^KS#jb+(m<aeVedrkLz5*NY#_PArrp$QKF6&Ss*feeAX0(QyYo
zxaAqxJs*wAr_YL-{#%jy#_8Tcs>3$r%LFYn#SYx;nB-*=)fN|<Outy_(~oe-{7W+Q
zwDfAD9F3&*G5bgTBL6>e?*nI9Q6KpJs_wZxr<<Oc(>*=V!{53+4KxFq3xZ(@N_Ep<
z4<fnXpcA5a2hp&^XHZc=jnr)#Yz-zCg3r;I<N^~jjwYEHHp??^_ApLd^zr;mTrlK4
zv$j4q&#<m<)-^io8uPxtI`{UUneKbryiaz2-M3Et`PHv}^{c<XsycOkbEl-$ys{2L
zy_4#K5l4V7;hHU=81}p2{WFGrDDJkBK+u<!lc#lr>H)d3eU#;#I(Lz>+v)~AQ7JMt
z<VTXeNYz%kB;7G^pH6YJAdBCMlnV^smKuNpOHsPsC)tIh-LlqcrRWAEd(eD0;dQDD
zD*GFM*6`-p4bw!>LpIh7Qr6Xyn-cdwSDu;!?Uw#07c1${d*wpQ3dvd~u<GmrPCTJH
z4~~a~wXLT)?NuoNG)Ktf?7t0{V-DS<!)G~UrXCe${7BLfGh4QGw;Xes-BJANBwgf|
zYb}^V?RAB6B}$T^TjyT?<Ds4P|M3a0nIa+z1R`6PH4;UOhFaDH=A=P_Bb+7s4ivS4
z$OK@PL_9K%;fZ)H1%OXD7CzkC7Cj!sInf_{UTnTczqO2zB;hJ8HZCBhbYo+e0QP`q
z+C@fmaihLg?0-go_s>ZC{|9Mg&bv;&y()lgx<k8&I!L~4={%A6a0mvib#ax!BKK78
z51lIGG>SHNeXeu6)hA*py2u?*-R+NaE~r#8DiPquF}xRHxGr??w2Dt44&1aMhyz0^
zhUMsvU+-s|)0waqYOJktYiFfY(R>>>RH?&7HJ8XaTE2^6LCv-}Gf<e)Z;U8|s1rS5
zu1IqQo_Fe0ZbK({Jfa2l|7jqch&-%xeUXJCwBTR`A8uK^<*3WNS6aO~mu0ueLc64e
zax>JPY`#q^N%{JbBStX&?E0tT;_#p}0I$);qIF${>tJn^bdk;qu3H7h3cvV~N}<vf
z8E;9hbW+N!mB1?;Gi<bD7=4Y%P4L1YA?>w<g5(;eEBuS;>S{R5mRe!JCh=^SUkziq
zUz-iirY#e(A{_0szWsb-_g@JLslFX~7iS>?^Hl#4#n~L=v?KDyMucobv#@kCHQ8{=
zGK^NV2Q{nV6&y7mpjjZ9+rmaX@8V*M*ZfwJ)rNd1KR?VeiO%C-!+ag4!ZnRwkb64K
zJqE09xaHpdcio7vkBHx5<HzD<;d);j$O-RRj{l9hiaM`q9U#fKo#AETIv=dxUXz!e
zB<B;7aDn!WgPr7&14-4q^Mm1fxhI>K8|@^a-GQwXZ9EYW?@I9MRJC<?NF}Hv8fsY!
zkXInAoV*_yDiS;^WXH-rsAc+!L@vI`NVTz<s`)-A{sle(`p`DdeWvOIidVc%yIiaY
zVSclD)TvK5U{f~aA82n5fM}H#s?I~R@SIa-w{B0Eo||C4@aH7*6Q)(WIF0z|&1qIU
z0Lzb_*^d~h0)JzSY)1wA_C4!blnQZc!V|Opt}BcjIZ&)_k!d8x$|t|<d%JP+U!K36
zc?3SO=pX!{_&Ifa@?yKy-AS_M<{+bQ3zC2AN~<G^)S8K(=jr!d;oY99v0?jf$k5(5
zQ?$LnnQRCKCcH{hX)P8qcBjAVH%juB$)v9Dw%Qs#T>%pQ*ygkk?NpawV;QTw7C)SE
z=rWG?zr?U7zkyQF#e?U`@|QSxs^UL9_(&!$Q8_#j%Q*2*f5>%BF$VIM<KzLlFOp5;
ze*Ig9BdZ@&e)h6DazoW7O`Eufzj=Srnp#NOyzvt@Y<nXppBhM_Bu6Rmy$hT~{r(lj
z^sQ^s%9v(OpK|?YMD~9L&Y_?N0p2~0`_p?f3IF+&RQ4SZ=QK!>5IPbE9@}dDA0H4C
zD(Da6|GFjaM!L=|8xuM21+@N!lH79pWlSRPcM=XKY;v{ZY1}ozIkvJ@xJOB=liV`w
zFtFdw;P$DmA8H=Df>#pXsfcc>E>;lDf$rBvs52|gw>k2z+X&jG-VWk^J24VZ$b<u=
zr6L}V+(6`jzGBz|NY=^$xC<Kshibt73iBQjSI_%L!gsPJR-fd&0x!iY)L?A2C3}#$
zN;qRI$a4ejyj?-a_i1tqzk;O~Fy1YJz6v6JuF>|<+ed^;%Fq$1TJi#8ZtaiaaIXH#
zU{~3Rc~H0%osw*wFSU|>wQ~O!dW+v8=204V?LOICnKg%!$u#ZLsG3w)xKmdE{`aJ|
zv?j0;Jr)T<k@1!OYq~-^q#dzc5tjAu>D(+RFq}+je!U5vM?{~(qBaJR0U0zkbpkp`
zSRX*pE71;kEV!8_V^POmKBOcpPVj}MFa+VjiGRt=f$g1p2`r$F%F8s^wVmsHz;!yt
zE#?))N9wsggBk$(z9c?cF`{KLM=3`y6;lPpu{=6XetA(DygQ5ot$kD@**iFx`KSh8
zpuSz9uKBJi(Zz&L#1GQ)gDm%*7;?N%fXZMXj|KCK^(u6f2nX9t{=7!a`LS#Z1H{s7
zML+~a?7~92k-Z{t4Kvsd0VtUkyKx1gZagItCU5P;)8I%K59hQFsf)CW<P+l?4-~Tl
z&B;#zcl1d>gINh75r@yTl4|;#Tx)>@ev44Oja@BxP?^m!l8$z|4GV9Q4EBd?AILi=
z;kSWBa~gSGq_C<bO#>0?BYklZW)&1IA{DcbPbJz797h?LsKaNQ{i2MQqVRsNs;w+4
z;^)*~Ne)OO#Iq1}97Og!6xcO|vEI6?LvYY>iW}5W>WNx{j1)Xa*EsWFCwCM<8Y2xy
zn5D)rkbS^lU>m9k({=1U00N!DFT_-^Kn4&gKMrB39o<T~@r%fK;e(&|SvAg*eacWi
zmCnR1X{RMxse@2ctZA)%RPN-h5<*~b^}eqD-GG;-03TEDhF9=W>WUHr-3chllZv?w
z@eACA6p)~T=6bOTjv&%P7(8_|+_$jw09S<jB{W~8P)J0*(LN#|7v!lE)@)k)|FX<!
z+pc(g^apsnep*0)={eecw}DDAU>wy73#R0rhvT;d^JHJSDFv1OxCR&*&WVty$0QvY
zp|o=yB1VZEz`r<=YuC|{_`@v@8+Bx$R2HE&S}n;2IWtQei9IwCHrUv57Q<Jwpx4Wh
zbHv7J%R)o4@JbIJthOP17R$I9zh3WZD&55m6U~#1_)lmsK5~@~B|GLsH+jo@Y3rVO
zga&qn)RE&;5CVG(vcT-bX}QtL8Pi?ZAmv;uJ?#6|40n>;WoPYyQ8O4`?_2iomAiLE
z3Hb6cHe_3yCWF1_3z0xqBeX+R_|E?}g`!DxAZbc6F)yw9*QV$RcQA&bwk}PwzCno|
z-Qc{N*n|2tnmBhQhlE~>=<20mCY5C9xhxK}UM}Z4sa+g53a<(xzcj{-zXt^2?X<hx
z@mL{xa9fg1>=mdCbEvI(p|Ky2y3#%5uL_grW;S`hVRBvKT<1nI3k7~bQTIJDR(vin
zestq~bWKl{SkZa;4B6hyQS;h^)%;odu0!0yQ~iMqH}5<pnbU|}fk{>5FL{5G#AF}j
z_%|_{BtD;Sw&_0Xt}O0`>-mgC`V%YH+-Pm>i)bPr{{Z4TK;E?KRe#KldWK2+x9?f%
zGS*C4Q$WJr^YjN$LaK94sqD}!59UU8qQ%QaT=6H{PnwpUH)=-=;3>cPLpZDbwuGyh
zd%wvcEp`=U=YJ~8)E^_Z4}Cqz&=G3_sA2HW#O!-hLw4MI4YP)~uRQtz!imtNyw3Z9
zG_ECR@uX1)&8elb(a8lI=&ixJvfCYOiW0^|CGNI@8rtX`wN<xaYtOyP`j1gd%nG%&
zq4lN@U2E()cG=FpOU&+R8o^U!vL_&@cz09W%RNT2pD0=@x`oMQ%*hQh%OPRsW-HT3
z{M|Cqnl}9t8&a8l)xO}pCZNJbZJiGnZq3Z}`REtx0WHQc&FA*(q<rbMab|d*MtuHP
zC2EcC?m-h8_GKo2{ycl9(;yY&Q}30De0s~Yf9xZ?ME3k#7AogXW`h$%Lf1|IVw31X
zhdXp<$-A%KD3`zECnXX&$NEqFn=y)_7o_Qzuf3S~;OT@c4$dp$eCxDXoBtcl^LpWV
zNjk4}gvB^#;;G5h>8A2+C{zo&`?i@`?%T5?cK=wzs*iq#L*y;GuBzip-m>z%Jc_Fq
zr1id|bk;$8l&H4)7^5D1OTK{EN2^Ft$}Z+FoaB5dDb-|Zcbd9knF3c^9&iOjM&Yb=
zcE_ji?`k3(qU*6_-p{5*VxhfnnvQFu>E#0f1lokYtg;9Trv?0oxa(}Q3Awmf+Tj6b
zRM*Y&Ee|Vdn(V(=&Yr$15%==+?Pe>hWD74|){`sFYLLl{ZM}F-1sYZh$8S7wkpYZ$
z-q%2k-b%?)Mk}Q<plmD9H_lC|rOeOq^BSRDo0NR!q7U;uV>R2_7S@rhB63R%W6=n!
z8R}B-(IkGy$6J}h?w}ZS!F)d6S(?MH=uaUK9PypHdO+xeSJ6i@JqqWc&?c3hO5T{@
z&M9k7E+LnMcEIb*zk+Kt5M`QLJV(5$vS%g)Iw~RHewZ1BRUc2?4P7kNsk4iauBN_e
zy1W{lfJ{1VrIVeZ-q4o>a?>G+Rh^+2x{5_oua}JI+o#jfKUnk~?gdgNauq`oVo4@C
z-I2lI7bOnDT0k{u2RTihsjY&lt%3hsX~#^G1EikX*W#g9%Gege@?!RD#?Qlx-9zXi
zLA9?1i!tl8C+d{bmk`<-m6Nf=Tgp4~-ym<zB{Bhi;MmKZ#ZqZ80ur7&ybX(H6IERI
zn;=yZDZx?t9E=lhJ)EU|NWm#?0dS?xj*PqtV_sA?>xHzhjT|3rdul|l2Ed*iw?)9~
zlE!0l%UbAS3M}iEyrS~Dg_cg=Qjq$t2^R4=4Gn5AgYIM@D-xeR%zl@Q!OvtJ`Gc*%
zcbS(mt8tz8Dpi<XEHTCF3LVVk2CC~*5mm(qXezYApif(ugugb-@XQj=gi5hYmbo;j
zx|Le3A01#--G}I?sJT&AuA#+{RgF-zzz%0Ca556O-yki69GIX}X;y@<>hMGe%R^S)
zU<L&{%86ag=pxW+oe)ofBmFUcKtx6LUKB-vu)68hI~r<HAUcrhTojcbzympYt?<_F
zU;>3-MGG(r+wqJL$S{_5r5Yo&jnMGKiPKK;KB#X@mf;YqcNpVQ%#kr{>X;K+Amc_2
zd(3TI_0nptkSL2xLx2G&Uo3f<G;CkH(y0F$Kx0@NX}^^qXOjGP&(;LO8Z?gcuAjv5
zvUo@s9k5Va<1u5+U5eT|WyZ|}v!yiHyC!8MDCyr4o8^OEmCL8>0zSSWCHonoWE(Oc
zrEy#;CphbU2tzk{7mRPKts$WnIZ2%4icVfFYO9x7t^s#8ovUpPuKdeMGC`oG!EP&e
zZnE3jJTxP9Jk|vsEFWqgbx)LoMsTKe`?SYWll&w<B4^DL?wu^(ZB67GAxCYUyqc{I
zCqJ$<(Md`FEoA+nlafc3jyyMp&V65)!<v>&B@FF<xs1s>1DoG5yo+JSo#L1_N?4BS
z4_MYK&l35C{ge+OhctyAFca=z;VSO79yQ`0IVrM`{jE)AiJ9(u!phtBB&ww1dLJ2n
z;R7PGzwLO<a+6#&dP7b8x5v`#lS64be19r?=QmqJU{B!P+nB6(M;k#<TY+qdDm!O*
zv2q`k@@&TH!B3%+UjBE^`VVfAksG$9ZZ9*Lptu@?-BvFZG~0Q)|Bg)XUmK_mQ4?~n
zIm@zFKNiz156FG0V4-svH-H8#KbJB+W4HAhrG!M%-~3^aP&-4yb)U9nx1S08+s^8j
zoj;sHkKgVUMXE>ap1E)GqA)aFE0pcN^KSQpyPrwLE0ylx=izL|E0WS`H-B|fi^wqI
zzd#QO&n%RDtkN-PZNvCCZ%Q{%8C=}<oIV9A?E+NG0Lv`LUIJnLRwM_(<8JH3r#7>P
zo^Rl@SWeP~mPup_V!8AdhPs0^IIl5#Ky3lUnC#y|{b+%G`&KWxST8rUBrbk6zDb>X
z;17fBk%}aGLi|<Zycqxe(m>3;?zV>JDVaRq-WDv#bTL)r?jNZES0e57{liKoyjzc<
zYrr4@|MfIp>io~-cKV%SD$kY}Nuh_@D*5TwOuhQlAk{nx;m%W7*dG(A*R~W@>b%=Q
zd34w&Up~X;M?Mp5xMY({<}MHJ(Jl<NgA`FFow_tR?TeNbZmM^yKdFa=tx8HUdcvPn
z{F457xE<xpC^kxRY@FSHzkhHq`-}M?zHetD8g8;DtJ>-!@jF~5PiGS&VLqhtoY=KT
zi6ve}bYD`F<y{agcNHNpzD>S>T0ZK`j<DTK%N<mizy#SQr8(I#nvS?(hqByP;G?$E
zcit!R#MNz&bv#_4J(A7J1I^#1!yv{p8)NHmB_(@oOO~cTC|jxhd|C?>m4Z{Xwaj(A
zBfHArein7+V0kEY_d1bZ^@<_2@b#%+UZ57#6Q4E?piFNy$?o)5oU;+3yOE?n-x;FU
zMD#ja8lvs?0?ib4jOszsUNhHMc&T@U(Sc9$q^JsiZ-T=e9agqRlrZJAc1=S-{Tq9u
zZ#N?ggcdbY(U5W4<muJHe$0@Pfg$U7dW5RyHZlvEyMek8lvhGj%{NdPnVC@6dZC?e
zGFyipG+TXC8jb9Aw~e{ZlsY2GU_ysY&y-&#S=~+RurLineU6SdA!f?VLqeVSEr_J_
zTRN?;Re23fC%As1og!4%gqCFncJ`XVs^SMo6$p{rHF0CW+2|H?(FSj5C^1UV!;lKo
z@SBvpOBuT~#HndqLEkM70gOb6)zK*#l%b|5rEU-iOw>?1hM%hM0J4f&v*YQbK^ae~
z@|;lhl%p_f)E~h`)A%r7bdm)}(X*GKH5eG@=d@ISNX<(hUoj@-fX}dhj(L+MK@FFH
z_tk2-O`KGCasZH>0a$aS>@)=S2Mo)Olz%#@^?ka;3OhUM5Yf=?Fh_I;y)~f7F7q_y
z-K~MN<eltSJi{+GAQ=oX%tsT$@oTZ<DT5s!#Yg=0wj^*_uRhxe$jthVco0F9jzUml
zBP_%`u}g#VgZ#*+cz!|ZnmFi2qvQp*MeM*>ek<KWr9dUP2NcpVc|`M=A*LFgs2G$3
z!0`vn**cjYh#nX-{6Z3VD;rBYPE>#Nx;j;N0{)TOyrMh;$9{$(E5|qW4zmXY!b6d(
zMa(5<FokD4gQM-BJ2(yYl+u!1ygHT$;-L1a-y%RZjQe&%p1^Ff6Q+o+<LL5SL0`fY
zsEnZsQ1A(czQt3lCe`st%LI7@PqK=KwGAQQP_JgkXT8sIY^gD8e4Kz-nx%pXGy?DJ
zGD6yormo1EzGW6`wrXIBjtulL!88)NAo+!YGhMGq8%+)gGfdcrqI{Q8JJA}{Yizzq
zeKEM5rMx61Jy}-Xx5cxYY0S<=j5RI$s(IP#ZmXAtvY7D7$%y)NF}8?&p5x2o1`Y?Q
zDR1V^;AV*y!|SY``IE@khWyAARC0d?ucqsQzdP5(ZTB@3>;$kIjOs#;7Z8k(8w*)D
z=BOsD<+UD5s|5S8@FFL2;}~0Lr7Sr*D6R4@i#@NMf8YQ0e(O+MxjMB&w)@j-a2k84
z8=1*)FgAMJQat<EZIvo5bXV)cl+`N=--u$rF()qX^FAE#(PKi+ww_b3^dC&<{NGgB
zZDmLu`90QWUNExp86#HCqMYcuKNMqhH=KWS2+I;&!uAW>X~+MT>j8cw)4H2EwiLFe
z&CGstt7W$}30%pPvD+FkQClUbO?Tqn^$^^lq^7DjvF}z2H=IQi-?J$V=`W)N&RZ+r
zyJCh@+W~Fk=ly3v?+GDC4@O(Ij#p|+|L$fXQZjU`bf~c>$-c0!Us`T}midKE#?AjS
zM-@06n|`*RBWtLwjSrH4P2{4#VKR=|I(pl9(Kq)@mR2V-sQ0z2pB3M1_!z<Ty8vmK
zp+dQ_o2JCRcXJk=dUeHItKrlydFY2?=bzyG`=35;<Jjt6y;0^zYeBAExL4dcr^><M
zXHJrb|Dw-Tzj8@c>eu%t4{YC@xruiV8D<_mAx-ZtiwA8$lhgLyiBw@ZA+8z>vfCPW
zGZn2D_`kRk&bfI>Nrg6cEI=fw0ofC;lJE$%M9bK^=PQzZ>2j0CUGTwAiQGcdl?{}E
zip)Pf;L0lTUJ&`yP2S%;AXClvoZisf%-ks7%4ar>RBqUXjG?n{|K^IE{$GRCpKY)i
zeWf&CHSWZJ4P5a1quM$&lG*P+#1wTspsYDX9O_Tq=)2^Lh%n6d`H`gME{tb%x1?rb
zuTPxaw_~6{C3{BIR{yz^=H;~?Pj*+ENeH*Rm`=C~wdx1NyeZAniQB|@PPCibPh|n|
zi1Xo=4d$V%?<tO{Ynola3A?TCxI@BPBEVhD^>cPxj_7Xd(SoNUq?`FIkOPGV_YpMb
zs`$oh3JA#ZZIthV2J7DH+xhLc414Mm=Cc92OGVs?eZZDY#}4Ki5R^ZOd%0l;eb;}H
ztcLsGCWh4pb@fhLv$;4rWNk&paY)#3K!SAKFsafJ;|*NFFB2~Z`(mYve!UFMA6MOK
zHF&lyxZM=UkUVM;U_6b*KtC%r&20zbZtHVicGNBjoOSf`QrqbV_P@WD_}9zG$xmDs
zQu#$U9lkf>%eAdzBP^TEBca+Dv#xc>LpUh(;+E^E@5c$SomqIpR_U<R{aKO(N%<3y
zprGW64rEmCmQbfROqcLg{3(9UVW>z|SOrv~#5%6kpH78}Oc&o`a7r9VxaGyps6}0T
z;Ybg_IWWUc_3$@g%!6B3*NAw1w4<u^rvXxMir<0_SH+_9U!l`cddV0`s=EUeB>AM)
zY1Y|oWtDo4h~69g*=58x=IF5ip%(UWer)m_M+VPT!7-gq$?8)3SVHqk*h?Z+A7^>f
z>&b8ujB`sgqAiF^lRij!b(XwuE0%#A<nhqaoE9Z=71Lr0huB9R!o6(!F1pq<yiG#t
zG+3)LGNnI23h)o985A0?g&y@;kH6K~nS#zLJTcn9A>qJh(3U(p0X?523AA|-@j)oI
zgz^z)Mi`k_a}k2t(jYl|gt{CNbD!o#l^Q2v+Q_7pJ*u4WGZmhnw_^IgMj8ik^aQO_
zmUWR;5Jx0v-D4_@SSG+&4QWNZed3UxQ&ANkI&n!6t}#`xL7g*6D4M1Ek~#5O&K`$M
zfmFp7)R8DPGNbmcu#d<@G%SQ^EKfY;Ro8K106hZJ=>)1y6(1$2%y>mUP&iCb{5~A6
zjL|zyqU%9zMVzVOAbwGq$bhpF^u@)jLI7nXjzF;kMK$%&fsu7mX|qhSu$599K`H74
zSjw3?;Y=;-0XQqN04b%lqT~#8*#6_S(0%H!D7|0?M2CXN>RC|SBw#F~T!Un=_-H5N
zluyG?OBTM#y}@Ff9;4K5Vy<APiD!4vWWgZW5EPRyJUbqqUkqqMx1o+C2o-fo3qaEY
zMGLZsD-;C|ZOD#aZ#Y;6Q9Bq=C-`}^PK}l1Z3@O|RRM}J!8EPH$E&aPXvY*<P=tiU
z7Zh=cn&=+8)3u30W+cV&L<+tq1cp{cQd%*W>L{GdMrBwoWh#=Jd{8!_WcGwW->2XI
zx&sNRJsuY0kt=<+P6&X-4S6C=S;+;k!5b1m9H*0m1w#ei3@3NVwD^*<i|=D8>Y5PP
z@=)prkx)$b0wuUC*&63i+5sYUZ4v{44I)L+>e}H<RA#!|xj;y7s46Yc27-~@#PUiQ
z7?DZr7jxtWHD^NQs<{P~yAJrpWQoU|O|NweQ-RQgf^`g_K?f0SuP#^8;%lQ2^#QA;
z%&{kp7@&b`!ljJvf-t~LI?1W~p9*E@bc^dcfw2;+L*-vcqZ8D5hK{B8lVrPs>l(Tu
zP-Uj$(mKGmamYffMWO9p%$vGb<}Kp2(f%19epTA8?K=(^4o6^sqjt4@yFHAjYDENx
z85V7AUnS%C1w(cR39nPvamTy|EIz?UyU2`_F~v>)Vx4+*htLkz1lr&_miSyD>gcm-
zcI>LYD<~cBsEeEvixq~GJlb6B`3Q)kt<KsaDDC4ay&kXf8mNrZato0ulH&&y3$0$Q
z1&X%~b*u-1A|00?K6Rzau5U4L&}W<|8;!UO{6=3eHjSrKn!4l#kTV<9lDf25Gq(6=
zcm<)S8rKm`FI?9Yg0{UP4;s7<@Ee^X>hf+zvc9kqQ3V<Ul&<UWqhr6<p0h|K#x3#>
ziWZXQJE*lg<OJ(T+zKRIBH4)oKUj}?5eRTn(1kT+rV7>BPO|u@UlN}kBeX4x*$>zh
z#c6<2=~)Jfn70u<&qYy2RZ2bD)Cf`T*VSGJMy2#+Whzpu7F>JfM<MVEXsOSqdfcuV
z@aRi|_6I(4+?lfI@Zt%~`D{Ipb-`k8HSH=D1n}bOJhW_`CeTEmw!w0-#^@l$pwM6P
zfrlx^E8;fG5>$-q+PW7_EI=6;Ck1De4fRwK1nI<#aaHSSFwJDV@Ww@)eyxQ$yAILm
z5JhU@9*5me2d0>wA4hh;)+7Ry@6)`E=+aIv&=_NDA}Nd1x@Z>36xMELA>k-kSX2HM
zW!|ys`Lzfwq|O3GyPs8D6*q-h)FbRcrj^B?5=IoCWCM?ql2t(}gr@p?Z1|?Gip6*6
z-;M*uY-sb2vpa-k!AV8LX%_^EiV~M++ofw`pP@80p*#60IJ(?GHg$!;u}M&b29ex3
zXgsBYf!zjG;R5uwR;nn3<X!g0A=`mYkJoXpcm}4w<MxTO3QxBpY*mM=<huTL)C&uF
zUcwHeS<!<t3Q0I%li}t#HCPX(ED+YZmi)YJ3fJZ8Llq9^Q}ZcGL&jV3ixs@r0byGp
zS$^F1(rmH)tZ@?75$n5UI=pIXo@1Fo;^&<!Y2tM0C&0r9M{nZ#p`yzIE1Tiv_-v2S
zqu=_BCrd6#?Z*pbJ<g!;?O&njZnCT{KL9^BUqyZDtRKEl$2N-1{^))X-$b8(5h6PH
zK?IUgCEjghYn_dpaJtmP3mlEfUjt{C8!x*)D1`S0ow2Nrs9EcOhp8{Lrc|#d5q>@4
z5MQg$ju~m`LBPWopd-;97G9y1Skk>;<t^cBZ2IKf|0c#Ao#YygP5m-|Oz4na&SKWl
zQj$FKYi@9~{-F1U;}Ns3XO!xhCIX6Ya*?dw_7Xn%o|vP&I?$~2)f#E`@96Sr|LL`t
zPf7jOE%b<&IXQL?3fDy(AU&C4&=!>+J%x65#e}#AdnXw&9A;JJ^w(d|#jMyaW$@M@
z8ZhzS*r0jt<}{bVa}sfSTamsJNMVZq52YkM=hRWT>4?}+p(Q_mw-fhWHuhdU;6^Wf
zZ&Qx=^OL?`KeZy+50QN1WDXv@&o=6xH0gy9=mnDwj99m0a*D2O0zrSt-Ay@ItHgaY
z_3Q<q`tN^+$(wGtEl~ZY{whY$SHKb_o8Fzs?O#FWu@wH61ezNt{9g@)&*(8twl8UY
z{?BRc%1C90+e;_i8`$S7j;HE2(TAuEK%{UziyYtn;vgG1VsE#<D8Bk%n77=vQ9gS)
z1zp#6^ou3-OB6plDVu)vjm>a`&ARnKHQOuUkQ*2I+fN&DSC^@~LF|Z4syU}sAmIn=
z=-_{P7JJ|9-tFD>0U06p;{IPF7e6*YQQem0{_E$;$yaanQvH_9e!NM8?)$l+P~ocF
zGN(RoJ^gN%`bl#2#W&QdT>rZss1IKH9qIz8n%rIPxH#Eu*WvTS0U4<>)0;jnbQLEP
zQR|BRnxh2g+QkEJCbtoOi*oxVri^tKhz*_Kz*Cd>%+QkYDaVfZN#-3b4tm<@d#yZC
zO4~7u_-mT*7w?j>Pt$XcZ}v0*341o|q#afge;)^cN{qMpN7Dg1VlR(}VBJm(eOsAB
z<|^w}-?X%bj%*D{erkAr&6HLIP&0tW^~ZRr%6{^`fTNtWF!fb(z{^u4@Z2fsw0~JT
zEC&jC41`~iZ%M7+OYIvR>Uz$#*p5SqbPX;tGRCD>$TnY|9Ujd~a-aN!g^TAt<X>|5
z6e{{l;>Y=vbXORa_eBw`isYzQn&H@*gW&816SNu1sL)1va3RqO@F9lk1eXxcBk<#>
z9WMR@WfHp!&UnNpL0EbM$;NIpBC5tKj}>uL^VWr8H?MB;LUD)b80MlGO2}#vbe<fO
zUi9f<34zLZzjnTbc1p1kpL?#nk1-udt0iXQaYmv}ZaTiX*Wfnfx~t`I@X{uPEc{BH
znN^D?FlxO%oEkkKsBAU*YT#WA^QsOec6t6+!*2U|p3X^vgz8uo+AFmZlvP$C@;Y>_
zA%uJwkC~6*7$~_}9u<CIs!<ghbqRMbfIlBc;Y3VUFM50kq>m7h0BI=m>A#eAPPO3M
z0@lzr5NI6p3EOt}ew2b{frI6`->5YLC}I<!z<^}tb=Z}n`shps(7sw@2Dox*(4jo8
z_&AN7JSpDcqnFgXhyttk1>6b2K1S8hE|6s<nXW;6IYjQFhf`BSqYRe()q7Q_ZHwy{
zB(1r7sZ1$W)}ilpJ(Tv+s<tC%iS&z;2O@baPW_Q?-1^|LO{@<*yTh<wYy>gci>0qY
z3{OJpzJ(pt=s#H%J!Mah27_}vb+)tA8|2_}bj=sp#IbJ3!E{%Pj}c;Y<DR1aDtK}F
z2qtq&BuSV5#2g{mCix@?Gul97AtLNKjpEf!*-v<_1v9*8*s{cGpOsaNH6e_}s<dV}
z0i7a{>26pW7UJY4Ugk>Iv^q>CirC5EK9P<UZzeaSkt>D-HOTwydM@K!q~XYRl$eTC
z>&jJnrxp$`^dLof;j3bz574V+52}29j%Ng_9eM@Tpr~kV-*r4JjAm0XQUkfpFx~+x
zPUHjXGK6}y04)*+*hL!GXB!-;<^y%B3;%`Ms@sSGG*_l=C;@Huy`iaRSlepWD%j>O
zh*kBLwlg6aIavj3$;(N28Lp$VWQ|rSFE&xmaXtg1TyrPGr}x2VypM&V4=TPJZMaD;
zPxfoG9!Mv`E^o$SS~mY}Pk2voA~(a|(}+XQA3pNlc-&8(9(7Vjgvm__w^)%_xa_Ke
zR%D17oBgqlyQ+gJ>^*mQqwL`9=2+yq@LZP}Zk(mA?9Luj?8{|*U<`J0$|tUP2ae^*
z3(%};mC^e4V@sM;F58m*a>v#oZ*;iu51^dhE?#!$K~P%<{TUS^hEcgSVFz!Axz#RI
zgqc@w7^s~WC-)~}YS#MSXSoNGNiZkNYKxWqMBF8xL!YPkjv>P8DQq?UEE$8{y?jRy
zn`x@rI{0fYBrms|5JaSZ_u^D$I97@eD}6Jx<xjoXB&d49Lqn!U#A$Qt0l~l@-~M0>
z&o_%Z{ld5;=l`EE8NUHCqkkaT>;#s5w^4}Dve#4RZaaro`jacIoZ41f!_yn&Nb=u9
z)?%z%?4!CRt+XP0&)x23{7}p+ryoth^q$no=vB~q;N{aYc7WV|?89jwG3U8xM(#g#
zG`r~^m_a|z<%rjwLqoXG9CBxGtfUh^;q<;gEs>K^w5oq0dE<^#9!eg6t7(iMT`|L3
zi?{sY`sa`u|D)P${4%_yH`-7-<?J(@M=-tNo3I^UZ`@l7wTJE|s?<B@-+cO?cvEYD
zGX)*Bb#?+RZ6B4nuH{mrubSPvHIb43Lf+?T%wKw)X+W?SjO+2#gk-&H%jVa9P9uc+
zxN*rgF%La`j>)EvnBX5JrGpR5+VIS%%}#d}segnn?f-^J&3*lICuOy%o4qtIDLR>6
z$<qCZ%<bArKlT$Rd-PgSVD{2FZ@`)GaK3>%J>TuQSoTzNr1|@-B<=s5qRTt`9?JO2
zYg2#5Z7d77XnuWrv%K~_BjH9~F#JR%5B2#{Uoc$nGyhf;`}qUZ#n;d4S8HT0rqa!*
zh`jncI!y!;eoifIQ|}MeH`-L`%+iG|>za@ru}3MCxcB`ujjdKLD)3#AE}h_3HrdmO
z{Jhvhzl3d+hc)d39Ki_4Ae8)V1G|O-xyyomH?@C1Id(<l?k2seA=$vDzn8=DeYGt3
z4+TcgELq?^p1EfRLt49)hBV89^Zk7Ch#s2$-zV|NBG#6C7b*Cy9DzKwdtxg>(_IwN
z#BZ?l^4e`Nz@Nv%k);I#(fe>zFJh{{9n0s8Rv$9@1`JQI{{}T<+S<(P=GEAw;f_F&
zg&kCwx6?&`dy5I#vkXl&E9HkzK@`Yr9TRmkDxXiMVp6La%evikLdVMPQ1A@5vGOD5
zwlcRgMREvTR(@2HhLIVa%~+kt#AY%M1?GI_LY_%M6x*5*5B;M_6bO|Wt}xJfkMeOy
z{WQSy2=oUGoMAc!C7je~PeT$AB3R6t^72yvk#l1BGWqx*@kYr7YO7<`6etJbGg=+i
z2-Oq<KS$mkAga?1p8FkWQS}KNm=M&-Yzlp8f;{o_9^4Z8C9G@Ap5@>Zp<#@zE;#x=
zWWcx!CyhSwO0owSR&^ueWK&7k+xVIng}??R`b5TCVytJAH2EEN4MOHXfg55mv$5nW
zslmOkA~G$V?qKo}64dIUB4M4AFQwcPB^VP{3Vsv*;Z}mx%j@)sryB>$s~tlV*GGY(
z?sY*>>9GP~9kF2pr&92#$AL97f#-!%@}p`gK$%dOGj7oFZ2vs%Ue^b3N8>^n3;G$K
z1Yblk*W`S)Q`}xam2&h`Ye4EWz`(2WzHHL2-m3t~Qw4ks>2R(NC`5?)*3L%@Kd4s{
z=)43kl|hImp3?{?D|tD6oAj)j#B))Y^+Q-y9Lqpmc7$1p&*?GjOJ&Z3KEdv>)>h|r
zR8*!bk#n%gXGk1A>jq_<`n$J?5Ob>M5uNvgMG;Iog4lh#BP(N3M-&K&B_`Lpoa8xP
z{;&pYr0<Rt)geaiuQQ|6^N>pT+UQAh>jA92Qqvk*W)a#;ART9Xw$xPdEMlq0s?dtQ
zrJ0zwWf+<r1y6g@hZUyQ>Y<<losG8WDlr^^#GwpC;1Kd+(3+OkvXGbqjT-$t%Z9;Y
z)kK`?)7nR9iF$d2z7I#BwuTOaF_V^#BxMG^PEgW-EgsPvu0se9uQH1Pjdp0>YD-ZM
znnsA{xz(o2ma*C!97*IzJKX>&moV$RK#??TsnpeHH5kqUl6I>Wn8qHEyG%Ax-QrJX
zHd4H3x*C}!zhLuEFeo0yN2fp?$V-JHEnl`{l3Z-cVFy7AFxg_chf4-*ai8g~{w$r>
z<HcVSC(YB)bI$0H==$`<0mY-<8+Kb8=JEo2@H8=X`Yz#3E?XNiNf^6|m)H6kDk%Bz
z2Fh>$L@LeG+X7hN!Ux@LHQRL|@TY=<l*>gfM)97<Gv~2a>};6Tm*m2RMpRoT?&{Q^
zAD1XY-fNN{Wr?|?JQzX>3XA-{r4{q8*o836pW*6URBy)oixLT!ch0DQ(G?JfJj2HI
zs-WKSvln|y)bF#bUlnV)rye@Hni)WLY*Iqb+>n|aK=2D2T$EGuTLV5w;$->~sgE6P
zNcs8~8{X^^ue+_S>H*Sx2cJwy|H`?^gWJVU?Fy^)Aj=ais;|D*H*$<ifAUu_G`~ES
z)0bs9O&=xvw4E{+-a0ZrvhO|gmmedM^ZJ;)=0@^6Pm+PDOR}JqnB7*FCHGXF?zSSC
z9sn7qC_E)S%1aib1LT)XS8ToYT{;DJ1m&qWHvPu$RFamvkqhMiuf4GWi@%v_)yITj
z_Yo_N$Ildb(YO)!oU!Sr_#XVk4-66khA&Cv;Ab*9{JB2#i}z$PK~&iu0P)tNMmr`r
z<L4uOSTy~<9U<<vChYrB(R+ZFz@GQh+r5LXZ-LRhkd2EUmxyV+PqL?@3U(GeAEVHp
z`6zNwEfYmHj6U1&jrs;LpLsONZbdQ^UwWN9s1duu0DO0LTlL!?^6PQ8HPlBd)5-Oe
z5NfOOKRYGq)n__EUy#N#qr=(rzt0@%b>-B&Z3n$BDfkEP4fYFX)#Ra97L$suskR8E
zGR!o-c`mmol7)S;MTyARLFP$>HLJ9+2i}U+UdFca2ewhw>A@)a%-zFIVCfo3KJgl{
zxooli>d|RAxL2ma;g=hC-Gv-NXqE1dpL|L0wvvB#DjWUVZ0OQI{#@!wq&u|8Ozqn<
z^#IyNt!a*5NdjgYVwdp4fuOI=g^p*pXR`ML6qf35N86QIbNc2^lrtp@2`U&pwAa1W
z0iFAW7cr97X+I5B*A8AK#?8vC$i1ko^v>%7?N!^_vRvdgdpNKSZ@mmQv$2Iishb_h
z*CE#MIR=FLsVjGFF9&%Icsm9hk+t~y(jE1mrE~cy)K;(WW=npZ5Ao$Gq~s=qyl~Sq
znoj0*C`$GulAlik3q=*R;SKf{nID)JzZI^YqM-e_aBPBE&Q&a$w9ZVpqg67b?jLRb
zHLB8qzLxV4Fgqrv3mTB^0;A#cl56;C$l5gpQZQPVT}9E>2@X88qebv-o3pt{v##@z
zyx1wxV#}r+CSS1=k3@LSUNselI6T**wkj4`P9<oB2=+031mpGbN`47%=V&gV8G@oy
zeI1De)r%%NbtgWT^9^2a7*lf02SdN7ze0D4;6=u;xYQvB<H#D|)KG9wDmN5<!04l*
zWofSJuX5lhWhdcE9J=-ErCPk#tQ)#vMkDkDCR?cFtAKW>dj1md=8rWk7aiRUu4k_n
zc|neWwH(+`;ud=Z9H>erud94DM0MD}vk*+l>+GJ144HHyPO1bcT6X|rM3SaXvl)UW
z(|SR!1etqjNuGTntziv*gG|C*!ggPTjM=4ig&mXTf-6PF>j5R%hVUf)4w;QfDBo|^
zfKgphVJnE~k0!f3Bbovlp1GH573suoTVq;zQvRaYdM%ujD1ZTUNQvnKqc=1a#hrjx
z)FYKNVMtn~-%05N<l{WHF;HmC(Drxwgo2W2d*-UPwjJv0^;ZbV3B{nGt+wu20<#`h
zZzxy>PX)%=<W><yT?+BtJsp*j*#I-iV31o=(SA=Vi&1lG-%gJED*NjPU!bCWifhM8
z^M2!I#s{UG<1<jf*sIAZxM<=?^>Ej-Y`-fHp(1kx&_@w4eH*6ZM?VrPWCKT9=a`fi
z0MA}f*}no~F^3)BwvZteXhyxjgP@5jndR6@Wr80$7Y9P-)S(@5Oa1zE94)|s5dvT9
zjgTc0Mo!?Vjk@&kOIFc7MxiL0Olyfh%8wVH>QNs1RC3sofQHeekp$cYbmGF9b{M^&
zK=F#!A~zK#31cw{3JSY#lSmv0T0k|P9mbG@wq%co<EPM{vE-ROB6(=qqACzAY;<%X
zbf*i7vV&jMu-nrEMo{r!M!Sy)I21JJz-CjGyC|OO7DW5IEP}Ozi_ld}y?8tPEG4SD
zt;-><a^FlopH|;#>WC_q3+MoTlk@VHu`nPn2{}n1=lV#^PgC||3?+W6cO7<?6I@}}
zg4d65Ks{yVg%)skqL-^MP*vE+O<Jg}?4*xVf5tq?4oTAN1N~j3Ha}d!)`mOu<7qp}
z7g0RUbUfF3hIW7=CVt3F4~!KHP2S6lnPq7gwbf2)QTUfnisgfXTF|k&r|;Whx#R#z
zAF%m=RECVabjZmwXH!E^_{=kz&LqY7|KJXWuh>~uvYAKiKoWb6C!jk74IaHJwufk}
zKyTk4>Z8hV&8ee3Gpez}p+AwyxZA3(c7;W4B?qW9?1!3QPERsD5*&A1D|&49U7jU_
ze<8wdE189p^p=K9=~1U!P8O$xdcvX8UEH&Zmz19V-iUu#Hv3zz*(igfJH^j8lRo*(
zpV2ywGOF*~!rJp2X|K;JXJD(e^E)?i<K+8LEgtNdUV-4Wv8i0rX<M5SYwN6_O*@P4
zc5lxkC;i@;^nrU48Gm8OXuF78+cO*zmcF4;`9HrpV47dzvo`zQ>k@7tMI+deZF~J|
z(WRkk27ZTm=kuO5qwCWDb>9VP`sU|Qrg}row7x?>MRG>V)oYBB8cdh?#jiC!vbz#7
z+C~gq%W$%Xl>pS%mRFQE3(M73d8(tf#=@VVSh+{DI3&C+DzXTAZvR+tU&rz#);5At
z>IJb5zJna7+WO_9pW34}@e8RB*PdhQSH6_4ZQv|+xE3I}f7)h`zn$;Xyl{PyEzN!X
z7;&d=uE~*0d{~e4oNj&wW$i!yTMkrQizER{cQN#rlEm%mx4a*pA7!D|WbZNjFVu6b
z>h2y|>b=*b;S;an<0x+=#{H)<;g}cuF~3n}9)5yF-Tg3M{sZnxxn)3RK4fLb{bvQq
z{{4F9bJk1s|7dd-lOsv3w+iITkLjxg_I-VI^~jx?-GFkCgJoAjZB=SYLgA+6YOBm9
zHrItkuO0Eg!!YkT9}!Q;sE>Kp49UX9u<^Bty6pdIo4bP2>gEQ9t(+2x+Ol@@w`vzB
zHu#W?CIejBJ{Z!l0}ZvcA@Qb4vIqDQb!%WYSW2}6E%~u_r<6^;9<}ujokP5&h&-^s
zfqnbfebF`YCWB7X&oqfa=HSm)Bs)5s2LCcAgMTzwjNfs$)v1K_!;cpstkxKFiou4L
zzaKJF3xff*^(136c2@o0NUQO}Ys7_1vWeD?;2Ao)LzvBYM`kW|BTJY?ool-@;}LvO
zK%D|#LS1PKg;Vh(IE?_?VX2)v@l>3J=uKc7T%myAN&;0mCKxd5QdDjpT_D6TkLjcJ
zDS8_BSoBm%^T|ZCGmW7^z*26pu<Rt_;H{|rzCcm@8ouiR8lR^qpcNH4r=zut5!3n<
zN>vGu9Jl9}rQ3OiWw~*arMTN#ck}2z3sDb}T=$J<!B+@whC1LO6`eJu)Gr~ml0=WS
z4MYwUGa<EGbr$tWZ3RnQkusr_@{)^w-3{GvBYT|6#EkS{P{$etJrIoAIvMJkMJ;T0
zTWuf*$(W{Ist5ALBB@q}#M_xmLGt{1LZQZ!6tD0%PM3DZk%>YDq0yx^7QIE)af(Cv
zD^Q~(5~<)*cuZ=<UNETy_=P5iL9xW|HnN;3o<EAnQfHb<1UIEY-h4rwI5C}If?%Hw
z)boTOrvZT0zTlcw88=L4bw*oPZ{;#X&egRh_@FUJ6oAl5NHoC?K(H36c05*p)=|L`
z7hsn~R=1CWQ`-t)HNva@Mq1U-Fis|x_Z4CFNGmAdfOQay3}~{<rsYM7<dP7@F6n3!
zrvlssu!C0Lxfln%q7?A9jtWNHpq~^>9Jt-VCUy*^sefbC)Y2%$8;AmhqQhanl%v?u
zBjcGwV!`?NRD%Nw`iNO{V_aZ|B3l%h;?lTkHRVh*^f)BLg?#I94iq2o=?Znpio?)k
z%0sdbNytAPLgX_j0k6h#=oFAMQlDQQ5L-?ZKH8bYY^y@6pxFds)hn#4nxXJ@i-AVl
zXB&+66>L~m*d_Bu`f+8t%9zJ+C)Ke%M#j~VU5)TalMgb&ze=+Qq_a#8_3dlzBjzcH
znoV#Rj@y(a_kVa?0bCkI;FV}mb%Ti+tP!Q1Tr=|=NCUxlaK{uKaQ!37k<#x-N4?j8
ztQ<?C(>D|jaGn0XvgpL6-`3~_Gujn?v@MW$Tj;VF%x8*X(u-3U!M&9dE!&!J?BEkV
zyA2DYgT4qoXk8*_7I7BwSF_BhrydekU@qpOC9d6-Q&)2#T$db5xarf$j-lc7&hpT}
z{L^x}c@g^SPqs*sKbA~d4m*~=eb%&uD<*ke-uNrqMAm!+L~Os_pZHiv?>3r#R9+lX
z7}$D}`(^HnIl`AT3}@5s&E*dh8Ef&Ldz(-BVtyk!z@|Bohu=ojMmi+>FG%dSQ*I=`
z(adbCo>o7(_S(584DWYWYnL#ee-Edf_V!C@O_tgLftNe&f(~TV4*w(e`Yz|wLkens
za8uDkc=fPX&<Xbf?TBVi3o-UAr*&iHB9hmLhhA5Z4Kgy8YprwYJM<fAcwmaG@4Gma
z%Ilcb?0IoJ+1<a!3hfol5_&<(3A?BigV@M_Mh@?DF-p!fe(dUDn>8Qp4-Y@ch&%Xm
zlI^*Qn(|9$I=7dZvH$V8Y4Wc}_(;x2hfMyXQzZS)J!bTg2iMakXg>9S7;4Rz)9Inx
zUOOby4IN6!^n!i3`r%0{8!nws&U-&cke)wJq;+m1+4q+N4q-=u`1D&ha&+SZV)=x<
zljIWd?ncI<Nff@_ud$Q)Qzec@ve8%jov~ZP$NEh6hx;coG{x~wy@+{S%?MLZhH;d0
zDV@qD*{_zXUpljdE4C^hwXU}KUA&}pH4-cQl;bDQNSGAqv;k;y;M5M`BxdOmJ2RjG
zQEjbnNaP$Hkq&JwX2St{tPbuaTw&DM9K3pT1*IC*R?)dB#totmsoq4z-m_^cou6{y
zEswLrM6yn&;o-ki=iV|duD*4ngu7qH?T7zSr>cNuS$19TwuT4mS@TDIbmynU8Rdv`
zCQ=w17XPjV60r|6q)vzvi;}7hCFc{BEJH|eIOJ{jwCnF_miEnuehxO6!f)B&rdgSB
zts`6I!dIjf-WnI5d&>8~nJk>6*pF)DZV*bQ$_juFW|z%3T|({SQ+;GzA<<>3J%t@J
z@7eT0(jjBP#`+km#$xQY#qgwMjJKUAsc5<I$$hP+{-(BX=Rv1k*JRuLbi7x2(zBU1
ze=Y`(>O_*t`XZlg{p@M}8p&bjrjTnT4V5Zi*7ygLyrycc7iQ)5h0^FqYd`{_i2t2(
z+mjzJ?9pQ_gU%}pmw8G4Te)a~UKa!LoOeFBs(8aCmDKS1j%v`^zV1JNWw}`DrQ*#i
zL$7Fg>B{8bBwtO;Og@Mbc6UYe;xUgLcG-F19g^|!zz(%yb%z@HWCegF4g}7<yX^b*
zhovaVlAXz_^tq*=)ootAJ9DtrQPj6nL%eC0J6hUSwp@>of!Y9!`s4kNcSi(XH1GJU
zg>r4R-CCF`_#)g>d{>rbFu6eLe$0f3<Zfcy^J2Be<E%WFkN*+nM8l*T=_M$rRNn#t
zLJ}~`q<sy~$JL@8$r<nxPqS(>i#=Hxi`pl&o>M(au%;)Q^C>24BabM4;7+4kp`f#9
z*VMkw@a<9X(iU;LLoN?eFOoYG@v~qm5Be*B*`j{>B7$Shy(zBkTJu4w7eXS+aV@02
zMR}7aMsjOtzb=5T6XBIWqZ^~juJk<7MY4+1N!DX`RGm2q+J2^e6^|)q#N#~0qxFDo
zp3=PHGsD<7)d;F#DWGt%Te}``I_i7*7gnqTKRk+2;fDmPQ&OMAYHx+J0l7tzm^Fu2
zonHY?raD%nTa<0#5$Fa2R+C_yZJeCljyI=F>Ri4DB>D<KpdyHa))eXZ6Jl5+jytP?
zP9dLw()I}C3Y;Y1&Nc1j1)}xE^8>t#4>gjIp&01u34<|}IAlr85kbbeWt9w%wIC1x
zf5G$gnk>*ClXhyIRN^?jI>0jZHjX;6hEe3ZtZ`nf;;;^*JM2~Nyy67R!I7kt$0MIq
zkgFh@I7*6uI5Z75wS)|!R-eGH13uA^MVQ7`MFkr_)z<yQD3c33rkWyd_r)|bjayWa
z#TcttIHu4c>OFZOnuDX2pt}9Mdi7Et+tE7mP>QQSU0ULn{6oN=sfV4xSPsrDcdcy?
z37G{t31j7AJ@qL}`n?%PK3%Qj!@Al0Fz78jyvA!NYOJ~?oGOB8e%&F{B=+(PCeQ`N
z1QDRd&Xw#wQVbODIEKRRlo0<AwxCW;WLzz%58Am#2*k}L5sO94q~_@)oDNFbmxYt*
z((vs8)pQ|gqXZH<tOCB^ggA9(VY-M8-R|IEID9=YH{b|bb_&QkDe3@cCJ6{q<BiAY
zw_rj|D`38drfT-<k!*muOO$WAe~OB9X41QII$|k*nyl2%kq{!GeE1VX$hy`HrX;R<
zX-V<O1)&qIcnX5K>TTyyCoaSLW9{sP{f1LJrYNNtVJ&0I9!Z{|C-Zf(GmmgG9ZW@>
zlcDm~vLC4ays_b}GVWWKnf`(EX%%iKNsj7B+O7sT$E5i-(jMFy({X|MQ|T_xmpTTL
zL493FzMt5#^f4s<C^5+=NH8LHGp>unh=V1j>E2#rv#^A&z7t-=AH0_<k6z~ssV{|}
zXoCqe``d7Q%=7ZnxpiLiOzNO{MYZv+rYvh5=qrns>)HBl>)W{MXP%tIHz6HQxt@85
zR{Gl>*J=M1ONYlaa8;N_Du-T|^=HQ@qUr`Gw??$|makB#eY-inS4KrZAaT(Dp71?{
z^9OvKyWH|h#^A4B%wh09(S>OG@WeIblMhk?t0uL~(`y^}M;0+kDTPpDx2QE0MTFX#
zjX%3}Hv8~dssGe_q4fA=tgKzpNcTU8hBtAojRLV0Zn)@M&Nsf8I6L^}c9QQL9Lx5y
zmsh{$*Ertr4j<nBqaoS*+TRGf{uDLp)~7aV=iVJWwah6BCFnNpw32_ws=#Aa3Zxoc
z4tI)L=y`UB38MVv=E>sSR!{?+D>yYsBNmt6#qOO3#I4Ht4PLI>R$;OGG?cPG=&J`p
zM451E(X+ojfr_kZtJBKh`I$$_7b#TtBuzPw@#!f%-*PDR)89Kw8hS|hWA<m5ao(NS
z1?E)Ao&mn*otMWouAsJNM_$?PIn-lKC<o#(x$%9e8Q&vG^=aclwqLjc?eibW{SVob
zKfRizeK+u8Li2Zh{m@&6sbl99a|`zfozm`Wz4h0ZGCO-2=UooKHx$NDTRra_C*&&l
z(HqZ}`s+#~l{d51cknaj2pB!U`>ghtLw43Afiv}z)I)<9zL5X&xLHoE?hOcbc9_D{
z{&p28<|PM044Q~rm4`VnP<^8eR`ab*wg{a!1iFZTG0NHBWs{kX_wi4b?3VH8Wb|M{
zsn$w6^%KTW^k(=`c_<4*$EZ<_P`ZsN)uai7=oYq;%E8U<F}KyXBH8RC;@EBV$ER_E
z8;k(6ZqS@AJX^cjQ}#@}lfxUvvW1tWS8x1>epFX6>BRn%X|4Cc(pNNp?QuUnb{f;m
zIjZ`uMA+mtm9V2<k1}|^`XocLYq)92)raI4Noap5E7z(a3p>U&vF?zwb{7Yh`}G_U
z>n@s4IK{FG=(y1x;0YGeTG1K{+)k`TW)>~9v4<EmoTZ(SYEx8iUIdRV@Y9Cd3lyhN
z5tm~++HKzP2x=h}awz75XyHu<?IB8Ll1^W{5zj+st;iZ^MYFp>jnH%@u@g{G!XZY;
z7|KF`lrAwXmO}98q<SS~b-YbBXne9SR5sa7Ci1B{%?gmApO{<QqDq|J-Ls8PfjjX*
zGtnLVY+!9gmD9nNCIPIWb7trOE+TX_lqnd}ysnwLN-+Yh2*lj0LwoyVQfHwnp!X5G
zHaZEe25!mIz?R23W$RjqPa@$_H^z7??Q_k_yOwWUt&jHZM!o2$CskSXtQ3T#kdVHX
z;EMcLpfIWn*5fK&tMrT-5uEhtGtqQo@2v>BHAkgjQo++W8P2ze%Xab+#0f<P+T~O@
z)-<U>fqEv5L-686yk8Yni51m&)!;=>j`g+~NB7dV5EelxOckyWA8L*!!Bn-nqgld;
zaZaC0u)aKi4`T2d4{@}3OsXA$c={tOnajkxz3RvMIf;fs%BPayCb4nqA`j!O9-Uk#
z_>^@j#nob{1xBeP$3-zUE2IcdS#U+M6()C#`J7+}7Cgb3Y3n$TY1t;Y&e8Z@<QlE>
z)zk59C>;u(H~x}VZd~uhndPTDyob9^idg=M03(${MO@fAj)=NF{MzOITA-<Om^J);
zJMt2S3VVHkR2Jbdv@|)2+uSEI?J78w)UJ_&Esywg*~}$Q@0;9M3_lt_lCdYLwJXdN
zp*fEhi>|Raw6US~CTKcS^r<ib3py*Q>kL6F7-);28Ym0`^VG6i3xDr;_DM<N*6YwD
zG=^@VPC|DySkch+K~OXdCg1JK!_%AmTF<isOoCj;-sNfiM~cvLt&HU*VF~wU!!h23
zE;@co82<&%0Jg62KHp<y=E)LC?(UCThsFtNa1&ITjxQ60daee2j69B&bmDy!acWEi
zg-Y{49Sbs&%B3ZrwkGgRSVma5&S%zDp0eL7Wmh_%IvFZbNl{y6V7qarX}s=0XZhoP
zqMe;E*V{g&g+s+jWyn<JCp*(q{RpbSF8Su9<12cyZP3(Qzw3|;Hs5N>a*>@Kzaz_%
zR*5qr3ntrha4a2VsBW0n4RW$?WK}sZYe%M=vMF3<r%K;93G?S3z)S^Mx66xO+_+{D
zL+f>XuaKu#FMW43TGX*NxY|S8v`b=V_~H9SxG=bd-ScZ75=QP*ymzQFjE983#AUFr
z;tXK&Jo68yyRFI)^(#zkJk-|6p%Ul<E=8?o&&r{FGyRy>aa25NYnDAqv<EF0wo=B~
z_zRQ49oUd1@7OHOQPy_y4a4FGGVg1L#S(|9g=-Wy32Phc4*5l`f7s6DXvlf*TP3-6
z(rU(!Bo}(w!&{E>$cLbJ3p_pWexnm+t~E?T%$rxj-+HH{7tXup+)EQPwC|fCtsZ@a
zmsf0Z4~_oikmN7eTJ~n%qWjoaX$co6$-&oA1l3l<iME#>Ks}{}swgj*rrq?}*kohc
zDj+?Ptr$kjc&&Gv3GaY4kDTvZyprjT(xeupC&=;Bw_}&C7)H*8+DiG!CpmU0H=OPz
z<EozKQIbsv9@iiuad|zi?$BC%w>4g1{56e_4E7Al;CWQ2c{>v7hqx&26=!lu$3Kes
z^2A}*Kdwl_!Tem2v(S5A|EpG}HPR36p=2&0ZDp}LgseKt*Vn)Q`)t<y`LNVkm(U1f
zr&y`YL1AMe52H2mvDLFomhI<erMFzfQP)2NMd$sm-dIgXXBbIQTV;w((W8M#LuCKM
z6D@zve8Uxc$nTIOzl9Hy_Pu-vwblCGjB(uw6|4q1N^soO>wjd36rB^=M-HGsMX>0P
zzOZ&RtzFPm+3uAmsQqDsuCgnHs94ffj?h)+(W`U9RxT|izFIp6Bo6u~$BI&<rqk;4
zk}q(3nNh!0ZTTqu!yV&AELQ5W!QIBzHTFYv^8Q6W4eu2z3<$La8ngd<dFIrKOB0c2
zViY>^4`eUOPYn|qr57N(;a2iDWf?fAi#4@jnnSBPQg*kQp}`;=zNtj5@yNNEa}PU7
zzXHW7i$^LW$%a7R>KX2nT=ub`=|f<}YlQs23C<?uP+v}$fz0l>@6n`uUUP$76?TkF
zUt0)BNvs9gBa0!Uspl#ME!O4WI*v6IpH6UmQYZ{CL7V6CNqZx{gUci_LXe8~Cr+Fj
zWViJeA{RkemcelxEeq*bHL=)GlzVjq4N)UbQq-q{EOjH}K2Kj@Et?u=<1=i6#!IIY
zadV(VFpAG9;=<L%WFC-bG#)oT!8DAd-EA>dPNtx?AuxORMMT%0S%GD8f-hV)Pj&4y
zHds}*MDkgT=|?IEgki+TrE!ODQYi^<jYFcUE#mkh!v6%g79Y<qxZ*m)D4jM|RNxAa
z$eL^WulWF>ijWc$v>#<oLY5eKlp$;k5#qSPoWKa=$*DyPF^a#8WEc;c>RGhtOlFJl
z=+(u5KN~bWDau!^fgg+S;@GHQCjs7QFW_O0%0TTY6x6G22qZrn53(vBz~DMM{Q{FE
z17wGW2zb}R4EzsB>UC_#&bZBE!=Owg1V*T!_Z2oGt89zzFs1O++o|zEPH;I1R5juY
zjDzF%k+<zv(rOk-DQYipsvMP+%?>1?or-!Cg{!u1Kp~zcw&@i|3$dMn7)2>~eu2M=
z`UEvn(H1^mTt7?>Sp8A&0*a#~%Y8Z_$2}=1e7yQvHT2D81?MmVULmUax~1OsAdCzn
zv52CJ6Gd&JiMasIiAz=*a|LkM^?6cfZIBe$Fb;+r_b6ggdl)<}Z(&?hSFNtmCe<jq
zl4Y_CWPJq$b$Lm(u<KrHDHMij8u~K0G@zgS9w~N*ED0+SY`!ebWv46Pnbej^d}Xw@
zD-_R0@$kjtc+<u9vgFH$rcqm!G#dD7;8*ip;pdz>{j%smJrpvQIAVi9I@*)mn-ps*
zxo3se<`bNB`HTtLGpB|Va(e!{G_Da>RLSVEilK+Lc1hr`-DVwhwCr?Ac?|D52Zai@
zI1<XTp%`u39T{tHI!at308Wj2;r9ui&33nL5*$vMukoY4aCx+P^#IoiC&oFQ<kZg_
z_uY&uGupC>ADHRjuKgs&M~QJ1j1zWSZ>D2;T4o*mE1RBcG|UaHYvhI}_b`r_^YMG?
zRZ^GDi3W>)cY#B~g*|$#Z3J6<0B2U1q|xL{hE6>U>>UzYM-q)+pOtK34|hu44uj4S
zwj=e2&UZm>xYF&b4b2C6rb1t(W8Z%GA2Y`-nXI04gWXniBZr*dIVJYcHClnv{G-XR
zVHKga-=%|of?gNk@J)i+x|70vS6N7c=1m(+o}W$RPMDGhc8;672UFP(5B~KP8ER1h
z{4X#_92GrS5t7z>WagySh@Tu&g54q4U@guX-9)gQ)Ln!jRY>$EVfBeee3hH-;LOx1
zf!$VC(5E+4*lmsUyhc)8hj&}kxvM{%TIEw;GEKfTm?j_I)DScG>6zf3H@qfuR%B?x
z&vU&TYU{vnc2BYhjr<*hYQ8y)jl9jMr0P%8#od5q_!a0ZN13Gl`sbxl*9%j(|BRbI
zw$sa%-=e|&`lS*c`Xqg6xF12ghWy@x)Jj<F0p79ODkqgEoIH0=@P6T>IbvjY{wq!*
zA4XOztxV|pzd*{lG70pToTTq=c(0W2KXoo-|6o-ot?-Q;P%fY3vM98o^jhl3om(<_
z&FL--e=lv!gI@jQ{+Vo{riUeZgE>cW;31snuSD)UY$s0C>!aF=_@e^V3F-2j=8!P2
zFYMZ0RE9P&r!gQ>Y{M=vf@?rLB>cp0pw;~~YCMO8cVyqA&s1$$Me6v)9rYMf9o--*
z#d?!4@3u~E%36wBXGJi(-nr)A-7{o%{v!udx%Vl%;UmU}^FF|W*A;W&lhdWG;nM?>
zU3!Q`HH~Dm*$lOnr3-a+hr#UcCuwwtVYoi&Tdg6QyBpeY6Pr16RvMq>#rBa$hM9pg
zrbCX6{C=@_ZV%2WU2YPVnJcB@KW)9(GlCrb0mX13*?;&E@9MisV{-m=GCz2mbx;1;
zxnbbd4`+k5zcSi$_XK}x=${OVc5(|ra7b9~vHdPk5V`J1-i1d_S$GZU1q*ym-qYX|
zPGq1^EQ`>19wzHglS@n4l+=F@U)DZUTV8_w1It}Y{wLU!KeXjQH_s(#diV+v?V)rA
z1I)hxUVbu{+Ik<KDBHor<KePP7p{XrZ#}mqrLwqmlU>4Y>&Mrb+3@nxVHqPSujO{z
zz1YMB>!-}U_&!(W{GWPpNLU{!hlHo(uB)t9SDXtRG5FSY;o=2+|7U?!ncYDa2E6lc
z=d(i-TbNb9!Htz)AY|9ikj4(O)Elav*SWN9(8w=W7PMGh(Okr0ar`29-2q$=Xt(R)
z1TJ>K%c6KPsLp~hQstc&GF#OQk6>uYoCy9zuT_1P<7Kn(ibvA%OhPdiW$~4v1`dL1
zR2EL|8y7i!2JCq8Ii90oA7%^odV%VH4e;hB$XL!#C%+2UFvL=|n7y7&af9X6S3#HX
zsyb9EI5k+ljZJws;>~BV-`_we?1ORMh?PGMqxzZCOY-0h8%%+Nb%nM_Xjgy%sdq3)
zj$~s^S1;$iK2!>E`%f9@0rjeQo$^aq1u@JOq>Ef>N_^RE5rQgf<1jE8y&_}U=CajG
zdoi9`xHxbi+^Y%;S2C%GvZ}jaGq55M@N^SC_c%!0Cz_=k(w`N)s8&JGD{Lba$Wp}G
zse5W$6Xw1}kmkUv%v$8Rj>D0JlX^xi)m0=fX<ZWq=$IoYPYSR>M7F$A=QSP>@Jd4*
z*n?I&08_;P?dUV1_TJDwQ!)ds`@r@~F&x&Qq}!ZpP3sO#>mU%csj3z%Hnj2E6bf-G
zlLY7+gqoQ{x)xD4_z=stv!}^s<)G|@btD@RHQ6YFWyxv)?Z)z`O-VUdwv=8=yCq#1
z7@UhJB+lYEO@z4rA8qdgUe{F}_^xyAx$=>$I7hPV$RQ+Kvg{}(gqy@E22$8pQH<i6
z_BuF_(iE;k2qEwoQz)dbK-N{1M1)XoAbArg0~a?i#tl5TP$rMgdp!xJHGFQLn+ctC
zKIkVhDPKx?jL9&(JO<MDTl?IrKenW+&U{_cJ^SC<Yp=cb+W+_2hqa@k7{FTv!tx@G
zjJ30gmKh!d9fIK`DGv2}0ui7WU*gcRZB03R#PVi5cz*EULaC|wS+Wjl1xlzMh5~18
znVGQ$xX9>taIM*xGVvDBPGf<MPQc2h<BB;Y7p8|XXdTK+GSUar1(!9Ghlv>0`QDT$
zo9g`}>m5GQi<m9<-NEthBv{@s7bm;rU@XT~i-5}ru91YA%H2e2&XCJI$BE{R#Xc95
z5u|Vc7@t*P(5TT;z;4SBt(yeMl_f#|J}nZ57{gr)yeaRoWQ+1Lwf0unhMUpIXrd+s
z5m$<PWQ%iwp6|Ih9BnV?_7lB3z?n66H+kRTY#|PfgUp$ep_%M5OIP?+=D9GImz>B3
zun)FlbSUH|yba{T0<@&`YEmW<XQ&K<*X7}>#P|T~{K(pqHU8Sv7m_XGIWB!s2<X!Z
zk{Bv!*{_Q)W(%Mmon&5x-}S;EiFPL1Kye2?jI*vVC%F=f6yid7eJ#r#;vceim<x4j
zna@!x|FXBQQrrnDYP1et(*e(4kW_{Pk#J5iSjH$_Hxf`l>Xf_%WmfK8U=B*ARSAhX
z!(}FKMhAlSbsTFjtx4(%OZZwPg}5uF4#G;w8ihh$SS(q`Zz-%jk)`o)c|^s(Q5g0p
z6{hs?bJh(4C4Tb(!6zcOnGZ52>|YRIYt7JU>Q{|m1Wl5@gOzE=*3nN!MwWZ9;zqmO
znn!W-HY`2=6EZh-1#Dd3DcLbf)|t>dWb?w(ae`TlWI+i9X2vSuJ7H$gw!_r4WA7aO
zBDagR*SAqIOj6o$I<vG3#CvlXXLR?8Vg?8Jk+xCHZ$$`%4Uu7Ep=2SKiAAtsrJc(2
zwEFY1Sdo$iT*1%cTao3auYryjh53Mj^#nf;W>`u!ZbQz44<~_wLmkm$8C$6?TI>R@
zP@`^hRc8qq-vO|*%|$wvOS~C6fN?ZI&gSUXC{nvOG{zAGVe+>U@cg<1O?8c^8Y&_2
zTY+j(hD;n83Bt#aS&XJLrbhWKn(!2fDxLtm+W_4-D>y(W2i-hMLav;3y9GkPTIoSU
z;j9)mEM?~n4My7!I5xY13(xKk#)4XW<j<NQ-;Q9~VPKUM^$RH!X;5+mWiejdIMYJ`
zFuZ7ogF9vs)&j1BR3zjJr&h^Y7*<*;>1<md7RqOYqDtZn?*JQ#W(L>+|D$Ge3tSW-
z%RIF$sC!H+puqq*6k&thSYw;;YZ+}{y_P5XIT0j54Kx5du6qlgoGxm1;Jyrg?9p>$
zH;PR5u{fAYlO}Vs8{Go8AS?^s+CwEsE0zkI&CqgYSq4Uy@jKJ2$Bnl=#})-bwg7F5
zBDfUU)v#rlp^ZOnKwueI%b;{HP-{O(eg>(S0Ig`8tI!NhP+YD+aF)T)+?t1--H5rh
zp$+T?d#qL{-N7VALNR8JC1=8E$%fJmJ2f+edYG_b=>nLKL8y1Zj$Se4E{5X~mkAZ+
z&U9k4BNq?7gCcS<9rb{CKU+lZ{<K7m!_md4CQ-ZE4YCHEjhw=@@-wn#DYvR>aLVZV
zVtgJvc-Y$vC?uN1a8P%Vz}>Vw<!`BzI{vz&gJ`94GqEAq9c~L#9JK=?mX!e6c;x)8
zh-<?}mF$AlbjD}N2<tk#daHd>j`tjX=d?sWO*DSC*^cK*KDrmgcD_5bmNOqr@^zry
zpLr9Od+s9?tt9%}&JFBmU0>2_C}h?Jt=cj&)-g)%fX!bG_7mD%Kbq$D_U)H8GlAI7
z5PC<n&o-0d)&|<-4?yJzT~c$4jOq~%Ozth&EVL`QOLbj4nNn{ob7zmWqj(9do`5d@
zEYYX(cvoul!C!oSiZenRtw_+7=dAoxzVK_7KV-^JuH7VkCizx=H?8ddIx3YbWFTuk
z6;JBX-Kl+TLma_DM1Aj$dc8ST2Pf&z+teSs!AD_Pg&12|!%8{$<z*s^;@df!iD&bU
zy)ruVN>TTNZF$O^Mtc7Pac}EMV`F*aeTi>OV)Hn<f&TTY_}b7F;$3`J?A~>@6>pmT
zqEu}>)RVT(yOEWrKDGu=ekPsxgvnv|pp$JCgkvHdo}3c@ll2n+rz}aE|B-NeXJqG#
z(`Nk;g}3Q7>G<$1@l^GX<KAnhf8qUo5Bo$L>*`Bu{_-qNJjyEg(NKb8RX&Ocn;l@Y
z!<ih^JnZ;fXfw>QGH5#UCDD;n+$(tLi+tFx0a-1AQ3#)eWUIwm7OBorr=P-i*IRI<
zZ})Y7{3=qpplCW2&k)JXt`MlBgUJEPX_k=(g41ZPjO~6q1vreWbY9|m-%m?&YO5rD
zOjRp$+-lW7$<-@g(BamTBgc{mv8J9if=eQr?e0+Z|K*O<9f5kL<!CmW@fmsDQr#xL
zC-(Aqlbk#ubEeVGAE9k}_x5n(oivPg|IQJ<={e9Ce;Z3{$Nvk8H1rvcww~gay+7Za
zHS6n~OMYAA#wQ|q(W4jm*5S8H?7#W(pb{2;HK=<+FG4xf+Sg*apHHUFD?`1fXe*28
zl!cXXH;8n-+L8oUrP^^Y7Gm3wh68vOKnoqz$hO+Y{n!|rMBAR`%a$@LPZMlS^8%cW
z74Eu&A>NEoE9go+_s(M66-8;QoMaq?z{Qw4@beQYOL8?VR6u|AUSGaGNsq?ihyz0(
zzn^yi-rjxi4MFeapBS0!-;`9V9`|`0Y_H;VbjuI*lu)Gla8!+|=`=x<?6)N@?J7-^
zu6TZq!4JA-WA~Sv*8}JP{_AO9F8S;shRxq&+jaJ=DS2#&TaO<boSBvf+)$bADbnZ)
zvtW3`Iv|%MIh~%>qc&unPQcuBPTKZg-8c%PZRjD^0zLR{gCoxdK~F5z05+moGW4Oc
z8j2RdYk5`;sYo#-k=j0|+=39T_7XtKCKW?ziH;w|lx^a8>VWSHjblAL!z=Q5uL`Z0
zJJERO--8va&67%2)@~p-p<3=j4k>zaBJmhz09`Ou8SnN>pVVzbDdYV;sDR!|@Fh|@
z5rJ))Ng!!(UwC$TgrzD7c`3x_mdE!rPBE!;g<McH+Ca-ts*6;?Th!Pm)DgsIVB}m;
z2+r~nM?{F6%;4V!Z<$;}vQyrQ1{x%rG~1CeY$@N^u!LlL%c>A#%=<|6;@EtNF~JaI
z+@$Y355PMCZ7rz=bW79*)3y=gP!~-tEt<T8SBYA`Rj_}5znIz@Kl9LJ=*F%jjsCHa
zBvS!TX~qmXjR(~y<w1~joK|x>8D}6eP6wxj$mXdmXQ?=Ry@f!=6{bA_`=nS0LQp5)
z9nUjOL{>LyQOI4Ja2w5GCIrX}Eaz=V95ShpmT9S?H%p7qHe$p4r-Q$|In*3+7Gl)f
zq;EoXJYvOb5?_sZB)-POCUpK%aV>o8MjuXKlhp`p!+`<yW-(f;LlCc*x>YL&31S8c
z#<6h`SzdH8jrW{3*9b-23>bkJ5q!{ysKtO;o!rV)x5nO<BcPV?-Gxhg@~mE$wSd=o
ztTtP?gRL<i;DW7dR^#YeqP7ef-8vK61QwEEY-2E7M<}O(Nhai*hOH}v!ZZ@?Wc!N@
zv<X=Kxf-=)a+o&Rl=fS=icqa-9Fkl-XKoygCyr1IX*hgTLj}4(R$FIPA!5+MzR%&E
zOaoxSqaj+d(ne+WE+XMlCAY_m90&gxjWUH`A&QN!k@egLZ8_$SDsJ3FkcU__@p!~%
ziP|b?A`@8F3cR8jV0efm6)Qrr0vL@P&o<oLv2-!x8@7f)k-Z&IoImVDxXp!tLVV__
zujjV|th=I_i{$G_*xC0u+F%@n*|G*pw?{D+Ba&UB+ExT^AFDMkkNK7vwb0p$$Kfg+
z#I|HxV+ZZpI*CTdN26~}>}wv6d+sBBAU?!5IheM#FKt~t*@0}E=x3)>O|C=g&oJf#
zR0fl5(i#C*70y<=&_we(nUvKg8wbYW(7<83^=ZuUhr{yxXguowgn{(eqI&d`@_psQ
zJNOVoc|wL;eW*iIMyC&tW^(evH7%4h<N9{*ERpE$UNxb@L}G4v=oOkevmh&8h^mIw
z5_7Kxn!Z!w>fGHNRJ;IkT)ScrDA>eu?i}%F*Cs>Zg_CGwmpeJgNHDtpdoF4;?+&+L
zi?fOvBE261Z7BpwD?R#to<W^4GzS&uKcKVq{}B00PCWRRUXmnty(^Pl&&HBh%gNa8
zKa8_FUmYF&=#Dhq^@B)Glv!7x+!+ic6FN)U1?MZJXPDWqG`_Lh_0P1NjNR~Rk>4E;
z*x4*|<HJ3S@9S~Pof?r#O;veGkXC^ap{qdL{vW)>v#~erna9Uz_HFK;-4DvpuDD#O
zap3f?`(1qfghct#jq&xLe`R&N`8CZS(@X4_RyR;>-FJ3uh|Wp1!6_+gi3(uaS{w~D
zr=36SP7cJecPn42Y_Q7BjDv4$7%0DJ{sbcv%P_(YFSa4c>89bJ4l=oT+M0*AC`oqI
zg1Z6J)<OrF6vx*@YLc8jaAhjn@8w%|hc-p>jq4c_?-&1dM%yE=`;O$5)|fnb_<T3{
z(^omUl(uD{#I*Ive~M)CZ;-oDSRI<;kFS&K|I-DTT>h7lzbCA2%jagNB;Rw-wDerd
zlF_x_r;D+#=2a0x^yO<1=?}Tn!3f_wJ|Z_Bi+bg^=^SQ%L{s)NTA6!(*=MJ|pE@q0
zjlc5nu1Ib=MkoD+4XJFIqzOO%Z>=@%0*u5wD19LIz2P~Z=m@(R1vJA)F6OVw%KPmq
z`mVrs@*XI#gc;A47(-B1+7Lm3ulwR+Vp-I`Q$<&pRF#3LyxwsVnqZ~M0Y2K_+q7ek
zg$#n<iVqhtDK3cSCAqe)F@@r77|Mm&dVl;f-r`OM8F6x4AyMyKtw;OiaCA%5VECQB
zL?wSc!%)3PviyRPp_#YGt(3T{L%;ILk6DRMuJb**-P65>rQpP4=&ug8#NCQ0UU9Xw
zWKW@T<y|E&?ubf3n^9ft<0(!G=w|;JD)KMrFZ{N&-nd*`UzPD^Yp?i6cd{rIzrcCf
zL~DFlT=(u_dO>C?98qQTUkE3RKeHxmb--oXv94}93)bV*+tcw(|LrGn?erk><fAL`
zO(=*?U}nj8`002qW0GSl#ARR<KgUN9)WV7vrIqjC@LE;YvlFjb63j_*sL620x4D~I
zLy|_17895<y@Ld%^l;b{@Y<#@i$k+IJk09|IrsQ3fMO-O)DeNKhv77R6dO@BFLSDb
zd3R}oDeJVS67*Uhc`m`L!w941w&Zd;1ngr=BSdY6{8H}~T&QVI9<qddK{(Z7kuYF;
z^NGDJ?N}}Xv~%BfafC}9h1w3buFfJYMQY<NF%l_xLyPdW+h`12cuK?kXf<jWF%_^9
z`k0ZnBnLPtb)V+Mo#BL$FFMx>>8=sT(Ilw-aUyj&dT!V|3sIqPpZbD|r}3R1p$D%q
zV+v?m)}SGzjF%<r?4O+=wOuPi3&MENo`yWm&wRT<=H@YI*Nt!y3mbG>+77L_wq<og
zQ954IjEn|c%=$&>4ttokVwydq#3|5evnqVo)b;qVs$@O|I1DYUt2`$=6v45~0}r)=
zVM|Qjes;E#k!1%eLZ1>jc^Ho>S@o9ld-;)lyQW5Et2tJMmLpiRDQno2h&}wASV7e6
zF))gLjN;ZL=UG&3bcbaMP4EC{jp90-Fmh3{(DoINhm64A)pbdN19wWVZ08bnesXMB
z%R@_aHzCf2V7S39ks0A(mI7L4R0{jbPmM!Z+(C4wQR&3&eX3)_q&q1<O~9Q6sJ7pl
z45iqRX-9Ij<~Y_{RMuumAUE4ZJRCnuAm!I+M)Y~q3wJ*QRJH16;Q7zYLTPn}9!Ssw
z+Qpk3)8<FjP|7rM5Xx}}uyX4#XRK)`N%L&su+*Y))}kh8VU5KEqb5itX%d{2xTXAo
zNFs7IK7nFtSQZ3lWk_8h;=xc7gj9f#uSouVnlJ3O-fY8<wZL^y$!(F&7Ww%$<9wW(
zv4xLHYTL8E9iLIPEnV0+g7((8k^ReqT*-yO&9X0;T^_yBZQf9n*XFPwU4u$L7Y1I=
zX64U*#qB?NK|6bMLzB#wd2i-ty_3D;eU$8PAir~q>9kHiPpO<R(RPEZA<@ALn^Yio
zJo(Cbt}Ii?6VO4oGub4uJ08{g_=XLw^zJ~+=@`xE53C8XsyCT>nSDVlx+nUO%(2`0
z^a!t`Z6@p}nQz^i)ciZ7(f81nmdJG@P5mqJ^28N=4usVqY&;`Q#=8+)*{Nt>=zA<y
z+}Y_O2qub|%If4i!Lz?E6V)(({4-u{|9&A#D7f_9Q4~Jtcm5Tl3}VQAWnGpY`#(kI
zPS6v5>~W{}vD=z*F-*-7Y{_OsGVAK#QSRQKQ_T$Ru^Z^KNY&J-jF|tDVxD@QHKb=R
z&^RRft{#!ke<gPHA91Tq#Aj*t{P##E23dqKW}p41sw#Tc9Vq(7bIexzcS`n^H$+KR
z>hl(>qB5P!q}$vx7VVqs=L-_qT@ooF$?lIyWFOA3yhX$N8^`_knJ(OOt_){$2;^Cg
ze|}|WCiSQ9d@Oy@dOy*7tCM_otJMGII&N!x+DEg0Q-)4AxL>9eoTTT2nK-$FH@JRz
zAqv}`LHwvPLw9yXyXJM=XuXeq;S{Lt_t(r%`4zjZn0C!+5W2@PHA<cS*v|&N^fIF?
zc3bgA{I$C<!))2iRUsq`f6lOMw{_Syx=8l1&q#Coy(;w=^h*EMw<R)lj6$4yt0X@?
zH_EdgmgE?9MEakh!hIqN)1fTAF&**GZ>4YR0y-hFf8uU#1wtQc&&X6>StnL0u76)5
zlY>1HPn<8c;UAt8PO$q)BlqQNyfkMeQS6oeD<Y|Hh(_gYDFV5bebv^qOdi>k)+)d7
z_30{KLgdv*+Vd!lH=gC|Q+t!<@#7mqTSokqLAQ&WBG}dpo7XmI4%ls-M`!*R3X+Ti
zwwu`<TwT{wCd^KUb9)8E8sZLgC=f6YX|^s^Ih>^9{xi*wh27TqFtg;LUs~d|f&=P-
zE|X%>PZpe?;>sM?OUt~;qgM2PwM|r;IWqLzsFWM8_1{lf6X5f=z2YxVw4i)a(mS7*
z!S1ypnc&l%{q}l|B*II<eeF7~f1B{Vu&NAAZmW5BYcaR*L5jOzu00|4RT)82>%_~;
z?X>uHiOl?LC{Itu(i1+#_H=ot?IF5c;(c;>BMU6YvMfF^UC=9dUGe!gYj_MsMQ5z#
z?G!6X7FHL6d1%M7iphA>S*?kQ3kA#YJoq4M)|VFfG4S;<Ia6ZM(@3eqP7$j@%euBx
zvEX;e8VQzd0vx+S#EoP1tQy5*=7*{hn9?eGa|Tz{MTHBry4n0x2wL@#jxxqcgi}$V
zX)PvQQwA?yE99wekxh!uECHDH*&JHiPGUv03JfeP*#VChD@3^Q-Aju`gn_bMf2p#a
zS`woGV|YxgVXWZ-OEpWznvbYVk)TipjzrBQiSU>e4K{PF1c)maF2s+$9TueW7eyP;
zeOpVi$VdY{_VA&OX-EzUAf+V$9msS8B0+s3ps_ucFW_I*w&oM48NDe}YN~6I$S|`D
z9g+{J;f%p+8<-1O)(fPL=Q5@b`A`cf>VhpN0K^t=jZB|RQq;~l>;WjEB_|sKBW@??
zVcMFe8iD76E@&*#q{W(IFszt<oJSpH%rRGoe97Xyj~wVmxdSb;1P`i>l~i}QNvL!d
zg)I2R=&s{<0T$nJPzv`$Icg9kihI1cPKcRqiEDAl>2^c3d<UVLSwM$lA7L9khNo8x
zp&u=RlAx?kQRWF(ganzW#O7KRW~aso_r>Bd-y!Um=#TN3LMf&(VJEiKW*rWhum?W;
z{36ovTxM%V$qYepVwDotj>yS0@@v*5i5>W}h$s*kMOg^w1{DQKZ9;0f%+8~_Kzk|7
zGvSu{FXOV}6#7bFoL?b1b1eroJhej{wN4x!$)3fiAqQdDw%GR!dq}pee-_x!aoXVL
zqaj+w+_GnSPD4=~P~d>&lsEZud`YjT;fSr7!lwfk(hV}nCXpSPbcX8NmDTskSj;3P
zIvmS*&dJ`)nkDsyL-I^>!;~kuS|%X}?ik0QT%Ub=mxjC#)kqYZg&w1Hm07JVUEDjn
zN9y(#SQn@jvcN#BY%p697XTd~h_&#zjfQ5Cv+z9a>CAlt$4v6|SgudZxd68nG-d7r
za&iLyI;-RQis&M_|11}=-jfT{*3;lN?@uFh8UjvdUbnTG(@&6z*Tj(}mQkIe^AXN*
zTqi%1csayH!E+aKB<>t;!}`R%u5W6mOO&QL=3=`7m?%lDYnmVpBC?Zoc(zg?Pbe?6
zzIjIR)7G?HBx8DbB&$wF^zyeDVPh}SF;87&GTnwen_WM6NcU6+6F*6^f07N#%NzCb
zPp(cFEM}Rn`@O@c$8>g`|B5~d%6m98sFt_YAlAWjEJkCwjUdjV3JYlwj3uJPvcw%f
zF)DTlmyqs|{$?CsJ$Dt@=V?$kixMbs%-EZQ4<K;c3wdNdkUsPZ68Y8$s_-{0nLfIk
zMi~@mctjc}*@Ql-JAh~+W7>LNrh|Xc6Jmb@S#J1fL-$|(;hDZ?FYwvP!=*@nOi}#s
zPrbDIqlQ+;<C!hF9N7CHt1Xtn%JUnOM`Ul&TN=R?A#>&F|7g?J%DAuJx=s$?#|TRJ
z?uts%C|#YzNj=Jr9--7xtRT^_+dB6uzAG98LOq=Le#zUkRWr8UTP-F<Ph6U&JK1f$
z?7$^*-G_e0NbXNd6V0dIkm%q^`E0{oX!7X-nH-yTJ&At)2#cuSEvrOZ?0xs5{OlPn
zV!<3@uhdIV7jgur$xDk;nV+5FsTOa(xaOy=b0wy%zfOsMk&n`(zoX(Gp#;MwFL7u(
zi1bQntsz+i*_pONon|m3shl10{r_2q4_%0|md4@k{VdJ9&60lp%D8s&`6-=_DVNVX
zk^1}ANjV6c(T;CRz&KbLk|cWcod_vDk6W~InQfL39gyC_-1z6eB64VWI?nE7y$$Wk
z{q5+D?Y5r!$hazK+E3G3-#;MR9_UTvZQst+{|?mdVM@rfm1VFEW9iQKviHFnfcwUV
zWPECZru;+5tShAHLI30(X;xybdiZ0J>N9_FT1$Inn?}yDxvu0aTlyk+!x+rlpN=>!
zR&DWX95P;eKzeist7&=zMe#7JmG!prl*QV&PSbcAl_gG+T|mrB-WYKF;=8t?Gil5R
zHlxv@{y)U)e6&P7pSLBE*8fHQ{Pxwd<N9)0<M#~_%sk6K!Q#|C?l}ADtAlPMk;{Er
znf$y(yqfnuyot!`GxAw|u1_}6SxQ|@ov9bPiJMF9+e-NZLFee?cYw|iI5|#1>MYk*
zAneM)u@SXtYw|>|E4e-mYXC`px#YD+T@?S-bXrC~R|h(2y*H*_Jdlpp>%Jl1;jZR|
zC|a;oc=!eXm24rZi%?F3qV?2ZU-Y2O@3^X1Y<TU>!_D-!zvkJFZ=P!c$_=~@-zM4x
zs33c9&a;BPI<xj!t2m7%ouqV+Q=StziZ<8^Vr|e0weYHtE<K?!T`+>hb8WP<4{CEv
zA|P0u*mzA$P)hl<SyY@rEa&+F1o1d?y$E*=w0I{>IeZ`D#s|AOG0~Ly_mp9G1;-`h
zAT}7@m{J90TO!kP<SZeAY}KF@tgAnA$|sOu!q!|Cb?0Kv94Iwd*lVb+Unczs8J`Dl
z1L}O<xuRvzcVaD_=H6v#q4D_yQTrmq6N}9#dD`^ZCa4?rWY~jgE8E55opAe`4X3-n
zv>F1GFHR7iIm|SR8O4HzXCXD@$4U}Mn!pgr189@sRqUBMai&;?rToY=ILYJWsxJ^@
zaBUqog)t#<SI!jOq_?h<QWCQ|oyk_C9{>TNEp2dSBLCGvi$*6fLS|q>=E=>+3^VVg
z-pil4QqAiY%iCi$aEnqg89Le^{5)2i=Lwf%n82#I7r+N=uQ*SCS3t5TsanB(CukYd
zBY5OC=y;e_LwgXJCnW|KJ2BJ91*M4;pQF}B7{WL|d7I4e?uKSonUqZ?nB<)^;<Ye?
z`z;5k!&nVK0@gBk42TL%(;#IPkM}yMl!37j_CNS2_~=CT9Sdg2PQl^~PG^|DMuVYP
z&IC0t%V1ZSJPl(iNDogFSw4#CaNKf6);zwXaIKUvhmDPn;1)F6P?m*oY{Qs~bVyv-
z-+d$?7PZMmRM?Dzq9tm6n0s4xr^ru|W8q7bwx(7I%Na1HMVkS&WHS|rB}Q9^n+%*G
zw`c+!N4zxwZC>5M+6zn@{AL<FVi#g=J!{pz1Gfdu@3@vXox}fzi3s-fG5Os<X&%!<
z-yE5}+bTb!jO%5xbO{HGhIk94{B=dXux~grS7mYLMey{F0rOlPTp~_x<08R;_C|49
z$hF7Z{<<`>X=}xQc!7#x24#s)4yT#EZ!}5_HES>6I2?6;tAi~F?{_h0jNrV=UP8Vj
zIad-6*bOCx<aVGeo)sSD&O26rQy-?Svms?l?E{|U%Y67jzBiF2Pf1eIk*MApz0=3n
z>SR^+i1(xU6zBPphjfc`aMMIX)}ZBN?^1U761R!H>Vs#c$*HqOLtZ@3-7j;93y3I-
z^yh1+H7$@i73w{v-0_>f-EtIVmEyF3_z;U_8xNO7kA50;{dX#rzNnEjzb6eP7`X^9
zOTvGHZ#|^%jmEq7BrRevb19OIFNj@s$Ue#%l5I}?H?~s$;GSgS4>q~Lj}j1*NT|Qb
z+xunP)ILe4Oztt;0;b+G{KVU1HDIAiUE=!3K8sq_A}&{av2%4~e|P)cr@P*70)&&J
zpW#)v$0j+5GAPoTMD6i(FWw)?JN~3EO8+sFM(xMFseV04<k&@`H$733`@eX0Uz$F_
z#{?c+@6+8MjJ<KD@MUIK;4o{P-t;GN^K*|>v*;h#t8Dl91NXeJ$fVADnPoL_q&sss
zYGEQ%NSR(DK{YofnS^ARw*C%H;!uy&M_<X2;wf@z=Yu`Lt=MqBPi37ve>fj|_dw{U
z@LL%iLG#mAc3b1l*<_YGr2ox**^P(xd41VNu_cC}S`re$F+)^8a|Pvc)4qK4PKGDO
zvVUr0>^+uM0UA@EC}oX5KpBR=NU;X&EV}n^MEwzT7sc+Y&EY$B-TI3EbjjJft#az)
zOx7=3$Bz1|(t(GX15xzhdpJe)I`Ieg@J{6PxtXs#5xZvG<1YRbo8K*AvUAn>)<sHE
zy?lMG(@lirmVLlk?(bl9MZ0+FYdw+voi&gFI6=tw3;%gQ3AnjSToEaz!U5ijb20Ey
zNgwMCX+5?%S+<T=Y|MoZcr3!Y9Q)NI-y#nRm#YFttUJ5GH9La5nX}2HnsSszSwECm
zURF{*ax`sJ=5^gN=gi0FJLuu|^BD$P#t3lArn_zXN`{9({GHuiPR7Z&Zgv5$?&M3}
z_M3N%O3B-C-U|M$H_{aR-&`%m$3vL5j@+8el?Rh_kBr%M43T|;#(%rTRRX(N0=|n&
z?7lkaP_Rj#Uy@Z+#@J?it+5O9N8*qRbF2u)8QRdQwBqcr|1)aX{_>(GZ<k*pP^T*r
zY6p-D5$D<hNk`k>+BOS=hBtDY__xvu^goMall}0qtAl41w92T_hAkPEZeZD%2UZ_w
zsJvwifEVj9XUsldYDf}3%_}g#vCiEQeE}H!g_4izm|b8twDLy51x&L=70ScA6R5=y
zW6&6l3qqj>5*lDye$Fa+MOTSbY2o9TXr+xze1n1OMpu^R)V0O}#cKTWGQE_yk%M#u
zWY2Gk-&!C6X}FP-l!<dTT8I-k3Qos!QhBTjDz%)njelT5gVBDtj-!ynywe5{KFC))
z7??iPDxWX%TG^UP*(0X_#`0mZV%nL?G-Oi$IQE2WF?K4zTb3uyZp`Fn31>iY!i|ol
z(i>aIs-S^dT&Wutb6_)!K*Lf>2(1_7)o6xah_Df48fb}+6D5Z2OUtBg#AX;<IU5|4
zw3}vWqKY7AC~%__Mgn>-)!GL#P*@E-fm2n~BZ}3yD{i*!#OP3Pj+8o%PT-m5sJOaS
zjO8$)Py`ewtSzg?Ff0eF*#cM%)j&WSCYd#iNp}n5c?emowg`vzV@F=V6pfuTEeS-e
z0NpT2IE}p3p+G;1xb%Q<@6d4C#kIhk^B_jPg3ud53yBX6j?B<d<bg!)gf}b9noxlB
zN=CXedy`pik#QvkzrvfB>~Mmajz&HpT1fv4d1~>_RbU?sW4;Txc6fzsDjXpbo{ON9
z!KIR4gmAjG6Jf!>wqWhp3`xl-%@8)5(OFrxVKD_`CMGLugLy>Lc#i;zXlOcL9>Sqo
zcofNE4^u<)8*+?aQ6}ZR7h(pMbulA`bUJA8fO&)lZd*jtq;3B)(XtTsGJ`}Tf}MF>
z!!M(QbrjsF;z*z{f+?OsMlZdrMatx>usg%V)!E8Z54?H98Rv9_ncYAQ0WJmtdpv@N
zc@{8#uClY6*$G(AR3mjmT$Ow)!B0AdVQob;?AzETw16;e{nl<7pEX%uLf?0HG$ZA+
zm3$f4-ojj&Bc(g&6MidH!Qj8*L&c@x$|&39Wwf-AakdH6qcYExvSWVG*8_?A3*?PD
z3ajt!4P`;kQI^fFj~cy4Vl9d%^hYbE7y?k9@{sex`4)+}r#*C?v={^NTN7KL^gV_Z
zed%JK$VdH1_Q-G1#*Rg9{nzL*^-CJdbwclZjZ8=_)qq^v6pa+$28nvlnSHSwi}z1(
z8u0~bv-aua0Hu^|t8FTTv?^<4!TO-r=<U_nq-PJQu+Q6x0U2>8q9llk-ORQ+c7m5N
zvuK}7-|5oul4;L*ag;q5^su1teoAzX83$J~Y4-Oj`PFck{J%4HC6n4@FIS_Pe2{*M
zH$vsZu-5ngbx)N+m5c1kC_hKP#UWwM?kt#Vyh$2cc1!$*f4Wf9tt?lV?&=?1%{5Bz
zn&#4ucHVm5D^-8IG!n(gEYrJn+Sn*atnx&A?%#Z|$oJv%m2ah0!NW_Ee3DVTnsP$I
zwJzi|PxCKg-~0?trmejk5>DhJ>t*IQ|AEOyE1vK@Z`5;*v;3BF>My=r>T^F?=iSIl
zhWa0Trx$;8s~?PCNUlJc`2hm#3Q^H8HUI8aapgUwlE^unrnOj}A3~3eREuAj7Iw|4
zQ;lc7q~eI6k8TKSYq{C^Stdh3g=uTg-fA@V%zM~id~HpVM{eYFUHXqIdkv3dW#~B?
z#mg?P#>XC>sRu>2kd>fCKzY$_D-(ol3_s;3_uk~=(I**x{_R-Ni+cj<mPjb$95GGu
zGPC<t8oRfk8mQ6OjeFKh)grG7V0uH?xSN*}DmM5DNk*?3j*iY%24^DXnrO)#>4Vo?
zr*iD2eOb+RTVMNN!CB1vdXeq6O7*NfN%!fvzpSKw$0uVw_ZO3XX6OENg2{MVpBp)D
z4f%Of*F_`wp^_(=u8@0B(uu*y*M3ZLS)wc=P+f|MRupYGTUbX~11Jq)fcm;ZL(syu
zPv}W;qCTG9DE>O*)EX<H`Mo0~y-7^gZMagnDG4@OeZs`G8(0CI-JaeW^?FVg+K^2}
zHNPX?C!eY=PM|1NkvR}g{c6;j-c2c0+HsOMgyr`RiRDd|wse~GAUejuVDQdO<#p68
zCk?h3{aa{_uY;A=8&%}>a;UuP4k?>d_;+&nUu7IIo=D}nkIRsLD)xGFk`C3@$%`4v
zH&ZmRk6g8;cZQsK>%8LfQ^`zud4A6D^=bdkMD!6qE@5a04+YFy%(;e6&Ux}y$sE|@
z^gLlgZz5j?eDGr+!QBq@e|4PW!OI?u9n1*TbcOg9J`b6fB8K@)E?5f$--^`sveKd$
ztiWR-%_5X9L5mwy<V;FQ;N1eOMePQzgAgpnXe;d}o_8cbiE>tu8A@Ocohh<|nU5(?
z8jEbOC3NK$wqNSTltf(cB<G0AL(JOe+e#CpJ3z2E7BRbm(V{Gjrp{pY_{CA+u>jw(
zbTM6Sb=_b<hMH!c!9`Y#Eu000ECtKrhZV9BNs=cQd#`9G3E!b)$(fuwz)F)@7je<a
zQ!t0&GdF}Db>Pg1GY4|;W_AImhETT$4NF0nZVihjJa4k1Ewzd-Y=YzYg%=CVq;z3Q
z`HM#Bur%^v=j<R|Kq59qHigI;M$bU7LFojMkTY-Au0RgLWNVb}MXnzfcPx-NJ>K}~
z9xJ#{)-AwtXk;eLu>cxbK&MfiLH@1~`049(cmq0($ULH612}RK4i;FElBZ#!n+YHn
zWRFK9IPrDCqLE8k^e!Naox|qCuN8ZTr7L*LW0h%Z)R1g;zYR(>8DrWylZ$GIZe<+q
z0)n>r#0-~M^)W7QWbB+UTQ=XBZ}RvMRkxSrUs_C8qqQqECbmT2{x6{v7MK*XD>x&|
z{(N!>J!2(&WIl$GnFpi2Mu_7Qn0_T}wE(_kDr2aVBR3~waccA}#|2oH$h|PZSzE#Z
zYf*HQa0imKOuZO2Cm5c3)d`umP(|=_q=?cj9QN$stz!D3O|<lhY)~({KIejqhuSKG
zix`aU!F7@{8b4Nq*&L&3$y!_DWGl~I7D6Ec-dD{i1fY@G4ey@?b|Z&mE#idu?YJo;
zinjaaHIgg655$}o_~b#ycd}1oq*8)pm89-Vq?akNua3!dKQ{@Fm!FOor98*@(0_@@
zH;m9Pc84t7Gm@J=G5QoU4bDzPJ(rL4Z^RrdvR1CN$8_m;7W9Z?E7S_^MiO}wg|MsS
z?JUq5pu!xbJ#B@?%qQul<>q7%&b<=d+snbRoIRbt=*hCqG{*R*%a=^lXOr0vFdaKg
zlKy_?l|OS0Hx)T$+TBQpw#2uz9M{M7xH&#su8;c*++gx>vDvr=t|-MiiB#*+W%5Vs
zqIzdJ*Aq8!l7%~BP2Bco>K-t=!tC#Q=8sn~8NU)aJy+ld3RwMvh?MUF%C1W#dVKRn
zC%@V+j%jN&kUfjm8a7fbc3ZEym_?U&;<DIXz@<O8Y3n)C7r%;RiwYAyDmi>j#^UQl
z?3lI&ZP!l_YKe?YLYRMN+47r9W9+u_4eOK2CA279mlQ*=4onu))(X>BWg{|s6bd$N
z9pH2ti74}aNo@aBPtX+FO~OxI82Q+?CeOP?qPeg1T`fJks>!)0*&}@H*H8@xa0fn8
z%A#vnd`qutn9S0+bVZ_-FU6uHySOD<iOKY_%O)rNhOL?W($i($>p8DLbQnvnWU}4N
z#Dviejy;T^$cw(MpSw-p9njUD7CF4GYgxMCtU>?1_dxMlHW(kdF^#fs9+czW@WM^P
zr~?;qC6c^CiWOuFSp|~$3!jYoR75N&RMx5V&pC1XBB$Srq$d=hk)dU)gagnwzCN~n
zYpGvO<7~UFCoU{W{jp)0TqU(mkoSFkjq#0tE;FC3aI==I6SRcsr%Y7&AZ2pZD@(J3
z-v{~ln`u#x{2uSNev^*&L78eETF1%kooQBgG)vX9B<a6J#qS}~>))W02cL0r@`-h6
z^MR4rZ9|ylZ*V0O+jLPr8^<?xl3&d<_G_Q#<q0;fRhwmNn8-9x@6n6HLSAqoEqLw@
zt$UnZ3%~`|eBOW-Whq<-?VKjEem(wQ@0ZGXUzKv+AB|1fm?nVQGRl<*X{bL-^ektX
zT_MR$hi~H-sONczK`S5WtR((reU123@LK#}ZX9JWa}qVsUmuLaK3ILPXOo+X-LCPA
zBb;tm-eJ{|W+E5s7-33sbrh<B2v6Yl+tg-H>?99lD&J+!va5s-oF?a$v+aE4a;Mnh
z;B$Ah#J`EE_=Y5n7-^*b+|sF}I-qWDN9qyg)KLBcx7Yt`X#OY}FG>gdY5)slY#q6v
z?TC(3LFTb(EX6N4Mdw3SuvmmJ{R^650|M`tMRmv^K}(vO2!>5pcQO|mL)-+KC*Cc`
zU@q>Iw|OrQfya#L0&kn3{DxHMQ<73YnXYQ8n1Q`O0jv(tw~35;-k_bPEPW<EEc7Sz
zh+V-GV+t%6Fk_h@g;_L9amNH?u}xuWxMs{p;gg?^VkT4I>R#Kq$C2%WJ;oM};Yj8Z
z7X3dL%Z7AZGNnI|&}-0%hc@UCq}B!~NJRe0Q`qJ!A~}<7C;uLdR###~$&E~`WGQ_2
z^0X)>DifUJk7D%}?CcSq7HR?E$=eIGUJM_DuZ64z9<rtglr1l*fr&E+fjK|rtR815
zKukCc&w@*1*^njT7t%_-CGGjG4q){w4Ub__BHVz5>tb^mcz*zTObSfXD#6Q6W+g@&
zStksMhxv$rO4Z4j*T{LnQHR&Sci;)mMkP_Rd&(l4RcNWK5xlo(v_@7jLKZFJyu}>O
z9<e=EgCt6CF{Vh|s!3QRS%Oah;dCcZKUOek&4V)}SERTo*`yHJA|JzB7Dmjspl-IB
zJs=z)f{xL!V4&^WL3boFDc7Regjo(jrNCPqbc?b)1aYva2E`e;_YkNzLYYA!=cFUi
z?uaVmN@-^IS{-KT3BSxi+mf9zx+V;c`HQp0#NjelCEX^Xt}e+4p79&FH!Y|)?KhmQ
z0VY_|m~<e9+;T{Gm9h&cU1&xUGwx{1aG3~Bqd;Lld1<i*Ba_OiVKih6FG-pyYk-9o
zqwR5~p=WqaF7jcC8`1FFYL)=nNvWNPeO)i0nEw!VW&OTDUG>@C{7gW1a=)k&RV;sF
zr)9>DI56Tbq}&v5Xnc*DWF1zul1#DHg9xT@(GPo8sbomgfF1A>V{c914a@ZOcwy%4
zsjzup?kfw^*4v!rwHqi$U*Rz?f%poiw%ZC=M!i}1AOkk*PcKi>9n9!zkM>u``|jqe
zrsb!sV96p~yqCEK_l)(B>v!}fCXw!N+lXZOhrwGkZOs||sAsr68c!Z_O~|3^$%DNC
zM`Z3!l4F^PL&DQTfis)XejF^Ot;0dMUDCCd#-^<k(O-edjMczWNooUC&pq9qii-0i
zE|O=qi#Em(2AjO1?<7+nD7A)mNZgVKP=Y5Z(b_rm#g`D_7iB4DRpln8$dw<WaQ(lb
z?tg1AT9YV95Gm6{g<?3?J4=0c!P6e|QwA#)dwno)Xdx?u+8sP${wQ~RmyYhaqP-0i
zh~<w^tQ->7CvRl_vYFxhS84VuFDIz^j66<RvM&8Hr=zFPi|-;d4hb{cTLTz>SIrSC
z{xgZ1q+-CyQW^ecFKR-!de@~K^M*e2$3pbmPDM@m#)jC>-pDZPGEM}(_FN~!6_w-f
zXcH*NtoT%3vmB6{sn?a?XV33L^prYbt*Xu*-pnfVu8M8xa?bbLvFLsdA#U%N5qCMm
zm<P^E^kN3V)xkbaK3rCn!NZ<6?lz_V{&#x0@%i3C`7qRGuZ!b+ZX++&y?kQi^1m+*
zAFrio^%Ggy$<qheJ9=upT8i^vS!2?ZsrlHn6@BUko-3J>Fl3PuG7ZYm?hO!Tn9s^S
zD##npV&r@4cwGC9tzL%T60wc*o5i>$Bw{nl{LV-Q!z9?0q8o%m!c6eOO;E#E1a!6M
zy<;NvF=YF7R%UI`ls~vN@#G}UzMD-nb7oV?xD2?bqt<6RN9_OdLc=ewMTb$-3piM~
zm09obH4*P(^_%nt?cv|r=R!^%pQXINc~vBj-A)09L&6`S*g@$}Udh+EX3MkD+g|J>
z{ei^!J$<}1Qq%O4kIQ5E#HR72|NYXu@kHs+$eS;aGHU?0cp~1!uN$Nu41dpka&Gpu
zKG7eW@BtT|JXrE5tV~<iq9%L*rxUfr1kGB+#c(r@!_x@vdIbA*e#6^YOzgi3?|-d}
z5U(V$u`L?6c35>^3&0-}JdJZ|tg`9Zfoy6rG{lk=O(ZXW@B%!ck^fROS(;;wqV-NX
zt#@$N@KZLpI#IQ0Yc!6EbOSHzdT3{8Pjt*9AHH5=og&$jjg=5t6)!ipX;70*6V|vh
zIC`K#zJZpHoz#35Ju;25U682!pf8JSXr>-XXXPiXPPwzEBmcfQ?x_rp46z2F7H<uV
z85$FkbZ6q+B@D-IGq-k15X%DaV#0!BC0mo%5;~<nJPHF#c$jxE$H_F7*fC^DTO^p&
z5QPb43FNr4*~SvTWgUudWHZ%qgoxo1m@o?vTAMPGbd#1oVoU1g4<zAfiqlg_%-r6V
z3uLkgGmn)arvWpXEkg+rDhqVX&pb6)tRy)tmQB(ePdgl*AD|Y^^YD%?H)x(Blpu>k
z8;d+dId$94kqapQEMTf>$ywr^6wOZC<;{oZ88Q$4XFT!+A1E$3f-R2KEvfTGdXR^@
zccTmFE~&ggrqMGpXc_MU&iIRCq+rul17|!VwJp*NYNl3n0aC01m{BIfQgzcN&K|`m
zx*0pQNUy$@3`e9>CmM2cyGTc)&Mt#a<@l@h>sDqm3CX!mPCRHGaFFPcekKrxAAF-Y
z_w>*n$CO2J!-4h4nGZv!e+GEN<?&fF3&_n#NXnUo?$3->!CT)IrLLm`+}v#V^Asqf
z;KZ1Ksu5Iv3{^2=XQwD7#+s4r6bPOMN!)~V0g_Due@2}+?L}l?Fg}720w!oIV=(N+
zZf}DKmKF`&E}{#yIP$o-yu}eCa#&Y~hX^)?Nt*Rq4+)jnM(>-bZZ$`!4fhfg-9}ut
zrL1^{QxndVkf0zDZ?+_HVY?j~WFJmI!8>y@YiN$&gjv=C4}p|<9*$oCA98Ni8b37)
z#EbAyM&`2;XaXYW5eU3qI^o-h^As$A+<A{B>2sN@;cUdI-6f5GOmL^HGi0N#O<;8+
zBnwKLy7)GFNY=heYyrplg@8ex8M9Kgq-=)bXtTwRv>n$d_B|BEWpzhzH<*H9mr0XL
zN3?$yT9zvkF(onmwuXa5ocB0Dr5BFuGz%F`@NgwxEOCzGAW|lm5g4T2&(gz9J}qur
z+v0eOGoVZs62jgEexqO@(6S~h@e2_SVpS_i+tZoj*By3&Xjxmw54+?cpNl9g1bD91
z0plRK35n#<ybs9|60$zGrit3FsNipby2US&ZOM2NS-`mTRRcepr8In$7gChbZqLQS
zs}>QrzOUEb{&5yaJqP_M6iU1sDDxWoAkk6AX=;UL#X|~t?08>Siyqe!p=t2Q86R$|
zEKmz=B8xQM6mwW{K&SmgJ7F!-cSII(BOrijT~)jm&V*8f8mJonj0V4XsGAL(wSuX~
zX`rXM|0SHuBs-ss@7UH*P@p&kpYd=|s!r4u%(9x+f-7|sy2)wS@esOLd~M+6%vI91
z54{r&2B;?Ue@QT&)(Xyb#kM}N4XB|rt1ikz@G$*6Q^cs_3J@Z#5H|0<O!WT|(YX$t
zB%-HV6A&ZB3L6s{1q@jBX3V1Yuw^@nQpWf>vlPQwOUm&JVZ?}Y`X}p6%{TNL*8M9E
zR(J8``U4ww%#Zxcx;iA%vhh_sZHbza8DpWdFNR%K5=_l3V0Cx`7Hr((4b6D53>p*^
zq#Xe7uJE;F+P>za`~nGQ1OIlUnt84YPmorTtXi@O$vPs~ScXOm!yDBkYU`8bGHD2H
zBQ};Tr2<2twZvpL$%FZjVXX?DTbtA{Y;qKs<Z5_!01LZCA43Ec!*I&OeCBg&*3^3h
zl7JNCWH_BFZXfI7lm$qhXrRP4V<R11RC5e}c?e|)0eWXch=^z@7muQ3%!xNJWsfd!
zhjoStNEa8zndlDU2*HwZdoiPi9dbSsDh&LzBZ@PFm-=YO=?Y6^8M7pqDaOc6D|{Wb
z2t!t$07`?|M+Z2CZ6cjP%=PjZ$Mn)hkV7YYdDEjB@&s9kV;|7HD-dVf_#mjfn~Ykp
z)kIJUQhQ)nN%77&rA|I46`wgQW0J@SPjURaPxq>`HLq&fhG*y6RBCNd4BF`GmBF;t
zbN&nP9m|?c2PWJv0=LNCv64p*(`xRNv+LxEUr<}~3P8z+7A<u_U~S(u8g2>RAzTO}
zZJ6&k_LED3$#84ZMk@xEm=$q7Hdhw_xoi=92hX?jJ}>&n2H8LsSv3YcMU|R5)vQhV
z-?328R*)5CDrw`Z#PKB^`6dD7f|?rh)_Qo0Z9Vwfz*FH(w&~+k_N`0e)NR~tFh`0m
z*t$Fpeu!86tYZ9-iA7~OCa#0R2{Kr}3$?wRdd*~;W0f0&NDJyD%f3jJSqV3-k9J9s
zVAdZSZLFIyAJ)VK1f=qn!jk#-x(qR?_+oK0FM0M&0vstze3I3=@P^{vL5b)3CAzvD
zxT?`Qp8|O+sf4pE0d<Ob8RtWuBufVS)o+m3HIjRePN1kCqj-i!Livh(n(3}9(MsR$
zb<>gGhqcXI8}SX1P3+!CV~6wQANR)6+A(w~Zw=Dste<ALu;^a{?Uf&%7vWK)2Fa!D
zfB8SFcW~8;(>{9v<M7G*YrbH#gRs2m9s%pXC8+#+on258vJfa3zEPN>Sm*AKV*hXZ
zy}aQqaU=hB<|h2{3yt%3FH_-c+E1x8?&;<9!YC~T&PRf1)L9OX{Yy54VTmPMc>}fK
zBKny0zxvRNM6Z1V4KpE}+M>V3a^sPKD1O&VY*Rp`?xKnMyL*IX`8B{--!vo-qM64(
z#qb7No;dd7X3Ma8lj_Ci(dPeBpU-~EbZGb*mRDxM<G(&fyy(NdBP{Y)#cLdI-u)&g
zA7cgd<TG!Qy`TRI+pRyTO7o%@vsCsw&hI@|ipvvM=$h*5zL<9s2k)H_y^*vYev$E1
zK>A)-<oFyVj<BCwRF^s!%b5e;5w%Zuwvt^;#BE0fm@h5@Wb(IpW%cEp?0T7sd}_l$
z{Jr}}Xsf=(@TOfZMY8AYRz90Z?6z_np%uYS*ENiK*i0-(p|aY+$p<fwRL3bq+sJXm
zZ@i3?j*#?IMhwn$@QZP(<6I8&{k^EcXOdKVOH2_9)(vSzxY#!S_I{o+x~xnNHbqp(
ztp1A;uAY05)M;w{@yR|(=U%l><P%%m_=!(Y#-ohlo?>u(>cEufM2`%e7(tsJg7@lF
zk{stdY4x9M^n*7K%2f74Wa+QwNHyDMW6w35eCUIjTaleb0s82txjMWm11J7*G?BaD
zs{`3@P|h@#1zgD*-WoD0Tyi4O9GKj0p0J~`6fB^{j@9%5EEf}2AC{dFYAf=V0X4%G
zaYM4@Cdtb$X;=fZfYrfh81=m0@UQ?h<>UF5O#6GrlFT-84B}7qdP`Xir(!<3!;SX+
z-2r9Wp6>0^D3Ynm%)cwpfTHzoBTDiKFG)S<(x`l(JS+E1OdI<e+qJ>k$LB?U_%Wq%
z=U%T-N!;W)FmrDteg1!O`;^1}rTw!S?@D#3_80QUQOoOC?b5NxeVMD>fASGl#CTb;
z`hM}&wHn=SP)okHE*{F7>@WX<3vtJ@kWpfJq*9F3+a#jQq1xRchv5K@+!htJa4&kA
zNSPj_;l&%JLpRF%+J(V4ISJl_PsVS2QMA>qV7q{^DBp~E)hoU&E5r`Wn8SBmSm8i4
zxCsfE73x<v(8y9ES*;bQY4j^Jw2_Qhc0%s$QDedxu6WFb#d}hko}#`wi$a}M45na(
zmdR)x=SkSvZzSlYC%_Mli<CjVC^X-MbcG}=Bs;^4p5oz5mVojb6!;Fgl*qL$c&`F{
z@0lu496_@J(GIQ;7OrEF!qzc5O>7W?;ixz>B9schk|)yz2j;sHs6^~qn(REU%NmyF
z=b&I_$PphjnTc`86_zPrK1E}hiGx^So2M%xwB=x^E5c5yV$0a0mh((wU!+WNjp7cT
zRWqHlnrxWL&$oH9Y7@g%=33})-N|+`LO3G<f38>!t8+`H#P>{7NVGzcEgCQI4d#k4
z7E*InlC?3`4BAnEH>2ZF?Amcy!1AD`bT*F;wG7hBfMZJI8GfaZvy-xE4@d)sXgLyZ
z4}+aHlZ)!g!h1LH(`qP|tTRhnry;JC5exD3pRrsV=vxgbQUW=0qUOpiD!)mRuk*qV
z{NUdOXsp}C6U|C4ye?y;?DI)hFn#-ullo5PrdQR)DIo^4q@rA!$wN7pob~HKa}S9o
zuwVjdK1fhslJh+#I#V@a(nDV@l=CFP3W>G!`Je#_gsV(j>1w<SK0%a|!8-p?owu%F
znKJ)WLnutF3<zANEtv6lWq&YvB<9nB8Y3u=BX!DiRdCGvmO>?mRt-OgsmM$eN6yb0
z^^!M>fx;yig`|urA0Aj(^f!dnU;rdFg|tg;sSg01dFWTHY62$L(9${*fjBcOZ^cR?
zQNN9pKZgV=gd~^ZKp?iZG#p(E%3sG))y;A}FEe}R?PHZ_T2KufYXjelngR*Aw3sgB
zRiC^%F6%jgl<iEWj3>H6BnNG6)Xty$keGR?9er^`<~PHPU_9pv?MO{jxnAUp(TUEY
z*eNgJ1KRl(s>64R!?BB_FK?gQg#SnR-G<C)udH~4H@jr4S9)57yDgSMXJH(@VFp%x
zvlIC{PL>5=`XNkPIfD~E!&-Q*@*Lu;W+ET-42!n6#=@zPQ4RR6Lf3J4M&#fBG43Zy
zFtWSi?F|sQZ43#&+=ppv&2ONMo%yhCo~9Sj2i$w)8@$@)UW!r?naldbwRTKO^}0yq
z@ZcWEtR0-5A14FjM#$#mg-B%hha_ZEh6FEn0tH;Ah)zqyi+f~5lE&HGUi03oIDbfV
zAW$%iQLt%i9UuSFlIN8w60v<he{-B#E5uAHB3TH$b0f)4My=T4+YRisKHs>24E!8g
zw7Le#2kGZIlq8I;-BgtT^R?SMtkCuK%t;=$PkLO<i%Z5?d)gWc)7F~e(FI)e_?w2^
z(f_C9XR}wc7P(7_5Lr5XcfX6B)Mr)n9Z8b!+0XE`Z=+<x*Wh#IYqIRvrBQv{4vBr?
zCE_2xiWtYY#`5Q%WVp0NeDl!u*5Lg+_+IGE(fH?>wvK<|_TDet#9LRg=5htmHSg||
z>9}9wWNaZP7c*_0Feez9-4<$VG+m%2%^x8!Q-=Os5JuPr#!Qf;IUYK~4&@1izVCcV
zAKnnT{H^%9C!<6R+bT|&Eni5d!nAejemuH@@%N#igG}&TNqQg>7=Q3JjB$rJm_1pI
z5o4IPwiB5v@m|UcQyD~mXFrA7-u!XYfID`Ymu@BY8X)`4*FftQS|#3=kwaI;Ez%r8
z04TP|uisvcr=%3!vhAahT>6DR>c;lSRgd(f2kgTc*{^U|?SI?Obv;KU+CIs0l1+l2
zsmMs)x<jV+oD<b*PjR*1jokB@yxi%bZ;fblV1urKFHoYhr1h!WZ9);(%CGw*(~J)M
zZm|YqPDf)|lyN6;1+yWCG%j}1X$gz-Zl|HP`o#O2MP<B{9<E;>Ug&Bz<KMEf?*OGP
z%^_YK`6Vrsq7$%!X)lHObk5WQd6vrPH3<MN-y)Co_4G?`rRYJY;!k}j^bsrv5PWO{
z1^87|?sYFtn6^@xE@dU-rr7DEMehQc9if!{DSfnSrTfvPMqoFy?_hfWCRVxW93p+S
zm*_oLH4+;4GKZf>l7mB&zItv{S--zmc5_q21dD^Nk4doeug+%6Z)41sm*uWU`>F@!
zXj%Hk{}oF57Rff*Jb6tpeUDC`ygeDxulGdu3SPTPIvO=c3C)9_x2<9^xdvzoH=bmL
zXghujW((rlt~00%U<oNd$In1*z{(jhzlO$8iwGDV8^3ujZ~~_}!>B0)BqVFc4KzDo
zDOQ4KflklZ9n`WgC63C<$es_3Mb+H3qw%J_u|h#PBNbUnWG4hi!!&;_e0^DZ$T_Ps
zEb@bvIyxwHLDn}0`Fxp5K8YU4F`MwvH6;Y5O`7|zFivCO4Qr4?8O|&n&>*CaEAk!N
zDrUy~x#Vr~?7*_tRE(3Q;BlI-V`@j1sATQO3_b|AfMVJjm%L5My8y4q2}28pplFN9
z4*b?>accAKN{1)X_1<!CTm%vY&(0kDuL=6n0Y>ap*D$NgUOgXA9q}imUyV#2yxW(&
z3-fEEUm}S034*7xSt`0oB#xqDOr610;~YEz4*WAC-Yn{ex8XE-tp#*8YB`hMh>;8h
zVOd@rRTn!}w4>sR(kAUv3zW`4b~ZAj5a7SZo6XX)Y+G*UA#xS+j<D7SYH00bm&AZT
zRJY_95{Cd*dPIW_^qLFnKe(;OXy+M$nwoS2PoWIUg~}wsxVJY@hnVr$w9GSg-I(SK
zMvPXqhFGCL;oB*z;oGD&_INXbaKv)<B5VR{sUuYRrBM@kVhiLoj(uqdpBr3jD{LKp
zItc^Wh`sX_fGl@FJC?j-S<$pi1V&cGm=9<Ln=!0rBfV_?%sp<G<vfkvY#@qdW#~Jj
z4BXg@+vwKzk%kcoGDd{$B+W8U8>Ke8{elo9#*baV*-}TFRvXn*7Umc8FbNK+h{uGc
zQDsFWksf@mrBr8P`k{Ur)|wS~EOk&+Z9#R?+MJ!#W_m;~d=Ddn#${>*r_RVJo+|-s
z@{(;Pbh6M=Um%{K_RqsyH3($hy`tsd7SiW-mFR~f?6z(ULh2wFOwoO$yj(AyX-5xU
z<9XRL$BSvo+Cr6lcXk(Jomh?+_lI@}tZXu^PQys(HaBHe53v|z3DZ{VG%H#pF1#dC
z^g8{zPF(%Xv<lbX$@>t$=fiGmdeflBp2PQRfs(%+#OED3-tH4=Re47$kFrGV)^9$N
zLWb0Yx*xf=ejkb-L&=^jdv!0TY5Ga;WO?pvHzxa7_dRs3_j#mZ)7GR?a;Qh_(;=lE
z?<L|sr+tS9<Ev=37q@AItPHGglqAZwDe|70M`Oz1@oBehr`A&Uk(}+emTmrc)_W;9
z+tuq(APgR<ez&4^Ux`Jpy>ir+#bcd&rNnj>MjQ*@vIIq|>=lM->(f_RlrCV&o?w}+
zaX~acZS}-K+Om^<>*OLx^5T;T$VZp&_2-2|^1J=#!<Q&;K>r?P#&PeM$}N{goCUYu
zx*HhEe;}iO^iL&v@>feV<Wfy*S*^B}0TL&Khi%&0K*96dFNvdTH~FyJs^4MBo@wjA
z(b@nF^amszuFKo}(dpPvAB^S4=(^tA!&&~Py&ow@PX6%I+4wM@S*q_TCCT8w(QbTM
z)$n9O;_G!*8b@A23o*A4$+W`rOTh>qxiBfM3N1o6ekYO{%ygA$E2Z!-oe9%y`DL3o
z9i;Hx*AYAaK^cQOyp%dO_^dJ61zO}F+}M(@qbOe~b;k~;#WBVo+#AQbb3_h*PTM2k
zH&cKX{MeCrz=gb#Pd!N+a`VTP1!0)DvzJb?8`#qC9cOW4@=vW7`#l%&CCKq!Db-I!
z(VgW!*X%!7()`9gxz#akmEU2_g=uS4ZILE7+32n>_DTM>avI;eBW@jfXkFa<_k79s
zADF@9-#sUm-?+fZ!Do6}jX%6w`cKqHr1H6vMql3$TKUy^gEL2p=U(jL?5Dil`M9;9
z%L3wG8(dQCA{B#>+s=$rZ}oX*i7dAr-oxy03nJ!qv7>rmG3p5%9E54e%T!n5Xfb{g
zZljqaFV+xiv~fO=1pN9J5>Rm?=Be?~KWPVkyD&{{QaK2UEoL^1Mt<f<y1+f{nLIY&
zB>(6j3TcYM$sL*td4Gw5+boHHA*2uQAk9~MTgT*tdcO>5jl1z^|EWj#?mugmkt!3d
z{YicB6uq@ym(KJYN&JiDb2{TcNg+N_)_ThpxUZWYjq7V^G-1VbPU^Rf)b-1fT>i|E
zIhO~k*J}XvZ6s$owck>(Qc`A$!S{M9%GVgx?4?aEFU3n`xDRd;l{J*Br&6oYEq)7C
zoPYpLds>N&+X$i-{AAs9!9{SzAsFif=^^Vif(a!;h)S!H4zNy#dxS)inMk}j?ob{x
z`0x)fTFPwj+i*DQ?5nDXS=E^1wj!S9<il4rueSLDK6KRTp9PrmbO$3t(R$};8E9@b
zT|Q3aC7E76Xu;Qnw6J$?jkjM2Y}>+cMMW)SR4gx+C2voD^Wgb50Z^(t+tXMbGTA#B
zxnk$UpN8tiD_*J26LE_$6cz(qM46b{lKUL7FQ<-e%mpJ*wC!a_EG>=S7=lco3W<!H
zK)6E<l~wa-A>L$M!iG|D+NN5n53$Mnm}8`2FB^@wY|u`1x5T4^o}z^jlT7JR{J7Fb
z<pAB%LpZuX6tWP+nx;BauP?%Pi|p`aU`ehHh|j?fNEm7+9b^lmfFi)-u%EmDc}&g3
zlJ~huoVW@Ib%=)PuEUYjj_0aoz$&OO!3+M-O=kJg3IeEZ@Rc5Qol;dz#ZMQE*D==$
z#3#}5K$ku5e%E#|>=7-9s9fe4!C0dRb}HKmxRywKQN_NG69fejxWY4vj!Jqz0?Awt
zUvB;wgkgT7ju5$N+WWy_DKD(;76~l-bmq%(cpp=@OJi0FD?zAdD+LDs#0owg-qc1a
z#CUoPj&9<mQZ-@N*rtZLCzHCePEdd$K*}aOHqh?|$m4YABy9@f2SvSE#tloupV`b_
zz{$YUu0q6Z@6b85!<RLDpw%dPF))m2&m_yh*~9XO(|dC$ZcnqUlh|?GF~#j4p0=SU
z#E6S1M#V}#M2bV5V~18IAmlI&$*6V#AJRpaFv)jX;}DJuagu_~U=NSEhU@f53!bOh
z)FOR{S08eAE9LLmk;qG@p)j9C?f7Z|)7Jcjjt_6)s4<b_kT9+eFrv`t5-(8W(FN4P
z=g338mrU3oZI=mW5%{aa;$GY5q`(9sJGjo7PbwS|PLJ|YE8UAT5q$6B+5tma4J-wH
zp*r~>+B~c{{&-+VU(4jKiJTuhBe0RSNTYG?DdKKCo3_rd+e*OKB<}NfdO2*2uHzeN
zE@t(6My|i>8<JPp*hwTU6?g0$jpeicby31fD}}_>Adp=h+Idg(`6QA2m9zBnrq%pV
zJ+rCBH}*OkZ024S>@EKCflJcl-rtH6yDiipP%w+lXKmW*nYPNreiHd|9P5KrZ-4ZT
zLX$$W`Ab-#xfuyhMl-gS&=uS%qT9As`g64Eypa&W#$e8Db_b-b&v<k643Ajeyk=z%
zm#|NC%aMUcqrdIX2KR2)gqaFwPBv<hb;Dm7T=Z90M(*f;Ehmk$&P(L;RCfy1^DHxg
zX<1I1%1XXp&ylca_h%y<5_Wp!S={Gv30sr@t(=sv8TZ+PSJlPO#_7}!uBtt1)7JP(
z%f3VErTj&Ap3l41uXj?NjpfFPO<Lp)+N%QcmFDy4$78Q%y8ic4HT{KjVo%Rcz;L#k
zIb?ixgY0XuP8$-_)_KLUG%T|6W4BdW_Cd_@zVoS6?-b{s86^cKvdE-JJWN}A-rbVy
zSyqeZ+h&Ws0x)e=C9GwKghyGLFtB8={p$f~-Zv)t5MN4h#=?K@XGi_F2gU#3MX?7Z
zZB8SBFVF|gP~P<)HEhE`LVsdJRt5Gn<;nMs$fUBp_oE9^FV$A-zjJI74O0Z@tIyG1
zxwFej{DqfGws(6Z)te_$N3!mbpN+^drmgpn{X2wm{YHuJ_&t$-II41N_HOChbH3=O
zA0Lv&m(NazW{yn6mCp_MomYno3|HkT1diBt@9eFq>?xlw@x;=SBlQAO+ifMQtHVJH
zzNCX?4RHbUWP-D0E4UxnCPU-4IP>}}DL*1P6WNh^fo;zd{Bo;oFH_o)E<mzno3>hV
zeYF1)-)u3QJ*s+MT#4g`?s#TO&4c>D!9!0+Q2wK!YpVGlQkjk%;9$PdcoXFSL_Qd+
zJk}AW)cpL{;vuzO_0+oJ%Y4_t2x|)WhPXfHdB^L$$a}UXF7H>7KShCvX;+_LD*Joc
zp!;zAvS`1blH(tzPrVzI7Y(r_zTJ)M5f&1kgq*jJRbF>TF1x05X%QK%(*e$UtotLE
zO4!E|7b?{}T8Dzi$8|4OMw9S60kVN(a#mD6GtU5TK10QT-&xT)^H>6utEObC3s|$#
z0n;GI&+{ulUCTBd7b%CgL4v!NDPsr6DD*I$$P`N>_`2|1<)I>Vc$;R7U|1$O-eZ^S
z9f-0*zQdr66h;Wv*qbCejD|@JdMhJ6^8eHJKHzm-)q(Fi=bn3YB+Jf`EGM$#BwMoV
z+&CuOn1q@TU|(4_N(kX5V^c!|y-q_ge>%@V2uTOXlA<_D2va45sp$*tjhiyUP{vRm
zFSNA1`NMoJFE9>GX*yrqCuqu-W_a`bGSH@J8s2a1bFVBpwyrwgH%q$v>_2O-z4qFF
z*WUZ=6RU)7MeTKf)SZv(ZerbMuRuOVHY}pWo6(4m%W^Dz6vxt_mX?e;E4?8~7nliV
z+pqu)4jAqha?ueWQ^}FqnK&tm4{lF?CBsLZI7bqJu+tEd8&Sk2m6L*#&e>qyH;Nh|
zo+8&IiSx3d-2yHUPg?U}+?3`WpgUeU2tlpVO(>U)EtZz>U5LE2!I44BWH@OU#pImN
zVoWO8F}jXQDU4**P%*tZC>Zasm;<##k}ZQWdT26CSEcN^BPGhYg%wB?q|meyh_WWe
znTaTl<v|$!rl3K-ccgVV(>$WDg(og36Yg9~`g!mvO)wpt4?^n|00}@Hf*3R`E(Onh
zlxzkrlJ&s@qls_>XzRK3V@4V+gk)YDioJP-4qRL8Yzg@=Z{*`;pp+-WmTu-+Rd6s*
z_%szVL_OIcUq>i_7PutuqpUPM*A5NEUhI0~sKTT;HbyK2qsJcJ!BV_k#)Vfo6puvi
zC7OY5GBe@~1!Ea;M#OPOYJ>o_fKFg39h;_#R-k)gAr+52hanYMUlw>{EQO@DA`>fQ
zLvD}Fr^ydi<7flVA*+rSVK1gDV;JgklLB=yIGf_79E-}q@&&a;<g7ilLCw<UvR%bm
z9%`|I+zn|-Pz%k|3V1E6XJ!<Vu8Qv?0FA|fH|oq~G9BfSQO-WG=xI6cRIDdSW0Qq}
zvkY+}D*38yo+P+wu%Xiq!Alu|4>*|Fj^bY<r|4OTBVp7#o;E8rG&*<dy=6PDx`6vr
zQ&bpU`JZ5(8$bI&8E>JL<+(WPnTv*`;e9h^wzB33QfurY{4l?oLp1f(<KNH+Ml6ck
zSl>huGYPU=lk$3D{-*&&K&dU2j3;z4H{xu8_C}VO03M-4@=~i{<1Z0V`;S5CY05uX
zb1<QQJI8IxLCtMTnUqv)r@5zezJI5po>`YSk_anK_Z7br5oEQsS(#4jcS@wQy|x}G
zyvaq5-?K9DT27n3k;a45aet!C;cMZcX&9FMa_S>_e`B-H<h@PJZn9<BHTDut2Y@ph
ze?A<)DEAfiSA42l^RlbpYdc+yT@>qqk0WVjcNG58pp=z+Z&h^Y)z$Fno@xt!iV`x#
zSFd5(@Z}$LkNQ1lCvs>FW%lRHKg;BG{0NhU$#W!Rd#b`*E_oyMlP^)ar4vO)!)UBy
zlwi~obJb&%cw!7(GAzBrR>J`}PY>?nxcSRS+)Dbs@4DoEDY>w)zVQ%z!kkQhB+U6}
zGInUZGdQxqmW6J}TM(jir0swE{46QFYfvhGmt|T`;$+O1r109+<o0>;Xmoe}w^4D=
zPDuY_7iH;H*U%gu=li@n*GTrHsjXmKkg&+{)t~hxdcmvW`q~divg4^jA^pN1iYK%)
zSO(sCY*?m;k|_J~!yaeeJ}7gk?n1tXF{mdhKF(8v;(g@PPMR~sdg$wNSLNxv7d&)X
zB7HBYJj$D%asx`c`(3oETS>tZsSg*$RTy33YH!%v2%Njtw>9i|&(feUeB@|6qK0N~
zfjY~=jK~ja;i!qXL(AF<2xTnk+v)zU+wKOw_PVH+&7SE)+%20+7T3v}?QW4y0PAi|
z!CMx*XE7vnbKC+4g|IN9>HeZrGrlk5rZ1Jolk3F)>EDK{G9>-NrQ_w=UrM5&#^0Dt
zzUH2bqQ;Y4BYL#L7Wj8diT}>}R4!&C_faj$)ID$L9<g>|;^e;rm{7sW?29Hp^aYvX
zC0}c(C*ZKp?XF%u;dwe+4N}c>7*&p3NJB3onxEu6(3Q&sZ<NS}D5_U_8Mk)x(Sp1H
zSg5;Kp;+`H4;SdXTHv$`-gu=p6n)$GR8Nu}(z16JmbDH5H!WfB&5LR=7x^Iqa%b@S
zY{uImrRkwPyvna{Y!~8=5GI2I+iZf+0mxH0{{@<t<6-f}+8IkhK&9Z%l=Th|oc_j0
zyZ1$t@m!xXkvF8a5zNb~mRVPq0hsmCq2la!q_@@;Jyg7rjEsLs)(rijuk`%%oYC^L
ztK?{Wi)1At<nwzhrv*3zG-0QCgv-?<doSn}kY`X`=X&BJMr3c@jN@l{#06MZruo?c
zEjE=aW7gv#*8vN(J;~S>!Nb?0^2E&7f&xOvZX%#cQiFFT5|oHuNbD$XX~G;f|CxXL
z(wv?|ZAxexC|SdNa;Qlw{gJj$$ER;$aEvh6Mw0v~Bbm663(H%?g0sn?*}~>glBPFa
zXW-f<216#MsG1{8dJYM5bggL%UXw!`kllNzp9ux#j8Z4?dD(lCmS`Bmw__mo03(ob
z{3C^B0GNDQH*CFt9c!Rc#yV_~+cfBkNvZ|oJPkwZ7-TXBq&^1LvXV`akvOXZsW;&m
z<ewK6n|NMeUiMXhc|enNpX=4c6uPSL)?=HoMhhjme;&7kMO)!Rd4{&CGmnZSs^Y3K
z^9(f)-b#fL$!4a^!N(A+bdp|6cbeY{GO%N-BxTcaO$G_OH*}wTQ)3-cGZfR+Dm)iR
z&RnMk#oL-GYhTbokXg>2)Ctho=HCo%_+^n*sik3D*!r%xMM#vO0ZFJe&;T$9=>-rs
zc8cSTKXTv~coPNC7Do#M7TJjhe|Dn*!`KOYm&qs@V#Z5)7LWsuday<C;B37qaxlIS
z(uI!G+4V#~LNgo+PG<rG2E}#*;e|uM*eQy^P#oid4^KudNrryZRxd>1BNTY>Y8VV9
zHhM%d{LqJZ5!+j2gHe77J%E~HNzj0pE4YVHI1O1z<7CMD>c>y^euX<1N6-$fcUur%
zh^e>6Z!>rnTO)WSN2w<fG6)rF5+9fQw#>#N*Qp(ra721KA55R?5uUf)D8EyI3(*M4
z`JPA7T#obZr7TgE&nC||c9cOagU+^|jK^54BW{CYNux1LIJNt+O+Y?r<c-kT?&wD2
zWa=FlVk?^woXs$TAe^fiM<^|(Ak#*-6Id#<{Jg+`!_weq_8ge&l=a_D(1%4WpQRo#
z>vli)ETvslmdSBrEo4EW=iu#b6yI$ecAmTn-)HGx<lMAhj>pYQ!u`i%F-q+ke2?d=
z6xe{d$cN{WMo)G@R2bB2{2zmMOU~#qDv{pS&d00ex^_UIgm}pIPL8c^!150f>+%a=
zmuy<#I-S*t%KnwIA6-<+b2nOnux?pmJVcjevT`fm!E7Yyeg?z$SG6(Mi;Vv|abeKY
z%P6t;bWb^*c9dhR@pCK2u9UuUKlN?MR5p00uW`P+8b#6UMe(-yy?(%WzMpSvD9@$A
zS(kAxQ<CF!v`i`jYk3swd*N=DKL0<IWzZd7MzMNgIF8Ilg>%KvT0evbMeC+6j~WeL
z<&2($%J_{Fa;3kMC6@E(g<e4WcrN2)#D*x5Yk9RSdx5Db@!(8G-SG*tFAZM2a}l|y
zu4GRC@zj!a1vizB-4?~p;@Z2mt$@IghP-|8OeYV$J}bCus$rN3*(WY2uYv1M0DsYk
z+3Q>Vd=%?PP0zL%SzMjlj#hFV))ykxC~@IifcCy@hLS!(>jQQFunaw0Re6l<yx-fN
z#y9vCkuUMFk(srUP5fq29_sz3%Edn`jBmZG$5#hGEY1_pJ@;GAcwZV|<b4P?wS|YL
zC*PhN!=n+Rbkkq__cZaly1bCZJ$uxubq7%4Sm<Y5uD0IvR&Q-ZEzan<%meoJ$gzR5
z*;x2MDwSd}A2O^W?Yp}>E<ALpYW&~|S!ti)@c3pXS!1jtXiQi2^Wj9n44;I2=9kZR
ztg@A^{Va>kP_qEjXD6LmtbUGHhs2M4#W+iXoD@%e>P;?j!tC>re{Y%Y4BEGy-IZHO
z0?mV0P=(a;ie&rw2cOr}&#jglT*88HHv&BRw@$t@9dnu2xoYRGlY@KDa)sUt`}$oa
zDl2Mh@84HkneI$$n=X^VZL@sc_M>aEyLNsc`;e3FM)YUsOv`~721@D2`yOo$bPcyM
zlgPtLTszlrn34iwJNVcckXZ99=6j~L9-*BB&J6#CvNTqyB=2=}wO4v}(8D^vw?LVE
zO+Q~U-HQq^*H62p3K+OxULMSjhR*$AuFnlN>EtH(XeTUllqN(Rw}Q+sJwRR|A9HJz
zZBIP?h{qJFGbtYb-_)L{JXFtM>tyVVJzukF#G0xz+{Td2`$)ukb<cjj^o(LyQL~@M
zu@@Y*;k4)n(%5}#f~0oH4cfy@<GRsiJbPJmg@3acyBgQ-oOJrf1?F^7G}P#!r|z4S
zX!bs##VrG1AoW!ceWopR%Q>R=(wfDZ{-_j6D|m^AP9q&!;Ha_2{2-vJP0(jsv63<t
zh*!x>3rMbCv6mBJN-2%p+nD&*fO^BWSfl`}dD`Y@;DgyVs^YAC<AjMF))ufLmD}N?
z?bqp<W{EUy{x=k&y8KfSA&+DwKuzso6jP}iSFxViN_E0Qn7t2)sI#D|MKV;#%9x6J
zE%JGfjc}%9iTaw_wH(WXcY=mI8jG;iRGv04p-Y!hf5V+8-2c#u_Lg>Zo+j_sV>;NJ
znTA>C=kCEEKV-x#K$)KoMQ&M{U=r-|1bh&Ph?i82OwEiOT9pik{}h`@LbFDD@QH7Q
z(}T9K2T;A+o=ZM2C6t9;D-m@8voeuCB$=8atYoev_Cw)4uZ$Emzj|ehrNvB1y2DF?
zO+&2E&r~4w5I>j7n6OJ2a^)U})cmp+p`Br)$rel#-zh}sHIM*dxHB!f91$NlX_8T$
zAc}8AgMwLkn5HdZK(iordoUgUoL3~=pNNv{<#=`mjWlrI?*eY!9J(+XB3l5>PzzKd
zyRI0pl&vQD{F<(eb_|cp0}%PA8iB54z-XDOsy?qJwnVHkr@T!XWWFRtd@K$sShrZW
zOmD^D8>+bC7%?Aq1LRVqwF8??GyL1>$+xkrJRSl&8Dt>{z*AqmdnI-fyo`zEfG$Ej
zA<Nt2b<{m_45K-y^?!hh<6Wi;Dm)wxHNO^8kD{+F7Y1pJ-sk0mh!Uu^q1Ez+ThF$4
z7%g%~9&G{dsh`JM(xM7tuMtj7+$qILJINPN$c3#Qh%eI)72h(b7Z<U3R5%jLQ1HF5
zVKb7zZj6sKxz|&Sl7V^Hd8pEnL^fF((WvQuE$LX`l3;jf7wt;h!VN@UdW(&N1i##)
zE&nASQ7^ZSa(vNAb3C7A8C`k5R7`EHAF(vptr^%Es1tIS6}7=lUIxCGNyBkKi?eBI
z!Q!wZ>DX=6R#P&s)53^wyl=(+qC;&ZK`unf>d{5=8owY$G1e2V20}haLud}OT6?aE
z8i-$T;W;%Inq06iZJ@R`BGlHzR=Wcvb!px%EA(@o{e@VEF1NfiG3My=^%qCczIHh4
ze5LovD_8)!gk;C6!u~+NpSg4DzB_EUb&e)X_S4?Mk;&~gSjb1W*X%QzO@AH>-OGRy
zD*yxWdu`Ivg#a(NN+D_$#ac@9rLJ&8?%<K1ub3<kb)@I}>u;hK6gVe3K0@Omf)Siz
z_Y$?0Q-mV*dq!obK1`2mg0S7zN1ww|zdIV{8ePvVL3!`-I}edBZi1S&(WWD~pWg1}
z_ck-5cnPl8mw0`NyQ;oP30qVs=;x|+_2#f-XI|{niSH&!dc(zN%xCmPhT?l)#vpX?
zpD$A$%Yd)Z#bwWPdMPTVz0@aO=8x<is+f(i>HfKF<gN!G+>ADfsjYJC(_F4RbB-Ju
zc%$^YukoJt1$T4X?adNh`8aGn%GnguR+)PKlC<$xf8>w2UM?;8(nbCHj%&Ps%P!`&
zg-ctrx}}-(2`d1Vnb*jiHs8iUa^4KJ2v#E~5C211Ws?ioeL<wpES(^m<&90-ZGDDn
z!S@xzZ2Zt=WNB}7`>`j8zVjY#S-Xr(@<~WFC3WupA-SPqvyTTqg%<b`@zpu1ci3(H
zF>*F>b%Fs!PkIDQa*)-#yRtG<rvqfey4QxqF23<Z8B6+sya0nj&3(N&$~{AL7@)dn
z<#Mvh9H+0q-4RW?p}#pJ{}h(Q>Xe=JJ65q8vcH&)Z)DQF>Hq7B^j?@tuOiuWv+TXB
zAhl~>kfgcoDz;u{r+lSBcUfJTl#W)I0khkhl~zl0-7McQ;6Oot??1^kBekk*{rjuw
z9xOW@pkjLS^g~psF)G>UZi^FIY#vW}2Q}C(M|<x;Dg-;`9bvci;s4Bx;i)`Itr+_W
zPD3a33iUxsTK8tx)2T#?k~$!-iKFPTy&M~!qqVW>#%UYk(R<jnd5O<yEN$xb)hnox
zYTD_eQgowaBGRql-nv#yw(aLZcc&U0%}rk98!i84{;a3Eyi%o#UTbw_ny~~jfJU6A
zt@n|GGm|y4KFi|!s8I5vB!lBUV-40U`b#qEi{-axD!)Hbk-na!mZCk5exhHZ{<3_z
z*46Wn+z8d??l^7yF)PRiBY!Pd5KqX53s=hFv#ZPFE$Gd>A|Rf<q$XqhV#q?@Vx(fX
zIOG&Ai|i#Wa&*?Z@CDUFth$6zp-e|p$6=FZS2ZMB=CntVMQt4!C*TAN7D-CW%SYyI
z?g&r~6%wP6%x~Ir<_oDn&Fp}06HSx04PWOi%=mV}(#aqxK?U`Ue&NkGadn*v*NH;I
zEhI7mrZaMCe6*8X!(9eV{L(EHtO=yR&$Rvc5Zh^1+*6}?^bN5KG995ClO>18av(?K
zB`A}KonFi#7p_JQr`mt3e&aknIMQYwKv!fq%*#W`I_$q>9ze*^0YqW9O}0xg8YW&|
zAZod1Ug+5uV3}LI1uPAYM5r1@FZQtc15q!dlVj8thhMl(gLDHc<_6kyy)abeyO~z&
z5U4?)42S1(jHa`VCj{pV+iOTAa;P*7^qibtESXlsq&VYbrHqlHIp87_mjqkMOkpe_
z2B8)_;>|WQD6!|5Ny6Md9oZ!5qy={bN9K)|QWrLPM7c0VVo3u8x=@MD(E%Evcnpb?
z&@vM&W(2TiB({@LXSpr#pOO_N9b4ItNoCaV+MKI778ZxOUjfk6$a&~m6A7$_Sf+h0
zKwdy+hVg;)L`MiG%YFeG)>w40M`xE#2OQtRTq6lYYq(UgvMNI9gs`vU3Y@^T$H$tJ
zV{b%iSK>NGpFQXVMXiD>rrbeG!3#NyAz0O%4#7(So6mZXyqN@!I0l7<K&y$j-~nxZ
zW-blw6hl>&8QW!Zc?_5t9Bd1g?^XCvVZis4Jv$YAI9xstD*m}TNznP&fzHW>mmKJ_
z=*=vGLwVU5*{$fK=4?YA7+f*wP_-J0=*V~L$Tz#B7C$;bEg|`3fkl{3OQh*?{3i75
zN+QcwLZ=DPpC+33yr%p)dKMYJ0fB^2#V2cRKbzK(I9r<w>GPRWUxLy5iZYDS=R5(+
zUDwp=5wN{=>d>OwGjPF#h%xyscxSgY?`B#7r+Fl4mEC>)gcluW^lUI4Gk6W8QCnT}
zN>s1CQX6=JS{U|L4^wQm+dA+)NgMJP{EmAOyTDj4P#<wf*c%HSz%l*Oclb9ZX?VAF
zCv_Df6Somf?`ZX`xA_G`{+R+iXge9NbsT}>daDrjGANrxwsVuG3mzSefjV!?$>EHB
zkWyaxjMvKQT8YNiU2HHb*v9HnbY!!$3oLnwEM`qD8)MglrHS{PlVpt#PNwqF6^90&
zTah$sD`c$rZ3YykJ9i_qEb_(4!X8Of_GGNg(Ampp9Vv8%%>Un_!UT1Nb|K2mvMG;a
z-99prEzY4bghRp`J5!?;)}S)P?xyXwjvw6+1ZHn09ztz(d(UzD=~c87)?{sOwPtE7
zyR9sNQ|dB#wzoY>33t{$;o<?**2FT?31aus1c$p;Dr##gO^L_%*0bKR+Y))OS@dCG
z+4GN8>ODZ+m6=)E*mPIV?9{hp@5sT4ptef-FEBH(lNX!T_XSi#Ujkh82UN%k1)(20
zD;lsOO?o1GgL6;eU1^#f&qRNfdi<R|oZ9|<+UfC6C-v!TiqgCR;kakXSYZ{5F*Rw_
zJsXyX)+8A>3D@;Ei=24+rpu1}tSSQ+fIIjvQOu>Z@tHqf7a9K@Aug;N8Tbq}W2T7$
z@CAF7*kGEj<6RQf<?4I{w0B!yF-gu*7n_56H`8ELlN;F4t~c`{xpuc?$Mz<7DSLJL
z_P-R=)>gk@t)%{`3EBMh%bXN1zHmG!vPedAwe<z7TAd*}cDUqqm>gIQn)@G-8sVV$
z@>C-bDyLbDrS$J5@<%VEv9bVg<W7myLhPG8jbfC#p;tE==Ft)E;(cFBY4kZN1ES-w
zhd7Ic)|jNXtdZtOkxr_wt6T3KkZ62&cXZX!x5)6;LgH%AN!rYI@Dc`lkJlq9o#>I7
zqZI~-@0P}r?+=Rm=8MULlOJI$y6199!W+A*S8CoZSR$tfFMa6I(<4k5*KN<&eGFO6
zppR0Gyjdf<gtA#WLgTP_x*aDEZ*qy$bNpJ-Ib9_UZlGgbuTVp6%{LYE;MdSqPwb`Q
z)00ky-PR`v&@PfC$E^-BM?H<1XzbZZkJuyYh1RX1t0_QX0W4HoWevi4n!tmfO<Z$>
z(2@*zg^5Wgqk+Alz8u)uY6Vjtw!&pTBb@f*$r&0QV4ji+Qy{gF(l~>7<7^z$jBHzO
z#QV#15)ZDD+Vo0VU>%`7yLwn_cV@fnkZ`ms8Sa)@>fqB>5C04FZ{&F7?Ek);Ql$vw
z^<Mn7bQgEeXC>y`4*}lju~>^4fRUmjTw<9hG64e<8#68pK${qF<amQ9Q1<(I22jj8
zU3XZ52+|qFhiY#GJl*;{UwEAwJTa^<K?exL)zET5n+<R|JHc*-M*-n6z-(m!d6#$i
zJzTmokJ-VZwH88s0ixP_tkqVfhA)|D1$rS>^RPQAG^sHEfp5>B44JQ6fdNX)R7a;@
zOD2jmUN!#52*I)_S9qNkt|~_s#@s}M#jH?JqbXXoFat)t+_I$UL)sK<UKwx#j-NFg
z=oU!B=Ilm~A<irYgs3+QS;!)rr#U-Ejz1yGgiAmlH!g?aJR%-BnvaTYfj~48yU%7Q
z5GNU{L&lL4glK|}=Q#@@oef173E*RUY^7g@L^w%02T>WU<iT0e%e3F7r+`-btbN;D
z5qRIFtj$|lJOC@1`4}y@zMY?+l0-dzJ>wW1L7kzrSlYB0-M&0&vtKpuDKk0&hns~W
z$srOKDw?^5_*sCXiwk>2DM>1Jv9s>9k<3PO@rD%>&vK>KDH6$HUmEgconhwnU|e-R
zMjERHKnNhQd{ntV^Gr=ZFW}4fqzom-StHGmbdHbxv@nCv>mI^!>d-YK(#dOV3f+cM
zH)AkD`H*a0ZDS|&4-%<$`w98QZA|CKGBji#ukgmQDU?a#32%W>kshLT0^`gZ63_6^
zwk`KhdK`*0EKS6)H<cqTVRHGAE#{1nFDF22$O?rNd+YOr0hYw9bd5{=;MB~bGauW2
z1dN>!$sC=t5t7XjoyCaEXi<n+HZuy&d<d97K~;)9+jlZKIl%?70i|x`V23ZuhT9Q7
z7zIRch^2a~0I^3dY^*Ydk#3JA98qs6>sH?8=%ru;cNhc^2sLRfj-w>*&DR=pK<R~(
z8{pd6A?vl-C@9MTI6JBu!9W777+S_k4o#94Q#<$bQ)Z@}VJ`7%wSPT%nKN{H-jv6F
z@(?Jjr;J(wk!&NMtwd-iHb2@1_I$FTSdCgom}|+%SjTRq7g<LilC=u7p5L5#!;d8^
z&A1-hT5dRorfrm_BpMZ18Rt$*M_>n_Fi<H2!*MTd(BwqH@E;MtN}36f3Tpey);M<H
zQ?n)H)i@Faf-fvPhqNN9NWxC6^As#aXsu|nNxm5Q)m6ZpqHs-^)jEz20B1C*s>g(u
zt;AbT@;?nBBmdK}=Oe1wtc<)_OgKw}kK9589~@SlS`^G;PBlv>Kn%+SBoE|fJBng~
zf-zsguGUIySdmi8CuFDBiPZ7<Uj>VK>Xgbduw9EryDX@IxqMGW+np3-5?z!=aA-$C
z`#@aHG<gOnP(_h26ee>IW+AR+v&TtE=OOBOPErbu-2JaGM{-<kXFND_M?DX6o~Pqy
zJlb<HEXueAIWx?cwVE90QWwjo<$ubDb1iQhb-WLbU|QQ1TgkMV=0!uul17bwB_LWX
zW2PNzhK?ZEV_~ZUjv;0^307~joH!>B-+^(0PnUfQISFb7BMC(OSe!Gfn2(Y3c`ovT
z#1UFk-d0#Bkg@}%im%1Zi0ciZP=AG#2|fubxMP0K{39Y*a>7P@46QZJ0*oky(J;Io
zet6~+4%5Vfqs^B$T30U2{FHBrDT)~Fhd?ltYuz$AJCz`v(FhQ;h-u)%f3S8mNLUT&
zer5oc?>%9HsKUZOpHj&QrE#u_h1^|OpNTZ%U33b?B+;&(nZ;fX^h(p!4N=X=2NJ9`
z1fo;s6^6H9F=J<eQ=BXhMM}OJiN*m(=`%eAM54A>v@CFj#Zi<zVQHEZ*q1*9Qc*Kb
z)IU_0oDVr$vT3N-M?qQbxXIF{krAWe5V>|~EJJ17d(WiQ?b0$rOH8!In@}Lvy6Fnb
zl28TFGD1BGm7@=<IZpta3N|xyp(dU1KDEs-`Pl?orr@fTT`W{vtKPst<j}NnJfASa
zZVm(|O^dS_3X9oU9C*UzPgq48jgYd9YED|oE(o_I$LJ&wpjn*@%;fbupe-*+P?Inj
z)=201w&_ZLB+@j>_~u8Zo%MKZ<c#qsI!-8qQMXj6%DnkLjQSH)J~#^VU>;sE46?aW
z(Eh|V@SRU6gq_B4=Fc82DX6_28s<<rZl%BnR%u|99NP*nJxu5ROPlpgPUL3DZGdsT
zEI&PRm^kGUC23hb(4FkD0~xZLpFw@lrH+jb&%GqdceZADkq+<U7F1HqWx%fUNe)Qn
zA}0-Jc~|LCM49*u2Q%RuA=u^dewWsNLn8SUga4jObI;`I9ca(vIBv6YSq7-ZOxS<&
zd##-ZsD}?y-l&e#hEX_e$n3Q&6Rf(+yVp*8*{uz|jCwt@F`IN;w<4dd`egQutT#TF
z?-!j}km+Mgsp4nG%H8!D&ueqS{YKq>z>WHfzqMystVMDQ{BStVb9+H#hdbL~`w(iU
z*Y5jyKex{CN%nTg5>K7vIF%gumJ@d`XhZoj><nb}d$^NB$zEIJpSZB(2E!$#M(dXf
zGXA4$N@<$jJj!P{R?rRp33c>^?s2W0<yK7@P6yDN&dAq6+;LRpx0J0Uvm;X~dOb@v
zR><ynH9z`bHOoKO6~+B@OrQB3FZuv4c^S$je~pZXSROg}?{F;#p4~{Rl$ff|(gA5&
zl_+olYs_6U&dwj!Z>GpA6RBq3UCXZI)p684`u12pvzL{CLvNPJ1N#*3XmTR@BMuY4
zP5l)&!ua)PO09y-?&Gufj}N?V>WKU4im9QAgH+NND5zz?RQJcpB_j7->!kPK_wSyM
z<8CTaOVC@x`)h|$tCvBr^2BQ=*{-Cq&Adh8J7&5@OkUH^LH_{bN4%b5qt-UpL+hc#
zWa;n*ncR&6dF)yG{;7-9*<B`SJJ~C#T9K1Zpi=$K{v;jcU=ZgcRr`t|&YoRSRM&zE
za<BBgAfiUd7~1&E1mhPLTQ2cOw`&-NDjdVL9YJ@`oA6!^?7BxH_e@pfQ@@s<04Jp>
zA~w&Y?$)0kk_T685H~Z{JCOcoL#^1x`ig4yZ0|tgr#HByblucgxY4JQxTJSTyn9Ua
ztJiGdNcgRp-0<I442+aGpL_88{dXTz`tf_-ARhXiVdUcJvb!&CRzB3jcJ|E+VqHgM
z_95~f@i2AK<j?^c@-cZxnqQIP+&a3YTEUwX{Tg0Cvje13lGH2DGifu89xS_A7JkB!
z+dKEF=n9g*h3XpmXzPfd5Qo_b^pfc6NG@<^IJ=-qg+ssCn8;)eZAKcRN0*03%lI(0
z6{|C6=@~N(%4BhlT<U*u!QIJlSvRX{yU_UgDwEX^I<zu$T~VISyzq6>?s0pKo3!E?
z!o4k0HkdCpo|gLL`;s`SmE<1x+QiGA?kJh_eVIS!Q!b8+Na-E%*OLaC$oNoFW*6KQ
zfBLG4_ciy`s5#4k#y&E41uqV6ekaqp^|3z@#~2M0@tl$-CxVu;sU7&T9-CR+A|4cp
z1qgvHyRG{&1I2akN+vf5#jXuAa6$5R;%QkxvIbrbu`8n3T4`?(BWFp@gIX0eviYb>
z`?es^(p@Aw!_S+?vY?#LdZuz@>gR%3&g|~}bn*R`TEv=>c}%}KI3zwwM^<l2)6a^G
z;wMQ1139N7WW+0j@_0Y@!d1oVKuLxzBVm=3XD8V2;7pXC#qzD3np9ly!Si1QW5lz{
zfRK6+GWpRH@yCsP?)EKTlYY!zc7VP#_Cea_J0Xcg#P0}v_CV8e-3TLBW|T^evgPh>
z*UJ<$kKYInXQq~XRJ9Z~@GBEndA8X!DcGd6Gq@bZt37G5CqTL8RAL|A#tG{&z9}5p
zw=^o&W8v6Gn^m5Yn5fr_)*&#XxZDWuS0IF>pT2-F-mNP5gw^Xf?Usy?WxzBz9$GfT
zKgf(Bb|**5>$!L07BYS^R_-RUGQQz}bNiB^_&mVOWPo#4O=nh<npt8CkHnNJO<7E#
zzp|h<gcKWX*Xf^qCa1cEE5AJ}g~?y)u}W+`|0{u<L}yD+)<k-75?BdHQMsiF48JnY
zDSSxQwY+ULf`V!-X<gOwwTIe|*4j&p@kqx`tCH-b<$j38;Q%B{#*=Z0{mcM1jkx)8
zIuQ?&rQxD-%Dm%x312tQ<1A&4$@I*%)>-!RcDNy0y7SCpRdX*7>XRX&LSi`Nl4zr1
zt4O^)?`#vYM7A3}>W~=Ug8tauAUFz1TTmN(+p_dCPKHlLs8h8`c9#v`rvyX?@J9bw
z?L=-<dBlAANba;fJ3#{?Ns-o7UL>&)EsO9pD9D544F%GA0M_ksOfavajO)&V@$x*?
zdHQNw>$F|Ul=_|c)$AN{f+rhe5{;BhT;RS!N(7t|4AHkZQ%jfjRtxWVaaRaoK#i>C
zwoay93-f$3joPYC&WOF?&lW_sa2<wPN}r3$L)*4HyL4R>=AO;{2kF5o_FC9=@Z2l}
z#*^eYT<D#amClf@mvDob%G?Cl$%IvR8AIo<x7nWCv4Bi{H7feqe9Guc(05&}CW<Jp
z1nI7LcayZ20Zr7_q_Ncx?Eht}t;{f;7Mez_DSMf2x}dhYXICY1J0C}pcVFP*<9BoB
z<uaMMWQJE)9q&r@9*xG|*?2Wg`J=;8d}hI?Gw-4dzLNMY$IeIU6)OJjx4QNWGweHs
z#Fj83u~%*$h<xMNA6a=C_}rX3pQd}B6)`1^+S>9Dfu}R-I*RnZu+0Uv)$s)Y%Wn3(
z7kvWD&LJoJu{1sx(dm9<LaK*jk$+RrbaHozVff$j{`K5yox@YJ7lzO_&d@ejr%N*U
z&)7FD60CfM0x4|4HYSy0q*6I6*Jn2!C!hQWhWru6^3iuQJNkV%o9PPefJL9}Y)m>Q
zd!8icf$q{qbaW$q{n4&8`o?)KuL!+yviG8fY`JMDDB$%!=$3Bx_h+!$;%SwyjahNo
zD&0@+WtMhrm-7eqQCv@-#V6Qa74N&^AEk2DjWpm#-(Ai2AIQd<)nfmyFJCt9hTjoQ
z^<T462CsUbt1it`9-7?q_8oH7_sH?>Zx~!uMTc*qm*kDMTn@YL6nEMV?L<OZ^Xf@7
zhV?Ro+B%{U0s~BK9Y26f&th&p^EnYae`p5*b!c}nX})TcB#+pU(i=8exq!!it}V||
zNXvm81BLGB#a~WR&PO`^d6y(j?o~03+$dNPUHs&VP(kd_=jcYG`N*owr|&8_Zw^B_
z^7sZ&toz$$UY((^s~3i!ncyznbAn<cjzh^7&rUzy@NJF|Us~{@7at(El|&z`FpY?|
z#PQQ>VdBX`wr}UVnL~YfG`ZigYO(7=hR?@bI`rfj;>z9+{ph(1ld&JHndz_m!-&7T
z(&c^ctt7Dwa1R|8zi}_e13uI<F5|n|P;bSGtw%&1%bkbezcab!5&314OG(@h*Fi{g
zVt$Q7ZKX$?9-xy&6tbr{5%FSM7S<1+NDr|vRh-E$yh3fw;at{^kBjFldq;3`bup9U
zZ&o{I?&NRsOC#r3AT55BIeRRCdV%!Mvca(hIxH8+4k|Lkfp2>*^-Qxr4QlITJo_1!
zBTj}^V41u}{tmAjP*Qu=7LjV1^ACgc2(v4)Y_8X7^0nlVNY+Fytn3{vZmBjl%Kf9~
z#N*wEx5ke%3eMUY#?)_=M&tF&?+->)(tF%+p3st}a&i*UU%^VmW(v@+(Kfnc8Le$+
zW&z}*$GqR^ECt83nhz@l7+x4jnQf;>^ME)naC1=1HHt2o!EokbohhJ!0T=8`8`YXk
zbD(JT!(-X07las=NIM}vHcy0{8Yl@lAFR2-WE>i;<QMp##;UE%ov3%+da+VVJaqFo
zhEZ-29Ks&ks~Q2ALv5H?7q(J$Y7%Dp36Ji8+x_i&1~aSCx4GCFnOuwJRxQBqLW#C$
zo%*48A0a=GJOPQRt&5-|J+FvYMv3MnUJzAV_VA3wJKXd+{LO<YQ6b7e>~mE?dGsc_
zkj^~zVv9wfYIt(MCD%NF;UNyM&=^bht`+&xMR_v}bt28l7P@&Dc+hAQa<F4w4LcyQ
zL7_h5f}M6@7@4MslUNdnvC6_EOf+baq<XQ83~bGPZQ4T70fSU{&$yJYH86>zZOecy
zVNm_OZEj|^;tcp!jNmxEp%&DtPAD2JM8`97%dWPqSmDuhRC$lpOT;80Mu6sTBEY`W
z>;~zG3m)Dy0GTi!JcMu6nw6gcRcko_7Ox6`=~FXFk&{`8V)1d3?`UCn{Mx{5le*xD
zRO2&pe!At)7m(T*%X}($b*ACaYN_`jVoUgu!=;j_$8ryLssN><>&%z`$b~NyV58Tk
zT5#Nu0)$XhZKBq=gc$51G(XM3tTAkLT5J*p&!r9T#e1X|xjdI)gU;x`5@-+|AaCv`
zmW514b$+I{#!{cDV80%&a&AMZl2Oaw5qr`-#q)AiaOaEH?5BrN3F^saFpgQ00B0^+
zC5*h=&>sY!OT`B!c=t3>YYr_@IcdcoDKBVy?f9p927HgWC=Z}6x++IY`gj8_ub$TJ
z5}L}Z@*oz#kO4`$8u66jbI4?Xqr^a5@iPPw)6TW|h`yJq$*XFJzt05cb0SNdO7L_f
z4mxHPzT8YwW{c<8gV4`8vt!Apw7Fv`^M%6bAZjaLLt&Dj>yiq{@hn#lvD+%m3SZx{
zp+i4F@An=ornc52k21nty3uYj+*~0Qc{eOPkwl4h#mkZJOoi)Kr1>Vk&NsIP>gt&W
zM{E<!%JKg*pBTtX^d0l?le34j`fi;6FAEvB`~t;dFc-zv5lZ1>qxR?w`EIMCkDr&f
z1Y2#8SMzJq>%6o*OX@PE%()%it7g*QmuAiCnCN|iYVew9&(N_d<#|O~X1A5EW6Pm<
zpdd$%S;Kx2rgTy=fA?59`B@)lUEW5SUgw4g>j=HFqbrUdi1b?Cb8N`Lv3B0Q-(QI3
zQM#8vzRA0E9f7#|GK%ibZ;CB*$xv&z)jnAN<oCF;$3ErY9%lFKk(ExSKODvWFa`Ph
zUQ*q?$@kv%4tb<Dce{)RZTZJgvv<8Z0t$&%sQowHHk_+RAK7McBD*hU@_1L$V|l9o
z?9RNtS_|@rVlQ7?I}*<v@_w>h%3pPJFPxvF?D-!aqz>Q-f0o{~DLqL%`pebW>PALa
zJc0PP+~krUy?ccuuicN|1ZfU7i|(qd;P)P2h{~=Ixuc&8biPog7uyp_Bl<lSiGM!i
zu6i%6;QBN5+O@N{%janN&E7Y1C*$$R#dloo_I3Z;4qREVM{rkM&taO^Ml#y9&PjIo
zMB$-7YQEbF=JhY1VV%U%pcGN_lan&Ma~Jc3OVL@_Z6!*E+Qe>aA4fqPYAfQ^hr0&s
zlaQel^z-x<yb0OwrY?#XsI4Di`(lm>$<m2JjAS2w?JBwQ`+v@v5~~cg&kN~h(=WSd
z^o8x=c*c|oU5!*I<J}YD9$6{=9kf`_aRh-zn%zs6)nvD|Gz71mpiGQQ=rnIA!2Zy>
za2w!=PXdJumE2Jl)RHvOiLd<yjde~U_cpqo?JRvC-Nek&5<qRORDOa`c5X~ZzHo`3
z8G4K=@GHFO_KqJosrrJv<G|&Tz2+~v<v;~x{L5eJ#1`RjraQk>k`ej@{WcqxHVVwc
zEz~o*#sGR-RGJT1%2GOqH65Qg`QbXZFGX*$XdIk*P%qnw91vgANU}|tH15W73%@7m
zY<dn9U8HYm`4GkKSPsWttUNkGvRRX~#<C@9E2B!BjVo2`Po$B&oX54oJOTQCrXF)>
zc8zxqOX*WqsNDEfr`NaLR==kfUeh~)e;QkyT@b5Mcq#l+9MlfhROW0I^9*uz3wM9}
zYb5J^0kzeR`zW7a;q19Pa=bUBh=A7+dzhV8WmT-v<KxkDs&#pIYn1uVf>Ims(f-nq
zlg$&})Ybvr+>qsfYxGEWbj5_o!;3y8vN*2K8`@&e)45=W&qrA(Hf>>H4Q_H0PU|L(
zJV3)^YKUr_Y!P)#^aE;;5?Mw}`3y5hKfSp+>S4XHmlP?%EL*Kc!3q;1ZOAE`OC$4k
z{HGa*N5@+s7T3GP*4mc~^q_^N6|4cTb6I6{a9~bLKUl`B1(_`x>6I}H4=`@IW#cey
z7;0G@XCXuEv1~8IydfDgaF<ohQJIfwuG0f#GH<~~&xAnCHu#X&;A!)zp**}DdWxqH
zeopOSal2XLu<R<od9VOyem?gKiJ*12A$MD8ICe3#?Y+d)iy}1f`wWMfm??-}iU}{)
zn7GHx`xTJY9eo6qDQ)CmWj72ct&^y!VV~s{QBLwm=H1>>jBu({?cseh2*8_Gn&$`P
z!73r+>d@Lo=A-69_kxN&`3Q~##6v~`A#um0rq+Ru_u#fWKJTL^$?w@*K;V_uM9|o3
zvKm^MW5P%-Pk=GVtf%GSB`fAWEsxVarftzx=Y#V|9(S7O5F68*cJ*o6&=@MII6`vq
z1dACV#(cDS?~^U8I*@S#&CRM~a%xtqRUtkT<r6T1(Cq7d$y3~&E+s{J0C5tKU0{Sf
z{Hq`ztaQ{{EX7o6SVa0mVTohZSg8>-OzAkDV1xtWHDgi7=w+%Oz^C7qF!&Y-JybRk
z<8eLuux_z93|rH%tavU9oMk+r!Z|}XS|>r-@`z4)il9Z9fn!gGf;gRcEKV$2y*)Kl
z>22nQ;W`2QF96q|8XEaAGYp8-hPGGRee#oJp{t9~3dI;1<hcoD7Ld%x0NUOmNUV;l
zKU!dT@DW^%U@mDu1o~AQ%V`cSBu^?7kTu?PqD=3J#hQwmO!`BFDZX4aY^{$SLwnb;
z;P_w~(bQ7c^02k995Q&Lz2dmbq(3f*h;lm63SQztn<iAL$$3v~4t_XcnAuV<a~)Kc
z7}bhP(Lx6kf=^@Eiz^Su!?eWPYo@je=VhJY&eF%Cwq{{Iv!8$&Cinqnk%nHE4O)AR
z<b$QUCF==d-Cn5xB?cHHv=mqc-@j6+FK~U3JC5eivAD{M?{x^|TQIkPOtR~2Mq%_U
z^x8!BT+%|}n+MW3gJxV`7_m*@q^Bb>Q(G;CKEFG!J8n8n<P1)xG__{O?E-8XPc$i5
zaW~7L$BdgyQ42GdQgFMnKFQWfVV2!i`9!s5yRAKNC3k#J4@vE;tY)9zSn<GHB|To2
zDcNI(VLE`b)tGv`%XV9B;%Ti3@YdKor*-*SBYN4)&zmmnwuZnChW=`awM^#F?s_oU
zZ8fm-lHri>1I#DfO^EYPdmU+zl&P(g=O~K@&JFMxgP3G(x=iL@V4hmx?g|fHC(z0W
z6`4Ze+mV?(c^=pF$9$zQb80aOKyTV$700rMcn`;X+-t3q>}wf^@{0MLj*ai`h~>}D
zV@yAuR>A5BYHF(oEk1J%w6I%BWZH$@R^5&OnOwLkuU-!}cW^?SE`;wrc2}s?dg#sa
z)Pa3e-KV4K6l!aucbCMq8=>%}ZB?KB2%Y=0U9s+Z({Nlr8pU$!zfY63pOnoDswcRo
zf%1L^SlexV^g8F@Oe1jt6#>bSf8w}o*+((o*3ce*8WIb=Jw+1#oAt^e;Z&ZkcO@pp
zTx}gfH{KmJvcFPx)X6{p-dS9(B$eh?_9ntdB9Fs1|M_mK9TN72(*f%C880e>vrAMb
zp8bu0&gte#{o>6`Q3$Bq=|s)jByU%*$X{+Ik#|MT>y;s{U-uUpt1rg!)VG?3*%9JP
zRy*YaR?#nV$*$#820|isNZ8lEQ_wZn46@YL?D9Rm$0hpR3dx=i-qE$RoA=zFt^1{2
zV_IpXY&n#;dZ3cH#$)Wuf;F*?*Bi#a$tUniza7hmUzF_oN)~tBB$FN40wG3k&fH#3
z3H;rgIJn8S^E_C+dAV4o8al3%Lezop`QTStny{l<D#f*nM1M#{mLuGE%EP0aP4baX
zTg^`8EBM@K)kmy?GZ4*z)5BHJ)rxggx0s(n`;hQ*l9i%26#}@Nf_tfp=_1J)g^9wW
zmJ%;y=kqdT1CzhVK>p>;X+zG6;^K383SPkMY4A;7?E$G1@LqO(#;!KlwE_O$9MG-G
zSRU9;?$h}16v8!9pJQ60CcZ(Li~G~4aomueEj5K(-b)jgb>9&Ebmh=4xjJ%%bNcIq
ziMa13F8XpJy-%GbUf!70lb^n7Bxzhd7GxGsPG{H|M)c;YT#<M=vXhEtf|v&#fz9Cp
z?wr+51Ra@R%m9B}`i%-VtmYD<K+SF7`PK6_gRKRgO|2v;lNn^5_mf0SrU^DlEe$RN
z=Xk-6AZK#T3VG*8Ydsbp0<lQZ5+RuxjB$R(a)7i^gu#lq{&9#b4MrPqMCaF%O_V26
z#M{E{Ah-ld7@6kDCTc$X3hcHHlEJ3pP9u8jWFjC#wZMdms^^W2Hh4P2LBRIx0I?yP
zLW=Y_%Sv*%7eXRCp*!OTgJ-fZ=#=&fzDex3vfeTU8{y(|4Oa7zai(T<OE2Wwo(4Vb
z+#q9{|5)S*Nkv5-%K%NdOsQ(9K57^Vrarl%AibK$XL6W2to7hbV6DPY+@{6pZOvjs
zS_!5nG+kE0#7-iw^aF8TutP)!l-fjPNqnEE6}W@y9t)V@mqlZk2-AV=Y?MkU-9W(g
z;~ju!#JZ;XUqkO+QSfDNx7Q#TzbwuaA|+^KL#9?nmf8Y{rHd?Dy1u_=!denMY)G?*
zMrxy(SCF$&#DhPe!<KU<?9Lo{H^;|ITRnkcfNB|a2qcHr3R}x{+Q+aZTP65fH5^h2
zx)N63L+59L)ew?v5r%UDQY|t)bCB4;QCvv~aV?HdAf4J)p7$oZ#3C7zN^L-BfwQNl
zuN%7n3mT3Iv%Pa}VGCdcyNisHsRENc?N=L;I85<PT>*OGaT#FgKr0D(r`+J{1bAc8
zFc{!NhED{Y(iVlh5fsG>6VJQw5F<7-YZY5!GBonGG@;6KfSxEo$X;&kX!=~F;KguX
z9<wwwGzVK3q(24-a6ELLEj1^Q+QcE-WjB}D>Yc^31+V2Cp8`!@8>*nTstrQ)cxHZ4
z15op_gok0G#<Q6OX0YYZWTF+o9{XWclKm9m)=cVsEKl_7nZ}lQ=gFQVgm(n;?MT(u
zF-*k0d8C$bd695j!0>YH{G8(@=~-Dm&1vGf^StzIVBTBX4sG~2j>I`6oazg>cY&ps
zF$&)tsWf&<RzKjATEnAAIyxzLHo7_r-(-`7wQI6-F1GeJ-B0h79TBs;Zoeb-`D?-|
z57VO_Hx-L%RByGIN&`C()~g@IqVcbn;)*YhHkz;Jz!6^$zeX+aW(SWQz)^Xl-I##q
zSWAe3+~P*?VimGNH=o;IO`mZ~qU)Yroi%IgXD%t;m-`2^$mH3XE&AZ-wZdjn#(eL=
z_!(QP80b!QbD?UXPCt><CR(WGaawSMAUkL8wq7CcPLjA;%GpDf-l7#MbR9g8UXG8N
z&r-mccE96AxMzM&v%Q`n^PlsJuX#;X^$En8ypGh^qm!Xur`~<+8udqLxLa3K;Pxrx
zJx^s)y%(QrnML={^(VI5+FUBd5JrUQm(ELM;FIEh<mu?TR)uO=`GaaQ`4lN7pG>4u
z+rh|28C%epWsjU^U%QjV?mFL+AG<h<9+LAp-`XRiZ~Yi7E(4Oa&jwne?aw^OCh2V@
zlKH{7b%ZAPyd+X@(CmiK6@Lt|swIF_o$Y^y&aM1UylQhJXuM%3*B(|m5GRs-;S$b;
zg4%d&l|$Eb7Of-H$fYy2^>#L{)2)s48k>C?I5Vy}Cs)Vn?_JzGTi7dsvANzTCDwt~
zzR&uLf?|~-z154q6HyTm=%{oJ%N>_H8G4#CM<&CkZ01mUeJk0&B)faI>kvnLwMOXD
zK(hYjE|DLd%RGo}xQW7;O?-;uAB&=6|NYk)5m<Dp92(~W*#1l*oy+FQbEp9~<FZRi
zzt4&Y&6G-nN_OCl^ctPOfxyX+K<kcc%EPv&!9h8__X+l7NJQ!{_R#{dXtpwm2QI<q
zovWj0!x__4f4WIBZzv{^nYE6q4ZBj*R<>v#lLL*3br}W7EhT^awp4z=Jyvk$b?g_S
zWZ?BuC(6>`SW3G3b-wQQ63<=}UjOJxQ_op;N1@S>Z=?2AmZrumlq|eR9|&mkH`Sir
z7?=M;8**7cbx+isl;Rm=<weT*sYwkUV$(H!L%<gKtsy)o@H^g)kRzSa49UJc#zOkr
z2<O-fs-ibc{|O#1(y1zC9)>Tfua%wsG=63nbG=IZG|qh^HpT)PX-UqrZGa9ChQl!{
zHpY`?zD#I@le<}O1$yM8eN1qH<md`Sw}V;YZgN>!%_7!4@qP;lQ2%OiB>HwFyBe$N
zu6hn{u|E46J<~~bK>m}=TzJzaKLTFDv40je-fxoW0B{yH7<c3f#95&)YYe%qC&h8*
zraYLiQXQ9uq+Tm9;jp|oezvr2PbR$)MHHlo6KKx}u^MSg091pfIm>3N(L3=lO{5d>
zhO&rSxp|TbeL@2-v(r~7kML7iSOnv!3eJW3KmLi$G#mWx<u}Q1IZ)9WDH-?9n4m7Q
zb}l|x$>s<a<rfC?z!0YgPR!dv_40&cnX)9O6AZsnk~oz*i~-zRTlZ$+AVo}t$&<-F
zPH)m}r4s~aJ<K!SgJr?2HN;XAvZdxa3Rpt~h8H-mnmzE9k7nLH`7Hz=91Tq8Vh*bK
ze7+cbG3unNd2Cq{ET_uyJksfx`gk0p3|i8(Sx2kHX8bq!Ed&~nV+k?-P18~9{Pq&6
zY!Hhlr*vH%L9d|hlngBxW~n6+MdZ!Oqb!th*v|3Rf~aGO8%FUoPXlMhmHfu|&4f!?
z;52p8%lbc|sf?=C@`zw-EF2UbOjsoE2s&xy4=wA0GL6Dn)Wxwpe9!~HZJ@q5aFNS}
zHW|DU*9vLo&%^{9K&@(8hmx=FG)x9`zs5w=mIq;emoVlB6&=@-&@kFf#kiKAJzHHr
z7Nlu#6~B5MtY$=XOt3M~Xj1hO$|Okt4r*69&tskNPC(@;GYPaZY8tLtCOnF{)h+C5
ztl*j9=cBjcLyq#?o3(643sP7J@gs6<g;)5r=0Q``&m;{KPp-&qp?7*fW1KXtwcFOa
zZ<5QFAQnco?pNs*JA*eAx*4zCri!+J_$kVTYr9Q!mS&H~Vsf!(DD71<Jd+*t(fGFf
z&9XGuH)|!P&xK}tAtDsie6;!c=FQ82W%MKd@=iXahEL+Gf)N*KbOuD;1Bn1R9VhJk
z_~5~J&|0AQ&`<+dZ`}7N*{^JG`OpeeH=jOd$A;^WRO>WTBAT4U2Kok`UoT2el#kr_
zECm*eT!d^ueB_n5+8E8s$4msBfcUBYh7^DJS&DWzYUibq%yM9u-PRm-MH)4%kK4r*
zxG_whw?@=gtZvutm3Z=Y8SwqMo@QH+feJBq0F%j2&+>bR%H)DO)B2`!DU~iyIKque
zAu|Ojy78>X*&F*nJhPp5o0tffp3(kn`ghF_5k7!08oz~BR|_6X8%l7jkv(|bDIdC&
zuDsTuD~NCLjkxTnXRNWi*$+64Z$!wuvYyPp3-0a<e5gfs=|`FMW9i}iC*4cIzuljQ
zu%8GW-1OAMRzA8lx6#!bS2`5xD9;=Crv)`yHxi86+AHsl8~XBz)fI2itk4JlB_7jN
zg<v<o(?g#NXDR(NThi>%_0*BPL^OMz04AZ5@EbaeZ{d@f4&F-db(9&TZRt*5;G{T6
z9N(lgH`Cw;pXXMQ*^)nfa_x}5M`C^HH`pooBzs*qSDh<t35}!jTUD=xu2OT$X76s`
z<zW9=7(gtZ_faK2G^q9&N4@vx%0`%@SH@^TU!)xN{G`#QeflT!>#6kpPToSvRPBQq
z)TtTk71nb6#x}yP?1_CT=H?yuf6)V{AJO`b+mPobl$RqF20TbxvQxv4(QhCVH+XZk
zGWK4)3%gNQe=MA|x<};8+cdL-sl~rsDF+6B<w1+LG{A`G%Zr<Mx7C?$r~OZvCIFC}
zvnP6VY_Ev!yRma6u}a`gZIx1%CdV%IqELX}@s`@kx<C5k%;6HM3#v%+?>zSz5zfEP
z4RE?Hxg;d3@&@kR8NY2it$>=}5z-9(mdem`Dbn~B#G=v&k<u^!xs!UeP>s&qJr-A{
zxH#umDenI;Od>aROCh?7xzgYJ%IGtj8I=d}j<<On34HKZm~|}&cD^Bzi(g`9(EU4M
zFe%fa&OG7s`dgR2A%_6<b5ETYe=pfYPw=Kfx2#^7PNTMZurw&t$JlyR9C7jmm66Br
zulBll-#<<;&skR;E}f$z*)gden<$NY-kGJ)mI3Uxin|ZQFRqjH@?BC5*=y&jS&&is
zkv)^&o>>m9NcF{DN3J|yr<{*4gW5VEm&Np~$V@l0^!?O|SoEEA5l?-}(3H8PqX*lZ
z^iqy#^uS%(-?W!Zk6UO5P<z#!FJMV+qZ9WP<xoVVHL}tCy6ljKWu;#dy`3i?Pm;M`
zs*7BQ@9f#2ewI4*RmQDbx@u(*QsG1faq^)ZkENmUM!LICf-@d#z?@(Xes__DDyyG9
zYW5&NauIPU5f(+;AlU|Lt9rv<i9illznYDaD8UydarGRI&nkQ8jHhh=#4<d?B80py
z>M8zoExlW>3>#`ED6!kBu^kfL6~&qSjUTnVwSiCCdXMAom_+GkI)QOF;b<1gVoVqL
zmIn!uV+-Ee^09|UffSD*azAs>cTM5SnxQ|<{ZDPW7KTk)l*yVD^T7j_ozJ7pC{Gvc
z1h(@>1C=^mo-hyqR1C_O&f}7Hd>l&xiY}~*eMB#(dbiK<Eq|80nci?1Co5GP6C@sd
zgQ;=LVR(d8yyvN0c4N$B!~DX#l}+-MCNk-*jyQhHf_+hr=7*%Ni(*jgbebIy648-G
zA*XS8B+{@jT1$W|4x(zg;MX$gn1HHf7%*XqT0k}5E5ca{UJhvx5aU=9EV7l93C!gs
z!ULj_gMw_wnk0^@g9TqXXui{R2kNJpQ<U+KZ^&nx)}G)bFC%*{4c>y|P!@RsbBx~E
z_K$&!8IsPF9?jO#qz%f3G?Zg%NX7;K+|VZpv6Hx<Or;xm+8cjx?byrJjQ7|jZnor=
z$5_Ht8P|{#l7p<i64m21Mn)U23_6uhE0cM}&r1$8YO4+hbj`D6lCvz3dDtaLcX-qq
z{G9W+@D=x%1$G85QcAo7?^=Fg&6mp5hNe}VQo_1}Z;{Q3li$&)`>ce8exkzjcZkfy
z+e+UirptoBzG3=+t~}_}CiVpv<zmeXKe0}b(OlB?gL0vzNs28X$GN?ZR(EBb`x?3}
zIXP`tu{-D*AeGjP;f^qF7)FaK;d$sOV}TVdqYoxN;K<7{MpjRC)xqFpYAbJ%m_4TK
z0F{WTJxKHI+I)wTi)q}N*Dl|x<QA|LSk`k0`N&hu%gegi0y)aafC?_`X2T<BB&O=a
zgZCEF>MXPY%5tG3Tc8)HM#OP+$T%I0%vj!xp%KNXg5neM=5Sd5Kwt~(%^dRpMm?7%
zaV?-$vz(eUUnA05S1C$t0iA(34RRTQZ6EXT5?EXm?+N69+PXY&UH;vMnG6%77GgDI
zw%Sr#ZFi5|)}EuQrsBdbmeU)tH?>vzneh{J2NRi|NvUzET=8fuQN5JK##$#RY%54P
zLR`^~D6LV4fJS8EKGwy1In#abi)vk*0_rA%%sXV)YA22VI?7vVtE4h}W|lUGmCQ#f
z`bSccpR~jb?oyC6Z?o}FbYL!260Cb%*02_O<0Mxnt`5SazD#&_Tgk?=s}c8iSkt;M
zUnSL$wVT>$Tvym-yRE)b%tngl`Bco2=L>UY>hfxd<>UQr<Rzcp-swtETl-A7x*tIp
z@bLD83+?}LJaiDXwK-)z9bkIqtXPdm<9f>JpD!FW{P{z|D3;tZOJ06>5yxhO+In_o
zpM;bLFCeA0Rg!&>G>5xcg=v(cNe&4I3QMQzYDx|qyRG7W%z{kew}K?DRX!B||FFS&
z)i43i5bzm>0y>@ak;DB`dixp<2R_fR^~F+j<QY~nT!Ue;3V!<Ml>9Pa{W#mo@GSBX
zW&>19@iO61TczhC>`?Ez(<ZdE#4d)#?vFe9V55}Qt{fN@c3b_V#WP8L;V}$k;=8YM
z!j();c7DQ-8@1*>By-P~B!Yj5Cw`rQ_Jba4XGqhJCu+N`LAcq&4*CGxID3APe)FyG
zQ*GV|d&{Z9{_*X6I)3ep9OJ;ce*W!&T=%V-vfJv7tljm?<yQZZ(bm+~=3Nq7BF%w{
z$m6$V!q-b<)K)%LyKj<pVTPm5pi%8ny562Q6$d}ufI361r8MZJ*`$#cO<NxLmqMbS
zpU5TYu4a?>OPhW6DJB+Sw{`Sf&c1#Q4XnXw-JiUvr*ooUL_hhHr0B5dy_63N0A{t*
z0vXP%a$O`9Q(KR|{AO|A`-DXGcit`+e`!UksI6g@Itb+0+IR}SSejr4{?KET=bvri
zrO9981@?OEt5>c`Dt3+4!Rkgi*1IjNU|2#+!#B1mYO7<Ir<x9qjd`m5i5Rn^GG6;^
z?7}M+%aO4BD3<tPdJ0opqpt*7UVf%W<g!wbRgv>2%@|>)sI4MDL;kbSmy#EmyV`5a
zj-)(5lVS#LXOnGSxD2?@a5gIa{V0}jPLweq<?v#%E<!mJy-iVD5x0Tv6qQ|{5?B94
z<&+LSR&Ses5)-~ENsqkRkUB$j{G!&VIL>Y1_A+j<G%a^`_tc0R$q!^QY8J5m4ed+^
zlSEiNiW*y0j`!+3b>}b6sM1JEe|4%iI;U#mP}<{mOuGa4_czaMnzq`MpLSDOdtrPz
z&{z-F6{xO(f!&Lvm=ty~i<?5!s*A%;>9YJZnG|IqG|8ueR-7Yk^w8v!P)##PYGP3W
z5GUhAt2%Re%wSQH?hFz9wdP_I2($&>o)+H;Imvl4FJ+0Zp2!wFEesuM&>lG$w{EQM
z>hL_`EkB;0hDWH2p-aV!`Ne#yR=N!s8)xIQGJ*rUt&-%L;5=(a&6+wSo3;_B<M=SX
zszXe}&5G>LBZ9FcFgbHZRIPXNCo-2uvIGbrh-XiXxfH0gMT9#zv8y>6Z3S)&@N0u@
z8JH#m)6pcJJ_I1>DwAThGzcLdwi9FN#+KEk!JAS6cz#ZdL=H;Mv{rV|Ng}skUY#g4
z8OS1+g|Wq(wr`Ph=$vE=kr5P|4=ysLB2%R4B0Q=wM29ToY;N=%qqImN(M_}u^R?v0
z%<%jSpK{z&3mqB+#<^gt38mCu!2wdsQpgo}%VI6mF4F)mL5%#lswHqT@a1G`mOI(|
zWVe?=W6S5P>cZfud54N~2s>^Xe?1`AkS>2R(b|A?bpq6=<ZU|75PqivYcPp&xB~=g
z>69b(Nl?O_B`%jAk61igRwIo^s5>sv;f4j>Apx{zAD~1eox#a8jJH5}+Rw%h9&Dgl
z#*jrn9grV2FUu4&jzHX*+aQW$#PHJhhuMp-dt5={lK3g~C&y3%&@lEzqCPf9C-9J<
zk<+fIBWP5oibQD}8E?jtka&os3^9cp49_|q1KVxg%t?M9T)AOqCC45oamqx^i%9~b
z^1a4|CmZ|O$qSf?Ww`?=*|oN~G2oE}qW~m*==0NNyMqimv*ZC-5U<%2(sz<DwqpsW
zL{wWG5xRVcg5aD<Nk^SkBfvUg8XSg_LJ%>ziDF7VGT#8)jVBfgj8Zj2c5kOqHna#a
z7`D<e@XkzY^UH$@$!-DF8G4H&vjWTyl?qbUU&N795B{e!idh$o6_P0BknolAYGg&*
zn2nt6wwlA6+M01lSoloCMAX=+iD_0fX8a<5w_4>eeLZSxBYqi~)Jym-2T)r@nLEl;
zLur_RSR_pvEMif97e#Tp-kK}&l<P{F)PITjncc+k&y$ioeSRd(3kf;8-HU&7G*GBH
z#kmadaX`w|*5k3PrtBK6+MFKQ$#um5{X&$;jj?o>SIgu2Ig$+%yqvzqAGHD3;JU6U
zyOPPyg&fpBC{a_A#unXtdmgIqB1f0RK6iC8Z=u6M>B}!wshudg5Iz2F<CDN<SNmA_
z()4uttnTCqTFvnFC|NeS2Kt{*WfC2#LPhf@4herG5<4VZwB1&{2E2Pd?4{a>eSH}5
z_rE+T+ygA0rJ;_XA4I;7zaf(P_0f#GAa5KM)YhqqbEC#jZj0plbcaMMklEm0%cK5i
zA>*}ER)S{Z37syv=GYLY5}qlj{OuWTWN_cIs<6@!r>r(|s}u}pFL=qyiK(sD1<AfW
z%)hPJ-5G=ay6%t2X!Gvvak}$d<!&vJNsEU-T;(xQ6Z?+zDwg`+i*Gzw)$CxZ_uGtM
z=Y=xp@SJ^YRbP4VL+M@EJAwLe-R^56zv<ESyeNL0>ed2hPg0Ys-Y4Vrb2pi@Bkc3f
zoiWh$jkTlp0i3aL?G`+<+gkQ_USQpc<(@*6u91QJUzcQ!zlxNT$h4LLmH3`UJ`Il8
zZI!|O)B#H{F{1<cks^cHrBhP*8j40a+zjI{@XC8RD8Aem7VSAEk$xWO-@^fKw*$TS
zf>m^ox01+D3w?5kX&S{W&4;PKy_Z_CECcR&I9I=>yJ6Vk@SAvo4BKXB!w;p7GrD?k
zb`^)9H`xM9RVq7XGu~}=mNy0t)R1Fq6KsH~t-RZ+@_}Af6MdoL-Dn!U^S?^ULW(x8
z?;3mRp|6e_W=D7w1{!WJiP&AxCdvTuf{3-<C6yPGF#0a=KBZNq0jY<F>EhN!wdiGE
z11&~v6}c>rP`1}5<SBN-P*Nx3n>iXYYpIn6wWOQrF@flT?gVC}ZjMm3f@LY=KG14(
z5_-`Pv`i}itnX<+ylw+ancw%6g5y;P{TSD8l?%KZayC9+1?86aS`7yNimp$d%k3Ra
z?agCl<6CoFoIQ85ddX&IfV5H&hMh9&hnx$LPZXx&ZSZzHbj}oD?H3q)zN#9KQClyO
zbJ!#-Z<cYk=<rTFH#ll86goC}p+_d+uM>C)3|xT}xeJ=ZiWY%%TX{4WGm-uYCNn-L
z0_JmiaGHmu2&}a>%@Ya~?PB1aGU1R%L>mnOj08=N@&qlzw^OH*GG%VN785v?D-`CG
zg_s~LS)dPlrdR?UEY9Ju#jCM^kHfUb%nxH4G;B@{cmFzY^thqHB1#~OCg>E#f}J@d
zDed=k72ZM<8*sLfZ{<)=+HBzvd4B376aPPP?*k>*QQ!Ig?(N&HJEM_wM;h5<W1E`M
z*lvVl+W!&*4%CdsW-JtF8<{v>*ll@@ae$X62sjYPQZpKx!7<6$YqBOJo0c$SPzVt`
zmIoxeX*nWKOZ>8em^|kk*d6>Fp5x=g(IG$_Lg0PAb-PDnTbiET^UmAfOxLYHzpDEE
ze)acPRk!Xw=1&2!wHcr+M&c11wX#ef-?brD1@l5m%}dCqBC3`zDFoQ+<6}+3BfE5h
zrS%f4Vjpv*Ez_Du7edccuoD^(uRv2-QKHSKu5=nxP7W`lACv{;o`V*gl9w;r1>P&v
znJq*Pc|jp_WIOiBO;j!4-ED0kdPLw)iNMx`t4rzia8gt<>SC*d2gx{3L8Xx|VceMd
zto74&os(mZUtJb~j*B)=SaVU1>_UcAB8QACnMkE9Y;NVcuRWlx;&nhcO8#g8)GV-L
z8Y{6RDjzUL%tg}r^7;_StRWbYx_ha32(qF~Av%<<lV}qx-Ao?DC*XvH=p(CErjXj0
z(AI<rL)Xu}65!q<P@Pg2xIHptQ^W7BBxy8hG|hsh=6lSeNkB>!x-%RNwbS(sI9?x-
zPf)+|ENHmkoEE$0q~JU@Wm~6{@Vbe~sqhm#rGPSzqwr(5XdDqD-a~{&Pz_L@=tasL
zUd*9W5r+?cf)LHM4Jac!;+AQp&%!1#Uih%!YZTR>PaN((FhkD=TZoJ<2pF-{^YD;f
zQ{r$3AJCkI;2nggiDQ+AOh6@KLf5Tq;f#L6$9jgfACPS~^^)tXjNlW}5r-0L5QYNU
zawd)&=goCIxz<>ZXyC`^7zu^~%1AN#!I3J6q*?({h2+Z-EN0@A&VUyuBsvlT*#hTq
zHd#KNLwuIHxCm2HrrACyT7J{I)o|)-q$%PT>HoqI5la*@><duV78&P2({b|lTGQ)+
z#)_-?bu@w9EC%{PfI}hf2T^vutwrKW!7G5_#loq8Wjt&Hd?*u8&6Z_ZmF-}RB+oTL
zS&2H8MK{}s-_Z%!m2Bk&HQt%CbR&G;jOaVe8SE_M_FnaFC_NNSW*t!aLj%U>CQP5G
z!Hx)hWJ4^I3GE+u+#jESDTl9B`Q1zh(MfTtX*S6%@F&VjlmtuJDSI`4K`N9HP)Id;
z^fRDl6>5(3eZMGchKua~2_TvL{}29jS(XJMF$NV13m+67O=T1xAAN|WN)RX}%bi&Z
z$N$IR|GUytm#{WaFP;ZZK9einIMXy)aX#A;p5=6<tADm7p86SIS}~n$GBoK3JOOMH
zrm*;b4k&<e450r^Te9?rQ0BvpDX|9*G+hCtB(BWQ74)JaEqGt%ZV4{Id6@``fLA60
zT5_c%N_8ly&LGvvk?_z6v5()npd~KJAuhglVw42ai#+93$faLD@SA*zC^nq1Nwo(-
zmN>)f`K&z2gh>R>+;_8;qs!SkG8VT&6S0mT4kAl7>f%V5S3We6DJN+P4no%%zm{^T
z;$kFY?ul^`KY8|r4j3cj5Uh??1e-Ej(36`E3tuiZ#e<<!_!Wi^SwlrP0}fx7=%Of=
zJ&^#?Vqepjbqs8#n?a<P)gz(^?aa`LL0+cX1l;%_M>J%C;1)6>a9Vly1!tV9(=q_y
zpsyhdE>gDL-iu_2h8;oNvkP4ZSq1z?S298N<i1WQY|J{RaFqvn`BJi^Iuh7Nksn-m
z+GEJaTi9dU8ilbA6jtzvg!W9i*MzpYDREXpnJH}R*2xI@*WyDci>7PF%F#7;KT!le
zhR4?<sSvOpN3oJ?*Gjo_b(n}HG<ekctq7>=e})GaI<YjcIE4(=Uy<i(VeTeY;e8TV
ztvo{ltGyK!E~o>5$j1S#&fP%@GwjI(c?5nWtTlp8IvN?|n)4PuRLtjs?}k6u|8#Cg
zWm+KMx-zhc$MmCJ*$M)cG_Jps>UejM<F$TVV0a&K%-Y>&pNA;xQkP{cn+XE<O}l8r
z=;hk8`GQGm^o=2*#B24?M#rK@V!sie4`FsF5@?p@#?A5NIgS{(wm~itoQ~LX%Uf5U
z>iV+K=Il@AY~;vjC>%NTgTR|!&H|Il1^T}ZYrP_=y_x&jM$Ow(2Ox3-Q@TIKw<(9#
zPy`)qN<HwZQV^Ye#A<E1OZ!La9Q(tv`r(rhSls257T|4ZgU#Co$n1wBIZkh#Bly4X
zfKQHmh5GZhh!)PWpQjkVU`$L!>nmx0KN_BkVSNl;qf(YgxB}Epg>-CjcC&Shcs!R*
z0$jsj_L&WZYi~{qUzkf~dP@{1w+4H(6jE+Ss($SF4jWBxLV{nYEF7|X!zg#O`k08T
zvjW#VCySj*^jX8mkI|O)*JxSIwxzA|Vy%cT9xw6v*sTX?%~w=xc8yeeL2mf(3-20X
zJPX&Q_Q2B<YC4<%t0c+gx|C*_g6yEd%>VJMxyQ(1YzvE}!nqD*uJL8=*HN~|+39KV
zA|0<CamGu*{ooxnO7xkWcbG{1p@^ONFKuJ@_>~+y`{!gPymTbBccQBv8KGMJ%@Cg}
zzq68fVa~l^&WbO&B3zs0?Ym!TN8FD#1O@bi?CNh0OD8n{$VC{-yA&b2jYW^TY?VB3
zi#N|{%l4H|Tx+hnId8wzA8h#x(HT>M*!9Q*?;L$D!|vLfGWV@n+xOt@`JDgYpbe&1
zQT)#&omk0gheNydSjB<bA8vho_RtP4RSA23jZLl3?25T5T9EP3;b877V`k?=cl43(
znc@D$k4##4>=$TyFG=_;s+j|scj6K|zveT&8^|@Me1YYBCIwF?)dyP}oK3$AoR76x
zlR3fA9w--4?tYZa>d;&;74+KRlKWWASa>g~|AdNgBQ1gi+Lm<e)mNKSwtJ6PhVv=5
zRT^J{*_+VU=Rf7M@!=0~lJ%{8O!h5-JtRhrKjVmE<4|u3w05>u96~CMYTmwXtB)T8
z(Z=KD2bd*&TLDana68l2V~Rx!#~wX9{muC&2MhORS}bgF<uLnWZ_dj3;@0n5_-#(^
zxqGP<jgN2ic3`88-h2b)viAix^Ef--fAfEh`93to;Iw!YE_vC@YbU7{*sfX)ZB}>F
zH}PStC*7*ENUJfPZBL7{4*0W{zp`lATg_Jpq`IEq40Ag2<mf_Md-5D5Y*%mF;Lf$T
zz*uwRc+%DpsZo~>x+T`Tj#ejCj!k=i&5hEpX}a1M=+$QD{I6B5_G55I;|T4|7xPKo
zBQ&zjmY~M}6t5{>n$+#^wFM`$xH0vO<h7idZ{Gq9^cB@*Y88X7@0%qEbvB<;d+cJ0
zPUZ9NI0&Zoi!6!9G#Ne|-kifeyLq<_&Cb%Y3zt{z(TA@HzGRYc`*LoQRIv7BYUk4=
z?850ca3Rdmb2`87kRVgNk59FSPy9P*-kGWW_k~OB6SJPXW5C|RsO+B|L6trvK@_YD
z!c;lma^8X8?8XV2MwH;X&$6Cci(1_C=~~N~a-8!CnKE4$AE#1ragnWzD#C|MZ+4AH
z<<Z=lN~{F4e3R{ueI@c`-PKyN&?tNcu=PWTs7@w~L|&BoG(VCVdRPv`=N3chQ?skg
zjZLf;sOFW&g+>L)CwO`soaC@18MI5r@pX78xrR1f0*4;f13qye`U@e7XZ86}QZm5T
ztw+B1gD7N1<I{qV^br)pdxgzxLtbd%>W!w7IMGNufvrbp4W-u)90(!tLW{(zN)c}g
zw@)O85t@^4VPU!!;^PFS)evHXtc3#T#?n|ej`-^U3Jk2=3pHkQS3ECj(-j{pj}i+}
zu*1o+V-GmXI%IO8@Sg?ZF{yZ8*E87Ytk2MToNyS0+2pL|Ez1^D$|A_KFQnYe#YrMR
zAKCT(IT42PI6Z`RRq8%Kug0skp}T1-t?+JFMp0C~RScv)7AXeq1g_~cg*qPE6oGK$
z<%*=$MgnBauMaqq9`;ByNwt7Y**O{IZ`ZA4kY0;BZQvtlqRLfwD}Q#j>6WjjS~1U0
zRRS^lc=9u%u4%L>Ra*aD5lPv>{)jVcM=Kr(Ey8uA+qT!kS)*m2f@>etYX?>2CF{1w
zdKcL|Q%Xgfma*7fp<8N@giu6cUr3b}6NJn&hq;9={xU@gG9m<XJa@_`<`O;6V1UDa
z<slB3`I{_8gwF`hQ-H3tM{^vrk?e)P=mc$$O{BQYzUc4@)##6bF0eL)%t;BFW(_9r
zR5hscLwLnxCJR8?tw6|D5-W=N(sP0b_bXy{I6yjGLxy8G96!&mF9Z(5`W{w0!RAB2
zOsdLuiayoxj3RiL(3EV)<q`Y-uHL5ZsS{~X2<!Rm=(8x6Nnv7M&%qbV3dsWEXJM(V
ztvuES5uiSgs8bOWk938r&Y$MRC`a-#lulvx1>gLD1Iecw@8t&9WoCeq+|rg5#kX6}
znpLZYUrqNLbH3V>o5_nRkaujB>i7X}MA2BIak;LoATBU;(Y>Zo*fMHsXv6yVE>2ws
zyRuE0YxtwY{9$d0YzTcSEo}dQB_~n$!*y9mTNT*a&JmTzQ}&&76VDJb9M5@?p+7j@
zrF5>td@Q-W#6G4?#?5gZCh)F`N&yo5&ye>YO&8Wii}dw5OS@II9hNT2PQ8iv3}0<{
za%Ss|_70m$zgvXO#ffol?dvYpaluP6bis6)QD1X;lI=1!R5cn|XNT}hYGgk0lUdX;
zdMcDobq9UHUx9pYK2fp7>D0KSbXGBZs8}EcWQsJGYSg%^X}fxVZQrGNK0~qECqQ#g
zF;<Q3j2j;2A7E(Vg{Vd#v=3xfs;%@0T+pv}3pj7%9O5iSt~v5gOd(&&q-p-AtZ2P+
zN8R5r<Za=-@OI?YsIBLOtXM9rQ*5GCFACNkPO?%4Yv-H0ESYor?qzO7<MJRgAQq^t
z=HN5zJKx2w_TJCEwMZ^}0V)2~U=s4L(rW(9tc83+@igyC@g`!N?eG85SY`(|bD8v8
zs=0sn9M`I_ta;<%`@<YbPi}cR(%G^ey1?ebQ)j5HZqKic4Np>nJqWTqbeQ}tX(#7X
z7VClV(IoTr4oW0ytKGSEibyW1t>=7#le)O357QiL@8i2K-+`}WOPZls1^+rvr_7;`
zxi%Zj>KJZ6!RQm!Rvc>sv-p7>wD?C^Uf;nI-l4XpK(3{}ZP)o(cJm%8>_NoHJ8^~H
zJPV84bN^5~il1+fZt;%uhyLidU+qh^HB5rsAM(*3r&$1R<lZl)=CJUaxqOEUtTKc!
zw1I_)SHNuT1-wf74DI3<H<?3i4edAk$QxVZe3(r4zLKABQpVxRYeW92w<EJh5-58i
z?~2}eEr&VNMID~pi-d}Gk=Fc1@L`_IoVga}$lEzaM{1{_JxKmVmYnnC=+-^ql>eD*
zAsyM~?uE>)_SURZ{X(oI9<_BYc}ktTMvlX@S^D3)dwG)Bqx$yD7Av-m7E>IWDmeaF
z4yrz`%y%mGz|fg8>-p<8j+xYrG(T*^wWrcreN+<}reB^1J)hYzY6v}a)&JDkc6Haf
zkISDtTnZ>VHV58ElhpqA!BDEL!_N{zFQ4Z=L*4#3l%AbSU9@m1)^J@N@-;TG>24i4
z)cM1(otAeEZF%o3JyF#b=QMJ{o4}`Ewxo{bdV6X0NcPo9+t;3{?50~ko<3Qb)ez<F
zOByfKvX)#6a~;6T!!|LnSktV*?(X%#WyA&#3ZXbECpD`d6i73lfLxtj5l|ya%d=~X
z{4}6z+5iHY6{bhZWM*?QCxWtOFEYOC0T&lQ%EF5Hs-!V#Pr?H*;P4I#+I*A@Wf1`)
z!^>(N=!XXjEsS+QXReFnyrMyQU_3{V5psI12%bzm8Vca(uSVg^_p+2{5Z}NQzj-RV
ziwR6r!N#GGvbkxcGRWB<I%RfBxXbsm<8(<}&&XP~GnmrBpa=na1c}2ap-fK`6F-TM
zsvspv=JZHT+@?{<5!b`pxsgcWYeVS0@)d;FqgQr`DZ`@~>x;E4bNKjJjvZ`*D;vfO
z<B5$U-Gyu{O3}xV{zl1MEGtp~wic=KM379&Nw8UVQCWIc8dEFmnB~D^zp)WLN+Xm+
z`}op>%|djMh2SPcE4xc1H7}cL=(@pY1-Oe6Y*toN-z|(X3DP3hgf_S?fSX87xsxP9
zh^+ykoZ(vP@rs;lKQICalx`N#<K_)^q9@ZI9h>V99^wkhty7}<gCs?Y9Fp#or3pES
zJY1Ay;<WIT_<f?P;(6T=sm&5>X-M>FgUQOsIv|ijM0Dn2`GvHQPBRx}#q{ZNWowu7
z3w#(*V!mS%W1OEH=F8tg78^vY31qIoH1&1~p=p4-hq3UP2V2xRV)^z5IN>eoGKZ|v
zHr!%+1$@_*9AEJ|lf|Wkgh+2phGf%07#lF>F0tTZJlsOt!LNZl!{8_rLxpT>i5+FX
zQkcw?*8vTcSr8&~T>v9tx@L^4g_DP@O4HGr$lEQTfd~QRfgC6B@ti-I2cx7tV&YmC
zbi3IuZqPF&NewdI>1naZqRl$2SzGp%441N6kS`TFQU^h~m&Zdy@X$F8R|C_ObwpDL
z(8wc?rQ?idkWAH#TKqc1NLh<iu3dOHUK-ll3_r@hFZc~XI4(tPeUY_^3bZ#TMci%0
zo}sp8sI76@#Ahb(Lcj4Hp2?4@)mC`hC`19R*ShjuFFDqNU};oav!{|^#o4a>fHpDM
zZ5^?HiTs*yl-<6V*<0{EUZFC*b=ae}PNq*EpzOEPE40ZIwN<Q#^c$0NYh~CAb9@6l
zl!f*NW?h{FcETqQ&QfV2EN{tm+bIHkC5EhFCuR4p;gI|#o(i!?Y+h<>L`y%H`!cn6
zEE=z`giEb6K4Y81yf9~zE0S9im|GtlsoYgwZg4yJU*M*j9;jAuSBTWsBzsv|KE1Hh
zKM`Q|Gkao1^kD&F&vL#6>Yn4MtZ}y$2Wo4O+RA1fjZwR;3kW-~+q&KT2(GS0DlpG(
zYsH!mzrow8N{07oKxZ9LTSM^=SrP7fmD%S8W2@9|YrHqJap)+T6dN=1@8dIwpV`h%
z+{Q4(rx|Aap}{QujW-7N2nRFN*4dcb#6NEc{rP1w<`xoNEfj3%o4L&_D^6~xt!*bV
z|M8WD6d3C~L9x2&*-qojmlnl?cX)fl?dG&;rR}?-joO-u$s@Onm7C3@cf$VX&dvSc
zs4X<+Qg;ubhNhC=zEpWIRsngO5h%IOKLNYn;-*9HC`p%(Z0U`FMNq8it2m600+sKp
z#Zz2oOeqGihd2L`vGI7_32Lj^57?fDqcQEao^z2`an-LC_qF#`t?@LanY_db?Y6c)
zW-Rr6xr&GojhJk8)z-VPuMLA)`?7%@&hk4l>je7M&BZXY1P0GBRx&ry0khls7vFm=
zA1~(nh)2H0Y5DW6vTXjEWZoT`4feWC&FuPjBK{vDUG27hbq?D5L7RE}=s%3n+NjLG
z^WMT7mV(Mf{f#rm$M#o?k*K!LU2W}iziSioFWO>@sI3n)ewZx5FPy%ou-k4&U!bh~
z6(6r;iyyuYUH7WYTHmS8U3TDw%$na(ag)k}m6@#g_f%9IYeJhrwD|oU)14=`jI;2N
zSgZN#y$CK^+B-?*c58`N-wRsfS!B8?itA2VsI6IJ$r<g>r|h=cQ{DMbc9Qt0t*kT8
z@!H&^W4F~=h27TBQaN-XSy5YiK4*LuzM?ZEBh9aSySqJ@OvKG7_@|{ObAxomtnS&5
z`T3ukI4hh*GdnABS>O}5;n&ckxnp?DpNEvc$+8B!t)o719kBbtzVJ%e19IN{i<ZJ>
z)B10zz<`@KVr=2ahyS_M+?}?ZKQPHLDynYU+z~MzEj}Dt^IulY0NO8OY5sG$4KDmI
zes=06wsMyb6x;V#qu{(QcD=)O-@+>+oY`a_n7ZNz0>ZTyRi;miIjh34iPMHX+tcYT
z0eLxoEq<{-RSoO1Dlb_*!j310%5Ddr!W}d3SL10?0r+UHVdSl6p~N1mLiH|l3NZnQ
zS|Ev_WJKUlf}~~3@1T??usD1jq|Ic{o&@222Jp`K2Lkn!jtAS2ElLMI!Vf5pLIV>w
zs?Y1;V{469&@*fERpoHK7rJK-qGtq;>ExFpFP2Xdrt{~~dAjbEIRqaf_*S0lfR5%u
zb6r+KS^J(9ja(e$t!hcn3SQ+vKyo$Ad5I1P>Rkjbnldu!VK&4JuO(-i^p2=W$f<aW
zFk}>Qp&_B0RM-DBk6F9cnWi9UQE7;K<<y7(=2WbYi&o6x=52JmA}JDmki4?svHCEZ
zG|3qhhZ9(lb?H2vNft>`@~J^1QaS2(%r$$+RM^mx<5pPli3iDwa2(8(@{IyVQ7<@L
z<*8Z%H|{ZK0!;(HT?@xF&*Du4=eL;)c%=OL0F)sIM|Dblz^=q+`K^NKkgza^M|eCH
zUHw4K61*}M#y8<R*oj<3BMsz-C>t0`5l5E#DyZWny6wkTLQW;C5?elJ1g}IAPS#lX
zbCQsNRaHnh>PrE8WR3eI(n)v>LqkkJ@C-XdTw%LAsc>)*$3&FAQNJE&O!u(L6o}7h
z1f@c&$MCY@OchM&kG;qnui?i7iulNvB34Tvm^o$!c|No0nS^R8M%*mMS^PkmP`Xa`
zzEDjV{uJNSOZA#oFIKy>Gy=7W{Dig^cm#zKJj0uau_vZN*dcyZbFP^L!b%7?@|@#+
zDwy!?R@XOi=-M+6;|lzk@`zP{-g0dyml|}WtYB>P@meQO6y(bzl--<$IY>#TFpzVn
z9aEp6Ur~ON7tr$LrR;j@ZuC8ak(K_H@=<$0PaoGoc6iwrY5dWGJ=v`^|4QDec4cUI
zithOZNNy860AURd#Mst(?Q~osvQS%-A%q8-Rz-8q2VO;gABdDWUf+soTo)82R#Ojs
zF|Jmbm+p5XM=tPNtNl{Utz~|Lf6)F_Ew%H`vT*d@l~QWgEa_;eRDjwV?2m1XX_K>M
zPSm2dHuFxJOxVI`%ryut^|Tx2Uj1PKQ7zN{>?sH&QAe{^=dIn=oU{8BB6(-GQ!C%1
zqe66uC(5gof?acNp1Hp^hp%PFr;x+1Lc%ix^YT~|0+V{%%Wa#&n!Krco1Q1gx4YX4
z$G6Pdf%hX(|0^sav`LrHDSOvs;C2Jp?n1#K;d=N6)#CxaG_dfRv|wW(uRi`S=ul3K
zU!MMDP0fQ2{m`rpygt6c--~+sXOQ<^;&dbwZdugA1J;D2d9iLwqs&|XAvOE^KNW6&
zNM1gK3h{6AaBygs+0zd-A;0dAV}A?PQH>((t=jAZf6N-&6T`vYbg9dvw%YBq=2jct
z$eGaw+23&SboTHYy6vb>&UxHz{fCSjs_wGvyhdI4^y+L_{;Fk-<-psKoPVCbrmIo@
z-KAyUbM%5V$q&77){{*LpWMXj!!I*y{dh9;$*>G|PYpjHf^DEhzazhfwNYD90L;g)
z!XJOXWgQewJJ_DI@X0M(??r7ra>w^xo!y31m8~u6!vtr&JlOs}-(mKPgU((3z05WL
zu9A*!F3f-J+vUoppSUb{w;r3MmiC8HU8R%l<BOO>k5&u6j4p41ANm(&{)1PBw)^w#
zRvrFboMNC4=)$3WkKGQ%Dc^ee!M0c@-Qfe461kkHFT+KRWr4=i33uG0=m^I>Om!-L
zoEJeEjO^er*#b(sc3ZuC)`X1PtC7eZ@6TF)@z8-Ht(`aDB!c^9HE6%qjXve<*mu}}
z)^6*OuW8x5Hr&Zxo_O~|>Kc?S-Fy=yE0Yv?-2bIr>*1BVGM{2sT(O?`(^N~rrrE&d
z6@MeE4B`HXv*GO(`2JVU+1>CU${dG;J!)&a(N1#v(4ZTp{<f#-o3ou46r(ph&3xj@
zYGFDg+*%$BRnA!#qyJ=E*=;Sd51h{lvG3N_Q3zzY?d!v)Q}(smPP6eZR=4BV<q#@Q
z{(LbMZbQyr*xH@`#Naa+(nVPnyL<Vb!L4^QViZe>kEnX{fa;<~$omxhnj4^Q=hTG#
zO|lT_bS-8M;ZG+c1~(f`7nNz7RqqkUtkU}oCL<_nD_t$>x;@V6`7BnZrhUJ9UrGwJ
z!(iDD%iY$3H#2g3lnK9o4fE2QCuuZ5`?r0hgX1`$@1(En2m8g-JGxlUT<ByA>StPf
zxt2r16WP5L8WwtHv44Xbq!(<MANG@|tshK(ZEMSxwq@{a6ZTu#1WTTL2;|Vj{^Y9z
zlecq7I1N`O<1B3y7l+|&KfA4qNoO+)QXFsZ3;P)!V8LuTaU<=Q%s2fT%PNak;0H8Z
zNP>htuNJ&E1SVZ7xf=5jgcZe<;U?;HAT!6GrhK$&g$Xx!YHb?}&~myKq+`NrVOtAA
zY$qi~lceU#_rs!xmm)D}txQ8LKm`DUDmv(Kjpqo?A_00SP@tIw{pl%9G5Vg)5T{i9
zmdsO<nPyu<?w||Yqe`Ag1a1c}NF7lAn@D_yFBY+UvOrD|h68t2<_AlM)1!kpVxkb|
zwl;aIUA|!}34BhrH36;^PW;qs;B)Fly3nQ6%PVQa!$Af2g9h=HM0yER-MZLlQu$XB
zRrHLE=<+8#nmEapVbQ!cX`PZ!9omxNZg9VByQD2DdKP-A(l>{0OuWKy+9Gqr6z>K}
z=CCeh!AHM4dPU=?1~)L~#lq-DKGOr4bwLu0)-;)#>H2+yJedsUL9-RT97xHbz;s}K
zp%&ui!?1^}2|_G^DpFgB_P~`3ZLxomjYsOJDuLR~7@Ydv#8a4S0OZhrIX`O!T|!5R
zmyp>u?_|Ztr*=<}eQk(R+*NW|vT5Z)hIt~AJS>rz{6?^-5P}5V1y??|nPfXiwqTbp
zP4_TP{{(HTP1>U*NV2DD2ALDV^DEUYEK;^qvx2Z#5R;Zo1HJ1Q8HqNW5kmP`+YEGM
zF*`?B>MPbtOV%woa^{@@lBYZX9rtd4Ww~o%3Jt}0p2%L#Q=se@<b*^$5(Xm6FR7vB
zGdNf~X&25bU@a&}9s<NrU3i0Okh2TEOj)kb{mH%tC^<+eJ3N;~7v?2#P0n0ULbP7j
z(Q*aIFcIY&5hEF;O-mCH*1-TpmAwz#)eWbx!Yb5QZ|q_DG-HxwSP<4Pmpm8cx&wNO
zDq0WfS<klCljKL~OJgZbh#wb9bed(IRVxhumMUF7mj!#DVISf)O_s?&S<*@Xamt)3
zvC_wsj2<slrRJY*V~ACIPs(GsV%=-YvNot$_?U1@<Wbe*MiS|mPPES1yC=h7qq3O#
z|CU94Ryb#b8RGlj^IixV4PwH1I%Dli1G|jbgSwr)+T3Ipg~Mbg&5GUDh^{E$u-8*3
zB>5G4V5Gjqjj$x@@Ld~bk|J3iVrs=El<n2DEka1c>yQg2&ZHx$XBS7-d<<*v=K1Di
z-aeIDyTt~9eMchhLiXUrJ?ojDfuMor3wi8fGr|6?<u@kk2}<~{T;rS5m7Cu<YmV~I
zkA8>)(0^p@slDlN@fGTIvt|=vX~HT`fHn5h$)qjc6=D~Qn!9ZIZ*vLKM(qNB05$vU
z32T2gd&2e(hq4~@GCIwZZoQR`3>B>ouX@Jt1!>7aFEE(Bhz%`WaXIr~#oWeo@$Cod
zbN-&gCvag8hu84R9F{p}lgBGeWVlVS_`2ocO9=i?uA~GHqgjo;*5VSEP@Mzay>x(8
ziT4k*TlZ|_lPc#=T~Fb!4LMaFwY69b#s!u)<$0HJf0UW%>pxrA;sODFOQL{zr^GJX
z#A)5PbEN3=7i9L?a~N-qfuaz_jUO_UqYqsE*~gN($^qs`^(iV)x4|ie_IGwsaHDB9
zx|d2iw45Z5x05vevn_lH=siW4b{A#C>17i$#nZvU$-QV?@5}wzNsd#A+x*rfIr?xq
zZihZ>_N(*3z8o09reA8wowroy61DcVAY}RVw+*m6vu|@Tg>Y>5;fo8XiuJaQ+ezzk
zoC$4z^^Zh%AIPoU{>WHbQ&N-s)W>Twh?uH&^p`km@)X~R&}EE+=cRgGw-pvQXqy5!
zbV19<H$wkC=T?TUs`@(u2e6aP>(DgFuED#l8cI5zq(Y>h8T6kIC;p4Sr{$0=`0s2<
z?a+35HRxKr?dKAke>c3nv1*e?nRLfXN|&Kbac}Gd%svnZ*U{~VCGruMrY=VCiBc#Q
z%33l6Z(MHMSj=y1`{_<+Lvqh~ttq>WW_;!A_AunrY><?*d(OAw{>RxZzG*|QgW%qM
zlOr7efz86-@s>^dU16Ht*8H)rRd{`~4+IWhTz$-LL~Zruq4KO6pS^gyrFGdGQ1<6i
zRii#YAC#Z9(Om+X6DmePP>w^wRNz|57mWN?Te>da-n^KwYd~qfSf!ypTdpe@;-^LS
zK7J10lyy*^YlFHzeFz<(a96>#X-J>khUX%J`XT9_D7kRy-T_x#9-3nynB1K%r&DLy
zM<L;488_HxV`8gPI*ql-c;XIEzRA9~X?UmIrb+!NaP!4P&oySA10nX=gm--|bmKN{
zJCk#Y8*OPLQ`HN)r`LFixg9QN9x<{b#E84z<=n{4Df&>0S$SKptMRQ_w9%}mtM$@<
z-jhR?A-MtX<+zZKe)oYmO<6&tL#4%p`#jxc1<~{YAH(N+vMrs~kuNfxM{p4mQo@b?
zhLMKSk5bGn@P}6e)knTm{JL|ptqC5v0d;;smK6v&YdJ=4PU*!7N-s=ZMA3!{k54`?
z%JAtyXS`=y^BK6P7-q#s;mKiD_CYz4F~0>cvPZGB>7mevi)_k*bD7Q0Icwt|!Bc&M
z=IK*$mjPmuNvIkhghD07M%@C|FpG{<#yF!%GCfi}9EJ(rPCmLC+v6A~QC34(<$(Hi
zKo%q;8F8K+8=fT|zj8Ll)6j23s=zs!K?Y4pWcV5E<b^$B_0Zw!2f=|c#_ze)y1kbv
zC3ETgkj>Yzm4J?(kFvv()j~e1(~n1zw#&2yByiDOhY=A6EN#IPRWQcv@Bow=KneKW
zPPW8N(`+g&gSQ7V^S3#;{unN;>UqYU;CT-R*`(8o6#e3tzmsC}L0-FV&46bWrfGfq
z%|PrFE(&v!CzmT~JFJA>Q^L*&JlFabYak{HGyLVW3}2?;#F|Ze3}8WqJk+9<r3j6Z
z$9oPd(onEA*vva@Eq-f5fQh)RTB6Y;v?mt9VMcX}-CnQNAJ{zwBho8bp2H`Arv{wY
z$X0F<u{JP~p!CM0M$8dV67Z*u;P9RD^N4vyiMG_MRQ%#hVO8hxP_}8^XuJrT)B>fi
zb%J0!2^GP7Ldy@Nm(dhL5-(Jg{~GWhf<rlotw?Be<>pKLfDOq4nH>o#gb8x%15V+Z
zZmRlqfkZM`;xOTb6Q!3AJZD?v1*VU=D5p6!HG;gyQHw=h63{Q-pxsHujNr;h(N2fQ
zj3h8(ky!+)Ti3?JNy4e?#U+slzGvyW*M3AoVWk6FV-;$ts#Lo^3T@ucOAM_Vlvc<R
zGIJ-^L~o7{)8Tsf3bjMRHWZ!MjG!eO78=Sd7pYT~RwOI5(*id%$27WuZL|H|B2LYB
zbiUwrW=l({J;Y5*{nK-SS1EZ#tkh0>9Mx>3O&ieuumZS8Y|7lBDfocE_G>~sB%Eu7
z2EC1L1C7JRwP-l7HP~a>I<j?zc3VkE73BfXh4GSgNCR)F`Ma<#x#F_sSYG!N!YLs|
zZRNA+seLl&{O+fwQoXoD-jw#bfJoLnpSkNEctULj6uSq$XMvK>QoZ(%70sqkueZIt
ziL$gUbQW(|IFg*)>W0V`VoC0MiPe^_o(@Xc_{jSL50cD^Msov&f4I7T;Cnyk6u34J
zKiQi&c3XW!+`2H;m11EFZ`w4ibD_TV>a)`<{gO3fZfhk73C%0^6b0I8_Z3#K=?(nx
zZ8XOJNY|=>eW<PTN01(Bt5q&YExy}2{j>O-#OEMYvwlaQy;oSx<bx3F$yRFXeJaZb
zD%uPCH<3zz^g!W0@fmJ|{%$3i`^Yr!+HAGp6h=N-{`Tt&|C$$Ol_@Uc+V<Br6B--l
zCC2_!ZzbV5Y}S5)-Nk*Iz2#GQ6xYdLDVT%LkT|yRaoC<OP8aT-8`|?5Hs$%~dy2+X
zI4eyazQD5hYGh+W>(E2QXf)5x!YAq06v=<<)j@NU`jIfq>h*@y%{yoBXtRRS4}6xo
zF@#&+w>fAmYfK;3P7;7ArN@1Hj5Bl}-=4Osf5=I_e(AwQ_}$CUe%Y~{)M^i8X<CQc
zI&VisFIt-aJ35@fH&A82p74_C|IwY;fhtATf=%#YJR-F_EQhjKL9{+l56mNWL}^S+
zg1dpYKm`}E(`A)9YrUQ}<u47%I|jU1voQ9XRy+1CD0^eFXfNIAH`U)$WL}XX9kE>G
z>I0<Z7f=2sH|OswcUy(86h?!k;RO8^Wn9e96(K+JwO8{w82X;<{o{GdC5O}5d?v5|
zz@|L-_WKuDI{MGam$gG`6Hs>hp^dZk9fQT<(o;$1kH0E7(jD0L3<By4iA`+%Hdp99
zu(@2BIr7*>2=NwP4LQq{P5Xas4cbjfD}S;wHPbgawStjdv#H-s4LIyIgp?EAN9P=B
z>y7a<Nt`EXr_EO(+nvsDYHsnXl0|h*KTr+U7@A=(jsBr^b}WWfD5td+HZ!#n;L1;E
z(49MGQp`J&LTanz@dgS%!eSEc2)p5E@2=D?(Io388}5e1hg<Df%bsU9Zwm<(hh}jK
z+zIN}{;}whz{vvKl1Uu_<*%kSo|6RoiiJVjj<O?YUNaq%I_odXiObvfKsP7CIWb;X
zhsAwc%FPK4<-VRo%Nm9oOBUh^z}|E0R`4434_cCRiXuVC7O9=!o@_>izL3>HiBqN?
zYM58+pvv+K{Ivc(>`FJ8h{Tj%50u+{Qn$tg=wmn*A|1WpGd!~kR|f<VbfpKos^q~u
zpRvp0MA(KDk{aoEU)6+!Ats}pXVFncU$@ByIZMD@p~YCiMrf;~9l>kEFk_Q9JWL7N
zwG?Vlz_ez(UH;n=5NK)83=@clu4J(pWY&@(lu9wyjSz!QZ)oNfA#d;yzKhOSoMV(J
zH74y$;y3O{bA1q*5fy@SV!c4LHW;D@hNJ8vZG>gPRv>XJR#`mL!Tu~nOeYfvGF({~
zy#+7lq~mRuI&*J1N+8wUAp2CGUuc*&NM6zGdPx1BQ6lv5K^D^NflqW0depX+YV<gn
zR1~H)p9eH7Wj5umVnKioA`c4jU~a600!`96d=BClyqSZr{cei7ST16bOi!?2oB>+7
z7U!5RXgV#({K8UcJ7uDRifU!HZlJi}5);TAgm^49eo;r{38?1_WyqN*T~!b<%9#z`
zkmv=b(;_z}>05z|yRbTZd?aGAhvtX%VStKP6UaIpZXMACr3bEO>G$-?%#(v#g(<%=
zxjjE6EAjdS0gSLXQy6z7HIansc{9uKPA4P`zN;mf1qcq#2xPIqNr<85W6g6+NPOKX
zU@cJgDAI9QXkk-VgwX{r+fSQHwa%i}k=T9p0?+(pno=ebDWVpJy17}>a-kbZM?EIz
za4gKhxW|$@j1}nCF>TXw^lQbtzePKyE;1D&awJ@hB!i|-JjNoP1R3X49h@~Y&&;e4
zN^DSNXi@gnrQ?idlQN4{H!wZpx3b3N3GgZIz@@8(WeR&KY!QRYsoYdlS(Fk@M<5iW
z4vk?Pva7^*kg6{;g`Vb36rrvKK}2!<1T*52xF#79oYdBbZ$&v?ep$Z3|6bR--vhOE
zTH5J$y9&w#oA)qVvcIyc*smpk)&B8nNXb`f>+#J~=P_Gh2<(E3&sO3&I*0W!DC)}w
zc*{fP?_LU4Z=DSTf1*Uf;1UOaO0|{U##L&oi)V__?2`QIZPV@LH-h~K)a}4!w1T1O
zSXj}%mf@q?3Pw(6>4n)P)!UCYjYED|@NUkEaG25YQO2Rhr4vcAH=P|`dYw)CZ|1D_
zJF7gyg~!QzW}F?->8;*0q47~F`-j*E_)nQ1K5_Ac&Ku_H`PLy0#|WH&_Y#gpyqi_5
ztILB~xkJA|ZS{|!)cE~uqHsZQvbvKJ52uAIhI~|8PXtyWdR%hrajM<cMT#}tx50|@
z*zS{NW&3yul0(9tIg2_T08hSg_rd((@Bxnap0_nlMHH|GxCFJ;ia$z+!@lbf?ki%(
z{)5y}c3WNJX}*XnwRJBQ*pZQqT{>wqKhOK93kSILXk^~*``^5U4!c!~*&0qnMPIo8
z;A1F<pr&;{JiMD4%PdJLEVO<y$;%ARk{3;~WxeOc+2V5NfYtwLC%p0A<8-K{*)1bQ
zal_M=a*I^3v)*fm+#~QhJD4R@s{CkLnX=u#<K2;;3{Pt7&yj9(Vrgs&g{?2#dRueY
zRcE)PVd#CS9nS|TWEg~0baUgfW9NVIR}R>rkHToL9j}pS7Cth}MC*NUxOYQuoi5a+
zw*Eh_fmi}M+HL*(fcJ}s(=;sp7fYw#1;vLhm@3uQYgtY>_Woe4%f}|d4V!1@!y5Um
z1P%OawHZ>kyXj-f6BRA1n0pn?xbBmV|G{f>`%+B<I=pqV3CrH&q_&#9bkN+)4G8VW
zm5|Vlq>X<FD&4-26i*kohLc<7T(+;a;Qr5QhelweFw~f(n_aGXH#DBO=5_bk&c?^n
z$^%zlXZPNFO{SeTGj?0`Lb2P!A%*l~tcVm3a-`}D8>TGdh4of4kPiRTYx7V2-2Xl1
zZu1qdRVdr`ZS!+|>0)FV`8JhnKPqtT71nC)kLMQ26L^qbd})Wb@P3=mIgM@WV)ZO_
zofq(<VG6=5le<TEEToOCh+P3oA#Yr>gBc)Imz#ur)*ck1#?fo|9ZP05E^ns4Kx0em
z8{z~);cLT;m^OQ7SQ=TB+8S%Lzb*{&#y4}%d3IZw9^A|sjfl6e>TP+C|Ay_oKBV01
zT3P<)fZ0!&LdD?m5-Zx*Ffz9jP37hno6kLi>Fv`h(g>c)!H1%gNf(!_xc9{0M@O`@
zB`Lyg-{8AdPn@$<Npyk29G47mS<@wcl)=#F!&Qp>LSvsev8~T+^LFILA+;Z-gXM(d
z3O<Cfj&hh!uArKKp*oes{qpy%e&Hn>7Kxr&Io(2D?~yFe)5Elo;|2`e_MqirM5#(N
z9yOM6u*%Lh3O`br5Co_x)u!pnf?S|wY0JyHCMdZwE{}BUDMBeKlG<u5O&?ZG!bvx|
z#2Ovt&z^Lak%AYlvW&JEGy1Gybl7cG5(Rp;BB-f%p;O0_Ck=C&M~zB5nTN346<jL}
zO<MQ5*ET9IIyKf_%m;=d_|Nj~XtoH2s$zBa&G^_SRFRHUv|#OMlj}_26)$M#Ru;<~
zD*z7r^I#NuL+YOAe_9U>HYC;y^Rgtclue~@;c&&)DJ+=H0?!EE5+^1-^NWVYadrC?
zM@%kaoY^2^1W$tAv2;Qf9gCUSETnApLm{|`QX0MuM|QXt>V-36XnqMbUZI{p?CXPE
zOOryaP%5jVaOXp%MPk!%!ljfL@STXNgh`;EaV$nqz(qn<$qX+Y4Oe`KDFjdx$n!k;
z9xX+^$*SWDD$qth7_h7jsqXdjNH3r0#M3v=?(&#+>uf|viLiXUc3On;WdS5e{#~J{
zx*#sV^Q-YI16<ESp(&(<Y?f!>=NuHlmuFol#xBFpY`URxKfn{+YZobk<Aq3Bx=D0A
zN%kNNXm+Fi!^h*K9Rhj`hS0<6_Y9=yN+f3~O|Tasl#0(p40Q=)-DO^90@ybJCrxdR
z%%}a7A|RI$$8(m{NCX>jkp;(t$tvb-Efj5@dUMpYq|pbGg}^~A$Nc<ItBV>X(Ti3q
zw>@*U>HQw6`a=+kmr=qfGZx+fWRuY!DFcG-A!r7ADF9CwRl+uS5_tCzwcACzSm>Xv
z6LO49f8(FUbg(elVF#rr@ZK|`*X~E<$fgq;o?`4+S!AMC<OvmS{m`Zu7LiU^B_S8P
zi(VQl0nCcZX@s*tUkmJ%0sR+>1J)#lZ;TZVE1+G|sJ41_@{ZrLmuBVhJYc-ze1Nsd
zVS>O#CS#>&BPQqcI=5Ol>&Xhcts7V!SqF@8ld$j2mZA(9x3V@B(*G=U9;U<Za9z)=
zvRme~=<!Q=J>0Zl+e(9cxGibM?EN87Eg|mZHZk$6aykPI%R}bE<2qq@q03n1R-D+Y
z+Sl`-*;3ZL*e>xCvGV(*J-GGW^rp&<$<-Ba{&##~A7U}S)!n+!Z@zey7|xI*-t}zx
zLKmq^T$1uhkT@5K_#<pOw};00AOp)n-+J*F*CNgOqI1RQ3=>c{dYq+T)K<@IiD_{y
zxNs}?h_u+=;nL-)UH|6SLo&rEdh)-i(r3)Zszwrg;$iu&;MPN1K6zKsY7Z7C(sx(r
z0R|&cEThu$QR0qMX<L((ft*)X83nq5XMVVS+$3D?wt^Jve<(UL+HFnGW4-L_X5nkR
zmUs=xxs$U}TbV{EJ$752JGp~TmFUHzpHv_6$pMa4{~NWnb--r_th0FXK3-v+_BQ{;
z7~^=pGjrEn;B4^&7DDoYX{oJ@q!9K=X5<UMnER=PUr$|nUY-=cKjj{5Xs4Fo%RWVW
zSr1H{q?Jo5FJdLKb8eKk?r}8tp~<3nFPU(sm9wW`;>|s>VIlnOi!9}B*X53%%SJxI
zr=sHd*~W(A*z5meGCt9`b~I1U=S$n~S4&Ux?5|%qZ;kfw4U4Udi-({r=NxgEh|PFy
z@@6h;S1o*XCkLcZTRWaPcNZSuMa=Y0ZYXx|tcC->dmr8_VLhDZKf_1fPVV@(e5Knl
z!sHW^^OpRQWeZRFmVcD$b7zeaP_JL!ceagiYmiIRbA9Y~!Uzp{Xvz7O=EIfERM&N6
zYdR!6^PNq8QY3MlR>jjAN)r3xE6tv~$jl$yX0<QXC{pZ;#sxlcxAho_Yae*walB((
zjK+OQdG16WYe3q3IxE7@(#9UT(s((htPCpL2Y<rd)5%>f9Q(dc?DH?2%bVZLPW(-}
zXF6mrXD;lM0ejPH)1rPSgUoWp4Q_my%SZn(O~Ulg+vfQ($&cjz?$XBKIml(ta>d>%
zu8Jkw9#r%CKz_^9ers6ToThqR`ZGV;mc&S!rui|tfeMxF4K{8g+cKSF?hj}6PMx-=
zddR-=XvJ|!U9!n<xB2iC<$d)wD`t0s(A=Ksl@Mp0SHwnpERH7b9)hA02=2OICY`oo
zdlxlqC@q&Jb6mzdI<h<z=<*@|=JFNlJlo6kGVGoX>6>@Wai#mr$nx)I6mS<pB&Fv%
z^E0!<!ATWQ+EowQ^a^VG{Tml4UgtW@<?4@~ZNHG*N#NuF^U}lS?Omv)4fTvSjal`i
z1v~L(OTx~S)B8!FrP`Pd0N9^YtR6gl`$^)!l{X4$9S}lzFEZVmc#gf$-~YAZAmg&$
z#RR<B0kJt(tSrDs|I->&&9bq=la?jSJAQcbFog-SfGvO_h`S83_~_FvqqpH8;;&P{
zN`NGKsm_#cNyps0@}-Sx6RZoY#NpXkprlQ7Jhxj5UA(>zue3`}mX!Yr1Wz?7Yf6<P
zj~V?%#!Pz($-3ea2y<rlHkmP|Q(_cCW{u+XBv5A_M<{c3DvJ6R<-p1vLBLEqKGrt;
zPDUM)6=#mIGX(f8nM56vcNS92RmHqkf*l1aHM;~tqs4Q81*-&jT9_<-RdXXKbLGgx
z^BYVm>u9ho2P%>%Ss#lIxs$kwEaxI6?qrFe*GCAJZjqx~@U|(3I^@-ZQUpEM8cz@5
z-b(KLDJBz_UVScQ;gt#CW)iZ2JYDgcBsK3;(1DPgdY#%G6ncxMiN~0{XR-L;V#396
z<ZDv$NJ+3sSU>Qo)AA3S3}B`ig6PHw=CFlf9t!i6OfRU5@%+aklJjbAHxlNcKcaZa
zO)0>&0v7QP3c(E)NL*(vpA;XDUx!~lP7DcmZXRQ8P<KZr)tCTr(h#eK-i$8jhH!xZ
zlTOyS28L#lu>y~8bB4}Om2ST9)ZvH?5+}p^!i$s^F`XSPS*@ocSeb~oKtPeg-feWa
z^6{X`q6Mb{8iOQ~f`u>6802YOplAgmCk3LE#0P~6lwn`si=GjO>3J_6bd<mx#M=DQ
zbI79JrM3(@lj+#buq=4Ov&&Hg7pZaBp)wvsE(6FYk{+n2Lm8wyxZBDQgdMoeXY`N|
zKj7$bL``2tTzSmdD>|unc`8L+R;X100lQ_L0mO;q#4KNKFt1#CaRc2;f9P;Ikz%~9
z<B=2jyr3N;NunWLkjm-!!^tqtA28zK&8DHO88fHOQA{M#Xi~Xm$u>jk-hrAX7%V3Q
zpUg{`La{JQl^B{QWNp|A;(`s`X3o3H>#b7N3({RU5AiRPuIZznSND9^d@`fF8srY-
za$L~ceu*mMARw_;1+WH=N8rctgv`jq@PYXXKFpx-0m^K>tbIT`L!fw}K|)Mj_EIvm
zepwJ+nXNJzu@>1lvyEZEZpNcSgHe;|p%nP_fetKGJxIaWZQ;qSJD6n(Db@+oRIpBu
z08>GUUrBH)X(TKKGks%G#;aK>YvmVI-H{fNTq&~^u0(u^f~7AktE&)TIz6>czY3n^
zSml2vs~Y(K1o-dI7RKmvts`P<{2KgXS1hTn7m|ornpRe-m8j41b@G<a^W+&6vI4zG
zD<1!Y7QeoPR8Itbv7aTB9GCY<tBibFQ?>B9z|sKKj96YFr^9$|jMDA&SjjBNrM7S8
zWD%^AYTla_2L*T;zzY3yrF)&`O1i0r%@P=}H6YO*T}sD5y$Sdfj*hlyfs(4z;5d+~
zR^DTBGIqTLJP(wvFMUa7y->hV5c1YCM&wV?Ria*g(MOiG;Hq#+kXYsDRSCJGgiE57
zoR^OPoYL3HPu4CM>{yxW-xhn>DzCtgY@>L+>?yxh0g;BTFX4eux@7uB#h4|gD0BS!
z0|n!RrDd{HVlVsACfNq{eT7(B2^BF7et}<9f1G@xenVPrHS?YTpd>wLAy_+8Kq6yp
zP?ZT0k(`|ua_r~RmGyV$tB^Hl4=HSYkdza?E;4lEAzFf&7gIHl10UQZO^8VE!HCrc
z*_BNL*)l*a+JYGG1Hl{f3XrClY27!uf*rEA*-(g1Hp%pK(ZT$hC!}b$+3GSLx<TaY
z{c4g{{GV&lyLBAdih%rrN-x5Y$cOGM;LJQ65+o5ACyabP%Y5x}PDbEGnEX|2omxOp
zWz!A#&2_X3GN6gZsO2+{Su?<6o;bq#0B1j_tPU)aw8@yWvMM1^x_AZq4DODN_59EL
z)O^}2*vTltdv!Es^JL{^QRUSfG%%Mag<a;Wpc7^IOl(2eYpZvr6?R&1@;#MEiNhj*
zDvXn`Q+`a2RsqDc$=qwNnRQHS&*IYq$!{H?RQVm)6Ip_vQzST5?QJocgv-;oPm>i<
zXkaH_^mu;dCe@5=D=^FSsfBAI?V*t5;&hkxbe}l_mF+sA)x|r-dU6fXf1OmrtDSjH
zm#qVQ>TgejEv?E})jqJn&y7i(c1b-OIUM`AA4ii49bO*F*XD3z6WpnZVYSHGI{)%C
z%g3t{iwLJNT;PO93BTvKc~6o<)W3uXbT{V=N%$Ayd0+H5R_VCJt62@!*-gGTRSw!C
zzg@<O2!7K#@+4vr&bG1eiW%Jo=xIkI4sij&_FsSzGG61m)|-90K%q@%?{GB1^y{-h
z_o<B}x0C;&`(r6Hi_Y6cvqsd%ht0mhHHVPy?51MczOn-mewg*)dsxOkQB5*Z=?C7R
zjHO39iDl9XF7#rQH-R9n%E66E{gK9O==6ftcxFRa_~5zrUWL(6k?P0WQCx^g1w4%J
zE$3TyqyYnaDb@$rYSC+RRASl;sO{`Z?i8_M7hZJfkh}N2+4Lm7ec?E|wHMZP=Q5l>
zQ%W~^t@p=&jJ`F2`yH=z*1U{tK}siHoE7ek7tW{q-k96*Untt0+ga#=xJYhTM84~Q
zf|sC@wDvh`x86*;UDYshQs;EudE>6&1wb0;9Gm9JS($z6*37vZHY`}>`eNjq_sp^Z
zT}jo!x#BJw<;aGy_UB*bvi3r?D0bzpw!r3y|K1kY;>_mN+u9J%mq0A*Pnw6a+0ESL
zve-Det+2P&Pt}F=!}-kOJ`Rk9pXMc>T9T1-Kj0FYmonQs%r?*so4U$U!aH#rm`A)k
z22jRZEI-b!#O}lA^77yX8M}DQjPg4y@f^VOmm`+Oquc##Yb2W<dReM_WBb8_Hhm*C
z;%^5M`>Rh=gE-wtK}unnc<4VNv^SGLWx=ez#k|Mv?|)a*7C&7<W&ddo5nL1OLZT~<
z+K%`C`Ni1Q0n`8a#hDH{+K~p|=@_PQ0&4YMmb94Dr%)JjTb6X%yR0=hx)8r4GH=!F
z=gxb1+H#Lwn2#yjnMsD(d(dXN?S;FB(y6d*g2fsJzlrLGWarUKvoQMlv2;3c=0$1u
zfzHG2bfERI?M1lp+y1sr>*AGIjT0MecYE`|&iwn=TJz?&W##$dwbP?z=*xpQfwi=<
z$Xg$5ZW&9$xdQ}*6X~Ig()=VBA+V#~PW&HQ5q3(}|KwUafVUkXF|kORERAs6<7=KZ
z`%=(pVZaS!-u83xLOrDxT+l`O1-?qNWz0HPB#3S>Ew?}j%jy3)lt2MIT4j76bY1-N
z!5{*4>w#<utQJi>Ot6^$TzLm76#MzK<GooH+Cz(4VyM|p|Muk3fqYWiHB)<;;wdMe
zgtmPJf>Z@VT+PkGK=Z=3F2mf-{anViKFl{dOa(-HUs!;H=7qkh9iPE(avq`!Sfafx
zlO->o1uXqQtT|P`6`--ozS_^NlsFQe?K;}RiYuNl*P-oD!T74LvBMoh)-pUOK?oCS
zEc;5zAtf`3pw7>0HVJ7NhH7qs0@AT<Rok5NDV|CBIvHK?t)8vVbHlfykic^6w#3x2
z!-38t6s!aWyO!KN9$Ouy6%JYOOrJ7K%nd_XZ!QzSurwr?NBDu_c({d2L_6s!X~}ID
zb78D~01j(2VzXX~GTxG<INo8z1ahm*V-NiL14+3Fp<#(IIwq^QfQJ%X&$8+%;UvQ1
zn7zCsvUqID)ern^#PG_Q?T#|@jNS~UideY=GJ8-+%E(DnKvd;s0ya^52frSKo@K3P
zAcvSzs+#HL=z<6*z4@43PFI}Ke|U;@K1X@eC)^J<BMxONRPBA(9G_Xq&$B&oDUtO>
zORrWKE1#L}p=nr%1#*J<bYBoZN2e_EHp_(E1@R3;l6j6}(+M`98zSrJVSWWe3VP{4
z#x<~y(pu(tra?M?QF5a^d<UV%<YNY50zYuXr{rIrCzSonFq+w<O<T3%$(7hsE2y)0
zpmLYo+#S6mUwoi8EN~z~TVf55ze{~G)TIKar=M5{1R{z~p3Hiwln#pkwKc9u7CihM
zC`ns-RKw14N#dG;(sVQM=B>@AQizO{ik&rRa?+@oYSayNbCS)HR%)(J+nosbxQr;V
zn&LP!q><tLBDz@Shyt?JqkFta)#D(}sl@Iru5b$J1B%@n)k&Qqa~MIjC)UDPUPvH!
z-HO`nf`z2GMPeR{XOSF5SL9{ukgzLbT1Opi4^Ue}%v2se30i&VR##SaC_~M@fvR2U
z92;elWEcFYHNc+N>7HeLOGgNF9Wv=joB)sCE*M3ELyU<voK3RibVyly7+R(l^&VAB
z1lEIMgfxDaGY1u@nnM7b1jFv4G{G2LjA3gS4sHontW1_GEkJ?tmFtR08@h+1flIqN
z5_i6}0)GAB-JmR`mOy`mVsuh!>yUk)@rnSctzYP=t$YRpw)QGF0lL;*vmCy$BbB_`
z8FGm|T@qFXuVF^Db?>fL$@|F?6T-=E5(ee%yK+$&YAfCS2BzGDEZy9cOmayb-o2St
zvC9jqKTN-iLg74C{+A`L>qXhW#ap<X-PncHS(@6xB69}`oSYcEp_<heJoWGPfibDA
z7C%-gwe`fS?3VC2?Vw$!0FZw8S0tDYLHI2F_9K?MP8PHk-yd2Rg%DnG(1RI@r8~qs
zRSeL{rncsBU%kbTe4~-1$tt--jMEwU`|{2nsjW9stnkb)uSB(VKN42JVT8BXAl)Tu
zFyHM%9imu;8afv<?O-f!JaJ)>@7ru6L+=^$U2;yBS<f$6R9hb<b<tQn<6_9zptn))
z&0m<<-r5bW%tS%Qu4E4Q<e1q<ezlO=I`6|E*9HA)myY4HyG<%4b4Ft(w5S<Fmj%1^
zqaaOgniQ%y>AdS~>pcCBmP~wu>QV&9=vlM$f_F0dd>X+_QZ%FQu{Phxqz~iZ+2S1R
z)7a-e%|W&HbTZwjo-<;{|4Xp9xk0{lNUe~nw9wqtyV^@xof&v3&ZT^JA=F9N-LNJ0
znL>9Da}~vjeY@@01J_x4``!2;{l0((+;TT<GCtG6<pOtT**oj0t%(BigHl^Bf;FY}
z@C8M@k~E4@YOAAMI*rb?i}8z`Ls$3Butb=+mzTmU$?bLbFq)#a0^!3Wh3)y*xj6~_
zuGhqF$h?An@bm17et%;K`!D1+rk(Kip~T|wqo&}Wp?<6f{BaIE|A2D*LW7byUwyIF
zNx>gY2lHg^jUjMvO?&bq--RblfB)(0Oz6Jr!s6sKjc0sZw-pr$$9A(z?&Qcz``o1Z
z@C%IvDRXnj&bDmGVf)SoZ^<5mFJ!iigvOQ4+A!H^^65kBOFsGxrz|h46^J#0Yf-BL
zWn(ve&^K?sWPvGMe;DNLtQ57CH{u|`_Qs}<+M2b(Ezm{4*2gb4sjXv5ta{toY<trs
zl(V}>Vg@0fttXCsEf@Wp(X)@?212lcnzFPF%x-6jwrK4+o9kSWI}6*onJA@as`PY&
zc^JHTz?#jUY9`^jF;%D%k{|VKYd<-!2~UhV^)QhnOm>+M_!uRm<~gv<B<dQZ;Lphd
z<-;P&+4CdraJ62!jXtQpiz@$ahQSW+@P%t=<v&clJ)uts3;A!y97l>P=HFzMK|1<H
zd@tAasSZm&@ZrZ-QhFO~jyDibq>r8YP7_S3ez5;<*`zE^#@gTsX3nz;cn3ETnTzt3
zv?oYtWyw8|2Q7>esSzZUNf}vrk|4v1Ofc65N9`^_?JW}Bb(bkPT>Q{affd}I1wOSY
zN$$$J3(O6A*0rB35%!==r04n=7N2(@pAN?<+k!XW8g@N>ZL4ZqLjwd>UNXn>jdO6m
zAa#qo@ucT!Fp)@D_Qdd+EiltBKbhwtxG%hnNC*Oj%De-6yca{O(nuU?^x+tY?}?#@
zaGIyeuLs;q&rE?x37roG#fuERpt1m?i+RhcVxV%z$thkwq_Kz>vT!Qe8EnWiB9Ryv
zMG{tY-Fe*g>><oFZj)hg{D29FqbhTgq+ARX<uqADqN#)#`K}jyIrry1o~*mJAjwN+
z;xs4N1`6sf0?vwEsI3yqK*#DcNCgFpu@}6c&g3m5kY$R9?Djzm$er2X*kluL?V*r0
z71|%d<gz#CN679HQk##|kX=DZM<5r6WgQcyEb$-)SW;b);AEAs-7r%GM2M>gp>%j3
z1uI`>4}xHA7=Rz=9SVWG`an|VQt`r*GU#LhrhRV_1RCPd8TF<zkW289Wa7H6QxDBN
z*9pO0MG-Mt0h0SE$at~H<pI|3nS`j+I@p<YThhH|s)ev)Eg*qdRK55-DQ8Z6`WaIK
zEk2io^O((eT5y6-A0R=Rxs5ogNKk#rLxNo*Fd&nG)fYJ(!gOC|1DO*+KhIBfQnrMe
zDqGxfbU56@sI5&xl_JB@YLGKk#tcqeUu0RpzBYuIW!3@9^HZV`v~CBale{f9k0sX2
z=q2w+95IHw`0dEDLI59VIqLzZELE9TW|}Lp#Ka<PPAlot0f*zKY^BF`#t4q>nA#p;
zG!pJb|42z|64b+iSBF7nV06S(b=^+W2PnU{lzGBByYp};E?pU|PKvi9*y1&4QRk;+
zW$%-sCJ-Tw+G$yZh5!1v+xmSU^;v8FY!XhXt#5&b9;6KM!71JYJA4*?mgUl?8Si_+
zYd)EEjkG;dz7Mp+UDOHlaf>jjtsjn_LDCk~lUddz!k{nHf8@8Fd>IFU*6((^(C9j&
z(Ki3CVlW(LwD?PqIxp#UkZnc+@6bGpggG_6Q8sP<XVS6d`9;6+$zh-8Q*MxXl;bOF
zVUQ_D!6mFoy>*eR+aItV@#TSW3wNY*e8$n`TPvjfbxQOpil}+*8L3$vkfnP+&pd8t
z&{lSqAAgx&34Q1l@Q1W)V2c&sY-rr>1D^2weMPycDz%krrv*Cgw$}6gRtE6eTp_h}
zu2fqsbsz<*6>95C!rc7l7TQ;RxjGw;UOHY3y=NV4c>1uJi%7lB(%2`?pKa(a89}wa
zl`mM#mAkFiT`-~!Lfu>JhupG1J5By>Cvou5ZmX$Ai;m9z?eoG~8xTjhe}fHv;&ZvR
zr9pk`C0;QiCm&=-FuN@;-1iQ!uhg0J;b1MVU2}*WzPDk)Hso17KNgmGrHbR(zh_zV
zyTeW0zhV#kK`_TgdcI>Q&#wQK?D3g}3ntiY<u<mD=h@djT<cp3;_hI$W<zG5_*^#M
zU`=55TkLjsAvtsvBz~JdvqNsT-`%#P7j&j4okd$~81d@ZPtp${u=+HYmn?1=?e4bj
za+4q5LckSTn%FS@g6sZelmmkZ#o~#Y{MI>(T<DPb#e_>{q_(aj+tEixTDI8!+D0a@
z_cBTO<w#-Rb*6AHCp<p!X54>qN2JHdgs)dzWrK^KO0vaIGP+1m<6ma*S5DAj{xfPI
zeIQT?rk6o{_?6}x*C&&mz1vkWltS<){{^*VYtTnG!sx;;Pn!RYDfAQ?$BkcQ=D&D$
z7P4_yN(!~rhVIO4s+HQ-bURi2(>3&miF|ly%v$>yJc@sO3CcLqS>C-q%G~1*9I%T~
zTdziK<-?-vc9-Bd5i-eDsHkJh3A?RBD;r2_v)j=Z58n;WQYyv~nkT6(VPm+3X3N)o
z)8&h8Xi)=%+LYhk6cVEixyw>CY2{&QGOq;6C;H2~9~6FmE`2-0(%c{eV|V!Z5!>2f
zCl&JwZzD@~s-C;%T`B8_!=3c-g<an_t<GU-{uJ(N|L56H;?rUwBTUdp_i`m@4}L@y
znaAONpcSU~BrSVY>MqG1N__azqz!sz{PjvwN~%LqEnb79m=dR9Yf??PHbzPpY0Oy&
zNoGH+IHk<%d1obBM(ziheI;>@F-@N;nHU@yAdOStEldYF^%~BoEPWsl-l14h;W-%w
z&DE~GtI>K@JP41l=*s6Qvw)$Hj%x!Xu@=An;6d>qGFaLrN<8ieWlYC=dJBGeBnpeV
zNqv^96MT&;SCoO{Z6&WDfhG~HXzOEum-!w}$#c)8d7^O)3Bckqg^mnjo5Tn2S{pfM
zWb5jrV$QttJR_X2U}H%f51c8qNmGp+VXqB{zkZ+@HZdKKPO?O2r2AYVI0C!^SbH;6
z&#dC3{~AUn79t;AL#|F8L)_P6F7k@BMhhX`=jsQ9dq)xpXJWF{uMRq$Jtm>^k$ytL
zV)TsC_+a+{X;dOYk0NPZ4pb$S5+_(>n0WK@Dj{S&DfE1v|MbvKA4Ac&GLS;s*F!@R
z_>yAclBs}il7$MA%#z7;IgE~4o7$hx)Ch6o7TS)pAcJ&>-}N@(Au-!c2>U{TD1Mrn
zH{Qm>5;Amoze&0WQx$=ytFcNIV5Wm#4;JaaY<txzkz*0ME=b}i2`Y1$a46RcE`Am#
z_0pFKWH#y~QGf~q%qQ`IF=lytfhQicb6I?R^fO{Fo(?d$_A(*HWUtnEWKLyS1<^H9
zs;ybZ#3`H#Ole-HTx;919;Pg@R+spJv4}PMC<MeiOa*v1_xv495~rcX(|7nh5!(dW
zNBE_+&>nG?LD>-{G`D|}PD8(lLN!o-v!3l|)uPVA$OMUmgrS;eo!<(e@JUEnK{vXN
zQceC};@$<kvf?__T(!?WM_X#qY^enZ+(1c)ws;s0FB@YpB_XgNI62*JoVMe~p@T^q
z``+7mm^fd2?IpDu1SYm%@D0v&lH+zyuH5E2#5c*1r#EfvY5U_&I=R>(i8G_?kMTH!
z;r1|2LL6-7U$xIstDEj~G>`9_C7r!%SFKvLYSpU8s;XVPu$ZfPGqU6;-Gi?9c5MiX
zkAw4ha%7nr=U2L-gG<mM5^c3d-sPs+PS^?WMur*Fi@64-29DSxG6poH93_yGdZ4*$
zd&Ur6@F$c+h7+Qv-ac7z6#Q{Ia5UtoD`wNrXEAk1AitQQ5~G=`5hSD3H;N1uRmFo5
zQMS}FRD8o4Vb9h*!5s(`dUSh|nV=;~Il&`aY~VN1!8z%jC=7B<s3rX^xPy7%Q<ZD8
zB6ThdEdLv(F7Hg5qtRT6!6&|W%L8U>TvRob<k9o6#gi1X^-MMi&tlJN!fI=4ZkbFq
z&=t&P<r?^PU?f3XKPk@ljo!!6FKsKS6MBNXCn2R~X5))_A)ivIKGnveun6PDN?NsY
zS9uwrbIUgd$H5!pD}#BicTK6|Reo4%LxZ7dPk^ql+Ny4F=%9Tv97UuMJ5&Y`sVzLL
z^tmRV=sa{`I6wQ3V;7=*Pu~dYkE71phn*`vPIHAZAS`RMpNv**o<oF&7!}d`T*fBh
zMna3p_bEVmVIkBTclusUu;q9{4xb@*g8YQ6INcgG9?sPG!)(1Hj3w&c$}90#=+Rn8
z;7OqFIMqbsUSP}hSzlz5g-V3knzKnb#DD>&xAPa5;wE8RZ50m#k+>4&2`Y}%pLJvM
zC$FLDIMP^8vU2exvo>*pbz|<Z$`VUm&Rfot(I?r>L@}o|+uMofyoKC4fxwl6%*HNB
z{EpiKJ2{hT98wvIE?;U$J)ynYN@ZwbLFolns&r{wie&Sc3^o~+JWFxq3yJFOZ2jB(
zM>F--)@qizTe88c@0Nhs8s-yrrSJHMdt`n`b!>3ImwaN``jX7g-28r6J?)&VnT$@#
z(vM_XFX&UF-wUSn*|+%CO<$Oh`jIg{K(Ud=ozeyx`>smp8b_rl-r%yEzFbqO^`b`J
zPzKK?VXN<C@gvqT=={>Xxo4BG_}i)kY^0Oeok>_Go!Yy|HJH{cTPDTtxtcn*!a8@e
zFOhq$b&sreUZ9-}Mn+bs0{hQflz;wMOx6(f<?At=#u0k)V|3JikOUgu5D3X1!idVB
zb-I}Majpcmg@0zQ%`(B$8h4!G>H*Wgb1y5m@L#`~Uf>VxZCq04Hw6K2i{sm#Oj6nL
z{xLbUor5{wds=n6!FG>%sg4XR{96V>N1Sr1Z)vtRzhBAae(a5*FPtGue|oOF%xczS
zoECMlyF@N{^q1j&=Z2^@J@^v$Twcj?wl6<E`b}|*MPKZliPfS>@G5jX13!k@n%Ng2
zdI8n&LRMS7+~y;yedurjb>IY2xk=Aj402nh$$?WRvc|7dq|c(0jbA-VR^wV?utuhi
zbRI)W`fi59mhEmpvW$M|%YKpu>j!&yI;TW`*A$xAWJL0zqtP`w8@IW=dd1j-@|o(;
zY`BDmtx-u~DZ+62+^Y57_Bz3>;Ox+JnO5IybltC#e%rYY2}xM!&_21*4{@eaxQ)tp
zh9v$ao6$NjG?6^*!p=ik8i?$T_K2CSu2plg`;10xJd<zR0OM2{kb<^s`Q!dz__sr?
zq-85nJ)m%*DKki|SyQ7W*~;-EjI-^@IAZpv_n>CAoH8nhI96DJCG1!QV5G1NZ{bJl
zS7M+rL&DB$k7o&oS34%2n~afRMwi-wU2g39Z-;sYym@*Qb(kXEZI8wdDIbM==`n_8
zJR3GcR<3Jd4UM(lYu!FR^v&5#`6abDhP6k7&+*H`O<cYGx9AeEJV)LCC>rn_gv~r@
zI!R28gQM^ksY@$0!X}}IeK3wZqse4RjFJVPZZ)5t;KgVeQ<iOuy9PWZLL%cZ6G&E)
zqF57p5~n3gl_?1-u^9E51(T|Ay9#{dX)v|P5^J!ILRG;BIg{o%L5aK_#(Ha$>62V-
zCE+1ZBR}-7z-CDTA*7*!fYsV)i3F)wv{Ck!JVBhaR-|(lCqmkB^twY`O<yd>vulx|
zP&5fUB*A+^dACWJcz_9ZQKpB_lDXn{g^mdV!Q$Du8gcf>%+2XU7Vt~v7YMASA-BdW
z-N&5U46EWw1?~wf_|3_b<-HQra!Fo0Fpa|)R!h1`Q;NGQ_!wHI+AgqiRh(McfhFiE
zX=Dkt#gC9cYC*wdjdzPVZqtKg0$DT>{cuiDci_WqAkfamt66FhG!ibIrOz>HWGrQD
ztm*`<-hG<t`0CS19afAmY^w*8UQ`^X#uRw0LbMx<mxAH1@iND(Z<$-3)cP7D5Y=wU
znzmG3=U~?`1qMTbbl#Sr>t{(44x5CmGWUeSCCli+u;mb8tlg&2nG1-rN*}gL&>Lc=
zYQ98NEpX&zM)OwbX{^P}q_Z>vo)PLMC1a&*5s-yd5KhAsK^ZJ1nDpk|4Nwq?l{#b^
zCn`&1+#TplyvZXSpYlFy4RNV*+6lS!1SQ=GTYC=^gAJa^UovHdhBB&{1Bfg;Iq#P8
z5#4S3fYJuvzH5wP6HuUJMcY^A$rF}d7OQ4JYy*kRcuR1d-~)(bvG|S=AbssDpPirr
z4aj}Tc9LoHd{Vj|<PhwmvNr4aCUH#I7wm_qC>v`!5LUp7+XJ3HBdy9^5M^CUs*g@_
zK+r~=k-Nyu5G$3k3-5QyL!F2xz5CpYd}pdD%WpxAwu5)1osm=7Ve(NIMh<n(e!D+b
zk)yJe<;!i@0MOEv@U;nSigV^}H7>gXa<i#))dQI~vo)-ogBnI5d1}EF=W%)+c!a?>
z>!kbS%Jck|=5_G{Dt?xskfj%dA^M1%lR@R)lvCW(%yt&@abTak^p?qD{=Fe}#SAnH
z|A?H*`O?kFoLD^|;X@f1l<JmYhvf%jfk8$Rqs?4J<8S+Sx6%nN{(b*Isc~IMdLnX6
zc@n^x-SfA|_<3A>S>UT1SzN?v0rF0U{q=*aRLs)=VD*IhI~nVaV&N9@t6t3x8rQMu
zyfP5N1+Qe%Q@$<s_09f*tw~sSc^c!km&!PE=Sn{Mu~u3%nb5aP)%R*FQbqjY`RV5`
zDytToJ<CbC`o9O|k!qAW2;Cs5E)<^>z3B^@vf5hYW9JHVqy3@oj3E0j67QdKyye-V
z+<pcg9(}W|^ss(C_ukkDJ!ux5B-cy-s7m(DZ=E`O=yx9%_gl}-&87eR8a{9Ox0rg(
zfqZhqrzAi8mn`UBHlbd-F=b)DMteU`I)hg-hOrXl-<SE6d>>UT|K=RC2H1G}cP;d8
zhKXt!ivrubbz?rA-A(H=CW`#x5tz%*%w_VroAUgbU#5}ybmHXnt(-yoR^nKx-$A()
zXT3%m^_P5D`qpVOGcp!F+-@WZKM8pJ_g~}1|8PpGb9XUeb5}4_<(EADzEqkm^yUK$
zTF%65j*>J})2d6MrdsG*{g3Ag%e@@>08bB{XG+imrdv}}hElstvcvT<IeUKT&xT~`
zr9MV{ESlKIEnW6^sRZqNa0^tGWPMz~CfS@)rwEwRnq)k@Vy^_7TGk)p9WXb+d9l7<
zwt%Al<<cp=`AOM1wXdQksqTPm$)yU(xutJZ=jPX-`$jd1Mh~lq4cEe+?+I~?(81zs
z81wm6!qR`_!$g+K(-lpgVlHfDtF+h}#an?>GFhBy??o9D^zTa*FY+gDDD?~3OxPd&
zyI*3mA5lKelJMd%c?q|5B6wN=SC?IMpOcf~WdK<oA@IXjj#;TPZE$0}<?@1?Hx}i{
z$6ZVBM9ZUpmrLmDbmP^6I#_nlhF?_G%cIcc6-XvvB``~!Dgy<)OYm-mIbPgO?&Mlf
zW8=)`{j`>f(5G5+`1Gq|Iiw#HO>{t$fQ7&r*c^gQU^fVkG>?cHPRctemeQ+WoB6Q3
z`>KFfdxWE241%(NrG-zj)S(;sae~c*=n1hlKQ1cr#TIjc%ND+P_DRYBBu&njR>_?q
zo)mJ6Y+u_`sXLkQhS*VQFLjT_Q$7X@fiAz<=)!x%o&dGP4ZKNqD2@-}^GPo*w1XDW
zoe}~!>;P~5yYd5qB^_)^Wxf$TxRAJy?!XmU*zRASP2#%W9$Nh1C7EEI#a`iK?oUPn
zo>m4MmQFvW_Tcp@V3>;9WR|njq*ypPKIQLQuZn)Whvfih@#FMc+v^wjk6Xs@ijezK
zcx4v1bmTu2ec9qnjwfg>V-CVB1lOZZC24Xo?QyC-GD3)ul>#*81NL-%s_if1O>?cD
zK5a_@ZJ@=#)jQn<8>t-&AwF_tssYJvPQ~)I<Zx$NCSVyKg?N*DJeO#6Sf<UL4fIRZ
z|10snYL>7Gj*FVkj$KJ1tJ@v7O(UEhprDY2Rz!<}Jto3DPab7alhLHQCbzDzhJ<k+
z;K-#x%KVfuXUS0<n`CLK<hI->YZz*284M2hV}~Y#>Rlw*jJ{ni<2Ffyu?sZ=D-^)2
zqf+a+Sr9$BL5<%yKZHkGb}?|?TEaLU4mYI{!JfN7b2d^Z5e=Xzj){p_6GtD01xrSj
znxv_)l;#|6Yv<p>sXazt;#&qwenS%QZJM8<R4LGD96>m4-XSyqbq6J;YPXYu_hC9!
zY5J352xs6Lo$7ir3J+_cN<%F5_sb%!W2f>!uWSU_CS2kk%~*VH*_GD{F+*)~gh?4g
z=mpS9mJmv$*;*|tgvYU`M6SmGq;xSq0Gj+aB54a>1ybWwD+$(=_J9BZP>gaY=@p&M
z7UE630g54T^Z3M`U=GxlmZek%bA<>?soa{eSEAvp^Pv1>V2;S1hf|J3(cz_#>JEWv
zeDD-3<M7yq$EJwmYo{+UN6mKCp43PXf^B}(4qQ%`T`OT)jMdhKn9+Ur$Y9g<dps&>
zwRy&qwn*>X`4+2{$w;#Xfu*_N{6a1(Zzgv?Td^0lyMwA1S(y^dR)n@=Je4C_#`vT#
zdaC&mzk#ybN)``LgE2KFe2yr0^GcPp&&kO7K0^dmh9p<M#>JeJUMIO`N>(}EL#;sK
zkxaf6QGI5tx@2=h29J=p<PWX%tNp=!kvYVz{VWs?`T<&p+%^egwx%+t^FBX(mHN+`
z*}B_JxkDT09iJ_qurc6gS2nQxo%6D?o}v3qT3sR2!j`fh=AACnk7EI|m31@**Z+L|
zO#0Lf#|ED8iA5A<b4AQv@in4veLkSDPQLmZyb#F;FTx@6!kS&u_!i>bjk*l3<la97
ze*G{7YP)1FX7@>}P7C?7zasjMUuby(y8{EWvDptXhoDeroiD60TlKz=$@mkCDDO?D
zk;p>7U|aCrh0lxg;|vkawy=u1bGcSF`FU%MuU5cEPq>d#E&7tdnF%lZeum05mj#Q|
z_(K;Seu1K*rt&2X#!B@sZAu?pBBk^VWBK?qOsm-&qDaaI_Fy{9){s-TmKxQunVB~R
zY5juZOp{Aw`=@VVa-33k|McE4&`?S3?O!9?9Vqw3?N$1}k2>+7QUbafYujysFLKtx
z((*=ecYlr0?!@4dBdYcv;BKp}KYUFhlXp{SBD(V@W9;EAtZBN})#{D=UKtAEg$*Jv
zUhm~UUEzYY*V43dnLpc0{<Pd|=OynOoD4lv6)XAlqj}o;;ntSSQAqZEMY5)lOuzf(
zg{)bvR^5NS)XV5WnGE>)ZD*IW2G3MCb0pInWw`kZF4Za4KQrodk=J@RO^_)~;A9iD
zZYH@S=dwr_i%Y}1Pwlt5>o<K@8cW&R$I$3KvEfe-?;D@#n60augtNhen<R|TAAjw(
zkkqwb78f4K<%^!rws4ro1?~dq&Z4<Hkx*~&VlTnUJ)<%fHwnWW%pelLcBJTqbZ&gM
zRvLr-gQa&DqJcqm>waM`aNdxY4gD&qsFA|Vwp)0b$;hWzacx{LQ~ECy<;&*>Db9>T
zaX#8xFg6I+dGQxAm<cjtBSI_h-p~pt_;&E-w~^$TtFf~0oy)r(H@Yl&sghK}r^X{G
z|LE!D$skW=U15FkyU6#EKB?qO)L~suqV$8+Bg9mv(!v&z9XBXM%VzIA5(t6~Ho4Ey
zSvuZyGY?7i51Eo(iM=0>ALd6xJRAqr1Cpf8s%$P8uV**X@-*JpYE0*GeeRJFnF*r%
zYBr_O9aITFB8BMq%pi7ige+=#>5kV9nbsP=6FYr~BTHJl2n^(WHZ^S);BX9>#M>km
zxEV$=G$LMF=3E8yA=nEq+oz1R)XJ(Cus<@69rs2=9_+adC<;?IBpvVwAzl%F-r^Bh
z;O8yO<4EVYE1g+bLjeC1LY{_%SgeD32ZFsit8K&qvosBqzZ?!?0?bYr6n0@%*lw``
z$9w3E4HxA+Oo+LfY)Ke-psobdprdRpv-A5FlZfB#lF5_px~a@<tgdn#6NQBX3@s#;
z9^-xD2Sz$p!+=D#M3e;|Z=Fldq6AqjGnH7_nu?LKSZ7{<C2Bup(i;Nh-xgOU(~Q~u
zYMcTC8o_ufQH}djOztSnQRBtLCWRVL_5_-`G1~H;ps7ZjSo0Zd=ZjRzi}6B<W-Nq#
zU@WAzY`egqng<<?nLwN3ou?$2D8`vZ$(d6trIOAFz6OWQkrwrEB|=pfy+dgt#qg6{
zRFaG@?PTnn%6vsUMAi<U&8(?UOp-}>92{69|C7**qP^9GG}ggD$r5ufO-80-kESG8
zf;as|jG=rqZ&q6qyPN2rq@352s?o^gj*>`JhhT2_uq!N-@**Lq)$qHT!f!)atE6qV
z;;Dhk3TiJ<SOuB3NRfCOVnZ7nRB2fb)cl`Br~2%?B}<$JNcv08cqXDP*A{0<J`KN+
zW7WJ`lB+aL4Yd@;7*sN6T-QC99*}j!zDP>id6Bvksl%;*(0nfIcz3zOgRQt&j-;ww
z^2~FE8RO2_^i~y^vU5!ygXwV$!EU2Jj^Na8DJ{{u8VE!7{9^fIPS6$tu9OFAW3xSx
zvhlO}7EZ$GaLr_dkx<$z{9?`bIC?-!!d6QMI-be-aC8qx=)@eFHP;OpRoA#<*kiMb
zSzO}j;6ydE(45*xvkMy~gq+w>Hfmb%ckGw3AU{!hmPjYO`WeQ3-V;`d1sB$0F<Rnt
z(&Kc#Zx~KEk}0+{YY|T14ibul`pJ>V)}ziZyTbX%IAh*CP4?BI*?OgXBTZ9zy|2m(
zp7zCw*9}{c&qlJvYO6JX13DW}<uQ6#o_c{^A+u)Rrk1SD<wH!0Te;lU!Z;j5Sbqg=
zGh1WT<#X(oNEQ~k8kpJI3ZVQuYI8QS?|2O_v5vX=!iB3cDgHzjF<YZb5WY|Dmg)1G
zhIu!?l{qfUX>g6cFxeW{@0lGo!fI;?#UAeGz;vE1B#o<BYw~3M5k`*7mr$hs3Fu!0
z^B1PGQ4CL>ZlCmB2OREe1$ooWrZ3`GljFh6*7_@bnf}YE(s;fu0UN3p@Kxj@kwT_<
zC*k*y-}C)!lS_?}U4y^m0te?hGh6-P|1+iKLXznlkml`RE|I?{#e7(8_4a?`Any;d
zc3%!4yQloR?`;tY;H0&y=*?alGmWm^j+X5Ds`z51FPXfFgM7?vErha5uZW3=yWy-5
zD^hd0#;etY)PKV}<pYGiXJ&Iv=N@`Xc<NaWh+g^k>^~!yz~ayS?NC^#Z|8N4H)XQr
zNQHB49_4@@sV1%8{o_==<J{ud+_`fTmOxnHP0!@qMBb*ACEZc=`NAF3*t)bh|Gd%5
z)q#$2rJ_Ug*U0G5VwhNHo*}_oGTneiuF&^L@&MmA@*s}S{e+3M<j?lFE*(gM{_xZZ
zx%+EF`CK<rov@h?Nz;FsCh&=kvTK8_w$fuX&1_}EYYVe=@^ws({?*4+p7>bB>3bM8
z|IQU8IEZTRQaZZIW)5>MgxA-|TY5D+^(moV5H5azI<ZW$bN?on#Sg?R#8-d^J#?3+
zB)x#G0FN9rNs`ES*l$W1iXBKLRt=c*>DQk<J81tlNe;41nojphlR6Y>eGNh{)g><;
zt{J7djGTlQVEUogXM?udnq^JNS#2H44qR7hEZu`ZiazoN^7vEqI5s14@$NJY1JuM@
zjI(dLrn+>jc)<7jyOT<)dj}@v*Pk2AIJC;A>ySr$Pj7${)PMJ!1SKWYWo~4dq&e+2
zmmfO+fyQ9`d|eFadTB9mF0M!Qo2N3cv(;8*vZ>-~u_1W6x|lrGaFZ)P>8_MllI5!!
zV^f%|q^W-lYC+>88|i@e?agE?9m!koIkq1<Y0|zwFwseAPErYqzvBV0c{?8#cxj?C
zFS{5Tga^lB3oW}w>Jek`GdIOMnN2ts;T~H3dB!v}5cGpRU|L72N8q(7a*0}px4mi=
zaK5;1A;>Sz%VhlnJjUs}ttpe-NVPE`)z*9vGh0izlL2CZo`vf|ULBw@_I-S}>Ou~S
z3T#<nT;hW!F8khVu=C6&VyXIqvUu7APJAl|C6wT(F0-lS7+CB)p<n1+YJJ!GK=VT=
z2lE3S%^C`DEq-lG`qD*w`vYsTRvredD3CoMkJ?E2=GY0ebSA6rQ08+$)Z(%*)E;S+
z_ol_YF<vQfdkFlfk0rc{dYGP1BoTd8Ks&;ko2f>ywZv&0P3m4r)Tec(M-%dvcoG{8
zv|k`3Q(T~`{E>j+B5)hA<T_ARDO+_8F~sl}2pQzkOe<_E=Duj6S*j7%3p@x*$U>YH
zDqUlceh&y(WWZsYOgK%_sTd=amS<YF?Rg8%ykS`==N4xgco<YXYnU_6qtkedTU-~&
zq(>4x!LZ4AocR#7C&Xvli~%oDSu_^_F}3G12y?u|wIB#|)^d~;u=PONHs(VTe8>J%
zA|^H-@cc*y9F{y#ansKbAUyJGbWIj0+mH&$CZxAyyqP}*8QGT9+vv}w1#jd?D3q96
zGnwl&rWXIipq^<gg6<;r8Hu><$D;A2=`|ke%GB0)9q;tUTHDa<FRKQh9w1{<6~Yo6
zmYqo+G)Ssa@hq7q;#H>b-%A3PMuLH)!YLL!?U40!B}6g-A)>M<15TAx`Qb_`;yw2T
z!l^@a@%6UkXz)9(W*`7jMixUh0&;f<V8X3J%PXj<i}TQEN|w7?D5n-EEE${QLXELA
zp22q{X<S8s0EbFiRgI#~#p6w*rG_?<$gOMy_lyB$I3%?9*0#2HRhRKkcny&jt3ZSr
zoz>Jj*k!nmQ7pi#f;(tO??wgilNZ9-BCh(FC{%1aXF`9qn=&nNvJDVK#taz<K8TER
z>&{H-;zX%<wgHGpu4l4pocS2B;UuZIsTc(yhk!@Qs1voOY~eviTXvv<VYO>1^NKKI
ztol&Ab-5^&tqj&ciYa4+@{uOT9QWJC86%pI(OB=O!U+#lSG#n;<DhaaEYe=eg?v!b
z0?1G?9j}I~{0$GZnP2EMDTdb#sD@`*IQq5*qS?AqRTd8D2<~jlY7N4PoC6&Ap~<4X
zI`gK$*pxdOrbhl-WNKec9%xz@t!b$82I-`J0F!9KO!{ZtJe!1ZWOJdq#X3no3gRy9
z2>V2dt?|QbmFyadV&wrX&lw@GH6XXpcWLq%M^<xgW>dzI6oaEPpZKFO8OVobwoZ;J
z5(JQ5Qm-wI%GY9hNn5iXuu-Kv43B>%SuGAEcz$L}DvzJ%quDyRGDZT6w%?%|f?U$y
zkQI|M!%2gzI8QlAIMI8)GPUUa8ClYLvzLKybBx~dsq@3cxMet`o)@!HWkN6+(tGLM
z)&Z7=>hfm;D=Xd}R$)Jy<B#;y8fKYJBDS(7t%jf2F?$>HEmF&651*E4JP-F<M83L_
zosl2tpE9#Ge<y8B{d;~&<x<+kF{FRHFkk-sv}coW76vCc;b;>loc{JD3}ru{a`40n
z9pjrkbEZi642LBACkmu<B$MrK9t|y-eq=*MzC^%d?8Kfgc%N_PGL5gDYW2gh$&gT!
zAX_$p@|iJq9${om9FxF_AGEkv52naz_s@W^Hw!ds$razFq`!@8(7tJZq@pe_g3K?m
zpLpRCul~plg|K}&N^^FlA`UYoXa2}9UUn~S^#N_RUZ5cU?i~83VoY|9!OVZS%_om7
zihro+lNmiRGi!abd3$>F8jdqPK(D^GT=!j*%OkI-Z?UxPzB`uv&f0h<b-(aG<kEcQ
zwUYeJhjYg!VUM`uYO9^DWM-?}c6!6jevEG{+&JLfJ8x5Y?5znh*s0NM^_Z>M+aB~m
z-~K7;&>PFTbkgL?08J(y(7d%gr8be!K1nzzf&S@_Wv%9uuE;*cwAP`I(&}22pZgYV
z{-5it{^&PjgD1^8<F&n%yw##`fHPj<sVA5fDXg~g0UX(><@O4V6ke+2GQgt7=(ns^
zgsKlx$=$a1G9G+hl4wwy9e@52B+iO@ZP$&d%-%N;f=w0-y=3RWo$bdr*Zb4BkN7K}
z$n;lcH>J@|?#UL}4!`*`UcT~Pj+F+xc&IO|MzYy}mH)-<GwaW_E~RB(Tj;B3$2pE%
z??kVcdHD$A9?aIyo224us|^mHrbB&-dwwo`;1B|6IC_*b>3*1jb4lUE(-05oW`_Ri
zLCk`$bL$C{%x39FX(VQCID&qcr6r+ti;6Vol6*E%39qyjcgJZ<QoNZA{%{Oq7tq@S
z**BNLg?lDtJ^I8+25LivT<J&T+Z(Jz4W{MMDr!L|=rLVceGUn$;+(hL=O_8@jz)tz
z+VLL-8*4~f_XkN{ScH-_>l`bb47s_RkjA3i8BuhgPS0esqSY}xx`U?rjZ`al{0f4#
zY<+tJ%C2kT=oBH?9eC-@Yy7)7jgs6#t2<AwXaSCe_H&rM9Dn*k7LW{T{FE*n=}6L&
z(6Hy!^Ri@BajpkG!Pv~of}iKF15F%SRzh4IezJWnd|TBxGAmJyv&bD8a81+lUSQb9
zXathgwo|s^FkU(yo}NsSuS1jkY3B`UTY^w;L<sO%Mpy(dfnk7b9A~xF>VkD+BakcP
zS|?*+AqqHRp7erHLxZAZg1RjbJl0@)bE{dNF~@5{PUaj<gA_J3#DAHwI+UCAlhHH!
zS|GW09<nM1D&FH2ZGgyjpm@tPLF@%;5`nTW=|<_5afs}pK5xk?y&Ob=rd^oy<~JW*
zb^&D|KBO3F@X{MhN1$iR=Um$YvXnyk0?%enQ(=@Q48VP+UM)RuRuF95t`c~aon$?}
zKn5juc~d6T(cjuelwjV2pfow7+b_C22&KHPHnYLB0P$^~Hk3K{6mo4)yEAY!fk#2v
ztt$i*ixFrmUVA#gT2``8hGIDd!g+*kGhfyKJZBysVp{=w_#)o;_!^WGI@`%k5Qt2Z
z1*6VGuw;#&afszSYMGwl$a&aT3mAev!{6x$C~E1IoOx+Fi`x|rz-3Mv%AG<nXA&dW
z)e1|EAJ!LKeB0j}#gCH!*y0JZ0!OQ3vT#Q5QW+m_z#E%(%Pc|(-fn7_uCSk2=zt|}
zN_Gs;<@1G<25VG84<(%)8OPup_n@{d14IYaS;?OWsIc*rhBSDWCJcjl;~I~^9D}`!
zQ72WMOZYfmNYX^CU0x!4%3Um?=b<-{EE08M$g})HJBm?gncD)&WO1N+-YTtHmaU!g
ze8EoW-fRO%8JCd@&R#%L3HXn(Hlqp1AJiBl*wvnMl86C_!F+5|!SaR)Z=894;yj#b
zVA&Zjs}v1>F_NLQ_(_%DB)?#}FchQG9pLP8A4*z-vo7Yc6JxjWRnd5qysVU5biz(@
zzuNhT$jF)P2bn8eh+MEF0|lUu9|K}3j75`4%&3Vp7|R>sWH%4WFJ^tE%#}TMftW1e
z9qOTtYsq?ZTWUzw5<#E1JVp{~Qo9%~S}x~Ee2+JXk+aj+Av$DJmX*a*6gO%G?nuEB
zX^;gq1`2yRonK70R+M>bnjYGpH4uSNZdUTf8E_o)!B7lg9iR-&4c+Q0)JEXr{}q_3
z{r>>}50kaRHVE<hfB%B8y2{IoG$}Rvx6v})B){lWLB~wZ3M-}r)#m^IORx&QZt&~I
zjEKICU+WSrlMwp=Lt&OMVumu0rkBy>&9y#AOA3bUj>b}ZwgT|{0zVU`N!6)6v>~;~
z-n@aX#Z{t|jbho!)ES^?jOSxuuq*kFiEwsY%vmHI36oH6)0T#nCdQ~`RQXxLHuqVo
zfq8hl7z$hI^1?`VlcymY6#UH43z0J$qM1sSV0;8~TGK$nYVNM^bVNPM;W5a$wjYg2
z1GV;$v?T;CF=w`fQjSCLF>V&Q_XJDUAlQ4A!<i=@P5`3<IcWK0I3!|aSvHu#gJ8qC
z*%0HJomq}C)JXIMlT;ksrA?DQv|Nl6qn4vS=%$v0S}0jvBT`1&c&JI&K6)RW#+i*1
z{OU--2P0{QUu;nmW#}?wUR|LqL&zInkuw%Jf;j;bshVS)A0xY2bN2vCoE}B%hPT7m
zB&)W)Xb;pCdSfPC{H$&|nU3yY3;>qt4rJgdzs?F)$N!{vlcOY_;q6*5J}gB8r3oyJ
zWOA0>fKN`aH*OkE-I&J*Q0y>GbuBZ||J4@?Bk(8Q23`hu7&uE6w_4T-h5^3ZIoXVZ
zGOKKDyfQf8VNzlE==2HvtV5(u&gQ9vXyX+WlS(Bh(|+p&5F4LjpkG;YP!#!Gg^pXp
z_^MwQM=p&8m~btm$)~I(Ovags(2f#p&*#D{{^l_^#bt@@FyzTDfPIcLL<bpNN@X&j
zpz8q+A3}g9z~rDn+n@$4;3|PN&Di#nMydKKqTVlYFPtyyoDDg9!GlgoRDzPxIF=4}
zkHr{yfogn~yb&>Y7_fpVbt{I&nJDACX*-IPRBgFj3_S^mgL_m4Q=D?yy3~c}fAY&H
zTup&#`wx%9I>58dAF_~>%Ex)#-Q&>%GWiF1K5{-MezK4$ExVAzyU5_7%7iWC<i+i9
zteYN`#<$79bLYwAp?3CdkUWzd!S0EX>fT8|C4uaF!~X<I>m0|)?KC&Vo}&?3IQ<RN
znXT~9{<MiN546+#DefzCOx0T@vI%y%-zWZ;Qi01}kUyG#(_5@CbVn_gMC3KF2UwY?
zi1l6H0u?_Xo(78+VS-IheJoF28<P)WiyfT%D%o<M26>o>_n$gVJ3A8OzWajswBqDc
zm*_>cmE;G%nR-1_1sc5|_sw$=?xVEal;AM}%)d#A^3qkg|L_Vv=xCYl0eStExlH~B
zoAsGL+sj7`Ouibo64sw(J?Z>YnJn383;ndgKX*=$O)E?Qy^nN*5w2_=9<?1^in}%V
zIP$O#snl2tKN%F#`WY&`Ly4X`Gq7!}&oB!UT~qgDvgb^hw~dL#9i(KL%%3U~k%fOn
zB1c%Y`(=uC@V#h+Bth;nV`M!rjUwgGSHnY>Rm$W@vREGWa<Ji<;bBu!0V_c^Fh}{P
zGEi4HpfBT-e$?_tKIcxwzWI4ccFkRy-|~g)gN*(Im0wtR8syELrcf?yUkiVAmn6^s
zs3L)LDeH6V;q1ltdfD-#g<u~pv9Z%CEIx-&+<RoomJ}YjJrBoBfvln(=XmfyO&<Q?
zPo|;vCW@wT^G5Ujck_lL0ZUEJ8=c{s8UCxN$lp>5*`NC)Ja%5pBr1;2;BMsbw-q`U
z-fYSD-M`xO9GB2Bk3PTIwe%b4;7!}0^%T^R9gH`2KZx{rUrHwIi0>cWK+DfAzr~%t
zRHS*fm@d5n%C8JHWad#P&0)7F7x9AAG4xOTFmJS`4*ewyk(|ew*UC3tnsqlMU!XP3
zrWmHIa17r5ofYPL&zX_z?hvLvKQBV*1Zq>Zx{!0Z47m%oj%MkOU#!aP=PsiBw@Fy~
zZD}0*$d5COdb5P_oWaO{E(b#==4Y)hi$eb5e;ltjVZg1;OgPPxT^DRgL0g}w(t)o7
zZ0X&-Y)$udRJDI_6BKSGoRZcE2-U3|X>;{Y^V;0|klTf?86M0Pn#->(CwXi>p%rH<
z7OnLialXa;+{`*s<#jdn?%5EWx3?hfETh19C>GC`ftSy8jmeww{6&<kKxJ0mttCo2
zGR7`R+*^>@<b}kYm}Xzx<usYSVQ@6k+7Lj!iT2a%58z#<$#Y8wmjVw*5QqCvGRH}#
zJpB~E#-Oh>Z37JI>uhHv3pwwcE@-~!aGY#SN8EStl<LIBl}pEiyt09L8atUQuVu;d
zSwpfef!Lx@aUE2SNHA*0LFEp6;l2>{!5<fNqQ_8rs<WwXQ<4xXPJDl>45Gv>OI5}V
zGYc1$exQ|(*xoMUw%r;z@1zidjCz6^hK(DMOoYI-j7UR=J5I(E=y4k~V@f!vGbN~R
zbJ34-Be~Up4#KPNlN%%@dp>3Bhn?KGC>oJ0-)VAF86h`=GbKZtXE1cEZ1)^8>O_=>
z_>oTFhE{S7%`)N2pv_S;BG#sPd&w1sJ+E$Mp`9<hPYyIqnNATeP*rA)pS7T|1PC=K
zIf>4bUqTsVlVLX93vX&Z+TkVGQ_Kq4NTKYR`Bt{Kl-@p7bCAElPj9i9w4y!1l2TKK
z5Zi3kU{WZnoa2as^GXUe^=UNM5HQFFype%k2kHqwJAH*B=SST&XICg7Lb4$G_Q4o=
ztmB1;bRc89qj9Fjnww~&a!X{2bcq(X(<OwX86bJsFp=P4ye-b|6mO>cRJw@IKn<>l
zv>+C<7fd4h)0}$S067h^9*tnmVEt_^^EmH8QtJTE3b?9JT9!Oh3yz_ZqzY3A%`-xT
zbLya?CQU2hBnbl{@=DMWvL%>no#U%4Sna7Rgwn814apzZM5*&h^e<)M&0Xqh=`vp0
zU>JsLb1#*0nY$BovO5`4q6C_=?2eq1#X#K74_4f4uvoZ4vl7OjIkkX0^`w3S7u2C1
zgX3&K)1+gGD>zAt_$WkpTasynf@hP0h_ZuVPw>szHqIScjm5uXBbesEj*~zkL7b=V
zuoy?JmbawUu7IJ8F&%G_B`V4SWQ)yC_Jj=*;2@BS_;4eF^&3PDR}XVYX`ornw0AF;
zFTr21XmLw-g2Tsu^J149G8^Za7cra8#0AXM$(EU{1V$)~IaC<VCJ1i(cDpe~FJV#=
zQFB^!Bbbn#U>+tmgE)2NCM>NW-f|n&VI+o|FK?UX51K{93uyyQ@$-|+M%oB0U6i8b
zt5TB<kcQzP1^8V-%`ny*;3}GFi6J+IbR!(#YG$i%W-hst_XbMu9@p(OU%UH~hMBEy
z-$wVV0Sb4K!9$zyyha+Bt(ttVFT~U9=JT6Kg#9nFbnX(L7KiwOH1U31RsRbQ%@CRD
zktV?(mN`Qjz&d3io@TX#G+pN9JEk}W324|*sN4_pP1dHLc`ZwVUdn9w-wN=_kHaXX
zc)v`0=?(kk98R!#J}rb@vp3HjDBsFeV|j#u&o|Da^v;0(WQFoxnily6A=}TOv@lzf
ztyO{;m1DNDgfozAU_gaAbE8xn=jTq}%&f)>vw4#aSY?PL@>3EY9`<EpMzk)Ft1WM8
zG0>_XHCs)Ypkik0GRj?B!C1e7>_^>-VJE#bITpstoBF*x^Aq<8+YIUInB@KCWU2lv
z8gf2I<;-G}g&+30{%vP3)Q45ldB(reWJltL%I0}_42yDcyq109NnS8)UgLblpER|j
z0j+BjwE~)a>dYw#kMQk409oeVihJ)sBHv@a{qRVV)RHe#2;}XN#UIbJTj~BhsQJeS
zB>dVgnSO%NbN&~nC5uL_7i3saY5u~3-p3|~{I`DB`f~Odo*`Rmd?))$-$8&ypA<oV
zjN_kJXM60~+<kVWI&bz$=AWTI;*e6z)*ykdNbWy-$X)$_B*pvBm*m!uxqWwhxx%;0
zulC9NXOUS0Wvz{*v4icw*@VAmbC9Lygj0WyGh1glw}%aQXyCc*a{kdw*;n?UXNPgB
z{yHT%c%ks2im8ACdK2<xPtJ)h^$qWz`Sd{A+&QNCPj3u<G{CRER<dS`EjpO3I{B{?
zIkYob8m=|O=dUE`!?B2Zq`UMSqtF&Qxa9%y@k^A5fQWgckW}Yxm16raS~B2b;m?2l
zJ0v^Bw>`el2=W&{@QtM!LkrYE#x0@u-*vS8wC58-$OdwZLu}D33H|q!-_`(=;^J)B
zQ?rB*ikR8zcX^#FcZ=-!xqg}2{L_+Qwob)q7fRg@nPKX5$a!A-Y-L4h>-N_+$>Lx9
z(FIX4<`*tV*#EgzF8uE=@|{)P6EfBD%rK~DPuZ2r^oqR;v?e>@G}t@9HVp041+zv&
zC(g<5n%bcvl`l@DHQS;Vo@SgcDQyujj;*s5+x+T^WW_Jn^89i>K$9<^0nb(4Wwelm
znXRgypz+=`qvJAMpY^9@VI8$b5;+3eRyVQ1_p5!Vq61B@Dg)c^L)u6vx$!ODLXzfC
zpgWsn60e%>YW@j6iNZk#uBK60N7K}Zt$j2OC4Kn9GS!CsliQO#_Ga>HyC08`8<}a(
z^M-f0VfQp!44O59_(r3wz;?k0Jwkz;9^WvzkmpX4Ba&aH+zXpoTyZ`x{<VLIUG+R9
z@v9EFdO%T;O?i-a7z31Q{2doX?YaF?_~U|(e+&{BIG02yV@))@>6SG}L8ubi5cQ;$
zrh#qP-e%i(7!I=ZRMB8#@&(%bff@Xo7Sa_|RG71&0h~7Ko?kiLL#%+FaJ#3Y8?<8)
z{Gu@VGBv_blky|~VvRLzj9o-Dplv;2HyH5eWxKtUL97^qq@u%HhRO$OYX?XzDh#0^
zTf$e%5FN`I6D^LB{Q(3L$~>sOeU@lW2xv)QNUByyy&yFNFU@2WI@%4pYhW2M_amWn
zjn7d;W%@A%^9|mvYL_-=3*^w3Z6ColTJ)Cx7=xU!JzSdJS%j|8S=WGg7Gf^KDt<7_
z&mhXuvTC5EUw_u5Ycyu^RL=7j^5^_U>DkQP1Ljv?nYnifvcRyl0Nv<@BxIPsL0Wj6
zUR9)O>&I<)kOy$=i8O|cK+{sk7sW`8Klb59c1Kj9u^H1B5_JNDD9b$yMxYmPjFY#V
z`(bG5vDmh$GJ>rXg|_=xl;fXR@%QGJ&5*%1l;+r8_=Uu{dFEDUKrJD+Ir4~vkNr<4
z$j6u`<C5RlM(c8m8J&#?z7$!EY97qgn3zIz(uSGnVn*k<$p}+n9Y)P~u+PkpB(p-Z
z9qtV6grG@AW~|$?QFF)wu32xW@j|V$EJoHUv<znoFKk%qN$|F<mMkK8OU3g`ljbaC
zJSUIP&=j>`r&f5FhbZq^=(HgrH2RXMZNuPqg;0iO2Z>9|*#X~ngpP-pODzN4p=@ni
z3?mFi3RJAIq;Zbdn~&*mU{vEVM}@KrjZ^Gd;#O}TXfPtcj8AYScbL)H8w@v&BXl8{
zE|BaRu(}+ad6<YzjwLXukL*O6<zp<+d2>6@WeuV|ofu}FhFES+LKv~86Y^CG3|VHr
z6DP8F8U->A3&xw<5!sP!qJt9e4|8Qa5<3J-K7n*(*ILpVh3UNqrA#r#ILXC}wnJu@
z7?E{AOUD6j%`IGhznb&j1-lY^Lm@9z0)+ub4eral1?1bY4psW!zIYZ>@3(VM-Is>*
zr}ZjXP@R4V-lyStIQ=3Dux)P+Q{V5SX16|D(8~y<)&a`Vls=IMk}KFiQdn!yj`*xi
z(;%I=+Ipzd8a~dh=-qt<jb1n;D`Q@w+4^sB@a2Nge1oTSdO@zg+jzI|+FimR!CE|>
z6RafpYipH8=;}Y{JRbr>t2AMBW@qCqrY#O$z;P|U4b0YJkSKRj=hFqL#M6<!;+`1d
zV<U-weWOJlD)!EwBs;=G!*73sIBX|cn00_UQb_ksh`u4J#%h#kw$}SnzSgLDb87Eu
zz{wpH{A2%e3cC~r{pjS=)W*3zGTX8}Fw(l(%+@D1rdc#wA4mDV^3LJWdO@YN13<!J
z5?E~=m!&@(8q>#5P5Vc@NV7GB40-_={+nF>WJ8b#uufTRwMelYZ*HAaj#bHcHBqD(
z=R)Pt;cwFgd+O9?8pLQ0ZNiwodb{|7*Pp_dS!d~~O%0#BWV7@6-i%h_UF>@qvx=4;
z{LmgM7cZ)9`u%FKb+?gl=#vvNeO4+<FNm9~zm<CUQOR1*xMg0cLg#*-kHNWGCV&5)
zT&~s)^5=TGPtvO-eP7^xu+O6^*$>6<e7cgkyWW7{dV%dm`&z??tDh#zMc<rN`&Ec$
z>-HNkSwBPb`Qn+qGulGD`FD{TdC3M3h-*DFrF<xa^G03#y5rnKeZ$!VjP3go%ai~6
zC6XO_Wlxx@PD|2c4A?TW6=N?<SE+8_*`3N~{<rdg=T)Xo<Y>``FFmJWfxskM%jIgT
z6=3|P#pB<9gYzGxCG#)O1);>}vtOdUd&Cx{v2DzLEb6BuA^pyndg7$#jZPS`?qFYz
znLAbGnOmj4yTxd=cAA+;y7QZ3vf*~R#r~f+4XdD=5BBM#8=PS-iN^X&hR2aJwu^LD
zTiI$j<myjsl#~^9y<>LE{O#{K7h!5LG{@1fvx9#$y)e<>Q$AlgdmXa}R=r)n3!nb$
z8@;WzMnROB(IlKE{c<2#k_KAM8$HFbmHA|OzJh?bhRFNE?rE7ICzY8~(hz&RMn(PT
z1rWNGVf*(l${ss%27*XzGyjZL5L6puPt*C3SGFrbKQ}ayo-C!K{-aKgR1TZaV(-*h
zZ3SUc-aO`nH%&v`OqY*UQp-gmuhID0Ue>&jQodFS-m=Tgl5N9qAiM_zxjC-3HWANU
zD_uBG?L}>f-&iTTcRiCi_9J9MJ`^5uemF{(jRGKmMjJ^+qohui9hj}^c2*Kcq*0xN
zk!9;uJR_{_bAF0hgKVmSBv$6bc1xruBw1sC66COKOt=$(CGU*`Gt7E{(xe(rN(S51
z($wmQ<sxQU;SEqG2N<~HuqPWz@sCl4#X$#>$aJ$*qOiU-bcQU(r?h;jnraUvsHJPG
zzbc-3+VQr1^a)C|C^zFpP0sy<FdJ-;f!mC(?iUEl6eVEm%6*n)Vw!6BAgHsomL`K{
zJCj+=IURA7L^#OZpoJBXs#8xVI~g;5vy%rKMr#ktAP*UiH}*_aMj!R-36PkvgzQ)8
zH_na+Z<#mBW5<WQ>N!f*3a|~-k5p1>i`7{yP%ilr7qyC`Ov@MCy*Wvq=Mj4V0zVq8
zSzde%tMdvLaAF`qk|+Vqz@hCYZk3i5nq?1TqgKS?D!|WghlvZD_)jI?V%gWej0G%1
zXH#Q6VUsj1tJEo(PMI_xER!v;&y|cPSdM%LTO&WI^KFd^tNKn{Q;0d`j@HRuG947o
zFpFY--03C>(#TVqy0@4xjV&7sbq8n|LKXeOZ1w(FYzr&Q@=973uqrxxI2piRoQX~+
zaLgJftMOt|e#(jzC*uu586uDw6@RA{BoZ(oFyIK<BGgTak2#5+-7h}d1wu4J+l)d1
z5jyYSAxu(o4@^~pUQNZ6L!uTa)-fpP*6CS;{Rr14r=E3!&G+QsA0nCt5DrPvKhJ%c
zAAa8Y&ZZ?~X+z$!i^?d0*8WDb)mRPvJOzHB3@Iq)4sW+eRcbqpSdxlvSj2c$JmZ%2
z7J<FM6Lk@!(d_A(%Ghz}a44$$%s**cqvk#d7(2jpc}vELAEsc9n*}+m3V~mKK3lpt
zQq0pp+lfKG;_+2};=%A+8T!p};O#7;PRGr=E2J_{`xWC;OuThimTo)FWO%e~wvtz&
z8wb$UB@#ifRtCt7L57aRAPMGQ$?@q9g&!M%z@(E~7h_q)X(IB&n_;NORASU)3h>jw
zJ!SMrBiQRV`0+ExC|xuA485G`^akWX`gj1-pp*@6-Bb<@&`G?#CDs)p1+{t5^62V`
zW3UhKlwORsTu4IOs%4XN490N}YR@ZG@^WdmO`cB&WZy=)p*c}ywUud87qZ1`(ndIE
zN|K!e^gOpw*k8`%s&F>B(S*oXd#OIo`;oh`HuV0~4a`&*3F{7O!P+<HNjAg}Uo9K0
z2x<EC9vr8ngVLA$1xLDXyD9qr0HGGPz;mtF^uP7@%j^vPHkBSwjN*f7yNo09i7%OK
z{+xcAu+~g|S;`qjqT~{|T5caX?9#voDT``zOZHjkv2EnRAo7DC)tU3dfLsw)Bz`0^
zuC@{>**JYLToyw5>`aj<8|(DTx9>v!6~3lU#2I+~2ua8}>*$o2SkrKB5O=^M4_kl-
z+6}WlM6njaSFkvwRCj;AKdP7^bOnEeNow1$Ie548cBo4Loz>PXepGUdfb3M+9bT@8
zf9{=`9DYR-Z88%Qrsz8=n-g|~2i3<}xOljQ#B@q8>zZCW5VKXiC5yGpN9HOv7Ov1C
z<P$$YxhrR9dgcu@X)m2BGnK&H^I?&Nr9K~b>rVWW<G9~JAD((Hy?n;~_<Zx%u%i>=
z^#C_;aC3O)BR`O-IeNd!;8<gU7zGB59L#m|rk9*Nf~i*vQeoVGb=DgGq0DOYCuCsZ
z5152{il%z*)Oj;$lBRw3?hBmlxb;Qn9^%6p`T!r=SYd1-Rc10rw@LBjpHe(5k*=#8
zeC4m1Lik4V<U!70WW#{<b!EiTZ0+L=KUP~`|D*MhlV@HzZ+O1F+Pcjb&Q%jPaR1r#
zVk^QYH~L0&|FXCi-|$HO;na|2yD0^IZ7MrkWAYGYs~q|>N1X${bB#9M_7~RntOJ&w
zyGQkM)Wgn_nf&4@f@tIKA=*QI>C$<5@?%UMWt0_VDA~Ia*bu4x{<%XtsJNp4cm|Uu
zZx(I6m+{hDFIk7|;QTxkDSJOhj1*JI2(#5gs!9FufA^b7-d=5$TJ!Eb;>S*9?C>$h
z8_H)BS#6c!mq@ngV*}6|8B!i`nxgb!`R#l2x9+aUz_+fYTz)$*=9ABG=+A}8^kc8w
zkfp!!Mfz{cL3g;tZ9QAU=3OGYR?5{@O16Y>S~4sL)K4f)f?Q9XTMg=<9Cs(9QoL81
z^2IxFF}oRTlQ0qrr%bdMoiyE6a<O~~a(w&L{OI>tb`3uqmg;j<tE3@ntF7U1b;{%{
z)!mmSHTe|fFkp{efMnz8C#U4ETd)qL!7ALGh_@(vTZ0h)HYb0t{P<!nx1H6dgSA}c
z+oO{&u{amKUUuP~>^~V)&h{F4#J*M76SB9ZMI~IgG!RCS^%IkAvz7E0YTJe+jR!v;
zF)|!0oa(laD}_Jz+{9witmy*Q@}#Y{hQfx>A7+TNv?0+zN1%_7GqZR{I$Hd8lBSwd
zA8z5zho6)cSwttik?aO&w_8paFteP-$}OB63sJt-T?2XZ*sv2kMHSa{$!ZGVLcAuk
z-1H!-(UxG{4#BY3LKp{&PiQTMR1Jq(gmuPXg9mW4=@y-eZ^tsf69dWmw%JOSmqMh}
z)&(966q5N8$-1%-%hk*HFtb2-Ruj9ylLOUOy(jFkD-2|gSv?hocjVA!IhaF?G4jAI
zjZQon#!6~F^d`X^@mzDCFft?m9i3Iw9yDSl7u)EH<FFRT+a&Ty9A0#q$XO=??XVNv
z6cr#%Nca&mJMK6hr(LW<A1``*;7Oh_m6%LGV&oGpybQpI)!8skhEN|!K{rSW$-Ra{
zbwZNC`gG4<JJDu4q)3d#?(pzxUNP-y4H0lVLZEt>*@{{%;T1|+3jS#M)|!?|3kM4a
z34c9E-rI#=4+w2m?dz60)pX<sq6VQ{f6Sdn2wtR+sX9C`XvTxGpQM=*Sc!I(+DwD-
zJ&yLlSQOkrW0XBQL)`X;0;8d?#w;%6W~}^s!UPzfgV-o$t8mw2V-%g%$gHe&fUd#u
z!5*fg55gvmluDJ6sT#x>CtJ~aG8Zv|X>KrW2Ew=pW5x>HE0?a&kVnR#MG`KQ+Em!w
ztXwG*sppQ0xr4Sr9_6$N>N1l|IFt#KTDkO#%u=gbV2+t6dIBFe3kfMH!_;X0mNC3#
zO5{n#Yvp(vS_7jp{hj$TJnBuEElVx5eV5=YC=W|DFg(g|IT5GeYD>b{Q7W*>?1kdl
z8yFSNFh7-Fjxsz1t>Zw`<2-sl=9LZ(w5OWVQH&ihi15kD66s|#Wi?GL0S%U;1yS50
z-n;@i3dE2?xpaqIYFMi1jD4SD{t(C(Q7O=-Ii}GTT97R`C3ul}?z1-aVd)r*#_0j#
z^6FLTv%V|HjIY48R4ijWk~auhZMAuvRq(4W9HIS_0td(w7T@e=rl#QAO9%lE<p;AN
z&P4Fgm}5*l2$MZPtqQ7}P36`wUE+>5;~na91jSA_%T92FFOg{s=yr)1JLs>0a{Rix
z66o!W>83RHXn$bgDKtC<+s7NiA1Vt_!o`948Imln3sNmA`|7RXDKfA(#2io^x&mU@
zB`@75LyLpy()8Wn-cM}<{KIr!*a%s6>w<(`We$_#4J>2+z`C@}ok8|%b6fTd5;iO(
zMMWNFhP*deuEKSEI_)Xs&tBj;i-N3@FD107r^&-??n?+jgP|$%DbSuu<szJ;?g~ul
zl`+D>*CGV!6mSj=2q;%IPV*vHxP0)#jMeLZOcf0f2GZbCb)`FcobZB@&J?%ns5_8^
zYO@wHdA&96FwB+jDTYEG_F_6WaiABib^`Tx-I!WzBa#*0yEJdis*R8q{IeCA8~Y@_
z7?#aLKPK7y*=eyfFYLBvOd1X((%iFyEU(b}{3E(CGH!ai4p3t6TdodIeEl5nv%k7o
z!m~&NsJ*$KpMQj*?&r^8mTs50=@Djsf9z*P^H(G-hABKa3%eKL_x4NjFuGGFr&n$e
zzppc1?v?t6cg+Y3kz;13D6~A}!VXGq`aKIv!~c0)9>xM)m|b~`)aI`m%Rx<5z*%@>
zV9zU-he>Ml*Fqd)*_LCYmKM7hh%da+=ew_++OL&KSsD#D($1WdWG~VHCZ-JCU{{ct
zk7Gy=|6WLK;cqDYQ$zQ5u{UW^U|`=_2^+zu%-J23;Cy+27oAODZ}NIRWrpi6_(<|+
zll1UXUpjoxRT8dz)`fi-sk`n=s`>0=d&F%au1*bx^4(SzLS_CP?B7}`Ss?J_poxTS
zE28R91~Xe9YuFMHX*R+l#$m3@eX<WN@xDq^{kaX~jnLWq#zDbx^^<8_AWjypcZ;^7
z&d5e?GJ$smXw+@~<C5JH7ge`TzlZ*hF6R*0wt(4pFic#*C%$Xz29ua<^f9xQyov5v
zKt5Q@o}_ecU`F~sf@Nsw8fQ74-+OR-I*4VP+}*6IzkQ?Z?_FCLWaw?DrYUx_#^jPW
zmHRr4F6(|JG)|KXm_O_d)>`^WF58EK(`($YMQM)>Q+-J#J=Euu;w;uDUYsj3j8tig
zZzaoTcn@Y%9`8#En+}QRm+l{KJnZZ2DecvlG!_|9*G1`0h-!V$ZP^pJsPHKEwc=&&
zK8Btv*#)uvTA?(7$JvF{iY^Wq2)tzKW#uQ*(ar|rUWt|igMv;bTvxPM)6A3IY%Mlm
zpl40F(3G<ZY(97L(_wE;`ZnJ2ZPtWW8Yxkk@F~_Z<p+Fk1EW0KS-cipf~ijzu|p2-
zT^y)aH1%tPPvkyD8^ep+Nc<cW$rvc^T~&o9%?Tl8imemHKCxdAx)zwW&YtL<kubST
zb`yZtl1|VlM;t>i>{Xyuq8Bc8Rs9X%r|B^WtC(vXwo^&R6d$FH;!w2MAS!K)HE#JL
zX`o#7m=dFj((<DShN68D;Ebr2OrBg^j-+{B52R!ReV>)Y@=IU9#bc#}ip-D?@zm%s
z{7Q&Dxta*zGM~YbRfSfPP#(;{n@P}ya#tqzNRtBhDUBa-v^fiR!9uzNpIOB&ufvHv
z#^iu<pmA1eT#To7^>$e|cuFLSjSMjujFr`OG(YK=4b7WP*ojJ$h5ISXQedjh?i|W5
zX;`M+*y|YmaVWh7`bBXuu-nB&rg_=N&QRGVsYWZNDIrFpNQZDi3Gl`sSW%L8HwYY`
zj!rXS;Vn_16|cQ6wjd?W>rARfIT)*{wWt=L&L=~WTuR9KAec<V-sPU=j!haS8Cp)L
z%m&4SkKCqy-UY&~5aB9taho8j$V{l<Y#||DPZ)`kX9p2ut&F%0iGBBp;&mi&qOgu%
zOtHn2S|&U7(DBsq!Bx&#1*;VyvB#7?$BdIQZ)G|f<6G#AUAn`l<gX+D9i%*~gy^m#
z9AEl+*2*&5m5G1>wPH(goX!tER?q)*v=%1Q$QZ6JpoGy&mjsR08hJ-22sVL8LeNaD
zLz)LWfwcFqU`beJbr%<EX=bXpVl{b*NT5ucQ&A9>LO=n6MQBE6w~NhbnCi?6r)@)v
z$qp>MGDe$8zi7`*QkP9-z`Cv;rL+t%c5pUBX#8Z8_B>;kx?QX!2KXEZY8#)*k|B~M
z-MSUCb=KUKcHqfx4P&v<5$ioXa58FyX|W(<ehTTNW72dGH@+;5RcM>7HDQBT+cWaM
ziqORoTqkhVQLc*Oo%vP284Q|Wm`#3x-y%Qd$K)w5gD3Ksczfb`?mVu+oQ5&M1dhkW
zp<s0rq$|aW>*U~t3Z72V)2Sg%&}J6qFi0_=<mHQGo4X<~2wG(@2A=qmz)b+LH2~d)
z!o{Y3@k0^WJ^fnB_Jd@ifnI6?cOT+32P?F|+G;dg<&hxr%t)4hKOy`1oTMwUsz(AR
zzi>3JsX3#i)P<k-Uf5EeAQ7=OX~6kg!Z!I9?Su6OVFT9q4~E4zx4;k|3CrYlm}0g-
z5I7UQs4zcneOWK?HmmX;l08CFSf?GZYH4aaQhSuj%mGZEx3AK-@#T%r%8@`xF;H}D
z67DEY(4w|*`u8@loWy8pUU|)<SzEF-Zcru|70hP$CwH>wBGc?Moz!`2jJraMebI++
z_aoH<Nx?4V#SgmIA64U_@2V6pe=<#N*(k1+cBMsNfahj|yx6xa26tt?APc5yNY{@Q
z&il$nmySLy{>fHN*<+e!Sgi7Jvk!g1Y?a!z9O(Zdn)dij&4rO&?B27t7JES$pYm5R
z@0?aP`ZW7Llttb>o=D0550I|?|97w9HO03jlfk;Yw_j75tqb+OJWcr;!_Gyz=G$3`
zo7|}(tlUfQ9QTES+YQK+tym5Wz0{v;@fNAzVKBoFouz*LH{`(qOeyc$;xoeGX)obZ
z+{+l~&5^U%JZGD~Zts95fu+<$hLxhl)QksVHGP$D?6J;`t=TGg^*XtCN5`@tfs?_0
z7`P!%CC6;Nr;fs<e`;+5fD(=d3Tk_wb1z;`JNiwx6a#u)&U)TBhb=OhT>cG*#svy6
z$v3^oE5n$r`|i2QPuHI%0XBjsi;42hw1ln%b5Ss4&1|iQAN&V0Nh9{i&e32kPY-Bi
zpV=vIofGyZFFY>Wn=GP3%?@>v#&b2}C(h%IdcL!6A=%{DhbEe=kJwOaB>zzoFxtcE
zEXbA{!BMOpDYk=cwe{lN$Z4g*iG`b|2Wfoj9G>McFZI5^ulQS6Dt;`Qt+&4k)%tmn
z=GPGpW@}0rhnNi2Ca=G9Ds@oPGs9F=j62Yn<h1WferPGp5AHwU{Q1w__~c_>*|>O2
z_i;it^E69;dQdh_-X)9S_sHVGQH(xH#FDG)SjzO5=e3C>)eA%Ggd~phRQV;B46c|^
zkzVq@BE&>1;dS22b9)7|Rci&`Ag#Q}s!Hp0Khi9~ShNoB!$e@<P%*Prx1;MkyJ8Ug
z21i#YGMbeKK$+w8!CjXu=7GI5k%N(>DxdZ;I5Hx!<x*D;5p$obs7^(Vnb7O=p}4Pk
z<rB%)j@fEssoqdj<Z!r-Hv0(tZhx)Nodv1hBT1d|MP|#<YQ${S<V)i+5@!OI_b$^i
zLi<|I&g6C%?f;nEmNXpHMw&Z#-Ii|5(a?>^6@*v%r>$4>Y{*g9>=SF`yMsyWu?^#S
zajtjOcP7b2&3jo#6Ux^hP`-$FSVn!zp4SWTns`HAq6MuEMgg-)EW*SB-pEuO-l-X=
z2J<|tEkfR!28R9kB;%I$I>E>B$0R!oiNFGp)3Q#+=-TMy=P0#i=^RQerwoJxH`}pU
zH-F=9-4M+VOV$SVyiiaM^O+FOrknVpp4MK)b37K30Y*PO*a0h;c$Nl2P!Z3cB=hFc
zj7}W9Fkpe9Ri*8{7!L#%l!o=yxv_Z1z-X!&y|O9o{Uj4&BC8mUV50TZT_uHekh7RB
zuop~xj9N)FDTOpq5+dh5SaJz}xus`dsRVNvELuK^=S@~kemwR7(i#V4ncw_4_<^72
zfo;Y{Byv6*9Y-&9#v<@)9=;N6%}(W@<uyHu)7xc&n{?hI#bkm6V`R%2{HRc%3lN-0
zOPXn%lSKK9LrI&7XA!>CBA;6AJs*yRBL;5dYAE6p`lL}D%5S^|Z(eFq6?yIgjI<bO
zr0VM9laS1(`59>gJNV1k1_le7<fLRSdYtsqf-Q<R@;6D73WTzcheL@&VsaN(Tfqsr
z&8Vvd88k?GA?6_oQ{FPlfV3Vgs4L_H9SSAd2sZ?VJlg()2&4@y?z|8roOfn^rmkui
zl2$xiY`jNh4zG29$x0=}t5NAdW&wxz6zz26z=9BFn6}ob<SDIc2RTN>H!*1!=37(r
z+8ol#FND+t4^v{&<S-Rk%}c~M(ZyRH-NJk<3<=^zwSz}}C&2=g2wvNco;RH~6wFo+
zHyu!pi_YvBhqRa{;HxZ>G$}`W!&5!J5fnW(nZQgmTXT89o_fG7l#9J{ZLsk07>Se$
z*)d<$0uU+Vg-NdbQuB#2#`|hlqBE`_%j<_~8<qV4o-=zRkhf->WkXX?T>RPr>d@+_
zHHPQtI2o<+^L)W53aZUR^zqhMA3h5T+^68S7Nru1*!~a{F;5C~eav3fEjcr<n6tF5
zwGCQX_7HR!P;~7Z7%;B~!cf@Ix^%H$p7sU!0k*axtKb@au=tdhie+<&^$pC{5LGY?
zdIY|S_5VL+e@B*%Px6sSx}P~o?{Vs&&<nEc9xIPQ3T&HGWZ_YbOqRXIn7eDiW+)}@
z>j^e9^aJFpXS8$lvdtXwZAM0_%2-Eh5hcd#b$O4d4F#*=s?a&VI2*5Ie`yw|t+r<R
zt2l}qm~8kIv-pc+a!Rw7W&TacRAr@FW=+Elx8@A7*wB`?k|T+n*0?GgBie-g0v&4p
z;gDz;o8^t&sju1lU~R5X&YF6eKm1?AetACe)vGJaRE;weYk-h;=&&p#SLVt73mI3*
zdFIy}nvII+UtWq(@0R=q!$(}kh<|pBfiAfneL82g^`dM5vsIT8wyv?_%rQz7_nzzK
zB)_*msQiQ^Ba@h|*F*wFrW;HTU3L}WmEUNE(T|SJAJTcl&PT2!SseN|Fc9~4QahTz
z^?OW`yh0CGlvWt8M($w{%}&nIoodH9W!dL$vuNvp<lHoW$BK$R)RzoCKV}M;9{RLx
z3I0tED*Dp6U$R8(WaDJ|nlayakyG5TBl9PJ3C^(S5|gQ&nmYYRC6BAE!!NOOn$^~Q
zupC--m;J}DEHWc;vzs>?D!u78-nr_{SjhKa<m6wQp3&bxe`k2r6V61re)|;&Z)fYW
zt?fSZO6(^sv^%Vtt@{tq%P+z<{8@JM7p1Af@Vs^zdyJlSObcP8&N?6NSR~vs$!crE
z%vLP|qvCx(mF1)F3o7eSClF;uhpIAo>zi`#H%=9#sQ>eO`R3z_jO#tl%N?5%&fgBa
zDSb-W^#?cJo|k>arLl|$FAF6fe{~1ZdxOeXKf&7U-I+|WJnSlGi6@f(BiAwm+%^d>
zT3JMsJmpQ^xPXlz8_aCY>nm<dPeHRsRu=y+;@&>avZ}oEefB=PPVcHNV0U!^)d;w%
zDB43y<j|lZ7+qCeN<msZIN<a(XigKs)@afi%_WI1tEvkqkeGsy3`xwr2Q;~z9<S3n
z{Nbo`vw6$yIK)ruU@n>K%+$^0`eC?9K7A7%4KdFB{?<OHx*EF9sm%N_Pu1Cby*%q#
z&wAGDv)*=o)jN}s@P}t*hGrWMJaWG|WKz8SkH^wu`?F%6*^Bg`#=<jiNk2zJGzjvQ
zpE!drnf+2&^p9Dvw_lJDsA}X_wT1kMM?4g`@@JL?k&6COTNmR*US}kX_|~?QM;>Ua
zP%K@#`fhfAp|)15ts(fH+S+2Z6(U#hbI$CMn!D*yI=h)jxbMRi<>*3@@I_IxxB5$K
zcO?=1d)JaAH|&#Xn)2I8O-SfwRuLHR2xI>WEnG7>ovq4zjDGNT^7=ECN5t#%;0^?}
zZD*&B<zc?_c&^5L7OqKA_qR`Jld!AQ*4yPgGFdHPpJ3e4uA@d>O}7A3Q%E8n5=p{H
zaV46qOQ;cIawYnuTWPDA^*~+ZEc<z3Dd05#l0sJwAO8oUy`S4>ThoxJz`>I#dAie<
z#!KU;&4Bk{jdY6!#&oSbWZ1GXm6<@nb#df^MdOPZz4-}TfQ870Qwu@=J{UBtstRL#
z1;z@hiFw{JUx`RGe3gW1WdUxcX#Hp~ENBW!8FbX~$N~?~Z!?gaBOMf$RO8s7BmyKU
z3ruds(UOnp)dRKF-bn;8sliIM!F9?&p<`Dm+$|B-{64yqAOmvnE~SIkunP_BA(rRo
z+}dYEg}edGkkUD0u+sH!^$f7<rmd2L!?VqAGm!WydpyXcm1&YuTQF;u1eozK$Zb)<
zYsoW`Plg!X$q&x6ELgCm1mqF;QchLlYI*koAub^W{)?%kZjv!D&(BZEbv=w!v8_3=
zN?WO3M3$!BxUpfajIAM^*1$+NlSiQ5`HRR^Y~xhGNrcKOF^c(6K-a1AvCfnt>B@pN
z;7iG;vREFdmHy6pa5<~|$qL1hk>BiLynuFo=@_$0rOePRoH&b8lgozSZKruEqN^}G
zp?ZNT!Gy{~BHt8rx>%lfN@28ICNU!z;#fk;XcZwaT!1D@j&^`9!?U*)kWf-u;$X`2
zh?shB5<=LY@KLt0?l7RK0xK8|A@EWX^!CI^ouL}=5_rx-RHiJI+soE`D%TC4qUa$S
zLkTO!+&&o<qdsC%f+lQhB|~E3mWYgk(2eB)rlDG>E&wdCh)4&Ns8DxCZN{~YJsUW)
z!s*Hdk?RYSD=?OTR!M!oTbFw<<nReS0t1OfM5b$;3`^9{k~~r=X;ul?H$N*GbOi|E
zkSr+X5o;@iIW_aH=Zyo!(<U0<oR()lm{+-<k2^3(hbIQ-D|{NqE;xx1AXO2@r3Uum
zn$Wa|xTvNr8Yj^z<c*#p<|P+snciKPjqi01(H_<!Z-L#$O{F3Rbd9b#QtPqxbj7T<
zTfr)YDxaRO>>Glka7-K9?qE=AtEMZv@D%Tsq``Fa=%!X%74X<yJboR)Jng7$(oVCP
z1x=fy_|*LypiZLH@6moOS0!_8wKaUK*dAz!8!P`3l&!WHuPKDiKtR8x7rve;sT)|A
z{PLR(`a|}2&L^u2#@B89xThbL+M3uuqvJbV_iW?bCb|dAej<yTgp*RMtruD5@5gsA
zgj6&4brelTmFXQ6ibVxFY}B(IUZW+Swd<T;F1K38|9j>N<;`i=hFf)y!eX>ra{Eje
z3u(6_Lh25zA^QSsa#_eou`lm<zfhw5hAI1d1|?N6(b^D3?dA4R@(g#mptf3=8rt1M
zExwy(@dG$Z|H{YJ)^2(4`JevXd}b(-4j52dt^L3&b6TJDkt^Z#*^A0Bc^PY(6hi+H
z8GRlr5vZ-K(Dqha550?W_4JH|zpiKY$j|1x-#{;Cn@EMd9{n~XH2CxXIWMpOO6tTN
zedJi<1Zwm(7uobY?Y(DMl-zkuu*?5)+4nXH2Uc6HvHw*rzu*>|l|qtlS39u@C?4Z7
z!s3VIV#yGGbY~pref@g+9uydlN4eZQcivyWx`$#u!O0|;j7zEKd`^u6=%md_p}ysL
zZV^Bh+9bSqC+~deRe7T0ui^1LKQrgTOL1m*T`<1ZOZH*VC-v86qX&O5mV{q`>gS~W
zcR`zk+y8}nx3xtt`0Yv8^XU6-R-1%FTHj@}3c@e>$}olQhqbKQ#(N~?{3os6qhH7x
zXsoF}`q_xaemfM|<>!W+|NHl{l6`K*YHJ*gK&C&Sw&p&(2R&b#gxz<mk}z@;O~cb8
zR^CBJ{_Lo=-4W>j+6OHxfAVZUBQZ&mD?c9bi@dWZK3Tj;E2H6c+xth?^9@56x~PlJ
zeDP(RCA%=lV|tF*#lVAa-xio;p?aObdT7K~(|@?=<S~bRhqtLXJbb3>q(W)L+JMyO
z;cVpkvnSbcJ@1x5nbm^q)J;Qf=>OsNV?{Cu77p>bs>Ytgm5+n^FojPcg8sBg_>*d<
z&UbMGhCBvC1C$%ppy<dakef@d`Ya?<XXGm`RGHWicc>F>Uv%tn4VMTQ3T{Txa+W=E
zk!Q7aW>fd^p|)~=>wQCTOFQd7dR~;Py@_adIV8P<!=pQ$`P;T891>yt$~;A-QSuJg
z_>7ljt8azd+c145i4Jn?4~My|U5chQ>~uE?2lj+kp;tISpzY2{T*3YF)|rYHE^#J+
zUDOT*KUni)jM#6-wXB6jNj*J*#W{0fSK@L|GDaz>-IRGd%5C*?_zr@!eXg_eCO>4l
zvIOOWY^9N`f~hQXZJ*r!k>KDf#MH5gMPa*gT7qPxrbiYpY5+AVBD|{a)Xas{_Q*D=
z_^qwS0Py$+80Yf}%@s1%eJchCxK*XQl-*OPVp&fpYHE*zTnQN+1GBFlTau%XL>KuD
z0utvvk6KJ1#S$_^1GLQ?tO!DU#&pZHnBo$2fsVWqT9F|wHd8`8)Fdz70Mrt6pb_?&
z#u;t7O~+axQ$HX(Gk0D$wGol_KeEM8nragcxk|n2N8}Vgm&)qrEl}QoXsse>R-^;2
zUV5942~8Nd;u3RS$k8!0u=_UF&?SIzL-68Q<2~V~$JXKD;ncg!!_&lToIX863jG9Q
z_8`o6)MB4&3}T!Y;x_o)6tp?N6auJTu}o|9Piv7vn|E1b2dicHQB0JkMP*YZ2+!NW
z3j#=Vk8Hf7F2^MtQrRLU6bdfdBfwEI2R@m?qHQBk_7JbZ;3`?HWT5KmIDaz8EJpD|
zfkLC+O!>W}8@S^!Xdku@(IrG}!bS7iBZ;PzClPSUSSBa8=;13?U@OS2FI)nf8JJF3
z$faBP(;&NK>huy>CBn<1J^tkINQnbVn6JVv@)AlA${^5a4}}-e1oFjO6&<lDB^sPj
zVJw+YmPDG;jcJ~>RXHiOjWDz2-ZYT2Mu$KR0tu=mZ%tU7CiR=-%n`W7FGg+>ZUiqe
zj5voMtwSo#20?j_X3wgHL|0pk6-Z$!_IOUirDNP~!!!iPD7{|ZyY*0P^ZYzx;K;;E
zLbPfo2Pb0;MEDyIP`9Z#=>esfD8g5*jgvu<G>kbB(pn#J>Rmz_QmPniyAHlJ%_|>M
z2R#rzz#s>Hz4ls>iN(=mDTYy<gd49&@L-P$ZG+`7=jA^V`0A!<ViErghYmm6;ZO|&
zh+=VfhjAR+(8XDtiE;`$grz|O2ZM{8RkTDxIoN}eB5Z254)P1)bs&@xv0$FZY*iBr
zqUJ>b@znxjujqmE78tw=uTmJSb?73HILDvhGSZEfRMk`>2Ei%_LS!!=(E{DxO<{xV
z5}uPmk+8O{nXXuN$ky>gLAN#V=Nwr|*x0eQK^OpJy=eKgBTYqV7<()Rak}wngh&FB
zgj;B6$@+cf+a7OFZxOBv>>6hk!%&mV#o4S-#Jo6j74wOrllMR%*M#W#gO*0YVPKek
z2*~8W1Ni^CXxB1Z!7DLfNH?7T1TWb~5Uusl^$27N0L}Ogm=jD@WJIgTgj({mI=?2r
zAb!+bwE3CpQ|zi`>7mHn2dYhM4vbT2^$D_RuOLjetDaK8lm;)Cz^_Ux?<HB3NEiLQ
z65dVmq7BY7AEgly*K(&;MXUG%zZjL1LEw;XG(=<9#H;i@^C?XC98dFhxCOD=jW}S8
zam9!|7O&XWK-D_>%O&U`kmE}s;Ix(=dC%(M^w=!WkHw_ADm`A|oEm5JcxW?dt+<za
zAE<eA39+YQ-8U5q!lK=kZ<3Go$W>T9_bQF4Ff*g|B78<W<sl=-{!jyP0Tjvw5e3nT
zfin6nr}(S(%ZnU@@pd>_)MQe}SrV{E7^Z0cCa9ULhOX8hnxupc2sYs$SZPI0AtHr2
z)=D4LI9DTy;HYPFcsV?y3(CBhsicb<E%z$g!edlz6^avzm@iyp9zLTah0zC^(XT7o
zUhizliljq48VK-S^Y25c=cP77Oa)kC*q3$PLu4F6>$?<sGL^?uYX)xIKDagU)>!u4
z?CBEO`1N=<wIgVG+W8h?JT_iTO*X4iuVm035Z^RhHWhKe<ybv*4mu1WX~!|EYtww3
z$`rmEf<ztZ@}%kHCYz{!V)IqJ(!8wA_&CzkBk;3IG|q>_7pU4p`8-t6VP_-TkAhKA
zwoh9#fp;~_tVGQ9oJC_J@O$wgrh*k8mV7J(>@mV>x(O?JySy#(h}R%!TYIsKL$+4@
z%dQ;`N}V#Y6`<xYXk+QYu!M;?7;p^H49XC(x^H+<n1SG<vbS2;KJ`Xu4}ukbUcyON
zMWlm`IC4g&79bq++2oH!Jy^ApiFp4}&?yc>P*GL{&0G~ega+Gq(ngnBCLTW6we()Y
zUJ)~t^K0ou0hpY{KlE_IIzf_GVt4>}ln%ba)8x&dE+Gc>$`K9|oHGd8K4)oM$mx3Y
zeI2~aX`>=RCA$kGy|&$ty-^Qlzs&97$Myv0-yMQIjV8q1Dw$pG@MrGX+FL0<>=d()
z68QP;PWQ1YYX(9S#PhgvrOcjZyTRdIiC2(^xp_<n*~=ZF7@3w(0slATK*^bi;vl^J
z7jt}DBRybW!|OX|kYtve((4vmm^KMVw%lW_cR91UOv52Q$Vu+rK2+F$pn4V`o%7Yq
z-;G@rk;%bC)0Sy_r-2Sv>8I?5&ON@B-cFgLa3AJwJW$4>@_LDLkiJm~x(uE^Hq}iA
zn0+9zCqISwuV)&P);xVud{v+uKDh~mB7cNBe4}FA1eC7MF*UNa*}6ErWAd_W2{u~S
zQQ`lT(06`~eOb>8Ep#Te73-Jiv8kp*du{|>v)q>)H20ox5yx%Wo>;8%ZMvrk<OWBZ
zmLR6zn*^CdO|}44;OH|ozhrz*^XGrVS{)Uw8<6wf4@|n7_0f$zH+thM_da|Nl<W<3
zW&c2XvhX(U1)Z*D6C#y<52_Bk?zR&5`FX4Pgaz#3XXz@r)WgmFXHv08+e-Jp%3J<t
zOB7dtr5)CMhIIi+o{S$%lY<krsqoER%wT@Z4$LqwW1sy^HrM{J+t_5Q&MrQZ1WCy6
z_{&)NM5iBk`^>NKHI3!8QU5UWJpXRphcn`;16N!&zVpe#wSP<=ZwB~KCrd9k@yVy-
zY+i1#^_KacW6Xt@cP2^p_<2;oC(NE$;b7a1AIiqu2wPtsJ@YYJD!2HwevQ?xEXkM0
z&kVMs#Y*Ts_pxv>Fy3%|`+<k}C~J*r{2f_%`jV_om~7vk#A`9DIQPxLuUz4{1A0EU
zJEtsnKi+1Y$$My^K1TI@;cev0%bA)$lDg}r_^x`UO@IzFI<5Gmh<xbYPpBO|zU=C`
zzU~-393Iu8UG`PRb0?A&oBSgVko=-G9zDjV7V6uWLnYes>2s$jS`-pKl^wqMHd}tn
z$CGsaa%y<m$^(maRIT$fF7mCunl^~JrM({voewV~$}?)-{_3dp8lUO7q;PoAZ1rD+
zJbdyMDw&&rXNQ>Dzr$G4;NGtXSYI;VIWg*UyBZeT7r@@%-(ktIEh*XU?NCy)vCf&q
zy2>GEe<8DJt3=X1WK%ZJIP!{3#0W|&y@EpCdQIUMzJzS4K3k|cWs(FncNecPb-()C
z;DJ;;_kX%P`M6`tOPy(SRi?itX<>_XlGkHl-8wy3&m6{q;A4kzo1&^&$#l>pL6U-o
ztsF%Hw^3~HK!T)=`8pj549UZ3zCuHcfa(oelvMZ797yQ%b5Uc{PDsNTvbxcYr3>}3
zpJ0sCkQ_88+77>NZ|~($KlY|O%-p6Ar%$KzslCl_$=hq#p_h?um@>cS-q%1XU{qu3
z5HifO&F**vH>Z$$_?^u}QsT^}<`X6i&%lKs3e|MXsl^dJVcXMlIJM)%D272GS`k(l
zFp3xvx&nTb4Ci?Sex}<v0F5K&j96?I-$fm4krLN|TQ<x^bfFCdjfax7iokUR7KcWj
z@p!VJ@L(uY9Q*|t=ea80%b-16Fe?is0VveU@Qpc}o}D!p2y`f56T==}vnLwnQgVDC
zbcWgVHV4|p6{>$p2nRF#Dvn;_`w|DbO!b!`q0qCqHByqvJ$XA?;A$I|CL5$0ieXL5
zYF3yYNq?zLIa5l3dlhmMsffrvK6y|FlVga{kR-I7Yvbtot?(nRmDo<;#UWuz)2I{&
zCodI1aa78<8Sp|%`8nu9-T9>A*F&eIY2f9hl}y@Wnvp~y#|?<w*@DNISuJQRyj<{-
zl*0<Ea3tNOj_`TS=n+!S-QQK-7h~QA!x(hNvk<dxB}nn@g15GhMubnn6Nj4t_>TVp
z-k~~~hRkP5hd71=j^-T2Qx7@Y=&*UuyJk)WSR-hP!wfE+z$0}8?+av{Lz-|N_m`zR
z82jM>bXmSq!mGfW$KX@f2ES5gqQexfzma%ds*av(a|0s<Kk7&^4IM1Sn^*}W>BJe_
zB#ErmeB!YA1u1sy9E_=Tu<5}nN^qStyBw^0DO$|~N&suj{9@56f(k|x?f+;J-BNc8
z?;EC~rSBumT2@R@b!du5I$x)2s|nvl_VR$y(>{2S?MVjX#^C53@b$5H$OQA-NC~M8
zA|OIk6M10tWF4<itw7^wtb$i}(jkvr=gT^|f((G{%|uHqK8%|q%AjTurn}h+g*LHR
zM-4o{kS20c9FR>gu7{$OkCP=L%FqWKejWJ_RWTF}b4IG75<&wM=S^F}5K~@n^*BV7
zMfxZR4%<8{u70wUT9u7L%eV(_R$LK!F_0Pr8uDcX=P(Zhm)V@3?DZuS;GE8_N?}^}
zDI<y^1cywvC@Tg-)15VX#=<Um^+R^ibJsg+XL{%TB()))|IVe^J`KKTr_<Gu_~qGg
zE&W$#9)1A-L8*Q<{p-}7i`8dDq6GRz&6i;q#<P7f*!w{Y4dsq4sqX^rD0eK-UC}Ev
z5tILqMK<wVR9lxqB+Y0^x4odY4$*0h`j#Q?%|aRP5{THJpNa9gS+AS$TGkwcjd#n7
z(Xf3q@?xdE8`oWIVIf*`DztZ=Rhu;JYP%`P($Vd)%8sWmWZ7gJnK6{-4sedPlk=P-
z>9#|nx-mF*vek;SIrwtU>L^<JlSc0Oh=0I7om%?FBrV98xUX(wGADh?_PN&JBOKQ3
zY@3|A;rF07c2&WBp#iluM{Tt$Z>IX+ab6lYK;_?}0y%qO?o&Q^Xrs4S;wR}AP+Q&Z
zyHSds!*Mg^Nr=UJCd|3VA(-f#FW0BvM-}1yz|U{DAhk8U0o&-42`Wu(8)|DTzNjD9
zQaj#|nfoy(uJ*r*er;O8HUUIaaK0{fna$$IF*d(#*zOqq#bjpYnL|YRa@a=|w!FO(
z1shMP9sR-r(Vn$nqwR(4pe3&J&9n09d*3lht}h~WqMkVH?GAm2^V8GeAUf1s@^iG%
z=wqusCay1c&Muu@vGx~VIcw|<v}d#@tqV;ZkmItFO0_#O5?hF#=SJ`FRA-m2Y)w}t
zj??UNVm46Bp4;K`$L_qC){h0z*B&16ch1~ojqI8taom0vCdtu-a!ZI8i#AKj@8ln`
z@8d*BZh7F6wD226cGBIo?@7Y^?#~wK$__WTbou{cs)pBnJIQn>P<jnhS;yZ(Yo<bU
z?<>gsAK@>JQWE<5a%%gu5wQ3hX4y;X&~3kQl5}5Fyw>PM;-j2&tte!}t!Fabgg(3T
zcV^gId101`rn{HLdj~OH<uXO?_}O>AlUz5OxhgOcM_bnBLO=Ob;-m!I$X<&&_dJ}n
zP+R??)oEEjDiVEpik{h9f07F_pITV9GY;A451W&Vy)fk;r8Vw|!is8_9NDaz(J^!E
z6`hR3`jFTzXB`@X!md^t)DSml>3w3e;XKP05(j?Wd8u|c#O7xel#Uvoe{Eyg6;{%C
z4utpE6&#mq?X<atFOgL%!$u$%8rzEck?eD$w9w0s?y%XBI*or>qu2eUPi3eea8@R4
z2_Kl;m9Yw+gyDnrFfhu9P*Q<vx0^>!{vF84$@RvB#up9LZW;>d!(%O_EzEQ-quK%~
z(bho?OFxrFhrB#d>}QvEm>0G5HukN7G73^iPB4!SXBpe?=QYZFUuPt3#ZUttS!Z9^
zn|wIQC+5dO;VG(J2z+2kjA$-+6N2ppV^8cFI>9p(v)(CxjpE}hXVy_Mt+X4Yub{iC
zneujF7G&4Mp@MX+y!!(jI$?KVv1f>HqCG{|n}lld*gBN03zD#-r|5KDUH3ic<vf^G
z_N+sNo5GM=z-@1F2~SLp7eHGd+X#%Ed4_~!pm%f-8Ad0h1ViRg3-XejRH8&bj3?cJ
zw-5(G*|eh_1=UzC0wpFwFkcyZ9-ARYh!8`0xSOMeo5WVGllL5UCk*Z8v803PVFt!M
z!4M)1X)=a$;OF>dz4$S23?OxSM8H~X^9VRb%?wMv&XbNj!`nqo6NA9Tv2akUJWT%v
z5O@%@0~m9n>=cku9!9}@Q22VtGqpN+4LRn-i?i{Hhd^f%5X2vRFlY}^gIrudDg<Bx
z80joBjE~p&wZYW>!{&t5!nd*XBEh&Z1iWaoi>6zT)3fx{XZoaS^W1u*)0!*sP025x
z8@6p}YF^o@GO41MERxWq5-aslXk;Z>49GQdjfhl^y+%BDQ|kMJLlRX1O3TcSVh;Q$
zPViirqBW9skw1p%%kZN44*=1}cEO|%h=+FNF2BAI96XBQsK<aBri32~5ut@>Cyoy>
z#}uj%$7-kMDg?rDRAtK4W`)Gf4^f$x+S1y|K+O`QPk^pMp^D*%;xHOdav1w81O`An
zkQmXnG1X(CL=?QBd@>*;<>F4d^f!5s36Zk@jA;f$bn+4*VoFFJbCu+=umE2yRQnVw
zYgxT4i2@>8ZTlPm-E?}0WuT_~y8OGuAsmLk7rh5Zd`i7ETU#*duX+Tz(51pMH@O7`
z22$TOMB7FW*Yo&%&v1P-q(pzOGAMsDHF%bxs9<SY&x`p586;AMioz8HmE*c25E&U3
z8gf#=xAU_~0rx`=l;uP&{U8`pw<$<86`f|%MoC;0jPZpnt5#c2K;y(~`w?2_=PoPe
z7j{u0TZe39^-7Z9SdU@C0kxIe2Ns>}d&R8tZy>JKoCOI5UGlLoduvMrK_g(@v;xLD
zzXL-9AS<P|CaA64GDj?{|H2(6TheE1o$>E6;0UjpOpF`NN17sZb1fvD^O)v2PW^Z)
zBW>r-Np1CZ!w|C(zmDNLLT?IgCzj^+tk9?uA;tpM(V7*ylQH9;6yGO;lJlu{<Jg=A
zX`_5SQp*n=Yi-G#%kHC)?_t&O9s+;d((}0N##n6?wV-=wTBdtUduQqF#>czGpg()u
zXg@rj+IcQrMZ&DM&h+r-S6^W*Zs}xc&{=rl+HRfbd7tjB6trJK<NIog;xmaWF1d%o
zlC+NR_xXdUtpT+)ZQeW-I+K@KYxH1ZUK+=F|B{C?uW^DUp1>)@^z~Kw{Pxq`GIqMy
z*4&8p>F2oY8MU>8+8XQ!mql`8Pv>Ff@7~7s2s`2DaquZLHu0`JeeCE(=`EVWDZY#B
z_%1t_lxE&N%K&=e<u-ipv|l5>p+PA5$8xWeQz`1bH6L^_+S=%7(fH+|)E{27;XN0U
z4g1ezn#c3Mx<{+6js-wZ<8W@CjlRe1;Pg-)zB%I3(Wi$*ZNB~4-}F{Im~CUN(w5?4
z-NeF5Gx=EFn3zNJ*^s5K2b@jpyOq3HJ`|+3W~{dQUgdB{YN}&q7nDBLqUFF69Kd)I
zwKaSAYRk_%Og5snrg_KmgF|lSu1Q*u^KC~wPq*zR&M$nmNYvdfN^O;D=XKO=cgbW>
zf*eL~uoP`Hj&AxUB+Rlb`#>^cyKA}KhvNOkbV>Cl&wsWS%EL6abyl?s)ac)7(0P6S
zN~=C{fpX|Uv(;j|>D!FwHJ7Y~`fSB*zY+Sz7(J29afw{3(jj?O=I?z+bbqwW!fts?
z-MY=<C8fU!&GD>h&Vi6cZJCc<JZ7nvOlPmUKk-ppmae<sSTRoCV!4!HP*S^x8?Ce;
z`}IpGzV+|tNgXPE0nY5+%U%1U%SnUPR@?h`&21+G-Q+1~XWq9r4nj_BrrMB38kbJe
z8lpXKkYge7a`GR~@}aAzO$wWf`fNeop|*y_WP6a>if|K{QIouC$Hxy}2A#`^@``gz
z?)@RPc5(#*YTah_h23E$YhA1WMfl0g*|Up?|KfRbN-SeT>pY3!HdreuwipeSHBH-f
zYugmz#K*ytLJ&e9VA?=SsP!Y4@inAxPe#nPp7OZKuHzdRw8+q8wRPU(7GguJHapAe
zcjI80Z|B3+b*^VIEwSGYrO*8?_-fVzg*wj)AJ>7$gSDR<vHwAV20^?0`M}qZQ$I1E
zuH=3Ti8}>6f~d5FQ=B)ltmQ$61k969vqcfLm#%_Q=&QbkBY5B)skB+I(cO4*aX1BY
z(Vf8*xHeCI4F=+M{Jb=yFY{YeCR)etWp_Mn!Bs1tW;i8J>PHbHn8EA`VxH5xsSI5^
zs~*v^xknIk;HS4(<;_fYWe&V?80xOs$tG~!$JS*T2(*w6!3H6-fP<%@;ZH_j8`8fL
zw+AScwDNHT9X<Lz&Sl9YfE<XsN+p){pmN*f7idHVffqt>M`6?(m-eot#!kt(0(&xx
z*ED>C<M6e`oJYLsAr1w}PR{^}%pe~YHB4O+Q=0+^O-PVrUk_sA8syjmBIrRtKmk5s
z1kNgG!4c@L<eK+zj1rgkd^UV%VsKszYaB3##cA#=E&&CFLT$wZG-<TBq;YsCJ@I}W
z2>}?$!9<OA2KG9j&|HNX-$XY`B7*T*ZY!2RsYor67g^<_@EZU_PJEnYK^OIC!Baf+
zz@eZ}SOi_opy$)?9bz_t;YBG)ciDcSXS8}_FccQC1ZF>+!>~tLo7*nGCUr(px(+Lk
z(t$#fs=)P!lp+%RBszAcCLj=%0vzMgf5#iz>3x$`p=I4dUIKEUn|%Cn^>R$bblbAP
zYam4G>>E#(pmfVV@TmlvLTEV5u4Y4!gB5Y*afz~21S=*Hlzs+t#jJAt773p$;JRut
z&-k})W6pI^{AkGh0W6dJ20*|+YbZ&K(QRd%W-C1zL=`H6-mo$VAR&kajr$@z+NnoU
za&xy*mSy14QktSOdq0%sU{6Fpgc57ECvP1-lT6;`!tD>;Nyx85lP12o#Nq^W1x`X$
zOexogM($!fMCn@i6bI$)`9&DFt5OEX0vDhCAF&3CQOAy}U?u%U3-Vndh(;VnY}=hc
z2iNJC*$okuNPb!dI1QwlOJ;&gD3+-zmLmYAI=kP&+Z>jb5E%$~bx6Bp=?@p#etll}
z4Ca_X)cntAj741Jhf_=0B%Ilav>alJL(%sKaZBCG&;c8K`Ozkqw}yq7hq$A*I&0p+
zZj_5?;YJdV+R8N#W>3V`RxrG^r^rz48@P@=FwfM3LmRzMQt1mRgeU4@4z<;xwtCwq
z{T0}Ih{l{!)A<4=ZTU^?g_i5hxS_U=7soTU;>!On9<L{_HECB?tF3b}EjVomPDS)~
zLLE7m;`@^}V=u(IVJFCdR368+j?{{eX09H`Ph8X@T3J+EpTaag`2ZziIAp7QCx`tD
z46)doRw`pJv~=hzlupu8?a^CB2%YP(d@}hHocjZ%VFtA|OTLn(9<?=RwbkG;)~Wd$
zYawnDmX1~0`Ga#+k%iea*fshIB>ha{-2eBxmd&W=!2`858^4_|Q$0hYdIy)}jvfp)
zNA2K~kQ8$GMr|b_H=Jwf3-4TX&A(hOjy;EKhu;9$qt(`B)Yd$zt$#Q&<p{Cz1q*@q
zz1hyxexJ#ip-bq6C;q*SmB%ik3n%WlTesW-Yo9Pa0+HOWkMgnFsy=ftr1_5s6>5!S
z>&>j=AFc-#hQAx0GkN$9+aLE_=sXL6H24QCwD8U2#W3Hs?6;m!r_uEK%Dths77w!8
zN;VuK3tpb&#SzQci)2oB>`a|l;0E4_NxS5x;m~V}`tZl9J8OP^f^0=?-FIS#1v3`|
zxFdTQqG?6)7mbg7)Qs{s7)sPu*rME`X-RFJp_Gto^Ly`HpzArG@t3ZFVYPLxewEqO
z)0Q?KJu`LT@TXA|F1Mtk`S3sdRAH>Px)0nlG<xH}NV8<_z&(kL?LJh56*kO2@b;mM
zEVJeRcRN?e*1Y|}8(jXSWv&u>n7yleU&%+5{~<}X$F#wuRPsz~nkzqEjOugFYHMd;
ztRUpsuOcmS#Z8`Ntv}zZ?mPTeb4$>EUpIMcvh0bZ2%sL;h|^(^Nav)J`oOL!qIE^s
zZue2N?v}25bYfdV9(zCk3kXdY!rZkD6omQcHa<Ny_mi4<9R!SHeydZMdw*gHtF0qH
zZ060R7f2IWY7*GdYSm>WJ)aHUrGj?&1&Tin@w7$*GZ=vouFfbI^>DsMyGsAOozMQ0
z_hadtS#Yll!dbo0#R1p&EExV@htKJfuQh%|=5#<L9<_BiYn=oAFR{j$IPm;A<xd({
zQqu_7PPY&Ob?5LUA?>iQCH*+<e@SZu>`rMT^aTsQa825jiaB+#?&Z@TxOAzue0_U3
zs;v)y%h%i8_Uu6&x<&&{Zwkv*n<_$KemTBy32^~iwXR0A=A6yyZq)5+t3#QD`r(m<
z#g(NzNn!pc^3i5JZpg{efI9~`&>=eg!EakV%B1v7T%1pLJnyef+^GSw$$?^B3s41h
z0f$*KrfAcDq-SdwfrB2nMN4J2fF;lmb*;QyG!kRT=QMJV*ZL6A`^68}4M!~x^1Htq
z#`UV)xHa1ae!fEBMT0`Wx&|^Tno@C&7zNC-HP4L<k!^=>&||bPN+Je8VLjUnIUf*_
zq9aA8OY<b@xZ3Kw?8iXD=R4n-f3vk6$xr35%mZVbs}bcvpfGfNI<ja(a3Sk@Xjc~J
zq3P$9_`wh=GQPs5U(Grrgz9F_5=N(JXE@e|BuK22#3OhlqW%s`8gI7_a?T@{GHnQv
zH{bIne3W2EEU=ixE3-)&{D>e$AF<gs$8d_aNRXLVthL~shFE{z9eYN<0gvt;IFgWc
zF(=?YU{0jAj^hy{!DT5TI9x*FWgbrEY|hVEo2CO@@<E)=%*vv;lHo=UOI|{2)95*o
z;F_t$MLu;fig^&gKr#76G~UVS7omFDQ+v~zvs*LuHF)KVa>DBYmsHso2cQV8g9)j}
z;D<KPtV#h=ksC0biB3Q8v)Yd16k<f7V+ra7qDfPZRmx$HN=t^qmXR=iLKO$07iAmO
zs%IAF=^-oDL>9H)Cq)vVBu^iZ0lJIPB@e;8T#!jq+<AT><HuwL-)@C>a<QUTbMEb;
zQ3@pi(ZzonV;nHs$VB8G(}s}8<#$gK5>{K2q|@b00mP731OnAJhC-VH2bKcs7ov#i
z`)QE18S-=x7)9XjyO%s-#3h15EuTMTh-U!gE$c)vwnb;Vun`*JNSc#v9lVHIHKDjJ
zj<W8B%`u_@FfF+W+G-mv&a_5@i)R=isd;(zTKb6DS^JKYyqq2tsG1UtX9sEqwYW{j
zF$0(d0~FlxgZH$U#Lypln~6B;yc5hOC4EUGC_Ks(pL%xVMF`g_wgEt_apP0i#iqg*
z!%OD!>0#33`HSq5OWDSIYWUl`^|<&D`(N_wT_?TW8H2PWpxRM}0o2wI8H%<I9=o%Z
z28eG)Z7p*R!EA2=`$4AM{wcrLr#7<sVmilPizxr#P}bD2CBo{YjT{?IkEhq!@rjo-
zF<qqI%k6Q|n6JFd&M9tWedFtq=MlS<$ZsdMQccIZ6|HIoskL1-<{d6fj@pTWxX;ZT
z9Rt<r*O+|R;qgaS-+9>x%b_bw7A!KTd&ThQ_z+w4iI1><@}y-WlcQJ=#^twAz)@Q}
zi%-T9!G6E0w6*`1{gp7;ez4pU2Bou#_i)|fR}9^=TkY~k&rHb5d~B8VE(UeX`4XG(
z#A*H`b!ot7xp2|`)0wDt4EtwS*_y>7S={ERBddcUbtbjdP+M*4aSTIeddCZ@7T$Mm
zR!DJhCm0CFXmR!Y?9hiZd+_O$vFBy6az{<YUh%3NwRIt)3Ts1X(p{^Z&KI?dNW!8$
z^A}ZjanofPXIl$HZ<<U{V20CVWQw$9)BfI<6-oL=YTOT#s7cvU!)|bMNqY3q*T@Dc
zg=aBzZiHqy>W6=ER<QT%w8Rll<Y>YtDkA;CZM%GoPQ}fyo|{kn3i<Kn9cmAK4CT}$
z{2o^EF12+&I`?~|Al`TvLk~WXS*%XkVtb23tFNZm{9Q>J2S0Kt?|V(POcD>!O4#K`
z`5euauM6g|gxdca6N#cZ89WaCp`QB>+%uEg?ma%PwuZE-eqwxeervH0zU-<W&157d
zX5hG!foN$st*x}RK~W92^5Yj|{=0i)kr2|x(8h~m`mlR`56k2bTAtMa%{sI9TDtUl
zOJdqIx$&UAC7yQ8Iv=<!NNo-ANG;{p{^mPr9uKY_=Q>QNWz*lT@flhaox891!GFKT
ziO!-^6;R?!D4<GJf9MqMoJZR1Ha~iw*>5r_{7lo6*po0ZUQ734?MV9@NH2yxqQu@|
z_3$eUc3YpSXnj9RlB?sfmoDv_`J5?6ADgD==C>3hol9w!1YbTYR&4I3eshS^n$dNG
zhaV=UE8wwJPcB~g(xLYxLEkp&!WSl$f57{Q?Zu!e^;xB@2mTD7<kugp=ckCF=X=U~
zoM>>!6Hk3;lB0wS!f-@{0zO<*v&(8L$)xU-n!|es8C2H%B9nu(vR2wh&I!7J8*O>g
z$0!$mHMNP7sqoG`OB^paD*fw0=|X~L+v-_1eCv#D%hKFFRtxF;h)-L0y>w+&;@59e
zZLp#WDQRs<h%l-efYT|;sp#oL9m>`oFqJo3uwx~aLuR`1q=I>D1E9mca%j;6dynCP
zir*>_ooZ#k^Ykfj_(zF$@su~t?(Ew7yy!IWb%|Z)%q~TWaXj6j8;gmUuF@=L!134M
zovKpiSpEbgPg9Ir@K%ov2PcOZK2E3RL6Q%Csg~sg2|q{D28u%jnUPoP8h39-Hbr3#
zhM**JfuG~IIhZCl>9V9WFfup^RTj(6v{m)Vl*C67NGUTfe_8#NHWheBIq1D9SXzhW
zZtPkDDtRSXnzMBX>y6oZpTcV6C3P^Y$2h&&g)uxxtnoDrWR!TGg0V2eXgJE>k)jn=
zaMR_gtR<>`T;%8(X9P{nP<~1BuC9*9fmok1%0zle6M4XU8-f`>q2;8}%iJGgUq>{E
zzi_8Vjb%NE?gj|!f`LKnp+zQpl=xFmsW@EuC!#O~gQNr)rFClXRz{9YbXg7XJ&8jF
z9ts_dE=wzi4WFIRl6<{XuyG29qEHq(xzRuh3JF~vky<Od@o+N0n%7$p&akPhjnn%o
zd!HxMRN_`OFE(-I8gBC8XiVDjHP6S+7s_cO3sl1$Vgd-N(q8|lxeZERmzipDSwq$e
znxJX!AjoApQ)K-2hcO#UB8F!Myh4|t*FzEKmM&(B#I1MkW9~_na?duC3URbK%)o3O
z?oI|2zZHZea^WbE%gvsn-idjRk*s$)o!KR{I6gr#G*}?4O<F|?j4pY5IY-Ymf#G_3
z5Zct~z1F)fd2I@S$9BRb@Q}P>;pH7<0U9%45WTO`iq@DooVz)T3D_&9mvQXM!_jaB
z)ek{?CAP?Gy+@`-d?3_k9qhyc+z~C#ns$kIgZeGF39|Eh<-Y54x|i5(4MC`pE$6N6
z^lI0~6lAEa4OUwl;e}p`bjav7&`a1aKZ?v*<+K?FuvH4QIqQTuLwy5r04)2J28a)#
zwiXGSg!3@p3*ofrpd`&F{%&5~vrU*nwH$%TwRbvRJ)rwwlki~S1!cr-0qTngaD+GO
zQV>a9YI8R6Fh&x~D#=9JInzqJ-L=l?j1cXPAT+Y9zC7(3Asb1C{WiYCHxhN-^S5V7
z+$1a(PrNp<)yrtGK-bUsYGh1~%o{>T`H0Ymm|i-3kIz;|?ZNP*`5ra~@2=TfZPX}@
zE3yUxvItUJ>yOyBsb_0;G&ut*%#f{`Eq;Ui8@dW9;*x6w&vIWnyLu4|PiN1tjS@v*
z#|*U&?-t9A=xs&$Crj*v!l6HCn8_qcDz#Ost^VQ>PlzTVeNQJXzSyEkh|%ID?;HO3
zigDIVXoi}UCWPi47Q2K_p4C=$6a4{&e?0%i#Lqol^X%Eqn#CQlhZ(y&_scnQYd=Jx
ze(YwrNOsMgIs7B@-bRL!$8M&_gY*KQghZby5Y8Sx#K|2^Y&kAw|7?%hJI~A1vbexz
z^y1kcG_`%NRErjNTo)@tf6i9sLiWDz1^fE0t=SH#t*ll07=%%T!_fJ?Bpx(#?F&be
zs#(CbAI#jiCFM#cKV1CHw5_yXVJS_~=mCUw7iwX8{%~vw%l9#Pg(Qof+In~aqEgBx
zI)BbC*+WOHj%w%H->7!B^@|a|aQ%nA5iHvchom46IEh&*i}^pCE$sSpxKHTeteOBI
zTHDF5d=u3dlxeNDip|K`(vP+Too#Jm?++#34}6Us4tJcf5^g#(A3pFQTZNZ}uia_c
zM~LATwp!?VtSngl{xlwgHA-u@M28q{{W#G+Y)j=OXqRy2rhhf58=IX~=nG%gi?OY&
zP%||V9;EdBzNicY524X((njYn31hXjIMyU$B~PgY^6`HXjj6rBrC62QfaekXX^1&8
z!AQRKDMi6?Pd9E?hmP@?-3rDz2@a%PwKY_(T5jYZ{?-DuRV$L2y*K54$3d`-GZF8F
z>()7wE_`XY%X<|nDYA~WU+d{DlSbSDyhiPZpAMDz#F`U^|G-%3U_F^x?{-=<2eWPr
zBOS&w$g8o%j{6;{hC%jjZdZ!hs!LKSsk!tRsjVreH5Rv($U0uhq-a@QGS}hKPTCbo
zWM<)A;ErCA=#!A0p^ireXEGprJ%yeQd>AUbK<f|iQ}<`0-=woyIzMKe*8iU0UX^lX
zuOM&GR9GMf)Cl~eApe}uW45|Ek1?bg8dSi3Netf1#Y!cMb8<<ln5X4(6%w#bH2xWs
zAp~edd>WvTkOo+h*w>(ljp1<(DSGbok~`<2<;}05ZD81)ucSm8l&r+2g@rtAiJ#}k
zd`4&!Bc?c-l4}xVkB%~ko!lPcE&d_|+&YW|oJi4{{KoNZ7Qz%3#vC!AYh&pT&3IhS
z0$7LFMYa}*>GMil4TS91oCg_PMBqu2bBvZeR3cv|R60RZV#n(~x@ypD{#gnb+^?`Z
z#FJuM1Y=#GXgl3wxG7gj!V&6}L9FK+MmS9<byS<KNTU>;X~!Ipos=pEOu#E~JbF5L
z2zw2DG^q*m4H%%0YRhGU?Nq+X;h-1$9Sd3t%#3_Oi?-HDFb<2@m?zWyqVU8z)hvk3
zG)oibrT5d6=b29}Mb!`HK@39c4=NKA+d!Ri4r8}ioeV=cT$mR>IPE{_+{Xm}ah?Gb
zHuIl?7}~NzPHoR*SZiFFnh2!H@w0epozuBh0e+Zw;5P^)AHlR9F^|)3)UICQ1l*DE
z=sE_O5zsPEZ&}w>Zc<yh5d__U_HzIfY3V>|Y4TbOE5Y0hmyX8lVxfXqyaY^Y1MvWe
zGhSrWsVodFqFN&)B6hsIbuz-GGYz4jtR`&s{)5onD~`*W)T00CA3Ao;N=cz4L<U~e
ziUr)+iLEQyRfaYNL0Aj?Vhd+8vU1A4n{Cm?!-r_9n2$!U!afxXXtWcbCs16+i4Ge+
z+-&0pFxBVWNOHm$Qd|e~GPm$ppM5IAK|*3P?mAo<OFbM}FaXw;8QWmPY{El7fUaP1
zMFzEYK=e~`n#nZQm}+?ubqo<lqp|;BA}4|lw74#{M0i2YI5wDq8U%iJg$f!&-$|c_
zU~<<D<9Yij)YjXx7qYb0*trS$Dso0kOB|_slwH*Brz*9zV}}!Ku-fXod|JE1ZI&9T
zYfd}v)~bg~gVk=<_(GX;VKOCLx02bb<}vgImuI^`+=<$%v#oHUR<MGib#GN(HRF|+
zdwcGrw0td?pC|X)J5Rb=epUF6U1tb#5TuOkSyavFD_oeFnjiXn7GU{(Cq|Imjaf*_
zi!5W{1K?t}t7Ox}b4gR+NbMMEtA&R?%(Ub0lGGDtr8l72BLB3LmKTHoB7&IAlR%0x
zcJD=)^%RwX1x^L%U1>609tyfim@|z01avoE?`!t@u<v+gPos2hBBiA7#vwbqex*%l
z>+A9Y*Rlb{U*;B`!XOfkUpRCj_ramIR(oRKn5M7%H=m{?esI3JI)pV!25{`2o*$e9
z(3qMNVpnZtpMu0#wLj(iDxK6G>9Fd#|4amjkC*qSK0Is9FFY2n^j+g@Wy>Xr{n|9%
zn}~TO*P`mvTjypTV+O1Bh3sympZxN#v0(Gdp4C?F)qU)I;+lNpToPB}tTxn2|7Y5<
z@6uc~&n@g(^p*CXo}K0Y_v?JMvv}dnX4f;oKyU?DHYMqq&1suHBErZmFDGXP7V~hZ
znA!2?nb)TW-}xol<G+n%t4fpO6@Hs7RG<HZrR}>ehUz9DDr2mH+tD2}=}LP`><gBk
zC-s%uT5Y<}QO+zXa!=72Ns-eHzIpxq<_`Xl`in~;we|hqu;4clYoq;|;Ud{xt2I$u
z>8Qy{AZ8#*>)y#s!>DL`MN49`OW!ny_^Z{{c%`p6<7_JxaTAbgb$;@Wp)y=@rnwJ(
z$Yv-D;j8C3Lv3wOzN<EzGRYFc`2R$S7Ah@<PP@k40$SwdCSji+e6D5>e4LLM3Z;2s
zhL2xPbW2}IE&1@Pk=YNce(kfP7j>+&3C@zG*Cp0|iY&d4%gCQ;q6?cl8Sb3z3{4*>
z9<i%8Q&$!41V5S=^OwVC>vtn5&U>(QR!@gozYy&v{qaDl=HWJer5a+CGQOufd7XW0
zS9HlxTT^?lrBxT*4Y%Q|Qd?~(?A~^3wG7%t?eP=$*%GbtT2SR%`9G3AP)J?SzGk0*
zqO+~6D-MM44(ZwHo5n5Mb#5{3Usp}X|MMksha{yxfC7e^eLGpvY1cIUXh@T&(O!u6
zQ))COL&L_$8usOck_0v1N*2@6b7vKKTKDOUee70@sI3Bao{81Lkj%d--(?@()=ICZ
zWVE*QQeA~iY3o}g_$sWkD&2#?tBz<`C}hqV80m>XxzTWUxoeFtce1mUJtgjkqDPna
zQ+bI#r+<V~oC|#bs|Pikgr7o1Jb~V<>v{CvV)7J8<)$t=gdW1iZ>Kr>1$J^wQ|+12
zHH{A)jY3MvTv>`E9c|s=BV{v^2SSPC>p0XUcd6O{4K8U{II?*KyeA|n;Zw54O5U@n
z3V;Ac*K1>y<7u7=AGL5)dpHEtb~V>yK_&^XN+h(#n*~}Bac+b}#PO|Hw}QwtAqK@F
zTAE3FWG7qdN{U2Tx9QGqxd=h9H=<VN(>{ZXv8?$iDeJ>bJC!xTOUp@u`mp9&3l)#Y
zl{xDv#K13o1n{HWl2_w-IPs2`=Lf)2>P5#a2x}Hi<|2)qr$9L@Z-yIqN(u2Z7!DB<
zPU_?+k$YSsN_K`+AUG30tKhfY8oxq0J+$S#sK?GO4+`D`5oqnhL(Qe@x%PjDAfEXZ
zK6YaXY{#+^>J-6Hk?+xKtNB&sj$LruC=C?iWWv~|Ay*?c)0JW4r!R^+l5<^*w6Pvl
zKC&;V9XvgBW2!ur<Tmp4r^h|jRY(e*lH%|e7@QIdv@vD!5xF7{i<R_h&I{E7KT@_H
zLagd?>F7~G2IVHA>>xx@Iw)tSM_;HY2T)TcKUlj`c2wZ?A{(~)#O@6VOTkVq1Hg6t
z#Y1dx(YLECQxio2QBu258C^44J3RSmvZ<p4J5g}(V>eIo7yus1lII?1u4!n!Fq$^s
zjz?HaTh}K<E~AC8JqYzL)Ady6hI?+Oea}J>$fD3SRS0-RQ&#3n<WNCayWOoIZ4q4e
zEr~1_C7IfFX)>D>fwB#~#ne!faF}OLLEv3?>d*RulkXg<bDk<ATg8!_fxxvv49i}?
zt3hSn6ri@Es0=skBSMb{g*$dcZqyrATT40n_%WB;F@5=39`DX5-j~twd@ITFFTdOs
z{;RC@oCqDQw(4B^ASk4^4xzRlL~RYHU?0>d`%9MCBQ*qA!HQnq{#nck%fh*_DtNh$
z<QId+l}wW4V7M)v&yMa|c}MHpX*)JJNU-w@`E?82O~hy^q^zxat;2HqDxXIq&88U%
zGOkR6E+GjsZ%n8<GxmPg@fK4F<l&TZJ+Tba`C*&0Z5M~HCcn>kve?@E0FFMbu8SVP
z+SOtIA+;gdwpAL&JD#Nf?}qTalPmTH+jo2{d*U0h?hPP@x7606zAIS!aYhZvTjCrB
zpU|=J4Sch!s=`yPO|eOM)t{9*l+>uw*iU>Sv*$WfmTq~2x3M3ZNgH*&_M=bacWAX$
zYOB|3D|r}!fb-?d1^3yduPf}ss|#iHP!*lw=kL5G*59C;gjI=x!}V}2ci}A)ri-rz
z!U~%A;=Tzg)jv6pPUp@#R0{j*R%ge4F15W}F`TisYFzO(C7sm!<{>|vzFhi>b0}LO
zed?2xXg`$Omh-14@{c+5M_<7wWzi3t9XR5{<)3@vjhQ~W;u}NDuCwEhGupFFz=U@P
z{0*<PM60bwcdRv3nS*Tj?a4>;OAlDuW)5mo;Eynm!cD^VEw=0|wEwA!aKa|x>G?a8
zEMc{ESh*BdFUV44ph(!QC6@!2W!d;H7mlvZn6537+G?z}W**-G5ZWMGvU?AkvUd0^
zj14&`X37}pq;=Hj;j2yzhXw44*6=p_w<DSDdtVk&Of@-jHZhc@Y!V(1LKy^6^B&z6
zq<LpK(GwuNdWnSXw264=RZ41Dxi;4|!Q&j`u9S4C<Wa#V+T<Yk;jOTxfA@df;H0%@
z4bSPt@BI`EzufYD;ZUqrqiD97SRDYtZhSqdWJ1W@2i51AMU{P3(8A7Phm-%0t`n{<
z(#@2TG`6?gB<%g=-s_S9AT>4#FI+w5taVwJpASt2nPQEoVq}gyU;TMs*k7^rzEoUl
ztlo<XF(k~s5a#OdUDRsp6zwhKigoSw2|~8(HW7X)L>i>B3kSgRL>4veo?|+`bp^GR
zy4Q2r`0Z{gHS~K&v8+W^b_$vo@`a;ZhruPxtR%OFqLS**a9k6Q*W8^!Y14OiZc((A
zNT=xeZVN5RArH5vUMNZX8J2CHPY)M?W8aAKF?`LT+3wTWc@QM-RV0)~J->d@I{q%<
z=OI-T0AmOL)7Gg5vR${zr_b}GKnM}Kg+Z*8=h(9E@-!WD6iKW>>Kf*(>oD%u+&5wH
zu8S0@tI)5U3?+(;C8adK2!iY<vpM>9m+I`mCfZ;EI2)>x$gTBOt)t;cOm0f#T%^v_
zZ;(wePu}u!;z~aYR_)?jOd>8FM3Ws+oUd-<!&0;Op!<!u7}them^X%wHVN;g5f8%A
zXq6(|rH=(u7U<n(iT-46;n5GA!#846)v8dQB(I~}>Lv-dli+7CkEQi;L8T~QNg657
z*p~9{191cCnm>XFvcy`>$5W;;>r$MPBgl#=6ZL}4bWF5js$c>cmPEQBaSnn2VoA2-
z7n`?-6W<LZx<KkPO+`H5xC409BMMg!%dHr<GATF5Q<CrnT6-5VWKQy}K^iy%5v;Am
z)SQ?9@dZ6M3CoNkO>wN88bC~XIc0FsZJcG@7(NGnWczHGRv+MJVpnG44GA!cTXQaW
zKs+qsR=K7Ob^^|t-7hF&GTTt<<n3hc3o%+BshfQcRHt@EEWi)uYAy=}fg)T=j`3FH
z#0w<_fmSUI5#M?1I3u(|4gjBmAX>}3Ly}a{!MaleHH5+#1*pV$q5+kdf{C!AHO^33
zQdVq6S5R=~)*b;zDq*l&D~d=Xx-Z0_(YWEmt9p`n%bf_rnWF1L!n<Kv@O6?o;$dna
z{ItaB-3pCH5M%H0)+UfB#KoinA`7B2Zswc}td->rBLTF!t^+H{5aMXi_IvSFcc3Lg
z><9B!uRD#HlSI^W0t%pzq$8}?YJ)-`Wm)Dylb1-6HuBqv<w|^kEQ;5NxSGa!p!9`+
z!b&2O#EBNsC3;p$x|3n311}-+qi7eQNdd}(H?M}6Xo=8_XbTAh6hKW(MGb>cTKs|x
zYbcoegC9CcD+kqcXUtlNEtsx??^0JO=&OE%fnqAegRmMfbKl330+ni>7!k%vlIW2U
z@2W(X;7a}@a$NL>i|k&}RwCln9|C(qY2>=pgQAUq6V(vW9i$zCBYDJVt4UI#@t%lM
zkcxwZ2oh<AYT?Wl6nlTTN?RK!l0!(11hhp<iDn2c3e;bV9-d|IdUUa^LD$8Z^Dvdr
zKtyQ=aYnT8Mj=qVO1|f9dR93f)Hn-eGf-)fJ>iOq-%PL#aTN1^2T*qWH^6@-*FH+U
zs#2$oJ;jeqsVWNCA!1>5GHHaQs?_Eei^GKPqR_UT9HX8dMPW7u9|@O2P}-afDlVr&
zIMw=(w7JvbqmfrdNTtvzX4TOkx2lGbdUZSi(%B3s{p-MC4*Wr05j3Hby(DQuI!%J*
z>hu^4iZwFmE8Ledt7e#L4J$;SfrYs{{(K2PRSD>o1n_d`dERRf)=UEo{&fCyjukoa
z5%nasjRS!$DM~3@OP#_CM6g?K9oDc&3dgzssiX1OkRwOOXwb%kXM+}U(pM!K4#T!e
z3<T)|RkYn9ie%T7SA!7><7<}1;HL!>M6!kjy`H3p=#9mwQyiQvMT_t~8ge>4lsHp1
zb&giS88`S4F-I7ftI&o3F?sNcs6<FK8C|KvNDNhx^Qx`G4EPlY;M7L~3c&$Tykooq
zcEZ52@LsO{p_DgC0IHZx(RCj(Fmyv4f>&0r!Ov}xH<deht03{dt2U|F0<Wq1+-TNi
zG%k4!yE_7Rk|c6#Tf;{`Y~gNkHV9H~vJ#%>r&t^Os+JA6INYv#7ir65LJ!cjzFW0~
zdJDv#_*e|{(LU(W?0CfeTw8eXP?h|^A!MH*w<(Q`G#pLuS;XM9(|b~=aMGl}`XCDc
z%j_1Di7kpFUYUt6Z(%|dD?ED(xJdII2u>R~dv&woN_5u1NjQ@~kNw#-x4{PI*>DjD
zq-19gifOpxKZ5SMG)9tDF33sEfk!qG(#2+Fs47=w-uU?-UcTo&i-cwAZQ-LK8=q|B
zun8dgB(jKMFd%BRl4{)9AHh%@ON$92UaG-eaPYGtGlse}xHSQjo8sItXsbp~SW4yb
zsH9Fd1d$3&=nMD|1JJd|xFH0I-4V3SJ59`CUI#N5EZWeI4%y<-2Q92~-`MDNn`wt6
z9p~n|q~R1QJB-$IlrJL~$L1<vCYH||!nnTH1tj6;X2{{Q;^3#SAHaOGMw`SjgA~+3
z@F<9$ivql+38&nYq`?Wi+N=(zwZrpoCXw3la0=WkBnwRTRpmH7{n^R>t<%Fcbqea~
zExFx*_&SFjtphF7;WWzKjdQsFuX1n8yP$Hr%58(pdN5f@!bri#9C2vY+^jwl8NNR0
zxaDy&b<QmiiDx%KI%6N7;y$*9>(~WLtUa)L*4~+CzLOYRg(f$_TBzI8!&!axtq{M$
z9G}ih2wQ;+f7+zZ{|pzrTv78~=K-&WxpkDU7-kQgS!2W5BQezc5wcZ>o{CjcA_AZO
z-$M5T2yg4E-=DrRw}USv`n0FH^Vzbc{afxL#1_l90&NVr39-1%{4!Ip^`%Bcom;Kh
ze(jZ8Ic8b;e_gw-|5Vy0{<=s#Z(YQq8d6Qhu(>R4-fziNEMU0yfx<nrklH1q*2oVO
zuKiOwdq*MuJ}LOh<Wlp|x4Miq8J}d0Wt(~mf|J}EpZ_Rzd_B_D*?%|^1+r%g8^)d5
zYIaCGexb`Rz0vHkgoNBl^=$pk%nZBt0%!P=#GR<cE4LI+KPcL_EEL*)8J^o=uKc$r
z>v&MvxvjozujwSi3p>u~M`g_~*bNt0arg7i%G)UX-1b7bn7Fc&IJe_YTh0$AsTbXp
z)Ju}prz9}g)^}~QgNu~b5_OqniVjOrVd>AwimECJXG5q5Hc#5&?{Vni?vZLMJGk*E
z-rpXHty%G0N#!Tnn1Ml*MqgW4`y=#l%40?1^*fJ^fDc}Q(<a)8eESb64C8zsqW%%0
zdy-xj67}s&FW_<iM~31@H&_h6Fdd0^@zB*SYjYu-l_yVRp0`LYzCM_!J$UK03!Tx!
zuI-@ItSwvng7=4|0}C}|_Hr(K4kK|^0?)oM+WKzBS39n?<>}E>6-X&xgJRzY(DOfD
zYbVbalNxRg0$QR)^EAZlH(u!s*~Jc1D``zy{=6*}{wK3G4uM}+Y^xH4;P{2+7Y;Eg
z6kS;PW=CSjJ~L^LI?My$`0!`8`P83JNm({0WFAfpAZ>Vzp-BH-ul<*|AZQSHb2OfO
z<hjdtl{*SQbJA@iQ*%t)0n_pQHgfoF!%cr{-4s{gc2n(O%)ayMbiAabar~EX1~qBD
z39ghjaaPvCW4t)0$cQ-GNx=fezQ9L#LLPahkgeeItF$L&63z&GCbVpBqL34&o%}0j
zBS+st`#sDQ)rae`MB@<wF%=C~5oQ(5W(c|}T=z*48B427oTZTjTr4$_QmhTqWxCLG
zp)$=H>+lJd%I+%He$TKo&VeGy^UW69Vm6WuY7ov}Q?}L;&^1J6dbd!XlD>do2s#Kl
z<dm=0M_leS?nL)Sp;@8NVe3>iBdL_EkXUb5c2gS~U=prsIrP>rH=i`maVpCmLQGzD
zC>ByIXlYivMNIQ~(#40NH3(oLDB14OD?!DOT)sYt#3EN9>y@Br+vpK-L)X_k2xCsu
zaB{9$GIv4~cYz81DC4q?jo7B`Wf)3+p^CP0<~b0=tJD+o{CaPURRShP!+kP`wFiQ9
zLQY_$#5M4Xpl!XrYwr6(U2zd14MgZvO_e%Pss)>1w%E^Cm4PV8ud-lE?mpU+l&tsq
zZio~5XyCL4P3sIP&ZSpFBwo6s6g?J+YFOR2BD8TKIM4o2WRwgCnGir6$toeQg^|eX
ziFGJD+x(hqe}nGku!>=(V*}<kKOmh$?o*_YPQx^*21t?X!V(v;&=p`S+EFw@1FA+;
zrj20=uZ5R**P=`OT&TBttP&MY6?c{2Y+l20jf+VvA>oX~a)r9_6C#T$i59$&n)`|F
zbr{Ck<Jce(F+(rKn=_quo<^dGaWNtzQXy!^o(f`_@QIsh*$06{c_l^7QO4uOGGqwz
z9jKV2b$wA5;rdbt4%9#_?HPHdjsZ9j^Z-yL*_`QgE~<8{avJ#5z{G*&_%^sX6%1ap
zvq>oC&#-DRip$zg3s2+`lG*C^t**8E%BTIQ4yU!vi-;P*c6^f@-U6sgeCzTp+Nwvo
zX7+0)+>Xh;Tyxpbu<&mp{U|<==sA?wz;`EkJKhz91u8FmpvOR!{A0+l9vs35JqK^)
zu+^c9LoyHPX-LT-LWkw9%CGCN(Tmz@6SO%)yuE864$`EaAwpsoqz|Rf|5SUVGZ7pp
zgCUNVIyRO+ElIz>QW_5bx;=o}>UwHx7H-MpZMJ%~WBlMTsoyzP%aj7fI<YhasjY{1
z4vsgZAR?~RCbM(WhU=>DTytvvn@Jllgj#JbjOOZ5sjc{Qw{Oa|!M8P<Hm!zvGw^L{
zsLfB=%&o)e#IAF*80@&S(Qj+@^(<sb+NyKmtJK$^WZg#dQ(k19@Y`&HUCy$kb#`$^
zS+fu$4Da-`aocU%dFN6%f433%%63Nw`iAUl^q9#)*2|oTzQH3IIW}WfzRI^sK0j`&
zV$&*#^UVITX|C;YyoRi=oHrm;Ifn$bm5)p0K8&*6H@hZkF+Om=JZh_xmbPH<^##U!
zjv(blAEcrA7^Vkyv7E<!riz@aJ#E_Kn4pcu4946K#-+CUCi1-7&UIyWRUuw=T+ROA
zf}+|IS8hpFhGVpf1hq9!J#T%Rv8gH@WQk{+?#B=%A(xGz-7FW9p&J<4UiYDd8#lMx
zdkDt|3Nu%diEJ~|M>nQz=|?#VC!5bFFN=o+xqt-DP^gRIVVhq#`yG})yT5AU!sG8|
z6f+;}mV39<?9X1tA-s+y%grrLoY7)$*%V{eIgw<wpFLvfu^qN@eY>V=8zJy?x3TuU
z`-LPA7woKD2R&2NR-3=6=I3ss=-1ARMN5fHE~rn(M#_ssoB;SPd0grvi70Z}wLjBp
z?LLvmV{>-qkH%~#YU>JW>#6&ePZz(le;!^(!I?N<<=$;It^Y)r<{4heRD()JZ<n9C
zzOX3&z34aX&y&IN{F+es>9$+@%v(4qRJGkWZ3IhPJMlw^9VT1P`AD8m-aMq3^Yqne
zSXm?`q)mAd?9Mk@h^Xzi+9LZ8eN?E)b^A|mPPqYOq*;s{qz#9Kh4ZgX_ykB<mA*s6
z*1r1_G&yYMOzzp1hB0Kese;Zi%W~z>SJ>1v(~weIRgin&_kAF<+1B<j{M_N#nfE+4
zdIwFQ=_9^=>B-knCx)_E*}h-P&VEjt#Ci}&G1K9uV{<ws<`Q>-h47k5^l^q<-4o44
z@tMSdGyrJY#y^uRFj!$6xtx|=^q_arI7hilmYvXR9poMD@_q-wn3vK(rGj>yHe?4Q
z)}F)0?=T(}P5W)z)p=WTm48PT=m?UfG-MB{;U#UF8$Ca9w~}M=TTct#m5S?jGN-KB
zrK=;z=ZIJ1&+rKi-~NmNNq&8Iuvk(qS{JN<g6@`o1T18>3C`?5as^*}J^Cg;g4()_
z+S*<h3T9kz^xGQ7{o_D-<UGMML`R9v15dY}N+>AC(wRIy7|C5lCyU8-h<D78TccCI
z$C5o)sjbGz9cXo<$uN8VgSuU4Px3kmL7r%L78#`R??G%*;uYCFmkr+?I;Jku-Uav;
zEi~7lw<k5lZX(7*(E~Uqj&~R2xavk}t=lPBJ+>(lHmpS8zbr~t>Ve%If@X;30go!y
zu9E0qge<!<CUF=jR-1$Xo)a#Q_?B6))?Ky9F`9(}Eqv0K6vEK1ZevMiCh&N)YIq&P
zgswoU@EbinGKdh6M3gPIAQ#`XER|>+zrYWL9<3^i$;mx#DoyJyhil`MFpjVuNzhLZ
z0cVheH!U+FkEJRnFtW;cB*9maUP_j_gw(3@w>cWL?EY#dlYoq&eH(mHLfI-p*_Abk
z5$nxSH73kx%~3J@CIv#DL?hJI`m!?FFXBOu3aF|~<uY3YOPhpl)Il7CDolKNnZ;;?
zSWM8wjU=TsI&+RZOubToKb8v8fyF6AM6YMiL(qv&9_-|d#)tKUA0KUN53SPUsty+g
z9qx9cria9mYz<{21KmrAeqkuIWgwziUe&%z@)#094x}fm2N_0rdeRmfKShg~<dsre
zXX7kH?>i{X8q@-+FL`Vab|A&Exv9(%eo?{t0!KYm`+=k}qk@;3yIxkW#~L`?LoDWN
zPJ;|B28M15lG_rYHe(W%K|xkQt9pgNJDbzP!#lHXFM{sw$``q=x4MO9mu`s8zU$c~
zwJ2*)bJuODyWV;Y#Uj*o=z3>uRppl~;&qWuzK}aBk4wZ-OjoYG%Zjr7JuD{!k0=C;
zfszBz2-zLcWXdUX-{Mh<-+~XB^YZbUG#arPf{t>%TC5IfizXmn!O|a6X_XT>x<S^B
zxUB%09)%vY+k&OfZ_Nr;TQ>>%hQtvBb3CE!Hun1j9y_E4wRIhQE%V9hB<aMp_AS+q
zPf&zE!r~8O3@%TpP)E^5yOLNJ_Ql51lA|DINr$~6cIuqA`7ciU7~uF8vh8ap!>Wv#
zz3^5Z?`A??ppR(VO|D_PhZ`=s^naYN8@Bq?X+KRJ$v4i;2~|&SV1g<P->}7WC%x`=
z311;HMuKd6z;?UWYHPTc?}ixjPWM}D+_l3kv!D#ywxgdiXLE~qy%J(8*>75BXP$;F
zcE5Q_Lb_0R{00CUMOzFZ4<F#xFs-(()c$|g-UYm}tGe@C=iDRdNTsSeQpsicy(P=G
zTp0WMMGP3&QVAo#fosQ3+yuzA<2a7<m?D5<5*xN;*%sgiL7Y$~5Uw4Pt~fNQ&PQf|
z(BxEMzNuu~Jr!biDw$+j;d4A5kJD3OFmVzB^ZV~}uS!)e>0bKlCEauOW9_xqUi-QB
z>(Jv>;AA+Hy&Fx>dAiG4)anXCL30Toe~b=-)z(FBdjT@PpJ@TqR?<V#qEodtW#Orx
zaCYYV;dk55=DvArlDLKKDMzYO^TORxeUwN+HU@1wLTznac9;<9C*00hEG<&7A3M7$
zp<x8YD|>B1B7uZaHzQ7KP7g7@K?NGY(kfZ@%wW0xumy+1<}k=Q|I-Ug>BtraNxQu@
ze{F}Nbk|&(xn@aSUO2}tl1g4?`z&!!^d)v+I1Q-eT5Zio4xSmf`~yxd{4vXZ^in3M
zpGYR$U%sr!_x=jZ2PpKj5O!Cvl~7(__wT$Jey5oB+ng<YS?6wksV}$R{m4p&+UjQZ
z4y<Ks3;)HPExvF2&&hH)?am&^sTKR(UF<2kF|jw@HqHFtDQdc%yRnb^WT~<3)z&KW
zb;>a)Ba{n;io@Gp>@&W}V&TDQ_iN`VX{fDJ_-+nw3*phfTrxMl$81K@NUJP$3MS=H
zf>{0bKpdm6IV?uY#j+P5riaN-P@GV-Y@eO}<3*!*D#6+XTEvJhnoDi<zkL<S<l0!m
zHNJHvr9^2XC1W~I*PmYD3_a2<8%d2P?4C$k8QOBP_XDWUNAC^)$G<zJC^cYz{Nv0m
zUGXZYVF?N2D~drwoZ0;&gGK%08KZ?R(8`>v|KsT63zzZLqW6G4h1v=M!8AYbLXkW;
z+t|&dA5$OEz1w47>QGygEPS1kZ|8ZDsolr|#B(dfn14+XB7q>a^=b{3+TfzgG%{aJ
ze9^ijI(z%nbw-Kk3PtuQK546gW+<y%Tw}Iur-%EYA{pgs1<~hnI9Nk@0*~eEnG)FL
zOO>_maJ9sL+U%S6p`~!LMA>RDrbT~pHJ$b<wvrJbn-svh+=4aU5nYB@Nv2JxSy`S#
zoBASnhn1(G=8b`ohTG;ZjMn89bDXSe=&K(^K1Kezkq~`0f3$qEkHUQDhq)zn*bW%0
zt;a(FT}z~1_C92ac}0kM0<Dc>Ngfp3T0Yug^Ee#?73Ff$_t~V}X7mt&b^>MH5HhDW
zfkr-Ka(B=P?^v!>YYUCGo0n%BT&Kv)dAY!vxXU3_+4R~B!lU?lsW*&K3P*|&C7Bpw
z7Xu;}VHu3zFsAbL_e-Q0>IwqHp{j31GiTuyG;T#<s;hE?&~=z-X?*rU(7VA+LhwX)
zu#Xpc8tTUf2`$FTi(;lbu@1_jNC@3kHAl(g|2S}HryYDee3OS#s+fSPp;?JUrYon7
zpELH`@{G+r5l_k@S{1ZS!}O&mBx4!*1=oqvmKgk|I?EB6J(1xKxwUsuXiYKZ6ERc#
z`%!6N_*N+7Dj9qS!h&XTz1V>sxU(}}@o5&sMM}loF0Nc8`B@r=yL1!{%5&v8#p&<B
z#tC1gVG1*%5$#QZ2+*CU(7q>$2gtlqz8;q68KA}i#o_hN8=1Xi5;=#Uh9QBU6E}bg
zTojq!Ej<{!+Z-?F>(S~0ucf@n5KwlQ3DyoQ`v&l#0HTV5c27&euAspya7Bo0K0C1)
zg3GChUOj|V0ZXBY3rijAhHqpYqGyoijU+2^JH|fdNW~I)K?_^KBXp8%V}p_NEXy?T
zCR7E3R+?BXWi6yv-NCWcv6|N?Ag`QZo`Rlb8NTalgMz#i98Sli<^wXXX3o~5DtamF
zVZGx?&0cJnqITYqftYqF^mz=30`ZWTii&5jrY<u?7nz)XW9Z*43;<08&=R`nZ3-oe
z98eD+T`JMm*JCSMDpQ<qUGFZlj}8cr3_b=LLwJ?9E<lZgIEe9;jmzR9(Q}&_Lz94A
zv;_n0vR3wUv6mtMgfB>FF{tG`VmciTc&lJEL~YQMA~}lLVs+f+v&t%`jUXGPWimg>
zF~vFLw^Xw|7Uk*NA!ZtRuyVKGx##|nO8lFGimyKfl*eH9u+-=~G%i5myYeUFYU^6?
z%c9Bikqf0l>Cm))W5nFPU%=t-W25EG?dWVU6Ve92nX^`N90`7N&N92^cq~7H*jX3S
zhZj%q`PM?)0Tt*N?6+Ay<n5e4=5$h1kW#st;Fr&~{NHU^8j8g!SlCGoyY4>xw;P*;
zlW<yc6<DjZdSMs2^PL&9?@B6Fv>fK^vkM)4FHZhu0?~l(CNGr{%lTw-bkVZ#2J+q|
z_vPtUBgZy}z|1RmzvpR-WZ!%9jtBGAE#fmV7oUvrN(L{h@Nl{K=moAPTXm_+0&43Z
ztF4YeO;5KWwUt)6B^}(JxH~&dKDO}DYVg3Y-`VPNUp{&1cE*0+ULgIzuMYAdMHw~&
zAM)&SYS-bTmW1@w=C*eJc>*;ad(DDY&*rN|GF%+Lx>ETdmpysj#%|rX?Ip-EJe_%W
zV}fX8+YIuAPe-s_MysvYzKiyD{PZd4rgK-O#=Rd4eGA(;@_4s1ckRDSvVpX=QcI@C
z^86=RN&X(<OkbCOkg^!Q{K${;p=+171@akNxX4@LCx?n=f8pj~K8X2{HFLXpYGyo^
zp3NAOA1bh=zsEHk)1I~9W(|>q=&omY{I0~;TglKv|MWU1*KV+4*ReP9gU?wgZ-dg}
zS-}xxqD<1!(`Z-oJuXVJ8CP5JDHoB+kG>AnUq36gtG*S&!H3RC^Qk{7t1Z5L+q%Vw
zf02g_#1U3oS5e|aHaiv+%<<DVEn*JM?x!iHglM_kFW^IKNP)YJ4D6tI9O7)sC~E7t
zEStg-F+aahE;<snG-2t~@)lErHhKn27|+nTk{4QS<xafcbPcVxcGT9fD0HIr`3-5K
zY{BC1(F->MJ?VE(ZAjPk^^y&w?_Op?sJYPcH$dt`XBBP?y4@jJaE*}q^1ualAae-f
zxumr|R8d}=7HkqeTzs!D?cUo+7u|;v<4>Ut{rXa#`>mCJ^FnQ@c&=_^{y&C_e4zA2
z(-%HW%gwfs>EgX)_>(kLr|fXIOp^uG{2_Y)eMH>kalgh_HTxY_TeDEo=FUwW!!Fy+
zOn6aKd=<>`a!E8_zQ81`HX62}56=3+t}vfu9jA@oeQp=Js-|&DI`5fZ@<JV6sfAC`
zrA+6mih?$^ZdYQsnqT9G8)K#9cpJ$l+D~xjQm`B6ef%UFyI_{>#w2Tka;9HJoyk5)
zN7hWH>@nA>mD?y6>Z&B1O#wA1X|YJP{|&a~swcRl^tx+Qq6Jl|8Gbk-4wUdLI&by>
zD+2XFA*6K%@`^{uy~?rCVKm~K3N+O*Fk2k!Q#ywW8KiMWGrCNroS}0fw;6=xfOnn=
z$1AkPeHhv>hduI=gpSkNTcq*zm866xhe)X-fXeM8PewJ$6Tl&*m11@chwoEa@K%wD
zu{-+)zBKEpuVc7{pXVotay|sx?Rgr@R={(=%aWdF<qQn(M2QFP&<#8{2L+;Vdp?_$
z5^&JPL>?C=<o_#cW_a{FP<n%w&{Y1#@(?`(FB5BP6q=-JPOjXkl9YJD@o<*anzJJu
z-<+kjmJXm~*k_%dn?kw}NCqfgL6TV^%PNo*Gpu+FE<~60k4$)RN)cBtpC;H@s_|`C
zh{bIh{4^~=UgW0)Hx(hNC(4<MjiwDZ(!}xMUDQ^Xa7!6^rpqimkpq1T-t<j5zORfu
zIgC@<4;A3iMf925(R!SRnDhfCT)IIZNzM(9f=7UmX5OC=Bujss&qv`nvm~Co0%U-~
z=}8Kzl$w``3&Hg2M}RRgvH*UfddJc%c~*1TzUFOGJ{nnf1$x5y0}TEh@i#iuD~4yY
zk`}ih+9<<C(HahxiFlA@+(z`)PtY(88}F|yn?I*P?5mo@WlB_&$SWwSs7YMMC7^_<
ztW3$_^#~*49uPw2*R`rrTj|*SP|ei33>A;V^|k$esMSYrEnmlPb8wnRFY*h)e%x26
zl<MQbwXGdSkM}*%7Al7<$yjZrT<x^e^OWre6S%u>B$OS@D7xKBGM1T_FjG-~$ur<G
z>(xqmOboZzL6G@a-HTT8aH+`T(FVHob^+|T{6O!ZMhOz0P~sitt3_hfmkMZv*0^xF
zwM@}_I73pt^3f?#Puu2LSzJ)(r@{fQb$XOIKM@1AiEi-9bC#57^j_la6eG=+-Ds<}
znEL(xGd{Y=bwgOog?+4K9EPXx%XG<UGuby_*3!`OC^IeW)~&`5tLHh9@~l7d(uhJZ
z|4B0RwlpoixGi(+--S#UP_&I#quhO-0^K~{iI!IwHVL;H=LF7y;}O-?%afzF%KBLA
zEU@n4qkj?YN?Lq4tIOgn@q?=qGHwn*t;;He%WEA<PXE}rU4|h-Vf%MS!}W1XFvi;l
z&m0Z&Y#R<KainRjxIQBMb8#?tTh!_UwJHCT;Xk4&%_L8z)7#U-_T%B>_MRE*^DeQ~
z{k2j1&6%vLKmyU_9Mu~VXUT2W%=7W6>&_!t$<r_2VfK^XW{dj&7q^co?k*q(i*M1>
zptf=sX&#m`KO0EoE3or*M>L-Y@OW)nDKJEm$4$c7Ycq3%4Ub%c)4N&7oIls%R};EK
zSb5i8W8tdLF_%@R1VP>795;~8e%tJe-}<0ERN}Gp$`GRswR2LwNvL{a;pPW!419M%
zQz=xQ;hSe|;%HaVfeN^zv<xh-rSrEEUDEI5sA_oI5qc7cERm9GFgH0|3xlXMn#60)
zB@d9b#J%#p!~(bCGHRtaWSp@yvAt+s=ySW{LtBdUn%`t3_1Ba_%Zfas`u@)UUQ_km
z9KvksAH8#e?=ztt4!%3sp)A$JK}=Lo*k}HhwZGOvZVy)--sbcaAz^*~K9&uBS|8Rr
z6PKdp%5(SC&iGLhh_yU48)uNz%34^a>PQY2i^DVY$KO1qy3()yp>tO(`F!*g!p5K`
zO{(Wb|7CbeUk8b_KzID=BrW^Yor8U=<pmt}grB&`OCD!X4(!(TVwp2g@V(3^?Rr+!
z_y589Si3;LA6?YNX^y#jY+RrIb4J^MNBwy`czdm_$|e8e_me)kq}yH{><<f0tuAa2
z`S5p6u>(073Q9Qgee>lCrSF>8IBPvUV^{w9@298dy9X20RzH%~{T%9WqkFcd-s&&Z
z?C`;Xd^r26C2>zOaj!vZd&AG%!+gcgdsWQ304)*_7VW+65A5r-EREl%FyizAzh|q`
zV)kX^2?V5R_SA(8QGkj#J28g#{8S|v|J!MnE^Z;qx`CoCx$(37L!@@}1Z?Imw|b_4
z?5`%MCjGE;HLcxhRhYE5#w!~tXe?#PU3*eZ@s%C74d0RNt5GVUMc1)duT7`(eKEPr
z3VtW7#*pQ(c?`i?yOKHvPsfB-S%y{u%Xx7nZbMfDo;JSleLph1pKfvAO@S|@KsKb7
zmQA{f$2=q9sq{hi{<cM>5F0?FAPLi9Av<(|OIntGkW@B1xKLejSkTRMgIeUS<G1;H
z+MF1wnj>=`%rG94b|lszkVe&}ZG#zAR4F@D1a>!#paG~U>kgeFM;CHDJ{}qvJ4k%!
z7#V71kPZDt%&i6DKA~t09UU^-Hhe%lxgz1CTGhoiOkq~2o{>_r)DBj~P+E{{1-H{W
zN7Nf=Jdo5-XFF?v`)q~8>t_A6_L0gAu;o97Y00uFghlS$Ev3FhMT=pp*=i?5l`qBe
z<Ec$5v7zJ9_3fxMLYj)*)s&2pAsK*R$C|iwov!2XD-v$E3CfwdeoM%Yj9(9MDTlW2
zOWXtztwj}c=rYSfNJ!yuh?!e7RZlthK$cKa`*{*u5!;#J5bD@Lj6Yu8AaOJ=5YYTb
zmF6mh`pvyE1|sz`tPONZvkB`DMm-Hwn0ADjP--n}jN4%Hq!mMKikiKF@kgtM6tu^5
zj<R4hfUXzbGR9*w$r&7#Jwm9tjGfa;FQABm3{=z}A++&4r47iuQQ0W><ekUta0B|i
zi|+t^MdG4WAwt3fwY4w0utvxEW#rQhLL1=#@3jgcH<1&Rokh8hL(JpoRdd0_L<HqA
za)XUM#lAJ%w&zP;xjDt4qZXu>Z@*xf$Gj8wm=cA!#mLr6F$8lBIe3smR#Q5GRXy4e
zh6yO=AcmA~Ew?U~jJSNiXG0l*R}!0U;j=m94h9Mzk#0uza2VPlDn~BDiMi}h27Aw5
zB@-S*f;sP;f>BU8LLycH@1r3S#+o5bC--&(=$%3Xq@%rgI$C>q_%$SnrVXNl>a1ra
zcuZkMb^)1Dfrm3?i*bKOZ{UR%2}7D@CUmMmQyvjuBPiN6@O+adRJNea5XWGdJ2(76
z3n3OwI;5hBXE=rcf9oxqm=}NebVN=G;nD)jmOAq7glH_@5-f_pF>tKY?fAar?J5_S
zv}~%ct+wt-+^sok>u^+CLC6okr5$i@l4&A*IK4{&FAo&n5lh1OOjKKK{~4K;@1?SL
z1E;jJbeSCmGn|^tbpq5`t3~m(`#-->4o7Xd<Fm><U4$=hV@O6=G8ffr)coHfjG@$Z
z+N@51lf3DlquOd8CI0Kuj0<L>tO7=*<T}FmgdrI#$$=e)G^W6E9HNyUrt=}fz9)_m
z=Bn<&VoP|3BRIZ`Y5GW5wk7MIu`A{ryJ@b@d{Wfh@rB`7_+zF~LLGU%<*i-F;}+b9
zDz!CYkW&9ViBt)`{W1()LHtlM{ptI1zZbRDqqgen!}DRcOQPBe!r_JOSxcB&o3e$^
zSSzZnag*iInh(FHbu^T{vd+%pH@wZaYr`gyLo83v;mpO0S@`vGzz0zW*n?T1_<9@v
zT(FgLK%Ht;aKqQWoChiB&Hbay=zhkoqlWlU{2J>Im|DifohWPuo`NuObb%zm@EdPU
zvp4ygr*XBp2^(c?wK{k)csBz;(&pTMx*!&wk#Xi{-nNQx(*0h`cee&)A31A2HdBO&
zw~`wE=e`ZC#qnaixHk#GWyOTfir(@!UHKv*SysRE!DQd`k8GKH{UI{Wr{szNSq5IM
z+s1ABQdV2DPd_5(9zfAnYAc5H>K3GOSJrYngB?Qfn?3#97TuE^<FIOJ8-6u~ZD;&z
zUtZ2|C>Qa6w%M47l9}rvA$&1(C@j7FJ<J^<FoRZ|{Nr?NsnynW=x(d89!0FEtvQm+
z_a52G5S(aH=t8*n;&3LMS@|q%UUt!7C=T1X*t<jHd0O6bfWhG(5anZiDuP4b9JMP@
zTR9sEeD*OOO54a^PpD{F?eXs?F6xo=OQ)atouVvPY8gWz2)t0MNo`Hv@*3vU|CFue
z3xn2|zo}+(Y!aS=`DFYVAH?eBz|7HQ-``OzUOM2iTgP2;UPSk?yeJ~uw|jYh_8v6L
zF-~hl&z>Idb>n?spKs-j?IClB_yxi~dsPhDv}Luu9axpRLvfGbZW(m;g#qdd9Mpa(
zo#P#3=?-5!b&9VcrSY?lZEUYK&9tl`)w6N>Z1RZI)|3THpIkTCNMf{iQS5FXn5u$M
zeOU0dzJ#fx-e4CJBME%sxzQ+h*+CVkJsM<xCqRolZhc543~(273Q4G~?e1WD7o4SE
z#`(&?Jrx8JN<f`U_HUVPwr*-YGW$~t4aRzQMVN%=C#dN#pV^nR9lQ$=s)gpA*r8-0
zZz=r|oSvyFi5%w8A3H+<dGrFVLQ?jP6?PG?P`Q|SQW(u8&lc?r(I11ni8(rWDQZ6e
z46~3z7{>J{6h9xQJE#t^ITs3@o%PQO7jUF4M3Wv$a2$;4-4)op?N@}AS<6pL(WDL1
z&fX+;pwXjhm2Abl$Ifi9o}CzP0xw^een-fDl;4=k_raMKFIwgaA*|)Vqs4D?DCY?k
zswvBt6woUEqD4~kN1)?2r?t*kYs+42h`8A-zs&KdU^s-1v3etewnME+Kd24>2y1DN
z)-DgpVSiH01&TtejZ14Bg&}PtT^hC-NBN?!=fU{AjCUVMrKww*Du}P9P%zbebdckw
za1&f6V^-a5;WH=z4chsH@BwoudF<wg^n5(q>W^67=jhLI8_hz(mhmLa3B&rWnPu7%
zi>lf0<l@MhKr@e<#F*Pi&CkoDD_ma-zEszC;3TMC5)etGmKpNs6&lK$N;FB#rA0z6
zRt}P62i!18pX}I<e=Apdg^UbzrLc)39p_E<cECjrWW%rmYUucoffzX?-F7IY4~&&y
z^p@5@I4AiqX*AFNMw^lYe+qwI&O-5w{OZIUcn2olr<&#_6|Fm+SqabpA7_uC(?}$c
zx@wpgXQL#m<ekxb$3#Gv4^wo50+B*locX5hqr4msfo!!4qg&{H#<UX_2D0>enj2Uw
z($tw4aUI{zd%k0E2zmqPo`PcmM`G!aZXG(g)b@0;-+B!51QUh8SK`IPSDpx@N9aVB
z#X%M+1}bVL#Ns@coV<!!8~T;clmV7&Di`k?ol4L`ZFN|v3`G_!)EEM+eH6mx;S1lc
zkj#?gpxk^&X<rYDa&Yk$Wh~i*+Pbk|)(4B`eIqu_(4%0rwG{WQesrjD6+Xx{tIZsF
z%uN;qZ_=`-z{m5S3}h%5)S<F=B1>{UIgEK-r+3sl-MrLUxfN9(PIJ|KG||Sht!x-@
z&bC)kT8R?q{|FR8<5b512MjlGz_AB#8ZG7JaL{V&ltw(HX}CPgqDRBMwfIz(w#!ix
zR~Jl&tR7CE><^?(N2+FAc62g;&EreN_weB2zX|uGb^FESp|p9bPyLNlirNf&HwKbr
z5Spm1eyFQh@?s$y=fi7uiDjs*^MtIRAg+W2qqZg<r>rNnRbdsUR$Fx?Qzo_5&h>u(
z1D1Bw)|L9H?i7+=9p7fvEYU{V7LBIo{AY?5n5y+CJDQ4!c88(wc`cH8odQL3$vr{h
zPb+adw8&c@;K<%<+28|jPO2u6pbqV3zx`R1KrG>ds9-k?+i3HXY@EiS8>H^&y%s-R
zzkHLqvXv&JYw+pMTg@HaUE00d(qfRbl}lgpjq{Hp&zrXu?xH(GKC^nSOAfxyN?2ZA
zNYA!~Q(m1V?my4i!o+s(r{9;`t@~>u1#5)6Ru&TXv2q{|fYO`)CJBY>#uo*5&+zNB
z33gyF{Rs_-ZwHtn$wB7ZZgS>$r=Lz-tV43#6ky(l-j@u`+*YLh>6r{xkRsPUWvBJ$
z)0$;i%Pwu3Eoazhk1VR?^2%jkOzOKeU+A+-rF3o@UB`1b+(VtyxwTGv78wtJe(|JD
z-{!1&;HT*tSW4Z&UTWP06{Bscja$oOR$CjtJQ%Ea(t2ts@|#v|6}2_k+&!6ZQV~)_
znC_qqJ<m|$j{eqIAG&c$65c-gf7Mj9_`u$)CtIukbtcRHX<Hum4;;9isfjn89g6x=
z77nAfp8DVviqDb6tsK~9L31^CND2}JYHRF=JIUVQ-Lm4J7_ME<uHIY6N2Q!I)(C6J
z&3#{Mo5#)&)n4Jfg$rL#OTPTLuoQgZ`zDOju?;>>3x%T{DpzCp!j87B*>BfyA`}-E
zA!)2otX^+YI@Mcthi7+8=zhCNDR_bqpFE}+ri4$!{9mDe1adR(tyxv+6Z{fuRz#wj
zOC!9L_1#pnT}-|80)fv9F9kKk3G--$`8Nke9FmYF-wAWWH}oY9>BiF#^Y$*6RF@3=
zGTqWI)q>r<g=nQvzwHXf<>%92Buw(N+FBHpFMEE*toc#AK?&}oElj|dbl+Zg=yO+{
zGL^jj0>7oTn}PaW$3kQnsi3(>0!>Ll4n2a)f=YqvxAW`6`G6D2icc>b{UQk2%apAU
zN~4$s5-=B?<lF_uMAU=CU~L_6)p~XZ9$GS)l@draVrbDtB&HKb(#R*WqnSZliB!Z)
zFW}o@E6&@+p&b|v^kWGg!{bmQLEO(2qjr8d;fha6t`J#lVYL+l-@u@1qWO4L`Oo13
zw`$5<J_El>o<?Q9<%GQ%1ckIYP>Qk3D@0elh(QL1V_t6&Dn++f2oaI?*ZkOusvbPI
zfp0TbCg?eo)TItxB`^=HZ>9KSj>}TKdW7i{@w^=B(Y2o0Fyy95P@H9vpaovZyuwnC
z7`T5Mi@?{Mi-xWbI=Ym-z-kv);JTpzPBRf{kaptiDFhj5TY?Wgyp`q|S_LI8cL7&0
z__OigDSXQ$e-YI+Px@_o_EIYzSpa2t7(FDmS~Z_3L>CA#Zd21(8j~;mRSq5(DoJeV
zO}H-{=eoJ2p;SZ|w9KF?SVW3I+oq(zFuy?(c6+;otC*4g_K!U75kOo(U{&Ss&>}3d
zW-L=toW!h>T0tf3S~Ht&JMi+AF)$h1HdYQBJcB8f6`?5w$Vdvz&ss)v+T^yrRuiK0
zbzA|*oIlQ(#1#;<cQ*By5K_9lkkk_`m-{&!I4SEG%2q4|WX3M%BCO+8p*8>yX|C8A
zl!%*<(mtQ#px<Vv#1#A_CwLu)ccLYu3^$h=3Pq8bhIt3dB0o>FG?!uMh!^!1n*j7m
zNI@>n_Gc!s^#(zA_YJS%H`}2U6A@^B&PS*Dw#VAb$68QX{UAKd#OT-jH!&cUYHNDn
zon9fH+rXX3`TfK=$@o4dqA_OUi}Iu)R&93E_@sx#UM%Jbr~TFTQlG<3NTGn?kWtem
zCUn?X6n3{bdX{4D0=aTEe*SW@rHLklEeglrYq!umFOE*MP+NZh*mrJJTT^WkuDO+T
ztY(K=G%xl<mQS;JvVv8m`4WD2IUX7<?bYqDmyo}=VOi1So<<Zsz;t<!P1tAqg4EXB
zz9MlMI%#@sc$iDA7%fd-F)&rt{nexz$gqERA(_^A1e6GkzRBEAA;#skS%kLF$zRhj
zOq))6QZ@-|b`Qu<TfOaPemy)_oK8yoxLwT*VQU8Q{yxO-@{MG5hoeAHr~lb-B^$$Q
z=^kbWQy0$imfUNtAvOtndv(#Y)}$rP^IOBKe`J$GX)@T$w9tj=*jrboTSNH}YOAH$
zphR5(<;9*D4%XDVA8M;>yKnvymmRe=mD;*w&i^!|quTlmvR>H6tyo}bhwT*$Z)GPZ
zBX~5*EUv$f;UY~XEuY;{c+P)r9$n?@{lJZB`Ks?0gJ>IE82sAkj3yOkSZ!^LKYMNx
z+&S@cOL4G|N|Quo>$xxN$XTpo2tlL|Jxn`y1wG<<t-h*Ubcwsg!e1dhdmn16l{U0&
z<_)!Vp?PG%vVXsY(ayU=rti~FuI`~?ph=yj)RwCcSaHoeDZ1YqK|m;7V^>&f>bfl!
zCbp;c#)Dky^w5^f?tP83`eAD<pcv)f{^KHRjWg<2#&m-{&#@!yN4EHuR$E#4Tf+}B
zvD*4*{e|=9*(B^I*St0}D9-$SN$PJ4%UrGzgzLUWww}?St1UPG#(^RZiqtObm3PdA
zSRBwO_mYBmw{Y|Dm9Bj1Y$uGaus`9Z_|M&$_%)@N7@b*b<!k3K4}>ItIO?;gtvYt9
z71AuOwu<uZ&&7h|%WGNb{BnQpIP`K%4x7b2_9FERTBpq2<FfNxtc`-*PD!bc5oJ=q
zqsvVz$!x$}4!dL;J+cU2-$v(fcN_pSNB9|zzb^5`oRxuaa1MUma`L!FcW!yU=9*22
zif;Y+&{H|L;>fa<2L>ilTcJV72vu0mYHMwIw!v6xXDt=k9^t)o5npE}vw=*_F7#*J
zo7%IT_Webgx%F^twUvfAbmkAuex3$vdS`E`urHrFmH2mM3sQ=YV{~Pwlji55J{tz?
zChfD;S9UTro`U4rE%_Kj0B?_R_6@bQv!yEfZvMEM;LwuVTB)ZMdO}K;l#(0D;fkG?
zyXJ(-F>rgz*%ZbYEjGielTqH;<FSFsr=_;$)7wCq#8==ZDLVCP8qDlYn6KP7d(!TI
z761Lz@z(B^FdK@5G!vN&&d3BmB~tzTdIGU8eR^KliwxcM7QHt3<C>8`1?u?lmb~TS
z8Gn<d!x~$52Ncp-F-xo!bPNnmpy#4vn}r}t>gqfLPL4=AWyg)mvE;FyC9E3*)P0Lh
zfsi;>k+2jgHFt$@6{Shk);5u*DTM&HJ9Nq*%1$5UDYSIi28~RPX6uC$0Vm&-iB!e)
z=;*r1qs0_VOk9lJSD2mn<Eq1QEA<^2Ro*>3eP|;E=dzC3S_X_)(aA{6{2ae_1T~k+
znEB{Z>YCLap>DHbISC$tMVW<8IEJT080g?EnKJV#H`@D|W5Nhz9G&OoVyb0g@0DYJ
zQ!l_|VH~PP!f@UsP)tjWK9S|Vbg@k(^m8rTek@MEiGCPmNIWm!Sm@_uN^xc5+&506
zvnpU9;O3TK(hbLPK8+?>-&;9nXE&5rtc1q#;0=m1xHb6s<NZ!<TOmmxYHlQ!(j@R!
zP0-IP!5WG<1m_`bL*5HrM?0F;T@E?+=%R@q<V=3x-wjsMU?9c`8I&nYBXz=$6?pKu
z1H6bfM2{^@>5Nl#@JUS*c1~O-b{<<eVvL|#hN&xD2!3Wk>B%4v8IFOJHs!X5rx15H
z(Y@Ok@pwCsM%3YeMbm&OtEbbJkOHxp_==hn1xS0BvLZa?v9_T{&Lr@4FfW!WxHZri
z$f#at+MwSReopKgHvustBK*Q8Vwi-or%ef7@>S)K)PlUmus9i_OUl@N45L%i&B+9t
z4)W^;L@PwE56h=c;&m~I)ID+;53e#5BgukTL>U1G?>^@U>);I6isb@{_X6ck3I<m@
zWPv701p``2MNEkZ;DG?A<ib!x#IsOTBJHb_HXMAyBlW5|<RZF0i=Q5p45=5Bb|@rN
zH=1DefzVAu0!nvKbbg(16-x)s#IPz0{jOc5WOoG^xC*2)@wusW-=h$)D4kan%9sim
zlt<t?7CfCIVH3Rt{;;=Q<fana3lOakJ%8<JLky;9HTuR`c{WNUB$(ww{;XIfY9dKA
z_2XbUW^2A5`~Z4Czs;dE5Xphe`do`p2^06wRTO3D^BJ|jUs0r-6Il)+#p@z|xCEjt
zq<uC$4ha`HFq*7NQ$N+8bvH+&YZL17n_y%bt#aqoN-65yIa^gb5i)4Gx+6MhCCKQ%
z8&pucK<MO_6Jm{@0+sw?3XuLf7fH$S>jG7@PFSL@6g2q>Bm*ZyCt8{R2LU8IRQ*Xv
zDs8dfl%Er-T#kouy!C&SO>Auly{y)55O^Kka2yH+$J8KukMjsWN4ENyFRE~P-~mE>
z#Th?vdjl^-U*WbWqLoPz$YYkhMzP4WoeT9*4vVfrs7!62AM7R0gMzeUkKF3fC&vn6
zou$?)qL+foaSsp)_ki~jl(5bva=<VTnLCyh@KRoM1->#+$u2aNScM?nG1C&vdDWlj
z9%V();1@LXrKi&bW^_ry`QWh!mG%v<zV<*9&yAsuSL}&>ptpjwXaOy$^L=FCG!2ng
zq`RPd7zCnaKxILZu#XHzr#-GpCcY{i;<pRbyb$}0Nrjk3EP#eljz3_Cs0$4`=dk<e
zLj08JB<Ne}8J-T#xa7U+>p_tU%%WC^*eO9k$rjU4m37BFRZpB5Z7_&aM3%cqt1S}P
zH6nF>5d-90z}_qPpa#b~egskOF7p$YYL`?=+aMWM&TWSlWy#6Bz%RdrNB6FTHe85S
zYj!ROl`X<_lb5S`KImN)BW<*1uBH>|wjdK-UV<yS1wfyteCY+eZi*zM02f<Xk@48n
z#|DR)!zOLu!iZ5^?8Aw(QM!qwX#ti!PC$S{s+3Yfi-QC@U#?9(K=EqJ13yq4f8C)U
zTDm|l1jeb*(qQaZII1Y6N+rdv=}zkyMnM4E4JltFB$B)#iZw_s>=*-vAlwM9dZki=
zOwm>nt6aN29hVxYi9a4lp3*b7(D4ynV6pwK;)tH!Y$6&IrZ?pf#5SEgb66^1&R*Hf
z3WF!<6|58MbT(JHjTHn|ma%6JIbg0eAb5}q%qLp7Aco16f-NPO<A}jG)OopR-SmM>
z{e)^35@e`OsN+PLeV7G)yCfa+XH^AyQ(|kLt+!A$1~`YubTe>6L(2qjZg<t?m0Bb_
z0h-Ys-oWepWI?lTt{f&6w{6fNoe-QgAaCg|CgSX!g+I>ot{F??{NX#1(i2&GbL`Kw
zSy+7)J$nP0*O5V(C*;TY)z7Ua3XUW6Qj4>>D~lOcXDBu=Z)7jhPYa2xvGVK%bH7Ed
zu1?VGJz<m6H~bXYq;IV^YBUDp>3I5N`Z$-r5coqWXC~m`u*%Y%=xAfCR)~^4KbvMu
zk+a0)Q|_m+p=VDIYooA;aq>rzy6tmJVAAq@h$veZs*$e%DcBU#r_-!Dj2)_*Z@X{)
zf;;nv*nh-|&qT56gq{2b>g>MrXwYSQfG^L%^n8#-kvJKY49%I_gZCtkgLHcxI}){!
zQ_8n1XfD6`r{~g9Yc9V+S3{wxbiexS1yq7K$scS%p4&b!8KVtfdsE1k|7C`gbu5>p
zH;yz8leJ-QU$$J)*!1Z`^8!n=_mhN=C87R4&Y*!`94_pko7suB^y-}3OVOQoJd;{E
zJv>(~z0%vBBQqAZ?8-lO(Vf}y>YLw8OZI9e85fE6+jIu^Uu}<k;W?Ou`C^y};Gg*-
z4Y@W?7B4zmdCx$4a8sTt&rlvXhZ6((b|g7ym&fLy@=7VSe|7T~E1%=g)qC!*N@7=%
zF`u69<64+UXu<bb>JxUBo@@CMg4h1H&Mv<xeJ7%MkXC?Ph>EyfySL^>I{C7sQW}>(
zy2c5@w%_xju0^t#m0|-)aq;N~NXCml6r*L4jCv*4P9!QwZrc@Y&L$XE96B#GFO(jj
z@#g(M;w19nl|yO1<k<@gs9?{ovf7FVcLK@fZgb7&1}Hb@P@+TDT)gLkWJ~|6^Sb-~
z?lAjjr?aO13+4|T>E{k%TAUyG7Mr$LIJ7zZN2%Rfyuq^T&Pv_5cj5N&-HM_s#C5D%
z|0nX+%FQ_&z}NK<2zx1PV}$DOi_K`gE3pnj^5jfoZ08oL?L9@4=a%<!<xuz}>Aj1N
zyrj8{@C47t$7Z7WTApK_H5LulIH^bxDAjuR0^xOD)O`Z=8ml4=qK)CgO)Fvc8&$NK
zHfmI^^bpao$^d!w?Aal4#!bhgtv&zNZm4j2c!qssWRtEq>|^ZIQdw%lQO03-%*LIR
z@blU5g0=W?l5OLPA8&uX)kc@!mOMWDfxN|M8<Wg_j7<MIn>eMsxW(o|U)Z1Y`NVIt
z#*Af$`M#z-PM_w|=d&zIrxVWxZ_hfG&q_*j_=pFGdw|!0T#VV79&2hlWPpb6&}r1-
zAlNaOf5~iS+N7$wb|^SdTvQw%3w`D6n11OAxC)s%4{EH9#|5EfbdjI-@JXI)v(|B2
zWfjLT?j1G23#l6rokqF^Q3m@N#y6Cx7}45zOQqHN$x!y;XE9l+k_o<x&jjI6{DY?!
zD|+}U)a@kW47ye_0%ox}mX}4jES$J~C3>CsSV*CR-sL}{aQsSsYvAE|NGa`P(wa{f
z1I$zacd=fSa)C<52!6Ek62qO#aw-=RmNY?$QfB!hD=YWz&l0r>@l`i>2FQ5KY84K#
z-i3!}xg<C|G-D?Sv8_x9Wd}9iDeak$^2KzfIJVJ*x-pP~wHEt$wSG9H)<iY+>_5%|
zRJ~&45r{e%HS^#BeT$*r(?#G!Zh{m>lG|Y$fjbDN;v*aEw-uoXa^}w_vaGUf_N=p9
zWsnMmtD44{m@oyAA}w}|_A_N*ilt}p0n{W?ob#SmBaoF+k1<J->mlahdWXvF)yv-k
z{!6`1;?jhAMtp9aUnKl<IP~MenoUd$Ej@3E$@8<}VCfw)2-3))F-08tuN*ghO2V$f
zpoCg3h1~Pg{>^q?I7}Uw#Lz+rYDR^zoYh(x%XhW0fGy`YN;l8^1P?6;dEQx#deM;?
zYU>8#0&_hi=Dij*eMn++msXzfwHu{+eDQyVx;DujsPcV%;0?@LEA-5kJgu?*ypRHa
z+z%uQl#tCpEm5OF2r>Dg&CzCo<hS(r$p{C0TKvfM6Cm=1n}k_`ukPxnCeb2x9D99p
zj2~15Qwqd$oAJClu+}tfasUQxoRZ}o#;Kq%0iRMq36vh@2io|)N%Iw%#9Cxb$QOk=
zWKG|e4%UrfcmT4{QMw(Bc#n~kvdrnG7p8_$dh*s=DdG%RdxsW9(KC)U)Yg1C??-Lr
zs`i;E!Wti5bRANQi4-|N!gX=*!TJ9Pi9b7QaM;XM)-KPPzaI)ZaWQP~jP+46ssMd9
zo{3|$#O(v=O67WayDs@x;eA)dL(QME+{{p0ryEmM%TnQP@@$@u=T}nC?6zmyi^FC~
zolZ0!+WQJ!^$pW?L*Z=o?R&#=#zvSa)K;_Aj2WOCs5GtngKMhdl37{9+mhW0k+JQ3
zZ|veCRnL-*XXx>J$RA0_eZtNUn7Y7F{l!l(Xt_KDsjbQ3OVmb*g4yr9KeZMz{@uQ<
zQ|?*R)++JQZ^K7W{=DhXy=Jc(=0dtvM~)SS+RCOivRdIZ$X6^umUvqz73vWhY0r)>
zXZL-{!#*cczIL`pGbo(8_O7t?F55M;da9`Bwxc30hNq>^vS|&?@9i#XetYqpUHVc`
zBo@A=O^$a{oE5`ur(1Y(9@qc7-|^}Wkztg>z}F3u%WBK9wvO(la+MD-ZeS;6^BuK7
zw3(GpZD%e77u43&e)6@{$U7}v-M>AZd6fEH9A<cQ;jn-3{;OTO|G9-n?Yv8}rTp3=
z@f>HI7-)>fsqwOYYA;<YN%;5uAw@fMsIA^UtQMpVDeu3$dD#L-7MI`CPk-MFP$ay2
z`V_NID=YWVFH`e}cL&S9Xi<`*xW~#F>5<2wfQ##O)a~|}9Z3_Hm;&91;$ci|bcIr~
z)j7i?s;w1%;I)EBQ&-5w5eZ*a%&uLfwh&1|w6;<o@E#O#7K#t=lG<wJoABug;ujjB
zbyM*l*a*s<NeVUiXY|cPlDzH5mi&=#q^*>+H4fZBodk8b_+DXq|Ic?Ye^0bik4;c-
zE=3^kFhBEl#>A+tjqw*~mYV~XXr5wfj1F*SZyLtGZ|U4>&3EVQqBJzQoAmsHXNK_=
zRJsKcw?5Q#_y|hpDHQX@waI#qP0fWpxzNnV?sYZ)nyf{>480d2w!W&0Ou0NRY*14T
zNTW=X|JLVF?SdRA$;61-Ivs6YAMKC$re#gVWDO?c=EA!=_OprpsA3zim<1`iadq2^
zirT)~i0wIE!|Mb*>3g)JXD4CWfe}UIV}o_n`1H&vwk_;r=t|lO&fulPMC-#JQ>;Fq
z4rx2WzLABE;o75V@d*O|!W(I%E_So6Z%#}O?H@?a2(L*8lSe<;P|;o~KU0ilFt71e
zHyC46`9U`|kWC=L`udtdvkspj@N)cUG~%<TM~D{^+s#5&-Qbm&m#u;-gE2?h%8h2w
zEo&so8HWl7FTdtpIc@q3X8c#nY87H9HKGzJO`1b^fEMJ|L-dtH?Dgw1bpp%033Sl3
z|G?Bob|7!C4Q>hVG`$|TfZ94ENw!q5$r+E9O;6f}%sjmia0*(`qvSmtY3SxCq6BSs
z+YZs-&=oT06FxP-cA`9VkgJ5-`LfGg!rDrQ`wr4ZZ@1o~P>vRU(JS=HDcogq$3n0z
z<BirdU%8xS&X-oSCXXR(Y;p{^8T@NO^~7`s+Ol@+k3zsRG(1L!O^{Z$t@QV~`~o7a
z#<OjY4PPuY1wyPPp%pO`=ck7Q^M_)k)>K~T7c5S=CAB7gHZW82Tu?!%^OH7nKDw@N
z+H%3>!kkM=^K_M84HPY~Wqge#1p3J7b^RnEPXZ(<(+p}%4|xzF%AW`QKJzw=+_LI0
zQ1|N!j>X^;XnKBRjZ|$Lb;Q9B2Yzb{IL*4HGjff9_{EErp|a=ME!3+<W!e1Mly}V~
zlk3o?Wxhr1*L*VAnKg{lw)ME-slu%{BTvy%i`uRATS<=e0Fsr9cswal0W;}Q>5>Pm
zCm156zRJLmgk`h9hIpL&YNhU^NfsAl&f`J`wk&Zvv>7)Bha`2D>yB1&M9G~Dyf+7D
zZ>07|@oQHg8xcDAk((`EEibL7lXFXH=n)Dyk4c;NGpMWPm0cf?f#u_(iAP$q{_;4w
z^Bpgeu0f6W#~d~{f$X>l^(C;h4=0H^3MQ5tSr$6cwp4W65IP1);|GHIR3RKc@`GG)
zt`Ykm90EVV$}lKSA}whVTDT~u1QT`5iy&ymS(YviMLLY0$VA~Jw9n}ZNeD(`)(I3t
zp7fz<18|YWY(oeN(QL;ST8}vv0tbu!eILbemYVopp>@CgA*-zqMYR=rHx1j6y#Qap
z3e(;`n)C?&4+-I`g_T3I-^Ghq<l@5{7wi7-eUGu;Mk!e7x2!{*V9)}-kq7(YM=_jD
z(w;y@3|r!jok<kaCHVY3!36#tp|G!!DXzyz(X)&5&_#XU+-b<}JO#_BqrR^^+p=)=
z%|=Qb5g~)-=|u7sFd8+sUDmQPy=~DngI_7@N5FdVhbFjC?>fJAnS5;BJ<n?E;z~M~
z*&u_jNW>afIv<UjJsjfn8Qrvw;H~xr&ZH1c1>twT;BEiqhPbv`f!f*~JSfT_t+pnt
zwiZ!s9UGZ?nB6%n(U}nVrhV1_1uVAhWqdIF2}WirQ92ZMD0^+;CveICjs>dWwIQsK
zHvmuB&)@BB_2_Qy_2-gO(Gno3@iX5)6IT5eZYKE*aX(|}g06vi%dbqD6ADM&?96Yw
z$eEpgdcJu0=By0i6`E4*0_4(C{Z!+47Il-G1Z;sDlMz6%kM8T{3%m`#ilX&IQl)lf
z52Xo}rnUdbAj;n>i)~sX^pB<Hq_*Dl;^0_#s?S=iw(@l|1ajdv^IPv^@H3g(Eqq^d
zSg9)a^`#GW;frVpKC^YihJV3krjE{3N?#`w8Jz#+&6XWzwKct!Z%uYQHhfRxLt>i~
zakX`Vk^Y^9x59_5wGmcZojO<>?I@OB*eXR_yJB46Ln2pe&Ib6ThSn&9KM%RR68~<X
zXt!O>XorhN^SJb0g$TR`MM2B3`(C!4?tnO?lQz&FZ3IJTGV*Mzt(NuOW&QaLsIGrH
zgkKj3us(BW%LK)gM7=OW@t;zV@k75*(`~nw+<#W6D<$!iXOrICwbx($%8ln(eb`xm
zGl$yhrkDScd53~4!%<r)7-@N*>n}cp+8SK{M3E^~^XNhc_t)sRx<FX8+h?CVH?x0t
z_R38XZulhX^149D!nVRQ-dJedbghp}uk+m4m@-W`#`!w4KMa97GQ?f5&~67P*YQQc
zrG(Rp#dBk5l%c-oCm32$WQRVuMCn}5O*{O_Ud`4$-m_v_B=s6S*D*+;5VQ<yI-Cr6
ze$*zaPK1BB&eEva%9dHuDjrHKd2GJ&?eZK8`)v6<Xa#dgI&9oyO9ZQA0j<58ZoYyE
ze^L_D79MMuW(gN@DYCbZOwQP|po_ENTADO|O^pkSBB-rt>#MUl>vi6twwm2bL!eao
zQ__|lNqi=Xn?efFM?r3INiESW+uRHpupWXjb#;FxQq$|*H#Nh@G(X!(PwxZLqNhNZ
zkspUee#hW2UQ(D-m4Es1@A<<}=h5KT4Lk`aH_Qbvi<4k0Rcpg<`L9c6W}y?tQ=%fw
zR<ABk_^nYeH3=VdBW&tnp%Vtru)JtKvXhav#S*WqC6_)rok=W6Bz;@~oLmW!av|pA
z96k<524Qi9Ix=r6h$IrJoGgL3uLp;!yFxoL$7q$2wq<48x4KjW);v_h`XC#d;Zoow
zT6l~}%xw~T1*&>^y<_XVg*o%V%9b;%8BU2&(}x@&hM^AH#&1wchGG{9qZ(Qq<G9pU
z0{T4?K_2U9LB4{41-;uo{WgUp`*09bn}d&`R52nr@+hZMBO2xcIGYzeq`3pcMhq)W
znQ@_sPadCAiS5S^&Q=^A2zq4tE(~-0oESVP<})9epMs)6mqo)ivml%t%DizOHvqJn
z1ZX$eBWqzghAayqCQ>YS1##o}DZ~srA(IwgIZvX7PZNh@aytDN??|&Lm%uN2S-(#t
zelLf`;oy>6+P-qw6n@@_6@jT!YzY%Syi(AVML-7_342+Hq>7e;#v#ad^pxtd#3E?M
zXSWBb9Gf7<!FI-Z0_dmgijjz|2!Z+>T^2|(jIjnF4r<;8iPmEj2^+hV2bken-eMv&
zYo)%+mwE#pfNs2dN|uemIhq4UbQzVFFMGGsrvO0@;`fgCC<WM)hAsdJfvawfGVZX7
zt8?@VX~8{~BQ-oj#lP?>2ogc4%rP?B4s43;v&7#6w4<GFqqf!uQO)as<QAnKAg-cS
zl>pvO7GPqKx%M6*QUh0vj&gaUr=;#}hmA?XV`Zo1%v}MlGu=SPWH78YaBSt}csT4#
zkp$dhkCVoGw^qz1KikLLLni_8)9_OjN<`iGv7f=8Ip1i{9*0~zh9e{zB-5MTmNTLG
zoNM^oHm0)X<Ju-Zp%H!^wH2*wg2J_&vf9c$=`)qL|07=++E1tNPgLNx&ZX5DgOb|1
z%3Rzwb{zIeEKY9XuU?z0MqY9t@Y*DQ`7-S9<aab!8dxzye_Y{)mbt_(iP?)65b{aw
zBmOuk?*Yg)7k&)Huc(ZSP^hBXI>xQ-mIt;ok`lKyxlmtHBIiQiRF$^XJ~z_3*ov7a
z!{PLf(;EG5D<y<Y!frL84BY8gZCtk!?4qrH-pxz1Jr}h#KqR2zy6)@Vsk1HRPg~LY
z+3ay!eZ8~rCIVYV_~0^3dr(^!Stqpd%dM1GSCEwE!v*G0TV3%yLxUn*#%k+0tF3-U
z!3SQG#r7tuUqq5?IZZC%z~9oFqP8LtY=8dwl`Q{mY(*4ob3g}78d54cO0m$n%EgB6
z&Vux&K`q0gZG=`iU^`K1>S&ZgiM1$r;iosk$1|i@mR?{PT3q3h{Nm(uEa9Nu3yQr(
zx>9aWAIBqaGQAs9`=y0*l(r0&X2IP5d-0gt`kl;H-*hj>Q7*Kp;y&*E_=hu-1NUE@
z<!*Q|NuPSF?cMsFB$Z}ssIA($(pp4M?ha9w+luV|$GmnaTkU^4Yt~iG3eEoM-2C_#
zTmdCIOYftI_W~*m^;VMD!wdNmYHKoNOQ@}Bx^#CtyS}zv-M(dB<Y3vs1(}O(&RQZH
zcTTZH%HE+{F0k@J7rcDCfS;1;dFfx#F_BNzWk9rm3bpNSD*p5E{#%z!Xt%C;xqkS{
zG!`U2+rpGLVVzu=PKX<N%U;x01!%yqmQY>s0_D*6#mf>8z13W~pAFFISy^KzDT(cU
zbK!K$;}-7kE!fIGUBHm$14xQsRvVx27u~%$H}mD1HMB|i--ue#H(}YU)d$vGN~((6
z|1P+)s4aHShvA|*&%VXHc8(jOn7VM^`39pE-2L7pl&>518d13NjVU?M1<tJeZ(yKQ
z*v=h+FInP(-twNjG1O68$5+md>*$5pJJtfm{kunTde2Yfb83k5Lv(YiP9x$jK(t!A
zH2-x-mf|1L04ibqt#>RkX816foSJKU&<efW3B&rh3AJjgWh+Lme-xC|9=raS802v>
zC=>ewt=#s70UPpHCg%^gR8qt6s*ZRcL1};Jf3f>IT?)kSHR(Wp;dQk<{p*Ay({GKp
z2QsiljkbTGn0@a@;s4^6E!;A3;n3gEsV;A&%u5|os%VG@L*C0KVP|s;nOhf5eTLE3
z<s{qpsUis)xs7utuK8cY;$S!K1C-Ck5Nm*iIbk4SL#0bSfn_FL60_=Ohz<dBP*FLb
zAK=lN^<?#FN?0fe0f%)tFWbpLL`Zzj4Z%U&XUq-AsU5A16W;91>2pQ54X*vJnCe(4
zLoRJ-Nv$imh#_%#nP{JE(k8@+%V;%J9E+@!R~tNUWgvr@c9?KOg0xaw!pBYHqxI=|
zo3j!`a$C*YJRzp>F-nBzMKl^vZU&Bu3IiEe@i}Cy&9buus{mSAS`~ToawVqTAfS0W
zP>UHJxzA)4I~81^k(i+E!k_>MbR4!dq(zfhUoS7ZfC)3#>M7ci3}Z$obt5#03hnv9
zJpxir`yjh5>LF;_MU`QkV^l{vnSB)#Y=OWYKZWfM84Nm#Q3M(nWKWTDUSidrZn`zs
zrj&)`!X|WAYR!~}BV9aTdyA|;h(9!5qMhDK>ART^Rn4(o9-6@yw(OSsLp@v>g<qs0
zu}2t4bpv18a4=|jC4}kQ6M!*5qs=u@_X18u4<5;k0;(!+QARj1ovlaZ!K*(^2y;dG
zmPfCCZwa{`!RzVt=mnbK`kK>`!s!)OKcZYoT8M#b@mWm*=M2zO*(G`Mab%&%TkJW0
zKM24qgnXTlLE-fS4p*=CVqe=as0&L#ts0W8=r>LRf-{d}AuR@ma)eib$5wh4(RbE7
z*Gj-L1Y&y@`R<^d^c^J8$ej86Fpa$wtDq98bf3)crP$GBMNe8ACAwWye9@9)1tDpt
zl_Uv85E<d^5YD1Xke7PbGmzB&`=L>nc-rMqrsE5?hpt_3&5<aXPLz^YG}DMn(e4$>
zDkG)3d4<tK!4*lQr&J=*wRo@sbWEg@W(n-}(78=OfyZg09Pfewug|GzE7;r&J0-om
zC;3&;M#BaV=VsUY`1O{`{8Zm!qrBE0OdCn_rM@S)IN5LH$GkN6N@9476tKHAo^8dT
z6ncBuOF1l(#+h74gaT!&DpF5m*@QbQ*duqYv~pbd>;?F@sg!pCr*i$TAgwUPUcM%2
zqlco!UcP84w=A~RR;caSz7*^$e0FqoCNx?%1!mh5)s&Dn+eIk}r{dZT0xSlOz;S|9
zi>fQ_c-a8wVnR_;nfcrQK$}##EqRlDg^9w|#N8B5AGeuuBp<8qpw_k_bKI*s@k;OQ
zPe!N}+Ip}m#`=;sSZG`YR_tDabyC;~c;b7Md8kn3J|tpEUqkUQoS*l4n&F$b(Q)77
z)_gWKEZ;%S?X9K$6>Jjz)yE=k@o6?#sg%z0^LLz${`gF=r|v+NU;2_I(yXGo_^01I
zb#S)-yQJ-C;@rY#!W3FhNtmvX4}Wvfo<F)}#0Fj!+Vvx}`hFs>qFt@=1<rGF7Rmhl
zk%etprP8p97hd*OQh9e;dPVWeKf#1B@5S;Bmdc?UgmSyr+19|vKsuEuD_%^ZYK4+Y
zGxu~7oM?uR4cNz{CUtZsEPS1z`mnceBB?M#Q~{K*^zk2Z^`)x`aD=vb<}`%%9!JjB
ziafoPAp=wvK?|-MTa1_%7se)EK@OrN&s3`}okmOvEB;eIs}R@V^ees_F*65BKbvx=
zO7iJ9CK%M+m?WwP!?g+f{C5)}`0%yUbxl&t{HoQ8sm8^ZtwmCx#mi?H)Yf%LDR^DM
zf$@>ATJbxLBwwn1hJ31maB$VnLSbCxrVdNeNlWeDt&RXc17{^|%C=pkUO_++yCxKk
ze>R8IG9l_a9m(j6)p$(&4!)b72M;DjXt%zFi)cQ6h%FIviMjLLKHtjRpw+da&Qj`i
zyu1g^51mr8;vZ`ntE_YO%<I_q9r}{`PokFObD8OrkTald4&+?vMniL`o;8XuGk#r%
zuIOEBm$RX_FOdFf0%e{5NsM$PO`6U$dEvwKDz!0=K2&A+y(G7#!8U}FFQS}9c%uF8
zyu8h!)`S7utEPE)FH-IaG$Qb?Y9=;$FK5IaI2LA=@*Zt>b=;^VeMb>?vmck({u9aS
zJ0}=*SD>=Y6eGf~R}LFKeF74+#PAZ@X)H^mlP@Vn51LUe!`>Me>ygV5V#0-B6z2CQ
zeBEst<R>SKlrBrriq+QG;R}qDI<(b{qMG}t@4)pHGb%GrFxjM>*$jwcJau4<-*2hA
z*j^&X(!9-cIZd*QohqAATJvMmMwOFtaeA~NrdnoNh@gm+idb~@j;Mi>?lj1mMI0-N
z&++RCQmYRIFj=jvhMHA$ljTc7<B|9^*FJJ%+FW#)lB+oD5!9<xKp@{SL(nT(E;>|C
zj6^%aYdX5(eU0NdC{xlX1Ee@8S}(thfFi7-s!<idAes`CQe_B3-PU7s02iQhuJbBo
zJ_d~Nh%LDBYI(0{9P`@5<Vle03~<9b#KY}|j;LbC9|x()aV#=G4*qsqas(@+q$DIT
zR6MSubTVU!R2Eq#a+ldQiO3X+QDuadq$<}y$D~R04Bw1}PzOpfzZzG;@y4|hB>0cV
zkeferMWL40GN$*!8Y-z+iN}wd(1&I$U;#vZo+x&raq9G-0wgpVry%<{E{urESkfZS
z%nn#RF33*e>V+o1il7V|!ioh3)WXi47MIoojYwt1*U7}Y3osscHV0COA?_2p<Co#k
z#26{CsX3DJcu0(aSBNew-9-q<*Dj`5#e_C1$4#C>7u5KT$FfdbiFDG6aruRDrZ?tf
zkWCQ45DNE3^5pVMr#x-&TWs@zaT8eeQ6w?)NUM!o@}|SC)K-<?KsLps(6Yw-V|^xg
z5V+2zRz{XXOlcO~n4Tbz{AtiW6=uwbSlVuo3m~k`p*agym~|8cpcS8{)B<`%Zc(60
zNDZ&FJ)-YM4@m}KU@r=NNXg4?AwDV!q(KHRCm;q%Wr`2pE3*7|gP&d(be#-BRZQGE
zUz{SWi;w`mort#QhOaELu9VITM}^AE04UlE+wxlRsXa*dSf%gDN{0%nsFTu5g*u^(
zbfN?-IN~pYjH0k3uH4wdE;;-F;MSO#m0aCg(2GaBu06NbCCt^oYt4CMLs0giwif#a
z?6<VqnsT-k*wwf;yehe?l9u<cZd4?~smZ?ND+qg)b_-wuk1x$JkSRD)h0FFdRES-k
zU~vf6dyZ7mh;zWK4c<PANzs-}yNCD8Tk-@q<ApaEr#@#)=eG2bu-v{5+CC!V;v-OS
zXzI*IH(+@*XXRE0R!z!bI|Re1P{y#j31n#h4x0G?Or_<tt6z9k8!4PVZJu6Z=e|>!
z0Qo~Cbrjh*2^Ri<xspHG;wCURk~`CRb+WoQAtXnAG*-fj#tj}EKN+*FwzFhq)M}^3
z7N~<-W<TVX+|h~FzIz!B&wu-a9gmIQYPO}e&a&F7k8s%NsuOk#wbeL)Sf9m`4=}n@
z4(~0=c)rbOlSlEEi_Sfw$ogVRE-X(X;U0jXeP}K^-k1~v?_U<J0D&9|MO=wnr5pV)
z<VK$fK`KrBB!afjYC(4PQ+M8H{st5ht(uKKLkZvnsY>|fkeG*IPZDyJ!->KZC2*<K
z)_}psv#n2ab!_pp*{_ukaOKz)bLQ|0=W<dm_o-hEHE(Y?d(lQ;WQwc4)J$)9r7JEw
zGEp^X%fI4MpA0ZiK68pKwn;M(c#_}dFkx<`!5+w4&-ZzKJc+bA{faifCRhFIkR5nx
zz}eKR+I`mM1lgtXSSVZxsfQPs!F<l92oSbWTl7stzAPe1B5~z$T=T}8wN*bJcS8GG
zE@dwn!6j;xS-0rg{<#pHEa-qyJH>e9=B<r1dZ?5{k9S+s|HE5c)F_E|zKTQ_Qa!eN
zrQ!@aQL`1XE)dmLPhn_ic{sGOQCrPpmH-!|wubRv39kI>fiZ0oR%$JLWuUNIf2cLS
z2d!sMEw>e&y1o6e9cKUK9ke0eO0zI`>WERZn1x^iVKP0XR3Vjfj;nj^C{K9NXO}eI
zrlQGeYcuf1j1Wj%7_d2;4ts`tl9_vp+`2=vr5nFrxR<S@wfSLxiYg&1s9B*8XAH%S
zDP=9BtZ4>qq>a8&=R?`!Vxvh`r>L>Gux}u78AiviC#Zwfi1*ud7FFNAC2l^WA;zm-
z3;I^%l6{ezUWlZxYCIFC)z&mldD4grGHIiVdUI&2tpzQ%7_OvdNS>4cd<>J6BzM}M
zS-38J)RvJds6JlO^wmNCwxj<OGI&y5=FrFcVY#*Vp$USIEl%4ja1055XCO27IY}MR
zMN{0^;CXa`5b_WU7I>3UIfq*OkD~yLlzawYLsM{R%KL5*b1_N;c1#(BrA2~P6w>J-
zaQw|yrKxhLI*_(7gWL!giB<mHo^=qKZ6t!ZXyl-5Qn>}a)S!FELtmC!OU)$aq8-2j
z7J&A+GIV)*1&yhNUy%>|Je?-53R=7h5BZ426)nOlio~u-;nEXgf>v<M&EO16a107w
zg3)vu^0dt<+*ASz+F{y`Fyfs2p-9%jafz9N!v=M>7_`)rFP+%d;h)3^rv4*mMF2re
z$o9B~iz%LU3LqZo5@;df)tnR{SCYsXGAHPp7TI$2B4AGdvcF%Lm+=c#jE&CBk&~T_
zkE!*F>K4nuvt+-N!y~w4vQu(b<O~#3)qC@2o(0`}gk)+iQYVHL4QeBJbBZ|22ASlI
z5j5pai@-J@Yk16#nOUKv8kKn3Vj%=n;kl@`E<hpg58%mJt*`X4m<--sU_t_PFBxBH
zuf;|D&V$V$%2^jW(c78l?OVueacL$l56WF(mn(iG$!WO(qty%QUM96>m&!nlos+pf
zTDv?%&#m!SU_(G&GB^>!ELA3ST)~|4O>BA16>)QoZ+lg>qixynh2&y@fQ(=`%8-~V
zsPo#Fw3KQe3t9r3bdyK}&Vq`O)qKrMARXR?+$Inv=9)qQ0<RnTWazJ^(4y-mk4ej@
zAr<UVj4uJU6`46XpUhY8Cjd!>n@RC4P-BeRq32p|hG<*=h{<YjQn<d}RpxM_!-n=X
z{zMExtc9e0tOuXS$5rTMg{El5xE^7RkQ_Dv&EVLl_$fq~#jrkyl<-zu@S{Ylrp1bC
zLY4Un;!4EXyrLsJ$ue7OqnH6>A0-~7gMCPhradTL(~qj|n}bWavC+kvEyN@ytQ{l-
z)afmM+~<G1bj8Q*U83I|@;LNp-ES?gj`gt^Vu-11^Kb8jey7p_pg*c`PE`wnM~AE)
zb|sIt2QqkUkDoyen0kP_+C&*wFye`2iH}MugMpGyD{3H<vZOnG_-uR`;RuS>b|2z^
z>h=+PJdSmadS}h^i_c2_U4cPS;Nl}oS4Tpve1$oMII0X*E#Lr^Jv<PSu#bhP@||`b
ztF3vqcaS{RVN)_Gdv-Sj&MvsS511O5d`K_*llyG+&^2KEw^`fyi?xv!-IWmXQ#|dO
zgtjT@Y!AagL1xKJh=n0qc}%@*%DMl_PV%3gx3T$eFJv8$P2NFjtAG6=vXLv9tavKo
z<}arp=6|0j9&0=_s50`|k_$pbR11P}*njY2+q0$Y{S3R0?%)FBb6ASPyBG0t^HP?3
zN(w7q=~Yr81W}XX9rcy?y~k(B;sutfGp?I*LfL({6l&%lzK~A!9ejI$kHmA+k|jMQ
zx4eW!(pMU4E9-NAH>@daLpg&FR{Ky}i~7^2Fc<X~xUkyV(rW9}6UlVsY}yC&|Gd3$
z=s{OWAYld7PSKu!B*`XkK6}t_{TJ{35mpEn5frC2XrHq*bk9~B3jT*<%T5mWr4A8J
zLs#H`kD~Fa!)N4NO3asWf5k`Ft`9i(QzdkM<2teup}|D>9QKb~F<VJ8>W_+GmCPqe
zas6DIgtO;V9B`>$b+l-7u4L*OqY${&%0lZfia_n(w&&K#z?(U?D@oqfNcwd=G(?TE
z6YZGtc!oAb$6xEeK`Cr2)R8kd?hf%vCUj9|3aC$)ons|oNQs|EC2x|F0<F=9<)6(W
z&Gh`!Glxr9Ir>)4(zqnkWl;;~el$<U_gLTUkDVKKOpcoSk>}}Pzd>R?GC`^uefjdc
zw&l~~-yF168^~vRX*bJ!)MaosbX7>x(#BG<A-2Uu<H|Gygpw6~qrI)RMmbRVlNauN
zIvM*_tY})2&tE`t^=;8x`eWO0wAx`?Eql@catdo}Qlnk#4|gVMwo1qnVfO}VbAH~X
z_C+??cS7jqDjK6#+CP#a)Yi0WWvghJKcvh1!X;@xk?abW(=nF1S1&f=u}kZa+3>Ba
zkG*u!5!&0#jx0*xC6Qd8K2b%|V2>_C&!^bvOKLA`40!F@4cT|!XjA!BRMfkWc5A1l
z{?pzTKXe|#W+DfUlWfmmUX+D>k{RlTU8Urm!JQJT3%-}ZoK{mzdy=g@is^v?9v#TT
zMb)q@^XD-kxF)TR{|0Y0BQFIlf<@5A2qhmh?<w0zyjqF$t<=(Jqkgl))e2{wK*HG!
z9L>{3aU`^MsjOlcn^K_yqBcPm_z+T?nIA{l(u_O4>1;$0PE80hDB46kb^)K#I)dX)
z6pb7Y@>A?SKu>v<H94Ep8A_&;OlB-x3qn4OK-72xQEd(LOiGS3k$|QoZ6q#Zj`@Tc
zWl(C9QF;-5!$*)$U>U(=BC5<fb!k_;LDlO*Oq)|q9M|zG+{wU4N3S{$;Yc;Q&^(2z
z#H6(IPHw}&vMCveQRiz(V8~dJ^xkUD(UnLjJ)}WchxpCV&2e$jr0jx#XmEr~e`y}E
zMg``W-c-YlZ_TLmXVxEVL=!HB$_AVrtMaxnM2)RUt^k?+|D3%Km}N&<=l`B_PxqYe
z>CBv-=_DN(lIl(;b^^jB2{?ub)tydgFzO{vFuMG?lV1!Y;_o*I;<!er?sSqSu-IT+
z2X}RE*towjvhJwh!_PnK$&mPrY}RLFqoNP{Jgpn^1QvPP7<6C(f1huib8q*=>3bXB
z?psx->aDlldh737Rj1A+HYG<$cnyJaUVFP9lt`i`EKwYlI>l}T$?mgxsx2Fl#mT0*
z@t2F!oC-BZj_1TJ70&&o71Pq_eN)esC{S|aLqEeQa4N+}CllMZ$UZ1MRKRH!z{gdT
zg%QgZD(?ZNibMH;y?kljLI7X0yp-Hm{7BeT!3fhbSyT(1n<|g|`;~)xkgbq?<vG|a
z+Tb{<$DF8pen>Q$GNeZ22keE`uDzV>SQv7&HJxbq$|J~!zRSz*4}~?9vr6QuH5Gb^
z^+A5A0z7$p30Rq>Fh}8OA&J>krPgqd7JUO9rYq@WRx_@Lyn=kh^$byK3m?t`b{H}T
zXF<^iK@@Kn(MgnZ-6*h;@S0Fz9cg4dg>J}>Y#ok=9L+%JA;zim9d5$Ag458Az7dNY
z$@_AJuE-T+%*q%5F&{`I5)RKpj)BYFTq3NF7e@5PZu5f;Z(!6M;`1#*8|<((hG=(b
z$?alkOi-rM**wV!x|g1ZCDP7$1G8EZq9skn+9{TG+-XXz(f^5}<LcEqx=3sT-LxqL
zTkUuTf*xY{RFaQ<bSi6g{-4E={`k(8gySLMNhU?t`AxO8&GIADCPq#X_rFV`Y<udo
z7A6&X{U)Dq$uB%l7n%E!mBK!+$S<Q}9aD_Kuwcg+BFYbt^S6NgL~J?jax7F)O9uAx
zCujs4$oS|k>f5!+lG4sO0B!d5xvW^!mk2Z&c_N$1+QTl&u!_B{*+IWW%-5ptA6F5)
zOq+RL+XRA)lgQ3aa!zpNgK25y9y<6NEMWt~oc4jspT2Qng12rv?6!8eK=Z`Zp|KIJ
zCV<jJqZkSM=#qaXXFQ&Tuh&Dly_{dy`nJ*Zs)~Mp6B*A$F7D?f?K(5p8p?$mrVAZc
z4fn7mlmC?O2K2WV*+ggBU-&I*tL>++Iq)O-e5A4KQjba#Y^B^aAItR$Ci$p~&W_Jr
z;cfUeRvc|1^d+)Ba<_y(7;<S+x=a=wkZHivRgA7Cb<6tw@w+=t`t0$gOBbZlOpxof
zs}Aq+{=gd(yW<pfXwNUg$J301dV^GrY!IN|`ccj~ql<F)9O@B`Y@|3lWr0dtqFUwc
zr^bus_&<y$;luaa!q}?{lS=NSNu7SL#eF??Tc_>zFM0dJLsaJMuJpE(U!3zccOVJx
z_)|-~PgC2&>UQ(AhBOW?4&qATVPxWC4<ozD>uhQ+T%m93)j<8QlOMNi>4pVMo<6*z
zeA4-&5jkDS^h?RdGTpAlD6;aVY50A$?UR<qUB4lVJBO4)R9jgW_VL|T6j^^5T`NWW
zr#mbOM5VK4r@!?ixA^{R5sa#5h1)6hLNRW=oE-l258_6C)F1QR*H5L&X}E*!MrpRq
zx24Y1;?#ZVL^jqy$YD4PMa{drJxm<w#!_3AH+IzVIsT(FPD*<6z-9CbXDwfQ?y`M4
z8t&XTlhKUbR-5!h`UYQlxrZ0c_y11n!{3tqi7P?TRCO*dve{PVy?w8~XEzY?#S>R&
zw);??-~MbU!)IS{ZVc8By*;;N!=1e?31|mEJ+vo_kWTEk3IF@mnEB@#7ZgCBnv|7t
zsH3>17ehV%nRPWvX@T(+$?n*%Dbh|Lyu&;DTbEYvwh}`{v@Sz%7scg<llX4y5XmM-
zUq&K=&%Gamx6#A3L60>&VWI2nZ$nFCiPj=pLovDFl@qD03RsAHtM;d4f5V)GA-}9;
z%k1-si^<wgYRB#B6*}B~mVVQ_lovY8z0`(B{~>`xsa%IBRu(zce+2E8pqLDVBJEJG
z>@uI&S5eN7N)VwNOZ8&GC>eYlt5-XKp>Ctzns~}U!i+CKK}{r^gPdp$$%w@&%P{~a
zUc=iAe&A*f_fElq7+Nx%@&Gub8y&TwL5p%nM}`UU0mw^s;CBwP(jN#AfdC+6w@D%J
zn9eiB#|Ca?`hYd%NtO;ZLK<}=`QxK$6xD$M=0(0{jhe_ZlM)Dy6iA|t%`)P-e9G&e
zfyYN=iXw#sBg4&WX7cPpJ30zNeAlb54c2%E_PR)NG`kPco2L-q^FDlM97PxbA8z+U
z2O=BHcS7t8=lu>-C2~IHsDHh*aCa(k;|aNhWV3)%;M&Httb$Mb(wsFEw+HnGTkm;0
z2V3IGA3NQRjy?(NgcuSRmEPPN&~WsyNtKPftyZFm<0ahwaYj-a4w<$l*MtgM(QI3W
ztG$ddO?l*5iq=E@4nj$#Om|OA@w_d-QBdFvrc>p@?g0|E6@I11P?s<Wyqf4V*_6z@
zq#7dyYssyE2MGu&w;>!3s(uLv#mLc9A~`ew{_rV66h&B$wD9QzB+F_K<kU+AB{ihT
zP{=S-1!R^4t@J3s`9LD9Vl7%*cnJ-rTKD1s{nCk0<ih&G!$ej_L%`6m=jDLH0;cm&
zXr##3N1riTPMh52d^nxFIbmuINrmq901Kj)29IL}kB)pR2x2p;*0P+8zVI+OYXQ!L
zwa8D*)UZb01AN(?cyui7`uDL<qA@oJPiXr&q`g=ND(zPRu2MtEDtGsT6U9O=1S+{v
zt>7*NlEpzuKw>9AvXQ@`AnF>9W@EGoOh@9e#>mSnqg5hxo^`K#jC)CQp=KFAQV-rh
zSga6Z7L<|9i)|9gvteAkXFM8~aEy8Us4cPB68gl*6UhQY{32(Plg^AFb=5>=-)*AM
zS*AY09CfLP4S++SgQC{~VhKtRT{wzY(2Vc^<k!2teeI?Rk+nLo4)QC-EO3CIGnd#d
z);=|RiUBFIAQAq6GV$u2xU#D9QA6j9nt}!b$vP#gznt0$tr(}G5QEes_?T>iWO*}*
ztI;iF87NK&3ER}57)UK-5+s!Y5U9XH)G8dbjDsYxCodKEBBrk=v4hI3OxqMlK(FA9
zF?_@q3x|Zlu(~d_?E>Z3QaCG41p?rV>xDppGZu|)q+PPGtC5+)9ROiJ{X|8pqy)3!
z12%(<{>9+8k13G_1uN^0Um!<OkZo*}D0)7=>r>z;_0S)D3=T38#wK;#Jqq0bA@#7V
z%Y&EiFvu?8(0C*K0gxelvfz{=ghZ<k^d}hl#QfHSRF?*WisV~^t+O?in7~(~xP;)M
z2S!bKITkC=E;<meaC=Aky4d|~r{KiAh%QwXCD!>WR)R%9z><KS49`#HE*oFEJ?Df)
zvtStB5zK(@V&_0x1Dp&}kBP`#<xHsyoQ&#iLAka-h^%e#h|bXS@U<(iS7Unt107Bn
zk+}->L0I-mZ3^FdnpcHvXO;x4Mo9%_1kw05Ho$x?4zQBe5Uic>milo7I7)&olCdK=
zyf%=2k<7Q4AB2>N=7hvP2uctpQg59U*$y!oo~>d8jqnrBtP{w=O)#balHD@ErnEL4
zIt>BeShSKovnU=109_-9>h}vW5HcIhVlV9Q4<2uwesH4X0$#f5auwV2i?JAs^q{c^
z=~k6qG#x(>#C+~N%>k$CUlfHTG!XP6G9UAWfUA-dfeIF5jq?QaMdw*NnaVK`0y$c#
z6J}KKF%nZE)ljCRK-;p4sKy8{pB{8a4UbP<oSj}^Uq?ust$-1eAl(Sf%8EHaaZvR%
zb4uhiznD`{oF*wlV|+iv!H=SjcKN{FA98|E)hJoB7PttDLQnwZoM#NeSAm+9c<7bD
zePqtBDycnzqod3QRMW1(w=GYf1?CtPtWh|cfR3%UL~#;=OLfoyE3?O9!=ht~S*`dX
zQl@5<s{W8*EeAOUf#zMx#SFICG{`POWKC{-CXz@mK4G-GjzEs0Tc%i9jIpEF00RYY
zwwqlKF4F2{Ba)KgHRPxy1U{M=tf-$4Xd~Ym2!G{#3@=_q2>GwTRn}DfNTE~AwPzTg
z=N3VSkB`A<tduC5mS!~u2TOg3VS^11GgKmC(jP#xhNnjDC1*G*;a^S#{s1^Tg7rDj
zZsDtjx<ixK<^+BQV{y0XZuNNnr6_e6<<c~;qULq}Fv=qhzn3?3+l$Wq73{GX_bF8U
z8rc0Hw@>UYs`D{-(W{h=C8W_iTv(mK<Fz^NdT+;LIL0}Uv`xFQ8$evY39*g9$X$2<
zyhjqFS5MoUp`!H!Q&`b*|0>qjyrglO&Q?Bw?!q-NL0_Wm*sJJ1H{^417Ruiz`1nX}
z>wHT){h8n=$_DS<{072*>ORl=JoZpbw#eQv8R+W#xX<j&1;P9O>0-bD!;=|69m34d
zmKF|<^oq53)|N`v&+XmAY|dZ1W%kjJrf%N2H`(Ltbd%x?_e9)V#>^jmZYoI+^NIBX
zZ$w{Tznl*suv1f<%{}in1!?fSH}+}{;5}`H&i$1u-|5U9TI!eBX4ug)m+Q?b1|yc)
zwWu!OJ+_XMW9j>7rC%qYT7Tyt;MpXQh>MH-VmW*`V`bo7a}tL)I7=085G3hq7#5#S
zD_ZxGG_bf%3B}d_rvtk<tZDo88*TVzUO6hxj^M)y)Tds(8n++p3oqkpi+@UWeMrdv
z<E0_o`mD`|36_>r4(-*U;HGAM%8T)tKiWu=^guGB20RFoi(0E=XTEIha*el(uKU-n
zRmbqR{7A6%yYe-==9V?yJWKo_QZan;Psxkz;$^U5OX97rc>gwaSv5K6$Cj9PIM`|l
zOe2(QN<p%Xn=c2x$v37>j@l2gk<%Mtgx(jlPr^Q*iV|Av*8uUp7zId@*@r$66Dhjy
z(@}cBuK&t}?Tm#}|DN|zbpB9rXW0bWf#`^?vy3`s7_%^ZD3Xjf=!${fCRHzQCytoS
zliTF)FY`9OZcC4S1ePy4$ezqMDePa{Ljzkh=O;=1YnLrM4O?q|*R+j&tdfu}DGf1m
z(C-IsiKR>p3+v6RIWv1HonH+t3W&FPQ+pCRVb6tUx&i&{+3*O#Pwq-vx4(q?R`+VR
zqa1g^(GjzE$gHB&a*$vH#XBCr#>c`ZiicLtjwkWevKYK0;|3<V>&kHbQXbCu1tV>j
z=*8=N{dz{$V@xaKvByhmqG#wn!tdT=_Q%1u;t+8c6AJj)WVlcAIxV1`r(4NFNtLQl
zk9A{^NJ8FbNR~-&!#e)W#U*jr`S^FFvz^~b1Bc=sOge9A7xptDv)O-Jm|t)ivm~=;
zbRkUc%hc<vc!y#+#@Q@MXr@cQkDZ5?#n1^`S|SGLT6@Ut@P5YHRAmnHHr)&8>j-)W
zp;{EflAt5hS(e-R=z|y%TCqT7&=pEG868$?tIIKTM}`-c<5$EaE3PZn6|$Dfq-n80
zCvefkSQE}1zpPXHYCh+@mVO37Maq1{Yi-WPs&a`rMh6I9c>_0b)>cM+Y(}I~%w=(I
z=fs@!k<2NS9xNg9<TU&)a=>gpb8Mf5m@k_M&VxMw9N~3@h?)0t6S}pp_VGd;4DjWo
zqD4pzcLmC1Q_j=XvjsiPRu3*HXYD3=x)(jjUl6K@uErf~H3F|aThc>pi=Jd<kkS<)
zr7gM`iW(wit5Sm62s|QAlG|V`EM!&6p{gAO_JK90m2G0Bs7Kg~^ODuDCr#>0NIb80
z;Y{%9Xd>3((?wA<M^MBRF_5g9c|oM9w&Qr`i&d_9#e+|1n)GaG3nrJ*%hL|e@F=rC
zaQ>;D-)F&{GH7<elUU#ZekY9nYiAH(IFOTh(1RsT`4j{QIXMt^2(mL7F<4Eu1+S#!
zq#M~ZzvxKuk-P>%NStUndk2PtmIya_7K96IDS3NzV!RMFu*3#QD0xS=T@ZBEbk;|2
zguRnetvEhKY^N+ZelQ$=1y3E^xdO;(_3CuVgPyqM&a%LM2HWkKJAxOQZSLU6iKT`_
zL+uNlq$vIkoX)pRHPI5(Rv{DI7g)GpU?qZCupqj&+>JoBbq=L@DK(FjKIO&ojv$cs
ztwXkGs%!#As%fk)fmmYaVXg%e0`H?Go?vcZCWOp1XYuuP-#ryH<|(#}npSNE$nAG}
z5JpICiJt|r*BW9DiXEX{+uxcMYIHB+-R#;`=6oGcTYOG|3Y=5&Ay0YlcFjOxv&F^m
z%H*;pWnJ~tGd+N!w!~xA!|V%7YCF|n=FACIAE${98-9c;b7qQrhF@++k_VD%v=UAq
z$n8*KNw}VthuWH+NFfhfSHjuaTx@qu`)rKwQSEZ|LG%f`V7IxSOun8~mJR&c!$HSh
ziX62yVh=PH@27BH5A)1UE`gRHyl0_`*O3ZcO<U5;zjHoL(k%Rf72&4|Sx=S{_d3Tq
zXXd4JdfwKEZLNyEy_xf(Taj&~LDM_Ft&z`QPL`Jw`BgSCw2|6N0({wt7v#S!nwlHV
zqLSzSyBGuBz>+}crMx=!K5Jjt8MaS{3laTikXRc@g*O>lzaSsYQ~0&fIZN}zBik^<
z;{Yg5Xr`!3^xV656&H9BM9@IGMzKD60f(p1RN}Wa5_t~-_XufE?alP<NUy6?95J34
zv)kKG({@GTz<clYbJ+1p4jQhPY8TKbGrRfFD%YK4ZO;8UG?k*5{>BoRJAk9l4JG#9
zE^x)@*Ne7}Jsu*`9yC>l9qxS#{mtElLk)5H4<KJ1a*SHfp103N)e5zhhVgex`R(f$
zvyJu|wUL3~Ipk>B_}L<dVYVe+9b-gY=Yd~h^f;RZ-Ck<`6_<Nd;e2%bEK?*@@-zSN
zn#`I{p;8U)v0F#}X((Ag`Q7>OXI`-4&;0ei@zCVJ#A7eb3m3@#(yV=WWWkCjI#mAG
zvr66^$QUDj`if+X!<~M$;A<Qox-&{X##{YCOWJp>vQ#;iWuH16%X%=upL>LUZS4mr
zO8P_h2t{e;m*1=f0OYHu@BKoY5%?x5n7SB$(>e`=Z+bc#`Z4odcOuo!>GG7Sf+^A<
zfO@|A;rohm_>t;kwkoAvd~`)8OV5PiNhhJlPl^7I|C@d7Z;olzAa;~NoR#n3)iL5^
zsI5M#&x2A_cr%_?mD<WOM}F$=mOP`9S_fEpnnc=PnzJnCmh}o<FY5058KzX<Alc;N
z!aeprOPcyv!xdLMJMk>N$CE_*>wOv55Rcf>H4LT?KEg!wk%k)=m3lg=w6=xhp-0%m
zzuQ9l{iCC9S8KDH`r9(Q_i;P@?R=0Z3wsjk$_^l0oqB8S;<o*(QcG@&l_BRv%gNX)
zh(PDk#9@_b3G)J0)Jm>`rtj-KVAWkF8;m(^^=mtW;GynpgA6}ITLc2X<jjXKujO)_
z|EZPA?j<v`_aV|x5WInB1gX4#T+Qh6$VaJrXa<ARn|}?|)}UoVyHlwE$N1IyEaw`N
z%-PK&>rrh5)iO|>ziD~p(eFwg7=4n1=<9ommVc5N+oxEa@|Wbn9@zCOLq|vK(o!$W
zPMZJ0_-W+ZyzN6~&MT4rkf&i!CCcG1Bjw4rY(e)38kpp_S=jO!1lnjqO`-C4fi_<e
zt30|P!Ra|+wn73}m63b2-atcJSnhhs9spTK2+Z>;;@VMU$~}h2fjpH7NQ0aqJ3c<u
zMtsN~)KiV8iR@rdO5LmoyOL586gl^<N+cm5$Z%fGYyv4C=54O&mr${Zus~4Y%vnTX
zrU^<%OpHgyOGWenJ#lqKPQea_Rv!^DVs;Lz*Q<CVEm*_tXDgKWE?*bBkFCVDX&{1Q
zk!p?1tJ+@9(poJi2f9V*w%5S3=a)t)>4-;=OKsh6CBpOhq2c5|zEUDSxs39=0|k|t
zNeGkHK&8<O59A8PA$>IQ&MAqQoXSIWS8!1lJfp|X04*Y0gS`?m-rD?bCwZ>1U1^e)
zHY;0!omh^X*mOrC4%GDt@>T&YGibG~1SRFQIV6{XWbbDoq?m(wq4|=C4|nQJbs*`$
z8wlRnJTZGvX~}x@q!K8ij~R=t{8}*?9DN~B6r>xACml`7h|JbRZAUAg5{jFwYmkqg
z7-UJAtl=Oia_*pVvK$3Lvw$i=q%Nb#R`nvn%pHVCa!4|b3E40K*H~66JicJ6;`Jg#
z881eH3fc|=0o@89f{x@&vGkx?68ObL#DrQ%_NY=2cPu@f4%ibstiA)(qTve;fSU&+
zNO;=Ury87OJwu+{_`EO9k8uv<4E#}Em!d}3$UQ0Gp;8?;C)r<45foltJAeRA=`bcd
zMg%e%l!h`aYqhe&TxEAnW%yqVv+x-l(Pv`5&&^3iHOQj%df83}@cw8PQFipzil?8C
z-UEzKhkM!4AeT+t%5A{zLUo^&N2Fc8mK21C4LN$XWm*kxl{%hTeWFBO^Z3}DMzxfn
zz=P-4ADn_iCCx+|j_1HrMV>#II6tQ)kq6is+yOMDwlXP#wI_{f9lQwMURk5j`Y{>}
zpOWDAC0}{BuZ*=DiC@Zz$qgzr8s&thSXG1ytDnhkD|=R9H1mGJM~MkL`8`)fitof7
z^YujLIgZ8XeY$Y*Qf5DbxYnmEbt4FTVJe~wp^a7%2bd|Ech2^3DiwGrrb5Y-_aJ}f
zMwOB}tYnoBE=^50vV;p*5lkob$@&nEgXye&#m!`A8?E`UWOpooCY#*f;<NVdHFIWf
zx*yFpUr0R@c}VyuPW3W_po8>c9*VJ-IHrxE7lGZ@#XlKi-p+2Tz57}%6%B%fM(_wm
z^2>~BUv(~i#gItZPiN!+Aj~G8V^Gny=dZmlYbt3JIqD~lYLD_PgJHSLm+`h2JdY}*
zFF^I^nO)P_-;b{4i{D6sudt&^<K*U@xN4K^`0fS!?#qf)T94FL`_QWyWj7MPEVXs^
z`<LKscRs{!YZPNeXB$%u9JMu%+r!W*@4PZ%N^kO~-V|*A*(~VOjsDc<UR<<qzBKW-
zekl(hDOr0NbC&3nkn2NvKJt>I=3jUA`|S0nih0}jH-(+~)r<Lx#B0)U@_UCY-1hC3
zt$x{NZ$WdU4(<RXRMgh%WS8x+WH<Yby+)ZI^7BXDmgftv{J0gLI&7*g{h>qf+9PSZ
z3@n3XpK><y2s3v2m*p1?*}-R0rihd~`lE9=!qQ7oQgQTlTXhqw(=IqKn|Uo(gzne{
z*7neWgmQ4|=U<!Ieb-SuHSPyq(GI+v79Nz)>#fuvoix=(sJ=VtU;9JMV$PELcW}BW
zqHM58CY0^dt3yUPj|O5(3`bh0_Q#N@wkq2SklO0GuBUqMvA6#^+zh(^rBKxhV=h@!
zq!YikCvAW4I}>{fwRQ5hUx+HuL7+EZn1us4TnqUf-V?gHi;11r7^STK$A6)(z1v)D
zK<Uv`3`Ov7Wr%ouxifNx_2%#)32p}vuIBr6e#wn@E)A%yF~*R;fEM_kZoSw`H5a^n
zmnIg#hUP`bkb{3k=IFixw=`4iyQ;1^q6{!p7rjmFwYNX>L(5&<{OGqsfv!ARCsU=S
z9(S>oP$Fn8<mvoLe)L5|y@83+A2Xza5|z%LLfxgbjopfypD^r|g$vi~K}<PO3<7Kj
zwKb4zTWgXXC0l9BS*A;7oH#4&2&b8j*`m$9lw5pgV8pv3oBG^^kl@%-iaIu7Q)?vB
zxP0@593`+l6!!Jq?37)~>lhMcmiaEOqv2R$=@eQ4Ne6dlH>98Ks=yq3Ep*Efzl2&5
z>c9#GGwW)$Oxw*|P=JGdL8dpbQ@NrcM;~xiSUP(yvb15ZIuk;Lz;2wFa{SH75_HG!
z2Z>uS-bC>AZd3hueoJS|1dg9R&QTR+B5?tuN}8MpnbJ@rtW_Ky%odos%?owPyuKQr
zd+`dz=?{Z=D?f+G7HydQMrS9BkK+SyR%I}RJ76M$l9lXx5ac3sUG~mE(M7KkCXU`{
z47Ux}tul*MwwqP9nFkVqS%<k-($F2zgNU^8z}f+jY!Di&F`+bH%Q{jJKN$guvR7S^
z(8P9Bn<(ctw~(fdjyCHgR47%dYzUwX0NR<OL_*>yQ=nbvXV_QMU2>t4&e#zTs+{vM
z(=w+6q=H3+vnI8*Ta!NG>Z})hirW)8B%ri}s~Ah&3O+O|uYRCBn^S3|DXy86n;Vik
z!l9^YnIrpIFm|w>H&3q7o@WJf26il3R+_w=WT_R%<U^4?#JgllgdVsG9}dnkeDvNB
zs|LIXshkQW#D5$+fmBFsGZ!7WUuo%s0XtLQ+J%HGc6@1zx#)Y9u^@~E%e-88FT)2s
z?*ND#<0HFGAf`5^7E8P`<s_wa4l2Cl=lO8~Yxe#%>=ihhX^Td~wI`TJ<bmIsIH9Ht
z1@SnBlz5()w|2&kIvRx7>kp3L$di{#O52v~%({QYHrZ-w6BKRT#elUvRJkhxbvPlG
zt25DpCY1RX4As^12s|gX!0GD=SxAUTN=1vSrj(<wg&7{VgDpahIo^Dpk5L|y85<Nf
z^=Al9;?4D9X(=xBC_q@Hj4J-1w7pQNL^3v0)KgU@qay~Wbwz6G?!EkZa!iOEne^1*
zZ2kf~ALdi9PAHClFdB}RAdcV&9#7k692_C35}*Fy!Q2EA+UyZ<K9ZHQXOOfG31<%^
zE0k@22$I&Jgcp%7h47OgqqgE%sjZ*b4?la!$j{K>a=D4MUgfkQ*qJ?}ekm@E->}GM
z*sqw&c>kZxOM<y%fEfKDD0m&T@)n$NQ?*)h58N`Sqqw@;AZy&kn-3-J#{X`3IDC0-
zf|JNd>_-)MjukoeMVtV$@^YHYB{trz26&$zBn}Xhcs)(rR8{urgh*sDeAH!eveF)Q
z#@Xbo11ewJ*w+!U)V?@0)A;iHU2F9P)|~swbY`8mSkd}Bu8PI2L&DBxJ9OXP@g?r8
zX}6^<`^XC&tD_;VFN(^x02e1nOi<WkKWyKAc)fCChJC*k?9?9GJZftjwKXVcAh_Eo
zh`C=ThhI%iYAdosZOx@v+Prp^CjW%0vW|QkFN!B@lXCtSGO3Fh*PWn%vzt>c4NsZ&
z(byy#+~bHRr@foF7j}2rX|3NA`P}njFA634O2$VeJv(uibAa^Kc|Lh2@yF4YCw}%5
z3Hl>9Nq#tUXtqqG)=_3p#SQF8qrbt{A(y(auu&3=@{lb3`hGOk1D5Z9I@odD7jx+N
zZp%)+skm<cS*jT*^B29!Iro2(l`!>v&Mr7=_Kx3ZWa;<6h)vZG+sZG_a!B~VPg`+K
zHpD=7wYU5ZOMS85hT|ewf1aw);X|t|X;`_uz9)0{&1j5MowM-4Hzo;cYhtf_hf9wi
zUZ#%i08m?Lr&O_(8(dcJw!R@fP$`xH0_FF<FO#r?^hYKKk^^Nd+2%tRxLnGf|L?l6
z@iLobv<W*(R=cg`7x-jOT^S;$qZf`#C(V}-y1(dmszl;e>ev^Ssuhu4FQT4(HchqL
zs&b)~04RsD1_N2pA>l$Nf8$yTQIr!7xg$n&<0rJ+s!zcbf47GNh4}dYvp=!_^8#;^
z&%VyWb9*@{%$EI~mULzh=j_V;lv(?^y~P6AE|_T8<9|qvkwSgavywYBYBPh`qIzk!
z72)Q0yqt<bC3AJG(7Mf8`gqEX%1gHL&>o|_2LQFs!qu5)kIDaE0X^Stb8RwWt@kCX
zy}03a0`4N^k}aL+yCL%!*<iP|ptCaj7{9Q~9#FtQAlVev)1^ftcl5Wtv&l!l4fhS)
z{kl$yo$p#nl!%hGGp``CPw;T&y)4fC?;y1`R%Ug@as99!^yA}pMo6Hg-PX2LVBM-3
zL0x&X`ff<vZM9U%p4^i~ZP~uYYT()L$c{|C9UbWNuPeBunhwt2$blx%!kcLO9T(fZ
zGw1KL$L?vpp&YYOj*KVyiP7Vg%&Mf$Z&Hal)g8lVJU{38>PLvVi(bygsCRPuTj6vu
zdiFCmqf)V`{F~3`##;7FDj;0z672RPS45$-U^-xZnqQT+9Q`3C<H-uTF6Ecb2pv!U
z9po6Hs?Jf~ZV?PZ+Po-IrL>Z9LZPFuE)+3p_h~0~V9bl$;t1q~*{inCoOKkCkR#=d
z1BL`)!_s8p;`9*wSvZHyw4OdXp)?}L6!0Qs<Mnv~lvQIw6~12x{UC7O4(zEKXOyHj
zA;280X{XCbIHn_KUkC{?Bu_81=n)Jy+>KYFH?1jv-Bxl8$lxap@5*c`aXfy@z{)lA
z{@gzri3TdRNZg`%ug=*fd^lq=&NT`pi|BI?lc8-3c2xsuPx2FZeiSRL>;O_%O;TOT
zMAmyqTtqA;wrY3kvg+e0s=gDXW{F7Kk{wYZjbP;qY~RQ!n{3P5SZmFRsPl+?-bp?U
zelM^x1p4Dn8sx<}MOg!YlX4Y$nvsf&@8nfc3T9IopIGK;I#7FdkWo*nRb-j@c&{kC
zp2*nAJ=d@`*&OpAqpTmt>?(BSlzhaw(p$!h|G}`<#X1V^Xu~bE>Nq_aMD`mrQU&};
z9f|;JmdApt{3OYp!Bku4ip8f7%4yAlPkcZbadt*z_)2ozb_vuud(;9t3(%~xZ(a>R
zJP5GW$8C`z<Rkw~n7T-IvE(xVZj9mUzUJwi2$I7QegumBB7TdM=N&<h3-fhuMb7b)
z&6xr@@nD?-tDQ#fSE8Ri7@~So$Ez|{g=}js!s8nv4UC~Gp@_UDv*Z`}31)&!G0}r4
zXr4mt6YZJ$p`Vp@S&X^yHL8SopWKlj?5f<DY~$AJ!m$a*W86w|Ds=InrmN+8+|PFd
zVv~Bz)T0Zs%IasL3dj7!#o40ACVhCu&|VBZnXKuMa6a;Z`lwAmVssyK$?*}#tpSY5
zUt#u9HpJR2$7kzu)~6)&_UWhIia*+nJup0NM_=ZOjDx+Uonnt?^`-)i(k~|061=|2
z5>MxcfcMzqi^=U?hS7hdHh=1(IKyTseICU(Ps>|;-Z<ui&F-nI{RVurtBXawR@<+3
zBd(%eG6}-fE$hnje5TI>YODXvbYs~HUSaLwxRlJkir)sE>6zC$#IPGh{jy{#d~q(x
z!fVYhvGtlAPkhq3G_&Qm)ic9zsb@M)h~~@5>_a6l$RkX(<3F2&c?1#<o(z)7YE>WF
z%a7b#+GD?Bd)99l_mHu`@8|C4i{0$DrawGv&1<e@31KjJX)aWN3#g(;Inugbb!k!Q
zP;9BKQefJ14F<Z)cn$Yi@5|+vG9NqMSl;z|_AEa7wI#2EwBy|QiAK3JI8k97JxfJ`
z`s9IU#?$qa%P|&OL4Y5dkiH^q<F7t*d9^IO|E$+0uN9z>$cWx;wYY5j`t@%^IV5_o
z5k*qxF+Afpii0#L*Hv3r!1JqVNbW;#+7C}_C@_^6o_&q^7p|uvqCWfwvpJllYeRe7
zTh9JHk(9vbWvQpFhj0UQ#*Uc%aJmFrlt%so7M^%OGJB`n>;@F)e2|AKm%sQ~%fk9_
zapunVI<G1LB&Wy5eETkDv)A0>n(Vd?h5*Wb$}JRJB(m@mwx(@HZ|Z6z(Y6q}dzwBZ
z{~=Ww`}K_*SIsHt#kUmhz|Sm+hp201h%5}Mo8%hmzm=pC*xo%?n?qoQ>QfXtZDpys
z%iD+kYjDyiRkd!WjL&!&i$`3P-I8}(E6%h({18iE^Z53KoUXR3oqAy^Il!$#;nRCk
zZFVXV=ENI`v&;9gzourm-f-!ux6&I2W-iZN>?~6xe%Zg<>y!MJ-Awd=i^das`Jd0(
za$}-MxbZb@&ks%HkT(7L!a*?jPvZ)J?pc-mYjAvc?f89<ukfboxI+utoYi(Q{+ZpX
ze4I_rFc6GpS#nqOaa~N(^6?sgc=7YwcTvrC!uH|nrf62YP-Me(b`$t?#F|mw(2d&1
zj>*1j&eWOO`lT(0QtX8f1=+b)Acy?*&Ue+;K>uG55{OX4A0vp8fh{Z%^4Ier4c(CK
z?0-`@EqKN)RN*v8t|fvxIMb#lP$EM-Pm!#j=!`PRXias4j$q@p!N|PXb2sUzVuWCi
zv7+bSRxjiiP$^%N5tLx;MZKJ>dQxAZ_c4d^I~95=t^hniec6KRa5Ix(!CqxyQUSgd
zP=0`Fo{nRhpW~+qO##W2hhn8=-iMT#F+agrU?F8;rFtlo?pBs6@AH|V@>Ee3+A)=M
znT_f>LKZ#Pb*&ypDQm{QO#m@dN(^0r&TuoJk1GU-=6Qq8NVHl?8haL5Iq^+Scm$H@
zVUs};I4GkUxXYL~WL$yMfKJllATr9Z=b>gZ;R<u3Z7PmJbfj<q_$nMc2YX%mn~@fv
zAJa~h<8J}>C#r+Q>O%0ioSwXR9`=?tje!P_VP4g3VGBQJi_!HWrrvf44&GH5rymvl
zVRP>$AvjMf!i1EnP{SmlCA9!&Q5`2Bf)<_^15TI4J+=8QtXCNS+)UH9ixH@mgnAhQ
zSjnAv*J0^s2|7Nbp5bXrBwMXHwC$GJHxLr`#rtn#w1|?0O0$h3@L(t?xCMA7HwHDp
zMYE4l?e<y+6t(o%SJA2ns(}+ogW}9qGAn%L-Op5%8k){ly6&E>yg64tMq9i(a^2;4
zRE;@;YEkG=(X}?(AF5>IuoDq8##M)lucj;nBq`4Y8P@RmOQJ*Sc}%u?(%nc^976<|
z-hHkbR5$oMc1XQs)0WH}zs}1sfHhKw0-dHBFp1=bkCr=bDHTq(XtASl%FB@xeTk;(
zIetiCD-_~&a4f1oGhPc4A6OVuah=0;h4g$gO!s`+kO~L_CMrPS@jctl6xD1Mzr|{e
zu@_^2qgy=BNBid!YA+O0214Px=_@O_8sJWV?0Wj#8kqc$7Xg{F$!a$tJ|pOwzKi-J
zV`&e3*OhxJ(@ghidpp%QvIUeFmBFE9LO~p?gq{>`LOqZ#(2gy{%b8KAu5!o(w5jdQ
z6(1BepjBCzBlvejVQeecz2I{k*SYF3%On`^m%G8)eb=)R^5hhq%gbrb9~i0A>4u-r
zu26jZ8b<si<R%iH6@=cjC498<apB@%`W{BdegUCxP(~40yB}G<w|?knk!-#(P7aiZ
zW7y?A9`|f=2LYdK6vIq~f>zrnP+JB2!e8dA91@OEEDGDb4!Ir6+xGR*wD55`B%*F_
ztQWWMAq%OrQ-SMF?>;|HFV8mYy<fcVu`F<|Fe$&A@SlLq4SrmR>Jz5|6dWmh<H84`
zQ~6#_uDx-M*V1q{XyX&Xjk>+FG1ykG!TxB)bLF#*=~`<F$<n2pa+`S>G2Gng8aH1%
zjC{r#E`P@`H<n(D#0G&doT}*(iw=AevKIxyep<05!I8U}39RpTQ}Nr3cyQ-VqG>;u
zj<ZdSN&^MzWcKQ0MjKk{!TN$nM28;+4eG0?5T#$2Sj@lipQiU+vyLi!c#n%)sq3G)
zTysFPVxzHkUkR47?C`kf!<nycZF(=t;eWg^;5PuWAeDxX_@aX?!E>e?portYObYDR
zwu(P7DXD4v)`#8yX2;Q13S1{mCftlgfixD)ZhxFeMAY1=_{ec(|E;<I;9*PJUn5uV
zzpSbP<#eO4`5OY51ArCi1X}s^A4%G$+IyX4uBt<l&@&vNIdT^b_?nl5+2e<&&kP_|
z1ykjU<!r^L4?mKm?6yLvTJT4o_2fQE(q=Z2Ku}nz-(<CRXMIlJ8VR=N-Sk!}V;vGk
zWU9l1p&49UUg&PUdk8r6$W+mhZO|7iShLt2lr`y(&SNY0N?}pEt-6w_aCn5jK*JPT
zUnr8rAynXtM&G3!1!#TxfNv7n@srvbmt9Vsq?X`gtB=1lPe^vQeX`+(pM3$zlDF{O
zw`J+W*QXK1{`S(T<oM!DrMCX{D;b%dEz&Ue^S-3^W$mZncIe0sUJYt`3qQ&DHTyaj
z_mtZzV+lUcP&>D?to3*cwUwLCI(xDx4;b7Yd^ad%T<_>w@7uaQ(XOiu0|siVtAezC
zxS<~B$M7i|R<?LGe;6O_w!T1{s1@D-)7#Ljv{NZ~qo}O{*X~X)*7af+t3CEv=M<u4
zOC+_m%KWhlqx98>V(7o0tH=8Iw2dKwz_9vTfp4~Nh?jrhc2ZlPP(XH~o_ZA>E`K6f
zyZ6Ke$?VySo7x9<W1mla%iff?h}6>DQJqPLhr*uuQF8P1{7M#tfZTo@(_1~umDhHl
zX5Zes@6+xK(VwWW@Z!IMAPc_2DePXM$g>~JD3Cl<QiF0ABuS@-u<04-FyuwcjR~O0
z&XVN_>B%j;)PCo;NG*7R5@<wn$^yx)*67_FZAsWDk#k|T=1viJ1XKew1W;G_Vf$Vz
zO?&hdx(VZ+q(A}{I0`c6RmL<g>J>e4c*-LN;phQf2X4;~JSDdysEWTDwKpTU=!DJ{
zwV#j4Z6ciC74V+b{!*(BceO2c)Uo;aJnWOU9D!dp7An%kD`7e$U}hnkAw)9RG4w>k
zS*0pcmtka^FP6Lt_t0=XBRrYVx<Sgi)TOpAFYy%PT(_e-yf4WdopvX2PBnAA-6ci|
zPUBupT!((|{gpReYOKwZjA}`fjAspJoHa@pH@fkfl{}ooqj(1@8IBd)A(myJ*~0X2
zT>8Mb59Dd5$smIu7c8qK-peY<v&`clrB7DuD5n));7Y~N`hZi!9u%VO_}$!aVFXFq
zJimO{hqy06w(3-fB~&h}THC^og3k|~)uc#ftFTT~QU9oVSUVS=TH^4@OD$E<L#u-%
z^A>C@_!!h`czv63DFzYJ2c{pE;L4c8y0@pQcu`wZ-k1yJC9fh!XG`W|GC-wQy@)by
zwz%_as<?wGgaW*bbvr1FNzbOfwx2Ix=aPft*Bw`IZVzdls!xlQx!e}S8FIgxm=E|l
zjN5lmOM210^7>%ed#)X#uN4>CgyZEufN|ZJ7iYAOn0&qzn~Q?F;Jc1~HuWz=`GT}2
z5?jf1w#KXjI2p9nS8kPYhhmN;K=ubfs6?z1aY=<+uhY3+uj&&hMtVXB{Jdn~iGme7
z)zDG}o8=*LhA<SMGhF+yyxiJtty-4Q216)XQ5LEjbm~;1Ex^4>o#M$PETXo~7>9&w
z-nXFqbEnsCt1HFulVsyWB;P|z_yVG9+!ZXF9!_0+gLI?NA>kPp4+-0aOiedDvp;pC
zTIAo@z1)l4*HI`28ruAiHI{2eJ-e+5dzzVN3|y1i+IwFrS!KO8>`HY)g(IIM+0Blv
zx%95kvO{Wd`|M<=Z*mF@$44~<s?P#bGVZ1rN1wkAmxOHSi!1CqvOyzoyasE@hLvc`
z9CE*Ud@gD2w$}Pf_f016d$a^2@Uu_YXNoL&?DEtv<=)#D$1xW6{a`HPc4IZ|SQbxb
z33povw!~$~Nt!Mth`M{$Ug)feA3q%I3~K8rYOB5TT56Nqme6JZTVhM?se^M1BR}PA
z?oh)kNR`G>>3X}ZN1of2`}mgQS>qrp7aQHel}zr7>{syCqDLV~%Ar^1+0ln@RQ$p4
zp06$C(l$c=Zp~IA1f9Xu&S1d>#zlU2&bB8<c2l$K4t^s^R!gSFkuy+Mxk-33e;2*e
zHFVUMkA%8v^hudirqlnxy8F|Xtu(ncYr;kBg#rqwt#<TJtO#fCw*pL4Zc%Bx-CMra
zk`Gd4Kl#-DwDE<Pag>QenL?R@Gb`2`w!F?u2T%)ATZ><N0hbIMv9vt-vo`$eO>hQ6
z!dI?dW3vZ8xPPpC=HgMWTnaqDXU4+Rk+)4|cKul4f9J4gS!M?y-F*2$TEWAQgw)+e
z)d%3$5l~gg`WSCWx?7bka-z+5ix&<Z_>raLP4YqMEXIkn6G)oBcTc6Z4%3}?K5<3n
ziH0OSLeD#Fmq&eennd*C>Xiq+$t7m%4JXdDrCXNoxTZpBjxD+HM|Y|g4ul6(O<mm6
zgyH1V7sc+@{UmLKfT*^vpWKyc_t)&JtO_i?ZzNqm-LNa)_(>Pl)(1BBCfO6e8e%6r
z`&XAbyZy$IIVr*RpRTw3<QFfGxhfxgMG-mD9mkCO10fhG+KbC^TRfc71GWN>RbSjW
z&dY0$Gp{}Kav#E;)a61Q2-L&TPdH?&vFo;YgiCR9`qWZhZS=<`+psQWt1>EbLmNW4
zi;lbGBv1JY9@JU2*@j8f5$_0IYLB9}hUA$`TOp;X2x3=$E%K=KSxZSo9dQ;uL3g%M
zRWtSW8Ha>}RNmD7d{;;yM0pQ{Txx5Eb~*tqZ|#cNdtNo=^a5?vXNOKC`TnRzf9-|o
z8BdEHIx%#$JA`P+8!MH`;t!sgj48Ejg9Vy(I*j;u;%!M1bP`m|mscATXaKst+xDWz
z`3)!U8|fY&T8eLuZR)y36=7Lr5$1WQ`<Tjmd(&6PErif7{U8LFP}$|EASDJqiZ&j|
zOwl2WRi3*j+t|U%Kv0GhoKVJPP?wSk3uKN}q^mIq4YQggGGmK%cO6g4#Piv(irY<&
z8D0m1A|)yYr=2+_JHCpt6fK&ro_9NpC5IHp-(YPQus=dF{^NMF$DW>o*Eo&TGs5su
zAhq->y?YIf!Zfv+LE&-xyJ18)KZKsQP#ZMIRZ|n{!aStn_6Mnj$YeL<{5I?gQhuHv
zvA06fte!%csJ*iw$5<fsH1->zSWVm(w$HZ(tSHZi8AC;pXUTx4#J42v#0~*oRt3M2
zgc4U4Fe*^x338&4un%mx-d`I4K3q}d6a5oM8+0W*%&%$7osc+v+|pE8^*^jTo-+=4
zF#!;VblWtdeer0kBMz#jqEb1ag2w{xHk{aU!1aE~taBm8^p?EwcwXqpw`nJp>FjVj
zrY|o+F&nC^W<lvV+W|ergYU=}4(~Al-LAS>+&lu4HlAw5>^eORL)&A!Qq>jzzyk_>
z$cN<EDa;&E#D?>V&{XXPVrq~iAY^f86RkR_WQb>`5SG7V`dAr9H|~?)0D$9e1=Mlq
zeLPF*Y8P7EfRW+|nF>z3zXZ;NQobDTIZVBYYHJ%tmOT%&WwAL<DF-*3hG_=dVH)UB
zZJu-UH^G83<{~m&d2C~@;ja#>D12Jl)VWxhIWCzYWwkC2f)6Iwiy!k#%q}#T^H=a-
z*9)7xVtAPXWJ8KoDd<^Z>qe`dw>5bQJraW?XXTln)tHgxEi~e)hux`kBuTf0VA8H1
z!krbVEn(+%rkxImC$@w&yqXj>I3}xw#Wyf#^YU9@*f-IgscO$XcM69Upv=|vHmE8b
zNy)K?ufSOGSv(@_7j8pM*MhGH*%+{mQRQB#k*MWYZ9&UcuD8-XnYh;6%Sq+~Ny=<;
z2e1y8M~Ce%c^%Vr)z<L4Q&*!L*0GQA`bm=kqI`w7<TFfNcrld82M1{*{Q8Xvs$DXK
z(rNbjU1{xIM?Sw*G}csa_U7-mf20dIQtOIeNam9DdyPZFwvyhp940=6n#l|&x3BqR
zBD}UDhRi%S35NseF=y<yE?YUpfIAq9-O!q>u4F<uF1v|1En~Me=o30ak7O&h@ohYm
zRJ8I%bEvJOZers*GMjokiMDpTTi5p{t+@S6%)H~tIg`cIUqNQL9YoitrJd12v$Dia
zUPGiT!)q{W``1t-!pCpq{LV`sR;6%toS@y-(;O1cc(*mXM!T)ua_L7k9_#%sdYucr
zkMFjM<k;01oF0ZZ8;VCNbtTjNyas#C|0)e7)$|1zYm485pG~8W&UPk8TO%f>27zlo
z&9<K=|1Ua}%&wyu3O@Ae)TTC)GULlQnbeTKIys%8QM$bOSfjN@vLfD|0rkWP?~cTs
zT6SCCFu%r9RV2~Z$nJoaO+0O<m&)&hmW$Z_J?NUc)am5MNAgd7<7Es)>o=PH*<0y+
zq>^v!%IEI8JJ`vmrjqQh_R=AJJ@s=$P2WN*YkqZlIkfNR#=N6+mN(y@E&nQCu==B0
zxOw4Ih-di6DTl#O*p)vykxu@)C1(<{Sp8SgPBRTS^0v&<SB|9#hlE>$seu7!7G5{X
zcFYaFS4H5b*;8BZ)f#~?*;~zG8B?Op;bS*`kP{#8viuf3RO)-(Q_G_t91Xk-AcQ^F
zQ-iS8@kR>RsyB~mX+npDhomjP>8rcrK4hYb1k0{>NO<ObsL$^_q38o4uMP>n%VxZA
zMGFCPNZ3m^j%sUpl6k0(0`wHw#k1e-ll$JxJuab0!{NQFt+5U-G?Yu^^aYMX9@Qb?
zc6v8^Lto)NhcKL#V_zJ$yB=rcKK$Mt2_y@@Pc9GKJY#L!Q!P7+!@%$4=SC;e$9Wg}
z%(%<Kp3CtX3_}rRX3kuEw{<hZP+SVsb6H;lThKK{wH2MOhG+KM82yc^20YN16iH*?
zVCZBaB6VK0COaPNj1+iC*O>>AY<z*1MM}Dnm-Fz%X2o~hB%H=W!b@*WZ{5cd>`vfy
z+#F!Kjo@5ZnDbJ=)!R=bC#K2GF%a<iI6hhWP0HR6HG{M}YmF3hQeym9lw^ZxTaVfY
zpzzbGDte<_(~ckJ=a#Eay5Z~x2}_{7+I7@Ap&*qC(r$iFKsC++N``8N#BTwfU)_B-
zE-GU;Yy!`Y{O4o{oYHV|d47rSG9sUT0L6-^GZ#liUtz<4Y>idbPzLM7+e&g-p<BUu
zZ^4DFUj5w6ee;+?52>z@dS=XwS(%sq>r5FVG$K5PJ?=<}(z<Vr(2;}(hB)pDrCE2+
zrXhK+T+PgbBHp#v(p%o)d3(4M&LV52w5xiaAQBQ&z*?%rC7<Xm#|~j@j=fcVWK~{~
zz(EoSxP(^n6Dac)RLP>+bv^pp1-*C>#_76vy&kqmL+vl0=j=hg&*BGgs_>pUX=xVp
zM3tVLs)^{i5BTORp&@abA`-Up!vW|RAnvOoZE|r94`F3*Xsjrk-U4QYZYiyiw{Fu%
zL(+`CHg8#Vh^wB^D2=-1xeBAN$w^vUvF2l07SNf_0r5xesmgQZoS<zUuEKwTpA)yS
zZn;=4UfENNX-Rt1I7Byij3M(vuc{P2($hS1KtPe$3X!uvTm_o4?L;TVK_L=3iE})T
zlWST4Kcq?V(?0}0OU@#Tb3XNn?Y7bUIC=>25^zXbHBj{W!&(}|97=ZLlyuZd3|H=P
z2dj3)Aggz6RE$7M7(T=VGJam14J9rLgoiv9LPYrx!D?rYAFpsRwc;0W4`gjkGN8TM
z47TI91$^Qt3g>K%zA#881Hq$93rPjz8aIn{1ir?k0P>0H3>aeULw?|4j(VoZBog`c
z3EhmcO$|tc7WxK4$&R!#l2J4rNrLSUL5p7%K++xg47JT6l$1nb_eq3tIK%5scy&UN
z`fwV)27{B}>hVg+uO(N<NQtX+Vh6NK3b4aZK3U9_JT!r+Ib)Xwj}AW@;s+a6D#H~u
zm=`lMfr$!hpmvD^C3uhqK}*RMb#gAg7T$|eO3+NF?5Jv2BlH5cca)h4F`Wc?T@uoy
z2RMqh5YUwD0QF~G<Afv<bD>0NNIIq>KQnJWC0V^Zqq-R~5$F%4snRg<<LA26aTiKf
zwW$seM<dxmk|7aVCQ>@8BpTpmw$gOi68snlhp`919(r@j+a5G%6_b=lsVL-b>~;v2
zBw$L!c84mzy_O295>~PX%RpBkhPoQ1PWFilBAity66Qhk!X5zMt3<ukC3tSJ4v2cb
zU~0*B&{lxtH_5N$*UJ%E78k%UKPQKLG;j6%B$z?4nQSF5@Fg$6%Mb-68~F7DU*q?~
z*%GF-fWU8)0r{L4z%GKY;f#MWN+iYW2}IeC{L5D;ZGPv<Odd@c{b3@CQiwscB+53w
ze<_HmO{mKwmY95%0(%Md4h4)m@8plKb`z-jtoaGsS7S<bz$f6b6G&qY6xpdD>1EZu
z!O>8tq{UEL9V3yAcmZVRB)?^T;yv&qZr6}w060ZcyB8TCL=(g5#>3>49-RzoG`JxP
z(%Ea|G)?MI5a#(s@U>l8k(+aTcK8s>A|ZhVBKRtj=Mi>zO6U%CBHV9sT%nxTY^(|~
zV|F6Wn~Eb!rd`7pUIDurPkhK3PcptGO`^I}p+g8h+^d@g`S4jDIA~RCxC-k7k{J^h
zs54se{!GW45~?V`LeR_rZK0cpG4#Y_h2rB#$3V`lG%Vi+DB&BW(kDrRn)ETuhDbVC
z@Hlz%Nil-@9i{K6BRnuNSt6?tDm4yPsM92jvmOQYps}ba6j4wIR-<T@n3YzcKqYkx
zvirhygl3770}?&t(HS%4<xzo{)S$IfP)^*r$dLp@dcJL3s!jC-KKidZRqLi&nqY!&
zj8v|{rsmzoj*r<*bUJz{<sl$9AtY^1j#SS~=fF_s7eSmgZN6B>4jG2mbZQ6X8a&8i
zSRH9wZX<btSN@d~j_yMZpTlIGEtNv3zEmL(<LlzT#E#<*TUf;}_L;<=WEa3!d<0FM
zGLlP}CQLm~Us06jgKv|Cb^;YN)Yqq&FeXd9WOF=h;10CbWqA&Sc8zf-cGq2dJ<rO?
zmQ#i|0iT$!O&{fZC(wrJb7-khC`8wd?6~M?6G7f{-Jq^r$`Q!8uRCo$_XRbI2&y5W
zaz-->-r@B8V!94V(ia6xyOFm5^OigU^IQ+c3htpy9{jq{_TGF|xpJHJn!H|<FmQFl
z``I9A3SO{FZwU{ZkUhg%{MsdUl-pMP{@LL;v~LEV-{n$H)mf?auS4Q{3$RPm0|l+w
zv5~-+taDZiL#(=#LYnD|6kP2I!iHlC{W6T5fX*sKSf9drS>`F{bR$GBt~n)hiw)+c
zx70pyx9BYrB#E+Hl!ck4)A34~jTiF;8ZJVKLH&*PNIc6z7FYs}v-wT@FX7j0xQ@N0
zXdbeck>R`G;dekSKDp-Y1mX^`?7o<s;7c`rsPpRFm4E2UO$xCh=$-u=hC22;_Xo}p
z`7^q~fHpP|GW&zk%(9E7_m$sOwbE`Be?Mcur^kxqv)n>|=D*txh*3LrV$j~rX38wP
zGseF_RZgqzCOJAi6X1BID)4ClcQ{_7A?(|q%(*{wmus9l;I-MoMIKDmcLHJRHAN><
z-)PY7aQ=`su<vZu3vo6rbw{6@qbH=wD<9e|8tv`_td_gH-HbxzSY)@aUVz#^msTY{
zC}~}I%B`yGJY5zSZWk4SoY>@hNQ3}wHq6w^{>hyG`aRaZ=S7y@{_M~SS8FD2_*HY(
z4)>xz?s2yGk4A~p%cU4ai9$^uW5e$a`IUc~gz$!Mhxxl5VS^$2(m&Yj`r<JAskggx
zmK%TNTK3PcLJq(5#^e$IQ8Bv%@O+8UrmreSia(7q^(hiYk}F;X3cn2GmOr^Pe5Vcq
zPO@1S&zKH%DD}?7D?rj2J^pn`>5M*A5%u{&DVMg)WP;;gI;gn(;h`YOyyO@i5ESC|
zE4ORAuY3ORC;oCO7Jl4gi74;75=jzw^$S$XTRxdOSQrSr_XxuqtnpD_+@$wR6&Ay4
z=Hnqp1;mOJMChs4Bq935tsUOh(<dQ4ERRmEyH;rz7WO5+G2(=)w8wsmw~C7^E!8y<
z%`+hlAKsNuPrTjjq<s~3OWYS^uko+g*gSoUs8$f}V9LVnPTpVW`4Es^|JVsULK!~D
zjA`lW&_$1xulrC@`TTB<hj0{=uE}d_ql_J3xSA~7Rbf__lx}pR4X}rkVbY{OV8_Rg
zz5Ahv?td3vpfJ>Cjce(Dhg042ht3|S6C~NV#}a1`2ODsC1JRxv3bww7qap)RRB%QX
zv^&$%$@Q#wjQju#_$#1s3;_}#@X7jK?oI`j6N#b2nQ^{{WStzA{X-lD9_3t<9o^;D
zB6c)>H^Ish7FDNjPbQODJDmgz-{V)*I0iyzZ|)j@<}H0TvxNND5M<Aa^A--TBm%!3
z!}IGvUS)4Heo$WwT~UtX`@C#_Dd`-MOF)>f5h{;9X7w#Sa;z?A%*U*Us0BO4iqF`*
z$U<9UQ5cUHpotYTRDi~#^;o8ydZI=Qg7TV(5elajGxl#QI+m?CcyDtGtD-^`0*ZW*
z{Iuz~;^W6iNeP9InE8jRg(Vk<t142(-i@%i#%wiEIP?claZnu$4h9}b!kP`)B<cBH
z4Co0a@_RVjP`RrTsN8)_FTDI*<j}=;ZCrt~X=A4(K~g!~lrY6BQsCHFFpnEe#pT&p
z{UDD4u++A?3tLJpSpYjE&EOG8$5BDEhMzISvgSc6>)PuA4<=|MFe4t$4DL7~<8Tgu
z<q&HgQC{Ay8dZ$^G4hhB?;xNmh0=n)d!Nn=Be44`@1hNXB6S(cR^Zv3jL1cxY1UCK
zrJ}lKO1*>suv`%o;&wn%1jW%SBQ@Mx<E)au$r48L8=<>DR<7+RZS{v##if|W?YqM3
zAyH34o2PEsFM^`aF*=_#%1rUCln-jF#~uvbUS<`Fmy89wmjoWQwIb^Vgv3eXNt=-t
z0#eeUn?9f4m@Wf8(Szo^RSYr4c@2+m%8yT7^|CT45=Z%EN(2e2jahLgL%w`?^7*6q
zaC{`~AeaJt7Zj--m#%TBiV@-&Iyk!`StgF26C?-jxB~k^NF{Rj29V(H@=aVP%1yh2
zK9Z|mYK4zBwKEWp6pfOP#d_XY4qyGwflNY*5f=~v>^bY56*vd+pFOx%^irB>wdfe1
zVIu;h7AY#9nV4(x>xNX}&oi^S_@C!}zDLoSu|TQ-4_>xFdz1p_c&i`2hF8R#M<(<1
zMXS@SC9++f&TBobTZ>?>Ee2KUdBRFmd{AhCJUR-f{i1Ulqg$2PD+mxst4U|51p5pF
zlYc99=n*<EKeG*q^Lk&)Q14kh>eRE?C*m-@1(kz<)l{S0J;(PHyCLr>Lo&N(>IBb4
zvXPg`(f_i;Vm<nwO{cZFWMG6>YgpP5JiN<>xXLB58`vNFBr0R)&6UjJYzYJvNr#_R
zm-Va<AxY$B_hYII2EZJecU!Y1Zd47ZA`uiXw_`MjayP^;r3VVH4=d@DBOcV^Vf#wf
zv=jF@79zlWWNIP(hIX7OZTlG3GuKe`-_3sCD5I3avm8sNC<55}3~O@7d|Qow5QOyD
zxMd%?*e>o?lWu)$qqbW5i);n`XYZHay(=FHgNQNbj5r_UFjBKMmm5ds1jW<AVgN$R
zoch<pXlWd`i~1v~9ZO>*cHbpWC(ZVMqgtlmN$LEHIh4qq!202#cx$egdbITEz0=D3
z!LQ|+wB>jcNb}5V*?_yOn#7>eXf>`nKhjYGH-E%OO(lVkJfDxfnEd;K?x{pOZDh%3
zU$j{dBsSj7^S7)w=J@bo=8DHZWZ8lD%(doFY4X=zT1+4O5;Y;6DQxUjq2<0YHLad_
z<#m6LXihNHJ#wMl&|K!#o7;x?EW?$SU-?MFH&J){EPlPA+qAdm&ByyP+oyMp+Y5{E
zz}9Yd=GtKP=!b0Rm)_`8f0Fq>au@{83uC^O=K8kA%At71U0qBT1E7$^^M?q#bI}bU
zN>Yml+0Qq3`PSIobCnO7v=NSfu77d&xl4kgem<D%AO-Qa_N?t+t5%#IM(9poLd;PP
z`EChK@^3CGF49#lNB@TQh^iThdlCGt*RjwBN@>Hv9{lyBDHaC6Y$jUhqTvd#XH~`k
zYAd(CaNF%u|A{Ype439|94EIncF>QwZ-A!{M7-puEWWL``@T1GX5gF71tJ!Y{eDv1
z@k7*Vu)_DelNz(m!|<)%iWB3uE-KQKcLKL8Jj4J$xoh|%pPu#9jb1N5^5`8*9M<+5
zYAdbqa}a~wK~SNz*KD3|YiRwjTeG$_Iw^<iaNc=yN?&1ZzBc5&G|C%0-$T%`Dh(er
zsIKl-9tXm7SeS51>S}k8NhY+ANk#`4KQ5F6TC9$eC#^ZJ!-ZM$I39GKst6SvZ1@(7
zq-;5{0v2}Ld^ccwo3T%{U^uE#)e%b2rM7l%a7A((T~O!sNvLxBQi6W+o;z}T0fPC8
z8<)0>$g`#J2UQ-^&s{*wZ}*X_3IG4$yFoScL&{CoOx6>0&As+Rnh6a6KbLpX5Xv}b
z+|1;bSek<~e%qYG-VwAm`=jUKt89JsQ(DzN4W27;n2`^^Kvp7nGHGs$=qvB@nvhFG
z5^(&obV$w!%b~8TPLGfj1Q~gdz^XL$T){=-voJZ_ecaaO<b^g4K}@|AKv#7axU!08
zMpvmfOfhWUV{FcK=5;u-Vs|nnC=eJ~L#YmFsrtES9r@8%8RS=CC?L9yLh2kSY+LxZ
z&<qQt=oxg>d-R}#E9gInhi|1=L0)JY67#sa;N?(GZWdJ?n|w?Tb`nq45=>VTPUT(1
z`vYK+aKZ-nSXi2kPXi2Zq54z_le{W=q|jmt1!$^i4KL>$zhW^R4jRiD5acH~ELIZl
z;Y@&d2ZA%+Mzh?8>1l-Afnr^mo(j-*=F^S=8L5=yEpx*XwT-180ku6A+zd~-Z@@C0
z?W$UXxQfR66Xy*S5|~IGlQJBQw8e_2s?ZLA8j$k#D!b(&5>=Fr3~yv^F<w4(k)8*F
zWAUOwiY2vz8+NyW=G!F`rHCZ88?6Fai^yWUC^6Uz>Q-7@{UGyIs7Gywl<IUSu{=MA
zSZzrujfHCR(5CynswzNy0pB!dAv(byvzPR)ZLa;!W2OF`UfyIeURYC7D#(&=R3xJW
zWNGT7Jac_bKD6nZwLZwY!#;hs#a61?>?cD~T@UW_nuAq{M&{KMT;h0Qkw&nTI9UTB
z2{%;{+7b2EUIZ9n18F8CL34*Aj(}>7qleMoQ6O5*4faQ}`<xJF`9+6UkJE+dqlaoP
z-SytaZbxw<4JD~*nrxbmQxSXBt<(;ZDY8{1(NPI(0tH_QLSBkHzWKO`^*mSVyB>87
znOP>5Qe=}erE0`9#;1kl2vA0~o+gLahMQ7qc%kVb#JRcIl#-?(H>;hhWuFG3(5(>a
zhh{avh+G6YipejU|8>0)kIt0L7R<uF1#pxq!tC_Qq}+^rJef~WTXXwtI>k$JNy&vI
zgfbhpJLlnKe~tQtr5A7!%VxywUCt&(VtKWbH;q^uM6#s)+F~NykAvBgeG-+%UmqpJ
ze0dK|tEVj!>aRrL>q(+Q$^Es|$-%(I^T((-Wh1a*;Mp%450u~3(bqb&zoGO_=#{|B
z)Z1%IgI6&U@^+}aj4jhI+uRWII8>RbENksI3BZ`ML1}-g&MMgFE@vvs0(m($m&g4O
z&NAo8F}@HY+ySthw#i328f@)`bMRgJz7dB0>yy@}K0D8(eJ^!?5FnEPcj?$)xy(Ja
z--fzsD-j7Gr~IT?@=3kb@S^u-Hn&dU^J*C#%=a;Y{iz@=P)Bd6S5K!F-)O_#A6UCD
zSE=t%&)N^qO-o3T!dbp)QO2*_dwb=XUCBM4{#h~$vGtA1^HkchN;!!7mHVZsH2BmD
zaaZ5&<<}oP6JfMd_qz3qIf!<EvE-K{IrkSA*wROTys*;?RHT1+A5?T#>*wE>q{^E=
z^}hME_@`;Q*<I=Q2X6>=_vcu^CRxjmxKRG}uB;97#S5Rcq`Zz=joMmVc`X|gzjm3W
zBX?)6KU;))D)r>X>li<;PKWRLu5(Y5{^qqQtBUL*zWGNG|6`4*f#d@0cwx!D<b?T9
zsjXr5ji~~h0(3=dt~COuGUgq{s6Q%`*6F^{=I{(sTTibpi(Y>SP<>Q&8{2>9MzHem
zkj_dw>5+3#VoAWb?v;xFh5wgX_jj6iP)tcAma)ek{n+(cA%*%u9&E);Ps{ELvw<w2
zMaJFMua4M>s}_9%%@s{N70~|JZ7NZ2#;Z4Z(N}@SWV18L3f!H4w7Xb*;6?dD@pNwG
zA&##-{L?G#mwzd#CLH;pES#FS(%$f_?r2?yc_d`n`q0F{_C+7hg}s)Y{FSK?{udWZ
zYcAe}aK}ZA0*!RWUzoe0zwUbP*q*f!)YhswywxjOkikM8=DK96;rEz@7ob1dn0(6W
zB4@2Yhg527`n6#-uECHVU#^hCKXCGT<HgkjU08&GKw`2QN=Rg__K&3+-ObjJxrn02
z^_KbQ-OunkVpeUc7WQ>vmJvN)uo*`{NPof><83cFYIM9Cm3#u4wG}CSbdrwvpRk3w
zYuVqpjpfc&R;o<*5DWO)jAfQh+1XvpKAQL-q1KLi;23`|nY(RtE!oI6b6FKZvJbja
z0NokV@)3Inh6;iW>#9vu_@xguw?@0we5(5xgpjLe30|d{Cn2Wf@peoaiVx!08Bl{f
zm_A4z#O9ZH4ANpTm}GI@H%CyfrZ|NP6yz6V@QX66s-2#;gJwQcMGR5?g=e=l#B3>b
zfcIz_s^j^>EOo4LFIN7u%jf_~WQCd1WE!fZ7r^w!Lj;d0T66Jf&HM^JDS7gc9n9N<
z4Ja)nLHU}D?DX=CPlukth1gw&d7<<NUj@5pF@TnGM0%TXUG$rTK_H|^ydxKVCdZ{n
z?V4fBZ>1&$Jm4xMohT`uwgn$U9tuKC8f|?NQX^z2V^<LaLp714ns`r$lVEDPLAiGL
zQiCmJh}26^t{ckZcCexf<UEr?t=Vtx!9bsOn<q^XzD_lUWQ~WgirwZHuviVQj&v@*
z5SGz;l7~wLp|y8pS2czn!1Ki0mRkDYHdLF;sUZVEX)(}^(SnqG1m#%JMgnvUx%Zr?
z;o1FW^d4Z8Rrrkf>H#IY`M4%;vecICNNq_DHQ*jNxk^?Ivf(h*^X=y-hp8DN5fVpL
zsi|Yn6QEA7Qd<d@JA$yQJU7TC<yZvy*9f990GvZ=0MS)&r?EUgQE+k)JQYh+xiuQ7
z+f5tN{%eZ{V==>UM_&siwkKkeZR#A@%6@M1*kaKKEVkL*vg4`U#ux;#F<DTR>y>Ob
zPQrwHisZ+*tYjxpNlBRhKWFa)XIW9*`>wsu?w&n8Ju`cn1{y@Bx@qKqpa+5m!vw0E
z1{)-LPzFb$@j#R}DlZvgL=r`+n+99r)s~P1b8~MFh)GL)d`2JlKCc?H#W9cML-Lsz
zjV3S2YrS3{@g`<s{t^7c`~GU5)7|r@`<&d>eRfr?T2-}b)!$WBySB#Ye5@^N2gqy%
zU7`h=<SG<(S-Y5uCl+V+A)8edX_fd`ODD!q;VB?23zfrH23ga3%Hv2#oVf;%88~v7
z5tO24SrMbg)dwVHOEObjLFB}zpT|&i$c@ju@Mx4gVw`nquNN74a$*FUT1@u(7!1t1
zLeMwAVvOVSFb`>vdu?72T_=2ygg7JV`3I>CZj}hs*wdEH`rWzD9?jZT4i2yRu96*N
zA+8E)-W_#F_$k&L!mmZYg<<wIlX93wb%*7g-)gc#PI4%+s?<R{l94b)J4p^pz3c@_
zmPwI|bW>WsXCfmwl3KwDVAR$SY=ug*yu-)FrA2;$#9!zFKEC;lb)|c+^{sYw&t#qI
z+bz5aP}Zi>@L_)uPQb;d)K)8XWP&e|y+D_y+AZ_BEyD~m!Fm#=?InQ&j^WeeX18yh
z$d_L^UXLN&-O<SHui$$nnP5qm{m|=mE6QTXky)pTM5+@%T*XANr)yJI=rbh|e9W(Q
zTYY-EEq&@setxc{WxPHhh-P6$XA6?mu|4j#mYSX;Mf3r0H@%3-(Yv{=hF!C*s2@^t
z;zno?Ms>~heY{A%GW9`6nBEY|b1V~O<FC%jv$>rykgfuaif^Si&2bCa8HrOaIlr4J
z5uIi8oH5O8<|UNK5t2rjR{xi+k%i6E^@NXKx!=MB@eIz#Q#r)AV%T?E;eX;E&LSt5
zCz(UZ(f9kxx6ak3lP6vu>Wz?ch1(Vz9=*ibN8gE{{%xmSqxM_=`nGf^a`sgY34iwt
z%g=Dmz2wm(IrlX$wkh4P+6Q=)Bn$o_R=MXd^;WI#xEPR+qwqQ652p6|JI^+Mh#dQf
z-~1sOS7YKa7Fgj_Q39mlt91toP|6|4tyw30ThP)(kZKpZ7T?tZqhyeS^Z)ag`pSlV
zLlGj4L_4NYU?hav8deVpOKtt~O&83>LHy?)A>Sk$HCt6A^o@$MaAfCb`S@qrV!H?U
z_<c}^=I!l$+hZ;jB4+yIm!#p%zm>d?8dhOK%o__a;fp(}jae_^LEhYMgyf6!&+g3a
z{BI1{{%32+_Rl{SI6=0{&)&Xst4;4+u;O6~oGhlpZFU#>spya2k=boyTb>vlVBuk%
z4DT!XNaM-jbbE+dYHQ#daM8105~Hz%Vy`x3UF|fYkMImzD6u_AV1+9E^o>M#i@A9I
zL}HCcYrDIxj?O9_Sgi2TbE8K|T-je}4#0pJmkAZSfa4}?Shm&6Hlt4ZdMamxuilNE
zYRpTd*)l{3>X78zf92^&>~$4xlV>X#mI~})*mHo_t&%GB_Um!(Wso6}D25kA4fhrt
z?U%x-4haK=J)Y0OWN!a-E<Wnk2ap|K(cHnMfj+&NsA6ZYg|ii^&lvaH(+h46^c=~)
zVJ?IzC6k&}Z7YTe85Jv3E!1mx_bU<K<3R|Oeldq^9QJvB5m;IfXph3DDasF24qo*S
z#L{CV%w{B0!KmhcUA;|+4Z%@e;y+9(9yz$bpbHu9=#t-H{IVJZb2!uw2b&^wUH&In
ztJVm&2e8}flm{TN&lR<WOfEq2U{Ag{Og@H`#k%r{<sx}ed@;kK<KRMYEfyz)k*DLi
zFux0?=|Y4E@poEA_oJBP+#K{0XEkeen8QJ#WD|IPj-TBVc?h1x8##M`q5#rktCX{l
z5uZaT$NO~nEzLV+1-G{-j}o2(82xNqkG_gkWZQ$2At+9Zvrbuq9<hF9LAJ3dCM=xR
z9ckb_k3Gw(%)*Hii7qB7veJ4%Gaoo4nn9nrvndgk08tTx(~y!(Wj>A5WOD1==kckl
zuJ9%D<Y0mYm`n&kl~d4heyV-GI&UmdwIuKfMGAd;n0Cjzzj*-J2gExm0)$02a02pH
zm8zLYdVq2Tbc~Q$m=Z^VpvT4h9sv<6WgSP<C{+rcpQZd%&(O^yEC|sLcm*AODOo@;
zp<DY(f-cer3dwb^F0)~lN?Vp$3!lhWiDi_qk&l=f=yVExqBp)91F<R#o?kYI$UC{F
zh9%zw$99Fopu-~GtqUNSpS5EeX=%|bnQu_WaN_0US9K-PFIKQL*pj}j@erP^EL1Hp
zY1-xxCN1XDLFN($8xoboj|2ST3c_(7Cq_W-x;_b2MRJY^JX%UXzu4(aV2KcT1_ZMt
z7i5yyaOZHcP<?_I-C7nr-x#T)^XR0GB-9`>%`{g_0qZ*O{k~_UN;pD1B@q&>P1ZZf
zdYy6@V34PQRob|Ng$B+_25OfyQi8Vh9Z<E`3JBk|Mnqc~Nwn>o(8`N|aI_$-^!kAi
zlT){?SPOL&T>wXq^e9RRbDi}bU4rAys3s~053(-3yd$=|F1PJCZ9zHIRHKM<BlaKL
z%#AwD^A^3^O8bfvnZ;l_;=5Kz$0t@{lvnt(<min>3*Vt7NI7I0RZkyBi}5!?`_;U|
z&zYELwj`3SB~tF3<BVJ%vU8F!XVW4N;q;jfch3ANG`crY<jP6$As3qMd|s2eB>nbC
zaaQ@C2>I<@<6K)xCH{6^&;I&~n0yhodd1>9G3C~1{wTT93`;Kxmlq%PHe-isBZIvo
zz^l+kb(*FN9!oXt{|btzURmu4RHit)hmRc1C9!kQk6|cB3;cL#Fs+osn|3&K3*`JD
zr&OPKJ+dKszG=aCrF4;Jx;wSz4=ht`eMp$tQCq7`GLlhTg0bb3vUy^#h5zR5;Ndx2
z`pC{aoN+_a@c6z7ZP^w2HX|gvVA&i$dl#>LcFu*$xfukPf4@*E_~eGYmceMC*4Wok
zVCn~GjP&lUX~t<g`#jbluCu0ZQM`Y)J6rhlW2_?n;N>pt_>8lI|1bAv!1B$1er-}*
zO9TnAG_PB#WpmfRxA4R7@YdMNZtHE^qo$I_acVQZNU`4i5a*aU`qS@dJ=MoBPWhC8
zl*y?5Mf7G5h1I*Qib|#N`KfzMZEsb7)Vc#|t78Gcmq;?zj{55RpT!3r&$W3OB8D>l
zcO*+H$$fh{rh_H$^Hie9IQGcTC13KcoMKI7$J_Ed97wvSP~{EB;4A(jvh2bSE~jC=
z4OB01q!@Kk2*W364{CBusKXn7B2BZO&+Mgd(GoqiB<$jwp6|aT^=@X|E+oU@&+kGw
z&u%NyKij?Ne(q@t_bIi}OWgymnWR2S9mMCC(HCC*28#9Y5FeBo97`8ibm`e^I)cu;
z!<<Yz`-5Cbb=6UG1uuNnBOa-&n?55ukD4le1aE)YSqGGINDQ&7j2$sOw5De|%fZ5s
zie9ktX&$U7MhsnZ473`ZC{6@1Srtn8+V$SPV!VqAZ%ZcZ@hggK<;Kv(QQqQ=LC_9t
zkLft$>d?WqPD}R!2I~Y}RPzQFm3}Q6jsh9}dkf9wS23}9g=%<>9`Jg7O5)bENFJ4H
zhbCF>o;G_nSbF#z>eimlr;fv01MN%%UHDp>zNATaV=oOnSiOCclk8p34NW+c=IbyV
zrw1594@%f;&=o0B9qqA3a<r|9Qw^pI-gRv<B?&JJ@s={{5>2e<L|;;zcBRk)@Igi?
zf?g0H@Gu$on3byv+;K9{S=C@i)pv<0pdhM?QL;sFnA*?o39GD0OOb=P+R7b+QMY}Z
zKf$DNvKv(v)w{%;QVL!Z@G4z1cXDiBp-UQLOP0{(=|O{EPWX(HMC(^mU86kCrqc4l
z4kKe`+Hq-3?g&|B#46T7ZDNFq+^v%E?LA*P^ma^PEgT+AV1cVZt2mW^pbB_c2THY~
z(BLy=LIYAN`v9`ax%z8^NSz))V6UsP@hoaK$BJ1oSE9$QVnfml(b4J_Yif79Cxvnm
zzxiXDmKZBh19}w?Yyi7rmujf3(W$bK2NyE)MBpmGt)TK54ktG8UZ7d4Im}9-uHq1a
z;2geTVqI8}S}b8TsX2W>xsGPM!4lgVL`K(~Yr<H=9c^>09d$4vn!~oW#Nzn{`S6ho
zC$?_p*G3c-FbmGK(s5o3cQ;ePSDtINx$8d8bRC+8-FuYZB(B&7i8BNqB%P!!GpD+I
zb(dCBPxbkYgB2!OX~B@I9Gg7J5Gh2u;W69N>X6bKxR|v9KR0GIC1!7;5LNPNgWO6K
zF`$<vOM*p<nwDV=JcV&JnQ9IJi)GBC-V9@j9Ge31d!i-4lIX&w#HLg>1+vlg@75{t
zz^lkrE&^gDttwv=n57(~>wHN+;juaiIRYV_LRVu~2f2aay7<@yl(=Ftt5~%JfJYWE
zEpjDG7hspkP6SVP!d#QXk3B(&gbtPKm@)2XcYI(zMpB}XCnSl(i7Y@<pPt1gJ`UrN
z2Q0XpbYHK28devC%Z3xXTNZ1_C*{?sEWMw^C!#5Y(q5ZAFH`6dp0e?JtDl2nF%z9Y
z(P%%visQ(%)dC}b_(qoK+Zx_pOfGI={Y87LhwtR8n(aI3DehoZkz>Qb&ZL!bNSK`g
ziLM89lFh@-oPS-Ji_{XBK#Ff=TLIPH#w`NuY#awZe8c&Kut^)gaI-q_9uQPJ<CIz<
zUY0FkP#C^G`$~ro4zG8{U&7alV!fWR@w7Q$zT6!wEKl%pbdB(PQlE@=+sj^iVq`_b
zt>D|kSw8urF1Y1!8(P_(-onLBMQyLr=mCK*0N4edw)(ux8VqOya|5eE{PlW$5GOlb
z+L2uK*w}(7f_x=6$1mKi?Qvpw20Myn`N~Ue1eNCDlXPsB<D!kYC06@NNW$Gaw(_>C
z^U|aW^q@tOosCMcV%QW&b^&<~J+{Y7J!%htfQ3NXRSY=BUch}zGhe)xeT45rtN3Ex
zFaz%NhR;~SZflX=z0>%T2<Tow>{&Oi{FgbR3BnWG)H!dgHY*ObQ1##Y2C_f?IZmux
zXLilvgmFkXvt8d!Q$*_Gsnbu`_UZuXzMFOxGk-Io2^aI%6&_1l=IyG>EomG<^Jj<8
zp^ZB6y(yqdFD&1{zSJV^^oo&*{F3*Vs{x#B2#D8j;TK`|1s<x5gq_M$r6MLeF>s&N
zyG;9`WjW3J;RsuWAK*8Hx!b8Xo!!>J)l@-&8vQ3L{-hM|J2K!&Hk3qs#+`*-Ln88+
z<gTXT^Iv&yQQL8s`M8mfnEV+xSnfL{FB8iT{Lx_s!ZBxS^;_N>K-`_jFI@eu*vBe{
zrIVgNQYvq)T{V0BZ+0dYzQ42m#}7P|*!T_>8osx4I{Y6$v&)e;C+Q3~+r?<uKal0@
zsAmWNDw&tmZR;;s#{0`=4_}6YaCj&LH@GiHZEfP&8)n{-+e9T?OY7wfA;jDo3`f=O
z$Qoi}o7h<gIU9s7x={`Xk5GW+Ktl_8S@QU)tEr%F)|gKE{{X)`?L0bSmx7Vf*&gUC
zStTJty7`mC?TlwDl~NoY5Aup0`VwW!ifzXF;X<`+Ng|>A=jozL5>2~rz$fjG^f96<
zT-j;XSz}Au#tp8_{<0&6pryWV|0q#?pN}i747tqit)=$N^Fr$Hq<j%br|z)C`FIwR
z_IDV557pw-+S}fV!oD^*WT>r9YHQ-vkLbO*ULeleac)gWa*2wh`m;JjPU7&rqd7L2
z)$nXy9OV}orgSwsiP5^sds4>m{kVc`0t(0Jrdk(Wy&la<t*(o%U|k%(1wN}xRJVv>
zWFvC{{z9s}8{uY8+~K-T$jyurqS)4h(uombrj{*UT)7hp&oUZ*x_q%UrW{zuH%w)E
zepR7f-(^!y)*=)}v9(x3rg&18%byTNXxi;eKLyg|r3%$#2~#nwLPsnZq1u^U_36hF
z-wlLtxhh2TN}GuZvhQ{h*{xu#QJD#EyUxlA8R^ZLw;)?zpvYRHR5Q;B3ItXbWNH!^
z@Zf~4%~>f7lNG#jeVeg@7WJpqu}6}ArV=cj6!F!Lk&A7@&aQ%=i})Q@k7>+WC$zy9
zv!oKv*kuU3gXl8)WZN%p0oQz9G-rAJwX;X~un<XT(|t)5^GusqCz+3AeLTV%jc#mS
z53X_)eV(0JAGBjfZ4Di3S($@&H`%#&JAF#WBR1W3bVNaP(bse>eVEj_4g^I@8BccH
zu8WtsnxyYwS20!bSJ<hk7PEs@k}m0qOjjXuDrT)?2NRrmyVgdmLIny{D+$_(@)1Sl
zb#@g67<(@X9j#r>p3eis;5^}|h+L2v3;bdhy;Z6Z?oC1YA)s?hTnozaokFfIRGFoU
z*?yrqRjccJLK9w(8kWK_RGmc`W~qL?k4xlQm$aJP{{jRuA0Dd$)@97<0pm_)l#DD@
z#$*GO(5jD_mk{F-NO^7wq4I4h1jl2KqSa?g+_)1iq4{fm2*Hxv8j**mWBw|UE*2>}
z-5#GP229Jciic{7tl}TFa`ESmVO^9b1Tx4D1K{Y?F-Dbs1)7BcS-5NbLv?MUMn)oT
z!w2gj>-O)G_8aPv^r`I0ggs4jFCrf+b9Bp>R0}ckEl^U87m<jbdxUtmRr4C)h_&PS
z-RS7!;Umooxj<|{K=IAABk1H(vYwO3BmxE6vJ<j<Hcj)mm|fR~!?~N;C5_&jK76$;
zo2J%Yc|OOpy2L}2$-Q(_Zp3-zt?;Aig5UegD|X*V(T)?)9~MC$z<fV<9Op^0HEd~+
zY<Mk0-Qr2rsBhn#7_sI#Y4UX@N$JW!xXw*eSlUGGqa2zLhSL{+(mQ*=W%dO|_YQYb
zTjj_fd`>gQEuOulp5V2+IjoxD3}yH3YI{USJmt~Oe%4S96AR~Z8d}kLek0OL9NI>u
z2XVG@f@FDX(OEpd3rSB1P=uJQZUesQMILv&i|2kUhDWB?EsL9W_>jLl)h2H>_VEI3
z5=7F~RQ&VkZ~lPOgcMD0KyA%RN6G#0jhvK#UduTH&!@kA8=Gn$RwCrh&Sh}Vr<ewQ
zbA(yo<;lV)|2~-v<<78_p}e&0iln%1(87n`%A)p1SbtFwH2*gBVR>gU{jKrLE<SQL
z6R+(_eU@VN_-+mv%N?&vQvbzTF*|)`w(rugb*>vi;)hL3&>vlyz*#@wuYY;frK#WO
zE+)i{Q=RGFa<UKmjue^7xH>kgL@3cbjQ^Gm{VKby<LtkBVN~kP2WzgMRI98?gmK}6
zASJ)^-!hs_uaK->D3-?)Hx0Dxls%R@e6^+PqCzc43`^|_e?+=(V%gRS+XEbxp=j~Z
zGONuJ7o7mPS@PS{GP`6*3nMXajJ1O{^T;?O9lNa;)pitPe{h%c{)apB{2P}C-*`F=
z;mZeO?X&iu5Qu-vZ=W&$c<Swm=6I#Hex8c<$fG@2>Uz(-gQ;{Qi8r>o;a>>gUFF9@
zUIk}TefoQ^9r~lvT@iy6uQpDfLUspsXZ5*%NxT$Gz5l7bRf>RRCHtqur7J(iR>3XS
zsxbHvD9GpuG%-tqX0Llz$97k~gjvTCl!lhP_fYmnuCQ(GJKL%;L7#EdtxXlgu*&*<
zZ?VDlM_8xncx+;LPj8<Ek9bDk7wH_&sJ|}1lKvD0T!(~5hnBC&XUYTf)5dPAEz|!W
zeq(rG;M;-qV6Bbr$<yRsO`HU`iC4i_$oh>Ffqme>hJ3K(=Ld$0_K+WLR{onkU8T0Z
zK23<8nubtTA<&htfzQI4V<X#fBypS=V)1$(`6ZMHf~PT9Ndrm}rcOcq0L33``#g<2
z4&ol9k%9C&S^5ESn@k*496k#m7fH!fl7b1Nn-t8d#?6Q!nsbDbr#e#6hNI#U@_3NM
zxE43klXMHG^l^~<JlUXmDv2bm@@@2uVnkm)vwWO=x)RPDbZc;4Hx5H>C0qs5M290I
zC{eMr(I>?95YhUH<3f<@xeD1kx}z!rV|L_2qO&w(xOyvB*$>rRYNvGs&|y6HQ0RcY
zIoJ>RMQCUZQ2#z?!9F3n1t_)EAqp4HCwau7D|W{Hp{je2XH1h=6_iQ~@e6_ozk~&T
zd&2{eFl6wv!BydOWKg}Te37aYpAaenwb_W1<~qoAJ%wA`ZuX&;Ehz8;nr#=nk15}S
zJ6fCtLi!opyRI&~RGXSUHX2o5w*(<Sl3xYawFNA`>*&)Aq8qM={kq@@s&(9`E2!Bn
z`g85p=$Jn7*1{RPATpUv;Yg!@KMzqh>=c_6aTG@tDwBr<9g;@m$9KiAwGk>(uBLNT
zN(p>qF`PU$gSsbPt9hH_P=HfPjtmTkVYi<g<1P|jMZSAXNzM{0Y7BQQ;q@ePcI32$
z+qBz?q;zr9wbc%5O=x0n@>I>sf?Uc&i#q96>n*4az<JAzWJC1#>*_iPaUsa~`Grmy
zMNEH>ioJ?fSrcTkh+oAXWMV{5AMKq-bR30Q?|YoRRbkv(Q>_sGWK4DP0{ZuLfVij#
zM;{!D-et`9Xw{#t3vjG8bP>e_y{ns&)5rg~?-e99en|tLg|-d@pJnk&uR6uyAoa5W
z8O$N`oGEjn@Ug@OWa~&hjzc0dG+S;y#Nr~QC^iDGc%0*B1GII>>T9GOwY425LC<XS
zYd)LVI#Um`l_}=W*NU{Qqqq}Te28kR*m^OY?j2L|wV~#nP2(Uf8D)-<lvIZB^RsPD
zv4++w!I5~QM+^NR+<diF7g!Rz;3-S=-38_(&W702jFYtFma4u^bB$7AkIY3%)K+nY
zaN8tbdqozav*Wk1aR<e=vL$&uT(C-$H}>R?b9dQTUSz&_i4oHa9s4l!3Jor9(IhQ>
zl$Lz>oclAI!1v@@yiwEa2D<37d)3YWVfLuFKSv{2c^{RtG0~7Vs`}Uq*e9@7G6Pxo
z4Ia;~(RbC>toRDA5B^|x@{yx!`x@nX8!8Q}WMDeC@;G_wDDDDgc>no^+B&|3O2fS9
z-H1^&N)e|od{utW)^``|R-MK7l%%PAi;McozE)<<9&Bt`m}f7yHTl#)O6>Eb=7^yg
z8mDsS-eu+w{0|Pt&;2GdlDE&rWUoT&$u9Z+yqXKm>1B43lSOLl;@Mb~i5@V$_1(_=
zGgO2xeAaY{mm1sL)jOCSyggwjXToOgenU!jc-QtCrhfj6X>z(dZQM_>F8vdV!0?4W
zyU4aPF&wm?I_;--dCn1Yp&rp3oM$?DE4GEps18SJc^II(L~RY#^3>+64Y4ijpO{Hg
zchzO%wr@Eef{sC)p4259_NJ}vAa_sj*HaK39ni|DUo$Nj>2@Wrpf5Njd)<vk=B|y!
zCAm3a(H|=fS6ZMjVPN-^O1*upblrYH%L}&U`OOB}X$YMV+@|cWT)~3^3{qRsmcya$
z!Cq<0_WEDYj0cb;)eOQPx6ya^@aPReH&2f~{v0m>4_snt>_Ab#=XX>UyZyDZO`kMc
zT>3d~`+EN+Ro?6$c8(jI%}gnQA>K(oFi)~i=SBMw4%4>3M&%P{ip@X4WBz$|jSdNi
zIbQ4_!Lb&|o^Zq4GJ45mtMMwWE#Fb`c2ub1$VkxE;8Dm89gljLtlC&^kDnzvAJtab
znm_7%xShJPqWaPW^v6+Q3beoqzh4oY$^3_oxIYjfw-HD?4V@6I+tKEZ;8I7NNOdET
zt!T?WQj`?9zfgVjdbm&AO|8dlY_B@?yV7Q!l{Vd_^PRjUhmuVD#?9<&31a=*bUac#
zz0Dk)#jbR~bj&ae*I8?11@b>baJ>ywo6Xq6{kgY8C-aGwmj-xc>Ks*ljGoZeDExCN
zox*FZ@MnmAt!QcX$iQ>oCZN{U4=nL{zGLXT?;--sIvo0~0>dh=_qDrj_%CK4iI?!g
zS>Ld45q4u2rXZd~qVUuX1Gyjr-U+8HcUbgsG3&S#I^mAPAB*6uHmhZdOL2CfiaJpj
zFdPS;b=r?htE}e%Vp18qcMwJ+5FiX!E1-)V?!b@6>5i8eGBQAr1j0UG1Uk*r0;94M
zJ)zfuBJv<lod0!%U2A)_(8lbnV@hSANNO%?c1gRYc8Vjo_~cAih?alH!#7%@rUiCE
z3q>xY{2XJ_I39~6f^HEa0on5U9%xiLx<R_;Y}c~687R5hU~t66O;W40mDtlkA2Hr3
zCF;@rDbF`uOmDqPDh!V5j-Nkc0-eL%K*NMzgE|8RNl>JL1ikeE0pe-aUdVB(T|?#-
zT~HE1jtPEo%#&j?cmxS5{opZ%JlP2qhpNhTh1`lqp2d7-LClX<iD()OsHHJ~N`mUv
zc6y-BmC5qk7?f<C<xMuf*iS=D&A3?3RLOagMJURYJiL}0H1ZYBSzAX=RP1$YsSOO_
z5DC!fFJ;{jyuMjawNSaJ-otVwq_*s2#OlbR<%yBRlt9%*c<ff=iLWxM7UR)lNL;ZA
z>lIuvL}5k}QgI>)MtnU0&Z<J2O&SUyVXlIj@RLd-fo~D^hO5Pl7RQu4&ru)4kS{!3
z0q-etCAv}Xz@;SND3Ku2puG<uL8+^UP%)o+p?bkjRx+q!hd2v7$i5h_gp+1fvcZxz
z9it79VotK2(GL=Ci!g>bRk%07K|2QT^#~bRP+X>}q2#I%lPp3wS?M3hNs{IggTrA-
z3ydYHPxeWqyb=gLh{cTTJ4|BZxDw2GIhZGjvxL4`FP3W(1aTs-&A<<IL<vzH5qK8b
zSLrotxrAS-s;J3GZy+NgJiss1f+~r_x)y`#VnoYhMP6HIzmf^0nRA%Q7M7sE_!91G
zeD#6?=mjy^bd1<TfHp&MX<&N(Qeqf8z+^0XWH#v?NmHNl;*v<fBB8E*5?^zKi7Y#O
zdc!3u2&9&DNR^x*<LA2Q+?axOFv5{Ag+(tEwHV%!*VqSS;0RO&lR!#E3-cXe;$Y5P
zkzn5(J|)hagqu);T;;I7ST_%PB429BQK0JDDU~2DHSzNNV7Bro<<L~r$@0Gp5?j9@
zk$Dk|2SJEW9?sxV*j19Q&xy^Zjd=wph(al&F_)N(Xjbww?&hgr6_bG}f{<{XxlY!*
z5qNn>ATc&MB(s(*f>_>_b+e~Gny>+Fm$ObV=Qay}jGsp?Yfwq(*fH6wLUwZj{X792
zt1|FR#qB2NG!PyY8w8s|t~e!)bPl61C+D0eT0A_aO2DEiy9BhvFDRJfSHXN``0*~H
zmnqJ(Ds48&s{)Q;l)wnT(5=`Jt4F~qZ&0y`gt19aKo|j~y#dt0hYkFWLdPh42jyhO
zhb%D$6@dCn-z|&ivGHTrRfHN|n*<7JBC%N=yH65conqi@7QXV(qE(xpX>>xqx~$$?
z+eZwVLomj5`S${9bR-<24mII`xFXb%Lgj(88EhbWjJnli<Itl-=oyiP7b^pd$k$hG
zEk?58<Ma4vvK>^IY0^MWSjmcVQm;JNx>0$hxK~MqiKIzZP1C)Erm-j|kPnItl32{j
zzDnQm3n>rHMx!bFMo`8uWn{-zdxT@Do#J6e(KEVZ16~-}QP>Jfme!f}7s<uALkCG0
z!zS{D9Yh9Jn#!uL1JN6l^(XlSbzu5+;5>OyeSDl7Nb(0e%s3|!?W1?Vce58K-&DQc
z;1rj7NmUOYO}LL85F>h(2VdAY(^48o#t@|dV}2L?Dtngd8RONndhK(%6TE9A!69((
zJuN#GYXuGa0S4z=6h|+}l2&Z@<SuGcjsOzHao~@`^h9X(EU9(77dhutY3Gg!n%0F7
zS&&7U4_zi)#Ps`EmsCu;8;f<K8Eh)1lAjm@+VOeR!^?H3<A0RTv5xgLou$K75;zG9
z(bb^#P{=yqPv@>eNh@|H>AZ_^O?roGtKp8a1j~nP*b7JP8JUk|Q`MuR=#F&+A<pM_
z(9AhGjs<VaDg0=Es~_N&&bV<BX~Vl<8EBm3SPDeMi&K`kp8&H5(LSh4&H?|$DP*#T
zba;`D)iE4*DDz|`d^ki)?}sj$JHm+3>P%ALIV;c74Km*BNZ<j4x9OFMsc7d)K4?C5
z3L2LV<Os4;C~<vPENsgoXBB#r=Sq?|_M*H$fTjc;S@iy$SpI5jS}b1^oWIM_EU)8G
z=;)PbwbyvFyXXy`sd>J(!S)i@8DutBn*VhI9R=;vcjYUTAbUL_4O@H?9xl>&+Y8mB
zH#{y9R+jzVts%W%XF59|$>Pf6M$W^h8$##<;#sh7AwkjZcxxgV#$|Y|{(tJ(TKdG-
zPjxI<Q(<)tj1qaj)`+wBq;B#lWK+FT<;>#~PnOB-3G9mSRR^XbjZ=vWa(?lptj^gq
z|DdAy0G)sL22y?8Az3*{|MtY|U8kpbZEm;HgC8u<YKy!VjOYlOo7*`zyhs*iJLHdC
z%8tel=x1-!DZA$=zbh}a(T88jJmptj!HZwd&H3_~Ewyb=+?8H<@VTj0xFWN3l4~oR
zB9K5-2L4GJ@Grv5$iIemS$@#cncs!^NAVX)FKB;siU}hh4OzT_4*$usy7U}n+_8{8
z@@QxsP@j3-^Sd6Knr-{oTO(W5i*AxB5U+9(GjS(wg+mZ3V=`WC+njP9^97NPeg8Dm
zXB_jm$AZY>9*bh=35xxU{a$lXe-p9O*wT3JPn$zJ_Bf**p185}j9IxfI2jB7!2h^A
zj-)d~Z>O1wWat0~Sp$}SV1)X+ICpPIC%<p$O|PtJ)UhY-%<bT_mWHWOH$8lZH@oUL
zZ2U)_Tkzrcci2Vb&9}>eM+Uz4s>R}r+r9Z5kqthNLwdoIpcsa!7;myynf>x;u8)Y8
zPpXX5-7PD=lK8OJ@<e=M=p4TcmVKreaJHHsW`l^TJ!C_*k~d(N=Y3zTbxb{Wgd;p#
z)Ha<&yrt@GwI@T5$aof5>QG6fD?C>&%ky(Z>fS<)rfXL3;n-1c>il8<Q2uyuky^29
z5<?7mJXC!eHRUN#(PIymH$)07Urg1s5hpjXR=Y*%_={XIL4Vg9+MF1-tsaK!I~L8Z
zj14w#Y;#3<Is2P_%3FI!Af7?yo1aSxn;D<e?bS=^JEm;(8D6%vccg6*SePLDv4+WU
zK^|h0oz;w(?^&kb^wh=6&4u%rZ;HML=$_S>v0bVJSNL?`m;fRAMr1!ZWiU`S1*%l^
zim^YWy9Ma6WC$E(3#2wJGp50Jxv080N|ccpk{BGmeS@D<bMc}NG1634BKNG&2t{<7
zpnzGBj}pNi!Fw5`7|+$BhQ+YatJlLZk9DI^QE-YgUbwIGX@j95C;vni5(h6NSIp0L
zCWOl0MAFIRqQZiSfEYu&V-He6^0t()2(E+Q%m^__D9|(u(sZP<2EMZ9i3+>kmB5<+
ziEUlptVQIS_;w`ZLlSIk7)jnlz!;l~p(ODDskLf;R2j>_gb6yOzM2dHD=4E>nZpuV
z`i2|yT`wH6w)iDAOLR+SOx`-3hCC&LIcKrOd5^Ovu-ePb2&%0en3H*P*F_r40E?Tr
zA&-R?nDR=s#FksIH-q3EGp9nI0yjf6J{D_L5%5(_i9lPQGsmAK`C}M8p{R98ym=xn
z*9V9zkh!l=Nyl7IaJ-#NrePJ`ShcYbgMExz;|F;$rD5E1At1Yx(ZcNpSpes7g;qrU
z`ya(4G0b2U(ywKWyn!q(vU?}R2g0eKRqNC_E$wySD%xJ7p}Tc@0L!_e84fBnGO`LE
zkUlDnWUITGJECuLX6<?E+=$j2ZpA05vGqGf)ssm61J420W0ps((Z;UE#giCdH5I#*
zbI|jALOPn4^@fint*Yia%jeWVDV_?vjI7fHv~SrPqP)`e0->BEtcGT|5n>&UdIH?z
zvlyW(aW7;)84z6s(oEJvHz!?lEzNEsqMlqIM0Ty&ntkc$xP&?mLWK$KD0dn`qeBv7
zpq+3(o*~jo;gkjxf+&2QL57)2(#WukgMr0F63IM|E<}uc#Y$*)(5>~%cS(;kSBcbh
z(-9wXoyzPqTbg?{iD}Y-+B$|$Pe|A6w}Z?m6sT$nKLzj0bh-z2PEXid?om`hU((Rq
z8naXFf5Eac=T!znc1PCKJXzP)dCWfHF)9?VoSoezFRSJ{hCaK*Yze8}Of`*DvMxzH
zTO-Gji3;U*jSmh}05;tv+1PZ_yt9?dM~m89X<bh~FIJ#%`8|OTcqBvN`E*hLjPk-6
zK+C>AFfAz#lUwBQ^0xWAnyLMe71cYo>`LvEbm-r(1y)znkV27%AvA1`N~G;PueZ)-
zW_2muh^Ddf-W)=_%`_{o^@+_8Vi={b+mf#1;LHW@UO?&O#v9buSVEge2g$2hwoqja
z{QSbpB8wiobc^P}zqIW0Q`>Fu1DvIEBH~LLL6?*+4t_dMP)MrR5SY{Z8BwIWtG1&E
zHUS9nZG3z>JXG@8%nSz-_A6H~hs55wfz%JZ@-vf-I@)rcR1~(-{vb<ok)&eTvi-a%
z<;O+P6S5a@$Z_s_FXlq6chJ#&v6i$*_5JT*sqjcrHokslurm%!dCM-$vdQPJ48`~m
z!|c0VqxA;X3BLM9YaDzovHAC$YD4emE|S*6<H09LUA1FYL&$&S%)yO6pswCF;CQ7f
znA@8a^;mf}WiArNgMTwyZ(p!h@`6m07(uxHCCnFJhHn1cIfZ@fJl9W7hup``tJw02
z<EjVrjPH%b9%c2lxvu`G^M`FIsgu9`e7+v`cZpj>ZGGsJcUNaS3l88(=)Itb`tA95
zUeQ_jsOVKobf%Gd!^x->#6+_C5~UhNmA6)#RRl8TA*m)2wO@3$>$!CLUe%2rFwD&{
zT-KA>{38$9*8N}mkm!?ZE}OA~{~y~!yH2j#DHl^ngJ+mudU&)5mt^+Ah0CovYWuyN
z)>`DonJL<7I(Ve81BYvAC<YeWO4@y6-16;A8|&X@n&n?;cFyH=+5Z`@J~)en)#1)d
zi{g{tB#ACupE$lhWNG+4HdfF^*L=DZCouEni8U<8n=2ORcVg(cO7|25L29G)#}#cc
z@3gJs&Ec}%zS*VvY~t4T8>*hDx}sz)!i{V`>bK!y<{pZ@f}z?S<}`vlAZ<B20yb<3
zRkETWZ@%`<`OZwBItaLA&!m3frpp=f`T?C~93EeAMYC|Z%_xt~{Q2fT&*DZ6^`WjE
zs~6f}$m18k#&!(5l~*ymAds=;+IUv})f8*R6Pad4_l%$6S={Ipn!k-*fZ1tl+w)ke
z{~GdJ+G+aqq}Tb}UJxLBTEZO)xlir8N7H9;IRLBF=c)}J?R~uK$zxE9RfiF@;;h{g
zAN`3gz-Q$k2}>4<o~f!2vlKw!^m?2L(%me?0DV0?eILoi`cuUnGGfpIyX!^}+35(5
z&Y2}(zaqb6ZAJ(=KC8NgTs<I<J^dO{)$DOQ;o>I;NY_Uy&sZ_J4|HJp+JVK&Tmsq!
z823m!&aRP9K=9E&C>~Zu8Qbm#-&$o~{u=;VW!%9gXhS5#y#~R@7SB_VRK})Hy)3mJ
zqKZVMQC5Cl(=r_dZdn#scuA<l-o6O3Xc4L|jgkx(hv_#Rh{z3nXK&CeX^V_OQ2L{&
z;{v5}A#J%;@nP#;BP^q^3yCmJrCKPE<JNM0<+hcyl~^qv_=52{xmt))-Ky+Eqd0(>
zxRt+1$@s6xErv2yLhepDgR?cVJS^<$@k`|-w83B&Qf6J6vIsSnx?Ny;g16NB^LhW<
zX6gPVlVmN7PU1yLt)Vuxh3Feg@Wgbb&>f|6l_G2DltQdiq$YK?-m-<bjD{ZHokp*c
zpV$&xq1Xr7;(%Xt2!SQ=Oh{xBd-Rk6wr1SVhpp6c3W2tRjdv8IW77vo*2OGDzJ&@?
z)B=$SCJwdn$cMw${ALP7C~gVTp`{28)4A+48)}v6q=Xi4gjvKIsQC1>w1D%fb&4lJ
zdKW_nXnF&Kc}Sd#gpNB&Eb$9t#|Epidn|TCcR1RI%&&*@E52xfO`*jx@y`d$Sccs(
zty1sXp#Oc)T1PI%D>-9HP$Drh&!a0}S=)L<=yH~}IJ_|3#r9=}imFIhp#)M!5wnx9
zh=ssU+EVfAwv{FJ!M0JXSoF)6=+J5nXj`Y#v{v~QiDXyj=S67n*OGaRM1|TI2t;o1
zAL-`0E#3s>HrQj*(H9&&ptBGzDDUn_@;l=xAGrYYBMCW?&$Z$G>A%8h_@B-vD~aF6
zL?*E>ZL_pw^4D*&C7Zl$?Y8peM?x`?5%bcw0hekT^``%gMBbJMG|E6`)g*xZ=eR7+
z;~u-a5?48v)RR8fEbEG^1;exUE#hjuSM4ry664Crwy!)h%M<2C$;xGmR{Q?Ic*009
zTzkh-uxI|GbLDT+Gyjkf(6>SwxKe<=yZ*<*5KVh1aVui-Yy6trkH<Zxg}!I$arXxF
z+nL1+9CPPdnh&lky^jqAx_#=(3OyCOnb-D=OSR(Rb!w}=Wf3|t#3AgG!`7NB&#~<b
zFZ1T`iLX?h`Q<q_W?vXGUZfMoyEES7n@YB+SIblen}U+nu3qs>rY}D-wZ2R!={m(I
z)!(sumOa?wQ<ERKm}HNTn&MP3u9RrG+HJk`OKEIY?Qfmr?LauSt_U^<;&4Z%0t~yY
z@4v06-}KL0h$0v#S*3tmGJZPmHND$SmVbL0q|YUJZST+8*w^l2GxCQun|<Q)`o57L
z?qbS+Wp2OG%J#YPB&+S(U0sGS`(!Qmw-4HI<ICg8{JB(C)W8FdOG>Niw;6Bjg1ulb
z`oy@d()oon>~BnHJ{lohPXRshs6Ly;ROH{-9_<N3Wa`f+T~NZFoOJfU^-a$>3`se(
zuKpOihM+j%w<V2I?>*Xm2wE8L@R_)2M~EdPvJHWXoFL=XOH^AbV?fEmI|WFxy6wf0
zNQQ1~3(d2cnBw#BgX2LY`f6m=3~INu?4pn=*yhlt4Z#~XA)H~2d;d>fvwVHxsYHA(
zA?M;D&btJz6&U3O-ob4w<t*K6cK;vheiEWx`RIVzKkh~;x|w9zd$3aun7{wwBrGaX
zk+i>=WcGE~c<@hCYpv8m^4mo#FTSEFU=L`sIlk*FyL?zglnZ-C?832i*}0xUzCGkK
zU!D?9`Qb}?R}xYy>^Ih82%X(l?osYCqR!w5zo3qI6<Bc*CTR0Aek2m5t57`JEA3XZ
zRq7L25U1%Kv?}&i6$Z7n181^)NwSVaGIZlXyN;nY`rTe*(2*d!-PD7bc^@R$eqngN
zKt!HT+t?F?$%2^KLk1k9X8V;I9tR4ad|{hqGxx;G-1HY@#ppA&Fj!pYs8tuKN=*fS
zU669)2oCbrG?%*R{D+E|s{vMrP7mkFvk!nUPrsN<?$V{ZWr-qp4A2jMNGN{{zAtBI
zMj80>SBJh?&F-qnfs^<Kkic^FhF$Ohgy&Z^GYqG3pigiq;t)_Dqv_(4NHo-T9VW5I
z>8E^)`HHh32Q@3oon{=JJsvSJHjHC7$ck47sVpfP&p?l}&`te~?%SMMRENi*qRhuA
zIPWKwh`xSwEX;}Nm_*5phqk-e6055d>SO8Gxqa83t1&LD`y@di^G@C)aEqgev$`(%
ziOtBvIxppr%uc{dm+Ms$AH8r!pDSAAK;)-W!@W`_P=r1@i9{P-6`a035COe+C!My?
zfu7NZdA2MBdOU38N!3OBkPfqy`T>!JRxFnlT%8#3Ju!4iXy#>Ub?-9MabsdeKcZVL
z=y`#r%UX)MQe-nPoZfq!fi(6=sIT)l7ABIK%UP=Jg5ru0iaZN+)p8Io$wc(V4@ne4
zK=UiNw3K=|x{#Q|dQ;`B=(=8;n4LtC5tY<+31gcpak;94<g&Pqm*!Gora|=y3QF1L
zEzBm4I1Y8lHZ`1lOMa>u0_98z#p3po^<WurXTF<{+~Jh>7(aoJPt?|VS>g;YVm5n-
zVK!CS9njk`UKwazX!n9Gl8mb=>)pT)VsS#NjOQu!ap~t;%1T+;cl=GldLz^|^+g~W
zB?ReKE`qNzHDEUc)xPEE(d)sC4U$4K@D6L$CB;zj_G}lecq*~Y!AI{X$!H4%>B>1G
z;5pKWcT;?&ERY0Jb}EVp(V~EF=C>-D%I^eEzYe#Sc!iv=q(d#K%5ZU&b~Uweq1LgP
zvNAOG@G9MgmQE1$s)=UN7gA=zu_j2L+Vq{grh_51aWD@C@|kEk3nob&&Rlhp*TwB|
zf<n~+M;T8`LgPG?shFC&)I4~cn?glPeG9RAE15ND580I6F_mZKD{QoAG-K^w^FD!%
z(ZbwGL?&o)1|qy`%E?}Ko5&IR1w70?yZ+*^Thf$oT8y`n6;1Q_tY3OZ5qQf!q~XJ^
z1!{93uM$9<S9H68ZipsRA#X=`;jpQ?bkP*5Ce#1ueM^*Am2)KFgd9L^&6romwj8N8
zdIUVO6$+`<ATSq?j4stw27I61`Qaao8^_N^UGh###=>PZkUvjo&9Cyq_GLSK+S4`r
zq#{n22a_yI9;t_)q@b_YF!a;HQ+mrMHJ|jKfTR0h%`w9a=Z$OY-PL>~*!U6T^|*TN
zhbzhKYMi8X@gxTM7_aa$?RW94ZS6qB^?G=_pAABysIC>=@z&UvY1?y9IWC^rs$;x`
zM}e7mftC!F6q|LE#`iE#TUjt;CvGfi8!Km3+Gwvdm6(<fwieGgo1=|PARK|`H=XWg
zz4;lAH@)SxnVtWxtS!witC9`WTQW}AxyUjOLv3Z6H^r#b8?riaHEyE!z4k9$Sr$7T
zVaie7u52$4>}t$0xGvwtg723vU*rJv+;nlzZ*u1K_AAXl``$$*+h}~3LrsBAvU_f$
ze%vr#+T8mJPd&|M!&#Pol?yTt|9*bm;)gCT?3HhGO&t>MV~%6izH!{_SGMN&5SNc9
zX)VMI#V6v=&fdEnarL+D8AKRoU!F+x#S?+k14)K6kZ<eAmS$2d9$5U4Nv<tj+je?-
z;jVA7@6K-PV>f(;KKUthU1F2Kdx6ucM!_NB(u)*<0VDtQpReR*WcGZiCD}J-Yl%&N
zj|<HH?uwbELxagMc{@t8%{+mUpXMM_b7@L%=J$kM@hEO>FfHzVdzwxBRYGE{i(SZu
z8s=O{6H_Ag-OH2om+!SS{QfKL)Tb^_#wJyN|7K@iN9gusGHv-)91=bd?#>oLa4w3@
z7q!)0x7+Ho@3y4WA>k)Dr@im6&EVM^mL5&RL-(CbkzVfX_A%Bw*1+qu?miA|cy*)e
z2HiE1V{GyJ7;6O)$k;jv{xi&r9=V6IRY$ys-%4UPmvoPf121-2!q+y~ZS~f^gr%2T
z@Fv+#(_0tKvDPi{hkl!JNcd>4Lvii}j;++}vF+A4G{DQ;HzT)q>K3}4Oz`jMhNyO1
zojsX3>UAuiuGfjp7L|f5G=|-nzpi{uZqv=JqAbReYNDdNHA%$kN4BI~(v0s+k~P~e
zcE*Zg82R=|&O`5$oNoB=1kpL>m_VwB=Q^fr`ED$qV`%%PM`karPtRROZyNnYvoVaJ
zwq9g29Hq&xNn9v5q+Hn0XT8UyM*VKGo`V~zTtPwt>G)55LVw(?J5WsEXO1!TK~qr+
z=)@a7ClFx>-V4Gyf_+LV<5wZ8WjLH-X<ldw&8F#t2R}qQLaf%o%;RLVjaa{m7V?Bp
z<sm6Zkw`q@VxLYxj;s?xNd|t3Fi+c9rdib#Z}|)lpjv_-XYp&6Nb)JhC!xJ)1Sw6L
z4%wwYM%b%a1{`2}o=+(#kDGyuqE@<U`0?%hYF^w8)S_GjVzEs>&>vjfA<J&YvalA0
z={X8|oCPaAnC6duj~~~TT4R6BdxvAH1o=XxDd?J&YlA0QNJG+iIC?8m<!P`CG4g<&
zX`!T*ab$taB0J$IT^T??afq-V8YG#_&sXlvo@_}tjm%qy4p(GZh-Riz(&jm<`AVck
zgH2FdbIp<Qn127DPlL*D1}8A(Rez_Vy~CQP09|1d3v*yY5{Lq}ea$PU9l}iv4-HI=
zFA<nOzjz!ib&NrhfqmjQuj3JGDayuK;4TlGiA|>?{h-fhE<$z#xa#~o@oU|AFm<v}
z>aCk-^2%{Q-Fk8@N_lSpr<olVAqB>_Yb!OsDLV&BqGGBQf2j{kZIYuIDASZ6WgMZ5
ziN)G5YLjYJArf@FPh>E$D%A+6FJ5(_%AIn;PBAf%a8`wD7`OBjovX@+EQ6nqTV+Np
zI427mblB_yenA$Zu5yDM9LyIP?|HQEp~B@JpH0CN2VY-tw47-&n5YDgfhEbpx4@>y
z`1Iur0kQ_a8O}k__X$eLIYevsK@~K~p#qt)^*G+!?cn+}I!vz1$GRA_01y+Iwo=z^
zrK{bU(l_}|&~)IWI+q~i#=vQHG1{~sL1)Pb4#zLGUHm9Y`sSdz3s1>mq@eg06vXG&
zCP0;9GRWzLS%#}}2rq%-NA^Riz~Xmdm$m#d_H@iVm8KVr`6vblSFB`YEQ?gVSBx3^
zP;Kv2ku9e)sr?Fh?FDoaYb4B;{6qhuJdvXsgU=@_ew=%L7Q*+cX0odsu2`_-Evoa%
z#fzDId^O4#x$LS7xjB$=CPhsAk6_boE3eeXWQ8y9tkzNV-R`=5HVc}_*w=oRdiCyI
zSy8^wYeHoMN9JRaX}Fk~jgQ}%Qt*u-FisD(UD#?`z0U?EJFiDlUu1x;U0Afw3|`?m
z2AtH>CzH&t3<srhy}4h4+k1=AfgKZVIuVvWuQLhQx%~X%412>iZhcQF`v*DC^y~~8
z&Dp!EI}3`d({AZ2>JvhEALZ~*b1aMRbct^ge_3;pQiq{P-)7%puJveYt-m<g;ok>H
zo+`fw%l9(4eL7Z#_;%rI&s3yL=f8exVLL9i#F2}*+p1#mANZWjfw5hvG=BJoU2sN3
zufB_CKM;5I(4HR9-KeKL8cW(M;FcQ~Se2ynt+rt~!H%j~duV9d#&|bRdxS}fGAT`E
zUi4>N=Img5An(o(ggY?|7fFNf(x00!6p#IhwWc6TICS`1ms#<NXA^6`a5!019hrUQ
zrIYOB%oX{Y-)Od7MDN=+Y2Q7G+xq8Iru;1PFWi}^JEqiMloX3UL#S_GLF+tYq!>G#
z=#!ABK)*K~+&5J!J)pF4e^E1WA^BbIoW64)WmiwZ^vi<+KXM62Y#wE#_`wJBNg*}`
z2{VSp^!%L4SSA{1_{fWils(OrgIAf`vNuSQRU%Ps9X#DU80O+zyv`;s#=TN$qg5Q6
zJeBMhE)6-W8sSi*mYI^JH*l0z`24RkFMGQ=|IkES+-S0;8v+DTqdc(hEV0ZP?e`SP
zlfQLVVpkQmwDcX<JK2!V+0y(_zLfqdaZv;$7vZ~{bvgZC7p?rpma%N%yu@kKIp{Um
z@I$nnncE^~m8AAP7x*%18V2ThA+~6zVU8%$LqG0{NBBlw!d|G~`U_0+{<4<8R=Fzv
zwj<J*(gu&fD<jSCGTC_g)M6&PG<EUa;`PMsYZ*KCCgJoytA+M@j}zMCSU}ocPuI2F
zLME05$MsRk5kr6EZ4Js|kF6jM`bl+N2mUV@-a}EWu+9di`dTB}=p)@oHZ+y&%0xE8
z(G_Q(W^T3y-ab8uI8URbmxD=L_UOjg1iGa3t7&8*4Ufa(mt-HEa$o-)J3FEy*#-}0
zXjjgqWa0X8r;4RtNO(L$HF5hnVm7<evigK`aT%4JWS@NhW5x}nsi-ROzsX#5h@dMU
z5MtC2g}3rnpCxZ#I>yKF(&Bjx5l;<H%RgA$36OOYXlkr~X_5~30djW@F66%+*a)40
z1Zk02Um%W8K$=KObBQ9-oJ27O(SeS$3ZaVz?UgFQHk6#5>Jg%~*CVA+h6v82sPJ84
z@q$W`+(>dA!53_ugjfR9n}Sf49n))@Wa4Tmx+R<)=ti=k85X109YpbnxDIksqD;IU
zQAwR0nkD6lPGyh&mJZueWvepjriW4+5Ep@|DPkcc0T`WwYYo_JcD1$gedL2Ep<%Z5
zU&QsMPzGv8(CeA5o|%g`%dQ5JP)H+$6rq6i(cR<W<WDA#g0}c+D9;k}u+3S^hG%vm
zj{qjWp5*a5BdQ&fYHLK0KQ!n?y<Y9bXA^i*eq%{ss!)NGaWSKHK-gHd1{-(bik##)
ziOgJTFnA$jGn<hmi-oOB_X0=buLV(2m1F=4b(1-#&tV60Qc5-Vx1yxCBm+`ycS$oz
zBTrmJPu6LuNo~bDkmmV`j8B2bGX!3wlQ_aI*?P0asWf6>(j5;SBajevJi^9|I;4=c
z5|?&)k;ldmj`3O_N+0`d{(%VS6eEPB6_wOduH-`afN^2C4;izn%$-^)j}0N<L+nvb
z#GcO*Pi*i+qaJzo5Co3js`O>2YRwjT&1WvU;v=LsY1yHJ%xO$KYzkxUe)Xmwss#_-
zOw6pq*5JfaBf&Xr?p(#<oy}(tCk-Z{VF3q`cVHwi)ur%*bMzF@PRL_?k_Sz<?S>3I
z!cp9w&vVP6TGRuU<=-GI`GFe_KduG<qpC}qdMMs6@#_ofT`EO!6sV}0>o5?6I9-p+
zoSq^8e27Mem0*z|qBeVkZr|%;iTDofq)cX`oy9UN>gqa>BB8>~cAc2qv4b=)7pB)?
zH?XG6U{y=Qs?-jX!9d>&dZ}pBnLBKPG~nYro*}y9BdD`-ehc2`QdmBTO)3~txi^!{
z7b{x5ir@pCo2Ja+C;_fTc9bpqiPNmjU+f7})%S4zdIEpv6tQ!>yvcyS-s6OJw+^d{
zz@{oJMhH&Ip;d}yvS05bCI96ddv*JFE5g)%#H)e2sj#o$ixjN1l{NE+_ZFdwV3Vhl
z-=ov*^r<Yf!!IJj&pL1+MO)65Y<ffmCioHdQ8~X`!NLNEgkK)*3kf8=kTzX?Yw=U3
z_<BXN$unhXVTEDv=^dz;dwp@*Tc5|kiI@)N^{vIrQ@8SLm1^F;nfIIiX}s|5A@94_
zP1%vx@+#HIJ7_#3<NovC6NBof&f`?bEy0iw{RqXFK6cge$%jA6*nQbUmL9xd^+?#p
ztfl#%*j^4*wBMFDlbN$<n%i1wmz*-TYo`)E@KnoMuQ_F|i{IF!ifIszZF@;%aZ`#_
zYOGTzhoN{TX;rW0U6x&P(cyt~;cl`;hN4Py#{_gsfBHf8_1^BiUpdFFnLoK;Rj>z;
z?9j_EBiV0}fvNY>zg%WF69#SBy@n4j+Q>7WS`J8);<Zz%6s7*3-p0-OZM58!pd-&@
zv^vy};TGcfe${3bWJB;_&W#_Lviu)DSfmgBVv_hasuj6;<Wt^0DYf+rLmrhDp00Y=
zgt;Fi?fjov8sWPkWEc4E^T)O>{icoF^D!FzcYfS4HA2SsFoRm;g0k|=S5Y5NPmAKK
z@cQKe78ft(0Q=YAycc*r&@%pE6w}vi=e*YKp2MiGsKQX=qxct=>81W;yScM}X0can
zmA_^u^()ljnA6E$b%4@9!#z9VT3eV|+!p4x+!$gh@CDCc62>j>eMu}AAJtaMW%LC{
zl2VHmzK@Jp`0qnbO7Y~%?6&(=PW;DY4}amle17efTCnKGvjNkF&&%w<Gk2?ugH8)r
zdHwXP-8*7w;}OV2vMI1CH@3`d<mBPZ9)H$~n?FNW3QV8e8aeGti;KUq|BV^jfWSxY
zN-|!9_2kyiFMKA@sn*ibq)r4rrHpq_>3=?Fx7G8xg)Ou0O+RYqvR$6r%Z6-V_<Bob
zd~K$fzce2^^4}P-dqOQQ4nOsBH-G;YpDpb16P4QPEq<bP1$nMK#&CNZHyd5T7utJ9
z*ChyA=cZ!l<Zm1=@4&VH)HscE3*YitJ*urgVs*WuRu$WU|DB4>ZmZPRA?;Ddlf|g5
z{lURO;!!vMSS`>o#`I$hpW>2b)Yj4NdCnqk@+#7(DSj!9g1?xsa5@+U%B6fE8S$}R
zh-yP9wFjlUxS1{_?V<KXcCG4?rEY+!@DHifCs$%%I>n9GbgG4N>-@#;PvYU)iTu@V
zSLSNb=Z%>8d*UglW|Cjo9%7>KPG+xXCdrrm8?$9=r@<W>2(7QPF}H0)mO38Jxuv=D
zVBp|Z2BGu(Y^Aok=*@(+Er}0UaK<pFzOpC8I(|B}u?y732=YieEg(S@d5kTg1S-oI
zC%Wdz8(v(L&?y$m7t!?tiM<~(r^NI@!VUzP!z$%ylW(-dB=gF?2yzutG91j~URcF#
zWC{6PNdwd@lXM%ILI#MLi#T$k!+ji_?}mOAv3hZGLDdgzT}-14+_Wf`s%c>v+N@wA
z8s}gu@l5n)UWY8OFk!OX(GA-}EgqY~tb`iuW0GRbD%6RJQjpVsisd%lgrmb*^{Biz
zc{&R|dbex_)2GOqrG~-WMXWJYled-{qS|t7&n@JkQr8}(9Tqo(RsO;C0S%U#gE&Xo
z_ZR_rI*pnyl|vp~0Vg$=b@Ey)l8CkO1cEN0kM#~gx1#o3d2I4bYC)X35*o!17Yu*o
z_>`J=SXD~^Z!V)@h$78`xd1BQ%sImbWOgOp7S}Tw9s<vgQV%l06?wD>&tDa#d^U!O
z=oN^i>D4ZY#6=X3ELuXWHBIb?qr0C+OgTN8vJnffgNsokk1$Ke?#IDqm++vRLzOC)
zxmsCKuMb#ZPW)Vng*9mIVkO;8UZKlw04RJ&Y|1MYx<r+#UEL8>6+#YYjkzu#-JmBh
zr(%6^=-HkO5Wq8qH)D=qakwFGRn(3h8>-Jdl_q#~%xTS8v&vU)hw$51*nAt)<Eiu&
zo3*PR4J5m*`clM#&EeM%WI<F(?7r&VVNNKg2QVm6SPCLUcOMTgnwA~{auzFb<*J@4
z!`K#?a7d}@=3llhuxuI2sq5}-5>a5pjJ-pb+IKB2EaXBd@j+2pD)17ZKp%XF@ZKh!
z;96DaU{7RlnXI4;o@)U(VHBG#Q^b>7sa-;1jGK{QEqh*jNsBH+kHbg3i9R&p7b2Mi
zp-9*$$PS%^Rfq^Jc3YQFveQ#oY#N>EqBk<VR+mb8fHKySrFC>Zu@|TJ*<O-gtXa+9
zxSGZ~qT{XOtEkqX!Ne-)cBKf4C)j5Z;>x)Bl^e6y*&SOEwLZnTGGNW}S_p1QlhL=n
zm;SL6s0!Na`4pqoq)r!nHua({(YM2C!4eJ$ufp)`S>%@`)AWYGCAiySX}0Zejl&1X
zGt?O>t{+chdsz*1B1;}Vk*++yInnl%;9k2vU%rSn=D-QkWHNhvi`%mDtXH^@hTGFL
zz3#NUxtRKpz9XQ%pA*u9&oLK$&!i3bR-Wqm;p_!g4EeuzWFL~!&3I#?oIFc;9zHdl
zO=xy$^U8&*sTsYX9QyLvyuLEw9!;B6pR$(3Y?8wo+n(_r+G`%ZJ8MonpOpH5L@h${
zVJ^>jT!kQJ8vO2jNFMX@M1hIw#{*wv&c_Gz?Bm?t#FaKvtf=x1suYq|dnZdz9P#Z7
zNH&q$did~`acRqogo>w|b#7I!B;KQF#LvNJ1_Fs7vY*^)Pk9tNvE2ORS+<0kTziqr
z+ke9ztg7GUkh=zoTXx&-eCkvC3qSRVnxpzW`dgRP?eUeVZ1D?2oeqbqh(_W*>C`WT
zZ0yK@`6FBGmjAvxNe=#Fk}RU_p7Qvmbh>Ae{m)D4?}GVpX+3A8`C%%@6JaplwXkR0
z+{Xvv<Y{xpcFZO&B<aM5u15d(LGD{CoeQGrhJu2A>!ERLe3Ux>r@z^!e5nj$B8@Wb
z9un3903LCyh+lW??s+Sbi?v43{O!xxZu}M<+SI_9ZW8uU*Zs%`JF^bxHiPhmoi=^`
zepHDS=Iq2i3$>&EDA~pMCCUdGxlcdI+eyz@T!-}^zbuVaOS<u>)K-MbiQ-XKbicu)
zQzeDl0G#dmsJZzI2b@3u1?F1XF$acz!|ZiO=uMw^uYH+VTCLx?tLD&_wGzOYw09Im
z%frmSZJV9=b#HEFZ!Mi3JV+D1m&X2OCOC(F9Ol1*%#s}(623FFnO7)R>_=a>ocbk+
zcXJ3<tXTN)hqkbJ^G-y`ZntF7fk2Bv@7SB%eR5Eh?gvU3j&MXh+Lp?G2X;KvSasJs
z7X`^<Pjs@L!rVf;98z2J<S#j4gxWe1mCmIzar6UAXHNcVdFQlcB&*Xc$_L<d%s5AF
zjmZw!IAZQ58)k9983%HLj=jW$vi8J;4+oOQHF)#@XYGlparTV3zi>WvwOiBJ)it+d
zj?Z1rNiVFxGpmZpuJC$zo3}=4^vw3xTP+QLI5@BCD~D{ds0R%Dd3Y^voi=-iO0UN7
z_}BTUJ$fGk8Ax}8%L?u4^nx(Te5Q`tN?~q8MZD$c0F*;mpr7$<T4tRhI-25mSC%x7
zM+y@nn&&(g@$9SK8e1&yhfcBJN166J?Q?~MdJIkPsu^Rl#Xv6>qjg%=@8n&f@t`8<
zfi4BY8wm*9)KoM{@j5DiV3yx>TMtWlZVuY5^>2cPQQ0|4H|B$mP7`9Ot=W<ysDr0E
zdEusmFd?BQg+uK~W(-?t7y}zw(;O8`uJN-W7G4c!2QizH5uFImPTsI@0EHt>YYf`Z
z3<k+|gwQ1?DkfFI&u6+#r%xz5bZDj)D!Wga_OHn)yVZOsP~;MtHkkl!H8okdPpmc#
zAMyNd;AmgO_Imh>7$KKgg$>(-i^Nr|vW9@ri;z{kD2vRAfEe?jr4nF*pvfcPZ8%M8
zE-9FfZVoOBMl&a&U9+6KQo0jW2qH=y3EET=<D}t-H#1sGL8s+eAQ^r(>5MPw&9E3T
z30tVGEhfg)ktTjK+98B-3Oyc=%n;usIkD_qe0#z)$LWbUwu<qTe#2Ek0vQ!#qs=6c
zS#mCCPe@~1gba2fbmZ&F(m+I@SS~imn-V~zJ{<==2xjRa`40zu3y2hJzFL}yfqFg0
z5Sk!kw>8SLn>>P~ADgwbi-`FWF+;i52!dOy0Tvz*9+-xO9zf`Ys1b(g7V&W&$ri|U
zN=}|^b9UBP%!!G%8f@h&*;!_?=7=__=^4ANrZQ`-Q*6+M_<8`R$DHaM^jqm-2s3K|
z63^MjBua1=*QU@^9zwj(yB>GniK`1;F%&Ft>Wq4r@A_<J1`Qg=0vQF!SS716PE*@r
z@sN3WA$UQjqg18@#ghtje00(CxW_KF@v2O)gf;&uS!dSV*t}fo4@f8uhjIfg-o3O5
zEO{u84iUYNeXIz<TRe*9s=PttY6*khskzg2<l|`O3-eCBtt0FBgm`LtYOA#!$XO3x
zBp+dr7#p*pa(HtrE6}+q5N!7Wvr2{(7TR55MmI8z=KRg`mOuJxSNPrLJ3gBmez%JR
zMQhM>7A!*JB({_<#CinAI3%3ekIY#-t?SRDV%;HD_b>)MxHT`rz6GhR^k{=44~L7h
zzOrHdQdfO<=kR095cUvh2mJ23v&TrSrF9ijSF(epdVDwSZ9m&`(v4#?$lQnzpUd}K
zpJ`4c?Q1ED{WIJji=Mk&O+I*&)tld9t>vF$TocT_hw@!X#;;o*@~Pc2A9N0WX6gTN
zZs7McX>sh|eIGhRCLXUwZEY5lFM`)GmuKHG8`rCC0iDqPVB6d_hq*a~g<;QOoA!Bu
znU|;4Y#Uq+K;Hacll|7?slEEU9Oqi~*~C)(BV?lFizi$``LZY>9TFb=?cEE!eVTJf
zcuSE;r5We6u6^XiZMM^jEYIGP#Z#y4Ki!S8_ja4U?b}<Ny_{3E{Xn+mb2cosb!BR&
z?{4yXLcZXtpErNW$1TwY;A6Cb+#NYfy0P~k-ftt%wzp(OJS40Z>hS;DmzZxg$L)ex
z(3__1CobfWaIWv8T>F1#_VfeSDC6bec?;nk-<iw9bwkz1OZ^UNbo}nl-@MB*spO@<
z#_}i5$lbx`{M=$7Sq^=A=f<P9oJ(z;xsUpW+8UaN?7Djc#WHyDqP_H+HP$9J<w~BR
z;hMZU{wG68D{ooyww2XAA8mVDddof=ZL|~K2&V}80yb}>b~;N=lDjYWO+rZn9si@t
z<`&d9JzZ`I_B(eiHl@hT-8|stwKSoPS*fi#;wO_}9LVs6p=pfX(0<_?3p?X2NwTUf
zBNRutaQBOBNy$!0Z3U@hJqN+<(8u?1xs?<;G+XV|x;L#ra>HH@asJ?xrS1WW&C<@<
zZEY_75IGIL$E64F+42Ml6d(B&yXeNh%dA}4vQ$!HX21Q0WRhgdxlf+T`1{#l&Y$D#
zG}wCbdxa~Lnzx~YY1S;A{lNo+VKl0(-yC-nsI4}<KcDaqFulCyRC7xYGoy-eZpIg<
zVw#8MY~jhQJ~+xv!df(mz&a1ThPUO~(&6blx7sPEyry?#G2|&%=w0^C5HNXx&gXDD
zJH!8C8u6C=#RXx&s}tN~-i~aaDj1%S{}xM7TU~WUs4#++uBCEr_=JDjfcl#w&=424
z3ij`u5a+JD+p1&>eRn6fKL&pbzmn3VBhIAqGM!7$kLm&T9?(otILd4}zc%-83}*k#
z{E`ToFG&}|H^}VOzZAz<V%g2GvxgLaBdMER?$B6rZy#8+<nV6ewTe72|F!dB5|wA`
zP*UF73ijo6CO0@^_?w;o!!)UvA0=luA3IGrA&<paxHK8er-q4oJ1P?Lmk5Sp8KyAe
zNY8fBRJC~A2SDVjA*Lek%y=B3`3iCcaSyPKow;4S=oc%W%L=KXwlc4pugKyvj)&{q
z8(IUgd!^>EtT9{7JYzd0jWrkwb@S1=K84Eu5qzYC_JYM}E44K<LCj7g&zwSxkrQX-
zc*bt4ibdJ1U<5^0PNELN4A+{lN^T!sipM^=0(^w(Ce=D;iW+xcXd`hRhy2Kz=g|&4
zdI94?SR$I~I$6&w1OilSsKNgKw7m^<Wk+@AyU)2tSEtqL?xSusmOX8|B+Iri#$59e
z8ZdTAmW^<na3O8e;eol$>v$T%Tj}s@k4YeuWZ4mp6NE#OP8Lb7jVI|Lgw<q7mLXrq
zjg#eJJnwY~Bn*qJr4TY94)A&y2#zuEe*Ze>N@}~Mt7NU&(yh;3yLRpRIJK+l)WOy9
zA_ymwvim{E)?>UyMXq#c3Y0p<HHSmUkHYl!27c%!UPn+sjXts8eT3OlWTIt5#}v^Q
zUIP84#C*mm;5z0)F9n;tk)^|{j5WHk4>>UMq#0}k<*=Hi=RwRcM{AV6mwq$5@C};=
zVWG`bM_O6TqobBeDWs&vCs#NOU(JS7?A;bHjeFc=0j=IUghkqvpLa#WYq1|pc?yfO
zZk1wSk`xIjTB+#^PWjhaparL4T^gs<2?%Ol9wErTDbVOZgj`CBDLmDBdBIp^Oy@B&
z=Zt?I`(Pa>z{6)qb5~6SZouye1;Iu3!zy<Q-2jwrP#kkg(g7M`fl+5kQ0W%=O+nQs
z>|5u)uv4L=oxxXu+`6$=U2e-Rks`{7=sYR<z;j6~mC}jb1ms$F!Q;-0UP*G|HFe4y
zFW6f~UXzt9gLJD2aN8sZX{v$PoAasoccch-39Cv)2J_&?a$#=@&jn40PAv^`%ve_O
zGhAH)({ssUDy)lHMR}&<?OfntjHHBTqSm$~V5tu%!ed!FM1`pV1u(MFpjsv?wDJ&$
zw$YHdE)q%xoXe*ur2;pHm~ArcX(}nlrJ?SEQY6TEip)JCNmKICYZ%H_8B#VH8<|jM
zZ$e>{g$aD(Dir*EfGaRWXVg0;hh#j^#U~0@QBXwJG9I>s21SjQBZM%ZD7PtsJa*L9
zYm~wcmu60(LQ&OtjW#dzqN@%-NPigMqHWLk8q{bVH=uCtya)SmtjNO)c(z}Tz5v7f
zK`zA-=fV(Uh-n66bDg6Uo@PQYucQ%0q?*$TQc*|<ji4cO(m6uZZ<tbhA1Q2VkZo>r
z!em#IlQU!+lz?YEThw_Zkus+oI~qA6ZXbo!pRw{D%LZqpwizL$aF&p~53E?P0BR!C
zfM@|o5DEYlT4kd0LQ^5ruB&^BMLyP<ven?*;uqi-6hk0@Jd%2;(L*l{9u;TR!5PJG
z0*)b}LHs^OsTJW3+PJKLE3CDNNC9z+?Fi!C$+cD@JSjgVD*64};ThTXCnO#OUWRxO
z1R0WbM~)tf+-C=$bQB@^jrlscN(nd_F#@}krz3)lxe<a)Wvj}JkE3C?E?b_-Yn-WU
zLCi>)9e$Cn?2Vzl#+i^x8EP)i0CDiI2bIC)J}6}+cqb>H8<6mr;M)RaE0`DH1XYG|
z@^T2y!bufzHgmOVmCDspuHDMC0v|2S7l06g7NzM_4&Qu@MA#a>+#7*cgp&dI+Ndi|
zzGp(rw95GzQPT6he@5V%mvL*2qh3kYqMz;Z3S!&>)EFYfbWx%S&vQvD<`_e2lnt#G
zF+EXwal<?tNV+ob=EpQjifj=h+5`k;uIsSuUUQl|@M1Q#{$jAYjL4kGTdgl}HUMQi
zz=L#(6<t3~QHD|nX@*9q4=^TAg}_-(gf~Q4Vz!r%ghy+|*#Mp?wJ9xHkMaO$ySk2v
z*buUYhh;jC7$zYZDnB_L&uV6kyP4OvomU&~NQzqM*IdRYgfU-Z71=43vXv_745(0o
z`N~sui6Bpw82v=9KG1G>(bDsd<RNmVB-`YVP^2>hwwGF13=r)PbicFXb?Ppw^M~Oi
zgp`Hn!P3182LnaTZ!9S!nhNdkJ3BeWu7k*LqZ&i~x^SFx6)6RJeu1Bw3ih%k!_iAf
z!})uubyvbz+AQPUvjlGr7qL|k5Vd9Cb<vBk07}@j31;DxO0Za~n(v77;20D&gyTKV
z?p5JKoFS+Y2Y#9-`EfNis&f_@u%E{?lDKV7VVi>&5maA3o`h~y<GOWeKtLL|Nnkb8
z>mr}+>{iuPO%czCZrUP|m1v`_0`OB4j4(DUD^NlFuYq54ZtfDjc$GCGS`YPrp&$r5
zX_A`R=(^XO^$!=fRcTD(!|}5~i)zc!7u58~HeEn|Q%EoC#3UVe82bbdnMD!(tcJq6
zl&&tDSJ#b0gavG*`*zGy&gLA{V6Flu1wKPL>}ZU8D|xhgw0bCKvzc#^h26!ku-^xR
z4bXLPZ<4v=LrL48&x<DO!Z&n+xDGf7xa#{hLIgN}m@M0Ahxi85(0w_h?aGMpMLgsk
z&Y?N}cnC&FtR=fM54Av6>1^Z(dOL17{3`K}S1*}sP14^U3idAo=X!9QhK0^0kk)H_
zuO&zS25H#9%HWI(zu}y{A>+ahO<em!Xa&B3F)q~iB6>G8?r?_Vy#Ho9iV%JZAJ7T+
zCP@~~NyoxZ&7b0IrMIuV#xoc{$braWai+a@G7V2R-HzGO5ervv3DB`5bu<OOu}u?v
zcxYfrOIhLJnW>A8UTSl3x?Pdp*nIRQ-t3A%33p8MNyr|egHKu<`)VKhi_5${-m0e=
zz4(pn$68QQr0P&RDgsGv-vK*3ZRP??`nz>VOgjl-@`V%CA+h~W+aZPUZH>gm%?@ff
zY-6`dg!+P7PrOU!<Ua4nc2OzjccsbP;llZqJ*ImzQ+;&f*y>I~yOEcl+Qr@xs4H`W
zng8=^Qa|>)mMvd38-7^?`au4Ozp3l82gc3ahphkG&e({HZ}2MSCtqXBf6$ujTp|)<
zU)vU9+5YPGgbz`S1p5~_n<}j+@8rbo%wE<mzV11n!887$E3%{R>j*5lVx*Y6J)ib(
z<OEoH9)0zb4ClKCvfTAyOVQ!fK(cN4)}(XdTghT_XlK<))O97!&mT&b$`3RPyY>32
zviedy++1R!1*j@@m=92qN_OJL#vdoN-Y%KaR!fsQ*4-`)GN8tKsW)<T*^c?0&s*#5
zk<><p_W9!LjZk;m`2rTGz=@q#rN)bQ+KH?9X_IX%TXD*#QP^s~x3`nb{(-uA{E}qi
zhA-Yl<J<xq>CTw_`Cir=Xh!d!zf?&=&Pa6lZ!TiL?mTbjP&WGrH&c1fLAk#=$LCLe
zrr8dk_zfF*`jx>t-)Ext^JJTMT;j*rbw%puab~a`%HIwj9i_o^H1oXpeb7C?G1Sl~
z94LJtm_JA<FL~io@t0rsf$xK!nIP=k6NYXYNSg<T2gtlX3?0-n0;ux7pz^H1S;>r`
zw_Q@QUDD}owZs#7i`qbmdn{p)85)BGdn|rB@Mh|kAX2{*)DnH2V}>0w&sY|G_x!Z_
zq(_VUrnOxjv&9PIBT3MXdIjH}vHTl6X;*Ya@LT;Qr&PD4ZOo$sw1M|ekEAO)5g5|;
z`N6U-OB1(=`K!S2AIogu%Qr5Mv<LDeJcmc<EK3rnci3Y3o{Oo{&)dg~(jJ_zCP?O@
zI{QuJ4WV*@JDsdUC28VrpXRK%nqeO}6h6YkrMMVc6P9j2n4Hl&O4b28S~#V)o$pDY
z56QLY4pb|Un4Dp%=?R>88+nY^bFqCgr)cAl7&v@Rl&~uqoD}7I!v~&C!6OCXPV)13
zm|R#k%|@SpZsp0z1o9e)#6&$QaX1BmI%W!$nAfaLUj^+8t^j-1Y^e)Xl_Sg9tajw?
zC<)b<uaWR|Lyw=B^aGL0ShD#kCRE{VrZkLXRf?dbsAWv>NSJexKQACy;9*-uR9Kss
zoR8TP>Uc*<C!USVOj32Qb*Ke~{(y`shy)5sZ-?2FslwEI0WTpJ3#fEcIDDrXzN>PV
zlwwPHmk^3lYN58!26d}kkW`_NTGMB{i4B1OKO9hbB6P-3MUo=cI-1Hj7<}3fhPZn3
z5pmTAe8J^Xj|wU9b8yg!Jb2xbmNH-zb4}Glo-Atur1uT?QM%3){V;hQNt&=DnK+d(
z$<nY*{l^Y+>NFliz#U1;j^MJe1-?KPAM;oefoAm!vR8r7i7botP>-#vQ5!h2dJcL<
zw7Bk2gcvwRF+N+ln{l)W;$8X2_!cZI_eA<OnyM0S1(HMqm8hQ;Taf}~)RFK4naofx
zu_lT}tbfb?f^PTmrjOzf`ewj8{}zs->{4IOeh5^i)|Qb)5Yw%?&S_e0+esDL3sq8N
zoeYO$N(wbBXpN+i5}c>an5^!ySxB4#H}K=MSLlF|1tubPF{w5O)?Xw|@Uj+aYf77`
z65tZ>nGWx<wG-&KC|@1XtYLlr>?xcftF&#Mn41%Fl&!}x$uAxVayWoVx1LB9c2;w@
zC)+UlOl&H!JOjTjS!@8d>H#I2p;~5pg=B~6jAYODc&Bb4G%e-?UX%^UJi>cXskB(O
zr<Y2!0dOgfKFC~+ildiRfx2=q3vKJ-1qC#*F^)}L;-OZPM1z~-r%e08&D7+p$*>a%
zAQ)0Wsgll=-J2{7b#F*c&75zY-q^Z1P1M#ZF=)-l<D2xI@<wm=bT8r-xckDqx6Yu~
zY$<Tsu$9>3*?19NPolSaUFlwB;=k=GM_=;*J*HH9x`mnI<57ZUFR)=QPN(0j$`=n)
zGLPl-ZeDJ?BtYQEIrAs&bFH!L{>)z3=0e)lLR9f*HTSeHrXn94d9}?>XE#jk${deu
z)Yj=evzOac_ou^@YR2>B4Ju}kV@X%#Me_8(Y?~=zwOh!+!qoht+5dMbPty0o6)=3;
z4laIp{-l-fL}o>B5BLvS`|gL+<BT)AucNy9LEf4@9Bljw8uepLwYzT@AF-qjnW(KH
ze2)Fm$6ITawJFW7(CfW0L<s#cr~ym2*!NfOH;-Fy!1;q;Nv6YFo|6>W)k$^7BB=4$
znC<%0q?mY|*`DM&d?1uc(-)==Y%BfBMWSvKTo}2a6sWDX?OlkCPeMk1sNK%7@-=ac
zOyegZQHONGq_v{kUViI5Yn}UQdnioJnnTq6AU}0rz@OsdMa!Ll_VO1OI;AMS(d7Qf
z!I4Ju#c7BkFZ){2nJ@W_1n2Hr-S3Z6SKE?o%6IJ3=|r%b-(;;Pzs+OaF(yjt?vo7W
zZ@q$3((k(4-@rO<l729Z6kl{<;rE)=z^05g18y_TU$=OLC7q>neD=JZu7^x3VqN19
zCrOrerQJL3>4o>P55rodp<3ywtvFpgN+|vDt|9Y^_;hhmm~OmsoDG~B)xYEa^zFf`
zU8Yrxa(cjiE1pPH^ya{uBv(^6UtoFTLqEaA_E0xeypqKYB1V7UmOb;1rnSgag{2Al
zv|f$8@+;@r(!;y5QAzUlgN@9M&*eF4tIfXmu3S&a&A~Z0>-X5wr`ft~b(?nb6PE^3
z`1@{l_SR1~7LvOz^r{1we&h~r_4ppye&HNm#MZIL`JHoaUpLD;U6z#wkMl$*Nm=l1
z8aNv*zHN^M&tpHk%)*PGn$L%CV&26$A?rMG(OGA;XL9O`bhfyb?e~{=!VAARZRPRm
zfV8k2wVKWU!ieAYD0R^uUT&S4_Uyi)gE!LgSK)%_QpeTV_xN(!*u#6c>{u_SJ+)~0
zXK7H1)TbCVeDQXwTGoqrdH0Kh_cKN+vOhQ>`afHmv*n!@qIL?&l_V(Jw*M?0rPYWz
zrBQ9|(D=d+@V3u%uloLap`A7PGAC;51B-$6m-WRsD+A3k&)URvekHqpdenQaU&&M!
z|4V2$_wKRFCtpdW5})}ivyMISV$0imgOA4^rxTmDDgSV)QF^LL%P#x_fniwZzbEZQ
z+mfWceRsyDR*|$d;^h-3G#d=vS>9yo51qxY^Lo}YEy=FncObsbq-2atW+lHFxfQ=<
zpeOXe#X75ev5Z9vjU`PGJ@q=yuZG%@PU3e813Lu|&2Wp5sC7r&8=&s$ROpd{@ye1(
zPO1#S0{F3<@;H9O)Qi`=KiSemVwmAk$+UAYiz7=>G!we#v~~k`tCj@h=rNLjTRNUp
zS1r8j08R~DeHY|R5~ygr>na%&XCP#Ww7iVo4Dm;7F@|ntAT}yY@@5(xQimfpIBdBA
zAEf$_*%}Kmd=tYzD-P+Yg-CxCt;txy$8pZQ-6q$HMr$lw$7aFyfeYz(+qpQm3`LVA
zCC%q+ib3KoCEKPs8ocKDP*!<eJjB}3k&;FXZGb{#&?$BA6Iv9$%^~EiBg5t#qJpwB
z?uFSF5@>Kl1*LP|zk?F1<lAVSiKh`6YOB*`Sp=dO6D;jI=5++(M{NZ!qUfkj*IV%7
z<o9&GEnyje#54{O-4vWT;>Sgk!6<kgt|bT6K&)(BNd^_XS+Bkoy&-t2zYX??8ZerA
ztU&RRcNjy|hOnlqJeockyV9y{;jAPkLW|4-JUqW%tf+8%u^Zb{Vp7FvY@4jGV%~=>
z4;k6&J4Shw2Yms^gEGm6L-dhKGC*c!EO=?X@H+Y|mZNa2VG!dL>)GCN65>e)gM{G1
zaXBy}h+4E(jFDnumn;*pAWsZwr=1kWJcZP5TbZ{QVY7Lt5NeqdqWMH6o6A8F@AL9)
z3Po7nokA2?h6&5~Nf>l{g$btU^-S8~e=7R>7(oy8EG{yDnVVa{l41neKtUrkJXV0;
zOkS^Fs2y0<x{DkUTy6KW7RXjP+G?rgC+mf^!Vus(7=WbdXnP^2Iw}A^JXi0n^N1*P
z7jPd4{@;T!%P(dr;ZbQZh#JaXNT2ukLX7PR6i-q76`?JnjHP>eK+suxRjnn{RGZ@<
z_{flju&i1f;71;@YJ=*apvpD}*0VaK;8~)!I;Qe_<j=q0D#tk#g2MAs@6Xr5@D?EM
zww}_H;{w=y2sQ;TfXvsHeOf+`z$+O_9?z2O)CIiQz>94$``)rY6MHyXxtKPt)iyp7
zSyAX`7BkF*8`dZ;Y_o+BKo5s7w%Mcivoz2MAGHfI(I}aCW{Ez%XOD4MrTeB>*vFDq
zgL?k;w%M=JN3zrfA#V;@nufQK>ZLsLF3Oi!3(5{EMc0SRXNPIS|JWF>%C?dusdkdP
zFJf=G{a$$UX-3xzN$RQ1a#|w^CB1SXv*QJNJeBCWknK?V6RCaN|1}PB$R-E<<mOxv
ztNDnZEYk8CMETimBU$(IH7QDEKyA(Jf$c?(+PW6A5nWG2+-+TH@C}#?Gu!`^njj63
zY3jaj8lMVj_~N(8EGjVbgR@!oGiDBq0Y2kc1T@Ng=QZQ(wvy}+m&fWJkGheG&e_2e
zeDHBE?KHE6+ez_cg{ZvW_+5&)at=L8?`;tfO1^%$cv+s@@%c-$g~o+(?VPmCt?qdx
z=V@PLv)wQnmvkyB8<|<YSb7#ThX0qF;teRqaXw69cHgn5?4j~2ud(bo*Vu7K>c;-B
z6_jl-l#B14x6bDq57|Xy&c?3IQ}3Ha^A}*N9j2+|tgzqulVI9y9oRl)`L?6^%$q)O
zS!S<0$6N7Wdf%}_uaDh#Bc7`8EK9@k&)Oe+`5GSmfyeQWaB)rz>h<sa{GoK{Ge>xD
z<kowF>&0wnPZ4vNfkW-7&<cc}uSivIz`312?)Er*o%vlMyZp(KwDXTY=(549Qx-vJ
zto#1a+YP+Ymi;!eRjmhw-u*JnelTTT+Nq{H;WDWAv}Ia154D$Be&X*3%2Cy^wqf7$
zKlu`+nke6$wDORiWq9uR7K7b%j<Ba~^179V{V0K(LRjd|ce*n+`cH2t>_7imLjE)!
zN}Iov@AO%7w6m};8>VdTT(S+GsBI^2DYE6SFSbK6Tufd65_508X`8v^gSkD|`v*!(
zd5m6Y@rtAF@ur*3E=xM@qtlkLNM+FV{#%X6JH$4I@WYGfw`$_dK|gk~X=ORs!*<az
z&!&2M(_1Y&c)6=Wdhr|BLkGW_nIu@SyE#!I<?#);l{Z9RTerP<{|Y{U_t3WR+*4Qh
z80_pCM9rFC(!P8=BrmE`R$H{SdowGE`t6-O+o1jjmD;N3EET7j*Pm4@f$_GN?4j!_
zO3EZVeQo8jM?Lp)Xuata^?TY}9lVK^y8TRIO6PgaWMzVspS#J&lJD(yLxA>+|3jUc
z-CwmTXSX$-+28TuvTVs_mVV87yFK2ffTWl{rvZg2R5jp}FY4f;#_-oC40GEix_nz>
zUe|72UQ^x7dSIYSxqVg)gb7;KO5#>4mSiQ*ZO6JudO1AJ!P%Bz3arVDORR<MWzZoq
zb02U}aFk!uc@dlORKMPYiZC9{>H!|Ap;v8PeYqbvrhLk&=z{4x7(F0ckvcRb0g<&J
zXEme($G{t1VkjkMhDn|RrXP#Jn;LN_x;CVCaETmz(9EeK92`q&tT4>Y;fRBQZ{tv`
zCl`Sm$vE)h8Iu&CGP;1#<~CM%iI6SGN|I1aNo{ousMf%$=JOTK+0Arh7$T3Q(9Ou9
z%k>AOJQGw8fuNo?cxLPwzHFUuy&DSYqr}bdqX`;&nuRy2bD$GR6HJIT>E}Zo-p--F
zIMAdf^|rR;+X$FNmQYBW-qM#vJ>Q3Q+2_`*QwB+Pr$y2VDm<f9)vB6aq6L9LR6%lW
z4vd#G!{+(p>51q_zpNC6b!4d_SCvfJ6aa8MAhR?Utx=-&kV`1uQP?HKwKA|q(l*Y>
zJ8AO{2(RNePkZr>oFbu`stBGPJi!C;1g5rILl7T57U~qrCc>m=PSGF4l1LyN%gY*H
zfgQ`16)}$_iKum*l#rmG_EK_uWBaN3yM>5si?^6Loc)26PFO=@w&1b#GXm{xa?~wV
zJcU@r&ml1IG?au|PAmw8UmI526Okocn?lHJoR=A=#H$E1%*?1>OWY-k8+%#|f@CtE
zQGu!G=P$I1XgVBx%Zp{|i<OJUDL7sbXTDbuPS3=FgZU0;FO-9)!4#las&Z`xKKJ1G
z2An+x-m?obMqPKSn90ou)p07JrPs-nz+9cb##JgaJA<86k6QJVpx}Ul9H&n5NjswX
zdzZiwG5vsSL5$#&V63E`(K;pT2vI1CY|D$>#(pn`V@&ZwtP4?mxP2>NZVD|w{3;OU
z`2Cz}=TTTy4ya}1;Z?4*OKBVrNM%a4`1qF*d!Sx^>IVElPo*fbs1HeY;tZLsa;B$R
zw(WJWO@CMTCcv(unh0bX39|RyRa`X^!M({+2a7|(>HVsmO~KI@rM7Zf*L<9|oEC>Z
zDQ_g|uRSeUjaIAw%-|cHOPqA$vN|NzU2s!@sbu(Z@6we4vlT9bv|FpS3{q?iu8vAt
zdmO6YQV%oMqTM+XQZ6Z-Ak-@+3BN+2Uo?;E!(1^QpS=}1!LqeK&@%hamhOFVV+&`K
zQ*T+g-xeT!<?v7NB=xU}IX3?TkE`~s{P|9IVNPFU9SZ2BEf05}lg!v}T<eGYC_=w;
z+(w_?ZkcuRE_)m$To`Q8Hp2Nf$=fE@U`A%)Jbyj2rQDv%mThwV%m>`FLK-OR-7u5m
zII(w;X`=%%qcO>hYHQW-QCk((7qb7t(1Q+``FM58lU3tD*9qs}Y`Uw1m6zY-lE+g&
z%Q6eQ+0u<KIX#X@zn#vY+9f(9oK157OJMsBg=D&JUwv|p&F5Gn*z4b8*&b6@(Xu!c
z*rFp_=Or|WJ$`^*hfn|D;J6JO+UYoa>ZP`3w)@{v;$I!K<y#q~;c0U?XxU?afK9hQ
zH0!){n>C)lL*vcx@*i6GtLI)v@4v=b>u;EevD<p`fpX9ne{fq8I{z;N%Aq&2$^~cT
zQ_pJ;q|6|SZ@9%kemjwR(Jd412Has+<VW(ww|#R@K09;4=+wEVT=s$G*R0MkH{mV`
z4|E3X@dKA+zWezk3>>;b$dW)bv(F#mIkVDC58Qf>xft5dxUI=DWL!+(YZwwX5M<o<
z_9Bw_{RUgx6v-cYghh5X7f(q^wGV!;$h8sLp5fveLc#)p7g6hTO56{+NW+wE!NSLp
zYPU5~$ansDYA3$6w`fU?R>Tct@;dFd?*Fc3i{+p-RmZpf_q!L<fqm>-dz(Kpy`@)3
zv!%CnXZ*~`Zx#N;KiJ&-(-*U7Mkep%qy>kBv!A=r$A;wpuYci22(q=;ea_see?TB)
zd)Ehf2jeX_J=fB~`_f|SjwHmA4$&re|BV&*euIAbforVWeIp~+Bl`+nXk;7`-a<W0
zTJlcR)^P9nK5u`PA&Knjs)&LN^IT`U{b<5b;^EHa{bZ{{b*_Em%!n=(VKJ_%&N@}m
z{jc={@5njM#ew(>gZWgaNpI9jmVJz-ews1o(Sf#hTO)Y1QT4FRfov-v+oDvq8s;lV
zSI%=xrhPTa5)rgWnUU>5`_i~cq037>;SVRvc6|3pwvuF{NjH6vpv@utEb+``hg#e1
zhacgyPs87hqPwxUX*r}_o?`Bm6ieVgwk%b6*_h%tOKL}tonmehrQr6IsN5d1n<gyw
zrjXddaE15!pro-LW{sO6+vV6K%CDuLp3JD_&7n-@T-v2jZqR1pcb&;D60g#E7A;lH
zLzbX!dh*#E>ZEfO7Bf7-D!o<|-xNWNOH=^T4cK4>kKIv-J{E#Swl%cP_naHrP^+?v
z=@!9rwLF!iHA$qdu@#P!v09FTdaXeCll)%$TKdYTQ=6abKatSa4*@0p5N|95>^R>g
zm$t<C9NX`Y6R0dLkZruI&fy_RaN^?abQl7L(;H~dVg^s1(J%v!te7Ii(?0wVQ@ROB
zLi-SLB1O!G;Nq2&NQE^4HFAe5@LL7)cdDKEQe-T|YSbnUCJ$1CW6iCrl~5IswPh(X
znH#q00FvW*O125NtuWW?MAeSc5LUsKvQ=(Ysh(1b>!esEzr5+aQB7IE0|+_iQ=iV<
z7-javXv3vSm9$vor5W^xSx3Eg*qE55-AAgC3mRz1cr)wApj)JoOyWjt2U=Z+av_@J
zAT@(6HP>g0l6j5_Ez~m8Lx-BYk)}9JwA#c>fUu4xI?KX*Afz8ms2wlVdw&Zqw_lXV
zYZ!(OL%Mui%g_tm#E!+vhrCcA6G}M%)l5eYL8NEMSsAq`+s|XGQ2a+2cHD-dyM(Gl
zLhB11o6WtjME%pyda*pzS2R^&992V!TZ(>VtD1}J4u@A!v>G5!Fza^Y=mT`3nrpV#
zve=mTjPNM}Q8L#WhRe)BH(2+DL<voDIt~^mmsYfFp4mx4SgA038LN!3=vwILfeMu=
zk(y~Y+M5|ZC^nqH;G7?HM0h>Wh>AG^x@o0Lu8%v58|DRKAn3P_+;045K#fZn=sx-+
zeZX1msJv^4m45@1rMUGm)0HQNNy4GpcF31RyQUv+E-5_$y`)uyTWf>FZ3HVUmJ?SO
zY;|OG>k3^ZMcvV#Er5R=d5`sE5fraA8fC9>BSOub`O2%f7*x?+FVhO)*``nFM;(n6
zDV0}Di%l=I04evp#lr*lZmWujHcD7ua0cRX6p|kBc6!1hH}AuZmL~9a3qgE~&2?Cb
zVYk&MD|+&s_RCu3ZgK~KPngnX<uD)jxw9wmnD*?3Q}AEgjmoL8TWF%ERS;VCFkRu!
z%(LmhPT9V6BzzP_l9x<f!UsI^zuA$Z8!rko82iA?e?)?!kGi56U7Hz2d>B(v_wm}p
z@4q)!<8eyBapydXWUHp6w_Wooe{p8>KV?bwG|y9^O<U+>sq^qmX+Hupol9&W{B%``
z1O5U}Q>elJ_gJ%<Gt5^!_F~RzQ+&7EGY~RU@GMu^3l{OE$~Rs79o`3fkv*tvj<bon
zbXE#y1ZG~lt=$;~@{;M5Y<mWrxprHnTX;Ni+q3oHhy0RmFO9pcr?)Z0JZW~U<fQJ$
zzZ0zc&_xNmt>qYrN~P%wm)|@Rsi)fH<qFgwF~qNPyvwrLW9%2-`$l_c>?1B+C<kqF
z@nvrJcy}8gf!P6Ppi2F4>CtL+?p~`aWz%ezv*{p&(MyWVo#GgBCHZ<!kuECvPw)%H
zH#mcF|6p<L&WF?cC!e0qwU}RMSHZWNS@K}Pg6c=XYYn>5d!}sEQ7d75SC+zA>7meh
z!#>qM&q~J$r>#I(xSrF7Jc-<w$BQuk0;Q=^e(EMGj~z;?BHng=tf0*)I-+m8#}es}
z;gMZ*h=}hv?>nXa(D?RggCeC|BU;t5^hfcVMy2dn!yCJ;ULg{{4oi0<jm->4;U&VT
zElakQ+FE@$LprG<x(~dM*&lT*-I#_;L+agx8c`l6A^+2`9Q<`Zo1--Lfiw)v9cwtd
z=O*XGaNwuh-}o<qNt8KdV(0#DG9URVANxP}rY8$AYU&RhI>)64UOZEDlwx38nsNN=
zp^CHKUcX){h@}!)(S<X2<M-(xeSuHid61e5Ecg}QNJry+uf0@<f5_~Coi0(`T-Lr3
zPWyp$f;Kyb@h;5!S-$Bd_~Le4yO=rMN#n+umbVw;)agvDz(=Kw-PU03`y?Y^MHpKt
zg(yaVdIeE!ox<%j5PM~t-LLb{7uX4@trgTap$>tfMas59RTa)Y7Mq&<8-wSO$SWZs
z^?F`bOSjQsSIMj8UYVCA7wZ$1UQ?vjH!p?$RWQ@O+cmp47z2yvJ<$E63(iH(cn;Mt
z)^k)`$(P!<=lojm1}-?O;L+zS?c?T~PI9alqHxau7~+gkK3rP>JzzYzh;TH{?k8iS
zv~<yq5tS>*0xjA&J--NrIoVn5iPlyOvdyw8l~uFiI#r;}mShlO#WCIWWXnz3HISdw
z%juq9_1pBTz6~9X#8q**3piFA7lXpNh|w!DSXt0@T^6{U?R5%xkO*{h>t0zEGnv+&
zIx+gO{42A9*`DJJJ9dXNLeA##RiIi%h=f(*2reF^W#Zlo=x@7NxUj%gov095S4s67
zvx(#}%cqUEM+%V%j4vY;-HwonYzxT2gPV5PZB+o1oo#I21>~_+=wU)#?WKmo1zdTH
zp)4fcG)d&SM|PTkQtlCDcSbG?Nr)9s_-4TR2DHTe{CJHgGUV<Zenr|Os{yb5MQ|c-
z8E03FNgE!YO;nR;v4RSnxPm8XVcs0eUkc+gaV#(QItc6B8#x12M;yPfK-Mr+WiR~E
zYHzoz*kl@{*!MP~RE1Xq>go#sz9iW38xFQ`1ShP<++;<FGkpfDVAN;?-{RC9Sylm^
zo+HL>Way(J>)|BySZeE$te#9Dv`Y-p4*ViG%vvAB#o7`AuVRI^Ijk`6={-TZ+!x^L
zB%g&sB!jUm67uji1}yD2#y_Bwm^+S5j2A<hpGQv1&5&eH@#29xp6tjOlgqJXa8t3h
zb$bb>RwYq|+&IPoj6Jvmvz=~#`mtcMrh!-xz0nnPBAv%a^h6`ytxmEEn)CHQ7mra~
zpns0NH0y1zs;ZM}WOR!3G6af<%?ms5<6&C^bpVr~%Us7#FaB9}=!N7gORz$=22M`p
zv`Pl$!c*cR6>+hHox(?S6tiGXOvD&50Hm>#St=rR>%q~HZ_7Y`c{T)2G3KbP-f>9H
zm{awIVE&X4^HQ_j3#gsbMIcoXbaT|5NqJuRgUIq+e{A6kQFaunmT^24gvZ?ck0;~2
z?J9RvI-_G#Bh;~La=rI11$m}IaE^$|?PPZgi=d}jjAKie-ByJI?6xjdF7W+8mf9yd
zS{(*!>Gz_}X6M#L(ab}j4_f)}$o&Pe4w(1N2tU@J24bh+qWuEa{jQl-3>$A>_ddKE
zvHOH)a$FCb<!GMzgC<m18OMBwc>Z^+yp~dYJ{Cl2w*a&yhFZ4{^L=Z{Z~h%iev+@f
z4gLIY@Wq7II;4%9Qu>5gP1NIDK5=9b{t~q*e^(y&-Lw-|6koa40*EOEDTI<JUqWnB
zyRCc@A$D)CE1CL&lB!qC2~#3`#n;kTW95gg@Qw)YSMIVyIwU;uBnNxSS6ROJ3EMLv
z^g}y&tA$*t2=Cu;ySEdcw7Fy2H|Y!W95G<SINbP0ZTr11P>DLo3ZOT6Ia1Y*<EO#L
zP9-Smi+mSR*}CuWA;W+9nJg(iV<Crx3r^N0^IXpJsqE^a>p)3#BLBX(!PZKH&sgmX
zv4sX=`UAWy+pDZA2FCf(oT@|~O9DD}C@sQmFXa&JpD$K1ea!5(CJQH!jm;f3k>(f{
z#;^A@KZ^4>vzFerXFGo6;@#s3-`{NO9A_+n{p>Z#@cvVFLm<F*zQ@JKuiTr0l;Ww!
z*;=DWw(sURCz7_No1n6Z$CGaO&<iYi<2wfmiAmRPU8UAg&c6>8pF?d9migvMupgE}
zEtE~OQ)FgoY`+g)IQPO<X=xzL^Z!Hdu56w6Z7CDW?{J0Z%Ny~PT0-WQ4h@baJ8yH=
z@$}fe``y9ew}hxrJ4wCxYThoF2Nx%z%ud4!{~=1~wT)bXeZh-|q4PXyD@hRqsd%8*
z>AJr#$%kc<nWR0e+jRN>9Ov!F*CR#!(d?T$vXK~kD-RbPE@6a@M}qCMO<UBsBgmw;
zO}QO;nE%eWk8<_rg&5V}Q2)BMMk{ZR)1Xw^TCI~(YnS9F{gqDJo`|!l8n9yc<Bho_
zqTn0hDzMaVPsc!^DE(j>1Q@mt(CWi4Z!3jA$FKOG)f+My8fbt6LiUE@?(fa!17uqP
z!)?y4Dg`fIXHx+-U&%YHq6RH<A0D^lvBAh<wFVF)WMtQ`IyZL2Oo?_cWI=NZjRQes
z&;??-aQTljPVOEux0RAsgP~V?0p!*A+Uz|}!~g~=0`;j!vQZ=#ZdMwPqFps)M7^r5
z0HCGN{@~Cxr(%YX8L`e1NxI4#@Z`pS+)Z!_h|lfl!ZXXyaSRF8Ip7DPcVaEniE(ZO
zPJ{}_8>$7ndgybc;(v_Cp|8@o%JS8!nHNUZC2X0OZ=`S`(ok@FVcq6o)2mC0PLi-&
zE1*<oKze_F&gulLbx^MIjO0$fXpmDNdTX7ZM4q3G>7jX4E|_Ka$43{2_-4VjuyZLS
z9F7J`P;sg~B#wU;-WtBjx}**i*bl;gQMPH7$ht{|&numY#|d?3KY$}}*U@oJVmkaH
zjM2`fdmijDQ1ohKCEaxqXLT0Paw$1$VQ8M8l2M#(ahJ&BiGc8+8hly%g__R=79}W~
zXU?82FVdWN4mnUGck#<9RmpX%bRATpS{HCurzb-n-<0KbtTrN8O%`)tJ=#INEy@}@
zw*XGl_M{lAQ9bss-Bs3JdKG+sg>RDHh-0*6_hj8(l*4hLMF&;ZO)=7m%;DGy%u<w=
z5KDe!6C{=?ei15uxIwy!7ficblBQmkVzfel@z2nFm5!#k1rRMDM>H<F*q{!!pCzs!
z!L9;+{!}c$+hsKQNj~vdX<@69BHs=Ls1go`@d{lgK@><(MzgOWG(Cu7S){hQGm|)b
zl)GixseQn2rJ!B)4M$_>z)1vOS!Ygs&S-zDo*I=hlST^XzYdgY6+F@tz;xw^zG`_O
zuHICBE0=2rmCQS84hh8G5eMqksIxg->eNX&>pYEhtjDkut~MOyn2TkjzoqyXdI@2-
zl_paLMVH8GoQ#7amZmX{xthZggd>%Gh8a?ShJO<ed5fe=gtIDSCNfj$&n0QQ`x6A7
z&pSPvkmyCVlk?4GPc)ov?qx=SQ~{nh%xB_+Kl=F+*+3ohB?4B)W2loElDAT;D-7X4
zk=$u6y80MZjg}fuc!hP~bcJ3HufLM%7B<eFAfnUsF*;qj+uGeq9S^C}7Rz>S^6#^W
z?7$$O@TzERW_BB$rp<;=PFwo%Y*l#kOBa^|omcrP<w}BFk6SUqZtJYQC^=$bi8C?0
zdf=@DC-=Ko-tF^yzK4uEO=|v~@u6$yg&|i_SZ^ko?z-4YMUZN0{->E&_-&x?nut_9
zCbuP73#~m2{E(mdT8mcSpIl37Yv<L)YvNo!?0(XR6bird8W&$c6xj{|w*M=f0>-wF
zUR5O8HIpJx&MRc+pH3gW<n(kLc#8aKHS_+^QRkXoxs=|iZLKGv1{~Vy<CRRaT**`@
z;?!dUNobu@DRh%$8wM_n$B?-HmbA?aa{ILx(UWf8#YSi(v6<nF4dc%8f#>qs8ch%&
zNAqp{+EbQs-4p^O@g*F0E?VCxviGywI=}cb-gR_II`FBTJjUC$RN7rd`kh;{span%
zqGtY{tAaTay7AZWg<l+=pGjsa(=YiQ*2V4z4pDml5QF{2UrzGnN^PZqkq$W&pFfma
z`NUxMi+9|^Bq!-d4O)k<x6V<n<<)6jT?#FRwA-3Vv7`b6!lsSB%Usm?uKzf*&?mv6
zb5t9lzx*a@{dAJ*CShrmTZ4hC(TucX`oNAEwIIeiX=@=T+c2ee!&*VH?@60myRMjQ
z;f!yKBC?qFkDvE|-8j}T|4uG0*+RY<v|QHM%Nx_5Nvmc`Dt22-kF8lsHg?Jd`}}*R
z^**&7x##?%z32NbEG#r<cQ1aTnYpFG`SkVYCdapVn?)dAQqOg2IxOQ*!*KlkbFX0P
zjN>i*236Vpz&~~us-&8@)YiScDp55vmWBqc8-8ILq67Iv`|^DL%*W#fgb&_FX}(Ph
zU{o6}|F{~;*lpGAN^Q11+1cS50Mu69ja1sHOG8L%wN;0N$*nn4ggZv2vX#VFO6LYS
ztqb<!Q1?-7{Zi`Fc-n@E8roV)MBL;RKiB&|EQ4O4%_&=z?H3#IKwd)H!gy`sq*p0x
zhSue9HfLFAdpHkidSw2Ip>kE)e?*h2)vGN0iOpO2=Fm~LiT^QV{3l#x;Nh&i0%0s?
zIZIWZ$?(v!ivJQgdv09WY$vPoZrf!S#ZIbf_9EUF!k0OH46Q3rTbUQpCs!foI^AFm
z+F@uAxNkLL69>ry|969;iMjI?Zi>}ACq!$k+F%t`nRVyThf0bE2}&tb8ic2!^aV$y
zTwY=2>x;0OP|YjQXGASU>;cL?zZ1uVa0pJO<habd1~8YZ1bx7%uw7AJpn>+Funu=X
zR6eSU4r|tNMxO9^u<Q7u_3_kFhkuEm7|MzfR2w}<+B7+j9V@XWA}>oq(IP_zpxU{y
z<zZ?9S{{@@w&s*o4KaZCz-W=&yEA9Ay@*Y0<(^VU&<(meR;96XnP-<(CMnx}M8$}}
z?xWq9f>SeESxgBU&O;${pu*f1K##&Cjm5B(Qh3q?gs1H37@k8QL@p;qb;PMdjzK76
z*6^}PB-`e?q#%wZlgPQkHU#g6&D<fovE5DMcjY4{6#OEtDftdGpp9#ObeQ*cGX<%K
zNIoSK!nEm$*U_cKD~wqa{Hh@ArpJXcP$T$gI%E?nXY_Am6lofQrvz|kiz<ohp$<^m
z=z$qdvr>Ys0rKGKWVBH=VHlCxir9c?P~mpUz`&PkJyN-@f^QL8GWjqP3e|<xxIT_)
z;+KTO;)<jcl(it*;wNF%#i`Bd{5d@$UcwzwWYFGtbkK}ptmvg(jeWL*azZOINm4hV
zWRxo)LX@+K`<*;u<Poq`BFdI7G^zq;E5`6rG*;q9{@f$f{cO{-NPu8KwnRJXaaf0J
z55hWkFYIhK%-5JOR5g$FDLMDup8jECPN?xsosGgX!U6>26of`0SgK@NW?lJKY0Clc
zQ6$l!*dEYWfgWz?1^2VPiqLx;X(S7Eie>CTNd-Qd7!xp-Tg_z^NctF!;gIUT0w~H@
zTIWE*41c7gLXN2*9lM!cLk1dvJQWtm9tXZvh*<{4E`BP0Y!R!mZq+5ZZ2{aky-N)E
zXCVI(VrRGYGJ63L=Layh0_cIs!-KoMp)A<fqjs9{0R*Y7732C6O%r`K?Oft{fr?68
z;e;LF(hlqI;f`5jwnSII(Xq-su9&{yn2Qyf6mgR<OL8k!dx3Ed30D<VvdL@NaU{z;
z!iRrebkzf*zDbyV5t?1SMSW|Q?kKgI&>tL%X3-4$RiU#H-9si>8tB@oi&<lT(KLG;
z32O9Hj2}8A{J>A~GSkxoNSgfgjzPLKOV7T57nG0RleDzk8ZIMi6~7wEd6JZkkl6tk
zCrHdE@0D|N2zF}FI?0Rdk|Az@I;R|(SjEq-&W+tx-jLsw+E;lr-B1Z=72#|SkJ{?L
z+NF9@cKG%mr(jH{8`n4~9aD4o99v=u7cg}e(bA#<BegY%Z4{C`?4;;i^1IyAgU*)A
zv%~UtrT&Min}oCE1b6uYx%S+2vee6W@{PQa_r+wJUZ4#-`9S%Dr$$m~VS6c-7iam+
z=P%e8iu&?Dy>$7ZNhR7Gy!N~Njeq3d@nc^|9^6Y^DBsUNHIn|?`*&~*7v-$gW+Jrw
zz43JU{ez7E4^QxMl=&pTYbfzk?Jzr=ks`f@TK_7~-{W{@Ut&4m$f0jg^Ab2(Pm-tS
zSvyLoyp(aKKe#e9CkDiTJD5zlzq@QLNebDA5Bc^oyf^N+-qaQP!(rZPbfAU*NFSF>
znTF_9P8|}~=D3ChCe^o%OObO)<K^9hdxR8A02kV$j8|nTk^AVMRCOYZO+g)Im3ozJ
z{De-`ZXRcHEH(P_BSqXwwV!**61^KPzqFV0_$bs}o#yy!UAy%*?@p}@ZfPcQczUH_
z+mVy~=%QxB6~yDt|Fk{4MI|}*86HIN)47(&Tp>Jm!^vcD$}azK;=5rNm)qvq{I-7{
zasI%oyos8&;n{7~gpyK$A4jt&p#!fXXba$l6Gi!vr16O4FL0tp4TN84*Z|t!P<xm)
zas~B+gEtlk2w1)XJ}#)xS9H11E~@U<%5VM^5PKZYZ7+xg33WIY!%RSLY$qhj!v67U
zn|3XJ6IYLVoozLgtAZ3!Hf*%~Zs<xm960*?NX92ef6P@Uk(2ApzWO6%-(fPv+Z{2!
zpOKulh&Yuzaj~z(<D@hvOG8Pjl7!3lloCUXObBt2=4ZKAz|kE6ZWK;kTI@}aBp;^a
z5x7X%*lq2BDzwVTK3v<qs7-CMLt~>l5G5sxGdd-3{FoC;^D-yTmLRLJMl(l)Y2k?{
z&Z1q#h_#f0YPVIS*8@l50%cH178EXqwgzC%uVT9BN^QVgMM5%ci!S-9quvv3p75Xu
zLNqa4m81G{KL|olX_wH4ojeh|qfkvnq+T1XZR^I}+rT6(a`-}GCP7UvCOb;H2$R~L
zTZJIkgp;`n6<e#`{*C}ja44tPzW!lVt|H;#5SsjANI!!DRfswy92on0@F?MEkuLg|
zla^O~rX8Na3Tek+41Wj~5{>ubrnE7)Mxuvv7F)YLt6~WpGpHb5_LYgHgjZIX%@jTi
zQ`Eymi*CZynV-iQigQ7b4lNIt=*#X0eA=od9G80M<N$(*Vkcg{hPh#d#I_S@6Ih~>
z2firh$eL=m>``fiYZpSKFo$@~V8N5_89^~*6GPG_%P_?G-c{isQ{_l9ucTX<@q2X%
z@g$LjfKhYiRY#(%h^{w^1=T6Zb()Z&l#&mCdt7WJG=}3As;W*?2g2q+wi(o;wn)do
zli>l{{6dWI0fN9HnL6{D1P}4ynuBl=G8X@u9Ext?sW}syec>T6oQgG$gC<d_=;WO#
zLL^u#mPaoGGAW|+1DChqToMlylx(G)2JMaQrdA!>Afccs<kYImO38<(Jp+iaaXR+B
zJJuH-VqOj{rQre$HohHs)S&B#L&_4<;lNu-z0ghVWyIOY&<2b6a(wVf&JZ4F3Eq)O
z$|4WTJXZQ-%(B$`R-2sXVSLzw)=V{X#4(Q}M?9S_MZw(%P7J``1Y-efAhe&8KADm<
zE%SVdkD*+%p)oFyh97EyHo!{*BO!?DD80-n3u0h{&eL?(<Z?Qv*v(;150a#{%n}0(
z=fhbrPYR#RibC9y3iHEr`K&@|MRhY%P8wXg{9?9KfkaKjmeLlMle-MRwuBI7LMSr~
zdyLBVphqgQH-|ZWLP_0g2wIftaM@i=a1^Scfp?!dTjAFqT0ESERmsT1iI+FZ*eRGL
zIh|`)L~1)3tJGA<B(qX!Rzv7QaRr)0TL7|+h^TZ>*D@m1fr@b)iqOKGSLo_!qOu`6
zv7CS+1glVXZ)I$fZ1g5KV-vj)N>w-QWumHCRt?oOn>earjD9?f$MGX$wI;7WJ@xBx
zPQ^b11(_wKaM}Cn58`YmL)B3+P}N}nM4Mn7*d*?MW0e2jNP82~*(PzTQPf2mJ;HWY
zReEedt0-r8sEz$wVN=e!J*s)dSkJq$t+6FCuGiLz%*m4|acqT2z(t!D&>YqHfYf8C
zoI;$$>A<#afkZ;}4r2=toU5>$$IiVe+bMn_U}R+GVkR-$)ozJSt=!IlaE7msM+~nA
zCr?6dJVSVv;t87k2o&O-Ttq)JQw6UBFrK+8{jaU&s>rJ}$-K^0E)QF<p`pg%?E@vk
z)EuCzR0BM>H9rA(MDON#QY2lc2nffC%RHz&#;h$QRe@J=?j=o|OoN0n3I~0m1Ve~j
zvL{>73YeNLt$U0Oupu(#$wZ3qP!X&>A5omWm~6WmgEb0j;0(Ri2j<40VNwsi+;vr7
zn$pA?bV?s1D2X>4hiXle*$;n2Cg~KRUeUT6SkfgC2TS3i)1x+p$1A*=V8o`7*cO0K
zS(2)5Npht8Jbt<5@<U4nc|p-{Wv5CBCt}WrN#z>Oi%d&~K!V6bs^N20qZIe5O=GW3
z2jaen3K0^AxmAF2gr*)RKompew8@SFh={zD<Qik6PbgJd=j0BEL0|mq528U$r3+bD
zn`EVq<$VnUH9$IMmL_Ek@jfyU66cuwP7_wx5mf`tEiz?#48z$tRs{}AQswyPpp8{X
zRm{d_#lHgq1vP>wMDUm@-)_{XgtfQ+pxzoE>r^UL>=tTS$3nVZdNo32Hp$Pg<`!dB
z^Q7yY4UV-RgZ?!}A;QmsQX%ThKt5d+yYj(KgoRMqp|&gEhGxxq=0|D4!U{3ORSOHf
za!~}jGk_{wFk&zsu{n!y@<oh*fIMNG{80iG|84vN=pMTQc=ff@ue$1hjjVL45~U}D
zXFxI4^dUU#{kGfn(VeZpZ6K9;ssA$rVegSkt0aF!VOHjG?@A~Va74#(Zn5f<VBwr>
zx4zb>V(|g(EM@ha!{}GxE$$L_U(ki|nXZMY;K=L4gqpV~97|g8<Jk&=Jg?1V;a3U$
zdh#G9AQZ`r*XEM&^6j&Df-yk5$YzY(*huY`Wby89HkKTCCFj7|BcOV0YUhwsCd!YM
z(2Sc-8fjX-nXdK(PhFoO(yJ4m0h*s*lczqDI)popUAT4!y)W}G^CDNno$FRmx5Ak%
z-(>%hQ=h^7C~E7Ae2-92vpV(vAlb>6bCK((sDiCP_fzaa9NJmrm;X$Xtdwm104$|<
zwM%33taQ^tjSnv}&{g-bw6&x^!?J&>Ia55GRep|<LHkEXzs0GaEkJd?j7weO>se29
z2Qv@->}rM#-sI9&&{X~|9%U=n8Xx7O#T?hVGe9PpQ%&kZm}9qSs)c~BFJ@%-1K(sR
zeQf#bxjnMX@hfhQQHsugWyMIDNPv_r*rVUuK4(w8+4B7>=#dkw20ZkhMRRZ3=4^Zy
z3$xyw4{6~}zL6G1n&t9UVfdb_>e&opv*CA9KO*<wd6-*)lQ(4?{LAx&4n2#P19>V$
zKo5q+pB>=JYSv1=c&>G;@IL0LbDhevw&5oH!SlMSdopR<EMg;PN;@iSZA@}iikSl~
zNBjq$e>2BmR?uW)9Y3k$TL6wO#^#Y`ARm457h`9Gf**O(%E-^oPbT(`?zDyf#Foi6
zHkQ1|4xZQ36p`7!%PUDHhd!dXEdWKBXTRplPt0x4)hL1d#1{ra{-Ir#NPzKd<@k5E
z%@h}1##fV$I`dC&Z{^>3Gf&drN;!X%S@+9-7|fMB%)R#fB|mo)YyT9#nE4s=v0=cN
zsZ@@icA@0%3n%{Kve~$OcEe+hEd8x&Od?gNQoh{V<)6Lu0S&9&Dx{C;uT1Erw6HiL
z-Wi7?JNg1zp-8VJ40jBbja%`QjgV@qC4Ia{lM{(n-tP3eno}c9>oKwyzlja?;T1Y&
z1opye$djv>e~X{)`Hu6DjR(_-3kr7l>-eL)2(4k#n$guxPrQ$b^;V#4Sarzp!xy<#
z{68C?Oqb7_to*03(sxsAmr|v_&JyWU6XD8l{tEkqe>q!PanSN7ciOA%_Ib;WbMvL&
zn>dQ!9q`x9$7hOaQL?B2nf08T+tB(rrR>_58{MpZ=1F$1q?(f-pqj@vr?VD&|C*DE
ziBS0X?iW*rV33peyflCm&wgRljK@2uRFE@nq7=gBKsHLXyT%GmV~yH+Tl|~N1T|D#
zi$_>Sj4_H;lztUB!r`i#wyaIdd(qFfW8p|3QjHr|<AdV^9%840fZ&o=l~G4Q=>o!N
za?x^3$O~vX_zrtLXxEOl^-EGCC?Mvj2XP;m0^eVRP;Ov8?IErlBGeA)S9#{)J!q?A
zOEAXN90p?bbx6^Pmz#vhc|Kcnm`H2mJ{2B;6kEb&x^4ch#Bp0+z$<82;;{OG1F<Ty
zF!LtE7rerPpTT||#FtK@7Zfxnf2F0fcO{mpe6C}Qk#>|+X2Ge5S&Mfz5KLd#4Wc(C
zQPZawf|BPs*60W10XQ<>^z$Cqqx>c>9u6uib2$1PNqAgQ{2QBypcS1MeC5zOB=oo`
zL<J(xJq^D0_OU2kHVKZFKyq=|gE<_Y-zYl{Q|lvo2xqb5b1HCaO)_4`W>v~&v{W8J
zu!i?y)0M`2p$Cq-v67EVfahXM4pr(N!p3$FF$hI;D3X^%oC3(|(T+4hWiZB$0N<3L
z9|ub$Nuep9MO4kD=;L~P{C&Y`01G;ow3zwv)xJeqI3P~}4T+rm5}6F;kHA!yihhvr
zq)WTDVY}9OP=*@a>Xyi3@B*&bh_km)(;-OElVIiB#6)ZHM32ZIpBhLm3Z7qExv**w
zWN!&b>FfNRt5QU5Er>pn(7tX_u{*qOcnA?SLm(WV_R%+L2WvtxuD{_xSr!_PrC1te
z^I`=s<S)o3cZKaUic|5Ruo-@>s)m>I<D~7W&5GOzoXP^+=O;1OGs;}IA~3{d(Gh2s
zf_9?If-RBt+(2C9^2(Y$C9-rF;z)L+rna^Ue$}-V#}zbe7}D~9YuCkeA}@_Hv_6=G
zJnW}y9gBBF_oe9KyX@UJg@aK|{3P!)Da{qLGQA9y-rK{^3G$$r4+g}!24nWo#2S9U
zlH@Ab`J3%q>Nlpjn4}OTk)i^-+Rd>Se^IH8%+J6HYU^nG73`!hEr5Knb;u;(GQRo|
z_?ic<;zpkqx46vJ!cgo65HwrbW921W;i9+hbeIny_XStYuRW_DJP#f`&pG?0<%c-r
z!$mWf&W?pY4XVM6S{EZ6i|hW{B1$kUepn;~mj#(#hGbU5E$Igqd+v?x-1*-$3qDK6
z{lzJq1#n|cppaxm`FN54-sH=R1CuBuHn1_BUQF6$Ry%(e>kRq3GV}g@G!Mq{pFnNJ
z);X&MhKGD*t}znFnuovPwWbdT7@2VQe<aJo-(T%!bZo5E-eRq~)7z_hL;@{T;5dLG
zxP0<7k9pK++xPAy)e*i<<4w+r@3J_!a2<R3SDSMxF{)Ma`J3EHPmb;X_2$&WN?*_s
zN;~ltd*Cx~8Q9&Z-vN8WvBr|S=O<_N@b>y7r1=wj_zu_w7Iyy+a{VsH{l0ol)|vFz
znKdqF;5gt;_!A9|5?lx;pR*!9l}Ep$tzrvmDl^E;yx0-Sx`hb^oeek)ao&;@f5Au9
zI|EL4+N^>O@A-Q#vWe~IF)TjGj0Q3FgM9yS`o!nXsSfjvpN1zu)g=l#eQBaHp$Pu7
zeMbrj+q@IsS~d9KKj&_CrQubA;^j|+v=xAQF70$djp6nc#0WrPxXzZhsjh0;iSD%4
z9eDNrT{I*etbsGV4ivO%Fq&P)=Rl4(QhV)=$YsBbgS5!S9S5v)=nY(It5QNrrys*#
zUNLtpo<F2)nO+jqxz$V}oqnpZ=+nK)v0}v*!y{b4y6+O2mZ#?a(`8l1^rDlF>S4rO
zkDvR%RTwyIL>FFe1(Kc26y9on_AyG?K$NSAq}qKtvx!rK?zr^F+0~d09f6m@+#^=(
zne-epwDit(m{8CNT|pg@lz(gwG1`0O8shyg{$q6G)ADk9+1?r|Vb#etwyvVsD@kx<
z+p@2P*pi^2#lb0Mn}oN6@$JUYXsh9)wrmf^`3y;DUeat6fBQ&c%-47V9ojgjwU`{u
z+Yd7p%ER&G{R*cTMLguFtQnyf)6=#*!i(3rzV)F?N?r3QTilynY!ls=k4z3cG~I6G
z4MRCv;K0vJth0K^?W|>F;lCM^1t4`vy0|W4Bd1<0O51z=eAb0F+|<?Tlwe4#q;#dO
zc^ln`#52P?bqmNs64d;h5MsR{znW(v=(U(3B<i;@SUY1t@Ps(F45(30)ouwq$iP%2
z8fQ(=%F)QZ9v+!9bGt=-n(Qi$%&uK46QLjm4zY%;Rdo~a`a{MhpP%q-T%I8w?XCeu
zP+m*W_1dkhGfrW3$!nH`nmvpdTAF~oA2urpwGB_J&~nk4@m%9+vlX~8ceDa;wmsMy
z;P&#R(+(3zT9w_$OiE4r=PN9ozp9yI-9Z!j8k$w>;qFWxdMd3~1P_e|?@GL`^-Mi}
zMh__}TL%xFIg|$<2Q!B_fvk;jQX5NC%~EO{r}>!{BinFP%t^jPIxA5rnu>=)WkvVK
zMt(8rx)fnxM^$4%xV+`jaU5q1B0fye5~U4VC}B8E-EhcC+<;reP`5F5De$feSP6aA
z6L2w@@=H|;*`RL`9C$gu1!w!>nrie_i4#>oEM)(ZLL-n$TveTna!6>LELEw*D%{KH
zL5X9Hu6O{v21jy@5Z0pWkh57KVMtwthD*dlkA%WqXI+_;Peqo~hihUI`;kvRCn-5^
z4#B!%3>0!o^QNzIJ4yhB2I{gzH@5{Wu;~du`&EnM1de)b*yq(o9ubX>jv9{BA6%8B
z6`v55JDM?^K7R(`b@6M?V1Z3fFT~d=RI&hEuh6)?%2zC%OXtV8HCPo?YYl%jtlJB7
zJ;y4aQ@s$`s|nTzZsIO1u1?k%&#IN<M9^5`C@o7BQYpA{RCSVCrd0#IlB>adYj6Z%
zX}TV@`(BdyBurCRtKj6~{%vIYHi?&KK{>{q2Q;D?Jl@ObZOsJG1ap;Dn~~g+I_iv=
zvv`D@&_Q!-uW?BbqFEW&F|%WdX~)qW>)Bj~aHcc2mFrAv`NMIxgqkP_cZ{dpH=5=p
zk8fraE`E41ZZ4iC=guV>h*iQ15cg?kSvW@%IbfytyotU|j4xhfDzYBO9eenKR8P93
znxtiHr3SOFQOuTl(k=X+;-gSZTXMTZcc4@Y!Dcs0kD%v-pNe0Ji=NGl2D`0G$%n6}
zW>I4V^a0dXKT-b8LiD$yd7PI-PH8gwy_5qjD3rW{s7`d{;KSEi%HWjpnX%0Ky@>w9
z!~ls^YHQ`I&A=DfvwTZc>-R1c3w~!3H~3etVug;XF??m0h2Oe*-nrZ6Bg<#x@+=Pn
zwl-B8Y+d^NX~(A2MG=QL;Jl{&Twuwp=>HCmYghESKvec8$)q(nYu=2d;A^1pq^(F(
zi4Q?{x)SuWaylb`avtqACR^CkYM-Z1q-h&^+0|)B*=DFTw(pyH{NCdzo4l^|Xv0Fd
zF3<1#Y4Ai$vKo7R5Fcir8Rfar4<sKnsQko(!A>4INAu?h+Bf!1wlbpt6?7_GJ7eE?
z&&15B?=yF9@tw8dR}`=Ac=G(!AN5(@p<O+;$7Z#ax=ghO((KG$k*skRdmW*s*XCqz
z3I)@c5AEfShQHu+ac6KKTl|DuO#mt9Kfu0U<Gi%cT_Js;3r8>i-8@mP1nG|#*GZ&9
ztNSeSD^z+_e#*5g*}m^tiW~?b)F@~1!SBp!If29N6gGbQNimy2m&md27HPolihB3&
zUnP-B=nvCM{JgYf)(V!6o_clsR-~PO+d#DuN+wbKOTu6LJBB7YL-@HdIOzvW8g$R<
z_4!Y_vNSgPMGH7_iYBXuB(?R`1avxIey`cL(DzVV{oK<u_4KOo;$vS=?B3gUvC(lg
z7s)N544~Oo!{!Q7|H3O>*j=({Cz{!1%s467NU}e&tFVn>$VztS(^PxPv!PMgkFbTi
z4l?`njJeMay25@SIk_%kL+4cZFcMkOJPRIs5Trkz0e8|Q%Z8QV<9zh#@pVy2T)=(2
zX1@E1$#roXJCBclX<bD$uFJe|$yUc+=A^c^c`z^#HxN}LO!!w&@29J=P?%AgT&9+7
zvk&KoY~nc`Dy=`n&t0DSBK3Ltk~QqF*;_Q)Cwj=Js#80F^_A_DT^=$ac`8i@4qR$(
z`ai(KA71OLxAne#v7y<96W}k3Ggn^Wn%#*+#R8>fC!KkKfp{x$|8@ka-PTWMN!}iC
z?#x8Gn?fBd_%p*d^p))nOc7m(BeA3r<eAgDAjM}<5fLq$16ef~Xxy<*W=Vx7Qo`yF
zQ|nR0EeCi+!pCa_QbsiKLAQxKVY2!Yu%eouVk2b34w(XH>vkpgh5)8$`n+hM0t;eV
zszmf~i)4fZ?&4`2`FN7r!3tC61ifBl9KQ%{nHqsJ)`;YGP>T4>f`fSl^#L-@W>b(!
z=1wJGub)riZR8HJO-dYd+msx{VkM2i6fHG^k6gJZ(`|KFtYjxoU@XqWv3?N<aj30T
zKtdh&?>1y>4Ob<{^pNE&iSjM@)sV_=dMR6+CQ6DKm8k_*1c}v3eo4hh7S>V{dRAaW
zYE^uC2f|4qi4LuD+lx_))zQR;@k<XiEiE<mzG667AkZ?NJliCtM@dyQgGbOYLb`5d
zj+le|1YQQ{YIbQ^?aIox5ooNm$)F-@Dw?=zzKyd2hc(8-U!2+9GWx+1-Tp9$#oKFc
zM4Qr|Svl>7kA$Mxm9vs&HK`8@j)K;J{;vZEx@))w3mXwAUx>sz`t+nk!*1)i$a=;9
zfMw&otkrE<hK-O!Ay)2<O{eidO~=zjCWJ?6JN$;oR^U&{bTU9KO6=qEFloYEw&o6-
z?hp|?`K8R_grZ3ZS8lQFBxaa8uYpqeq$a)={A^dCr)sCcU?zo(_v>*yEw~MrbLUbu
zdNyqi8MN4m@988#*p-~1z7Cct$)x<s*vX;nBX~(%zpYK<W11?9=<G%l!_^Mu5P|hW
z?AC-vrfC|PS3~psX81*iY&eS`4*Gzvn_kLpt5E0o1v#uWi_7<<VAIapi?gEGYuj(E
zYO6>*hzm^KLIDStQ*f|`dsE$thgivJ&6$J9>Wmxr*}*F~BuC*OysfT*7-kXy6EAB&
zXDQ5cNH{<G>f&$=+r$W}rvp10nY{q4JNcE3*kpR2H(X2maI;-`PS1pj{Zg+g3QkjI
zK2;%Ssrz5*VENAuLBULl4#em?owwx+b~9g#a?Muu2GnTBOq3danE9#yX*^_N;Z^+Z
z@VI(#-S$bGfq8#D7WX2~W}_}i1>SFEn(BJ^y4CY_h38}=?eA#0w}NicWg5#RGhKFD
z<Al(SPnlEWP5fxq_F0zN@`Zl6C^=C3^`u(~|6j&0tBNjR_JG63RWW-3XS2~EeX-yi
z=dCBK{nE_Y^E8v8{4@_t3!^W!l-*W8aT`i!>ufZh5q9(qAjaEOo=z(j0)(Bn<rD)D
zpQ<o+TjNrwjk29Kub6o3l3Y<+{o3{&dQdf25XxrY9v?_6>hH4Izdap?&{E>z2GUSS
z+qmUWC|6D_q)%-Bb!AeRv@qNCQ^^`<``hrLTz>erXvw)LY)gNWt<*2gh~Z`F*_6$7
zo)}D$#`z1C0F~Z<?Aq*lZOj(`BV7mtxa_iI#`(P?_P1=3jd@1y6ODo0GrW#8_F$R`
zrE$+y;Nh_O*Hki_#oa!+&#PYgLCY_^JaybEQoh#)oZa{P&Q(M(-$icU+GE*=E_D9=
zzuJ#d9UmJ50xPAq9$ksA(r^-*BEe;pq=X%}VG|svc7<0`$4|$Gy=pzyah(Y779eH|
zo)`6_D|<v68K?p+wh~=Zs-=>^C8c)H2k%H!f#Fgq)N5&vz{l~%{B}^b1PO=_4by!(
zPh1qcLK~XD_xFu(e14~&l-l}((8=CbzS^aC-M|b9k$P?nYM;C?IdSm&mL6LnCoVq^
ze|tL|zxI5a8h)*}>SH7IZfk%-SiCCsi(rrZ@Rk@0ap;4A;K6_G&2Nlit&-A^((Wa&
zwb$j3aO9{8-Q09BdPP!|Xug)ppEE>N5F_N&2o3nSeptCNOSJIlIgLpoFFJkUXq=B!
zXdWxEuT`Fy?Nv}YriU1t*bTNlm5KSEoQWtdR0_4)61%2;mfem#?u>pm#&2%8bIV3h
zx)8b(Yp8z~M(u687BkAmJPCf%+d&HqUg(jQS~Ib44kkAJ9!mG*4>B1KSz$L#GMi#F
zFTZQ^8mkNIM2e+MH+Kc;6nH<(ZvmoiHw**&L8hHB4X;u~iAo^}6q)?P7RGe2UH!wN
zV&K?Em)^LG!1JX77cKfs<p_8|sj={sRsG`X3$ae%el0PTS9L-QRcd|Nw)$pWEZ>ZE
zd=&x1>ykN28nQ_hV@uiBvdTS2z~cmVRMi$9nA;IE_CDrDPGM?Y*@W!oE@3Gqu4Umd
z&kU#3go<n(R@#B9k$Z9ZioK#5)0mSM38DQUisUV%UJ#3<s%4~f<i(Y$Tx@I7EWLvI
zf(OHou`5)nF*LopiP~KnxsyIC82<l>d;jRlj_S^LpL5T>eWaG#r`2j(HvUmks~gc6
zd@+VJU~oy6jc}ZB?U-P|z-`BI8bV$={4@zaN^02%FHaD}Nt#I}xpq3FF$`(4n7j@{
zCdbBPIXu5v9mXVtm#k5E4$m-w)gkckI0nDZx6Zw4wJqt&@BQ(%bnDcQUAuPes#8_F
zs!kPeujlE)X*_B;*oAy)Jnlv5xi|4#TES^}=jk$2q=cBN9F>G(D;Uu`yMvD13B660
zE4j&Ki&^B8!zQcoR`guo$S;Lt;4F-MC@h37o+uP3`e{bqdUJM#RR@1~A<bjvHmk9~
zDCbuoh5}<wY9MR382T!0)+{*e-CPyvoj3%1pj%lsG|BtwjGe;uSnsNw*+}h_{{}X%
zFa*h%ur2m_Ab#}&hP+5Qet{o_?`V2tt5PV!{cyb~4@Z{f8Ggy$4<web(8FqXEzk{m
z1CX;Z8tejPI~$2M!V+9%o^-0skw}v9SwN;X&ZlktfEJUPd9s`HiH9GH=t`>MICw_q
zs@#srQ47=LFSd*kO~snBlJ`7bzCF>07P@t=r8Am>KztDbCImx1cK{nNb@%1(&svNw
zBk*%FP6JoD=KN{CeH<}ci1ai-WCC9aIogHC7Y&sZq7OA+@lsd0WZodT^##9z(Mz}M
zqs?cs*4L%treo2F04qJxruYv%GV)#rLT<MyC_$UhOL>AgA--Kc4N0KjBI~8-b(c4=
zR8X_|o^|D!;{{FgJs(}yJ{s4|9i&l=T)xC}vKPMo^R&#Cv6@s~sp%tAMGQmbf2Upo
z(U4^WNRn}(eWZ(09+E}J+(pH*74|xLRKOvnAw80$33oHv2n(~jT3G6zsb`FqT>R{G
zV3xIzeh`GP%>5WVrexOy6VWE^vTV|pr+l)!%`r$LJ0x;QtF75df*;<NS?Ap#>ikfE
zqe92B9DRDh?>zmCVTC>oxU{)}E;_sL&sn~G=H;hmwf5D0$7`86Omjk!TPjdw7u~A(
zVd(Bx<P*umJMr|%oG>ZCn^J#1i%>pQuLpFB-L^E44f>fpWrg}g%1*5Q!cfdy73nXV
zc`U(fJjz7=s)CEd-!$qRweY)tVdk*Jyz^Wi=DizZ=bk=c4H|7lJq4z9J4aM3|CP(A
zsF3FQN&P7HJ?`y}@|6*lyQIz<Ws`7qxrAjONZs2X+YRO>K<j)ktwYNB=qAbuhEcH;
zP}JW~h&GV2`pb<3D6)@bR(dYZU=v`{o;lmJeVGF+8NpdvjQs35u78@Is!ta3?GJgo
z|JHhxPaxVgi)UH=o}H)_fyUSN*h2gJXEPcmh*w74g|!~IoIQVKvS_tIKO%ulfoth`
zMcxXHbRG{o?*;T^4<W_+kjwISBuSYZ3MMLjVTfL)v4f!rC3x2i?|fBq)eC#)+r3RK
zGct$wI91e_TmXZ(akp-qL~z|GKY8KInDoc;qc4U{78e!Jlq6sOizLEx0`dDpUp%+t
z&U<IRSF5cV8fCKY(M@C|P@rPD{KqXeaNA^X%s}8q20fjW)z)F{%x-^^z5dckr9Un|
z`YdJ*F7Q&?K}M=0Hw~NnO(c2uU}hel4T1F-7L3iG_pN+_$pjd#(C_)DdRqJgBeBVH
z#;y?m2j7$oxb2Iv&M~r0ZR__~d|wJo0jKqeI19}XFH3j-v9T^#%|ga}w*oUeKVsH1
zn@rQYe_XpyHMc+HFrU06ZCpd&aNh&Ble1NETJL4Zev%Bg<AIE;Le{gkssN|e*3-Z}
zkM>;+@r||VXGMJ$K~^}Nzgs1GE5XOl${YSaV?l4zL7o%g-E*fATGK(Ys*aP{?1h{`
zy*Km8t>g=Ug42_UMVFQuh}>)mcLfuA0eL%;czgI2Xg)8DNG_WGHM}^*Ci*YinY5(>
zA2PnWxb2ahQR3uj(5~do{oSPH+FW53@&>Ml>3{98SKUL#^MyS|JqxoM&h>^z$T{z%
z`Is=EVl`RZy?mSVU$WsWzdFt5KNwe~<lhH0`#p~$;dip%?w(Ao!D>ior0dHh;#T|i
zwIk!+0!G9Qlv~v+pcLX$eVY=4#w+<pJLAb%Jh5_BS|BA8gEnhu#Gx4aktTl~p4EMu
zj3dd(M=7uj4jld(rgHGWAJ8~g0ymcgytwyr!KrWT1MUGSN6h{t&g_ek#EvMd*mlIo
z6xx<oVM7AIihN~}P>ytW)uK{|?Sos*hXaIU!tFvrw_kLcC~I&(c1h2>&odAnZ_$(G
zbO`2_jG7i<g`v}Np5k&{?nhVo2kdQ|rBw))FoG8f;_bpjPfyMp_`KNi$&fThX0X>i
zc&%C|jCE1_J`xt(PC!~xiHuB|b8_%DSE6#}u~MiVEC=+SwB-gOKF{J#p*B~QKnz~f
z;9YaNpOj$(r+-!&9dwQ`Ga8FHt8Q8(Zo|S2pvKbnnH|a~JioW*B3W@5=Nxdx721kd
zd5XUe%NKqkNjx_Ld`?@phNA?9Ju|U7jz@bGtu`4Awka5u?i@SSieRrYi1SE-k6z=`
z!)T(=(!A%<m8+^li6*CB3OS%GfY%=&6u{DTo2P-sre3lq+1)Xu<}FfGLbXPz0?gb(
z;$k4ij4V3hE1m9nt@{jvUh-jnKe*vWMc1+l{XtR<SaSz!ZL47=$=+C5164kJqSE0X
zi_3BMke?N<zO2SKg7AxTEtsRN9`lL>R5w-1wjKn=4x0DzYamS0J~{CtPRG|kSi{So
z@=Ilv2z}M?c0+tNCYw0#N+4KWJ|tIxj&BtEF>{ehFXS0LdHL0I0i#N&C#qsfF3D98
z_$gsE{}EI%3MJ~r!p0E1RdvO(U^J2+CZ3YvH%Har3kg2zx|*`nAV?6$!qJ9LZTl#%
z4Pz$A01hVbO{Pg&Zb6MLtv5*YjNcFmjlByopdW7`BFv>iRwH;i+)D--bkxJ%%0Hr=
zj`9>2RgN!SfQw-Q$eTN|D9{&9F>K+I+RhELoRv<=Hfu{GtQ;ok*AYP2lBV06J7AiL
z@OTMoTy4E9v%%$V0f^eVK(fi<0h+0c^BcIigL}^C;wZG_g}!N114X0r#%c%C@PXGx
zBD9;Z(7MQc=iS?F@N-*eB!=vgbSG>wunVZI5pP4IO=9*Y-ql4*>|w^RVDl@sw|7|D
z8aA$1PaIQ6EW(K&|MI+OoFseKpIsc7d&L0jpK4gAW1~gXV!UHJS$Mru=LiF19k~2K
zQv8fI6wkjI)Uer})e+t6DBqLgr(PG)6nyO~Op%r!qO;g*ZHI^W-Vi)VJ62l@76>D^
zI+aJ2LAnLk&D-L0&kS+7FK!^!s@Y3VZXaAMx6tSvu6c(>`MQ07JDwdzAsIpG9CjyT
z0d1HnRmo6_DJis#gr%qy>P?M!l<e5z_N8#>f<fjQ%s<lEqKUlt-N<bDTU&;$@vF`b
zp4gq#_iytvhkw=5*MFZiq)n-<8M+4=)a$nYVC!sIoYA@z`E=l9`m?)cY@FnZ2Qq(K
zI^qKS6z%jf8!sLkptN5Z?BNf3YX|aH=N2WEq7Sfj^#xge&VS9+lTjC5U>*0PLq7d)
zA7QWdlb+sbizXcV7lX}&A*;QacIvVDFb}O$Q4rGN+gW8ewk6osW}GlzX~=}QE*yIy
zv%33H?vd%RtI(u@#<#Y&+UmHQv7=JRDTQWST-2;V`N@mJ=#B49X0Dz~r|m;8LNecs
zgNb!hTM3AZs#Fgxs!9b`Ep1ERrhjTHS+A*ygPkPaz!HzLS$=fum@e?hTA!|65uh~m
z;!klN<(Fw2KQ)wUn6fc=%UEp<cKEGq)3@4n_My=z!{(9X{_QVeYwqm3DXwIk@1>S&
zi(yRnb<pPfP+L-SJaBE`EjV~#wS&c>wn`v{mS{Z*`)!x;egql=w%^;38y|Tjdv<tE
zU#`S6lPq&DVb}8Lfx&7*h~&&sxPhmCU7n_2^H{HmL%36APT-p0@hv}&adJy5p;cP}
zn(_*k*+_`ZclX1vdZ81%9#Y_~{Kgx@oWfFk)b3$3!@)DgXhy3RNeCMQZ6`-Efy4X&
zw1RTd?sY87iBF=o{KNFN_yKLCbp%PmS!S>3Cek^}-#dSf&+X_X>eBi^Mpsy}&)F73
zCoI>3*%{ii>HOa^bp5@7@F(RL40Sc7i};RhAH9c(7(w{9uSOF#PbarH9J(bH+ERjR
zz2)b^H|8hZy}<^j#^$$%tNA?hkd17rR8_9Y?+#eaeuwl<!lA&MMB>{tYJ-ruwxB_f
z|1*IZNrf?D1Vrqk#W!qzbuneZDMZNuj=G$?YmK&8!yRfnQVQLu70SBi2(QJ6C@J1_
zRj5LyN1`p3Aqf29>5+1HxJnXQzj^HPFvplAS}>ALsI4V0-3+)L4Z+}96o@H{z(tcH
zOz7q5Cpla~J~dEal?Y`^t!-qH*!m1gO0bU}x(*3>ct`x4nG=V`62OM+N&?Zjh7qD4
zu`N{A=&lSr9JY{^8k#;cU~ug{QKnW!i^Eds6<sJYwJ|ufI?PiqR<rsdl$QvfX=c~j
zy}c3yZV1Y2NX<zk)r=}`$V50SdByBBe4Y$<ed&KJHXY~23WejrZVhW=?_ptG4`vDm
zWYiO~K=)Y8%^)zPli64|wiiJLxAej<;9O-f7a~H}V(BO{f^|j8Y{LAKTtOa{vgK2U
ztwl_&*H)_ICN$VAgEM$h<f`7tvI0k99gOv6#jl@*dN~waaNw!JNO;XEOLiWP)_zi}
z;|c!}#)TEZRXI8yPyF>`_-Q(*%R+^+o*4)@N*`2VL%OTnth2NEsve!*9$AkElE~8<
zuQ06DvYw9F!(8jhZUM9V`LUgsyE2fV<5%;%kPKe=DUZ&Ua1V@V%m&1;5yY~PIEQ;~
zLca2Ds@Tb`SB|Ol0wz1+vocmBwaRZDtG*id$kV~VY7!B>ODB!3#ySMn@($rCzPe`D
z@C@5m(#U!!%0&bUyI#r`eNubw67vxS-Bn*$A=>Go-hfyTmFu}<Yp{~!D*03xp~6dN
zs7NA~`xV?OWDRq{sfC%K<__$_ay`FLXY?9hEFAQ!6tnj|COm!>c$AOOwN|-r+OY!P
z_#(vDtIMIcOzTlf$X0a`Roo3sPZ*q;y^>z0n-$1w9`$4z^7bCfT-)e_fK|efb8VPN
zye+@fC3dS{L2x&HG^R1tIp68q)`cqM0v60VX?1o?)}#>ZyrKx5^nSi}_3YoJ8TNBk
z8LyC9+j8>&CkgAGY)5$Ls;yE%57w8rTY?%LrB@}QP4g#($J(y@#@#lE%3G0r%@kz>
zA5vRIX+sF;3TWP=_IQ0fvzK#SG34}rtZqZ7tycf(gqHMR(Lik_z(<nAg2C_s9G_Q?
z9X%?L9jmoaf|GeU1fs^craqr^F1FV(n74#k`<RPP4BFVpz4`%i=@y2kPNBk(j%4Dx
zz?q90?Id!v70-T<w?78kU)-C<b837S{SzO6KL1OHE?|)VjwHkYJ~B;@eRsGFV0o!_
z_WBE4R-BwReYNPez0W##e|HO|wF!_?oXw%CQ9wr`EeeQlTUl-8vkl#4sgm=Dw`Pn!
zl{asPS>)|}f<bUpd6l;te%@05F2*FEILn#GV`Fd^4eRsV8}9K|j_>grAVS;u!!+?s
zCVJFX3x+TJST<g4FAIY2g6P$Mdii|jzMB-2wIP2VoaO%T#gs7T5`#h{I3yl2+fAFp
zrIM2e>sH#?vr1r7knVbwA9&VdJJQ8sCzU3~$s=LZ)~NL4TMiP4eN*(BxA5)3XF065
zVylXS{-`z0Fi&ymQ_kGUpB>qGJfvuuYJ0Gi)I;qImma2`p_^xMt#sexc@SzpNY8!@
zX_Tl@(oR`zjgu>g$)V5Y91-Pn)aXFr$15Qj;ZTuCHf-7HIY*hX8=TcHx+%-tml566
zkiTmabvSqw&B+7rP0fEYE%qRCN&S)fSg60GW{v!&+<T30sW*jfKb#Ey)dv&*lNY3+
z)?gy0S*C9OzKm|1c<zyb<hH4cI{D;sSJKlcGp&267*q63mpxLri8B*dh%1$RKL~$!
zGgIX6V;J~AO&>f8N*UgtQ*`ti^BVXRa#fKlXhV1*q0KI#9%8#;i)f(CAHo?;rQRH{
zG|bg(A&GFvZ`w|dUzl^$nZ5nCdxlDBls<V2jgLb60vEAXi@c1RSZ$30hC)t5>=?yt
zua!d_bwZs>%UT@e=nGONm@X!3m$CT5mmXY1VEGr%N#_UsIa7TT1YuEXYt3Klj@S_g
zF|Fp>;9QzG`@Ij_Ncl;Ixp^b2(d~Ew`M&nTY^T)c%s2_gLNRV_i}7;1K4G!>%=~I9
zr%=I};BLsh7C07+$>3lea#NM)CJLfpxtCN}Q%=57rCkw?Rc221z|V`4>tJjWCaQu1
zyT^n25rcKytw^LPv(;0H)eun>Su>&WqGVGy%COXvss@{V!A06O?&>iUp<8j#1&K<a
zw@Y|&NxsS>^<RukwGmWN;?Qs>=8>mH(Xay({U8vDUppb{z=Bmkyxe2;*J1G6axG6u
z5-rD^OX0|I+6$R2J$^kw(UO4!xM&ibZ=W~Mw$wO=>j+U4U~Ig?Sl?vd4}=$?HA{qa
zW;JF^j|L>*S=ZRSgrUtrEW*=KbC<v(Ma10PDM*9(j9O*G`%crm8qc{xTSL7<su|@|
z5!SPL=mY|N7a^7j{D!RNlINgCD;?`Jf(xm+3ae6EXSfpB@(^=NTTC395gh>-W5~5G
z1jnRmpfsFNdc`Wcmyz+vWT9l@_;@?HO#;VFIg*~lQ;AfcYmNv7O5nGhc<}lam9B%8
znVq8HtAym-7}z^-DHs8K8u2_^l@+g;fuAR_7%+olQy{h;tmIVTH(5lVla=ha%4=l<
zGArNUGeGduD)kCP!IAv{Ls#<a2O)qld4?rXTfG{`T=lxe;+-bhd>l`d(g<gGIglg;
zXqgf*Qlvt4vj`s#;MWHd$7Di;e6bNZuues4Om6{e`Z6u3RL#-E>yf~VnCgmWD9lw>
zBEF9HX_lZ0gaEtr%oIUeel;htP$)4|(Yl`D;Y>BT6B;QsX%!k|y_l&$1m}8=e$SXX
zL{|aCae01XGeT?<v0W=4e%-C=*qqu(fP&s6IN^DObx;;%J4<3A;@7R5-Be6daE{V<
z3IWEWITB49TH={bqFpl^*bj2or8&e1(4`T*8*8$PJ26i>Pb-8{X>V_(798klOo?NK
zRgOtnMU3XIo5@O>?frv?E8^x?g>GbZlBYn8v5#vkm0RYQ*`pA)B$K_>*8Uk)EQTI!
z?zxe*2hQGtm2aEI&>xx7*K`a+7n#Yojr#l{Y<thea*ktfTE;+pOUT0ipmdk(*3A+q
z8$hyLPa4agk4v>)Gv>S@iG3k+8l;UeN@1VvyeS|nUITL{p+(*-{2Gqs+lVscS@3Yf
z_Gz(x#|BBQ4q~6PW!vU$!Y+0y7RN6?ewG_#G=F_EXGhNP2ibpuZ?k*@=F!`^a_uMB
zDRpmcl7VVHDKE#Dc%vPLjzOQ__P{k+ds5@Gc(sqqAj3~=bun;{==Fip?FhlXmM(Gf
zggXtl_@@-rZj0AytN7)9k<-H0b}*JtwZ23}v0m+(`1Sv?V7nhm630icb*VI7kyT!o
z{Ndni)JvwnTx(vd_1Cz!6OGcgJ=ddj>h{`AfL7wdmj;)V?99~i4o9r}(REVz$tUK{
zOxR~jvdf1o|H_*kYU@C}SY>3}TW9BYpG*SERv5kE#zd<xO#AH{or~;koU+qK+s?7S
zNniEgZ#_FIn$y&rM`w4qbngI%N_=dWEzyYjt08m$-(0xen*U5G{dkLAGW0S><xjlb
zeP*IlLR|Z=4(0BPJ40+~f|4Dg-@b`lvD}h&2A)X$%>TVLskZqkcw;E+H(q7uHBa1c
z3rkyKTd49AWcmMyQ}w>L*VaYvK1Q5{F5hzDNL<10MhWEpgs6sZU(8?^#d19IOW~jQ
zP9_hQYpAV1sFQ;;ISPd<ai#-B{zq@D%6L=78mWsnu-iJ#+Vi%ew#I9cR`gj4Uj=A-
zv;6)qf20~H-|%>&QhDFz=wLr;iT%tQ60Ch8h~Z@PJ$ytK(jpEKh~s{DY$CiIWi-FZ
z+8kG$#TEW^>|$NtO}e2roPPWAY~+%1oKM2fzRTDMp1DW11{?cjHn#LC{q3V6Id+qy
zn!MW5nakX$`^KDFpb$0kKD=>L^FC?@w5C4wthBf1leoc!o%v*pjlQH8%k?3p;85Z4
z8P-`PV}l;FW0Q!h7_f%)w)9pwEGbR@Z^K=+^#K;1<Re9P;ht@Lbu=_l*Zy6}V$(pW
zLirY%45xJ@leFb!D!r0r88+|DA6mF$yT=RomakBn*h{GdN0s0HQ0#=^q42uY(vwaV
zN-_%e%`^<M*m-yPt>O@k4&LIYgA9On_%_);@k%~f3yAgic$ZiuM{O;fb(AcpHVMzJ
z=bNGO&Wx9R&Y9y?uzyi5HV59gVY-?V2)!6SRb5BqQ_++maX%AC-OB5;IvTnK0Zh15
zg|&b+LcuI|2vjO3XU4DgpoTUG$zf~`Vo@mP0oI`rcwZFLPgD(%=lg}~W_l+q@)TnP
ztc=5nl~l>c#h*kCXFmu+K;~Z0)wQq0=|#Oo5l(4L<ZyVNg1FQZaL<w~=~|nb7-|m3
zOv5@oO4U3aC=H__!#Ct5&uRmmEd9Y7OkB|&4n`^~aau4F`GLj0P;owL<5OOYoC0M)
zaLAVy6N@e%lIDbLCA{Yay4F%4Ezgsw?mTk}+YIz7QJZW;2$(7+y&|*G2P5u8rb<;v
zLyTT!OKLu#zw2W9e7IMCr@Ixd7j@02b2d!va49@5^)OH`6X{J0-IpWHJTpq!i&lxl
zv9q$irRFUkwYq}`2Z~>m5<Cg1ULJA@4U|R1gEW+t2t8T$+-pC#(cheY0)MwW(v-Df
zAL~=~3auS~mG5(~&+zk}SSgaJDvGq5JdWzTJ|fUdseq13e#Cj3j4Q;c6C;}Pnx*?_
z8xF>%)rJDFH-P8x)}LD(<{b@LNYk^}+}1=q=4&Zm7xBt?hy}jvXQNP1vdpi*gLANw
zkXc>?PMXA5oXO#__k|@Q2Vv1ridNDaQmT$r0T4n6PDX{wk`xs{9V8aoSHgf41j*b-
zM@kHDX^;cT6~76VF3N%eHiRWY{S=1ko8uYyb-^dl9CUGhZ?%6fe2pig`XF!0%sW`B
zCC-iFZjk_5cRr+m4&0}Fz0ClyC_U+BsiSt+!J7=;e1Z&8?-eNvDZYK7)Xo@S1k)K&
zAS!?m0SI}-Gi<SO3KK7clY049c>_g-nStBk7voBP{lTfOCaG6ygZyAP!b(o$iW#UE
zT6rkQ8$K24V8ybMb^OS_w+93J$@J}pP%7rJ+)O=iJWY`!XNt5TJj!ek2)=QV7>KoM
z1;1pEL+tMl;uU(0(@OAKmQsj;;(*k$c;WLk;i)@?g60Sn1cRD_-$zdPOJgGVX?wHv
zd~{nkkwmL6ly-{xaz#DHiHwUv#SeZYlJB#;T_)aYydz9L7a@>L#tKu@_2Ne1MG_ks
zjD<KR0EUerQ)E{~AsUtVy&M`aCGt4{7hcGGy-qETd8=~g@SrJ|0AltvHD1_?)Gvd*
zw!%b(;q4~ie~CB=xzydr6|JX6+k{+uQPd6p{{hb=*>p97%A1o%k3uPjpemutzK&V#
z#%U576kP-VHa~&7!IgkhJ^@s@GS@{_ys9u^>$FI#)Cf?#${RS1d3mf2oFYs>%tDW|
zwGlVx+v=gMy!Z1xwtY`@N-R`qMl0<YK8|0skV$1ClV|h|vTOoGtYDDgg-dTIX+<G!
z58^=u7$G(nJx6X{g9phgU{blCDf9%bv4Rhg%6cT+ssQg-IfCr!pjW`J*#19SAhd9b
z1g_94ZEY(kD!HFRSjWbOV^7SWR_Xc>)LUgj9YkO)1kZSe&l|I%>c;BGWD?4;7w=@m
z+37Sf9I8$zCx}SNI%%!)riW<Z3}RL4V5b{abz@c!;{=R&vkpJ2!_p)czXL}^!9iRN
zTRg2ZAV*)&?1H|`avI%eq$h>}Tx61*(7sm#pOA9IY6@z{<`i6^I>m~84}}~fWhCol
z6}8N)q9+05nMbnFKxF-)3Ch)x78XSpEx<)nhWbYBUk02I`a%%KL`17cGa5dUAh{z>
zZY3j{duwGkNg5q7<4MMIT9{z5C>tJGZ4$U{Q;ak7^VA3g%tk-HwJ)MYIXQ=4DOW=V
zKmo<4dz<Vk?>^u?2=Ld*&h6#`_oS*P5EJrP)WNyk9+^zaU*Kgl$`0n9fDw;lNcJP>
zI%~I0jWPk%Fb8?&qQoybdnT|1vOg_CWUEU?`vkQfyJ-l*?CtnE6{`}b&7aD@!W<I;
z3*xzB<&-=E)m3F~6POOh#^mS=F^aG<HaN`lRGYX8rlZ|qcKN_UvJ>(~a6NDyTLQ7G
z;G;i?>XNF!jD<X`;D?+mc9oDjkujDlhpO6RsRM<!C}(YMBJH7zhrrJ{BF(}S|6~Kc
zpiqjtior{xJn-KXh)6Ti4dL_%?XAJHX@I$ou~YTzbd;yLXf<KZp0C`l0?vym!f(U=
zFYebuPR=D4aITGsOL|o_UAFwvbg$h?PL6F|YS{(k>j*>h6WhvFWY)EYD&#UGkxcn&
znh>v({KDCY_SX<13rksf4S~1V6dMys-~#0J5TzJi+b!(#I5P7X)5GcH;I%~E1l&4c
zBTMOUtMz0o4V6H#%(sjFRkoP!tJ?^N1kW^%9@Yj7Nt!n5#D!e6baZQ(-O40s`|{rQ
zTED=O&p?t+Gq_%QUzTu0Og4EQ((ymRbv&Tj;;fsCBsOD&{fV<<)6V?w=2gPo*2h2i
z+}vMxVV2w)<`Mhmz=!K8){$SHld{n1=7cpFTE>#e&tJdPhT|?j?$(GK6PF*Y?S2Cv
z$rW?Eo`-(J%yik@g)YcB9?d82314QzAp5lXLJ@?LeSpo^4<rlqxicv=1k6z`agu)<
zi+_7`dMT6qIyaMDel-NlQ8d+R5g*|YVWj<2hs^#QTmB72-vmU4Pu6VuiV-w%BIq~v
zdYgL{?dUZHefQvKk{|o)Z8oszXUtPb_Pxvf@V<XevoQG~a6S;s5l74aBl&w3es1m$
zvBuGQfGYVg<Lf&od6CcD%A7s@lwMpO{bAI%tvpUq?qM=nT=k&&hXc0wY)&)#@VCu-
z(h$jhP?Yz+-t?i{K>U7<&3r1_xG1q)Niqg3sf@Ld<8EciQ{`4pZ<(olPU4jK&$~50
zvi!MM_e-$~S2^i|%%+l!)Ga94Wd(3t53AM$JUCS)>vT4%?q=k2O-p7YXV59`sfD?j
zlrR1Et`@}l95l#6`)*6hk3H|=aO8FGOr)SL9DA|ZH<A7BMO+E1CG2VR#XtYVxZV1-
zgdGCgSeo?p$@@55!>6|vj32EPjJKij*-j^JQ6&5M=vyh{JEph~<3(xs*ppY-;$!ej
zor~gHpQmof&@P&S8)0DV)fz{xz@UFk^4BSSzz)CDPvad{f;O-e_U)84w&zV~<Mo6Z
zz6d%~<s`O%SP8InIq~{_ZRm;{#i-zOyX@NT8Vhe~jWO%51y-};Y(_-b$f&-!>r!t*
zUHKoRap$xt;t^1fmmGcWSu;vj-_tR}MIz;&=Od{&6IQa9!q`=(;cEL$44AZ>fTYv>
z3R<&|6q!FS_SN}lI(O}@dl2Ox)xMgJi!x$JJD}Rbx51e5X5NK-yp!8jhyctHUvlm8
zD_Fh1g~2%4&;4D+&hSD4C+lEej#Qr<i>N~H55?pd_cU=lkJIeOX&@?^Q0+p1^d=xB
z8rzdJdjwFfp&MzeJ<uJHI<gr(394FtIWzUjG+t?kC)syS&uGZf2U04%XNcidH>Z1p
zfq+Kf6fjS80w(lU;EYg7iTqWT=&#@xv9)iaLfP0%V{nL?Z{Dgjg~-Nk*ginkEw%GR
zTwB4K9*f3l%9GRMinJmiyNQ1ds8+zubg&0davvYK9KTIM;Xu@>>5=ZKNNKPHlDRVa
z3?MkWiCxy@qXN3OkaR_dT$v?vtOQ0$ItxfR$nzdnGG<Gaal`Y)HcR+0l#Nn}SLIxY
z>j0@(n=n4xtfn{2NMuRa-nFT-XA!_!NRq|`rT#Ha^dX_3c||9Lh~IR4mW=PZUeUdt
zv7<B>!=|eBaWbP;m%>}HxO5sDjcR8a)!a%3KqD-w9Nv}Kj3Tz$y=0g!p1)tkri{2)
z1BC#zRn#@7!WmeIZAcRR`x!2zpzM<<vsJjQr^ViE`HF*b6{S<w<|%8}R`c6qSxdH)
zZRLv<pcF6vaY{6A#H!WB-RPk#Je@k8NHRjeBu7IU%0-*ng*YGXNCaU=Umu@sPJ4J-
z?qkU5hHuMVa~*9lboW(ny>jmmf5Hf9mTHPj$s46J+Z4?qYIHaYi#19%ddebDU6_?c
z8G%ILF&4RM+D~IQ$8S>yfC;$*^<N>kg`T@2a>})7TZouZB2{7aiCGFu8Hvy)Vo=$L
zk(L^y_A}um5Nl1)Ceol(^v0YH6_*_qh2XHno6$~d?x;UZgW|<vw{%8a6(@^s5lxfe
zt%K#bx*gFB6nIPyBTk^foFKSs(@3py8ucOIu3e8iRC8V>9?t+sKoLUxTv`?-*kag{
zTlly~`y)Mpi)J6A4f_$6cYBqumoy)WK7r8^IbKds>XgbYsoQz{EY(d&mqSiF6219i
zVV1AZEc^OS%MLy-iU5p_!L|1kGszb!BqbZ+<an_+Yzc9YHnhB(G+&)BrniKa_SSUb
zm5?Xl<KXjVkRp&TEW8D^wPoqurtxVX2vUI`O5Vz+JKCpn+wv|dh1XEcbEzDKeI2{+
z@0+r$9O9*UI0s+XM%^{m;@RN<g}@xr_ENq;+SKtk9Dk6-T|f5Y%q~G~_5Qc_^YQFd
z+GaM8pv^+#i<T|zqFeqCW8GLjMny9S+E<qqkL5NeuT2njp~(<Ih}sBP2`g?A%L0D-
zq>2j=#;SqCz&m_<d3IOa*yYpx&yRc4vhwKdHg*4bVdy0%lZEAv-o8$A4z<;=hzfyv
zl(d}$OUeRtoidbX@@3O2iVpm^=I-<JbnqQC^UFJU1ujfm+^w;A|3|fV0ep9~Zpj;Y
zd#Xc9BaID>N$q89mmgvwjZ-~Fzf&Red0Y781QQ*z4d>$lf#@se=I=)F6mwg5+OVoj
zIR0!)hnyRBq>S3?q>p)|?xB|2u_v=MJPO{Cal#*{)7TG9u+estFnI+X;W6$FWEVJl
z6i$I=4V?DX#fu<L`EO(kY1~6dWyptNCV-pr>#42omFTnx+t1+{q_!SBvEAb4)3455
zWnPEv9Be&@0o<Uu0Ynz5f!i0PoeoPojRGsBMln=?!t`>@T3dF8?k-gVVgV9-><=!^
z;)J(QRDa9nf10wT4<~l)({J}neUr4Qq5;Ei|HF{PEL?QpZPLKq;!Q*2#UtzoZyU{B
zGL#RN^JluwjH3oT`B9r>ED<-@l;41v^jDVjwH|s+y~rE?ve4Fs%uEXPga5{<H@^V4
zpSWCV?Q<-AeoGpe@6Q?U(>1@ySR=k!*C78>QD`G^mo?^@X<#-FCqZpDR52sCXo`XY
z4*nD=Tvjnx-4*#A)v8+X_V=$eUk>pO{SdsxOR^b`J2?^~MG6}mQEi<FTg(YBTSm~l
z7f?8!#bhbK?*2nZwU1EP(w+)kiR^4Q!qD7aI@R$p8c6Nk?gtLF6^4OlwaJ2KkUOnW
zSe|my^sO`iVShT8(zMRn=MEW3<!SOkDiE)BCFUP3OfbVA3Iw8ZPOn?Ozy`D-Q(c5R
z_N;LWzmqbVaa+QQNMc)W+)@y>N$AuWwm~a9`WsJ+F#$nA#YSaTKI@qpe6^}~W;Kdq
zS*ikFUf&C88Ny5OS@7d^Tc`#a)qbFhL<Lb;Pr>cQS@#K<F0@f0sEnlJ3uT}KKL{jP
zl35z?upaK198G?KpT8e`hlMn4A(odM8vsO|%`+$poJwzP%}xNR-JV_)V+EP)vg7@G
zpxcf}{fY@Fh`qHHWK@Sevl-MTx;{L-_f&$&I1EP8Qgy;9jP-40H)x6{6jlQg7}K_s
z71&I%f*fN^BAU~n$Se<UBNYBn+`EuAd>&+{2S{AWD!6NSA3YGRCq*YmU+_>(X#guk
zF^b2c9w@$UzhnVJVbq+%vx25&bJ524Yr$1~>lsTuHj}ci58keP0RE^V>4dhhK*4pf
zL-h>FyF}J$`wqnfOEzZPZKyg@fgx(=piKn6){BYz63MU<oSLhso$5%5>Cwk}ivr+p
z2Chhbt}okjB@n^Mba^~_9slUp-*7?+s{hqX0f%x5LNuG0_(h=`yfO^vT@laup%ZN@
zyw#liHAzaW#%2>2)n4<8wVO<|RSCsphrn@_XEfU~lSa@(k_&P5K5a8y)Q(;o8L68V
z5^<RSR!dMpJ`}E`-KiG;J^TmB?-Esjq}Hx*w7#CIoL^wmKEW@RAc0g(t2+u%c#a=)
zQ<iqH1+)@t4&k*Kn1-8Fh^kMgpzCs#PdF8@37gm)9`7N#uB9t;f4#EbON>Bg@*r=1
znrAwXp<e}#$7btPH_AE>UepMFEpo2ajTI1MkStTz_1WN&v1S>em4&KhxgOcaym|b|
zV{?k)@Q{m{kjCUwLUavM7T2S}%e~}9vW^xxo6w6T7Cr0zGc-RA`vM{guCUO-aax6q
z?xz`n_8YWP0e8#jf)Zk+IE}$VXm)ROZp!FL=QI02MS($47H~Ems`68WcRP+XPkeRh
zhEA_@SGhQqVx5<7AF}W83DPl5&%cSXmbR=f+BOC42Euq@h051@xsv6>yXhiq$(&tQ
zG&5$~vv3&E-ZC#iTP=LtIi6<jjEq)6P){6ctG9IQ;mTt}^R9F4Rw#AS`MmW5&USvh
zL1B0+HHF08>u0gr>I&3WTO19!y`S73-NFHH<TpIdqDm_g7b~zp$u{}GF0pU#7`(#o
zw8i;BL_qWD!d{9<OAtq|j;KDG{fsb6y<)+Dg=<yRQ{ZnvFJ>WhsrV{<obunm1|wkv
z27dk0G;!cbJrc0mS_YmI+a707@=$%A^-y?zA16J0yJl^bKsdy<$Me2#wtT~(v>i1S
zv}LW8uJw8mVHGG@o#wIdXUrzcznkoiZ<-f{BWO}u@5<*sbs^{Cy(3oUsM7EXa6Q3a
zGs1+1wT<cAxZ28hk}Pj-45i~DllP^lMO%v6p`COa_hbpL)Z{;oChowfwSBQ8G*VIs
ze|=%H{cFEmPnUlT)xpoRaQI|y$DT96OyYs;Zbv#ks;%#JP5%V%>pkb9A1+L#;S65u
zt3EYu?ZNF?bBg&IgwbCf9)brZ%yFho>ZJlJmt8>oRPX!HOcuYbU1ysB-jMdxEfi8$
ze~jN55^t%ew(5}5n8pIW4@ybZ9Dz!q5k7iWrc-9^lJAej)z)nCTb4Z9`N{t2lB}10
zoBRO^o^qfv7D#O+AV??GGHkoI$m^YgyDRFp+~HGLRjr@loeCVuw7_a>Qy3e<QJ-fz
zImRuI+5DA5({}jRct@GA*J|rK`INvdCi7OG^x;0#R{v>M)+oo&r1e#MTl%lP)^>d5
z{GutAIXIuHb*Z^a9y*(^xX<UrhxcqZe+yfF?zub}`j!7ntF2qq8q-p5$QFT<7Q)+p
z%Gsr_NwQeQSJedFr4y`OOKLO;5xTwOhD5W58p2SC)vC|byiOab)K&sQH@?>npZG1V
zv@~wpNM`kEvH7pSH?7BK?Lu18ufy0TAfS4>`pnxZ<RRKy0cvYZcCxKDwp!%H!UPK@
zJs-(Nl&{ZK@torT@DFk0n{S8s)<?AU3@(qVD+|8W2&0VcI`**ldYMLV57!>NDhcTy
zr6UYGx#0bCwdtwlUn+DaD0>?V=OWFS#AT04GWfzk+Ooa8Tz^R^A5D{8tv4p=-0w6R
zE~|6g+RHfO>dD;^SEH)Fu!p|HlGmi+tSH>m@M%(F?T?!1X(1arW_iJT2zm*SV(8Lg
z-A!fb<jXu#si)Ukm18=H5^RAPA+FmM_oX&gx%-)wvTIj%@v>yHO5{YBLI~ZEj#M^j
zvj{Sx_*OSWK8!&l6vJIhFKn&nAf7G{3_h~dCMT7XBwhvLBjI)xM+a$j#i-XZs3J^N
zLDAdKR1R*|iV&jd+R$#wO0#a7q+u;O$Zb)i(YAr%2qU@V1!R=Wt^%4ixlZ?775;Rq
zue{QBFNj$(2YF@8WfEH#e9tmXs<R}&#IIuaBV1!Jg=>b9eTvdayVwsrf~6&yY?Fex
z?WPm3=19b>4e{-aZn0_w!|{i$*{yvk)9}-bJHvo2<4^QuNu)1i_H*}vG)FNlO%R=T
ze`Em<F|5`Bmb#}za{rbGEAqwi=TNE{tYRpn&6}{q3>NewrTEe<4sZte5Fc=j#fhVN
zRM*V_2`Mcqn{|W_XQxAdnVybcxx`kG72@s0tdt$dnE)7{*So7!UHp$$3&V)NXxojE
z2hFYd0LscE+BYy9VaHd($&MKJ@{oW5A59YJxM(vQmxxMsIDxHk4TYQ(<1~1&8W_HP
zA!#e02<;Lsk;5KWS!qvqR51x4pIOK9;89x{M9H6?73I7L^Nms`Ho3S<Ks7%(pl!Rg
zw%0b&D0sT0z?Y#C=Mp}_Ic&6Y{Q(N-zT|~j70DWi6lE#+HoOAYefD`o;Z!(nJsiI-
zQ90RQX$&Ib2)|p8_*lTjpp`@~!nq)Ry4=THN0fDqZnB|Q5+2MRE3O+$en9ZMD+@dR
zNCXiL1zz7ga;fIovjc&5>1T@`u^#%<pSR_0c`7BJgqVQ^>`pZ5v=Yz5fxa1>5)#B`
zo4KXChioKuG(_qQoPsdiC`ktFYPkeM@Zp%kutXklzJig~W+1VG+N@Z?a~o0>MGVrh
z+vFAb2*+g}&mPK1eKU|66Qg?|_l0bkD>NV(PYX>M&ve+Wn_9TZnf?8tTmk<+y@lKy
z->RlUUxA&;yy%yvEiE<njcTh7<=st$ejoyY@gvC!)p4aq9%MU-l^wv2y=hspOeUC0
zpE5S~R)e$)I3oSAxx#LKk&qcbE)UcON82>hn^BhCyhjC2_b25ppSJ#@Y4&*~@2o7c
zOhaNT4<W@VHt`&Ne;D!)s|^yoi;{XganzsrcBh(7B9;$VC*K>l;utLo>%f;Z!t{|z
zM&$>RNxQ0k?W-(*?BYNWl_us=)^)()A7(Mi8d=?*%vE?^Z>;loZKZWWA=&=T)$=|T
z%DQIMEznbRx(Wlhj|h>4r!jW;ZL!X0F7tM*wWZ*?`P89)jF-MPW)zEO93I@;-fPp+
zRC1Da#beIG-<=Vw>blAG0z&ypMw6&V4xi~tZ4JYZ+49FpcB1})w5juA!l7SfVER6i
zTYk3kmTZ6hSJLTl?8?~h`-Ar;yizn1`PBZ29_96)B-PcR*lLDqa_OQYC&BigVI!!m
zQMIZKwgRu`nW+uEyGX8qSpK0mTI=|aJ7K;!gH7FSCzgGh45oI*yDho-R^CxKb8(aK
zwi;g-Jed|ZGc}p~==mvXHAS-tNRPrmdwC1OV5qJ4wh|2{YHJ!*JIMj>ew8Ffot8=N
zPOWa@M3PMvmvvWLLjYkGoiG2>BLfsZeMsEDyY13oe|S@UxYkYfSX>ANw=Zb5bww%e
zs;#=O!=T`=kJ>VoQ)+9fY@jX2LrS#{Tq=>+<__OGYvKOiq<#J+f@#J!hU}bJk@jCR
z78X!jeg4iUp-`ZK-nGS+++q#2HE-q*yp<!N7QWzPo$Dmq@}=`xQTL+_JNGM<9v|jE
zxosq5$Ki}-$0_@hzrv99*|flSoFCkY@6Pze#}N}L_>H;hhCXzSkE^Z4CqJT=cNN@%
zU8-GFI(bl)`$EhZSRrE~Z=zCLt?a3-`N4lj3YS@kbV@Zhf18G+B$51cG?vRBaI{f5
z3~5Ko1&HBf#N5~@#n?mE(cO_%y{y#M0-bai3PEc0m6}*&88%cHw=ymz*~nR3kcC9B
zxx@x3@K)#QjKNGFpp<ITv(qdYlG^&)t>5u6%J0tG_0Uf2kJ2H!Z9kZgJZsFtzmI{T
zaqopoWYX=t-4>46!|&-z?0TA~qrdK2p25@r*)L5x_iv=bxj!$-{m(J>`SDo9tuhda
ztz(>rf4hNktF?=Hy<<;-<n)4mO6VHS6Foo13aSW^W?}JQz{K$mrxVreu<&pLfgU;V
ztcry9Wz5M1baPxe);C=hMB!F8S}|E&LdC|%F*FT!DSr2WQeL7^F}DhQw0qV89c;*0
z=%02d0$LG0O{k-bXR~$ID#jwAiaJzeiJOG;C6ev|GqTq4^m@e{zZqBg$Iq$|cTl!-
z2C&Z2v&Lia{a=!kn5*aZXl(do4ATv7F?OR{IfWf84c<{R;HQ{B<=@W+`UE%*MZv+o
zZu#In(lR6Nwz5I!OGL%vutsP(t~p_UfsIYy#}!_S$Redgs}nU@2o>t)A?ASO5@Zw9
z4-H|yMUq1NIo~Scj3DLE(d*$BN`%xGUKWT%I?;1oW7Kx366@vhP$GfCW=S>IG$8I7
z(j@a0N_rnY(N)+?_9u9D6Sw5bh{KqbCwC)<xvp-|&3c<?3|S?I4+}HM=m+BwAq}MR
z6bbr7Nn1M469`#+Y-o6dA#CN;#aom^(yF54W~)_`A`YTO^P4yW)cnSh<FH1nnDJ>#
zLM{2}yc*B5FN9SX(eClksO4ufKYfYB84?#?|GaIdK#WEhW)`<28<o2YzGqqQ2}0ZG
zFltsGC55c45bHyB+XMl{$|hD44-=Y6LuF&2XfrM9@1n2+OQ{k86Koi5n+&ZK(ZTrK
z{dj2qqH+=Em&B{eV1;Mw>p+lyw=ABD!iM-FSa4l`=bwtOu^XxmhW+-4cHW$#tF*dM
z=Ambu*I`IN2;G|FdLiU_Q`t}@vi!~-vSN9D6?nDA0;YQbq|(yU0zb#EGR$`HO00%e
z%&zu6%}%WYt)PJn!EZ&?X8)bi?x_90h<3~24E&?y#M@$=JOm@A)b31eL9Xm9+W)(;
z1VlDF5P7p~hIZFAnKx<czPZdwDYWBG5jFwft^u?5=#Kr3)*F3F1rGMabKM$9Px11k
z9o1HSO1|@q)Vr&rsIqS|4H0p_V2;&Rx|TPNOXsr!)h@F)lYoEygs<Hae9Rfz@@RUJ
z7_5~(C5<(lDI>d?7i*2WsyGfy%oG$R-OKTOA&H#aMGL_2(0=F?8npc25>O(9Uz=K8
z>$<)hJsh2*y~gJ3=&M7g^|Ev-`ED`;w+&vh8#&@Mj2^$x9RtVFQ--_z2R~fc*S0d_
z@gifay)EPZ5a;Yi?qE{2{HaU7N1<9iHy!?yCG|(<=Epr7=E4iDHTdvO8($o>rTgDs
z`YLZ=t_Ln7%@%po65mtdZBtywc-_M>+?7vU{M7I@-H9%7tUhM^`kWR2`vnfP(0U|K
zZWn&`icI<}MaQ^4e}`wc?iM?6_3P))4PRtTi9(Y3xgE4j8up{>#xGM9u^$9S`6JWV
zExAOp6a{DHUvH@w3x8(Y-+n{wW7Wr%k0yJj2^~m(pFKv8<>77--}cV#Yz%QXSH4XU
zb(j4AIk+{m+RM4s^29)i-_cK=Iqfg{K$`Bqo41WB=QS%h!MzJsKC#QS4xLXYyo6NF
z$dYW~a<fn5wMna;m(LHqdx1%bG`IhaLG$SMtg~>>Rf~S%&n8;!vYt=ecfo*r@PjZ1
z%?*LNl#D)1!auJ0h)fBuK=W~O_#?)8)XFR>ohw1>Sz;atq*V0oEZ+Z?4>{p#0$}+h
z_iV)C!b8PXqP7+XJ2hV9Gc%g|Sc9!|&|i`1)!wE?(DUmLN*1-X$^rYm7pm1(f8GH%
zR~9u_uWE^v@v~{>EdFE<WnNIbRFQ&L3LkorHXl_TY<}YeU1mRU2yf)M*~l>)D;9SR
zGR6FEnjv)K^p&)(mzw=4!-^(3iQP^9{mX6X?T=i+mQpqZJ;(F8&1Y-dHLSR!*{LP5
z{$`VlHu0l+BaETu^8NC3dml$K{_D%az;ApWnJt~oBEdeG?gtKpyDqatPl@uhYU*2y
z;oKh&vddL)GMXD3UL=5K*rN3p<6Yqu6fn_YN60h*PHugzp}Qh8`ytyg-};8==c8#~
zm242Z4EnDApkxy^)l`^F6LQH>w3mNQYLB0lN}u(bKSXUMpyDZZ`l(i1V|oXlSH%Z`
z{%y*~<SUBnm?NYbzD!5`$AjJ;y>K)Q=S9^mdw5`~zI;d8vLAY0*Gj0Nw*1TUnLS+P
zZI2IAMS8SLIF53c6L&3j>GSp;mT5n>B|BRDCeAybXXzI%POP(c>^{3T!SeiR((MDn
z2!mNwa8JSYxSck?ww@BOk+ZEpNu*+*v7D0+5K>EhR@L0-VJJXuCJ7wftep2opc%u9
z7+F1+z(=!>0gvfTw82s#XcK5%Vgx6%b`u7r6-!D@0F6&Hqv3sgWVU$9vySf5AL2BW
z6TzS@(D@WL)f(RVnA8HZ|ABxCxcYf0(9TcDIcTMy<#z4+8RY_A`zzCe_J*C_-3rZf
zfq{wRi3Y}is;JxT3(w)3jZ=Kaur&+{K;l$6JPiV~KLoOs1Hj^*hVgWdG<vxn>cY8I
zM#+w@lZ;C;NlffnHZXgY^3!05m)JJ1h;4oWpQ!9PNl4H?7a)a|Y$zIR%<&`H@#u1x
zZG;wUO3Aur2M_)1P&bv+v>pZAEn{N{QTLcmHM!8FissgF#K3!=VlD0_Ct)8RD-g(w
zBezyc<gdcQiU&SKD7bgQYbL^&;I~U`VS;L4Y)mE4MkdBU1GTzAVn}`)LQwU-Azw>!
zekyU&pK6DEBoQm%hQuO=NYfm@B8Uxk{zBVF`n0F&Rs!A;+?XCU9|;En(o!BBqAO~I
z8j<>gGvZX`UulCl0>6?Uwj{QMk|eWDsyw-y;wd|D6n|h}&n*Y#HC8=0GHDYan$9pw
z7^uIUzXBOrfrbCMgV@z?27Zo5P@T={HD55HZ}SAkm9use`;ssyz=DG<m!2)EP$^4r
zT4bN*=VO}FT$+JEhscp#+Yl<Lfx8A2a3Y;^B3TKf!fyy2F-ShZ^Rn>hw7LSk8CTx@
zd7jowHF0t=d{M0zvd<7#^_uIsX%Kba!*)GOFQJ{?+C@#hBZ}s(Qy9^v#dHBhKpYu;
zAjI%eGIG@~AG}U}B~xs4T^xivE~kTL(&0Tsl7T-P<9EYK{t>bdq%HO{e&(HQ3C6U!
z86I?BlxASPPc6g!aorW~^}&(Ydc|MddmXRN$Xv%xdNla@`czgzn8vK^mr?x=)8uuI
z_rk~zijRGv%X&$Z91mbRepXVg1C-BKM$Fq~+q+blqIa9xBrJiL<Rw^Ee-zK|Nl|=*
zwa%uExQr^klvrXHQ(eAv2a;#^tzAIx*r`Oxy^~`zwPiAS>ok09KSXWp1A(mg{EBpV
z>GzpA`#7!ScXy{L(=Q!XOzZ>$pU2O>3LBu-wf25`&(7`KME2k37<><<lgod^TI_ph
zX>}#!iSzNK=^qI>OuUImpWbQBgI8O_ecIdLF(!wP{`5?ke!sQj)J>$jjuEH{{`z$S
zZ@wDU<F#+5o;-%kj#e-BI=Ef$gnB1y_KG~Nwua|k>~SV!F6VZR)atKDhaEo6{m(B8
zX+7VVt&OAgWM*F)>Zroz<(sZZJ+<@0D4k2U^+wXfSsxOc4TO5Ar22B!vCiip#fPhT
z_;B6nlUi$kbJqw9fT`X1UM<!=8(ehb<_~uvatrrt`&Gwc-JIF~!5sSy*T6tOV48j*
zM|d}Vwl>dxRZjCe5u=2;bFFyWds^)5P3=%5l)RO_(+Awd%!BAFk6*~(ZJrnRB*XL1
zy^M`M-=!jbhn2W<TB_D5%Obx|H}E&X!aLbZo?XiL_aAn!q<}iH_`z(dA7i|y3`75C
zmU>}|fvR%J#bG)fwx>+}G*{N)*qqub#Hc?auzjCSTIJl9j>nS%^gp$I$FwAQooY!r
zRo|W=>|vHYHDs~{1nP})v4a{$P%ib0-p_K>G8K6<;3*pI1=c1YEvnMNnbg*#d@x;#
z2Y2mzA{mRy;kI8it+rZR(w+PT8hxTPx|*%Z*v8?bY5{Pp3mpsTr(c!~zw<U$=TTc{
z|J{$xf&HMb&xW7<R_dCMBt?_VERi?VyUT4y`-3kC;Y-`Hfk}4G`t4`U?MLVX#a}k&
zmgdeHu{)p0d~+tTKiJJ}4Eg^=PYA=VHn@+kZJ$gh7Sk=B>o+8xKHyj?T-Z-rCp@9A
z&P?+Dd@*_HZ$vGRnKz;I1Ce-$AMI@jzvvVD+*b7wBT;SD95w-&cI(>TGk*$Yr_V1*
zG~mT}Uq<ai&(8Hpt%XY$X#YXk1ayQ`Z!?INrP5BRJb!MfeSTia23B!s+?EMnJ{RI7
z%aU$L!*4ol0G!n$XR2PCgJ3r-Uz1t#16N3G-ClgQoFR?;`}KURb3s0K#rG;oR1#F0
zqfExw`?;K|vxm3GYqXz{BoKZE-eIgA=pF2b^(0@~!eq{GvTbHDSk~Ij5c@9*mp{zx
zRJ<Tukv0O)g&ge`ZS9&6IQ-9sk`{r~efo+uv7Y8Bv^WUV+ZQC~DRYe0DLclCk%($s
zw+02OmPo|B^CUtshG;!AZFZunYzp5bOo8X)5aYB6dEzR!_gLnsYp#{x<IT-i0fzr+
zFnOA54M(c8J=sWU;Wk3E)~tEwm_SPHD#b01qCS;adbcJxC9O+X^bz8+FEy+|AW;y<
zQk#y!ps<k7sk|*(Unj|o@O3P>3y|ZwW&}8`)^kHh!_s=;;U3l&3PMF%Ap52uR1%_(
zA36sfiMf<`9${dj%>zhS_VoM(<*X{vnh*t2X<|zn=%{f!ew%~fU^b@LtusfHPT|o&
z6<}A@{4@{q4?q*?#7!>w)*k(~!o*Mye9yAM(@_@(rj&&ygNp6dlBm|vtki2j=qbqY
z>CnDYOoL8bl3HlRCqp^TtTkUpvA+Ucx2h{-f3cbh>Pnt{IiTmvsmE9w8zm|+Nv;8j
zmw3+#KFYQ{jmb68S9u9FB+{ni=J_gw+#}A+ejX<$Xmz1R*Uj{uDWid(GkoOo_v3m-
z;JeskihcwKS>r;EQjLb$u|%6iQP<iS!jPvg`JE+?r$FBKjZlQWscJojgK`q$dly(q
zo=XoX3EKK_8eQ55V{>J^^*DG$G~cudgdzwu!ZumGMdH(;T^ko96$xr9&It@t3Pp&v
z4Gj-1PgA=#xDLF+-!(xCfVu;IQ$QSnN01@fdWJW2xs}8yXF*B=ryx-CBSuSpGFEDU
zJT`(ZnNjm#xrmuVD#Ym=+%1$opdLf2Vns@y?mDZ7r;I9iUeB`e6AE@rie$#fV6<WZ
zp+e@tm=K@cg)W6Xvz-2%!9!g}4}|6Tg+bodXq%QIT%Z6(tm~*ZDrWm%S#3pF>3wqa
z1EMy{iW_LH!fx5U*A;*2FAQe)W=HLbt(=LwDtH|$J$)C3xQWb`U*UW1qTTQ)hjXz?
zSKqc0lpX&qcfDPZP`d=T1RLpGH52WOy;AM{-E^^5vA%jvn#NI{b?ob~aN>5a3$(r6
z$m$sZ(v}~T+8Qfq^4;pSoUI~PW;*q*;nnVS?2wzvcYT9d^Q6^!86yAsl?i^<`DLF>
z{b1bZ<#Q3~Yl?Oi|9TvcZ*^r@^dk*2m4u)3yTgBD5||@O)nNXaeQ*34cFfc{2#fyz
zs5g6H8_SgQKF|N*%B8_Dn5O=NzCDsw1UEMCStq!Cb<Nqo7UsV8m4R^o6Bj<EuUI?Q
zoEi*jE_%v8U6~!dO+&k?x-4m}?5tl+ZA?BWFtL0eou$o{Zei$g@vxocySG^)#*1&J
zISNUly4x257>;DULkG;}UL7OcaB?_Xn7UBAhl}v`8%TKW%=sW~d20Dk)!e=G#9WvI
znO>}VRp7(2{G?}UJ<{0FNCqgY_Gek>t)Upd{s*yg{ztBE%&ysQbtz}XO|Nyz8~x6^
zXY9%!D_LrO>-O7h{=RLN9iikqS*@_!_(GXY!se;VC~6@szL%!qI1Ap_>}Gx7M@g_R
zT~K6`PX<u>Kwx4rzdA1?BIHhcUEP^4u(|&*ru&CT?cTwa8KjMfCZ|YAJKcW<vaAZQ
zoZafOs8}js>TINsDB_atzp~pJMHYGD<9@Iuq?CGs_)8=c4s4WOFYIbr$U(LP>QOtz
z4TWsEbLL%f-eH7*j;a=F>m+JxP}Q1XwROQ0BOW%4yu;#5X6~O~Aaa|4p%;#)thU-b
zYO77YMLBhWc<G;BmU!(%&b~Nkqw*Pvb<SQ8^x<lv?aTh;mW8QC%hHh_rc+C4mfDdg
zEqtOJv#|e+yqNr8-Ia5UJ8R8gOOJai?|N~ZaOq#H(B@dj%sJAHRcdt&t-YUKZ-m+u
z;ok0Z6OXdOk#>4x)I=-yX9nkJh(r9yl&?MMIe26J1DtWvc_|Y+e_x|v;%s66u9-!(
zkwa0}Jz2%wj9Ch)Qi_+gaR|78dir(7r|6_E>ZFGg*IGVzU=p=8Cy|h`+S&v$NNp8x
zyl*454!z(~bZ=;cR(LBPd;Ia>i4oM+(!RPq3XxoKh;bTHb|TyHOVkcjdfqU4pR=R$
zHmpTnd!n9m^4}O=-DO$kFY^04XLbsE*Vd5!NyCnm7gEqAXxVd;MrUu`C!aItamRUj
zJvRbfkLA`xNbp6+io=#k?0HxdZ5>Y+M@+^Axhqf)so4z9B1jwSLJ|gTLiWak3F1Wp
z0}MXc4T81cw<%abyo+QZ?W<TWKA@DR0Rt=zR+vkyf@wg7S&R6mc9P)L@;2AQS??JX
z;2e1}dh-lr(`S2OU)}`RURmk6CkTZr{BT$O%NQ1i0#lw#?U}$~qJp0`6IUw^<FHBO
zDaD)SZObQR(`%RU>kCpR)*9iPBdVyVM8zE*RoZfI4l?TGsyLz97Dd=Ao`t67ZI;VS
zeG6LIFv^~f-y-316Ug7GjCrn#zd@oPR)9J{H>Nb`FKKA~Kyb3#1cf&*VkK>Hnfeqg
z2I|OGp4^=41J78KJZ89V6Vj_WWq~!7{8C-~XhzIfOWKDK83FkS^eu*9g!zobnoz$d
zK@i9^YtxTssIA}(XQg?<!EZ7LL|0I>6arQb?>0GF3Bwz^kop3dTRq%f!S~o`8Z9|7
z9sL67Jrjsh846;kf(D&glr~N;eKr<Fjb;yiS*8M<449w75URI^Unww!tOtH2AYfAz
zCBLj2QmH-BBS0|VY5VyxaX{|OW*?PL7qWRQ+NH0Y1{wW83F#$INue?OATIh55(<0T
z*gY-84WOW?hT!C5HTpbK4W*XPGaux4?rm0-oS~9@C8uXUPzyHjEGpmq1l<P{-TZr-
zVI)av*@!ts+X!aN-DC@n46X%*<8AY4Hz>f+Gl$irCF%;K&vs-@%`Hsw^pbO%AKCDh
zReK$xis`+4`+=gbfYK@Iaw>Jd(2`XU_)&*ij%Nj{*_*4pyo<_BdK$?d{^}>gO{lv%
zISEM!B$mgMNUOZvr4N^R5reePpbH8$i&QZD3CSXyu~EcJw280yBA;r>;atZ+v)CT{
zi!xilYnETm7StpqhQrYp7}!_ake`l;-g$kCrK9@E2BJVr?&&yB_gPsVU1n~#x7zv;
z4T3*!!rKd{4k${#d;uFMZ{diGy|*Kk3&@9^Nso66Ip7Sytk4N?50MY|OWoS~^n_0H
zN!#!U_+%MI%WHxh$!BQFPHcn17jVH3#}#8?DxC{(LSWc3nw=CPJ$`t_QWe+FPzblW
zBt-u{MmjUcqQTD0*{{%XfA^IMX%rpS(vlz8{5kUt_J3>O$R^>AHDIiBJCZz~jTqxw
zt=ZNfEobulFd^mTHg5*C<7a1`rT1B4kJN2~zLhNr$+Wd@oBa8MSHao)2PxUU5X|nW
z+J~p1`d>gwFB}TR=wo?0uX}B>r{O%^L%Kx=#F5=BdxqzpnF~eN%#`0^Q74{tL+(CY
zdwGaT>VeN~Z6z!&4i2JiEDXG3&hG2%ZPwG*xG?-p7TW$%S?>=mzI$B!49T+Eikizu
zgy*wqci*R{m%l!DrZlOXmAEM_@)q^;4%j4%huH|qA@`?LW23n{A5~n$I))-Q^aM##
zLjAyx{z~ycI~jKmzTwU8x_u|q`j|WP(|P{3{cJ6H@QRtKPn|z}b&?#gGx95v=_^=m
zb>F*us#DBaYp(g)Y-q?4;qP~6#oZsV>?JfK?M2?%E8djYIp1^1!T?!X*k6QOzQ$|+
zcUjRm`ayW=U$Dhz@-KA{9TD>CSHpdAa6Wweqp4kVpzcsx`{l6;_dF7`(`xBmYNF8&
zQ9;TtGv`3StKyox0#r+yCz7R%Qn1i|4IdBa{OE_0Qk6b%lJLYcS#7PdOAdTcqJZWd
zA_eiY?>ltkBzyn$muFgS4UUTBKY3lAUL)MzYU`35aMpI4C{`PKNyfRuQx^W?#m+u`
z)4XCo;IE_y<fH9lEt=-JH>txJnylS<8Iz1(OS1XhRQ1VeW|oqz)|kIMPnVcLnLmDZ
zkqrG?mX1@MCJ{($=-RCLHkPj4mVLoK`uRM3WtM9PC9_RHm|wV?Tnba!i0_shfImN7
zO3z}R#J}0)c5f_&Dx{A|l~ap&8Dr?fiD(C0!S3(~i<{30$WsC$`0tD}HmqU)7tJc3
zNh-H=UzDiYovhHFk$EcXH11j^u8E&;6Qh*F^km^c&}ysGx2@*i7`Y=@6%fhye-ps#
zf@9CFclI|h?AWUAzoi{aT5a{OAtyJmN%)SGv)&0Nx8bexEqi!A5C@+{Re(F_8D4E!
z`#rh0{|qy%w$fjZWfI6j`6F+3=NKh2nM{VgjuTMX)BvP$urJ#N;M!6m*8!b{IX%NS
zn=0=1I!J4I7nLWu=~Wc0^%L@TybMui#RriFZJD(hrkM5wt+04RZR!CdfD?rG{}P;r
z7#XQ5;SxLKCM%co(DjaCOXQF<&x3+bfr_FZTw-mJnSy4#@?E39kXbgb^lnGTnd7*T
z`8_xm$0835s;G1xW(;mBhLnhOfwIXA!QC;`@>!lyT5Uq2ev@-YkzI<b|Nb<X0B>#R
zbiKn8mQ7^wbSj0_I+kkG+4E1Sv(#nUp30{hY4Q=76uAgvzMIqIIF+i(HwrxlZ`$Zp
zia<(|fpduUTAE-{pbm}BMS)U<<Wof9wy`CN+!X}hvu*GsW^QM3W`Q~BYjl4g7w1qQ
z^RhNb-Vp>e7zY*~`>&KHCqeC*1B>x-X!EL!R4bP%S9~*C*~0cvE@Ixc1w#b91T~vb
z(cgrh=dUjmW!!+gCSHNBSBPFNIr_p8@MEkb$!!sI?<`fUEGK^|A#$g?hcu6#1-&Se
zYG50XQo<*76g&-;0T~XrnJRSzv`G-XlBL{43$oQ|L<J0a2IVYsg{qRJI7T4cF&M}|
zCoYu^X6~RgI?4bXDqutKBw?zYg)=GyF0~5)PG%@bB#J^cn;bzCPP#ryPk4%lpOV6%
zVK2(eJOV*ivX9{fej0e1bX;Ucj0zLm`rt)9;im|mUrbI<fWt0mndmaq9}YU9_Jdc6
z00jeH5PocI4azV+=#;_K0{$_;$+wOJsp1p549iE-_Tp=h-1LVxkSyqIw-a^BtjZK#
zVq89H7V8jih;@(=h)RSRAfaetr-eu0C!Uz#x~g~QmAux04h$#cvQBm<BP~hM>}JSy
zRNiQ*%3ES19-1{M*8`{lk%C6D5{N@m)QgyG4KK|VOCU&H$4al_>}EV1zc}Nk=ep48
zin7Wjv{qwkc6=Wmr9v62ZUSl*;z0}gqm!xPcs;7>%dn6&3I3cdBNdZa^@q=dTSjq9
zIJhw1XR~cZqHBz|ieTLcVzR@d2jMl;0vmoTbKraa)VbP0b|MCz8JGGs9myt~WXp$V
zO2nt>HhK$Qq(Iz^xCU>Vf#Xqly(*&S#w)RyX{XX$mA5X<Gsvl$ThGsg9AAK1XC;!T
zjYWY#Ew@Gx^Hz=LGAhe5j{b1Go7@&qS4yydwDmB2eI=wVTaR(sRX0?dJwLjNDo3Rp
zn-`?8*Me^CSu1EwKfl^H^c=2dk>EqmvHtV=Q~A-G)#MkHOF$G#Srp)8k&l<9K}kkb
zIW!7rOEeP5igZp<BV($dZ9-QBD0?4R#o1bzN=VRUwsLG>`W|8s60Zu~4h;;D&?eEl
zMPC{x`H(%qO3xA--l~XuWTu6X%IFUs6d$^H5OuO9UZ#iwX<+0OZCC{2Ake9zZ^`B>
z$zpw`paevMXOCOoO|&9KcUD0!xa;gb-04oU6^|K0ynkwNKX+HOLhFh0R1|MPoT5oN
zr|`8|I)#r-b0$L6u!Vtwgcj#lC(Wgv6(<{H@t{Ru4A8=IM~T!mEF32#^~D{@W;d2e
zD!*r{9%~<<(nFoG7<jS!PIW4zgTkEn$+*9ZKFV9QBla$^I%@c@#4<^0#Em25$Qg-~
z<LX_*djlv*VK(?AD6)14I^_kZD0mAl1|Vels7Lh~){JRJ`Xc@qSuy*CKTx&UL=tw!
z=*l4^9F;EM<hvVg$yWmQ#!wO*lM`CX4;H$yJWp<o!ij~TI2sY!=3u(plDHl^SGi^n
z%b{eNmM$FPxil2I8v&a*G6fF><+KaY=l>z@ZJ;Z=syokp@4I?+C9A5gWVw(X8y~4u
zMm7ds8JiTwm?M>JWVbtchBCMbAFmwa6d%)FBnF&}fg@SAh2uqJ$0U^wnLLa;Q#cGM
zGIW-c(8;qYG7hVnREVJoE14Dy?L|C>QM^dv5D4@8pZlJqa!Gp6$yzg8diQ+ov(G;J
zeB86o*X=mAHkmjV0@PJEBG9wV@s$$qakb1BBjir~q{C=K#WAH0v<Mh)`$;F#O&ndp
zk(lZ007DHd(D4}LEgufa;dFE`49Q*R7vJ#q(mbpdl0w+Bq=dCI@)8(dq66!LTC0H{
zZb$B`2!9`|mvCRR=_UMw0=t3R3PGyDuBI?Zz{j!tR_N=)f?w~7_7I>_0t=1f60t2%
znB)#-Q+{MgR&oN!V<y^qd$?23N>Y*WB$gYYaepUf!Kh66iO?*Kbx&0{u8>{lvzZl!
zM<+)(#TK)m48b%|@jL>*l)nqYrD{4HUWKP%!wLV+Yz%aiOG1DEUXdl{ae0@}B8Do)
z*scUGiTG89$~4+xn;2gH)anhOK4>S?^U{%#7U90@8Lc*j20TS*ROtv`o;0Ygu>|dp
zmzc=QUA$X8ysy$qkMP|XHnlsu%`;|yIq$t?O4!#Y@FBY-o9f({O1&HS`dgs2;v8ef
zB-j;n>OgBhd;fIF%L<O#w&B#S;Qg?&I~`zZPxFWL3%k@dft7h1ml^&baL%E>Bp{D1
zz^PQKi-(c=Euby_B2Fk=NqT4H#mrGMlfI{~7=^8B{`P_y3G-$jD!k#7+DCKli+E8n
zd0-oaevlUF53Wjg**Mz@pJ~zM<YV5=lYPH4?K{3BvDVq71FV*BbZz#S>rXch`VFW&
zUE^~K%auf5dFTnMmz?R;lgCN*eBqUD0sD-izV>p;_u0gU+6$cRxZT@?ZhLv}FY(gh
z)Ro=&`+@sIr!4Ge89Tq-Ilp|SXa2p+iU@24t^3~+;@U#9#WIohxdEEwziHd$;{@<3
z8$X}z2Uprdhi{~ovZ@pE+cR7K-V4eOlI4dWR_*CO&aLt3F<HAp+6Z&A;n4xF3v2wN
z4{|e)(P2K!yx9tejOSkF!;QDiH7#qRwOo?8WGGMU+aF4<dDI4Kb`NVzH=Ya@?2VKa
z$L1z}&}S~m?c9rho`$Q&cKPs>G0$&{x1y>%Ip`XW1Y*yQxg{*Orqn%^y@6kc`oQ*z
z3%6X&G~|C`N#XkK!s!7bsoP7Lmit7__K?Y=FJ>A&Znt|nWp6Z#IU`Tfp5BRN;Zh%$
zcJ$c`n|t(byKeAuCcG*25!P6GgP1H=|6B+9^>KSDx2$}h830k>Tb8Zm=1((gr2~jh
zT8Ov3utsRNB5<wZ`QP|w4KWa}>Uiz07xC-?ehh|NzwnaGs^qw~Jf|qdJ#Vqr*Uqkl
z)|X~2JMmJA`l%~9H}_2DT8$s)h3U*S-qL3;zW&N&bnwui9sCiiG>^TFyS|$4=HpuZ
z{}n`4`xHaZ%Aq`&Y-Be3BR*5Q`$Bx5UN>~ug2CZhs8C;kjGvRG1Gf&&y!gh!<e0zV
zwRJn%c|mnTH#X~%iuU`(g_Ar;9|msYcl2%-zhDuLzQIcM`sE}%vOB9U{y$W#*m-M@
zc5BFd^M7LabPK_B#Jxh$jV)>}zNC)r__XN_;v+v_?=#)@@)3G_V@2H`Y%zXL{^7;Q
zN{M_X)@>{>XS=nfz8AQH+j;6|SpDc*8cqKl4UC%R@65LQy(35Mo)5de@RZ2xNgBz+
zjtZw~q^Uk<*Uzw8MBOQlA@is1$gTOd0&nWrU%e=+dk$0ESEnGx%h`X04*MxPo-L`$
zJ$#1fb%hC=?2>^=(NLkrirkgp8bW-}w4D-n1P5#BxHQGog11bHN!eRO6fIl`3dh6q
zdw$^B=;b#Ta7?RmXIMs4OOVrKbl@%-B5`d-)QdFoQAUTwS;grALUsw&zz>_FJjsXh
zZ1vEz5EGh&RFKyaX06FX=>~o&50B}1&s*gtY=Q}XS;i$ZBkz`4Ch+DIN8jp*arNj5
zfpl$n3pC`Lwo-|{?54LsRZt`q#DywLqs^K^UP1SBN8<1aS))OI45C4EFQYbEu-le6
z_`tQM?*ay+#v1jBPN_E_4m2VJ$V0)iRE~L{+58fkh2#{niuYDZ45Qi#8tyatE<8pA
zM_uEuJA}T9^PVhl?AorK&phidF;?0~oz>nn;6|17VzesN<5Tgwp21#@VC~YRU1p7P
z{GrWk?1P6NtHvx8tVMW5c4-6Q@C%Ys58zU_85T?~vMAylH7fC&VXgBoQ#?@m1eCEj
zG?X)NL}R>#ZqZcE``C4YDD2k;gSUoJ*r0km;&d9>Z+3>~^QCZN(B_Yzp!L~x@~FW6
zaGQms+8SpUB0foNL4iTP>#gZ9&01m<&O&tYxRc0TA@WB3^*-j)r}C&l=zbRIMh3$f
zhdgdiPs#`h0Cl24A`_KX!N@0FipeTO0Cx`_(CuR$M*=h2kcplDYLI3-?g%&~n{sam
z^NAM5HUJOV`>UqU{5BOFE43`Wf^uV(gKhLG{5b5fmr^Z>T?$DjIaf$|auFgQ!YL@A
zCMI2GfJTqt!Slpi1xYfxMPhw`6H0u@0%wB!{`DxOU$-Zv=!Fv~Nj5;m8@8~YaZ=*i
zLx88B2&y0_*_Y7(v1D*eMaziDAq6ovjmmlk%5<DZ&2Gd8-OwEaOY?BKJ}i-__w)RE
zfWp_yNsx_jQCt5!J<l5U$Ut8|YU}VRqS+`0eqwSYJ;5_7x_=`#y{uX0pBQi6_38at
z5nc<smnTX5R#=mFUgaMKLfU-a)TD6v9tQP$vgzY!skp&Kzg`|$vSO{01{cOtbM#G%
zRHLQp%0S5KgG>i}4&RX%&-AU*Tl$a9$f7;8+qfVfA+}-7*74cMyp3&xt?MX`<Ndbl
zVV%b#Z&zM3Gw|L#^fmXB>y<RpAGi8Yt=g30b&Dz=*OD|}g)YPyopEm;RzxlBji<{m
z3qC5rsI3;RNYe0B<?-Y=>u0E~bUnQRUs7TMavg41wWGFXPuGI^8Savj+DhH*1`av$
zf_*a0!hhaXwH<%#6+@5wSJ2W%zs%sF#pw9DcjrML-3VXV;YZIsK$ETBUU&x{ABkib
z^XJA*ATO|R|Bs1Y4**&|{H%`Pk{qYw6a}@_n=VX2Z(3}<<8F`IS~L%HA_wgee15GJ
znv#;(_k%Q96lao!<JS``UomEUpQ7d7{Q*n-_-?zIZl-#XE!946$$jTl^X%UDk<7@^
zBz^nWwuQ-rNd+|A!nZ2UzDb2Ep6(Be>7We`9<5u$&xPz8zhfWHe=eA}N~q3XZuuim
zW%kiqx1~FuWW&7ci7f_ZZsZP&b7{(@=cgPC!r*SR_x;Iuv(`L|5e56w=gNRBpY$fB
zz`og{GTb#flOQLDU-<mxvo`nvI-Da&a^Nx-_n3CR&1l)(95K?a)8k*+=C$k8CRP$Z
zSBaM^ZJA;WEXxVqQ8N$@?Nn^AxzL3>UOHZW9OX#G>9&_)$~f2lLorq~zSp-1ZqUNC
z?_6+NueB7tJNRSw?M{!|f~6msw8r7@B^s1DYDx3R+55xEFVRaK=PRaGJ=bQ>`JpBE
zOwQQHLCGHqByiRCWMZ_zi0JX13pV{$Uc$>m+(o!EX=*lQA|zA8e?y;>w+8+6BPgL~
zUX5l8Q!1#gP&>{9jIc<~96!%bkiB<-4qD@Z4^ZssD`rPZ|L#v0QNGR<NGD$u$wv1h
zRgO}B4?a&=D?j`qAHSZPE;HqziM$IBZ=aA)E%ANBds@`r<TmqXA9_)Y+vDSf)}$jg
z7j%~l0ELl5JLzR;7urfLeYRk8p;P~V5O-p)8;Vl87RS6$sB)l9!b=ZO4T}6<E(-PL
zhZ<&I4gsg*mml0~zm?sS3=d3R8=zSYi|ihpqL(7cI4-VKMwTj$mjUjTe(MWwTgt-a
zggwEWg9L)eQ+uRZjMU*LJk2NgmNHLJukhgJh|SDgQ#pho`syBFttOS<W^^%*vO-=N
z26$QGTAly2ta21Q7x<0AKL$gmOU%i1RLo3+*Y40sms+^G0}cuqF@3Dw1f;&qg6A7|
zmbFAw;Sov>JFYU~s%ukAlMt`%fPz4y_cVH0m5^HQQcCgx2YGDe4oe4=t=S3VifSxc
zwJDD<1g_QLo$7IhVp{Q_qOCmX$Hk)PN?hF_bP!y}vfd1GWW0L=6rJ?|YiSNf-Ujm}
zSXaav#vJ$3jKb$7sm-L8_`qN)3y;$MSwlDpICNaWi+K%D_wvKh9hB#mg@{N3ju%Gh
z*u%0Dwu}o%!i<wA?Qsk-rr>(VT&2gxnir6jaqu)BJ>=O1bmnf6q-|)B@*Nc)0LLlZ
zBKxOsa^m}3^C4lb%V+H}`FvF=1Ku2~mGIlJ37n092ok$fLHN#IW@(dCC5Q^VhDnws
z<1)8|ggH_n_zkcEYa4tS0-DHLV(0>)9qwgTTe>wBb~b`4o9gBW;6{{0`SGAu+d6w(
zzsi>?h@Ub}Hi~|lU+DNCjMWQT7AtNV|GC&&$2yIQ3N|O1O%mj<x6qb!hX6b&$>y4S
zYnztA+2c%i!wiJzD#yC^E*TuO?Mh?;dMRNc?SnZ)g8Ei*^MquNx6EUf5F`d9Zj%j&
zpzsO$!>G;9IoO<1yMVD+T3EJ*xx}l2oDMDcfB{yP2&1PE$IlNu9p5V3;$}Sw>9jD5
zCu#hOEG`oc+0vG*G|3pyB9&rwv6O)Bpl)6yN^nX<+XB@Qkk2+mRWaIWRHqFt`x<bu
zMxztyG!xRWS3IgYY_c)2m-UOa9PVQf7W<$$A`!V!1`#pG=4y({>T*CnL2R9*LGHoF
zV|O3tLF2BGd*1R4onhW76A5H`U`&}7QOECeV6^1zym_YRxfuv0G)m`mw9|buJ3;p9
zgP}a_-$Br@Wd%VrF7VuDlzd}wxi6_MpEEIO?+<h~Hw`&ko+7oDZ>1k##5cZ+qIgvj
zI`OwM)v`;-hS^34pxWn4RRr~8^-+dGnH~N~8Yn|DJHCBMH_4aKoX@#a#YfJ#QU<;+
z>PxIXW$aMx3eIZ%#Tnsz4rP32%0_P5nZH~+`9GI7l3O`t*c4aqp@{<b*bn<dpL?0R
zZt6p9QG4V}S3UXP=}6pI;1;mF>Mmk8Ceuy>)|k0*`WclBtF6U>q8T2hEBAY}+De)J
zT_5<}0mX_}=Z1K{PCa3@)fxvXY5F?Uj}5Wbd#d2Y4|+<r{43jr2D1;Q4g5Sc2i+p^
zEPF2Bk8V+%`1c8i(-Llf+#YQ7kn{FiS6C(b+(3OCy`GBxy=|#&yD|{J3y`cM*;wzw
zRcGZIs|c1?DwSOWA7qjDNsj+cZEvJ}TjOBk8#FGC%{{EqP3ui(g!U;gRNfY9>&QiP
zbl=)G6De%@Ks=52Pr2}g%SV!nZ}Y9j_bQ1uMq5`}e(dvEx`Ns|$!aT?ZyZeu_oLlO
z@=w2H_NN~T&VPTu&z?D--QXcvnyZlP!WALhY*XCmIbhR+|JYaaR`IjxsAB^~c5?2%
zZJB#=(B9Mhp}yzU4XDx+7fhY1wszu#!AfrLs}?oK^gu}Vb^Nz5wV5a(Tmrie?bQFT
zui+(Q-r){^@v@d@wKbD+cnJM5Xb2c3`Kec7!$(^sZ0Q0P7p1oDVYO8qbay~!ipi>f
zlG<9Y{Iyf8+Q~TzaEHy3Y-^TerM9N1tzH)ieVoG2RFPub*}qS`S0w63vG=YX`no1F
zyvH6tJ3MwP>+q<p?%=oj6?^>k=eztb&#t7$zcfmbK=Ok0QdbP!MQ&|dVjsD}2lwCi
zSoWEIbGh#?TH`yc^4M!gH-v17kAdb?j0eU;k_`VHqStEc7au<}u`{ps0SS3YX-jC5
zvEr^>BnOBACrbz3JK~f22^$YoCQGk|;~v3Byc6*0FBaL754R&J*Fy;?^+!ypt%bdl
z8W>Z-hcj10<<a6>XgZP7^LbQPz<wfj!}a~&;j+?N#d00I<D(m{h>37oFGFn=aP3xE
zsw4H0z7V~56uj76$FY^!3@r1dQ!kp6+UnDp-9paz*wKZ4FS^b>$y`jvWzLJHWlx+@
z)WaXpNqi^^_Vql=xVLY}9-j1BbLXRn#@M5lJ#nFnYAYl50X{8NnEwikI!77su>dVt
z8yH0A#t**Pv2j53y%bT*!di_xnCn~Mtp>%Eed$c+=}m`AUZR*XwFD12{#CCdOvh)S
z7W$L2!vB32k*w@azYd~2HU%}*^^hwT1J0nLbLLgGQj(gqxCl*X<cmkiA0CWNR-u*P
z(H%Zv!RD$~ozJ)@!IGeNsa9{t{)~4zvoEn53`)WANE=vMq%v-tYj}q|NhPlNctQdX
zhdIGuIS@4z<AXL~Zz^Rm#@z))-Xh%b>k3UU&|Wr%An!c&%3~TG^4J`bvSG#|0joI3
zgZwy*w8m&!bgUdgn3r8iJG%HRx{~Mxx?D8Wm~N0%wg%$0qY5wg2W`<g2v@z6nKxlY
zJ$^RM10He_p5+&#dCaC9F`@QQDg->XhM3EyPLgo*F|l7kijR=Fn-op-gdn~!(atMA
z4365AJx1ptX1o$4N$<?&kW{8QDD*u`8i8O(5dV4^cnsjDOT(INb8|xpS43cA$Z8_X
z03-0K>rmeq^>knAs+v%fpHnTS0P8JG)li0`=~WnI5f9QLea(JC9%vyUW(mf8SxKUI
z4-X%4L>-Vg$(q-}n!?M$bfUU+cZ{GuvK-`T>KVmmi`v_g2jKXny=GU+N9sL!y`E+z
zO$R8(5=Rk*q~-Z;EB5NcB;w9x%SPTHe5TTfsj}3Wr!Hm8aVfq*OjE8mA4Ci}DB&DS
z9#1WIRQ#f@eZ)P3dVjYOwpTq$Y<dDNBfV@RtW*4a+ttAg>-e~ebUZ&(;D@EOs*h;$
z1F75x&_OS^a!#5}y<HKyf-lQRb<{L^s<&?tCu8|di6!)9@{FkqrvxWM^)0@?xtTA<
zm#0^?Q^?jpMwqN=I7A-$EWJPxT^Yq!xk7+c`&da9IRNSjr6cA>#&}_drM56A@1O;x
zDG7#5d#}nqcOmg;8N2b!V?=@rhbyE!wgylWyD<~N)1Yx9n?$D0OPjkcsgPyv5A6zY
zC<uBaEUM}*fe0;e_g0cw2?W1@5`6~}SWaj{J838f`aI|VQOJ+<!^@<rRc<3^kGuj=
zC{j0QCo8mO67IGzc8T*6<e@im;^My`hN!l_3_sM$0Y*!mO~SO&ifJ6Dm^?aVFr$jl
z1%gUdAGhZd8ks*{Jlg-wOPKSHkR|Wss{f;m$?dqVJA7A?4E&G^=F4DYaIt+61@{xd
zcBGZ27O6f&&c8RdFzm0iA^%L0S#y|LuqQvlr3Fj*6D*^nw)O@=oT0XE48N8H`>!>4
zx#SGyzRuqm=`>$aQ@x*SalI>FeiVXVW-KiVL(e8|p~WD7#~&}Eww_tk^pT4rZ?r!9
z^yh4B9F-=y>QivV0^7lB(9fSwvR=vl#}?-sCtl^fnQJ_{%?7re<K57cT<kmdQk272
zI%AP{Mw^65ghsQxZEobTH@mR!9~LbTKZxN*F_l+pSh_(YBV&75cDe2Yd;{<h4gd-@
zR$I9nsOpVn*tyn6E@epdqZdqBa<rISoSkc3TU3Ho|955*=SgyfC8q2{F#N-9VPS0N
z_{iYT7n3u`Dn<Tzs^L$CzGUfpcP~8r<h_2>#T2?fxJ_$HO;!cmsjFqI#qF=R$KF>>
z!~YmeLdK1ny+BwcwS0^&<nGIYq~r9@Zr!?yYX<!>7MHdJOKlzeiT^p9vRECSWH|B3
z9W#=Q)=H@yJB`_at`MZ1W}-g3Oz-(qZ%rnd@1y{k{$+^^wbjiifLb#7$TN3)Z4!3b
zrG@?M_wl7w1oja#oB_ng(*Myl#fXp=M+3)YUTcQh+C29CM2y#=aO1C?eTV(YiP7}r
zu3zv)!6h@kST1bghY<dihWE~q;kUmn^ZO3vw*Spk_}?8W7V80lq%>Wvwl=?(OpYbo
zGW*5%XV!Y0>#=_N>NtlR3#to$!HQ>G2D$Q`=gO8QC;OsjoYk*$T1i=A{xI#KV_Ki&
zr<1B3e#u$~+2ZDs&a$U=>&81(29}wqYibcB0+n-+4xjS0AdOPr){vaH2HGbZeZBT3
z$JJJ=pSu*(y@hyC(B9<ov_{w#X6J6Q8Eq0yW@iG6+-0qaJ7d6(kT%CPRP6$X33v3I
z_NRzktF4u%F9_{8>A}5R9{r0+o;J@5Y;~`Odp~}8lJ<W~Ijbj2(^h#fubpWXUhL?k
zN!oYd<Ggy)fyK^hYib9^t^eqm?yQyH;Ka_+*U{f(PV~FaRv)(TZugv9c|0*A(AZS@
zfH0$xNQn05^B~4P^Q$o;G39F&l31DrA4!x~P>R$1xZFQNTnuRQQ2K2643W<~t`l?+
zq5x=zB1e*5{$qMjN7-Y-;1#P1hEbKCf_1EU?7ZE#1mdN9BUY61y)=ga_R%tito9IW
zdGf3oY7NHyOpVl)?(kR=WNJ3fr58q<<<odMP(~nJAcx@ncE-h%jIUow|8_sYnFIGg
ziND1Y0xb(0BfyX~`4v*%r}+h{eNWJeSc7(7XmlzDKKsn^iPjioX#<DhVEUvV7TS;{
z@<v%Fb9Qmn8+X-sp>>70C(<b^yu_@*<swBH$Gg%*vxpXt;y^K=G{`w)Rqumrf&Ozs
z7C}RD1+5!AAcWdEr1=;rhRn~(Bja~4MMF8$Y(6l+F5Zm~#VRT0Hjm>1$_!)Iq%ul`
z%wVW!U>!#+vy0S)06p}}B5~%yF-8jfylg!{3T}CI?P<six#!JD0;r!Bx|zplC!mUD
zr0q~Dw08=SAv%tDwUEMS5t2d#pN%0+hdt-vqg;v9E}w|9=|ePURsP3H6eq<(;P{1U
z*?_ScuT5cb6=+m<!YPFpOIl1jAqOFD328(`KzZ;W5<Mwf9#tzTW=6Q}wh;qLO3s1Q
zhKft~jgtF-JJvTxRcnH$rb@NSrjkm_>U_>DC~K=Aru?ewUt)1Y;+L+9{rM9K>!OhR
z2&wq~aN8kcwb*oi-N)qQ6%?k2<M+IQ+?Sx#+Te<D*(8`wo<ch)8WNenmo2$;Z1Lon
zAJh-RY<yX$zNBR?i*NEFM(<#MKU@7Rp=6j;DC>}tcKmzL`&X$`-{@y;^ubog>tZ<d
z#QB%N>}HW1nPatefV=TxlM^%Dfn1h*!B!ApXHcYQ?A9$mZ^*@djsSM+l2u?JJnq>x
zi=(M&w_6iP2yUBl8tc^cafz<bj^nh*n=~#kKXy@>u^RK__SRwqwKYu+Z_B*)ru8o)
zP<A56WJg+Yh8V|6NhPsYmwEO0Z3#iUBAO!;7H0j8c3Ya-!xdidfnijCp1zk`bC2#X
z-fUb_Dl*P!zoMM`#$7U&uD0KtWg-feaZcJ(lyPza{JxA?y_ck8*&_@e{a!pU^eEXv
z=k5xD<YE`le(|&;;4Nxw5)M&q#m>v9M@V0j#zUr|^&(i|Qc$3+TV%HH=$$6Dm5*GQ
zcZ5v-Z;b6xKT?~x!ddfXUPs~^O$CMI4x4`L+?X%Cx&ZuL$D(RFU*iK83r8ciG^wa9
zYqfQL?uA9jK8Vu5F27Q3C0W0`TaAqjqipF_`QW`j^5(FVrHo}$aCYpb>yyAtQn0}v
z<aXWh3q&f-4!c5|gg<$9)%>SkmxmT5a+3>W42fF4LJJNT*>RMu{-L{EGEcdsyIy5y
z?hT2X<Z~bo-TMY}vp?9j;2va$g#-{liRFsQHnk~3oq*Q3-R$J3e9*;wcsa^^asxI(
zx%p~qI(flUcaSI|=RYSl064E>G`_LT#!)P7@YZBCz$n6|^hcF(X0LxMn<t++)8;xk
zIQ;B>)3v3k2yF?g$x@HJFkkzobP2=pW0P<>Jo;9PHF@;MYxjLS^JvR{7s4(cS>^yD
znyn^iTONGdHPr0wOiD24iUqERe)Mji4b~Vhyr~jI;lZ<9`t`Fb^N*bvEwbM`hL5sP
z4`mnaNtPKAzBu;!K{u4|C%a8LXrUDRq{lB_fHu?ov&1f|Ova5;cI~%SK?z1?-64Py
zX-#o`Kum6ZoLjSgzF;~Xy}H+3q0x;B%E>q^ee|~x-m}Pj3Y^tn<z6q3&Y@SQ`9m!(
z=5}DvGk<7P3YH&xZqxbl*lBca@#rKAigJVEvfaCAL5)4MGwvyDWMA*g;@zm>ef?RP
ztP=VTc&)NH${0{+M4N_qTR|Pws96!MN$YDqmAz@|CEme#adOxe{9ZR{znDzj(7dt|
zCD<3}Ti4#D@0%O8z`>57tk%b4I?Bf3?aRETivIjf;b+V-taEq*99HNZ>K#<yUU=xZ
z*PG|!sIB+t+3p#g3fY-qExWaVB~~HjCqjrfQt%C2Ytmh>4x|H-{3=q3+Wi^RYbV>r
zF5faxy3fm}$z)Pl_;SIDWB3`RTRIVHh_;>{VV0BQVM@4xTGE-sP!oAbwEN7l;|14l
zLMJdIG?O4R%Nk@dVb6wKQAQR=U(sp%VKYRl>(tjW;9vEmacLKS_?HlIQE+PF5?BUT
zDL%8Ib2P6ZKLLY$aJ|_fp^@YoR0A*Rvg=v%+{D&UQUW!xa5F2>(Z!>Nt`Y5&uF~Wb
zSHl)YZLA)Bt1b6XE!tKenRD1lybCnTW-aPMzB8@H2rWGiRD2+BHXYbp*rwF*lM#W(
zwrZFkW}`IwmUtECM$xx}+$gobWyRt+LMc?niqx5&iAY@;W6Ty2LuUd;E*ue<8t8Mz
zRHn#uq*exP_6%h}+gOK{HsgvC{AwKk9Pk(75%ddsF9T7oR&l+hy2>#zeLK&CwwC#1
zrj!}GPBKvk#`IVfGWM{F&U6tWO-Nzc5+;4Dv*(t*0SZmUnIi_I!bn1e%tI190yN4S
zXPGN3K*ecUGLNiZ4_Cx7y8}K|fG$@03f+bR0wK+9tv+FdCMew@Puylmo{)^xRAJi5
zZiafAKWV$w^drY^tzy(SLXUEdan#(R^y$8wI}Nud57M4nLv*tp`@OR4;um?+W4n9=
zG0D;zpAlo7dn2ogE=pa2^G#e!*O4^p_aeQ-;)A@jX|P#r7u-=4f)^s7ct#ZtHCdR{
zNHy~Xj7~hxbDrO{da6C^1+R6s;<;=p(&@nB!RelDABWmH<j*TVS`r!A6txrJ#H`>%
z+r;YlWru#XF4K~gau$EmK9|c)#;-Gvl3Ge9StdF@Y#SR3DLa9D#Od~MYY36gkW9u&
z4ZMBLei>d!wl<UbxVE6tQkk9G3LDip&R(ecTk_5aw8yxTqs)dpHwOftFKY$#KkzbU
zT7GyY)j;*ami%sIrs8PDipt5dz(~=>GVuiZl)HGQ!>h9gP%J%1J)@K?OR85*F?@94
zGG6zOTuq&61r%yW6l)jgkz{SLU)~!6oSl||c6>8736DHpg9$~A`QDJmI!{FvqSVA7
ze>`r&SZ-}AyGO2MQeE^~cxpOA@`F2k&~lnk$KA>pvo<>xNAbyS`pm$PhuZZ7ZVju+
zLOFms@~MAvDmc$C{gW%RfKECazRm4UTKyeg8FEg!R<iyGqfxZ5xVH$-n2JZ$YrH>c
z*E;!Z0v`XpE6MRCeRuNT-C(!eyt`iwGrjdpTRir8zLCsoYw_;)*Y)8WzEBlNlNLG%
z<=N~0u;T6Wm$CqGmz!E799^3R4oWfio54<;W9ihJ*)Mrdk&1bHz;hy9C|YTBm|KFU
z+Bz`UaKVG0=cm}J&QWb;wbeO!2%{%hCACa7MPP!%U*B&PG|;R0Oor1o-az&Tq=GFU
z?BfP=78k3p|38_|deWRuyH>=*VG)2@Zz;!QRZhel(kC>4xRv~l9jR)`<4TqrgMA_~
z%@G=tJ^U;?p%M0K?(Gd{<w-qMbeVp4s2xQ`dBbai-TUg)j{U0o18ba9wLz|Avd6!)
zWci6lhO9dO0cZ86K_%Ehn72!1G#nhDxj!DJy}M|f<7P=b+N)EyLs#>*a4Lkcd^YZQ
z@^T|Hl}q;uC+XI|Z&{!aW4Gl@;A7muTd$i<>hI1SK0#7@UZB;@rsfaDjC~<J5H(Pi
zJ+tb{8ll48ylqx$tD8J<t|jb9aoKVwEq!eR(7Uh~ATv4(A^|k2WrW)>4!tb~6!C7n
zkv-{5azzXb<yPD;t68rHzsF}%NZ0#qX!r6R8v3?9(QjjX<a!`nmV2o(OU!mm?H%;V
zJ$rn;$-yz3xeD)x=T?)t){e}3JGPTIZ-`|bUe3x*W`8&yzd~}b=ug^07!AZc72K)L
z4P8l}UD*-iD#B_+Cq`1jYYICJPoA3rBOl?%^)c!v-4F{;Z3;<{#q%R1mV3e$phc}!
zIy}^eMB71(=K<0aVnv9RI*xQjKTy4$=H!)VoxO)%zJh|4^sp-H=tUjN=O7ZA(b?re
z``55C<K&FfR72v*Ika#W0mv+NoF02jq@WZ_2o_}V#G>)Bm$`+w@=xKh$cutZIJ8+|
zFy4v=58ttLHy3sLx?hcXS_FcMV!G|^P7B`5V^RUA7?aN8i1_2kQFHE^lk>2>mLRv&
zcp=l}DuWV}&ON5`sd_!12L!4}EU|_J3Sp69->MN1INR!Q0wh8S#P<M+fYxr>9fc<+
zZX<FK(YJmy#;Gs)EaxeT0o}9MF2RwCcjH{ipmZXEJ(PE8i%vGUkHVR2Ce-HbYz2Z{
z`1O4Jm^VbLO$Fv%MArk95(dhVb;r4p89csjqmbxVmy{I@yFCJINiLLX8)&EE<A9v4
zc8Ln1)szotu@b0mfA~K$p5jEPO}I8wn7zYnL?x-=nvKgIYmfT58M)ep7dHvZ9S9By
z7X3<S+aOVM9lx#2B?`l;Wfo9QD~>)VLNiTjdDb7Ma7Qk{BQ<5ajX}Rr*lXQ9KDwUg
z<`N5R$?Y&*fIM7QGDjjli_Ara3F!tQBIvv#;Ma1fA_(Jzj+;}^zY5&C*iuX5hkAmV
z46s-lv?Aq14SEffi`JU6ciTW51cFZy+0j)|b_n>6Wg}DA!7E}9P^1p5CKW%*ZaO}*
zfS;S<F;um?3iUyr-zqe*&C2Bvg);2<32vNPP1fOrlc7j(4Flg}{JMc_BXrDFd?&Rv
zo#Ol58U?h8uZC`B@!BL7tB6B3!os9z&WM#Z4VrCd7$wQ&QGfL3u<0Hc4ey&b`>Y1e
zzr?!pZA5PI6=_ymdr2Dg<gKC!G^*T2^S&{~iZP*(#nDob4x!P~@{sV_pat1@wiUPI
zmxhb(%WO>VxbBeW-%E(~lZ$3I_!H^JhCG>`L~WhOSZzJKx!*XY%M0AqqIwrZv83Bf
zi>m!OT_LsH)r&bkR+;AM)F7<=4$~2rAqzoBY<G;{a-HEI_VS*<%e*TDFnkgRaO-ik
z7|d#G#%im11@u5F#^;=28Y|#}A|Xgcyl#27rC9Q_zdeP9y)E8xgZeRN;R`#1Q-S=|
zj$g3m&n_pa&7IGlgWHS1O~R&iw4NYtVpjb)Qro6`ien_tv;Nq*ZgKe8!j7Of4VIsT
zL{O5Il8x8(C=tb_bZq+G+pTc+BI_Kwz;81M#|}1!SXw;aj-36ERH#3TnU&gVthS~f
zKaVT2N3SP#wr_l4Le+dV+0X0_+5E_i-8b)SkzV*G(D4pCg|kK&P+Lo>fAzh|B#Q?{
zXl7ooHiya<BIBF!)b@8ymXC8sN6cmP^)bs~$L=)Tau>AZDTaE1@cHv+q~}vA^gZoT
zIsEnAnYQsNz|DwEl;pGI6fMo**TQRQsK>s#*!Dq@J^bwMn8{vJEfJLiZ4%Dj&{lL-
z5*K#Age#eT4l#B3k=ojt-)RZSra$}a?tJO<=ZwXx`n{5xJ`n84m$iYmJ7l$|i;3{)
zwx#OezP$L|gRwys!_~lQYt_DXVxO_w+!{80<$PYJI07VFBs=^`ONzOJ4<nERg$gjl
zN>A1D@s6si@1+y?G&d&hz6cb;{hPOOw+OMtd{92S0kl~0n2AI2vIIM2cq@nPZ`4HO
z^Ma*aHbO`2)baH-s%6|SVALpP0wPa&44_BUv56Ag2a>`b#&sldTpLF{`Z9TKDN--c
zK}=UPZ?>%#6p1UD?2#Q*_OoqX{EW1dZP{mk-G)HO?aS=n*Kx&FnCZ*>9ICQ<n(i>3
zI9txa{fQ*ulkV}_ss|=)hO?~`_KS0&Jf%CchaH#sjDw!%$JafwGpCbdI~f4b2@51;
z{felybML#i|2F57;wXNYTu{}P6F2_h)eT&UaPRtzof6085IyDG=PAJ(I5f!_Ar@d;
zIDMxgN~B~l)<7pKm1|aJ6sGbg@R34k@9|00v0!vo;7{^X@)-_gVrp5gF$%NE#YgvJ
zN0OmnFdk1u%3Z>UMCaO$tqjmI&lsDoxRye=6DhpZf>YW-8YpJ`Fq-%%VLpj{g(uK;
z%BvGrnmPh3S!kxwBc~2!LQ_jl#Xa5SJ6@}njz?)iG@R<w%~c~Si-`~A8@`Rrtc?ne
zS%{LFr^|=u2x-aW&9P{GU=)#3FTkr}k=oqG+uCTWG!coo<(OW3UHEPZEfr7)$=I9S
zzfNCpD^vB=U}u9emkLFYX>dcrv0E&?HhDTN80g#O)*=GsTMhofHm;|W$<Ah%`Qxgt
zgzhm)$E{KF6Ls!eDxg7%ZD?RlNS{28rBd}gaY$yxV2}gQE{@(L0`jP0Yz)E4|N4ys
zH}GY8A@Z5h{yRnDZCU-D`IZ$8Wm4ez1%yq;<fvKJrw-T2sRvsIo*%TPJNPx5h*n5X
zDr=r!6MjZ&SVCg{n(a1~z>u>FWe$oXpwk~_D2onfci=9MQWqt;z{gE|CrU70Br{AO
zMW35BsSpyUi3>4<XT?eAX%@(*s|Lq=eggDh(<~HDG$bs|h;V{s78F%+H<pmdF&?Jh
zmOv+%f<Vi<Y6Cpq|Jf=D2;+GGS*2k(*n+PTs9v##A+R_TxkfEDKj7QWHE!kO+P=LT
zQD{OBq#N^vz5VJ!>T3|9)Y|zftG*-Dwb}JZ6SrD-7x08j{c{J&prf6aorKL5yKFK9
zdIvU|{fd#XbiNPVGA+x*=?r{^Ni4zh7z9UBipnH~*tw)ElwEY)8g?=4MFMVu2wQ?f
zLxixwP-hR$Dt>|5YSXN?lH&6K{~C~2pmumWkI%)J#j@Hiqtm|cPEo&^V=Hq(U{kH>
zHW*0$CbM+;PGqn%t+Q=7?d(l+kwn+WTTPpUBXt+vca8A538biy><p{FOS)w_Brj)7
z@>gfr`11Dy$->1ux8*u@g~&>n3$KEgFCqA><F&cztO-_Y#@YOh)mHj3-k3;pnL}LZ
zt+w=b)K;@MR%Wgbe^gAM!FC9pIb|)z|E#taSv`gC8V;55f$fNgZ@A1~#_kFlKoJf?
ze}z4ihdJ{n$d*+-dWDAOuT;3}z_HpIPSoZ~-&LO0VQgS^$=yf1M&YxqgD}v((s%kD
z+gzb<+3Y*Y7)9GUNv?3j4=>&+b*OmAKJrIi>uAL!dYiTlYavuGxl@_iAj#4zJwMks
zP@w)Irn!G1dP*lP(${cY{K+&4t-AwPGP(M#^)nuOXg7TwU)h;#w9fbakG+{!xR~LW
ze(JYp>=nOG`A|aL;K5pbEGyo=Bk@NLS@q^0Pc*f4@3#i+FsrRLcV3l-|BiI_-s;1a
zxWF(`H2J(l;g7*3tE~&gQPftS_1TD{e4nCiD*Gq)Sl^?zBTu!uR6Oe#f6**dL=)QK
z%zsyKU{wB;+NpoPhF&ZV-eJit)nF5l?j@6D+{pRu?b7I|t^Z?>?TrB{F5zk4vp#^c
zSlbqK15s3D;|Fjan=f+^Po^r9ql(xSqEZZ&7iRTmV;qMyy!bz;0L_+tB_?Y(e#$bc
zR@5I&C{dEJBFT~R8@;BdH2vb}v)pX>*j2$sI6wZ``%_0`&uZ)BU!HxYojj4-W7QWg
z+!|@B-puifrQ^bD*#`O2VuCWhY09PJLK!Ze9LP~ygK3lSLo3%XNY3LB;E;c~QmcXz
z=XvIOVUE?-nV>7Ys0^b{=?ZdIvfevt^&2nF7D}Jz@yylV3fgMxfPEp+2eT2fc7q7$
zh~sI0lvJyrq*}Q`dWCuWtDUh2<sbzzZdJS^ushT!v<~D;Xuutq<f`q+&v*A^G1>5c
zJ0JJfbTB%{Usv7pVZyIEwz4G5MK<i_Yq$_-Tk)V>6Fe{4Vrjzn`@NQAzu13|EtcB|
zOeenA5k1D~oqKj$pS8Ri;i4Xe{h_mLnSFspe-Z2hiBGJQSFor00vP)B3Rj|Qgede*
z3|CeuGj|CEJWJTbDd8Qwt|lvR+Dqw~q>Z>9t0;x?hruL>!$FP0w@ELR@%56U(T4{e
zi1OPTFvq$IorRR>;mJrI+F|op7O;2R(L3|eSbKyu>sGcFftj|cU?x*MU|2cv<0Qbm
zoi%ZnNzKdF0p4!1W)g;?RH8GOcQ_)r0MiqkIjMspXdALRJ+_8m)>7g#>(OFWCxk)(
zl<xC`V;r#Q#BfA!pB++tZ1aSUAx2~0KIJtLk!X#b7MGvhMrk1r6r|80^gPVA)MAXi
zHn<oqgDL=Ej70hoJ!!U~hLVcax1AW$mwSOwaf_<AtdWl9j0$}x(g2C5rOnOTky#Md
z6_`+_S#6c)L?GJ?x$8l$u@ot=$Moc*xFXa#7S>!^vX^Ydd~|{~HbGIg!v>*VNnglM
z#5}*QutW}m@t85EwL->}Wt<$NsQ{6jl-#7s4}k0;9#ZLO^2tfZgA!6oRAt)irM<>v
zQ`$K@P+83;zN7_=xBv}ckNA<LlG6KOwt{6O>rg2`;T?vC=fxRu(LYXK$y3O4;6f<n
zStzG3bo{9Z0Tc)VO2o^O@(XfjSR6l_!&nW@a5!`TSYC~kMYRN!#0&p*5K^Xs9E#W#
z`qwAdA>592Gh8&Wr)M*X*Aq2+cY<UR@1dHaFj6#SygqjHqij>ksNiu9CyIcvFz+Jg
z*fYZMD}+K2TT+~ScriPY4Zh9IRz^(LNS55EAlA(V;VVOv<`f_WmfNZ@NhBuAGmr>A
zll(lt7<UOX^q{hW#t|B6pc7b~_H*<(Y~n$QEK;dLVol|3DM_<{uVwt4EaD7-P;7J|
zCCh0VWZ|1v<;`S$L7aL10EM(mHaoRvRp@ge>`>O8lUxVsTrA7tLZh2~9p5cY#F5jx
zMPAgA9ge(|x!6Y#0V$ho)DX#fCGch?ftZMzW)LTBA1N3pL}jkFOf*g$DA|@OH>*VL
zL`%k%XbdQ8lLaM%sLd^#nyDqKvR)_^tuVEP*Cj;-w=yxTYxJG|^rDQK$6>+<P)^Dq
z@#FEaR3df!NR}|m8y-gmNsXS29SCE1qSQc{gIc2bU{K&J1-VVv)(s(uy%8*@K2!)G
ziDFp@D#3pR!2kar@O+YWVi2je`w=XNY_%d_Ed_59%huqNh7dZmf*k8bE(*NE8N2*{
z4V_`uCh59O{I~Ybh?b<}Hc?Aa#TBUHMh8ptgsBcj$@-2+oe<PQCu6g2C<=G5M#&Jf
z8^j(Uc?`5nvUNcbG6rEm2_!92QyW#XX+ry8Ltk*Xvjom^*;2V80v1^89XiM)MEfeC
z;}<#}r<<#_Q8-@VVnH(+(ISu2L4xfDelr9KAZAT{qgQT~Vpphv!C~C;ouH+}fpQCF
zP|QANo+ne!3znuZKyO#4A_q-49SF4%E<AU-rK*BYZX+<?G{%;C_jLs=()6LKPJ#*b
z+y<Oeq^2HxE|aVFVn7Bzdh?o+<=w}x$uB0NxIx8|5f>sb&;_zeFqfniP?^Uf4$-5O
zBs{M^d4K^$;eDr{#z#~^<qzR3U~Sr*1WkWUvQE9Tvaj|Ksi7g_8{|-z4&9z=936!N
z8N%fNkyx=uN@RNI6n2-a&j);r%;^5WOc~8FIB*X8RK<sY8PuL6R3u(b#iz${P>S*?
zA?a<{(#F2IZAPQD=4dsv;ZY1}xo=&-8VWXz=GFuIOV&F#vxn<oIBPTPY%mlVs44mD
zbjA*MLb4&?yB<Q`nlbOrrc(Ex9aRw*jNVDdt6O()Ry38O?K@FMJMRP~a4N4Ilv7L}
zlhbEP)`9QXmyr3;y&YFCW>`%#332?ONbutOFeR+h<TYIg1vcL8+m;e3GPX)hL0bV;
z`4q|%&y5LVszBF)wJh1hM9SR5*hKU><xxMywW*_XAUB^9!{o)Q1}XJ+we+?h+bPTu
z$Rcma1$Nr7*X{@6q9wGUiHnsIZcQsa@>u=LHqb`d%4iUX{1={!Gie9+n(x2$)O*RE
zi?y*^nR=l3EXBDJBF6GLd{W>ROY=u|E|!d+$i!~oN`VlI)$F?*)o)x-=(I*+Ead1Q
zg$5i^L^8L8>1W1i==6&ALL~UDsn~8}jN?#f?MFzjvW4*7?YW)YhL}HxpqKmFW&hrB
z+tu3dR})D0?Y33<uKJ#Caq7#5m_H0QGc=#xcD2WC^FM?8V@W>V8blSD?VoY>eNE?<
z;AGITGVYl4MZf0?HCl5qe{{jD@q%p8UJg@V&Assf?S<)u3hOv$n5R9L6dI?rzmnwU
z&+AVQayPT+_nFU^^M+2fEju0QbRQvlW6k&f`lBM(b}9~}@ZpSNQd8;6&FR=M`&ZA?
z{odyalviNiQ6?DKt(NM$3*`ltzZv4TF@<)6F!=Wf;z*^?=M`+<GnL4zO6_AGq_bP*
zU9;`g!=s}o6E37hjbZ;`5fc&0(XZK*P#8$X_GZf;OR`dmUD9p&m*iRXpVPCN_f^9D
zD=YEke*eF<ymi9t>RYQ;|4-i=3VowTz0HdhTxE{z*|v*{B!9yEY;)MMbZ8_ko(Tn;
z^@?9ycxA9xyvybn_Uz0?2B&i8!<mIoxh+-IKh$2}JZ4u2!dSQ|B`rX?Y=ggqcf}DF
zB9|Yyy2m0_OfAMVet%3?rv!aMLlF1Ub&AW8#-vtMJR$xQmwNSFOy#|wQeQ#8iaQdY
zM9-s)N8+wM1$P6IZK|C5S;$F69SHpI`UuwtDWG`=9ayY$Dq|J?nNJel+Gfq4_#|Ut
zMSwGZ_Vr2HIFT2V^5_DSUI<ix{McW*taU9ZP-aIbJmvM<mVM$pwBRrE_UV5^AGy7V
zMOebsvxcFwLVDMQEKRD_&JC1r5UORk9?k}iaGvc*k|pk;%i#>>)5@feElVqn4g%dE
z_rj<iD1{s3XhZQtlDfv;A@()5KMm0d+1k`%45JjSiga#!NtY2AT~b^wr^bfIw4#C^
zyD48L11Jt;i9M85%Y_^*cC)mjNQ%}Cyf!LE>O(B#bdJr%SpM=bz$$$sf8<x&z5NRQ
zf%>D{qT_8Z%|D8m?Z;U~(|&Ee$JX|ysOmdOlQuDDbdeda#F0DIO=UlsOpjg37Q*6f
zt{I$*gy!PY=C~c=gJa0zj)wUUM_D{zPv2j1<|iPUGE3q==#?wY)lGqGO|}D+om)v|
z%V!e~f?}Nldao_<YpOoBWq%67CJw#Tf*4l8dAB-lGPl9Jy_%0ermC`w@z}0_-DG#s
zCRZ2mgoh$NiPfR2Nb0@h_K`N0#M3!o#>s*ZK$kr-;6U@GRmIf}X!mVsrK-vuAS(sG
z(b;iQn?QzvkTUtUBr{EI$?o`-c_%z+ajiUvAy^+*7J#Bi^uZCyEb!)bZTptS*6$Fw
zinH(Wt+OSaPGGCF1oRYNgtl*_fxzId7~!#WNvtruwhxs$qfX@1a;Y>D<~%>A;nFo&
zdXX-z8fmb-#XK>%g`<=cc3Xy$@|dstbU`tD5DC#^24UpK%{f^FK~<TLH~L5^dTsUy
zl6W~GEHf-g!yhU6B`9fm+<a6l%#ysCaROT<P}MU#3CkmFJZmufqB;O4mJJ^wQr505
z*`s(hq2)8XfL;?Iri+#?kA*V)+(`En+_ukL4&B-*A-y<=R0<gbF(t9l)+^q_X<1EI
z5dt>%xO~aGAOt-rV-azy!jR_{;Ds2OZedX>f`)WLg{bpsl`Q2s`6;W5diVyv2#Pbw
zFYxmvDQug9FD1Me1d<I@r<~Y9iS1WTYIHRhGf9ygC-C>ylgS2y;$$;c;eazQTi@oc
z{L*M(Gr!R54V!hcxKW#vEFx#L<E~J4mbKH4d&6gH(<hi?L*T8UMpr`X5WMV>i#5;a
zSHMu58Iu?yL@Y@YxGpZQNX|~qqk8lVQ4Aey(EywtY&DLQJfo>LQY)6ZS7=j@4ou1d
zGu~nL)=8M3R^Q8435$tKv6Qetr7(LlGdzp(AhUWogf)^dQrwA*7AbjKAgC>^#-c3T
zx+%_D`F+ep1?=jz5^5qrdh`NhLlEM#{lG7=aB#1=?YHLkrlaqS{ymb^W<J32yEGnC
z!?JwN+(j6{-udIMu(w+0o?rZ~pb0THN{kQCqqfFIMTEYf4S0n22ElI2>Y#?QzMSaH
z5#aUT_|?v2fb!~jc79pLmOrOYLJr#z^&tA3#cgGK?rg~Mx$W}75!e-qF=jchU>$97
zaN?%hs_G-7+M0&DZQ<h|GCw$*kihpT+AK*r67<IH9#d@fl%VI$Pi0HQYg)GCL#eh>
zesN^<#L&rDK&{IdmsqSVtNqYc%=t3#dbb`4M({^%&DcJdhYPnqGzsxjP}ZZLV$W|+
zW9mMINbxLm5H`E~G(rfCCIe7*2(B%D>Dm=;E*T9se*5D(Ql;5bHdL+5nYN8pW1dc-
zzllTNPVfpN*?38*?5Y;$z9VH<V8xcVy_YfDlYHCuem?qw-c*q6ah=W6{=+gZC+pN6
z{8I9(rqbvJdHB=5t9<o?V|gPV3Jb5S_)(I-|K-+vpta2xSC7qy#`kz9jvjT!Yd7X?
z#36_L;Q6RDGj`Jy<K5&z0#s;$KJx*6^`rJK+GS;OCM>?wf+wW<<@0RnOe_!Z>qRC$
zfQZ^^4JV5P(SgV4%T6+}+d9-2`&2mY4o=c=pG`8SZINe`YU_N9(v&_MCjd|^t8KN_
z>1z|JhrT%X9n<#Czl)___B8=QCq=Cn(2XszdaE*oGj3Pj>*Y~AB@2n8e?b9W{A}))
zo9R+2-FWC(B#CZpk!9?0&S^XK<K6y@QzWq|2RAKq+wu50m3+9x48+0^U4Yr*1o<Jr
ze!EB~YG20Z-Z#v9pIo#$-7y<TQ)=s3dkVg|FqiW|NYGUKGC1?2dsACj=7TZ|7g6a6
zaZ^WPaps~ckFMZ_G5sFxHz8+ow4tE2N^PuVH*CL0#obFSDQmrd^BlRXgz<8lp)aoj
zMcygho%VF=Je?p&Np)EAto3&oi&Km)wwcBo5qhdgU^-1Ss&ooz%i8a)s*=#TyQt5K
znA<hd@_!go`|g+xkgU;p)>2S9;AC-;v$uuG*q?TSHZ@o1IuGozX*V);Q?e(i39&w$
z4JRvDR({C_!*5Sm=08fEan4iJ5qw`?e!aD>bhuLTSXRhkUJ)$`WQU)i5&tcX$?qv6
zWTOkwa;)=KE4{lt-N19pETp4E`U1asDpv3M4G{vrAy+m6iMIsAM+QPC9aoBzp+@P$
zBp1Dvaqkt96?lHDk>#-^bjX6_xq_|)XyIQZM@y&DZu&q<p(O1=uxwh-^)T+m>T`Y9
zV|477YjKTHrTUwcaZZ*_mO;2760_2BV33|x+XOy7%YHGT<i@}q43dVzIYL_0n?gyc
z+%-%m$6B<GyY$`kDO&Z7T4KzWx`uer5;KUq9>Ir9GYX-Nt_AKX+0_gob1J3SHs_Tw
zdi_=d^Irs0=%LnB)Q|+Fp<<-^w?QHbiPN5#xnK$>#h6L_)*xtHGl=lZLRbsf&^8#t
z1Oe3ghHnwE15RV{Ml6CrElO-`iS(4k68N?*oRI{1A40*8AyeBCSObJJ)X`G0u6@*s
zY7-CcH)#WOCp-47%t)|7HckbGJq4Z)-z>AS@l!*$c9l%7$LWZOoeEK0AqJ*A;kQYZ
zwRrH)%saiDA|Rx(3kh~@_m+ll5S)@1jkjY_I$3}QvkM_+5=RT&p`#m{lC75F&q}Qe
z?qUbQs&ByB1sv7HLg<KGH=V`%xe`UDxae7n&>veIl$xLtqs))0T)0Vfz2b)$`-e;+
zsh;FGz;B|<Zd^m&0#;ikt=@zoMA8>rP#Wb^4NX%v?3TkLp?G7t#I)DrZDxlxDq9;!
zKx&wPk}5kNXl?)=-?e~FYGDJ+)4U>*V$7BVikUT(RZirUtxI7I#l}|c5b=E4BY*R%
z&*m1r5+ijoRs<s21P|4eH}NB6%E8W|2XF{dLd$AR(TR_$jy$eHsB<;HswP{G^;uON
z%dzW9p&7f@RuQ{eSlS>Pg0@jQoQ#F$mCcYYk6C_nXO@v#&k%&HR#&qXb&Nnco$sx+
zKROG&`BRisv^1M8(_S%W$6r)dAdtd~4(*tVr!``XE|0)kZiaShqR#=71hGU2_7ALd
z*3LwM&>-!e-H-Fp4ZnIxsYY68wi>pqhf$rO=mk6jA?{iI46Ca%cH7k)bcXYvv8K-E
zz1_XT7xu(<dOLsys)Ft`UY%3?`+_Ua*#%)OA@GuGaG(#hb=bbji?J!u{ca2~*Sb(L
zecrG^e?3=yr(H6!lGrEb1{@ts4}H2PUA1dWuRM&EtF2K3)yOD|!+rv|NzzNV$il+!
z)A168Lt&YpUwWy_B?S4nu@_q4*30hs@nGjam)LbjxRDa-;qqs84<ry#)bpOOT#AFV
zWxMe^@Df#;52h$vb1l@N)XseauN+VnH&KuB=<TtalGhdhql*Xcq|IGPZ~50(g}`bn
z(7*I@E|KLXn}zCYvZdd;vp>>Y3Tf3vst%m2au4?!`~_liY0X$|t&^+^wKuvuq)@-&
zUC8^B{|gi8@67#G;QI#|zlyWKue(6laxFv~Y|w6HS&QP6pL&!1JIW=rd|z+lLJHm+
znN3AXUmeXfM?lA@HBC(bM74ENX|N3IJf_pKry5pVA-#54;>TA_{p<I!*sVxifjW7h
zQyJ8WCGFMLMUtItYs<~%9seGY!_PG_5t7wH{*s7C6j{XCjW@W^Xld@G3j`QF{s3>P
z`EzGn?WE11wo3BFQO>qD2B=|`vsk|PKGzj%;5qH?iFph4rBDwaCU078ohXJl_sDAN
ztk0Z3vfCVL>i}wN8fgAmwl_=0i9ES~G7h9$9*2Hgf;jW~pZ?pm%Fu~X)Ne>Vs@+5O
zcYTW#OK%X%4Ah_;dOE&_;w|Id(mO|LD=>mStAeoAk8adJZFZEhMFrW)zhS~pk)8(x
z;g+f=`*lb*jlC?%W{2*M{8-c|(T(G3Yl=~Rn^zGde3TdMF9*$DcZckY({B5LZH&o2
z=4Me_V+{ApA>8>?<-y5YnI*Fe```!2YARg85_NYbNv!qHZXuR5tF7B<UYR}32&chV
z#81FgI+*3HLlHr-ntDW#WV?a#6%4f%YR`qyppxNHRnLgoBg}y3M0kxEkKMs|>`B%-
z1-x05A}qobnGe`}S**mSr}TLA1i=ffOt$PxQMqjbKgZ821LQG=KaK|w;!}@A54aPm
z6OSDwQ~sMnPD>-M<8(=w6dDUSUbJ{Ey2r`atdfgk`!-)f3US(7vjRdLJ4|tVM+6-E
zhf#uqP`vm-FMLc~0kf-x>7u*KWAoPFXmNa^D<5k2&!t4RBnJ!pd*Q^_NRSOC+blJT
zs*hR1?Yu&=29KEIxnxONd70I5`Tm&o&3P;>ep`d`4@5f1GJ@kNxgLiitF5VLYvqxE
z947|@w|?;=L#PgJl|UJ(&7~V&LT&BP5yHmcEfA1;9)OcV7&R#`C(+YuKwwNg=j3rQ
zr}bodkoeh9OG~LbxS5Pmk`tIyD&Gb*zrg`|P!{VadA1>DF4{er*cv>+!f(W?@*La|
zSWr)NZB{b$oZwBIH(9pS37YlTB%eHtPj)=RDV7?!bo>m(JM#o-Aw3W$7#2^EMQLF6
z4lP^qU<bHopq3SKs5*%iZBQ<U^>P&?;xOI1MCh3iHj_f#fkv99`%1i)PRocUwZ&UT
zGR|tDNZeSYosv%<F|}A#VrKEX3|jT@;Dk4@H9dO;VL{`zLF=1n*l6UHLz`>tG~li)
zw1iQkqflDwA#mX5+7WyPSogbieaPl^XmFUT?2k^t3ahTr5uj^pATvv16NGFL@fIJ(
zL8i*;wjfJ)crNR7-HIgU3&I|humct+bD|7vr-F|d3j9`qF`b`H*5tSvaH=J8$xsj9
z29H#3ex4#@11O_CelcZCCD1JM1(H+MrEAudqe4P1MFVKWC-xA2FBWyASbBElC!)oN
zE)OdqJf~Qb^v<~}`x*%=k^@ICT8puz&56nHtm%NMzRf7`Z{orgSx_v+9{Ozg!5$0m
znsORYIpf;Wp@reNKGo*scc@XfB{A=cyD7Nmgf#4-7Z?c_Tyr|->x(gXFsiLsD{gy|
z*%f(+S#J#nbmLP+#?W>5b4YIFjFI*}%7)`5OGdNV<njIGImWqxre!a&i<|$HvkUkI
zv9N*|Y6IOt^CKa|FD%ux7xCIy;Dt4QJo~iPZu75FvaRoe{uT3zRJ1O$n`Kdn%iJ2u
zY8|*qtE_r$>@3FJ^-h<uBAJFizi1>@yRB)pLtpajnhuy3PeL0`KEG3YnJC^Pm3fux
z#F@`}H>aSFTv}vq<xIP3-?wwS&sAqqdd^8FT&?S|cI(#Up$MBmq^>Zihs(bon~GKj
zvk(6hZ7&9#pVgGh);G7!jC53*zJo6%k)I0_QxSzn?W0pkt0%P;<ZxDIUqWrQL-~}2
zZ$$mZYWIfl=p)-+XVuSo`^;Y_>3)*ULvv(kL|JiUe6o+Jk<l5KPL0kxOFznsf()a_
z^UAog$S-*ppW-{X!@JqH<a#rO@o%z1Ean40Yw58y_&|8dYAfvpNc50sfZu*Eq@FbU
zllE$B^z8cBb-Np)GSKOr?_&o=jMhQs$k0IjIFlPOjd-WZa>c4>Y5J5zh^po{XU|}8
zLxh-v7CH#xhqWF+0=s}@r4)x!ZAH7^#!C~SI|2tN<0g|E+42Ar5NOM-;b-}P2htqa
zaeI<qu)>f{xmW$T`GlU`A^62~j`h(>C>BWeCXGb6+4K!4sqFV{e4<E4>)*Mvq&btE
z5vNLYVx3*?BVj&kvj3bbCmgG-d=Wi!*FH=qfk5o+m-8l0vXMM{ICEpjtad%OiL~2=
zO>}1r284tt-D+hhV=Wc+zT$eWrt<j>)XAOzj;#3>n@exO^3E4%^i#r{KS4h-$VCe1
zj}hWBEK8NTq*V7`A^8_Fc>c83|2wdpc<ue|E@34bLCFH4)8EFWR80=buT|lBHmAa$
zN{*D9gs&*yt7-GR+;=!@2|3fH(%m3Xhte6AWhNY2%FxsW>B`yjsu=#?<oW<`==<I;
z*?1T)>F_3Xt<tJzHj#}u$IF0WI^+0)V-IBX;dztVIy!ZMJvu;{(3yskv!k6Ba)Pwh
z$ZTwDiHkNoS9+B4=&UjqAP-Z$0Gz;==b_PF5eJj<%T#Yla9*a;J&IAs%$$-ibGC$v
zw~9z^hw<n^z9Qb{e$Ej?ZGAO2j%l=2hh7g(y;=F5@F12Ti}Jb(t8A?LoMv&cHRzqP
zudcN&WHcU!ttF{+p$aDi)SB(6r9u&K!NY3dINXDt^ql9tzq(S4@31na%vgpRTmsW8
zzO-%ebfthd#Bh@KAyQ)(mERC!L(f(zQOBr=9e*WCD0tOD!{KEI@N@j~{yrqx0NvAL
z(_|@MweF5|7qORs47x(6fMV=sI|iLzcATi~N*Vh=4HAQo^uUUimTpfFtNKMkT5Scd
zD`d<7f~n&0Wg?KM8Iz`}NexP>{azPNNk1mwQrq2{L!Gan1+lK@=SWN!9c0rD1|F<l
za)qj;*SBm|0?BnWvV`ruDAb^Kq}YkKW)c$UALyTe=cT$%R$N+Vg8~%Foez?bGJ11c
z-o+FSM;RaM6bEkePETMd2(JgRMr=K@ROl6-U5|F^ecOL9$`wb&Gq{zah8<LGh@1~i
z%s{LOOq<aI#6CT}N<e5^LM%I<XO~(w8B|)zAs_?(l?9_+dQwqn<}HkweS9HlDsM?j
z02^F`wlGWtRf?<%p17Ihr~G)`>yz^Ch_Fi)MpK?8<+ksJMltFUuJGyeR1E7NvFegE
zKfUfk#yI4~>jJm5j+t|TwMHS4A&JTEmzYY1!u|&K=qnE=M+}+5;yW%S-EL;`+8T;1
z)?!@{+Rld3RTrS_!G-4$Ci-laCc)|)<rX*jNMucZkxiL3u_-Q?@aYB~GCo;s=RkB<
zq0bswfD~`B$jHbPM!^B)bb)*Y@VxTp@SKZM*W-|?T@-}v!`;%S^(IX{+7!NC|LTlW
z=xz;-kb1_79^9a6w#phVvsV<81MfLw>K3epzro3CYj8Bbh_Q4vTL$^uTK4J4!=bnp
zS9GHCs@s`YhTVnX1z0{uojMY~wMQsEB`gn-ot<f!$F|?5hEvFU`At@N@M(3l<tQtE
zPGD_;^AO_%oV<*Cy}p~6Qz8MRbonaKe}`WO4p-vLrn8&-@<UzI9?lmuE=cWf5&n&;
zATLuH22pb}mwAWjvnGdA?P*5)j`w-us05VfWEk|uR<Ug4+iwKxqoFLR!!PqF!La$2
zJG1LsJM3~h&_A2qzmxSdgfn-PjwZa(`fzlC(As`7^^LGAG?E9By=`n5V1aMpbHQql
zR2GrFHE(=F=t8O;tXlrfl?v~MU+}i~%RYL~ogW-3P0D?vh23&x=ClmU9#abbN=AF=
zB?}0I6+ro58C$7nA=KJ)FOkNUkK)k5O7hef??@Y3=R;v~FdaU@^{wbSwZ>CFS=jz_
z3fp(GFZ(bHq0*bmt*s;yE3-HA2Y>HXV=5RQ4)0N>yFlFvZWQQCpS&Qo=BLOvpM)ef
zqa>8MrER+Tiw>emV#SkZ@*eHu)#(^k_3<sb<a6|X*QM6@;kKoTyI!qPoYh+_8YOTx
zI@U@&->Mk$lkfA^I95^Jv6<ng`<)gzSKHpE{LNZ=^3Yipe(O?8n_r|FB<gP45g)re
z8z}xOFS?K3kp9+7UrArk4IBsyR}@a=6y?%B+baFB=tweret>BdFt1y#xT`4zCpl>S
zwfM%$ZcEVHYRY6h5KAPd&@I6cTKxl4ITZ_c49u#l@+wx00&RJkfTbbbUV8C?@>as+
zXD^7Y#(iySTX>x+l4#h=^L$3t((^mR@z@fS3jb%Mhka3d^je)b20w(qeAoUMpuE}8
zH>=K`{*m{-Sq+vJtk2v<|2lb<rBD2*8ZP+OkcIEOrp|>+nQuH^Ns<RIk5`t!d|wgn
zx-7HW*SI}}+@$^gXzt&#9e_l;KpI@*6^UK@VmhhftCZ<F{91z-#M}kJk{c4AH#knx
z74*9BI}p(=+H|76hOOfQ^v4DoXsLodvSUbsWI2^893%<>sD(W=<!g;<EECI?MPg@c
zcM)ULhmt+|>RI|*YuO{En%Y6usnb#Eq&oC!tslBe330Zsvak?QKD$$~O-Z59mDhsk
zK%XyM^xFL4_ZOv-J;)p{$gcf)kTm>!j8x_=A?VT8Yl3HFL?RP@(pXuyk^XUO!l|d8
z?fUjMtJHtPO;^8_xW0PqaU}vaF|`<X`e&-@w{5&Qi{Zct3Tktn$`HSOA+?|3;NIdx
z+@bj5Q}OAt+)+y6MjCN=i8al2Bd2hdi~~k__Xa$990DXoF_STDWubl;yN5JJe3r*x
zW0)9ODhEtOZ^<$;iQoQkIvXlbqXR<uz|df$ZjD8Gtb)_{N=!u<WI)xi_h42-2fJt@
zY{<l8Kc1E54#}j&DhYuRrtB=bsTw@_s$D>TtWF82u#|d;5`PRCdC9584>>GA#W~M&
zOunc}4nxDhZcqsqgEGtxY^5OL?E=7ru)~<)$7ST5o*B!QaDaD4%EVD@10t$Qfidf$
z=Ee4<HZvJXY!9gjE7Xc<JyA#|9NYVq3szf=2u^%-h43{Co@9$dd|M-ZNgJQ$2?s@E
zkpRSLqpK3Rsg2=(%*Oha+9}`>T=!Ii#nNlRHUm|!w1UVi@{6&(TpFe@+!?$o$B=cp
z5_}w(frEZ(`DJkC^m64Z_d{2|8<ZGZvTKq3N;O0!ksA+~+(gO8zZ=vGXhohpsHKkC
zjx(A;VUK(>n;TDP1f%Vc&5bk$IdSXYEpNr@5^ONIFy4taYU3WeH+B4q@i@QOm>gzQ
zX+ryT;N;UCAkqMfn&df-cu(*+9KS&u<Jsw9vA|EPwgp3p7y^p<(iR&yj01r=0!eji
zXoe#~;7X>uK;~ZsryqT6%u<3iB+g?1nde*EC?_HDT$@3NYYP<r^rz>+V3-?*;W$tt
zb|)V8(|U+gk&1aziN{ip9-BNIm4r3r7~?c#m1N|S;0fgYsKe3|&=JF3WMf7qjCFcm
zIfGq869yVfV)>*V5q#T>$*Q@Z##0AjLz7;O?1zpJB97$YYCI;RlcU}@V^K4^rt~oL
z9SdfxRL;?Qx+fjV56B>*EbO8{9q|pqy0Ir_smxa{O4&3IO<4|5`POR8|4ZE4fLT_R
zcfRl5XV>Z7)kU+bx_}b-SXETFB@#Fy7;F(&6$O@v-UGIg@q#(c^hHqT-cI}&ocOV-
zD6m8>7KC`)j2RC|l1>j{+6<E+#xWbjxg<}=r{ieC7;~p$j1M}R+i@@<Uex>huYFE+
zb<=fDnVILAx9Y6DKHl}NcfITLU2E;N!SJgt2Z~cnSt?+CDOwz!7cz>_D*(}m{_7de
zseY;>4$niGKR^;%E8qYBhLGNnJ|E-wD8h*K{pL-M)pqjpwe8}oXuk?A=_VUedoTR&
zXY(kQX;Nx(^EvZ1wsc=xKSEGT_u#Sq&i-pi%d4^6wBRv&Ls0Oo&N9a<tp1f0;*sj=
z+4c?eVa%2|o9vyC!qOEbi~O0k(mTMbPuMEybtZU)?XTN`F2cIcsYT?YGW`WkH#`Cj
z7>*hurvkcVmE}*?ApXq-bB^!XgpglFxjMQH+noL=SbAVv-fsTI>|{Ke=eHv=Wq;ph
zwP!YB|1{;RJ=?f5`oCmF{X2Hg>Sx^uT_5sf20hw&CS1+qvHXJ<S-$;HlKpbRrrO*!
zysmdV%JFVx26nQQ^5kTU*?n@!(=pENH7SShveJW)Zh946^S9W5x@X7S){fdb%(3Cz
zI@^tzZ9g(>>F%xc7VM)PpUU&xBpWy<I$0h<A%*&8l;SzC!fn*7{QVU53R;26VBZgu
z49(A@1KNngqxygc77u!|^No5_$oyCK*Xs*-_J+-t1!CD9XlCv$+zGIIt23bS%+eeI
z$bpLb(nHhiXMEq%rDDLfGiObQ+G@M!T>JVD<u)76G5h}6%$am*`recIcFG6SQR#;|
z>^(j7<{9l!XX)c-7umrBn<b&PNcV=}eCDZ#i2v@BY}pAlmI6=De|ma4xcuSZ4~J9t
zyKjv<y!%7JmU22JyttU~{ul#hLO=ukMTavXfRUe?@?T#^qdFTU=UF>EIP`%e`{uzN
zls2biRq9f_QzX;BSd~UsDYh4%oXu*tmG%7jPC$;BmgAoM8Mk_;GH(42T`-CGsA?(^
z5@smldL(f+d*_y7wU1W731QK0o^uNg`@+k!#`5bK7-3k<QWf1S&sK^t_N_GAx7pi(
zU#h$DlzEZV)?l*>S3dj)R@_*g<mSJ4R$~~o^>AxxWLj4;S+Qa+5ZTvXne2Mxsl<hG
z+Q`+nFbPrxC8Rev5`TFT?4Q@&Y{5ETsL&H5pg8=`N&oX%mi=JBeEWh#oz(_FJ*%Ls
z1zWT2xg8BO!eCjm32d!&$=cfXoKnA2EWdlau!pDH@sup@Zv;AGFQsIIAnNLG7hcFZ
zHYX2OLHo5g;UZb%-Bx{@*V`qxp%}i*G6os9ipf;RR1~)ON0nx9G~`4!gq%)f!CJiE
zTyl9K7f<;NM7na-jSl>SN3SXwL1)!wevwa~)NG0Kzm~PnZjH0#nWXJgt?qw~o}87<
zxDVXkxmd;ayri3;w%Wa$vIkiANYz)<pY#C@gl}U;ehC)0x{x0f%Tw)U-hf57zfMk>
z!`dI(g|)pGo-#NM4F?5gWfNj&RsjV0_#jD03w*YW!^w(IWIK37%r7o_@z@yX;(uFo
zAp4^cGFC<sz9(OaBkcqRU3m_ZS%(L_)7W)mVM}Z?lb}AZMVIU>P=uk2xPa1Nj<l6X
z1m=BGU2LKu@|+x^12!!+OmuM)ZI3U(gbQTW$6$tjRSd^JpM(ryO7tk)VB{oUQ)h&I
zBJjJ?>OOr17OgcXI%o-lKrZ?*5k2}qvm4%^yEzQEVqz>(az0@1oNgAIA>pOP$yk&L
z_SB=0pl=a{T9%EO^F-VjJWh#xnv4T^SkzKR2TGDgD1nxkl3-&tW4O&)3Ps+$m{vjT
zi86N0I_}hUEWI9FC>jd3T{62vXq29y4GU1Jz^UOl1xev-$+H%Mu2)W^;5!O?<U+!J
zxvF{0CkgSyxCGJpQUy>CDMDI|7fsP)I^y(!;L@NBwU8oI!ZGLr7HnJs8X%?W%I0Ij
zPwa5?sYYJ@3BmAFAX1HUHZ?BURzUAXYMl3pq9}qaC5moZFDng0%PXtkR&DEB@)iW^
zHD_n2oD`cfBuf=s2|ux*OD2X|7*rW|l3)OK9W)-brtDsv_XP<bz^Ic_(K*Mc*u~Vi
z4iG4XkT}l+g%q5dFOpT>tQ9O!(oSwW!;)l0wIQ>_H86$JX_K>I8s=mBd`!zU^;lSn
z)e91b+8S9?V*0IxLEB8ZTn(pQ*`#<k0)ZT@0%J%8jz?%<klt;6ZAzYwN|1%OP=6)Y
zz)u>3s@qQm?T(;2B)W0MgO>IHAI)Qo-D_Nv(e5!fuVrx!#!;)EaM!@K!)KhIzZ+vL
z$|%$5<2qu<vzR}j<cWPGAe;m{3nFYo5)>##W*L?RYJ22A#h1BNxd_@Qf2|ndW?b|Q
z0Oi~poagH*WmH>PuI!dT6(^l%>uQjDK#KhBetzM`-juqbO?wm8vX**oUb6YG#k~1A
zTe@}JTe-!`rWOScWlNDo=0;OP`;t5jf5VZ(X6y?IUKy}+h=d3>2F>JFq;~Gdsq<@R
zONvauSXoP+hyl-TrmocO+%QRlU75CK*phlCRJ*HWPI1T>vG3XLZkevUdYCRM{A1-S
z5&MM{RXOBi^e=_f*(uyzZ{`iP)v`l${NWnz-3kkya`I-xWwsPB?JNEd+(NcLO`Ydb
z`}uRp$S!rsj<EN5OP4n}Eru4^+iYPVoR&?+QpRU};FjX$Nov6)NBpkaJiLnN8RWk;
z9&GQ+vXS<0@yhbkU4gHnoX`?%?iSaaUSSrVeu{DQ>C1(d&tpgFSn?~kQ4v2l=d~Xi
z6twtzKJK>edg1=m%3EIJEW>x=$hgnuN%q*9rU>hRu2s6_ks8y{v+4QC5n?9$A&d7d
zt)O|tFHt^}qzjGH@)WhT+HL*yS9#AFQ%RbR<b!M&@SJD2H5DKIAdD_r^2{G3nfnB&
zZ2T!w<6Egc@s&;aFpkhT#BqS(Z&?;fR+ko?1vj`kT%3HQ@ZbK>Y`97(|M{!4eZ_Zk
zX0Dkv9z54t69*D!$(?y?>WH6fedZ-hmJ!=0xUf|^)P`VXF)7~oh7r#`Fp`ikWRkh$
zm0z&2eY;P!FuTbf+_P`66~p=&r#|BEZ!HZ=H)pp3fdNn6La}xg%kYKM`5+XErBpEO
zt#U#f98epo4)U>A!b{A-hTd%@_W0IwEwFTA7m{q=NmdjdBU$&z;eo{M-WpW3{50t4
z@BAUvUy8>)+^V9oaQy7Ac)gg4)bQB1Fj(|~u;A}UMgQU1&GF^GN#?XYEcuPmU3&f<
zWr1!?{g}In`BJ;?w#~5ZK5{z>_2{Gx4L$0{-C>&2k1j}xeDA39Pi{$@59~}s@%_w#
zsz}yw&K;n=i|*B9H75ye07BaO5(lIH{pO@m{C2_gA%gN*G^S2naP6&3#-A9sZ2vhM
zpeB^I^v4g>rcY;gGwbfQj@HmIPPSJ>#q!ZQ<D9z6BMjWFdMN0Ksn`0b96mLCcz<J_
zSww=^H`Ym5vhqO=Ro?_1k}bN)LP5#;<a-=(B%pi6aQh+@IxkV#^}5@=1NjkCc~I&+
zDfE887Zv}eo(w$mvzCQ_vAxvxa8!17#kfJyL-H9<?fEL7cVxGf#+Wz50>Ps>?dW{;
z06)WZjL6pih0WOh5zq#xqz9(e=?<E;g0nZdNGbI?UJ8o_Mn4#}x20{Vt$zLlirNE2
z_XAe92`rjp_JslFnoOYsh`i&6lvG7x%dh|)xTFr+7IP_59iOAa3>OkYFXICZg|Q&U
z3XbW8dSKTffVCGWYJj4^^REdBpaWi9rILhc9Qh37lELGuyIT;Vk`ip7Fe^k%l1pvE
zXLiXP(Us4z8rHRBT(Z{?KTbZQHnp@U3k6e>Sh_5hxdVF^&K%aw4E-X-NeV`y07|v>
zAYW0Tpc9){QhmTdxQ!^6QV{nYhpZeIr?VdNO(^-}0#EFmgR3W*&?+>6uoDkdh{VfB
z&@jI`hWkm-XOuVc9>`#porkanS)a;JCkH?lP1$<EVHW(THC{Li0V5+nbQf~#&MG-c
zp-ZcUV_6<>7Fmr(YFFadh3M6FoapKN9eCFj#KIA`*>#bYV^1(8=boCkaamY%D6EBL
zG7YLd8A8z;n%49Z?QN2e`i<TENIAW$pb0GDPy&&a$UGAAN4pmVpBM%~N<Cpw0zB71
z7R+2w$T#3*o~qIx94M~lbSO7jEIat5;X78|F2T{13w{e8UUp-w(=Ml_(bX}6TkGm!
zFIohqwX*6`L}L<iEN&zUs3Y_UC1$K9D2E~7P(?B)O9j!>FIZq??E3Y1B5pOWENdr?
z`!j4)5jp0r3bLf(f;!ER`B-=DiNvyZGB}9I!PApAAC_a4ywqYPof*}e)bXV#Gb0Lf
zKoA9>#Ce=#)*C$Y?m7e-CqSbRXQ9yMKuyS~?BaT3uuQ=^P?>*J5lSAuvSQ*HCn@q!
zPh5e-BZjZ*xK|%g+Yo$Q941|Q0Y~V>E7!!I>#qM~N(`X8>&8)xMfo`_ta-`W6I=(y
zsXnd(qN*r%LZ#>o4LP!h$2QK8R*bb&h4D?sWufFVLwjg;$avHOJUDpSt&%vZp1eO_
z=v@^DqO9z!fe^MP32N&?5$4Rz-v|S1Lf5z6O3<TME~i1G+mVQ;Y0K5jmOT0_>gZXd
zrGS=%aVfQOW!l?-e1c~0FQY%&mlT}2r7?)w24LC#o*dk)*_t+a0WrJ6@vhoUNRebY
zJxoe}Ghkdml2p5`E7J(_beOq`pP>BIVth6Zrz~Rj&u(eEm~MJ!|64LN(-lwKo=qzj
zpw&!^&EsZn)UuGK-dy{eDQfFmVgaF?=1+fYdB(q*#`B#tJB69Fg>$I{*KJ}l<!GOD
zH<|;sP2=+0C}q@E^q~H5;WEv<Jvr~UeCZhEG`yF3bx<2Azi@J%qqh2E!q;(JhnhIK
zau7Lv^yi1U)m4!S?(5|P5$`XuYfxK#+<1D{>qb}?wI1$$3S7y=L`&y)xk@+0<EZic
zF52iuz@2$>X5VbTE_abSQQ&|JjHl6?=53l}6%a1jKb%CpX>!Pd?!R6B^aXApf0wT^
z_bqLS5jWgdx3%qWT@Hd9Ery0x3Ufo$Md|_n>E35Y5E?+?hRMYwD;oP5?>!CjH+E9Q
zsI7L&QW3`9cfZ~IBP!gVy?QJZD>)yO`CpvPUd(%~*H5P|xr)u^78Q@();hVdPrTmd
z7gh2bfKbk*`OFUbiT1w)9ky2CmFFb(tGfsC`&Q_u_fW<gf%M8humpj5?Y2ry6s&5X
zl4Li)?fqL=l#<GBD|aAu6j}M`dq__%kb{8I*@`6k8B&V(HoMd-?7$=IYRfTeQ`gvd
z+_2=3u&!%Z!<ig^B9<8e{g<+UyFYlLe1oQUE$a#aJF9;7<kge~PnAVrw{_B{uFI^o
zZ-Pr)2-j}wJvKU(edQ-<%YhfZ_o>3=@0*@#Ev3`hwQu4G$-|Zgy8`AL%!iL8E_v)@
z+(-N%!{SQKPZOsP1a@18!=~Tm6D-Zwl0p~V(e9_}dAq&UBd*(hy8pJk><0FDI?MG^
zW~aYBue*@9g1pNibFojQN7R03Y7gF?qqairQZ1HNima(?PCCb4oTK;NAPDjA$3hBq
z>gX!ukwUjC_y5Jss{hX~spYT<bU3T<FU_y5EN`=<n*3DG^~_NkAk(B<(dWo`7pt|S
zYvY;xgKwMvI6dNblXR;5T@*NU$t+Oe+PX<zz#-wx-W1w=h%H$2b~=oABz_CS7L}nL
zg_#~cjjA%@;^3v~*arfKghA16Yk07WAF8eh@()nZu%6k4gsUd@g;O|Wab2a~L~@nz
z;<k*7880E>_)nYUc|<A22_G&B+6EMfV9(<p11vU%weg(vn1pha)IA~C*AQ>xa{POq
zM<E=w_Oy9NFpP)5vk>J~K%QOD;aIQPk`!|0vXy_z_HQ8T#O9O;h3K3SN!bU=uCi2&
zc-T`F4C67xhFO&84`XmcOc7rN-?dH1vcz%fU0t8PPY<~TwZLvJyPY=yDmdlJSE=!W
zA9>LRR8Y;aZ1yCwKsXR{yt(LLR(`$AC)D2SK2NBBT?klwiJ>%Q1p3#iYPIAe7_-gZ
zM;nIgS~mDxR<}^LFcR`~VxXu<vd9?B^Tr-?6V0@Ai(^cCD8Y7&(;)uAB-j`Wdai{R
z`k0oc%T~Y<kj&nTXcs}tGtkQL=nE4kS)y(e&W?v557F?lJU?8%$3i@!QqP<<oF%~%
znBgG4r<Mk#GKwbw8GV44N~{&y!g%8eWe%R5aOZ6c)&gs=kS3}ly@6z@FJyNa0wJJS
z4ODwlB@WKzN=6R3r6iL1>cs+X1+_s(`d*wNVwJa-k@8dH>I)AFkzWwzB!qk?mYNee
zN<)T){)1$lgE`<F0#wnx91<xbe1e15sTrY*5Pg}k&mkR$<0K8n9(-{&Ni-L*^n)&E
zF$FQ<j>c$`!=Qb@JtW#bX23d%bgb<l$AhV!NR^Fb^6Oz-R4GjF5NQqfSPWp*r#=Xi
zh$YN}G2|16cJ9a;yo9u&NGj%zq(E68NVY9Rl8x&DR2!ul=Pzwp2GEm9mbD-JMUiAJ
z$kf2%_>rh&+i7+EYm%bORVUUfTDW7HN(7$^Tk!;A7VyUhBdrp|#4qy&EMw82GZh>s
z0A`8gVlSNq^#XfJODbVH<qFQkRq8SN0-Uk9%=i!!Tjeaq+e<YGDx@>uV5Q1@AA$|0
zAd+sUyD(n~kqo<v!X{c$j&~_#Uw?a{s6?DsT~Cqp-pEVHh!m+|_5+f2!eQwK>Q+(b
zsbn2byj5mO7>4*%<QU=$p%&t)2Dd^JNH!6q1(Z^_S(!#>Zv(bh(UPF##4;4T0%phy
zWhU_2V^IEB*Ccm>;H;%*&1*`O8IOvZA_eW1XSQh0TxM0SD(0c1uAmP{ph`^1%T5XY
zcY*)!iv5p{{L>^Gx~aIXMHOKcT(nU<YiHA|p~qSVLaYLKI%IE>pZeFpzXC*|#V-at
z-)GEI10;Pl!dL*$izI3#zlcKJt*XQZILiXaM;Vage-I!U28%#TQN7VniM@h20>+BW
zxZ_>NH)LL;N6ILO4>NsYL1e=a2{C#)odF`vm@LC;Fb53+s_`kQ8nidxq3pzok_4QO
z4<yp@=r~XOSjACNokrw@x*D+Rh`AM7kQbI%m*jB#jsfqFapG8&LcpQlKN=z%-D!*I
zdp%4#`co@G(G;(p1@*<VTw3G|2oq$50XAuSTx@-IMmhwb?SrO-JO#&I6Q}5dY(h%q
z9}R@}gA#;M>UCQZ8zB9uC^}8jI9SJwg8;n)5(7vCu@CxS&3QOO#Ka9S0I(ej5|C&R
z?gKiQ8Pp~+=#w|b71bz5mrhLOB&W4{hm}E&{Z>%t2=?k#7pT$Iq|h|>IQ~M4e|O%9
zRm?|}fK{9=D><R`1$2yvI7RAC*a<)1sZ4T|gB)>Eew|lmu^|Xa$kYS)qUJ>}!h%e3
z)S}?)@>Ul!#}5{$HZ_ZzWJ(+es3Mk5L=i`iK1M_&N!J1~TTK+oKud-&SO^eha>Xf}
z7^aOJ+>r;8zAoA^#=DlD&%vsf9HY_(((dB6V%}n3c{M}{0?uHnekaeZlEF(651akP
zb{ta){Zm%sW0_;N;2#Iw*F)!|8$ysEO>tb!W${qb5{`c0^!)~=gPC$kU5n5W%TN>+
zjc4!=g%SDeVDx!}E~TO?;jkt~^;&W02CWIfDn95L+Op0@2C!`yGS$7KgeSCJ(uKR7
zN>vi_M=@;8@vSbRp5@g->;n+j>RyCMvdR<HI?<e{0;d`)o<fr{oay+E^S#HWJy`Lg
zX^|tZ!LFiRI&fPZG}SMN2^_yES#pV}4<LW_37K!2bI0JOJJG48cA!Rno;|ZW`3Cec
z!RtG`?LWy|!tE-y+-c#L!pTY!bPtNR@6DiTZy|nMEhHo^wv`|C_|WwnNu4g;Pujl}
zELo|tw0>e$2=nX#DkbZO>8%t;d0X^$2bS{cGh<p<yoPL+m)lT04|6Y4YKgg9$lJ<5
z5|bgMs*b+8yR4$UzUfoDkHUB-#kS`p%h-9kUv=SgMe1$TRq@8QPli)$n_V0}Ky3{}
z>X(5B@`0rJ5ntbb7L4plM+Vvp?InN1>_mJ`&tDwhqt5J_?R03D#e0McKHI@y_13E5
zSH#yfmrH-I=lu>4E`__b@Y&rKzWgP=i*@R`A+V8C9d=!daU#1@ol8DsQ~J)q%G0-z
zZK^cO@H>tS2b=$x<!3zO^==adcy=B}*x`vAIa+^@n=d2JI{)a+r;VibXR=9mWc);l
zJkO8&P3PG{_!zUI?uG$4PyB1%q33p0_7)Pm`Mr6mMA%7i32#k#lFjYz%bd<1I*Od7
z^b2V`JZ*xq-T;i+rc>BLJj5#5-tAu3bgEXAXKhOT8~K2TvL5cPTg}hcYSUjBO|v54
z)0oWKiwCtsm&}LcfA{&=ds8=eux7*Q88$ckRm<;N-W2=lV#ha=Bs_M0oa?zgY_KId
zJV`_72U)U>I;%zg`A?EFRkjL(9l9&E)`ywi{Ob?3-QnGdmJ<5IfBv!+<vqO0UH>dE
z7#ykMXiH3o3-2So(^0~4EX(Jd$)tc%m=@LXL(C~SGbo>__}L3>?dWTb8-krrbL}p#
z)V8TXZC6G4%A0>4Js1kwKjQXs(iT7bXHRnav-ACwj&h+WJ6>Oy<2m)xZF2U9VtbzE
zQ~#09C$M}^E<JJF^))+}L}D4Yj!=<Wd>J$Brf<qU-7HIb*~0aU_SqkE>h#$crT*a$
z`Sj(p2?AcSW<1*ZBz;*rnlz~fqxY1X!f%NAhAu0Ughaa!Wb?0Juzs4}r+ggLH5Fmv
zAa|bF&a2yn4cHa)klP4Mg#+{BcH}pC(fQ1x-Q5EZn_%W;o%p4uj)Ilb+Byh$k?cBv
zZDS2}7<5be?8Qm3kGxcY{UL<EoA7oDjgpR7GwBFk6P8PDQvH9Gvs<fxWQER<3sdM7
z;cOK;Lq?$Et|nBgAt$zkgbV(*xgyy$P*OXf1=Xg1ID{^K+kSjoR@$X$(+>V8JLp5&
zGOlWwLINRtaKTKUG;MR%*8ZNgPsfra13}yN=jp|~R?oN+e6~`}eN%g_E3~8TyTp4v
z2R_Mp`jx949dTAkyTZo9T*=%!<*dIPI)Atk2vbfK6>VaYc49ap&{1h-7VB_#%&%rd
zh(g5*P#$uqHtI(&ioajWRrEc95s+$|UoIu46QKznR!=9)icf@uP{BkrqmfrBVYYFH
z=!fCERJtA~c=|o?J5S7M0yCXG^c96vsbH_blbPFP^@*(%;zq#9@PGoyZ7(=b@Qn>S
z8<L0}6dwo@MaC|4LdS<^1(W#dCboVMK*^br!On5WAxc~E9je#H#u{P66O-#CE#=_6
zUq!|#pc3hy@Kk$>-`ZO=Z%Vkl%YwfVZG-B7)U`1SEFtr3S+;(#T=VDzV3ov#g$ON)
zP3<3;li})>*lj^5$W><#jzR!yMou^iMVHFa@Z)SF@E-H4e1#+-3C+CHRNh?}3VG&m
zqzxO&0>Pd&{mGWf4Ba)Svki~iQqTlG0k19QwU70nr$l1)ucQVEp<K+<Wf*;+)d2Z~
zIMR#ZqRx4^pGLDW7b1R($VJU#TI*ugc!F$#J=H^B#xv*TK#GXpGk0KolHJ$6m&V4>
zvO%Cb42!TC&mSs|<HrODakCOYKxpCUma&zn&QUmsDX1bT*^)7@l9&W?v|8ghF|;Ed
zi&iwYGHJrFAXr)Cykq1=Gw|dAuz?Zq(V17Nt&4du=SHYp0r#R2bcqTO7yT~ilT1;D
zNg$1-K#0|xR?Ig9p*S5pkr9ik?iGlZwOkW3C1jkJN2WUUzCu{f%*=^JkrXV?SI<;_
z1OZA+Pqi2)i-6`^@RBxJm&=>?dTtyzY@06$9ikDG0i{WnB26dX2EWLN932iT9-=Qk
zULhh9qNS(7SqFuqgr}Z9ubZ+q5%8YB217Zm{Jm%oGN{T)HA^%i<yX>pdBg5hwV)8p
z-0g&#>e;;hDaJ8z)|QVz3C2XDYki|o!9}<x>ci3MVxI5dFx5+^>LJX39**uzoD%2<
z=wL}0DCv6QY-zb3OEA0xzV;<cRSs{R_7$18lC>k=PwCnfTj2nR|NRL^P-%NV#^ZB{
zZDl^z?h3z``N#{itVCQS8&>f&-<qpszSPv=Rvc){G!TS+ueEsspCjp2n2qJ&qdTnn
zu4~C{FEf&b0~7>m_Pl-0Rj5og{n?SOPnrYNtaOXBumoezX8B1iiYYlbZT8HTB5R*N
zW$CUoO?km^)E=WWj)Y)bpL#BBDVV>D^WhiJuk&dU`{Xc1{|Ou4u`WZa0r~x{ea;!v
z{eh!uYb*-ew>uqu>`M&Lr=B~t*k&3V8C{KeVoU1Y#QDeFTZ84#rBYiX+SZqNJ0Arm
zR#g<3!pl1)>pGh@Uv3Ja^_dy=#$LsGBO&GdS+4r*#gVEe2)!rlU7;`8eSR^<vB%&$
zsM%$?9enl*D=NLo@g~={KohVGwG|-)@%Wl7N@wiGB%PH5lxl%Zj`bn8orirf@^2Yo
zIOM6rbOQg^6Lgqw3Tml-A$h$+`*|IcHde$N&pKOfOy+jwE7I29AB|fwu+^5w-j{k5
zYHylpArOZ?mOhX*ygAr<DOa9yzlk&6l$voUea^*XdK!81vZ4INO$sd>tG1eb@2(-=
z`tW9|+P?^Pcz0g*B-9BEa26;hR<bX%;uj7x_%qhSOuVk===noQH6BcSm)R8*iElKy
z1AG3exVz$3zC(%EcDkr^ZX{W2{I^LfXXq0aKfjDLsyc`s8Lx6F|726<@BX~$VB(@n
z==`4Ckx<6egg?81G6sEtU-+(bx#HUR={mE}4_HjU;UpUv`fq$XcZ_S8s0>#t@~)Eu
z#X%~l<WC&flBcdc;Ows+=7ymbXF=#zv$WYxUi$r|*77~CiL7Rh<as%W5uHeW7o1VX
zP0k-`t;X!*%mH4$JBu<aR=a!BI3Wb4S}#HJ5B;e()K=zbN6}n+AEMuxZXP_mDe?1n
z=Zi<f*0qI9LFr233iQX+zBeqlZqRaiIeG0VKPoZIqorM#9buB;|DGAeXUPG;Yo1Bl
z-hF}BiNp<ox8DKp>;KeWGe_?QglKFsPqKy0U4X1kA4fU7O<OEsWM#<iuMVc)5R1<X
zy;y2_LamvNBugVPC-Pnwe5?M@Ag%Og(i;crSL|~j68)N)sURxAS@gf(F&hmRa5R)v
zBo6uxYG7^C@gk4|tQR$TAr${5evX?586jA-7&x$Cxi99--eD;(bld6W>8`<*Z}-tx
zgV`U_vHJ$8xWAIL(tD4|h~I7A{Z>lCqg=%bH+ExxYO5F{tT7x@-EjoR=(Z5xU&moA
zOUN10_SEv&MsZLhqKS$V5>QGBiYB;G$drXO>3W<YU`+6{NgUDzNtB<SKoKimWjEgc
z$CeYs$4>e}I4l%jF?}@EB-nNZWUPhq$eAd`M~2IXWkkA|bS9^5X2x-@DhwdMy@*1A
ztvW>=S!9(DQS4ntNIY%QjYrg8h7(hY+?o|yDWeOavINp`zU#T6XA`W$rAXJyIkIIf
z83G=zjJ8Vp%eR|_UD00mQ%qE&1gOv<ps5TcooJmHJs)lcQAxIqRkT*u#+)U290#)U
z@@s4EMinT~A2YjCUKJcIo32lfXAuY-x^D^9D$`u86WLXJL}W~*z(dJu?4FcQ#vW}t
z)#CgiJ;`K9sS`qr8J)u75+ColY|Rmpb0N%mkPQojoDY=&Clr3YAq}46`m3tO(kgaL
zMsIMz2ZlHfmES7Lx|TpUQ)RS+;v1DESgb)f$c<EwVnt77+FCWQ$H;_CW%Q?mfHX)p
z&0Az!sRVw4AX-Db-r7<wYSo};WjDNG=L@R>K6b3AV$b!@ZAiyKoqH0xg~R4CyaWX+
zak$3H3Ym9&M2@Mfl3$URlHkVx+0-*@zLR8=njdy(?X&v`<yE)TPcpB}>6k~TF;jS2
zfXZRCQ7=bN2oxz_00^WRK<qXS7t`hABlEk-A6-D^DTLupO9HVk(AYXSfoIolq*H;i
z1|+JfT>-|P*<AF;Xv(rtAO}m}hDw|eJq|n>Wu8L%G0c;tm_Ub*RqSeV;c*umSXR?5
z9rU;spvPh$KhMwjB9`cuvf`EG7us^PPGxppsv!CYZT!W#k5^bMw`qFWIZ;ZX^Q#(%
zWNCL>eMcRJ^Nj&-=39uU<XsS=X*;v&(WxE9jrQ<3Z%HNQD(?-LD{q-suSAE)ZJ~lo
zU4hy<r`=Yo-3sgIk7fBErl**;aF7GFb!>SncxQ8k37~J2>9x5a$Hw4#-pKN&Bg<Rk
zw5*E6C)DCPx!*~F{@F~DzI~GmG3ee7)o|m{;u|cv`CMY1@gLs6PBlH_fIpks@#}~_
zLT7sCwmQuOH75w>cO>cPT~IBaSUfmj>0I7&_+M5l><39WC1_&v6>7($r`fjhRkVg9
zkZQe(qFrE!|LXQM_iuHSFX?=8IPlJ2W?4+Ex3RxWCPwWcvaGi?*21H^%^&`f*&U1L
z+q6Ri>JM=5z`C8!E2w!?J74%^A7m~25T!JKa>}%yO1Q!%-<F*=we8s=d;)by8g5p<
z^F3jTI%W%vO-tImOdO8>xggoS*A1k%efol#t<sh~u>_012jg6G`k7CkT#TJ@i}_aj
zwy1{e+E%HpA$|B#OB|@NIG?;S_*s?3fnWAjbyUcDz#8ws>2I1DZG>r}0NG`kRy@A5
ze2%pqzuu{nV)$h}#{WNfZ>4<}OWxljwe>5n_Qm!e&nM$wIG>f-_og$vQkAE?b(Izf
z<gvX2<CZz+T{*Bk|HXe*3G?k=qT`mzMs|C{-o<9RfO^#Y(=>#C#!c&MMfi1g6Hr@q
z*2!l6({A6JltSCosj<To*^<gB>iH}t5ZgWQ^P$kj>5{M>ey(cx>VT!%1utK{VHaL<
zb~+$={xydiQth^m5~(k=N$k<@^KPAzeZ#9wZ|f;i+>?Ldb4Bw`X@0+p+WI?f0{Bl+
zTQwMClV;0vUXCX&arZf%?k`W?fba%AUn-iiY%6!^w(f-vv_#6CJW$P9$w_GPZJ3r@
zMwxx%nJ5&~Nh-C~r|)*n#`lAL_1WJv?Y7z_?6wxkxhz$Ght}{UTczx_E{%OR3wmqN
zK8`ZmxQUS;RX_IAq_aMpyI{j04qW}FlYFVoN6MfJzReOC$6n$)4|%xTzTFM!_4Mt_
zn2N3>L9Z!??m`}S47#M#MUA${j#i!$E$zaJ-mT{IsZ%8vN{MgtW^}~y+R`exj~Q<C
zHnc*C1?>^5(IDS|K-{;<6Ph0ZZA<^2%N7MIj1lVRkKJv(`8;`1*S=r#7gg3?W*Uai
zczt$%sT;WuQ7=eN?1vgFINf;36KOIKUi(@boJz;Nc{jrR&9*c%=M!DZ!)~i*x7D-T
znhvYy_nfw{{ilxe;f-WCc^{R9Tn+lO*ciSVq9w=Ly0m*d_l$sO%`Kd``@~UccO&SW
zUgYpeeEjpnyLfA#9z7obIYYp%U9|=nrZtNKmxLCpsu~z^o))m^%smev@YBA9kN*_O
z2B2)XidSzf2q>kh?_w~=5#35e)V#t3@`(A9!!<aYECyU=ce%|i`SpTelLR|{=}eW$
zh#fE;1>J?|Oey%>u7-A7!z6PhTk?1&7!#UmRaxY12bPv2NI(HTgIt<tFSCzq$!m3=
zC9Xbjm;E&u^Eu~G$kVY9pf`$_Ck3aVAfqR!9%+s_X09c~yzZryInGkL7yv0d49=uN
z1))Qh?M827FYQkHhQj8(w;=IE2z^1xQvaNaskAYN08;t2kV~uPv-|}}vb23!UN7+^
z$z?GDIDUa2;bc^0)5Ibzr-OiNT}YB?E?|Wgqa!UaCP#6Gv}DFh3C4)}w1xVGAc8W|
zA)9I37^{JIEaL}zoOMc68cW7IC~D7QB%Q0-Y;2qX4^h!QK+eh06Ozmvsm+tz^I*){
zL3zzjL0q2XHw3`~Dr;b|U+6U-Brv+!0$JNt@@sWTjoAw&%IdbzOhMRH9J-4^>#J}k
zV<WJn9HfY?#VvG-Aju$uA|&2Ef`bJBphgO6k7cJ@z)C@Mfe$Zc0f*9_>w2#LO!I6k
zhI%Ft-g#n)dt6MEI^Z)jR$p_b{ntIEc@v|a6XpxQZO-<q4uK!l+NX%^6mzpyS}(Nv
zo%1js7dk{O<rh#}$%2etFk>I#GMyF@2tuo5DqDoyn1-k`oZ+|ZMYlI(ptEnwVnka_
z23YNFqw7wYO!7Nr82!vCqmk*#jhUPGfhW{90+1WA>(aK_G>lSa6$CxFlbM!VE|P4e
z9d;z|y+SExeO#pj@a|-7t7}|S-12)qP+|{RxSRkbT2%(Gr#19Yr84vMzS=XG$FARy
z=837+4;`+X$)8p$W}sz(5+9$y*WPH3Pcw9ccRy{sC0{%YJ$VD*gP#J;lT-wVLtT*3
zhIVGwn5x@5lZol5wkotI1O%5p^M6|A-;%UV+UasVi&cdi1Z?GYuj@NmZKuru>GCsl
zEJtRv55PiJiEnvk3_-;^dnB;P?`>tg^66y;0@JU*q)4aK8~mB-VFXcdLv&;oZZ*d=
zs%7OlG~>4t`UzGpc(B@TNV5YouPB{_mwGy=Ro`yt@z0#&N#Xr;p9$@)byAq@B0NfO
z33Lj(uy(?X?GX+M1A}Q&Zlat+7SbPV$*&A=hllq}j1(L^({8J)AIcEOnKl)EDfumX
z@;3U7vyP7c0d=^WJ&`*x<jL@G^M;}o{^-iJ2$Tf5``T_x$}drMpI{GEYHQz&ipD{9
zB<}g*$wi$FLjRXfe>BKb+n!PB(6;9pyOt;~bFJGx#k$F}taqY*WYa5`2dlqFFZwY2
zF4xKUWm)KGDx%RF4z^iYd+Dd#)EPgQCez^F!H>^V<a?jJA_>3!u_BN9>`E=5`Q?q}
ztE=uVJM?fi?m$)MLjK;wd7gIQSE2;uzdp2h*Jp;qdk2@M!~E~;uvyg;;Lw57j4-=S
zISF=AZm&OtB_0x9phErCi|BYCu;ij2ja&YOtt08!UR#;bH!|r~9EWbRBM0llkKHlF
z9PX(k<&f~iwG`zfb=FTleg;&js6D}P&wL8v@;7Wx5N5?$RUZxwCFVao4;2o-9^M^h
zh0qtSJDg_!@t!(6ikGoQa9CZR)5R@OZ6#M$ZH~(u%_@F>Lff7k-e!o2KJPadH$u?@
z7e_Xtwu&d61%Bc$KV}E7{H2rxW2rQeZ9aB{k)hng*)$fK#*ZXH1z24vBcV%e-G;mZ
zQEZg%!^r|l>Us7AHyyJ7@RBJv^uID@fSHioE}pGlAL!%_x{n<ofg2l1Hasw7llk<3
z9s16;P@H;g2p6t|new^Q%zg7i7B1wJ_x^D<`Lx@5<D-Z#W&GOq-8({5#_vG8-%;M9
z;|V=^>IU9vf5jkj^)2I(GlR1ZjQWGuF(B<^YzmufDR4_Jne7dG2@aQeZ%1C_`I;^j
z;(PRF2(QH!b60KEG2RIJwnmLkMHg<CQPnK)(RO1V7tlynyRD6g+{+-@F%apln3n9n
zZZ!`gc5eIcylFMj@4q2W>4;TjeXc!CAavDMnt;amyE6I8VQG-r3%1%X+jFcumba#R
zz;j*PaITJAlQ(%J2gn~YTFQK1Go#nb>;Ra{>V-ecIo_|nrWoA+CFWJ%2l>(0V4OwJ
zL#)a8Mmpxsg#yge5f_DjPtvTuXAD+PXy(P(!E0@_`KDD_tl~Rtn_(@C(xW|&BdF!|
z1ZL|VQ2}Y9OB{e{8A!^{RF<P=7-BGS=Jio`h$EM_dJD%NAj4VPJkNg68Emelqsl24
zC;W~d&#ISkj9B=E)sQr#pi$hI6~xl)I^1~Iw%#*XMi!icD_XKe2v(}c@N(#5RX~uD
z4WhO(ThiGk?fQ~+@xbItN#71L)k~B(m|D}6DBGEoi(z4=NGF8}^yjRT8n~@RDFnxW
zGwK#T**F|z#{~6oOebj9Y`BGpQ}>xHaGiRXreC0PqdSxdmIl91%Lnodt6l=|lw`mQ
zsB%mOHw28VBx~Ub<XKiRCPg8wIk`6bvZ5P511g^iT3riI&tg=D5try8(+{FXnx*@b
zqxFGI3RI|7{ZSBXP=JPCAXp)QW2weFrrX(#FTn3$9X|==;)Gt2PeRUk@eWU#M*BNi
z-p;IC5K4XyXuYAHy_-3AJcn>X#I2ngC4R(Ne-Ne(g~D1KG3Zo=&b7W(War3JQgdXM
zL5(HQ6KE2wpjpzet;^s9ej5VyDr<md(y*C0aJbbfE9O`#nR~pW$rNm}NZ3J~PB{d~
zGhUyXj6_>6!;jDdcOdg!eBbq2wZth-katHOs=oltXo1bOY@bcY;|xw1(1ue}83U0k
z4;p)Dg;=X9T@34K<hvckA23b`_qE6<$w>RuUi!vC^6O^Q=GVsSX3b6E3)+}p4ejK{
z9H}bjJOPsbM*stcNaUojDov3=R6$Q4YZD_L^$!s4QAjus*f-fg2M+Z>G^eO{$w({e
z4r{DY%B@(a%x)@rHsuL=DHIi}I2+)*N4amZcitv_p?UFv=qHx-VWv6ZZUj&y9C;5B
z*R6>$!ftEZ&Z`IUo~3tI%&kFqzBR~eh0B)wTb$XKS&3y+HNvH~Ct2BE+3nV8zBxt_
z`u_~O55I^EokmDw+hP@dD7$~EWEmvfczK-bbYiXl2n2PxYig0dQvqFaW4CbhzLlh3
z*8F6+lp*cG1Q)<3=bcU>S8!7*Td;7mI`lrUWWyyWL1-C;BsmE*6!>Vvs0y;&7I_Nt
zm5(s#&-99n!}XOk!-ESL&a{DfH)-d!evM1$I#5w~Z?@T1wk<`pZpgaNkhFYpN|;C<
z3MR^tdWV<rS=81i55b0f+b^?nT{3F}^fv0!7dXd##s{2nC^v>>A53if5i+CvXa@hy
zBej~{bVjgC9<r1fd>S`q)pm6JlW!uPHDGLnqU%-!)~0YGyL0l5)St_2wnCYG!-vdN
zm-47LLG9|5%WdE_A1tz+Km4dMUNOR5mZniRj&a{*VFur8W=_E=pI*?mNinP=2u?~!
zft)-M;*S88<lHjP&|0bSWlKCFDn2U4rfY0V(`n`#Kl47ak8dkIBeP!&woo$C21$Jf
zzog<UaWjAW;iyC5*9V->l9|uj)U|(_W<d;z7F<U2&=3cy?l^@Dg}$2F@@^OU<<kOL
z82Ogv%QFL0`Q4wN_VMaih@l*gOR)q2elKIxV-uYlVUtW>zwr3R&!xmSH!1bmm1j0N
zdkqR7kz%MY)`dXc5m=-?)7j*e+csV1qdu!c%ciXDplU7N{;SJ&{Xf{E7fMP%H*VCl
z$DuPyH4u7l$Y*l(vzolx94d-vS&e&TpW-YU0W%tTJwJ2MOt+ux)KUw4+~A#OR&O-#
zbD7QDb!l=fD0bWSf0MgNEsP{~#|=q2_I=|FKPRp)`i2#4mL?3kN~1SS%|Gs@A2NIL
z%}K?8IO{-p@F{1v?+iBbmD6mjy|sTntKs5hG=Z<P-{{$>jUTz-5jNRSR4lRU^sxEw
zA%sU??&HxAJb{}KaHAIVwrkUt2JSHTf$V39bhrxcVK%EW6Nb|#loC2(FW2F%<R`8`
zG7Fc7dT869+E)LW>4w~r(3*^$99Lp<)MsBRxF?{IYmycTr*8{oB&Zm>?DjP@tK!bB
zeQ%^zMAQGf_`t~TvcTJ}5!!VtWs!DM_)|E4^S*%a636;JFHP>MD=>JOJ>eu<*zA+E
zXeM#f;}~40`FCpRgf0eb6SVi3;NFe`c{YkrExl7zaB9AaqAbAXJl}_y#9H|ZMU~q4
z3Yk-lR85!L^V<Lf;Z!svx8O>7L<&3xY|zO`fL_4V6wya#G{!MIa&1ONse%+sCI6#n
z&$lg1cl}~1ibleGy6dT@h<Gm>x~llAX2oeIL44Ar)+s5)zb&Fr)ws<e*UNGlMZE|+
zE>f5265l~u_mOAcgpUPqvx|fj+3R2jgy6BaoK4P>fLPuDRD1WeW@!f9W27U_VnL;8
z-RA{wvg-4O-b0vE7{R9q!3kv^g=BjRcA7f+A)kH_%K%K}TXj7G$22G2hT!zgZZ99l
zuf<7Z4y`Rak0XNe6<PD-cmhY}D)bn-zA+iGV#?^C6%A;W)E$wG;4mZY3lVLZR-Q6l
ze4(v9Vy=lR$cycTEJTzTLtZr>n1O{LJFu83xY|339_tu^*E%{xNjA2gE~aN8q`1$@
zKu^;^RPAm+k0<Peq{xOj{B*cQ`gyHoq6-vljBd8Vm@ZXC*vOy)uSYaWECoxAh(EjH
z_GBX$7<Z*WQi0g3(7-mIM1^md)=~kIDOQv1qH=P!vO20+Ja0e0S~6Xn<DVh9pG%a|
zC~3>Qs#A5ggO0t+kvU@VDp3{JNfyv`Uhig07=a}TYsFI&DEoM9$#@kj&Wm3Tk;P=0
zx6@<fENSUUC33MMMbCANAZ{Qo<9L9DB|i=o&O53=;>_T9q!YOdI^a@CpGp>jm>2lf
zoJzi~vl<YCn$cWqFfsJFmGDms-O}sEORbRwl)njyR1lyW2~R~Q2E`a9<vSh`lOqiM
z04@`XNGoS8Wl5_mkr4V(mvxWtYR-LU^+JJJz+ic`ta4d#7ZOl}9-FWw8oB}L|FRa<
zIqGgs6m&ue(~&b#?(%UI?~a{WHg(>PV&VP+-s_W){ed#f=1wk(_6=FE?@=SqJyoCA
z6*#^O&g0)i2j8%jrg|0?;E0Pp9Yf#4I1-9UcjkRQ+*oUKvh0}fwYW#^e3T06NVKzs
z&<UBf&mq&%lN%OZtFgZ7EnIo#9Eq^J$2_irmkuw!&_332JU6@~wH4<3fJ^gWyNX4j
zHI_4*p8x$SPFXvC<)(b$NLAjT=7AGyEWky14u&m$&VCSEp`GGyAX%4D3k&aTrtkw_
zzhYub`wgsRqi|*4xIF);4j=c0mhKk(b8pF0ad0>mf8TEU$V15DH!jLNYHNS+puGFp
zd28Qx)^c{{GmcAZE>|o^c2jhnq<ZfWpOtb`&1p-lc$O9|oTdzXHp}P9zeM71c%{!K
z4h>WtibB@|PXISBIh+4fi20ZyNu+iPI_bz~zBbRd0Jp}EN_qm!Uv(K;*t2eKseDmY
zc<#G&lJjSWMb*1M`tjwKptc6=y<svG#T$R#sR-x79M$HOivlr<*2;@4RV`9U$|t;Y
zg#~MTG<UG&^ejgaX+BEO{U@c#*ME}E&*IoUc*a=s8a^r*Sp8{lb(T#2h;01B$yvJZ
z?P=<du(|m7^#RO2Fk385+;L{&o8KL_1>qw9Rruqf<mT2L+e7xoovrjwcB`Y=0Bkc3
zK7aKzHgGP3bJRqjptuV3S<Q^AG<d@}gfCF6XZ*OZtI2h1TtV7P9DEn0ez4B_%V#Eb
z-C>Iq6xb7@2-%E}Ie2iXHUV~vWK;NQmft>YJdOISXk30?nB^L<vi0w1+&YO2N<g#q
zaY(!H$Z(R}e<!1Re`s56tF=@aW?#NJPIQ~t9sim$?WZ>lULFobHs%AL?5a=JHov33
zcOedu`>1C2cRvZEjZad&FXx78P^cy8HB|9rMCwUsZ{1x!_;9e+Qv(ZHSJ}~5B1Jkk
z|KgLpO}*Jt{|oxKDRer8%WmsPpd+5QT?2N;{M{1NMxoe7E)ZH&6Per7-7OpXtU6>3
zMNRu&7_sG_W7F&r29P6Nx}5tcV>k2g6`37AD;o&^A5DCNFr~A=l8Pl$b+0GMs-F6!
zsD*A1?W}z#b>J)pt2<xYuI|PY?n)<}bRcOZ#VL$={a}#+Z~vA(5iNV0>Xik44Oxx_
zzsqVG8{_!MO;BEJic_ydcegnKY(F;@QaexV(yFZ<tb9>C^;yIZ`nGrS=G88a@0B`<
z*bktR-ps4Q;a9+XlvZCwP~m#<`4N7@V@z3pS3dmuLdBQ4E@HIsrgo_E-1Qdg0N75J
zHA*vQp%rrZG>v>>fpEF{LI8tbmaY}5a?k}*DYR1~se3$~0(6^Zp?$B48+n0|FgXlP
zj())YnQnluC`M#rPIhCFxh@2H`7We3?Xg!{iuwdi^7e?MlX(3x@{F2511lEi2=OWW
z@&P7sEzXq9je#~f#+u}94I?pQk!R<OQ5}dW_M;d{j9D!yEuT*7KH|%hR_CpoyS!dn
z(jX@X<=cgkQ{yr@3DK&H7PALeb8C6(B0m2q-qaa(VIpALW0TPx#%x>`N&x^3wZTiD
z@K4Ail`$5ji-VJ##f2LZUO>j?W)(X&y>&V5mW31M?Yxo6Ld;#VS5Vp|x=$<Ck7Y44
zCBoNQuxTOai<pm@ir2DhCd>tS_J)O=!>E~qJK>4iQSfHtTqfn_3v_%{8Fw^neOpN2
z0(!m$pJ}HURVM>KQ_f*8maijluEZbWmU=?2<`*Ha2fMJrgiWM21R-$?nW#$_SOeJt
zLl!5qr>}~NPlsNJy#rj4a)c1gnE#q9&_+8tP!+nKnN2V~tpYRe=m$nsH&nxde80@E
zDT{#In3Kg3Lt+^WdWl(8@$K>!Y_>Z?KsZ+SOG4K9;W%(5ExJ4Gk$C7bE%!Rm)_qs&
zK^7FkF*S`$#}&FlP6V7RAzyUs>f$<ij(F9$vL=dz=o5C1C5Ni>!7^E4xXoUc4dkH0
zhl1<c);wpTSR05+yDLYtaALandgREDxo~XR*wzQ9PG#7lxWU3PuhG*fhCE5J3gfDo
zrCF>i3h@LyO2~@Na$IiuRC)&ngiZfDqaF;#(@ysjJaW)q!M8wxzMO?D+nsQqtkxPb
zDuf~(1r7-p=k4&Jec7-L@^0(K;E^q%m7hO0pMDR%dFu_Bk7v_Xu5j_))<}i`7f<Vc
z?UZDowS$r^YiZS69HLJ8^XT{46}71A#uz<~*`)ZW-&`J>;r;WMB~DYJVui0jMqu~%
zyf`I0g0r>5sT)}XH>F8FTH^}=H+M>BP1p&nOboSuCqQlW^Pi0liGE&w>`ujGHxD1+
zO;$ig$o<b);SQJ|`uc})I~xlhQlJ{^#W-_stRkk|28x%mU!Fk)dBK9Wl^SHv${xhO
zALQ+oA&T=Y)Z`~lom|^;!=t-H_%brC)z5XKIwZUy_=T0r6MOLmmYw%Zp8AzdF;eG{
zaL`@9vB_Mn08Z=LB}eEa(Mw7lAZ@02@@@FZ!(V-kEk%XoP@M4hO}RMugIb<&B~zsC
zJNWnA+|1pPb1d9``f?SpQcF;2!XqQkGPmifL*qhE_-T*u=9_r!C+@bwOm7I;wRfBu
zs=|`mdgY4|J7vOeT#<_fN>R_5a1I%xl~S(7;oTp0+2W-Wp>YEhZhC6uo<IDMzV5^~
zk6!oIX<r0OLTgj*9^5%$6R7%2<6Dx&rK{7qEB<y9S74rPOV@(i6TC0%T~~5afngvl
zv+k2c^ve9>p<45nJ6P0s{8!8`@7AJxe+WCDtIFw^i?U!wo8#f$lF}4)ZNqw0FjZ%N
z6(!1cdE&KLk!g>8rNrmMiu7z%4f-Y=_i`zxBvOYcQf!kf>kh0&H#YgJJ8E<&Zo50!
z^}EN};jfu4i^{jLLEMJ3I5s!FVAMYL_I%$o?amZETc;Uq?&U8)OC}fCA1srkt=g!7
zS$@&C_|eIJiIXCE^I4WAe&d&%75mH{E8cANY_GfDrPG#?>?Dy~`TMEQ(q(hQKiO>e
z=?#JG;v#idY+k5=(sH8N8`AJkYBsiiEGwn98k_;KvzR$}9ruLnoG5>$wH*=N?I(Lv
z>W1Dj{uuhBAMU8FbMg;rw6u3NPC95e@ucixN|oBG9n!KEq*3xZ!N7pI*MofN28%WB
z<)XHB>6b`Hi-XnMu`%FeQoEJk!o4=*KajLzvaLE%P^i^cs~86D%=tlawh_oj(X%r!
zv-E98@ssz^`%cuS+DE<2TE(-qxW-h3=d8?{R}eU4H`}2^1!;V(D+!}y{|Ouq*nv}%
zWENJ#E2pRI`qzXl{^vrOx>_#IV(nW?`vmsX9@?Ck)BN#Ke@u7_*Am6-Nw#%t&@p(&
zJG?EDPghlrDv*7R?xHmWJ20WDtWwy;FPv_{SRN1N=?^<d`MrdsVr^rffl>sIrV$h|
zlhHm2V?R0NF)M_H4pvc}XzkXXV5XN*XCot^^?(rL#Kp>(1S1$;KxIa&j3pV=--xNq
z<*qP~2Wbq@xK*r7c^%a%&ZLD-#ek9DHP5bVj9e_RJ$H>W3D@J*2bd{Uhh~}#qI-@-
zb_H4Y+BA@``cJ@O?3&H-a$~S3_$76}wp7STY!N&t0dBUg7|gQ3e1mzO@*aP)Cxtw1
z;rMAltt}WF+vA;RQE^baV<1V%pTd+-7MCTmA<}Y4)M}nb2LhaN-D{<TbUoL3mSf}0
zl@wT&SQjm137efUH5sAfAH``N7D$uH9s3h-FoI6H?4~XF6l6kqCoVO&L{o^IQQ>|0
zIKC*<mO6!R0EQbNCl#Wrim!6ak-f0MhA>HM-Q4-riFhxvAt{0zvhmrL<#UEi4|cHI
zJiY9WU*HHY)$wvGnY53Sof~7)cnN%+9H8iB%dsycxG%t?PDig+n;3ztWw((xj~dd+
zBL12dmfTRQsuf?Qh2?RFXW*yHkDaA(*5O5d>p{B#t$4CAWTA>MSm6@cOKu_5J@S<&
z$3ZHnmo}+-?O};=Iatedx4h5+wb~~$RwORMF`qal%;6MJa@(UJYug%4Sm-APrea*l
zbmB1ejyp*8Ei6KMI7{g;HUe=WGc21;1a*9|ym+h?lf&)El`=fbaMlU+cu^E;Kox8-
z#R@qDJ);PDiWX@{^FH&je~^y?R6naEf_x-VIi0K^ghkAAqrIn57%$=_dxhgHMAQ)5
zf6O!UBE0A);-|S99!KD(lx7@B@)U%C;rO*=*06Asi?x=g60G#s-63d%imA^f0LN-^
z@;M&zuuIWnk4=7}b=BCJ%}t$0HyX~Rw?J)G6Y2}uBU{qM?_654FXo)0{iq^1&1ce;
zfr=};iEA_-WgEc%MWbMD6gVWzWTLT+{^+e>AF?nNPP6&&jq!wuOvPW{bfM1Kv}`K5
zl`<-~D3+W5r6r4R$Cl?$Rc)cH*_6M<jnp5ei(o><JZ{<s3rSP^5^4&ltrqTaZP$@|
z^j^>Kzfvfrw$xUMCy*;1R`@R4O-f?(10z)Gf29CQ?eNcX95_(TTk#(KxflB%q{Z0&
ziK1-B(oO>dpI_icDxZA)io#Y#;pF>8vpC2L7Mf2^L^?f<aOcWhAiRU$6ZP0Xt)l<=
zZaQ_;)|m${q7H6UZQZ-Fr3jzCAlU!$K1*g-Brs~|Whq}x;iJjSi8w$S>>K`aUK<;=
z<dUZ!%XPw5hlD57^iyQ)TQ(HR58K^3Bs_JbE1p%hPHfQ!aCnC@n7+F+S0#JS)^}63
zqOkoXl^WvN2=%|oB{Q5&K0Hq%y7wvF`$Kwa6zX_wQ0pd!v_HCZBV`J&pFV|30Y_mm
zVR{=`E3V>^4oW#wz<!Pr&K=yuLfxy!<<ne#X4A+QhuVw0xk}YaHk<$BpUhaP8()57
z+0tv;OGRL2y|nlWXYR*Tif_|>&#})wdtEK@>8rWhKc>^$82PsxDmcjO1+{h9*5qdP
zkMGKwH{QXbXYG`<!Mm-!>2yPNtoQJ@H@TDJVgfQ%xkR;9FDFxcBT6F*d-v8bijtap
z#dVr|Xt$Lmfe^n<Q$Kw!s;vs`3sHof<%MD#^aeHiH_zs-qaV(&K1aRj?zV<=xb17{
zgG1K(41GijYK+U%i?fUGP1y(TeuN&6o&dv6qf0y_{J<$9P&mc-wZvaD^?t5olEcZ6
z96)vcU@dEX`eLfXJ(h>1jJNYIv1|uTe(Kv7gs24Xessd7Ys=PXd_Ng!&lC3G{dURJ
z6?{D!wRK*U`a#%SYui&hSjoSN`l4J`5bWTXZ!Ye<h!+X|y(Qsp>dl7WQmR_<I#5sM
zyI;3fBx83+<2wojRPSk?6{Xq<Knu*{(jJ{ezL&Cy+UU_(eQao_f=;%B`7_9mu4Gz~
zSJlf}=3kHO|HNAHy1y9V7~{2peosmFhi3J~9uQGm6Z^`DwW?}NSH3M-^z+ke1ll2&
zhW!lfhtoWSxQNYsynTM`C(tloM^7PmXrL%&wMu^Ou%kjIu51i@`ywHXB1g+esOvzg
zRj(C|!f(kcnrjMIi+RTFrRf2lf!_we=R`^;z*J=OGAOJN*L|WxMu=&7QB`g4g0kg(
zNG--)!aH#o8v>%n9gj80h4-A5BOtUX%1E=K3=Vp09xDLBN5PXmuJgKe<7mi<Y;4ya
z6MHQVNyp~dF}gtkfev<ih++Vir@-j6nYo56@VVKbo3z<6fkp9MWLH{<9YdE;uV)B^
zD%vp+b9<2fB0xKJdYy2?K$B;PF8ou9v5B!?Pjklfr(@Hjj-=TTTnPAf0`R4JMvc<g
z2*o;-jMp4dHwbZAy_*-+m6r4uw1U+=Dpg*3=LJNz*U?O>l-E`(o395`lH)?{3(l;(
zLRiPpzzrKT`cB>)ma!_W%ByTC2FfXu7U4QF%wlx+D1kUjZ$3(ts!4D_W?<%(u7JG<
z1b5;3p{gmduNO;F3i`r}!B7r8f>YL3JJ<wY>ZmozM@Z>?XgW#AOn;7fc5<qX28I_!
zSKPKDE7>Irn0-LWF7a#9UW1l3?u!vf0&+PNJZ=KW1vEn-iA5X^9({s$MDY=&^Tl2;
z`oc0Xy)vM3SthLzGtXv&3$iQ7D-nj?1RgTdVXTWX30ex7B+MxxsV?xIctx7PV|g=v
zu*!HA%nb-7b<icj0F{0aIn%)pI8<^))Re1OUSw4i%SoDsp=DQj_cF^<5ndx+h3?y8
zg>QmERV>>)JPwhEmcvnlQx>n1;5o&SrJfp?I4*f)a-(eXCce(edYgx@{<(<BBF)Sf
zQ0LVLI3FXGrqxBk<)b0>jtOLqL~JS`958GU5sAB?Vj1-$DUrSazbSnCgX4T8+<9Tb
zXQU-Ns%oU*<wza;%jZeLqtBq@Ej7{)cv==zml^$3q*M6us6NOfnS~+DJy^&URA4p_
zxcUN|&4J{FNJLUrJ}W3m+L)R0;!R*xC>#yxAUyw3irE0OETcG8LbVn^WJ3+h8F;Ul
zt7>9S+Fm2>R;9fO<V)n{54YM}q?YmM17#=KGr(IBu4n-<Sqo}4ldAzN=y>l*B28_i
z*h?=OU|G`&w*nm^(kv>rMWYA2p{jDF(yAr{X~a$<1yepMsTvrpE?zR;L5*k430<bz
zh0LwQcJ4Oog_4#hT8+E6bR1or6?Hh%<T@nK)fy!c`vF(Cfaqd!D#3%DSwtsZ=okO^
zaOLoS0{pbeRy77j5m^PI5Nn{EDZhp+y<wD6S%awPt`kEPRuhRMdMBXgLoxn`z{Uu<
zpDL}Y;;P39l91{RBZ9|{5LZQ)B@(GqTk14vAy)i=%j6pZIFo>5L$KJ54t6J{NWp@V
zRce49%Uz3}-eZWfRXAoLan*NSi|dBKe(<4kiJoHzhP-w1%oL(hXoV0(BH_>{#Zd}B
zBt?Kza1|-aO#W5Af<iiUW$h2{#3&BIk_73c8bN{*=mRy+fHuw6HKWvMRwQi~h@p>#
z%xQql2q*~9ctXH-n`As88Q#N8+G1ME=KFon*vH!jzRmmEHUNb_K>rSPj>SS*i}&qN
zMHtLme9p#dVFDg@xfq~NuQaP+Y?~4RGsYccayS}DT2Z0X7knckR#gW%Rn-AMuc%rr
zgcG>J;$>m~xZ{IE3HX3PhGQw~Uiawh<kzL<3B^&7ijIwN7P}e|hJmVCXj*4U<j2|~
zF`hy#rS18T;OY-`Xp!HxDkRfA<i{An&+&^8WD=0yLdNc-K;|MUo>4(D4Z*N5P-52T
z<tkp}*8{w|LuEwZI$19{_I9p3E|CEQ1+-*aABKVwoO|8@#uLTZ`_4EMG!K*Gf#jtJ
zhYEA4NU(M|sk}tE&|L0DI7_@7s%{~1E>_(Zr*P^uXWABG{cz01PUJ##kdQ=$Wb-(Y
zHU!O9#YhxsSAxedGev#&waEGgDBjGVPyQl=(6Q)o%rFE+W!oacJQfvxRV@|SGo_l8
z#qm3a8QkjvWGYw_V^&nU{8Y(_5x%uE*+D+RBW$QliRh~-CHoa!=;WzQq7L>|VXGW)
zW56V6O-cwh#G$uVQ0P3`gP!6u4OF|-)3OnP%^Kjk+_!O5^o}McgcE`n{Te~jC>w4q
zO8y-P^Chx&_S6ikE=XflZfntwx9@#5ZT-@$Z7WH_-FV8tXm%(os_hbSwlYte+I+mp
zmbeCnUP9Y8Kt;dYlIoJuS-sJwNE^rm!&Z1rMFZ2b$XYob+-#$*9ggok=6SLLc>=O{
z?B#*Mai~W)mcHLhMgv4D33hPSdCaG8DsA*TFJ$Xf+h=bxdvOPo`&xW<YE8SN-D<V#
z0cSt_m*}A{;C=IZ@NT`0V*EXp7r$Dan@R0G(-{goqWatt-*DKG={*u3-T{X`zpZFX
zVYoGk!$v2W^&jD7<aCZa9_h$JWh}V)j%053l{FuV?*{w$q1Z81A-&9UzV5WBu3IUW
zIp`HsuEXCV18kQ#9EBG7Z~MXp53-Rn-EOYb+_26cGJCHoqmGSP{fB<6c-Do5a#K?F
zO0E;;L&<`#l5$3&?B1%f8oK1UG~sL-0em^Y9ho+LD>BQU%T|1Q(AQP2l33u`jcZG<
zsJYfyc}48>6wnjy`Z;Dv&+%5+#AcRxUlwa-gPhc#Y*;aOli5V9Jj&bDKbZ4BhWO)e
z&5M2PVT21e<>?)lFl7CNT|`i_d@tN+ujjTi&F=dNFUmAF<>A41kSmu2S37HX&*t}M
z8>(>iL#WEr+oAf4R8vW#1EY<Xv5<P^sm8W}<*)s4vY{8q;$gnxHK*tEJD<*ya`#EQ
zAvZS2UfJ|Mii=Dpd|Sgm`Q@LD!XAm&z-T*d^=xO{+F_fbt_`-hk<;a<*HehDvrR;~
zR-n_Nd;cqk3u6F&+Q@N3kK+5(FqgodK26_YMXX4*&sVuG=LYS;t<Sm+iJp&Ql&u#Z
zQD4FA>uJ_uNaJfH686-Cjej9zHEl^PFH^PZm&H0~#rHT{d1!l*UeQXqSeRD6?<cjv
z1rqY?5wi9`L)I*7=|drHJz3*>VuhcjUF7%N^MARx3)PdSDsXDkl@K1MJMdd-UTm#G
zdE>b*d)iUpWH{M5vl`IL5_Fi)?fqw#g})=_^;;}X2F^0a=6I=?83(~xhuD-f<BrNr
z)~Yro_HoWY;q;Mn9KbW}7keUY5QG>ug>3DP58WN&c{9sOn~eQMU`2`Cow6y-uXB-e
z^(mpRY^_qa$$87#XL(`wg=YH=!xhpelO*x~cNrZkEE`<Mmlo)V(Q2v8*)<70VQ2rS
zc=Tmi(mKhQ8O13@<L3MSg=@u#8at*7ICJ^rsAuQdzL_i(uEE5ZFEpi1amYP15x0+#
zIW7(_={{^u!^5#K&+A}m6ThoSOHFM<5YR&xz${uAfox&M3gcx3RC&;4Iy)+m&4^-|
z;;e$QAjM<DkSbYIb?DA}i5mC~$3AFLgpfC8Lq&0gHyorLVWn%)ViWl7O1JHVuKSoG
zWC>1VYbbC8=;%m|JQV0+2+Aq`MLqzkV{izGc>--4J8#QG3vvjY{Wi0IEJI}7>mb;K
zji4X|yohTKW3fsNR}XOD24$r;EcFgv6Ut2>)>1}mPILJYsfA3>gJqR^5oJt(%bx7S
zLeKPe4iz<u!0Mi>9_YA&6lP$12d(#m=!rY}i^x!jnpB#RC^~~RNMTMvC)K@q5=mnU
zVywlNHWi}JZ)CyprK7Tz_lZHV>xx$0=YYlWBPAsqAs;6Zr&Whi7W`nLP?zE8XoH)<
zC#$t39Ziub3!Y>dI}=Yz*ZUNrP!J4EFX$0u^alS}SDeS=Ik=<!4wnqMp5)WX<1yBC
ztKSVtC{lziDD~wAIBQ22Mo>Tt0VK7KSCS!hCtrNR7}+UtR0WNtFTi9hmM&tz@)RG~
zjc(3%M&PUqFQAhht8p9$@vk6BN`|*$F7BqqLDt+O&*yhtk;ED!clJ-A6-gBI2`O|p
z1c^V43NV#b_@QCGT4<W$8l^n-VF^*y0--bT+l&J?yRDq|ORA5OY#@>G7D$)#Yx48_
zR)IQ_(VJKA1~E`%ZZ)Wn1!e?QnZP0$t{k$jf~Ok#t}9wvU6)av)lqtic;j#k^-eSv
znW{~w=q{s)(VzvaR+(0%%=j26lll?nCZn^bQ98EwVrBznOUxkj|DUt>f$prj?tAyW
zzbnm^M!?k|K;Xd~34vvdjrfx+VpID_2oTOB`QeW7IKj<tri9=mO(*_W{9=+Lp#j+@
zsc^|EZtUb|O4BiM-HAiHc#hj%FiuI<yu68vUE<}odRbmx6UWJ$x-^}-PTu=`&%Iaw
zM$%92mVWo1Kl|*n_de&Id-nNvxvQq!4uPqekING)cPxE80bLYIq^D4Uj$fcwYP6Kk
zYf}};Ke>Oe<+Eau!0A9MzKmPn+1MRqeKz8lNllajlUWdSX&0w$@yjQkh^t78Y*HET
z8omH$_w2F$a!6kl=KVAOSY?6U;wD8TkM`_el)l*$k=GU_@1^n~`u^`j@-yS6lL>YQ
zo&JK=jbvNvRgRDy8^Q8(38%fdD&o3q0Lw3=AA1CUvxn{|otf~9S=5<3D*TshpL$!p
zAfyjgYg0?l!`=6#xCm7`9Hh4t;tIxdNwlwE=JK&D(6Z{iiZa@-O;v!-UK+Q7Sk@Q$
zU}poJbuGvYJlKzoEn4XCw!JS+M<b(3xjj6(a3d2`bE%CqW^1FDKc(-O-biDhyu%+E
zvhD(cl4~v4(Wj23n29m<%im4Ie0hic`(}|?f&nwS{}s#p3N3}$WQUSxOI3D4JM7X&
zu3+E)S+d2}-4%o>Z3=s{b)C?qSzz>OC{$)^MvDoMEoY-T>zvrb+BB91s!b^8-|R-t
ze?@w=GW-xj1N;A{i|+s>*#Y<#<iR4D7DhB%FVzDPi^VWo!-1bBLb4U&hdxH>x!aRh
z*mM76jwRHrcd?9sBi~4DQYhDc(4)LG%isD-xxQ6VVzt{u_Eei!F6Hp<rJ&V&Qy$cw
zaPn%qznp;T=jb@c+EXWa=Ej@K`OB}ixxe=y8;w-PJ!!!?$BH5gU&Cm#Ax>tZ-ci~C
z7cI~zB*mp~Mf&qUlvnEyrR@2resE>Bp7_!Q>7mOXB+<$)n_<4mLW83voT>~JqsQ_i
z3{1@J<?~EGzU(F1GTGYV7cx8g*;dFtH8@VQ!71QE*J&?8Sy|*Ixp<9NSP#fBTYu39
zM~2y-OjzHGD4Z^CP_ldb`|PPNa-g@0OCi;2OL@Ndt85lzoM0vyEHcd2aM^cmXE8^X
zbr=6#GUaTZp_$ySq5%DKFEU_p>wa&PaadTKtt?x0Lw1B<NqIXNc7C0rcnoZ$Y=8rr
zIRou<KE78QpZeZ7UNurp^tSh<K6)T%&)&3%k`hNrz7%)Boos3ipUKEq5Vy<bPAyDS
zL+rCBqyW9*A24Uj7Z<JYKE8B%CI<GrID4u!QnlE(RLDp&(!L_N@L4up9K9k+mbF%R
zX`hyXx;Xxn?Hdik)hi8KtbWN1O<+&!1G%w46u%uf$ID_cRu^ZVNSw9r2(DJ)HHQvB
z;PMMs(>m4e3c7p<3A6R0;L>sG^;DnxmLdiUTe;4S->SOhMn_%<pPXSXYte=}?AVRQ
z`0OmI8sdvr6`k#`F3<bjfDO&xI2i1$3mXuRA$&<m&s=Dog(;!}0lNXmW4$EAIqS0-
zi;r8^?xf;8IZ9|vWgIMLlTt%svpA`)N>szp7|(iicj}NGZ!|Pf*bsZ8a`r_VZ`3Qp
zO?q$yhR8^|P9&+bdZ?%oY?WLW6=Tl16xtW%;yKfZVG^M+n3m-i_;_6}*hJbKrqE&%
z5=)!cKoC|AR^e(jXT?OM2X&V6#5xJe?ZVq_Ik=cAC`Dak<&>UyNpgRZUr!m8AOfa#
zMDDNHieW(^kP6Y4xOhxtDC=nwr@~%LV_dw%m30}3urnwpUP`@TD9nNs#3>myfNj7U
z+zF0}jDZdXK@iFMZNZ^MzYe!fhuLZ+Ij`fVp?1!lccb-1_8=DJ^>wll{ObRDek?dy
z4-Q0Ri!kfC^)o)`RH-~MU9$xtuuQY-R9ng;=0eJhx773p^Snsbo_nIV1V=Kn&bEq^
z)EzjL_@U-_OG2xGT^Jsj!s}LpDhCy_s&oOrm&hH1s-9(@4kx#fL*N#{m9=A6*+K&2
zuTHV~rpO3$T#t7u_wWRFU%Bi0wIH8PS^7D16DqQuVXzqJn4_`7kf~OH#mXSryrcn`
zwyFUhv``x0Jkz{1+~B0+jJm6B5KM|sWjjd$&IQvz1Sm`ySSocwmwH(}ghcEBgNwdH
zw2C##UgBs}tALKYLvZq1lol}*uqzNYCE0+#zj3X*PfW_Qiq)x=5ivSV@UF6z0%GNC
zQbihw(ufv>A@w<C`MJ}H#j}BSAOP^XWFYJcZWmUF|B#!g(-5#Ax2p<Fp?wTY>ked2
z8Hm$1KNy=@5;I*woU(mu0yb@Rd@I3tdKj+Ku9Z1<>w;YmN-vlPK@z)#=3Q0?u;9Dp
zPIVr(xxW8F1=4Kmt{~ij_Sl2Q0VUqb1Az{vB_}OSI{ns$apM?KitmEl*_WoNi!GON
z5Isi{9`Kct%T_YZStd*w(AtDcqCHKr9uOy0Z?q(qZG#JiqH{HcS9hb}hd1tbh;|o_
ztDT6VbJ|M*N5Bdj)Q<KSf5>|$F4%~H+g}!$ZH<owTHi<A{}Or<_I3Cf<WHGx^-b!w
zz5k<?+iR=pW7M%QmR@8w_FVePdB-R?)bv1wu{V5y(S)-P2YDCg-^uk8svj%?@(0sh
zC?wCi3k>qhY%QYMdPbBgxc}pcOW)KgM$i1U`^Lh_bx&1;an2p(#4SvkUt+>-QTwFC
zk3N%u0aL9KBf{x0#)Wr%(1!gJdu`--dhnoz`0!xTI2lOG`dpx>eeRrWHV2UH6Ecrt
zwq~VKd*=CJ>lB!+#Uvk<Jnoe0@cAy^|5pR^<w*|zpf=BlJ5YkDT-}*rTgGg){Ox(U
z;Xzi~&EQFL;N3Petq9E4aO%>C66P-$@_#tRc<X(<H_3#Ln{(lNkLHE&Hp-IOR*bET
z=W&8PQ-4E$KqvzrO5^jZ*;ZNYV*%#u;cK%_=e9k`iBDgU=J^N3aS!lzC_j1Wy!kIu
zw9K|n6=(IPh%n;5%V_gFCkX$GyTerZ@pTV#gR=P^7^08XY3o1Pz|G(DZ4~B_>lkKh
zDGRiX=Tg1#RSL=Dze~3YBUPnP1cYX(xV6U#S^f`iW~=yzP@AS`djZ)-`!-f%qz((D
zpnqxCzI!1?xOe=dg;;>p66?QapZ&tuK3WX`sPMdg&?sc`mW#v1zVm;tuebIllTrIE
zc6U1I{!b>HKg}B!2)f+cZ;3;zDlQj8GD4kVue!h{F<X=8UTS5IZ0$WO>LyKO_S9QM
zjnTto(l1|nG_%7mvd?VcLCbzOv^cIiv)ie;5a|K;v+e!&AGM_W(`30<)pT8gR(rN{
z>1pPs{YAn0cv^P{LVQUFJ-?e@ZHq>;^$d>@(A6a#BU)aAqi%O%pe|`jNHO_aIA6_g
z*V&$l6EdQ(2IUX%N;`vSerUQ1U18((@j(ib_A*&RtOVE2>M5H@f`vD3j9rhp>h{j=
zw(4sbMfwRguX<KBG;nAr4gT_5Rce&vI$+B0G6poYNB`;msBTZDUhK5Hf8WuC;l<(d
zS@ZA0^7{r=)gNP~C!MwY-p_=*thOetBe<0lTI}^m!;P#unoG~Ap_5cM!+?q}^3EF5
zTaj7|o35OGHN=^tyliYWfQ)o{$#U@MkT|O@a)6|s!cdYCmZ%!<68btqR8s)YG60>&
z>8j!@@_+|WZz(8DR^mC}lS~EC$M4~DBF_mJ4{BfUhe^>2Y9C%!@){g>U%NRL8duaW
zue&8i*d$x)c|!cfRH~c#iEE~}Lqgv=D`w1(%~i|?l9p3kSQpDx-ko7eV%M;j`+8Bk
z^wPVk##~@wH{h!*vyKf7!@<&G8UvQQwB}(w0m<kg>e7BoXA~19jwt=!_}T_ljTg>Z
zXpGwC;t3zB;+$?nQ1+RHrKIc6$6oP=Et_vhc}&;bp;rYg3w?ud?5s=Q_BijRN4?^9
zg8epF){Ik$DrjiwE@k>Ec=Hw69APf6UNOFK;%0`*cwAlRF$-Q@zri6m>@+oyxk_m<
z<JSXb<AC<o+Uv+jqH4L>nn>tDtce~>HM<!Sw_)j%1XXF;{kjN#2B|yTb9p4z2`3kj
zG7U?AaWoE(#ONw~=j+>~N5SL#Jin6Pi~Ye`GG?N}D-6fHHO4iux#wd2{HEj(3<YWY
zz+A$0XDA%A$<;ufUaB5)$2X-2FG%F2Wc>@`RR~)~p@ScGEUV?6pt(=)9bc4BS}sqd
z3>m1gpL0{hg*r9&-P0&G%C;$^jb2~wyVoKwUWHdC2C;Q;8*TzRu8m{$^qF-C8=YdO
zCg5N!de>v*jfdFCZ1j`qI^QIorxKe+q+%vUMWmfBbw11Byoee@z@Z-y;3r#3ZQfM-
z1s#4~`kLS;2zPO*ANClKsVH^<Ee}%R#W0ZcNr;Bwe)~b0`AMXkt+Ep_!@!fV5}31b
zP$Kt?9VY<_jv-I~89l7LPua;Y!Zxic=t<-Z)<SDljgj0Im%fbdmYO1G2a*uTVKs@*
zPb@GP@)P+2uXaAkHVjTLAX7Va2M_9v$>HQ(7eEUOPEX=Vu7OVIDwIPm_LfqX1V_25
z7*1%3Uym%`U%2os&Z@!a><!8`>`8qh)F%ewGWMA2Br_|g-eAk!KSw(&^dm|-9RA?=
zg60++C@g@Z5W^)Xp|))O(c67yzua}Jiini9xVR6qx$&1BNdd<ZHJWXmR58fFWVTgi
zYb6_B#Sl`cXfmskJcjq+4|uL)%<YcB#N1@cj7WBAci-?L1qo^@xhxM)C*3%#(Y+>n
ztvxWXRGCqV+Xh@pYBzHrxtGRvg_;%qcAC&)2tAuS)Uv^ace(uKFBhlgzc@0y4Uvt(
zVfb<u3~+SH)Kl{qk8$mH!g-@vC|^^(Zk!TmktK7h(fo+)7t#hMP0-gP-6L-guK1lK
zmC-5mo}hU?lZLfC^)Ar@u$CV!XZDPRhi{t0lHw6P{049NS6FSZ@=&$rP6l<fwBzxq
zq+yY;WvBnYq<66@0}zA9VMl1lE3?&^a%Z;H+V|B(v#*aSBQ%{&3w7Zw^Tuqeh2wit
z%f_wKDHFRP;px2ggJYgW!Zwi>ONZLsEY6oq&bq1bZ@N86_~XGmM?+3Tc7%}n(WN6)
z;QtE-K7iS}{Ko}cxtPd(DS5&^{Vx-D?P)sXf8Lslm1jqK6pZhFG_)8@&?g})g^^<a
zS5;iR&mh6{6A@p&B&47H9xdSq_D;vC?M2E(t7HqldE)=+mj;u`=Cl`SsTcTZs8_SC
zJc6M@kA|;*@9Uf*9NBtJ>CXJ<^_k}^S2qda3}wfvmB3l9S+w$rVGHnalhGvhfF#`h
zIxlU7R7{?pno)wl&%cim%84&J@5Zk4RwCOtG=*xv)*78!IB+!&Plr6e%0SGe-|0`5
zK6ZyKjyV4*rx(Ok*A?CTy;S-qTCTIOZ0&ttv36KwmpW8pUmrr-L*VSX1Fy3i-Dk$k
z*l%FR-?NIGCO<{DB5;-x%T@RFbsf$gP$t$5UrX~WwzmvkF&M|ikC*>y$!YcQ8q8gl
zw7a9jAMpnbu_^F~N*kFb_nFV1y_iP$Qq*vg=w3j!tdF6+i`iBWtx^RUzUlFlR+iN_
z1Y|li)w(zFI^#hCye|8ccCsoCUbs9r4nCZsc7!K*TD#ig#v>jP{n}f`w+}4O`^(wm
z|KuQT$V%coG;5%~ltW=3y)-vDH&OJBeT#^8AN|BxYQN1`-W`XXPkLGHA!BXYG5gl7
zWjgEIgQ5~@I@{kC^O-gsF@HBGLnyb~3?IZK`2_up`Pa~6N{NHL9^hj9z8W(){HvV^
z>R=TeaiB#7KjF}3I-O7=SrTiZ<E>)zS!UUox(i-tQE@TVHWycis~K1YJVlk`VyVE$
zJ*1Wi_pS+046r7euYAq|j-4SjdP|Ot?Lb<ihRQ)EwYVILC*tE{udOk>bizebS1B#R
zl18Hg-mCd}cG1agLjew0w;7{GiTA}#iQTR!I~K1yUXqfOS%3%bi!QN_twC^Jo-P;@
zyxKiV*#(5~)csUDS!7P=qzZ|Phj^9p3qFjX_8bwYM(PL1Ke`v>nX3G2eIEtx1mQeL
zjmON^(7IU5@-20E2vJ^~;z>$j^~Xk8LDkrU?mi;#hm!zLz0KBq?0H0}mMKBq;f|M>
z6YdxI`RKt=^Yd7W1Te<HVhjdkRk{nF8=4Bbsh*GKuj77EYHkrGb<$>%9;O0ZCS^k9
zF0|u98PRvTWP#YQV7gT>-8ejS=PFO0EaHgOvWea49z_WxZ@?o>x+g4tP63OF(?~-F
zaglH;w?gi(0yQI<C-D^$qngm2?)_wO6GbF4>lsam_#9NK94Y6gMCB?p*+xx49)WDw
z2n}OvyfiUe+$UmAsJt=dv=9`C*02TxR;gX+4ig?ySEMlGC6<e7ibgZbAHWncDP8X2
z%ua!3{k}NSXXiVb?M(4b346mLi<pGfT3J&?BcVcSDn+;o&l-x7>;Mg-k0rBaAg(6q
zG~78joeYEr&!x#uPQ5O_PoOWIL=sK@6`hJo>}Y$Y&m4ZwuOcs1ZVBCOV^-05K{ayl
zfCs{h%FwiAL2k!D<r{>Zkl`fvu5w<)5ewhraHu{c6d}>tA)iJgR{T$h^u7GJgJp-}
zBbIVj<{)L<3mgb87m1AkWzDvFLKj0|S>Uc9HebSIk#M>q#r(@kgp(X2=!a%1<8baZ
zw2885@8hEzE3dJj6xFt)2Y67YE~M|ngJ)-EtS_)gv?qxD@Cc3QyYrB(tVx}bt%W<d
zu(#D#rqSGV@b&;0&+hRo5++7w>p2jEq}-jrNxlch?4qd)o%xU2^^0Gs%K5kkH?&9?
zvsE7lPuj<SG}BJrKeZ<>j%8Gl4SVeMtR1z1VOtysKb{WzZt<cWRE2&un~2U(A5M*z
zK5+}){yX1L2ikV<p`|StR@@pmIWz3h$+fV`1siiriFrumqak#{W`u40E+WRYz%mn=
zRCQn$-walMm9?Har1br-&<P@f1+U&ZcQTtE`JCr$$!N%uZTpTZMyhq8C8phOAex@%
z|2s=2&dgWM8L5WJRuKjK6k}(2nE%;jNnG0cE&mTWu=fi3YTtxOWq`ny#uJJnsxV#@
zwGC)D4_2g)6Oq4tk&Qi84HL{ETlljnv+4Utsa2}>+M%Tp?Z`a*;%hQJeyZzkfqlDv
z#057t#8mB7SL72z-rM1)2eXVbTHS?boqhFw9^m~e_A&R@u*JWB?FVy5`kf&xGa`8_
z%H^EcCOcC2n97m0gH)FPgmnoDF?7cZ9D`WZ*_*#NmNA$RxzWUF=k(sRjgXu&>#7ym
zGUSe)oiAHtQUoPE|MTRD`qLY)NH})O96OptuLsoG>iZb>rqiuf{Bj2jQ?H7Z(|g%L
zN&&>F)al!1;#nk}*(3`s=Ele*^N?TL{wkIqKHR_0;A%%eiu9Wwq<eSvLS|bt3tA)$
z1ho<G>z~QGU!)Uv{i}#Uw(;5b=i%z7Z>8&bT{U)DTK|yUQLxEz(XudoId9T26!S5d
zWvnL2KQwRmkM{+`Z|!ed_Bi)0wXdTZxFdAt%pU!ab#C}+(n<`Z+yGDr7A`atv<vVX
zH1Y04W@42L`!PJl3{j`wvhV@k{zMefko$5=Y+Ee7r2B8E#x%s{S~yfa&gj+y>TJ8B
zZs7y;K37&5DHvY<H0eWZ|NFkqCr~1_2N&Auv+tObys{!dpfn?3*(NLP+OyM5eUSW~
z<w5^tzP0-sclosaNE{cok6xM%wttQW^YSDcY&2lqL7L{bljh0sY2{cwwoV)bkHiJv
zR9a>n^-et65NlV2(d4m!gGv$JG#?$hXnJaA5NBbqW#LA@6Qa{f*4=?yhvr0n16)Mw
z(<Q_qRaB-=LbTVSvb`SKYiR-zwf+h*pG^dPmyk1$`6N1`qZWxPnb&Mr1zze%LtWRk
z-fk&Vbro*l1rV{iaJF!RoI#h~u&+zo-f8f*s{T_k2M0>vM>eBDoZz_?UM6wMo+IC^
z?i>fO+SIZ@0ftz?P^1Sp0<lWo0~jwWKuILr)_}=fOl%#sQ)tUaeMwtEx?|dNrXzE;
z<>owrL=?{YL(JF_V7|2Fyp*493{^-Yi=ul$ZEd&=^T;>IED{c4q0$9M89pg@p;hfS
z7zaV&aSG8b#5-ngSasGRTi%wcP)cKR7N?)Av3Sxta=yrqg|%65IErIj3~{7v**Fo7
zI~1ZvhEDZ`;#09fUrS_mepx-Q3S1))D60(Daa-K-0i>A=M&q?5z=nXsvA6~~cLY~e
z{UsrV1Xk+w@;iPkcwHu<lU|$P>+p*Zd6lbES7eq5nJ|1Keni{$;;I<0Oq5KzSr1cE
zQw=UeM=R*yBO%uyOK}yv%*f8FcN@pm3eOVF+{zKJm7|z}l|Y9xSsu0Fc8rlSI=CFa
zz>hlYJ*-~KQo5r#so5tK>$<a1m<fN3&-#5-L^eqq7sRc05u_a)JHo?a268R80~%E(
z7Q<$3ZIvX_sZ}((p-?>N<P;k_<k=3Qrs1kD)>OA0+E(H4m!?WTyD4@|{)(AU-MC8f
zt2QC7c`-Y_4+s-NhUmVw1&YKzhL4^_TwqhtQNB?&IhGVg18c5wD3O;leT+*XekVvR
zaBY3I1&E2cr^9uO0=I|0*aEE8@N)_;x6hsvwhcMew^i`!gIo|_8;DXA^hsvBKbsVT
z_b>%p>KuamsJ`W`^anm36hbb4Q8iD6|3x3^>@H)?Hv=KL20g9Z7G;@^>4{*OF=i_q
ztk8Uff%v+2qo2RdckP++3W=omv;DP(3*h1D#<RmcDDLjQ1oNJAfLSCQz7(;2m&Z3{
zkuV>X42b1uP%pG6=`BU|(A?St-^)NHQ?rw-gv&J1F&67$7kNK19P&=TV~!(ZRcOom
zC`o(Tpu^kv{o|zU0YMMYK}4QQT|`~{W93?b*Nr%xXrBgodIC8HA*nvS=Pw!Alr0LV
zbeL_W2miXo;^<Qen_kc7Y^3*2Yf8*b#|?-q688IFDQt!s+S+q@`a>j|Tc#FA3Zk+t
zV2TDsK7M>M#XMSe@F5jKp^(|yt<30YEB>ymWisgay_x;_n`_QM4Kk=54v*29jlPsl
z;NBV7dX<g-EOiAt+xGP{hj3|3kYC=9F*gONpJojA2y-au$60aq;h!OdtPOem^2eEV
zO|p<?H!pEU)rHRb@@d=e=ZnrCF~)oY6V90WzWhuQY{=zF=Np*%NM-q%otcWU%geSf
z`d8TvKQ}=SPU;)}uhrwCf^k9-spCJNxVP4Bh3yC)6;W&~$UI(Taf|?T%+?7CkSV8o
zIR6UES`k^_n{Cty9V;z-9CNYydL;Pz;9-!ht0`I()*JlS-(mI>SA_L@TeZKpQhMC<
z`c1O>op({^D9xj<AQ+j9#!OT$lAdZ%Rm;Ur=$&O3lox)EA;Oc%atpJSiE}rNXe^T-
z#%yIq=8IO^kNmwPl!tG#*2TX!Ua1sm-|*tCW}T7#>_|Va;S>KW@yp}S@bZPTsl!nE
zua)?&^8$4c&a_affF(LX*Z5c_JF@3lWZ!?2^HaZ`btAUwIA%g6r8JJew6~8%p~>(2
zfbfgSq#C{mn61$Qz3Gw}))5?wEh2~J#kic^8aS};bV!qOB2R_rNTxGe41h(9O_$KM
zE}ziI`<kUIif7zT6P7sk(0k!jqvX&uK4tsmIb{-3O~^(RZUSF1>~kNzJ6@P9=umpC
z`@s5*F@_BOeKi^M(LSHF4~(%}gHFa1YX0uIAZv%qqHOJGlS(gPkb!&e$n&CcdeeG@
zB>tUj=sWvSyszeHhsU(~mC_VM&2%sD8e7>JNRxH13rV<9<yk{x!PQ<*zC8&wX-({r
zLYJVi&6si!l>>20S!J#!<^ow}o?vCIWZ8nFU=>2Dz}+dPPyXFNKfU#Q+&8GA*g$3>
z#CIx<B@EH6QQ?8X&56TwK>@1}EB1zv)u?q2Ef+$l$$IcH%Af##UgoPDB|l99`iR@`
z)Fw3h2!o3R$Zd8JJUAu6kw7?S15Qn_W;~)9I8k4fZ~H3?$T5$jfZHGicHxP`-9r??
zTCNE7xy+@~4h0q0qmGCPa!e{LBB~0>qQ?9Md|=V&a7Vx>S*d$3U~a%$2Q1%mtK|`(
z?GbIEgN6tVrg>{ZFdS@bADP$!Kb`0U!a7){7wP@FfGwSc&6N~{<AGfdV|ctw(FkZj
zX0(NQrpv{dmuxD)X5fyTgSA=8CKgg%4vtxH^Fqev=DH4EU|dlpwlm}d0nP@IGOQu0
z)gXJ34RXYX49E8cJ|yTj+mvR?&UXRAwFR_3mY(s1{F--EU02sBNb9=>59abQl8@n-
zsIyM{L*$}pNL?N2wS3H^4YmsW9MD$j-T*Bmsav-aI^$KEWQK8wSy5=OlJ~3tw$yv9
zMRdxq+g}d5!us=&oM2wv_IhUro%%{5>PivrC#-_5MOVhN+Fu84e_NFB%vkeeZHt7Z
z9KYkSEy9)&o=~TlL%OVi!+9uK^HX->Vba*Sxf<$m=~q#ZW0x>2Rj!vi;6=57YEojQ
z^YYZWR?ZFFR6!V)ky7pJahq}=YYaON(QJh}DUb`3la@B^a*ZIb6isc)=aj9lMVw~Y
zkv!TKQ$uD$%Rh@-X@ESDnm|Z*{Z>l15==xYnhWu(c+ubcvQ{?FybeaLlRt>QQ@3UQ
z2(D*-xJJ4U4;Eb+yDi;MI=n!+mpAdN(aaen3VT8f+}&jft*l(N5x2Z9^9spV&`0;j
zoZN8puxGY4HqEv{dTBBB@1O1j96ceun|ZTmSz~;ZxuD8yb;%?LaWLDOXCp0^IE=L8
z6VtYrg3FHAg=FJcVMq5Q=fzRsKWNR{*&pT=@!)h?d}6qrb{@88?dfrwJalEf{{61$
zxIZGXgRKu&yRmlU&0C92uy${gU4u-Cc>dMtO1`{c?I)Uu9`~vjPHH=P3ZXC|fcXAi
zD(^7+EPHW(VTA~(67wU)=3_#TY0uDi9U+AJm4|}y!9%tr=3$=M*7FJM2|*YKu3qrX
zu1fi(PfopcLDGzC_V?BURVFLnx`3|$GySXg)PiuuveO;Tvbozrg-5_n;78vv?K{)A
zVx&X7Hd}3gK|^L+oy=A{@^)mEwAcO>>${&$?GP%p<t0X%K6FVj`NCm_x{kNP<o~>Y
zkJkJ$_<uz74Hr85iNCfCv$cBLUiA$~@Slx-kgarJ><patgxP9GZWz#Bn@SNe1*?){
ztrtT}-^#t`-kTgqLX4zt{_^mwtW%|`jYF5+K?UYiT%)+`8LTvwLXoNPh1z2NHFF}M
z5K28}D}PUreVaUT(TpAX-f&jc!Jw?W)Ems`D_EP%sYWZ)x25!8D8Q46YZg7lhj}cH
zh!7K$)qy`-G$+w}K>t_&%(b-IJo}T(U;E-zA{{RO{M$6!O5R`0hexjGT=Ot|8@o@Q
zW~yrH%KQYfExkzfS~<bCg1`CY%$A?t$2m+ae7e?I@`Fcs`C{4Tank(-ULF0*R<yr8
z7&+@Mz6m3t2UkQF!;4Q_(iy5MLtS!C>0%*D1(;RlX~4ceNbHxAOuHkHRIO|W<1pAM
z9!bM~tn69Jj=5DoTJreDka8%l*C7QKB}S(we3x*>Ty~TJJA3!4*wXQMW43CxH5jw4
zRpn$Qazj|pbm2Ob!x}`n*Sy=f+@Wweo%Z_}Ir)uY`&4^R{0wr+^ETLiv|zTCbWaSB
z(<>jgPFFqAcfk|VF2~%CUuS)1_BiW)meAR^nxl8x4s)PQwZdSuxivzJwdL%Zyu`_f
z$NBco*r-R}_Lqc@X53;MWZD9me0K?yP)DfFg0kP|<iXeGO5M@H@j;G;VsP+XYjKj6
zAvz)A!13Vk4hm9u9u)ulx%jDPS)ZY^dWIK_0PzTEeP6w~%H>?|f{pUIF(u$5e-%`9
zrjk??8vj~86SY`+Tj^^m4&i;4@Ys}`S(F|pQHOLn9T6W$=7ln%X+(kaxR@l-z5NBn
zOCKbuF#RUfj{FU4r98Wbmh%mAs7o>L7*29z^}49KDqD_*!$U~P+tA~3yqLIsAK->U
z0d>Agr!$pn@b$f~k}s$?d}U+w#mHzXMy&CA2dTr?F$;c|93V!2tfrAlB@a%FaIX+{
z>1HD#)rqnA=*(ux6yi^cdLAsrGEK9Vmk}S$NL7Bj^9NAD@dW%Kn_ngXw2GWzlq?FR
z2c)b}_TfbuD<y^Wxxion|1tX9$n8T;z!qFYcD&HkAlyJtHJaH9h`=VMSi&+t>~Iwp
zjgk3iyAlwZYSlz;dG8NFV;Bsd)A-du?&ieAR4i)O7Nts%mXDbPG5Nm>nPx<X9&=Pv
z2>T`DNkW0-8bos1q0a(SwOV3&gdokQ6i7<8dS{jl!K0Qq3!8)-UPduneYM^6ltH{d
zP_~Txr`E;0dyrToTsm7P(Hpg+OEp5VHPZS}KepZ{cTn;MQq)?_a#Vd#!kud(t2;^(
zfLQ~Y+6}n16dTby-a#(L(jMTB(0jGV>NruI;+$Ju-CSLaUEYuOwyH>R4<Yzb)(o&4
zF&LmaMq8BD;>31hpv?(_G4=qlU4H4fd7H-(@gwEbl2B(MlsV&B?g5-MD*~BJ=S|RE
zQ`6H#cdquE5O(%DM(zt&9;l=^iAZq=>7RKww8B8Rsp}+IK0n(>=b&Br9++;+Y<(&`
z6RMekMxH8q`>XRqi2ntS{-;y40S;bbPt5;0%cXuH$=WODqgK`?k4#=nq3FyKU}ytA
zo<VkyuDyFU$FB1qvY*W7Q!H<pt;Mk~RZ&ju485gM&9;V5_?S!A9+;-&E_RvyXR@YW
z+jsO5H*I&JAj%*OoDq`xB=lp_jC9y*m!70*AG$L4(}4leb{|hHkQ_{Q)p8!6ImlyP
zHH1pH2A+xrWlNWzrcAWRayQTw5`v`a_B%T20!*3%I_~wEUww1ReCU`Am@3PaGp}>$
z^ZP?Rml$W_uC)A)E3&cTEVV5r?|o^%_?0V`-hjb$!~43d9l#2{7S*9{3nM?6+4-+a
z&8etbulJng8YWksAufGOobL)T6Ik|6872H=kL?DM$v;dcqUHTL+ESUV(*3VNtC?-J
z%icsG!cVRbzjXfKH4Nxo!CURDxuvsg?#|w?=I}y$loNgYq|ej)-@q=>8~(P-w0ya|
z2YN$pChLA9$uc<WpZq{N?svi3K>j~7x+?6c6-U*xRV8!WbRt&z>7P&Hv}YB(^VM|@
zVn0SwXVED|iBv(=S98tD?IZTu_URc#_)L?Fn5|AmY8H&zpk>1vP6)q!9i3OEXlGXH
zHksHR!7Fypt2+bjzwQgmxWl?^?Z>ZhI&X<-&x=x~%XzrI_K2z$0=^f{$Rva1T+)-y
z+~dC#jJnqo!lRVRiC2!9vC-MjjjDI+pZE>*|Go<?VUciVfA{jlo;z|IJ0rdTYBLx9
z@}({Mw*8rV{*bp5pH0(6d&Zt;k#I5fSQ>5+XQ~D)5;ptp{;FKU->{H=<W2rlJ=qe%
z<8PwAOu-5NDuW7CFvwSwEt|2oPd6=M6}iJTv!~PgrF09E1uG(2gSM%jVzxE>V3x~B
z9f;GOn5`IcKH_AUt@R?|t3x#rdM1t**A#l)PN{7eA0TOL*eZ0||GoYhbDD-t&g{uA
zi`jk&jU!t%AxkFk87h3P-hPb18Bys0MLC$a?aS2K-$;_7sUaQvklP<+nLBzrNiUzL
zBvVc&xrY&?@HDmNC5lPV(MKpXwbSV@EW8fIhb$P2gl`ISfkly25)G)buqm+z`jrCs
z-ecy&&)6>b!a6K}H263SUZvGFHXF59kG{_sHrX{a*?LmKX_GFo1qg@6>*Poxjv8&@
z@_;z6JO1EZbV<j%1v-~{T-2jn1B$NT-SsJjpx1zGMeLK{@SdL|qDs*)USZaOc(#Qu
zeP2BY^AV%XRm~FR<rGj6wGol^3Sjl1C3UF$whzYiEfpAHQ14T@xmlt3^F%{H6AI7P
z5s5{<Pw2SQFWUu7YUg^xLrtx|)v2fGrc<xnE{K6b+Ew*P$OdY0=-61NG96b`eUvl(
zLls9<N+4b*3HL8}Xfa*Llf7H$u-e^O=N$BL^@_+pr4yb=`I^>FhNmdxhlE^D^#{2d
z*j3M8RYtR<d6#5PNhuZO<fTC*kv90}m?zF^V5lhb3S0x{cua?_!+ee?5mB1SQ1h~Z
zXaF=yW_q%u6-soJWz^B9kewlRwMl&rC>t*>XK=XPP<u*<{DOoLA1DzQD;x@M&fyT1
z9ID7yX|r&_x{}-z69?W8Ccy$Kus*^jQ%e=GBRoZ{6Go&?R!|4BxLnjJxJAHa)SWU|
zHHXWBep-Z>iL*&(sn@GRygGg%QT{z3X0qTZ4i~I53wE8vDPd%Vd*Cxw<|RZ5X<A%7
zz^kYL(r=K5#tHqBLREZ8oGJT^m~Lg=2*r~e0IMf>RZ7t!lPbF(UaJfuKo-0qx!!=I
zH~fSU#e8Z(<&k->MDe1m+OSte1OqSCk-5sm@h%LObn!&KCqqoMn<7;bvK{nV2<4y-
zvsoZ;HCshkr9T?I;1tCnl}?#VOJOMiYby2*GCU@U@OFZ3i~7jh99lLR=v7i31u70F
z$E95&Y;TkeR6x?c2rFKmLFeEsAr)Iw;0zSPFP&<%PKdO=#u*;hTHx9XLI&bEv`}p<
z!SxAb(cH|hOgzncB)>j-D>tpu`S5lW<RJO>SMo&)44}oo7@^r>C)KI>xmn_<b~?2Q
zdt#WfHBn2s_5!k14Opju2_+$01?zj=#sO7al*LMutsWvWNuz8UIEW~8JH^f}vVAtu
zna-66Z03=cVk%Ks;YXA<*L&l{nB2Q6Tb0=qT?(2=Aur<%eW2`zw-uGa9zVwHhaOHq
zG9Bf<%9*QbjpBBIn-k=Oh8oCNf~mu^2FlsVoABEZqrh{aLRm#rs`a1<rvOE)RwHE+
zVKqcP6~%60EnBA~4fQ7ZYPJecCJ~hFHko)78F6;J9E`L|;n1Cpf(2#09+b(H0+ekj
zhq|?~Cm~cCg_zFNAdY&WkV5<_QKVMMhOYtNIJUpHV;49gt}1sM?8R-u&k0`Dn}bC>
zP8gD*8h`NeG%5|Mkc?g{TB7^Zb2lC=*^o)8yY#Rdp#HDREO+>VE0rw~4(~#sp(Hed
zIPjIT(qp&r=<aQPy>};fP-K;LaFxZr4t<p;!qOm28VveQpbDfbF9$`9z^mXCF^{5H
zO1T<XJHqCG?fgPa#K0OPIDMROz~T4>e!YQJW&vgx8f)_xER5U5A~fkbtamZKkKtGq
z<%md=2^&H8UB?SYyKTZCW8lm`(My1rK9WyD$%~PmKtC76Asd8Xd|NRc6SE~HU7-wq
zIz+&n21`fMDeLN#2HBXCMMs=*RvaH8a;QC`Xdh-zD8VQ)WT9Rnizzu!8EYcoRc;xT
zIJ~~CslgZ$D=khyvPtcZpQZdXdJyE3N5vfYt)U2iH;i$9j$6yFqLu3w_-%mIqm?#<
z?%?rzV5}aOh-l)eM1$S_ieo#b5L%)9+J?+BA(QePt|!TMCj<$mq@CCr^m_`}Vh06<
zR#0+tax#Y1)qRv~sc3*u8Z@<t5!!a532TD3yf06wuCU`!xl7;K!3r;MO9^zRqF)-d
z#7!?$S`;=(M(s}LxzZeE9o8TIlSNuydXxoKkP48Nj@ipGhuZ=_jB>>}AF1Kl5i0(}
z^m?Q%YsA2F>rr-c$K)Oi@xKWw)h#GgXkC7)l^Tl?Os*zTYzVsW>j|L}qeweKZSkuD
z?08~VPMo8N5`@)4$Gr(6N1MX7@fHi?7)>O|mahS&V&CD<gHl9FQ&k!B7BJu4rw)|h
zI6QXPYw4RNDbP(?^29`2M2ZqM$FCw&-?Lo}M+}e~o$G|`8m{E3AjDhQvR3;yBZqbP
zwzsgR!A?JGg}xAr81#^9m7jfWEK57hM=n<8eSNk|U#yE}U%$1+|BFVFSJ%a}ZH`q$
zsuNqnixkz-3rcaCsSn9{G0CZW>~M0%86VDYDdUG7&Ncu+vpf&*WAdfRp~PFm<FUzV
zeB0igy>y=a`04))!kws)Bi%oZvpZqlu7WCqeslIfhMDn$p|F>Jq)5Y$P)iT?JFO70
z@+V!_W~qWB30>-^-5=O1V|oA4emfQRka}gWJJ9(RNY&uDXX#yiUWQ^%82poqXuNc;
z&SsFfXn9hnh32ixc2%saZ-qI1o6$3<PIZ~^P|_kXyZMa0sPjfoWN%Iw(r*Qu|4lOa
z5b>&+N4p5AZ1=x1mU?PxOoYD|c$O|QO!MD{!*kPpX;-v>IJYpfpNO-RIWtfxd*U)p
zEZO`|n$ssCLE*F)a3x*f7y0P;F*$p}Q~&JP{7jg?%-he<MEd_bN?*?IGw(h|;vZ^p
zR)S=E{Cnw9S0-J)QaEj|{XlSjg2(jvpM<lQ3bud_IqPSV%>7NGFHz=we{d_DtvqD@
zcl(R|aTW?9^tC{FdA=5|2XpS*eO*g#i6yvJHAocr<)YD9`jK$WYtQpIdxEQGMZnXn
zh)%AdHP{z5sVO>y%;t!=m<SG{C6kh)b&l!4O-en{Y!&MF+BbI8K}0JOcO^y+^|q!w
zzVR(4{IrG;aJnel{SVBV&Wmwm;$s;fxrjk|CUPPQ#T?%Vp1Z{|KCXQ_y&+jXnNojQ
zbo9zlX5AaBO7Zytj&8h<F<j1%oPXix@{S*5?zLD+v&T6+SSk&jpXLf@**$OfR;C!&
z&tGAwwnmn->{j~5m`z>%?Zm=|X-A{k^CFW0{riXQRmZdG-h6>E`q$n*e*bx#D2m5z
zN+RJB`v-}$;~&`+wY3)}Da{CHcyV^<9tjXKnPMi2Nr@skLjV!8tUr886FF(A_efwz
zGqp>T?_|mMaTJzAO-k<#P}c!ftZ+-R)ohiF2<Lwfhq5J;_>rT*Gg|ylL)<Vc%yqE5
z&b@;(F#Vsvu;Xh;3`t&ULA`~WIbOw4#P&#H!_q);s(;+V=P|$zR>JHHKSDD&MPo%H
zaZz7t$J1}n!$c208Rv*{Se^ABnC6-$T^Hzh9(QK#OAz4Au>$VEQx$cLS9favY8yPg
z=>knwkm7d(@zof4Pc8AJfNwzvT+pP`&W&MDxT6{cnVP(I9D9J`I9{yo86{fT(~i*H
zLkCm`8QxR{+KnK7VjjFKE29PGQb(>;m%GB+boE-6M5^6F_FRJ**w`pH4;g#U5%~JZ
zl6m+ks})U(MiIgjb3VwU(`Lk`Y$e4OizC$O388qR1ww;&ueVxH@YIo56kB7eP@tvK
z@w)W{Y-*=Lbn{rSuvmdun&KA{AB-B3!I}iHKOVKdrMKaTrJwK>AIX|OPl)nOi(Lr;
zGSu0hWEqFL@Ydp)ttn{T-*QNb5VPx8P`Fh3&|FzpB;~jfeCmzPS5NRs%lodH2#V1Q
z-NpYZ7sxsc$S7Hs4KnJYuG%W(;HII<rR8%wpqLPJEp;KaM=Iv8+^nZbQ%FJUGTbh9
z!5XUcZ6(<X!umkJ-qYJn<5P)Lp|)QoDI<hRx@B>vR=_C~wwM2dLR8uvUg}W}+;jYP
z10xKf-&_sNtw)E<%5wx9uLF53$WhsL<k}3b3MlMR@zM*r6x6}mY<2x<{O&zPP(KPv
zO`#+SJOrmQCEG<GYk-q@$uJ$Q`*Dn^Z{ctd7IOb??nTQ7&k->(Fh=Mi%}KF4gQI<g
z3!O^b*&s&Pln%u8Wwa@FE3Z<V11d7WOQt0_j*b`<FU%ulExG#0tj1l7?di%b_|7IQ
zFMneZ1Zq#LB@Sse$SbS}zP`^?Rj>AKb5nCPlVP@!%7sarl9^T@+-jXPJTw?YXD}zR
zBi%`b@M7mTL@{wo?RIY#kIl7xuvVagWEw|SG2a0P*kz-cvGsYW`&RIkWdo^sa=-^!
zpu95PV7WJ}k?E*b(ZSX*VuV-czV9Tx^m1aTk26&k)mu_8A)!N6m*Ll2*0Jlr{)-~;
zwT+l;SJ_(mNpJR%tLAi)d}g<}m{b=!HR>&OIixgX_Is(19CrT}p*o~A%K7Rwt`(By
z^Sfz+h05B%i&xYN-^sIav%dLiX?G&dxhUG&{x2Si4y;uv^EwQJ2dtFYn)<T1h?8KJ
zE!^hA{Ie7pyE^PdKmCmR%w6`apUCpgc|obYwXcd>N4>p#k^M|lOBJ;(EYS@wI305x
zLM%-Ub$B&dSSr|$>!NpXIuoL5BxbAQP|!r32hVR1+oFgj%`eaajbE@hgT#m5kaOA#
z@f2)0+I}Rr`G08P@>izG_R4ClM~m2=(0^HG&wj_sCBEE|XbBqNb>TCUL&aGiEh!uN
zT`Wcd!$aqf1(`!aiMDZM8ISlV{?sR|y59x3`}%x1_J4T)X{g>iu#bM3YAsE!5=)Ik
z4-f=RyZY(GrdVyc%=aF%>4^kOl{}9IOP`pgdd>cug`=2($>KW^7lj<@tk8q!ql!_P
zOP}A9iAv~xz3&Bx^#<3bqwy;wp`ulafDb{?KN)tq|1Z~A(lLC;i@wMaNo5CMD=G}q
zac83J$9oR<*;`jyp`$!5JWCGc9v?r<nNjL?>bo;CTUF|HA}zq%1%$YC@!EGMZl!#P
z?TwW(9Q6B??I(U|sPK?!zvI7XX^Hum$;F>16A9U{3`&Ug_so;DU%P<8<?s6RxyNo_
z82kor%^SW}Rlv^=7~}dP%vk}Cz8~kq7Y!_pAZ@v<8hta_{(2Vd|M^Ypd-*Tn<|BiN
z4W43J_$#33-Nf=s7nffSUumyjUoPRFe3$pILUx3)WVv|6!ejq}rxNwslXoN=(n#R6
z{QL3bgDCxu)QI#ALP5jlWF|&<fa_Gtr~W~&7BMKV*g~rz{wW$_dI~~)5~iO>g3Q*8
z#ww)ct{zo7SRf|l`^R$o8cWWhB)zKMa}E}+{~G<UR}E8SDYkKkP15Q)Iern8L=ZCn
zYn7|#)jbKyJ&ayGaCJK9&oEa7-270yRhLpN=FzKI0&xo#)m;}RcAU*|0gF97`;TDg
zB6?JBSHEZ<FV~Cud@{~iWGKYNk<HoEbt^i}but-ioIBmeF(T6Rt7uUWZc97SL21@^
z-IA$zT^F*QbG1_V3L_8IT`JQAYA5Qq4)p39jdzJMF1h_{o+m;Cv7M+YiH`xjFA1rX
z&0<}IO^Tc`9H5eCwWGv4z6RGg*4=~F!t{pYWEprMd_+y`!`$cOzA^@I;lcHC!<<hK
zRnLx#UWGcZYwexu;#venoH~9L$2cPR%IhaW<=^@0`I?YhhqB%sg98jj8QrQP)}e29
zO0N<8kY!>nN$@rdh9t04!_p8@Vq=YKf+bv`L!Vrw?x`3_sd$F!gXCMSDGJ;Uricj2
zYA95z+!{n8{9@AeUI86hfr3%gUs@X_HcZIXK%2~01!)4excfxx7HqLmq~kr<-HfGy
zk&--eH67UW1L+8#v_BxUAF%OxxXFvy(K4?vEn+k!2nIDyHbsemW-u#;prS6|&frJ{
zqFciXA-bz;6YO@S*#>*{u8m=<FeT3m;<o`6LIhXeW4U<5@rOB3Cv8N5$KFuQzmt^Y
zO5m%9-Uddk^|q2;>Y`|%rb;_BzJncw0IPgd-gupgwQ*g*c21v7Vwp}7?UEGRw8Bfr
zx%<k^m2AnTyR=$EVM6mu5j(aY*tB{dwABO1seJ(DLhY;AO>xgCFpy+vD~1)h3N(xJ
zj9;LK3U#&T>}wP$M@*rt?+-kWhOeovrBwA$9%3_IoE+<5a;*&Ia_gdYbl$&S)J>I8
z-aMD)m96Io1nDa-%Z{}mhON8!ip6yy=Q^R5PzD~ewbqXl5*PZQatV}WUBjYhKmp*y
z;<^YYb^yb2ZR%SGUr3?%J{(n5un-Z00vf4~tQL|&w*xqH=aJ+3Co3`)GuC9`=<&$P
zb_6ztJG>d^YG&@#B}pw$TciKgp!iAb!HzoiUvP!3H1hIc3Lnem>mMcS>++Ct0!hM0
zA~8C{p^X`A?Yq^U4z3!@e<XaO!s*1D|DE=zeU_>p7$?VCp5hwz`pdl8|A5mP8lBZ%
zKRwaJ?06qKnJl$e{!VCP9J3Q@Khn_<lQv2dlio*7N^Yc3?%F$@Fa5Yvp?J*JVD_)Z
zx^$8)J=@3Ei{~tuBjt(PdG(M;I{Q?IlGzCUSLk@{23}z*1GDv95Nq1o<PWx7taaz2
zYzm>cJXPRktkYs~_@Znis}TIktv143*_6yyeYa1BC1-L@SMsmTwzgX~DU)XZgGJHI
z>s8fjQ%)Pa!ua7==dL(A5Ee>0)J?X+`sYlE-Taw6(|IwRl9`wzF#OXWBa_p5)Bsps
zdnlCl$Vm-p^a56obzj(P;TRV4X-w75T@O*5A!W8TW)jO53pBxA3B}aQt)->0-_%NQ
z%QV|+cQA@E)wRXP|C&$VW!Gn}Lq{aYY#n%Sk|KW6_q(^RdtAlQ4c|?2lJ<aG(~+qz
zXcs|C71poetGg1L=i-E2nMD@YBDZm=CPFP0sm_@_MW>qf%*ODCD>1+Z-fP9IjslId
zt!D|PjB^>O9dtW*^Jz9AQ7$pWk!aW1hAaPGKDk%J3oET?dZL3)q(ChR)Ej>%)H1S-
z=S!{G#!V)x(#JA>`od^<Dso%s5_A1$({}0mX7<g#pOq|MyHd!9-_u`Ys%a&X_(y*r
z%kPy*UVJCb!;8n9s=CK)T|DvMevA$2onZcD>R3N!Yq6ZXty~-~exKP^yXq@Re;B^f
z(U&H{=~mp*8gBSb8aq|WXj|xxG2Q#$sbL=<h+`P>tEV-#<L)JF>KD`M>_I%chw#*G
zXtrMoM8)jcA2ml?RehV62uAoQN$kfou0Ih<_^VlyA$w#sM4`KZ>{$)0QvLhRY(g(-
z{}rL)8X(){gnTrmTWpz0rsUzsy2+<a^fr25N5k`<_(oHAFb)2Uq-9%P+zN*iNql(?
z;s=@J*Emjr9&j>IWwsV}`U2}lzD`<x9#dL<&I*6tMB;T^a65i}V>X2z&3fPosNm^Y
z*En~&AL_mlyps)z8ud*OC|;+Mi41Lu-0Y27X#(RD@LLFhCL?&Rjvt*|KKvq2RhvRJ
zu@%rap^B-@OK+f5l>*n!a6siIh?)5i-MTDRmSh!OG!YrOG(DXfwc#>)8)|jj*0(ON
z%|KL^aUpr!9owK1HtSVBeX7{MP4JXe$8&^Llq|lq473Pgg7!NLBef9siEK5(VdEiU
zSn#!@@@{t(XMVfLwp1F(I!8+HwnJMD*CS9t$cAjm#wj1MCYZ7bNgWHxE5Nt97zGxb
zeEKmJ<@R|Yl>F58e2ib<*8@-}8l(0EyL6~#VXRK02uMZkD@Y&bitya;>qb&UtDxaj
zwnco8G!a|hqp05R#}<w3r~Mmw%||I$gerW8eA3j<e~LnrPAYKbls%SB2!!}01$%y<
zI>m)0G>N|neRc3i3k&g1z;ar<w!KYF2IAaWe18;l)$cQ$UU{KxSlB(lY0#>Y4d6>Q
zoLGNQB@t1$9SX6AyJ`8lWD&FMSpF!i#I?|h=m`!Lw#y2QhogeFZbUfUmE}@OaRvFX
z5hrwSAXc`<gQ!z!=GVO2x<b;?9wBYFBbzj=*6MXBAPojI-CQ(HJGeXWw5Vz^$FJxQ
zD%{)sSY#E?5oxF8x=HiZ4+mO=Zq?&!yxZK1eH?Zp8j;|+NI}I)_KpJBisely{5roQ
z(b779hkTH5#K)<kR+TAKLx@ODS90^Zt5OG$cL}~yj|^geS4E*|_X8xSQ|N#b^Iy<i
z^6Ug;9jnAnIFVZryr@TT9F*mvYlC4a7Ra$WgsMqJDa#hh7@{KDEd;2fI{FS}XYT`_
zm#;IT@@VFJLa2#KJ-Tp{lWQj+-H5#mM%l%=4t(Wa<kq&M`?4{Ash6^Mh7BcAUa}lJ
zMM_dqjP#bW<ReK)kA9N3%`FVEtngf|=*@ng4K2lQS`gys$PC$+B~k^Uacp~!+5R0A
zawfIp6cbqSixre)*-E?R4=l%szVHrs_`$Sai-a|k5HysoCgEI2_HP}&0W-*Vl3#fs
zs(!(W{TlP=3lmjK;E5~zd#dpl^mr*8UPoCzkn*;t7{kYz*kBH}b-zxWIYXmsS$p(E
ze_+xh$<wDlQgm4)Y^&7<a?}8?hht|57ADbS(I3|ytyR(LNr!_-qI~&cOP<`ns^^_(
zR<?y+U*X8FQMuk6dC)RrOd7|0=)S@7v5Q&wfJt-pnPHA;eVR<(3lsXLg+iQWTd#Pq
zpj3d3GAU#mh$aM+s`F##XPVZ6`79c~cU*>Y&+?hOl8-wKeUJXw$%LV`3;3|+_p;T_
zl&qe)AleeMGdM42Z*U*)OIQ_}QxTKN!<em}G&k{FUCmwgW%tf+57#R?U&bqweCR_(
zh-T~a`-{BzHafWRACv7HLC$ZpXtut1D+f=!!lUrJ{fu$cobdqyO7&ne)3aD@W&uPx
z6knXIwq=Pct9us#CuR?%SS-B@6BtYs816c++Ce1iv@K-=<7W`*@cBW58@AG=Q%FSE
z_f2a0w=S?*o$aCm3{yO$S~hHbA7b;B63t%_5UVGIrGIu^o<coe>GnS^T8E$r<3XDA
znl7JtqUALEo6*hmi)51C{g%v}NRv+@U3qy(Yg1oKHngJ(-x8kq{WL8{c-SPu)Yrx$
zsn35HJ%Apd*#GGJb8~-qaTY%%s%&Gu!E81Avwug?e=%9`_EDM*8spJLR_rYfhbLvW
z@<Gya;rc5<ft2SLIlJsskh2GjC4TgjW4bkSF}tfa;Y-H2#CJEkWxFlwn2$FKIceSX
zv#ld>+7tVc`B1AOZlwQO?EUa<WqfTA6Mma~Ryft+_<8LSwUG&}cklL);frFq-*vH0
zi}Wv(AWHml8uz?9`1IBEoYY<h*^g*8UrC&W2Xrn&1(l$cJMiv6uf5<X2<`*Lgngy8
zoJa(JW)H>cwMcjs@)C8p&Q-48ZX^)dBJk#1NS|#bR*n_>7A(z+Y*r@0pwA|fT#JM)
zWwLqX-n8f{fs#$Z{%rWSv2+!-J#=`!=idxsdS23KZ*CoWw{fqRx(Pe?9ySHx&zXi&
zFJI?B<go*cThttXfqsL{eoXbCZdkl3a~w_~SrDF&BH`E`LX0|KED=#>OT!!H37nR@
zejxSu#M9zZ7qLYc^axpX+k8zn2W;}gvadRJ6@j4TOtgFg7q48{PZ!-|h!aDpr>oLt
zv(QjBGv#O{?i6Cj7c(LRe$}(BJI_c2pDt969j;NCUI-P9Em4)P_3_(A{0)gxUYlYk
zD70oE;9-d@0gKvK&ot~p2d^g}s0ZIhPP8r?*3Z#^37URm)tpsfJ6!kOK=+v(Ql>7e
zDH2}q@Db2!YV=xSX(k;=c#(m;FD>ua)7nwMW*A?6jyK1w_j_{zS}vu@FP8LRL}k^P
zRG5-XwYFv6jaIqGCK}F0!hCcFnXC?WD}Xb|L9H`Y1qA7?8{I7t=>={=+09QW*_JRy
zH>%EV(??>qM6Uvaw-*_|@vDY^Eo^$~c_|uxV}3lANtC&RHe$=IV8@SsoVh!x)~;#L
z3EUZ2PD|=QNtM}rgDM?!Zq7`UK+P}NEjN*NFRuOyrKOxH|L+eX^PIO|y_jRoT!?vi
zJq6QV)DBxt143w5ISmCz0SjCn;+;!$hyfS>X^Or1s`;w+!g}~58VE~JDZEJafY9LZ
z05wh}QI#ni4QRLqU+)?M(kkqQslE7SRzu{d1|dwD%<)4$$1TE!&k2;vQNf%YG9Bvp
zUEQRaBIUBI%Npd$Z3~D+S%nAP;zf>Kg0CJrPko?((`15lsF2JVz{fpb({V8)6=%us
zL>(F*?6#EQ6e34%qw`|@W7Sw)5Jy$jY14xuLW?UVd2jWE8Cf=b`*{--)R#^<m?R80
z7e)DyO>m_9<R+wZz0h*nWSV@JuG8$bKH85kTukve_;)cnab^bfY3C;OW~l6I4H|}q
z{lz*`os~CGI1g~h`?HtKK5v`W@2*2!b4p|3CbaNPpSy$C;?;ri=(xPnJ{R7{0O(0!
zJi@a6b=?-`G<omKvJE%QN3{xx-!37L0jQ1v`^h2yj`Xn76;PO;h{LhO1L=R{d-ljX
zsTII;?LHJEEX>wM>D}0Dl&w6^TSGqKK)qrA5*7M$NvebN?_E5L`Q&0=<QQs)Xm1Oi
zD$=b!yI}Tuh9+2VEhW)12Rr<F=Rf?;V6!WH7x``M8dOA2NUzB3(5YgvJbfMS(jRh4
zfUV=~>4PIWNm2_)nRnyf{TfY`47qC`DAcu)ihzd(2Rr%qvSP(Qf>tU6N#Q#}`;oUK
z$?%`H?8V2aG*}zcplgaQz2he>zwn!ubW3tt{6D>S*v7FGwKh3gwvUjBx+;NRy2{5S
zz8zsERcjXP&);JA=kKNrz^2S*4$|s&?bw1c@%!&4G}1hoq>p`i&_(^qY>oRYRkq=V
ziK3KAGj7v4ds~Zp&-<W##NSN+`pL`q$klg4SZ?=aBWSBT@sVle(G#-q*@0B8Z~7<<
zXuWlvDlcz&)WY4bV^j6h5AmhS%VTlxOb?Xh4?Y|0Gru(Jr&oA4%1k7Q<Cm!b_utPM
z&7WhJu%=;S850ve`)@%Y+o93p$-r~-jcF&dl_kDC)hk7vc<wT9`wxa$%E`@Dle{ry
zXk9SvuxG2G2{H+B{W;m%uioTl$k@Ucuk&iOymsA2@ulqMVZymJ1cHTBeyP9hE@r*x
z)ivJd2fW=Ke0pl(g5tTxB)5Ik=;!9>D@29-G@Kw_EaO@3lj$;t3V(&KMuJk3$akJ#
zpySiL0GB98zmI`M6$}}6;=3C6wh)LZmVMBD<eLX9*9ZWWB0~1cKyh{VTlU5{?{|Ey
z)u`jQxanw?)2;Mkj^ku73>9G}&eEfZs3kfp{}%2S7mBpQ5y;gx4ss4p)U>+4m>jWZ
zTJ;Xl2MCR}ZXLVrO^3C7zJDn#|4nFX39>enu9nLE)F#=p;s*{8@5X3BU_-t!j7FNv
zzv`uHpMtUq3fU3b7JNi_ac{DB<xOs?!tTm!J;v}&$e#JA$)252#SD@*o#3@52siq8
zU%O<ypTjkDk%U4bKEIJ!dVB`9o}+g)sM+ZnRJ=Pvo7nIutEPo@RQ(pIvIbH+)*!#|
z3H)9dQc5onVjy9~J=h+i5%l2<M;~7vap*$hnvg@_KxaRZro(GUs`}h`x4*M_l0{y;
zFn9=j{it!*Bau%gL_FCjLyu)FO&pmpfU0yW_v)3rcM0R*EjPHK$w&cD^dXBz{|NP|
zBS){`Rg~2{Fu1a3>X-!kyNjD-=wu%z_=i(^&hmMFPs*_)p!1CG8RNB8R(@@|)Kp<+
zJQsmz7L5{O$aa@L%+}+)1VGLa$*tmDkGo4h@mTCD!l7d)D_az-`=X7G3C&rnYuTtR
z(Z}J<+wYSJNw%BX)V;y>v4wT27~+dSnXCHXK{T(o1#akbC}fix%%!qcoJ|oc6wd>u
zdktyh*yipgVg&0|7tmpmF=Vt3{5ZuT<<jdHr8Z)`mg+MvtcJ9UC0C`I3|13h`Le*<
zg>Yt1s+v+5^9tKF<l2}Igi_ajuWJoqUvSas!c8b>uFkcIKKCACP?~uaX@B+dC}UW>
zh;Ih))tsz89;!Tt8x)5_73c*ytcB3>^@IS12*O{!nxJ-w{<%PtP=jPr+UX`h_jSr%
zAH2yuTD{}e*8~d@M^`uP$-C%KNznxQC8yD$V3}%ZVQ$^{PeVcX2}t-^9Ga0I%;C#Z
zz$uBj(}k$ImU8X@IcHB$S)EWiXq(4>BlOvfU29GcYSL7(jTq<nf&*DASzKjHuOftG
znm%zcXE5A=$Ke_s$1+iIG-_3BGpiMy+g_wJFDqh8CW+h#pl*bX0ZslJaklm;r5b@M
zjr5PI9G4Kd#Lyt7P>R|eA04j2C$NER9#?RngeqvNkW>-sIx2UuTm|iPt$0~|?Tl~0
zZ6CmU4^P19R=4n1tUXj4u-1DVe04`{E_)f9;^+lqbzEf17Z+tugtKXwJbImfy?udk
z-<7L)8n2@;AE?<+R^+%24Lks;`>}7Bk?alN#?LyYXD2LUEwGm#&{N3KI3}W9ei3}O
zGVFhf*;YZ|dl=~8)#;P6Y^8be>iDe^k$Y=MZA#eL$_1&}-Bn)*mxT!~-m?|tfD7q=
z>^l{u<4csmut}GMBD2+V3;YD0or2t+7;r+d`90nz$1hABW~<fxxIjEGyT$p3Rm{38
z#FKV{I8x=EGFz{#W5?{oCll`netyY1j0pVQ|5nw2b!oS7Ld3n1H|FrS2dtcbwK)O=
zvxFx{E-8xQGaoC;>0dz?%(hPOxxj>ZHzw;4RjB&fhCcUjC{D1IEaziJGAbpK+3rHp
zLiX+3K9gh^#nTG}c#!qudmZ+uc%SDdegfHA!j!H`aEi$~`U0fI>PZ49YL_y{T_v_7
z_!*y!3*&!X=WX;IW0Sthpj(-(ed&PqU+%v<RI-g@Eie91%Owzwi-dhjF5>JtJ<}Jv
z8O?t#VzxT_gIjI3e4MT^W-Dgk00%K537py0`;xjZjb}UXM0CG_StOJ4(Fqi>qJdMO
za7B6kt$Fy@@5?8rZp_O0PmX0h1&t{$z1{rl@6XytU)dAK03BKITW&=m59Ss>lYz1?
zJ#;$#D9R3e$izna5t7XV$yhnfK#WTL=yxBYFfIs^rZ@DxeoC{gS~2dmHd(1;t%WaM
zF*iy?h~o|_z~Qqz!li8EH{1PAloQ+%&dVb{q-_0mhA~WFp1blc@_ONx#N3S#GW%2Z
zwib5<OM`s<x7fbBMRWKoV?J(Njhtz=RoH62wF_9QrY}A8ZH`%EZ)^J1*Jj=k6OO6&
z{R2xp%;_b_Cn2*rH9|dMc{$KsVov$Ke}p2KFBgO#rt|ea3uE24dRHD9NG=`u;n+U)
zA{UZxF^}l~OV(ykdO_F{DFPN~g4sHfox$7bx6b?rVh_)fl^<WKP-M0yU%%kazSu^-
zU<a$Y(kgQ2YgdzQn#(<7p<bJ8tq1Tg_XmBQV?t(YUr?>R#a60m&*rm`$V>1hkoI>3
zPi)lIhc28RT)H-0T&P|c+08BITt485bawn*wQP*6=Qci8kqkGo8)Y@yGv>vzv!7|b
z0E)BjC}{<!_vXnmdlLF8FDOrk+PTBc^MC~Uti01aW-GMrTg7JSc_z_jqt!QH`C?B&
zSJTq5bdqU3s7u<e!ZZ+G<Q^=^CUEh}C7;JYl83wl`~cN8I=8<xNT*WkYuAt3WQCro
z*|X3PsxkM`6Rh!?v=#dQ&J_w%asFm~;!fpp)wtv`zJORo%@s~UqNqsi#G+xej}WG{
zEy=9>L@zVYxzWb!DxeokS(%JANcXRoQ0{~Lykg~9AE~e{K}bvd@*$S%tjCx#dQ3@h
zm|&?n#kAs;_6N&uuL1%ggB-Ie8s7SO!dTc;C}tOMdkXdH@t;B)N|Dl%-dyobCqL@Y
z86(E2mln%7jbs%sLJ!J!_uwk=FkAP`kxJj`uue4vju*3)LcyY)blk`#<wEnBjYsdg
zOFaJ;g=tfy#+YG*soRKfQye_#irWVKSP-RNFw-JS9sN^Qn7&C6H0E~=(?E098E&&}
z7A@@pSOO8~1V&7iNNCcGB6f+ov;NY@Ffxdx5IRjuO^DWvCliXFhA~4R5$OpFsP(NS
z_!$YKIjLq#88k1Vk2ahH0wXkq=tpfPqE?qGGE}#nt}Mk3i4#T=dCXd!b=%Y2v|?1w
zHZjGeOLjj;RmUlywvy;=m8ZT2?#B~QW@3#{3xLj37+1L}Ry8l@f$j|@wK&#>4n4w6
z=u2G%h-b)|m!}uZ&^Iyq!jWbMc9b~YgPcw*1{@W{oT<Y3YSyLsSS+rNYA}1;lgJ)Z
zTidbe_?p`)jqa)ohq6YzP4N6C|5o0&kHm-2s|xk^uN{=*HXwH+afvfuhkM;g6m*X;
zP~YdpjPX6~+D|1_&7^sA%Q4EP!fMpcj;UA~&cX4AhHQWOVA4rW7rxux<Ilm^Dj=K~
zrG|c&6H7Y%K?o|^2>wlu=6QPB9ew>$6}TdKwQTl(G!NCvu(iV>SIJgtZjia#T|szP
zaQ2sXEDdz_jL|8oGT@kCPPVMn!I?Ud(8SOae3UN&*0S)t*Yv|Wh>6|0fbE=Vde5G;
z(>Xw8dOZa*DQScDww^X0iP+cZtR#uuGH=?++c|N&50RZY3d%oduv&r6IOa2Bx0ye2
zyPfhcrGF@vqS<Q4_l*=Uyk<Hgwz@;XYJsYh+g<N%-t~7{o3(+eRq+{H`uJGU&hJnC
zkw=nz?~Us5>;kU2f&T70PmM1wPhFDB(vk|j67G304bOhJWiNc};aJ$+t1(hF+j@Ne
z>4&u6gy}{Ml81i#iX=Yjb1SdG8vRY?k9Gm>;diF)=2KQIe2ji0mP?03`bOhuv`O)V
z_gv>xie8=lR7%S~R7B4FKOb>blSH6Usux_P2nB5iGvNzQq3u__%Dwi9pYn0$mPB!H
zYuC<8V-vu(PkITgm3C)%n&Wv(kkf3d-@8BY(oW!acRZu&Z<2KBoh@(YeXwqHnBxvp
z-%0)Q3I-^gIX64sOpcRk2N-i>QOfWu6HyTrD(sy)e{Y7_TG$DSbm5bSSKm@Q5TmPd
z>BGrr{=x7<WhPd*lN47pjqiDouLVBC!8}s-MQ6<~OzmM(03+2@1(|=%%OibBICyo+
zWOu?u{`uxA8arOSsz<-ZFvvFC3Uw6<Dc!g%@<FD{S6<nZ7Z`_ewQe+9&;MC%nX?f7
z!&_d6_?|QsA9D0A)~+4;a%%H`+-I%NJe!QVUmwz>fxV}nmu4{QmYkA&{%_N5X=%9Q
zJC>D8*E8kTneL1U_0~g09P{XqW^k|_CJ(I`mhJT%hdf5=2lfQ}^hc8apSbrAv#dDp
zJKuBe>7Fw^4V)PoG+=&I&orpPSi1a>%p-_Z-Lz0cP}JbT533OSLhyJjdA(yxA~?Zz
zb<;vEOze&#Cn%4-xv)4pAx<*VvU#v0I~Nvb$rGX-+t}7>l}$%0>%m${&%~=ltYXRg
z`Bt5C`}WNAy;sQ}`*z>@`PN%+y;Y~G-l{rvZ2ou|mJfV94UsE<dTB+)j)byWx1g89
z?dadmqW<0_DLyoBbKNKC6(3v(Hq*+wP0UdHD>T4xKdt|C5>Z4(f1IIDHTx8`_r%^@
z7cd>nZbjjFDkBuhC%DzRc7F?DAEFC+1j&xI+iE-zk@^)RC)*jQe;k64_PVP{FNx6q
zU*%k9GR)}MOTLxa#ar+5u`TI(7Oe{G1i#aJZeRF-yL0+DAMNO}ff*nyxV2R<$yuT$
z!NAr#3g&^*mY-W~Pajfg`GLBE%Xk1Iu%$t5g}=V9(0MnNL94ds*`Iw6Z!G;==B`|A
zn&7!On%AD)tt>oN>5gL-b!cP*yR9<>E%I9@biq;V(D1N3F~o=vOF9@o%jwAh#Hw+}
z6|lvE8gnTqcDPyOx(-=;##m}3L(Wx?58^XUtaTm@77}<VjbbI_h8|Af8icWPjf81n
znYQI+@FMj2v`~i(v-Dw?{i$-=zCl#h&`vPV&3D`iTvdUNY=yD>nQKr^#Rs4x{0T@?
zX;Ud6o&wE1f~!qO7M46X{K>u(-w;qyikOoZ`36&xz8(Kd*tm-|@jDK9o|IyGI&9;L
z)Z3sOvbJ022BOl@wvl!!-Ye9xFw`c>plKiV;uIie%IFwnkY;m}p1!WBK6+?FmPpQc
z1&>*-U#nuIUFN!|oFfi$p4d^qI<imcYzOFCPi9Ulm18mIvG6t4qSRJ4#;JC5*5L`Q
za;Kf-_^evY2qWMZGufQnMFyvYx~HPRz3D|PJIrr__7~F}gJ6-K0j1m>IxX*FY%k%k
zyj(-Z<~pq|^Dw)C`V^XoVYVtEU!l1UDpy`CsYpErvSJd4G6^W(+~;g6HL|H;p7J39
z1^J>09Bn7+;E8$zWP1<uuz=rRON7?d<!SDlUGG2DF?3B)<3pfdCkOQG{2}VbS1qr^
z6uj8LE~4*24w&7kV9Poo-d=6Sl8fs9U~F%Aiyo4&$q5Yv5TvgoHEvb-to;tQhi#_-
z_FLl(3CTUgY)h(w4nzjQ<KejKf!>82|0cI7CT}Alz`)))9oz2=;PzXJ>QfpT^)6sL
zK^CipJF-rmoTB8!_Eg%jp^scQD~V@Sfs6b^&haxZL(Hg1UIxG5umwQ@<3I<bAViF7
z%{62p%sZ<t#uPDAP{as)h_p5}Jho*4!!ISq(rXP0rTmghC}1SRH@*K(MCJ$*WTG?z
zVgVYNHg=t6g(oS$*8)nIJ-?zse+;;(tLNtHqzrn=v<4<Vo@q;FU#A0MKeRG^8RrWv
z%BR`VH$#I+>vB`emK{Y5^N&%uG1XR|7WqjK-bA*1w_6l@`?9C2zeV6_>$x~>`AjqF
zy;bsb4_S{b4FQ}m0O;1H8Y<VghS^&Pu)G{y^j;k3qQH4wz1!+js;Sl=?J<T_K&S3b
zPC7Y5+-*f|jWF>BvR%D}^FLb?Hig=H#J;L^&^*la{sI{17g@FP<|NEgv{dIK;SaL4
zy+$e1ZfjhcjcMk8mEK_E4-0$Xqr3}w<Mdd>%-C(U{m<m9yzu9#n+WKSD+|&sZay`u
z&7v%R<^HEv$czu*gv(!}j)m%k{jaYG@dNZd4$c{BYePhFyMoXE1;u@XZ_SXcZe9wY
zO2x|Vd8Z?S4{-MOtnmSyI8&=owsPC}4h7t5d0HCh-}!~!o45IJ1dM`Q2aZFFmnrZ2
zacBOeh+oaoRdwyETwNTytv;#bj*36|8<g^3XWbS+o!WQVMtUkwOqzT4=gUlYRDn_!
z*WJ5eFROn+ZMFUD1v9A&N_Jk%9{kdIS)@CHwc=3kUF<1S%DZ^XD5ZE2_}(;&Jag|b
z|2*^d?yufW6C4dyc?o0Kb;pVznVJL!I2qb)MX~h0&FS!1$FJuTy)XU}Rq_8=SEyw?
zzx&0@=Vo-Yw)+t^;tQI`OC)xO@cUOT*>ykTY>S(qniJ#NZS6hwlMp6h<cDlay;2)Q
z32iwz?9jTBg;rjh_IOIMtQI^@E7m-u3jh9BL->`qvBAyB-!|RNUq=EL2J2~;?j@BZ
zsjXkNjZ>Tew&_C%<j3-!A!+ru=K0wT7h1mgo$s|%OH;v)JYQJnvkSfd@R47#eEu|x
zCad3@gek6?8d9=dq533hYYz#2`7Xu-1QCHLqkY(K%(=gmWvdU~Zc{TC78ASD7>KC8
zauQAJ-#M3buYnjk;%U0d5PlO5JCimM*lo4t!^Y^jEW8lku*i<XLT{P|`e78l9&KYR
zaL6(|3hJ|b)-m?CxF6wnOb1c~r_E_kb5UxmprHSklqx&ML&^{#5l8Sci|8C~93k52
zu7ug%wGLf0MD&|4ER5Y&J^x-M;W~&t4B*d&*@-#z41S}J8u6onhFOGLkjx>TMz<$;
zduX5KueS>GznXQ~!$vCK6>K2bEfO7{tn$9vnhNFSDfI17J5DRp{CzyQ+qQxxMtw*u
zMX^yVYpr1xJ@X69ir4e25RK#u1hvJfbva2>ibzVUkl|4In4F0(wC2M$GT{jlC3>{v
z<#p-km``3Gt$x*}!0}9)ACsgofb0g{ilD$g3~ee}$Lu+eV2Z0^FA}7#%`6!w7@+`x
z8eHQTZug=DYvj<!r6R5H>Fjp!csBb{BOERWVLH@RMS<k!SubP*oDq=K^1LV>y~}-7
zj1H7|Prq@og>=wIs3QT@b2Vg+am>7Hu(hXkgH0|+KdV5R1r;#SXN<gn>y4dSq$jts
zPcTk5(MhQ4#&{$Kn!T6W3WOK=<sB70_k~?TnLv$EICeroJ(N!<f7+JE&e`rOq7<RL
zE&auv$<FPoT0s|+X1=HRf%gIGa>i^Bh2O3fA)XsH!S<dwx{fF&p9#?!OX-vdkwQrk
zIT5UviGPLU){&Z_o}Z8auBHX5g>J6+5wJ<E1mP4cVmNF+Awn_REJ#cfeST1-^!39P
zRk>)-@RWf<vnzaDmV=MPzXFHCHN=+7K6f5RMkk?6DNKNMQ>TC^l#OLU+Exh<9@~_`
zvL{+$xub7EjX^rf7Oq{M+Zqn2WuVX?z*I{N{343%p>R!P09qcj972h+m}bV8I(A=V
z6Kwd-M{bAGBJw9#mnM5ZX&LVUIkf*wWrzhK!h5QYh=Pb!s*a_enP9F<DQK8h1SF!{
zI-FA?o&nYS7!b3qppFO_$h7DXL3xwyqPHa`o-QXM-xf|+I0+?+7!<DxspY5G;lL(3
z4+Jv_S|5a=71`}mND+89$t8eb4}sxCG-aEq+LUd9A`fS30}m0@rO(;PnG*NuD$Q_!
zGa(c{C%Xb#o7;j!AF(aPGM(b&$aaLn&JA#LGci5JM>u3iPUNAW2eEFhO+*k4J-<$l
z<8(72`D3;y;v^V5+dggfc_S^+6yqi5G~kCui(HOd)e9{;CC(+b9mUN+nWkhOlpHNO
zuVC2=Wi)K@K&p46(AF_;wlBm)$1x)Xm5e|2OXd|fNs4L<hfVm5Y|BoMifvtN*OTo`
z!`VmNR@M&UjG0d1Ja&f6%19TF<To6)Qg-<qPm5RCnWIp-|HYsN_5TC>7ia4mX8RPr
zi_-h7qvYD3KIo}9dCnBMrVc$toB<79Xu_Qws)4hfo}ifT5=01qmI~&@))@u!ivO-5
zG8gv}Ei{Q~xZ<2FwN$8_b6O!CJo7$~oOHhJqIGI^c3kx@gk3;%cuEw@Q$ll3E<JZd
zWIbh2Xtb+kFYGK}0FEKKE;pUzS%Qr?yBH)SX+?(+<T|@nVnJh6G?c9%L=z*8Qt(hT
zq0~V?w!!+Zuw#*#)c_i0Q}N{p^2BgChC!Q1A&Pmg`T3OgECT!FVZtUDDd))~MX=Dl
zLQKf>!Z;Ab2vY=2WLja0TK|L+i381bMuM`PV0516+hu+)<TQ&1x+=(f;ATEpPPPRR
zp6z4HLr%2jF<s5$l*v3EFByw}$8RJQtw1{7OUwPH%>=ez>LfLVf++(_!{9*E@y9e!
zbC0^&X!xmOPQfFu{)8&Fbkf9RIV39|kOth=bTh(60FBwvVr&sSo!JWszXR3DD0a;j
z<1M3XcBHtWW?+6`bFjY#+Dd~eeme4y9TMLsmJ_H#Lc^z5*bNHd7w^@<9uFdKEkBFx
z`U)&b=YJx#G4m`)7k-c!qD;`~ud(Czb)Xv6NO)}k!&$A-!GgA>>dYux@uJWqgSIUO
zxhbKh$~(Zx=k{w$f`vXNfAWf*mO05JvKuCG<cb;rD`*%8lW@V;=wAb5T8@`^g8T<`
zBfT7Bz@(c+QP6yA5W)a6E=F`PW2hdQSV%7iczuD(KNk4R9)DKJkYaXdXOcYSoY}(s
z&WL(tUV$V_0HN<5s0%*r(xi(mj5$jsQaq5eFQypR5hE^nF#8GWkhv8i*HnDQ3eH7D
z3?<o&s7`1Uaj~ciB>%3kXx{rKw%a(cgTH>EZ7;veS|?gnJG*?%4MgtleDOi+O|Bgv
z{U-;i=K_lO$bxApuw41oVA*LNq_|yjE2OqAs>>L(#&#=vpii;4VE>dSn@@U-1@tLB
z9bK_a?zhNK`|U(ud!owP7cN`)P|*4zjPX`VjNbf6zSNs`W`9H`tZc#~@T#pwdmMuz
zWPbK7^zL_~2s-AQK=?TQPyafq{d?ZUGU{3|{}GCR2?yN;pvHnFM$DGhtXSoHk8bM4
zOA*1$9?AojEy2`$+P(BKU3Istkw8kcQmtyL>l`>!WZ~gS^X`k;;`$|%!M@felX2i*
zarEKXHxB2Myy%ugHG&R_vB=MA`<q$YyEtnf;I`1vdp8a82P(VjG@Xu6L+`x`;qsJM
z;iXA5(1X<E&bGpRx4mm)>nrc&t*y87W#%^$h6;4q8|dV`6PJCI{e|icrf0p6YG7eh
z_%a$)dZW#9|J1&;(8Xqh3&eK$je<@*=XTy-E3=#aF{iWsR;($j?l8A%H|h8Vt>s%;
zfQL|p%{P_yWj5TMsDi3#qj`Q))a}6!y=>*@zO%>fJbIqXPyVIVIFl;N2Q%(C;#0k#
zL}h$^In8}YHWd6*9bR21ehvmc4&o|hPZ0bqcQKUnDUi>7mZgZJx97f&8E!pv(AlA*
z3k9_jn7s(X(=v3puzr6n-4?1H70(Glr|q=36UQwpZvUPu%2+QtwWnKnVizqkL*e`n
zSoYK3YGo&X{{kOrfxXV}f6&QN?)fxF9ha$T@j+9>WPHFQ-z1ap<nu&>!jqBaik{eU
zVD2YAGquus=4}+=%f==SZz+-Nm8<po%;IL;q`HreBhEiNuQ0DTd<{FU!Se8<2deJN
z?_8|2El*ha=lk8UPu<4O4=8v4?!~tG%YVNzeW@d!e!XUj2`8;!X$2}{K<-b{L28%m
zsT;EpTVI{3Jhi_FL6?_2u^Q~Y>7se`hEje1iQ9tNy?My!ZzVinUPk(Y#Ur>jA9uQT
z#U@S@N{<-mcB%GDIEY9Hr&zs@C!x18AMgAmY$SBHE+w;<Y1NLC2hiFEItsM<j+$#l
zw%z{5Qh3<S7h9|qZ1Ez0v&B)fyq$cgE1YQM`6)g7H(IdIQehmDJ^iH3tUJ<mv`O`!
zvc)d$5Kiowu+1X(S(sH%Pk)d&V{%CLy({xFKXIP5HVXK^j0?GRK(ISiuB2Dp^qFm_
zSn-6LkZS~VA3srb#Q^<2D}9u58!9`6=f0f&V&0telCdER65;^(HXcG8bxbL?q3`jI
zz?cP6iV!eebd6y|#0Af*qQ;CP`s!4<Wub7YuSI_FAm$=eF4<aH3w=gXSi?l}?P9|2
zLs8zue@x;=O0!sAB~fW{<{&Y&WEPe$#g>PehvJ-kxkDggPVli)xEzjr6^`tX!stR}
zq*02PVyFBRcW%fsN~^xk4aSoJ2jaXl96=a^kwe{lv&|bjDh-mlV&6lmlXR;@xKFIZ
z9?oK}1Ew*Jvd8c;4|mqFIX58<6LBpQHeR+pTP~|fpDnlHI*3*cJ+fXTuUKgxXHw}z
zlH%A@tK;w}f;{@n;#I7@B4aoNF!Nr66PHb>Cjmqsvj^pZ?uzVUuTA)lTxoEiYq1T)
z5OGTjw#lc(Q_c#EEUhoeCC=EQPgQ>&5eo_(4YlA}W-cxs)+q`I1~yP8`0xcN4-q*A
z&}3bOT-b19o<0B_`eFu#O4Sv?O@>A4m}9%3N2xmcj2NPGH$gL{Iet5+;6EpH2z8Vo
zKs~;B(xiGnH=RPCNeMqM2M|lVL2$%kDwm+)tnrVuyI^=GKfRE-RnE`GwgXM)AssWB
zw>EB|P}y#<LoRw`z(y>!Tq`ST33Q9N4{aJVNG};WbBc|ZVtTo3GKEC<P-D`NE)eud
zg8rnF4ABJRBitjBbIFaIgu6R9SPVp0Y%FH6lnt)#i>X^~d_rQl7K1h<&ANb{4wp(L
z2v}WZO8LeD=Rlhjwn)_Mc5$8!hnk=>XouUHh%sy*>&-ri_`!Bfp}c5%^Pv&gQY?{h
zV$2Muna`%KCx{F2Y%e$g6-PCZcSV+5MCv0kHyl|*_iQ3NLTdID*5%jXXUAD2TDX3-
zZQsb;#EF(oWtUsHNHL=zJjg27#`ol9kB*}c7v%Hy&7Kv<-b5LBe=R>vUZ<Eg@%4+q
z3k7<<5zna~AX<|TdC(~D<o-}X#(_t;>897BC0#+WPdjT0@4rd=f<P7zCcav{Xq~I;
z=C;KyN+kWr!b-HOpDHvSMOfF!F$(5E;A#)+WdG{j%hE*!sIAs6R->DC{GM1J1f!Cp
zlXfUsT_oq=DlN!Z_8j<2=lM>L@z?HV!z*-x`JbhlxAv7MIcgjT2k!B{W<U9NGgoYm
z!=3I7wY9KAsI48><y_q*lODA-yLLAUJHq)UqAk4KD(s`Y`B|5!LIce%dyQ)ldVARL
zM5Q_KhPU3r-_=J8yk_uenZCESM<IdoQV;P!+Xr_L-`#`e(w4%ML%of{6oiV<CZ~^d
z&C8u%$y)1|5u;u<Ql;xk8KESF8ry#GN9bm-13y?A4IuiNyU<13pPI0Ct+sBqxe|lT
z`It%PVeXHNG*QWCj{Z%%?H^p5vJIE`RqvGtwd|@tFza>Rlov<;rayS|mllfa4{tEn
zc$8J$Ke>>~oC%S$b=^?vlxR3~!dzi{q*5lem4Zb;1h?G9Nce|*<>6JHrK6807KT&f
zd4HHKs;iE!*2fGJdQ_Xv|4p-pw;p3&mzE}+YGFUMaM!`p`#1>nK?|K1=>%IBarw_1
z6mpRgh_Nxi+vN9FS?4!CV%O0a3Y~7Ga@KlO;3WF2bkfa#^j0bmTFO?Ev|C<R&xe$X
zM_rr}r-mdHeq({|XK}yDmh1D+I}1M%C%E>nE-_?vXKcTA-?tYAvORoz8u&M%{!DCI
z%7!kcJot)p_r0+%TLi^6Kg#bnP}KhToo1acwGNcC|6NVxL_S{kwKPo;5w1P;9!jZ}
z93hxHrPr<gk+b|4vd!$i>%utA*QUC+Wo^56;?x9-aedfgX50NO%JDURJw;rBh)>f1
z>6(_GemGbWRn5;|XxDw{opZe7%S81H?=CwW4IB&hz5WjHjxcnzTVB-fQ!=uhdi_%L
zz(;7|?(tZF17zD%B&%q1v3jRYyeExU`5?=-KOzk^R0MPPwKBhYahBU><8<%H>FMGV
z!6}11!DkO<`LnoZglZdwU(B!(xyMR|9I(a*S-&%7)1U+-)MKSB*l892$W%D+Opf4q
zXflqD+(2_53B}X_s*~DexiZ&lbCW5_3VC_X^}45MjLhnsMTSPw0}&AK30$;dJ67Or
zo*~3*rps(;7Ap=Eiz+C4YW5<IDt1~O;yk}`!IfUwk_Q5CIqXM(Tz?ukD+T~%yA#O0
z2G=;o8o(OlekvTEz>vx%8o^T}yi(cVjF=kw8OTvF-eFDAI0RlsNbGX9pT)Wjl}y0G
zXL5`({XNvH+Dn8`+p=<(xirR5EpAM5>_X?}J8c@n04bi3gHkN%5Mrp0FQ=XCs47}6
zwqL2OnI}YHISR>z>kCHIIM7298|LTT&5~UW8r^!hTT&d_I&e}$h<0l$csb_nU{iP=
z><0Q$ZvxI`qi4^h@NQDv$f8cTY8|a3uoMytoU<Vlj<NMw*UkX7+2{@o20H3wWjo6Q
z#UW{rG>0rOFW~TS#G;83Ga7QW<qpNp)inaKZPO`{hvg?B5?BwPgPOl5#*a2iox6%!
zOM@#~Npd~ukC`4UMm-i_WRpP+la@{<1pKSW!BZAr#|^hSb}Sera6<DkYUtFqHuIO{
z*7MLktIouNxRiG5og5><^)Z~To6It{I22SMD)J~;QeovvgnRsa;hDae!;Jch1soCL
z^jRrM#3})^CxaTy6z0S-r8-1qcOvp6AA&(j!@&^^(gC$6aVEkMVgs{@&5YdD&lAWl
zLLE8OV&+B#R;Lh8A9}S*5h`XnCA(ri)DZ)g@(RjHKhH1l8y_T|!8-fUK+@U4h=FjN
zaK`&3O_;|Kd1wO0uq#Iw74e!}WJCAhT!_JXc+?FILRW=sATTOvWa61XGSk*`b&Ojq
z<Vs2Xj^foAXIVOIv|NXl#!$Kq{(4pej%0qWdz%#tm*@FTmbMXhxK<zJM#kr+yzZhq
z-o*6o;_cW+NblH`wCjUorMtA_SNh6sMDgBwSIu;164`!+R1EPMS9`MCI##Bn_}ZZ?
z@BM<kmu!7KDbjpvI;$zncwU2GuF)G*TO)td%_4up?fCY*Q2m^>v!87-`-uBDh1Avp
z{WsPHm(z1Z`E>4W<)#BnU$R3=lA`3Q!P#jd0!n@F(tz6fQJV;URS#>%)61gJzw=_A
z^@NVhF~Hq`<n&G=^H04l(m?s}<F<G1XqG>HIp4GUH|-{Ti0z5{+H~-p=MNPHFS=zk
z)>woG&fh>egy&Dcw<`X}pD(qIh1xoiYu~MiTVkMA%)`5=G?`ufYBqZ#nhKYc7CmST
z2hU<No2ou(E?1Vh-i{OKZL#uEXCQFS<_Ff>;^*%%*^jH5x^|_lRwK?lw&nbU68Mb<
zHg5yCIo0J(&Rk&cLTz1Rz(Q?>!p!o#D({7@!#uEWOf7_)xM+;s*22*cV%IDlJwIjZ
zE_{PTy*)O6l(FafFHOwb2TSlC%=jt?^O`$(^DA;z6)WO$I26_ie!}tApmn3#s*hFH
zu>b8(vU&55L;mt-s{{V%<DrSz-JYiswc9#(LDtjNvFa~Kwi1(S+cR#C)3Gn>+l<tL
zvwat(%8y-(7wLa+W%;D`UwLcM7x85?g$@I<ZJmEh*L3yIiQm7HZVKwu*9M9H4HUe?
zp-*~f|I4kgqb^CtcP67k{g?jSCWN9iac9(nHd4I_(CGZu)Jpc#433}vmGBB`t2Vkf
z|KyU&q3|$Uf#iMPW<8f|qqbZezTL;#S$zTFQ0uuPCXP#&dERggk68{%@grMR5gzym
zD8zTakQJ@#At5RY{6>N}TRM3gV`@@c^FR{HCUEZ5?D~4RHk&iPp^Mros-vMiaoA_8
zs7qB3=>aa9GA^KHA5Fdkbd@^x672Xd6%W-prl``-IL>NNiY;3HK<|;FcQFfXam3El
zO`_RB9T3Oc`?WPcg?2g<Yh)tLmfeAKygJ~B90grF(aP-p$86EQr(m}=;cxLs1}beH
zueS$R^DYk4z>sY)ogzbTUwABr^=0bp*g`ja<vc4uDZ*dRdUpT!MU-F<=dPSj-!gNP
zgvHJ{#_ekK*xbF?No}1(Z9NNEEvQ6hQ-wdaL;PpqZU@X$U7@K^I9KlhU@>CO%2`TV
zish5w30P66z=OBgqx*?duH0OcI>rt$R;tUCDcWK20MltrFKd45>}{q=ov$kf2`fPJ
z6ql(AqKt){R(5fWf+8oAn(PV$p_GyY9>it&fubvuL#OT)$`s^LOivEd*ZEpU&IsW^
z+ItDE4zN!vT_mRjBl{7vj_@et{JEu<)1!M~fL7ue0WoK~4YVv*qXz7lu16v6!n4M&
z7eiP{EjpIAul6^*ibN&VKz7$-yd2%b4AN|wflJM_t#UX7BC_0*s{u+8mKqO&j@fj2
zjbs($_yvBW!AC?$M(}Y*&|pR2ASvPj!MT`=^vH0W8dWpucMdT%@tZseC2I8@J;mk(
zOH{eXAX!eStPmNmU!4ceUBJ@^BRH=VjoR8r<r~!2#phA89Aw=X4}aPttumKQH_twe
z*@=-3=M2^P#l2=vz#s&RWj7Q)`XEnKWyqoDNQ`GB_y<9OL^yP5EK*ERD%<yqlmLE^
z79dkW0eo^Z*P)EK`;hSa-XRXBI6dTROb)M`4)Wp;2H98*jGOUX8Qs3R&*or(7>lqs
zb3Wr4rpTLgU_KC<_jq?Mi^6sg5@!VGDj^Vjp;{jW*RduL$Lw`D6U@~q0-X`9s$9yc
z)@So=rLK-Ym&Ifp7H>yXv5Rd`Vky{d4GQ=*ekbK{{DL@C^cp{E-iKiJF1pLMd77nq
zLjpztb1-OlYOA`-La0O(sH<nK8+~=(>S|BweQ7$T`<S<Zsq?mHs0;FUg3uPyOq$%P
zBr$z-$O9KH_VaSWSLH4mD3ViPK~-TFD;VyG*cL<LOt4?2pr7>eAfb>R=IGnaP!dF`
zE_Qh!Hv+R@o$F~q_hoh%wYBXpw;YCsgF{xm2dS&Cw3a4!+|P0WmH17x(4Ia?ctz$l
zZ9#vm$!%Q~>)7nIH`&4Pc8d5po~^APUUoVp+#eEm%baYv)sHf4u+r@Rc?itKEDDxM
zntgLJHh9<jEiXKZ$wxQhkvMc?okT`$WhWy>$@q~}tzkQ)AGOm#hC1gQUTkmr>^&{&
zB#y~aTf691b*p;*d+eyvm7S}5#fz6NL>h745M8fdXwQTbmQ8#ehL3;09b~t4!v5fJ
zWS`HH)#H`@a$Ta8iS^53!eIuSnLCbgYq^}wQIKBUNM2at0O_PR_v>$3e)e+of>-$p
z^e{^OxL2lazT+>XO<k#%PZID2i}ToR4StJDFEs0}zMN+$squA%gN@p1-Rf=5&wOjs
zIuB*V$=2lv15ITd2;2d>)_bWnVSBE~s{?P8L8-Vw#x6hNy_aXtJMyTuqS7#};%xH#
zs}otgTC;q#bP+}3IQ2($`yN@XAVVv+hpD9Y4_#GMX}7h!@D4hke5UNFYW~?4Q)P)k
zTVq~2slziX;u>WAx86K&`#3VW`JLJIC%&;~%0Q{wJ+^2;33uF^MkKra2M)!VQuxC?
zq#6VG+83kQ55O5~Blf^snwnrYlD986zi3OZyy~dq$BXqbsF{6;6HM*}c&ay5mFOvc
zJ>}u#ixF&&>qK_k5WM-@tEuZ+BG$!P$8qXU_SiF0I&qJN>6^MUKYeQNTKT<iZ3lh2
z6Oc~oo}Ax^=WN#=n{o$eB}K}XXmn#Iln_@$lmM=^=;jwlEB`2<nNozuZz<i$|08d9
zTm2nZTl=oK+e&&ZyTopJ`6)h8dH8nAR>B@12+V)&U(9x|!l7*a{Bp3RZ`~IBU%lPJ
z@0~zOin;xrhs>S0!}fDXI4Qpy;|#18GQW5z30J$V@sd)}vjuCP%Di8_!ConU;XQuk
zzG=T*;Su8;hPsFD;qLF{_s?3<qr|oTDAY;RRy_?=FcEQYm5#U_)cV+wj4=hKiy=7j
zYR}#M-XliuW{|DhdJ8GOh5$oDok_wL0_$qS@~DNG7yd4eE3DI~tq0MKT@H$?yQl#6
zHjFGS=r^H@Zdz}GruXrw9%?HinZNiH+fczJO7qQ?GM2rHuDDS!Lt-tE$Z)Ax7N{Yu
zvFUNpzCO8e(JO`HknqfL$-+)to8ogz%h}J`3hIMmMnKmN(cemxsI3cAakxoI$Sv^i
zZ-z`%Li~<mpNlSi38@$i`x0`IJ196BZt9H8)|sCA?etwf_3fe*)ey8c6ccHdFfzxO
z0P^U;8YCPEc++x_dU{q=6uqVwry}_s${?s%-1~>qNwf)|m7pKe1e|F*0(e)88MZVk
zpVTS^0-_R2<Z;Y841yBrK!E&!qyCc%)93KdAprUdhp!IDW>&0}5i`VvlqjAWVRvg!
zp=82U5&J;7@+@<iC-xO$Tt8-nBS3GVt8xW|SM%U|OwA@q>G&x^%MG4qhY3;3nTx@S
z5=4<+YMB@tDc+a@86F6eqR0H%kxJ7$)isBWGt14pwmp6zkfVtS5tY~@b3JSYcz&SP
zFh;&1=`c{DEL9gH5scQ;k&dUOdbvEe&)9>Yv0W}dj}bq|uMxWThFwq~4LY&mL3er!
z?1qN1^VE1pv$mq!OrvlM7y$BEQn@q*-N0V9;Gk3&K{2C1`jQutBqtD)9XSN@^!R;(
zGZ#razyr)DnUH^oelgOCt}zS;PT;3^E+QnkB*9tBr)(7%QcS`8p9%2<A;)WOr9bwe
zVZ9%4mLp`x>acw8DkZjQ<OHc#>QF4ntR3HH6m!{p+ty5&0^hM``9`CcJLlCxwZUGH
zkG<QIDf^}{+i&AH#S-2S2>rN_RT5+$f(px>fK0%G{itShX^FCru$yD5VZ7gVcVK$?
zl#{b9Ig`M#$}Hwj>R2YPD1jtD7PP@~HKy#wjk8+tm~;HR!wAf87Rj;nc%tkiu9!Wx
zgN3sfX9zn3n#+0!R*GLw(ftJ^Un|P<${=P-NZpyj!6(R20s0x)2e}HBVH?Diz(q3}
zZos`AdWI{D44o0Etl*Q~))V>htSq~?xsCktF`gW9yeB+Jx6*4h3`NqarfhrT^oQvc
zPp`r3uM&PM{lFHvSvQGwKKl$M+{y@gD-Py5#0>|hXx^OVe3=WHqzyC#E``rJ_WtiD
ze?Fj{pN22y5q#MvJ7mj$(Q<n$cMYT$Xg%{d??p?n5TZ52$U_lh!{5N#+E01*np5LA
zeS2(}Xi+NHYDA(l+N6`ZROO-;yQ=c<f61y7xpn<T6#hAam#$h@EIsBre8Q=Wm>^u@
z<nCJMyga>UBJXan79(KqGv?E~t@Wcq&)j|Z@!;lOSm=K0@=3e)tL@-p2D_1}!wVe}
zj$Z{7W2#R;DLLX<&UyKyz+C(WOAr5EYAagL9Cvcs$~Q0MvIu0uyR9xNva9dqN&28A
zK`7xc&;e3uE~rO^vh6rzK(<aF&ggXalo`9f*I&#lwX3~%TYl4DEAyZF1{>WdTcE%q
z#AkVFFpxH^;t2s`C`@G;wcxF|g?r3TlUGt(*;@^<Lh>iyUoCX>d8|nDnxe0^ZWh<@
z1i$j%AgSjNlWri@A>pSs_r$M|(5pa=|JaduZ1>XrNtof&=Z8s0$WUNr7=*x8tRbqc
z&~j>UKz`$OMS0-c!FvCOx$V*0W92AfcW^{Kbg<n2>HoNzYNH+-f|5kFwRsi!$^W$4
zQ7x1|sHF)-AAC?ZbpS0YS|OWK-_L(%85B4a9HoGIl5Iwb>NSi&Doqs*wogq=v?*G+
z=BTp;LZus*H=p29>h1B1Dz4*aph%LXUv0@d0;mvw-yYk0&--Bb%TVXtRsj?`4?O)n
znSJ(3t3LJTkdhd@qV(db>NtFik?pdd%VM^ArrpL@_@c5F%J^U58)SI^J&uac|6Af|
zeNw2oC^q-vayaCcd2qA(-PS=7c8k{*?0w8*vh0bERH&`X%5gX_sb&9>E7Vuc-oe-T
zlY8h>J5g<2xjt;5Kla*7m(9moHP3=jgx7vj{L>7iYxzsF6di+hF<6hCg}QcI<8Gc#
z+tlEr?Z1{SM@Rhn5#l;bNBqg~H)eSa;+#V2MeN~*e^-8={d#uDPUT*&mpnW5S+$EG
zDdqNgZercy5XR~|L!Qb*@We(DpBT#yWo6ZUZxm=C!U{TK*H>|4pFwDh&raQG>0q@G
z-<OZ9h3)6BGimd^OPo`}1~e^P17!}|z0Hh8;W2@f=@ZZW@`wa8b2y^lsI7uf^XH<E
z%FEZHE4J<EN+L*sBhAf(A^J50(!1!E23$j&rI1C*@D}V@@t}5dyP_L*vG>=^DR?)S
zaKtdA0zGIodW!th9FhGv2V#R0Rru&b+`OoLE6FB0$TfusA}UXZQ$REnNyAv;dH8OD
zazql*s1r-Oo|C3B&u^g)9Bsjpe<lyUeJ1M53Ybj!_>){3W9Z^ncg*>S>G(iiEK`RK
zQF4qzKGfrgV)R6u-HouQIQkxkrL~ZJf?iy1Ah^lY&*N^F2#-z@F3Xl%V%F+oTu`WT
zqK>0m{t>Xsi|ndVL5oy+4uIGo_#!XPD)-i@$Ra_ngMD^!AhI*KYPpEz6@ftWZloz6
zFds{h+~+n!q-gV;Nsg-*egI7!YIsJ)&x20Y{(4-Q9zZyUGv-d?%FuP8=$E%~+FZ<$
zN=z7Wz@$$uiV%`?&MdO)fR>PP><R;go@T;UOFEcJr)uhxeYsYXQ6sJ<xMNN<J3<i-
zn?@@Nh>%3n_|9QF(e~o5NLfsWh}DaxmpRD-5l9U<?Y7<&eZkrtQv2M|7IF0GK8Wx^
zv5#e4S=JsXnB=f&v!Ljcn!}+378o(-RT!X&55k+`vNxT}qDFOw*|Ff_Mx19>h_i-G
zmk9Ng@yB9ljM*Vc#VOP)>+c>&-sBb&2bsK!7d_O4s>9-|F)>7j>$~I_nXTK;(v<h0
z_W7140uPh|%K#6VPhp)UIU2Gt|HK7BFDDciWUr7=yl-w3Rxl*X1(<9n&oDEUT;>W!
z$|~ZsV*bGOboa-zy{_A;?)R7HVHlwpCk)iqY9dVCowJso+p9%W4sM6f7J2C@<`IXX
za%tK^czby@7chZ!+C>^NI(xSkYR}P}LXLo-_(vAJEY|X?Dti@y!#rn`1)|_R#-@Fq
zNs=J&J#hP<TP=s%=Z|3aS|~(6T=|L9cz}LYCGR=RgNv+x^C0*+BA?p3nWf!UPNJ1d
z_S%8MuWpc;zN8^=Wjj=;t*Hk+sR!<8UKA%J`yZzFIFTQ6D{oyFs?VghcK<iI8_?0`
zwJNup^)CM?=+~n@(mq!+kP`9UBl?m15c&dYE4!^BjG`7Z{0hBb=l^c;*@63=uf7~C
zXJ#&?<HSAt<Ca*UAbfd~eYe;5JP>BSWsWnZ`_tJ@<xubtaW2%w_E3H>C~P>WoN>cV
zXlO1OpI2C>66YT{->*<azd*Pr+x<7c-f|nl`e%HA{_UsOwWG|-@sp5SZ;ol<V=v5}
zbvcL<odNr8eeF-)&6%TVdqKx!3)I$ma1L@_IUJ+Dj~tpc_grQdiNW=(n2lShPGtUa
zE5sXyR*tlIpswT!`qxVTO17tZhT>Z+`)!x?;&bK+041wV(MrOvun$YXaG>7}!qAJu
zjoKPh_(gBGJXw_0e=z%(pRH^U2f;_T5|S=I#KQW?U*o20H4<d1f(Cy1`8T=D$<3K=
zoBknhY*l*u=-YCRY9ouwzJuruK>YE;szDy<y5oS4(s-5rE@sQ}0uW@xh|^hUA}WvA
z_PqP^>?V<|c3WHL&!h4Rw@C|1;zfbGg6B%kS6Vjt@EtxtYgzBMYGj{&ln88n?y}T=
zxJL|$-r?IB@suq!RDS8_Sd_Z=JQPUo+FHK16?{0v)4*3hs=zhZ5A0zL;A)s9aq~SA
zTe%?vXB6ahb}+CvzT27-WTuV4Q~QI3o5Oth#8ug`mFd0DfISlYiI$tPdp~++8wj?Q
zbV<er9_3U2F;8!M9{)b?+4iK*ziA;7S2d_9^dzCFsEx+((MEw%>=W7*nw5Ihl7NFV
zNjP!$SKVKEoI?s^JD=3n`!Wf>hFawv2x(%@uqlRp=`hE;al|7upLGc%QRwP(mw7YM
zS4_9uSm#;0m6|`Ct+ckJY2QmbcKf;()z(*vr@2N6sY`F&V0BTViVz*po&01T>Y!m(
z%{&aS+bW3)f{Yb@)hykK)Q*ZpxpewiQA5C~IxnM`v05e9ZSgoC6B4+F!-qHpv})>9
zdQ6yKC|LMP90@oa4OcjK2O&9ranSD2x5{%aNYpO10J?AZs}^^ldVFv<3K&{o(+Q3B
z5Lq?&RG=c3y=Ov8koKFCNW#2!TLoNiABEH-OK>X}I4VInFT0pIVKfkDV4cu-ceCAE
z6SF*!c^#&)J<E(2q)}LC{3EB;4J~HvR_({9nh6GPax+jYMkk>mFcQ&Wx%p0vq}x4_
zIUfsE2PA%8vEZA4k@g<Q$Hs6brk}L3tA~`XFBI6mV>DJh3COeT4W^2mok`%_{w%&n
z>tdvyA!I~q{q~D{LY!(P7CIu?gYwmWvV{?G#Xz|EJP8m;VO{}n=2|up6z2#CZ8i-a
z14URNnmC3*Uk+LGyboYAA}O=5<XJr!U~d5BTu#<7CQ_4(v7wKnMkz8Ke*VCuuQXYA
zkubHs(B$BWwhW)^SP?x67zs-aMvn;-=QDOT_C&nwxEiZk%i6QZ(F!sNnuerjr;Z-O
znseu~V-Mn5lJ|7*{Zv#Jp0!xdO`vnAt*RJ-_Z|Bc)(X6rqz;D|80rT(A?;0p#JCvC
zL_W_&b_~dcgK!PCRZ`!EmhDAHVKzYfIG|QFCKPuZhL5X8V&~S2J-u4FAT_YGSdLeW
zAv5Om<AT@^Ng`fpdi*5y2p+S?quCGWw>x46nruJ*9IYG@1K=&Fb`;`d)G#NzQ+oz2
z7yPz2CQe>%GP6!%+m<&{aSzVEiO4#zcH~xU){Au8bart)*$+Qcd>My?ubp~%zjj-z
zwZ+SAwU0W)v9k6cu_qR3`d1_o<|@5FyAusWhW#`m_)MzJ2W>->m;_!{&bzIdeeI<b
zG{Ou!;<N5YcKGr5l=*K`&%8mJ+h+={oBWIBnUYQ0*Bn)T*t$(3aW}6~WCU;s6*7K~
zL3#`HMr~zo#KgyE;bPKn=~$?s?3!^UQ}Rh|4XYkW<@U7Q9nf`QaB2Hl$n%Y3)iTKh
zA)e=BZ(yxtx3%9MQ{=hK!c^ROZW5jwR9jtOqJ5OC-S1|-4b;|xL&AiOhM?WnJMW~a
zYj&TiEX1-%16>pW<*1p>=l<kPo^Laf37(s7{&toHm7u^-NP!--&MT|qK)8;FJb0ms
z`a8b4Dks^7I2rNsD5Cvow!?aR?2xj(;g7St;`p*I8_xAcrn>#uXRKj6_!t4j-5bBL
zr!23dFwJhOhF6tsojt|;t`B4>LShJ6QM%@ku>BPT^vchhd3IZ~#e>DibVt?3=3CRQ
zz}3}-R{X;Y^1bvw!IOB3HGp>enar`<YF$Uj2naz4{hNfd8eQLhzj1nFdjB7r{oZHW
zC08<KojPu~rFUE1`?A3HG%_8~AJ2c(_RgIq1O9cTuirY|LT!C#Q6HoQbwQ+Q4zbqb
zJwlw{&4=fgVm*i*#|lJCN-<mS>bp1EduTV*6he1wScZp`tu}eDRwnF_dfg-(bz@yp
zeG{Bzm;Lyhaig(?M0lv_{Kk~qcl7F_eCkhIS@?+?A~tHPEomqD!MAhz{SRi-TU0$2
z<nX`bCNz-PZH?y#ygP9l#lF^;<rfRP>k3d*+=`p=!rS(^nWYbx=0sGbI{24M+xigk
ziwYS5UhyjBQ}3B<$|BO%e(icYxOzkBizg<~&8{m#3|7=I;B8ND_kK^AHVCgs8ix{e
zFE2mWyvonp8s_a;o)q_eUR#yG70ntrd*|}&k^w2NI|uw2a}EQ<#2*UYg-i*K(+8EJ
z0C3s{l0DsRz?UfFOCo{VB-<*Twz+^Y{t+f5g5HOj*67wg3OxdP$L#C8QqgV&bB|cY
zZfgRmt*`Qf6}@Xgw$gyIxsu&h=@!5t4&6kR{0LdQeBprq<#Hwl5IGTqvPtLBO)HHx
zsrL~2w)lND#g73hWsmKP0a&3`m3J}A@Z#$_7#xV)-RX$B9qr}ivunc>HPAG0?#sx8
zJ}ZO*N18J+_Th{Wm*UF2@ea4$V6^wiS4g5jpe&FVsTCTrtAmZB3Tr8h(1v4$AXRZR
z9NO(BJ}|mEd19S;<-_=0PXZM#*uO@{6nThVPy@43-5eT63P)(l(<Qa_;*E%h5o*UQ
z%rAUwHD=Pp4YgCkreG13q6gTV`Fr>nFRT7}x}k(336+S;6olAkp{J3S(K^D3EZ96m
z?MJN)F@)k3F1i{6N=0u_4o$?lY@eQqD3}~teUOA_CSgO4^>nn-yN)E)@;uOl_9&<-
zA#xWor*Akoqxhr1_mLcm`m84OkRf-cH(8e-5Kla?+wkM`&VApD9JHLAq-&_mD^Y}4
zubxD6cwH|AMzU~9BwV>Ba6B7Yu}&K73ESWpYgMt+k$K|$j@Sn43>%zcx?;W45mEX&
zRwC-85i^E}d0$R?A2ll#DeC4iu5XYCylJ|tF~HS0%mTD^dD0_a-%r=VDIQ*KLeTDG
zAA296A(oq5)`b#btSrS|9;~b9yqi^<GlK{83)}CBfMT0DQ6vgWWE-8)=-7JvC=yb4
zG_5FIR(=2k;;@`#7C{Gj0v$-K-&GgGMjKU|R3URaFzMB~uYl>sJ#-(Rm_Wg&#~KN$
zFsZDu4Y&dHB*r=*Mzko)T?7PbAQft|j^1I7)0lQ7uv&B>YzJ>fakcl>A^j|c;v_Fs
z@?{_)i3AO5<3HOD3UX^QSyASwe%&>xI8)RJ0WmU)L|A%zwO_44Aw3;Q%&D;jvL?zY
zP{3{p7h#D~1biYMN2=IfQt+;3l9`f|xf?)p7CP7SmChrp=1<(_ImX1w{5a5i(0Vhk
zUs$S#)fE^Cw5I*d#N|x5#1T<>`_ONh7WvcMD5CPJs6cHZaD7M~7Vmc<mMMnsZoIFV
zi?Mad?Bw$cLUl|*q8Q6f=8^GTTk#Wb68>?rh#Dm)k@F)A@4R)JUiMN-fs5u)qc?T@
zf?(kXsggUcv`N%fpYVO@uk&%2#{MizfvS|f@tR<vyr8d3=Z{s^y_6=lA2y%UV?P^T
zF$f?W%G_IcKkkv#;Z3lIO!ZfXiZ4y&m!wA;q}`!@79`vqyRC>rYU|1OWyOX*UXR-9
zcBir(^DaJsv)+07Q0y+)f}*v+FUn!K{8+BOJZ?P2y{Xqa6BVaGE4`zbyNdI>>618!
z_gdj`g3`+WGsrm_wy#zC`}zh-OVxQ*ypjpW*6XcSV8b$IvW7<4{l(vQNu%T>@<sQ3
z-J@+irVZk-qJ7}N4@r-N5GvM43oh2V=^NRLwzm~iP-K7V4?h}rTYcxxFDTj)!diZ-
zO?~;}p0hT<Z$MpZrGDjb)yXfKjfaFoUQ|6IoI`D8w~)E@pV=u7dYQkIj$|_n;iMYq
zXvl(a3eKyxAHb2xmms@w+LzTAvfe2^fb-bV$@2LoW~i;*)_?YEe5GBa>P8ckLTam%
zBSxUwp|<iOG1aR5N9}_9_^N2sC<zGsq)~d=BcWN<5cT=_AByD&N>xXMbWN}_QE1GB
zYy<A;D9O`EK&h_#*;!@jaE=83;up{${v~zr_x_Z%l=_gc)K-oW?9GYro6qq~NDN-o
z>O;cmIsVemmCh+N?Y8n%XKTLvzh*Yqs_;bQY!95N_3>QL#1DS4YTxw_X?-z~67CL5
z{(17vLEr;8kygZY3(j7f%`dgLl$*s9d-M7Go*dLocBf}2Zp&Bf-YT4h(!E?vY7a#q
z)$ZBzGCTDauWe7B=qotUf11#Mq#7vcMmHPJa9iDcAFf>JJ8NCA%1|PuEr%FGCL#9!
zHJ<Nx;sJdhafFF&3cI@|H<)H^Q6Z?UYpAV~V=CLm9+OI3rjDnfun{#Ge1|Wwm91Z@
zD`-AvF3gQ%EQxK{5xx{0LQ0_KAcdMCLLGrtGdCLwxQ9UCe0LIb?-F0*1vADt>3O}>
zo^5d+|5ycWL*oeL+`^7fPdzG8DhP23RRapBt>Rn2A~s3^LdgQY#E-(oLxUs#t^iU{
zBz&4JkjXZUH2+YzAcdDug&9<f8ek~q<MAJA0!P`t&ScZgF!|}zvd$ruM1@_6^&Aa+
zJ9bi>vD>N`9K{kgC-rP%5pHST?6x+EC>R(u1PV7hmOw}lV2=cS@N!8&x|KM4f()pF
zIH^*^NC>c0sZcwh$Hx*ShLX;~2MK{mRo=17Q0*M8khsf~#{-EU^L6S0an&K`uqc7+
z2Qw$_#-sfy#79yc*6LJ<2AqjQg#;ODQfffk`T+clf(jXVkf6kDR-Z=~NSZuSBL8GO
zqZ>nIxK7L?`F$_hmLEVK>veV&D0>}`rk(~-YJf?dId2N_;&l`t+z6Q-^BoZ6oA<$-
z+Q&c^3O^@!l%n_usO5I0wM{r&K`T3Ei~Kh6bmb}dIfpnh2<sd&A>O#|1Oi#fJE}^A
zun$nvqkwFA=gk~bV9UCq6g2@TOjr?eRzaYVbybR@a<Rc0p90{I=Sk?2(~MJBLH0Aw
z3q@hW;aQ?ZxF@s{?kP@8r7ad7H;(l~PX&#{gc|!%W$P3=!4G~cicNUc0*1O;c^qm|
z$TmbeKpZ*UfCayh83A*|JJ2{z1}|QEaUWLb%vPy%ZVxoy<=KiX_oL6{I61+d{^OQk
zLUR@K9+m_}$YNz?nbWd2B0z#UZJ>h75C|wd8eA003epXviAC#Tjx2;JTRr<(2N?uW
zFC()BRGjEcIG6Y#g0;vj3TG|%bSi;$SMn;<Da?bvKz5*v1IwwpC_*7xRs<9HNk@hB
zN;0`!U4b*NVA0enZ;)4<b#YqOAv-)?z1EahGh>U%+6@XF9Lx(PBU1XX=!}9($<Av4
z(_jZEy9SQq2zrF+8*K~jMg!b{SQuBQ+RdzA^y2LVqA-`zXLK$%L&vL_Vvse_l(Q!+
zKi_iQtR9r@B#GLNWZB4kQ??=FrPb-1InM&E*g`}BegX}BZwWssB4x4}$hat&pQKFo
zFeuO<d`x@(&SCJ}42Vf-8!${G4gCwIdqU4C@hNV%3DDJ|LxUQ;vYjkQ<|t^!6;;#o
z+}G4Y94&Td51zJzy)Xd*N!?|h&koW`mu=ehsPfkNp*eFv^llLLS;my~;HDwe3C2Uw
z`mX@LGcDroj}IDnf}$yr8Y8mcml`ULTp|CZ;J=H6p}}=>G)>0KBcP5Fo6$GiD1zcu
z9xsQU0F@^UQ1JNsnaF)EP@WM)Y6p1vB$_^3XQ2q=Oz<=dfs5ujjo9qZ88a-<)sX?7
z#FmPy-j>z0K4XZKnFS3}p+Y(nVj_QL=q~=CaM50o1869Q#?u!~+}m#|G|5!FC}fa1
zrTebIDa8W6nLa6nG~mt(jrpsjiiy3yZ;-Kl!=@uNDB>&v3Oo~(ssz(}9Bcj9(#feo
zFglpn#`dDXq0j?ge0pI`<Z-mZECSO9&1V=-pgF<1;XDEG%-jg%6*a6AJ`e)-wN;mp
zj7d;T<ViLHdSp5if^`FkYN_-3>I&1SL%3%M>?)tD$Z4M7D5{vPR_ZmO+U87YnL&|c
z3}7^mhy}P_QyTacXkhV~TcVa`DHw5*N#IANIIWBdl^e;xszXh9+Z|Z#VZsndD4!BK
zrjfD9;2#cfMh=oSgk9}{5@AvpdwF1z!K=pfn=j5`js%KW`NC$eIv3{rU?3_;R&5c|
znpAMhB`(B?prZ*@$T|=l144rnnQVD#FG4q9=@+4Dd9S&;y`)AKv&EyrHsDnONz)!9
zV>W14m2%dK-eTFd#ZCF>jN7t%>M<rmkUN6!rHg2jFJ?<cy*$sP6g5QOhOtjXUM53s
zIJ$k#IwV<P($WYgQ5a?(gegHjNh?YaqLte*Pst0-aF$cVXfv=L>vP&?r^XGEPUN)?
zkQGb6z*5V0*u43TvjpiCFF}t3WD6u3=@#8Ol@GN;R>MkD)`2KFL*MWFt}z^HD}xkw
zCf+qqMU)k$t9!!*Dp#{z{DLN7^i0sz5%5^_jAMu)e-`5U?-cp|*WO%icF(u=)Q8Jh
zL1$r|5m4GM@a3-)@sT)#EilXa{k6!vZGK~ojhsWsk{dp4^I}T$!`tLi!JgMSmC;ag
zK8ECy$RlVf*S=*t$y0j=2yC9e%F-UBHx>?*^==WzgEF^`-?$>V#&d4l=i$Q;Uy}5H
z-Y>7tCA8j!`xWANaioyu98$2%4>XVK1@yn)n3%Y`D}`k#%O_4Kzm=6#>Z+QO@>=g~
zAt0?E7LP*p_#~eficuqsE%n2%!oVgR4nTN{BQU?`ud;CTATO5xFSdI9K<sYL%H0ST
zzdJRZ?p%y$J{M&tt?hyHom%yrSHxpia`D9*p!eR5UUa&}XPU0$Bp@+C(Mt3)r`|k<
zczL4huR73j9(AtseB8f@6t*KE$3{-2uN2w~-$J2Nwq#OWefq)>AB=wUR-WVJd+AFk
zh}BmotoL{J*uEtef*{e^ViAJWzWSeX3r860J>(+2r{2c4lsr$qyRehrnyBn<?&UA<
zscf0o=J+s()ypWbrQ*Z<p~TsrmA2f4=nX$I9%uH`bhNsoq_<2e(W=3JtsTt2p0C&~
zt>8a*$wU~ZmH5pEHp1^6yNY9NoP~%og&vf(OS2J+q#c!$e>}^ubV1NnvFVc1L%c?q
zcH+SG{0b87z2SsypB*M}S5V{DIZ>4$eCR&5RDhT*)IJd-$oBXtgiJmeyG1?DANqHL
z(!Tjrnk{z4*&KY#WaDjq+5QK(OXI#5E9?C03kv(`t0Uu1S>JY^`Agnke#t*a$CW}3
za<K5(RJQWaNgDZgW-XlHbZBvnEx6~X)=zRRftuEWgDw8!_|un}`}+*7fAuE`9s^o`
zi)kRGv<E+nL_{k=$o>Cnmt-##p*=sjI_<BI7f?5`yW8Dg%q+h*O*+`I9YDM_6_3qv
zR-%4~QuO$7LNK1utMa2P$S9-%q;Edl!hkXk2wOWTf-3tX)m<N|6rmlSuc4X)=^B_<
zliV!)=Zm~T#aV#mSH`(LP3X(}PqMDim2-=k<;^XoP&F(r!@(lre6By{I_md8jo_)V
z@BvDDBrB%EGNJeSD2JCx?<Vc`$YxE8{#v_G;d)B->0f99N7&2xs!Dmle$4N{bo3%^
zuA_{cyrd{v`dH9q9ki(V(oEi^R6d=qpp#WxXfr4=6naI*c^|7hIJGF#<tGRMV@0lU
z0Kz&pAHmOI)hsmmZxR$zbz>GAJfii?B&8vJY}Z05mQ&bpv#lZ|iuTc{CDr&ovkeO6
z8xCUd45c+!W0aY%U4h2s<c_*mUF{);z@kaX>w{;Jb-qUF2cFX*QIZ>d?HS<k2l(28
z%pz{DfbpPAl_gEixh4rs6EW1)q-$5?3oHa5#Lmje5KtfwR6?<)DD-YiY3>k%ha20o
ze_f9WH058SH(&M&nPf!|aAb?ramcV%*U9Sf;;?Ks0jvz>qI;;};TAM{0J17OJ8*MW
z15nQ;-kOhsyFn6)P)pw;cL;!FtEVEvgvQcNOYVS#QHsSLYq0_d%!KF~VdU)wA=Pi=
z6U|CX@0x$V-Kd`|N@P3!+^+8<ZwFIJKm#~%v|RJ9`6_S_k-XAixR%dd<B{!UtYy`D
zKam24ftp9ZGHL<t#3z#&Q1)aor-%?T=c42Nm<L<EoqWWYa~qxt(?^fVc#^l@+IFaq
z$3g>jLED+^4ZIol3eRw4tQ|kw;4OCAPQ4Rneo&W#CruD%RHMTk9fSa$pSCL&V>uPF
zE9AuuAo&<S>5Fb3Q40~a?&hF<cTN@aHN5V)^4<Ro?A_fbRXfB?EK(EUv(VDv&kzF~
zt@d3_RNp>W^VSa-%YjI27iK*j2m+%>{()^;<u+sV9?jFW9lwif6Xq#^g_VLjgk~Qm
znJ0(~Po&h+1ZVQ3GiQuA{VyQ%H2<zJIkY%I>bT{UQeygw?_MLs)ibH|G0t#gO|xyn
z9XFJFTmK#F&h@Ug&eP}H-f7+h`JpC$i0!7INNTH!yA!_fy#oyO4%@W<=OCP3tFh)M
z4-5*X4!wWhK%$-W&gs)<9X+o|sQYTb$r1YpJN71eSHbB;%LDpNg!|tdEmU6Y`Nxgn
zVod1$1<0rw9Dir!SLgbvW~!emIa0Zl^ZDy(HRu{XP{cCM*gt?lzYrdZ2XY>wS2~fK
z>;1@5!~=&#+xd@Jxs|3fa8|hLuH4(Hw+(a&4b^kmy=gj;S5cQX`vR0q^65`rlCN)c
z-peahEMB6vE}tv)nPGYNM%xV6eBaBOsQZOFT9l8|D&te33Xdnz_WU;e{2R1qVQoF%
za;7pX^EHLUME9+x0a*dVz$sFX1?LYdy*VWi1t&+0z~1V9)UJ)0yuoy=$Lum@@+^;V
zN?V|*pz;bO@EZj`v^c{cwc5I~xA+lePpGYc=eP2MS5{T^-)GkQHcGNWB2B5S0e7}^
zU9iqdE9gL`l`GD?)Yg~KNhy8^{w|Jrag*&VAFHf6Gq>1dgZ-Y%3kQKw;Oyh1L~UI<
zOKtsXd!PBQ{B2vh<u+US{3W!$F(7O{V79)=x9ZRVD_5t8lEfYK<HfdglJgIK+m2oS
zA#;?0qo1b{Y$N_9h3IC@n_nNRF;N1VN0&sdkRcTq=x5tY-}DSupUzUBh(hP|Mw`wb
zmR$7{IpeMyD@hwsJZ~}#hi<uPzwncM*79g|C^n=|-w|i+ZA!BF5C3Tq{@c5k{KAnv
zJcc3!x$;TQWO^|<#m7-*zFpZ`_ZPYG^Bq~`PF$F^QCn^LXMDbF*B1HYMT-Tc>IBm2
zQ=QdSpDcoXaN0Vf7$d>Q=arq**3R1@DnUeW7W^Jmn(ic@A-s6ucK@ka32ZcUe{t_Z
zc5*fpbT55sgUPO?d*EU$c%5G}^SA7ebh*fR5J~P1V?%g&j55T8x2EJiT1S(oZ*FCE
z6?1#3dIN_-$47l|g*|i)tcxj|4xG_9#r~q7beMw!DJ`BYR_Y_In_C`ionY)#hqRt?
zjNfzo8mQcXm=XSywzB%$Xh$pJjN`!eS8~f=Wkjw%YzLWz+05}bLzYtEc2cPCfz40k
zkG$#FIQ6iu^5~SM*^gmwgPX<ehz-yUFX8E=etsL}T&^_*=Jt4uqh8JhE@cE=T6f1s
zlrrYC6Fc_fJA;P!I5o8$yDBH;_jOQXn~MPyba2Zxq)<gQEW3_;!y#L&zsagSn^^FK
zA6j{4*Rgce32MRHAiYnm3JA!+>yi~^*v=W9f`S1r<7s|_wUOFg3Ts#t-bnCgVmP%D
zPOKANO2FYvgmd}5xNb8&xnrBpv+-QXwJQYA6oEm_;o6pG^vG~BT9(EuxrahF7&}n#
z7|sS@iYB5X7uhyy$6SnAiDt^w$sJ@2hdf4adReNzjvN4)I0yX&)sP|zei2qPYnlt=
zx6&U>7g-d`NgzcDXS%gj>q=Twce%y_-H;OraDS4Ij!{Oa5wiM?ndFV@&5YPp)R)bP
zSl;KZPO^*Dr5wSjA)F0jF^0CFM^p8u@Hu`t6&N85JaY7JnLRsJwjWEW6ESP~MahiZ
zA|Oqhi>{VWGvc0B5ZKeyu_^vTWHuy}Xo{l|5NspRewB-hHP;@fz{=J;O3#%iwIDzX
zJqry}R~MF%a~b#=nh;wK1mHzj%_mdty%^Frq<S@Z^#gZt2s1&wG7~*LOqvXNI=i3m
z0d1jjS7R-?)BF;D=MYO+OgU|vEX1T`6_!%`+4bj|R<NC77uQ+24H6rSoNWkf^5j6@
z%%`qR&H?ZP?sGd`rsc8K1;uvwtx$=`DMC*D31oWf=g*p|?NfLSjii1Nzl$8x1`1rA
z_<2`hd9{kJT(z~me3SyuVY(e+!<WD(>vt@>aphu<+M2y$A1>X!b@WgxXSY@F#V-j<
zY_pG07%zcLZRvnZ5}~)A7ObzJy?(uEEHAt%_7?}Z?j#Tw`$^WS4)a)z15i)!2q#!x
zc#Gai44Mil%Wc>^KTG7Eoz3jE^KC+$+4K9uHcI<KIz)JuF%$wHsb#mdvM)W><rO@Z
zm9B2IV@}Eb6xp8+5ZJ-~2NK1~hkU}m!OIy)3dJaUhD%Dzd}{%wPb_o^I`g)=M<~Z#
zn?&DLZ^$M>BTSU@0=2c@tc0$QY=-$gS#k8BliFG|g4>-I7;}j7`{EuVXg;C_6bFY&
z!(N#NTo^3w+EOpfHKI44$ciAWtuALNm4EeyPwVxP$MJ6@g;E&11KG}>UQMltIeodc
zyw8J;CgqA*B?BSW@7C-4szRCE_bqxyf5BAbtb2;jUNk7uRD`m#If%%az&%~|66bKM
zuaXt7;AJms9F5E8KL5chmN%nHp53ZtL_pd8%G>fHVB54ayZT!hD|obOc3Zo?YI*xp
zn()Ct4JNgfjUnsI3pa9xrs9uIRyK9OB$wf!9+>Ph7zk&nt*@S3vgH>zi*o~2@VQIQ
zwFGnq^)CKTJ&@bRCwN^=xjTLW6-jxm%A*MFt%eqg`u+d!tm(rlZvHgv#}d#qyzodA
z-to11$W_2@&?N%u%K_VI$28ug!}S$Sw%Tni``U8M<by1TEbrshMABUNhIyqGXQh)Z
zl#y^J82|dZ^<wYC)na<jFBRAkJ|PO9{6lVM@rSLWkXSa<*38Ru=<l%G`sZ)9&_xf@
zmdqT1^HN)BPR?^xNO|?!(SD!H?c>C#RP){LtmQv?-stugrw=d?@7O_YO$XtXEf7|a
zMfU46-hPGi`2PA7I?`PI#gLUpCS22p4RYbPQy-;wKKA|S=GP<G(+WqU+>UNs;lX;O
zZURQz7uXZ|BN0svDZv(n?CDub5$4$B4f#L0u$~3p8rxihJg$AvnVmR9YnnIu+p|+G
zdtMt0-&z`oL2VT<2F*}xwb+$x?wauHsnVnFOBmI_q-N#K6)*Yb@hOnnx-1oUX3Te6
z0|gH0y}ciU;sA8adzbNmf#H|v7`lUV)B(gnXMkJlX!<PVVjxNpgOK&;iX?dHk3Pn9
zWp-rL5a2D}-}r{vjz|&H4+w5BYXa9a)_N5sD4L(21$!As1c#}#fnS1o*SL1K=a?<1
zEoMArS%*nP1D=c`sMN9KvB@&Svinj*ypRh$!zLZiZMR`}SqWj}Y2k~Z1}Zy22S{j8
zIYxpLhTe|xatwfzdt#!dy*v=JyR+dVmSJc1u0ygmzh#GEY;fSCIcCns0I>5|e#Od>
zXwjgvrpSspC)C;2qI6Ml3<)!Iu(QiBR`@w4`wlx!#|m!mNIABGDb(}Z2Dk0p#dUZ?
z5xvOjx!z7{aY&<>4g(LvD!r4qWVdyu%!!xUy5tGzHwj_8G)8kL4#khqQ*DaDxaCuq
zH^!XPpaBr>6t_cdRX`l+nOGRBTMmEdXRX-XU>?MEw3han2=fdXll{QN@5fMX53WeI
z1tq8(gK(0#^>GO|vQqmrw;dc1Q!<JlC9v6#X?b;V(jSr29)gw8de%;I!2R8TDhOGx
z>aifZmBF+KZ;7X{3X{FaLW=8cm$Be8>^!XLczvKl_Cl#o#7u?*YU4hTg{0yXM=o+t
z2DwK<oold3zXKOVa@nt#HwM+E?bfsd=S&ZUYoOCOw(UR@sbL=5!?VMdWOV{yhgcLA
z!PoXMtKgHxgYolvOwN#V%~~K+K)T~K{G?q7k`M--s}wxc^miz_SQZWa1_z79EQn^I
z0;U{6P>5Hl1$9S(d=Wq{?%XjF9a7x2G8#CEL)8hiNgb*X-NOu@B73sPE($mW72MMH
zJM{lYt~#*M{q1UT>XX~tC5&^J0nYQIM0D@Ue2nkyv#uN{JyR<ak$VoUv0&QM<B9@h
zU!1H7AA2{wVhwrcY8^NL?ms-hR2_S!6%_DP{B|!6CPmri#R~Fv<Erc=*i1)uU$|nn
zip$@xqQitexr^~LZ$+%^(KQn)1)>1NxZMq8-Lk*C(G8z#Wf=^oY`~x1SI(^b=Q-XJ
zfy4@D-c-WCugf9f1YRqbj_X5`+KNC<P|oU?D@Qz$)s)7KqWGD~fDN#DU?&dKe#^kn
z7=v~<)CypT`|_FMptjaf*%mXl&s~!5KXq)vHYcA)Eqk@-M>lBaw7WN&pSb({a#FP8
z)hXEewnOJ1zblno-=Sa77c7qcz#(h@i3@8YwAG_eq-gQMK?~$07U_>aJ4S0#a_z(+
z92)kcl|Oy@w)pr(l}2JxgwCygX_@^NJ_)IP$gtXLc3VGBeEja@qYh+RAbivh2)^B*
z>#V%<`&rff>H*_h@`bCV?H_-P3cuXS&CPXQgJe6^LxO6g?Y+&ifNj$qSl%StsJ0#{
z<0YlGc!hI%qJtG)#jkF<^}O}S{1o4_>>YvM+wU!cD2;;Z1{MjVHxH<-DiXJ?^N9Ix
zv~2btUBtKIp38fqNGU$t{Otqly-%D!gJKQm3IfE)&8Mvh*t&LQIqrwX%XvO%ZbhNT
z|0A6k<%}N?krpU91Ti)iXxtCNjM+*BrZH*17BThKVg&l^Z2i%V{rCUuLb*gH+S1MS
zwb1~|Kbd^A$Q+KyhwPyci2eNw81R0IX383dx>Xg$@!PnDBeMtZ^_f3HYb7K$t>SN9
zlIcjan~>Ui>d$958h#NhUt97iNUqfU83h025Bg`MwsxRq|NFmBoV977GxMiulZScj
zmWWXhRD`(O`rr-B(nTvmVZBZI$h^BaH?i`gt4CI^&DWc_UG3v&)EP=#!6D&3r5Zbg
z|Kw`t1$3}SDNPTtqCcu4fR`7O9ghv4PVRXBOXJ+tCfkEMBOgiL4xJ!S%YnA8Y{l55
zT~D!<2`J5NFTqay6+#+tjbk^vEdMHFdga^;)kSEWeh{y^c2aj1v-|YifFu^&g&{=c
zRBCJZ7w~XozrQ=ollETty4AR&>8EVYa@UL0dK69I(YaUb(Y2X_?uxm(Q%EuAH2JWP
z!qaZ6#-43(v$)m4Z%s9Ffs5flV*@9R>5^Upi7q7qybQsjT5*owMK4p1JCnmZ+E)X<
zaE)_Ud!WAzLYn92<)|T-JxwVhAHt@h^MKvK!(`3lWZF77$?^j{#MrY879qSO0?}N>
zju2{FQ)33tGpHQYDYF{Z;Hp$IZx+<$2PvgE{3`a-H5LO)U5ib^;<33VZZ|s+Q8Sc#
z+&jRTE1jlt<npo6Eu>CMC*#pte3W2APyAYookJ||A<5&CWT~>nSex`IM5tEq7lG&5
zCD(AXDRg6J9(;$un*bWSXR=Qo88O|g?TuGo)B;@53IqW!4qhuDwBZnsg7UtJFnKS7
zhSTpDoMQ+_cKU9}06Z<!X;3?HVWE?H8BclHerEPgjHu0$sM6e;b{9<!-E!tD?;TQm
z90xoDt1(sM2;~k2{y*a02fDK2zVrOu`>xclh3I~2L?bXXC0Sq@u>B0!>DUY@2^kAa
z65)W;cAWUphv4>~%ybg$A&Kpj)D4yi<H&?KO?I;LaB#MVb&~dsGs`%hGZ%vQkeuFZ
zJHt$v9A~32UJmit-p+2kVcGoI&$sH{Cka}5uXE;{{Ym%MzhBkwSHJrEtEyWM&qZ^v
z5Ok%4KKE=@JFvnZ5d5s70&NS{#dOdJ4pX%RQ?TM)wYeBG8A?JP!e3DlOD|{G`hXv`
z`QyUrRFxrB4GxMy)^`XPX?Rsq&GH4l<VW2K1PY~`mu6|XEI^!+ChOL3aGO?IYg)4F
zByy_1%4Y;l{*>fIX)3hjQ6=uS<wXty4!e_HSD+jNtAQ8u449&f{X$~C(3LTQu~I2)
z4^>J+icGa_xsEWSD`z|AyqAxzOFb)ygWWm<jXX;43`sbfO<RgpSZ1R%G4JH`5`U0w
z5LiNNu0|ATa!2i^<goh`;KT7OIP9abHGmbjZv5p6&LJJeAV*&ah1-M^a4l}~!2x{=
z5QSxi_w<HPzQ(3HM32IbR?-b>2QHR8A+PeRR%EN#Lc~k2?A{HIEv)*~y#mqg0m}S%
z@mSt%o!Wuafph;VTNQuXLa0N_TgZ+8wH5GzlaZsxM2cS*;KI$&`=l!SGI?^Z!?$Fb
z$NnqLm!{mgfR2KV(Ck?D3P~x&O%QMqFWA~A%qgTvS{3;0z30Nq?tGcq61VXEAR-Q}
zuC<2AO?%IjeW1pqOd74GdQI0iqcP3`RNMRJY>3ZOvktYkY>*9lzGGQ)Mi?OrHuC}p
z3|j}QOH%EcIDQheKcL$*7}f>1C+&w{Nq0r~lVIc1A7R)Yn{C<&v8k!v>*zMyjpBHV
zsg~rpEr<<(jcd-sNulP)J?P3*!%5~h>0quKFFsqyV|Ny0_JiPraR-}CN*g_85~I2I
zZpw}uNYhu2A2ZZeI{zo%8~Bln$?g+>jt&cI=5z(;fxlhl_c!0w9Fwja^&q9#2b=>T
zG|ru^$x<&<2h@FZsWm4}Dt>N>ieSTIt$Z=KwdFaw+)saE%7~jrn*AO=hA;9qP`Prc
zT{fj-y}vwUTzFd8Un#GoaFUKdDR6g17TT2eohN=FZSt-@441;0XAidhEOj@-(L9uU
zFW(z)W8>z9#{H{nJ6iU@#|rzM7su@CrAu>r;9X{KLx-~GJ~04ySMiZRWZ*@%INCd$
z-FT%zK%E1F?T4Dp&ii4oanZtwV;A~oM0r~XgsPd!lw6w*i{S0=Yx)>aqQs%LI%<%Q
zwXXSXuM)LXfWN*w=O-bX!yY$;N$q*r`amE}QZJXP)a}r*F|Rl=1rmrKy$*k9r_P@T
zyLW+G+&v3%Hq4LFzh^SBoX_WB*iD)nVP1!@i$DU~0`)c<`kBm5K0li;{Lt<!n?wG9
z_Iksse~~?n59G{z8>7~~`5YEMXt6rAJNv)wXvQCjJn$_B_xw_4^B<vqCQ|Fjr)}xL
zPi6M!M!)d~Epw9DgUZ$Ow{VPFiC=a}pcjyB8_?Y+PrPciw*qkJr;&FBWjLSD*}uwH
zU(b;49bb%vRR^BgTuj~+Xp~GnMv&7Vjf<vMe`M+sBD0IuuVkIHRe2YFt8-R{FU1im
zsI_w<rN-RG?2%p5nZ4ai?>>6OS6N5d2MDkiv}*j<IimtwC#|Qu76K~GVK(w3_-2?q
z;A}C(q8T8wFc<61_z8H-f0f<P@b6Pn_pl$+L1tbHr{CFOm-+ARS>U@}pSC~$o@il5
zF#F)_9((2nWBo9HK+Be`L$4~9{e?r09@w%wVU+ZI4)Y`2D}bHKwsxM*)b#;4v*+Gv
zqxA|vw!cx-b0aE?EwKn4IGg6a1mfX7i47E-cSW-Yu;_7AobsE9w<;rPZeJl)<<pC@
zoh9!ot&Z;b+z>4wARdRbLe@<>N5>hrkt_{G@>sdxY?%T*Y7}UQ?!K>aN&jLc%PiGW
zZAg(?^LVTS>#*AFRe3le#&v+Ki|ccuh@bSV1gZ3_QI2rVw2NN>^DQOkc@}8W^O$|W
zDSXtZSpiGD$0*eiTwM!p8uN{gj)Qca(jFKp_EL5`NmJ1_ix+#jlIiFL(I{rngNZ;m
zk(rafz(ucQAK=Zw8Kti7zxpwq6lrw=GEdOs<b};oa|>XG|FW=VI<fmsXe%Xo2c>Yy
zJ=j~vddUOBs8^*(fOh1160oue^!bE@ECfG_V@_zfCnm;<9I(w3K11$ju`Hwd6IR3j
zY*cnR(3L{%xwQ#u&KD$s!9cl8qOOu#Af?+Bz9&`}=eJI#4q4Ah<s(*sHzvcvXs}2p
z`uDJh2@VyCm2jaD)$euRI`oVt=%Eg9vNX`>F`&|oM3@AYofMF}*Z^=SB=S-94bwu<
zl2d{hv9h1h2%L*&51g<Ab_xbU56iipwSYB;4A*^ZIG7Mhgr1-i6NwD9ay;oF2~g-V
zFD)koY9G#^*AgQ%#&!@~3N0}d#YHVS`9W(`McKRw63k&Ye`#6a3}C3t)*<X{(Fw<j
zBfifFqZ!2#vzA_GL^^|KxAJo{SbS!Mq|>YN6*+ffrMBMxLmV7?0F;oTp;l;k=yBCg
zcHmYqEd*lu9;K9?-V>C#=MOH#Q<Zoyhh1@cAYw`-^YvYrH`CmnM*5kObv$s|#!!_V
zfHh%?WMKX$1}stQq6d7QQ=QLDw&ovsY}Q8Zu6hA5wgyN8UIzUh&_<0>_OGkv#9B&M
zsEBymS6FtkK%Kb&XL*EfU$8Puj0>`1`wEV=A(t46L0i0(;@XhSl%wHhyK8x|C|_M;
zI$OJpv`0f353N1^i*`e6CFE53)uI?<f$2K>OYzd2n}X>%4M|#)s++WITY$sg|08&P
z%)IN|9@B}aC)ke>EPuwFId*u8nIA5szca={=`fer$L;4AX)qCPuS|Q&p*(w?i*jrk
zH+MEqG+MdsZZ6tQ^zz3Sh<;Lq)dyUN0%j}2(e+*KEKIM*(3aTKqm9t|jcc2B{PzaP
zs3$TBg@QiaDQj#&$#{UDB+Ln5Vdc_U9|Q1BKY;Ljux|MpP}iu2IR$>;ZyQCrh3EP#
zzg%a3`+)~x3Pk<9LQ{LWer<<CbXHKYCr@WK6V+&KrG6O-d5fRQESpO-PZkTcM+nQ7
zHEnp}WRTjrUh_y}YbaV_?VXo2{pue(fBYwzaYIf}9ylj0XtdtQrEneQEuCLZc?+~W
zAMWN{@X>#3nfn_i0kAoH6UFL@*m~CmtmS>HVNcS!+oQ*=^;6GM|CX4mKR~(ockq)N
zmv1@*LZmYRjL^N3;EP!&{_^6Ds!#&FSKbxuj=O@-fBjOvfWFYZGlledj}ab|QYKx6
z{PsU<wpB}>UE}5=0$f~WkmOP1X4X#Z4IQC|BWz!fzGx#JN2l5=Jwx9{=*vN=*JSfY
z|8}ygXrvHF=yK_D*5}x;glyLjv44TuiX>IWms+kKCFD2qwdwR^>Q%&9Uzo9OoO?A7
zkI(oou>K-R0`C9XF|FcS`u&RnL`KYY@6D(;1W9cz{dwLFzBv!8-^p7+5sJHq&B=1v
zt1O#1&?>y2ikyuse$!$VZ{GDwq<i}i2b#~N8|w#ZIFTH`h#8y9zrM+K1_b{&viG;=
z6XC1lmKWz|LtfjHgFr-!%Y^ILZFh+cX)n=kdR5d(y|z6Q=qDk6YqD}Y&QXKK-*u@Z
zJHv5wa8+0zL#ZD_dV=hBqr;$P=q?#Dl6`%Lb0v#{4ajC;qWF)kQ(aDv?9JPOpT1BO
zM9$;VPFZyKf4PLxTBTO}YTRNIxwh{FuaNxk_cM}(<wwnaVyMdDKKvI^#}_|u6I?eX
zCe6AxS4+t+{E?0O|HNo|JfBNfOHWSDpmY1|@Gxtr<jPjQH%966QeJ>sZMFSJ<ji^8
z7@2$w+n@97`8+<JXJ81zj4xRdC=+uP#r3)^dEQ&2s5tyW5CZ}={Xs#yWO0(D2$2e@
z1UVSy3#T#zmJYF#03)60Yc*Tu+rwNX5A4c^(Bb5W9*k+*L+Irs;^m!n^vS%A{715c
zI>gtj%|zwD=U;`>L5lQIy2V*kCgxCF(SYfyaEuZ5B7B|ry7y*VNKTKjjvMC-_;eu~
zId?cn{49Vo>5TeSnxxU;YTp<g0Vja7m}JOoIWX2FVEc&SH=&Z5W^8hG;PxgZwZgCy
z<CdBC9nf7}cP4DCC|QS%H0i@)ZJFm>dm*$%o=+uFX?wW>*H3s=4pwKZO?n~r$0@E)
z#*mEBu);gO;1Di>CISH(=4IG3=4$EZtCD!ZkegEl;L}To%B;kfDyRw?q$Kx&qSXZ>
zAY22tB3H%nm~SJjUAgV@+S1STFQ;3nO@UeF22c)4h>ph3bzwo2!jtq)YAG>|umOEr
z>nfpSn{h0mttvVmWx$*s4NOjeyy5gQ%DUe7#cD}h3l!5JL@Y1{1Vp}rET}Stz)K^V
zGyeJ5O}VS9RimmSrM!lHh+HmFe<RYN3RmcXITPed_8^3t@p&;aqmssch_9~XJ0KKK
zg4jX`4*6#rBP~Gbb19cDWqD)h7WT0G%7DBfzd4?IP8M+}$QhC^Q<3^a+s73FGB`NE
zry#^Pueie+R~cgcR(S(mW#KUk4nw=G9px!y%cr>P$pFbqwmtwhAFx&9ag3G4bn-bx
zJeO9uSf$`p=+iubJi6$MCDkudsVREd9XD>7W4G04?}0e!)uxT33vOx|3Opm!F^vSx
zZ$!yXPq~>>li?_yt?VPQ@^1{^&b~W#pOvs->;E<?jUfI^b*!WKKJ4h1-d5NtO(fWu
zErb#7zbv2WROswnim$%V0g<)*T?p?kqazDSi_0`xhxh^Q)<}24w>X>pWbSWb<FRBr
zz|$OxR`FT8p4B)qK4N~VpvQ}if}{q7@=e9W(EUe(b=WaoyC#35;+?p{-)2AOSO~-s
zmi$cf@qG+w!0>71rpp{oANzh?1C;>%M&PI;sFcN+Eq<2U38n&H>Fy3`xAi7k^yl8$
z?Ap(1O4}bw|7X)jxsnM6KFKp3V+3UtmBE+0&^rlhPySy2q=d1@=^eMAFg?6VMtiR-
zV47Y&{x&0%d;+5S5#I8*nLWGo$rh^S5pFlZcjDWyq0LLkCOt^FeLz?4%v$!3GHpdI
zJ$-!mC?Xp}Ck-4Rwbj@C6V@Y{?BCLb!pH=23(Y_8`tfEM|Ikbx^L#ILt=VBMK$O7Z
zFw6k(92Igkm<vC7eqrDEe_{;O)_nHuthAuEGNxS2WiMaMKczIeH@UE2=StZk(swwn
zj&%G2#X75~zcI0FC%!dl$1d7It8`}n>QBaw4lP}pCAIZV>iUk0GLt^m7w(^6XW@Cv
z;>A-^TUBM$g}?4LhuZp(w_iWsxJlR{<^h1%zSbY>k4&XMs+NT1Qg<U=PkE8yLR;JV
z!uS@FEu_dswN<L!;#xX$8>`j;MEUmMMJf}i=V+&G?RP2{swHHtQ_iw_yX)s!H2iz2
z%MMgi3edbU2mT*^K9gqa!}5H-JnklYyRB@q4FLa^uKd`4bmp(-mu%kkqj3a_D*5bH
zv-ZMebRf2CY`XKm581U8VDa<~Ol|My>h6PYraF8lr;M376?f+n2>VI@%-nlFWJ{je
zl#N_u&3FING;^CBsDr<h#XGPc`Jwyc=Y_)F9xCCcYnuP{?+ZD0lHOlxllSqp#+A3d
zY1;f3v#@<S>!F48M{)t&lYC>JdL8z)%s1i@4iPC~K7KY4k?yjNNo~bvg8f%FL&@vh
ztfo%`z;(>K*WeND^ih@xMPJ#-;(qPd&$-3?MJ}hi%f_1%#qL(wwR`<=KI2CV2O3qj
z>77l|j3GA|MWT&A{u_)Q8n^G#0K3=4s(+UPcC)u|Zs_J+wUfg!AZXWj!fwyzh88cI
z$--MBHj5QE=Z+*SfBd4N=>B`>>~kaekURegqX!BI(|+XeFgYRJ;p4wDz(kn+yIQzi
zok<?rFG<(nCKpo{oA!utD!KOWX9f^f6Oya~8iXKS1(YV})5+^)@8D7GuBJ>RX+dQq
z$2M;-5)!aO05Mh&Hqm7k%)(rxE46hgXC$4@Y!-FBm5JEDlG;jK*<+=~><gOk9JQ$`
z29)BtmQcr&yh!iWOcaB4lW&lrPvrC;9rEZw)4X*ua^XEi!=+B8Q&{GB3A|q7u`i6W
zu0ehxUaohQD<7a6GV@Pgflj7?O;cETYy}~&=hIk()KRLmB&sS2;!%NL4eUS4G2`-J
zk8o-0(kfgRbv;1sI1A9o0l0FQ=2A)RkbEW>x=K1}BS4UeEAqJnX9caS2XxPcuUtbt
z-z_XIblL<>SsNWKlACw90}rZ854>!vQ4WYxifp=B&1$u^G>3NtH%5;2D;HV3&LLwc
zx^)5>K22yj9Q=cqo1d=RNEPQyM(>*DNLKPs1%c^#RD0gYr?Xcu((8-ye;_FLZ{u-1
z6dCE(qAYQEgq`1rrS|lR8Oqk-I}nIBzsqijB-CaDPsQ-G8?`yt!NVHf^NuV8B9u~u
zv^Zr@oW@8{lds)dm{}}US4LXkI3A@XP*(KAML-AzrL(9N`ZXRf(#BwqzdLJ2IS0%=
zRn2K}qXg=aOzomd7?dIqv^^*?@KiFG@TM%wsdOA|%gtdaaZCFD4WN>BFQrzzeJJkb
zMsfE7uy~jV8$GtQFPTS_m9*-1K8{zH0OdjusGtr)qa%yBmU7E<w#}YQboS&kI3gcD
zzHw~{c?<~^K6?eY>)at&#plCUFF%)qmPn*nxR@ALWfdK~m@~@iS;NfXu0i+M%)0pS
zB-9DD<$%xj&}u7udIM5X+37S-7EiRF$?WDw9z(}MZ9NNMo2CY`(Xy}bUdwE;)U5rU
z$&k0tt1upAwyq69ZvQ3U57RH6j)Gv3{~AU;B5jaEo#rb{f36T;cn`&N&rnCxg;-&~
zLb^-yklu$>n7y@*|DYACA#_4fbhG*Po(cOzs@cuvH{7VVp>@8Cb?Yn0)gD5bvww1f
zX~Q7c-zR^ro9af}XZQ(jw>!77)m?1K?(?^0yA`rT;8$ote{=5?S{U<z!-?D5{IA(q
z{!MC{oA4H<Caw4)d$pw$g`0Q;{#RD(YLq;-c)RG2DC1Ukn6A*MVLHiKjy78Cwyv1_
zy(*xOQ8*BMoLocRo5`&`O>`adkhVR+(1BN#*Z!BRc&NQYKIas!(t|YL@?A6)BC*}5
z6#9WXJ!VHIS=NzybTdbgDXnfKd+Sghj=aUANi}W$u|_D^ZDrrLnJHzz>qAB6NIYY=
zm5)YfK{&)&Kmz^1?Nk>2^Z#VIeoQAE{XVhUuJ?^?@r^XC4(0ug7tR^8#-;qm5c+wT
z9WO?U>vQY;{Sah{(Y(8eWc@|on`c*lelC0B5!9dC-s<hzXR{ocdAo&P$b&j^<6dhI
zz*)?KW4G1VxX%3L4E;6y#0PTMVcwpLcfN=Wb-;FJ9DpOHvZ$l4fFC)ZTJj>YDtGu?
z0Zvn83O~E}1DWr9_cdA6aF>p}o})FCi&rGd_}v5L0AzJ^R({~pteI+1Bx_<^WXrh=
zTC9j<91^BBEv4O7K4qh41Z5<07I$0kgtG>5WAv1U65kp!K1bbOPFndm<N0&%jl;CN
zEA!!rkz(TM%d*U$U^(Z+vsrgJR`s8@6JDEQ2j9&3v%iLyk{bQ!W5!gC;=SSfxgUhD
zAv^zWkGG5XqImze3-@@rBRCET$9YD$eWYmlt@&9G5%*D)YxG?8A>l9@yuZD*u=Ld%
z{Z$}Lbly0b50KBWo~~@!J<;7d{5{h%akq7CV;XdodHJR?=-UiBPkzhd&<@vAWLur#
z82Kz-<Bc{4M2Jw4r5<_69<?turmcGk^=Z*2E$6q{TTgYH5UnUkp=Rztf9F{1s|c$0
z4FpcL;0rYN!<RT!BnFS!=5z0}?qR;i8~TRs$@vzolH8{4&u`uaA4A^4?@~Y#NOweC
zg=!#68va*Yu-_aCjq<!%7Y>efh2jqnN98Q!GqmG@Ig4uor_J%xJR*?Wdku%#yJ01Q
z*zF|iS-pd+&{akmN{9K%136+_w9Xi5Pti%lUN4HM#%MJI);+azJG07ZKBcKUX}Jnn
z4rCj1<NQ))8Sc?p*qFjHsnCF<*`;T}CwPTN@US%iT<k$oPVVJ#R(E!FWSQznvOiB)
zqLy|AX`jJhTeJ2G*jbw7h%?h7<N7|-);aT}X?sGAL4+ADY3Vt)wm>+d(H19bEG8b-
z4dfpWuX}<0A~uG`vjx%-@BxVxFw3NLLn8VS`+)D!(I6zC&0(Uz_hA!qxayI;FCZVK
zKH`y~S0n6HQB<4QJsX;T8iC}6r`h0B)z+m_SkVj9%fS#K3<@JA8LeBrN*J~k*w#T|
znv_Zjp$&%s^Wk%H;8QpzUl}XRAqOoAHSdTTYAc-CLWySuQAo0T$4f)R*ezIEC9f{e
z1O%TZivvLjS;bOk6TY~NX{apbHwA6scrE^lwWx6AVO%b3OC+Rv>9d^dk*FGO*YTo9
zGED9y@yZCmM1~@;%rluMQuLGm*6`X2(Oa(lN>`PMQc!d7>8NK84>No~)t!YzP6$Nu
zSeHj!5D#LM9Z*>IvAE>34XnbNSGdxm>_iOU<6?ZgtO`)u!-wpsy^=PEi+IVm$>Rf9
zy56mcZ@?p=D2Vw8C~y{nlG>wt@pLiP(O4z~ZV9V|1cl};9U=FStLrY6p0xOOg1L=~
zLRkHv+*@(xy*VLgiGxL~jG(D79Z6c|9J55Dm<bwjq%O-$2>3ATqC1i(iZIZEL?qiw
zov3uW0&P+UiAFW1D-r~_C`>{jlIq`bB!#1EMLdoXQDU&rwuBc_!OX&WbEJ%A7b9gI
zPCA-1ubArUY=~v;rvpA24R^!|byy<R_d;-l!!mqh5oB~|Y5*-NT*z0ER>(kM-kRY%
z6W>_21vs0b9WsGdF2_hqaTAm%tHx<Mw5q@dhN1G_&L|B;5cE~bnh<yBB^H$emV&=E
z0tv`$KOR2S9&9_vPLjB1c@~euiiSRdwGWi0)Rp#hN?pwyI82SK0!&2H$hse*rLrj^
zs&<jc#aLWIvZgre5C1q7s~6@)q(oY!?B_yV^dk}V9R{^gd?r0oZsfFJewU^Uh+~-C
zwL4jRi4%ZX^MK8}GVfSpB-q3W)P_Jc9G-?tpN(h6d}{Q7`HuC4*IRMGtmAVOVx}g{
z9PaNMXFCM=uYf@#0X0$J^-{@7kR^{Ppe>6c#bS_;<B2|_m>oG3sShNwn^Lc8Lq{>|
zfFMW3kE{t?Z8=->d|JW=5W_Xpc?<H0d8<RVGB+hvF`sY;ioQ8nb>BeHYg1bC2t86g
zi@eVY3iMDSxZLxO6x4ESAP7fQtRmv#8lq3((HKkiLEn&Y5jPXruB=MF1#O=@IR#an
zYc`=793DYPf=+y&%}aEAZ|V`Yh+0c9iU1s^XtO*~8{HI%*@roN^h8iYh!7L0Q>s1B
zWQvMYfT##udIuRTxwLl2*;Ml?fWAPxa1>vd1GADVh9*AEIE`Yqw1<%{ST~0>T?}_P
zxt!_gl8zZ^P;A?AADHV9JmS0}4Umrph|XAUqre!gvM%TI6IlY_Kjei1O68%+$NElv
zMjjoSP@U3XuGx~};wzd?#`e%AEg>o`qQk$75kfsTP<aGNgqJ2N5-3)oHnDnH`NY)P
zj1B>p&G9%M{F|DJXhKEQf*qep93DrJ5U_0nZNdtuJK?B;7wSrKgyKn>ao1eOqiE&$
z5_*;pD*R{ao$z>E6i+3WXfnwsUn<`SVN;(=F%1eZON}U&NB{_t`)DQL&Nt$71dFB}
zZ5O>$|4)`q1l*AyOd9ps<PvcsHFfdqorPr;88C`5pK>Q>j(3=pjXuk*fO;O)=a>p8
zflotz^uQi9AS+5NI3hbR-(qJ6=#UeceL?BWC(g{5X~Rr~9hBhBSt$HDCbiXVP&oT0
z`U-^U<kPTWzbT9fV^yV-_jq(E!&Qt;*jqak4cO^;d7hqntN`W2@gQM~a-$lxXUO8c
zPCW#kdTGpQuV`i(L6Q1_5_dwRYf#O&Dv}bxm|)_hXwy>S92_QGPzW-27{1F((DaHO
zBenQ$GZ5~1gqO*TxpU?xyF>PAVfF<FN2_&-Jsnd|ytP{8IrgaEK?V8kk<Vpp<oLdc
zy&Pez_E>pavW5TJ+Q|`)su1qM^U!N7FF&&6VFUOHZ&u!5T4P(m8F&VRm}2;^Na5Jd
z)!~(eI#!u1*Etu-9@6i9-7~~hDHES!dP#{q2Lc~5C$x+@)=t)e-YFl*=_)p+_|?Z*
zlK?x)%eP$Cyb+gUX*hQyUg@!bbb*^Je=T%_&LrRVeewiu%bbh|trq3jI%Hklx-dTf
zW;{8fXwxd)AMobCIuZ*yA#eG1DWp_$-AB|1*D?7?gsgb$Ex`_)VnuqikxF|#{EW7R
zAa81<&L29LSy1hK{H3L^q<~#lGDYAdnu$xU5#^UOb}!l|nYcCaaWj8qdEEYZ^5T|0
z$8QDDgxVK^Fg|^4u7iq!Ee{DNR&oV+R{!GxIGcR^T)dKF(OCZ8v*_9<P7h~c79Pc>
z)0d<d9&$m|Tm{q*9Q8uq`DOmWcSG)_#OfQbY}&;?WB#V62)*KGgW3P`>A<o8<JrID
zGM(oxZH~6WlrQZysjqNsdwNAxYESvbkTs4u)`y#6_1d?)FX{J4+A5cS#tzT}@5Is{
zTuh6v1{u4lJQFvqN16P_7~7v;Ow|1Q4_RtZ>j-DGdHM1UT2H2Ok5qdyF@PrA)LFVb
zN>XL4&AKk~v0Yzou5xCuH54=XF`J(yvh4l9)52|U+|_&DLb!EkS}_n)i(5lO20#8S
zr>3p+7jV~<%b1>JtP!C7!&zXDFjzj$9dVqD42meu1_19yFQ;+d%A92A2U!ICr?DaF
z&}9*~kv`;^DO^I;=CE!Vb9<VpkPa$oXQgw3wxr6VAI@N?wUsaY?oe^}B0GeyeZ!=`
z=r4jD{34^4a&?Rr8$g-)LYwy>@P{AwS!_VsH#+%nFG`+&IA0jwd&GV(dVRGQu&pJ;
z&`_;HRH%-P1YZZx2u(d=6?PYOsohAq&bpWQaW-EPE|KDA1{LD=Ml6Wf`(2}3y*2NP
z(9*FxeR;OPZC{77-+2wvbItd7JA&eMV4;A>wV;Ia3J2bGgH@uKvR<A>Z}wAjj3w;m
zmG5(2zT|B}+eqb`aD<%K`{garuoG7$_F3oN<3nli(+_6|_Mk5W`_{-}>k3)^1vB_(
zZ=m>TPUVFX8#CqZ@nngv?OuWPaUE2Q`$lV83rP?#4xO9olX)B~Jc9w#_rxgZAx3fW
z9ba`wsJt>fv<e#~;GC!1_9@6E<E-8+$r-INKU(F(lYyWV^z{P}9F>a4vT3#$LPiav
zg5|8l?AI_*5OUTKI_iwG#a_fB%+OiQ;4YXv!41cyNE}K*SF5#FM22h+E%c(uLg&#U
z`)cx6NlK1~>1uVgCM@bRp+)%)0#4<><TZ$EDY6H7)S_Z($DZ1Wvq2!;3Rht|7z~+D
zt_~w>ExFjB)Eq;*LR~2(3Vej^1390-BIyhUAExT9Fibi2`MNM0g$B9&4zfnOnq`M!
z$t!u<*jzy9+EFPAP>3R_uTP+b(ib4mdQkccg+?kF)4>RVIe|-7rD-Z7S>mumZiBH&
zMTyTUP@Kga2S%s7Ic%AazUKIRI|d{adHUY<zX@f_H>1i12qI1{1)6lM!jPySUT;pm
z{h+5GY(y+82j`|p5Ku*m;2I?#U)SeL4&vv@<P{3@dI3G$<lN@nrW=dEC8bR)%8VeF
zBm?=FPh!^wK!V~~kr7W#R*yw<9GOR`QIczmcZbFA$f=He2L58KAg`_%55~;QGWm9R
za3!Xmj+d*1DsTF24FP4weQVab343A4J5a^1RtRcq%uK<^u_wr9TWGeXH-;~iwvyZ~
z8jrwPewcnByob+3rZ%E(XZJ4;tVg<{VK)Y4VO|(w)KP3lS!#D!A~=aakB|AlvWdfp
zv-NALqp;tzAj9h=Xd+FA5kI)az04EU)+GfNyaeLQ=5RS#diM=Q$2PBQhF`xP0wI&y
z8WRc42HkFzj?H<`@{j^bB?E!_3rRP56c1$FgW+XIeelVxkEy+Py})EqLjN!bW*2yC
zK9>6?YU_->H0}(wb>IX8Iou4VlXJoT;xo?H#{4?Mq1{dMzgs7L7kKT46ZS)PdKo?M
zax_sn2Z8X>R4a4lT~(ykwSg-(Oy>_58a7hiVzY?2GvOz8{(5T;i9R|sJ<f#c^ON=|
zw!El+i-S<AaI)-=N#a{Oxm{$`uMTsV&dk{h=b-z3H+ypLjd{Si*tM0vCEy-dI%z83
z)kS-p4*B%kV;#29+X#tp4}qOa?I}A%VLwa9x43UA&f}8WDxBM<!08JvrN|vS;~eGe
zMzyuI!1%;;>E^~*<E^7^0kw7Ze$>`M(z76v)X1)rrQ)~sqKg5oUEgPU{6Rkjs7<bQ
z-@%UD^*((A(ERBv(}~0pk&4I0_-t+tdtV5`*!4H7&S5Se`B{$<+d*|-j7=PVaW?mN
z>~hvD=jjTdkTd&u>)-4wS2>wi6w~nBnta4w3tQrB5GX#yUApBJbC#pF7D;Ule)fAu
z?8A4srhf_n3?F8B@`+t;X7pnne$0^uxVOz9{B;+?-(8xz3aPD8QWLkfo?Pp4ciN6;
zUEY4)igND`<A`FG)K<yt*q`=<x*db$l3+xc^GTcAptiR7aO-^3)+L+!!Y6#@xulfB
z>I;Pz3Nm9S+}JPNq2bP7a`&WYFbR-8`#b^qN3{#FjNkY#xD*}Kbn3KHWCN<5*U|*I
z{b7~_JEXp>%5c;Yt1)Y9jj;H`?`w_nJzcB(k3U>Yi)<G$>Hujj{ZYR}nUAz~hTE2y
zs{RCZDn;*4HNV?gs~eE_f8n%2^G9QKSbEPTHdXwkW$r_H-ul{ZhIJj6Rhr~B3^i^+
zIzNq6zK(B{)T!6HAYyl3jtc*m@IZp$!dq?j9gke;a&px?_WgMjrdKKhaaWN`YXT=P
zSCs%%DDPtNYVUt%dznVq5VyUY4Fn-KZ7mBhZvN+RpTrV&*xTawYuGbXyH(wPH9mEo
zc~J2~*+bV_)IsooMj5n#HV8P7f>P%*Wk!u`Ot}(pNiuK$UOFOl(vj8<e-lJn-XD2q
zHq~SyYoDzYpcDb!I<q5Y{I2Gp5a?|ADqucq6ese|`05X&h}VwI4|Cc)JozR&wdaLK
z&a!^yQmXezuvl3eZ4P~hS{2#8B6Be&xwic93Yh@>zX0`5=0Z-cE-Wv!JV{6q27uv+
zgK*=S`n6GrhKzKB$IP_I53RWVZV7dOG;0)Uf(lij531DM^#xK0%Gu_g&Zz`u@WqlO
zFe$6qWFU8afs}i|iqGa69jK*hN7`}?O=p2W`_wl^Y1Pb(CEA@&583{O&*4b4dujEt
zh+(mJxDrvU`YZ^FT4Y}caV1h75o%7olW;bYQ$h~4dscWt(-W8`m`04~!WayEh1P1b
zsueR|$6L-VpC+~9C_YZUky%;J0^(Li$T$z89CR$iQd<<CO!K6qD%H!=8IdQ^Gz;wr
z0t-&rR?aA-!JwnGlb|G`)hbrAeFp_-)XrE#lw?Rj#gsTpF)Cy+b~bRVAiV{jq~4A(
z`M5G>VOlQ6G8>y9I3_%7jIHJh(bVmfvoQiXW+2#?(Zz&a^^a!Od>xrD?yy2?60_Lo
z%dXufh6y+mROFxzFt$W!c{NpAWtbUvi!jG1K-V|`_?P22JW7=iS!-PlXTOI{P)5oP
zZ#&s-O*Mv$l51m`NpDQe`dqXQ@@f+UJUzY7wIxo{JWAGlP!*c4Xe3G{-{gq5YjbLW
zw$T?-^cqP?Z42{+vO$2_x~HrVN3G#KY{#sa-N2#IDkRI@a%;kd1B;9ARNn<<&=9)k
ziFUnT%ahm!B?*M;8Z948^+#CSf{)4;m4Q!;B>$jQ9X_>F+iaVsbX^0XG|kN=%3z%p
zh;wQflWX&EImtt^>kwKqX0CSM7cFt2zxL{d)gIfKt0KqKI$U8L!knZPQ@kq*5G;4K
z+se_K08`>8GC=1<1EB;`aa<Ptw|RvPVOL>yau4fel41gfarFvQzhB2f!Y-mE3g%b$
zC#>`qce6uO0@VV9awpZnPtK-5^?GHu$6fN=;vFIb-YaX<!eI%Fw@xIJ-xpprdE9f)
z!_Z53qP8x|cTnioh~m+{GZw7%Pu*1aqhxEX?kVp=kgGpXl<c+!er<zneZ1>>x4m#h
zi68W9jZ#EV@LV)H;TB~>;4Qq}oO^6}+J5JpeAspuQ(g<e?6&5uMOGsIB+DBe#sCga
z@Uw}I!J;ae7`@-CyeFu`oSQ30?F4$ZO2c=CJ-Y0q<+~br9!A1Z3kO0VcZ+s#hh^m@
zwzQnN%>21=D7JbkWcFe9KEJt#HJe$goToGvFV2H~g|*n}EV!p{ft_-Q!Epfack<0w
zN$cbW*syW8wKI$7TSr5F;M7XcZfh;7trIP5F&N_nm{U$@nc-#;{Zu{@Zr)+T!!Ir5
zmz^FH$J8Ds`D-sUynT|3Z}gFs&3r9$y6xpoagH7|f1-UstQJaSYk*u(D4L6Rvb=3y
zOQsqHDpn|`xsIZ}_G$*1-5l$jE1Z{<rMB*W;RZV<^<#X>S{<=<4!ItHCdEhFT=>|K
zoy@tK;K6sdGO1QT^Y^c^8FpJ|{e4-mk(aC)zRkX)((D}H(>mvmE@44GG^{*$fi++q
zt!J!^0-5;f*78F8i0!>`HH@zwpS1FW7c?Kz4j;R%!DT<{?4SRvNb~`3&Q=b=;o95D
z<@Z@@!)|M9>RIi!W;U-{vT&E{U#ybVEF`s<uoIc8j6HV06XnpufA;IFwkY>qupD1G
zcKDudb@^+T=95C58oJ)z=?IFMRH^H>m%b20LRctxI~V`Du>01yGXnxhvXJ82WW(~2
z1AjYYPqvF-h2z2$PXTH`M{RZQA!>oz+T>2Y#iKtllDe!RrMMl;K=9}%IJfd$D(^=w
zn&J1NnOC#__r+mW6aUg>?pY{2v8(&Q*H(v_9Ye(Fn8QzA(sT=VO<ISoRD*SPTbcf1
z+5;bM*^l4<>e8-3|6cg>NxS108Y@y;4YhU8O1Z<_7bZ!eAHZ2Gthgqi=7QQ<N6YP}
zwA=cs&y9EJmiTOLwO?uqcV|Z0m%Q7zjb{36Zd%Tp>9_*>k70c3%`tnFjnq~EdDG7H
z-Q{W728E!B-Ek(>-_10X3+NenlY>z^$hRUF=5|hVs`<{i+nT>;B}Z*7A|gCp;qoKa
zJPWneo4?eB{Nwaa9sLl~&57uNp<-?gojd<ONqO}GX10IXh>J7I5(h<wt?O?O!Pa+M
z69=yQ4idO*#4d6_l!wJjEX)1?wO_eHZKW4DmrdA_Rze==eUEjrlFGBjTr`1`QE)mv
zU&OK?S0yP~w*|i`6gIr3^a8dYme60gxr|by4s@Fs9q0^Qu3(@?!$;@Yyd20G^NLm&
zvZE6WT~*}CQ&{E$)R(ceUdLzSjCM;@>7&e2yZA*|Rb9$^^ef+OjX)X^PLPEh+kA>X
z66EXAk;#v~62YP1C4#5Pwmcldusf5DcOjd(c^#o%#x~C*h9+4Iav@;jeh@CS1`udp
zD22hkSW=8*v^q{6nv>Ywy*xL;P=D|VC9${xy=LT42f-C2CB`EyHWypVZCo`<jKy*z
zW1=y2jeS@2+vep{n3F-ODXE%am<b&MT*C#Xf}h0di;&0{a}U&Lc%LosiO?GPA)2z{
zc-mFz<WnBkI6)3Gz|l~Y2~#!)lG!gow$r4{1fJ#;FyXrya&&7)yyU^!&|HT^$3TG+
zv20;e8R2mTh{W)xmv!P!)u{%bSqKnC)ec%p2%98dW4+vrNWD~g7SNP`?Y6FB*8V<&
z-%;k>K_%%sWba7B9gUpdhR*<50IP;Ji=3q#qaj9A?$n4}8v;*cP8?_fC}qTh)5Rn3
z2$I^0MIsy=BqJrvk)sre)HTFf?s@SU+$@F-P2<OQo$S^qpI{bq1MGF-%=myh$z#+O
zRuOt+Q+N+j4N^ZDviNzAxlz-OL|+Kz>*@`zD-mSMv<~mKTUUtP5kh_hcmMQ=8hNT2
zbHo(j_A;58-&d!vjrj!BADdP=1TMkySDCYzOJ1(R=wm>(lTgOAdac3=$(<_3Q_ydz
zFXNZ<x`;5Tt)CXA@+N9;5tHnboJ~E7TpAs5Jlzsz6_=tSuYuPnYoV=~PMUsM(}5in
z17^dBK0>@1M-Rky1O@w)vYBJ>!b1?^o8(7>l&I|?3!B27#E%Rh?ops#<%j(zL#KFY
z)L#9}q}9YWMcL$tQIn6`7?7V1Ft#HvI3zsQT+66?73A$k(6q(N?d`88t$6%CL?SpH
zR%J};wJp?S!$I!XSexbRus@0IP?1`l%U#;Ad~d_<Xio2;)ij#pQ!Sd*j}d;7F`+Zu
zVwgX2ILjtm!?oJlw}463>=P{XkF-Nr{3S;2Yf{T>-V)4z6xFzB?(vI%roQm?!Uay!
zYyv+)m+2?9g9ZdmjkVi)+R;pJ{Uqmu&#5Rsmw(2}>sPtQ6x`_~e3mDcV?x`$oI<~a
zj5)rH+S>eFR9ijkXSfgfBhBVpk?^}u*=_u`hPt!<5QIXd%AG8UnY3|Q?g+N)e?*}@
zjjsY=-`{c!%`GRR^7-^thr+2BPUQN2g#tkj3YY^yS6Kh%x{z)aX^c41ixoX?i49$!
zcMd<w??nD4-OtRzyz^|FL6*hB=OGez&77J%^Q>PgUbZx^l(&NYKhL62G2Ch$eAAqL
z_F)~2GJE)a_RGz?y!V_N^^NnF+IHpcaphLKt!97tV=a5|BxK9oHqIrbduFuT`ZLYk
z4&2Ee;Uibtu(E&ZG_${hud${syNQQ{!J2#cCF%s??F(1^jJMgfMm8e#D5<Solgc+u
zMUvWTpZZC&Ti!oDP_Z_>2*y&ui~_^dp62>)s{(kkbU6<Mq*=-5S`_a^e%hpLLs^Rz
zEKQ^_fWYlRi28j+RR+H@`C|+8YDGMoOu$|Ox)a~dbT-*W#@m@=c{E6Eok7@vxGv+6
z@W^7INPm39xIQ*ky6s6S^xBWok^jJK+S4SL^zgRylW&6dUp8-zYU^KokW&sFmg;_k
z8g)50EQLqD%z$|p73k|bv|P!DuBVu?l9&@&$HUFMQD(v8kTNc{)s_|VTkSdd^#yWb
zPHO8+rMA{F0y<V_VsB%@IhE~K3ookMLP_nf5z@%Xd0C)IFB^ATom4P^dfBW*ZPjjT
zTH=y7YU_CPksbPv4y3k1R{E{m8B@Owa$Qo_zwTu|Z5GLP51!-L_VhVb_6pxRvWFSW
z#H&Rp5-A*(7L%*1GfmY8fQ!L#H_wgQ52L4OqZD#&W(mas#IUx{9*Sz~<I3?Dcg#1s
zH~SG7bj=5M<fH!f5f)Svk+GoGT7%MQl_@o4!WzmIYHP$f*xi>bHToG%ICBKJcqUnC
zt&IlS6<!Dm%L?Lm=OdO|<l4(?TX3%ot*Sy0og5X6R}C~2XBl-WdS!U)5#<>fMdD*9
ztjCb|8Nl`Y0<lb&!i9iei}cAr=J}v7(0b!gO~>dU5tcwW8Y9N^Cv;ml{;4*~-zRP&
z${Al3U*5uGQBapO>j^x3z+YTj#qf-vDdP^ZLpb~pJQc==IkhaDaODF7H84U@BVBU(
z^~NF;Q2PL!i8)l@R=`}J$>4B=AfO_D#5_)64G7a4@sxgvgv3x!P^25T`TP_!cw`cy
z9%4^2hh$D)bQBy!v40kXivEBcW`4pD8Z@S$BpG*=yMn7hL^o>$8&ek8dQ+<WJVGKW
z8Zm2*Dz;v#p!9_W7P}=lr_~k4yhX(rRnO{W!x9{Cro_RX5*3tmn`SUx5=W|WLi2DI
zWQkm0?uknhg!Rh#AT3U+psg~4jM|g%w}BAD5H8&h6(rKB$PogevEZ@5Hg)Z+0nUAu
zq~c09T?bcNBln`P0fw?tE*PsbyCLulRuEMQ15ElVI0<E#?c6r94DyA@w9HwFNWfRO
z_yKwcv5KYXG5doP!I%~$7a_8$M7*40X)|;vLO)?gtv6V4TM-<)b;&pjS{+J7054$=
z>4keU*yJEMVSxpleo#2;2nW6vWtJ=z$`pv_Ri=|iS?tlFiKdh9wh*=sbz25)h}5GE
zGFh_7oWwK$bXM*sx`WRwN_Rbqb}xsNMIWmb>9IzDD<wRhh}2ZNgb=zXSN6AuGz7bI
z!LJ&*i%b(M&}Eb}j4xQ@m56mp@z}X&5mLbl)0(Wx`S4Dcm`h<WuHLw=**@T1tXA>1
zG1d>aN2KYEsAMkWi=VV>?tN**W=^r4zcKWT_OQ|SSk_#$H^A8$Ao+4y3nGB@$5O-h
zJ)ReIy)>Sa{5n!R;v4<8c}XUVzi6MzzJgf)bmy$x^ID!cNfke}i@E7@4A*O!(_Qa6
zts9!mBShNiex?N1vG26@HsjPB3wUe-^#uopM4sQhqryEE%@I<t^7~qOnj$P$ff%jk
zahB@+pIUdw`RMJvtso0Na{{vL<1V8$7M{uCgxVz6PtwPK1&ry8iOwZ9Lf(RKw}m)J
z-;<r%o91zuliI4fB$(rI*U<7OPUS_|Rd-u4Z0lE0kc86v0uQ?+7<f{EEF#kU8@8Y2
zkp8IeQIj5ohr90{AND+Nwp`XC6W%ruEd8p3cZ*rP^NR9oww@2&a_Q2^$sc&@6#DEE
zL|*S9QlQX%((;@Z`{nO6iese9FG4h>@_H#-!xulpHt9ChVo(?E5qPKbWkf?-_Qq4O
zVR~s4FT9V$wLN*?TUM&vk}dzGeA4YXf5r~4H1a@{P^{UBE?)*oAjQmc8U5uRyZOoY
zx+t?>ee-MZzMh`*L31lhBjc^df3_1O&21qdXI;gLO34bqrIg@Ji9^M5^E<PphbL$3
zmXA|yIOD1Mvpq;q!cZn-QQrFoIn$X~nU!MME8|w&5L6ilo-9@eD2M;>`n+}V2WCC`
zbbt9m&MgMXR%&aNR!Nd<^0vrY(6_C2-i!FCmawJk9axg2?YsMJ^AK@8mLE~bt}9YL
zWZx1Tomph~?@09j_(hwUxI23i?4TGAP#*3e%g_JeB25T^i28Xhpq->KkCv8uJZ+e-
zHrhA>@xr)EoP{O2$BB2*gME1_cEU}4+gf_&g`+cI_5%k3<ot<0&4%(jc7^c`-?m!g
zpEefry=+0Z9x6KFt2g#bjC3TZP4LuCk`HN@5iVIj3~3>+!s2WH4fu6*Z!;{ml^>yY
zoZb+;l@+qNeRBsl$Rb~$-9y~R%<&`z83X8LV@Iq*!Zn8TKgSuD)38{9kLKF-lRcC=
z<Q1mo+JLu@Plx=a^RSM4c|<6wj^zU5z@a)*(fjtJ^gutxZ*AZ21G!_!AIs=gCxb#K
zyWmI2_p`wC%fq4mIuy0lN%^I7SV$dQ!rS6qadr`OkOs>%YonX8<LHUpyUoq4zys5#
zzVOO|Evh(e%$Sq$wDX8kfJd5j5Cp>;fNO519C$k+xrw0-I4`$qiz1~Gsvx;e$j(eD
zDm>9D-Em&N0%t7T5{j9ik_g_l&z7dt72tdxbYV{WButkK@2i}L(34xpC@6mHf_)R8
zuqHT($}m^wKKXW-Lxo$B$%@&l<1DYjPNVg7in`4^q_9I6BvB_`MaZN4iz48TiC6yH
z89GC_3F<=em2X%NRglUq`Y7v;C-AT&hm^V*c|SK)!inBnza|(;!@;TwR4R*+rali{
zn!l5XjyZiD-`5t1XpV0v1RH_%kfMLF5+|kTvo0$eq;o=9@;tyqh=y3GWgw3hYbAv`
z(oe<U4t*hPwics{Jjg8Cae#1L<-p0uGr}-qZN3xKw-u$lwu7Xg>5kS}?OUXU>h%bb
z>&O(gvFKV4JcG@x`<2l;8tTr>uLo^yQ!WC*I``;K=|{<8d)PWc3UL^$VbJ-;CGsfk
zs)~97T4VeIOK}vL^_t>_6v<vyf~y;Rm1IB2nd?UANHR;C&^xdLG+(AYP*XW191Bf{
z-19w@u`;b2<~cS)<rpH=tBWd?4H9vL`=u<FLaZQF&cNFehFuI&)fBl<ZfLRXm`FIM
zD->o`bte;J4Ezc;Cfu#VndF;7!whW5>R260UW2_mK}X#+yWIpLE6Ii0HzKra7bfkz
z0^vrXF;>go2YL~M5VM!X@c6wl1Fcnue*{r-#Dlv9?-`G9=W3|%5Mot}ym&Fp6CJA*
zyvN-KHqdoKg*Bxfp|$!dw80&oYtI4H*8UJlS7_1RotUnif!}s0KFm)^L{MUjc9)G|
zhUk-C_rx4{_KnauzBzf6NWpCgKeJV&P+KSLV5e!vw6ykyD4vLY_y?V{Z)QGQ8)AdC
zg1qGOzzAOs+HH+ebUWA7?*rM#tJV=wws?iw|F6!;gI(N;)A-uYUdN{37s#e2YZWQN
z{E}n(2tz2;SKjkIxs^XZNhiHPP~p5S9}U=maeP*WiZloO3WLgYW>=P@4z%SBWfpN?
z`3gF=e^(xcnYU@S>Ng$|p8Ne9no?U+qa8?XRW{(=3P?@yge%eDa?9alg|8d~Dp-~~
zVSw4wda_)TS9~~inkF8dColG&d-h4@4CM|6h<*^s^1Had{RwMbelmMH?(-2z0(fd^
zmldDBc1~)mpA}hVf&S(-CisvYz2;=5&BOSaP;-jk<<LlH7v6f4!`L2LcFL=s`2T!P
zdu;e)j8YZ8QdoJHIseC4p8O$7NIp%Tj)-%#wL~Q^!pC+v`@^3%>sr>de|Aycy!eBx
zM1s~Dely3jkNdDvev*PjACuauD~=YAeW>NY*dA61ZvJ$zg|$Z3eDb}lf!(wo;ly`m
z7rGBm+WZ5bfcN(Y=hwrwwh2jExMUih_}T@_*tMrQJr@IN#WL<&;}b8&LVXWQJs+mr
z;Xhm&v^3FCCI<n(5Z+D&x-|Yi#$teU$rJ+_w)t??XGpTQU7l`BqBPqSXn@GH7X{eV
ziBJEK97uBOVL}KsXr;i79--j=`{u;L&)*>bz>_PW`x$Kig_2*wG*xx?r%OR<YkqEN
zxrf@=-Z2;n!3P6&aTLq_RrW;w+7IX1%AuxiZ9)&a)Y|deRxtA4`d;URx-ED@Be~NV
z#A#W*Z(9jyEH->|?>pwK^-$|~vahBSQrjkHq_P<nF4*L5(Iu(K*%huo{J6_p+HLLm
zDA?V{1a)79D~~=9@^2139XmXI!YZIh6P(7NmmT7hTCX4NE#gV!yV6*t9nu<tER?JO
zQS^m~D#Sm|@3du3?s)2K0;d#4!-9Xg-aX$Kk=p7}TcaFYYtn}Ksq{+Gkly>VB*D!w
zyIL1g?Vi0MT#3wv$_rIYh$>v1T_xML&`RatSrb@{!d+uise)iOFHK>d3lF2}yr3!E
z*}{Behgem*`erLakykSgxmoH;z8l^XOq#+5_qJA2R|>r^r+UZ)s3c?G;lzuJGlkSI
z3d=Qvj7{)LW;O+Hb_7j!s6;y#H~IHmsr+J?W>qkB3rpo8dW5R-vD^tK#xxmk&*SnK
zpCv`{9J_Z}6r6?$S+;~w{Y0UKYRMhUc8v`KBvXikn0D=d7UqVE;8lE%N2bakL>}dL
zkw^gRRN5@I1`vlMatz%5b+PJ5ClP4&a)94FJJ#(En@<ucRP*@*iJAkOJFoB+lk22$
z2w~P?_Jf6>?4+?@?=zmvOu;cJulLm&WMlzm4n@)oqH+bjtdv~Dk8k-=3bbQv<27Jj
zvM8<fIfuDDG<^_)gY=0uRZgO;AS|kua|Rz-MDUfltx*+Kg)=d_A;Fi&3$=%)E>4bb
zV2MIHC0EHa0%HR$gmi~}YVhPg!gOWcfZFO*&Yzdq3dZ;t&<L@Rn}}&%RHI%5vnjK4
zl^IdDd7XxFF|R?H2`>aTf><HIMZcJ^SFxm1OI|^-4KWc}v`X&qr#Spx!h&q#H^R}h
zXkw4vl76D2^4`iQoOKjd2_uy2Hxva*+K!WXCxpV*Wb}pkmt*vXxJ?0STdww*>p7}i
z1exUekYB8E`j|eej#(~l=pU*$K6q@gc8aVV<hNZ^o$++6Nb&@{b!AYUt91>z1^}1R
zo$jGh9X+|o2+%yg0;VUKW1}B-=c5-vdB9d{+tbHqaN$#wnD7BmHbG_u`D(>@?QsS(
z)|g(YRvl!8SG@3QJI{a8v(#g)^G~szAG?7wq_U+~tGi!eq7r1O>LjhOl!PmY*+vfW
zMl8eSeR$a0eJ_IExx8YrM&804LT#PPt_fyqvo#71z<n9onnopkmNf5zM0c18D#tp9
zU(9syse<28_1@iF%D=tNY8`eabHzSBoa@)iXm3Yt=!)req<t=nYO6gK);*2gR<keJ
z`S~|8hb>GmeK2j0Fpn$D&lj4{%(EI65(Ayf!IA){Gj}U8Te0sVpxE+bz?LsvV0kOQ
zw+ZTxf%M=yV&{>(ImIDiC&8|wwnDQ%1fdAi@q{biFfS)5xPT?E15m-d7k3^cm83P0
z4cZ$;iepv^$;Dsz%tCz}6~FC4yRF9Y)bYzsE1`(2>B3?;H^h0U>x(9uR8cV5e;ub(
zv(tWe7}jRp{x6)D1+Yiqtl3^W=RxTM#l?T+rf*4!Y)dwq_?k_Z-TP2Y4%4CD8<(@R
zq-7KTYi75gwzhs@Ke>}n%<avMtn&`8SZX~p>zDDI{=!?W=(?r(v87Ax-j%-#R=%3m
ziN|g$;@Cs><N9GM9umIe^{xD$r;kLp<%+<f#qCy}ElJOoWU)zYb$5-qM<1Td7a~J<
z&17m&{h;u|P&uhG#NAEIn8F%OA?lBW1w8A*cQMypJm%_S!{OfRTTL`dcgGipb<s?J
z@L`8#@3_=PIn3P&;6FwBq!7<0+mZ8qOZ#R^u=FGa*meZ8mv#r~#xo0C78QHS{ip1v
zqfvdn-a7N(_k#@W^v=#&=IvEv@xbk|CIrR$>`bukLB5tlZ7l*GDYt)muZ7EYH(R40
zvqC$`Q6OV4TA(?F&yrfvac{RT9ofZ~oOi(^`eD3D_~Gy8^H(_Yzwx~eYJFj*j0!bX
ze26uS;^gJJb+Llm&kN1HSL&#njo<fGiptd?1Dk8T#H7GE>5l@(6BMM!^F(kycFp(T
zIJCn_ZJn~;8k$%A=m+D&-+bG|jJt%gxF+EiT9A-VdXnevOA3eKc_PfkcZpbqlAnwW
zSqT3xMUG}0)z*5+D57rh(yda>#^OcZ;+RsT+(qP%I13A;eLAfhRSC@R40%wmxDS#9
z4IvPxAp+@QAvLy+kj*eZe00f52rnL8jWT;eAH~Ai$jW<DgQ?Qn#*jiSQMMald~L&!
zhtNw61-J7+Dm4Pke=z9QtyD(wt(?3Z)ZvGgm$xUIaI;*>F#u>zG^4I~BQ#A#M|Tk^
zCgSVijAjr4;^06ggB(hRkK6{BNTkJbq=WJ#3Hgkd;{n=_&d3<84{OO`3Mbq1jO}uI
z(ICrS4uvin6(d`t4=+0A-2GGu=>cw<SBsg_QXBDT6LtVt1t$m(xom_yaX2qtB818u
z+?a@Zbd9f^D_7M^mNNhd{%V_Vu4b0G(X<<R2DF!XQ32dRR(Z+8row}HKZA%OdSsx^
zC3LuF79zcrW*TnK&5}hx(97%oJ%m?S0tsu8(edF^fyn&~PmKiufer>&;7K`agAwE*
zmOGfPp0)fZ9NzqNei?Ha>;(_o5WMyEq>^iuTtKga-X5wN>4sC0#ub1%hUaTR*}XTr
z^{LwT?95GVA3l2-6vv1lf_j9QhbZvqnqb3-9E^uyKhV5S!Yd@#jUdLgr%B7<>GI6+
zIOZTKiByYA)R2HZ7EWL)6J_b;(-*uj)MWw;qP*+fdwMo`rh=JVFIJFt`iq#(dZ~@W
zIN>Y@&*?4cxN|H-ix)38?0sZDWDcwZb+xSBXD|~_>k1B{>|x1<<i~bO&@4Ky^g;%<
zlxM)~5zvR)5kh6^T+aqjzvk+r6C3=`Wc7EL54`}NY>`r(!#M8~3LdpzL}R8eQ>DWB
z6Il~%LaIHtGLh5LEJ-vsB2>AFld(FaZ2?*(nAA7d(&CZR=4u@gs;$;l7NoEjqwgX)
z#$5}1n2Ql%s<v!nrY@w1kg7=KY#!fZUH?fEeasbCJ;RUM*0g*0{VbE4SImR1n5^Ip
z2;r`LR;~igistzSK6JQ;Y?bGb*?pAxZ%vx{tLEw$+nFuYR;AAN+OeI1q|Nc<>}hh7
zFlmbHn!E)cpHf#%z8<zcLyvONaMX>t&ME&o`*Y=}#gDyK>RKn%Eg);mtC^ig?Ry{X
z{H3stw=cUTsjYP8>l3Nf-CV8o2OPA~veKf;eN3MR)ld|UD@)*aGPk2&C{|myNe<Uh
zKc_RhISTVmyDjuuMjh{!<|x8l8Y#~q`j7EExQ^kkZsc6a<io^oGO6TBrYNfQ@H5+j
zykShpEw{9rG_i18F33_`Uk%vk76tla;ql~*DH2Cr9Eu9bn#K_{%D4Veo|WHZK35lq
z64(l&+RB`MV)`W0mlPx4`+Nvev6$>P*==S0fq;E8x1!Q09e!n}z5gYOw^C{BaCfr%
zraPote9Ub{XtV#ZpW~G0(vHlYd!Mt<{GD{~NW?XNuwikx^}e@+sFKI_7(WF4+`eg!
zImONvO?xKzgF1(&m=m*0?kV)u#a~zqHui5^Ud~V_i%&3$+<}-7=IViGqChuuaVD2;
zK4P~u9pF9IUPrl%3@<<YldTzQQ}FK}WLu8NUI~b_s#JJzm)_bgpYhl}KtLPC(gz_%
z%?jU`C473-A(pXS^?{wHPgVy4)Ye&@1?H0^5lk$I@y>U5w5AD&!@2@2);Scq1`3^o
z-I<jyoaOQRWjS`eMen}g_mWo8S(~K6G7l#$LC{Nwgu4f!^)-IcHTsAwM+J@^8M<QT
zow5GDIxlSaoxxg9O@}2#lGc7ltC1H+u8N!~`(dY4{rU%R><cp~MCjWB!i^`ebDGP>
zAHY$hRpXFwg0JS87&}WiJ=;{Qc<h3b&SLayqGWAn-9v-nd+Ek{m6ed?_hYhw4hhG&
z-yCW-!w#Fq5qKO=f)&O#0>s7!K%pDw_^hUM6lj8?R(Y-a@lNeIfVrs2$AsI2Nd^|f
z0!bf=1y+a6WRrHBRjjB`^P`waCaYC2{Xg8~@S9I2uhSSE`tb5XU*Y`Y<;v2}*iBOR
zAPb3dO^0O?cnqq3GheJcaGWhviXhqc^nj_Mj7PD@l+wh}M?0_8+TwDX$Jh6t$=5M3
zQ(Nhk(RxUOb%m-St$Ri<X}YPer~*RlIOHf&4XpgPGTJHNC`O3KQa8|XF@<=RW@B_P
zroE~ioaTYoN-xwghkAf);}PQMBpjq(30@<yA`S$Io2}XqClQg6iq#~1RTPp5V*DQf
z@gnUF@yL^hh@-k%n5zQ9283ii1YS5Axlzsr0X4gW=H1J2J&LdEq|9sxL!mn?XPwy%
zL0BKMv!5LzDVWwP!Lejqy{Sg!VX5^dR#@((-XMZ}q(iM@g18WopGG?5oPWz#RhIWr
zDI8`oT=$uTMnZUQ4^NVe2bFCM8h;XH6+<a|sGA-+`og1N2r&p#vAma!%iee#iF<8m
z78KPYPb}D`V-RxuxY{BpVUIC4XDkXzMF|kvzhECVAGg9SEA-31r0x|fUI4BXn2?ax
z2w0o|DIl^J4bwq3uwDz=OtZteL{xtL3=SxpS}@6-8N4V-yIcqrLYiQw%9UrSfPy2C
zhqeQ%h9r*%r<RdazycaP1Qlrd%1i=bmc_R=lrQ!?6cAEbdmh%qoQ!QDa<&9YT>2I&
z)N0u29G9JD!RO54N1StYz}DtXY2PrFEaf!r#Tfj+RqnNn7We~-5Lr&S63bSQFDLRD
zv1f?mGY8q|RQPuABcx9FA|eP%x9|}gvMS{k2j&$3KSi+28NjAal9Zf^i<=P*d~KL?
z<KhH9+d>c`ku$J*QpaAD!FAbYU`9?(g3Xd*m0OLFGdR7P+z5_EWE1j~aZ-bel>Lkb
z;6QO{wKb?djI-1@FlSC_4LJvA)6j?vT7(_E_v0?r!Zf4p5A+p6Jj@dsfgGkNr7q#f
znYkafKmeW>Lu^fjnutUnhmX@C1I;PD{!%0Y`v58CplGfR*@D!aVn9{_@?K5+TntB%
zNCt2FLGk=$yFfTB6g+aKoy2wqMjzPER1=hpZfJBrO|&G6*tph)T^D<%ydAPp4?hN3
zV2BmN17^-=i_OMfgnhzR%7AY^ZBwmI)(+W_=eG>GORmg221+)uY8QJOTI8TGLoX;x
zgK*Y%8QD1}>>ORN+y$}q4+jr}|9?PLd(Mt@>?0IqQ=WTC^%tH`^n}<;D|v1Cu1SSg
zV32}3jF)jE4`=3OW<3<SwuQwQB}5!jby$)k`fSc{^4j+8Um=T@i#0mt+wpciv5}D9
zl-LT|MhG2op!Tdx2H|Xsf#233nK}N0Dr%b1XQj}Uf<s^gXk$HC%_g1^A_+zRhXDgR
zi6)4tIN2*AP8oS6M3Ni5k2w+vl~2?JedTa9yQ@U1J*%)Y8<C_V>`b)1;)pyYlU70G
zu`Mtk4MJe_VAu#6Hl_`c&RB;z3FF)dQyT(`kh3R0p0ycI&|imITCjtOaioDy)7}Qw
zp*%3c3^L3mvg0=59r29Rl_9Tz&HQ<A^Q+d;b=3-BN*0L}u}g$AhOt@Ggo=@FiLxId
zD*qYo?V%(XL_uM(ID7UL0_Ic%&WcbarWPHPtWaHa@S3k2k)Bc$I_Xs?sxgY#y_c6F
zwu*>}Z5w!ku$Y!`ZjmF7^Ky~&9>>_gWA-%9LL?^FKmh+e^+9%l7!-u~-t-a|HIyCM
z8f&(^d0(#%KZB_s*wKKjtk+b8)}DxSc`u15IKfnHp<mz-1}@Lzc%n4odt)jJ*b0XD
zHdSFc)dQJF2)vzMxWhVG4Wg5GQj`n$MVXY~0C6Lys!2f+^h+0B8Bt{ehJCXmlYL;n
z)U3rRpKZX6QnflDWDN%+HTbBBgf{M-aY?!k7}$h<r$P?m<;<eetniE=)h@g2j6tvT
zTtd4z`bzKQqe(V})!-#Qp5oDlouk~nJbDn4%{AS|de#d*qovG^OJp2jUebdIahpZp
zg@rRzcvj#&c^W|ue29gYXdswQ^R_A+j}W3AQOz@$2qQtrqZx=gAQTm<+lcR)92)kQ
zgygr#g$El$x3VYNz0m8Dt$iNcJRBt|kC1#fzH|Eu#S)JO{<amm?WK9eeN@fgZF#DA
zKM3Ccqdd1ina-~0a9RW?>L}&En<~Qd!4;j$eezpVMR^0itD*CUtDHRys2$qtN$?en
zv89*gqY68tv35P)uj6^)h{C;IHrcexxwk#nf!rGWr2RPR%RS41%2idS(+V7?eAz#;
zaM4j*@PCTyB%WhwxHU%26KAVDF~)m8MZM?`EnDNxvF3Zo2CJmDu%4anzuY}Cak9;+
z3;c_#IlIw6H49{<s)U%XxIRW=-y%=nHsKj~qSPJcjCiGD-l=8(mW~F-bAK#^w+?-&
zG2J+4UjU&$%t|j=d?AbXRCdXDYnXPZcst%=Pw)ALJ@ruBrGePxEb@!ULu^0f{G>-Z
zB(~@IP;my!?j@-v{ekN{fIA*A|0y;`Z+>Y9R8!tM$NALo-5h$j>bWCvJ;{W+mNi?h
z`B8q6A>&GrD5)3uQSZE%j30ZQ2pKv_Gq;QHHs?<aH~HZz=eVlIO3KBPt8VAOV3VA<
z$RGY<S8JmAH;$jUkeDO*(AiPsA05tGC%${WvtR24)CgOc!lRtbD_naIzzjc}5i6Tc
z`Dt&em9k_}lJOIF`Gk1OY>7y<lhJ<kvY-$D27_!LSEqbn(r#I67<Ya~aJ(Nnva2|z
z?Gi4xjRSA2o#oQ7RvlRUQW-~<L5aIX#BDwP9h&|iu>ae6Gu(c!x9j%sA^F;psb_ic
z!eCcF6Y_9B3D5J@VoXf+yR@QZpQT-Py4kX-R(SZyop$j2yczGI*<T`qUt{_=dbu^H
z!4J2SeKFtpLztZ#&qDinsw4z%54xlE)ZK3<m-Hp=_xG~Xv=c*NadEVHTVt{1$HyBp
z&^t@0ewJt?b_6l*KHewmRIZDq8f&dNd1lw~T0<D@WQ4gtwmlhpEQ7$J9lyZYsdO!j
z-w-3T4t)<)HjqtS`pQULnBQ>83@AgVt*f{ldm+f|58)uv_XR(Gqei!=wu%s64aK8a
zre13Yx<e^z3YaOn1?Bp)I;eM!i#sd9k=r5Nc&PqCTkF5Y*k`O_;&06v4hcu*-|y{B
zM=xNked{27rifj~CjD%~>tv*bYn;3yWOiRpNwOdkGB2M2YjBL*d%0*M9~)q~w#U<e
zk<TP-Ei3WGO>l_fP-^rw>h`8<!Y4H%_7hIHL9YnS6|N)Av=_9IiQ!oU1_bjmsvyZy
z5Og|WAaGzw35k7gkXemE(NC@vDjT4K4=&oOmy2w4CX#a!!|`;Ro;Pr`U^102CWk)O
zwMFM@E|c$>-jbuvYpF|W<ue;mNF!+3Z8T3y*{!oL)=o;#)glT#`I&ixyU3sfQ1W=5
zSeDJF#LzIpZObwMG~Wobfgd>pJw>Q1H8+81u4xa+`{Ft&w4Rb&>s(v&L77M4j7sce
z$Lew)y`yWJSMD<MHoE|d=O4S;IwZ}7=qT~%6>zkbT#MS2I^KqwIAam!h{Z2*VhrO%
z3P~+1Vw=ne1C%-ySMw<EJ}_ZVgou)Qk!bb2JyY>)EK5s6kz5Sg^7Zn9hrzG`S-BU7
zRdLF4MhG92cO$ShovQvBu{L@-5Zx0SeQG-ecw1SgGFI^uvLr1LiNk!vew5tLL@Dx;
zSO<bI8qzu%kw`y5lj)!85dtWjt32cKNA~{__cqX#9M^qkb-%`&Hy}7{3}+~C#E$|9
zQXoZ1;D?kEBU1$oM1d3&KQW?B%arnlp~tkXWa*G%sF+p?AV|S9y@q5u89DauBQ@TP
zWmy^NXm{z4IL(jvj1)R&<ij|Mj-7?Ivch!~?Ko>Ev@Ngq_rKl!@PGmE9vz>v7kFJ&
zw{G3Kb*s9%ZdG-4N4ygs73a=C@{2CuL;f`sjexS2loqGDhh?@J#$CfnjVoldJ9x`j
zs-7!p8(x|9K=r_)zYiy=iTiu#T|9nk+&Ks%*p$oGBr2T2K=~^=HRZVX9vV#OVJgoi
zg!p-Wfp2THbV3&CbVE>^Wk6Fd73?lyO@$k&2sVMYHl0R=(G&}!s2W#tQr^LZK>u(N
zD4!Flu4slpOcxZujB!sRq33f9x;Z1*q-nQ-#ezX%egh%2Ym!dwsa=of{d1SPu><jr
zRu{9iyl3m^9o#M2u-7Im4@Dec2TQk3C{6l0U>-`M&PmGFN2Z^B9Sg=E)Ew?Why`Y=
z-UaFAk*|K$^u-Z+_a8-fUq2WdD5X^&GL!Mz+N@FW!Rrl?ZP+5I){$bEe8nOO3^kYD
z>WcJLdsQeHU(X`cDQ)|%UK|mUvb`&7hcomKp&YF^*S)IiO_X1QwzWT$dwkv(mR#ph
zHWog@)aF@Mjb*l)@Gqa&x@TC)TJiFL*~;Uf&un#4FlMVi`p1mRFk3z0LEueE$~TG>
zJLP+Df`Zas{;H-|07>cjrOHIr&=uw?e#$n{v8C(XbV;XPZfISxI{{`ZpJLqW)`~aq
z!9J+yP-U-l_8gpUz2lop*2qU?MtiYHe$KL;#%!Hd4*J5OJI;|Zk}UOSCrf)wq`QGv
z?aw{QM8uUY3$MOWC5g(tbMlH-@-G;!9RHpq5l{L&q7o*Y#y&!{OPQ7;r^BzhWHsT9
zOg3cZr`|WR>V9ZqEM9!tx#ymxO@8;?+}5wsHdQYY{{F|9w3g0x2XCc}|LSL$8I^go
zVYYHA^ho9&YPxX`i|)@QjE8sURmO^l(#4?QyZ;Xr)bdbunF$tz!JbWfl~1W-hTJ+~
zoqmX(s(x+G5{Z5QM3zij?n565ZjQ4^Z8Ivlo;V+?<FS40eqeHg2-HX>+FW>ia^G|+
z_1oE~9N!rvXD2i=4~f3Z;UexJh*pGym!$4?s<tyqMYy0$;_S;VJ+AYPR^9;4c;ec=
z)#)j{8qY@rWwu@tlw!1%YyWKiA|$_lb23ix^LwvCVOZ^{gzvm<FT4E@@~Np`nJU{2
z+;)S#wuRCrVCYL`|EbDaLhE-%TJ83=`7%QJ>_8(Qi*?ihR~1--zqIzr4f=vn2_4?7
zsJx}4G;{I_Jy(n|n0dGi2ssGWnkO&!F8raJ9C?X1z01z@IhQ@!Y2Ej3`h9)u;w57e
zXXqAJ=#RaE-VADNV>KujzjdJ;0P{JTXPAqggZYm^c~EU5T0?e;XCo5(y9=sz1CA%*
zy%Px)Ig>7>M8#7@cr2##ft`^tJpJo)srz+Ca}@u&<RG&&X0=~NkMRAj<%`RFNX9m+
zZG-hz-wke2XWDd1v(@z{W5<h+6{3`OYvO_7jVd-$&)J+6bZd{?sEgXZ@{c6KA2roo
zHg!ep2Givuq7wosqHd1ImEJZEwH!F19IOQ~SVq%jNY_>wlQ=)uLt2VnXnRkklV+`(
zy)_vRPvtsAIMg^?9t;M063uF;aUa1^b<z+EmidLk(eo+<(m30raZx&9l1353K#Uqj
zQ?lTEKYb-@569EswL)j(FcC`{xqA7$Ep5nGL99J0i~l`ogK2UrT&eP2{PrG{q}Grz
z@(g%$|CG^rw%z4(L^$ROOUMZ%^vnF{J~XINE<us!M<IbU4%M1GtOO>e`6@(!VX3}?
zhbo~8m<GmLWF<f40V$D}lKVX-Rg!j$Nk?>#x<Zbs)H7lDXp*}pbT2@HbbhWbh)8w^
z>NOUy$(nt1G$DemkGq79g@L&5i`(8CD|A}9p>li9If!12c{+6v2EqJla6^FzDM6^S
zRwDUz%;_Q#c}i!<yj^L^ux9Tfewso5DKfp%Cm#GDsG7YSi?wf~ep$rtl11XHd|U-l
zwd3ZSs(!w$5ewu&>E6VSNuDpeI2Rz%zRWzs=Jxn?o0pZTISi%U9cp<fB`=&&%7*E}
z5_Q$8w6HWo>wbpu(t5A^+@0x0>_#iz!0q6(o&a&86_7HRhpabLwL?ln$HXT4CM>mP
z*aXsqAzZB;5Ky{+y8$P*(GyRffl#rAr8MoK@ARdyDY+F&l(nwtM?d4-MNtUNp`FBy
z%o!)p8E9%GiFl<tuL4xyU0c2s+8Xs*+}>9|82sMGmWWH~EnZ<D5inbafY2*zO&n^E
zxi4iKqEZx-vDaE=d4;|ji64tj6X6FK>zvxeVEaIHn5}twLUV9E=(J`VXy-DvOMkZE
zZeSP{SV@?b2KC+U63B$r)>sDY%{qBGljEF%lq8$3RvG@xTa&<BC9e5u`C65c%rQZ6
z`tL0|cXG8aN%uo89693{3SHRB^S6@6r<3k%r)q~|twYd`FsFG;*<&5GKhk>2oeh`=
zno1QM<m3?Z47#kp3ko}Az|&v#mFA0Mt>iy52h(|aDs?xFmCa>WZfas;AUE<uG8b_4
zD<i(K5#c6<R5h4(RNWjbs<S1*JixeS{ZZmCuby@wcLcIaFk7b&f7_)?P`w~tXh92r
zF8!D6iTz9~iN$v!53kLUt#2KDbFgf~I=7M*4^8BPwyU)Fhs4C)F-MC)P>;v|FcYj_
zIpjikwR|^F9Im{cSgk2u`!y&GqdeZbZ>%-;Cs?{jmL542!>MnfkW)Wt*>>(f$@cyP
zOJA?Lt>@?E>8CD<`G(m_ci_J|%m7D{o#mpJ6<gmXS#`5W?8tw7=<$}j@lO-q{p2Jq
zZxD>S!ojUn7_J#(xE^ody~hKZg}IGzLgkOjn27vrK~SdVAu|_?Jz@T{k7R3n5|R$;
zC&X_6(AbmYvNZkKk1~UPyb;8GmRg-Ao!*IytA9dhy}<}c#-YkZ1$L$E?&(J2$zoYe
ztMi<i0VHofIUq+xclotHAKUT8OEPyipSkXgUg5-(+<p6#OUsdyM!RDl_ADWQCEI+(
z+RZ--`~6=uY<%t(?`-(Or?Z(z4i~PyHa?O)C9D1DSO1#orJ7E7+g^qZm&5nxub>MX
z0A22GR9SG!ud~&8%vK3zAkTPvEc|k4FJ~FA%~9szq0Bp4*DaBQ`qYJO)93URZN1Uv
zF&AewZx^~>ahZJ*^4ZsIo8%m1s?}Eahg8r@y*Ledsb7r4{F5}dv*<PMu~EMpArnFB
z9$*Cr&$0!-dLb<dk(d5##lnLw!Tohuyh}B9D}w<uTdOp!#GTi06eYwS7tfc7Dd~@c
z_y_5&h7JeaiRh+dDNftXjbQ(J9ue<w>O|3*o+1;Ntxhik#-*Fw^OkVHCFgO|8eLDk
zy^|Pk;QZ5#6kT=W-6W3WVy}802&%#!q%M{{ETYQz=u|PjM^Sk+<St=9Lw~PUpwDTv
z$#lMs+0CV9NK}CeP%AUwkMvs+)%%EU?9Kr>y2eEi?fQDVA|m_jftcph*D#<qVN)3*
z?wPFxdjKL2f)lz+H;?9duELyb>w%r)hRKu~Wa1g}j(hnD(KM<%6Ioi7cV<D)mmwhy
zHDT?sF$L9XJ8rHcU#&F^0PW~3A@(RM?WD7m#9&)>1)>uB(?>@N#`d!e!lOR+Hy9H8
zs3%HcKUWQvFAzrdJo8+m=hp_4RGJR^U4e?#iipX^Vlwa5K2lC}0JA$-!cOiomu59}
z?b3#*Ph*?ku~A^25wSp}*5!(OEE8B8(vv9<!oG;v&4dNJo(NE?6;4<c1e!wVsn}54
zUL;wgs}`lo^W`|BqNI(Z3Fm`LJTc^AVSK{_<1OD$U01r{`eQ=qC*!Wpq9NG(o0@0P
z<&cwt@?4#MRI!3pr%S28PNAUqs6arB^3q7XYZT>Ya~3Uvi-`!YinK=W=*CQ~g^%4w
zI$X&hh=}4<*W7Qx3sXUy>U7j<Kv$Txo==F#kCp{X5+`Ce$&Y#oeB?|GU(bzUAVSLa
zWtVkC-SE2BkljnwQk}l&B+>aAy`vl429eYg>4fWsseGifAlIN@aq-Fu87sH!XdqrP
zJ=fT6-C*jNOEb4(wW3<J>~JkRb$8146hC7Z<${UqrFL}DCAuw71)=ur>{jx7@ird1
zJxa*gADYd%sEnJd6;e*rL;RxPtI0ty)2i0GswSr8Lqsw1S?KAiBuSP*gqj$V9Uybd
zdK`57qU-+2jbpZU<4C%CaonFZI>USk5_w{eRpgM2_%&KeiFvUXvDFhn#J%o@C1<Og
z7X4e9W4MsCiVtsjGHp$)F#Xl@T5TOUky5p4;J?<2lppI8{al8Q&(dro+q(d-i|fju
zD>n(dBWz!uWGik|+7i}ng}n}K@5T}xlkPpSEweT0mI_ZU7-v#z*}Z?FlLjqHSxYkN
z?ltbNaArP9PS$nve}|`$&kE_?@30o{{Qg$>s5|Q7_wtr+o4sCV)2P+fnEcnQu*Y}Z
zc#P#Xm#9*%k2@WBn!96c4A?MRy}RzbR_moC`pzFWlIG{PNxmJ*OJ3zG6C(fYJ7z@`
z_}N{nh!uY1SSeVlwt+^u61P;|R+oG<nnB_|c5u>*WFTO+y4gRSj}b~6)AO8KSjRXt
zljhY-CXF3nnR*(G`&a+675B19_?xdZ@_^YISjPG>rIln6n{Q42LD2G|coT22e&tFg
z=)22I%JKPz?{~@P_l<BQUn{tYKXA5!TaHV<JenodYOCu=Q>Xr-;nwy}uc<lS*XdrF
zC5^o??k&b$`(HDal1{Lr@m1fl)z*uy@vTn0LaG}GnLo?zWaiNWNz!k&zRZWHyT_QW
zJoU$Wz0=q3hXT>5dD;s0yDyJQbd@d^@dy$44_W2EiUtYTmS7J?14P64ryfj7dzwTu
zA{hwDW$w01?{hvV191mD+zwv(y~y)Gd6Y|{2r>!U2yUOfc<{^!{XDlWUyURoU?i`W
zeua01!!NoJzm1{$As*rP-dT3V#^IO7xxKP+*SwA)iD3|<(4_Rr%|7v;J>q7Ut_gXW
z?Whe)-QkyAC*FVg42R74<o<S&%swzNS#A=(o~Ew`+Kyh#1_Nem_++)(8gKk$=6bE+
zk1q{-4>#Oo(%v60`Zt3)ZJ{_z*uQCu5cO&+aU)vO1n4Wvah`?BOJv9U#?Ioth;6-l
zoHhwhwTeF<Um?FJA~hnwyI1xn-FUH;Dj15(DwCAaX4aDboG|WYo&w{r53u?ALOXlo
zpE2qCa<acQs|7RlrUo&KvXhu`aIHJz?IlvzZiaT><Canm8P>>SnrypEalWFM^9jqW
z1m4f@MOs*Qzn&rlj!}Tf<fnggGPs#{)TzINzL(Wjl`>CmaLf1%IBDgyj&XP|^JuB!
z|1!|ij&4MN9UrBqx~dKFIPqqm^@xQbfj6RH*Ih1AEQ~n1HRzO8;Ag<(Svw)Nl|oes
zQN~QUJmQm07H~ZuSH{r|mu@5{v=f-LQL(Lbro7ATZdH*GAdT=;-&)qS2M2#e${T&b
z73d;>VO7g+4$Roco$KJn#(c{6^^{HEC$R3U^zL>giT<adf%z6-6c^D$)+9Sm+$NoD
zq1`rUvkz9%I(4i{P?KjMHW>SAa3u`2z+=il<r)M!lHEU+%m$k_5jCj;4tiZy(9QGf
zQj$;?G+iJzZH84R3petsA-eKuSci9UQ%hL0EVXFzQWWVcO2JmIL0s5FvGP0($S||g
zJxM=<xsG7Ok|@fvgqrk}wg6^pQtv$Q&`q>OG6=-bK5bLD)ySIiR@ij1<JQPs!clQs
zTf)|`%ODCJ%Ex5IjD<3_1JBQum3&STMV$k>7hT{t#Ym|a+bBxS6wIp%smY)<i>)hS
zRGE;r9SmJvqM~CzW;=hLh@{s8s3>BU->B-M?$j?$dJ1Kk#U#i;PHg#8q<8R(O-{E_
z_x;{ki4UP>L3oYT%8;nqL*nk@BnkktReedAi3$yXnE3hKUad)|)R<p8_&Q112U+K)
zQkPIx86^R@coykhBP!szC`p%J<UdJd`wfDniXa3VG?k1|5+A;?m}wN%S?O_U%ZG{#
zV&$51b$?)xALX|^l9!+|5m;99Ny!`G0|9SUM4Y)qFi=+lo|RE=OABq!xPmTsJP-nt
zCO7hR9{kITTrx_P`f_HXTu=tN8>rB*J_oub=8oh?oj)gXM+BTUKRL@SvURygch-jy
zw()L))V)Z;_)u8^Egtb4=r+05!sr}d`+&VCzKQ;vfC|8%D97}i9Pt;pTb4L-36wrT
z%?oMX#qJ(=txsFAm$bOu2Q(Zw3AMt#<gyv46`D@hlTw%}Zd)gM&}&yuDR-BCsA{MR
zyz(@LOC#|%*15CfnYY^C8Rz_)p>F%uK@MPz`9YV(jKYSWrw_S-HICKMhN|7A1-<pu
zk??%`^~tT-X|;lE;Xe0JbXj{TpAyM#5S=UBL9y!lOt>YGtduN!=?L9`FqWM>gFu9;
z$0$N<QSJ#J<hKY$-H~m)PLg_I$;5r=&xyR~kyhe`Si*$X&epkg<^h+#Cx9CQp1*`=
z&^K85$***7;f*H3y?gi1Xel-Mr{Bs?#JRWHhcmQW*J~m4Z&Jp*T+)TV?Y_k2Sxo#{
zK3|QyD?|#^4eS}A2yx;eU+M{*j==Q4+n}RikKpPLq6zW*+%F|*{$p?UuJtksS?5L2
z#}Cnm#4B9<_ah5vDsVO`FT;x4B@YL;@De+g(~r8<_Ls*w$K;~uF8WmlE7vE5xa|sY
z3KRY|Ry~*gcKP%PCAoC%R&=?y=}`gz%3S$(gt9S2yZ?izRF#0&PsX7LRHWXz^%|Dd
zIImv@8D)oR-I^Y38JKK&S`L6RTc<}+q3`u1zoNw-vZQv(Y-N+OdpH#<KCT%euGG`I
z3Xc|KCE2t|_TwM+uKo4#T6E%ffJmZt!Q277-8cS%tV+Uo3(t_*$Eh76td$rqYwFKl
zen*;hsrojP6=WMGZs%p+`#6yC(My9q2Vz?9-u?>+&qPrErvD*Xx%45I7timxUR>_D
z{#X5anawWONSv};77e8gUY-glXz1MaO?PXJ80=P0D=F_BXcY~*2Ekc=ou+wRhGo^T
zz5=7n(-UdPV9<N*w4$ug+c_gv2vgpH=4TqWj2yng$Qlnb%RsiAH_hYvC9@zHW!_+|
ztB=uay^<`+il3xH-k!|&#c%IrfjGvS#-n1BS1$K*f$ps5^=0zh26zcpHgmh(XcJ4e
zHeip>W^0Y<w=hP(!9_Ju*M0M3z*6;TY%l}&*Es<0Yo+iD?$c@Cf}Uu%fi{{17V0Qf
z@wO1Q#qNfTJ4Lq3dh2DCc^jQ(t`#}9lt3Ry3!yK(yVo?Lenlg$s%g!Zu5X>8N3-NP
zwP7A~ANe^1DpSrVt-fL&$hB39X_VVvf~D%M1lk$KqGY-$kk#zwRBHrH0A(4H=&)II
zP+Sa*2+Kj?jVivPVeIG4%;Dx8M;wrkFNz<+`^?xVv=anlu~Te`mxyrw?}ps@l1Ika
z5N}Votbl)dpNrCJA2dV4ifh?Q`_MakEj8Sw?#Qo84-^iNZ7li5X^`$70#f;D1-vdm
z!bH6rWdnJBA1{^%ZSn2NX9PQ6jCY~RtbnFLHB|MgIt~i$*M&LW6&&?HxpeTfc85~O
z;nae|u;cE1k|@a5+!GMV+??npq2#BSlvSO>gC#4CJf@MHmt6hB*l4QZA{k9~@!b{T
zPO)2)OYuFhW}RJEW@p{$jKwv4*n6njtI#9f&J+8Q6x^%2lm#5F$89}Vw%%;M-&BK2
zB>XCA`cKpMLzI|gMWQ<?Caxo1F0^%}JcV=yY?x*dB7JQ-2_1{+Fx2I*vr+1Kj=ii!
zDUEA?jiW#LBJ^a%HUR6@VscqD4!c|+C%bTde|6U6B$jQFovso2hLAPtwYs%2Vd<)(
zmpmvmr$nHc8k>ViV;MR4s^m%;#u;UX9=&J2*C1QHm%GO1EYw2_C|e1)l+MQOrYh}k
z05#zjHz+(Y$7MzLPtaXf!lBCTbLyykiJ=)nMdI`;r4CcN5j9)U7EXau@W`#oO_j0&
zP{ow-yI+H%TS=YgX5uc@7<%tTU6zK;(c6T4iL0E7KpMwN(>|*_d8t(AO#PCnB3*in
z^O53zGJlmw&e}z-7$59I?Bw-TM~!mBNas?QtG9()a^D*$*<~o@Ta(e<|2i%=2w%f7
z#?G@BF1E02L;O;PS&Kzw@ZgW-q4MtR=)kOYgWK;SdbwlEE}fa7I)GOu)z5ND?><wk
zDh60jTv*%76Ej5wmQ)wr0V3LgD9PlHP|uu?ix+5xmT&tad_0ZmR}wev-axa_!bq{V
zCNaA0FDV`Sf%BMHyTHw#L-F48U3_Ua!jCqE`JwUM?jQmR<|SK1$7*t(#25~q(`ix}
zmRT9WZe3#XK#Ah$1Nis7aV~->%P2*xpMBK%_x$ZuLn>lNsIs;4#@TGS`93XB@ao`m
ztn488?BO%Xbo@M%AdkJ>1!A-lg`>S6aIIU}t=qt|-JAcPj7F+=TU`firC*4507{o%
zmnAMY^N7!b6u+JZ(eAq`xK88U%wk=}IFRB?4Q}%6g=?+%zRA05L!N|-siu^hIzO54
zYR2s>bWmsahrOvovN&-con($Ck4=R9rf;^ESHHMtZ{+pY#e4qC6(^L(t`IU#=y~kI
zHMjIXJG`oh3Mf>R_ugB=te5A#m+o*+E3zLDOJylpX@L;%3icw_8^I&8Ek;E0xec?m
z)f|048iE##G{Gb4#1c&#TX!g^Oi#DCnkMZZDGyPbVk@~PV)@b^U1^0sJQB=W*52e#
zisvo=h>7U#LECLU!m?*vUu+;2BC}N4o9W##_ef0po2^`KW8uTrOg(;w*_y2VR(c>#
z9k5yMprLDS*7CFeBzGqcyX4BxKI-!8ULP~9wieGaA4JniXHTx2`Dqx8?Yl9_JGUKi
z@t5|wrK|57>9oK6XmG!H3A=kgH@~brc7>??pwK>s_}iZ`{ky=QDuy`MylX6(G!`cn
z90E3z(W`~TZosgS_H0>oJ;XeH1x>Zwks@+~Ec`phfdz^l3a|l{GNfN`oN$LPjK=2}
z1tDU8{3D|NlmSEsmNjIncP+HSGnR}Zv!<DR_5$u5b;R$WH?Qe-beAZ{%%rz?9$4*)
zFqPRFwc1*lawP%%|6-Dlgz@eeeKxDD`N?IkY`e|l=|Tg^R+5ibEaKsmFKV~oxNjnj
z7yDJWlE;zuzTC%OadZ%aAR568{eGBSyEs(jzH-Yt*R3Z^>{CgPV0TaMRz;wD&&yK@
zlm!LUo)jZ63U5uKMhR`tn!);Ih$(7uM-we<8f%x!Wp<_f@a8e4xqv<hsf#|Xa?He_
zKleVuZM_j}EXyRxJ--rEGBd9>*hP^FG7KGWK3zC0inYO#Ox0D!_;Mhud73BNhg^(V
z!;L({x^WVaH$pcYG+hv(UF6vWQj1C(H(`egP+C$2(TYo1TzIw5Cq$%SU4aJ}^SVY|
z44ScZaMq>40)sBFUYr*Z+*`h43^P4BIGDlhUrAy|@y?V271=VvX-46yY&Ad7aVs*6
zv|)KLc;<l^1nD(Pph|(G!pc|-a!W|`v__cLnh}Onc2F7#tYD0!_d>-JLppKsizSB@
z)+#9igruXVajhwu!7v7OFe{p^h7!pVi@_#X+Y}lqAf?rX+?pT?VL9m%AT6_<CFCiE
z(w0wiJV>{9t<si)I|GU=$F3+wtOUl`G+c&VS8mh=nAWAE3rR{D6cCtlOYg2%zML6q
z0_9VrOI)w#hs*(|ml-}4g9LLO;dxk4wiKdP=3NMt%%?04{36EWdb)(orF(eZ&{K%1
zuL%qTzfmOJsD@RR@Z2O#%!9vDQ1P;wW5i=BZQzM&_?y5FWj}68!mQf@71J-YWzejs
z7B^E9I=&SXw<2~5N9v|jIX3sxDv2r~bw}<c`_L~!$$^JMfO$so+l)D4Yaa42N2H#@
z9oz)h;=40=P{|UPY5DY^H9L;mekjmjU-!ipAaD0Qn5~@}Z`!E?JGuQtQAA=>gCg^h
z&Q<+)@&$By4@<W)%BodPPTL)EdO)V(bI#)qg4krW^{M0~GQ(^QOVchWNx_m0JAkim
zzU1cjG88I>t1{uclfk4L=S!3&RO`SQCmN^z+*+xq`W?*HG8oDnt+XBP+$nlgVw7Xx
zN7WqPn=y|cbN3&;4#D#-9CSW;KNBcnx_g2F)%EWFTT2l`o7s?=6x-zf8P|MfI_2f1
zImU6`Wk0-ks9FtsPraU8d0#F3Pm|VBNC+F%A#nW7*${&e6q4`|0HMhiapx(e3O3Kr
zI1mUNV3VaPz899YRrX7I7D8`E5ogJRf3MZnK=y~e`?7i5!O-Hfj=7BD<9eU)#xcG)
z#n5S;<C&hn#A^p|_yjiTi<WJbNtA7&d$*x4QA*5MU~5Wbmc*EP9h|G1)!oUzn<&Od
z=6-BcvvT2YzBRb@dnhmw$LN6ciVkIhr~Baxod3}O!?Z;9=Ggkg#Ypx`98r5k(?#u(
z?mpbe)J%@w`rjtqZU6d>G5KyLgU)<2SzJ!`xzAt*-r>K{2s4v|CENeGZjxq87c6IE
z-<c$#PLMet@h?5pOh4iAcyb#KL`dPXfNO_B<9dFsim(M_)p0aUDrVm`6#Qdvb>m<d
z%L6+8R`0gzJBE-B29r;3`Udri|FG%bi#n&^Fb#*UT1n^WeR+m)=q~(*TUWnZpvioO
zHBBvhYIk2)KgHYZn5}J^fgWQ6q18T9?teS-t-n~!I_?c{aqerErS2>%2QmF8ww0%R
zA{=<txtE`MTUj>WV6XV(1$lD%V%<V}_BU_aKkjCWtg{RQKQ^2BW54m3k1ssoT8j@Y
zyW-5p+&!PVB#*Oy#O7nmWq09Pcm4eSvGU8MG#78f^4Lp~w{Op^c*8W^UaH!|M0Wi|
zGgQ=-B3r;3^Ne}dKib7?J%4gqp;BfH*|hqO;ZW6zeDt^Ih+TZy2wR&$*q0EqLY)>i
zY4g+GB_<DRnxLrHF`C*jZYC^SWfI)0dy<sC+R-Dn7DTc;MCYEFGm@~*90ozbZ1GVy
zQ~Zo)n=kEB7&Yi<rzC$tLCO~Q?p<_iNVd-W(z1}P8@W_1DWC-JzK_J+i;{NxWjL>}
z^z%MS;U-IRCD{#<cn>UWlkhfVv&6l2=x<H^e&ZCk;pa1uEsN>hBaA3S8FU#4p^qYo
zJe6aK$YycXEu?L9`-~>jP0<y3z@3AnHFLDYOy!wdj8iU#%#&bO2+AaKJcL0cKsHsP
zE`HDNIeu<a)5fUEm!%ZaEh^S3{WN{`nunoAI5C0kJRT&=V(JS2Y`L4Rb+k+OeX2{;
z?$F{COiAZ5Ycksr+kmR8n4zB4n^;`CDO3frm~BQEnyBkI-ZcSlS`VeGlS5PdgTaWR
z^V(wKqv+uknugvVaTx4J?|eBMK{W$~ZVsuu4B{D!N(NBUbDE<?^j~6Mpg?-`-}2z}
z(w-nB{i{H^IuKP_!H<I&QtfNDmi!cSJOfr-VE&)Ta(f7Rm~vOSg=Lyz6!z*5Aydl*
zzogKv;EBcZmMS%`yal2PS3d90jod=JbFk9S0u(*{b?^m+WQVlw!NYA;t@>qstmOB7
z;a$CDMv|04Skww&!_DiNS&ZZN&6rx2k$}K=#G49SRl>k8HX~OcQn~x0d3U)4i6&CB
zK(c_FI}1t%do;IN_rZFOpofrmqKWSi0;w0&f1GUd2=%1u*nLWgB@CbW^EmVTT#OL&
zZxycAO4u?XZYN;PA|`%eKW1y_oJ(X=)SoyP|5`BHutipivKf$cN+mK-qeex4Iq(ZA
zwzuR`7M#kK;x|v;_i{_5B{V>eeogd1QSEOiL)%|rz@5~Kqe%5E%2mDc*&SmfRwmVm
z`UiHp)G5Uvz{s#JPRT>v8HcMJty9u5{)5OMsG$ym#KclgVGC)@x}$D6z0{gdne7&e
zZG$EsG2Jru*ESOo+jV9fzM~Z^s<=Jsr6CIPP>C>G3qv+{#d|3H2UBl!11^QdpQU0d
zv(>_DD%fTD{*kk^^)vfe1A7Nm!8k&AWqT$q9u*0{vzk{vzia^RcevN<l8AB#n90VI
zC8-_t1!nzuY|8%-i-A)~a5MW3j8PKPaY)wZg1a9}CViNP|FeyDirI>BLu)$oHfrhy
z_^iK+F6*De<X$rW!A2U2gUK}Swz@|C{bgllry5(I)ynZ4@T|5{{}=ESJGP}HthTyW
zW|3I`LljcHOF|VcD#!w%oZy@{4(ds|wx)Tri=F_sMP%8NBJFzwQxOCwv9j~y5pQ;o
z$Jz)W2Lt)+)zLpImD#Ek>t|n|*2`?JnBTL+dylO!{Svn)8S-jmbnW#<U>%re4W|$n
zAHLi>RqPLUAFal)VzUcOf1P(IX_C_u>vQh8OL&<Pc=1Q`wXc611@L0##26;IZA9Xm
zEHVCjxVIkR12}(rUgGb$h#CD^=i}1Hko)Z}F{>SWZ0-1;q|Jryd0BY;&KT_U<;R#x
zkz@~c->|vQQHJM2xcZcB64smm$_;%K5r6t1=Wcq{3wjXSfiP<dgUoi^qHKZJrHaVe
zt!r;azk|wOj6^iQ>qk(BnTv$F{FGJK%QN(9Yn^SuLoxh_-Hiw8FBoMqTVGmjL^Z9H
zWltZ)Tji-WiLza5{Yw|PP_4F#U?8OJuV=h+?ii1)SEVG)o}c61e~+*Lnb5TG$P|8V
zaWuHE|HaB-|A8cP<4l5l<*LLLe{fBF&nR!NYaMvGz`i<oopYV9OuG1spXG}<f8XEt
z-1WEkAe;N}85bgC13^t(tF02i^dFU^yyb&ye<&!Zi+-;K&Tdc4`xGVnSjC5|J3*zy
zJ%&)mUNKUI8-BIbsC7wVmLI17QawLRu+TEBdf9J$BGQ4m6>L(ETLC0xCfbnm1S8Uj
zDm0H-R0O*@nd?q=L_q&CPrp{d`N>RiC@Bj7N~T1VDIDB%k|t-EXmXD)v1Hi@Zhb7K
z$){bKhj*<gH5jPZ*@LK|M&da3I(!8DHQ7q5qsIEsbQW<214S@i8<f7RV-QlZsyp&C
zkKAD)>_nK}x+TWjsAUr}DqDIlzX>~RpnN;7PvmTw`=yr}&D9WX1R_LsoVJ9;Yb{FW
zt`CNkCyAabz-%zbF0IF-+`e4uH(bHaU=t@Ow7hXdCz#+N=*`FYcf@&5VvXNd_=Qzn
z7Pv(I?QnGby8|sC>vHe+Q*C@50!_sJn7;~tRxwfAGbkL(jQ23;z$B-16|`|R><=|!
zNH_Az5TxQRH+QApX9!$rEb#O)5m|4NaO!;5@*Q`;te&_@BbM--iwBcRP9WNKg6qBf
zyoIXE?Q-)*@HZ*CkVs5HQ?}Bk1SwBuW60Uuxi)*?Aq?Iz0r~tI@+#en0Xmn$dP929
z+e4U!<6b2@7ram~wT2ZG7zArD3nEH!WW$9eh3qrCy@w|46)N$~5Z|;i?>c2pqbV4V
zlGw{eVWY~oxmlC!99V;}8$pjGp3GblcybBwSJ`GBeOR{VxzWHUfwO`~UaFTPJtR@b
z?_A3YLy#QoLa?MH*bT0RNTVUI%yes&4J3s_pUx6baU@DB1XY!`fotEWV+4gGO?5!J
zJNc=oK}TU-gQpFfh-($@<q_Xi-S30IB!kE=V8B<>$PqAz3SDmFw8SUNC3?5(hj_*i
zA4HReQmuH=vqa8`SkMGShSyOQKo){2K56rwoQeqsaVRZ%W=<~>KM<5{tg>bI0Pm}i
z92jv4D=JB<T4r-6D?DxzO_6y<Y!@n?VVT!jS&-63;n8+Wn02eXGA<6g0$X5BV2HZn
zc(IxY)xj@HfGl|D8<bbAE2hdeMo1q=GDI;=Ni(DDa48cl>a}$q*y4lmRA39?DZ^-I
zFC?SlqGW>r$<jb}g(S<%alfm8ahF?{Ut@^FCWS(~!I%i0D-td&iu4xp_aLGo0zV?O
z!oSA32n3Xg=T{cJ#;i-pVlqq_Y$~BITNVxAE)a*qZn4Z(ioTy;Y{ZOgtEaZw;b900
z-J>GOsjG-a@D6}=Xhzy4uXSaWu=0XK^_3iE;uK{IS($A{Tb+ql&2|zFaUTh;b(dS{
z1kyFw%QkU}mAyzCYtm(uBv{U4cRAN7(oR~DI7o`DIY2IIEsMr$+9kP9PB*Ov2d3JY
zKqdPB0shk21_`Um?18G&E2Mhb9fIyO2x)o}zyd-59bME$)v5C@fZ;|?wJ%!KU-cza
z!t168f7Q$@eo<~uTeZHtumY=+5b=3W!J{Oi&F39lYy=;MtTS)piswj0X3@<?`J~D6
zaL_1!=0d;~h-;LpYlzk{pzf|PBSYP<FyWNAvIxdU4`m=&pu7~5y#Pw+6~^ckv&7G)
zD-^J3WC*n|URVW0V#4bwG8Cw6tNdagbv@1}qgYCbO8Vk=@Xms#Doi|@%&5C2pAczR
zox%w3{muB0hDmpxdxBc<=q{$|RXk7dj?%{45iwGpLdw4@UL(Vd`;_fS9yFFn$(Bcv
z37d53)Z9oK+{q9bM!{7PZ62wZHI_-z4YY!h#4D{x%Cv2C=mtU~NN$b1O!Y~?6{vsr
z8ZiD?rX~tn%JVc8H<d9G<oOasHwwL%C*fxUDh0$u)f@RSS~8OIi3B(Jlo5*D88{5e
zi&{BfyR=bt%E%zsn|Ni$C1QwctZ6!xha5u9(Y9ZPngX{Q6YtW3JeaF2OC^ciSaiwX
z#id}w1H(J1rM&1t=M_?SsED8dU`<UPuZw}i15JIp=u~85V^KR_Ld_v2UIME&3`i`0
zzv$vQ>*iyb1m|`TNrLuMw-O2h%C@8IS=M*AFoOM(S_lwMiCF<Z2~{l;;oBMFR1@vZ
zZYJ=(Aaa?g8<<|y5T5CN8tH8(m@yN3LkaQ)vi3VA*co3{tJMs>R#Ih4Ayu>eU>fU3
z#5x|AExmQ9pJXRL4Z`#kj3Ary&YRD86!J32wwB`QhYozIpFCJax+(=!%j2#qb~2Y{
zy62ali*P4k5IamwaK8@*It(=dhKt+6hfS7kqjp8cYE@*aq<V|y!3<(#A}{E*IYDCU
z7I$j`;j?=-s@3AcAxg^r!=ZpO1Qj=-ySG&l5dP#LW)>bsQN@pQ<9rWgtg_u;S==6C
z3W>J8c-w!dy^Hq`_u9{lTbQndejml_R<bU@;mOQpe##*Wa_GWI^4xG2E5O64t6F}T
z*_XxC&E*(ICRyjIf?2|4=l-qcW&VRt!{3GNO&T72&~+dC(h&+d?MtQ*><aBMveKf^
zRzNs6`vMOw#cfgfR@#j)gwugwlD;#s6%|EkzFr&xze(HWSH3pKi`j3F?*0=alYI6f
zE9F(TSMiH4yoJ+RAHg>SM7U=QBK&8wyt=}X`P>v;R^j%x9>FqRXRFd}cQ5O6fk}iY
zC=<_5d(*U9<mQi`M{jsJ8bq>U?mN7jR`l)=qHmV{q`xz9@yn_!boNYi@m;A)va8!=
zCe&JMP0Lo_;H7~s=8a=*tfR7p>4Y7TABda;l4iD_?7%&4zkiH#T^eI<y7lnh<hHdp
za|Zq8Y^?bGlmR7@OZY)hT=O^b%oc@2*<ZWYvz~C~Vi%$!U`0nW1Sn50I?Ac%y&&pR
zN6Zr8MpYzXQ-0&Ga#11YARQOxbzsWxPuxss7^u0squB0W(nd9=-F}hgLD8~P-)ivv
zdF((ki9u1ygtZX&@nVndKeWxBzu5R2NzfkCSN`aT&qXo_I&4#9wC;3ttS?r_y%J2k
zm)r8Uvt)ncz<ks?icLB%(zH51b+rp;W9s9B+}P}`JbwT8Gj>jX$&JlC<dQRyfVj24
z#z6Ipuk*e+$sp^+@z7fOdvpN*CA#N-h1Xv#7v;1I{NPig<M*%@Wgl9J{e&zwkA%;S
z($xO4;LC(F=cMm_64L6Oo62?Rnk#Zqzk?y*I`gL5qxV{%?M^lG?%6TbazJzQdkVc(
zbH@E0cj}GH%Jy)NUHr4XbLl#xUr0t-YwoybHSfY&Pr7<xw3_eH?&LXnp|_~`PF88A
zlG4A3%6>@gSi<w-ov>Yf(!-t3(nW61$<c}C{!yayc!OKoA2_AQeLOtqPR~!M_vMh8
z#>{BJiu!7vwdWs5=JFprFFVkFJNLsd-_cTb@d-L8`u*JY)Qf2efeF5jynp#>4P`Mm
zI7rzBN2x-OFIcF$l(9-f$xW-iKYBNR=!?v3bfWYy^hD@Oa)Nq?U>VYNj^C7HxkLd2
zU%9OztF>2x0-=@RIS_gz5LD2m<=~a=sDFM;D9baCWsQMH54j3AW)i&zYbz9uzy$BC
zW0E}%u8}|@&6#=J&0rlU-HE*>G?-D9xV@Q48Ct54p^nTWWlacC2z(9vY(}WoS45--
zAk%yCc~mb241&-jFjWx}hC%V1)RZ^FOqVd4i*ibcjZUxFw#hV^byLfcmm<PgOqN1P
zwd=L122(yz(cwf{S+1%J?tUcbt82ZAX8<Actw0_X_Ljm!YeAvxjcFg2z#Py(Kqs|6
zk$A<}*g&4$fKP$Og<uqocrGE;IbA(us+-_knsYJL6ZPDP?J+U&&Y#|xX{m}g7X8S*
z?!H*5ZTqzSSg$~tw>^HM%wQp<+(_#f4|oJ!yK+&CL8dF}UbN7j=;BfH?Q#j+ZcKGs
zhLP!lOU{o~!6z~`MGh(TwAc!+l{@8{3oj&06lm6?!*3z+8s=&*Dc`JYBK|C7IhI0T
zormYF_u>^ne)%~r(@my1Jf7Wwb5Y@Cdl@$qN-k?N6Hd<?LAh#K`u{4gG#w_r(a20s
z$ztEt#k4KYYk)kd8iFROzQ8Z=i~L6T?FQ71K{(3lGbcC<0ID9|^{7yDL_L^Qr?t%Q
z940|DkQT}-SKsRbtxGz<Th4}5YdZz;^v2hLO_G?vYK2y}PE$OGt0nEfs0iBsy$Q%6
zQEoUN)<UGj(_-L%H&m^ehU#2Vb8ERjWQ^)gG*(r}Qsm=%V-gN|mX2$xVcqy)_e}hR
z_=Ln=z-;9)=lSsBS{{BE7B6KV-(a*p0!ax$PR5%aQ65)lFk`*}mvDZTLE>BQqi;NQ
zOG*7DiZh`D1|BZM9;aLGww%J7j;5o}zTPG7hl5KnTfL-M-giFx->*XJ3?E_WzN@(1
zxo|I0vyIgg@n;zXeWj5(tkGmq6oa6nqcd)BKj79Mt4Sqkd8hanDzlX{HirY%To9@1
z2hIl4o+9QHsv{zP1V!$<&P(0lZ)f=u0lPtYwJeD*@Eyau|GX{SV5qZ=&$ArKW<J5}
z5+B*)U8_lLiM!*Xi|2YLkXj~Jo<*F>3d;iYt>^F7f-LWqAHDR}W~l`6*%20tJPSF5
zt*KAL=zAJoq-+1txp@AgOa;!^@mS^Bx*f^-;&%jhfBL99`3wIvcZ(0kfY}=7?wC#9
zcWA{eV7Bt126k$8yD03@(fw}mf%eJU5q_lk&ILE|P49|-{O+N)yzrqfI@y(9cA<U)
zu~!JxA3t&NUMFRbBD?R!?B<a+po}Q2?pO!_RYWxb03tx;waf4AzeVTsbN??-n)Qa&
zx=C)E=KjYo)Gb3Sb^+slHVN)sho{1CUL4e-3fC;(iSs9TZSG&+JgIMM*mn)oqfN?M
z#x@RmZO%=frCu6;V@U?}^zF#e3A^N0MNQAMDxqc?^8dp2L3$hd8$Utkcls<^9i8X|
z6JKrawAKUm|L{DM70d?w@$2&LiC>*_o{wFOkH0?4Ie|0@FMV%p!p*f$vMq#qnSSyY
z*+BZGWI6t=L+uU*wO{|)#@>!d20;*kHY(cw!_Cw&>s%LwvWu5*Sn$&G_P{J%4RIRF
zs=4%^9;GWIr|fKbFE3mCIt^p}Cbf>?fOn8x5NYGA2B^TD7mV3Eap93iv(_rwpqCBc
zP1l)qcVr^7)g|gMF<VQ68aal7mD4gv)O>$1q?oNaMa$f6%*DUzshx}s12rsp?B{12
z&bz6`O!jREqiXvG_rCp~zR>&lYapIU4VT8h&h#R)28)GXi0=23eDBHE!IuvUC#P8l
z+gY`BX6l82PLqaho%%)uWshj01W7Oq_`yU7)lU`BN6b8rm^nr|8~Jp~8XngCR=#Bm
zh|KAPe91%)Lfe$Rm%fE-3nh5o1#=@KQ-2(<S5TuZ)pDOCLhlHlQjGMZ%=`5n72$O;
z7%c}YxrbU${i<}h(|ofx;Evx4E^0PniQfUHlxx$;KhN$XaNfScylf>SxC`)2rJZ8?
zWmNl)I}!HdLod+m`OLGXk{BG&h^_`N4~r#!Il;Rr%L&w84412zP-^QBX`fPySWWPf
zdBCNbR_`I#Pmr&6gc*3Q(p9S^$w-o<teP?63`$V$Ga_PV2&K3ujH2PqJSuswfr>U8
z)GM@zk~GL^U`KPb#B!lpuY_508Ve(gC73|gGrDj{X(mhMz^r13V>L$w8vvn<FFJN!
zrB8b;xo#)K&kf))Y_tlHp3{aXj2DNb&~+0qCEyS&ZbI%Fpxlg?0_A5~7@#`MO~_V7
zD*~5Fk@x@x%4YTSmhakyyQ|gO(j-gTt=C{}r(_qYm6Yr}L<K*p)vKO@yk$iooT6`y
z30HN%0jGkIMI_fDq0t*Tw6dFKiJo(=!yp?`3oZgHQt92{8r+1&=QB#b3F1a*!#hMf
z*+_PdPpP-%5Y8d35rN`Ot=6GIZdU}}MQey2f5A_>_56T1u0!6@X9?yK9jb7jLsgyA
z{`#UTZ%g}ILd`B3wk%*<uV6+pI~2f%GRopz1B@@dT)UiDzSve@L6<w(ah>cou<B*C
z{v;TSG&@at9*FF7NINvkb1KUS`!6Qhxh0b>thhe=aJf^XKha;#Z^hSZ6FLUqjtw3+
zI0~U{0cWG*{Fh2g>j#}XsXZ}&OxLwRJiv#67vdvnl-X+V7C1aS*`3hYsNu!ze`QUx
zu)_5iEov7Gkn!5wf%wVLb>DgyXRGjP*AUQk3$`(q+e)jg#T8|m?xXWAu-4$G`gt%m
z<b$HDI{(~{x81r<r9GySrCct~PAxCdL)`zd+;^8z!8%K!GF#pI9uLXXPvQBUBwPB@
zk#TB2Q{x;Aon~N_p>A}2^t8Ne`UMbTvrT*-Y2^(Sp<Ju2T7}pS;=r=!6~R4!x0i7U
z3XpB#<*{+NY%Q{lvbExu_bs@)j}DP>Ai2n7ozBf4aQpLH%aaC|e$qXGRnWCpyqf#T
zq*~-vCYEhXzGJ#fyUzV-FD{)#qf7flFaRXz+ILq+xX5h%y+oRdhhO0a?NE}H*>=~9
ziIrBT|G(?kqyPKA*@*7Lyn2PPmGBl=>W+QXr}-yV-O>_kM<+<3gHW=g`@-5Mznf#>
z7BFW2mx<Uq^!to0)22S?G5|8yk$Kc&;qL(K${MUoL^FzKFySMv1F5#PJ19e?_99ae
z%Q{(%s63@3QAFIdqHedMYScaX|FTN}mky*f-;Wn8gg*J9DR2Xz%GOWAJv$16(^riY
zq><s9=)9QEuO?IOg|ToC-}JOh%s52ZYfF$^E0M2(y!FPPbeBqG+J~RS-4!Bpxt)Cf
z{0IWK*FK%P<@Ntv37TUMy7V;F)ovVM_MfuZgMOYi*ZL2aq;B>b6DWaGL$e24DE$rY
z<lH6g6)iU3^F>Hh{OkTCi!uDP&!3zbarb{EaqX+0fDKE<#j5o!y9#FG^3GGExxM)(
z$>LV}aNWr4R@`d~SI>xEqP+hNIA5Z%th)K<LXYN3d^%YZv}P5DgaCc+PVHNBwb?2T
ztZAm{pC|JNUKwR;!Nr?-c{1@L5_sPGuKX{R&9lVsc0H-JCm>!!+jx~b6v)4j1)Y-R
zc>7qZt=71|V0&8bYhv5{Z={Gx$m#vtQTx==42K&v`}z^>eq<f%Fb|~PW$JfbE$*8k
zrq}3X2}s=E^yjWFg5C<<r6-n{{$#Z^UPD9K0<jL$vU~m-H>6u~UF)OXTGLpWFb@;l
zF=dBnv`w2T_uc|SU&dVK=uQoIo)Qwo`9QbkQFZW}N}0HMBd|-$+IcAhS{w?(Y50YT
zXO+gUu7PMP{i4)nGSEpAzKdUM$tOr7mKUmRA%)NMEH#J>_9C%*YK+pv^WgLlFFU{j
zcQC|~Ii1xuv~d!o#4~v-*|(vqQQPvUBWssp7);a%Rl~(grQO!UxwMR5-N5YV>&rIg
zJeU_YC{G9H=@+9gW6Qct`Xa&gmx*^=jFS<&y<<wV3y5=%MlGq@=6Q--kfM=xsE7H6
zpDTH2jS$Eg8A$_HapYgv>RI|EiO_Pn3_<)H-O9YkP531S!P-z3r(qd4a)n?!2&6kd
zX7;4d>Neg_sOnUPuMM_#|8d*orjojjv*$!pXJyJBbCYvInyTd)3XpgbLXY;aNlVku
ziUx0Aa}diI!6YJ)4EXzUBJnWL^7VbXWa*vjkW44+P;Jq}FpI{WumQU;EZdAu*xd(R
znsjucPY7#HU;PZ@>d2yKB|pwgNTrNJZj$wAa?4`5*9qM2(2S|OZYL5Nh&LVYM6elO
z6>c-Kl5;C^Bh0Iu<<iXt3ZLiq35Hp62S8u8Gbm*e@`z4UUG!smOlzsN-1-(&Wm1^u
z=eqn92>doxfWiZSz4;{cMpf%*#X=Kln<@<z$3E$pnzY)3YRaX&){r3w1E_>uc|9?h
zB6KIA2uc`55@D50F|yVw1^ZwI0dn!uV1^J|p_b*teQkIv%{gIz4yHmBV;fQbMmWhT
z*V(r<{%}0!ER(JGc=rQA3zl34fZym#L&0k67izP$xILD}VS%;Gx^-l=HEb}`X`${d
ziQmA~zE0EbyE?eNOI4=rJ=3x;r)_u#87e>EzA~OO8J|0UO^C8*eVu;F9ZndejkwWQ
z-U9AUD(mEwD~hMx!t%G0(=LC5EA>vjwEQ&;yxuh$%kPoA6McQ<0_@n&5LZ`D&3CJd
zWbVZea$)ydUmSe|A<FFh3osEE<ekMC3~Eb3Wa5no2DTL!Ur=ol5s9eQR&^xlUF6VP
zKC*0~jgMW%D#jze=3$I>ywuqyT5bKQS#@%@05~J#Fs#2jJn{G;JH0fG;$fM*#LJ^g
z7epJg2Fj}K5ZW)lxH7wE(a1!)8(>B9=J{2m<@+CwEUnQ0EeUb_XSunsoILidsUeEb
zft%A`@Mp)};-6fw*DW54VLe=sXCKSwCl0;H;OVh9<g%ALoex~OkThr%$B(+tX|1yP
z?)R_eeCIEF@jx?<da>FaT1C95b)YvVAY~vNeP1c!$1hH^sDSh^1jJHdqJ-7FluenV
zuGo+HB$_-x9S1E_1b$6cTWuq)Z4wqn-()d8yu7?;;=q9$H)iLE+!2E0^NK!7o~xx9
z^WrsEwsM)R9M|L8pSs4~N1V5*3C%m$W30d?QCd3?=E@(k_B*`}wk>9ZAjGLO-t#sD
z{<oYNT2Zh5nRDyiW=j^RO5*LFux!8f(RO=w-MPr!yplcWx_%5bja<Cw#-7iw?qIf#
zK6)wh85pfGS#hU7^LCOy^Ex;E#WyEjHn+I6I#otHJ2CyfpMD}QS6lz>xn}Fg(d&FK
z@odkxlLuWP<@TUGu}ON2O6*&0?b;VCv`N_PHcJ^x<Bv^9jo4oQdmTgWdLi2y7Tu}G
z^X{3kV2GE`<Mz1#eIFwjT9Xl{JR6l>wuE);9`ilS^;B)Pesz5Cx?DjEjk0cL&r6z7
zwpk4<j*pzYa;;W{FY#w-KOy6ZDLtlHI>U3eH!|v;d75tj>qojSdlT=%FK7AK*-4ki
z+eh|>dqcbR#5FFM%?+1<fMhOvf{RKS4wmJsQ{|x4-nv3~T?T^4`=KsaiGv~49?C#@
zk0>yoRySm#X;LudEskHkW1ii&nG5)>P-Yv2o|f6#V_;os?o@@uvXL536`8Mf3AD*T
z3!nzU?yb_F6*XZQ-sb8p`EpQ{*JT5g$CUL38#qqqh)hd?2wMM*Cm~AbZ8QX`jex7F
zZIxJw=1QjeQoKuMIJRE{;;0xmP#@mNQXZZqFALTearbpVg1%<3dX)7kRso^KVTqq{
z6H>p8#S)L7C^^6cXFK9}`3HipDRLL<a>oe{L0>=(MKgK`EPFH;GYpdwGJ5M^PaK+X
z<ldP!{8*eT*F7t;9h`{xst9;Au!?(Bh&>iVFIajM4UY1KnM|Ur@p~$TN9q<<UE)Ks
zH|FlBi#&%Sam*w@Ht9vFOtOT_7}P_-Sj>V5x2-tOz1oWq+u=dUiazqA_-m1(JYJFF
zIV(>E`@KpK6&j1BtGXQy&~3!PyAA5-t0WAs!#ufQM&J{&N#HO!D{Ixo9M3Q36`J5r
z5cp-H+Z{-f#(57>EL%odKs~a7Wb+=~*o<kY%TJ0*n6h@=YRX;d!I~WOkgXZ%kB^a!
zTOutdFtluCnN+sH2AXXkkQPD|y8!hzKx9k&1;eXX)DeC&;@MWHf=%)SAva;z^IVt9
z60|1eTxtFxFXX69trL?I^^>COQkW-@vE4DuPX|ljAu*wqI`He!<KG^<&|bv097Q13
z#R&;Fe<_EEph&O6jx7D<b<P~MXoxM2yDRp(k&;Ny{R`<yF~$R!F@H6J`7&;(Ypc^Q
zMKv|brzjsZ#n{V8#U_gFxRRmdtl)#R{j*U4HHgW2%WM#46O_HzOEiO`>JO83reoIc
zU)e;qW56rs;mjQ<8XRZ;;aO$38Hgx{WG`iICcfK^#)nw5WCxgAzd6XV#i%`R{zSNL
z%46A@`m;!qU16SBe~5uWn#?D!N^)(^EbkNEw4hWhcJ4JyGTL<yzB9Q6BRyia#-zAr
z`8I}+Y^a!+)TCnOzO<5Mo~1Nons#?HT4JczPPI71!3?p@fo|D76s&!1!h)@s?gGos
zy|r_dTl7D$g-DH1GM;#W3tZqeMEeyJweld3UdOZrH~etmB*}cbi~u3cM}C%xmxq@-
zllXf-u~1?#?TRC<Z9a)3((QmXt1!2I1$%4nv~iNrkgZu#bL$OyE`2!T8!m~(1#bUE
zk2v0Y9BG|woX?Q=0hen7>E3^KDO(1=;j~*V4!&E_cx==BZams@-ETkk4BL7w*Kw{f
zp@+b<@{<b8avMJvMm!h{*|ST|ecu}yCO+WOu$0;^foDJebr<7r@0pyH){osal8!B1
zkjAk`Xa#YegPro|ulsV66c;tU=KXgENydju^2cwUc3z|?0uXEJh2Qau^K4mx5+&a*
z;E5BVTw7Gti=u#*J!7wspSqxBN(;nzWny>N>PL7KcbA<8eB~Z(5{1{2ZMpP5@}`9`
z6c*uP+l=@9kWad8MxHMm%IuUXv;4@!KAcg^y)M^OlMbSFOD|9_RA&)LJUC}~gvBGS
z@uhcE%{1AgT;0q)dFUKyG8B>l{wkQ;=Q0_bp0~9t()@L04nO}pd`0!j(GY&(zfRpB
zAZ>}{<DYas`aM}Vc8d$0z{fTo8%_PS-<5>$xeEtB^BwB~;^mGU(x=bZL!&?+#G}_G
zrgY(aU&QuaJ;Q*q(bDk+TOj0_u%38NrxFy)XLh~0y41dcGydjWb0KS?EZ_!u^Yz5M
zgD+%T3du(}Qa1YTtru0rVVzl2H}x1hfSc85|7^|i26w`J;Rs3ql4G>vXCL?F1EHqa
z%?+5XkDui8E1fsam2@$2Ci2T}Npl?|Q3g15P6I<evh{``oc!jUwnC>Gcgf4Vqu&0U
zwZuYaqn5jtfAdN{Q8l*sR2tHl&VDcL>>sTKw-5(+n}KeLOkCr^H_2h#v;{ojd$-_*
z43?c(6m_?}^Q$|6XP}Vhz<T{aSB$;wNyEoGeGcW0i0G>(WxYTbI?u!`XL3eQ-L+Z)
zOw?#9!=sX8KV~0SwPw@@|DFK~_9ed|APbR#smrZe1}zrG%&`kqDw9mo{cQ!63pr@$
zEl8(J*QFtG6Diu7m@P5EHSnM#{}gV>lK8YDTDQ4Qs;=yP3JndGo$}rc!EX)^9pdYY
zJYl3eLFNj^Di*r2(n1;0cMa(LXc?ybONZQE=_9HNh6CLkvviE7NG@nOAI{Wc;_H#e
zni>VwG)HVOam$kKoG4?^^{wc3_}n5XlGrMO^B%8YHJZaChGETWpl(v<RhvG)g{O7s
zly{MEO;HBVe>UaP?sW;<ocIBmdw(NDJc)bJNLYGL-Q#OC!B!k@w86MgoI2GAAvw2N
zUAiWU;lK(ZQg2m<)Fnt)HEaB-;q5|%@wZaCW{kE(7(oN`cAd8CZkL)h50Y6vYME+^
zL0Jkq_)(B-QhPQeGtE-BVM)={v5jivhs0Z4tQi`1r%T7VSjP3pdsbrP9aQg$t)tQm
zVu?{sX^}0GWn=HsBR*$V;<-v>#MZaFEG=7`tYhm$s6hfeu!rb9JsfLTQl?v=EuB0H
zvX*X3{JBB9ACw?+F-dBgIzT(3gV_NPh^#uqhKsnrqsX?AOX%&ubT%FoRcD7cDh#Nw
zSw62a2~?(nUyt%1a|cIZy|4`~y93(iHbh7Jdn~-Ac#@immP@QSOq3l3tkvBDu{9@Q
z#>E0GKdGeyGddacWBbq|e6{G3K)*NA?50V)SgTm1gF)pv7uZ6#eZ;w><Xt0Al7?Z+
z#?8<BjDoWGcT2yUAz0A2N2YE4b?kTo>5Cwb(aZ-y6u~jn@`HO^H~a`nsGt~&OFD09
zqG-6k6@Hao?0Dv;AAC#xA=VaRc6=|&*0Sfrb5t-p&Dz)L96lg^tm3enGZWa>>*Ipn
z7+0Qox1}d^H;HM&X@K4{?z3Y1R83^8<${ZN)<;6_-anD1-%gS&=6Tk=IoN=z_2S69
z>%MI~N!tf)boUGHQg<}#?q?^!C+UArW=pQPd3p{WyF<%0MSw5>U$r#1zDS>+e}VR*
z=%Jd3s!N37eU!uAz#|~2j%3Og@pr!KgSM-{if9$>(WBi;r<eCp^*8fK#M*F2F5xX0
zmZAoNW&6OA>l7DeZqEn3c#%^#umFg)?6EDbaOob_=Vrf^EuRh}sPm)ge!W0@HT#HX
zw39QeU+9ugU0O+2&^`ucn=r7wX>4lj+UfFc^9^PUNOi|q@6M=0;?>fw7n}VfE<WF4
zp>*t28!K!)#{aa>EnM;gd6@e<%dYjFFSxj$PkOAKp*AvvxtBQ!J#5`?&L*z-CfMJ;
zBwxG!pL>6L*(yv-cY&l8mx;DJ!c-|<g1}FeeCFaTMBEngZmx8Y+ky(#drg))_SBi|
z$1Ca;-L=N$>6@+cq0~NBj+5kul5RWQJA&?Tf8ZOW>Nd*{ff73y$kw0w-MQe7T>GM}
z+>#{n<Krl9!s9vh=xC-n6{lB#-4p+S3REWZvLC5%fBfKDgJ#e~4&8=B09xy~H>U14
zE;Rea#pke8X;4?Mx2D1Ym&j~wW47k`lWFpV%vOCFQ>*l?;=Lno?{9y{N`B&(lc3YS
z@+Uv)0@+4B+roX1WNWi~VtVZH%zxj#SFW}ix5ezPM^c%s0r3Yw>K(l3EGy+|BRC48
z9hM0v!gYF}mmr-C33Pk{4Gbu#OV(*FMZNZL-(OQ)3EIb6HKofa)VD@#2zNf+S9I@9
zV!Ngr#trTamdPs|s#RIbWF76pi>8QYFUWNZb#1q9@h&$)Cb|1Uax3Q$@acpPP)=J1
zMvmbCMY;6`+mbU(PbKLnJC}!_Lx<pPB^k5T6XCsm0JGC{*Fxgm$tKV4_tO!+?-~r7
z279FcuscsomFNbTGP8NCJ(gVSK9KlQjd$m(ZXv>aI0zDe(IWsa4cTf?mA)p`u2m`R
z{e@7ok$Z5XBk#j!blR$Tz}q$GT2vxbF%~iS64f5D0n09;N8heEGuu8_BGZCpPpC-X
zIQGiBfE)EtZM7(E8u4}b4FVHSDyroSWr~ua`3v!80Yg-(4i423KH+#5hg=+^z^tZg
zMIObLEpamxAK(mdBY`$aNW|?GQgW)cyozKnv`StO)*>oRRDkF8YXfqpQ{@-ybUL6P
zun3I9X79eA_AW1}xTd#^#YR(v6vcDBu*0QHgl9L1CUrBkuUE;LeW-~$MeUn~l}Uk$
z7`f`kbs;hn6K^X?f>Yi-OWV|6#_V{dQ*Q-s1XY;9JzSZ{&Vxe1t;p#aeb!b|$uKLO
z7F3<brE_u1KJnEaV_{MR6J0@D2;~-oi`*2pQIrwh(;gH%Kr*9<+l>hxn=#o;YN`OW
zuo=C3D3sB~7Aixl!htYVx*Kcg5+eBo*lrawS5pjh%e6!LS`T-tVk#(8vQC{gLoWu+
zkn`Qi6~#ur&1jv74~m*FHEcX}gxd|In#A`qBxKqw@5?k2Ht?0}V(sCUrMh@XNeBkb
zR)JhY!NnjCyqp|6tfyDS$ztL#he!ZwNML4WgVI-Cx&WXOw89PT_-!f6CKAh+YJy10
zOiJRI(lB%CMiBSgGGrMTc*S%nfm>yA8|pSK9QFdfnOe5@CIK&u(h{$tO3j;OQg}xQ
z=V7*n+H5UKI=GBc&d!GNVVY;hh%Jj>lC`38OPFo!*0Q^eS~!fb(fcw<o&^H%6~uIL
zgL8@6=4yQrvo9*+xiHPUtp>?!JCaFeE71E+HvUl-7nwkOBeMU9MQ*v6LRm0h6<*1c
z$evgr+I6VQY@^jJ{>27qG3GBx9wwZ>oy+C<9M^8{&xij<>893snigZx=_Y3tkWS*A
zYu)4<RlgJ<9sqeOT<O@f(waBIvmE3kPi!X4b@f40O%+qvGk*HI;afM+zbx!&XZKy0
zJdT0?d3Uz8=I%XcdJEazN$R_oa-&`<>VqC_1czh^M@(d)Wh{od{6Inqm9G5RjUq*B
zlkkY5UfYpOym+UoY3VD50ysojpjr~cu$;8wN5xns@~Hcdzx<uqPgNN2e*f}GyNOIP
zk?aC9%17@Rx;;0IpVE`dbN9(`*!u{5z|&0aJbtInVW1+v_T7Gd-y7$#!uGn6qi?o5
z)gxJS@4ksy=&y~2sPvL!0I->qzWk|K?j=$FiM|@g5EHXC&bY8qwj8tdr&;99vXACQ
z692C^hvk`%L?qiYHS_%4(RS3v`<p9D6z{$3b({yiuho5NcFz4lMAUEmL-xad?TGuz
zoqJj_kjVgOEJ4uy$6DOQ<CC&GGPSE}&Ro12BN6e$r@0OT(uTitME#3B>jPn#O&c#K
zqij_dJqti4WfSk!dS$mQMn!-2*M~b}HOeTy|E?nk;$x#;Uw&L0W3GT~JvM2E867nv
z(jp=pEvWok=%vg!ERYP6T&t}sFN|{Msr8Ywegh#KO0${fC1nxTetS<;3aTqzJdjV8
z+nq66<L$|n;Rl|+hP@6P{dLi+jF5idWBG6W#&<-{#-2o?eb(rUMV9B1=6kb4<G+`u
z@s&Mk>)7Mt%qJ!@OAq|>R(|{=BjGuoA*0gS?hsA<<kL5&wx(>$&ZVx)bm4P$t1&P3
z#O{o$*jT!EniF)5x?ncRY&FQR(sXb2KWGTj6WIh>8c{SBWeM^4aQe;R9@Bs4iuBpb
zm$kcPmd0h-+9L16<W@A|sO;JJ)y9ZB!)$~y$<~n!lFw`I(LK9wvXldV?zs$r1MbNS
z$)<XMWq-izl~Q~hoi&=#4sb8c*1%SlZyj-3e~n;J1`~{}f5<ZGx6@Q+>j4#?DaPQ|
z=GY?tdH9T98U9v#%yrX$(3nenGp6BycWHN31seoW1UY9y`BIfuO5rv@J(_{9+=0#}
zLTa#ErtoDIr~S=l6R()MaaA~FiqVaj{CO|?O{C`rJg7)YYclmbb{17SYftPKAQBn4
zBRbrxRDO(|4AY`+VTsmBJ6J&?+)+r2vy1m~n0Q|^Pq#|KKqW*X3<9O0HmFtw%Li_d
zlv8Tell+haD?=4ZY*^uDk03ZEff4V1=k@AqDv}6EdI?FR1%(;}4D34>xfsZMa~kFS
zn!prWs-;R-F;r1X{4AZ~xjauXrZoNEqi9hJ3MyqNxJz}@<es?BP4yLl#ZW3w#acY<
zyo>zJjF~2xlvgI|A_9LL1t9w|`-BQ$at06sz`HCmYYn|GDJx-pD%Lz?GF+ngZ!Mkg
z9;MAhB6uD#7)oE3j~l(kiyn^KbFGa#Lkd$5mDgH5115Ea-~Tr1_(nPqPk5$mB1G*3
z(F&m0Xx1Z>v(~DFkq2y_T6@Hb-W`gK=spJCnA0eGne@n{P1nnSDZr>Yjvad)ut&AC
z2ad)a8*pi=5S<tTopLqTF*Kb=MQuZKSkVeOkil3ClhkNbKT59eSu8k`sZ86GhNzt&
zi8h&_HUY$-E9qtqz)w4ojZ;i)%tB~Z@c?@gZS29Mt@CydM<(5+sZ%1E0clPAsJ0<;
zmo9+>@`Prv8vG#1LM2bnY~7-7GRpTWxBm{PvJi(@v+=b@Zl@RM<u2XRN>_yNz3AOM
zq=<_5(j>*^E;3;0q*g+#J<bK<xMLvWFWbNqqpXJn&3n4Z0ChhHkP^E{16N96pw9p}
zzSRPVw!sideosw%nz@^%sdIFvU#_*qqo>flu4HTyPU2`GAHV(^O~Kuv=C_6F!8-h~
z$x(-PbR~v!mD!rRv&#yO7J9lpJdVZ%m-ROkeWPW4((q{cb#!0)RyuH@`x&mkHD`h0
zF2#GCcdVG&q`Hz^z)anL&Lu-g-Hj;pGbvX7o@6cl*GRU?`jCsPwk~qmFza~#1Wb3t
zRIxfldAlxL$sP2)c38IyZc$a%g-^0yb>)5y9_u5nlQc4BNf_qZ_-TFI{hj#EY*iGT
zn@P+ky^mjg^!YKj5*Xpk@g@4XnJYPw$|aXFA)g=c(H$V>n=bXmTl$qJ4%>nRagTNX
ztnMG)vT;6_$@l`%l(k;z67}vNZG_5fUE2Suh}T$n;uFf8<r)Zi2Kl!#AaIc%R*z3@
z6;IMWRd6_{7Rj!nO)fXyl6NlsQKJ&&?qJ!jH{5Oi>~hZ*&Jn1)GHLuJf8<WyrnLVK
zR_%W?6_?2*?z@TSAv=-d3qKP^v?9oHJ*m6pqHyN@&wz#8cAhHTZgBjbpK$4uZ>LaD
z9cYXNoOs7KlXzx^o645^$iz(`j`k*lNn4cGFTXI_vP}|Suhymg#90^P5^IDq)b7Rp
ze){US%(2?K<knBlyZo!)(Ymqy|Izk7aF!L<eP`YKZui{jX@)z)01f6(P1E2OLedi;
z1xr}2ZrY;3NO{O$VFx=8i~%WjGFl-U+Y+g68fYmpZfmhJa-`iSjFnj;D<iG!C5r7_
zM&OUu%SSuW2gR~KPCgxfy!t5qqn&u=6_Mp+zrR!WzV2qG`?b8gr~B2dKc~()b*gUN
zI#qS+e&#aw++E+lt65y_q~O8*^nyudtKEtasL`%n;HyZXO+-bG1S`watV%SE!IL8@
z7YQq~S{!dy)FBFp2{pPHd9b<uv+QZ#N0nnyF4oM-T>ZqgHSxOuwZY?m^_E2as@tNn
z$eDz#_jtPB|2w6<9(vEGdG77Iu(VIZocN{vw$x+`#Lr&#Dz`u#cLVsl8i9xR-{9Pn
z?atpX?NQrw<vo?_Pf!ZmMxchhnwNq7=ad#ys+mF1c%|v!u3B`woC+`BndLo0A^G4}
zU04fHxc7JSYH;_SCkF4>@295zT^Z}obOO)g(GY|JJDcBb%vNiC5^=2mX-*#(2BzIE
zL5Rt0#lzvZO}23;Oko`Mw7FypctSD7{NcHI)_V)@o5*aP+qdfCKS~L^bDyKpK)tH}
zCN>#@mQn|%2kw9wjKf34r`|FcJMtQ4{jPUm;?%wcG64_LD?PLSeu=zm=<5-gKj`OD
zj`jE3wR$4z>6wl7X+LJ9_9GIUqWQ*lZTYVrMiE#!uwBd7_AKYsd{`ViW%*suI&hBp
zdRuQ2W9vOGE2q!T2K6r^=@+J(#ju3BvkN=bVzAY2=~yAa^E2-lymkpam-O^9^m8Fg
z0y_p=8U(&9ogmLu54SaAOStsjv2MIum`$=S1Pa2PFoY-{Gq9|6Q;Hq|JWVGH$LI;s
zuso9$KJ;A*whhhFc5ohRn=O5Q+l2d3IvXY!OX@Yyua`@BPyisDjGs^8ejtOw&B|8J
z2@J%nf_s?gTeyZ8kuww`u^ZswO!FE-*y1x*!<gN8sGbBd3tRA2HoBIe5+!IQR2R(d
z%DCi@sAJA3G(tVM*TsalD|fs$y~KyJ%C{M67tCAHnpW_Ih;32z-GWERf=$Amy+i$D
zwys7SM}s)oie}l*?0~!pxIveRpm4dzMxyLGympW<Rw#+@<9}4)?`l46l@}qu+q;?k
z9E4%1yilThbIt&StFNu@dEOo-)P*in%k<|2b_Joyjw<~|hA6KXd3kozqX+fZl#E9u
zBNh$xO-^o+KxB@xXT4)+K(xe00a?(aW>Gs6#^B?XJHvpR051rMMhn8uAhuC$NvKiI
z44HwR^3UU;EoD)%jJc~|5@<LDbF0`EAzLnD?#^?Ed^d}rVec%mm#ObzzB4=p6UM>h
zp<#&lz+4S!BAU#`YvR&Atr<LCp)BVsz)%i>z%(8Rh;88ts>@4uQC#I0Xo*JJN~P!(
z?{(HxAaQ4SiexVoNv4g(VN4+dqn5`cv3Kwo3CC46jO7u5D$Niebr?lx%B+Oh2pg_O
zQJaFJszXiNjI<sp7IP>nQy@4Bj4eoG0qR_X*Z@TcPyjL?NRT`v^U*!)7Nb(AZ$!rG
zNs@W;qJ>;ZBViH5ppA+u0&qy>a4-SHq;kv5`6@=lCsL^z)Q~61#u(DfMtZf(i)|ni
z+hDY9M;49mAlVrEnrEr^kWohy#2Od36Cl|HCF(Iei#Y*`G=wAgVh4xy3AfH~G<1dN
zSsR1qb=-rY$s!6~GcB6LFNv;IP}XtW5rm8?YMoJ1J~}~|m`<em^5;Pr4aOF<jCmr8
z4t;0=7m2AnylO?lqL@f|VzIWtWIdrI$qa$zJjLw{k&g3Foor;&(;;K7Zc=xDzdFt<
znXw4PJ%L*^KS*0$bCWUVo;6cQ_p@&1_L1ifH_7A$G3S|Fpo~HGD#v}PcPX{y;1205
z?+ZmWG6E!-XdS1|h=u<yX!#LYc1#XiQ&G2cZJ@_@lus?k%hN(%9+fHzHB}29i7(|w
zej^}QdM$TI{pD=ON%X=H46zgt$06*Jqv4OylczbpzJ(#w(6W*wn#jT3M=3xpyksCo
zrIkWze$<{lH&gK^eIurdFO<OVWhjc-8ITMFO#$`Ihex#jzl8Km_K;NZ68P4`Rf<dn
z9ePp}W7WdN;4ONz6G6!-gtvKwV5(D@qVq{PQA!sUVT9o~CQl0mdLIJ*`C(vNPoN$d
z8U){9%r@Q2mK#dX{AiYs>U^4?t}-Ws%BcveI|)?a_#BUZ2BEor=a<-Kna9J-vY;o2
z?wr4vR8TpuxSgRU8AR0|Lm)`adQTMn63!tyzJWrQGp3+K!fGC;F@VZbCF}+3O2(-@
zdSEh55hQ68)R5DlXrRjE;Cpw!J<~)1wp9?@(h_Eg2pa2Z2~LHKc>xoo0R^Emo^(az
zG)aX<f$oM3!fFqmpRwawMf_Y-0<=|H8Ys>T3A#E-X0Zww0gnfbIgLY94wqB?Y5`H{
zD|o!p$C^V62yYME^HHg@!DU?@Y(|(cgc^v=-Mg!5Z8NoGhT-H<S?CsA)PT9CfS1!k
zd4Wk!fj}I9R;=oQyBoMnNT|8)%fsDrH5b%2c$l+-^=4y~NuxAahpLuu3xFamyQ;J9
zrAwyQ<?aGJx)0!mG+QO^6?RkFpF25jR*fH{g-(cVu&1gQBWVCu>*Te!$+)WE3HElm
z#;lqjgP^BEyas$!YcWvIKN6<gbWwwa;aIptH9{hRXV;483wA{<p$dEG+vG9wq{K~e
zo4j;amMthQ^7H(52P$dJZ*z&!nt+=X@bF%d2cXs)h^=SK)x=Dy*b;wQpkk5<wFibi
zsv39Gy2;-SD_Qi7-ul7DJmVN%l0hY$*JZA-36Z#p$kSA>pC;Dxv#(wFRgNxQ)zM>+
z_f-B&LFU8YdT)^<9FqejmL1U)-_77pru5Rj8L>HKNB=-~<I91sJEo`yTZ3Q0Q;B61
zA76j3TT*1+XM6bIjg;oV!)R;Q@ES0ot~V|Q%A~g>{;1<Qfi#cqOIcK0cJgA@&rjvP
zV9NPc_gg%Pc{k73w<r;KrrDXkxq+mVGr3>LtKs$>H+}d6!Wq1oE-8k<c`=mfRpr{b
zlg=0Q`{s+W7f3E<rkPx=!o;0pu2=qCRfUC+v%$${eDBdZ3fF%GDnCsd<z>af-|XGo
zPmxhCMn({(lgh+uJBaS&drG#SWqG@nHpG-ZSN7Ag5w5Z`Hit<&c)Zg7Cj^jyK>>^n
zsfgFMR-7u2_t$0?6))+kmkJjZ2y*tFo7v3t6Skr4uVd)`)gH&~FdDp2md?(2^{vuk
zj5P+%R4I=1_T{#=aM42_k3m@Z8<<Lesi-ym{V3}Im0l?GckNHBr0a{{og}+exI4q7
z8|Mz}{sh_<V)3(v-p9Ogzse(l<%+ESV^-t(JjjcE=Q1(z)x20%ulM1n-Q3`gM~e9D
zTe)X{Hgo;Iy3yVBBbOdv8w1pq&*Px4pIbQcy3f-L|F`|cRQb|PuAX^i<sSXfMQ>b2
zIN1$+9(C&5J}%vc{-pmFtX}RTM(Wp>8FmFG77DZ4us84+K`HO>OxaKUYk$zI&$2p(
zXQ0mMhiHzSvr6sztJ&M>UFS!7wl$E1k+8z3fR(R3(as`GY!RI0k~e;meQIhYPt2B?
z7a?}}t(|qhSLFxy;fphGk_qL||LI-#De6H>OuK;Kp1pF`E&hU=pA&ZK+xy*xERVPP
zc`apzyF(`{yAzClpxF%3LH)o#&D~eN?qd9jJ>HbgmnglBR;TV?cD37A9_+9|_$Wui
zK5<~o7sZ=0cl?W;@p!9FzT6F<-14g1XyWULB}F8N>GFItGa9e7T4)kSUDhFLaPKBe
zZMQSHFf^VtbhL)hRaEuN+g;Y|Ka5w?%=AXv?jeWmWwy{{Y<ckM%Z?9auh9O({va&{
z^|bBLo&0Tz^8z<n7+*<iETHg7jnEChkKXDI_r`7*KS_f<GNlr1f|Crc8NF#KDDnc}
zbJ@e0@97vYZV?UGf%;q*-2HRezBP`70zS?{PHn#WM+tr)&t{5S$~gCF@7y=eD$2#T
za*Fq#<ng?xUt{BJ<=F|W?yLHHqfM5i<7T$v@3M7l&9rPm<TO#6v<<)Cj6Gz4f>rRK
zclLD>NC{fh!(`Vm4FS_}!>Y_9dFS{A8qERCY8gx@3=~ZF<>q4@fNNiKi|SjvMUHY{
zRWh@@0p7gPIwB}}&7USwaK#`2Wz)SKgD2YLRfOjkO;WnLl^l767x<NzlQ?kk;|VuO
zO#JrXn<O3MCOBP*>lTmGV6?$qTqhXa579b}mmOfkk|;6CG3a(V4OxZP+%zg)O#PYy
zyMet}V(~>dmgCe7KTocz;|mHEgY+l9gD!={aF}q3Zc&t3G_!|r*~`a6(i%H<M?%K%
zWr##0Ov-~ZtQj(p?9OtJ;6_cgdptupq;GJRf%`TH&5dg&-Jln^WIFUC%y$A!#N7a~
za$*I#9E`c}WFvUO-o~{uP|9p-5(-c>CM|NnbUds8LiyP?cGPu+vHWQ`$6CVuCdntY
z5|SPSu{A+7<^W26B9lnF0EPwD?!r%UZ8<5fqLthAZn>oNWQLzaXSE_^-3ECiOkW;q
z)AXxVmYrc(#!@zlSmkTVgxTu2b|QWw)pLHnOTg7~1k?Ol`U`u(4{akt!tA&-!BO+>
z$!v{braKq%rMrvl^UnED7&npG4t%2b1nHY~(TJlGdv{{H%-hB<ZBE%rmlP^72%%}5
zcB3e4kj?0l^P?BKp=NNJpGLqC&)^J*i~It=O;9ek0WVJwJux_)?wC86sqI=yz%v?R
zFdgqrm_FLohetG#uqii(hCp;!cks{tt&*9?P(K~Hsne|x6q_f1-bY2G6UTW&b4vLj
z!W~?cZx>)C-Be1i#;cM$_aggJE#<aN>6UV4$6GXJYj}D3<odZ5#cT6<qCLcjH^NU)
z|ESl+r?)j$J6^}ur6k4g1nZLTY?k(9wgQc~N7!K?jk+#llIZG(A$JKHKh=tGJ^O2b
z%IV{ee?e@$FDhcnw-^d-0~2c>Bjp_pCZkHLN;6xP;}mlY@%$pD$JZr=$B>=L<M~T7
zn5{x^{+J{77Pc1D9h<b6S3UaM&Oe;TPtEf^^s?#=?nc5Noreie@%qbKnu`(H&Iu}I
z5!v*XAhE>l$H|VnO?vgWH+pJuwz=kB3AfVtXlX7e02qZ+P~blqFp8BnSU|!qIXlLH
z$Bon7h<U6ZW0S`fp*V7~vpc^2)M1&e5u>6ow#o+EaMxdTY;IcCa@1g7$3zyq#;18(
zP}t<?xdxduSG}~1J#d+gnUpvRqWj%Tmfgu~8FGVKFT75B$h$IIC!QptdMR_On0lc<
zL34wx*PC3nS?uvE{ZS9+=^tc*clMk4gxK~_NYx!=*~-GW%O|gKgR4IenOD*kOx^3k
zv+-cz-+XS!yF`uvJEDUfcpi4&o%G-4P`$kKUepXX%+~SHChT<WTCLp1jj5`fej$re
zn<%tqYuNv}!=_2qu}nMJk1luutB+umSq$pei71wdgpuIIc16~*oh73d1VF(b|GF!r
z$@s<haT}o3C%$}kp0{j0%I=!7F<ZUrSRdCk$(nvubhZPI%POZ`+20!ir6{lFEN4({
zE8%aWfVL#=fu~&_A9>nZbfu;hK74VMNnS4B&79)OC!_m#&pz8?cSG;yb)L&IHGk!T
z{J?X!Ue2iD4Q{pnCwuewO5QU`h1*W3CLW|H0TymUDboLDh|f<udzjO~sGfESw>9e@
z`Msvel<WE?^8hn@11@0-`~~VyF;#WD8({1mVvnA;4?@_ky$$4@edRja0cwrcA54gS
z9^>v9Lp>6_OV;wL^ZTnOZF3=PW!a_|%4D{h$=l>rO^t%8I*;+!TF8T8Lc)q63ZImb
zrX7r@;1Ms#a`(*Hb9yI^?^L?AD!hJ4Z2Rtk%d;z2*)i;XW_~%ZP1S}HUx#Fmgx9)!
zZ#ka%!K;=l%^6P3o;Q7H#kh@hVr~LF9X4Zn1!%F$1FnJJ?m)^JLZsbqG?Xxmm*(3h
z<SmDmpfm>)oOe-)iZz3TN6+qI$jq8xv+r^!l2L+@hjJ7PjmET@#8?(YR9TBd`Y50-
zC<sDF-=J2d@rq^SuFIfX5U$)3yk4PY?6*<AN-}D(5d$dPEiI7b23h1IPIx@O$WOBt
z!ej#so{XV^;)z+bSfy+aC9D%jty>_rArD<j{I`L)Ia4Qz>1sW7MNhoz7DHSr+Gg=&
z8WNabCRAuqc5$_}FlJK|s+Ue(KcFrjpS2_DNx069=TZE}RHuN|1+3ooEP-M?*i$De
zWoKab5v_hLsT@?#Pjn@^XRS1|l0>RQ@=!0@l^FV|x{Aeu`hn{zYFYFktZ+uj!GTqp
z_8$hKdY$0*UPvLxS8yj6pAq6{$lM)bsYaDXYg|nyR$c;G<oz=P6to-gh7{AR`O7oR
zrw9tuLclX@TD0d>(PvROTB}+w4?MY};3rU?aEiWE%3734BxtWQDTpSg97n~Y+gut%
z*&%XO`yTWWWen}Ld5GT;qFPOiO?&Y)ho)o$W$V>)6ZCm!3Q#hPc!1O3q)<v&^^x7I
zWnI>VXB!8uC5a|8{r!q&a@dnG$Y+i`+e1@VOJEqgA*PCK;A7)q3vcV&={l^kA%)Yi
z18abr;Qmei<ZbkNut(3eO#O}qNiUAa`9*3=N-#LBil&JsQb%fSs=$*3W*tZW4Dm;n
z78Ws!%d_OLOf}0weaJusQQ~ARueD4BqYG#NF7tS^C5d~`)v=W{QBf>yyIj(Jtd5)F
zi#&#|>lSPyoE+i{@r*Fo6uSvK45Pa*9=2A+Y11b9FkxrUz)G_fC$|qTD(<Jf(MnbO
zLJ?eiJF&d##uy{(Gk%(O{VV7sD$xE&v;Cu?E0l3tF?}$&L(iO_1h{6dD%Qu`%{Gj>
zw;>Zh8=d<)4^~!NbrR}qv3?lOYp~Rr<j;9+&bc4sw=1~b-4lPZQB8cKs;FOJhXh|w
zo7vip{}ej6EpcD}7>O@XImO{=&dlirY(VCWOF9;e7p&z?{QTuE_`8`+egJ{o{j+}l
z$ou<Q|As0*d65sB5O?%46fL~FXuscrrS?@%c7jud?{2k~@`*<03}$PzwK6GS_78Yc
za7AGHnXkrRhFn@c`aZ?bEozZ$^0mF#A1obGo}Hm#%YvJic@)<J*&T1|e~&xvPtEz#
zmQwXeNXHHK*ri!^-LZp(u`S+IIhMp^^15)*55<77wYX280~ra@4<EB<36((;{`#~3
zO(k-RpQgD?u>Zv@x*Ac!ZR3S3Daw{}57K@fzcOj+vTSN^x%b^mWe>A;g6ulY$;J1)
zrHJEK_8hCNhw{#ZTU@*~3nz~53m4A6w^%bS;<Oz=Lng44Tc4QZQzDy7Q^I-vJ~t!v
z7rR<*9VD^Jh}jw-m3w2XKFO`T;akfk2#sMWkLn91F7R`n-#s^+m1o4v1OmnQFZ+mq
zi$dEG2Bf0GMXRUr&$$mB|N3E~LM2UJ_sQu}3E2y;^qD7G6==5c9M*E4l<ndYC^cql
zdE}{c=QPv^LfsMQ5LPmr)wk?3?0w5`;GX2UdHa}qMa!gr3MLq`Ra|-+JM!HShOK}5
zR6kz#Z8smq;qmwQX}<d5iw;{{Od;zXH+ALru4=V4kH1_L#iy=wuK%??<;VZUejk))
zN0@*mMOZ!S9hK`pn5P?PQ;wo|zOch{3e48=O$j@Cy}RwO--Hp9{~dI$0_zb|l=ID1
z>d>D4wAsfZGk<lO9coZUTx1llXa0_3-@975lO4+9E{{y`xQDn=*6GjUJJYzNs5?Qn
zu^WGZ@`7S!YXOSP*3x~OJiCPG;-ypW<Q<0Y`TXvJ%8}phZpmsrVqmiT)MLer%;@5C
zOitQLGHiX1Zppnb!$bn=3t@@bT7-xD^NNtIt8epiG_0owzsQw?i{ij7@&b!{R1e#c
zV2eT3$=A7$$LqCZ@c$#!u_5kHS6oyh1uiP@NglOYZ5P}%1Q{%)M`d$2YbDE|BsO+!
zDMk!77cZaZ4T7k<gR1Z(n!zKELH=Qbv%ofvD$!q%?l3J3g%%HHvXZ=uiV>Q_V$nFc
z!fX{=gk{-H2?9+^SC_LfCeIbbS;Ht;sg+c?M=g?)aNMEx;s)GZKu}Q*(xAT+HJ*vC
z$$zE<#dYE^#kan-))S32#df-BTG;Gw<IZpu+l-+tuQG)b)YIB{Ff5NkvyOM&+%#dv
zp-h^C?qMjes?>L3pZquh&&Z{$$#rNvND8-$RY)c;yz|&9HeX5>s!kwxnyR5I&#)T(
zQee?2V6X68=b@L_63WR!gp1fXio~(!W?W$3aa7EnP6&p=3bl8@aopH30TtX1L={BX
z&CQ(U)Nh;)NLd^uI-5N`ZQGc{nIa4!@>LNl_B}kY6W?JP9wlK>(j)P6q#t^nTXyfy
z{0W6eLKMbiET5&PHQtM;1--eotO}O+lg@e3#bn6DWXX}t1b{29BvLoekss&k`5A$i
z?_(kUG+=^hyo^L!zj(-{(On)wq@|TBBuw+;{&dSKTdWaE1wC{*&T3|#xCtmp4E-9T
zEMrd~RPI_*k7wF=9E-uETP@F}dQ_r*0p17*mR>V3$;Z!#>LrGYc`EA}Q8pqC*SUcU
z8*v-HDw@AR+K4xw1eVfGrA=CXx7qMbX!{Ekm3@#fiVx|k2>sCNYPwPi1q0gL3m;ie
z`mkn4*Whskrm=*7W;qj@+%T*J+bbyXMap12iwD%@#z2s}HZ>?qr~MdUH%?_dZR47A
zH{0VOlHHRQ_+`sU{NsTqv2KSv942}JlynQ|x*dd#gmPlTkFPD$9WGA!S7&3pGFzia
zXm<NdW^3{O+=xc^`;7lL!REGiNzQPAhmR%S&*hIgYU?{gRPy=(?^fRsIQ3)BGBiAD
zcjvx_!GkEY?#xx;=c6m0I;Si&T8eyu1N@M=*P!%!@zytpT&iF5ZRe-~lFtpzR`;_B
z^;jOJ!?}U;M%jA-6Lzz>5Zoo@Gw#%crnTJuXD5~UVUB<D+%oS9G%%`peU3-rDb@42
z)wug(A6RYW;qcCBdXjyt*qu{JgPz~cAjyC{K1Gq^`O!jFB+4gk#H&bMd3E_6Y!W{E
z@ae0qP#;{|yDZ(07rlcLi4!~$69s}Cvo_jo!~1{BWk&{w(aA0V6C%d{d}SUk{-H!m
z-J)_HxnnM|Z5PS%JwKLrzvtWBCiR}o?SEiqFeCa)f0u7-ygSs%eBNl+O4}aZ)-7E1
z#q<RWSG-OovLkN7lYAJYdWkuq`WI;_?uvX)WjpW^-7zS$_k1F_-~2kZ+}OmlyZ=F#
zhs*P&>@Vp-4zffW|JC^!=XYYgf8Gt;HP~Z!+#2lYRgIjdBNRq~5KA@*^Wn=I+rp&U
zmV5JkI1;w{@>1Y38muuKV}qY`s)a{^D17Bx%efhrkN=KOElz2sY@v8L&!1hms~&LK
z0;Zjvk#h1+hAaC@-yT}af92Z0W@(x_7OFJ)-~Ty#erpV!cDcNgMS0aj*v2sFKgPOn
zyR_}!`q$C*|A-ftOlots=ctsi!;@tw|M%38T<4;`C$bx|{8%>I(-&Bx%vOgy?w22V
z+FjL}t?t9u=TVwE%CCGJ+iXxR(X`kE!1KX<er1pAu~)o4dcm?=Ir+F7y!CrHQxPi5
zzy2xEKp6>0A7Ayp1HNshTQbCJn&7ThTaP5<!reC4WP8xADu6zzMOO*8@GBN<9QD~P
zlwW%z!?w>BuHb<(+aG7g!qsis4p-QETb70Tl%F_!3udAhzIs`IH7|0LP+*f<q#ZI7
zzu~n>m>cQRUfPKaiW^KZw7n$|4R~{Ra8SLQKG@4oeyCUiZQyQWGDG;Muu{&G?-J+Z
zQ#UfFBsH+wDzi1hcFpxZk-89}9}Jh!kS-WMd0yRd^NMlH3o|Z!usn;^*17CmharBE
zU(%kPLzu0LhO(1Gu?^z2sPok6n7Yf>&pSPSn;0w9)-+Mr08|I`f?VCrn;<2Xuh>hM
z6^Rc@E1C__@^25Y4XH;+I6e{IkS25UwI*N%o*%sW*(5F_GG7oA_!@&ul1R12!(i+J
zqCG+Ez$_b=gpDUkg<o$g!U!gLpi$8&9^!p+gXKP3VXTmToJ@OZ5j--oIT4V)Ja_OC
z>M5^vhIOdOoe#P<^n>CEh)sIMfZDgX&@+%$T7OJY|F7Imf3?eada;H|E25-M74L~f
z$!IpCj>eb*>cc)&7)c`_pb|kKch9@=pn#WB)?I&@sTr~K*pLl7&^!&9+I2;k%Rq!v
ztocbA!n+0!HiI1ir$BBeiy|U}(`u_f3r5K0)~KR#No*S^b+-ileu>$&kIS;{5)yxd
zcR(<7g8Z__7SV{y<E(RshbV@(gEO#JrJ@0CRm#7j`nK1Bd15GH1iXx6kmi6ctNR0a
zRO~*#oCMD`)Hw1Oz+cU^4CkR4&#b|+qAAH}h#4ki3v=idzbSi0k*ZG5Ps@R!@tX!C
z0h=QbN<SlDnYi}(jQ|)<*#<lC@_H-sg_OghijWdC^WS4WYRCYu?@BO96hKdt8Z{f}
z6p79l)MX5PC!;Vpo(ka?Nmxuhy>PYz*1D%itN9h<p)Jw|Ha&c-xq~88(0SSox{<i8
zPlHec2*%`N+5}JFN8<7^B)3MSNVgydi2P?#t>u3Oo{gF!FamnRbPrn*hDml)OJbm8
z#+XE=D%N!??2xn-F@>Vhu}nl*afWE5wFxGQ5@H!}g9_LHqb;Tyh?rRFwsEbQsgV;)
zlLloNV{ym7oJmSNqZ@~@ZTW{0<~g~?O~or$+{8E7Exa{p+mJWOX<M$U9~PF6|G;HB
zr8BS9JiqC_u($3I1LUWst4#&HsK{3Sl<5ArpBnu14PBDF&~}7KYH?@B50OfDK!KQD
z$@A)Hwo<v*uxj}rrc$MsmKqp~Z;#2l4x9RxrY35w0|3^*Qu>))?y5?s-3yABE_3%D
zmbd_AJ5+zj+k8DAw@i9tB_%PimMpZaw^UZ;{XBV2GH=`MxDG?CDLzf+W*O?u*cfnz
z@3jvm7@FNqD`7!aN}Wxb6NznLk)DFVnF)}cRQtN#x2PFy-aU8yp~b;(@>uX^XTy{h
z<Miu1h>BJ5)J*2r_joR0|0^-7PtCbP%bpi~t<3Gii{i)WrD2(?3;O>AT0ij3P^@Tg
z=lIV#@2MOTN5cbm99SB%T|D=)sEmi+QygWHH)<vB7}iGhwLzW+B`TYYtz1ghw>4O)
z)xCod>)-7%Nv7Y9FpJ^x_Dkj+v|@bkt5`g{jwn$$$GH!^9(xwEb>$d0Lm)Q)Cl}AF
z8;OyCgRSrLB=%UY@u!{xh1YTUG(+a6eqECNT{l)dRJ!hmz}3?A>^tYH1<^&SML9cy
z%5mb(hyY{m#Qi+@WZShs;zIvkWP0*k*Zqn{=A!_NvifzV1&%#xlAGB|3FyBmBv%kz
z{+s_bxWPBZ4(cV-smcH9@<42A4zeik_}R`twpRKg1u3HnVN|dCi*u4W_rx`-CmSm$
z=Wk)p`d`tSyyWnIP8r)a*BW$DChsz-(KZ<4F_a+BP9Wup*5a4Bk=)H?cJrYS2^)9&
zZpeEb+EWa_sD)W&3H;o>Z=yMTIS)(t3)q&P6P0rn|Ami$Lh;RN|CMX95TCwr!F}*g
zgQ!F?q*NmSHhfxy9g**LuKz^}F8h5G#Q6L|G28nI2B)vBRPvpn2j6&}k4|qt8$6gU
z4?O1XKp>4vJd=@uJ$_|<0sW3!`)m<OXrLx0+!|)FwFVhI(e9uJTD)5&2I@bh*svWI
zUdymYQ<@7uQ~h4!CH9m$G=We6Z;y!N--X+jaWLTza)SpKW>PM3?{-3(Mr{ePC|(TO
z0I$^2)Bai5t7lRH+gUScRs41BjzBW)k$$AUz*8w_xdZM(6Pu*nz?kc}XZ{XDq6^%>
z-51f$hAIODdJyXu&SOE-lkJ9Li!;Cz1CAOfBlQ(7LqO$mae<XIs=`;%YCvL_ZY2bk
z9Pu_E^&4gx>4^!0ehpDKLy!c8dNaX-Riu~!!6#3sTw6zq_Hssp4eZhoXuxCk34ZF5
z0y!6zo9B)$Ls(cCdhx(H<Z=bo$MEzzZp9*a8hXXDfIvrTc3-2+8L7t7l)eLmEXfcJ
zr+}RrkU-i1qR4<{Ub!Q{Fk2jKw?2MW9@`l8S5sbO1&3pnJW1B8iLa<=({Z0sgP<K6
zT3}nJ;|{3EfM=6%$flZr+aeFl1tHi4TwVLzBZ9>{D0GddA*8qwFg{F=na9uU5)kq=
z8d4t9lR!-rn3l5v#dKrG@D*RhLg@fQn2JnVUqmV@05i~wVo|%`<T3Egb^FUSnsxbM
zLr``0lL!{>A>Ie^9ihDxmoeWp8hHF$^I|NY8bzm{rMlTPQDx#anrzhEP>!iCs{5Pp
z^dXJ%XGijdSIoMFZxIi7`cZ+dD^{1en(`qN@f!rWo}bMlBu%<jB&F>JqSe*{+DQ%J
zXt&7)A&z8fpsjeF!_#jg(>1e;QE}~e%Y994D#6HNwyF!(_GQXAgdy=^%vMj#f-UYo
zOLQ?Fwj|CLkn%L;<=o{xRwL#<vnBn^0ZFr2g0_u$vqil!rE<t;uxjYR{B1#1n?N3h
zE!4t0JH90>85m#+s<qTp@^o!U4J8buw~=^*!U=>j8sZ!{skiZ)v6WkjuQx|pRc(oA
zDzEm6^{>TwvwT1yH6&G_Om1OKULE8q(rcD=g|s82mSHI9!EeEhPxDwmdAQ26SJM7C
z;b)T$wjgc<wAB7Zf>>Gx)%}-h?kD=$rhC$hOZmOalo^tdF<-X2&kYZ&@NCWv#nmw?
zvyTkQ%k=|WTZxf<xr1PnFQ!G+MWyA>oL3PS{r#@cB>$|~a*{mvF9U4b0enh$f@?5O
zLFu^*XHrDtn&q=4=H&s8)f$=+rYA9^k(b(&oz~D-Gb=b;Dspw1Eknz<1)^Uty-s11
zp0E_E?<z8d?0QN*lP$1)xy(Day48cT2a$C*;N2aOQVz6m%@;(sX8FjM2EOJ<CcpAZ
zm%aY;$;8`=^0H8%K$qW#^4d+pf1FmNKluFLln14?8<x)I`;?5j!}?>+pSUQx>;7iB
z8q|Aol)?xrzqE|q)$Bk7_o*k|v|_I$jw}jU-GetDkm{`S4}X083dOlk{QR8Rq@JZz
zSH3$wwQzJ_f!)L;Zo8z5ZE;Wrb^J3Hl2jv>5p6{LJ44}ocoa)jcjt;wwc!}JTXZ_1
zVwAu$Nv2g$bpCzWl}dj?fr1~8h-~(!cy57S@@{KP^?Q?BQ>G5*Nmbns6^vB*gk%{W
zar3{?Db1i3fgNEXvd!jFE%)+CJ*Fm%U7O>UcSINN^Too6+g*P20=M2K>~!^O-8?S0
ztF1@A#Z3w9c_`BnAbpAy?Nca6{*T9sE~ec@6lo?9`%Vwq+UNfb_q)ER(yX?Y*Zn2Y
zy8&6JQ3^z1>C-FZ!djb^CN=L+$|mi<_Hs`5b}?1p(N5^dpleW&4BRV(|H!NT*vQu8
zLHztLvJyCt`A05CS!dwUzvf1lb|MpZ3%}rT24h!RyQ%AE_LUx0mq$MUfq(VS8Jz#5
z=gzv!(=1t#yaH<LoixdL^eq@ESMQm3@Aa<iK9x;nulqh|jRKm=((M<9DJ^C9U(XY5
zv)S6aJsui=-i4|^=8OKP{pcPbAZ(mrvGlgA8NWP-=)lSS?XV9%^oW^zo^G$(iIzHa
zs<rW$UdVibxIV*Z_g}&=btg|+Z3RP>!65_56ZgcFX*~-W#$k^dToHynBgSE3+g=Q3
zUGWKe?tVIzHni<ktzeCNJQ~xq^K6n}xR*08>W<sG{9n$VMV$+dIw}>brT={BP97iQ
z?c4pCXG2U-Y_>j0>M41F`T};)9UrT>v$>&v--mp4dPB~Hb0)Vum>=7-Bvl@A_t9$O
zo)#+{aNaEwI>{6kqN8StF$!V;L#?08DzNjqO4BNe5+Xk!F4<+y+{WqBATqM>1D&x>
zJnm|z&`2m;;BN@A5mmjav5j1O3gHX<sAH39R{o7{%5M(HzY};B3<x(hSYiu7y{4)G
zXT!-73%8Jv8&q99atg~&1S}G-+zLi?rK`Ly7C5={@;*$A_J5BA7I2)XwPZGBh|K6p
z%h6N*8LmW(hB<QZ-^e!}JR-WEbYWI;N+@5HR&^r+I>Of-Gp~YOlC50C<b56R(yRw4
zaYrb4AEFsPyEr}G;)*;~#s<>GfG6-!JqLjze$`}f-h50Q@)nnQDX2Smt(zFi)F7Pk
z!bcqaQ7pjpHc3cI4C5{gD2R%=2_W25mAx-UO1>^Z)CVdd__E*<6XSxK1ULpLg1GEt
zj4PQ><+W6lzAX%1>lX4~$S4#22N2C|9ccT0`i5m2HR2k#P~d4Jpt=wUkYq>XA;Ie^
zSQw87%|pG+q202Vf}lhSX&EhjduL6E0&i}ozjB*-Qh0Hay-W%Rwv^afS0Hc;KQZzi
zhtf;GpvaMVvMZRfjYkP}pi%-fMQ4*CwFO(Jr5OviVsWeRYa&ZGCru$uRkL?gCxt~(
zdn&CVuY|pBa#yw4GD{uf34#T8)<$gdMGV)7H;;$h7lw`P<ybEZS6jntTZ1X2s#<Il
zWE~p>W@R$nLxM(0&DyI)jd0X1)oxCMH5VfNgFa)>O}xZE2oKeUlqXntw}n(*>u=|h
zZ^QNSisUhQT8Klzu53%2^hAx(vKAGH@~IFxKfB3NRn`*I6PHrVvkPb1a87Ftl-N}-
zW`l*ftC#v`J%Ad-ZX~?08Kb@|g|5jKQn@(NH-C^akZ{QC#~0k{fp8U+>yBHh4)H2D
zC!&n?uV4W2Ti~tl=3W(#^(E^?f7so-+;h)t%xRf=+>ewh4O)A3VEQ{~Oj5O@B@?WQ
z*I6IvQyDLD`J<L$gcIIq__i-Y>!VP18ZB||6T+X08`%%Vk0=q9o_y1SdGhtcRM+Bs
zncud|Vnd7*>vL4Xhj?Jc$H2JW)tIfcopE@CY}olm%RR!mEj~aqIRzGGD?3tCSENkH
zrFUCda=or92cIY6w3-*%RygRHVnEvFd9iLIFwgfM*JgyMg(pVcbx?v?R$q11m;T+^
zo-zG*yI214Lm}%u$(UZoo^AisLg;QlYhm8lVie!==_^bLY7(B`%3rj{1b<^+m7Tbg
z%_T1t0jozx`nw90F!&c|2j%Gp@R6+8-F(iThivvNtdS|h(2S6xY`g}C9m0`Jaft-0
z?7kgEM4(<)+3+B8aD3l$>5hL$55=zcxBVq5pSsCmkD;dGp@P-cB69~W4pURy)PX!b
zYIx1mOJFAmKXB;`0vvEJVz#cxwrgSahrGM#KE^OPvzaF^a7!j)n|kJJU=1-dGf``Z
zuK(v*E?u|Ap;4f^a(jPSbv*UMoV6w+RrL}dewvt{K@Y?fI#5YXt9>Y)nPU@cn}nOj
z;6+PK5VqAhUuCRE!X)y9{(3fUYnr5nIb}snj(LpuC;#^Crfe_CmVWg$&dy#D#t!hi
z@mF7yxv%`Uz2mj}Fau1+?tuR=n|W1gS&cz4vyK}EBmI!Zu($BbK5=nj<%)kW7R&wD
zrsBJEexV$H;fl^oS_i(=z4qu^#<}MpGPz!6gMXhzQQ1vHFLVQy%=`HM>n}+9hpnIv
zU(S5~ym#5jx97*^UW=6`Sw}&<GSDM(wq~vF@0Ki=;-cNOsf_6j(tEKT>8xD%eUe|`
zhpD;9Mq03ckWC^laO?H;G~6|4#ncv6wHNq7ZWY3?wZqmk68gwfxu1fi*q#P^7x(B6
zLPR9X*7nbY(@;*2h}qhB<<`FoTZth-XJMu`8b8qXc-XWX(CtJ8RQ18R8|4Rj2WZV7
z;}P+o>rZLSv@W%sqA5sc^#y7Y2;_2iB^xRyHTii^7$bpFR;;!jbN7MT=wF!v?Id#j
zg8I`MPueVkX9oyzBhkyAC}u2T6}g767UjK{UXyvY5Zj3g78G0&au@O*$@*D4^78Bk
z1|UTtqNv<F3OKVil8^oko^HiL!CV~FCm3H!SEp;CTX;8MhjVBdD551U24l-ytUj8E
zbXm>XAYXGa+)iNv9T|{NMjXRv$SkS~yy=aYa+Wkg<+9tPO0t{*78D0*2sE(TdYpV0
z^NTYOSM1etMnRQCx8baZZfG(D^*;tBt{-m#NVpU+KT?o$a`ly1VMJ_QSKW%wWNgrP
zx)kc24u(cGx+(h7Gx9_lj40{ZnU;%MI<-7v$2ywVHTBBOzD)Tu-P4A#$$72SWH;|+
z(Yi)c_;_&sb*_k!K63-Q8(w3{4Hzh;JFtLbl`t(a)O%Nx5y63g3?@~@%v9h!MW&p9
zB&dAb!_}-^ky<+4+Wk#<y)*==1_#|T(dic3lzwJ!OwpafZ%UUitNaRnWgjQ<Q#}WM
zIlr_bdVxL?BP(8bm?HVanhL4F2nZ2Gm3GGCP$OC33R_QZE85IqB9>5-=W5`at8t@y
zGo}{z%#_QEI8u2a&~4s~3zOJ3R7`T8o||>cz>*lBBo^>N*l3fO3=Wf>S0pWDuHIbU
zn0Z!Pk>nmL9QtCM5fd56Z4YYD;}JF}Hf}|Oz2EEBwV+n4)30sjw-xhDq0=fuMIUU&
zoFxE{nT@zg-9pKjLK^K-;i?ozRqPHn)q`&a?V;eSk72sW?{!scnrWL<Oxjd@2yzYb
zEQZFrt4l)0W%#ijER)a(7(8sP%cT-yF{dW4iYD_!Y@0D2fe-V#ki@^AmS4C#Lo`O-
zkn{n{EwJ+Rc=4)}yt|@h&$Hgcr)Bdk>DvS@f&V~iyVvC<YlsHFMb`B+Y|+?={$wA*
zU4rN9=WU2NQ@@X{>FA2D;`tQw=NWm}AZQy-o1#O$-Y&~Nn9)?vib{-s&9i;s{V@2K
zJWn5_o0L3S<Tc>jC%dZA_QD%tij^C`v11ht5pyBBf1KOW!j<mo^gKSAd0}Mk)V!`P
zsvZt8m2aW!#m6bO&rKnit%pLVM?&3UjCy_un5~SK&bQXr%Vx5eqs$&Tpu>R5_7QU#
z1y96pggE{Jb%EJBTm~UmJo+W?BCD+*EUsm1^5=;{l#y`w?4{-dIM|Pi>m3!z4=qsJ
ziu>)nm|y1})WJvHV>aRGVgT)?Jr`EJtG^!IT74t$^}aJZ=wBGy4O8y&Q!o;*^1XTe
zCxd)Ug6_Yz$nN=SwvZMqu{Jo%HDjBm?IUY!V+uNRYRSc4WehI82Y$U9FP)OAM}c=Y
zUV7La|8ECf{7-B+e&RttAWL|GM%@YAb}vDkh#J32n{LDt;nM!{<mUnw-QnQ=$%VXB
zQCBXk-@pOC{|kfpE(2JK&x>BXq<mMgT-eg}$s1hw*LyD4nr%CyETY>&^#hj{6>oPI
z^$Jb9SqBC?x}SRAx$ds}T#@B(sAktNes%>qyD172vD}f~x$>qWz2sJx6&Qb@u8yp8
z+t}0u5g4g4^LV<%=#9`|c3bBSgHoDNWsQXEzRCAcz^cXe_#f`ET(k&(l5+y<2hN`|
zdHT1W<qNTGJ7EV(u6s6q=&flg-7E0O<HH`4;0^$->Xt8a<9&c`Miob0sD))0JcQ-k
znyp^(7@Wg)Q^D50DRlG?$L1UcbuoBr(=3OZghlPBHVG^9oBx3epM9!9QN##17N2GR
zX}d`{OOjchd3PJ1IeUI0Ty^qBm-k=Wbf+Wexp<{SZsD8Bf{U^tWLTnS_q88$nfr@r
zr#Uvkaxz=xwU|q27N-b2@EVk!GAV5Y+;0X&P#f^>dA8WJ_?k7G+hYkN&DCYYwoSMC
z#!}qtHU>TS(~mR{!Xet3Jeg<>COkW5a!x!oOGy@}%PBy$b(0GQr@>G#G*w`>y1g}<
zgxz;9rR4QVsHym(R$ma*OkFu(#WnkVZ<8FGM<Yr+6J+jluZM*0#rxdcX0uh;ck){;
z++tAR9yz1HT7HXEP(daZ94xL0Xjh)JR`78*RG@$51B#$p>Dd{^Zg$mS!&>|<9E_L-
zi+ZFe1`#*&&Ad5&HwWJ+k3o>DY!Yl)0RbqDI4Qh4mt6b{qU`m_MuHS&rV8C5Aa)I+
z1*1w#if_f2J=Q2nNi75yJJ#^}ZOqQsatZ9v;P@f#aTksIQg;}&8;^;e5JMP`^YY%q
zfPv9OHm}55N*oWKmDU*a2;|VyK%_w#A69QBf1h7Q3*Qy{vg1AY30^%O@`c9Flt;uW
z$nHsDM#k4QDY{5|Q65TqnU_bvXJ+!eyGiva`V4M2<+hZp-vqRhjL^%(<^d-`TMRuZ
zf+;E8y~PvH!ZCLtp+zN4Min2Y69@sdoI;M^aJuZ|PF+r!V&+qW?r-EJQ$cLS)ydK>
zhEx@^4ZMPQt%G<<M4Q`a^%^4TvuM2lhn#fk)C~f$3j};1ZZSIQnV3Q`9*@|zGf;T9
z2V+|Wd&M2LjEF))&bTn;%pbJHc8y=mi@lt<N6%OGvyeHy$3T2QAcmUbv_Pw@(L=Sh
z9HK7g1P|C$9_4E)1yHviRE`cq*Qt<swHlR;4GSe@<1TU;4SGC~2Las8Xt|=aF_Kd7
z!#vC5ngY|1@_3{`I&2sBf<Fq9WKf!in7V?f$(aO!VY{2~`Y3#kDkRw`2n-1|lT(BM
zHEz1GXjyu=QDrLvk0P~@u|B0IHb_W4o8X<M+kz5u0+wl4Z0qxqe4_5roE!7x7X_Xw
zE?`{5NP=fUo}aO$$Sx;Pk(^M7A&eYBa%4G|5#ZA~f?<3n6`^Nhr&a%1HwI-UcqT+A
z<2MV#z$i9ZF0`eXPccS~QV1XvZm&E@-n=hFw63LdB<0q{<?$-XTu{u8;3e5vP$GK{
zCK*NFpq7u(8=Dy--Fk}L*{z)rD|ZoS>mrre9Y+i|rzj}FYw}8e>J2G{o{8{f?5gc9
zK`}IliaFD@7%A1rLbw{XLWFvEopb0IrtO84n8w(N#W-VJzYY=!TD2^FO;6vHO?hLH
zQ>hhsGvwHdHn^!q!hY?~S@a>J2AD>eI?f3K%CtAQV$tP3<ZKo`&mFFy>D(PGAJut3
z@30aK>d`umg|fKH`EEb!#%y2AChu^rA9Jrw5}k65`<%8><yX0!b7PQlpDRI`>_cn>
zyw#PWg#a!)6m(;v=)XPmhHb)V)N-3z3G%CEr}#yFme7?)nN$mZd)UhMZ%^kt%h_~n
zQMsB@8iD5iNTsxx@6-`B|D9&qguhubMf*)@!_j0r2fiikjDg<f*pLG1l!3sn(SB&F
z)e}dB(iLS*wR+lr^g;1F32AI}ObYA*wjk0<jUqQv0$*_FwthugG9KFU85)+y0BEqc
zzZ6JbsRlMdls_W8lknbxih4Qtmq)lltpSMbLp=mSdZbE1bA;jjE^h%4n^N)=cY$96
zm1>y*fs+jv5Oy?hZl+%f>Q;G+F^g_s%I0}eF7l*vMbt@+hq5&{$d`D)5}2j-g1Y2^
zsMF~X6Scx!@DTFKw2SV)6NQ+?iGrg`a@g7<MUOEkP=QesNHpPW;COSGZ&t&^>ABuK
z={$K4g2HT?8x)emBibnF3K3eKT=uXjA|B|<$$2!0M$`(N#jFtWYE5c!8dZ4*t7#%M
z+=^T^EFcr1jN^c`%!ii%bR=&KIAqafXXr*lBzq8H<|RxPWeS;9_Jj{a1|l>d84dX+
z6f76D6ctd<vIH0~28+x;c?_7yxFU(~`o=YSrB}6_rnrjO5yCk1rA2`#`s7<<DC!P%
z(Q;ITSod3xuB}jbtC)tdcu`%v%i|dZ_aHF5^jV596VaE-qF-M$fM9O&sYU?}g=$l6
z60(j+by2D_k~_XY+y=%&8a>9Wvaju6DFT~>ZV^wrF46<aI^?yv!(ulC?z{Q<ELMJ!
zq07y#f8e@SZ9|kZc)0n>p;&Vo02!Pit3|P|yo_LY!%FgYqg0|8pK&W&$|xtOb7~>t
zNjgkQAvo4kqUV>?tq>68csZD@1G~sEoNO4}-UDK6QZo<JwwMEGSR*kp8kT9A8uWNM
zO)XIOk$^#LuIUmsvz|l&i;90y4x|Rd=BtS9fawsgw9TXpw>*Zy7x*gM*tZCu)KF{}
zP}PrY!dh=Oef%NR`{T))aqD2zdTm0dg|4x`NBa*`?cEEL-&37jLQzgFS7XKW?yA)t
z(Po)zv|&`hsfoby*Y~FfJBQ5t9!o(e{cN}39`v3`%9qiNZ=zdV*E67j*m`!nvKCc-
zl;>anD7CdZ*W8d~xg>izfnPhPq<<pzU9-j5ACBd(>=o)tfTIlC7jHDqcyiZa&M&vs
zA9nRkgAjQKG4iSjC=X_u78nV6`2E`D^<}i&gA7tn`C*Rxf8zti#2eWDQ=P2biT&pc
zo8l1TOrEuMSreqpQf2Ys3m1fR-Ph)BTI%lcO5o)*y865J2Tg>B|9I-MS>~acm7&@2
zk;rWM7QbAuGQg)QUZOnTe^%Ly>dwS$Bd%WB@7>D3a)-U*G?xz?{J)_f&*PuXD?VRH
z!Y{Ik`rFQ@9blwLmyw^F{LkFBr<N)YR#ffm#$aYuqA1_-MX0>J<NZ`kr$_G0m+mV^
z#+Czt)LfzIuIjnF6qEhEOL^!0)L1`e<IPt#k*xdizo*vB+Yd7!pSZ|d@p;wFe*&HP
z?tLWLQo(zDUytSy&?_c?h<kD!!|F0-IrL4+2CCoqwQLYSHdnY0J``R5UaDyqPzNEs
z?RH3g)h({o+9Ae-^WE6y>m3(#i%?xXc5()4k3p}{C2!<^`9+_*{@pY&)eE&g`+J}3
zoYv}<<K<9TJvAFP%lfX1y)f)`%jU&9TO@lijM3OxJXW#>Eyg5pZI_rrR6r;W@kT&A
zAw<^B%71bz#^_i6v9&<GoA+<W$*T4n#UzT(d9w`diE;dgk3Pf={%7<otgKYsn7g(4
z{gr#_cj5!x`xtL>NU6>miaMbs*g{S>FGSbv|2H;0C4xJH?Pa9BEPu~Arijp>=kE5f
za^9g%JW<`o=P93$erGzHQ+sr?>JjxV3u>|qe?Jsjl+eAA7IH}NcrBu2X(JGD)u8WV
z{vKuqX!iqK{uo#jR^kYNy1MxUcXrSn>b!vd=LI~Lz|QRKRu<>!hz-Qsi;3D=TH?6A
zkr0&8m1;yp>n5HjU-U~S>Pu5GQlUwB&`^@oA3Oj<HW#MgyXd&T#T(|4v!~pw&kA16
z>Mic~E?(oKzRj!Ua_{a7jO3`zID_#2E35zELf;6S=xpn*{|D~rdrAIi#@%^Al8j)~
z*ldhOdm(*R&mu<O{F}MN6tIy)KM)w&kV-h%YES{!D$ySva1gph1>9)9-8n&MEuG>+
z1h6Z(4_w|n!HA$ZM93<Ewn`H=vXoj(YIe$KzduQ%02IBP<T4SAbG%RJEsGkA$!^SA
znYsr815j)(9>>lv2&aE2O?gW*3x{cCmXi#H&u}ce@C51!2J{WwB?^v&3JOS;AT(FR
z!qoE;Y2czF!w^TI-2l^R<Z8>v12bAKUTm|OrXdL=b-oRW<D5ia<3?xB^uR<bT8nYU
ztBeZI?+T?hZ#zYD7SQvw6Q(DkE2i8H6e|iRRj{%d^pO;{No6&jB?+<%u(o=b;e;kW
zeVd_XM3RpO#S|$vDyg9vmofsAvCR5hRZB_;{4%Y)p|Qxf7l`F$ulYGmqv-BMFO<O@
zurFF!czef#XjYe+fxw$92iB3h>Vtt!^hxJdtbT^6XY_!dTe~V!a-+3+Gx92Q?OcU6
zlC{@R1clJ}YP#Y+i>*80x~sNXV76*fGJ%G9__$k5j@ad7)kuVXs^_g><wEQhR>U&+
zO)+iC*6Rlu2M`mI4VDI!Dlor+5@a>@xF+c9BAOC2N)!Zvby2;__19*VF`)g4j?Za*
zrhWD@hNAKW1{wFBP*`<ORPb*PEAIXuC)N7N=EIjmWH#&-YE)7Cqr_7(?F=C$>#{|8
z63Bpp3L;H%GengyL7ZjSCvQ-RQ`|0GdNtoPX%|i;r66z-R01FicF~OB7Rj3ACebdn
z>r>L`{N~6V{1Os2OP*_N=uMAVl@ZgzKpwTwH}jhz)pK>AzdtCx)ooO)Bn<L+enzov
z+SVq!O5X*9A&%8=6RN((GGx#b{p%QiCo}hEM#`gLTtkmB&VHXwm>dcUWT(6ZRhypu
zhuK7Zi&dGa<j~3APQt5kXZh+sqmX*p?CCl8N;2%O5J&#erf-E0ey(W|`-Aw-4u0CL
z+YZM1A5OC)C6z;EeL~5mICCuUr?{KPIzrhNIPi4pqX&Y_*2A$@l^I0$ART|LbzC6T
z*}e2c-E;a^#0$LYztFjVi%YXrbkE&1t#RDa@&y>Fn5`P>Wwz~QZ6<{5w;=IF(K(w=
z=k`p8k?jH=gmrxb?L#ArQyUrP!woLSYz@_Ou3BdQ;ck|yc%|wwUbVea)dw{8qgkK|
zQ$?i>@@3LUueT_+^Erwxz25&bMW~<ZteLg(v$Y<Fso4r^N5E{=8<dG{JvJFU{_cxz
zK5}*A@5TOm0dw!NeQpNBp$<Ysf0f1|%ly3ZUZGp;J!i8h_uewuVnpr$*xB!O923dY
z;_V%GOSK+_95e6TUYOjx&afLMys(Rdu@&`A3B4}nuKTOtK2o2Zl~;X+Ch;FhUphOR
z`2yPL&k#6qCz8BW#1pFH;!Rk!_dx-h+pXT-o)bsJP9Vw5=u2knMoXCf3P#UIviUH1
ze+>P5SKVzAaTJ87FEq2&ZkKva_5>524;)B5RHWXMS*L!I8&@{p;IrA1Q>mBu)t~xy
zW~N<6b0{wUTFm<&P~GnWhGr}E<X^l}mE^)z4@MX8RA$e9mD!xT_S;lRoFTOoTa|u}
zD-!^=^}t2^c1WorN5ZF0?bVh~7hgG^rfi}61#%r^E8*aBWfzmke@;yF1k6ZZ{ff)O
zZG7nC=I>hZ&-`gD;`-z604T2e&yX<9J5a}*(BdC`1A=$+K|J!-Y~{SC%j|N|905;?
zmTsWIA5d1BRA@8g|6LKM&igLv;nF-j@;vojv`O1v54xvG?0tWO``JDASPgHCsUzsq
zNk>|rD><UZ?8iH^X;BMu_@;$-866-m(nTMSp^cl**+m)1nX8+Dx*%ldCidayO{+?X
zh0JL8mBWS+<*EVKW*jQi<dxTXW;Qnsb}a79&fpR_+yu85dLd6JGLd3B3A@Q-C76Jw
zIDUa+OCkO-{7(m#GhXK&&HCBm*t@_2r5mqtD|#nRX6qDt2EX8rjGdI(I-ULSUN^h`
zCU<8;cBe~hCTCIfM>D_4Y()=I!^v{>hpA5wjk|WDvu&D{DXl(bJ#HnMM&NuRH_lsq
z2HCi7NS^{-IH8jirqqh%A@v=@cxH_yTE?(BJ4&~C&8B;Fu}w5y?dqv-V|TnprQ)cJ
zMpt3gZc}I~N-+lA*27g5pGqu5DVpn~{QlSE0ybEkm4~5o5)H*^KGQ3CXYg(Sf^u2T
z(9leour_+~EkVkJ-jbSdPInPw1GFXtM6>OzzzT+W+F>%P2&6Q{Yl*^J{w@JB9lU%J
z<Dt0=3}ahoGUm=V#Q>>{NW7L+K^deXJ7I&+hIraDAEMHM8GdWJ*OwKlHwY=XE%=&#
z^$C)ho`Z76JT9DgDeDXr>ZU?4wirxkAZ+~@=iD@t4w*7B43HzqvYyK^TNThAx`e*g
z4n-BcEpTttN*oV#>heI(Tscsr<TIX_X@YCHB6kGOBRvmNZv*??SdF(<k7fcApt_2t
zNWu(@*Ai(E?`Gu9L)aUqlPNMEW^Aywzf>d{7ZkRN|2de6RPlNoYnY7xUV%TsMtKaY
zjo$SYR(+7ibc3>X;bW6i)zw!CsSDqhI`k375T?v^jY;he)sopZUa1$Un5)q_G_e+%
zK1&CY*_a6l2#y_2BOx-$Pd3BjP$JQan@Y>A<T8(5AS;r)092cY4Lp$-6cTR;1LHAn
z1yx;aK#%*T@?H_-fW6;3fwqBpy3Y!34r$%f(-l*vXz`EoraQ)~6Wj`0#oC&dLNQ%H
zG+b*oO`K8|E%_|DN{ZC}W+>m*usrP8BWMeBRHn><%6TCwxxlL@X=qxdL+<5B#Lf`u
zXPx_CgM?SKT9`UMUA_<=b1^<$4T=}}JX)Kw<FzOGuWwM+e=Moz>tmZJSNnQ}`$a^&
zmr|@>X8JJv(mkIS<+5AKvD-eLoyrHUI&9NLJ8~p3%33bnHFJqhJsBw)i;RhT<*u(%
z1+HI0zb2^DQUHnrUVIOZUg+Bl7i<n}<L|O^8{J0_#QFYF4e-)~RpPiymW|1fD4&@$
zB1rlX_scN`x9?~cm?6EvvEBa>hL2?)ZUF_8M&H(8gc;}|XWZQ3Wp^U~Vmju6Mbyrg
zN-~;fa>6%nD0GxgW43BTMuPARzBf)*YZv}{z7jd@#Z+)662mw!BHxfWRJ<vtoe}6<
zY}I+)$pb2?-GT1Nw{D1Lz-ZO1KE9uCyC^9G<IexWTOoIk7qT|6+xWub++?;Jw)8WP
zrE@Ahq{_QqZR}ZOTz{0X-qvG?ZSs_!X0$lBP6r9wsCtiU?5F~zFBDT6C_(-mA&|<-
zEo*143Ye|scWGNR<TB5AmllQ16_Pfk1WLOUxMq}%mAL34uPByRF>XA5fE}+`bcf1&
zd~RlI{(bB`VukeC#k|U&`;FYpR@q}LqE_>!E+}maft1PH+-y&!Y*t%igI#>~*U;!k
zvT)N|{?m$EymzJ7By4|)FznCWnEG)P){9@dL~&*uQb?Z>*n8dIIJbV+SqmSazT&$$
zhDakCADs(Ve(DI%@+uqGv86KTi(7u_hV9w4DX=K!7x&OSE_D+cHb3XiW99+2Jgfpt
z#%}!k-g?TFxpUdiPmA%SN|R%lt@ne%@f?4jXo-wJP{*SOYO^k=F&xBfE!KW;+zsdl
zJlwP@sv~Z~3|6CS%H}3Pb+(XC+1518wSFa&vRX>5{;zXFjE9(-8Tg3VYA3Xq&M;d`
zHSvJinlF<_3`fH(DCfO$)y&rT2QxM|(&j3&+Yh=!=k3c&-emmD((^@ZQ+B#W_b&^5
z>#IRNk|8a{w@#(a_s5J%@4U>0VU_y}YPyAdaLKBhyMRFhcAF<tg_YMP?sz@E@{+?M
z-eYQX?)GzBn{QnC{KrymPENIWIZ;!4G7i&I&&!Z(AYf3dS&W3tEbp7#V)epx`3mUD
zm8~;=s;Ofc;DTtbX8!1i*UvMXR8hB|liAtWgIVmBTlvV*pp2}xl7eId(;0J1Ri7fn
znM6aTeotbLf+GH7hN%+Zql{0CR>}g0G@>Zz*461p8s12d30iE%TCkC)&jLfnR#kJT
z)zodbkYRgV>6L=%Zjmo3$qp$cI1<<b&(dX6oAVl<3Zl7gYOL`rn{bVU(WV@llvcQu
zp}|Ojo!kty3>D*b7cyS)&UwYAmJ*u$*<y<*>c{yJ4$-^X<5!=>0Nz}p1A(S6jyi5=
zQL67?`6FqNE(im)ZL~3ue4r4Ba&`p)EM~rDTI3#88IUvb+t6C4FVk)%A&u9I10{)T
zsNEfK3-h6%FK)`GC&~y2N{<<)k@NCWztOI8l)X=~I%m|BTf~rNl)wpPH5FX9Le0-&
zb=?*avThQgP~@G=Tab72lu+d30Z9Zc&9aCt<GAk>TgHw~vT=Kmc9Lff-c>L28i;W<
zi!$xA*Y>45D8Q~^806atOtQd%AYsEIXsb0KE8ODz0!6G`Y?|Iq<VZWCaa+6Ums+yv
zrk{)r9ptq(Y03B4qcCkTieCU@sQw0fhf8opQ*)`00aeXKw{N$LT*^8(8MD{Qvjy~+
zkUiAyi%5ySw*_gtz$Em&9amQi1%<jvnowVX79@wWDrPCww@nM&!X89Xr9{(G_;lU@
zp@HbA7i|3a)Djh7AX2+B4eo{>qN#~<^aR(`T*%E=jgFz&FO<%Qb2zJiw2t9DEmAEE
z@K~9+4s)yIzv}G$Jbb_tavHSgu0|e3Y-F&|P7Z86vl=DR#}-dqplRU~Dwbebh%bkz
z`itCBHw;tMf%{=-I}as7R}!2X3uO~lNUdZ^6ow#KfIJ&>165ws%aUG?Ji+=Vv5OUO
z^<rjP-Qt=r>1HR7P~8-`O$A$c8%OymQ&a3xD`l|}qO92PEwlB>N52)rSue_J9tEOv
zG@<$Ad5tr2PaUw_iS*IEu2^SL!hrEZQ=_nUe}SHSlhQ5`HuAKwXSixJe>isr)6=vO
z(m<v`jORxZ5|PrqGX~=IOAbuvh;Br>b$3Fsd=k>zHFcEcJ+lK^7JewpF3@Ug{k8%p
zajAbC9cr+$1?GP3z`=ZQ-eJ!DYl<iXzkb-?!zST{%P?DmD-ZPA)z*}EjVZqDI=UQI
zTUDJJjE=5WugniJby|aNtF136#=y^igUC0sF?{M|bSEb}n!_Cp7-Q;OoK`pa#=Lf9
zv$*)JyjYSVRc;cprO)5&tvWdgq;Q6lk#x~Z!96=QU6>(T5s0n!N!$@Q4HB)siH=2R
zEM4j%1@M*o%&Y=WAU?u^C9S9m&>a(7m;@Ol`KOMTrBH^acE~>pit@fru+`T4_QtBW
zzG@jRejFxzEulxq56gB|&xLz_o8i>&UA!<jNRkYE_a}#4)VY~67+Z@M@R19dtt`k^
z8W{E1B+TyOhbnh1BVtFH(oDb6G*;U?9Cm}<e2$wiv-PWaYH{Gt{Mrw=V;@`Mlj{#*
zQQfz;J&8>ze(q^r2ucb=auf#GTC*0ARe`<lIhJ+mlYfT~$zj@k`lW~M96wc{yG%=j
zcm4Y@HzBk2suyE^vvTtr2|5hu+%$*b+}G}ZjWR@a0}K4BJ?9>FJa`wsFgKQsK`&?>
zk{K?mV{d1pzFlVPOG#ue<8b(11z6jGA$IRAqEucjvTp&fLPKHT321Vyh<H@mXFON`
zKkrNDfN6pFN?F=$r;gfA?Nw6D)~ce8-NbvH>tDS$Tq$KvU6b3hYT~><E9baxMuPv{
z?`8aTDhtP&)z&sg)F)uGL+9kNx^3DqtLJt>4V<UjPL=t?iS;Z%&%WtXv>n0H&$HL+
zrjE1q$NWoqzvW1mM2C>~&W#ma^Pv9iW*oVZer8`S)tz$waDUwCP^nm+yHB!4q02LU
z1e+fu4vIhD44;ZFDiSuxwU2l<+{x{M$ZW{LL9No}j&PAuL5#P!gEs04=cYU@g*LYc
zx(ih{K{;4X9zA4y+{5fXmg*Rpg5oh-S^nuneGj9+%q_fP!xc_cLcV^XyC^e)irxm0
z?B?=Yi~#i{_-IyrmZ{hV)By8EJ^Al&etA^_vuk}Mm^mU<B7^qI@vx>H%R%DSoyT`Y
z0c{^P-;4yj1B!^_HJbFW9c|!v&{MU!@-WJYZAj68XB^DWV5N{w*hQ3Nw73l|1vZ@~
zJlqZ6Flvhj*`yvIVbY~GEjr-qoz^Bju?dW~J}1ZWbBOfIF4Nn70&gw?R$2>%@bacu
zc^h3Ov~64?<r%wC%0zY}Um$|PbuqO>=3#AbLueSSu4~3Zh@_LH1p^)zkV-Js@xzaO
z+XlqDngkc{NNPVr?^%**uVVWAM#3X3%kn1;M|Yt%3AgNs^ZhoYVUWssn4kQ07Y7J%
zDUb`}ae}<HR`mj*5wKV{%QTrG;>x4VW%X$}iD~!HPFrG_jNX_O9n2eMQhFAx#vvGp
z)LD?yHGmSi%8?Z}8jvhK=&uDgW*f5+fiS;<?T$Wgs1mg^1WT4An;|GL9^ydPNUAkC
zyOBFVaYL9)vk-bH21UYncQ76i71Tl2-)z>U#>51G`=Er<yS9g2SxI-Y{$t(TU-O{k
zGsK9<Oy5lvRP+caA|v2|A&E1E>Pp;ZDveouOOjK@O##AzsKfNhLEH-P;vu9HzRx<|
z@`WWr4ml5sW(%u*d@9J!5H=-Gxw%cDq<X3#v-b*_$Ikth<edVWC28>{7^kQrqY_OG
zN+}p<c&;-F0OgQNb04MXUAP15vbLyCI-5;d7o%EIAOf>^xwd9SL`0D$3#!~3rOyFB
zARpLeM@MIzxS_n83Pr9l7CSi_v;BOmE8ex46!{unnR{4NB$-_`D-tD<B8SjxeTv<Z
z(k5)Zo=N|Pfi{%=P<SlPWZzoObV%uFdZ&|1_6=i_qwdJ}@>b^c6leYWV^!Z0-k(26
z-|Qdthx9<N+-sQ6x-&$E3p`i&6hU?h0pdU1D)1RYV*BE&o1{BCco@h4*|*A^d2&DF
z{u8GOV^8<ie}w42%=+xswIQ-|pSsL@;tKbUy$8y5o*?xt?w8z`o{j3GcLcB0Z?^4-
zW8F9UmPmWav+6JTW`&S^_pW&j#x@{+a+x<fdcKUW&R(W8Oq!=q$aH>vR*X%(H7HZy
zJo=LHWYn8dqsPJiurdKU0oKgcQ_;c>Uh|MU@J60lKX%OZbx5f->y*5`Yx#xgg`<Hw
zI%5Ry>bov?e09QYY!a4b)&Darpc8j`Q2#DX_&;R%+&ZH`hW*9Cm%Nv)kcq@7sKYO&
z?{59{Q|B+brT@|JuYRuM*1CJbQ;+{n#9AIJ;$^>3#=Un}VGe6qCgI-eKbhyNx>+87
z6ASjI4y<9e`k9N~H=L2)p7EfF#YMOIJU9d&e|O-Z?Fkh;W}XLk;C<jnA8u;;BXsz*
z=P*aIhpnp~<-Ny@uIkTUZI-r;)U5ZG*;-<@F5dA!T;}Tim!{rCmTfYq-%T<Eb_7qV
zkQUZy;%T*2_(6{9r5b#MJLi)><jT2wM^m#h1Z9=N)OyVr<0>9uu2Z?rB}G>WR$b?P
zpL0hBW3xFT=Vt7E@NfJ9@8}4LvDcJjQQ{u~m|j6Bu<c!UY~t3>bXj_Z$=;vJvN<K(
z%NloTT4Q-}=v_tXIq%vZ7cTmDZb9q7<Nq9CkZf^<ylTLjFW4Ep3)92)+qsUs&#Gvy
z=2v~9pK02~tw{P62DWa2FW-6sUB%eW>{VW8RUP*}>GL{_c}<#>ujk!X-3?2xdNCde
zq*g*XzKk-t?gvGYJA)_r!=KIPWt_+Vhqd>Cj_j!KJ?q}S>gkbX`_5RlWv_8cvTTH7
zu#6#ZLY$-|3tKo2X^2e*Vo1-dGci2&oq2&Jh6GZQWm_TMpb&?Q6S8S|UUuRTc6j0C
zkdVi_HYR7X>yzVnfjDf)Q8+BeA%BjRC5sPB$bP=Ry4{jIqwY3ue^S@2`qi&~^{Zdi
zty{mUx^=(*f_O&N6&Ic3C&TT{GJZDCRfd5OB=JrtHg{nDshMB!xqnwj6LBE?CTjTR
zN+nco=3?9)z(zfXWl;u24+OF`eHu~xd6J#TY@WBgxb$?Zj)_Gaj6*H*a=cnx7Sguj
zRxh7vv%xsJFtKRJ-rQ#j406p>O$5{k)@OH{I=7~LtVXmNvu?a=Bg7twmY+{%wRV{M
znE2Gb*>lVYzCO@0Sa5b9kNBMPa$KBNXN{jN6owe&Ornp?OZ`-Bw&tYV1yp1!2(zY`
z9aSXUVAxi4pDyBSWnEl+IeOrh;I+`+TaG@`oXfU|_!&g#kl}d(a#|u!x|&s~xl}VV
zwUFc$^Dw`HnVlR_GLMP320~D*BH0L~txI^Nhylw<qw5~baM!I9P{hQFuqKrzB}~sI
z5dpHsrN7##vcR!JhE|k=)V_(Q=DT8C485mQxC{BNis@N2?XwWBo^li#xbrNLLr}cR
zVx={*xWC1AQIq{4PP?|wDl~(}egJg*uRANhVdU7o)(;KwP~PYpzKGDJ23pQi#agsn
zl4?rYug)f#N}4%<t|CvW`?zi%PdexQjk<yY2?v8u(c~()DqV2tS$SNSt)fXlrWHlb
zd?X-Y444g3CHHjWXE0kAX$H%#krJ))gzh9-xk3ucCzZyVf3Q<IJHn`CJ85^2hM=yE
zW>PJ<2;aD1o%{}pGriu09x^I-6@$qlgT<a`3R&HDoXA7i?o>J;W)v@2CQeV?XrV!l
zx8|JMq_vT{F;vVr7`u6wTaH-w(>||RRZ?oDK+<Fp<=+Os?LE5>MvF*kb;GyBAX+y<
zR=%UeE_6F;Je}zV?eH_e4#Ofy@_1b$h16M2xj2nAd=e@WFd}L{5{P0F`1v|5-o1bV
zb%@ImfSVllI{>T96TE=Til`jbxsMD=;6+_0@<D;KfKIEdK`NlcJ6g3O`q2sug1Y@+
zCiSVpTuA==tZ<%&vRKrX>aOBKR@%d$O7x?A?uTck4tcA!)_YDWedcw`_tY62V2(V%
zxToi}*g&5u4AeoBh*sFL)k~?ENLnwC^bq86-rNCBP~1c=ReIx~a1G@nuW;S=KKHZv
zM~Q!O+7H*S>aq{()(kC(y!3Z`q0ij_t4)nx1jpRb!XLE8nfq$OJ?_4J0be4xB1xY;
zfjtD37wJHtV=dxOK*A({z9|DBnXT@<ji7`fek(~9x|h$md}$^V*1pZC*Rfi0pX;o=
zgSBhcfxV(Q_$Vmrfe>A`>OQ+-_hT7<xE1oFNpOvgqO#axu01{!UCvUfXG?S;Jvfd=
zVPZ-5YjeZ7AB~7B5f2f0j2~v#hvOyQjcqxTA*+6U!AKY_6;UK3NVed@H}ei7uh4t9
zwIUOPqqlH&;Y+#o4}QTHk7KqD2g(vfWwo(Bmf2XIu#AO`3SBciw>^#y%1oPtPk-&=
zR9es1Hd>dx4ly<xwva4?Bt{YrhYZ4MU&!_4h}kXH>tzCCVjcR&)<Q&O`Ky1|W!}+A
ze(!{fhyMi>0o#du@Yyk0VOeqByVhlpv^<hwev~`L1fo3)sFmOG&QiSm^kc7Z`(JvU
z@ooJs^J(i;P`G>5wY5~JZ%V}dyod-X&x<$Y@zf(B-^gy}Gol}9x$Br<SRZ>a<B+!n
zz1tdld!&;xzw(k|5|XS1mux>IJBMXrcm`<pYvQgl51Z@`z-)~NpRLnSF&^^nZ!cu6
zx4yY>ou6q16?iBFQBWpV{yy5S{j|q<sw*B*#FM8R$w+1WaSF?7LsnW`p+!9QE1#x^
z#MaUyHJNr?M*`Wm&Bxx!E{SJhRAG7o6StM#EOI6{GFpkRj=T~}^7~WS)aEd#P(KYR
zY4WReT1d7Z_{QoiP8ZyHZ1k1D?nN*5<zHWF9r4;pmWpozr-<@8-XeW;5_MXO7MmZx
zcF~<U?Z!g~ZSbGX!|8-#pt5&cZQfzxbI}E1zkX52mEW0BsX`MjvqBC8PwWRi?S55u
zGn<4_rIFJPa~JWJEskUw55HbaHa}ZR)z1UsMaC?WL=XG^OYU>=74$%xaHHF`SNXH5
zQEM?=8pa!U8#RthyOH4uDDNC&oTo`TaR;7!ceInB^i@T@+ZwVv_63fYOX@NbbGC3h
zO*aM!_Fj@KZb$FsLruJDI&Q|{T}*>+9#ri_cN?`kzsYLN-L74pun~!0+t+(AxZ7w-
z;Xbu=ax<uR#xc-w<MDdMXsq+`h(uW1&%O}%+xeU%)8l2?(hPD!B!^2qufjm}!G#{F
z)rX^a=-+Lq-9}o~bkbFi=)1X!)orX;7lm8JZ1rB8kF()po0;9>WD9r<h3$x;zKm2#
zsGrjL;QTt*1C&q9fH60#<&s*PAcC+0UMfqO>WNW89kUcM#I4`R60zqe9`etL^$rd_
z-bAsn2N8li=7?-rp+0owYcsIRYn19+9A*^Gtt*pn5S;6d2ZTt_?s>Qdew4qUd-O~A
zT}RIIg1D2Kx#c?O-TG87MiTd-lGT{kT?W`<tsgbm6SbX|bl33Y@=|PwC~Li^*Q0a>
zp%EgL_Z&dMKrF%$E|lI|@GmI&2t$d&MP^rW*1s)Tmxff3UX3Q=hGt-;PECw#vkH%5
z1RD^kilPF5-|@IaA!3rRWj+a~F7!@HQfcYBBH+0WhSIm56h$-odQxCFeay)uAXHkz
z-yJzDlnN1$2o7#?R|TeS*&-YS+#8gob%cEw7VHfQv>W3nzhMy2t&Pik6gPOya;eCf
z0;soJax0mO<WovRX_z2N9%@EXFl#WQVBlAEa7KYjGeoc<KP~~43sknC+NEXKHt#Uu
z4&)uM1|nis<bY3^(QyIlhJ!q=;h8Ss8Wj-CBhWfmqw5GW3LJIb$S_-1&O#q;StO8Y
z{Qx)%&0eTf%DrNRkLIA5Ghr4~6nZ!pQPmKjj(^w-?YQ<jv>e>*hAb>Sx5V4b=0ntr
zDL8^LK%2uLieLsy#dD4IkBdQ*2S{**{1H#rkP7I8apk-N=V*3`gC$VYoE1HWQUcu}
z(vlux@(%?FQ;9vKb34hEJhtx-2i?=In&sWr=Lx)ynX#y9skY$VxeD)}P?}A#dS6{#
zRqE`zn!;|m$7g7ojo>(2xZ}2FD&CYTARYnYz9_SmvDg@605e;=>;T(P(lJgF=C;(5
z(#OgyyA8_u3xbAZ54#V~E)d70z&lp#s!hT%znh|`;6S(S{yWe58hcm0s*0IW6|K58
zs`6ZM_+X1Snz)VU#pPJdGTfPk=GFIc7vAPuZYDDBQmSkDY1bTPYgdWJwsJ74e;Wg;
z5eks3-<K!M+1>0Zi~-F6P=Ab87ZVk=EuX(0JMZ8>lq-)<G<=E~;zq@*Dmp)dqg|mu
z`E02VFBa^+Y{luVX|(t~Zc(>N*t|jyAApU$`5pg4!`^IUoGq-EJJD^0aHGHpOi#?#
z!ampsFR?5RV6B}{>JPkq(Oy8D|KDHYir4?UMu|C8w)v`JeDWW%5D_Ds_pWl%Q((P+
znX|?BVX(s>7IV*1X);kS+RuvMb-5Kqg?@l>&GJ*Ll#S)SjTdo70H-A93*z`|ui=S%
zuPdl`S3YpkxhuEMQSlj5a1zv!S?XAcc(vEsL0P<~z*IU=8-3r-+w}uXy!M2t7r)zO
zGTg%UYAeL>e%TwQ-Pl7JYxsZfIg)A8Dr-+Zy@()>lsf;a(yeZ!Z9STIFyn9^z2Bj4
zyWDP~U-|TmJAN1pW^1azU-|S}+pIuoh80OqA}@wRA&3I&H1rySS{6&G!LlX79jsf4
zb+t2F+)ZSgBU!Qe%sI>YSfb8k4q7076yvZvQgKD-mG!4)*`N6l^IB89X$5=sTRhHD
zWLeP*Mjrmo;{TO_!_+TKyKwRr)&!7jl5DHRF>g7}{}#2T;<HEkR3MG}z(rwp{$Cm{
zKH20m7@E#e*@i%V(baBVs*Hbir>PQpZ)p~8C;3G;x-wqqLj3H~5Ju09jt_(Rs~1~e
zt355+6YGv&J9jCYOIoUTEGwLEudshs9r0%7UI*r&S%I?KY?mwxq3C2ph&p881|B8w
zQddyDeEl}dmWaEEs1!k=DB#_^u}8K#$$%BQMow=Z)rq&XKy00ONyIQ{*0yNJeKhmV
zUy$hGfJ%A$d7o1;faYXx2PT1U3&Tn0uFDS^W&61M<N9gCCSg)*lkmr*$Lm~s9+4+!
zI0pXQAjuNeqV{yW+x#29piVvipkAxmo&kuQ!)<%hZgas+!$8tLZ_ptKKrqACG!^Lz
zvYJ&Mh_f2d)da39(RM~WzYLMy@gKy=#u_C@1`rAwcSfo?b4@n`LJ&R9ntaOs(V$B%
z^NQP=0Fo}_9SBjerQQ5NZDku~l-_3gHw{T!DtR`BnnIrz3ps%UhN!DP*0EfW-c(g%
z$}W=0e_ulQbQ$3CtatO`u3Y%cuer68P;`-$6bmrxg?G{n_D3YlAmQq{v|Pt6wLHZz
ztydaBHp3DpoR}6`?zDZa209grL~@H+yAE-t6yK4f*R)hQK$XQ<d%YrLSEQO#tYyNy
z!$#yJmg1-jo_e=R4yVyaS0uwALSO|{wa(SllI2M<(n2J=9E(CHR4>NunhGLJU9Ptw
zurH7-7mxlLA^V&{FoXp4a8iK0V(nFMFQCwm6W3}6ZhSmZA6nS~K4<ShplQ)ZbA3J#
zobT53LD!<`)>`v!af3W&JqX`{_Y%sMUc#lc=AvUJU&6Qm*6or8x;+6EQUbemGBpZJ
z#pOz6Qf+=84|CP;R6W>;_^s~!rhL89dj$j?Ig4@zLY$V3Qt*U=O!o$ZSU{Ojdd+{V
zOQ~+E<rb{^6aaD;(@4$&V-W@9G%ZU^B4KHh+J8{bXF#7~lVlp&4uk?@tw*49zn%*b
z#FEs04$tY0Gvl92|D150KpLg=9bKgUl7OkTFlCr677Xu7WoFjdtURybxB5J?Rp%bC
zTI33ni)W@#T?>?3l&8<O>B5>9#^jV|G+?|VE@Wv!lV~S{C3c-`L)KA|d$34?4Ns`u
z6C=0~x{7XX%iQ9VRSDun;3c>T-785Qd6tWpx)aRxa@a-I-UmsyS<F4z6Ma|opunGR
z7uP+(MC|bw!0O9g*0MCRkYV|kAgXh69_V6zEk+-^;P9DDFSD;E#C-~n03EfLHy8We
zmsYf$Hl=tkW1>#ex8j%CB)q8)hFzQeuSD_brG~qaaYV?s=<#p6tYCovZEdDPvZe{q
z&N@o$&TymqCh~rblV!|o{lz7de2Z#cWf3YB;C@og2TN+)OSdrX*s++q&HF)9u|UD1
z1o<5!(Q+RDW4t7^-1-H%J1KQsA6@2kYSXn$F&=~Y$WS%1-n*^+R6(gRTiyTht%B{U
z+9NRnMA4|JbbgDwvS!AT*z(gyu5|9z|HU0Vet7Idb1T0S*Iw{um&<@Tra?X{lB@2G
z?^JiiTrQ>Y<yZ5GSpC@cBZ-JTA<kdyZKJR6(h!cE7ex8Vua9R~%dUL&rvjEAoH1!y
zm=~MNCmK1QAZcAHtLMqP7=&UtO!5Jou8F+=ZP6JAaTx@ceQw=V-)itO99&QRYwG$a
zM7))L<CX_0{$m$Rw>Mtn0_U}(V)43(nk=cW_<vFCVwMkfp|5x^8zy81b{>O7OSFei
zIu~ynV_f$~&Y#-YhduUVv^6#fn|j4*0L-bj%(lCL_O6|@J)jnR{Otqt7hZFlx4DJh
zecdBC>ot(-0JY*yVL8N_1bJsSzj1N4jJ#2O2oWKNUyx;0plmZ+wU($gO0y`R=V~iV
zvp;=L<_>==&$KRy2(k5Uw-|_UH($!SCly#N{2TXJ@o{&+3yX26rEPcDhnNj`!`;Ch
zp!8;RKJoX|feJAUKKAK);{AV{<(Ya{m?1&MuX_^%%qw3WTPxH8uh;n8p<U+{c+n5E
z+<u-el?JH!OM}|2w`{cztPkLr9go#s1?b&X)c)bEybwtt4UGgSSE|$|;T;_hybUHV
zaNY1bd32w>Ce*0m7cY`tM<~CH!?E=-cc7!UPj|uHgsKL^j7`0mc)oiBwpIxy%GL@*
zsuhd`Wm#z!lrBJ>X`3_~4~9r{$67wOh!}^?ed5NzsmrZ3D;^!ONtS={9=>U?kG|!4
zNJz_v33}xRu{Xpl9?JCmYqPbOV>WKz?zrbYci@p;+h}UXQx8sFNx8nkAc7(~URq9B
zk*%HM6zOuM5LxXB!poOjd`AeGNc8a9s3V45IJFOw4`!-i0XHyZ1KM;gp>!P^w(z(Z
z4yuHBCRqr=i9vT!z8*w~*XtAqou>|qqzb0hoX^ygj1KJdpu|xLBnD0==nAZ_Q4o2&
zmk?9(s+=AAiwJfSqiDr&Vlc-{!crX?c$tUa4uZ}cfiAyXNCgCi(~Y_VN>tz#UNAB1
zm_<-NA;w7qNYVtJo<||CLdBSnLtXlL<5NGs6Vpn`*bTMbWi>(3vqB65$rX1>s{~Qb
z1Zc5QKutGV`)y*V_sHX)IUj<lggQ`mGyFyZ)f00ue5ShLSJW)qAUt_l1s)}k@ybV>
za*f4>9z(J%qLjt(!E?#8%&vG<7xk#iLVG!C0ey(IPXpx7VL)i9u%qXuLF}EmgBGI8
z_@i1qYTybWOfZj{0Ig+brItnAE?OeVm2z~LKZBHpL0*Vec=9FVq3|&Bh%QRbB|L2@
z2zVtw?<tFYZ#+;2eiUClN~D43Q`{hgWRXo~!T@6wV=kBi6x<sgCdw<{1JtOF^d(z(
zGY&$2<G{qWDx0n+qD^dtN!C}p+Q?MoJRK#?3Q5Lk25t8kMpY7<6njG$Cyr;fl{koQ
zRSvZ>>++b<D_f45X;9_H%%_K3P$fw#rm0mf3Iv7JU+Nn8>AUI#G8YwS;`)GRIx)ew
zH<)BO@vW{)x6dsSCBc5W|2fzO5vT~m;U`m7nY^MdBI#=>#i8x!7{pEm>AJ<<nkPgF
z16m1M(YwIa<zDVEAlu#CO-C#X@&bW!vut%piA+B)Zs=S}&x3MHX{Eo?Z_6<zx<L>N
zia>KQfgud46ksx_Y!@k$77C1Dss%9T<wkm%j6()C4}qzqyofn6CCLz0_i-!6ZOQm<
zG&(zlhJpz5#KjE)lZ+DfCEH1?gDMUoL#0?&6h?qXB0LUhY(!R2OiOSGl!B&L+RaIX
z6yW)h^M1<&QenXDGfYsn`RLj1;9kHBKF$UHj6=$nOqJ~>KQd`qwm|`uiDYhDWKUo?
z98#a{RfM`H$WoeXT;)2Nem*B^Vj0a{Lj&$;{tnyAM5}VIt|6CzJOI5&w8~0L8}IV%
zR<KpxO(%8e7{|z(otp*gvw7TMfMf{3e%h#^;{rEkXIPSf@lxA!pdOu&f!!Zg5Q<PM
zQp8GR!iqHVLn8@eiAH$FrEJyD1b)W7&ekbgaR~e@qE97+Aj%O3FHa9b&$IWno!Wv3
zB(S=76IgzJ1j!Mf0^67r6sn&mGD^&;AgrKH6fNK-Jn=j%Tr1Qiv6wxbBw3~M@^7NV
zZDK=h2frI10(wh_TwaY45y?uN_2iDqvZzT^{OECNh`Q2qjs`(YO^cC%Z!g;b2h`^a
zW4?pa%npC@LfVJu(wL@?IJ*bV0&gx(R;#fWwyR~m6XO|3L|-8p&7s3Hp6)5td&q-c
z(1MM$L)QmzM|*_NL8cAq!5e<C!=qdT1zk1=Pb1l?(U0MV5Y?oXdE$7948<@=uN2i|
z0J@GSw$5w3m<4I-H_>>T(QX_sc+xQp>uL}_=AHT(B%uH5YN+u_B_aWdMgX#fP`06`
z({Wl~1Q;zb4l)iF!9$5`)7)xTC9@$JJJ-S(pK>;mj7R@CN@PDC?hvSmFUciH_j(BU
z2nOL9j`UivvH?_zx=n+DwQ<it+xnx6kU%JG5V5*t-Mrv;B+LoWCwL(TLPf0JON^pY
zDld<COWP91<Aj2oRyvA*eqh4GisU>X9CZd~by$L!by_x~rhtt$V&=0o(R%&x1g@jQ
zX_3O+)}W*$n!83rz*LY@Z9uBA_clPny(7uyjl$MOOkU}HD2S%_kZ5ILRS7&lj#Qc{
z&UNvr4goi<D&55{-()n!v2+1vq8T|UE!7^On3Oix@Foxhr5*Yc=kc!Z;sRn12r7aO
zGV~p{)}yKUg_60fn*!_tO3Fho`n$f)A-kQo-sjL|ACLke)~K#sdo^DpN4y}m_t07o
zu{%v!s7H%5PWE?}l!ijfp{A$luO=M!c?!!_J$recC-kSlNmoWsepW>&@QThEtg`Kz
zj*8sTjMP;M0yF|Ho#mLPfUA~j&*00vDRxJx61hM5HD4{hz<Kw~Ic_4{?+0@^d#ono
zfa*sO?M-CyPmO{VmD&U@?{TjC0$%GpCQWK;Z@Dp}WeUAw;Ipb>&m3bg%u$g`x5b&(
z@n$^Y1ynZ%&sqpm{%ec2xg;KCs^aM^Xmepw*<BZN_kLr84T;l~6fpD&>pT=32+?g`
z8CZ*=Jv9&Ju6=K;$;ZZ<Eq4`jlT>STQ<ZvyK2TccFP(AaLu9t)F~7#xl=*WZ5qLdk
z@8);1SB>9X)iGtWIq#8hgevl#QB^7BPPgU0#NnOQM9`<bX}fCF3A%s5ag?WNX$xK6
z`r@>g#a_(7Yf`XE1F-fWHEAJ1JHX<hldaQTR#XZ}cIuxSdAx@=+_WQ)1(eJk|HgsH
zEH{Jsx49#?ZZ<M@7>xvhmcVf7*-&bK8N96I%Jvqmg|z>K&4oIo^kX;VouhYNypr1n
zI9P9X_w9H0FqMAjsXSBj4ob;^FunaKgR}3iN=$u*q^Fxk-Q*^n=bcyoBIdufY~ycQ
z@#_CIwxGXyTb6|l^t{MHM*47ut<p3fDV!%Z{wh<AY<rv!w?U%fZ~R`)l>dcn@~7|g
zTUTt~<V5ZT<$QZAcSl~r2FO_?W0z%*@<Dm-Y`W+_o4NIeWSorxCOL!w87gh&L%812
zGfQuLXJc-2xxoNUkMw8Va*TXFY)p$1sQ-}GSWZ#v><iT<%d86GHUgBVAH8(lz46_d
z`%1TwKD0tdz~(~xWLt6Bo3pq~9lPKALEd=!3d?5j3{uloki;uqjDh{`m7@1%9qofb
zlT<nk{@^RwYgZnnB}^P+#O3eRpxcp;JHf#9!DqT`J-H@y-GA`Z&Lg>HTNX!HdH52I
z@195Kq}tT+<-g*!|8U-xm_EqeO7X*dn>MYLEjthf;m6UCk*vXgD5x53QRu6;sxj==
z<JE`Xx_oKlr`>DIi*C$Wyc!C-t6nbyn|A1TCg&T`h3g=A_Lq!JW?kh^Ys7)@jZPC%
zI!{h$3Bu@QvymYj_~VQG)$ZR{&V7+B3GfoIg*$SI>_6O?%(qx9X<t)>l|M=?H&hzy
zD3ec~$5hbU8A(H;zIrJ`j(~qC#Fs9R8)S3TC8~?P6qR;)+(!*{t^&n52XW<U(?mcE
zWz0WM-9+pJ_0r7==*U+45BczJWGs(D!s84PDm9VI8J9~kE0su$5!a!xiAcv;JZkJv
zr4rAllndN7yDMxc$LA2JwX|BCuIGGz`<yyFj2u6&vgy&-)rFZLuRy?GXOC|f6mDr2
z8p*u4#*Dv59|0{#RUI=tIo*7URyjOBCwjpgc`BAed=kPg-q)doJFDweD$lPNbMuco
zvfByWT?{lg*oUj3-B7k%eT|)?@>~(?kRwW3DMC<tA%t}0M&2Jq_2|xiwaO|a+?Wx>
z-DD=2=B<E}yQ4-7A&|hE8#BLNOhogi&Wa2cf@1m4n+=~u@>*SRK{v70c1=9^a`0s+
zC}t(eVtV$#FS0nKWc~rB<Cl0_Z|<n`Gt~ET02_&0a_S;@>b+mv7y?f>H7O+XnddSB
zR56gjvMA|eXLJpkLCFJW`zfS1rohY*-Gjq?ZKGc}TCRrSp^i*P^bpLO(Pi_rl=TcX
zjK%Hb^=_{ox3gZ&4&uWljG9vXcJeWr3OdM%laA>qMu6~KnkWPu=!ou3c~B&S2sY!%
zI$MY7n=&`8KqZH{hy=ZB9X#u$((by`w1d#&j^vJ=r6zUdT<8*UTvly#KHZjTH0?&P
zcN9bA0tY{+X&HY%O{EV3($mpWs_2|&5ZJD5wRxq>$_4FG1unDI#q|wH#Z%4JDJQP2
z)@}Gt!64Es6@jK9=x{9>-gA-e=1nq*YxiE9l5Y@1p5$a_(4p-LEF2|i)GAp%J4ZGh
z<eBeLifS)NvemJXtFQeee$F(Nq^r~k^;%NEqO7U8_}aU?jT+>O6DV!62+)v~rkbQD
z&qW90%-I$ODBL}&w_c8TsSI3V3iIGs3v5NT<RPFXIrQS<I+tR02eply5JP!I;Y&M;
zN`iSgq>G0ct9kr1KHs2yWQs_jj&qI?m_k86Ilbt(N?;gl&<C}8DU6sBraqxdx0Ssh
zU(e<mt#iWtwh}sw-H!OUk1vB<zXFCWSbP;M`~cZ(sXxI|1iagvcCQTYS_%aCU7yXm
zPn=`YUjv2*Yr}oWJj0#ns{ek&@#+IQwxLIEX*TL^(0!4tJJRv@@-#n<p#zK?$w>~s
z<RsK?{MeQB78hGg>0ZyX7Cj7y%>(56LHFMLJ04=q0|I}-kIcp?0Ha)5Nu^S8f=q&A
zZuQdYf$)^uh>op^(X}Pnm)*2U)Hhpa&eJ3joPIc-bm%PIqa0EiQsET0CzS3>_q&{P
zR@-K_vbhsdE1Y}Lc{8nloOjdVz4y4BPeSg=V^@UIi?qMviVDPRnsNKy<FV3$d$8JP
zI^&SiM!E5s^P`ke>|gu-*ggK_jp<-0sfR?o<~?fXfAggbX#eSoNwUow^)9Z>tt-}>
zaCpt3XBG<fAGX{Bf8gD$o;xZbnaqCqLE?EiZU59$F}}ar$Ni4@{)6<NNeR#m02vPX
zJE^(W-y?9i+Byk+2XlTL%N(<{czSEYO?<?8ogh=BY}q;3IWpeLo2ST1dn>QJcsjf2
z6It$^^D<lcz+~w<-SO1BZTtog?dpZrqjY5{j<lU&zMHi$&dX%BZZ`UbIQ=!+{V~)s
z-~RQD{Gk<wv7<n(Fjsw&LAvS~FtgQ6Fn0NMPOa))msI(WuUuu{*1(WuN<eno3Cvcz
zQ(lD1cK0L3YY&I%g{3zhVf=NX5oH1^gO6`!&aa#w`<7qleqLuPA3wky!sAV5Yv%;F
z8zlDC4`wgCzP~xemt9`9M?SmJ2;7F3E7$I#cd6rE`+4UMzux8X88_Kh3-do7Ao;vy
z%P{TZWXlxzmD8`Vro}LiM?tUn)mwS+Az3g}Q#zXpv9-t<Huh#688U@YXEf*{Rj#1Q
z>e#O#0IKXmc)feWVQ$ieck|G?h%;!O4;-X>*=`5NNLnG8_8;E+u`yG+aclkc`L0t<
zFlkWRZ6!PSJPj7OJJr1ThdIT3Be?J{)DgW}(Xk=$Z2ph&=s4LfGA8Ys<>${`EBs`g
zJ=r?<#w(I!Hf-G@$4)bP_jf#o)ME^RDErog4R2cN(=rw4!ey><_l=P?6~njcmt4fC
zF$gc)AM<ddE4njvs~5U1K4z;c+eo&b;%ob*^KQ)@NZZKwq0t-ogsQO_=IE`#6Pe7`
zIG&-(8fY{z$lu{~*sIc@u8tb<vawtfQcU%x2C@YTa_d9zR5!y(S|K#1qeoL@?4{|`
z4)Sn}w&wfT#LrWxZqHE}u~XD}jaaC2UahCXLJ;TDd0d%SM(*Y6t6EwI2=E#T^a4Ga
zx<H{9hC{JZw`$AF_hXc1gClV(XmTqqh@edrr7k^;ab!@HB2&MYvMcM%h}jdScucoE
z(RBPZ^irYbB~WF7TwWf@Hx&9Mb*9rquaxr$4JtA$?d1U9DYpuq!g%@&*T5A6E+Hq;
z6#lw~@C|^2^CXJm%LbFoCoXQE^^3fPOt!PcxsDuIoAO}HQ!2FV-KSGL$F3yK$Y>iQ
z0F9+Tuv*ldMjkCyM=l)90<Bb@0AjqyvkhtCq6$`kPX)A&m;x7$?u;a*r^dC}9~}L0
zN+7k6Fr~t~CzPm?gcU~LMwO^iwM5He(ohV%1K8<3xeSg-49$G=l}MXmo%hEQ9M(mm
zZ`U4Ddm)||cu`k!n$e0Kvc%GgP{EO~U}k%~0mf%2d*U*w9<aNM$__E}QHa4%7SUxJ
ziKb)6zjxFP1+N0(VcKQIbrkRUMVb~D7t(ZH$MJ^i!D0afNG;&kFi{KR8orM^Y(wPv
z9?8%vLd7gFCkf>dWzcI<J}C*Mv=%9|ZrJB*-;lzfOc!zR$s5u|Zmhl56G*v12&))*
z=H!e5sa_IgW=hCXbMbX*+NSARyf-!^Obr`E#3&(StDY^w-#S>;@q1r#RY2^k48ou@
zp#aZsV*{o3^LcLvR6n>(x{P{GrB#feBZo~Hx(K|ti*8;Xhz3?nRn}mzY)iUDgT4@^
z)-o=0vi=JY=8=P~Q*DN)&ktxXV(9Bsk7-PjZ_Pya<V#8+Q$#gUF1x!uCBC8LjZf{?
z<J%e}T-I=bhcYoE!xK=?{tqSNidGy)O>jsrJbaP<l_~eoU7w!gV}YuV8a|1o8a_qs
zY&mz`+h3Rkn{6*`owP?Y;Q9?~E-rK5T5#?=%8nY-*y!o~We2mhVzI&QkhD&!Xy%VI
z_v|?|q?e%svURgp^3>O<tte%`nXSk0&NS<KDeq%Gs2NxoA<gD=6x}dj>mr7QtpjUF
zU-8;p5B~1F;Qov!V&|5|bgn~6hXUDJE$AAn8=OW2s+EAe&HTS`_#eabYUNtHAM>k-
z;oT<8)?dJbAuxv>l=0eJF(b9>{1;XXM}Rupy!`5Fr+V^YMgtfXfWCx?RnW>0J+q=i
zX397_8(c@PNvf2}WV72W$ItoC9@B~kQe>?|M(6Q=zVW0db}+!>RF`TsUcZR$zVm8p
zE=w<`xKG@Jx!h!a;@jXp5?xp4v>55sLKYtV4$+G*&wa_+sF8N4;&(jxt(e*RHhS;w
zElGKQ@Hada<}XH>?}6`D=2GJsB%37r2G4zt(y7hX?VIxP)#i%3^FEhNe-uU!E!e<n
z5Hmd@$^grplFWuqt`P+Tb%dc$;!vFE=Kdy|J$-s{U6q|Z{n!P|e3-MIJiuJk`m6gu
zwJ)kU1lCHu>0xl5#M0^Np{AwxpoMdf4M;d1e;60bFB0K-?~y^DY-1=RKc`H32KBio
z{<5GMP*63bKjM`;Vh2N)=mWLc>ejAcl;eI?DVmhTz5kJB+<2x{sK#7z!M;57R$Enp
z1+`PTzq%{)`%k;;eq^U)n5_(@euy5J3REfbr{57xvZe|DRp*t-K<LuM(w#+Z9{aVJ
zc-2W--*|!h$-@(^{rT(YjxTD&fvoDtAg$=PZJb*`;fDLLyLi9L{y4=K@m+Y@ERLFK
z*Qr-qZBqxhlI|;T9Sy7!Fp5{{)k=>IXozq7v|vd@k<&vfVi%N-FTfO)&YJjj6tUHd
z{Bm7}UU;u--)ya3OUbi*S%j1%s3RV`Z$Ir@@BkUat9uPahOD~gM|hUIlR=g?4J}C)
zF<XK2>)u;__Z!r%Br_8B5GD0l)Sgbtc#~#vylK25-Wo!tIuB|zLUL0)FDQEDh$IXA
zXwN~<&1n7KB6rb;Xv(V+Gb&aKSe_7p?*>Te5tunM7eivOP$h1`?$Or>xyElso*giY
z-xqS8<OK@>YEgIykfZ6(GX}ulOJdfFiy&kI+dXGf|MK_1J4VLEGC`?Ti4D+>fztI>
zwt_~o2bT2_k`k`l^^-`?=BnQ8L$7Ax?WBlgr%VEqrgNT{?#|e=`*-CScZI?{Np5tZ
z;-zIPt4CJBbSofhFh5fXflo1-P#}!XA_hBTq`cNL?>ZAa2Rs1~z8P3f$4`e~IJ|nB
zMZ>Wg8f2YGGN@Zqz5L2X#}hFGO6Og#I)YVirCet_5}dNtW-B!tsE}4Ft$41xst6=@
zO?N;wDm(rbg@Jmtb;m@7WLHlf?!-}kFXA^CYW=}$p;d{rX=<=Uk<)(F6oX{te_Iz8
zJ=}>VX(d9EYb&m_8S-YRICiB524eQi4hl;g<wQZHZuv%p2>0qyh*j=fDfzV<o<q>_
zSNuFb$4NT6xQ@AU8XX+!p~9I_VnNJed2jL#aWkLNbYMvpX`;WYB%BeSW40DW$Jxt3
z%yA*moT8WtS@kZce3zaM!Z2oHP@L|2HxXSz!q|j84MFAjoD~eZ_|eR8C?3f|qUwlC
zV>?B}Te6V8eh&E%rQy#I2)pB>-w`$u)!(>UY->^<B4{432w7*nTq6ExiSP`DkfKYt
z2Qi})?!DmQd)aE>CYWSes}>+3-0UmqvQ_!9Mrdw}S1J0Ty*#jHBB)Dd@gS4j!S5n0
z124HroLFKl9Spt5U=k^57On9qBFIa%85B_$H31`)Xa+saq{{7K&vq@`3g})!?_S&^
z3bg3%*W$rA7Mbg6_*Zo##4zYFGP-qzZg6y}w6-gp&I>Teg65!k@?)fK=xlYy522%|
zdA_#cwSQNE7PeNdR@N_#uxAC!_HxFLTQhWlSNX`wt;)s5Ge#~%xQDNplG)1l9%(8Z
zQrfFz_VK*0aMhR4=+?M9z?x=DXR5I3+tQ6U5FpFlU$bei?TgpY^F#dK=$1@?)ORsP
zY%?U|+d)JVV{&4Ba-+`w7O$x+@#6dzgoso6qpc<+Vcg8tySdlW3Mt&SsK+PS7YcZ{
zxnQ1wPE_oxE~eZXoV|))Ww&cadKW*Bxq=<(wAvcp7SvCS0ICHTvSEPd8asajehi0*
z{m3Lbfye&tX0619v{<L}Sd!UF62|l~9nwJwde%l9UaxRv@c$&{QCy$j=N{048#?^*
zsjJH%tKiVLU_QTZiDO_^{p=GN=gxvq-EL~Nb^Ov`D}wK@ZgwrDJ^ti9#Ek&Qm$EF}
z&SA@~D$A;sD@yn}-D6#MaZ9VM?)0sZXUb-v&4O3-)ZdJ;X3193yj>Quma8va$j0DL
zsM3%Mv(>Xnxabuh$)@8MS8pzEC4DZdr<j9o7<}J1#<1;vtY@~~41KgT)dyH<eLIr*
z_AA|~-?pkA#*8tRBv-SnV#8~)9yn?yn60)l?{KT+m$KF6u2uW$zDCBL%vLSFr)|!x
z7t81rv*Dm@FT0I;`o#JB%{nDKE6cAw$|WppvN!qWOQ-#HPh_u(#A><RNJ?cw)6!Z$
znnR55e=1+d)C7mYp=W0D_%ax+9idD3MGjE{KKu%nkYbjvKS52Rzu?YkGerM<8CMlu
z96|x%3j30X6;2iC%_b%G(K`>uO0y~R1m;w#sdkKzgbd~p4bi!e04TRZOJ*DNucg6D
zoo1GAKP<oIP{Tc$zq=J>^g%NO_Bp>zQQ0_J;g(rxl{$jd5l5L|QBgf36(LXneRc%n
zbwZ52zoFh^xO!{BeD&@{=iW>EgS)t~$QUzvLR;jO<(E}dVD<w=MPvf4LzZOHLb4Cb
zepGH{{Cg}9)%qYfPKCw)2Z~GYbFO+r+hw;W@;38EN7O2G@{6FHbIYyxNQ$-bAbN_q
zDMZLEeuymMfDE)_W>Bca8rFDXiNt{8Q+wV$ug6_nQY8DWrPr{7m!nOL%ZWVs%Shd<
zsagg?+#Q>RBtb+$60$H?!dDvP3%qnUZ(eP?WW?ji(ZYdRI6{x(+ZG()#B{$$?>df+
zFUrL-4&uagJVU9Vg9cOz<sQ<qTpGR+7I9s+o-QlsP{}|b8LII`P8|Uxjr}A`WF5r}
zOi*lsemoX?K86Kd=cjY|eJXbWB}>~WLT(2JkrMLjt4iJhV5PTsaeEH1+PWf*&%)d*
z?kqGy?+N?q-FHIZv^bt7pw@&IyRO!|y+Q^k*Vi)Xoht`%8AFO2=!&V%qFX32DrO}w
zcWZ2-Rpk;f{O>p~(jl{BiU`#&PhvFw7@H_=yN(`mRSRs;{zqc8SVyFEIt+5(YSG>K
zkQ$ObfjT5Q-S9J|n%JY_)N#JB)z-u^@+>9|w@g(d+^GOU`}X1#j(zX3h*4xf@D5Ez
zc^46GA`X|#lsHd<qEfP*kkx@Un_rP_!SxV3iT3c<b1Gs?Qbg{&UY9n%u7r}jk)I4y
z-{FRm-`z_No~9Zsgd_TqpkGqIlblu(3CBfPDpxJFcgcdVWy{Uf2y3=(UAd`LJV=U2
z^vHk)>y}7%0&lLm2ZLMfb17<C#bK6G_umCJq^O=k!`P&}4R$fx)-4ngEDp7_BQZ0y
zMdJ$>XEB5af(Q+y=>#iw33A0wH3NS=v7bL&m6G^$q0xEEua_x&t@vy_1!%uBOI&YL
zK=Ayt43>_nB&lh;ms72JMW-EJ;!XCFz`)m6H}jlu5C7aN*0GqjT<FKl>s|voYEQ~w
zH$+#Z9VT_A=c-i$K`i(xJ>A$X3In~`Fs+ARxOzh9Oult&|FYcoJ;&4C8GfeW9uD+l
zJ8@_A_f^*$9mJpCFv3r&SG(N#dQLmHVzo}}pFiSQqjQgo=ms?O&-?aw_}a!I#-6RV
zYTjlz)Y<aEG5cC*?4>BH8&U5i=!l^ZW0GQBnYa&0m%aD4?z*3thaw}bdvit?-LUeG
za;&v^fc|<2kVfGBNg0QNN*@pdZb0#^Lb5Z1`@<PEB#KWgaqd>O>KeyHL$2k<B9r{Z
zueK(N5RP;j&54l3n-s<F$GTdVR~S$&GK`clb^{7z6xQjtMA4oFVv)7?Z;}$|R|)>i
zLRpRNT%NaD|99IH90Amp%FiP;*Xq2tTZ+fR`|=#KHI!eCu5Z%Jm;v)X7e4r%RaE~&
zt^B$rCTmzCEc8vpu=zrVaW@*YAzaqr{}lAyS||2W<70P3olcp_ZradGuYPHTSLV*=
z$mn0-yDHVbmNuV;PkkMcu?O<=-sQ^at$GMMDD&v4Q<d{Ceku(J!dKFWT&tp;g3)kB
z^wYmcg{=M0W!8BE`g}<CwBBvy4)rwds8d7Z#;sxUzB|S3KvXB3w>o1E5`5hKl&V#I
zeUj<EAIf>1R2`n820$dy%odLX-HNK$kch1-A(AF0R!j)ROT05|BG|(f3&bi;-|9jT
z4a(N__&3HD717_VyC_Xkq*itGT+Utk+M>PNYG&(WE6tWYna$Sy%twb7BDF}kYb0GM
zJ7p`-QtHaRucnb=lfG)R;X1E-lPfu8Hbg}?v7x;@^*-Vt%a+y$Cy+G{#h)D_Xc5NO
zX@MI<v-2Glk$Gp9?l+!l1~nx24=)5GUK@YATvnWBucg$k2hmpu-}B(n|2=Fm0BMN|
zJiAQ&1rRMrWVQ~6$Ouh@t0IM0^k<}bOFmy6y<+vE$=)O942m5HdqBD%6EyBXJNHz!
zl){%&#4R48Q1EVs^X`sDtJu68Q_3(*HM+mPqE31@C4a_5+r{h5K+1L-PdiO;3=Vg(
zCQtw0%E=bf`@<XbWzrwhhHu=^CCYwGGn<g)*pH(@yGQo9Y$JUD_&qm)>T2K4SiHy;
z#b)N(x@iPcJX<O^-lC+vKAWs%Ez^-q<`?#}-ONIgfZ`{s{c^jZ%HB5WdE+<8VeUgc
zcIeTZ<xy4^)>5FD&3a@5u93K~lZ_#IuUm{;<8eht?VRyZ3Ys-mu(cCR#-9$)k&k)O
z^fXX#ID}m!xl`G)MW$>K9IwJ9MGdt3gD?jbT!F`+egtJmg<V%8N4j(=L@z;cm0C$^
zHR5bsr;SZic7T;_3J-J%Jf0<?n>E6vmJk&z{7>L|d27gAFJTXJ#x>NX+C>=8AVZkC
z*k_4)4ywL$LLW^Q5rONRYBcqmm-PH`%KdWrG<{2U7i6LtXJ@O?K1P5Fi68EB8pU&$
z@qib^h4eIUy-XkkJJwrfR-`lv93OM7C6C{|9O`w<kGyc+b!bdNJ|7rcw)K{Ml_lyJ
zd#@W*Fy(?SzTsOFlx?v}t8?^|y0e)zU(VfulC}^u{s&p_cg3JCz7NT`ncad)b(CjE
zr{Q;0Kgd0y(bY@NCQ3~s9zcDOROK6F2=@>cdp0Nbk&OL;*y}Ht@>IAjT!nL75s{yO
z(eRopgi!{RD-m<GjS}rqvgPgEyd6lf2p3%iK@RWs+bVCVz`W+81=1cDFW#qxsN_69
zs9QR$3g6k0R3+H~4<vt7R!k&>qYBq$D!B>RFdY<Jb7PJdy1~%2T5Hk+GG<6tw=?gY
zUlV2EHxQEc&rae&tDmIt%m*sL@*zAN0uu@brpjF2`QQyxI})zbLwN1(6vl~E9x1HL
z&qX;SK!kKnbRNEzp#qjYT;~+%V-+xv0x48XdGpE58lNtY?h5T42sDY_ewK3HKZg(n
z*0qm^Q`)%U$Z{Jv{xW0?9z(A^FB8}0XXX)CpE2>-D+%HMUm)q?8SZ;B9}d1pg4rti
z;Qqu=#pVlrsN)O~-1Q-3n`3UOx|RFsv!1g4Nzuwr>|egiR$Grj%?q(XBZ{HmMe&Q|
z_(b8d$M^Zv`GK2n6q9DDZmlw?5gaua=Y8}9cXJ!tCm~hoU(9xtaPvT1=uz%@&0|Wz
z@|M1ak>!|J{NN3KGxHfHc`N>WOch&vf|zdbtSu8=H6lT`vAV+Ws&!2$ym#$$+=Ue4
ze5-eJ@~{TmXEd!zMQ3{Zm*LoOV49@i==OJ0*6m3Qq>QEeIn3duy;09@(%m5?RKYI5
zZ2e8HQNw=VnNv-#QfrG+h#)pNtBDajZ!z)u<-rfW0~Dks28pe<YF}u^B3aI`e}rNv
z+xu_l>Gaj;R<^F~o2|S$7?1qqn-<L~Fx7nQJ4?<(o%WdW;YBhjJd!ORdgcNb6(eS{
zEmAWOW)BG9z2g4Er3(_ccw${;r#F3JEAxEav9a<#w#@!3%7y2_**9EJYGwpui)=S9
zwq|hP()WMHeeV6Y248f_1I+v$2rJ)1J2=W6jQSXVxcuN_-mMVuX@z?1VdXIpLeVN`
zp(vy~l_T)8&I|oVeEvaZWxCg|7OR(xatMVIvvlcheRq*qX$cjOnld7E=znW*lY;)_
zPf282?U8$<oA|v}*8Isgk+CewgTLWUvyy%A)Zv9n+^#kjL!1VSsvJ-S!|v6y8knjy
zy&b@PYq@hjFDH|2*XAA6=8kWUG1JAnSeJbv*P{jt==P{SZ)mNm0gt!8K!KM~UqQ;w
zSh8GX_)dL3cX12s+6z(dhc9fo4ZaImO-!wuh3l2mm!^XI(MrqDmwL2Ol<fx^uZ)Ue
zL3Yw}%~o3R@P0~VE9xk-L_^D>7zmMV12)YeDoN($(I$zyR3W@1&*Ra&&C9nGV-!&L
zQr;$JK&R={Vzk=YTU=z9haR=J7S|}k-LbEgZC;Hr*S>5?wpQVu$l8rc(|doJ7qZ(%
z%T|l3^w`VUKc)WPvOUHi4Gw9Mmu$!U?;AItoyfdC;NjdqW^HX>cGZ8PF4dxs+c#h3
z9|Ar=@V(_-?zRc-p>i%Zye?WeeQ{vB!}c2UlhpB}jTvlKQJn9Rc233+N^AfQhlve0
z87>SS`Ne^mVv?XURA~nF7{W`L-X1BU7zit9U3-dlLpN@R=lxs?v}U)F1ARqcExnvi
zG&Wd|S<KZ=OyoeDX`??IptPDar`&l@tf^HbOOJZwhq~ZKjkONI4+pO=B4MZ|xQh!d
zBXWu9+l5)rcqriN6|Hrt8m6R3Ak|Uw4{<Lt<`5N$Fx2!ah1ntCgG!!;gpom-qEfU-
zX6c<HZ&b(+QJ4$z%)0pnU4c2%N)Q_id&}n3c5)-x%ZYnM*iD;vi8d018U+GGK4sl8
zdNz>Om8M{j({V-U$TQ{6;kqo$>|ECHm>|Gu=tDEgI~u%}WJQ#bKnCbaK(^6MiC<Ju
zx_>L)0$*(5IgS08YbeMbqayZng=9ujDa8=*5rca_`?4+ZM_nb}v=h6iY^oE+Zyjnf
zYv9+p2Nl(4&~#TZN}HDzs|2xiH0dUl!brT_Y$F=OfWKseY%b(r2rL%x8wATd4_AZg
zrC0Jn)OB34sL|<FhG<mY?@ZO*p=?L}rsGT;C07ad_cJ<x1~#X6rrgUfr7hQyp7!3Y
z{rl@takMbm8t)njuF;A0cI%|<j_9N~TH;WsYKj<+;G1fA<4z`#ZXxlbKSh5)%)BZ&
zP}&4Ymgh+039jMTN_pGLa8xy~5&@kkSJEI=xkdv1hk`!~#mY|HRcs;m*vqj9JJAFD
zz491I9Z-pC=+xJ?t`)z?Z#VR{{_rS8=%*zw^oi;yx@x8e=-Kg*H8`hUGT*)>a-U*q
z0s_msN|0g)x+yd7{Pa>1*ze4~msC3iVjdOjWe~VgjTBFIi}oh36FW)M?okjVm0Ct>
z9eB>hTU0wC><pagUu+}H*Jw&%L<PSr{&k4%k;G{&9;GPA=$qLAJ4u+Ao-~!NQ!QF<
z^IjL+`7r*+K&cpVb8J!Z+Phv&h-%1mj+1-SuJS43Y!IsWkkeXjRBT*1>2=j;sp~H1
zbH7``!mBIqKx2Klo2SZM{{{)Mjk7O?MMYp~*CabB`$=|tyal^~%jGNU<)Mb&M!lLX
z%EA4)<W|{qN65{Op~WsfZHW^U%=P&DKC@E1m?=^=7Pb~$&Z$NQrGG6id*#<D(A@Hd
zGp9I_^_t-}@~pnI+P7-D$P|`2;N_P4GPi`;Izl-~b<5>B$E%`S{41~ilrC=bYx|0Z
zt#>_JR_S=5_Y_*wblS-oui?etpp%4UkQCGZqqWtrbfPhDn=Hj)7;xlHn8s}NQIwy%
zA^a>CokgtkmTb9C5&3!Fj?_Lt+2&*p{X?}6^bcq5rCW^<6(g(1V_0k1a~Md&8}3t=
zF2vT4<?*o-KV}Iq&Q|7s#ucSrEj?Ui_F###pCwXe>;7+h8V`MT^W|BXij0xnMET$c
z9_9mbv)qx&w#7{!Hut$jYT3@etu)jth|y}RpT;u;4x-9D@q#iKb+jtPrKfs1uWvI{
z&MztL(IDJl_~{oox6b_?M7Hlut7;&uwldl~pWcm^Ov5kTL(lU)jPbro<sZG=chN)8
zO13}z)HH<zOt;j!JNMdP_q&h-0q*L!e07vF7~n<P@*|ID<EO58F;gyND{FcD{tN3m
zR&6SiySrm8?IZ46w(d`VsC8T4<{OwLA0tJ!&RSz~+UYQ4Z#O5pqBc*=H=`|_-t?cc
zuC2e8=tX8*t6w&WeA$;n_gSpFJa4zdp_o6qie&j!pRT!O6KsD9DD#PC!RBLknHlz@
zbYNO-Jt6U}F{E<HXmqp`*Ev1z<Lc30qQA#}8VOFVB87}L!IPJ#>r*sCdc+p9EG_rd
ziySM5aosGdr?b3iMrx<Y)8jpk)B;LuR^R$L`H~@qI4!sf3Ytwz2Hu+5{o9cFlTEM5
zoxIp0`uOi77`^?(rfv#l^3C9EAF)kRiln*|CbIeJBH-H-q^H2-A3u0Snu<WzIO`(w
zhwcsR7)HODyXn#SX;vI%M5VHodZo7OuA_-((>!1&UFJIOpe7w@AhBNcJ<xR_x(l1f
zAZ?FjI;eiMW)9&TIiDRoz2ryL@R25-on$wb0)}mU$VcjBCOCXeC!sQ^qQZgS_^NZB
zu7(Vl2-h7)kVXYU{yBalK`QOI<2%{VdrK2Da!+GQBJ_r#b_1G#6vz}5*F@2qst@2w
z&jZJ~X*q)+^i^V6=i->4#g>66ukTu8Q@PXvv^WE8z-xIIlFq+|-mOwsoYlKaBeS5>
zc4uM2O9!UJ2Xu`j?ne0rLQ1qZ2^O%CNbnf;rrQ<M?T7Ai4-^E}n^sM1+(|KOsR|UJ
zVE%KcHNTUeYjhTcah27m;?o*Z@{Q(3(^ySgU>5p?RjIOYx$pE=3Niel2(D^Imy0&?
z5YCY`jJc%%#)lo%B!aU*KB;m9ey>s!#5gxr9S}>xPvJ4`b<}LAU=|PEVkKN2m}nzf
z3D(d;L91g&v<ok4xdSbV5SgbbohKSuq?F7b!8a|9ZEMe>_i_f-ZJSiVQ((VlLhr?7
z8z1o^nE=VVx;BDWVM5@iaEAyN<(r82&hllo!Z4a1dXca|z<gJR**JL*hf8^ZD67ff
zrF+w$jV8T(Cj2~iY7`kfXOD34jn1kk?4IUlj~S*WOdq<#hJe1PXi&zET{kVI%4V6S
z8;(bUm6i@_c7i_OD3LN(BUgz+eTO1)CFIjQ(p#*FgE<J*8oH41(O%3FU6eBzf<-3*
z_Mm(@-O@Fq@Ji`Z$5-rTR(gdEsiKgdi7I3Qx+nBn2RiBMD+YuIyy>cr+3ON8YP=#*
z;xhV~k-rCBJh2uicT$mL@W^vk);@}4Yzb!|uu_`htN0u`4j2@BpsST+t7n?YY(Zm{
zAl7~yUMnzM;s)QEK(hY)tU3<RbRxMjY4a1UVQZJ*-VpYVvY6Wsxbhjq3z@g@P^bEB
z*Xfz9Haby?jr)qvxi`6PQ}$!$sxro(r_<tWUB7;KE#^N52_LS`i%r$;`zX%cnVb6K
zn~I`Z$?4#RgI?uMy=E9I7+yz9!VEr!FWxO*DO+{`uZL`tua0Qgl6{lv+i3ED5Nxfw
zv3P$hkSs973D67$({kPw<*|s9rq<#``K+0()kK(x*XMjmNw13?qjtIwxx1;Lsv&Y#
z1h=?M%(}y!&Vn1iZzaDP$;RC`raO>CXrgyp2LmSw=jo`Y&9RX>;c2(ILh@_th6f{S
z$GWIVpL`t)&-d>y#?M?15XqU~SEpislW<qIDDXADjKr|NHLg*2m#w(*ytlZFmrRT9
zU$D41b=$I=(>tZJTl?Jw4Esy%-|d{@8`Agjd7LvdITMrr<r@#uWub=uv$@Q7ZcO2<
zwk~p(YvwK>TUO$NV+XLU5f&@I<J=3L*>Ia%=fne4i+zGb21)n4xA=&0xay3>nK|vk
zctXW5O&w_Of18Wd(#;n6@XO%$TcnrW^u$#n`5`{f_gQ4P#D_6i%V87JChry<e3k{f
z&TK0-|J#z=0h@H?r|5Eyh=liXR;OGrlLpD$!&fKatzs;vy&aBe&Y~@mN`1iyttx0=
zfXddr{-9eyAoT*nL5a<5wHHOP-~deHDjA0af-o4CEq3d=IQ<iu`^5hn4hkc~d-<0@
z%CwU`&3uN8fl<IV`a)>yk}@0t+h>bzb7^v6v*8wqXdV121CnZA+_sG&*`Qu#MIt#g
zd(j!CRyA5Lqo(@!5B`zN5-InoS23)W3^%<NN0^OEOZO<BS(q@h6{N5CCNFm~+SQL7
z3=>$(;okAFBCMSX&O=h(!|l*IlI1E@2P*anu%CkKP?+TPZ6oYuXDO&-aWT*YU_Qw>
zbz}%E8rLsnq%?FutZBw=7M-SBkp1YiMcuuZAD9A6!0Q_HL_xilI;)ZHR@s2!Zd;JA
ziS<jick@uPj#$?77T=B{VgZ}f%cAVrkCMz4ShjR`AdzEEl7$iSRV}g)f07kj)$fNF
zxzH-Pv*K(pKL_1W^<cuI^Vwo=wbd(5mbR8s+q|B^7rd`Q{Oj56w9GN+@$w)Fim!(A
zgCTtY$1n&V%`?oAa)IqV$$mE7r3r7HG2`=k4_Oa6?23?5a}T1F6qay&LZva3YjRiG
zIG!g)go2$%H3@Vh>^n)!T&S<QWN5-geskC?TzFK1MDeQ0Iesw|<V1nX0*{f>{{@X>
z_7gV9ouY<8O>>juE(c<39w#@&N5kOw;I#3$i?<wOX0*;w(O8eT3<+3`#xsd1ASPG9
zt2zbi?R14hA7=Z$fgTli7qr99paRN7Pp;8{5=WHfW6fP0OyRxULY8Sy9ZE*?O))Mp
zX$(T80e<EJ-{G_OKofd^%iteY0w&vh$1TYlnn4#?2m}gO%yqabe|;CgS9r)n3grqE
za)1pBUY7y`UFmwBUmCYkhz<e$;1{^8@&h_TG{|5IG-Wd+38V8=AmU9!KeY;3`BLI|
zp<@R`Yn;(A_(`Nbdnhz~BB^%YULY+3MkYs4y$pj5G7KV8#&a&ih*pS+8;a7E;?(8N
zMVtftR1<+8EygF+YI;53w^6Mn@;xnp+zXU#RHV3jc^2f5afsYPco;q=8*_zBTdYa7
z-J_T~*b^Jb6+I~nzCARTYJe?DzJJ)UF*=(QuLi4Wjjjr&VR$QxMo4CEa;Yxcg=(M~
zLKGo5FU@2Om?ad%q-zDL*73FmxB_lILZfzKB(mfgfpH)_4)fWr@Guz$FGA&TaPwE<
zkfZUc6AAC-AM4gS!9N(@Dg(XL9YGTdGPhPN!5A)`I4IhyvT5^+YUnIYxh?@P*d>aZ
z49XT?N~E}9VA;AX=q?=hs<Q;*Fvl+_n1@hjD-}nVvh8Jp$dGs)*|UOVD3Sjmpt%CT
z>O!6|FPDT1>EmaUWbC;~!Q_eOWK`J-HDNu~BAOzg)-91E-M1oXTNFQ4et-v$igBOJ
z8YCN~`;ugVS>~YZD2NKzgUj%2DzFdqA$f)ZvkW4v#D)QAUo{FJVrIC?$Sg%Lk=TgR
ziMKyUF=h!<2JbzRaI3dkaO=3CK(-v68^pbVLS#KgCCc1>Dq0bY!p?ICY4S0}T$VCc
z^V?5ahw=~?djvTkkz_+*lXj>A*k~Z5z3R>aPBFt9^KMzpx<=V`zQ|6Yl1Kx}uYrFj
zBiUGR6NlYWCm>nQ@=e)R@$;_J*kV3plQBCdvUbD9kt*-F#=-bj_##=cNshyyDncy0
zLx8{1Hx^Wb|5boKcY*{6HA4P*eo@&_4=EzGWw0Q=dw5Q^0~vY6N(MoYlk*dY$j`vn
z*CCgXc~Pi;EyE68LRt=WgoU5uC{IC@Bh`3$B$nFPnIICNBa)u*33WC%WWfk)Ug2ys
z-!)EKJSc5U43c0LNV$cCxBJ5zzSeF1h|z!}bAHq+)8ne<ZuMmT91ivzTOc#tRR($t
z>W&Tyt@88oNI*&E<%q>_@QI`(X_W^HSlN21r_{w8`1;zvh$LF5uBD)W{2Eb2^9duV
zG(-~LF2B)1MLxkV?nq)PP$ptW#D4fM?}*>SI}ctD4ex?vWayzWCj!N&IZvK+JZ6I0
zw<0v)j+z^q)ZKD5CQqAs0Mp{Q)R1+xFRQN@67LDhR!fm{Oi1#ynsDR6!`gK{B3J|j
zLB;t^bkl}7O0D`7T~}2&MkUWd&){57I^+nWn5}fx-di!zQ*hiO2?{Pj87RlL$EhE`
zg<(vk0jx;8E>>@-ATU}ttVjYsf<{tQ2kGP$sQ8qr(hY`2Q1VvH&<v6#UL=t~fR`ix
zD9>rp))17!Emv;J3p3%?*5pBQMt<p<j@g^10%JybD&>uZ;27cOT&xU`swg7@W~u?z
z)`!gwTR6p5@&Ki4=yH%B*`^pF46S@C1>~8LXE201dSb&oda?i&zkIt@Fv=AKj&>)*
zmOgh$nSmpSple_?g9KB#$1e>bnNQCt{F1C7D83fiuN&d^1}pRKXx|T}0ZnzFNME7u
z;|F?F$k3xm)e_u1rRjt3`|vDdC`LonB-VMy0IJj`_EEt<msDZ04_x}NVMES-aF-|S
z3dLQavj-$_8>`bL$wOeL61B8DOII<{^#RiN=I#Pr-Mw;9eAHDi&eRAE&xfS0y5Wn&
zAT>$nQ>aY2rNAC;kI&hoi(miIV*F%-q4yX)*V$>#f<2jo)O_8;ue8|i3lL1Z{8SQV
z=|Z+e%VSX@ckd~R@jLD*v}ceJ;{9M*+7T4)f5E+T)dItu+}(X(!``@Xm(#^RQG_~0
z8U8t%H`qeXvk^<<H+Y_2?^d)*Gi&=#L@?iA0_08Px<&RJaB7K$IElz_uw=BU?pvk<
zutn()T~Sx{pSQ}6VYLsC+yg5s7DgfT+EpWK`6qcut(5NEi3ja|WPq)^_I))OOY~X1
zBo?+R7McFnT|WfMBJMT#RfW%f7F}P`3{$6{+XVOGt2zmfP%tf=9Qt+?UA%`WPFuGi
zzz)HvBRN>`*ym<G@b=*NM#4tHHxUiv&U=}6Ua2(6Klk-i#|jSuee$mxPVoH^&E>QI
zuu{?amA4+*k1Czd^55ak;xiJ;c2%oItkPuDoc7{P<P(iRTHZ60Wb^w%zBDMmIxgy3
zTpd|cpl@HfT$!>=;9d2>tjwD+I`$u?vD$-^oL_V&y3z7O5Fv|HEp0B$Z#l^4<K7=#
z?4WY~osVN|HDYxD$>u{GFSEz)a4p-+S-p_>;ZVhjR$;tEY;x79s2W%P1Fuay5x8rd
z@6`A~ml(hBNtgLYZe$`5wyH|tAvBqmOB5m^txcU^QG(@?IQbL?-^AM~?PepiZ+-<Q
zVX=_&xg%qFn7Gz^r5Oq=Q*f|N=4S6X@5x!Rtw`|+vW*sjCY9~I*0jjhS=s8QB@*}3
zT_y-v$cdNTmgRxOrW0KUK_IfYilJWl2hPRcZF<7COSLmg*VJ3cvB&!2Tlo5-7B?wd
z(A#=$=}MoLn5OqL6ZWcXZfW@?AtO;a|Ce<WfA|NSNW7cAEO#e<Hh0UL2(Q{23^BKL
ztj}CPc2Guso?jpQAM&R3FaM}(w>zPa9OSur<1(z%+Y`HK>xd!W)Rr`EK0w(3>Y<-N
z`5hh~{)eI~+CRUhH5TX8%xr1rj`Q0t{@dUQjsQBF_8989ixI|lwq&Pl?@kP2oo&tT
z2J+v`D6mL=?n-X0hHF$ms29eOGpnfvT@b#TwWAx0mjnh`6G`DJ+xrPe>MqWfu1nat
z&+tn8oS#+MTK4Ag$r-SBGqh;t({Y~n%;JipZ)EMMdL&$JJ0qVtFSH>Ej=6DHEig|f
z4UHt32){x{)gums1xdsTey&(G%xI49FM>o8^tgKbi6fp~-R59Q4VhNE!uEhHLs2Fw
zFV84Y=1a^3NA8xhQTrO}>DKD0f3C7OT8<7cnrIwG*w4)9&c^8soc1y@GvyVbRDo%w
z*QfqqJvhfXUyA7|rLBO#d*^k{ks@V=amNf>3P|C!78_|rZG@4X*s%mQf>+AD!DFPk
z4EuMxJbmK2U}XT~g|$X3&oHP5`UsXK(kZt;gq^7#=E-B>4&_>OxEx!$uzD`~>9~SU
z4VClSkqWuY9Wfj#)cF7`J^ZlN+B&EdXvMz;F_H30@<4&Y1P$-z+1JJ`>$#z-4Kk;n
z&N``TLobm?&khm!1WRT$_2@S&XVlsuO8!J8rF2wh4R7_hgiD17*D2ggR=9c1->U22
zB85!#8h=VYQ#lujfuOHm1^0%s^Jd%mxF<zai|V(xJ;~|_R%Uy?+H4IIJmNe>s0(b-
z!J!A1p$=}W3teeqG1cIP#Yd#~6X|SDLkx1FBHR4PTen~WI9%CrC!GeV27iW2HVGmf
zUYCPQVu!GAL`&wM)@q6n&0Zpf1^~)2J;$YUUA7A0qedL4C_J9de6GS%G+oqWR361w
zD(diqATR*el-EY*3ksL~V&<J*<<Ss2Og6$AIBBRQ_SF3_$%2)@Xty0pR7bSjIwyrj
z<!l*lQ|;wrUWvXVfhSpF6yh%Wjb5nOUJPJR4|YA`bojZ*kG5UtIy$Uj+AsIXE1R+j
zgrjhQpJdvGqUZJWoC<i#8H5bd??CXic5{1SBa!-)Nk3hr?~RM}i0-iKv~m^}`q^tj
zM4*nE%;g1cmBW+aS6|BY6u+ok)Z9az-KZ5olIH;0OgxH-Q`w8!n61ylX1%?1%}OZ*
zAA2Q5LALL~K)stcRqYKpHP$U!2`1QVeAkK}=Owwqee8<W?6}4*A8{U+-?jAAGhv0m
za3I5WqB>nHV78*BkcC%-7RMB<<<*VuHSr<Oo|bg8h_vFca|)_6RgQ6|e)5GerGKxU
z&%m6y1D&YYDYKS0$2_xy@B_9Ex-rbwF^&7iF<ZezH;368Rv6$iT3RdIwKTZSIazt$
z`#i(P@;H;3s~HM;El0T^`i*X1l8lOod`66S{#-I!8HJ4ig+^XwW!*@h92S7w?$cy)
zNz=XfbP8L<Kt~%Db*!kPS;j*jwFYwfGp`6TTLa&rZ@-0zx$@cl0sC>$z3$Dq*(Lta
zQ?B*c%1z!q@Slq}d(z5m-I$`Q7?@oh*_1+q0yi-N&}&gZ{LK5@>Sb?k*`~DxEU8yv
zQCdfaUNOnFiHc0-I4v~jlaLbGee&z8t<hQ%`9u=9iC097km(qIe9kK@!&hc279Ab&
z&wwyfc#f8LC(RWr%*qz0j_WKT&UwV7$=HI}TB-Kse0CzZxhJw<pK;`UFmxtm{%|@v
zCsy~@<y204Ll&!>U2*3}kW55WVjn1EEa~s#6YXsNSRXyuGx?Qi=Vxw5VKg)Ct){Ko
z1OP|RP$mq^{>y2%)Ml&g<SZ}yg4^J|M|R5I5t&Y4w2EmL^cLDkV7u$EPW>-mld~Ds
z(mYu0qcNs4fn14A8s7Tu(*4M0!(~rh8d`^+${P=gP-*$@WGej~@8qsxY9bhmflhEY
zDt`44BjK+)zmeULtF-Gh>?2Q5beXLu=20WHGaueU4gMj4c8qz1EEL{lFPpv2Z8YZQ
z-;2mmrlvh;H`dS@_v_<oeg278wz~flua?#}chu6;FevnS5ShS9|B#0rN&NKh1<Y0o
z+IEXO@B_RwRqt+>JUd`B^ZJ6(ehf?72uP<w>=XPtO*%_DtA{ydB{R(Y#jEz&qZYkZ
z+8W4Z7<78pY3t+_ltA2p&BP(kjv*5^X>=cVm#F_ATe`5w<G<CjThFZ8vNfT@zi&!1
z&Vw)(108R%LFw2ISS)G93Wh(z+W$lFj{9N}XWdJ?%$9b>K9jp^J{gGb8kt{kcNI@o
z6@!b3^WFO;GBzo~IOpTvFXYAN&Y6^W&OOOk`OsB(E_WP(Guq?uRQ3c#jx=i^u`zF|
zW@Jnigc}%fj|7tJxnM(SAycHsCk@0p8})x7AsG^So(!%_^oJEaLfaIdC_-680gn<3
zB4ulvPch0d4>>sQqE=*yt5+mqqGAo`#p~AtYQ(ThxqeYHTMIG~6hRqr-y%q~B5xNW
zBA@{cZTe(VNB;rG(PJqx4`YZsPoS`OJK$F^|GCX3k?rXoN-?`CG@+7+Au42!Jl`Em
zxmFC49o0$h7Be#n#z-Kol*McVKSfppD0E|`ppp!SBtE1ncN!J(%u~A42+wfMjP8xd
zlKS#_F<Bl5>P$BOR&?B=)*;8t6M7ynYqUH!0h@Oq6T3eSbifos3nOU)&m|;`UP$++
zlFU`>cw3k((QM417?*o@$&~ZvpGL9{pC>Z22GojS2Rgy6k=+6`;W=~~lJ|g7`D-#~
zTJNFuyavT^=VeAw;r@TDy$_USM}6N}_xA0cJ2S1(?NLj#Wc{fgwL~Ke^n@UhL7?hZ
z3%5bUjUw3-7AsGRG8qT5M*&RaEPtw7Evdn>X=C9G32Q%OZFVBFL^vdeIIMFeLC!2k
z@tLrAgW33OI|u71#Be4)tgT>S@8|ogdtdj=bienU?63RP-(UUeSHJpm>sM8`u9u51
zwC<#+Act;~uGaY^$a(En6yPLs`wINHJR?JwRhT?ws;Ui6?nxK+-%r~?XbI}(K%xoz
zqg>w%Xa2ywm~Jd$B*=`9#<RCYHZ52JjE59fH=+7~huFwc$b`!@40tK&!k-hG=TB(%
zxcoKRg&i;KWj-~7;DBvzW~KslEGom`>|RQa31VYUqeps42_g5Iuz^-2-@>HUq6Imk
zJ1flMj+@yS;ypC(vma`{2_0-PWIeGXi-v_-RjkFq1a+&msMMy4D_m6p_%``Wkhd=i
zd4@pQO$ec-rKLNynF2D+K^(fAGGbQ^XltrB?z(F+i}8p;5M6?_{3NNli39V5H7qvK
zL#;C3HNke^<f#RB6ty*E<7;Fx3cQOUZ~eA}nVs=bu6Uu3`Geyth%-)dA4_IS`f(qU
zWVYnCZg*w;<~6;tdo4ov07+0}QCp$(ARpTng`x1Z@XSo-BF}6opK&KuZ{&5A3*l?-
zTRGaYrY+8Wci%JYLqc2ddk4$n_#x&m590aaK4xrG#Oh0|N&#`SY=xTh$YXlvXKoMj
z>Z6iw<`I{NSJ665ZDpQQX#yDBTAIhzcSLs7Rqsr2y;jB1v?nL054ifFymsLs*RAat
zLOeQm#%!sITTAmyf*7Dj0h=v-X%|cipZC6%6&Y%431e{=oU?-h-twos3r~(E9gs~`
z6Yw=}q5*!;Q7j6YUR)~NiQ3eU()OmZnKN0Y-Ky%)%Vlg|shVyy6_O2rK-}dYVzq`j
zebAh~^RILk)jfUn1q<cmhfrHjjIC>v*WG-&jM{BQoa}S=u6EhNn_0YjId@yVORN)>
zhrh;N9<jp#8c|qJ{_SE)JGcH9FSDj#O6ufQMZWaInYZ0mc9M%tc3Y<>yN=Rc-RO9v
zr4^R$t?xZjp&-T0?zF4X4;wY`HGxY?LD@1*rN}S(P8Qbc3#sE_P()8DGu}?4u?cx+
z61Ar4k6c+l&m!slqwKcMlR^UXNo}Q$sY*bSZ13c(q_#%8aFdvzI@UXi?gDNJlG+;n
z@vZDOGlYFDFm^uvua$lXC|gsC&t$#%?C%r-HBkc&tt2iIahK_&tUCnWiL<6<8YPkp
z@!_kAIjOBb6Em;UAN~0|vs~@tS_lk;h<pP7**o9Gg{KrD_H0eWmR-VwIiJEJJ!&gz
z^pCsa%hyAFj6DoPC8jF=ZdpC;#(Jj5UmEy;_A-MfR1Z{jZZeZFgPQof4ip?co~wZl
zWXd8VG`P12r3>MjAkIzW|797*e{PE1)_88zAphOsPSDpML#u%XTWV_~s_q2G5pRL}
z%`b4YkujkRY8XKNd#@~}<HxHs7NxMgO&hW_nCe)D4%G-%<6b|arkq6BgrgJbv3fae
z^2-?;UQ%1@fB{sUkQ8e3jbg04g*hxma1{fEW;9olyS_mrh;uSnSIK^P(am4q@#(Q+
zQ5=$tzdz@uJ7d9jXZCaKB{q*g-9fko^MJkUthWaFiWegv5^8T%x9B~Lo;~F*KeR_Q
z48|rZ`n_<@4WBtTfQ1-;*v2@E(PYJIa=#6Dx`#KD-=1-HxrQ*j-^Lp3qR^>DNRk44
z`4Ns8N8E%dGI+2A%Q6DL#i))m(>zN9Sr$hK{)>R7vBAhUwW29~6on1FGLaSOsIx94
z=%`r{Yv3E(W^X}Ltb>udj66;oE<qqPmOQLOmUdf7Y%Q}*ySq(UwcCoAcLQjy6CN$D
z<z_d;6b7-gAS78Ttd`+m+5qme`Npj)Udw8gC=c@prr<}=j7=vu8mvJU*?ye_&D8dY
zP(8oMuPc_2lXx$^-275>F&4}{Co`LHvpwv%hGsiixH#{Wau9_6)D<z0MKL@@xvYIa
zKq@TVQ4|O*oCY06lSLbv6<VhOayH6?TYN;hpvKS%wd4^W9k+-X6%bmv$+J5IP%ogk
zW!erpABp-lfK=&Wc_avim6CRrRj^4o@)p_{wQR+7_(>My&tUtB6teaZApxZm?{XaB
zVWQTPDs_XAV%9?oDPkD}8mC0;R_a!nw}wOD#q5ys{tGY`?4p;Z`EiU`ybObaiMDW_
zRS|$O6&eok)xoQ5s=64l3Pye9`h=mXs+Re|XuBSent){D6>bpRk~oX<#1j~`xDw7V
z=m{Y)unQ`Tgx6{Re4NV}heHOJu2|>XS;FPw2RQ<JU@2gS85;NEopMCpO`KX_)Y7!S
z9b`CbPi+{926=Z2De^*@#lgXtmy<9-YFx?9T!hUwMNHCE?7Y$(vKC5jp81;bcs`?T
z;&W|eqoffH#iBy0H{6$N<jfj>bU5^NOP`Z<;!*)Hve|RaGlp1u_N#Zf?rb7u@o<H$
z(py<dnLCo>+Y6fYRyaEsj1t2U;S(oyGXTeZQrNkeJN#bm_rk_W5oETsww3q@m*o|U
z{OnR)6njL?=z%_m3Kmx1P3V>=e-2H`u2TQAUdXnlLe{%tz2nALi5dc4^8J~G{b~)*
zhQC{dKK{pPkjHYCRxj!uj-Mj@yL#iqF+O|=4y7A!-9z4tjc!Zdh9t(O8aRf7%INdJ
z6o?8wv47K57vcauvgF)Lbk6w89PUfItwcP{vqg(~Zc7LFKTa<^%|}Fvi37dvjC-P3
zJ(!Ji+e;q`T$64pFSHzSGF?@(22JP&iE9vuGo2>3dE7Q4PX;_9?D=s>*j82p?x7IN
zKVAyWA>q<};*ZuGJj7qS!B;39nx3b}oDS03Cm|30=QR|$1vhr{XZO2j)((~K&<~UC
z8J26unODv%=5c7AWZ+KT$tIKd{q>)UHrOeZw1OsEDxAsw%_n1wijhilEs8@NyTGH6
zP`yvTwW9IT;a=iwC!AVW5$Yg_hsQbl^k*)!E!2l@mB`%bKX=9I58hN{OOzz3tuMji
z(TTjC+;WGdY!!9__}k7ua3gcoi3ip;j(#F{y>7985`rdm$<38Pqx>5C4p*_yBPtxq
zRKzeiwWia=#fO=!2{k2A@zM~k=6Cw}`3$vn6l!2ovT)7a%)y2K*dNbgI&FJqM4+@`
zv}&uA)M<nrzxaL9py58PFLG*2*{2fFFeUy`AUEm=>;T!m=W-4l1K-%3I4pfunqTFq
z<LYwm2a$HKyHQu9wtnSRSIjGId8Ef;lWDdj49<D1;b2E`pZGpAKHaHu28Mx+pQwsE
zP+Q%zoY9@R35Q13@W@zpfNV{}{piX#cUJhGEyTpH%m=ss-^_-$Wx3aKbgApTqey8^
z?w4*a<NGenJy+*M-LPsRRqOz`e+9&GZZoyD<_KokfgKS~7-P5fCsw)?ei+an^hmFC
zNZ4TIMw4%=f*Fa5ZBHAarKHYwNs!&A=LTbTafTR%nUc{XrbN;xhXI$>iZTn0q=JA8
zZ%hx2|3d0|k~zsSnoUh@hCe-EqpZHF7*Si<<sb7Tp_G5`@LEz1%{ziot7u|)S}R&Q
z`TJiL67%pjBp@|*3xBxQDHQH*p<j}%jf`bDnB7$#XCT)2UmVKs>WJg`h&@`f_-<Vj
zCCEbuvvOZ7;zYQZX$~8*1Plf^Qz?DMZKl4Dsz=N@U|SkT&Ivr<%hE_2Xma(g*Z3E0
zRwkzTv0B(f@VKc8p?HP`4bS6IKE_j_MgsXC3XKSua+*{i6O^V<IHM3FSs%Qz(VWaM
zJvqfAii|Q`O4sB$lY;g%dlnNgE1T_;RW#zt6j;W;X=<y=5ZRnr#m?|3?<0n^tZ+1{
z;vKrGlIgc*RpKJ&C-4ghGCob3JOzwmdePhil7xt?AsB@;3SloqfmKHjj^$}3WFGvv
zSEveaG{^i}05!ggfY>E7G3EKy3j-J=ejCUkOhAk$6ce><(_^7WUbI#dv6dS(HW4zv
z5IBkREs?(#lpoO{VU;vy^%1NDEt{=>Py1ndz+8&;ngcwfd}5}Mc$+(pW#uE#mWC)B
zA!FXMJVn#mPu9x4sFpA#rNGYx<P+tPF~@M`$7u#ecQQh8mwqSgoluBymk^OZ4?H1A
zV|9TnMrbcl1ZLcX6-;hdn@J`Shki{-vDfA4uvEMzhXE`*)F~hx8wg#TlKfEc!WawH
zX{-fh?-3T+q7fj3F(wEs$Hiv}$dw6eJ^47c110ur5xE*lO(;A0iXRR=?pd_$VdyvO
z2T7PucbwZqe<&`mRa1z9b+)sh$(RD7I)B5WdL-(DSHtLYSF_jtEOk7bFESJOowO{Z
zH408`h;9_Mgxp3Autm<F6EA;Mm>Jmq8u?gtIhAZetTklr>OSK^QC`Mqup+d)X`nIS
ziTs<NO588{o}a+-N=`&|K9uqNu(Lya!zPrXsD-nLTJtrXJGRNXt)sQ=DKQttlz0>$
zai@?i-dZ0qbNm9o-TR*+&V_JpK%aVXDvP0an_Hu8?-0a!_)Wkpe5r`cP9CzL?}k+N
z8+I8uw8-z=e_9RMiTxDjc|7q)o$LK^aQR<*7=`{qcWK6M>rn7I!*z`2cio}<v1)yT
znOC!haRaU9cG9!k>Q?>~#-67OcPBirYq?jk4^U`A6|7*eoIaraJe^8>427lwuCS|_
zMC;5x^?*LCSj1DRhcg7S!O7<?acpHlIN7s-K_s7wPlsPEeO#R`=212I*oap76O?w3
zY2(o$;m8ifj`>SJ<{SqvVdWGd_CF7j;?tu@6>{=hx96KzOav49If-}mW*ebogYcE<
zeTU9zI0txx)EZfkN8-?E#je?Me(2UJZ7#ASIc*!E6TeBwd&V<;NYRh9+bW{_-<Rd@
z`Rc*EI(!qOD%yqu$u=(kY?;0N1iQauS9&+ao~E{Rd%y5H%QlSPd#KbKOJdnqT%Y<F
zcU;zM^*$vZ0*vNSC`+$*6oF3lryr5m#`GxHlh@Ip?q>13;s(+<`HFOGm=9n^O^nvd
zxA^R>?%FCJdwuj%k7aSKew0D+!<tUHp6YgS|I1AeMP^0yJI=>i_dpH<u+yG0+MyS6
zYA0zFBhuaZhhY46;MBWwUHpT=6RpOe4MJ8RDz>&46d*}T1MLaH)(9>?4!@|aNRq|<
z7pQA0Fq#(l&{d13c%S;fE4;hpI$gLh1U&KN(v>ZNozw~hK+!_=xtG!Tj}oe-iO+su
z*4se+lhm<v<2B*InfJnfj;9=DU)g$kLjECue1cHcZl(y(s_#l0W;1n)=(4cpPUwVw
ze?^4STDF^NH<P`I*ma+D?rIwS^~e1}?Jg_q$*)cy`8{EaCOFc;YOb{nxFzAikaJ@E
zC5mg=ff~<2k52ElevHfHR=Vrw#O>m3mvYqzxOy3d<Na9_p0+(1Qxnwm;QB*os(QCI
zN=dy*5m%yhXt0`l6YI9OFf@j-yx6*DIVBoo_One$G1}=CJX@LjtG$_V@BTe%AlY6V
zZfqXBE7wzzWCBtghcl0ZV=og%D!9*$KWw9mh3;Vlm5FXO?mtcii{YnIukcY?IQ?y|
znw_sN^<<$<-lnvswia-v7NpfgB&F{_{wl(cXV;mR%npD+ryq;2fy(RTPWj5U2f!Jk
zTqws7?yleoU1`XaMZ`A@44H9<XX(23!RFJm5w#zfX;ZJDmm&*649!^9GcUDRW^xuy
zd{S#IZbTz0uas@T)!D${_=hW2GrAQX6KKJ$b%}P7o(srWa!t?+gbsoI-3CF`lPY90
zg;Xu?lq5P)61kWn+j?PK_NxT)$W86C=Uf^}T0FCr8n8Tka+)m7xrdR(70sZVq}yU|
z(SsCZctqF^_XwZ@dHr`F+{<t#SPm_L4vv`F$J~Q^fV`23x49$*^mUh|Gba(ua5w4K
z)9Z6Bk-;{DKvE%YRG9#ZFMTCjo(OBUnYqFG;JjjvH(HR~@hFCutK*6%WGkT&FwY1^
z=Egi}TIl4L<E*J^QBmLZ4iRT~RDqtOY!1aoaj7*FT$$-Pi5CN5JD_&us>dJr<x%Mc
zHWx_FJ<PHSsY=)PK!Bq7eMB6j;b1RBh36J&5;>rrnfw;0Y=So@Pr;f(njAWW7`|dW
z_)_h(lkFxZNgxR)1{J>-<mu7aBKj|b7*g)@UEIomrQ#5=tvFaY-PbMcNxUdrD@7&R
z4Z3;Em1RdW9Dv?uHVsn2iV*Zm7m6l?K*}cIRg5skq6y{Zy9+C{gd-_YV&2HC&|3HF
z$mBC5pPfkUK#BJTulZ`&JKnl4eCgx56N%RW$W7F>eU#95HKp?e#3ryEs8W>GacH78
zWs|LNKPLB35O2LcR?~4LEUO%Ej+pPPsX&`Ax6@F-ov=lmCEppiySovK?y*gx)bP`A
zV0vP5dtw*Qp+Fsh%j|Lyqx96@7-*?W%LbN{MH35hE%0k;%fAQMgr;F^H<Xeo<VtTW
z^iW$R=fMzp5Ia7HF7T1LLVm{FGIpq+_waVfH^*t*|A6pY8eto1cY^ZW0_R&<?ACYS
zxhq@ili14<C7feBVzptQ5g9=9V;QBs8nImER`cf@tv<d64eR&bUKI5t*MdHnaG$l~
z%b>j4jps`#Y=DV)%lMPDz3XT^&zC$<-jcA#izo*r$;oa%D}QIo+HKuS&Dh4Q#$;fT
zl1+2Qa3g$jWo7lbF|sX|v_%l~ty*o!=BqjNX&WP)9!c-EY7=!Bl$B?JG}t`uJX}@J
z?7JQ=;}zGs@)Q+y9>%!=s`&Z4Qo{<|BIFLg6buLEj;mhfE17jq-F#-MIVAkyG=MVg
z=dJh7zT&qz+1fk8tD?;5OLzQ#<YE&eF~A^OU%qcOyj?gsa;{#ohni%PG{3DeH}RIc
za*pEW>l?y)>^<%xzmnBSarhu(p~|NX+36Rei@$l*W)#{$m<pyGR;IQd%huwLjHx4i
z^tJ2b(-DWApY42tmQ}r!xvyWyk#p%QN1mtJGw;LX-(H(%)QyM#>SZp!EcznmjLqzj
z25mMM=wrpDfx+~|LB8V^+AEp%<vnN*hAEymi}x6<Pk5oWA`G|@kX!i!HyfY#S??Gh
zuEReR%HkwflQ3tOnwVYw(?N|R@?XnAM5BUX2YDJruA0%hgA`f4kohVU*_Ha={p6}U
zbgLKEa4_m;vP~<&dp>04Ky8gifqiRVvdQc2_|VjTGV!_zY7$j5L?|cD(6q&}o%7v#
zI`?5{o*dHI(kEcp)6~xGX1%U87M`qO|2095Coap~iMQv$-nCWPR9a;l<4F!mPrp9T
z?{jyDOp?;6>DnC#nWWxw<{thLH{%J2muhH`gzyMsFyvL;W@lq;Oz6!hfhWF}s`$AJ
zLbl@afPXNkx4LVZwfcI@9j<>Sv#=&vVyGEZ%u}LS-OjtM-qhBK=i%FQEh)0g$RWHl
zHfcw((qI~M_jj#J>Q<wJ;qS+HY8zJHdn_wnY#(QowVR+A?uzYMpayYRPO8S|9<}a1
zBu^T`lUJYA7aHx|)@*JzD1|o@#|j;xzEqU1q%NL!y>_>?%I;cqe(Q#^TqJ2uwgHs;
zCgPg9yE}<M%#ltwE9j7#?Uiyh`<Uk3%MfxuyFOCvyL|c#M)Lc9@ZOFdQH$?TeCg&~
z7c24SqQaCNu;Zd2O_%+S2AGx@g+$CWh`vdqpdk=;#4q7qYv@){5y)?8g}L^MLSf42
zT8v@=5Zt=CHjF284m32Ezs)eHIgi6=hGyx?BAknwZ=@K7<opZ`JA|0I+0zPU{$Ikc
zc-YR|;|}~-=rEc-$+AtZnBBo9=!$CB26jP<;$(v3d0*Zo^4y?tNP$dgUMnMGU`gO*
zC9YFIGP^v!7vzlTlBPgYSmGv~;B69KGrv{#!yvNg7amvM0<tyGMeVh6Wg_N1;Y3JB
zS0-Sh!wT(GlR@mOA1p*=ddv-jC_N?X3T-T?@}iv0$K+s0z7)s}DQOm4faa~uf~PhO
zfg|n+oWNM-?zIrtH0Dqf>Qm5CJeeh0F%`1G+`~d4TG%6sVBbV_)Wje=I&?U?&5VR(
z=Rzt>5<#~^38FA+S9U3!JA5PGP~z!qnJtf;r56prw`FE9RbqcHqA$k0=A0PFI$}iD
z9muPJdD$tav|Plbvk`fVvX@O|0qZg%C!vEJH6N3%<nS`+4u~P>4TV0$#uc!=i74Wd
zvYUn1;Ud&{GNx!P20p_44kAtPUKYhGs5LjX8-lK60*>^U1Nm)1?1tJ8JJNU6{aaZ3
zLCF!45Y3bFr4~Y3?#SKYK$Ax>wTWwY#?B$w_r{ho>BX<aqdk4u*|S1xCVnhvQ5Cg9
z!0VNAs9qEdFH2^PXoyyzW3^EFmB!gs8-{)v6%b?y2oWenH@P{1Pu5*uCH@mTME`>D
z47|*KxCQNP*if@Ka(U|Kd4i8|y|bpbd*k&p$lZH5C{R;Z;f)CLo7XfYFa#ANu&2pO
z#Lp)w6!8PD%WkX7vyG`WW)v(V|EJ0wc>L!(Gbaz_QJ;hy4M3dkTtp7{xZ_-fLAHJh
zoz%InK*1k6FjxQY9nO>a%Co1roE^`6qWe#=j`0ktf6irA<!3^r*9k@`Y{fZelE1sC
zSmftW=v$2B1Unin*SXYIH%_eE`n<*BSakts$ijH;eshtD6b$mLDSUakyVTUy|Ddhk
z8(72&Zngg!T7HH?btkq5B+~5-=?&fx&%y}srFQ!nZT&WfgwI0Q%QIbmV3DoM+nn3?
zrZxA57gPB#=V=qYpk%sUNN;;adWSpo@>0nzUQyiqgRxRugoh_?by@e{WYNEBl4YO|
zR-lalI_R6`^uJ0^f5B3Com>5>pZ!Jm?e86QOZ(oyCNC-tXOpw?bN|!4T@5OghF2qF
zS382)3%?WeMrNqtCxqd-)*JP{g?xRMYI!PijoRv}A2f5OiO5od)K<F#_zW{*iBvkN
z`eb=2IlT2t>~iJQ@zEdn^3=Ut5M6w@3jXda=xD2(r++M*ILLa+tvq~D#@XO33&;)y
ziE<JKyca6jnW=t7ZW%WT`_<o$t~?f|x{4YKkM-bOSYk_>79^wmRwOwj?3s7OEXZ>k
za~-ra?=Jrdms2nCI2xrV#61Ini9<Ajk)XNo$=;mR?q(#Fie?J{IwahC-&JMSYJNJc
zt88r_IK6dy20r0Tt<Qz#hcys7-BongJMT`k>h&89d-=wy7v!QO`H8nrtVj%Ar*@?+
z2g_ERUGn-e>q$J%9m?Gmb>+7@haIQ9IimiA<EkuBCOxA|!<kXB{b(v?C|DE!wFkTn
ziZP+91`O6`|3%q7@G*4Hl>qOsFdTXk3_wGZrlkpSAB+I{V+{XKqaeQjO^aIM0{v&a
zbgh^%%;=DCa9_B3y$pYUv!8gNqh`XAA0rj}l9TL9Ld@A^ylhymFv^DUc!}3*rwO74
z&s%unp2(v1G^1TI&?wY~Qi=T`5ZxA6t*?xSL~Aa|r~62h2zsU)*IJ_|+jQ)OvZc~)
zff^owvnu4Si`weF8+WS<E;r8J0h&;FVq~_mNvU)o$3AqKk5H}J+;!u{xQEdB5MAy5
z36&hY^ReyA=cAn!5`EtbciFbS-w(D9am2j5>=$^mUnkGIVpli!*o{i%GP_3Nzu(0A
z$%i?1lsae1Ymh<Ct!B>K+zEH7=cvXc(eH0Mh_e<(%XoqQ+JJZmM6?C(T$J0Bp9^v+
z2QjE^2Cq*g(q%N?K-)i>yMsK_y;10*6KvwKPjDDMhUkyR7Kk}&nq`Ii93V@zW_$T=
zfM&a$D)PyX<m;epZ-<}lBEP2a_iF~8`AmC>erY`MkslcIPOmfiy1#>QHi2_}5!p&$
z(ITGCyfMq%(j&8&bCq_$#TCQNveNwsFB7gx9<ZmiLh*X$61WXIZ*5(J>`AB`2ca7C
zIU<b0C6fdpSy5KjM2bo8ctcu9o?po2LK>YIaQJSjH;-Eo+}K30noRoTWF*Y|7QMR>
z^HlrCIgPg~MiPExItFJc!(H)q23}4P0BXe)iXDWb6^1xF%WG*=CjBBc%6=jaeod9*
z>Ec`AHx$&$v$0@!{;QG}B{M!0r12D@QSMbWoemB!pSYWsLvSfEf{b5~V+fSeMbXTl
zOcF>bp*x)@Q&IBaQDg$;W&pd&t2*qu^3UN3a2SeabcvM%B`6NGq(s+A*K{+!PexI@
zKu8%zEh6m!LE&m+<z~@mPhkT<oIqN_Oli%5(H9`s`=mmHnwA`tMGK(`?16vn&WILa
zPkTWzUP&~(wP^BFt0{!$W|Fc(83ta9#bb43fi^!i*PccJdj>ydCfQkzMOvLum?tam
zLOV>KHoVpl-Vqnq@n?azvBXwr7)e$Xs_L*A0OkFQLD+rFDIdSRxUP3wv=88nLNTEG
z7p^|&>i9jRd1gnNW3Wv`g70RGI-0h8sR<~ax6Tz)OZ+dZZ1R2_-R3*3NE);~tz-HA
z=`SA2D|b&(*;>ByUehQpbqYoO!)}ggRA!g_K495;o0ITqh7uI0a-Gu?;a^qL6KA-!
zL%FCe3<WE~e+6xe8bxjOY9Y_LO-rb4SgEaD6N8TTx?7+sRCfb)xkkW!KlI3x;VO2X
zS3~yda>b$XL*rL|6fzeUlT7t|BeOWoZYw=s%!|M<Ksk5uuc@h=0}}8PUm17t3ceD4
zN|7U!G?t5e$6@Pg=YI66$mv+^u~zo@DBl-|7)$H0H=q1D)Q=yhExuXp*}0xn&Bt+A
z>%8VDZR57<S)+Psq%y$T`;gc2SS9^HAJb9EQCl}0`(2g3FS3ko0YCJLwO{UCqHRyT
zQtQ*_=Dn_H4QSdSX+7d&gu+sUABEu?D`*{b@plVtYh=HK$`(aI+pwK`IrLDyGzBX9
zo=yPUl}xJ_X6}l=z32k#4*MrGd3y}?AfK-CZ_R@8<4iQ{_1E`BZ^DE*$06Ym^~&lf
zfO?d<&pqX)y|5*X7F5yIAJ9O4+vO$ACbkg+?WK2DJueKYtq0CmTYW|zvDF{_zBdO-
z4Z5VLw_T%Yl+<yY`pcQS<PD2~h@s%s22H^u+w%JNXP!rsG{0#oFg)<mg6lnefCaF3
z+iq*nwx`!X7y0QUN4dw5qqf>NdrUbDgbafqgteQI(?4S*T23R&M_+p+Dk3~_8P|#R
z4+(!^4Yl<mP$_LB+8ug*b?+0*$2b28lG1ML7JbX6df)8jxuL+k|Hn6dG70me-wwez
zQ{rI|?xI`MlDD%{3ZIf?z29)*;K!IstZb!_p=M8WA3;5a(W;3SVn$HQiHb19)33=d
zFtybppI03G*s)=@wGZ^Te`{1ogDKfo;f;kd*KnuzJ)HX*4fBf}C3io=(1C8OOxoTU
z`nR4JoiUzmVtMDY1Mgt)AJ2G&wP3upxnk%(lEhb~-PVw<<Qsn{-2{e`+A4~utu7DV
zRq@VzS=r{#W#jWi#Ms3&;P`U<AzYLygo|NZoK2;;!RAxmwR_49Vx*4SG@)=zKD^lB
zY{764VhaJs`C~hQMy|!`QNT1;0axhD76TzNwm9<-HzbjE{<tGsTSHlxXYDOOEgS&}
z+HIxcLx03HD9gY|86Aj`dKv~11SG|K&j=jYElG4;Vtj`V398A}j2<RmVUO;oGq==o
zQwUcO%*5bn63uObrC6h!DBIQ^HX&u%K_eI)8C{wVqnXX+d>gHZJ%Nl{sA7bdw)3{3
zR`i&~<nOvd?{O!26h)ggeT@a5Vzzb+a3ex=6PzXF$RF9N1|<%!>w0J(K@aeJ6@GFu
z5kxaJw?DlIp7}bMzm!o-Dte^CI+80Xme~<|Tb=33r<|hV5u@+g`~F^`JZ#cqt#CJ5
z;wlfI2@~ihG1hQ`z6*o0h!gKs(KZ5M?g2)pOY#g+o()l6Nx_TStb9YjX7U<|rb!Va
zROgh!Hkc^~GS{RiDoh7K=w6u><UmOnNwgrF+Zdy5xj=x^WO5jgEqfi5q$;B8c_@h%
z`K(AB7C}xyVMVpfmmj+N5_--jfoDLei<mPoOrvH-F{JMfllyRZ5)?1AjDkwp@y)h8
z0uTktc9=sk!YGR1yn;2cD6j)R>%LSGO`Oofo<#g25pH6^IUlmZWyF_-%exBY{vTHz
zNonQZ6O<<m6!kO?D3GoXDw=A>O-JW?#!NqM565N!0l3eIpXV3E6(Bi#QOLZq;W;6U
zJgB~X%7hRt)1=`e%Arp$_ppb<)8kM9#$j0*A`cO8Ma&X~aUa}#jESF=39Vna1tRsT
zd{yUsEL{+Z1Hqbv8w|@#3E?rxX@(DGgi^%{>I!*7Ax<(mCPb(bwT4uxiMK=&XG(C2
z%BJ|Bc%f8u0B9D`QK|{rMvyR<#2Jist-|CS0LEF4aHF!*KJGR=fHSHKUrz8ASqz5`
zlLBFBKBCg_m&?zDEK%4;FKME3p4EqwOc-vB>71uG7hf}YQz{!KJlSTVFc4C<Q9Xgr
z9)xb7_{#TkH`nplMCh(cNgRF-ndmlEwn8W^%c@Th_;aa&kzf!=HaxIX5sErZ4@gkw
zp3NDkJxy)IoRE-r=(q@Y(`|&P=<7+@Q_J5+^ii6dP5@fXKMfbL2sX}DUaeq%ofXUO
zH?kU1V~3p`StZo~h!^o{dvr6K?*6ej9$YT@|98M$+i5l3@$xpcLTh%l{AWejb6cTm
zKL5=S{sJjui|bp*S$2glDnzYd2#iM|s0dw^QVZ)!z7wob=8+%<R1{dM*ieNNWV8@*
z7z%buBx*s-P@8&UC4kBZ0B1t<BcP6gqM_V?X9{e4xoy&Km(R(UG&>KsDjpETd*h_w
z#y>_CiSvbv!Q&VKV!}z3lsVF{Idwxp5q;q#T+22zZkt3HLK8B)UbC3e2D33JrMIA9
zW*P>>NBl*M$M_{w9D0fd>}@zNKf6sy@qu4Q)uiEQWbj}HWo`pkO12^kp+Yhefs=(4
zg$;%pR3Y|+HcqPf%*z=?emdw8O(3^SF>UcK%!14=G@o4{&B+kc6XrUi$Uh@dX%8XN
z4u+a&t)}$Uh91Uq+&V~;Ekm3|s0{N&1TB1hj2u^}#l#to9)TQiUeUlw=58`mz(COM
z%_`*)_hA)Ol@frOXfQD03IRt7A$lDT1FSOOBxgoC+z9@9NB|j81vbyrL`|)me?~K(
z85K}+@jn<ef@J(ALf#O@6B2D)f{Gl-4zh-s0tc8r#dVn(yaVS-@<v%^$j)5w*lAeq
zw<bOQe68S#m_0z(jUbLR6*kI2DQ98795Y!OyAPr3u(VpuDV9iss>ZsFpMAk1!qA+A
z+2tn)n%QiS^+<54e-PR&S^~XauSZVgm&468OCyO`O^96O>oBP5pj<g_X_Y!VkH?}X
zCj#A5K0zAfF>^?Yu2ZTZuq#TxL|ta(P&??UhtVE?BwZneK;ujwcDhw04ZQ%_$22bE
zQ93V!roe15-RWkbgpCf7cHOX`t&eJ*))Pg>i-rvST#(ViT<eg%jOsx-Mg-bo^JwWO
z2<D;$$uX8PbkK|zlT0_W+H+h`I^lfJBa*jfar%CXZ)>hC1!z|1P2>nx9L&G}dvWD6
zT3wnhH6s`Se!Io_&SI9<51W9kSy$F~1o<}H@v-uxg`X*-mbjv;-xfJDNPV24Fb`bd
zGyhvu$ku{k4KvDo>vnK%ptT>1&izMD10|Su)6B|WyvI9zor8BGLJB`aUjZ`rC5p9`
z1xwq%Q>Fgr^QCWPYKVIqh5M(Gj()An>PwR>b)hZ0MH(uX+~!=2oU7pw`eQs&juA#_
zwKmEVh8)U(<L>a-{^D9cUESC0ldX({@+E3|i)pNV67rE*hcF|HvCXIo!azvdRlAfy
z1&^QL9k2Um-2FP^lb9Yzj5A*U2n1nX{yiG&)<cF~U}_mY)7dnN8^dR=N>6f5`Ei!+
z6&}<vcQ5Pj+y{vWesLnZr1<r~;VkkU0jlev?zk3aMxR%B;ORvhLY3`%|6rkvt9<N&
zy@if$pW*4tIPeloU_Z-JI+<J)*_SAU;sT-WQFc^D0#(fBzgH3VmH7*ko|<#v{XEQB
zW7n(5p<d2?9$rf+K5=PPvLBGIbzZ?f>%VmF>682U6w^Np?y;Ysu5V<_V*6>?q<)f`
z=R1;cwja)Dqo;0@FmHo-HP}%qA}#V)R!S#9w4lxz{*N(t-A&Ns99L{32HH<|q~`<0
z2YdPZ|3F)ewvo^=el6n7OmC=#9PW<Vw>79yt93g;X|iP_Cs2afn_mt}G8{DXuDdLk
zPTu4*+sJ_n$-pXbYMia0>&j9QB|ALff9BFuHtT|kiSN0jduTp)rn!jrq1U+0a=7rS
z-m7m#3BRwLQ=^>t8|sG6&3%P2S&6^#lT_DlBU0l>`&rBH%-n)XtM+^I*Ig00%hEl@
z9;_~+?LAj6R;s}6qY1^Bw+mrJxlaZ6a8P#rW@?qNou<gYbp+M<CyK=d&G|-wH2DDY
z<lAXhUr7Tu<Bo=v`9y#W#~y5HHQObXcCu&EFvA@BdFmtXqt*Ykb*>h9Pdg|k`>9tJ
zdHouMYSg24X(F3Lh5OzGjI{T}4GtG}?ZFUkj4q=Rh4P5)ADv*Yr+4L|-BMH>-#0~V
z42NR=Ep9S?FxS3H&z+hJGf-ssOR#m2(*Lc1NBq=ORed=3&5pXu-NGu<q0Du|A$LH>
z9?RkqH@2n4w&z&#f-~FeDF{ikkCw_h5krCOdbSs}2j<!(jPcV%dgSvL0h<*0rp^0Q
zzm~qTuqbzzya8sO6vR*h)k9NKnE4a30)|5F)|lTtAf3P`<n*G6{0t2ql2Pq;&LLqH
zX&kFG-4=&sZ!=hhW|_wt4ok?y3r(`ofTUS|JB9LYWz12Lpb#}3nsE&OHsmBU1(mh|
zm7^|6>OLL`i!iH2WihUQV;-C|C~TA1#Wk<TI+S-veFs)R*z(T9YVbQEMsaSUrzE`d
zQ=+q3pveHFFb^uFqaMf#X0rS~7u^K%_o{<Ypx{h`Dl4o_1Y_GnrW)%hZRXba3c#1i
z<TsE{Sj+shS}O1KM;DZ#%3mW3BpHxnK24J0(1AU$3O5-InbcNjv&qQpBO-}M)za~1
zDGM9{QxPsVQ*Q#SD%;68Weh1wuyR^xRud!?#!wJJXvLK1JakxLeKUH@>zlmK!#O*^
z3s?QHMAh=G<{YAhHb$4KvJ7jcNY<hPGkvCubQ6l}C!$^(EQ*Nlx}6F4a!)CO{1QN2
zMAaEZVVwwOoX)>vEG$LE)LIWhq}qeqhHmSea<?gZ2rvU=%oVIz6QOp<%-uES`1m`y
zMGS!zG&$kN93Io-CMv7DNNR<E6+|7MwRq=x9UNl5h3Hfhf}No$WLJ|Wd>%BV@{C@q
z6n|sCJGv+)hQJOCnCR_=9f(jt1m#@UEQ%@U>M_EqO@tH|b&Lv{F}WQt2}bi{An@4t
zXa!6IkA)v-a_m>&2?#uHks6~yKiq<LF?98&bx1AP1|xgQ%ql9v%OFBmGVOrYgI*pT
zs{xvI<X#AoAEn*{Vn4jC-hRM&j@>c*Hu=;0^5dwjA=4%q;lm(vjoO-zeeG%(KcKo*
zuW@ecVY8C7Hu(ah!IS%*Ohx(PK~VMmF4Wd+<pww9e+%xmS}7##z0Iu!=U#j>@eh)s
z*47NI`X>BatMq#&X+*?)?G-WSDi`OzIrfBm|NrWxKOW&u6&!*;LC%8k`Oz9wzWL7?
z1wK2~bDgVsZeN#HhEQ8mk<P5S*Poh$9{lJvKD~*;?##aE(UzV20UO*~e3io8y;$zA
zA97=$ESuIIIb7Dv<BA;SJEl<AZ)>RRUTZ||0M5s_b58Ei_yC!4kt#Vh6VjV_7Cgl0
zHfn3Zw;5gdy|*n2pHiA`A*o%adfhrRmQLZKz{E%ZitJn247(~T^tFv=FP`8VAwL{?
z{>&_qBY-CVarMAsoG;5wTRu)Al*4-)tw3sP<+@*eDCg8x+<)_n)Iy+ab~cT)1)RCd
zzdjWfuqS>}%}XJJ!Mo=!t~L)p0{izf<ms3pz&GvFF*B)F^@+@fu=OatT3^L@A&-2_
zk@FceK!1{{?(MHGx^MsK&|ThQ(ImgBKx>Dynr2vhm`NUoxr)_aWfA*j=x&WMVZJK0
zn8Az@dneUey%by&=FT({fB4u~DBs9~<`bEFe0VuY(N|kP_glfuAus{WtD=z05qG6L
z-uvV%PjqQk1Ox(tM>cwE(QZWf*3(C_l>^9Dk{Jnf7*$uG7SvOE!Hfc-9B#h$Bp+Fa
ze*7!9vdsGAJ8Vd#&8@m65jM_9%K+@sYjZfH*^acNru$i9`5!s|gvi|^D}lsLZxpCa
zun_Is!c%O6_Z3b)3F*RnY0*!-A<sLJqatfa<1O#bi>DdV)}K3BJYiD*;(?gX48A~H
zt*L!`8BoHM%sh05K@Z$@%TAb-@@)8OvHq(0OTy8R&8Btfv!l=V#kqzCU(Je1e>5b&
zeYjBmm$M=bO;oG=GJL6}Ea_Us=jceMCypeIQt^W!7Ish()w8Un2|k$6BQM^>H)?~0
zMgI8Uk_-QS%;OGRnyNjiCR<BO_Js|1go?8~$}t33i*zpD!aVj2nBK7W$4lSV#TDf9
z?ru5YXBt$yEHwV+5)%u~US~ebLD~P#-hr}Q{r%Z|y3iV`;N>5VT4J0q&bFu_N~No6
zIG@8kG-7-REYmuobn@LnOF@hsYC^8NJIbD+ngmDRL`O=H_jcg=(0Z&|Er*6*-Z~;%
zUSv#ruPxpHJFdAHHESw8@(joUSScjYo#5$3O{9$z+6Pea5r0ZjxmkJmjRLKBy^sUH
z%G-ooUck$s+ResUxI5K!EDZBGCeVS<2u9(l<!<JLv<<47fLF5ddMIO$1SN<55@KVW
zpNfmV63^#H4GgK_qvV0p2XfFPH^D^EoYN{4j$4>^MUFdq_R+Adh&#*K;+=0-;$L;N
zthfo6cVz?7b*D8L;@GI@4HnOvg?>&s%_)Yg{B?2w)_<PRF7R*|51;Jl6pI+0jKWXS
zq|jaYT;_Y?-Xp&ZeI>Yc#$%XV+Sx<)Pu58g9dO^mvrZ86`L5L_?OSiwfwIg;4D~+P
z5knYkWPt({(36(D6XyFK<+H{wR3?Ld_->A}2~=T#>uIYyn{Ns=bF6XK*wSn{w6-Oa
z;YN*UqRw$rylfQt8Y+*m#-=;ePAn+xDtmO0ow_C<W@es+$*p#s(y{=p-T*BU+-0N$
z3lA(T%P|C^v?pc4vBg>rYd;h^0SyU9Xna^Ut1xc|lY0l;Td_me9_&e>+Nc%Z^oI0a
zYa&YMm{;5=&<Nd%x{dF}Xahk4D!TGL(*%ubiMdYPfxXj>klPsLh2&lSsy2iu>wX@s
zYE~2Vk>C(my@Xk@NR$*~o*=AU1qC1Q60+($QY0)uOsHZ6R6=M99^0x(F}s>xeA5^*
zJAUWZjj)APvpW+ExaHIuZKUKq6<90Dc&vTNf}8Y{qd0{p<%nZ2_!J$^!HTWFuI{>I
zf3JtU4j`sR5^dxjHq#a!@X@=!2g31J<f^b1cm=HCtUeg!id?(W(4GGk{8w^3LN~Om
z=(K>oL{_ybU`t{z`^0`8tN*l#-TdWLRW~8G-y3sF8y6PU!k?f&9eKneynB)hR+vy2
zH<PHm)<44gnj+R$^n1)+`8DBJ<^^gi1$hPfm96jxeLfT!0KDGTIaLJY@esZ%$?S|8
z`aY`g7H-KuHRX<;3gv#(R`TV}B3qchiNO;T6zT<Sn}v+ol5_u(#&=S)yeoMOj|5CS
z-I?vDUO$Zlu*nv5aqNU!@HF4VYd?M$2N>Pw2}e(HGcQi%TRk=*@x!%o;~SO66idl8
zpMD9Eh|<<q$E3Ehl=wpK>QC+)N3|>bd%yo^`|uai9)NBq1+S$ZzxASZwy^#qzUr)8
zQ0{-`4P|w~*NesOw^0ws_Q)H*A5aeWG53U|sUNUDUjETSd58F!`1^-f_Q-2HSZ@^@
z!;dgX+ybGwe-?->*lkUZ=;_~q*8Mb?utiPU-8L`HdUVpvOKt6ae>}_nMj7JUf0}(@
zcjdBO<?>6PA`#zvtW2fh9@F`IU*p|-{_r-x#G>Rn8TxG&_He1@@?Yh!Vk=ygvIV+X
zv3L{#-SlhjfR=0Nu!EsTTdaDQ#D_tP;{5&JP^EayL%i~e`i*1E^0Q{L@y8(#6g->f
zB9{B8b$tkQ{yUG;s~)-3+2j@qgP}*XDaAG0aHi**wj3)qk|Plt&;0a{yM=XDwEdq$
zj7%<OAJQ+frK>vrF*x(~)sI8JN!vi)@ws*eH7H|F)~R%^{ExxgO2Hq0L}hgTD@EFE
zwav~CUzi28Ia4?lvaqFWwGaFW#{HZxsXWFiMmO76Z9c=KPJ`P*<ibrjQ>l8tNU1`<
zR4^Zv=|G^5J}jikmopcHDOx)rem0+S*H2VoVKwdyAK-pG#WCJeaet`AdxO@t>fO$#
z`g9Y|X^>!FYh)<%?%TZ4-2Dd|J6l<cx0@aN`;wk)d)m5G8|u<ivRj-#Fnut~PQ4~O
z9Y4ZDyw<pWCBNtOF^dE~*R!K{MU&yyzRxT+F#|2=lg}*-#Ak4P@lktBKh&IjF$FyS
zd9`UfxXRW-3^g*!cD;^VG6krwQ?~Pr`&YVDWp!%vDwQv`R5u9IlyRsG?OmWI*!&Ul
z-VHK0Wh#g2D(r@^TbQxN5j0v}%vN{9=!bb)q<JV`>@YlJ?;xMZa7^gYKH3P5pv`A#
zu2lws0<YZ2D?pV;!fcz<K@*u*7RrPNAHO^;PNX)6Y}-bt_`%?v<G&%^KFXd}h<g4a
z`7cny1?hHCQ+`E+G)1iW^0HfJYY-&;v%%Wtdz&XPu3_w~M0I6m@*od`c@RX4QlA5g
zfi)wN`*R|9_u3s6KDWpk6ScMS*s11loCm&L2WYy9p^D6A4emTufC@hhL>@++GQNvn
zv`&Nrr(-z#*o@mBCfv<jnBvmI;CiAyMV3kt`MDCQ=QVR-n|4zjBh+kG2PFlHI2qO3
zG`F$2mdEnU<*i}cYos(djm)OvltnOxV^{?bHr)8*yxr9;+!5F{2xj_JuHe2d>L9A5
z&EWz=*u&tG({x!|XAcC|oJ%FzCh&WrwGmzp7zp=b`>~LAH5CZxv8qy_f`#p+iA=&R
z#yqc@;Hdezq<HgAqdcQP1nI38P-aiot!$JqQr}veoey|WTP+VyJ$5I^_H_g%kj%Pp
zth61ZSNRe0j^Z3-y=^D3O(_org*QDu;3EVq%oaQjegSJCGWgTzQVkwauFtv{9ejJ-
z2Jt?KRbwIOYTeNQI_2p>s5MV}h63<<gU}R*Z2H2W27xNT-ikTTHnd}G&yyw?Z=s?<
zLf{KTW{2>iyn_LSK-4q>Kb<f;&qAl4?Pr+LOYlLFl?)zg#c}K)PYa5P@`&f*5E_(%
zrK*POHqrL710lR$O0E!(eX_<Gmk%J(z$b_;c`TN=E!rc$Xk>EtLt)1NT=KdB&lW{Z
zwnM$)?P7!!7E}ewYMVP;{QK(u*RybyXME*tXKYG#o*CO(t<e%}+jH}h)QoS+h!b#T
z)4*Rcl?ut;>NwxlV3Xxne2AY4X-Cq(nhy5iBI@H31Pz9$=5b=bhdOG+v7EWfFLPfC
zV$@OGEoQ51I=~OwWqmNK;-{j0B1JdJC)ip=_BYU7j#21Zor($7MB=<b*~RKN;BT#x
z*Q16pC-Z2Y^{^O&feyPh?gYo(OsPFXNOz(vwClku7p~a4Fu0sA@a4q>m1R#XtW92t
z3wq~(TU!&{jde1ociqzj46=-~dt7hrmV-`AG%|+~WP=pk<^$v29m_)D(?nwsF^fx#
z>1!CeEp!Y05t<$qY}P|<nd$kwGTr(%A|(%I@D#Yl!~UxacCz&a)Yh+|=Uwt{mr0|9
zo8f>8v0kkHb+>ZheJ<y=7faD@X2t*W)?h~~@7Q8vhD?@M{^XaGEe}5s)2`W%(<a~N
zYBUw*UhIsH1XhGEyRPkzev6GiAY6|qiC`s!>OR54Iy{f}wSP5GT5fykyuxLu<T@mr
z&ENjN@szuZ^}`=K#7tzxN?Wde<yV+0c{qDMo9aMqW|?XYPeBFFLR7AUA+Rl5y32lr
zlTjqJQnp=A;tyXu;EJ0N(&1yy+e-Riax5nFE^$#vlIaH?9@jvSb`G(v0wu{ge&g_K
z!VcJlZOm#F1J$nB`odVXVyYeb^hhAZn+ssw?WQe%&vI3^`)~f*9FpAUKK7Pd=?u~z
z$s|yL$Cs#MJ=X0@ltP(4bX{A=oFk@_4+n6jH@*#xM=mVgom{R%lDU6P?n=CTH!bzg
zSXT4@3tfa3ol4ti%jHo!B)rZ9k8E#o`?#)oIiW1wbsO8|h>KE%2qk-T)A}MKK(qh_
z4uW|1n~atZ!h+UW@W^M~$?DS?pP|(0kr9BscGnSJ*Ot7#l4R3u2ehq5R*eOo^haRT
zl(J4b*}5|RvGII7YK&yC8VU~xLx@oSG1Hd6c8w(>+YsMPUM#^K**LnMqZ?~jL|~Vq
z;h(WuAVg)8+PZb+QeQcAp1^@1_Mqg##btE21Ri7KjO7%C^WX+LbrL@!&#T=sgL`bh
z_iM2WT&l}6e!RS__wn+;Gm&P#$mneAhw7KWIHgjT_wwlIvk{Ixc?W?wJD%N}ZZq8t
zF>@DHWKs2Yi`*-0Aw_suJsA)%lR3?rImDiqD@*O#_*GFf_4Rqe##^|6S~3i*u(U{s
z0nt%63Tl2K<)nZWVnf1m(F+$bx|%HEtUz@&ZWN~95QsbC$!hBUhA>vI9~G1%KXsTY
z%rX;HRD&remzgO#X7Tp3f}^55sFH=rBlcCUzIcSQ3q%W3@srEEI}OIk7*txpS<IxM
z-Au1jcqS~<*W~u?FhEwz3J`{}_52!`2#kif;hxtmn80;ikriXng%)F&9cG}p0ELYS
zBka9WuqeY0XN+rvt>ZsTCRt6nn3MS@VZvuZ!x3w=SLQ7QHO)}&p|DPRKERQM26J(u
zZp29h>oLrJq^?N>J<H0O8JLQCFMaD7hBjr3=aDjIE2jQN0{8@wcLjE+HItrDkieTc
z*r?p$Y>#Vx%Dl>>TJE%7BpkJ<o+Ln*BHd{&hCOU_%I%g>F%AmCX_>|^AuGr>D1a%V
zB*QJ(@(l$9;e|v+g?8pB|C|gc75Y~za+w4T)aDGmp0Zve)Xtc8@#J{++qW4Fk&r#1
zNHJ>&CXjL0xxdn9xPp}p(=KXZg>4DLinvwcj++t7iB69|;IvzA7rz`$T$)m}h}M`5
zt!r<4kl51s1Q(yz%Gao{44YXakUX8DwWNC6gQ$j#+y;7<cm%l(Dx-yf(?{Em-pkdm
z1C^-LU~LnQ!L>zg0{K{9!%h@-;Me0<H)!j)M}jJx!>4bP!IE(`*0Pf#h>zs5pp0gE
z3?ngxH>S$3-%cn$v(tBO?9RC4jzv?7^P|v^z7K(Vyqu43rV;ac=H9qX@~Cd`J>*v3
z;p5_Wq-7<D|5M{I>p^CZ^=(ba8EiWfTQh59A`{2Y9HFqhDCp;dE4RjdgSfX9$%f@{
z^1Z=DCPk~69j7IMrco#MFS(6_`C>X}%jfrWNH~5o3-e17&@G;{v#zqYZja?zQ6J2o
za7k0yJ4?lsu6s$;Vc(}%d8H4;nvc0dI`3SBrM=Z-EFC@|R1@=+m7I?Ec4fjY+iVBI
z>v2mU<!qtUJz5**)An0~n0H^GKrbF@5)#2Bg&2??2pT7L0izlJ;iE1)ar$=mnHOf=
zsx*UP)Qr+K+`4JIt&`u|bRqS;`q1~5dS1~y(m2NJb^0<Iz3Qb|^b)52dJPt})oUxt
z^q|jt`3HrYJu?;iolgXIgGiv%qw7|a>Itnh#usm{+_f;?dFF>$hWsF_i;7StKXm37
zLwxb${$i;^b7#if5wxDjd$GF5G`dG$e?(P280Hyj-uC8dKOfBKe#|}QHvaI>Edke@
zavXw&@igOH{5!8H%6j>)a3q=#)z8NJFW@4)Zs|PN?z)Aar+vI!xVm#7O=4y!{?}iA
zJayU5JG1D1_J+b1V1uYX!Q^_Ricn=KyU5R_!gx8|i<3SE<h{gh>&owbZGLlTwMJ5%
zzBITsY-byUtU!pQX`tAVpXKpDZ?@9=%iC9hKJeYwN2zwj@efTERxfR$k+M}|SQYhO
z_$`_eRry-n6QAT_h!@DV-sc{JpA}noAlvNd&t~>v6`o_M^qbgozwldSPbl%%xjb@c
zwk4y>H8e<Rr?q3PRty9FmMo|wahaXe5P#UYu2yzTZ6!MV*=>f}slJ|N_3v;#qqvcw
zX=Xo-?GUVgijl*urIYcx*))=7Q9|_m-2Xi%a|ozg(q!xz5QMv3mUyIh!hEs1{@QXp
zK9zY54+CL^*zoz51|?2VopoBZYk_~l7D;C;)M#lOdr{EotmNI+fTj?2=C(d7k)_$o
zAlpqgRTG5E#x)QdJn+iZsy%0`ZP=pKjh%bf{w}+%R`4hZi0Lx?Lrg|Q=P#MZ90KDm
zxJ}lnq@5zgOlMhUlt%9Z)ZA+sE{5v2Asz2s<-x>2VepZOG6!|SeS``0%a6|Uctvcp
z*)y4LCfJ&+IBBYC1nNtDhe=g5j~Sny-FENk8s9Uf88C=HrM)%A_+UfxfCLs5G3|*8
zbA6yOnp+XUTu33HhB4oWV!B`@9xLS#7IDrZA(R7$z>7g#f{^MYAVLFgW~sVjNgF{0
zu~N%>oL`iKhETm#6VA3w#w{KXLSB<`unH3Ho=_+z1d#}2vqG!aG#bcwKt^+|>R4Z3
zBn5)yw$fx8j9)aLYF?N1bNM|dDk2Gu#VX&s&_jEdO0g#p7cEky<pDq19vP|HM6e2o
z`>q@S(o7I0LV5vlBSWCz#d5+O0r#-tqak(S&dX(FENBnIZ--akaLd(xY9)oy(n-yM
zKJFqHu{`9yV_`mDo+P8TS__e=88U52;<YZ{7@8|@4=B;b=M!d;AD7o)qvt6LI=?Gu
zzpilch)oa}iroULHCl@`{Y-6lDG=)IpJ!4`)ZG09p0$%_{!tBUGJ7Id(|L4V_IBe#
zJFdgo6TK0V7lIiL_54PKwBXGV%=ER3=C{v7D`=&r4;M-(@wZY}%-*m}OF$Y{HA?YH
zev*!NkE}P1ezofrs8G6Lcm}(ih|aniZr3HocioI}jM}Pr83Q1ip1i8Ik>?Y!?sgIf
zmW0MiE3qL%bQmxc68X6a8_w2}mv#rN>v*LP&Ry;P4f!6iVHtGPR$`+SMtFkUn>EOY
zj2(NzWa3KAZNdx78rYubO$5!aXy@Ry3EBj7waKe)kOEb<D2{y-U^1Kw$+zK}blWO?
zi?+L+Dj-@U)f41svrc0vdt5{)M}sBaj02&kJ<x4vl2|~@__Ey)NQpaY5Dn&nmGbOl
z-H3nX?69+aYI#??sK8w9%;ezlDFfzoahsD!$Ps=+pm`STj`arkt?w=$`3yTo2aak0
z83s9zk)J7pp^ZIAeRkLeQ*--Ixo?HWe1@RzVWdGzDVo8Ki}ILAu$Nf6C()$%AVi4&
zd4mbWf)N{RXyDw+7C4(63~`1-xe`gdFUu|4`cQS0Y^%#^@pBJL=-(v!a6OS<$~)R1
z5Cr$NR)AkxbScatb~k)vruKSNnWtEzn)hKIG=druSK=e03>QzwX`%|-Cp{Cq%>-l4
zu^#R)SUGheNvdaJ{>6PHs62Q4IL8M-ifH-IWj@<FOKr8M6sUv1r%0r-3;er#868g3
zV~)-E%6~T79cyR8fT!~uf)h(p#?at8dcYsLH9YCDiHHTtVP1cctDZ#gcfY^ytx*!)
z`sypaz1(^8%bxG${iutVpc$A#qJ)DWK#IGYA|JDlCRM3N5U)RX3m@22%B$bVHu?M9
zy?ma6haOw0H@`SreEoMW^hpalv){cAmN%~d&?=k&`=*^eW98lx3SypnXVj-ISeq&q
zk1XA*YDpCGf6b;E5u07AtA?L~Y~$gVvJmSVoLfS+etgWu-~TwBahXKgvYA*Z;$=VP
zTy$JYBl3Jl(zy@aP^41fcFmy#Irj!7h1~YIuYeX_oSY5!E$mxzH$7A=R$p$LVH>@N
z{f$d~6%{w}o38Y70FO!&f60}06jyol?jH}T{McT}<R3ge{&<B(Y2Q4t@0PGvn%(?a
z^|~PtiMP&KBSO=bQ9V1z?a`~o_-YDbUATsM=9}qM&u6u=%{Klxb6dUZD7~FFcdQVR
z_Rt$jr#^>@8AWt3P`ZtKFDR$%7OX2@<FY5NVrE9RN+u;$&&?1IRtw$x$nsvgG5;=H
zMnhk`HP5QAkLA&E^$Q<tt-3R;;#|FdA^zKIvyilQ&`-RbA(%8)$Ftbw8^=bPZ$y=H
zyD_Ma6A@SUj&j`K`(>QJp5rd@jp}tHK=^#~ygvCRE!?9nAanofIqe*#JxwF>f%ZYF
z!Rm~HzQZWbn5~V_9E~#Sh;I@9v(0i8KL8e*xGk0CLUe=&IaH0)zlm47w3YfFE~G6<
zjXuT?$XBMS&$#b$3L@@{q19|%@Ap#lwu;&KceQ9q)o&bfPg<_~qAr!9Ej3WLvzBkK
zp|vj;D~$CG9NOP=J(fE(C!Va<*(`j960>|+lv5G4H4hR9%`2j|!gmWQQT6Hl)`Hux
z-R)v`91{s#tGY8Prz%b|VU4@fI4e{*ULhD>nrV{(OahQBj8D(r85k~hW$0f1MSawS
zNm@Be$esKQ?^zu7G6nYDK*cmqoW%&UAY#FMntkHpn`gZ=<zy~Q;mFp{35~3U855W2
zk7)t{ZXkFVXhm-$>Bp4K7#1}F1$P#J)5L&(sZ@wZ#R;h+k@vWpfFHIY#d7W@@!-sz
zH(YsIigJ$*9@Mxix?<J}H)T0#Y9)CM1<6GtQK((nv!r;sN$1_!@gjvtkY8aEp9oA$
z$s}gJTGHI`J^GNym|KepZJ_B}VjIs&q!X!3i_WjXw@0N}g?n!#^t1xJ#z=|GO69qQ
zhZz@M!Ql?k!^N5U1Pli^QAR!}M$(p#4noZ`?+Gpl20V@oTQ?e!XRshRQ*@FnvC$N@
z?YzgpC;l%E{Z#Ykr(F@7F=}$QMr_Lbe6({yR*cj7_>Sd^PQSP<F8sEOeTHrZ+Z}GX
zRz{LehhLN+Mgae?5J?rWDjI|HIP{DBwxJ>CpCOKiO5K#n$3i&W7E#%c3h^0;Ow*92
zI(G2fdg=jq$fGo5xCk<B6Fkaw7E6=vVustmx`WrNlX?Cu`k|15q#d&=`TDg);E2^A
zBD+JuYF5yL9}bZNbBf_W6Xvx(04*g$yaN1>B$rGia2CWq&+7_5;3j8{0PbZ4)G~%Z
zP`o<5M<6x!S<u6Gmd@P;c^zd;Rjd9`9+CY884}u2IYt4hP553vuiA(iMuIq>>ZYrp
zp5Zhxeyy3NY!DFC8YO`U|Iw<<h{$EdSMr%{vTi3OqIQSQ?!kl}cBrkczPP+5GCj>t
zt?r4rGosl4{?_|)|I54~e!y81R21_W-1XJYSmgtd9I)KSZFu!qNVBDHvUuLTmNI>b
zk#OtwrnR?J_p-Na=ylTz9}2GMTqLQ)>`P_2U$^)gJXo?3s!TrR{rGnuWl$cUF5OL8
zaQ}AP=R%RD-9pDgTHo$AYu6v-<l<ADYn-QbJTs|EatG>%Vjh1KdEHXv_G;G*OA4-c
zPo}*ET!bpy?Bp7?dNGgGg6R?j=nCi%pWu)TUyWSPZp!A$xh!U<E}Xtxkp|s!J4G9D
zw%ru@?7-wZeJ|f;JbjH@`oK)g{Wn_a?1s7>)_LMNJQ=_1|F05>F>gY?hhDCxJYg1L
z?*?v-*-6fb`Vl_LCm~nv*t*C~J$rd9-*|?ZV`pEnDTQSAj7W_D{>(!?QJ*W{k!8yq
z*i<uuLT8pOy6tRFj1~U_dehv^r`^IY|Nbjnhu2@jHD8`xEtC)Yz%F3381I%;0mC4?
z?Mki*c#7o&cEMMcILk;ynRfDqccHTW{({@MeY$e>vk*f2(UnXzHkPl**7>{0^Bq?(
zSGsT2-M2Ls?mgV`)y$8%Qrpj&P+qHv!0&SmR@DS;=l&7{U^SexP2R{(BS}=M)Tfg9
zB7<7@pRc()-#Esm<qy=)Mu5|o>cU8odb8_!Y|;O9sjV+izw#3?ql<Gj3(KkF?rl0Y
z+x^{Z9Q&`)efrOsDN^g~WLNGRfAmm#K#_0|1ocj?m9}hM?+@9RpfVr5b;|bSw^m>2
z4y%=TuvoKT<?wi}n}lHiVNbopb?-Hg7|t~ZTmOKwi8Lo3lqu6-?Y2^c<?aOI<eg*t
z1NcUvQCmCp63ZH1(+EN)tVOG|%C=fZy_)CYus-X2=O0bF@jtyVTl%-xj=4J!8mkwm
zgKwV*QuW)*qJpWz*0BdO*0f}hf)G^)sg_Y&zcJNwPZcMM`G2vtnav-usA0x<xG^jy
zB&mt1COhGJ2K$@b9R6VXBX6IcR;=Esmy$|_-|y~X|CPg)pAV+Dxd+}(@O?#lfJ^9m
zLK<}5#o`d!>598!A6K=~A6^~P%<Kz4?iCR%Jp*xG{~+|TGd%Jb|MmLormY{=dOAOt
z9%&)9ZA-DYq1{&7T|K}i-^^c1h#Jak>Mj8~e~@l&A#zY!%hs`e=*nwzxAo3NAEjNt
zbag;&B{qAc5XyLcDbMZ`Sxh>&ga;MM_}>A6w6jhBEpBA1qfrfqlT^yH03InpjDgVD
zE_-`CfY;S4Ft40)3vmm~n4~;x$Qvr3LiaX9(-2t%UzM{!4r)QT*~e^(fcUMVJOPoP
zX<;kKm589bpDK5wf^|gE_&8#|fd)I3O73%+Usf5Y6ZNI2WJXgC{JG`bM2Nf(nz7+J
zB0NjLNPBt2ZLkK#7Nj8bVcm`PbnPcN$01r_oDNkmplQJDoP)5Zw|T&a&|(~SlnM$e
zz~*05=!DCxpfPbDop&K3+~V1j8CZ(DAFa7d$FlVUrP&*_9S+Pu{aF{3uRSUQ)6*kl
zTwaRg?*>7gaq&i1te?!DuHvLCq9=qcG0V_B<6y%m5js+7GsN={2J?=r`kSOmP<Zba
z3H9=3#FL5FqlvObj;9e)I7&QU{tz*|thyGdtBT-_h{3ON!L6s=R!Rj}6E_zvv9X6)
zRNii|Tt22kO2!Yl&XOu+6tL&JyBAcYZh=DW0JO9KcPfcnrAWbP&}#S%g%V1xtBRlJ
zHyDJ~Kv#A%0Qz?AiJ;WyLA2_sAv!$~jlZB22HnOU>1nRYvGmW9D$wf+c3Vv`6E~7o
zR9!G|xC!x7xqWIk_=3z9;_8ChV?GuvjjLrL@d7KZW!`z(q6a(hqt~lti~xR595wBV
zX8t3Ydw5w`s@@Txs!lanAx{phiyCJW11aA)ZKO{{vJmB>W)|e*@W7Pp!BATJHyk@D
zGLJJAe$AhkvT4E_M0i6AElTPZ_zb0GzKuQKw$xQf5njq}c0LkSv7%6Tg3SagZM!pX
zl*tSNiA29ZNA(I2kbyTj^ivY(6*ClC#s7T7h}wF6{mJr?9^VEy@YnT<{s=Jn{+5Ra
zeIH%NjMICXH_%%i%-r<xM=9^8B8&XgH(DC!N5*KW_khPDKd+tUA-e@#Zuwy0!59uF
zB+?s9_4IbPBm#&Z80T~|A2+V`=Et%8wCh~7-gEb4e*Bx`E_*<8I+R1*1d@Xi?Hn<)
zHc<M{`GGk<9&e!)o*^r0O}T7?=0;Buaa!DS4e9H)ID}|h8vdPxD4kwh-RRDJEJr=E
z&2mePN`u;3%y4|Ua;U8;RnQKF3OF6IGI+WEo8eRUy4ASFb(zO##+{yxhr@|I{ha%<
zaZtY8^f=Ny{^F6t9P!MUp0DeW@Z46tuhct=>_3*yUJPB{qN2G;c=hlL)N0NAR0_!h
zFU|IvjyE`KsONlWh34_H_jYqH_=i3i+#G6a=ib)@ZTGFQ-RBOXIE0(ejOWiTT(Ljt
zkI#?ig`tRLG+R?Y?i`$<#rn5>*mLm_WK^S1rtaR=qG^6>ZriXMkJA|fCuzbH_XLzJ
z4q5S1UD`Z+KI4f@Cn%R#PJWgqFmdygJJF$;H^r|y_qvG8_&VwPvc;e*pXj(v*~5T|
zc^a{zFbf$8!gnUKtoydB*|p-)u=(}SMhv!3T>7!F+OVanG;Abk9|T{QPkDGKrpo^y
zrQRBI6aN2wb<}(^mVX*7BzyE?<nV&)f<6@NfrEk<UGeKKYqs7uO*up-UHzMXxomE(
z;`Kk&*7)f^TMT!c81wc498;*<hUAsk_*F~Db11}(Ke*1hkAAzdr6hOf)mB>Sg-HR2
zgte1g|0Tk@9tr-F2dO|pOk4iyn-Ka-O$C1IBecA~MLj&koAewKw&J@tzAJMa5)P{4
z`jYqZX`Y7eP__&~tZ3W}@~Mtn=*_Tg^wfI1?)r(@;|mNZ#&jFIm)*UQ-nAuE4RMSe
zf=K5BeDm8$sy!qemMl81RTpJ${EQ2EeJfPZ=7NX~fxC#8g6Hn$3cPgCmk_e8*ihi|
z0tRCnB9HO;$Ie(>bDyW$o=+$<%4C~m-0t{AGKWG{Jw4G|v_rxN%4~dQLM=7{j}+;%
zd;mwn)dP4wrjVR5+iguC>09LB<muLBxr;X`dL=8iCOscwlMMCnxHL4vytJtqqYLJL
z3mA!tl#kK3dW<GWyk5U~6jHCF8c2CqxKc7!n?$K<7?93}1Fe_3>xCqhps;bZv;?!Q
zV~FjQqjeSJxGi8PPq;AGB+eN1w8<H&oKi}$&xrDUbQYktr#4NRJuP&!xYRIeGK)=W
zN^2L3Hg)0HMrRcvG^ItOAxnP!8F!Qi@WCvlzD&Etf{DaWFb_u7msuOKi`~z7XI!cS
z%I7J+<FT>GV=*zZ6KyZI(X8R7CElg3cOpkc^b`^^Q*qc=b+wBGc$zHQE8ecVe#vq@
zLhvZiOGw`2+{JT8lj|MGA|NW$Np)a!D&qe%<?50_(4>(M!HvgfSYAq^bZ_C^AA&~$
zXhhAox(U0=ql!TXB%%S9JLX)m&WQwc=SXb&EUeViS=v@<m;b<b9+fDLM_3cq7?YZG
zlkg1T|387&wxG@G5C&NfhgX53B@r)FB|!U@leGtZKb|VX9gkp0d_9j*P=(mn(!nY&
z8dQjzbMpkb1;@&6UdlNbUd4)0nQzbq14|fWoK8hZz6acaBD%m|oG3gZ?6~Nmt0flC
zNFR7D8s`d&Az<q~o1v6$KYR^_O$r!1IAei+=W|V34G@6qYP>kO9JDN-`dil%GUlzc
zE(UNkn#rc12n3f=Q@)Z8Od|D=@SP?PqKkhx7-vGu`H5EK*Fb=5aoAUUhK3m|nJK@)
zP;(PV&LCHiqKAAkN-ADfARLvn2*G(d#(QaxU76%LnYi(m?~IBTJ0yY{#_)U(r?Fl`
zYL6eZlnx4F0GN(0^Vp6~nuL?htHymQa}LAGq(_s0^UTfj19J#?5F>)lF3;V8TJlT7
zqpn!eJxqZE7bz(7zM(l;xC3}7YbqO8B`21%|Btt~fv)VR?tJ$-_egzPt!|%g%SLVd
zQIge0I0i1ZA&zlONtQtYG7-cu9fHYiKgSrt%XB8dI1_M6vTO_RFtQ&>ntVJi9<QY1
zki1ToljX_qCdZDM)syGPG(1@2Fk~V!jF-bBSv@Q=cnFhuzkk)ax39XTdj-sTTe@}X
zV^{56yFO0s`Z_MXeZ2^e`2h1Y38X_}MU8@kT{)P;U?whfq%7nh_s6LugMB1_lz_0K
z3FayyvOEGOjz97y#z+<x8$kgK63odv<3fm-hg7F<8$L)$Za%FMc?mlyRNE*lBC2Q{
zKhjcVN-5Bf!A${Kym!SQk@Y!bO7gbejq6fe4es>%9S*#PsT}Mib%k9>XL_QJGQ#t)
zt)_r6$e1?6_k1pdhb0&axno|yrc;@XxwPdm<g-)~BApNq`po!MINFkqINQ<qMz2jF
zR*I#;f=cjv0j2Z*KltyItZHu%pQ;EEl!A)VM;C@rh5$Q>!E(atMvo54u{ShiP_+e&
zgXa|qRGah^0MA}(L2OYn)|PKK=}HcPi{?P%f|&3ilpb43{yTzT0sLIAT6pnTNrKv!
zfU7>p84$XR7e#K4p^Ln1L6Y%KvR>X9Wp#T(4=GvR1ziY?Oqizj5|haH3e|Nny3fQ5
zF6Zo=z%EknncfvWXS9T9<}&Mwk#=!M@7m}cQ1i7%k8E_i7@OP&oO=C!=b-*#TX2Mg
zfFTKWiD4Z8^mv}&z#=erh&c5xk*_f_xkQ~LVALk^RtgxQPR<g+kDzRT$_X<f&t@U1
zs(SY=)d}D~03a(wR=>E$+Ij2LgK&+CmX;$w1i(orkje;+Y_^O<c+=s#<P<m471+eh
zDS8evU=D#6;RR?azaZQ?O0?&g3Wy6;Ug0_8x{|RrR^|=)d0F5t;`s_o;kuFXlp5|N
z05x7OM@>W4?LnN8f)YlUK#WCB>mFb?gE@+|;JSsr>aXDKA?;5KB+_M}0y*mU(q`BB
zW#ZEDi=YO21}GxauhN)R-qSLMfFcBuySIL=R@m3@i@770!STBa&v?MK-3U=<B-=HB
zLhW^{5e3c{^}*DgfGB8}^CACKz0p!^v=voMAzmsG;XXPrlv}kEiM^IVkk*rU$r?`a
zt&N|RqrQn0;2dFo?+_Cv)i@yZ4TvM!wAwZ-aR>im1n7kLsEwEl8HxQg6R_UH=wQ=8
zwjUM}Zs_+LV6PLK>~wJ?yc%Ycu;fY-YIWJ@V#H@pms;KAy{&_pUczEhwDn{=I~S(2
z<T3YWk^$E%79n%D_q;QEsp~lgSauHx8y@sk*z^~;wPhA^W^Xx^Mq@*wIqnIFC@uSv
z+Nb6Zfz#b=T|@QT5XQ^MnO1nXQzgx@*~^L+Q;iNEYUjt0{@Trt#HAf2uoKW-0(5eX
zoJ(dTGku-ozz7HLGW#oA%r@@D@-j=83_SjEr*AWMw4#!0{m4E=+@DFjoBc!IwGATd
zZ0_s3+SzepcS10(LahPncVMk(uAWApw=_iRt!KTRte*~@IH5|{&t(VTxmZ>>7IR*F
z2Z;@5>C%mBJley4TtHZMdJF@<J%YavA`cz3$zw<I;>nNdO4Q-tt9=cJ7RZ>o!x9Z^
z4~oO*4a15o>;U6~e#^X3bV(`G-f<_I7CYplHI`{kw3)t|V2^(*ODh>pF$Y8V6@{<<
zOWXhZ&r_SU1r5-iM&`*g+xN$FcE#z;8P~uR&2Lk)I#ATHIaX9cy<Adojl$&*QuOqb
zZ^?KE3<YO<e~!&`+`*$s<yO5pB4kcE$#UhyE*d47#^d;Wo7`egd()m*-u}7STV641
z?$&!OJc!IDf8-u(&oI7w@@=IrS=p*6W66v?Z_p5DCo3f}6w=+`UU;OCx)V8o>1&*Y
z&$6rQ{~ov3y!#WXRy%<9J3xv_Js)4A9;YtFnUy65sNPj`+_@At0&0avC0ZSMGsk3p
zzz(qZQg+MOZd=?nvwH_Gx#L=JO9D$p89Vgd@5yX_gT<j;x0>rNmz0nVT3Gr%$a*T$
z@xSy94iQ{t<>7CwEd~i6l*v(LVi??a10wHS<JS(_{PG9)#r)N^gn&O`u>WT><iC1B
zk#-KArZgMZQN}FU_|vROJj|Q6^&nIFT6!(q{<x5%>u*Nj%-Ww}NLQ~ySr9W1{I_PD
zY#qj!sbx7~so3;>=)#k?F*IMf6217DBG|Xa4Z-aIKK-T|ksK>+LF`oMsiGqqkL_B_
z>J^@L+L8A*l<kUlO}u5Lf)<e`R-Yd!c2=F9rg;Ue*Qg`jh;jVV3(=xZ+j{HNrLAVY
zToNva?0VkqBO&67ziH%U*cEQi-r1!^J)<KX3S*0x7FJ!!dvX@^_F*4mKz%9Z?b1eO
z|N9(%7fcXBnlW!hF=63dYw>HCFLBpvT*!f{r-RFycam!w6I;|%_U#>hU3bUKM&^}x
z^^y8Gh#cPygp|eEpcxWsNWLTa(x#;!2z<9tWtYb$2y(>+fuXs!dcf-$&^nba;1$Ff
zl;qlhxhS0ARVK3$UFKXnDadi-<aDPluxze@JOLRa{M1fE9%PLW>gSM$gM<@KUvA|r
z5m(q9Ggyasc?*0ORkWIj*{?<a5o>8pI)Zm_qu1V|d}1>4$B~Lfj_)2)GOlzZq07tQ
z#8mdaOSvzK-yChy8n0u-7;H2sz}w5&qm}WhYjWF*p%ENlOz-$=Lg>pAh=V{>-L6et
zN-N@X#EXdzG1kOgLCqj?=EDnGd=Zosw1f!C;yJ}6|FeN&Nd;oC8kG=;(3v`W64Y+>
zPO&OIxT*&=LBwmVxQ#VRiM}|20`XhvWG>A#-DV5HYOTk3{}v?wJpdVOM2Z;Ye4H)V
zL291HmJ2VC!!A@^OYd1X$K;Nf@^SSKp;}p~1&?~OnV244+d_@d#nVwy6;I%Qh3A25
zjf2-%;!uvKwJChZ(dZbXM3P-*oA<_GNFR}9AQa^o$#_aiHxcj8pXnz+OcsVzCo>;Y
zZ_9@tH?0Mqly@A|I~N#S*xoRO6KJ?xtFhCS9HYJvN;odZ{~T~6=*jL0ro9)`9qec%
z3=e5GdeS;QJ~kC%*H?LT(E*Xo5T#AUoMT)uA2x?=;d05(5l#J8c&ZOa#oIBv$;pp;
z(uJk<@l4_ca%Kucw3&x{5}=%~j2(0G-NtnC_p#RwR16Ytwv;IW?Kl?ZGN}~{b+vKI
zXy8v+k(VW?!?m+{u`$XWgoMPNw!<^x%frd&fojVT=*#FC%n+@U&!um>Jsz$vo}9g9
zq+AkLLm)_Pory?aVhGfQ(>`WJ*)hg5Q;e3H)Iv1j>K>{qHzcBJQg7};9PCILjTf<e
z=<;TE^d-y%f;a>`;X!){UA8e7*xgb}B%`O9AVh7=v*)tFE<ZARUZE{~nQ^B|Zm-TC
zi^}2A^Y%A&Hm~uGsahV~_L92e!E~E*U(Y{Fu>@*P=)|2fM5u1UxJwpPa)-KQN2w>>
z-9P3Y#<6gdHQQG-oqd53TloM!O<qAcFL$Xl9mZ56Pun9>TXT(;vJEOYNS5C<r^is(
zs$6}H<?m<o0}VTN#KMzzvNdmLVpO!SuMvyzz|VB1@~%!)N=q{sBMB)mNu?3#sJ2Q;
zMb&imw+Z%?O}=B;di?9$DR<=FrD_Ls!!jx4t3MEC<AJRsFU1KnTtL#PUS#v1`N1NK
zd*x7R*urPC8@_SK?tgCp#fK-B_t`8ejk|q;nh0}t@dxTle_}G*8`<8U<KkJ??=#I9
zbocasdG}Ph;%0+(^((w;v;ROAnm_AP$-HnsOOB7y4Y&BpX7P%wIkT2MX&KXC&1&A>
zH3I{`dBI#6zlcd0=f&O4tKI3jG`5neKettxoyDa3j=CaXQJ2+)scX2U?X$1rJ0Iiw
z^V?p3zRF}c%-_KV94f=^s3z9<Qo+3J3ON5+Zmj&P`@3p(UB*wm^D;6ijZ&q~|H7}o
zZ@0BS`qQQkYAD<cM)u=>-|T6pq!2ECXQ6r%X7B&SGiqzp?vMWYNKsP8v)UTC@uk<6
z+S=-`QzIpzhftq2avKWnmu@hxgPQ7Z{15GQ#PF*Wm#w}izBj4A6l>5tb<7*#q479#
z1^+d3`fSV6!-q3Fyp|PV<w7e~r>uPWuNJ;Jbu4>;0(9+HvghOLR5*mW7>HbfLeDT1
z(xQ<wa~?tTzkKY;+o*Jp=Gpj(NrqpKuEcsgEWu9rbZp_^(RXyAR$FW5HP*^YW}y0&
zR6jQHqfkGOW%j$Q&9D$L{S1B5SH;zEa8x;#YB)2TiR?zE@o2C=X1sZtGXvFS<qvn&
zR(;-foL9y2fvN!&Z4K-|q^*4^cgJ?%4uBHh5km?4ON)cCzt!Y<`<R$r$c|+`Bkcsw
zUBO<TnHS?=t7!Bp;5A&i){OnXyQs|UPG8y+BV&iHa#^^>o?_v^uftivrp1%ldv;Bq
z5oX0|Q%ZQC+21_RMTF#})&@P6Je(W8bD!YyK4g+CXw*(#WD?!frA@G<2GF^abPFz7
z<FP{ihe0ptHG~U{@I$QRO(B`X06d$kqepViX=R~l4nC*=K$~Z@V0Urd49hU^YbZ9#
zf}OR#wdC*%{EEmDmNO7vXHITLquGAQJtp0U_8n?pTZl?^9hLMwp$QJeFW7Zm-|^EE
zqb0#A?L#Bx4xP&%AzMHd{TiVc6o|Q4yL^^;EtQY7sdX-TwrDSo&t5F$;(pY}w@6fw
zf-YjA-3<mGQu(!cZ=$xUC=mpZl^(NnZF`{ErXQrb6yZs&L{YvEL3UkPa^s=#6`uN{
zAeU)ksYoE$FerT54N7?&a8O)6BOhW@SuoE)=xVqvdyQqNt<=^st`RoUh}RK4l!Zz+
zLu-E^D?^bq2u)a6UW;K;3eWchK6c8ai6!^N^mmk4;DwWfyG1lUB~fn>XoPgT1O-@^
ze8Vlo7?mVLCNYPAPii|4^N_Xq@i4c7Bk+sx%K91kiG~Uf2r=<dbw+YUQ?{Lgw5eQa
z@zyv{nNvJ<E=yER$qZ}U#l)j6yMT!pm|JtvAu~{ps`M?7icYoSw294i@KyGs+UlYM
zw^!J3VEnxWQiy(3im5qx;~CE>Zi%`@Y`^>3t$fe+3$=&q2KeH^WOa5ZS#I%q4zEpX
z3B4}=$>|GmyX4n1Lyk4$*O3=R8}wvasRk^eKc4FbZ2Jt&iZE|Vn8>BW;h`WlmiR%#
zt6I9*vr8hh=sCcsffoVJY6@o_uI^T2@v3Yr^;pCic2dg~FEJ%sA4JdQbEPYnKF%=i
z`odZJC;K_+!`*D{t+raekr-1B<KUo&xN)-;8<*DXZ~SvRj*{A5+ITB@xP#%=x}^Jd
zevj<#Na>tS>GYy+YZ*mt&GN-Pc3bBX2iBw(dG#%`ecV9GFiLOS^O!Nbi|$NIx{OI2
z3$nSLdMUv-u;V<U5Rlz9<+l_JVVl5zeZ`|^H}g(#p{uq+<bb`N&)6SFJ84g5Eb;vd
zV%-tnsFak$acqXQh1Vj|H+YlU8g~{hziISOGpViq=kgU~=F(~_oW*aX5shJki;wT#
zxKnCt<D#_^wRJ9>810-KnilFrweS42+B$O@$)yqrS~(1gUGS3vv)s7kK%BsD{~qVM
zI3$;c%YU7Y3q5G#^gVgdcMPxlmK7{<<&HRmfmBz7p>@f}o<G02(s)@^n9)gD61(3{
zqFX?Aj$Y@yd_kJu>ozW@Mqh?H^ennDXZYe8;S4AZv5eN!*P6B=?(rZ0Z)Guetl?Fn
z<-|`WOo&V@zLn{NM{}C1s`Y;&(VmXC>ohgt(JVYvofn$>euI;aYt+X7%pCu%?=-Ep
zhV0>s*-`iWh-bCcYdvqmJ<Z7#akltGqA}3)go=MXsW6*c_z75D`@)#>|CW{gH}FZw
zp%6%-{SN0cCB@Y#$aI(ddRZ!QaJLu%sCHgutjPndt-6Rx4i3c2cJT2m(b~<R2!9|z
zA}oN>W?j->|KFMCV)s6=+{JI9p0Nz;2$+=`y$U}o64QH^Xt59pl=1A`hEQNC9-AYf
za^D|WA?^mkEVcBP-iyc|ZTQuLZVEX?{7Po5NLopLV&9@Iw=b}(K5`t66a?8g?XvOc
zzM`F9*I@>SWsM^fv*8W1&RV}(6jP0+k1|7TZDy#gcD{tE$Vzu8z?s2*+X)jMHr3I4
zZrgu*d3?niYHMbnRPhgoJp1&0#@iqyO>0Am;?fq5z5?O{!<my0b72@25sHXPj{6rv
zBZ`aWPK>ZCtQnU==YP(<HzZm8t<wo;>dY>3a05d~h+IJ*Y4*)VCbA)_t*5Pn7eGah
z(7B}T66dwY)(_sU7opz1*;l#(+QOf$3NIC|h}^-ia}hQ97a7fmNskkNY$dY16AD{8
z#J<Qe%3!sy(obiswlYu}-?N+}vo>n0xA(kgx~I05k@=L)cW<sy6tj>w>T(fz9+uV$
z2rH6^XJSCeRcvft)=f|#=mg|xLN=G2)USN6dBo~NjJvb?lp<#Zw;U-U7zTVaV=}Z`
zr8cj{5g-VImE2U5VF6H_sc3_TgjTz@d61Ty?}dp^*K<*1q(UBxkwu8WSj`O<A|*uZ
zlkG*TX4_&$(UU)GKk(}xhNDH2W!1e8YLq^obFIqC_Q2$20^R!>w#TbOJRJ0pXn_n`
zikeZUQ))esJtrH0XK58EC&|07Rh;X(WaD#av3ey?L$iTsCJharZL3<LK|E>~nRGu*
z^?O3*a}<Ym3tQl4<I%(p%U&LpHCK~OuI)f61I%M-v|coqp&(wHwnAFiMimU;-w46#
zOkHc!T4ho!YA%2C;w)9D;4&f|P^5rwR9iJ+fm`?yvPZhMZJ)&%>~nD7qR>axJ8;gc
z#}7d5i`%gfA_uFfzRxJEs>P)e^zz^W8wtRI#P4M*$HO6WSd;}#Q->zYa*~Wjk~;&+
zi4&!5Ny9G?CD_RnkpyM~)*Q~tBgxNROhrnxCH@>P)h3Q9w4Jz<br6IUNK_Ts+$o;2
z3p~FvujG!p%((MiMV(HWd99MNuROzYp$4#3_pIRJPZ!tvU4=6r^<1q+1yvbG&?b_+
zwtsgIXU=(6p*uMTZt3%5ISfvU%mKMDgR$OJGb~RNWBo}4d79(ryFri0p)`VgsK9l4
zI0iyOODGpWiMM7JqO<AS$vXt3Nt>$EoW&B!N<>Z$S(MH)KOo&!n(W(|nSFwY9R)jn
zBV<?42r47TFCaKmvnJ3oemDWBEjc2~tAb^ZpE{L-lg&&`;OjsE!*Y)ia75@}HoK1G
zwUrqOZ5067=2uJq*wRldPUP2<>r=lRsceng^%cQWSx9e!#hc2avp2DHnu-{aK4mj3
zd%A3cAp_t`#t%_R%{Q*6Eo&jPYA|c2;liI1!dU0xFn~)XVvvpfR-DWKFMCFA-}sNA
z5-*QrS;3m7&#rJ$^UE1<?1o6QWJPpB<G9hMscY@gYSRF()VDR%mIs1EApYxAKIGr%
z(5>0&c-C4&A{1~~LTxqw`f$KnSB0hObM@q6I2ep`xSZd+44K?ORsZ}CHJffm$XTI#
zOdSI%)Yj<^YHKKzD;5uGUS_kr7G>?R#lvlGKwS(UEqC5W3XO}*eeuYO4?)vdI{;Q&
zlWuVI`OLC=KN4F~)E|jl)!$}phQ=kkb%j7Vzi~cl`p3<}pIo^%6IHtnX3w6yIM|7=
zH2Jp1uKbA|P>pSX)Y&I=xM9m9m&A_Y2fp15Yg#0G;0HY);~Qxf+O!OjTwl3oCC+Of
zv5VJ4j@;N}9e8&fxRe)vVELq}UJM5B$A8ZLb6d2&|0ep?=M(yuch5m2bNWn1^EWRj
zn65a^HRfN|auM+4+sv+JFcdm;{^%?1_7^xLduX@!yZuPqB)o_~ny574i<GeycV`af
z(-8CGJ0Z3M*lM-a#dyDW4Iewp_Li)+27l)t%x~&Kw@bNPc*jRm^XXr0z3TbWv|E=6
z0E&{_Q(Q4io~eltw`x~k{tKICI-%8mdsejgrbVe)1Ff;&vK_5{|F{^h)LF~*Yf2rs
z<oSt?)Yb_CmU?70XK~^`Q>kkG(dpWixE1#Yo}13a*@aO#9A1lq-S^vB2esAmH}1{+
zGyfxwZI0D>Gj~l!S=`0gJljVTyOCBcuCy_|$^A^?%+LQv1QK3k4|4E*>an(2>tls4
zgz~kcR=(?MIs=$*#yJ4uW;;?_MFs8`oh&qSEh=<jY~?ntDgWyC*+)+t3vbFEjhjfi
zfm=T-^%S2@VKeGGx{~q#Dlm~pK#;r%kp8HNybrNdS;jAEaKggBrW&_-yCq-NV&!j0
zwd4L!@iiDCSrECPDqM`}Su|tn=KQ~+%dgee9@!;`g#6Rw4I-L9EJP%7#y!^J%*8Ff
z_h26g7qi{zq~6$XCavRi!c2ok*vOnVK#$oS=*A(kpK_amTafi{1_jQVor_A(*wV+t
zSAJnis`JW(P{NCF++k0Nv$*X=vByYvDJ3)9EW0R?g{}kQhDZ4pek*ha!@<Ffu+qD=
zzjgae%tSg=(X2yxce=#9qLBU-@`&He6S2(WNbk39<-m7Ka0~>}3r8o&LjWmFv|;hl
zVUF^Z)yAY-sPe9mw^d{-Q2{j#P1mo;9rYnuwufB#apD#9Xu6;rX39*0>`&{I6I#rU
zh%*5^zb+Ksqn;UXT{~le)W&~UzGS1w%r&{Vz}hiDz5*vB5tHq^1czqRQQV6Q`$Ujs
z=Rk#XH3LEWx05avVgj_?-EimR$h~@roGhQ5!wEFol8&T3H6Gj}u@vOLJ%okv5JRUL
zklih^@wcSe>1?_U@r4Wnk!m)=qqf@BEwFH~ou1NYnxnZp_ghM);`gJn>;PQca;vn=
z-0}?O7)b?<SE(wbKNC5Tk1WttZh4kWjH}RK)q%#8gM8QE%%(^xWUkrPe3h8DMh6>E
zkhY7q@7C}{)UV<fZxC<GvIB_R7a?;JWP}Q{3BR4_!k8VWSli~@o(2!qUn2)z&o?T1
zYNc{o(TTy)zP%AfD~ogwfs;jBogQwE;U(IEr%8C$Fgr-Pi>DBL7_InH0Ps5*EXg8R
zN{<011y%D-?!bGp#;r3QiEJ7DemiCBZ1<`{3=Ua4c(Px$t#En6#hSOK)O_I&Oc(YV
ztf1C%z%~TJf)#x^*^JHg^Ub|@QL84V-)I%9Dw`3uaycZLU&S<z0^5qvS3)TQo?Zc9
zdL9ya4S{Ezvgvy8RDwGIM@)Vx@AI<MAo5WjwNU8Z>JX=AVYkPUd}Hzq@sX6J<TKEu
zks<X6H2CiTQqR?`^+c3F1j|?!m6YQb=8(`y_z&EWr+P26Yk3R<CN-2bdU!Xx30JP?
zQsOpxeUa}y#fGw>Am%=wnGdh>ERemPLtyccsg0hdkK@hnV;LRGoE^W_`~2TS{f{&w
zeyNJ&W#r)w`i83EJH|H+(A&%{6i*U91R&cywU5NE@xpY@UM5aR;Xptq4f@_=6Ky$p
z+8ryjjLUfkbAUE~o~f;)e0!deisiR9;(~YNvN<fj&ii10oqOomN&kAfrl)1~dl=OS
znCZPITFx?BZq>qPUZm;}S0)1u2U_RRYz}6D-HYOxz?h07JI`f)>=Vt^Mx_%aBWI<y
zwR3@Ux-^_SV@|p#q=f{uN!Uvg&m3WnVSc0*N*8IH=Ze1TJ^t0gj-JAzfjXc~!YqlU
zPI>z2k+rb=c3Zpnou%F0VaEs~c&}rp?B883=QbKFKGu5B+H;qQmEmw|nG=QD1nQ{d
zQF9><Dvfl~G95tFBAK$;)s5o;+Uq`<WltR$X?9kBz+3B)dxKEoCZl1cYL5Q<l5do|
zm&Dz}7id*)MOItB4BeQg-(c7uxsPP!!_OKmy0B-(=G#-><Q7KEFO%c7H{|&oCuNUZ
zeZI5x`*+*PiNg7Pt<}&zy2o^VYR)<^(T71ZlyCS(G3Q^`aFGEue-RWsa*gHr6MJp`
zuf{F&CmW%N-h&MC;NQ{KWP&*a7Ii@3PyUmssDavTpJIaNc_>um_#@X^a1T=bq(4^6
zqx4KS(v>3q@Yx&F-b2kA43#gO7aN_i32pSvV(N*<pqSi1nqCG9;7Dzmk&Uvwu>6#R
zZ1~{a&Eji*Pb=pBeDIg~X+v*sD4o*U!gRb}KJu@#(Ef!Vp}V|}(JOj35OVS+S+)M0
z;#7$yB^`_77ky&Yf-_s0<nx8%EPnurPh|;30$H4+uvxJ4-+XnmY~9BuVae?FQESH(
zl+tz}&PKoA4s_lDD$?v%TW$F^lG*r>UD)A-mVISqyF||Td)~rQTXQ;*X85W7RnksD
z_|d#0we|d4MwfM4DCtt6H@;Yu{=KUw^^shCt&vjT!!LBi=!2uFf^jl+I6$`KvyP^|
zE6%iSibBswZ3AwggMVz7<c-G%s4gN~eio(iZ>EBL`+%MQb*w(mv#iqM{PnqoU%+zV
z3_PG`3xbML&%aqtmYx`DCqY_%R-f&aiUcCPb;HBIK%9{)T6Qsd!SlaucTC~IX${{#
z{O-<&@|2&5xur3&NH4XgxfHJH@v;ez_e+s(p0`@j*%Um$L1*X{969iszfXBx>c}^a
zi^gTMFy+`UEnCqcFM)hz9%?~@n8P?UeYO+G=SbJk0pqyW)lmY^DOC}P4=6&N+`7Xd
z9|g|0W$S~bKKpi7BC<5D9$|ilZIm-Gth76n@wrj_S$&R=T9_DU5<yvaYdFUAQjH)E
zGJb71T<x$tG>LR@>&~^|u+~6#ncfP|%agqr((`P7#Fm|?><HR=#Wnm4e8qtWv!z*<
zQDVxrYq(~9(27&15X()JE7g>h(Mg-io=K?(|H}A!qet9pxlf*h&9FDbZv#j)HgguP
z6IpmEAX0u%<=dg*BGQ1hRou*yJr;9EWC}dL4!^<R+0PO&D%FiKyO(xfLnLV3B4Q<Z
z#CL=AR2`Rx1WIw|j@OhmnpLb~6tc5<Lg25KczT@A8wTcm3>s*-&i<27NnC(QR(s&F
z=||e@pm^8DF&JD74uMBl&yZ%FUIp`-Twr_1O!RWJ)bMURB;(YM#_gt<P4N;ZmnxAT
z^(pgsZVwL3(cq_AWaZ_cWr?i!brdC8MZ3u23fAyRgq2Df@dx61P(o2lGGq?tKsaDU
zn~eRCkm#}(d6cpjfyydqq%@OblUeDYsMzWOocSY&B2HA$Fwtx+<0|+mtX^0Y|BfNI
ztPLNV2y`PeQ#&2)P>jUFmS|n{^z>9icQN^ai`l*ilhfx!b`Z|Qb(DpekEH=#NNHj2
zmTb<6*$X~n@#gpgGJal`S`c;O-O5u{q7t~`bJj&9s%#g$EYXmqC1W^DFYZrBUFJ7O
z*|spKv70fYtH{KEvSKpDXQyZ!;R1Dk3C6N(YuomZrry5!$*bsc+&Ng!C7<6Py`I1&
zz6X2`#@QZZV)y5#z`kY~wUue^>J3if$sRex$YK|?ZrlHpSvq8zoytGwQUc*)zGIzR
zGbXk}^wHoWt_;i`eMv2~gt@gT*}dl%{GA-B3c?tx#yyXMF$puoTqnbQOS1~FwaEib
z?bglReXc@nUCusq`9m(emeOR{GNv`nTGJlhIs)nCe?8AiV1r!{n!(8OSOq(Ajv04F
z^%f|M3fc#&8OmN@M5@(Rnhhd*8MH_EZ#CfTAOrFT@z(n^d)Knr-)DA2@$<CcDC_nR
zb}fwCn+e})SR%F6Q4+={A^qy{;e{HT$`j*_RSubQO!w5Tk9O78>%L73sdjn$-Mh(w
z^hb^0ulj&x9=;3o5_Xth>XSwZ#XM(ynI+oA>IgX<3Zz&05pAdC=3`+eZMhkDhgQ1+
z0nCPgwEkO{*)+OE@wKlaQplD%K)YJOjMjl!)6CPV8EL4l3<O?~;o|qe|FMQ|KXl=2
z-U{=p#As=5L9t)A@dC1f#lfIgxq5!`36p{PrYo6xi*-`A{_Rbr_s7^<EzZ^#ndH#H
zuYHbnfxn-dHc|=CwUm(|z);5jvmdkU^?w2*kn_DRiyDsFim*S#IGl|^{zE&_A0g-8
z!Rr9F^2yI-uZx-%p1=0Kdy?9^>(BGCxZ$-ztRIn*dKzZQ((xzexTWWJ|8*y-tzFs9
zYDIEK;2$_|xBbJvaO%;^P)Cs-sS~7U7I_JnBWrf_8!YKk_=oGMiBz?e`@pZ-(VAw*
z=pJu0YyXc!&HU$8lxfGfQZNzep3;q~aPm=*>Rfjv`3z?g$if{~IH9Q0pFEW1exf<<
zca<Zy{|k*G5D?xoIyN!9rt>k*E3Ri#&9Aaq1Nqifl<ZN)%eURUH2K_~`Ob-B^TGbK
z*SUi>2tG|BZS+TX_ndY0HUBfjIE}zhY0~Kiej8BpZ(YsPL41`RYU^0Ijw*QvMWf|L
zpc7TQXdP^{!=HlSY4u&8BOIqIKMvVW-QA@i8Uruv&n+*BNQn9)oMo`w2Z&YT7zR3w
z+X}DFf>p1|nD9Ic|E{y#$=PazJfcGO3}+IEYan?+MfTfF$B%GVR9TD!`^1=6MKQPZ
z20eyAi`($sKEJ=BVfKM~kS>(@l~`e9j*{L1NE$lhM;s$Y9ce=`GtZcplzib8Fl%m;
z@EjG#9XPIO5hYSX=voFp8#brGe|!-~0o3S}Zt1YE@Js%3@k^s+Z^nP3=N`r;=tOe|
zM&)WGCY=2a@M{!(6QBn{%%mADx*D%BFtVw$pvtY+M+X*rg@R)kWTu#oU&U_|RC4KM
z52TG($v(u)lAvf1?f~P2_)c5pB~9CLMcY;rca!GY74rl>O*(ttHpuoV&;_IsHNvn!
zjok@^8S0B`*V3qkwjNZH<Cp@a88a&q)u_$Oovq1xocy&(0BaXq*D~noSPStWR7I>#
zA#N1ti%|Hw@yV|)s2I!<8|jpRpZpt6687z<kWvIqScS+iPWT1S#YF)Wpv@^I{Ig9e
z^5?1I{Um!RK6T0YYAjV!KH3W!U<nqYZXn_1-E=G1)VeiFL-Ei(Ns_y>Htn@wr-UcK
zBU{auHRJ5%?nyfUL4Ziz>_zuB#+g;|6pa~)MBB^#``2Qu@GEf5Y)S$T;)Ws;>9YHk
zO(+8#N*wU9NqschF$!x`vOBeytpRO0mAFWT%u%%h<08Y-g{ro=E?06pel<}!w*znU
zN0@p?`8XE?x{l-F&PKQ~`!L}<NG}pzb4iG<o`X@+en}>*Z%zeiwqpJ;stQU6DC!#M
zK7lqf7&`<9UWje6FT%TIhs<LA<b8z=EcQIXmVCvuhy__Aq#D?D4SfbMLMBtyum`SZ
z+rr`lOm*w5m(~AcYQ(y1Q6fBr(eYfj8Ep!oh!1qGlx-l47LgHEh}fz3BbU$NsxAp;
z*B9B|Heaae58c-O`6=)1?kuyvO>eJ=xW+KAJ<6E=wmCm?jN3B8<iuh7_tPsmcO%7g
zM~~k+S^8V($6Dv3g1;hdaB!#o!M21p2ZR?;Wo~erJ&_d`A9*dM=C(0KY3c%FV6u9B
zeA?*KMPdE{95*1ds8FYXGo4`V-u^*P6gINp?dc*2i>j5VaOhR;1hEvOm4Q|G(uieY
z7ggZ~*nUn*#-}L8E0??2Jm0~54uujNOQ)%dlO2Bvb#iz?gxSX1Xc6bAt@PpZsI5!f
zNx1Z9M_3bT?IQm>fM-~34f}qISL)jR-O9+Nz-19yC~?2bhb?E=@VfpxueQ0Dypyv2
z#HB?}&g`D-vM{sw(~EJF<<d?6R97dMJvDdP@H~JQ^p!$i+->G?v78=3QR8t-t{6_*
zh7<>hI&D71f@Zr|{ncg7@#4m;yrQ=tOURCLtF)?eU(@~OPq0zt+2C;7)Ri3(2@BFd
zmABZ~cJuUd<bO=HdUhoL7}|1(EOYsB_FJe3yWhntDWVX2UFs#p5JuaUIeeSsYVl;N
z?s)Ln9(*}AerujB{s|~B;3Wtxa*2^guHn6XFW+MM+5<EG&TrhK!R=6(oqq=%0Bhjt
zTfNj)C5e_6q6UgS`=tZVBZ|3u{gs-tK(#C5o>-ykN~T<s71j5hmyOk`of}G12r>0t
z7r01HMJa)I*ED-;@(QTP#(|^XV3)Th07T?Jb;imDEK@E_L&1l%(T-EH!vMsx^(f~S
ze)PVWOW}uGIC>#jNo_3=q$Xl&9~^9e?h{DPt03y}vc%QaH&3xqm^yIsBFAd0x4Ca#
z=31@gLa79M&#19uZ#azpo2y*bd51S<`XCo0_-HQQb|75z+zY24>rC1$E1l@K1LM;+
znv^lE%4{f6fTR4QPg|#K>)mq$zc0Pe(zhA!qJE-3HiSBZ7Rb~d!QuPqcccZLwt%?<
zcp8BneYH=RngaytHBDcHU3N1Qi@kIDF8kavbxT7U5&4^`@>)=I3$d}mI2?hG9nw9|
z@^B>`wq_|~S|oQ%R~NYpM})2zqN7I^meb2v{eRB=E*l<?X_~k~+CMC{wV1u&`Byod
z%OMJL>8gd-)iT9%TL=YjU{+htMGeHE&gsij+z6Z5o~3OQ=?f52yWrdH@*}6dBa69c
zMkA-^W7_0C)u43<bUl${llh^m=qWsJ70VT=VY@>_7-B@EgEbxc2Mu}S3u#;tc|*ng
zL9I*BvRNh#6{v+nVJBw?xjK_xNh*UOD7e=ANY<ML8Job>E@gHzbYB$f^44pJx#~1=
z?0KebRPtG5fvK$vc(LysvJr6A?Z@6i@it`#?fxl#UhmbEccBb}HV6m??qrZ%3X0g-
z6>V1L?!==&&{pwtquoU`l?gtYD-XU!)K%@Frc?rG!vVwtZCi+lD>eFaD0{NzZA#PC
z+>k6f@u*G5jH0%Nz$Rh1^ESiEbC+f7kmI3H!Cj^f2;}9ECDGNHrXl)zuZdLhK3G8@
zu{zAjvuO>dXO2KfU^E~IoPj8FDVm%Fl@{?WOSzQiwlGo=<7$EvOIRFPOyEcA5tvW4
zzw1Bj`H2=7uoY&=ZK$!8{?(Fz_*HS$;1-f3nRd3e{0Pn{<CC=3MKbB+HylPooJvoK
zkQK!2Lozypd}^|8q~QZEc2%voM<7y7oXOYmi{m&s1_9NSQt?7*G%7uSn!5Q0d66)=
zfGR;xvX$ID7deicwG~yql2s)(My-SOfZfddE28N8P{X0Hcec03D%o-p+<ayagc0*W
zg*6nIuIaIxkkuX3;CP0!f?Zd$szSsPdMz0C#U**ifFXuccq3{Qm8_)GYc_H-raS|z
zwx&QfOhkUpEyUcNLEqM<MsMb~4DX0S4C?XGE%1oHbat!`HBcqog%s^X9%=M4aD@$5
zTN&z7DJs6X)g#?a)a<K99r-+@INN$no5OrNfmfVT4MmOVUV#)NoyH6=fagzP;p-8e
zG07TZBPLc3<V756Y+P#11`8Odtu`O;7Cu%y)I560%uc8>1NL!m;Z>^<nfdoz1kod(
zKwG9g>ICV=&G<1C%I>1Vua7Rw*xU1R<aaM;WB#bqK4Qy{WyE_K)j?N74ToTjzxJ$7
z?eF|yd(s_XphLF%E7L{N(Ns$zTSMR^FLT$YS4_(xY52H-V5)Jtt%Jxe>be@oJt(!+
zmA3K6OE&h?`wJbZ`u+J!bk=A%w6dR>^INaB-UqcGy==n1cqE?-N6{U20BxOZjhk|(
zPEYZ^iSlLP)YXH0EqgwlJ=|nZZ?4OE{`8r~!fw`9$HF}qJ<(N2S`~Vbwf<(eoqAAN
z-vNAnj@CKx9_lD{F)nLyiSL1DDO<E<=}po$2>1!RgnhQNfB77xiApnl-RJT`T8~s3
zsaA?x<S0fnI~i}<#oq|l*2nDsAqpqwF9G&!QHRt@e4qeg8AuG#M+n^w(2#W;Tty(K
zFK4mtr8dqc;kmflD$Q1#cPhG=&LcS5`aJydKes|^>+6)%F!*P8+3uSU5lakEj}s$2
zr>?P)@DfJZUmI_l|Dzq=B<$~4;0vR-lGL*dMo0$E;^N}mMx)M>gk2%Y-#AgE)mGLY
zOUZUADzcgqz$cT^+5Us1fRe^wV0ytP?G(K3*;ZW>-0t*~73Bhqqkq1a#cnJYzX#2#
zI*)mx%Tn$Go(77}fenSuN8d;FdnmW?#tYMTnuxOgHEs`8WVc3D6Oq6#|D`E>utc9(
zzg*9Vh%9=1uvN|r(!Itl28tBbR)puj|NLfoB5+A2GGn#1@=9bFT)=8;+4)t_los`X
z>Htv2Pu|uDW5*9<k97_Q8(F&|BE-N!M)>r&oqy^dG}-oYW^f&Q+0#S|`j`vKVN}76
z-^dK3R6Eqxs8P;W8e80vd~_#K$3B#eiLc>Mr=AcuVjL&3;fu5s$R3Vl364S8spW*}
zf8LpWaVm0_d}?zC6Lbu*!s|O`KNQS9vqV9v>!eP+FOtA^YB{!5d3xre^z6bCeDqkp
zLB333%)T`&#q7(?YOA+KnU%-Jy^AG7u6DNCs_1TC_W6}-HnnRUiL>??pJYeB;eI^m
z2zy7MH@0W6)lIbfROFb^m^!}sTo&?0wA`3w=gc+dgoMu`565qlFmP`T0Yor)09dB$
zrye=(#o+2d`M_M1Q?kN`Kb6~Bkh2S6p=%rTY^86)W%-yj=a(YCo6y}E7y3!R82k)D
z89yI<%H*`u^EL7lczz+ri&%v`2uK&=(gh5KhtDT=H(D1vy5*RcL=dmkR^JUB`kcAl
z##x&>gGa44m}xFXo>PEZs^C|PbxR<+fH8j(Lt_=8g@Eaqm7B#e9L9sW+sJ<t)LL1z
zpp?eLf@|YR#}M#H5Ju}xDP-k*M%=7T0GaIr-)G;(+K!cjEC|GK%%84gickk62bt*?
z3AEU&MNnZ`?lfVNFOUVg{+i46n3fq~1=cn*HD@ts1E8q-wlAH9ClLjaX6c_5@Uud<
zaz27*DSq@*^zNulksZHYfcH3Zernkr?aIa@k7IY<CsYHVa50jw27|~tr7f~!q?E`O
z#vK~n0ButaOsfP7(>4lO$47euFTv(4R<F1k)-3V&1kEJ7aC0G(@Y&$U@X4*P6QFv9
z<})%yF=bRqcnQJ@@x{0_d4x||^ey2o$g#%H%a-#iJ-(8iq~5_N=n#jBmVlJ5o`b-N
zGa|$y@WNEWHOPOF#C%p*!AN~*KFxj{sd`=jW-EaV)5atCjA3W)eYs@&L&%%@yqdWV
zdCEqdBdd^_2su7*lTj~bL(_X4`B=46vaTfcu@H24wM$kON?G0Wa!@Y~S#$Co!6DJX
znNZYla!w(xQI~>H5Q9PnLMW`GhRM_k3<vWuMN+`+6tg#HRgjsEe3a%aS@g0<_DdqG
zEKYdJ&`@HsR?V5xNhn5tO0ZIK#2F57))p~QiMi~L!dO*1&$CLQ``~&w(7)<)h$VCU
zLHWDbW)#V5V@u9tiJB$>eOcF660TG2VZ9EfU1lPic&Q@^e=tBc2P2Zj-X$9u?~&DU
zKmBcp2=xrI4Dgk(7}j5qLo9FXpimj;F@h1|9v+&(_W4mIKnjcqWf==mfI2dhmmP3y
z4?eTj^cCW0P-c@$r~qMv8N;h=y4B8F%h{fgjUQ(JOO-pzILQMF{W}v2oCMEX8zeg%
zuA|9k6CsL{60}Ms_&q@JJ;ePUqJAf2RbwKkA_#&ErQl@w4g|1trX>`#x0p~Jy+=ez
zCh+x>4z-3J&92ARPq(%AAYVTyaC6ueoNh+wcR4i!4y7pLE(NG+D-8nFa#QOFn(yS|
zRiS7{fzLg*j20Ki#sNo^xSm6xN#|?SaLWTtF&oDQR5EJ$IRbhzRiQcsF3SMClPOfd
z^Xlyud-B=RtXsRz^9M!;fv$2>tWD#_UJ6c3L`G`HdXao4BpKagnq7+mqWq%eyEW(+
z%qwynE%6LJO7h(fq;`s{F{<wpaTt1BA@SXrd%ebT`xWxD#0x3pymu#@(<^6$KhDli
z!}SD2@zGs2e511n=I6SSwgCWHQs>jPkXrIEt7=11vkp@!jAaCn8AcyXyA}>Rs&gYC
z&BCSM-;E3Ru$-n)2GC1E71SnpO?o-IB_ulu#1imLY_VMAQ*t`f3sI=CRJ(Xii&)FG
zZ{Qgt2_-sI!yS%Zy0Q<1icrP!!V&}6HMYYY^clsgtm!iI&2d)l7KO6|C|!m2;6}+o
znh~`QtuI1lRa~vwPq^AnT(_8R@f^eG@Ql!Gn_o0VnzZ|tYR|!s$rxM)<sr$8rw9m6
z@*5}Q02S+4^uch^((oKUFy$8*4dtqy>oS~-A+VM?QVu0(pN#5DDlwUW>Uae5b{3E~
zX6^)>eiZsE>9r6@^79H13PM-fupUxoX7Py~zAy$rSSIgES7WX&C@CPwDDzjuY=&kf
z=P;o1tLfQvM1-Fj!YXutrk7dZP?&$%yc6{ZftrxGPb}3O)S<&4Bt-2y7iN;MVt|ik
zg;|Ii`I{B}E=DNDrt)9)*ut?roQ#8Og$G35h0Sr#E!8fbo?VtDu`U}}iNx)j0UOn<
z7FTqrWe){M4OtUbU6g$hj;p!+6LVU~nXni7&=<D7b!itd9?9}%+z9xogjn4~wm;@<
z<dK_K^3U%xb9aAGvxQ|Io&n<yVSUP_D>y5C67t`#aYGFBtM^Ka8xA>FYpjOHM^_W7
zW+%x~b&t*4r8ye{&3#{+Vhn#squ8MPVgF&%?m}AYA7Lo^F~1Zi^6Zkr<JYteO|0z%
z7B9E*=xahAjxb(`Q=kyJGRE{;3W_kvCLh*e=90_qqFAau(7BY~-{Toxi&0X($K&h_
zj=LOd#nk&YU0B{czpzJW%lJ2o_jYSMuI(W_Xh#p(=xn#j^kW`G4$U{(m%SEpR(>!$
zx8VD+yY{Qcxe4T3C=1mtIJl9hG|CN1NNX~DCZnvv{d_L!rzl#c^dI=`^E}Ho86E$P
z^5JgDBm0_m@jEle9VwZ;_9EX+c+iuc^s;=i{9>~VLSw-|bh%5!`#6LDY(CFI4sXIw
zm8>o7HhnJeVDtUR`nf%YI6I&vrs{oMP=w6W@&hanh4+3V%Q`>6ZLII!Yg&5IsLdXs
zSRIAMQc&Hi7I$k&g9OD@^V>-vWBIG8RsZ9B?o46TZs8B|(%rJR4`mwUH-Z1wKwAFZ
z^h%!j6N|GN_z#5g6_3-XcSBMgfbYW%PdnCFuAQ?#xCZafj`al%u)1H*D5v+^BWc4X
z%M;|0C9!of8CJCtr+`AjKFsIzRQN%%&;rVt8(QvrOj@j!4`04F1`1&ygvLuwd9By@
zZ|q@WA>~9VOi+M6?qJlxI|AZJ;?x(|+FCExA*WZ*z8I8QT~b<t5__(4CxlhgtJVF^
zzvais=4q8$db=oKU5=PatXf}~N|%a@>`^;p;XhHD;}u;8ocYl=Gh6Z~1*q2Wl_?f;
zsQC6q;$K{$5&!E;qlCix!3Cu{44fVOCimw28dIlY!1dwhAI^%|<J!G;+o)Z5d<;@M
zfab)WLdVpcj;ZAV9wp+tFe}8$noK-4H>&`y0(D~>U7Z6T-Ow^Cv5r0WE3w-8=Ee(l
z)<@Xm$Oy8Xu$C(YRZ^||ROtrlOKoBFX?dsCP!{Ejz)}=(c4cmr7GLtyLg-erXy1u3
zlQH1C32`f}K8Ph6-7&YRYsL-P5a^#yBZIQ#GVL;Kh9#!Gelb{F*%BXt?e7!gjGdh;
zCc<A(Bb7?~_hN#>3}?Pr-f#a7k)927!G@X<-!?SWBAYxLV;i@l{9<xm2pt)rY^63}
zCArI%61AWr(=V2SJ~P~7qm#U2*bWS(M?pGiW4qLI34AnBOg)v1w@lE|R{}P?MixXx
zy%bNUmrUjr?)Wt+tRWDqkC4;Kf*%;clb9$0F>8^24in4xtjN0q$4(ZYudBF{&dx_q
z!euD}#t`u0tuull%Q@glg<-8`Q&Vow!8pr9bFQ|k431k~bibpm8X^dp!(?LXh|Tz-
z;Yx=02~M?@KJ`JcSYdem_-x{qd=a(@*hnzVcNZwR8XPRhaiC>+C`n9$x*ZRvyw+ry
zTpMLpj~CneOB4iWX^9C(6g$tM;K@Rpm~MR3#{xSyMw_H77^;gkNR#5ws@>-q@P;U0
z?j~mvrXn4%KmbJs;9}8)X6|_{c{~npLxrF|s1FD9`6R2?!|^vK9g>~>l{|I;YiL4H
z9`$Q_L}<7)AI{oR{t5B>N{TFy(NzVj;IbA*Ckt`RVYkT}=uFyL2ehFOkZoCk_6B}!
zemx){){+Vz52aF7XP%)+gskE1L!gA{8npw-5?#ZLs0z`c?G4Q(Hhf35HN|o1q4p3#
zc@rq35yVKhmq`0o5s1{*a#}_2`PEfCza5sL6mq*lzI5M3d=4=_n1mZPqu~tP#jtyn
z8l|#%CtQr|NWM&>J0dU-;jNbqYj<zjQdm-IJ+E0GqEom6t<KHyj7?r1b@i5YI5^08
zU*jQYQ@gygcE^Wu;$;If67jRNPkC6%o9|V`J|<%LmPYJcJVEOtR`jW@X9-GVH$%_o
ztRg}~=pw?I)K+aGU1j7HS&m_6CEmr~{LJ@T+0h2weqiK9o$oZP%9oJ*R|#AC_&WRW
zcL4tW!15u5<9-l}4ub*iLKM`4c4TD3k+AN(lRmpKWh0foWDV%T@`CdlF~f!3HAmG&
z*x@}r2?%Rj@Tjef#S*oitk}V*^B!dk;M*Ey+V+@vu5zJq-Nk2{+=Y&ffV@_T+nV_u
z6492)?*!VYt+sL`U(KtA-jx<!8tVAyHwkViXKNdeJ7|BPmXYOZ&q_Q;7*G14w(^-V
z(qLy~wm@duiuL#5IQJyrdjl0;YU{Lo2LYX;9o-+s&Qe<wH<xf{;k!Su9Hh3o#s#V}
zJAhYFM;`xHw)*6kcTH*kVHma9jc@FVSA^J!udmp0iveA{Q-vc{Y`62NO-jQ(+TraY
z;?g#}h`si*pvQ3FYm(y=&wC4MkJLZO7sX+=oxi$?-sJ6AB1>QPbhg~RlEZC$^(MO=
z^<yfkt*3Umr1glNlQ9r{<_Hg{tsb=%#Z6;*-UHvHw(#VV($wD+-D7+yZ$F!53!rk7
zO>Wn1Fl`e#yBmtAt<y2mx9N7K5yZo!a*B%_!v%X$sM)hAwN(Nd0!?eZCtI}#VMiUF
z??Vqy)4%`5wWWKE&l%W}y&75!hqaGo<}djG>%<$4I0NB{^D|4Zg8s-ZKbAbCKWb{?
zt<TL`IQoKSsojRR?7FCom+f@FNKtnFd?XL|d}Q+q#&!&>|IW+GT-s^uQk6P6iiaA}
zmgBa^$WOf=(w}^Yp%P?Qb=yn0XJ4#HOig?rbH<bf8v)(=cBK0Jxn<U*wp#Ir&rp=7
zlfd8f=Ct~>9*axpIlpqP9?&JV^(LnF5eR!LD{uSIv@f&p(ETIrdJ=~+{wWKwC4K4d
z=v*eREFx#?2gf*G*vG<_*2bc}@ay)b<#*>)Q!rdV)`x$~-0`vO#ml#yzcg_|8wiHO
zqFs1XHXg2ZMVyRlkD6W<`8O{l`&4TGs$iTfvsnUsV1M4&%SW2ibi|e&eRW4ii)W>`
z>4S$wV`-#qcfKIXWGLa%y_BkbsYVt6sRL;XA7q(7v^+bF*QvKtH&sjDcHY%&w`P0J
z=kBrM&ikEI-btoBO`q=_p}TX8;&%X=q@2l?cDEYgRDM^Auyk|cnXTmgDR_n(5u)0P
z4bGAtpZgM>G!!A9<ISW<9M4>N#hjZMU&?Lc4`QCgS#YSWGxIT(L53snmFDf=si~T|
zX!aS`T5IB$a6@W58|w?$)~d2kY$#G!|6+Kq>uAl|{37(4e&M0(0-oLLD;##uFD5{V
z?-bZDRKz%tb)Sr}JSDgq`EeTXv!LteEd(32qDskzl=J9l#2#xc1?<cWLW^pvcaW89
zJMf#DMG<Pe(j`lLbQ7qb5+wW;9i~<#&D>*j_zi*FQ)w)0iA6erV8jxv1D#D=Z5czJ
zU==Hw?Pnn5LKln1<75xo;6it-(k-pwBtbv#F+-b}1uqfo5j<I%wboA6$Ch14#i_~E
zNf@m`{H)LO(LJ83R4gC}CYduwt!Yj$Edh}gcB+-kv)Nn>wJew<IvAEhV71?oR)S*G
zM~h2N5n1V4)3Z)<jT3f0T$d&xz#iw=l(H{=i_-SD158o#BJ-A6%g3tcLGgI*1SUvp
zp<74JL<o_CsnJ=yGHYk7c0hJ#;L4i)Si_tm!Ebz47J}SJ((DAqAWb}eo=>Z-S;$<|
z6H>J8u$KkMU3~1ssHh{6bYFg$8LPR`BZ?;_HFZcCiobfnGx>i<rqayDN!H0iE(LK$
zT9$J<nwk@WgjzG>V*xte5+U=^x5WdLAXD5ovk6p^B*Ex6%$RlD<7mO1g%^{k%*SbO
z$tYh2X?91QaQ$}klo@*sjYJY)74%6Qm+$v#<XrCO0$xH2b*`JA5Y8}Aj7U<5p{6B!
zp{)Rdb~Jm2k2YFpTgV~0x<=%&uLgAe&w6Uc8F(_~V#Ujmpxdw3PFFvzkFTUu6A*RM
zZpbF-#Av(ma<Vl81~B<h6`w;4R*tB$o(6ITVwRj%TbFmuaR~|QE&eCEwd)MpmNtJs
z+2m^&d3ZtGfESU_(lj`jwMTA7z*lf%G8c`H9os$6*SfOTWm@(Oe@CVtYw#foRr04&
z+GEuPn?$iCMR~H?N*{hYh2NJBWwe`I<#O}-wUq7YdB-5lF<Q!4HU!qrn^YwY_IRVY
zCp;F9P{Wx}YG`*Y1D^BQ2C5WlYhkY^3zga+vg}SgSK}diB;)yAwL=3d?laBo(xOv@
zi4J6|f}4X`jpQv9Bi%&_EacW{!(#qMXn;K{wbkAe_v&I91Pkk^t;BMA<DCUgtF8a`
zCcE<|@6W<menIo_SqSGkRoPxO?n?B75ULk>qr$ZDt92bW%W7-B(%Kbl^<R3Y)z+4@
zwB0Ow+J%q$&ihWyg{a8B`@gU0H5c;Nyj5uqfs%?O{h)k)j@LHPNL^7x_U4=ZBCNts
z6}4qln&6PXJ#l^P?n32%#BRI)GN%rr17~X9)H}r<3KXO}O*f|1)=wU4qS4(S<J7CI
z);jXiNF=6dC%(-wQlhZh3cuX{qElciWo3m9^iAwLzFxY$%vEusEG@{YW<N}UesS&I
z#qi=$t}nTpUCDn!RU8W3df9q>cQNvdWJXQY_r*YMb-wt1bJub@XZMStHWbtVJ~ri>
z=#Mk{8it2+`MvLNsccbg{Qz6Bk2U=MU9`e@O03dq>y6<2IJM^b<7;vKwUo~co(Gi4
zp#X_+&rg>{ywpWxrM3dnBg69R$Qp~h3&$EEYJRFGRd2PGs#X4rm*rF~inGIx1z2X1
zB#A?bYzrMil!fXTb5*xrm)p!8nTpNc^aTQVCJhuzL61Y7L!-l?>5g{Pa1lsa2R?og
zuL7#~`h5khK~;<FyI&^Ki!Haw(<tM&GG9e1cIu$#RW$@U2=3s2A^J}fg_1SbU$P&*
znUL=*{1dl%%VuvPcsPX73-@GAbilZ%S_XI&JOwLNgXA8=@if1q|A<ksI+cygu8hl`
zOXtn`@OPQRC+Jg*fk1Uu@iE-E^SlthuPbdi-6ezCN_SWM5ufUy|1S#27F~X<)Wuxr
zk8vVzJukgj4qv3x>Y)s$$#9=6WLNVZt8OX+J$#I_ME4hgyhUh5Q`=r5h%B6?KAQz%
zCI%zfu-sriJw}RZYrc|=H_MJ4oVV;zdrGNz|MD|K2;5skU<bnT<IR?Rrc1KFScya4
z%in;xMUKri=#z(o-dwMtdU%Zq)B$w(QTG>R;$1LI&g1J1BXfAJ^Mj79tx~Z(mH?iq
zlJyyK4S~xQ+slBgPiZ;gthoiu`Yj`l(j>kUrl8_CJq<C2K-#*THasRog%1R8ZDKYN
z5&!2voygfi`DR4Q5+5&5H<`ML=#YomyF`Iv*pCrpd#qb)<k%8C{S^UW%RqU0GKqlf
zja0ObJO)FWanLroZccoRFzWq!i|#luuegMdYug*jcEg#Uq{cgZd>f-^Y@~0eeHw=V
zs!?RgwXF#;Evmw(kIQ<qL{r{#epg$*hIE~c^4dK@h9Vrao1Ta)js}Ovc=(Ds-o3%*
zFHZ=uM%LDC9;JQMc&kRWbuJ#5GT#B$bp?9X-7Xdhg1|g{;R`Z1j{|Y+rOtU0vW8d1
z;>98AYD8T6sXWZVTQ@S!p`e44np)cuNT~k$0(^pa^OjiWdb-8RIw;)4ft?5q@<KfX
z$`$d;E@-DR4uK{+gSVe+L1Y<{n(y@Z1b)nf%G?2*=;G*2-UE^g5=$3y5efW`K^8l}
zMJzKH@vKCZ)z(s;K!A<mz;sCw*T5aPXVli%8A)x;UaT|}cm|k343JF_ITR^zv!40n
z%V@xRP?VX-(6q`}Kr#4xi8L69^B_nLp3W&-JS{8impT-IS7qtuc>5%M9h5{#tUeGg
zFqO_oBJ9x(VFi8>9Jz495d@kVC;&c+G#Gpep5+m(-DF7REPzNy>8_mdZ#Cc0b-WQv
zEX`<ieYbr^ESI*?jM!D@h{ttfZVpj2SPkbA(Ho!#v<c2eg=u+&o-ZiF<zd$rZDg>l
zx^TD`RTgj7K0y!RmmabUui|nf{}(<eU?7Mh33~gRdl?jI{{e#tRk^BRKODdA_`IRN
zGK>m8k7PFv5%e<3?k*MH4U7dgE-=<#y<<dCbAPF|K^hD~Wl$6cX%d#>rwXC_VxEkn
zx2JK0`w6&#8IohWmqz1gNobFM1mo?Dm`?L_{|vb@2!ds=_yZv*^r_wKZByf9je%Uo
zNa0F_03D5udN7)=%ihu;jZMNBm)2zCAWg$ZzHNXBAP}joPqj%z>%g<&1*^A{xYKIu
zyeD)Jgr@WMR2KG}v)by2#$uVh;R6&DyLSDai-zViQTlxv<aMW(7pn*F)3+IeeEr7x
z+y?(@^7P5`ZMpgpj!M4EYzp;5H<zGWIGV|gg%lFjUr}kA@6XLEX3h=xbynrv9-h3|
zqiy(&HBd$<+gYAkZDrpo_5Rs>S(j;4+O0c-N@L3(Pu;**78`j$w?NZwTJ_l%u=`Sc
zY)@x%Nc+p@>wXqz&m48x+y<Qi&{bRQx6Vr^<4tw#MB}v~*0tu(&LNP?l{b-fVY#}W
z?4y&qy@xDrKxuy4nO0kyZz5v(e8DZtGzC)0S#7PxsC&b}xBhbZ>`lTUMp{)B|BV|h
z`vcaViYeVMIUHR1>$KJvzlBoSXoRfRA3KNdU5LeX@duiwt+-Kt{PAy1=lV8dT0Q&^
zx0d$S&+Rro1gbJ-a7w8^bPrW(C%|PuHhb|~mU9nwNjW*5)Dqvl3e?3J5o$>M5@q$-
zBqlHYas9Xd5d$;O=UE44X`2Ly+}|O}xfSeYwY3?JvkU3{j}!mz-W-v-DTFK$A-DJ+
z`?94kV`^<#6EO#18O12e{WLws=wa&|2=~zD0aXL1<~z5`+l&2fs~+8h{s3p6J?QWr
z1{D0qp0m~PYrE4-zUzz7d<SVauWbGp{oBUG`iFN=th9&xGa80`oY}$Cq}8rp_3zJo
z)Ih^yaHoJkj<r2%to}A5ebcS9&%37#wbe1Bh%D|xg}?I!4#XiqT5LA~=@&=>aHJk<
z!(F%uXwXG!^|!(^sF$s5@v>=Qmg??Gcb}IdmqOjuY=^IG990~xwm!<QYK)ABUyx6o
zw`j?tI~ndrmX$Y9waMoW+eq7&Ri__SHCkF8cP>_dIud&H#8ShY_nhnd78}XPRpx)M
zq0V>+F!)=(j&APXr7md`c8-gV!5t=<mR<!zA%G!q@@h(;L3{$|c^333t30!H3?+YN
z--E+N1_KX592R1_R`QkS00=4UOm4+PELJ+XG|(n-hP(lqLe4}xcNhr^ivV1W5xwj?
zfHckzJxpw!o+DWbvXmfDoY@hwq_=~YA9;6rI^pnh4*E;-NkA8jw?<K3IV%E2f|0Ie
zyQechORTUZqGYf@Mu{wv<%HV9P!KxRV7wd;@x`(j-IepGV75wVsb#Dq@@@El)>Eb!
zZC2@58*T;vCf|Nd@@}_mI>sMryaJ4SvJRaD<>)L>H)73EQ3(npob1x-A)8twW2dZr
zwH<g+I0~<>!$@7sPO=Nmv`7MDVKhXGGZ&v2eYGa$GND2T)ZZ)Mu{4*XASqCXZQI?5
z#?cMzGx#|eqlmJ6uHKI6&me7QbK{;F)R<q%VG~3~Y99qAscb^o#^L1;TNG@nz~ug7
z`8{bIl_j9l!tv28$d4h1g_L%{;rS^mJbh7Nr#1|O5%Vw@+n`WyVQL~qf$WkbsV_Pd
zkiA7&Iw7N*rsN*`mJ}g{IEmSN;q3&*gHl;2=W@3seDaoE&7h3w(m9+2Iv#78Oj2fl
zhVa?z4VPZFeo$e0t-p&Q#IpZM*pPH0$LlU7hI<e|J@CaUkvY`v&99{xp2yHR<%GJe
zDapW((oY3PR^%688lIU(1ZW?*uo46w-JeGao2opntzixCIR%Lfzm<n`b8-tji7$^Z
zqmt<1(~-A8>2C&nynK-Q5Lk@i`kGQu9d@+5IN?O9L4`|qo*w`w^~5mcaA^81ia^$J
zJk9~{0$l(iiI5??H^lB^T5feYRSXzp__BE+LNB8rEk6^X(-*5I(C4$ARmBImq-pIU
z;ti=ZE7}bMujTxAsjXpGVcDl_q4?4sX#XE%@2}@$Jhpu9UIP<;7%gS*Y830?V=e{_
zG?1_Jw>AT0OQDyY{~F7<ka8$}_TDezd-Ml+(Q0(LF=zTj<ywA6f6h*aP!K51)-^Xq
zd>h9=2&=Z(IC+0*8~@ak%Yrq=h9kyoI2hKOw`7?+{t-^bpO#QW_IQ9X4m9QZrcuQu
znl=H!(}5tt4H^ber9f$!*JT>2U$4r{{)ikE(<yj-Cc}3aTvfQ{Q<+V=-3a&1-CTy$
zLP$~V%zLHM4U>H!fas+I_STocj_Z)pb*}$p$JQ%-{o=-EIJ(3tm<IV5e}m-7M$q<8
z#DiSlkEY!D5u2_Rq=6J|jp$cg7$zX=*MvHHLmqhejeE3jm0scW{q}_iN0-r?Xi}%q
zVvg(!TCB@n2U?-Lv1+!aINW2J<x?!84h3PKcqX$Gb3e=kJypxs)#RzGtaaNL8jslD
zy$k_<12o-0+B&|ga4+6#?b(Ww+0Z88mdIwNgg{|H&a?Udz|w3LnjVMEUw}&U=!ZF4
zbSO3Y&Jp4$WC*Oh{4bX?x0e~~2Y$?QpRi*-19Faa#>v809+3AC(2gFkyeg>n0()s%
z@Zn_sUoUa?z}?M!qqD~*e(4hP*L{1ExpGEM`>q^I^+tPcgK$yp%A=hr`c6J>FqAOl
z)*I)!IIE^FKQ5>;(CUvqzkhyt`K2sa^0mwM|NBCVYV`i+ts^4i`~H}Vl1^T(GPXxq
zZFOQf_S2xap)Vk%arkTW_f%86@3(2JcnE%+OrQ7=ynlkO`SwTfK@2VO7Q+8ZM!)^X
z+?M>UIeqxRM&kmpK`n|L)Ns1+_P~oc9eJAYY#;Xo+|so9=@;1kN0+>P?wSD75D0Vj
zrpd2`rT*2{s*dCIB;^QAX>_7I7)JVoiBYe%=IU6j^C27OR9mnwp3hL>!YQ-AswJ^;
zcQ+oJgvq$IQSA!*X44MRdv{znbh{^H_uu);#1NdOvuKY7SsR~YMdV$t4Hj-~K4xpn
zZiE2!vK@t*=X*`|v$i6II!CjOYHJKpN1QAJ%q4~W93tAt=+rNY;|1C*3*Easrk}T^
ztQc!8V-Hf&(Qva@;yV4(V4k@<V%fM}5rV|KY(K}3T+d6P&hv)<{iR#-PVunKADShh
z3jA@Q4T2?m<3h$J;p{Wbp%ci>)j=t36-GA~`$zLBl#kh4#|N$_pJ%9-Q?}jyWIgpP
z!mE22XO7CPcYw{-UMZ2SOa?98%sOoRI30k6G2j&h<XD8_kVokl$Y>a%;eVM;A<%i`
z+a-}l@dkqX1TEJV;CmxV?-`H9^I6kKUf;N69@6#`2b|JIH5l&#sNUeHfOLZ0T}%BO
zEhxWO>Ma%ElG;;lW1ggO0>mB+mG(l0JmxZHXghRIK-eyDOMe#15m$;85=Oq*(Til9
z(t_A}+3<6b=%2BffkHO&>s|E0UZ9X<_Hx?Nl*2g$I<GYMkZ?TXOckG32SFc5f8d<H
zSm4G(W^Fv0gv1P25cxNVKbGmN*7BjPkT6BRAFvF8DBi`4D&Z@J!0SaYd9`^ZG62p<
z?SJzyP<pQcL&Jj@VG>IaF>`@m^y@Ps+K7+icbm_>wK@wRQ%e*Dh;);68#DJ)yiOG8
zx4}r>B-mwY0A3(WW$F3ZsNY0>ohs|amq*wIH59w6`NUUM%XP2>eoDkq>N(p1$J$ZU
z^4$)Cr&F*GpHg_2=DNxU(1yYwo?;p68C@cLdreH9aqV4}`nAxS9!;^L-_}MmUyT8E
zpU7VJgx4ZnXGaUqiUm+u;drb@CPI>p{Cn`BQQxztPUlYC^ksA>aJ>`*{eGOIVmm3l
zeKF3p&d!f6L#`IVx#4|2q0c_Z8o37nZn`3l=p_M#2>Dce=M!A_lnNKa;v=l^baG(F
zH#CidVuK-oN$LSC*TXE6ZI)E8khPZxJCUVK3V6xY;Pi|<)E;WZLm<r^qIdY!voJ$k
zyMV1`M(?b^Ci#d^1mw~ajE8MM-A}m^mcn^g1hVgXT#+Fi+;7?mC!9e5tqf6|&<kN8
z(6`r{8wR1dZs5~MXkok%*W#vVHM|xiIYDZ6)v33eg;#?6UkC<t{0V$C+;kA>JUF@|
zf1Ta=%V^&JXNWihjgDiY==>tSKC|{H)f!ORTK+6w?rj8pHVs=o1)(o}cpbGhjN4yl
z8JcZkg3oV60kRc0_qz|PXB`G(HamWj7P|3IOHW6{Ncj9%cHv+)W1l~SpJ(BNLTfJH
zSmYX5xsslWTdwlFR;UY+)$Hj^+SiQgP>lyxTXmvETQ=@mWj`O0t1Ilza4f6rQ0DO-
z0;BeO_S6L~Lv5{VQ(pw-SH9jX7}ux`2Us-KkNwXEd*(ToImNTF1b=K#F~+jza$M7#
z<Km<7Zv{Ja_(hs>fymEd#2u7RXE`d(@`8N6+F?Ms=M}u>2ptFo^7=P729fgj)*F2t
zLoKbul|TCGVq6QBAFN&!iTHoq;hW^BG_#z@3_?L_u=%WgFo=rIp+2mms>8sOyA#ix
zmrHGJ>S9=_M}nuWa@P6VkyZPxix!&AH+pk_`1f{T>hw*lS%Y!>=QHm&ZbG4c8`ECT
z@)lp4C`MNQWiW@Jiz6>ZAn$L^E@soYz5Z<|56|NLiH|gGVP>UZ01-rEAo%eG*ZM4V
z7PU2vn?R4{i-dygDk#U#{+Dx$UEcp6YwrVH*>%_V?sM+ZojbBTb7w5uvNN7+X=F!n
zOmc}G-o%(>OO|8BOp0tAVzNxQc8zh9bafyBCcKbr$+9D8AR=|?B+Y}HVCZ0ybQaI_
z8A{>Aaj4rh@P-tMoA+2tX61RAhGeM?X-yjF`+R@<oGWQ8-K&KDq<i+i-`>C9{_VfN
zz4zJY#bD)xHz#g`yW=QRGE&&cT>R`yy}Rxd2RF%m_AuXiIsT3Pwq}tXcz>QWd7Zg^
zgmP)xjwF%Vh+je<3^TB)-Bz(Ux84X+6OHUSCO*8|x}uj}P3Q!?95F4}`^yKuG}`{r
z^H-M+mLr3Gm=zgm+Q+}{WgQI6G+PsY=~`v)K+He*`jksWx%V=ccY4eTJ^jZQUqMYd
zusGLVdl)MJaM=|{dc}kUqS>lrG0Fv^Mypyx=Kba9?mx~LzX9{VcH=^@g$}*}ntzt1
ziSuttb9FEWKnSgg-*z92AIl0Gj=kZAs%*DL>}+-HZjZ35R^#&JFHE*(it0wCQ~0c1
zwvvbcf#}aU&-Zqh*lpz|^>reIx2A<Lt+9pdG<SlOQd>{aJ)=?X4a!DLh#MHFiSR&I
zj!`OwqwY+84n3BDVEW_f%)9j~UGBcjuL4zJmxD6l{vx{tzJ@_`{ypxV?Cu9qXILwf
zq6u`YFQ#8Ebe-GA)GBWUAByeu1|#}+=!ES|s8E-|9(UUbjh)6_KFHS`PLTmVRvg_e
zb9}xx&x`K2d57A{2G|e?ZY^Z5q*najwEj(8ziHiK+k&vgcPDF*Cr#4AkZ+VFr=V!V
zxkt>I7ObNyy=%JV*s*#*paw@E4RX=!JVI^R-Bb)s8(Hx|RgF#3#zDlupsQ(zHy-j-
zU8C!PSr8>-K-}I7EfONW*DjDYUN3@(ei~<qpJxqs(nClb#6-pV0Ehjgs(E{jfP(px
z&9p^8sDYnvMV?NwF(3y2embD2RbIV-CFdl+;_L;Y@)`DmscYKz3`Ty;?Ps16mX(Jl
zY~R4lDI&!tl?_p>v?*VOIbXUqT_6^hc@s0<ERHl&zHD$%@a|B!Q18SQs>%<Tl=y@_
zJ8~V81#*t!N>H%YpomqLkX;SUV8KG6qu|jc?urCj3soUILP)9-Gs#pYy?qI-OG=Po
zq21jqAI&i4ae6rfQd@&8)<Fu>BqATjJc;>{@rT39CxMn_JrTFmfGT7MW76Hxh=#mF
zVCCg2b9=Sk9lzpP2wPItwr7Oj$*dVn46I&96HKQICXI@4e#)bpCPyO-_bTmZKJpy^
zi!X79mdlia^C?CUen|V4e0G5{j`H{o?VkXxF8rlcO*t=wy-@vqi&V*_^YYxA%y}x~
znoBE@F&2Q;)usfqSyTjk=~Vc&0uNJ$FcYX+-s1|MUfaZnrHj$AxDi?8XAx!J9XwlB
z*`f(Q)>uk$8~Dmqo7)0+bu1EMZLsQD4N+O6P6s(kCPdb@<S^(~W->AtlSLWb1Efi{
z5Z}1j(9mLR?S92%KL-5(f{jk(n(+!(6jxTQFloyPHq)p)b}>wNb(m5j)6z?AwvY!b
zN^&WkB_=rXGk|Q%%T`nBHyeCEsDM@k8%Mu^dRlSEeO^8TVWy=$VE60PE06iV40yMd
zFF!h)om7d=xwpahr$_QETt^A;l2L2pBFoZwCI=<6r9ATW$f&9ixsu7Zp18ay<40hv
z&i5ep!oMc^1~QDdf_76vE&nlT-9XXxSk~$`xia~tqBYun89qScYm_RQt*=(ws{*=7
zN^q(ShBn|aQ#^fZ;JcGZ+p}(VMvTTamp?e&>WvlN%|hrgmD?00yH1&#+IlF@APa7r
zk$r>UsD0^rW2XH3G|Qv@j+RmjzeI|wS{1*Cxu5RuomS1+189crI3(N=PkmU#rUX=j
z0zZ?#%waI9WTdCW^43tjWU8(vXp3&~u1|XRpZ?+?ub;dxZ~w@nH@C<bM81)?GSpUo
zHM^YFS+Pmhdp=yA_DYA5RJh-Fw0*^)7iL4X$*UgL=_cVrxBg%VXTQ>Ndbf2ABE6Ge
zho;Eh{VZehI-SRpN1}So5c%0xEIpyl9<mI8$DbKl{dUed&t1`F593a2>B}o!y3yMw
zxyI@Wj<>w09o))s&$-nHSt6#K&n!R&vTe>)BB|MEHwmx&R-zc6-R~CvfWm%2sr}^Z
zXI<whmqopU`p(xcJMFgG&@_N48h7r#{UZpHn}lP(1XYfZkBW(T*hAed@h+KUF%&==
zF*R|$;iUt5Vn|EVF<v&ul_mI9fW7UBu=k;)&dX=@@C(kTd#7IK7EQGyQrrXC5RZKu
z)q^#R6THHDFT1U*i}TL*QsJ&X;M)@q9FFTf=1UL>$NwhtOC`6HANcLWnN;3LTtB<c
zJOh*#pZ$y<9-31KYPa<>y@#3n{FqH~i4*L)sg1v7-S5Fid>p?9L4M*VgO)qE`W&|2
z=@Z!*wo=`73;SJo8r4S|#8fR8Fa7{yMAy6ZUt!w(5(=et(z%6rEy@uJ_1c?ibzv}j
z`NV&r<NC!VD?uv*@OKbo*dL|_r?fTnC=O~|TCc-Yy)5-=Sqdl>aDc9|kd{`Uq{72K
z$kKU^qPFUgu+&xtV2=2%U=D%cp7=wku@#9@9E)z#O=Ar|kvn&qMp9ly&c5<cp>wvZ
z7Q{(<#F+KIYpzohiNu|P<tRQ5#dl1lrKcfeGuv&wd*6avf9rgO8+9^z#=X83E}kkN
zOC5HLS_{7(%d443b%dzA5yU4%VDWiyh?L+|tHoM*w&=bM5im1g;%t3oUYtgUefA3H
zZ`+}Gs>qe$-TcyVcQQjJ|4V_j9oVfG@`KVYG;eTTEHM>8e!uSmc3cchE%;wWu0a)+
zHw*~60u+JIG|~+Nlw$j2B_ctqB36nJFvs-rLqs-O32?G!@FrEK=YE!61k4qtoV2HE
z+{vOi)9iCF<nEtRbx4s>omZ7A<VebNf@Oin6n;2RTiaM`46|sq<V9QDs%z;(a|!F@
zbaMOJ+vlLd{2qbJ3EL;Z?G4Mt+#VAIEee&hz_3zrhwwW1&)^^6ZRI}9q7hSVRK{$g
zG>?TcjBXZ-<Fdt8wXPuNV7P&iG-kdRNq7^pw6eitEo$<cq|)#qN|h{G8HIqs8bWKe
zwWJ{&<9nN^6V{8K^fB(XE8R+~ROu8k3gceofFC|lJ!U(fhd0*<c+#EHe_#t%op5)S
z)RF-zWP-LQPJGnbF=t{(X51Ai$S~vK8ncS9lhI}|JY{#M&@Fy@NDJ&($7nUnRkPQL
zPq>%iUbQs>EDSx_+KTbp#i<{S22c(>`L5gO!sbq>f_H*MV%3ahh!LEix<cQE+UmmR
z6iMB0hu<=2K}2+Lxz#B3r6U(gi1y?Mr~yVbwmrebSoBQL3j4OLVt9TLB5I3)BcoZD
zIflqasERF$(4O^;am|>V_8g1T!DExS{RF%OEH#MjRP$<|-Asg05!nr+_J`AN1-3`?
zbrQCYX3W<<Hi*zMrYvpxhE3}(wj?XB&@M%$mY?L;HR87ItY*2W070}T604a*1eKpc
zB)#;IWp~gE1fm^#R7pDC8XD9mRjQ!CHl4q_Ey~9(%#x*on!1Z0ti4M3I4y_qfLY2>
zRdG(*;kZ*i1A&GQWmMM?;y^@plm>@y4?S0utvl)7;X5d#<d|9bFTU4&?qOOf?WRWu
zoYPShjuV&ctwxg$pTwbW93vN}+`65)mD;)&NZ0b7V=z0fZ&v<}#W}QgV8QNc(xGL|
zmbje~*{{PDM6Pf@^q`wqYr1heiTst!UE0-hrS9}tf2iN022l@<r_s&VZ)6_-&nY`{
z3B>sIM5Nt&6-hlzD~<14No0H9>GG&WF5AF}g)T5Isfb>urW2IMXpW~KZ<;MdIC9QC
z#mioq3n$uTF-?+F73u(k?PcDS^Fwx9xsc{cq_r0yOPb3U=O4IrVYDEZXwYH(WzPMJ
ztFrxzU&N!lmAc*I-r%ou{&4Ag$icg!*8bfT?*;}oLOtI+$=$3rFQrjBaxx5fcab%#
z=h*68`lZ!nodpKI`1~=3Nwk7Pc4+wnjHR!0C|k!+D_<GbPX9>TJ^TEtrlnhCcb&N;
z<Br&Zi)iCvy??nEs)rwcCTp$EzNy_>I6(zgF3DeUoTHK`ss4}9n^xbE^EIX46ImL@
zPp`To&y-ool}x;gf86Ko7Z{$~mr}CTE42?@@k-Q9&PYG7uA{A2GTcAMg$U(7<__1;
z9QLAiiHpvkArG!(>hHG7QxNq)*v`xHotNmj2T&QPS7&$A>rn0@_Rd|6f-9u>0M2{e
zJjx-*jxLRN9RHjB3qA3xz15_*Q7&3e&?UczPktRdG)iX3!{L@o|4kvawWUqfE@ao>
z{Nxud@}`sW-JQ_=_+e%xtcV<XjtL3ca_cuYoKM@HP^~}BLvu|X>z;<DyPleL?6#7H
z|4J^6&EWnk-%n^i_wsgmDchqb?x8vG$)&VHlXDRLlW*sqXAZfice9_Tqa<FlCR?7n
z$>r~+wRS&yIiEm3GUI06*O(4Zunu*{TR8~+riweGwd<p&PI%juObPWx!|lhGc1>fK
zfOGiMs|7L;{&XsiTfb8sd*QVSCPMf6kgX@R)lk<=wOh}k`bZkyLQJo$?m}R@H)K#f
z+o-LUmNnPU&4sL_au5*h(t}7P%C2{w-rnWCpYuNHk3<1Qns$$8f>2v_Hy88xzq`!c
z-Pm7*UoeRoRmvpyujOWiOB?OQvw;f>!y_oNsN~cq8XUjuejEs7%#F8jZiUm?JiDz_
zN@@5iohZv!u$-TB?6zh(VMD>Bp8es(Rz$x!U~l#QJJ_SK!o%yOqFH!cjU>0N^0WzN
zPT2%Ufa_3@#Y82`U}%LZd>PZ?L{=Q2Pz2;EvWJa{afZ5ie7&$3_fjn8Bn(8jze$Li
z^EO+=Q$qR~?O%3LCrYQ3LCp<UF@v(C*;~qxf&gEc$z{*AwuvA{xdOkKlM25Cdy)qo
zNJ<2nHS8&3jl7$g8%IewY4S;-4v5dQ{-`~h?mhH}zR~q~`nAuc%?{c%($RV69uqk~
z+YCN*l!zzh5a?wb{)?GUoOfw1O=2|pDh??`tZWsr=iOCuv|fZ8OU9lN&~ieNT;^4i
zc=Q2ghQXB%Jxsf;PqHlJifH)rRk<;1RoW9CqKJWI5=u~$#DH&%Vs(qmaT%oRhZlIm
z+G5WwBa*z(0!<Bj;7cc-nbPn}0;!{#>Gf11s!-H-IS0cUI6)}4@blhf!FXU`@#I9=
zDDc3}R0#}(n-*sdGqVY5SzLz5U`!hlF(wm=v|?%C-W4F5MN2*RN*%7H#6uQqj68}W
zQ~{7!#eb1WB`uf<Nz1#Qnp{CYdB)wN9Oty~?L7%eyck}NR}n~9F~lUt-DQ})@G(`W
z%ypfc#dnooPaLTiO(K=U!zd>%qe2Lf{HOs~V9Z5%-GRe$a)8u@G7PkS%skaOFU*X%
zB3FSD@UoK_{(26BcP1S;2yfIIGZt-xlxN^5AV=hiR6&UB+DLv#6)?V4{6!R5`pgkX
z&Ny5{!3#0<4y2xwy2OHNzzK_)=xVYaB6%Jaro8opHG-uDy^yU)oZ=%dVh%R}$6z>2
z7C^i&v@_p$gtWR!0P2%)O~5z~h-COsQ57VzUJaH@NSzK22Z^UiFk~x~n5XQs_Dind
zLnz!mXJ2oP*!KW%rdT4^6}lWX9Ko_K2h$ARE8bGz^4t;VK#vnpW+BPwWQC>D=6aVT
zDyhm<L*zS$Ft0z>FV|dbMEMknta#ZAQJu!2S4Bo5no?gg!ij9C$*RmM!ig-|6%ny)
zaSyOE+!h~6!j{JFkFuaxd+fnbE?u?uiy~#on{u?vsOoYZ%=DB6`B()~K?k)S1<#lx
zQ2hKB#aW~8D-?Y1!XvQg??$64D+Gly6xP8|OHv71OHv8`9e|`Nh;^ZKD-YEiFMAyj
z<jDDHwifxNiY30~Q}QDpRU|of2T5zE)bZ@6P?PmSl|vBp5D$WAPaa;D+E@0SA!J?&
zZ9^2fZ4kD(`n8lu`nr>kkTqs}#f;E}6_l=0>qMbo8}pTf@Eiu27sj?+%H!`0DMiag
zRAP))JiXXey|!*o%lqs=DL6z6WZyzAp$1tPseDKuftGVuD3pVcqyZ8FF--z_C_p4;
z1EvLFEN`*Ps#ct!Vp5K%REB`B!|A1zIl!{xI@qFI3JClJDF}<_r#Xg^oyF{jV7GWy
zBvW#21-}QDHu0BhYp5-0Sg1vk_)=L61!YIH8PIZC{~>p6z~$H-irh@$=IMC63rnOt
zTD0g@LLR3Gwu6$lVOb=<Q3<4BiL~^({ZJ4JukO2<BI*Qp;XZ1jqX(payjlSWD@ftH
zmcbh$nGtz}ob{wRSeKZAa)^XR=~#ow6~{oJV+j(97{<&(g*}dkmp$WWZ<iLl-o?&+
z!MI(x2Us$U3NHA0Su&2JO7p>yJGD$XqC#@iHZK~p{A7B5!vW5`urhv%75J$V$-N!a
zG42t%;EheVH-@k!Lf27{kXuA4=zhU5QA4+Qw-83$*&+|JNj?xyIbvVWb+Ip!&7lCI
z*jNAE&Xo+!gq=8lb(a(*Gy+)i5i|)Aku~zTqSn+0;srUzi`YV(LqRAU&v$9Ss2C9Q
zheU*$>EWrvX&dn5gCZNSd4AX`5l3@vd9-3gflwZleZcFXdM>V07iX3Mk5HifhZ@1s
zs`6I*eT!x!USgx4K=BD#Lvj~n%UAU9F&hQG38C`bsful4ZQ8D>tjL72BDQ0Kk^I`s
zS%6B8ybom5;4W4O2`yk4%ZpN3_Oe#0F+#Bf(GrC+J8{VeioT#w%G!yk>C!^Yh<l1s
zUn#Z(%en-L?q}*lFPlkrA2S#F-UBV_f2c)ERvmW5Y`Hh?8n#OS=l$%n(8l$@L|%VN
zFIUoB`2ym!`$E>sPkxtAaXS}hUDoY_i*Lc>cX&1Lbk=g~tjhCE#NaN>cZ#(28AsiJ
zcl)!>B}LEOz$YuuIi%^^>qi-!PoaLiec$LK?bo{%h_F!nDr&yI_qZ<c>J1A)c~MNu
zb$U6?U6s+ehC}P!uj1(UO|;1uu3BKhGbl=2ogyduvKjAx+POFD$j1gr>TVnN8<4zr
zDF@Z(+&(&+`NOT0y>rD(>TY_VaO_35wx&}*&t#LX{p5V^ewf79I7cqFhrrX<`~Qo<
zZh8kak@NB=nf$Ij_Q6f~nF)&Z0nUPrKbNK_tk<`XeBXQw>z6Zhy)+BQpFfnB_uQfu
z#ftY|GMuoJ5vntTY=5v29v>W?kNdyj3QJ8X4uA)aJW!-Jr@r(ym$#pb)c4qHT+Hc*
z_qr~xcsYObjjI!O&*u{BYH1^fQF!TKnzZRc7(Q}=cJv%Y{9~6BeE_*S=)9-&l~(r~
z)Y*GpY5tv_o42Ec#d{Fo>obnL*!~d}XzaCl*1a8#9Mqz9yQ8Pi;|OJLWTT>w`4!js
z>@gbJ!3^fTE1y9-$!WpoS>%roXF*s)p<LUyn%_x#^`N3TZ-P<78RhktClJ(LpkEoZ
z^}?=*Cz6UQ9(ezXo8GYE@^97`EN)|~Wd$NZhfjI&&r#|$W;=j~k0Pzw*3MqY9=K`M
z?yzmE29cJ?{sJjvKleE8^C4zS1OyS`eLCy?iyOb36_0?Ta_LTrh;k2#`_Iq+x|~Cy
zecuzKE%)G!46uKkg|foe>BrETa`}NHF24G)HuVOd(y<Ehqip52pW=+C$d38_Y5z!)
z64{^xn&7|sQ{dB|gyP%zk_|F*$KIH^)6;0?-yt4{L%8o;-pYSte;QTdt`SZ){jOm<
z2b7!*U{}N{!@35cw^Bh)k%1=;((h<fg09j8sjZDMe7yCM-6nG=eAGw!l8Zcle&_VJ
z`4+vOVpdJ+bn{W2=>w7yDP-#(rJ{YU8P)$skuB(mJ%}su-bo{(j(8Lg8iYc`*`ri1
zFXv$B#ZP8bnu{l0e8+x7D2SJl>Bl3-7H@D(HxVCWIJC{77+iK{lCjoL8(FP}1qoyV
z&Qkwx3EamH&o6Mn;rhj6F4Ae_8{nVG$<H06{==>?tRau!9=pcnH#Pi=@apI!m|$<M
zwZ=w%SVP!!cg!9sSP3xiY=*$D9An7HX&G$+8AGkbZ6H3aO(=LUc;2XtRx*>Dh+6UV
zv$(TEN?RPooOvn`>io%19tr4FU2twLAkiVfx|YgA4AQWazDqSQv=>!LAieqt<pK!&
znoykJeffypAb3a@(}}M>7pF}+bf0|?$^wxAQHin)fzRYroy&GYs<Ty_sW$I~xr<-y
zGoafJN@cAXa(z%Ve3A)a#*rAs^r#;NsB6-6jQN#0aj!2@z+BtpCBy-cmuRLo%lQuC
z%%p@3|4E)>ysg*iIL7X*z0#kijx@TnH%jUO6cOq26PSX|WM??Q-U`v$3#~@bvLtR-
zMq@b626aIIX6BuD29ak^<u<}^f*){=1(HvTnEdqg$V^IM8E`0R0F+LuD9OFsbF32X
zZsFgOzxb<oR(!8V7c*=0S`jVgaOpe+80C+l!`?LnSys&z-DH<gMz3M8=H3ZP(V!A=
zQZE;2NpuWdq3fonTqDf2*d&)YYnkNvBO=PHnpTs##El9r`Ry;tL*u>@q&#;6Przb_
z8A(SN6`!T-46ZrXfqS!;)xIN+>0(Kr5)~x$AZxyrR<6$kDll_%e3b{oQ1GEgmQ^)k
z7|he_EQ3^TN8Czhd&nMLLEM<cwx#VO;^Svx?|Ce$0BX$@^gAEV3~JsyQ@(119n7gH
zPb)N^8lK#O#Ka6XO$I$?P|o(V@x9n~cg^><qa$`g-S_G-915WXF?@#-6|Gr3WNN4e
zCIZW6hXb~tnb~WFq+s0bRwZI@Zh55;Cx3Z{l84d2jLY&Nk0GnZaNN6tpQqhWySJ&o
z$hab*h$b!@^mk9@f)KuC!5pB~Yof2w3<TZ|m-uGp%J0JYmDy!Jnb;E7Oq7nLEb1CP
zRmI5HHez#Kvbmp}83Wh{!u@&HDv!Blya7>c2sLEA3DW%>h5p3DxZy|oV;(uE=2uva
zeq5|wITLwO^%9@KZFpMXO)+KLf(AUM|B>_YO9*Qp^VjYh66QI_0yryLz8ncz7TxH`
z==5pVzAvzePhm1Mzw^vN;&ii|z6c%ms(=jYiv1x%PWkz)d@#E3SmDOYSFohO$R)M4
z{Ro@F^gF|#czJu@%5}ZzZFs4QB#{#Uo$#M*nAnE3vqRi*NQ`mj^>D%MDrnGw6b|S+
z5$k`2O1|&SGw%4AtQCLrGCCRB(Mjf=US;=Tok+w-)Bfl_d+ijO!7TaN14xBfSl<_m
z54?WKUBY2L_=vA~Rm*?!$75Vy5I>whl>Yccxz9bla&2^vpP$U*mtL7(gO@_RLM6~w
zEM56e_f@0(V9M>XdyxFRCi|gogVy-(_y{K1LGkr5Qp5*d6S@2>n`%F^oVnG}CV5+D
zXnbo{I8G$;zEti)51Rk+2gv>lnTw+K&f_a?{j&({C9k6+e?P)pr^4-f>EZTSK8pJD
zE6l@$HU!$ASw+&*W2^uOljQmUL94P+KGV`T_5zej&|-p}7?d&wn3neU-XHB#67H)v
z1~>7xn2w8z$P-_gvWaiIev!`c+MFwY3z13FzuM9m{AiDVHILV9WNYq6K17iwwKWoF
zL5lCmFC4S`Vk{uw8&Vm=+5dN$|5vcgVNY1*N|{-8apf~_*~1BI5W8(k^FYV@&Z;Zo
zotIi=GPU*6M&Um3ot$`BrL&P3$}7q0t3O}3({IXSbi^yTL)yqrzI1j|ZI#x3{@H)L
zP~J2)<5u1Sje?T=>+eBry&}uP9|rAA41v|2d*?Z{<sW5Tn2NR-!QVMj`;~PkF(gR~
zzMp5QUQIe6unuSOF2qN`cuy0Ax40}jmjd;@Un;ObooCz^=S^)5$6QxSdqE*XV5&UO
zI-+iVd|CV-wXxbdn38AXb0l9KdsH^oxTKmsnwmPgxD=H1=ZPDehJq_U%|q-DgZP!D
z!aX`iT1xiLNfVxpS3m2{jGVtU7LzghB!-a%D)1$4ro4i8I%4M8;fGaNc0I}%mIF^p
zkw#6f!$ru<t)J-9s`oE7|CTY?GqRz!`dvzhXnlyedu*PQj+gY`gZ2HeEtZH>)JyIe
zX2D!B*;Y~F3>GCZZ`~|{P(aiJW430MzPARn8wz91JzRV2ZhG?S4o^5XOgJ!2Wr$mF
zy?30ZW=uEoQd<-79)tK<E~a=ASD?Z%yvB;z20loLt1a#%R=c#x64;h_5Ie=~%mZ)H
z23$P}JWO^HorrL91cLq?+d(pcyBci#;QT4<qLa~i#GKF>B3DrHT03_zvtXV(s;yhm
zmH#c2w+8KGSLQkvC0OtT2QW(72rPz3E=WqbK?;^=!@IlXax4r-?}BLQjucTPiaiHC
z$g#HFO6oaLnngq@7O1_I{Co-^DN}^;0VdIw9cpW;Wf<+q!^)M|trZ-DAyidS+q?#q
zxFM2iM;8+sl$}-9C?sDPR|%miWABt@rd$G_sz#b7#yV*W+WUjpsI5T}swsIDce_iT
z)}vLS!wd?G-PS9*$h!uQs8S)4nY?s<MZz{%1D$_BIYUP6B{?9-%+W>J2Lppom*g!C
zQlA>B(Alq@ycgN#2$w^j&ezH4gO8z?v9}M3$+HbgUj)8jx3$LI)eLPfLJ_q!#Eg=$
zLbQrBuZ$n}u2{3!rCxDLvY6*?8)uAmQhoB4V?)DgtwAVcM=pB23TAP)B96K?)d4%0
zo_>x|b)Fz~cr{d7Z|zJb+Y);PI8LxdHk6pH5<~>Sk3zG|B|O4psq0cOR}~a1b9W<Q
zT;qk|?S?zqB$&wgP!<WRtW9pCNbss;m!DOz6_6r9I+9G-!n(Y70N#(KhYT<si8Nt#
z_O1%AVA;@PSJI|&R{m~(*rK8f<HhaqWkKEsRQwqxe5xFpCq-(n=ccPFbbxUJ!ckf9
zTadQellN%jz3#Rx7`s{%Np6PgmA_d;DP!hykd@H8=e(vZ?eqV}yZ9Amx!q<^wq3qX
z--yV|PPgf9(R*Y0`jTt9SG5*xMzJfg&4B3s`~HA49!6~)mv(9begC9$f9mc%RNm}b
z;rH^$-ooK&W=m}8BF+VlOf0<B27SlNX~h1B(g4mM$Ri95gS<2SFa1RPQsiopW6t%g
zS{6(TGk5+WcP1OpG?Y+d9-A&^AnVKjgP`dwayKezhc+a2eag|oCrul-=7?_nP_PfN
zxu2kD-aRKghKNthuSspadKg=b^UE_~y6t<@JD^H1UjEA91UF6&g#d=Ch+P=@flH%w
zz=&JA&iKri-MzP;ZnW~oYxpwpc{uG{9-I-`m~=Vwin!Eamy@q;^t64aNZIH&_E0qg
zEME1%QVWw!-q#<hv}G5szSylD`3LPVx6Z3tw~mLl-aK0=Ulv8Aee$m^Z!LZNm!h$}
zuzs@}MYp&E5xR1gN;eeHzRE6Dr1=`A`D4_IU$bIuwf|4D@}+}qci9bX0>Ehh89wE{
zthnz{-hccsJ?lLOylZu58UKiff{)rdVxo%ozt9OY8!VFR8<}^#W!9D7$V1kg2<=0E
z<npzJ&6oRkXYfdz`pmocxnlnCFtt_s<4~Z(sLF{_K?gKtj9l?{VaN~M6q9oJ7q46%
zyZc!$CDl)+cNB>y)lT2TU?-axFSy00X8##O%WL;=RSjf&6vHw)U~jGQQopFZTp;rM
zdtzKKr>%VETGyk_wOIgYx1}8N;S8!4Qdbd5f7FJomGS!7pJ{tM2STL6b<e6)^nK9M
z<x<YaiGteNE`R;)F1z+<?tbI<>7S%V-`A$lf8!<dQd{|gtH_>&>{lB5<6nG_MRGy(
z@(#!Ao`tiEUr!b9Y1Z&EcggHgj~41sTXpN-5P-AU`<`Nwj@oK{eB3?4L7Up{9=<K)
z6fXMPq^~ji<K;Bh`vKMwQ4TL#9;HbC4ZHmtWGj+CQ&LUC-EdxNt9(lLcmu^@%+2hf
zy?V-v0ufohts$~qo<Niem}U24{qtMtgkd9oCAhpxhNZR|XZWhOr)w0;f)`kn+5?R9
zDfLHS*!|GttLe<v$t8+2YHQE^XBQgdyw4mCP2;ECUu_GW>ChFh^rtR<ktyV&dy3q>
za5;?Pn_wPB4$iqzWhQv7T)4cw#<pTS4cZR}XH+WWosFpwia%%j;HCyrelY~|D(u-_
zl3KDSC}0f!6EL48M^1a8UNlO%a}^&$0CuS%K_hT<%T)np4}zaFJf2Z7tEw^vgJMFZ
z&0`FcK|J9H;wKx8F<E%Voc47lg%p*T@PpN*idK6s>*=1PR1tJ8wp23WBJgWNin`;X
z+$$n1+Ee^mK{DuNETzJupTq$~J%S#BNp}0!B0beS4PDKD*^QvK(%4rN+-3u82zZ;s
zEl6z@xt*cP>CS=Me8oJ#q)nQ1p@{N|{1!@b|7g?5T*j+XXb1Q@U(;Q}QJ}WslXzjq
z$cW4Rp;h7Iy&EL5K?=?U3Va!p3K8>4R$O4o>Yn4oh(Wx$eVr(aua|K02DAiy5wxNm
z)2;n?HiNOc5@ty!s7RUOl0t+!S4~B+E#;FSmto>V4>7|xZOluO!AG<^{EQzNUHo0c
z%S!t+>6Fe>xOkaw^%TNx5IA5r7UwaBfg~ap_72rNKGw0|*EVx9B#8vrJ0_RLHitd)
zEW;7NwR01{hIFJ+;zt|Ta~Rym1v;W+IuwGjxMR_0C*5?+T!<E+RNkOKiF*l>p50ba
zz5vu;Dv`awTF1?iR=eP6o+VYnGZCfuPC>d&LF0rurMT##%D4im1h|{-<lVzS6!B1d
zuELW6)~fXlTl{vhmXkB{2)9dcKXc`dxF)h4L$-SM6Om^Ob&!guo4N7cOywgpEby?>
zRJI~N1K~;r3{OdwjvmKgfGo38{*ve-rhfJuaRJq@oqL=jWMqxVWpr#ke0BmKSE860
z1gSK_IMnCph2+GlMbV<T-FdN4wDxo2W)5H9bR~wBOH|$xTngS!pu4)9KJ98egA<o3
zcH&Ox7x=*nG5G|MF|;*M3~qzw(l+Og4qy9nDQGV~UWC3I3hr}RJj^z%zW3$a2BRPc
zX<M2tjUK9w3$(k}Af4;oC)_%lmFuq~C-<lOYU+e`G`+<1)I)(o!tJ?uMF?o8UYNZf
zaP#hKXimTJ5{mV0_?%<2k{J%yz>xLFnHO<tt|L@U@cMZ!{KYnaSir829I_rIgx%KY
z?!Me*No{SD^`6_<=Vts(-IJVmBp0aB4L)LjZMiQpEzg4HaV+xlp-59(jkDA@i5iuD
zzZ*4_`>7fEjV%{Afs5MeI%~Y>(dSdhJHZq)8FrRtdehqqR=s|z_+GJ;OzY-7sI5X)
zL(qXu4he^T_kxxd|KWRzeExJ}#^t|99Ymj%KESmrE$6@fGH<BpL9Te{wQgG4Mttzv
zaC-l{q7oerAA6rGbO8w;s-WRKm(M#_mLo5nTm94>?#b|UzIrQXlZ#89i_#yNjG^_M
zJ-@UTfBBbMQ90w<l{QlXw0<1rAMNwQNzxw5d(m&3ubK2SXR=TvwKc!%e4fR>e(7O%
z<i9zp*F%ooUnH6pF2C=WE46ir<H*wJY_~OCP?IKDJ(^js>u%2CdzklXhwteKTMvJi
zZ?{ofIV22wLwWP@$yGLtQCq!bL?sBj{iiY+<(i&?-d;dxw%clID{KKOz#D#*Rxzb*
zSOW5~2j<)t%VR7q5q#q(_s3<+q^g57O062K5=r6@N?{l*t$fPOQW@5CNO*>{V53~7
zmgu^kaL=cf+zbIa2;QP<Sq{Cv_bATT0fjRvQeLaAsLz2>a5zY99p#X4xZ;n!iw6(R
zGqs7U-yiUJS?&)15jpwGM&{o6Q;hD)+jDeOr%zCTmN$0DMYh#=JCFCePJm#%k?fy-
zc51x5^U`+v;dlC^>R-YPU|}}P7SMWz7sPyC+;g@uxBp30*SZ8#nO>MBzTv2jbTGhC
zg8LyZwH0N|m{=!UXWqBa$?vCC67a9i{|%eNUr3cG#&@vCLD$ThAN^XliQ{_L*-s>O
zR)-_TK!EI(PwN;Pd9F8kPa;vf%7qm6=XcT|OZBox-C26*1X5d3H9b#IwyCWfsnsfE
zS14g``HQr{lNWbdOYdNoa7tZHSS~q{5a$cm`F}OuUW)+2o2TfAN$Dh?7(phP$Yzli
zYv-DSGD?9Ptp5lZIp}<TXXd6>zkuH<*JZNAYzwp{K4U5D!B9Bwo}rihB8xB;rXL(*
zVCZIzSc)L>3$BMJ-H(b>xy<IMnVvu>bGxuCr7I)BJvXVMm{6nywys;uRIc3(C~!&U
zY>+WZx^(M^#s-gxt7&zt`0EwA>B`ULQMN+V>YfRU$47i5SgXw44R3LKq(0F)n|6=q
zBj`#YU_fzIL`aw{0vt+8p>i0VoOv<vEesJQXt#;fn$B=h2Lgr?(VO<5Xkv|o219hk
zc~HBlTOW*T`((pVHp4yE)d)LqBg361ui{TLlvd16wim{tLIBo3%`B2(8*KI+wOE?}
z9v+g?2b;kimXMYt5<oTNDNNgsQreYn5s(hTqBpsb!>3pQ;@ZNW#~!E`I>S5^lxDaG
zN#~6av1iQAAmTZ=9xdUV$<DaQwP(m}f~2-)3*u{qI0$5ggshx}G4Jne__oinewZvs
zZ3|7<Rf&4bnSusGhpu%c?1mG!1ysV?=C|E3pO_2s-MSPqg8N>1($_D_yp!BJcr{Q-
zI5L(%JV!`PE33Zp9BLRMv3Plnk12z09xe;ALsl|WqiJQd7(qT#^7Ih#_iEL^@aQk(
zD_|y+EW18~VWr?mbj`dLESa=v6<Ci+#Ljaw1*4EZ+i^bCxv|I#I;q4s)KQbDWiaCW
z)C~MmV*oKPfca^&)M)0|>9G(kQhT@J@7Ex)7j{bFLO+Y4N8Az;WEV5A>Lr2gU~#N$
z<)3(&__*wS`f}_AqL3cYBiQm;DjJ5GNexUuzXMBTv>u(q*@rD~Q-sE9<+rPmk_dIU
zn5`I|l;0-vAm)%)&NUn*z|?-vVk=f2ePbcng0FpMDoZ6Jk{JSNos?1F0*JNGM7$tm
zug=IGqHu#AY%Z?mr{IcP`@98g@IFPCH-8k`2l0ExE*4$bmj(AKLQnMrcei*2oubZ^
zbO!O=o8nxM-0r8J`)#iF<eJkg`}9Z>jelj(Y{^|zo@ht+c@K-n$nzywHi)w)$O}%y
z?u#B|C7NEk!IHh1Rb6@7%}7|B)2m(W*UYutcVS`IV>FC;UV9~fXKuq%&z8E)R?rtQ
zxpNJEyVHEBl{K81SHq&<F)C^Inqc;Uk5Dal**&Y9n7Q*fR4Qy1rsdVDqHN;qWQ%Yl
z#K2D<G018O-*cdyNr74K9ax+tV5<E>h^QZhT8a^~y1k4e7O%_0$-f$z)5jW^_7@?;
zcPQ}jM1R}*%cA?h4@OIiSoy~fqL;sG$#uiNw&_jBKN(z9S}Q+J3*KPgU0T?Y_hq@%
zkM_U+UHH~}s6rVE6bgEZE~DVP^hhga-r{`tG1N?K?MJVz^0xL^E03RShQq~oxC|XH
zpZN#eK)Ns=-BZ~`@Tq%MiJ-3~#^(DJiDjDEmh0`mdBt__Y%nc`R{LwD0?KfpOIi{Z
z_pC-QOQwev4b-r;KXoW&a{d)?KMXtw^FIb#(oQKAYK;;LD`Mu{JKSNdGU)4$Mqz#7
zpWEnSSu&sgA>rfCk4BX-YeI=U_T9mQ#I|hP)-XQ%+pTfcpo?jM&+?wD)*b8$S=Evw
zKjmFeLLd02DnR0uNjLV2t1{M*mJR_3Z6F|@#4uPY71OgZPyC7V0kiQ5&IKzVTX^$+
zcjBYen@{{?t23d6m>VAU#fgt|5!J{c$E~d<kf6<G*I={x^t0Nu0p9S6;5v_G(aL4@
z-%Z;4zzYf)2y<{Igq&%v7>N8xdK03yb_BhvlR5CI5xA%8gX#FjOFoY(Z1wZnZH>1r
zd+SrB&l-Gs%W_@v*>G#xymaxuiJJtQw%X@H6S8^<R(d1dd^7ZWwS{BTQUQYnlzg2d
zKAt4xPF@9XH!-@c!<n?it(;Au*_L<@hM<@m2`9?lva}=tCc>0-zIbU0JrTYaYEOmM
zNarDZZbHlmq*xR$noL##36>h!pK%{rxld6?P3pI}V{(jluZiPuwsuIV4}y>t-9h0O
zgjq%|@Vn3{Hi0EiC!R8k3p-mT(ptB`ZHz!x?pwVj9u#_hsv-uyGKU!6N5nPFo~hEv
zUryb?EF^;4vuNEI8tghw!00Ab(>YN4z}YEgF(9B^_dR#BL<M*~1Vx@&nCu=NdLk0}
z@$v4UQ)QFbRm(#b^mUJpIjvk<MY8kcB0tx|-1MQLDMtn^R>Erg0CTc<HKAbu#<vs%
z=@#3b7Pn@DVx4pBbBr?#X-!GDP$hN^!!ntsiETIC=xz#iYX*1aCMbk88wtzOBYyiO
zZmuP5IfpDN47z=m6u;1QtBYBpE}A|tX*70wN=IP)B<pTZs%drn&M>xqTpaN`-^Dv6
znnfQe(EazhV4s>hGT|O11dX&Ayz@HYF6i$CHo}xT&DPWMWu9a?id+LvvO#`(f`Nid
zGbVi=cQ_dN70Zif*sfVH@2*==8fyyhL21FSm$?lLS3XvQ{kE{(9K_*2STL!FS!^@R
zy;x7M(zy*0byQDSO*AClaGx(;k*v;jvGj9S*1irA4g?QPvJm@7kV^omCgZ0ZQK^*F
zDkG2D+FH)MXRUyll50(6q+ya0ZqY0^8S!|8F4<ty-RedxYvrsM##t|>YGRouogJX%
zeC0bVu^l2;UhuAtMN`HORT6%cDdf50&D{D>uz}?TTbZ0go+KR;N<20%%Up8lX(OFE
z!D@G96Gz+N#hIfj>;e4BPDs!Rt+<tl<%SZ{+AjYBE*i573i>(5vK%d_dYFS$d{Z7-
z)ux^5!eGc?z{Zl@(EhLrh}Z9ivBf{i{$>|s=;oz*Mj;}t>~mRg&tE^!d<OT1cQfY?
zjCw)@L620B8I)S5VI7SUZS=+R7V0*Ll}qw@GW_cfSGqIKDZPX4XWXenQLl#<EU<_C
zKL`AQ_>NgaNiJKV*V19lGSilY6g1!|a@<NUjF7D#qP}Vi75HKD*X7I^Q1Ed}ZY#Pe
zKh%zwyH)#e#(Ea=b?r-(e1)u31wU%I@H@uAwVSNaqIpGeG4tw0^K#cP-p5-L?!f0v
zc&ZgIFXr6u_|A(ERT$kL<{`;G(?1sXBD_rxmCNeeT@f(5`AZ8_h@fnT%(2b<o|U3(
z>kEjlN8&G#t64V6AQHV=8gWAe*RT9m=x^UezO7N>IT%D1G96?P+`jK(CGa_m;C0Sc
zCrfA78*b*wyS+RA<g&FD|8qAm%7WBU-cWgo2;{${ozeZ$dN}Yo3=V~nr+RNl-KI3C
zY{`xm=cliCMcKI}oz<A+05tka%dMf|wx_>i%Dv{`p?JfuwSqem7Eq9GW-<p^<)O^S
z7+v4z9=RHU%!soOGNedtbt>2PuTCa?Y#3v#x@3@}cSN`I!d6;>z)wk??c{mHbSLhh
z=IsT9<%K9Ukxk%0k`ZSENfzj{?fBV)A6F^xZN`hNKUutl;0aXC@FpxlyRF~(b;hQ0
zU)&>2qHQOO2N3TWaqj!5L>|Yt8$a)Le71#;Zv2bCL7}5+MP>ECd)*<Sq|ZsxJOYm4
zfPA`(A8=Zsi-_Nq{K!}9#6(7-z#XhMwLjHfu&va&D<OORkyUs0S?}Uk3)dSz$qk$H
z`%GI_L}|;>fAt4Lf!aD3@yMTJwHUQEw{mIyhm>w0WH5x7+wpriv-%PfdaB8?$LZw5
zmkDxF9t>2uCKxvei;IS$?Y1IX!RY#pP`Mx5+EJ@9-hJV_wF6Z{-4k_{#9y>$w6rH!
zwC9kADtm&mnqlC|H(oxQ#k;8Na#+Ao*E8jCQCd1`t03!LRitb_aX>FzB^aJtmq+*M
zY~tEFhD@^94u_fG%CR`&UC;D><?Y-YSN(lEmJcxnKc(=XO+*yAz8-&0zHO!;A2QW6
zy0dRU2DjL$yO@{Lra*)~i^AR!cmsv20S(V@BE(HAw!Uj-oA)qBQW%1-@jA>!?^9OT
zH>{^}A=IIpW`WhaQatTJvYYWLMt6v#6b19i&=X;;Q33{@XRT4&5|jA`dk%hx7Ab9k
zL_Ls!O(>|CUT8T>I~G6(%y>%<*|Bps6JlpAG2OBr)I1wgHNSL@!OzszXk}{QLm%zD
z2hMiZhDI8MP&G|ZcsI~Rp;qE6T~&y$mhL7Pi?NotihIpGRhC82U1vKKP{J7aOtq;-
zIaZXZe@>fUF^k%XD_mDqIqh<|P@+GAmZT_CkXTIiU7ruJr)hzU4f4dMYlRtBW$E(s
z{F0L6VxDzP8r@WhY&X0a5{_lIuOKx%v4Bz!HGGv&)Yr@Q2AOYNY;mYDJI6@fWQXw9
zW|8fTTKN{q)M!(Kyja<8iNh_dm99&|TYMBIT;^JJY3xzJL`o$gvVq?};Rig>Rf2TG
zdZl~ukLcmdyF=5pf<s>6hwu_-2H#8-pD|_?EfVeLp^)-|#$BhU07=%4=2O*~GKfMd
zz}6i2fm@^+##PZQi%4Js#p?2F!aVjy{>P}Tn!QI!XfWjZj?f;#?<L0~nIwm0dZ(1P
zGBqiLxDAVgSc2H=r{c|H504sgMz~gJmiP^h`WUB4H*9UnxjMBILM_~!41-XadpA@u
zH=&<9X1SCH5LGA<i)pyNkAP3UN)Mq9Siv({%S^0lLqyJ*dgUJ{;v}*l5$C7Xvf4>P
zLfZ|vEU^me)|Tz4Th-Rptt@Rv+u~yOC-D6jMRAlTVw~f+U4o;P$nR`s(ftm0om9|s
zsCH~O@;kHya(WXn*1>x;kG7%?<qAs8i@y9BEX*OC$iA?YStjC-e>_de$`j$d8@Wh=
z1KuX#ZT1u982CWHO@P|k2dS-#<370`kGv0k6D#7~=3y6Eea_ZL;#*2JSM9d)A`Y8+
zEcnNVVex~|*F5eI_?`Vn(@u*8<DFwJ_{Xx~&Mmb@;s*%Yxu^)}Ly;S2ItslN0x^~U
zO||u!RAIIv?Py1Bb%7AmQ|eT0<LM`Su7E{*%Mr`z>3yEPRbBT72o;rP7M~*cuOlu~
zNbnt=31TA;O+={TdL{7%FRN{(UdNm>tRHiSMfUh78}1PTdIx^evD-SEP(C^5x^wvY
zinADnvch8+NWV2X`3+_RnfHnywe{&cZ%qQ^0w&i!`z))`H!vH1^x9&wBSn_&XWMOE
zcg&+3C%x-Lm!Y;2>3xj+_mAZ6x7c|41LjNJ(@d`ZpZ_hikN+w(%6<02r|9es?Ukii
zzKXOsN$Z7{87`b)sxF-+-6+5559&D-ChW70UU-$77_i#bul7S<&NgiP?3I(I&q{wh
zR7p~6=BYZkFTGCX;>smFOk^^LK~lUoG9Uj)JErflYEu4uGq-@w`ee+kYOypCNJ|BH
zLMM?CQ%rH;Y(+brQlF*s32i7muy||QFh2B)bO{MPzG(sl^^cELYU>O5F1(kbBDY;r
zWS>JIXSl|C{zts)UP`wrNj-hDi?(<BRdz^DKl@;k`u*$~cOIK{@xQRou5CY|q%s=J
zThLMH^qMe;F(DUqoXk24xn}mqy3p&uoy~rXQbWtpB%ae*R8n`E+WN$0uE9dyUFeU&
z_Ey33mRMr=Q@N)nQpIvz^B(^2+A(FJk>9ny$Ojs)NHOnjbZoaZe7P}|qa1qpvF$z|
z)p=g;rY}ZR1#vsZ*#rL;U$K0SYO$qP#dl}OKh1zB$T)GHP+}ffLU2FxhThELLs(2V
zerxEOw%oaNT4Wj1vsrtAnh!!0QmAdGc4UK)__ArOdFEK%=-H+pMQy#!srO<suVd6E
z7`b+bDHjT<t(ME((JUldgBpTFun&gQuNw4cYIO+Mc%8z*IUTOfM|8&Gi~01H0`<SP
zRPKQWf`~$pP8?(b+LWa6O`vNnPnu`)kMfeon#v>a17_rzAl8;$O<rlGMW_scGNkgA
zJt(ttx66v7$n#XmUQ|y!!SNP74M;$3hqpJ_CeRe1ls9I>_%4__;qK=_fx7~+EGyZr
z82x}x_`Y=ymJZ)|JX<9W!_aAa*Th1WQ$k}=mf#z8YJ|G*58bLR!2uuG6qPx5e*|I@
zYP+p!kJ4kf+%~uSYFo|HWlB6|YjFnC-Kz)Ss}0VKQA>qk3&C0^2z#T=ZlzZ`fIh;p
zoUFvwjHoMD&M#)c%Z^WAw>1Pb73qx&mPyW)G6l|vOm3;{(++N26#g?}L^8viTFSiq
zSlP_X9Q0TuMuc1utd$Q!-D_B(ob(~e1`%jXXL$oT)?k9Zp>mO}3goj?yL|1t2h)!T
zX<`eeWNXmy$t)4iZL(6e9I{Iw?$pFRW+-`B2Daq_&mCZ*(G0bBq#ncvlZ$F0=ulFY
zFMZL_;M>{RkWb`}V?4Mz6(&$y1!0TsY^>l%x!BEIObGYDj#4oQSxb4cTqd7^Pm|j~
zj0*yl_+r(WsBq~=d>`c=*)o3OxRL}p#$moPyWbQ=WEXAZ993KsR5Br}a!fFX5h{Bs
zS`z_2s&V>7e)P@u9Q^1qz<jV4cs~nOW<rXKF<KMkCiz&QM?#a;V*@xSu?bwqunBDj
z+t`w%3>It40JEih><Im2Qt188S8VKvz3Ex0txP>gdZY4x6{7nxoO#y0<3~IJbKE3(
zd13FiasyF9>tHZj@?rF}7Hkf}f=(9i2~Mg02;Rn3y&E>*<y`7?Wp>KD@wEd}1n^zW
z4a|6}OCNX8S9U;Y^8#&)58yaX{{b6eZLc)7+ZrsAdz=iGV-d&Ww%dwj#tsQTP9++-
z$*K#aQCr!-$XxmN8EH^k+a=94euQ{2&m|C>$GKB8-o($!aL^&)%>5jnO8csNREqsW
zlO!?>^agLv<g8=qY{iCz^YT#0#P#)5NInCgQd?OVL0Mq8)liwi$0IM0qrbY9FA^V7
z0L`If>$P}a*1LKG3T+T0B51PRs5@(mT0yb|hCcMEm>?|sh|LSexL#`X+HGA&snnrm
zBfAXQl9R|f^IDDwrNs-hXtrUI_Ohreeb-2beU;(R-);53Le2b$>LP0En_RIX%lvET
z2Y+SK`LoZm5P^qBZOuC5HeSJtpbPWSaamMm0_j9=I%#L+w>)3DXE70(gcH-8<zTlp
z%P;lr>|dh;)p|0i4T2FN=BSjJ2dyBjK9I>;*es9hW%s>+(7X^)6DO)_zk(#)r+=3K
zva~dEa9S^!y6ziqW^G);ehze@27XPI`V&tU@xvV=k=hwNhl3pwuFfV)^%Rt0Bp)Ln
z@k0S7om4@P%~Z8Sq&)BrpLsl0k*xO$*tbeTVLO5EG8J|vC(?>%Qgi>{qvY*0z6v<~
zIL~t@vvAMRJnP=^wZff$oSX6vyp-|6_ZU3cvd@m^mi=yaVAfR4|L|<S^wT0(?Y261
z5qv%KJxFMsmuYum<pRIVRAA$bkXVQM+ESaLSKIb#cF1uJ>j)_xUpB>Z^nuHxltUKs
zxV$}TrY1#BV500Y^NU|!a`kOVDQMUerC1lzQI^_DQR;~G&yKl80uq$s=V+BhBYP9o
z<}@_d>sP=)QKuo$H?@aC;XZw=s=1`)?xc4G!eP&Mpw`kfDPEn2EZ!P2x50?h;S!#B
zHE5^SoVOQ+{9&46v!WX5ql~i;S(RWh==VwQmP2&bZ-h;WYJ=Y%U}6Wvm|AHSJ5*++
zpH;414Bz*soo#_-a^a`4EUH?1Z`n`5K5jw7%B^-tv{Xh@5|!MxW4+kr%SdyRfAEy3
z;wLKJWTsSbd;Y*+3KB8YpqOf=b|rfFe3Ou9SR}O#gP><-WT|HEibWQ+2uzHKEF?#l
z@lXs((nZs8@mUV^C{Y{<q8=f04T$umP$jFN-NCOg##nHj7LH&Z7d$2|aPPs{Pf|QR
z4QF>W$t}uZ5s_gWi-$hbbtdh^E6ubj%LYuL%Pq)bPx%PK6m*FBAQG9zKEdW(Ee=bi
zP1X<*-$CHP2<JFCB*FKwWUrymeeJP>ImY&$L8B*fHAro(#xvgZqL=kvsrjxd6r;AN
zdZ@~rb*}+M!NvZVH0G<_I-#JHD%z&3ZYt-om+sfFLopW3vYE5w<Y@s#Fb<G{(j5Xp
zbcLwtMhrZz<_9c#9;!f+Zsf;Yv`!bwtq{{Y3p3uOL&?gpeIUMB3@=v5=27hF9-W9u
z>On>zHONwqA@b5cmT~V>=crZhQ9>7mkYgDqW)#Y_gUy!fVjT>R60BR3qR<L{dbvuV
zb2A<@D(zJn>Jrv83xbeII$+|^wsHrADC-#ASl30p!p`9*7gVYl4sFjHzU9P{Q0xKl
z7-4O&qi`T?+{g~365yHqmF6&5D@XuDF+amER1s7+dMfJ?9|+Jg`aE^di{T}v_J&H`
zm1PlnQTvb=uu~<qlW~@Jd{s0R**w^0GbI&8mV`!pB}_01YFB3w4wjtL9eTbCieeWN
zup9#pP)KknEbuV}&`eHx4`bY}i(xJgBW#uvFv}BwAEA1D7>33cw6c}M8H4Qz7H*8n
zf{wk6mJ~iLDyl2WEHTlbj`1z7JY-1duot;u0B3nnm3c6a!i9VvPGXCV$UA0O*7*&G
zPKBtky~VGDUBM9;)F1g}AA-7AX80mJC`bJj3H1Q(HtIzbCr4;E>!1vWL^gB#m{#^v
zCt6`G&x>fr%is?A2KG0Nh$C-C#3#NI%R&fwrN9m&e2H_Hfp2muymQyNIYkM|8~58X
zX+Z`fIAYFH^Jtu-BpF#osNXZu<CtNF8y#C7Cpbw8p3br@^0P=n2^yeBdn#5GYoUxr
zg%1I8<_^b3YYk>(w-Ou@XHf8+n}OoN^NY$Ppn)gKQt<QqEI?%+_&K4QkLIm`pZO?K
zDaT+47F_Dt<mdTWT9}AslWeDUU>cT8gHV~9__fCXb0lsCW~qznldD4fCWi984Z=28
z?eMi_o2hgSUX)55u+0QZh<=;rx9-r8YLF83mRFV70>8)~)YLZ+u!IkTDvy9og*b~b
zFS}&hj;R}un0tbt8ls;)v&^bRKX-+zdNf1e5oF2ui8CwADuSE_DXrSIqZ#F^iUjPp
z)RZ$I(!JN|HI^VFN`jz=9CWPCSf(RRU?@f9kjzw+LGF26zDASB-XUy9U6fNaf><;@
zoX0r?N~Zzd6N@M#%oCUb!BY`=xN&yjdTv>#UJ1Y>WCicqBiO}O(2y%19zR0@&~Kzj
zcnpOS4ArO}KR1%MEiJ5cdo8|O9|&L`H^K(eOo-{Vt5F<_EQVA>gaSMS_cPQe@gY_Q
zgE|&rB{@|N3?Cq^gcacRSe*0H+;X=<ar(T}NGwS?7x>v&ZWod$HBFEGJeDa^&_ZxX
zG{#J_RDSiULtxBjkQ*iU)`Sw9Au;r#sC%n0-dn`3E4+gt)bs#<?Xz5Im~r2zF$o1b
z{wnU>_`aa5Cx}mCPVqZiQ`=M<DwLg!SbKKeb(yanlyxnGY4gMNTBTd|F=~rA=q7!q
z@{-Vp0o!Z7kK<Kk1-@WM(6kfUa)^t*;Z-s&JdKnyQ9{Rqjgu|f^itMU7(jKbA?EFC
zu*YhCoV*)l?vzffB~xSXU|Lc}bW7ki_om1<$!@{j-C8_cg=wlCC|S?iTH+}&#-*yl
zVD?Vv7BClazE$x3h{1;R9&Y`%LTjrE$b=?A*hEoN91hW0)UAmr5(1p6B8TEIt|H<j
z*B--Q2U%_k8dMw%BtQ?D$uwxzmSN_bi5qr9iV6_lykl^+?0W#Nb4&2~Lm9V))-jl%
zqSmaxZziz9*D_g@KV|v%?%h}M&6hGA(cu+(a>O<TD~hwRjy=@O*Ds|Fav@#*R4q?Z
z`P~f0rJ(Wx7gvFTaS@c?)@sGC=;Np&uQk7?UY>hUxIR^iYz@X^?byXEzZO#nx2k5*
zMAUX4JA_DYXKeYO&byO8M5)XihW=3!eCsk?v9=#)DCsP_h3l!ACf}cvWr3DFH(VeL
zt@Za9v!>vu_cR`Y=dVNsz9O1^$Rp|<nVq{i^4+pDplLU43`r^ld({&O=g9lWoIVK&
zi0iX2T%E5rIB>;wNeJ@Y_fcsxly#R=c6x6tBjbygJm(5_1{j83Yg(Z&hl72DLx=f3
z_P6dc0esQ@;LLPyYU2{;mkwsOw~&^<U&?)4XEI)#qsr=T)CWG#bZUuZ^pE{G+~Dir
z!xE5vAUt@bDh)-&hC%++kIrND-9N<Zdw*bQV(ovTUYr>#vhaPkwp!ZKIQ@B0OH`@*
zesg7F+U<++%~w5I=r~;v8NFaQ@j?+|w!#s`-wW-|&x3!vWJYND*qqC>4YCJlfoQ^Y
zQP`4y4VKhzzb$356B`;0hQr!pxh3U!2d!RWvf|?Fj{d{tzM#z_YB5vYW8aqcElk*x
z8+CQ~k8QVpcIumuEll-l**?Mv%AVcW!ch6k?}p5Cl_Yg;^*6ts9kM#79iE`fASPW>
z>P}182i{+}YuE(xG^em%!9$=odzFbigj3XnUww^9sB=%zino8Ltrq}Y`1B~pa6Y@Q
zh}u6ocXGe$KK=&hzT@uLKDl-YEfrN&0_lbklmk$nIY|NDPiISl?xWwG7jY7Y%B8zl
zp$uV4!A(nR^u6q1$*Huq!DF?nKM$`xb}{3%DUHzkfrSdi%M5gPAz$ZH5_FZ(Jf1k<
zG3k*vm_yhtouK9AZ$`Fu9#qIT2Q6KlqW(6WKg786dl1L<SRk7YCO)+<%9^@6jFB!f
zvyNCOfwrejAS)eDz%UqnqB$j;s3d02SJHbUK6JZ@$j_)XaO}J&8{pl_eEhA1taB$e
zMn1~@C25N(z^bAATc5de5f|v?mAth7^A}gc{37>d3S}?A9Xp_@Q{NeE;uh&7XPn;|
zV@KaWJMmQI3qd*eq4ND;Kh(>njJllDbu^SM+*=M6v^&6G0*WP?jZMMe_z#s^X)lvf
zv4|yPu7_b@MD+;#+NflXG)Tq#W!n|J135{2wBa7M2oVabXmyBm_3f#ZXf_qy+b;r}
ze!v!yz-oKEEeeTv%_-}3e3+}7SHy<i)_=Ru<1PY^p+HqCJPGMLX*)vgAH>`@0VP@3
z292Ipn%b_ce7OdOt0a@d%dkxHwGA9&%r|O?wPmQOMpiN(;N8;9v+U6&&4AFtggX?l
zNZashGNVK%z~qpar!&M+rYjvhR$?78W8j0mDAdpj{0TR&JWS%w$Qw^w6noZcMqx$&
zU>2m(_^4$U_7VtpbH3!6H_PeRaRICI{31WNr*a2b#9d`=#Y#}-HQ*5kgr!smA-p&Y
zQ5ghrZ6M1U-cfbC3x7gE*j4IHTmlo(XJo_24iHD|eYq)MDBKH%Quq9B;1_8-0n<Es
zdJjkGu`nyY1faM=)^2jAr|q3>^>~pzY}tuxMg=!>9)abCIKfgt1*G2S$=(d5?W$mX
zwWhj2!5Hp?Y(W33AIZscNlRs^KY;&+*K+zE0pZ#TfY4(<&SrGWaPp@=7y?43Iwhz}
z%laLaQcy@gJ(1`;EQU%yn2iTrSb~1#s6BQwk)NgLYXm%E&N{k)Y^DQBFPDopvzf!X
zdTsg$CFn5-qKosiz&e*1q%4JsUth%yTy{xK6E6gh$BVco@cUVD>JlFL*&w&pVrill
zM!+}0m895nVO6e3&9oezPho?f%5EPvIjTvlZss*Q%>sr(Uv0hb6H&UT!S&f>I$U^=
zj_FjLh7>tLyfvB9wU{lsxk_zyUX!53DsYd+DK<K|)CCCK&6&9$*hjyABD%)?%WK*C
zKO;YHLpo>LCZd$)dTIq@nl1G~v-hD;eyu{$B-I~Gt4vZ`<DXRlU!3G*=thf|RCEmU
zSE*WG)S2OflYA>g??3kV-Jj<)ODu1L=7u6(Q*npdnw#2sidu90X9?l(<Q^DfTTCyj
zY-~e?0H9}_r+ih!9y`Wx;B~#!3!eUK1iSvA#b5@Xo6@oLQkJa0;a!loolT?bizTNL
z&F9G@Ax9wzv813^UK{2)8n{`n6lXW^1n6W4N6^|WDNJ4Lkp0olU9--vi5z{G^Xq4u
z?s<{z{A*MgFjC&oY}K0Dt#{2DXAx<P@f!x??!hZLp#$0@ce2^`&QqD%uBok`9bZZU
z9Q%L^-G{$B4_|G&@J}9V7xCh^aOCPZcw-mQv0mrCO?Rf0)a9-T<OPZ(JLpSEU25yH
zsja-26~<{Jpy<tyVGy$??+%=@Y^RE*v}%w%%PvVMmG)CwC)oq6ao=qe-lxBlIqkX3
z%Pt-I_}8f!_oC9EKSuLKOY<TU_z(ElS~q7q*~+0@JULj^(ZD?ch=C=6kdLD)R%)wK
z2ugwThao`raQCjs1$BwhG)jorDZj&?%xyWLG=&=VnYL4H><pnDXRk_Q^*usF>Vg~Y
zXCFf;7?C@h983Ew?f2JMz>?3s97J5c{_g139&;B(mEL9RIs||iq_!&i-G`4A?s{Z)
zn)9gTnP%q3ZnRuQLlKdI&}Lpxy&PBuVX6eTz+u;^T}uS*rCja6vqicw-%qa==x5Sr
zGX8=~rJi|XoHWH!7-hpv8zypAl@D_0Ml7$M$Vb*~vYX^L9CVo5)K=HKcyg@n=1F0J
z6lO;M?7LgDM)oaPB(Ye1TM3GwJm7zK-f{jgXzj7D@(!mdj3=7DMqH~b`<G6*`><C;
zKCLVso$9*Nl#J<-Zw>A`)Yja6g0k=8$+!<P!bc$LJja_iHA}{<c~@T9o*o_7rPddF
zan?@SD7Zu5c5aTT7#NHhXBGw{yeKqo@oA%e1&_yQUQ}<$2S=eQH&$8HYAXn-E>X7`
zhiSr$T6>2XMu50k0kH=qy;84`r6DzE_MwUdwDO*rX=>Vr*cMh&$S%*8<~Z6trY!8g
zAC=+)AW%4+Pa}|{5pHEo$L@eY$V4_tEOQ#B{40=7rqfKO3doOhIj(2v7{+k^rlaQJ
z5cZjOJ3^dHJi@`mjtIMXmbM2GgTlRNq=o!Emhu5&hey9y&8vF&NI#geEaH;eFz_T5
zoTWFxx4p0dU4EVh5GGvK4W<c4yZ|N1&OkBa<#OG58w_Msd)*_jqV*a#o{L4IWiD)1
z2=lvIHHR-UqS>U(aLYGnW6?O%eI0E-;V!w2?l_ecN-#-z-P+1{Or_UNAQF2dy_RdL
zIxuau#IX&6U2tYz6h}!81LLkj>?)I_UaN2aICJqj5@@|0o-HBx?UvZQxwbyCX4K+J
zI?=N=U|0JpAv0C^`#R$tJlB*##MJVbt`QatsboiVd(P$E6-o`;gKOUlOzO*~k9QB7
z0PvCTVyP`~3h%H(TNb(b(vYK`Q+nF__dZ}-%zeb!xDC6@T^JqrSfW(}<Ru3Q#JyFz
z$ZCu#LryIHD)8G}wQr`Xvj-4+22+)oldG;4GGp?po?)9SIeMFMhbzlOsZ+losh{rq
z%Muh?C0y9}Cl6%zErB<QwJN2rr>=85^vfW3X9<auRiXO@Tuthm-r?;tWXXBl>;NTB
zH90p}ix_0Un`<wRoavT9tV|hwyQczIZ0CnVO=Sz_4p!9GB+IAb!o=ooE3>-&Nc2_2
zxWBGJT8G{k^*Q^GR(3je=kkp?SDd_xYie%tM9NzIWeJ7u3hUBuZIPc2ynICvjrij(
zgDlc~Rd!o;3jQC^`)Cr;>a3+SqZRt%^!{*>#l7EcwqcstFz~MYu?puK*E48~JaDd2
z^-z!DU`mGC%o`&%TiT!lTAzgWhhU0ZqKE@mr?>{3LA}jVq_p-aR}}uz@OvCFn94$i
z+R9e3=k)v~QMsz6hjkYSj*<B&n&F0jF$RT$%5Wq&Ny6``t-_+zR*&iK{+mY0ZmZQ$
zOM(5a2DgQx97Y#J&ORj}y`<b13w+=P-^*Tbj(a?i_UlNETQ7w=7({ksiPR6W&hy?p
z*ghXo4!k#uq~J^|*pKG7-eUtBBKh&ZX=JCt$n@IW^f}sv#eG*6f=G#vp&-T{eCtwF
zy^r6x)#dk{npdRqIf_>)wEu*Fl8W3t+H`YYWo5Lji%%~m_}x#$=vT8zaTcWYES!Ci
ztDrm6Y$N97viq1T9({e<ZCycawXNdv&u?w9$EUGv2(*jnxB>Pq>2^`Ll79_~9(u^v
zSVV0d3Oz8|e_|iuU{m$oE}N800j1FS<XlS|$njTymx7nCX=#{24zGu>rMLb0zrQG_
z!l_y90eV7w!7Z+kiE!Y?ylX{?A8M;-lh<_8R7*B8cdRBdN3;MD|Jq;4;wp|2Db!O~
zJSb6U1A!*_v$IzfCT6QhkP~#>WZ@M1>Gwn6WBF)Ue=E-K2X*0H?c7kWe{as%8@bOw
zy#-`@i*#~QHBY>m6dvX*hq5oV^?V1VcK)^A_1?@ZT{0UAqpUZZaH%h|!d6<_U@=tA
zrF?o@z;2Gd+PeBZBzFH6wBN<OPKmA_Zw0(L%&d{+Lh!bJ_%nP!<ie0aZtF}{4`+Kn
zg;9~E1GIfmtw5&T)>Bs5<CKVqfK{9Lle0FR)eX<KL8gTE29?^{vlTzc8RS*I)>X{s
zXcz9=JX=G#ckwP98~oO@pqkUk&&=UsjV*6q!Hru)443j%qnlLAfbyf><)`1+3cc&x
zPcQ$YL-%R7Re2c>CfuXWUw~P=Tiq&P?|H3L3Y^st525ntnEjCRl&`^jWnxtMFb~Ok
za;4^eaT95v%_g0~@H2gqI!);^kEeS%Td4spw(i5ce4{wo^kcpD2p$H$GKUyaDQOLr
zumkDQp|{l2c-ofWqEvTKTP@pFb{1hQ>foqC7fp8zoc{Dxt|#Rk<`h5eAGG(wd>8!b
z^pQ1%><&w&f7BA(0Wa2mU8~2nYiAQyw!mpgFyc{pcTENBe#W&{wqR9OlTP2e{@R8-
z1~6CQEBzX)biVSH!6{&#sI75fR_-P&$tTw6^7M`1ZBMzxp#TjxrROmiIO-`yQ>6#@
zh3g`6z`IgLMTFU~2r60j;4%n}#WtwQuh&w*p$a`_OFrT0qY+FLKnQwFxO`>SWEgP)
zN^3A=kr}8DuweCNN93M-M_gyez#Tk&^6Qe1EewR1_0|fSukzDpEy`Y~n-Z?-ZmWcu
zo(ovNSukoe3JxPDGOuB%jo9PGE}!;Fu2G7HHPRr9AU+O?m+f9XYS8A&P*4RRwn6l1
zoyxiHvZUFH@@|Hxwrpe#E%3}cw%3M=BONHDZ}wQF&vCC%`@~U;!<bmubeDtWoUXH_
zvLr!5b_Fmhq_`_i6%a&X2&A-pg;mT~mWUb1Cy%h&Z}gU+5>=LMek6ylbc0oEKX?Rw
zLjbZ8M-?;0NUXF1)i#m{U*7{`hF?D$vJhnL0K*QKR4qrY{^q9~J3-*nXZZI^e=WD<
zYSd$1JVDw+vJ)(~yuM)Qt1K7zEm7O0IE#rnT_}x%*nwWg_0SZMP|ogNw8$l)gQ1MB
zBA4(&AHC??DocAJ_62fbSnZCo)Vr;XFK-c{0>*E3T%3;ZPth4Mptre?B`BaB_mKy7
zNPD{OB;Q!Z?*j_hBgAcZZ)xQd<we#E;{Tw<tn*Ea=Z^-I!~Oq1ZSMnJ*>Tr-*1hja
z{aTj0U$+%UaU8oOD~=KpEV~Wc2~Av*l|(UyD8v~W*1)szI!-2&Z3r;U;3OqkvE}>$
z<qv~dLU<VOPLs(nJ%eXY$Z+7=&g}8*co_o*GHhl?;beTg2IlCn0enK>?C1Ndd*6HN
zmfm}9dw$ZZzrXs`uYUFC)~~8=T^8xS6^Gyn2B7%!DgS)?h)EKZ;NT=dHded#v74#~
z?T<P{zkM4bKb*$=Z)Oa)|JgeZ33F`!CumH(H`n1yBAs|5FN*CM?;{_!;gB#{Jl5*u
zWeK9-Dc;xo9QO8+yjlJ>dvddxn?-GHxo^K@g-@^KkD&Z^ggFp4k!}CguvKNkA>68I
zL?u_KA8S;R3K;;sL&DE};*O;XQAtnzNp>VQuAD`&EZBy<ggmaa84b6+91fS-v|rnI
zrjWe*rS=JF6!Q^5t=*~JP5*<e1+A=&urGZ$c<Hk-`z7}P%3<7o=AyzXuJv?8qh#VL
z&gOO+Tb34-5C|C0G4vY>QfW+1I}o~qR)JOi{m)WcQ`{9pwZ=0A58ZojWc&wp>#IeK
z|KG9>3F`$-@?T>{{@T*HpsX%>33q{`>y|rHs}o;CYu9e;L#VB-=G&rs#*G(jBhqt+
zL%KNz&f=PAtCVR}OlFW*1r+b2Kn`L%3iHrEY_%%=Q4}VR|GqVEB&k&f^vCo`NR-qi
zp?m#jIAA+0a<irq6{BXWv%p>lu*0Em<^{9_t7;{-+q%vO%vNgni6_^ZQf2hD(HKC9
zWa2m^yi#AE+VKP!A9_F!fr8!EN>1A_eEYY1PYVB77Db_DYU{60Ot{WtuTBc*TcwkN
zy87*Rue;V(%*$6($0iVo*i_B;yN$aZ9yhf$o4$e(7?Pde{hgVO_Op!#Vn!VYLIy%>
zaZ9_cD6eiVfLW-N=Ri2eKdN{82SSei*sk&8pVjS53N`wpeM$oTF{ZXeZPutZM#>Y1
zix#X?LOsS0?KE^=!Pht{Xj7Y}?tkUGP?Gh!*<a*QaoTP5a!?sm;t34Wj)PJ|454=J
zXG=-_!uX7$rM7ld9u+a(mS`8Iwthq+y@FrK`POoZnc)teuTd}`Ss1kWKw4o4LYYD!
z3;7Sk5(KAPQ`3t=J2$xL@Rvu4&ecSRfSv{HwsvYX(RvX;WEfwy7Hg2|t*m@l{Sn@R
zgP9mrRIYBHpsw}Wf1XVe@2rC;YN6~UXxY4{qsb+pOU{>8<pR15IGPt3ehG)+r+{w$
zRs6YDv`$?$1eKTsJ|T6Il}t^RdCrhuraYI(q&4o2vyvF=k0B>SOe&pbL3tJ}Xx0TQ
zOH@J?QPN347Qde{;b<<EAos(u@b<vib0fvYll)qF42rWH8g9`%CA(Dwq@l!mi%_DB
z8dNyzNGep6XBY$_Ks7IsUa!xo!ADaZiU0!Qw6lkN4y>=ze4|4g@HJ}2vL2Jq%NPQv
zt%V`$ZAB_9L7A*5TJZ9Sl|j$+jf`(6Pe$kA)Mw6ncNv|$bion?kCoGjZMuisO9l!A
zebb``<_{iK;~5Uio8V-_@h%Lb0NpD|qb;WatU0YZiAO8Py2hVW`8cc=W#{}dSBB0=
z{40gPtGJUf&Fg~&(QmOM-xtXz<5~);OIlVKCZw2oln0n<SE07{v%el+VeKnmHPx1T
zb%^x+=*sbS$U6C|jkd%@9-GES2h&eRHF1EZRm%R7(vHW(yaEi6ViDxJOh#9x^6UY=
zE~e2+GTApxl)x_-LY<;pOClqWWwa|dPiWxhV9V^bJgL}n4FHg&pav^Yogxhd3yvI>
z>27)S%1)dy7u4_c>q$k4_Ji1q=+bKU!cuj41vH&^Q4WDtm<+@v#qWL~tHqYP2H=ko
zinR+QCIy}0x6pUKc^6X8v*q8E%Alh!zN-e;V(1}`<ceJ^%>nLY$~ix-ptd`aI>22v
zC(&%FyeEE=4MCQ@qf6h3K-Fy7B0sT(|1f3KZmWZ<VGxDz<@?c^eqdIM{Pguk8plrL
zu9$jxF}wYS#dJ2Ai0UZrgr#Dpm0g=XOlbP<<XF}CG{qSP&AhKoo*s8WlQRJ&DdJmJ
z(LOnmxB5z99Xvv|*p$|luL{iLXiI3z-0-r2J~hE+;W(NtkbPs_Wlw50cETGoH`%8}
zUPl0XwoJY%4sq@ap>7m5LZG%s+s97$N+0DEU%s-j27_1h+Aq_%&|J13{w||Z&EUD&
z@>@B5X=*EHwM^%Gj>kqxDWq!7K6-0Z$BCQ2_tF*{p)Nozir`S_pb?#YjLYrGHY{%6
zV+pwC)cyFMWbUD>UdQ81-+Lqzv}L-?bF?Ahp!N7uPrfRbJ`mA*d?2tb<xr&_2=l~J
zIo8wTcivFM;*BP9y`|f{?p7jp;Qq{k7AtGWw{d0Wb@6H3c~i{AnSF+1Y?>$kV`N!=
zG*P?k3~LVIO}+t2%Zof(Pq_adn1n!q`QZQ`aF$EAd;FQVxQU0ZR~qBaI(?A0=3VZA
z5Q$Y<+1(FS;O^csTf$<K>Y8r<IUN;AX3hUQ?OW$pqsYcbD89+|UyT<BYfWDS20|p(
zw9~I1E-YJnf0;liy!z}{=G+$gY^@xoA@=fjFUI!&i$0>V9sm4#xh|BS`RyaAA;H{m
z-AXkNqLf1y_%cfUI&pW~o|3rmIX-vUF2>4BK00lmyKJ}by$JmyH7#q=lav3(wf!B9
zF}t%CYF?l8NGOml?_xr7$ER}lN^M=Ie}V_W@wI45_v4fC(e~rKHU4AcsY>@sw0}&E
zy;?h9O?!w7*_|n*t+Duon{y9e#B^UH^v&Zs$LjK}mn;RmG@a9!fBLrO6gpn+o-4Sf
zj;l)*MM(yOWvc;j<)Q_no{1I!1-`LC|LpFz;<o{+{0Zvwp_gXh10QtbwjmpALQ=JA
ziy34XbM;{IIZ|0ENufg9Xs@CCbDJKOgs#7=oUd?8@dWP}7-wR6o6?0b)a_ef=!rB!
zG_|ssn8)VE>1>rT-soyDRZAQUoSu1!FwTA%gJ0tWZ{sWAg+a<VMrvdcN|7(kV+BoW
zrXtc%{K1fx^1Uf@Axhp-OstNumlYtDkC@@`X;7d(7p&5%G@R;-%2t`@^CD8W5Oj-K
zytd$k9W^yAaCG>&B!TV`T?^XVP~r9j$VDQeOw+%8y$z9(O@^Lh?B=knDeqQiBa6Rs
z7f)j2^-1i&uZDEf(R7dfI$}S2GOa2pm#3IrtO!rCec{l&1sYy$3_#XW2)Pu2FN*{V
z3PE*7g!dE_$2j2&Zt7?RZ=ExGG;r^8qEsnEq1EtqVGc6%LbkSYJHnx8ODbNgbSqt1
zg|nHrf}SFV#*Bxx0Z+TO%r-2Pz`-yZ!Z`?OEn_@VD#zLFj6!Fzm;s9*r!I?Y(jB3R
zEvIbx3ZMcL_}XzX+HJe8MQs(=5h}?D5WSEB(sk_I2J?)VRJiAY=v2_g4wc)i1)1F@
z!?Qzm>Pks6SFszxc^ahZ!JVZ!cx-~T@jVP66iN0<sE4+ZO(`TXb~HIl9j&_3y98t+
z>;x&i@{m?@(+c_uQwQy`W9ZAOw*X3YfhM|<A4`@@7qWoUdGTWfq`(GI&t>QY67f^<
zYlvz1z&jZg?{QT@yLh(XbBvh#P$7B5=lwbHFTlGrFs%yc6UNOhm6i(FCCHGXFVKwC
z>=~sAOu%Fd=!scJ4$qH>9<279=emX}hq0FdX?;AGz&y7J7j>XFhv^%2P;E1$>3-5$
z9(AyF=;R4{a50pz)uVteQF-=)xZ$motZK1*;ngZ;V!jt9VR4`EzThgUtb}b7hyIk;
z*eYm{YM0(*{gdnyT<MOezc|j5O>+$94cE2D0~+NTGYS=G7%0DOkZmsZWMdNQ5Cl#%
zgWLWvkIXkFzqVnu$?L{;Sg~$jP1iYwOih0TT^qz{u7h3h8weU_yYO7Y-S3VCiN2mK
z74Gv5pVZb4<4DZB%h*ZwU^w?%braU~@sAwO`f;DTA6jr@Wl;?R);fvhCij@XmC4A$
zB`pmEAP<2KuRCeCb>j`rzplmYR&lOQkv2l3bHNJe2_IU}0Fn@MWz2+#mrP%UD-BQ{
z$NbviD5i;ExAoD>y*ti#5w-2vY_Cw``3=p;23t{YlA+qIk!%PA;<eA0ul=xd@BPP3
zk9KNF(4?a2P4AfSCM#vj8B?|dpM$G~13uL6J({d8|9UI8*Kt)}Lxr~tk`P<`;@|yp
z>!@e}VOuAWe~0yaZXrr)>->^)>!(t-o5HD7as=`=y5OJXu6;ktBifK%*!D#P!_9qe
z&V(87XLItdX%|+iy-Lee82dsIqp6gixXp!f^DW-pqN%5VLa99kxoh6#9tu`SVcEEG
z@+uP#TADtg>dLQjI$N#d)X7G%fDSu;`H%ZnAfQdXL~S?PNUVCfgG5Ip{-N?Extmfw
z{ntx*gYAvZ>R5r5a@bb8DJ1my9cD3PBHeg1fMKfUcYGuAw$}mLuhJ4aT9%TJc#~ba
zac<~ND+Tsutund)Z=Ktw8@K(}4rKXl$3cD6+hf*iA6Pd*S^F)1J9iz<kVX<UZ~lN9
z2F>zO1SXk%`PQQ@zvGhJN@efN4iyMD1;rUe`S|3~cKZ|zeDPp_QsE-zivZz|ixy09
zrloqMt)Phu8h=cWE@3|Ww9WqsI*mjLQ5#~7jdGG`u3nC_zyZcIh^1RS64L7ur<1^;
zpa_J^3C~hrqCCy}+{%{G-edZtYQ8(07fSb43t~nA)n^SY9;9SvK<+9@C^_xzzDfDr
z=iKd63$yDFO0MJheH&Aoypt%@m&F@+6DMR={Fb|gmEj$5+WZXu$otjPZ$@UPtp%m7
zR!8n>Z@8JMt$SRK+Pdk!;5+X4RT0D_+C5WTP+(M%c0;jN`K5sbx5{@#s(>gvReF$<
z!b=MMva`@V4fZ8%d?>EBtI?yiON43=#wv$dIdN@hSJ2`$n5Y5=erkh&=IdULfzaf^
z-2)}9dG#nd%i)NTG)^cNx3$D6=NByvocSuLF<G49@R^uEAnk0WinV8%q0L)NG+YZ9
zVsN6E+0_hK6zzyN%0rS|Nc4DmR=1_42`*2ckx-K@tU4ouVgf>#>+$M>U=nULYxKx!
z6rN&8GM!1(@^lYQTMHD8juZ#tt<8k|=mM^oMFk|_)gpTv(Uo<`sCMWfMmSAFgc~RL
zdOR=>JCQb}BJh}9!!nq&TL}_pE-PscQQ-@2qY0gGa1t*^zEdliuE=f(Wi%KUEvr>)
zqD!Nt8U;(j>xa<wcyoEy<g4bLxMyUH6edXrz9bU&VZ$BOP$#Paxgrl<e9Dr@TvzPV
zOy<l}qap*Jc<6;(uq*g(5=vssZ>5lkMa_{zVFBYIW!4cBRAY7*qeI^C!mC?=IVA*O
zQf;;$B$&aFCsmPmd~!NaRlik|#KhqAd&bh!fQqRaBgjGLsiDm{<(%giB!<AxTIJQU
z^^8g@i}F1$2z@mtIjH*>un%c-G|SspfjRT?1l>~iw~;z>U)vL-(WM5Hd?FQWGl9+*
zQ+2R=7!9pzNr9*>4{lTI)^mz7`R!VqsCvA$ma26ajlGTN-C|w*lb{6MIbH|son)lY
z^5zOn+Nml}(-r~K77hu+<Xw&1(bCefLZ%v&iaCZ`og#PC)>p@uvV?mKPPS*_DEtHw
z=gW_@44bcfG?o2C;U>^$b+ct~cdnDkRgQ1Yw`RI;eTsPgqie8u7#`$Vxa9ft+%q|I
zLY<KV${Qhf1>|-j6Cbwa*b{6PQDnb)Nyk0;Dq75mBG@9oI~iR5PPnqm?y+1+Lh140
z6Y^0fr{3)25^AgKe^J<?_A{bSF>7xi>+)(hogRe*Qd~8zsCbpv%P|UgA?ZqAm4fdp
z%3Bm4WO^>wZHIz%3%C3T^MCXK^^$0(b;I_3u66qx3#qNyT6w_vjn~JnrlPcizzR}u
zVX!-Rw>SMj*>`mvBAVL$mEth{(I0kfd!k2z5hO!@x>0y^3$bipxpz5HXcWUiIFi$s
zxsr*UTdx$Tt(5HsBA(*`uz)IEHg956;hpR5_}}MfQjBA4rGDD)+{1(Sq+8njCoXHR
zUF~vFJGMPj=#DB^be2tKo3E$6Z_YvY0nTX)WlOmX0}!*V+g$7a+`6xop|(mMF7UH@
zkq3;C-bN9w3K^0z#vVA@siVBAK%-z4C}E#kohhV0PG0^;K7F+i)GRhG_Qm{viV}a6
zMj0gjk$}b!m2C&=!4yaOJ{027r(GF8d9PQ*alLE%Yxhi4P0O@<UVpWv2^x}A-e~G`
zHd3A(P7|W!)c$tPa3g+!a?h-l(0;?`2=&WU^ljhiqP{j-N}l!cWs}s#2U^a@PdQ$>
zX20^?lkR3t4Hl+zL$18_I*!iW9Q69ObvHMhyTWBcdVF%(*>3AU8TWXtX0dxPoKg>$
z-py0uP6ob~`{VR9jR(@nDvdi6w!-%}`KoRpI#T`{67Hz!{4sZyec{Sx7GFVTge<hj
zIUZP#-hJfva*lCGINFY>WqaDSl`#}_dbr4TE)H5)^!c6SL?%*O^WL7OGJ!Lp=sgmT
ziwZGwpb>kq?{b~4hc5$Xluel&b)VaKi2K#3@>5q)omUWggj@TKGiCcg7VZdFgtaAY
z|CU^%6n>7-wd-7l%o6+&4Yb~ERjEQ1KFDfVg`GVK&X-aAj(4XHgAxsoV{8KuUo=P0
z@I9wo!L^ZZYDd{DU)*TUsKXN!rwN7(&Jkgu!m|=>Bo9Y%(`;!LvN_}y+d4kGLMVi7
zAtdkE`{?92Pxq^6V1=G@6j#o+zm3Nr=e|yHJQX0Ssn{G$#mQGOTI9fwKES9N$-P69
znhWo7evat%U0usgvm=kpJAr5nfsW!Oh(~ibyI~Sh$O{8x38mm3AGeJsh^YWhWz#G)
zGEEK}ofa6InVSmW&J&XJs;Ca(Z4n*|kW!gtj{>b_I!LOPv_7ds5!&82+$A;%*9yq`
zf?N9JC$cS}2JgXXs$+3}#h2JXqTxt61mf;^Usc6;fR>v@2Ca2CV4#K{T2NFIGk^`;
z%9i405j%I79&9nZl*J|+cFTkVFIQB8ib4`*9k`e63qlQT(i+oVI0{?XFJjMd5fv10
zzM7m?<VX=HQeVg;O#7pPG+Y``tdQ%~V!^*Mb5vt8Cdqcim&DYvo2%Z<#7z$z&x`!<
z*KFPo*+|j1BuNF$wQcpI$}JAfwbkKyT0_*E&a>uA)peCdKUNfp7$*b3WNjrizp|~0
zIZqw?q|lUVR$XC$K_@qKlbeJY6gU{h>gdQFdo-Mse;xRu+6WMk9CyQ{^9oqt7x@K#
z?lsoiallWo@+fo|XsKpV*nK<Uh;ly3j))c2H&~p$Ak$eq#tk(}Kp!L?cLnvu_Bnme
z9nTvZ;k^(yoBS45ggGa}@r3X8pi=&-64Mu-)Zi4@4_UjervTCOqWe)RcV`(yAkkt?
z!Y0`Sh@s~XOmVZ*MMxi<L9oXV;Px0j_s|+k`bR>w+K&7-7hTRvrUt=g6gxcpo;>86
z?zaeJMv>x%n3LN_e1pgFraMh_EHom8_uA9UzRuo>yN2%YWGE)e21DPqU~Dh3oADMn
z1Eu<SPW(vD3w<busaA(%cuw@zTnKBlMvYEnBHB}20K)6XucUEmENH_IYAYvUUK!YJ
z1#_EoY3T7BDqP&i&yExQS@-bR=axwQQffsLDj>Ap+IljV+KM_X@MaD+qD8aY%4gsX
z_$y-7pcJaoMLFPUBwE5vh}uI$JGCo)709K)d_rf@xj*<;izw2b=9TUscOw<jddeWY
z{7OpAD~Z3qejr~c-k2R_PQRgup&+GV{SR(<1ho~V_<;tkGR&GLwK-N?Cw@Nvx0zd!
z8vW01h~eyC=I#sSfv_YL9X_?ohA;oXnv}!TrniRX34$8G<Wz2CWczKFBy7Kh``T|^
zbgi#VxOmIkTA@9C4<AQ)dsAvFmowAGiZ?P|kge(Q^FPYW`1_fwHf~sS)Bj@Kwx7{#
zGZW_K5g0l{z1U`*%C%tG3^b;UGj?0uqit3;uI~;H>4w~(#5L~&3DuD*q}7Bq25}Cc
zr7>l2EmfeD!=tDE>XoLY1zRJKBs&j`ZIvHBWVN13K%xb-(b3=w)Kj@e2~<xK*s}AV
zFwO5dguaAIW839wcDndT>wK!fDE;v_zp?Jt77j3D{@ZAhbcyQ`au%X!wSSl5e&foZ
zBvxJ0K<D3{rIL6;XS08iyVrh*Z1G5sPt74G|Kbc|L}WQm)FyACiEmd;%UaCmSw;OC
z^<qb#g)#zn(G;A=Nwui#z6c3H9BBkkxP#2osZq4GJ41n`9OkCBeu?4E1}n`vo)C#2
zJW^zLvF~Ua<qm}=k(AESApR+vln-k!SN9ung@KYq-AQ+XMZJd`tJ-Z9glvJ0P;)9<
z%j9;L(|W9*$Wx4>H)M<q??TwmT?O|5g|@P}BXo!z6&qHXLFNq@0ywMS9eCysy0D`v
z1i}w*TB78W`A05CZRH4~=mNpa!G^c!v(r|osI9*$e?C%DOF7I)1?|J~G}COEM-Yyn
zX>z3OngqrMO{%$s6!ey^-h^p!5PYPzDFOym53q<*5zNIPfXyP!@=WFDY05I5JQ%r7
z0*k{yLLDIT7L!o>oGD<inNLl1yFzoW!cFvQ83bBUmya$rSn%>_oyNNU`gu9CJicq)
zU+9D3)phh{AF-?sd=c!9(WurQITITKQvCFI=q*PUOkRSr<Pygi&*GY<V|lNHc&Pai
zpwV7r!n741q0%(#3#4HPlyaB{&L)SFit`S^@-v_&qsQPgGae<;MV!qxNh|2N>X7qn
zrS5{q#n{QjHZZ0d1Kv@zE>hf7Yz1ntK+DbK9AEYhjZPw9maatAQFRO8HG{SsKz$Kv
z@(nfBoQx>8uN~H&?Ew%)pv#>+`+*vX5UGkHO1fJWrZgut#z5PQ5||=7!qutGd0`Qg
zML9P3c|2he$4B@L1ujQp3e3nCF=qK8G&0OxMg~nJ90+5M?-k*q!iZ4I$vMFwZ`FEo
z;YV>s@?o$=If4>nTX{;8RwCC{4vkqW7Q`dj9wlUn6kZ;ZaJz>Q5ThxPh2~_vMgFB^
zH5V!r@uP|l9>*{^1HtIQ5@8>z>~I4?hQgtq*igVgC@)Qjg=3y4%&~;7^ZZdd)KnlF
zS8zoQ5jt2JG90=08g=zS_dJD65R$T$ISiDoW@M@}YbsfK&0-aDMCdB{j0nn-k^6k4
zqO&56d6r3zyoykO0*E11GyWmqIUXfMp<PFbR^6NBbXiB^`5F;Kt0eAa<o$RARm3NP
zL^^{&rp1{K(Za=8hlP2TH^Vq5`S|P+VY;gkcyAnoYhVmh84d?Hn+7WgbDW<_Swkrv
zm^9jL8_|ZBI%+?=bUY!6WOlc(jhjAdcSk@r5>e1Rz2By}TEub2yg;SqWTFeSo7DSC
zAcP>U)jh>LKQ^NAMc4o+A<rMJ1@a6x8S@c_aZ1yQRm2<-2>bxI4^XN7nY7C2NGg_V
zl;&|4+Mo{s*gg(QDLH8*T1{=jw*OBu=9IZ-w>J_q#$}81NI7KSTnb;SuF&W_&2giv
zIl2Ujwxv%peJ7Dn0v&cTqe3;5<!&1rDj6sgawx!=axl)+q)!b^F&IG%o&$OE`#QMW
z-l_-}>loNi4a-7CVZTn9vXv?7p$^9Oa-SDLGfUZaGf5P7r&ZEHkaWX@0imX^l2eQ>
z-Q?O;FeNZl@>GQSRmsmh3)oSfNiP!+XW}=-n`5Yv@Q0$k5CqLekaVaIv9uD~bS@Q6
zkjAnUta1t>Kd%z$X*V)x><uatL+q~Rvq@Ntis08$CYc%X@iXWqz(=4@p##jqDxyY6
zd`5X~>DdS;FOLTn$2(Sm7Q#z0pgBE71u>X~(O+1vek<_ZU|Wmq=QAPfVR9AULA4ja
zTPkw~nJRFULz#Iwh5{q72Pr-2f^!}DfC+D7R1w$lOyTKZn-VimE<rLTWSnuP#oY)z
zmU!6J1DoVO1jv@>X!^X{lnaSEX(oavBGb2Ec&;lV5~@t*;jzjjNY@eyoP{dwn?`uF
z+A6kES;NS1RMY*4)8&|)!Irj#JovdnZH0h%6c6nz)!Hl`RaD?-B^I?(9#Ea<7Z2hR
zO62F1;ZRrrqvk9MTeMum$jS8rVKN$l5;O4Ya9lJAK?)23$|`t0R>VZvc7@II`5;6#
zOF)bmBS8t)DN*0Za9JU=ppQ7T6|~^SMc+2^V;cwGSyiO%x~55md|R}oh;5*Tcp)%D
z2_;QE)vM(W%acqs16DX?^GkBwEQ3Z|Ra@q9!F7;H3ys_|>*Y2Swh<#vqcNwzBtdfx
zHwwD!aze`!d&AR=fFbok;1`pfe>Zk4F~sLqlLY`ZME7|aa1dk?wdUohQ_DRRNVO!Q
z$hQZ%CL~msWg<CyegV-iX*(ZUo%K4<+E?w_$2OwfIL(^+LEVnBx}e#c#-o{(dpu|n
zeMaDGJTV&n^#s2LJaBu^>Me9Aa4*h#$o;O?%v~Uh&6WP(7v>Jd_GPJTJ0Tb;K62q$
zKa70jBEQyN#NRr^^N@oe<E;4|<=Q$9fHyeyay?aBy>9O<<uIdtwe#-wRZ$OGKQwp(
zGyJ2_ihox0$>KBxz3V`=H@34L(h{Q@)5=w$>3%k)y)ZL;(v6LME~RN7^sFBu&XRj6
z!q2r_-kER@h7XB_m6i)XKbuxdBMaE>x2SHoc4sEBP9LEPUcTYNFITz811=A9sA8`a
zxtn=#R1rh0_^=^9qn`b8n${=5w-#?r`kVoJ2rY|_m>iFzz442WacKj<0lX09ICS?$
z$M4KUolPrP<j=QvF5-P8m4ZDMfBADLA6oXm?}yi#Q%}1h5>c^(YXET2t66-{hsbtk
zQPh=aQa6y6KQ+cR9}oLEk6f5YQKfe`=lHfpT0~&CD6svYCpn||*R!>BvW#Vbl7OM0
zeh`Fp)j`+f8-NCH{fCxGw2hnxuLv&w+Ju{Y{6h@WnymdKZzZ;#UT4Un@v$$_@l$-i
z<<;-g^*2z9e3r8D5>DShE0#a&@~inkm8V{sw;f8mFDaKHrZ~I#J{I6_{C_;xq0q&x
zCQ`kqfmt68L#TA44H4!mwoo7e<9D0ts`o9{%e0Zx+w3TB=W_0`H@eot9rC2sy|#81
zE%|Vx{My9Z5_P?U_7SK9UfDjobAUUHZ<y&GE=)T-|M@_kYa>UcFI$aN$G`cFB^L?k
zAZ$(RhJzY|=NDhkuG-4e5vN<fi-x4#BD<C4?Z2bikske55sql_CQ`~~yENKAYCT7`
zw|_P@VD0|s*4Chr+E9MuYUiFjM&r;HlQJ9urk8~HE62!t<}gQ(`VMi7ka{S}w#oo7
z%4#R0-nR%0mCiPD8f>-X3|4$Fr}1`um}uSo%|+Qu2+=1Yj}tx`6whWHdQfe$U(-z4
z7MATp2lLFoj`}-+P>4__t6{Z>x@5*+{2L)T-0f<Q0{T%j$Ee0<vaI8&TB^c59B3+f
zp5Doi8<seKPPXBY$IJDinCWe838Xzv0=8Z`sn}e_&p=E)*PNNmPB!xJ$je-rPE~?a
zv5jkA@D>wqzbKn(gT8Zf*cbJAMbzZfE3!659bk@}0`hY<II4YVkcyiM;TQN_7;L&n
zs8j^m4+m*lD*^3BGzB`T;Ifd}u|^AtW|DR7z%Pz30Gcgo#gl+)Tk58RljdSJ<{}|2
ze$h%Q+8*B`Mr(_%s;GOV_5cW^<}4%`v|L9K2xaEAm~q8CgN<4Q;Lf#f8jO3vvD2ie
zGbkv@Z4{aj%1ul&yatgQhfNg<P5pivBrqOX#j{dhh-4=bSX;@}lqXX1$l*e?4e3p;
zum~;immnan{)uj!Nr4StGwbqZ6x#EJQngq_C$L6@t(#FR$P$Cjw+RRhAF6OHkbLda
z!8+IOYhh6_X2>xB-ciTtsd^!DtkVs&#a2J)%OVDf@N%gZtY0YPcGf?o(xA7kB>{KE
zOz1#B8n;{vM$Ej=B}ky;SBwYDzLLd0v003}WjxNP{po0H53~|E7$!r1{E=qut?D9`
zjiX`WW(MA(Gx``ecM~G?j(NDzM-`Y7)lb4w4dGfhi|GSK5}B847_<{Ym}FN^!+tQo
zH}i!Wor-`8T7kDZl*eR0Ux!yAY1IHvPr@VDtXhnImei=@xr4!g?Ck^yUXx6e9cv7E
z5|B97?rLSB>)pfA-`|P$=cBZmQQ=mLa3$t|^VL?<aH5T4uj}W*&?&!H#Yl+8v$x>E
z#)Bj(`4x9zkf7Pp4qDB@;IxBdt1mxVS#~Pa__qwc+b^Lb*=uuzmVEt!xe;)fWr@F;
zFvMnjn8BMw8QSP*5YZZR<7dWkE<0wZWKS>wd-8qFc6?*EG0|@Saj~9gGLO>}!TFEd
zqF-cA(rZJJdKev0TQhYn0cA_aUe2(3W-ngEn_64>NxBWCb>%P3MmVd;>jjh5HJ5j$
z1BuonlO$rUpyx_v@j&jvTnH0$8n&-V+)eit2AsVhd~E%4Mu}(1zkCG?rcztA9xGFZ
z2&rNszmXscOO2|!%Q08#7V2okc86Y*1<l~cOa=R9;TCle@X=ensWj`acqYamy!)<P
zTRqBW6FD}fzBU|Ud7qtpa|?g<(kw>>j-)yAbnZ)?6r21}mw5tAmd$6fvq2ua?FGC1
zJuVA@W#4^qX}H{!9uQ)X1GUw&;wN!&0jrm8?7~x=Z2I2sTy%~5nt5yfy*}5qrS7j^
z!JgyOc@hYEP}aUBYi^9a7dG#1#&DXw%lrnEoaaK)Y*AZd=Qh|=NxB&-qd{=<_jniX
z&D>4*oQ&>M3q4dXrz&`4Qc4hHsC0IRNhyuPwV}{jlIx%8xaiYt7cc(&mXt$x>aRZT
zblZ#j(%OHa)=zXyk&Rcq!oL}{H3ZTq`=PMSoomhf3cq#yj4Pzz!T6@s*7m<*Tt{0j
zl&vD>?EE23tJxLPcB5*)&!zUOr(wb0FbEUE@f14#r#UWl`F=~Vu|w#WevAk*K?C*7
zZLcqy8$U|OnZ}qMdo(@%i)7na<yh-qXRbVp4o$key__|-es7{!<5+Afh~WF*${H&Q
zsBY#B%20JO5K0$C%l&UsTd)1+uJz2-1Mx2;(q44iHWoHWr%p@xPn0@JxZt>xS$C?$
z{7c!2*4S=Ti0k|yIJ(PZn`IY<=7@KADZq*D*I!v=PhIML{AmtiaE6eKwI(_3e*K_(
zZKONe2}UB)`NPw$-6Gpk8Q5@V4m4XJn0X;aaG%M1C~b#yo&todebC!L+&ar???M{Y
z<6+Zf&D>3yPI?7bj{Y~cs*20Ki$8rZci(R-b7Z=lKY8@b8*uQ5FzKCaguA}_G6sO{
zq4inwT)lT5Z(l2>&P+6m?MZZyB+VMd?6}J}f+x~pRg<&A4KfnMK!kvT8bq1sKI$D~
z&hwXAz}#yTULgx-7-(lGKs9bf&aO7oLsM%W_s7)Zqvo8JEpMMiF}2}cg2l>y-WKoq
zrFNSrz_#heUG{ZmuH`}T8O&(>$pfw`KDsq6UaG_b4+@b90;GIL?%XXog5!of1A*z$
zJO~l&%`OXjrs!s~XY77~rZ(^-spH%B3`3^VeEXI)0%>WRL`EI<8Out(R!^|h*4gMO
z+_F3)0ctBlCy!zJyuJBYrHXno-<H~aR9Gq|Beu;VEH_Y?kqDxhlKKd+$LgY`oOa`J
zP1QPXL@s53a7QC-rL4V$@}|B<l(t)L`n=;>m$?lKhlg;-0!5GZdIzcAQ-vGnVl&nO
zqu3nfOnWz06@HW?1975aCu3u-#!{iQA8J7B{&&d0b7Ww3*Dh5^@s&v(u`aMHXs{=C
zRPdsQlyi$Q+l)n_rrRVUv=NoXUxpdX1!D^8WSzd0Rm`ZC(Tu{Tl{AAKsjTBVQ<M=9
z6-E`;`OAmUX>wdLGZ~kJA9Ef~N2r3R#Kz462fuL3KQ)Kpyo`asd+b$wHa+damVCxc
zD)_*(qea$r5``WZly8v(wk;z}D_AP6h1=kX>n_#L$Y8~w5!lezmnv9JmNTI$)e0ko
z6_KbUxC!h<dEhm8IRq77$+MRk>!Mj?wCdao&nqxSayOx(J}z63f@^4^_b`G11+CD_
z0c2JxY)e=dVuWgS^HmC;%|a(u<=R`Kdxt9jJ-}-%ztx$xL7q8@M+IYmeRr1emRKyd
ze<(1uU_oi?5YJET1GsDW-KmERz-+07YIgz9zB;gV>6I;xYl?ZL-C?%!<hSPY@lVH`
z7WuV;@7>>|`Y7EGF@qtKmZ`kQ)^IgU9E(bOK~PF<%}?aYf=sB6J0ptIjmY!o2=GUp
zyYZbkP+O<me_F10Tfsj;j!!kBYo_NFMW1NuOJvNYc^nJE9E+h+TUWzosi0lW$xzNU
z#`85x`>Z0qk2YlwoP-r*DON>|{DuR?iNeAz{LUpVe#_xS^@Y}RKCm|x+@TwCru}Pi
z?Viilo0{aa+d9+EuOxxqXtS5Bz`x_s%egfBX^tl084k*J;Xu%L7dHIPMNyiI<{+)-
zSO8|{b>@4%BXs6=4t5G%19SN^YcYr@T2J%n(~&QPy^7h>>!obnL)Rc?xZpqv6{2jZ
zt?uY&&FR*-yr%hnj;?PXaHh7p`yqJpsbbwOz4@n1@F`pVK#5u>9q;UaIb6i-n)KbU
z+n(jRT<P%(f6BXdP<B_-Vmj1IXACOhY$$huMJpjmZJoI1<r^(-t?h!Bt1e`aXBb2p
zK@bwQHHM9|_o+?Td6Ph+ok^RET#QB?s}^E=GuyI#Yw9JYH`;cxt@sC5`hecHK_a!0
z!9cdf;x?y;-f=o}uSaM2bcsA!9Q@c%X0~DJt4-cjsjVi-88pg9Rkrf$od%jMDHa}F
zwh5d@@~NTO&XYn&o*!zfw>@RKcL@C$EyZUacg<h>RziN9Wwm0anb~s3BV2c4YAY=3
zJ;M0qZ?K&zQlfTS30pMFyh)o31faGC_sL_fBek_2mKDA~%scO)wb7B<`pBV>KhDKK
z`=eiQO!L}{NfSdiVOx_!_Cqy7zlIUfxer{F=|$p6?ImU<vkh%GPWgX|<BH+WH?Ry^
zQaxL@&=*Z@g*q^``lCy6oCqIP%>pvf*&3IVNe})cOC2EowxvrEea;@{zOK&*-JT^$
zTct=YypzB)`B67<YooPVD(#*8wr|7`DxBHddfA!9EI;x+i3isvl+=0a3jr5!k_Nl|
z3(bzyR&|mQAl2bkynTJ+(k(dI`Pklxl%?N0YL8H`=|KiOP7{cNF^+`w9LYOO4iw2$
z)fGvGFzxXvX}T2vE!_otqe1SXhawt((w0eEKd|};D63HWK^0^ve;0yzEyz`2-H`Jg
zz7AslOlqqaIqWwR!I?689X~6ycM8InEz(uxsG-#^U09Af9XU_fSjIj;m2*0<L161F
zhJKDJa_e#ogjIJ`v?6ro`RuyARk5&F3i0drir5tvcKOV+SO<xMTB4~dky$r?g3?Sg
z45c;B$2QP|^0f-3Uj{wgepfJ$7xggK@OF0_ZY!2oD`~rk7hqv}<q_4pq$p6kVx(Z|
zW)O@8bLPRU0fwbb@y26JZUrwzt3xBlSyH`e)Z`@#g9R3NsVQAS%kqhW^59yWpS8R_
z{u#7(EJ`Dz%}-I#O`=%GGZ>0$ZCY5W&Z?OVPBc7L*+-!<rq0P0h&AOQdFGSupr6Iz
z8h**n>=?&w3xR$0X1OJz(SS}~u%l^Ej}WE#LcXxzLQFB3ZMhmHpQ*-P=9iC0KP9d<
zGH)4r+#|tUAC`&ElDl}L3yNu^Xf<T-J<AWP1gKoHU4Z4>BPgG>7MmBxBD5WxH`?na
zB3>R6mSkq4sN7}^Gd8*@tdwFic7ys8Cw}`w_HtK@bfY?5S8|B9^%Cr84pi+FC7*IG
z<!EPd#zbZ~31NU)Wvjt=MRg?!#|j?_>NV(#y!?u2BTblSMJ$7`S|LZB`BznpR@ig;
zz;0H@D&q6>J!@sqluB?8D3O-L!cElfNhKnIv&1~2YUGv{0K2|AbbvjUq)cJm`zW)Q
zN~~gwh_bvuAom2v)`Ht!bho36R_w%dbIEVz8}0#gfzEdZO)aAP0!Jj7Kj6EDk~5Rl
zbb<Rrp|cY)Mge8Zq-ac6r-<t|*;?yFZFN%!$<8K=QaOnbPgBk>{0x}7wr+<||8a~H
z{B|1kXbeNcD%X>s3;t6KqIV{5+3>-g=D3-ia=soOB418y{FqnS;-iMN6a7MDH$!Uc
z<R3C?j>l<`(rnL6Fzw@e81C9=m@&*DCJqU=-M`$Y&lz5y;a#5k>oWw#uaF$|sGvxa
z4rb~=s+bLVMu8|Kbik-hDQ$ZyHNVz+$y^DQW?}Y;tQqe)lubA9&g1r3G;-8d`y@gu
zeXa2-?Y7RK>%tR>OMXLPQ>th2#yre|I+hLzYm+ywKXCY{JAC&-(~AbjG#8t9d-vxn
z7qRxvK~K|cfA6K9w7e^L5*BG#Dt#gJp`b<-g!L(@t-nE8fGghzg>MpZXN~}m6Y|)_
zxoiI6A`{w|x(Nao?9_C5AnKBtu)st-zVaIPz{lScUHhg+Yg}sJ!Y`~_@guvfGyXQH
zp!JBeIpr}7UJK$*;E?e6J+Ih&*&pycw@ynkucYF$<{f^9Ljc7KQ?*iVU7^IrOu)YE
zvhR0Z5xP^hR#HvaF$!(``q)u(Ky95(svV&t!87c(25G04Jm=cdPH9OI<uEM%#z$LE
znYIiaJFR=@i!q#fl8pw+rU5Y8X>*|*g|m&S^*I|lhvi*>;Dz*Sm!+fI3>BufYL!7H
zp&@y<wsR$?)n4N=|6o?QM-GRs+PW&1k3KicJv7p6A@pFGrLTTG{-G=j1cXnql<?%u
zuCR|)g5rfX7&a5FnPVYt*&*SpYy40<diGFqr5XXtf!-`ewTU0R#GJL^SHG_n*@g|M
zt^QjoC3PjY{YT+E^Fgnn8P+ewsI)*_gF)G5zdknJjMXPJwA)I{ibmma-rQ~5g9R$v
zJhVIC>5sU-STmX`lD9=lQ0`?QUO+hv_HB(?=h-*!%Sl;5%x{5*nqhWZwMdytqTN<^
zW{E?>b7bb1+*J8;9JSgC%d0vhTm)(pIGDG2Zj=qCRX=P2uDQUNzV<R`QYr!L4S^sA
zfbw=!sWx{#?o7hO^9G*=?f&$Vn?X#L4!i~}d27z^oixqB13u;2VqHdPA!n@zoNnTj
zc0bdr2HiTuv<Q<*Ejkj5-B8Kw!$bsio3==A)Y0Jtt8lISeUpqsDuSUCHVFD9rB#$3
z9O~fSU?4CuGQ!q;n*Qbt)+-t#R5r0N&qF4**4b!odAtzfRDttSxw09u2vBKth>3W#
z0Tnm!42EV})>{Kh{nk{<#lcBNkByptZAsYkN<<mHMqzb@gj>>m0?ZGJvx-p(1&{xp
zYkEH(n&EnvXI?=gL(&hRMLT~hQgd|o$XD)<FcfF<D-%zpve<K+Eu7%m1SC+M=$Dfg
z2r@W?B5N>2iqeDVw2N$zN1AP`2=cJVul$2kwP7wOkP4@^n~4c}BfDq$qvOP@X)U7C
z1bydY8N{NEVUSmLtn2|+%L#c)7z^YgHdX!?3o<pj3dqRI+2L1<BjWCZ8Qkh#tJp;e
zKU3qeFM5D8r=BDzTY;FLG=Z?pst~{;u#1avwo`w!1|60NovoK9I%2D4ElHe!ePNlA
z(;~ght4wZHuk{Mb8(#IfXd=c@0dm*}yuv9yOwR0Dh*J24Kxq2+fFE3lN@j)}FAfCg
zW>x$3ZD@MYRZ;7rMcmQkfy1Db$((6MHUpM#2f2nopbVT7N?0+cK!T#ujUl5=R>pfC
zvvi(GR3XL<(3i2{vYk?jk-+bQAy<l0h8iUB5XF47E?2Oi+K9Ddpv}W}|M>a+qf(5n
zA>qLyNgHnFHg+k^RcjwcrjEDb)gH9d)#kVMDCoeefz(!J6bm(C*Dl=YfOsyVT6iJT
z{ra17|Kt_R-RONCqPxnBGTmm%>-cAW$pvcBJ#-(Y-XJ~UUAE1GwZr_>J;l%93KH(1
z4u$Wg^uL89K<Pq{@ovy=hY#d%nw~X9c>5%VW=YP=m~j7&^qd3m;iJyhmJ~V^P7C9r
zRvF$tHvo4yXIBO1evHDc@H0Sdts&sZ6)rN7-$)RJg@klSxanT~Kg*jal&CayL|Eh7
zfoe=a(Uv(9El@}nZrX0}4E+1xPJUjePDwNhM5p&t-`Hwu=PPD6Xj0NT{tcIzN`toH
z?QYcUd+0_#>8osM2`x?{$F?{#g=8%a!s4u`#?yUs_rx5$yXAuv(MR90?6&TkAt*XZ
z65skGym#_2?ekaBTNJXpv|W*!K!{B!cQfIO-@@#VM$(TGd=~|W(hLM2S>pJqB^Mr}
zy-B#MZ|&iGId?JCi`&NqiJ&NvsuvT)gjFEbrG0Bt4%5<vL)gSh&2CE7oD}ZDc4I9!
z#rtl$Pv;^#q$jNXA*WNs`&>ZvY?5shb+K^yyBi^3=R_RUA>jwMUgb85f9stmlr;;-
ziipy_g$*-SB&3Y3@k=|cOkf6rC-!Gh;{5Hi&VBX!xl3!ua*c$?PybYK3-8KZyq~_T
z5UUI?$1ahYqzH_PQStpd8%6y0uce8<A7S2$%%o5s`7F#6TMA_;cqT9)`iI^Hs<L}V
zXDxc*d(Kf@K_n^|v&A?(s#1d;CQDJ5f}tGN!(FhLQnNmkvQ_!QUr>>RXlc*6KWV7o
zgMn;w_w3l2R(m|AHNfo*2SWI^X29}!dz_K-7|zw74X=)uDG(qN>5rs6Si0~MudoXM
zjlJOt_F%5XG0B1Bc);638?TQyXRGm8;OT7x9zmnQq<e6-{j&ch^Dp7pOUFG%Dwv;7
z<NIhNXqE}_HEYK*)kwT_`{poe+M#$*(#)g>x?9J^Sr>XimCN`jensPsfhm{hk$MP^
z3MxRW6=|LiSHn8$!%EfAOl|cYMO@z_XuU&TVIA-0o)AK^2AS#+d0oZ@HOeZx;JJ-W
z)B&cnpagS|Zp?w|`JsoW@wl$5Y7#`~0Px+o7U@I9RX6a3II`HEI=X^IFHf%w8f-Wu
zywZ*C%2SSVJgjm2bICLn=B!7UxsCvnt`$9aE%iW2(KDX*6~|k<ou(U=)NODEP0rNA
z3~7_U-z;OlZ!b4XC=Z}#S5<j6C}+JY0SIWHz4xs4pq|k7GBxyjSHvjh*}ZgaY@S9J
zLZoF1cvL!7t3loRD({6@z7ILd&5?n=Aaf@6*g!63t0=^iVB5=1_2Q!3HBWNy51uHg
zo+7=<kI7CEu?0n6)xu9)l9<w9&}D5rHc8J5G@0+i9x6xJ4$@>Wf!T9;E%Js}gpo9t
zd<MHnZ*}?b78&xuF#xr`1PfTca*rqw%BLbC3w0oI5NiT2j$Ouc2I3?Gh{v;44l&kQ
z?GlWIc1v8N>~FVY%u}pVGA<-IheA|nFCU2v@b<D0%R%$WFSCm31)S$H(nhPCbFpqL
zH5!NJ=qvbQV8N=dxe(-QB(sIo2d!X)m7-k-cS~W}4P~vl+LvD}Vom0G+T`A)H@S^-
z^U5q#v=V2>P<j;6`9X|3^E*<c^hbl!m`r3I)FI)qou$Z*WPVPmE6jdNq{GG8rD&&~
znOEN4{(FngwA*SYfN8m?t(l8&;0}<dlDIQFimMei)Yf1Lrg&>{WS|x0`IkVym0a2<
zb2p~!68MtU+bL;{?T@?cd$$jdL^nU}Tkdm5^NxFpLhl4OW*-}2V?;Xl=n(5B1_M)^
zQnuaJI(d*oj7qMN-*6!BHDML}{LT>{XD+s;2Zd%-1YdXL+Zr=2Hm+<<*GGcKrS&-R
z-TWqc+xC5)Iem*Gz8Z?qD2D<`P4(pJp8~bDjAIvDTi|T6cH-8=57~k?bC{(U)YfHa
zjy-yLv^GQ9n2Y6q{a-;bK89uq0&CmxGauY=;g9h=`VQ83d4pFV3MT_KI*02wG`j!o
zHNjci!@XOiCMku28rh=tWpljgE_#WF8m&;pFFx2rn4I|^nKKRRmK|H~?o%)0hT9jW
zw!&TzkKM*l)ynQ7p;$ipRgS^xA?}5(BH8|Hw~(f`zTXw)pO33B!y!ZjK=YWCw!8`c
z<IsG?KY*WYp4DnMsI4(>U4xju!`nuvw@g4yX>pjQZRd!GXUKp<F@NUA$5C57YU{fT
z_mxwcxW~Bj8Ml7R_0BK+V&OVRuIg{<qN@V!7Kl>ub5{Ii#PSQT_pbRiIMX)#b$742
z)*t3Q6rm0VvM^fj3NHT2M-j%$d>EW!lvwL3hPd6U6t!A`K62rTl}5J#MU~NMXkL|V
zDN5=>1F<{Pqov6G;n}f&KTp+aFV|#-Jf_@-j!tQDFjt*RZOv9GWBh?=8=*}yN$fp)
zfAvs3fnDus?w?a%%y|4^w-By{3TkU7zRT9XvwO2G-+9lG5Rb93zP!|jzrRzpkYJhC
zve4M9dG3r!hT$bWgc@;wyOLQ^+6Rq~2DdZm!v5$N95e3LyJ?aHRjoi_!(cbg9BDDp
zqM6AO6vWF?z8h;_UseiJ`cu>}U~bN)ahU;u&3wv5RU%KoZlq%X#p9{&DDFyr7XtJs
zBVc6;x#t;^lD`=%?eF4vemgM|!;+{;5Z;6$pI|;&qnY6%YvrRMkBY_QS`f_a8a|8D
z2>D#_sm4=qOKNK??tyl0vgAkgY|g2xYjvuEn6-kW;%4g*)K*oVegEBZ6D|k0E3q{?
z_>v^+6a#D$MX9X-P6p$e48c<xdBz7M-Y=>gC$+cA1Vx_<Y&+HtpFgnMswVs24e~_U
z$MbUN)&nRpWB6UAIUp8bRLR8gVErS|7z_|J{|UPNW$cjC#YfHc28)%-pc#ZgS}!|h
z9`gc#9174wz{n#;7d$T1R<W?w4IIfq@oDsRUyseOV9B&|QGtjK17As7ca*pY_9%&l
z5hZ?wUlgs#uOC9ygDuQUD%Gf1FR&BB6fo_cOt^N(5Qi9H#)XaLexz1rRps?il|<Ug
z=_w8#oL0bfuG3vn10@!oP_lK#oOmBWZME`Q2|$nOYT~rcq0eeg+T6NsWuiC=bi}5f
z39|{?XWjbnDa55FSbO%d3!~$_r|ci5U=qQL2Ej4$tRa4%x#oL|{E{%xazB(DdhMvt
zO~TP#3m-e;<#ma_8et!Mt6;a)+up)9l~aTC$o4ozJ5f=oc3Y#)Ll_i0EKQPD)fuu|
z*%G@T$nRJx+`Wwa@xT(htwD)jQ{IgEc5=K!*`v0uDtKhL=!n}{LuFM0lh6ss{BD2p
zZcX<G?shMj_okd1HGhs~!fq=>41!E~L?!YY38JthM9+_xOii9pSV=0FB6d&%kp1St
zyK@%^NH+<qHl)bj#7)AUuQi&sQU1gMPxw%X+HIZFL0{gSHR?*j3E-Bt`;ORFszU1B
z*4v)F$`1QPQ)x(REdT3=vgU&EAzb5Jj{PA%@Kdw~X{X<Qw_Dx1&oDjLP2Kg@uLbws
z>zEyw+FH{LLf9qJT2c~-b*T_hP~RbajDYwIgH7>4WcDt6H44t*pe_*}#gN+i<bsQJ
z5-&$hD#$Ym1R=qBj=+LdC4S|xvW+^y&SA$SS!w~`jrN5(o<4_J>RC7t?bz_C4tX{%
zUerNae=~L5Ch;)vE4=g~?Nqz1rnZtIqm`r+z(ll&U<UTmBN4T=b@o4JA6B+eiss_k
zk8+ArY0+#yNi(qFb6A!ZZ?*D^6!$;8Ry*phBs8K;Z2j-o2U^&HZ0*R85b}3#VV8p_
z&u_O#&#z;tt#7|{#%-c=Kl71{l`QIbYe6$9Kvax^>;aIEe}{9OccDbj9Bz7U67~a-
zFDU8+JZ!63L`#<Mu({IKf;?(#S_?bOgi+11Y)~bri|tYy7JqZ_i2K4NK^vhfoZt19
zdWezd&mK6Vz1&%-s}TuuTO53X$0!jRp}l(wNBn`Ta8I(lR5qfddc8Z-Sjj-i&}`?6
z2eM#^7i5kC<#*Gu9>`j^*!D0f?p<rOcCLvota9RSSy_B@%&KD)YEEkF6JUn#DqMby
z6(=}zajq||`tcC(F22sQ-Rqlf>mpa|OzIr!iwH-Vy3`<-SPBZrV?ljaH4v#ySFAhd
zyE9o(d@rd|41tVl;dHF7WwOVTp?l>AT@L>N9kQ(>J<n7%Du59<CY?D(`Bf2#Njdg~
zxElw#)eMVR^luhF+!`=KE$qspJ4wpnEHSeyem?B-?&n#sV(b_D0>UNe?ug+Fs?;+c
zQ<JL9(76TEs+Ds4HJC_sJRX*bxHK!380ghe^6zb;dIk@DgxiIfdE0G_J_QwAU|eXN
zL~V_n7)YV6bukVw&8tD#^t?Jzg*4a-G|H_W%7bWUyDPJI(!7VYw~H4}V5S0b)~5gN
zhW;|{j_LVI6-ltbrBCK~af~1`Xwz9AISca&nB+GvM+IS8y!zTJ`w@Ooj**}~=qqV*
z@1>Qz#J#T6-IL0bF-J^()|!e+8x+lMtJyL0)x*mHxr`y88dy$5g!w>KnW@ao2ZI-#
zG|L`Bs*Y|13cxCPNkAMAi<P3~@z$_ZJNC5`0~Wp4y3fApMvYLp&Vj1!Z0?d<(E;md
zf5%)_G6`fPX!AN#7m+$G+Q}EJ(@;Yz_(Seur8vk(+2^EY-pSC9B?uLBa_{bL3ONT1
zp~z@69iAuVOXmSXTGmn1f*zUke%U!`2YEe_g}8Ix1xy29*&|uXGJ(pIi&ihFig|t(
z+9{vBjK@_wQ6$FNS9{q~TSK<}LwHWZH?f;cH4woy$l%WWsiOQYW;HLvv!lqDN-`q=
zyRBNw54<@W-8P@*P`wz1`xwTLab3d$*;0eu);DBNxwbAKacIj^Oipqg5>~0byY(up
zYak@3tmN6-4DN68+_cm3=sNE@Y6Pbae+1)$N1EB}QP*iRj;?Mq(;p31i<mQYRC5;d
z(>B9I0{v=hYC(hPrCO}jR=wL=Ly$w!NGR2e0)|0H2vm}^)2;Z=Z8gFc!qUAtDT3YB
zS7bTww)#N8k^D*?xNC>kO>JG=ZumzYy)~k#&<D!5SoUBIhS)}Oyi&W!Zfg-6ANMeg
ziWR)6Sa!=Sr-yTPTXje{*p<He?#|THXg%$u(lk#!ls#_B7II9(^59He^YUj3xAcF3
zbtn4kC7(^`FFQ0Fr$3Y}E^jj1e*ZzwZtLMCYn?#|yF_Y|Qm7h{8gS?k{~(R7_1u^%
z|FG3+na=%-eJCO@1bm_;g&MUre=&DkpJr<r%}}$=db?ajl0LiAnH>*OTb(C1ka;WO
zsG38@-s?n5O6MGPY=Md#2sfX-=Ny625-<O8mj@-&Ia@W(ds%n*7>9(j>b29ziijrP
zH*$OsK2H7}S%a3cl*EU@6w4<bq{c7MQK#Q#=v$MAvoP+1^KWOb?t%{qC$*JJZlJdP
z5kzy{`&Zr8&HbDW<4W=3eztB5FXBzY8WD?!ze_Dp8>fA60@;22;-k&;PQHqj1zRus
z;#*u&IvI&5*$8lk?@s}$JOgOu;on-H<5jA03k&Y4!<#-{hUYZDg$8GrH2y!!x{kr^
zmBu4amr{z_+bj>YQ-l=Fh<*tarzbd!^qRO3-kFazmvfcs0syr&dxFf3+OgNV*NORX
zb+`Z$HEMZ`!U?vu5%eNK>?0Mth??NB3w2t4eUj_uTH{!SfYXf-fkCk76&qyqU|CK`
zwpKijhf;^OZ6VtbL8p$|DazW!Mt%jq1hIAuvg;)|F|C>i*d1lUt|Csx09|%BauJlI
z(y#*#{qox}d@U5*yA=ov*u#hxri_^r2FZCB35&g8!>S9KADMQ)`gpD#gnnj-h`Bo&
z7i%FC+tM63ij5|>J9ie43q<_fr1MUpLqQ4?5Y;Ug_^t4}CrcOflpasu#|>Y_<BurY
z@nAb&Y3P^At4y*+J3fh>V7YeeZ^NSLW#Uz!j0K+D^qO%gkDHYtentWnz*7(`F3EyM
z`}x#}F%+O7h%!{b1ghX5XU?zUT;BcRA)<sBWla=8$(5M7XsXyC>bjjVaN07eRg+29
zktXwGB;730M!@5k!jL@_lr3{dCfFoCL#Dwijou^-Zl1Lov_G~G$aaB%$kYiu&l#0C
z=H7(tw6{)L?Z4}D<)sN>Xn_MA!DakfTMn{7F2g~Lk{ltX6)ZyJ0im+^)I+T#mBt96
z#DwBp8_t=8K#E@^M*bcZ1q=e?j0v?hh^UM!&XlOmBgoSiF7H0@KPJR3zf(~}s)Bfr
z(6UUjbyHDX7DdV=hMI4<=T&=Ks0d0rp>hp{Ubgl!h|SVS1O;j^R1Jm9d%_uul$l>p
z$yGKxDwDHt$~r6z0Lp$K#KLt{G$At5(x}oaU`0>_y-pF2JEn5G>g2r65<%-j@w7zN
zPlEO<)NojuD5BQpx>STe5Mn{Y0K|Y)rNFNXngAT<S1R^UH+Ybvkq}RT6E%g^9{`0M
z3N3faMIxet=iIiIQ0q+WT!)3IE}C$nKa!17tz?^%jZt?--Q!K^4-u94iT%POlj9(i
zSzw0*+>{o+F6XyRz;HO8_UYY3)TQ{aoCQmyX;(-0Hcoh5VF-1dS=m-xUD~o1X(g#X
z6wTgFx($Z2wr)wt?3%-v`#uyf1_QMgvZ*B8RmLOBZg7%;u~vz@G1NHsgnc9G?&D|!
zz#cTurFRaBWL8m+=c4xfs?762X-9-r%Oo1M8eejytb>JOjM6G=T<lVA<1FG3GnzDb
zbKw{f&RvimG1+Knw&YT@JlIjj20yPF5Vv}Yg>xjUGmmZJC|8g?LgY6}wJJ@L#)1S%
zZ_k_F!Xh~_3FA5|R)?c9uAu01*I~(SiAD9d;ZU`mamT*D?bAe92N*G<TNFo(BNtk;
z-E1>xb=$u029Mydwq%@u?8EL9c=e!3e8t^y`}ihZ4kFh|5wEF7<W&LZ0wF%lNhTOz
zR`ar8Zd4GZ84Qjw-h_%1F!O2Bbs~=x)*TtYq7sSL5THdz?Xu~e@Ku@(+0IiQE?hMV
zdPW6B<WA$eM);1DoUxq87}ZPK!X|jDAdt3Cnz;9ck{H@%7S%+=rS}*>4n;{eY+*>5
zBilqXU=yu$mTi?zq356+be_K`x*{ELc2R^r5K8iB26z+JO%PCaFAl)`^nz)piJtmy
zsDAl%xb@~e!cWCS$O$~w9KXm%;@ovC97L6ODCjbv9{_80oYGvM(5cJZCNZH-u2uxS
zm1&J^0{gc2w3~(5B<ihN0C7e^!+>VPHg^*EZa#fSwE^&yH2VUK;EKeCraL7+c7}Uk
z=Q(=bJzY^!gMsRHAaJaNd*WVjV1(LDb*j45fq>?DnJm<3yX<9rs^d{$O*DN##IcJW
z&nr#Cgsq{`z?&J(G~6CzhL|D-m}$iJV`SaK;`_T57?HC*qILK%J5~tMsyFOLKgYW}
zGWk3*exQm7*xrv;oGQt_mUlX47=OB^7P)ZK74?ov!PhS=skqLykT=azW7Q@PH-kGp
zV+Ub$$$)j}ee+2X(S;8{{RzIL@#G<&bK~chA|ANNXJk8O*(xA@17lT{`Y&B-W($|J
z7TveiO-?w+f=usbWetO`Ttt~V5ax)REAL6@hoSv;YIf(U=3M-?*n2(>qvl-TB)Zp5
zVPdcR-VHv#fefebO=)X!4x`j`U*Wdzd5w^_UgdkYz2H|_HNXUZE|)P1fT$)G*f@#q
z(2oZgnF}Q3Y+7JXCaiExWbiEVAN6_xkxaPTg>2YkvB{M-Q1rD8Z{MF_YiDJYT(kW0
zLg&l)gvQT8k&}8rxc|HCNL+JD=MNQ99M7ixm)FvfI5I7kH~_b}{tBn(x)aJ{+UvO*
z$4GFhLrwk^gdV?<2llqq7w6u4I&-hQWhQrj_v+T<6PGc6P-S>UohQ;d+ZrXh?1OIp
zah?%D`0sivkA|mR5hwZTNKIuyF+-rWu$+}gKT)`N@%w_m`LP~)lvAULmqQGV1U2VN
z!d7E|8!tBz_Ef0fU-J}cH7Y_IIfkl2u9pYWr#fwqg*qM$9yyc;c6>IscW&f~${9j(
z`_Zpw4{0{zX(etMIx)Ysh)4fC&hg<;7p!bMXvx_jTkCSqtX$Nr`3O-`90oe%Sl)GU
z^iN#Jr0}sc_WmE2P!|uf*c>k}I#+)$H2(U^)rE5_Fo_g4Qw2&=q83{pMq7OiD<W{_
z|CUd+K8{1zr`m%{R7L`geD}T&s^j0`?J%n9<wbz~rLqI{NZr+$%=B;M1RYh(Erg-j
zZt1M?2HKq~{HNI_TF4%{gw-RqPmz-Q{n@BQg$@LYpXTb7e%`$&YxmxXBa{5hH7*D*
z`}K@u3A)_X0ejneo%rGC!d)8fuFzX1P6ZhA*HJra&aH!Fyz?rB4~G+=Y>H7WF2R`&
z6d)>^<`ccdVU!ArhX1?sES0>DA?VodqenerFN$j%DsX&+f_HDRllc1~F&!ge>d(RV
zNABz9f<x*usPb+!q$o4a%*&cZTb`oAc(12v*WqyIQt{~-VwU+WAU?19m`dWrWiX2L
zXbRqt;nlKIeNduhrw>>G7D!2Yt;8!>PzR|RD+t!Ai13a>!A)C<fTDNer4O&h-`5VY
zj(V+gGZhnc&<nOzVX2^fq{LpEUsr6ajJ$Pu97h8Wu9j7qxyUn*pbiJ>#zh(dk_emF
zL0OMG-@(#$oRn5&%V^7R7UfYJV|e3DQj#hEDbkkM30DM$0?GWeVQGjo{T1Jonu|6a
zCRA4a`k?Er%ij$!BrYj+WqSC@KjF?~r$lVgVr4`P>%*YtK9<8UFFd}wUNt4G8>dNd
z!HM?@X0UC|M+N*evjz7ae!fA~?Am-Ma9?1LBm`o!@xI>QV6j0dBofPhffq(PnQQ7G
zY48~KFqFzG=$Kg>BfLAP#SIqsq82y=#sT(9Ytw0p7Bi%~te6XerW&VX{6KlVs{IIb
zyRu7k61xLv28%QEE}Y;OyBm+iKVM@gso165eW>Y?B=FukO^nwj|1dLVnj}yHzd2Xo
zGB;%tyV~ibGpTru%?anN14RM?A%gQp6!N!-fkxt4!?%NanC~KIG|1KFgEX)sv>U%w
z<=u@R!EsZClLt9Opa(<6T6a|%7R&vUGfFx%QIGx}uCO~ybASXo!D93^TjKV*{sxFb
zkaMwUD@hjx#hr$Wt#PIydTnkb_z8->1A$X~(5+5z*Gs+CHJYF5FFN-ut#-A6<C=UG
z<uHj0mG?aGE}R#3UV!IpWynsk?Qb6gImsy=$?x!3URdwA*t>ha?YvZj1DYT6eDs^X
zUf$@6^2&KiMJ>g*q*P+qk5EHV=&wO-ZMk=nW`(aPDMTPih|j>U5`bJoKpCsGMBx=5
zlvfnI4v7VeDEZC?ie>bQvP}5Mg)SC7Yax6{af|Ct!dIW+-T3dj!NNcs3~f|T(+|o|
zjC(t10seO9z>G1j_odcFVB-Y3aizA#`qW$-mDgC_5Q=2x<q&5>fX`hnx(~me4M=^b
zqx}7&l2`U#rm)^|(Zkq3VkzM=HcNNW+$GXlQe_W?dsI<r)}#hD|MEkrRGa1Dbj7C^
zN5eVu-VhIRK<?%{Lkzm@rGhBCms^@*RB;0=5irhS%ii?D@A+kXrKB4%Zk7LZs{Apj
ztp%#)y1LevpQJNuNnjRr%{_8uro_VmwN>>rzg?zmVZ8Z2EnnMFH*KS~&Mj>>f?N7+
zH{JU4=<Y2Kpe=*q#X`nal$<|Q>r3rd!X|b&2(jEa;+kKZVVrm@Q^DP5|H!#7FyzFG
zq4DOA5n`pqj{J<UmjljrcN?qY>+fZs1c3-8d;9B{L*LCa`!pnKDuv}j^Z>|3>l2?L
zi>r^Z9Q3Y~+kgZkM%nEuX}nD-dLPc%NdcbKLS;_TSaQ(oYDtoBJut=hhp1;7{nRIq
zR=Z>=&HiTRiuSslZv2yXAU;}#-~)NY4EIWHW&JR^@Ve#^=40QhuPWBSA(>Y>z3Qgy
zLmfI&y(a8ACPr4K&suTZSuUe1-$ER-H`LZxD>*&V`@81cOSJx?AHbJ7ymanpFJq^$
z?tGx~?rm9FivQ?lvd(Kd?vZ1`8qwak7Z|z-emzH2(q`1NlLgr%(j)^#@BzIum{}$2
zWoeRpUoNVN`MstyO0ygE<S3{VisPBdXtz@k%p}ZRmYb*P{zD4Ns~EE+1m7Q!y2kF1
zeSGQRO(f;Xf+6`9n>IcLIWNcPkh>Vh#A;Thfzf8j-Nxu7YRrxtnjm`Y$nV7fiK-37
z^&YXrT6&HlxGZ>8gF%#;$v_J%N;&vOy{r*N9IzJ1iR7V}jM;LVluDbGMxN<MbZt4?
zIC36YI6Xgf6J;s26+nJ{Fg#mnFoH^L6{XpLq4uRh;JC-U`y0L+)t%5>MlmA6iYjQ{
zZiBI4WyH-%(9eYuGGgV$0!c}1)qtG*6oN;ril9|u2Y#vc>Q@qbGd4wWVQ8|3nd;j?
zNE-NRU|f)}Eh5T++KPa@RhhLJ1#Y488cMFTmH_*tqK3ey70=Z_brT3Reuzm2j>H77
z&?ut|{Y-WPlSB0z+)A^Bm~w7=X_f>OiW6sbPV(;$j8*eh>{6TYk(6<N>=!l0=OP!+
zqgmD=D0~+JF<ZJgwed7+Tk=-%d1wR)#Pf^N@pGJNSzYit!2v`W!JM^EA^XCF$f{8W
zvuQIiIiP|=pL`L9@~fIIc7kq`ssnb}Vxf~lVj4tt)n-Uh157=HD9@uZv~nsC(H8^k
z?YLvvTq=CbdGf0?eu4SSRQyS@c_7=cjFOO#t)*Pcn?vBWIcAs_#k}?N>!a`zmry<1
z+Lvsi;1wjfL)qSSpCxAYHW6Cv{$|XU_-s@ouG%E+v<V!}q+0HfV|9<I5{1OJrQg@M
z+G0>!-960FnkRGKs;%HFmqd4piBG&xwbi{gu*ZBf%S*0}+7`W?CDiy>6TT4JAEb#_
zYHPP;s9^F0QKHbpLDeQi+4goEdWxt7e&{-xX5DPV-WQ8Qce{)i+oDC2NogvL7an?0
zv-y6`cWtx1wf;XSXb6a^RL`lWWBf#UINCQH;9|RTcy-M9;bxMpl1-hByP1Q1c`drN
zUuK8-?q+$jNU#4At8~wKw^_c$v>vPNA$bx_$vjp>ZDqGLcPqdDJ(ftVYUT$yGy98&
zCt6Qj#sp3wo?nY3yG1HV*-&1ixa@r{<0}p!Z1WD%kI`amv+e}-Tca$HW-yS=tS~Na
zxcQHLf3R<BNDhK1qb60CL1FuYCc3*gKkx=GY%{cRYOQ3OX2{Y+JX)_2q}|plQ*$U6
z$HLh|Ukt6YU*~nzk#<{^Eo!Sb)iba*lZwC|D9k`1+HNb^HkUrjamPQWR!LDvH#W{5
zd0$>^e%WPdADAc!dnk0k5F%=8%Y8|^ttZ(1BA{wWjrf}s>CGRDe1D-rjo7<HdVU>q
z2@xo@+IsLRpVZcyUf%04A~Fy<Fec76K9l89yRHB0FQ$6gGnK0N0^!s(zMFzUCBY6>
zn`VgGT7k4QhUPS-{K~6}tn-SPyWh_)Y_~Nq%y;5{D;}uH>g0&CY?Inbr+yuoyvKy^
zijp2+JarDm$<<%t6skC@VU*Gakb^yD+OMVrxAlbQKaed<e1o^tTdaSoF^>#UceF|%
zK+c+<F1v|#_RfNoVdWTL*_OR?|B?FDZfiU?p2|ER$!JmPL4shW6|E~M&#P)`O)jL0
zOepDC0`8oW`9;sJ?7aFzH(5g4&zy2^ucDZ4TecF(ldNb!&SlyO;<YNiSBK+Nl8g_p
z#W4pnffPY3b!%Y6T&n`oRhKMvRct*HRW`8@E>NPj{Gx=Zkx1`cPJP_MFw`XmgSG4k
zj?b9MA;uR3Nm@M;?KJ)<fKj1U)-hfIUFL#|l%2I&tLkZY^xz{xB>pz^ppM*wfovBj
zK{PqUBV93$NAE;aT@qn=*Cr=?&4Petz?k9Z*ddDg*DWFeS_a+vt^DU(>GNZ$`qGh^
zz6xaP0+wz(KNVaI1nsuQs&#otNMX%TSW=?ZfobbVl^Ku~9__mf#X?`05omAHrnf{}
zq`Gn<q6<as3UWjlyj^R;M*PN}8HyMPmm#j8oYYvV96F6akh6t|U}3B~Y{ksm$>F(_
z3tUdSnJ7Fx)l#0=k>5}#vKZZD6kc_)Or@E0C@*D`)~x2_T*+@F(96Yvo=$4Dm@Jg3
z74{PQ0M%g-!5IU|$Y9&D>aaxn#D{aj<Nx2@{l{98-GzZa_xA1AZ`$LTH{-FHSYuP&
z9-9VP@Guxn5*w=9Z8H!DHO53NYrzAtmLu5JWNo6!Lf~{yV|NHz8bZ(@S-TIfwL43)
z$kMWs!$#!B>#X==HX6J^Yh|;m21SS@fCe_OBNoN`{hq42@4bFMduBXio6qTfw@#fp
zb<U|z{kV0i>fSs0PHS`;j{U@_Y&AnS#kS*UxE>8!UWku6<pS*FnX=qI?Bi#QW20`B
zeP2!-tL-9|0yX|xxDwx87j5cyHnB{OC7;(AcJY@ZL#R{a&|%BEk*8-FTR)!}v$_ni
zq#M6jqNXUezZqHXAk?-##u?gyWv5jqE2gz9x7}Lq8|LU%o9oF+*pq9u+A?+PP4TjG
zw>2N%8Zx)eVO)CN6WaHOo{evpJ5^pAt$P1_KD)UVYxjHh<T`jHs_n}U$3gYk_<%-~
z{!pBY^_lgPuOHv)o;|x=^5-e?A>l=PNI0g>9*>u09H3WsTjQ)Peok^+ir5B@3^i9`
zf9joiw>56s#KJwjv#*z5UEFtJ{cP>;_-<>>wedCWT)sXK-PY|q?>oKKJ~%M8=eXln
zv@CjDadoaeBpk)fzjfD!m1`jvv5&v9D?LXK51BFRjc#ifC+cm(=`(wN8DpEUJTu=|
z^)04KhI9I-XZ^L`|Hftey}Ye|6Q2i+FJjrwnU4#7+-;5Tsa%wJHu++9f&X62aqH1o
zXVIQ3+4FmHnH`5mX650$+nUuzx3%=Qo`@{t-PV|QwmtPNj;pav{~Mn@HFjGci?ZH-
zb|aTQ7rFb+)A6Nn7iQ~Ezcy-XDLKQmw0(}Oq;h1H<=olz@_YX-55$o@yRDo5<9z<)
z=9lec+2~@@abfdc&lV-_whn9XQ#;vfMpw0EgH9Cov^>9EB|?`k(SOY2LYEJ`<~q)A
zdnq+0%(If=i&&m(=RHwv^xHo1%;{PFTH|rsX3ktr&tAW{-tLOuI@N9D78GxC=boK)
zDf#B?wq9w~<_i41pKNzS=CShoE;B}#w?vlBxFK8HiaAl0IcH?7pL#M5bl1OPV>Ue`
z9ILDQ>@U?tea|Z&DF5qEMYccv+_**OJbOs@>^50#{m_}6yRGGG-w^BNgQYzryxI)1
zkYhuZ^>cp|FIn9if8p5tM`g%k*zOR&&A2lfhr3*e_&h~f=3~5X9*@xdkfmjP+pq;}
zwSL?0-_^RUZKdxNb3p7&bo8G3vh8+SaQfN!9qTB)g*?iJRQCMt&qL(tcu4r2(QS?X
zRq6AaQ1hPJqh<RW`^-`n&t~3}hR33e%zO7+;zV`x-EpY<ug*<vUGLvM+br*mA0)nc
zS3D&5?3q~ACkhwJzj{R(7C-a<KwOrKlb!85dq{XI9)N7M#qwXtNdI-iuG13l_@y2&
zN3O}+LoVZb93%FI+`h^xah@}t45Q|ZZO%R;-LKDM<ER;}Q*m96&Eu4JY)<ULt?+pB
z&X84inKo;k%^_2c9~H);a?6PB)z<KhBIA4cBEB}di*jQDVh}H5=8PX18bTK<<H4ah
zrF=`~pT+V_MNGrP%b9Yll}jzt*5O%S@RXrvHxzR%D~iW87jXq<CoH1%J7ImTU);Yr
z+>F^tJuJ3a`aFN^R@2jGI#kqLhq;Egas>_tja=`!(?-~gznYQNZ)@bp3AU*lt-TMn
z+*wqgb+qu_S)Xk=l_S}bygG5BFw4?D9e;iNWw&+XXJ)ZYMAtROr?5Ldr5!a~HS4HM
z&tuxD?s8LF#u2ZzDcXBA-*oy{#x?quGF6=)ArAh2SfA5&cWj-pAJ#s~`^4I^{9@*g
zD`w?Xck@Ot^$A<nYT5q!Sh-nIKU9)W4n&wf+nVv6P+PNh#`nd#Ov$3_@P)Fu4(lSX
zLeyGgUA#8Nr=^PM6t*&QDq7H574g`!bNjmxhuR3a0dyJ3Fl8CWqWE3YrnIAn-O-a@
z;MA^NmB>Qo<8g2HvqPJgW62X@H;lI@_{K>m8q`{{i1_Qq17VDH?Rvn_^^5nun0oR0
zzS35=@ApkPI^jmHvwqm{Vxb;fl+DeoKf=v<)P2514|&PMa~%ZY6gm$Wr|KxPe~x}i
z${B{4rj+A`QOyeuhwfW9C%RvLV#rf}WaCnP{;1rFNB(XLUo)@mXZSMtMAt^5$Zq-e
z5RH?f&F<}~J%pP--_`Q^7=JdFuKTO8mjBJAanil(H6MVBZfm@4ef@fu$-^qiSca~>
z9{y4vj8*gDSClKyePm-}o(G5LhC3JCh130AAG&M4N3`E5=>1dl=9Ktw7rSb_H*Z~z
z2F30=e|%cQQ&)eQr9Ae^J;kolcSq{(k$v%8%3KM3PC34?%oQOs=9;SUS3)$yt!JN@
zw+VmoAI^sf_k5_-e8TqT6MtzwZ19=2i@)|O_pkhGKQmPOsfTJN9vk{IZ(TeS_xWba
z-#XLnR2$#YG5@A$Py9yX@;A<Oi~sW1#?_U#`_}(#y}bKY96G=GduyLfzLwQY?Krl|
z8cX_EIk&#}@BdQSe)O-G_)`8;x$tG}LtXi;&s`iYaJ8*C%4~~qx{-eHYU#J5u6gX=
zO==#`Q$4WVm2;b?=Ns{Z9DVl3`YdYI)z6V^+4hIdW%T&aWtLW54Er1zL(So8Av4FZ
zA(vrKQEf3x`5S+HX5KZ)?1E)6XI|SLA*-MI%`aQD`{yOHE*|;)SIuiqo-S5g$R~@B
z4N-0Vr_sNS;bQsm_}t)FZGJrTT&s3sYF|?NTx8EObJ-q_-J?G7)zNK@kv{&~yn%iE
zck9>4e}9yfpOY<bzQ0@VF6R~Cc)yN^KsKJb>(<pA$x5a&hidQHjtdo;x{|szFPF~0
zw%dG9JzJKuhwiV@YoE6)t?`kykH4vuIL|*O)R;c*S$%6jcgzgOOr8!M`?7ty%=3pA
zcaEu#eR->Dvuu1tIh)6w7V7uMi9?1+>2f&RJXLdebjWId_BG!=Ebedb>Y+Vew(iPm
zvrpQ>)>>5Xws9l|wM9P=7XbE!wm$Zy?n=0lvu9aP#`@X#%IK5)(6G0bFWY!c_YL{G
z3kQcsZcqNiM!A3E)lu4Z7n9-$Gu>?+ZWZ62{n+tn*-I3%7usiC{kW|SRmaK9<;AY8
zug`nV!#$smXXacbCk(@<+hYC9FRkXNc?YSke79o4l|Ei>#NR5!EYB<SJN3k>$WXiJ
z!`65THWq2Qh)YjHs8b||H{&n+EA5oGk3orT`o6da+?P+qNHnG;mU&Lf@yxm>Jh*4<
zWgO|(`kK#RY}9DuA{w&TD#OPOqWdwceJ*GVq0?f^7|UHSKUzGV#<uB)zkEa3<aL27
z@dZg^VMFHexz%|;jFxioR2Nrnc7^z;=7)cF*Z34Y(I!<>{@OT8ZHK<~a=p)l)%s{-
znbN{CzA2y^<HO+Yay28DVvSyn3nuZsiQ_RV&yTwy&&&B*53Rf#rYvK*bG054;zxLf
z)xH%OGG8p#5Xs@8p~jR4%UbDU*ssOQPUtu1<4Ej8S>8~4pNU(;b+wE>uW;e=9`o2k
zyWQoqk+uM<)IMW<xjUW$>1P``lA(`1I|k=79?wn2>w5XA9Lb-A+_heFNxEqD@nO$)
zeSG%kpQE21I(T63zO=W*IEz|rPf4>Wa<WF&I_2Lr+?cIWA0Cpwr47c^gc`%DwkhF6
z!=Y*QuI)UZS(NCew9v=vYOM`P?X`~asB9zl*m_?ypykWj*LV7Ikvx=~>8nO&<YX3O
zH80knJEWlXkHtc?@RJ{jE7y4${vXHRlX+G6YlaEK>;IOQYvR|^XYY?|2b-_jJ?V&e
z7t{J5DSbR7ydJ;FIEikQfBVFCoGs<95MgVr)a`$_z8Ssc)Qa$#?s|OKt6RAZspD(E
zXY8PnID1~)inoeS+}pQjf!BXG-vwfiT6{}<+v3oQRoPum8CLc3eC&r`6{CMY`apFf
zcF^u(OE_EpPUMfDhbZ51X=q~og+Axo6&|~5RphSJ+oDHi$&z#H=yRqcb7qDN378qP
z`8EDpLcBiud+&<=W2AlZkIKcory2L%;*ixI_WbE_6U=$f{d#=AS^RqB;;s+Q=9iy5
zwUMQ5W<f`WMSShYnb%#*FE5I_tsj}H?JnQAr_5G8zs)n(>xX}(%%a!Rmsqy7hkmT&
z{jS=YoR6*5tR>sg#ow{}Mc<c=?0J{(_^V~@vvHxY@2};;m&N(Av9*3~cyn#VM43C+
zJ04n=d7pKjy)Ul$ZpZD~S)4Roez=QgCZk!|rFrT%qqHb#^`j9rN3v!A?T6lw(W65j
zYoW_5QCvG+>~mxcHHXtewjASxqX${k?Hfb(AG5t1AN>!DxNm)`%Wn4B+!^DM;E!L+
zPU>2U#OBb~7|vglA1#iV=2_ZFLUcX5yklB!{qCvp;g?uDW3@HTuGhB$Fstq3CU1Wu
z%Us<qkG}EgJx$KdGXIVai`u%a^@pQ-^yd5H5d0gb+adlvzgcF_{MTix=IjX=@4CA-
z^{Go<{=4V^-Sv3f7rb#MesAT0_)da9?iR7p#|%Fbi(kriJ_o-S^F6;h--^PH583>h
z*|Gs$Mm`VW@i;qK25b4+MSkeD=H1pI{HuH8x?gOq8FJ~b#EPtC`|YRR(|-1%rJv;G
z1NYv@&w|7^y8Lw8zhkkMt%RsH_r&tyfBDAPtIw2oMptuOW%rKfOq<!V+e3038DeL>
z+Pba(;$oN20>>{x4;$f?(`B)YeeRGjF71_4Uwf{PpIIvNPe;zJ565!nk@;5qtkI2E
zu3t}#{MC;=p_Z?1N_!Gt){$gdAC|n`yBG)}^}uteKKGt>3_fwAbB<EuuYu&qu&Hj8
zzQto&uHSCh{_}OUL$2?dWypKt*F3nk#^xMxd3gx20WGHZm~_A(t{ui6S!Tm`{B%*!
zg~*j(CN!KDN3<=}?pf=(-D59re67zl87E7#RE@vyAKMdW@UKeUq4is1YV2o`u+~qb
zCm3#)Ymw___U*ep*|Xc)R^Q#VD_grKJ~OTEP<+1ORF@^r$JzTf%-1*~xA*}s%Uu3F
z;gzegJ~!nqM#n1-(X#bO+a0>yBQJA&I+QG<9nCl;Yy2H>!6dfe;J+TP)7oy)V_x!+
z=@!<OJ11FD?dI(@tY4iC8P~Ul;R|`KIrH7M&p|fe=CZ|d(YkJk?t9%D`=o8cM!AvO
zZ{J3?^H_FwiO2G$(5wcj*is_YvGG%e<A)>5@fq(t$Jn}I##KG-9WT??@+I0^b5gcD
z`Ux9d^c;p&6(<%a2z9l@Ipdy?+t8qrSLvqu_cUrx{*#ZyBJ{Z!ebjk5@5T%lFdyt<
zi(E|G^1k9WN;a`|hGJb!?f6K!D~?g|9d4QbQp=LD77}IO;dq>O%%E)z$K-jwlb6#L
z_-sEG@wWATcI$N6xyawr^O|}4VB+rwemh<Go)b2!|DPX@r?{dEcqN`JoUY|B-w>rv
z7y0X%`GxY0@hQiwB*X0Si$f&7Y<Pc|wD(WhN$Kyp_3E<NK3z8RBdi<cRXNjz@>Sie
z{Daj6;hpS5Y`%O)i*)U^_R-P%aKyVZD-Y!+_hcVul+)dcsqrmuzSMmi?P}5qBf0ds
ziS(I2D?CxijJb3*bC2uf@~v2sHsQHxLUbA5^z7C6h|N9gA86ZQW_{z+(a(sK`nu<C
zM33?namv)53(caA31{9O)&5SIFaQ3TE_yDl$ox>_*8HE0?a7YA1M&3j!%xTOU31x{
zuj`3VWOjR-+{M)HB!2O{YPtFw@mTL?-x#~=$G*8W@}qI3rTgRft-A?uk;|54W=egi
zFY`X)4dhCVZtH!~vb%4^>RrTDiBs{e@#y6;s>c@y@4@VrS5LOrc3H#JfIdgYP;<Du
zL1X$cgFQu!8$;_qwh7U(?4y9K_k7QzLwi3F9f9mWwuO9Eto8W*=yK1`{mS|S`HALs
zi}sibhsn_?zR>PH$Es{)MRHWz?ezR|!n<BO%R3H_UeB4n?Z;<Z?TX00&S6U4%q+)*
zE}wIL=7-)=*4`amw65JFkJ@8X+<dOgYtEg3tvy+0&5@zo`szTBd2W1aRzC1#tk(M@
zVKXj5+=#_r2FO;Id8d}WJ4f1n@l?i+534V{-dTgk&veH*9-rRpr-RBO`j5Gu%h$%|
zKUX&w+rjhJtd?76YksGBd>2NnixY*GF-kxE?2x?`{&;LdtDav@c<in7<Q+oIx4`#D
ze3fOK&;}>ypTx23ZSl7H&*OQ+jc=L7sllw(T4ODhUpw?5yv$Dem2>eDUp&#jdacag
zfBJOU_)lW3pM7U(&jGDK_P6Z9NkQ5|e12bspC4&;w1<Bqw!Rqm<cHUHcCXmDL%oZ)
zrxvcpYunm~(W754$04W71JtfLY8RXM>Y#NxCf?Xx$d$}{wOw7C?M`p;ZePl634JR#
zXWUiem?tN#imYSeH0b&<_Grvlr;L51F0Z!5A1CKv-%ZKB9prZ9c=@7TR2}aau?(?E
z=P<&J+6MXbYu{q=a^+N4#%mK-rt`?1oomW<;Bd2)?i16L=m*v*9&+)271r0UM7+=O
zWt?r#<`IdTbqDQQtJRX34+)W{izVBWwJ(dSQS4z?I6j+2<vV6Kl^M;w5b^o<<x4vC
z<IKZl<SAPl#uLtaD%&&hr5>3M9LoW8s6IvGe17QQZRJRvZEmdPO4y3!?lYz3$;feG
zQJxs)SgUnw_j-&OYoBwkMQO3}qmphr23biS4G#^E9y(<;;cP5dS6;cZR)?CR)p-SE
zW6IZOq>GwcyV_VjBwR{-R;qPdV-RO^@mCwjGH>y<ywL}$d)8u%wPQri@C6at-Wr?f
zs+DzW*2ktu4!dz=qrC^#aqJ|6X<c^fyXVSkSL4%~ns%gI%ZG*KVG~yAZMV4@UzAv;
zW$H%rF7niT*%hYdjY%8xK4N{WrS-8}es!D@gShh8_TS7BTS(d2LgJ{`W#Sh`San<f
z;3vk#ds}RDxAKBwUJ;MemTY`q-gjn}UujwAp9!n+B&a{pBJ>}v@!`_N;=(guy)hrY
zXQalxg*yBMcl2j3Y^_B}Z;Qg-_lj0qDgSIJxf=$zz4o__A3Qogb^5!zyJEk5eOzF^
zF|6Kh{=~-FUy3zzNXYZJ;p`!@)IQeXM@oOOhCsKNZRG9e{)f6@-ktmE!+880<O|+e
zvyoXypG8KcCkvS|4?i`tkLz&w1Zj*v^3?d|nq8U;ajUY6??#G``OPk6*814TXX~@8
z_eQt;$FB6l58!;$K$V3Z8Q%2v*hYRQ-Y_qona!{NqdqfV%--^+-q*#1nxD0e_I%@_
zJofQd&E{F^NB`!vwru^rCU-HleF;Gfj|`7J9KFu`1nGmZb$<H%(ALGdxZC=ZufEZC
z;<gr&q053|>GS7)*8A<K^EL5#*ef-Xmf3CHuF<DCy&gTfILZ5ye3~g7KlQ%47qeU3
zcl$NsEO&qCGAY}$T7#Joq2|l32Ic4p!k(fMEW(~{>!nDjXW}M$`)q40QXTHLMrZGn
ze>xu)^25R3dX!Pxc=T=s9sZK{a@!I-8y{31uVGAgTXz<1-$TM(l-R%V_IsME&GPX2
zhAEHy?0w~#kH*d1%W;uu>j#I#dAuX$&t=sdO~AHKWSLLq$m%9<lX`dbdp{O$IA>lR
zziM08<3JT(R`qkyyFZ_KXOEoUX?$XS=66TZoO)DPEy8LI9+msfre)bJJU$Hi)rGwH
zt+3&Ucq@7(*^$dfRZ98o^R@Nc9{raw5{KrKhd5$4!TQNqxvi|2H>%B!Z`)&9QCqh?
zBs`S=<f|_1WLZ^t62E?HHe3AjSZz;!<+Xb4uMF>!i}>cPE-ozPYC9<8+s-PyDSFx;
zi?KKm$EP)FtjXD3U4PHmp80K!sP&QCQdR}M9Ff|!TDQt}8}`HI+-DObUb^^eJ<56`
zV=c@=r5ocX8LaYNik)Q~sd-{KY+Dg6SK=?$eLvn?h_MX$iM`eKHzeh2cOt*K5myqj
zx~`qF=Gut9%Ob|kWg%JJZDG#_)I~K>&ye<pF@L>KR^Ld!>no0ia$@2aO4yEuv_ol~
zmAJVd3%eC(#JS#D=wl@ZON3MHHNIu8^y`<_YWJ~7Ye_LYHuOV|TDmB`#n*PJHjUVu
zYRRuBokF}TW>^~r&+9e5zN=l9-?e32@25pOpu{@7<qaU$BSZXV?bR4u-{{NM)mXuQ
zFG{*G%@{lL-q0Q0E8Cm-z_Bh<vw=}p>ErL%a5KRA%$0DtoHhP3<lEkM{#bi@U+7|b
zmYc_{+)?WJj0`pP@oT*?mgh8Cz;^r{8=~5{dK}qK&$`m}5y`S5Y{anU$mtRjGUa04
z{OaOVrOdK(*?ui}R<oUZnw-r%Hhg8kWX5IYj7rLdVX&+b&k0@p#e}U=Gcu$^HLa$u
z#HGSWozMH0uSUFeUHgp8BJ=3C`nkKEQZmPp;VWb6P+df_Ww{2&a9H{@{ea;Q4V~pa
zCrwNlKOKL0Kck<;$Cc(?9uBWYE8}D{``}$RAr@j@^Vf5;+U=Y>%Zlb?tBwg#ZHSgW
zvnAC=+x(|$b3#l$+jZ?Ie03f-MHjVfZI|=8^(-E|P~sOXVzyP2YmOWr?vL}EE3@(g
z^-?TCgz@9zvBfOfvaJBe6*N$9m-s=n*(VaD4o!|90g0B)W2PEwwvVR~ON3eM3Kz;<
z^FBxB@i&xmk`wghYqF%<)@&wZcqsmEWhBpK9?8hDAx?cV<8l@+adsIW5*$K|Z#)vq
z(Z|0<PKc*p%GFa5S(JDVF_+`9mKF>9P^86p_CeNTrbi>waUrT*FL4T;)doN)4O>Gv
z=V2ly^g9!3F7jB(uxz>Y>}hh%mK_^zMTc|kR_vp7dvMB)H$tqj`1o<Z3osd4nGeJU
zzBSvNmAw1>UFF@wAu8A8m0bK>d2f!t?OdE!)XdV~*0L=3*svU{+p`9bo$K%n>3K-V
zCTFPaHD0<Y5{s}a<f_Tg=gTxx#*YX?wX4cwQ(2XsCG44SL@{?bsgI^kt!=X&-`c&4
z8Z*_Y&MqTUX?>2okT4bWLdrO1-kQ@FQBm88`WVTZ5;cZ9tF4cC{*`O-*Sep%YT8Jq
z-cd-peySkn%(a@!*(TJ8%;T?Q1vQ8Js3Y-&VKWM?@z%0Bi<ytNr@APh9#%-7RZrDt
zQ(GJQE+VUt?aeH!Epj#Gg-2EvSyZz)uFP1@mN8pXGjldA!gj)*j-|g4i_y=@sdx*#
z83&$aoHj%U?}2=P@@$+^#*?#oC|Zk@ZkXwfE3#J5!7o|u>3Gw5s^5yz7xQ=@%@&mH
z`Qmg`8}CtV!g@?7TlqFN+$YRW9&Ts8(~CR??rL(EsmF#mR4+4AJ~*BmN6nEaGZ(tc
z=mfZvaz2)ABbK(-n$M!;Ly}vi_K`CmZtd$b{5FOxeXVhoBM#KJwXDzLj|tJTF0;fn
zfnjSN@@IQq#1QX&LpW7t-<1H%_}iG5vK1?&MtlexYjuchkM*B?N7_ox4AGBjYc%6g
zZImA&i;D@}GN;AJlPxt~TGp+Ywx8<ZDbG>EScLct<)z5dWwt)cs~IbOOgb>ssK4fv
zt!zsE8@?#2%{uh++T_f#a~R067KV*x8oRS$e`ne6Aos@X+LSvk8nlyyE)$mda)0R_
z&EX2Uskf99ywoXAH$@H@K5*{aBXw2oxHkL1y)D%JNw?(~N8ggeMXZ7CF<~5xMej`<
z#%jGSHEVCX?QQ9CI@aw;+KQd|<lFk5Sw9~m)8(=ceEIc_@;$K>&qm|oa#>tI9JcCc
zZ-mEQ7vKGo;nvl7x%UW}mTULR<4Kd@^|>32;okCa#5UqaPSlc5+x+rZ#QF8UkPkWT
z3w2-00SWO<sI@*^YWZ~hqCmGc<aj!cd(X!Gh6D0v(ygfli#Nn4&}-@Y`~~Qb#iq9C
zqIdSTh-^)Vx8?bqqtBNNUHSA|PqbE7+wCyl?$<=^G9jCBqQWwBX6!Q(O<nC3`3n{~
z;Z{6J`Kr7Ozwz9xUR$1t4qn{I>0(ODy8PL9m20iqXQR%zcHc^y7BO=j8rFX_-kEZ0
zJZ3nb7V7Hv=Es9eH~gr=KZ*XrXLfy+%Z1FI%l6Q}e{^q?Yfd>y*p5&B)py+=d+Kk*
z^@CT%J6eQ|-<g;CtM?91gmx_@UTQ{$WxF_%MsK&R(fhx%D>t92@z!uUvLwjneM1*`
z_+(vVA2IuS>%&>jv7xV-rB#=aT*@g->!oHw<~UK<Q&g_X2>C2sE8($c;_;5CqsEh*
zAMbNgTgMs6ti#uqMkH?S)ck3alUIBFZ|2!Sh_sC%zDp)T`yQY6l;3JAi5nwZ|JSMe
z;@qi}D}NCDnQyge<<hryWa_x<W%SU{wwDjSDc-_sJe>a%O|M?~jr(TH8&SgqxKn0J
z`JGt)y!C$fts8M}5%ZjSFn(s`y|LHcitVC-eC+zrvehT+RxPW;rgLbErU`vUrUuj;
zdGW)}4=?`y#j*4}B4((u?sme{(>c!DVqtGJrJadK#%}zTu1#MoW4Wh$&yU7oe3?7@
z<MEdh@<4ogJI>o88c!*oZ-cGXQ+{pqj$WRP+>gW&zRw-)Q_ZpVUmKM?HNWeyg1#=+
zX#W#&c$&q!ixat$k2Uo_H?OCov<nU7=f-(k<M))a+%xuaj|_m(ifL7C$HKI*-Vej!
zHMg$}{S+BSk9+M(+<_hs4U4>dScf^fc4;#CGGyIZ?rfgPk*Uj-5n(!Lw~_H>ENyqv
zLGg_mw~cecwKl`h>{%ZbJ$g{~Oslm`>GJw?oHNF7k<H51#g)wH0**3y<mkGUSeq%f
z_SMue;pH3TCYh}+YyD<xMUAlw8QY2pu@;7qH^>H~+_6fGoHRtv@iUE^Q9zcS)n&CA
z=JU2TOPdhAo?%^<vfZYZWvuo6EB4Wotk=71i7zG|N?+xVsw2LhEf~VEG}BnF`RvEE
z-;0cO9INSpdA#KOU4rDLo9oT#W=o2fRk;1bfU5~FN968=j<ATE%WdhGB|l^mDbe~G
zgCQ)}mKR&><}8@w;8}<C6TEIsdE#fC`Z3-|30)L4g!ti%sDC&N)J(cCq{p`~mmB@i
zz9}V!H8Y<i#Mk1kwy7?nwJqSmZ_KThJa*)!)yGNUtlY}2?_9JpzJ4)x-7enKYgV6O
ztK40uZLlT8#Ph?EW*B|BUt<G|5HEeM%oe6d{P6DWVWZsKSVm%(b4~ef&vf8;&ahgO
z5pTwsv)^6N?i_g~bI*9@j?fxBL=S!KV#+gP`{vtYw!7lo=euJKt=ip>6Lt^!Rl{06
zT^>5VyL9Uj$=&?Mu+$M-yR99O;R_~gKiCg#>E1E6>FN0H*{$59-?mt0(qQn|>&6ST
z?|Vb6kQ07Ef6iXZ_;sEeW%rkz{&Y;5`m^=x7kzoQmi4VSwQJ6$+`2ff_5Wl0pp|%=
zXI67tSak98l288A&DaJ$9cTET7*CR-Z?fL~bm?!)J&it@k12LB*1sX%N@GQ~PR=jI
zkt_DYjo3pkwhvWihO+EqushWE>>hhQ@kPwk<&3#}tBorYjtZHv&kXbU8~1|xzkl0s
z`F{EInc))}t!uY=Cf;DiZfommE`R1V!}p~<_Fc2}`=Zl1`e$*+g!o8R?K4mI52i2u
zx%%a?{r~8^znBv~^1XF<Brcvmywa8}dOfpPwg(^j>#=`jmZ`}#M@|y*GhpTY-?f-+
z|Mt~I`9HJN*nR7{Qr{ED&IvF-$yI7jYAH`gombDs=QX!VS(a}tYv;eai?8>tk>$PJ
z;-0PbzT1u#N3QbFvM+rMcUso1bvb@)sF`DGKr3sSWzRxpjuVAFMU5LnJ}=p~3Asqw
z-kp`7mnI@%9_wW}^xI<WlYbOXX>OkB+gd+Kwa>H;UX*_AiLdJOS14-CwY>V%U6xSK
z$4J+zjc)7ZEUzuwbLHmM9C`XbtEJ1xo|cW9WTqb)9-YOl<Fy~2ci-`QWnO<F&j`x(
zzxBcU=F56&XI<=C+L-=GOseyb2Kt3))jMM^zwa-^@6|-h`dNIPPdpj9vH3rY=kE7x
zN0yjpr)630NkX5QcCEoSo@p;;xHT(%EARccm3q3y<{qIRo=ALloLs+u<KiqnT0A>(
zk8+v4(<uFcPsT&GQ@8b3@?Q0LD9^2GncdcmB!8a|g6CYNe(SjT<;WPe^D@D)Vb;YP
zVO{Ii%U_J|^mt1iglnn)Q4E%c&$|_8{_%*&mGW>j<(-l5sZYgK)9lAbm8Z7WN>^Vq
zHRzG?xV|cFxr*Ik<Rpu8hehtnzOVE;P3-bs*}3>@;Zhl%F1s>KK6W^K_isEno$G82
zm#4_iaC3@wQzVAFX4#c`qUhKK-d)6Y&Nz>|gGYu%*}O0I*C(b-vuN48T_ntuen{Tz
zhT+cZsk#$?nPaP8D2aCLTdzagY7W}IlacXA)AIJ2a9mi9tg}bT`OMqrOMK7gd>JQ|
zt8jg`v8VdjTUyxF#a!h*K_u2gyp6^upkv?a<M!MXy7dcVH)l%OJ)Cc43*Qkf8$*0r
zZywRyLGwOPiIFZ7a+j}dxbqU-*7=@A*qQXQ#JX1NslH#;9&aiwv^`~hCF0xh*OsS7
z%X4ikbF58|;gMl09wy9fA#TK9%Z;OsxmWA7^`e%Mx*dO6Y~7xCV%SH*orW%Eh=MlX
zI1FR7Ze&{ioNlb1jjZH=kjoaU@N|0}r+4v@-eECko4aS(+C9?Z@d4+3X)kBOxMOTw
zUo~P<?K5SW)AR2_j%8?zInFht9Q`_vbIWwDWh*zBb33`WGumF_c(8h}iuc187RLE6
z4W+aTymd&so~yNAm0nk|ok*WKvvb<Vm9JVBah+yoVjO4g+dZ~B-rWJo?)g3+@#Wp!
zygc5=8SYwas6(j3;2*cIJ@4cGYwhx~f42JJ^5k6+i65iO9q?q!@tN3)m#1c>|I0(U
z?e*S8enP+17+;zf!(YC)3?B)}$??0BL*6*k$`B>oVaUt!`StL%{Q6HU*0+DKw0&(E
z$JF(1w!gT(6@M$Q`+ij^7yB+Y-gm@rHaxI+U~N06JrE~Takq6*9v){NTb9#?P`9Vp
z^BpE<mov}eZ(12SerV`pN@mPqLmJugTP@;KVkLf?@eT2ia7>H|>os$Y-PW2t%6N|F
zn`6U``Qsy1v-sHDwUbx-(BEDRzf^zb8y~zfRXg3UeRnKK&EM8|<TJJ8x0i0TWqUdf
zgl*YASmu2$>)5hbOD73YMqPeIEW(d1y6w-N&QH#?bAxC8?YZc{+`YJ`RgxuTdum2n
z%CqO9+PJcH*Rss}oA<8w=l}C~w&|&uX%=4z5+K_T_p{PY#G|7&?_=J!iL_F-+ef;~
z(IH!wIa+lY$)%jao`uXD$A$}$V^2}z#_;KSZ*GDi7Z(7sj*W+&+i3mA_M?s2-t4x<
z<HE6TMZc}aZ=M9%nf>3Ia9|Un+CDdrhg&~?y!9SA+ouboKihXXTdd>y(1*rKa@q2l
zMUB7h?Adk^X-mJ_EHmM#Q0KMX9-jZT%|*FVYq`0dk3Ywq`peM^{l8;LCct)0rO!!`
zQuCvlH~R04x1DHrcQ!Vy)A2Fn8;?fIavzSXDfRwaL(BSmZk;P#&KPFH4)fTV;~#mc
zQB9w7#c*en%7hm;tp87ccP#Mnp>>P?FV~jx#yE<NA^UC5#^2Ujyu|P6zVcQs%ZWp*
z&G=gB_UX88nkh<Hi~ekF<I8~V|G)c(N~Rpc@Suy7xvd=&YFx+&yI4DM4I=Im{n_8i
zZ6bd3zAv*s_{oeO7~*bg=8w&AQObAby4{%F-GAr#`1H-SSe*&7nOQR2ezm-Qa!7yK
zUUN&?6;|&w-H_Pd2;c;75@iv|`9&SG7|%;>HSbEt8%=~0cRs!{GC#at`nHj_S)=?Y
zYdG4cWIv?tJsqjT7ClV5<JaL6JlUVAr=x~gQL*tvrDgqFR%Nxs)!0s?%Y5^?9(T3c
zO_`m|xZlaND;kM$6>VqIOBLJQ{@w8h%R5>VPQ?|5k3}qgZhkzWpOrc^?hQGJPT9_x
z@Q@x)rc9AThf&os=8VvnuZ`ES>bs)bT0Rrw?Hw;C-<WMY{NQRV60+=WnOb)q`q-zU
zruq23lk2GNDy0=!4=6a#)gO$OE~jeeLxb}JN~h;rF(tmL>3S=vmi2dC+f`=F5gWm=
zp+7dqi;|(fG8aC=1E;#Sr?jPQNg=bd<TbL?+=8z~S|7uchpp1}?~S?Qr&rETbM<%E
zq28hL*nvJ(x^ihPs>n*}?8-p26;GP48ZqT<>uW0M(BWE4>0+%!d0j+z$k%FHkTzp&
zudA1+s@1mDQu=wU<NNwyYTcN35v%bpJ{s8!`WWmAS>YXr3wJ!n-WghR_a=>F!vc3P
z7N-a;^yBb!5)UC`*{!@1hopW;I?-#Zc784M=HCBDtC?!oqKh%1ySrSk?}{8PwBugH
zw&LP{-%{@EWo&m;o);cA%66=ev8LITe7~HE>!(N?X0_wCb19-X+dMJf<&7)RvV5*B
zLUw{9Oja2mLpN42jUP1J5j|+?9jA4N%&~Rrd(P#gI9a@BJ~Zp;@p?gx#|3i<wsLxj
zXKv%yHr8vob$WKbUF3g%OF#Oh%gO(5Z1tO`y1xJ0SK4@{ZNIMc<?+>M)c*&sF0(6l
z$B!<)Em9wSVsU<%JH<aczgh(`HiUY0f7&!{80HFiF3xZ2`6&1kaTL1s)w!NZ`S*+U
z`IR_>J0RrQ(v!1c)s^o4S$XPwS#Nh+%e!LB@3Pw(S^8X``HXZd{+M|xEV@9)hTCS@
zn?L=#Ov>fkIlN@b5g{}7IX%lBH=BCubwde%`0T00qD}anGXIIpb<clsv+H8m4p~Dl
zFnTI)ihj`f;rm~1U#y&If2a@ri}iVX81+Anx2>_-o2S0~@_O`}YM(P?wcqtrS^UY*
ze{Z}SMkS9uH!Jh+yJw@k?{D4K<eK?U66&8tAMEmPT`$}JI-WiJf4-*8bLCI7+xpF8
z-#C-9JvAfO|52Gu-*VE<5HH4K-(B8q{f=d1iQiy|j@n|oyK=Gh$MXK-rM^UHW-+XF
zEu+VWnpyU&!D*gVQB#g-!jZ#0MU5N7^0&Tb(du~Pty8P5q+ZT)qLbRSwUAjK&B<Bq
zBmXcCrpw_L?RJbG8(O#ZTmWwWgL@zD$LoVP;&yrbj@htrZvW=5&Eo5N&i0q1l3~+|
zDK-8s<vQ*nvf6(8h<97@a$LCecs%;{CqG^`uKZE?{`!aCd^KlyFcz$TE;_{%VB079
zoD@r2zP&yXYyDROeKTsgGK+88jmJ5DXn9|`crMPB&O8>MSb3&vEvsY8>Z)bmx_z>>
zT3U5e18P(qvd=d}qYn;`j)nIBX_w5qLhGbX<MU^SSgk*JE*{;Qb+ODR2vKbxN9?x1
z>)q<4;=+2|uU&=p3u|S&|HF9u8!MTn)Vv|PFKl=Fl5R_=S@_##<;|bG6n6r@A?~*R
zSzKt!Oqcox%5$f8)jiGm)?C_I7cGsqqATS>SX^0bt#6!)_vLQZwa@jHyD!$MH_(kO
z>&hx@Z>*w+MwSOueQ4$rOlYtN=Ih)0NsZm3-&f~!>XI{d`4U@qJzv}DWsF>CNk_dz
zwOyRHOba{=TU+*QLz%u^<0af)gwWkqMn8P`K2qaNAQrOjThN%)t~XuTj)xATeVg~i
zAu69~?lL*M2p`KCBlPi{M2qZyIV^ow&TfqFS^8bmU##eKsiY3~Y4#SoQ~8s5`qDz|
z+&8D0rnDo6pPr@;A4yD@7Iw~iq9?UT>9*1*o6XF$91fQ){~f=aj@6Uj!hWm9taVtG
zabo<+8fp7N*HX6fH6DA3*NtfBRt#fpZVuaTpQpchD<H!%C+rE?vH!vj!%p?`wDC5q
zm#PsjQ?)PE;vG@Xl_RFTc#{s=m0rBk4=rh5wfhndoz;Xd4uSrQqnTQHGJ!u=JLsO%
z-JJvRi)j!in=en;vurO<6TWn7t%ohz)?pJq-|6}NS`l{l?>^sEzF6hgg9{qY-=}GZ
zWSS;_sST&|;Z;{)uf~_m;&w07l1#oYZS||Aty8@(+uOs`07C+IAkg1I-aE>=I?(N#
z>m}PoK5xsmZ;@V#gu_7(t-Zcv)a_hlYDb+SFWoQ?|1U$eFTw&okJb7DYJDMR9iOk3
zK79D{<o4T|`~q&59bWnu%#`k>Xvs@b$^Hd-nX292kQX84<cHJ#B|9H|A$#<TK%$7}
zBXHsQ%w(P~VS)YyEL(j6^Zt37wfpn5uwUBCy8He0C3~wqg!JTR1&0)HTk`H@JAK<U
zqhCS-pRW$p7dTP>1>U|BH*fpUoL!qTd~)p2OeTDh3Ea`scV9fq*6Tuk@vJN@{Zbc*
zFS1#z&n~sE`deS0U#nfWdr-Q5ePe!oOf2W()12p8%KpKLq%Mv1tp+hyls8m6l~AWf
z?5`x+GUQsdW18uxVOzvil{pr<S0zjfv?rxRMP12dp9WL5{>456KdR-=ds_U2VU6#F
z%C^of$HzAp8+!+Fp?kKISo(MnI#c3#_#BL5ZE%t%gjB0<XApBOhH4k()K=MCmiU<5
zsuBAti7GQ}M9uMKA>&v}I_f1CajY_yG{z!CCA&+Hu{}$Z%eHa3E#hok(qSxS`r-)r
z;e$iNjf1D;_P!Ik7xIMKs)kv7WHvs?abQ{JcPblW{l1hV5{_KN!{)oA8V)Pud89uW
zAIg8tYQ9gDS^1nmfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7csfzOk`tII=Y%NTzAN-48aH%qzH-CgR&l)its=pTD(HQO+Gqr594_13j{IseJ+
z^587S&ScV!OzI-(p&Z+rtE_+Zg;K7);_NVE=4wf8##UBK${D-(tM_GWReUCu^?aGf
zU(HA>ewEZ3(PjGHq_yWhcW<5jhtHkbs-OE@dGOZfzNwrnDT{B7*jhxa75{~r^m$&O
z1B%}-F`Lg9>l<BP%WUoLvi{&>?^ydl+pOmIlxIuXDDy>3S}(B@N`0V|p9<7|{)e|_
zwSU{=Wi!|6-SJmW#osa`v27ldRM$WK#F;K<ypc1W-?;bnC6mgktS*zX`0|GM>!;!m
zn(?kZGq$qYjH|L*yH;f_bJN<JR3l|q(or++v}<p!+`L*-Z!13csy?T+8rxRAO6oHG
z0IycoDp&JAs`WcHE>a@BTGGbBggdG`Gp_7gQd`DVQd_l$B^}WEFNmb(HH+<QwdItW
zqKAcf_sDxs@11zI%-15N&GvzabPvYMeE)8A!lW+C%EMth5|tZwpFVKL-MPjZGb!7?
zs}cK?+P*yHY6rT5TEBmfpC2^izN77-O`U4IlcpY^dO#x%NIGD~mNcmz-H5%px+I*E
z2CuBK-1zk?v8vw^$F{bHGO3P9yNaJ?JS3^kPtO-O&;2+3)iOJMHjblPaU6|uBiz$J
z){djEU6!@Yaw-doy2|Ab&v$m*;W+y2=f1q0`m@iSS;o<Jwz>S=kC(e&#H6-^l%M&<
zI6D2ng<Z$K)zPChqK~HC)~+^V<|?bhRBL@ZOtqwqzi@Uq<n1kMHDf!*l-zQj_X4fT
z+G+g(Wvz1U9OzD#bWbkcs`X{#+a51_lOD+o2b6U{BTkldKv~Z>>2>A)Xxxu}-R9=z
yH@tIm^UZI4=Ud+S_3ya&uCH$^?B1C6)?w9^N8(?;BR!N`V1)IOZ{R=wzx@BAjm{ka

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/hit20v3_bkgsub.pof b/FPGA_firmware/output_files/hit20v3_bkgsub.pof
new file mode 100644
index 0000000000000000000000000000000000000000..5c3258b8a39e067a88f4cf639a0511a78789cfa9
GIT binary patch
literal 1450250
zcmeFa4V+z7dGEjWIy>RaB*4iKXjH0e4iQJn#es6wS}(3S8F4_UL!|zxqIU>U0wSas
zy=c?0W{5CQsv}y9FO|V6MQbh6UZrYf2wX&bL*y!G6%+(tuuw#KmHdCdXYGCFOcF5s
zrTyRD&+o~sw`V<Tt!I7r+H3E#&z{Nn%MNwU6>b-ck3@Xbn~pne!<*h1#!ox(4X;If
z>ItVE_l7sT_O$Sd*Piyq6Hh%Q9Qb<&9C*NR=)CE~lh=mlK5sY-|K4*BI_NnE4IlV>
z;pK;iBTn4#+VJAFCvJeP^KLhEdEoGo|8;nD<j{kkfAEW6?i#KSx<5Q+!-*SCe(hSf
zhijoo3HV1}KK@_NE|$5aVJ|98J_+sCUoQ)6cK^uO$-lnI<5=u+|Kn7uN(4ke1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
zKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU
z1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1Vlgt
zL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>YKm<fU1VlgtL_h>Y
z;K?R1zV#(rkKB6LmQ`CjPrG~XW89P7|4#IGH*D@lc<>bvq_0Q#DFXGkA)HX<Sw0ov
z3WQH1ya<8q-i5F`!e1l22;pxKRw3+y@GXRAAv_P^Oa$7TU8Stw1L36zOAvk^;YHKe
zI5Kz|!W$9(1Yv==dD%LjMXuG##j@7s%r?b^mD`ofdO?$J!OiEKE9=6xsa2Kp)uoI0
z2cgQ0bIH`u)$Owp4I>Q9rp{Og<#Ow3zK5e;h$+*&6<f$48_VU(mqSA-tr0S<YJk`s
zDaMjLXX(vx0Q%W=nXZgx6||M)cH73w<Iyqe_C^xX(0p5HMpu^GAYFY#j%qYGdPSAv
zKxQyHnlsB+#BozFdd9toXo4o$jKxu8Bdc?F%jretV;R)NoN>8kzHWTH)xr<!n=q-W
zTU0^~VY@MeV~=GH%WR>{*I0FLJr!(ONl!a!sy^9&PYsLx2(Nh!BFgwe>8Yt|&C0pA
z9EJ>9E;Jt}xNcuni`s-mj#WvmMoLZP1s&?C8DHuO57jGPnMni7vBz3H(pMjamalnb
z!2?sUkKFR;qmTYW)ReBU(drtgj~*Y#56x|~+!8vgL9a;Ng3)*w>d}yKOWo!bHju5i
z@$qAiWnb|5tJh_<yBab_$r<Oq_wA~NNpB5WK6SpTZt&%~IgH{4Q1i{)a&GR+5NnCl
zJnxR?+|@U-=K342W(Ldsdld?DM4$irsB!zpf!<LRtfth2kIL-d4%PQ^Rb5l3sQGr)
zhz+}hD~{(<L;V9^b&ecePhVa8p3Z(=9miqzh2i57kQh1VGoh;X*jTA~X7B3U`KWmm
zCnAuI#3QZ2NE|s5xrn3t=tC}`CQFQ{dGU)!N6~VTbMIptj>VSHjxHSS=T_G<+7a;M
z2Qc3H^CEY-6k^Tm%;zt&VjbOz1HbFiBTzijxv2u{aMvSPEZhhbCTNj8$VJx7x1fJ5
ztH>?$aPwZ|mi6FnDK?E0V7~SKlzVGJELUg9sYl?^uDjY4z;Vlb1xB->I62mk<Gto*
zU6Wh7*TG=Zo2?=J<Y<$wIOm*c4ttLKe6lKQIhoFxMn8K|^S$G2hx|Os5cGw`XY%Ny
zIkg!2ZVl?MnXh6^EmaL#l15!qwR{Csk3O1c8yG=)``lV})7vsz*=P%|=~ZiY2QrnP
z+l=O-bD#fAb;NQ%y`#Agy?UfxZ&k~)*y8iqbO&)=laDhF#FnWk{BWG*aJ{OYq7rHd
z7tAu$Uh!G$ZEET)h}BpI!^6K|b&RH_&YU{)?6YaY^MQx3sy%ZGTBx_=(e^~e6;~Kx
z^j3|wg)3$``>g%6k>;Z=C-%$Hy29ex!Zgf&`Tks6SPOH5>g`%k7Z_DF<|5}j&Xx~V
z{@GMH)LAfmNpS9#Ti66Lvrw!}uIbjk8!|J)KG&enN@ixVx~B%CQR*6W3={XPXq>Fd
zYI_Dm`O&I^$CEYRLI&F(wI9N057k>CQ!}mhUCZ0<x_<rmIDSastih~C4D<C=*EQ&C
ze#f>N)Uonx7<Xx)9dx;dm7(5XjUy{YvTz)-tj>o@%Y=SRq2@c8Ff_;E9}~pKjpUjZ
zk}UHz-Ig{M_Frphqri08a}aIaO6|N*mAkPvtXP$W+RgLTm6i!>W)U9FEqiJ#n``F%
z>#0YTwXFQxrp89wYIQv|9FCWIc%B9OTCX^Fe_g|RtLlSb_rreq1LuDBXLY+u?cArY
z=-E%$V&t&CzQfRB3~Pqg!`7rI`VONS!g7xnrmG?|{ZACtAGUt<uIzMO-r1C`K8Aab
z+WtRu>exc;SUlN-&M(&|yXRlq-)9!yJ}j^&=YKbOGUx1jyu>m3KTXK-=2!K2^<>Vy
zr`!J&S>8te2J*GP+qUt1hyQNtm22wBJZ3w)UZ2b{x5f52Wpe!8@Hhsl+GzrB+VI$>
z<h*m+)%+Uo_VxtUM(Q?t;+fy1?GqnuCtB<P1v&mveEhbL$$0_C9d!Qq-7ct23rbI{
z@SC)KVk14ib(iA~Q2e{?uaEE2f6Ch4Eq>bxkmKt6YAr3B{M6Nz$Xw65>^T&+jH@bB
z2bd;=EX!Q1vzB^$=#1>P%fDGSN?rS+9uf{^??bM$wy|r6VN-sXomKgcc-|+!U@o*7
z&4!Gv<7z(E?}BM2aOjyV@3zgTcBtwHom6Uk{Q3oz+xldNt)BIYCV@YQT(T!s$e@?V
z#8k;*77B!x#VonN2?fhq6xlAp0c0o(9L~p$J(wit+P!UC%g{D<o$sw;cld#%9GG+k
zJ>si^F08<c;Cx*_nkvXKH?L#XW6W+lmIG<dcALT*{;;N&RA+LU$nn%)v5*k(ATUk4
zX=JBOv20nnY*`DVa2OoGb~^+g0xTgofcTOJ{g1k4#MnNiCR$tD(zRmQT84Fp*`cdx
z{4@i21r}ZFop5~_+k%%*uI(MV&SOFq<L0?hd_83cVBRM*L~qM5XZU3E4pV5`4&KiO
zn>2bH9pw*v!n`qN?Guh9eBxy4b0IYyrh<{-mie?Sj+XezK5;(NaES9kSI~}@9JA{a
zD$&;Ar|Xk@JxrVQB)}&Z*wR`co?ox1h6Ib@6C@&7h6M<Gtpwm9HdRx1JFV(-+in4w
zs;zZbwM(W(9FUn8xSa(KWuK~Y*C&+G9ez@`U#N1ss&8u>pzW2>x{$Ir^FGz=&A`;5
zwyjbdymF{&$C^r=IbO@JDihU`--N)9?_V?Z%idn~Tpj3o5$^1GscyHk4SMWSPkx*1
z<5X>9xqWf_wml1Md-I*skkibc!1hV#Yv)G%&ujIGXFs;@-Szg^COfQ2JJkN)t0brA
zyqfdtZizcF*@cTU?L>?JK$D$!XW=w{t&2mSeQXnQd?ExNyQlxKn)DwwQqMr-G(1`<
z>OH+qd+eUfZ0hN(H{YXv-0c6CHjmrkPF8-ddY@!R<~y~&{X28rkzY@$?g^fsJGy3)
z)9UK`qlLab(asmP-kDO`8KeJ$Y(9pU03J(jc<W=;WPR$X=02FVI~Y%#cW<9P-S0TN
z?ONZqyyI5eX=7LO>v!|rU(+?-F7xYnZP#FD6x+^;<!yC4)6f4;HlMlUu?Hrv^w`zg
z)ogFOgY~r|HapU>_ib2i-#?9hGl@^I`D=gv*bQ#~SWn&db4peldu*6pyiIw&m@K=a
zB_HRFw#_~7mTfij<)cqRetW;>4R$scch+zRcH6Y2PZ#chLFjGT>bZ^E5sw`#v+5B>
z?j_Zo;U&SqJfDSR5O_e;eZW#bEh%%ASw>iPrQNY?{~zG(!Ebc6|MzE}j5SkHBD;^B
z(Sxjp-lO^rvT6IaJl2mTxvs~B^jMaUrQazud6?}T*{Q}0M}Er#3(LJFvfWk^6@k%X
zNwSI@S0~pK^=n7x-wuZZ={&@a&f@J`WTz_q<2z+8#O=H2(S)A7F)2+mZR(To9?jbl
zvepqR>KiZk%pxSvd3z|0Lpck5gtF@v8d_WEnhuo~x_e8{Hx5NBpthERjdH`Lb(X4{
zI(6Q)rYqfi(z5rR>j5kMNY|O_!VNzIvZJW4R$sEQh@a1yW3ESOp}_sR>oDIH9+$(c
zaGPsm+MwP|Ai(!#Kw>Xp!mgD&h#^4<NzRdRGk2UH662NsJWvaBq)!FRpbE%F1lpEk
z%s@$L=cJA&>kP;8F6JREUmus0Um2|0)4mVBaUSC=P#P9@5SR1;bqA+>eA!=i%SBJN
z5rJ(X30*c5bNG&=(y>Gvv<r-?!;#!XQ6^MzY)WLrHp?(y2)|MBfw^4eeD_O$80bVL
z&C(dY=Ngppd^}O@XI%_*5_U8Vi|ji%<J|ogtO>p}&fhf{<7zrhk|`r6gV1&{($1u)
zz8FCP9Y-egnGN&zlKJ}?`Vm-ZE7C2d6F}O!0BLe=s0U7j%DAJSl?gp@Sg7beB=Sgb
z2u6u1>S?e%76G}0kmWGst42_yK)X;R7jre^3G`7-J9+dml%NdIEw>?=wf+MgaJgl$
ztUGNA*C>21nNSR<Nk;G7T<NecjHWV07QGuny)of-5fCCm;So^^yT3E^6DfB{e#n|k
zAU0Fj)e`nB+-P9Qv$+|kiF}`krV~vJRKn-TA1L~J#@clTZ`~f`9DeLDA)$n$Fl94C
zJC9CRLOJQm{A(-7^9#JHo04lZxV{$W8Bo{W&$&6IsAtjE7mpZ*wlZ~jAr#g(^ptbg
zU=`%$mKE$EGHbk1s03b^bTt9RBI^*dWaBfXx(+M{76NnINI*Gd9Ze{6j4;?Z)0Fef
zZYvor=8K8YH_pfQ3#8}5$vi*w%E}UJ4+$mJ17Vsg`&^)obFz#@D8MEn>5<_&Z&)(7
z_n%xV12Pzg$pY!ZTA<B7K@||Dx2ZB`w$-7W5IB{H&=o4+tDWy%<qk44J-TWFk2MZ0
zV`Xl8De|Ez*Ga51+oYL!rR>jXs*2bu?c+gRhB~q;Fk(JoBAM%v`!LsZF(KhOw4FpW
zOD;u+7=uP@nyrY05-sk{m;%>sZ<%0meW}8=f#ryRum1xQN<c7c^lvG~`bX%@)@}$;
z;AU9nCC=Xioen53l*n_5TXA=bMSpaep(}wo^juGXMULCfeuVK}5IBeViUaD6d35`I
z$hm*9-w<NE?5*V(EjTV+?R=(pNaho(n2F5v2q7dqgk~K=L{baAi*<o%K%iYhfTTJK
zFoSV-Hte%2e*Q%5>T=t_dyd?z)$qP$LDR~fdK&ghioGS~EAl()fYs4mcn{OWsAtez
zB<n2GNPZpM&9yPo?xbBxmAXzB%%-d=>m<Slv_;|q>ll_Ia2g4LQuW>3oQsb&H8wS=
z>}$J&Ykid_UVthIOkrp#^AwcpwwA8TC<akTRXr1Hhp~bcwu|<I`JbKTTx3nY4)H)+
zkJ*^nRM@Q#=N+l7m|LFZYEo4>Sh^Ut2~A@jx;{+7Wnr3f*5VZA3vjpUvC>udgXk+u
zfWai%lOZfq)^_8SP=&fw5A2Bo>l=EirVxe^B7z;ej_qeC6b5S&$-FEmn7aOra4Y0$
zvOM70ZF~<fSPCDvbJ7}a6TvR_s!}d62?!D4*GYN|g9PUu&j(hw*_KQ(pBfugl`K@z
zj#8(&v>@&_VCM*lwaoVl4+16H6m#A=vi$R->k`s{P|P5OZwn;lI<()h&<TWYHTs~8
z=fvWWdJ4#fs+fB6wQj+5alA}6BTfkLjfu&0m2&(_FsB_#>ea^i@q5()Y6LqjOdm^n
zhU+~vH(rYd0T;mD`pQ|d?ylO5w=iCTdPuZ*n<&3pX*lZpzHKaek99O>dOEU(VScWg
z^T6|6pl*kPYyA%O*5Q1AsWP(p&g4Rue_aW6q_X$R%Bml05g8YDi;<Xx^zsW-lo+$_
zxO5-8!MV$;?TWP!Ow1ZpM!g**GkDA>)-@P|l0P}-JmXMh(>8fi_bREV`S#AQ&Li!0
z%U9!BKZug6Czwz7P*?P%iTS!e=Gi17B!nGEq;9@jvq)^8b>#S`ybm?MA~N(TAv}iE
z)9cQYcC|lf8&MH@+s58PmB-jslLQS%++HG79IOJCkgez8tw4p#W3}uOnEULt&n6bv
z+^2hV!#(*ro2pEm){bIg=Ct+0JS37~J@;g;Mrdl6nXQGK`|hesb;|aT35yX`pCv+F
zW?FVfnAcXsy2k=F6IEZKYqfB1p*mJ|p=ubaGLuBN>$&vkx69Tb>x#!|V=nbNi8hs+
z^Ul=$RB62!rr2-lsf^ZkKRiqLhbyT@nG&newXOVPGK&Cx9A*k>R(wl5ONhx-jN)jO
zol7W06iTE>=Bl|x=Uu{m)-3b^db2^#6Ue&+_Ru5A17f}t%zxa4AtZ@?pq?-GqMK|7
z8|qmV;AleXpsQtNm4SIS;wgpaVJtK7vzaw+;~2-P{g`u?LVZ4tV?>{!QoBx_u>leX
zD@I^Q7Qx+8|6;z2Y>4nS%nwx%vUXwA@_D?3xuI{9DlMRMB?2ddd_+>q1oaf80r%Mv
z*??dI-L*bvLxFqY+1xf!RkgD`$6<zjV2s4)c*qY?jq(h~g|MrH&k8B#P7{@t3|DDD
z>U*w1XR$wE8Ls+Ze~Gpo^ve`o;YDxj+s!eb>oL4LsLDGQB0>k|?56=c{8a6mCu6+V
zp6zbD%(?x)3H`xG;O_=p?cLlig<Ffi(X(Quo4a+3bH|@qxMBD|`eEn3f2(uUjeY_b
zxxKx+=NuQm|99TK>FK_ie#^OgT1C9|XU+{i1M3PG!Anjjz9LQc74EDh#s1G<=fVYZ
zxc6>0+{NhUb0@j+=YJbZ{wn+qIex+aAK}BB562&iI2SfA#avJxKFQ7Au&U_)FBc|<
zKz}##+4(EZ^Wn|sd3XD(3Wm7{?uc_Y-4Wd%zhjYm<2x3$et5NO{czN|58vh7?Fc{m
ztF{~at9HEc3K#FY0>182G!f$WAH^K-*9~Uh(z0*~{qA!^pFh4}Sozdz8v((6<|j?}
znU6JFm%qxjp8qQ6e)%N}{^IML|J1c^(WNgd9m4Frzf&ZH=Cd!vm!B6J-~Da@-&bH!
zz2eK>eVG3K_hRmXA2|5y;A`QILios9=RR^feEnC1Q=Gf$FT8u;uYCN)XI=b@Py6Qe
zI4;-!7W}>6#Va3%k8iP%hWd(hNuT+;|L0#{gs09m!u#Ow`+nlwAwP2Cm%kt3X88IQ
zgs(YwANc?BTvuND66Y>^nWL|>KR6NR!1aK7w0rky_`4}Ear^&P;Z8=l`nR#Re%r<M
ze~xv*fMZ)CO#A@L>kcgI(#@?eF~Q{BAi{Atb`$;Z4P)MnaMb%y_d)Q*dQJ$l_=6nb
zw_WS9Yw=eA621#r;hVE7yt{nNxep-h6<uop>8019ej5E?9bCS|{QCWC;FljO+yKI@
z`0FlnPl4hng#Vp=qF?lT-ES4<*LVrP&netWgyY~-fN${G#Wl_ycs~4j4|MbyA>hMr
zLVwd=ckaQP9etv2=Jzc8e$SX|oe$p*O8A^~Eza}9oO?dP1<mX?{bEQ{sGoB&?&az2
z@-{HM9z!lqh5Nv0;Xa2tw;1QyBKQn{%J&uV;8cX!^IVvPJG1D24&$xcjL#^e7Q*Z_
z9>ZOXzjZb0E&OORw*5ax?|0%ndA%#AKjG2<+AI$i(pjjxehB9dTsWv7E}?GtkAc7A
z(qyM__v{Bn_U+SOMJ^mjzvv%)^FGD_??!RlM*EAn+`&Irgaor&VVlr2!T0s>4IxZS
zyAW}l#v*(}xE6koA^20_+imds6WRCLx0P>mX(ifU3g0gCF13M-p@<BHn?qr4$Q`}K
zxf{47hv8c|5SdB>)8$p6N@86skx6hA34>#~M?z1YS?=4E)MICRb%GLg0SVk>m#&2{
zQ{|CZo_tx)Jr;5!lHdQ1W!bv&A(y*x{c9fynmF&FbyFFo)}hVV9Nb(L7bKwHm0&$|
zi#yIlH%Qm%e>K~#-HkW}o-u%8vAI=E0fnwrGQ;SaEdapNVC?JE)T|amVNxlA)g-Do
zV6zz(+&fSY;XETk;3v^pWNIU}NgO-6YL3kojWKrpg=M+gxevaVx}A}-^eb^5#N{!j
zx8-BeE(7}yYcbdy#vf^;nDD%LGtTq9T?!a^c4^UE&;BFYP22G0v}+y>P8+cmxzH&+
zzH2@I)K3>Tt-bJ`lkfd5E*@^_`EU4C-?gv1@Scq*@B83=yPtp8y_46TaNz?dUv}iC
z=RSDf+3$PgQ*XQWb>Dqx?ayDf>5vCk?sDN>AH4FgPyOnV+kgI*L!SHNi&wq>_V-_P
z<mbQp$l8C{c*td6{QJhux4-|mmwoDsn^s=9@#**ec;9^<eBC!Dj=b!PXY6~$$xpxR
zutSQQ|M5HPPrmm{o1XRAQ+7Z9?n9P+@wvCG-}tG+HtqZHzwZ97t(!2Bmb>u>*ydjD
z+`DeM3>P&#OlgBd>2R{)i>!&KV=gn8<~y;+lpwtn)4*O|;Cu%YcUV9j)N>`yM~D3i
zI`?5*|F3p#Vh;KhzSTsV^yk<sp-UKYGmhUhu3gZ%HjgC(WE%HTvmSiWdpo(ZAN%HI
zThLbrJ{%5vq!9Xh(;>*5b&{30kE;H9E9&n^x;lK<)XiJQcZ=Qcd23Ao4}@On8DhR+
zZGbuU$hrN_-G;q=JK<X9GRAkPm>lzv5;!)KZ;vF*zbbO=1GP#0Y_WhMq}-l;h92i=
z7#LN8LunFt9JiGO+lYYvJ9V9}Ge}dFXaCWq^XqY9K4ICm7W&Z@j}BoQs9-df&;5k_
zB`Bh=dJRPDvQx3ZW&UrgY97CYJf*q?CRc~=@QqnSGA|g9k}U2<eJBT%i~-sOlzFU?
z%!@gYi^b-gwgOTHNS7^!2*FeqO($<Dr@BCr%N42HMM4(i_Q(k9U>19H@FO?u(bZXw
z5m>;z1QSX?sC-XV(T!H?2=+}Xvyj^bS0EoNg(X!-V=TbA5KU`*T$%IR#ps`7mWz68
zFj&mri6b!y`HxpwK3Uuo#VTKqVPL#X2icN+nF+?>^!OR2W*5v1<3UPRF0KxFM4n~H
zECR1xKxNOx5*pW^qoEC~;sAA@R<7Dwo{`7i7p==Bf5|e=SEyn_wv31%Xu|h#N^F^P
zRoRSMT&&i)9V?IT_9HZ&(+vqxC8hImGF1h1?ywgIeE#83Y#ysB&I7x2o^*o$lXV3K
z56Cy6tDl4<?7tWWZ!7o`8+yQ?>>3sb1+f$expQv#k0G1_{Y7A6ePF)P2kh~ITe|hi
zDw}JoDp&hx%f=%i++*fE?CSkD<<I@DVTYCskG~PsP*a-dISo&B`^VR_#Xw*U_*AoD
z$r?0QcC%I$TE0W8R&+iRB2INopv{>sIK-p*v@Y%BEe?t>r3};17YQvO#WN!lO3%<M
z5*5DdVD%+8Ef{P}OL=Ex>%aw;;YUi$@CFCtmLtePS-qP^%fRYNP=oqKR<iAXG*`5^
z<^y>r7+^#Xn@C#-RQCNvsLCj^Q!;+wF621~mKeKmVGiaV^FZ%tJU)!ST?ln0(99r<
zg|InchFHVA=~~GS`uyR8w2Fm~_Wl)}u=xc}9+4{(lIZ;2d0T*i8;C{0k5c*D0SCs^
z&RV<tC4U2LRyclpk5PPxs0JT0q$S1D%{iajAAym}tf-Q}HHt;l!XMIgtxnab>6UZx
zQ=-MVvklI^v-K=vL{MNCt&}msbJR>?3Fpy$WLgb!D-97+LOYzC5We&D?VsWF<Dtbu
z!aXZ)G$WeeXqSITlcE{>%ix}kTdE<n_eI&lxeHS_jRO%e+_Kg1&pW>wD>ebdG@Kec
z!bSYUX#m3)BjtV)T``5C^Ul2x_e?EJE>48t_H7WUn+0slk4M)PZP(fde_C^V4LZO<
zT=Y)o=aNhP9UNZt-&h8t-Oz{=>c^~GSO=StA3;DG;Kw-YIM`sLxV}VoPoP2Zu;W~F
z8R~`ryiDvJ^L;ix2DUN(QQOAS1U@s~3O8_Q3HN93M^!=_8aLO%9{pFscb-f*RXg1y
z=0yz^96yV_JY~&>p@`@!<O+*9X}r>b<;ey<2GiQH3pNilp|0DV<vBtJ!6imnV!dWi
zjDE@$AtA>;5F(O*5ZRJ~{&=l2A)_9NJ^4JBY8cw1gOKYNwBpp*b<A}Zw<2Eiv}vJ^
z*5D2yx6j!9rumW`T3_X9Hx9GJ4r~8-&456S<&-l_YN;LJEu+=P>K%X%)(rBLHY0T4
zCJ<;85h&1M7>~7Nl44FR4vgU#+d;5@^L&S3QfHzYU(ta9mn6@l7?{D~Tb3=Ol^EIb
z?#^j~8ia_Doklu`fM#Vip2Nf@avo14&208%Fv&ES$&!Mlc|F=>D!su#eh6VThAS`}
z>X+j>hi+?Z*|-A*4lPkP1Ng%@ail(aSD4Kl5}f<l9vA*B*gz6KZLv@mZ5wjjb=Mio
zfpw7OR+;l5F|~8f6-)6)mt)?-G0$Y@2Z!OtkB;#(Ym6o_IN<R8!+<I}2-)`>OAzgn
z@h18hP>tZ0RVlL2HsKnZB^;{)QwS*XJ)GlzgbdIG&Ygx43CD!4S3*D?B_eP--Fjq3
zs{&0*gsyarOjFc)v@cfHg`BcWle!6Z;21CzBZ!S2qUE`dl+31vxxz7{%_vt}%=)UY
zfNaYRSr;~Qem0@9l4@-`AF1F3^7&ddK<CgEtfS<*+@?~Znk?V*^=tuWD(TKD`!XD|
z9?f#!GqsCZzoK2WV-jH#ayeSk^&l&&xXY_5*Y|jA&Yx&{&+FATlIy$5kaO1GHnuj6
zs=oHA+Ya{(b=ABMzM`Y~ZnE#8*RVPUhP!S!f3Les^&E~h_Hi10)vfdU4sgo+GD^As
zeDK&K#cnzHN@2Eh)nmd4tCWw2eO?VN3;gZwKgmTZq3St;?A>OB2P~|uq)}&(vO2I_
z`IGBRL#;{3UPh#pgg_TL5IzrB+B>R;Q?)Hjx{fg)7(s%?+1WZD;7lmF3qUY{9ak&l
zD3?pJ<ljU$iI_odkjrL+wnZ-1u@A_lx>Ths!?f#*sfR4CpZ{5bHYOOjyOma|wG{^z
zIW}y2`QsLCULt%AFhB~y-iXkZr8yrh*~WVqg^+!veMyI460Lw?12dGK{*cEtqAR!^
z%l2p(=Yf&sk-g71W4A@l<oh$`tux#vER>0=$TU>!Oofg^tb8;@?jRsf_h$+iP*{N2
zaf`+-vP`vQ%*?x$R90;BcE&>0N5EJHI+r7#9z(28*vzmnf3MFHJI~Dn@|6z<QD4be
zo!KT0?5VHYq_>tVhwrI1C=4yNjzji?6(xMiKGtSU*QosL`drq};&6NGqsw}WgX;?V
zT(GoYM~OZ6yqIDZGYnM$k708|pZzj@_6gp0t?EqovVuF~mBX27&AoqqDm^PLkAo^Z
z3S5J=qfLTn;ZC*-WWIy?jIFEC=67$*T@hPr2>Dc(gT3>VOPyK?-)XcB-}+vWKGc4o
zKa<G8R_46L-Fw7*e9ay%W>7tLm2p>7&pzhC>p5`6kJU!08sDZ|H>g|+FhV^fAVh=)
z$FAH&Zd<WVEUNdTdd!$X_BMqIg75z*0imao@8bN^pRl4=Ft|PAOHc;;sBX`3*$^rp
zT`jp!&N`3p?RjdKGtC0#SUt6=Th%FWCARJHCs)ND72D4bP_(dp)%MjmJYAAC<UOdv
zJuWYb0a=DhXv=m8mD9PJ+XD5y5_$`%x8Pf4w_Kp7e7nQBN4#!wJ(BwTGaei%k4DZl
zq+!=)0g{{Nd~clF<j)fsY|PcUB7|JBV}yEq);EcWgXOwR?PDYEOX2K7A&*e2&~4Sl
z0v)S6JvPh+G>k~uzLxGi2>OXs?rSy4Vnn^Ru~ODLyO!04by^(|53g(c>LBqwoF9+D
zj{f2^-7uS6zypD?u~&r{5UP{n`N{AH+Muqvem~~0LNGYnPa}+DN<;WOiPZ5On1GJT
z2xF8PB0?58<LMFgK5^ZkzF3K&F`SRkuMfW9Gq7X!fivtfz#-<)=US+S@xhaQwjz!X
zF8}M1M@PKPA3)ZXZN~Gr7)NtL!A;;l5Q87qr*+UOih&{CccQa^2Ka1%UK(x!c}hg!
zJy<}Rr6*6exG5aU?=*ez?I^xD8wFk{SKt>)rqDGcFp7*I)fx+&6Q8fFLp^RIV#H9q
zC&g<Ewn?u$g-ZnA%LgbSqrnZZKBE2@g!S;5F6=+S0lZr}iU=5{5@O5ddX7HIK5=A^
zKn<od6Op<D-RiYST3{Xa^$rhGTKRhE&1tN?*6FCnm@G&31Hor9T=)WP(PzXs2`T;J
zbBN*K)83nDhH=meE@GPKyUfR8lt$<e%*Ofb18cSwQucF*W!5hCSFT19aU>}F6@KW2
zn|ycxon3#n=Q~8r7aZcl#*^LbO(!+n7<@l{KVP0c<Y(6%?nCF?M)=eH{P0uv^}`Pi
zqFu*_r~fYgSF-^>vHtiX{P@;Jdf~Gg%|CdC59<$dVZ-+eci(Oex3tk{ZN!mVKU>Tl
zdUnH|x3n?3@d97ox7fvF&nm{3FDhCam*f9Dxy0W(v8os!+r<rUJl3@~E_Ii_8lTl)
z_wu53$bWMOAN;3o|BY|;?aSXW6%gzlt<yih%UO3F&`6&<pfQBHaL+n_aa_~6_?VO8
z5bDBxKPlP|@8ZM5ySQ-EIv+OOTdZ04$NNm2{KkFSk6c%@PXCB&Z+ea!+VmW&a~qa6
z1~%-oM~mTwf8*czisuxaN8VkGJo4^_+pt^X<u81DvHJ8q`(BPPv)6MPH*9!OaoP)C
z<^Fi%tK7>EetU7zrFh?Q<EBObbK@C{zIF8Tiv2bm>sDU=4j<ON!}#v^)_*M0$4_Zo
zeEXq|12%5*`(BRsxK<#nU*ivW>*pK(FRp70-?ob%`02BJ`+;@7ecHbj@U^k#^fxxb
zFMd*-f5h31p-s>5?M=Vu{hNPY_}SeW@U=0pvC%mHn2!`UyyEX0Be#B_ap+wiD0aE8
z*%)8{_Ts2@dlvE7WyLpM@%P2Q9eqYYUr*ck-`)8B=N1>>9k)w2omzbAt(%JbHf$>V
zM-T8TpM44z-X_m?o<4ToiQe6{)Gxk#H^2CS1N?`6w8^a;zSxHiXSq-O%Zc6(@8`n$
zHLksGonzga^?k*}`fGf9-5ow0v!5T>bf6!;>z+pYksBKAgZqlc!HZq7_eE}CDZ&AJ
z_#2LWcX8CHFZ^=fXq>*UTYb!wJL(2kjDNFPd}H~08h?H8Yl^{x7rBY&;}I_EoIAz*
zx(S>w-GKkm?E$R&OPBicq62*Uqu{w=v%BQj6aB}JKFlxv_-@`!Ot{$}z1e;Ek~hQ0
zPrz6B=CH>$_rv~z_3*iS3J1Sp>?_tx+~HeG-{x8e;LpdN^t=9`2d*!Qah$Tt@tp3M
z#jbJ0-?&v<TroF1Q+$2hdm5{wZ@h7|aI03pXZW@nen0d~9RC--vY6ffHAQ>xMc6b>
z$BFn>o_&k?&QpQyvS<yI?p3}F2*n?uX0PDf2D}%w|8ieUUxITn;gy1$(DvKdi!lCL
z?7hozV&ew0g?+fS!8i5-vl81&YwfdqYwa`r=<<Es=)wDVKZHTX+r>b0tkGJr&KF^S
z=O*^YdrN~j?-#k&!DXYh9AW>mf#0ph;Oo1-Ex(BS(Lm|(ZbbWO9-n_sD+}xwe(7@W
zNB6>Y1HMnsI=}e_=V!0C2NcD6Z=bFGa_%A1ZrRCrG7DUb1D;?{;OTnU#~q6O>d<n~
zEgSZ}5i$MN82xk0!ZTelfzOnq;1ma4F-$fNx0QH)w-Wk*fM3q!J5N{L3g1xYr?GK2
zeZC5f=X+2;mN#Wkbd6zL_)hP44Y<QgXfcX_%@UJE-~|W)mzF*1Jht{?BKQH!%`b(2
z)Q2{lz~fasYi?kF=Obj($AII<{?H}_+k@@59Rsd&7>5c_GvPZ=e~W3c%qPLM9^d-e
zV{&jnN1I!d_z=%J_78LR-L)+u3Xljx*qCpeQv=t8x()3a+Nl-U2lGr>&rsJR>k8i-
zEDFBlVy;_V&fy)C^Kq+j7Y-?ayG}w|OcWAu-GaxdZ6zoJ=M$YfuJR#bl#&W7V^Ia;
z&RfhWb~Q#He86`nxLBEQSkMR4-29}kgE&K2*GjIiIq*6js{Wy07U>Mw!mnER&J$m=
z*;e8O(+gB#9K(*aOFs(CEnNAA@PRO5N>5$ccGDAnXc*@F!x?{sJz)jDH+f;Z-yP9%
z$?d~=HPFtrRxFP3zJzj{ZZ73JPvf|s;@aHz=6~J&vNH}T9(d&a_niFDmmYoYgQuK*
z*^!qm`Ozl4^YqZ`A3fy319rJ=<3nd&d&XxUI{BefH$C^e`>uN5#?PF6?WTtxTKn*+
zn=X6sS&a)%zU->QHa-04?f1XokbA$o@8J74{KHj89`f*`Ywth#kjvik+~Vfj|KYfo
zZTi}#gST#c`uVRuWRC|o{^i7xzx>J>&%Nc8r@!me=QeKMaN%hiAN|Uv=iRb)_jkSF
z(|un&g=M^7^{XH5?yl$Z%I`c)|0#TaV6hJu^yAdRB>n}b*qFyYy&KXO;8@T4aQc1?
z1l$MV+TR~=Pl)!o{<nr+;N4B<Wp<~7-}3!&-s0R}d0gQ(;6QIc8+TjLI;p@5VSO$w
zKghL~w+nalVpq<2ABO{8DYzK)3ZITG8Z#@F`eFWWn)~nR%C$(>Vo$=CJLtrO?>xQ!
z#HxVqxgJbnm2Q(H%+cXc=NldP@atuvQRr>3u!=RQr#klJ`PrGH@*R^i&g-oh>K0lN
z7NJ|5&tO%XM8uY#MT&U<M}R8FYz&$2&Wf?JN2L$sLkZKCbf4$NfO5^0c}NQGnK@^-
z%ZYj3yPMckUAyhHNwtD$dC)OWd?yp|C?fDZknB@;Qndq<E(?6d9u-*#j3{W5orX&o
zk4<9c_JI!aET?8sPjo7`hO$>`KcNfguaZz_EUilUfp4xc6@l@*rpzKl1eZGrdHAeL
zmS7jdelb5rZIO>t$gS)4IAG62Gn*`#VI5BP%+VDA^Kx!8Hd3b9&JG|v3Mg;J+!NHn
zN86pD>PqcH$eM@**El|dHUYO5A2`4V{?yNMxE}w+zC+CIBP#=J2her`YX*7yUT!=h
zg96M#c8T*xDdA8+&ptUERM8b?YR0tXF=L=PjOL(Y&e5(p4f|lt-3%{XLspa58XJXN
zW?bSSBE%lqaUe>>y$(~3ZwG@q%j5bTtB-mZ5S*!|n0=@Y+Bh}v!$o_%z&T`rj(xH+
zc9ppbG2a!r;kn4nQPso+gMDCLA>|Zta-;AmT9?3#cgL*?5vCbA0S=IlY+%)ga6#ix
z9&HjA76jWW?fCJIUs6Q+N}DFzCo1zR0IBI#IS#O*7(~N}I)4;<;2()9Tp#C&ri+^i
z*H!C)qZiRm@)2iUWfR2cHTGHB&LbipXm5gUd?%o14Bf(2KHmcrE=BYoxNri7O0b0`
zYMCx#R32j`zRNmdcT2eLqksAs_$mUf)AmkC^>_Hl_%C_wPAkwGjvBkNelg;7KAr=(
z6EO)kDQ3+IsU2pR(+QL2q_femLSaL$E3<-o0PiKLHe3jct9~N2!D9Hz(F58>v<=x6
zyyH<O2U%J_RzN*1IQ-kt%b3|UXG^MW5W9hM?b<`r1=hMLwCyW!KZ!g8&Xp>M1f|3z
zPt4CD7hpBS!DwvyA_nJ<$gNAfFB>9ju!yW}fjxo83lbRRb^L|z!ah{E1`@Q5YNWjO
zX6!rsmTQN~e>SAocBfRbl>1CAJSsqb76Dsyzs(HGEuuV}|63BQsyvW;K0eIRj;$#;
zhaCSjQ`1e^I!0Z>%8eJ`Sm1hdW^@IfxuaVgJ}f31mgfWR_rfS{7D`?eu#nId1vi$<
z_(zMd&jwexcR>}<lxr2YYcR#S32j;yO&ojA_l;s=(VZ1wG&%+ca8I8Cbl#aIHqAXF
z=rqUC9<RS+oqFuaF*e=qwhS>DuGir{w<Y4nk4+(b=P8yQ_{p2WK73%<w`lT&p2Nvk
z_PKb><^ml8$Cv$q@D86GF%xL;3~L-^AER@;9XE1|io*_ve{L8bE{c{9@8n73`8g)u
zu!VFm10G`-2V|kIzJn=>{$;)&b8xd$#h7ECm*S>++>NGwHxZtikIX7|hjwJK=qbh0
zv0>bwLjzwzpDV&l#4+LM*mhX%4C4c46MkNan_ak#I`VR5zzz8d90u-un9G3}&Nbj9
zhD0@LAt;|)xb@>_*}FNHy}-GN=AN$j(8o9gdP#^e4>!T#A>;?43MXi<<aLx>G&?e^
zYkeyso9ZIc30Dk6E9aPuAY2@kU>xoV^dd2(8u@wY_CBx5om73fGIm&HJ=#IxwL1&e
z8!{pG_y|L|Oqt3PwR~W6`<}^)WM1h*&R|pJ5ZReN>k{BmhA%0boVy0UmWW^LGH8*<
zA|hb0fW$>Ky@tmMr$wTIW@sE8)(_SIowD8$O;%ImJd^$KT&fM2!3k%^9&YEh9b{OT
zL`Vn_G@*vq`52gDjFo6cWr|c3Zm!|3uQ=E`rWS&01`|X$&CBGb5=ynOD#q-Q-5^vW
z#^3^~j7dbMKAaqv$HAtM*cyk4d%~2d$<2P30u^qW5&A1>mYC%kit!4ZHwhW^#pZ62
zqX*QO;Jom05O&p^1GI}uj~FVnX&&rtSB%sYz=sHZ7Ffi*5tyXSARHWHJ;Yk#ykmZH
z!1-1}AE@`^{6S*~niP=-F|d?X;e6(uYcm>gegxx>1)Q(d{X~I|dHnH%3<5l{gUB+v
zq{?IlJr?LWm{qN{^SBjko*Xi=Vv)o53UnBk{bX)XYwzg{tg>vjGun(2l!4|DOai(7
z*5axm*K}8ijGx5w4GPp9gv4r#Vx9uaS@P+}V;7@olEsx1Hn*(7-drKBrh;LLYvD_*
z+_H9zCOzXGpD<Z!=7k0r&g_sy8epD_k$YD{sD+yshOyI;x`+o#E;3h1_W)GoguxdZ
z%a?q-wgE!?<b!M(7BFUD3Yp1C-bKvy*sZf7>bVf$TDLjdZ!3YiJP}?ttM|H05l5{m
z#+nUH;XBIn!nt62xc*f~pz@m*wU4!RsxwT{8Ou07STYHWQAD5Y7M}$u<_pW%O)X!=
z)YM{sU9`yd)a?huJ-?c3?N{%x1Lb36ciyN-ti;L#oK)JVEf-t^%3=uRL1fY>%7i!U
z>~OnTv_c)?q6kRoJIieZ`so`Z)<bkfa$GN*41}>w$X>sMYgr8~@{qO*Q1MK(g~P<f
zd`}dS4G3^!B%xuo7eWJJH}o&dV4VrkawvP;%iyv*X=R=`R@1?#Sm5~OGxLh`F=1u*
zEKDe%{{UOG`pT|I>=@+O+q|KJkadWBUI=@_giBB%4!Flj(B)G$BFDaJfsF}wSqeTq
zqXWK%!hMXAV-5>jeu(GcF}J)6Zo>QyP$UjasZ%TXXbIc0HT+4Y=&vSX1w^bT#bQN3
zT$c~Cd|l3MJErpy$y`E2N!#?6wTL~BXgw3tW`3DQd8I2|L>_x#8!qJAX=AzU0JE;<
zQlilEMF^&}^^vM<l|-9&u+N&vXGu)hHqVC>j65D$3SVWQtOS|XRF${2TICZKP?kAM
zLNg@Gz~{)!0I$W}_nx8PtgHrc{*%V2=8sA3LS3%Zc<u@p!K_D62)S4rchk5)-?T>-
zS=AlLSpMb1S=(X95&fl<6&CZTvrLbJrHJxka3e@@k)er6s#5MkwbI<dat)}<^>)p#
zj&rQf7}VNFHl`4)i#(6WQeM)`g_zLIAP!s1K9uv+SZ_n@7B~$GPZRUnO1Vedb8Mni
z;&TA<MJ}6Dm1j`%z+fm!)6P-L`a!5&(S|a@kK`&CO}-<t3|~vZB}z4#ed@{@++TN<
zS>vKxgB<#^npA0-L<F<8D3_yYSzF(@kFa2<E3+<lc#+s|evD%KPRbpchj9#5xNnOz
zsXS&iXI~vUt0GW*-vccqS={|hVx>vM5&yD;Dy@^!g{rQu!98$QiPR&@P$ktlkwUG^
zRTigio}7RC>Ta=Wk8<ehFoP)<yX7KR;P##pEk-k*wN(`_8eK`d@Hbb?ht&0twd53-
zK_3Y*!c2hLP66EcMd-|Tc8+{rO8NSSVz0!y5Ri$m&sT;J2dyIC{YA^S87FiGE4Mjc
zC#=F0h%ijVeDh?2RoS#sHpsS>FPvD)mgIQnx7ap1Tqx`oc;Wp>v~Ez7#Y&^r-a~^M
zd6VopvR01N&7ZI=WkKs$*_6=yH3E7;8)zW`X>@tO?5o{VSX~7Y`AFwuR@SjcruSM~
z>vLN56;Z-R-1?YQonU{?Bf3_;sPmr0q*7ZxGDbgLU48aJJy!LUBHW-Sl#quR$bk6H
zQ~M&+&aB0+&+{V2`Cm;#*ewEsVSIMj0~>qrxGjbw2@N+uUo@JneR1o}esJL7KxmC1
z<!1zb`7~10&y8Z?mrc3gBKxFak#Jas;1TxGWI8O*2|S-dA;QmSN6R1Hv}-s%#+}t4
zF-JeaqX`!x0)}mmaT5$x2mIV|W%d2VQK)Zve1V8MxP$-Xwu77xg)e4oMPPRfIH7~@
zIE<I@{K*fQ4N@q)kMJ!_v1>%JgEZn<$cRS*ITQgtH0M}AiZLK$dDAN9CJ^3@g93@*
ziRZGZHI4@YD{<d}&^pTFr5rSxg~24!fc46QeK7)MId1QmJ=EjFc*Emw!o(FE@Kz{G
zd@3%0ZJk+;*qIUG0}fMqHtZ(`I;i)N!*|?B4E+PCN$)*gh{D+13gCab1ogaap&`1B
zsD|XNhR^(pX3@G9-=&w{jnkJgjB$~}Y+SVK%}0^*K0=TCKJ<y^KHw49oP7=5;Qyd&
zKDhplYr__fCO&88sQWczL?$7N&%8dNy}KBS>`DV)yzw2O;(U5Gjl<;JmM!0ExC`FY
z+-t*|`_lNujV+xoG~5eb_teiV|HtBv8@|x+@4U^oRy^8YzVKPi+b_D!cRu-jAD{9J
zzkJ03?%q$H=uf-;$AvrWYu>$gH{ZGbhyI4^?`h2a!8;mbeYg0ZTz{{B$phbalas&W
z-I0Bb)en5XbNB@(xsi8&$<MjJZLB`#$L{ze*10R^?kwYtSGlL+4>mn>^bvRbRo^H(
zTi&rKoc9L%yGWZbi#45}7VZUaEwB0Z&!5IHbMP<UkML*Loc_bzuQ~nBXMFFQ_cy-x
z&F3`+-uutZz0Ubn|LuQuXXp06`r+a6@~!SrgggG}W&Q^U>)(6IlGASf*GA`ycegu-
z-Q8aOy{-KWKe+j4{s%YT?XP;vPx~2;`o;H;TK$V3zr6ngKkZ-gf!F(Q9CKUaTgM#V
z`2KlcTYB4hKPzALz{AZ~BD~}a7nZBOa7B6iSAVkW@n8MvBJ%yhAK_!t=@0LE!s$Ql
zyXKX*ExG2Ezg+U}4fiaWS$p5pu6gTijcZQ2bJ@mketO`MYd*clz<a;z_j>P(-0lB-
zXaDX0e24FRbgL`>=~4g7kM8d8{pbmvzOKLdZ<fR_-tFVfce@)txV3S^_qH}Z_TDS{
ze{%Dt<`>>_oxk$IpZJ&m&mX^Z{8v9dthx7ber)gG=|BINTbF!e>`O~7I`8gs_RD|2
z^p$sg*1hs`Z*eDl;fkeezVJVmPJH#wMaO;h?p^s#(;wp3QP;fn=Hi66zOjhz7yXON
zU-VBcJ`m@{>J@&?d-~pU+FmO@c+af^*UetNM>^-u{%dZ!vw!WDpZl=oANscxXSgly
zzqwBMi1P=2!LPYslRxdfoBCJ3^I!Wr@4UO|uK&9@KK`>fe$2>{xZ=9Lqpm;I#TyYm
zaBI_Fu%>??{;h9}|4#pvH(k{C^$RZP+j8D#$}Ru$(9%_-KXt9~*Ec7YT;*Q(2VZh0
zTz%E9$8G-pu5R(vQ}DfdlYXE0I_KVZ>s;fjv$y&~)7zesHvg}uOmsfgzq0d7SFV|J
zt<!E_7Q+|38+@jldhcz1?xs8a>d8C$JCk=bQ}J{+=U#*NtNvG`(<}@4-GACSoBXPO
zIo`*czVABY&pdqK`ez<~=1r+_!v*IwR?nQ;9C`PtO?ULI&4KaY24a7Iqjj!dyZN?7
zYc^lB=&HRhUwY;d50!kU=_hyL_%9i0zIM06Fvq7Be$fXv`#nFn87E@7`Y97`pJT3a
zgU8@m{)(p-{loVbXI?byuKMKBt%0ZD`PO7noU^3ekFcaa6h#|*>ByHSi;*L)T-KQ!
zaZ8@xS>cCPHQl-s`X=zp+npx%)wHxf&MfL*@_grl|FdTJ@C>%Zclu8A*?!qsA9IIa
zo7_vUb$+5V(tPB9a67mS?=D^0Sazsu#63Tl;-U|}8`|acJsk5}u6@i@%Uy78%T1qK
zq)(2!^vRZ6-FIWF)pxa<UQ+ZUJheIe;#M>4RmAgL5wZPYyKTkE!uxd%ymPf?k2S7;
zk2To)I%z5Pt<pEwO*fnCu5;}VU+>!={yKcXp1R`M{-xJW`NOaEE_C{u6aK1Z(fk4G
zwlrG1`M%a}L)f_Ruq3(VeCO$pcEKK(hH-_mi~2Hbx-;18@js>qZ1M-flsohY|9^M<
z2|@gZQ44>R%IZ+UHtDeoH}K|bBaNYt!B#{E=&{*B2A|dN#Q>fFVh_fJ6#pnqT!E&L
zPNIC6Swq*4y|%xIp^5v3=4<h87&cr!427=&p`1al@C)w{b<q1D$3QDa=%KV;0{t;P
z$H54E_%c8PmSe8tg{xoz8rr`bC#MN*AXS&x>p2rhD3S4QAAsSflm&tc+BXNUM?5&n
zvH3)mKg^pieCG+W0`BJzEfH#TYV~}|;6B8mF@=bRiEmR^&(Po<l~hpT1g}9f#1X0d
zjKvUW(6BPfUqqs8ia-XNizXYOiAQgoL-S4dp_mX{2aYDrp(}jnX?uyCn0VhbZdJ+Q
z{%d?gV=B2tuEfhYtrPIE^kVoC@$&zk?TCl)&DJ?!2#U+vKE{OqBBz0IR$zblito&H
z@IvvQfzSl1KI%@s_iJ0xvAy$j(zEea=w-KT-S_7EcR&A@PZi%gc<aBN^1iQ~@#Y7A
zdG`6QzJJMe`)<AGb??9Xj7>M+vCH`z@1MNx(_0_7^Idlz^5!p|y6W2-??3yx&p-Ik
z3Gce=ke}atLgSW=S6ubdU;gUR6Tb7Sr{8<?o%?*}<cF_%*{1J2dcrMtKmF%_bbsSJ
zcRhUk%ijFOP0#wy-Mhc*E06B+@FSmH^RmzU_>2>7{@L#D`r7@)ch-J({i*l<bkp!V
zocqR+5BGiPfUT#Uf$~|yEr0c;eBd`@e>cg`eA7>juXL+h`xfn`=ethvb?kMs&d28!
z?diY7{nFWu&dk}q-MY9Kz<cE{cNh7qCWG%hKQvdbcwPUJ@n^bKSM~c<bA7Jie%4=%
z?dKZN`7K51w=Cb=t!lp3uZo3lOkC+l#=q+Q1;^ox+o#hQFB(^Y^Y6IB-7e)mu5tB;
zipH%&Zu%S?*(<;98fnC>iihL4%nRRnGT}mUML=XH3zmgtdm}U~xWakH)+;Qp8(Oto
z#6Qag#uinpp5>hpjNrW69a~o|fqqR+TR)5Aiax$$!o9-dpGgag2xm`=r)6|Y;Pwh{
zbHRClvnS&0$(9j+OVr`Ej_2Cu?ssIY$9*b#Lw!i_I$#gO-)?|**(lUu65oq1w$YXa
z*c1VsfCD3Dn<1ZZ$w55c69Jq2odU{pzPi6|noFqi(OP<1H-^!k8JvZwu;))W|C%Ua
zZw%05^Xs@l7bEUxQFJ9<rnip9cth>WglL-Imp1Y8YTm}IV>mE^XQBBBj-X+yAh)kz
zJRUv9c6=x453&<z+?+v%f*!EBMf`Iv5ko&(fFlQ{&NmQ2W)T*_BqC+N47l?`x=&*Q
zpUYAr!ohiqZw2H>!Id1)TdGY8d}x6JdT>L)jQayp3i5N7;nA`#V?-Il*@*BypcrX)
zATtRO1iy2VI3Yio+f<(rmZs&f1%`y$s*9YAq1eW!f`mm9@ed#{$Meso8SK%0mgM+%
zL?BIDkAQ?16HzRQ8tW1Bh7OM4r@(p)$fJ(3*ma-!uo~UA+C|9g5pCcX;z5_fW`cy^
zdwH6n`w<Sq^_*9OJ1{h`HfVzix<{8<T+3*fcvx{Y=GZffu-RK<97pE@uc3qNi#oh7
zAMzh-Ix|@%4NPphzKz3$wffPl>!4Qvs@7vfd+P>hnwWCJ^a_5CT?$`$nmHel!k<AV
zu;PTBi}udbDW9ay^)-*Nn~WUsoslx}w`Tac9dXOOj}f!Uez4RdKkS=yFi^l-1uSAw
zS??~ixc2d;L1{KI-~%<V#$gswgH!t4><InF_acS0X73!A9`4mjNakE4m+i4pT#Nz*
z!_WrO92uNIJdJF@uWU@6&Cpk%seR>ZE5H|1xc9=cPLUNnWl^$6=dgm{0l^kJ00O>9
z1>P6ubJqOG3NJ`R95+<cq6|Zv+yreyU_8x@2NLM9Ny&GfzW&-=h~*etV!ULi=G;oF
zFmQa0<&uPb$D|n(fzJzy=oik|t{5F0LDBcogOJcIPjfUF;?5C+8;32%VH0Zyh}N=+
zPXwE@7GHMTdWJz!gi&;qkOkE|zl5ha<^d`yNd<N=3YHhNc(I9-u`S5Y;9i`0G>-O+
ztf(e%LH``r<BPK!u&{v=?mua3ozHTQKu`F=i0rcDI<h*%{msJv^Gl(v%u&VrP<y3=
zqmeQ0f?aDhZsnVpKnuO29s;T##^)&W$sD)<FP}w>5aAwnzb@hq2TS-<#v#$X6(>L%
z)u2&?fa_Vn28?}=ZBgw;!z@+@^RAzN?aO&vr$rH|nxdz^6J2qvn{4{viZ(PwfI}nr
z5P=H^=&=>PnnYhLLP9`?(~0MLvxDQbtSp<mdiqJA(=OnCEa42N3(2QN*jbwXQXa9H
z0t>m>8o}biT7@0E@9!}639dLiOM~<^+eCs%^OFq3o-CFjl=e>3H=hO{64XPbiwC!S
zYWku*xXex^cnRnJuI!BX<v4k<?%+60TW}IR4&da*IBwWIyBNgpc;Ggy<vR(QP^9B{
z{a=JXMg_0h82Z1Y{t-9VKQl0at|r|(cWJs1T^QU0wE6PZ1UAOm2yOwt{})UA2^=U_
z6j!=&Y?GLb$80>BCL`fmixU29)Z3av(<G10eI$7Q;$fHKJMl!RiEX<BcGww5(P}E-
zZv)#n=l~yu*xfKs8r=I16pMJ6+#W;toix;xzPuctSeh_s#OO9-SbjY5VUm?4Z_|hW
z7)b&WbaCz)=U#ONFkg?|62eou4CuT7V3$l2*gwVSfe!w_kCiRrnn<XF34Sm;P7qEb
z!F*fQ*#{M`z*Yxq2(MSQqygq4qe=@8Sz?zM&jh_e_@;mE#)^!v7v;K0k8OzTdUR!S
zkjUNwGFZguFd|pWmK1V!ubecCTrT*x-U8j~aT9&d;Aq7JHRQ8*GLE<nn_{=fW;d86
z*TqA~G+4q}Xo6%E9nu(|cA4fD^JCy|p;4^6<U-De=zL@r&2T7!<v3C3H(SB32-pFv
z!;}C7t1q#tuo!1F@&O@7c3qz;aT+F~is&k!j?%))TUw2Qs}9>i3Y@rU4u299=W=11
zIx^o&zZjR=zFcFQx+`IjXP4i8s}8;`JA93YbKFc24dx8&TgL6$KgX$vYI7+?c$fQ4
zzJvwG8==Pt2_p<5=k~|wOd+_AaC<46zRxE+9kU*DXa$@<n_ZX~3&`1@M#FPlG{Kr5
zf)fRF9fUN92;)SKmK;_A93Ddej1m*L$LFav6B;Eu!~t!K7ejBIAfe#eOIhJgLyXPU
zN^k?+F#qAe_!1im8IH~X;k*KTX_Qt(#7vt7?pO&a6=|HS3m5nj7aZsR{w|bWVF%2Q
zvl_ic{KL6s@97}JSvhu1@fe=<`Ty7D*k~1CjR_B%1$7W>WVvQwu|AK{9`>NXeke4b
zvK&68<GvtSMec;Ak((AguQVu{gevV#%!C6+1njjQ^Fa<`X9&E`C00`Sx@oj2)q2=t
zC<vN%WwHpCuXU3sg)n5gDyp}huC55(thv75hwxYUZp=D<eyjy3ayB6ez1XtaV(1ex
zsd7IeU$jOMFO;q(EY!2#fQi}y!1U&j8=w;B1W^=-DRr7l1ZX*%w$GJtHq{>Egvm06
zgsxc`c0gLy^dy0LidoGMYC2qjP?3-ixt!C%s=&nh&5ijU&Z8fz>e|)@TTLx7XR<xq
zLOFPNO`(?wA$wR3cNc{1Z7I}Kv)(G&4#cn?uy`U;zJHaFLRzrLnG_L0>~;fbk?k=A
zcMb|C%z)>sh-=x*`aHyJ)>*->)Lpj*^9B&iJ^oRqe9uFBd<bh|j*0u0rO=HSroJ&7
z4odz}0*;N*12ViK$LtGAW@~@P>68Bt>jN|}_c0rzG%wMz$zr->Wjm1Ow70U=n(HOY
z$$F$RusAR90>=XlLok2p8t5rGNx=$;Fukg#-*uI40yS-x0|7*o7%E9Dg}PLy*jsQP
zSC!1~%CTTNOsD99W4dTD4qb2W)Y-EsX2MFw`AXsg?wY>N*%?X1Hku8Eg1x81OBkiA
zv{6G=q2UB`6dD9(APJ$(OqNh*Vx2+S&F4(wWa{bk3>JDuHjBF9AkDKxjBa(=AoqkR
z!9A12cm^Rb0|^%MO3+L=T**`sab)l4C3jT25s?X5g-n25CAeS6E(bO(0|w;1B~8OJ
ztj#Rel6%1TD{B?fHqXS$#o)>W6~RSI@%gQhbICqUMVHXtHbSdsbSMv;t!Wfmeu6rT
z+jTmZd6Kbdk1b1eJLc;`J~2&Ww+OHaC}H;b<K%)i^)Qt=Zrpn`xKr!L!w<B!Jraj7
zw@sCGZ(?+8q-<mHbhhZR570ye3g00)9)HWXBHW<P<``mq=%}it$FXL;oUN~J1sbQ?
z8fon2>rJv!)bn7m+Zg$PFc-Nrd_;C$BK$(<lsr2(hvgAaq@<paY*hA%5UmbTW`h;V
zii7}xE?S0>9hhb`yJ~={&PHW3)OGjqz{+6Qf-9`S&=_^lA~csV2M^c|LeAZBnKemf
zTRCZcV61X;U7h`Gg$Tt!bzG3ew5?b33&jK-#wn_DJy&WW^;}RJ(6s6%M%Lx=^PKRp
zm8wcGRs7(CCfbKuS*N4hX;@Q!xUP?NCZ~Df=KSo!DjOsZfGLH9+E^pQ&_lh}oQS=n
z_mj(zqjz?MEzJ?SzzNp<z!9@SE9F|o0GIL+iCH;=CWOKZc5s7K=KA?ei*=~vx$721
znsR3{9b>b%GJQ&UP5FpCSqDoknr2L!N+MF6*w{C_Lw1i=R$(j1wwODoZ!r%@)2{Bh
z&OU-v<It$IeBpKtscyyVBqb|w?_l@DTW>QZqg)O4sgv{e|E*zem@aB_^UbZ%Rt&C)
zgAq?^um|(S@qqtjWR@S=OLsI@d%%lFKY|X9m-t(YcuJN3M-13C<6hWXBkFiWu-~p6
zFIzJqI`rudjBY7@Ck}%ZxDd`VZiX;oa|?J7Jc%dFX%uZyK^Z}L_BeLq+$^uP=s(v*
zd}gyb_=uYx)HjDF$6&>0wb9D_5c~hK_xAC1RaM^jI_I9GCn0T5LRtbM>|8<!@0U{A
z$Uxb-jTqj>P>a)H7`aUgRtB)t4pgU<oe(jiNCZX18NF7(%Hv=y4l*!<m%?a4W~jw+
zcvI4XSb>39-qIGz@B3Z*oSU@ZZ{+zs|NK6mXC-I9tiASHYp?x!_SyFw>tEUwUX6T1
zBsU=ORVgLqiUPG_KL-UXwlWQ$JVEOrKb*wXIm{t%2YB%|))*6)d`F56>Cr?gkV2p>
zk3JZIMvIpR5M$}cfUP9B{fR5a$2sg{M+zyHnqWsfXfzIS@au(r29T1JX+0-jfhC$i
zR!$5GX_aFh$+SpPg6`0X#xfR~7!(2*{^3~offQj1hiFe&gbO&vVxI&$8ELTac{dhX
z%;zRuYl5>0IM4yX4H5vVFtD&e9c)QMA#Y%ia|mJXlvz;Q0pE7e=D<J#W1Juu^C;I)
z&;bfxe@PB^xdC(?Lg~OW1l}40mqYINWo-%5!rZ||p2_(P-o?(AS-OAyH2dga(s}GT
zE$f!`w2Y42AC5j_lVr{jElX$jwrpHh!gt>850hgLYxrd$YS=isux|8{`*QXpQ|dR)
zSk>^@($Tt6;D!&`Ysxvx8mBBBYmt$q8|x}zJazx6E%CFRow8!o#qM*HC$H^@8#<3$
zA*D<1iYuR8J*8X|PhL_uBF?W|5?8vu-B9`NXQQ5Dk7!uaxisE-<;djHcW#+HdhEkr
zr@o(T#;LSt`s(Msaozh@zVcYh3S7?~`|y`XH~#F;Uw`Yu{YP+p6lv?1eXL>LE8m;a
z`^xX9ypFW9w_I}cwq=jhjV^m6Sl{=thD}#&tt-88!PM7ZyI|^Xm^RwdTw3<nl=E@@
z5^2wzSg3jPvTG*q#5FqFlI*<Wt*HFkep9~l>hV)XkoGs%e{b^0i4VrlocQ~A?2fnM
z7yj_)_4nPgcJf2GI_^N)rydTd?@2e{9dCcQc*@c@Hr1@!@|1jL^Ha&C$2{D)ZS-fg
z&%Sk`tb6*xWch2?P20G1mGo|Vp?2OYFVw!e@n^M<ZM$UZsCgu}?vh7xuDD8`ICm`A
z_{L$Ap8K!Er^c(7PTe$y;bPfiQ*Xufz`0{}TTbk(+5W~g!Hzessr$uaEzyn}-jdeW
zjt{rIc6a?|=v#lsHIp}A{`-cJ%YPp|{^Pfz)vsJ!zu}&>b&KxV7@Ts)Ki1$3Y75T}
zJ@GAk>hIBu!{yIB+;aB9`}Y0j-}bi*&weI({Z1Q~j%(g`*0Ig|7VdbsrFWUF?;Sm&
z{<>F>sK5DD8&|eHxmRh^Uh%T~Pm|t7QtuXZ)va4(>u&C|bsM)lnOpMeP_*s!MRg<h
z_XQ`<?W(f}4F!u@lgXx#Og?<=kW|iE+wj85wkc~m+osH&f!6%m=E*O-wjtj7PnGzY
zX~XfW=q0x`c1+$JbWC3K?fWMG{p|aKaP~83yx-Ap+bu6N2g^numP?;`SQaem$2SU(
z2w#8I%Cq0KGNZjYSUa+p%qvPbZ=QskMvn-G`)sg&<CD4dqfh46Z97e#y>d~oeqn%K
z83f_6HfSv*LH*jHsO8lmS^aun@QKd0aCMUlHXr1IzSbo8{XbQr_04Oe&GU!lg3H^&
zC3xI>YX9b%uK(OzbK7eb?bAFrbkY{V!IL<cFBW~zwp`b9j3lRAf`O+uapk1t{uw=3
z$@WO4*(Q}{X*@Qp4|<bRr8l<8@Dkhdof*w_ZeDX7pVghj^FNq`tyf{}xC#s5N*otm
z%LR6;SYGw5*oSG2?kIOgOUs>NaIZULr2g<iOB^>YkV>#G#;ASkzuo!}hMk9my1i1s
zUP?#QFvT>;rJ;>&&oN0abOXc#4)<y^;^aR5oF8fHF$yltpW1jyz8=$lZ`_12%{4VA
z{qvfWN@S&e{s&>YtCIfKtCD01#=D}E)`e@5g}CG_?5IP(QRsCHF6b@gR@`|P7GM#v
zfO?CAeiA%{VGH`T#^Gz%iL~RzJqKfQrru3Z3S%?|GR%?dbqOa2!KMR1;kd2r9g2Jo
zi8&*n$JQ^#*c|+WxU*m+o(p_{c&kNmFpmx(JOq01kSh`13s)De!!d5=z!x}_kUYQ>
zeyaf^FyLVYc=5L}wg<o=j49HeX&SwrziHzrY$SwBfDcW)F4%U!^GzEwjXar`KI07g
zINn;7;*`b^>uDG#<YO}!4kpDcA9XL{n#hxMK(@j(S}u4E6o3}4a(Jfc>Mt|QFY^Gv
zEQIc17b98-ZbjlvSBP1p8Tg9F<}Qj%GypF>unl=I_?)p^5H^4o2ZlpC*O0e9|7!@v
zNC=uOm^$I%&|6@zyBY;fRe|0K?51gQxR;&m&HPyRz+7q%{dV0`zHXr>jr{)#O|?B>
zVC_a%0iBgzJkak=EY8z`2l(29`h+P7+F`|DJ~VjTX>D*LYHMR&l8PIWHsE22nA=-F
z!@Oe*bg$_EQtV^1p8Ug`uRN&VuH$>2HeB}f=*o4c?0S9svr{)+acS_>$DbTqiEr2K
z+PV01n?AX%?%~TGAA1$wu3NQp@uW>FxAlK|*7i4F#kcETf8o1xcU->hv;Te4<8MBD
z{e^S3J^1n5+ZR51-y^f}?YevL?Yiylt@oUF{rwl+@!%CN;oEgPK7nu7{r1s?FTV2N
zs^5JBvM!p_xc$8AOS|s){i>t3zc_X06|;l4j=N_m&j=lOqsTWdT37e`L*8Cmn%*VD
zbM0QqTnpP_bg8pgELf=&Y`hVRoL-!MpAW+#U%cTME3Pml{>r-Uc>X9pU4Uotg~gL)
zY2QHo#;!_Ox&-StSjGs(@p4yOD%m(VPVhPngJ+!ipxl+nRwJ@x5{UXs(!UTkElX7C
z7>uMV7TX#};W2HspZS1^a4b?P{Sr{$+wtt-uHX_`^X+~eKb`g*SX%)t2f&Iq3@9*`
zg3AJb%+Cn2Jf0t#9cnYf`Mfq`5h5uI(+8<4X8ikz!gD4hI)+u@IJ9W*h#B8)@N;gf
zaf_uINzhz0l{B)R&U|bJIteY>S3n8KZ{Uf;HK4Awcu@j?c@pFMI(g}78Q^*XgD|&m
zssKhHz;E;-3r>O5GM$$~+{f3AMl#Ihtx*(s<0&$NS`4DRUBW!pknF%z4L}_R=oSz#
z!{ix-pk;T)ZywO^NR<Lua4n7p)Di9`rOm=IKFvs-211q_XtLzloI9S?lH<fkca;~C
zJy)+1#x`J_)%>bwKh<ti-GJm1eef%iXR0-jwu`cv5qN3~;Da+epeVse9$Mf)5hVkf
z%nX=<1e~OV3xF{!6dCpkVLXix1UCTk>B*mZOPR4&2B-m8UwQCMQ3x~zV;~p&6$1L;
zTwo0R0sKUoqYqZ52LY3{9hh6Nk=F%fSclfz?L+H9LvXOGp${1h;O2qN3&#?aA(Je2
z<iG^XZ7Pj1gF5AW3w<rMaDwXa6CqR{=miRRg2QETg{^Q@AhoAux)8@%tzNV>+>zvg
zYqUV=p%wUqqW4000WRmGVx19#I%FJazNQUm0#YhYqSOy-5kTG5;(j&=rZO4%4EaU%
zmb9GNoaFPGq>iH-U{OTh1kf(sdq6`rKsj6`TzDja2r3hB8;*!>I))*VE7I$QAY`#W
z*K1)JW1N6S0Y@wyZ9N8B0p*WasSUN773<kSD)V9zg6l*KJmIrN=$KL<1<_s|LYN8&
z@rxkb94a{GR8r<*uSS1US&o_@&8UY^$f%{KdlwYzypT+pQ~|OiR7guX7`&MoFP?#m
zyJNVkaS^;|Usa^hbk6Y#wBsP(D;Nyx4JlfpGW6Nf+`uUphX4R!PV`Yx99u4R$|im#
z!|$^FAvmV75C$1~Gz?uy!Z!w0!6KwlIFSqx&myTh0udc_2wwYWLROc=&gWGEm^Kxl
zQ94=N=jBlYQ%z$?)0xN!0C9k!qjG$lQ4dktloanW>;#{=fKO{Elp&u+J1?54;ZBao
z1dy`-vp_ii4}{es@=-Yc0eC7-)ex!i{9soKjw5W^#7!Z_k51BM#WbYVk~Vq~7+-)g
zS}I=yh@+u`Ns$3EBMh`u9A__zvVJfMB0#DKgg4kUOmdsrDGb2dW?ax_18}e$mPz8l
zXh%ck4QrV~P(;;4KY~P#r5nIykTv#$G6*sGLPu?{!uCqO>%Js1V;ura0nYzEj_uFD
zthh;Fk_>m$^VFk-K0qO#K`%xs4iPaQl8{1ALX=U%+MV(476(2|3aAU9cSz~PIf%pW
z@mejX2<*&p!?0f&flrM02pA0An#I>SI(bx_EVf_#x<cX`#2HucvYqD+dMvmlIbHR}
z^uRJhP&7XX(Qgd-g^^Qrl_bI-Nqxl)>e?MAE*Zn&BPO%^BcCG;rgh2~<fMVvFh^d{
zq$<|`xyWBXfOP0i{j(8Q*(e%wKh5C7>VnQph@#>8DDVK!7?YXmsi=2zQic<VQjJLL
zG*$UIH-Ut9c~{^~pUqN9W5*Rv^Xq<QmRZ}T*H`VRG{`bR2i#Al)I@UbBxHFQrtQw%
zz>wE!T(@!IOeJ&VQyFX;b&l8+xCHQ!PJC$$R##vnOY<_IQx`fe-lyipI%3JYABpI@
znGzOQgR6iG04_!>0=_S2R6w9_4fP7y>7BD;;GiJ{BsXwW1qLFWSJKSdzPu15DL9>U
zk&nuIGB75ej5}`A6ll8#N*YX)yHW%BY_V%a7AB>SI4r|TI)niDqmOEKW*b0?K`i!b
z2PN}~DT#k&Oo~eLY3xePXLLy+7SA8GvkXI&1%ItF(9u`DQqF1+aln#Srbj<976{|g
z!Xuo4@d5QxF51U|2Iokbc@ntnaVemmV{G!`^`ogi^DT3II+N1wLM2r(&M^R0eu91(
z&#X{NlsfN*tERt8;=7>Kkkvd0n2C{Uc|20*vot;9mEp2@W<%|(q}_vuX4mqkj8c#J
z-@#)dZg=vuRqcsHoOb-HmEQDKh7;)az-9WALhFJ0l1A6F#J&rpJTUHhNPWXtmT%8;
zr|~R{W}HYfAzZbc62ZyrmH8>2`jX#nJkzwy+bxZ)kUS>v@tq>0_I@?bf%vU1^YF?5
z<(t@E6`f{KTcR9{R@Xs@RQY8*=x26Hacawy&=5B<(?r_LPAN`lNe?jUdMC?HTV`QR
zN%hlkY6sF(?U3=GV55wde6mY%bV!FQlc7Fw6Kq!HP5M2deuqd0en&^hWc%2Ab2A0r
zTdx0+`d!)nf6?=Ql=vP9`koNkruUKWArtEAT?;i{hwq8mpFliujH#0U@7Qq9Hd$r%
z#{y`Cw9(z^B38*vl~_Zbr@Ax?cX(28<L$N@vekw@VYZ8HmIbXoYxm<uHkzvC^}=Wm
zU7~1$tFlyqp2Q0Ton@!+IPD(3>a6CZgAIfXsv%QVBFjk<lhHX1kSB70HjZhdvD1Oz
zf`kPimN9V*Q&~hK6C;j%$rqKc9#N*fyv^Wxn^-@Zun1}y#1Se|eN{1tyV4X2^M6Lu
z;6eag3WY%YslXHq(b&*%aBxv9L~w({s*52P%S42|&Agimv>@k|mJ3)7`AUeeYs0w6
zCAxT~7#9U*d`tvF+Y$Yc&U*({gxRVA&ts41IO9DN{+L{9`#%6#?aA(sW`P+LGJhf=
z+sO?dAICtaRxEc(3jPQgO*7I8U+-N95x|dCi8k4C(V+@`wT9d+^i5qWlVl-p?o%sU
zaJ58YGrb2P)rkUqX>bQ;G!<$fO;ZOUChc3}0`Z#)7pb8Vym!V6#9myw-GE(RG+f1c
zf#hznLByEw7Q4Dz)(U|t#+O@JLQJZLDnlEszK3c7?`aun^(rG|7*#NyKf}sN5chpa
zli9peNJDJe8L+Q~h#=2y<4-Olm>`gJ3fTq_1ez2jE(^dSK1ek(B>Pha;~|@&vZ`Qw
zg1~CIz15Z4sH-Wo(d7?noa{}t<)n5{K}H#ZsZ&C=P*p9plg7LiJTL2&Fd`GwuBtVz
zAS)(Saoi5o4G;)aVQhut0)f@LEJ*Tgg(7WMbMGoJyEP?c+GG(jj4GHf^k<v+Dv(Yq
z$_~|HKi(KnBZiB99S1~}XyD;;_`{eCy{IzMs4jNM96Vfzfg3Kh5n>jMEnQqOE^XMf
z4;nbJ$`pdqKlCqY$U~r^uvB2J7e;~DGvh8C7&|2Mf*=azrTxqTM}dA!wha(OVR|vm
zmy5R1iy{JC@D0=0PMU9HiBUGa&{mi$1Cs@m-c#t7q~fu?s*oz^BUCp9-Tn<VGTw@M
zyn?`53No5Zl@(0t)2phXZHRpQyrd+wPYP9m*?2?zZfz(fv{f;%QJS50$Y4BVGL*=h
zXNx?7XQJLlRs1-sDr!97%RC;RNSuW;KczC`)TvE8qFT5#U9;`UKg)|UO=SDW!WsF5
zqE}IS24a?f?E4-KxfxIT2G_*664k3ao{&c0;bj?_z;G6yShh5*Ng1B?wg+C*)B3E^
z(iSN$6G6WUOyk8$AFp`dEGERY{%`$QH5&ujdOK5jPhV&QUPxeCmX6>%?n|qQ6Nym1
zJ@aWh0G>0tlBPBw%Pgz<x)uO(LfIM4Xh>g$iRDb`CuRekX`Fu(`T)+y*C6JuDusK^
zy!G^?9Q^2~a*c~OTD!>I(6L`Q*tD@F>75+ZcPwcr1jV_%?ZJMzC(5mIQFu*jIa<=w
ze2ks@`EcgV-7V$dD_6-sxS6#bdw<B?P`6)haK^?Y>2*If^-K7QfJOMg-F`UOu(8L=
z<koWSl82*K<h=&G8<CfCXGRDfBL`=42ccIu^VV*gmW(=|_9`M;YK!{yTY0EyM-oE^
zQ0-hg!oW;^n6lzDnM0I<Hy)`q#Npd8!O<ZYb*l{deF+b~mTVd`pG*U(Uaf`jbnB>-
z6Y6|WbZd;ylr>l4GhI;I7nTMKHFzL<Ytj-_Oa)xNXmGZ*H);%XS2si*Htuh9wc+1~
zokjVG>z7hXs}w30bH>RXIH!eQ;~zAb$9K=HtMml9;HpE5r3a#Z$qju8OS6(mf|KJf
zN&#;Q>Tkpg4I6I8H-65<izWI(QwY1M*Sh^ge)QFGy`Z)?#l&Ky;rHUDZC81{2cB8K
zdoQB?C~fr4l-<hq&g9)O6Z_8YDb-k21ns!!<tm<XcvYKUHN^+s4WH?j`Q}f^vj<64
zUdCh3^moNq3o%apu5{zcyN^AYo%Y~UEhEyaNwm{RUzo_L8YaD|#?k=V(K~Q^(jdN@
zzPm+`md5u$S8eq!?EWZfPaY(EH{2g(@P8_S@5+eJeNWt~^}$?!qS7S$lSuz0qW7R~
zI(}%53E|z!@E+J@q?wvkKK2t?(mQ?H_<s{JIeTXRWBA?ZCX{zK{Qn;#wBZJvwNHWL
zKxPB_1{doh>!S#2dbamZnrdC8;cEUgP>nM)AdBxAQ5j5pH~VI|%-76+f&==A`eixZ
z4VTHS>Ng>86_+u9pW!lpBF}6*RUB>n<RKGs{@>vLK?`8^0?fYvZ_Vl6jV<cHr3f4k
z^R-iLJ|-izSzy8>sHkdn>PCu}f`p8|n*7f8I$?uLo;^C_Z#1C$TbkGDIfe0?WPih4
zRZu7~T{Bx|4NOO>1P>c2is*4bD*k!a&?pk^5&>-Pg_b(DDKg~`LJt}@2s=%G*YzD}
zz)O|(={WZU<0=H;gp;zdmq~s7za~zwk<ag?+iKTInWP?AA+ra6m*B%Dy^REpFJ4pN
zIfZ3w#%-T*7Hd)-#8}c&Rb$}jeOa0xvS1Sc4~Z(&(5=d+?J}C`QP`z=4wz^K1YnQd
z3dzHw6G83ew<I+|k6%WXB%Td*$TqWxB^Y&gcT!xvO;v=V{$vrzsK-R=)OKEgPuG{@
zcplEscC}wb0xbjecgqYEIA%YT#;s6YrmB+Lag(cg)rOjf_ot2_&(50#Iuz1Wy&d;w
zt*9AgTUJ3Ej)&@zEz;qj4BtPQs&0r<n4lsU8^!sLP8rpJ>FHi1(uaBK25nN=G<o`l
zl!ev2<IbLOrho+i{T>0Q;i|*2yoWy=0T_q`*9IxzX4DM<Q$*b5SvV)s!9;8@YW4Op
z1G(Y&7q&BN@Z)S+AXhLTZt?T0B?Ta=T`OuDzHpepv$D|VG2GL3BVfTcgx_IUrT~H<
z$)KYnM%yHm4p0N=0lf6bvx*f5m3%t(QK3y0xEZRT$vK>Kig<on*^1E<s%Tny`Ql-g
zWRZiT&;vp|P9R$Zs2cTXAcC(D7TLF!k8lSNL^_}sNrxH}MYR$yAtC}E6-B{`zGv<@
z=V|#`d(ROFMWLUXf>J8N&;@XJ6*`bZ2vwNL!Uf=$VN}OzBxQ!ecuk;+K2AuS1q}pP
zoF_EMU?JC}hrqzp>G%n}Z>mV_;?p48?4S>RZ`FjaQ<6ci#r6<ZM<@(w@t(&Pt+PZb
zia|#F`?8U~gC)@;a7_VK(!|u{mJ9?g4llzEFt!BJWDv(|;W#Vx@~e9xJOC&|;}`;4
z9qGs(3eY0ZsYCF7J_89Bm;Zk054st`;EJXbHw{Dv<c9K0Q0DIJFuJ2Ht43i1m=pu0
zmwD=uZ-k*NNm>kKH*)C1_P5pq^Kv6c%Z7HU+tB1)&#{lZL;1WEOQC+wlQl<+3?&A?
zmta^0AymQM2>V!+_=Ciu_Pm}FS&yF^42GN4#>|Oo(uRtVa=HbT;jk->AN$5)McHct
zxY`a#HMp!k_6Q`lk#r2<@mvfG8d?~y4LmrW0gDYPKcvS=b9z1u*dB8m_Y|NCGNQ30
zlLUuQjTkKwzh4^5)!K(46DJ01kP_ffE_!HE#&4GOZCfqv_>O{sCUx9dEQLuBbc6R#
z>%)HVR-mmNLwKKcU^$an#L>nmM+c##Ca@?=B4vs4Xi4FjG`@$(!FR*4g*PNuVTdxl
z2KjqY!hkPlvm9TF;ACn9wG^WEz5`l9uftE`;g>1LLM=;~Fbp=uP%TIS<XLS<V;?s4
z&1e%6x<RlCBS$RBl+;2G<nBV;;FlQ1Fy=ewPQrb1p#OE?4HXo^-F(CR4wun?1gMH7
zUq_sWE_k7ZLqLwu!l%M|QR@`6!YR}`V%WXLAsP=tnDa5!UusO2rs}EbiAj|WQLjn>
zHyt}PT9u2Ks}{i7Nctl74UDsJp^l2qCSRZwPv1j`5~rdv6nuv(FysA!7~1v9FN2{c
zM;k;L+d!z)Dra0NZw<tu0RVxB{(uG@gT!gcILx9uHK)ZyjNpHJDHcJ4s|tfYQx+#R
zE@iHc=yDD!qAL*cxQwa+93Vvh*8rVt&54|fY!Vj<dxNJ{I*bZHs1%KlhaDvY^w_HL
zKaNyH>I{3eXt&#s^Mq-NQE^UV99v+dI(P>B62_rSRx9klK*SD1DuYI-V;-kTpc3+V
zFeUo_l^$sCYKai3N?@6Wj;TIvg?`Q#FyrSy$};^)2N;XoN7~dJe6er8K@6e+T{5U7
zEOoEtDt#O*GI2qn;IMY_7SyrPBR#o8#1LUv7T-oa0wP>&jV6*n$5qM&p%rXm`w2+v
z%=Zz#f9|V?l9UD;5NoKJ(>S?nR;70ulh%N&uq4sCMns2EUx!LTaTWqGocSEF=Y!Ev
z5qv!f)!<kT03mF{PzKtbj115K1mtJB!KIuiO9Rk=Vdy{~OBYV?8dZE`(^Kt{4e&-u
z3o?|kpm|mKlt1$WikKrU1CdeRVoqT+1>}Ix)Y!yXI-u~ZN{G;wZ>%R;JMP3nF^mQf
zKo<V7`~tVA4M-!75rE^6pv-8yB2lS);0a1bTLF!5x5uhW3e6e>MiJB%;C1tu>HyAY
zx97&-F<v}_DcDrjgzQi{gH)R=DkX%{`{5L4GR0AXg!dU*UQ4=^f}X`49z>@qj%(`G
zISiy1&QHk=>jZe!!YI<ITUHm2&tz_FRD=OrGPH~ZCQC-7sRCy=$mCnq&bkSf0}83w
zqsTJcm~ztc5Shb;R8)vz6fPPXFi;*EWu;A!m}fH5!mlvE94(s1fGVqI?dYmF+p=co
z)JQf~#KB9!g8M0;00)d0X?CU&rx5H$kDD8N0`V4Cx*}jSwJ2>p4s4?tI0kf(gO5e1
z#(~Lfl4YzhNC)^ef*)g@V!VT=jH;XQQFuP5Uw>v?c!x<aNS~mD;xdO8&j2Q_0!yCq
z*(0mR=8<kZHSZopY}Ia@E5;$Q6Y|>>Z>yq=mIHWNy=rcfc@o<4(v)Gg3^P!T<W(jl
z=d{yGR7&iKBxF>MS(s>u^Ku=cgb;BgVZcjsBV5ZU{y2kVih19=kmtEDkb<jHDk96q
z_tF9w#ha}$)_cel^091PQ`I1)LfoZ6c!t5mA}hG1{6k;uA{J@=_2L!E`T>y&`VPt$
zE<l+1T5%ctIrvqum_(})1ibBdgD?>$&M#OA#x6}noAepHUOtR8|EPN+2Rkv6hWj&|
zZ`xqh28_k}V|VGEEF#irSd*KRP~}-|NpSrvA7C0#B05Gx*<e#-le4t8CEoOSF=!^N
zmkbIT&?MX!VEtx@u=<X<?He--Wovnr0hT7UT<Upypq3mF7%*^4p?tkgl!p;Y#b$k0
zlTAvbUTQ_l2=xKeiHaKEehiZdM%~o+3ee>no&6B#aW*A`rwCJxBRU?TL?BSKcL0>|
zKat7?F;Y;$tcVC^`7CIOHn==^EfCfK+pI<EK$fg_J|sO8V|+gFj&zpPTn5v;Vl)do
zvWNph7=m1OVFkzq#ygGy$ST4G4Zv6|vvrwkFu5Q<idC&8a8OfcCDI`u`B3dvnK}yb
zjF64LT+IZtulNK%(i+_u<7O<?LQ1-O*UBs@xU!W%8#oa#u7PK9rGS=@GEIvHO*7Et
z*aG}M4>*${LB@9?{)Wxe;Tj+15E;Ui0rWAH=%?2VTlFap>13j-O*IPR2A3KK4tPLz
zH3=~Q<~sGOj#6h-_y#0ddmKq%c?T~`M~Y<>K<)|?1z3+t)4DnkO&8`tAq#mDbqnfZ
z(%sFf69}jbgd6oHI=an-R8Nqmq&w?_suABm_wgpA6kKSqH%MD47zw%!_dop*qGM>n
z?`1j9%>ZLQ=Sysn2O<V_nv1ZmWywNRN(uCw`}tN6e34D|i}~|Reh2}8dAB(ZjM$G_
zMv>q7-)-}r0;3)m?bI=<!2${fN7e|@kanN|yw68%0va%Nc<GeLWL!ZTS{q*`p-U+V
zr%g|Cp+&+pys-xvgV2Vozf*z&tJ%Uxz9yP5nHcnycI?0)9kkc+3{aH#gWLFi%K)~k
ztQdV&QMyp;jG{t%TSZ$Q`y%tPTVu*EJ8&ssn@V>nLu=T^gRtAU;IL!>dIxAIEK^W4
z9eMbl)e=f!5`O=_7IC(Vy^VooCC}ergI*yg#u&_Fd|3weQBi)ApROqZl;zfUgD`&>
zg$0&Gq;04pfRUtFqk{o7l%N;6Yr(V^V;mQG27H=fgU|}Vzm~cw2^vur-I7ZTErk70
z>`k>fT0MjjEaIpWCjq{+7w5oLzek`|*URrnpckKshD5v3GR-0Po|CfBjt%@4D}3mN
zv|&m5uwjgMmFV|CTV4a!vT|yrukty3O5)(SXX#K}8NI4zq%W6SFypwmvv5UEsr(mV
z+ve+~rEp+F!^~L?rKOL~UA*wyb7kKH>gTu2nY_I8PjlC;Juc`te4l+9S`L^xb97NK
zQrHv>PTy;CL%escVQtcN;@V~6`cIqGFy%uv7p}N8xqQV~(*2c3qe%X0>io_f$*iSk
zo8@->q~5{L)t)eOL2^RNN8_2lxPNM;@?TR6GcT><yYY7XH@@t<X>P9N_=co!bag}D
z=yw_(TKlDIDr>*=`KOl7o;tSl*r^NF9)0RLYfn1$gkSu9L+2m<Azm{7cOSlR{u@&l
zulUKnxXxU>;vYV=c*VE={N8(JO}h7<8Iw-fdd0E0+857yvf=z$PfB!GZZ59eUB~?0
zq<e8)c<E)+7GHW<%}H<mP4k>L|1O!|`N}?L;#zK=IONj869=zc`*h3YYoD&&|G}?K
zJ>c=LO?~~<SEjuF>USnl-%ATP3qLk>(yFl!PdXX8o<I8ChKEO|)Kw~9nmo2_cJ8Tp
zGjsb7uRL|d+E1R^`G;%b6Mpfvh6}r2o4RB<^!@Zt=Hl9G`HG)Row?$BlfHRR``+LD
z#_T5OI_ZS5%lCe+{pa#*``2s2yK>=_yY`;@lOO)wq<_J6@v6&eE?#v^&E;?IOjf@5
zLi4=N-%py?dC#Qzg&S)YFMVv%svkXF`*%NjI++4pk9hn)r@s2?Gq_%x!gu*~VgKiX
z9UsoEeE!3^tFWazi1Fu$)jvS{_+MdXxjj5$V|y5lUMXhnmD2g_*NRKlURT^OY;upe
zV{#_>La?~?3(|eeYH414hdt~QbGzm&nJY85&Z%p=>+r@YozsG-r7@_TaX=6*Iv{BO
z>b$+%zA|s`_BmbBe*Brig)KeFik=1XF*_}oI&E68bnW}<+HkdZJa5kLygNVV%w<7m
zb3VBHM~}$Z+DGboRv!($4iBmK;;)O?%9RogUnv8HoUF$i+8!Q0F8BAYEq4y|?xEhT
zKeWx=W$Aq2E8&I1*M~E=9@=Q`IxJ`_^f$Hz*Eh<H{euWEW1jMfxs3-bnR{m2QC-q@
ze4{k9;6pbp(}HvCM}mfFXV$fTHOaLPCb_nbyTaw2TV++tsq&eg{gO2|UmNULd#%h{
z`@Ud0F1{~sC+<Z%&osed(bB*a$~Cq$SkqndL(H1eH|pxm_v`ADf5dijo1E1$bmm8U
z`{&N<t*u>C!eO+&+SUPl3uXYL>RBxf$>Q>SneGmi=HcV;Qn<)S+umK13iYQn750m}
z%OAyKjyv``9}AU}6D)w*_K_JK;odXsf#=TX-M82&-zkQ+j6n<oOu<ZV>X6#HyYV58
zmKiAD(hnxRqf#tMO|gVQ2SD8=`921YYvMNOW(uaJxA)4%`53y^*!>!yd*GxN*Vp9C
zmaB1nF^Gnbl-l8AsCSzbqt>LbU)Quky>ypPmc`|6=}z*}Ee4-1+b3#*?l`d<7JBRI
zJLHG;o%lAQm{Lv(rCib>dnX;?$#}b`G{iGR7L0r_=~;{S_P}li=N;BV@5LCd5yrC$
zC^{%bcp*ZZbm;LrAxbYzD065rB3n}6M#6v&S0Jq*<h0XdxFFmgX%S{n;>bt20mnb)
zBoG_+l2<{RtjF2Fhz_91x>1-6>qn?y(}|Ip6!iP0fnZS+Xx#I3DPPXtUd90C$}FtD
z(Y9icY%+Y2@A89`EKZ%t6?%KEp#XjpRmAjI0-6>fp8f<#<luu4ZFP#rL}?MLHJsQ0
zzr2pFG$i;SE@yhEg*iMzn$C|yB2Lp|!&TJ>;|RtCCp>8;v2dM0s28kvA~;-;KxbA0
zKIRk<!3?0?T`jPIm2h($VNn!1B@3iQ7b}PUnMS1`asce>Z=gL29|KMU6FhVfTXGH<
zUIZ&<DOL-{MfE632^MQMcs-+O5}U6vP$uX|Y6Ixh7zM||FG{3e@|q70In;}d3fMhH
z9oufV9^Ws0x%w`@1)meayZd&vZ~xuYdtbgc_vXxRjb6C!*Q;i2fBAE-U;g8|hi83j
z+xd5#yK2t%*^|~?_(uPK9P*8^m+p9a&YTBl&%J5ok3ah#vmW1m@g0|+^yA0BoBPSi
z8}9q$tetPpdh&_`-`GC8^;^rYzyI7hPrudvtyKr!`IobTx1asm!YgL|{EFG%xNPbT
zXRK=6x%|=673-e7Vivxgdi}YV20LdyeaXe!p1k5hd?)ITzkZ|ckvZR5x@z5Dt$Ltv
zORl>xh;o(n`=wDCRf3^nW->*NFwfz^#+CSXUVpH-@LB0@d!Jn8a=G?WBKajJqRf+I
zihLPg9PO3*4`4gKW40VHygH~|eO+$RlIGx8j8RE4E0`_^2Olc5<ZfuLm3q9zu^rFK
zX4zb@6z@izo-9MfEt96g$ua|bDf3#E$qac^@=<S4bj4hy6Ah+iZ;T-W=xMb1IPhJ6
z6Cl)ZgrZbo_jXi8JBFO+Wf6=Rp8%c{5a<D|?@0BXp-OJkP%C^qDn*^|(SD5>+^xoK
z`n|{)-+{w;lyv*<iS=8czi*`!tn4MUkcq7YsKEBlJ{s^7XOXSNNqQt(D`79%W*K7e
z{20sfAn$}bJ#`)0<0Cwb0grmTEEb!cdDK#fF*fQZbBCVVi1q(<T!8bdXn0az!lG9Y
zJsWOqjGi2_(?V&M9UVND^GSei8CnBwB}7DR2SVJx3`8-%@5wbUE++$6yA?vLYisa+
zPH99JZ$)acTnGbSX51?TIOveXC<_OV#uA?Ahq4zePy%J+v^uz`xya%SfrSjd%dhU6
z)oQ|!Mt$XA7z!T4QHu^xerp876OczVhKcn?L@YEYRuy8~6!JVw4^-mA_Y_z<6bKhz
zWYvbMqD*Z=anuB|5W|o0LJV?-c<HAhwd6pU;6BOu9S*}AD2tSNvY2vlAJvbT=g*TF
zJ%|xQXwzm!V>`r_2sooaUMtk2AtOA^mI0*hjSKn!eWqA^W6p$@MMQ^10sx;pcks{v
z8uVfGelp|zoC&2Cc5Ng@f^^>3L^v#?-!Fw!XozpsvEz^p$}kKs<=E7VFzPBCLVYl(
z^eB+HNDP}%ASai>LFoi@zYFpbv{)-akG0?lrDzW5+>czK6e+=t0`PMT0D+kot=-9u
zxXUs1s2kwa{DEv>$Oy#JQZ-264-El$w^c35Yb;s~>Cw*NB`v56gYQJ*OOb4kq~s^k
zlA_esN(GBq{)2V^ELl$JLX%g$(1bV_p?ma;<UxfeKDawW0Z7IVY?aYoz>a60e!P=N
z=+>A-uoy~*F86r@w<{6{PtBz{8TZWrgifqT#c4fAyj%%oNH9KN4n&dy{2~~5u8@!K
zP=*y2pI}KIB3+DSoc*~*@SR9zuO$YRfV*$R9Eu(ifd-8#i-%xSoLn&h^|FygE5qHg
z;I<f5SphCAIIS+Mk}Tv48j@*{vKFI+n4lHrs8)v?vUuayl4id2o^->ge{`}o%SgQ=
z63~pxuef+yd_2meOa)cuj7(vRbj`IiP`6`#6$GSM+BocDP(mxl*O%NEIS8j|EKILG
z(MlM0<e^#uJo0PX;AeoM$N>WgESxw%`mjYl2vws1>6l=|GONKw24K;K*5d)f0<l05
z0*3-3YDf-1B7UAL_(7TldI*2Ef`*K`!&rcX90ec=l}<8t0c2qdP8pCE#uo#RU<}$9
za}rQ7s(8sD5-8FlB)E&o=i1@hbO=#{w0T<~jLjNY3qG=ROK{eC%#(tlD92W9p-%&C
zjC?Rj5IU^uP8~4f5D=dGp`9GgE%lgM)Dh-(Gz5J+HmrXgvRC||V?hsT&>L+nV6$PT
z4vb=ZM4=CNAzceVW+W;i>_W?Du*k;sUr&Vo7GZ(Mc8sN!$>XD%;L;_HXg<mtAM?Y@
z02(lY^(#ZPqB7?Xo;&D*J}!W{_|&HdcRB`I1o$#(h^$Cj(;)`|Ls_&`5mdtl%T2Ul
ztSC6_qM6Q&q(XAYyAG758<p;G7OziaFz%XywuBJ_1;kg0oRTT2>BXz_2hihBK@|AN
zxUhhFvpuNg=xQZIBard}gC>q{VG{JigTV!_Dl7z{WfSRwj85EsfzHTAyk=L|#7Qse
z1E1mmmZKk-ItjaChjBKj!40_NZJn%^)+uNj3Ew+w^L%jMgKy>ZJD4vDjMTWVShSV}
zc*AQi)(bUtu>tQ>U<w%oPu<mv>|=-`Cf4B|43o-mgpz(iEQi3>(Ds`=RKO~IVK>(N
zc?=XyQa9XKZtJ#D7@+;&z!c=cut*w0#o+uRl`W%thUN7Lq3mF0k|Z+rD~)1TgE$fy
zLfLNy1HjdNA}{_cdQ<Kk5IUmpN=|xEOG<D<1{I8V8-c-~j);@m@dQk*EQ{uKP;Rvn
z0E5c2+yYgw=wzOwm!G0lip?SvO%qw?+lXd>jU3_%XkTDx5yp^H2cL#h@x)?f6FH5o
z2ND2U%C`(dX;@lAFpT;<mTH)47=`ZxjEG|+0t6TaYAyPt&!V`~Us4ZF<a0PA1|CPd
zDy!ktn4)jv1j7jAp_+97rvaUk7u0SBsT$2>XiW15KP_nrouLGS2pA-m!W>Zq9NZJ=
zVLi%N2OQE>AB+A0nT+5qcNY8^Be3Mirr;Q61zId56ca^x`T<52rwDDTnim8{3yuT~
zJ{VdQaUE7s1d9tD4`}6QQi+lDBE=!GI?f|#K$8;CZY9SUom4SMve<qBU;?#tQ(!s{
z7osy*pi3C;xv_0fI&9J^K(hu_1~Kc<M*`RyVAQpm7o<U#g`?sy(pXL$&<TqtaW<t5
z5#|yT17kBeA|1@Nlm<x#g(z@HN1o8@9a)fdkOp}X^yNV~UdV_CM9CM~pqtd_U59nx
z-Q0|kM?tH55Yr>#ZK*cM6IsVKsR6%=(j9Rk#bLqjC{UFnZws23=X4C^Q12>O4XI0V
z$CYk%>4PyI;Ee*7X%UFq4MI(W{&Ckh-hdqhMZg5zMCT;cN0GoAOEf^&PGU7o{h+$V
z=OdUMLA5~}y0m8oJ^+h<N1lA*fq?b19#Q}*2js}S2QZIf)yEV=86HR<;iw#9m^;X#
zl<8ZgNlE>gr)@KQ)HyK0>Jh6oMT8dGak3)N^!TSK&>|7)V5AC4Wf?sc(>{F%6z(20
zQ;!&6a5qS$R3&O;JVT-sEZvY|DsVmEJ_)QG<H(DDqh;|*@q{&@-g;vg9}jx{{hX#T
zQwgCQ*t%}924TaQ-60@Yet58!4c)WNS?^<H_F&*yAAF~)t4-B|XGc!^xu;;(#1-o@
z`XU3y!a)z<)*0@s*g~{4@D<8K@RSu4fbUp#eKoX?D^UcrN%i4WQ7cyQnBN_XmI9u3
zF;vjXNTpzG5eE_#fo_hVwQZUKb?!6(!JzW|A=`k9mc^#2t7C67BAI0AfuZ`D#lQjg
z5ljKlHw<`AAWiLy)s{zRu0g<gR<z~nVP?()i88}ghuku-9A+kfMTWEztwqRrUS3J1
zOv!ma0j6B&0g7rV43(BKuH?O@I&2f8Fs^M?re(n_`Zobg9K9^nD@s&;qLv{LYGI#l
z5XE|n6jekj37ptMb_c6unT(7vnF5?=;UnJleNmzZixaRZIaMam))`m?94j5Hj3T2R
zaTt>{Ji&3}VJF?*V0Mr8EOla0gx>1l)T)_Oob@bI6{_X~7LtLrV3rl%A?$#ou@$m%
z2BdU?3eHG1Ib&K6a>EoNOxFAmObIMB;ZWuQjhzACT9CyuMnk0Q1rXz(>ZJ|?85KeS
zqqOA#H!%cI4BSeBv7K80R_U{GAM)aU%N3MGAxK|6<q-KvKP#t1{n#z%dRU~p1|AY@
zy6i~%8Iuffpz88EBJA@+jmRJd(3VF(vWzOg7}<)*vjx2x$RhtSj-~K?s`Wus)tWlO
z+kRqN^=^+Z`}1Jnxik`l#OaIK8OXo@&HFUU0tCjZpvgQ#a@Gcw4k1|$Q#Qj6w`$gF
z0Xrf)1YxXnNFpnf(pk_Tu38|?=>kNkjJC=FO(1Q$v_gvY<pWN^k&+ZPZ8%0JMQ%Al
zVI}cn2Fd|$y46E!<?NGFWL1^{FOvFkjkzodC-{hI6?y)KsS}`vVI(O-Kc{J`k0;h3
z*5Y}>Le}BiJKqKhzJW&{V6zV9zh5e_QVL;r8mLZRJ|6OSBo^7UE>xJ8Sj}r3D0!)B
z8bCO$I)k7Gllm45ElZ9l3&5uBw30PQyZZniS`gKTZ~$Jik(@DzB@T|UaDX>Df-+Kt
zvW9e@#p6;gS%gv3r*`$Iad+G<DNb+aEF!K04w4N#l!119{{VxA4vfdUeWg$y3CBr*
z^V5!om4G2qI0gt=TSrjGL&Pn@T4b;VQyoi`j2RJUBXSx9t@Qzu#&`2b2m2tK8XeI*
z_-HuI<=|T%&RiWgAa)#V8Z_{&>cG#N5Oh#B2v}V24o1-yu2H6tu4Td0OC(^yO1k3`
zn;4Z|b@ltDjv0D-u#*^vvce8<qY7hylc87!F<jXBGzy;MqJXDk6TxcT#-S@95&aIw
zqO9YOSB<zexK&|igm8=X6f$>2s3U$_^fVf^1$RGqYY}aJr8OeXBA0|k#25NiJQ^(O
z+SW-hFvxz}U?nhl3kGG5xpf>9^>Ok+9eh3!9br$0x{l&;f56JX2!`(($y@{WVbm?Q
zD+o+j6CfVSfc|VlkiObMy?hPIfV^N?!E=%jAwXM~$?hG%&xx5ULt>pl1f~E}XpJza
zD^VNf5i*Eq%m3Ji6y0bPJ>8DwKt#9w!`f)T_23~B`b{@Jy;0d8Y$RQbfz^_Y;&>m5
zda+h-2#|(PKcHwi3v<<XV6O(rEj(Rl<-WMh`T@8HR>M7DpA9-ta(iZ-F44>79%_o?
zWmZ^0hYmqijLYl-fyMJ5-OYiG5ziZujuPnbc*yW67;GJ&JP!0-at0m^1n|K<<ecQ!
z$p%jYX=v%Ovdmz-k87jWd?53g6Sfr7A?9iXi@aNgEi3JM3wtJPZ7Z>S8~mZa*l**#
zuTDaHDk{!(pzT1<`+i!>Gdch87l@RMY`O1)!TR<440e8HWzWds1#7lEd&b-?>;Fv#
zE<PbH-@G#3G_pAuc=rBWGUehp+I3O9ZQ~hs(}P{1yuYFThL0W9@!05DQW;$+Zm+3w
z^-br7E4D6|t)ssUDpRKhJ)b{NRxUZpTr}p)eV>~exSq*j$AyQPOICbO?t9_du>2oW
zgB5F5%0bJHmuJ@hARPI@q%c^0gq(QyD%rf{{@i_)+ryDtese4JU0g4+`TncI%5P7s
z+wrTvdwAEcKK1Z(w|w)c=YDh1)R7n8YIyd=?F~#T?t0|V>t6cDsn<RK-+LkLw6UuX
z$ZvY;jD}x5bw>QtU5`xOxc$RY*?Dn<OU54hi}QDkT;A02_RG<dw_lb`+vi3*UOJ?8
z>$%s~Y`x;zVCTr?(|`ZM(TCk}&(XC%+<8>E^QA)$-oAB5II`}?wVT)dYxu$oM<4a<
z=G$wZ-tm)3kMH<N?yfaEYDa$ir9Ach!yvxfxB2$y+239s?E2NBp|M|GF*I_^PY)Ye
z)tY<urGJ%?+h3FJ-+mz2xa;NMx{IHgdc#XU*lT3Rg_Az>#JR;y|9QrgU;X-w`d{sO
z`QV#A{SnpIzVb=gvEPBUV_Po|FL?X;n%my~UGUhaKNkJ{tw*=Mbj7tbw>^DrFgEh(
z+UFlR+^l`&=-O?Mem8vlxz>a4?${-p*Zm|~Kl&}%`nw~eTfcLgJoTCXoV4SKw{ttT
zZbLi!>(BD+&_8_<_T7AY_<Hv_4Xd7g_~gSzA3S;Bm+${x-&yCz=fBZ2dCQjhlb@?J
zH@KG;9w`@J9@v*Isd=vZ+=dNbJR_>yI=O59oi#PT+;L>xLr;7nTEFQG8TiuVXz27a
z#O(ZJ?H1U4%l4C_4c}NOBXyH&p8x!jt<OJo@WBgr{Z06tQx2*9-U~<Ociwws`ybAk
z9PE|<R_*g6*M=`V_@&zWPB}U}_A3~gwoVPU-FRfpU(Wb(_~NVo7Cz8>2A-)lv{LWq
zw)E6&shlO-y5BEjH*W~LFFvuR?}7KpbN~6isPu-d`Q@^@5B~Dr^IF~Wtu=DnB|-Sp
zGoqn}Geq@nmtf?FABwJi@*?SZ;=HK1X|ilR=g5QmcAX#g?YyA2e94F8u3sJ5e*OM+
z!TP$onl*K%bwmHP(KA6Sw(Ad$ZhPj){ODbiYR)eFGrH=RqwkfkMW@0pQeNasAIBKD
z;ozVbLvpX1-&2;*mZQCczwBCxVWu-4+He8xu$Rg8m1g;}le(_44MEq^r!YPtvpp(a
zh<)WiE|lr!{_bh!N?C~U!G=Aie|;tFzimUf@THP0Jpa7z`$w$wmrs|{@i)}k!Z*XN
zN}~-%_LeITs&DV_nv(A-SH#Lgd~y(-Qj9Ehd*&KU`jy&<o4E62zBK~I5zbpe_a}mx
zn3?i%+;hC07g@O;4@+e9#=5Q*56DeH!G^XSQ^66~87RrH)W~eJUb+UvbPZSxM~BIk
zS3ek<myDENTG)M@8R#BxU^?TbP&#j@z4EsEpkI^p2le5V3u|j#<#g#Pua~+a4!VRG
z*ei)$ilMbmYWXdes0$B6Lx(5oIv6H;<_X1!!$I2<;)W>1$Qa7$xbR(4^tTWe<;mf|
z;S3Yx&b3Kg?7=UU!N5qjgqA=1j0QpP4uVw(IULQIOWy?%pY$yXqX;}qt^@O-?csoo
zK7w-&OW<4L1XjUdB#0Y{c&6#Q*D)G`F5(=g`ldc|BHrrwfUO6)EOg-n&NV%B;fSo{
zc(z_k+UkX%0&vg^Wr81K=Oh;;Co>KJ8%<-n(J<!b6yHjpd9l#IoJP>QkcelRwtocC
zAZ&&kIY;?bV19)ry2Xk<^N==w58*@x1rGH@QDB8A9>jW1<M_0BD4|7|H4tLn>43g+
z5GdzD`%uLMCLCm5y-gABnPCbu)XyLzOs$i8&H|CwZ{Qi8X*yfez|0#9-XDkX0lek_
z6LZBq48IpQTKgL(=fuVaQ2i`S(npC@&X8oW4MW!>6&&TZR)V3#3ZhAub79HW;4~N3
zT&T94PlHVdjsjlT5C%PBpIZF%_7}JP``f@a==V#XdwTnucb>AV{qfhPZhB-+-G-N+
z9((aOXRNyOt-rnYx_^JY?xB|+fAhH~KfG$!uaBH`9nL(RcIWmte|P;Eb1r@G;~(1b
z=Ift*dDpMsJpajy@cq(HPI~*rZ~faRcm4aS_9yZE(g#0&@IB}M*U#SG@yHd=y?xOE
z+x})w&CZwp>%5D%J+kV%PhLEA(|?~dZRh#lTD)r8Cs$p%^QEb;yo~hQzp<QWgr?ms
z^5}oxJNf6g{$#n6%i^m_XVwk6zs7=mX)Is-D;Zdg2kbVgFD6IE;pu-X?x%?xc)e2Z
z28;3fCDY`lh8kI4sfh+QwBh@b=S8PEJL%N>dTRPkxiC7YvmxqpUD2toKU##gWlA-X
zk@KS5`qQHCjGPl~TM<RY`nKrshfa?2JvGslg{e4CSsR5H92EWRf`;0;YwM$B@sy}9
zmyh!6Ya;4<-o0pQ<-?+IHT%%JfN$4=3iNFaBg7uS%JoZ4O)%rh+K_#ey-mTv?Z?Hm
z0M~9Xu7Wm3lP3DiA<vLJha>PrJ3h~sT%9x)#A57W3;+gbPUr@1Ljb&jGL2*jlcNE=
zj)iR>ADSnlE<M_V6h~6-6@wZ6Z1*tV*?|Rl2s{S2Q1V!H2C>DMm6MI&S%XJA9EO-R
zqGM?wE0zbEaH!9Q76~zLE=r3HZ-)aRt3%P^E4Y`5oI@OpWdQontW6e=VfsT06w4Fk
zhrt**LN{y?H4H-l2HYZ^;|6?C+y**@9KIwiE+2N=I{EWqq6`<P2a}%fW2L4pGz&3e
zB;XRs<_0gN5+}6lE$f&k=CK7no5g~-riK_TAp=On*)S9$H8n<3r)cl2hHaxEFwo;%
z0g9TJ(1w(Wp#U_<ia7&;&qfFcpGE-S0N2BHIKJCV1hO$<8LE&^fAEaSTawukmS7M$
zG;f20-ISQax<wiwv=R+KmaSzB@e1w(tWsGFI8twc#KTPkkHL_3%V3yKCOq)Kr$B|!
zKnFmC`c~jGZ6<*W?e@c8AjHW~buv(d4ckB7FgTiFCBRW5X6V9V1Z<EURe=kWWA<tw
zkPMZ8L!zNt4s{~~jB|%RD%!XU58G6#fiRGe3z`n?5WzKQTX+<wXwTlc8jD2EGrS!^
zI--5Z1lq(}V_~ykC@6%kgaqqC(18rhaL*N>tcWBICCvrEvOa-<h)^kANsV9~(8!6O
zsMwB0^xN32f&oP%0o77Dj4c3)z^!1a$=64Wvj9-axS+35%H#smiL;Ox^Q_1Ruueia
z1fg3S;6@Cy6<Ab&CBP~*28aq2GO|W`hM+Z6cKE~5Ih>8)1`M)8c$XC^2_SSG*1&I)
znWk4d1ab#}3=H%D8p^UBp%c=OS(=9(W>a8*!&5zcLqb3K+o3OLF_QFH6cN823L(T|
zH?|O1M{1+R<C$(}1H_%+NF9!S#~8CLVxXzT#fPgF5<uUoB{E@TK@JLl0S$=qrn?p~
zvXMrJL7l|RlP?o946*v_$r2(u?%*Uugm534WZ_pwKptb#RN|m(pbyTc4S}7}^Eip+
z4YBPO?5V(1qzr8mluVl;QG7BnO-xm=aRqF{LJ8WjF_u}aY*0AO+}TgHyKpg1qd`YR
zAlKj!%#9A}Ron?qa5D^*@VhB=`?za02)c05CiNyX^#Rz{$8sHt6Cn&{vgFGw+g6y)
zw`cPq`2fhJ)wZ_53qwdQGz11=7?QOZHt;;FOVAAJXckrl8W6gx5@8tYREcQ(k<AzJ
z+HLYfO~S%BfE0$7geEdrIwEg~`XmFE6}l(5ti(0?uB?xMDKkd~cr0p6P(-hVM#$ix
z1XeY3kpWMvaUv$>=o#375-LIpON#x{Ug$Lr!l3hTYy#k8n@5?3`Oc*oGK+6cYBSOi
z?AI1{OHe*S9BTvrFdrqimuX3~;wJfW(2XW2(&5}1jvz>vt9#|l!3Kld1`JEN(=pX!
zr=^QWfDXft<8Y$JfC$+ayLF{x5C?1o2TVa;4g)afvQlJvj|@nlB{C;td}xiQ(a1PJ
z#FpX2910VmP2y)0vKMw<4f0?!E$Ri%@;N-t;gmuNq8izkBOt&Pa42>O1}v<+_cf^2
zWJV&3VJypb3j4Lee!U<Jc;;!r_rXHKnHVARwmxjgw@6vr<Wi6;!}hk4gUm{7Tf?@V
zj-<s!hoNs(4s{(lu_%@6tb9;<ob>lYzA-kJ*wr;+OOZ1JR*F%F)Hq=g@jk8AI4+BP
zd4J4X#-cvUfeY4@PHQU$(zF^?i_<nuIP+zqGIGopYlF#B6XSkogM6+Zi|(Sa*B|UA
zS!w>@UKZBCdISYojXO)}=@z*vf~0RZ11F^*u%DHp4J1T|b0~p5Z0JYOB1EEd$&ls9
zFpRJ*z*5p^IOJPYhVj25>F@)BtsCHQ2K$wI8oz*w9*|^7p$J9<dvzb)zx@dYfk?uB
z7ey7uQgHMQ9SJL;RFn)V1d2j=;cEwBvj+5orKQL52}DH3IEihI7!6w+=UcU6(ibg&
z&VY!-2!daTvXE4qu|!$OM1v<dbbU}LI22sNpptkJaX}77AtNp!tY?cba02QUCq;yO
zTmuqu2!si%&=39`G6)cjegWu}WDq*!5JYQfgrPp2M6}!SpHkf|iBMq^IfF+oR2%21
zK6EHy5+Kizw8c;s!b6kBumL0hc&-DXK0*-!CX7jI4V;t+XoF;(zTm{@cr+4(q3a6*
z%?_@Uat*TZ2@WS{LY}^L3}Uje-~$B4E}R<aK>!s76aWJA=-`k7rKk;n!<)uK>+*_8
zWGKZm!yp9GHVP*7kwb8bItBbp198xjQ!{dS2t2~aoyXCxA6Uh(*T{=T6ff<EARzIN
zaTS&`2F0*WLIae}&I8cHi4FjUM1ZIQ6Jh$$;snTyka2X;8bS=<(M$_w%oZ4`2TAHV
z8@l4K8VWdx0*eumA<b+BVG!aB7f5hnF@X3fxSXOLD$0=Dirbh6bwnD293fH4uLd&>
zB&eY=NaBVY10Ukb*@X<Cm}NNpt#dyR1}Iz|+9(74#WS@4a4h}cXBj#TbOnPzn}i4g
ztmS~;0u2xcN9E5E4|oOdM@E`%_K2{@pa)yreL!gnbHF1Xr#H<N5CNMH0_}LDR(Tt&
zg%EN$DC4zK6P!#^fT6iCb!Z(RYIK}N?R#1zazq0l4%$Rr=RG85gHEP`l6vE%!EQs{
z!blpCiMb86H;h<Z5*SKCen00E1xS1%La82#z2;*|8BWA$0?2gU5^*j?z{`U0Ir3>=
z3oQZ)c3e&F%D7Zid0e8a1EE!osV<Mtfe?^%33_Cd3dj>hhbt@QE+H49sA3y(FvAiM
zO^X<S*B$#wCURgv<5!_qLxoxnH;@ZZha`j4Hn995IdE8%L`b#12yNC+Cct2{p^gT<
z0)mWU5GSdn`e~V2oC!c)0MbB|IG%Sn@povShz${g<%)%CtRYh^0$AjsKN^nSNtIEa
z9#Zg~pa32Dpt1uy#tofNLR18^^Kzh9FceLoD6mA?sfuPYX;#f*Baeg&_%fQh)|-?y
zE;7I(8kDh0rv(L3sCbU{9zc*!rDD7R3@F~J3u1IT57z67h>;T3NC+S~<%1B?34wu=
z${;ST)i@m5^1KT)md|jca3Hdh^Xw2syvJLKR5UHA-U(W<N(jb=d>osvK@0!{pu>9z
zg^{DKj9dIExWSYRd3`SQd4nX4s5KZvzI6Qn-EcmeC{<g1(mIBEak1G%@T>t3We}B_
z##suSk)-zRwicl(FcB01NdN|cByZuuoa!<JTm=3)yBgZ^7ww9*ESrYJKlDt)q(qw5
zT0gv~#0X{=i&n*u&(ubx(Fh%PNKz;n&d%d;q9KrE0EdfdjFoX^Kp`m@_&T^MF(SB=
z!35+vI>ZS9u8L0Qz(bh|k?^r>Cu<UGj2MJ$wVZ~C6igOiF@jW_5unHOdXn)bk2ul^
z4p~&vBfn;Tub-xb4eG&Zqpd9h1{d7eVbIo~I$?Fh0a=A8BN(%+W|2%IvW6&=NdPT?
z=cW{pq+s<<%R+Zpzyjs4*}@4mkRW7S<PhK;^LZ8+mRb$a&KI{4LF=;?9l`)(;gmcM
zA!Kt#tV0m<4E2F1+B>8Y%0-)#c5q;j-y{|ISSA`Hrqk0f1#QXrY6MS~kl@6qPbbQB
ztYUbE<nF0iOG?p}KE_oQj_igV*#qukGjLhJq6#!(O@@MS73C35Cpqgi^2N#+4lzfb
zjxL@%psv#e3sK&tMnkj?3J4KUMS0s4?>+15nid<9B2>mUXw=rK*%(OygT?Muo+ZFX
zanp&@NPu`a!CGw`zmc<BbE{)%6D*1oHaObx#IGq27?ZgPI2Wy^C1qG524x#4YxSq{
z6z9|(5Tky`29e%Oh()2(e`7L*ARkBo6|oLKDz`$r^&$ogmij))q-1{lM)?2<9*Bg-
z;l>2uaG_)I4w9>K3vCm;V9gjH%DB|jVAg?!g3~zWNeE{Nov#L|1>PYMr~;A#%W_9b
z%yMUdG*lfh-5x{L0elTJa^aT3tBwdZ3lK+9C@LizBm#7_^Dj<CnstJ?fnb%$h+U#l
zbvQaz#-lprTgEZ&(IX7dsnDqcRdI|}6}QO2JSg0rU^AR$Cgh+#z+LAFqbxm}@_T@H
zYEV)c9a1pKQ06$0Cs_4@K#@*e<70ueF>2^!1<{CFUa?%CrN980(}Id5Z$N^v%kmt~
zj<0$IT#HWFfkEl}R1#3O=(0H1*KI{MEKt3HwT%_H#)Y`V!GM*MBQXsFc+$KC2}m3i
zn@CTo-V_jDf~BAn>`L&aM2pbTZd4~dNn@>Pa8S+|xrs`)xmH;Xe&R}I#8GEc90Z&F
zjcKwX?XXKyc4$I@8GwGq^)H?db_V83Ea>?{J<vg{iA=vhcQi#1V0hAvK{Vl{oEY9k
zhuuI~`~(*5)XW{0LWF$X-FV9fo4PbLEe>#0Wg6GCNgKJeAstU68*%eThV?L&^maic
z6c4(k$y|#J=u&L=O+iv?d&Kgs6%d1U7Ho}=0iaWw3Tt-_v}(3!#DE@S5UVdi#$bze
zc!x@8MAle`;#-?ID@YDNXt{|M!f!G|peXgi!4zPn+)_aIhHV`Bgq8d-wmf<8iT6LI
zXP{#6yC2EV*PEQk!OjwxumcJ?DAy!TPX4^%ucA!Ib4x}FTR(4VA;;nuc$my$w*=!(
zh$lpD0}5-($(kXNFp*l&9)mqHj2&&pbdfPIQce~-POI2df-Nj?Q9vuf@c8{tu_r8t
zk*VjR4VBtxm*8GMKyrju2|#MWFo3+s)mW5aiRv&YttosauGrfLc_!zZ7l`~z+lu<<
zyB-bKm%cRV#^pz~w6xD@d2yt;eoOJT+)aIV*Pj#4X&Ebx4s01Yd|*Lw&VCJrIrSSy
zM^}$6TsJVZ_w@RX!}bYZEH4dqnDb;q>poIBbaptlb!O9;nGvkb*XD)~J~G_Z(P>tW
ztjiCT56M*qzZU*Y+X?2a&Ku3Y-FjVaYiUw$tn)<kXUkj6BcGZSUUKFAxqXjcF573G
zW411u8$Q2u*Y`&XyDas+;Wd$8op;Y+Pn>tpLr*Nf?av-te%m8sKfQR{n?GH3z%Fz5
z(Ys1_Kk{PVZ|+>v_nRliww!n`u1!yk?7DM7dDlZ@%kKRCo6CMw8M*D_v!A`~<8%Kd
zxOC>Lt(V%d&9i6Sb>BY4rTO+*EAq37yN*0=){e=?^^KLjyU$qZmPJ1(-!tds@=s3v
z*L(Nd=U?vKZ_(I_KbyUM#h)$OKIy<&D`y|rxALFgn7!hk-}w0BA3t!`jh7u*T2gqk
zV<dUKoBB?B9`DjS?}d&X=k0vxv6;6Wa`y6DA04}D`R%XXdTG<DzMBqO)mOOh`+dK;
zceL-NO=DZ$f9G9WPI_$rjlVhI#?hDT*r#r8TmGp#9~!xB(d-v*`_$Z(t(VPwv-MMU
z?Dw<VSN#5<;)?wA*<)eb+?S4g|Eyg{p4j*1$XE9nt$cUUb2tBB*6(iqN%6#cZ`$Xr
zd#_&f*oxz4AG6@3MLRD$aMtUWLEn4cIQG-`{CLsE%MP45_Ms2=ZMfj32eG53XNMYJ
z$N87#N3TD%G&Nte7d&Q57j)bu>wfm?S!?h4=-=M{AM@tle$>ro&Zg0}Irlzx{@Fb@
z=Fk4oQzM<l$3{BmtO#d5aba=Rog3`@;?TnRv$igL&c0fDb>>ifT(LJkZsyoPTi1<S
z+KxN7^{V38vU=92n^hVqPoK3t|Mk)>#jiJ?v9-PLm!EH&e%HFa7yk3D`%D`fG<Jn6
z%;cG-?GK1tH0^}q3Ufkp(OghjFBcS^KkP2(y<h9ErrrF&runzFKe2q$`l2}`e`EW+
zjW^|&9Z@jlpD#ad#w|;W`_F4D&YAOK>8P_u7q|V$EPTMOEWJJxdiN|Scg%cjbz9e(
z0drhIK3Xg-?4C7Rp4C@&Z8JA?>|=X7Ce50>HR}8I=i8_MCb*&RAu}-jn43*$v}~Hk
z!mrzB`#wMOt>aFxcO@rG-?)08uBEr`ecWKNxeYxo<hh~`PQ!+LF*MfV;fsw<{bGJ*
z<%A0MgG-0Xno=$<V`KO5+@pP6SSoxuSreb&S}Im%o!4Qn?)sj&IzH^6pRW(1{9+6#
z=(}M!WR4m<Fu7%P{u$>qMHihNR@#~d=D%-xsat+1-R6hMHwxDeE?>}IvUs0{n3C(=
ztM)3B9NpJYYHW(_G2zS=?Ss%QPu<pT<|wmY&5(`q8*H@xi(zv-Sj4bw4lPwo;9MB?
zREk(5BtxYjsjomc=$A;V44h}oK;@v^<MsK2?!(;T+Uvv(;;Fo?;E2)#7xl~-Jmd6%
z&24#$GgP&a{LtW%_Z4oLcVKe;RT#<)U%1n}S5q;0p9~&RIws#?8=ID{n2xhf(+B6T
z$G45K2V|1NyYPz)4qr=p1W%gyL=odY#_kT_w&GfY$-`k%>A*O>X0w?8hp)GRv!kf;
z{!jPxOm4yeJ;Q*bBG#P@IPyfF2_m9Ktb20<0}DE^tjqegcVdL#f(AuoR|s{70R|s*
z$Do35%Z;*%yZbz!hzKa`dK038uMu1fATlVvu%ZhAfk1%&_gCF_68!Ave`c!c)TvXa
zPMvz~?&`k3b6)qW-56_bJ7EeWEwq|k(|bKU;0Gr7*kWQfkMOIJ*<}Cbd(Ez%b9OaN
z)-*nGw8|ZRc5rqMc+;~EXU?th9JK=9R-;*&V%KCYQ~do6eu@;nj?O$S{l8idSX_18
zSLi1_Z^g~Wc%tW9Hj8Vc!!?vkdYGLi9%-&JrsX%O^vn})mM#!JASb<BF5Y9hniWyB
zwh<>B#hr~?2Ty}=1|3f3<*2hrJUNLQqdcaUe4{$^^t0=UCE;wVBZKP>Vh$HP_8{o6
z3=wZTZ~j&q{p{2-=^n;u4?>6XTOc^|wpIl~!^A13x3%nx{vpN-GFke@S6b$w9hRV{
z%Q$!w3^a#UnS`Emdp~uoqd5e{O}C?(V1Uj%Efp7eqyIb)X?s90dsE8c*ibXy*@%Xi
z{Uh~{jRaS(T;m<WhbKerP;Sh;&feNgQ}1#MjvYJe)va7L&bkrbX<wJ-?l6DZn5*ba
z)2~}<xI8;<v@&w{`;J<?ea%%*?%MI-vk32h>dbF0zV*~^J$WAAeR_81ANT#t8Bevg
zpZ3`&AKGxidgA~1&GY`_k|$4n?%4+({qObbcOJ3mzB8`<?#?52?t18J7aaBMgGU_m
z*)?DL?hlW8=Gk3eTYuD!2X9!k^MNbgecuuPz5bz_)*rOv!9!lQbIlE>{^8m`T(JII
z>koSB^doxjI{d10&e-wv`X_EWd*9p7Kk5ZPJmRWz&b#&<>rdVJ#J<nH?}$b0U@JO9
z^hwUNJ#psO_CAF@$*dh#3B7jB_DxH!S!?gDOxS<1x10{Qy6hU}(2GB3hlb01WvVms
zFKfq_yO~Yyrs;YAFROhRJhd}6*kIm0y5e4W$nWTDGw#TvTO8aTcAG};*m(OP4_dlr
zyR$X3Zggm-eNJD;UUTZ{mYsU;vc93pFGu#z=G<F0&y9X)n_b=aQ}?RARrZOK>wf4h
zYsLq&<Cn$#V*KvZJ3d0^9eaIjOZotxtF+iDu`wM0mqg#3;v_GCdP@nRi^OoxgrbWS
z6#qOfTZjt5#S8NU+$==D@Z4^EOlM5K^!t*K>Y6@7G+IZd?B&ul*hnS#SmH-U*i%B#
zSn<p~>gP?be%>J`p||ASq!j8+OuLSEpMZz@izLyR_ra+IvhfT)L~1N9fx|mI2J1$f
z=BtER3hp>$Df^wAP0Msncc|tl>lBhtBAk)7q^E5?;s7RaeaOy}lw|T$^yF>agR<k~
zDL|ey+GvnD^GUCY(7dC^@Td`N)C*A?dE%ASHKRD)<7Woqk!c_Qx<g+(7e+y_)fLBm
zJ$B20lP9}|0-X-l4{fwk56p93snHlA*4C#1#>q%669^K_+UPip&6i<xRXAbE!PpI*
zwv3VP`3vZ5Eh2DNTGGsAp$&1sF6@{3s0h=b2gyJk?y`pE+QO%?2zuj8P%N#Jj2YqM
z)K}*6<6&?P0ae?CF8VypY6SG!c)V0Bo)09MnxBbAIlI@POC>LsN0};CTIPp0LaxXN
z&T-vB4oU!c@C;W%d%0c;i{EkDXNOW;WSJBy;5ix(>82Rt63fNA^OlS)0o&U}1ysr5
zG&rj?gN2}`RvD_jrC#EMDIlp|0j!Z_+OmK`g|fkBW>p{M<+c%zE)XGz#0132GD#(j
zOBic&Op(1q%w*xf;36||Z}7`YQwA3ySni=AJtdWH$}NpZ?~8u)VkxMTC(6^5u$e-Z
zy+=o9<J#y5tP$JMQ#JbAlcLP&RpP`^vz$)c*X|1eES`CyyjaOfG8L>9BW>&9(r^-P
zL7|8<l^P-V?}hy3nRR5)Ol5f&%=437@Gz=k4i|L@9CPM@iK|EmmgV!4N@n0Dw#C{9
zL^CK`gF%vzC#c8LuVC_=Le?k8_`;eu>SBFPQifOnTwQUqUhhVWZkz@49zDo~@cy|(
ztTkgKFtU*r>+&LmapTrgVMlVTHwdHD;7{nxtS!=W2r)B;!~~{5_l}@%2INQEN03oK
z6(tj$Y5G4`Lg<i@9;o8TMA=@2HgSEqy_|q-K6S{SadSi?aHu7zu!6-%Doyx(`E;~w
zevvy2J_3)}YP5{x1Slj@H%-hy2zaizD@-gMCz|wS>Q%yw6G`6Y;SGE$n|PLb@$0(Y
z`aC;?0duuLJPt^S4ir#FAZ@1NVy!?1GH(Lsdl4h3RhV0PWko8dBT$jwp>o2QLfOS5
z;7|cf0wF#xq4%mQB%z`_Sdt;5LX<yq!aPk4%oY9gdvl7wh02vydky+>$iR2dNC_Eo
zEn7JjYgNgDh-~94m+6jkrpaDh9H_12vwZ(7pP07RSQ8xsHuQMjB`!q@byrtZTLyOD
zBTLdGkk{o)m`3us5q4b?)t;N?gFpFd_9Mv%Q%|1EY0B$wTUvKZPRY`mI+ItO98d3G
zAgNoi^Dr7$QEt-lmN2#)w}gqB#MvbFS-6c+OFPVlq9f*B#k+pLIL}8o1f=B@BLr;~
zIfj>|9_xBXKf;=cJAlQB^vNuVYEGK@Dsgz~<2EfbA#WDK7qq_cHihp~a!Y5PUUHmK
z=?urKb$R6wOHZ+(4Ov3Ex5`k;Do-8L=)>u_E(tc_mBEE%i63S5TT)qRdCS^??LGs<
zvKH^fF*Rh!7)6ltetLZ6C<jRLrt8aE-dL8*`!zI39$rV2QkLVuUIQ}DB@j}|9M|-`
z`RKXIR_0A=fYFjPnS$3b<N0hh3tr>c)=>8vX38paGM%;O?eM{asbY#kVFqy->e^{M
z|8X>2J`4{g4-LZp-f5RrE?u1H2A_k#5vYSTAEWoihVwS}q4+)4v4eHKc`U#Y_M*%J
zbjAc8jMUL5#hwo(7j`H>jb1_}ZkLj7w2(pLz}p@-AL+~yY8oJBgvh@Xlia|Z+Q^*)
z1=<xKB0`Sc;IWsu>87$u%&)w18ofOTOmQWYNQhA)Vham8LlC&={|{b+lo7-#m$DLN
z6j~lm7C{hDrkh`Od+Rfi?5UyyQ!0?BzG95D{auXG_oE7YLOv2go4pU>MWj-}d=Xen
z^9Ci85XS-i2#o%U+@XMUuS^+POQ2YFY-buSiex&+0%$^XsYkl<*kTtEPXtjJiGC7_
zfH;6iPZJQ-vW8_$tVy+5%+gFQlFVFG>7lF$ne#D32#;G((;sbh)dYwGQ4(Ve!k8-R
zB?EmT(c7v&P$MW#HlTh~*-esFAiMe?EQ^x{NXX#!A}v5F%p=cj6*jUvnM#KccE^=W
zSD~VE!Ut1***}^%h`?f2D{VjxrIIH5jIbJW%*c*r%}{kQHO3HUSHc5F>S;Q?%pZXk
za-^X_8^e$u6I_{k7$Lb79cS-PZUFg1Sb)1x>{_)&7sRAiM6rY{HD`@TMR-R8qL;*K
zWFS*K^Yo#c6|GbyF$+lW=1l*=nihcqB27tu4$bEiLQz{}dt~4QsT2fMDHl@$!VAz(
zm_`WN5W(YO%&?^|Q6DKu%o|N!)>Gsl%c!)39HL{AK+DEbWF$`bC9cfiOA+)U(A_Xu
zqN9Y;CUJQ2osk&IFcD_UPy`+0s4#C)HvhC=qBBkZ_rsAzU7=bst5Z90E&T<A7?5jE
za0?L^Yq1d3JSN_9jFi?YOI_ds@t!jA1aK|Lmt6!Z-s6~GY0dyv2&FPz78wG)*{A?X
zmukbKa4J^F)PoKNJ`O1L>6$3r&8Aeg@Pe#(#bH4u9~E(^<duwOb%oT_s}N)o{_|Z*
zi58A=w3IC)=)6NA+YyiBu8Imp0nW!tTFK00<KrPiOZo%cR3AUq*>{_kye|GnvP}Nx
z;B9DDS^-WWCz3%i1k(`F2oB%l;@dYMs(eUsT5|-oq6{Qt!U<Jp7?h3w2t~a_9=6gz
zjtFuVpb3_sgA;{5P7l#ir<`L@)F$koh#}Nb+ueB+?szVgL^>c__VKMZL0Ol`Uok!X
ziqk2xdg4efL<b>B^o6OAa?&NAi={~e;ZcyP5_MA8h2raI${UlrWbyej;s?U+e3Izo
z>UaV^F{%bvCA%P8>t11bh3HRxV|!mnG!_+Ofvc=SQ<g1pc7cBGBR;*LN6kVx=ax)v
zL<kq(l85}=5@gFY?=9IvOe0cQBLqvAb?p$kREHKs+TJ3hiTZdMkz&p)OuF4F5-;KT
zc2nhcr@_)G*^0myI&@2oaw({!rdk!E;l08HNlpmhY_trs7;<@)Yk#^2Bym+N2{Da%
zk$q+fecG$~sBMaQD8}QtZrP#$KDI_gV~Kg}myf=yND>`gd(j~Qjbh}FQinaEsK<C@
zDN>5bQ=BDKpgW98w5UBYJ&_2^>4b%N5qwOdNU5K=A`2|!ks?9L1e~D!wv69H+)~fO
zo^lsju~yjusfQ(!P_&@15@a;bzYK~J@dksVAh8t67L1<6l7I%Jq#lAVHlbhuL|@1^
z=OblRBU)i_dbcg0N1jw?NGwn<1e4Rn{bbBli+)UXLYai&IUbgxi&1_m{C|K#<I%3B
zyF>9RvAjHvS$*_N6s26$3`1yV8<nJ_vO<KRDpsuM6n5#LGF6PjzF4?SrI|M^SQQ~D
zDAem!5z71;<>U|eV5KZ1kgUaUO0wcaJ86q`b2ZwV>6Zf8@hgYy_{nlEHE(rZVlB!i
zBG8>gF*-%clp=(>#Uno837k9*4S51}7WOrw@tfLfp$MG3+}ijaCpFq-#fbUB1%e1=
zO}WWb#1jQR*3+rd5vY?Tsz1`W#ufv5&BnVi4x&`o{VM{vyelv>M|=ub#R;N3X<UHH
zrr(4})~9$P*_VO}9{JD%yh%a1?~A)r3QWZp5c}(b{DQ`H3`j7yhh25&_<x4pvJ?f*
z7p+%vdWCTd-jyWVO6!zAX$h1`B!H)0LAf4BwD35f;*~cLrJzdUd^aJ6r4D1LP|!<1
zwMMrbU+Tsj8pVhs+F_)d1AWw{B94njyjz{AZk*zKgcn0%f$DS)=U<V8aK!Uq%_j6+
z1s6Lt_k*G&#&;G@MAw?QkY7t}T3Euqz*!z#oOxW_Jk+=xp{DR6CkR_sG+VG~9>Q^_
zV;DPSwsIQw5ylYQ-d!dYLP%H}=;0ok>=hBF00{^Vh9viPnn$UD30<yo&oz#XsHH3R
zAbf+~_iMBcIPMeCiQQ1G7yEds$P_#f`)JD1AH+yg-+-Q)KiOwJy~Jq?=%hr^oLEbG
zlLJu%iRnH*JC-qB^Gji3hYv5gz(&w7mo2~kbJ!ZZB<l2Y8EZYar+C2_`M}sTGtM9<
zcM$CYa>%V2kg|ew(_?VixH6yne%FLDro&ihLfJiuk29fvZQ9So8&a>`N0U^|DPCbA
z!_mZ*<AQNtn~LbFsNyHKRMNIH{t$;T(OVZxW~;Mge0;!z#eEa|$=c}1{+8TovBK;W
z^Tv4AsMyuqv{Okai^#=2yyt4%>x%8SPPhJ&1RG}uV>#-|BbJ0Kc+dAI;*TtIS2B#J
zefDZ(G!2^$s2}pNnwpxADNcLUgtfPaJER<zLv<gLue=+zyr-S1agC?H7oXoe^6qmx
zo!i^-x7R8gUTa5w=FGM2EmIeVEx%1Gga0*NIb!V*%YOOb%0sto?&*K&>y9|^fY-g@
z@LNt_IlAThxAfQd-LL<k6|XsY+f?n`)`J&bwq)-YEK6U~v-aV0-*tCqYN|iHu&2NB
zj)4{1&$XK$UY4%9=#xE_*8lE#`zdEEKVg37S%1BG??oTKqPJ)G>^F?RV`A69uQ#8Z
zWVMea!~Q(?Mt5fI#MLy@N|z4*-HPUliSyiz-?^v$)JL8?=HV-!{I1Rr9lCAjqATxy
z#UJHvY&^YsY}<o(xH~t0XxW{=d(A7iJ-O(-e|q}s%l`8(|908W-gf@7+aG-N&Moi#
zz}tUx{$JvbAnm#pPc1uO&5kqQ)!cFB%DboE`>NxcJ3p{u+xf|n+s+?Y@zg6`@RA>%
zKk$ybPJ7kg;ErwXTzTHcGmiP(qi=ZqM<0E|i(m4?clX?T+luN-YIjF>=Kb$JX5%rO
z$~b++nuAV1yzl3v-T0knS3mXECl@_@_mk1SBPZ?bxpMomi#NUX%rD*eo&Q)pcKgy_
zjy?XBMav$$t@oAN9_cynsyn`X<j>x==J20=__SrWzw1|bZ+YK-Z~xId`cC=9`L*+|
zditMleyW-^cAVK<yW@lJx|_Nj-`@F`<J(`Itk`~La`QLG`rh%wXL|nXu49(|&0T-D
zbXEJ2_pfiCo_+4OZ&>>ICysp8OMduF{>*LXRbP_aU43Eg7u5?kp5D9oU-*XN-yOL6
zphJ&r?z(hEb^F}?wR1OU9OqtVi*DR<iXD0T_V*l_Z-38~8@@4BncI01XHU*rwq>sm
z{F^`54&O4i{O~QE&x{Q{cvIz5kG#MBmiOex-}!;@w_oz%v(CQg<sVoZUa{Z&lE3e1
z@ALQRlD_vW@4xZ<{gw^(Cu4)zS)<!tvESYgo<7jKd1ta}?!kQ3lW*AXjNaEK+dulh
z{pas`qu+a{Kg@?S_%7M1YVRWx)t67cmcD+ZNv|EhWZZ9lcXK>{a^%W<<HqgzH#VL-
zcq9*64{cptAGS@~&b1>uoB%tZ@`e7P8=IB<k>=RklGZ7g{AGIXB~^E1r~0lV{n!_;
z+2`+j(!Tm($Gv6stB$|(!|xhBDI0KeuSm}buSkBd<nL|Oww*nzZmg!28=F0Du>Y)&
z-nG=f<Qp}&_k(K>>)m|+U^4HMSDg5U>bbpda6kCyYy54z$~x4V@V+(WefxxDc)GvA
zJ+2W(os)mcwzVTCPo92i=I2hWY?<|yiB)D3t5yx=`J&-D$Gktr_XaC|c(Ar*c(6L1
zxQWjGO+LfWS)4XHr>DdI&6|h)qV_?Z_Q*k<Yw91bnfthRRqHux(9&%+zWukT(aJ_L
zf6>>>&u%!Nk8A2<INvz6ZohPD?LgXaNxJHA_9&}Xr_2d?;GJQnSLt@wIs6{i<W$N$
zk=d58dN}PzzeX}NH;@eH$;i5Gr*jXV6C#u}Jm^!s8a&XPK(|`mclcS<;5Z<@sD4nV
zgZo{I?)FKoqv<x*_(zgqdvi}C@GN-pvL2h9seRJiiTN>n0JeFqw`Q}~xBB@igZkcL
zpB_80@_@eHrTk#csLnjCWV+%?g?Y<2DLqtz^+9o2z}H@q()xpILV`dy!Bs-jg9tnn
zoWr*^JJdR^W9B?*S_la%b+e8m+c<eeTZ(hIL8j-N*%lF5HBI1^GY+1LjoFroniB|$
zkHQWF8_}7k-*RuYgh1#lEn-?k;Bi)M@Tf!YgFPQgHi}U#;N;7X;>Zd%=@x-BvBbEW
zK_{N28865csZlESV%3b0U^jCtk}*A|CM=|d*ow|PJ^Wt?OH~|M{6r~PtECHcQWcM`
zp1>`mWMqLxNKaPacxH&N3`b(iaY{;92ia02<0PwE+yjd{4=14_FwL0LKA*QEEvSmp
z%%Nkh6<VM(Ph*N(eYT+B>&(*$f3*-@KqjU?vVaR2WB#&f7SN0JoaRM-=nGRlY<c*}
z++J6iZt{7Uv7Uab?3eW%+SAVua`jg#d+7`2mwD|W#(L6B&zBZ^-?=j3SU?X#;&+_h
z`#nj|vP16q!@mFY<0E>W{L)Q3&e(C+vqwGs%q8Fa@uQ1>@TKQ=oOkW%&mMKp`HMcY
ze#eDB`0~?Fow4B$>yNtaeJg*l{^^SzI%4O}GcJGM`fuL$#-6L*d($l^oU`-Uhc18S
zjgQ~<%IZ~XzIDq9NA28o#vSLs@js4zW6xc`es1b-kNDvQEABb}rFZh%b<dpr+`CTL
zvGamM?mPdbm%sUq$-VD>?gM8$`pgBdx#!*cUU9;IEdJs9zIE35kDhtKId?s@Z)H&R
zo}AX1C(mG{PL|CcY0IXu>fk_<)i?HxZTUMJo}LQ*spk%tYny+$t6cm+cVK$|NPoKa
zurr3&9=4*g-2UxiZ;R6k-=`Q}Ua<$q4-DVGcK=qDyWd9+*w~SqDxI&)?cF+IWWZIH
z@+@=t3xji6{`b}w{stZP9_-&|+2C06?&Vo)l+D_KgQw*Ga8_1ZHr`k39dESu&xaSk
zT6^vY()Y-Q^eurN@aGT;!UBtF=mLyK+ARLl#X_VNp4Zl~>{iN#4V+S(Qy|xcNg-@8
zOXh;C2w9#7lf0O~44|_)dp$@>NCJ{QFN@V(JP&|6R%`nB%2(CFF+!?M(9hYGp)3#P
z0vRmz=I1Dr2+%|lPrKO3d171=P_S!LF9((cG#T$`E~a{jfk(Hq=%JbvHG>YjJTOI#
zWaF~LkVB_n#uHW@?{^-ZC@Nnv;}R#)%+gDTw4u-S$bQy)8yPu_XH#C9+5R?cNlS-x
zkwcsufqF1iqDM05jmmQxs@MY?vYWYemPpmAWqvSLi8H*?4MlT}D2H+#rexXeiPIs=
z7%9(70v9D>^8rF1Y)N%OWzLAGE1S}8gp@sk=grr(aTbFQ)=TNBGqjkItN@jyT)z@C
zp)lG^tVko`9Yh!$wzW0{m|P;c@J^>pSm;WUBZ{sn73?zn=~a#iF8MzN%^^@Q>RCUP
z-SKCyqFgVk8YQXdXNy=SAkYSgt?;sCs+dTz0v09`ly{L7pKi#uq(;bcr!b($jHrsC
zQ8oagX_l8*Xhf2O?D~uMlWa*lLn9jaxXO@YH2{^au_2vV-M%0hPzBP%xMoOIsF$QJ
zG^`ctP6}mZmFhU5Z02|o#p`xPCj+-|EN0c*iPyT+hI|uwk_P{z1d>8m=1Ow|d0iBj
zd)9pvPf!|($zUp$li<%h(ec2QO{xP6bIL0bsheQ$Up+SA<R982)AF&7a)%|wrI&ws
z(X_fo4bIHNBB*%zDdi^Qa#@3gyE2?~#NdXjI*&8|Z8)ZJj3^ZcdtH5lGDZU#5vH$T
zt=8jM#tTtelm8}Yog9vg1q9#m!V+#eX~=l2p6m2m!NB%wGTPc2*jyzvXW{Pmv6f&u
zgYB8X8Q4mo{$$io)d36`%A@!gXN>Uxn2%8;Q>bfv0mk_{lY~_4huI~yrXF3+Nm~K;
z%%}sGv|U{zm9l!qp}GU(?*p2faCBJ8p)`TFEVwMF$B4l0B2*_O;mV)`H>pZ8@>AKv
zG_{Gbfw36|dV=F2B&lrt;wL~eoV1;mgb>_vv5V-!WbOh;oKl3em6v}Mbo8^}nG!Sd
zkW?A&RZ_<x$$KYDM)3Fz`zzBaLV9Qx$l!*uG|=P6NFza@nuK~V2cC+MqCvtu-Uf%I
zX<R#d&W<QC)bmdS(jE9X6@br=fCHiIE2v^9#QS+5-sxGD7mdD@btq2g!jm6xZ-I%H
z+)gPNskrM|>2cO9NW~l3V+kEu98H*fRBcjGbt+&Soj7D^iJPWJTrC^F>AN&D2lSO(
z;j1CBesrFB%K}GGRjp~yf)iYbhV^RGY@2&Kc1x4xVbp>u>5bIN3Cf*-nrj-L{_*BR
zj54gp#Zx&%zg8MBeil$+wcSX+lLC`Pdyo>|HAz2}x+8d;8ACuUB6BAVR~d-LoX}_*
zmV6U;H#nn3@1D@TQbX1Zb1@Ike3Tl{%VTFwzm1NhkT?XR*%-`GSx-1V5V#@YhkPJ1
z;k?(BSqWo4OVJO$%GHU}{Cgn7CJl*QsGCATNvl2IYNL0#$*u9c4g!#rj@aQ87)A!w
z2E5=fO|dTSmdQrLaED5-DfD-GM|97{A!RZgPBqg+Cr@ZlD{MT`qx{aY4o9$z3CP8^
z=|uH?)AqB~mIV|^n^xx_MxJcycyi1pc3bQP9LA#TxqQ5-LFQA=yy}5b7Mgq?EM$YN
zF-8i#b92Azq|IrSmH1P7mXIrct*AOFx!}CbmqM+KI_4+}Y@oAoWDSWa={W<L4@{*g
z<Hkgw)x$&!jm-s{oy4epoYM3B$fI)wLm!iWl`g`y2(yvSkZin384tIP0>sn&vAT+d
z_=OE&U7*dBnu@Q41#~=!f|_0-H3xz$E5iXPj#R)KB+q|Pte`15jd9U1Nr`I;FUBlY
zB1^$dPoWA9s}Qe?W1&Q;jZlXt7bPLv3*QZ{39jh|RY>guasEq<6eisig_YpgA*p6X
z7LRlcN>p*e5@gq18;J~1KyF^-AQhaj5_}BD<hKhv5~5ca50vZVsDpEn-k`uz6!CmS
zL<nW=h^C;7G?C0lKgegH@&o|~8DW*_h}KgD0GT`sSpdzz3aG4eyzwa<fl`U(BWPIy
ze5HjykvQ2Z<^u^uq4dwL1-r7mgRLZbP!$s#o+Y)KBT5?k^wrFsXB1_5rV}95<kF0_
zoKu{{@gl_canf^Oav6&u0wFqfTWRpV59%lah}Ufk{e?kC4cs~cAUG$4Jb)H#l!z&;
zI-aN9f#MT>UDG)(5?~<?2jD#3bWaggf2gKZG(hZvFAxn&N2SQ?dlE;^LIB*;kw0k7
zw|Z>2#GJ++QWMfu+%irort17?wZsOg8!P>+5>u;Rh8mIvLrOYo@<%h}q5wrvL8#8@
zykey=wIbl64=W-qwq(Q<!-S+}1%n7BcZekwMJQ2up)Ej}qb-8cq(vIdrbuZjON6?v
zbXdgZL@dipC3LP75y=Z4+dyD!As!Lejg~c2)XQ`7fP&sFF_L`rm9_^N>qgK@z`v(<
zRKqjLf?C_T(k8OyYqvlupgrHkVv%04=m`--TNJ3JWmpC+!Vnf{PFVEzs7uTfJa$Ty
z?9rnDM|?7(k>VHf6m{xI-RV-^o;paqB3_K-FcY^IhB&vRNFg~EhIDay-1ETyd90Af
zb~S4Iywp9iyKX|k&hS1o<)ye^b;&XGe=Z_k6Ka}Gyan^V<Zg>pK!7fw!lkZ(_0KC(
zlvM25!~$qY#$LCOEb63_FHmZP*b%S*1pWi!y`wj!6f9fIUMh07EJRB#TycxMAR`lh
zTp`pC7oJ*?y%T4f1;(PBSS~GzSkpXK0I!}1=?UGE6m#+jxQ`u?=<WUf!V2sZ7KrT0
zqafK@fJs6`qPGXSK=e&i7RdKFhbx2-M%_f%4FS~ej{X@Iin#ZC(96zRG>_<|a(l2m
zAN7jj<yfZ+M1%06MTH3_nL#ug13@0(x>|e1c7q4)st^jYb44h>ED0-2L}G|OUi{9}
z$B*ttQ`f~jMV116K`X7bz!4&Ok2(|ts2-<?!*v0xq_ahmx6GI1g%Hgm_@cVqs+3d$
z|9o*u2=WT(W-p5j1r^;~fw@v3otg*W3*;hk!QWkKlou8fK+1No<sya!Pe`0qg{WT+
zeyyma#qH(7B1!%(_%0H|+&wQT7F<|be!&|e=Ykh`N?nsuZgXxSxj;yFdy>SjA-#J(
z>@ql;i36UbES4O=BCsbHcu~vpin<RYN<eqjRj`kdZV)35UoL_#(6|*qgRUsA#OTEu
zDHi0#eT2@4Jovv9<5I_>UQV$tl=VgjUzVgD5_ngLFc$?%y7!7l@MWl-o$L|8FK9(s
zfeS!iO6_W>_Ma@76?7|6o*Ro%Z9I3w9y>>f>~f?>H(Qs@3yB_KzzMo*c?uqI3cU~l
z;avz_<awcsG3^w~b;WlJEo$2!p-b`c%+q5hlBGy=F$s<WRGg2fD+xt_TGVF2dJtX7
z_k6aJd(TV@q~onS?R2#v$)j7bm@n{wpoNS_8w8q1FdO{^FAofaun+}tdqzsra@u}@
z+ST0`#wgY$zmN^GN(_4nLJPL#1q<oY#JM7@#P2wL;QPb`UE!c~B>{QkDp|$~Ge<tJ
zI**onqEMvo;X^5iZHUqUz+T>$5$^Dm)FLgaRiL3uQRuS}wQ`EYydh%IlfZbf+#x8S
zXcMo(y(sda736|c;z}KnCxdjsm56v^W%pq2^29JLEWD@O=cP;O!AJ=$f_UcXO_vk|
z`3~oC9oY$CZEz@lGTO~2M4ZE;fKU|TiDqyLq7|E3j{-5~1E&NoT0(=cY(}RP(E}F&
z^jSwXJQv1!%nrG@qM}doD?fo)&W(*yXY)jyE_J5GH&XF)%BltkDsrNOPQ)kkO{SkU
zS1AI|{?lrFJt4*x>z*}47h@??j<gf#o<x*~7z*Vc&7cKW@y1gSht|_h{q-cQ<H^p+
ztx@tQqm!pIPe1$$^&A){76%ZS0=N%cX5vwqB*O=sJTLtPRL3V9xLQ=I<~=v<JxVk^
z1+Y(p7Uhu=A-<d_%yY|+$%D>V@gTs-k*95ryCBpCTcw4P69f*Kc@tzw=HVk=s6$TY
zr-}1*7v^QS$~zAvU;~dI-!5}C_(=_Vpxgr$@pda=7qGK33!*J2`NE5`qlxrzadk@*
zrStao7-<{%h!$xu@SnY%`%UnrIwSPSS8)AN4s$+3m8@8CydBh7%Lhv?zVPbQC&P#K
z+lqXRU01L5J$(Ny;lL$tsSF)@;3?O+dh6k&Gwt?&Q~J4dg+1o(x7$1SbDi+le5!KT
zc5LfZZ_nGw+@igbSv$y{_3P}N?Ku}_7FlQCz3i>C>+-kwdDof#Qs0K~(PX{d>R$Zz
zbKRZ({$$(5t>iN&ueIgbI@{5iPj2^@*oM)wo%Ef19bZe{(oTj)Zgw}XIIfD@{PW&F
zesNpxAA3GGcKpFNj~)N*&z*GeA-M1C`u%^7;rw+=-uabHOWyf64-b88{IQ`QbsieI
zcN{l)=jO+k-@f_r+K%sRUyiGt^n!mK$N3%pz2m>}@AY?&UXkOPcVF`1@y}fHVgIQu
zryj6j%c-lM3g2G-z3}bYZ3pgL{__KOPW|Hc2VaOg_KvNa25#TFsdoFCN5^kj^Jr80
z9?$zZ@0?%p>bK3`{O+4q?1R2<+Wd=Ee_Xn4)&J|c`OxF5xXqWL@69K@`#TT){%3C2
z@2{BHbm%+3aowTsT>S9<Kf3m@{XbTJXylpkT_ew+?-S^ILv6>M+XrycclnkV{A=wg
zzkYnZU+;f$HTt&E_a8s(aMJg%+qZn@)bE8=1G~Zxr|x?Dr<ecY?K^9~xbwk*ciwqh
z?NRjo<<@Prlh!<u-?8S2c&6zKpEvvKU*0_MwqG7t`&{dhTdwSUb?L_@R(H7XJ9T*8
z_nmQn^dUETzxifPBd%C-{KSg49`CMRSFdf#>&x@Cclw{c{Lb;8E^hdlN~8Uq1Abha
zPJg`o+V<!Dwe$CmZx7=hH~xN`ubng0UjDtlrOmtFvNX?6K7_gNknt_nIQsT%>);Ms
z;&)_A#&0>PIn_y<%eMzNHNg{*A7<65?Rj;1=gLp}pKRZme`aF!W+ten&OGhn`TdRF
z(92gp*ZS%$m!bEj$@+=c<@IWg-u!^fA%$L98@>J5TaO?6Li=9y`uzAN^gbKCSC@Kq
z^`0#CIt9IP<J+<&em+~0-`%&=f95Sq$8SZiQ-TfLZjCzb0FPd^?Vrwna#FK)d+G;t
zZs@;wHt_ANT0`%FdKzk-bk!Dq%X2BiF`4bXG#PYbn^U)T>ZG)jd?InlwEdvPXCvHf
zFOT*7n7y*cPw&&?-}Td^$<K^3Xnh_AecsIdTD#I+mZWLg;uiFp4KtSQlPwM-GbhSD
zoV&~NiTY$n!(L2}f3Ysh7U%1Fw_1Pw0J)~GPv&3IPwaW!ZL2g%%O^*AdnVIWE1_1U
zJ9^d7FF|kV*O|7<m{fjX=q>#=qgVRM9_Eq6P0b|D&FE(6hD^Qwy*3P|^_r#iY;eX#
znK#jEz)L@Lb93&p)?oMxYO`0~pDo_RFX(Y@^#G4EbZbjLbo0^=-JJAu#Zozc@)qvL
zam@m>gVVKqXj14rt_>~V99qnaMkL0W?>6F~#R=F=7P6YerSTfv1I&%<rp<4IHc!0W
z<qt)^HtE}-kz`HWy3&n9SA25nVf-k*h!?o;K%D<+9lzQb7X$qBqGiSM7{J@5bKLNl
z1)ne78p4?pZ)1GXnZ&CKo4B@=0p?35oxJMpX7XQJ-OeIDiF3GzDO%}rf^A11g<oZo
zEr77nb{5)->daHF<-!rC(n$44nQvPbh|S~LIKX%G+|iO4`5l?4UfLu!k5kT^j7=&L
zJl}32J}#+bSVzlD!QcXqdc}xi8x!|FJl#f8itav;66@g4{Wqb;TIMDYm&I7=>CDrg
z10AT=Yz4@^O!7AFh5Mnw3=z=jRH^p6oS<&bu|Hrz7oD5<Bdp0RmK=&E)#fb0=Lk?X
zrm*Qlu=94@7Qf@9?>w#L-N9Yg9{cR|cRjH0wQqhr*){svhtJz^!Ud1-Tyx2_CtSOD
z`yux|a_Z%8UjH9=tyy&Y89Q3HzU-czzu~v*uD|Wnm7h6p$3@!@xog)smp{aB*Zp_T
zeP`Ug`EU5n)8n7jZ`b{?de53WZn^KMyLKIM)fop}d+ZU(JrCS5b>9)Ut$*&bYxceS
zgrf#_uDQH<-?g`0@LtNk=grqA_l(}O?!7y1TYoS6q|ctPWAXP7`PRDguDxyjP)Phx
z*y_zXUT27c`IR_+TgkH{XnE|F%scC8d&d>c+8R4b<|E5!KkOiTHH`5wFqc<Cp6z9W
zVXM9M!Yx)u;v{>bVLO%mMkncbp2`kQU?)Aatl=uQjl6H==L{}uEVWOEVy`)2qntRu
z(E7Fp`yR}9U9S7=e48e1B@<1T+5+V9J5NR$u+Z+ox-34@<OLV|5oMQb3ZPX8_5>aX
z{?FiJ8AV!GykdLeu1KEULk78s=^J3)OU3v-qM4*4BLvt(yGpV*@TQ)jq&7TKuPn9@
zDoyMTL)?dcfxTfb5vP9dupRd|+zfZX7&K}C#~*ODm(M<rYWe=->xm;8Ql;y8$kFMD
zOG5|RStP8394wzhm8);Gx>qK2O#{u1jQIpU*dlDf*R(XL3Rfr@y};mQ+-f|`#X_qb
z+a08&#BrZPV-=M`Q&KHo?8&6VJf%=w!9uc?$O)5mOH#|m^0YGN^6~+NMizodUlZ;2
zw&JH>om2_rL~L=Srzx#@T91N`EP0rqDC=NXR~D9}e6h^?UYk+z=v6!~)Ydl}&BG|t
zfIM-TWtv3FY#{L3ClWkZF=S>FqfRkg3GF1-L%k5&n4dyrpfeYPG)OI?DPF>S5eO~d
z1Wg>zN_B&6Xxt93$8vSgWZJcCfV~R>flF0aJ=J&8Ak(x*pDDGddoe}6NQ~Xap$H5d
zO|9B5G#gnWyC%Z)g$uw}T=9J@%jP;F1bGDu9l$j^D%GlmXeFg(MI)<TC~HCV+&J@b
zPHfW^ouz9#ne+@9HEw{|A(G4#N`5d;B%l~E{}GRx^OUkKR*i0iHC#THp?>Dwwy1y#
zQC6Utz^9t3%QZw1=s9P~3_-|mdm$Vqyvg{>8!-yS^Jj4#@#e6%1P(fiPLh$LO}r*`
z0ewmLt+1m{_5LWVz82<UnwR9%>N+d3V?`vXI`+BZxu{h}pg9{ciP9;eN^jICIM2gQ
z7hvU?K~?RQPNOWcYS3h-loJA=j+qx82+=9<cr_R}ixwdXw$+Urxg(6tCYz*0vMQK)
z{?v#GXp?D&NF`7WrNjec0W_s@HR?N>)mt2C!U|+ZUdxe@4i-56m_pR2DcP57jF-WP
zoab0?Wu^~VTv}ry#Co0^!o<Ru%%LOuZeq1lEJ22uvo<W4VK#FrLs{rHPCeLxITM$>
zVQZ$-*bO$zt296!e|K$P4Goo&kaCF7kKjULD~pC^jSk*=OkeCIV;ukD@*c8jE|^0}
z@)E0Dei@4R;=xZ+hrKc;CUScJiNt}@1p;B>vJmM;R#)CjRwZp3k(`ltB*dziEs8jK
zJc24|WZ~KI*iTh0qBI{GxOO17ii|WLXyw@3s<b;u8^g(tgKM&?&4@E$z>K+C71Sff
zp$~UL0H>RZ8T;!fP!xb76mJp&j=xEIN#-Z;*ZdYzp5~<GL(PCiFOBlZGNOLWNu`jd
zn8op-H7dCp`5~$#QCYfy+dzH<+_W%x%a>0WLnc`2>V6{Q9F4TIhIM!@!W@$}82rgR
z;?X;r(HU<nc*HXe=!gx!j+Qt-(P>3JntGfv$~QcXRqqF~vU0YA44C;oeoAx=Ig@3T
z#JtV+>DAS=*EB$NBB!U0%wTimVl5hT46m_yXGx_MENxVVhSL3^`5Jd7+iXqr`(N<R
zWh309BB9lfSHO_$Y>V}wKMd-<r7hW%3$D<lY)<n#t#cfOawqW<dd>$KY1F-c+Uy@c
zraZVKk-?9MrnYyU4f4q-6c3(?<cUX$k%#uXELM__qVto~QP4EUf@3%I@H1Gn;em8G
z*+*@LeiS>A)g0rjDCa^K4x^)_os&DkJ94pk#`YaoZ8F{(OHdn52I)}E+FBcFCusa`
zq^BD=XD-YkmXBz4WJznnOqJ3km}3-h1X)(KTQ^g<Pu-Z3dlx6R|BF182;^wZI2cCh
zF{?MsdD1OkWYd%roW0g2a?3+sTkqQD*({>?mRqme+vdjE)h8|s9NMe2yuF;d0y<;z
zQtmnRIyxeN%{-r*6soD9fDo%>X&Fr$Abf^U5TZ}eTM0uk>P5j`t{7)A-9c$Z%!*=-
zQuY7`9*f7a@%j&b7`=xs2dt8C7fXn7k|(ilp>=#_uZApu=CP`d;ffMmNhM&67sW_4
z2{CuZOaYtMA^@b6vx!ibI~9DAgZ2u+(K1dPacI#$-}So~anUcRDVYTEESdN)gha*J
z$2pXC`u9p9p$pET4;{}u-MmXgk5U>GPdiGqOPKE>^h$yk6ZHzH*PHf9Rl0&8QNa}p
ztk_<0h67$b_~Mg8b;@CI(4`_fGboHEX*o`abLKOloZAX`a!DM+L3Wr=!g!X^^C63^
zBlQ&lJc99Oe76ElHURoKe2b)J)X9^NZc^qk&BA%?kDK2M4@(9RVwoW&sn2McdW^@U
zHi>GTjN-a7_M<?jR4=deg~8|v91{64Ql<kbUGa_t!w2@E5~&yjYWD(iA5gLES&q`(
zhAvZ5vM^2psGCD1GD~HgQWvu^;)6}XJ2*jQ$)tjj@ic*5EkseN{wo!#BBO|$Iea-2
z7HNu<fIezi<+C6UG}s4z6)}db`Y=$bsSCqWoOvoR{0L<85n=5ttKx?uLKg00ktTbH
z$CuhGRdEs)AP7q%IVin@wo!`cfRDuoQx&G9O(^R{9PtZ=o>6Zsq$`EXqb|5k#1JYO
zWGcmX3N4thd#$E~qWOYQu||O^E{=*qv?l@~u)q;epde@}i5OlErZfTVAzMI%;vu9#
zzRo<ID7)5iabX|~xGtmx;=6G*^8&Cb>p~iLa!zxdXDD{b3*jK$Cq!j}k0y3Sk}o-^
zMi-=thqdh8LG&e_^ip%hsftg>EO=&k*Gsf0Qxl4-IARVOFhfPvgS^xxf7iM(5t`F7
zTf$uE>7vD*v2mgliyiTU%+|G#$}23PbSp&Yyu-WhRopUf7(}^~*r@{rsd&W^C4OQ>
zHfs=z^2;{VY(|pW97;j-ktcd7SwqYZk?V|LELMf0W{}8G_@e6V1bAI2N_GUAJU#s@
zI8uOEg97cAR;pC$r_y2yij^uBy0>LpOwNL$BBLZeU>OQ-EBb0|7?B(<O61zU>_oFJ
zR!<su86@(=e6r>BPeKt)DGBh=MH$_wLV;@Og(&bCJ({o}l>Y89WU<P@lMrCsow4L}
zgkmX*4R8_J6K0AmRINT=RLZ*r+gVyjgp!1|6|gX9pbGp#sX1r?!aO#%D%VSep_Pqo
zI98HARcR7HN)V6eA+`btB|9jE-jQjuXu#b(ix<|5#2^A=r<5Ac=|~|!7j=6yi4#pF
z6qhdn!Nl|pgH9m^ekDVfE)KT<8Z!mxjDG~!;3=npf+XLY_c3HW1&GE_GJO_GoWPf8
z0CgoUMNq2NjfR%kVtK`Daz#Rjv|QXtlB5u$eG`vi+pG{pZKw;35xo4aeL<C_+sUHz
zf>M;LR%#Vg_1oWkm-ukhHv|<7P5HqkGjRkZ1aovtM=Zdvky+?&na~B``;6weD2arq
zO2k6+@v>s~*DjNMDI^BHapF&Fl;G$mW)2mKiiW5&Qp!eG;k~8IGASP=?xQ6@kRR;^
z+9sC96!{i1Xr4c$2ke2un5*b)fg~i015lv74iL)_ViuezK{7O>M9`V1FJQ;4t5Zpj
z?I1nkM3RbEEg*;zvj7G;s@m?B;vwz<foAcFM@@<bQZ&{^2#}exmJr0oIX0>ntWPv>
z70^LzlBIyQfPoMs212D>P!SHdTgGJ6T4}hvfq*^02@ioha4ByIz6`amuF!-F&`l`o
zUsRk_hYLQgL?3-4qQ<PqgiOEC)hqFPSx6K!E_&MgC$5OgBC|@EmWK#m+<%BMbv!T3
zMO8!GUPKw*GRvBwtCMy%;&QNOU<=S25DC=ed8dm|AkK>Y=6Ll_7c4DE2_i-!uM~sP
zyoc;kyrBQYnhw0^p|Omhc!XHpBE>~Q2$91IUnGxHi${@Clbaa2Baz^DdsteeOW6Q%
zA#+63Ur)UOa*#?3X(HeRB`ts!QoGtlvEo2`7ejfyU8V&}f%r1sEYmw>9L-HdYljsf
z1e+<-=<X%a(|%&pea<K#8eBEhT+S7}O_0aI5K~1n^_SfcpadA;qMH<*oH@lq(9Mom
z&l%{#_v|Y~J+z=n&r(NJ*I+IXq*X-_s2m+0sB&M_6GsNTboM#2)kWYpf)69D1Gbo2
z1iGaMKamR*J>UVtm9#)DuhKVp1B_g(BNYZ;)D;#P!h2W)mYSA=^wjapYzr&x`#*-b
zgacE=XJ83d<4W7dLB7(GFeB^sC-jTij>@vC=Uqn+Z%7A_*$Bb6>6#a5hO_}|z1;Ko
z%1y4J4lS#7bp7mXCACk<pUiGW7Z}s5H9`=T^6G`_EbY4puJMZX%=B1eAhUSifzRYx
zt*Xn<e6k&q_sHTd__;tHuET=vxwd&nhH?VhaUm<IQ+Ymz?39W!z-q{<L1#$ImY048
zjHf0cT*G?KWnW0rtZs>O&<8`%y`-Z-mt1K*p@*D#Z(1krs@Q`P_zti00hxBNZtr$<
zMk+gm`p=mUDQo!tiNik5E-Xt8sImoi@-$MrsFpOWF_a~?H>63M^h_1`W^219FVPuY
zrnWq(2jtC?v1!fv&_HTaXgbFYXxBoYfn54nVi-S3CTF-N<??UDrp-fU{wUUGY>|c$
zuIYvx^d$ToI(OFmI(i9jg8CQHmhIqq`L2(aOB_|28%Ki{d^PKFH0!hjpGl`YLApQo
z?gZ1Oxbv$;iO%HQeGmzL+Sc5$xwYl{mn28tG_>xOPgdsJkF09V-?QqH{2%&HT=9C&
z8{PlwmB0Meg`0;yv&dzy+k4`t4{uE7AK7@J-EhE*hwpgh__Kd{cxuOvsp@gZyfn?O
z7+U_8XExdN<DnLQob<eD(Z~DNOx=|Hc-O<t&e#7j+4}j`3tn{gZ4+nTe81m%(ItyI
z|Ge*B>sFlX?tW}#?K?l~>FwNqN%Ep|W}2^m!;TmJ@+Y?>ojWe>ZQiu+{nGbK819x|
zP21a_{(AM<n=U``*{3f*@uAP|JJr7Dgxen8dBPo!-G9Orq;34ctA6}}$Dh9F{>Pu5
z*?jf)k8S<*w_jiWz&SU3dj9bnK7H#~zyE>jpO|{tvrnw=!7U|i;LcxfdO_b+q2Bj&
zs6YPr{ikjG_Vs&x{|y&ZfAsgyP2Ks}rbR!0<j1w^{{7UI*Zuox$2{=B4LuKk|Mq12
z*H-ra{EGUjU;OFE$KLa&i?e&4`PvKbzV~ax4_|P5b^e}xtJ3#Z*YJM*Cof)e-cygY
zo_+N4foETT#fg7>@!nJI-yh$4`2LBW$DTfZ%Xv>fmi+wT-|zSM)0f!e-?*fG^&Q7A
z{^=9f<q!PkhR@Fb?1s<Y`u-pH>^kS+)1Lj)`lZi4aY4^dPrGj5&Rt(!)c4_5dhz+K
zo?RbW_p<wc{jK!JXFfOerh6}_e(KESi~eczkI?tDMUVaaZ&yC>>u>G#@N;)ow_j0j
z9Q50jy`S6kquO0hT-@Aw?<4lqt`7{fe|#q$ygH?`L;GzvyYGoU8~^^^8#lD}*}UZ^
z`_#U7lbc%i;x$_)|FZWde$%3lH{ZJV#veR=(O19o7pt1n`!&4#^qO0?o^^G;=BC<y
z?q6#A&0ZV6di^CIY~1|MSJZaB`ikVIU*EX=fJc+lKJmpTtn;OF><f!N*x2}uaO{P*
zZL%#lZ?dDmW{ch#8h+RO4ae+y;D(jg?X+6`^4=G2JGg#u=d6{z$361hWUym)%$b{~
zChy&1C;h7TB}adCpUpq|v}+opT6+7p^=@w7w0AQ8zxHkoZd{UFyjR1G?zN_8-6?CP
zC-X&#`=;M-wmlPm@Rgal@AP<k_LEompT7F)eCwu-%h%lK_X}Ts+~#LKm_2sU2eW6<
zx$lKvwe&hW?SOx_MW6W4Id=2r8;*JG%+})j&*Y%M8yJ|6)eo-xXT!g<^WEg;<_#++
z7uTjHZ^@GMl5GFUukxUV&wS|I(BGYo-ap@BeW%;U`~EB2I{mMWzHoXYIlg{jQmIc*
z+lHm)H!MxV<iH)Bx&1H95?{$y))xD%AM>{LV>bOL-@p6Qf$O&a)#B=BmM<QkOlIaL
zSIu-j)o;gsYSupeFEjS>wf~uHT>AoBKGtXLPc^UcpW1rOW|ohhaB|vn(nfBu3|P}X
z`Q_C%^W~-6+n-)~%D|_WO1DS;AD30(xW>!3-Rk?!vTXYGjmGp>8%!W}DY`M|Rn2Z+
zn)m%Gvrbd5RQn|B@ySGey2t#-EbMrprDqK%!R?>UPF2=1_2z?NhOhd4%szFEE&kp9
zRvp`F_PzZp%`xWHPqnYHPmO*h`P4PZVwTi&av-TrQp6b2%%Pj1n|t9>R<)k{kAOaR
zYwy^+7WXfYa6@|_?&=&r%C<$;#f9kPPy2XL#HL;A!IJn$$LbfdDtV4uz}ZQ&V7;u=
z!Q$a!=mYtXIo7&1>D8chd(Jxb2H)Rn+NVhow5>R&GtV#7IXxe&CkV(`Cq7}TihHvN
zhf!ymvKB}y^{~_;QM&;_h-C<gaaKe+Z0UqQ4-iy9vx_K%T1n6ov_<V6a8@iKkw<H^
zBsw%NO7xZyOL^;E3<WKVyrrizO_%Rf1dA2mwUwcS*&@ms!!p6)V<d-a+yW(;k6MUM
z0l-!qtGB0$l%LziqL8!$9hyGWq37JJJviFP^p6au#5s{_I4PL1g=gQRWS6l7y5Lo5
z5&^Ct(BrRHBQr>^p!)v*Lf;zljP&@<@216<+H~gZBR+AzBsP&{cFR&WR=r8izJ-ro
zT3E%#YdZ8Ew}~2TW3RcXWjr5E8h;3j{hf2Rv4Jl0d<H4w<FljYfBvnjcAW9_4;Rin
z-TK5;kDmARvCmz9&jb5zc<wcO{pg0Pc0P1@apq~mbJs8a-V^ukJoSk;uYdOGgBRWT
z>=Ui;KmN?F-#l@`QAa%YvcI_dxf?DzVg0?&JaEMsZ+!fjm-XED-`8(`^Yss2F#4_Y
zUb^F%FIDgR)8)6k`G((L@SEq(eCduqT%X+az~xg9J@NhZFT3Zr`)+vVTLVu&@U^L3
zPuzCFZ|?fdzL)>)Ym)mO`|Mdd({v)|0xy5&+QqlM@2a!i7r*SY-`jDGJ4^<dwvXFp
z`)sngvngA8<XpD2&xV>8|0L8pkJ^+wDQz|%?%iC!xc8PV8+zNT^Stdh_0FdkUNoQn
z%7TA%@7ekBY@oAwwAJ{o|G?(oWb5)x!|Cu{S+(+4)5)4FAK2kczZT~G)$>!fDI7iU
z$b~-t(xc7PzGn6NLr-U0a?JRZOa18Ze#yl@NqVI3YHrWYCExR5;6jg%MoV<TVf~`-
zh(gTh1`3M4t#0;w@N_9>S@L}9pT%M?a(fn(K92(-Ue;Ow2Uf7?Ow$?rEF=i=)~W`(
zwc9xx^je+-a)+OeJrx{-1PIm)_>3bRRp2O;NF#ia4NX(NK57C626$5G@9P9(pGVYN
zsAawu49JF(4#km1?YSP|zD0-123-dwcF3h>p=r#ijwuTGf!Q^VP_^}}3%B9}E|?D0
zXzp;8uq6ai-8{dArDF*J^AV4VoIE?6PG@|_h7oH0<IDlcx|D4>41-DCMi}>D)Fu~a
zE^$+yVFQAauFg*QU^Maws&Z+uoX3{l2Wz+?Ne>iVZDcO@j>=a8ow8A!&AH-Gl2O#^
zG_pC$i_B#4%7(&yNYYdwKIA(B;lUCW?LjN0-5gQuLqPRCi8ko%z{@BM5_L6e)Hnme
z;?n045ISP9Mn1-;E+j;SW7i<6r%cB+8rr8z9Pw?U3aA6iPCq9H;V8a6f<8#^v-y-u
zhbC&C2%p2LfVrsSlDsWKnpRSZaj9=hpVT3b)u=`}fw=X$fiXRTY^Y$%=#$ph%Y4kw
zl`9#ku&X~l`U!F;?JQrSGJ2`ww3KKSOcRJrg6{M248ECXs46xWLNMf4yr)J%mU4;J
zbgi1g68|Z8$$<619k|*c04C{V{HhV^NMHxw;{sycY+N5=O<XpdjA0Y5C7a%RQsa5m
zPGlxh@t;ty6`&h3GFdGi)<Ey9wN7HGUT_d|PXWUz&-O7Of>icpj{e9OxA?)uVnWEs
z;L|L?i%ds9^_IrAK$Kezv55l`dy%)ZnnHsr0RfIoRYqW$Bc8|k_CF9!l4-sO?DKI)
zL`+;Ydf_Qz`wi3A6$4a(O3^eJDJ*u(wLt0|oje3{s*w5J%UiL0&$?jPots`1zedW~
z!5gxxVTV}?@pQ#gNuCzhk^!jGdQurkpkK7>3^=9~`i+BctMUE5Uy=mWCb1AYLFZv<
zjxB5umxm5_Ad-F$ZVltP%qZpX3&Zl!kaH0<tYdnC!mk_BRCT=E#f=v6lyU3Do1sAp
z69B6E`4|BmAkra{*g<z7w6e;2uoBM-vNoxf`6&{e&f^s2NI---L$*UzksB@PB9&V3
z9i57pC`7kw!-PI|tpWqBuExmHWSCp#q)o>>ko0WA6%iY!{{tC)UZDdaf99NBN_GU%
z0eD93qAUoo$o7(NRi!g8GZzX50@bej7kyRwK=PbrOI$!EY_vs{`e6Z!`4f2fQPFgi
z){&ZplbV!1$dBcz0G~KDE1(uiwINOTbv?AHqsPf<$_|O#`%y{nRIR4?fT7q=Px~Sw
zh@p?ia&?!7z@p#~HN``A^KNWf<KDr+w=Cf_<l3c~jicOzeWE22A{<I{?!Xz}eI&|B
zsjBWeVaa+9`I?ZrIUOO2BD{-*hOG{jR9h0PmUt<@IJqJjhmaO8m03bxt&DKc=7oGe
zGj#(EYD4|Zxw?6udChRy%ZcaMn9e$uqV6^x(Y190OW#H!jRc!x28GvLWvDa22`viC
zY%m{oV{`+|%$eJ?P=yL(3)gf>gYLq-m2hD}PIVLvQ?XCwwoe_Y>OVCoY+mO0Oc5R3
znyTVByqj^wcbwj`6_(U<6X_!)j*hl{7W4&D{+5K6ag>h2Dtj|syn}7#h;x;<pvPDz
z+9+`yRUw-k<rzC;BSq+FHF1f?TQVJp3WoC<SGAd+otS4*tg_?Jl2GF?l{2IxGc@eN
ziPTeUz~G5(Wwn}EHj@o)ab!=YeCjIBHQSU-2Dn`AXD-D;`B<_Ji_ThlwJmYEjdC0k
zBTnRPOPa}2UNsCd-Zc!`lzJpC^!O|fLyo*h+KWQkp<QiwxGx!j&CA5?EE&%a3tw_H
zNG86@kpZ6{!$XzD&Qr!g5|$7JbmnQ`TiC!nBgv?eAdSHsm^aFmkx(RpTA5ZLLxeV?
zUnDOlPY~B}A#Ly=ZgV&b;$#GxuSp{Fkcv%ViVSYrG1`K7`G=^ZfZeQOi;!D7=AtZL
zElEQ$Os>|sOqCtfhf9#2-qdP|l*S~a<BDaDnmI?Ln1x~)v=M|@DTNMeD70R)kv`Rh
zL0{PI-pgVF9+bf5g5C>6_E{B|3_-?z5MA^^JaRN^?ADOvQJ7oGDC0y;t=UCnBo-=Q
zW=wve9vPgLEx^Td8nIZN)k!^Pmr2nH;sR!3^(i`TvJm3qt=CBuq0=DGi_gc_cTvyy
zVhL0<GFEJST<Qsl0%?%n-6=#IhDt^Ubc&5e&0L_H1-`G$*v_L|hN8mw+l%VCHY(4d
zKwR!nMg8%*_d--N%vIPNV=qC)nLZ?t1w#0pEm1cN`7BYU=V7nVOJTq%za<Ga;^`QZ
zkj(3=3E@ml>C&%-qbf5j5LLQ2q(EGbF|yE^YZL|q)A$pX6@x=45}5RTKACAmm5@m<
z3ipJG&=4G%g{cm1Tzsv(YA(d1Rp>$zDdZW%a;eQ2G5~iR9%?y70L^M<%Y=G<c*qth
zV}vx<Ih;FqpVL7L)M|v%2<h$(X@<aS#OX^XyZ~83g%o`(#tKSGJ+t7+OK%F%Cd$r#
z#Kjruu|+KlvQeRUffl-@wgAmSUGGI9l_XF)tY#QmQY|2gBM^`tfz@PBpekm^1-#|L
zBDm-y6A>zxeu&Q<2Okq?rFiEfMl|IV;L5OgP*;?j!RQe2rhQ_f4DJ`$3M9zZAyzd`
z8zEGDQE}449?bOnf>6m8$f{H$Y8S#uq{ak(@0g`Z+@55C$}O6Oz~QQ_;emciRu3hn
z2k5XCl?9uogT(|_G(>==@&J#MVHSWD3f?irV-`ZO#=bo%VwQF3#DL7D%tIiuY?QBA
zmn}$?4V5)6ridePaEP%eo>*ZB7pG?gH$)NWyu<y^6gYkcLo!+eQ*IZ_(P#|VrXa*n
za=R4GuR*MWNOVEPxVmaKTF~W(fT|88PT+){vc90Oj#?nhaH_`)t^}kAl%o7ha*+cS
z#~aLfN^25Hf@3EWqfiP<#bvf#nvBxYIT(==?SdS7JrTwD_xuS0j;Kjjbqh(yC#Ic3
z0Upw%P&cY+t^nC`8=b0{u^mL;!NpN3jv$ZZiBkXI6_uftM(7;nu=gMnE~?6=J|xVL
ziuy92@Isw2O4M;=lDmyxBtg%#&5xj-;K7jP2x1-wEg*z|IG?FD7f9=Zc!DB1!=hnX
zS?^56M$?wEyQLC3#|CZ<$v&2p+q!}$`p^m;5+MaN%g~i!saX+|Ef>E^IC2q@fk~-S
zkr}1<LHSY9R<Q+v=7xf3iFpOF5?ZILQ9>liu0XsX>hm-&!e)A{ugt-$MQTcaY)3B1
z2+<IpIQlRS3+NytM6DFp6Y4JLqx`H%9HB2LJ{IXIp-&bpN&*oMgb=UnYGq6s_=QCJ
zu(Lg&h~U>{e8Oo0f#cdRmX{D|7A7mmZ1|U~2PK1AQ0XP43T0~nS~7J+)De@F2mvq_
zNr!MB5=5YFqMZhGZ=v8R`4lME7fQs(FqC~U#wIAkYpYhZAs=G8G)rVyb=po8ThNv4
zqDr2vjKxnG#b}XS`e<}miAGhWR-6}Ojg(TCN180~ap9^(9Q&5i*u0qnL{BUL$z5oX
ztw@3b5{f{{nRH=@lvyF@49Twjl~xLhXuvN;I7XXeK5dFLakPW3vLHv0FvJ8rK{i6!
zkp!2Ir07XltW$TG7i&ps!LAlVVIwazg4QT18jDF7?hExnO;tD;V=3@?=^{$&c3B`Y
zn-@j_6$JX6n~W$Mtc+$W_Q#?)7g>EwWpIEvhlLFw%oGxJF@WrYP|hn9YtpzBgW_e!
zHy&s<IST<kSFDwRBoVln&!VibhnZ!`C=Tv4M79M_%qYR+<fl=?D<LYSy^ke|8ps0h
zrc|4VSYjeC!%^`7j~640zU~3VamMHp7n@Buz`dfQmIb0@W*#6e@X^OBikr(!TdT~R
z6bd2r7NO{tvBM-tSjbLd>hT0og16KUbfrP`d)UGgr@GO{rlnb<F!D0ciZ`6%_p*B9
zmR9*?B^#xh0w4Xt3myq=Xz2n`vYnWAlVWz`1JY8;7lp$kD17OyFF%u{4GZ*w$uD%E
zQbd~^4xEEJWs@>TE3K@EY+k2`P*6yS0F{ew@=%`hBF#y?)cbO7c2qGyE*2?}c!faN
z1=mHQW^uNrHeEmir^|(4iH|hYcV;w%&f#2A>{&&LgLBv>_L-N$y6??g2Vchh{Xzp&
zYg-m9pUtK#vmKNiv`HyzOn|wKu+E$sYg@U@=K4FDth}A!ls?0F)0%eRWd9Py4`IxY
z5;9ZFD&8@BH^IslG91w`?!NFPUfSf=;58&nCUawuZ3&ylkBpkn5?O<#)$u|I{eEWD
zX(6zbN#pcMem$mz(af?9fmIFIIzyXOZAp_7Zxp3sOT6xX^1<r_B9D+!m3w0YjbWxb
zTiu3(H@`F#@+NCk#aRuzr7tWmIVQ2<m~k(edpQa7z!0tbPtP&75@HoQY`|4~#|}Ik
zv0D)zzw>koKa>JGW3GeQ9N*nnea29YDaH5-KlMRi+Sa_1>+1B_>EmNt%+%Y26p5{t
zWzpa^c9O-<d~heuEwf<sBHw7u|9^a)e_&L_wfN`W+{Bv@;3h;2NO7{Pu+kJ(M2(0z
zi7Q<Y>uPBqTD1$Nh*S|Rwf=}W2~ne^HmJ2!dAg#t)L*5DmZHLfw4!3w+UJ9!f=Vq`
zRO(Mu4ByY0yFvT@_@3m>oH=vm%$eUm?%Y{q(WiJ?F&9x8f~W-TzM{a}5X5#Lu2SC-
zL6oB()-+QF$&prR+dzN0Sk<MbN9t6cMS6kl3ivJ2_AA&?&AzhBx@m!iY=TyNT9%8T
zV^!+ARs|j8jc(w_ny9lCHqywgk_=N?`D1mL()^4RE;&<7D1fr?L*5+bB(45%C@5u;
z<C-NU?y3@B<w+Cdixae|azuT0X4{xzaY=`q$@v3wgEi?keUI5y_Ih`xf9a66^xW}{
z$G*AysW;wVKjW@+Q{#x6hs<C7p>AF9x_z_#;%Gu@V$^TI$Imaj^Zn_&78DL@8+SwW
zwZT2y67&A<3x?_PuMPgNZ~s0Y?`a(KX0*KF&-J5@EnMBd&ztFSV?N$ofB3pZ;I|Af
z`(*t1WB!o)SNb1i_l*2=afE+)sx5W&yp(>@TwC_R`T<`3(D98|Cfic~G!wl&OZI-Y
ze97L+Mc-5Zq0}vNmp^gy+{Z@GU$W=p&z9^N`q`#;wq3I6oj>&KnRD*PpUqjYYy8=t
z?-+mf+BMyK-}<b3?*ktfAAF5x;QW~{f7&y1@2@_NCe3+7ojjrEqqZx0KAJad-$$b_
zd-J2wqm$w7XUq)O)V}xd(U<+};iHfL?DRu^_{r&q9DCL33773#J@m+Z-=28+AHF?j
z@FzR3IDg;HE0Q0L{oV8*kNsW4nwO8iVBgC}_u1Auq4|#135RWddFRaCFYjy>eHVS3
zZ^Ltsy|-rW-^yNHxaa9{3-=~!_r5du)m?8bdh@f1C!zCoJH`*aYVY`Q$9~+s=bgWH
z_xyHm@xlM?dH%thUOIR8l`oyUa_!3Ktkc?}(`!He=*l0z^wE{a|MQCx=U)EBh=$qq
zYrcDLxaRnCA3plr^$#D{aLblMF4?!`kfZ+n;DpxQ5029}ef!-x`@a2`Q6KEQ%<S5E
zWq91Y-~C|iyx*0-{p!&ttbKK~zN2;ih5K4BAK|OxIAL<+3OPHJtDxd_y;8Mf)Bn7F
z!-hQ*X4^e4?N<3dyP_$@Om|y#wQbA(t+4%pg}ZmWwIjFVcgyvTw<ipIwS09&&yUi<
zcOIXozVrQlnVI2GZ|1Z|8ty;-rLp(VT%>;1cS!Dm?`<ef8};;tsWU&G)c?2#2lcrk
zGicQD{|-l8b#})A<+nfijpiTyDVXr_x?uj=<^9y!-Th{Ld`45_-m1Z^qE|?7_hRas
zqd#dn_mqAcHmZB=#+^^ABdP3%FWhS{Rd?G<H!SS>)9^W)p8d;%xlQ*D*1O(WtY$6T
zpv;MjgToJgIXd$6mkYZpH|*Z|Y)?a>=Jv67fA7PAJq=?jZvE!q;+YAxVcP6WW=_Ra
zZ_dPpgGTws)Q@WURQ<LrZ>~G>wm(&mJots`*@I6n8&)ysfFIm7d9Zq{sy@52W3-<4
zWO?S7sdK$wHhpvYzUBQId$w1#nj!8!pD}W-=wIAfF*C}K33k4eetqYwA9f7MOl>Yq
zRXx+DCO*#AKQSZ9PcJ{U-h88bWVF3|<nyl;T6r(MY??}|)9%uZ-ETAx$t_H)M9!)a
zMH{@hvu@$3XN|31d|5R0mPt`l*Cw4Zrw0QEKOT9vzQspZSB{;sv2u1)mJ9sfn_%RE
zDM9Td-Yxs54XJAyGh|59H)apsNXOuQyY9WMVBw*YXKlP)-LUZ%(=tTu@`sqzBiTCt
z!ED_*!=wD$!&QFd2AjzAwIfZjFn6&j<ig46<ixkqN{wiau0Nr<eu%Mw|GZV_1a-@v
z$^;8DlcJoxG@4sht;74WI-K%U<W>K7<aM1lHt3o(HnWKr8h?m_RKWzb_hy3HT?2;H
z)%|G55H)Caq>h^%y&`9tjw>>1h7C1!;h|@@MB!?RpPtvOqH|k9H?~oFxrN$nv`Xz{
zgt>j13aYd8>%5~_#s}g{`l;Z%Df-uCO5G06&@M#cevD^{RkJo(<-RmumQp&;;1aR{
zb_3%aveneSj7VAqQv$AN<2jROJoi9sqEG&Fqf+ydN)JkM<bk>GOim`hOc*O?p3Zt-
zI$<@%;3iBpVu@CCQkHnn4;whODmTR|y`hpF+{#G4LRHrC;Fg}d6CG}5DBVbU6Sx;5
zXCYo2c#1rTVNem-ozVuy4}neaWaPnZa94xJ{4H{ql(_wjcB-iyZjun+<Fw>RVr#G@
z!4gu$s!p&@Y%I-v6cM(vZqLSprUQe!NGOpjctfc2hCPN5PuWownjs;YQFAgfEKiHf
zpOIn2(`U;GE3$!VK)S&#WTP=W>?C}oL&BQKx5P*;0CMJOG^s~4Z2uRWp8JW0G%O9O
zt!65gwOwkv(xj%k!H=f;+j$%4N158~-t2@$+QsQ=?l~HwI(W&yf$@G;6!^bpiujsc
zNI0eLuGf9!9;a3`GRhCG393}j_vcrBHg?;dUGKl*&OG&;)zkOYqxSXeU2$d4e11P}
zP22lFdwIm?Jv}#`Jb%rn=l}fnwlzP0cla0k-sQLJ)@*6)e@9!-pFTb6i+w#eU2y!G
zr{<ipw)N2`znCEY=O4d%%Y_Gg{^2L*?mOza`D<=#J7nLMIfs5R?~a*Qt$6OL(cJU2
zX3~TM_9fT;<bwC#yXp_O&Fs%rQ3t&;{EnYox#GO}M{jwz|3jxtI6#JbIYac!ol5OH
z`H{YtMrW!y^+mNbFm}6D?f;tA<_}Tlt3Ojd`R?kD8QDg=B$#4vChwO<i~UYcA<oo#
z!3~`a=iGB+s->u>tWT@)rioYae^(2K{iY^tez?A^xU74Z_w=Gn+0vS@W%t;y<uP@>
z|DgJYSI$jx7pvrq>gXu-bBcJl^-pL|_d6jM_4D|_I={M*Y;MrW89!$BdU*91ssQy7
zeNVSEHZ{(pw4k_3h-n0+x>>QEkI@eO55v_G8<Uv-#f-5N5ux&0ES0a+VjR5!6R}?<
zd0uab*w(JTIviBM>AD_e<c!Ij&toFBvc>wM=va%)6qC}THn_u3wJ-^@>B-DhaZ{lc
zRh$-P1Erf?Xrr0~W%4Lu40X?-xs?Tmv6fnwk93;X6_o|GP67UF$w<GBmOk=0!)Z*=
zsjAyagH_f>KJRF1O?Q8T!zkl%+J+8kdt({ivLD%?HEVsQ+^5p$RnZ`kHjuYb(4m+`
z;w+#)dV{H?;f^F7NKodh1)ZQ>@=_3evDh}!29FUO;Wvgb(}}=uNKy9CLnY@UJTCb#
zec4?g;fA$^@yt>hxrvf|E5I9SCAmOng!Y<9SOlvelzbHk_%qntzovZtR61*wh9E?O
zSOP@FmLSh=Gm80H+-}FsYBn$$2~F?im?;>eNrBP@m0wT3PC}$dRGnHxwa4eo<d{!@
z(`r@pIHoIJfVE<Jqzx6cvE3bp0Rq*ofgDP##G#d&ViSyi2PtE*1J&tVR`L|EQ<SH%
z5%mLhZe74MZc`(QYRImC$KiR@VLy!oEnY?p_qg1062vX#WRuEbNxoe#>JSEKp))oG
z5M*hLj1EI1e(VMo$iC)SFzE~M7vMZkQXAA@h3*NW@@`ktk~X(cb~iL6n3u4KZAp<P
zSbTB@=L{qgiSo4a+8dOY5wE&Jq&k%CR&MPTmj!MPYBYGt@-EK8r9E0Ewp9hn&m}0B
zN!8$JlkoI~k}>$JA`ka<Y6vaiI(gBr3C*2PI%|Ro7rQUHl{AW%HH_wDWf?80f#O#l
z>R3vHV;=#mDP(<5cSv56vP@L?UkJp`*$O|S_*G#`%k>vPQ%QF}jsa6#A!g}8<mYsS
zU6TdGLNg8wci!<0lNB{WU2xuv&;;480#jcm*FdptCWbB~IZdPm4H`t3W$0W~6@0Nm
zec}`Jbp|ilWI!KI1qauNvc`0&F)Yi;ZsP2g6s7PM1+Axic^gM-niZN2PB$tl?GVA@
z6@x*DtcxvbfCIb^p-v-|mO*`qy0cj2s@yVR5Q+ql*oc$-KqvAiE+Ab^-9m}@(6!G(
zx?1*i@+989BbLUQ6ooP}hw*fc<l*v#q78zHE|4;btR|g?=|OnC_yiPX<P(tt$=e1n
zBRvFZEW~7-DHhn&AES&$n(z90><SBqA5M+;E*%vfDTNjt7V(p~Bu|!$5{g@%B>E0b
zhAqbp&BG!Q!ozL?Fh-2>f;zN8J9@XL75ej1oBf6uGxjuFM}I1X5&E3W$=LXZkmf>Y
zh?1DpZ%zWMW~JCJN#wQ5gi6_CX%JyyoljtiFVbbkX<_iw)MBmb=+fk9NmWK!VRm|A
zGG3s6Rb<c`4`ruMkvx9+I&dmsV9_S(_9?e1oK?~t5>y*Jyoxl1PU@@sMH;RYm#0wE
z0-dnUi!24xuI3sTm0qP(x8chK;<D^8HH(fkFjd#lZD?JF-o#g0s<H{H$W8QkK~%Jr
z(nIi9%iI=nXJviCs&<dpr|=`0jT*9xs$^yRh-)Cw%t{Ymlc$ST%BWS`hu1a5Hz=yg
z%T*>F@p%FnE^d(_2WfM}XTTex3QI0fsmk!Rm51k|241~LK62*?85z(i_*{c!h({vi
zP(!}1E7DRt%Fksv(UZ<9^bPf}fKx?XVJo5N2r9_k0v@Mn?dw`Y$UyFSy7FQohXc?_
zVlnc5poZRz*wK#BsE-cRQXIcmeOrvCKu%zD2e#bO`sIYWM_H>85N7EJ*mqmc4pwcV
zMjDy6nk12jRi~Qznm~Et<ThW`v5smSMAeq2&}r2X$+EQHUP(4;Pm$4CtGFC<Om{!Y
zSOpkL<_HYA@ujK~8J=Y>VS^53bbEsrG<$j4o2PR%Y?4_WR@lli!ctfA3Yb)_weriB
zsb6#R_Y0&c#qEvRKwJFyalWW7sw?ldh_Bw@k@<!rUep#IZ(U^9X?3ex5nYPTWyZ~P
zl!vE)ac4{z)WNL~h*JQ6vIKuCJQ$J=%EuHy<(y?R_I_|-G-i28hy-%L$uX_Gg6pu5
zV1?)edtCTs723u?1@%NXR$bPXXv)(x3>=mpF87R;lGqQFD~Z%hLqrH^cTz#vq;8j)
z7QsqdU<+u`NqZV0Xli^bB;}!w?8Q-&@lYf2!9$?KnN)KpNjn$y9=nz&FK2Te_?b}4
z2uozX;34HCHey@>ke(!HoMuPo9nF_6A1@AGx`9Ai5@JG+ZQ6veiat`OyG7v|acp#o
zYN$Le!3Ny*CbB6C&_-0G9omUg5~-}VtnElC{}_ZI8V4jBDJBkTp#ySojtDKqMtCEE
zk`P2291^%>Sf_xa8qjo^3>mR^+#NG)Lr_IT7{cBh1a&yOK!5OtB&h@v-D2hII6<yH
zmf}JI0ZGIe5_yZF1L#(s&a(NW6+S#fshw$^i=Gf=a!`<{EH)2B^aqhhgWi~;0xp%t
z)FLDn#yo~2v=AIsXc>ZO#xH+^qSlBM<%)`G2`Vn*M^RWIsHo*UJ#jJowS)wr!AO7V
z5~$&z8!VH270}KUqda58N~rc=AY7g@y2|NGG=9?Q9ud2wq`8|^+E81lS$H(z<Q&ce
zPl7Nnh!c(#LoP)q<sK~Ul7IpwaObX|u_Tj{mXZ1^uNb-g%TnXD7H&pI9Q&n%%fyJI
zutL;gcm`$Nzp}jjmn1g`J&wH7*-Z6?8#d2{ir=Z$3yY{uQw|U+u~9K~95g=sD4smX
zA0infs{&?>Qs?0XoE{DncMv;;59sxy<1pfK6Ff6yzaJsuoMg<9ynJ?g9LT8@D@MEq
zt$Tq^EileOf7m4mpN?28%_CLL3KFzSk4x+bvLTft0kH(y*%rC@Nu6jfdEoZ!(<Mh%
z$H-*IC!FXCxD;uJmJCPnaA^LzV@1Tv;`~oAD#YI<3%x|y{SYTuhsIE^DGTusUUUL7
zJQB^6*y%(_0RV=YpsHO|RwX<~BWECtcmW+C80V=a#&*JsoK6<50wf9sPYXK`Sd3o4
z123nD5k2yBDrrK{MN54vfmB@j!V)BW+8m*r6U~UBMS^HY2urn6g{ICo(4=RCKTbO=
zkoM#B1{RWY>$u)YQhKYG(~H1yR4}>`%o-4hHBKho%6<qI7{Mj=Dh@1|;2ynv*ddBY
zKsqXE0UomeA&6@~zlLU9nULrBSp1ZcygXtR*kR%cIPqDAHaBiDaHWh&7(6m@)`-6q
z_kOTo8gfDjhCBh!Qnv*WpOPldUtGOl1(5*KN5uUEw=D=!pk8$ttd?Gp;6N;2gBbMa
zg7Rgyi$hLl05T7?nEQ*wmKt7%_yVp?!{WtG<i;&g1u?<pwdsuyKch>W&dNGD1lA(K
zF}rg(E3>^Wr7gNEmszk7VXrQd1gUBkTOcW_?uXFqN5LdytdX@bT`U)+MQ0-ll1{^?
zYZ?zDnrOFWEq**2vp0(vAmSm2@NqUb6CBWDluQs?3Q&qz{6gy-UuLK=P<71f<|ncc
zM?MNj&9(AxaRas)njpP^|Cb<>DZnc_+t}Ds>SfQ}y<9HmyaLW3CTYzWB;nFx2_j1{
z)QmeH;-lZR3CFLM79VKjm<0u>Y(zl7;6~K}=2Q?$uuQyN2!}}i5~q=ny=v3<S@D$N
zPy8K7^wua_`u$&_`Q;c4xf*S(6$&h3xT@~H{;<9Me2wc&v=MJB<7+80C!HZ6CmyOi
zbgj~N?c4~3Xtj*r7RDB)O4g|qNM|bkwZa1w&pcgPum+Xys>BjQKsU%)oj~e8vm_B$
z0vEO5R+lJQu}z#=EYMu032DD9ak$LX&d(jY@--yG;}mqI<`D^fly$E-pzCfe-hc$t
zE-?)({H4j1$yq$54IY7uNIPM1lpa(`jRX^1IE;|GU03cX7%`MfkL{GTe3mOT;|xSu
zC!vP@P2~%X5{eVx9FEu3w$etH?fq3H+MPhV7@<3hGi|2eC2+C|h-^_hCOOL&fkBC+
zZJY!M`@y#c<qT^>NEUxD)(V_#w@?H`3Lt$w^;l3(n2lfphDY<1fZwE(Ad)a7!@1OX
zl=TLv_I;u1nBC#=z6yB~#V?$&T|6a;%%j>tC8tbS6W8k4%NQx*{Xi44Y#9j1R8ylf
zpvCwK(2fx$0|#*8q*6-AV)(Vt*p(M>zinsZcolk<08EtA#>l{9L4&|qE;4WcKLO9r
zGx2tG=f-f};;>@GK$0BN$@&Py_RattQ7ANVXKE`J-QIqYj=(D1hzCHf8z-9GTWuUk
znmHRUf{PT%7%Pq#xDH69>DUFA+3#JVxp6`(kBBW9$8r}jxB#+|6D@}D?${fG_^t^$
zzS)7o;K2QM-LOB!jt+K4r684;m)V2{D_}-CQLin-id|^(Xi&>!W*PGsQ`d>caILIY
zv*B&8P#rei$>`g_+?7ojn~HR;q~Q9xWy<SNV>I-tNOveE>tQ|jGHuM07phZvS}m=T
zJg~AD!T_E@Vb)q5)Yt^!yuoQQ$l%c(bmW#|=OQ~!+QN)-Nt_qiRLYfM9vZx+J!qF4
zgAb9_mbE~aq>lEzm@Bzeh7Lz-)sl(qQ*{O{^WCJ`?+&sx@(R{>`$2|vcM#fa3f;=-
zPqeDZsro@Chny%k;E#C(^4;5Yq4DA~P3b|B#k}HPK;xz`DuTm#gJOhDAV>4@@75;l
z&?D3AS-0foiO$B_ku9oD%UI^A&SXFybm+0ycbGsM*{kj%6Loj#HFKIGur!3IK%TMa
zx+Sc&DNtL0ja%qzEZ%;%w!FRy%rwRwYZ0r0J5{<oU5SEGQH@MEh04iPB8zHN+SU=g
zPECRCp*wp}RZNa~qaL&y1aRzYAzr?T`l`TIsr=56UmReMrAxli(v*#VLi{PJU6fIU
zj=Bb_bCb+XBXyt&?S`Nhapm3RklC1EK_we!xjN=}Vbn}Nr&%xJCg0n0eN{)+{N@7D
z#E>v$a+bZhQJd<=T{tb9J7>WHIg_*MsQPfisJ8Ht5l?vA%dS<6Z$G1c?D0L(j=P>&
zxAch@7hM1I!TwSGCa6btyxp<%t!Fx-K3}U!u014Nx#FBVUw`L{j+^`R@4Mu_L&C?F
z&s8gTU*>f#sP2Ew^=I{4bMN!@tAC&K{^zHg`rGUK_N{B$n>xswr>=eG@xB{={_9}$
znQh^Jb?w!^yJ>oP=S^eF$JV!{4m#`7)X-&0-SuLzync0K^6^`*)Vsg_Ow*;Kw=S4F
zdg~8G-!&g?{oU<-);@LnH`X5Z;pk@;ui3Zd-Vblv_riyF>^mI4Q{H{|iskpb`^x%z
z-rcqozrU~ieBQAue{<DaD@R}TEBwraN59{+^3e;kJWVS<Z#(H0ukH9XOShc%VB(cg
zqaOW!_Lo0xJNg%^Ke}Mi>W>b*X+hg5i|+X1$oIB>G3C7%zo`4=g0>6qxb?WhAHMC<
z^LP&Y#V`No<jJ?A)2F+pul;n_;lI4?xD$7O<COHJQ?{OzKV|DVqVK3rw%&F7=(Xz}
z9KEmM!_m)mPx!AFSN!dcwcdwoesbpxA8kG1{P!*!bN9RZ*5C54eTg-nZ&|<c^W%=V
zdF_=?tz0{Q(7W%RvwroX-#=#6ZKq`KNAJ5oZ$04_zwPM9mi}zwgnM5}Oj!N>Nl#w4
z{CM;|Z_$b`2K}<E?VG>c_K#!Ue&tj1uWipp|J!HpxodxQ<&h8nbk+|ZzU|CoesT6Y
z=N);MQfpt^*!<`f3lBf`*75oDLB*#NM_;6s`u#>ZTXgT}XEsJ(e=2p!=%+T$JLu`z
zpB;MZmffR!9vXXC&$ri%ekOJI;9HCLOn7F@Bj3B}uWP>Z^dIjo&d%Pv>A0p3tB=lp
zJaX~!#)j`?SC)ONseAUfvdfFJo4T8x&EB&3pfLmY95k`<{VSV>R6TZLu(a}P2j1ED
z<X;^2Y}29zyE1<$`|*%BsxCVJ<m*>`?f!!=nqG0!cWQ?I{K_A6|7`Dgex9c&dJUPT
z)E^JNXzbKc+2XvT+h?SYcxHWK!0%@zNB6vVL!V~~w^lx55`CZ2122E#v^AI9`uopD
zOg=R?y61>_)yHK&PTaWs?%HnCIrOJ1I@ecc?|wR;zWXnin$C?!Hx1l;P|IT%wKlD~
zt1WBqt8O~*uD+9gaqrL4H?MxhbT2;Ws5jM-vnEwNc3^$Ss*}-sQ0+C%({Jv-IeqnY
z8)w~h-DOSk$<Q%_n`@SBJ+-xJ>v>0NZ&m%+^3~D-43{%cst+%DN1XSap~=lxR_Uh2
zckYU^4Lfr610OzhT<t?Of3F)?aZ=sj-~_*6-LPx#YreI8>A|O8?R(+X-mi3fN1yA)
zUT?EwRW_{f8d6o>>|YIEcE-lxsWa-Yi*n1m2IuT#KfmtpDyixhr4nj!(~aKsxsA=;
zQ!DxTuDfcY=%(U!bE3K^!_^>-Iw+gP_;y<(TJ;m%ZoGpRJ7trOyj@-Tog0ExT!(kv
z#)chH+Fx{Pt-q+ICDFg(`CxGH^=k|5m43?e@#}8aHM(7S*>-OM7bOG>#<E?BZmOR*
zqh^uqv*;du+ICw*UpL68v5bXhSl*pRO&w}b%D<;@2Cp-6(`#zf06L|z^&J_{%+2KM
zqE>z%Li0nO3<)az{M7YIbv#3tHP?87Qrpu$zsu&CrXV?ebCNELE^it0fE2^fW}8&Y
z7+03l9p(wVIP&TXK_9+U4t;SK*?XA97@lIbK8yKq7yTggXglYRcQPs7h<i8Tb)_HD
z^C<e^XghYAZ=mPW9p~usx6^$x;sl$cux>Ns7vXVtSI;xHdM@~Ko}!$2n!iRoR3QwA
zSB2uYn^efIK(})9)XZ`iBp%D3#>USStZXkU=PnRFZ#Wa>+}h1Hwu2XW#MV4%o^Bne
z*F|q|Mgcj;fL_+!sl=G*Y=hnxDQ)5Rkjb*e-MK^z=q&d<%{~Imw;h;yWva9VVT7|7
z1yPZCN0(AYhYd*5)<D-cMzvz+2`G`bvUir|MI?Jnz6l_iD$&o&E7{$by$t!Xmtm(u
znYp+Hnv&?NI-Ty{Va98aj{0u7o5!vvK}^P3720ABw*xuz^ysW!*O&IR?wvUDwwIEg
z!HcV5UQnCNav~#dx`*d{-C&g-PKj3-GvwAt>1r;#xO${YR2#-;lU0R!3TQyCt`K?y
zZ>WySIsTlpH%k@>RLhyCM{ug^l9@+7f4Bc5r+nh=8NPM*u1`MgdF1m8uYKf{_bdN3
z`i|W_51rn#W?RnzkG%VS``*!8_w2oW+x$n~>N(-oy`NqE@^7~8`S8(G=0EiIPs;At
zb=$gE)_%VC%}2LQ_~h-Q8}8U~+Y_&>-MaU~M=zN0he?-sue`H$`g3bvnLnK0w!32+
zzg_p<w)|O-K6}-uJFXmh+qR#0TaVv2cklbJ%wK!kmHlseWnbmiKkS=3|Dh}Auid(<
zzfN5CkW@Q4L$vm9v?I@Kzc{!|-9P+&RTws-z_h19*H2UT4D;2}VXAQRL_2+K^*Fn-
z`boR8%IX`;Mtx($P8D50&@SnB+Bw$rNwoiVu!;V725-Hd*8NmN%`fg$<`>5fHPM(W
z(m|z(uD;I8x9a+Q;7_Qj?*BibSDDK<RfhR$UO^u>;D5pnKe%Xdef5u4-I`R<fq7Li
z;MY^HubFb%uj<<*e*-Z@-{qePRwBfxpNVZ}8mV+Kn7I1k&`<@Ww#nllUh%~^lR6q>
zjN4uoPnnn!n`KyDiNFN9{VRSNycAlfnmJY{7eB}ulZ@O&>{HL6vLbMH&N6Rgon@j*
zwXi(0r0&<+H?n<a1E*ht32l_%69yL{8fj(C2~7P9x<v`i^J#wcR|Tf*MkUOh1UG8?
zb?a5RXqhqaELVA7^J8r5l+78wm{2Y~i}<k}rA1v!RxxXIS({Z>TO82Z4eOz1gs{+I
zD(s?D9511b+M;aC7eku}@JOi&WQNV8Qm2@58eDR~z=WJCF-&clw6-{!gf&ccIZ0T@
z;&lcAc=5mqJL}`0XB)M})CABh$zukN#M6F>Cc@VddJ>g@7X7lRyzFOe1g~@X>1*gJ
z7=oWxT?varVkZdiu?x7!kv>>N<?959U_h6(VnrOwkX482a#`W~iDt$H<Gal<6Z1C1
zw_KRLG&eF@<@={Hw&<wC7<nNRiI?(tlA<&2h8)^Zni7*HXFE8}VDdODPfq*97>H20
zU?nQUh6GRmbzO<s?wzBQuFz~!2Y3<(UmKI7hz0URM6m`=SGm|TT85<rFP@F);i-mp
z)-Z;AqQ}%hpgc<;S070M`G64^rA#cDjG9V)tO!tmh_q-#4FPpv>#T9xTLJY3@z6ch
zVKmFBbtta6Dn{4?oi?o2R9<U!r)oi!YdykoaKTdkniyGmAp+)ZMZ^L|@+=c7OHU3S
zbhuI%GI@jcMGtoCvFh~QzJ&E>p}v)>3UHN-Sn|b;WdUi0B1z8sM#%zK(Zpm`2n{?>
zoCe)}TAajenB6F!feVmQ)Ple#xq~}sF>r}P&We0*r6MHHB5D`IS23(S2ektzx=}oA
zV8K<2WuHh^bso9?l%{^w2MmCDRheP^RZcp!5|x!li50Z+@{Zrss|1Z6A9g|v+8nMX
zk#dzaFp_ybK>`oSbXy@m>P3W7s5&p+uuBHiVjI=0ApOm95Gi1U<c}mv23RQ)T`kEp
zqAsLiBFjL42h(_6fn-Elm6<rp99IpvyopPaIv?RgqndrGluls+c*Vmg2pv-Ylv=6-
zt7^0*yR?ddmsLcM8cwQDeKa>J@~5D38Rcp5kv#tE5->RyBOqJBfdxT%n`{uIJ{L|T
zwlGr&iCpr8B;ij24;B9kWv$p4L6+?dst}{M0F@M%uV@gK_uvF@jZG|1<xz)x07WGh
z&~QqcRA^PA)~K+PGLx%8=%)C=F4fiQGEV~7F43~FMY>9AzDpf*0pE6M)FV!Na~M?y
zu|yQD^aDcSb+=g9##6y$K_fLetFZ>DN+WJiQ-`TVPT+ekQDs73CqILvJSLm`PN3Yo
zWtB39qCUVUKT<?M*Mz64io$ew7*6R0l5EhsyRv@s6A{9M9Ff_6mgC~}e8<N3QSB`?
z)hd~)H?C9lf<jGWHiw+R=8f!cSW>F=uvX<|lsZsnQOhd8^SH3cO39m2cM{T##Pz3A
zC9UzcE4w}5D5oSvOC9hnbwzc_?%0rZe9vV&>G^yepm`m?uU3gD_=2FiT^$gxKa=7#
z3gwlY?24LS(52#&?7A@DRcFZ*og}<6=%)gXrAJAr_v&g_%DwNn$OCSAi{^3)=o`1L
z!$sv+b+(xXGMxONa@a6vR}C)iE_t=VU0?wTrM=Op#&U?x@Y{v?3i9~1PYF(9gQR<l
zd16bG(pr^?P$g%cD32YwJM=`Z;qb6Vn@*(*eE3GmSY@s9^QRu9biJ<ON<c4RQJs6Z
zjrXSfgz#UN%a~PPnO9w9)y2a}sdPuGBd@%{T`!Q$iX%)~G&UTiR9;F|d8#^J#YS#@
zLl>{)3c{lr0$b1xN`fn^6Eu+^qsskgasdLmotWT<z)V!m1YGj7GrK%kSHs1}%4CR2
z)wGXXW^HK`nlD6}TMR28jh<93lg_)`^)d6>)fmN$Mh&U8UCIo!D!ndDMb=NN%9L%?
zYL=?#3^Xee8k*<MkPN*@vdLFkU9BrD36$I;@uF{+f*cbhB^IKAAj5_Y#H-f8LGmG~
zNOfZKZ=Fda&?Ha$3ZTsfR4yX~<ZEHVC@KL@1|5NbfF?%rE@uR%*|cy;l5w#kfrjeH
zq8I%L4Y@|VXlp{ZG-<w0@jx|?1M7kkMLKEWi$U^JQ<h?Ap19Az7d+jGZ4}^)I0wY(
zx=mYj@`zp=-xIRLu9@US+BxIjV4HJ@c!UO>+#WyQn&P(nA{8-9adEiC5APHv4U@#h
zrJcePh!g_{d#t{)&J{C2BOE*~9x5JHPx3Z)OD6IdF}ppe+A5&lB9H($tfvcFyNt#|
zfJo_yT{E>JRAdB35KXU_RvOgBCmvSOyTzcHa;Tiei^%CO^09};vZ4X9j7CZ*jUWaQ
z4^-(COdhVHOHN67LpyQxarcujIT=C9Do<;tfFdSA0Yn<GSgX9#z@#dT5kElhPoDJ5
z;to;-3as^TMV_`Cic+5N8QfR^nP4c8xRI3-8Hk657FJq8-QglA1=Kb;O<rRrT_hX=
zRnl8h|Ew#zfY1f}n_&T5O05>umx>BjVPJQ0Q0N{*!*wT0X|lu2Fe*FAbi^V)1{s2g
zJEUO>8G$}R1nY&oq??h_GAXt~>>^FZm!yVrPUqfXLM(v{lK@rN*~WU<F^zbM+e&|F
zA!;7cg$`5fcANkoPoup9(Suk7s<GiQpcYGOoIIt}gNT0O(n?ogOFJzEwHjZ;BmNpX
z5Qw3oPB9TH5Lu=__*e|(X$-(<aK~(7wpt@(>8y>jW%o&Zc)8+$)Vm0zCaEGM?K`(0
z23?Y0F|e;;yNuxIXd!FC-TAS<ZWgS>m=N57K{GFolOPT>rY>bHU5ufFFD1o!Ba{~I
zP@*9aGL5(s$~Ra97K09>H<T~|7CG8s<c-$!V-A?(h;2zLvE~IgVj#!#7O%wNAnX)I
z0qQuWJT=lkNfesLA<{PF`dK4{-kv)4b`<SQF*x!Krv>wk6N$k1AD07^lSq`+*eq-0
zyu*JdO7TF?#(f`bF&MGLXy-kjsO>_lfanb=>UHbDDnO)f5JXx2lwKrgrJ!!u76$2#
z$uHmd*a*>Kss&6mfTBUzoE5i#N0i#NDI9c)R)}CJiCH8|7zdPL03uG&66p1bN`0tO
zMwFMA;x3*%Zs7?jS{tWI+C~Yav~^Yj=>1tL<sdrQn1>OhNL+Cx2+|Po-aB19Q3bXC
z54bZ=LNoCx@LmQ&l~h(g&EVM!5}Ve_(?T#}#GtW;E3KNXa}$=q#-Yy8Qc>_Kh%5ZE
zZi~~<iTT*R!Em76AzF#w7$Impwd<0F=D?6dbd|K1s%cCY(|(CM%oa-os}*6&{*Sjf
zyGk@;1(D1xfsF@Ra>Kn#4RwQfASJFdy^LC@uHGL0h@g_5oY)4#@$;sy+;!1pOH3p!
zwNy1_VHTg53U`d`cM3s67BG@zDu<fvas|2;vIAR)Enh56ODCVTQdTm^0S=ES1$xtG
z#Ss+6bPdNLl0nw}V<dV*t6AFlia~Je9AbJrz49CphsNKQh{h@8e7-b-g8C|1WK@W+
zr&UU9Eqy?4x1b1%A5W%C#EgCvB&fIy4+~MuEJ8}E<LU)E1ugiOv2jan7-&Z}c(~r5
zpz%;)kr8p$W<MCgJc)+e-m8SkgE`yF;k<2pvH->ciS>l$(_{Q66vS!8NU(q>%UHq6
zrNMFjN)k{pD+#g0rX^A^A7nq+UQBaBkvI%ID5AmH6B3nV&mxxC9$y0NW}tGWY0uM=
zPr_q({tvi;&-M~y#2rgU2LU677K8kvJ9mI3y>%}bW=UBa`*<a_se$_eQ3+QJ8j_B+
zH2Zy#WqTb-Evh=u%pptU`mSCKZ=oWPMp^QAei{-WW{I~TZU+byUCA8E&tamRuv+IY
zql|zNLla(j0OL$I6NWSCTqQ&I^2BnOOOemh-*djbdiUzw8%_%%{kU&HT;$^FO|PSg
zQK3Z(I-gh#(Gwn*-zBx#Zla5^q9K$R+&aOb6q3=BT$PXAVhSHG?*t8Er|*O!SKJ8`
zCkUN0I04=ZNIP+{yN^qd;T+a^OWYDNj$cGD-(?Eu@&m80fCiVOIM#%OQ>BIu!tB7u
zLzm`XE+2pLsIZ`lj$;>B45hibbI4>-X@`288jM*3*#a|;D29$>7Ss?0z+mZYlI$`=
zXeu77U6R1}hXE4^jL2baEeUWbWp^T$W}#?20pEzh(+k2GmtZMEq-aPMx|>jd2wo~?
zS7tcfm>{<1k+vju3A)5#dtHgR?s>7>MTHS>4ezgm61NU@DU5}|3hvH4^*dUUT*k*_
zzNK;GBhK{zm2AH>8F#l@q<L`x$-B-sY4%+P5GUzk)6KPL;WmCH8%#-F{!TVoU;E9T
z^^1i9ObE-v(7`XoHE2KUgBPfq?Ey)B9aqlJ8glI3PWs&rs|@W<Cv^Rt<uGc^?bMW%
zMowUfE}jFpgw*+D8Qh~(C9@pM7b5MFC|IMz(9S4rSyR)O=K_!6yelDP$6RS7znVgP
zl$>rS9jdQ!1tE)e0&8T3NL5*Xc~_<QON;Yc!m!?g@UJb8YeH^5P^h&|zxd44iq{Ac
z&Eg%S)owi=Sloz<Qk}*tBMS}ns0>luV{F=Urlx|CrTsc)nJIK<1>c~IA%+e$T&sjp
zVM7IZ%bZJB`=-di<>S`Ek@gLt22EGW*eo=kUW98%EJ3wTL=12(NmE~LNh^OHhC}V_
zhF#B6LoHB)yOKtEs#VG{x>JSqI;lNHza(3=QW-Yt1nx-5Tho+P>g&j4|610gY9nvz
zi6gX4yktOjbD8eY_<Bw3=_!;hgPD8_qn7G|bOwsoI*EcTJVW+iNRXmvZK{&bf~wKD
zS?NN@NIy&lW6(+b<;+dP^Af*6-run9+5_s3yrlAmxtIREm>Y0F@x?c;G4of}who$}
z+wsC1f79#UD62bTR1h39x^Bm7Z?v3t-dhX8lSlQNI_;rg-dlGqXj#6!Y;t&2RpyL7
z{aW|jrT0YJJzL+ue^~k7RU?~r_nEWmhrYe->wPN1>#F9|?~X1x?5)J>SGV_59ew-E
zY<fx$zx1+fMe}>SFuks9_V`(|#x!0U-ZS}$^7UN@R5Yd9W{JKVW-B%0`X|cGxVF^G
zAI<Ia@;^Qpy-9!Xn<jnP7aJb`<i-tOd~(l*EyFsCTZXM1d)oyEjotdr(L1(0H*v@2
zcaA#y{O5jl_WAEU-umfH*Cs!`=?{}vebVP!t9p)U{nvdXlmEJJXj}bz{VuKl=TV7c
z-tl;j_}8%~^?CQ$*~iR@J{>$Kx@_dl51cn@#RKP!pRxK+!}6>Dba3*ReTrw=oIk#G
z9?wM`Gav1H%ba7s*0b#LIX%lRo-g{gRV#Jws(pveSherC&Hwn|fR{h|udn|leZ}{R
zbHDe)4e$N0-?{daF+0$A$Cft==sF<1^|_;W>^VQ$@#&o5XD9#Je)a|Lt)2Jjjb-zG
zpFX;3`F!-f<=EDL-CNPR;<vSX>;GA?r~bm@6UY3x&&c$LN4)#!Iep%}@1$eTSC^5$
zpN@Rw{^_Hhf8e*{@~by|edg+C2P7~0I6M5Zp4^<r-<m$^fwwNYan7;cBXd4Du%|Fz
z_bi*=Bxi^Iv6uzM3iMsQ_LzmanGa40W-i<?<jn-Xa6C8@T|746r!Y3mJ$RU%d*3xH
zr`>q>j=r^>tydS5t=%WonbUtWJ~!>^>L_>hAL?p;eQnF+pN}zT|6J*pUpzMds}K60
zzx=z$HGTU1zGIr+IDE#eH_BQDJ#a)&f2f!2+Bt4!_iwAJzy8$O^T$0s<&xU)m>FfM
zhVgf9zqGNib5_M+57bON?1D+_tGA8si2k>6`Kr^0KJv#w{W3!?xtwctCX3$cUbb$h
z-*-=E{@}7OH&bt_n_1QRi|J!p+qd&N@A+gV_kNT+_1uT*%!q4O4!S9^{c8_Z<d=MK
zbpC}G%FLi39i3iLJ*MfrBNF;LCX3gM@z1`&PcA+Ty=GOR_t8zif2sexs?^~#`h<s>
zL5Ch&5kAnTBGr2O#MJ%GqrSd=$eH6dR;^fmc(n4)%hdQg-$L)#X34pse%I402WQuJ
z)W2FCPUBjl8SK~pNInHu$twHTz~4T!x@G%WQ?uDc7tPSaf9l_<>eOp|8*9HkHxVwY
zv|TgWZE?o0X5@c;gc`Ixvs9-t+taD)g!$<aiMnMsW}?@EscIwpIp=8IRXHFGe{*0q
z9Kmm4sz-{c?!j8k?)1aMy7JxL@PQj=MNcGbctT=hRX$ZSasp%j(jgne1$9L=usA&t
z&WNU>pGG(3&SMpZ24;KTvDs<uIbJr@aT=%H->G(oT{*)OSUbbB8%;w#b#<Q^vktA;
zu0wX+y5{=fbrTb&k2jUW4VfCP`IH@r&2&}2sX@22W+j@aqc2r-$KiCHx2amaSPwX1
zWT;NysEN_tQC>&EQuLC0r3MzCiUw|+E^6iIta4M=EA``_)8EMiD&j&K&$gNx(?Gw@
zz*2i;3q2wIzovI%Uz$E#`O6f$9$GP5H+n4nVx#gpzRt!*!1;j!Jj3ZpHKVI#{8|~Q
z)N&Pd(09AZLy~xrrP!OWgN=FuS?#MBx{<^70!uebJesQ~9$yNDft3l8jDq;NL0Mzx
z<jfONgeGn&|JESJ>CY9Yqo){i8o>p0{4}J|jqcjb&?NlbI67lL$0IbnJ&lznKg7-3
z0M2H$$k{CLc%G7U{+uZ)*=of1z`Ovr(QcZdLiYCzM5X1-6Tm=aQ^*m}{L!1ar(is#
zjhoAvsm8M!Z_V)v;_x%@<Pif+(jxiIL_4b@_%&;>G!;Tas#WdE$3{*)Gio;`Mh)?B
zBom+}d?RCI)73$$dppdky&jk76~yG&lrvBN7lNp^#dLRjh&0Zx<}^QfY5}SIm~Gu+
zNOy%%ekq@w-AT0>p_O{dtEx|+3KQE&38D|>ckM!7J@4Df`^d#+F0N%N>z!m;78lg{
zA3WEC5O?Nj#Wec*hd%EazGX-M7r+0A_sXG<?mqwTC(pm+)1O@X_p?6evvK~mf6v+a
z-u(GnMjY_hwhtCOebu9%zxm>Y6OP(4;)Gk<KDc({oPB#*Z<}-c`&)ifwyo{aCnin!
z{EL~lT{-mqE&puz{QQTWxbXNd_RhTH!l5h9TU++&u7}RK@c5_ZpL^R6`rmlL+5w->
zdo+LHinp#B&K*)OUbwbwYvbn^&-v`B`ESnQ_pC1Xpz`fe`+n53deZ#Nk5%J_MVm?I
z^H$CfRUBxCv64tp{llcUbYVqNjW)RfqfGr7{m!i4uCkMtE^XP|@S&NegO;$iuQJ0&
z_#3Au{j3h6Su401edJ>%T<~i%%XX^V$UudywZr|Tb*)@vy|jMh!rJO&9do6@tu;20
zA2g4-;bFX`S)u&)>k~7ymoyx;m>d?>MDFWczx*3xR{V@vYnU}lyTSpSp&V$*+!FYr
zFO}s#%G|jiQXu;cWd-d8+l#P`;n5IE;K&%d<o-{oG0__Qo$$CuLN%=4zGU^)iTz9A
zorR|jI(1sKGRx$QiLNXZ@zR_O6a~YH4PyFL%BVZRIMAX3TT~%^Rj{0%ii7v(xz<Ws
z;+mm^lGmGwOiE>}M2`BYeAdU4W1`x4MNZs@DZ}?L_FH6uWiHBh0K^b>nQr>0a`Yue
z3t2s3<-JEi7Z{DS)_Izb?j&YU@`PDElG^De{3I*7s%lZ!lW$ez*ns7%6Xi`05kaO1
zbf8Itr+Tv@=tM}^NIWW)4D~u<iUvg0hiYYE5B;3)<w4Mb<%;3OdZ7A5nZOXKIUJGm
zG)3E@$~6Ie$+t6J74{DFVH~2JN4DCkw6!V^XQij$ODdbD=J-KgSreS9M3;3a$=0g@
z53Je<ZZ<&XZLc8+%5m&9SxN*2>8a3GS;&TT`S4iPm5+Q=>46&5<#Pj+C<P`w_skgI
zXfRdau?<S&tvzK?)Tl%nB3*ygp+*#UU_G(OyT)3M9R<pc!Kq1vklCP80dYhF92Ykh
z1s<Q;$&dvPhDepT_-voI0#?okNd-(8i%pmY>F*WE1?Qc-I(H_Pw?L5?p*Vv&1cN$E
z@)fbh)>jl*=9DXv->rqMg}N5@LrWWwh(Kz&Pli|(CRnjZFl!J={YV&-H(*Nh7jGhH
z?W+pBp@p_v<42FJP2d#+8(1}n6{TeEf_72eg;c&Ftnz)vU>SS00<6-OMU6#^oCs4o
z1I{SPfsCROWl@5DI8gfVq>m5h5U_?9wVo~?&LCPY+wB}KB5(<4F{qCb8XHP4&U4rL
z$oYgatUx`45Io9b83`d}C{W?+qDBFCR^<0}P&%C4s_t04<j8h1p)v3@Kb0;=j)*$&
znngw3;EM{O<|XCLHViUkspb!+RFM)icn-F<6H9BWvRLRrrZ8@Xwj4nM)=>MGb>iEs
zLCH13YjX{PyU8JmkCh&ZXzqpyG=mmL9str~eL3X3R0Y?lfP*cO4qB(+!9cG9#PaKF
z!dM{&6_P6kd@zINEbrMZjVMf-mg*)_<EgP$Rip^ci0uMuwH<bx2206eTG1KU6he^O
zEW|t?@laaii0}51X~s2?iw{kYGK*3MCf^cRN?Xo6?Y<I<<UyFw#4T-52npqN!lVM1
zJIZLLjG<*))<Sh0%8$JytR<6?8A_GoGjp^7_!x`uc|jG8Da}lWV<JYW^@hBoJpmp(
zp@Jr|poE-=DS!&W)Twq5<1G?*r((V|NoC+64y{{kl)h8t@sa*9P_}?5CNxOtR973x
z0Fh~{cnnCA2MBl;loSV--$nq8k!%G5V_aqLjG{4Gc;#vig35WEyiDLkZF)N=+u+m^
z?(P4Q1gfA6oQ_ZvWjXD8JNfC(m4)SeKjlXq7C`|mPz{sH1FILLD14OCDj%rnR(s6!
zQbCKA%r!y55~-;|pr$zGCyqF9NFHvG%!W`<ejYK^p7Cfkp``}qReP9KR~PQyL<TrD
zL!))lyV+QEA~8p#RF~=<IBHOr5m7%x2T>>I79h4LFJD36!iXTv8QG@;qO<Z%cqiEy
zp(y=!86U58)s`7P3sZb#)(;+)YM{_T+{G@&WvJ0bnQ!tVWPFhtkk6XZ%c%sq1%<j?
zlq6}?3S40{L|z-flaKVn$!fA{IP{#dc9@)L`g}JorN;~t8qJaWmAa=yUG)&XG$tMO
ztj@u>tQu!1EE`qn#*M1d+9M@gmr>LtT5_QKH5(meLjQ0^8p)&Z@PMBNOsZ5Xjhaf%
zZ@~HU4zq?@at&Lprsi(##Mcu}W%I_CUoU;IXQ-`8tB&dq)kMbTWM+u1(d5kxhEC|Z
zodaNX!El98ttuNkD4kq+x@rK2&RVL}dcy^{i!$9=Ysp?S*=ie^1^!eTzm^ZWIdDor
zsJqnjBk2V@=q&P?(8?YZaaC#RiSm|2HR<nkEBZ$5b@2UyLVYcUI!%RBlN4^H&U>EF
z-5HaQ4yINH<arDYq=HfoO4rA^rck;-GC(`Sb@!TKQVK=sZn4<NRyAqOum&jsj|dQm
zc#I&YatEP}mk87(EhIdx5j!acAiaJZMCB2wHLeCB`96jf3@|*%*CYpWXqJZB63P;@
z@_QwhYt2GZYD5Vr5u=R7UyHU#Z&&1>2p%Cy0)|KPIPjcFC-D`Ua7*a;2u5Ior(Ip%
zuUde=ap6>a&y%Yw^>jJ}i#_P+*<2(6uHB+Ohak!#%lP4#7z3kN2T6?pB9(72gdiD>
zV%kv&3@MV)3b4+U&cPwvi77pnV>D9HRj@P`tZFjWIJ)CBG!s4<Aw0QI?^qC9v=XG8
zhdh?CR7(uJL^bH?5-lZe$X+~PYL@P=0Oq;8Y%waT<~vk3diw-%e9}GAo+U`s0!n|t
zwyq>Y`#vu*I(;EtKSQZ*$i$-QQ79@zR><5}i+2njGXXFidQy3ayNt;?Dry(KRwf}y
zmoyoo(b}az^o9wpfbPMhl?Nrr84--Yye=2-5Dfv0I<FG9#Y;vR2OQd#*np@T@y_Ad
zyhs3u+?};WV<RHz4LDg&+?Eu`0EeDBD<eEYBIizcGLTplW5VaM(8t5tKn3&%fNu~V
z>&+l;MP(_I8Y3#z1vSc8!-u!p5Sf1FM{#4KmmmfQ8c86=ozroMI6Y;JbGU?pIpsy`
z{f!ZxI9a|@7CLn#2B$8lv^8cWhM&*w^>B8J5i775PGD@iOa+ZQ4xvdVSWM!ff9(=N
z(UfYlI7nH>*~D)oZ(Tw-HYlP3mM3u?D6yEj1{a+cw=rT0I9|E|jxrHX3^v9*v~zNu
zYSYCJjCeX-MB+}0p|lvK)N5R!k@I6`uSPHN0otXgu?cL&oe{Pe0#F;jW)$(x!x|8|
z54Qwmk~kh8tKevY(UdJqN5Oid*A91v9O`re0%e2{hX9GIZ*K@y%23bsWX{u;;&mZ<
z=W%X2N6$|AScE9PH^ZSkbe16oWvHeaTfjK86em88WLy?m(jjie7!!j`BcMn^+;MTJ
zc(De|$NqBO;m0##ocIi%MQDvvwCv*1PM(wLs1kz%VeqZN6oSE7N_wn;@KIGQer}?#
zOZvj+K?Cr0cIaoF%OE56qKd&Lj9LapEe@$J5`{LUBC$AyjWu*RY5WS9-iTd|iuEnx
z50mTXYfCDy{B@xuixP1X79t-^$X3C}<jIN|gG;%_+x0C@S*BbLoC1=U$DUMTj%%+=
zM`;*!9>|b#mXz`DWT2rbWvXN*{kFvJIt~NsfF>Hr2bF+}N@j0>h%dRpWYSfF09726
z1nZKsmn=?OqLCmc#FB5iMDtnRO3q1e20e|{3tmYEaW|tt+5Rv&I1HYFXyw4eG+)&)
z3JeJ;`Il4^PB~H_oFzjLDu_L*gv1HmACXWcuO;Q$1u<Z~>5nXE)=00`3+N%eiY1Ih
zYCTabhA(q3&PWr-m3F?8BQZD(Ud=!C#fq}B%yxphN=$gdZzOr3d{JOseAYk^ihyxE
z4i!U}<{JoeJ-m&5jLNjQT%y@K$covUVf*tJ1q6&p*Z5l;f;5*h3|B@-0;q*78PchB
zt{vpNUC=l$AO9G-jnp(xS)|6B0|+Z>;pYMFu9DCh$*92M7BI?|q%eLU0aC1wp?uuL
z5rXt%L~g{#b&1Yq0_cn6B0}|7YY8;fPNrIHrWlMT2FyWH$5H6mX|%{ya(Y)JVVU-l
z5<$#?KjK}>a1=7s7hZ^80aCOd+*Kl?X|Dw5BhmEsnUb>Dxu2zk7<Y!`-?zHJ+7gi@
zy;pj*BRf~x3B^DU+Jn$cFNqrBw2KLW(&ABsCnnU(V9_g5yp-ec4M@r*UP6--!lXe3
zG`NIGD5J%_KmB#_(u6KoyaD4(Wd)7#-qs@3E6O=qse56XlY`GC%aE@EM0;~7>x?CS
z6Gz297OZk4y95T?E8))8I9wYL_0v*F_l=D8WDabg32=#5tf-uMlAcnFrhz2REwKp8
zKM@Paiyq=PdDrIBS_HEs6O#}Q8ZaGMT-GvC!8YRP7DHKQI>S{Y=N-%G^$dz}0MWtG
z#A<K{!>tQgfZ#jqtA-XwDe6GJj_s8v^!>9v@VGm5tylN@1?c^yNIuh|YB^xgZFY!j
zr7_Ewj4==6bZ_#ttFQV}Cr$W7cdye~jv03)9jD+jo-1Vpm27ulw9HP5PM#aLgvE1S
zz8pYtWdb)-azB=WKwXMmcmau0`auUtL|MV$Df#2pLJ_E9LE=_5;&78DOIYwO9s%o2
z!ct?jLKEclW-@u?;!4N1QP;;T#1pr`l1N0jnTJnU0ntOW&tumbc%dU7S+Q`DFD@Oz
zVX%1wv|MIST-S+1e%mf1YatE=DgQ9p=1yBLnrmFaN`aF!U1v?KTu_7;+`as~*eifV
zoPgl~4{0qTn-@ubSFMEd)lPzo63l4{gJkxgacaC|hE{H!S_n2!RVIsZO_SiJT2mQ(
zFsv{;RVMXCH8<#DE5q;^8uL*6{Q4F*jnzfh6EH<obu(D@aBXUN=#^2nWkH5pnlw7d
zJhLopx0!BoFK1EL=lWn`s57dn&d((z|J1OmOwQG7(VE3nvxS>KuX}8qd^=P6vWy|0
zwF+jVX=F&a&o&0SN?wkC2gL9qpx~*Iq8|MubEhuu>wv|wQZ(v$f>aSVRmK#_p1Qyc
zreo2F%CZ0ITZS19FZsdsbnVT;2b1m4hA?SUuZxtO7Rfh;iGV#+r-L<cNw%8=c2(37
z7RcAyVp-6kOtuyw)P+!I@VvFCkfhcxM4W4&#&s*?HFVzRZt#@T+%leUKf7O77N{Zx
zBxxXL{F-J79|lyQh{~gKEVC<E7ReFoDT=}{Tmr`3Ea+9Qih<}u=_mPdLggE_vR(gY
zoeUA+OQg&<T-h2G)bC#Z3wMvxU&l$fD0R>JV#oCzb!AP}ZF*eGW$Ep@xol_4qy>xn
z4H>KT`D6CJw!Lh3@#&8Gfuqvn6SHP~xMI5h@vlus*CGAJJ?1wy^}L?b@2{WU&~!ro
z!PNt*$L-x&tyitzG;GPA`yafw&ycD%vuDhiJCkF&i~aj-I;r~L`W;QtUb81%eDdn5
z?x264X$|9>&i+YL{a;SFT5Wu?qUy}D#v#Y0+M53P#1!x8Cw{GVcYM(xXNV4-Ps=)?
z+PmiU`!8N|!=)FlzG2qudpf@O-KG9{=j@qs)>@tqI$pnj&8{~#U9tD2T@!Y_wCm!%
z{&}PK-gUv{J!`)8*vD(WwQ<KAn~whY?J2W+o|tn;&w@GM#&5{pH>$4~|L5l>jGy@A
z<@gQXllkO_n`eza<mFkTuV{NijehyA31>X^<dqYep1kOC{EmP1jXz%cx1%2(via!8
zr@j2fgn?&ysY%=3ZaQS!TjNjP_QoG4Y+wJyFwwX2O!gMN#zXFTeV4iAhPF9_Z)kgB
zPjPSGJ&E(mc2D`veRIEc))VNv@NaMI`r)pZ-kh-arFUD-Oq|#Ev4?(e+KRQ`TDWHI
zw>~@nja`TKynSZNgasEK^p^z}p0xM(7gXH;cJ&X(Z+NEv-Pb&Gp8xil{q|(`o%(WW
z^l_VZe*L5!Z&Z(d`P>P)l~4Zrs69`9aq-T~CnH{c<G*ufAN_dU#CebBHve<nz>~`w
zPyhVwc?VqecH61wJCrw#qvY(+pda%aT&D5hl`W|WkF1}x^o(noN6oG{ZRskT9lfe*
z^To^hJvBjBG+n%^<+U}1ozdK}yK+O8Y{;I|_P!Z<_Gt}2y2U^2fR+Ahe_j4ie)MOL
z_PhKqZ}&T@@t<beW3OkAU((^9v83G}+IHuxb2jV7>dou>&3*aWie%ewvfo>hnc45=
z9iz@TbNi@%FBf!n)06iP?L4vX?CujQCp>@RoXHQ~qSPx5$4z_XqT~9#a^v08uIM<u
z`e}c12cIQ4y$k)eRNKx}%h>fz{SPXhx^(5P`hMtjLX*w*UtYB_Kh!_$$R+-3uXnb*
zc0+n+E_eGo{rc^C!<aqqo4VT58k)Nn_>JLRvra1fK0o5KKlVFq$+cAj8-Ja>qH$@q
ze_;Jte=Cd}__usx%f{`=U~@-Re&dOKE4ogc+0q@%4C?P5*>ZaNYeToZP%sOF`v-0c
zD$k%f&XjXQH%(FMXANJQ)>?jEdQbVRD_^pOPrhrHPuv~Miwb`7n4Aj#ombJ^qN*FS
z*bfHNXWmVZnI083j^UZqsCND->F=C7b<(7Zqe+$F)26z!#Z)(Zt?a}^-<Feavn|2H
z#t(Ma`6o8z{N~lxzdy(|-=9A!n`t_#GTUU9_MM>a>^u3A_FEFI?YGo7YSq}7=l2`X
z?I^wrO?%OSX|FD?%BR0jVV8gJ8e8zuJu%l${;5fYhtW6aGt2Xkf~DOI6+8^Wts32)
zNc!6+CHZ-@X{xRT-8%ki*tJ(d-SDtcdH#v*q~$#82RrH}Rkj5FiHu11&nlYxgPJE!
zw#lw+q~7qRsn@;n8UMs($@W|HEUmZ?Ml~j%%BUaH@ui#VPDQ`q;`SS>P+%1g-D!09
z)b%pJg`2E0n{QST#|2bVPO1AXzfH$DaI;a-5aWk`rf2&Qb#JEkmPNod^v(Bo!DD@u
z?c^sgl~IH7Xo~2zu{-HzXB(w<!TU0^+=<2u)~jYU9{IFlbw2&3!GAn*TYa8DNq-*<
zXMAguGfe}|mBB^PO{<waT^2^>6GX{T4y87$hRz}23ymyE@#m=qCr!>>#Lh5)i+cl)
zKsC=2KjwiJZp4kKhJ`wC=jKu+o=w;r(9>W~<(Yyyt=Q8A=Mgy>o;;7x8|6&Xd40gN
z75;z=F&1L?g5V30#|*(E4%?|b-t=kFGbrG<gh%8xa^;c1uI`pJ_-b=hOYSR%DCNyW
zQ31bG>8Z-9+_%U;+#<FW?j(4#gr>}dKGk}dM4%-beU7KeHe?yoBg3n>(<tC)o&Uth
zNFMzEVFe>?ip}n#T_=o@_3Lz~rul_pJvUZF6&t(+2jTcSU8|PmFmxGDeaQS}PpxDk
z=dA2P6~%L;sw|)M_k9tbvLNs?+)_Y2*mKX;-Fx5P(nC;p=IOKH+jh6DIK5}Ww!QsV
zKX<&hcLeu1$#2)~YvZ1$6@B&&-||`8ZKup%v#s%f)$e}R{>sOn_Uz(^=hi$k{DfC~
zKD+jno-KPneDVAV?>}{J*|s@<f8x1Io}IsUYunJzo*F)E+pasFc=m&5ubRK@{Gp#s
znozdo&28sg`N323uiDz$|CZ+_4EW-ocg$$};N<yo-s-kfCX~JMjoU7kGeR#6S8CfS
zYbswEzIN`as@$c8z%+MT$vV?CR!vJM?iu7~?I4x_O><YNi}WoAFc0;+8+MT^Z6oW`
z<FBb4w(^^{Dy>qF<ow2Tb;rWNU1g@vo&mEG%T;wcGAAaVU%!6P^S(-N++IC+@y6ug
zVNnm<MZ22lRgasN*)%fSGEraO>{Xq$oiYD};bZDf=%3thLUkWjF(Fs{j1AkDkNNIv
z-bm5+vT2N!YS6%-K`KJ2GQ^u*xc>u;RL%c@nBB8dlcb6%El3GuPGwy+c7&KW_S0Cx
z9>o*hSnO9B@QdrM<1;t~<P1snA;CPA<x&i)Pj#d3dqm5ki6GU{qR=Wsb~{BejDNGX
z+;PI;4Audz%4^$AE$1yR-tEI_9Uj%MAX0&XEox=m>Y&)n3me;N%LfM>iD1rYWb$Z&
zE}7viQ^hXB6x-_UMv@|Z9UL}@q$e^wnv;86jU;nIs}e=66=$WY15cY4)j&Js_kL81
zl|;+p{;!74jTUGs_%=FF+OU@s7>;Nm4)5(V!tSz2v%HDa;X3GU$q<fRr3Te*WVLq~
zPBk@B36jIUg-#HisKs`v-(|!Th0-=9wl|T419R&--Od$1s7=0pdJfvU;s{Nr$Kr%e
z=o;-+I#%w^V2W>*r+G`%#fks@WgUxhH|-t@Yve_AA5uR5kFWQEv#TiY|7XrUySck8
z$+?>iEEr(!aswL-;RcXD7GdsYgNw%W24jU5^d<zQ6vzgF0N;?zE{j<(wF{*}#gdDn
zQopoDRJ7E>jZg~~H7MU&R3y~DZBYVf1;z4vf9Bk~N&S9bzi0QHnR(`!=XvItXa1aX
z=9~*R?pBy7Dq+kFsk(zd@MRO+tqFUE?eRPd7iP>C&E3#41du*P5mRts#Iy{P6HdqD
zGcH!3oDSWIjdgValVccJhr2(FrOo`|0mc+18(d71FmxAZhAzhon2wwgV-;$XfM8?E
zB)hgea(U2PLmsS52+nkQq7fX1q)FOrO{CFt$;`@b$Nwr4b?g2KR!JR~%qE$HtP#cG
zN`j)f$)S)Lb5rKldUOf(588^FF<(Pl8}Vs!l(dsS29+X=rv~R@@Fa1*oZ)oYd*g#L
z;!!tyE+Vpr9Xte5#h8Evy&_6`!%YiDeHR8uw~XU~Ws8@1OzPWL_)f&mgawdN*7yoj
z1+?A#*OVi1DFxNO!NN3alv4;&t|(0_=^iuz`Uz)jnJXmpm~i@<u&Y`M@9d8{btljy
zz6v4KMaP$NJeF8stT4KqHF3|=U*YSMtcj#LSG<C*+`lQ8uv?oZ=bt_xi{W87zNc)_
zj<}@eryOON(4=sM>P(4&fdIg}+p+vwyf%n4ol+&o(+-GJogBNZy=YYl-pE0!8iSis
zU_+4#@g7J%A5TC{%0+HPH>u()wPN!ojLN66qQ||^-vlx(8z8(973_@d8KA1r^5a9+
z7r<3bg9I0j#gB>xsPHxpg8}9FKWinJu7vVMv#i`QDI=KiC|E&_ev5U;_en73gUgH<
zjk-~W1orPtxJj}che@>O31%?q9fL!$9IxZ4m-l6Pruqoe`H<O_cy{-w2~zqb9*?xV
z-URU;lq1qRZRJ*}iZzIEb7F4lTf|I?(<vx*1qMY%t<kQWhv(H;-4wW$Vazy~c?L>q
zEz95-aH69K*gvLLVc9_18wSt;GCd^v=KY{e1G}m$DePiKCr8!5(4i=g@EOSB5{eqh
zFj7W!G2GjsUyE+Em`+lF$%y>KOeG&zEtMlWWdO%3YuJe~INjSEi2KGq^)JdbW`uld
zj~3G=xM<AjBHNU9n&Od|h58iD+~}u6vAYF6SDMgRl{#AWnG3SAw9cB&nqD94mMlV=
zubWgq3M!ZDMv=j4#oUDwK+)GybB-G(iglRxYKjHBGv%rLXjFYBz6du1e#J2F2O!{}
zW>5js=dzkvg~`)wEOo{$Fg$uN>|r!#7p)V8pIlk;S)C~}c=MN88Vrqa6MYJsrRD}y
z@|o{7^y-Q^t8h?RN=iQc?MTLNS~6>z;@ha5DSjgH+^f^N`%ElEwZfUU*UPX+nP5OK
zvNMb(LlxSp*PSUomZ40c_B_4$GDX>6HHhc%`+>#KoY~DMz}Srz63?tW(6`jxMSCAv
zOz9-WDr?Z<Plq%;cB6f2mKj?!i$-WPpguGe@Y@wm6<`EmUgI~j%?frKg(ka+@Plc(
z@|hKA>5Kl>zzv=r(^XHFhY4@|s4{374L{vJF%2Yo>m1cGnrF;`rXPwH9kVt{L|({F
zufT@Dp^?P+DNtX=r+Z#UudR^BpjVv9N=Kb*ZtV_c#ObFvqdBK3nHJ~HSjYP~nYrA=
z+qMJCTqD5uNcNXecfM1{ekwC0lqsZYCU2)woIve_P9g3wd1i#{ERl+!>DdD3<gUhP
z43YXVm3i+KjVF;)&Zc}&FBwyu;#paIokw@_bPCb)omZ5<j9n!$leEI(RMt18{uTH0
zfarjg(6mFE^O6Z;{~?R)LYxGMI}UN<-xEUy`6*w(iz*5qKnpAwb>aBiO+o~EEYcNm
z6#}V(YskJium*@|vmOU06S=`hyIu1Ebx-JuJ|{KF2ocIVQ2{WVh_a_*5=&v^=@9LL
zsG0{otU0V46~D>QV6ygrxc2137@QnfGwu*uBf{wKkdb5aGf8@CY(QkzXhf>XKYc>_
zSc_a0G0WR_#FZ086OX4WBiGj&6O?Kv4Fet?1euHFEIgeU2VvR}%8F>`84v#8HEa^~
zI~ZDLjG2_f!<RZ~7C`;fc%y$HwT?`3`^Qb{K}5S=`Cf6!p@6eEq8=?MJBJf0wP8yB
z(2F*XtR#&lAWjM^So)a_Z$T@iWd&nX!q}WhMOBhiIIp@Vnv9gAuG&df^ETQ)o7FbP
zR04sFhzYI`n3Y-}Qk3$95*2VK-=ipvpy?7w11H7;3B-S0U)@+N;+5+n1uP<X&c!%L
z#M<;Zu@o}_g8|Bpp<}APDP2iRN~(Q0r47P~UBab;qGC!X$t4hnkvEeHBMKFxK6PPy
zqH_mOHYo04p94;X`?=^F^i@RroQsdP6f0uzYuAKPE_Q%eTHQ%$5qPwaEvwKPODY2W
zuH7<ZgUNMPR}CD4coCQ!8NC~11g~>!+}yoThLMp$OVFeKgiKaxiqQMzx9E_cBWosY
zU&!|{LLoZqXn|{plL(~wrQ2BC5f{kTZB?AoKuGeCbMXKli)o|*P$mzMDsW;Kv%HeZ
z#&?vN<P_?&%Flb4bnsDSP{dQ8*G!Bk93dCPml|SUWsZq7uAQ6Hm>`p=FPc#fZkcpU
zAIAt-O|}V{r(-ORbZuOk<T%r4Bczi<0b6e)^!pXE6iRaMDr!aovkRqennP6H(F2^%
z5!yTQAFnCij}<UM8}C&IXC2w9H-S@(2-TvcC%ssPh~Xp&N&tDaz4Rd(1xGJXo?Z>o
zASTdw6O}_GUy<wp536jhv(CYwY@DT)-<DBD7ay;Ez>RXaXtJDHAl(LJcX4g3@)((J
z>O^eR(?%2^iT4>I<VvFtU!bbzs94P$?^G4_KZUV`n=)M*M`OYU2msmg;^Sh}4Ye7w
zT8RiT0u{|ilyM}-tBP2?gE#QpA0m-g;kX$zucFu(<3yJ;=@PySf2tXTrU0YhtO{Vk
zc+w93P<U!O;vp=;K-Fpk(|y1MG36<usS%I~b7->^hZwEIT9G%Qe3)@X)zK<1A^tvg
ztxg?%%!p%gha?Z38027O%aNN&NIM5x-Moo@*rurZIO~rnsp>G;GzdCE)O+@kTl!A|
z8?mz}>7$ACX+Ur)66@(117iksT3J9HIKj!9x+0K{sO+p2<iparZg|;%k+;pjqi($X
zqTZuqJA;ZU<^lnb6`f;>0_YmMB^8!%7BAV7a8zRj?defH3V~=AL`OYl2jW=kG{`x}
zW{K1ito6JQ_TN6wnW%HncCNA86_Ksm5F(K`tq#IF#S%x^NR{M)kii>s5JOqVDNPU-
z@NMF?qHWvCw{z42ShQ0{3C}Q<`xyzyslharbEHU@yeG&9bIcpr2@}K!{*LnMi9~0i
zMLI%PTRby8fUVnd;X({{p29M8EDg$s=>C@BOu!3I@oZ8@m^stP^~cbWlhnu0JV9Fl
z?ZxTm-T7GzLh}``RBca-C?CP+fzINz5Aw0!QOmqq5{5}s&qx{v!l(fVx39Fa^STki
zp(+a6klQ@*o%HX9F@x?wlm1UYuz;x{H;NKoC*<aN;N!o~hhs8??`jt$D&ts3INJhk
z4!L)N9-=Mu=}O~b;Y@bC{xd4j1|P$jJVjlU4$%ZI$8m0TVgWWWFZdkAJ7$q}R1_4d
zNxSwoQj?CV0`eA0jX~RKj!;l}PlM%i3<<To4{Z)LWyk6<Mp6OpOL@}lj;HG-6!T&X
zcr%kI)G2Bf71-s46F{Xb*QRc-r6SHt8)?fmX`JX-R;KM6`ydPXs)AUZ!*R6z!RMi;
zbQ~W#b9;L&7762?r_Vk|d<JrgBd2RW0u6l;qVh0uF_rEohqW*?0lbfS?UTgj5Mt2g
zlh@uh^5n3x@@QW1N}g0%`ifUJ`J(WOswO!hQSXGv!41#$E%{*1vTf%M&AyVen06$c
zR0C)*kKn0I5{;Mh8E_rxZDn0fM=l+8MhUBZIPV_HEiS66u)ERKCey?mN72=_vgu~S
zMyL!U&uMJ%Of+?>ZIY1@lyF%xotT~}5M#*-FFr*EBTvAgiN1HruN`hl#(cXlp&W~u
zMUZE<8&=#F;-`|1zYzr761AT<H>U#-0)DYK?jR<BvX3su*STw;vmp(*dR2M^Zmf^H
z^{(*<B@=uh^Ls=iA1Y~04r!v<={@;p=yW%=i^kxK3ckz17vK&@Vn+F3IkX2_ZhAz2
zmM9p_=eGz(Gha@#1~<Pnq&vt=x<Wr{CyRNrz3&G++q6C2ng&%uWa6p8d=n>4*_!W$
zI8#p#kUu$+K(XPC31Kqd{9`<+VlqS#FPqc6Z>ePx#Lc8);urLiZ~KCHE0^C|s$sul
zqMc)3su_Fk<Ja?%Z%x-}#ytT$a${l-3?7Sf30U`N=zMb&rrsNjRf`s%Ad_WKp@Hqt
zPJSHgH3oeFY20;3C_BY6YR}VCH9pC#?$DEoko$dW+?z$hi|C2Nj%l~E`UtronOM{h
zU6-jT<x6HxIq{VDx;nJx0+Sfya3iK>Yj&x^);Ch<(P@mp^isz8(|_@nJz-b3)t;P>
z?_lpkb!+3tPb|Ow-<~*N;@<jsjnjW`>-c+?y?bKl?f-0hFF);yL$fnZy?^b6wRNkX
zE)3Sss1_F--hcVcFC2M!?ZV|3Ejax5R`vWr|Fx^XS^l^2AFaLktRv>X|ExLluYKj#
z@~=0}tPKl}m|vTi*K^gzRrRfVuU}TUYffQg#Ws8P`td_HWq-GNMb|bv!Vh7bdg6xK
z@2$U%ht%8b6JIXabC$kg{i(y34F6=^!}d#`Uv=ruH>`SA`c8b@n16ZUj8Ff;3ujz#
z*%R-+^yg3f(Op|!xAh-5HqKr4+I34ezP9>P8{d89y&K<s%9hoyoxWxDZ;!n8hSyI1
z!y8_kf9;yB*Im2je_eCcxnEgy`MF;?;XkhV?~^&+_u31$9sTPUZad-HH|)4-%auFU
zZF=F&=fCfTH=p~zR&P6a%f@Z}XRrO$5$|04tHQ|(&RB8sg5O)c^~C=?^M9TApS5e6
zuN{1K^R?3Vo;&$HPd#_?+JC<I)AOD==F^M6^!b&?&iry!+@tkH?vXzEnbSA?*9)6J
z_WTon^tFp8-d=mx>o*^J-ZASwv-E;r9kS$ouPyuH#w~AnaO1VtY_9$6xXt#J<FCEp
z`32Yhh4j6y@7i~4e%)#3e&yh6&-sx3={3LJ^wY(!C0}~wwmC1qd|Tny7w$Oozc1V|
zf770~9d^PCZ$0F?7j8J1qj2`3Uv<Cp!vC6o@`48ju3GR=4SnBy@rggP*WCTm!Poxq
zrP9}ae$w)%etxp~&BZ@I?zM}5-m~P&x8T%cU)P?e=P%%9@a|RS$2YH9`SZVA_3Wq4
zUv=!diSK7e?f(8@9}K<EURLjY+Z#)dH5S^hT{`fsgIAAS|IP!4>gODJcKw|9-jW@C
z>Mf;{PkXNP%mtr%$M>%qddC+|Na~+C_}lgV<G)-tCtZB%zn*Z}soy*Lg3?6oXgl$a
zqiZ`>Z(6-$&DfRON{1}Fe!;TRNVay_NY@+Jf1$X=J$T$!^GNOD6}#Rnz5f1Bc^*Eq
zbnW0HOW*tTb62gs>FHHJo4#`8BzvCb{%uHWkMHjO*$;QG^k+V?s_&p%*4UA6Ej)kZ
ziSL`V_5Fn}nqhOFedB^b`*itmziWwq$9*Tb)%VXyR-fNE-k;lb@hP_#mY#b1!Oxkm
zul|pBe4~3&ZAbQo+KvVP$D0#crT(KgE?Z$-eZ_(!>o=5+uHCR=L)t>Gf12}_3vbB&
zs5~)n-puQ3#i`fNIcEJsi!XBz&K=u*<tY6#?s=MSG30NYe|-HK-#`AxBgJFFR#$E`
zlfi)-+@WdMKHrt5>h^%-AUmI4+u!5dr@B@@aq`+)-+Qg?TQ_#L>HA97=-pGQUind5
zEq|&M&iG-gHSmKmzkcIcZrwRaqxTo@Gy`WJ5-zx=7}lLSu{-_5jF~h4>7f<NzBZIF
zmLzKyWF=Sef4Z#VwvW%4!g_T3g!ViwzT23o!R*BP;*kvfl41YHe1!c^(mx!SFdUWs
z>ii}B<E2~vfWeo;me+o&$CaDizHbA=<)4^(sk>NbE-O_R6>N3cNNIO@xOB5ybgpUm
zbE@mBnd?2J-}Np+uTy%$y7J5;=^H0@54`uU*7@us>k7V`@#+sua`1_MyE&2DA~Rgm
z%y8+w=F41M{DXd>f)DZxW&@sI|6oA7$eDD^goS>@q&Fq($#LAOWU$i!s=1Nd!It^d
zR2cWhm`5MsvM?o=W0VQB?;rVHj+Mq{y14sVmYGMqO&?`^o@OrkUQXA27Nhm64B!`L
z*}!=orm){m-T*vPp0OY{S#O<P1g^rIjB4ge;vdzXr+b;xnXf7+BN#&$^pI}S0Vj0f
zG(z!Hx@a{2$BWHuC7~b<CgsbqPBcE|vzG!M%12%*Ueg>a-4sh5?#&^PJS%=W1f4iH
zw~7tc9J-)T!Ai`Hw>B7)ZZT%lNnmUkFe8C7dNtlm2VR*)F7ng4u4W#keq;Q6hUE4c
zm$nE!|K|~EsdXUnM+_O*RkvHXDCiH|@^j?tnUYpHHI9@zsNkA}37K^cl;nnNR2IV&
z-jifYk=6>j&f{VL@{tMYq{C>>)8b8vX&(Fk2Nz5_G&<Kf)9V`{_@V3oJJg@LWM-t;
z^a=O_OO4ubCdm%a&F_TgmNu-eA@Cr3F`s~9Ipu42O<9yO-GfPwzQTCj5^d1#?ixww
zn$JG7rSRKdJoDmZFXrEQy6^mldcL~pnY~*+`&Pd5^!&X0u6u3btDAPbeA%DBo9{er
z*!G?4Uc2Ex-uukU?;*YAsWay6xbC)x-@56wSAYEH=bv%aV^=Nz?uFle`25qK`R#?@
z+H%IPp4wD+>KEU>;P*Fuck5NZ*?PoFPn~?^E9-B&;P>zQ=dJH~X3G&ToprMPZe_>D
z4KIFo>!#nVpZD!c&zS$u?|EqBZ|~c%^;fU_WZs`|I2l)MIqe~;oyDHZOYiHsc*c(o
zXHVQzX{FaErnfMh75!l8tXA@^q?J68V4qW3z1bm;jI2K3v32A2tabLfnT9*We6{w0
z;=0xL(emPjtA~0{$$IU%bKg=s|F13>&-%x+!PTXAtbNCdUFqA_uB~OY@x$MqS+_c|
zYYMhCr?Ac(cD5gw@n(Ei*GQwQw!AT?^oQ(W7~mH&|H)aqtJzgMBpZB3De-I6n$mak
z={#{9UN4{75AX&prUdc?7afLfNL)t*Tpj;0A<rIxTn;PnvnNG5;A13ok~!6ED)+d3
z$={7-**d2^CMUErqIUfBvg3Me2rY|)Y=Y8nyV+V`1<02bim2xJQJB>M^_LiJsV`}{
zH~a{<AQ}t}>-!61<IZ#iSe}x?DV@+wvYHQ`zGD2eNlM|gw6)T8anC3l`R0V@OAuz%
z4_Bw{Aln?*S|4zG_RM4sL+}e=>5a?Xgy-^Ld)Ch~6y#vhuHYHrDm#Q|E>aJ4-g7nJ
z^|^O07Tg|V9$`dbcumYgZ)?6uU)67LHoMd(T~cQG$ZGR&)FW+u%BQ64;8>4wrkU6x
zTh>N{xDAaBWu|ExjBx36&q@v3;}c!Bz->K7D*v5RnH-nwIg=H$ZqC&;qBXe^=r`kW
z&y$n3>A<4~XlN*KYmwlo083gJ2uqb|Vhy2!E)CQ(sUI9mtoC^HVedp4qb3<kcSFUb
zKreP0Zv2hV^T`c0z@!=J+2yefwCs%-34G7QYbb-H%A`N#Rx?eRG+<T6+K_%3VGIlu
zp}>&_&fZYZI*ouo78Bt;TofX!N-H{JSCG)<ORwp3u&*$v>e2p0{4~L`%_PloHs`wN
zNn9p`wF}MgC_gs_Pjtml@`WCkBp*VVO07T!7dV0PlMI>M6Ocdt;1L>SQ8R9-QuA1B
z6+czwiVHE8XIz`4r_fax;(TU4YLXUrO&hqUgPqw)y}6^+FsZ8^kC7S7Z;m$eMGrfy
z#JzOihiJC5AajYCVP-LbE5mUUKwCfKg69T}CDFwP$N+B>Z%vC|+(QN4RH1uN8FA#&
z>W~!;YKUiLgOl7;e*>HcMvbc>%2*Z0_UKJ*aoB`ic=+914`$3)4UGpUmyK}-Rm1C3
zPZVmEkHEa=Mvq5AgU05Qj3C)FfbLw3QO4F#C)@cqiW^>U@ksV{xmT=%%~onZj*mVE
zK`?!~(xxKde8U-wGG#;U8clFTJDiL<7-M8AIZ@=Yi$ZEtCbl8Ts6fT#UNjJGz=tUt
z8XH1<@68Ok`T8Ce1*RLKLx9}Jv-yQ`i<p7%Nr|s?9U{AleZrx&1ze^tgtacLt%C>3
z8Z#8)O$s}TPIY=u1ZQ~LQ3bd#Ol4Xa`n54MCD4(llYQ~CZu$ZG^IUugW9J-#M&$AW
zczE&%%s_AoQaYSj;=Te)#~(MSJgqDn7PpaNa|HQ%Z0r#~ye^^=ol|V#5Im^_A0nxk
z8O4A`>QGNoBB68qzMBOfT4e{ThQuOQxt{uB+M44#APyT+8T?0M8`^o3;CqgSAS<D6
zLn`LpP%x%Rgxdn*?_~@MXk>tZhC!Z#P0(24RC3fIvWSl`By^3AbVaKc0(tcB33`xX
znQ<e9KxN0ERWD@V^uc6j#!W*EHPAFT1mL?1szMkoz@Kjq_<mX1r7Qzee3vt1)^Uo$
zoSF1y*yaWYNxzIXe&7da;E^4z#Z2#~ykouF@cv@s>AHN}giPu+ovaL5Iu@X`wt_lw
ztwZu`cb9cAu8_lT8u<Cf%s7nf7=m=e+_4+Z8#+e?y&$njn;UDxkfJhtm4+_Y&){a<
zH#sWl@XbMJN@Bgllbc+K{|&k!_M~<d3+&fR2fv&*@6<}TI&%YjYY<W_b06=bSM%W&
z22m%kD6%C>&zPr7NO3N{r#*?$Oxj!V$kY6jtIu{LXJ~cnFzU*XCTWm0M@zLeCQ(jT
zN|rM>R%s){@0H;z#?Wi39z~a|Pa1d-9|||+-eN5%PkWw9j)=WAGj~r8-)%Kh8@Gqv
z0V7kuvFX%Tugs2Wt}(|`;TzS{hsIBVJ<5)I_fG~3u%0$cT57*x6rx6M<iH6^A{<4y
z7N`+=nybIssLGQA7GBR&rIMLwhM}TapanS&;w#J}yc{scOg%~wQ@y%pP?sDnp0)en
z!BB8;@#I?54<k{mwBpC$*E<y!nPk-T1=CFZ!pcpykhpL=OT*CJ?a}QI=HD8aB29X|
zg=U7a#3a3pVc958<AMyf$h<Kv`gCHLiJ*=?a&uiJWFL8n%FMZPQDw%Y<C9alr)bCk
zZd!+_s+4Am)^EhoIVO!wWH%{@WoE$<YboV3+RIXg4UZ&g^+?7j>q#0cr9cMce+vGh
z0TR!Ng&0`th~=Bni7?>}6Q~+U@M5aY0W@zerDCUHCg+kd@3Xxn^<#()k|t1*T-T5U
z5qhslnkbO?A<l&!h7o7v8$igq>Ke#%V7!6Mbfaok)xg9%8EvIal;B9E-grW<x;WWw
z<GsXS7ucRiET_y-rWk|}v}HK8J=TqBv4A5&hfNt><*N}?Ba~#gahw4tgPTg4F1RtZ
zd0cvgAzfQ1ot+$!FlypE(uz*eMan7HRAa9wd^xn8GdBW@0#LMDH{_y0p$Q_k7y<~-
zXNnjNX-1#fWDXfL6!{6Uwsp938i)rmcGM19Vrj#IGUy&hccgg}^&`7!-0QB52~ZJu
z&`-!#M5Sa`q)-5JYpQ^Sz|n4=q002D0tuL2rgTYWSP7zoz5{TqgQC5yP&!eTRWDIb
z!g1i>@yy9V8AK3kuSyVevId)96H&pQuSZHU<1as}O2iS(AyQBzofa!|OLRMz_ixr-
zA!!;9rL9JCC}_uu`bA`$GfJ}%Kv)|r0g_3kkuk%Eric{jqCY#g7T<Vc7EBJwdir9$
zd$kYe_Pw-C@K7asMBuTB3Om?w?p3V-tYU_z7;>W|WdkAASm_mQqlu+CLO921l0(q6
zIVasN3Zkd#!~05^hLpupxj2<bakHE;i>M*RT|7MJwmZ!dM;xhO#_~LU0al$qf*Qc3
z`OpOkh1FYH^rJZ15toq&xK-tQNb#*+gHb)vXmW*Z=%`#nK`BMS93@+_f`&~#gfhA(
zt7q$z1_V#)o<7jj$vK@94@uMHbO8sE&Pki4soK|vJdWE|BUK{LR)qv?Gwv8H))kwA
zO<=Cv{|R2mvbAk2a{_5Vc(En|IE`bf6wwMNEx5BGC7Iz(Y>_5KRcS^GNfR(g0ko;h
zRSUUV?cuB=Qp*fuf~X;ob*J<sh2kVtDX$=hFxGcrr*5&lhA|+C=VKJ$?wqCSC`Xwi
zbaMh6oKndmmP0)bn|OCHsR<!OY^0E_h0Nl--{uc1Ug(SR8<C3EieX&N(03ebh@45}
z#HpCh3X@V@u%tXE8QPKOa!Q*AIx8A)de+pFJU*vt<Rh2zT~H<BSVFUO?1OX>nt(C1
z8!I1cOz@DhjsnsN5t}+uX27=1v=PFkQHF7%a-sob%fGoJMs-SDj3UBo`?;v1Hy}wO
z;h}sI0<L8h1fBAxAkgrcx-nudZx&)c(zI129U=FJTxT!p$V{aK?P|g+PctNn#<x=<
zaKx2s+qj@HF9$1pC9ga8Sm=_})`JZY<EW7eh5%lX2127&5GpOj)c@<0o9zFU<3PsW
zTYD0zvr2o#JK#c$<>%;0(ka(5<~USP_XD&t%#~ECT|uvS2im!vx}$iz9|z5OZQuv9
z@qA{%NS!xiWEUq%h*aPG1UX02F<sjbRm(GpJ7NOcj?&ZHv96%aKH?L-PHP~!J%l*$
zY`K_@r!&cjBArMmWKB?HKM=E2etGtXJJ?8Torw&YbO2A6A>f-ASW7c~WDh1yyd%{f
zMVScTq@`*ERV-e}MOGFrxxt5&>tK<1A}Rv-{G>!s!jX{*#~dH!#CXgMWy&gp{}3r<
zh1|46_z%oT#xib-9=)}e$a6>uyGU}pqEV&X8DUjWCSl~Sf=*OOs_U!gcuL$oC=&Wz
z4B$J2^)<^$XETLuE?_@y4vrx4oPfx=sJ%MgxT(B%r+tMuSJG>Y`e>{Ow8^Av>z0|o
z1BSdA^lfqg+6XwGh7kUR^9s5hayt3>Tmv>D$iWJomI9k_M5VgY7*#TdK;XJ!Ttz$l
z#@ZNiyrP{_<U8+X$s(0iHYYZI!a%3?oD;1O8N_YjPWm56+4k*<SU7ht6=D?0Ga^3_
z*gAI$+40b54(Z|Za*lwMf`v}!VGdy^Zjy>J@_Acm7uWTQ38EhaB90^0xm_&w&xq?t
zA;Xv;$~}rn&-g8}pm}x{K<CMLj%CR6mQ%lqD>4f%pkEs!3ssd9_(O=S=UjYiPFS9u
zwPohLDQ84kr&TZDbczr<Qsqqg&2E#5WgMVQ^gAO8_slONc~p2ZUkgGR!OPBhEO(Z6
zYQG>sa0gr`qA=`BNIiU*0PyNMxgQXz2?ebuvn@1qiaH^N$goqv%!z{@2*)9j6YVom
zx_a)!f&29lC{$w{Ld;B#;LbY<Ii-W%gM>t2xq{8L5z5ht@H#uKEZ_DEk?PJKX%XZu
zsakXlZ0MyhBHNn+=Y4ojN}zo>&;A;^QI*$y-6FoMiq3_#ne<4=%o1*xLfn*(R~kIk
zZSuwxh{;J#QJ<9CKv~0uctz@vvwE?HE9m(i5w~iwmp=TPgsNRXu*OD3wDN<%(Va9m
z2Rip+2&ce3$|#IexMAxwmg<5t4cNhZ!`RYwWQqGwBLjia&zbkDevWE0qcM}8cz0GW
zu|LW9VxS|!%$xK^Gc`PlB;>j-hJ~zRh6=_Niyy<3>}+x=Naji3*OEq+TFM)<#ruXm
z4damuyMxjRIxe}qhiiLo;2!7%qZ@0nbzQ8Ju*H~c`Qe|bwfOQAD&tu$)9-A!=mcld
z$GbD{bm#Gdbe*@5eIoWL4tOSgN6HQ{msJ7+6X*FjAxCPK$am(Nfc6r%T20EmI$P!g
z?d9&#uC$l&)(+aF+th}fS?kG1OVqG5mLgqo%_rQE78Z$38@27BfE#k_j91)|iNrL_
zO^bIM+b}1kW+Z5q^5u%5ZtOf#V{;r06NkC6vrCuvnKEGow`4bxiNDVwA?84Rt(|eL
zn0DDI%3HWhyQIv;jF{k1T{TTluqm-kGud91s;Qs$=}|Mbix$ax1J9isUxk<?j~Z<k
zUViA3C2x7-6{n5WYaiUEJw&HmzO?U@W4HAF?GOHB+gH~f-F@iL(!N98(!RfacKO5i
zJ$%6RgKzJiyKvy>zCUPOc>Sl=UVr`YoP)a;u0DF+roBJ<*p_FHo}4KhH?Pm0G4H&+
z8w=IDoV|71ar18NJMM_n9({v(dD#{AAMe^WC%s|byz}1hcLyB)!xPLqcW;}s`-VAl
zmR<7t#h1FzC7=A<x95CyYTKOC79O$qjPXIYoSkepEPuE#efq(b(@xwx{LM>W|MT%T
z-2aX7H$1pO`abZ&aX<L*H_q60=ksqm?t7QKe$@jP{LRlF*tOvs5AM43(+}=FcHUJl
zE_!v<6>t7Cj@KT%;BWryw2z&*Y0I-e`PgO8{`i?KFCN{u`Gl=o*1WJ`4#%d2pFDZa
zo$ozk)0ZAOqwu9ij@Y_+{=4Vid)LYDJAdaF(sMrlg{>bx`iyzk?cA~Hm;Zk3l3)J&
zaqlE=&W_JLblqzoxqa!cK61y_>zX@`zI`qC6yEghqqkr8?f2ce^P%Iuv;Md}SHIzb
zw~k-=p$nqEFCO<NxBUFwH~#JOn~wbciUZF4;su|69(_OX;IkY4_Xj_F-1S>tnzLoq
z6=%+S*A?rw-haX0eDJhS9*@5N^k-W>^MfZg+*jEC-2At19ev?lb5_2v<;v4OdQ$hD
zAA8f*FFt<w+%G-;dl$TV!lt=DoA|<}b3gykoO3?+;1wVI$?0>p?%r|bkN$n>k^kps
zOV9q<U7xiNeeSibuYKf>BVW6H$NRSKzH`z0cJke!t>1EeXFM_f;H|G6dwg-}JY!$}
z1Ut#PwYTVjtC!9>^o66|bLb1hkDqex(of(1?1kHQzV+B&H8&i4+XI&_-Eh*xB@=7P
zAHQ~B?I&;g$gcPPWOL(3bGFpFFTXY&>bv-n4SUb~$E&(m{-pcb!EbgSFu3vIt8N`X
zV$PR#ANIbV&b(>f*v*@++LL~|aMqmi_`*51Ftg~4try(*$=-i2cVF>0<vB-xZpGhT
zIkEmW_t$IwV$Hqg&%2gRf0AF{df7;?-~N<At@5GE5B*HyPdN3ck1bw&RAI3AFQ59<
zWsCm&rb~ODz3G~zA4tagem+qC<N+Ug_R^o+zH7s_2i`jGrOUXzaMj(HymHxH8>Z9p
zCx2bMFFEj(>X$d2*Z6Vw7Jt;{mv3HJIA^B5>AZ>YIV-nyZ&^6Ur88YeYzp<?n|IId
z)3$8Cu-kpU>)wrf?7ef&O43dDnp^Er_k3*4)*C;WK3$%(@jnhW+=2Yi_(c7-p}+RG
ztWJmO?@yC8BlNhco)QfdiXR*pNmp@CWJ$Gp=)%5g|DA_bvsEYU>b+!W&oR9wx#R0*
z-Dlq2)pg8PKAd~_#pO9)J-a+-?t(_ol9C%<dCpY#_VcIgBLkJL^#jh1xt7~rX_X)A
z9zW`y-tnRBXB|7Q?;UTdtoq+~AAQtEn?nZ=Opd3w-m<Yaao_M=H{3V;R~LoBKHoZQ
zY-*}hzNvZgf^=xj@#t2RZi63T#3=APq-+3kRUYUj^)-XznLDbLjtuSUn@UIeR`T-6
zbqx0J<QoZ-J>&gmq->pSEG}Bt(=y3t$IcIPo*Sr`RRb>l%Eiul7wmBNcy~y~lk}WW
zNY6R7*gR%xsQ;tk=%msz=L}4)9=hR{;_dbpKB}<z$glWt$l{bwkQDFkH@8l1#BS*$
z+ViyV1)dkR2FK9#hum*mS2yNv6U=U|>q+ajLh)~%bB}h_?A@6&RqkzlkrD85Q)3O4
zYRvAvo3c~G#yW1NYtFeRb9S0(<z?!FH}Q!?4Vi|KmEX!C|3to%x0-8lcY|AWH4jEN
z8gJeij2&jY=2KR#&YZCt`ZDw7IgGzoBqkZBY?Gs<Jx>!~BW9AACbEaRGzgm<Esi~`
z_s0Xjdqq5OeAHOu2%Aa152{IA>0w{go+HImrK=pfIrg*<WZKMyY%l35R6K9su7oBX
z9?Ni$ub)3LkFte%oEt1x6Q>Sllw*9@ME&BPr<n;b(q$w#dm~(;t}b|!HnGQ0#*NpA
z<@s*ZO#1jj9XiQqV(U>=0b0^2H(E@sUM5~F97+C*;EP4iw<AqlzE%^{<++zJ?u6jC
zJdn&}tordO7w)v!y#9I@jdWL)hx*Xxpgm9bc6U<yLcizz`x3;4YI8L|zW>lmm+0cW
z)!*nX(8<VH>ay}hW;k;N_?NQs5ZMRtLzAv|z*bpn@YciHqb)P8Et>*g=lD2PN(-=z
z-*NiJUWrLpob<}`^B&l6QsLK29@={uzioFCdzv1+^r4>bZ`!eU^Glch_vud^H|M@f
z{`>mJkACRaTVC9-<@Cq+?Yiq8+V;KozQRw`ZP;@EV@DTuY`*Q`^G|;5)mLBIaK^8`
zcJz@uF1+pGx1Ii*S2y2w>FE#t@yUg!fB1z9-hJ}(Ti*20)+6q`?u_}btpCEgx83)j
zTaSBa!x1~)eNy4+6Ytpg+yDB;*5h`(cixWczR>gZ={w%H`M%%Z`pH**H1C*YbA#MM
zdx$o@g34~`M0NNwK3S6t^<LQZv9teeIytf4XBL)^G9N6b!8MO5xQ6Z$EKLSlL&<qH
zTdtRfS<o%zT7T~HG`!i&tnKz$ZHYg;6_N$pT;W1fDcCe+4{EnLFubR5=Y_*Zu1Wb|
zZC8Px#2GT7dDOZQw`gR{oNVsxI_Q9HPnzY2eXg>$&m3tE8}6}v$D3MfCRx5{fOUTx
zr0@3`?XhwE@8I_jX;-gw&<V2Ktrh+*%tT79pq%gI&5BZ4t^#n1;POluM{xAscC;OE
zV;~C3lfim~Z`aQ*YLCg)^fEjfE^b)gtubR=i8K8_#jzkO?xIh|a$Gk|<Ks1+8blAy
zrltdTGiwM-S<q3b9ta(wsW7HADdf$xJIYrWPvK;3S{N%!x55>04mLm?k_pBkiX@dA
z6qv>QR#|W%@K(Wr-HcUi^RScPw~wKjan4jyvMGOyud%K-D^$A9v;OI1@*Y&?iC)o7
zrO?tn28+S)K-ZNi>p}GU>nWKXO@~GebcL>_JD0w1&<|g)9Y2ZBnot^j1=qIkzp)%o
zb$_Wh(>>TzO&0fxZC(KfeUvnrDHy9Vyp|F8%dh9)i(NA_-85D2ct?VyZJGp=W}cE=
zXcD}YAtsGO9U)=gGP--kir=ITwh{pIvhgUqlMLDbwX<ZG&`us;nxKlq#+6}tvvy(z
z5JReqDYi^d3FC|lCJlXIhUK*C7R-eA{pKEJs?{gd-*QO5>=g;+)P}$mM80*VH3>(f
zZw;aeFlv&TNn?WI#>#_4>yk=rE2-J&GUza<f!t9Y&UQo}N0Au>){vj#KuV;;ee%c0
zMq<K2WtNPUTLg|nFdSmt7Mp%;CQw;8=|la+Nz@k{-{Vs*w7tndI1{7<A^wO@$DJq6
zPup!JTN&}jnBWth>6MAe#8{D|(v)6_(>2<R<!eh}ihV#_5eH3BG1I`d0plJlL%kT_
zYYr1Z&<gCYpr%eTd#6P>O{a>@L;_zY2lgIkbUM#rkcx7-I!_X91CCa~oW)7g2LauC
z#M>a(AcyOzN$NpjFg}6>ZRxz)k8|+@5b#AoSIjDr*sDNr7(p_te7^)tc?c}v(|};M
z*p<^M))UG%(7gralL?~8<-i`!E24+m#uH9wW`tO<LW-zQ(H2n+N0FphRNLVvR5v69
zrmPb<J}yDpTJhr2G{j+vQm)V5gvz{_Lv8U*mxW$6OG;jaqAqEuE7eH`k|07{8+f+8
zsx#3#LV9$a9q61e66Oh0_(n}Y0wQvFeEe`G<CX}s#Hs>pw;W89QHUsWqI#rHm5qI|
z@yDMc5;!cLoLFCGG=ZJhJ@qg!V(PJ)<U6WMP7WR{l=!OAghNbs7K@f#PacFk1oxE?
zYtd_*bEc$Bv!+&n6(n6s1)X48F=fR78;oP5n1Fxp0Ni=3T@t=AqZVP13zE6cm@liG
zz>no&6BPiLn)#W<gYqQZL|E2kur*d#mNTPfGz(%-%t}#ruaXRNSy$w$oTLKMQi3v`
zZXsgh`4eR@DgWZufg(F?5#?C(3Q(G+x5mrH5B)KVs2=N-VYo}=yhc=Oof!?=gU47U
z?un4+CNM{xh^Yi)Y5S@R5|T_A<5}<|29-ES*yV~OekPpbkTo1Lp5&orkMWIQiaY7c
zX$uA5%9aIaOn+<*P0rz?`T`DbEcB2^>5vRVK(=**MQ=jv%7%@w6T}A{tx`21;IG!P
z)5x>dKPVd=?HXZ?i!KMr^<DHEgJ*dMC+0bPm{T1MRtNSud1FkF&ebZC8KYQpCezN-
z^!e6{0k?)veZnun49MbPHT!p5pqBXYo@bcGk<;xEWdfhN#lFOV<nl=>S#ONh%e}f~
z8+h26Ib^5B?xxk~0gZVVzo0cCElx-^<OMo+G2ALs4p)PzP5B{SbsKckA3;Y=@5#c{
zOc5f;J2sYt1W`t}gBJ4zG206L#lEh^HtL}5qGP7wCJJoCdlq4)JmV|cic_bdO}|HV
zxF*dMev=LT=p9XL;a@D)xP``Ts3jz`iK(nOz}9MyWv7|_*41dmVr3|#gEOY=Jac@d
zoED3H7~-HQ<Hk(2$27Rn*_#fBqueB1XG~HxGx$3tQir%^Nbd1jcGEh3hv_#Es2XKH
z;bn{`hT&$<$>>2b<x>wXvyL<K34~R}0FMSaa4U6@Xj1ONdm}5v-bJQuY5D_l(hfQo
z6r%Xx<#k*H(y#MjI&nw>1IxTHevs3EvN6LXZUmLn0F9W7y-QRL+KPA^LJWHy8YM&G
z;Ta2jp6MI%uL%;wx<aZRy_m6*w7Ib@#)*`Zmy{VL+RWwtf>Gm~La&oaWY-J&6?Ho0
zN^1~cta9x-F-@pfp|LVX=+BT511ymcRZ=uMMI1p?yGWvaJzj|>hc#8s!%>KI%lu$V
zeq5w4IkH0liQ*E)?-{3&i%{_9-}5)AokSi~Kza76IijR<tH)cI3=ByXuHe<K(=vp{
zbAhue_kThBNrQl<Dn#c?2!g1x9(+_V04M6LsOK(ozNhKT=an{|xdx#qi;fND15#Zm
zfp;+#^P>srf12F*7_Fu=ATl=9SZ}3)DV<_DYaT(JK$17B80;8=2lE0NSy(T}Sw%4c
zTNMQs9ovvFe;d>4aY~Qcf-!p((=QvRGIgn~U0!7jCO5FEB+e4SqX{*P@&2)Hl2J1=
z<?=d(=xGTlN&<^H*ufY<%yBsa9568<Y4E0)jO36PHOuS9@FK3-r*l@ULM*5b;tcAm
zgdi&6V${<&VkAFBdZM|S`B+V|<#SzyZgE8L(%W@-s(G<6C8K+YX=E1b0@?os|3mIX
zJ3IQl;y!iO;cA%}?St7=7O+xYbGa}5TeS=OC}qVs?vN|6&YL90W@`sB2t!{{5W#Wg
zUPPXNX(C&m_@_#DY%{9^IMq%|qG&HqA~NrE9PtkkY1$!Woe%+S_vaJ2=K}CF8CEnw
z`bDKDNDEr=Y`g+whM>qSq`7o2_R@#|5FJ6PFGmQh=j4#mF^41FhP0LwkG9jEkYVe0
zAy}8!J!a$;33*o~0|-b+V=U^b$8Lb`WZb$nM{~xP<C@yI4k~iW*+o|t5tiy?cf!co
zYq$!a27Mr)7fOcX(1Ig|5C|Mqb^EyFR`6a~0EX}}lH>F7CV)Z@rwkX*Pz^`oAe=Hw
zZnl3!6ol<6GYARebYdugwhhYnCPCX8XBV-ZGNN~R+h{rfoC|q@sDf7&Rh*vYoSX4Q
z_ryjmo8eytnFG8vm*uur=s3hBpYviQkx_Hlr&{Qs@*?|E`(jSQ5s*W@6~hpmLa$Ra
zOPeAq$dA=SXN5%y$AmQ{oa&z|7V)~)0QSR$M$F)pI>m6XC_dLYJ_Dp#{|CgR&zp3=
zEXvWWVV~|4l6HY3*EvS^J4Ib`L15*#C;VBS?WmDJ=U|-pG@Pnv_hYa0ex~YUjtL+f
zhr$j7tFdE7$tbYHA=WKQAcx5_XP2L)ch04al_E|!(kwyuf%4za;d7MB1JTB4Xr~pp
z+#Wec(q8IVj?}lW(ufOkH3>WGsdA3b&&uV_!9G-Q#I*)unb9sRTW(mIlStbjK|v&d
zjpzK7HVIjNbB+tWQjXqtmL(|ARyrsnR(~Ip+*aVz;FQ@WZ4YRk44-P&LVywxDDB(p
zRWIcn*pQ!nt{_MgQcgL97`S-3rzp2LC>8UON1{hstyNZAK_|XB#D$d;fpqQ6e*GOy
z+f*??u?RtDrYtuazl*bhCiX(*mVi}o#Kp1$E{{Y8dE5&VbTU%3ZI^Z#QVyi&XmS97
zak`vG+r`kf1x28`9Z3OJq~m1T$~nelF9m~SJB|qX5ZhS`b+Ckf+SIhX1Umke$Ag0Z
z0qrR_?1!wi<3YmxY^`!^WE!IZ-hu!{jC-Xz;L=Whj`0e#7w6O^IU?kN%Y7jxTzj)!
zo@1gYmkVL32{x`U+qrmGy%SACv@*%*4oYm{Ctz?(NQIbyX}(McHw#gQR(C2jTf^DN
zKGI;KAcB23;wlzPyO@Y4v2W~;jRe@LO_J-Txtptth)a!eL@4OoEE$M>dU#R-+3}5k
ztXSaikzyZ}@Er(pOm^bKJCR2F1MkH6Xx4~y?JR|};@eC^JFgS8FS1PV1yD0lMISSD
zTaWvXA@2_n70i$cAT&hJf^}#FuB@{s?nFSTw#57fmokBTT^SVhIssZ4dP2w12Iq<7
zej-fUzKZ78N={M1ern_haf--Jo49<4^V+BLU;o%9GQ9~gmzfgFgm{%BaSh5k6<1l!
zH+gr&CSV+fILCJtU5g~jH+h6`qVZnBf-8FlP-m?7+$M!O8|M8n#sdcEWLM2h-l8(j
z>@GQ|J<kzLki>~tx*A9;W@<IEgCF5qOydLJEET#RtFxF-UEOpIVFC{hz^+rK?zmr6
zmD(<<Oauri(tT>2Cou+({MwBSUFI<+(MoL~)8-dea84EXB8$u*aq<EO4R^j7`%nV{
z+4A{a#MY-}XYN8L0BMfeI?3Q}4{Ldnra(${bK|~CX>*L3&|1{=tyYR#E)H=Mnh&9>
z86PCv*a|1_y!C|Knw)k7MN}Y-Mm{)hupon2vXip>cLi~<d>M{cZi4z^`_`00g8)fu
z+=y4)!`I^m0&Rl<Z{kcbmp08fWhjci&Y%T5AdF?~T~EHsTcp%E<#*+{8D+EV=6rb}
zr-<*U4~!NW*c{aIE(SS%AhD7e#~&E}K%!%asZ7<;o}2mlA_ppuA>X&QrKgzlE;@bX
zUyl3M2mGFqhj{>S%KGZ?c^8fQUFptU-yO+rxpQ;YxV`jmjor1q&pt8Yc76Erg}44g
z^%u{+Q2XLcxqOd3EL-@5IpLSP%eBzjYs1`!7aUtSB7JbrK<#Vy>|Pc=)@8T<*?|Wg
z{?ol?%_*O&uKC0^8zv64rwwn;?%cbw`Y){;tiNHjXYh)vOQ$r?bN{uc)}1t`Y_?=g
zRr<c`J5=IfUmiTFuX1(kJC|&3efN^h+wYhe-~QpfFOU9a{mY{-x%x$ax}<*5UtRLK
zZ+&me&WE3z`=bBX)f}ZKn}0O^i#^}Xp8Ms~tDpP)(;L5Z^JyiHWv{l%%U|79J|SK8
z;z0WNOX(MW(7WRPAIw|v*z5nI^!V$asNVUbSCbF@@V5sIJb1F@SoWpAzOwXp9N*jd
zc$uSm-V2*Ej-K!AIqazK?>TJfpnG>O<A~pJy6!OcXZ&d8qQM`nv{$#DNjJB?U)i$#
zj_Ua1udBX%=5Nfup84xW{i3HYYFzYm@pIo?b#3#T-@o?7#-rv%H)ema_Mg{1$?@Ek
zn>W7t%b#sL5nVrW^P84Ex4PW_>P-3V>DOP%rdAzaLf5Xte{gu$*Ixf*dF2QGqWq!D
ze%pQL^RFgr&~?p&_m|Pv{=;8iQ(86tX!YxRA1|Nx%gy$@U!GP%-{e19=XW2pUHU$`
zOnZmk_ZP+-_D?JA;7?ZCQ@Up^x+IyoXw<uYT<G|5bL0APKV2F3J(cRHSwG{S+Pri0
ziMQ>1WO;pW_*Q+*ioT5%KUKPS`5k9}apc37PqnJ`=_i)0zGvCF=G7}7t4>dr7MO>#
zu8;0=_7lO`r?$UX+P?k8?ERnkZvW&*k2q;?culGA(bcxn_)D|#?x(5;nU_lcQhLdr
z_jdzk@E*4AHQ&))-}{c_E!5%g=Hq4bI$nB7@9;Jz3`T|OXis`dcgb9ml-$lo&h~r5
zazD;|Ugy>LdkY8fn|r;N2mi#?Go$BTbI)fUtN!elW7R8Gq&$TD$lAm@+wGmbTO;lh
zuJrzoKXcS%^U$G?WToQuS?R<*|61Kx`Ac{1_LofG2VX3${JX3)cn>dn4zIQg$Lb~Y
zvWGSwxBc!5*;kg`U(&vzPkm1Pt)8HF_Z6<k+`emM-OR4Hl4FK$XRKOcKiufEuNzXH
zY2NOq%z_4o8(eLM!bHnY&7U3{sAt|ZZf}^eQqdQVE3PS=JREAf%;4SsXt$3%>OV4a
z?x-1?S-I%MiFydrKA1mUGkEu!fh4W0&ZfIYcqMRX(SUWuJs~}%;!{@{Z6xWU>YI+>
zQRX8TrEeU)XtdZ$M`v1Z8M?hSBHenW`x0}9NzI|j8dv1&a(vIu40sMRSmPZ&KGZjL
z%d|<q$<X0$mwvu}{TXJ>^(UL~aEozumsvP+Zn<ydQKkVdtj5A{;B(g@^zr59HGXjF
z$p(789sQDH2aGv(V8Zi6Jw0WLp(}MhNz4A2(P4A^`il&D>k%_p%lOL!t1lZfk3GcB
zShNJkwH_~gQg1dF2+i7zyoLe6ZM<PUUIH9S4eM$GYkFunCO9(BhoVxRsq}>~vBtz3
zXEOw%!KIq;fhZ2&W)xi4IGi+=GFGQ4WE^t6)SPgouo0MH?5JYJJnfzwAySTWYK}o4
z3bwO5D8g(xxTx<eGHJ)aIz>Hu4<IZn9u)~~UE}N)<5Fk28IfL7UUakIW@C+GwCBa<
zEQqC)RIZNX$y*|CCey$xuND+)DF-rO4~M608fREG85fy)z%i9r&(zBioY7|q5@DSb
z9#@nMSlKET9*>;b;+gN9cw4f8EKD&;Ch+umnsaqj`U24MYeXSdJ;zY;>`rXI(D(4%
zE$oM=<;xN?ktU<m$KQ?>Cr~T!*y6ylYgv2GZv3M)n7N7jSnGR}PIvJ>b{z_7#w#Kf
z1{&sO-<&Ydz4+K`B;uZ@<&%7e=*6@C`~Ih%oA<5Xf2i<E<&M3ZzxlN-C%y9Ow)@`p
z*`9xW&yKx6<U3BMKgDm?J@?|oPv3jT%Rl_q(`TIi*!{~t{OaG|@Y5eZ_3|(N{JGN~
zc<c*>9name>#X}<d3DL(Z$9GJk1Z|VvHrG)uY2&RSMPu5)g$iv<1O~7AKte1-S<DW
z^^Cv&#k^a7c6#ZRAAY-W{(VnvJ^htm%)8_Hlk8J>KQn&Gi%)Oex`ppJz3s)G$3F4Q
z#?AM=ZA%Dti2G4xwT<==nY-<X>Q%?gRWs=pnhDlQ(+xH+RQ08gyD^I+lZRYx$><tq
zT2CKeY~9Qn;`UOrY1~YhsjdvSINO@3n%y56FBU81zLqNu)J$n--^}>#zP*|Gn6cR&
zKCkA|>N(m60K?1`lUv*)*<f>^S}b0XrFZk`&z)&`J|DC(?uwGR+n0*Xv`Pbkz>8>c
z=^Hys05dH#wb<VSVmwLGJd1ns30~~lsox10jykYE3)&U5#TrN!qr~vKF%<jALFS;W
z_aY*PT&hdD@fB8kH}lIny+o28Gsv<vn1Xx1FUQZMdczJSS)Bd;A)$il@bM6sCBb-S
z$ReJYrnzv2uu09=aVL(S(@J?8w=$Y69?gp7a1TTtQyIYX#4oO~J*;8(9(qQ=U`dPX
z`ZFEg+?DQx?#aMb!^8|5cE;NzmK-)yNoepb89Fa_M!4unoJaQUNKDy_!6MY0=?_39
zKN?^BE$KlEIcq3it2xsw+Fo-^W^Umc8Ajx}(nO<5$|pQ}1;HX&kDl1hL8@<sPzPoW
z&e6<_1BoX-!>~&&%mm*nz;6HbX>e(vndh_OoreSB19fns&_)~p)wq<P6}+x{8HiGH
zP-_a2WF?^b!%#_^#7-ox%O0<GOd2GDY9Y|}NqzC!TORwGG%yEa1C!Leh0I(`cEdZB
z50qOc8~_`Ok(g!J)KDK}_7S)Db0a}_#*%vcxztF>Ne_tnlyJN~H<!?R74PQLxk=qo
z_u9UD1(82Dzg!niBu^3q6tB2~v)BRK=ct&I=+=d|&XgSK#60{)0vl{N5Juja8$AIf
zw!<p=qb`SG0~O?sPdu@)1w!v-ry?C1d>C_CPQtZJfi`H0iK!(u6QXc78l3|j@&X6j
z&dNRnZ7wJ{F!2t!r`bno7HyA8Me6V;)2|32lVH&GBhx^Fy(CO?@hC3Br5<W{Qf=_$
zXTk6bwW6!(8Pi+S7WrBFuwxU;i0S4RNg=MHG}_R7-C64L3eb{1n;aeIR{{AjxGU4W
zTz@cGL%R<EsWxU*>9ex2tdE{*s=^ino{>%(L#VwXZ(5<+YSJ5NPvBWLV<uct3=jpG
zZ9tOwY5f8gU2aHaohy!_D9+(|LICrIaquUsqo<iPS#u_xu8D*3Q9we}LIACv!17T|
z2OBO6)BMqz!7ms+O@#n(h!`u=b6Td@FfK)?bJU39WWdowa#!5<VMb|RoXTW~H8ro|
zjFHsV7gtN1(Rc+o)}=brGt~X9>_G>vqcIOjfWZGclb&U%7ciUzP@W=?#&M$|K~5jQ
z0ZS=P=foPJIvkZ7=#x%frbH6=<Gk`kq7o-%D9RN#UCF~~Ae8euVXq1z8peooY{P8C
zCl+?_;if(r#90f*9yO{YFrwQjj+_h!%O8tQIk=>gWB8xgWvNe=<P3ezWYkWUoTLm$
zouL2X4a8CoL>J8=1V}b4uA#sNY>`oxaW^_Q4M|MkH#xXYBswY1BewWknP3g^;;?o3
zSf+v?h7sjVw#(caZx=~0UnUio5?}s{DqDs;Ynsy1OyROFb$5y&m@X2*(UEYATca*E
z`mtd{I=oY7ModdOn>y2eKW)S(I-LvIZiJjOiYR^`knKqgD0m~<w~*s{52uSFEYUr5
zI&#UC4Q}a0(wI!ACyaZ<k)e&3GE>31UOT{}YG?X}M3g#g&g6vJKyoYUQM$^%GuEAh
zL$Kzk!=LFxd#6l+gW(BU1-nANZvOySdc@8G8N3@-TtoATlJ+YZeY-P4H$~iTg!UvS
zbmb^B7>K0KsvF=UK!SqM4Vde(npcBxaf81{`;s4uryx}k(_&cAo~9EtH|@s39O0y{
zGqANh0<f6eR&lDt=esYmN2!_}j=vl$>-D=v*26U%ovjv*x2~LxtO)$3vNOIhraib7
zxC~fxC|8W8+i-)4zUN?^9yrbT83LU%9GUn&HW@WqHt`Ir%DypSP{2$HDP9lYjXM)2
zz4@{+(<WQ&e9Ak**(4uWWaDK&UzGEU(cSTj%-#^mdS|Q)W*OT=T{4~yQ<u@KF-F$S
zO&3%(TV14?bzzg0OJ?=v9hv%$xOa)+?Lwux@EUX_$2x~g5NS#$pt@|LpZ!mY#_tim
z>9e$hbe#opke%~Wl}L!qfTshVgMrt<nqJJ;D+37Jj297zd7)L%BE8>ItH_y@g9*8j
zS;RFGrBoCc&<W=ej|f9_3;6gv<%UHUl`?iX4-J)?Av^Bq40QRVO$;uvu1!tC<6=%?
z_&S`<pd3fEhmR4l%C%R7{uOd`#9PHdRMg#zNk^xD_;-42OU*3s7J0|uRf2Bqd7_BJ
z-xy=G4iOV5ofx4|yomEeWAUhKP%0Y2OT#u$W-QGwUNL(IOIRjB2ZnF7hQ~iRRJ)+C
zV5$<Q{l(<-hHaz@#j<Hgi?%W*fs1RPL>%vM19IUSwW9nGgo5JkR)L{GR20U&TTKso
zR-f63wj0a9UEM@9DX`$O6pPZy63``G6kwbuN!b*!b!EwJUq6WfS0A>d=DEii<C%b4
zQEe+S?@eHibhJ74g?VnU{zRFkvvo;Ai|UFgt)Qz$!5)s>4@DdY9(8!)t*B+ul>!N6
z2E*9EiKyd<;5Y{`C>;$iI%&EO1{J-_pr>O5qN-S+olCcM`j=gluN1}rrr_cg;l#L>
zb99L_KC?3+rHHzQNqwBLR8)uMZ16}<l-T--m;_nQ`-QOL<V{igbn=+oGz2WTT8R8%
zBjFf{lr^C$8#pM0JeYGh4$lF!ltP^jM4C<_5-NeeBR8)^&Mj~0oG|gOEdv@pS0}9J
za8fskak16Np#-jC$y7T-050;43EF2EX~g$~qVwF|YLkgx4-2$vl>}Tk0@cdZbKn39
zslIXyvZ$h;)!0Qs3(;sKb+YB(f1%xipqQtOvLpW(GCX?tH&I`<^8D$7%6f-23L<H7
zI1bVgJUkG*4}zm@I8-#xKs^|djG!<#U7l>lpnYo0@&(~od=Pj=IcxDqI-n64-#%>H
zW579Psa&E65{_ZV>31QBhx}Wi&TVk?nb>l98bdg7i}OW9Q4cYW5Wko6mW%TQ8G@2Q
z8IkzBwWM+m)dYcUs@Tgw*Et+blWSZfrP6T-%dO0XIu>NdZ_J9U;H}$rK_yvRtri1G
zQvmQj1R{Nmo6tiD%b}R-#v<0mMC^A;i=Uw0aye7Jc_0dOj8zZHloFg+L^vg|ny$)g
zvx7r`4FoR4%=W3rwIdAbxt!sSuQg+i_zMDu_KrL>M=3dSnn#f6I68?KY6$3HI$@^{
z3^?t%SS{AcRc-kH9f%l&?w`jZ*hxi7N0!022`o#0DBIv<jF^)n8l4PJM5^OAe5_E|
z*zpw+6q7QFgncCu(jRmDe&-nNoXBu4CeDuM5YL<(hia=3Dadu!5%~7;9o~<gHKQZm
z+s+`6tz+ZvL(QgR#e9e_w~mo7KbT5210gFmm>1SFr77$*Xe{qZ=KGsWji@et_wkJh
zAIDZoE0shW6X}E{9Mvd``oO(?eJn~2Ao`^up?!!@@s3v#<@Xghydv=Mlnlnjl*_ra
zh2^+BqaD|L14BRv9X?MIi*njEj>*nRwtVsBJT*<=qV`_&MKhk`bx!lBLp8hu(3swU
zKXk5cBq*u7Xkr^0q=FJY8b^h^gNK6}@V=gCD$Pcef{pT3uST?+P)Yl6F=kwjfom1o
z5z_G&FI`1;Hc5*U>=k#i*);8q_&AHGV>42^NC-}AP=gBa(LYC`fcJYjGr}byS~!2A
z0DYWJ$U?dH_y_YynpZ|y5({V#$qBj|28KCojJ3&pp5PqNtDWT}(sKqPst}{b<pyt%
z9c03MPN$}c@;&**+ZA&<MbMm2nv6W1vy0{zB9Rt3NjqPXJ1}B%Tac!4<NIc=+bb8_
zIi$4Nss!jjkTX*R7~z1q=iE}w1N;(jAow?d22+?942lVyJ`gRsypGaNot%sz<Lm#e
z*p$`+f>fudKcVc51c9diJR@&crI>R)0Tk#ii1%F-X;(whec(aw1LtB2tppP5onq26
z7$2h|2{9JciaB&XZ}9hyQJt?x3QlcaDq~4{=i8<83bi`<s>)Djxa`!``zeW2!5jiX
zmKSkEC6P6yNoOU4jMv~n5y0uxVW+rBr(=-&>+!@xoUNVuY)&bz#5>>>spWYgD6t>-
zJkI^Z4$=*#*SF);)#aR&i`-lht8DTNi}W@)!XQol2P7`9DoxqW3W1*Lav~LOqi4;m
ztXzm%-)26ydR#2|C>H{O^bLw&!?y8eVsf9Y8ZkXPkUPn95yzQ-v4eUV9slx2oh;?Y
zYn-e&qPVGRpN?b2A4qum`%Z;pv8WC4^2t}sIT{lk>=ORmGPm6XU-#VnXbhQ;!g1I!
zU>X}%QdXjhHIq)!LD1P3hfu8s*Ib7d6oX^s5MA;Vhc+lN%Bks+tVPQ@%8&RD(cZPB
zVG^W(LZ5`w$jHznnl7u?`u!y7L^)#(x1Mb_<U3qrBxxB7cAR|IFvFe{*D}R1Y*8O}
zjHTd{aE#=d`b~y;K~SWh+rAl?cn}Hi&v`G8r)d#i_mpa;<QB)sF69H7AO1rlS4`<n
z6Yz-N%(@=$a>o0>xdDz3|6^6MCoi&Y(3BYzFzZ??s?6|i!9sGbsF5o6%)DY`$HZrA
zjVD?hY?QHX;%O|8R>L#SDeY7TVknClE1K)AnWPO*X}UEv;fW77`RxdHL0fOkSD_z+
zUvNX?G?O#C6F02^tqF(mq_Mkf0#_cxH@Ts#Uz)M#pT@e?mPAd~^+^mrUG#xVl_Ae?
z;;b3s2QdemT4eQOQ#+J!`?wyoq>12~nim3=z-Y8G^&7?&jDaDG4?m_k&5`3Aj~OZQ
zsAJGgSr#nFT0eaDdhH=<S=G>F&pmv><nG<wbC#WWMRL^@SDU>*efZ(M-&{MH{o&^H
z<tr{Rzy9~N5AS*9;pAW6by@eq^D5@%m!BPKyz*>PJY!Wd_`vYopT4~J|D)?|0IaIY
zh5u*o*)yIQN8K}yHW=DEha-->Xa^!fuOI6i4s<}Y15yoUy$3|Y0-U(0WQc2qkw)Xz
z@#EhmvpO2}QrGS!D>ExQpmou{knDzEIT|W@$q>B?i1`0KYo7t@{r{hty*{4xtY<yz
zS!+FO?X}n0JJ_@P8R`A`t8J-K%i30Mze9HJ9uDfCUfo*Sc~aZT{X6Z-{lj)>^D#%R
z|I&XPdFIL$l@-_Qv=4rMpndzcW7=0t`Qf5f`&ZaK+t$eN8)MtMugL{xoVnZn<=JO~
zzJWC@yMMTEjLQ2l=Dlb3)SI7t<Gq>JURxG$o$}fb_pRRh<O^eVZ@+fU@b+u(-2TRU
z2VQz}##?)T@z<6EZ~t}dfdel*u<pfII~N`Nn=E?$Z@JB{&iMWCx|jcH|5J0?9)D}k
znWSY7{OLdbY4Mwvq!zvTm)!8)mz(zPf8ngX*Zl3g1K0fRbEF-+|EsGmzW41<&HC9}
zpIUKX#S5j2@4Ne|1NR-Yd#4;M@87p-;fq^#ANR!m?+0Jq|NYsYz3=X&yI*_E%lp|i
zBKO|AJJ|8YhwglB{Z&Wo*fBZ%<sa?~cRu;TH+SE7Vz~R^Ycst+K0Vy_xy!HH`?ue>
z{OpY{We<#gq3J8Hyc#ch^S!d@?JrGy>4_O1+SzyTeYah^Cw%GWKS16;ga@Af;+Vy6
z{w3J(=3mYjzW3mfKim7a6$h?)`N-GyzWlx?Kl<Jy_rLXt7<pya+b^B<+HEhipLO3o
zs}A0KQ1-ucFn;_OpD;hUZ+FKN`zPez-2Y0)<@Zgzj0fONdUj~bM@9B=9__WQt!p05
zU2^A+&s@@U)$ASVy??l%bNG?`of{v`hkGZTS}SdPu5D=d*Z$ACjX(SR&TUI4rp|b#
zt>=kTCia|kiny;ocjltu-EBL!tT}VtGtalBrp-Td@9G^h?!95#85?$P3l<HRCvI7H
zS8@2ZF)Q}I`OVbcpDz5&-g}QJu9))sl`HoDzO?i4@AdW857_NnHmtb)8yhOSu6ys?
z*M7x&3I@h@Y@hS(py$p5@wcwLWZ?M^uTS$@pFrgv{$Vgsd-U?LJ0{JLUoO97%({&~
zKVrkS(<km+eL-j69YLn&o>Qdfzn(j@e&e@NL$%vaSvT+7ZK;p<pV^%cQd9o<h}_QY
z+gf|}?mn|;cN}i%`_;tV?_O=Ue{RPayDwQ7-239T2~+m|zI|x>_a<%MewXaNrfJHq
zuMI7_{cFd>duP5^R($Grxh*$;J6N%0WqHw_19I=<Lw$_4$$D<6_c7*%&aoZbpKj#b
z&$_LrVHuWGiVsec7Y8rr>oje(b;UxhH~v|?LDuHJ*1n>1u()+jofoI1WlFlg)765B
z@o;D_InU%CI8Rnzc52Hl3omb45iY3pg#}j`=y5qVVp1!9y+Ahn+q-&iPG3KF+k9#5
z6EkC(i^q+t421fvq-~g*Jp<imxr~fv5v;O3m*>RkqTwUwmn+!2y3|iIw!XwnLiU!m
zC-O7&wwjF!wT-Omy7}rw`@&S`apP;9>9uTj>-*#~uEtaJnvua=N>-m2eX}@2zS+_`
z#&*x|@98XH)k+YSYH|KN8tA*ti#zSROwQhE;sp{ICvD74d|qt<uhJ>Y<^di`WaKPN
zV!k5rGqh~Fr_z)z4UaS1LVY-G+_2@*h*&-Igwfl8TZ%0&`if<zE!i6JIt316Acr~m
zYt*t~_G+?7?#7}L7s+jqEI%2)Q<!8CK>_1PS}1oj(cEl@D;v2lF{O!;<M-~o?m%i?
z1C?A)#$c2A{FCqkkF9bq#(awL+Z#M=veK<*nkHY6@Po6O=t|>aenb#HJ;1XI`bAJ9
ztno}_D1-9(ou$SNSC23Sl{AQa#JP-NX*;Olz{fp)kVj?O$27lQRVqqe$weAx+mbNg
zCZHSr8<{ecc8Xqlrs>I32n9aB=2b9_O9L60P+fx5P0~IMR?Uj75nxtkS+dbW%1S-P
zNp#HY8&-_IThtlS46_(11Yo02#4_9;<T!7mIGq%sVSk+WV_VYGRgFVGP|FG15Y)%#
z)iX^SzX%gg?B#;&{~zuyrkc`OYloc+pbFwbHdCdu<aSh~T(ObN$S^o7`XAbIMe2+0
zptwrVJEcx5@I#2r{ZbBjUbl$#Nu?@n*R$SPV4{gUV>ffe?w$0+D+gXbeCBD(!C&k?
zu;=o(5ANG>%zbZP9c;hur*AHPe95ZGZ(aNOJx}d9a_7N)`xpQ8id6^qU3$cAi(g&+
z+57h$-1X}D=d9ZI!qojM_k8~RgZmCHe{=CU```Rz)6)mGJ@EFyhgN0ZeCwn=Pdq>7
z&6i(&V9EX$uRHkku9NmZc2(29gKu22c+ZQgPI+_3F}J;af5*Ppe^FVvf61!L-rRM}
z+i%|=?ECkx_URd+YtIsS`>nfM_Z|F2U(Y>LJF4}db?er4^wB47o(bzN2p{I-!c(}q
zdp{7$@1#k#SHcQPsdQf|rA3#9^%*9NdwXO`oDUa8#jv!q-c<RD5xd<=e0NbU{;my6
z^Q0};IoxI*9!`bN4u_S^m9}TggFP!Q{)?=5JTDuc<)Hs?d#g;mGnIP$PRVbsooZ{+
zzHlgPA0O7_yL+Tv<^91`oEtlHiuBxRvW;Fq(<PuCaY*PbLXY6z_XPFg5GSpnq_-xa
zkuY_2icun;ORPo#QbvIB3urgPG3o`r%WFuX05{`9>L{z^49UymeJ~Nl@yI7?)$9-y
z(mtiLC$!cC2{PnOaMpDBgqWKc(`6YTL~DsKT6FeQ*TDd;wW$1R0ZfR%U5>He-E4Ra
zEdd+yHr32t9O(^JRBUM42pb9Gja8#(8fvMGO*0V7eDY2!HZUO#ecQsEcmcMUl7-&n
zS!G)@DE+Zqw7>*Dk^UVw^FT954X}#rHDMIYw9YvbW#Ukm^8R}sJfAkIT9%e@l9rpg
zdCn_GXA$>!ZrV=WDp=Jf;e1>i$;66qwt}n}6)I#+h9xc1^XgPH;5Cno{ow>D__I0p
zFxHqicw#Ss=Hb4<s2{ayRWzup-2gL^G*=kgj6*DG<=jdw4r=~sp)_=@S=d|*$dW>@
zh7~cLN#8kQElikMio|$-MMh@phdV>B*APWJvSvCh#f71DDWvmHJ1MlLrOBO!9}B4M
zN*OGL0*#<xn3(7d{UHyKwA!cu@TD4wR&0&~u@LuYcQX>-%$BuzHjF4(caJJXC3P^%
zS?SQ-b)KnZC@@Zkpar|s;qOHVvSq@va+~zWKk)lyG(=%RjxiC3QA(@|%HfJkCn6io
z9zilztW~K(jX0H8SOHiR4LEQa{8nQp`hx;JIr4(!f}3@lolZEd5}-?~UD5^QqE4g=
z%;+gv1GZAZixuMn$5VnaD9{=bU|LP{&X`o%8tEblbWfoOWzgL&d80+K17x%*l)c_u
zqB5^RMZ_iJv>b$}K&&G{YY}@IORR#B^Z^>2gbIYhIT))nW)Tr7<a~Bm7%OQK0B+sF
zdl`HB9XTTb{n3E+-vs;ZCd~>k6!rH%)`b?K44KkKQ{W?je@@V*!bq7&^3d0_G%|pK
z$wN|1nW%^&7z4?6GyS-l;<SizqNrL2oCCc91{Hvb{Kd!(bkqsQ6P&>SIDInhh|@Y2
zDkp)F1iJlhXsl=KkUA*_erSJC+@SS>lrWvafSzEp$ULNyxrnM;dJWx23-j4k0y2_L
z6B|vlA%{~GE&OImJqizE$EwLDqSB0t^9>N>l+Op)&zph-&NFSwj{N8fGJodDw_RLz
z)2VErciWJr>W=pSDM#Cx!!2?SbI`E8peU7t4xpeS7!A;Mqf(@2p3tDy$f#M7cBv^t
zE-Mxn127F?S=zB8qddUy3QB6{tlv7@tQ=_qbpd_Q=`>&v-i67%G=+g-*MMf`aX(?y
zPem207Q}G`M@JXsg5~t9>es&r$y)Mxp}~hLBdv-ch<6mE8b@Sg<=r??sF=}=il@~A
zuvmPuGHslOy`cKO9zC1)9exMU$e#;CR~8p37e_T&9B!u5@CGRmicQf^Q-kzVq1|j0
zC?g92Vi;$fKAR7~7|=j0?SqX*VX^9KLMnk^5T9CVMPoTC#N1ngshUhcRb+?n4G}a>
z(NfpZ8gZB)Mk)iM%~#ybK%x`+obPcE^Pxnzr=p^oeyN5nG^SNGN;Lu@9QA?$X55w$
zIL{0CIzx7iM)i=(N!FWO)uFMfXBZl-bcq10(V^7<yFzzr!1WR_=rEPlQ#3))-DP?!
zyl31P<1!FvUW4oO%+pU^CO~bOKP}^@Vo8vG?i1o%dH&QUiMl*@^j8qE0TVZmDrhQ`
z;rpCHw4K9a2AdPfCe5g8Ak-f3hz6TzavhK$P0*B*t%eS4wcs8%REw%;gy!ZaBg{B_
zORbz5G~ur@dh96r7U!It>faoJEK##kQn<*1_oK*o!u&6`qR4i!(>uN9F#E<H(OWch
zNF@uMy+i1TJTzxw4N*tGL=U$6L}M%sMz9dcAF@Ik2a$s&TZ%e1#F>cv?Qu^KuIrU!
z*=C~Ggn_bbw#}wBl^KOxO+mO5J%R-MnWsC)XpkQaTJ_PV@t%bln#DT=*vukvih<sc
zL?6(R1kf{@4cZFOTad9}wC#aF+N#WKs6)Z{e<HEo_rRz%j^z3pg$gXeL<ylreb<FP
z#SNGCSug=~fg_ugN;u9-mvE*a6$c(3)WmZH$%BOnbFT-6SrQPRH-s0-{JWAUUv0M$
z&lHj%uBAQjR0_-G-;dRM4WY0N2Z)0O>eXVW{29cQ<3|@UexBr5l@Kyz{c>CodQL1O
zjMhO^CPGFcT;Xf6TF#-eA@Gv%6V8T&AS9xrsqdvFlnRy8A<%HB4&Y!NF|WoU{W;a;
zD2EQOr=={TgQ9>~XFmwZl?s1F9idW4T(P>s^I}=NB3ZS5j?twbf)2bC1{@3FbRcy?
zz@R#mjEH0|Fp=oV5((;{L3n)xCRyBI$H5wZ=IKw*Y6xTEAfcojDIP5O2DIxaSg{UI
zZM&RG1-uF&Fd(Or3OM%95@O=~{y4~x&7^b}7zoS_&eJGKzgh;{5Gn*w^ch<*Ybpz1
zJ*^h#*N+C2<Dwdd)96|wXAnh>HI}f3Y$3#}8DD{<GxH5VorH>{0+D1KHq;VicL$da
zq018fCEuN?(WXk|VE|2P&^9*)oa%veKQPk%Jx)jedqSFWNrQM<i)t)JAg=*u7@{81
z${!f1A~kcAZg8xaq9Ms^L8L;EIco$opY=)FhzVFcrx}y3rIl!~mw+T+7yJh3_qi#f
zp>Vi_p(V+;CL$07oG-#6AJEVPVg0C*f?upz&8u|i!%>p8nglc?Pkfiej7pM#Q;)oX
z@mf73tJJ+V)=nhZd2&OjQM~iP#`!TH#<42)NUu~RWreDWL%=Mo;lHa$SY(7dMf=)m
zz#bM_qZ;>#>JLeOBD;0Ow4Ul|Q6Ap!U56WTS^hQbBkDIysnyN}IPa2ICmcLG5>HY<
z8s||s_HZGMd<}^sQW(+Llmwhp|4?NJTds&p0kXrohd)o0e8zFOKUf06NdIVTmE|=P
z;47GI+_8B~!m&o!9uf$$L=%RRD952&1)_(*CLv#H&QrTYI%mBO5(eDnI$sHwIg}HI
zqBhNFZ;^(&ECHSYc@~8xBIrzUA&X$Oh$tc!MI?MJL0?5DwGb?XrlBoM#HikqDWZ|V
z7YZNJxI82#gkX~9i-vnc@Z=oM7tSU<nyd6lF%oDadq{@8^HPbr0VGV#uEE0^$RbRk
zL@k&lBBB~@@F5b|MC2jD4KV5-wjUmQI0Lc~vC`=@!Ky=jtoM9^5BcJ$6L(jKA*q!~
z5Ik4&0YtS42A8`ug;WQQ^C5NC=zWHk>cM$8$*fcjU0Kkn9+RYcl0!CG7cvy0{j&CZ
zpVZ}D&%-DK&)Xg<BFSD%yhZ^IH6|h$-_9;9HPV%h^*mfd7N^xuh`pO`P_ld^X#}it
zw!Q@#s3dzK$!V+_E5FEcBUw_`YS5{}dWows{Jq_bu=9Gp&;uc>`e*Dkq|&aT4VyqO
z%o_;}%m`Z_W!j<=u3;}JC!w{@hR6iO@;=Vh6Q-3DsaQO~KA}@xYt-UNKmb=A4+h?e
z81GoQA&$!9gv7rGo6wS|0T{a^UA>4Btg)<ch$zBxB`kE3OxjsF@}Jyr6DkFsjpsMW
zCW#05D(F;hd<a(1jeye|m<D%8NzTtrBdJLqn?w^0Xl1OwnIvnYx{YGJF8s(h-7w{M
z9h#BX5GOf_joiB`-soAJe>?o%JjMNgzyP?B6}i^H^BkdraZ*3$V951OutXp@oWW^D
zaSj2gRM#f)2u~Gbd^BMzinK`>d=f}mkZ8&$67=BIWz9cQoG0xBrvdAS?8vg-qZ()u
z{XUuc?}WobgLPb<AHLyw2lSZaOw*Sy89{0lMnLuMMk4BuaG|EozB9o(jU~4M1iWI@
zGm1{Y{DZH|!5QNx3+IS}vUrMDR{S5Xhl|us8=vgAw@klJWVTJfkT(%yB(A<bMY9@E
zlcE0}46Z&;^ZYD6=inKpV+ir%0y><Ygd72#+X5nCXvvZyXdAXfLJR&7Xfk&^o>;|C
zVA@DP`)l}}B&M4XOfgZuA(I&)Qs37Lf)TKu$TXrO{f*w@8mPo`jUqkPJB_7+)pSY&
zjH)214l$MD9YE4MAd%u72;}<5493A&Sb<n?7n7R5GmBQn=q**FQlvGcG!3%<yBOz2
z=0}~*l^pLdr1VVFwt`1MV6m+I*e5q4y+3bRv_8(~<JuHoF%q$`vIIk&d$ZUxF9(j}
zuFOyoo{3<~oH%T`-reOK`)hgRu86W%0~m56KVVAuY5mDAX#cAqw#u!o8fua^`r=!K
z!cF>%m_YliY+)B$D*?jk?H9fs2#hFXLXGP0aC2g{Wa3-crzwO!*}t4fbz487p(y4a
zYn2S%C2UrL1`E>>+iR(JS@Q?gA;yrS@xy3}|2+f;;>m&RgS^W_?}UftWqPRPsR5<T
z($5B2O^*WBMah{b_1T+g2-I(~tsI~N<s6mr3P4kEQvJk3LzaLnavB?eC40_@#mJ>t
zkYr&gnX`2?%w3ix&XA%{Gs+xAC}Vb+OJs6GrnQ*lQQV-h;T@K^v(PaNonm$U88Qi5
z5WF_kxHjb}>bL<7gauwop<^a*3}`mMEQ?c9mtdv}Gz5<7#3U#)!Hd}Q?NCAPOa(cQ
z(FQ8FqabfYq!4G+GC{4K#QQw%YTX!GuWQgqWwmWQ{kU02_6$#3J*a1hKARCaD_T~0
z_JIekAC@&yF1pxsjbAr@_pWW5maQJ>&$Ub$-@SHn&$c_h|3GDETRv{TCmS8tnO?rt
z^k+5&Q_YE;<4QB%BNvtC<ah6!dPi=?yTcv7KJthaFD;YZ!*hbI?%2Ss`FPXf1uODb
zY~Px;UpS_@&a>5?Kd)$A+`HS<*KBJpto~)N;)}E9PhYtrn7aADn*OrchTW(0sji-i
zU9fqR>^$lVcMTu)g|k%NHK+28oB#a5w;un`AH1?VdN|89>9s8n|8@6o9{>5W>+k#C
zW!K;LlZU_e`CmW$y?^~&-`dx*%h&F>a``VO_H%uI?32e{o_X@vd2?odD9<%->x*;7
zy!K-GeFwhzxp(dT%RjxRZ}>vt>R$BiD+`x@`^tBJ`q-zNm%jT?XTSJ(-;ui>?>qLc
zuP-}!!=IO(am|+=n!oBx4}G?H|Gzio?>{)|;I8cP`*$sDE4*}v<?4Ou{2QYBj4yPl
zyf6G(<^97m`~UNmA3YNN+3b$~oO^BYMH_Z6e*7oPR^NBSM^+>6X+Qq-<KO%76Mbu!
zPg_3tde_2VPISxvIPs>jPaS(?_|&ogbW!0$`4eV-d|u_5-lj*t^RZ)}yyTyo?!El8
zNA9j&h>mBEs(kyjrX}mozUYdNJ)J%MiKkEe&XZGuyGE~w@A~te^v<u}efBk9`tAHx
zNB#1%E%zUksRs|f`|Vu|JNLhw$h+XBXL`3pP3#8_^yt~4KYd!{;H(>NeQDMW4-VH?
z=Y|IdOeMH^Wnc5g#S5C-e*Tf-k>3fo+&Hh`ZoAwL-uXY}>+jq#w?F)e^mm?m=M5Y0
z9@tVFDAbP~b@SF^gYx$DoaHwJO~YG0^q$>Y&Oap{o-@i0mxH^?kDRcx^jMQDSTL`&
zAd`P?LGbS3u|bnvbNPu;^|Qf(Cr$T)wSAJBUOn^tnN@$L>4HZ@F36<1XD$~Rt`Fqu
z$c5Yticpp{j~exnV%uqdo^?a{rP2+I+svc(`r0r1nyXVP&3E_Q-Cye*sBg@K^%JHP
z*0#0gdV|j54MCyU-#IGo4_nK%@~C*{MZwL;-HF_(1(jYgmArHR`=2(tkF$}T9u<`*
zG~c!EiFYq@kA$W6t-VLd_Di07cJ`>+WgT*XDRs}BWM#qaeWNn7OpuFu+Zb~_damfP
zG0Yv&jqK<=V$7`F%n#dVma_JUza15f`H!Pk&rP)t{if8~CY7*WF=4$UwSIF@55JsU
z5G=oILF@9Lkrvs?oNw{{k)X`y9O{KNQR-N>wc3vja$mfK-^&-CyLro;9#;)b_2#gn
z`>SDo^iYejvqqcJ(W5_e+fZTWlmg$J3(B_8Z{yKJN2{6WRN219#51K3wzIDsn_|Tx
zTPhcAA9ux3!Eyg_RDYq=-c~3@L*K20q=)6eWNpy1zK~wfH22m8N6uZJ>Tip<D&<1?
zxVU5m*^CRn9OaJgh;tX*WTmpX#;>jKsCHtOcoLtwWn6#vEz)m)*A?5fqvggS+d430
zhYJ1rE7UlJY&EW-xtlpB)*;x$wxFj@;Zp50M7b}Zy<J>Rg=6uJi2^?FAZJ<3o=v%&
zrirJMDd08|tok^=TE_yaiKLa{@pPF<;6F@9>2RQl<7BFKNGHco|EDC6*}~6=3oByv
zH4=V()|*O&i$wQs^(3vIx)XD&XPzp&H;XiV*9%OTKl!{>!zVlPrz6E>xqLiIXmSuI
z>BOB_#-h0unt)5`DNAAtW9|!;POlvG){WMYI4y}B0~+@?fW$fVB`J9MTYGJDz3tPx
zUB$(Z-YoLcW<u#fZawimFa6zmU|9cd1QWAzAfL<mS&<{pbY3cf)K2oGE1*v;6D-f+
zYKoE0*omQRFIxr%xkgwDlG4duWsRBcdA?6p|17IJ!C7{&`J7FxdgT!j?E|UhVh)@m
zvefHWPb~Z+xW7Xf$TQJb6ld#$ci;^KahNqRDl=BmEEj@_fzGvY)`iw~%GOe#B?apc
zN$kwLz41ojhqyuU;jndXr^t)n25oI~VNEG`^+P|__c-lY`T9fp%Z&CtzrDM4%jtZ(
z?w*GZPJZn9WA^YKr|qYFb?@Tap5{GI&wu{$13$Qa`?nw4xA3b^uR7<c$w$1+dz>ym
z_~wBfUw!(Vt9Z}T6EENLz>;&Gcx&Mwt~+PXuYcV1*sfdVUvbY9*JYnr^`1RXOiu56
z`Ih<T-}l&cSAApUNqf$l9PB&&iO;Ou^VoGCcw+f6kN<vE$G*$H@yg2m^WI+d#B;}d
z_4ii=BD+I9Llpl`<cZ(!X<b3hOw=EC{n9mUbQ_u~vv?>HJ&fq9=`sN)pgK*Q;y&Ys
z0iJrfT)BUpDfe_58FUjeaGTHJ=?Y&)TYBRkO{rcLJHIn9h1irfhiUuJ%^6n@rS|yo
zJU}R<C2R_8N}38BvM9H8a?G<J)!}keye-0h%}u9{p$kyxChS>vs?VG?FozO&4H5Ew
z`Xkt*8^;hgiqd`tXoECqzz6A^vY8$bg$c?fXzi#9387|*d^~Xo|NX5AOT7d_vF{`t
zLF2<i*^GeEKm%cTrmpYJdGe7YH4Hdmx=zX&sf<JR^}I4^eOS)h$hA2(X*nVjPfEoF
zh*|kMH4f-IN=+Zm7?z6GNxfNDa%H-b%So|Yz8TgeayEI<kngg!8J^CGN=seqEOt}U
zSvGAIuZR|GgLY@&_z8hA0q@+ha~GhH2Pv~NjqDENW~?XS<u)eY(rmN55!va@3fk$3
zTo{HG!|x!<80>lwSy{#xLAec~+QHFkhm6b*Im=k3*C2#(4@zJu$txyjGQ6`dC0laA
zP~1jwPI#kV$naLffpme<!z2@0#4ck_G=*F+)3uxSIxhm?yrx4<U?bHl#6T07IQGM=
zLIHvu9#s8DHcw4bQG*B}fhdwQgJMo|mK71f%Syl!TPk_t1+D;G_}xYu)_bs1QZj+z
z^OjZEl6Zu{tD-EaEFy<Xg|HY@q(29tzTPT8X(Qn*mr=wW$fS}ZqOs0lS4;~*ltUt~
zhm@9?{&`d?BS)+F;cyu6m{`&!%{>+4*dsi*i$W*0U}P(@+ogDelS;*;RlP*wvXN>F
z=N1$tw@Tjfy(rQuRg+PSY4pd!zYsZ+4XTvbLKQV3Zz!RQvv8`0R{NI(dep@l{azTq
zDX!U`z@QZNv79yIbDi|nD$^*qFt54Pu+tm+jnvDWpr&4t3>4{oLt-`ss%k4JH}9Xc
zZ<8R3DRW^MKcrd#blSD}?W&HDC!uJngL({ri-Tbs@P<v!pdc4I+al2b`hhFuhFa7n
zG6!`B8|{z&B_kO+Kq}SRnaUM})J~eO#ItorHmg_A)XDvw(V{cRz<qSUeW`_bFcmc+
ztEAwmw`o8Q{n(a=*ky6EjG?!YRjkz{r;b1Kq%Bx#4;PTJI}8j{772N&ksdkTEsC#d
zGA^JA$!~}=+0skED?%@QUZH-4!*&G1ML}v9VMtft(|SYd$I_}E2#eEFe0)8X0E{{U
zf7IteeR42w4#rW3>NDu^X%;4ts+&7did2E9uP=SHij|hxh7Q`LT)JF<1c(r5sgUX;
zm3&v#5<nM9;cG^MWd$25Ca@}U??fuXv{)2GTkS$#6b2Rn*6_ofG%p8IiP4D%J&!Yp
z$%QF^W*8#8yDMuP9$3iOGqFCAy1>ay(g?tcC!+T&H}BZ?3ZqdQl!gXXrEVy}5ahU`
zIP0(>WE&-6)q&)b@huoA27gm_h&Z2bQ&-};tatb(QkQ|pmI*$6Ob=CbhiyT>w8ykc
z8H9(rM6AK*jzqnm6E{`W2H*}kld{GU9H2@eg+?}V(gF+KLYf>Xr8SkF5hx)&MvL?<
zokEx5hP6sLbfM4`1q{T<E4`?ijOcj&W6lLlHpF$$C<u$_(5a69^?ry_p~d_~;Y`;f
zQIs8a;*g}|AgA+uDivFCl{8%hLE^Z^tfT$o5M(hcsn|3-UiV8|TcdrT*dp7Lm)oe0
z%V-D@kvQ!-nC{zq)EckmSXVe+Eu^*&6+vAT{Y$&BihT4_U!s<p6ADfBh7og52yLny
zci1+o)RJS+%!+Ehuo4XDH7F0$0mm-nbg;KZb>d`n9L?vnX*7)(=N<KUyaHue`ek5_
z69QXJr|uLL;U$)NF?OsqR0>{I%h$k)q12VPMLu6nu+SG8*`BZn%?V0Muj(SK??aJ`
zmx>tE6uaBjDyqlEfr&WKn+i_mKv^nU6GzqPudTc*rFp$_m0BjQ&yK{^`yvyk)>$;K
zGDx;Hjk^WSH5*O^6LwL6+N7hc8dB$&I!JR)ZY~D3e!B1@jEj(I@;j(f(lYVk>&cKw
zjs)Hr3HH7pw2?)un;(Qv6qe~7x+yg1I8bJrgH(hOtf1p~TD?0h>#XnGw`RPU?UMpS
zbCkt|^kf;&2<snoOaMnv!~W0>1TAbyRW6F6e2bXl`QG2rshi>o1*UmD!bD@sfmEfX
z+r-YCbTh3$j~*Q6ePK-1mNo=0fIquKdtz_E+LY5?LU)L$zEU{qjT{PU>I|M@kV!S7
zh&&Fxf(g<Rr{xCABw8gUcjS~tZh*IvCuNJv3c^(dHqynVeb-x3m)!fP32dZDfspFW
zgU9pEE@mtTBFHG#Y8Vax4E>9oe1v<^kYa6zA?lQ$28{Bu1h9dseI0d<gKLN`HN|Sc
zst+^oX+Lz@(<KUYX!0-qY|e+NmVyc4?V62*WMx^P%b`qA^M&fW5Vdf}(6Z11bUwwU
z0;91Y4|~kPkTi8$PT-AHRW<AZo=*R@d<rK@iRu8@EJccBB7^DDFOzFNkJ1c2Z{$D@
z)Iv*K>okO;lqM!mHmQzDJc`l0f!|fewg5#+U~%I#j9syK4O$Hubv%TjjA|#2p(ele
ze3X|Jn1)bxbtT6f#!B(ZB#Twe9_HaRc;f<uL-LWv81P!KBy~XE3NH_26Nj*Ailr8b
zt|I0!=sZCMmysPg-@k%5t2tC22~;3TFhi!H;hIO%S6GFR+i*_NL5OgWSr8>*ZA6@_
zs`vzAer@F|P*);ow40!5t`>^}u=M~7P4*?041ormXbC9O0^$G;;k=#=5xO^)qNv)b
zYFwMa$)K;Mr(<C)p@Fg56i2$A!<jKwSJ+g_g776<Lr5=>UJ?y^FzR~yhM!jv_!oC8
zPEGTZf!Ws(4UGOLmBY6LJs^h|z1hItCd`rFr)yz{=&VM3*?307YR@1E%1PvqtM=v)
z5XR03-P*HKEoypXH6S6b;d&>S(Z2jcD69EBIBlJZo{tCU6dtLI0a&Xc(T?s=s4fzK
zSao^CbA*gW`So_yPoTn0n98mKI8Ai8fJ-_@5_Wh-OR!vxlJvN>@H{jbn3@Wopjj!I
z7x9F3YM?wdSH#@{ArDdAHF#iB6zm93jf9jyx~I=2>DuZ}`@JM_C@8=wwJ(SuWoa7Y
z0!-3BVFU>nEqR1a!&;igAvg@K!P{z5L%gJiC3G<zGZmIJgKsW*XaYg)6v$?UL81k-
z1qe7j@1Wu+Bkx0Ki0V9KG~l6Mn)@{tX&>+~aHwGTLCU2i;M=4oI+rKnal<?4^#0YS
z3AcW_6?aJTeu9A(o)pg-LSjfI=<?&k!q5^;ASqSnz({)n`LZL~lm+p6LKxyD#26I?
z%u5so)`yd|Ji#Pyf?NcN=1Rzwj#z-n8`N~irM_XN_Je}3r=U~Se3*B+k>Q$?plQ?_
zbVEzXHBy*{8Za^;HN;RXh5Ia#(-;;<yOXmjXCyB6x>i}71w(NO91__OABk8^W6kaG
z{s9_Ni8YP6Dm_BreEIKGOOldI?;}*OJq$_MX-0#P_8oFrqhw$XRbGWlN;lq~XdMEl
z1V$aebHE0W(DZGO8G?h;N++CrwH>d6@QL2BTIt4Z!eK0|dK$66qeTMk-3r(RN1B#N
zHDF?_N}{O@V%#D=kn|f!#OZAO4tUTK;c76{SeZ+EXrn1KSEG6%fn0-<5}dM2qHUx!
z5{y<v^`t=1sBhH)bcP3%5qX(78i7NeH7dH&!_r%q(4QZ>(YIjW*^y4b13}2Fx{9I+
z)#FN4G|6!pJ;M7A@L7~Zz}IvIb4WZ|l3uC{ay=Jcqy>|Fh+Fp|i|fau2K?R>KNsef
zr!n|-p9;4Ap8)lABU<swVK8VzJ1wRG4xiR+=*enky`@922AXt*azmpnNi?Y1<SVt#
zh_&cbHR|Ud;|VOTFVe@n6Q{7N3aM>#yifXJF`TL#&@&_|M56@*o#GGaPnDL);ULjD
zrvbz;XU50WHQZV^D2ZVOR2F|c03YB++^SFcRtx4oY{U=o)U*r<i8$(m`Fo&$9I7OV
zp-qxwXLVSVG{!8U90#=BTp~T51qC~-qtTGU2y-)H{#Aa>3gR$;<KK@hTLSIth3{Y4
z<*Pul(9EjGleQD|amD=|FdZ8$(H_E96K0Mw-67<lir|=Ed^I%#2m^nDcpjX(elo<@
zz6%)d9^$U=JJzZ+z>Ng(4~Ly7|A=3|j3k#;dSCJgrr{r=XpB;8Nbm({ZLO0EUIQX;
zPex+iw^Y@QV8TGW-jbAfP<3J&iN-k%-L}%}#-Snv3?paolW9KbuSAV6o<IWv10Tg5
zmLJ(%l4`w&UcFybx28_BI)*FK0B+v<;@mm{RwGGD!pSMdaB1(Q9v)m$2!$Ok*(W4D
zJ|Xh1#Z72TVxK*8<I}uDS>a(Wjdg%e@n!MzCtpL4aScJ7kD;BBDi9Boy9*T_^Onfh
zs7^vHQq?n0o&LTml))Zom|AY7;t-?;Z!mLJ4jTjxOphXI!F!{?)Vy)9{ey-h=+4&5
zta)Y`Zirdf7)HL;)^86^S9<m<HW4#UY+Jid1gRh>x#D`Zjew2_ZyM}!b)+miC_9Rp
zAnW+9f!?oZuV-QE>!X^p*82U^b~8lO?;r3`vxqg#$)JNynlTS$DGiFugg#bO<h&kJ
z0gSA!+jPu?GsO{g{M^n8pD!_?@5dBI9;5jp$jjQ^?9A{PjF3>$A9R)gNM|2iT0*95
ze}3$8eSdiH5wVNV0;7_xJtKLiv}SO&u`UlT#m#PBvOKk>5ODo$%hggQDM{CdI?wk|
z^m-dL$2BQOtvytq9aI~2WUI#Z+gcfpv9V%JJS5kb^uEA9APBPL4cuUjbtpYWWtZck
zb>f<sVCWukbGH-?ZKnBAa$`*~SPY{f;;?1M%G;tyvbvB!SNhaFV#Ap9L9u*1CvZdE
z!EYQoii2Q)bRhj(E|m!e>_c~Aca6~ma;3{Po~IL#V#M4^7hor$r2Hvf(Kpp<JXn#C
zsu$>K`s?tvV)F#e-IR*kt*l8&ySewT<=nizW&6lrzn;nIIdf8M&R7`_Kk`h!`@{9F
zy?kyQO*t#Bz4Dyx`PeDae%ui!++Kcf{Mx3IWy9<TLi6EwozNbP?!I;Rd^h;WGXw5j
z!Kk&fk2~S6*?mE6b~<qXnr>VBzvquy`{aCCPkd9?>Nb}>s`bg0m&fh9bMde2RN2zp
zlp4K!PW;h}ABvwZ6lCBpYot4S&Xl|7mZscy3a?HNFAS<<<4I?aU)fW8^TpejedWL-
zeP3DmaWC&@-#5Cx@8_H9KRNrU+UH&@ub=(aN$Vebt6Y2Rt<gQ7{lMI{kG^p0u1!al
zcWpXm^j)*xDzE?W<P&dy<=UOMKXdKRNZX$MXnOSe*_Y1dI+3)GwO>8qq_uyVKZEN;
z(t2;X_`H)ITYTy4?Tarxap>xfi(czGZ}gM%FDySb|H9G#dhvM|{dws*r+@v0`&Qic
z!hMr>$LIC_V7AEC?1fkUF+25rPcJ=ZQSIOU`ea}KfsVe%4jiTOrY@PBs_(pZ_V8z)
zdaCx*%Vm82?e=KHTd~{sSbNXsj<-YCzYy)MA7fW;dhh7$?6>EvpZkF$khP4=QTwCM
zU$p*0bJXDMD`(s#R~|PwZSw4)H{!@WZD*|g()?yKHQoD%-e0#ows`T3-dRgdT>HWV
zds$iKooyex^up**vwmGTxOC;%ufK4=z3o4LcFyju^GdVM7n$91Vfn)?7lzj@J*(0;
zFPgn<_WM5}^8Ic8eMvJGm+SMs+wMx=<)QZakDG^TWpl>aqs_k2<=Tv0qX%tz>-gON
z+<w<*UfFinmi41+*MG1i(>9H+&VI1BD(TzXH(fn%{VS&(H~7kF^VZj=pA>y?{zdLW
zb7C~d%xia7pSY!Bdh2t7<J`N_^ITK<q=%!~ef6_u9R0`fGcNjLE<L*X(J_4|T>0zM
zPg?keMPDzLc~i-Ry2|yyKhwd(F_T?>T%4XE=YOU<dSqEV;bODsM7v?e;`S}AyKFr_
zZuDK1t>x?{H~OwT<NiBmjqZ|7wkv<~XbDcX8|H64dj0VD*@Nzbk^ANJf@^+|-`ASi
zZqwB#uHAI?jKSgYN3m?3Cr8-GebAJnBg~0^OqFInl{H;;lP*6PniEf2_-p(1;_T=m
zDX-X?Djj|FT5K(Hb$xWq@JUzRu*R)(J+f(#Q7KtHS0vT!6eA~RWzp!a+D}GryutNN
zX{~=IJ3a`q<IDXU*Tr?-Uh&J8<EOQhzuXmWjN_phaq)Xa7oA&?uKS#u7i^dFg9o$4
z6;;#KyUD&bsZ@XP{m0jfX{n1T545mWYYE!Bu;*2-aQ^X+%e2XBShU=XNm+N95&L`(
zHnvpho^CVUQgv!8L}feacYIT+nvG;icVu4dPPr|E)z<#mW<0iid|uzVkgdkNf3LG^
zjdVr>-K5<r@lnhMCy0~VQdL_VL_TM_R@6<g7u&Sq|EX_%zir6YD>H(*aZ6CDme~(y
zO>2iIwG2!<{_!Z;$r*@SBpNH+n_C`A@JXG4`IFaRy!@G`|0?k|3M{4*S&J#&fC=p;
zT*dHlPsm#kQ$c&p$)L--$3@(~W3QPv-TD-?*yRT!Ik_0g;2_3V*L9JTlSyx;wKzx1
zCZU%>_YtDtVkT#`zLX}TLna=_=O`ni&xvFf*7RadeT*K|c~FE?88RKZ<FUU;4fmuj
z8}!W6c%&nbmVwMrC24C7pBEB~g*S4$#M5sF4?EHWzfYoZ&C|~1xH$FW<0-;$^lS0o
z;D0gDJi6xut#R=M_*#bEKhENsPFm47ZXy?3n5oNLu!gPea2A=0lwZsyw__<i^E8|D
znA}#4W?FV>E#IbUNN_8>hR`{CTjs7FVQ(*QK}nZON33a0kvXQ<sJ?tTMjtknou7uH
zStXFP%|c&a-9+^Q#TR!r=yiMApl8~PqP_fN*R4#-Cj{sesjsaWl!CJ!qsTcT%jqot
z2-XcM%8uYo$-#Os3Y+<zZC-5E1mVyO!(B|X;pw?em76W?U5;j-Vh35V54KAWN1SCa
z2&`kPQQy@QWyPPBau%&1m!5g*`-QMJ$VaC?_S`XF|NZ3P$?yGi_u^L{I(W~%9iRXD
z`9E&`4d1R?dEb(Q_dj;>5qB?sqkqc_zu3F@=D)7G|F@@1{ra^(zWz6-?BiQ@SFF1G
zp;MZ^vE;{_9=iIi1H1n4*K-d3_LTHD7XILY-=6!_frWose9rw#CI?UKxMlwDC%?Gr
zhfiO7(#=cG?bx^Q)%pK>&x_aH^YoJU+;YX$!DHF4_8r*s->Xh}`qE?c+jUQkeY$Vu
zp7U0Hd*AcNtiNf{(QR^ihUo4y(HqZtQr*kC+k@Pc_8_XcvTGfT|0wN4X%lTQwOT#P
zbE<Kue0`O(`rSi8I$k^b>^RE5KOVFvTlYX1yL@w5CcM9#y8eOgwV{>YOiT4fbE9%R
z=hC?SsQIG?ia~FEZgX$kl}*X)`ShF0jGJ@PyL~*57{he8D+Z-<PLFw{yK^!p=B+#S
zL8DJ)XEwTPa^~s2WoR2UH!cmo18RrDK2zwUp`n|4P-K-W&>nUe99{6xjR0NGrvxME
z^fGdc#2}<oCyWo_BIgMr-`(k<jK3lH=-HexN2{>i_d;u(lP=zMatE)daPl>=IXamf
zafh-gvoP;Tr{v4xoHfE4wwvdzHjIqZ-$e53mK<_~m~%R$N&rn5%BPS_PrFbC&(%^q
zAIK3VX4sZNmyXYe=)I3C)on#<?%Y-b86g{>l(0Ol<0!uvg<~PP+0SAPxo0#CRx3q}
zRGWlWuywlbS4DO*_&Qu9k?31WOs-(N!qh-p-hd%rb3UG;%Ug-s<XyIoAcUvzEfh_*
zhG&-{V}(jaF6FQ^+&bvJL#eN*d9V^~s<+hVi1irGz-Y^`og45}(n8OQHV&D5nvGR+
z<FE^XuL1NyL=@$dB91FSV%i!_sU2xvXgJ28((p90t-oYJ`X@d^sJr4bcsofKX|kS&
z(QZOpTQkJT9zbo7vwU?fB7uKn>(-$tlCTpJ;aTb)di!L9Fl#l1bY8T?JwlI0kOy;u
zWY!uiXc$>m>Hsz;5w61_u9Z;vMfK3~QwEpHD(9ZS7v*Biul2-~$Uo&5S+}DqAT91l
zY2!4ajdNNH17V7(fM=rU_2XY3$q`i`j;l<1C^u-Y%Hlz7PI*WoCyq3Zd!dgZH^_aY
z{wh3YL<?wUUh8ty($OiDj%ujns7Cb=n=Zw=(5R-9E@groVTD24K{hGteCwR5f|vq^
zHPw}G?NlCApRWva!z&Xss^h5=;%4g--UuD4P7x(Znz;%QZ<us`@C9Lxt*=nI+om3=
zjU%_!&P*4w#Wvp;$&w1D7^^f%;Z}eAVh9geux+4u<m_KZ<di1Vvm)ny5qd9bhFUQX
zsbURtVE;xIcezQ>c}R6jMefufTxe)ji;07re|#>cZjO_#K^f|TKs!^7dDBXTIg_|r
zA!Y8LpP4AM;v(i-id~@nm#0yY)*wz*QpZ9FYYv)fLEK}bGu4y!w00PMg%dmNx`JV_
z2U5!(r(^~Ahq8b%2OWSzw}DSfcNE5^+i>ftsx$D*!Kp~N62*B-W+YQmz^bEKWu&P<
zAhc8y&nh!(d!mj0RNq<*QvfY>)f%ztB47}2jSgm(Zq{&HswWD_r8>TE5!9YRsIMy{
z^J*jkC)|;{(D|Sx+GBd?2F~}CSc^w0Dhfiv0vXAwMgc4>iI@}tM0H<lMRIY{=|+@9
zoqMBxVu16U#8*kPI6?|Rodh3*X+(kr=_i3UpQC_FiU+4_6enk76Dn5t7JS5|OrWA{
zQ#HyW<X2*>01ata@wOCJmj-bfcUD}*|Gtso%z`6NN6CP<W^fbSsE7XR&Yn?Pz(|(!
zCQ_tq1zQs72gxT$O|zt-uGajSr_~{;ss|hP(NEB?Lr0o_VJt)OM)rB4aEj5dgXY9r
zy@FA78U8sb<Ej!m80cIRXsv|X047*vU|BM^58wh;*wOO+SfcZyz$mKANFk;)Ex*`9
z-xb<>h|wbvPtht)>#wFAw%SjT0qYaToAqlRnD(5V=_rkLx9P8_A?zBD^mHiOBT=hW
zzJhdJcC?B^d00Ce7k%%OlFdX6hLnDCyJVk{h5B3pqR499WS}fz*bZ~Z`@lzW&S({7
z5;&!MAM7JjGMx^lrNv-Uk<7}Hs<r7ps)Ec;BYNhkX3HEEkJ@=#ig5_D!O2*D$xzqy
zu#bk;!0{;-<n{Ghj8WrnoDHpnFm`?L9N?LBT)iV_Tie`538U~LbaC>+u85CWYDreB
zdy^EG<7L+C7eYe>k><gzOlpKPDq5-~kU{)%?08H`w_&t(P~03tzti3`HjYkU9nxVC
zjE1kkx6?-48I@yx0fTm2rO+bif#rg7MHgxKv4_V&G&4}jqVf_9t5tquGTPESkVcNz
z)7khGJ#^cpnc6oXntlq+pMXgjJwr16cQpK|7X{cYj*TF!fe^jp7%oc~4~Xb;9#otj
zrvxexsm_OJc+Dv%ShWEO)+hpK>U6fj21bFUC?x@WEqnx#`J$yS)HzZpK!;>f4)K0R
z8VI5PFn}E)fc2~O0obb|-;u$i$*xFBvzpnoSO=j61>UIFZ+#KQG$e9?asmot)D;->
z@>sHikx)HjVad`dO<44!XCiqGwZKv#rFxzJ2MB!>4rraB8X847FAYs+H9`zYn3SA>
zM%N>M2R%B$MPd_mXp&YvkvQ<OHC6)_-d!pb@Ss*`x8n?8+>$G6-JPNVK9*QPtc;I@
z7R$oEBN#|9-|*&(Sre?U#ssCAh)5c%;-!44icm%9WC-}Nre+H(44rbZIwA!xDmv$L
zGyd7Hrqd;PZX~rurv=ptD-kS*PRcwHQN8WlCPFrYE~LZK8?F8zs_r~$0J1|GYBZZD
z(0lo^fguldirGR{CKMsoXtFL))pdG=T{&5evDWdPo}7)m{F<X=ahM97S1;2RQL=<O
z13H^T^nocsa5Wb)k`=ITRxuI3&k7<Cux#`su_vpFCEWpu{sW#ZcLhEY*i=gxRaGVA
z@dZbmtM_S2NQ$q`NM@x<<WiEj>L*#NVGBdfYf@9s2qMsWPG`y2G+A6hMN5FW)P%I4
z(Wv!qgR39O1x1&sy7I7ETN;vx2OA*}BXI=EzLSo`JiGN8bFpz`4wIBduOaSpTIT{1
z5Lx-Fn|R_hGJ+)F%sZmCsIvS6XpOzzj3yX599~7q2sk`~5nf8emdi(Tf$?%@0-e5~
zb*g7<3b~Z}o!~UWGx|H}E_s4JjvusX9TZebhwrs#6r1C+Bb@Y!N(0i`c+OFZ&TUb{
z5`~m)Mo82T^GU2=6JK5BYm%r<JZa=g6E$9$ir4z<g#gBSKZ%Dr&wI#3c!5nKDye5|
zeLx*cNn#lZhcHR}a5Qq(M@$3dv_9maP9E?)53g%Q=d?d1pq5V0j(ld)h@2izU2Laq
z(5RJ%1h9=OiNThtIdF}(G8&8;#i|Gjb>qFn@kn*JkyW>npcB`?ABLJ-G+JFkR??~*
z<abKs$OXyBFd?Qh5VVA#HY7oiJV@1LManv`jEZo;r>GGdB&0FxF(^yHYLwtm=%YG6
zYl+$ieSv<OQOU~c7+q`v6s(YKkQj|b^3u~uN~1qXJX@`3zb1NJdue?vp)<b99+Au(
z1Pfe73+G>p!c%z;gD>9@4<S(B0};SBN}xVky8$sKFf#HS5sapLQtKlQuiL>fiF$P>
z#i|hWQ_MOIDXf2#pVC<g0~OXNp9HDaKLO{xrX&*4m5gc%{=NWKcnLT>I-0Is%|K(~
zH)`UmDnUcH2`P5L6Z@=IdYneJ-{#rL2Ke5m^#M!1BxHOXmvODj>O(-Z=0JnMk|xv?
zE8sZBqrwnCXy!yBF*O|#Sn+_-{{V+Y0AVP^xWF_dfIZNdWK}ys#3R=K8~pn8@OcNs
z=@}s!(Iau?mT>fv+OkWCl%%e_O%hkv1YS^29$DgwbR$zW<vAya?JF83WmqLqP+hjN
zR#I@j>of2?HI6x~K+oJDtlo<&;3fed^WhPB6HIdAiJLZr^X5EBHfqyAh`5G&)do{Z
zYd~pb1M6=Lz#W1nzdvQgI+cl*qRUywg2O@*a4A2;;a{Pcc<TCNSI*BYBTDreFea18
z<B8OC90qqd$S<dS8ConbV&gPy)M-|y!N{M*dG~w}MzOfAVd{O<dRN5JYcVg{P$MXh
zOa(?f&{*CwSYlm9-2}9Q7pbi-i4eEsE3GD^G9p1RLVDOY1RL@t>Vdnan&h`$8cLcW
z0M841RS%8}VuB{hs+0-BuPc3$I)+!{CXsSdkqj}_4-H5t<T832o6sPpX@nH-Hw`r2
zNUm5PN+j_D=%TiID2Gz&oTIgM{w&Tt$$E-z(;)I=KucAy-Ccorp2n(l(E=RLuA<3O
z;4)4_2^d?^fK9q0W|K(hydZ=CEgLo}VCdskwgehbw8hOGn%5QQ>1S{kLNEx(p+DU4
zNGDn955{;-5$GfVFJTB}q<aPhpY)FoIY~Fl&htw~lkuWCMJm(`PAYP^z98@Gc8pa8
zD$cXfvtvIRD_{XIT7F<~5&&Zejm&1Gx<+>E2{f_nLkS0F1|-*ZuuzVGnma#tf^bG{
zC&`uwqc;JUP)A8j7d&}_aI%UqMqLUH6LFl6!XcT-bjkQm$T-by--)7JqQ;{d9dhJb
z+FgnadL&!&sp^;{WYZ(<VG~6+@QKt7S(ziPG<%goMdzn>IW>^FI020FzMgr?zUnc~
z1_1%af8O_JUj9M7gzjhgHiB-W*Yr*($`&PmGYR!dWxz<hNK8IcwqD=Rm&N2N{79af
z6)43JVE2Q|a5%=`)61B_z)V|U-B1*Sv+XowF`}cK6<DE}4~QU!g*MG4gB8(txf}vo
z(g?pc4~$e&ygi)XsLeK%6|fT1%JU0b6WA`cNr+fyJNU)24g#J_M%IE0Ez_^@s<Tp4
zKO1D&;}^t5F6oQYu{Z{)i}C}+tyHkVj-Ljd%pSXyLA{m22MVkt0^NYsi0bmH=iq|f
zGUf(ILgNce+aayDDO)osuQNypPnsskWPHYabR_%5Z0!^%EQ@Zej4PxTB91ke>cZK=
zJu@q;p%j8vU=9xklg&9xC=4>eodJCrD{OAD0ZBoj+2oWq>}UzB4Qm3{1d=b<g@)WF
zJinrrmh(xvy2uzQ_39RWVB<bVeuZ3koF%Qrg#L#n;h<))LFmNRxwIXQXUnQWYi*Qq
zCe-ryg$VponNEFam7yH$g*7l6FV5+YXsH&3@+F|AI^3%Dyo52ol9?!WP|)%OWCZlg
z&Cp+k_u}w~iZ#uS`7PH^Ic;TW)uPK6)i?cR&4LFuH%0Fqcht`=U1fJX@ag_V^QQ*A
zOP99yUedE<$NbIx%hJy_NpsjXrT_HPCOuOLo*kYajFS&EE&kZ_==E1FNxwAQcSr3@
zM+EKJkG32f?n^J-`9m?^8rwYmUrulN#D)d&b&GZe5B3i<75c{?an;Tha?bKTbJc6j
z&AYEZ`G{qc#-~0oX=VEL2c9{iu=VrNHD_IFRNm!}i2P++OBmlhY0}DTuQ`9^l53uN
z@;m?iyWQV;an)r9UOM`+w?6gmCto;s6W1dv&s{QW#T83V+<W0m-`YF%r2~^E4bPaE
zeRfpOD;F#o|I7tv?;5^p>dV7d9eeP<KRN&4e_z_Q^opzP(wDEC^7?C^yyW%Wr=0t#
zYwwx1bjdv@e&UBqKQj79OOO7=zE4fP|HV&@x@zC@smt~)f6vPGS6;gEhgY8c`W>fz
z=!H8@d)J@d`1vRQ>y4kEvvTEM7M`=~S^wUt-qS^1@0)zp8(Sxj`|N3}&cFELRZrdj
zoei0-5B>M?m;LQiM_%^wOYgq;o_F=HeB+~!OuFK<X;a>F#c}tBi@tZ@pJ)DPa(451
z6W?DSHKlUFlCxe}diKk^ub%q5-5>4z`cE${-v856I$l0_W#xC*UHz4NhOhqM{SRLK
z?hBUOJne#~koUBu#ZP?ig7$M?d?~+b-%Iaa{^ICq%U(Qd)Z*7B<X1g<<r&Z4bkqlb
z{G(Hk{nt01dSS;KZ@mXuE9b0yp<B-m&EoAU|FdUu-~TL|oH}cGOz+BP#*_|Ra_z-@
z32E22|L3B4cR$iQ<E-++*=JRz<zIXDrBNI1*;%Swz48R}$(83VpSLv5wJx>s>_wxN
z+fU8-&BV(49)7`GGIM#`s8wd%`S;ziu>0ZNS-WAy!cn_=iVK&2@3IpsZ!Me_zH#+Q
z@i(uYzT=LMoUr4LtL)Kd+<U?&zIWgBcGq_HC+cmN{@30`=YILro=?91o#8XSy>@u`
zvPoTMU6w5`JTUdFK9RHinWw40<yI!weB8x0J8i}A|LPt6%>SBYTIRmT9RKJAW3TU>
zJ$d82d@g7k-Bm8l`r)gK;tl`jQ~9<_$DMdm-?$mePhC7JH)`>W4L!xPcTFkUmow(r
zq1R2p{_5)6J8!<ac-xP%-8a@2+F9SZZS=~s*V(y0FP><3O`rDsqMr9W|C2?ROq$R+
zDtpsaQ!nf4J1d*Z6;Hpl?Tn>c$L00h(C60E{y*7q);+iHm^P_-)9smYH?)K^ZwMKF
zW@+sU)s|cvzYes~@@e_ZC9-Ip<s50j7FsVD{zCd9F$Z&lceLmFpP4l^D4hPjsOiyX
zD=o#?wk$ls%IVgnPb|+Hc(6R9;5wq!{R=j3JT5F3cEv?|SD}_}-mp=QTmO-0@%pQx
zo^o!R)YhgaoIL&H4_!aKxoz=A8+7~+_lSMznXAhuXR4zE6P_spnTuMHT4I&G#bA(g
zp_$7Wl(|K3=Uky|)2F*5JC3e@f!{0L;o|t2>=-E>KZdu^@l)m6&E-gXtvQ}wTW9Qy
z%|kM8VCdK=eN#siNRHXfY_(`47#-GvVEy#y<Q>za${e#1^R-Q`pMG-F$<v#s?yMH$
z#V(4%a%7sUaDs_X61As~lDxfLDur9;ZWfvMB^1~ZR83#7k(uI$667<P4pYUBZIH5H
zT}sBp=27XB^*qYhi1f=OFuSSS2A&t}#m|{Iyor-koayDoc^#&M72-S=UX~-Y9WEC>
zf^nVQN!-R2PIj?6=9~unOXgP2q_V1!*j!_=>CUfe%*D^vb)L(Y?r^#*99=^h8$tYx
z%juaX_E<GuGdy7u3%A&(E3Qi1D7{m9mcB%M+=n$CLmw!6y}AR=mJ#xCTPCdXIpVWD
z&dZi7M1|A};>?A}tv3vQ{ZQmdmygeC`z4sb-OJ=x>Pc=WYCP4cf;D>P3DA00rQl48
z*9)KzN{t+N<Y9)2{nwHB<uVy6B98MA;9@Jra>rFBMy*X5dflHzkD4EOy7iVf&=~i1
z%&b!G9YD`4jl0uM%AFAuRdR>UN?Ce!f1Zr?l~-__beH+1t4ZpmoIU87r+)<25Vl?)
zQZ#ZPd3r`r%crGcSe!8BnE>{tt;w<iiKb@fiw%RGjtUiFT{k}yEO5qThoq;FrqN^!
z9Bed)dw`rQtk~MKX+6^f(w}+i&hp*0S1&(!**?A>cg1zVzLVeN%+nRT$7$*3?_RRM
zb>}C4v1jQIu2{8d-@+sIEZN`x(kI{C`}`lSICt_xmrcEI<(})e@Sdm3ZdrWp>o0z?
zN#FA{<DNGUT=i4l+w|ht^xMz9@xX`ffAg)YezEjD2Va~VyuIU3^RN5yudloM7YmR1
z@>}P0?A!5!%60er^}2gFZ*|LclY=)Wed9APa|Y_qPl&ww+aI*<yXPCb58i$G+o|J%
zd_CP_wIX`vX~CG*icRO|RMMX*EN*(hPV5hZ@Gq6v*hMy%@3E;1ZPSAJ<7}mJrd?o{
z*0qT;to1TA3B>dSowWyo%eIEW0^7#wXQAYV#s;1J^JSs6JdA9SIsBIY^cQXL`uA<v
zSDVz-J?V!MJ$jkUuJy<=(;_GE!lN^%j7i=3BNG%hn&8*Sv^!3t{*z^O9|nW+MnL5S
zLUmH=5Om%jaZD138brhltu_KC3E)9c)rf;X_0W(y9!TTguNy61NO8m!ESJ-54AVf+
zBQNI+3Bn}1t^{Q|2P@l8&9Q#>XH0Gl4ahulq-N4x7r8m1&FWihhK!DnG&OKYYuctC
z#S7n3VQ07NUl<)lsV-jIm6|6__1=PYWv3P1ES;6A;lM~Kooyd<l~P97S<#yCo&j6d
z9$tf+2=~W3!`Rg}NTF|TYZ#Rz+LV#tc%&~KUF5e;y^LuV>N<X1Yl?itN^!0}Wc9#4
zT({cFtrCQryCl<P?U8W~dg;$QHZJsWLbJstKp2>6kSYr+$`i~iC}e#X_d?}L6!rwA
zSy7~-c)c-fblgg@?D7%3Y%zt!s8D=oE9l77QPB`{LNwT^XLAl}t<;9_c{e?|0bs*!
z<b-ani~JqV)yP7{Tj++o24pA>@zstXnGDS{q)DAiPwObU*O4BD)(RA175of`J%X2}
z+u>nD#jUh$cVWHf&Z-1#cxuv69W_{M)Y^s=<V6W()_llIDj2z1%UIR+l%)g;2Qrq5
zheIUhH0mfbYNj^9TH_?5UO^m4#C@Zdt~a1+&!uj}*|EZ>w>T{b0Y8smPqOIG5VglT
z77V0HObbbX?m{fKrMjt9)PXI9^KHA7f-x-D>qEdeJ-uqVwKVNKpHjW*4Wa2?qB0dA
zOqX#7VSz{$T)BWlz+q4@^ao3{ZJdNvziSY+(jzVJ!qIyRz{0#=g^<9c*3IvVB1bt;
z!%8ZF1Zn0({;U&Y=*_-ec)1%tOh*;MotK2L=`;f{8c+oDYBWHvXbm?<FmaSX6Z3e^
zIqr%B!)(J(CAIQfyYtSl2i>gqdkj7Q7Mi$Yk%Te&PNhpVt7M&&0FzQG3`$|I)!r_H
zE=vkv1=;d+L07c2VN{mmcxfp2xSTI^QFc9h7?5cFdh|R_%$iu7Q5-0p?^A;kuI5YV
zG;{|yUD6V#TyU~&>S%!k`8g$r&JFFn1_@)T1awMO&+^7@fwUwKnnVAX0-nuDJ~j@v
zKnVYUyqz*dKOaPAkW4DXYQ<rz^5MI5#F7&YvD{)2HgaLJo+j$obYEIK<FA|7s7Po^
zDs@ZU?=$PDq)%fxPzQ3sJCs{}wRBh9cBjF31?j1UX7r(u$`~9GKCMOo%UO}psix*Z
z!V+2>Z7Ci&6AUE0pr=2GAC0V_q`4e9G;}?H(UaoHu;oOWMq$TPs!t^Sd7KZ9QzV^?
zr`|Fk=+0@JD-xT8T)V8%X6T6>`v9T`bxwAu6B$ASiLbW`?3y*BWrhdkny8VX8?5sW
zdkwGWAh8Hp%AgHZfpzFwoDNErtG@?c1LPsrkifu*MF6(c4{AQPOrZ`Wn-dHIMjXet
zU`A0jmIq!O#8v{Bxe#i8UxnR`Y8nhfIbKyonbu%f`1==%8nn>+64eJOL&|}G(x~Z$
z5gN;Z3tOzz#rWiaBaa&R2+u@(Ky{H(jJUzkZSZOG=gNpzb+`fN+kQ8eD#koLbu&{4
z(xHb`6b8Fso7y@ch0dUFot37nVq0{Y2}T`FQ0-P!SJeq$7YyWBC#Qhc$2%?+Hdk&c
zGb|k#7a1gp2BVF7447`Gv0$*+GhO?2<2#`Qq=k9o5$)J*=q#@o*qIcjLgDs&oB4m)
zdlv^eifZxybZ^b3ciAMpn@yNJ2(`-q%R|2#3~x+oHv?`U$N~|=d*KE|FG_$bsDw~6
znS==j*^mH%L^5E+__!K@8&F<LK*a|V9)cJ!$d`*;FCxlQ4e<M%>Y0Fk@Avx`{LXGy
zSDiX_>eQ*KQ`ObgHMGsVo;^m@?G<LabUK&jAeSf?^g@GJC9RfKA>jp8XBka+aeNcF
zUtdy)5=Yv#LdhH&9F27(Tv&q5N5>V@4^rDd-PolvR~$7+8Y=@-mDb<fCTUJCD2uH7
z28Gc71eMsX4JJ)mR>x<M8j~WEq8E@*n%Mv`JjGNahrr$WLLyQ3!QNazGqGN%^Rc)|
zGTa@-odXD!l1tvNYHn%vkan4y;qHeS8_j}b_&FWHk_G#bBpvN-u}jhxZA=z1*j8kV
z?R^~41kF&4e1#G%4wIq3JnN&VCAr^u%mr&fZIzx@I!iLb=Y3|VlV5|3%;0FOgNxB<
z(Ntu(EDlBa!KO#sUaghwgWg4Pldv%=k-cf#!?}w_kApfPheOhqp567wJ|$Oq=_SsQ
z9}u${yId4cd5p<x(dBUI$xTU$`|So3ni6Z|SDZ-=^6d5@ok*!Y3w@B{4l%r^o-{EE
zu~JL>kX1t|+iXdx{R`HPb|lU#q8#FF6OAT-W-V$U!0RMkWQgkn2MGiNAefN=Fpuz%
zzc{Kyy_%bvJnV^&MB9vlRWcZRb&)QK9Hb>F;U}f>gsfJ(!@2`}z3BKxkA7Ds1b?Sk
z%Z0&p>g~0ZN>gZn#0c);9IFVmfMtR~`xZ=?;*d&1Pn;Iw1Y*D<2pgiaK-jxu{9v7+
z-jy@KRcNb>6sjFmCaFjs`(#+PL|@e`Xk;u*Dh*j1J%lE<L>dw!BtZ)mx#3o0k5_}#
zXs#$tpkoHCKv9BJEW7Z@y$>&=YXe#-M+V4Hw>D(UVz_jHH~nZJtCa?wvK3k_brw*X
zNDXeHm8csgG1vH<Q|l7+=SaYF2NOo%NP1bftKjR=p9O{93`AyVg7y$kSd6wux0obw
zQ-DXymY|*jwW#wTnj3AQp1+<Bg)YMQDeP<{y2T9XGk`+my$v1|fJ83%BfcmgkAM<B
zI@8_UsLm=*WumPRWCXGYabw3NF55TNb((u1^;&AYouOb+O{hZ>S3y;@SgtNXmY`#h
zyIN1?Ot?zmH7md>k3kLe!4I*`iUC!7EjM8L9cbxlk;!Ti)Q^rG78XV$8n6(ei<{#v
zMs*h-JxY<F$t0)<wwWRrpKq?msae<P1~?yl)&w0E;iw(Vig=B1T!6|4(>UNk?nv&4
z@LT{XBZwfg5%Gl#OJkwlBCmMr#RXnOv;EmC1@bXM(AtTo$vCCRWKKJ6@IZ{RG)GOQ
zm9IcI=&{H}t|}V0K+GgwK?M<?MPd;HE-Qu7S2PoVDx_c|*%xd?2O&c*3(=WF0xf-J
zb*yp?x;*zM;1HO(qO_Em4Qr27o7j+9Gs*<e<W@rp$?n;WXdis)WJO9X-niZ}njL|9
zg!;;XS4L<V>J%_vnQT0adcs=gfr%DNwW9G>d=SMcDgdgZJ{q8;G{+ExP-pPnY6E~!
zU0`A<hG-vLnj*0jRIO*!8*riPd0XcLe<ot0OrgXmDtQ2>byCvKg%AOBzr&u@27#{Y
zcpHjsrirs2nowrG08nyfs4`f`DW2Ipw-CkMia3yf_dZe!s(Y|IBCDuiPx?G_LQNQ;
zN8LD@$E+h}!U+QhGiJ;Z(?`6tgplXAM|1@79tzTH1$V0;ghAKAnqjE<{qTU%cENmJ
z&v7H;G9efmCAC?jaLNT8X*>|I2x_^js&oo2>2yMP>ax0wFytMS8p^FCG&xu~WgN~P
zI&%|=Lxj$sGO+b~5IGb89jL7YEGr3mM_1ue|NG$7TX;W=M4=R5GV`o`*CD?Lla(ba
z8Nt|*pI2$DC~tDmOo9+06oQJ%<jo?pc$m?U10GE~kXZ^m0kY9zM~XUD>AUKFQUpb2
z!5~^@aMa#rI?hUxSqv7pGfHksOkCpMo|@sj-gp$U^#W)}+iif1OE#4W@fo5X+ei^>
zUHC>wNuqjcA9`$qyq-9VY#;-zBc$kmV9$(15KFu&D1fWS(`!Le6x_PQJ!_qiWOb!c
zV(Ug!SzA96_=N~XWZd2_xCw|LUZ@=p&#d}PgQxYO;=D?WAMj3H<rRhG4Cw&@MF^`d
z{}kFI%`)(YgA4sPlZLVBeSt}$hL7y%;$A)KC|L2hfq}J3qLs?PsN@-2a99|H4i!6&
z!wiv4-^{Rt)S2OHjGdtM<EMJone56o8(oOWz>4we(<mvCk<I}%QZIuQ!ls5e#e{Yi
ziSxuc&9Wa4cvT`5p?P^O$^ucwq>H#<Xv}Uz#4hi-ksDQ9%rXh76`7smw7jO#PJ`7x
zb;S(h1a8c$EEYUy&uSFCK_M$-!<cxb4GHv~0R@YSI2E6T)dVVlg1R2aP!u@mh$sb(
zYs3e}Dle)4YaE^s=OC)n<5N(Z955QM`e^`2*T6LJ7<}azT46Sq9}pW7WK1Ji)d%N*
zr6H%)OqdW3w1%~bFtkQ!h<V|iI9YO}bc&MRAgxKmd0AissDK%rQ@Okp0>W8tJHV4a
z^cqEl#5})hEoGs0tA;cy%MP?gx)5J?>Y`LbFiYxmlp=*!oTBgp4O6ER0Vh_iVm)!A
zHe6_knAt#27t%%x?YM@7*&G67M&Y1?3qTnZ=hZLpCR?{72s&#}nq8JMh=pI%B~d0k
zUd;@w>T%6L2qU9@TBYFC(V_%TxbwLP^NNgRRz08t_z&C-{%l$oL<`coe~`9Lj8yPf
za$S!C7{ZVcQcHwWgkl>II%v`#5-3h(Q+mE%6t6P|y;~febf8*CdT2sD4A)c9I+dcH
z7}eMHgKDz8Y{my6oa_`>^8Uhwtlm%7NDhYdbizhjk(D}$u_SIhHyRIhwn(Y_bcCh#
z)Z`*rVynmpojwdSRr5=moUoc>*qCZr5|mLoPMG33V!Czl#<LD>$u5yT-_IH@d93G=
zo_7l+ghSA%+-42^%RH79B`#IS*d#9d1ZZ#T>oOhNX2l~1OGCMmq~Uob;RiPZ6CGkb
z3omV{O-g6xkhX)<e@wDvzwWyEAB@&E(Qo<Kjj_GOGutH}%D|^*+P{yLVtb4@1ktsg
z6smnuCpa`LU1cG>EM`)M@Z`l#qG-g#j^ZRei^E;h9?OZ?p5phh3XDK@T%U$g871jX
z<xm-_%U4bjpgpNYe6Ytt&wvr?Ij-s_b-~8+ioqIh_(D!>MERo%`AqQLwpE+>2qRG1
zk<&?(sp#V>y~ZLb3k*Hzv*Zxii&?CSVHUU;*Z6K};@<kZ4^!4ACuNcHuw_Y6%uZma
zpd8e^_TdLb$TJ;0UtH1?S<mNf644Ag;+<BrB)4ReQbjE?uEhI3z8=)^nEW^)A~Z?9
z18ng{ZC!F~RBk;8(UotXFtwEHyR}5eGIZ)X<{%g`YpD*+f1|k3+~Qh%oIC+T%S8d&
z_QuM~DE%~ljC6D-QH{1TcTk)=>hdPtLv-!ed5wU+7d`xV>BTQ!?q`f1FEcKkGxGXb
z_m}=K>hkiJ#@=lf?z?^H-mm{|<hk7+C{LNXP7a%K*n+nQ&$ww)---wFxm_paC(N{`
z{pujOV8LEd&!}A|^^BjKpZe1I_HVC$Au8u~YB8fGPx{=6UvmHJm1Et_mrvfwk3BJe
zNZY*gFFEdQ*LV3!`PQgoS`IO%3>~^~-hz*P?1AX*=F3|qHs=@4Y`f^3-#;)b`dRrZ
z>7Dtr2UOmR|19#~?&rDF{&?^2-o0wr|Msete&Nht&f0$3JLhk2yJzW}qwgz!{Ey%J
z-FNSJwzhrdseb#+XUi|2{?4?w55HvMq~h8~JBnX@^jmj4``ign?K5f7#fMG)(#40h
zyxn*H_iz0D!TE)6d@)(Xb=p(AP5Q6X51jqw^Nu>|TmO3UtQ&s+1-rF%+a-rSwU0aW
z@k`u)pMLS|zc1ZtKRt76*QGPJp8sC!whP}XZk@gDkps_o_L2QR{oc~w3=LlV$Sjq2
z=HtA>J7Vh>7ya(N``^84rM&%>>txDhKb!UXCGSM<w%irpIOe|iv_HO6+H~7{&uu?+
zTY3A;ZL($2JJGK{alx`l#jh@IJ^ZTZTbtgko$%D5@uG_lnE0iOXHI_m6PHZ9@s%(3
zy!*!a$(w)vVhd%7|8&}=v%mMJllwOO@ub-|yz=SfwK3avyX4Wo$t6$yO^~<cwWUwG
zFJ7|s{PQl`8X@nQmlanY^xH@F-|M|cF6w$`={74ecC+qzn)I^BWyP)Tv87*m?xdDY
z{+!Xb`m@JgwfUvop|>V`PAE0+*-^UpE6bmIJ@=>0+s7Vw|H~ggu=LE)J-1r3Hh)Fe
zlHseTElD?w|Ln-5rhO()s(fMcNvpotvY_*;>D11XlPT%$cIw;@$%GSnChzs56I&L4
z>|c(oeeBTw*29mNM@D_|{9~^A*TKnG?KU`h@j%NvqsN|e%#v|uOs<UUx~qAguInyh
ztlIskFaG#|S+n1rGIr?GZR>qu%vCh*u}<Ya<-^yNe*Bf?{@umPM=ouv`L~bi?Hif%
zgYt8^Z^zyHtSsFyZHeD7{!iuCbDx#%JN1^nwCZ0c&+EJ~pO~*E<*p?%<r5#aQ$M*|
zQ%Aga(;=15OsvlO;y|lAIhmRspG@s6$ha?`DF;_hoW0YJ=FR^0$GUj&I<9YxT(aQ3
zQG3ZJuj+QcoIdLZFHbpU!=GA?v4@xR$AV;n?i>32FL@Wa=d8Zud(%tZ-(5dkh|7Ff
zFU2zl_y5l`2XFcM$g-P8k6d}vV&5d~wWg&bN7~{BxBC%iy;_L6pSSY0p1y%Ka`=g#
zJY(Na`UO2t`a_RjU2PwnSnRoIaCq;F9`aLb{+zKjUzpI}Ub@2NWx+}Lo===MagX-o
zBjq2oeq`PcU2@J8C!ej%8O&D)(!4R9-k2$?RJJetj7h3*X<1&G*cN~LwrZidEGEps
zq<`qxt`Ch|S<8(qt2HIx+M`r!YEJqKMdR!deM83{c*gTK+9`1ZIdSt!zR8z{dgdnk
z4CYOA{A78qAe(zG8mZ=P_NMb@FX!+32|>2Ros>48aaw!YbJ0BC!mmz@aWb7T_M6wb
z_C6nubZNtC8M%oGSrcD)CrgvjNjaai9XZIXHq6h}=;d|K6To=J5CK^%*S2CMzk|Um
zaIcD)upA@1%I0Kl5_R4H{^LwcmdD1==@E~Sm-WmQUc%;Y*vCMxnX(s(+3<JpO&KTo
z=IQXk$hI*@X&W!C#f{SHSx3-!ct=z?`$@+$>?`A%tQ{7&R`)dh<t*jonk(YQ1fz^>
zQ0a(wPNJ`rtmrcjJi$RpTJB!MjZ1twYdPTxyp@JxXk7dYd}Fvs60<kKE@vT#mc{Wy
zI*rKEAHiKGfSPU&mk}og?tqTLVFsjk@zCj>rrkb7z*Z1Z>a&)_4GF2hg6!d3pDM$V
zC!B%R<m3no22uh#enQV~U7c<C2-dnsN@53%!qsueuA5OY11IrnrlOWPL-y8|v6xd2
zNX-n><f(bi5m4pAPLo=v@5+VEM$8#@5>&`w8O!X9+yC9|&P`GQN9I?&SE@;)F1JbY
zpd2(?$LHoslG{!6rCPpFjthp&7{?JQ>gm*v;iJ@*?w1}O6ACQ|z$fxU`>UdlWloWB
zaE)`@Kg79B@BQ&zScg4Nzut4*Ul!hb^t&^*y)pK0$83sT+H>983$J~4(TsOKfB6kZ
zZ)*9?9#6l0_R2^2?YjRM^+V2iI_ki`Zhz&vhiA@sc;>7hUUtWl%Vs?L&gZT>cg9_h
z9N2W<xohq}@4%-oo3ZZFUH|sT%&s+`TJyj$cWk|E&vlnhz3ZsUqQAem=8W^++PY}w
zy7R`aIeJn1-_L%0=$%a`F1nZB&AacI1EZ~bY+Vrc2z^=Pu4Dez^4=cX&M&mwKJt1?
zd*8oR{TXQTrL<-LSCevjQ?<>M7mVKbiGqyxz2d9rK1t^sJ}^P<p-z{`^XaPlhvwf|
zjLkK?S1(oiALtuzdGENfGe6wjx#HPw)91c@7DqJ{^7-B?$K)m~vDYWvvU*n9lEmp3
z&8UIBI=|i2GU)+6^qJIl+(4VTF!^$HVsa%-^=>)DO)~%DM&;aq%DdtOkvmQQv0r0@
zjn<i0rvWsNx>wsPK+DsX4>%icc(QvVNXUks<uiQd(kirNd=O}y4d%36Vzdh>ypIk2
zJwpb;bPvhH^f(8OXA^DvviAsQhuEPJIyUq31<U}Y=D%YFvT`fG;L9&|vUlBhsa#>{
z=q;8WP*!^-GSsURMM)lX;T?Tq^HOj=Y)$MDu}3hUi<a<eR_CutPj08!N?b__#-#(C
zBgJEdIPZ1Ss&iLhZ!D8Z1{wMzc5i?)hnQx%3UAHl$;~`QJ6+S6#-4{{(5otJZ6s!+
zp-cLzakur}=*o$4Vr7yk#t(@Ut#-sT@{&x5XTy^o<4D(q%zMZX-IJ$)BE1$x=*%?1
z&N+;8G9*dspjCx?uDGqgTM5cM>0*M<;iG}rjGL>;3S7eDjp}t*og}xJs<8$UtRpmR
zO*0Jfk)uSt7T0sBfi+gWKGqP55YB<pT6f5&#LY?XFvp?B;W3i8ZbO6BsMBjSYs4&9
zbP1ZLI3!Ix4@4v}#)P_8mi@3nW$I!a(?NZ{X@IM-1i(-8Aylj-pp@j2vLhzPAIqqR
zhs9^n%&39X=x+g%t#wq6buPn`mBzC{C61m@S`9h2SoJ0md3jy3r^Y}EMqB1sZ`H47
z41&bp$xZdP;BK%yFz^f^lNR&*<p>+=5r4LNWr6dXOX{(4Gc0-Wx5C)!dZ!q~ifiIW
zu=_FDYik6GbTR8BQh6A`V&RDjnVQ)fAj@sDK4`aumpqA+8g0^%W`i3IXNi5*v?X=^
z!@9OeSfASV7zkop&k@7UMc(!BKx3q=ZFL_fJsr-ILu^dd#gSAc>Q$wY$v}M&amIDj
zrUfQ7>T4&*$wx@G8<nhdv>6}Mcw;hbH?FKWr;dPdL<2Dwo^o=8U5coHrCyx1Zko|B
zV^SSH^I^WR_y_yYi20xH8L!O!pW+qwz99>3?Egl#1Fy3FGc<B&+&>uqKhZbh|0nuJ
z+z0Osy2ky3acJ@X4Ihl(;eY(q4<=H+n5lp=vFdnL(D<sn^f!a8j<%H%>#3wf&cV#b
z)qYHgbVX_BAjmFAx;=!}2Oep$kGI%*_MG(ZlrZ<<kg_gjHqxKw`z3bC1ZvlBrf<ew
zm2ft-+*DB+&culw9%-94$?IK(swBIcwBKsiPiw2v<jhJofy&9TX9`c~k=Q+0cWNSD
zj_a=}Biql<ly)s`b4(RzNZQmwXJr$fRBM%duBA&m7%3|~y=)$ne)8cc>OL)YyKIq4
zx;z#)B3<j7Ed~`(?lKxfoI$j&E(0VL%Fi@3-+3JAvE<X1`k*J(;nE7Jm_a4B3AUkt
znMD+i@`{t?s^dsC?OLS`9olBqF@4XTqe4gh$(ho^el>U-k=<P+-jf+UTRTjLGZ;p-
zut&0r<B{XYPg`F}Kc=T_D>xHZ%Kcceu1dsi(=Kz<s>lW%$MF#5joP}V5Qa6-wbVAJ
zad*(edUPC(sF7{2Mbh8TK;)?xC0h)?^tj}vsAdwTfS#dn%phhIvK+IOY#Tm02C+rZ
zah{Ec>;|$n?U!Z!RXAW^gy9agpyNuMy8C6X_06Q1i#CpcfD*Aj1F+W9!$OR-t)gr_
z>zmTspQQbv<0$quB~Tr&V`Nhu|NroRXu$sy=AXm=6#Y*@<`#g{J*F2vO|8&jL+jJA
zm_F65yKEU|<5)Pumo^kLh-r$(3kO|fq-~NiY~EuPSD(8ajh0{Ah1ex@&8P>SiV3Yt
z$+a6Y71ai`M47(e@cS?!U{N**rDUC+83m-ei(15vR5T>UhMNkZPoWH{#r1)uHc;k6
zbfET{CBGihM6Bw9i5W86LIM?pFDY2s1@QA=uJZ?{Vi;VFcA9N9(rFGD#d#Gu6jYh1
zsR=oHy=UNLAh92MO9N>R$DKiT5d*9g5d<;AK3<K;q%P*dL?Yy8!O;&Q%g^I!PLA;v
zN}UZjdR52@xq>Igg~W0sz0May`VqBT1q8HWyyPn_UVtjgC7K2)v`_$bL!lhC=~WCZ
zlN<>$M3WZL)dn#C=n?k6X$?819jWvyHp{D`9;;5{)@ns(5jK>!NjwIt9)%uK<&Dfq
zRE(J$?aO+z0~5gEYQ<iza~UV05{gu3z_QK|p?+p{*%L=t5mz0a2@f92v0~241Wzf*
z!ePBJ;S%RsnFX~m(H=2ArN+sW@^rJ~#p(W=Y;Tjw<iZa`X_-bj@s^x;A<(No1j;WF
zJ6SO}prte_V3O;0j8#6urA|hIS<_i;Bp@*4ForUU(V4RL(yCLv2RZh$C!LFG0Je+K
zQEH*QLEk=MqTQ=ev13-*N)5&XR(}DRRR-EIY(w@O>n+q0watiSVrPWscA}&y<n72`
zQqMy3X3cmh<pO>dTv6k$bqtI+$(c4hmdsSgwvTj#W3J)|PMtE=J*E@i)CiO7(UwdX
z?O^DDo2M~|1H;3)q|0mz{i~-bu&~0fnrc(?&PKSZE9AjkbTLQpmY^>B4-(IBMHr9R
z2shXk-e;)Up@Z^JBguHmL%L>9nEvM--;0Q!Ej*2Q@t(eAHABNzeV{!ZWO!+#(bc@+
z35a<M0y<saPm9o*FS+puYo+I*$D#=`qG|MLPUVj~Xzh_Fpu$@29>zA3Zl?x=u<l-m
zA5R~#8BeVaM?IG5LK!SiAE_G;p%O5s<u(9g-o4`sdm$I^slH6fo<adV!PO}g5R)17
z!c9|)Ri!EvEI9|pXrGjH1hBF0Q562!UBsLj3}DfSxZuShIZ6YRa}beWn?qVpFk_yM
zXsuH|rBE;bMEQ)yON=i7Np0P$;wV{57LN2rbA*dkZ^l@C856w+Ijs5uIP%kEYOvl1
zc#f#ekBv4k+D6z5dG3oDg*FJl2e&S-`s>-b46m+wy%wdUz6=~UC{r^M!m0?LiR(j=
zktXAhCxti@tPd_~9JOr!2;KB=B3w~ZXCx%d(!wd@MG`z7UdA=##BaSM2X$q&+%YeR
zg+_IQS4ftr)oXsuBxPtt@DLS*(9aw_4|)J$>w46ugL4cStQ9g><3Ve{W+kZe3hi;}
zH1J|Pmqgx52AS>G?Y*8ZZW)w9sWg9DA5c+;f`SO_y@u<MSY=i=Av2zpbu`W-@2$&(
zx%4PN(E*&e9X{+QpB?ScoaW*+a-%x%R2X!@tN8=r=25@E#w$kqDTQP?LIajLr#`A^
zT%dIlyARZ5#zyNWXo#pC;^=-{g`rFyO5zFW9@5*d#pAeGVr6_#51J2m^%qb}#&<Lw
zgcFyT9w?sS2G<8R_~<X8S~ZFykqdem2>}gjr2f(@cx=C-GySWVaU<jq;=IOXV7Nu?
zngL1FxT@h$ivk94T+DKu*La|yP6m<B?%L~2<_#`#b_5wT6a@}=l)~3P?6ty|NCet=
zD%_FQVV1P8S)SlKp->3C9TOW(qpMH*t<Qw<nA}VV3`?dLANK1~gBb<Hfo1GS>j{N$
zL8AkB9UKB!>I09CZGg}IL%RyJMyiT8KI<5r%HB6>J7+YGYE^yj$T-&CraI#$rh-G}
z_1r>4mP%7Jz=lrjOQKOB-v^a4@%8qkg;DyEP^!SohP0YZ01MLLgF#4-w}WM(5SOL(
zu@f(h2o6USTx)g@fy|*l0AYXGZtAP^VlRoDsbS+)3>$>e%rN~QEQgY48mCHU-iT28
zL+46qwJR&6+O$pZi67)%@G+YV>NznA16rE&2-*c$h^>}D^QoIWB~cR?FpQj5N_e$7
zDtP@A$OdoyhA;|n2$L?BMAMSyM@P({j2&}v<eg@rLT3VEC4t~ZeOfBYG}0v{omDy+
z(9Qzr&y52m%?vgXew(FNwCeIJa|Nj~@JdYMwcI=xB48{62PhR(Di4o<!{@VS9Z|*_
z<HEhJ5wIyF8LhGcGEL`bs{k=x??#<aS6+Q3b-?v$nG`G+zAT`KAb|1<Y71G^Z3{%9
zz2=Av^cGJY8tGA5gE|Q8l#M1(fNLfkBG`aYA^Yn-S~;NhqcPq)MfgmYul*RmHmrK>
zH8RX7hC>Ohi1i>SJmLDph|1EnX^zp=7_UwmIyYg=YXF*uX{``|D@Vs8LIBMpjS2y+
zl$OinhH*t|;=!}6iKh*H`xdwdZ7HQFi@Jzx<W7cb*7MyKGF3CmdR!pIG4+S7$ks77
z_H|)Fgw^mYod-=x9JwonLN=;+^^m308$dV=jJ`h$gi$u+>awqQ>s(cQz(TDMe&g2j
z#1KM!Cu*cAY<eL+n~V`*L!`Pqw*`MFEWe{hNb?B!WC91VP+2CG5|=bUknR)e#3_<m
zwcxz~^!d=WpwTk6xUzI9OZ=LwtTf6zm?1Eto8@%j!Lzdbe}G5c`Ww@FEj8L8?JNjd
z)`EGjZN_E29wsj22X9q&W1I-Kr=EwZ$V$y3fXcu=MO<x$;Sq&<w#RhZEg{|!)JR~Q
z_;BCh_`2?SE{Tlt%E0PPYlTOMEN#F@htp8OWB8QVb5*$z8H19u!K)NRMq)z=^+^v1
zj+DG6uqr*^nN@i81Ry(xpHRY(PzBH(=Jhf+$Ubnl<jemM3F|3{^juorq(k%9CBHg^
z#k))ojF#{7g?}cTmRFNI{l^Jf)4h*RO(lmwL!nf59Fbyh)u&K{x^XnJ7DS&x>p;rD
zT6xPxi<3Po;ZbHG7J^_nWJp_9C5Ir6m<&SJ!IYJdHO8Uw)QhZ~9r<Mi<M%7PYD2%R
zwTfb{f(s7N`9=^#9sP)v_C1V~nKp@h_OU2<uh<N{nro7=a#IW#kIUzb!LLr6dgFS~
zl34ljWCY5pC_dalY4f6Q;VKYa_h~4JRL{Gfp?>jNRJb_h)Xf!W+wmmga07UCgA}@s
z133upp4&gbj!c-g1>>&AdcU9bLnul~JeT8A9#w9tqJZ?Fg(3+SE#rkm!MbHCC~-mr
zDRXckDUcDVuT*D4P4Jx*Py9ZPcc`k8v4=_ELk0n|dvH~R20DmSC*kHT4wfS%rN%YS
zK<dKpTW<RUVU2S#0-bv?>9}(TuSt<~&W$Tb!l#S!5IW)AZshl4i*ijWena~xmTfjW
zE1lk2vSON2bAcVXq~7|dSkS4v7?pxH<#~hPq2LqFwmni=EnTAP2KjQkG)<UKzMk*u
zBGy`XMHl55|48elGsiDNL>pUl#MU)O-m&ueee<wQY(LKxEf1>n6NgLQz>P&R$NZZd
zEK6NUmuCh-`E1(am`+fPj)Ne>FZkVZ@6-0k^{2+$0>ZHKfXM@okUgHwr|ivOt_I6~
z3Kh5y3jD(Q!p&-MkLY7wkho;HD3<-Y&xnlV!cT&@m}EX394WLkX&J-0dPRMHN}EPt
zZ(<hMmbP<Ji7pZFV*2Jh8(#QC*Y;|El}?*qs^#`IezcDFCc0kf#E(x4v<>O4N!8aI
zneR;DC${YgiAG8}pJzccvG+@9SQRg_OMBwmmmoiFpxq>Msj*~yrDm}UhW5?Q(^A#j
z+tXZ=?h1+~L{ZV#lBk<06g#GnL{@jx$>5dN$VuBqT#gP;I(bJOo^Foo1y}TtFEP!;
zA3JAnTwm?zVGL=Z$XFPKj;gxUhIE<M*`a#mgp@_xv`Z~H<&mU`4ZN-x$9rR7ATBid
z71UKyjm>7Vo^i@igCoaYzF7A_9?3hCy?5EZ;KiRm{<Z#S<;a%~`}~5+%)@$LJb2~(
z&#!!ZNqp%3yWe=jy}fUK{~M(j|Gc==d*gMzX4hS#O;7A|)23xNmG)k@^W^2bPR`%?
z{j{r=->s`Qdh$V)U3Qtc?>h@xwy!!as*OErnZM?k=-&>$L=L?E@wBpJ=hFR4XLZeZ
zX2C(1PWesrqsy<0o-bb>O*d!v+%a&XeQV(IXtxI*ko3E!&cEk7^LoDVvsuyhU4H)f
ztGhgMy2@MXXWjCtyI%X{Z|^&O#z)^8TJ+J^+FsoCuHU^l^{#tf{J|T)d;SNn{nsmZ
zty%GzL)X0X=6fqPzWLrY?;P;+kKVN3BQqbo_r}|9xcA!Iezoe3ou+NPW2ev8b~$9)
z`dtn={5x+fjK1@qpZ&xs>n0})Z#;R<8~1#^<<IwAeE4nSf6~5bm#04Q-fu2EnClbw
zTz7iQJ?l<A{H^By-SyVe-<|jQWLwwk$+oi&_~UQqANa>@-RoYN*tP46<39EJsXv|d
z>Zw0JM&+INugJUYk_%ti_TTSa`q9^9(MR9f_v{1jTJgfnZ(n)#T^HUz^zG+=y8Y0D
zyWaiw!4E(A-im2&o_F=aRgcUpZF*|PkM6$lwq-Z$dh1UP`(Eq8tM8k9X>FJNy4LUV
zk<V}V&r4;)Uk^Kc;hGbZ?dwkd(Hq~H9{u^AOOL)|%CDkL*F1^5A8G&lX%~Lt(#g-t
zJ3Bvn^ixZJzt@G$zyH+l2e$2X@xU{mJ@CA3LkIo|c|S95*?q5^c+B*+X}bu&I-q+s
zZ@GsDtt+p5dCc`!4Sjs&*ZzI#wO@;F+3&9}KR@%Ojc0ate|Tt@uXVq$Y}zxoUccM4
zO_PTIc*~^W+R}Ue*ZlIqAMU#4psP>qKlthuQ=Z8ke&>qjsCV6Nmzte-v$sze_lXyp
zj&Faked3(kixZRWZ{!ZY=kD<>*Hw=_`r7Mfwfx7_qtE;LuE*^2@7G*deCbygwp>*?
z>g>O-o^3C@;f`X*4R0hW*TtubY---~_j@+)+10l4meEs|e(k2|onId<^7ZJ<U8ap0
z%H0|t`PHv1oOAtGUhUYaeD2c8<yzs;FPu7bz<))xy*i#9*{h@dg%!75y2;mu({a1a
zUw_qZ2e1G4gU?#ubC8{%pHy6R^dwn(^wgvC<J(%UyFNPl>ecNn8^;~@;B&1V?H{^k
z+MIKqxFC9Yd*{*jtY;hLr2m+++YN8X`l+XU>g!`q*=<u?_|!L=3teNE&;Izy=}}3o
zIZ|5{=|0ZGKZjMi6(e=RZm~UP52-bqYIL|CRY}L~X=PlT++3|TEjhMW_;S0mS1eAW
zd5f=@`}O@Ro!89kNZXI>kJldi&^5{U+xyb!`)B0Kj}~j|pZ<Yu|9q(}JztX5wcC^U
zn^I}neth+tD=zRGhJRq!9CWc<Fu(7|Q>FiiF)J8M^7-}0&e?Z;U;B4A#O=38_xBsJ
z?S3``ubq|1358TXZm*DL&wJ-3yfGR#t|sHY^_`oUh~9jK*f?^9xT#v2=O>hkrEzKX
zq`1=@`Lm9SD~{`Qt}iWlp5gymT)+P(p15iKuuoY(?o3<K#1y6_kv-mTC|ywfX7wOj
zdhj6o<@?>or}|kx9)mq@ozEWq<Xqb)=UIu?OZQp(%LTQ$n?-&)1|wdZRZI$f?To8z
zn~7E<_eRX#YC?>GoKqCFuL8H6FCVaC@p8-W>G8;TXNrMlMp22zhxZ0mjI)u|(UnZ@
zm&-C)&Gw(KGk|ZXMT@^F<5TRbtSX5djOjeg%Hq4N$b$$s0RFQj_%<2$Z<y_QJeL)9
z?DG=MDe)VB<0L)>ngZ7kb&u(3f5RuS&d!j9Z#l9>1(ka(*LunJm@a2{tPs|V=Vw_P
zn+ROG+=wUWmOHV_#psz*hOn%);SB5)8hD6Nc`3hqoC^Y0RQ1j{%Y8nV$~~Q{81?T6
zt4wng$2G(yy2o_+HF&xnoF}b0o#h#yBvtfVjWgNW3?m6!Mk^d7VZ*wMg-4zy!(5Y#
z=wapAX4<WIl_S-+sPV%*UJrq1Akvrk=_w3saN-16@^?v6Amv=^rH?v<hw3!Q<sx`m
z0;xU$DK0MSsD+n^<FHMC3Eug^{eL<+(>kRJ`)21>l%(9Aaz03oX8e=rOvn4Ts^s@r
zv1e3nU)3_*ULKpylUgcCQ`INqTQ;nXI9X<#bEPdU{0Oj^(S3>jR_K+pQHoDZQ`>BL
z>zF&5{{GQ5oSXOau*Y=MskgQKZ05SZynENr-+l4v-;cfZo!3ggIB?C|FW>O&qD_B&
z<MMmoxoycW?%4X*7uKD=XvWibj9Pc;b@zXkbMszU_sEP*4<9&d-5V<(_~U(B-+AG>
z&&|B;+54K_d41&>@7?$GW&5vNwCh{X9?<pIg)7ha?5$5<cE`HQrrvStWzn<yZe8%%
zzYtz?*4Wz~zO4P}?{53^JNKUa-kwjtJodI@E=G+TldxwK#ozYuYb~!#Y?4Cm0n<D_
zDvzwlmDbN|k}<n{+mxfl=J~yv$~MI$<foa+wJTihPM@s5W@1`d{*h?;+V;pEJKPny
z5@%apH`sjDV);%fo${kxYqWm+geX7$Ymr>Hc=R28ar$r5)86)Ly4y#s*gMxGlcVQ*
z4>zw)7&N=z7@M5$bBp=4z>SkW*~w3H<x0|bMpx3_cSbTd%9Z~m)TGM0@f_;D&7p1X
zS+&<|+0_x+q(p3R)uBbv%$!hUui^KBYW@e%$G<}8s_-zH%4YF_4##CdpWPb#-j_ms
z*%A|zM7dh`^z}4odCTkMhE~}6WVHp`!Q9@{QCf=Li_ZIpZCV<tFe5b{`I%B@QbZ%r
z4shBLU)Hmn=j2FZa=-4}z;i+=&gZ2j8<;|TbHY+Pf6!JW>PwE4Jx18MjolP%u9j*r
z@iMowz5R)b_}DU=9ZsE>VTrcbP||${WMn_Xq6m38?j5U#hC4lbaG374@q`xj+0^w)
zt#!mfU)@96=9SG^NJ(+}Hm489yf4m9aVVRph0RLomhhn6>^3I0*#`|3RX4@Hl5#+(
z_zzO5#nM4=s2mkJqN&JE?3_?xzaB3`7kn+$Tx8?c*j6K%Z;tg8;#)@IuvfBXc>qd{
zH=fCJT$S}qZcP$b{9>AEi-D_G2AE-ei4qO*V9k;oW(CV-lh|SJy=Nd`nU1Yh@&HQ7
zO^xD_8V4*ff6rsnc_rK{)#f3)8KENB$w;}Tjjl*Rpl3G*s!gWz^z4Wfb-bscv7sXG
zn_#0@4~<n%tBVSq$xBF+ZfPTIWqmOw(($E<ayLn{w59{Ttw5wU92crC#$SUhazauk
zj9R`Jk0F~#^`>HwmNP&GB|qMh4a<|hnS%Fml2Xjm7Af@L8?x2*IO;2?rHP;mhY7W^
zCSmMB1?kqtZoKg1LIWjD08VF0G-<oOnq&X)T>Md`9L|;#=anr|f_s$4L=HCB<~=A$
zhLC_-@X~Tt;;e9pTr>v?A9E5LZzmZ<20A6$$uk5N$dn(voj~zoQu8F_<AGH6%P}BT
zG|zs6M4r5mi#EWcq#5FQsHQo)^~l=fDk!JVN^}GmANk(2sUl{W-3#Ow&Z&_&%~_PH
zXO4ITB$Y%-Y({+A_fSdXe(`6<mQF|<f=CS_*cZjALXMPw`4vfs=K(sVUfA1=u(7O%
zIMKZ%&C1Z2h@?}PXf*kP(<9sNCy6p75`9R^5@kN31(m2LvhnbUreK8aCNt2QHI$TM
z*d>Y!Yq9K#12w?Ji(53T0jno#Wb=x2y^>ims$4cvg~<w{Pl3*J(cPg(VWj4v7+%<z
z9?$HDDT10Aqd4O9ALC&h^z;wSr0TTt(G)9-bGTs}6s<BA&_#?#lMjPoN1mo3mOiTa
zu&?lAbJ`RoCDf={NP*Q%5@5kSMLklw9ffAw!l3GK)JK$rs&13M8dwH-zJt|tG{Um3
zq1v)cZ0EBju~v6xb0<;@(!&jgmh$7X_;o!gbp~PJ$ZU@GpgAeDaVEk>N{}UqyhbDs
z!G&Dvzf29KY4fS2=&F@4(&XDw1(X#MB0h0sFl@<5NhmG|+BT5%;dsmHD|lfSD|t4n
zOj2dG%vylzJf7%C7dM$=ZxyzYOZB~`=<L*UA0`u+((NN_dMuUKR#KA!QhWFiNmvyj
zgxs>9<}Go%3HfP2S4>cgdh;G5j!>bUp2glgV%VOYjvYW=W4%-d<reS7anzJGv5e{H
zL)KntvV+P4DCmboVjbQ=(PaXQAgT!3Yx`gi>?l0KRpYkq7$T&oGAZoULe%s?KPNpU
z@W{Zo7QgAYqc|g$)ebsL0bV|Q`xPlcy4WU_&|NeG7+2HuR8-BuTm}m+sSS~|BJuiz
zrII+vhGXx<<U7Y;SW1a!wFUKaJ_Rg~vzm`~?;3SEI6o?Liq?2AK2|Yhi1Xc+755{>
ztsEl@f<&pBPKi6|dxK;N`UvixQea)9q!<dwnP8i#T3NavasyGfP4?YLVyk<ee(-lD
z;a-fFrXGiilIdGqA&qO2yp*ITaGK}dzSk6DR^Pe{L$NfGPJHhPY$-!uJ|1B4XmxiS
zS+W%QwDb&>t5km_i3htAUzy_=D3fG9Q;cZ8R(43z3il?r31&LUVNltK+Kw$nU6|F%
z5IXL41J3TjF^%2LQA`aQXWEL1G3b&S%Jp!F>j+E7!<L0SaZ%h+wn=Zyj;gdUIA<i9
zP@Cl_S+~ft)NFP!Us*7XXA<D)xCz=BD7kdFy^T-FQJQcdUbmQoR?=yzH1=*3=%_qz
zWLT@1FXO!|PN&_b4>sMLD8ws)$U@QpANH6KO3*y(VB!lj^-he1O}$n}nyMM3EfM0@
zPmzO1oxDjqgxrFyw%US>W${sm4N}s{5U~;wum);EgvCN7HTCl~zSEn;AwDn&h!~v9
zGGvhUsF1|u!VzkgC<R@m2QZ<qVRcXAUC09jZBiqxS959yL#CjicDPdJin$QVbJKg1
zzPnLe21*>dy58v!-a+I^r6kFjM5k8Ie;cN!yM6~!#-b{24to!kRSw#DXm0y4qa><^
zKp{QtMU)>Xiz5@flM%0t!$#ej3VW-?ay?2DM3G2J^3ZZbRh|+<#jRhQ5<_HZcSP9c
zK<@Ik(+JfT(x$^iKm#y!QW=eR{kT+J0GDY4qRfDL5_(BTl6=syRk|kTK^Z?@t|UhN
zd_bbL4}|YO64#Zz`Ef#Q7u;M>A$3R7%Cbm9n?(F~%U}cwuTc(rh9a|)hW0q5hQV7$
zB-E&mW~+X1fzF^-dPR?-oYV4$MoNE!M0HMkz^0a6Naeg>aj={;@d6YPS8yn?7!7!J
zT=R&_qS`c!-~hdv4r|q`Lr?G^bFT);E`-T7x*$|sH)v`I0-DPJE*&ngR7Sn{$gLe3
z&k#F=Y`jT`Y#9X51G}s_6R;*<#dgqHAttOZAY@v|&Jv^`xN6i3r~wZ(r~7ceff(3K
zE{%naI9$RRQFbF#N9>>@V+CgevEdeSW$qJcRM#*F1xq|(ZVFi<H9&yNMDlopK#Iew
z{*16QyN!Sh2{~@BNL*lD2-&!hG=`ozfF~=JhgOa^@YHf>O*X(qnt{O$ptT?J^Dcy4
z98v~<Jc%u%LVjvN1Jsq0nGp@x#0A#9_*IuTSG7(8xj6$|BO8IMMII%#QJ4$iV`z<)
zGd%~im00Zn-cXou&*FnV0y--bY&t@@BzCE0q1gj*s5S0cWWZJGF|b!kWuWYKu++r#
zBhTOJNbQXR?_(ihUe4Pm1*eWj6+t?$de$1`mc?tvPH_sU3%9x~A@K*~ks*!s>I6`Z
zWL~Gp#LC>my90s2ka(9R;g*5!)7b$#YFC-?X$r0lky;8HimEu(kEeHG%Pj$~2e1GP
ziAwST5!2X#lOeBeQ5|8v!UUBxnH)-N=#^Zmf#b3a>oVC87utLaC^~jl9%$=8OC@D$
zyo-k$I8P=%lLC{W3T@Kt;xoPGKp0kWKdCZ7o2VR;9uhc}$w1LO^?@Xya&g14!QZ2-
zDmq##G7zhA%tETm`IEB<O-L3Y4{y~^fxEan$ve?AihwK+^+6u80rNi8^H=Mt?Ckq7
z_=wE@vy}GzlrgQ!LQFxuCeavAW3n0mygCJSvckeAQ-uwv;5e0rOFNWNGO7$BZ3j{!
ztaq>RaQBp@3!Um1oiVEC5oDqc)QSKa2d~U*Hwc3sU}81B4K$h{>>t}p?P)zt8Wo7v
z_2GKQhED*~yCc&Ojx=+)bI-(3S;-c#TA~JM!$B+cpcQfI%|<$84k5+VIdRXa>`Z-Z
z(2U0D*s59x5H~!`<m#wkQe2f#qqy9uO%=%MEdy1Y7L8uiNU0G~P2CJaVSPOSTZ9kN
z)G>O~Y%+XS_8lRw?efrt%3SjfqF6jTK$%%C$Rhq+ePa-^WMYT%FqsaSHc~keAN=ap
zcbA25aGbi{clZVsLFZx3vWDNG4gC%hk#$U-ze8vOWSoZSMQE80&1=^BZU7n8n}L6y
zd8W7EQi=?Y)LWPUSRV!&AJRgEAhDC-_c<x0inS9iSgT<`n_8>3ZPG-FKp$+uU4BQ1
zgqC=xeuXghwCNra7vxYwp7b2fQzIN1)H9>U;5r9(oh%lGM8%M{qwJ}C1%}WZ^Z`7q
z3{xNiiVBsX9_3}ZD>NelpaY5aMXP}ZWKo2IJc?zm&d_N}KIi}h?8;d*C|#{k6fPmM
z%Z6ESKq!B9Z?NNYH`knmG=s!rNSS45WY%o()N4z_nm+2q0r)O8WLnD9$J{^eW`4k1
z2_nNgs&L-h!;L({6N-LTg7yIBX;}`mR!8_8GRy{tOfsI*6#WkX=S;)&SaPjP2sUnH
zl8K~=GQEYYvKf?Wghau`)8jJQqGE#%y|{o%xrtbHB%Tu#;qm4Qir7NfhzF4sqoT+l
zPEbb3mB^6XLBy0HlP!}+Pbm{7Y#!MSzKoDSqW~JMgIO@r_%)1TV!3qxti%}~833=D
zXmCK=E1*MbRXwK8&53yZx5~4g5H12Jg_eNHQ6`7?q3vs2H~>XG9{`3<1?+n^S|e9m
zXf?{pg*aQYDsD=4tkLesPE!pB;fTz}4Fnv~BuWFrOaMgyinE~&S9XNK(W=lApleQq
z;iW6&BA$!yqcErH(_%HismCcl1#iPmm6=&@C8Y^EZgrZl=joNNf$$_`PH7NDUsDdH
zvBS?XBVrfCEDh_~XEyakenP-GUj9YH4vA{g)QV2oYsiNy1q?9a?8UYhPA%vdk=Q9e
z-76(E6C+OCLlL6ER8En&8SGMty%uXwZWnDJy~NWc()8E#EytQsCARGlz$Hyf%;GUd
zUOGy|i5cijOq+P3e1+ezNlKi0Lp!UoY&L?tw0l2=+Oz$J*T9&gw7|jV{9qVYXHB=^
zb(flZXq~yT3=einG0eRw0VxqZqP<0}MjMyw%bpNeVMCCPPVMhkNHPEo_OXMu8?(FB
z1YI7@!g35ReFV@t9gI{jZCY(n4PEk_70uW0Yg^-}ARTSGy~=85ihUbpD)br$>6qC*
zrmZ%~C^~Y7X=*aI1HsBrxVdSKK3bDj+G3~ajC2_4)X8BF-;);5f5?QEL*3<zyyrm|
zorz6ibk$*ss%{t7rJeOvc85_HiGF;oM*>Na3u%@OumVcic+Z>D&$GRYQ(lEf<?w}N
zA>!p~y1@+lVRWqqD!(M*lgBFBr%}44+*v+0-DK4)EaXMyqdW0ckxdr`6w<D8;R=}~
z&1Q`85$`bckt0e?C+0F(b}RDhClH`7ov@!YCG2V#I&AzY=Y06IdFQyt)?BW8a?(jt
z&pB-8(>}d^+{bdy(+(GQOr3Me0W<b}VcO&F%~@qr*!jk`g*(qU_s#qN&AqVVslMe+
z>qdbyn;tDa_xb}XXH`mLbNgODrZ{8E>t}4d`lo03Yo_LI-)UWL(duUw{CMNrUB${$
z<5!H$T{Q6-J7f3>dGh}2_UyiV*XBbGo0Kfd|Ha-?I$~7+{Y#stPk++RIQk^}?KL8I
zEWSLRbjYsLH?=IZzuozyC(ixK1AiL2aqFcj@0%yyxN7aryMBo4op&dkcJB6-&px|-
z{Cnqe-A!E2>rbrP_T8sWJNK2RPP_Y=mCug8d&Og)-}IApFKqhBu5(|1a^2BKeE+S(
z4tV<Avkv&_E4v)F^0ZIgJN`El-(9)w{C8KL{-Gnj|6XCn+KayM=Jk(v{pI?nF8yKd
zx4G?CZaaC#UAvCqI)OOTxopN|C%mzx`-C?hTeSVkNA}#~8Iikx@YMtE{lU7=T)S+>
zsK4!e()N!(v-PN<Up{_PkoV*p?_4|n<T-bnW4`+2&d1HUd+{TWZa?rnd-v||Y<&L2
zwaM*IUG?lQpZt<}_o>gUx^v~TeOwn_`{Q*FZhC6n+$Ww~H+%C<=S`gP^eefkC;s81
zcdvZrjC+^-c9&nSd207}*Zlmm{Wo1Ei`Kq=%A3oc%DuXJ>xuV{|5@&phqqmN*!M;?
z&$w@w;})&G$Zo2B;na)Xc&z#CH=dmL^25K{eGA`P-}S>a>79428yK!G?ArVI<;`u!
zPkTdT|Fd*&(X}HdM~7W9>+X4noO<p>9n0@~d*ZHb+nXkAe|hH#=RSGe$#>Sqo!oX#
zQ}gyyMm3-N%;;U#-u?L0=Gz~iGOu<`+dys9$!p{2w%zwwJn^Hq4qsom^Xjz+y!hzO
zU4MA`#uLAL{S}8#i0->|QSLYL=BgV{y+v-={T9FO(&N5*<8EIVfBwR~<@1HT)8C#l
zwY2jd6S_vtOAEUc_FKF3GUS@Aa@~72do)Vp7cD&GcsV}xtM@s+x>wJ!AAS1e&iI_i
zRvo|k+DA{`YsxvNZaHjJ=fIs~cO724(=Kvn)baL`rPVo=QAZCyIPPfE*3|jyj;kj|
zcV0avz4Ni<cGY96Px<b$*1nGR?;jjTcb&0x@%8!jzMQ*7#-93o-&MJv{q%+t6FJ}R
zEx(z!sPnhxO;f(Kd-rQ3zOr)a*<W3on=}6N3ojbWxp{v4yw#=gmCmkp?-pfxb$)g-
zyVX5UJ^k{F<oLD$lkPht?H|q`*Zh}X3^s2!>G;)MKDWBFd9dk0GZ+<l_4PS^OXsxa
z;dsM@6`k`tk00}ybXMy}H?RKj%Om+G=TGSU%g`RZ&$rin%R?J|E_cA>ReKe#sN_$Q
zht>~9r*w6El`}Y&`*}C_AF&~wHTUJ{>We;By84yQ0spgo=lOv`OUvfMp~+_63}gD3
zPpfQq+`?$whly&}^<?IL*r5x|3)bX@r>q*kdSu^0elTaSeP3jofNVcrU|w?5y^-|z
z)(Ob=q8S`#ew^2jw*N9W?tOm!0V_<-`l!XW4v)8!{0lEspWtLD7o}ISd*rL~V6Put
zO#A1)(6sWRxr<l+p*+YjLSORzW-qqZ9^B%3YP0$+mNT52cV3a#W~C7_Yuj$6^-g52
zVa||Ww*jzkM&x%~ST}i&A#(v%@@*fnA4<~az)ffDdzJg6+<TbdOrdn}Ft5hm)Swxr
zsN1{SrB@>VAauhWY1?Y!E1ir-SHS-U=9@oYQ2YX~%Br5XRoMTv{K6`GhC6skmGsu4
z_^=LrF45lu1$58TzaNMvmG3ZaprwHC1*7q#N6uc~8;iRe|1j6@QjRvP$AvI{<Y8`*
zx6p^F6QY}WahCptoTf|7U`TIdbGVCVw}h6Pp@TQ>jGTG=S-7A5Up9mx2@@gsb1WQ7
z%uie`^7^A-<JJw1uSX(w#1fj$#k&+)$<WK|GGQc^RqT1<CRNwf#(B9hc}S6qv0a`(
zwqYJ<iyq}#_M<r>7z+=>t#F~DR5A1TV5411rv5-Bd0R1j7fBrRAap&5zUKKr8V}Ik
z_~Jn)9^y2yg6?^G?1{|(LD%{91Z@}<6<;{sM1|NC$27OezNDYt+sx#X+&kK=#PfJx
zw@M1}D%LJ<l>)2iM&CIPuSVDs_&Dk|%xO}lXW%lGW#{JI_P=QX%uio@`jxS7o<1|$
ze!#ld7QXiP_cs0gbC<t)`h6`gAGq$%3vWC5-5FbFjM{YBTP4D8pS$vyMF;%!z*#rG
zckhyy@7VVC3oB2*?AD*oY`X8#8}Gkl(>vSWTzUG8H=n+*Yu$gYd*HqMwr-!la{G);
zPv0ADdt==hmmToPWe2R;KK0t8?`{A43+slCxoz8Jx2#(<^{!)PL{AsiEqLX%ZHw+$
za}nq2ZED&2;dKk%z3ucx2R!}e*v@G^7o)qd=jqjth`f-t`uXXXl5=C<Vm@hB+;aTt
z&iUy{W`5Kv^V>(4%(ytR9b-!SGAk~O+o^5R;#I~R-&0x7OniOQ;zU+-$dGGxz0xwW
zpT9a8Q}XH3-&JX-RTJ}q!?f3ALOQxQeR%n(gGyIK6FBZMF0GZ#?Yw=S`e6=Oqjlw)
z-Qt_3$h9mx-@qK@ifEEF^)*XxQl#3ms?$ABSMR7r0dFY=4dQ*Acxpsr3>RiaL-i`+
zZZ)ujoM{{Zs~82Q#UB8N|9wQPG0YhIK0vQ1#as0_bs8xg(>)FZigb_3f|Ed}-8ai(
z9y+7gatcbvLCNSP5?u}Z0U!Hvo1e0LD3*Smn?dXJHPBjZ_ttafK`3T5nI0GSNUY3d
z3XjQ=ej9hQvoNf;KcxL*?{?O>XL0ajdSuNkwk0ufr)|==NQo2MUrmRH$9uG6q*&$T
z5#IFr<ubyAmDN`Lyo9**Z00XB`)`}CMPbj3c421Mn<=F;35xzcgxG~bd(8}n-xO_b
zOVX+<O82~4axC)Fje>eRm}6J51AwJaRyw<=rg9C2QIwud*`z-@$#j;d+$@ppb<$mq
zbOJlx^s`{0dTW1;Oygu{`u#&gkrYCudLFGAg8=5?SLkymj~f>D1HHQX)7xcz_(d#8
zRFg<Mlu$Lv5Eh#(InF8Nxd0D#hL>7K9#Up(D|X6rU*{$6byodCQCtUlMR@B|@odfH
z`NP7JGo|SNqWcd7sV%jk&tqOHgVN!hapVN}A^67-G3DPFFr<}s=Yni_`3*Xygv*de
z8szMW_GWh)uZ%4E7DG?yml%0st+q&WSzUx>zO!@0v@*Z1k%p8!!NjJ+b{=V+^bdM?
z3Zpbnh*qNg{QU&^9pC0;Bv!pn*h+XA9QEZh>{-BK5p6||C(^`v0Y4a*+x;?0#;9g!
zVI*f-mBR97tptxH*F^gnXsOSTSInK`M{(dVBJG;g7|$5t+*IDex0hJLX~TT-;MB_c
zv&|=YhxG^yd4|)vfZ7!%=t_ZB95>^-)b6t%%gjP^5Yyq}Ub6+}&NO*e!jfM=9U1!|
za{wMR!_v?s!HQwX+Xs0z%xNB)42Pgo`RFb_jk?IhmNYmhahm5r8hvVQ^f3PV*;I&e
z7RgYR?#H>0^9nZ8a8hw>i!s7*Qi+YXFtpM!$vgHygOm#6K8DZ9L*d68pELRBAY}ug
zg0<l=BG}Nd5`EAPEmPXGDNyjlvez~cs)K%c&WqPO%Tu3<3Ij@dq*I@C>WzY_sAarC
zEDhjSH>vi70`b6(JdOc07(7~SMLU5xh{aE1l>?Bt$VgwCPxjD9OU+ChVwRtah9HQO
z0acIY<E++KXsFTy(tGkO(Kks+4_JbsQo#7olzW@oRpa>{nixX_U`Aw!RB(r_b`nsk
z<7@X8agI>QN*7&6Ys3-`xf-VlLYll)HE_T#Qeq@XZCK&36O<5g6bP<M{SLV(uZF$l
zQk?2cJ1_xs$c?#4JrAsk<C8C79u<kn?hRQJRuYJ4gi*OvRV))um~o(+MEwOH=o-Xm
zL7@<82a&Z+1CxUADy>g6r%->LJ(8=b7HEW|qgdGzTf#?4nn*zA(0Dbb41jl;5;QNL
zCcOnyX4dOeKF3U4tt0=$rc$Xu;+P$>cwP~owc|A}6BTJldRZ!>7`7murMkgn3p1)-
zC%r|IPghxOhv|t2`~oECyoHv6EFD8u`2%U3KM2>gI3mP(=A<!A8vDa{`7t_X%Mfiu
zBg+`c9_|VTDS=$xOWI%Ldk-e7ti8~@1EBm-UTXj*r~nS#$S>oPGR5zca#0+SkyO|O
zn=&@irlQnkZI$D-BFT>^Jx6r<M1Ov-eYik~Dj3=eUJ;8~$v`?HEOBj7Mr{0%n(EAb
zb5)I&NFM;nks<lzl((JyEeIf?Hcft5$hghj`MqHH)N<GgnltPksIOc_7f>DD(mJm=
zu{ey#iD_0Ati+8GH{6o1#r)<k^CVb4C#i3B)`%VA>o`BWcWRqtkNk9#r(xS}%K=&B
zpHE4^8^w{$SiX3mI<!noZTBb=eyV%7wENt=&quvt&|{yG6?B(S9o@1!-EDz(?>Sy3
zrlo{embxA0O6q#QE^_x3c1vk#{qV<9M8qVzqW<EcjCOt_B07qivuwCR!^x5P5qh#g
zZzIq~^vxbjb~nifX7@A1cISOGe%KQ>M<i3|s;-+YwPRL=2OA7YrmrgXa-2=W9+Fim
z#7H6ev788B8qRQ}KOn56;xWRkGm=yA<5~nnnXo5EtzT%U`rt#$VYPNd(Gc{ey*?!6
zH!BE66`$5fCJ|R_cnZ+p*wz9zz#AL#y;-fYf|Aox$wb>mY;`XSX~;+;G$rlECM+?A
zY9|vO3`3$2FQ$h{m*&ls15wZzeUx}d*Bk0q8oNRJB@7{eamLqc416^yV*`Go^cIS)
zHzkgHkj&!kWa-a=v=&D}_dGo@L48h1VTz6jabyS;N+`ZsLeq;JTQ9SsTFR_@LXna7
z54EQ+79jRq)Pp*M>ZG+y67>hLCC{j3vjB`y7#0hg%=4~yNz#RI@B<j>+u9u-B)UQw
zduBwj<8cz40>?a446(x@1P_Ys)bG6ZCIuTa1QPEV{|FitMz`qgfPo!;H`Ld_X89)_
zE~uodS(752%@PtjS8a{z?WG^7><X<?irIcBjNm$gF(M!unJO<lR0{oFL;T168WVFy
zwZ;r;td|<mBm$ITEII^{Vk}7?sq6627Xt~IHq%gSKvq?P4hs))R{9dl%S6&zx^Jo}
zbxt?L-Ex7)YG*tgd&WW4G{;C$o-4Fny{R84W;ghF4ufzZq^Tg*xt_s?UMv~<D*5XW
ztB|TK4?tKSK#+KVM3EKmeGo-shrGICnhcUU;t1$Io&ME|CKzF{ta^LZQC;^?R+U?A
zKmA3mm_nlyg7jga&fd{d3{?*|Wwn8xBZE39WRf>r9RwNPZC2`xp$jRzlIl+^?*L_m
zIZ?+NA4J0Ij68?@NUW)y+rgPYmOW^Y8SfBlMnE8&3mmOJas<dS$h-qc)CaXEs0&LZ
zU^dQ}*5DH)MtbrvspH0Fxn+>3E-%U$!X|@8(t17xl|k#@h(}pj-vy)5Ez<2AcOAe+
z!o8k2(pLwOHB^FEysej!nT~R+W3?j;tDy+28PVeq2M>$}e-JzA^DqOHbHu>UvzGem
ze2N-HD+FiN<J75xht|QtA&Y`pz{Dc($#kk56?|~(R>{$kLl~2jiDT=*ETjd=2>7lo
z#5gpetaQJ_;(PHB%@7fDvzDOa0ysX6q>UFS(%@z@HCrXAgE9-o5*BF7XLI>bW*xmk
zGztg!u14p0fDPFuP6@m!*?|N|Z-XaG7D=ShidKFKDktDwXdc0@(O!GD$$|}+&H=_}
z$+75G3ul%h2MLrV+xr47v&5{h%A9{qW?H<(XS2Kqd+_hjje6<d*a_kp7&Rgt<G2SX
z;D&N0vMj@>t`(Vu$V)q*4gYu|hQ9zF*Q0g1JR%reYb68xnP_%UeO6ndnwwq?ksPCl
z2S(m2CSwzPZJpeRv{`yjNaY|182VoDWPVu1ltox@+yRhe;9;ucW5|*s$6@h<I2)M7
zVa$#QyO4qULdMEaf!0lo(QyM%s~tG`j1VdpBI-_?<_6;(I%`C#E*}l!NVThhg9sgH
z0+ErB!qD|Wg-fycgO*XB3B!~krPXUpy@%k>0FMhtk}Ib$1)-T*{EWB6Ar<WeDO7z{
zWt2#r9pHn{XSl3;x(r7|y*ydixR9Le7=ew-3*K@AyplQwVg-!~;2IquE7Hj3M#Mkg
zBTd}krI9{)Ux;i($!x&6M`)~ppKat~byI00z~+9HDx<+gQox3IQU#Iq#>k8DYLq9`
zyr&UcZIPj9ffy^LM5;ckcSk$Ydjq_VU8?B1o)jMyh0+X&^;Q#PQGuIEHlQRVAwgD=
zjw~6VvE2bENuYK0ux6=~6z3Xwgt3-a&k)cm12Ntr7yhCRbXNPDLME3QCW%Aep@9_1
zGVI0q=sh}f(xOEXD5w(~?)bKZ67$lzjv&_d;{Xj+52bZ#&4j$WLtG@{b<+@^8i8}<
z=RqjM!3|m3M!3$4DUilnA4o7L-UT0dscG`!gd3eiY(4+<A<Z)sFO~a46f6QzjhSbd
zc_(dN=S@XK$&i!{AM*{D!dD?{BI*n5)FZ7f+;DvGXbkf6c-s-?J{j7%5Q!5~8uDoO
z844W)obJV0b!U)U8L0e#7Q3D#gh@!yQdVfx<P2u$KxW0;5OgYywIuGAidPi&4H&dK
zN#!IvEWCo_TA`i>1bmV`F@+R5EdW?cs`^F|kpMq<mXj5%(u9f$L7bpqhd4xp^dZ7(
z0DbPL;M91HaO%L^5sfhmqnib5Rs8HBr$G}4B`LY!2?;V(=3Z&D_PV8-g;kEmMFtsC
zxyG3nj4Bu>Abc3}LKH%}5M>?WdI}kOlg1IH?F*DL*My!tTI(v!7=rNHwTV}9O3{Gu
z`J@K2ew>YOt`WP#lZ{_jC_XUIQhX4C(H{`ifJX#f$_@}SmqRiQjcCdt$*H=%V%sua
z!LMNe3Ku*`nt@4&oeO#LgJk>wTu=gq@*EN9`v`d^JCK(3_bos9YqGX!1%xmA$QoC&
zy!qJTli_ZpD3*gHzQA(<KfmI!f9+ztbo5kHGtA_wldo=dVcErT*;wDZ1wPe$+>HDK
zUJKzDIPrYi7Wc$0G*lIGuqyrNKRoRXVg#2%7MYuQKMj~+U2|>md?-U{0iVX4;^fua
z#|y}Z()34UR~@qT_G<KtxsUgFNe*{bdw<ayl3EV`9I<U)`~C=J<U=yOw|ke>ed>%S
zJX)V5DVC-F;UsA>A{+GMWz1?cs|LA!i)-0j@vLOoQ*|OP5c4t65%`?8JO$O|W4yJC
z`?$J24?s3l;s3|ny8uX0T#Mh;y}e8CIzaET=zyp-<ANiiu80a~pmtbwLD1C@MdM>3
zsAy2u7aBpRSr;7%AtP|(gFFV}O^_&}Nz~|7hDQt<z2W9{HO7d~_`r8mkca=@sh(Xh
zH|FMl@0aiU&TdzoI(6#QsZ-Te)z#HCMb(eB7(cK~B!3?bBQxH?=2ejPRvVtgdCh{Y
z6&BBFlti*Fs^+{?(GPNpu1|N^P9@!6mbA)fovr4XROPIDan6$i^t7@oENw(5|AU9N
z>V}XJ&-#_{M+wyt+~Jn$)KeH1m{jq2Ccxy1Y~-;u(IJ@8%E))9MunZte!#;m1=FUd
ze87ij6@+Pz2}w!map;opJ2SK>o@JVOR()IZB{y?dtN1b$<H<)(6h(65tp(+hB*aaG
ziwtN@C(BMc&lppJzq%+-n#wc<?Brtafb6;HFw!yB>#D%0b!+eUA3XHR?5JrY+BUuZ
z!1{OBUGFDH4r_ieGp%*y3omuNdgt|KWPVljZx7uS-FN5rv)8_$n_9lp>#T2&7#{6f
zwyf#>VyY?G^Vt6Tf3JV?qa8)Pb?avD+Y`q2Tk!Scl7HIPu6DlG-g?_F4yk^s=eXqT
z@z<#9X20A1^PlG`az9U0&mKFib@Yx&*ZgvAR<Hf}FRLHjF|G9r|8{o!E02v)zk0HV
zcg^^T!$sd|*RUDj4<`kaMh%$#$y@K6U2naZ*m38Y7v8;d&EZ?OKG4k7a{KFFFWmn6
zkN)_lJMV7Yb@1J1Kf3gu)`ynfGhp_P!}`zMaoEJSe|B5b+qd1e-`jVOoV4rik>~Du
z>7m9;XFN1u`p(z;&))g^{=eToy^d@DZ8K(_v~$L+FYP@3+L|55UpwHD9hY6kb@k4t
zrcQeOsfPV_K62LZZI7IF_N=eH+4||Wm(F=^*8%NZGuJ%%#o?cB{NiZQH~0dZCw827
z&CVU?T|R5eM{3uW-;dw%`aNISymsLwTR(X~z4pli;q9-#x#^+T-&`;!b&vVuo%f6%
zwe;}l!DGLfn6u-saQ4o_0`#rj^|PN%c=YaLvya}r@Aw^`J{0cS{!rq|5AUqq`pBL2
zr++ZJ=1-rT-D~HJFHidLo>?dF;CJ$VGPZx!Prq>46+3pmch%0GQ~PXta{B3?9(vX_
zvtB=I`u3mw$h%_ao59Xq`?l}+<di|%H=dFDwDXLkW$(~F>_*u6(LOCZUp?cj!h_#^
z^0#+=*Z%v0`=)bLP22FyPsa}*`>*Eqi;f+zsBz!cvp&&h51wC)I>Py9FA7(-9=7aX
z2fTmpzed;Ic2MH|O+BI~p1Wtj{G0Acj!dP#G)JY*{Nsw@i6<`_9{#D6sej_kFnMU|
zYv;T*?aVJewPj=Ck1ICzzi9l$6Q@tOxbFO4O&RsbucjRPizi!-d;V!NeAL;^qh5Nl
zdDh)`oi=CZj?>zIca4Aaye<9_CoiZ&ul{YK_Y>cuZJR^R?$6%z!isP9+Hlu5IcH-2
z*~M_aS#fY@;=z_q_5RI295CnU8`YdY=)|onizefxCLESZjr~jUUlZ4i_*eB<OD3`I
zcVRg0nR}}G-*iv-?aleqe_PC(iJ4^8rq`4H)P>`YI`o(08Xs9U;@mI1He%AplbWyo
zYNC0{MLh>swe=iqezzri_1a8U^D89{dw;v7QT7d8#69<xKCRb|#?z9sUz@h5bMtS*
ziJK=9qlRiW2;7vZ%C}~!dbF>-XmR46pKQ`UNpHNj@6a1Ey=sfeTesf)bShnaYRV5L
z{cxDtss@_{w}maa0bz4gzqK@AvQ^90E^3+FRCmIIYOq@UmsD-kTwgs=)i>7<RN0jq
zFG_xMfKEQPNu7P~uvFAk)XBv)NBFlqc3F@1aB}Up?!s=R<i6`#Ie=%iiGs}&2i0$$
zNZ+B{eykRKgI}v}xcSP`<Q~_Q+IlTJV(965$<RjK>xd=jx1u$b9ylrGtBD8EqaWTm
zZQhcw+48cW5It=R1D-y3nOAqiWN*=;;a-h-P}Q`cTVGkO9gyPN-N|a)!n_WC(X7II
z|Kgd|jb3%d$){HJnSbiO#g@rlF+W+&Z%x*(Gg1G_)pSzDHuUm_(cL8`uH!caS*i<l
zDzNmctt#J($fU;^fjskN3Sq==b?QWQr$#Z&1R(k&E5A>MR{gt@xdty)T8qRbY)itb
z&?Z!~Rr<*mqsA+%#+SHlh0hrF^aPsyP^zzG<Lo%;W}6M~%EEJa-s{JMT~%wS_U^Q8
z`^(5yjb0`Udzip{gL&&-$QaI*;2I)(o=85R92Qy?{q`h$YQgawjh|MvS&5VUrz)A~
z5$E&X8UHXYp);C!PlC08vsb`9s!JNtU527+u0%#fCo5kK1ebkRlCBxI3W@!}C0yUS
z4{j>xL%gJ~YV_Rq%I)Bx?0G7nH%p8Sojw*btfTR3cO)H8$oeWu8jC$-`B_%5HB=8d
z5qg9^W^ppJk<yGdiq~AcuNA>9E^qhFm7sg%V*V)K<tMO5pgIx7@3kuGg%Ove6f@Q@
zTyrkz;VHyrAo*^PJx~7ylAc*-chB1S)mpV;nr4dSRV_;7Ro?PFn=bkc=vcl%cUo1E
zT%!C%nq@bSv7SQhmoPOgo$Y=hO!*s2Cb+(t0yHc0_}Ze{@yX-66y=n2o>nhbYR*Gn
z+x6(Szw}=7t7E+FLzccf=i#^J?%MX38^8P3ebrkIU-RycHT+iSwuT;`Y<WNT^ba52
z`qsm5joS72sxg1sdEdN0-m`7%E1ymuwf*&bDxRNy``YIo-Nw(6&ffonr&gt&f9v7(
z=j__H<Lc+P?7wEh9PgPe4^RHpoY&{fcz$Z{?>#lAcH8vrZBKpj_}mMh+tT~_U(NBJ
z+p@HM%dXewe4W1h+2`J`e(Iy=-`%lm?5_KZUSna!ylH5gkv&9-<+Y6~jhFeiFvuL1
z@rIpt)9UcoUt8TYKRG-Ya`4Du-(H@h!RV;HI5<j%R|GwCxdD$qUaWum&=t{uyZG3f
z^VG)XJNo{|Yhg4gzapxBN+-Pa%Lg3)ax%GONZ8tU{O0f*6WWq@>P#{dWRl^e_5q2O
zvl45YTEaHdl01IFlqj(vHDJRQFKlVfgl|sgWy64z>Ym)v5}6V$f{F)d{=CmYUjZFI
zp2Y!NBUqrQt3ANRX<~}OLzFN%aWPd~DAcfIKm-lTf$-QkE+**M>vHApf=8&oV;<VY
zX~BjtDdbjJ*v3!&$R3j?Hs{B;25Lbsb+0x|sZZyWf)adDwYI8O(^K}3+AL?_M4@Kx
z+FE5hQPgXBF}K>1M=H;`8yuLzbUz5Gv}Bkc$8@eO^uwHLDCMJ;zMA}UdD9vkrC7Vs
zr$#crE&Q1MIJ(UrrkV5AFooS@b^T3DPZbYs=$BZ1M^4qeO#L@AA#KP=$xC5W;wYLl
z8>NDO;ZPSykEPYH7N)w|)EJ)m8-=Y^Rqz9)yxL%X>b1U*t4Z|10AbXkN=2JEKHyH`
z;ESyLz)73V4wl(<C4B*%M~7)Pn1@f1>mI|)n*82AyRUARk_O(1${dewyo17S`}~^D
z%E$w*bYDF^?WW5?N3fU9^PaleHX@J-tfto56bIkYk4UwV-iB&S3VN%0TFL-MEnkpV
zj0`EYH${kA!xI$ut879rvipTGCcFtYo~$}73psvGLQb(#vX<os9_l3yEhsz8V-}u}
z*ByRP(dMzKM6?C^7?(?t?3&R7N=XI2PgbVGU}Jf@szo;)Skw)4g4dRs_RiLhY^$eD
zE)$9gszR-RWUgKZg4A-tk#wkmH6-?p&3c|^eJ@XtKDq9<>^uh1s?=0Nz6x`xGro@j
zS}oOTNa;0Cpt$*v<t8s2E_PLG(VyklaXiJSwUQ5AA5hXtoh9a`Cf0eXffu@_E{Y1u
zvskIn(w0LU+hj9E#g-GE%q%70PAsY^oNZeKtx%n+h%%y2z<v?4#0fSXNbg`kN+sos
zoyclAP9|y5NhI?06lBw0s4OpO*en~E4Tq)!_SUA6gfeWrP$PtqK-d8{)k=#pD$qQ|
zq*#Y85mPD8R>Iz@c$^F=m155w!h;rEV_Ouu1Z_FLg%^x~Vf=KdS&|I60d!rJGE`P`
zf-Mlj5EVLA1u_J8d!Bkq{n77e+BG6XieK~zO0Ej&f&o_I8vTF=JepW|hqQa)C{c|J
zI@<4atW~n#YOs}a4N;P|=W>NbgHFT&crT5T+)kF~cEXmhr{teD!W9@u83`5Hl}orL
zi>uLv^*IU4T}@j7_j&)sH%NxBorqMWOr*v1PHAq(7_c0P3RVq8htNp8G%p8Hjiz5Q
zw2w>`=^c$q5@GHhgg_GamMfrY+JvD60o*Gz3{jeZQS7aDD_YPEH?%xkQ$X3hC3~JO
ze9b8pbEicu>r7ix>R^eHnFm%uZCObU;!_YvE<lkjSvY=fBe9gF3vgw!sX9rU5VK$j
zA~>W+cmo|!dKwYXDeAR=v`W+o8i#g)D{=(Hq&J0~Fx$KYsXD;&Sf8~{8hR;fgc$3j
zoj$1IcH&DzI91e^Gyob(2hkYSss`aHQEZw*U@#RX<mQLSIju1_GRcG4WI(KReJ+b6
z)d{;sAm%hI>_lt64Gxzm0U5{*Dz@U$TExZ?)rWoRp}0k9mq@8Q45~<)(h)?|G&Ycc
z`>RU%+GaEo>A?i7)IlIOk;aI*+8YExQwt{xoMD18@%0$0lhv1CYvD1%$_%pu3X2d-
zy8}O4=&6tipo;5~8DgXlAT1O4IEq+i$}5yc50zXe1yvL>he#=(PtGRengcy7D`N+e
zBgv<Q(O}-`*Kb1E78~6fMJe*&fdqNd3b?D9rRQny;gk#`gpjd|t6;s2c`NedK$$?J
zWZ<||mGZQwZB!w9ns&fVH1|0Bio+f)=~n5mxHr&BQ$jIK4N8Yg44n>lpw@NTP>dDD
zX5E*14Aar(#?TgnG2BnIO3htzvvH@pBO}rz0W`ZFY%XF~++9sH)O=vRgx;Rl=KH#n
zikv35h1T3Ym(qvjv`Sc2=txKH%0H1g0Jh|;LG6~ElwB6u{lsXjqleO+m=1bbx_&n8
z1<Tv2I(T3Ui>AUFGDdYiu<u!~S7?<^`N>*Yt&4m*=M<5th09n?G#gW}F?J8la_E$6
z9icsm%JOnlpjMMpp}N?*MyxGMa09cA*i%eYXq7!CkI*Xwomm`beHw3t7J(KH1OQqb
zrQ?9Z%MM+3HL;?Lfmx_N`pJWnv~nj;_R(o0^=hS6G{C_xED)y}r0-DVTF#*W&P^q<
ztc8e4T&xDK;f8d)qB#Z-S||)c_M=Ws7w;dWlr0KP<VrV7*U3&YRi%9pSmC8Jk{|Cb
zkqsf?wDiDkNKhG~1G#~uEV8RoAoM5_Pf>zOgDR&oO)txyWl_Ysz6Rk5-wH1vcBRWx
zZK_hO6N2;^T2;6*C6m&_kxa4?k6RC3Eq7oiDrv1ntmrBok=kHN^ay#O0Mb_rNDrma
z&WOF-<w`A>ALxuDSqh1SfIvA?(%N`<K^K5_i7%TA3?X)}fW;XQtk*ohiV+=HY$sMr
zE0w{B%qtCdqjcInQv;-6JdvW|rad=`<5&60NZy_n&844JDd~Xs$OX38{>IsDHHNQK
zm@XD+!IfI(LWnk^1Br`~veFC?+ZoGhAueq7MFkoNU41%W5t)$kQj$b%(4b1`25Dx1
zmxq_~<GChW5qBJl_2k%G7F#Kgf3b-5NQ+6hJgFvVlrZauwn^v}l9O>{oR}9x(f2dZ
z$;82#M{BV_8MI_iR-!FnovY~E*fs9cy2(Ol+By^BX&Egow~>L`shmPEh$$L_rB6d7
zWRX|yD>1zAgh|<_)6E_i-?xw?YyM@<B9n0Kcu1uk!8*j<WuU@X^gRtGrY9fO3@X+W
z{<wiLt#D8i*s>5&KuQ8gV-~=(;^$#TcR{6V5E0z8);L1!(7nY-5Oh&<Wz5<xJ&8dd
zcZt=MqG^i9Ly5~+x)D#J-Ppr<tP<>oSaF&8l+`N0M?k_Nt(nw-I9!q2KQ=QFOO|*M
z#U&^ZbUHVV7F0V1YbAZdZZd-0ZHP=6rv=1~rHGv@myF>s2!t5=CWl#E9amW#rCLoa
zSCXL#4Au?j1OZ!?5Qkdg6)DH%D9w^qcf_%()E&`fc?3EzqH%Y_E*p)sl4&;>WzcO;
zh(EVMD&&MEhRY>(>16N7aRsOpNeEgCN|tg1X|DLSAh<%cgbu8XH}oS`0iEK+w`7co
z+cgO$turR~FVKh`nKsM!GU-rB*N)Yl3TP}oc?ocTv8%ShB_QZ&xwj<34TV+}g;6_#
zbAsKd!<OMXvCOW7&?=6|hS9o$yI3RJ?5xBHUE(E^YAAqnjq@E!nK&I%0i10q9^i35
zI5Wz91DJU4$U)WQ<T9oQ*h?!daV}Q8Vq9QBT}RB|Ah>IPEwSyTvB-mvfaXFy9cNS{
z!Ey;CJ}g=x0M@y1eg<~uB_g!Tsf)p|Txngv;5yE*6HKRsXcf#!XLZX?bJtxJB?7Qq
zafu})Xk0sch>r;--mb{klaA4`3RBEj5~3CdH|iSdT^L9DSk4HY?+h1M$wdf2SD~cc
z0&+(P#6qp((vG5u=wcR3_~nXeIxsOFivf?zB(paiOA8>z*&0_14v+J3YIPMH{%(-I
zSF5~dNF4t&xrrHCBnL?zH4D4ub*F14acuck(AXL<T-J)Fa+OtdT_VBVKqqQkNZdH3
z3zA+ayTO2#r3g{J*N(GIy1Eft9`;2dESIRbyYC`@M}X!uWA8kEY%5^|N{&T?X(9q-
zS#W`L-g(lVT@tN~c4}y$%LA_nLLdo^&zDB-W-Uhwivuef$aove6~v)B?yw|;1eZm*
z4q=pWTT4`|KM~bT%7jxoF0rbJB*z%SR#9b-={2kZhD%H!krIw6E>I3bil5?boVo19
zxzP>5^5L1XJbE-px;WNJ5!n)CUWQvXtd%J3!p_kYs6#M0j8-xvtR*b`E^qXg44^A3
zWCyzJJI}G%iY}4`>B_rIlZJo|m}@&;T`Td(>#~c>GNzH#xX9SijwK2@<6vAoXyuef
zS&49yrLw*RJ!u`~0%L-B8YC2e5kZTO0Ox~V{4kDmucWe~rP{4ReEyJRYq%Us%mJqk
zv@j#dWk+l?El;@i1SSO9)q{mqt1`&TC6~0T#&kIX>9z|kfoT4$+zbM7@j;qhkg!CX
zIMAhHnaLxj3zAGT5n%|&^QLk{S*#R6HN@(GYZn{WR5?o*=*m8hcTBM@AXqS@x%;Oa
z6RS&vfY|ZZVrQrY$szJ^B%Q7zDH9W~d`MdkD%nYnDT*R?La-=j#OngzWf|)#Ej<3B
zz;VWjm5g%*EBx&2K}_6-8zDG-afR%4*-h?PfMU=DGc4k`Ai2xqno6<Q#Zc~GLF`!-
zm>9$Dsv;q@#2Q1Cx}YQh$_i@eZex|pg%WNRbl}kbbQcko)FvD&-JBLWi4kK(2EU;6
zA&ka7I1v)sqz;RMKtlHE&|i~O4lz@F^S~q0KoW**({Uhj0*7_@IqAO|R7LmUi=7=Z
z?MfpwG^H@SHLvbd!*oL0WTK=p?0oT!O5M(K7-NE;SAmxK1-Bmqi?)7}ryg*1YQZ*!
zL0aF8eN|;fg(cw!_hmlIGIE{e+ZPt~IK;J<%$j8((bznCY58o<t5dSat6D~`u$fjB
z*%ox@K%Ay*Imkp%v~<oew~6RaXhF1XZSjIrdH(1?Ou^HNXR`7H7e&QxqF>yWd{xLa
zpn0uyeKrU?-i;@UR*k5F$({4`FL^LcfTf2HT`hD&1$)I6ZjX_+a?+B8mcr~c6%8y8
zMH!#s#PhDH#y3*28_1^U-T)h~S+mBWQ4^_*6M-sr(86qJGqf+;20_L}G`D`gHYS!l
ztR*2(&$>FadqtiOt68H{33&y*L?fcu*YLX(m0Afz=UNk}jC|sgcg27v2hr+gJ`<Z7
zFi_}Ck&>p2`L*%*h)VPiGj5(~Ju<TWR9YUR@`)(tO@zXcU@WdE(+?ijy)C1hoNv5o
zh@49$1_{w$-61+sT)BauDAP(9nwj#AO4*a6Unfs)iC3>5GjE-LV`nO=Z>hQb%#B-C
zJih+5msCf%Dmf%G?3`)e`u^9}71utS&G#BLe!*cwdcM5%HvPt%w~Yz+-S_0=sN)g~
z-@QyPf9M4h_U`A02kaND+S(qy@#~4H;{4tf`9t=r8k9L(-SgUIZT5!V2i-BYXVuE@
z>^E)K)~)8{Uwktt&Oe~?!CQ~hgIXqekFD?9Bmd35Rhi3=`zX_IcH0luK3-K?U*E$F
zeeOBYcb^8OzQ2A$`rjWoVCSoKi=TY4Zt;?qy5IKPvhc0_?%I;<_1c!??N8itz*`F+
zJ?GK8ezh~fbuMwg-15$M>fiok=_PNxzw`_9A3gr<8@69EYT=r#Q&z6odfID${!YWH
zd#~$t=^xHZU;KwN`geSAN$~yUXYBW*OXr@r>e4yqt$Odey;m*WZ|0+)ULA~@JNN7#
ztURM~$4SFSzr5EuJ-GTGwsgNsS6;TGX8z-kT+nOdBXf2<JA9xy?YX|9Z_h@hR$aDZ
z=G(WNjJ~&YzF2q5)8pEooAB}v-dZ~Ksbv1O8Oh`u5A=HLyKAod<gQ=6;}7}O$Mw?}
zzLMCo^Iz&;eRk<7Z){(5&h6j3Zq>qV*Cki2dDmb0$O}VX+qocEwe7m_(x<<y-uT0L
zBm8aC2i>^xyncsYI`{ZhZ_hnv;StvbgKnvwIp@<)&7VH~bifTOzgRhY>2dqM`t@^q
zy!y)t2mIiBJ*Tcba>uxur*~ek>X~h$cB~)HL}A)S**kRh=}O&m<c`y(c1+rGf_?9g
z*}}HYmisRI_JVzqy*BI<JhJif%7fc}-8wsbb^HnWw|{fq#z%kCvt{q({?n%RyXcLR
zN9?~c9MLPka{NR)>!-fjK0j((K3`8$-kC$@*PgJjIHLdjmqz&ZD~}{szH!d+%FH?-
zXu7(`g0;1Ce$e!Vs=H3=Is3R1226c))j9iJdQ<YkEngq-h1Yrw&{KjV2Anq(JGOq~
z?D^h;VC78%zBXp{dmCF;PkUOa%Q{8xji&{7x3x~%G1YIKcB0)@*tq7`r=VB;hJBJj
z=P{KdR@NLbI6uGn^zeda6TbcHq<LtOn&wxJn0BI9{o?r4$dzv%tnB2w_qUhbq4aMS
zHFh>#U72{H{_MM!*R~zDQYV-6>N)khC!cf9{Bdk|F|+o2tw*Bb#mW)MK}|=fhA{)K
z8GO^X*R8DHZ|9|FR;RXnF(La(hRB|$_kPNWa{a!2R(?o6v*Iut_42;2dhwf472*0p
z2i82Xq@&{Cpu?*T(+dliEMHYfPJJ{;Y~U!BAUQ7+-1?0pR`d@mZC&#C0*m8?C==P?
zJvUmq<J`1O{<3Ks3u->c6kK1M?L6{3q5Xb7+4)c+-+AAFnm*AO|H#@gr=NDyxR*~G
zo89b3jp=N3@ae58JH1t%=!<T@zh9{)mQ<SfT6sm~GW1%`^?fZJL`D9WVModfxOmaL
zB1(4_f(;9U#MC>2OvU{5w>L!J7?_EY)tM+fIDJQ<wh)bIwn@6bWM$Y8%`12-N<Gy4
zYEO0W$PpdU+L>OE=p3p1&Y_X@R%~2yq#ctzJ(t~l`c32Rum|3D_6<>HNVMq$KQh@&
zpWK+b7oL*QiBYpv=@Sa6$SN<x^FN)Jj%3dhomm=12{#TSa1A|UqgI}r$}>dyVUaCh
zLT}}2<7%{F__Sp)EfcbQS`!Yl^7>WrjzEsQ3*}WTvOHCQ#<&_$e{TPejDeOY`d|9k
zh*!g7IXYB%vynN{D2~xm-o={zYqF;)H4>_OGw1D%--wL%*cUQ6c%9JjW6;b&8<9Dj
zAo)5vVSl(r3Bra;e0dmOf-K+D?%hhkDE)i7^T!xDiI>YQceK#M3ociID}ha}rRSdn
zE@wUQFFJ9?1ADP#Pt%GE!L&`{hWsp+WJtWc_H@i=<K_8C%`!qX${Mheafnae!8(y$
zkIzC!#8{|;PN^x33`Z+diV4KQtFl}O)7Z~F#zZYVZy;#6>h$=m3e;j-BZDh*Ic7Mi
zl9QXPH_R8ZdGe4l^HuX{Y|8o_8L?7|WGTzv1)p~#YG}%s+>f-F)}|BqW3}Gw$^0Ww
zed5Y0WK`N}kG0i)Y*z2b?f{B6IASk~<#nZO!Kw^(I#SnvOJNNabX4-nA5%R&XzBaY
z-{01~=V{|%>?^u&?5<VM?(BX0DWfYk9=>$z^xG%QxqtiY8*hK-$JHBGJ+pPo(o^O<
zy6w;&i!S{j_xk<Yc5He0oYD6`K6lJRa~_`e)~;uEZh7{)QTM&hIZtmdUHi_Qr{>)8
z>~;Hp^7!GYhhJX2{;BQHagNh<``<Tqw72c8-%OtV!E<vDT6$gY`<@zAyX~!8+Gc-n
z&YVHd?CAaDUybs%HLPiuJwmsRQ0kU*?yG+4>hHB@exOzGf=-9UOdWfk`~^MF?3`a!
z{Q{eBa(TXv4;Hc#enZaMi*Kq{nO^i>l`5a{Y)6(kx6F-_Bg~M*Givh_`CM_|jJJAt
zlGk{*)pm63yJ%UupDLE9O1mr?vaX-H%P<|mrm8pgJLy7o$3;wFbAhLy*xM{P>Bxkw
z=4Xw)1k<zY#%ue<gw55vJxv#2%^;UFRfGjh=mpX!ku1(`(7REGNo#N|!goRA+&vvF
z(I^Dan&QSoODdCun3Fh3&h*R(E<i=YqeFwYo7n|q56Px=4s}k+s>!}ON)jAd^c(C{
z4HjISVCL9BhBwg!foLGPTPc~UOij*P6<FS&46e!z4^>O0kD40&Ix1~T)p*}GUS#Yc
zyqOIund61gpyKjG1KZ)VcC1@9L~>>@9jvPJqN&^y{Ii*T0cW0ME&EGU(3gWtrjjcQ
zok5*pX*FZDW?kDvYK5`za=-E_L*~A<DPF*YjrA=l9tPAH%z+|$UT}hsd;)EaxD~`D
zr}Da2*6TF~rb>sPTW?U!6faB^<}m@4-xal<YL1Oe@9FbOQ#uy6783GGoMQU*UQ+LW
zGHb5u{77=b>Y-PR2D#q^yt|dGWuK!VPwSNuenSf7HjCXfeVI{N<6G64sX|S8UDa5t
zGt|$*z_xH_=klJ1?P)p{9->?5qom5&MPxa!&iF~g8{o9^Vai2TJ*Wn)MulKsPbGie
zX~BGiMs3h4uqSPR9+oDcd6MDx&_y%ZVMTKAc@0keW=oPxOPzmn-qJ8S$*;omvT8GA
z-X{&j0L~t1&fnsBMpwGGBb>5^3@Ujs&p9Feois^ff~k%4T?g_^K>N@eRZvJJnb`Az
zXygY2c;+&&>9pE=oyDi5G>uT&<BN<sUV}}vsA`PD1D+ILT6UGfJQ)?-K@L5s5l(<5
zqLPb2%fl&P=LX4r3hEBGApGo-RVn3}n@Q6~m|`P6OKYIj-Ab;00s@g?vyMzi6QEp1
zi$)<M$Z5?gN5IL%=bT8|r<HX<#&lBh6M{;3?}eqsfVPS~ONawkY);^HgD0r{IXXH7
z5e}$gKPPd4##~vBJd2t!mBeax`+*p=39z|X9fdIlM-2zY3WfYQ*U!KzATAGHflmYE
zD-ca<tTBQDt{JTSclyw8NboZds*-V~TZD#PF*-(^C&h3`8;Ap{kemfNbvXy_4haVa
zC%&UShe>!3kOryCVdM%=tYKV-8k!Mh1xn&{hy#V=o8ufMOg`Fq&XLJZWjV-;r7{-V
za5q<sY2OMWYDhMQcRS8N;5CjSv0WO088Q`#Rx8E71F_?J#-kXlcv_s#g4sigi=nR&
z(^%Ey*u|=%0$`oHrz4SF;EHX_wo;zm(+(m)Q=Bf|*f(9lZZV#li3quyBmvJ8H!iOh
zq#W+{#X?>7*(06~qZ{@RQ8ra~xw_<;Zsr(q#g1<Y$Kw4pL!77B`Pefg$!FqaV`Vph
zTJ1tkD5!BOBicA3P6m?G(YIRe7YDY>4ur)bQpN)%#<D6Teiy{;)ftUWtqk3W8yd9a
zY$U2fd4+hmN20G-ID%NVu_h14q=o7fighX5uiMO;G%6<!f{C<(D#-(<RUAX7K`4F~
z<n9|;CD{!Uuw0r;;J$@Q{aj{uo-OmG=q4!{hHR@d!U8j$E_bh#SH+46RkEwI)?qjl
zTuyJKLza@o<!Iv2N^Qz_t=3Eu-0F`oxSD8SNv+%!wu&`8Wr)H!;_iOk(?K%V%~56(
zt6-#<9VkPGCIi2`T(Z)Tv8{tV9XL0W)1#w?p{h+L=}}X4T+bFJQ)8?$u1YDb%hOT@
ziQ*V@gH!Km@OU{5#FIj@{^$v_;quAM5`l$I=HcW?L4jBWTv&E@MnW|%R$O#(ZdaR-
zfEyX50m)#CAsvWbnyaatKyU%=+_;IBQS1C54y9vH>=x(b3}<4c;yCAuS}_E+jEKjC
zr#qbyog57(6QhyA*UDPb%k-)nyfRi+!%EP^PpA&-zEwyR^N8*CYZpF1m(#_e`1P5X
zJ+e@Ck1Z~m5wff!Cxr<``kwGJ0w5Z$SSbs(2kd4{$6~}zT#@H#W)Y6lh`XDS0HP=|
z5L?wcyo<)*5ohJ71~=>qGi`80ofFSm7m&H8!^APMT#0Z`k52V6jrbT7Q@g&yNb8Hl
zcB6I=aFTWp&_)7*kH?I%4IGTjxw`ZWz~yq_5oOA_c<9W^YfLCJ`EjV+Jhg<Fb}PBL
z9Ee|A*0oHcw<}}a?WAm!n6AsQU7ov-%Ym-R5XbO2ip4d8af?V198MrMfm6bf+{kTx
z7+qEt#DOmR^cOO}^d^1MMfk6NI(~HiuMwZ6NGAUbDBI}275$I${kMYt9)sB8H*fw;
zj(=A9|7K=?gZMuw|NkUSch+Ky4R3V^|Nn~ougds$3iTPeVvBjl{2lK9yQqJ5Tl$Rd
zf2G=A$909f{J&!V+rhV=`rCA&{)7F==L`7X#r$<S{yO}5(*IGu&rAO|>0*l>qyJ{q
zUlaFi6MN!+&G*j^|5NNBO1pM(`2R}%|1a&br{ZFx|64nKhQID1rJiG-%>TpizqQY2
zbo@KI{XM?F7x#BWem3gDqdyzoGbFbA2cgRzUA`pS6aNRrbhGVQwk}-!J@GE)E?QT(
z%iojUg?IT~JpU74lgOJoSgEBgGSy|y=_s)%8++pNz~v^4Oi~R&pVucsMg=HMf&w}&
zlLckUNyyoa2T%(p(^<n+wj{|Vna7nv1b(OvOgSAqrOPqh+)8bE16mvw30;>X{*7=K
zUHrf1-81h0Rea|8pP${!D?c}`Y_ZRc|3@Ok&i^eu-1PY@e@DO1PxL>J>C(5$camCP
z{Ct5EFaG?ve?rV>^!hycqSFJ9eKyt|60AQ%i|ZFx$lMFgiJ$(u2toubS0P>`mSAYy
zA`6&_pSOhwSQqM&fJE)cf93q`W+l(e4QC1Ko+59K)4Ec}Po3ImXvpB*uzPxU>@}PU
z;i%Sghd0UU5bqRuYag)Wue^*Z#FEOcP>m>RD<#G%&#ErHV-^<w+|Ed-mOqxD=pzD_
zxEm>zj=KuULR7;ZK#&oaj6Kck6C-^~Eh$;`leZ0um;UaQ4Ii48MUyPVgo`OJsBpNl
z+XdPgSi@!lO&n@g8hn;g@Jzgp=H7Bc1SqsJN^JM)07oEu{sCEI|Jxw(hMcu9`Sh6a
z3OiJ1I}yo?m~!^4RLM~yEVhdymjh%6F^0iGOdJq5h)d&RRv;&iB;!SxAr-(bJMp?@
zIfb>XB0-B;;&>~W82B+>cYYcsU-A<&z>)(B>`q36TM=}TLbi^Tx`-9d2(!zZ<;8L#
z-slwWKv;QGBRGbZXh3XBcI-2d7FGrwqgsX=fHBEBghTZKTP3;DI6YbrtYV-pbz1}@
z6**d{qDUi`1Ku8rpT$<jRpTa0ixUv}4N8~G8J0_1p-U18t8tzZ4lTBjwNUrVrU45o
zEa0-ni&boEj%X{q(zFAMLzQd7M%vyD#5!<mM;Ibu#MVxCW7If_i|QS}pp?zD3Ie#r
zMr&N=1SOFdf3x3fol-@D2s4%p<drlX#h6%W`FuQ(SXIModWXnS2@5E(XH?KB6f4q{
z(i+E>_=;DOdU9Jk;LUTh@|!dPjxqAAtJ{FclCsKQw_4S&woWe&*)!a4k#A`Oii$v{
z%e#XNJXV}xbBFoo*|X^naq?X}R=|9c9hZ1GvD(aug(GYe&zCrzRz^6KmFm}mv5N&)
zi^5|f_db}{k(5e1QC3_@h^VS~%{JbAD_>mE{1M!+-xheP_)?Pqt=)L3lC0fIn{dBV
z!gr%KtaaiVy|gEJlYl0W!V7dKt~5tuwd`*e6-u!1?o*5;_DXAE@oNyT5d$gE4V;gt
z(kzt<KTvRV5aep@Sql@Ek;qCzBEp8oOIjnN105<1@te>j>%{CLu-FxlALEeq;K*j_
zW8;dT>L?h>S(8>8nWWaV2pR!pIkl5av4urJFbCX_6d~kCk?5?_DBr5B@RI!)DF6Y)
z!S4H>_1&kduBgWI4P<M*cm-4wkZ<x&%z=pRao)6~J475d*3@6nxw;DZmBz^0F(YBx
z!l-P@s&KeVB(FI_juP=RvP`VWSSy_|oA|m3wHrfK(?9|MF;;o_v{eZ=`vkDN-5YDN
ziOd-gk;OsutdUJ{JXMqMSuvpU`N&?{mGx{LCrqjZBvFGg7_VF5wQ}-PDEuA`npfYd
zS=4nogdL5dVj3|*;T2EDBOjXzqz`HhpcUz`jnD1mz7>*9#=$hVSWbpYt0ZZ)QEadF
z(L`$A`c`@tAkFXB;c55gh?{^jS_If>k6b{$+0UT>U>Ho%AV6Z9II56`+UU0HA=iYS
z?n{pnvZH_|G+fot_9R0~NaATE${6_=z$ia!YvmXZ>9MgKOfAjI(?w91tr`SoOduR+
z2Qgw#c!_-v5F*u|5{m3;G&Q=82qRbu<x$2G(Is*uR-QssgS-~Vv7rLVw4JG~&?piY
zU-<I{Q9+}Qs_;3sWyoX*1@3`Dww8V3u*4ezv}jC|9>R@I5umGF2kN1=bA{lBv&hq?
zBW6&6Cf-3be+rtmDeA(+l=A2FHV(NWIvYilJsDWai*eZ-r?TWAdYJg7ywH`@6?}j(
z;!;3(qzf`C1HVh)k(p#z29Y6<;(|j!Q=1l>fO4oq%wWo@Km$CDBM{|8Hub6FjI9vM
zz#Pd6>I6ueMZWv!@d(MNSza2NJBT;J6oXc^S`wHz$S=T1!xlvx=(6woVz-5-ILkou
z<BYTl$_!z#jJU|%IOi~#ID}HRP4ob|Qh^!?)0Ih<zBED!#ufmP5ZaisLZp^r8!0C;
z8XaE%Ef(u{RYojT5|_aVD&vy5lNTq7socw&F`lkhUdPZeYA>MP+}Pa`v+T((jQ}Yz
z$umZwgM%*3T_sp)^MK0@UrRthx=mja$KUL?_660H39|4qaL1B`Q(%Juk?~I0To%%c
z6DZ<9l=rJ8v@NG%s4zqbXy@YCE<~vgP=wIHQ!%kSPLN4L>#~=H!ne4%f{`kRLoPC=
zcydd0Lm(I={v}DHsHKbq0_TFb`@q#+T(4UCO2B<rUd~ZIRB?BjmYC0ibwQVr3gnyo
z!E=PtsIt_MW=`VbF$E!nDy_jdEGs5Ew|TcA{8+oP#%NovIxCFm?Cu|U=#v1eIA+Ag
z7@|!%8Hw%?q83MS%kP#SV^)=<XLG8+rd6ATC*T4+jogwLK>AS+O57_Tztb|0B9`h!
zH37p_Ogm44qCil@%W`Q3RG`zwynzG+Zg6gwVT8XNRnE;Kh0GBe4Zjheyb2<zzqBf}
z#w41cJO3c={JPA<u;w7L9pX!(C2$*2x!BF*yX3T0i5I}AoiP@hyUGPVv&*TEh;TNE
zlSzmU!ATHZtxM_hlAz0>TRxPM5Q#2#Q4&HB1YwoBh~*P(0_*N-B-Viw3MN_FJt&NN
zK|vdOXW=lCfdlQDnnO#4n1n22aIkH2%V!md<a^ymPlXR&OOFG#EY33Ms(jG|YojUs
zM*=}*pbP{cyIIWca&&1-WDGeK*ccPnXz6ac2-4LXAxnB^6@?Duy$2Y{8?fRSu82vp
z-~!A?W5hVm%f%rvn2hVpd(cNz@{Nr9OcK~_x`*9$oE@f@QcAKIoVA5O%OihD76ZMR
z1DCB4ROAYXEr*}kt-V#s7#zTvgxQ=6Xy=w4DH%VAv?pmdZb9X8z@)<lx*UkLv4rFj
z5EYB~C08XNK!=;TS%-_6tV`Ca9f3THAeIuA%N%zoF0w4v=>>-oUMs}1rd@4OnB&xz
znCrXZ!QpkK77l@eb6cIO=mIR*<~Zb@M)FF>A(yOKZ27a3pityeIRX#CMt21XIIv~k
zMF-u1F2ve$`KY;WmFTTRN29v3ZR>P8lPxqrbIl9*5!{#o5q!`CZBMWgsEo-5)VhDt
zw#A09<rJ}^x~v9_fOT${Bjcs$mh0OXlRPWF4lD{eVe9Y$!OP(4QY6aV1k8`=M&nDG
zf=d`Dhw!^sT)cFn#$kIXBeqti$&t0g9opsCZVNzhcJmnIVlhDwmK<NL3rj%_m-s;U
z1RxH^y<UvFo{o92%n^+%K{<^NK~SyBiOSN-VVZ+V5i>7KyMwX7(v&5P4J27yzkx`M
z=O;u-q%$Y&tg9(Fa%?D25?VZ2LBV&=Rvpk7aa5}+Yod9|HQdnffjTfQKW2H|K^4h2
z&|_Y3k~`3_+Z0+di5l93Rfi;zzLt5NkO8Yjv;~X9LhG=q+)sK;n-NLjj6{^ds3tkN
zPQZ32vtkC3?dq9n9euWiL;FG28BW+my;|IIUZ@%C0!dT`P*6*>;g6}_Zlxga0gg_*
z>86#_OY&I0NJy(}7lZ462}Bj*5Vv~`jwdxOdl7x1iXG3UaYXK!7hb?hFQf&7NBCU!
zhF0cg4Uipyi1<lXp0AY`(<G6O$6%rb${u}tSQgr?JISP0JuLzaybeT=6DIp7NzG6L
zlQLZcf)*|-b~RjeuE{xm%!z%WNvTO_!A$%#pCir?jDcm1jyQD}MSN07Vnme{w0zVa
z5Y$l19a>yU?G$3X(w@;Wm2i*$MmTW@lL934>s1WK*?Iena**VR^|^q~6<t((EqHfJ
zw?=|xKt0-+XeqMGP}WpJR*dvnNE7r`i|(dMVy_}@W<en?m66y+aROAgf(U5mmQ7J!
z$Kq*Sz~i)Ryu1qtr^`8BP1Yu++Oicj&kSy!r==l!T|E`Il;r0?%AmPiW#fxoFgLF6
ziNcmkd92Y3qkNP9=SPL&(py~H(IDTx&}N;S9%^~y83}jPvogk>-gM-($aAo|Rke%p
zLQ~(OI$*e2*aCWoN)c`}S&=b7z4=CI4nQTq!K25+My=SiJc|`rFB09YoQ5KpmBpg8
z+QgTP8iIgTDLC>HWfYxTtF&d6Q^RG*T8o+a;dGTd(9@JGL^;5iWWnX`Xb^15C04DL
z6;z0(sA3!1$eR{<G-C7t`YRvTc;;3<zwne+K@jzmTOcU<M)gRy^p%MRXN7ils77lv
zzdKI?)=(?8(qCSsR4J(y+Nr=o=6pw+4mK-5Y(1qZ@X2pFpV=j4Nj<pP)6#MHDrIPL
zZTSuY8s;47>Ws=nO&!)yc9<+t4s1|TmhY76__-D`V*XRgFPE60&QquIK^FW)o_lHo
zpF?+f+Vlc#ndZ<*aiBnrS866NMmcOsxR2Lq3dLnEJ>LVe_EqHbk(?Kn$lq(^J}0fU
zDv&QCqe|CjHK`0`l<M_rJM0G1+K{(hUNo;>@wrchfnRadtC4OcSWa6gF$|<->!;@j
z*Za}(4&5djS}Xljle!se7dU&vhuJjx^+irXSke)xL*$HBNCmBejoS5BgJxejZu2QW
zpD*8(U-m=J?OJlxwS#}Nz9PHNja9>szG~e3(E~@UyzCdJzOnx26@$M!Z0_(rqxO1#
z@%dxkSUYCStyM>lUU)#T*YbDIe`)y(lgF&=F>yjzx!*~5z1R5FmG4e&%Jk^_xZSV%
zfLpgUekFXreX{M{bANkd@80{&8rkOy@1?HD9aGVx^vZ#W{?msxe%i8n=+AGg=>5y}
zJt`j@(lFx4nZrl?=A{FBy!2Aqi)Icz>fTZ9sb%Z4179Bf(?4t;{oz@n@2!_}xalt*
z*th?G-v8#cM}IJG&M_bSY2|r;9=r0~SMPl7oDb)|{oIEiywT^pleoVA$uF*&`N@e_
z{pYGn&VO^|jPv(edBG7AR=#@KH;aEc^ol#KIyAlN<172Ey86now_Q16df}=OXXNKz
zcWF5Hx~p%Qd(4T8=N@&&&#pf3jGuj+zWmvXj?~XzR6BjmDSeI^eaeq7+&<&LBe*Vk
z@1T+Uym!pV%ikY3bl3;y5B=KBbB9*e&KTOZVf1@7rCA@=h`tX@P-_4Gy#Jz+|M~H4
zvj)CDU{0Tp^O;LuO{Hi2Irqd<A0D`2+<QOzL*3k(t=`-x-aql`6F)ie>R0cYasJX3
zJJ0{}{0lBSCA{#mr;1m7A$`}x<Bt5n8CO;>Jn^c2w@nz)<JLn*3_;iPxK6%h?&#CM
zHD}Zb|Mt;=Lw|PSf%`mrQJ>)X2}hbwPx*0=PfzJ{#``k{9y)8rz{}88z4*KS$D?b%
z4{jXVdc-A{+k59;e!N+dEpeV&R=#~dg)#T&xj(u6;y=H8=^N`Ce*MOxhU|)~m(AaN
z(6U3O?eog^QK!Fh#khT@K5@-|PCe=UvwyL3<&%#MxS{Ic{(knNrJ3v*&ra)m+P?W&
z120}MW8f8sT^Lm_JUU9|F1xBZI_Am?Z#`<@S8e;i)4q3f_1y0r9UlJEqx$w(*50>n
z@r)jm79Trsz>kkTV#+b+G^Ptzk8Ig=VY25RCZx}}eL{sVdKDf}YWWm>-I4p~#wXTK
zwNKnPHA3%2EILHl$`_W^N3R?_YVo^Urp)+B^77}_Ef_p@{Us}=6qmi&W0|TMbK19C
zD!+L46F0U!{`3iLEjL^kC3_8vsynML;n#-_4GTvN?4NHMcu4-@)Ts+*q*{K`&^KCk
zS>H<U@+%K2^u01Tazvwf;M_*_y{d5hcL#+7em$YWES-?<+c9I{_{GOoh3P4}^}ZAJ
zeuc{66Ize&AFha|{+e5ExqKHd@9uT&@p-$i@r(PKj$-4~C!*TQsnw+eF9_Eic<qXu
zdb--%lvTl(rr4l%aO71!G<NLNao)f_#%t&kR{Mq9(^HR_JUI$Zo6Jk*(zLceJy#;w
zrp9t5)6I>K*Y7{>_<6ZA8*<*6r#{Zl{CERXYb!7C)Vx9TU#m`9``c6Nj`<Ij8pwPr
z<qb{c(Czo4+g0Z>(r>T(st!#Rz0hMT*oj`$ZM~|q2Mw++4Z1H=+jOh0<()*(cN{~~
zqA04&pdUwe_o?wJ`z#6zOZ;l@x8o-B<p}zH>zT1_HLcUyY6_O6a)y-jl}8OtPaM|2
z)0;HLdXrvyI-9!U9Me`|1OHUjsn*sH8JCR`C;4k_`lwUUje~J3@D|B8`90aIx8%sW
zFV>$~*Mr^{i5!JrGPF}S#y49&3q`jiM<0`w^!5xzw&}H-7O9O^#z&eAFWco!!-Irc
zRb8-&etr}5KSH||o{h>2+PGRdT}5Q%;k!nurl%FZ-agOw3No2SaxvHHZSorVQpHCO
zBZCTbBSW1$D@2}V1m|g1zS-~7%&=Og+6YHnt<F^jROa~bX)AOYPzyq%UzSZ6dGJmy
zkwd(Hs|mG)`9y-SRu&w7uY|vvJd^kqQ7_^@$R%Nsx2f#ox$s8BzegUemNi*7ipP49
zhcfcb{v9_6p_3mD&Xu4QMIGiH7F_hrGhBsH6(LXN70OzTG_jNNOUzXy&tQd=Z*_z1
z6j25EEMr~X)5;QS)nnGjH)LrUpE^8e4N50E2yLuetS^Zf$i@m0K{Chj8OuvnG2R)W
z$v69_G=nVBE-bX&AQ|id#xOH#5xq@zS!Xo=W-qF#t85I1HLJ{eHw}o=eFia=tBj)6
zoWr1LU|uCf3~HG<8>?7Gzd5J8dwC?`1)cm3$^8Z7r@cg7uvhr-c}IKOj(+~#w?BSL
zzUoRm^!x|aZ~TyN_CKDm>j%%g()*#=ALlk+`25zl7f+b;==Sq(y#2b5=50LanXNA`
z=9~TJ8hU(h#w}|fpSf+vTfdnw>i(xL9JBQ5#p{1H_c_ATNB#J@3oD*|dGX}uuYP>a
zPadAV|MurENNvAhaockr|8njRpP#<}Lt~Hep1ELY`*k1ua?TI8U)X!`j8V1E%~<p9
zb@yMi>w)dB_P%At(VkN6k$kg%R6o8qopE1vF$z@XTc$C5Md`uk8a23dhFV#9zD_fT
zG_^sg$Yb<^jw@8SIH%H!n`qYorL8Kc`gxIVo#&;p3FYad3dzbWZL*}i$$?e16HWih
z$!gvhCVNMyme#uZmcl+$Rrp1%D#lb}#_F0T8dP-~_4yUDY4e%GrIkH7tt!*n%xm+j
zzZBL*iNO`F?nK|~*>~Bu$56sPW(Bl!X(j^k#Mhy&wSc*lG3CFwK{thZm8Jkl`vFW@
zqN7?zqQL>>Yz1}6wGq@cc!$8`Y1k&IK)#V)G7_p)95)Uz?9rvK5xqFHvMnrfYx+@v
z_qsNW{LN8toI0z+Sj|gR)lbunsMR(qat;&xJP;r&R6UC}soNq|%&b$~d!Z^S^=?yM
zb*j#`THh$&wt2{-K)0q1_Y}Dr)oz(1=8HK#Jw_GVtaYyf@8GjEUStGE%CYZ(wU!cA
zn9i{W^HQ5SXM$|j25PDr+o2`hAXUke1RaLw4M%aMj15hi9F!i$vW4NE4=rVD_Ozct
ziBbn52>a;4PmcJiDa8x#Q!5Sc@fFEz0iRt`oJyiq$yCYDQwaNGw<Gdh<N-m2_{^6r
zGQh;HK|a#tX+t@297K90z(~NM^ot>H*sVgFplSu*gRzV{jfC-2IaUjpDWiaOr3{rR
z1r#fpE-Hi36D72ArZv_qV^p+QTFX;FiCf&;#9$bPRmL}ABW&>6a?=Ug?x0q9R<lhT
zd=q#?GbX6CLb~O)>4&NXI%FfsSf5H$+*Z1l8yJVZu)ibwzACzckci*zaJwV|((|(w
zhI7B<{P@Ah5I`YMHE9)=T$A!$Hd<Vslq!(j?ohF@v)jp>52V|O1?qHQd08#h9ApXx
zmKLLUgw&7}J2s-I)=(0aP5TxKXl<HjMYfa(Rlv8QuJiIO%3^v&KfR7y5YW!y=OqJ;
zJgZcLw8uy=qP$kL7SI*T3ZCc(80tZKcN(cCiB1Ty-sUBf3X$%>x&;(ZwVAP~T}5>w
zIj?yYA4kV(spXmkx||D)o>p#Q5;-~RIB}YNl_O8(S1vN1=N|T9V#w~8gj{J*jihP_
ze4~=;FI&VU6s}+mX-kn!mt4tUlf5LQ5QB+b3@(KscgvvdOB~wRqTeh&Ir=H5<_$;;
zttd%HpeV09R$a0YaIbO^8o0$&2*$}%-|#e%mXnr+uSE8Cn3O`^o*|2ZazlzAzt>1;
z0_0PzBC`&q$k{4WDGUM~8DDEeTX|vxM5dDGMGar1!_$m}sqVna+cwcV%r=-NdF6(U
z_z4b7lGLtd14zDGXKt2U<RfH`Ww-&65@WeEB1A7~bJnY~!~Mu==t^B6Hf*7-C?jo)
z^nR!47!a0BjUj(`r_+a7$Wa*33uxI{z~Vt%;tc0iD33Oz$*q#gRjo+N#agRV$yBwG
zF$YO_h;1eqJ92kI!hzhV{Ut^e=|n|MXUE_zZO7-AmtX=kZX13USu_(>B$k%Q-6;;G
zZNCX7x_r03%}-9RLq*%9vaTq)&4wv0I=P@Sh$9l9rj0Uglcs85zF|DyYZNZHxf>Db
zjrV*bH%!$O6vh|L^D1uIzUPX=n9^v8z$C0}X<=&PQZ{a<Qx{5rAj=}5Zv)I>=t)~P
zbf~QKy@1r4#g3q8DPFb4@yIC(rv7Ak2LWeOyiQeVN;D%FX$NTIt0>ET%p!wVq}3Se
zTiWmqT6k6K6s2LAhjA#is<(PcQ^SqEB-TweFk%DZ39&pGOtO_5w25j|VDGT(dm2aO
ztTyCLMYuk(5jEOGSLK@$+Zs)6mb9eLSbQLCYcx$r%PdO5gp8^tn^c1W>fKadzy?<n
z1l)J6D&1^V8x{?$*Ft)Tp)rm8>QuS|F+r!lS;T5(sB&t8MlU7S$tcRBaim7lDqx8B
zJYDfTN%#doZM}^WO)Yf>{E$z59>WH=(yqL)nb9-ix4e{}$%KW|($_1`=jR2ow3*Gr
zO`x8r6?r$)x=d&io5KrAJ~xjx)Wh|v)XHo<l1Y)VA#YqEo1(P#aDnFeFVjjbXszpQ
zF3@ca+#xpAvfS;9R{e+4pW6a^oq{i&#x0>OeY2P`Ap<1MnB%qlp+mh!zb_VJlxp%q
zw<@i9QJVMt%~jL9jce7qT0dYpOI<m5wdE`?qq!-Ii9QU277b`zhNI8qe)X%uYE6Zy
zii$DbO{rlFFj=hQeVKV@Wc|pm5&Ox{pDFFCPT7p?-BH~6vda_OTI)EV8Rf@@r$lJS
zk!&Gx@IuC(5^seiY7c}ASC9}dZk{1~7=`Y-m&sc09chymtjtbijr9p5+g*xgDOzb*
zk*-;&v|y0YOUmg$<GL3n#s&HPaw=NWXGt4j9h;L1igG{sL&`71T!t2#z$Gl8Mi6Cm
zi<G!Q=oqij6QT~4=<PSSAxc<js4@pYHWlW80OR`<r4IQDNRqxs!z3J@v!4vU<a30E
z1_*nr@=-GmSTuEJ5zj!giXm2+BLq)J%-Xu`p=bya&u{^gA`=6Wrk9GWggl{ENe0L=
z&J&56f8VIes6zqubU6;V0YtKdf>VXhDH^bSbFvh}S;039GPTZFjZlQfPceIbHTj?}
zVV@h`f|x))5Ky`VZdDzZ=*rmMlTkyo&X`PEqIjw+$dZ8r&&L~mKpY5S60UC=RHX~K
z_ULl*#B@es{vt8j)3}Tkl1RR_zaj5RLMV*o5EV8Pw6sBwgp|lBOstWA8QT%as71i1
z#2zh@&K}uB8+u$ICr(33Tou@YxESAXPM7R&Di?y}CN^qg!f4l|Fbo|UjaQlq2?!h2
zf=k0AKz`zqIr?!oIwo+(sWiTpJd?}@d~KAl#ULec)nrK{x1Q(dGU1^Wz~>kU$UdCo
z%Hxe=@q8n`-JONY)Hkja;D*?8a-#(opjdGZq_mFG?MU)KY1~NCy4FMh0s|(@fuaRV
zgsVsp{sDK!N_9s$ZBZy((%iCKfsMl%aKlB3{1gJ|iHsC^1LGSNfHCO-d?!RV!6#6M
z1o#Eq2o-T>1lomhq^^vMmu{qi5Vv-@0tqk!l6axYZ@f8R4kq$^vE{Bbn8CW9%A$bn
zizq*CqA_zuSy)L<PP@eh$b=3UA4d~a?!{a!5-ZfWHIP(sZq|VoIl?Tm1gzXeh^4DS
zou)F?NR*gP!s3%Ew!}KE<Y)RE=qN?=?-o_oMb(NTF)%{uGAccAH;TquwUX3<fn74P
zj#-4q8JMy*F&7Fp#+V0#Mg*z}V^;Z~E=`+Kb9vqc;BopCVi~dP_B+U+Xo+?&dT=eA
zqAw(E<2#LsNI>;l9Kh$+jkq1GbwNo1zk9yXEPqwddhnH8#!9~ol)G=^x(6qwAY_&G
zjpPp<;IuVdUpwV+OdqKOAt~R`zB;s<_*q58aKS-z%uQ=)g(Oh|=)*r*(|Te{U>M)i
zN-bwNz=IWjml3%51=*6T<<=mM$5j_cs#ucvGCz%h-av5(Xq)Yp!1>wmW*Xzn;Ob&+
zb}6`NQMC*a-8jG~BHZX{;(EK;>0Ew35snzF^Kgwr%BviN%it6ZOgTios8Sh636D+P
zn4t`s4cwrFHBYk?$k461Pj*m5T5f!=x?xJXTy30*U05RF&x`+A@Q`FkUoN53CoY{9
z#yD)d5Gb0!lrozkESE}g#Wea;q<!~WLRHqesHe*~QG_s+L7Ps9nwS_2(;OBagweVg
zkC3}$TIi4&P4Km6Tu6DHg#9`Lmk0*1nRSSBXq?(1*_h_^5DMJVrUgZ?!7GE@iQTpk
zG#v|WLlZ4wRMMU#ic^cv@Z~(3k7(zz6hwy0?luy~S=V=py74k`+_S+&gzQ#!>NsCi
zG|KI3{AS)!G;XYn3&xp}lDR`5c?NN<bz&Z|8d^b=$L~0ig_Sg(3%ZU$ORgx|0k;D>
z+%7aw9WcxN7f?|&A>VdI35`F%h|>k4WNba9D!nEl%Wzg9bT3bTqZ$pU<)ZebV-Xp0
z03y(pZ<Q8>Z1+7dD3b2osK6*nBR4KVrP{EYOE=YpwXz5xY1ruo6pX99v?5&t%#w}7
z0(HSjoA89v%B4}o^NkTsK=$eYPO$K##NHkh&1Id-LkTzm=sISN+2d4xQJw~X&0O-p
zD-uMymI4|sz;cz869@KrAZwX1Sj<CHawSv+9;hI*ni$B^Mpyp{CK+{uX%rq&iaDU@
zMCwZ62%Huurk$RjNz|2E8k6hfGA`P<B+4}$8O1eOi5MenahmEqvo~VLv)0E2wZ0c8
zcheTQOI*~yvw}rKE2{Yr11|6)t_N<duQ>{t7{g;&xrI2MJ-Q4@f?|M3D9Zp3s5e^<
zFOWp!!H?be$nrDRH%yTrI<mndKR-(gZ7S3FMu9K2P*aQCv~VaF7n?;?rQn9PV4d<C
zMTLm=f=>bgF$`Cm;E;M3#FaQ(sfET(>O8EdU5_d%GK9L$L@VQT^PALTufm%1OG1g$
z<HwLFx7V(4b9bldD3<)KOBR$lC{JgMO5Rpb7Zp%ev<0_yf{7|}zcQ{>m9<nFHHdN5
zCw^S<QXrBUVb+o#>=I*LY7i$2w-hTMCu<Zs2}nVbc+92`lY~qmjEK;JH{eib1Q@LY
z?%p_4s4Qy7eNC*dP^fe=mwX*)kps0WiCDJ_id{&|QziRwzW*<h)(~Sg-vU`J%SgN<
zrGMz4j8qH_3Wo6DfXQ=IXFQ)$6~Y>ovNU3{G5M&d&=Tc6eHJM#3bpWXLSw{t4ahdA
z>(vU4T2eQ@al}%Ak9iu5pQckb#fn^sU;3ss*6PS4RN7N}D-&RriXvS~;HR#iSTu>P
zev@)jCdHP5M#GkvS_ER3#?V`Wf0|KVQG@vD{`JYoYpkn9|Ew{L28Su>5T+O%Mp4$6
z?;W+eJZ<VVt=n*)gc$W8?*EW~1ej1aie^d{G8-a)oTky!vq$xf6jsAyeLrhG=EI@U
zV#`Mtvm_uD*M{UAx$$aJt4g#XLC$Z-Sp5F1CEr^+bWZ9huxe9Xz?&EtNH?z&Lwc;x
z)o49gNpFMs7Ac+2X|VLvz{9hhtTeUJMoB~2yr8+mZ{h3RJWqi(7wI0RLpRLh(6@B9
zKFk%2G9C1RHk&?7dHp?`?WBVrG*5XoJQzpSQA=gPPua@GrjXrtwY>B9J2R@GmYbjl
zs_=Wi-Uc$gkDulZ>Z7P%)_C4v<zJchv(j**!8#i6w|KQ0Z4LVIE+vX=reUzAm$<M=
zN)X7e+N@|y>N+FuX89zibcnnt&uUExvvAPfEI)GJnWcQmh1f&4w9iyZ^SMJo;!9QL
znxD)WKJ&`iE6i_iQL-l|`skRR$K5eI{OA|I$xZ$FjW+q^qxYLMYDmv1%hs=LTYr5n
z>UqEc_4|+7Z_^9+%-j6J_1_4`9I#*gc?aw_v;Clf?JvB3qdoC}#E>xu4A^zqX%mOG
z_dLFEeec8%PTDsyYSv{F@0;A-yy5#x6CKdzTy*i&tGAun{@6=3!O$K(5+mn)t?jE{
zd%A7V<tGJ~ukR5w9(Hoe$k{E^o<OJV>&K{(mk&65)UcCVW`8(q#g#vqdujVmW~~r?
zul(?VoBs6YHShfC&!g`=?!#HTw!V4Pzg+v>ci!Q;srADL-n??l_U~-?bl*RhK0V+Y
z#Jw}>iv1_doH2UF%u`19ymHH@ZykN%=;n{Em~g>ISDZ3_)RFriKJ(ghuY9z9*33t*
z`0CiB4;npV)hAz`z3a{MFMjjQgC@Lm?Rh8cSW`27)T~jLA2Mt7B|qA}@45S5*}G-t
zJ9~Zk@^|){_}cesE`4>LQlGqc-r*m;cb@8XL5~Y3UG-^l=pD08Xm9(}+4stsM~8p9
zVD5~EUV7)?v)|kP?_1w|AQ<`GcUE2d=sP#H-+$DbQ{VbD*zoC^w>RxtQ~C76_x^d*
z75g+_aOubsW{&zo<<u=7e0={wGsf?_;*<+^U2$$RWjW}h?dP5U-C45^|F>gj1@~V#
z_ky>7xw!9+Hx4>!`<pYSeZ2kL6L&r5A938=(LMIPZcghVZ~pS?!)8|2&wQu%iKpGu
zGkp4ynj;(8r@8&T1CHGC;{%cdX7-$Q+@D9i`j@8`u2AasOJ#4-%OCD_>BU#Av7@FQ
z{@CmrMy($H^5T~oUs>{v_E$RJ+_d?d`NsPOeYNn=J-O2M!`^9mck#To6OTQl?X668
z!&?nA8eUEJ{N&UFzS4T_0Zk3P_n*<wV|35-pi53#bm7^RRYQ9pwyJgC3E@dY=H^ez
zj(xU&_TrZsue+%6@k1^ges9089rwbQ=Oo5ma!LK&{(;B!sA`=a^qAYc>X1u#PCh~O
z8m{>SZlRwzt6|LvBVHV-My!A6^uIjbU$sxIy7=A6d*$Dq{LQ!fzjBW)9edZ5X_qaw
z$@3RaX@6z!1r2u}Hf7ik=o)`KXo`LK?tIX@-;{<PN2<0HMyK1h9Hbhq7=Pia+P%F`
zqCSVTAKTwN(|^ofUm1Eyc;D3P2CG4*jPJGCJMh~l4XMwMyX1s?&6sKDR#hE1@vcMK
z^=)4r8Qwdl;pqYoGk5vXao^0YN%T17$v<?i-tdRYVV1islzm0%u=Yyzcx_vKuD(?7
z6-tLCbBW{5to=j14LF|nhUD_ilb=klz0B`(;CBkwr@vQNuI_kiQPaScm%lKzIA!?-
zjVp)NzPxDYfaRAr{r=7=>W{bSx^WZzx-mb9E(&t#Lws-8<^IO{_PSBE$z1N>YjfUU
z(|5xEVekFp?5e7R?{&_cncNwM<jgR{0b|(r<|Yi0hD%ICKn&~N+~5RJ2Si0m@g~F&
z5g}596fx{O3}KQ|9Al(bEZkro-l$bmq-fFNC7_~Kn+JWYqQ!_vkygqBRuK{3@7m|w
z$$+-+=kvZ#|9jWW*?aA^*Is+=wSS&{_Br>iGY?-P>o)(TG%oCY`5Nhe`I>Y?vsut>
zpOCjan6&EX)@Qo?><X~S_dhZuJNFIwp?wcdlx6<ezC0uorww_D8IKOQA00UPn$pYS
z!%9c-tL0Les<tk=^gttC_tA#5?%7oFONZX3(Hpm`yy0UNaVI+2SLK{#Y4GhFHd=Z_
zvAij+4s33gjvq##oEG(^hqM2=d8w?sFiAEIMhh4@d;hGku6LW9(H9T#16f07*_o$j
z8Lt-fGU)qsC%0+)(x(41)8vg#(!2Qz#gTF3PeuFrjMdLqr0e#W53Mt%|H4NTk3zq6
zkft0*vY}L!hvQn|%qiErPonXyD<at^Di04zQZGez`x_}^uA{o{V4HanY43NnXmL82
zK2Z?4nDKipu?*GnP3{z5C!)p4h92EYhv!s87+uBmc$1xZ`q)!o{45RWwxSEA@HTgw
zOygO~b(R<1f=t3TQTdbeIEzODk2nSW3hvAJ>zFr~Ti7HqT%vW1>Nc2X?gX@;cL=Y8
z3{Sca`Nu#xlM8urzI5GpVj4uq(S$F+et05w=IIl61+)!kjBI7~bUmx280!68qj27U
z9~YuC8&V;@nv8Sb+lE%-+JJr&Uj427$o$#j;)YLUJM?u@=yo2T^zd6b1L7z{Ty)YU
zO1Xxh`-p5gl@T~tr<e}0#Fb4l8pp$JQNI9M06X*aJ<S6%yvBWTG9xILwS^m>q2$!0
zzr0NReU)8NtW7wsOPpL=XNBBdMXyb1b%BHGlGnsXl&bSmA9ab-Lz_!``l6*#^agEC
zjm6b)1KV$Bo^JSztx4q78-DX2a~}BjJELbVyXDENe(}TSm;dS~*FEshclQ3^UkE?-
z*5_CLX8Ei;FM6u^_`lrp%vCr3aLe+qp0euM_kQ-;$2NTbnf07`y8Y`Xbbaxix7_om
zSN!_9N5A!rl}~-|l;TYn+;s0HSO4(24Nq@bdFMN>j=uNkO=~YX;rm;b^E)MXz4erV
z->$!@amnr9zxwhozIXoTuU;AbwtUm3=brlhmaBh#$(+w$@^tT4xBQUsYqqTX^>62#
zdB;vKGBssqh|0HM(8f?(hvrXh+<M)I<l7VNsr@@f$L_h4b<`iG$!(EJd+>mhSNihA
zC)2@wUdO9aUMEi6u}jC@my-kWs@^?ItB2lKsebl8cg;0>23IYL$JY+M&aIk%U*D=v
zw1(nppHzE~b!QxTQDx0+IdbIq{@J^Z7<st#mSdO3e<CLpyOP`1M}<v0`bJj7{Dem7
zkJR6;I<j|o<B9T8r49m^zB{hzgfc%=tldF7XN2ICsk{JmGV#hnP!87rq|rhwj*$;W
zO;dRo7li<E5r27q=)?z~Rhyeh=rl2s6nGJ5oS$#BvpN4%#lD4o-UQjRzwLVy&nAk<
zTNZDZu{AoeTbg~XQhiLW9e0T|Cpci!7?klH2@lz)q()<J%INWh+TeW=UsB@x3lj?p
zkrqm_GhS8|Kkg=63E5h>KbCfLH(e3wtu=129&-?+60hDid8;d?6k<Gj1+N=uX&Kv?
zzTXLkNhavZV}-R{AD5IbzU=mX@C<f1If@}8)wrPFZ4U4rMp~1l-mO!fBDCzF3B@22
z3YPFpeea^P*a%f_q)T?cImJ=?lprTkqf4>RL|WqAgTd~`cG9#}i&Ew}sHkF*YwGL*
zc&$oN*4C+{wZ2fMKY!KicJG_9dV%lcluqL|eTrXiJd_mNkx`J{?W%@NiPW~UwyMKT
zq88E4OE;;QqcDkRRP-DdQ<W7ynd{{ok3MI{i7&G5PYGB(uo|{U6`}`7qxJ3V4>sy5
zbJNIf4=|GFQ9mptNwT(bz@C8c@RLo^l8sr#{U#@dg|SL{OX69D@XR9eC8nlP9>u3g
z4{>Q=*>i}r9fnKG6%rub*6=2nC(c%{Cg%Kb?`EZiVWY9NutB0;BD1^>^kk<zIQNO%
z-Z+UTedHyHCkhHhq)6k8)qaMlVa918ocpkF=IQ?LnNStvj+ZEr5T9&{@o7>+-jB&p
z)GrgsI1*%iVZfVY;VVh~NzBb+jo<HX@<K{)+}9v6C6AI<*v*#oP`)Ygi!^aAeY>(f
zHpn|56O`2<X-x$aB~9*k<@(AP1#?tov-)Z;?1(d*V}L>pXQvEyE3u2wNh!2H{t9ua
zwI|18xwe<Xri8J1(JE;$n}~1OHxJ^mhysYz1?p66UxSbxaa5uV5;^<foc>r_>XMQx
zd#frQ7aowFZkwWxAMm2^L6vd08ir&n4@Q+#i#3%|JCAe0y_B^;%a2NWr8V@NDfrS=
zatX%lWilT_oKh`rdo9Gd3f?#r^ria|XKz_Y)DCZBPTg0gd*$1-u@h0Gh!dT{i_)N#
zHYTLvIFV9y5^uBvIB8F8M&i~~Jek}FGs##vMzjG#rDp=C#jXcE)0515+h?T}%Gq(M
z*05-6K5;Z+@?_ruFF=o{eccwd$`+br-t`I+rFI|%C^(IkB2<tNAm&_QUHZKvI`Pp)
z?Jq<QzVI0pul#OW+=V;tD1dm&nEZ%GJ~*5V7IeR+HyaP^3k8m$NK~RrsBb%^2q-u~
zYGXA>ozidC@5w?YPiT4)(pm8rn`C;5heUBmH``c<SM|tI;*oA#cJk7*fQp@~QNOfV
zZ>-!!J00{mW?^Q1@51AC4D6*O{f&sUCCQlO%hoGtVq*1RN;)n<zG5)z-EM-Q(~6N(
zohl65M(be~n&gU{^r36yA{bJWP>N%s>cR$y31RQ2iyQ*zeFVXv(iX|XW#r(>kSfir
zOn{p8;`cuwp|0Q~Y&QP&AQame0(hM)a_YgiGiVR4lkx<s{-C#{3mlo~IPz6edv9dw
z)SVJ5Vu)b9C+sOuT#0-#>{NN$2W{AS63IkgO$$-WR0Iz9<0bRsN+aIn`m~t%q|7p}
zA#OBI68V;J7-4}pHx;K%zM3Cf0mu5&wS{=mRx2xy_{V7mwegq`=apQ_+L>m-)ZxUz
zz$D<?o^}zMiYy+A($ho4_#YJbeMfArUgAWO;<|w%ZTOx@lVq|`I7DKsd8&-jPNhlL
zA;{@uk8pOgRnZ^ITjQ!xUP?eSksf{j$LV3BZp7KCOQonu<Q?S!E*%%Sb@cr*RzZWx
z8xhE6@XO*_Ij$r`*)LG>1LbGB^}0K5&61eIjw7|M-GwAMvd25|l1yqcnTWU+7UA5R
z^&}sOazo>WMA^PlmdEJos=m8FIl`y)o<v4{v%x*ti0P<OSR``?WL@IM7<y1@th+UQ
ztC_C1QRz98;<e+ct%=Gtn0lyN{HkW<?48mSUaO<d7{`x|hupv@OA*pU@lZ3Oj}|IX
zL`RTOzDtJ1SU|L+_zz`#?U|%05BkCsQ>sdQZ#2=ruN|j{DkoF^j>(8&aksP>GE|CA
zqQP)BXZ3fmTugV{!xkfr9>vMTk7li#pg}^n(3I{Bu-T>NYXozQ3Iq{3Dd@}&X{t~V
zq{fBoQ3`?q{QM@Kg*=f;Qg7tCB;S?TFw3)!>q7lw2Wx=d{zoW25j36P8@nSsX~~F~
zzyp}})W#4SgoMe3NwLO0EkalXMo!doy0F^>sY%GdTNvQI92^aK1_F*}QjlUL57Gjx
z%m(AZWj@qkgOO?o=T5SH9b@PmLhPJc0@NHyki^8of=*%|;WBJxIv{>B7zbK`a!tUQ
zfhJa00g~9-zX3uz;9QP7S3r63A%fa9;kl+piW6s^nnNC*+-UyNOh%2#!&-~5n>hQA
zrFS5v2OEYWNr{LWmyL&J%W9$MrDB>=CrSiV%h@>`iP|{aMyk=&kBA(CB*#spHI3Lx
zxWdv}3X=e^Bu=xr-t6|N`9?EvHmowzM4)vem{u{%01+kR%yl3r--ajsHj_S4g@!mQ
z9m01r4#Q$6O6iWqnpldsY-uA;m~>`h*qPabHiEK&H5{j6H6$TKvfiMtI}<&|m9#**
zO+79VF7iH(Q{KhNYyzoKLcWVb`b;=`-yuUe-E!Bk;50D-;<P<s`T&#=nGUU7mVcBu
z+2)m5kJyAyd`t<+0VWaaCey$<aT1Z(Gj5s@0KUt2D`)W7$tY)uGGbaJvxFY$EKG|)
zdY4(kAfoOQ#002Q^(Y(ByDU6~d<sd&%9QZ2$zc`gAOMULX_wgrYSxnzhJ&)-WRVaZ
zEZ#7H`wqaT-piy4f;7}g>T2Qx=7P(T6Hte)1J>sT%n}-ibnG$A;n4s>Y_tPGe?!kG
zC^+WiXFO{dLPC)?vL1#6gwpCk6XvDowUH1tO4w!^0LS-Ra<k=6RvC#%UP3br@LXZ}
zXo@iK7>#yqL}j+IpzKdm%{nxsU^DcBoi<)4TsESLjG2#u7PgO)<;^6B3=FoCu}ol$
zgT|ipkx>sd8wH@stp3ah20_=1H<p$q=0Aj|S(u*rb0Q6E@{ahB*pu4Q+k>KtOog5m
zNUU#6O8^zg3GRj=NOk-L#L$q-IBv;ejU4-cU`x`x`%VH>Dy|a__Tq~-N1!D>s2a0k
zkPsuip2KIvA+D5VMNx>-iA)WPX*rI^Bc%%28zB>jnjGgLOB%BEn~-N$Bg86^&?$4s
zW)dzRa*Q>2#2PzaKp=N#p&-*nG*Wsmi5<RlnZf%}5Nd$&+|ObhA)jBdg2XO_Gg2cf
zSZ+C+WTK#BD8;y~BvH`$xE>5RywyQ4d5I5FllUf12|$ZAiWMn*v_J`GoyTk~0@=!G
z!=RxGhNd3W!295lCIV4%!??zPVul&b!u0>xLRmQUy`GTP8-s`5RR|uK&B~o}iFc%S
zj&*?dUZ?wA5|Ll5O!5Y2!0zD#yf~3vWZBM11OvE{92pPeG6Ay*QVdhl0akVcsNQ@v
z$5>PxZnM)kz^%QsgC88Wzb$*0ry)J4ft`&9%$CpZGK?rFX~@WN9{|BP9G7<E0IYc_
z00@y|M##X~>=s6hOgrM!o*><_L4uE}ZCF{+;yNYF>oS2i8$G8;Z~2Lu6YR}Ek_n4a
zSDu1Mb0I$Q0t5#!h-Y(#FeaR?7z9z-4z@6-OcpJyA?PgEkP$%_{tJY`4#IT2jUj-K
zT&|Jj$JlPNyy1XX7DRbT`37OkBj7b5f@Z~G{lJ1#sMKkP-H47HJSe0DBdJN%LYV?h
zHQUn6lPrfQ&^=>QAc!^f#7txz-dP=(s3e^A4niSjV<=2*qTnKB7<NNw3<>B&-UiHy
z+#msti@X4<LgzeK*H#=oXjH4N3=n`4MN5z0NlALOP$8k}J%vLdIAaYwdAqhuVoS<r
zv`vp737X5Z2enl-;9NM<w7aXrl8fgS%UOH~Is_>wI+IJ1=L8`rl?{FtAS-w*n#<u?
z3iHhIT!59XWJtxUj#doQ#AkGHyEV%MwK7RY3bo;oNm&i*K}v>)lqSZHT8&!OW$E2`
z#-N!u?V1go6kSIlB77&(3g9wzb5hia!ml9P(gJ368cV>TS)Rcb<|V{ALnxV>MzgbH
zf3pLs^-U|u*g~R#C}_aPK2tiFfpu7g<#;QnN4n3tRU~I+i??8D6lzdZQX442ri}qX
z7&0AL2A*P>j&31xVhsa85R7=!!)I*f8tS-s?<6Nrd6Vs|3pjPSUc8!}Ot-c$`&sYx
z=|<}-For1SvoS9*K2FXOW6^*!r$LIyS!6nCVM~~U&&L8O27*;=uveClKpfiZvDRx0
zNFU)f5rMo$(8}nn@438%O(Vxuwx9vcBm>tIe2vXBb*NIn+rNS&<5W^Y(7-;2Z#|KY
z9{6zrx7h*k@B(ViL{oSj$OeS0DdL4B=4S7IL#a$;k(xClA2_@T1sfs-@A$xGpzwI}
zxx8h{o-t!nmObx7I+GvL2U3)k*E{lu9@|qbSO5mC;V@wP5X32t%cybLx<S(G@hj+V
zvHf;VXUWlql53ay7*yRk7F|m)5ylIE(<uCrsSm+rY*VMBw8#R_9Ev=CO(s(JAuqlu
zRZj+IRcXMEno7JpNuJ5(%y>%j9w)IPb&P40Js7`n%Cxsfh}@BZUN+%)^*&0=ldKJV
z5?<6zVx_CJBBCc(po6;RJROk;&PZ*Tc^E_9Wu?XlY$A+~X*$*tGIky}R@*#eAZ5nu
zv-e81_QABZh!Z$&0-llBotpN=M>y6*BW?IeQK-?Jiq6Ge3RBp3n0qXjR@jQY)#BIL
zV_>vlt0u;GmnqMmq1Vlp3qFln(Fpeux-3a6s@<#$QrYDqQArPQbZuG7*0jS!ZI#M7
z)(EU7ZnS}rCeR*g^bIwnS=c{R_EAI9GwY><RcWDhqYV%vUMnS*^WNQGN=yZ$vO$wf
zW+&Y%iJYOMQ!u7}qMoF~8-2A>8cGXOvUja`wB(yweMz$^eJ#If_uytxzI`$Qv+PBQ
z$dx(bWw+J5h~h_m%xGI_+$v2>?`bdtjkd6ngZQL>yW@)?qo?y=;^TxR+3q=fJi<7^
zo3362jb)Fuv%@$#(ZZ<Sh%6(L!jZx|rm~Hh(V>vgc#DL+<F0fb&fp@~bm7d+4@#kr
zxWZ(s-oE#`Ih*HRb<)bqH*FbPb@X-ZRd4PYo4@SJ6)Ueg=c!dcnf36Op01^DUcPeb
z>SY%{`lHo-dw=|sFHgLA{<3*<SFU{OC;$828~6Wo-MmBQ%paPw^6n>p^zN_SwfDe+
zon0@Ve|^_c^Y5N|a^v#Pt#DIEA2Mg+klxuVKeu=3yH9*(*_W>Q!0esZ9Wwj*70)ic
z`@Nf2eC5Y~G5eA0uA95`iWMilYU$>e-S*=LXN_NT!>rGpwB#5&)AZ0sMgGS%<6ZL>
zt$5WlUpeWdfBVWww_SF^@^5ZhxO~gE|M-e4_rLb?ryjgy-di8M<m88*`pO+!9=`Xo
zUp)1X?^=B6KVJ6e-VM+HeCLL{?|b6>`Cobbf}5|t`8A(9@8&<c?aH5D{ho)Oy!xnL
zELrgQ{FMtHU%I^O)9dd%?2?ObpL5c2cYb>5aVr<BSjn~IZ$Ghk{@=d*q)V?p?#Yv$
zJ?`m?pF8EemA^UVyvu)i{>@8%dH(#%Z~Bw*uABeluD7my<>F)Re&ymzOy5&}BJzcW
zcb)S03-5Z*-+bkyqo4cI%3WKIUjC<z3uYa+|F!GRoO=D`AA0tZlgA#v<cM!Q^_5kF
zPhEHCcQ1Y7vXNi>`=*ait-tHO%F)l?@x%o;eC*i^jy?a#*L=Ft_nP;;>5+?%I_Jqt
z-Z6}>#ZN8RxA^X^<JR5X^~J`WpFXnpwmByqv+|WI;+3B`QQq~+lPdqQc<JU}ANSPk
zXODY!^K)BHpLg{Yue<7(7tEjg^oE<yy5(KZ-g5UFzV_<7PrUx<yHC8KYG;Q&_y)eA
zy70qC{N2$X-aPvHO<RXf+Y}}1>fd18xcb|(KK0vn{fWySKlSI|dv^7;=RN$|`tz60
zJL{}VuRr~<OaJPki}%iwD|XIWRz0~;s&77h!<G+UuzCJN=g%9iKYhpP>5uQYcx25d
zSB|WCTV>_>PbGI>uyxUn1)sZo$AZ0!_ICaI>8(}oyZBvQk6(GmD;{2&E*RE{kFHpB
z=h5%K@Xlgo@kd-^^KXimp7htRY`ymjuetT)6>q;?zp!xdsQwL&Uo#{eV|s7;gvjId
z<e%<(_0SpVoJw=vX_Z-*-f+>!FMnTQ<J7Dr`}fzEy!7PPZn$vs=_R-BwKDZozg~IY
zf!h|#|8?6aul?OKRU7)u;`8q;t-N5|efWgo^lR%j&vjkztF>1BqwZO=(0yUeCl~Kr
zFuY;sf)#FjK}B~gSW)?cJL#P7xp>99OAl|lqwDb%U-;4Zc_*JdF3T6DjpYmY3<`bg
zOW1SI5!=uG+)pP@9&fBaw_F=OciF0WJgt)}cMd&#^4w(Xk-4+Rj^DcetV+4>vf-or
z&=20%9y@1e{o&1Rj^r$8pSAsHIqTwOePeT1_Yc40<9_MZzVsD~+H%F^A9?xckrQ(k
z-JHyMQ_t!{hn9T2&n;OIU--=x@$IJ$kKDhc>DJvXgQHuyZrfgHtZVCv(&)g~@2?Hi
zp5v&;UHb>wtQnYn)Z+s;Z)jInTw1A}JLYPp8uJCZ_por98!_pvFP|MZ%9TUfV}+OU
zm}4jzUon*2x@UpN$O28~xxPxj>l>QrlS`xRa%rjzf-04kpM7SU%wAqtedwsG_SYvW
z@s$YUmGa&~VQORz-&e9dZ}Fa|$gQ~QYw2kmq#3U?BlnSA42KsE^hcWp=8v`yq>Xli
zaV=WQl+Z4mwNK=@jSPRX>HUd}wbE$J+rTbS<3nsY-jRxye7K)Da3ImMK138tbbWww
zA$H>D6O55Vl6Xec#K~r47EWi}oFKl=xct`%-&A6G@{vB#vZRfNeM$e}`e@{OiPiQs
z_PFuJ7l^x$bbRi>w|Pc!fEjJ%*%Ocu8BcUFA2gXq$N>4AA*$i9nqwGe)Q;MO{stpi
z+=qy`1HZ-PxS1uKdalVZ_ef(3-A%V$kxkgFCv>tpAzmDM5>%4`Z@PydyaB!@6U^Bv
zMe<W9tVbL?0gT_-wfuPt+dh?n<6@81W>RtOZ|?vdi1tW~?6G@n3TaEF`$I0pm&oSV
zQ5MPfiKhJKOcTp-dH$wWPul*omudxp+_4>ygo^T0A5gX;gow5bQ<pw!$PVFg(*WtB
zVNM-3Ea#%Pxtwcgl*wx?Ps7ov6*ZE{E`9Z52y9|LAC2;BI_r@?4R+?~#lUT(>a~6b
zIpw_=hY()qsGm&jQ@w7e54Bi|u6Gksj^?rbF~pH^A1yL<WM{$Ac7{>Cn`}A3Fj0_+
zXq(>GD#~-e{O8}o63#pwccsWxpLr+Wae8FV2VTEC`re{1{_p4h>9tqi`P<8`+wuBe
z^#0(2FFtws2j05n?(Z*~b>k(!Xg+koZ-4d3x8A$*&aW<Cb@!G#uYG94ub%n&2d*M~
zMb|Bt+<niVF8|GQWxnI|i?44e-n8MSdw+JyZ=U<qEmzII^BpUr-~7wdYybU(pKkf|
z=Qqr``;xl{ezW1G#y39muUCKSS3jTgnM+nizgl$DrYD~M)s~$<7Ww=;@9O>f(O-P>
zs?WUV`F-aPed&RC{Tu1^tL+R?(v<aEqh*PgWqkfKt=>3G58ZicW3BYAUt5Vv_4)S>
zHMXuQCqt($X@8`CZc((NlQrqzTUfSxnG78mlJ$*wU31s+((xmek!6n@8=u~|Hh#ru
zySVJWmYmzTzsr^TU*5QQcTsybMW?SnIqoZ6-?P_U8%@g21+ILIq>IXnOU|D!jqOYO
zRy}YAk6nu^TwHWxj}?d3VcTgieP@8R;hDh7)g27i;)A%i1$ji1rMyNhccLH|SS3$G
zCYA^FVcDCJxsS@kh2-L)rW&ID{+{6F4uazK+S2Ov61mvU?nr?{3Q2maidH8kV<`{!
zveD&O=)VCvRR5Q>ZC|t%SR6}LefJ(YJ&h9|SJ124YD(o++w7?(sjoXZHc}biD6NFH
zC<RfD#4EX6Q!%yU$?_iYp3jbO^E###w*72G;|UlAZSU{CanzOjYOWQ<_ei5EY);z!
zksEdF&+~==M~FNd>^An?<A=46z4A%9wd*uG+vGk@H^}BwUHjT0GU5ZYdQG1URGiG~
zW2|dd<0DX|GU-?&Qw$Mbxs*I9sPHgoPc1637B6$YO<BA~aihRlBRx!9-|BHj!ZaFM
z>b*LO$sR{ID>mFkYI>%*;@9Kw=qrlG>#U?*Rz+slmhhyOmAUlT8xD>{NmuyLNCH`0
z+V-krv7(2My_`lfa0x^3_!wKVU?z3QJNzWx4O3(!J=|lB^en@<QRNLHhAURn@b`#o
zh(D}J#1M+gwN!v~RgOdf>P4fPwCpgImzFalxT>WjLZ@T|nbeToyK&y3z}NR`gxvK<
z_^J)_H3`|R@p7XnmAD8t<}mwyg^LrJ@E-d%s<vf8$<S36t4OspMPOvak*A&5&{I$a
zh*zU{6{RA+l9EttbXaZeF-;2Sq$a(#Q^wUkC(X~CDDPrBoB9MnOl#mGE#X;u89|b|
zey>FJ;UIk5MC3&H&hH{zZN;N{U;;Y1#LyKHRabEFWK>`ZH8~WTiG)~BYcy7w5Iv*i
z`#s7*j3^gTXu^viR+skJ#|Ylu{-GFah{7z&sUt^ad7g61j^3ffnUX3;^2rM32<%A_
z3b6_XVp{2@R7!f91ws%%+wtRD$~~i$U=~@+nVblFG<qZDE(z_u3}{;LX4Rx&qM5Dj
ztjLlppp2W1FrmaAQ`@6<TvV45!VP#Bk>WY7cn#<dHHijJX<H0Xb&HqCQ8ZCcwTrxc
zLfTM^l+fB#NG%Qy3XB%wx*_dg7Ii*Y2w5KOEhle$#^qfbr6Nb_xSUvFBbns1ogCZi
zG{riiu0S#+p^kdeghz6uOrX^*!nDU_qvS;D9nmr{Ml@Rn2glWdj2NGzFGPqmjbp`X
z4jU_cg`QA;@|DC{bS<(H@w~D?Hwc*!B6mmfVlr5v1sg$wjrVa+4-f^!PBHkdmL<=D
zN0^BRr)jC!d<8f}@fws+tcp(fxQ4LdmNzM87qbj1or6zaNaZ62YF2b*3(}&*HEBhf
zF*BfI$f&PS#mHs?8smMWa^UTV6OA-THS0j5s@YGWY*I@k@@44cf<|45{mdH%FaqjO
z9><^YVtHPzg9e@;L$(KFFiac8Doq+7v1e$*Co(R8n}C=aH%g+`MG8oSY@nxGt`a$-
z`=i(3_S`TYD<oSIhIXnoXV$QGoc5@tBcph~h^K8FVb9Z)XFiZiv?m>6rCg!_KpAyt
z>fUS&k2WR7Iy3+`+CnER;>vUfFZ*PwMtz*k30EwFf+MCgf+wU#npPy%&V*f6)mZ%=
zIi^cVZ0AGN7q(8p+{P(JUL9&lJ1L-ZQMxEFnh!_YkKJP_8KOpHj2?VC70wd6j|}2y
zOt&$<lahGqh?Z_o+#E;iMlH3n2t1t_6rtwfsTE>tJQW8k?Hg9o9sr3c6G0u7K@T;l
z*l=5v^f3}uN>OVnJJWO;T9Hs=iQ9#1ku)BaaDgbUM7^`Szf`EOuBDI6?i0UJ;(;m3
zIjW&aj&-{<9+i6Jjwg}xibnIw^6KJHgBKx9hVatd+`fR1d6zbXDdmp1);E<%TjJKZ
z3=LNX8<hLTmKG;yyAv|9hjLE&VV)d&#+9glMbXKa^m}Oz?UJ=@Xi+v_AB8Jc)(N7o
zauQQFv@4!iD($~eIJ+iV^zGz+As?o6YKM4g`S4MiZsd{y&gxQhTLg2sG4b_CbY69t
z#7VKWjUS5G8mWCfWm7_zv!f4PQl}CSB3-SXvXqj0>XbOLGbV>$#|_DjX4xVw6W9Wy
zg_J{DOdL!G3auHAGqtG2(E^rpG#TTk&WtyhGzjnnA`$Zn107)=R$4<23BHxdhj}UF
z=gE!XDC{<Fbr#!@s)_eptobEjKB)x`P7gHU_N1c$gw%1D4uUGouHO<EkPH8DrWsY&
zTfnAvFo48)x^cU)6K}dCMzl2=5aj_&AA|&t8zIUio;>>GVw;Dgil|`)(ZE`i(7esA
zSyJfTG;bHiAQkT&3U!;#w8<DQ!T{@x_)P9!(W-8pS>Y<vQJt2tdtjkeF{KcbNXrUE
zBAnO+1SMssu`wJ$&GgLaP(9Za<d%KMFs1Scb8yC7GonGi51vFtA)3yRVt+@Z<wX5k
zZkEi7>!5n62l-BdwiJW{*?>HXYf=Dh_6em(7<RlQFNK17rcJ}LPNZBi;XIS0q#zQ0
zOL6Kdp}&M&168RwiK|4L{Om!IVv{(iPa-3y12`Tf#!P!t+AE&abG!GcMp#cFxwb#7
zf=?oA1GH^A9igDHkpno^mEI(`9IeAd20&5DV_B)gKB)^-HTNS{BF3QugoeNiVZIT{
z5S!`_H>bcC8rd{iG!^eiXDXReE{gKfnF^A4bGRb8hcOA-1kxt#e5ef&M2+)q!X*Sc
zwb-dQNFvVJIh{`XR&O+eu*%>`n@J|)MS%!=t_DF3B!5ODP@RQx&B0JXjl%wUA`}o*
zxg7MmV4MslLQ-*R!NfXFh6FEA(Uo#I2vj8=le-0G0MS`)E)Wlx8+mg{N2fH1g6%xM
zP+_<k8R0Z|Bg&97H!uW5ym`g|1Wig9FjSsVLK<m1!--Z(hx!tkEzd)^wLku4z{cfJ
zT+Q?Jmb8Ms$8s$QyCK>`41EST!;Ke>gR8jov<{y$%Mh<=<ef2?U9#d%*^MZT4Pqkc
zT4|BSW_C|bu2GepD)1UOnyi(vB)qMrAfakvCSu`+#L91luvG%S<7#>fqpf+S-MAqE
zI{F*c;vHTR0w7t?4CBEqOUDKH=~b&e`<ilu$;D!(79%mb%g`V%LkzW?ocB?90VYU-
zf^w<T4ikc>Q707MYhXm5*jvxYJ7-|4n6<Lv;3;bq`VSc35UYmlW-zc<1Ul1)XI?it
z^Iq`aLv#Kee;T_$>^Pn-VC6apP0&qZ;}XDt;CUG-bRXO>;Z*TWDQhI-2<AS4Mhs<}
z(a23A{&Mi}ssL(RfOw2^u9F_!xd|oZ#lNu_z}qzBxohQC#KM3Jt_k&qIdg!Hm7qJ5
z7Yb1$cS1H=YsPLSP?OC>9DueB#KFzdxqw$P{+w=JEAJLrmOZ}{-|fj;l4G*?f(Du9
zjzIMYm;s(8MCkc>ulG^b35>-Bz5)q5T3Or8>P~dJz9k!l6YIZjoRzL|SPH`G@9#8}
zXx&=ogyGOiNNi^DaJAveY%PhGE@mnNBUbU8<zpre0xgjmg|JSFw<tmZeD13QAs+A!
zN4W^cxE_HaHz@{rzG`u{vD{^dn^4@y+M%VVUetM!S%hJ?5m^HUXVA~)<~lTEc4F%k
zrB#BNypWI5ro0hi^2YcE#tr!3CK|jL?bPhtO>o>+frQnWm+)OY#um%lQhJlmTMy!u
zPzK&S4?_;tZg<>Hz!D@z)GX7o;lc319#$e4oO4DV632!>Oa-f%zJ$`2Kj4FFcT6)N
z@mR_qB-luvsSt>$5KAVQI&=IT<h8j3<<wYktTM8c_yH1gNtS_W(a3QuW3nuzLEteb
zRz!pW1BCp7O9bnOQ6mHhX)vR+5CN-bX8{I$iLib5ZUVvhkqhOK$i9oS=Uih6piyEi
z$WjL5*r6%QKMJufuyK<XLU>;I&*C!A5=FTz6tlgdX)tzAD7U&x)Ix$7$1{7;3^zA`
zWouD_IOYSsU=LzIiwVB9xd7I7G!#Cv>DXn|e6)s?f!EB>SGqaX@-U5vG`+I>4P=qb
zG398W+8EcCm<|(k&qZchbm#NlgrtA_FVjLzkT*-B8`82fPZD}VC>Qrw$PW@UO9ZaA
zQ4m(cwtNg(5jSe_-W(mtXpW>Az-}@kBe-nV_LEu7PBl<LX@K5XNl1uwfrWUh_n-)i
zKuiD+j<iCz$1{{=nzVB}SILX#eF=BC#1QWp8#EL_!i~7C+DR2CP6JQJ$$PvHc9lNv
z9|2@5D?u9;&|bNcmUT}6n_gqS<MTc&i|InSHNy9@KFM>h2%C8Foe3HyfIwkz!SC@-
z%s&X^nHe_3i?<j@RhW2{9t#>cv6(!|!;T=uHiZLZ%t21wcq6Dji^^PQMsVRjXbK94
z6>%EeG&WrbH7PlriK5Y!X-a%3CL%4P3^dEJZ5l#V()nO`mgqf!k9)R^b%x8WT!4sH
z335B{*qCoeV{@o*$85!{+BqF|<*X_q9l;#bHRX1vF4~{$i-oC|aP+PUsrl?Q`+;#?
zB`LCs^;Ti4)Quqq)yCc1O18G0(Ba5wLC4)VHGU0}k0%Ga{VwssXSHF&+n~g2{bbQ$
zd-bE-1dpwdtuog+bQo`xWEoj_kFqg)oYitvRR${0eQ#7vyr$)Dq{<}mg*Fln!4d$u
zMZ9OsD-;b1kod1wRbnC8;SsO#xMo`(V-!uiI2jn=aj-=dx}qk<4_n!iXiNKA^a@Q7
zN1K(n!L&#B8feEdF+wkErJM$<NRb5{`(rL{h`gWLn;jQPFlx4Z*-2omoRLw)$26p+
zrz*CNOHw@xTh!hA2h?#Fj|ERHT?SXPSM5wzge)wge%FXAuszm8$1H2CtVq^zJHxQS
zZh%OePsex|tG2tnR4Y~QoOh+sh7=Y=ZJ)?iPa%69eDpQNRL*oVZA7KswSbb3jDy<U
z=0bHv*~?a$^W0vsVc{sSlUNoUa6Q8V+AZ64!tUKeVPqNlFZAuh8!;!hlZZvED^#hV
zVjP=zep|#vuFLnwO$?G2MiL(RYjQwi>J6dJSmc9D(v-t?uLkUPcxPeAvxUZ<m(y5=
z+pm|G*qNNq{*}mT5<L8=t~vW=&Asl*C0DJu>!MAcd$d@sJ^blaJ+iX0;tNYgR(xmI
z#_<CmT@{b@EIxT~i97jCPc=#p{Ex<VIqt}L=gu9Ow`K2Uz4Z3AlFT_|{_Ex^^Do}K
z>D-4~8`Uo=y!7<)k@GhczMH<g|BN&5N#-2&rP+tfDb3xy;_Cj#(l1?i%^bO|_o%lo
zJNDe;&f2)*(XU*8==$rLhZhbzdER^HZa({8?!9MLZO5M<{^W5_{@V2Y7<=PCx%Zkw
z9{kkTuXy&jE5GpUaS#6Tnd5ZMFXpsg_2}Q9`O-)K{((0?bn81#`Q{1jhkm|r^pqzT
z+<(DSa~iez7ysnE8<)K2Bi~v4;D3Dcgf%xWU$$@M<*&MM{^h59?dtQMc-xXsUH<Hb
zMT_2k&W785y6N&|hn%%)&e$n`bNzX*|Bve*y87QQyYej;9JaUni*wFDitB_|&)Glc
zl0`rL)1STM-;VpYm;Boa8@ir3<!58RUGT#<|J@(|@H-!S?<LEBddZU)_|>NGd%q>}
z4`+OF-ZMA+*<0><`TUQ5?&#-#`pi2v6@Px*f%wtCJ2QRsiw~T=<%UC!c<6+$uKxL~
z)7;*pw{L!Gjvjj6miwyTdHFfb8|VD`z|AKVy3ZTB>G;dPcv^J%DgWA-x21mA6I&h}
z`SPOCu`l=Bf91-dbN*=6`-WffABFQ)f3R@#1)sk1%tKy%-R4<eoU>}+`9tnK@zryt
z4!dOeJ5PDy&AU(h=9~Zen01HkUHFYRJW;vjO&@#fZ{PT<t6#t9wXfpSFE`lPp`UFN
z`RN(&>-yT(<)>V@`>v}W+kMh2?qBl2{f~~EHhcZCpF8iexG?vj8z!!L@MH1ady7y1
zcJDENvitU<AFsXcXq{j0-gCv!!oo{#{`2uIJ%6xze)-VHuWrnK$5H*I_B*$h7o4{K
z*gfxAf6?d}i!QqF4}0abqkfb;bIQ+qHofe|@~v;baQ0&_eRTHyOMX0OwCC;JUpr-0
z*JH2y#K6D4@rmT4Z@hT+W4)(6A+mAn#2>zD$MxMO3_f<z+iyMc*!v4RzJlIO)BESL
z;)oyIaOZm_$CDF3aqEX0d!xf%x%UsYzxI(ur$y`gCeIj(M&zMSjQ`}re-<y?+xx9X
znQlG0X!6q8M~_Cy!pTN*(J@D!dhxX<Ejq3~P(JSKjSnVAyyTyfufOBV$!Vj>vD+#S
zAJSWRd-T97-kuB|)-1jM55F0|=CIfG?Rw?wW*3inc=k5;vK`4^ym`<+QJU2{{qb1~
z4x>wb(9R95+JoMI(SP&<a|cg)V5yw6zyHAd_xEf%OBXfHXq4MS8(Y4x#{08ZxAeWM
z-IG@>N?Ye#Fu3<UQM$G$gKar$u(5kA)nE3$>X_c%6Pqt9m*r(i;!a&tf0x@>`=5nw
zS6leDVr}jJ>>io7H}S*U=>FRhr~A_KihYBBJ?yWEcX;W0Q#6#GUwp~byyDTD<`oxh
zI?Z(3em?KwbrnXBd5P3^EcXlcC&hdACwmzm*(WG9qERnz<cc0x?n~XGe|mK4uh@|K
z!A5d`--4?y9GYsMKbAH&y-hZ4KIUbvP<FnSl)07WXCn%_sasn68sgSDi`&bS+-=f4
zW1B>BOnp;fJnoNtyuHel<^RU^hIWi~6`fyIEJ|gZrP2dySz8UXYrWkv;s(Y>b;N&2
z6aQV79Ajtg6Gli$BF8u<a*_1!*sMGXanicVImZgzo!*dU(@ArRd6b#1xq%f9OHN-e
zy5f3uyG|A77m76B=A`&l4$_<*aimCPS9M`os>H2{r1dWN-`z;$D2<!LJa0g5>+34+
z?_9EHGjSWE!ENhQq6I4ckL^s;Ar~^dCg>X<7)7s5@Km9QqArtEU7`uo*GBpE<h_oo
zA+l>29grQu>ZkV2gSSlDHPEVw?Bdj~rT42de!m+5-(XT)MVPsvDNZ8e#bV(?X0Z$W
zUUq=bPsLlF&4RSh$&+V$BjQHvOw-6e6XPZ-xFb9vkN5x$acw0Y+#Ve%XN&e#Nyn?l
z%xX+0oWI77V?T0UZEiaj0j}V9F3nWrz1r%J{A%iW7DM`4<h7B+;`!5cqAn3_$fP)d
zS0X9G<H9o1k5#%;q=}x)-YPejz9sS)>J-pkD|V*omtQ9rKiW?{pu>L+wVs0W<pFI^
z`iybOkQ<*pChIPyc18HAPRv?^k}wU&l%nk;!cnuZl%KQoMV`iaT3D}p+u~jxtETd%
zyRa%ZzNM|`Lm|Gq<nvEn{EP3|sj+b8>1&Jlj?>+1p5O4BN9OF{_v8NI=$oFo_{P_6
zS^n#HU-tmNA9w$4zj|i<XD`{Z^0y0TednU5n`@T;>bakM_MI!2e`Cq22e;gQ?Q2(l
z@45A#xoG9nKRdeXhZo&-4|B+t^_+3~<v%Vd{(AlA?|to^U%mQ*Ti!YU>DQkS{pyjM
z*1q$puWq^Ernk-c&RbUw{E9PA@BQqWEgQc7Z*!iu-_<+ercHK6sPeSP)33j)_opY^
zvPov`nB-j3`h812#J)o+dTc@V{egdz9$QXE`YXPkyfm77&D7SOlAm8INvum~Lp{3=
zi4#AYHBZmjJU1&!T5}G$wbi8`b+b~pqWiREt!*{ge$73N!gW7NMrM_JZk?4Z9PeK1
zr2EXc5bNwoIVRZ?Er>>5eMUOUM+qjh-t+!LRidsRu~ON@Z$dN<`v6s;gQoA!i}@|x
zSzgAw)PBIu+K1SZj5flEgf|mLE#Rgp30QXLl#}An&!*$4wci8e0$<37N_8{jVIs@8
z1FS^@n$Y)xYIcU?rxzH_1OP0JIZ7AMq?ZBkRL@6wqy@n@ZmlYbG+FD*v?(utCJLE7
z>OoVo;KxU4guMjZp?vG2jFh&t&^T(dqcj?MVS$-Cl1PchS0mm|w8Icr57jaHdXf(D
zg%A%(_a}Y?RaiL7aF3U?-k`t8TCzVzl1Y_b*%hACkw_6)sICG__yj|nXNs)tyWBl?
zS8Ko#9@m{5NZ2^m>z(PN^%zw+p=F<(2@v_NgrQ^=!}1z!N@@H@l!BugFSAc?15QVs
zxuC4PThguIRvA6ZM%H_b9@`Gjq#L3XfSO(B%`!Cc&P9}aHmg^MOyIgv!LHs#4i(1>
zQ{x3Ne)W66CnM717&zN#E!d?ZW%BDPByl|11A%dpHL&Rb_+nd54tT}(eq%=xu9!z*
zibhpX+lT%GsN~NXNJ}L0qdv?s98;{a1<6@@kf+|sB<BRV<C2l44I8psk`p<fz_Bbo
zp@KqgvOA7yd|ggzrX3o%GZa2P9#?Rq$wVYNUX{rCG~p8kdDV`RJC*JwY7C?oilQ({
z)(lz$^w!vrGwGZ~RCtz*-TwGFkw&*1>*FC)hWnVQIA)u{KvQc#B6T}wDs>xvM-&Q&
zX}}`(SCm+9smKVNPfz7t0RCQ%!xbd<rcRwmgUC@{NicQ`@pVEOtheOxwk%L8#AM}R
z;uNWx(a?8jbURIsj3P|P#~D*109TiWEJ&&`tw|W2iCzY|YF*2QU?^y4wFrv&(94BD
z=BUY&TZ!XF3$+LX>_=qZjX=|cct9;(o04QfT1MhDL9p>UOJZ4*6_<Yen^gQMU{VXG
zQ#_LS&$KX30x`FcP~uTz^EU5|<P7vvGE3-;)(IWgIB5$CLOPhKdGn?>_Q{uObI_)N
ztm5fFm--G~3nfvD3w76_bF-MCY4R3t7{}URqK>T=3Q@>eEuv*k2Gz{VQl?`;v`l2g
zpeZP2q%<CRRyjuS2p>U@Py(m`92t01+x6S=2jez7zVQw42d<0-_snU`OzsYbyveMn
z5$L#{;54-1%%GC#t1eUEV0xc3SWRT0j3Ea>529e9fIcGy+;lkz9gQ^<#ER*xf#f{?
zAR`eLz|qWel0QkdFpz{qO35<NPSv_B4>~PKF|b*K2Ye=!enL2qXdlpnp1}z+voLhC
z^G#c=(rd)3^GRl7st!@eFK2qw9%C@y7UxXk0O&hrVd5O@W?g0}?v(hV7dXJOIQYTg
z@G2s5T@0ZM)kztEkzI}7z?(zKl>d+`NJtiZXWhs$Lt%c8lbAFfh2KXJ-^%d{S<K{_
z7~{1;!KC@DHKogh(beKz&vaKvZIs4VAwT9=4+Hx2_bI|+FJqi7cDYHRNJ5TN4mIe@
z!0k8iQo`c!MB0J@T+lKrQfy_bIMFGhMzd}VHo@fshZ)aGB7+QXWhX3)5sc3?Nb#Hp
zC5B*}c<pZ&;<5m7A!=|4Mc5V0p^Z-mrsGoNkw7G0OX#yEp{Ql8BLfr*<F=P0jmLli
zmf69;4d5Unf{V!v2$?zsV`;yanPH06w?zP+EAc@_M52Isi!{AMLXW~KidnUjh)`Io
z5oOT#I_9j|86E~;Q`BX8sgcdG%RsrZI2Nej(-DR{u1+aQZz7E3%^@_MKU6hRPE%v-
zKr6N_cmR8LX(%A<fP?a4NFYG%r0=yH5+mk7L?=$jQag0>lT0>AP&rF;kT=*b=MLjz
zhG!+1p@-S-taTRYGmaOzaV|M0)3B(cU?OKErkRi@>knge%(ydzOGJKZd?C`Z$cJ?(
zqjaNC1WN~l;vhKFka!@g3ZtmRibs3I&1Gh>A^bvzX*+L=fj-R_9yK|m1)VKd1M)uz
zJ}gXJP{|Zv(_Fj{@tMp0SuF&!cK5uc4iYq{dRzB&ASSOcD|n*>2RD>4=-|jG$>q5j
zWe++Bv6jx38d;>GQ)l$En5-Y*b<8%M23qQHMz{=^lcx=lQG$8L!s)o2kagHJ2y+z6
zOAgBNLrMg^qPEMaGxG{0AKXwd%g|X6rfd|jKprI;)cqK3FVH$<3ucv@+8i?tzxPgD
zr=wqhbjsTyx(<^2jHA*vJkQh{J_B696*s@k3wTz4v_vBu1O?@?(d2~&c0>SbPN#Yd
z|6Rz^WeRz`7s|=_v(f5z<@gtfJD4)3n;lm%$7G;B*MzaDLwm7L{%SOH>;g2n|GA?b
zhTNwAIj6;BI(E|d8O#da(Q77srUoIMx@kU}R4m;zPn0#wjvR{#Icg>wFF>Y6oQDp2
zYAu$llfL6C&oJsan@#FI$8+xm?bX&nA)QWZ^+N6$A=kn6_weR*LDUPOW9K}=<+0v;
zH75fl;H6VW?U1>%;kM2~_y*Huv<Qg7vxpqB_$<?4w}A4M&|HtqmL2YCv4PN$-HBBY
zk9{pyb6*5~&oY<W9-P^D8gv?)MqZrfbi{uX;{KcD{vQ;(?m;%HfBgSip#Pne?nRVN
z_{DYlA~x#xzW~kSIzB;@HzP>szXysOJ;z4dzCA;{o5ll{HOc9QnfmEye-NE+dpaF!
z+hIAdChEZS9o)e_#(dw24edXZmAH;fKOO4>DcHIbiIwbLBZC@V7EsMeEH-=x%`3@^
zlU*I!!K|U?HuvVM#gNw7lFe*X;!S^~6PBC`25RZDu9*#jq~nzcbGaF_9T+gK;AS>a
zaBA4bieMSSU^Te2aVO#hpe)8R%l=%5!)2tvwM@yDKf>Cfl4+J9RDew$3tMTzzLnXG
z3~j+#0yQklusE$oD6N&43~;B*m6com*S#j!vO%;n{2-W(reV5zpy)L9Ao5~bRyDsP
z^I!tQUYuxVti?q$2^sExmz3Sp&7`XZu*LsJpv-22^kpxQQ{)!1nH4YGOj@LqA};Fk
zW+lb4YBXwC`-6De3)Ko{pB~B~RHotf-b~hxNQz($3>vC1SYUX%kFm~n#2QD@vNM<<
zn?Ma229kQz$TDOt&AZfr8XjR~+1FC~7*x%dsTQxOk+mKSYP)y=inv)uR_;)S8Qt3%
zkJ;#!jfSDfF7pEva|s>gjOfgP>!7N6qc)PDGD>C2W@|xcW|0g!HX>Bekq#BxbT~Tx
z3<a~y;I-|*+zjEqI!o@Sv&phm$iWU-G!_Y)DuJ4lvKK3}z>DfX$PcB<qFwN?S`=*b
zNAD(_(OQr)OcF1l;J7WW06w^hdA3K8={-g;U^DCx6HBSd0=2UX&+IV5)v3;aW}^-~
zHUtcrse>{;$YeX(!UkiRXYzcGvS~}kaR@1S5d|oe3_E!D!?~tTxk9y=Vj-JA_2M>v
zoca%?$n1ow)=rwHY8Y>vl#yXYGM|O6@o_mkz=y%#GZK5KnG8x0#$(TGHL;p?vOg=C
z(tfxsDcPtg<;*7(`j<F@mQm)05EN`=^oH4qjMOsAGqetj;3=XF;wT%5+06}2ms}8U
zwjs_MuVriPBxG+{Im?ca;~u_atpuvkgAG1#C<^!l0d_%WBg({1g9}*TpJ_{@dJS<X
z=mRqCKml+ysFJrK0=XRm)zm|Y4uniyCp6Q~rjblRyAv?*nYvc;EVDq3Rjueiuv5Uy
z$*7%e8|*M$!cZ<a9M=qGathva=ZI|P%I#ywe-3^+N&}X;)5HvUVK&o|zn7O-XB?#Q
z<{M~mUr5VI=J^@81J~&UGa~*A)KAAHV9v^aE>G2h9xjjb<YIp_OrOUb^fX6b$TMyD
zgN$I#F3R{jpj0oH)%FYIKr_(b&Ty(7oR}O}(3#)}csZDvpBWi&4Xz7rsQ**1%5Vv^
z$mgL<Z`;~8O6NMLm8UI^&CpTd0;>9gvZ&E;f^RtBB9{}gQajDsy_bW{9gYAmkfs)o
zW1w7gW#um)5{&u+a2Co<(Wx2B(dU=AGtT-j9QNL(gS@p7cP+cEp0=VpzN~*fUf8dC
ze(T1OBWn|b`-ju9LyLVQ8~ZE#9`0BvI<o7*R#Dz5e_m`Q8%KwZA6vC8UbeeFyeHbZ
zHT^5UtY>6k)#QzZBfGAh%ZIJU{Fhzd#==0io^NU6)B5+1svKHu^=$lyq^PU@?9ZEh
zBb|JgO^gh*j+cd<d~>~4D{2~;&X4eWSTbTErG#DHFm_sl?+gc~n^gXuoAjxXHQUbu
zYh<>`Ok)+D8!3?0%%p*TFRsDa=GbsNVTk1$d=0MXhu@ze9leT`xUNAbA9P-j+*TN7
zW#2BG;iH~)abu!_i0IaIIBL5#)p)&=v@w<p#9fp9JUuTo2YgTb5vkPV4BwQ-aFMh$
zmE_csxKNSR@q&p`GF;G!_9$Yu7HW<Ak|sa0eLc^G8!nAb<tN}OsSY#;Vjgzx=Gab_
zZ%41&j}%#XIo~VH^$G@?#D>-$ZN|wAsA2Czq1&I)90v0EcA3dsZa4>SU_5F_W?$}Q
zn7ts_<se&owR;@R<0&>&%ZIH`c)U44RvmGkNA^J0V)%ZcMQ8FglW7t>xcLTS2+!7A
zPH4x0mN_aF5R<Ku=CTjT!hs&kD89*YlHhVj=kNdvbzrE2@LUQz-uaR|JV~Eyb>ggi
zYUP;;*4HzNLe4O>vA|5oZ4)9i<!z>Tdd%Z^WX`F<H(fJZ<z#g3z$OrH0qmi8j?2UC
z2>C!kuKD~2z_&5kK)Ev6Nm!#;*mANi-~w)rPUD%)vIsXV&}7t&Xm<MLS3oAXLU)TE
z2wcMo!63@KO7MIZ!0liP-Xgb7SwCbsYj%49_5x_n)KN`KTNl~rsnQ6!zJNW{c}6kY
zIBcD_{|G9V&myN&+Wq-xu5ia*#^Sil4q0n)d0GuR2fa-mkhRS;^eq>{v5|o+^`y&W
z1rkn@BR>09#`cRWtl{6V0Gj*1*V9by?~R+5elXS@L^DiZOgI?s)JM=VFW<q~yhJae
z`(QiMNoTTR=ijgAWZ?RJaWe%U)a0Ph-<QT>(|2vone;_@y3EFT?0@3v@6z22(#+_C
z8dy$wO)~aO1L#4X+BDfuW1ZU12va%T#?cpo%Y(lY@j|u`>a@2`n%`x~>L_c6`n%Ep
zPZay6%at8njoEsEn@&X!(5%!>nTw%!!l8FS6XM6PSJuCV!np0se#AMVZ9=Iq-ga!q
z(uBFoY&pstWqdW5tW7{v<`MX<-wsQSLw2^O9}_368|s;is6kx57LC?RC_ns@TwYe^
zeHn@Hg|kki=VUb!&Ll2-4cW^eaaq4s6E03N->|IL8`jRXZgZ-@33Cjb4X)1PKf@Jm
zT=26J+D)O+GYB-Z@u&YD!dNb^6Z`-B|HmwF)`cRUtmoo7BMjB9KI^s-)z^Wfg9JZk
z_Bk<5W;E6;ZHO78c{wn<Xi^<%)3OZdw>XQ<+3<f*HVWYL6r*e{do_yMIRzTj6m5vM
zj%4=eXruS%w+~R`5<53U$w@Nkm_tu%Sqi>m74{=EoJZkTE0vecBssg{pvT&iAW-?;
zRGYU<tyrU0#X4w}K-i(>_Pg1o7Mp}snyTJ&xD2~OEKTbxYCmJ)c=d_|!kb;Nrb$Cw
zZ4~{+;|Zwh+~+D5EltmUkrw<2zip?!VWa?-ivN1zTalE~0mlx!X`b~0k9>&)7?Fwa
zcz$6@zxUaPq|_o3FBYb!9%J)3;6@NxH_UAJslNp&s0nF=F4>-5bHP?Cz#kijuo80i
z+Nh&ysUr_jr@D!YoR!u?$cjQ?O=WHXjLDQWp78Y+6+n~Fju=J^5-!8E_jDX*V-|oq
zpw9Cav*~P1X<gKCuY)Gn4lxAQZb+t`S!xnJld2Evb{hu`aqt>u<DtM~fW8Hfr{E69
z4`V<<l7)%Q;x)01mO&dMt>PPmQJA+{u-&VFXarIkyxbhN)C%U)7Gunz;!SmgepgaH
z*;TNQ2&fCf6j634CSy2TUEPsw0HOd})^iBMOSH)n&=hT9NBd^{<xq^GlW-VUF_|Bz
zSrim!b)2TF2?257A&1z77^)6PJRzs{T!w$N9P`%V2%)#R=n+f<+9rQu?8Hb(CdN@g
ziEY@ImS`s_7V_+g=ly|!LX|{85<cL#3U-SJOA%Z>j*aDi`Bju}L11R#cyJszC9=$8
z>#u;)-@Pfrxjd*EZd(iLnA)buB2qZ9k&~Xl%$NEr@CR^-w5kf4m_5#p*P)3CB1OXM
zz?dQ7#z`iOL_ct3TpY{-X5`p~eQ%_>K-3*ONgy%l_Ea;9c(W1;XsB_O1#A!xbcQc%
z0$Z@QwlQ{whO=>eMIO^7(pJ;PK>1*p%9KjNm-urUWTsGBbFJW_#O7~bs34Qy-R$Dm
zvq;#q`u0(fV2-s~OCVB}eiv-~N!pCmJRcN;w=asC;w?8*E0)D1b=fVVxHVAhrIi*O
z5iAv0kOe0x_%QOWrovtd;*}w$W<nUi(Fj!lXHF711}1)jz@dn}y=-?ZX++8ZNjq+t
zUAiD(DV7duabpPE$fx=xPF*XE$@^@Nx1OaDX@y^@A>?2t+bMEj#I4(5aP4BS?Nu76
zEoL-wrcIH7%E4}#g#MNGL=7QvnmDNUNSSUUu~`Mse8}OIqfv@r-OE@DGEx*x$dRTC
z1zHob_vu){ZzA1f6k9vK;sT*%W3yrMUh0V;tgYb7B7|9&Kx>JsQW#5y{C28a20ZUK
zWcG8kW0men#1BPoB6j=)CfPDAMLfcytOIp^#M<_Ji=mqpHxawfdSqxTbV#KwQZ*XX
zoG3Z$=w(+|W@Co-Zt>%+FCF7QUr+@i40EbP(WFu|1Q^X4NkTD(N*+<&-HfH!SfwV-
z*H?%&m83*Tx?L%IV1<3UG>K{^07aD=IkuqXZJeB@`8$bAq#**$JuQB+!0$m&O>yKH
z$j7RMk%(3wMZFVp&zq1PTkr4#)<8gqk`jDqcj-8;>$agRk&y<qpA_M7(l__W6u~|!
z^w-IPF^J#Wt47z3uq;hi$FY?;-Wij4n+hJUR=BZkz3NjtYHRu?iwbBs;2F}wkdLab
zh^NZPx<4t&OJrz*W3dfSuUD%G3Q}lBah=yXC>QewS{&orUM-9u%cS0quq0Nup4Enx
zTXDr5sPaZU6(~dX^h3(IY>w~BWLfrG+w;y_6H6y)#Un9^BPXp$#z-FTL!=B!8zHAi
z<OZ2+n0sNSd72CqNz+05=3Mu`(=%*tT0rwY2qWaqe^iU@*SDQjM#P&n<R?9`mvQ?P
z6gCf*q^l}6^Jr>-%2ZH*l=71#3w0Wd#grY6r;CQ>M}v;}AZ<2$TZ~Igu+vPUO62T?
zegI(;j=JN1gsw_7fgqOz22_sOl<Ac88Q8qgfl>0o1R0P)NHmF9GS3pk{0c}88Yqc|
zpmE0G0ZJ${LX1w6ap(@oJ}VfD8qtT}g}t*H&{)P2kQq8S3j*{dD^5KGa;Jjd<O(V>
zICOw;=e8IY8(yi7yjZTogm3Gakjh2_8)X$@(oN&fjZ5qVv<6{`98TcFS1usWQVkDI
zAS86J%o>n=&^T2xsL&0el(_)Ly2RnfTo|20<fbQ6of!ZWR-!CGG+;xP8WO;&%-Z7(
ze?pKxYhA3GcOV%Ksff@Zz<~j~%yF5ukQG*SMgmGf3vYRbPJmZqnDY2GAlTbxK_RpQ
z5>H|U5pNFWak#u@rD1N5M>J!D*u#Yy=;KY5h#LuX&`IH)DMzM*R45<&hR1PHY_ow^
zi^8!ADv?$V^Gs1j$FB(;8jB$@7!eW?^vWz>3p!$|hM*Yjjj75o-%UhNQW6idHJ||A
zMCFj!_vbD=*Fv5vGKA7O7mzGd;SoS54fJ9dEhNayxughUjn;8lgUYZ_mFDF6Db{e{
z!`6`bjs!|6l3f~C6fA;MDOuJ8f+1;20fO$S`YvZd7uJ1FHM2yVC2J8BOy=+moF?8x
z8lZ${IyJihUPD4$PsqRpcZ>xQc0xmS>N|RbDCo=}0fx*44?(*@ikzHbwD9|-O=iQ8
zjSnQzP<mcI3z?NLaab_Z|Iihp3p%*S**q2!BG`Fe9Y%LFA;N&bAR+#3WJ(lc=jt#Z
zX7P?FZ;KSvm+tA5B0ks1k(o`?@K2G7{0w5+WI%AdM{JbQErU>GrCpn1#DzAbW&rd7
z)CG@6c?`6+LI}`#Vq_^C^5aIPqeUV+;mFHaV4Tj^<{s8AopB6$|KeC=?ZvQZU?m;0
z>_1ZmBqEd~vBgC8x{M(PEpw8<>I|jVAf%GTC*COBN3&!k2YO3b9TcI3l|+anf&!;;
zu4O8{Mh5C>Tt^-iWUU<;)r^ko$ivbE0%(#r(1^)3fGHP8X6+1|O{)^-!lGdjb=qlQ
zgyB?U^jzc=lb3?BC^Oe|&7hh4q2Ux<(zdYWg#dUMY=&I8hnF92A$8)R3q>$6w$Xr@
ztpS89IyEA)^+uozncL+GiZJ7EAQcgzP@b@=kuzgsv!qSV(2R%6XLUiEj=nx%aaM;W
zki@>z?g{uXhIS4kgl2~n3K9wkMxSXBCTDZfsZ0g|7g8D#Jh)MoJm486B(i}y=Lk`z
zel9K#=gfJC_n9)xS)m*SP^<r(7KZaq>5OK!e1*+Z=<O{lMNJDz<kURhQOgt1T((6x
zi>Ked0K9Z_TWo*@hO#-8fMdZCsHci)Z~EY8B$i}eOm5`J*zQlr$D$(}bPUWRoVDsY
zyt7G~jRIZ9+bN$za7Z#bnw7YlkF&Q)93%u%;t)j6xnygs04s8z@#Jn!4IVj+<_KPd
zra^BckS2AZXc`#ImLrGfyphY0TdlOdQ`kUrcEb*2N<?9Rrq^fYfUXu7A{D(XeMj9q
zP581<L<|t@K*p8_putqQwr~izsp~8ZIP}QVWgkoqRI%g%7<w`}-h$3MQ%VgdXZpLZ
zOPD(aiwU>jk+ou03X!eV`KFwbJ}<`Lh$RZ+9ooB03in|kIS0I9B_CPwvf?5)gMxj_
z?|c6%D}a$)(9v}ak@LBXJGkCdx5CAW15WS9$w6rv&NVx$%53O%d1Oaw;NJr=w^633
z=3FR~F=7Xb!8Hvir_(|hv1W8`E16C+f@HE0O+=m#RAaGrjHF^E$>{_Fr0enA4DQr*
zjOaSsEojF#L^A#vuJ7P3AmO98xwQkq?EEsGjb+g$wG~Qjb5KsJ!^ka~sRl8Cv4p(p
z4lIpwy8R+AQQQ|QWWWVCcWmdxWEe2ZW{Am2S@s2KYP4z?@!+jF8?OVfu1XAX&W7}0
ze-b(<Nj+qeO&TU7wy?7mbV!lwNrYEhhoh~{YmrzLRqJXL;QuD<UEriDt_1FL@7x*g
z3<KO51{?@N_0Zyghz%ma7uGZl4vN?!CWIJl2r6+AkVQiblA58B(GW8})+N!^mbiwv
zM$t`-8e>`{iZMn)OyXO7Y~p64A;vXoP{04FJEQJ?`~AK%bL(;H)TvXa-gT?%B6WZi
z#;ROVlrzw4fm$BMI!vvBUW!2bA$9i^c*<4vICiYkF-Wp<QBeYeOXGVsIVo!GLjaAK
z<H6@SJBK?BOG)t>9!BoIisXHYXwy9k;u8<k??u5S?ZuQ|sC=DI&r=9a(k$s98m1$u
z_F!Iw&}u69`ul_=G=atY5v1~2_4jof?A%p^Wx^-GC_i6kFc3<iMvZ|yZ1S=3*_Rzf
zs?Y!t+SN9n2*MpG4uT>)t@3h&^C(rdthU}iw~jAeS>YZW*RIS$Ql(|uM#H;<V#;Hf
zL{<{h#y30Na0xO&D<6n}7=I<o>Kr)24REmzAC*Z4&|TUvYGUll7esbw1|a9!fR?V=
zP12GvDk@`BF6bz<)HV^GNagpfFtvqZ<Z9rCQgh=%UBpwCDm+y&OG~v%YeF}l8Jdo6
zYdRP=3Ag;xcN{q*E17_HC%vH-q%Fj~d{fhcckCv`wg@saJv7ojuVfrsV|-$0xsl$e
zR}5GGz+QTF!I)f5I;ul!gLWK3{D`t2RP^5{=>jpI{U_66rA5oesV=|pUql?%f|!V#
z0zU<{<$W?<b*oa=T6w9pne?T8Q=!-;xT;abIf@ps(NnIT9GQw?t~H-e3`ZtzYUSGp
z)E-xB0@Fs%#3Wipx{|WGQs<+N$@;ixkfqBa&yndAe`iFmukR+>VI`Z(O5R1YXt(U;
zq7BCvK1z{Ik|wRk?OeM@OAaG`M;_8yA^bQAFNhLEGJ|z28sA9nxz0s`SSG_BDWqvq
z6B;p+SjorPESW=b2q%GIzqpyaObp~u-$Rg4tI*cajIqHeR=<>Ljy#Cpm(uUV@?(B(
zFQi&o7wTPeT*d>(q&~?>^Hbm1RJU&8)cE3c%iHaP<xB5+sH-lSG*u?vKQ(^&!H4Qf
z%QuF(h8ZnW+o!kOQt8UC4sHsQF(X?FGo}pRKmMk0&901%PZ>5UI(Yc#{d+Q|x+1s4
zojPz-`>Cy?*Ozij*FKla-MM*4V=}mY^qK>?<rglVzPfm6*Wl!eL4(&XoPNxw&zwH}
zoSC(C#Ycj=DQ8Y^pFV2s_?3_32ke|(JD_#$`gWD~D{pdd{>+&JTZbQa{5wPTkALls
z{q5`S{nPhW-}|Q(cfbC_;O^J|JNwJ`|2FIA@87+2^?CQ7zV^HWtMBgl*6DZmJUzvZ
z{&CaV(SI+!b;8v(`%ZXh&Em&@@VO0-uWf(p@gE(z|M7EM?W!M7x2wK7b@e}NKWy!)
z<s<i>b;IF*Icvkze|-Di!`Hn1l_^KP@V&!xFMMUgx)*+U?D7{boN(cop9E{iT+({c
zv-ckH<!8S#Zqc)MAF=rPX@g#v_n!k_oOg6q<^9=Vd~@}T563)n#@8ly-SOnAcaB)Q
z^5S>@w5s&(pC;b@=O4_x`_KQe^p}?$TK~uQ56Z62KTx~&q!-$*?U~+m_x8@ItH)e7
zYuT7*a<9(#&guJR{B_)h%YHa$!)0fzd+Yf_Pu}zNA7)pV{@7F}o!8!ZM9;D7|6yI@
zThBgl)L&klcib1>>^Wl12kRzY_{`B?E<N|9wab5d{}Jn6_`)%t9rOKz&N=In@S^L!
zH}>2YztXno#antVdiJ8jUTAoI?2GdbZ_qpO{`rd{FP`yX=9$laEhyc(dUpE*#S_<E
z)wY7Z=CI`Zy~_&s@0hvr{@oK6ZGSD;@!DV3^uC@9o$|9;)7my2HLUvByK8RVc3H>T
zZBH-Dy?oiQH;1j6{&v&V^=psZbJ6OVH;pMiabc@{;)laZr+j%rX~ZqZ%5fJ=FD`eP
z(!7NeSD$*%2}ccH)wpcY?Sl%7*EJ@K@BRESXDw`)adOY0Qy*DSchsdnJZSWZ%MUtf
z_&rnSFZkTp<}<z(wvXI7ky|LwSGf<mMP%OnJu4<`k5A3r+FQ5ofgQEYXaC3QDgRpj
ztbD(>t#E(ufb6#AQ*tlYpV+(nwCs-8-K+(ldTD|^@5&SR?3|N*>+%u9?3{CtD;<34
z;d`5YJ@L0q%?GcZw{S+Oq33ve#Tk)(?1#wpxie)^&lhr2J4~s4$I;oJEo(liys74p
zx>a>+7kzWUNiAQhX+GoLwvlHoA2<5sdj{%#dCxs1GJ575b5iqVHMz^)NG2xnmd0HB
zd$h@SlZiJ!R};-WbL^HC$0YSD56=ZRe<p5RI=8j`m2=oOJSC_(C;KLIn>VB0kxA{Q
zq04u<aRqZzXJOf|8k+`u_7K-PS&B>V5nI|Von<%vE<O|TrM*MLIeTYDTSiSjWRJVE
z^_eS1H1FN=pLN}F?#u0R&v7=$6^b3D;niwz)KeGHuawQ))^gFd%ZN)RCOumllNgER
zJ(YcIdCT0I#>P>mXYfc<KWThCapU?p-o|)Zn4LtkX1yHQ=w&G-NmQWEnl)>|ie&JD
z<uW*^`F&l}fY}4=1nvN9Z(VAurSnQo{$bAEjV&E}H=g5Ki?%!}somStQ@8hu_@eH{
zlHApp)Y=X=+y=62kL&0}zS^YRTadDx$u~ylwoB`hoK&VT1dLm-Q>2SCC5fxdFycN9
z?jXyQka00fjs_wBH+cpbzhb3tYZv{J33H;3I{M>7Su67d1KMRzfzK5@M$k-pLEdXv
zdTD!Z5+&!xvgd4(eY1J>%jx6E7fM(<RHVu{)^VYcJ1;Td6RBpPzeEbXXG&Nt%+kFS
z-iXI?=O~f=ha;D+tVUx`(7XP)%kN-`4X-h~21ww>f|<;tP|Gt22?w}j=U@>tK>Qa+
zswx*_g=MUl0fAU#u&-LV;Bou|c^P>j{$&ysXW=JLRh4lXxD#V%&K22Bc$Lw^o<e_5
zeyaK$kDvDJ3db)bR%Vyp*~h?8IoJq`P%-oI2Txvwex(XUC6KUc#TrH_XN0YPE7gr$
zh^0&2EW_g1I4<ekBY}e(k)XTFNOUK*zFn<kvO04Nb|j&=fORRjUIRj>#2vzGrzCXD
zPjySx1R1H!l1PWRE1MEqsWqWa2pF_&Z!-0}I>D(lkS-VQ^)7(_NAQ1rzmx&Auv*7_
zF+6}NMI~!=o)d+QTu~!U%$ivbI!4$q8fQ2p(Vk3JTuUx!WA`oyTN;^Z%}pX#XhKI^
z3l-IeNn?^Px;vxwZ$A3bU4EPXo$r_4H|K+k_<rfXbC=({w_Ue?#kaZ3@7-ma_db4C
z{X4hZxPRHzr*4?>?$iNSt$4HRsXMOYd!?svm*2RV-(G*$rq?Dt{m$AKSIoHU@k48V
zy5gz_zp~-o15;mIKl;trr)92NdG$k=Y<T*>q!(9=zKd_8zW>J6OIFQzdc&t*TsGu}
zFL0ONimOX{*WbA3Umfye4PSQM>h*6wx?v18_qwz0s(<<-?iqZ0&IjgS$w7sOa@4!?
zfR=qb$aVXqh`E`Bm&-Y}D*0lS^VxB1jA_Z+>tr^yBZ}j)YOT3gD{Xw0i94au;x8o0
z?FxfjEN2*r7oaCeW^;(8APaWPl?8TiF=-zh#)qC%nQEpcYngW@QDhsWBW7!*wI##M
zC|g@<y=_-U7A$B?&OeGe7tN8Lf=J2gnKkQ$RHIK`F?|@<XGh+lRZYQuGK$9_WeOoy
zADKFhVk>HRU<zim!c*52Fh7cjSL12v_XBP#p?qn2Kcdg>@ppq{*%9=2(lOZzlJ*3u
z68e=(*E$)Vr;RX=Y|OIeawW$~ICn@QjiHN&vir=no(!}F<Fv(uHk5-=f`JXQ=30b;
zpCkh(AWX#WZJb;kNwg<xG7WKE(`DHx8E@*dln-ycgmqEZoC`A2HF60%s@nEiq;VfT
zO}pjNqB5TpD-Sc|tZq==NL7wn&30E{NG-N`YZ|E<!>?JwvLG-^>%yj_#mJJRu2xku
zj`nN0-RY32c5-B8U>iGAwp_ojHffm}R2w_Fhw;iN;B{2uR_F6kw~3SXpg!nmd$1#@
zL2)E9a$p_j3&uvfgb#~S58M)7s-TT1(mUzqe%7m>cPpj9iMp+SSbnj|Kfw}7v5mZL
z7FTWx3zFyhvDs1N1GITp^=k{EUjU+^Hoj?Q(d+DpSP2?!LHQxtgx)mKy|K@1;21j$
z)E9+a!f~rCuO)*9DG`?fXXb7R?XtQJlMxxb8y~|SCnij98D_a2B7s4vCCrdvC~Ptm
zchI7H@uUruv?(!U>cn2G-Vq;kh{H-D&Vr7_ur**OTXHha$kK2`Qw!~)NxxbKA!(qH
zV!D84O&>_t<f25TEuOCDnmVj59_aDn!XaIin}w=F3|}7+fy=R!N0}-YG?+}IN|jNK
zDeNezD&n)zvR@su$TT8am9*DiMt<4{=wb|>fDuRBR-yIBaZQ0&a5QgLE<<^{quUm@
zGAy}VrVUj{z>h{Wj=hPM%TjSuS`Z~lmX#E_z#P&e^AA@I)z;LpheG+G^MGE87$%t;
zTC{e#wCtb)w28};1+t+(SOoOede)WjKZLzo*a~?d#kz8>ivsJ!HkT+^(_vWLok0XA
zaioW6Bx6JAFj}^f)I?5d%pup*2?I@+bkjzCJM!mo7X6ktL&_P#UJM{;=RAt_dh1ca
z;c7+o$O|;}wV6)Ko{%ZBZ5xsfA-zx_Zd%sdpDHFT2MGlktl8!lb$E2&*-96VHhz9k
z*4${~-7Fkw{as#;Mx;ibN@%<EqOVXgdfvAPp|0tvKaPW5$Pq^T3{^}{mFhbu*@Lu%
zL^(SUYNe<CS&G@xmYs+pZM=onAkt1qTvsfk5FdzYv}zf3#;3ufpn^$_b+i$UN+}Ic
zbwbnHt3ig2%Mk!3j8@a_`{eLCtwo~gKoskFoRv?gKTRhaRwSZ)rLIlc0Rhzxl(p=K
z;*GN^XMk3NyasEuveeLlrEQqL$7`*mflG;=;HL!_G5vd%tg(#!(AYZLsLd%=G6|@x
zV$ilS)mVfXu4dIK2gQ=eAY+7gC{PjFD>I=;LaI$4gxC-xxVq4nb6D`=<cma(*UY$d
zzGQ?*3F89IC$!4!7}__WnQ`cuw19Tw(i%;7LL48eZIT!v1=Xr6d<kvFk?OvZ5EVZL
zH1LohtFgikUyniRakZqP6$L7z9o{%(<qQk7V)@34IF+@+33bk$1o^;3bTkPp^m^rX
z-8Za|wh^s>e0HHA^`I;<8@IuXb~n5j1U6-VIex-g7lc=Jgk=(7P-u(uID`_ak9xB{
zi+C$zOTA>x&|Y-@Sg;g>tBC@1#%I%_(1v;awzKkJ&rItjXR<Kx>28UKJrpw^pO0Ky
zXIw!5TMCer?8faG2ruQhrK8Hs$q6w7q69AF*Jp6aiW7T?YHhhlc7Yz+qNR0&Hm=fZ
zkwQ1+7<aennWmNhLKh47XuFD=3HU;GCG2ht;a4wB!=n6>p4ePPeG4KJ8XL%nW)s==
zxEQxZvH(qH$W>(EkkoAy4v$7w!hx<vHZEul;_tLYwvx$TR+ASFi&7SG>?Vg{=?ay(
zDd{MQbesBWL?a$$7+=LL;75t^WppdlE1l7jiQ1%<!Bpne7K5^ckJi?9jH6tow@$KR
zj@B)rybByTr?djc+=ObdE$Ozw;E@#urrrS(p3JM$)`(gdblvnwx`JWcA2C)MLNr%p
zd`+BD^+#cNF0DX}^thHl8WCVz<gTx8<hxws$z?`6vX;8G*v{vh?a=EPlOL@?%)@4p
zhG9LWK<*G<?KYkE!H&Kg+oeG^tkE2JzZBFCQ8*0;C;3kC(wfw%pQDzra~ih?KP9OU
zIciT_pg)p8+FeAn(18vjD}W|ucr==k&=HBgHjS$N3{X{rvZFg7?TEq3`Y22@#Om7y
zL*T>&r9!8z23G``)3!xT4ikru`YaYozQdey(L5NZvPOP9)3j*0{xEv1nNBmw8c8mH
z7;gLlCV-dzY>^6~e*axqQbDIM2rMY=Fp5NA>^05OX@n1xD06`J?D^8OFw<c0uy~E;
zBcN7eGud1%^=1}il%KGJOdO*=Cwp~=5-=>2DF@_GkpkkOYZW%tI~HUi-?}xn7nLer
zI_r#8TO$G8rvIIL)JK4Bd`O0TXl`KQJVMGBq@rAvN-EOM(4%~8;0gTO6oU$_m&fZu
z*M4pp!K}Cmu$phn?9XG=6r=TV(bt&(YFdsyVJ<e)N=yaqd*M%@#if2dLXFRoxx5(u
zR1l1jHmkOjBMie6p%S8KQP<=30FE(Azpc{;T91{tv9+ixzno%KHY5WBTDS^=S?8nK
z9ujS!L(^c5$U|#JXSFEa@?!|igo4v~yBMc#txM2Re}o>ZODx5v%F?VEa27sP=SUM&
zKgEYTb%kgb55%rHY$sXj7xzwwY=E0YMjZ@sWYwS^5n5|$G@heBr-PG!jnapNQiU#H
zCUcO=8bzc~Rm;KzS~X1SGUD*2O`U=RTcR$4u@*dS`Xk6G8BMMap_%Rj(EQteuSQPY
zpP)f!&`_30@IOGs*Hjv;GpZ!|G#_r9I4!6OKBJ!-(wN#k=)VP%0zI&{f9-`>g?PZL
z30qHD=TSb-xL~2&m?n5MoIvIE{Mh5P{XXCgLXIXLTILZMaDMFeEa91GONyjJ`<Z6-
zD?hI=C{qFPD}-EtN7Puug(MX$k0A<Sj0}C)lm#6L2nFj+MmV(zR6jMO?0X)?X>>rt
zk<s(_eFoi?)c^&WHNBMMU+cG3l+u?R2A#9de@}l}Fi};&$|92it+Wc(n+(L>7L#^u
z$}993=TkBt`}MrT1MD+s&({YtC91+a))_f#7-Bjf!Z~g&wu*Mb3RVpeCuv1N9{vrk
zwmdNqOXZ`_Vor|7i59k%Hq|2tBXJuD1=F53dP0r&>$E6idvTBGAie^v)Z5aP!M3CX
z7;k1R$vgE%QF=G8qM<N)G@S~l`O-49<T2{wr*Z9kP(jiL9&kP@7MZQ)T~Qulua~NK
z`$pK$0lQhTsVrDQjq38n$304a{q6f}gARS<e$vJ~C=ZqZBYE$Jn_?|bg-0RBW7T1h
z4oUg5o=9;S1oc2fT>VLe;B+W9e#BD(xM-lSoj6cPKUgLH-(VC$eRFDit+>84iKvXN
z$76U#%3_D&J&>|05HM=Qlr~|`dpwOAE-evUM5dIT)(GQcRY0=&hzZa({&KE5Dryi;
zWXjSLf>2$j;Mg<jk0jO-lQwVQ-O(pljqNMXR7+4OP(JKC;V7yvc3qkytE*9ic72K(
zkb<Tf6Yl!_&@i5107+j7Tkmt;#BF$#rE>InMXh839*AL#cd4Q2iKVCI(XujXIUH6U
zgfaz1LlTy}w7Mt}#x9un8wSb-8v3?SZLdea3#1-}tY;5D1s&s3=;>dMd4%fn=4%MC
z{Q?9ApQcCV`dR~&42m94HUiND@`Q)hsw_}hKdh;<Ur*^I1}>j~Pz*kk#`(B9F|fOs
za!Y~ykysy%CPw}=k_TtJBeWSmAJw9Xq@{n!sVoL{6NSl@2DSKTOzv$i6)Uu0`v*!(
zRHLm6=u!iqz`DtbwqNHIVLUf=-efVTH+@;sv@{JRQ2`b749Tg#SC=tr`T;R=xJ=)J
zl|sM1Ql%;*!=p?s4|S1!M1cJ_tM*Q1_WuH+`L<2KmA<W5T&Ym{%V-avU}aJdZrJF`
zh!vXiR*#^cz|w{F#Q<#yVWy<2S4cUgJkqh)qrIN`NI*CqgCeL4eGxpBa#O$cKGNv}
zZ4Z_T?NVaJ$DT)D_=j&%2V9!C;muqh+G|1eoUpf+hPtqXi_yknc?glj%i?_uW&HjO
z0abSEQBskq=vKjWro$uZ<{xRap*a21N}~{^mM>*Turf)f8F+jtrFGre|ErKvWt*WN
zwdqs@s;@@%*&zXgoBr(+iX)V&=5+fTXhR@U^KLH?aR4nf<!8KDAgYG*CZ4HJrdx@W
zv-Ngge07Ivs2&gfxiU6=xwI+YR8PFOb5L1*;Hi1{(eN62XxB`DL>j}&P<nD-RW(<>
z0#spYm90yal=K*!WZ7b59fsinSTkC+of^tZAA?D%JH3qyn|~)BP*Z#AFhPn@(}f?o
z`RIX!DxT#rmVQT*F!=eEOxi2c>A(Z56QD0DKSW|j+Ea!picf3$DsTMWj;hK-lv;7g
zmp@4aKm98xA4l~B3nW8<3f6zWH0mYqrsNkRA{%psc)3-=I{LJrGmPej>>oS6)47e#
z-O}(S;EQ0(8Q)Ces_b<xtvB@b(!DfF47>_Gt#PoFdSuvVc9n!P`mszw-dm$2v4;LY
zb<@uH(8_P3j10p^{gAZ9p`0iKqLUS`R>RV1{bN(?+9WWE3@c@d$Zo{=d^H70y}g_b
zpv!%h+f3KE47`KHf7r;HwEM6YZnc3U8eebHVa3t-XiKBYjm!c=ht_R7o2hl>&^1xt
zDTX|U@BK)JJWJxnkf;^Q+&wp547xN1VJzcaCV*X}x_lB!a82zY-#wz%wd+~62!68=
zHRiohkPJ+gg$!WsxVW>#4s5{|;|rQv?Y1oXlqjywgjWz+CZIY?3VfBVNX_;g;HB_*
zosl`tNYy0`zQiNab{$E_HeyS5p`Kl1hdGq0uMuqa7$(a>k1HuJex324p%Pf)NGJM@
zn;dyi78OY=iS^xkDBJM&18-PNg^C4Res!NnuV;bEatUn|uwmRixL3rG2)UMy#_kF=
zf~oG=T9Zl~M{_|~v5}LA_%cX0v(Wu9y9HoZQe2OY{YJulvhT#N2YM!F_|rO>2;`Ps
z-9h(&OM~fymK{Cq%zyaaikBYiIOfEiwXGX+#~(L$&Gd_3-x;iaaHmYaV#f62HcUEt
z&HjCv)sOD0X+I^bA2oXTi1luNu)6D|ARe-*zV)+L)o-|GPt!AZ?(gUwRMR+dNN?kr
zcfK=u@wfH{t(z~c9W`X*pw>zI#{c6xuVo6~tQq7sUoj|m+kx@NuAE-~$Sa#`JMSph
zZk=@8h@)@YF@DWs4-VS9@!Hz`qfh=fmG_id&OCkn!P*<PtU2$2Axn>cU`Si$tuZqX
zUH{_YN6)zAuE{gLviIm4elca`c^}^WxphyhU%&o|^=sGvZq?_{`@@?f*8O7X!RvRu
z{I#VY-aTgZH!IWEZGLsgx^KSv<%|FD=Aj#YboJr$esW~P;-4HjZS6Pr4SecHcMn>0
z(6s{=kGb~KgdOy`e=83=^25W9nD*gehd=kDyO00t9k(9*?j2)>ynn|}5B|b;%7;Ju
z{iCAK|KV3hEc)}EW8OUCzJYtrnlnJ<{r4>*&wT%ft#|)oO7?+)v&TL#c=qVG$Hcd;
z{p%kN8u!&TpPzBUoAYnjQcTu-_~d|fkKEt3e#ndo>pxsI_2R$1`I&XQmY%lo8%uL5
z|MpwE{G0o~y6%dfb*$cecJ92tP3he5)2qk5aR09hFZ|@+S1<Uc>3nY52MvqITqE<Y
zZJB(|kA~KMZc}#3ksqEc7k&BU!=C%mjALK9WAw;(U;k<R;S)E0>WuG}Yd(L+Kh=Eo
zi6%Mk+$$%)e8;!hAnTZ@XNQg)EAs63&mMaH$&Vc|^`WQ7w`?4do!V-%Ez#a19tdB)
z;DLk2UUL2DnhDE0&zZ3<U;5nK6D6D*bPpam=b|C)a}NE|ajmr{<xX39-umBPHSo;G
zU%sIAS4(Zf(-*B~ySHX>*S^W~daSH}`Kswp-h1^4i@){jqZWPR>Zr4}H+S%$TZepl
z^Hs;M+1xyM&-aIpzHjAiLwa9*=wNrx#=&vxd86-K&YRNP?>~6a<rAa#CfqiC*wy#c
zPmOOHPjd)V?gyG*YQARl*JoWbx~4Sj+BmzS=H)Leo0VUZm7VtPy3**@(`MBkH|qAO
zs|$6d&ahM`Prp2%;k0QdGz@C7(`#$T&8xZrbGOa^>iXZ$@3iG`+M;iqUSn&EN6w`U
zf2K>OUA%e!_&qoOdc>3W3~gP!b?6kAd!;_!`tuP7*PaxAdb1h1=<??_{xNR6@z!~b
z?e3h7{3=WSP0tOT&+sww_EF8NKa=@tX|XwC`H<NIRu7&%Gdi(!*r>tnr#A0vJ9XsE
zrO(TN(i+)p2Il^A+mPJ%mY!5|axqiWF#YiQLfe4)XzA$}RQ8Ntvb{Gh9@IXmIJ~o_
zc1)D3Jt#W6V`%BK9YgKdJ)7h!Pi`_JmW_9xUVWIGGUB!<bJ^`Tk8s;|4r>gnLs>{1
zBDVy|;P!GfysccLvi)+s$UV1go3(x1(wf!HOU$~4*|ya1utD}X8qnD^p_1=tdo4^#
z^G#9eBr^Yrwr_Homcho>G&CEw1j3+@tdUFI=Ps!1kBY;WOYxxB;+laY<JyCx+-XB?
zeA>`ze8KkBQmnPvwPQ=BG`>`-9ab*YZ;4tOw>1xCoVE*S({l5bQP@@pBNLS_+frWm
z=a;#s;Ff&dj%@cbiLNX%HXcVF=0dq^!A{Jmdxb>yeBQF2k8d5fZfD}gJf|*XVq#;)
zy>OCLcMea29n-`LwOS@JUh#^0-?%uC3DD{AJVAoW1XhlhD@QuqJcExu!^!D6;Fd<A
zEKEXK?<(#yPF%BdVJYg76@;w;KW(J3%gSO;(=$!Av%vC3TPmfZh&wwHyOzG%fGzN3
z#Y9uF4KEyLQLVC!Du>`byf1tlyN#1vVvoU3`t;c8?~@v!(Q{CrVFXzW9)AWk$!y#U
z7#2Q57`7m9GLC#r!@Ugmi7X@jF%kzaM?8asLQApJoY;%>Ow$EtfeG9c%%vG&p!^7I
z1{qmDz2rwflP{GbU4s}1;&R2XHN~8yl{Iwak2eRU$r0}sd&!i}TGQ#-5^O(5G$Q+O
zV=;YTvX{ecq`V*fla7v5x<J!lJj@+9ehVFw-?CH^btaq^)-z45<QzQdmb_d(#{Y*A
zo-v1zN{6iyT`XVVY&5OWQe!#{sdPj#sExxF61Og?wj~9F<bhrx5wsSio!@Qd>}3w!
zP)TB@<v~s!MBB;brZF5GGi?dwK=wM$5&hRkXP%xqhjT@LJ^6zf&%ZI`zEgi1>^|bU
zch>*z)D0WnJ!kV>r*P)!56`}{;#vI9-#*}~KfT%Y`4j$r;J~j>ePF|*chCIxC3kK5
z!cU(*u=ctYGv0fY@0Xr`)q`jK=&=n`uiG&Cy~oDg^z0w5e(0?Gp8nc~8#j!;>%XQ2
zPjlw!1HNDS=^rl}^33ZSn%;fm>e7MxzOZ5Cv#$=h`p*{yPfvW&f4}sdJK2-^^IdaZ
zyyeE#)1%3fE!;G5YkAN_Eerois{u8KoEHVhO>bm9Q{b)U%&=}vJ|4H+HpIE_)x{I9
z2=jI;^=fW6dTRc~=zQJf3m=RdT043glM%v6uyFd^AZ#nn!ENN6WOF2q8`;s%*oW6l
zkfp7IyCvCJ6PO_Q;?RnnR@~kk#b0lh-miz_3hjkDUGG#(DA(N7F-^}jeSNaX^?cj&
zimwZG`u~6=`UEo67OU;;Be0eNOWa5PPdYlgKI!XsL+?TBU?0@=J3eXmCDKo3`F%Kb
z@n7$SCY#b#+f7G%jaC_B;;6_<!$MUdke4h5EN3&Q%*GKTa@#dwvuwLdqKPg$#dXvZ
zGtlh#4Nk+68kw#ham;|ToU|}ORg&RE&*b?iK_lyT+rfdVo+PAK<c1Xqs%#c%^N6AX
zw!5@sP-odJ)vkg#p)1CL<vn&M{mZpMVvFV*wIsxX#2&J#O-wOk7u_sIXNWOBWY`qR
zH;id+j_6*SP%D%!Z2B~(_kjh8K_!mUazdxwL2$if;+vVkGmqfIa9eq^n;}p7s=yGM
zOtXmGWP5@<Q*-9IMyH{a6^n02H>s2GN}wIG>h;Ti!;xdp44p`g*yYk0fDz{mrYT4>
znlU!IH0YA{&^nNrSc9ZiB5Vs00^`~fp$hsEqSsn6`*?R0f>tQ;gkh}=%{h@Op4u=(
zd79ChdRq?z<9XE@Fg8?b6Sri>!;lE15C13#ZA}l=*k*jHmQt+MZpCuuDhNYW+LCfc
z8jA!Jlr=Bkx^tIhO$d9Hvml|(;n7}wSQt1{iQubroE`{^5QY9-6T(+mR&%JCn!wpz
z-4e>7GnNoG$h7o$y*<UOqmA5lkqzg$9KvZ0YfLx%$%EDP8mapCYEd`hvECJ%6|*(y
zDU+dkH{Vdhl1BPGjUwUL7TW_eBKH<#YHn-Rfz2YGDpqT#C&Q1xkhNDiNrKaQA1-nY
zL@cnn<>plB_)j{Ac!`c#P&RN?%Y&^fS&d`4<zJWvg}|bGLpd8A?&4%9moRvd5)N7_
z)}a{AIHPSQScz`S8FU!rC8Q)vx(yrz_bASNMSsl<y%(bsi#3_?19Gxl<*x~M`b<;;
zf(%c@qpbi)?;tu=>thO*0O*Pkbo)Cc`taba1)W5+2weeoqJ^>#G;LNZES1al_bn~Z
z1mpnz4&6w`Q1g0_sj4wTYtU^$g^FYsW|xaN|6#)p+|o@}+N`!w^+|^qN6P7^9<qut
zYA8U^Y2y%DO3WsCxRH)VQ`Sj`iz!(f7%ecRC8|MdF;*S|z=_x*efA&-BK+i`zYNuD
zYw!mZi?hLb&i*tY0Y=53Omyr<RaD!_FM(o{!Y2YwTm@FvX&&{=lhP?TYdA*%wg>|Y
z7j3UmRfC{}Wflk14kyVWit}4=$Sl^1#f&v=dKH4Gi59jvO<V@&6RF_CrL!4f!jjRS
zE=g!%6maYybmAd4`_%5X7+x~kIB6(wDT`C4c{IYzEf2fEhzbHY?dOd;ZR(vFbVJL}
z!2(LGw^oJW-ve)}oe7Qi8pQ-<m0clGVU?rv$-_e|*@?1rt{Ng4e3dGWxW{19s8xr*
z(@_(Cd9hC4P;p)#L<yl#SLD#16$RC?G}n@Wz3A9X(LRyHIQ!5XTCK&*u;PQHhI$@3
z-sF@eXI!?SY;6ZrCNBj;F}TpGjx$cYN=;)BXm8%K8(D#{voeV~;R-fmL!>5emP+3v
zHgCHKr^7B`Ig+(xpaWL1V*DwXUg$ySEO4SGNo7wsC#{NY*@@i7XjP`m=GH_T+HO;|
zTxQZchwvKh?ct;4mKZt@m5z?6%LEauoW&Co7l=YC4qdED(QHJgfwY%wI5{#Md6EEc
z5kgZ{7@=pLzH=S?$WN9r9>|f!XitomT*R`Ym+340S##4^_6wU9*j!R-4z@=Hl38kY
zREKp-m6ng{>SFC6$f6Bfg63D3l%k}uV1wR_oYV`}wChr&iNgskNro{luJH#QYQpML
zp${(?f~3h=6F2t8!+NEwf->V=EVB_XK1p&@>BFO%8bbnBvwzc|D9ZSE?{=o#6IMDz
z3Qnx4`L?i)7HpCBjmv|4gBXW$7CLF_YM7eqX?A6~GLgk$^&yy4n3fkD87G~dp4!5)
zlVGhqi!}D|`@sYq#zCi|64O-QDkC=<n4_s+Y&Kfg*!Ru!COu<v%(GBM%}NVUPAX&M
zu&4tW8Jh(cd9BxhQwX($0)#_hcx`G%K58})6zcg5RD8hbTP6mTM0v!X76-pzkjQ9q
z7Aj3byOTzoj)!PKoAb75@w=q4WV;j#1V~6k$DuuJ?#{qWys5%1@Pc>)o(t)*QHw?z
zOvxhwG)N^<f%Yan1nbi@qGLssQPT*pQ%EC<7#(SSh(|@CSViO2r1ueh@G4&E(ojow
zAc4Bg^EVoT%aW)90gQ_Zo!a;$!(%M2kdLWbMqC2|Z^?$5g5xoPwlxX6Sz%w`s3CZi
zS>*V~(PIci62cV%7wYJvtrn4V;-~8L!#C|X)YWyE#Cd^t3ZXRhxs6!Se|YtZ7%#2K
z7lWh&l(85RN;5%#QQ5jEIhYyMq=Mn8A>k%%(#k34=Xcp^i1#BPdjKe1KN2annj!j1
zLsj)*7+N2DF7iyAQDl24swW;gP54@^+jJu+u0pUL#q!y3cr<ka9Qln(^tJ@0Kwn_n
z)oCi0NkK@zlU8@;U%X_{_w*wru#}hz;vB3(6%YQ=V9lPzqXidee+W%Lv)53Gmgun6
zmrpm;Um<2Z8_&s0Q1<Q6JCTjP6DW}L#=vMcM5kF6X2gh`x?nG566McDcm*O_OPX+(
zhS&1L>s}wi+@->9jGn{!&&R+pEU6CqAaLG+<mpXcM!BZ502|R6Wt6q%gE)qu)a(7Y
zH4AX0PWfMa;kWp;>5#>OCZr^2GbM~I-7YwgZEE#()iAfQ?vQ)Uanz6yeE^MTNFl_w
zJnbq7K<^drAtinJ2QAw6V%Ef5AV)COFY<Jq6sE?kC><xj{aa`&6D*<1+v-U}%2;EK
z@GN{Zjf}R_>}XVlIeOs11B;ySkX1zLlg4VAAA?a{EAJF4T5ka3MM^cn<f1RUKuGK~
zgGQXyme~&moVY$8+9?@zTQxiwOeN8rV24)oZ8;FEkQJ?-kp^J*gYD;MjIs`N5~%`t
zx;|#qR;@}YxIWv!-@9pAHpQu4O$Gi=y8#G1^s38JRTRAHwIPHh=BdWFQ`SSCI)JPJ
z14vEHeVa+b+KLZP%O^cMa>a>C21GoDw(Y^BbhgifH$7?P{lcw@eWinlq^18(MN+Tw
zi9(CXQpKnRSono)8oUw8i2ldVv60V;F*+i+B(4|D8zBxl1*W0IEcK<8;tV<dh$1q6
zv{Sxbua!@1cm&3QHavjgaS^tKV-bfJ3DbAeA7}1=B&Ad;;Q&vc6OEsiW|~VSCTXqW
zsV-kURb8D4`7=(ekH*kp%Zm2<lPalL#K}ODmO4{ZDxe?NoDU>?fu^M`&|u+Dwc@lo
zAw!-g@J?(e?R7}ep`v`OI-^}%trDknp<2q*r5Ml25k-NxGEStM3NG7x6sN=(9@11{
z1~q*{sN<dl8k87^Il(*Cpk+Yi)TOr@8j-593!~6-j23SSnyT@l=t|90@YZ_2M@w9p
z07dmnpaG||M2%q$!O$xhwT!_)M@6in1elhVprb`9u~sIX>?5?Y(Ke9kz>`w&krSiH
zw7bwq6ht?Pb!rsk_QQG>yh7H3^59d)rCuYE;zAy)4n_dpxf*!pHN@i-ub`A^1r4-#
zC^`?JM)qTlw=vQhC3QFnQ}HpBN;#-)bi!zG5Ef|e6>#W0PJwpEWe(oS1W<myC3Sw%
z?61hGYeN8|jDm7cw>#9=Zo;bCQu2(gcZ)c+BSYEwG)VX(V7Z~VFyDvCIrXKUK7sIb
zrU-9px{OemsuV#rVpSxll`-zfIO>qrCu#yDo-m+7+CV3L;*{L_IE{D>58`TMczp~u
zb!q}>2z5oBMvXMSvH}Wf1fHpK(V7uNZHfd)k+uuIsjr@aGa4X9&ybAO_Xrl6v=Sl$
z9-z-_Q<*%@eI#Ju{ZMIJBmqAY$FWR&{{}*frwQBgh~u$5fbDnTaA{|zXrEq~x-6Da
zww8aK&i2UyK6LJ5kL{pZY3k(9)A!{Ij8;}_1)aDwD@>@<W`iFQY>k?1eUN4`w0(<q
zaB{X$RZb6ZS|0S`@C&8qfmc?20SHs*L#iI%elzt%TH<s@1>baVlLH=D<aqcQkouUB
z@S4KQuAvrQx@u4`8e4zbWNGkpZ_a{L4IruR1$zoO0p9fSqE3&n-qbPyyq+-nYjGW{
zjYqn)vN4-Y3*8X{xsk3<jHd{ZG6}G{)$I_8VpYG;oc+_u%+ywx)k2Pd<RYDI^(qm+
z$wg%SFD9`wagEC2CGa&lhLcq~fS)w#=&7=XD2BB9D6!S8U=r2ym3jlhC!l}s#25}X
ztZ?ck1?w%NVgY`tp}Q-b%Td;$wP2C4Dyf53tFnbov0<kXYt&_&njR7;jp_4vEvOqu
zC~egcr*&*jSR5p$e(0@QK%o;Ol5VFt3<j|hu{Z$ex|Oh~&DVVtPXa?=nWrDDu?7-E
z^s5-d*02T<-)k)$%kZcYgMOR=K>;~sWk4%6<G7x~xp|YiHR+}<iL7nSE=78c%1_(a
z6W?XR0`AF|5)sLzb(X;tVpXv67MgD9Xag5kU=oSlnL&lK;;OWf=4@~Q?J`3TXJUSY
z7d1(ZC1%uVZsNrw5$YOjXm(g>TZ$A>ToP^D<Z_CkTM6n-2h=QhHPsNwjAgP1Nywgw
z$gp}XZ{NEXAxH|56nQsNA%Wf~9xnyfoYbQ#Yp06eu|?*r)R?^$+LRTxQfl^OQB`Q`
zdz)>C9cFXZM1g5?vLh?ZPjpfgh~ri2jts6QetF$S8@9EwgV|)zR7|plgae-Gi+V^_
zqEayYFHvXBl$ubM293)_GcZAQO@eGkgoQYq67()(hF>tO9o;Yq+e#E@M_jNFwS{K(
z6m%tlHFY6JtT{^NGA>ihJ7JMnXwNpX8H?;)RHB|L$_AemBc~@}Cprl;E}CwnIbU#%
zY-$-Jw%tsioLrfGyUr{<4}E|$#Y<<^!ND*OV$^qSyu@Jxtsxp5HN+%aCpAIP2|-yh
zl?vHv&P#Fk$gYh>I=f&h`I*wPwtH7_d4zsq86dAjb-eO2F%roX$@C6G_C$^}w3Z4Z
zMPfO`)exz?NpDaXZ)&2`=2(#(Ez&0ATcTd{G@{u~79bfGm`u>2yYo>mJ80%GetRBV
zzJATR>ddP)>zSO>r|~VliRVn8a8Au;yL9;Gc-h)@4dcwRTlVF<|9Ij_o4>ts(s85b
z4VD*{?9Nw9CxxwpC&XJukG$`#J@-_XE_uy14jDOe%MpXe{OP<ucI;XE_h9#=PmSI+
zc;t{X-+89^iyyoryT%P3(^EHm$lMkCljje-S9F_)45=QvWl+4~p5<SdzOMNArmaIB
zKJpvUWhWfp`RA{#TmHlsw-#PHw?3Hj>Eq8le$plF|1tBiVD}00pS8!%|GdikIcn|b
zl?Pop^1RP}tMi;SXLZhA^Zu<5&);<0!_7b2aQ>uYKRAE!vA<lk!Txg91IcqM+Z&%c
zZ{e^5zr3$={V(rZzjEc}8&<A-Z^^6YzOnw*RWB@lZo{JZxee#FKKJIx_0PS%Xhq}Q
zD^Hkv_Ztn5uh?+hqbnEBc=~H&W<2-RFN}Wts}oxu|NLz&|MHWqbN}Th(-)n3{P*TP
zal-e`e0|Kq6|bMLZvAa*k015=g~tzke$^d^J-_Ow(>sq{{ZRF+=AA0<L>9rv6)ybN
z6lCrkH*J6CIn&l`zcl~Q?Z3}=z4fITBM<yTcI0zM%&YnBs(GiMIVo4WaNdMbZ@qBe
z83$gt?~5x}y?4gSRkwC7TeYF^r?Xcsdv4KJkG*EYSC78_?U99r?~R<@dDk1Q)w}1-
z_}R)2Mn1ao?ba{6f62(_K0Ni9$1lEZ>f`HgoBA(5X}$P2KiN9zu`!pOG;hXj3y=8P
zJDq>n@Xo^5&p3SK_y6&@`2F*LdF%VD{(N-jnM>KBTHUH=hc5pv`u%;r=A>7O^}8QE
z=Dp4rCcM{hc6d<FN%@1qrBkjOUDviX&WBAupPiT8lg?VyvucQ}UulnMpVT?MePwY(
z`{171eGBrVRunEi?iVZD2a>0w_sq_=UNiW%W6r$gsnNUtT5Wv(o^aWtx9wirF>dte
zt@+u5Pq}dRw8D}P&e`?Kn8ClfyS8D(IptB054(TxpZ~f2%sYN-8da_zj}ZBfmbmrK
zbETp4k@(Hsy%YBS{J4-hZuRDgZ;h&JyKdC)`4#ai67HT?+uU>VK_~UhX-h627bflV
zWXi+|t&_IYH77gklA6YqxnrK3R2jK;<$N)diU+lp_a3o(&sCFFoUvx|tA(XOM_t`9
zTbI@y(|g|U+lu36hr9lxcEWFV44Cx%{ri#!x98;_uFbXH@ta)dpbIbkY~k#>x|_4E
z_0F>^4Nn)M*16Nl4OP2`zEh6Xb44dtX?mq(YGdu<8=}n0Kkhcw+jl**_W8zA?}b}T
zrBXG#w}`{=!Fls<4I1s7EjzQ1%4g<XFN5YEUq3z^-xFW{P|qOynV+>3*OsU7TckBB
zw{#5L7ggsZH$T`p;k$ADd7E2D><k|{tT%e-uv?os?$a|TyJyys({>zxq-j5<b^0G$
zS4{oYuyA1Sh%nyWdUCX|7uhDLY|oTLmQUM$Xk0t@pCvQ5Ts7UL-L`vUqj7igL)}u@
zgtlP9<Letr(W9ODN22b!2j_N=+fg4Fk;9WEaeN*fX<MZ{T-NPs<{j~Zx@}Rht~)qc
zE_Ej*T|KeX&@u0QX#9@mOULgBY6se27GE2h5}EuI`sLPRx`(!Yib-Q!84%XHmO;^;
z9}LR&?$9$$e_%VlJ?v<iSZ5g&`8~OjUpOf(XZhYqzjg}cK8r4JS+uNqZq+7Pf!wi?
z<O;b{Bub93()u4<FHuY1$xDNUbk59~IN~B9Uve<5j{dbqm;eTmv~|gJ`senq@D63N
zjhe5NaQm1*;!j!0AH?WU3-61e&jmqm)`sEeNMH9xNt@)hHq*mzCtUQ*(}Q{fMmi^A
zKq9k5%v|g;Pi<_az+0^a;0|Gq8L(l4%=(yY7@-Z`itx1AqzJ#szl5fOU-4r7+@Cn<
z_}FH7QDIzh0RE$RrlX6ojMb_q?uXQSrO*})nutxT*kNKA2Z`=?>|L9N>zSwa+i)=m
zhdM6G@<SLhVU_P7IB>ex!HCw<u&*Gt)Fm0qJjPfy#52O+&c3#WM~&>#mSta!lk-@Q
z2_nElwjs|FY_uJ#wI5_Y%xh*EoXtd*nZjxj=V~-m{46oY0B^<lOeYOVXbCXVVGTA3
z&1diEpEL`G{QUnwY!B+@^EXm5uJd7Mn9By?InmhI<eS?IVY6e-7cW8QQC!<vTGL{)
zy~T1{Mo(WPyZs8ixuf&aZegwzMiX7<f@VGkg;pOND{C8SW4V@loSs^C-TpV;e%7CP
zy5ZEj>VLtRrwt!`?t@A1zdhu)E8pwVGfyk7J$1v~f4}IF7uMhRufI6w>33fJ+o>Bq
zct1Pf#g*TFaL$asANbSXPMz_=6O(2>yX?kS9-r~-fj|BG$_;=2^AR(jfAzX0PfUAa
z!)-s^Fyn8pPs+S|?v16#fAsj*zI)@!86U2ivE=y^u3No=dz}98;}u8z^QsvaJpSn$
z_h0g(M?X09{nwB9-KrTGinLeH5dG~u?(IAO$Kyw4n}^?A+uY)+ys%sy8f$wOG)|n~
z5-khOV4f=Tl&QL<FtbKnUhJ+C^Vwx_u#5G~uI^CgERU_NYm|j`vFt9Ohs?-$tBIHO
zj0@Lxt_<yW4~dswmL1KT<#1}04a;3K8<t;rWJCL|x;k@;gr&k#G1YC2M#e^F%Yf$6
zfJ0nvQ&!r~Kf1Ma_NR+&TAE&7?)N#kw%(}!e}k_^!T-kg`9Fzw|C2^5se+H6I=$I{
zVarFTu%GfHjIW7llMAVt9;^gLnDf=@*_?MS0q6KPzjC4WQ1w*h!9gN3nQ*mQ*ATi;
z@)EQ>JfNmi$Eh6cuyKx&33Xw0u-hXQlZAu1nJs#03pygE<B=SVVMwn*w@<B1yoGfl
zQ^0_mnR=>pLwdfb&M?EYv_a`w#*0?jskab?*3j1!dc%!OB4sz6!>U9bny*gkx^>od
zH?ek%hIQ<W#hQjVu;6Q?uDD$2D9aFPs}Ci>VI}O?X5^`W{GbU_0b6Hi9c_eOIlR{y
z4#^QR-ba&+<3gS`DpIZ#%ju7za3k9FT-peEaXc^J@r&az^1vNfY!sOtJ$Z|G;UH;K
zOxPe^uP6aHP3TgP!)fa5W-^k*^V@K_awrvk<seC^)^`ThIrahD=xbVqgI%;@u2eC^
zCEJu=%(lBAD(`FC0-KW<;m93~B;eMJZuZYCbWGw|RQdgWe#sjJL9LUzkn|!N#U|N_
z28rpQ^!mw)-(urc9IOpz26d&_9djf?It=HYf}pt#0RpEvCT|)mzy%_}A9oN<Hyg^*
z)Is80Weaz!38dL)f32HM{Ps<ti40{R_BHPg6HaEr$`rk{;<8Di_3@BbG!e~LNDO$X
zT+$)&PJFG5T-whj<*sN`Ta68E-<3n$&S7fl)(zxtKFLc(nYU3jyq<JX;`L{-oJ3c2
zSu07=B6(OannHch!*YyJDM^qWErG52{cIR^I~Jslq01Kno)k{Pk4%vZYh-wMh|d+Q
ztE(^99Oy~jD6Nm73*f1ddJUga6jrMSw)k~qF(z~+60WO6*MRZw8^SVyK$~I72_!+Y
z90~`QMc+kkKPH6`gT|$AH5E>zE}44V6&u<}uA<6XhHVwmpU25#8}zSZXu@a9$tPhx
zm_kHUf~{ioOLxZL^#dBy3`?dA_bON@+JY8BoJy{{x#^E-3@F86v|FL2_t0TLVia5C
zDMz3K7ZK+00@x~Eywp9FVSMrpo$_!LHfS<NuxS&+FI;R|mq@OT082#{(;EeS4TIY}
zlpbhheXnu>9;J0nI|t3KR;6$`A-=v!mMJ4U#FpR5*s9YQ72|c`b=K&4SRr*}#KxZ(
zJ&*IFbHzg>rsPyTstju_nS;dfZ*jC&5iznsv_*@@Q9fSFkoIlmz!`zGC7F77lR@;)
z<5d56J$=}w%!ReKG2*VG>q#g(qH1XY>UP@poPo$X#raMz&#X+N1`=8<F+9GNV_Qf8
z;`KVD(RY@phg)g(b&Ivg4iu2S!5Yy!UR2rq&O`FGxD^GBfBCywyCbRgZIm0NiAI8e
zgR{g_U|OikH{PRuJd`vXTM`=>%^Fh}0%9hzkkal{$A9Gglc`HAEM45}Y$GQJIo{9-
zA#YqAnPYZKk3uSRHnY1mO=?Zt?qBYi$R3BEy65$yr%g%GD0>=T>?ky+j7$*cK&c9R
z9o8J+i}tu4r>>HI7Rn(O?XMd_j5b}MCzP5l`evyT$hyIHtJaaQx6bbCS%`kA28JLQ
zJL8%Q$Tof`UZdRL$DkGxL7Y~#C@_k15{wGkMca-<bXUBErdVM?hQ~7oqt^_&?lQ8`
zK!QJyj6uESM}1+ZA{Ys=a!!Tu=R_i!i?I=@TNMSSJ@s?2`N2Rp)%G=!Jq#}t$%BRF
zsR(4shD-Bu(p?o7)ijWLqcx;CB`59BCILExB^ziqEOoQB&rd}%!j5*}X0?^=7G5)P
zN-8hi%nwkP<J8Yy;YM(>Ng@UjdV3_;5_a?=3kup9UinW2iRxq9*<E#EE^KOHU$~cR
zxlA)cHq_V20vOdEW~btHH%VBnv5x8<A_Mg^l<8acNBIgz+;n~-5m{}PvcC4A#qi5P
z>T3{i2(?=^(nz83T8*)zHISdRS@xO0CS*IL4ke~DZyTYrrD%5~RTCuNu=1b#h{9jK
z*ILa35dbw4f5s&Bi<m$c3=(7`O2R|vCmWC{m{2<bEmv!Z65wPY!4aZk6rtd+Zj-UN
z3OrTkI2)$*whwH-gF^A~@w<rV&c}DGR8%k(2)E;{h7p|rHLHP3B?dGqs<Y~j7*9Na
zByf+$)D**5T^?))QC)LNuU|0Ym#89{G|;FOST)5{l)MW!R|soDu-8O2aec(-<L_~r
zs_nCHt9u`H!K+6bW-*&4ZM?M70~wjZ<2#&@&V-(mrWY~Qly6w-oMy3`(?Et%hcs@2
zA;6qRc4~ja#36(M5nC*;sOcw^ofT6-A|+K41;4Vygpp64%FxuV6eO0>aM<XO2O?|r
zC<uOsQj|0GOLM6$PW#G;AlL{+-{aXADSDqmUfCHMhz6>m$Evt9FRJyjK%-m`D$aW$
zl%h>z65kGZM!i)v40;K?YOoaa%oD-@>aU}R)mDhpAfMw8w3nU9lhr=FAtNP%6$cC7
z3;VK<3>fIixVkzeRKMm<v8k;tE&3))9|6ws&@3@kMcxZz>+qty3jL_hMNb++og&p0
z2xQarZ&r(VoT0Kx>S{2|(mqC2pC$#@AG<}XXg_RI2fY}P0VB~ho;-xOLz}!&UVsnA
zw${*vOWu+m;Pf2MU9YKz`=K{N2K8DVho%FAgW8P1@TcA=7#{0M)R&4%8bo!_X(1Vi
zLroYQEe9MK$ATyd9>gkXGO1i#t|lEy=Xk6TO{Cj;%SXo>33XkJ^Ho{H6&!dK)e%4L
z&ZHeb448rN6uiq1(*?W=r8J)|mu9eU;+Q7nJcaP$)7d^JY$fxNr%x^TQ!XlvFH4mf
zP+ivQ*^xkfSj{we@6ucvB{H_ZAUqy}-n^>G@ZyL1jKk;Nc`|(gf!}IA8B#Eecj8DP
z=Pj$IZ@z|krh4eJ8YObtbO4W1zAb5&7m8HGT<OC;4mWi=Y+4Yk(E20wYB=<WWBPNg
zC^Ba-QhLG}aeP#D5uh03J`us;SMok0ZC605#=v6{(rF@M=}kPC!*5jEuTHf)bLyd8
zdze5H9+1rP^;lZF?Zf;}%lBO>UZM>6*E9;=>@x^cs7e{ryHmNCx5NBnk-JjG^sVcd
zfiR5qOQCdtu~Z)f2`!m2ARG^-Rnv&4_HJBJHciZGZ=|)lqC_mX%B@im{pO7KqD(J^
z#<zW#4o51!6LpH|`)*AJr&d<x9?Cfm3<zc#mYBJ;gI0{6h^fQ!cu-wFw%0pNib>7L
z&@sbLvr6mh02??T%^<#W7DOLZ5ih`9);dHSg+AqJc{=BD7<foc1C3gK;-D#LIAaL&
zKJ62nt3y7UmIHhYsagw3S{pnwxGF+T&k>T3Av7PmEl#JMUSF|R)z)2PKx3-hfKvu4
zb12yarvj9L#dPY4!m=t;$-Up=0Q?jqbz-V6H=mA!A<HWJl)KYB0Qii<lRCX!hDgLx
z|A?Ya;}xfIRqx#n+i7f#i#r|V)ZwA8c|;KT-ZWqnMTOE04Bu9CrR_lUfzzQO70XgB
ze5+7;pLGH(SHo&jh#z@MgNIpxDzGn0mQYa@sUopH2J0ki@REb_$5>phZ-n(uAHwTi
zY|DR|U5`vzYCbjhs>|cP)}KTsDtNiH^>#UeOR3Dx;7*<1krGkw4Y>*sUapDV9?hcF
zaHmF}d3n`)gw>a(2Z>O|1kO+KYU1yc098?~d}Xi(8LP@W>h97RA2FpHB#~X3j(01@
zA)9L1PgL-H0?O+4*>`?~#c#l<T2Z(EsY@u<S@kw6Bd20U>P289&N5*5_{MK@D8Dqa
zwB(ftk9K`fs!-qgw={Bpt5yoY2!VQrBz3180;)-o=uX3Z64rb02GAjcf&EoD`=R6=
z)`}y7O411tG?BAv`w0EgS?B$cO?i6$U=%_gKS}wx#(*gJFn%v#ecIOG_w2Ee$74C$
zfKP!9l!QC9B2VEIV-tN1gWowXgQs-93$@~WA@gpEpx9ZZ?*mv9nnF=6G~&~?=?vo&
zXUFv3N`h67xBK7L8I5TWEz*c-i<7Pt)s&(z)15z2c>>3LomxuQ$L%YMLND}*Z04t|
zFqIA&WQhj)sa5%-@xf{~tdauy<v5&9n}PEKx(j`qO@oz$5>|H9B47D%^=kYS=!PY6
zxGz(N%1C`%9etFKq&O7>1H~A1S?^buaw&U9phOW&AXnWQb@<%lCqTh?`Vh(}_-F;G
z^jm+c!Cvn~gN#*Twoj3&=SaH%fEBs7;X?u_4RFf4Pg0NQPYohOA|ws8eSuDG)8Es3
znP6lU8>msn-9L7zA7Mz}^GMl=rO&nOzXnq2<6S0rkf(Lzjj)e_kdjmWTgW!hgWIY@
z#Rfbw&51H|it7uKxSG~M#VHsR3r+vHphEORCS~Mxthk&S7Jde<*z~beME;vQuK_Ev
z?<TU#?-Y_Q{6?m*t?TO<n;&F%X)ez;`OT&%`B{WdE$f>$Db*CBTI8>0ZChm@dKzAg
zs^Jz%UP8yl!N6)C<dO;oIZMKFZ$ceMVNtjZD=0(;4J73#%9AKt@X>i*Bjs!nIX4cl
zu6Oq}lr<uEqZ59Rzf9l<v)xq$(B73*U6dRXcUnRTGOe=3y1Gym>E0wO<$^{Cb-hY4
z)^=49rGs@d$=RX=IdKklQYD74kzQg$PH%9oazVF&q1Jj=;w4Fu@FlIfSam^3+NbUy
z4ydfK@9FPx8gdfeo|0JUEg)A{A<6WTh5<X4nO9H{ss{_bZkZXxWC68OV4Ckdk_+iK
zcNKE`SlgO{m8ug9W6Aw%Pn<8g$Z75aE6L5$lj~rNe~@o8DLU$Ox{BT{#h#?63#z2s
zmJocbY}q+7z)`(b0GfPZXty{kQCW|tOBA_$T-2}OY_Ypg!UCSIfDh)$);-&ie^bDR
z|E}3olI;z}mnE`4gGqOzIO!aI(j+InVWAf#Mda5x<WFkja@R>!URm?&RD<@X#*x@4
zu9%)Joi>pYwJU%vA-k+4jLK|Q^Ky$f3_Ya=VMDE&>Fnf<kiERaoZUuh(M_F651l}F
zMfhIa!eh={vTjf3#u`17(>f!${+?0O;#cFHn|tSP-rRe`@WIK9=jPpf=gy7Wu6k&r
zeDm9lEjJv~_*P}#L;Lpa+!$~9-QeeLXukceYaV*=&6^&2$X!u?)-SGDJov!wJxhN7
z&O<ZHb>S&b-jE-1=Jk74yC3XX^0P~4o>IQ?lvCDkeQNc8pSgea!w+{wPi}Oz*FLv=
z;o6>c#XmgKRr};OH`T7cf9<*xcD+-4G{-$o5B;U1^@@8A-2a2=>+V_n>x<tR^~!Dg
zN4;{t%6semSO55_Q5W5D=BR1kxPS3qFW&#b5AN7;;|<^W!Hpk0_Q3r^?|=LD|9a`w
z2lk%DbIMyEly86Iz}rI(T>h(P4_xt&tKPo-<a?tB?ycMZ%h{*C^~-Tzd*i^vW7fW~
zbl7v(?mY9kYhOM!df;1=?!4mHBi_I9H}Sjw{F}r7@<RUj1D9qN{PxA3F%LhxeZUW{
z`1QfR{@eGCdH<&`t$+Q;FCFpzrFSl9F7xfW$FE%f!sEXhyZ3KjI{u!;zgzguf|u{x
zcjn9qD(`&{40Q`f{lFb)x%)e}&HLTL)f?`<v~uH&%YSgk4KF|Nz||YyKH^I~$a=|J
z5A0p_)(0&c-#GAx3F`;{`po-p_{(c|-*NJu@{D`WyMNyBqYgZL_pCo2m^FR>;x)%V
zSJyq{7vFw)Zgk(bmj3q@L!<XMf8p$R#~f@fd}01k?>+pN;%}dQt#1D3dxrmD@agu$
zzm6aB{=b*%?>*t{WB&f|OU2QTh}`%@hk4<N2QU8M%in9?@%q(0+s{Akd``a|t7nTA
zjXHhn!s~Z_y>-hgx9+&@>fO24`Src6W0T%dlYe~qsMBx!{Z+G1dv)s@+uz!9#aGuh
zUUl;B>Gp)(TbCcU<*D5#yuJ6F#~L4Ko?W_r->0%YI}h7^+smg;e<o;pa`BW=*Zh3s
z35~yhdF8)eos6jcmwao}^-B-_$+wpr{iko%PaVAR`liLdeXi-%7m5e}X6};YSJfSp
zuDoXZ;otxEWozjh+EuPk@hrGz$=BlY&aOLe>%RS_*TdV}&wukc7iE%$QF|-TjN1F%
zh1a}XS$q8(Ti1@_C28wbSxzDy``kj?dduE(GRXbaS9`8_bXlX##qFhuJ=3da_Ovc<
zEYH4b;+FGF+m>mrp)_h~sVQztj&2w~`JF{`j=pBmeMg)$`<mpf&m_rBW0IEI5#g}s
zlU(b)qra4FA9z{v^P1<9vESo;eX^wa47=p{-xRiAXE+MBEZ@~Yt2278NG6qLxJjio
zYg=xbpNp!C%BFT}lzn92ljH38>bU%<{XKh@za@LVXrUBW8P(i<`j3X!H7$LzacQpV
zULL-@XX{Uv$KU?twb?Ho{@Wc7{iL$-$=j9>c<YL~_|?sWuP+?D@EeZ}Sr|NaV)KA~
z1DZGQxkfGvAL6pp6N^%PWTCU09^2eCePhjoOFPZJFLhR`^~lFKLkEs*qu;?Xqc~@E
zWb3C!fy?IIBFS#*a^v##*Nn4=yBWpW)l!WkSLvXenIh(qtA=-<zT-)^E!@?(Z69(c
z?e3UNgXxek_r?E*w0Dn_tEd)#*WR;d=$Q<#XEMYg=3sSa2+c$2gcze>sOdDJiBX!6
z!-=4>Gsy`75r>c)Q83g@1{jnhO^h1FE1ifCA3q%eC;9^qbRJ-M9S7v+4?G?jAo3D1
zLJo$9;rCs&djj6`x%Z#DW_DGrRjXF5TJ_wutM`sOTY7IZYaiQ)Ue~o`b`Iq;-7S@W
z`Qypx6?Hb%!xc@BRpsC<g^KI1cgyHtCD>8eaeeUqa?Npc*JY)3-E`G$(RPu)v2U?<
zf-N%iy<x?!jOD3I8G^saIN#1fbON+y;Q-W-R1Rjdy(JcVh!vy5>Lf&T5@syl!#Cn`
ztt=|Oy1w0RlqmUw>q<uI(swuQ>K+;DdqLXAe#V^ruU3+`%QE(JZWs!gXzah7m=lnH
ztIdp2!|n=+%(KL8LUvaC(+M}5k+)MMIh}Za=IKPgW)=OFWx_Z<7RgvEGDxDE&bEbt
z`!MLpWq(&jn`6H;&8_E0qVQOz7@3K0L~iRL4{9jC5mAhYmJ>HIRZut*S?qi#-^j~`
zbxeaJJcD2++=D2+YVc;>PuY+od!^X@b#^m8L>MsYATz<MiJo~n<9sENQ=16_TO<D@
zvQir4xYbpT`3Hftl{z!GVMec^0yC6!I?`A!^r;W&BhZN3ZHUf4W6IR4FdAX&6rNDY
zP9>3~7^`39aGWm;&&KM#kS(YFq>cx#<wYpWafberA+=GW2R-w2)c+XA-tl)0tKKde
zrx+R%tNOz_+c&dr=HA>?siRIChgT<#&u1;@ijz?klwgJ-O&qlkmlyFQ(6vvLl7!h7
zT4EOud`ix-9NMK~uhTP6lUYZX=r&uQ*!`=m=Y4+L<0s#^=cP9ue0wYJaoYN&E%!e(
z>&d^ob>{{9?|$O=TYvM?D^KnE;Ens<`Zi~t9-j8hZ{K?5`@3#=ec!5Yp7Hiy|MS*o
zo_uM`Q=hu~&A0a6__;Z+J-mG5lY4J}=3(&vy65FJKf8a{lK<TM>XKjG{l_({ZhC9Z
zHy)mI$?JP>PafX-!j-Sxbn&PE<5#nK|ML#MUAO=KHTT@K?2KPOe0%HtKe?&@in~u=
zv-&@GpW!wL_K+bxL-gL?W0}QLEX2i96gQPz6l|}~kZ=VHrlB|}4n<3LI44tg#^I&~
z?eAGuT_5&+ha+kAD39S=YE<g?K6c&U$|af3q>{;+uHh)#wLW*l?q%WN&D~+L-hJ<q
z^}kK}zn_u5676<M^_FbZG}YFf%q9D<t1}np+pK)`+MsvCko0btWNgBH6sIC-ZnCY?
zMSGx{6;$6Zz3zjme+q6qpuV;p9aa_IVNpzDbo;<r#Q;NV>(D?Hs_UWVb22`BptYn?
z-fifSO3S_z@s0#fYac#HTyLhXXH4X4bf~y9iZ)Z8$ON)Z+k7cOm5yclXw0wDq}OHE
zn?YJQt#Q!V(`$NPXf5flW}`O4hctrTV#NjGyyk^W<|w)aEmkt^&U9KQ?M>QC24U#E
zs$S)RQZ!^kFvo(o7R8)lgJh-P7)V*ib6$u?_ecY)9ZSlHPQ{mf#8Dp{^XKh+3@sHW
zU5v4G7SstXHx(I|xWPzBcLP10Evy_H0Cf6XI1so3D@q~LD6sHHrH$}qX6oLf<%7qB
zvy$-h5f_<?A?lMBQ#hW>#=UVzi<+Xh7<KcE3D%ST!YIHY5VEA{*`Vx<R-qHrQm~xV
zlnqhPV;JJawLL%)c&r_po+xoUeXT;6ZX|Gmp8gj?!)iO50UHVRCqc{y=oA(8zJs8Z
z032X!8N`wZf$WwzjnA|tpky9aOynF)Sc7CdZ9$Q^yVV(p3Z_#Qh3L7M@q+0kAQ5sR
zo|MG%O}ekTwky)43QfA1Xv&loaGBzu=3xx`0daz06bRT)s52rPo~5a}sw7{FTYyl&
z+qFQ;=GKWv6IPYs{kPT`p>6Q^u**vK11&Nnyn>hX)7Nlg;fE=0d*p=}s+fQVLoq@*
zc(Uri45}dyyojH&Som6`L!9;<{~m2)Bv;7Hrl20mq~jJzHw)_i30vaoyJSNk*U<U^
z+CoYF+zregPH|VV187<yk4UX9`J7k~M|%V-qDRoDbpNo)NjMxE)i^8<Vm6gZ0k}u&
zu*Q^!2u=$N5FJk&DI?&t6x<#~>S~QBXdBIFAw+5#K`slN`qmcp7;uPrB!Jh3dRFB1
zl|=C?8g-NjQwNgkMKwhwGN##gPC`7^SJDmY7$Zid-yHhJBQ>8o6Cp=|XlmBCqw*M%
z!e+Ep7IN2&h(-;EW4Np%RIc&xi+(R40mFr}!~iX<Ym5&$gB>)KFRDv&B*V{V1g*oT
zGaGiZ4IRK4F*QqM=<C;V2Fgfhf>^4l1zsx|@-c8=2X#}`Qi%cWNq0$FDX|V0DBS8g
zoHBuRWGrni>RSO?(E>4p^SML>wa^87+jOF*k_B^{&57Fhf*G({P2FsRL5WW#sCZOE
zgJ6&&s9psl#@FHk6{f%k=hgFdrmfp!XyBA;RD$I)wJ}h|61*nmN3>*p1#QfGL`G$b
zB}oNL(p?HLr<~48Tt+B{(G0k!p5~dTm7;`4)3L3{GL{j_Od<~!m&=hL^3@!IgD4$Y
z9*V7I&>sw9SB{uSn`t&ZB)}R-hLp+C+R4@V-06KOAgJP4S6SaqjS`c_i8L!Nsi8&<
zVfwfOe88!Vzk3y2wJ?$BNK~*DOJ<^zfT8aP1Jg&)5WEJRgv|>iijA0rFclq{BSS+|
zky=2TMMu|zN(R=71VtkmGhk3krf_9yp+<<2DK1E2swyx}MwU5e<2GxFbHs+0c1%N|
zHe%=M_&rP7wN+%gN6FW;7|&;{f4537WQeM#yF_MoH(wvEdNEYzaCul{KwsYG5*^6M
z*di{H9jYm-9mkjxvb^SHaF$lxk!4(VnP4q(Vh(Rlp30*%2`vlS!?bbOfJt&V<m5$o
zN!HTn9ET5JUhy9V-(d<-W<+a~wKe9GUN1<`Jk>BINL@OT0e{>{r?OnF5Bqcq?^+}>
za4nYJ0+*pv>bd@7B1tMnXLL(STV#<+o&mjONCtaN!fBgjA;zkfeAQZK%hsWeu_jut
zJ6wq%xL~Lb6y=LH5jG{jVp)2ruW91U$L#<_=`v1iFZoCy;@}8+vP`eeB94;PqZv`P
zPRNEsEhdN~?wtxUFK{w!wP3~0n}t~=p|d!{|9}*;f$Qd68mnonwl*4;b;4WyWvQVB
zZ|4q-Y;w(X)HrT;&YvOq-sj1njc)FckpiW|>SXI(d~NWwFKdiepw^{@3dt*u>&XV<
z0nic~eraM-N|bukEF)SfHiQGLF^;LNwA7ZXp$KeUnjYU&iLlHg#A^5EpL4N>YAF&z
zAJxTWHB7F9J`Ex1Q-X6oT1t=!roieZ3RAi=8lD~tr)eokk7wv;@R8%%MldDuF;bWt
zq{$k}raEc4yf%DxntTtrt-%vz_1*CxL4%;>G>!K(d6Kc}X<yMEl1(rR6moXDoy^E!
zu|4TY<SpO`k82==X%Gqp3G3PlHEe~NZ>X7}S7ZXCwiCx4pik<Y167r*&({m~4Cs~+
zke$w_5aYR&q88M-HPWyf*Tq??(1y+wpqfx>T9rUKFGPiex}~?K!$!c8%t~OzYP^S>
zgah>2PO^7m)o!I@G{X5<)H9*4H&w4@l<1XW#PEn(Ev=TcZ4lp}V-x2<0qb2+O@LbK
z;#7R|U`nW4pT^daWt7_~9mk}ZnOJtEX`ulnE^UqtaH*eq^F0zFB^uTslRL(VO)udV
z9h@x|>}k|XS`@8x(Hb-iC$I@`i^51GBkZ(*3KgYGfB@}1)@$k`qCu-keO8*trYJJo
zAaWOv<Ig;uq4(qd%$7}%s$!EmKO@6`r!W#a#z~#yNN229g2~XPsv2c=sYb^6TM@Xz
z2tKR%0G3Ppl|pATddJ4E^J?Ip947~=t|_wCLLcI?l)=YiC7}h>Sz?9;S<o#cmo>gX
zgabrs0_6{UWS*@LCX54v4TTrf3o|e>kYnJ`L4#k@1++(^opfRkZH;LI@*PGwLT?iC
zAD2faMUBYmB7Cu)d3tP*XEeA7RnOu#K+UE7JB5Z_R8`Xmn>2|}p?U#?tq&-R^Aa0s
zjVos(V)Rm_wP#zSxZXIVNlln0)9z*=s!V{H0R9l69yDz#B^`U21-0$*4;Xc9U~tF5
z5s1mk%OKk{Zy&3-2_B5L&J;YwH)Hf#meL3zRUN|>)Nokod8(dw_|7Gsfa5ou6hTFY
zBQ-86+rni?Ib;#<EJUxc883(4$C#QYTNvq3PP7uNCkcL5JD>5W(<YwUfScfP;PDa_
zL0WR~HR5H{5`4+5$^%pv@0X;@NkA~tHY(Qocq?e9)B|7+gfvj&DpPdh-YF}CyM)jc
zY=TS!?i6!63H!Fx7F&q^C2<--yS0JAM^~@bpq1&M;tI(()DP*gIz%DD&#x($+S;e_
zsr)afisVVD<7P^hXtAB*nk<DTJTht9sHo9<aXibf?Hp|lU%{8x!DiSbC0fT0vL<Bw
zYzVmlq59tOX^7`sy=G?Ah`mH^Nu!-5JWT?FCq|T;4GF9KfCD!o+X&Ku4?w_+Sbe<Z
zp}9R!2CLjT+tAaOO(_R(pFRL*v~-H3zivU%SS%>T*9#MQFsY}uoN$c~D+3mdhJ3RL
zCA1>8s+tTLf*NQ*5#QHm1E=#EAGFGbL&C<Llk>^gpYfWGH^>Stf>nyw31;I{;6#l!
ztGPO*LWm5YbO#Q2H7x<XhzGYU!F62lRp(1foF-~O<m`AbP4BQ8B$66ds+J^-&L)jh
zPNz--Dxpa&1Fp@e%H`!b2?!ELH?@TPnWti(h79ucqB)?L$CV8da6lQq)$Xg_I0+4_
zCgtUJ#g|A!VWh4TtDX;AFT{Z=?*YXKdq5FC_E_uVbr2wTZ#yp=jR%lsFsH}URPT~w
zJtaQd%Xjd&8k9~<p!`LLgN!H@pDF=KRWrmi^zr!(>zoBaY2)>7oDVTBSf~h93B$ZM
zlR%D3h4ke0)0uik#11IQSu4%hz-Q8{6o3qk`YsadM<Yc5ogsnLZrmGL5W_XZ)ksn@
z1XA1+y(k>OrKt%u`&6m4noIL0*?1KyJ3nMgp{L<@rM?|PbF1Od=g1i7*C1&uan9=G
z6PavEu?S-&4zGsPL$=N;U^A3p0}VHp$wnz!2V~(;(hv{smtMYV8cr&Q7-9OC(88et
zJ*e5832^IItDV32CPBj`&fyps9j+xj#AO|hrUxR11s~zDRHXJKg@|$tN#y6El1saU
z(hXPOJ$C*HJHo~`8b-rc`OQS-h*So}8}=k@WWA>tTrbLLz^J33>Uz)TQg7(jQ8y5+
zvIS1%g`f(~yWSZmfyBn*B7r`Oo3?~ZL5T`*hWfjvcfi1H6;)zJ?Re)pLem|NX$f*(
z7-26BPsh6ykTo8zYJ@W-jX;iV!gr0#l?zrGgk;2sC9HVbg$Sg;UNcEm5HOH>Nb;;P
z{MHcf8gxxx@!>#S<CM{OeJpr#0}jv?F$gK|)gDdrReaF-;zmkVJS~Wqr2|<_Nfx;{
z3FR4A6;e8<O(W0%1Ahaw)EXaXIz+lmRDc3F@^e0rQkwP5(_8%J+v#uqxTmzH6k21^
z(`p|ou~u_Z$YiZ1(tga`6nEu+Bss~K`FXC(MrWlWUAGarm)3)xdEJ+@YDb<uggin_
zYQh;EiDweexn`o+>|(&GT8U;_UWR1CYA+e}5Ffh2?8Jl>9U_~JbTvgP$QA;_X0er>
zQAsi@OrR^9iWv)?TC3AI<JiCXm;@^OAu=yi>bmA=+69i`LT?^x`6@7d|9Oep)Vh{c
zZkq&#15Punv=zvyZkVM%EFHN*owJ7^RPZocr85q*9a<(+L>v!OX7ps_io?xB-ARZJ
z7Yd}d{MXHJz%|UxPb|xpI5`HLhiDbnIx}soE;+}O@m^`~%Z4G=6jK*%at4Ei(Lp8K
zHYjGyfLm=hHaBUZFl9UKP;EU2S(#iVE6Ut?Ci!+c$-l_cBkRJ#I%`@IVYS0EKP_*p
zwzR^QvUDbr<7FmNS}12`hM*@-wp8$ENoaRS=IX$j&Vmsr^7N)6eai)de=#zXadqb=
zBU+hPuNCR%9&Iu2#m&-Mt5L7?UCiFmgd{MDkxrUJy`>apXmL3Tq>G2ALo88{cn0?x
zhMM7qup<j?T_W-M$c+0WKAK(nL4qB<CJav`F<bkCc|CLUHA-OPAb>9QsWWcfb<E2B
z=OoKtu0ON<nz5$kYrE&ndaE{V(v@Skwp=sTv+S3nN36Pg=)<eGjx9O+nrD_iyCZYZ
zq(XPgte@?9>b~!7FFdzYj(X1od&I0y?=3w0%hAG?J~#E2kMC;A9s1JBr<bmJddt%K
z+NlSPwN0D4Z~oT)W!*FS##+LIYE9um%kp<FJ?_jI$uH-wJ*s}trlXRsJ3o{B!(A(r
z;A?Zo)~-Em#e42rsrvrNviSVk+Jj{BNuS?!?D2=__4xM=Sv~r_d29B4WX_HIK61o+
z>$iUV&-Gi+K5x&Qi`VR(bMbq2pL_Oc=G^6<e|h=GM_ych{PgFaJEH0N=O(@9z7Nj1
zeESFIoV(}vHK*)7e)*M^6MuVd<-`Zt#xA|{gk_g5JYi(%NuS@d<fQZW6{nr`c=5Y)
zhmP2CW$lQ`Q^$_o^xpchg9rWl#P?kJr-|=b{fCKLPuV^3&ZF!<Jo8@r53f#q{u@6%
z_N8mSa+K=3;8wPBzV*TP*1t8i>HZ1Jr<IRQdVc#%xMK8~L+;!6kr~(SJ7v<fW7o9A
zV^_6ZGcu=h;;JK-oxJSaiw_&SeDYa;KEHO`i|5Z9+4o$_Vf&t&+;raur=Gd}10Oth
zWX`<P?wIq%3n~*wyGJLkoS(m>^VpXzX*+uFQzx$4^UR6o@0))_@9c6*@6AVacaI&B
zn>Tjs;CZ``-O&5eSslm!`K*aY{b5r0!QJmU?nwI&M;@MZ-8%94Z+_*3AAh|yt7nJK
zW+i^_wNoe5Z)}ctojC9M4Kp%_R%d)@naFt;uQ0RT$G09&c45%%CZ6%#vD(>(EZZ1I
zJyUISGVSAs{rmCDr#^6Dl70T-Ont>M7k_i!eXDcDs|y#_d*tk$(|&TEYijvuJjq@%
zI!6xPdGWs=luQi|>R(xyv}a{}ft&j6FSz9Pqw3ik4j*eed5H^Vo#Nubsk@{6F{Ohy
zAH|PWPq0m2>y(z@7&c*YrsJ05N6kN;!`5^~^}g;%dTe;`M0;Wo51*I`9?zAs%Yu)0
zB*w<iw_Mh}Id{c-pTDr@oB3m8fE8W5d!YTpZrYE7ojo@A_d_!Bz{igZM^ApJxbq^L
znRnj?6JEW>R9Ei1z)Y=tL9*qfI`g<M)&tWr)|6jtn!2MxrR}g%``}C|4^J6Oz9nPX
zZ_P2ySNB+6lwRwQ?9S$6j@ENSZZ7?c$62=dnr@lC`aCl{?_bUE&{e|5W~F12-Q3x7
z(dIb%M|;@bgQC9WpBZbK_hdaNom-jy-MRU~r2O|~`J{WLG_908w5gU`{@#2z>7Etg
zq@QFu*XP{aX%m-CSpLn@gr0dWyzU$)n<kkVE02&9x6G>-zcbOvIUmY*wH%i3>RDH7
zntgjR>4)b$FX3;W55l&39A5b4Cqy1^`t*s9PdxE>d)VOBX0yySn{9}0SE=rsW9i%+
zyZLtdY`wB$O_rVN`p4txg;LznJ?;CF)b5qBcxPX7$WUK?9(#<;N>xVg?&C6@-P0n@
z%0v^!VwX#n)pCqkGt5=|yt&oQH4(=^n^$y2Q@N(QpcdD{laJgb_8)gi@`TIGzRktv
z`VCF-iVaPS&&~OE6D5a9kL(k(tD<L~{&6;1nz+Ej?>tY+8Gi@2SQ%a{k^aiO+gkZ{
zALC-JW;TOQzC^-rS6J=jjr@G44ZC@(#kUz}zicTbn*#X_@XqE}35=(0RWbWS!p8^n
z3sP1VlTq1OS#dgZ(h3RM3`db>8-C#|hp$*<dF>64Lg2~Br#q<Yj)%F2;EP|G1u=S*
zk$V}fpz>G|mS9+EhF1ZM@YTTnh#8F6Frk07Kw%PeF+4)=h95pxA#H#~D{Sg2t;zuJ
zbbm=Qw?*LAABobvH?&T#d`)Y>!w_?@wO4TlwkrPq${6MjqS{HDSuc|8JQP<<34sxh
zvFiAKmErIMJ@e%Fr5mfUxK2n{DL}78KC?Pu%RiW<<S=9{xFk$TJ_1qLP;b5pl)=c&
z;6>!ZYDiFH6i)~qDZx%?abU&uBfw<+TF=e4Q3ZMdVVjpopk;FQfBhN{<zc&kSG6P_
zYdCu5>AwL}roEcO(afnnE@ykk`ubUanVvAplNDRKM$ROkUe-{?g?4%-uJAMsWrMzg
z2@7#4uP3!ex?L{lHk{PXMct~eP2BJW7rpl6eq=1rGf(%N!WwVO8T+4o{n_ik_PJTx
zo|yLJ9^T`$|FySQU-Rhawzlq?cGI5Sx1YCv|J&0}d-UShHtss=rhU6_KjZG#9z1@>
zZ?D+;hh5X21Ya}fl?PAw-jf&qe%lMP-hOL0->!S*{y9tDTz=z@&(3-Bt>rhZ`SdHN
z-<^Hp*&CPqdDeq#&cAW_p^u(7XZq{s-<W*%_6M(A{={>K-hSSk;PoSU&(o_9t~um(
zkyk%;`_V7(o~J8rKX<=Ol{xiX)Q`?q&k$`laa1=wlU&a%C)0{HZjr9~EvCz6mS=9J
zGrN|au+I9)7WuG3G$~(bnJ4vacA&n(M7C#IUlLA}dagK7H<@gI7`10)T8Eh$2Fv=o
zqgvQ5Nqa8N%-__pGsy>I(jAm1@-(68n9v6KsY!607`D|+bFQ@(n8PfeVff?o^rXX&
z4R#J>KbY`%4m}Tm>N^frEJ2r|)P}Yyarv~4Q|f<n-G8GTAkd!vUjT{PDWXQS#cqut
ztuT<Yo(0oL%^%1}TW|UqNs0WKr%qX0Z%>-F!AjfEB+GHGmax<@66g`AL8&}GBP5x1
z61B8NBm8h|#JH9q<TPv~k>j&U%Sx;(CDR(svwB}(of`~$j1k=@bF!FQ0HVn~%vlL%
z4CO?jtM<<<yyfc9`dd)Lx;1E#xTf0oNRw!u0AfhQPGo3wb2n>(c4jKR5X4SCi)oV|
z4ni9WbG@{7TASr|Js_*NHw<Mkk}*1GG&_<^u4s`~inb%C*u&5E0}1kRFQ;@uM+A#x
z?+M+%%Z9Zqs&%?fYc{szh7wdT1;$kB58;OQJP@3!EB#I}xICP~9Naw!V@(fhap@;}
zEM9K!pQrIC<O!Xv1gF6!pmlwmWg-V6wb<`UP?Zt?CKE^2S{I9@3?3+>4P$uORqK$F
z^n~3yk;S2*1~8MuM?FLOUbGP3%naLSwtOntXqMJATfBxq#|vNEA|b7gBTDBDv$O$6
z8ll=d0!s`9M7VAfNh#9=o)e~;rqj6*BqHRSGup%y65==y3%B2YEZNA_0;lqO10z+>
zWL#i7kDMVq=OSl^FJX6wM3Y?DLzrjH*cGX6D3k$0hBx}wt*RXI{E|~~x*t)=8}@97
z(~lvx*C=icQCb8lp{tIC625uG>Z!F$%@8>e7ltM<NH#ctC655{p*7B=KPLw(^-PA<
zMan@*slFC<p_vX^m=R*4n^Th5oGM_AI3E1;z#q<_6@Vibm#UXmBjp@=V7VH1uoS6T
zh+!JjUJ_c=KsHxdHb-HF-_huQ6o$be1!ZT2Qe!e@WFyRfuEwn|>_JjaRFHn26pRzE
z{>;-Mqj1GOhcX8|P*!yTbb4-)NhT9zJ&qGaS{Q^@Oa=Xr1xHlJ^88t1wB#9AG<a|(
zG&Cr-mn4>HAFEOzH926oR2T_p3<jT~z}OwRYp8q>J0L+VLT+f`wwf;BB21srV+uF)
z9IlO6b53-BPB@`m=9c~Fn6{V+okJX{>e_pnxX1;2=(EKS$KkO4F3_N3o6&fK>{E?3
zY8!<}HmIk%D^d&LkRe4Zs?f50NWwhjQYsqx(pW{Tfu?l;=y{wecWX$Tcf*=?VB+gI
z8bBk48<np(sxOA1*brYVQQ<xV&BvQ5&?qvaM|1QFo05n(0~zHqs#ZcMY%z$yIyyc$
zY`~n4=H#jm8VAXQLBXZ75ajAWT5e=UT8FWo&=gnHAhSflR}y^QgguNe8b+cs8t`eY
z+9WifUSX|mG$<>V{-Xl(&2iX<U`A^*hzX9Ns$cj)1^E817K3G^x~+jETL08jRNAfU
zIe^Z{$YU5;_&K0wPQMRGZa1T+LfNW~W5bcvV5JPywOvj`fsi<dt#m-QMw|vFWl&M{
zc<aq^QKK^nIW~z6GYi$W3RAhhj@D>O4pmfyJ_PUV3}3#MAP~JXl7T~Hz*<cp>>I{a
z<4kDjhcX}-JMJ)Qm<&nvE31^BbXI;a4~ZL;>f5OeEeCUNF51O9Ai~9Tq*F|dcZAY9
zBc5M}u=2h^|0Fi95N_96$wp2>r`@5~G(+tst(B+%x3%(Rp^ft^<{CwftVjY`xL<*V
zfuI+wzF*HYy~um-HAajSWsx~rw~36HI+U=$ZyhWqAhA&Nz|OE)+S@Iebx!ydn@<K?
zrDkE_yi3VNq>e(#3a{tt848#KcB!p9N~#%l=|K+VHqsnbspimWCo*hVhcX)usX8lN
zi`}ML55=p=q+NAh1xuSpMt4L)a*4zw(n8fxe>UvGz@aS%&BWCMbmWEO;-tXppcFVq
z(HOssT{MbtG_x}|_!)tF9vjG@fhZhD9Wp_|4G-Ob`FTCpMh6wO2bhXNT5L=isW(dx
zDzYS!&WxRi7N`N}8Iy;<LZHd?qh5vls3{6g=BlKtm+(U_fHq;&_hZQrZIy5%N`^Eh
z%7G^Y00vHRhV{HABSfH82m!sCQilVf$UvYxV{wl}R4qJ_gUIuYUOW%cctG=49t!~(
zSx^tE1yU5?4O6i?Fab)hYXBfi_W3L!>Q2FOVJj_33U1st4S5JrTGr{!o`UAZU0yNx
z)WaI`NgZTu`+!lWPwk2-RuQ8*gtC)pJ<+7;o$^`&DWH~wMk7>&G3tbx4xtL+01j<K
zlY}hqkqmQSyj@C~NDC%$p)rC-#ur;#4-hy|z&fj*uNZvBB*hk1RnZifdlttjQi8&X
zc;zsJEbD-j2iKw6_@u}OYPBt@0>gAzVvS4dhcTFxA&RCCp+cTXNBUwus0w*l{Xg;!
zfZA>9(W=}aEx~CFl52RD%g|f!eBoe$U=<@{AMN9yaNkd=szozGDd>`lwHR&Bqy()T
zaLt^5m93b_h>rBBJWcKhYw?Mu^3)G#O*$oM9-(E{8B~_AQB@yS1PHh+m-2Z~>5;QO
zj6<meVTSlNLQb)?y^8cS2n{U)O$whH*FzZT7e^!nsaYa=RSHinF7s?Q&0Hz=Fm>?<
z)9<YrFVS+0nW}J-GWxV>7b&2kY8{cCZPSWRK@}25Cmx7Rj*!MH7#-ONGIhTLtbwNK
zM!anhsU60<6nv@CbR5^d2aqYZqEby1v0P+g@YL`rWE8h{$T*J=rtN_BXrr*13^6W@
ze5_{{Cqs%`C0Q{w6xBNNMh-pA;rSt4S%i8m;*rECsvhxORB(WuHAN#rZ5jPSaSxdw
zG|G|!Z4L>pff3YjPLujYY=i#yUdAX_Nt{jT=nn<Z2nDA?9BTuy1Q6DV<8)jlYp<D7
zQ!v*1sn<}e2n~^H{m91-r4?a78vHCQR7tBn!~-=LK=6kzC2&HN^|ekA@WF=H=evWB
zamsZ78qHa$+D=rw!__Or;nuSw*L??ySZ&f)LYpY&tEr#i!Xx93v4pIb;0s`ijTjq|
z*h83l4mMal){x;ehH(0Cm;esgj`o)_Ss(4+O=Byh54e(Zd|pKPmVj$bY!p*Gk*eST
zDq%naFnCuCA}ANmkSBzm$H1SO-+C&kEi_%{vRFy=uYvOn(P#pT;ZlC3fp9q*0AUT%
zOVuNPwdJ|1-ra(sV)IsQe;&MT9YMpT+Ncc0Q!sco4dT++w6e?rf^LVZJWt?V2HvmN
z&|4zHT7H(WGfD<e4aC|5P_oeg{IHst>FSJidpZ@u>3rXCzT2u}y(qnNH9|E-R<l4?
z%|#b@4ak&?r!>%w$ay!|M!qS{i_{=RZa~!v%lgoQ8m<(SR!#A5KR!-m$)U-d$9<k^
zYXAkD50HvdXwc){NyTc=>OXo%YMXa~vj{7BQKU^(gyO*=ip$##*U<TCIO!Y!XBwyR
ztkcDDJL$7gDGdqP0u)^;ke0~0riZZs&JBzQQ$Oa`-(e3hL#9sM2GG5AyUN#+4m!?&
z=y;(p-ZZTZD4>G^FdW-7fa`on9h;VsH>fh!(H7DOwdMNX`fSNKax4uHH6E)x78)?z
zNbeEb;BfHLNHmHyxmPC$QzJN^H}SDE<k3*IC`IjN6lB;7QfIiRnmH|iH3S9;kqie~
zAXRW7ivi{0b{$Ef8J7oZCj$r(BADFh<`r1Fj#7TltG+jtr@T`*OWjmF)A%o%2EfQ1
zU?vs5SKh!KdR3JSSnsB6g!RM89{d@Szx++ZdXIFV@euMNwNL9ftMf++22U?*omPIj
zu+d^#2UVd%vok&@?-$p|+Y@X`RR(WMH;&iQRl}B<-=d2|&J!9IPmp2+u;^tXDQ{9_
z9P|qkfVWmkv(b25gRb+3YlQL0;Xwc6=JG&Vt5M3?YViE{qWJi-nj0ctq3VSEa{)~b
zNA1x1Z;BFQNgIW@I`}yC{n;{ab1Z6XfPVZpY-W6)j*w<)B@T}$y?e;J#fY%n&?3~Y
z6NpeLSc#76hhsXIK^!f((=v)iRx?!>$XKWRX`fcXDn`ATI9C4$=n9bxMbOe}RWiCc
z93C*Fxe>Cgl{Dv!=8mEBkm}BWIE&-Ks>?div@#$9P94S)O%VF5LGz)tO14T$>(nSN
z14WTyjezC8Br$#~L(eA?wj>^Zb)uem`g${LnqCGq5D*SoY<p#mF^EuAmF~-=z8b-U
zK_RQ5yfB|Q0+lfGoHF3(7m*l}H^7$`9XwdIrx%>!4S|{kQ4}|;*=WYVfY&c55Y(|W
z{bT}pAL!Z;0q5N`jk<=5{lu~aKEis*`dhGcZq(n-SnDf*5!SP4o_`1L92hfyM^Eb{
zC26@F?`EH*Xlf3_?N8j)H(;Zx7OdpIw`QcnO1(?<PBo(8mfbG27{(SByD{U|V-qG8
zdF(M47svV@LEgtLLGIBwk%4Hax=fQ}=Z*2tRZ3Mm+#P=CQ!UC>V~*h<PPHFZ!d@81
zSYkUKD+IP$bRspz)G&cARNV{wx=xG{Xq9Y&HA8F9WN;c1XEL@LED_(Q`so`I*mjrY
zr?=LWlOgaN5^7r7*@N*z2<x-GEUfa5FSMHyAIQifbqN~jtky$(8?XF8DOyf}l90~U
zjX@3%LUrRLGZk@J-$#mZl5ut}Rgy@3KybgzjX;80_mkegGb`)gO}cZ))Lq^8{a`7!
zlV(1rqQgwcQ@sHGI=?D$hVj;vr8i@S*bKXQfMp)P1g<b^4{bCuRAbME8HE|v+>9PK
z2l~i|9qf+y`I#GIIc|a5EcN(a>7Zk8%uCl0nq!UPnXw%j;8hukh^&)ZB|wj>;>>q;
zu?1|Rp*YKDc^4N<ax?d9Vb@cgy-}TehOqy6LvqeAp+{Wj{p~fe@kg;zq^5AvUq_Q;
zuuD5g+|5HoNs3ak{90Og2$ai{xX1)=KPB-xep8K=!f<Y-ZqS_pOKoQR5N8jUUOWae
z-8$%~LNgPkCI!=Gi#!VJ3r4s9p;yo39C{Zb#g@l*+`P@!YXgOg_FOP~)$Xyr`*&{}
z+wtr`yylKex{tf#f>kf<-j+P|?6!E$FOKdy?v4+w-m`3H|5MBA<|8xPXMXn=hwtCh
zSDNws|5cKMKe(XhcPAgWW?z5h7km0obrUXWZ~y4hDOdELV`pC0Uvb+LS^ujg-7~KE
z;)>NPRwj$Sf^KWik=bvpPG;<TB{}=S?ULN`O4Pl7<=&I8xI1}k$2xg*`)_*oZ2kV#
zUf-EK$KCO3dHm0NZ|Z+({S#c*zqs}L@yeIFZr$^@uB-O^?Xk7{{`}Y@%bxt|39H_I
z>j$ge-ha*Nd)Gg;`lV0*dDZXsKCtSo*REgo_E#@>?WC!v%=+x2i)MXx=LxG{nzHld
zzdrKOlP~XGaPsAkT>RSQCr-KS)$Maf-l%5o_~PiX`~SM6y!?#|&!6>~N6WK5vvBSe
zuP(H2y!`0-{dc{RS#{SdO{?E{<D&h4E6)Ah+xyGEyYlX(`}aRu9@~0Vi|RW(Uxc^?
zkN;}un*Ns_yRHAnm0R|0y{fwM-mYJc-n3|7^rq4val@;w{LZ1Pp8VYa*H2deDU#KX
zJ@nwJzs=jc=x>YuR66fF!}~AaF=5s}|1vY{vj-izdgt#S+J8##)SsXG$OXSRx8vjc
z-`sKBWv`yI^o}pa`8)26C%pXm8}h67zc_dGk5;Z&{=J1uuXy#_=8ZYOS-SG1mF3m1
zZkl`c{$on}-wx0E-3iC9*!}0PPJQ|1t1se(<|BG`Xu=Of{`_`vaWdoHYsW_J{r9mu
z?1sx`uDE*3uXg^R@Y%0l(|=iq>tAW^oB4&u2D<v!pHW&O^6Z21lUX;H+Gqaw_kW!E
z0w2y>BKIBhh4xS8K5_N=D>sjp7H&>XoAlAM<mPSbKezkg+C>+?|A8xeR#)tg*KAw5
z@4^nVux;(sNjp{^*RpYR?xep+x#v=u`<+j0Uoh+PN0-jH(3Hams;8B|#Xwhkbnfm#
zyyBtRBXj?9NAHI6`fIOd?1)wG$`u_!|7+WBO14P#sX}l_saIN`eb8RN<yUq%et$<x
z*Zt=_+;xFHVP?VRyE>$0CGT`w=^j0H(shsKXI^(s+wOlU%Ef=moOR44UoPaHuygmd
zZL<p>IBP=7N7tH>ZDG@->7(VI6RS&mRy*_KPj@usUaXfpx5r0K+u_PB8>MOQNPYOB
z?)q~>x0w~Q?vlB5s)c%PXwmiPU67^mp*?fs6YAAvFOS_&`pF;GcipjjN7paL2D-=g
z^mdOu7FFlpJfV8wrdG3RY``qqeN}&9=zIPBBlY+Pn?~awtR9*_|E;eqJZ9g(io%v_
zFDoqjzcZEPzwYjS<&n$e=^HMSXRmVC?>Wg`v*&^Zo1Xf?f~PO}$co<-wy*e2?g#O~
zNl*M)Gt<<P&O)tkN&L#n>*76?hg7#`_VGiP!E<b`_;^=*C_C*xS<+Q{Iq5|AdUS`C
zDfP;tDfRxQ_$a9}gbbTSw#%$aCU)H+*CrhMkb#9I=BCc-)8X*^whhDO5xc%TvT`sP
zjSa6FbSq?ZC)eP@3xDq1^_AL!r#spg<g#zXi|y!&`z(4@MLt&Tbl3FXV8-I(;#!sQ
zueyE3eaWdGK(|fd<Cz(Qi`xogg@Yx?p3h=zIr~>dJ@dqXcA6MD+eoR%*t?z&6a5mL
z_F&gZrspc|4!^<UpsP7s%b@|&70b+daVDA+%l0iydh0peH-qthlQErb1+(%o#>`yC
zEqg7Nr+*(OMcow%B{O!FIOe7L=#h-CKV+!?f!NwqM%H7o$W&g-GF{?L>%jZ;Ow*N%
zG}ZQnK2Bs3`YeUAie>G6_$?B+h4>2?tbfC7aJE?6DOS3meS^W86+{?1{iS?H-b3>_
zhcO@iu*A0%CNUp;mCf^M$Shb{GD+I2r-`kfN>x?Je+}37(yNYsfO9zsH#FggV8-Ll
zX<QSt!bUyQbi}`c1w-)2(SbfcjWXyE3_=A=PuwfaP14C)vLx9=@621!cO!9YqZ$*D
zK5xq;s2jFOUHX{6xEFxt_p3Kr(vr7vJlegQJeqQ@#yb)v5b4he&rMh}&V>gkG_m*F
zmNC+stt(zT3n!E!+b3Rsj@)30br)!ywDB0L)rbB+oRGzpF}6Rc)|R19!Q>+KSz?8C
z>bhit85Ae(i1WI;z}#zk8A?V^&oHGLSB)$Bz8ot-l&5$$mQQ^EE+@xzUPtZm6{UU4
z?%8w2D-Y|Lr*=K_v~P{#AKSnB_1)KR{qw9~-=FW<chMUkTQlqRW!G%|)7ERBf9=VA
z%icU=|D4ySU9<Iy*9JcE+S_mK{g2Phnf1c79d}=`^{P*;dGf7gZ(clS>;31Sc+X2)
zw_W+#3u}7bykgF4_fOk+(?!32=2Kh#c;%dXE}FCTf?3(uU;6cuD_(hU%_(m#zjDiG
zIrDVU*ODvV_zZbHd&1Y=CjPA(`}K^_eZLmD{cl??xPSFc{n1wfJLDuDb-J7r+jXR=
z^T%liK71vS>uR4VISxUY`3aA3OEiUPbgNsc;RaK+YJu`061Pv2$@QA+dBljjXj(QL
zoR@9i5gOCmR!9<KOj}P9E$wrQSc9+$VKVbgGG%-35+40!%d<_gBHyPUi8SlP7#U;x
zJd?|tILy0K`IaL3{_3Y_RzAkcbH3rw6v6+00ag3=5ZEXsSZM@2s&)EqAY-+XCjUDT
z_5hQfA$jj751^C?$(HA+)+o`LsHQ%qO$JLx2N}e4^mom5-DMR_-?8fT%nMn!x}t3F
z9>6dRyM`Mv8<3FiB}cVFR!*JLn;B%1)3uyQq`Pi682wGa2gD)6P>LScdnV#Fr3CZ!
zW~^!bu-7B9j-@4Q;uto5d(RnE#;2eKwaB8%T^k2Ci>Sak5_Hb2s7J>*39YdM!)Ex{
zu27<=$F%4+{qUkqJfQSY#5G-Y?JxxBBF^X|2kxoEex$JeE*KlTAdzNilC|AAm@MaS
z;GlXr15wLSzOHSI7jVbCq6d120KlnT7i&Kc=%qas$d=(lD7{PXOSP&3og1V?Xn+>X
zmu7+>QliR}C?t~-cS~9(N@}>lKn$fMX*E(BPXq94PLnBaDzeZuw`Q7ZB!@sTAi_Zs
zhvh;ELb3dTSn*)gjXR3!IWgrNTB&LP67+FHs9OP%vku%UU7fI;%LGGum{umL&7#)G
zkv>%AZG@plErYCsH^?j@Uvd^ZB!y#!30719PebLpAT$=lTS7CA{F$cLo>3A><0@>F
zfYDj(MnM6Eiiv8d7RZorf2WeL2g5gj5j_}9t~rD~iVxKNLjY<z<S1CpxIzGDkZIw|
zWtw+rh6+|~WQ*#C!L%N+DnQ3nV^mh)H($6-iHu8y3!<6wIJJjf2iZ3LjWF#o5aRiX
z7WencN0FS#Bg)x9Oah0))%KHbQpuKj?W|ZLU=Kv&0xrG74Hb(+3kGz8Zvqb@tNJkS
zijTJ`zp|K|Ia)gd3MJe|*^EZ{Dlz^%PS5X^3ovBtZDoW&N!y6+2yURsImrw_G6g9R
z<t%n~f%IDANT%Ig!a*${iXa3F2Z19yN08Ntvql3RT<uz)1(Q8J(xpU0JK$$#DKd;P
zEQSbDobmt`nf&Sy&va8rC!y3O=P-_fwcb-Umk4`d>^Q&~+7^_cg;jLl9UU=Ut;WGX
z!U%vJ$Dnh;Q`FKCC51qL@az;2ZvLWfJqv81^1?TVXFNh4iL#a_e;ilAONwP6MHJhq
zXP(kh1fAf$UO4@RmSDgqP%FwXi2Ou)IP)d`yb*2K5<!%g=_Q9)Y_eok`yAiYiusD1
zB^kA1t=dg$TDc}JII*NMVU#|x7Hfjph=Lh#F2J?0XE;@_eA=srHOlA0LVy5u(ji4m
zjtnf5)5MNYmOzB*lwVu5C12>F%J5*3&BaJ(_@hG}37J}`(}nN}4_AcJX|{-rWWM@6
z%?_8(VCft|lL>0brPo0O)P}$14WSWLXtIX2nzO=m<ml@}NA}2U95191@*@$e2CA58
zmUR&}j@ag&ueQ-?1<uft4HnDVRwfggkw#I>ZsVL5W42a{$?N+;F<(=GwU~{iPO20p
zaOR1SRn_K8P_qm}*j(FCuvsW4_8rd5*31wcv&K{Io{D-3*NV8Zrk8T&YH8NfpM)!x
zU+3{nSRzq$iJB@YYxT*1sY^*ZOvvF)Cd6FEcGlqHcMaa?In*snPVLaj3#%;2#RW$C
zGct%^!!_)XW1EMhoqQQSb);QEse=HN+?>~Slb(6{J*C$1N;a75BrF<hqUOx-lDL8)
zm0T0m!s=cO`SKF=5Pnu!V#qi$)HyJO1-gjGw9eL=3+otf9UF=KGR<v3ibYndHL{T3
zOgQ+9v^5%B!Vd&0ww++ieS_7ZEE4@SBsukch4gGY1ty=7bz+eoF}0s6&YGjUTXaTh
zGI1pzog<Yx0<4W~9{bq3+?GGMh|B?rdJWC7%0AVpc@tpaFdGJ~p^JTiL+h?}Q*1Pd
zF7SoiFd&G*guftkLoS~QVp0(!QD9-ZhLvNOpnD`|N@~jZ%YFRX13NW<5Cb918D2oH
z<0-w2!i&C3kQ5PJSeqVkdLh|r2;bx0^O0?y=9FL~Z!;fOTm!ytG>`&0G0=5rz5vox
zIrMa5_+zZ_Waw5S^wLqgs#Fi5_6tp6)uSg{b>Sz06CJ~xAV?NSkuWfzjzLsf|B9(t
z{eDBUhBavl)~_94cHpH<Xw<-rH)=QiV!IcE6M|zO3g%6%2$@EVW|mOsaNx2~pb2^L
zuOS6&4NC#XI<)E~kVdI(6}e7mpkfKKhM?sHl697>U`|0RssUwqnA~+{J^)xYsv%t)
zDI=8Cl6nZ!qQ=cGFiP+l8tLAch7rO2fWYOg5CsNh!gh-~0;mv6WP(CKAT3DHphn;u
zMhQ(EIl8-KCPMX@H@Ql{>wjd}kK0Dcfc380b@M786saMGZj^%WbKWp?$Of%OT^p^N
zwp1f60l3gM{yDDWdoV2eeV~%!=t6~LQeN$|WzEA{)fvbf5Z}&vTPf7Kp%r;eDqaPx
z4+W!+OVg!AXoV}bO4i}tAk%SF2gK2rSaexqK*%KYURGVe3GH7(rag~D^zl|d?r5Z@
z)nP_+$V5J%jtdbp?6r;b9L|sCB4J2lyllp8)*di<FmR%diV)31>xh*Wje5ADixL3K
zl0h@{puSZs$`~!a;%O7kr92S?!1;>x3bPv!dJ1jF$Ejl)p@4uh2VyX+LXTC~a2=io
zNT~W@5x{tN+)I%f9{s?j7$veAVzHrM)nN=)PgMhY4UR8zii5GA5LhK!F4fdagU1+<
z=0|Z9Xwc5e=^9jS3#Zyz2Lp8h=Oy596fLD#^^A8lL`zF8ky8w?(v${pRSHRQ(;8;Z
z@wlNMYxy<4%wCScPr=FzpME@l<tZA~lF=O&&5M>%$7?{q05nM0z>~(O5yn+OxpOl|
zdcx7(C2gRAie$wQuj6N8eCZX{!OYM{^0Q5z7@p1IYJxy&#P|BL5MbWJj9l=eqEWRB
zmyQxy^%ZzLCUVP3X;^w|syVWZCtzAffXg%}iUQ8NIuZj>198lXEJbYtl|hSWomrex
zY@=;7V$sdpLK$EKx?O6wl%ec1X$-4Ivh252wSGEud}H|n`1DRRd&{M%RePTh*Z8JF
zK0NQz0U@@Au+>$jXSMhhC3&c_vUM?U;Rmz+o<P;6>4C#uA^mumwWMZfBAp)xh{pur
z<g2!P#Q#>IWF;N8m9DzzU<ZUjs-jmijzg<N#}#RyraXqfcf&ElxJ@*&eMBm$jta`{
z-o;8G0Rywc4~li8x?92?g49jDMoOb&je#F3V?la49D@GSq*KuTpt-6wuJ!UrQENyb
zMnhh6|9V%DFt4?QkWQ5|4kkq$xXI{>)DlYF8l_Xr8P%9^I!@G<SAGPNbr7V-1-MRF
zIuqexFb()`K0z3Ex~>|JgkU0djHXf@0SB%=Fzj9T4xzzgqqNTHFrLFZrhsQ*CV7JE
z!KB`h=hSSSQY@EJ8nc2gO-e19ijM<Jhelt4K|01d<-w*-28m3_+cc#`C*}YcA98A=
za9pydHFPEH&?N9|65;tqt9Zw;ho;nwArs9_Ta>zl)z%)Icd-ENbi@-`kB?iTt*R3J
z@Sz^hGjI);2dy^7$y|!P%T-Gl+1$`qwR)FjJ)aX>Z1fK)rrP_wb)yFe`CXh-Ukyfb
z;&=dXU<eCHktzmH18U($AF|>l@IwPP9!1L3Lgbobh<yhPLx9J$&#+2k@Q;1@yuMbW
zj5<MHU7uy(6Y!>JrKn=*S)41@3L=c6y5Ax~UTL|EQUKfF_DGs*;KMkMNCVC2jhAw!
z;P67OgiA7A>H<2xj|1b8B@9!Y92ExA)}<ugy{(jn9{9RCLT|E&rRJ603@w0F_b+PR
zbx?e!>iZHmaBmnL|598_FsNZbKiR0G3IW7h!jZvA!6e?d(5;$90%h`$8AvlQDeB+j
zG>@=Dfxx7a2&UjtYkB)vNKUg0#5jkWLSx<`jyu1cBaYuJSaNe#LaQs(3QJ&T4Dmh<
zvJG0%RE$M1oS^9Bd@LyxY>k4Bs|?=5QyAKcMm1b+4^<gJopiOY>xd1+8$$rFT!F3Q
z!()dH=sRH2lmT&?b6sP+qY5F!(yFZw6On@D%$?C7j<X>$^?n&#`Rlf!na9%spP*6H
z__Jf|rwi#BKaB*2ZMuLc>rIdrmANbeN9Pt?e4SGPtB&Zr!&~`7pMVDMe94_}2cAK-
zXcWO&m93VkXh2R?2YAP%E_5lLE`mr~?K#@g4AoS`sH?uCZL1tEBsmpe9Zm}4^41rO
z?(VUqQoD(PKi=h8obHmbE-Zl2@r@T&^IYTVxX`D7fwWGuG*(@oX-3BuDpqyC(KAh7
znWkaXneSYM-7{-yyW|GziOk27E7dw-^F!&S^$kS)I=cmeX;RHl;88s~Ba?cD=;NyY
ze3`vT{g_`dDo3ZxaGL#k84c@j6hZPblvwVc*zne~W`oy~YsD$I<hUmrw5%TV6ihRl
zBOxEQC>zU<N~Xu;ux^lB_yMU}sqw2>_SZ;-k#|Zp=Ok}*Dk+m8&-i#Bkm1*YeVid5
zmH`v^o6f+69hVU6%p$Yh4KrBf=wqCF<^Cg+<OL;VI(HVl@I%UV>)4XxzP-os8|NB(
z8s;2nF=JF2_T%A~H3Ri|I_w#L9zU>cKce8hu2l*JmTcXNWQmy}>jwWtL~3elyDjuV
ztJCJn&_<`S&&A|4Jc!$?jivZ)yV3=+eUq0cr-oL#N240eQ;rVnVvV&N_@dwg@-%I@
z?Cn_+V?%UfEt?bP99-)n-8Qs?<afAxVROCC4M@0$p|@A^V^za<AfzLl&VanxRBIxB
zFRf{2b6uX0)|?&)%gUgfE!Pd^#j+D<*ayAAnpH=(=-QaVG}g?<iFu^JJ&`=miTY3m
z66%N-PAoBuRh5D@E|SHUW%2{vSq^SVO?xc=P72o6Y^PgNv$EmL%*YQBDv33J31~ZX
zGPBXTT@?&gU|*dL+6ijol3n+Kr~B%^-gJ<j$$1Gi`&SS3jXksdR=Z>Hn#u=$w|vn_
z?$Tt*_O;25?YG8jzI^GTy9ZBs?9H(q$zSR_Dp$HW?dKly-ugcKOyw_gx5;_o$(ae^
z<d^sLFWs}JX{j9FG^cjb*#{L~?_as^js8A2;ljza=PqbEZr^2dmtEFhl)L(x>aUG9
z6|T7KvQ?M$FHC+m+Ejny-X`;rFD?1t-}?KX{ZYNC_U0o^@rV2W`Q#53mY7#>Xd3<N
zrng6DZF)xa{U4vBbv^f+_l^GR`ftXwesN{xXOBO(>fA@C_Mh|UXZru`#gF#??YBF2
zzFog{=aZv9oq5mLFIT<&%3mM)%*8+2b?llOD|hcWbkWO?G(G)hc<!^8_g%jC_nXe!
zyMNueBbP3^bmY>~`IlY3;-i;c{`~ySZ(s7!&EH%yH~C8Lpyb?F4%++1<LB-Dc4p$t
z^UQgLEBntH``ha$-22%VrvBG^_MEc!?L8;n_Jv1IxZ{yWnx>q)=g{si?#VuS%cjdK
zKg%7d`cC^JPxHUN<trmUo6&UU|32pnm9u}bbk#XeU)X<nUtj;fopXQTo)`PpuX*(P
z^=pd%vg)Um|26aO`aeDNnct7>y7a5xtNi5E)<yR`bMT9oKK+T8-&}X@-u)BL-TT_q
zFIAVm_RrPJw_dvM@;i(BUjO3!;hSEVaNUzX2$!9;<)Gxj&gQ+}-O#-E_uawFyXCz8
z<K@iym;UtrKkWUt?El_Ba>{Q`*)wtE^&5`9<MKzAOgU!c{j)D0X{tPzV=Ufuo}L|A
z!E@)zIupd-+;siu?y=>g_nO7gEMBhj_1cb+pM81Wo|P*eDy_*KDaUR)!9M-%)1qhd
zr+)IUh11Jx&AIjYqi^s0l-;xMuJ_rOwwzGhz2eb-+WV(^rPj8ob!=hZ8A*BFh5eUo
z%Fn#(=1TI%W#_K=!sB5+KP)@v)XsYBz5VZ7bnc^Pbv3Q~)X6u;;pq=oPT2NOdzyBx
zt{tj+y)uEZVppYU=AYvB_^|9)<qu0fS-Ceim$B~fk-uJ;jBIL~A8#@L72je$By00s
zrEg50R2pjOt$aROT>nsV+0dH)FGc%1o9z!fqun1)7VrJYj8A>?bK&&zF`YJ9kxTkJ
zIxpOJ*H6nYZMvzvVo96ivy;U&%{aJT-jZ2$)(kuItQjBcnmen>?)XM|+b?T#cTO5P
zbmzxi$78=WpEOVKYm%$vb5kCQvll!Tw}&6vaR?ppt9q{J0iHlfseXq%vZYyG-O?3q
zE`Hl3yT1^x8|#hlOd=_5zuBBVSdu44%5q-ev|9hNzZMGhi`}4WtNpO^ATz)3ATwqA
zX|k>U2lK7UbA>|jIr&We!s?hCt3K6vyZKIWqWeq7Ey<aEgXZ*wUzU^XN!{z>pWeCH
z{QAyvGNJbR^glXT9B#g$Fub`n`RME~TUw+%pt`-dTE~*br^%UHLb+s15FWkh;Ba>C
zI;Nb{V;Mv5?FA_f{#gF0bDmr?(p$4nFR4|+rEcMjd2VHGK<wZRrr385&q806U1NVJ
zbl0aBx{F(?*%_OvW>Z#rwg+ZralT!$@DO=EcewnpZsfzozR8!x@0+}$U~AI{jQO7%
z*A4$52{(_K-tI5Er@9C0w=dex`=>8JH}k})HS_pn36d_WAH<Q|nG9f636o*w9tXn|
zM%8wiZTJna*}&L0g;p|!^R-9tNrocporr<*J3Mdsv<&wzFatAK-xj)!EllJFwcErw
z%TGcr-+tq0`N#t@ylEHD_sYgm7s1H$BJNqfCu7NIwC1>B*x;rm12xt^wdaw`*zAfm
zTNCnpLeD(C`YnR3Za#yr);fAKQ!_HN3|1WSP7<{YqZfW*Llo+BpeV}8j0!T8r|P6Y
z8BYA2*iPNSWcKN-a!SM+-v1E{n7l|l8(#JSM+UJ_O={JIbPJfUY<iKS<KiGLx4PU$
zIHCiN&pLF`8P}aodiU5m-qd&)QF7I6sSTn>6VHfRktvJ0>RizHB1MtkX$ORAwjhBS
zMqlO=<~?Ut2#@u>-h*Z!a^a|p3kLjfQWMA;c5IMWIMcsgHsJKGquiPPIy@^#Ii0lx
zk~@X0G_MkuWI+t&DTtJ%PC=|v$#o$NGkx%A@BW=*tAB^yCQ;afm>G$)>)fynI(ua$
zb8cv@InySr`(imMSFv$?W+hu$Xm~A+%Qr=oILP>2EROJOa7*+jxKT!q(=$y|evZ~W
z-OfEW+x(jE$35}08~0rF>iz!A)1!ZSrFGZOp5$Fhr|)0>=Cg-By5^N_yH2@r-$nb+
zShM==Ww+jW<(BX7y8DTJ%kDa34QHOtzvpw`*ml91*WcnjPjhBHIBo7-SAK2BXHWSL
zf97e+6Gt_@{_@wBd~WsqYnE~5>6JI9Wncf&*OHIje*cxzp1k;oEl<qKKCzYeIKBD8
znxp<>*`ez`HK*f+D{tEK)|(gXzvYQP9Qx|pv#_bl>lvc8lX#Eg8CzPDs%cA_>TU8*
zGKsQJDxaAcn@z+{b(3r$lPvEHh>w`U+lJiadg6{Svn7aUhji=u<iRhxPuDJ#W+Opl
zT3nlZ&`scLC}E-7MW(eba%{cn`vsRvX1f;ou*;gWsxow&3#-$=6K2X|Je+Y^d4DaG
z54ony;bZM`!)T`VKV4WGm2j+DnNpry*S$Ue?Yj4Wo`uvW_C!Jn{yS(B5%>R~2gVc9
zZSnBkk>hvC@20&g?4@~J&6P%&)Jt8j6+w3(`rWayp3V6L`YP~U;a*4o4fAvyWBS}&
zMj+eHld;g*PTit#9fk!qeb;FV4{Idq)o0?4pZYE-i%<*0LYFBwTMmTmF=~L2gQN14
z*eoPChSUoO<Z1?HZbRKw@t~zgx5Jw`>{O{7PBxg2agg&cE*ShOZQlwHBVFBh<tXWf
zLEqN#v^7f{>utv?-^%7&A;;552~(F8w{yeXmdON$KEI+qWCQCAHJ$BLo@j`*a^O(=
zNS*=Gm4_(0p5e3|#h|L2@@S;*!sFRqhPV50KcS#{S)=|CZk#EEe?<hu&PTZq>x?6m
z@wlz=9tho|U4@vq2WkpdJxqe2VM5*VjEYPKaJ!A#H9zb$nHQpt4*l;y)=~kZLqQEr
zZwiNa=l{W-4zkihDCC(jUTo{9Q%Mlp2BK1})#tlFx-2ViP1a+(oEG1YsAB0lT|LBb
z(^1y=-DD<^sq4(JVdSu3JDtY_Y8+>XVAI{JK?NAi*Lbl`&?=MQL=Y$pbju*fz88tC
zL`ody=MFtll}Ha2<w&}Oa|mj;*FvcCt+m3F>MUOqWPjA?L53oH4gr~Pu&d1xO`*{b
zZsR1Y(ufS9$#8vcKyEe=*cb(P2QCuC*IzI3BedULY1gRpMoV(xrUrT@y2_^r#RQ<e
z!#Iu^BQM*@#5xJDwvfb0<d92Q$&na!dc|aspg}(A;=(Y|vA<m`It@!qv!XHP1Dlm0
zxC(GZfpY6zcnlK|a5RNtWITq0`sj})Wxq`$fzfFAi)=Q|lP1CnLtcZ<TUN5NP<c+7
zxSvim#v#TUJxh`Ty_*RGA}s<g@eiPfWyq4UrCI1GWhOj|#rqvHky;i7;Lk%rG3tky
zUR(v^b#){)Uf#7nKaQmG6Cn~PIIkSH<BonsQBueoe9Kjqp&CPhvH@w8L=KbDFpY$i
z1{+t2>QP&Dl{+v6!x3>n=q+WmQBd7LQ5{v#xME1@j>CGTRCqZe0{I5NiQS)_o)f1e
zjBV5a{48Qz${}%L{oaVtvKwnc=g;FL6}TKEV(TqB)sn#GAV&0oh<Ea!vyWAy86Qph
z1?WpAXs&UFkl2!g;-ADb*ipCyz8b>OkBF-A`B>g@M6&_Hz^jtVM_))$B)bqHQQk&&
zKzCC}tI|zf)j|xqWH|n;UD2PzN+10;QRZPdECO_y5>%w_NM}i-W%FPRUi!#3-lZB?
zGEF0+pvwiCz-vL2NKG9}cA96GBJgV}ex0YB#w(;UAjYzQ-5X^Ohti$zOvZ^qr0w+3
zx&~e3^y8YL3o@n$997+^RK99h%p$4Hat0QA19=?<TImxxH3!G3PK6D+DnP<!$x65@
z7LLATh74_#)RQvW`7Tp7t8GlI>9MWKPuOX~OkS}b@+G{BVZg21NjXdt3`0Vj5NrT9
zJtEe}M$9Q-ZoTr;mB^O{AUSv}2d@orv8A0VUgk}A*1{G!&Igl}$l+Eet_01pbnP@z
zz&bA^8If_Nhq6#nYZ=?&2$FVI@ht^IEOMMaQ{ZODIO4(qDm7wr0YPE4NtOivhqm{R
zv#YA^{?|EkW^!i|@XTZqlJINKa0!<X;DU&Ni2L4L!X*tdgw&!{djmltjT#gz`uJnd
zFyMfwLqMf!<q|<-3rbPcqT&sp4z|{4)j};LDr&SM)Y^)_%Jcs0bMGYW(>~AZ`^R_9
z>~q#$YwfkyUi;_S=f@?^CXw+XXJ>p0iCoV-t>b&1A@!*nZ6&iQJ7d5E^}+Y{ye+uq
z5c4-#(2Xknf=`aC^nE4k@WYM|lGWe}z6H|B@MNjkv8pb@5=VZtkJ&9Ls;~%e<fRF7
zlc@z~Auw3)-suBlv+pxsuVsVQT*KE#neP15vJ9tID9LQ<c?Xc*x83?J>+@lj=aRi=
zNpCv?IkcwD+c?d#)i#&n%o^UsGmb`F=fw~VNt|n<ZQa>;K)qcavq8pO`dZ0$SW3Ct
z`D9v2FI?_}p5HnFfix>;%`qNgoaS+nn#Ps%hv!4jYxsc)El@1gFAYspJ!1k;-x;SM
zTrG`!V}1}vp-vH~My!*FmwX(fTz_Ge_fSR*et=6AN-kmIS3c+-D^gf8Lprz<jvZIl
zSBhm=*o=A=BOPh-R5wiUyEIv*R9+Zdfpe<l00%_S3`|?mKlDFpGl3=(*+y4(kpt==
zi6wvm(B>Po4Q1111d*pQT7brFKu=_c>6o)b)V2_p-@d~hh)wbK212atq;V?PIP5kk
z#D<S&tz9B`&xy`ZWEH3@+Se|t+Wp=JB$4?zMS{7mK|y$e96o@y|6L}U+7zwsHc@3B
z{}q|mFg^>(yE7PY!bF#6))59<F7-0NdzVI1;-YGgf(4B9CB@~RioxgocEzA4${>wy
zmHd>bf%}0dnxa(;q9_~qw7MfALA9VMxKA-MT||;3nV^O&8bO~C>Ii`V$gfR}y|^?W
z#PzOrzX6gL^%(DrFN5YpE{Guxb#YYLqSYgk49GG$^n^;Wwo^}BdQit&!Er>9B1~R9
zHW=GYEoR7}qt&ek$pff)a|nY#Njam^>H3uJi^^pIj#qmJltpmD1RaE8Lg^rxgBC%u
zEIHaxqK~}y1;ZQ&?y|8g5`xmCQ8mgF(X<XNeupu$vYx~F({dE$kT?!echFQ96n9QN
zw3zx5dX`BshI>%-H4%~78Y3+krywFEP6dJQb&7Z!;W1JYVX`Oyl1e50(lu3*Zm$>}
zwXh^r90Axt=!`iO&@-4HqGEcPNR}`@3&<a9%-H&hO<~YM^w!=aCcZ$C?uaKz?5a>0
z4DLswXo^vWU#4Ij@#;H<?x2Gm&4+Ki&+JwiQb0+DJBOi!;+ZCW<JcS@B||6y)uTxJ
zK`Hdhzb$z&!zz-th=5xen+2e@tr&BVv{W=8_~Jun@iK=uu?s;7lOKI|Hp;lbs6Zn5
z!WGNG3X+442*waJSIRx};JL3POPm}TOCt-Bb;PvdW!4CplN}6_=%#fM(cI2Q3YAir
z**M2ZAr3ZqAmbHHMjaMpiVK|g6sDVoxQDL%>?)pXSLKOS<H%2SzL683c7)mv#Yn`-
z5<>TR2eMH{-DU<J3DhlpD4#7NAx<m2wTfOEg#2zn={R+5DjwdOX1sydr6nGDGK#)P
zGy(MyqsMk3C7ya;#BU;<64E_{Ij$6y&hLUv^Xirm)1g8Ff{T)17;C935-3ru8%i`^
zM{5ES0CTWIw@~xy2!MLFa*W`*=Mbf0R$Y=WI3Xo>4Gvu>^aedU^7bD<LsO{e?6J>-
zID!BR{Dchh4I_~cpd%WMT@==s>}3=@-Kn%GSe7`keSe5Wa#<Xm(dA=CT9RQRswg@c
zCmJ-n&@vasSPo7F2ntR^p93LABIDAoj^E;}(kZHJk*gH0i(^PYvy)rf@t!D21n7vJ
zZWdnG(cLu%QLn2oL8&96vawx>juC>6v5U~&=Ih3dVti!Lb`gl}a$*iFbtow;B46cA
z89N=0MG+$6l&vV9zcF*f1MvuTj;)BrPT{8#*a-=W%!9|AB&zL-$qx`y(gZ@8%Qp()
zMf)!x4ZRLo0e3aWu?xMjZ6j?eWxUy?a(i4CVw605MC7HQq9Im1LE|Dl9{5&Dp=yzj
z@iB&y)KkmRC`esxM4eg@PHn~PAebkZ+U0jH7Y5W4%3c}+E6q1y_#r?MCl=Zf0g4AD
z3p{Wtp28^N49)Fg&8J5SnvpmfwG2mm%5@zuu4pvQ3FEf`Fw`0E(W*;3nHWV9Xqoba
z2Bey-tRXb|Me|Ki3<w18C~Q)dX6t7f(=+Q;t@K(D1iTk4-G#P@L5oj_#+EH5g@su(
zPbmn<r$LE(Tqu4D5rM-7Z+8AVRXd0UU+8eU#IHbz&yW<EWl>#{F@?l@jv_~o1d&*j
zF^LP%v1i}3Rh}-ACzw+h6q7mQSq(4oF8F|!9v;s=9*Z>8b14XQ4lC2LaT1Vu2odWY
zYSxGZubFQ`PVhx(>x^Apq1bW2Pc-WM6f5{8?g>qif$vE%c9EmzGhR(_lot22NQHP`
z;ew#f1X*R)7s(^I;uO7-sNR7P^vu&)4}tnY6egkuhIl5VfIg`}GF;6f6O5H*Gx9TJ
zOa=e8h#_hV*dwi(FG!PoKZShe$DZJA5)PC?Z956UgG+HowZJ+xDF062+L}=<SlgpH
zTcGt+8w=@+0r{fc+q7s5yc}YGp_q8q>I4QtCSkKN*%P6~QMg7*8p;SO14z2miy)Ky
z5GY6#^MTEDf!EjN1iT5$QC4z9CU~utyXhf^PWt6<s%E>x!l;icjwsJTeg@jz$(`h3
z!ZPL8gN(e0(=J2_Dk{3P5)qnvqLU!9!CMv}N5JbP$wb3lrD9nKL|jY^Vwp2ltp`>6
z;&uv{x|k!k3aAg5@5v<;xj1Oty6l>^ERGsPAiF&J+{;ewfCmF;Dmrneuj?IL5$N6I
zEV_W<0GN+<6N<()jH5j1JWsJm@AEqQK(71?=WHcChjYQnV2YnN-OkJG6_0+m8AK^(
z{lP9{_xWnQWBw~QYwN>;TQz13)6{rMaP(r!#s<P{hY|0jVM@%`4QdU`+ryz&E4dj*
zB_yd;Zzy9fJHZdaOBPM!lczXWPR#bUa9T25btSJ?0B_7T2ODg(a_-|Mi^klk*RQqo
zvI*P#`)r=B3Z*~ABknwk7ZS(TJ<F|`5KiFkr)SH<Q6KoE@~fJyskH+tcW$rXwXeG{
zeze-Mw_y17LuD?dSG2bUe0tpguMSSw2`6wJGsXDs%fYT{Se=2A(LKcKtc~%L80hw{
zSaS7ki{ojjJ&14rJcL_EH_p`&-?>S?{E*sZGQlPe_B}owX07u@8;ETrgy%G-;8M1W
zFSLXW-GnaaTABoSf2j?}Pwifx(S|;;*47hmTN)PO?c}>7_KmW49UC`W;;m*wHgQ|W
z_H;10aSE@X_?bKf-x91J&33XY<wxG;N*(8})_7iO*|OPw`|dR8goPuf$)n%5kM@bX
zq(<3X6>q3_^R1&~Fif1-;=avYjvwarJh~QEwOnat_s{txh=t|eTx*#67;m^zvtdV)
z?}ja0vT!+-*Xz_lVolGt*BwNrBgbF5CJ9CtpblE9_I!i0P*+==$kddZd+>n+8LHb!
zEChY0V)aUXGo*HtDq^2<&;2fGZoT5QcE`mR`Ukq-Av*4gD=J4mr?qF-<d-`ST>Yie
zyPkXU+?^LcXU`YETkCvz*Hxt_4}HPSUpw@kr+&O^*PbUHxWDwS=bSO~)#tz9yHEWf
z>3nxnt^KZr&$2t0pE0-RvTeKfwq6%LzVOiSu7wM({LQ9qd!N4S!aX0k>R@EfzWi6U
zZ9jd(d6#vr>f^gEeSMXGdgYaSfBlBnwjWrN?s;HA-_8$Q`O2OD^vVm~a2)nNRPQU@
zciQjD?|ajgb5E}MME%LhulX-r-O)2db9esTC+2?et#{4+;_GYYKK{Vx_I~8{Pwjn2
z?VP=z|8D=>9e?+NxsRQ-WbbdD_tm|ReRlock4^sU;a_ezXz%C0c=+Bs|MdlPe>;58
zmM701n0w-Zmv<h$=;aSTQ#*XiTNm@Yal6ic`bS5fwdJi}U$FDZ7cYG3u?Gg9dUEjS
zy<fZG(4RbW%!<lifB(>#-;53K{N;-mhW~ZaiCZ3f-`2g49dgl6zVOd4|Kz`zee|*K
zzwnMnH?5ie&L>ZvduI5P{tG`E^iN(i9qs+#w{G0~Z;OZa{@})s%sq47NB4eV@ikjM
zchNa}uRWrF?y;-iH}}kCOP>DOsg0*UyzIff|N6QQJp5#K=$7mM_3*vNK6u*M_gyr)
z_m57^I=}nqi#ks%f6>D~deK31=N^3e(?9s=Sx^7;?DMyL?bd<4zg#~2)R!lZ{^l)f
z2DiTK{lj~2S#!b8XRcjRdGwX%?R|9l;`Sr2KXLAv>tDU)nH5{MJo=$SCb>($^PY#+
z-SN9))=i)Kp3%}{cO7e2?Ch95@uZ$D>fE>EEpvB-{<+`ox~}xWzkEgeFW+<J+^r{F
z)4b=hw|D;I`>&gs{bAld{_(th#uwA}C;$H9hcAA7;)3I|wR1NfdRFt#9$2z>({!V`
z>DSAf_dIgw+`Iqo_v{5>bm#GYZ0BRUj+}Yotoq#QDck$fiSlPU50z)XS37pgl`|__
z6IUJ_zVMsFD_7S}yzN=<Tbmuf?zHxMfBdq_Ew5Zf!@gE_J%{gSw%_-M&6ztMe8<^u
zxv4z(*(Gnb6W(##+~Xr3>%1o0(0TO@e>nH1U7hxE1IyfG$oEW7o>Thd;;H8N+H@|P
z%}awfjJ8iZtJFO5n&D=D@DJa#y?McXe=xA~-0Q}6USZ|AQ>UzX!wpMr{^OfZufEdq
zaQj26cYg4gBi(|V51Lt$Hn)81uP>OpeQ>qonZL@*Y<%y--(A_c`FV@~=Iz*Z+EDYh
zXa4$croVOc!|mqPpKxb~9rU*uZE0KOm&?Pk_wTl|8cRd{i`)IGFR%1N_piLG(t3P$
z=f!vJX};~E&dk6it?T&}q^(KbzVDL7_O|H*OS^73qOzg?wR@j^_?dhE>gN9Ny<5xS
z(jT1UCi?o^?j5D@(}~sLz8hTFuy8Oub?MpJzj$9hwU*qr?fj9()2}`3rd{h!zo|BO
zTziK-tG&m+ydCP>_B3ll?yFb-1y&8owzpQnl3R}rubZsfpIGYtCZztl{=b;L>$1vS
z)om`U4{g7xf0cjJb29(AjidfLd$yf)R$pmD|8b@J^YJ|oW#i4o2ebQp@v&jbjk(*h
zrEWuQ!0x-p!s8o{Y~FAI>(7NgJ7I8B_LrqG_l;JP`L8d%DH%NZrpcjAVMpEE%*@c9
z(&S<7zymaM6GMD~W_IKKW`FP?quEUJg<*920XBRMw-d7;+t>5IveEJ>aUX5?8;pnP
zS8dsChcaFc+p_x)u-nr^ohJWkSnjInn9B!Fa5s!N8yTMo%fcd;Pj2NxtkRx%Nhw^)
zJ<P?E49%$vD>jrv?hgs2(F^!?(-yaF-Fn7)#@;sbEyieZJMKqq*^Y{}I>dR>$uTgy
z4okXpkhy12&pf@I<ypwb2TR$=%S!pwOW~c(6qs;t?`WG%kL9zI%Wa~*9DA3*D`f=E
z#-DU7vTZhIc0U9DdFw65uX>M6kk`3(xv-gNtD-tZoOi%(8hRm*+^^3aaRq${x_TYw
z!2BL6I4|RTwhg|6>!kXqUS;4~mpN+$q*Kx}Pwj(IMOmzVAwOGH3zT4v1?mh7pbqQy
zlG*J|Em$piU?#X1q3^a+ob`?IJT=#>tO58;IPGV*3yUk$%xlKJTC0?>b#X3pQww%l
z$9MDu=PjJ)Q>NarjuziXc$?mqm^-3o^(3?1eaItNK{g<3$?5raO!Ird3(zx9{=8mn
z-`VeCflI0$rPZl&|LET@PaCf$f%EyrH>I6^1jfr_mb9v+;nQ7k%$Ntf!ooSuvY{<p
zYgJKjcFRhKBvXeq^LBmNHvgwzvG!#$sQ8Z4yBqjx#72Mk=;P1&#%oSa9=`4UPyO_l
z5B<ldez*B;+n>1m+PRPL`*ELs=s)gzw0zX|tv{cfd-9g2w|@4V|M=98PhNBHoA17Q
z?vh_U{W#A&-Tlu;U3JT=w(t6}o_YH0IrshiuUC$J_En#F;EA{X?zfNsX6qSu{~pgY
z{qV+3=f3r!x7_yrH=S{}e!K1!H@2Sm^<TgB!;ft};}d^$a_v{gy?@(JfBnc?KJuNd
z{FdFlgFogwPQShP?6-XQJC8rBlO$A_9j#}c(pA*-nMtz81_wK{`Cu5%`#KAfg`q!5
zZ29!0-7wwPS;tzXG?`SFS-%}@Z{M?~HrUz){{yKH`PxChIJvg-a9?md32CeI>s(^V
zo*Oc2zsvHw4qzQN7@Yk@$iwxwj)cM6>CRJb`iLoO*C*3GZqm7H;q?XlJDIp}RqpN#
zSvVjhd;Ib#ck}X5Y;}bA%+s$<6(&fFQ}>u>1rq)fl}MnC><?a@ABfMc(0qH~ddPn{
zclGwD9z@~40T)F%jLF_o_6|K`(mAYae5h@)@-7HUE|bEp*x%+BduKQ+OSv)$Tok2f
z@J%#K+WLU3R%$+$A(&s2CvE50!1sDo<pAW{{=u2dcj&jPExC3!b+o}~VLssd_4tRL
z0_?b1o_%L;C!_B;{7k{?j+&W8KT=OAA5>W8<(;;r_u5g~UCA(xOA61GZc0C2$el-z
z`B*a9f`LA(bCu*E@)XCy(uH1m`!GVOMWaL~40`S(V02=KcwJhfQmm^8V~JhYj1N${
z4pBR)I?aWQ{B|mRIo7ey-<EfT1Enmq^*Jbqjh2#6YK|iTz!YWYW<6&Q6`u`f?da?d
z-}a{HhEI)jJpEcS?-LddradZ`IOEEtWyX0so0qG3bf}XBmpfa;qYnv2d-*LdA>ge<
zKTuv+M21q?28W?SCna;ZH^MNNkZnw>1x4E#BJHD`rQ|HgCat6QWd{xCk|wWt1YiuS
zzWX2y<evC2G3vmjkUhDDvSnPwm<v3E>JoFZZInq&u!j&cNEKt$!kbnh#NSeU-6UA3
zaj;Wqk6tl?AmO@_`|MRO<qXi=S4EiiSaM!cJYy6bj7$eXNK$XQo{1Yf5ZFq#b~24m
zRhoe*T+vmJ%{A>B<Vuih-z4O%EEGF!GhB(tiSjd`LVB6t2aSuWM7nGQ0pGCOWTyUY
zDit}iMHG*Cm@$W~i%11oz{ihMYsGl{C`+3nNR@*}l}~aa#&(eh18}z#u~XzpRO(1M
zJ%ZSuA4tRbTi7s2i%mL3Co;z&B}MVobG|x*5HU(>DJDl0=_6yQswuQA5JxXi6(7Hd
zFUZLVlL$;os3FV*%s`$G&<u!yP(LAhHWnarS=x16p*FQ;!-aY-(}j@7EWe;DE7hz@
zi=uey!O1AMv(sixs5(d%Gy*wK)EpG*Ot&J%9F`qIh*Jz}D+Xk-68ZLJz(M$5n*%8=
z{Z?fL<TeoR_jrpXqmmkSW@awH%QBuhDdb!;`uX&VQrMWXXBx5o1hFP59p}_MM<CGe
z1W004G*Hn7t`Vpz9foPIqkvA7itcb$nHI5VSMsdXaA@jS07`Ayk-;mrz<gO*D;FxH
z#>v^FILZUPj<>!d)a4dgq~uOYl_uImg9Gh?!%+oF3l$@#@a6*vScyj7gRp!O^-EQJ
zNGK?whM+{Z*;t@>?Ip~EFR)zg^)r|B$c4JnFr6!)&Uq@BM7W*ORFLwti$2Cg0KHN;
zilcl|_VkWW9q2Kf+BTwmX(SmF(H0M3&Ga-atKwDMoL}({HqAi5oFW+RSBxEFo^_G#
zEf~NM;Q0oa%&`N@u^!l?p-I~WJ2ffQwhm5S*RnSDtn01MgX71{dB?A)YJ7pkz8Rx4
zNUFHw#Ask+dEQW^mXV&X({Y4VcqGv8LjZAY8D<ZrJjc7&!K04iKc!qF!RQg&kPLX*
zZ)O1z%^Y}b=onS1d+jUCKD!Q#*@ZPci0`mUDdlxHO+Mac=ydu%ly^Sz<)b4pJTVbc
zhDgsi$Q0UV#LLA^&DrbQ#zPA;$cl<t>XM|91=&!-5waWENc9KDdy&Bsmujx#?J2~k
zsHUo!RS0R~Hw-3D-+`w}@e$e(Q~uee#9AwmVH!!9=O*RRiQv8GY-t!AVcp#@?}yGr
z*qqkGcC`1*_n2XcLrO@<*}HZ0xF*kn4dj6n#*kOt=%&%;FMf@#iIv4m>J{`vkPk~k
zn5?q|J(Y%34=@x`Jk02Xz9O!200?Vh#CDODt`qadzMhhz3i&80GCc?&QXRp?qt7YE
zJPnno@aV!)A60=+{C$t3_Vg=tK*$MkRt_X<6~nA30_Qc0#I8g0@m`7(imoxrQpE}g
zoLqsLwa8F5$fmW*p@0;T7=dTJqK)sKtM+Hh30@%tNe8*OP7nkYmjrbk1cBW^aEG?k
z@AC!9MuP#<Iu!bpSRj1`cuPskk}plnX1YWv?w^VgjVfw~^rRT)pnM|kJeEXY6W05&
z0(Y7#1J98Z(PC+a(<oqEE*NzX)2F=K)0Igx)2c>!cuq-SXNVj2(bi!*TA6m;o*xk1
zi6m<~9r=k%iu<M$V@n|)z@f>J#K%}X<k7@*TAIvGr#Z(0B*aU`$}8qta_}ZpL?K<k
zA%1_aVPWBD%1~qnTQFt23dB44rb8qfL|HNu?R1HQV!m5*!uu$!RHRuNU9C=5z`jbt
z7`BHcg_dZ%Itj5-AsZvTWK9>NxWXgC8e2yhoXz{fL-0NIsja$(R{4*Tx|LAZ;1_{B
zeROnG!I&Yc*WN|cM6}2gO#@;@;B5rBq#(!0)`6j-C>(Qdnz$%f6v3-R8acFf@SH}y
z)7gP?%9uF7TwR$KAblhn=j6!)Nc$Wlb@-ajcwI_WzL?0z>x)$PC<R5id+Hed5hEsM
zYAu@_HQAc$Ib3om#W4v?F$arM=^%5vz!a9!`<c25DLyRJV_9B~XgjJGDqqL$p*9yi
zG(j^BQar<<E*Ue$$J7$N%40m#%{NOqr-a0`YVMY;7@LAp2(pqS<}(u>+Y{sFX40`%
zljJND5RVTt_Gr8fv|(&vxfJ3+38SkafT&6Pcy^Uo%cVd}=?crRPUYZsAAhnp4kF46
z%{q+B(o8af45Dzyi~~I(xjMee=m{x7Y^C>-jsQlACWk&Ryr*mxt!~}hxP=mElQpI4
z7dt}gx`T+B69F3{-8qeig@zC*I>Zl(mT5RJ3c1+INg7z*aK&W4r@*5twk?u%2=mZ2
zR;uHqEQTVx2z?fa#J1)jIt-V&u{0(gX)>=9KqA_*li_-034UO@mqBt<4={+Ir13>G
z;l%5btYv`05V@Am5ePa?9Sm}anYO%L6J?rEl~N#Ie);<a9t`KFrRgFze}t@hSBe`#
zz#Olo8_<dk16%xH$wkeP%;9X7lSMtaST53%5?ee63ohoa6cA*)f|{eiIjv=gdrR0N
z27{)9k4LQ^A$T24D$wOPF_pw|-;y#h(xEdI1|L8fN7YMl_Ap7oKh*(sA7~nz2iHxH
zTo-(gi}F<ZMv5Y^G?Fiu{k`OJYJtT9rc#3;+6OhnHXkC!p$k)-+t{G3j7W0bJh3iV
zw-7~9z2dT2fE{tf#*W~ldl_Hg$tF_e(8*CeTQmzkU}*?e1;ZXOeW6>!jq0k8$BAYj
zOS60=O%faSQKu8GK)!(!5$A|SA4nw%lZ+!Eu?WrBo`tf=RXPsH1|5Ae=9r`cYnWX5
z)k)=|y{Z8@<K>4!rim0<xz-dvb|$_%hOeV7n3E3c`>>XTD1g;5fr~aF<c6};bDsAc
zvPh@#)GOtT#>TW%Hk%Z;D8f>m^A^H15;7W63yaq>k%SoY6m)#Ys7U(Y^C?TZ89Nva
zY}6T0NB7a>7{xA^!ZwJB79G-)KqW^}L1Uhr(xpX-NbJc`DG>8yc!<pu)lL3l07|E$
zyvB%=IT0e!Ypmca^p07sD0{4wG+nipUw-+FlDSYASSS&NEVtxYfZhYfg3?G~M~Ymq
zEJT9~zIP=^5i*CdUMRUaoiiPn8oZ7Lw5VUI-aA*U@ndm(D9VV4_uWJqTQ!|{6-$89
zpxm-%Hx{X69y>OLq)CZ1;x+F&Fc6)J<d{?sYBNL=s6ZHJxR2TC5nSZ!IfhZgWJSJo
z<>;O6C|^i&#qBhedL=+WzI@B^!j*`O1x|<5b?i(bpxcm_8QqN4{fMNVqX1T5YV8{8
zgivR6i6%@ir__m4@_0a7z&0wEgwlDo4=iL51vFQTah3om`ykL2LADmNK#X|i3zI$c
zUK0iv%h`HfHIib$7a?#WN2@f%Z&=n++)F-)G7cJX&-_Qyl&H=jDggJeMWpWt)D|%$
z&AQ_+Ecx<<ACx3}2pg2zdo%!Ci8&Xsc<qgZV>M<LT}8?%j4puXA5K%gz2z-(Mb&Be
zM%G~xJ6+LPTFX^Y-%CAzW^ll`zy@z9Xs(-s?@Dtf8`}P?kRJ34ArIPBY<uYFDW^Jt
zLW?8>3@-d9USa^JZZ6o5iQT-Tv@2K+^NXJEVv<6hqYxiSQah{%zpU>m2vK67%gF-f
zcoDzyCFEPmc%l>R&Qiry21A;)=|5As9qVW8(&qMT1R?IP8eKcs`hYHH!zo{3B9lS<
zJOVk-n(6fwmkzqn>T~QfrS~`a@)A>eYA=oa3$47x1zc)pdAD(3;C{c%w?pbXqdYXU
zYk0sK&eAqxap&b(J8VkpSY>;7sJ1i0ugfK6Ez;YTRCx1`F(JXXCsn9S-aj45bW0>X
zkTy7OugsGn7iRl2Z!><%nsn0<`E-1@)A}kooAPn#lV&3WoYltdK<pjywu7JAa4GA3
z&q6+NX~0yMH2i?pLBqVWG+^T^M{MsaWSCilAtGqBVZ61v2B{VG=+ES6u4{6>OMO<S
zWglu-KMJcl@RKwl98g+zOpA6$(mPwc)O+1jzKjMq%^k`-OQ*u3^pHUtN&9G~i=1<9
z3w9okr~g|Gd(x8Iw7k(_8@ZJ}+#0tjs_~q%#(kGPjp+}vw>a!*_kPL;)@mV1H!Y!k
za@)oKEvC+p*Gt^E?`ws|=_MDgE9YU2xtr+7`8FzNa)G7GDG+eYGG3O?d|DcGsH)qz
zH@=<GZzr7RbEg*%&nBN&*wn}p<hgyF^6qG=9z~B$hJCi9VT{zrT6uA1W4_+fl6a-B
zjU+W2pY<a)KH#1jU;}-zQSv(7cadXk*z7-c&6n(fYdS`0zxf^>YC7XRKWcvbs{3#I
z=zWzv<&SOt>BzTNu3q)PMbo$bb7@cY3kO`e;+BC^2H!s3x$4%+p56B?+Opy?f6AhB
zFPyz98SHF-cj?0O9=o)feeI&_uKsfAd(V8mwCDF9z0_szy7ao~x7knr{s#Nrc`v@S
zebZN8Gj!9Bl1q2}owbjA!>Xq~_tlG5eDKS)RoA@Ec5FKMl%Jo}f9kTs&RR2c(fNMw
zNBBNZ^~L9HTlxnV<qOtaxaUjnyyJU649E5ComqI(JNGW!e$<vfe)|vieC_=|TYvYX
z$87zF-HW!|@~7wi%^$t}<9k2)r-$wR+O@0q{@F*5t9<%~m2*44-rPI)tJ2fgUVHA9
zcTOJul|Omp$Y1~4?*?0U{o;i``M|&Ubyq($u<qS=hE-QQ`p!Rp?~hkCe{k9HKl#?9
ztA2X%kB|T9@87ua*Y~{P*n8joNP6#VXTfPVEjy<AZwDN7+MAcW?zAUsSA6D+Z#bqg
zZMNpTv!8wc4ZnZT&p&bA^Y&b~kWbqz*o(b;<lmV!&;DrTHP73#_cc4qd%nN(w)OwM
zVdd5jF0XHWW|yCP?svkLM;B*%|LT;LJOAohSNhivt@_G8{)^x8xr2wU{N2&#JpIVq
z5BP`0zkS8Fci*^f&$kvXntSBM&AGAPzPfq)u651dA8UN&mxr|0owcm8<%&m+xb%ys
z9=Gn_PN{$9FQ32iGoSwE*k{gIkuAIXl*-Tlr0?Z#e5Sv8+N;ig&S!pb!q_Pdn!?v>
zd42eT(bheOZ`fR!yk_&31ylCQ)#IbDH|t#czOQy3I_;hQsuf51tKNRx&i9AP&ab@b
zxV`n0kK5b#xnnxpKkYl;e!<Y@!wwzV^M`j1O$>I9ojB+6OYNTzTNHl%1wXU?>P0hl
z<xq3g;^UgHde70NBYt^c>AjaNtUPDoQGcF&c4(&k_Xn10=N~h3#bIZaZa<^%=A}c&
z-@N3k|JA%_^;@r-ea_LRe6F_mlviD_xN_#`L6s5f+x)65*p?-GW!tN+GVZM|zt%sn
z-1%#U+~dct3_IW1U)gftk*l^GbJ21BqX%Et+5TMH^O8eLt>=|&=Wk9}HF0WxCERjs
z!#;RO(|`K~>t^1x#5Z4h;@0ND$E=!o>$8t5y{^B$^IPL<E4Qt^aHf3f+L>DyH)p=S
zB5T&pu+rO>EV%i(3!iu0yWR7f)iYM{^I^xH^5fxZ<*eb2m6Q5f%c^~^rk?%ir<j2l
z#!fl?(91_QUh|H{8(;sf`-l5KcK?#ekK69svvha)z^U16CcXLU>vz0+=b|0M8wb)b
zaJ)T!)$!YRf3~*0vwmTE(+jzqIA!VN{p@h9T{qP@w;ndX%iH*xql2rL?1s(9+9$3~
zI-^UDn93(E4Bwx)By9S#Bc|E)p3Z%3U^ZPh@SeWP=ty7R=!k#z=w0=LNAF74$hNho
zuu9!?Zr?<wuP?W2X6i>?J60cC*~WIW*$;c$`QgVyo8O_bOQyz`+{(iV?;A_QL1XpV
zl|$R_|3qe=#PQ{GE8{n;8SqDbzY)Io!N$~=URdA$4ZqIPwa41C-^G;m!ipVv$q@Ek
z9BS9J!gtrY;MV%-ENNsT>E?_%Yl>$sNAr=<(R`S2ercL}x?g%ivtwU6yk}iHn%698
zqzf!Nn!7Z~vo?O4`R(Lndg`PqgKa)Nv^js<)a8AvY+Jh0Ue9QDaxzeF9bHN{kMX!n
znGr2#J}=j&?s7FNyECU+ZXo4n8q(Lh)#=@iL43tphV*B-l;2-#I~Ur?0nL!DZMJ!a
zcw|(A>jEoVzn`-Hw4Ds*Z5AIpEN$+{7x3AYK0jb<zWE~V#J>l>Ic6Rdm0n>VvXyC@
zpU?BwU{(AI(^@%LBk|^ro(|3pWa)G@UBmp_GE=<6NKDDHz)M<O@U5M4On2^*^>&k6
zYvbJbAGfkU(aLpQ=4?-rset?rW0rLfmbfv*f~HJ7<958tgD!$(Z1Eyq>TEEPUrgBS
zcUXDj$!0g#kVpf|49-k7ZJ&6@>N6;%kAG&Z@eZ*u)2i2xRlzO4kb}c+rkt?lNV0I|
zg5&JVG>G-Ojq4S)q?~OVL)Y3YwIowo(q(~(44>BFH`1x$1`{OnD7?^@B_ZK##8Rt=
zz9TthcLi(#vVS-G-lf9K#pD0&&|tf)c_MO}Mu$_LbmUIgA$fN88Fpdk_@uR&wdpIC
za!GS&)@s~nj(GaO!Q{K#=bO(7Wn0k-p)YmQhg<0vEB#GN`HtcDaCJ7|ZP8Nq<|l6a
z>hC`Fot6J_?_2J+x#J#r(-Svt{q5ZkedH(iy=MEXUv=`YUVrB;Z~E=eA6ohA_ierL
z(kIS%<Sn1RW$PXHo_+GKAAa)2H$L{<hu-?(_iz6AEiZe^pFe%cjjw%FA6|Oo@xOS_
zxv&4&BS(GbC9nGBL(lyCuQq@7JumzDs;?e@%YVH26K8+nzDGCz=2Nfw`MqB|{{3%y
z)qBsm=Pi${y!Rj8eE0u);;2V{@h3N)d(Y1wy5znOzUCX3{?T)Pb;XZvImg?G-^R7$
z#vhtJegsPhtGB0dW~nr3rM@W(ljb_?@s~<7TCIiZT&HX!+}9fAb&S$f+1b~#PXBwU
zq{K=GuE{D{Xv}3-TfINQ2Me+a>$7#kkGS#9*|b<|EF0~2rH{<<)^0PqJInmUHG?*^
z&Klt|pE;UO3q8z;<=i%wpQ;{ir_WI{1GUC94{&mw<oB;i*^I#gT84l|pyYsyN9(qT
zA`*{csNHl^D58#A0M#F1o~f9Nr2p;!$Nwj~v+F+0Z+G4babcI?w%hI!n`X5bzrM7|
z(VS!CL2IO}09n6hliGN-Qkc0~=b0=`QyW^Ot*Jazr&EUhyfkFvBg$^BZCO7{VXwY|
z?N{+Fqa!QMF`jt_YAYwK`C0y^UeYe017eGP32VSk%F`U>u{5b^&Ao`iE<qQIMqhAR
z&UrgwX6ObwF3NPVYV9f;LM$GA5;Ar<c3F$0fk`W{wsvVc#r_&97jYRogDMp;RVK4s
z4RCKs7kFbq22CWMpS&rL^F2JHMWM5S?SmoYe8ob;0Z`RdwRdS>LPHe6qF<M86h<pD
zn-s=2Iaf*{SWwKF@2e@xMJb;gK@NtfTrvPNI;b=N_03h&7<NhdwIX>09sUkQaV6*A
z4~W+V35d=$4Is=Y8Uf$w+~!cUquJ`DD|mc<j*T=?Tke(pxX2@d9I5p+S2Tv6D!k`A
zxfH?c78*-|Bp9Q-l2JHUQqF^TmHWZeXkcHuiCoF|jl%FTrALPUDg?F1?|useUW?p9
z8ARV8Nrt3whOazLMy|*nla$GWlQci9z@`|_##8gy!aopfG|(PXOGjkO4cvEU8nRmC
z)1nzG&6#uA4(};T#v#pu%8d?}Fw2HKYp5(9D--kyN+}!5h5v|g9Yhf(oN<jFylmo@
zY?8(smxlJtsc_^}i^;Q&jY|{h1I2Q-j-M^U_`WO;6M?F1BHf4m#G9m=&nL@ud)G>?
z7y}#&oov00m&Q<ACFX-FRe7ZsAcF?gAUWtckb7SU1_>H>!I@d<4)ld+5j(h3;&vg#
zb9ARL($o{iAdge9SH0gSjsyX#$B98qq8QnGE7#P-<j6Y8oe~7NQl}@Tpl9CmJRHQ_
z4G}dL62@aEw{j>W%uOrFms)I&#vV<iO~PPt)}~)tUI7o}<UAU>A9HZTC1VCR380i8
z5>1uomM}6i_|c*410)VXt|Y6t*i$IzNt(HFN{ncWHWd({fAa-I67mile*9e(EuM%=
zsO_jqEUvJ1B>sSE$2-b{bNBI;kuvWB{Jum{j|rA?bfCePjayU7zSNoo?WKp{>%_yf
zYbrs6wk3Q+#szG|Na{t8y$IUz7!N#9G7*t1oM&|pn#^XQ!?_2E2Mbc#21_jJC%<%@
zA9lnn&sa@KGo%aw<haA>K(hF7;s7<~cF+NpHbhM!AgFF7KOo4bf%s+8x-cXXI00;e
zCPneEj-4sXr;*QEu_Hu3KQKw@ogc?J{PsNAI+YriR@lJ5l_A`V#&Dy2XE+MdG#bnz
zi%2a~o+XE(UHz`Z_(4-5Q-o4Gj=f8YGQ7jgi<)^gv>|W4ojb=)4=Q8N^PFwhq%Epy
z?`O!dAMURo>qmcyKQjtjv{(Gh^O25`GN3~o%R*n#rq4sWOCo8YYN6!eS8UQ{qy33v
z+APshe6k2txHcUQH)oiY3{0CRjmxjWX{1P6Y#z-{&?*B{RgT>(O3U9HN4Fg*H`usM
zFsXr3AnHudB`xfuzeC8#Ckt{>URu8_MF`;LOWCrW6H`hAly<XRr5KCIUpa;WdPUj@
zi(1TLgBrUV!AA6jxe(T?Hl{N99zXDjn=^SG!4GjeeY0-`Dwa>p2Xh<p@*<lyfLq$i
zrkrk0Q}{(H<TRjQyG>kQXVRgcQWL@36aqsDyHuR<ZC>ZZkCb|%c`HB$T8XV~$k1`R
zC@yOfM(s@7HBe`JP%j=+*?n25p>{>PD<zIJ;Ox(h4+L!BiO?(?DU;6gLaVndjIP24
z#up4mWqdy5!!H(AZ|UemVXe&Xf+M+E2l3P=F3$NW6{<l4uVZOS(?WIDNs*(AIy{Tt
zGGh1{BJ)#`U5#_PXm$#7qEEhP9y0<|$EeEB?U0sa4nhrun1ehKkbs8aG!YvgapXTj
z9C*N@!95~z#yb3k)w5k*S4L`~Q!Nu^LRU}8i<-m)Aj-6>tLO)O6H@}>kP%~JX8AL~
z9q}F<>7Xk9{{?=A%Khb4vZAyuX7!&A6ePM)#E~wCwm)CCSbS*^6j}-%wh5e%r&vZs
zLv(XNERORfhTSWCH?c-3LCG5NOg_PPG1`)+AlSDLYF%`7j}(L;H7~{w9f(wzqY+Zf
zd9GQ|qP^paeANXc-^(M$C9g8DPEy*KUSn?85s@3>(X<)^VzN$8NkQxJdg)chW>3Tw
zGDLlmH(rSOu-JnoF^RBL!#JiXMZoGXvV6=`zkmE(Xj+SOb!Pqha4-a2oD>{`o6!j4
z&;i+rw;w25ALC$8#q5ejhiHm2NMaocy^aO!?+fy8ii%KNH3y+xU&Vw)k}1z*g-w!U
zQ`@{UUR=n9ZW#(m_`Zh~XJ#%7k;Xyk6a+3F|IdRf%F$z_adFp+73Zj8uuJp*ndepT
zXnU^!t-{ZZL8cYSdL0Ug1u0PHI5P@HAgS6#&(wlQo9+=@L5UL3f}+Z9(qjGQpQqj<
zEq)q}YA!RvxtMh@&Khpo5)im}jE62-n)XrWc#p%%Fm$V>l#Qu5qSNW8pn)2gvre-s
zjB1vjlm#ZZXU|QbYC4JFdiACH6d)6A<y^2_BrB8HRI-G)3I|kJMtIHuO)EldHw6~$
zD#lC*%A3Eal~dG>8d?(80$#?G^C%pl^M;8D#7iCRKox17Xuj}Pq@mx~M2i`5j8bB#
z>^2Z(h4uIip}xq9$q7`UD0{sQ677m>I`e7N5ak)t%>ry})QG44`yKUP=|FG{w9k2t
zK#;ElK9*6_93?DZO18UrPcafgL3U1OuY(rwNRW%lCLn7zaUv=n%mUz}I@;8wbTugE
z3sMviP5^gcQ4{@U99$q*MOv312Mu&PD$yzL{lJ0iS#w0O3qHnq;m8*jl0bHA{*ew&
zvOmfT2VAQ3Tn7~?3nFWVqRlA7gfL-oVK1(tUI_IewxFL7V1(Y32cynKYu9N>8$O9-
ziqZ$2^{KQjI8U^U5{!1x##0W^bdtR4w?Y3^nOMgBH{eLuWAx6hNPsC}o>wG|db(QX
z#}CDQm&l15r~4vGuSBuDzOYMN45Y~c7#R!KJ$2iMI1#v@*r(eUG-^D=0(KKp0%38<
z5R2f*F4>nCeEr8feaw_d7nHC`IU)N<Dtw(|R{X|qbQ;W7WLn_FA`W?95Mtq2+bV_u
zUiq`awUhvaf&)#sU@RW>T$m?ql^DA#K+@$$RHp8O$pS4iNXe|ItRThu{fq{}9>ntZ
zBC*Kbh<qX&B;YOeoMOJ5rM2gGXrZSgh$peuygkxUh_W9moDlCtb1tA*OYSTT#aB>0
zG9=tLwn9?@$x9~m^o)Z?VF)Q}Y#A(`(i?9ys}hyW^A~lomy$Fg0FC*w6mhO-BNCt4
z0E>FMtaw5`_EVifdTqIobMulh&PG75j|b&5C4RB8DCEbw`n?4ToCFUa<B|3KO5g}x
zNT|c<0$0~B7HlpOypD+XrftR5e?NAD82jM0(!XCHbFjwuv14v2KI(x3Q7FJi+$j=`
zC!Q2zwPlq!R*R=V5%mu+9&wyjUr=!b%%cGX+u>CUCo#S_+X0Jj{l>oFz}wMtWWZT*
zg(BYqk8yM;BZqG1;m5hM$8U6v@YqR4^W`pVaWQY!G9;@KidXkQ1j<(6<FR{iy+UDs
z7sz`aq^~tE(k*|N>!r{YJ=oJgi+%MjQ@I1u<*-8yzni~4C9U?=-A$BKY`>nf>i42|
zcKt6#gznfCx(bj{A%ae*)mcH2?iT}M%%WV}{)zsGMA0xc@0KyT3sMwyE{c@I69FUD
zPrIVTBRd{K;`c?crH_~Aq$~ErDCaEfClQ@MT&&*EBKE$SOR@h9em+XM)do^u*eN>p
z#TL|c2`#LEUV-9(O>QbjxBakKjCH9U^VEBr?G{LD;g~FTK;%iIGK;2SrniA~oj}yC
zA_zos(hsZ-Iu@nzDIDT_R0&A!LY;y<kj45v>t+$U384x?JmQ}oqWCnS8+V`>TtI9G
zzTgEkp(>8Dk*>A^LC`ICuKC9lVwG~_nlZ-qKlmcToYGCbkJ%*z&f52g8B#=jK~}7Q
z?m}O;GI}XvR0m&pnlwYi)NLby#63Hxf@pUgnR#fy_lmJ)%yG(lWcCB%VZUe^CwvGJ
z2K1S*>p7>>_}-60_wmVH@f?5J>XJ)6L6pFeXLVydlT(9_xK|NU$D!!L&V$t12@*lD
z33`{W{(F!1M|@#(EFiQ(w&!=R?2u{f>kDeYX_JG%N1ffmM~c;9gUMfTyU?4>x>0@a
z3~-X@I<^uiI;ao=R~+#XJ4;NIgsyC4=%9G?p?1xR6oGTZih{&zC#~1i)aSv?V+Dd9
zZbwImV!eF4FO>Gu#=Owg)!jW=%4N>~VH~pa<A>7IXZP8_bt0r9eQF`j0L`MD&^03{
ziHjj)ZgyM?C?-&<F(XlwVaJsCKCkt(s($ZY07K$E2q1D4&?{2RMQfJeyP__p$)PnN
z$K=ePQ9h<s1MpEn0F#jpsUU%FUcGhIY}a2E?_p9^^zWglqljy5GGB%8d8wCt3Leq8
zo+wm6<DVxaBX@{K7T4hWmkoKhvDYM=wTKHgV4XGu=Yc_VeoX{1C4_EAOdFEw8m&_|
z*(p&*JOMVV4Ae;vv}Vu9r_dV<XhTC?zA_MCu!~5s=E-86vla_QnZ%j}Pb9yexoT`v
zF<#i!VqoecZ`E&l5@m**vj6%1(2Dn^(iw+>#HLhx$hbD~x;G1|O=QP8e89u=78rE2
z8m!KEh7FC(Jfh^O5$4DlaOpYCaXLglkga+*&d674@j62LdD<1v*TWd~+&qdu5J6k;
z5Ik)*iSz6R#nT2PKEZ@d%SP}a68dsa%DF;tX^nhSyAHlBU|rPowu-WimWk6A^$GPB
z@+-0}5P4>T0e6un{b&__BVLz6;tl}^U<c}yPVf(#8RO73K>B4|z>e$s8Q~IjQe2Y4
zgty3RB4W)Lqb*DQ3R=T9p6^KQoxU8m%ZK0@t?Rn096qE|*S)=j`e@sPomo2?owS7P
z6w0~HHn*jX0ws=iShm{kqIDgWtY+`7YTG)jMHAYCca}b=p%hu{Sctspcj=iH<7auw
zsYZ9T#*Hy!K(JK-qB)ytx5$q~_(y4Xyq$Ic8i+Tg9B`>wJMbYvbS|4=bYcD(r{31H
z2+}$z9VzO~26+0xIh;tG@1(c^ZpGu0)gxYNm=itz*I3R?X6V&?6Mdm++j(R{^d-EH
zD!n%|VDl3J)J@SVu1lRQz_wY^w-%*#AZ5^+GWC3}Rj(`bnVcVsu!=g%so!YVkmvU{
z;2qJVOfK%RmliQL@=#TC9qD25k*zpBj?^eVdP-|~@@`3uChTnhUTGu!4u{0`-bj^v
z*~_B*rQ}k}sLW;5TNrT`9&|Q@!bL1N$Cpy44TocRMWCM8HOZ*mKX8JLO?swN>TJz~
zHMyBq4%+oId%rbwTiPDnVRpj6pdAoKsS|c-rW0GSj#YGU*4N0bh3puguNex(`uSVj
z+c~1vooiQRA*oUsv3`%XrNQ~rc{;k1HBx^(>)Rn%aU0HY3(MK{=vZyFWJ}^LU1-4$
zBQPEa@}Q>g>c?T-8wbx!Cl+QQ90p@4E~`2kgrhYYHzI3x+QKvK8!H&UnE;)xRTCKT
zG{#t6OIKJe-Hl)NETuq<1L9?fNN^$PUv6jCe?h0d>mY;<H6L$ABh%$4hjB~na_R0T
z=>a@CqdqyLrIiZPvJtEKlTg?s_@$&jj0)dC@cKmjFeZ=HK9@P$+3(FCj&X;vV4k28
z;!kpf@9p`SuT}bL@`L3o;EBIceYwgdtFzVF8hcB!CJE1i^l}V;k<x<)XIVG`Kb&8C
zBiBT`7t|~qC>{lvX4VMR<XNF=$J=?yACheM0OX}9b;~SvJ$~p^`A*mgws11B!<gJR
z52W5Lz^Vg^{mCuw!V8@oKjr2xqJSq7c5fozF*_x+?6_%XcO19g_8xy`Y)FBu)7ddw
z+Qw$`Yh7Kltw(sPEcDj-Ba*!l{%-OOvF`2i<UHFv*l#~MsNZ(Kl*Bw*Npm*bMcZG)
z;}A7F3I2sk`|X=+Nss*ktgvHDeQ?ZXhiW!AP_s``N9{x4ycC-$zV;Y55`LGSX&)Q8
z*nV+LYHdCCcLhv7-%_IQkNTROo+kE|_a^q7W3%`b9=jdoO|2Jl+u$eoyv!y$c}Zd~
zT?u)#X`bIKOqvWB6X#KP%k5-r_+FOS=Z`7b-Z3-(8p^>hmZTGdwzO5^jdx34&`)`f
zu32Syjn{)H#|7x$SW5KTb(z5<OOCM12iGLyhpsVu0fWcsw4Vo6KW1g>ciUv29ZLP4
z)=wS3n)I)x9JlAzKf~A%7AJ@AI>CndvfRkh#AaWg(k$TL!6-MwZ&_2nFD9Hs{jTjF
zw+4RTN!K_&ul_Jinfe_isE^tkvp}&agtHIOckjr&tv;?{&Ep%EYx<;aQo;y)Jp-^g
z;RpK``cUfg=Czl-)Pl`&?hvfT?c!Sc)WZJYm-pMm07+gB`6NP1by%}Sl<6?~uRo+e
zRoe`hEnq0dhD`+OH?8s8UDR(@^znG<=f$ttdEVPoX}{gZM6*p_OL+m|(2Cg>&fKpU
z^(`I}8?!4HjM0Cg9l-7P12}IXJ@euQU#0&h@Wz<WSUsHV&7Y1RE>-_!4kw@OHpU~w
zV|EX9xaTlSyvCtRaT0#eXP!?+@;UIz3v1>G_Ivc(mmpKE@JxnQZnWd1&$bP&;a5tj
z-<P5LKth{x63U^^Z<{>P-jwidW9m15A-WGF{WPJSCoY^|hfFe8qzDWo_=0v!uy<6=
zb}}EpUqL_KXsK_|cN@=wcOdoKF#Ee2O}&%bi#iy24Eo+k+326v8MDuXmfcGp`D%6<
zkM+fKjIw(|<x;y$c!oZ)_4M6JAAaE*hPHx`V>jYu^YPK;Z_+<ohxezm6v@^T0Bs$s
z|BVvLOk9qB*?}L(z6T5a7@vRGWC79HQEv}Y|FQqlwc_3){@+Ob{*L<nr;&c!I5=eP
zL?#jVvHqxkT0i~M*^3TxHaf_Rp}~DUp;EL{OtmUDEKSDj5Ef6(Dt@S7#FZGs_$-r8
zqMWmY8yI^##QlLpv~W{7iLWM{O8x3usH8ry5JYnsn{SzupZbVUx72St)-O>+tX24-
z94_KJS>AR-x*J<^^4YI`trDuXAt*cA+X%KWw+Fmu@4yc`DG_zGtmEtr(6(Sli}a3l
zrt0@`{H^C<COp0E60RXnME3*%I3##m7QDY}wYSdE2(LjwQGaP3qKNu$vZc>kX`xR$
ze?Yz)pm)<tVq4;UtB*Ff9NWk%h`3pY0#v`5&_(c6zXiE_Y{mK!Z8yBfX$N5`k$L^z
z&J!<9?3)9L-*yxY>JZ9(B}5?gj`Tk6pKZg%?nsEV)uQj>;0Z_HRT!iH*1Q^|r;fem
zc*a*jPPiHVY8&%6kiNt3sKtJu`t#Hu>*X@&2?+-!QT-~!3t#%LR~w*ispEF9exDD2
zD?vO$InY0n3+*XLyD=|+4ah2ja~x=jK}Du4lr!$#mKmQ{8VfU+B}cZ7HJk$TOG5dN
zB^=NC>OsB~OnsGnQI5C(bO?3OL-KL*T{(^G={J?MQM5^}b1je!LH$!kW&}rw_h47U
zM{gGNb(zElj5#p%{J^Hyvp=jOX;}C*bDDpd?h|iq>i@M%Ym7T3>W}ouW$^mYy24tF
z+003d&jDw*52GQd{~{*PuEw2I<=yZ`SEP)8DUaP3JlVE{_1_C<Lx+vhj%XiFzQ4HO
z7x(M8kxPqDX~k(BO(@nJqWYUaKYe&568JqiX^3);cw?|;f+CP7{}DZmidx-QL$U@1
zm_UyTK_xh27mqJ#P1stDBxvpSA_9K0j$|BJ_1Uu$t{IAgV+Z7N!P9lXCCR2(fA1ri
z-cO8BR*$Y)pJ$HoC)jGzY|U6>;aQgy^?Mc_APo!$gxDUUQ80bN@b6<-J<v!?sV~Z`
za(A%3!x_Hn*r|aK;xnDNKTe*IQg|m)-nJg#N*nPTnz8>^E2*_yOk1UXQ|8~@yvNwV
z?9laFbdBGX@?0H?YRujEZUo~gUmSliK{k@y#<97YvwmhzEbuAaxEWi4Pu~6B+X1w(
zQ${yoCp^Yz>xWe_6i-;{RYMx19S@4aSF}Rzt7HKpKp?yx{z<8s(;RdVVVp2uzg#CF
zUhc!jw8r%;dQ^_8BLTtc%)fQMkBI_(*JdMys1w?-6sTME&#j5f!ni(^Df?*``9s)W
zPR8tgke0zHEJoMWRrpovk9B@0Pqw0eJ%%)pbKpOlHv7?sabJh`s0r322z(KCfZUyV
zJvWaT5E+l+xC5Gjt8Qlzou+PG1sqzC%zpe)BGakaU6Adi@K=DS|F(+#F3rKS@K2;q
zP8htnutFB-^ISjqR?I_V_ikwI!!TxJ*Yh4d$S@7r{S<oCF;b;N#r*0j*wHdvW=Bxk
zrCbANj`>#`CR-sYf6^z`!ly0j$0di5KK9?OoOwg8D2KX{k3P*;d6W^fjvOb%0Sh@`
z8HUWH9*m$dKy_RuiXD#njjs-=(o#YT`bxrP>PL7y_~Ze2<JwPjgmL6zdPSVQ5*cO#
zTgHBJUZssv7P}bxTLh1&cSx{Kl6uEDMfe%%r_Lcc(9}Wg+hYPj=V|#Kq$($hKn^IO
zTXOCc_48q5oOq6W#TR&X0VD%xyt<3C>M)2uL1Y^<MVAjkQ%_?Z=7~}Ok%z2rne*yf
zW)~8+$u~XlAcR3eTA<Xe%1t^2U%^I85_CwdBeb-E)01gI@I_fuMl+4ladS#(Ng5My
z>H)4QGSd2E9GP*>xrhSgAn-+K!PiR%j;M1C^&as$<!Ajs(0>G~Mlxw=5%snw9pL#}
zn6feB3@--wTR@o2?UWMq1pQjDv^cdKheAw>eGCv1>i0H&$Nr-QS1IOw?h~^xmd1S!
z(Mc8SR`v*0urZ3~2}!Z$r4JX41Quu-I7j1jW@s0me~Zl`r;UIE%J(zIl_-eEUqL==
zh=aSaL)TC<64v5@_7_qFB?Czgl-fYlXoEqE&T;S-L2WgVuLtjCrraD+$GItbF-DZc
zA5bjv6W;79>KF=(1&&^>E5Ly(y@#cZw+Q%4MaG5*4g<Y(Iif|Y&(%UxO>sVnb4(dl
zs~W|Tj0yq*zSn;<bhM#Ihse`~4CkU>>l_GsFfBN1bif7V5rbp?-Aw;|ok~SSPLodx
zkQC{atru35uM$&6Tclfc*ehWyKTT@h51@kH%V2U{giJc9-+8EkF@A}!fEm3k4ZAX;
zClZR%2?2V#;K#b@B~Y7}4Lt}&QG3y7z4-I#rPjyjL?Kj^O}OlsheAeOC$<AtBXKj@
z7yDOeNegjbl;4pPXwNK7#Ra5ENPD=>-AsZ@V)K%LSP;bW80m%Z@@#ONeH_E`K2WBh
z`FYHXS1c(+_KL_(!q1q~DnCFaG6|&7)5<o(zS>Ugwy?>T-sS9b_<nDHo&CwxmaQn;
zArs4Nrp9}pQ)4zd>ykTI`)}!A!!-l1-Z3|3moH0~ZCYmcPdb~v+1YXV8hc~1#&$0h
zzbw8rTf7U0&He1X93T0tkKu=<y!vrD`@oK}O;)YHQ)LgUW-nonWcSd3-Fnb~4L+Z*
z3RU34OTNgy+cND>*6bIIZMU*NS$clOM&WDUE;$qap_|}uO2uz4Nx62Q9F?u6{hV5Z
zH!iN;WG|wupG^5)Mn5kVQqIxSR#VR00{r^*o9v)4W}o-sZ-BqZ`cKR3rU_OH{(>~U
ze#{P<arXIq1AaI^`XOVlRerM8vNXNc*^&=9yE8xE-dH=o>xbwktG1dp0l)uxmmJUj
zW!#@!INJ5&1zh^zC;4Hz8u>3t*q<C?18M0}TXZ=u_fgKAa$fx)emW$vmoxqRB3)|j
zgSd#qPrAQw?!QsL_v42}3Cm7iWuZxSsB2zSW8y1Y08`Ld!>r9CqKuIm|5F#6AJ{xh
z(=0MJxh{YoXfQ#aYpTMgJqH8>sQBtYyK%MJq3br`*nh?6GthBFlUM{46|FK!NF(wE
zCR$cBTAErE<G_>y*%{k{#Sq_5{7}ciS<I%(&v<2R9{L=b%0*OTVkR|?VIa4T;@tuU
z?I&jwaeU}Uf0-Yau4u*A8xLSdkUW7ew->o;uVRHIj#DfKgFr?aCtIv9?Ycvy>B6XG
z*JDvui<iJ*a)hZ^x(Wy(OYA273MJWKhYP8NY06G>^2&RPPCE^gJXF8_AIWQEMBBCh
zzd_eU^ZI=cBmey&*+25%;Nica{Xa?nC6E87{C)y%9-p_YXiH(9Q6Rm#{V(MIDH{GK
zhUoKI{ojQCXWss%sD5iN?a9*DY3~XBcUGi8M(^--HOB2+F~<(jO?*=73M(enqbh|0
zRbt|koW0GEqL^kx155Ssu;9V3C&W&g#g-l08YDqr+-V6Z8Z~nCpg=sfIajQ?jWcT1
z34#zQkUh%Bv*(%=4K!X}tz<s*uv_o|tpSzX1{rf@d6^IeS-12S5Pr2(1N4<vL<)2B
zG18I<{xkyd-7+Jt>?dIHX9=NcfDEh>utok@Oo&EGxRGGEB{haVjSE9Z7HOjhe7znH
z%=iQ~-ilY;m~W&=tZ{Ej-;84Hc;I9GRE}Iw<WY`zO82f;RFXXQ-}+Z!YlCE5V(2D&
z9pWBVjF#$R1#1*)z+JHz(Dw)g$orx^38SZ+8Pkc1ZF(OOBZ4Hgxz>fkF8I`~lDH^?
z@vaciDWWBg6GQ|@`gn>5p@>J=s463ZI!m1B<VjYfi}^qjFK~*K+at2?5cNC7*=QnP
zSxGdvv0?$)QbrJfz+TOM#em|X9g@&1fCZ=x1H(oBL2Kq7L_ww+>c@#Dn<Eq=Ob?K1
z`%yrt?+A`#Odk)_FY{$&#M~klZBukS^Xk9fzLt7OQ3}v)qCxZ0(>~@O<6{oIForwJ
z$V*u9F+vxDXYO?LU*g*E17g|^2u<3@b+hieA~Rnuv*6%+f<OsEk+w)ol_4+i@yPU|
zbH8TD9w@_7l!__GiF#C(u~PZ?gae>cFJBKr-19v8d|A9Gv9~i6`F$BecHM-|O9>!7
zv@0jPMy_gy^A^DrpQg=%1Ed&RY!-BaY^9>RFe#E0{av=tc#2Q|Q7TJT6uGKAT_^?2
z(luhVK1zWqrHg6Ek*$@2{<Ehr?RyX^1R&_(UFw2FqYi$au?$h|u_#x0+9~s{23Ql)
zT_j~pWH2VC!7=9M80&dWzqmlSSvrEj8=%l7Uq}!SDKr4v@`eyCuu3(i3b5{2Q8){m
zGKgtmi);*%hm78IT8PXp(l|z6BIHS$IDj_AjFGH3iQWZ~y(KM9L6+%OlQ|#ThhviI
zCW9D9U>gL>_)@3iMzDt{AeqAer%I$Eyi`P>MXL{Gsrhke(x)*q6Yh~v$kps+KZ&J@
zLgKes_Vt<&cz+gOFxELlNFGHzC+5_ARx(xD<BN4F$ph=Fr_4Uhy=3($M4d45;;i(Z
z5XCHX6!T<2+(%BHkr8MCflLa>gU&8U)V$Xba7l6Y(Mcl2cu?bx!_*k@g6D=}X(Hb=
zCs>g-OB@oCnRFZgQp?;aS?xsFXOHNBiwDvaTWz$cxRjNk6Vnk=XsqKAB4X<ZT{LHv
z>!TN;;l)^@aee|;OIK0_w3cdWrV&D3)tSrj@j?`tAWBm?@TRwL!3-hrpGZf-_#YLE
zL)`b&IW7{=CK-=-Y|w80U8XgbMR^^%WevjX(BZgP7Ryz?f6L7mK=Ra$8&{>cphUi#
zaoMP?d?HB1al4rl=RDVn9O#)BEX-P<ozd!?he0Zzjm#n&xM#_!r1x}#!P5dGmc;X=
zl!3TO5aJ5U=NbFcN{w2YDRNfhVm3{sfKEjvPr{olDh6s`&Y0n257^6Jw?7{!ThUQ&
zkSZZrQ^Q*7vjZ#+ZS|-uUKTmz<{^$ATy$twD|(Y<-YIMPZ=TSzN+$)zQou2<sqLlB
zWt2;J)!f85O|9grizY<iJxRwABY9bA2S<A+xRcE|WDLf%Cq4$l7hY_u*q%89DGhel
zA<qW>1wm~kANKXw5b5D`|6yj+CQ0d9)mfU2T&0arZ`3h(aQVprZ9m45)UT%>@d}9}
z1$lNG#U=z#RqsYRGB|jz1o>?NF}bms6ayCI*!7LUaoD@!VKZnEGNyo%3$gLU%T#`_
zh98yk4DZF*jZRl|)hgOErxCgUGS`wO&nM%fJ&}HbFA~G@6f*WF3Wg|6%Hcl{S6BMH
z6Ny5{bRd^$coZ0EzZxztt_I(MHDf{L$<tze?GYobSB4rCYpIeHK(0f=swkwNv05*e
zoa2*kG>VvQmiv(Qrm57*_(Xn3Q*mrsu%xB=TRNkzY1Hf9H7aGG=catXA~!3-1sWFY
z-uJ_$d{(Db2l5M&j%n<`7Pu9-m&v5^QUv5BWi6-|+FgurfDW!`uV|o>Ns7u)WQ^d2
zAP8B$?LimEPAIh~r7=~pXi86MaW2L8z?_&p@C8D*jlhYwl=sgelD$PI;13xL^z_Ea
zzC%dCojK=3Q=|*(fc(!xWTnM0gf3W4yi%P5W0?knm<cVh$ct>fXkCc;4|c~TX#3mK
z!vl0eEKIa|20~X2BY(Ffk*2!4LU{`qspffcK^&<r9$Bv!Kt1eqLaF4!C6VsqG1W24
zQ^$!<v=r{lGdehgK<I(*A(5kG=oNU7UO9+FtBFU&;)_;yLb?z+#dts7Dri#GHI1xe
zzEwy*Vi0_c^bXw`s1!-W>w@ngJ&!S-l~_r1P%#hP7W2R9dLIC}s_O9nzPE4Jx66WW
zmj#Cy@yuirCL!V^u5rbvcZVTPHUWlp;kzWDk9EZ*1X%gTG)2^#Wu+^nGNwUef7lKf
zBq-u)15*Fgk%l(@>9<==TdG)B8!c8;N~zNN@B2CT%?9nazq9-9J@?#m&pqe<fA`(@
z#%p1rW_^O71{AD!b+8O9Wg-MUvt)fpV|6fE8fV*@LxG#mSe^iw97%tJqILJ@_bo99
zc63sB2BckrVnH)-7GKLn{WdsHXlI|bmQ1?;vA?zqEjR_Wd9TNQ%TaQ>2!4~Et)aWT
zE@)(Zod3Rq8UZ|)M(API(=sRg4P3KTr2(Iy#t7<sP$?G2GRNxB{u=_J{su&0Te>Vw
zEx%EM%9lj0-saaf4?kMlOh1onB#2#d|HrHl$`}LZES&2!i9*@C49M*|Um}S-(Bvp3
ziP}}=OrMybm{k$Px+W0SB=Ytr?d}LE12kohkhrPA*l(&j>4ra`)3vqNC_ubxjKd#7
z>|9$Jc(n{QTGRpdYGEqk#}|BYp~X{^nZ76mJ-x5sRri>mK~%Vobks%<xb}ZSZFr7%
ziK1(Utb~!tL~o)-I|@xA)kkUKX^CmJ<J41nnDur-f#ETR=B=4)x-_g3Ku^olZqZ^i
zP~3@LV=<Qr(&S2-M%ic{YMh3ga<dv~fFUC5^(w;0b4Yy&SmStbUIy9v5c#vt)H@BN
z>6sD*t>;_60uuQ!F@cij$WG<^O(;Fi3(fg<Y^(#PUWG`T-SCs7%wau^$Ut}Ag23_J
zu5v_L)F~^k7v0uL8QWnnl=2|zTB|M@n2JVd-X|CwiJ&EjOmykt!E@-y*8UMXpO#xQ
z=oZ|;1iuHL-uA$&6kQ!<N>qHTs#=Lo<R-i?;U^s*sSbw}NM|WN9A|x63qhdzcZ4%_
zee<LYykf+wErD^AeG*nw3c%fB&Y4U^QfjcezMCV<20>O#abCHeyVH-fsYs|Ra71Z(
z_|UePnQo$UAl=jM*H)XiS51uC3uxo9&STa%XHtZeX~9m%1HiFlrdSDk5W&;Sk{3#;
z3`=}u9K4pWI;`jrpN#_+jyAw78Ja1FJFInf0^A7(7(I{pcvTxvR>_iD)5J~%r<IF3
zO&=c!Btj=ZKh>@yfP&tVtDY24-T36{h{r_dM_9y!!^)8f>BINYyqjWBKMNQq+HUu9
z9|;0DRZ5dPb**kQu<n{M$pIt$S<EaeAB+4Fp$tU5vbtK9xy)WdYq&x$jolO9UX+P8
z<KXL;x4w%66?o7bI{l2!SmRa!tF*3{Kr==r4)Wu`dp?f{^tYjr1$i;00I#O<03&NI
zWp^1tSCmVDoyuqVQ`t+PxM)D*;PJSwK@DswS8QnUL#3Pmmd@>a7yJyws;?<Xs6>u9
z2_C37K>Vi>83H|vZkj6Sp<FZqvN5<zG8yzJB?4Z)%`l%7w5)@gsw#ThCVuoHM7!!n
zQ@HryOd($Rz5FbpvMA7S0;3(L4f@8Jit{%5d_6zJ5_FGy6BKV|qB5nIaId4*<=VZf
zQ$c@cicb)U-<rYI-Y@v9dn58OrRGWvJO_0Z9r$`{K=tjOAEU(x4{gtCz@2bFY*s${
zZ9n-9x>H=isZbAsYdxk;tk&BM6FjRkY6!2Or?+a!G$Orq+yaAYN(HNq7rn$sJFv7B
zjrWmD@ye)W-JYZ<icG#I`%-lt?eH#+7vMzu-;(U5DB}k$OR&HdawRf{3uC|c+L|g(
zL(u-0fv6~r9K}F~hPF?i^0o^t66@J?P-=tL<%>8!i&*CqM!_5tmGwzz`7YzL>gisg
z)%BQ%P~9st-2<UnH?&YS?2R>%BdmrAmv=<#LTjJb6_ln_^7@~^(b&ZsshXIm>3k{t
z7HcE4gvr8XSrC9wLC-+bEJ3h@kawn8)^95+m)S@S_dtGL873K>Br?SkT@gzn4gW#h
zM0L`;Jq4*FT32c=3#*GjO*e16?#ip@4s-{?k8?B%8(PBT$@FML3#w%-%2^|z&9jAX
zhFg5EB-6o<0p^R!l>xkdn#~GN(?)9h0}IA%{}L=ESkX-rSUotp1kj+M8tkU3uB$nX
z^v#XFNPg|{$T4?mjFNr>+GbI2o0aM_!MCCzK)mbaV~Yl0u_x$C=w{sULWKaAW&=}3
zBT3NKmjQ1nZ}B8`gkcpg1M9tU@48Ii6RmS5V<GR1U)N6Uft*U?du@cvMh|vo%4xW+
zU;nXf<q0c{wrf%g8L%>pibRQz&t%h9DM~){sg+0D%Th8li<f0HUQ=(WX)qgd_1##z
zK4W|_%d5_`oRya=w6)e~O@c(fvK3!ETF-CSGwqPwfDXR!%&99ZirTsB$Pu9y>MA(?
z7l?<bN-N^H6qKV~G@@Y-HZx6ezxs&yMHkUI=(!5;k_86QJ_0z<y2t!<046$Scs>GJ
zIzH1XvK3d*Nb-t&04u{D9bu#$q;OC;3k2R<AS$e7^R5y`3CHopBtcSaBdjm`iOv5u
zeUkLY-V!2V<X_94kvYS~mP2%5%e}0M&FH~o$6GuqK=^5GRI`SBGkuddZ*|VKl!G#`
zC9W%6^s{PDA~VXzC0<o;yGB9qBJ>W$Xg)x!p4Q_PG~XPh;20t@h`i^_uzRi)RX%Kz
z#lfJe;pqjSi1o+`hgPPP0J-|F7F6(-viB%zSszKr>*L6S>jbnrlaLSj`Akp5Eg{Y$
zD%<BJZM}3)hCI1&Eq~hTybz_fL2pvEY}%0Zo24<0w4xgNO*}?!zZDK=5c(Do>zhKL
z{6YzrWOj&RS1M7#GVHQGDP%^6Wk`Y&*_RD98^<YNUrw|MjSNkJp;NMu*EU<iX-1?3
zNMs|Ad26iB<$@LZ&NcZl_Defjb2BS6jx+THzVI`UpqfwOu3U4#&NugWipkq~8*k+n
zOX8Lub1B&*PS(aQ4x0)02Ch?67u`G$C1#z88+`iT1tJof4>FhLiIfKGFT#dwU7fxr
z^hRcovSIsTAkd~Q<U1_1C$tzT7vloBf-SqA^Nce+WxbD5T7zz73mpQQEn<*oy@3o|
zrAoPl@kv-gKRDR;STMr_{<9}G;J&YeQb3UcPok4yn$A$%5L0ZGdUE=uXDdn6u(n*F
zmgoBWqA&`R`8c0El8!PM@?rMgaKLpBEiX&GMtjDbQR8+<Z)2ikTuif?*h;b>GL)Q~
z=iyGhs2|&9PS!#<A@eggTXo)di8-fI5>@~Fa123JBdugvJ?K4Za$}7+Uc1m^_;Ip=
z**9E>k7CDs+F!2djsb=~MQfcu8uALgSZwJ{ZZ%>X1%xNL@R9Z2XsydTUat*1tTs>5
zrNWzHcSb6-@K!CRu%k7uwI9|v3YyyEdr)UTWxb{|Cp}@p{`;YNw-?2;gH$94-9TVh
zTUt9pbD}@`)@kE<93-Siu{?D+%m^!z^l05`Lk^@)yR%_Dqy>)hWsB}=gqRK?6QCrG
zQb(NnA(V<`lyvBqq%nnKjl(GBVu8lIACySXxV3rE_7{DhO~P(za^x~eLuA>c6%VbQ
zTGO4IF>Ef8QyqF*HgbUaymYG$^UI12eMQC0*b<G_=CvZa(_~wP`^U7nXu^8w*172<
z$y1&twdR!rb6*y!2sxcLNqSz?Yifr~Q*<XPu#LM0%83;nGWmpAo<f{M-*xF{%E$}K
zlhe{;8}{5pcmc<;jHv`VEF-xX_S(Rdn<lRD$p^~HpGZ%d`O{@FrHJqBH$XHWcG$<~
zjrr`YwA9(+H21&b`}<d}e%oauN&3P{;s#chj-6R7mCraYNxMf92fnaOWboA!3GZ|!
z3xC`!9qTFb?C<=X^bY4*{UVdy;oAF8uH_D#yg9Z#p;UXq!F#$l$MeA!>htEP-gElk
z@zMpgd2_X`_v8nsd%iZ{;xlUdOXt_7d&UMAN4}mkO8Ke%CO@@nWOSevzj4~FIcMko
zHL`PT^Y(_U-ZK8(+YYY%+Bs*feKvl5GPODwf23!9@uzd;ftyxusXu&m_*i9ReQ~ts
zWzqagy2qdGp0Cw=_C=MR4bf*_BI9cBo(CBnZtY)w_e=9f>tDL6`)_~utktt0e9Q9I
zXDiD~pSdb6ec`I<=9xc^)7SnVBX67-YQ3sZI)261hYo+?>q&HB^_2@F)w~_(7^)9+
zB){5P*!ZiUu<@%~Iu2dVRXyo~jn$Jb8mz`!mRHS|<>?;{Ozrxk)2FH@nN?#a1sjf!
z&g^_<+1Gcady=({8#<>B*S>qx;cfrE^LY3w`%HNDw5xr7^4PKurAMwgH5q$*VeH^n
zf4X+Xoj<L;a_h^-<))WU{?|z_8@ug=>&BnF;MB{1amC9nf26y7EIlJx-nxFp71Qr{
z*%eLusmte+yT|vuv}@eHwyUQ0mJic<|M~@&Prv8|cP?C3$dCQ!ME;9?=jB@YH^q}(
ztA^5W)sXyuG=h)y#H}+!Nw2FU&EJ2d^whPF3`JpQU((fCwwDHR{nFu~Uzmx~lNW?T
zTTeQ#bUD}9dFRE|^M*_3TYP(7Z)^0_n~rVkyXnZ5{NRz1d^8z;z5Y~X-_}-PAgz~@
z+~L|&=J5Dp?f9ropBXKWyPm&G_t)P%IX02*I(9?y?1tM0P4ifFt(<a6S<bv<=+KsR
zdrsNDZqLE)tIgpLUO8a9`{PH}mABfn%GLB0V&~0#(yTY4>FcA~)b9+8FQ*kJAHm*}
z*CmVJ3TmxyS90#PCfB%K7$>HN%73*vSy(eNRDWSlzW%Ni-FCEEYW&&1lp25X-Ez8n
zM7CDavLpqWUR+VG-;f`&QP=WkE{b}OUo;#)-t{J#-fZozZj(+9ca&{s$3SCbIGwDl
znA*jaZVszYmFl|=?%0$Zwq28^a@usYV|rkJ|BCADXvgwJx!6jY+ta);h?`S=8;_m(
z*82UOZ>v6e+FR;7&p&H?vHqgz#jbKL{X=tk>zcvkTVJ#xX+E!SeEjYCT>YAS?x{2T
z>UH*)(zhQRs9)X8HDAD5<rAqiUThgJVo}@6pWPzmTYI_}?hX6w>k6iE*7r+K1>cS3
z=e6?mg<Hz@%a!u<no#OLG(+|))zUK^`Jv+-SC%fXT*-TSg`_$>67TBXJY+98FK%t^
zh>wKl4IK+By^F!Htp_~zmDk(DYZwn1vXXFkDyoc5M&YO|?g`dDwdWG*qHdZK_4=`G
z$>6b({N&&jZyq>&aygb8*?X>7S=?SqY{#yo_ljM)jpsivPG2TtwH51Xt=)OEc%j+4
zxNb19E6jNFjmFNuPNLr2`42NzjXx>a{m;f6X3s7;(3#9X5DXnYB{-D4r?crUtCo{;
zIvqum>8>6-pY~LfdVEe^PCh%|sO1mXnw-J9VE#y4X_{?sDuq45t7bN7jF?i%1Ve{{
zaA={MW3uDtCCQfaOB36|@>CoTmAFSbRFd9OQtdqyN2SL$bDE&%^|5*V#pa{keQSr}
zu(W4&B58dc?^y-W(Vo{!(!FA1E}7ow;-T6?_v-O9?jL%1Aec^~e0`yN#pO}&zNyk1
z7pk_))N4Iu+q*np*TGor`$xtl-jqxl%qc8L;=#snu5q$W%m*3x>oPZxr1RKUPDi5o
z1$$lKf*nCUmNQzh%q`S7Z;MU)mZeE+WYv&kJDjya`B2i4d&1hBtBvGb&gQ~1x^m^%
z<{qxt_z*u?l;eO(EH8}@nXN+yg6fc6e;GedG#(FKd2#$vvCH>-kZ(xLb(`;2SfCXy
zj>>0TnH);XC1>k)A-FtEbJk8-6F+5FZ=DaW96vrFvva1zamtB=@0eb0Kgsmv%;M!O
zV?KNh>#L`OIrG%8YcOG%5A#Ds7n{H>RQeJ}ecYWoW6wWSK6t(~tHaVr;k9-s;WEQ1
z4aahX&`Nf;!HLfK3)lvoj~LJgDi+gf#=NyA=Jh4`cu#0liZU9MlDZw5gUuvKEV(2u
z!_Vs*rTPAP>@K$`LtO6S-rnh{o0|1PeXjOab70$ayyx{&k8hM(vv%cV{Me52!t&vb
z<)qIXNagZ9+hpJsoHb*GS&GTJHb&cYgrj_dn{2eW|0d!56CEaL)k>ym`Skd(D?^r6
zP-?V5jMYU5vvzg$pdIF*a7!At9&xXdV3#|?wsc8jS{4=yQs)H}t<Op=H%DAtx9hOO
zG+5ENIpPzR9+)RdEh&pl+!!muq~3JpH0Ol<*t!|uy@wv@PvS-)$dTU0qr+^kkFe0U
zW;{u4ElH!J%;lzIO5$mW+^8d88GF_YB_*0cH!ap)ye7(->F8ilmEx6zhA}Um04v(W
z9EtM|S=ejbF?35!<e~~;;xX4%?@4rpy3ZNoEOZ-EX8o-B#EMP%gi4^xGKxi1CE_b^
z!o#8{NnEdOIetRvDpsr|3E-kBhPH=T8|qHIt^`R|k6RY`GzX0-)sb0>#T*S~AEFw2
zgt9V`vnDd*wq{)md3#NZ^pr76TbTH9q}USX=Ab$fMxr<(Q6v5_Ww8F28nk6~4L1Sk
z;=uG`b;$h!>r?_|z2D{usmdW3&w|BBkIM#~*sZ{k_T`ibAgx}yRt}XS&Y!J>YPn9t
zYeJh~n!ug<nCG0Ooj&eoLqSeHi&D`FqK;at1mOUv_}ivTe|015Br?z=_1sz@Lsip9
zZS7m502}$v6FYsTi~vS0;<FMXt)^EH<g@lSu1vtfWATZj!IB<floe}DO&|F<^nfEv
zuewosS`K^Zx!%T9Bk5`C66f!@*q?z%xtGcz)o8CnuPS0;Yy{jps!=7M4<x{qHTnRT
z-uKH-|9td5^VpgP??n75wB4uweEXmM^jkabc=DU~?B4vDZ;gE8PrmW-pZ?A@gugd>
z^kc`a``R5le)Qz_pWpGTcM<;V*p9D#Xv;m57vJ}-C$IV0=r_Lbwl!b-_Q*ZQFTU^C
zkIw$(_HX`V_nM!6`?`CMZ~wvNUpo7aZ~Xe+cb@&w@9g;Wu5W&P>`QBYIr7bqjDGgl
z|7*vCySM!4(#t+`$H+JD-FDwY|7*t`*KT=m_x6AN*2vdBzwN%CzT@oE-gVK(N4Na&
z7uS95SKIHKyzJMP{QCNj-|+UI?B4P8<G*^z?zjKh74N$K)7yUjlU-|`{-+(+PX6wF
zWAC{B)7yXklXtFp`tciI{`jIXmwbZXK>5k;v!6z{^gW?z?V}j91c3ShhAP6m*dI{o
z`J>GFDUI25P_$=M*f$J(;hApIBo**U-Y*V_{0{G9<3n*BR0REJ0WaweVjIF6^8B9K
z)>_kwY7{_9JbNAS!y9qEoEVI<mUSU=PVR0$L*$Morh#t>%tVzlGCh(Cwcfm_%e43s
zn(j$UFYiHK%e&m^ON_hVT+^!dvp^%86?vof?)fzpyOl1uReTe1WUU+U3Jd|b;Mn7p
zQ{oa3rLhVbH;C0x8+3018%{vs1lC5DQftt*X%4^H#wiyXJH_<hAj{1uRn+-^Rcp)3
z7&8{HEWb!@I(N1SD%fg?7rmY(v#HT)V5Q7z#-@3y;WK8Gc~uDOjWPT2`h#$hrEZ~B
zO#CSmksi2`3;JH{NVGe4Qb*hcm#zBLp$?R2({QAPqQKxH9LywK&j`t|X)p)rFm05J
z=lM>AZ_{M<F};gw%N!<U)t&r8|KaL5(18k0)3sh-f{2+nv>n3D|3F;OROsLEC&9f8
z&&9Ti+F`oPeiJ47Z9_k`Dy!jryE<VNVJ$q7VRj&tC!bJr=Xec5LNGrG&;f`}G(24w
zc3E}DlvGWm^kYpR!{hXysDTXOKx`mzl7xMNpx}R~L{&*Zv6}^w#*utT_)d!t#r<{T
z=4YVqC0ygPVf(?Y=8+nH{!+AVJvhUwy5gijw1t951-oA{dm`+V=z(&?6dJk91X|S>
zbDslS$&z_C$O&hDyxHImnec;HLU2^^IAjXuM_|non`r|g&}h(A|K6G>D}P|UimImL
zvKDN~788P&y9_e~vY872&A3bT(NKy6$~wnx8DuL04SL<Xmg@2<g&It0%bY)NCuABY
zPC<WMTJsA?XYmJ(Sb-}vw%E-YiNt--lU&7EooDqqm#C^`o+*f)VsC5PU@6s)0G+c?
z3kMxpHvtxc;Ljy?0G#wh;*@lUmv3Xj^e<IU3vd;I5*f`!Ocdfd?UxNJ#F1ZUq%rUk
zZH~UJ^KwDfl{>nKYR`U}p0ZZB%e!7TkNN&%u$$Z!k^nher10RpJEp}51i6MFDr{+h
zv079q67fw-R8drIki_EiI}219HG;G@piqI6WDLuq6o1T*e6?9O$kCS%s|dx)yeX>^
z>DTSVN<~1<YFL_ZwH!M5X~D+E&WJ{2qP1Vb>%rnWF2;fVssJcmR=kH3I*a3js#Vfs
zEJytl-==ji0c@cCmbfHjc>@yDfQzJRfHPlMEWz>bgxvWddby3AhW+pzk<Jw<UVV@|
zs%q7BqpmlgoZ!)M4@e@16zfoxLyP;h!(*<cUYu_&p2rU3(Lp29N0DX3uu6v(!YzuC
z4StEViUZbk;MR!uy$L*!b~1*ws<BurP&LI7$|$SoivHZIWD6yY3{{Z6<p`G=?Tk+L
zOc1&^3NRsiDbyH~gL1%GjYu{Fmx2Vy7RZ};fW>?03Vw`C6B}!#^kWVgxJiMHuv);#
zA^urJUfFA=0!g~8nsxx$Eku`&3}~E(7G)rhV3Q+gO>c{BRUL!Ux(1mGRBG-rvuFY&
zSj^&@HELe3FL&+t2-i;QUoE#ZWYLTffYcv9#m-QmEWwi9$ka5d>|Tw~3I*V|SvPbl
zK)W_zz3UxkA}>f|+kp8_Q78UBhditXLv=g|Qe=?<&r!#b=Hs}?I`f185NR^X80Mx*
zclyhHq4Gcn2_0>uY2yMm6g2gzDgd84se(44!$?*HgV2wK5p;%CeaPZMOB}M0Z_Rm`
z)GR>L$T}xUy}|Skp4DWy&z;5)q8t{Q&>CV0sn?d0p|n&bW-x#(EnEfdL?&#D^QnY#
z;18p<DYk+BBGrZuXxAyDJN4??3`%OYWjNExnOUo>P$zx={rW}l)9@Tby%_Q7znWXX
z_)ni@WuX06v{wf-AB)6j2J>ies>{L*25LI?z>a8cC=FOfk7yW89f3G7M}&O^)-AC4
zOATl$b67N%cpVfY6YvdCV;w9F-@gM3sue@$b9P!govm_g4Dy^|4-P}EN-UT;MDP=v
zl(p6;&mp*PcD^k4(rNb6%91*J=j20Vg%>*Y4U;f3d)>uLg;}p6*6G{;h<-d|MPgV&
zTT|+fno>|D%uI_%AXezVLf(?hV4W7j3}dILDkUl)@_Jk51BhL9mAAmvO!%VkaScJX
zM((~9;T8c-DPsezkV4pn7{D=Pw&L?KDw#@65Fb!tldCJGyYbx-vz{@AGR}${&9K`7
z3FE`8DrjVb<M-}wR9QXxmW_4hGz*;=NI_r9Na0K*5FB-anl3WpEO~Y?NX0IheVuKl
zk03iQ-Zs~lq;Sv9q*^L47U;SM&A@HoqnGi7U8Jr{0H<x33Va0akOW5SL?Xo)QRXa5
zKc8*2W%x)>$?2W46@NctgzS#$0KQeM)zkrTh{Ns{C7(2BkO7VT?Zq4LENag=D&Qc2
zVH4UYI8cOUD%@yMW0h*$><n2+oyR%|788*qD5ay8XPOd6WX)oN%tPs+Wht<THMZd~
zo)i)83Q-wT7HAV@ENtFPYZTT1x_*i%sE57Kq+e>t;gewD%WKldHq|0ysaxGH12JXI
zi}%;~jb6*b!}8(4K|Q5+2<(*9nE!kRa|T2hW*8F!fyw+fNETd1`B0jc@;C4}Pfe|Q
zl$3F97)L`|3H)@homJc_&7q(Na0T%$j#YGeDU|sRb#)oiR>QVqlMsYBtuqRSkP|)2
z<g}hViMX(dgH+F`5>!t-2gz&MrLhGQX}BrGqbH~dGNqhfvp^?_V*s#JvG#vYiQwUC
zL)!Kw>v4!-ba4<ZZ8g)K$xus%h<&Pr3Q|ygJW_45^_XH_y8)0bU+3&PWwF|Blq?~R
z7lEF@QsI<7=E;JaOX*l<FPMe^ty>c=g;b9sVV|CCt?_I824se_Ob^saGt`M@A7_bG
z0R(BSTCj%oG8)QJ^;94B_Xsu=H~>u(($-vt8jx0&iN*qc(PtS7ftIN2g<E`8)q?nH
z9d6eTw03%{x&Q))Gl|$T!w(~;39Y8oa|>P<6wsla#c{y*a)+&0Vj(1=KH&4lU((AT
znb7PkNoisMa#U8EkG2rU9aq8+LFbMW2|+ysCKTdABK+)1Es15^47CxaUSnojD_T*2
zGlFu8nQSfMF|^?;XsI!;xz~rYT#6Rv3~Z(l!Fo$6AWLpd5z(Mwk6U#&!y3?XF=ijS
zsa~Njjx`x!51LG22tG>Gvx`QGb`O-}U+}Zr!R%H8*;;vCTcSjnmVmm|tWA&+urW&8
zxXVaBQWTHK5m-_|@#jFb)l9{c2xQC}LO(wsfOZM`S=LNS=JFu8S?gN*Fpp9yTnZ)Y
zz04_Pb`a2d%0Tew7v2oetN?kE-!@~Z$7IZHwOCUqJkaEP4I`{Bw1u!W%d`|rv~!vs
zd1;|3Fr{ahQ}K0wQ>c*xsgKk;d=4CKT?o=20Ibc17Q|&TR73%eK&<k0I0peJGTUnQ
z;zK1W(wgC{>TTLK3q!3&i#iJ8U7M=?f=sLNlAZL$4h6BIrilLQD9JxiQ6)@})ddz>
zQECWJyWd5jCa_9X-Rj~I^eOgOB3u@<>NPE?%al?ZG(!nUiwNb-EbmldJ<8&&mPDXv
z#0OsVJuPoH0zz|$c#~f$EGP&uoucbb3)QLH%wCYM>sX?|pmO{3J%%O1l*wD)jMF5x
zIH}e%pl#GkP|umW)Z>F;*=xbRECv=ui3oMP-OrU_Ru{!Az0eMaI&gtmgb#?zQRZ9k
zIZ|3Q6k@y(rTT;|4p2D)16;glY)!_c87)DDWHvOK*c%O<+Y&7c1J%n>PobiOo~G(2
z+=MI1Cz4E?ka|@yW;m0tsAX>kIS!hFjtwDOmVj^-y&H>`CwwNV+ye7vFqdTx8S4dt
zsc@AQF}D^G6lk4FOT%HGpRE-o6~lR5F;RhD5!Kp{QxF|E>)BS8|0Y6ejpomyOO+Vb
zskuD`SSa*WuK#$oV(q#F2^8gSl_tQSwN7J=@6RN!`H(7;rSSK>(85KQEvQv9Ryo2B
z(Hz_PGh7u3s@7g}#w}G`S-VX?vQ0=c#A8@!+K_BD3}A8{PZU=OeX<!4T_mXzrXPoG
zn?@FIeYvrDLe`=k(&1QR)b|}O&qwhH62`hRh&4UFjEtmMu7t2(JGFLZ1uNX++di;>
z^^nkKx^&18jZ=u?nM9l(z)oyh<Kx-XsvjbKK91%Y!mh>{UCIor5BM-TT9qs91(4oE
zdFED=gW@8}SkAH<Q@NfQ8pW#VwP*-9b&I|(Kkz&XgW-nvkzJF<Wr+^5yp-v;z-FNo
z6Zv!6QtLJ_P8C88AXFzyP0={!Narcp4k@V3f|;V==%wkGpw&hq=*kml>v4uVDPYbK
z_8{H_CqCfsQWUG0K=XHPH5##N31P;Hb~0uVI-eC^X}-EF$~x}id@D`LagSPIy;c^C
zC_FYHP$!^V5ie?~F2{s{K?MgS(MDiG!SReH-lYUss+phlX;n^nD_p{jP05Ef2a}Aq
zm8N$iA|wYyJJp8jr5*vP6GL&FXl5Gedx)jcBhfr{EhL?Pl)nSJ6})a)zf~ia!aBn)
z<;lHO?6k<4cST)n(?-ELO;GNxR1X~k!-_BmSmgxKT2W6yH-tTqHRm0DLHMxq?sJR=
z(d~S-ar5uv1W&<=_X4~COg92R%gPmi_>>yZDB3Jx|1@3;ZAk-Yo_#jsro5<h@BmpJ
ztm*K~GzJCj!=i|en>O@Z<Za2Jsbq!jxao&M0jEC;8N=xZUBU{^>+1!v%Sc)jb1DU=
z4gL7OkZCHJuMyTNQ8NAON`Z?9j?j2W!@%mnk_Mq!NXOtm+oE(4%~sbaWkOmW>hVW}
zGAlJJmnJGgcF+Nv-4bQ|p5k!PL%}%)RXig;-YQ9j)j&MVFaj%RIg3ZYX$}}ox{A-)
zk#UIQ!9s7(B1<)Fy}Brm1V`d53(t+CbcKB8c~^S@btPE<3jo#FwtYM;%*+Z=Uet#H
zRGGY|DA1|)8RQAI?gx!zR>R_Z1^etvYuP?qP#KQRiRT1ZNPd!0^;nb=w;FLlmucW-
z&qlOgLRVne2(^uMW<hQkMm(kiXES+Vfjxy+Wl=3W$CYxfJpi>nM14S0uw0^ETQYg2
zkg(AY!eY(doEYE#vwiC}e>4NKWB|GVR-1sQIrS8R)M~B@mP^-K3b&|ZtxsMGG%8gk
zTm%_#-1=FM{iYLYAZ)SS7#iE}d{kcBC%S4HJQ13?e*on5hs-)eKSb=SCTt3gRha>&
zB&(QjJ#EE&I4fnF;nF5Czj>Z4tnLZSl0d9e9U|xoWbd`|TrCbGS@BJ$o#pRyCxULC
zRlWFp{o%n3n0<xROme)Zz?WhhkORK3-lOZhOf0%P#kHP=!e|)L)G30<Rn#o8D8LtZ
z+gecHdzI`(z~r3r@iAk=S~Ay)0({l@PPKqXW$;D%fXefmR;bYxG95=qw<s&mG8j*C
z(j><Eco4v~^EUB}KGM?s#rXI&ZCwNsVkGn{MrR3yfpX{?N`WpeCra|fM<x-~BGQGH
z)csWzfgTL4s=E$77S*BJY>x7p&nm_1MBWry%xK5!To^atBg(kCCLGSPbNe(Lb>U{Z
zimgvc<g3PJER=A>tqi%r37-~}aRR#|L^{h>_F{(WxT5iv{dcEvMtb;t0s-X-y%Xz`
z8zWkeyR|Bw1BZ0Gw6=l_v!9l;+g@gRXjX6>mkF(f1tc3!3AC7^@N6tu<2L~O7A2hG
zaBCB@ew?%>gwm%HK-AT+>h7{}6g1N6@%0&`)SVWumXVD-Ylk(3Y#5!@2Mi`GsQ^<_
z7QSU5fvDIvq==m)b!2N%9XyLl4QfREybEa}zD}S?H4m-dq(4<6fUi*ZZqhMmQ2|`C
zqEudR8ifTx4Z?!24{ZVGbS&;m9k^r(t>~2aTM*PV(kZP8l3$CHiSb@jLs`5RN)+QG
z6yGMyGcAqvV0AfLHpvq$ucKMe_e5Op(TB?n@~!^+pAa=EvGY>wv(`LZ=B72Cr@7Ig
zfkSq_v#*r8pplpzLw2Cw@+Fh;Bz~1FhSY2H$~kLTPRx=tG(*jZ<sQEn=gj+L4^usR
z9^kedxgStnVUIIwdJ=E*`kL!81&J0%_uCHE0<K&xg#B)^LtADdGRz~vkjyGm^JcG^
zF>mc5oXmvb2=|)l-Hgqqx39oK&TTU!5NA&@bY%*m!YY5OxW33C>FzKe@uQYus9#tM
z^G41wTW9PmQtJlIe8H}*7~$QuWX#ef%}El5YK5--O{X=tl4HJJ=b*??%SGGd?6lqt
zYjJ<t$vYgK1NNgV4LhR#rqiQqmvGx{hALr7`jgj+@S;q}{P;w1q!sp6#l4x@XYAmY
zBc*>(;^2Ig<8-1kwv|uz$ZT)iDg<)0FvcOQ{6ILfyqL0f{jTX8<F1LbiuFT@TR9LX
z=QGYFV~eKQpr9AEF27&Xj&{;x_7v@q1mb$l<pbBsv0e=~I|-*#%Lb(EU6-_YMinJb
zl%uFL-#T5}%egWieW}G-!TRpn)y=rk(k5k_3{RFdvdq|qbrpt@;kd;i?V|a|bT0BY
z_l((<is{PfyI$}Hrcvo4EzM2q(4^3NLNoKHEDQ3fVGYu%bR|vKXZfwkk}a6Jvm>dQ
zam!30m~duwI3dY2BN=ZvF>;G7*#3B+%QfvXq0_Aywa%KWW<x0yR@$wtcr+Il^Q(km
zm%dh_-gZiO2@^z+a6~+<%Xrva7Rf+IloZh3cC6fG)^Z?prqeb{E5}=h%8?mmKD#+O
z_vp!8lucTb%YuHotDTAYoj4a+>VAzh%hef)*qu&kQE@J1Ox#HyiDg$EwR(1T26oD<
znrb~Uw$YrLjr;pn=FOL#3`xu(s^9N3cb~M5efcXbH)OnwX)H&)Y4aRV=G+DSCv8Rf
zDSap8?#-0mEq&3^uIAK%E}1%Z^7h1Xwcfw3bnFx<Ep%^BTqoiF^|Ek!xiDt7kIMa9
zMs3%68GGLP!c(1RY%51+Y^(Ro6sukR#e-d|-|$q_x2@jQzo8oT4-(!s-?_R{59{lz
zU40u4eq^<sFRrdlhs*k>!&CcPh1Da6W%Wq0=ZsL|Wv9F1%BlUba;g~j^*2vGqyLdr
zgF9|Hr#MwUySpx2Gq(;-z5gS{(%{L#IJEKa-a1(P8rR*cSC2Pe(!FQm){T=Bw+<fs
zVg4nx=E~JIJF|T4#3O@6*VBEI+WQB8&k?p;bAtz7u)Tg@=nF%4p7yD!_n-5ko%1u-
z-1yizTlUPo=4E>xJL^C8G{W1qnPtDfZQzglmOb;4Ke_SXrVsqrGtd9k+mrX+__AjB
z({rPab4LIEl;3^LhWB1JI(y+id}`<OUbQFs@*9SVGjG^4x#gn%C+~jc$o{{-cH;gG
zn<sW&|H5}ZeD{iTn%iFb&S&<$@SWrTdik;kZoTlj$=z?9xO~-%Pk;Qz?Kl2-P4&X#
zZ~x_uvnPH0%(dGt8aZ(L^+ON;{6*8B|8V!NZ~xP#3vc<GU8^^}{i5+33n%Sa`1bWT
zJ$2Uw8=rmSRp}F(&PiuJaKrC*-(@d<&*$HH)7<T^xyk+E>!zI9Us8L&atF((br<ZK
z>pE>{Zl&0{c;om?p;<os{zu1`zxct#obu?<fek0+8n;eQCkMvrN$$O)^Pify@yL76
ztBn0c|DO8mKDVuTYiXi-^AC#yfBB)IgPT6|n#o&&9b4b~hM{WZ+`;2Lxxs^fabI=p
z+~t>UeM9#|@ii|g-1hx<B=c*2XMO3r+qRX~ysKtzc;%+!YhF5X+v8`RbMUr{ZruO$
zS#KzwQs`Ox?bp1f_x3l89RIH~uY2nESMM5q`}VQF|JX(K{oe@IY`wiOws!mKwe_Bz
zy$^qL_0+@P;oZkqtlpJAaOGtD?ZHDU@;%FgPY;%C=k(h6Z~5U$^Qt}i-plE0jJf8M
zh1`K<@0Q$+cjW#sTv^&T@ye;i{_oXf)xUAB<dUhQtLO&BfoU=CURFQ-if#2(f4lzh
z?PhwmXaD+U|E3$~`&XPh_Q<}<;K-+TKl7Kn_e78MB$G4Cri&xbpW5|T7fg)()lk8%
zIcK0Xa$VsUw_KObe);Uwt-pl#c`mL`&0Ntl{^fXZ(??!xzrXw3Xsz33isNg>cHO%2
z+-J6}G;2S6QK|ReUp)EPhl8Q%|6SSo?CleK%HMp!WP0xzN&2&Hv+>qzN*n+Eq`EtA
zXt2fO=YNgryLv7;HCEeJ{sVQ{d-29EEnoKd+<G%~b9i8Srtm#>P#zUoUmee#zL=X^
ze@|_WEi^g(;xy^{;zY9H{EBqFHFxm$Qk(YAuUY6ncB5PW#oR78dBfm{8=SrHI41*+
zOSN@%aWH;QaevR_gZq1SZHSLhL~-1|eA5-{XM3(SM;A|<Oye^K>JwY-+()J+*8bwU
zk>fq5Y<lvkH}oI+Xma`TXUDFaH0MlKN8eSx?VRgRIq=rNa&|C!?2T_O-FeR2dgDv3
zNe4~$)Zq532g)Bi@ACMq+t#LC>vQgk=_r2wj<pk?V3yyyW+4BIbS_>!T53ee(Po@m
zU|f%%WYDX}+o$X1j5IBGiX?wfANzxo9^Toxc`=!NVZGe@f$1Z?<GIhVh4ZYrs6K7}
zrsjHwrk>z;y7xur9G#9<<y=oN9vhpR;uWA)?ZwlsJ6}H3m%qW8-RouI)7uuJa?iud
zgOSp0Zys%J{k`>HG|T!|_x+(9GXH*qv!|KT%*thRXS||xSNw|HccxxbH#e_cGxf6P
zP0Ym`(y5W+xy|4u*U80a?U*p<)uxV~T$sB1v~$W2pSC{zKd)bwUUhQitM4>s>W^hQ
znR!8-=j9`HZjM@ESr;!0-ahj_TW1PucG@Y)5681XE8hR^&^>$0*rBJ)Wj3-i>8{p|
zW^rcf(BiFi-n-eCGqdZ5hHeol_so@T<)7o03&v&UlA#&%Zzdi7aANm%l-KMlk2Z7D
zv8(Pi>8#kr(`B2ix-!{YTQl&Tz3WS|?{wzaf9sJQ#hiQ3s^0hPn<(YO?fv#kuO2k-
zDT-}OR>bTQyX6eF==yRtS-GY*bM;lFnY=wP_p+h*z{;G9uikjmyLmY)=n~1jmG$Fr
z(eZ0CBJY0I*xQd@-s0wpm+=~MuQlgBYRl)gT6^L<4?J7?Y8vMrEthh0_3^JBZ<TtF
z(Is!o4fcI-F^=9NJC6Kysd40c);)T4W6my==5GCJ&fWIavdpa>Hw#}(nvWe%(xb=6
z?cDpqso_WCbn{~P#Ivnr>W^CInxk)?2p>yNKk)eXl0A3+M-qH-L;0?S8|>;`yZc|+
zcuRltOV68(7j{q9#&)lj##Nj>d-GLCr?29{(55cicuQoy{N@4k&9{}@Q=808GO;x`
z`Ib}o{lmyEn_T7U!~ObB&jWX}=tzcpb5EboM_{{BUU;cBhmP+tkmH#3SUek+<2l|4
zdVcLdt(v>-t4GYk)Y5_Y0?D<AH;=lw)ig(szFek`9@$f?9*g6n&+ISFy)&5_-!(K`
z|9-A^;CpfH=%d1_h>enB63-n;79TsDn|h{`pEi%y9Ub_Nsa3z1ix;{~yijDxcRY-b
zwBpTAon7cYRt~$9U2gTGmBiLJMW+6ynn@<Y<`=ID<r{A)7sm^xmYZOqa!KS4?C#~Z
zcCA?-c9}=sB&FP&qFkec`>qf3By76(=l?|g=EAr;*U@ET$|2w#CR4>!WAvRL$3jIn
zgBqo%WCkl{AKMX*l?Fd{5;a(PuuQC(II<4@Y;#RwXRECCR<Qc&q?hx6u|_en9LZf!
zO<0wsbEUj6;?3zno0%}OJ>z+JIf`5Fq;-Xct%bszF=1R^8OBLRvB%Q%?CH9v%zHsA
zI1;<6$cJN$O9HODOtV!m%lLSHu5OIAr}APP>s-6u`fq{@8<`gyprbU!&d=9>fJy@i
zYxyuJvXEr0=ZNGIqwoAQxW{l23vLe>$O}ms9;nC4+axVzj##Er!uSr-tj2{nVgmMh
z9Bd{fF2x5lsO6~FFo7_scNlRQ534|<Nj07%nh!EGK6}@t0)b2LJP(I%C<#)qy3Iq;
zw2%};FHSiJIjdBp`S+5Hc|=317Sg%#7TpvR2ajFlV=A~XFM(w*mpeHXNJ&!@pe&7j
z1?RmT4Z1$uWxG@k1Tr394wRFBx4+y9DFd}oJcE`NbGjfSfaLUScB&V#A!>!htNdQd
z(UV$Q4to111XC_8OQ&B44iX^%Nk|!(Zg@y})=jWDVkjdmhpA6|Yug9(ouB%S|Il}S
zrapS?x_u9A=e?UXckI0Ap4~ei7~ApC`@iw=hu(F~9Xq$&Gy1Cs#@2l510z2wew}xI
ze*L}Cpa1yMHSd4_$UVic-}kMZKl$|NukYP`_NV@d@Za8d?Anh#xc%3>)AP_jTz60L
zAMYEx`hgF9gYbP1{cOjli~soXv1>p2p>6MfXxn|i{@I!bKk}s?U3%?jJ~XoLbL9QY
zHFvz@EBEaF`6s?LvhUO1c*#S*=AECfe0=nqAA9_|eRu4*w)pzbp7!hO?-||lv9TNX
zePGARRTtlP#r4;JVf34y*tKKdw|1;7UUJ{qwP!!*-#1cgA7A7>rcJ!_bMNjSHsg!2
zvJY~TqHNWQV8WF|^F|_e*0>dE&Jx?lrUgy=AY8_@{JzLR<%FlHSD1v3eF^Rasdv(a
z7Qc=#N0Z<RZ6xfUnN@rmEi%X%=ET?L$gJgF7m0(h4PAbm-+kuMNRJKmaIPyQ{MId7
zD{Cxre0$;n!MMraRu9cA70Z`5Y-h?b|8X<y#8x`ctczi{YdWefbxCBay?6Wx4MsEa
z)~Wyh53~PoR6uUp1T&BTixe`~qrc^7lWgbYQ4Ibc!JeRs$21cKXN*<fVCH`V_us<*
zJvgw*>AMBzy(f#XJc^~{gpf0N^%Ayq!lUHG7QhiAR5!LpT$Q>^ITCQ0absawG>LB7
z(@9z;ERb9*I|OV~Qr@+aN@8@ysVqC7xXt_bcC=6B+NK*?gb9p2V0>lJMJ;`@k29|D
z3s+YTrGmJW3$zDUpwu1uBq<N32OQh5R%Tsio!`I;UD0x;!XhJya!F4(o5D>io$D=x
z=3?IAWt8yyRsE(5O*O7eBgDTr8z!nd(UE5cVZRmufHkoU)Ed&SDB+qj%oQx7Xjf_`
zCZ8GeQYJ#!#Y)t&K;j|>F^n2(ozrp^(2#QCi!K<&w_>bVMk7sS%7M?z5@f4@HiX=S
zuZ?sO7r(4FSHO2{-}E!TM1kgz)4DtJMkMJLqmEcAR9ziiP0+N6bY$rT7bq)+N6OGR
zh$hNvOz3F{r1PlG{DVMXLwf;S2`wm=IWh<d5k{z|#QKFp@w#gkfHR?pB2g=2Q*jEK
z1U=j-xV$kS8Zwb(M--h@<0>@vsdVd9p<+{~sAabH1gb0ZSx=U&kpZ+0m7*H3L@>0t
zE^^Tcw{3&QT3;Hz$x=uI&cST?(>#3#$5)mXB_;?-Y(L3)Laeg$!hA}7feKu<yd;jY
z4@9L{%__`_Q;md#BD7p&Y7!M_dX%WmTmf2UV~wQZf0te50}Nr-Ba&xn6Zv<3n7|y$
zF+obp$9X5Umd-@K6ko79eL59ZDH}7_)SR5@F7R<1RlsMdo;5S*?D(x|Z5*Mbky1%U
z&vqv4A3`xe(+ERxLO1iTU_=pnLu7<lG!+$uQhmH14t2n3zYsm>)NA%yQ?xn;v64cJ
z_yRTu#YD!PR;S`Z;q4tVLt4PDQZ9r~BG}?E4RyGWu#CvWj2il74I!yliakB@iin&<
z+YW8*nWp|JUw=&5sT5USGy|4m{1k>VMXpK5pkD&S+BJp=#>52zRuuQ5Oc~}-kMIvD
zBT|Uu8F5rx;a~0*lB#5MtK-mQ5$H=}H8P<%6gXX@J5`?i_$f|6e+|rPZG6#dLMh}T
zr?E4}%xK;5wT51)L4j?P=AdmurSpyYE*~t;WyGdt21LDxavnvU0Wq^#Gty+R$n3oJ
ztDiY#vWTo|#2OVFwhHJH?YCsc0;g$O4jowjQ%}mIn~At#962u{ESi3$MrMX)KG`Rl
zu`?l?tu#19M-sxSr7SQFn<nWRaOtRTQngM~5c^2r`RPdIWG@6Q^8lY!J57}KCwzj;
zKmKAwqG}z|FC<zFcLIEYNMTfi!@MlDL60AK@DXG$hR%RKaj_3WB27>IMzk%oClY%_
znKX>A$%<S&Jh7%#w<xLaaVfJlcng+jDf3SNXd=pJSGp@euqL<uosd6DHI}4Aua5Om
zmKYc5`+V3-oYh!SM`wgQj4E`6VZ~zNmJm`3zD2B8j$mD^3j@AEfiBKv`a@>C$4OY1
z)80rVOUJ&QhPY5qHsdpgWF-QQUNn7cNQ%~s?=WeVDik7|VJ^v*b6~Vaa8Xei%t+=t
zKQM(_O_T#mV_t-FXwPu1qjv@=q5_0AM6fkZd)suMgU&7)Xtt`?QY9)b8pgRx{Wg^G
zE9p{*eDsTgMdOqb1!db;0b!6yyfDyIV}Q_Dr^Yfpw5LLdnkzxthKW=%45Skl2Z?3O
z!4w-gr81GglhtqkIZ!H^w#9eZ`6S}WyxtilHRo<7BBE|W@wzht>H$h)CWHZi_uN-e
zcRYAEO<E%)tL3k4j8vxt#sy`=%N9b6F;0Abh%0kYFrIa&l}u^Rpe;2u517O_w2rr!
zQ9H=p``8_R!il@+D@mb7lTsG_b#D_jz!?a8&84Qeiq08YYdXbOQ*8H(87*OtK1+uA
zZUbJnvo4HM@^vy?Aa&$EtZQ?S1?Kk(1=I)#F&NtXK-p+az)=cT3|6y+uZNicam)}2
zgFp7rS;Bz63rM1Cf1axfeRmiF#gr6Scvx&x23iJbXUozbNAIR0Oky3+EVO<K_0Vdh
z0`?nY8A|=g9CJV<LIV+Ju|XTPj@#%NBx`fZ2ccRfi=>h*Rlf_HwilX*Ms9Glrt?*Q
z27!=tLMkC5oHZ`3wfusjXvF!m0;DZ64!HWFx!Ypjp}N$gVM@%n7E-0kZk$O;E_?%I
zjvTDl5}o2^;7nR$c3ENluTBs5=_1w)bRA;2p)3}>VGNu^^DxOgWNOL64A}=ZXKpj>
zD;OK?<>XmJ10eXOzLaS+T)Oc#)6h&+Sgb>XrL=&%Ka5(#2<MDr0C`wSnx`;sCzkQH
z#VSG1+=S4zPzx*k1kX(uIoOKjOL7dg5;Yia)TX_x46w|lJykQucM~A;0uJpeFjFfl
zraVJms3*xHSw;PIRnxZ23&>tuOW;K~v6OsFX0dPE`X0<kpOJWA!bEvkql%D>N4t3{
zB8d2jks((jZ(8LkDe;#Z!$VDEVPj#hpbl85X5lTjxWc7V3J@X6;a8Q((eLpr7l3iP
zv~CBp9T2lFi&JjNQ123UT0|B2lRPA40QaCp<7;F|vd&@3!Wg1aOg~8=$%sWAQ9@ZA
zpZ8Mky70-E8DcbYn5omYv!R{@Asz}0KPGY>7ojMvAG8^2l%!c|e#nSe#$`l57-%ej
z35<uCT<^j!zLYRfF<>^Jt13@BTkU_CYELNWxzy2)maSlg5>^V(^e!uA)kD<*R5`7?
z(xVyzzNn)CIaaL?s>Af8RyxJ4{-Xj31>B^ji3T1-+6c*=M^zA6X<n`nrJC4FP!AB(
z6MM6rhC<3!;XW=Qfo9^k+7M)`PC^oCT#Ez>WR-1yHK{%N3xG|cKG|Z-89qy42+QV{
zrbcCIgeQae`<X0EQ%7pe$AbWEtI@o}6#UsVM;{}?i8>YsFTk;i0d?<+y4JrJS1g&D
zgkGaCZ8uGH3MZ9=t6dYA1c;qb&dAh40;Wm>Ca4xEVy*gyD6PzLMh}gCtBE8&XjPu*
z@`f-OXx(O!S+PjlT*LOT#u(>ae90~iMn;<Io0dhWJ;9?SM@A`rB;dBKjHeJ#u-^4*
zD^9Uz>9sGqES%}4X{A@=5!u9pUDN|GSR<CeiB;68^WPw_5Ik?<v-Wm)9_zzIx-#)m
zQ?q$)Xz(oFf$Ymy<4|%fM9<mIkF-Iii!)u`yjEK`z6E+h%983XODYaw3gwG!Ib)J6
zmt-@-gt3_Ua5yo}M|M~|%MyitM<34&a{4Yv?~GTOGzeBMGl`OYb&q<*o0MIqe_f-I
z;%{c1ic!cDsVbmhMHj{t7?X^TauA1=W(j5_o2(Y}ARLGZ@Dz8<MIwoGXjp+sO7Ol&
zL-7NbRqec@?S(4OuPom$u}VevHUz>vX+zae6U1IVah5!~oEW5OC}L?6>G<z_<thn=
zkQ5pp#Fi-IdNe@)Rxi7aaDHGWSf<-LQ6nPfb0R}V-Pn~S!Ui5+Fo_Saj;SD#de|Gn
zYC`AKiXg;f3xYe=ZkWV3^D0C<-LQW`GGnT+*G+E}S|(o+GT}arcdgLJ%Mw2}Xgz-I
zKb60W`9`OnCf|e6uxqKy7fL84Ro6H&@k@9gC<wP&O7zT1qBkDY0=14Wy`hGK<mNO&
zq2;WZMNS8!V;iKW#4E^JPe31{5TO<2yc9w@F6yPVWG#+1LY7iiaCPp3Oh3giRU|Z<
z+9RBbvixa;Q<;PnTqdMd4m9MypQDHZgOVy@{UGU-5}Fo69Tl<G(Z?b*k*crk5``EM
z*0o@$`f4N~CP)VK;Hg+2Mwm~hvN3~XfTeCcJ5?dHql`6Ron3`KtSq6wS1W5wXXr?K
zRH>TC=U3J=S&mBg;2*c3fhRKyTa!ZfC2MuM)#G5seCk`ObXCJ92%Pt`xnI!^!2)9(
zWudn)*sRt%OJXHz5t+T}D~NZE9}m#W`bzZ%YR7S!V6TZ_5)10XLWriP;Uy@0Ij&hy
zAMpT4881~M`8Tdl1Y`mfAU{zSV3w=U&2OJe-GNG?T|>dCQ)p+SJ+O;$CRHLg6hiul
zHmLPy+$d$FN)w<9TFP5P!ez4irpQZEUVY_5E1-!BKoZ<g(Ofgg?#-0uloDCuLt7F8
zoyOvt$k8_YM=AfncqXk11%fKqQWly1^nMqzcS1bx7FnlrVV7ujb;F=QYOTv3?Z7d0
zWCTsC^I(WnETtJ+<@ItA=uAWaS)nChX-mCAqB^uD1c_Xt><851wn|x&q}in1x>$3>
zeCN~?SSV79JtTJi3_cmV#c2rSR#GO7w77)5Cd8v%pEf8*M3^zifKIv|+B$Mz?KdGS
z4)W2hK`*<g(MVw&qsXjIP{>e%ZhcmgfqXI~8qzERuVcdYn<c<{Qy|i|B4G?sT@+x-
z^wjYu7tc_3iM66aC1ft}U@<M@Z*NU|1EWk6)ejN6OQ(B?s*`n|R>yd3uz`*tN=ayc
zXl5xMMpSZWk-gUCi#s*L4D^Nc0D6N95VmQoM$(IQ7@^`EWS_Z!(7&`)wR}W<6;t<?
zo1n>4FTKq*vk*Nbj<2}4^Rgr$UD=Nmnl8$Ca5X|fJWaqBl|kr*?G2j%T9hkUrYa8s
z+abd6)7fK;Q$@v-C7%s|f=3cbhdtSVSGi9%;<7L*4QNmG^-K%n-ZhI*kD>|#G(kV<
zuzW28Ut<Y(1Y1dChMa8^*cS6KLDWzRWer62AR2OvryN9}ZA8XvP04B`?IFZfO)6U7
zNX=ZaJk@1FR0YsWtJZ21Ghh`@_-nU{_6t`UX=~^GX(l6?*CjSZVVSQq%5?g=wzLv4
zc~7z8H>aH`s5Av62I|uwQuRf2Bie&kEVMAjCFOAt?2?56Xo*H*Eo#C7kd(HZT`A$v
z;h;|ow}=4v<~%`6!+|I?vMstSfC#l-fo|bE;<D{khg#&~v``di%icGgW%ZqEk2+aN
zIEGlQTrb8_%pgz#8!F8i{YX+<fC#syO4cwt?13um+0YGgxK6TQRu=>;R6|MVt*;tx
zb%F65Wa>HOkXW>S6(ld}nb;LFaT?!Lisr?hIO@Bgj}q%rVjI|Om~HD4SpP1_7bdbS
zt$IfDJ^|pvSzxJ1N$Lwnh0`ijm#TOctI5TI_n^oOI=7pe?a-Erbqzd+d{FBenwhnb
zOtYJ{f|07G2&|aEgz%|o3q_$8IoxTaIN~sHd7D9>gAfKz6brbjg$~N8>mkReqY60k
zL%efvSPu4DsD56;2dZ3-3l?-p^hifGIwD-WI^M}NQrS*BhN#v+A2w^4AaoCH54^zK
zjT9YV0}(&RC<l)a)FY|N;aL@~f(|#5#nFUFb0X+7lOS6+XmKQV56sa63&uSECq6L_
z@d|0Aot#?@9q#-Z$T7IFI7W>n9_Wd^(zC}wprvS)->~F$siVPD6;_Lr#zOn|V@3Cn
z@3ut6{@hE=FQ-E-V5VTW+0~5Tc1^D?^J#m%?fgxI@58<xd8n&pH_2rx)?l-#fQm4;
z`5*-TZD8EG0-0$^3nQTJ>qZy{h~QbRyU=MT)1W32f!A98#cH~8NJNQ;_$mfIh%L<<
zS(LrN0i`NRU~8P`PLUrpkpUs(DpH1oLL2LCj_KgAeG`Jl3w^49Ixb^Ts$Z_D7DZKp
zF)Aqvt-v=qRX|)96%s5}1DZs1C=cEO3Je2Mwa7Oom&G})XMQ{Y@Xv$Xmxu_sDNzc%
znwLW-Aq14UhjdQ6DohzL6tFY^54o1|Cmazpq7Goao{B||0%FE98CaDb57_6{JYwTH
zO(;#}K&V;=B)T?fk%f~sg?mwFHL6$C1<2Dk44*eQBhIH5VkjRPm-E6Z&IIChYZ?k4
zwBG=o>a>As_chAr&!I@0+Qg@_e2FM^Ne_({&09Gg0qO<K1+=XzMNd=>q9IG@*iyol
zuKuV&X9Yx^NQE1#j=&=a70ZAG{EH7bTxM&hb*kJvBJ;oF6TOrOibVgL?9m?0M`m!Y
z-hkR1vgbFBRuK})Q#OiAd(8QiZl~m~mZL3xyTzF+&0}`BW`c8ds<7tNv~_4f8-2x0
z-#k}y(UoF01$;ZW&~Qi16s^e2)#wYqm)NqUgYuln^*PS>Z|2M7=)`c$R(9zAxon2+
znX8q?j4io^*aaPB5frg@nOX0`;&4?z?^SVZ6&{K<^+bV74+eoWNzS}ozAewKzwE^X
zS_w@$zUyvd_tq@=rOu`$doQI@&Ra&EDZ`_K+9QP?*9^BFn(rGZSxIfdbT#>%93E{?
z$H{qygH9|hyW;5P6*f9GUuv4u2i7K1+doY5=kdLGUa2nW7p=qdVmY-!ovt%e{nU}A
zLi_E|5y^*>>$JnxqGH+R=5FaIOnvgSxRg)2nvdEwTf_Bc^3;_(_~=Nzv?`G!t`N>P
zUdK=7L}u~#Y?<GQF~z<P6L+%;ZP;lmkjiJ9x$~_#^huN2sGp9ytp54;&_eQ+68kDq
zTJ9RxA6HMzRYE~D{QFzU)^vIEeXTk}fiq=^!|p?~0nf))@8xbNJ!HZm)4Tam{Vts|
zA?nw=?SPq-sUHnf?=m&J?_`&BmP<n`?mFNS!<wa+zU`M);s#!B57z6koqc{iw~{RD
zj@RXTdu-H{xniC<)ur*|><zQd<o4vXoiDO*nYYE1<Esa2ygk({n4($saOliH%O-PW
ziqUkgr+?UJWn6abR5V$BCNs%}&ZU^dZmYH9NB9s%{605i<jSZTSF4RjlBsx@ZY!@Z
z#-=OfI8?7&M@z7U;>MdNB1h{4?9}`!nSC90HN#5$NlBW~sl|b?K4gM|r5EL*n>*0C
z9uC~yVb<=`&UxCT2`h!;i0VCU6-PnpVHyl4y__9z?=$_juqrOy%x6J)=G^*IKFDv4
ztc`BaBMxDjNPq9Dlf>K=icYjmv(apwKhJJ$o@yHbqH*TT1~Gg4?PH8{v+IQUAT-au
zyI&%aF*i@kF$06?=6~d#f2Dut=d9OpzH#$qxw$nDP95l9Ikji=V@c`C&7(&@b$HFf
z*#}F>)ti&j4=&i&`tsqzWAA;i@bEPkj2`;s@ObUN4$Ig#4$J5Mb9~#wFTc9B=h^+m
zt>4(c_H*ypIezHn*VYym1~ycmnH{`;@ao#!!Iibe=ICJcSl{6Nhp(;Od60K{j%@3f
z!Aq05!z<05_ZO$ec5d%4+R=V^r;Z&gmNw?M_b-|^5-v_1>l&1eE4Pfto#)kCw+za_
zEgOm(@7X+l|H{qd?(Pl6BR6j--hc1a_50tvc~3O6p;-OMvcV_M+F3hv@01z;z0-?(
z{$}?sx8t3=^c|QFUrgJ+{h{%xAHFeHdVG&e?Rl*oy7a;Fo~O_0AHU#&>A1UVy!hh}
zOtk*>4HHv8czoLvKe}bj;Odt@{fp9DpZ@B*-nqT_lb>#R<}2?w{i~mR$E6#d+&J~)
zgJ*7h=8=sz{NmqUJ-zW~?-|<o=<PS`I_r|5frBfD)~?!GzbU=&(%S3JHuwMC3!>Z3
zdd1-9q8Dtq^KYKt^Vl!X*>vZ>Jg@lVPd5#IepAo%GsjNeb@(HnsN8h;_R~N2rWfDz
z_*-AQ>&{1CF#Vwqyl%Sjy_4Sd%+H?x>d&2jX0rU{FB<>VM@Gtj^yv!+HXb}@&rQ2}
z_I&R98>^*<;_~c|pI<)w%a<lk)ZQ^<KK`~nYVXVk3}*=5Q6IYg<>RICeaZAM4wTcU
zPgyUQ9$aINcE$FuFDMni^Q{Sc*0DnAzOzP4t1ln@>P!A`y7=l>Opo1nY^3;uJ8QqV
z^0m>izj$Ns@n_ClR($f#8`nPl+Gy~pcbScU`Q;lvSN&4y$f~n$ob6n-ZTbJc@bupE
zw<ft;IxoB_=?L#!b$b8Y%CnOF-`{!N_^wkXo<06LbKt?wiGjb`IWX{drR2_g|1Wj#
z113jt9r{-H_O4pXB6>$7X%Irxj7DM*LX4J0tc5IU*Mk^jnGCY5ETG_)Se&&i$buD+
zG2qg&z$TZMEV69t`TFJ#c)_wC_FEKL=*8F`VcC`w-`ouWN6z&hL1bU@J?x8ZOo)Tw
z{!aC@w3fjpxw+r>-r4P{Q>RXybLxL}b#>4A*<GLCsy@+@(~oE74t?kDP20ZncfH-~
zKY4A~ec|P6SDyWW>?dCA&wl4UGinEJ=^xr2oKx!g$c=*=hx0?~mUFU4i|5p9d(Y4>
zRG(%JzrQT+#dNjME5Coo_Bh_J_1CY{rGcjh%QtopJ$KHh%6mq3^q7lv&(R-eYv##M
z>H7YM28a0B?d+yyL)rg#^Ua6e_h>HMywlviU}do~cys&n54`8<;Qtxe+Wqyg7MKTb
zzHj+Y&F$y>#rBQYb@N%5vsV<~f5D1@Kb+f^YiU`l%K4t7`&+}?^|Z|^&uxFtf!c!d
z%g=gkN6L$;^FG<KZP(a>^}8NyS^wf4{0!Wtvi{D@&fF{a@_QhUwhTRfs6FoQJf#{H
zF3t`;8VyZs>WeG)Zysvc-t6SQQnyl1x%Zh?zRHU97F8Vl)IO%)qq%bZU@pFIGFKn(
z-hOm?p=^KYmk*yYN15fjLS1{<)c?9o9ewcZb%*}@#8CG4zZI(=Jsri@-OFRwr-N-r
zj?G(t{nu_@f8G;a^L|iQ*_N@)*7tAsU%BDG&F}6l_GG(i<!o?O6ttb<4_)Z5j%J>{
zXzQ|t!P>sFyT)!ZSM<MaQ9N%}%i1G_mTGp{K$LBX&Ai&%XYXpOM&J3^vdSxdT-kVk
z+`aOy0p6-Cm5*E+4wlzN*_!SQ>dfs$Qz*Z@{(a@Kh3Ax?XEdAneZI4j?JJKduYA=H
z&ZuuU^Xuj6f9j_;bGeRd`*&Z?9qGBJ4o(!VJTU70%h3bhJ8w^EY@}9R+i$i-Kdz15
zQ!R(z=^re8`z>0HuTl3seTBMj@8$N$5U=A7{O--qU3yujzVo|PTRdF7uXu$S9l5a(
z-gA9d7+mO&ul}ob-@Npc&DB$Tw+!}-Y%zB;;9NSV`}wb&c3b`P?^`;Mf6vgK;=qs%
zE}Oe2`}?(G+ZD<z+^8F^1BHQ`SGSE!o6}tnf>14b-z~*k|KOHwts7=k>dV{r+N=G~
z%zk?$`TGxhcxOVtC)Dp;-e2ndw(i;SZ8hY{ULkjqqmvWSH=Y<A^A4H#yl>Y_AAeMb
z>RDT^R@5Hbs6EFu*7>(XJ^v%tgM(MHSTMZp5bH;J59#OXjc|{>QrW#%^4{&i&>m`p
zr3XecrD^{q8ohA5bol5`N_+09#%9_#YSq`CDJ_}K*2qY2$;7=q`pNh8Jo3YEsL@-|
z%3h`iJ1b?|s@ey7`-`SE49qOfkmLtc{ZPy_^8RkUcWJp&-=fP0;}VA#D(kxD)%-&p
z{>Fw<XMBeB-9@^8@a{N_+J;NL<BN4Pz9v?Uuo~XICRcu@ma8396SW8b`bc+ht_g>^
zb^QkpyWah$gFP)<26O%vwL7W~mPh__u;kyTaxJ6wz{d_pwfooP>Te7B8q+>ku*?3k
zU_Sf}75?tQ#r0`@>bYf$+K=9~dW#Aw>-MzV6W-S{Y{IAiduCFZRXnTdsdp{V#ja0g
zV$LND&IziAFBnkvg6p@~N*u+L=H}9v>I=s7<~Xio4^O^l`PL`noAtZmcKe=qhT2f+
z*Ee0N%sQj?ePvs)?PlJ$o!Py<o-1dmGquvN_WvsuK(%5p)Vd}Y?da=??%FbXv}H}0
z8-ANs_wpLbJ;Qxb>mQp^pVC7I-=@b}p4~I1o)~?kWu5A2=~a{76Gr(DR_$HBK6+PQ
z6!_0_;OtO`z5gq!G_#?m_dVejQ1#Ad<FMtRuBu@)Kfzk?Xhs(fMr&vOLtf2%){irr
z3Z~$7W!70=Ww`k58*MJ1KbkR%tC88uQYAdfPDXe$$%!-3K(|rx@@kF!H7>JmJv(k2
zlwPr^$l5lm)@_<yZW+quGI6##bkx1m6W>Dre0Je#Zz#|GJJM`ln5*1H`?YnR^{I)L
z56k_LDm_xrp=rqL>*4NaS?>f7WZjYD&f)&B&sUmdiaH&OYK2g7P%F|;vOmkY6di3U
zmRZ{J0rs%FO)H+t1VcVQ)@Ut-6xrp5wY6QO1eYy^r`Un4t3@{IZ3`wkBh_h&Y)TiD
z;TYtk^6h%HsHkflYJ}UPUeg^EEzcHAmhXP`ujOX6_*0*J=prYg&02G1skm7ydtt9e
za^=T0rOv-dsXBEZa0rZ*no)+TQ0`(qnU`E>cR%Jq)pSUSH^RYkn6({+p&HyTst%}f
zI~=&Q0UX>bYdrdk+QF?QMKU9Z9YLfDG~<nGiN+Lh$%z&pNxsOJs{^)}%Xk4c2YKZ8
z5riO@7ANOWtg~uF2m*c1iU!=MHH@tlh}Op`6VyQi3}CmH_|WE$%P^A1WJg070PNs?
zaunvnp5iu4(o;^P<!W<#M99zt8VEDfQk5i?c+0k>VDj(X#j$46I~h{4Tvn4nz$4(n
zt_+ukkZ{^Er~t2tAj5h{ll`6)tdk+-6jhou?I8$|cY0QRRWL11?uHNk;FkCDTRI<q
zm3Mx&fAHs9-}m!%8$a{(jZc30noqxa$NN6=>L2{z>b3li&-Wht-e+I^(EFa=`Y-&B
z&yUwH{@(uI`O%UOeEB1H{0r~ZytZNSw_ds8p{+mr;&-pQn0I;}yYt+guU-34_xr#2
z)bCyLpVoZ;v1{EsKiwbv;>N4K{1L(%c<1NF$GX4&+4bN4@^{yKl<;eRxAgPfANtXT
zJHGVFjUWA|cYk{StxG@h%m4b&Ex-KI#w{QH*e}l8f9v_P?s)e@>t6fvw#9q*ueqW7
zUCBE?-+yhxioG9MvvAwfpZ>iceTess(7pe=TOL~Scf4<O$rrDw4jCgEm3Lr%a3ecI
z1(p;gZhYi=Crwl<v$lu(*Ul@|px>=ZS4;aU^IWQ%-x!Hi_6ub{n4~>?z$i1xHsS@5
z9}Q8klw<Va$j{E9Kg`l9x{&Y%437(Fl6ih-ca|4sXSQ;0P7Te;Dqg!&*@c!L>_h+A
zWtII8oN8-Te5aUAKVHG>p3OTzhNd`+uM{#A1hfD+Rk;(JxkidwX|4PsDvGm+A7<J2
zQDlz6G{JQ@v@zNfO+-NQ`_`4Db0KKjA+P6XWodGxJPsbp1rkvSezMzSvC2C+=8eOS
zmGU?lrk_lpIh$XnrIe<rO~u;KcSCt^<jf_UWHe>6Y75*L3wzn*t)V|LUPzd})VhZg
zf%HrBh;C+qP0or^rZ<Z9@j}p{9#o_3ws6a=3@Htpp$HE7adCcDT~aov4Xp%~;|x|^
z?#h_qyq|rck{yVZg^R?I^8;T(7@3bCAqsD`QZ}!Q(Tw?)F?T(}*rU)58Ap0)7+Un!
zN@}(mDY3?q-LZ;Z!X}p(%2tQwfgSJuXg?tNfHOw5x7V3IXye3hGYSiWvBh{mwp+)D
z3}ldbfpA+^P82fKVv!i+56QTybwvCeCI>6qdcNCcwzNCdLS6zIW2{5woQh!!T4hyW
z70;>1D)OvA?BW|IR48X+&9I`wOqWM~HTG?DEJaKOekO6@t6`x=-BGE#+dfBzn7yI<
zWl|@3i7}2@%|>kfdtk8l)?o?NC<)zv1HA^4JgW-okg8HOdbG!g4kSAuAHWVejw$A3
zPtrXPDaJyjS@8R#+BmHub5s*g&?VPy?By&Z!DtiFokpy4&}T(Kq@IPpGuF^(c3u)k
ztx^Z<_yx6bvh1MGZ=syYP-2+jJMwb2At*MRXB*;2RmWHvCM_*^A$yu)m;jngmoy39
z*KHOLYN-r<&>nVC;Zs*)1ItgfgB&<hjQreBr}mAqPKYF8YlST#*;`YZI;APX#fxfr
z*&YWkDJ$RYIR-BE?rCFb7OIZy$kiPwU~70oQg_?sP9>=@%z+CwK#Nf^8G%LA;99;V
zMzfBsvWB3WlWKmfJz_*48{N)E@Td+&X=upwapY=7N{{lDiANdAH7Qz%uwvt=c7mu^
zILHGwlP{YT7gk24z$jzb@~07Ek~B3;8yQjcGf)#qBCc#cupY&u_~(~XUAyz>vjvi|
zmUOOEWMUJv_2Bs>WDZRpheRs|U144MK{Uqk=pc}k80sha76HyCpZa7WsE0%s6m8@i
z$A&;f`Bm<YNQ-E|L@qP@Se<skx@4?_qNQW#c7Cfbz@Qj@MPtZ_EHcn3dgyn780FzL
zq0|myT<<&oAcA~C6&297ED3bdn5Nqwzo0m=Dh<vk(#INC^>*UKn2HCpi}U*w`)}-F
z+nPKt38XsfdHNfTVn>#7K}+W4hsjYy$}1NN2523Atxn$w!ZFX&@(xotyi2RGGTfxl
zu*kdA<i@JJgxk%q!dk$iOldDApIliXC@I9)#Wom6sAC5hXln>~fY2CM-ono8s-bb7
zyDp_bQ6-}%XA@*-Ht<<YraGxM%9!x_vakB^1w5{9(m$&VWkzDTK>Q-*p=FDj0ZY@4
zIC#@Qj*WbH5)i$X|AYcRpo7e)VYTeavz0wr@}AVs`oMxp0Z1wA0yUa{zd8Ony^OIG
z7kqX?cm+%}!t%f(`5&&vIDUhDybgH`DLceNK2;_43+R#+kHRO~sv<Z9F@do1@HCe=
zR(#Qh0$eR2A!>12BV%2sNceOu)V-cCQ2$0;$6xFf%=4v%yU+bA(5a9oz$m~kv>-G<
z7BUt<qyI@&={yO<0#8<PK%LeLi&9#<erlTWiaAKkii*<hB%ZEM!s!gqzS34xn{~)^
z3$oflw8pG?s!VxF-Q#KTI_YCl8b#8&r%M?+ZPen1freAeoq<o8stVT1^OsN?5XFb4
z3I+USNr{04HL*nU(F8-V%utHy4J8HdG&19hp=Gh2u@Yl7ND7jB9!-QX1RJVD@|&xY
z1As?Cx=cCIIIN6G&Hh^!yULj5NdZ}E&WkbBgKAtKReG~hJ3WrcSW~3`G9OA!8WJe&
z1uC$_Q2;#aq5nJ6<m|gs8n%5#*)ap|X=y^iUok$8krl~A9TPKt&MHmV!vY%cu<ldQ
z-HZ|Rc5<ivR&3Bl<>~vd>8~hO0og&=<=q<|)>vabt(}NGVd*)U(*vso@A1|D*{!HM
zaGmX-TiZ@vCLYE%>K9I}o}shHl<VE($miGR^0XJ~i2f@lZK|@IaTQe59RbTGQY;Qe
z7DYTI@p;Fy!bGWPIDJ{4aaHnfqISH{4ikKk9GG%|-4UjCgcF4AEJVm+(ICsOArZu<
z_;j}nt(NiOu%SBSAJH8Dq75r2+7&3M)r>1uQ??CXf9MIN4($$$-I|CoMdgvHKEwmd
zt%#W5XM5C9mERFXjeewlD;6_}DXWrc@LswOHH?=ly1A^82A%5Ac8}3Sba+49!LU)4
zy42%nxiV_Q`>|KdwklDiA3$7Os_cOG=p*u2g{8wtSmfp@un|p4EApr%e=?3R4prs3
zw%*Y|7sW`!V?8J~Grt|GQZ7`4+<6VlXv;G$i>~QLW#SS~IAbgC<GVcE3sR#{J*{la
z=k?%=+KnDJCDRr#T$NF(S(9R3nO1O^WY!yy1t$-$`o}gPq{3d*a8$H%Dr!iw6ZxY&
zRx;fCvVPWTEL>~@+Mwz}QlQ7xmH^#`n*!QyH~e1FVg<{}P7_&@d#YW_*kg>L;H{cl
z)lX3`lu57*F}zo&Cxe)DydtNwcv`44pgjC13Vwh*i|1ANKot@hjVKtv%7x7fgea<E
z)f!y_J~0hG6zT#nSSJHnRbC#0Xt;cFlr4(OxUMit^D!u&$N<VDVxbvtM1Cwy6KS9d
zXz4I&I%&0Ulz^4As!Fk!U6|$#F+pn*|A?d@8G@0TM0wy%b|)}lPZ+2YipU0%4A~-`
zg@oK{NP7BNl261j7!$>yW>kqd#|*(y(~$H_Nq9od5GK$j1dt)7)xsc%vR-I2^d})n
z`*dp~2{@C*8qG*YTEOFSEzfbIULbj2>tpjlB_1KwU`NttWuzA49T-IdZKdlwh^$u9
zyr9#va0~^H9t}z&Bc7|bWPPC$orw~Q+RKxp5oOq{v`@n&V7PSC7Er*Y^pP1$$VM(K
z6SS4EY3A$1S&wG<`+@R_w`m5n6*FDP7|!0&w}8<WoYXc!Wlbbpp)^QkEi@nGD84iX
zGN=tG(}qxhYA{1QPb=9Aks(YV*5X27bS0r9x;NZu%%<7q#%ko$@%JZeE`e4dHu3r<
zd`=t$I&3*<&4wgnVpxGl6-mF-cL+*aO9?f^ETf8!;v55qAU5$e0pGYh%lx4{q-a6-
zKMuay0d7WcEdQMnU~rY7cKpr>gg_hi(CY?yXFsH76G5aIW?qrCJK!92YUL*(5oiVf
z6)?sHEh?IHnul(p^mP%AU^;WrP%trNopKgrS_Ya62BnMygu=|78YOZgQaY$B(ijxU
zx|=~xL$wx1QkkX?F6^l}pnwPOsF&bL{M2QzvPq1H0Z1-=!-)|=tX=`FDqr1#A7~sy
zwRo^w+tlRV`N1%kmS}4jlMw?W(CXxk8F^-a=}mh>^@NdF%4T8Wi@QVgGGjFB2t`8G
z?jIzCL93w7a;3SpgBbXdWl^S89+pERNvMVSF3pFUiMf!Ig3&GkN%l1RoYfMCF72@<
zgHa1-0Fkv&5t$ln2k}<0G1r8wNlRHXW)d%5M6m^w1sAY#MOq_9P(TuBLBNnn(0~sy
zq2STen6UB5pb_7~Q*>b*k4p+8QdPlXaZZ34b8>4!F$q~8=NS?b?YcpPJ#LGLD%Vlb
zv<My*eXh=}l#_xg;zX<G#i>xkR+v~VVq^~C-zWf|z9Z%(eN23%Mr8gFXf}iZK08d`
z6bXWh@)RI999}LbB%64+5p$w7vC$S&>yB(2o~->N3GxC$BF7RHaM9eYFP39n;B3M)
z7e<aURv0?PaA>W<g>R`4i?1b&=W30HH6j5Isd6?vE7IX@_6ZCKj09b(Ah4`;eAc7@
z^<n78k!Znw(+I+%U9T!)Xobt^3|y>nuA?;_ziEXqx}u8KHTSZDIwaG;5h$WKk_Cm>
z=RnplQVm+t{S`x@#RPvOu%sHbN{=<`XmF|UX~-%~Dg*%%<;lL0PQbz}jdmfSxb>Jp
zDOKTNp9XR2a3z+Az=CM)jBgf@@*z1upa)`WNpOd>G6Abb6H4NGCgIb8(L%{vG2N90
z<0{;Q1+2wEpu`C7MJ1~|EmCn#08OPNJlc`81-F7~72r~5c=83X1TcxZtv5qud@U(G
zaheIEAZvvj$$iD~sX@a-*@&%~<}jdX70S(niIuV~Lk{2r#3ak3$6o~*x1iPFv94oD
z5jFd>ajYess1Z3*mp^_Q$8cFU_mTK`=SquJv#4(}iN``AQA;P!Ly#=v@ujnH0p^{6
zs-WCi$hwdeT2$85$T8G4BuZ>ET%yzA2D6*12**x?Hx?40RVvzpUyCr6F#*2Iu*hga
zFd~Q%fk4yqd#nqhDJ3<-vUh7FHS%GO;maC=_;N3-oT<`P958ewh`0u=EWz1_r39?l
z!aoiytbgi)$_AK-pff4|_`G9{6C=#fkDKo1ORE`97+*<TRf|-1fM{_39ixwr23a5&
zcMq3D)m>foe9grwWC$3NXnbrK#QQY}welEL0$~(8Q$s>^a7>t8M+nsj%B_R}mwW7#
zT1~)Zu!-YY!U?HPGQ<P?P>{is3kZ;5RUhSDN(hOootMXzIoUSfl^rz}isnij{6wZu
zj5vwWjOmHqnyX016ru>wiP2!vtva|8`&?!;0)oIo6v*kc2$FEqWMsFxG_k9GQRUQX
z$CW{YR(`-)QzJGtn+V&rKDa>h-atFkl0}iDI|sqePHSm~@WW-KUmpHBj>xk3d5r^D
z$0`_xdg52jK@?bqT`j>AnG5R@3aAem6Ov-0xymd34NVMsO$lGAUU02J43`)nc{Qwy
zUE^^y*wdHwjF^zjGh^%lXw&B`bVTMF4bsdJqKb)LTpf5))J>6Am>>X#OB6aUYx|sE
zM~UlCv=bS608US_l63q@r^3)mlSwfo2^?*TlDruq7%_CZFKB=ub|lO0yBQK>)5sd(
z0T<v#DzG9)Y9WED<kWJ>p=-FTBfIDtbGuBVaCAV|ve^kv6Ei}@(TPnIXL$C{niZhc
zJVrp}CM=V1er{6uW$}}M3~yA)ai}*jk!G9H)3QsVv~kk4vbHyo30>NpBw^pim2QTx
z(O9J{xsrGS4h$~C3Cvm<G9lBqhQ@@5!#$FR5DDw#@&y-g2sKN*fEC@0a~e)AfYqs&
zBy~ZQ7Mg3&hVZ&2hqQ0aoa95H$#T|eNCje{MP6W)PxW9&Q30AX0lwS9B$=a-UWzkW
zzd&+85(8qT*_1)Xgjppm3WRFb66pZlQbOSX3-E;E+J$4*Zgp-P`FLaV5QGf*ml!D}
z%1Y|-V_#B`JOjC=m{*tsL@UwaXoEwhv@~4VyMZotF)0QTZ{YPDQH@C08v3fmZ`PIJ
z_d=AZxyDfx-YTi(Mm}kKGG8D<^DQSSE=O!7UPLNSO9iVDr$xf@E=E#j$b=wZNG(3)
z8}!>WP!|&5d$D+-FHGK`$W%?R;`<&w)%TOCA}mC&g+lOM3AuY&84=VeTFM(RbTv);
zF-akMd}GI#bTt<%dwUK%N|H>#rFe3VTb9j85o^gjpo2PYqJ~}!r<E`fc;W+P8N)S*
zO~OLMRMPvMy2)=8Noft`OKv1m_!`=1@ug1)cv<&5KMAgkMn#er?2*JqoMuHgTL!_}
z@%&1x@-0pRu`5i6Yxrv}9w+ZeZk<(kC^CIPLf-T=3B@K}vw{g|<_ReeSJU_;uy`ua
zir-sT!4Bhs!U$yw82X1HY^0rPssAyxR?-V`lxqs~RcSgRm;VIP)u4nlbl(|R1x+Ee
zU>c{GQkaL5y+1OodE&t@0k}rOrm<s@nK}WPUCD^s%8-l*n-Q08BzV<A<IXv71{v2r
z0_d*DL2AODyxGS>J|RoGhP(&z{@0-3SCvm+Ti=KW)E?r<z!L7+`*IbpKyn#N?unyI
zHNW5ImFx~^bp*8*k<-#35XJRAtJ+FAHP&lmc^Wy*RHcM8cjKo1Ak2q!bkOfFwqB{C
zVV<E{qgC5T7_LS*_k<dGQRQw{D4y0v<wh4;Lwk)`2=cy<pW|$#+)9RF-j<E^D6YG7
z=(DV%e;b{T!@_j8eKi``i0@`GoO;pWsND?#dZM_J?*x^Ul}E$aU-Sd@f)|tXj<D0~
zR&~x**3^*YTr+t$dNP`)cFKIz$?w)h*-@%aaVw}dhaENxZleti9TlQsFDlj)pL~zD
zHTcaSimf2u2WxDm%p-3uTQ;#Vs%Xnu*+h+kOtcLHIvT#GRVErBgKGv2&s==Z)PL$;
z4GVg*q$#Mt?sPZVlD-rau8Y(Yxhgr$mU$Gbp3tP%;kc2tL>SgHmu00c4;^HfuLL^w
zePes8{O|zP^G(V~Dx#Oqq@$4fGFp4lq^Xc4o~2ys5$kK6f15IjaVXfUwAMM@@Gbm%
z)ZKLq)Va~tG0npv&GVB{OM#7cP*5W>2HJ=kW+~p@Bl4<;P_iR5_KD#V56tGq6|30?
zh_szybf9uZ*Zo``)t0){o-vm9u9R0+{;(!x%?4_V$%m9Uc1gctjch$HXFYik?#X&G
zu$)yKZD|SY-QHX>7xAo8+jq7EvcFQ(9?K*u$wWPTpgKH+BpP9X58d7PP2Iv%%Ip=R
zI~n<nPlPIsnpO%TisXE+RzcSx6IIl%&SJgcwbB08Ri7va)UAA1y*(K5hIXT`N;jg9
zuTep3xAJ-RKEXbfv=@!Ns&iv$EY$9pRjk$p?0bZo4db}lK_wVNd!TJ~>?xS6ttf^V
z@-gPsM*V8lQcT&SRW|#Td4j#(dZo7<_+1q<M8RDC_fg#Yab*uBzw;Bl_nN5G`_AZa
zk>C0GW`3||)7xvMP1mez1a|R}@p`G}`sw|pAB6pl`k0=yW90+I>HYN|sD3lKQ?H-c
zS+0*yuR^QVp1iBrKe@BmF@AdW0JPfunLEwiO!w}6r>)sNerk2-!OU{AH(GW0*tD&O
zAD*@)UNnDpynpuW(Fdn(9eucMYvcN}GI8IWOyh^yC5Imlw(9Fo&**2)$~5ZP;-QDL
z#RCJ=`@`6)8RE@@+2YE9tNKfEZ-3+2Y_amg?&2fG_ty3d^yi*@R;kJlqwewIJE{lt
z<<-VNeqiwBudEud*IiSTcVLbj{^#n;=CSgDxT|Epu_}J~`u}+Kf%vp7FUSA!>aojT
ztseNv85g{K@JriYKKk+g0|T#Kz4_-~SpLGq@&o&p?L6|zmGdu{+<WGdm;ZTb&+cFR
zarx#)FS%{)?6(X)|L7%mPEMS$@r6gvoBzuA{H3q7zI$n-c=e3h1?LUM-#WWG=*?fP
z_qVM%`p~)WiEsMT&1Umy%d5A}$izRmsB-Y7vo}8T#Jp99KQ`}16aU}u+4{n*w+}pf
z=GNNYdGV32EnjQ*-`IWh*jYDy=ax(U@J02z8^>S1BlqJ&r^PS5a8~qqVeQI$ik!tB
zIBRg*(6YhD55GItc;L34*gH$xO}~gGzhjrr?deg=2PgDQZNKq}cw*BpYA@?Q@ejnO
z6ehoMM^Dd9D~672ns?h|y=TQl{O(#jG`D=T{LwZ09_?E5%9WQ4jg7tK#@)aBr<-4{
zEuJy-!hh~w+jaVl&ySt8eR5*OlCeKOec(HK>4qa`uez<VXvM191!vwE@0(=?A3A%r
z{^&)k8xPIDR^N2~d(014%{70wbZPv9SyAJqpwd{qaz*3sR<1DSw9Ut&3%5T1;L`X=
z=KO&pKWtqe&R#k1Xywdp8((_swr%xUTgP9xqjYTKOf|mi)Og>+Gv@h^D)nM<=GGUx
z-?H`bqwg+_p7U6#(fc#H;FnAC&d=`BMe4}f2XnQDo-eB%{nYi@+g}*GsXw=A`Cz~4
zDjkT=y7}czTe^DkpX%wU7Y4WYp4Yy;QOdmF{YlS6zNhrU-c#pK-t-r@y{u;s?XDL}
z)q2oV^UB*NC+BZ}?t*jg94s%3;?8`>3p?j5dF}#lZn(3%CtP?z*qEKGj$U+0_}s*z
z)rVWpE;ceP=IAG**)Oc?-d<aM_U(=Lw`@D?=eK@mVx``u-%=i^%`6YpXLldVEYZgv
z?pSZ4_jK>sJV))T-LZ1t(Y5-;T{o&%IM7u6qo0+?o0hy?^;rfDQ;2KvT1MD^E_u)F
z*V}a_?tkXOD7T|CSJNNOy_`Q~DECb9>L`BT>T<QH2J4}IA^%AGM4oo8SH&;<ELYn7
z!16^e=UY|}dL6p9!&}$rT6*)#%T6(q<<IH(&%IhBvoLq$!-d<cYT@$Gi^`^Jl?rE`
z84d3244-?z+uZ0{*mm@;<tkjB3Hmpyp~jyV2M-U=9y+|uD{nKW=wm|#b<8dw+P-1-
z%43Bqx<@Al*2mn>ZLFQ8_NgoO>??0Q`uNC<CF9>(6)|#|=c&EV{3Az!$8Ig_-rZIW
z>^~A6`iEL=x_)^;uQ)Jp=%YRI+a=259%3i23_rT4n!9-@4u?)Zu&2H*R+Zbsu(D>f
z)Cl{-hySLm7CjZ4os--5OmvmP{LXdtvv>KUcTcwO8SWZV%l;@*506}}?`>H#I>O5q
zH|I8%2L7yz&jPfE^`5vfaaK2T@`};%wiR~K`K7IUPpwvtsXK#1Elce^XAK>@Icy&&
zwD+wK&e*bEpS2|}ch=&#vyvSMI(Ee!i{mbDe&1$~A2rKtCR-cG-vP;Au8SG29?ezW
zZl=ed8lHX|)2mBGFFa5@$a^~Kp6#(Ws>-!67xCOb_mky1tgSe($Lx&Nj=wiy?|mlh
zBY$lOy8CZpbJMPPPmQ?zUR7Td_3Q~gk}DO)LiIo?R&93~J?(B5YY*}&>I%M#vAZ;?
z{wxlo-DO_v;3j*{V0dWO60;%4K)ZNxr8t}Oa-0F&uy}2QZyLn5y__wc6|JA_S#&5a
zuQSFE$^&hciQ39iY;?HUv~+D|=9`RkP1%R58yl<{Sm(3E3Zrul)hBtd-XE`5xo5sQ
z`JA`9r=d32Sx?7$N5DhZd&&Q^YUp5~s=XEFy6)%n6YSBw?U)UBa2DcVcbTb{>G)W`
z+Hq{Ko*!p@Tj#MB?<g)<fA#323!>3Eg=kOfc%kvhV6o~dX2W}1`;|AoM(YRG)rXd?
zXPvQ_GdEjGd~>!^F0V01JFl)zlzZ%C_aGDdy6|Xzb7N<|WTJ9^F<Zz4x}|VvB40R`
z&GQ~A)3??vC%Q~MDsV9UIws{ptz0W)%H^)Ee(w;qskFTF^Rqu-pTxU6*6O~p>Ya>K
z>r*T(2KH?CDv|+Z)ks0N98x`AC0v>Jn4>Et<&DsJ@8O#@7C9qUdHXcBQ;#|}-gv_@
zt=BW-VV$F}-h%FunrVIAX?>;c@<+Xgc?L1wSLYhF#SCk=x3T6JHc`G!t9(1hGB&Gd
zh+S{JIN&!7Szl;dWB#vcT~er%WqYm=>COUL%8{P%^ayYN+DNa~s;jNeI>{rq{6>zE
zLl+iyAe7(nxt(|Vi?S>kH>|d-vPah|b*kZ!P}_hhZm!XL`Pp8$ZNS=(<yF8cM2#yI
zJP55#o}n4FiObV{VI|ni{a{H2Dpqwn43DqI1FyqyZ|U8$K4gWa?Ab7DUG3C<V>sY^
zVOiO`0<CT`L~6szi=UnHeKCm#N%DK(1(rQw`#LQj%bIJssi~JWdFGxmP?5D0+K%}p
z)z5ucLDM%f@}y65)~hq9@$Ne7V0AY9<oCzqW>+UzhIkJ%R0o~|iyJB>3rk;vYZHi>
z!lNvg00#l&#_<UVPn0PDp=mA)*9bmo<?^xoAejha!g2wU8RD#XSnl<ux1_P780EV-
z<g+I#LR|vN%p;g+ag16Nh#pk>xRhI7^|>f9$ST=U;d@@1cY28T5fu@yF*-3g@X!IC
z8&z)CCnC;pi44}WsI{7_7ZPjegvU6QCL&&Rc*ILNsA!MGr{xqAtD^u{Njc%dGAu!3
zlN|V*f|0P}DJsdQ@Ti!0gP*$GImmb1dm}A0kNRLk#ev2pk8mU3-4DtBhqhFl+P>oR
z^3KoDSx_1}*nh{xA9>|{pS|UXyz}$o&7c0#9Umn8(7OK5{PM=VKfmVFkKe@a`24{S
z)*b%L?OS&4`<Kt|yXn*4eMR2+`P|0EAAj-fKYH<|Pe1j`FYwOKs~Z;o{flq^;`9If
z>GfBwkavD=Irqu$T>bfDuYGpgH~8J2|F(bK7hZk(#)ppm@|V|s<4Z35k1zexonQXt
zhaS4+8?SzM&6E4refqUq7k~aouYGadJAU!hjZf~o<{w|Wb;U<s`_Sjtz2nu5Tb|ta
zz4KoE!;5F#@!DhSzW=3-i@&w++8YLb@`YJ9eEEw`_qSeLbN!3|^x5Cr^fJHWgYNIW
za_#lc|KyA7Rj*dHye6|Ml6PQwsFsKu3{`637VH#mkCstP9{2TZMtDR%@D|RL=9P)*
zP9ACPDV&$@^mDzWdoWi0d66`i?IynarA?$h$^QCB+f`|dXSaDTG7Cwhr>jN*S)b=B
zws7Q=;(sg~*6(jsfrQJav6GWkQ5W@7;Lu^zX2M-TpRF-$jCcA$SEpYbn#B$?N3|!p
zmEYy5?tQaVv4HM6dUgfs@C20z{^WZ(Z=dy4wJdQ`%_l(en}SghO=2qOB!G!0gD(Wj
z6$sJ<o%lj>Wc@k`o2*kkGd17@PbGlcCQ*7#6HJOs)h{%%yz<*FQajf<qn-*j%Q)fQ
z`O*5rw0RP?vQ)INNe@tgQT9sG>(EM2%eH@B_B$QK#a8-)D#gXsigSL9d4{233Efor
z$i+tL%xf6+KnGJylJ6=5uG1r9D~z6(N3LpD?f@rI^}s~l!oEqvj6%>{inD11o>taz
zR*jA!$FtZW26m&vR@`RvISl@jejE4N(6j6Z;FSgETg4iS4MW#eqKb6GN((8<O;c8k
zSuWfZWQI7yJc@7|_?)vMu`NXG!x$OCG>;i|9sSCuSs<a|2Mx>f3??bd8%~O8!hVuG
z%X{3)ql!9J!&hq!+?GvEe)vkeV{H?9NS-N|Fxg7wXvwM{=rOM(&q6IX@s_)MwU<cr
zT8r5zmk7&{$bp3Ep7$VnjFI<7KKy?vaO8UdpKn8y;tqa~HT+lvb?1e#Y?EnZ={#{B
z#e+v4`+`=;igTM)iD%zL`y71M+Tp(8EGaTal%;MBlHj1P2MMnli8{0nk>&>3fOgcu
zlc*?I=&HJ|yr`l{U@Yb+BSWZl5^yWfr5@@Lb%zADrqpwkbq3kK#C3CNPff_aAc<(H
zoX%86W)rfhhS*J2tzuEYD_xqpV+3G%%FHJrcZr$gGpv^(c<y2!51;0paByZ!1y-0x
z&>Eeil`V7TvyF{BC1p<2ra?1ofbvGK4HTbtK_@nNrX)PwQBeq1lbJxPlE~uKVMYCk
z3^|%$eTa2W8Wr_dW~EfgB_~OABz5;kl2s8>cm59J{OJT}pBB5U(8UQxDG9J9DJJn)
zn-nYvoNSDO3Jw=kcHxqIJBCp03>Z6!5*r0tg%9vNLpG5WNJv|)41`!AjrN2%Ep+PL
zY2iD_AQeZ#vHXvSNc58LqWEIDtTF^J!O*WHfGjDq1dyvqY6<n0g%oNoK~&g^Bc^lX
z7b&AO>CKqLB&#49_yH0yXtP+WwR^0$lFVczhQ?$TA;L!qmEDI&+mr~>z$Y0Jc04i<
zqad_#7bmEIa8j{?(BL9$GRjEM6qE;V__-y_iGM1rWEQZFLofjYXJV2ICM;@HR5-oD
zfPy|}iDR@H5yQgGnip{6gcVE}aa+`|G(^DhN9F_$mW;QKB&sc#_M_oWq3C2xOi*zd
zLX?Lm-`{kgQRyeBFGZy@1<4SAE)dNfq?qKu4MTqD%dg~kVvFX_=Z7PbXi0)R-3*C0
zG6iQC05n$<$%|r1TTJAWHj(5>SY)FZREXdXjHm?|X_~xASjm1TU=Si8@fzQ7Y2_tC
znrR`)`aDQ8E<q!j#GbN*97sKXY)u+!7E;r~w9sr4ty8Wy_DOFNi%;;laAL0`zHU4*
ziSFc3VQPnkp7JN{n0qGXV#sd<l!61Dc##v8%1CJ3izSHbLNHi@Ce;b<P@J?L67JOf
z)x0n)oB&@L*QSKxBUTFnOp)!XCk;169T(B09}k~s5>AYDZga#EJk2b>txG*lR$aVv
ztPwA8E*W7ApV}_OHfeW4)9@sES-T1)VJt8mSYczrmUx?HJ7FTB4O@;I8vS~ImBCWv
zQVOZ+;R_*<M*A$dK+!DmNii`WsAhh2yNm}8d_7luF*tH!wAjIiH7w!<lQ>OYe0i@-
zCQm{dn&=@?aw+lr9|vMifG#xgykm7^i6<mc1gDlhBrvtVVxLAu)<r1ZFL4Y>$;o8y
z00thriz!YPp7hsP!YKq!Q&QxTO2&pM@kaWq6ogjFDg&avwU$RtZv{!ZgW>3j7J5{q
zu8prp!XPc~NHv(%vSk+!i<R*Jkm1v?v`A|O5_6D%78^#$wx<)71Puu-PA7Wgw>|RE
zti_RLD7G>JA<cn5O~PEwFnz<4Ll^QYQc1*dX=#@h99|itk6TiPrVM|_fhgT%;O8wx
zHekeFVhmn6U}na)KKNW`Pk5+2UZ^b!n{YX+#HT=Y63Q}P`i?}IJ6e;K1THm?y_jFD
zSWL9oXgnOisc_{El{vx)(JQ<DBrKz1Xu|u_H<kL&H$ihvQ}|8*OxpE0)VXY07pFyi
z6Z90zQ<@02T>4kzoKeIyeFKN(QW8#VNv0$t#1o($ikp<hiHI~z9sZgw;i|}8kd$W=
zMpER2pIRyuFDa#FB&ozM2gfB4qQxAiH>0O`vPk<i&<RBcO$CO!@?CXJF%F(&%uASm
zlk0RyZI^^g>aX}!!CZX{f^3mb=Cy>1MqGh1mrXPq>Q!Vkvzg{e3Jf?Zj-*dUU<oB)
z;n$!kKk_7)fR-c<bkkQF4Bk%BiaI0o)K5Y#e4>(sVG4-AROl3P&NE~r1<8j_r6ux`
ztWB}gBzUuoG$~+_O|B#zh|nxof;j<F@mR0907r7z>pHT67O>(lCrM%_|D<#c=mu>`
zwv5!@-XB9d0Y+}e1g!8_E{{vn2pH#{z(jlzMs80N-4dn6kr=V!bzo{+6D3WsDU#Bd
zN1Sq@CpIM<O<e4f@loRoF8;4+gx6w<NoB(0z~H9+AfY5lbrNvJrbQft=J;=tDDJgE
z<Ptk*3nz=7YDIHfGZ_q;=}+=p^5#@0rYdE)B=4>a#XkuovkBbBE$IUnq@mPL%PO@o
zrN3D}O`r0g98T%~U-18T*><9gC6_lJJ~^*xrTa?iAc54DG%lr!pVCtQ_2Q<|eiJTw
zQeDC~75`1?{<U#p>r{LHcj@`<c1aoU{>$Ia_p2OYduns)|0>77E%dJ~la&9>+92c2
zRNMcxR=!z1ZzNZA|7!aePN{>_E_<Ui|DN<WvOg`yH>>Nn@xPItH<Ev{yfiFwQv8k5
z{(I1qvF2;>o0T=yrr(y=G(PoH9aCleCfaX`6B#GV75<ZDpBzqQPW9gm&s6^3hQGeN
zC)_;z`e{#$_Y(hl>0d9esVw0?IsW8u%KJuss`JgJOZiWhm(t&ioHxUBviyI0SjzaV
z?!F?G@n-bD8J<+$zt;cvmVL6klf$WfQb*~P(!@{eZYu5H7ysG;_RY@xO)^s(QvWyc
zPK|p#{*&{chEsoP`hP3_zalHO`Hf_x@nYLl{NHNp)O0cz`%3D=Uq6*Dwxqh6_bBPT
z%CFH=yHoy?!&Bu>#Z$hix>8yyE7hH*J2^h3r~KllJgF}{f~PzZ7D#zdjuUzsm-2}(
zFjeNs@+AKCXhQ!@kgkVPU#Uk*d^_l+<7uqh^ORr^DD7;h;`%6S;VEKsP3QLLM8D4+
zADbB_wKd(JVc$(ziRbRGnP*@2eiw;g52{3)G>g{dMflL6h|#!?#-ngSmDtcG3Q3uG
zva}1;Fa)syHp9BEK@c#`l?Q1eGr78+bHwA}gr3q;Kjlxu|Es=~SF_B1O_bzAE{PYt
zQz4D}ZT6g;ZmNu_cq&i)sW3Hs0^hnvsXfC}`QEIasc8gHWuBZqrJu|{HO<txlheNu
z-_$f5K)v@@!zV(%l05$Z52V~^?M>J?sMLK|r=j0erYX<s`L9>DugCXhX(!8jBfC!K
zdvo$7&y&A0pXYupp%u!BwXYOdD5NQ1r{GOg|2k=^i6={d`}K0>lK4cOh&)kYQ|0}-
zwkAa%kFm+P5X%1MUBg07g;rE(mEs>LI9J&U{sJzZ*|@#ER&Y<_7%toj{9=mb3Yr(5
zlPS-wjRcxP(}!N}sR%^)4ZHSo{>brnOZgsuK<>UxD-;py;vFKmJ82Sez{P=fJO9wq
z%8@7aLBS@mNiFF%EkWy8j@#MPD^@n2X|ezB0GUlh;y`6Q6(HW#8R3WrGbvj%4dG#6
zIdI|frSYsBwJL<h@iUnW3nKD;gCjX>0{N*?hF0PP(yG<qOmMP~Dj>SFuWZv6slTsx
zNJMIz;D}KgH<cxnMTwo7C<j4m5+N@k21$&<;v{X8;A|IME@VpB+1=D>d;=Y7!f#ay
zGA~aB;>D!YEZs(?1!ONbN$Y|!tAd0H&cL&d$XdYBvd#K)M4Uy(lNuL~O-@uQ4<98)
z*k!44qMQg&#*v&SVL>9#TeMOZj^mI%Z-kH(mIq6FBI`KQ$%suAPl*t{C%~wdG~oK*
z1;3XD#h3nvU5aO=l95rN8F6${=z@#97Q*}s7=vTEenqv00L0`EdDaDRPSl7yB9xMk
z`#gpeF*+r%3NyuKB0r&?Py@Z36kj=gDso)DMlnEq3Z)dmB2E}L0k(vbaFRF`p;H!+
zWZ005CqNQuCC7m$f64RPRvtLYGk?Mw!B#$LBBnHXhtm|kahTI34oxwloEkzsF1Klk
z7GsSo7m3zbEZ=8R(>s3r0xd8WVw#_HTyuG1Ads}~S)L;}N7X1(rK~)MT9)M5rM8+w
z0*P+p^IW(lZQemyT+8K}WJ;dU+FBB97K^o%9yZ~-awIQ|V}^jRBpHL2f(B_m-Z2SH
z-l;xLLyR-k9n6Rmo0QS5a5z(wB)FPO`c<DYC{MtU--B8hd1}kg8mlRBb;&f(#pQXN
z$6p^woGuyv0Sirl3|X<qFz|(!JCf}qe`1Op<8$WuG}Z+0Bh~9-J?lt8&Ll|l*aAoR
zq(rofbR|?1%_zV+d;}*U1sK(rNS6BjFK&DlGA1`v?4inHSKKr;;q+>ufx*gaxJa^2
zMFk4)2^l2%77|K~iY7I`@2QE&k=MYT9dt1bNC^z7sMohHkF*2Qpc3W61@Z*eaU53q
z7EXp~dN43x{5!r)RD2DbguyTct-(mfv|2<|P|Rz-YN&+@P(7CC$bl$O<qqTF@iCF0
z?5URIhG<|6l1B#|!ywMHh!tGM^*1d_2%91_CxhuJq}d2ja>p%{^xZzCtQf)VTT!D!
z)Ch<y0Z$_kn7~TIVHs&@O=w6ut+b&)qDCl_E5jO>=gVVN`nc1JfJDC&q){ymMLP@V
zOO%qVY;<HvDc`+=Ir%pAC-y-Rb}4Tws{B}jb>qoXTc^BvcEjNoee#+&k|;Zp0oLLe
zwL{SvdHF-m6EPz4<LJ#bg&lVBsw$^*Ga8d&8asz+j(V>9P7BMc1nJX#%AcwE;DBd*
z)n^rjtu^Lag$@ivf1c4n@H&>$SHQT!j&h8Q43&wcWi5#)uA^Atmthgmi45^Q+DXAz
z<z2|Qlnj$5@;4^+X+^GY&{tCe*eoCEFF{s$*2RIA-b;XrBB>jo-Qh^)NUib`C#pGJ
z&dUo%UTKLWY$yQNPTbLI_xlPEPz)z!xnlAlC~rlom^@p`m<j+$<&FTCg%g`-ur4Bu
zV#ZRB(hz+n^o_(a-fES=a?AM{&O33K9xIn>B@s4kIHSkpw33fvK*oN}i=q6)uns&O
z<pZ_eMYM5dNyli*QV$wNP_HGhE)s35AI78rc&}Y$n?$ieQ}ezth!smm85aU*E~_<8
zHfU{N0$`BB-9eTNx!Vc1<y-p6oYm)8Xu7(JZlkq)+q71OI^?ThSSQg=EzzFND=`Jf
zXpk!ANiEPoMnqnVm?F#tVPbp{W*^}kDCe*%-yuS6(YUf928ae4*r(ly>yaZNX`Gpo
z5ljA*4dTdh*u}DN;mDNPK_*Od77P8FvKRpvaWogDK)?s7t+9lqNI4vaV`jukJ;yr;
z!KeiNq8)SHOBV@=jszr5Ks#6LC_203xCpW_mjRWwDTvZgl-4+&v?oC*1C6-IkTL;y
zQnX1)Jq?{ABZ0CQ=t;_?bZD8-iF0}J=*t?k3AX7EOAk%$g(k*`F6~^-m@|F}gNS09
z)P7I`BNkcI8Lwce=9tzLqLYGUSTTHm4S^^oU!<^d&_m?75)egXP>V`WS$x275s?@n
z1WN)f2!5}X%%zZw`)SC!1v=`)FfS35#Gz2Te<gMI;YLDruEvG83I1`d7K$gfxJjG<
zFM$BIBCZxksW>%~<&c0ZpOSWCTv!|{4#S-ETLG(`=W>}~;*y^ERWO}ckQ5OlD?|q_
zT575ZI<X^B4b4A}5ny&AC@()s4A=2ox_~HY_AAK@{|>Bkjc#gBh~lP%W+qNV@b2VE
z;8;Z~yizX4jq#}wu2xcM_*QalWw0{I#{!)+F%RIaPEwx$hMtGk5j4yjwn?sN5O)I0
z)oqiCr$aH8nH2D}8$NZK5t?%3WrzS6XBY{T7H%JPK>?&`0A*!}ZGvQ~8IcE-Q?4X&
zJh0KMY2vDnO9ts=+;66otY{f$#cUe0Yqy%jA`U;*k(eaC#evp|Z}4h)9CV4Om|@pS
zu*r~ga*4y%qR51i^#nchxWy9dKyE;YZ^6}CvXp|MoMP<+iyWQku#C}yp9CU=`6;N$
z6p(;Pkt8>mV70TT>e>OZ$2olJ&((}C%WI${-@NTTASeT%q_VzY%x2>AM2d8a^ft;8
zEO4<9_b`o*WE(k8sXS<s(of8l*G?q&x?qK_f`vwP>>zIQh^)YgaiB{s5@tD;J!&YM
zupl#%Qr3#YvRvc$dAyk<B7NV;kVblzbcs$vtX#0gy%?-0R}Beh9v7#b#8w*!9xWqw
zy5$S`mLk#EVz5PHx08<xgmq|18`AI-z;&%l<~5lcrS;XK(hfm|7dcvRumV}N4mSob
zh#0{6)pVg)qMIkDd*uya=4obX-A9xZS2LNqROM<CL^86a<_s=xvElh3vj_n$R)csF
z5|DcQ=U#^jKfDIH)KdynJ!AbClXB5YGRtJ_`S4MMFe6iN%yo5;9W|Oohi9S4!h||<
z?So_<EDn-#q{R?I20yOu1dAH@S@#(cOVOK(Q-DrCtS3aLi%17$<&|kKj3(5ySb#8G
zWO}AUi+KrALrj2Ql0uCUu}+e2YHo5*LawM}{Yko_Tj)qCTD(Y2fGiQ|?w6ds#@^$$
zHG1eDra5JlEO$X<o#mb!JZBJeHqoiPNZNM0K}HZu*(iR3N)tlA#r3qZ52zwmi}CK=
zHOu=xB=`8;a7a3|V|c>9LoGEh0&&<Nz9BhtnNl{f#K|{eu+0Wb@xCMPP+LjFsuf{`
zs;-n|eFg}t05iM_dL7C@O~90~&6D;lU=uYiO@W^RhQ!N?BO;G~Y}0%TL1fKChWM_;
zm8bbh5TqedzJF>E3qL&ru|?HkU>4BIb91WE1mwL<DLw&bX>r6BOi=~$8z$Pg1wRv~
zC-IR_Q-vyWYq)OAt{P%kM<WB0K%58~aZ4g0@?E)Rq$L{MxJ@~&r56WQ>~(21GTJpf
zM)K4Ij~5AC>tJ+|f&jFu3w$Iv@I)y8StkaPMI!ap%$M*;f723Cg0Bj<sG#G>pMyjt
zt(T$Km%3~`CygM<3qeC#k!LAfc=hoJ-nUN_>7*{;A(>+Vl{ae$S)3%AZ-0r#veRT7
z4PLiMa>5J5Nx?&E+ONSSq>T8pwOiAv7U?tAOy_+y53<jIP;vsWkesPg4BiRwoI&&%
z88JkXb|M{vmPls#8gA&{<MFLADH<C}U!=H55hL2lVoviBHmH7ydXanzXc>$GdGB`&
z&GZpBI1z8uq(~69lB(??YzPCkj58{&Kz{0!&O*?rjIWG#6;r<wwGc(Qm<sCg2QUFp
zW!Ckeq(I9qLljn>Xj@3qu$++`N>xZ*&K-2JU=mwY)@mnNjHwC%PaE!A$e<w*RO=c>
zvM+<5mXStuN%os^>u@0(a#)Yjb{Az!9)cZ@UxJ&Fjg&BPtqJ>76iYss1DT`SWkdz&
zix|uOEB(}J!d(1I8-q0gL}i5CF!RDiRHQmA77`{<fCdZZ!eGb;Lq+5!m_Te%vLJ~>
zSWZGjOXgwqdC#Q;3SF|N1)c6(5N(ZoX5DoyNh4(?w>H{>07!D<Qw?E!Zw`v~M6Tjn
zd`8p&p?(s+z~v)om?QxdA7*57!I<3q!7YO#z(^t)VWE&kr^k%d>JcX6h=+ge7RM%z
z76u{m?G}PbT{|XKHi|||b)#!4v=ET5sc5BaLboE+U6MyBHarl^3J3Mbci~zrR8f+w
zJ$8U&5G7J^ba5IagXW%Vi9rcyk&gngB)Sq|B2P;^h`fj|VT?`qq<ss99N8dC#1Kf5
zvFep98wuBiT4a%!uB<T?S)^@dM-Y)6_L_v6M!*t-E8jGmuF)#6E}^ppnYlLGr*yK4
zY_?Rs$P`o2&K8eOJ%NN~5FOIRT^KQ)@|C_scf|a_P!dU`fUAyjqMnA~YiM%8ALl~s
zBzfQ#{hym;?X--j6kNL{I)Ub=O3OZVtj8!5(Wo2ESVOmRsP^_qy_ifjDYO!N)LAo|
z%4jKT&#`(`Mgq=ArOX0?32t3PE$q~SXw~Av;`CY^*SngmLInJ#R3E$0CStU2_!V=B
zWLot!4}y>+W&;s@%^4*FVyo~o6e?XOYM4P%EHui~8lQNX8Un%jF-Xbt+*m3YE2Q|?
zgEGVfhJhhSIv?phqh){v6U%gz35FHw%Wyi1*dgU!5`usjt?}L9jBmKmeH@I#w75fP
zU5ww%3z*>&@qpCh!M~MAxDdy`5hRJG_cx0@v<b1{JW;QDxr|()d#9gbIplU$0;{AS
z6+Q0hb(IM-DOC-tn3(uz>W%vNCX3S>Gu;#^9~tU$j=}VSI{AFdRML33l(Dl?=rul>
z>(YkK2y);x%BgTjomb?QFCtw301NXHGPWePt43KWBcgF?^3FKI&q6`g%&PKxn}(PY
z@qF)vHpv8_e2?@77N9H+BCQ))X$yS1A@cJW3e0v^$w+VlTufP6-6Toa@Ci5PLCj%G
z3Q>*~S)bS@T!FMuGGF2Io0js#cmsb-8x`b4OSh?YT4eb_9rHlcgG%H2QqO-V>tEOm
zj;HcUW(Y0Oy($o95)x>FHg2vbL}R9N$IL^v8E5dd`yWgw1j@$~vxLHENJb))j=(o{
zJPB!O3&vqQ@O91D3(?Q>2_Y(C9T8XB9(}}_Rpz&lRqV=Lo_hFFsnS*iM2urLh}YoE
zAL<m1Jp!&YnsTMBRfWh>nY?J^__miK6-~0HIu0d*uGM-*B1K5V6GZ_dPFP?b1hmM4
zL>(D7xrB^n6ei(h-6iSZl(~ZXkSaxB0M69l;Rf2ekWh#bF9@vmH8q^tZe`>URW!#y
zzIWS@lz@(CQPwYTH}fsE&?T;^;esHBb@^Yjpg`a0p0W$af<@}e!zx;Y5Y4(_hkl^U
zQ^$c0W22S2a;gpTQEv{TYDQh3^YmLsx<uz?hP78_#EV*UMN`s@TINdbOKa+FSzY5d
z(aTlClD*cO_jniYHa>~NL;QS3)w)k@=u>>PiQllGp&IV?ids>D^W=W(@`~TdO~aCs
zD$e6xS)jkS;!F3Qxvogl<%_$j!wWCq2mY$s>R!@C9e3sDgnH%XQZ20LE5n)QL0usy
zZ0AL**Vck!RL`}Tk#am@+SO5=yC7%{*o|Abslp^WYKl6rA)_pQpO&J`1a@AJz3bF-
zR9~S?9{iEI-)e)i=31kpC0)^GegZr^^y!Y%t2N#IP06bY7f^eC5b3V!m@;Ep#u4M|
z`&lZEW;0foN@~Q94()8)9QH*lcY~!B)!JvrsE$e6nPMF&16)*)j0P4Xq6KY!Pl0;m
zd%=N6Z={=t!^Ib=e_s(TbzL@8w$)2(Y~z>cvpGIb5)63DY<*~Lsc$-Y(T74kD-#D=
z=TwVVRvmGm%6A!!XQq|-a?nFmYsP35m-?o467E$qTQgza#QeA()xmT8)z@bx@`^FF
zOTI|dTle$jaGB{lq~^4$N{dm$sL6*q=9enR3)yu%@-wvP*>x|_4X?O`V>s9z`D>*)
zdzJ0H_U(tZ#6a$Q1FE<N9jx7J?B29_$7H|n!Ol(6f2oaC4Wpv6UA8dXbvij{d+%X7
zZe+tw<LPr$?F@>c!&|?D!s9Dz?dGC6draV0>Rq#f-nm;EQ80^nSvQWZ@B*Xf_C<3p
zRGUj`pH-bBeXM&s&-FrD*vMh*^WhA2$9QBqSetpl^r+Kj3hgC6r89Cg*VA#AqOa?)
zT+7!Q<1<bj{Ud5SQ)nf<ZZtAg&6>(&{F0_%NAwvX`xHI7h!3<xy8AwLI`tKp(HcV~
z^GDR{_C(6;hy?0jCS!lN@CNy|ZTlb62fQ<8kB%4b*j?8*MAOe$S9<21H>)SQ&+GZx
zk{ims@19+{KD?T6K5BF?%*AiNwzO^fHEMGC=848~-E)2G)dzm^-nS1;&Mp=wmoHkm
z?VJxDD4%y#ZDRKFwT;=!AGyBt_TBrIT>e65W_jh&%<@OZmt4Mb-;(zZJvw)G{AeaK
zI&t3R^Ik08F>rKlCjQCXx#2|decSdI|6t`$uFdEd=4Sd|EZ*?cPs{n9o7yv_7f#8T
z{pIsE{9?BL#Pi|YaA5k1Cm+mSRQc)h;(hVFi|^Yy{fyOrF}qm#>CW!^if6uWbjkEn
zvVT9jsP5gc(LOWhYRT_Eo~Kl4<bTY5dD<6d_n&)B_Q)TvnQ<h)`p%w%ZMQ|A%3QR2
zeD3Xo53TCje%GqoY9p6?C>p=ymfQEO+WYdZ`5zzp>YR%w#^+qH^5u75a{J%^&c!o!
z&A4R7OY`4)`~53!-S){d-nC?;ea`LwefFwX9$kIsCmy@v0|zc#^?^qg&Hh04p^L7`
zJ$BKRdmdPI-Q%BJ{{H8Wo%NxuKRoNs@xAlk{rFGMy7SbpT(LBI>WVE-z4*~p_wD`i
zS+AVEqP=|U+|rT#b8r9R4;SD0YR8OIZmG<8%kpP0nbY?Bmt69t2j{O`_2BX|@9a2t
z)%V_g?j_H?bjfK0KfL&~;&s!y=RJ1X%)@t2t2K6P=$HKJV@lPhosliKUfXv1^!Amx
z>2n842itBva&YyXldV_Juie{s(Vnjda}Ru_=<l}Y-+H)l*6Q(*m0QZY7F}FEG_8H;
zt1WX^9=vqs_P>4Cb&YRj&pq_iyz{p|Ff$t3yJ*(dLz(%He|^TZ-QzQ6ePZwY6_2;B
zy5YImtG4c%wfr5sKh^fTrTYA+r!e2!8qdDwxy`db$hY#|-xJMQvujRa(Jr&Oty|5%
zV9D(BFV^qRbWL36XL9%WnU4MbvJIbIRM_y@rT(>-&ARxuzF95vzB2o*-~38+;n&V@
zS^UzXnT122nt9PT?>*zR;D;Ce*~-G%OD9h|rN)}@D*3+eAnS?AZ=Bb4pfacBK%>xZ
zPP^JP?haaa``wxCD(W$Re0llE*JqRusLTfr*qLXj*51q!)s{QZ+BVb^v_zvVr)_$<
zH*;~cq3bQR?94L{t7&)aIXJJJy)1K6M`d=rrzJDAd*PzZkIX6DR$7>O@1EgslkU!(
zvukGgnoo3wZ$Es&j0KgaxPLDAD{OuCrGpR8?T+@pZSn4JZPcSbIlUb2Z=1ehR}@YD
zEHiWHAJ|2Hc6RB{+Rk3NapAN}ZofWr&V~n6XRs*0JZPELU3z<4^u7POsE1tnlDALr
zdmd{GrBk=x`}?PCAMUG;p1RoI-LYlOc5nT;yZucWJG~S|?Kkj&-nPt;dS^7*>UBn~
zmE86q7<&2Ag}T~u{<7R<GdA(1vG&^RX^gHdXGW?mj-~|xn+ZeDWz?1fwQ${%w!l1+
zRW}a$YM|6xjH8x}H?MP1bhxd1Xm?bMt$#`vzvVgYxsNV>S3SsV4-0*rxmj)b`!>(^
z4yl&To)%TwJu{=mX6u$Q|HAUN;Ox@mNTGDgdga}cXPNQG%d+?R#bsZb5lsKZWoLFi
z&%6^nr_}f~zjaAV=e*HH9WQqH@A&CF^{({{wv~}e;aIiNGSp)(Sfah<w?|`3Cf3`I
z@(X^~ylp|({QLf<e7Ai<w?!YG*H_!I_G{UvmTXXWUH&_z9an8H-hcb!X5Z3a@~-m=
z{R=K!T`S)*>ycf>u19u;=LUN(xicDHv2pFsH!rwvU;76ajjcS_f2_OE@zTQiBm3vQ
zwfOm!*Hs$pFRI+LA`15}K4;IaaJhOx700%A|6Yd*Z*26u^+q+&eXZFPT^01@*6o^{
zdtFp-i?h$FtJmH;eam=p`XI}{8zq0a5&EKTzb+fkuU4n6ePYyaJ;ujwnXeh7M{bTs
z&4Ph$<qgHQvL|Y+t<}C#iiQrh<tDz?XGd+{xz=V*$sP<V(fz0PjoGc|SbOfxr6)?;
zbfYvlIUanl_Q13`{ob^hwWos3+Ri>l*ITrj@UK+++U6ee^dPggZsXO5!h#v$;jgqR
zbvCNk2UiU|t=?hoRp)fHvB=}MjraW1scq48b;V)RdSx89bR7LZTFzsg-M)J>vkFU#
ziPqT*qEEJM@3^PMR35r+=;)@dcw<AU8~%)(82|dRr><!zbKhYOkW4nrh@1(qs&`kT
zrEjFs=Cd|3heulCorlb(k*E<zM}pdJ)iSih`c>QT%%?`Ycim%Ws<pOd`|5CA^+3+A
zJ*C<f1h&PCKG71KYOhpRsJ8Olu?1ZPyMP0o>r|yUr{eGSD}_;CEnq75hdz?iOLpbV
zXS$gC+W0Q-tjl{!`OC3CZwB)DYxS+_wmmiPwt8!DNy!Tq4tc?KgQuRdZeU@D($iXd
zk#bq-0hR3uqH3czGI}Jc4sP=Nn0-zz)()y6-!8t^qf}dEh@Gw`3)F9mDY6sDnyS|x
zv1~CYbq~+p)VObk>%QJ+TlARqd-<u^zI#5wSHfiNMxh0{;g&%4v7}O?`lw%RJJRZh
zhg;qj{Sm)OVFS~Spqwozx!v{ZfzDdrQ<`TGmb-ilYFX$Uea5Ryco@_wSKybdGCbGn
zBRpz?X%#)<EiK(^%IY$&P5n>4-UUFa;!5~G_xA1a&M@HZrojP0tD7EdUfSSDkf2sK
z4Gy45^TuZyL>KT8RD1*#YR1vUB;W2xqA}S`b|jkBJlP~Z@-Q}NT$9~z|HP=-m>ALB
z>_6GvB<`-pY+U90ow|d`m;Ju)%=Eogr%s(Zb?VgfR^6MG<w;;HTPKX2k*(RFy43L2
z?CoqsGZ|SyPOP=k*pdw<w6cdq-(7sy6N)WK(LW0`-E!C>k0FZ+#*7%fWfBK+nDJ9r
zE7B=yw|kPg&-R4C@m5+QBjQ@3D+^ng&sL>h$Dndp#M-cSp9!q2#Lp1LRSj|S@I)<D
zu`VBm&XppNJ!Zd*YfB&l)i5OUCEk-soERsgx)CdpV@lCtAl|1h>+Im=bmsiXxx~UO
zKhhPcCF6|R3n+oMG#c#dHc3EagDm;3Up7Tn%!C<Yvr*$z0`Pc1IO9D8F#%+w6&QFa
zsH=lHP8>pWA7#QE-bhDO0}pcz_b<S}N#dT|sbV(rEAj&p<*#|{R!>avSti9U_B0|E
z)`$d+F5;qI7DfV$fq6c7%Wo8nO6(UdMkF+v3j#8uKM}{UQ%p}ci*{DSLlsSGgx|^!
zNTPr%wE>-l#*)`j9n>`}O(|e9yiti&#;R4ZSnr@z)dBdW2W%v)I>}Tm6Ff2e=y0H+
zPy`LIw82~qfw*}c6j_h*!VugYxm4H4pyb8TUznzkdSC|Vh39G=MV=cdje^psigdle
z6QyWq0DX7y>@VVIt54!v{=e6+|G+O_T>jhF&i}b=*!B7qD_&o<;d8I~_Xody(N6#F
z;tjvrvGbYd-u}hg*Ij<s&HwVqH81??=9xcvZr3k1Klk`uR~~unf|rh5KlAP%?7IKv
z?>+X`vS0D;;x~3(e)mgP-M`}pk3D<Q=N?=B(j&XR@$ehF?*HmbkL|eV8;>pj(IdP5
z^WitHdZh2jV{6X)##_txK63rfkGyg6>wQOlvF`of`tenFzwy4GKm5kb=dS$K7p~v^
ztqZq3{O}96Jp9J2weLT2|M^G0c+t#<A6|ZC-wofGaOB7@Rvr1}u7zL!*0$chTfT77
zE$@GP)ses4HS6uSx7|Pch6kU$W!7Ui(dLp(8|k}zJ6gE17EDe0Z#^b#w#yvp*dk4-
zi><ASTG5VLE7&59fqG=^Vrkj_M%0lr1$yEshZ-HtdP8Dbi|9$dE_W#Ch$l`n-P0>!
z^-#_ZAIgUJJVmh_!<2F^4>^W~XG9$(>Fc)Ty@gs~E`?zz@EsHD@)^z~>@&5b*k#K}
z!It(`?8#p?wet3`-Zv68XMZ`dGar%VJoU2Gc(E)f*>DkKcQXg8p=hfm-s5``RhxO(
zf?Io~It`l-D<$5;N?udY{I1f6Iqv}0;H}eu2}ZFaFdcQ;caWoq|ND*l^Lv4w>F@c~
z`G3Ow0m&bF!#_k|#|p+@j|z<E4|vlOvEDMG?@&EIJ=0{Jw5V-%^xdn*ikVBK@WYYx
zFE7)Mi#STB5+ts{N*}r#+1!#K+sz}ME=|qwYIn66ZH2T(!eD!0fOdm+au|X7wO*O>
zY=}Y^RgyLYJ<d?GB-~Td7*xj+qogEIBufT?VSGTav|OE*oit70Y|<=8LlXEUg>GkQ
zh^yk@PX-!PO_t$%8c`S_dw|a%NP&*CC}r(xw<$YAlgs;q_jr<~N3hEzw$&)IV)_11
zz8Ngg#sVe=2GtUcCw|zMbYTvvCgUN)erRPkT-hK=C0TB1B14rII=H&9VQCJVdz8i&
zNerFQJ=u}DhUX9le4s%tVK9J2qa9s8L@)jY$gqw#X!xFT)a))IGo4MrCjJ2^q`vHa
zLw*eUBOME=c1J<_puj9Az|!#2F`{`7L-+FG0CgctV6^LEX@i9mq+)v^KAKXpuXle<
zI~9)?UJ4HHWLQEgL6cOI#A%4+(;M0{oC!>uUjq-rfP;sTQC+1g$q-_dA@8<uM>3Tc
z0<D@h$qPLVYca^>cZwVC4KfUXs>){1*5Y*%Mv5~C=qMDbt5R79(i&U|s~2!pz~OVX
zv@eW0JSUB3u~!X?{P#H7d>rp%O{0f3t<VxFmQ+QSkyS`?2D`{>JU}lA-*)J>ds>2?
z`Ew=!2}8i~>u0Yl@c;`N#h0sI4#i;o1&bZIxJT>V*Piq^ibD8Ar5%YJ)kIl2&p;nI
zeh3P{_#fH9S;U9R2O8aeD2R`BT3$7%-x#bw&>)==o8*YCj5V()5WpV^O|}?kq+$aD
z4us)7@O;=yX}L>Ot+#E!`VXPN9(B}<fwZCZ`_F~(Ls6)ABwA%j5P-xEYjrWavb<9Z
zmO5-eq8@No5qP@=8%H%(0^RF@OU$1W5Z8MtQ-JgxvYO5aZ<QEop<0JE38lbGMcWX_
z=sqaER|g&gMgnCAjbq=DQHcso5TvEC!G{bpl%<1ENz)XqvjHzg2MB7j|A-sGL?>Zw
z9;9_t6FM}4osTThoZUVOZBH4N;#`-}qOt1HGa=qG$v|DyOi;d~RN)?)ezQCPp)&aK
z)fS(8!>N~mwgfh?-W?G`SKQ%C%8YraLQ>Mmo-xlvx{dnaZ^>s84H^bmo*m?*Fz89s
ztr4LZX_t*+JO_(opZbWe0+z^xr)SW`$VgE`JfFxp0!G34yD@w}Kt@97y|IBb7&bk?
zAdNfk$qx9CUr<5r5w*EN!@kK_dJafnB4gwr^ercry$Mp28GgiRz-fY->Od(N4qLt@
zFo-O7=u73vFHU1|?4>$}#lRJ%UcpKoLF80cnk<Pi840{#2n6kZ(_w26Slr~AG<k<B
zPQEXv<NrXN{t7jC!+K}nwPEFD9<Li6n-Az?v<OO362OL9zUe`sgzw3u`gWv4`Oxu^
zeQqAerphJ^mjNz4_N!8Y1wJbl+ruH@a6Vd$)<*g7kY>(XtkFQpwfs%)AV$KRP8y-M
zd(LA+%>a5=@Xy)Qs%u7d=@d6t2j>YfHCINt5+jw#5xhMyASpgyWqHaAfd^#({a^ud
zlSI}dm5ue<F5=gX)mG^s(df*jG%_EuK?i)~#<z_n9}HTJq02z(p~-ZU&u2;iy&`-e
z5F5WYf&h)%37&nBR}_swU;=hh5()CqXh&fOB%f;9Q4AVnJuR&ZcbjBEiqY1=qj@Od
zFp<$Tx9&n4hT#NZz8}osad<|{m(ikx_%=xFE53WexJb6dW+0HKRVIZItJhAwv?OA#
z8OwIb*@*g!by;T9!dJCu9I$jtdP9aW0VhbvzwSw*4FaJ$lO_j%?GRg9*eo+f6L$Q3
zK@CDSOahh$)kURlo_qMpsrY?{sKiH!gi>DKE-WcaG(y`On(nHl`N%T}FiK~97FFj~
zHSek<A5p>7M7+&f_lYP(;l&E};$SIzp)1jL-z61ko7m(j*o}J<hmBIwom47ArUOi^
z2tTS%NPgx{j<Pe@CP^#42X<sPo`wW%#u^B`Jd|MQ)ui6ydkX^@LZLfHiEvfxT3u<9
zn`#s$+EWa}mLV~GmaDxN7yU$}_f+)^wPHCp$P$VcEZMX+I%AMB8HUiXbB#2uRa*}n
zL^9uBk;n20gD15;nPL$^Ttm>Y8L_Q`bcq>BS|DY%(W`cJBVpXMxhmh{h@&WJSQ*j>
z*px$oPXpA7gE47RMiQdcxPb|qAc|xIhxo!k216q<C+xSC7O4o|MJ*ntWrmaH6E%|O
zdaKnUFaD{EYGv3eL)%9?*B>!^A)e9fxoKUpk|0KijH$}LPq5_F(7TfipNOF=MSmgb
z1jrXjOGmAS49GCg3@s;iJF1g<TvtuPMu7oym6DUVLg8V(WG<|zdWXw>m12RqW{k-h
zH7I=)L@3(2^_(1{6w$abIwDTWoz@~>dkumcj3p-Z2(BXE{y2yFc%FLLF?Eml;!SE3
zI`Q^KcRCABydi%ERW1sHFlmL_5+x;~nsF_WPi$2#??BwLjCA0xL)#Q+&pn`!mO855
zCsuF%qK>0ZjVU7z-3_WMjX|}C5^=z%pwAQo9i^aAGNfUf)k~Tdlk+&=oT&SE(bR*=
z{XY)f0ipd58XJW`459GGI6V+V>t$09F;yoSObp$D)P2KB3Lgb`loJjmOw-93bd6hE
z0-x3>YxNNyS?M>pX;w&KfCSYAsexb02cM&7G>X<lsOJOdGlf9z#88FD;!2GC2$#Y;
zkv$uq{?Q;UyG^&Jw4rnuiwGnL1Xc+nng#D@8<I9Tt3f!dRv}1fCY+)GO=WB<6(lVU
zUYhi4CIZB=8Upkp8pen1M>1?ikv_y<bf92WaHA2?u%Edc6<HhghT^@zfh=gM$0{lR
zolZh8tD+<)DIiv<2?iN>O6)u(^H!@g?|}A%tuWhRBB!{7!S$%ht@bY{)rlIGoKy37
zsx2}Z{&nct&^UNh2Y4f+?Q<&^CtWN6r(pb|A#R)cy948AXsM4YF$`HJI^BUnj3MB&
z5~$Ddvl3cGk%DfB6fL_i-=8Yp)9R|JBOnC_%LYy#V~^*8&yFIv;pD#xQtyD%i{-b6
zBq}K(ssOY#@%J>fQICmin(qh%^$>`>`RcGizw(1ET1Wr}ffNK-6w7~X9de~ieZv4%
z2rmPv{zAePtoi)}2hu<vQYK^+uvgk%G_HQ97v-hEAhJ5TP-IEnf${~GrlAr+L+hb@
zjnP4gisaE6q?YKUi_w6THN?vsrLtwp$^<1TXnB(jhqD=RG5kEWk7OlKuV<?lLk(j)
zUiBHik(feER1MK8Z+t3W92pHNd+#b=32Q2;O#__rsZ?9(dN4lGZ$oSK(Zm3YN81MV
znx=(4=5I*|glX1kuq2~&m;tK>0}#SoUzufUX(S2raHCqaBjTm`=^%FoH(>nLUkvt<
z1l17Pr-1eug`lN@Ca`)V$e^cyi!C-)(*Z~lN}D#HNiG!#d4d852OB3vPn0g$s8i{}
zYKo+zB3v==KrFVCF|7JwjI2;lmC1z(qy(uE=Od)CtmdyLbe@SZgkt)-{>^AfN_ZGn
zI<Q7`_(?9cy&r8?tU*>C^lEmM9YLvsbk%Rv@6Y^vU-e8%&={qn7SPG3_An9|;#-}?
zFb-f;M7Ua^bI5_+wN((dkAN2S0Ce!0BQ;H(;ZQhEvHTe2!VH&&135BalX^ciUL?yE
z!`nk#ZD}Z(QQMDNN{-YdtjR=rquB$rvF7H6)q@kx#y7PEGEf9nsC!j`Wj_!Jc^MK1
zf98I+Ckc!p%vq^PuADWR3XlpYYdB-CUQ5f4vRQ{xSzSs)v;cAt-XAa{QQEZU@q}=>
z7hV>u&T9>?Oc+!VY(^}9C?Ir7XoCP=H8=?VA#Ol*i;J{LQ09|F>kS^D+DdIwMMWRj
z6!yv(Gduq(ACBq912&M`m^7n%G!Fc4%h8%N^~$8vV%&2_TpnCXs-Z0FN}T|Pu>FXO
zi|31J`u%uSq}Bj=a%_3)XSo+^HU#%*YJ&s<ri<!A6$K4>4UE<H-^bN(Z8(fgc@YO`
zK!Qk+Ie?hMe(=<^W5ZqhJlsIdTj+j$?|}z)TU9j`wPKW^Y_(X7VCP0z;4f%zMGgqm
zpN0jfK2TN^P*I6A$m*N_0#;<AYSVfotc?vy#0Bv150oMrYK>w%yY2v-AIKSlDzx6G
zfEXIYAt>)>bGb33r{l4dK(A$_3ArN`aaA^~TEh)Ly#s!nl6w4^pNS88v>VNn7enHf
z>dX2Nj7l7l^Qv=_H;JxT{H~=EFK0^Q)k0KX+oTCug|8p`l)<SDT9phkBZ2XIf|0Sd
z2b59Xg7!5!G<K9%$Ef6l2NGJVF`-dNta4J)-vQ)+0q?ws+C&-L%x4TTN{GKg-|W?B
z)dq}4Q1HcI$tT2I0NqI~p*0Y<tRhs~p*kQYA_3?_1!HqLZGc;l1gQXE1M&~O3Wzbq
z0e8#nC28XToWB}Hr+hn^CV5YK)i%zOx=#wcO-Ed~N~r`s2R?#^8m*VZAL8PVo_Tyq
z=h@&l9>;jpm#&F?69cZ~+hX+6^z?1$tK@|cpF%$lg)LaG<DQNjv_@*%skuWr{z`o#
zd%Ck6=&}U0t<rl$%<>&?4@$M+g_$dp(Xi1_u=Ig}73YUaDu?QYRUEE^IC6N6fzGF=
zHA9s|D6zqNuoQG@w6j5PjKkog^vcfnYpG<ot;GPGDrR)rlJZ3aEdph&rj|y;Lrw#{
zqeOv`R6M2h4d`+Zxl)PiJ1`9w#^W=fNF?@_0ApXL^(F?q%A_9Lnwz8u%aWGmF~8uV
zA^NkUcW$W|4euJg93~uTwb&>mMcQ|=3Ol1(l4#JIs)knih3Zgn^lC$gaSWho)TKo<
z<O8aE)NN=lSqi$9FecU-z|$=7DTI5t8>bQJ)fAk+DuVoIHF7xKp(iu;cYcQylsZX(
zrP9N`6<Dr7dew#(AOl12V1i%92P!TpP9sVHPcT4w)jF!07_9qX@YvZ=5mXQi-zY{^
zKwJgdG!u+^R9OIJ8<IwfMLKLthBbgXEKd0uqt}!Je3iAA)H`%c2SCd~hBH~;tLa$F
zBta8=+}0ox3Z(ywhj2@;^Ws<t#5yC|=^0I3=sk`yr@b^NO2LGOQU~oa{ItPT(3=T#
zG+ZGnA74##saQwlF*rPsh$RRKxG7CwAlLSk4x3yfwm01n1So^opLX$Hf8nu@-s6l{
zmy=|VX4aBh)tdyGeLd)<&Dc9?h82w@QfecTn3~ZrV8rL}omB@l*~G978#}8Jj5I18
zmq3bK`_)M;)~kXxIk|8+uwE7-b5Dd(gZGC<X###$9R?Q_)(15_Mv46dg3y$MCK(AE
zwni~LD2hT~U<O%qPX_C|p&8be!N(?^mg6Zc6rX6zsyfixLv9<8uz(2Xn)0Vr2whci
z9$NHEv~hX}UsI!dwp@+=bNZh<0mi{i9KRF{D6<Fmpw^p>P;?U)8kdGk3tp~0>T&2X
ztXgdo2v><MA^QBZiGsC1MA{(kmYkI~A){a=P)ZewGb+?gi>uP&hB-L!>Q6yws;unR
zZK@=-t0<CA`cfe|5_Rv$hG5|E16gqfF*MVfO*J!gW=I!^L%1p6o#Y)b^%%C_6IIeN
zMi9b5BP(4Cx{T7Q(OJ;gnQfKv(5_Q0+G=-_BZgmD@^ZBCDV8g;8qJHm{8hbrTcdyM
zQ3j^&OD;XzrGb_hx+gs~tp<M0RiJ!$%C1kjN84NKG(-yRe#=!;;U<IX^e*)&w=mJQ
z2!<QRau2nr;O~qQ#Yt$D+NKQ>7|#{VXhpE;n1;1dLq8^=m&<w%N{b6zi>nHtajoTU
zpu?$`LDt8VM!ilEKE2qQs(Pe8nz~a@N@WiFM5rtHEoc+W;OZeT+In_sMIpr!VWSeK
z!4{)R6+x!ySO6EK8Adkkn>7Y;^H33{mylEpf24-r;v<YIa@3rBiv^wG2WY~9ca186
z`iDQNmKEvGfoyZQC?4u$?CSA8w@UW#7^E(4OHaI1@-|F9Xr$P(1+#pAfAFd)GhS)N
z18ojo#M{hwt#l8^<0byQEB4ssg*K!4;isb+CFEyeJf@k6q{&-WjAhg4<hbRMDY4vc
zHZd6LS-G-zDJkXlO0=N6!-NBgoD;8URNH9o>H83!#phNdn!G2(U|mor-P!|5Qf)Af
zy{{B3uN^YNQ~K83Heqjo*-$4>+nIGx2$}A|R$Q`$u*vdEIn0{&NZiG9?Pk4cOeJJb
zs7y=Z$x*)vWjfnpg01L2$>*&J3)-r0rVoft9s@7>2@~dQ{{k~j)oo%qDKXVVCI@r*
zQX~uGg*jr3RPSg?cgQ{|6gjcfsP)JBu&ml{M<rXdN$cq#(^Y~)AW5Ho$huuXC2=PW
z|3V&3B!}XBPiTXHXTZGPtuRT0hJwPfe3<kYS2kP5#8uWB171N`aSn5#Yz-cJyy@fk
zNvvmjzI!nO4zko}D%RNQu%*f-1Lyd;y=h1y^{ee~gXn1+#`*rb4Yu<{rmJtt_I7gK
zo;b|WmdAoB>r&|1KT;3AXY;X}e6Lx|!bf6WO+qVC*$n7_k$swB(!0GHu?)MQ>R6?4
zE0bw-3Q4QSERUp%Hnpcd++=-|&6ms<dmgAJn_5jjxQzR;Slg7SH5p|TQ3Ho&_Src3
zd#z?pHq55D@7R*dSSwdMp6{$-OVlMz>GQIUn5J<OJ<ybJ)!ZP@NIm8;c5@%c8%;~1
zdqT=)WPD{fjw7Zb>>;UY1>8XcJ59z!tNNs8BO6AN-ez^e^iG=c!D?;WKp4qt30Xgy
zJUgxykz(G|JGanC^1L;viIpH>;FWL2etjudF9mgKY^J{wsl=WAj8m=+N|U3?glRP1
zcDd;^OT+G>tz<*Gg^e7cuFjCz#jvXv^2FW)KmSaKroJq*H)GrJ*cy*}^L<h=@ftIj
zm~FF}%XY~mjsclh(D-Y$N#kFwZOFUny<7E6NS~dQH?>Lm{%H2rKQEWJE_$MKRb}I(
z)pl>+)+V?|m&6xr`Dy?8t>M1nn!SB<AHAz`!Irt57qs&8H}BXx|LV^VZN2=Pxfv^7
zT{WR<pXuxU{C!tu9=&hQ##dj>&2K-G>w9$n*fD>;e@^GC|Ji)kq5n+gf3Vs+<D2{E
z6nFeA&l#Wb$ITor&-ldtXx5J8{QUOf<osZ@Z_W$V-dTM!j$hUK_<8w>U!LDPasO$(
z3+5i%teie32@k%jJaOOr@*>lD<AS-J8=8A2&R*mFbIz-n&huWoU8FHM+;^3He%V4f
zec6qd_MP$1zn*eNdt~Zan%|pSb1r=0`;X=NCVX=IkB>X;tebyu#_rD)$>$~U#7E~Z
z>S^9}=JhZ9bmz4{etGA+|LbE@&wAy#DL3t0dDb11TPOVI->*G$*QbUqJh5lely^UR
z{G2fhzdhxGXJ=gaM-TsW$|aB9JNDA9p_@-U?&WdU-1x&QcHjBn?Bh#UUUBx<r=7X`
z6F=*yJ@m7ai*LVt;w9$~{N~0_v`!rJrTr()yl>hGyWcd&7QeFcl*ON1c~<6KcmC@K
z{&McvMW6YvQ>MJR=#(4xo_=EGxRGPGJo59C&pkNf%&~uR-ieF8)IRG2ms~z>%FLPL
zrkwEdxGT0U6WLXp(({q<o}P!lbJl{L4@GAjj^>=+P70@Mejgs568B{0oc5{PW}md{
zFAIx)otu5?>^o<yzve4*R?NFSJ7wp`#&z|4yZ@vU?roiQ{avS>TDfb=!Uw7+-?Be<
z%5K8)JwscsJ#)<L%k$%BU;gTI-E$TeudMy1cWm#zk*RZgK6=aL`|lk${`ikiJz?+Z
zQ!lyWv@6bjD|bR^>Z9|EclS@PO?Y|S_;-Kr!ntqmKVjPkUp-;@UuI5Nxc39cUb%PD
ziO27sv@kdEds|Mw>H|~C|9^GNm0y4L<lgV!c<h#E;>;CIIbm$}@IqN!jI-0-yUdf*
zItu?|)3H<krgO|zS}yt6nBlP#``y@UgX81b$yPaY;*NP(`PF(Zrl**dyYuB^o{tKr
zt^3Hb(#_f41y_A!&cu25^>%%I-_(mY<j(0@l{FWxyLUm~^Y@OO)zdsVH~hVmTW|N4
zo1Z%Aie$~=?oPLQ&W6bo&fK~1{;m_}NcVN`i>~N<bm+PX*AxoVKH6E{@X#Hbv-9Gu
zryt)v_N?zL8@J`t-#K$$by$*b7&-0Ajg2kA)xqhXJv_GOZ|t1qzgao8`>zh29vqr<
z>eXNV&bmvM)#5A0)+#fW_LR(f<C8Z3T*ghkf8!}VPrB0<{q1jL<3Trh!7&HUs!aTB
zdBLj7;|bp!JZC)J$UM#4&A(>f?Wdz~&0XE4wV{+w8mg84F%!*tv=Ggy=6e@>V*i}z
z(Ytyke>4}bD$E^Q`1M`A*~!Vc9g99TdtKj2n>#*nXJgI8@!hRQ??3j&Bs*^A-tW!q
zo7-`-nb&BP7Cake>#JwK`}rBQdT!*Lojv!>zB&`m&d7|em8T9z%>_xJcHE4)$CPV@
ztH+EisL!<B@ywr(o4I|`r1Ns;WlmZB@ukK7+M43ir*{^Q-7+oc*fPF+`aM1862CLE
z%*-8gr`i1B)5mVvHzR!DWA#NJ{@AVMzH|B~PoN=N^{+<cGRHi9%lNtFQoP+n%Qm!<
zNwy_pY<r|?_sG@-L9VjpEBT(o?d_-KT6??Q9fQUWyX3}b^`c3aWy@PDcSaxB_g4#&
ziSzp8?s)bYgCFiWWsg)Qx907rh1De!#=Gpi1u~%;Z#wOgu8}#XO?UCJSGc*C5AU3M
zQ~t)@Te`khxH&!)-BemIe~0Zkb7ywXd(MBL(tX~l>Wpl2MlgLr7+p5+p3-}puVku+
z%-9nfa>f{ICY4$TFRjG)ULLkX4x5b}*J^#Q*O=pv&6M4VVg`eq<gcRnJMky<v*WX~
z_T_^;pZ{pj2M@d8gPW2u$v=m|7W%5vq~T<HalF`hoF^R)XSW{+JBQztqIE%Zx;ZX7
z@044mc3TjI*RbB552MaoBXeq}$imjhk`-atn3k8`=sf8SyCj+shGS>FS7yu@YowO6
z#@6!R%}!cT>Frrj%oa<vjxpwMj%DlCxP@EIIp?mjotZ<c<g$;Ck@5}Fv7_mZ+0<Ot
z86TLzD!eR;BwV}cXZ`P!;6vjwwS5!k6@s9?{ot6O*f}N$bRFI;`|gEp%I>>5am;S5
z?_YUOxW9Gy;KP;VnZ0t&t)EF=;S5+fINWOQ`)Fr;lcURbbN7!Ku6<z4e!Jj9!)&!(
zDa$j1=6j3xu|U!hO%Cd2dQdW(AN;ILKhRa|zoSd~=m2Lw{gfOVjBxNaG*bpRZPSK+
zV8qORIh0eL2&MeFl38$D&(+I*I5~*F^F)+9QQsT|%VbIIJ8@L&GMt`SV;@-|_OEWr
zb${m&`#o10JFwN*;ActeHjY?D%Vc{kuGVUcvl~0(pufGGL&*K*TI-3R|AwCjTdwV_
zZX8U4VahaFWJNByL1gf_1$#!m91rdR%e;9w!@x|!VC2sRrBxr6eN5`xCX{>52&HmN
zDCR(ibTfB}Ka`hNhI7cwSvy!HC^KrfZ)L~G9%AbQhAsF{&eWwNN4{!dz@E?`3XF*k
zbQw9&RgT(h)#Pk;@73oR_i|S@>bKeMJ-6DpxE$(E+c7kzwqano-H@SwxU<uQ`x$;b
zxLWLiZOP(bjI_$N+>Q5c6q{S&Y|zi9m(Ij2>s%dXYtdp^9@%<llB^oQ1OPqr^HtW+
z$TBl8sT{C9>{PW9T5&e&yv#lo*U8$wr8-jE2QX)rG#JqDbrmK%CLG>d4Jf}x-AVUi
z#?j5rN_mi(#NuJfg*O5~AB0UgtvJMdk#Y4$4>Kxln$FCAW9IBP_4Yo)?1dN6fWOxo
zo-3I$1ZX<R@H5h%i^L|yAW3rhd5Pp&RoT--U-vPUH4KidFj98&0%?dGPI>|<MEY!$
zQ8G)&NpQc7+Nf7@ZCzS0v7Y&P>>q_Q5KO4JNeMJXo&Jj44AT-@bqvacl*z6oJ9s@X
zB}q4zL1P4sh|Z{4t046DQ5tTH1qBL`jd%<{!V{&@#Po+Sp+0XltiKriqQs-X8iS9N
zIKA;^X1tc4#>Zv!8e6(U%t_q}8dmo%r%1-Mg!@nm5BV(qL6TJz-K=^8|K=S75|$R4
zx`y!!3By~HkCOgK07k*jP&E(w3s@vEai3U*rCv{gR6Lc2D-YEZ<5r%-2LlNvW}NtZ
zXgEJZeAPoBo3I|js1`mvU7T=L!gT#8KzKyacR}mfsH3ttqmx-xQ<~2-k40%-^^l(V
zdHXs-5bIlOZ@TN|_r89^&0l=+{4alX)z80m-MjHWw0gsrUfcbxuU_!A@^jzd%+Eus
zHhgKv<)3)y&0j3K=o>HIeB_bUFZ@dVJAbk0xvxEU<?hEX_|cK;XYGAt=lwfgdTi}^
zr#$wfBad8v`6qt7^QULN`Ph#0zVy(FAAM=(H@?N0pELjESL-i$^P$Us^zbzge(Q~G
zkL<qb{_8LJ+>sS~e|`RgM~=*VX!noqUv<IPpS|jZM|MB>>l<d?b!4~tZ{GI&!@r&L
z_6@Tp?7sZ*RX=+B`kBvvb=#G@u6=y!?pcpt@X{}L&HU8e+j`Hu_Q8uTdRyekU+$ju
zsh@1?J^9+t?HFeET+plndIn|>s{s2WBR>u|$^*=LTxP1@C*QM=u!)6S@>I8c_|<MY
zsYtYX_7pmTp=yE2W)$4>35-3AWY6HZpy#Qq+|$hFr|b)Yc!X)@r?bIF!)(51q}xcT
zAPe(B(6bO5d1b7~Ka4e{SIRQ^XHn_G{KTM{FJw053bJarkXf@(!v2qha=z=9^OGpE
zt}~Pi7lhJZ9UIn5b7b6y0=c-7jgw8ZpvAetI2Xu!424`O$vL;i^5hr_ILJye2IJb}
zv-!?N^E(P^tp9f~8idJVQNItYP5!<&b=&`rO6{8X{|8VkbKE}&aev_dLvKj5qlRop
z1Cb?^Z0ErLPHSpODPh9Ol8(`{2d2~HqhT>xC0tme;%Y9M$zZLQh))ZnD@GAD_#0<k
za{)E5OO$?~+gQoDc4ApV-)v-%IegVnCylWk+Q@#M_>$!p$i$+wB{DM^fW%S`lewXF
zQqCA%w2&y2a2i!Fg4(2uh)kuQJe*Y}<XNmP4sevBEygA$86z3pRjX@=@dA2Ek%Ojd
zxTjz(sdqQ4)|50_mAY(9$W6h8rfiaG2{UGCr%<$7x`!ld^Q>9ai$Y|>Q3=s@kmv0^
zn<X@2su~s9ct-8$6a30%7(5*mbsQ6lRSPj8KPA(41E-Nkohb$qPs$%4?Tswc+zGx;
zV@~rXfmy)Z-mr}Z#tMD%ox?GHLzUw-K-&#{NVKSl6rr-uXu6#A$!S5658?fuDv4|g
zwd~eBs_s5<^DI4L5L#nlOF2q0uTOTZQ$MVvNDJv#@ijsUgDBh@_?D2XWejUM@a}Pn
zlXBCrIOcG9Agu>Rohp%|tEgx~Bjl0sh4S~!d>|~=L(#^|%WpIb7AHAGUq;(^PzH=z
zI7^hI3Y)HEueEA1^s_CaWv4I#eODQWf0tCrXguYkHl^j~us46stc7$60sp!@g~^mu
zxD;4+CY&&%QJXML*~2Rme83cO_zYCV5!wdd{wp2~Vh*U2T}=RwuT!>$TL7Yqx-z1i
zJ<mi|&gMZA5H0|LdNl!qvnaZF+|Z<ytCrnQhj9jwcnoAz9%UZZAPX_@h&7*zQp+Cd
zozb%L(gs6Rgh>v3&^^s^Bb`BRDu%De=tUeX>bmLJG$m_7>K#2~(IN_EJIkl4IpFP{
z`XVZ4K@-+poJlg-tWz(wK7xx@QOB4kDS}i1Ma$RBP<wR}*?z5T7BmA{t4vf7OKSVI
zf5u-`UZjO8VMhDHEyNEvgkhji=DQQRU`2T{U?r4_F0vTqnDiO-uoH4%l9n>C0vPJ$
zaEKY@)W?)b4u+jUBzKPQXya|=$z2(TF0vc{<iR0B(M3h3!JrA^VywSMR_nUq3?g2Y
z1E>xx#u8|JhDj38bZPt2Gd=(AJ4osird6=ckP++SIjoY6`^u$0DEYRnX%y+8U}&Lp
zLshuMfwY`TKtITp{r=dt2bbP{?^+6ml0gPpC>gdk+(4M2j@3~HJz9oD!*D=xq@c|O
z4*0Xk*Bo>tkWh%=U0UhF4DKQ6s(PCof?kzja$XM>E*Y3gAx6(5jVk`YNp?t60t^a^
zq}0MDWkeAczSNdL-P#(ql0fTZKt$2X&87Q$$S?^*nFh|n$Fb6>kMoT8Yl|pW^8}gl
z)0A@kJ}K{ygCe8C$d6{j1IC}3%o-@6^*^<&0mk%3y_nc1<1liSkWfbYT&_SNFs&Kf
zs7&p%9q=k9^?FmJWx|32gB>y!rN;R)Tep84e(0S1gy4FLa767yv)jRHeKC<b*v<i-
zY!PhnIxjW`k6SYXn$jWxbyG%;3Nt9i$bfn=39^<1MJ+a^WjPscYR#*Xz_fz0!y~4{
zTAq2tHRS>+T7y(CLYBdC2Ah$zQ<;LC=!BAjv&MKM(VBytXn#noOX*=@d=;!}h?ats
zMEe*8<hH)WhS(6rkp!=iBE;|u<sd&y0R)sjrzEIxIVlrB#BnYF7xbgTLRnFyKL`@^
z*TItpo%;}U7PA7;GM+D3<vUl$7#vhkZ{%kQ)D`t5_s|vvbbU(29iyv=BY<;JfaS;O
zT;pXE+Eo0VPJPDE9$9JVnXMn62O3nyh$}l4K5CVmwCJb@_9!vR>=0|)2jh7pq5Mq;
z5r&3?zzQM{L1IkcN$YzE@hzp+!N~4~7#cKsJKwaC@pbA8b+U2@<yD%tGEbZ0Rbe0b
z4F^4CzP|O|2F-KAAsQ)iHjEPwRdSb6{&0%hYbY-la4M0KHLfa|ZjK`wCd%l{(5t~;
zYxXgBO39F&#5rpX`NI;lWE_vAOhQl;HzCJ12&<zy&0MC-l0gapO756WB(0|Q>eT0?
z5X^)MF2+K0XMrhmmUwXpw#d0Lw1lfttWa9|)EPkNEv#5jr}y%#h5Ac+yd>iQ6)4BE
z?3KlsQ(?>`sCkZ!qUA!^Ppk~*Q39Slv2Y>IEm#$>kio8Ksi6syj!`_u*nl#y6lgBs
z;f7Hkf5;Q%cnmYrilX^W<WC<&*F0GwB9l!R8ne_|DMOf48X<j$lUVxVFs#!0Db~6{
z3P1*0WWL-wC_`OFH=ec@RXUQuz@R5_%W3a(&KjxvGp)fy+7rLM1qQR_!>brkS{*6C
zdkB;yxADpj{^F8r6b+N|I(+^Ddv8I9p5tU7RzZxln<R3>(j-!x9SKj!+~)NgG%2Ec
z>tWtlXC*Q+g484`($K8akfJ_`BFp{|%t?!HfMk<qCOoAWr4NuKx-_A`q1iA&d|SMP
z0q;^NHYr*)LnozN;-fZ8%aS!jE@l`XBd5{FX9$-u!8+|0>VceBu?=iZ`~S<5X+qHk
zhQEN6hobIDphIc&4@DTG6Ohp{;k?0o;MTxT$6(ost-++eTunQXW0>u6$V<ZeT4dVH
zXU-nfnUrf`X=DX6uI2A~X^ArgB%R2TL{3pU>ayI+>QSBq0W?44U4xaCRg`b*_DY~`
zf=W?(S9+^XphPT<k#*`*s=Nl0reXmEqxyNU!`!I+X-JwX1^EtGbz2P`F@#1{%dEp1
z*lCq>VhF+X^%`0(5*Ve@APq|zI&f1MmLeL`v?2nmPt;FCM#GQt3KC<Kp4MN180=-m
zR7OzM5LpSp8F&X=B11w7T8+gOh@y@X#~4VITso6!B6i@TC@(;Fonj1D-G(1!%@9c&
zM&brF5c*GiWu=0q=SBvONy(+I(SbT6EX#1!s2zdPg7Jk&`$8~4dTh7w&dBM_=s?p$
zggW7Gy$2&x9uZb(G<DEUn9{g34}PmVyUSM*;sKT=9A)(o$q3|RHigZ~!D-BvvYMvb
zC$i+xwS<jXj0<R|JYNE7Jrn{G9F0$}3rqCYX$VN1&jeH|Hu-%ZPD{n&1?;GjXa{tf
z?Q!I?5*?&lF?r1vBtSa&#t(0wI30N)0akAnk(zrZ&1hhbPHQ?y)|xbqHgnRY91~w7
zG@9S!EFIVaSW@R1HmPe?xO4LYX}#NbHGV`PBT`F6GKv8drTKNpmg<0}$eP4pGE9_|
zn@w{;d+)dWvihshASP~^xT>ZQ5olr*G?IoA&mRmu>d_*GT#`Ey3Rl5uUZ5<Zo<wY#
zJXmJN8m#<bt2fVY096d*_6SC$idQ(QcamOe@l)9q8pO5SQ#$I5!J|DO^eS!|>X}%g
zDgq0USM+X2{fcss)PxH*;7Hb5sNtc;#5vngtbtx(jb7Y{P>^9#v*Jxjn@GS5>By!Q
zx!+l6B?1rMqxr@hq~MeohqUR|zc|7HIi{H@M(?Dr+w)v1pYf5cRbN93pOz}+7F5zC
zv3syiFA6jT2xYxnJ*i_<VWLyZ8mREr#Pc7IyAW7p#`G1S*L)zJ_7C3fOwhuqIr03o
zZW-vTt{g}<MeCKFI#q)71glc$&oyL(n2{J;8UO?TlJYg)8E^~sV<3<k(?>K?#Dp+5
zfOngyI7M}nu+xDud2>XDhXQ_p_~aO@h~p<MUpRE1rfBeT_IH#}0`&tF9t_Z;@v#(D
z<wxRr)39Y?YBE8@dT*d%+Cm!)S*%4wTES>C<31p;dL>W9_rQQ*6yW4Wom$SjCV3Co
z0n39t4;^|nV%y%QGfXkY=}i+KAQ@8TKP3Q#n`9I8z{{kq^9UtXGWER!p2u(%Yc$P%
zut{jSs*p6sqxN7J3;5bkYKaEJBv+;8hg4Q$U_sT2z>{PO6eX1;w#W@Gf?k1}9liTx
z$-`)q?!(#)emsTEfLF>;BQngi_*LVUYp4!}9!WLmKAIJZN+~rgFx({^Nv(f04u#3g
zQAJlNwbEMMb&S58`iq?UF`*G2N+GoW*YS>6#>+Z4Fc!wJ&Q*PwDO#U!;F)PcMuTC;
z9odZWXL>%rPLaGp!s7`t7Qf?1yhyFrQd#{KT-s?c)&|LI{xU5|+b_dCdRlI6atG$>
z#c8dyILyZ3P;@(+BK0C|*5?q!X|HYrFK#i_u}&LQJOX61ANnDx^0AEm)j0}Q#ZyuR
z?8$hCpS2NS$%XaQ)>)t1l`x5dlqw*^N-we1cATisgWhx~K>@dLX$m}e<*J~*eyMr4
zUQ86~)v?oWhKA)*4dSx=d?~{$t*^rn1X2fysf~ixLJ9ro6im1H5QD9PA2O_{>Kd3)
z;<SI&)Q|#Wn_+NdI@0vxVQqt2u<Dkz|3Uy<fwaMsK%a%FH`cQS5F${T74-spS{gy+
zSFj|;kD`Op;MD-V2F5TFA->fd!`=29Z>fYU3@fEmmuj6uHxR1pDDyDvkHodv1c#Xo
z(BRn7KyG@_p0p09BORwnYWPxZ%vpamcq3C&EL~b&hssvnp=b~T8Ri&DfraBoigwGV
zjRp)m;lYJgWAM~D(jkLUzwZl<nqJCJ#nr+WeYOD5GI+>pAAv;atptTPWTgbfC=)ig
zomDC+`YV@~*55#r)4B>oR<ERjDH};z2A`9VtK}#4^t1~H)Ya!N+!s(YVS?qC*lFp<
z!o<?D{5We@#=(Iy)O3`Q*0MTx52z_;t#|sX!x<XG)!Ebvtuh8N&~~Dmaq)Zbv7C3p
zIOp@*@w@R0@fliK$wHyBd1)iuCCoq!SesDFYRRcsk)L~{YwOiEnq+(*T8!IRPf=IG
zjk?tCELuwxox~ma(Xj#5E}|QDB<h6jJx*$7w8QbLMFutjP+0)le=nO@as)pKT3SlJ
z7x%L9bm*OuWkp_br0e5yQ&!SjRKMX5m}oUTEkR4pguSh5H`Yh7VF?<RLKGr>j6<|Y
z?ZXdFiP`PaVXsvR2dyRn8E-&MF<O?lKjqbEsw5UFTGKQ}lc-nC9<SyU&kz+ZPFZ32
zI<SgVF|;q%OGyZk4YA>%BV3$#%36ljmxxV=y)F#Gwscs?5*sXWv`$V*6{^ZUg`;;K
z2N>KAI%FGF$DpUl>s8T4ngO!<P-8g<fKX158w)nHL=u=_gyUvPFJaS<wjECE$7@_Q
zs`b{4CrtyKW$Fui4@R%7lDva}y)K;&kbpuvGO5~d8`@)L(whD#H&jK@S+<)JiHx(L
z>bsN*ER9B2-U@_~e5X_yFdPMsQ*tGV`V|dLQ7<j;roMgg5Z?uv4dc+pbtHh4VEm-(
z@4mzop*})O>I$^+wBi(pZe1YPq)s!6vg(y^^s0RmIU+V-OqvDn@zZl$bwjO%#FBgy
z8c+(zeiWPpMwz62Tr1QfYJ||H+#C*yqN-6fR#k@=kdvnMY5HfUjJ}yr8D}kcFCCXq
zM}3ji<P&I>#=^tv*=RVfNSOwBx-~fT)x3<0MqIB{VQ;D0P1o@z+FDUyJhM=BhOGv%
z8wM9VNSfB9>f0#D08R{-ywsQp`BU>yBM`@%dVFapE#f(!nt#}-!(qVcjSiD=*zjZ1
zwx;LLV7uXAFmA|&d;FQ7C-mJ0j?7qb{3*ntQ5_8uNkKUb-Rm$;;DBC?Ui^~~b!euX
z-u8(>IH_r_ucr1{L@9b1Wdwng1c4J<4WoS;$Rw0&Fai>E(|1(rq;WK!I>TlNk&(dF
zh-oQX6-Co3u!kKN^9iWiQnl(Miry4RyZsdR$g`th8a&|zhV|mhJ94;;+Di)|45|iH
zdvNh-(<)iT`2mQ(c-{KQT3>h;t>M!GdTeYV>%>?P*|fVLL}tJ+hP9SYSrJxKKm<^9
z1yWHBC`3V{iCEZ)Aq#tqHNHqwIV>x^6i#T+n~&gNWRw@$AfJ2Sr}cH(OJH0&OU@u)
zr_qEoOU)!4)F{T4z*wyhbS3arNJO^l&Eb&HacQL`F4GlbAt3Y4S1=6?8klt*2clyp
z8BY_!z(5{&yhS%S5YGjckes%xwV0FVk@y!?m_ZG8gr#M{I5i8qqsuRvE}O;Rw#N(*
z*ZUJGs=&!+4OI4)-;niT=IC0VFKxwH{)W{m1C_Hwnxhd?jVIEGjnsTy&ML8Kbfpaa
zRn_h38(bCQqUE}s!GJ>st@V~`zg2Zvtvlc+Q`u@z0W)A=C;>@p40qG&=jvtEOu(1J
z7v#5C134u9rhx~i3zDd2p|G@MaD|7H0|X7G?=IDIBA@=b$VYE2GlV$2hZ8!D2J{_{
zDCOZ+<gBwcSq_J0$qo#yaRp?e-0zdYgM3?|dqh@l9?YT;+K#*&v~dox`7{%`v$C4A
z9`H$ADHF@7PX?88XPqxL2P-?eqE(1jlz@jTZJXose#9PHA=#?Qqd>zV!#XoOLtK9$
z+}Jh~2BngZvRitC4S`*jqnZ-CP+E2patT>9!?)HNW^jL)v6x#q5#(Od^O<^7i{r)R
zJ~MBKS{WUtH1p@!%nr`$N4$V|xQFQ&^MF^!hrTY0Ovki?OOmi)5JFs|Oi|fdIqVw=
zg6%v&DHqR8EJgJ$@$;jt!Q7_IBz#g?HX?}08qPRv?9<A*Id3G`GG_6OHt0*{;$BAl
zj?55c8YYz}zO*2-XEZ{#%~9SZJJe^5nJTrKT^>wN=Jnl1`gXRdiM8bx&tP~bLu*1X
zA+VE;<ojtEWL#7BS2Bm}8j2A0Gxo*tkN=DqcZQ}ubWD{I5{+H+&^2F?1qb)c*H;@R
zR;Wv1^=GXpJKWu7#9^Dp=BBj|j)a3zm|JOvlff{gQ@gv476ZhyN%OX3e?8{{BiYLk
zDp_}5_?5xVksKj;#tHRE7B7k9D@$#zQL{a|N^O?1wRvg(;Z>Gh=vd~a`5n^Vu+6#i
zc!X**Q8ADu*;0~E*tbIhhh|RWNDmEI5H_=kjL5RhQGacE%&tXisqoo&bM+caJxR(-
zHYZi~DzE7_7cz(l=2^?msQXu7=)Bv$Cn&a~_gpsr)m(roqW<kt--w|UT#lB9O@(Ws
zLa82ESro5h476lRl5E>_dl*cSNexqpE6dlKOjdffOF0<h_SfPWo$*OlCgcj?%yD5@
zTh@x>b+u$B+n3g!w=W15OZS$|#rl}uLe%Q&jFvS@ZMkG6Gpi^Xf4Z1U`}@cCl#4^*
z1S^yBBU!2QR_xfiWK9y9{DRpP$|5l1lW0eKDA)5S%Nce+tocknTEkdK&wTvtV#>0v
z4MU~zsr}I(y%zr{fB5M`tJ|;kUi$p-&~?A5tsFn{o%P3k_up>6blu(idv9E}c+~?N
zSFb+!%y93j{QgTHy{@*tvUS<&SN5LT+g|nWeZQHob@h!)R;;eC`f}gqL(RUEuiJXb
z&b7-HZ~yy`Y_6?N=ATknR{Q#zWox&u9)B8aj{DQsre3-5wXx@JSe-v}>*Djr&-!Zb
z)=zwO>@B}pasF{vFS}sk-@Mj$<u})r-~Z~$^YaTnuws>czHia9>&mzM*LfGruiU)s
zLi@~V<+acEmCv|wMe~7f{DTko-SEu(@)_qW+pzHSTl=@SGuyv?aDL_SE4KLW+HCm?
zk=vf$Tm4ewie)<&y>!jaNB?fq&Wm4LYk%_E;<vAU_M~h6?b-Fez3BPt9{usE8!kTY
zpLXwj@z<xEf8DpIo$&g%ul?5IHHC%ipKW~epKm&5(Y70p`_|eEZs=P3(y1qpfArT2
zGgrQG=4lt^-t*dp#jY2Bw0_~YUzm8}Gv}2~c;>>=@vGlA{wGV{bL#Q`(0$9KSKc?_
zxHpy`f7TlpuQ>IgMejZ7E4z;S^uMe>{iZhy=l$th-<<Z1FTC{bujO~oI(OCX<)`1Y
z>!LH>ebq&8-LU(N8{T#1&0~Li)`^{8-+goE*Drq0@w-mm_Q~asEqrYGTQ`2P>y{J$
zN7v0$Puz6LsuO2kZqNGXi!cAe?2ET)`F`iCB4_;F&Bs5s=ie88?a}Z4(W8YIu3xyb
zosk9mgD<ZgI&S~kCp#Yf`;Hx7|NG~!JM)KM`J>4{eC4D^SKhYip4_*mEm}X^ShUhL
z7QVgfm{0xW++(J!fBusGv%h<7cjgz@_l&=1>6GU#EuQ(0Tc#~s^RcB1pZ(*d7py#Y
z+6A?h^5eqdOHNpG!PQe2uRr0>_8oW8@jsZn;`nRFjX62HtMmAWqGh|kQP}$UiuE`B
z>6~L{{>6*s(k<hsY<eKmH*-wqoQqC4J-c@P@r5b(ub6t`u^&9=<}qL2eAbwr*{eGr
z=sEifAN<~VkA3j<<JSN9eQVDC+imMkG+V!OqSO}O^2>GcmEV2O3_bT!Wu<j$yy^o}
zKe*+_T|KR<|FwD9CBIzr@-@t27f<}!!RgnW*MIi*KR<WXu6tg;e!<-DZJNCH`>maK
zJ+<-f(?7Cl)0h6E_u=<#tbh5$+Sv=|-kI5yy*GdHtp}>-k8f<BKI^jFGfUo=oEi03
zCr8hXk0#8JtDjn4KkhUA_1r%#IW@m#om}xBV=f*So^#RI@#n5wHSzqF8~!1hwdv>Q
zZd>x$($=(T9b?Y8_=Jmo@$#bg{_DS8zje|LyB5xQ|MlIceEQNY<Gyn8<}*)t*P3r`
z8`qKf$93mU>pSzrW8Z)Bgx%w&Ru=VN8a&oL=kiZ}_J$99A;Z@&uIPyO&c1&9?yenk
zzqn@L`p*vsbSrms_`DbP*m>2zpRlM<yJk^g=&}X5kDS!A^43!RlTU3*rVh5MKU$Lg
z>hZxbJ$D`WqsbEnI;Pxuo4M!K;d1oJTQ|$c|JqKOFjSwMy(65T9pWqV|I;=nEZMYf
z$%gPy;hJ220y`QeMk~59_PFaly0mlMv+v!yWNO&E>A{W}JHCJ6;_=gL{qrmH=Y8Sj
ztXw#fT|Bi=U)Ftk$Lu+sV|Pp)*ZtlT##P^AlP%-yNcQI0{ZlU-cVo7B%ar9aZ|+%_
zd@Jtmdi>GWlKf{c>l*(jD>hvGC(H5|cWucW95`~L(4qaS5xMcx3{;jr+do*^|Ksk%
zukG);_qqL7tj<?w&HHuV>_bm|ZKi$l^yGWb?+;h*eR$^f!>^w5Z{I$=@woPmOV<xy
zwsrk8Bkx}Q*ZY<{xu$wd;jiWn?pU#Qu&{j9n*5FB=$acZ8(R8G?xWA2KYqLU^Kf(a
zp6I8~y<%Q_?O<<h`HP#(`<_YU2M2pM{`(7;e(1Z|)}QWLx^emq@40T%x;4H3xO7T5
zaLsYinDy(cUDupgEru72&Dxn!<B4sxB~M&6<6WChpTS~mYj5$C<Y4WlOxK}z2XhWz
z(~J(>ylh<%kBROLn5{~W<}YsGIy^$L4LyBf<ObuS+c##@PlsmL-N-C)vt~2~ZyIm^
zy01|?*!tTh;jR1k&0aDzeB%=5b}ezQEU-^*?1=828$CHv&Cn11b-8;&qa$077Pq8h
z@zaIBo_Jefv31ee2M&ZwC)`?kKKYnw*%$JyLw_9F=B*oT@|lgFJ?FT_-|cBE{iCIg
z>?NyLPk6GvG#sd}Esd#9y=Kh%+z$H5s8P4wXSb!a^x1-4BNY15W49fAGB8iHgJjvJ
z>D#-XIk}W=OV?VLTb^`0N$d0MbUpKP_UHHw4g8BlPyWx2Xy8wx#-}HmvYTh7e`K)S
zF;rOcWc0=R?mQr~3Wp9~Rk-b+7==F7I6j(iuA5lil3UywN)EISB&V%69a(-)N@INE
z-=1)<m=4=m+`%|#Y3`p|hs`0gIOkfckGanT_MbM^<m|B3Tw=Dj{<hT`dbV}=*l3ev
zrkq-xR&UkJa<RvSi6Q63EN7g?oo(b@)7aRsHIm|G6+6Ep2r_wAOG}Zxcew=PH^uqI
z8`ntY>YmJsQd|pXE?a&kvxQIFVkQ$5S5MOg7uPW)10f|@(lbA9#2t>J4_*<KKfF2O
z<1%sJZjXYyI-<ZG8#M-cBRRA=iU+2<U|@QuarZ?Gs-tMAL!!Yad!>D8cVUQS=!hW*
zGcgO}C?f31C=7>WT;!@@bD)@)wk^3KeZa+#>In&RLnJ?Bs&0VcAXA>C=1ew2KK_`F
zo_|IJT*zZ4I_ZxYuMXnxsIj2UGqFI&l!nhu)uco&f`Lq&8MxKLv_GhikLtN_nT&*X
z6SKOop7dBT(}c;8p85H+D;c#BnOYj^RcwnrZw9g9sfYiqIAPT0(7M4DTG6;AhIZ2|
z#lZT)#xh$r4IgCT`JrL%qtoA<Yl<_Dsgj?xF)oXQsa-@olPn99jODv9_Mj2yby^9_
zCR;B39-}NdSjF00CmAbJ!!+>%%bOhui;OO*5~&hFLnP)%$pewx##_yYWU9DaN!<K^
z?3~DWa2cZ`#44z~L;OU~{5<##b&;e8Kd0`%Nw}Z8;jl8|=d6M<`7s;f*Aa3dQQ-}^
zh{2On50T~Oki+}ZOYNw~;@1IM$aOTjL7>Gbi6EvMj?D|uXc#nxTl(Be9f09iWJT0+
z*B@Y5mpKY5je=ind%`=NUTYLUO*aPVM2YfYNi9(tzpOqQsiuU+C^CXKV@g2f1OmPI
z92xH-it!;DmtWu$tU@=UArT2i{!VbLx>ROy8sz{^2s?Z}aVE&|yYN&k#O>y%V3l=M
z<9Cw~dJIx=baGCpk7|t<2*2uCm(AqM4}bq_(){h~dgkXR-^Ks<j~;yZ2mgH6?)Sg`
z>kE#&xcuR_UiiYpH@x|SUGIN=^;JinegEArz3|rjAH1pG`B}Z|?KL+&^5V{i=3o1@
z7k3?bWA$&}e(k0=Ui|IrH>~~7=XURY>w+V{{Pnxvc<z@E-SETzT=TwNFTQl-$lLFJ
z<CblYy#B+-*6!Z@;sr;J>^yR0_qMlQ|HUuXU-ag4D~`Oe>a91{ZoBKPH-B-%TVHx<
z#T(x||M53&nYI4P-M?DB>~sIM`v;HQ^w{hF_U3xd{H#Ck@f}xv|FPfBxo-W>FM8`H
z&ip)n^S19lw(ZI@{^MVseQVb17yRf~yJr5`N4NFr8JC-H(lbB1PWdyw^Yh9d4<+Gy
zd8ktk`bAu2`kvdR<J=CJc%R6;yB(i-8_q=MMqx)eF3#WXf_V>Qa^c5$%5f+%Pd#fV
zT)Rq=Yjb<D$I#wPuP>RqzF8}*ZhqEe`U}CaJ%!x+Hq>&z>KQ0Z`{CWEjd}6x@!87e
z;5l<nHMn%JOp9qIR2#L!rDKXC4`$X*_}8!zd_baXYiYK2+r&ccBT;v7b$5{4xHMNw
zmQJWm?U``z^`<fH<*=}_x-LAhpf7WPz4kK}*Am*PLQTrOwNh8qxz84sZKAkK^Zgm7
zN67QCziG%{-CClA{~w^1p{Aks`wn0t|1U73f$k58tojYV(fI289hl!aF}&dSlKcID
z|L#r+^=kinpkn;FknHcm4$>o#LevrK4uK}oXzxN9Kd9FJ@zxTfq)>##MD818k~?UF
zc)BWJECDufBXOw|MMV(0<h4oK++~2KH!zZG;I^ea^LSU0YAD*CVg_7jk_Za}YFHFD
zo%%ux=9)yxp{+=6S;S|CMTRZweoUHeZWv}YJ#Leshl68K2xsRl0@DSAQskZlhTei+
zj%pta7phK`8|G=ZwQ-~3TlQwYDq&mqK8j&^fHsvSz@S#0MQZ`CC`bk*tQC@gMewW*
zXx8$a|BPkQeq)SmH!O|$+>sb_=rU`xVI{g#vm)gV*QQUY^>hq`<l0T|q9tOhZ9@ih
zCx2T^5vqW`$x04U0&9>$_w6|F6%Hlb#~WN~S=}=(QInUIAmaqd8f3pCvLifxV^QeG
zOCioA&0s`g2P;dh^gt)5WlOBciM50ClB_t&ws>^yQFu#aoQq5SNK4L8jRL9>Ba~Z+
zC{E_#)q8n=vXKCuXP$4M$r-UmLPzKbKh+&%Y6S#_mI&aqd)315{j44YH8|M`(JhQW
zOu1X?iVBGu1vYe0G(&4`NV)m-O6fog00>nVhM_)y9E2pnid|0H3F;FvXd)P?i(6=B
zlJyLcB-H*vp_UwjY^EA`UqxPJJb>9*7F=K)Xf!EQauO&bmSjgnoOY*~3i5_zOo&-w
zJfKQd`vIbK(~=b`<N>yk>od>5h-0+j*r3^p3RN4i%$XHdk46EzX+ptfJ}*h24>FvF
zp*S(Z{$J8EPRs88*EK5yb+TM4Merd7V3Db6+L7i?1q+Dv2heF#-K)Z)A(h<7FvNU~
z(P{B%7nuZF%8@2-tQ1L{k!#J5FnDI8`t1ve7j!yhBF<6|;b(KYxwEKDB9;po?+K)A
zd(>eO09T0k=~J3Qkb%Eu-3J;zw^3{uX&DMV1nb0z{*w!%RGbfC)hv;!=ipi4_64k=
z0gc2k@7`3W4X{F7#w(89$1n&CJ}Vi^1{W=*0m5w?egLN!X@z`VE2FQ{3I{A=F^+Uf
zV4=_X?SrV)N>EZH4lP?p0}(AEHsJIUw}QZE+Ue-QO50_#Qq<$ZQ0bY0yZ#h1EH{*q
zH6xOjrG%)cfYG$tgQ-UmcxeVmM)#iRaIme|QD9?x7@Lw(bF#tcE9yg>m{_1%9RhDC
zH6HwEA*FhyfI<sXSg@0_3cWaqa~W;SoazP4h_tlq`w^J9a!7X*NY=o5yT)^tqNYX3
zIQYV8AGiT1yt@5&6R{2X5Mt5hIn|6m`c@VPc}3|oRVj-JTQqTayO6<`Y%#i10;3!L
zdi?tUl~RcfCc_uuusSE5APl$y$bh1z=oMj=PHj~okd<@v(Q}nB9V4e(LE{i94d35^
z!q8^4lgQA``S^&ze>$orTS!{<yauUKva#B4B;P(7PGAs6Y-*3nW>6X;EfS<4oiw$4
zuV1SI1k#2s7HhS1aK(#JheE`Y#fpGd8v!+fiQ^_K$&g50CGus?i=UK+Qyd*A*m8Ij
z&p-<?Y3^AF$m><aI4vIC7+9bk7nX8U-V$M+9&BLuFmfe&Q0-TYmxBv7Jg7{)xuD@Y
zB$>#XF6sK1Q_!b=VaIAdXb$8Y4HEKs6p$rNW3;(Lu$+<${jRnh9`t6sa#b=;Rkox9
z9sxzxsoFpSMJrhBOcf6BSs1<P>kPucaMxVxyZ~lg91IiCgQd}e!*Ij0@2yfqENvPk
zP1d<eVB3_0S2ME^&R}Q`O|wYoC?JV;2x@7F?jiJyW~gXAe2NcT5^MRc-<yW-i<~uZ
zeJauo1hG9p6DEUXo2T1U{(?=(<UVbPiOfml4`U92d@#)*2^ypbr_{J7yc_Kf9ZU2V
z&<$!q8j>t&_n`HchaO!W1^8HOqoX{a3>^{zgH5pm-2=k#BPc!qfek8z=pbA|rv|}O
zHW!#-j?ybVv-rkhpGcSu#s%R%OE)r+j>Mmif?zNyWqi2IjeQz?$t{u1PQ}57t%18X
z3?p=7UIcP69QCMmgmdFi4hc%2xEQ=J#DF33uphqYm=T`4g>+chu$k6vC~ThihH=$E
zJ~M5;v?kFf7pSHcjoTe+VW|c?wGD-#qe&|URma5rS*b8~!B~<qLB<ab>|nIvn86OL
z13?)u1Ys+-TTlgcxNcx@I}JxaNxR^GvG@LQc2(uQ|Jr-@ne3TNbf3vdn1KY>IXQ_Z
zA;FU$U_`X*oJ`_L2zV00Z<Lb|Fe+d`q*R5jnGAHawjB@=t<?ch(JG~uwqVhYmRjnU
z>qSec(u?A^^<LYem#h7%*Q@w_f7ae-60yCve}7-!XJ+rU*7H2;d7kyGpL?DC1CAc=
z5FQ$fhC?4Rr+OUsd!dKbW4=6?Racp@S=^Sqn4G-NWPYT^H_A2g^fU-$dfDS_!#{1x
zr)A0A6nnt;OudS^^Gl4Msx?<xH6Y#wto+HXHnzsQJu$;H17I`yC>_S8Q><5d&PO#<
zp}SFW)-JBL@G#poCZ6*<P3)qcXI68&Z8XNM@jT&rn2i)hc?R_46m-O8>$kIdsF}fN
zG<ae*iK2K2F&XJ0^RS8BC@=hr%q*TT4&Oxc`b=LuU@kYT%a>F3dEQ)Ci!HvTH}Lk<
zdTg8e;>>iVY2LYhJTloDGixYb>SkzKgen&HFmgHF%Nh^H9)~jpGe6Kyq617syvLPx
zb61z_#>{L<2cWFK(~@$$j=0rGyh&oO%<CBZOtOX*6TON1J!Vv|pwiQg`urGQ`I|vE
zYy0>GJ^JF~c;aS?VwSDJ4$q;<M}Q+)o{>wZ9AqoLjq)(Z8P^Q$Q<jCL9q0ju;y7|%
z<us;;0f>VRSVQq`SG{=}7b+J%$Z7ILPig(oN;mZ;bC{=MLQ0%m&q`JuAQ4-vlOPLv
znA&KwQ%ZAa4v>PtmP&5`NVv90ECfz5_^YC3THz#N(baX_UKQi4UZ6{^g{CmTf(4`s
zBE};KV^JQuQ|!g+26YZVWe_r0%ojzlBpo>Xx+~BSfMh$5OdE<8)1ZUWJTLrI&D@&_
z$;q&#ki9epVGYx)4OF+mB61>l4J{1?++pq5OQ@U32jVn^r8Kv|%VY-$gBzCA-BS{i
zmMjhpK<ks185kK&Fb?w?j<cV(oGEg&3R5h18;v;+kBKd1s7gB!7q!p4C5g9;R#|uj
zg7|0=h?h{}iE-Xc)RojqehRgeT$R}e>@ag=3Ab}8Ay9v`hW$wCF4mo1guzJm#ttD?
z?qLkfM?;p(x^h+<$NKk3A^(Cv*SDqsuayWLl<YLv$O#9=7qcu`;R!hh&C_<kVyx$#
zpkO7Iq%v0O#^tj8oECU;x-o7JQrgilNCc#@(wV95uIEO`I+9pp!lS%#Pi~?B+@@3&
zADOHp1XbtkgOgT-xUk2-EF}s+NsJ>KS#UF<5K5c2P+lbiY$&=zvaAe+HM&z2a8j!n
zL4dryQO+C@(X4$zvaG9Y5to&KI$qxv%REc6q=sUN)Pn9{AS~)GU1KH*7{$?xF;nOW
zOilAH;d8LoiOeA2gNa1RkA<-2wg(LFehq36G~=uo<YB$<hT4*GAyYszdj?A>q|Xs6
zg4$I1V1+ZsqfZe&IawGMzW?&wAB9#2D$--e2^_=9Ham?J)ujW&5Z<G^#@OtP<Hgqq
zhf^!vTvmuc>8GVB@wHS}W=2&shvcRujzqc&Z>|;t)WoZG5$2cBaZPc=afwJ@DjBQZ
z!qc$y=FqnY8B<}JVfX={hk9~ad<d`6(-R9_M`;yF2QaTPabq?~U9W0vuI1WARc8d?
z0bCegnR`4D2BdsA7lq}3f}o6%Ms*L>QxBQ|nnu8bBf6><B-UyjWz)oxF?UoTgq8_C
zPZ-9L5aasGI>po^q>V9Mk(}LyD1wMEenI53(~)P<dQwiw<>_Aicr?#vvU}$Ot!umu
ztxAJFS-hDvF|Uze*iP2L5&P-DN8<$P+Gq?W)EG$;JmM&#4IBvf_zv(K!?`)8=EvD7
zlN(*f%3Kj8BJ(aRF@0j>13JiVjpYJcjp8vMn|5HP?m%aZf#}P@g@Tu;+hHMa$IvDd
zEpf^Z&4P=%G+shM&rBIT-PEdwWIoyF(J;(q%{VMHt#IMAS66pfl>_qADz<PROo4+o
z9ZEqOoz{n%*RvdvH34XU!BbS24RVl20kUX(5`MKKb|qbqp&u&nW++FHW7{DIa^_i9
z!_DX}N8>ZBKpVa>oiHIq;d>!3{?8BvD99rn=}7W;n5T|yW1@+ufZiMt2;^TEmTX3i
zRu~SbngvsI&#T+X+dd~zwonmbn+%E}2yA#c4M9MvB_e}Kqc9FK5(CIY?1S3N5xPPV
zEfPT}WfbTY_XS#FtZFW&5Fr!mX~IbPVmemZ%gayC(NLgm4AD6}fk{Hcp$>?r17Jf;
z6w<?~R~a<o2+|ULg4K@3B)v0P{*){L4i_T1y(KSy#@2bp(>!-D(Rwk3OMPK2{}J=X
z7;fHa97zN^Qwq;--9N7eE2tv^J(;P6Bqx>87aD0@b*R3ups+Ql106iy$UTI;p2;nZ
z;Wb}j5KY2TDp;T2#~irx`Huk~QCL^Vb#ct)RU?S^PUzsO-Q;GEG(uJ2O=P5EDh<sw
z7v4V`%))u9BnM9cxyixt(18}BGs`V-%I82N+D;5WZV$@oHSB;>69CX-^R@R{QjToa
z3QzaQIao}wR1pCXN{w9E9H+nwWicqr(d2-bIuzqG@xw$0>R~q>gCEYJTVsnpldDi3
z;l1UQ4*WxiBZ1lf4NrgqoGLRke|7WR7?wvsXtme@ckEyc8nj)RgEw9gRQsYIaF?|(
zIUp2wP(c0ysA{Fn^9NY)Gl~>>axN#1CZ3QMP+{KSY+SG3Ly;;x;FMLd*ol{)zF8B2
z5eMin1ZY$cI1cbxRSD^I1VvFuQ4L;CJmpr9UF|^tA~!HUgYgS5!w3vHTW%0anZqQ5
zL&Y@%BGZ*}Kwo!tutVv7AMO`SIF&{a%w*n?i36_C0X|>M=4A>NK@UEX!}tdxET<E7
z9PI>9UAmV+4D8`FqBzV>^pJnhIDRq@<APR96nPGM=qr<O*x1;xYMBiUrGtiUr*CQy
z6V26;M@~ri&J!V9ICnX7U5_`Mm4%A+HxC(C%zV2I)^e!pXh1AnE?eVHoJLe?Onjga
zDANOk-|Jxx?r=h7)FWr<sq)@nq2RV5R5lyN$$py%PB6@i)ByEO2Xz`h3-EN*JgN_;
zIAzbr>B!sz-sLn}4tv-Piwzi}0%uj8(3^34m<#1Mw#ufUq`Cr*H$_$#sX&7nL1Es2
z<#nwroe)nmFF}LT;L<oeL$K!4#Vde7q7SPL>IEH+wl}ki4+*J%dAnsiT%k6THbfdF
zV@Fmzp^}+f9Ym9qZCr)dm^oEgH*buCqM!$e9Yz3os;;Ot!i7mx-VvbmD3BSj9C;?C
zfc|0%G<a_I&AWnl21J+P(v?dTMvzQ|z$qF!i2BC@j}2()$(15wb>=}DaV>ylc<74_
zcup*u)o5uq8V6*ns?w|3hhd;9sX17+9Y?%{VpN2Y&oX}r#}r}A6#3EXI1p*I?vL2!
zu%ZFHER3@^$+!PJq<4ZBWjdr}1#s_UK@NNl9p<3)$Y@7TFcWI8GEdzIJJ3Zmmu?&(
z59fw4opVStPI~BR)FN$+6<(0*Qq1ZkS6U-|IUv_LHr;F=A+b2u>3UX!%mPsUz$O!g
z4jqE9g~+_ah2NI~|6u5><ahKLFr6fzQ%ycWWP(d=ZW?Kc3<El3#W-ByN%$Q}&q2;K
zd`C}lHC}-WXZo~NgkG4-LWI-xjUb$TXfZaU>yyskC=pl#i#5iUFvP+(K|(%)t?-=#
zBfz`Dptx7{@C*fPsK<|;DTRGsv%6_hJDrntZZ!8$KPH-+Cm}A0ZyFXhOw+SMcx_eV
zca9=oVo3l_r<jcZW(9BjNYOUOwgf>e&hO0IK{Ao|7dz`rU3q%47?{)a4A71!qS31&
zNQbVcRiG0N5RX$t5c?2dCuSDqbOYdA7-(giGoG~SUs{}^c*e4J(N91&T+cK?vbQZU
zfa7Y~hw|IN&qw5ycHv)@k#IegwevcR>SkKaD)*N0x<F%>A*SVsf7&Qi-a`tl=QI$Q
ziA1P0)Rv;`>XQH#HNwRM8{TkI88V7H?Lw$oF-Bnf`@avT7b)m5!(*l2rZbRcjwNGn
zCcP_encdUn_GjSX*5A>8YR|aAS#KUPtu~K949q{~P0J$AO}feSoMblh<=P!lyM{5-
z*?4;YpkaKrTK~H{Emwt<Ym1YDY@&^~R!vRfDIO#9Qxl1AnS;FcHlDlFurf9E(NeN{
znsH&C3(v~DsoHU_4X}0k$gqo4X0}b5T>07oer)qmZSOFZ7RisMGr;TP+1{mclS2oh
z2oEIt9X}Ff^GG%&y~|HN$g*2UUZ1@?Tkc%CkqKgdTpi)=Mc!l<M^&>gDmNKQ`OU6o
zoyJn$t`;ZV<+lzER~<LYBxxO4=eNu-MJ#Qe=#H&5N4S6Dog*U*x7(5tv;Hw-_at5H
zj?2flJ)LwQ>1iBg94@aJNzTCTYq2G=LzOqwrjtE}MzxMRKC!p?s+r2hJ4|(NV~$@i
zBeQB^q~7G(h}SZjUrYRWvMcP>8=PHV)tNT#`<}HRf@gfZxQY|FW5;ruS6zM)iF1<!
z2P@;d)(E#gG4FD|wb+lRgRUJvU2&b+Pv4Pzao0?nNz?4uk__85Gv+=swxdm3qMT`q
zeE-R;P0N;d;iQ%AEnZmE%}!uWH?6((>`c1LP>+d~&D4=qhfU{lJ{gp8TLODyrMjJ&
zIB!0SM%_*`k<2EWyOq**y6R!t?LcFcn>;2=Z-V8jE`7?QrK=C%fC;8_{rb!z&RW)U
zlubW`^UM^Gt!!OIYXah`*E7w@9x8Mj*=*yh*?@VhyvFrPyxtC<@Uw=St=KIl>{o4E
z>ylv_!RuU<#1k54v-t9MlC0*M@P*cE*Cn}pls$++hJ9-WXbY5zdl#wGcH--1b2nQ;
z-yNEbqH{)*Ek+&CmR787dd<VNo|`nogFfla&hXd}V{G)WT|1l(T^3hu(x};s*vzQ!
z%J<Eyqn`UUOtaoh$Fq2n>#ZqkhqfbT$i5aCjLpg3znIp`^{g|M(v^B9WZmbejZ${p
zBR9LtKCnEw^4be7+I!GkI68m(z77B7iHXZj?_4r!hc6nPdH>4Qk55%rpZ;4r_om}#
zoO}4O<@Rq!NuM5F*f?|Xbz7fYUf*%+^7<!7hR%NA;^?Bo?^}A^!6(aG9$K;Fj0fI6
zbWwMB*{Ku9XQ$p>Deb(kvgCqm&loz7?=M|<&uyg5k~6Q{6EE+Lo6+H{^!n51m%M39
z`Gl<3+B{mjwSMJ|f3o_@)3;U6ZA8n?bvJL>aP6)24O<qky>R`?Rj=*cy6UpSH`lkX
z85+8%Sz3G1-l^)EbKkjn%`2BQ&NyvD<BV&MRP4SfTQ{R8glB%<`!SsOrH^hpdHQ$H
z{myGIdCli8x%lE6<ME51ygl9W>~+U4zj@R7`<|Kp%5nEzxU{nV<~=JuapatpkKVrT
zx^K)b`@xFMl{H`9l)ZTFqVb8}{{G6hJ$l^B4}9ZAFF)|;`;Pnm7b@eGnM+n4`tmo&
zd(+>4(WM_V7YsjqYsvob)@Aj_-gCmMFPe{D_peKahIb_9z(n+#;aB|V#h1Rl9BsJj
zgy_oMUr63~$)`8(UN-v9mtTAKr`MhMqm$ow<D$kHZ(p?Gq+kDy)fc|-)2HtK%5QEy
z>7fsmF8SRLRZqO2)i~oViyI>k|J8<HJ?~W;uDSg;UwYDOUcLT|v({|A@REBQ7yjTK
zOZcqAcw6=R?rV9^<?qbw`b2WUi|={$iqpS$*2Onmv1okHlefDy+2{qy7tUQd*ht3r
zt@)dk6F;50AUW+wH|Y$f^;eEpu2~URPCapRcB=jR@yeh4P5E_?o;Z5ondK+cp7Gh6
zzj|AF`#m?Wy!74|jKA&fAFMpEd>~!1eNj0%_q`?8t&~eQZYyoxGnlmh+mfO7WIVL>
z#J@WEZ8wZBdHt))OSWDaMQ`46<fQS+*>>Bq(R9}<K303<B`rI6!*5hyd)1<~mt6bq
zlN!9M=i~=hu088Bzc=!x>mxh(kM9_H{i_xY9e8}v+RM)yYP|4WM`pJE=eyRAeQ9d_
zy53?opv{{X>A9Dao;Bu@|EqD)N8`@%bMMYxw6(Qt^sRf!QGC|<OZ{29&-=oPWS?KL
zee|Q}?y24VJMPV&c)uC@<jq<3<>ljNpZTJ4W%zfNHb)j+Si6-kXv{9J>^iHS?by96
zyXIV9+4A^zRv!NCBP+)qJ+kuZ{~E7s+;l>^^)H@EuigICSZP-hm3Ag8%YS8}t)DMv
z6DQv>)ZXy5CG9g8o435lEU{PgmL9s|>60!vWi&eblyZ9Tw8>RBTz}-1L$AKordK+f
zwzn-A`_{mQ3q}V@>7FC@w5h1NbLvPm-ke!f`J;4|Q`v5~hqsW-tRH%CX6^7F4z9fL
zC1!kC!;CWqk1sVlN^v|gQgS0{cGqv5c|!d>6P-L*YBh$rD{9AByngxk=<uS^Q%8R1
z?EPzAaK5{5QRP)<-IN{JeSdk|RqtJq?JHNR_f9Q)^Sii@{?<j6<LZOS4cn&ErGGiS
zV)?mOk8L@>!~+CTdFjMxQd{&Qv-SlYbKVuvl7nY0Hq|pq$<8<NDAAUIp^aNuXDmsR
z9WR@#9lEOfvS@d_HhWVvJm&V4lCz^Fmt@h<&J&KDoDM|w8$Qf^ch)a4|G?dOy}vW&
z&t}#(DBlAEN0NIUE@vlJ%H0zg^OiqjnHjft?qBwB=L6ZYo!PCGowxhu*d5s&=RadU
zu=DaAD_(#9<12Rl%};ONdH0GZ#t%*%%(6}A4DGw`{?=d2-M8oAyG;3s_!b7&_c89@
z>RS9TvTvgq+LIj_xtO;GpJN81Q;++b^y=kjkL>48rBfL&myNg6;cT>AO*Sp7?iei}
zc1Myuy@8Sa2ixV|qwRA01z#wgu%<nD!K-dtbn%+Oq_ykj)z^LJ=2t9z$)femHNTNw
zG&Ws2?fmKJ`fYaE4ejCa&F^_R<7_-;KR>@=|NJB7`bznNt@U#DHOluvmG6`!eRB17
zbH}D>^8sG1`oJyG`J+{?6ly$CTpww@|CD9syp``=()+|0$NurQ$5*_6X|}Ulo*a7E
zm}PC7?ztu!NNV`)a&7}UP>VYIMx#<`DHFXp!i{y4#+<q|y84uX^u%~zXs0b3a|f?<
zEg#^g5Xv|>x@_YY2GYa(Bhx(?5AEM=N_##!HS+e=GtrgY9N3wTM|$||@Y;BF_Q@kQ
z{_P{?^x1c%*Ke#RBRmardS_;J@4xY^UD+FZ#}wuCBd5ilCI3z72k_-XdgkZWtTX*s
zWNvRqBbBKrZ4X4zq85+GFZz7ii=*xJ#Vq|dl-;U<^3F>K%R~0VY_U%crSpIBo~Z4n
zqfzd5*~h9sn!LrBNgpMYch9!6S;6~auUPDo`hZz-bsVL3fZ05Xqlw6ci{}=fhTOl|
z4E-8KZgJ<yj>)O$+RytD^WmwXdbPb|%Vc|`<Zm|nkL*q3Md?uYH_gcDbKb1@hnY(6
z(kN}->C?*8{K%?3W=XH*8hqP|q2`?<M$h!T?x!pcr$@T2=_R|^8`u;lToadgAuVhF
zMcn(O)dux2mra%$1GCW}w$apFY@>*O7S@rO_|2PGq}|l9hD$~+j1S<Khi$Z!M?#Ek
zDFb|F61l|q8Aau@1JJlm%pwXk5Uowf6Bh8dvZg#T8h!|HcbTE>la?RdxP5Pu%rgUN
z^@tg&R!ygUC(qT~HIt?v_T2C26FX@}>bl=zl~1B7YoI&1o=6RQ-hQMraMN@T@wF#u
zsdsR<2djyOk4@tAn^<g`SQozYV=Ql>FbvejVWZ<(E8;?_olLQuYQw`q%aNCI_}&4}
z<x>aeu$LcaS~_E=OE%V<$;2ks<kTs?u$0$0YI2^7(<mBEkg83bkuok(Vn`NrycUxz
zY1@1<2HPX+<hA$+3oX`R#@}s*O0(Rk%SJkK_#G5kFmQ*4b6Q?bo9-lOQ{`RnC2mck
zdS__LKboMyB&NLDM|%=uxMrcWhLs!FNZ;!!Lu@UFi?BrNdY4XvoPsVQ*Rk8s7FiTW
z#)`*y_--Z)f)s*c`JU`&P1&OYkxv%NhCV=YK*=(b*pP7iM4_@5JXSnWZ1E&??(^X~
zOj<bbZ8#7(Xpw^q0oM!xtj^k(gO4-q%9N89xcQKuh!`PeJ!7nmjfIB`;Su>(Kmzbi
zXUl;e<;QuU9D&XNK!*%8+DU>)8+4#henhPoQQJY%X7+Pfj$F3Xdlu`^X~Md+g^sTR
zpw1KVmfO;}1z2SmlApLf5I7Lt20CixR2`@filpCs`^kXOiOYMFKJuBTE`0x=-1wk*
zY+d-y&!eAs{HpgqcgcgFJMWc$d&NcHz3!RMT>Q4red8NH``oX;?f0Jf`~T;n=e~FG
zX&?OHuAhDKqVUYm-k(2r?nyuV;8}nC$qPRF)D{2h=X-zt^Xp#z!*9Iy+jn2|;N#zY
z`5(XS=bzjA=g)of#*h8<f{*X}?rHD&$<OaS_h-+&=B+=v;_IJ%JLz4|{qVJ)`uQd6
zK6~(tpPhT<=iamHCx3F$KRtKO$$xj{MW6cBD?jtp8=iRYb1(VfTYhC3>DQk5zn;75
z8{d4xl?TuM^JPEh8$)OQ{*5=@{+=5zyW*lxz2?d{{^^C^{PSy1{=28HT3z4sseM<T
z^v9Qc^S@trm7MZlp5}Zt&;0zsbtm27%(c_p8tEy1#dnge&X{}VlTik0zG2FnASUCb
zcbJK6K6N85q8|A1;P5PUF;+HXUyq{cG^szGO=OSJT>W@OeP;BLWxP7B98LIc*$$6n
zaffYI{e(A%_iLzLLwo2^4F{-59vRd-wOIi~TnH~qCe9w&R&z;*bb3hR(ZKqI@iW~)
z-yV&JOOCfXaH~YJjy^E4cbKPHR?|;bj|@lQem^RH{h}7O#JUC6tlnV&mG>%2p6;wG
znKyzEJND#`O%P9xrfrCZ9)1-0Z^UBZ{4WxYN#;>?$^Qemf*xAy|AF`UWcrGpEqL$`
zazZWZEEGiM(bp6>{<A5s`+%Ien_VON6?^EQ1+9wZ6=~cr#kR%1DDjrD;{?6)Cb8a|
zTFpcZFu2-^If<Er5;NP?Z6q6+zSu9S3@i<=$B6>RR6OW-z9y8$N26vb`mBBvb&0Fd
z4iHD}(LglPn6UvWl}IvBW_TFXSQhGn>^^KJ!vniXbb=hl7WR>`j?N!VhMR<1-0wu+
zk6{roUS?eHT2pH?JX$c;B#RlP*}(v2EsP^|ZeCQu216A(6ZJwy7tg81XfEPXycC7W
zXV6Tu*F&0(fQV;99lIB%<ur!yn=0UR!cO)hlFzrc5DPzJ)GiHpTb%i}hK3~{;Y{WZ
zHY-$jzt8)RP$OvQ#5Ajb4&)5}k0ssnAce7PMv+c(GWZFY?&ClxuNlL~R=II4zR>VS
z&gr<#{9JT`s16nAa`!}3wZeMCS>MHz1@fsG<3=6g>;Z8bKD8KIbz@G(;Q~f;^l5!z
zBL8lk5y?`-V;(YaJdA+nrhri@C@&dkZK?(Bj*qHHPskbhzHtMw1DCf6M6nGi{u*pH
zrtym4%yBR<J{aTBM>Sibkxqf^^H`*$mtBVS3=JxGC^y59Z<3ScUJ)$gUhK@tzaAWA
zvYe+{oYRDQkc9<skE3NTRVA}t(o^TSoxy_r{SO8n6`n=QLg|CZ@Vu7CYxo3X(m85W
zO<p#|vQG8J%8LFJlJkyxUWQGR{Z8zcN;;0%4suv!POv#jrW|C9fmR(I7R4A)^yosW
zk=s}gn#A&q5VR=raYCO=df>^21rcRcLe(3qAqes_ZI^hz?<H`?4vUNpd&vn|MQ1_F
znP%y*H8;XT;D#^B4r>Aho=2PlfE2zw(x65ZlSmmCej^|@=#}QaS8&EnDPgD^m8l~Y
zGLJa-wG-X%I2G;@K{)cc{f6Z?K-wzoL$H{H_yWTOYiOl?WC>_n<-}#y@U1V?B=5cJ
zjk)+GA^;tZX|x3;GCTjdN@-7(IG8-xoKC0`SsRdhO*8z&>?O&8COg?wjWCj}p#U>1
z=P4H|uJ0N!GQduF!bJstZV@F#R-Hsx10oVKTD^K4;8>9fptILaBp(fmpP(dao<o_Y
z2y78&e8WmhjRvrJ&_5>@1t@ZTgi47<M;;OM>$MH)ZQu)RtkZa*mmY}dgLT9h3!Hhx
z)J@B335Q1jM>d%j?j#5=!%za|;5__nCX^HeHfce7Xa#YO&k0<Ld3c0VJ-+w5l6}+y
zJe8UTw@0~Nkt-htL+@?NY5TxCLL2C*lRBjZ6NF9f@O4`IpoQMxk?mt;3=n*ewYiVG
zg`5@*Pc~>t3(fS%t2FW1I-#Hk4cwfJ7Y)5>g?#c4GmBc1?-K8WWQh+$rQV17BT0E2
z&6fI{NlJk%92}aqXv@g-grQX&GU?_0-YWSPQi3eV*q{LI{4|}npkNa?&CLrCZUE3M
zQ`n3-7)D0YPPhiyQe;`l(vgJKTLNDILK&6>bzqdI$VbdhNm$H;X_bOWY3LF*AKu;-
z`s>eb(KQ_S4tV(~5`&<}L7yc#9r~+-#;vFhGk{^{PJxQy7$s$eA6icuJp9#JXVhQQ
zX?8kP%v#q>&$(bl4F*~`hw7ro;Y>1vkqPzAU26Kn&kh8(S{{f>Er>8gWOrwIBs78~
z9hpM4R}SjYU#*g4^TdZI$lzH8J3{Id>CVI}pipm)dhuY)YIBcN;b-9+jjZrysB1Uo
zz$QIQ(|2L=FjiIE3}g8m8GuRjbr>-8Y-J7-sD^AA`}E_ZOCF*4rrzMzP|?8ZmeZJ6
zx&n$bvK<bYpcKlt21cdx3bXpz4_vMz8EXbggDg{6_{47BEq4=nRZe3$oQ6^g<A^39
zA3Y&F<H%(^bdO7{(aq9TYn+#8ER765m;ECGJw3$ADrYv88`j19yhon;F+ZPiuVL5b
zcBRdzUWrmQVy;%ASPizDi%-cPcT7A(wj*plB&KbN%G1+k+V&cXCC1M46Sw*@Q8{5u
zV`W$dW0S)yFpMdQ{}NF?E!CP9PQ`0DKS_*V{1^+Y`UbJgJdO}u=bMTtVNUE2UEw9o
zjtvTfh#BOoIe8Lzq3g+I<+s@I{Iv`uRtwFaCyF|5q!W2l)m+BnSYWxr9>rWmDK6t$
zWQLrQWg$?xXR#%~E5K~FjwXyrAM_+*XMi6*YRs1#=$RwY4U&YG4+^j$4E5J5P(|Pr
z#vIrgVN32LLQhoC$%BQnrAa#&sSjX5gA!Irs~9ko2WF7a8i#o})1gOMj%JhUg?nzW
zA=pBY=U4Fs{NQ^`CZ5<0Sn7%z5kz@fXRlL#Inz%IClRbsl+_pcdDJ5>GdM(0b0L3N
z!Yd9Y_7H4H$a>gvje*x_Ia0_19g87I3Diuo$sLYak$wSeAULwC{{H1}gKCPe926EK
z;!Yk{T7JTS9)qHUbFI$EDzXhL$)MJf6mg0pwJuZ#(E!0B#@l8{g?WT0{EUY)H$1^y
z?_eu|aVB=fIwf157ueX4GZ+%gf|aK=8x7~&l<7@FZOBZyV|lR#QNOStCR}b<AVQ~l
zqzN?vnx1mO=DDg3Lk^~hOy)dr5Q*^%E=+P8cNd@xl;hW@%#+#C6r!;G3%0OW5}4DH
z*yWKh=2}YvhH6{tqm=e3pG$^TE0ac!vy$C02WjiXh{HpkG{z(nxGy3AoKUL2`#(a;
z3uSczl7dC?2@amH;taA_!$#cD<8oWA<gefWP@|0ehOHCeIkc>EYVO3L21dxfm#dot
z4HOD(@JuF)WjQdTQ#YWGwF=Qel65E*c<!yUA%d_MD3XKkN1mT-pcAdCXTcuIW<!s#
zy0<VaI4vrU4Ci#2@2ujvVTu+eQapJk2gSXjLX74G!_mxbSW1Sx{5Bs|3N~+LNuj7H
z53E5Xw+=u9x}kjzn0G1xs-ZBfPql01XwQAXe0~sDilShGK)778Q<7+IFgp~ow@?bj
zBRVIEuK*C9sPGCGKnSw>B8!(8)*qy?NGHH?92GAa$E3tS(_}^tF;3VSz!H(o6Qp9r
zSPBHl^@V7kR}S*R<jz&B4|=sqFkw=dI)~a8vaHg859eb}8bNaCkB<^B@H#bhvWVd*
zV1eFOUxaZ`^1RZ9Y@Ed7I0|n>;VMt*W56n&1ca_b#?K~dZGj1BWk-R<L6p<yI9}kc
z{cU6BbP}GmjKW`liJV5>G<Ct8+#umKYYAu@%6FII@P#$cv2q-;i*`3xs9%`A8vUZ_
zszCyR_*5TgEFkaWly5%Y>odMTXQIO@d!fsd0lBF?nm35(`^>{^kmKnX!+97MIA9|V
z1chP*9{jFk)MI>vD7xnuvYZ0+brhL`35wTqa-{ZQiQAA@NJMH$Re%k0m6-CP<og74
z(4a^4n2%F7j0pWAij!e42SVK(Bpu2`5(8K+$PCXdc?3Y=tUckPM0K1Oav~6eGGd{2
zd;&LzaY2O2lBg~{DDOByv&Z;aTt!l9kAmXVgHw(^gQ(zC7dGJZj&UIY(jL`TabP~r
zqz{D$4zIzf;Pqlqeb6`OiFl6SXRW<eVk-n9vDFiX2Cg}db&vxmpp20v1SB;ovT18U
z;KNzGtXoAZKzt!tv?tfMi7|F+u3&2CJbEREz!&3ht_g%KWQYj-@W;IW?fN`^RMoLQ
z%W21+`(8U1_wUDh|31k$XoXL5m;Y~gkCJ{_zdcGUV!zDuODrH%PMZ^sDRQWj9J_Fi
z7Gg!jAB!l)mSa&xv0T8}V=4cE_<x*#$Jh9#3-`F?WjQK3)TKLGzN2*uPf?hug8i7H
z2h0MmFBtya!2P?Fe~a*ob@F_z|5gs+3g3G5uN?YeNadaOdBSYL`M(Jk3fbrR59Co>
zaXJ6@Kc9z3&oUvmOm$K~SZZrs3FKFEIbk*gMLpDV+=6U%SsyA%*G3{@Y+k}*CwLx)
zqrIQ`--gVLHEMQ_BY@}Zz>MX|yshgBUR;{(ih+dTNF049q78sYY@B?b;0uGT@B(Ly
zS4g=-X!3FuLyQ#(2x1IUDOZqCh*=nkTwvqm6@fih2%8lG2qG{zKnNV|qHh<X<@56o
z=JZ?)^Nl5Ki%iC0o8r2f&{bowHAXOL$9-og0hyGV@IcGi_%+apmyA<khe-3IycUHW
z0vXT^B3k<CgzS(=d$Ap(4au4h)EcIwP5IcR^8~&T%E4+c!dS-<M7$FbP&<W~uy3x<
zR_QHFF@%B*ZMm3!xiHv7R%_b?HV0!~?&6wc))wXFZXr{Jnrj1ltidAi@)%=kM5cn6
ze!0*FGxH+SWpImwND|m!%Eb@?R43cdBLZ*k4TX6!=UBLyFp0z-%VeC=N5Q!~p7Ks6
zpGS)zPb{1<`xgK!1;K_q8XUe5RbBL<nD6^Z)srm}&np8Z4&cMthVw5(y;AB}{gO&p
z4#6VZPu0bCwB&`ked_bw@C&vFrd+;LoV>rJZK2$`VAaXF*TJjBkuqp}wIScFp`wGQ
z8pe7^w3UQkz|qO?sIZZ+WYPE$-b5v3j`4v_4r4sWAO~xu`5>8s3FpHA;#|Plp`gtq
zY#WE7Ir;>z1b{Eei>55O%|TOO_q?J<mqTjY`WXd-F)Fa}8?Hl52b7rsr)62bJ}oqv
zLX4Y;^SW>t!e<XL3~p%(<(?}wFe-oB2e{eDS@=-N{6Y+15Oum1CyOjmxr8%w95N0@
zhImF6LJvx9DKidU)Y(%X5F7kOx#6G~R_D-9LXj=Z0Tl&2r`!|9nRGI5CUO#U!mL3%
z#)L+tEa4S=j)-7k|4;QIh+z+La$$h%1M-D=c=p={#DX?bk}sW-)z4~jwwxFmQ1FC`
zsQmJVq=qH0@<;~Y!<hu$34^Q+2u`kuNQ_l{Rwp1>Vsp(Jh;mfWMl@(Ea0+_;xF=#^
z4+g`gItdU&IHJm$qD%eYbncxIxS&n*$%0_8lF=$GQ5&@~YBmU<3RDyehoCQ9zqKPg
zSHe#M-jhS=d5!=+&s1D{M#kA3A2F|IW_O-YkHjc4$^;#<&vFD!X!Ak_tym#wK*y*&
z;Ru-IE&5?4A?|Rh5n7Irm5_Yu6KPaZLZy#&ZHw~ozrbcv=0niZ#$gG>8ubV!Y+gp9
z`KCjLP87ufArTy25)onhVk~dY%XxU6m1qLh$+(`g3I_A!&dtQ@QYu!LOEgy)Wnc`F
zO|yu;mBMn*sWG2`ZwrU#Fo)0=IZhlhf%|jJ>;ON>OAKl2IeFr<A<2%fL~tZ^(A-22
z)JRnhuxZZI@D|<*n4!s&o<dBpSL0F>5geVsW+Z~6gSyU40v~{woL$-kb)78#WSS?c
zUo7r|<`c#xiRej8U{ft2WmZ&ao0LZxqb&HKNt?GjIRteyIpW>pLlSm0$?10>LIY+F
za5RZo$`wk%cpSohZ&sbG`3>=c4nL||vSWd4^9n#?pI|ziLlI>J7rYV-IEkcvI?ia9
z?IDZn5}|kjq9m8+i?jqB)7;3fAHy8DzP_9vfrZ6|C*Y70R%v2JgvPmoC1^vg^P)`a
zByR{J<3j}MoYE64^sFL)EJ-}4j3NbtEeS!Amyj4}u_+yKEC8Av2|Krd@rmY!(BAsE
zL=nd!5t>f_MwMOW5Cn}2{o5RWKDbbzpfIo;Jsm2d5@{7rLw2vIAW5fuu7@B8OQ{M7
zh6GF8(W>bapC7uuSC1j!?NA8c_iI55Mkt<ZD6k<NN)bOFf0UzNdA?s<ncI*5TiNmw
zA0yxwqQ~Uu+b?128{CqCZ=ZNmh;j-quMP>BPxAvTN7H0;R6)`VRl_gIbQ;Ht5?OqB
zEX!{{f=^AF5!Rz}c7n7EKJ`j_?IjcDKSSn~ulq4z>6cCIRy=SOAOmDGA>$CQ3Pm;{
zwu>{(>d2>U`TSZrm@6{C5+sBn4m}9<O4S*#S*Ipe@$esP5DAd0y;V$L!#NZpTsnqy
z5@dH2=UDI&$xdN`gaGpGKc6O<4g3ajN?6+UZ3JN~u&f=hEpD1wuUE}l<CO+xCLKIH
zNbVtPh?<mLC2~7z8z0RX)_%;nQ`>_H;#&aQA}Tr96HnyxtB7stoW)A8l1>+1QR4G<
z5T*^~u;_9Yn*2_EdV){~_?VmiL*A)+D0(EC*sSG5IlJhDhnrJK=^$Q!p9ncMH~}fe
zA=0ZAd5KrB!$NW#x=l|T%VBL}i9_Qp7oDIi2rw7l0gC452DC@rFgLwy*QJ9~BgZ#i
zRecPs-`3i3=(d|0&OS05ot9lT@@V%ClO43l`0yW9r`9J+hOc>iY$SQ#7h5lgw@lh?
zb2pQ>vAFzLcedpZ+H~NK4>!qcqD_^9X>vhlTjgM5aD3*|8>d#3erupLcxdFN_ubrD
zUfXh~9hiHh{kXB{b;{cqiPKGwW#}z$$_|bs*tH1R<HMg0dbg2x7Q1r2<lPhOs-SoJ
zvg+_a->%J-%hL(;%C38`3nzp!Kk+nPdBkY6<SmN>mate4s?;H6c#=MksA?mQI8<8{
z>t+M7InIC&M7cI3^O=!oGN`oEydM+ccKyhEB3`lp>q4-gccFphdJ}H#vw?%<hoG=)
zL9eP)Q0Ogj<7-~2L2te+h}(MOoS#=czjZA!EU@j_q?{e7Z%>C;Wi{*4ch2(AZ8Fj-
z$2~;s7~l=Bo-anYZjxraPPIF2qM9{B@5~<8_bmBn<9<J#rm!Wvy7ZP?YDwu`Q8n&O
z&!usdj~dRUEkEI0T&Xr<H)9e4o8tOpdpek9z4~tS2D@6f%wu!VTiC_$7EQLLx3J3=
zdSzF6DsJ}m_U+pDEv94i_U)o6GY@Avn<wO-X%2aR#^&R&XSE#skE?3nRi$kLhQhFd
zS(2luJ@|4t!!{2yC;vf*6uJ<hcEh}ZAe@!^6UG;thn$0a=@;Z;icq{c_<mHO4mNCj
zPjNEvY<9RVi!9}U=!EC+9M1zU8+?H*6KbqiTVR13iX6ibB8XX6u=4PD0B9~OvP?b+
zIIyU8vfXm%_GC9`=8-E@|58z*ctROw0&iy4DFb*Hf}<zy>G;?`k+*2K2$IESa5lFk
z)R)f<%z{#glr`}Lssoj~>kRjqEB5b$6^UX<y5<}HJyEaTE}wjuLk-1oP$}LLI1cjU
zjl>eqE6WEvj!}0A(oT*($gEHb@gplw81tv(v3({8)keN9!&d=9*+a(M79kPQ>E*Tt
zo=Kg_pgemx)Y1Qfqb7vvi)Kw2kqXc^(<+7RewuJfI2~Hn6NWiQVzjcZ6F3gCv<U)(
zrUPfpU;P6~^1Hxmj3>#!sB`FF>Jw&w!*krn@f8l_D6bEBswCiV%1@ei`v4QZ5^Ib>
z#mJT0JV9U~xG1E3A<zq_L-0;~tx2#iupj2sg|n9eXrWq|v-JhCP{_V-`kbNj_Y>GI
z`rT?QfMht14hQZM1X~L2j&cTnN<NpF0;iMGvP;diD@2}Gu~4uO+R#sQrJ>7d56*25
z#uW=VY`_h^pEZPxF<wfk`%rG;{4@S!JBqfc<N~xNLUivV1xDhFu}zpMovcndc-M~+
z;^RcZgj0Adq%Kc^4`u~hj$!b`A%xN#gI3hbGsnt%KA#H`^ITSft?~q4^d<VEEJrmv
zF+q@Q#;OIthYN-rqgOup*1ZPV<niLRIvoYjzXXyc2s9E(*8=93Pkr9!QIZZOi`MQF
z{tZRNZ38NcpDp-o;Z0klBZ$1Q-CM%v!!PJYU!h`Be8;Mj_j0jeJMb8yC;^;PfR5V}
zBcGjJjN!A}K{vLTsfP*o_tNESu~o8>H>G-WJj~p2Jnx$tzncn~r;%^&n3;oR9`1qf
ze407!c%<#}wl)NgCZEVijVoP_8LoNQ)-mneP_J&egJVfu^IPT#80Y!g0Cb+Dnvwpw
z#LS5A?hzjKu_pZpb}gshY}lmYW&Rz@^(A{?6dW}951W02r1fyLSX-+vznl0*NUZrM
z>oNEBTCU}JpUC+P2W}+m@D-W31K%wuT}qhnlg8JP#Y4%lBVEAvW_SV5UH#PmAO3&M
z0~a5nYy1nPQrina8#oHT&=YgCFBpy`(E$6PXnHKIPgn>;{snaf+Aom*0}=cD+`pXX
z9Xxw?EGUP1ArR@_%CJkw{5CyJljq@e(+b^~lX_ETrZh*>C!Tg1J?QH!Hp-ev;ZNH7
z*nGp7J9*$AN|*?ZHO3>IZ(WfAIlKgN+Oi&&)(O@TmNA4VZ$mUY$)kI~Cs_*}Pv7>A
zODO2?0AGA82|JWAYx1roQ)TTBcs;cj3}kGuAjC19nV@2lxG;AiLu+T*FZhB9SJA<y
z|GSBOXo6*?#Xxum^g$kIpJWS#SN=P`$#auQ!bV-o<@qNu(@D-OOAvzSY3vv&@r(~~
z&%Lb)i>fmkSsT@Qv0&iVO`0{iAvV6+tegq<c-9}=oR#@3fIwh_)&aa>+L*oIc=v$s
zftz7LbEh$%;-0#gGGvkEx&8b*Fi6Fk{N7mYr(|D<SR0Rkab&l#sp}$0!y)2$O}@Cj
zBbUHCQ_(dPv?XnZXo|<m#RO+K&`}HBgc`VM98#39yY3yE*>D=yV{Eq6pA3iQbVf%^
z{e`%NADRa}sr^n1KS~C{>E&ix-^3hY0gu3%;;<L%GV_iiJ&${W7z?71r@0E7RWkF%
zCWfob2<wFsa64eat`PMAOmd9iH>bGMmUI;2{FaxACQJ+ddDeLPZO`8cQuCR!oc2m1
zJcz0h;S@#ra<DV$S$d%paML=ohAUe|*uGj=gl1+Agl7&#SsXQjnSZz#TmbAxy!u}#
zo03kyO~MC6e{I8Z7sCKN*pTgN%sE735HQV$XP?M}&)S%j^sfbrYoo9cuQBK*h*o(y
z%@Ra9u`c{Pip$U`htpfQAe+d^?6B38=K&p=rio&0SHO&7z-s~8li`5oX&;-OTyNnL
zQ%ymlQ^;ldCipD%Hef@O_lo|m<RF>=F@$_Ih$Vw1zb6TBQ+n7LVEj-L;?o3Lms`Rd
zGJQBk;5dS1C8Yow<QFYt27h|YSSrY<MpHcKh=Mu8D`~O8rPfO>QOW+5_YoFA*34s;
zFSdie_pFh9meGlj4Bo<tUulqGuhKi>)gm|cXD-Cqz_U3rHv4W-fgA_<P3$;@%MKPY
zHlXR4F~4kM5)2*mgp%bvHjite%$S7p1t`UR!v$aLDSn)BWkGov(qM==xWuRL=)t0h
zr)JZ!&}lksSa=@Mr7P2U=or=#31ah3MfML^r!uRfLC2(cjO{TsSMgf3@>V##_Qa74
z&@?<v3|-}%haMxa5rn2$Cqr=BX;Hc<wkHDraCjSd@QH3R4HuUAFFE<1LMr`v=`3#)
zoHL|{9J<jVkPWg6e86arHK?O&6ROBv@nOH`$FF6I({&tYn<cdB(42)-{dR|IisGtJ
zLmC9F(#43QCg_xgqu;QIXI*TK=0SR?5fzh=U^$_Ib!bonkv8e3;IS<;=1mLJ6Q@ZT
z+dPcU0GfEcBHOW)7l+C@oW7&%g!4wF=0>E@E<vaQ^?hj`RB<F#AXts};B1oH8Jsy}
zoQDt!&)2?CgguFkZJq(OjAPi#e-4?M#XiXqbR|`Q6JYgDYH0mJxrk%3&%g~OLdsc@
zv9n|BM_A1OJjtKMu5B<17!X25TW~6a$xd1i-5-uL*ur~p$`)owlrdz)a$zK&fhx>j
zEEcRVpM9CmxPLarJnKDA70-t8I}7#um^onS9<XTKVxTCVH|JA!;R__ZQl4zGjtQ#k
z2(^`>x3}Vl@L^l-DPXDNL4+1!#-PW|j_e4fubKI+Su}=rvSzd&J<|h;O2GwQSo}LQ
z5E18{n<JE-QECT^N7|N2VBiZ=`Y9p9K|PNEQ%meR-cB9IST?uHbXY4fLg>A!!0~FU
zHtd@zYjYV}kWPe(v8xlBe`Pv664#K?{N~(cR}ay_Sc@$THF^YHH0oDBwWnq*aSpd8
z^TyFQtg}egvr@0u*n*{FW|lg{+{`T>fWKl6dK;E_EDc6@KbWcDFV<oVeNM_)H^EKI
zM4~I<bi*sV!nVBS0ek5kjPMUnqfL)R9$pKF)BMQQTclTC%nK8n-&rfK$KhwBjkcMD
z8#Hc>q491okBCQ*Q?oNzQHgIcX2Kkxn}@l;`3AomU1rjF#u>*0q~x+3%v~*$esv;$
z+^>Zoo?ApzeHaS@#ES^9`C*zHrg`faYX+P3yJ$mp3(xan5O%gZrtS|OHp%ZAi((8N
zq_oMZd`zR?stsw~*vXfm=37y&Au@^g)D$lAOj)C*j$Q1%xom>(w>w@LW6jqLLp$rc
z`%KT%3EJudj{I|>5OlIuT+>@SL#;%K*_zdoo9X(9jj}ziX%=hE1>YLuecp1-BfOSw
zeZIJ9UzpP1(QhfsS8a)_eb(rlZn120rExo^_d*14f0XsqSVx=r;@Iq^j_KoB&)B&}
zC87i^8kX$!rk1*C?A@)rL6;)t1wCUP{YN7DpfD<p0ntRJVA>h4G0meBUn7JB&>&6;
zjJy^uWWZ^niEQwrBQeT}9+d<{4MaY3DuViO&SjC93`zse`0hj=!LI^&V@`J2@NeQ4
zNXMaM55GqUXfY7P)O!TBlM7ehns=!1Vr_CvaJ#?8nj9=srAj>2%<5Xcb+{YIibQr5
z8I5WN8W;n_P{C!Ec43be+Nuq?WRcXwls9OaquA6uU{wGagfde&j{-dc5v-qzL<>N}
z6)&8_Qky74BB$Ri`5ZwQ%?QDc4hm2Bw${6DLk_8V@>(wkR5@Z3_Q{Cla||KFUKmfK
z*s5exB#qaJ#z6H3gJcs~nU2F3goTwNugF9zmK7cb{ooVTtgr!i4PkDbxA0&e-^`d0
z#zXGN32J{366{MHNFeB>FJp*@<imP{tS(S>f>}#Pl-k4=XbV0T1x~uUA_4NLM3e(c
zW3?x691RYNJe^dHlcQ81^d(b<@ksH2P(&~Iu)z;uM&v6qAOIABp63V<t7-~1LS*J_
zLaG%G5g=Hy)sO`GO<Hmk$Og<-zpLn-^o|1(s8nq!*i8@@?M~EV<g-eUOv;jH>{&4&
zGMOfv;plNVc%<7A7dz5D5r#J<bS+{Pq>Kj+#S*}F0pqpe8r6Ya95$39a7YKjCJLwZ
zjk3aqwiO~eS;iY6R2^aJLLKLIZ?Gen8w~L1!WMj6*d?Edp-?s_%}O&=2TRoE7~k`P
zQ9$uq%$31*BPVit8A^K!3EHt}ZONz6ik}QoQ{o)8Y=zJx^SOKi$AJ@RF~|vtIP7O=
z2n>a0PSTKbnw|mi&~oq!7>X@{y?0K_H$k8?8nf1xcRkm{p)o=7k>w17tL0J#L*QkJ
z%EbE$S<1pujManU4Fw>Z3(E`yRKs_#7!z_C(Waau!4Gsc20?l&{3V;YK`e7tS(QIG
zkT5_G2Z@h$c_?RM;fc&0hY1Cco#=)pWC`lXD&z<oukKoh^xTNdIUCUq11BSvWqst}
zqA+Tn3T)ynfy5G4oTbbTKbMnvK5s_G*f<9Q=G^g3e31{{X~Zv4*+x%SQx;09kGsR#
zN{!cC5+QS)#sd^dy21`gr_ln9jJfkhc#5pGcNmG(O4U7Luxto~vWD;9ee_8%F5p8`
zRm$sB$DcskthXW3;Y^uBT&G+Fk-SEnaDqtAbE0d{34K_V^UCuzRnDw~4%tHmV&gdn
zoRY?IXyS-+a!`=#^}5CbAlQPaWJYTS_L+w5@q!=(SmR>Cj+sEYjf^Hku4Ecw6C_Ql
zmu5bZ%cU`PrN#~>F3`KMSPCnXWxSNd3_BJ0vq4A}gz}PUn+Xb=Xz*ZoL6{90)LDqh
zVnw`7JV{3~h|A|VrECPIggS-+i$2T+>p1#6aqhsP&|4K+Q8T;RA<SXPr`L<Wtdm70
zYj!D?-T60rFvKeza|Xm>bK__wrd8mT#|%48-f{xGP7V0I={cfpM-z;ztYxh-GVx%o
z&8-bXkc-P6MMz>i3gd5$Y)<2s)%;~j>?49<q~}~T4cyOK9-E*CtI6&t2?;LxDHjRY
zJsGz`(YI4o1W#bIt^y#>6QYi@)hU1r=g7>}h&dbNawfl%nr@KeHGiNAl(ES26CoNl
zz_iCffAnqX05B!A>$x~Y6N*U<fpx(OEegybM|)sx)E<T+rO-W+Lz_~uyJ6}8FCeW8
zMcSm5dO$jyiNd-Pgv&AE`%C{of_I$-tTi=E;mQM?JQo5&pswC43FHRh9Q((*xU<3t
z!i1r#lK@%dL)c!J)?G*&SwVjRcs)R_V}e9KpOXel*#gcL8uN-JWi9wV(ADKZZ|csr
zZ67P2_(GmTOCo~L+c<SDGpmfVC1?Nw^N14apc>aOAQd`t`~awBX29!AalJyvUx+A?
zw#cK8Jx6XpX=TkPH}QCgiLeP5ipcWLBz#p|7%gK%<PeQA3QXe5Npet~Yd}ZR3dLE@
zV_?n4_TV)2Q7dAo%ejq295`+7NfNb$80$!cr54*B&J(vBdV?@OU?}b5P}j=Cr@2gh
zqF9leF7ES@7)8S)S>mxGma$n4gd-BWJ{b~mKqGE&#(_95p^&i7abmrn^N%iMvy7ok
zISC}26N|Tzjm9LiWS()CoXV(D7vpLcw4(?Do|#rfr4Git`3B~&+{$d<N%DrE!XQrI
zdYr;dodGXpNHTS=0_>obG?YH(8I+J)+N?DbFnhTg3w4ei<5V2k2}!1EG1)q39%5vT
zIm?))0p>Z{;xSge$^{Wndb-$%LA&T=&Xvua@T9T>^Kgejjkvc~_F9H`_&vQ)9L*j}
zhXr_ytP2S`;cStZ3cMsD#!uT{jXK7b8P;3QiEK@eZ^aR_Ra^@bYOGU;V}dnA0le9l
zMsu>J1uAB=X1s$YhPe1~##EJzoOi6kBAjA#zac@j=V3K%DOS}*FdPH(dAyqk*aMkk
zN@=cU)jko>%E`t|BrN4@o|<)enA;qxhmE0JR}<3eqWy9a$Na5<gA7@b2eGP}sFp?+
zqae8O2t}X4V>s{FbqHJl%|j#)Eg*sr^Xq?0#}Y0xYd8y;@E<hY`xxe1E|f)|4(c1R
z;_AmCNy_p6w3;#Cs1A+}`?n^@3GxsU{t@GnIt0X{L*Oi@BpoOWpFu*jF{l$2h@4JT
zxQzFx6VVaRVMvuCsOL>_AuIANXfoskLV<-LB7_Xd2_<28n5|xIA5?`BNU--!vXGFN
z{G^Bg0l6;n6lGC_;hPnu7YA;e(0~%x#F+{~_c6h97*PxqNVfbr$V23JRb#ConalKK
zYevw5)sg|&q6x)J<OND-t$<_Ow?%|Op#`ePkA0@^2^VmTcNoRSQif5?(Rm{<qY!Dp
zO_nchDP|($Ol#CY%*=sXdX5<g9>$@=HSm@?a>mbLfrHhPp904|I4IVdzP43-S<@TK
z%b3Qhv5o1_l51J4@Er>BGeAh6^OV3@%4Qr=Xh<`xi+JONd75Szipx->wPV#mHa!#5
z{}GqYa1(!O_82uq4}~u|8VkWI6QaGVN}$PD=X*k-tz<b4z!#zB;2CYcq1B^DB+rTE
z4S>tyA^B|9lXAfzeAcq0Djta(%+r{P>L3H9_zMd1w8GSHJ$}Cp`gubYSmdep3RlbL
z;&YZv?B6<w9a9TU(;K_{6Hr5sgssjP;2a}+bsqUwsGjk=n^hyD4fRLukebJbIXDr~
zpO7RHz-p^R2F4VQO=;3O$Sc^^Bh|)=ycBA@mi#VrbIRmg;+emR0S)9jGUa24a_4HS
zL`g?ZcWX((=)()*QQTHKfLk!Dj}f2C?X@&jm$X8Kv`iE@Vl`j@;hq{&^RNr;e`lx)
zy>`~jLh~($@v>TF$m>;7=$*Ffz{MnTP>e#N7Y1uJ;T1WpY@wy;on^sVM_NVALqk|$
z0?P82lxCJ67+Qe?d7;fH!P~+3GwD2WFKJGCkgIQL-6;!EIpzjWpMx@=j@~*tw|ioy
zXAW9^fSY%Y7h2P1yxZs8#;V&N_dE{=J9l2m(xu#?!7aug*1Xo^=hSw`MA_8jVbgZ;
zHQsU~+Q#_B-5JYkvf0)kqqlY-eza>YbWzL4^~(H!t;UV>sKk23dw#ZxcQoyHRPN!!
zEKbU?JIi#drq}eAFGnnK#x_mYcW9b%(^}mGv8y>cRXxYuHHgn_<YqQpovrC6+5FP0
zy<X_zFRL=<Bou>BgUj<H#{Ac;<e4Vb+}&uh-OQWAbgScB&*F?V*3Femjc_3l)7dLE
zH`PMUo@URi$Ie~V-d*MR;Z3I5oZr#$hYwpf$ZlB8#0_or;P<J^yDsszW_K{wW}DZW
zf9%9GVZOsoox~TW_BLCd+d`Gn{S3`{?*3(UJKsIcER895XXE^qY&Wm#T~>0d*74c(
zGOg~cx{qo@J@rTp^v&J-Rgo2j_b%TPWP@3C$+ySQK9=@ebPg5WF)Om>Eq4yG>N3<U
z|K~?_`fb|P?I|9q4>;>^0JiT)O?QvkhpM^3?Wrpd@@=o>kBn7amb9z>3+(vz+<~@<
z>)dx6JAOB#8XOA^`|$WRqlcz2J2n*`?KSOxHT%*>M+a?8!-}(JdwQ^BpC-GpU6ZX&
zqM6ZVI(L8!{L*BqW?=h;TV_4?_RYpoyeQk}?i<|i^u<xKvx?Z)+M4yoY?N3taSl%e
z8}qbjy7XW&$7qCrWW_DLsyQ@fttq-ptrewDyWSzLMZ8<Z)k9kKy&JQ(DdPc~k0|p4
zvCj?|)rZT>CiBPy4Ivpxe7t>rTWamo$$H;ym1My!vpXjqw%yDgj#$~mL+5PjG;KOs
zYmDyX^?6%Ix-2C4vSU0%^Lxi^?=_hnw!YU~8`%M~bw1whn^A90?{#g{Hf9&6hg17H
zlBbQ;qNKYo8c!mAxVC96tBuFqiKJUEn@x$^I{X9Xfut9o%k5dMM_kPw?(7}y?c6)+
z?@#vYyINa2XOH&2bN2F?kJ`)bxW9VY)^EM~aAW_r?jui_)nB_kS^dDbcXb<=O?2mP
z-Lm?z`%Ybb&qv;P^#iMS?r~pzWxe~@sr4U!<c;S%aLNr=pZ}TVb@$a%>(A7$jP6-|
zL)881@mnUodg7Kx?q54JbN|{-Z%=%x`@!(3i|^a8cI^IWZSS9URrX)duKe}CuD|la
zf3076`1P;eyZ?>5PW!@b)eVo|Z?C+*b4IiI^;e(Yn|<+>Uzx4F<@zhm*n8;uH;(o`
zy{i7i?7B5KT)Fu8LvJ5?Yxlwv?e?#p*0}qMp%Z?}ar>wE)%?j@xBkJwlTLVO^+_ju
z;_>pOpLot)?%z6bp33{|e_eL<10S8g?mH*XF8}ApyO)0Fso^vIH<$Ld{(N)q*&p_<
z-ul_I_B?Q8)76b9ueo~bIqP2Y*8g<Ymhb%C2LIy^4c+;`DL3wEJau{W^zYSrKmNn`
z@K2V#_LM808{2%v<G-@`r$2k~rib2gAo}UIU-^n>HttTo_VGjJp6g8W^*=cK)L;9`
znaSG!xvli^Po4aV2jBAG1us8;?Mq(%;JTN*{?6L^U-{SZ<)3~04I7_*XxCeQ{MiS_
z$G@|>_TV#bUHRjC_MY;Y$IHuCJX_sz;&-!`{`^z+r8ivv(yM;<=1TUbCubYKe?@KU
z$ZeZXdG)^-^P#(zr5AnmvqMk4Es1`-qPyxdZ{4xY|8&Qtp}fnh%?D2IzVv~Q_6|Py
z0k<l>U{_*(b>Lw3ch%mrH!rJhy<zLV>-Sz;zJ76YW4fnNYAhKpedoBfr5}HD!}jan
za`L{$4K|xQ<&b;!&UW?sQY~43$<FACKiOs9e({C&^mAf!&rOR*zIMx)ePsOf`quL<
zSo&*|YZ`0!WXa3EUMW3z=0(Ya8-~t*`FL~XNn@L~zJAYnwTC{r^Z5HOKJAqI9zXt+
z2bQfJf7#gTs~)`Pr1}G?tv~S7R^<b?RTrK3)bXP)x?y;9<=0Mm`%`DHi2nF<W1HvR
zHM}{kY+m-0M=9@bA3y&0_ij%A=jIhN>vmt&e&eI-+r}IW-xhoJa=ZW8%eU|Eb&qTH
z9^cVzeCW8V?^$Gfv)|jhZT9l)8uOuROm}(QYAma6-1?T~hwu26wmJVtd%JFTEpm@v
z+HH)zBxyW+dBv^gX0hoV&GlCdCZ|vDjeopy)5hyRvZ(pve|hDS2euuzqIcoyO^3hV
zsJB+W_CV`zFRVqcSe%w`I)264)n~7K*<YT0@#3^KxcHwA4}ALWt=De4;?QLeUA%br
zLw8?LzIuJOVdHLBe;|vtJ}}oj<*{c@h-N>zZs_E%m+i?PHyi%!omu0AFO6>f%1pKS
zKR&T`<7t)CDciN7Y(M!1?e}}9yslX(y{?(HYj3R_8c1L2?CctAXHSmZvscBN%zI6=
z^%XtWSh>uki%!`;_EHnMiw{q@iA^PU;$~Jm>$!P*qT&u(bN;ViV?OyhQ@(zKGuM|c
ztvAwYbWiJmIec1kO>b{~&D&qNcd)hWg(sJP>&7Kf>8kO2cE;J-(vBsIhfZC&I4!-V
zwQ}*^`;zg?A4>LYe`sVN`?b=xvGPcH=>uuk{x~)E*^y3l_FYlw<e^QAPTpzb^6o79
zvlonS{U7PNO<x&4Y1QnzHZsqd`DYk(Ke?OR!iJAuYgeynKfQfo&C}kr?JfRkb4z#F
z@9%y2cDwq^r<!g5JU<q>^z?JCIsRMBwXJB~*7A*JX6^EL=FWCGzO!qa2T#7bd3iEu
zZ$G@Iaoa_;zkbVArGdw<yms^_8@4o`9oo2i{fa%wGnJP4&c5nQ=OxvwxrMoy8TYNb
z-6I#W{dMh#YdjiVyZ#%lo?P5al5<~JNh%wziJn;Vx@dYs&)s(@oA2)0u>CLJRC@TP
z7j7~8?1r^(=Npz^8c2*?)mU-u@GDk!tLsPhy>3Ht+v=B4zB!feYyYf`#I57K?=F9K
z?zifP?iz15m@FP)HND0^xPRt0+k0e--TRms-M(Yy{_^s)YL<_-%;2GqUuf?5qaCNb
zzkOgdb8Xjr^yD?oN4be*%RblGa+Q0>#F}b!X1$t?z3pIg^w(=6Bjc-+k#gPaT2h+X
z)n480q^)f1Vs362Nz&`DNZj=KhZ~hjef^fvBsrA@&ETGTDY@arQL?TYEkD$C-R6eY
z>}k=&>cMoP#Cqkn(V@oeqtROJ=-pPGSdm>{KK(ZPiVc3v=@Y$Iu@KqPzIdML^m@wI
zd;_1GW0e%G<`Qi?kKO9)pGya0o3%$f2i)Ej>w2Ttm+f-PtnOGbG$L;4Jh&)ZyQezZ
z=$7I`tUww}$BkYqs~)JDp&s{llqN2G!GQ@g+$%+KrAM7#ZFVJx&8{wcxZBzLEuF#&
z;%dGS&@xZ%bKC&S&2U-8#v>E8_~I-Yu1r*iOG|zFqK!V@;v#d+*4AC^sG1yS&6<__
zSj8-=HoA>FZyt}R@W|{KKZO~UNxvFLlTGg37>%N&-HpaJAB@tMCsWa>l$jNTGv+s6
z%cc*j^}T63i#t8O%T*s9<vr!2>sU|ex9Ns$$Lo7;)8cK(voXAu^^(~UWsL)7Z<{r0
zyUAWwPe01?0D6xy&hIxnP00-(Z@a_g{VDy?#cV;ev-RwAMXuv2EHw}e#3kcmw|YLw
z9_Ho!$!J`Oy2Gx@a(vVbZg$+?Y<Z&dph*w&`q^wvl$d&pWnVPRuh%ndXwMoJ64`Le
ze61R>)~=eR%e94-&K*9-tY}`#`+qZOVX+gwi}r&rv5NBRjPb(<jdyhxV(yTIL)ROu
z!uYC#5|*1}ZOj*P_Igqevsz`1N36~b7A}Pvu28U@wQ@&!U5|H;C?5-)AZU(j43CT9
z1Z^ER+L(1{@T~i@deeC*2z3y(aC0^`)<@P^YuS^?Mtdes=Ir2{XgGtdVrN}MFZ_g^
zpGS5Ao0C2kmM|o4Ra6JXKlcQutbDEcUYFM{{|JPwV!xJpsbhf`BaTCW=U9k&VlI>&
zgy`6%{8$9tL65C7rUl!6=+ylJC>JnqV6JlP57~OkFLw#F`Db_uNF3pg7IcHp1qq@@
zbZT<s7IBk-4Kx?dXh$t4)|%L$EI>p#IF!gZFo^^|@W8?$gN^w-N5Nb*G_@jsFscP@
z8;8mfcqGFzOp}&E$p%9AAgn49mf!QnS#pRTUZ+VI@}sq==qXUfcrE0)JFNhC?1&BJ
zV7O3T?RA8WT3sSr$-ob~fC1#EG5n-`rF=I-bls(-g2_H0uA0Z*8orCRjv)#e=5yzr
z_QyB8`rFrCaPL#Qp1l8}k3aXTC%xy2|NfC{&i@0xoA$YjK6S;<|Li@_z3KlY>}}xW
zDyoF<bF1$(cRG`Br!xtY5V5A|iJcE(Cj<ylu(~seJt06R1PmWyCj<<UkC=skfT5-t
z^BW@K5CIXD9kRdzDj+MLyF!yimvw#iVO`~QWl`2u*WE|_T6cYSMR@+FZU=F9-`{&?
zx^C5}Q|FvI^<DSYy?1Ze^x$Q?Z~wCwzi`RxU-<1c*Zz9LcOJZE;q9Nj_LUP~`j2m3
z{H`xw`@PrC-G1w5);@B@OTWEr^j)`n=k=#|y?x)SYk&Cm|M>03lTQ5XRWCku)}KE1
z(j|{9KJ&L{jQ;6MYhQf&+$Vnh-m4ya<?1i*`l}~jI``HupK;&oukU{3XD|MC=PUpD
ztKFae)%(8u^oLKpMZb%7@sk_3-+J?RE`Id#YiIrJ|2%fa>rZW5`Sd5Rx_Ef~Z!Ul3
z1CLz$`p?eY{`8|~U4HlaFTeK>kK(&%kL`Zf9p63cj~D;#6EDcRWvtjOi&Ys2-%Y#0
zX|~ny>0r-FaiiErx8<#vWNiI%ZI#J)O)SsSKGfP$viTbZWz9E9G*p6kT3q~AA{#!>
zZW4ED*c-DmCry0XXEvy{9oU$alg&+AZ|5%TPtVv-w_@j|>4Hr%xG9<SA$P{WM2qcV
zJ0Ke#-^k73nG}3~Y&!GggUtaMHBG6S(^w*{a4m{<%sS4Z<p`(tZb?Vu=AfjmpK3cW
z@R3rQtlmsza%q9im%U5vbb-j?WZz8-p5Rbreh;E<NUO=4fZ%_n46)rB^xyo7u>1m>
zHxp^ZK^f|Qvz$;z75P8G@0d7^9{D|*7yj){K@_F8mt`J)n`B(S&qN8Z)W>L4bzFoN
z7`Y=upXy-DBZZNau4j8BrQLdNgjBRyZAoQ4U39~wev0&kM)xi-H*R!Kk#1imrP}H5
zp;sE=V-+)`<3(o#sqVov1-r-6)UC#aUc@hqcoeuO4uU!_bfbW1mNOCG)E+<WUnbH<
zXOwa5T{_Rr<N8R_WV_4Cxi0qXk$7ie)N5s3iFr7TELlM{H(tjjqn@e=LiSj0y^&R4
z)eu8Si#YB!Wxaxw_SwNsqHnWKBd7M5S_4^Yu+YDNXE9T0$(rIwt)G-h<jB!7%UXVv
zcQB|p#tMBRw)MrRf?b(-YDx1Da#48P9v#qN%9exFoRae!s|%n1T#8T9+V~JMNHCC-
zXmg)9s)O^9-X*g`m_+OXdQ;{K&P{3Aef$%e%wl5!Wo_!wN-L2E9W!{>#Tq5)r#}w)
zD-1Bz7OFtF6HeRpAs)Q~B-}G1(oaB;8?inh^Fa?v2KnHHI|)Ww+6C~U2r7^c1Q9Vn
z2YqK3g4a>TLl3d*YP8C+%Y#Ayb;>%8>j;vq7V-L~SH|eACX;8$w2hTGFJFlx*-s+<
z_Xy;Zd`$x3+is!XW(v@*P%V_XCTUsQ#%I$W-pr=8h(72%p+I{MsOtRNVhJI5$-MJi
zY&MXg0+kDBrjc%sVaHHyv_!M7g*dTOK~Ze1-D7wWCKZ$Cz%`u$`$c@HO2q)mApm=$
zhJ*-G4ftu<9hD_A&Y&V@w2+#RrZ*(gcg`3J&UoXqyg4PQ^DrD{KC)lHGL{m>_KxI;
z8i~x1<4Qi@Z9TY!N!5ED)3reZ6A0ECf@{b>qhicA;AmsWDl|c(U9yUeIkF{Al9^Pg
zNhN2W%u%5zYwB8--#(-`jboPPxim!lH-qjZjCkJGp_gVWkvee{kIQn29WaE8>q6g;
z9}*iSaw9Y}E33lMNk#&Bg%EcKEw-@i5l4gZU0{?(rzB__bkH`e$Xd;~NEr%?J@VNT
zub|iAVPYOLB}^4ca-kh41;D2pHT~E)ygiMK_6t#5+pNsQ-iaI89xy5f9am>(KE84>
zs>e}<eg+C_J+a1!C$Btp=SZ3X1+Q<5#~x}0v<OP7`6#pieDu>Gl1RY&?(A$pGuI?t
z84VHPX$uYS5EWiZ2{T&;M;U?xoQDkPlj*pTGO}vS#Kn}k<Bpy3p?WJBgYffZm8vx2
zw$M?jc6A(9clgyPkvQ=#P~ZbB;;8l(U7VCuDH@yJQ}GeL4D3M<`-<`$0rv(1Pg`uq
zN|sklsVtxO%BW>*hhP8`OpUcsR*AG>t0-&eRU&VVY+(Wcnmz-CJ!=y!Pvb;6c^*r1
zRJwwG4Au9_2v|{;Wm{B=P_MYq6&IVzT;Cq*$-J>d^C&!VKmEDL_~-CwO4cFVfeL}t
z%?MZVN~MiilUlqE%GlC&L45=fiUX{3tbNc*0UnHX2f^dv7b;|SBrnyl1AP#(z6dT}
zF`*#2dKV-rsiTy{TaA?o;r`1Tpx$_+t_!q_R7)%HX>U#I)UU#VPGZR)V2$P$B{Oj0
z5_Hl>DFXeoila~hM~_dFctVzX5u()9I@xMEAN*YheL{88V0QBLVC-#Wm`r6FIz@VZ
zD#5C#VxEv@nO*_5U;uEIi(yzSa*Z==P>NtT2ef2Z*+8jFgb<CG4%X1}{Wi_SkAntu
z(h67(l}*4brsJ`SP%BcOSZ8ZUadBEO5%IL&e2`SrPVa`kND0&&z?`<alT=#>6F=qa
z1dX>T{SW-CqdSu70sXWrb!(qEE)Km2PpFn7V#V1kBkadLLz)T7Hg*O=tiYV4l5U;E
z=b)s@wM;OdhQhaq(Sw@kA+}N`wWBQ&pi(9Tk?IM<44+CV?wFX8K%rqgCCbA&yag}P
zVF+pBr#uqpRiLJ8Nc;M35@@uevd*@$w#5yeEP3c`x?QbtK8A<Ueo6H*C2he{r1PMQ
zrXv+Ya;=16wP!f(Q$dHh^a2qHkeIhesC^tYfhm<CQ}{~8hhkdbl#e#*5i)u#{_k!h
zjD0;}9k0B^YY?oKsyn&dA_uK|&?g!3oE37<p>FCdN;Ria<LVvy9%vHQGE<z0nvkf7
zOlh#m7Ae(06B~zbl*K+@C2Snnil1<Z!07u`u@n{tr6re?iDqKhAbbFli5BaV$xXbo
z8=WhbB-%iv5XT$DO<55AydkWF_7d-i=UNj-5%I19lLmt@VR;Vy^jW5K-ORzp0P{9d
z*{Nl=A3f{b#hUaEo>&W;j+1yt_3(IHIM_8<ac%hP+jvbnON9Z9T2bBjyVUP=ETCXZ
z#;l_P<S}&`S^sQtM2pILRG|#Jx4+r>YUISM;G||9aRaoB1{Ns7*RnNNwXVdpjZHJV
zOxCoppA5utD~T-ohY}}MnK~6&bJ?33H;ld|0!|HY@z@zHM61uE9}VYCV3kbu4v?T{
z<}prFOT->q4sQm?hX+3euMTxqFMtlSoTvy4x)h2woft+QAF_ei<0u3g^6&5);=E=w
z=n;WA*k7wR9NXek%j!4$Lc9}Ok6W=moDev5GoUnp4K6af*X~6><s7Kd3ASd6fO;Lj
z>R9IY_*;~yLk!U>Fk|CjJ4tI%Tx_h4r-oe9AT7+Gh9E>&xfu6G>VxV<q6HYh22r8U
zB?kd24fUisA+D}I((}vCja+a+Ky<t!0FP`>)Ag`412Gt@=$Iflfa<IlX@*fJBv!{u
zt!qB$;!@U+WP1BRkE0%^2O$-#I@HxJJ8BOhr;;$d$^~4mOqbY1VB|n$Rj#5|vKsQ%
zSfNHb64fo<cF1w2Up8hy#eqfTN_wX}Y4n`3#LlR|6lUrnL-dF^A0k^@QiI1S9S**h
zm`H{tKc=fh(2Ns`*YxN&qM96p5zPxKG?W4HgpfnqRHUbmD@P)CIq=A!(b$mCDt%dN
zhJ&u7xVA=Fk}FjCsTVzUx!nbAcdfTVMHucld3C9H#vM%S$QQuyf;_L@n4eWocWkxD
z1h5dMP+yRg`7n>_3G<L+OXsHq3Xx{)_kbZSXrW!cPI9S1A}-S`BXo)&F4#5F(C;!s
zpQoVO0ikTd0x1OP8R*B^|F;K|IK`8?5ozzOwL*s}QfJkgNXt)S$mg5HP#3Ib2#02d
z!{R$rkqiZ28n;E93w0pi6i;y_N)9`FFynZzf-3C!1)vE|*~|<y*=nV05A@7T1MyHv
zDiY-$m=gKlJ4uwKw-#TQS}|JBoRMC9dU#&DIOn;(0nk#PEn!D|4<RLE%*vL1)`t=b
z84nQ}cH~0?(1@W#Eh}gjWOTO<i0f8)8Ow4RfqFBP321jaz&;PG0&8_FzW_edB<^DJ
z2<igmq^T*O=WydL_Ta_%;A>IBO?(kKr^=DoqKL-%)Q<ChEmcdEBFEJct1U?5XuUot
zV;oH)vXbYjX{*?;CR1Torw%u2i*j((PDv*%E^RKeyT(Y-;lwtGh+-e!>J3Jqw|W&v
za^jJ!%1PPnRc2Q6vr2PiK~mTtLJp0V^D}>fFdL-!e!MxjWNWz4uyxJ}RiM|@=-dU{
zB2o4=WiTD+#?gRQ8d<_!$Qo_G&w{le#x;@{4a0z%HC><OlJY(Xs(wUqI7N*pmKGQj
z;QwGP&?*z=TlLJ)(MZU(ryhmI6ZMcRf|I3nC_{yy!SAvY$y#NZWzUE;YD@*KM^UqD
zSk;6!Qd7E&0ZJT%aVv-nAuGl)Btg=pLMjy{G)@TU))|(9EEniW<s4y3#tF|_#}V}_
zF7@hj>snBfZef2?PseBA*o_Iv!)P3&q~dKjJ5ae+X@XqeRhw{xKdm@x)tdOpEDV$?
z3i(E3f|Z~@livVUbv@|<p(D^%J-KQ^{u^G?di{@a6`XBYDfxg62qo0)x@Pdv{VI{V
zB;rr2LS20GBdQ7M6hP^Gw~V(aE_CJwNtUo7p>{GQE?SR^nZ<3ugVSv&DF#^tlo+u1
zsO-iO)}z&3G+R6oqC!0HiBVth>m}=x@vQYao>|2yR$MZPJruNzqTr#qWZ?AKTX7n|
z;Fe1f0kvRjMZSr>)j2)Ta<Er$L+YxY2kUh#yEZD0`0zR$qICB+YYU;QyRpG;8mZxo
z?Hv5EYGQj8r*UDdkU;B+Bri>k@azC<wADbceYo~e2}{8TLkhY9V?U84zZceTfLhRn
zkj3_lTrlf!bB+@8j14+QMxk#EG=oBMq6w3;&`$<raE$f^{11yPKp9#KDq~0XbTr;M
z1Ub?LG7vhI1R!B4B}Pa?O=A)z#+3>94CBT!T}h3{N)Pl-w`v?7ASAt0(`zgw3qsur
zeT-EpZ0}fy6wPPIYb7I9cVvn*n#gOmh*bhj1TS`t)c<Bch{_4F6i-5hezOGk^-byz
zD5qDS<xP<R=mf%*)JRb}HA!YP6_`QT$nH{t;UT@|!Gxh{1l_`Bv)U5K!L{FYRWjPU
z1^sHOjc<irAAFh7p(-MiJX3p&(L^jJ0(AR~By6N)C`npcgqgk+x6jZ)lnpF<wZG<H
zq1A_@Pq(AbLXw3Xf(pqko;<&17<a6U;l~0EjD8;8%<2}O4eO+l5xklcu`RVDJd9og
zVXPhn9?@@zxCxpx+2fH59(sf+R8e=Da!@zwph94y9>P|`$x?`QmKJjFRXw*u%kmg1
zaR%L_2kjV`Br7!6<k#!N?BrTWtEA<klIr5=q-f{(gCJWAL=nNP!-6&pb={t#g();#
z&v=N3u#UDu3eW*U7JTL(aoH6&pu4V+gw1a+d3S><s&(Iq&t|#O(G06W186#KkA*nA
zo;8kEg;<AY)l(Iwt+ru6IVfgA7FDvzEPcKg>tR8+RwK&tL#*r9R6a|dm8nJmvDf$j
zl$8Se4PKUEwsp#8ieKupc~gkSiE=n&76r8IIUcLxu&PvKGZ*sW9N|0>NOY*qOE^84
zOkL4k*ax2HwV{i_AjApF;ZRht(<;!_Tdcz?BkE+lxN7V{muVu&%7iU_s`na0b^<Gd
zFVH&0VU$KsY*b2r0}3TE(&pm1N@NL-1Os_g4xrbArW#a?<EO|PY1n?#GEC~Qfyjc7
z6s-~?2TLtu?w<t?YOY?NRYqu3@{kRlHw0)(Wf%}a|0xGy>I|-e^)6ghNC{spo61{7
zI-=F?+<mkt(gm$y{}oh704?hv#&k28eR(_BnldNt8;opSm2x<N){w8vEEY~RMC%ox
zl(q5tq!WUHW`);suACS!sybjDrWg-e69AET9aeOSml;z}U8<KTYE-P!5h^)LI3T%d
z8Ecr^j!rLKU^s-{X(-c?P*p>`WeFJ9dvMv_gV!+Y81KV1?y^%dyD7tI1bAKNG{ItD
zK@IIm!2)!VVq91UWxDvxrtokOhB`x=?P`);i=BXosUsjvszkhlMKhL|27QkQp`djK
z&@q*YrTa=*wj3(yeAVm11=(DIJ|c|;iLOp*4V59pXoeho1?`E?p?ehRc8Djv7+o|&
z66v%YNVTuiBnn`P>~DsYp}qd&zYDxH9tnX&9lfa+i;A<tebCHi6G6NZSzVc?9XvXK
zI+ex3#CakJlS(3wBi_OU^*sauoQ!22@ZxG2-n!UnfjEtF<WgIi*8t2sRS=)$w~BU7
z$g<c_3hlIYs;tqGOl34InT%<KB|}6pDu-Ywr(;fOLQMoR)*@8)s(0|XEV&f04S>3B
zZEFoSswMV}K1+iQ!orOQxXAq!WPnQd>QT^Kh>flKJ;}>ejdsBX#?b}i4@F*r%vqHg
z!(SBgX{@rD<mX)`iwpfUj(Xss@lNM3S`WQ4^%MX_Z~8!33mz_l?ipa-Et~LKJtuN1
z<y^NZPi(oCFcNQ)_)Fw}fM-Hg5f6T<!(&F|eeIx>ol9HyHYt0|#vRXSoSvdX57>v;
zKT5)V7w7*{WL`4fsC7upw8_jt(;rXN8i-^<QnTx&$P2<6WzH8(gQjs4d(+SG@ORQz
z)wu(Ahx-xTYto5o%rxTM=a?srN<`1XI>yV!$-bgA#${+oR?&!PGWSR_X?yF1WLc{&
zy~m_eJdY%@g=)mZfYWG0QK1;8HP7qW>PfQf05|@MQ`!YvOT%^uF_A4SC?Q(Mi!_#b
zv&1ZP)YFx`Z4hOaJv)_yhZ{KsCB~+V>!~CQ65mXFtVG}P)wO>--ym{D4-c4*#LQvl
z=a<<UHWI!r@cgntHef1Lza|eoSv$`clhb3nYN13_gf%i%9hmzooAT_|(2BaL<iFXM
zCf~4C4!+3Nkv7#jEe;O&oM}+BRA`>?7+iLPPuDuqyIduQ;82$Twhw7y+-($wm@8YH
zqncn?sZLM`l6Tzqj?1Y%jnZ+SSs^_w3YGIhx@K$943azf1jf!#tNc(@$#2?EnQPVB
z1k32<@oKA2YC|1vT6U7&su-Eq=&O})p&wcAbwahJG|3aOg>hMTJwolCX?fmzIQJPb
z)rVwS)M#@Ot1qpy-Z<Wy1yV`s#`$<dF`nZj9_DK;g;lC%8t2MlbBBKpyK#Q$oz3xF
z|Co);7Q=KFYqsw?ytGqhI=tIWk`(%6=8kAdVRWH5OMaFe@VQ<_n9Y^FaRGy;MV+)z
zR~|38{5qbMEl$bu<EFIGle13o$P;tK#CWL{6`IKfl8jKc$M@L_%YGu&gGcUpDa=g@
z+?n#d3rB>0%5qrfOSbm1Y-;pLqmr65-6W-HJiF1#nac8KIe!($rKP4<&Rwe~#wL<-
zo0}>_m8EscX<llrjd@AhB1uZgb(I}AFE$aG;lNjV)<9g*ET($q<LN7yq{IpHl#;z8
zU4HRpy=NA;9=@sSi^CWGs%RH4PR?9b?maX8da-=*uZq>-cP677Rt%lIp<|aH)%43a
zi_v>lWuo`0&c5ofYaeItUA*Y*dz0R)JH(B&=T?6lAN7I9Z#aH?vwdr|X67FI%J_oO
z|2JN6VY5(Ny16iS_FtA4@EyD(M|Tv=u2xbk?j4s4zkS#6g*ysIEV0R1E5EkiUi_W?
zcH0g)t5{iZ)`qXO-+9z`+nfPPt}1S?6wW%}=MQgaFCSX5xUlo_1<6@k_RY8N**CxZ
zS|VpXIaE2TIeA3+)ONo7h2F|pn%@r|M}8-Y$2>T+_@rI47VQ2;f90ZAdlpQ0{b!di
zId<EoA1zyS$+Jg1aLw|=e|p018OL9`YsS@Y{pRrTms~cqaK_L3DyQyDE`0ZnBetJ-
z&Fxq1{?Gk~ZvW*yr`C6@+wsj`KDXo5$MYvF+L^y_+D`L>tA1Jd!L~2%sa$+nzViNK
z52>zt_@g@(J$~X<E0;W4T5<7=EvL-6amz&y?Op%w51IZozr6p#Qy*S9e8|5peEGD8
z?|<TymrK11pP0XS;m;Qxb?D`vn_jqk$q~o?=7ISi`s>f1u<;#>k2-eQ0|RGoU$}hp
z$khXtAH06dw*7MljvG3n=eXAv#rY?{Fue1Lk1jv=g=u|9XntQNzYl-zh(mvQ-{EgP
zV_;?ZjQ*A7%cf6jxj73)FFSG3C9S#JlBpvqmk-RXq?gTIdHOYTkAK^)o`q}HL<`pJ
z?7KR@BU!lQsynXSwd?k6vwyzu-K&1S<n1Tz?5n<$GiA#k&Tm^#%`aQ9qkUJ4-!{VU
z-<5A&w0zIb1uF{G%`5ZU)5-&-bnlGPrE_mAUAlDddU;6tb06Hl`J{(RLo*(pF>~P`
zEh!#({QOekAyY5>!-IV*fAI16sQHDX=KON+^dmlM`{wWS^G1#?95ZzE{l^?R^5F1b
zZBg7f@`#?<$IcxnKKaMTwElGLom(fTAG#v`*julhw}bCJ(9u5nAm#9d!9~T@gI8{v
zd)SrDb9*?%chcadc?(aupirNF$&C2QTh||Y*1Y_J(R0%aPdQ`YqBYIIg{^enf@Im;
znT?f4MC%4h+b`mIyT-#4{f&qE+`Qu8!g<v_Js0kr@r6az8UJFuVd0zq;CY7?mY#fA
z{<5{zJ#piSysa<W>()M0aLX3uTf6^xiPZc(XY@w-xs4}o+_~mQOQi2}`K0G_?W5DF
zJ?rC{OL|Vbb5YN>1&fAG{n3)@T30%B$<)+gJBMY-am6M1cO@tEl=t5dZ}f~^JMUS!
zaM2Hi`N&a+`1XPe`c4=eIsLT$bIv(z)kdBuYii!N6#6gTG9!PE+0@scJ9*m3WrGWA
zuaf5jgWK};c_)li3(?~0jQsQ?%u&(o{PqnGC99%``^>=P;I@I{yp?^`{7-Ak_B_r+
zuTe1hGjlzK9W#3NEUqofuNz&NU)O63E-CFzW>)g{=t{miKf1B8%`cJOckF2u{&YsE
zzOY@|urS|WU$AGrOwBN||KsJ8rVdS4zQ52v{7(gY_1*E3;#B!<$IaZ^^X?6M`?mY!
zu=#RB|ISr~Y1>!bc*IIC@3fL%F`g{yy*F8O#6?rdg3r^JJ^m9ba^e#V-1fqIca-P+
z<U67VE9$&QZ14wBJowF=d~oX;i7KfddQv!2Q0g1{d9}~{#3Uy%jIP~k?pi<CKb2cC
z8E@a-mPHqo=pXk>?Jdc;eaB!td_oe>zHl-zM}CdF(Y;g2)lu1Qzkc!Nxox>_ZGLL+
z_FgHSk@ziV-8X&5(JL!Qy`yS-&KB>^-g}ch;;mCQy>q`DK6PaCY^e+`xM@YTb|)|8
zoa&d#rnfKOvi_mgvN@9%o|?3q^&R<`vlD6M>-Q#S+;-HwQ>Nldm<VeAetj4D8#w-=
z9WvV3B)KZpm{T{6o7YP3I7{b=b!l#0|3qtx+)(`&+h-~}`*u9UOJHAa`_Zq-U1m;k
z%H8z0<CXc|FG?0lZgfaw<8^(lL4U(L7s?I!(wunJLKCmu!C*6x_@Q3YXNOAV=PEfr
zk@Wc^7bfFF$CVaTwp5ehoxCE*$z9Reg~zrJO>3XGczADa$R28z%97S8uCn>vRTFKq
zvt(=fv4IuIz~)MFb0eROUwP^dnZJl<4;PMA=FFRXa9~zCV)ltEg)=`dy}+b0o;hXu
zjw_jjNld(%$>pj}E<SC<lxL1GR+Vc~T)r<ZerI-k$R0D0>qHYZ|A}PPw6wRrgZbR#
zbxAb3D$bR1KDRUHYY+Ljek|v2*7U}!Mi^<`N0O%Nl}+{0y%p0NoAU~Hxw`M`IPsp>
zy)!wEU12P)vu4|1lJUY$iP<lRU9r~}b5rB<`lI~NroA`R%-3#kW=|XqjvaPkN#dcp
z<ky$R%*;k_vA5ZK54VgT=y$8rsD2)^7@h%Lz!{mo-r^i)kGZ5RZ)18O`FA=NbMZ{c
z%h8gLR~Fl1tL?Z>w^8)0m(m0A(Aw){O~)j&T}g@~J7Xu$B;My@*Tb|sInB9^^>H}G
zGQw|^@%lh*vYC%2*2Xod^UQ?g;_)VDo0~3*-E`{X@QU%yh(0SA@#CpSK3wgZemptg
zV`rWp?^qW{lmT%7Um93?J}=<x$u}f|BezN7lV5O$)b45(qWlM^51Gva(f(04viCL{
z#ZlZlJIe7|FkN4gdZ;&QkM=VEQ%L`Ql8rql;#nLKYgrxXy4y{lConKku1jhi6h$_j
zh~fQfx8o)qrgL6tT$%a(+SPIQ-4jrCbWZDYtJyR2O#8~v^twrxOnB~e>FIH~njNfW
z(y-hawxf>aJQMV=9At9s;E5Jwvpwaa#MZ2Z#~!hX@sS9N%EjK5owR6X5%=;^_Od#r
zfLyjnZPaQQRwO;XVp(q_QOnBp$`6Ru(KA0E`<D8gRR<b=y8j^j$P)rUSH0A#q^J=j
zUgH8yVo1Q5Ae8N>F>CyWi1S=Ue2@VTri@~wlSs>puB!<;uxvI)%wAPh%g;r|VyVq|
zVH+r7X#1!{8t87EXu+$FJS^jhAf>K7NuYA9Vt_iocJO(2M(`ATSY*Q)N<GAs$p|Eo
z*R(Y?j0J6-8psM4Wvh4c*bwk&3ZlV}2$xCH><5m)lf6zlvLV-+PfM%}=7qB2C(|V&
zJQmXXz$Wmgd~6(x{#1l+i(@Cvl*)G`4f@$6JFdb)AyON|Fzm1C9vc!p!H`6g@r{=+
z?Y>WTyepjf>3c8XN3Xr_(JM~;<R$OBd)FyXy|i}UqrdsWqaVKXmfi3B^3JoKe)W=l
zf42Q+$G-3BM_#-3ha1*DaM|`dZr%RJ^WS^lZ!fv@*E_%S)HRE4|L*p?mt6703zxqA
z%U6Hzr@Oa5{r~K~`|W3cdE?nj9{J7df4pnaQ}5aS*ikQj`SQ^vk8FSOo~wTI`g;~W
za@0w$Trv72;Rmkz+|%z_`EQq=^w_SG?tgvz9gpt*=clh-bR6LgCw=bUFZsk%XW#es
zGoL=@^-CYzIeP!@?VrBmyGJcK`{@r~di7%)UVL!Z!rSjS_u{v``1Hn0-|^VhFTQ@p
zRk#1)?ql>!&*xv|-o?|q7Jd4AyN{_3FXu^1%NdZCW*>_Wm|{LLMUH5sj8v0~OpXyV
zPd!<|^3HYM1AQUS@UY0Sj!ICGb=>v8gf?05ydZ;`lkT-b-?d>v8-vlChSr|M{UgE(
zwjsCKUe5n`N_m~W#X<@;k`+;{k0)Q^xS7Zdn-r300mX<kWKeGU%+g%3*C_{{PorS1
zaI!*q7J69E99prxW?Ad{iPTBVvhgruHNVf%8<+|9W{=P+l9e-_-v@273X{~Pt~W#c
z4=yCXgE#nTa{)|tQCG$NPoN|<t)Bk{*wOku_1@5fq4K|w{(lAaY{8!|&{)SWMaGC5
zr+3F1AXtG?HjajA#0EuiJZLgOwB|gPJDFhWts?6|PD+7@C@+@3eCh}YjSG5uYwwb}
zPv}1p8t3%6&ZZ;QWbfCsJ}BKZj<S_<OU3N)`azLCnjND^Bes@xxP@nIB}{|Ty2L!p
zI1M>Ytq0@q+NGu{$!1&XwfiQ*65k=+fwpd<(hER9+IXTQ;>b=XJbPu_ps~f8n9UIB
zOIMv%a}(8^=kQm{(l6Ecwvib0V8^5_>z!v`YibQVhJyAHt~Vxh?(E^PI+v&|);j6Q
z>hdI`2KC?hIJP%o5;QxWeW(sLpVwQBFjPE-z7=j4C5$85FOl~VwW5B*O!bPWntq&t
z73!&%*_@@zv{1I&mMw*PcXNHV)3Rkkfuo7hO9q@~OCca)?azs)2)vM2ObXt1Nyvu-
zt<|)lCX)@mFT0T-<k>}1Ck73P$@+Xp`EIbvd7Gu&NW-m-M5Dz7T39Ot7qkk3+CkrR
zsD%_X);f3)BJ~)jB!DxLwj?V*4SV)poEWu}cyEZNIl^E)to423ergsN$4~DAQX1G9
z`U*nah6CV-@L1ONQVKj&Q-YL_Dx!8`(nV1q){sWVVli&2LWxp;pg0J&*V1E=rla?k
z0hFMUlMiUUpcW&m4Vq|+)#u%~XnMnhn6M{IGxK1yp{Jw>Wk)jF4meH48-FCib+D9%
z<CvG|i{ibpct8cnN+XyFRJSJJ1I!4sEF(VeT6q|PG@Joq1COlGHmL(jge2$4wu`ts
z=2b3w!pAcyS3Ml<j-)B`!d@cvOrKsXL@_pV%-5v8!OU}7_|Q$^c-Br_6dZwKgBt}}
zYWm-KC}fUDr{iva7{V@SLjteU9&6Doia<KAN}!KwR(GI$6oVt06iz)_IV%{4sK6>h
zDW22;NUxXJJw$GSj+A)%I4Y;f@-XS}=p)fmwQ}G;Hj&w#d0nu)^1~Nq1wC~wFFrB`
z&Uj1jk``43L8_h^c;Qx<Xe6(34gjTBj~=K*2R!;lqX6i|fhk2=-5ieeDIllC%J~q*
zd*#F8idx~dIeAzlX_W*;D7}mavF3Qe9L)8!K9S6pZLAg!s$-NXyxIn|t>6{B8b!G$
zlf7`+UkBHs7>%DCQ)NP3m3Bz41q*okYL+U4q~ptD0TnZ)wnKQSM+#m=_9_7^GK)9_
zXN42cI5Dv_Nt4uAXpp8vgH^1ujHqiYCi$uXJe5$Pn<f)U*ir98gm)=5j!dbIhV+t9
z7DHmDLUimL&0I-6KdwFESlQ4%D{+p~K%hyZ@m&!aTWib|(|8M|N39%OueV}cpiH%V
zt3M`%RcTr`;&jYI-VXXp+cGSovDMy6pP9zr?%Id0+d7r0Sm-jCRQ<G{aZd9=AE1!g
zjHZd2w1RNMKQ#{X5*0D#fYXtgIu*M_AES(9!Zb~ZtK$#NRTALPgwYgL+T?|Q@1(Dk
zJ=dwXIYVz1he~fl^@wypIEjvq3u}%W;9+D;<-t=OXVDhXGQv-9WAop^YaFGR4n{R3
zc=XVJrR#^lX~MdQRb-oMg9NIg51cG@FCZZI=!e>jE(#sw$xyJqS3wYf;D0(EI%R$e
zPPK?Iqaq1;JPI{_lo2~(n%F5F1QY~U&%YBpv6L7)rB?Q#d|!A!k=%2!`Y4AAg=1S$
zSWnA|#LP||5tHKhfLosA{L_BZyPxAV7%qRWNT~<<10<(5_$s{nbaa-9bh9!NGg}p=
ze8=R@3F<qa)KE)un-!v-Qh6%%;p7Udit?bdE@H@!O=FeyYW;{z<Y-u2y}0}2Pk1#5
zsdHGJmEJxd--FJEvu!A$)SjF%PxA=qGwF4qWbkWOr>{k~ACoavQNi|rEby7Pq_@5?
z)UYrdI--ht-c|4OddE#XarJ~rea^}bDq45&fhroD%1KX0%^V7n1IkE{I&(RTHe`#N
zKG+?=;f_qhjUkdz)?r)}5Mwo4bOCTZ(s1$0ig@Cfx|1(AG8x4(2AxApl#ddN=j8*O
zccDIUPb;Eo8K*ihT}y7#&#}TC<gs4lbLYcyjHsx8a9~Pg@;O(KGIg9zm24q)iiDhh
zK?keDziO9fK=&I$p-Hq{xGTu0G&_ENpS7?ovK=4}kGHnu9R(IM$_+q1WCe!Yw&5aM
znmCSKz1ShA<E=>99n#jQaS6pr3M;cGK<Mclj!_n|bl*U9psFRA&cB&C5H;1tvaOF+
z5=~09nS_LI#%y)wK1;PpR$EhQKZ(ANyeR2UZfldBRweQJ-5mvO_H?zDQDw?DEnJOn
zSY&Q=HZ<80eLH6c5jPm|HTx=XtkLBdLN5G|pw+kr0ZU5PmO5%jt#~V~gB<iwK2E$A
z>ZE58hw4pPC043E{z@yW>GPd2yqVATmXbrn0b_PGk{6m8Es+a81K+?ut!ljp1rX^K
zaoKfT1DJ$nh^<5iN17k4MK;vPbQdCPDc~&cpx(e|e%-C8F-PhW+w7WM(Ah;^%^$$i
zmhg5%B9*)l8Ge*1&xdDZ0<WTasoN;0^bY-eS2VhVp<;zAuLMYm380K4Th0RNQm0W@
zAH%_r2cfB|Dk<O)>4NW|LzVS`VHfS>WsQQ)3s#_j^dGJu)B$2;7%-}CHtA8eK|j|e
zlEJL3UF4cd9)Wl2=|W^C@kLY0ERkFES!E|;xdfok1kfTo^W)S&s)z5_Z;}P@>Xw5y
zI4OeEfXc}Gs!=44_v!)Z)y{x+n_Y-InxqRp<cVP1%Jc|yPT%}OCKVOdYw+oU2L+x*
z@EhPN2|a6>luUg!(+O=<wFpqd4St#neT~&Q+*B4N;RQ27n{^J1=S(IU)*LH9%5>HC
z(D{=$5N*Y(N&&cn4`G$6Kx!VnRVPq+qoZa^T&93^>QgF*7s!&?NIF*FpxkIehM2B-
zNbPAU*26A{uzjr&O)0#pOA#&-q8yrru30;2K-=Zj7vS;1xRp1mCDefpQNIHNiew=I
z*)+=#PW!CV7*ye_cj|~~D@Gx*&X=?wqZ1WzU_2uk;MDOnRZT$BNW<Ao!4iry0@|QU
z(x%BmN}|MD)D!fuSinvkv;u-N<<u&ZN~1su#hMU6jHkljPjJgjU)3Kw957TZ<>f3P
zZ4sI>*{dwn&xq;O6J&6;c#H&8l5yAANPi||7hjhaW|P6<N}&+?bWCV9z?9E%vHZ04
z4$<FGHIWD}WhWhVRCB9xGFcBy@wwYW6dk}<*_KlsL#!9u=|(7rthpwts|yO3T*d^N
z;NiTeCo%pJ{pK-1lAy3f1t(HhJ=mq^QchanVxweqpsuW$?AMM$S?9&n@in;Z!Uf^R
zJ7MtEz#HH)AL$U(7K>cXZ%xa<rD@q~L<ZI~xP^z>M4VU$HbstJC8v(`Hv=Diy4-4*
z-d`{9QlSnf3Yg3YPGi7iz!ljFN~?Wkq+!iw?1|H*Vn9n3p@9uOT?WaDd75*230!Kf
z57TIdK)B?rey{5wIA!5f6i5qpMA-t-Sh$$pe+gF{mg6~f6i@=ta>mQ#imSp{Sm*oT
z4}Cflq+njBD0Otn_WM8>(Vh&s8Znt}!92u-Op3ubRtRMnM57@(>jc4Tg89nOg&Zh%
ze6~v)OeYR1orqC=L*6X+jx^=L9uz()%bQ4NhhW9PngLbvog{00*s$h<*}Zr#hh#dc
z7Kp>9R*)B}D4rOh;9|T1v{N%qgEi%hhe0#S(e3Gt7vr<?ReA>v7)Q&FtmTbJl$YK_
z&_ULc)-Z%Il<I<CS7IQYb6%^FDx`>d)-KzmA?TPlC>C()z)JIP#iJz|WLg|jg>xWZ
z1L=rGfsIN)hLjk!B=OA0NJh?lFyItO;m)ACPTF3xn0Nvl;o=hT3^WzZIoJ%AWfvdA
z=?#eRbu<S-yMXrU`p6HUiHLI=RDi~+V$`?Ld^C-64-y<6DR)CQQ=zW9D^RY%tCX}f
zy-N^TSZk0%(TmTNR^FQDNRfbxP0IxzJxVYKF=z`ekT{wPkdbp!%)vl0s#|6|E>6oh
z6qt7efwnrH->Po@)J`562hQ>Xd?xUBA20}58{FVHT-H9$SS8jFkn}FWt(>k=fOD}A
z7Mez&3*(t`hG5Lk=^G_XcT9-=R?qwybec6Mmkm}~iFOOt)kv#MZsw=0jgYEd*RIsU
z)Pw4`q8zYHLkTkQVi=hN!49x99r1xR>r9uCv{bUs<Z0^yLVCO)9l=jHT<sS;vZJ5~
zSidym1i8*1RK1W+byGIlU4rDFC8G8oFwyLT$htI7K!H(J<2(@~8cWW+$_^>2L8A~3
zwu2rF<mw<+k$`7rV5{0Y(EnzJ1evAqfkK;SsAdyUh)+yFqo>~24t{UL<#UIHOPBM(
zOa@$bek-JOIz|DRi#7r4!E}OFWCTU@-&q6$_8_fAHE5RGkk%352s3w?gdIoST<SX8
zKv;g67W7Y{TCg96CtzV5J4VA0#%b#2tqKLQQOS5ZUCy?-jNWF^Jk|pOKWzlAsNe~W
zypdMpn2M;YkL99J6ZbBDjvwHH13`p_2n^vI?GkSElNxqesVO1gpoAQVBC8kOdC?bJ
zDF?tgHIofT+3{w5lU_ZJLfWS{zoW6xw>c0<l4N@5aq%h8ouCar#}9VS2IfKRI0#Py
zP1Vh>+9}m``zxM{3x%W!z510z6<j!Atx^XFD`R}FJr;4HCl8#3Qi`M!tj>Bj&PHBM
z;gn3TBRC;m1FAUzW<`XgrjF#Sx^Pr*NRPa7Pa{nkXfh>~;lVn~hBF*|Nvz7p$$$?N
zK%wLop-yvx<9Q({f@!^U1A!OFHvqXMH2}Nj+O3h!hFeNg>JJKO`8Y~PD+AILVs-dn
zwK9jMsX=*}pMyV|so1Rb1^U&5XyhhKtVU8Ax&&=^Sqkgn=TsF$#62}n40JknLmRqs
zGQd7VJr%3@^2$L5h~*G)63!54QwV)CSFe116np&mY!Fx>-fEm4Js=(6U25yrXvYwh
zZLkkkl33$)1EAxSiu8uQj9ROFyz8%#38gW0bwEbE^=ksZbGqdNL{iHngo$a7L|%+E
zg6Y`0@=8K7&p25h!sojE2YsXJHAGy{fhm|tOJW5IKs#C>Y7S|xGSCWOo%-7n)%6;3
z7L!fpq1jf+zKZ55#Pn-_p!8R^g9^%9JB&E8+A4_%RVcDNokL78BnhICOz9CKj1z!S
zBPh{QvMGKI*{qUn>~Ud3yn=STicfRKMtDkU2F+fn9{QD%6R8J^?sEU<4=N%+L5KvB
z?Bdf0o)2NMTxj!Z1iYS$*x+KQ;=$IW*jSy_{GuT!%>*f2Jf=uZX|uFNE77=O8Xli^
zV;=V1T0=Di1@boTe#0-Z<j8Z57<M6xF0_oS3xY1-d<&Zf*~s%yD?cwR+2f9me}>_X
zAP~_H1Kd`{^|~_;u+r7)uLfo#nyVAn)73-KIel)*sqak?Qf6V->FS{zG`(ga<U&n`
zI$m)BU<<2BHM#F5a%|m!^n^1lx;YtA1*Ht9*e6ceWwvqnA}u0UaFnp`D(_U50?a(x
zI`zc?6WZ(7*aKAkfH*3JcA|GBY?ex0r{&j##!zE9GZHYX;X(uucdtq0EXaer5wBo<
zKu}mw=$Ep*cv>!uxFe<mzgXy;GS=fsA)#gqdL2U1)i|!u1nv%bwmZsF^gM|`5||^K
zc=Cu>lGR<m1*HgWUE!kmgL9vf4o6-6BO;h0#t`N3atW`a2|VFv5fx2==0by}?=y`s
z?yK6GGgk!}Ku5034B=ZqjIhehVLuO}Fap|u%50(eCjq@5-~!G=hEMZiloS3Kk3u{V
zs!*^GDYzj*yh8D(&_`D5=@=M~<yVx(rA<^-&-@g8a*j61iH@{Lk`#x-e#D6PYhw#}
za=eW3aHJGg@s%}|QQ4&TLywkn>byi7;~`gbq27(U_L9^UmUd>n9H)GGXHvV8VHuA4
z_a<qHyNp}wcNuP=^vo$Sn83QUHj3f~U#c-O=a8{;R~@;H^>STH#Ex$DTiK0ftF9n(
z);qeRXiLMPUAY;dY}$8-E65tlc<6Y0zmI3K25r_YcDT-J5hugsuWSaBXfkT_Q?c`s
zPu|_;TLW4Md!t0}cQ!H1Ge1t<NYRPAzBieTy*s6)5vs`s$~|uw?_<i9|I;XT<9N@P
zw^V2zponsf+qp)0TdT=NSy)9c!+VjIbMVX!q|LaPB>SZ$ckMVmcUn&}c%V5HS&_AL
zT+<D=b4I>mR~$JgxtOx7<>Z(lY4OM`<wr$gY0mU#bGpCISI~x5J8*guYM{jCN`zHS
zzTA_eBPE~t4O!O~$}<0V+DX#)kGrH|ljX>p(V-0Xa>j}Wyf(tRZyaPN7x{`sIZykr
ze3@pX*0iQT+TvHtu;h|@u2~w8o;<CyKEzpl*D3OvdFy1Lb&BM-6iRFR?MVOpxY6?-
z;cm;FEP?9jzB1=uv~TQ_LkhkDenXE8(EYw_;%Dep<rDQoIO=7KGko1hDeZ5zncVO3
z(UOmfStFAhCynWIzGTX|!h~%|alI%Qx${U<V}wk(*EhXZrww=LZ!4YyMil0=GIG~w
z4-<t{#$_vaR5)Hxaxy$I?%JtM7#ri#GSetFQU(zoo`d61F4wzsTPm(z4`odcV9nHR
z4BYd1+nw({`Z{r9Ib&=b^^qArz3^M6@UkV7td575-ggsrbFO#l<>bP)L_HtzNq>X!
zxt%5r-|k&1oup@s!ij$#Gm%f0Qe*Q}B8gfpZvMuxe^%lW{mDSNOrIf_kFB$PgzLw+
zYU20xeo)VZT#y6NsulL`n;5=hUv&O!y|*uGMYpF1_KgqU@$e19H$<P_zrXkJ(t*j@
z!(W}cd3edtv;#k0FzvvBeYf8AwSBjipIi`azjs0Jf%?8%zqD@O9p(GqKIgO_5BIM6
z&Wm%uG;;ggFFkO`^wXZ~x&E}DpH_eJ>t`2_ec(rjuD^fyE$gqGHaPd?!=<=)-}K}6
zjhuYuuKH-PwJIroZC}ra?zp+<Lpw%CsSu;Zugxw`|L(1eKeVDgdRC=2I`_}_^_=jH
z+2y0IIk|W4ic?3=`u@K6e)xrb1H+HXg=gJ6I(m5h`RR*y?dvPw6a8i3(doT~4c{DC
zG4lN7Wm)>EU7FwjLw;9x#;eyHFZs*Petz>cfABY3U)}KS%T^x#*&h{8TlcGY=hy$&
zMSu7F?Cqa=%U^GM_N6<1^6X0=f8gxTKKkR%XV+~1t8X5?^B-RrKI^9Uefy_-`+oG(
zkN@_99UuSg)+-OZ^zW7L_x<|*1LyqfMc1GGi;Mp1r60`7_dWiu``>r$2Nt~VShs)P
zuaE!uz#lCAT;H)DzOV1FUHP6T-!Wc3?uk1`c3p92->z#OeDBr2dHY4Xf3xL>(NkMq
zIdpgXsQ3JGe9j*{-ah8I73~v_dt%8&yI*;r=g_Zy{^%=Cxbf=uzk1JyK6HL{)`_nj
zfANB+2QMCanz(ONzkcM#S@Y(8WN_ZJUsq4R#6AD*9h%?Ad9U81)gM>>>~A&|f3b3M
z{$<6<^G<x|Q#)6_`1cPM_x<7H`F)2@eg2DytbP8y?Th?pZuyD-?D&#T|F5UF9e8%@
zmWMxi&dw)4IpeIqd&>(y`SX{4u=Oi9EN}hAXO~s{$2Q9MM}D#J`f2In&fMZfd#C?k
zV0O=wPc3+B@&3wNi}&qc_YW%`JpG+3t{<7X?D}=Zn`Te{;)<6qTEA>;`jxxKPTq0C
z#|Mu2WnuBkC)Zpw<LNc$M<@K?qNV@w&<A%O|I6veul!}t2~QRlpLpVp!!u5};mn1z
zKR@T%D{h|i2V0*%{nFPzwR-5Od)HM?yz!`c{qDzwzqzaW(SbXwg{{vIyi4S&WA)ri
z|05!|xaV?d|ECAi{(Y@xYr_T2mbv_@6}`7zH8{AZZ^1WS?5lm^qmABM{&ib#r*p|r
z{XZ|M9e#h|$j|Ovn|$`&JLR0qcedVg<nFt#zvr4ye&(*$KW`j)`5*H2I5+QY@tM<0
zOU^vyi%UL~dvx~xx4doR%cJvG_MUm%(TzinUS6-if0tXkW$xu}aL)OM9X6vKAM)2z
z1NFg)jp@wWdXIbjPc9x<xqtD%@#*4$C*pGd&86wXe`u#~{=mlR=bg9l<mC_aMZJqZ
zKQDjcN9M&R+_QDomj-8<FJ0MpRO#F0;iDUNv*zuBS4HlW6VkExgrR|7e49SG*xKMv
zJC>)@E?>E$`O&_=-1qp6Q-6E=&A<4YTw`?X$CuQm{rsmxtJ*8Sv3_4+)z{D8S)2Yo
z@^?~W^qb$_{TJW5taayM8(R0BA$uEN=RxvyM=t3<to=ZLy}kP@&o7_#a#THfG-n>}
zeYY7OJ^AQknzC!o`DSGB{Ea=gOr5iQy5Bf!=Hs)@pL=huc1*K(*%P;xk9d6R*8UZC
zYtQtlk=!@k@Pd}@8Qx~&74O(He8hw6s(lwfQk}l!mY(P^*}CMBx#jriZGGj^h0)O4
z7u%6@-px?`^I84!!&&mk%H@%p)n9&j=}q(LN9X^<vT3#W)1Tpt?LD%-c#rSzFGYVe
zxXl#$2kzPs#rb8|J#}QEz_jes->`+hIA8u~`bBoH*|~Q-I&aT)_4@o=A(aojb->;^
zKE3*nWACkgG$)@b&7D2zWxMP->rz>Ac=^8koSklXU%|*<_sRSjv6tzmrxUT+c;h+p
znS9^;TP6A1V@<T@yj3#!OkGZ2Iu@OJ6X$;?CD~XMj?VUv=G$K!{d1o-_SwVaEzzew
z9Ie0Q@><Q?^_z_x@qy!o#e&W83`bpVTyT0l?XPmwU>W&asrf7JAA7uCa?5=6v=wIK
z^UK>0PrGR7CLYPY?U`cy>R%4-KV+`^2h*NqYd3E2-#=yX(2X<8&+JLlzGtNWo|D#&
zM2lvXH~-Ns^OoJ&>3is}4s1=$+@AjS;1!(t*dj~#ZWO0rX3D2hGkl}*=9HfPdK^dp
zGJRm+-W$w3vrd+ik7G+Rxn*Z<Pp4UnkLKCFn{vIUr&}846Ry$I>gNVkfA3^{S<-0@
zxRd4jIkTg?m#&ZY+uCO43iobigr01S$o?UTCVEe5Uwm3z9Ibl>Fmq0aMf&FYjk8A9
z-cUckm~WqdT0VEd==`x$Mz<dJ?p*t=o9laeUHz+(tJiXk=Bl18H8b69kV6`7&9rUn
z&zp9kJ5u`U^J?d87#OQHN21;hQDj%0F0FblYBt{2>l#P!rq9Dqa;v6At<nD4ma_+<
zW9kEA!*$m$n>H*RSUXT-U$Ec0)lpe%mYY?Vs4cek)%H@C$}vv-(X}{lTr_4~{Z8w0
z{!vbUSCbwo$)R??TN52=`L<9izO&@q%PU>@j!*t^N^idvcTX#7J2Pl%I)!2|$98wD
zt(i}r!cDZ{G?{&fDVAEsjyYG3q~=UqOL%<u{i7oHFg=Vb<+^d}Bwl^84E2m2u!SDC
z%Gs!|(URHB9$?4M#v5uKIU;gyUQN~;<_%|wC49`5fyl1ygJ?s&D#caS9mcF-l`s#`
zRZlH)A7P#`Udp*1W8H|eVuo}HKGU7TT*gEtw~C*5vmpnM;b@tZ{oC9cF|F0LNt<_%
zO~nzF;Y(i>7Kl;r^$(A_v1Kh54LrQ8cS!&}^OIOGBIHuDf1BR@Vt&gOcaQY=c+k-^
zbEcb<bu!KB#+EOnn+i1uqJD4mAWkmoAD47mot1{^W$kS$#R-XoQ$+n8;k^&x{<>#1
zliplMaTvN@=Bo#!pF>osFCi6j2VSR}sn4@V&!m@q6ZD7@k83a_s`g}B*Q3@xDSFO;
z#GX`amDQNn>uVkM#7-KQBLKp2ky$^4CqQ!I$*P|D0jgeIBMuZl*#i@$0fhntI)Y7@
z*yB3I19^3nh#w@LKU@Qa#iOW9hFT#YJh|fM;M2xcP#xkKI4w;O;Ym<EJb@SV2s(mQ
za%DJ_Nerp~JVRM%vgf=#a=fz4&h)hLFbCEYy2@0mi0Y@{5VT4?D)J!8D<Wg6X#HUa
z&1ZO}y|M~CgxxQ(#AuugcAze3!YF+XTM}C%=rl8c+DSdoL}^_*noo=xD}NxfGoB<z
zyj5+8_xd$sRn2wPV~wDUY^GnJ>E=^<@7AE@r}{;5;ZI*W<vYJR?F;hl?cvPNb3gmm
zB~QM3_I*#iwEdQgzxVnTjh~)-_3bac_~2{5{mr*7`rp6Z@ZF!Cv+|Bt|N6I|zx+3!
zeC=niZ1~=5FRc9J>!&`l_@#e->7v(PKZ9@bT>FRL{mvu9zj@_X7hn5tXY-w(KYjXp
zmpn53;wzV(`P#Q$C;T6ey>I(tCw%Xf%T9j%rQM%+>f9$@zxI+xj=A=gU1vW1t*bxz
z@9%r!v1_+K^5JV=x#G;%Ub^bBe}C<Sr>}VXF@$%1_^DTSKla*H7awy4XMV2z;TiA!
z&&#&o`r0LLJLd8y-uvNeU;l&ey>`u#TVK88?#q7t%C|oJvvA(%5=>jvGcdn6oHIZF
zv}@7gzh5<QKP{6#>5MpInw_-ZJMvs#GvYBZiGS5B@u~!w=xb`P(TXo~k`$h0wfdaR
zkGLa0#*^S<KU#z3zEeKbH0<^Bc+_vLlYTd1dyBNC-sj{kYwA6RG`?EyJ#5p~$hv0#
z;!SCftX;n9kgwaQ6c4W7$p?9Eb4%sMb=7{pJA33pmmcRGokLuW%t-Z+xKUldWi(x2
zR`(C*<MJWwH6L;r3%;q<>FIHW&Y}9wXp0@_=PPBlev~+~t-PkR<Ba~{qv$8H@AzE*
z0V>!1<xr^<N7KnJZ+1Na7Z9Q0247YWyA_H0^*ivHmy6AOzvuQ4@^2FNdyyLG#{C}4
z|3>uxgP_*_SAd_MEy%Ca2<<FF_d@k|+9DKOsh&%{q#TE>5bTGh%yln?&GM1Oqx07L
zXh0w7&632%8r>`4F?-KEET7f}V8uw{t&4jY1D0*o#@33T2Mtez>YYaH(sW#S;8k7v
z!P7lURdMNzYSt7J8B==Q)sD0qqhsd80>_-wRoc#FGHv<lU_rM=WG%A8%@C*-_Zl#s
zydVSMZ5?f=9!XiqOEl~{x>Z=x+rgG0iAPD&*oF8ucQ?|$$UDdAGsw+W-qtnqO6p0h
zV<!Tt#(8-AXs{loV>~;Zrx;_ojy-?p7(c{p%qb^2`_2M3je?(>KiZi^bFJfhf2KEC
zpXxqaf7I{DD!^cGZl;HdI`~~OVj}V#y4HlN6}^L4PqVT+^<K@`0@-Z2*`<Y8zzwuQ
zb{WkxNb)5y;;c)BQ2?de;EksplSI6lReZb0WL1p|JUj{5G>PDGgLQ$OC1OAvf245Z
z5k|r1WVZ7?2IV<`r*@IpyLN<lLpc%z>TRjl7<=h@9XzaO^v6SF)=g6vs@5pwCY2o^
zY=j3~Qss_4>L6|3NES&ttGXEH@L1(z;bx?!0tXz9ngew22n>nk4k`ACk^v9aDBpJY
zpKy2q9x5^D2Wh)P2frg&uPZGHvRfh!LQI_Ag{0~LiBM_65MW;$wGoIZ>5i~oVvH5`
zwnk>BmP3rhQ1`-fH|jylSC}IWg;R<|>24eCOLOA!X}k1(0d<Um8B>!u5D^ws`=NXt
zBGGfl_(|t+)fZG4s6wh?Yh-$c)s0_#bvrN_Q-PFzzOlFpY($A70WXudjvHtdu8KmD
zP$J6Es~=O~2aL8mzmGHlU~lki<FSmvF(I9YFiG(GNtb*^g{$$(S7&A_)>(4W6*TF<
zB^8qPDk1q$`E08SY>^BdY9*1LQx9s5A*aq81+*&wJdq?euFJCHhg82H+)9f!i4FDH
zU|feyvS;WtZz?C2aV;~1=o3cIfFVGHTE7xP&T;XI(S`<(79E|~c8y(m$5^A0dM4zb
z&d2+>mh(+&7Jyg%O<HPw6F={TLZl0M^IWs+(`g9r{t@jsR6=kp%Gk(dr>7WBJy>s1
zD~%TLG$0exII#CLFv@NgQ9)%CRsAE2gN9g}y2?(U^VxkC2VP~t+7l}|k?Z6(6Is|R
zdCFa@IJFuO=}>bZP&G-R&tW=!{?!qTC7P64P?nI7aozw+XQ*Zsiw$Uj#Cv5Ck*bOP
zRB_^K^VBmbBOYnky~n4~W+&2+#Ski3em(2~Q@<KIIkgnXY7D5k(k2E&>Qat3M-7(a
zbW|BT4vND3IhUnI4>TCVwlR3r4P`~*U>#iNAm<0UQ>CFIYm0rzv!W~fRQc>XKc`<I
zLAKhh6R-#)nez6y)EZu2NC$!0y*Rywa!RWjtI(ItNc}owd-{cdR3|%X2Ok5P5+XJE
zc|#8+=_;Mp+UXcFbf`nNLu0t2WSb0XSea>5B-T>t*r^CA@?0ntf&3a~b6|W(n}Y%l
z9#UY6_NQ$S&^v+FLl@D;v;{K!IjITXZ44j!n}WZhm3OQOOe4rvuVOu}<L5_0Y&Q;!
z2X96A=LDF+g+IAz!$`B_&_~9Ha44*=YSclXyeF#N0O_<#1YDC}1h4E-V#UBa)|Eg2
ztq}p>AIth+c2&lnV<nOi%F%~tZND3~;+-J8jFKdK*e2G);zl-$-V5f4Un)~ro7(Sr
zA1l?jT(G3!5dr68X{apfviO^+5GbWVA52752gR_rKnD99sSop>SXC0F^}?+#{B^1M
z6vNm2TL{6ZF51B)UdAA!l!NWDk|daD$Rx#@#+8cHpE0EKbtu(b(lR0#p%kTjCWlfx
zoz=ZHz51LbT`K1=z}KOT5gtz569%_VGXR#X+J5Q~e)?=r?l?5d8&x#2z(SH|7}PR8
z?(;nztnLKbCdA>hU-b68gv6C>{G8UP8B%hV_MzQ}l}?^P1oOE8lq^#!S|2;;Du=7X
z`KW@l809sPJWm?#%W-xe7~<#nTwfq#@`xQs>S70>ep1nK_M+d)%@%9}8IX^S;z<5j
zFY>o%pk9B{Vi2>uIJIwr2)7vy)Fm1$(2@x$xQOh_GJ+FjoP@W%2q+)tP?zjUZ6F!f
zu3^2=G%RpL#|?+gZV^udo1^HlI@1B82~A2LWruoNLVl&pK`&BJR5_C?^1Kwd==+*Z
zCnmH}5lgh(l(Pg@&={zrM&5#&gS-lT8}o04zl(dIlw>^xJVk}zqt0SV4lOVe8K)Y>
z_W7J_b97PklS5{;;av!^bJAO*y^}WfZ80NU(+aPBQ5!Pvv&pwnLZXMV&d)Webk2D&
z`cDjG64&MXV`C-pTM0C%4|(x?Hx(7-fW~`~=WPYeY#cELPGL;<+=#vcGj_SaN><cY
zh}i*4eTFTzBtj2ajTGiVEoOv#Ph^}&c`YPr^p=4@Bb_yNNIk$92GFaf^7y;`dv}gQ
zRuy~{Nh$c$iArKnO#cH|_=fZ_uO}uv0O2)8@#<KjIY@(Y3QUr4JL(N0-<aZfA5f;H
zH1zW9H*{r0vClLo1A%EEv{^UXWs*r#S=y)4yXdHd?dS?rZfMh7=>u?S8QCv1w{D)T
zM${%~+Un7xjtV5s(uYtm5MixkRx!G6(RSssfV%QEnq+1X(+N}<21snwGX{Ca-zo}S
z^ueZ7tqYM2Y_#m&wN=Ci$uafNGJRpum5c<<G@%O4z|c{vZyZyHp)}SqRl9qwOz4_X
zX1ueI@0JZBdG)8Y5NG`XUFeyrl#D?FL`|+)dd5ptP+}6XB2eu#m=6OGl%Yz{lLE>h
zz$7kJhdo~f5<)~lH1S(*eVeR&eTWtF9B5if)Y5QHrCNkV77z7T585B4-i*K3i_`2`
zr#L|0ih<}%I>{po5*mlA+_DHK)y<jLt2*EV;Bm4hc%4|rsS)8qZ&oD&4~db63$LJd
z68LIZxx?S^6iF48<<UdIkhcs#xX1-&Ahc}%JGil_fW$)KbSoFD=Bfv*HF`k;!<vE*
zu8QX$$kz9v7qP+00h?q;lY@Uq)6gD5(^L{(t*H^AYd{njoSJ5me;t2VgyHGJo3iR%
z7pJNMF1U26-LO|ZJ*qlloX(r*x1q_z;ZX?YqQ)Z2Sw*PO{|*(k0)t99NU@9_+W5T$
zQ3o>m*b!pOEQCDK+V}%MZSV}1um+n&cdwI9JvAB#7t4k=>XIh*O~x5eze|C)jj;kw
z+yhfQ#CM7YY{(FggJ?iQ3PCc%NYq9qywNF<whvvM<`_0U?hr<><r07g4A^e(*ev81
zpi0&#9CRo{L{<`T<Gh^AhfuBB5|3{(=uroiHG0GFszV@oR~@>lJ8=ZY_|>G<@v1Zk
z&qXI_FeV&n*k~f<?{Gc5BU%*Dq5G!NE0vPF5D%Gh;-@w<4rW0p7)3aKkQ=>XTYa1^
zc!QJi(5I_{_=YggQ3hh1Y>qRPo{^l$kTBZo8b%jdL+pRBkcq<b&nbIsW$<W9b-6hB
z03j!;9uQfiD22n1`r%B^`kV3OTpl-AX0v*1H--9Xs$?#9!7C<Qs#yTKY#Cb(^ftq0
zgHd=jMaCwiVd|NTL9h<#-eSj$nAu+jEv8l&j({@`8W$|eP+_yW$h1yLV}@WZP>}(v
z9;3azM3xLAh<}k1zl=(hk1<+8VISWUlhFi1C8MWSnqV1_1{C3}JXE4Z5UG_uyxCmi
zx=MF18kLlA96wE1$5mt?v|+<Q18?eN9eg3|GRpFuXPA#H5&RB<mXe2q&~d_%c18gj
ztpz~Ih6~QYPA4cda;G+7usN?oD%T}AKfV!%GQf@69@na)KWIGNoccUJ8yXASAzCTv
zE1@G!qx+o2%^<Gp$D1*&BW%1x|Ch0Mfs?DK693P=eY<me(lfa;OomAqpr+GFCLz%Q
z1EOZJy3@hV188CluYe63H9o-Tx~@MTY)xkfL(J+VhKL&3CL#t!jVuO4gieeY-RNc!
zL0JgV^|?N9U1a^KB){*e+hN`P{r~^Z|IGBgRi{p!I(4e*RNZ>qt3sXtB~GoH_@?4W
zlPNWL>s>{NsnQ<k*A!e()h>mXu{rOb<f<mCqv3N2G}#k%ko+oDgie4lEiYtrVa+E)
zW3|#IKo_V8^5B$HU>hmJHdf*Ucv(yMbiB$9De5F0+LT#7TT@!cPr+&1g2cQ1orxqS
zr8{6X5+%e1`8>Kq46-9ko0mI5m+GkPnWZ#t7<(}rcUXirw*IkzaGJ2PvJR~Hb0E)s
z0&(kjjAA-~Xt+9Oh-h7!y07=%r9`Ss9b%mTrAKE#$9{LTrHOg8^H(}Or36gMgHUDV
z0f(=Ani@`j^_law332A9C|b~@gf-7dUlP*6dVd<XgVHRBFF!?SCQsA?S0Gsp^of_T
zq^V#Q6u^iLyRKm;xEpaApm0zt7I8JY4Xln+p|n1yHq}+imbZQ5i0Ch=J=Qk?B1KNr
zPk+_nt$b2$dN+FU@r}MQNUbrI*Ltk&bS$Zk+a2ju%)poBC#vdF#YLf|?iw6qMbil=
zKF;Ie0v7pvIb4xAVsP<b^=h16b-Ew$aYLhQcjGOIHQq#$CP;p1za;rQ8cYX58iWX%
zD8H@)8dvR0l;Us$(bV+ruY?nc;LR$~p96gCfBBW=e*w?NA*|6!2P}6@N&*9~&<Xu)
zyOXydXi8cGbo?Z-`ZQ5x>Bt6F-GkzFwg<28dK`Wg2|p%BhWY6SXJ3%giPa}9&V3T1
z&@rbu6(ukrIsgNg#-b5=o_5j)X=xcvfVrDg9&Q{(?%vJ4<in7N_oMJc-f17ctW&c?
zZ0G-#sRCV_`mGMJfK)jSmk;;PX#{{c(SdZx@?ixcB?PQbwyCjwkCxUc@uWIW?7Y)+
zgcfSRABFNRoE|i1X;*-QxYoz#9@>-@XiccrY3rJo0$R5)<Hu8r2M3y;_Lr0kyctlc
z(}U%zdGuXx>W*Ql{W~TiqL~XMobmA!XJYXXfx=1^qdp*ucSKQE*{aF4ipEJ@00liU
z%6g?it)%syfI!B5u$NVfB(lU+dS_42_<L%2AoINZt=1)manoUuC4OQCIs#8vDCHy*
z@FA}!RAH4sCC7GoR{FjxCmE9UNFRnvLO3hRi{-e7Cvv1{*7-CVpdAo9SfFNunXvT*
zerlXL5GW6$?9{<6uTO&=a9A)+kRTHTTJMcJ5vF%k*YR`r@x^dUU4&D!fPmshnil{8
ztmg0pE-eZtq4g*YCe(*FQyNZBSyd3}od{%iF=9K&_~{M%!;hrtI-9uK{Pb0CB%g{Q
z#;Uonitm6*p|<xX?$+bf4k}K)I6K*MEwtc#InLOk1WMt-z=En3S?|-b2wY%Q)YvKm
zY^RdCDVh|*(IlN>ai}obk!pzLCnmI99aNswQRYn*08SN3TQiR@O*<0P>4bg9sd3cr
zlpkR>rCj17jE>bvMjMwO2UTha<|9C_I!zg=&1)(p5TB4sJ=W@2ItpoC9ZO6Du6eP^
zgcm1r>QFuBJ!d1~I9_ek)`v`nkdo#JwK?x<N1&=oF&TP(xGX4f+?81EvA2*m^!2og
zkvze~TF(+X59}23BpSB^SXhC^;_amSUvCuh{cbvD)o{a4fh<O8Ip22_uY#6o3UOdk
zZg}}FhcCm<OBY|jYY;ysFrB8YZWuUj25BsJMZW+wHCmcuAdROtOPoTA^mxM@DomJz
zC-4Pxt3e%J&JqV8o4x|O|DH<2KRt0?10IGTjpg`t01Kf#A!2m$YCMgK<&aj>)E)u$
zou1F6sdb{ia0{q@zOosQ@-eV)@Ua~lMfnc4<3Dl3CRug+^r1(Z6r51xURbWa6vIw@
zzXYJQ0nn>~H#Dh)O^+5m(=+W-b!%+McBjiE%S)We1uQS_wG>q!TN$`#;1k)FbocSL
z)Ru7~GhAM)2K!S(GZIf_(TItOSoSCT;;<QnZJTr@jW_}oHt&{<BnNr^>EgW>)|W#=
zCi0bpN#@vP5h-lbj>32_Fp=x(ihD`!;wj`c7n(qFCbVS~7(HrbSA3KFkdEP+Otm5{
z$=JN(d6A8X&cOkB#91C>3R(8aoX_I53EP?5!d~WmZD^&u9K#auHnC9og*Vt4EdD~D
z?sc=^ge|ZkqiSA=%NVUKb)NIsKf!@c7up$Cji!VXR?ez9QaFG&A1$x39va(X#W|D-
zsWc*Ed$=FqxFlL)uZ@)rIU8J1VtFbE>9-=+Bxmg@s8+%;Na>20XhBRZk47$%8)OMP
zCrvHj2vx*e+7A%eujekI)WRH>vV+w6ik^Gr0g-jRF57Dt@Fi+S3B$2$j$IB4U)H(|
zQxQ4CvhZT^g-V%hhqq^^hUYpCvp__jS|2V5=Ub=@c{I7QE98V#vp9(!@>0E2^5OVk
z*c_!Zb$K?^)?}c-%Ysc9+H_X1XA?6LO>>KkRJ4B{%pgdisGWEwld)&_GDRQD4~rAz
zt(VlJc$XE~B@=<otU`}*E<DrbyToBtt#!!^UK<rj%ekPE*p)4p@XEX>aLox6dU01o
zSz(DOmZWPP<sT+Aj5s$lZiZdOxLnRrw`^f!c#uYFs%<nz+3xO=F;)}ivuA<jdistq
z2qzpm<bCv(rp|hhDne@e!@gLLGJjCbJF8r1X!X8~L7fIxK{TF4;7GO{g5HuW<q_}8
z+BS;Jvz3jKW@Ri>r66LdiV_F4NwH&vkeyv&u#7jE2P#u8CtY)bH=^<>YOvfm?L3xw
znO)J8U}e-OP~@W%5-dk$XB`UN-YBnULSFHxidhT4x%WW+qkFe>_t(A=%DGR6`*$4b
ze&U`j-KZ{%7sbo>Pu^O7Y}@$K!Fm5w*)#j8Gxqo0YOYGQM-RU4VAtKzw@#_|eL!B{
zx5?gB`qqk%Mpx$R-|3U;wp)`;=CV_69sgQTKlwne%I@6H-M%!xV{*#yJ2pNs=jciM
zbKjht5`19C=Vq^~JyC2de<IwROc_3Z;ErIy1($?o<rU%by@l+<J8sX8aQ<MVwxYOy
z$KK)n+mDs*zhGH$<l2kE%J!XE``8Df`Gq%U&RrRuRC#o7fBA|1{cn!e^}Z?lv&^c?
zZ;iJ1ALy1vho)(MFZ_nc<%<sF`(Lzj>g4s`3U9rBW$uwV4`&}e=aTH<>D!kaIeX^?
zJMP((|L8qCYlC}Nu2^->foVUvWYe9`t-0vVy-U~TuYb+X?&nVXr>W1KcF`%1&Ur)m
zu{l2tu6otdsYf2Za_Wv<-v}NpUXXd$roYR+^2Wc*KD2jf{!ath_}P<Qo4a@0$#Wmt
zxM}wBjpvsR?f7Hxs~r!`{(SP`?DKt(XJ7o%zp-;)`qFZ3$K%<B+n&xmbIROlzc_tv
z_s@Ec4S%-h*O@nG-#zy|!FhAvwP5X(YZqJ<zGC1F*>??0i{|&AH86ks-6zk_{iOGd
z5A2%0{`5agf7z7hP97*7qIn;fs`<U<CLXs=>+eby^>=N*YUPyeR~-r;Jtr3)p0g=@
zG`nTm;p~>oW2No2?e~la+s}GD+Wv`4s^_n{N>-o!ZCO0~NjY!n>iF5yUKKn$@b%2I
zb8gK1XwIva4BdD^Jam4QHxbr@?Ys8LE1KEt^#f7#z(5rLY2b$Z&D$=S_3Ve%WEO9{
zP~Nri+nEb)JvMjcz;AO4k|VM>dAc~~<hKXKll~@HIB>cYcAOsFb;aCZ_Z4$9clLZf
zysPK)W`6de=;hP@BYIisaPXFqN3-YlZHnd%Ov#)<Ue8F*I_ZtMJEo72=lqnnPZ>P<
z?U`iDT3W@oLp>LB_io;7_#ofQ+cOsKXdTKVcU8MrkM}Q4ez$$f!1ELNCw9iu_VhoJ
zm+<0zSd69)+#Xfy<I##uU&;+{x-&DpXVJ%^>KvP#vwF#ld-{9whi|BczhX7wNcjGE
zDBK+9&Jp>C8>^*758n{H<Ho-WK3`m$zjJcsY&Uj8cE1}7_H4A-S*P8cyDPa_?wZ^h
zY@WO<`}6U)hYKF-9e(j6PX(ocwVA6=y<yH>-I3hYeOdNrxBpdiS@f0M)uoSTiX$J-
zm{YgUjkm4Onum))@!?{2MzjFCekj(wojD(qu<gg$9lN&3);$NZ)3;RP?RQo415b@#
zkbKu=A03k5k)cAI>#I(UGX2$LynjmH9fc{;ZEKcAUpP75(|@DfH~z5P)1T{Gw0cdZ
z9#yCQCc8SbHatIG8-87?bCybOPIS^=?^qd~{ct3o4YTnx#ntgwWlJ;`Y{~X+%npy<
z__bhRa@CZD$rItS$yb}M$tk%PuUZu>ST$gVPdiyk18Xv$?VghRY<J(3pUYX<-SYO}
znnrJMHT$WqzHA_D%$OpXO3{@ov!)E%;q0KC8T`_SEWQRav~3;vYc)f2-}$c8THduN
zPq|92a_+*Oi-#6Zd3ArGr^%-qE}W3z%O#%o&tZOfb7psC$Ei`*kL=2>?)J*Khp}h4
zAP6iU9QXuw{G6d`q1`;SyS-|t`xmQDp8D(D71PT370axfW;0>8R5nkEmN!?&r)&!3
z3dt|4<@4qF`Du3kEz4^`-;!ZlIo}kM3#XcBIZLl>fXz?I%l2<)WbC5clH0cAgVCGv
zOTx{w!_4O4;HEor!Opqa;Nx$ZTb_8!+>7E|@aFG@Q#5}+_y@*FgL8tZy=Me1Y1P8Q
z?rPr8XOTlTNW8k=L>EVFieQX>Nb+4X99ts8xaz{f%6s}lbEB*>J#uMOa5rh67iM_3
zM=?pVd#Af_f7e8~Z`+`Jvu|d+x$FIGsNHON2}W6(mB?~Fwu^plChItZ@ukbB1{1Y;
zH$}_lX_rKwEV;>9!%10Y@lh2@AP7EQ2!j4X805djVBuR`m3t25%Y7d#2I05ohH^9)
z_TSDIaORn6ykPDMw<%Z=H2s;LYwpwqi3Q=*{)VvcBHLy1*_k8sVT`aHqgpzoIOI7a
z+!J@_;(R<dm^Wkh@hryXH5;GAIicS9vnG=Hm66`K91nKst8&Y%C$Za7^4)ZcJXU4+
zKwuaL(=wZR;Fz#oO(!eH@<A=5a+8GqGHg~^qGK@5)zD$ax=hRVrlb-aOq#(#=6-nZ
zgtgG-8GrF!YiqkQE-;y`E{u9z5VCtAaFwt!!DG!$`@*nQHNhmhndEWLSqU8dH~qDK
z$LEV^jJXl&1n;B82{b2kDS$Ky($~r&e2r7R`ND0EksCj<%U2-d;UxqyTALaK8D!~=
zDlr?9ljIEcA<W*lS-LIX4(h>nZwh*2269t4AkD@J8wV4TC%@4W%`aIC_*RW({G@yw
zoP>EGUFwh{h))BJ)L5pDT{z5m>lRMcB(9gSDg)wnXrvm>LUeRR9#*qFS1+<Cn#srk
z1|XKKRQXw^t8A!edT#v!m`KMUBr4WFU*jV!@;Nl2$e^vEA!=f7EHgL}w+IAsZHit-
zm0>$}$mev!6?(8bKy7GTr|JueTs%<Qr8*)GHdbzOEeBUdTUtNc0TnqCv1A>|l__Nu
zgjV7b+J(;ICZ$O5BUMXs)_{l{#U13pp+$|~B%iS84{TKeWlmWkC$&Y-^c4NGAjEle
zKt$!BmlRSLYzTtJkPdsj@#z@ZqepQ#4PkhOQ$fQcE*f4?gr~?TTYg6UiCz>s;Tnbb
zx@4mKt$H<nQiwoZgU527-T5^%pT3VkvIxbq1{b3l_Dca?j!rlM0G`-%93)NEi8rdy
z9iVXirfyMPSx^3g3X~6Wl)0%`P4%gq<V6!qpM6zyA<W5`iV?`D26^xfWs*<>mBun2
z$Du!A5=E~s5c{OHPJ7J~Vpa5%Kowq8PvDSYysS>>G+g8BaN0YJUelHDa3}1OTM0<@
zB-cOl<9A;E;8QEM-SgO;^853?a^3MCuX@vik6yR!`KRyP`}~W(a_smQS6%hsqi@>w
z;E~Th_`6r$eBE2`U3KiiHS_O&;I+@3_q&H~{@WKnbj8!h*1YM%JHP#_Iahw=skgrT
z@jvLdbUys#g`fP3_dWmUiU+@Y`O|l-`SQI_U;nF@KL4w$mfio|<;Op_=FWRBx$dD)
zKK1<SWq){j`G@zex%2oXzy9LF??1EV8^?}a_p#?*`<Z)Rd)*hWeeF-*x$K$e-t?iT
zpIG?N-#l~nuU`B4RsVAAo%28T-R0LVyz-AHA3y#K{_E#|?6Kvu7ry2fS6=(pd*9A^
zqgQ<R$Tw%tzT`9Sxc2zHSM<rUVa=?b`3V<$eFeojN@TxhSYW)sn^gK-jdi{)Bho)H
zl8gAF=v{TW@0O2?8Dxi6;d_!RsO@C`naq%2D6D1Uq;`t=zCB5H+Dx`-zB=CKsOyBx
z>Y{Uwx5UG-<7K+-<u~RgENRCWRvzrFWKq4&^adF!#KV-0<3Um)lbITs-ipXgk>$&F
zTiA(IFhPx7DpnuWdcq)gi<B)NJmZ<a+@>hQ9trx4!EZ3)Cg{RW_jU2?q}3w@&F}s#
z9nb&E%~z=xnw=-oy7S+_)1)=?zu`L`^Z$hW|AE7dLZzu``sz-7-tj*#u7j}uGeG@1
z`<>W8&lY^_Zu~9|4F63U!lcSwCjj%X4WnBzEs+MvCAxRQZ&lzN7c_t?){$jGx8jAy
zDJF;<{jMESH~R<GkQnA>fTImLAK4RL`WHDIkm>qi*feb|ZLuzqS{N2{P}>nYIpR10
z@8^~S`f(7syx$Y8{bdDjkgG^zR7?v$l2BEGpjxqFH<O9xXf;f>kHBrX2p{sCmoXyg
zd^JtGO-GiT%OtB&L?N;lvm2ith}n@o3z_7z!Tys}Qt8vYSOgKioNLwWadA4a&!)|C
z)K5SMMyipmQz*#O)*~6ZD`Fg}*eq*}Q@;HqV3-uk7@etv)p{=t@wa1`7f9GZM@$oh
z61k8<N<($N6$Lqjv8q$Y*a_BG{X2L=dYU2pG!${@%hB$@NS*97X=4B}J7uSHmBdj_
zKx7SJMqNY>twsal)TH_yKvV&3$b98ml!WNYO=MWbpi6gEjxQ;~r#XqLASvr!IITmX
zR9%4$HL{V&5y%7$134u~!E&>I=2Zq58v|`%a6&F=*>Qx7y3$rjU_BGG!D$1pDSR-o
zsdPnjI~MAB5#}Sfa*h}_L<-U@>ToFVpP(_sqr9|iEEU`O)O>A9144s^>9d+Wl~`p{
z;BNHdye~71flD<|RzwkM{rB@_5T%Jy3Ei6{)UvyD%*P`=LbXh2U5PXrU<0J|+%>vM
zyrS`=X%)cJE5RfMoCn<jQg^!Tm|AlHB4bU#84=^aqwxrLn<FZ4pdp}$R;no7YG#wD
zh(1Enl?GGXZQ|%SPHz*APZ+QlTu&2FhM@%~krieyO~Wg|dl{iye{P^ca5#x<VhtB9
zYU&7o+f-)iE(Sr)<reB@awxQ7FuxdR_PHpu2OVe%&q~A@JVMG+1#deu-EPn(7PPfW
z9Sq9|4ie%@sS~wJsa0j*984{3+*0L8pzRkkV_8N+CpZ){DNgCAC9P4_9&Ou?OH}gL
zNcek+Tu8Xe&YwZ=7e0j_LaU>ACVMrDa?5tONT_E9iW!}ol%Uo28KR*ug{Q4^#5p}|
z*r^U30ny4vP)Sv5flwMuKPSngRdpdWH)e&|b-}535@VuT2!m>zAs!Kw9;h%k&NM5s
zOn5(f2?OKRf~7+C_(aFnW%#}<waUq18G)8!$J#pnkk)Whh^pdBNSlIFIVMdUMcuLi
zRGKgu=h2cYnNrbGmFMcnf0Hjeo<{t5k#L5+p){&KwMfpjh#dw4oZ8n)N7qlTsC&Y*
z-!}3vxuL6OneTKoA0;4HlWhqMGzy`ahgQ-6tDj?`KGxcN#XZnk4t*CN_#+Q-0RKor
z7pVo{u}H%@P$Rc43QavUJR*@g&tXnxi(H+^hhN?yYBZxV;sn((RWnkgXMV_V2jY-#
z#GnI!E0kD212fVY>{qUwjWq#fAy^g?gattc@?b>yZGuLdLBCV|84~e~n6y=<XLvtc
z3RzV$V4+bltXL;e7|<286))1}2PH5m_ecl@!(T;Mn-nR2Q`8qw0y(2d@%*%30jyp$
zLF4}sj+R2-MXg9cd2mWGM&mI7acP}tVm{24Lo)AD<H9`rFh*L_ZmFyhX&dCD?eNrO
ziBQw7Ux9gg)e5C&QdCg1^H;+Qtg|XDk=rmbQQpfAUXvvjGUz2VDz+xGTknXbkak;E
zeJEmF6ZK4GTrqRZ1=G1RpAkFL(pQ=p2>8;yDzQ)7uL<nbqVMP_9iFcdJv~*+;zQpf
zBdC~e$j~SQK7owZM~U8?>||D|zT0!Q%GXw!aoo%kPBx^Mh6it3;KW`i7lIk)Sx_5_
zI}p^ZY*EWZwr=5idCZ3mBDz(~2%?5buFW%W!FSSVqji?tGH-&I0r9bueL1L_vZo~R
zZ7ge59bRp}T#J-(!%@dLg%->98&EZgF6RhXNRPjTOj}Tt-WK{l)ze(YEf=FY8aq75
zU&0yxKL3tdo2A7x4^b<k8n3AjwpFRujLXfgu2OrPs!x3knlax1S;Q<tw+z#<c%Jp$
zQYYtTT!P|O8m@V{ud8iM(TS;Ry5pEAPB78E>uX^xWnYS;rWA(BWMtyegsB<yrsow3
zHqoO(v)H{Md?3`<2{!?+i1wQ)nm73Gi!>YY?MC)Brpo%Ah#b@)knkKwl1Xb(y&#4C
zTQTZI48)cq%WkLv!<wx!1#$}$C}BRhZ4RBXpbu)+uwD^!@Mb@xOD?^zNrc6byUoQy
z+ln<96F>HFL29=-gg#?9>9u5!K@j~!W&(FeP0|-bs(R79v-y}qScdb8#u8m^dUOYP
zIxM=PAQ+9DZkE%*fo?Y$i{k9yL8>3ed*TXoahV71Fn)blG0Lw+y|k9t%r7}d6CDmF
zn&5XsE8`^{FvZJ;A=wt`@GWkF9_FP&M|~D)wB^I0AbLF5U*_&ird%MCv{)+E*ea3p
zqsg{Y;U%5`Z^%!ryDPGriX1wMBh%2HmU5)r+eYr7p9pPn6N%J#Z-D7*=+kx3zG-~a
zG9v-s!`LuxSSBjyaFp9RuE+04j~~#};GJt9#WBeblOtliI48n|Y^ZviQJWAV80KDE
zj51Be2uO$lFwdhy5UoC{`()5E45Ys5hyybTAB_v0Qgwi4wVBur*jkmR55*{z;iu+V
z)Aj9<I^tu42%<5rDpkpH(a(hWG|84yJFb9}GGW%c^+I(gye&~35A9j`n=}suU}}1-
zOeo1wiH3>l!KSy8Oc&!cUyl00&GPf$)X1e^ELBZuNTY*NZMu#d9EG8J7y(0lKr<;F
zX<9HfEP`YR!-If<ZI-OViBu|UFKSK`*Sk`{TFdU&^VJ*muI8#wgC5X$Wbg+i-s+Mj
zfZ$pN0MmPnH#?;8Ask-g8l>PxW4f0xYN*FYFuq#APJ1fVb!aF7NB`BUPYM8jr*{O6
z5Donr@3jzfmNDtn7p=U3mtW&EI)IsjFV#S-lL#w81O?`fxl)t8-z(C`O9TDYz{06a
zN(4UvF+vqYMtmus-lVM_-dDl}$GJJ?Dceen9X0;$m8}`Y*OIU(S&dt<aHqjR$i<H=
zES@OzbTU91qbf9{N!u?mk9uXL$!aXDT&H0;^@=e%po@GvBG8vz>pcWm3SGtP<j*Im
z5&q0?9QH)Vw2Jczcbz*?3vq;xuo8+_{p-WDY6Mvve}K^oHy32YwAJbOr75Zl)0buy
z67}kE>%?F{{o-QhyhGiHtnP?k)$=y$O_3h!y=2}xb-j?Gj>!01pfxM}_+p+uD`CE&
zcHD~-AUvQef44qO?{wszY+>zFKo=vpMl2WHVXGfr#?K~z`LB3M*7LF?IpM%ZX%JN<
z1?6WLZJ3g;bRNwGGQjfZL8)Rr)2V6Qa6H8s->QtGJ@lo7?4fG;FcNX<2rU;z6kOWM
z4h@8kKyaEyGquGdZC{_2fJvI5EWoHz_>xo~461s=l7{5O_C~Eq{MO@OD%R0rY;Lw1
zDfMrS+C0oNDo>(}32S^E(xFuU$sr|(n8B!v)RmhuK}08+vc=^gvX(n<{_?!BUwAbW
zMVX-OlL`KZm5=a6WF$4#$e4k^C(eM(ikOyxOz0&LTXSvHrwk=RSOv8gaO0DEbPa|A
z#G`b++fpZ6AxL(W6dhOqhA|&>gvpo+?&#@8h~$|P1`Wo~so}I3d3wE6Y!{du-C$Pa
zpmU`W%~?dO0B#jAV<>eVNZJrpGSqzfvs+6)skk{@JZGzSh9H4=sE6shb;3~EYC0kf
zEQ@TF?N%Q;JXl{}WDBHVK%dy#rwL)e2oGst^iZj!bVQ((@&tI7Ly0P}5pqDF6=a0r
z1!Zy|e%#Cb1f*$`m<7|@(C%Hc1TfB*iuY*B%BusGJC-)f6EsepP4YRi?03-+?Y6a(
zAvMYgu;UO7s|(O6AY)0QpQjhYQ<FiriZ)t{y<5rDE3BN-X8FN}t4o~NZs|8Z$Hp-N
zRq2N<viY6{j}NlkEpZUV8p<g$AQZq+9>|OK0fXt`)(92jWF53d{?}|g(2eM9oI+YY
zC0P3X=6Y916{poEz-I%i<h}Y3Vd*rLqk<E%dIB^%PU9st>$rLCFxrBbRW=dwEF$J4
zfyz|df!?9B>V?%fjn%1Jp|d(=^%#iEgA$d1b{a;U=Axy<keohx!c{YGG_a{|4MARh
zmeIQcBrdWkp7gBZvMw5-J$kox8E87~!Ho$2J_8OG&N~CA4XG}GOHho!5-ODmS4r_W
z_<B}J9CGo~AceMIRQXSzJOzd!k_1|O9TpLTG*8`7gi6Vj1YNbmg=UN|aPLN}l#;Yy
zX*)=wAnvHnj(E`XTd%Eg@qS<N!a8=Z6YSHfq@+p`DNm~v+W3m74aU=`1O_^5xoFEZ
zP8x;?X=R3{BF;J=$VH796+aw--kTz2Ql$vTRGDKgP2MTi!9?Zi(oR|tB<TY*%s=D!
z&Fc7kCh40sZL(C=G{jK<4<nHgwQvCp@}8&i1!vNfR3fkVNo!RCLYsQ?G^s-)q~+`V
zaJLz+S%W|1$E=TuiyBBGRU>4*rB47EFisPQj8!4#;rC$XIA3y*lN0~mcUWl9iHb>`
zHBJ#H8rX>DDbR}%>X`>4Wp%l-mgR)b6UF$cHMkNo1@UwS)6%|$3wQ>*>Ht^*2#kvE
zbi`lBp&saQ2Z%Boyz_nw4!t;UpiD|5X}W}Hy}&-u;I+4Ns%XhO-M&X^3K3=RTbY)T
z^4E62CIYV;uWzM9tZpBcy0LQzWQY>jRP#`x%t}B*(J+OgcC*2F>Ph8KV|z@~(}h{<
z%T~9oBYK_-iubay_7RG8xLJGZFfk(hr@R)VH}zQrQS~4vGmAyB`u)rkpaBt*00!1h
zqj_B^#sf!?JFdKGiRLKMWE^VX0Rx}UDHyV9oVT$9lj<Yc6PFVb5>@O<#g@Yfy|D{`
z3s`c+Vj?3x&%C7w?4vl<A99H_)MeF=IFU_xGt|&9g>ab0t<3btkeq<H<-i$@=y*WT
zWEk(N*C$9EJu~i0)oB$s75I`LjjVfYJ@e4vfPSn)8~PdzokCV=tRD{=hWcV{ntp)M
zMS5FSB2wV}jh=}mxKfS`K1UafeIRd5d<wRo%*W9%iDe}!ips885BaIURWEfMNwVZj
zW}G@$ZoD%Mk;As}lX?1FW8%O^)hQ!->@l(Q4N0Km62oG!s>pV7Zq)t43p_NasSS!&
zXi*fM|5;q1Q97jN4``uA_N{*IFkucdC)hY7$|-FG*)}aAz^|<I@)FqOsPSI9O3aG}
z?IsNce+>gwh=S#p8gUe;;B%^Y>kQuhGZhI~WJ17{Ng9_@(){{jAc&EM2lj&Nz2$kU
z>o$HP5;<-joY<1U!WzAzKAI<wSSdu#$8*MoWoyAD-Olhj7V8N@8#<B_pJqm?>O>v*
zJyyj_iqSr1YQPySNL9}=6%?TUpt3Y2+sP<TdYUimxiDgYgM#a*4JQ?YHALm6QCr+B
zy-e04@Hi=<1HekMPEAhQF0?T8=lKl>M)?nefrXai=u2^X%Vn9}G$#}bm5mI|#M=;-
znS}c1$0HW{h#!FcG)@l<c(_zkCjwxtj!;r4Q;|sDYCTbVJf5N%1bEsckO>ka-I@kO
zNhL&78;Y~Ytd+H02JdO>s@)1c6N%;KFNV90gZTys#lYeqeua)&gZ{SnDr=eTctEx&
zvLi&Q8@3=RiA4s6o@rW!y9eyILdd%cybg_iz#abxqu^Ah>XjlwNib|DCb2H62n+AP
z;ZT_!c`d11U-4+U`vet{rsv>)Vhn{I)brn91kpg4z@S3UK)tX+%@Oxuk>665-fgH{
z(_JcBhf2%&1nA7mFzI#DNN>)^OsO>~$AHNA7<3urW;f;FIvlLOcW5b3<zNuSqtlD#
zAIPI=UL6O4;ol(Wgo@}h07;tk3wIt>H7ja|oQ+t2^$>7^!Qk?hrO87938rKq;gG7B
z2^<0>G!Cqv?tljtQ$xL~p|p&pOvlSQUlTg*5E6lgKFtx115hE!mj+uOSwf3%iJa;4
zfl~pFK}#JGE;7oME(Qp!gx00ZK?2!k&{TRDI`#L4-iOQJxA3Zp@uY($3@u~~J!tHX
zGJt@5M55sI%+I@@R&@>skKWSNEy2FNTE^!1{>fousiG_b@&aJv?09dkyqQ>b#=(nK
z_i%5yd3IS%Y&|T{BDZdz5$0{H&CU+YMVqmZYsR(f`XxCBJxoadM6!9ysFB`UGOjhC
zzkZX8<}sPod$g^KAUop0%3!IT?_W8(HJ98J29wgv#ur$b9JjG$roCWACa2h39JLGD
zKUHgPe0M1dq#^PJ`pme(G&AQlT;2`Czh|13$Z{JGWB&VsxMysrIj^>)5tfrG$8C^5
zal5@@&TMz>qom&$?T?#*M9VI9=ze+rN2Jk}ozlC)F^|9!@8-Bkl`Ea5lm1Pa9GN4#
zMh4f(<W!64<r%qlgUL%5LeA&ex_(`>DH@5*M<g(3zH0#6Icj3Ne)Gu^+Onba;yLT1
z`DcW)oWy24Eb6|C&8<?GzABR$*w8S~-M?$t@KC*=+|JWl5|e8T=j$$Xr=A~RD{6-d
zZkZXKW!H~<lFWquOwTp{DHPGDj4UcsQ;BV&F`1}e2v)7{{B(#KN`>+f_LE{O6T4t_
zZpR*~-Ef;%rBnxzHIT!uPg)EjhO1hA1Kx+gGPX>w6~={k^wWlIB0rFMWZlS^1h4-M
zYe{EP7A(x#mh0~i9VzluR&Db@n(Zpt_Tc0uTPbJ5WTG9#qYbGxW><66@Wk3kN~20I
z(`tsg&ML&VI(4?pevCER#>OMJ8gAL~o*AY;7uGmY6V_(B;p&js>g>%UlM^y(StE{n
z2Q7;V!|YdDN&O$A=2oPX2{ti2Ld}u9d~{wU*0Cbh|8K@z&3b5vvW**Y+CUmI%-d0O
zZseAiMUxxRM>utvO)@4Z>PRhgSBG6AGY-5YXvKqJzcb{&J6>F;$&Ji5{g%-XGBeU*
zMz}j-T|!DyifvTjmB^WBa>CqRbwM;To}87K>Cq%QzM8yAeX8r*#kLD;j`qgJ7+NQ@
z9noZLKJ-ZuyWSL9{Vsr4P<_i2d)l=plJ@Io`!heKWtaEaW&e`2e=^=Zen<4#+h4c5
z&%L>8)&4u~x!_Q9{M6QuYxB+PmVb1Ad&kXfH$MI7?D83AcI}KM`*zIPzi&rrWOnt%
zM}K7BZ;uY#Q+aq(Y54Z)sk>gc@@00(wncXTrbVBeeOJEq$?BKdOCH%<e$}>fHkPt)
zoLm>pYrOfR=ltMpkL12HyR`6;+e<IDKYt>;dc`A^{d2c3{LZG^|Dx~e%V)kVxFWaz
z?!9mP>c)GnzW8;^uaT>}qRJQc4t(|Qz0nt5XJh1AE|2WUmA|vM`mbmIY*}lzoRa?p
zgZW2xM4veO+OA!%eB;#itxuhCr04l=8G61)&%oUE$0uKX%h#`*w&m+rp8n{kpSttt
z<e?dl{Q7~{p8w2UuX*+}YcG4zvri8H{%bowa`bC!Kl1yV51o4Jhkm?p=7A@_Jm-eB
z|8V^$*AB1S+ctX+t=W3}p;hmH;D*<|=<1W|y?@NDedSNiU;D~MpK8zl#@mj~zH(#o
z`5*1?f9ZQay!w=1z4|*#|JPsLI`;>Ewd189S@-PR&v!o^d~M$!r+n?%|D1AX`SGPU
zuJ}Ow?SDOT>5<15z4xQh^RwQtV(p5Rk6*vO_dD0G-};w3%ul~HaMD|U^lWhbPoE3k
z{ndB8aqjp3H1PRXA6fbpe*gO$dwb`UM6UhEcgtJ<@$zWacOL9NbluwBJNmye)s>$2
z<$HU6XYb_WrxwQfegDBLU-8ReV)|+CyX%w-AG)jSo)10QSNzdn>7MU?ulHxa+u6H^
z??|<7SbF;FZ|;Bj@|)Mb{H$lcH)s8)+$$e=Z{M_^JvuPu@Qxc^x$sr}FTHoo&e4Ax
zcryF0d)w#iTlZ}C;%)tl)_<t~j?r8){Rj5u^4aAb=PbN>$K3BWj&*0weC4!neDV4z
z-zZ-`<#iW-s50@AO;Kg%J%h=?BZKG6IK5~7JNuWpgXcA#T6Vqp_<KIk{qwEoWXoTE
zu2BE^J<&Vg)8F-(#~<vu?W$WZ_`(&Zt^Dx~15?h}EAp5B`h+am`0nWQkN;`&w$_<D
za*e+ZME?0CJs0zizVDaK`A=nslHX+tyZ?Rq-M4Jdub&zXt-ZTCRG9qdD}H-urM&*o
z%F=JP|7?8sJrCS)_nyK(j315p<jR4O`Me}^!}iyhb>q>j!Tu-{|Hr`@ueo>i#07H?
z$mk^xpZBJ{kDv0zu>X`#&RV^2^s%)s-o0&mF|1U(&ad41svq><Gv)br?CB2rugp&2
z(dc^@ACTWS9-hB?Xm{hZ!fzW-JpCn^`PlD<w@rQh)E&#;*=3(NA|v0SzrU+LGyay!
z1;L^D*?GIZo&UrK*XM8i#@g_Vqwk2$_`y9vSMu+l5&3RL^OhaqP3JS73X_9pGe9`A
z@3iFKM_&K715DeD=dAp5_u}CDC%<X+q3GPwTclBXfNzm(@A>o>YT<dexv5Ko10&b>
zPnePI(b@gQ1E<q@&)s=jZFX>P`@ZvDmFp^<|KVwi$EVMl$C!F?vwwc6IrO5-=I~<8
zxAjL0<(}7FEWdfl%U0DFuIR0W_b}nV{o(^r;cefZoAll?GEh1k4HQ0-Tok<I6*C9c
z1ix%OD$ztZOcytAV%SXS?)&u8?5TG|x30=fd;j+L%9Jh7%8k1h<?k9khptmbe~G>N
z6nXpLo?39;r5Aq9T)Hxln+|1V-W-!$GCuv_>IIwK?Qj0*{Lj9B--eHT^8-KoeLSx<
ze(+`D+({>oRcCx7Uk&!Tz8P2VyR~c4M{b_zyX^D@mGLc$ZM!<Nl3#VP4KMEr<{s`3
z##U|K^jG_*cl{`w+HB?6(q6f=dP-%%@-+uqORhWA-1mn4`KT+L{Gse$@WXxW7d57a
zJ$A*ad5!9tv%_`gpDhcQe6&3E_7DE$HJeUv9KH4Ak*@x8e>Cv!?)I7u3y-d{r`A5!
z+Lc|lEeiH;>-xdhZ(a6_{H;0i7i<2$Foh5L6t?EBu|2OY96U6AB;VCLIy`4)v?ZD`
z{;dTwC!%?q-yW^Fx#Z%$@!;S~c1zc+q*6Kcw(m*b4V=~ZM)~lJx3w?*(4N^z^R!^b
zP?ua-a3<GVo&HFrFj!BP1%uJmrAg<OHsk7VDl_9&<)k3mw4}jquk)wYZhZeWVQXW&
zX~3S@{M@&<HW&X}&|GYnhNe2uf7-*n+jx=eek0dBeEZTVg<Y@v<d&1)6zn+NhNsQm
zKX~aG2Qu|(wUf*Od&$AiEs?u>zP54O%4HjO6!vA$W1tje*S1C8avMXT<Ue{A58BF>
zK{;vXDt9y6%U%C1(pMO??zBWcdK%A(gM%_uSY`8T%W~>!UU52fOZBAqW$lxPt_)wg
zI1U#SzEtfhd_=n0vNNMFF+MmnXzPmygJ{dp#_sO1ap~zD?~i64m7&v`nYE|M6$@Tt
zPg&5<sp7<O-pk3BE8Cx7=f)RTo^@cT@K^0q3PWT0>%^ViGt*B0z)W{a;Z&C|B+cxC
z!5bDvr;HDBKxp9tD<l6{aK#%6Zg62d8BYuL$K6}j=Y#lX@r&Y?d~ndk)9Moo<_=5_
zZ{R2$Wt!-jpI2>S#55?=+1wKhT`C)gs*;$QGIPeDjfVzh=D=lqH71dh>i5}jaFp%y
ztOOG~akm^kYiH6PVoT@rr6qTAFr(QO585t<ohJ_!qG)iY%O-<uS#8*oFQzXTY4^pW
z?IneAm+4_nSq8_uWzZ!(byp~4*$gn`_zKhcGfo?lQ}M^9YrMBO*dFaU)qQv(cGDc&
zWaGh2Qef|8q2Cpv-Ztl`+R4;d=3g|#HwC+8>YZ_Yc6W_8yN)zQa)HawD@^kIxr$aP
z{>;x;uf-KNIN~1bI0vx&qN%M&dYn!hjPYn+0VVj_M8Y*WCVBS$^jT1hRO({T50<*|
zb7Awo^jM{eWV}JJ3xc4;-CBuSMqPl3q{exm4UqNWb!|mj|G$JmsG}To&eAdjVi06-
zFu)}mB+dqr!z}^WwuU)jRICu&I@d}lP2DLON>+C~m@#M?8qD4X!oT|WI2w+~fX<G4
zhk6*D!L$R3)m0P254pjGisu52s=<yTMoMfzr!<jJ41&k<D1`zvTzP=<vpfY5ge!#P
z&%rIS>hbb9(&@xE<lpfWVFKd+Iaor7MG9UH($Ew#;5?nORH%3wK{CgI(ug^Tcq3@d
zhZ5_vE%G&`&69=<gN&i^Q$)z(!+9>k(Gu3+R0jr68lLkm7sR9F0T~Tk3HPiCioF9S
zJOc>PoLIf7eE!KDJvgsJl|hP{oC=+|VNZ1;TZE<I8q*mhzS@Ty{3-bSD~;jb^il&h
zJoAvA`FZ>oN?_!{zkcZE=il?pJOAYmPyf>s_Z<JygYP^3#bfVz=GDjk@bq=}fAQ%r
zExzobn~(kNLziFm<s<+0;Gd3s<=FR+KlP{g9Dnt(<44|f?Bl=w)dQD({<-(P;-ROH
zA3Ji!gHK-dsptRr%zNK=|KrDwAAjzQTmN+7rxt(z_&c6{#pB=P(?4H+@Tu!Q`^*1z
z{E{pG@c5gLKeXn~hhB5tz3;o?-oL%z%TNE?-#>fg&f|Z3{THvj;-^=A>;7Zc9eLoj
zpLy{4w|?>X-yUCc!Ts02`N#vu7C!X+@k@U7i~qd*=?9OU@$>^%z3-QoJ#^}?zWkq8
z9RKw@3BT^G3;y>rfBV-He8=aZ<F7dOr|UoUmdhS`@|KrG@1MEBmdI>L&%m5ExJY(x
zU>{yzIXXA#+g2DHysf8qM27g{_u}4-$<F$?Jjrv@duLc#JlNc`bF!y*Xwum8j)+}6
zluIuCURWBO8E+jr*KRwNea%C!aizsWVm`jTulT@M;^NMNl&)MUZgFoiaT+gXC|tqA
zR^PyA|DvkteutHnAK55{bHhD_!D#GM>}L0U^D8T73=B^jiiUeWF7e7&)Plm`!{ORf
zlc;A%Y70JxZNIBFSeP(F-FcHOEUvG3%Xm~N1e+SaoEdk2^&|8>n<ZY)JE`Ltd=|jh
zEG^sgJ3p!G#5KS{;RDuRPh1T3L~F^Pfji+gp4Oc3cJ9jQ{~J0@Pl?hb|8MgDk)#s1
z|C{Q+VeVjm`k#XuH_@Y5qWzzSSW+7n*(deBC3y8^sDaJrLY-)A>6RC9gV>xLbH*-A
z4iB~lrO!ebwV6^G-KHYsT{>SG7}l1vn9gyL_e0}PT#lWjle<<=yU>1PW&}bTR+*s;
zIYvtI*uB`&e&c9z9j2Iftyra`UhYaN!bEo|$oOnVEtI}BPncm7DAp)kVkNAROu~F*
zBMh4LNn+XwO9q+eVsE)aI#6|<WOXCwHdcRoCJoroWg^a=n!vSVCw4VVBw&wUAW`fp
z8J%7L+@q|H#HP}U5Hjek$pI?|NYD_5=wx(i6Pp?Q1}ALjR>Gvz&)gKD!^Fv8j^-c-
zhoU8HAcU+Qz8XB#w!#)_p#T!GmI)1<I=31Li-j$<skOFPDC1d<n9Lq7bz&}B0?IKF
z#20&rdiG2R%EJ=oKnGUpR?VMfo2UyCwT#@Q-$6v0i5Vkq;%1NsMO9D>V@%ea=pPJe
z!H^+`b;OecL4p<?@!Hb^@FzfNfH<^#?Jf!X$3op&scRoZDoM4edc=Ms#)#7K!wws6
zno$kJvajPrHCuD69z#`#-C3dZS%Wi)+G8ZDaRIn!l$IPuNhkWIS>%NPmWVpN0%yen
zC1i&Zv%LXfDO)g>G_7H3v=or8ZAMWcFpyRpN@rmk(ZUw%W`i|`3n;Kj7-_Q!C=lpe
zWI@=#AQx+LmS>>QB4^NtUJ%33cX87@lSw#7$V*!hkm?vfvrM4sx)>o?kg+PfmfihD
zRU`47Y#7ruYz02p7;1zN%|$iE1kQ!b#zn9K6)4KX9;dgs2qz$jWK`ES6f*wG^U%f#
z6cECT$u4aWS=F?JRS7L5MppqiwJxTH8WcQHL1aT*bVerY77X<g2CghQ+@WPasu_nR
zg2l$pm+cT~i3idRPUW+Z3^)_4SI;0>XLI;Whr2k507x(*Y=iJpk~er&sUbwlx(v4n
zPLZ_QQA-L=+7elgYSeH@KvXf(5Cto8mM%+#xLqVm@uMFP;RvBF6siX$iqs|J(C;W%
zTUH9c`lEvcttc_*kg=s&K)~{IY6XD6S|ee5q4NuhCf2a@%*UK9>as-xEexn&+-PvB
z={Pu?7%Q0pjH7NiGf90?w`f9R*O@xC!UZy>^d?x4CZx<5{C)uXQT@tMoY)4&R~N*r
z>I&jr{e0|HwJ+y#3SVoYaV!#9wl7n(bt4iv$_1n9#yiKew7da?s~;p78zklj5`r47
zwfAX}Vc)fcw2)m?H*nb=kp<Q-EK|Qkjqjjc8$@HvuR#j9U@QQ#KqJAQ)l5sj<3gr&
z7#gA8WH^@bqe-K)5|RuyGTH_r41-b9$cVHJ>$%#VD5QeqoKOz^Qq^D;Hnvt>5*$Jz
zT}`GA2gVr{CZVx}8aQDID$%fPjC_bxW%^VDVj6^k<2KIgpS-6=HYpGe2KBa7rv$s%
zoP)zXfm=9gYI2F5`8cv3L+x`GNU~oY%1A-&T!^GN$GDKL6HjOk`kQ*lt6c<vwpn1Z
zmy2(P+-+8yic^e@IW60a`Cg8}3wUY`3+<Ths8TS}BEvKQwNLoTutG?HTcxNzaaR4T
zDCtpLLm*S=#)z-3A*RnWj$|_-fJ!c{mgYkSTPZiOibM~9F|5UdFl>{G9I7c9QVFTY
zc$}Erh+GiCrjGs!dP)$FR8<m&=&={kVl${@ZGw7@syWcc)f(51TX`T*CtcIT6PAsb
z36EFtv~I*aN!m&AYuJ|kAz6pGygO9SJviPILM)YEF!qttDmluMFMg}(!z8k#S@&)(
zHg!zu&HC?f{rCao!52+zhzhn$TW|}gj$jyo29rs$DqIq(LfR8D?m~>29j&wf^mghc
zAA{u`E<E})c$G=o=82b~($Az|*$|;y0Vl2W*jKR%HbEjr^tmu1524KFGZ_fxrX(8z
zBVFyPlo;rsq*bd!OI<1Gx^hTa4#KN12`FChW=!f8hdkwC*m?)5ri3}XNP|aLG=Xun
zvdXMhK1H`~5T0ee+9ji-29_n?cZ%`l%PE+)<})#aO(l<}GqguUttW95ZD)-tztWZn
zz~nS~EQM^f@Ig@LqP9dlU`7YP@3Ez>c&o6GVQI&?*6k4!4ebKFQGEh^Q`96xTZ-$A
zk8DG64(DyOU-Z_dZeH4!q8-z7`VmhQ$jY)EQ79WzF)pHH$)JgH1=kmk)ahQvYNCal
zINTT}cYtjw+YyGGz`8DzRXN9r{3pL^kjPOL+?3`}97!~;hixQRkD}^*wn(Pq@d$2|
zMx4`cLk7kKN1-TFoejga$Z?8|B{Axg%jHM2K_&QrgjUEIHgkk`uvPSsL@PqUeZ^pe
zf!i1CdTUU+seXo0DE7>R$xhcOYu}q}s|4u1UTHe1V%yz80q8WN+@>=6+GJ+y+lPb&
znvi$G4YWzA5o%Y#D|O6SQG9dM)8>UE@bKn0Zbf2T@l<~z8)dW|>9VfWUcZEjfkKMH
zM+JK0w~<1t#WN9OJvGj86T6uyN&jSii_4HOKva&|i!sI$m1)j;cVws&<vlMcn{m`;
zqp&n#<nSk{S-ay*eH2BG%?VU)3ZpL~nx$bnEAgeHMOI~lpx)IrTf%ioYkfJY2PoWN
zOZH=xTo{?LC_mU2WN2z~(WHK3&L(o-@F1_+G1sU-QnW}VJq?^<aeJtl^q#aWIk9x1
zq8RI_uQWR!$kohrwhIs4f-;c^H)<86r7ce20b^xMg*TxF{x>k|G*lR<5=Yw(R8AsC
zp7~B37Z9C2;SsV+PV212MxsE80%`Or0YD{J?r<SisCy-?cOrFQ1Sq<3&h|P8lqn*s
zL_j32Wnji8uDIYv16s;@!EZ-HY4kTeO;%a+i|A$iRvxQp7*Hz^Bq&R>3R8F+sH`Ed
zt}Jsn=uS*5W9l+5B-!g!2qbk9wh_@m&Ctuo4+2Fq`wc;zaLuU=WRx2rh|wk@XTTGK
zn^pk?T6W7`q0TU@5gZbz0va80lpG$?q7^zUCIK{9Fk{+?J?J3DDveI>aDq+BDjrQu
z;UGE}aW;g7(bryC2iC}0`c5VSCQX3G_{=3Z1`9B7GEBgzBa<4F(j`?~MNOat>pqpm
zSX?L&Qf@k2$VU!dP9g_Np`xJyF)b9_*o$a2TaGX<d*@hydS$j=v@w=_X2^x0c@PGN
zL}*gCk%_n_7iFAP+paJQLtKHD6)mg|%J?ATR2AY3y|1=tYe&#<0}SRe;F&?kb0wmZ
zl?6B{k5oF}S!jY1K+RLOjc~&gC9b!MN1{<pkxdK@k<YL{!;yB<hM5K%end$rai@@s
za%a58HCN{1Kc(UYPg%)$O7~~i7*?9L@nj+F8EqjFoTFjfHjS=#bz!som`e5N!4NaR
zmG!>K6p3KOcX*tUqn5#qH6#R1tp;I{(_qg+pN)Ch2=-M%a46PMlJIlTC^)@n5<bWN
zPLqO{@ot#lb|?>*QC?aTfVSR@RtJlNL~(mMZKb`uxXWtu>r^mYYK)8+qox7~JR56q
z@^jo27?R*u3jXtDbj?Jx2GEvn(L3P$m1O(<nVx0rywEa9r7CH^$5YXMC92VNO*)m|
z{}g2c1Bb+waXX72Q(#F;GpBm=Hzy4mJW1Qs-wK@@Ny0G!pargB7_iYv$%bWKfS~Mo
z0jdu{jEOJ~t-%OL+)|uX@q>vFCk<#ca(E|#NY%55pZJKpQUET-q5~ag1G&(S`t$-g
z#8HwP2FVd&gkd71Q(9JM3^aY(azLw)$ms|wjGb|oK0sMrqxM$67ke1Wtv(|3?99-{
z4sb^n?L`zEKL!cbSr^fhj;ZiYWmQN<9M=(kgr%;)JFq7u%9{4B!8UTDu>r<VDw_z5
zfFMkt#Bf$iWITzSF*0h=QbdOZ2lhp23~Nz_C2b)2T#N5DJ&VgZE?Nz(P;d&~yc8`(
zK{RT3gCJu0cr>$`u3@Moe$Z_b2G4~1HZ~l=ULUU%0`0#nb9lTmnJutjs#lL`X9pwo
zsYtpF%Nh~g?L=C*G&DpWXo3m6^cF#tsD{FKZBF+hmxkJMGJuUQDhWM#js&!9sP0x#
zE={5iCksdZ3EaSyIZ3DhCJwL-B;^Br(k84~jo{m3$d}myT0a<4<E<Brw?|3c1)(yq
zVbNk{J%H`9>YC(dyfL4uUVTf9(lEqTFWHrVT|cB~X!?gWR9PAQ<<<H_HcT`nRO>=2
z8cFGV-vBS@gUL}Ru^qKwW53`0;FUOu2z^Vhe^&7t_`+?9bB4zXnsKJXFf@Tlbw!}1
zxs!Mrl#Hme+@<D4yX1(62@Ru&P0NZQRf`~ok`2!WYrKSxJM{HLvm_R|KVf_xq<><U
zqRi6Cln<JuSvGicux3E)sBy70ibAS*Ltp&@hueBXWwlRIq@e+ZFw!4k3bZr-^-0x>
zAw2N9N(zQBM_3K3KrxW#HaQ|v9|3^#A}2Zc>C+{YUSelqqr4PA^3nu#c&0e&Fc@UD
z%;7eXWb}?1atsfM7N|^+mXSOpi4vlLQLuVZYp>66A~*RwSQR6z1(s?|6mkrqdF5L=
z<c@H_$u1RwXeNG<A}qg19fqF`xTako70*Itt)yU0i1!7++FPF|A}Zb>YSX4|-4msn
z!(<t!elw|8C=EPS1tF7`;*iu6Y90%6(2yUa^N<QC#(BNs_DzWF5YmR$bUEFtrudXS
zP6I#K74@oMtnx1~(7=)R2E!Qvg3xj{!kCVZl5k|gfkvI4NFA254qOpIB0DPKBrzRT
z8rh)i7k2|ULXF;#$psK-kPECK-b5j8_x7b#mvV|6;?%u?olYvyiDO486(9^<3rthl
zI|ASVt+Gz<I9#NNy5SNJmqc3Z7gq?NiAYP?MZPSzKgw25ZLJ_fN0OEx!0>Z=_a$iZ
z>Q{qrxhfuqF@aSVqgPAK(E}F%t;B_asihXcS4cg6)sfRc?y2;0uGfRQG#xH5@p4+P
z5L)htr*5X=D4Er4LfTLdfCQN|iueI_iq)&r3w*p#Ry()AXk;COQI)jShRnl_LZxg?
zj@fF*fl7wvCgiFBOXIXvLX{->lxGtr9wJlIt(_$0ynhUh$Zp)$dv%<`P@x}Vn)>@p
zdgr=KmFY0J9WegR)ps}!pK1wztQ$>J8SDDZ08I`U)tqtdNCHON<-c|ka#|$H!D$6|
zY_WiqntKujOH6&5n8aCD8U>~Slovg$)iltsjFFF!XKlq7`K91w5AlYrW|IH3DY1M3
ze<j$U7l7u*vmuq0Hg6K=O%7IEdI$^Q3!2rhG(QYoNm9qi##n2i@D1EcO)au81NgAA
z)y^$kr|IG*Z*@Iiay5aGQ34#6bP4gf*JF|i8bx0Ish?bEt^`8n^rG`vYEn~}urAb+
zH)4I7716H<Dvx9s3PQwI>85y}9eYZpt$s={fazB1tx=wowgtaTr(^Y5oj?yNZwd~>
zg3DmE$;_xxtdkJjY~Q+2&gTv@pwqJ;5U`lY6P3E6QC}^|rBOc}7KIFuw`MU#l0(X`
z3=)^beIe2tT!#59OFoSfs3MHz1%2@3e@tXthSf>mrL^=_)D8#$ifK3ul1!i;rS{4B
z0Qf6XP?q7622v$kR-E+}LIX`m-LWbS^dpw*s5+G&LB7n4)YEX~$Y~Ih#j6C|OgZi6
z^(_!>yuM=etF5;XBq3^twvPu%ts0Iv)C8UL0!=tp$)>!7PB)`mjb=ipprB>8S!*7Z
z(Z^Ms2J~CQb+Ti#G*Bfg>%wBlJI_E^MJQM#=Efvnj<+MB+DZVzf(g!qGmhH`_9kjn
znOjE<A&s=V)pFkOb|p|s<eu;;<D=_Is@y}@bSgj~#+Mn)9fbVRR!9J0Tgoql7#@s?
z9imxZ@lDugg2YyAJdtSmEL-lAh0vFQF=e5gs8c)^uxs8DQ!7YJ?Z9REF-HqaYCG}q
zqD{@MW>}Ncs9uDckr5gN5j`Yjaj8qKjZ!-mQK7Xpat2;jvCUW~0AOJ?e{D@N1g&??
zqC(txXrc|fw&@@Vw1o940l;#VMzM<w9vG0MAA~@!BXK#bX<N_Pt=7?)rp<vo|3E^^
zwi@ooFX*<4Gl;WX83HJt`237hmv6VeA={8XB=DUtN&B-~XMft0kd#QtcTtI{cvKjn
z0k9<MJR-)!2YI<V2`#l4(_9mUrt`N3d$e?KfHJco*HjzG(Lh*VzedCGfU@(#Bdfu}
z>SG7?5O8W<CKGj|LEe-uQOiX5W<-vwLelgCp$ytz$VK!5yHVt9XSM2)vM*Cj9XiL&
z`346k|LkW-&^Ru%APA^Cd&1EQWS&0K1cgwUbn2ilg+|3l8;z!~<zaM)%8DHpR4EKH
zAW9o{MHxm*dfc5zx=sYG3v5n?2@E7@IT&avBn~hZHd-@-tto4K#2`!?`I+K;DWI4R
zgpsovHGs}S5rFsOd}LDJh{2f4Xeh*FOBXji^Yhhf)fE^k_5NKrZM;8{wtE|##!Ot@
zFwWEDw*7s!*yQcMcKwS=Oh!*$6WYX(sc@8j_O|nA)k!l9YhwSIGx0~y+;8I7Pd4S$
z<s0@Shp)LhFSWs981AYk_3~5`o;kzN$+i02>4Oa`KYU3p+mNE^YmHQD@fb^QV}mUn
zy)-_p4{e!&;=zK8W(G;ASZ}b%dVX_-LEc=u@7$i3OZ8%VO=FHYH}soL^tfjD;#%K`
z)LNJB8!5$MTgKR`x;Pk>(Swc_-PgLa=DHkDGUn1a9Ayh@`)XS}cos`}OKsteC?zS|
zfypR2YI8OiWnnz7j!vN?cP1-MnW#<AgqHQA&1Qan`3=^w{KN?&Ug+lLXCxPdj`ib4
zW~mr+_Mq53@|&}>L$b=o%l4FliP5Rlr%}VVsLbM<44bNx8IB&68T~oGXM*<UlXg&+
zY6;oW%UJA)&0zgZOV?2y>$iK}7^|61eomQgz#JJ#-lls>MutH+;z*)pS^GNnQ)1)V
zlEugwEMH&6MTKV5ZQ!-Jm!6ee4RvBhTze6%w5#5J<7Lhy(aS@sZe!L-{mE_Z=22N9
z%g-`hCcfNWx{DWX*v5L(wYHhOE!b3PpFg_Clt+@d6b6~3Xj-+zt;y1VmE_#}Ry6IZ
zu)o+^TG?>MEG!}8b&8~ImN;u<eyg@RWFjeX`>%1~gkg$Fw$-DC4R0EX<=o%NB3rXk
zpiUp&V5r4b*PD9G;H6aX7R^4C!`<}W)oA(FUSrN>;b@;t=8S)&z(ae*oYhS1!K=l(
zQM2pZ>Mm(cuQSq!ij#wN*Lbz`pBwU&QRQ<@;rP7KrKnQuBV}I1M@RRed4u6>+O(~A
zC3Y;a?Dd_P+z|FvgHh9aw9r*7pwuAvS-CPeSwAFpEI5VIi6%@iDs?&-=i=6oIdw36
zb;vfQaK`90!Pfr1Bp$OvW40X*-a?|)r227on4DUd(~Of~UM|TdjTL=2*|9nOqYDOy
z7j*>*AH15;h<P<zcDkN%`QVdSx6u~lwZapv(pxtyyLC<DAD`%RyGmC+_VC_?=N`PG
z@0xG?am_dH*mLb~?Sp^)uEvVDumAaqtM+fZ{o2Rw-h2K7>z7?VvVO)B`?o##<MSUm
zZ~VbC-h9RH*VnG7^zDsSKe4U<bF;3!;{KPs@gM8o*>U@tRa<vFSiJUQ_s@FEvihqh
z*IaXX?`fMiEzF;{_uBWr>+<@J4J(%SZGLX<yj%CqnfBgqUOvzWmz?#py|*vixwka?
z9bu(7|C-mn{E^4zEIjtuoN0@fFBurQXvw?xKN78bY;P$#?+q*Z?wfnz<&AA~);+fE
zoa_T{SUPzB+IdsoRo`@8_3)?GJ#fJrFW3A&yp&$}x0@F~@Vd92ao^AXe&ru_f4Fwv
z&z?Nl{ruY}9r^V|%lG``p%tJ0<rNp)|IC{&y1)8Q@B4Ig{C)RrK0dW@)6;KSeE;!R
zU4Q@aOOE{Jp@*NiW#Pj^PrMeTz4q@uH*@dKW0yYncMtyY@ym|g|DoRVKKh?G|N5iv
zd-T|EfA#l&`t6T*9D4ie3m<s<FE4oZ+kY|V*paWyS$=HcSkJM)*m~ZNKcBt+SI<Oi
ze|>$=UB7;PZs*?Puh@C_TW7sx(<QSGZF=k6WAA+HOOC(uZ)QFI+s7|@?75$=x&Ddi
z*PQqCtKPKoKmI2F<bQlB|H~hq_r9G!xqj)|pZ-m};3q!`eqH_W$w$_{GI#8|7hQPW
zfmdCk`Tg4OMgH{M8)iTGf7pBXIH`(je{}8Y>YhDKgL|5R3`n$Q=oy=*4I;h>RyPec
zFKrMJMWI1NM0q5~_!g?09vlghb{vs-h&BjHd?0!djZxS<R3vJUDDh}iB&g9SdJ<p9
z2XnuxdhmCC_mgvf_kQkwzt68`de>{!TB}x7t$OUL+JFCB{amwhzFU3Vg<pTz|5)?x
z$353A?bZ9hisPeC-amHGs&!Xj)##m{pH9F0`GyVC^+OxZu3NO}?k>X~yQj<WyE-oo
zw?2H|MQ<Ee)Bl2t=<Ljq&Uc6R_nNln_8z@9ywc<C7w#xd`^O!(-e?ZBUDR;vub=+e
z@{z+A?wWMA|8$o<&kZ<k;>SO^ZQ7zA|LW`y7X;?Ndv?vbS<iJ}^!{_*SC_8oy?W&d
zC#}Bk?%q$YTiW~Xna?*Ip7rVA{qHXh?)Mi2=TCpF_oxe=y=1xnj?-)A0!OYtnEvkG
zr56o6_@y`e-Lq)_MJLF^Q+`=BZSTtS4?p{-5TAQl^*!>t<BZe3d;f+$ub20XjW7S^
zvQr;k5F$GM?A0qaS5Nf6zRvsT$5T-DbF=<0o^APfOxiuvFTJ|Un(2S9Ti0o;xxf3{
z<-_Oi^QTYhvg{-Zzj4O0p06+Jm58=?iY<GsW&W7Ak^`@wPsc5rO|uW)+Iis5p1(WN
zx=kFq>(}mq!#@d#nU4p;O`8IX4j!m$`Dj4kfju8bzB&8h#+D18Id0(6%Yv(Cz7tse
z{%3*g``7l~SapJP=&`qwySCg~b$00d6UHqI)Qo!ncOw>k@L~5OBUUFuja9w95AKa6
zKKNt$^JzQe&#on!v+J1pIeOv=)7~8-E+~#!<Q9K9o9L!doOg9e?aAsua7f&ocw_bU
z2QGIH9UF{)-09+{mp(dq>!{DpzsL+6JACam#}6(qe>_#rG>-Y~Tet6HM+%~DQuk8y
zp=ql#i`~_8$5EG-+4X0;=i<9X&B3R0uia8R=CwkvDU*_6x%$|(Vs~`tftH%#2ZOy@
z)8o~$)Wtvc{fm#^kX?O7?W{?ToY}LhKj+D=de(~#yO#b`tTUH(8yMU6<7u&%`z+cy
zAv$gQ?C5<o(OVjLLD9k=4RRZzCy)At==OH!o!Q;l?tOM^QCg{X+_|E@)V;Lf7u-?B
zK2}6e<2TWtq0A0kGy3}MUXQi(p0sz_b=8TM+d9oHoNqSl+37EREYN!O-ka~9y>LPE
zo`xQyHZR<B{^t|_aaMZYNqw#~<!b#*VQk`?=f`eJ1S6mSJ@exWk9%_5+*A84$UT|Q
z9JnW=>mFM_Nhcn?%rBjqE#2*1`1<1;=+FO{K~Mi9xyx*BJWoIIR*&?i+kZ7{=s&vc
ze*CZ5Kg+*ND@}N?YQwBsj%oQ*b5CCllDlu}SKRyFCCgqrl#HIXtCuq%J-&LttBpOb
z+ciEoG25*wG;78QS08F>7<?!#l<FEgn!j2sL>OAr5Z$}0A(3gFk#lb!gyAXn)?Vbg
zds;_pG2)gc5>K672sZ2=JfKO?h3g~YU?8neJNGK{(>}7GPE`+^PVuLTW8?eACx#Ke
zbQtY<)gHR##%!TFXC5ujX&5?kK|>-tr={nFnb_$PD=j@hoA++;Vw=44yura&sea4$
zUH7f3p5#4>?F)tK@$$i{Qu^M><t1xs=RErJ?Dp96D{~`%+pE6b38htFg_r)gCOGNo
znr@}Ws?nuB$4;Eod~!&)bqkrKh?=H`M2ol?nL3lt{EU7V`IFQ;+VXzCR&(HVy}`M?
zysYjx<qsNK`Yd;UROfn^_1Z}d4^UNTgHO4_9O<p{r|8nTS|`_}J-zmTm(3<hdM0j>
z?T!9DFZ|CpEZAYn=?6yTCwW=tDmR{(;<<G})uq0U${P|QQO1-n-_z?wT{2x%&(f^Y
zD)aegca%1l+vu?aS&}A-aeFV?T=OGUe$$Jjf8+E>f8B#7+}2gM)pV+!F}ia;`Ktlt
zk*if*?c*q_M;&)osfs>s75NwrtnjLgU)!z6E<Z%OHc3it>Wy6XMW`C4;mVl$2HJq(
zUjN>dQ};@uCWX^>M7aR~>4#sF(bQ1Dzy<Hfn@H<n2t)juMlubv^NI3FCSC50`6Tq0
z9!Jt2Vx&7PO7%mc#vd#adXVUqRoe4oiViI_w7X}ao7)YunG<v(2fCYzSVg-KOG;f`
z_do!A;SMtsz}T!SHlYZbu?ibBOFi>AT7~U#-5mX79rjb#VA&lv)~*4#@i1aR8!UUb
z(Yp!qeY`Q>i#X3g;}tx|fXV*3M0Cza;9QUczZ=+29&fnxe56J|3ZqZLc*Hoo+^~j3
zIYIjXD)LdRR3tFy@?1@hj+Y&wx_SY{FVg3Fkrt#CSfN)r<X#8|ICP!o4Z#bP9fsn;
zYLIv7N$D5LNuK412G^kjnSfH5pBvC@@*G7t@SVr4f}&bA<UQ<lM3wNVZz)CCk4KnG
zV+iO24VHJDTS&m?nmL%vngFR8cDd70noL3y49|$j<ugC8-b_d)c*=|zjNSf+!8qP=
z%K*ktQHYY1kQx&nK^OxA3=W<c2~<5pzCb*7j58L>d5B_O6!=QvD-!{ZuQz1sZ8FAT
zjl!_Evc6e@#0_4-RKgMO!-WAZSIvnK7bd(4PA(VbhHdbmU^#WjMqLgVl?dSh*(rRo
zjg8MtIGEFr_Zhs3sq*Tb!kE2cjAJmaMW#3(5D$cpd?>JP@q28uO!?vQehgiiFmgB>
z#>fv`DH!lJfU*uEA3{2$ZCZ|IIj~LFIt45%Nv47YIi_(`PM+HbLCgaTUgki~D0(mi
zgN@wA!-r%Yte0zS;SZ6ifyd+Y{KHxkhShM@O+f%tz5BbXAEeh0Kfz~yBD0CU+1mc?
zmp2{0<Ks8KxO(>k?Qh)m=OdqN`TpBGZ~Vg(6EjC%Th#jJx4)l%LHlb*K7D-R*&khf
zee2dEUktl$+gn$D`_+YSZ`^<V+ixFvZ}`-0uP(mft2f_l|8nk;caA(9oBGM5b58%_
zjrMJe`)!$i#S=r{`DD`A)4zE8%_Eb4*Z$6l&onLmWdA4ak57B^$Tk1D_5AsFe7g99
zMHk=z(UBup|7OcI3r?Qb{=vkTwtlr}<(9<{$FBLdTl?Y<uKwi6<SSag{ANJ^YaYD#
zrUhRu{ubZ)dE@RY=3RQ;x981U@YN0Y?#~tb+r~8VnVuW#apvc%MOSQj=Y~ezw)Xzq
zmRLczBnpuJz2w)|QcFyGIVCcry1V{T)P=AfWt8XcKIqjoG~wo$E+oBpn!JUzZnXAi
zg6_tZ+;wxj-a4BWXQf2ADea2KcGZp{-|ML%RZK@Cs7cW}5%aKFO*yq97&Ot4YQY*&
zX+>-GN-xxyZ3tm8L6lt?rP^ge7R0D^EwNFCXl4pE@2n7omg7LAQYu6VEwrNCIz>{&
zWvv<PQlYzN=djKUImuk&=v|HyBFOp8K^u?KCDOSn@X}$#Q3u-!KZ9Sz$fFK&v~{W<
z0{+(y)M1$a2|EX%jv<T}Y5rFR74L`Y|3A?D_X!<FXdea+K3gE>a8RX!W1ZKbS3q0k
zFqc=w16YN^S}VhA!^un#3#vkRDVxT$&{>F46%X^=5_G(zk|J5ugtss=z0d%xGZ_VK
ztvpPtc^w%<C~6Edj>$h>EhcXxWxTaWFAT+?mYEoZcL<uPiVj~rq=oX)h2TTKjuPV<
z07jZ&?7P>rV#>_~+%D~ONJw;zZZU`WBJ(M-MT2|-3ajm~g(gkj-URZ)+R;yU$H9XL
z!jQk$>0FX&sAEs)y^b*a0)K~MR#`wb${;n)P9TKWu7r>|R2XbFrhH%=AnNKNq5?WN
zM_^tL)j>XBJ!~=qZVg)agZLdEoEj4(fb(6LS_=&dtkRW0JgRxxCC#yf^dxy-4QCQO
zYGvR|f+egu4Ojy=l-QFJ77gZwQwQncQ?_hDnf>tLf3QQ6AWj1koD4q!-Z+Z0!Y+XF
zK_iaS%s=`JqY$ik*|DVtpACek!ytozcMxe95$)mB;8nxRCW^jp2O_Ypq#2>81<Jmh
z2Wtelg-AP0k<b#fElwzBnK0miJFFIxMgu1h@Wo~dOli=9!8UBjQwzum%Yq!j2GJ#q
z8Z8VeDlhG$-Z0kzw`4O5r^X*TTtJgFoNw@5UBOY{@kS2!<8a<R2LmFk`yd(_x2+M0
zvcO=d$PelRHvrK^7~oVD999iL()9|F5<kRi5oTNCr})8gMsH&BXb$X`g3%Fw><aR1
z;dc4zY7VeXp#ozmAy3*hISMciTN=h_fPs#{KaU{%7-aQag;)dP@HsByg_NZOCsN^E
ztc+t-FNnBOj@Sgklp+z;D3k)KG|6#zLI|pu76BgfDDFWGIog)D0rPAGm3bXmrI2|!
zNPw`f5eV&#CH}YtQG_xwaLUejfsEB80{qY56<MG|MpX^N!J!Mh8C>PjE;(<ZS`NpU
z7!R!>F$f9SEHY>rVXat$2Gw{AHE`j?MS?VQ<ls-|0020{6<2X6hco{OM@ATujb_m%
z5uQY(i;Cj7Ic;MY7%s~jFw`?)phJR6bTHllhLvj|g<Q&9m2l?gA<V8PVBY;h{6BXf
z(GLcMJJ9}M{}9KH{|ftGAdaT_pJ0FR{IggV$Nx9O9l-w^a}@7U`~Nvj1*-D=|AYU(
zr*<^PfRUr_f5sEX|1)zm%~6|S4E`mTZ=<LrLEW|^TCL%CMitQN(Hu}oczc7^&>BVZ
z4Yumb<pk9(B4hAI2Cy237(@Yc1SBhJYE;y!sSlbqb#^eOkt&$vu1UBpT=L76Q-?YR
zKvYxh@;+oX*k&h-rdlcXK#1J4VwM*5Vyc7?(<D<;Z1OHg%i)(ux`i^@PXa9tG;3~!
zDcdx%HNC+^FH~cdWaTD|qi%Dg$wzqdfQ>Lx84Uv1TH@qOz@$uD4Cerq&gndwF$5I#
zRZ!vOrYn79(+MpBxCBRhe+7<*f*9TGhzNRIiS5QLGzvgoP~8lJt$wgrxH{psYA}YE
z+SOX8ym%S83PGDE@G`L$_i{U4!Z8S>V8oHCENyEXtjYCRLo8P;AZvVbThKd0n}DW_
z%22(d9D}cpqSwTjKRN{pp$DG}22qGKBA^~U2nqS&@_hv&aj-Adb<of29BFV&h35)6
zgwhi9I9^!QBa<F21>blZR4h_N0ZIc7;}y&fWI$`fS(REf);mU{iva}(d>5p`aW;wK
zN@2DU4H#9ztlF%@1!kJGj{yv(FW63m@-=QXR2=e)Ly+7OqabI1mY^HEs}#`VP`bhQ
zstCDAXD}WYjzVH6#w4mw9p$KqEh@1x%Efb&A?VkHk-SgN;L><5e}!Z6WmH)7mWoUp
z*hl$7jsoAsO)f!^R-=5EC<&TQwf0ezp-@3UPJnc3(J3VGQ5|yHAR|oJiWG|=(^gKu
zkFy*|Kn{3<@q|{=ROFyZqvYcXl|W*wmB<LU=<sz9(&3M(q3ea5mO&^r1}Ca1rBMl@
z8vu@;51B<9a(#%_lVHPBQCS4r6f*p^IWAu>Dv(1AJJYsC;9E+nCh4^Rs-mA;4}<yg
zUiSVU^S_w{4u3{;=hKx;;fNUPCvN5relllxC?X_R--b**p3p(Mgt`L|#ek^aNkeil
zr%&4P0K2%hq7iCF<Q>46KmeS-ouxQDK=F=IFHYo<(o70T%nWiB@GFop1}J)9P~Zsi
zfrDDWhDDPBC=SOPrNI^MCDJAhg$)Q@KuoQh0wzErh}%3?+Sr9(MQg6Z)k;9byMSP@
ztylpninSg#3gZ>T=8D!wd4x(dngZv-3WdQOS{kGh90tEcK@pX~AAh)kkHB$Y0m*EZ
z0B&uF6uLVGWkl&pjE!*70U%xz4$Y-_tqO8NHmC>{jNM&83ps!vbO2Im$h`%~HQ7GL
zQ(#wvV*x0X3cOH+&|a-rSdqv#c-Cp+ITDxe?FZrHv|uEO-P+KvaC2{^KoZG03hOqE
z*1!pZ{B%W&Yc#uz;3thU22buK*rXiNNlL<nVk?oOpx+H(ITIEh=da3$g%QXVs~-c{
zBxe*MAnYNpRNWv*WSJ&H*k~3h47>soYEei;O<V%p<tTykpc-N@wqhEF(+)94n=5=E
zz}27zzvL%)1B8u&SEU(?Hr#0<9t^8`4b0f;_nV%mn#$%a!o_5Wu`)aSFXDzVvRsi;
z1quc|lG?{SI$|R8C;(f-4{L1xtjqAT+B#JMpUk8*@FAUpWgAUGGnqPcM-~DPCkRn+
zS+W~((H`KF%L>$;`U2!@2=Q5tM;MpyZ%#xW70Qd0ycTy*V^D&$0h(eepO^yc5z5x#
ztV6Z4i|Y|sSB%6&(^fPoun(4EVkvXRF`%a%=1m!tEe;2}25bJvJP%P|6Z#5oIYUR8
zT|v4WM9yqlK`)rJE|sy&P63J-L%0prYp^-g@Q@Cfn1^cMdbP>g{$Rz_&?v)MbOQ}(
z2WNDd0vo4=ivoETUJygFrD!GwXY#eSsz;W<Hm+zx%R<_OYsyG=0J3o;5C~Z$AX=ia
zR}ecu+@APe^<Y#UNhL%}LwOt$2Xd|t)gl40D9kbiY9skkDgw@y^}m8mr%|NsEDi8M
zB%wS`LP}OmHd9onf*uKC{)e$lt#rcqER6#R@GdmLF{fT@6dM_mTv<mc<*E|s=}~;w
z6AG?6m;qoMD?Az?-Ws6gf&j=+L$tXomoG*%<yy3MC%!Oi<7kxuoRYPhP@JMana>mo
z-ia|0H|!$~4kv72gjgvE-7fh(KoOc$4pGQkGQ}z+?JLBC=Vi*Fm_~SzM%ay4!7_@t
zq*tAd_<Y=mXuuQ5pX5p*lqhGl6qgntJMwe^YyHd;9>rx<aHv3v=T2xZMk_B@Mo<R-
zPK>-=Lg-pE8ZQ&l1~n|@l_1pWHd0v!Jqw0^4#@^eKgqSK!Gp>~i3B4;8VEap0Xyu4
znurex)hb@C&}KQyq5Ey)kTp^Vq8da6La1l8(6SA+2+hZhJ0lT9*nWnpmzF1|;0BPF
zLV@mvTj54E&62|QMC4<)Q8quj9Ap9<3Mx1$h^N1X6PtxfaY|#1PX<X*m8DnqB3*Js
zCt@9<7T`{IHHD*KTC}zJQ9SB0fUzdW8G=#DT6m<93n1Wf0e+^8C0o#`=nw>G)OWAU
z_s`g9SVbsUE&xvGX%2-u!RrjxSTvO9R>8UkC^@7BeG<^ZjlFp2KMg!=@I-Y2S(G#C
z6KO8ifB+ep!l+S#1d<<x<`j$w<qcp!DjQ-S>@@gk#2}e9=?(|-r*nX}LxFsf<G9GU
z7bThra40k$2eS}BPTOdxMlNaxyA-7XqGb#W?M-C{NGfzqfQ9k!BF?%Hf=&;Sr~^On
zFb8o6!r&f3%nyqec$e36*&zm_c7$VH6#3x{!*JPBCC&z9j6#}9-&=uj7yz6wVh}4@
z2l59wa-k}wgt`Rj^8*HRPaw##$XejzpfD;bECsy@1d4;Ww=}50I>A0}9+k|%Vo<{t
z*yKdIvVWL8FrchBUXw0y-Z8mII0))ODGe`2vI*3KSqA_X383MI(MBUNq8Lt*L1V_%
zk?<N!%w&iII%=B4A}hi>Oc|I7y<eq%qu+o|gU$iM%FpIqYg^wn>xd-Fi?e|jRr~}q
z31(M0a58=5gOxTLc#U<~hlJY$D$UF*s*r$XO`#$l>*liShcmZq6owSed9s2pz$=!F
z73I)ciD%NlDDmSa2cdOvhbn#)B0b>;<k%<4q4l=lOK<_&@)+k}7!8C4*vJJGk2NS;
z7+kNwmBm052=`=~(+bpL#3}p$fg{J#o5fC5K?(@;%S;@PiZPIv!UINnwH4`-qZ}J@
z^Z^xDF%zxD6$X&ndIGQw@reMeZc6UjfFH4Nb`Z5-EGA_`z%7$u4+9xkm5f>9Hk}4U
z0U74F3aT(%77nD`gn*mz8)e_D0+RVfCC9UZ(K`6SXE9IxkBV1<M@{k;G!r&8CB8o+
zhxTvZE@J4b$(Kox^(<E;G+xl=Ddcx>0+QK86~{3HkT0gbS!l#vlq^Gx9OkkDP?gNF
zigdLGpkt5-e?HQ2JJGmH)ltw<oCE+2pTr2HqPoW*pirAc7#rx@tU;ev&qTF@_U_`F
ztf+7rRib1N&4P8)sF!+sB?(t*au`~<DreKdV+mm*VXRYuhogs36kNC`UpGK!aciNF
zNh)B-0g}*CHHZQNYXuExFcR)Eei%_v3ARR-kpl>VS>gMUAW*5;3*#lDfQWNenPu2k
zrE*lIv=kC?3RBO}lx4OI$0gX-Gnrf%VigS|`tOIkBOOl}u!6xudTY3xHHavrG^7w_
zpqmruI~>g+OdhcnwLoRgCiiC;4yoiq=7iHuQUQMbj5r47`G_t#gnY7LAOse4T4UEW
zlgM!xzc**?0XRIZ(N_AXofWTREmo8L<E9eiB{@CMnXGM;$T?sD9;NZ>hLj<j%AjFe
zUJzHI4^eWbR^ZWI#Q*|^TO?i@8Mydtmrd`gM2TaC;&{ebgN?P;4G4H+mWruR;O4`M
zA;pB2S!$@O+y;@{bPU{qts7(F90RAuv&7vF!trknDB%`=-Qm-KiJ=Hwg8-wDZ;ruS
z?x^~QFTsS#7jWA1UP~9ifj1JWXl+Y|(<@8wC@CCU!;+nbyhz}I1zzF`mP%I21U@!^
z##*Rj40{ZZBEdc5iEseg5{sRGh}EE=JoKFvKk6$(;$aQ!8Tg^sf>;cKTt(?h+N?nm
zBoe^Sswmn*+JKJ26G<w@g%m1MLJJ6uvQot8WfikK$3StW=`#RCkq6+CoSyke@B?A>
zIfrTt_)DO>!1foL4@8-)@iM5(kfF^>4dRvHc`KO8V?bg{Fa$_8cHqKEGm1dR2R*Qf
zEOQA^Q8NVmBn-TqL*@m`C9q)}{7liRcV#%h8X0A7IHO1lG>kzo*8}mp@jX0*LdqS8
zgvLZHr41f1Sg?U8HR-H_C49}5L_-BJ5`!!n!>*PJETA<85oGmXfS{)>qX>pBq`c*g
zAq`d~z?^0`TCUBwrewLJ`vr1GRf++1z*KO63c-oygPRAm>*6XM_<$C<$5TL10D-QE
zfgF+626j={CaAbKgdadK*rbG~kFg)%45ln#4>1~n2BdAEm8y+p_B7&5PJ$vLIWZfB
zA0qII8x9FKbTA{)w&&IgHflTrA&U+ZVuL__peiVbHU&Y=;L<lPf8eME8YmnH9M!jC
zEV4>nMkH2^fXc}-55VLqfqYodoaIN-&}E1+_}NfgyND)e6#VF=xU7xgl!Zz(oIIRZ
zM<rYDIdC1a0H)D>b(rO_)5O}2OSUpxw9_BXtLt$F`+I0m=;x(fbw>c-Hl`$VBttgC
z&_z0-B+^6b9lWV(6c(X%p+iDAvczgsv#vsQ)(Ao+;aqYc84U3$1vfLM@H=X_EyHN3
zt!<Sd`wgp3m=4h@iwIc*t(X;R1r6#>g+qpgsSE}!?`|Xfsum9r#}j!nta~5_t>Fhd
zn!*weVb}|o4?xQg+?v_8d3AAnN6c|RoWQyk4AO)byIG!P0mvX6MZ(*%y08=7D({xC
z{40+2Z90D7(1BqBipz53o9rS+fg}b^7!FGX)koADTZw_kt}!8N9Lqqyb?~DeiFt^x
z7)pR?__5altyS@mfm47Q>MC45+z4fP;{ONZDEN&nLWF7jU=%+zI)x-oF2f)>@YX3s
zp%`=o$X1NPbOls-n+oY7NrPa}(w38o`d12_9!I0naoLv@k8%P6&f20CuaNMR-1;Do
zuaQ2Y(7MR*zt(nB1TSEtLQ0OVv^~?1;bsZ1FaUJ%fW+&K1|7H=V*_Uyqb)Q!7^OKA
z3V&?kj!fI}H3!;XNVBLM_#nG%){?T75HEm&K7tv{PIFP_F@?O<MEj&USlcsvUyi_5
zn_!f^_{Bg6?Eu+R{N&1j4n^Z>6dtI<tO=-$<sQYlgd9(5ib|tKD==YKyCF2&Vwpqa
z33ZSYfQ@{P%TfqvToegHG)AZ%OB)_WmNiHUTO*E4*>F8&EQTf08R5Ex^*oFyBBMql
zMjKG$j#b+AWX$3@KAefMRWT+3j96B}%C)T&+`KC^fWv~LYG^?QX^m&nNCmu{RsnUa
zQXR6$2}boC3L{#qFyK<`{bAZ&0uY;M3$(JsB|~M<Mh~nJn#Io+1(+=|+o<|Dn9E2y
z^nT?Xi5G*knvuE&AZ!#4tU*M81OuR;f-Lz8kC;1iaGx>*TI!HKY#v6j@hfLFm0}NA
zFt{zJ$Rr{90Qh4jQKby~Ra)Da903BxA-$VO;~+A{4EzD@SaCOKs8B|4$Qa88Y6gs>
zw!@dUS*xfWGDv|IISNfajrwaDL;&}{+IqOIprzpzPm<yYHv){n*0_rfQE)LK%L@;u
z*|6q78fbK2FmUrYTrz$(ir)k97oUNrl2#gHNg+-Xl{tcm*hqyGP-29^hlSDb@-`_L
z_!ZhFTpDz_>|Li)d{mE@@repwl~D^|0Jj<Y)Ib}^2-ydPy^JD~t1SbmL8IalMGa3G
z>W)|hj);fBlyBY45*tC<fWNX}BzQ?oXn>aPMxa~x5K+#8@uf$aI;sfs?oGB#AQkff
z!)*yhs|sT9YixiWhidLj(YLW-`Loy7&`J>eaA-S+o}z((JIxN0paQ${9bTD0?FDkp
z0@{Q?52X%T(psF0iWzMg0xJ9qjW7iY(D4RN5*iN}_#i!n#VYn#wWHyJ1Vm>$C!%rC
z35wU%m_J0ZG4^@XvUVS3OPjz2=)o{Cb+ih>znsC0<c^{vG-H8IMU$^IO1@JO6Z9X@
z|A5~yvO>EOhk}5y4^kb&%F2rXfpB2scN~aE98?3cg@Os(#~y18vSIYBv=cGL2Jkse
zs>+T;CxMsf!jH*jUAziP!>vKhp(;w@od<4wEf^;`rl3kt3>VbJDeH^fu8A(Iq04m_
zH?7mOEbe|Ss!2X;q~9kGqzY^4<#98|@r*>@LM@nk=i|F$m~fS_e_o-!Zp!<k(-4I0
zvkD1RmzAoF77Zl4(pg5i%rgF@I(NjR$nI*Ip(vO0yU;2{bXpl_(0iCDHVdSG+JcWa
z)uC3!f(rLprkxE^Uq{J06OU-36+<+-+AA{#_%q~uCVQ1}b%btd%R2f3O14NZlC7p-
z9@U#qcYZA?ByNfA(gyo-BGT+|GqFKMZ%z*T6{>=<_$Ct`N!7VI{g>ee3E3smfOb~h
zqMaZ2<f<lpJmra0t82m(e@G_kdh#egqSbrQInk<kOG8BJlAu}ddbt9U?$NmNkyF0c
z5MPG3ovqj_uQBlzuZHOslxJ-iP5IpsUfh%Mf)Vk0!rB%=f?f!xo1C~1ooW**olRo$
z2E%1JYdjocXDvOJfGpjvnCYZ-4Qg<cQ`2A?F7j${D=@gHzG{R<Da%|v-cvP#%eai<
zRon6$^xzJI0)PsZ`hw*+Tnnc|AJg`%gRc|S$0Xi7RiEnYNrQFwRnNR=ut66eo5^Rh
zl*vv|l+JA$ja)5>xESX5pn@{^JV5@gPP!+h6Z|gw09uDAr1feyLp6UDQs*&0QO?3a
zVV(BsrS#3n2GJ)BxL{UdWLb|fl*wVC-Hb!UZlTe|B3`HLpz;(~_rexbRc=!{zSDhT
zB6!MFlUnYh^%d)ecwt>j0YznW_Nq&)+g`|8I|}N=>{eAg(8c>@Df}h)#$gX!0B)f4
zFg&jJYU0=d6}qZSxgL|kiQ2j#xj&<Q&FK24G~)uvC`EmRX=D;7l_=~Kg2+^_hzQ|)
za&PVSx!rMGejgMO<0!Yv)iqwAp;WJ3w-ms@3D*bX!by;F>&Hkhw*z;|mBLCA-30-<
zG2@!eu^0GE=8!YNZf%YZZY{rb_ZIcm=QG~?<D4ly3;VWge(CL%>u<er&eY<<IdAUx
zsCCP;Zx7x)a@b8{ca|?7``kzSw!XN3?UrXhpI5zS*n-TSuP5HU>&3rsEp9z=&e*5t
zjXr1Zo2@rr^hTlWNaMWeTZ5O6y=v-?rRk~pn~%iiRUhd;ullOX_Z)ZC?{|a_uNzQ(
z<PiL$-xRaP?h$i0Kip~fy2fK~96xpPtkF{^zPu%N@o`($b-r=lh_f<triMqYc>I{F
zx2*rk(-*%m=F0I?&pz0?b^QLjHU}4VzI^PkA79X^>GhSdm91N@JUrkhW1qV9@_v){
zt!zy1+j6CU{qSFMe(N45O24@>wq@xJOBem+%|A~2>YKAx4;}u8tN(4m_Q{*tpS`-R
z{n;&t&v^drjTiYxZd$zO$Z73+W<T+S8NPDCIYU3$wrBDq+kSuKcN_Kav)d<5TR)BT
zgKyLPm5;1gbl+F<$hJ?resj<7e{^-1cP75P^Az#X{qt^l<H3{j(;m5J>GkH6u18j$
z*!0oL=_l;@%L#?>!HvOz#Sf|$J@=>JqBRS8%zWgD<M00HlZ&^0^uc-8@AyOT@B@uw
zr!BibaQw1M0%xo^>-^zwEJ(ini%Z8J`Q?Q1hgV!SdfdMrGqTI~_tX#k^;Bp0Qwx$?
z-{^hG+ke^Sz5V9my5oL#LDCEv{tM3U-qUcF<n?}Iw|sQQbH_dL&E!S*-nDOYeE80*
zpLitn-15oI-FI&*-nZk1oA<XKa=tw6o&3_v-&r#I-?pW%zWvVXt3N!`ZTRr`%$J3a
zw=W7!4`1}a%5mfFy*o1S_Qhk4JKP>@x_jrHTed#<r}?2%QY#+(QD|fD*ex5IF1}^>
z#&%~>`IH_j3TIV4u;NEm%L-Lp<{$jCGr#$HXL$2hfobIvy3YQk({1D26VBcG(SixX
z4{oj6y5}-|_Ofd_U04{}Y4-i=y7dg5=x%+aPv@8Koi~2#1C2VfYW&E7zdhaw|N3~R
z@0JrYE6OLGwY71vIr8jcXUfylN1_{9!RJmt?t}%suX~?0eB~9*$34|=d#~0mFI=?$
zoXG5}Z}6}F{G;Mfwd1+akihf9A0Hx)d-Sb6H{O0k_xjTrdeKcAgVT<=hq^!c%$`uM
z8+Xipwvmq8`J%qC`EaUxaife>?TlP>bE|v(vW1be!;RtL_m35GA3QNI<=Q_4E}HN+
zxu~#!rX5@?GHcV}E7wj4_j>5l>i9#)SD*fyb2=So&Zq9n#*lbmR&d$9F9z>k@_jP0
zthXHZi;>R!4YNiJ??0F1y(6gh!4Xcw?ln&LUFqb@(c9^b2bMaCU(F8=dFC9=d6QQX
zt-Sr5<d&08q(!NL6KX@pWM%4{<wSp2G5hpzdejiHBGfQq>9o21c1?bCh_3y^J7Ut`
zz71{hj+Iwm@JJ@re|)FG>LLm~deQc#=U(02z5I4WtXbhstKL{0sk$o?3VUuL5Olk5
zzqMuf&0R#KrYamibwnUiwInjUFqC?&4GQ<88WFy?cesCXabSM_7$@8^-92vY0vh#T
zui(o|zN^}E?^}+${G1Wv3iF-eYF=Pqd5%aun8P;BPL9}>tZ(qwsQ!g<v`2-4*?gD!
z?3yd^jg~9*rK527bj{_?%0Z)@yUh8{U-w>6wfmJ{%_0nJK2}8g2HsiNGwjh@9vf3^
z`6TT-&&~R`3pf4s0#m+WbZP&%K;g41+_OsCQ*zUjC*{99`J`jz^0jTP+x5=1R9`rB
zV)CrWx>ddm?(?w$YkN92u}$Zn_Ql%OJEDbddd`}k`!DZU_lNL-<vUJa-e*TT|DiAc
zmJ77Ju*%=C?z0^m3)j9Ji|-89?Y=i#=l`3(@cm?9&axAhWS?r3`hk;h)z65t(yKbt
z?o)dQUzz$ZRWo*;wBp*Y2hhSNn?unN>m$9IFY7rbhTCPgXS@Dv=}Cdy-$!E_^-A5Q
z*ngnxDrbrtYVK@(V9v>_#>Dli*c9z{&;3ge8uMGDFqCM@?iJ<hbLXfR8VucWEHzzw
zQh10;wH=I5p)fwVtawKK*#4Vd-=*Z>X3rJ7YQ59(Mb=*1qxWv!F7AKn`6+ELjk<ec
ze}7sm=66}+`;?FS>W_5R@>!d9FMsIC-OE-k^e;*{&yS;jY<JUtc_q7N#?FPC<S#X?
zBr=**f|jHcy`#H&iK={cRp%c0<jtPJfHhT5-8(mvtnMuT6D6g^%;035?3P~M$E|jq
zwmNh}q*pXv<YRGgB6T+Vu(e=sF7i+*f2<r&g+#>Z@>!=qCOx)zt5=_o#gcSsX>V?P
z+u7(@v5z^HF;v=}Bkz{qq&<msF@xQ#Yf8RXuZszz^4j+@GFS4^@wRx?bH>Q}4T8I2
zTH8mey_!O9E+hSn<E>F?T-)(tS$QR?R+SR|ljs=dVlZ{OBO4O|T9f!OE!#tpF!nX!
ztp`pkhGZg1lzg_Amm0l1fj0zR8Pm!ThDC$1Sf3byZ&YIc!hZn#UPlJXn7od0@~R0t
zu;gEFL#U!`9y^tc2WGkv7^FTq;45bk7Qqi+o=Ul-DPy#9y$|cLNmjcQ#9YB)*mxZ4
zq;9q59-9Ym8e3_LN$nbp*NjXodBG(=E@cogj>gDIlPn(~xvs3S`3ie8%1C#rtAq8s
ziBFbF?AS4P38D=^m)J+KM5|Z-D{{-b!Ksgdd?}z*4)f*hiY7sRi7pr`Bwflw2E2&W
z6r)?a!?~dWa>H!PO=B{siF}%ZP~tPUN(~wv!#$3q+@`YNO)BVnJjK&rsg<bhKa-Lf
z%yNt{c>hIm(;RZw0fsk6Bj?ppQ`Hdob3~o6mMZl))uP4`u>cn4>YS@IXzX@r63e4m
zV>-ZJUMGn!nV56{tD?q@1Ju<yPywvbBozVx1_vf6z7c7_*8;}FyvfVrx_BJt&Ds|U
zJTe5G3^FG%7KIzlnjxJS)@1twCF6vVWGZKFQ7B}CF+juOI(|PGmxr>r<Hp+nNfICW
z?2FXMWCspcSWt~MJA*GEQ<B0RF*z)O8yg8=1_vZ&DhL8c@GuVJu}EBg<nS}RSjIJ}
z8gZOT<LSe$%!Mr;_TZBbC}(bu@EK);@UTV^u>HhMVe6T(0X}AlfB`pNju{FdG=7u^
zDq0*s#>6l;Mx-IFU|}X=J-iBQuqF;3Jbo9#FsQ4f@FS$J7%K<tKBqDX#iF%81<A4;
zAXJ1z6s3?X4=*P(_^}*VPLKm=aDcsx)&X>#Nmk<VH1_94U?sq3&IW`Wc-e?wKaZzL
zV3|%6Qqq5Z^Zl6pU%kDJvWxAR+mC<u{rtPXoBH6^^N0Uw!PHN#KJwIe^WT20y?x8i
zzrFLjZ?~O$Wb2XnTkmN9Wa9*!xm~<%@;gV`=kMSD&3jM(`-g8GxuSh)`y*d2*#Gu7
zpB$R-?Q1vndtz$)#y_@yi8Hs~P5u77dDlPj#yjs%{LPntx?$VEfB*jC@B4l={m9md
z592KC<HKLTck{ma>YO9rz4_ZC(-;4G-tV8d=A{SP&$;`a_5nxQKkfF(*sso=_aJa@
zU9foQ)b?)epWc7|rw?3n!=IixJYeH>+b&-4x38wZ^T^fx-u(WY^*3JE{?4cUz{}xw
z?0UraFb`m@dkN0mKC-Cax`i4m8SctuanE265iL9@3Wk0vYJ(B#Pn3Fq#EzDnY>m|P
z@drw5|NUI=C^UpjM68#?TuP^V=^aJo=(JFJk{5sRsycVfu#D#)5X+2?E-Q}m)R-%=
z{GJfYsq8&4a_Am>TNE3WrGHzk)VJgFCD=T0oThQBL~s^%C8n!td(4`Qy<{~`DAOF3
zGIX-j)E%EPZ7GQ5t`{{mPB&Q_pD=1ja^j?XUg$tLxTXhnnmI&^E>DKMOv@U5%Q4Hw
zPl?gEaO^x=&Ya&f=MW7pdt;FQiqWtHJC9ZccK_c@CF;Kc;Fka28;z(61ga)itco#5
z9kBm7Uj1Jntn;6Nd6x4I$RFI63?BB(?Qe-R{!EAhIfE9-??B$jU~ZXfQAUWg>Lea$
zaljl}#bm4xkfTK{Rs_(uwJE5F5bwLqVA`4`C>P0j!G-a7=7hVRoH4?yHJE-Y-Z`Sf
z3hOqQJyUN*a|D52`bwut%S~>)5SRO66oN*sG;1YvdK`8)Ko!HJ%2Uv>`0<z^MX@5V
z`y`8?AtvKkjKUV95-+5dg*SU7)iv|ELaYL>DPwIT2ViJIplKMj#)%Q;>V5)PoC57m
zDAOvj>IY>bp@f3Dl;W)ovNoWR7b7yu)3vo3yB;!03x%a-Z8Vmr>s&wLiLeZ@=7P?{
z6}>g}ylM%PTZbZ(rAeMh_013{*DA1(ZP3tLV4|ocNOcEKiUj-`<r}OC$XH9rq_G5S
zjOTf&Q=KH1S!P2RWuU|o9r4Pdq;Zw&yNxZo2fsu(3Q4Dd#=yPF1l^RQiy)w&;0^aU
zr`B`*4Wzqktu)lDLfKIOOIkP|4fYXIsef36K~Dx64&u>Q<&BU{j<JF%5mP85*ya#!
zt`JobeB7C91ksONA2h>ZIAIjrU;r-_z;VV+xdqBgjkMJY>>3aiN#iB8&3ghuaa}Dy
zflScRohj`VfB;~!H<$z0If@wD)5Ow7196-K08S`74GVl5ML|$Q_VDVJ!z9E9H%>oU
zRHT6lxk5NepB(T2FMi6Oz!7lpLng2kV~pK}3DUmewRC|#AIUUu11Rl;3Ko{TRCFy!
zr9u@Es<flrngd)R$Q(oj_%U$|!En3@ge9&HBJzRB*-gEkMLd#eZP<Zv4Y0Xrccn_Z
z90zd@HiFZsGU5$6ju;6?DOa%dA=3cr7l0!r4T3p4RG-5`7EQT@@J&HJsepQu#XDer
zNupx9$$)qR7a4emQyMs1ENu@LcpwC!SV(;hBDE0GQ7SG4)^zdX9MCL)z!K3QpaqzN
z-x#HAn->@|ppGF_XsuBM$d_^GRkTa;9Y+Bz8W#yFlR-L*3F@Y)q0F8DIViuD@dflQ
z3US)%90OubF3Ky_ipN@p!aAA(3s}kxfggV5gkBl-2??NEz%AGUBZQ$_wKfLvLP5?X
z{Sub0TrWie`U==<9UU;bM%keWrH~OG!Z?b;%7L4WFv<rNh)fZ+Ve1(Oa@NZVjgr67
z;%vgZF4DFHbd5a|^2S#HGI<0;a|m#PShTy!kOX|dhc_@LjGb=aJSad$gD%os&wL^Q
z08);lsTbm43|l}4OH)@$Yp&zK%<UU|$2Enu!D2b1)_7+KF0mm-W(=ZXTuYoIv)Fg5
z5V8ZW-4bMM3$05rjFP=@7*X3I$*9{xC{z--w-E!P6ogpgjpWfCxjq9A$^*_|egeT_
zHjA@y5FB=$!Do%;*B4-q+0B!q0IiYzN@a0Tibg}T8LDl;t)~#R&>FEw0FglY$eLkd
zfPjUU)R2~Epj?!r+@j)YT|?r>$PUOFh>*c7y*L`YBJ!c@OA(9)A!V9{MhF0^whXCN
zwK3>8_&J$ShR!2VR!V6FKTJ_-Tz$!-&=|Jbqx3ZM(EuhTr{OapTmK3;#hC*ho)45b
zcRmN!pcZ3CkFv#Cw-6+KjX8qhS57VvbVo%6D#Rm8WPI2fPT;|ao6H)LB?PGociO-W
z{A?@EpUlI7NC$2WvSg4Hks6T<B=F4&a1uu<#=tt0^*h?0!V`%Mnu<VV&VCXKvWt-(
zO;Lu4;)j;QOlEbKn<!(zpv$61Jx45VGGQoewL%L+kLt4zMuRmUHdB>JI9y@yL=szu
z3Je<!pFs<EjLz67q46#Nfm{w21y^Nj_%o(xTlLCR`~VlWs#ACDYjDWJr9Z9$R)^|I
z;SVOxFVd5?V3|Bg&A~~If)QwnuD8o*2%T(eP+EhAV%EVH)#3+7jXm@8!L!U2c4Q|E
zA3O4F8QS>&Ks!;j;8V~}Np*?V2-2lU7ck`rxFMP%wGaIG!#A*i`!?tv@C$Gq!2Uuy
zP%l-$$@*Z=Oc9Jymr!3cMqA**<5$@V90nWE&~B3w@tE_W6{4n#tVG8V$a)5Ka;9h6
zur80`h>Nxdqp}k5sG<>Ra8J}A7rS@iZ;4Yxj|lrMC>!qG(Js?Ql-4;&B4qVWv_H(B
zCxB23wv9m#;;;ii(_!fvY%F!Gc!FRJMuUA=y|k>$-y(K%MTRjagZ~0-E*NMG42W>x
z%h>_W94bcBC_B92brn9ztVj#g4+n#DD9^N0r&_tOO325cnj!*VZnd&?FHX2Dwmy!n
z1DXsJKc<rqPK5U##?(bW(!6O0FWJD_`4loBU`Ujp{Bm*<!rf$nMl?|xB+JBgvDTDr
zE@DIB>Hm8cGuArFuJS35&j5C&&?|BBX4K&BxN%}-E<A`-=P1`BfztIF3Zllr`;>Y|
zXR~x_GHEbqlxRMZ=<gdK2aW26tWQHVQ&@n^o0?V9&B`gBXmxB~Q{#wHJzBJ9Y6Dn)
z*j`TyvA2-Ipo!FewTU_-`a)Do?Da2U@R;a=>8aOha3!(u697t>w3Ew_zRh4@6QgUN
zN0*8#Q9T3gZep4Ah(6R<2D3<qn$&$S8W1VpJy7GM`v4!UZ6!f>k$Ff571+)x2m7C~
zV;RY@RYS~`QW>3%Iw8PbfVP!K&94<*l#?eKJ3^=!bfF1{POs5)6*zUFMUg<!bn<Xs
zn*8OzkqWOZZ$Twc`H0&<BEVq277&bZlLTR5E0Rw}L*_A4Mi1agu?jFHJ);xaCt(z*
zkt*aeP2{3Wj%e|(iSi14T7yE-7tr7}x45*#XJmn&!MGkO1S3~4cCgM41NF_ekDq1;
z^j_A9Qmv!|V;lp6x+j%&p`jtEW_WV5RujQ(>~KRdPEG-kRbJWJ{6G<q6o&bL54aJ}
zv}J`CH_s8ao5JQ~RtHQ_09Og@9!SCKpb<a`*p!Vxfd(&d4+0_#(BUj6mDz`MgfUXJ
zW+$UDLMs4B4L3{{KLi^zGzIo0!qFqKk@m@L+JHHfk};&X<nwC{5I|EYJRk-I9&lkE
zc6uS61<YiCD`72T$F}U`!el<J)7D~k5}39^S6p_kVRjh3Mif3)7i2c786$FGG*iTZ
zBZ>aWmXcw#3h)7o7o$i*Uf8e_R_xER4+sE+Ds2z}9VJ<E1_L9mL?bZ_M%J|j(F~?p
zj}tX;5f~<Jk@6KQ0&$ESbRfJGMmZrku#U-^5|J51c)LKkfik-Rs~C>^-MF>+KoxVw
z3S4nYbfVg58;9z|qbu}WdFU_4%2qQW+s^`o<9NynBbh5?0oNlqOauSc02D0Oh`NT*
zU=A}vv$6#H4v8cqLn?<Yc8du5NGk}9>?;JIW&+qDcLew9BwI`X9ykE5L7wqAh(HkX
zK-2;o40y_rKDPi5Ab|p7H!C$d${3d|3=__3YfAuiVN?~PVi>}s_9KI$Y~gT05laf;
z8d%XaAh+xW3t$NqoNI*?^^{2>DuG`WNM}%Ba9R#EgCjlADLi2m##D$$*P(GoXS^?C
zv<5|iOxTQeguvoVR*cZ9(qhbi4b2d+RaoPS0Sq=4&loor!17>G0meS0uXuGlOf#4-
zz$2~F6?tm*X&Yu?b)IAKb8N7-f`&JqMc$K=D=^q=fKr1pM)(h`azVjx7_hUg4X9Z}
zh|w5jz(YPHr^|ptTQ|%M;tV!haU9FbFvf~^<i;}A%nXMk2J9*Z03`CsI%vD6BkbR;
z35E}ZYq$*Dc|u1B#Py(RV28jvER+F~qBUEAF%ruiDRhNMfku`@2n^H$0$>|FG;k@{
zFkUO@X!05wP@B*v01%x8H)7o(2ZUJ`DqaPmr0|0+ts}*_ttmlv%m5oc9ZeI7-nFC^
zO1u)&wLo<-+cHo=fijs_mM;fstixw*#v2YX-rzvc04XMJ@bfg}Z4~q~M#GR`B^wqF
zP#Tqyf%sv=NGWS8a<rou7e^Xc?6gK(0Hg&70xXx((t<|AcvUOI_$q`LB0(i%&u-Ne
zkjfAyqLgDKj<kv4Vxv7O!}9RqL`JUQwq-@&(;9q#5VqFr0U4Ahp%5Ejr6|FnIsu(v
z;9!-<B2Wx?G&wb)O7eFzdozH~502ApL!T>H#;_aw8O~aqQzArhJleei@4&}?j2bcA
zadPYe3S<Ki7&l^ETL~frS@dk>_yK(Qp{NYInRfvoN5Q2PsvTpn#@g6bq%AQ7DK0~|
z9)Pj}gLYtbH83Cs|46IgvBts}&A6=}`if)O7_K8qS-fZm7?RW}MBB<`@hIj|1CkpK
zT+(n^MODK3z_K+G*ez}Z7|<@^2_il#KQRy>J7ah-2W<KLWU*D);Rpb8_6Hgpg#Z|2
z7xlBlKuAbnjZmWE&^xReHY&#`D#ld!<i-mMOu*oWq<M)NCNgkimX9EfANF!4VWG}J
zgLR;=JVA?T0d-ah11RJj(j)-ProoP1csW>gFa@2%Q<sX5bD2QdP;3q<<O=_Ib7%8z
z48=f!my`seG!>aSjW$w|4cOIMXt3s1P;)9~Nnt2v;L&k-*f=~o25t#m2MQS40~-e8
z3N;-+o@;ah58whg(GwBH*QGF;;|8QU80A=XlxrZ-0AffO^}_>h%^pjD%hG=o4+SA0
z1V)34q$OkXzzic#u(%Q>ID_ouwp=j)4dg0G(c8ml&Ok?iLK+*yPgDV4Xi!GQWB^4(
z+ZE60kR|*u5Tm@ZR59*mKX4nVJ8)HC?51KgaqxtBJCN~^j?=r;Xc&Z}Y+??E;Wo&$
zY~8c^6(dO$KdOj9x(cfbwED&X$Eo2~X*@9jw7tDTYFw~Ukx2!BcgY)!`XPl30Tzn6
z57J7cvIYz=IP{aQ1fU>QGX)uwHNJhS3Yf)NNsAD40)%KAXf$RuhTV!dqa6gWwUCY)
zt~LOvoZp&!JNu9rfQrjVah%~GHfVxcvqM`YK|*7!f}CJT$Ds(;AR&#FU@a;#9W^Ob
za3Gb2yJ*4jNXA4`M<Gr%hHy|4S>|YE1%w4U(AT*8gHgr8>}A0za;%HR3zdz8@VaF@
zI2=ZUKt{9c7L=QAU>CpOM%7`XG(VUIOoCe;jN(DJW|zUgBE@JG!YQe_Fcf-^qJ-^e
z3xX)7AA_wqiA{?*&71M9F_q*2q*(`YSq{`3CTz6E6N~c%U5%=X`#%(EC2Tce03(qO
z70$YCc_|r3I8ZPSC_qgC%CS(ej_d%IlX__JNQj&rx3@wFg~onG26l(xc5C}mmY4>G
zJjs?0>G@h>jV4!73s^3)#2DV#$&khED){k3L0Ep#2(fXBVocEl(eY6dUzBCeNgB^#
z+ntbS3r4glB*H)%RRK0|!FItkn-rtqm*$FnHb<66c(~CUfJ)2)Z9^n+s?Sg`7>H}@
z0Gq%BEQ$rCplT}(IN1?vEz2_!Ifmhqges{u(s>yqw5F@A*a|QhFCvcu$gB|}W7%RA
zA}T?6R<a0(1U}#d3t?7u8VqnCibH5bz-fzvog9O3h#sgc22cH}3}=VY#^P$Ql*<4%
z{4XUQE*H8@t*B)q$~nQkFdIE8Qbc<c*kNruqb$N~7fm>G$yGXRV1cZ|w0SL58o(>+
zFota;NNIvxDh5)5zyv@$0yrCfg?Uzh?1kZ_0j0H8+>SVHnSx9N#!lV<0k{;rPDnEY
z4q?5;%1Xk8a9iBCpOKwF3%Z2MMvTFvKqClZ;(}B7brhgQ&z&VH$1|`11R9VxU@Z>C
zPgH@V<^WE|{LW&qg2f0S@LqSMq6U870F&T*`(VHvArsbEe1@G2$&zCwt4MP{j4+Md
z3BGO^M&XC0Lja~3m~lcZ!p2$p8X?SwDgZWZF{;X$p0{2`jOqC0VR!Hd1UB5DXRqWP
zjUOJn+9l!GC4?}rE%l<%A!Lxf9YncBS{|1oKqqC^>TBp4aDjoMUDb&*00e_TZ8b53
zh-et(z;hrQ4f(NriDLNKimb7F2@Q-J5hW#!=2(Rsp(?-yWdL#lwGk++BHM1`F(!e{
zXKoNp%2;Wn0}2QK4W|0=gQ7*D9V=_}=eEn&U;(iJ6tp}ED4k_$T(007+-JGga3aWG
zD^ioe9pZ?LM|V2HO~J=1lFd(n2Kbc8Suen%po6q2f(pm%258Za;+mrsiG{F$i4Bjp
zNzXvH?eVLrdf?$WVaOmHYf@$SHGY-$0oH)FVrsa(J`FcSLfRmL8Fy8S=>P(W3NQkY
zo*xM6Fa|bHSbjiPiQ`TYhT#~S6zmiDW6SUpYTm}fgMS!12C{AgI8^{n19@PGSUd`1
z;WWc=d+3mw<^muJS!@!)$Ojh(dO1s5lQd8++6vH?GfJeATUcZ?5-N7F(Pe(%$K1k5
z%L^O|KRmH1kPY{<cqX~<r7d2?5Lj_!T?4oR9t4?ag=Y?KgCAJrKn!+KcfqMpjwQmu
zwjLv?vNR!5u+OwWpDhG)3Rng%I84Vvoo;~-F}iXNWcz-2>nrfL5xS*hvL}`0Z3s1U
z@F>;D0N%BXqoU#c5w3R$t6|Y#umpzYg=_mYr3|iY&(om2PCa=$liaYQnFK{jhz=!y
z1bT&b;f;yWwPTEy)IeR;j$FTzb4i-YHPxLn+{~7^ZRr0CdmZYdOn)kv5!tMRaI8IG
zzU+oXe+~S_G+`eE1!+yLNrUaI5h+3qGzBrn4N%_;L5|i$=b}T1=pbl0lwBV4Pd8V&
zL46)Z>aWs5w|?Y#*q6~q@6rkIud0O;+Ca;K*%_nV!n?Rj2`7_QHJC1SN$AGgm>-JA
zi>O1l(Hx8>Am${{*SluFsP}F&)kaSUnYon8CLCu<EZ?ahnwX1-x6r}h*oiy$DU6*(
z#OpRe3NIPMH~f$<TXwQ<LC0(DfH&^aD;hcoTYnRL6G9UEDYc7r%ud-F6N4BP5>-)}
zPSTqo0#7Bpy@cCQQC;xn^}w};CS{0<=o?jzB6(Gq8O7!Y*+P<;;WIz`&V$^H*VD!Q
zZ$`%=p+>y=G;}hmVFXL6D9y7-zQQORY9SGCy$wg-(FRSG@NnOK41+4Pm10amzf5`5
zcsel&s>A6D&N{g!8$-67I=>j9H12oX<bh-8t0?txLxt+nnq)e<X@nd<f|NUx#1IpR
z?YS)(A{3Fqh)cbjY#8H(vcZCPI<9*Sp}r<rF-KxfMg@hVqY{f?$+Q!tQ{$#gzQlD6
zdPf6FXo4#XxYSrv`g1?hle#4`-OR`umCV#>!&UtlqZ-sgANPpGYE{ffGt}Dg)|crQ
zvM6gYWyZa7E?!y5V@87Ig6@Z_^T=z~eJPRb{MQuvrS6?-%?zz3&T5OtO3*`j403Z$
zwKs^wXjvb0cL~zC{yrh^tIn8Y2qoK}8g)%-pmv7rRYPf*P}o{iTRT|xR=XgvHgKKP
z^-H6<pjP>YU2T-Z+Ncw)X%ni9tpl4jgt+GtF;o9pE0&hL7Q)@V19QK>ySsU)`E))L
za#xBd_wJjccCTw1zk72m^3&aK)@I%vEBwum4=^j%4cKt`RC(&pUsz=JZ5gs_?UwYM
zOQ)uuTtD_gZ{I0HCvDo&IPB6F!e2LjI5zwDwyP%p{gkV|TYveY4JRycvwv)Dl6za5
zhQ;RfTfJ^x`0EK1n_fD%b@s#S=Z$}H^MHO=oqu7|e=eCA`uEKP+|^&iPP{QWH9F&x
z3q|$kjeXv_^91&XFHasD9sPdn%=5Mkx$LG7$DTds(y=G)o;2jl$6L4bf9A5$;rOMa
zuivn5<xQ9E`!fBLFXl|$&{*9`wQiB)_qEC&ukX|8$$6J|y7tYL@|$Px3H#6A6XE<$
zeiZ}K_ZFWs@ZI*v;Xk+6efR1jch9r!)i1AE5ZZXSU9Wrjne^5tjwJei@%^cL8t0Gx
zYyQ*D8+R`L?biDj|L*B$+rv*cw|DyP<L{6C?#1ut-q<|-+W9w6zwXn*;->G4i~A4X
zwRqsLSI-!5$-CR+TWg+)EiNv;;<8bTd%yRmuTJ~^PuC1?Z(H2Z-i+US@AUcp(2*0a
znb6*};E#(>c>n$B^S*fh%(-X2x6L`_y?X{N{^L8BU%LOyz*m#D4f%A^f?+4`SX@0|
z$C=enY@dG0Bgu=ey6M$vdcpo_<IjBeO!tX*&kRgIcxLdtgWEcPzhnCGpXkLu+Pd=|
zG9TVUoZq>Z5j}L^%+QASZaSxB(-HTn*N?c%*PJL@?wDU)-uaANJK}rwbn}g;^}qAR
zLCf>ooE2-fjeMwi@!*HVqG9u$_AbM>ZwqfN-!yCM!SDM#J!{%e9(r&3u!mRP)PHMX
zajgH|8wL#YZ#ePa%`*+t4?NQ_FSuCFi!B~^|Lkk}eRcj<eZE-J9{$hz_Ruqj7M*d*
zdy7tM+`hPL<AiNp4?TZR-zT2Gr}N1l96$6Yht5<#f9%YrQ|8_?>zP>#1|ORAhry?q
z>ETljF79$`@~wr<$+vn3|2Qo;a>(0G^P1!39rqqj=lM@{o_^r;AS6|F^N8tHhl|6}
zRBr0T=VHcP2Zj0UqEY71RJnFnPg+(yJ>373Kj@Zc&xwTnsnzaF-yYMyd0M2r>pXYu
zf!8kY|M5MM{`XxpXXSa*X0CiK5_tONV@3~bzJ9<^b8h_V{CRzbt(l&gm3}^#IrOj^
zv+KG6!`5FPT$jIT=x5un88&l!@A&7bK>R0nHlNYExc(<sH2+7_=X70Y(0kYPnfJ={
zJ}3J3^uBauZNDLhes^8Xf#0cfbB_dmdTCXkNVc(-_MZ?Fp+{-fq3d(wlkJ&fM&6mZ
zbLWp_+su<`vVTvPvp+w+)3o=G4RqGWLZ3b@IB&&Y5T$n<SGBZ!SEjk;F82>~Iz6Bk
zJ1g?X<RZ<-cHZcJ8(8+jQ{nq^>85q*TI&1mTe9zgTiv2r9VpVR;&Aa8cldqhU?C*i
zIK(;c%8lzU?z6Qp4KMKrWHfyp97s0|7)IaH-2Bf^{W?Em;QaJXI&z?j>dmFW8Rn;T
z_c_;{euQr7d6|AE_TGePr=8N&cI*kEk;epP9Xla8ql@~N_wEm$l>RCb73;~1db4I9
zda7^JfivRW%=wXKd8gYn;SM=eH&gA}=_}If{`Hu1lK)y=rKd+eRz%-_fwo!mcBgdf
z^d*^tXF2Yn!lj9p{INtdCSNsj^J~wh58b@pZ!-r*mdvY0yw$c{EZB@gLytZm)+_(k
zMXr3(ZEN#Psf}9x?4MM%ch^rtW7hv$UCS%Iy%+A7mwf4tPez`z`7*cHU;f42UA#}f
zbXz&IptRPVamNR4pIyCF{MEX^s{K6&|FyMCbk3pCm*k%vJ+;Ss_p0B{dZK2zPw{`>
zUgM7OE;#$ziKEADdhVK;`CXUJZ5T2yK4fAab@h(l^xL@~Ss5Cr@n&DsRep5kPckn}
z8Kjp?sgD(^PvHDz4&lA>Y+X~F8S7ei;Q1@-1YUcm%_!urTfQ{%<K`5t4(6y7^@BxI
zBGD{KG|H6dT}+Rl?R~sj=j-TFo!xL(iOlNlpM{Lv6rxLiR=ey_LocU!-pC*gNCww5
zMY<n=o-f5l-{BohHomf!dN&`!ib}5lO{jB4_ns79(xva~o2t)qO!cKpat+-Ahla}4
zZ5a2ICd3`lW1P^{qe{*fGfScMy8g2MO-(vJa90s|EB)q#5eoyyi`?XH5%)!r?Dx7z
zZl7|B^xZ*xrl;vHqF?25U6<$5-Aq2!RTQ_IXpu1f)7=Ut-BT=~cnbIGisdOMRK#!t
z@1w;?9EHo%@uJyxqgj7g!(KX781g2z?Tm<(B*xrLfkIK#g{7zt8{u@y8z)@aL85y=
zhT9xx%xjcP`GL`W+Xx>P!G2_-np7Kg9lR@FUANZ^!r+8<l&I#x|BJA9fs?DK68}%#
zzB9Qq40vZU#34qk?sUTB0d``5@DQpyP3(lIod+>IgiaVR2!sSMqG(b*8L}gyJ3w4n
z#ibJyjQB_vc?pP}5Lr;yMMYFV2#U%g3P0tcAj$80swe91|MUO<&rH{?$Ej1NPF0<H
z+^V{d)Me^3yTlLd>brVRG0r?JQ^$7KlgwOJ0i2hKabx1dbVJ*i(&n~|^OMZRy)!cH
z%lk6#+I(1M?&g#0rrBK|Z1!g(b6j@rUQSU;IP<e{v&it6CUb>mZ{&83MDH5xj@sCr
z!*Os>`l1{|R;TOgygcxtH+lDzVnXDHRv17<3;_oj<I*V~#Z)Gtr`Gj~J^_&h-6V3p
zBO^Y;oaUf3exS&_RyVqF=$&B4G;%~b2T3Bz;%<cTQ<!X*BKD#&l3<L;Mi2SdOyt?P
z$w)C}6wGG3Oxiq%aQy21W7<9QAIs*v8Bm#caHiTgSZtG%CQT&DVVlVH>6xBQhiH;6
zkrmCu9K~I0?g}{}<=F33jtmG)J$H$fhsmguz7dznr&X_bS*DXN-DTQ&0Uf8ighfeV
z93MsL3duVN4(I9}Y>Ao6)P_MKW2-^a>8uPOJMSXW7=TLMcM6VWC8v*wIZ#x=n=vQf
zVv~OPjt<~S_$-l~8)b}6NE_Y8*xlT>k@4(Qjbel?$$3okkOh#J8BCR|Y$#A_GS3^k
zm%IC`A}>9Jd#_lZk}(SxEeIt;UYSb#12A44bs=uR>r{hnjl^_qqal{3Q#q0E06M*@
zvv({wM&sk<rAu)XsUmYo%4-aVQ{yXi@$6DUmSnw&gm;OCe6*mc539kzD4!;_GD$$>
z=P-SX31pY3lc`b5v>MU^L)<>vqSI)~T^nX0#2=-tc`Q-{-a^pA49SM99SFz6-~omq
z{9p~|r!uhoTEGqPbq<cz)z$KKY725u3v!?V!C-1|iqFat9!~8CXgFD|E)8!XtE-ic
z|J!1!G}W&ctXU%Z9lh_qQ$1|pW7U=W*S_bLH~#Bi?tAsi^0U`&Uw7fFOIO|U%Bn~2
zc<L*!y#M6S?z`mGr60ZJjY~fF>b|et@$vniS$E~Diyzy!Z`z}qR{j2@%kKHf3-|2j
zTXy^3e%+@1zh1TGFTYqn?Tx4Q-??tuQ-8g3+uQ%o>pywn`28Pz{pQ#9@B7KVU+;hX
zg%6!`-?!eg|BiiMzVEcx@BHmA_FsPL*Y~e_{q`%ry#J@GUOxF3`<GsVd*AKrzx>K+
zAHDsB^)IZw<m+dzyLHq4Bk%aov_miXuQ%Se|Gsr6-19FVy=3ysd}r^49c!O@Vc$o8
zyy?{QcD($%_3JPB_S*el+W+=fpLlN4mwvM2eV3g4>Xi@NWje@gkDh_i>s;Hn=gs+Y
zfA71bePpgTb()eKZ=;?bH#fSjKAkt~9UKRlQ?8^}33GVitvWx(&33LVa$Dprg9pv{
z=Pj98osBlv={FRgi<6$ktdIYIR(ZEMNT$ZoKql^CQYLFw$RU@n7`jn1o17eSt+R*6
zpUAB!cjijpIaE%~8u#6y!E)r^m&=t~_iwF=qjtNcJ+cqHrEPLN1r_R|`Pry*d|A3q
z9+FwPp{VCvO81NLK?7rYXCIfTyF#X1Ofu%{NoG&9ddwbo1*`_p{H}V(sN?UCsAU~}
z1c&{5Xt1fc)bAg0Lcl*5RH9Jb|G_I*Tb{n<O#^LN&{791|L@P%N)+LapXWDfhPoe|
z61mp%A5B^}%L5YYnV&VK5W>_{o4Sd+cM%HE6x8I-l|U?#a-Fu%`5ss6amFPy1)6-G
zEEn0gU1uXn-2HG=Yw5ds#l>;nk_Pkq+Bl~Q-ZWU`iDF&Ei4c>k?nd`!>0<g17x$fX
zxIVrl@g#eLRAMPqT?w3IKp52!)!F_gd)Or#1>VeHk6oriAt!M^KA+fQDS%Nvq5pK2
z{K0>0ZA|xPcb9Zsx;?|GVfv6gt|COL7bQK#M&j>~)xH|`nH0#e8IiczV<)Ks<2HNt
z=Hcm+sOH*C0zKZ=7_vj}U=zE-k?Nt`F~WKSXO3kVvX~ynwkQ)erL|1b0q3#AVs$y+
z#`I-vg0f1ibd2mlU(@~d%htT}uxZ%>=n*S_sg<1U@~W}e@fqV~4S9tVqWUq)rPZ<<
zf0DpOOBuKH9c$1=VlM)^7rrG-xvHaR)r|nzRtD5<U81sp8^8}*-U{i9A@r|Rg_&1>
zj4Yk$RoaVF89g*1H3Z3`X9yC(pT&or#r~{RZ&>WjbK-&yvz9Y5zL#M7Ve1S`AVsIB
zfDNXSV-3byIt1<e@N^*pxkso}HIGwh4twa6JV(LQU*gy|=z~z}ya(pXn0fKLT_A}#
zqI4u1E17hJYKUw@V)c%whHaQEQYZ9=s@U5s*amkme06E&8lt_ZHR<3oPg&wYf!a2F
zr${@SXDCD1X=NfF0ks7d2@HwyN;Yi2E}qzlu@VF<!ZUDd2__>gPuUtpT6T|7eaRF6
z%OHr`qif$b4vEm$t4QknB(hdYN!nC94vnNjidun0mugtCbuI1`YXlBVDRP^Y2x+G!
z+MUJWBsL5##ZAa7aW>UiQ^<pz8zxM{m3a6Cruv;s*`l9s!cW05VlH5`uuOsDm?DLw
zDYPSr7DfZCCV^{h#A<lH7-&hGaxG;iYh*JqVOYUwikU37P$dnPR(-5!C~y5GUhPz7
zj-M679yTu~n`r0boG3nNQhn$^v}!ctK-hX=tZE5#wn?Mta!3cH)MeAWGl!wjI(41C
zV!N!b1S%|`DSEJTI+X^sX@n-)Mo&UrD&`5KaHY*EH&PTC`h}*DrJ{pCJw!_o9~DG}
z`ooI{a@dw(13ALhTmOkk8fk(Nh24mh2~4ERB`-12v?2^+cI)d1B^tA8te@$|5$W{-
ze5|(2aV1Snhv-CVhiI#o5T$#T74Ql7O$Me_G>AeqnBW`BD;n`u_r=p*8?Y~f{6flH
zS&XzJG&Aw>WPd%}Uds;a9uu23s6pF@kf^M2z!?Q)mPq`DC~<A@C>;Sk6p-^K;4&^G
z&{NTK(IGQh=`fZTU-gosX!v4=4*VkC&T52(#8zs7pV5Sf9?F{M!tk>3e(BK|de590
zuj5P~#kdR=B5t=<^KNj*s1DB2)nRh@P~58Fq-XDZ$Z71DgLDxpHVmK17+xG^J7tJR
zg__0y&<%#olPGY_XA)`oD)fufM_dmkhV%Fsn(*I%l7=mD@c|!i)oOz?93!NqLY1Q%
zB;~DWsP_;V1wQ_cjl&vE>Z=#(qYu?6&_KT_enGJ<KLyAHxv4ILH#O+-2*+rHwq){=
zWSJtiMC&A8X$e-h))kEaKd}~76{5qT6trGz2px+f2}?i57eZ8Tf+mz0PShJ14BYwI
z77rng#nZx-6YsE&5ahkSnkE^btW96%9A3DLA$WoBa7pZgQ}0`VX833N5Hd&?TwLfO
zMSrE87T5tINAfbnFN_)*Py#>L$(NIM@3RD2Iqv(456`(R9!`AH6}D<n%{#)GA64KS
z1c~yzBpwm&+KXwX@R7Q@>I5tre^QhdJSF6?Q+2J8!SIcFrp$HPZ;ZeTTFbT7MsZi$
zlHS-8m9c{5mSK@bXuq_E@qW0w>Y`@2-8vmH!giUEDa}{fEtB=Z7l<QW03f@$93Fuu
z@eB~eTC~zgCPj}k7U(y*ey_8ZZWoP<sR^cs87}2(-6r_ZsHUNBevqIxUSFgx^D4d+
z)G+5fYLe6vr_)B&iLMPcx%0vkFK*^gAn5jyy74}6Avu)=<C(5ut{r1&hfC52*UVQ=
zx#}a1(nW;V8CC&a4GtL%QyT|)MWbzMh@-o(CrvRv%(!52*cOM<gAfE?8rvdmF%t@_
z>9}M}CeQPiD>EbU7A(SUz(LD$MItpJHxn^XWed=5{dL$mDRO}$FfADYj`0}1T508$
zAuld1^=Q2=5uKxO)CFIb1vQRvr)@?`(p9xlp<l?_>1D}}`Da>P0d<9rbO&20H}V@y
zUpo}3I}OCp?XYvVF1^)oXWXFZt6rjJgR?48l^&5(W=`6sQ~Z9A>_s{V$`Yj!?+n~Y
z+g+r9uD4P&(3@KF+?S|AzPG9hT5P&CjfT5PG9g%OTrFx*&Y^A=oV60Uo~YMHE=_OH
z5mUqB2SWmCjl&|`Z?$JoBA$43mIo#EBvewT){tmO4l}ia)UQql`{|*ImIO_*vpOVQ
zV&waE&1i3NS(P&4+PhklB28DQBT33RX*#Ghn0q%eal>i7FPb>rD3RDjx=^M4Ln<TK
zK9x&n)Hu2}Mt-3)^(oniNhBFIuHvrN5)0Beq{h`E8*vfSBCU8U{*e<(jf4$ti26Yt
zNGT|ZRUV^&jWqy*Mz>EoSa3wc14XE{PU-9LGNdEL5D<Ayr{zPtvUuWSTl+&5y`ee5
zdo;cVE3Zf{n5yaG#21u)01c#=^02721|1kt-L(}fu!QEw0HG*S8krl-KpP$faTeO~
zgBltjbOJ5DMVcNz-nZ(b%#Wv9l|#*6D_7_@T5c4yw1^`lvKVSp^#;$Z58`f5euml4
zaGD_qfeJxf2l7RM)>M{69qiP8A;vn?s#R12;!)5<(PT*u7noXhf4m{s13Ow9EKbzR
z=-Lca93CE1NjhYYcoQ^@bzLoFX|`}!k=C_H3wjdiouq~`2l@^PBtlb&nCT(9nAA*A
zY=nEof_0ll&ROg#E&Mbc99An*>?dmg;06^r;t%xRK!?+?mU*D2+)6$m217}cni%kv
zl;>YoC~bZerh{p&QTQ3Ly9U)$Z2#ZogD+~1svF372=Rh>B!XH1`ajpQDISQpt!!1h
z@uJJ8aaJ9gJm9$7%~ZO)TAO&8Nb=rToC@S2JmDafVNVRN;to7%j#F(2cql7LHP>Oa
z?7nc5$X(Xxusz-oaE*0dn_LSycxjB1P-04p-w31~R?kmnIW++d4B!+Wk!hanm{v8#
z321S`gMzCigECrLEka7K6{y!Vc~lCMGRYh&&VsMRq#|l{P$!EmfH3T|!1Bmb=oQZC
zpprzcLT5VaSu0p_I;Rf&gxFram1{=@>A+QOc{KHbry4eANn4ld0k$pu4Kmn}zhos$
z*;Mzc;%+rV0(IG*3PKf*8Y**BPD19Qc987okB17%da9m=Vn_4ogG60RR+_umSkI$C
zzBR7HUS_d<BG13cJ@PbGTM1s0>Y1O>1{i!`<^ZO#SmD)r_KC)tmNz!h&kZ6v(jO95
zUa{$5S(CHk;bxXPS{~kEC0>3IF><iqt2FhV2DU(edH|eL+JNSO`9%w8GNeJ8EvM>3
zoKZYThGEhpa;rhvR`{?ikMdgk=xU)K{%P-6;7J^r)-th9CaDjQA_4W%wDsv6oxMcT
zW7UDLK3kA1BW(*>?9>BVdRGOwo;Y~8h-bGE9JF+&KDaHzQKvZoV*Pv~CJ>IIIj-Zi
z|JXzEmZnZ%se7xj<g=**MQO7ZE$0q)Xdq$5O-`Ze4T1((S{Z%{PJddC&110vWTzY|
zn|02@fmal@Xh;*c#Vtl_PQtfSJdPF>{D7dr)Moj4hoSKq7g@C;xqziSNrV&EiqfdB
z3rWaco*K-fADjMAI@Fpa;qH)RwYDGv`42!%2HPfO!-#`Ia+(zXp&TIThzs;NyF}C0
zkA4u>svltaK`);Z=p>_3)dt`_=_+0vRAvD@1!^dFl%OIKok$@K45%<(mU;y00Is6?
zsJMWEg<^O_mVuYLb*ZF8`lAJEh!U;F1-4b%YFmLH^}{gIrAD>sm_3dNALXG2Qmhx+
zckz}_iCf;kq&#!V>jU3c(!*n<RmEd#6H6GZrffC>oEn(mN)H;O<*HhJDjQ7AusCFp
z$I(5Csev8h^%2S=Jli#bBYg$cRSJ>nU)%CzhL(8C*GNLhBFOfG0E0FZeS^5FfdDIm
zm}N~N3klNjP*zT`+E^-@LF${b8<eXrk$CX58UnH!K~80CRi)&eaPLmm#aN0OFC;Ey
zi$y|BC0$Z2JMRi$c&X<#sOr^h#H3*HRBl~J3O+}tfDU;w__Fz-)bPC*(7i;Mb_84|
z5YFKM?C3(2tBkrGSq2|=G%rxq7C{<Bv*bTOH=G+5hzW>GJdg!|1s|$HRhieaJmOmr
zA#Zv0b{L_vAOTL>&?xds6=4}=4Crcrju#1c>lGDIBPQ4}h4wk_UXiGOD9Bp5Qj!nQ
zyEvXWAz`u42yUvLRoVLj!pMR^vr)2&TjCeMs?Jd!B3=5lnossOQUESO06G-F&r1n5
zqF5<FMhmwNiVOx?xBw{Qufq!0+R%=l)=`v#kFdLXYaH+KQGc)P6{-Yb!229@fOCix
zI+npEKZRZ5ye6m-lsK3=!tJZ7UkfN;;>F#g9Ud5?;CV(JaAuAAXn^a1PaAk`Rm*O@
z*GItxQ$wJq`2(MXBM-9yQZ36_$74j210A(f#8G8@rE2y78dq*<_ostNa6(E-aTlm1
zWraV$8zrvs^%+ziWC06p>HuAdro(+m;;oWt7-dF%$&GX1c_$%(m<JWYu{`f!B9)y*
z9xn9RU|0F!^1PZ;o4DTLa->?Q1;$yft;Ak*uoCryuf@;+B{TsunvVe+IE_92!f>;f
zG_mQ6W@u{)e+Tce2i_zm%Vro9MV1n=03Rt+kxDHvFUF}i7sSd4wC#W<uKh($pAKfJ
z5{#RTS2xnM5ckNV#^nJTULc$Lp*6gz8~C51$+bt016SaRb#$fRODCwLZ9}_U^y8L9
zS?eb#WDnwM(|Z6q{IG2mY6Ff#0EwaY5SCgfz&elAd0yg&Whs2Y;}`K~NY{&R;Nh60
z=@~YSqu}|+M*ZmVYEQ#>gaDRgBFh*&c6bMHhCG1_MH@1J@1Q2y3J&$IU^P58h_yAf
zco+ogWDHKsxGtb#MsR|i2a;tC4@<z&@Tk2^BqYQyjx;1_?Hp;6E|pQKc=c`pWrxLq
zuK`%%*tbMyd35<eL1Zu5$HuB#wZYq~14`5j+bsmo95nQ8q<~M*10gLZ-Ya1!OJocs
ztLXtn-0}3lDjG?~D8()W^ub|pE4b(hb%0QUHHlme^y9vcKmahyf6s9UKj5#=SjLOY
z^)yvL^(go*#+FwPAc7gob3`4kp?pWH)yD_gc0m0DL@-njxCC0&%0voeY<vKRQdI@i
zO@)HmXce?J^kOX>$HN-6YZ>}Fsptrme;84)645XKuMA*BT6>I+dgIXriJJTk2%;gy
z1sm27NLn+P504;RuM{lAG$`(Im{bBXtvAIg%m5+g*-3LzA!SLc%VW_N#WM?Aj3k8R
zNc>no1&QiQ-n96k?F*97XKHiRG_1uSM(~O|xn0Kwe<h|#23j6Jj|1ANmgB!!>`LFO
zS=Aa7fuj)_x6C5|RT)g`u~-!d`wTG#Tb|0f6MRRo8OQqw{Gk++C+o30Yi(Il3thxz
zhXQHTISKGjKRy~?a=2Jqi^GG}K_L~Rv!z%YJsG77fK5%$OD&Y4x<~0zqj8O9L!a;v
z<P5!j=n(FBz=FYNCseI#rJUuKZ4Cg7hhCAPLs6_`DfE^%ha<7nl~v;9Fv9FPh70I2
z#`YKr;L{};Mlq2JNW;YOD_}&Fi@J=ob26WFJnsf1a?7pA5FtX6E#TBc%i^tXS(*Yi
z;B;VYouw6x)*)*0poYjP-y6jtp%`Tg$1#zxnrO7WTF|ajT+I!{%Hh#6tRGPpiJ=Nu
zqp?D)23g`?Rl@<OVd>L+C=%)|+X`5&(ZS6JI)Q)&=-2=U?51pu3+}&#DJNc$#EFf?
zV$rl(;jAjP+_c1M4XchELb%#{q%PbSVl+|<KZkGZrA5$%)+8FIDPk?9P0jY)qGa$)
zox~M}B^{uJe1-BgT0;Xvbl<JK1mr+6bm?9h4yhHz<ACi}+1vX=RIM*`!Ciz<lYn5T
z1)Un#_0h(<uF~f7sgdSK?8DfrSXxj<UahjVvXSvpQ;XNN!csj4@;Tj|D^~i4+#I$W
z-as9!H{-s^vwPgR)Q@Dglh3+rIy)LyK%%EKQ*Lf2*{KbcY?IP?MmBAaY$=&rwFsut
zKTElE95>0iE>n!!A1FSGN2MMwXUinYX@;Ab%0%()F3CFz<waLw{a$V#a*np$Ic{z(
z-QLi#G;&=i`SdiGHX1VCY@LIu<5t9KF=~27KGBLC_rRvZOO`k^!;0B7$hauSOfROB
z$&YK4=FxKOOerxq@!7Pou_6acBQMQbp^!6+wj_)>KD%pH+G{P9$$jz%p7v>Tuu|xs
zQ|~bwYSBnMm=|_V49_Fw+MpK3QA6$TuoWY7JIK$-4bd#3UXaYLFJTLY=}$9pTCMe5
zlgMG-txVFf$Vb`=6vrYI#ak}#DCUO-+{_B>8@na)sk0(7b7bN#=f&4omPM{U$;<sY
zd05)o#`SmlVX2kJOTMugtgqVBwnxME;kjZN`W)PmH2TWBWY+NetgSYZPA$t1Jb}io
zh5AyGrSekbdZl6IHezcX{Y)hC9bW6swjAo~++!f6W$9+xk>UsK9$T=>^LwJ}(5=j8
zF<sAXsdkzrQcROQ*&Z=P=XOg^W3Tv;qmh0=^Oda<9?L>!qiR|{D`QtAT%`8Zn#+$6
z;7WY$i0XRnDOo9vh%4x}9}hzarRR}C4{gr&50+>_v1}RX?n%zKwVjh)Z}Jm+O!>vy
z++krX8@XB3jT{|S>NB?Yi!z@T0c*{cbnX(#y86&yI=jydjJ!xiYug+rQkrXBw$L@X
z$-s{As42tqOkTW=mds-}0dMYQVDn`EAmz&Z)V4d${kZ(lkhHrs*}f@wkKb-H>2X>1
z#`&{^USjwZQ;6qztTl!^MXm+46J2qJ<5fyE%Vm5~+MFya<4P*B@LzMgm}1!@eJ<P2
zOX4<SC12f|n~ZXc<Wip;*C?j-ER}S6+&6q}&>2Y~EB#*VxUOI6f`nwwU>{L$F>mB9
z;v}8%<qsV;bLG4<X3D*7AJj7;_by-D(|_Und!D@`KM>zG>+;#>&tE!w@2PA5d`ID=
zzy8b7)3-lUT-yKgWsBUcGxJYeSIFPH)h)ein_IN9c})Ii*UcQ5KI!7py+^JoE&EZ=
z<RAQT+^nx|{cm?y+Xdx;A6<9(MZdh`m}`cnRBqgQWaaY9b{})m;_KJm{hRESH{N`~
zC979__w3r@`wxHe(Y^1y@s8ZvS3iA!&lTtXxaYT@{?f@$Y}|6>i4V<LWS5;f{((on
zbm#-uZ=H14`Z<gGpFgu_!EIm4FTLyL$@hNzppW)n)N%Hb*EX&!|LE&S-S^J^Gw(XG
z<IMlKl4HNG9a7krKl0SOCrvr^^50LWt-JGWm%DGDvq1Cv(tjL##lCId8u<FQH`bp2
zwRgJab;no!_{x=+uY2XfC9nMU!z(LW7n}J%U6Wt;*)_F&o6fl6{AZ3Sulmlo#%tS_
zHdk)F%v@nUAAfAyq9q?YcyaGvht^itpa1xhbsJw_`utU|&;8(eSC(Jj^u7L%-tk`d
zi^*@AzyCL9mfv{hPlx|CcYoK<H{O5N>qEbrdEcT7Pkf?zf7{Q0wWaMZ&wS(Xb<aGN
z{`%>2SG@eoUyXli>2n`?;n{-^f9}cO9{$?rZa(X^y)P_&<Bfkl_SHAuwC2Mv?>KJX
zvpdG^-@2o^|Itt9FMj3Iv!8!s$BCbzt=@UZwAFXqaZv4*egC{{Y5xRS@~3kuZs*%-
zn%`H7AI{&l`JDq>x4m=Vy#Ma9uZ?`vUUBQRCC}e6?PD)(n0(9%JGQj)`WdUwy1u*i
z#C6Bp=Nn6_7sYF<wV`8VQGRT7-6>ZteI+i%k8*$8UmM57e?9lg@*Dmh_kh1g2AcPb
zYu2a9uF3C>9-VxN{OkkAm)F|N?EkPE&R&$;ea4F$rY3KBbpF6EYPo22xfH!tTU1^9
z?2by+Zy5hbGt+ZlY5w%zJpa|we|&!9X;(h`z_FJ-`_J;{Zyq&$-R2#A>z+P%=5L=r
zxb(|k??_hPzj5|6kA1rL*WY~8jNh_X_oRELePqY1X??G5-QiCB&v%t4EEso%$Xf^W
zT+FiVmlT$L^^kn|<%9EcfA-e%pPgK;t<HVu@=ae~lmGPZKU7V2I+tu(BV8|@ko)v2
z>*Wc%P%htAl{1#Ck?$6&)yh?K<M(V^wDjyaEuS5A$B($blus)^8!w2X-rdDV<JG^J
z)BeNXEOtxc!{P^;r!RSS@O$%@Z~Wvr|F-E|b4c$Td3EoG>iWIEI`sPk-}v}I`HLU>
z{DV)of70#kUb5taXMBJ4f2Y%b)<`Ekykge#yT90b!OgqmM)n(h;pHPH@B97R4_)`Q
z&KXBO`f0g+>4w6_CpT9Q+2`Yv9$H!wIjf|3`}DtvTzbo!2Ie-qR+Jxp_xa;0V^)1P
z*FF8_WX96l&N}b>OK&-6AR3t=pI&jL>l!#p=I0KzPueuTq9=8$89nlTKfTEI#FxwJ
z-j`&JTQ{k@ytcSqp7UE|&sFVn&(Du*FWo#gzO4Qi_ZP0@e_!#N@gE02dBLab#D#4(
z*Z$+1qbpv?_so4-qWr~DT61On>SbG+e%?pyaK{DZq`Hp#N>6;&o8=pt=AwtP<t?sW
zy=GV3ec6`}vHPE%I`inJq+eZd%jucBeBt`L?DDp!b2(vZ^t{D*kTsX`<Qeg-(~sPG
z%;M*UuU~w8{||rOHoMt<UZHBTNB*$5d2r3Vulo9>xyI&YPk-%86aIbbRp|w@+fTS<
z>d;vE%2s{jIkB*lxBkOhSIm0YubB1XV5gnBdgA4cf#oZQ@&l`f<Fa#pVR`=UOWi*Y
zu5h>3a`wTU7teLIG9TVs6Zyu%S*usp<<j!XB{!E>_TKQ!l%AR2&&;iU|5xQ7K3I!i
zT;|=4Kl<gnH~n$<iqG6OlHPjb;;3)c5og`?z`NVu_|XEl<koGctiJB~D++z*4_$um
zir$~ymsvpm+BAO;l{qJ}>-%f2F3ighZ<%xV@VSeoMjMuOcaHE0EAO_lTPgqLHOaO}
zN)6dkk^IhOsP<}620Let?96!Ei2TGjS|R0{P4`6k^Gt5mDVh1Nb?z-qPgi8eP3p<F
zZ)V-xHDt-|C=(qMv0I{1n&s~A>Ur?!NsD@AMzt+Jqq=v&-kwXlrldzKn6l*1->h8v
z$M64Yg}a7#fqm9}DA_wRY5F<7L5E&&=@H4`+@D>1%6nFS=ip_vk%RkoJ-lbmbpQPi
z<@+Zm=bbn)K6payY=)GBXEjA0J&_)K*Yq{HrW+m}bk{}OrMG9hNj6kXcV<a?eLK}W
zBU}<xx4XxfI2uEJJczIj)|5AFt__ZjT|SeM!e+X$Y`lDKcU+6>%W^|)m)FWu;+otb
zj@e07K2wW(J0@qPj$g&q7{ZtyCN@xZD?U+mi>``%Z}*~F+3aykHpI54qg*T3ot<nv
zb!^BjYHK#%ylXpLCsDZ`JJ<GzEl(O+(c67vMh@MRJ(^dwz4Z|ncU)JibbP}uSk~pU
zrrF$jO0yx?w%6Vo&2?7`v&s{l$T{z3Hno}=rjzXvMijfNCo&5xz)!+zSf&t`;TbKk
z%9(RxGM<gb;-Z2qEcAIUPQ8XPQJF!JzS;D4(3nQ4zLzm-9W3q6or}~~r{5<{F{>rn
zaF8w3W5!XQIN}zXE_T3OV`Z4O#c-I-cD2;RP4@i(3zpYREE*s1p!<|%Kx3qKXtI+j
z+Y)HLyYU`lJnS%~^|_Venp6fhEB10Nt*-R*mP^n4e2+yFSjl5H`Zaq4)wnMwy(8?!
zx8yS!TBs{<k#%0S*KOS6*bP#PC-8PAxu!;5qQbH+=f({=2-I1%;Ns;zL*8-PhK)#Q
z;)yGu-=4CNpU;h0D-CDkg!ORAh?T{XPH*z=#W$=J8`aoZdt78M^(CWOgMN0Pf1G6<
zu#}86q#}|Y$&lC*)20;<{W+6lFZ62>-?@x*iq${TYvzz{vDZn4F+WGxO%7V&%+H?*
zK!%;7(Awr1VH?!&Fp1X(0ukm5q(O3oX_+Z_&6m-6p!Mojs1aTRdlYPVdOglk!|H-l
zrJ>--HxDZu_cB;I15OmoRyg|#$$;7c&(M}fiC+}>YuZp@sDr_2TgfVKibDjgP=?g3
zG;ucC@zA8z>39Y(2!!p{*tfU1c33rj%LQ`mm#d6q*pQD1i@rT}JQci#8x7~Ad7Zb|
zBuL4P=2mGWAqr!0T>#Q_yuOEVSd<wb5>hb$WQ)On@YIJ3))<^F2&ES1h&FI8SPJ>T
z9Wq8ZHl{2GoG?^9{$)M$bKgchk@LQvUU>WdQ+KR={qCpMz4pr4Z|wW<+h1OF;nyxb
z<GEj~dhFhFUO4H;uYYFW`WF_x=PU2~;OFkx|Ls*j{K^~qe)sCyC+|CZ-M`&&#tSF^
zpB;}}@|8Q!dFl^KkN@dy7jFB&N4~P;)M=l6a{rgsp77HrR=xc3$9F6}^LIDB=c$`N
zde5CdUH|IQ-+N){`|nowIXmur`N}&l{@u29^PYQZ{!efF=r{L&c-oy8pZc|>7vJ;B
zy3f9J=8jiiop#gy{X5Qh|5rYI<xMxee&nlfeC5sSul)9+r*?e!gqyy#YW)#E|MsDm
zobatPU;o4UllOmX)ui)2vg7@4Y}N1he0bVTZ~S4~v8V5N<%}df<(4k`5pt_%VCG9-
zExI{1<GtB5KW?9u_(Sc~nTOUQF}X+%jn^T>t7)Etw@K9JdkWLM$xlp^S?vvX>0BSl
zoLn4dOe$kW()1i#l~aADckI}ilIbnz4#n!BLnb~nHc|J?G&;ejOXB#Tx#gkjV`DjO
z;!QNEm}Rly)SlvAFWF1IGj(?5M!OFwR-(#P4@q*+pXa1)yEa7T2Ktv_N&maw^n8E~
zB@11@ytNt~_LhE=zL`d2<m+PI?7RQZVIrqpV4~wpyY1%utYpz?R0;*nZvZp;{NE4i
z!T&#KWIKum;eU+tzv%i=tiM10myg!w5C`Lb1^qqF|HDSn{N1l>_<((s5$dpCKvSi;
z>DhzW6?^1X?qxBNbJCz|p<7zm#Y%x&<|100p}jRF$rB)+d*e%%W&4s&;8zSaTug)M
z@+^TA94ca%dprOx+_%z(E-<DbvOM<q34IC2e^lRCnd#yY2i-`lwW!R<*-EKE4?h@n
z4oOay6a%ximwB~KrGP@?J!yprISkp@vmVbjMDg=2<Xm{6<2-RrafmxV0p6srhYS{d
zc=J)&Y@)<9Q0C|;yH~2boZ3Fevh~MkzmjS0_H36mY5oSHdqg5D+Iso=L9($SzT|kv
zFr~Ar==kD=5Blh5E}}nWEE*5%ErwmIogqcv(?}fMPf_1IN49E=OinmBE%DCPF7Ki*
zlUa#xAiM_0Y}Ph0c?fUDf5`p(XlGZBQ~~Oj1dKq_jtn8JDCo-ACS&?}XN^B1=MHqr
zZe<CvLc(Il3k8`?<AwcNs{Bc>?8ZNi#Ilb{(G*9oYbREkjPR%*+|>k;1S0#Oe))|{
zSn!sZ-OKvajome29RRC!BEHwAQL#lAtnel52z44c$}5Vs(4rw%&<yGuj5LOKKi{Q@
zhg)?L_75SA26~wB2SJv!g>hL@?~XlIF%>pO@N5d@RS4atBd%t0C65Bw<iaI`u!0-5
zxcSj*hQwla^kupCUbEvu8eRj8i@kO<yRE~;8#k-*jyAHAe<7A~%@$7$I{*X7o<A9M
zeermbbRCQrwEM7%j0a`wLw_gngUUz2R5fms`UL2G_d?kz$8jG?<iy}$ltmJgB$VB$
z%M??bWH-2CWU;2PALfx{Dz$cUAw~9-6W8nB_BxdUnNV&7oC`y#mJ`(YcX=YI?D;2e
z#ucoSw990bI%5joqX(Vf0njl9NCZKjUjY$#o;ISutqPbi1fxZZA5y9r2aP!IsYD8-
zQ041EwF;rwy|r4@t!+<3xLI$s6ue4GyZ$ty)yrnXb_U9X17Y~4Wzv9tdKDtHjNZsI
z_$1~KpU2MU6_Pq1aTQZCrmxF^7ixlHOf=N6NHz}Pmn2o><{$Juoz6Mo>*POkgA(go
zt}!$x;6(wQ!$96Hr%f}W^mr_`QJ&^O+IF=H#K2YWd{X8B1S2QvsDhQ{BAz_zKw>*N
zv7X%1K=jPVEeuk?)eR)=U>J)yPU)wmd(B<0v%x4dqRf)cD#WQct)jtX1y_Zf7AZ<l
zIc#K`MeUrh*Dy%VBfdC?k16#wbNE13&<L@mH5H?sHD$OK5nzaj+!RWRBpK=EVl0PT
z@y2Z^Xl&q;5l_il7$tV_=(0|%bah$5XCe}2@pXhS3$80k)C3vAF-WY>V@>ly?aS3X
z)H1jyBQZm@^4Jx6_(96{Csr+vRK&+gyHWqF&bH-p3ps}z2bB%gb$J2-3o35P)}ZJ#
zh?z^m_}iH2gek}PCLU7{=xnDBSZ!FuZ^Wj($BATddYebV>#iqwwr%(lHE)%$CLmsY
z=pG#jR+22%SaSHM9TrNe=d70R(t|;hJ+Y(geZx}5EH@u$6UfN$5hdKF09FGMa!n20
zsqAD)gD1R-@dtK<;?OX0r~z#@A{BnTf&iJhMX%U|V{6b=2nZevp~`Z<vEZw?l&Hh|
zD*T}rM*MV{Bjm1?AZ>Awx7?&)r_iK$Y7hW6Ij!iXV~ds)i+a+sq#M#y$R8Lw>TL!>
zL{o35dXES83xX4FRThqxH;f1Ly+)*Sp3-v0#8fU-_a6WT>u?ciY7nZTkQ_l84TvrH
zNRx!Uy4`3zhaK!zoyw{O@ZeGJEY`$R@f86c_6!?rAz3&xGU##jWfDq8)ip|!sQMcW
z4=vws+=yJAGGS?fXGlC^4-u<*<MsVWE+cJH$!L0sg>*HsT`|(mp~Na8!|#A1k=d)8
zGGx(u&U*~>h$XsN!08mS1FIw1a<B7Z=;eIcMQK;Hg|sJ)Y`cw1;0o805e?L&GPM->
zDpKn(pAf<{SvHJo+tc|HWyxiCIsB!Y^Eh~r<wi@#QLu4hBN?PvZSNw9lt&+_Xy&%V
zo0OG6mJ@>LA_QdJ#?VrokA;h#X^TVBStCl2V$>en1`G)d(8iiXB{9xxSZX?#K5N=h
z+LioJJ0%@q(B3qQs#;5kjChTSEH*e{oB{${FuICth1-HmI4rGNnV=+xsAEBJkri7s
z+6>7nbgs>l3lfB8caI8zwS{~(9`tNW@kW|NmK$>N-N@)?rff~JlB+jl0?hOignBy0
zb3X&stbYiLOiI1$VdH)jMFTkXwhPxLG7#sJ1chOE^LEVkWMi#_elM_<!fHj0{mP;A
zs5ED)PBkO%dlMH^ZO!ofOxI2+T8U=%t-h+wQU>+ZIAh5{(hCC(>$@7#&bu2{M{H`Y
zi`#1jpGikDJ%cdl7kD_K&Q#-cv*qiEoftksUMSz#)>x-A(N)#n&b=;TMTtR)F;444
zXFcLfMsFJR+xCaQo65s6rBbxsNw1q(mc$jSCO0)_qc(vVXb#X3A(IEE^(76<uw9%i
znQo#}_Q)ra<Iqf8{z8#<C*5Vn%TfCvDkkoRk&<<dR2J^tD?>D5x2%WkRASSELUgs-
zpvgs)O){M^g;dW^EA!iE7HxDHvFY36rPA!6N)+`&e{Ibaf$I2?uLKD;Q>Oa$cp0|!
z_Un?vLg!oG(k(}R5e)BgXR@s@;+vQe)nXLlLuzUZhV^1a@}UA!fxvOdfa1qN0JTyL
z#c?IATLA`xNpao6@W|mX!6R5ukSz~SOKC;M45<{N-2{1$E=Goc4JLDl@Wk*fO9z9d
z5vki~lsF};P*uYOKdLwk(nQ&6QiLxDe<TxG8J1H5>uxl0Xx18z@Bkjuij*`m{COjh
z6IRwJG_;1t+u*Ixl9vO`!WVwfA69R4n<p;AYhx5K0NTU_OUR0=MX|cP$588t!$Mu~
zGD==!IyLlQygq{>cUb&TiJCB)V=r~Fu0`7GgZW8~ZgC-q*qwxln+ipG8%ACV=Kws_
zBrr-6V!bCzPQ1<G=?WTA{XbzbVoB-CEtDj_PC5~41$|;ch$3sD8s!}hO^OLpBDZ2S
z;D_!+6S4dpgxQeS<aS(K;1Uzc3XUJPD7Od;lIcgcAWO|0-X=008^932s<2E%Auogn
zZOqmX0Phl&6y5dcTU@|{tI#VEJv<iW3|1VN-e#mDq#FzCA0a^Kb@R%%2McW1lC2Jc
zlHo|J0uf!<b4N#Edx9&*bBLe9Vet?vYf7~P))W>Atraq0Sz&8z@U)mU!!Us$0;o~#
z$`=`@et#lZwd{_)OtT<HBg#UhqC|LDB_}9wfe0mo%V`pA_$bCs6(QVa+k*nvyjcx`
zX%^*;+J^a!s0ASere<lJfEV^+I}HkCX(<{*BPf^xf>H574F6Qum}^P`x!6`+Zl}wT
zEdGPgi>GQVI2??4M&hixTL79^{XI>94q}uv^E|8BgPp2yf5vpI8VdN>SY;A$h#`#Q
zox>-JygCE5VMi!(<UzXKefi)UhI(vnlwoDeP@RULz>ra04$?F^{SF0IwJTd0ys#-F
zL9mSeVc3rH!owm#s!+rVK6M4wolt?S`Fca-pB{&cR&;52FS^YsP{oX-O%*2p3YPk-
z&palzngs@-NY!T)bby$EW7SPS&<j?`Vr1y=9r9Y8kfBx`hA%HgixF#=18DZFTBJ_g
zMJ`x1<7hzR+YKaJe%dxeAPrMeZM~lKM#G?!I%0)!(-f<5OwGdDZknVr7$A$>C*X+G
z6$~ly@ahCNfcu**V7TDf!X<wY@|s8W<{fsc-aQOoh`<-|9OUP<aDXO1O_`x)JPgl{
z?WO9r$~<*lsjAX!@bt0A3|)g`ju|9u$sVM|SP2PY?QI&VQQ!>gS)dL|Kjh6)(i&%o
zpI4DetmXXk2e3&iYf$R$){Y`p9wA6`3;Zo8m;7jJQy<}r=~{QKhoBYHGmnQZE0F*+
z@FaIFk^!AchAQ%^5hV_MD-Pu!5Y-+)GcpPV<umbuhH_y_6@lNv8)C?%So)C{QUsD<
z202=sjJAYg)C2+|QHe{1C2$XRcx9OxBZwuCz!p0KycS$H5p}LKLUc<SzMl|e!YeeC
zRZf$QafgVOm@P7+`7Q7zx}c<;I0C4I0l0HP<uMql2LzDE5VTu^Rx(Jt2^yywR5uxK
z0Zaq^EC#8iOL7fmF^3&4vK(y<RX6N6zifjFeuyAN2|T4GF*Z0=+ZY>o840Z{$lfS}
zf*=AI)30`~4x3XR^Zei|LQif%(W~}=#IDHkz!Jr=c5}}6SiQe5+==1DlJQoZ^c0?G
zO%4w&N87SGs+nySnwbz1WPO;yb4U%G>OWRBqJTdd6$`)!5YXZN0f_$=?r8dCt42n8
z!e^OeOCGu-d1pnFavD*zJz>MBd8<z(){mSi7OYVd%+z^<eKpNa>umHt$~j3{TNK(B
zKc?S7j0dt8wv2_iL<d-m!L%*a1R0W0jnyhePi93KI#7uNxovq(jh<Mn2C<N?96PnQ
z&TqlE4X%)Aum*v44XQ8n0?DXf*IR%zi^}bzvq)&N-j?x#5&ZzK*HB#=6m4l%ok&ju
zVX-qjYz;CN>nH<?7vhlv6EHLk@D`)2CjS}&C5_bVbBXDT)iI(5;U%qliYBOiQbXUS
zTBX4b%P%2%2**#C0PBkCMh*IE9alwtVOc<Lu7Skg0bSZ0RuQy(9U&I#Jk$yuWu=TL
zln2KTi0s3dR;{gBsoJ!q(31sT!<v`2;YNt!wB;H_l2{+<=+cV|d7<D!pdBF~HWq|Y
zfIw`KttpH6P?ovRz(lAJpm?g93#cF}3C~)mz7o-_SoNCQboe<^hmTaT9D$Cfauj(d
zhV>?#-q+(ogat_zcpLx==CG<I=Ym(LL24Vcp~QkooECU46f<q3j+mq!cFizN%xTTU
z@acASOAI#zk>}tX9ca)*qEO3`yH|cA{;fmyUZSRAS~UPiWC9rwU|4>mbE*+VRdD)y
z7{hB7#8m+$9Yw`Ef&fJ(5Q*X@48flgq4~;Wf<hZ>;uD}jJrSElv1yzT5%M8OAL<7o
zL+YBmwsrhQ<GMk76~f4~Uu}AR>-E2=&EXrX1riZ+TxBp1Ba91uAV9m)=|d~kKv6jq
z)P!L^6H6YALRPF&aSbe%RU}p6xIu&w{B?=CHAq$ZWPJoDHl5Xh2r6;(stGUr6USLe
z+H(C)iqr=OrN}g64{5D&bw!Z>3AmL?0FUX4(6gEbOu&2%s(ShXYv`vKyDY$SNF(S(
z3~4#F_MFzD<D~Aw)Q^xF0qRS#M0bHX^}?;>tt-Q{Sk|xfWrM(TP9MAkXffqN%Tz{!
z=sGJcP8k~j;GoV>5r;upalF#kl&Y9yz*q;qm1Yo(`Z@M+c%H3>`1OZH_C2TmGbXnh
zwlV@K&1b*i8$U3uDQXQ(q6)Sul}powfh-RNms0UHnHK0^*7=B@SM?XTw%7`Ys_Ifu
zd=Kdg`Y?;zhVN=iv0rhu2BM9atUAsapwL*)GP%G8Ypjm+f-FmDsJ_-|dsu-T1$~D`
z>N?zVLIPq~`_f5<Q3UjO4>|-U(0zE2vj!SkOAvJK12$H5CW0iVRNhb#iO0FxaQ7H)
z6;F<rQf3Ag7>7lD$aW$rS>%i9-Ef*<(-2EV*PsywY=qbdJ?i;uK@p5m2$YnS(b_R+
zm1l)E)yE;<5zEP3I;PGpie87Xe<xrSsRj8!C&VJ@PA%t8OhOuzt4~}DCksyAhwLH>
zJe!GhRI3*9j&^48AtRv&kyu=8EFQQ+PO(aaGa`+WO412~xe;Zi6`oq(B!R5-6O>K?
zU6s41$|Di+h}XfHQO#mQx2s|bna6L$(|ZukDw}0MQPc!f0}`$&0o$$Bhx2M^+pt&w
z%F=j?rCr-CVX15uk|VAXY=K%B*XSbvuU-q94anP;Po;swB5b7MyynPi|ECBztky1B
zfiDk8zcuvFKJafKt@shY0AveZ$iBrZ^4N%u)eMg2cQno91~7r7s-`CnZpzAQrXp3W
zON^G|6Rb6mNC3iI=<%IxdFZqCRzsZnq)jygdel`6e5s+?$8cLkWv{_m^;AKrn8tdn
zRt&UFmsiZZRW~sV%_2bT_2Ja`8|dpa?K(i@>|1z9q&lqy+$os#DzDV=P_m;C<P&IF
zWud0tPI-)dtYXON4Os_HJL1s}=?a8fBw}j=K40oK7kR8Awx6|Nt7!vH;%18%b<u)6
z52os2Tw^ny6r+aX2JsNq2$L61PbfA34_+*Ea-^udlI}2`3R?eLSUm0D^V*WKSI-6p
z&;ZY9+z?aAgl0@6i@h#!lIJ?E?V2a2=R^kP>Uic~3>yx`CL2;dR+6(*X2FImYNWL`
zD3!Qlr5YuTj1)6E{_3~v&+yJx)2%&mG*qk<k}Ym<xRi4GLFAb^Nn>wze6!k^CmV`$
zrCFTaFPjgh{Ux@$i3WDr;axkUW|h9dz~wx|Ff^F-x7GP1QYmfgVZoWtBG%lwnLgut
z3pSfW7qY0xtDQEJc96rJ@gSLLmZNl9$<C}7`Yf-Bd6SX2CfUl4*N##4tf)ASv^m-V
zbI6L{&U=qyS}>C7x04%J>}@WW&Mub8pEoM~c30k29gG+qR>r1g*ymX+NMykZ-ms+E
zPYj`&hjScMJssm6hb2R4M-Nx%dg(ieu{V|bVFrn{-YE82pUAkR*S}-93xE1&8)s~v
z-^;!eEdV#p`$dTy;;bL^ItK3K2FD(I&9%ItO0Cmv2yQGd9wlN;05Si2JS^^rB&kI{
z$KdNhFVvI7Hyf$Xe}|b;+F|o`{1`7$mP@uU!HT<+6%|R+UO&s;;46}4s<ygBJ-#<X
z?I_B!_zdS=M`}J-U{4PlL8Zera_&}!S#f1=B`2B1&QYx=*iNnps^*6yuIl&Qg}n<u
zC=+TEcy(eNl==&MXQPOVg?>}IdL(kGsUMP$%_(AiHECSixr8rVw{*segOV<nj(E$8
zVxfx*)=Z_`?2(4)w&EQ!k@@kS)K}#qNw1B&n*&iLSwY41tEJs0Sw2Q){jLsVxwhEP
zyYZr%@!<BP+-eRhs<T`=ufMC>7io`o(O?CVxuny!ZmAdNW+XF{lGLUrd#*Q>bRmwf
z$V83h3>Yb!1(Fy4$HPiivOcaJPP6Iqjc2kC`a(+hY|1B|X)A}7(ig47Tq0EEHFms<
z%wEm9gzI_Hmt!+waHeOU04;O^vWk<aDZ>-Mr=YCZF5U)B6j>?lLqdzp^_aeg+3nk4
zGk9B4@DXTv#vx<rvSQk7-Sp*_M0)09?)zDd+=^zc?mgt+Zae0Z+vhz#t}yS(9(m`{
z7aV@*)`JW4E=+4HA0HPD*mqy|=PhrZeR1Y}g^$eXi5}TGZQRdpoxJn?r=MvrE-uRX
zTeGwNym9iaC!V{0=aKiH5xw}0S@PoNX5Dx6g%{r1cENko$F86Bh10J)X2*xl>pcFH
z3)|C&uABAccmHVIC!g7N@ZqPuvt#zcAD=X({QCG$Zp}_Re9y!wCsrOiyg2Xi=%B6l
z9(jEJkRy+o_xMT4%2T7OH{N#ew?Dn}$a^bij!PCS93NeM>k&8kJKlc6^iy*;On>N2
zoty5M^w~|f9`%LtuD9IK`|g7t{@iDe=y>v&$)A{T@mn;%XZ@ZN!B1W{`PBS}KKX}l
zJ@wu{eBsIW9&^sVv*n!iXHTBAsyKDhf_XE`<CmR3@Yorzy*zQ=-GBMw>6iZJ!yS`<
zy~6zFC$D`ZckOF^m;UGCg^NBlW8oc-{N}CpiH#Tj^5q{7|7P2dZ+YzYbLQRm@=YIk
z<%!4M|LCUI-@pHrSEt|k@|`EH-~IVnAKml#F;D&W%@gmu{ii2i`M$@;p7XwY-f`1!
zK7Z_vUp{u!B@cXW=K2Tj?|$>|)=xk4xsOl&$a&uz_wn<7@Q%ly-*0ZZ==bK1#_Jc~
zx&5ByAOHS0ro4Z_zt4CozhCaL`}@yb@NN54d4GO=d5t-_{HLztI{)kFe;s_&(f5ph
zQ}T`RZ;Lg*+in)Q@~g+nWk<auzVF6s-gVLw|MuRs?>~Hzd+VpiuRUeKVV9mVy(3pU
zBbi(~BcA%_#)Q{ioY<XvNHS}mwI>{N?LBtUBe$%KzPzTp=c*aSfqQSBR=amk$Cl0i
ze*Def`i8yxrSTW8+jjb#JBCiE+%Yu1cJi7p9rePB-=6fgJ^xymy8H8m9T!|a=6BB>
zJ@%l5S5JF$_3mjO-uv9lr?!6b_>=cc>^rtR*!Q+)-`_U&=~a^tn|yfgogcV5`aF4k
z^s6tJSDIhRzUofMytQ)e#CKM%HFw&Z?CbWX%qNFFo;`W!TlQ_`70Ef}V)XOqEl2!C
z-ZSyXXB^!2y~jGn>A9C*y)3f$J&W7la?zaj>8Bi3DIK@q?9!CAXRxzl+4=Q#N$F!x
zB#X|vu`>PL$1l5XQrXRJyQH$RcmBM|_2cKYKlrEPq8rvsS@EJ>dFv!o+<4oIhwL7H
zvATQYMLYSSAN5E7^r0EoG?pIr#1GFM*m&C)E5{DrbClir`F!(Bi{jj8XV{7DZ_A8(
zaqiJe8<%E}t=}{4p!=^qX-Q*u=Oc}u<}yppDg1Qhr{Z@F{F`~#z@q#?a~B`=&98ng
zo7o$gb00i!(r0TwHMe%1Hswv*S9QF%_HjAvn*H{hyHA+@qdhOS{b<ivxvuN_=`(&v
z-jeo7V`XD}Sn2S1?ChJPp1vo>ihS&Cn)jXw-|vei3|F2X>Rj;gp&ukG%kLT6e_rRp
z^L_v6ll?_W>BSk@=;20fQN_B_yz}B)hf}*{*e{#=V57FSW5#)B`P;J7hwH^xZrfE{
z`Vxm4j!4H1`|kcl8>`Wxf9cKq;EUtTr+=9<=iLA7#CJ9Cnz?C3cIt__-pqxa_a*06
zRvmi8<S~UKj@S^Nx=Ri@wd^|2Z5FZz?OAHh=`Wi%+gaw4+VqKUZ=Brmk@8LE^aZzM
zZe6l?@~!21=A&Jv|BSA9+GSN4^NuCGLmw$!G<15YZ;Z74at?}X@$+c8!hdrO@}$mE
zy5@}1t-p9Ivt`?S^RFYT-9R&6Ib?c!@q{CvS@@~X|FE+9zDG*wReNNHuT=)W@T=}i
zKR-Ax_nFe-W9!8;Zg}Ll<c5v&P2rjq&VFIV%H9X)!>|89hkbf(vGCG{dAB$Jv$U(U
zdA_mpi@oPns{LR6&S{nH|Fl@1`@sCS-tsQF&_CVZ`Am10Ty)uVzhKP(D?F3>%D<Xa
zy=Z^_q3wSj7(V+3b8YF=xVzM3Zgj=O{=R=dNxFXAm&BLR2fk?Ul3z`_!T!lSIJJ}?
zPQIZ-(8c7hNAvgeg$#AgoOjn2E-LSSvD$Xsm!mh;o4l&`akQ_0>)cOHiN;O(iisLu
zkK0#%W>akZNLwx%ERMfww>hJ3=N?<n%;}qZP}{>pbRWa?3EPWt@19b7<-vS=W!D&!
zJ~MXgXG+_m%?~#1u3CT3Z3CSdd7d@kXZK8SHkLyN#*{M6Lb9S+oZ3vXmJi<*to*X=
ziuf~K>Gprk8QYPwm(P#?GH^rt&wC3~J#VB(`o@mmzQ7(XvFns2GCs*S&Fr$D)J*nH
zN{{cJv^p)*@!Y)Vtft8FAJYSS%fze1Z%_yNJ+6N%&vN7>UgQXN*A8S}^h;!km8jP5
z#eME+SM{|HSN93e_TmlVn%7%b+gNi|@ykn_1`cyq51diCx|Z;<Jw{=BlhV$sqLOze
z;-JPaBhs=qsnwQO+}uiK@AN&<%KX*|SJ-2cnzTnX-+lDTm8%b3nG~d!-%_2PAEqa*
zbTy_g?Wp;=Su1s$G+o{fm27|BG571?U0k(a%F@wai6;K$Z6e61W4YYQZXt3|mLK`B
z;Zl0_%nxI8HZM!YVN`L`F_-X7n+=@~T9Ha^j!$e_^Leu}LRK04#<*x@#BQUW(nLXe
zrqfI9>ZWmnMKgaBqXqmBU@9wOhAK^+OJz!>d^CSWY*y#XaU`BmrjQ>owNi~fKmRaG
ze4RChAU0+=5;$2dHP0cgJ!u;Q0{r$Sj2z&I;V-KK{xsKCfgSSOVM!7M!t}F_jIEJS
zJ&gJpBDcWknV-Xk!I?Kb8qrB|rK2X5V$A&67R0o(TCm8bjKk9+4AfIDcu^;7Y#H&z
z0?Q>Epww`U$jy|6_oudq=$OCu&9#wlvJlO}oBiAjIO(^832SpBlgmkusrE-pbW#;n
ztc~Q12K%~tI1V(6wF+1cTu(Nl^03T&qs9~pBl6CtUIt~jJYiNc;=uA%_MTHXJ|_=p
z5ee@^A{B8g&8sF+T<Oq|ks21l2)D@}sv=+BhD-fOfww7Y(-bv6j;uOKr*82v2)>91
z6CZxw!kv|ZY+(P{V0tY@Oq>?fQi{(KU**gWQA0&gj>S81py-b<exze$HXf<L!XQyY
z0yrz;^{h*aEG|$7jWDvs7O7JdN0%z#)q-qgNXZqU;{%r0V9PpvO>wMbFg5p~{ss&B
zN3m<_SMVB|jj_U-f|F54R$cmfyTDWBpiYF#!&|Zz$RZ~eEDj-D7alD1EwU$!9}!Ae
z2KfnlmoSw?iy0;=(xqM$Zb;g9$#M-1^jouD&OW&oR|bDAE#*YzptOC<f%p<nsz18z
zPhXSj-EZibpC2B|y|uTW^R<0Hx#SlgJN4IVD|bJ2_M@8~`_?NTdizf<y71RaE4Mtl
z>e1Wg?_c|u*T1lD{jV3zfBmdgkNtK2ofrN5n@@f0$~%`nx#Q8}pM2s6+t#hQ=aq}^
zx%14&|8UL+_x)tmwu?UUm9_7l_Jw`>zx3gg_nmg-tLy)=<MMe^Z<_!33yZ(K|9$s-
zd+og6FMaRbxL^6xj{T>d@U7o--ssF*o?7+POF!PR|Ko3e=f$UPJNu1We!A+(d(Ygl
zZs9$L?!RQ)(hF}{|H1t?zJBBj3xBtM|Aluhdi@Xkr@nsU>z8aj{o7}+KjGVF?*GH9
zQ}2H1cSq<Mm)pL^nV)Ze`0d}|J3kl1SI5=1K2|_G=OL4fGi%XeN1-p{lJmCLQG7L-
z&|X?_qAOQdi*vcO+L!BC!cL8)&q!2lNXq7gHb=Qtu$QxAq|)7ED``*kC~B#?I%6x<
zC|_ZtSu-~2IA@kS$=H$`-*zEK7r)1R<PpaL53`z_bW4p=__$o(UXm|Pt|T+fg)-GF
zr<SjjOk7KP?76N-K1d<1?iz1bO4pIod%QV!r9@leF>*zGa+{G`>#i@wo#u8%6RqZV
z)@LZ#<f={^-%1w$KOoer1K}eFEThkg)}0m@%Tp`UKfq|U{|6s*^8wdC2Kv#u`9Bgn
zfY^#L8c$PbSzBrSjhtea`B{FWJT<T?=(&)0Ol{dir8is~?={JM)bAIeVwswn5{YxX
zJ2h+}?`E}~R)Y?y$<`&1>j_#xa+$_*VR@SQePofJi?FA0+NtUGNU5GGUIEIiE%W}W
z!H$j^?a_@Xh~&J3+gJ~bz@f9Wcii~c3231r(ks#Q*}BjDi;_BCcA~{)$jAlWWO|RR
zNh4|!$CR9AvMno7QjeH9&+hRfxuFpwI(V>?2D`i)VY_@y#ZXNOhsC+Hkhu1|;aow)
zHeq4MHIrS^A9h9$t;#S%<wdou_<F?4%}_92IuJoILnsqr*o{h^5R4Doi<p3BlTUvY
zCgE6(t0wGbv#B$jVL>1b5BoNgq&<1kW3f4sq*0Y(T!iU}INy*qubG%AvfIPB;m&+j
zd%N?lUkK>VJLiQ(?1-2CBA>!)(?eXzdzlJ*k+Mkik?v5o2&D}V@gDI*jja^p#MP^G
z?dq#WLKla8#Mq*`$h~)1R78}Y6;>LEIMQ<SLRWENtED47R_nm|L@R<TMfgahq?Hpk
zbwy?m7M}^uLU&ADZ!lxl#X6kzY(ZAWSZ!!Z4}}m27^xGdWa5#roDB=@9c|MfvB1_`
zDCSa}ywQdpQXzE6(;Xx%e|U-P7Keal5eQiRd@_O3?ZpKFHdn<ZEhw0Dtk({<`~TJp
z#Ee8W?b!@!z5->VIe{F|u21Mo76<Q8D0YFY)(Ah0*G7KyIh>)egoJYfj)gVG4P=QR
zt410-;>eIwx=_}47%79Oq1Fgc;}N+@V%jeMd^<6;|H&JTr83neWm98tCiSeO*F?~;
z;tg41%?5J3a<Q}%ZA8?6>W!2<6-=ZdeF^oYi_)MjSk6>;vU#NiHg2djmIpVBxXtju
z7(xv*=Ln>%tM#H;48jh(|E92q9d}U#>ZI?S22;j5won*<q7`e~vakS<ZmmE-*{bwI
zmac}PBgi|YO8!bd9*Jrij+#gUmGW<dlnw2Ud;}qa-!P;|guXN*gPXC&8ig#Xsn;@Y
z%4>dwyUrZ3yQ`2w_F7IZFjGG|X=u3PcaRlVw6M@NQbVmE>k4a#8j7r?+b$$6CytSN
zUa$u65&K23ftEtKgq06zS(=T=TX00-J1-Ah9I`^HWG@Jd-Ex(~T=0eGz+>Neke{e=
z_*upo`Rb^K#7&JRWj#;isOug>hd~Ms&OEJ7$1sues(>OV9-<Ax;LCMO#d^&#X?JL9
z_&cht3Wfr}>iAlRrqu$i%*3N^0QUc~buMsn6;;AN_fE}lXBfhrVZb4vR5zW_K!7Gh
z77&-3P7^yJN+$$%1e8t)I6#1ih*5A;({y4JB0EH6W7cImG2#$;#E8hE3r%GG0?Y1Z
zkyQkR;UPqMe!4tXgna)~J+P18S2KNY)u~hGoH|u?>T#>?C6E#?R7A}cT&>nZ&Po{O
zONwO4K1~4D;`z@fdn$Txc$A;=f#AU*ppl*H5wB^C#~;eKUz~J0(YOSX;M)N!7+=T-
z3aJfR@&K4UfNdoYHYy3Dee8wT)RARC3bV+V2B<B5FjhQjMq9wix<eyYMlo%^jZ@~<
z^ypy#8>ey?+hU8?_({h^PsItFRB88kUU?1P8-aOo@a0c;Vu0l(%KH`(3bJ%_xUrOi
ztn-3D4X9k5W)?QV^MEEmtmkHvM6<>mlmLqbS~f~UZh+q&lR~j{FjNv{DOG;*0rBX|
zQ^8VDcV!i(RiK0OJnDnsq-zg$t5}<yikW)Fb(VMK^23!|+B{6~a}+SNHLvVrPOQ;A
zga}m0e<E&n8!r~8o`z3&_mg<_2d7)HLK`JS!RB}j?wiP>9ky2t_*ibyq=&;nUO{}a
z*8^4-%1Q0AmR}#D#rpKC9!pN6$4p5PZ6@_fLGiuirca56QhkIgUZF}R&e$O3Xar0F
z1~}U;6~_|fyCkmQQHUqNh(IqL9a_HCzf!;BSLN4GMuAk~7x&|j9J!$rN%+7PPx*7S
z3ne%}*R0z*PQakSy@bN7*R819elbxta&W052mQ!r6WP<ptttZy<bs+@uBRV}@Mfa2
z^fOv&By3HDTSk({iq2_`iaR^W7Oh|UU8vunlMhB+&e?YFDEKf5w1o%=k0FVOlh*zc
ziv<~i2Wz>JjI)yr|7u~qftWOgcB_jnTLb8byLN_%;=#vm4&{7P;M;-i#JcpVKvWP*
z$1+A5p(a}r84_po=|R?-^uT_p!nrq3G?h=W9O*3gB$hrsj6<C_YdKTJr(jy6U|4>-
zD=sP^L^oc_Pbb5UJ&9ne)Ko-xTLR$r8RLCqr6?$n`T&%HD{WhhE}IAu3S^v*fACnm
z|Mzfwb(a!L{o0?T(<*EtiEX~sxrjrxo>d!3AFPVCdFRLAu^`8rfqBr<kS48jU<Z%?
z*ux`!Dta81%0vfHTvAIZ<i)1d+Y=wxk#p?3NcEMH>Gp~*CK<~-D8W>zAg!je)@d0;
zRKYd$*wZ2{OTVooZhFCtG2id8cPdqD_Snp4dLn0KX?CaudTV_g7iN>KT-HYz7aPUC
z*ffRaXOjn1S-rVEdA*<U?!($i7`hPh;QJk_hziHgQKEFTmWqU*jc+c;mV*6dpwAx6
zAzA4Xin#g!C9zd7OL2M%T?UWO=tM}!BgGo{f@uSir)@?9burAad{t;;hR&`QGdWYO
z@8!x#mH`njfI-<~w6f#^*3#z0=!y6)OHrbZ1%s#-k;>E(+P&@GgLfVtI;ARd^_#G&
zeqGEB8hLV_SM`uzRKduD7@R{+OaAis_fe5>W1-ZYdiCNBA6b;xwKNHRmkt;d9-QY&
zB}NJ-EpaqyJPchY$!qj`BbyqedJs{$#8xAM4k}{#D-l2zg=x;g5?e6plbMJYGw#%W
z-U4w7R7zB#kSI$yiUpQ7YhqyUIUovzmf|@>pv~DQPGN0Uj(8tSXkbo((2^=C(vVP`
zS0LPQC|#mz@T-@6_7<q6Bp`|_uXP5f&OxuOPWv7q>ZdrOu<M+a#gq7TTxq;grU}#n
z2l{S};@vEN!L^RalzJPW^P)h#s%0zQQ@_OK@PdFXG#bx%W1QQ*npew@*}h(b3k>jO
z5Ks6fCK4-}XX?g-_Cf~Cn5OUO&dG}_s)WRc>?$Hgz<06H0B;}~dB^s7xgIK6X;>>L
zKbDHmN?b*zQMlxbRF)1BSkY^6CW?6|-xkZq!8VV<jyN9WN{_Yh;vZUEIozZdt#Sjb
zk*Twjmk1L0ZOY8Yi5e+Q#4m=DQ>kHT0tjfJDK+kX(y!L1?Mz;mwpckys)1!YP2grR
z*4?m)@@)c9CLz=6azjAsDzyH$T|>v5{niHs>EJ>l4pwTk;TH&M*?s$i1T@5yT3cq2
zNzDTe;)>7BI_@(xgT`3}m4&&hwcdI0h-4HG4q1r!N$Q%gs?b0|2cPe|P*WlXs2)({
z7#kXm!(;Uhj2|SC7}D)L7SLcx47yi=25(RtQe_l9RBP}9J&mS3d`Su7@3o5Jv6*6n
zH-x|zr#48+!3+%0(K5MqsT?j&(Hi`eK|!-qh<#pxlaB5Q7fUzsUcKCd>!Yj0;~;6H
zxNEZ6O-8n9dN{Y?2&8UEEtNX9=EtVZ93l;R7>HM3<26#dPK!s46z=vWuQK6GGY*2W
z8DnNNDTPvx*qT<Shw+M#V-~G~8i^}9jKt&w&9rMlq;er~6-=)R8^aSb&S`Nc@_pyq
za}UCP63op97EYiTY7M+0Q6(b?oXNqAatqUs8U>D~<|A&B4MZKaoNma5K($F4iOVi6
zF{B7pQcG81#K&S)HsgFymhS@Q7?BZ8v5p3TEZ!o&MVbL9+hAqipCDzAqk_Lj3nPcw
zZadc|G8yWImmh+<qM{Tw4Oxc3>M%i8*{aJ+wHv<%dh}Ga#X~;nHF1to3a+R`hQv=M
z(%b}R1><eSt3o9H>5XL2FxP2_;)`nv*$g~qXgQPKHXV1R{J!%ZFZiy&FXPl7Qo|27
z$;pxf;Hg72OrkOj&eLX;K{_e;DsVLQe!|{WHx{`zt)Oh}REGGVq3TqfVNDJ4{D*^T
z9uVC~+p0Q3@9~fzttA=<Z{6<5`!lRFI`Fm%m6F#h1dR3EY&$JplLy0b4^x+g#1U}T
zAwo|QIm*v!YJj7u@q#S*h}yy3I}?PX-aBVi<{&mhgW%eE02snipg##SzN%yi)wI#6
zL@|1bk-ih#OL8uC5BVUbG0I+OzCCeFgUS26L;!+g;Z<qT@U%+!NcWqcH9ti4_OdN2
zvVgTEiZuDr&yiNAyCqMa(SL9b{t;!w1dh_1bQ1$XUZ=c<!uZW9E7C*6TFHg>S+<T|
zheauA$@|Xxz|$d-istZG(OO>RN^WB@dg=t1fWgJ;K^tl#8MfLBSfq9ukEHy!i%Z!C
zSX(i1TUS6Fza%W6iYk=<A`r_zKTXW=EXeJNp6qm_hWeeR?If=4oYTAF29Nj_v?h6n
z4d>Oe@uDu)2pd_5>t<}lag(WP7Oy2VOzU-$w1~qslq}=kkW|b#0=KhK*L#<7Wt*6p
zEneV27-2p88oB?AmL;eE$PFV>jS($Bj0$ayA`l-ykzU)5l#`8GJa))}AF?pn1j`;Y
zua^oxRmSL~4N@$|Vr6ded-Rm!Ao(F2+OZ2+*OG*=4a1EwU@C<reLI;U0zU%o+1928
zHM<T~d+MU~Oo}uQ;0NT6b{DNx0%K~FiSfOpz)!sd9V5>r(6@n>kKCBXsZ-WLITPIB
z8C(@!o;XPKR@xxFGWh38xkTL6OIq0SfUzAkUX5a>@vDf_cvq&Pa357&sCbSWOd<_h
zy##1G+zvMM20fuJgtG8tX(;*hvw)~DT%olV=^IVoPB*S)-OdA19^0iseL@0p;R;{4
zp_X<r5^VuEaEjcuBH(Cg+LX9=v}pyu#we-{chBr5twPOZ!HIwphR6FZnm&p79z+cb
z_>fdL#@!+hD=ge_kww6K@H)_JY{a&JO*+e+AOC2%KtMth4aHssA0t8~j5Puqq}OVD
ze5m1&uZWs2*m6f0*Q@$dSLBB_^rq?QChd^=t9k*~83rfnRp#u<Gr%H*piMZ!ktKrs
zdr`+ZypT<XT&_JNfs;g?aWg~%B`8eBeOuTVFn(QcXmM|6*LlGO8+^xG&|D&>B>~o@
z5p5);h!km3whBa2Y^OS_8Pnbq5(lbR8sf<YUd@8(ne=L~qL<)2`DqjOisk%dv6ROM
zT15%<C)`7WP>>J*j=inz+`ugF91)SUxSG)P)UHK3qzcZ$r>#ihCt*rki-AEM-%Ub%
z#_b?$K7#X#S5**;0MhT;F-B9V3%5WwXhgtKD9@1`7OqK?(=g74tJWL!mH9b-ZKt&p
zXCs|BxZnr!{xkr;mYo<cIF(183s){Scx<>;)gR`EO})oO)?dSSLH^!r3=G-?Hd2w6
zYY|$7_;x;AVBu>((HVaR3)g0c2vyhPwDLEpUSs4?mfNr%*Iq9*ZF36=O_8AjI%f$O
z&8e`e+HiAKAd3(lt7_Rh5n|rI47IHaG-2j=NFGMQOphJ1R<&1^tkTYFigtBV*__Hg
zSt@NA()kKdXPW&g@qn&+#R{-(6)@09LRd|QDw_U1thPpz@z#_)kSMBHGKz_b+DqwZ
zj4dSv^05%5v1=I(N{8x^YR0>PT#0yfn6S2o#5DR$OdkN)Y8-Az1te7{R>v#g6sT03
z)xv1|!Op86SMDw8&E}<JLOsE$MnWz`{2s!X^Y)!2e4j6B@rl|F!`yzhcu>6xQ1rlX
z`@_(1*LCVZM+4X*@KhU)oj`(I9w?6q1BPh&L|;OK<4cvX%hA@d8ZtWTl6VLKq-_KB
z?n&$Q)rJ^cXlc3ydXJqrXlXbaYu}Y?O*0<xr9R;Q%~_I!^cFV#Y2>hB&|o~`Rh2lW
z-CGVRc>YIFTW7pPDH2s^#{*?WjQHybd&NWnAUMniqhl8Mkg>l@0}`)uTr-Bzkp_bf
zq{l&&BGGw^4!9A56^!=`6IhB1IB?~rhE`vCq(Trye>~s@5FFXGzNrfe4q*@&>UsrM
zyq07C^B^YPDuhUWj$~S!N0AvoaE@7!W9<e?u>wpk_0rTTNfVQj^TziDsw8)|ZH$J%
z^dxv+PC|Zi{72~z)<k5n@~|$g(#1Vg5Q~gyIU)kMC#fI8X9ES=l6a>v8NGOw(mC}O
zY>-^N5R)v!{>W;G*6YGusRfVW8j;e55Zr_XEsDpfcR%g5Bz9cD$qVK0h0?YFREO$Z
z;LO-TeU$T%0&zJF|JV2zzqKF)Xj^_`<4Q;m99IYpCFIQNGKV5l$2(|Ca9olS#xC1f
zalKxG7*0L39j@Jo7a9No8rTVM0K++Es-7e#wpMMH{5+MqqUS`+Sn+D+@#s*hWOE=F
zKk6ye&!I!p8z)C6#dy%<t7E+rb1dChr-k8sS6G*ndmQ@w$6i-BRZfsG8IG&H*%d8W
z2xT1?rFNk1c^21NzMtWdlc{a5NF|RLAKzEfY>%n5runP$MV_yqQ`W#wXzh!ToJcxY
z(vfsTeo{M{^Pm-bS!cQ4V1>5emiT$;kQ5KT+~ugiL&fE$z`m4fZXwp)$&51d;fyu0
zcYcOlaYGYgPNo^R*tzL^$NpA2#8{@A;=x5C3hBGc9X648$J$WFnWem-Qrs+=mnm`H
zXQA#hoFPSY|A!J~?#$d{jJG~9`rN;V{-@#(Nj4pwm}<v}G^!o4moFQ?U>du0hse(-
zc&gWdJ+>yl7b@FS9xRXd@-dv)4E^L-?@@ex&-uK()$-V+14ZW2Qk_X@pQQ!#NuwE4
zR5KDkqr=pBPM4I1{Vky;7*k0vW4#gc9?vp8K1!PMS=G3fW%X?J$?U}IvypO#OVY<m
zPSzzQ+D8A?pRhacAN*4F=<6llV^ha&-~J&cCQBB`PJ!R{qj{V@M`re1mh^j)FUeBh
ze^-f3+~~0%W<QRz-F8goKhz~-7H-9uxAUDXt^D3=`S`EcgCi@Mx#<$pE$m@Sfy}fi
z(rov6sZCfJkv_|cwQP_3<tKdqF7J%XcP)@EDT#w#p;UASraW$`nRHQ4mE06<b*7lr
z^#SRsI?0dH9~S1xYG~eE<*o8p(;Y?5OsUOJz5*=&+B91^zbHrVI<VlV`pG7~^;4lI
zDaGlUe82RKTI0I<Tf?mj(ls^Yr57y=yP}()h*uXASv+<y+_5HGd9N$GpxF3|@o};P
zV{}b5o7kT2l8&jGOfoyig}B(+n0-rr-!zIxs5`Su$yg`w>CVec8Cg^|Rq1Dk^8jb&
zMsjvwz<RXO;04GOrS(r2*^`Q)>?mO~d7;J}8pr23U3JKLdM0G`pMx}CI(BUR&Ux#{
z?0FUU_C9XG<1<@3?>^$OzuS6ZI`@En838u+9}cN(-FnF2u8S5X<x>{A$L`84+ICO&
zz!is{mJHARbmhz&bEQZ2%dNd;|I5~Q@42wDW81M0{Bhf?wM(a+KY0A1=cZ?k9s9uJ
z>yBM(f8z%8zy0LSJs;W6o$|<j$(?tca>CNr&nnIRS?u0=JWhW6!;8MTdE>>szx`Ri
zA9<qxp_{i|oE-b%OJ}_JPiG{%o;b}lZr;0o<K`o79Xb8e`4#)0>9*ZCt#spE(@xCK
zJ<E>2e5ITCan984%FW1KdWzlr@+ofDjdsq&z1ddr-SAzT5B!M!V#^~l2WOtM?6vrb
zfwyXR_q{cH<vEY7|ECqN-FwfXw_e|{Y{k}<9~>V3yOk^MeBz_a@BGF|k3F{j%fGs2
z<@&dpe?R-JO+Ol5G5B|%IXm;|FTQ*ANweM^U73IBm-pU!_UK1WUvbxdm#w(@_sdrt
zbMNQ=e9q}t{;6<9;jMK)zx?b6x2+s*-qSVw&Ot|?eaDj@p8ByH7F>1E8|7uUzx$c9
zUwL=hpElkzQuz8^OD=4l5O0{68n5`|ji(Gh`o@RKjoTM}YR9{0eDv)r7U#R(IC$B+
zHy(G@%5N?@`)9jnT(axk<nrdPK6LrF|8&BSYd`<9t7<>$S^Dx*E0^BCa&X!BlSymn
zs<M{vS9pxMZ1wJ*;|f>pSCPA~s>mPD-s%3b`r7*OWjnvVA-D6U4F?YPU%6;`<(sEf
z#(uf?@YY{Wdu#n~k9+O<zns3a^~=FU&Hqe?hyV5?R~`N7;-jO-=6BqGj@@z1i3?XW
zzBFt2#{MrYy7{sb7ajbe3qEw}tfPM=SERqX><j5ta^?r$%50mr;?@H{u;TUuPn-IQ
z%a1AV`Sb4KDc{VjsQ>%H!}ViW+PorjlfTj();ytD-v9jWWtA^4S&_eV(a88Ksa$vL
z(I;-K46L~FZ%-dN^P2~bJo4pBMs9nux^&u#OO`gT`gDGeE6!N<SI5s;Uj0b-^5+h^
z_^R7}Zh4#g$MxLH#};z}=GwoX(~!gGkGuO$+_Cq{>8-AnXYD%kzI5V~51rU5ZeP%H
zSLcSuzV^`-V;fFfU#K0szHnpV(e?kh{H?(UPfLz_@c3l-v6ItlryhUYwWp-NI`o>s
zUmd!%dexo#UAbcOY3Yuu?-|}PI`4}|ZhWS2<eI6M4Hx=non1NO^R4p+mR9G?T0Ho(
zuA$@h**++@e5h={yJOGt_?p?njho!&j`e46W~!KMy|K8y@Kd`i{>w9#jh_&g@7|gj
zzTuf;mp=8#)TJ-}&6ftgKVBH<zhavEc4gV3X>avj-g!pv<x<>R^S1Btl;zsw#1+ZU
zk4xec7ELUgdG@Xk{*b&clGd3I4Ng>ACrlJKo|=y@GL^As4&0i`z}ED8()#2E**P}4
zA~$%=Y4*5p9I#?++i?1|xygUbjk155+d2GJS}zaZd0BN=$3D4<(Rpd%YstWrtNGrO
zEOaaE8w10eXMMW0M=o<*+|@n!NU^_Xe58;bVlP<HD0h!E4xCfX-C%E!UUzqzGkI@{
zg=sSeuaXl!cGcRM)sb;oe#4Y<y8P402W7v*PnW;D>g20xpWeeY7cH&I@;OU8U3B?{
z<-O<37g=$rwIjC;F0CYslHR1d*Cu~+goym}OPa&{3#+b@uO`xeV^8#@1CNsRS6t<{
zKlX}$WX(UC!lt8o8;1_d)I$f-sgHdxedhN+p8Ci9Act)BsBEb$J-bo;)!FNBv`Yu?
zJ43pzA6RqyF;g#}|IkNE54?7f-}!?plg1nQ+*Y>7Y+!5g8nT?-!kD12u=l$&)1+D4
zKZkuDT)$*~ZuOGoxz&$+R&q;b9_Pg-&Hkg4tw(>Zx6yyT<hGxl^gL25&pUngOQp^B
zL#-JX+TY$*-P}0D%Eqq!|8NyAFuDCdWO~mRT#sM+kmS2rM!LF5{*30YBF`UIk)N)~
z$=Zet_FgCUvRj(9Cm(3m8hjsq)6Gf4)@@JzYlV3$e7fPXtJcKvKJ1g+ynKtR53jG9
z@`g8tD}z6um7B8e@}AXc!IicQy;j=vxt!cv?QPsOTwvvU@US_<$(n3Y2G{JBMujDV
z*~<<{^4ZjS%j9Uu<%Mlaj<?^+o-MqgZQQt-gSqPL<mh!#vj2ufsVy!TobKY@Q&-3N
z`#*ndGL-ANYh=1)58dooi(asL1!Kx17dyLVLJ~jGGp&5}%;OUIYleD%d3K9#lewEU
z-dHx<j+a~HvzqdIl-D;Wxxx4b@vcEXez%<(@3ez0&L-P4O~Za-b0QBkyVnmF?k>+Q
z+=J5BdnpVyDuwlz$?~1G?pfv9g~uiC@H<C}`8&spRrX*lFUS&`uB#63=UsWg))-!2
zm<;S$T#?3=VM(i%fkJgSt)<oUYHP!*f%dWo4)mobr=2aAeh|U-vUX8V8ZFv;W2Mq5
zS1g|<i<ylLrBS{-(0SOrG?G(KbZl8!DLe>IOZ$vgYPlrpVibO?Fs0$=8H0ER^9}vk
zB<W(lNVrN=v?j+ahP*!3EbHlNU`cDVz#^l~(rYJjvTdYmFZXfs(VlFXfzz2H_Mkg=
z%!xRW6@i>WWSB!g?DH%}!f3@i#}-XT6dqk<iy4ub@iH>IG_pIqjzAzy-qN%)-y<LJ
zQ%yYN3Z3H8Y1WBpl1!E}E*YvY!PT83(&_hPywFK{M9x;ecDmNlNT%ATL_T9gI6GM&
zePE_~=0~4x%E-K!To;%YWOy$LN6#38>3Y)U(Qz3WETI<H>-=F-h-OIH4(sMv&<&5^
zVWO@q%_gL~yU8P?D+et$p`ep)$$2&_S-3UN_6>`_YNB2_%$Iy5Mc`#}AXURWfZ0e3
z!p-@zY^(<wiCCR-XyTncaVwoRri&JC=YZi;?93Hsi?q58`_JS-GgZglh$&BgOGx6m
z%wXLxWn_+5q{c6t`9WyBzQ82{q_V2(;+N<eNXp|eFD(niAsINqt=4PI58k+%UNml~
zot|vtjJJ9tP}IA|TMe~wYzVg3SzLSVEQwW9iX4NZq9yo|gW4k=FEk2)t>OT(T<m)|
z_!&)7ncy-?TGSy11?dXE7Fs)3mb(o!6oPa7cnqTSVHCLLN%7wLv{xA-e&9u|LXgN3
zXlF5`jUlMci?hUM@GeG9<)dUN2Te5;Ft`YzDBRl%oy4g_2TarOM8qqyvW&x>6e^mX
zOodl{%*#X$+NKy*FPb*};yt_n>GyB^#Vs;?-<x{oXT?3Q|K&aRo^{K+fAPxKFFxhf
zE0*2!<d=T`%|G7u#yhY6V%f^?T=vKN-nsDiH~sOQKmGDYfBo+6Z!dg%_Zx?8`@4rY
z({sx^f4cI`FYUf><wbWrdCBYNKk?3^?;QT-m2ZFNb3eN4sY|~->#TP!zu?F>AAkGR
zKfH6-U%dL}iBG+J`4<o0eaXG|{p{~|pL5?oTz<;#Gp@Y%>+|mY;S>Mx?m74U`<Gw5
z?+eKGrMqr=>f(D}|H!^y=1kA0IP>%K-LG7H)tf&$efO(xp7E*gzIn+bKR9dJiJ!mk
z%U{0qzB8WMz5Alacklkq<?p=st1sX2`Z-U%`isNJ<0?G^v-Vle{JeU_MaLc273I68
ztggmv7V9|L*|FJaRenYXI7Zi(jVudBD~?~+u`7F^*z#e^n`x$)KeW4lMP|J;u`acn
zrpA_iyUXL=OcV2Nqp~YhhblH7$5NYmNMWyP_HN3xAp5Xie5!1Xc2;I4<t5AI@aY9N
z(=H$NoY45b9A~pqNCpN{PK{uz-Jrd?|2Ww`v-DLCr>t5h1JSzp#O|*Sq@CxRfmLy7
z;PrkPW;<QwD~IO>_PRStr!|Vh(|#g_`wucHt$6TO!?EVSCA;nK`0P1OCBEev*DiX>
z-)oE(`D9Jh8u4EJNU1ISzwah%SP1*~q5nV6d-d%-s^A2oq_Y1L|G(4!pE2);{QEvU
z?^AwH$p0Rx{*V{F_37Dyp|8Cc?->3?Q`r^UNpo`I$yr(*=P}8UO|wp$oH|}2)TawB
ztU~YzA+GVsiKsf3sW~3d=(!oeIOp3k@cxVhv%u4k$W5nd#WYacilh@HwL8Zc8)Tf3
zx(w#K0~`EwTc0eQTlUMu9*ZqjcgMK~tgTBsT2TjGlOJq&?&;!A!@9eLsW(0qe{e+Z
z;xx0x`3Hu8R$-elQYgnQWOJAd<MSe9PUT{QoyaqW^y^2wC7~|&sh#sl7mQiOj>NiV
z5pRY>owCD5iNC+dp5w5%?_1!<CQAJV<ZUL<6hpVbN?0&+K5}rX+oYxM&8$UZtdBV1
zYj&KP^G%r&mczuK9|{f5V{C4as>JY;swZqA0L`%frKwhEjNsK;I+2#$<F6CdsC8`)
zTGRdEqX00);+&Wv(+owe<a{Mfvl#7&o;^mWIKz*u+L{mq`+WylsO7xM;glXB7g?Dv
zK6D{ocBW2?M<g2-Q!Ar7z(DRAU7tf$#Nc8+-JxR$@`<zjv}><9&lP!iRARZu;Be%Y
zOB#<8&IZ&pQpH&#$?U8w<&+=^O1?n+DETTgu!xX(8sP>p(i7T_C)=7QeLo5bfQxn9
z!{!6V16mb<!3*KRbye82$}Wwv!{S>_6cUnQkkpx|McJhxM~;lKV+|a(vX43A9pg8M
z^d?$wYn{lF2eDwh7-ekXgraao?PruX01Z14+mtUd&&HX&T3U-i)LP^57ot?lmi@d#
z(l^9iJjt}DjAX1ygstOC%osoptA)IyKU?!;o_w*w#JvMg9|M_#;pdXA3yvnNFwL_V
z&pi|6poM2J^lx}nv_6#~JdRfx`mKW&`9pUjVvvM!6saQDY5a(>;vK=b5Ou<M6v`|k
zRkTba5?HaSIuOLg9h4`YxJ!fj^c82TS)v_Ua_|(Yq)O-5OKAmq8;gomv#PYQA*t9R
zi&J5=pgD~FzNCqXyTN$x_TXulA;7SV=>#5zq7E!zj44tJq(``-50auUFf@mgzG`Hu
zftV%)zBNRt&jghe2=5~$8S9jmqVzfM*Y!|h(D!ZJp*A@^GcaRs)dXAjnat$de6$WY
z!koOp4C+BYB<Rtd@v!wo(71p|(Ij&;ppFq1va2(wV;VGB5e6Lbkj_F@GjH2N8)!$#
z;V4sd=L9Zs*-QtmN_!~qX6Aswi2a;t3u1j)DgdG<<w)jI8di!h4HcBwF!k`Tz?-^J
z(yH(X0VU9!$k&L>YR;UFTob|caBSSiapa+8Eo_VoA#E?~(Livl+jqiPX+ii<2Hpye
z%KAnC9AAD1j4cM5j4GR;4~^<pwkix7i-?WXj{8AvU5o8}6|q4>HZgnyQg<D}kdm>w
zH!)Evai{T;6O_Pex8{^8N&@hW1*(sjcq~<|Nc-6aAmN3NM(>JT4j!GFX!(AxO3<o|
zINre^r4;)(8HTd*qauUTjY+b-8lOm&w#|`pQ5#M+)LD-`)?&wberbj&x^4R@3?yZd
zf%guNZBpG~Au?Qp)eCpyky=TWA&3=}AsYzWG3uBN;*m${y9(;X@PC+PpP6xorYas%
z4vlJDA>POLDZqP-W9&R$9t%dS`l_$(qQubGYQ2rouY;hr1@OpQ<Z~J(O5?+Z%(YO9
zF>Zv3iM5k(VR+pNw%Cq&aZG}H9HNd}O{*G0*KLi&3Scv>H*Uxp?==J=jgQNe|Mw`^
zHaZ+e6U5dmITQ{Kn>$7csf)ehrHPX)=%5j;vrGfj%X6m5UG06MnsZSo-z^`)Z^cnq
zg9s}&N%sdrM->%;ai}iq$}$bzIv5nBRN^CLylV@K+-njosR}>gnX1=2nxy=-I%j1t
z&pRu<#1`f;@^Bbay4YUqj2vn~-Lp6KNW)Q`v@eY|NrzQjNl(_UPEI>Cax$CnSY)*Q
z+sKU~Ut$->MUkA>_QSK>q#AP1E=Da5pL)kRmcEweP>G8)`>KqgToO;;SGxr#s*NbA
z_mA&k1BP{EaER*At9r4-Tiy$2=m=Om=uS<yHG9{1jm(JMf$G}2T-$}F#CZggQRGb0
zs`Z`ZG0ImZ4_Y^I%Et-s%kD}e>w2rs`0~yPQ`3k<JiW2r(N?FBJ*{XO{+QMxnwg{S
zctiP8oM}tEC6;l4VLPX(R!v>{tZWAsCFt0ZcB28sw`d^ZY)p(C>v{j@0z6Asxzf0H
zHJMHsZ!K?`BDHGs^!j7OrE+wBN%beqLabT)l!+`=y5VAKj@yCO8})tjx5!|*7FX?1
zWuE86B9&xM>HUiHe_%9FNi9$6nuXpI!co{<+I4?pbXS+HZ+6h5-0$z<WB}dQ7^=^b
zw>Y2tGUA&RT{Dt}(SXlos<PC#81BYfGj_yIU!CrBV`uRCUMxbEiWqfHbQ>E#oEh-e
zGfwDA($QX7U&vrD{47~m@ujy^r(G;0S>Bc%iETCG<`BFG)&cL!!hCybbEz-QD>*yl
zbFDqhXjV4LSe}lK5--{)QVSS&73oH5Y#6a!q)f~WwCtA4KG2t<(7g)vhKyIBJ38oX
zjn4-rtoQUZlkG{ghm8uAbVu1XjVWd1IxBvA?55@$(UP^~S)#gU&+k&q%uHDrml^d`
zqlB}hrR`fY5%KYqD&I0cN!V~eg9u;vh<0>1wcl3sjh&PPew?Qm8Lc}Z(rJbrK%|3;
z5C2%G2Led@VWDpk(Xi49h<a<gRi3-+lcomKavb$rsxy>5i6DvN_>xvjwR>&XY~N59
zPI=}ssdTDIiWvg|vr)g#X+>57F12&Hd4pFxRb7n|j&=c5>H5TLPP_#mqX6Ts0qw{G
zeP8R6qId@wP}}K3n;arDNN$1DEU1bc%OaW-{B2}CcYGmDazh9}b8J9;h}AUIdL+{E
zP5{M7M_7=iUjdHnTWD)1s6ps^HEWt<0|8H!;d4$(#Zeeqc87b#gsJf0)~OF$6h4mR
zX@RbY;p(&iO##b+V2<}XsijcaUHG?&8CBxsK!l2mBtxtOnhD}#wBYlWqOEJ^qSD*m
z>FAu3ot^-7o)3?DY_9{^CNa-@k<>7d8LeZX5nEyhBJ{n-q^j3(=>-tk9(>LNg0<6Z
z<G0KK0H?A_beP*H;kA;JhV@8MB*a;HEl&Q$QU3hNm^?}dk`XLj$cYTaUSgNzO^A_X
zJdmfmQJz#!iwM501vy!(g#P2=I#s=0Qh^C2=pd4h#njTnAg}4dzxAFYh~<zfNv1Ir
z(FL<MN#3t2qOwO;V(?p@-5GX0xQ>4t+Zszamy%CQu{dC9mu5TEMXpB67FiU=d^q?G
zVF#%SA+5+dKu}k}W@7I=G~m;ut6=2ooAe?Y8!qaJ8QR%Ui&ae_w~TSoWJQN>5_%cH
zocE@tXtF#ZPU|<shw560ZNJcB>R?05Th;FX5FBG6<GDw@_|=3#&ysoiSk(teR#`gr
z;?Z1LC4$pvk3`2Qeh5(!G>UnD-E!}VLt$vHNfp?^2wK!K__{V7r?J#_y+J21QI_o>
zol^{^gKPLSPhXfD5J#cvB_vZhRKCcI9>j?vR<u!V;0VbsJW$*Oj>Hk=7M$1QV)>EW
z4F;CCH#zA0=VXQum4}QlNvnp;#ZHo?i2;2We66h@wad4~$z{UciM0P2{&x++o{*QW
zQQA^W0qZnE+o<3Jds1}MP#$r~3T;tSG(6WB{$$O;sX?JdwIHmQYN5|NkD_SSIgs!|
zOB)6r993v9N7hMbrNd#3QYAL3L+qtQd&bSI$wbV}jL3F|^?j}jI+`O`V7xqSnu~Qo
zeaH~Sat+z8w|skMYC%sJdswgUu@VZlAtmv7-l-vm)OoUj>S7GD&bD>hqzoE}1a%~!
z_GwlLsM$stgkjSn70pILlp{?rE7aZ?<q?1kw@&pL-Gc75i7IzZO8_R$f{kxFh+2+U
zJf#W7fK3-N*XSUQ7khAp4`lG^&K9x?31EhLW1M(zl}=g*hNJv~ZM9?giv}k1B(1~_
zxnYR}HO0cIFs{Xb(SgX;sX<DCPs30fT|`vBbP+L%FSb;Fy^Do9bO@0#&4|oby%?7Z
z8D-F*r3lVmrX-Q7rS1ZwYG*;pc#W5~i*~?2om5r#r2Vj(W|DA|{6X7MFbc%$jf|EY
z_i3P&th4~*d^=GbSpvp!2}HOP)xsDQ(HV5mmFX@i(1g}PYtynNYbrZcb_~B*{1_$Y
zxVKgGz9%BmQAs32kL)ywA3`bUOL)UwJ>Ye5RXoirnR6Z*K9u(mP>I7ik;DJ5s9T!n
zl2|Q<Y)lR<9><S5gl-0<TGybn7@kNoOI44D;AM%|LGWV2k*20{BNbv%ma!i#vt%~l
zIs324$+~qYuSR6d4;AtA8l??elPef0x+LrIIa;v|aB^S))EWp0A3eyTEj($7^EUPf
zMJU+wQi^H!(&JQ290t~Lt3fT0uM;4CNeh__Iu9ERm7<~~nIf@d(pD9pd)yY1D;<m#
zcP>a^M6l$^gN$@oUhKhcTd&50G)1qc3Dn|{(L9he%||fwy17?rIZ<Vf65$o4$fZtV
z_^1OFiNtzg2oSvBSf1<}X+lFEsB+b{FIOM*%cHClb&>D@UmmEaKUNlH^=T>L#*~}2
zB*E^Q03z>cJRgW}g<(Mewv9)S0kcP&XA8EL3(P{MsY0Z{-^&j%Fm2&nAyrrb;Ms6D
zD&i`&@tU%&7#mO$X=aI2haA=5QNQBFJ^*8KjeQNSt&^^HfbD*yQRn%OBD9;AGx5t_
z{9xt*VR<kg5(LRis#L|Zil-_2YEDKd^-x~|r4W(VYh+s%d#v7^UT{88f-DKJ$bQr<
zQ7}vhiyLUyWo&_I1{DQ6o6+9E5wA8y(|S-H140{MzN%roJyL;gO^heNId85NRg=-O
ztbT+Gw%;mP#{|m0EtrEmF7#mP5wSsa%IeS6GU2>l${{B8Fjgv97th@$ktL*YMpIG~
zXzoTc<2~W&fN<6c=#G?rM}e^G!bk;th^v^Sj%X3VMWk&5!EltU!gC?Y64O#&<dh|D
zj9&{1ArOj2<wF;XGQ{NhS(>n}XoO~|wTRh`2TGQFJG~gEenRbGbKs?k3?@^BK?Yn|
zFA|9k6lo0FZbqOI5V(f-6Vcm<w?u|&XbN6q!KdwGdxZu{`bp;jM@<qs(rSl6UM6GP
zUz>C+*?3Xsi10|~;#%cFWyNuZrsk!s7Z=KuN(~@Lq-jXuOEfE^F#YOJ+<>9N`zKYe
z#64`e1wIr~MBDBY3qVFe4UJRd(nfL(QUtvI)!f@`m=mHrI83faM(71BvfP3fi@3^;
z3NG|k;f+H2I<Qf~eS4A#Mjd#qXaa1Y-f6K`boGw)9$b_v#SEfgS*+*+0fVk^3Q|i)
z=YS}|cu-3wjx2KVOJ(h3kx8xBYbUSFc)SG~tVXpwx+P9LnEeIl6Ali<(AYd!Z3<SJ
z8smxSNy_-TtYGNy;56A>Pk2(vI&Dq~<AV8epup2xCC9&}VBQ(Nis438nx;4f<20=c
zK8lU3F1~%I$V(TA0;xF;8{>&itB!itBat3oAqg)@^NjDvHRanUj+!hy_?8G<bmF5*
zm!h>7s@F+DsvtN`$bU*2unhlE+2SM5eRLi+JXWAZss*G>uw#z6V8?TKX7huE4VA#*
z4XzYOw%URC{;E^jqWuIevT$K-8+s}!H|0v%;#{}}JEY5>B)b~<XDDYj`e@otYjv<u
zb(uD<B|T)VDSA@3VS$Y$afLXg(&Yu!l}%Q0<90M@fT}1KPB_-4#G{NP8!88o4(&$O
z`Ea$Jq^6uS+KM<0aSN$Kc>@I=@l)qD@E$4k?XTtd+80A4oySDvA;9M-f)H8_`MiVh
z?iwGgy~;-3prI8<br;(Rd#w_yWa^syw3fZsBNEhP4XK5k5IC9NY94QgXJib~A!XAR
ztGo?GjoYu$a};{Rwg>Xo$AwNS(I#NZA4g#~r4|Q2A^wP86Z5PaVl3i?!J+Q>rwDM~
zhII*MB09zo`Ur6Hz&o@7h-*?wp+x$9+X~8P9zwC}+H1%nXn|!SIdJV7n8rS1qy$f2
z5RHQ+Ycsm!r>PZ`+7ef9wO`Y*Z<FoejDhk5yr(K8IYov=to5!{k8ET^CUv$IIp4Hl
zXc~|85$5rl@DQ-lt2l(U^4pFu`RtIocur=JR?i`!oE9R8IMT=A?ABl2O)zA{BDu#v
z(O7la*Hh3Mc7Xd#q$yM)3bTnPlsPmozJy%F1;WNS5Ukgbx+a8AwpJFX&cM-mq%T>?
z`#S7BT^a41Leo(esq&2a!LmGX(LoFGJU{MKt`3B_(e7@ICE!t%V@Rk82y5k9C$17Z
z=;98uT$B_y+p|XTEu+-!1RX!&lVCn>qe>lC*bP<hD8FC^Bd<V6>HHHW;wUNTwSmxR
zAq9c=9MxU>YU|s8mQy-Bth6Bvt08F6cf=lmGEQ@ifT5BlUQbTY8c=?TusTaDlBhcH
z<7iwx((eS`N?E!n1LwVl!*_h%__acDr0aBX6ORA<aE@15i&V|xsJD0jXn{vb<!|SU
zE$J_t>t(EH`-;x^@AGcZXIPi0_e9@kHWq!m<a?L6iH-)J<vxa2LTEmd+Ttjmn6aO3
z`dEDZg-iUYRJgP;w#RtwFbe1=$7%;Lx+c#gfN5cri4T?4Y4<HMG1G{*wl2}hdHKf%
z=Zf;Hg^-cG57>(M#kcn8IjotZfZcxaT3Xw}Rrm5NERMR9a#s{b75asaT}!3wABQ#`
zoJpLS`n%pWmKC#ZS)ALqF;?D|JQT&fqfu2$$JH|p**n*YnZB6UWRwb0^8HP<%bj!#
zk<=TNTu=1X1Esdh6-OH<G;Ow4lZQB4`0?NT2U~jM?w@$}wD3xW`-d=aw%KYmm&b9P
z55?D8-Y120xT_Q;Fe{rWJpCF=)1HTU&=tpVtBX~AX?(V}p=L{ReBX1Do+tUp#m09Q
zDHF2@0kg>k)PQ7;J#K+H_GI?F@UC^~?<p00$*iUoB%LGPMcF%1X}u=%tk^|0Gh<xl
zx<;KtMwCM+>yrQQsL#Zu-cF14av2kKwrEpjGnCEdefO_vZ9kFGO~d4PO37n~X2_tI
zj&obN=~LzUQ7=bzFs}0F_e|JPXZm|SvA;XT*G-}7E$`4z9w}y}RChd2?~doqnclfk
z4lrqJv%j`?i9OzlLBtBLWvH2<lj9MpVP|}Fv|!ZLc6Atd(WkpXS>W%tvNV%@l;z_r
zBgsOoLq;1n*9wj&iZXKaB36Ai#?_969L3xy-@t}uGsAvUs2Z90miT@jm))9w^HD}e
z#Av2A;XlJtD^-LECqw0?j6a=w;9CQ1U%I7~#%`;tvTFj1$=E2@e|@fK*&|%d3=Vn8
zxvW`xvy&lzteu&-^+UFN1N&i<bK_<-xKt7yA4R?K(B;x%rJ4CEwyFSZ?wwtJ(E08|
zgx2I^vz(_-f;%FO*X==nDz)ie+}MI?5?7*aRa*Zmvhe(L>#XT<_lOr?j92@3>Bzzp
zZ%FsWid2_vFL(@e=l<2xAOD-ytZ5hPnUK%i1jV7hxpB>J?!5TA4<CE+d8co<G5^_9
z9@&1wT}S=Ps#&)!efpfg9yxF5*R8R;ru}s1ozr?hyZ0|&I<I(E@%m#o&Z*xuZN_ir
zJ~4jY;uqcHH~z5n$hz;`I&H-{TXGlAb<cn8jnePG_U+q`UitAx^Qcpoo_6)UrC-#(
zeS7ZJk6*Vn^YU}gK6KN0&(?0d_O)rBxNckF;^!`SVqoInC;G4bUgm;-x#!L!HqU*c
ze`DVP`(3+k)y4nkk<CZkwrt*+<0G@r*nZCsj`+fcyQY71@T@b(FWmFf&uqBsi1Y5b
zE_Yl0w`YwH?tjiBV|V2q`2B_xZ{PazKW%BgdP@5Ejk%G-cfaFS?*6^z_wjFt%scs{
zmwP{c($ly1-M4AH^S%pSdGzg-%Rcquud7e5d|}u9Uw+}G|9JD7Tkrn&uTHuAzQ0di
zyZ6KI-o5Y-FI~0pbFVbtUbCe6_H`qF{KGx@NB;2L+n;^wq#r-?$nBTBu>08~x9om!
z%Zs}oJnY3MHZMNyU+*jb^}pVC$@EKa8F}TOZvD=)FW!2`3+LW;>9#`-TlTx}+`Q@8
zx9#n3{?Xog_aFZ3)q8$+(!@C{uh_M6_vglIe|PMzs}DNzm78AK=XV=k%6w<bo1edJ
z%L|>i_3S?Woz-t1|K^kbaO6u*{zLxVEtl^1`SE`}@t=3zx9puq@0)qk_LV2Ceddn`
z-MnS@%zK|(d2IRfyC+;`cR2H-@2*JpI_W`Kb<#iPKK|of<NMz<KJuv-AAN4<w|~C$
z!HbWoUi0PE%@wa7_|l!P|7S9C@5^Szz0K!eTYm2ITQ8e^{;h9cx9rvz*Ni;!`wN#o
z^7~!QEjxGI`r?i+9eLR93zlqpYVncVpO}$-=09IbPP*-&-j94`+p;5Puf3$}f~9xd
zcJ7QjZkgTs%`2;ZdhX4g_3_;kX7h`0ReyKG&rW;!&fkCT`M<fe=b3$09@hNIhyJYj
zm4jx!yy4bqFKxK}nDLvRKWfV>FI-gadb9dg{Oa=i9y#JeuWUGR`hTwdSnj3Gr!M_n
z{fPbkb^VFC`g51fu04O@M^@KYPXGF*l^@HMU!Y{4o*BM%^HI*l%)j^ihs+NqeCY?}
z=jLCx>*4%oUcMw*`NHqyr0>2mc*h|xt@!Tfg@3#8pY!$qxMj_bFMMm+ZKr0(XT0(3
zuIi0{7+-e#g8KNxlJXvpY)Mvs|M?4d9njUa>DgOGzW;{{^6P3Ny<5ib=p6suA*HWA
zdq{bYWA5(RvhBd~p64HFKXqv?|A9Lax%c)dbH4WdBhAmhe{%B1vxmyRp1bGbvA1&e
zr%&Ya&mXY7c=MJ$Kfms}4`oZ=&Wv30`X>*b`cmIC_soYgtAEyaNzV=G)P*-4Fl+4M
zuFd<MdhGbXLCe>!y$uuen}+6Xgy*G~|9Hhpzy8h#<~DN8^W0q<CrbC<a^%p(Np9{D
zC(k(fj&2*>w8O62II-)R^BVL0`AzYknV6`)ke!$@J^NhsR^MEDODjnxc1id5#y3?D
zn7zfGxjnyO`^M^qY|i**)o*%hW9d6f%B9<8E{bd4>+4z58fqT%K)Lxvlk2pbtxSJ<
zN8_>YFRu@u`}qemi%+}%ypxN~iQyHSCX&PFd}G@}ciWE^jutncJt|8VPu%dQp-nfw
zmHtcIGJf^y#gE)DW%lDgpEA2C53kx7?-gx!fA-m?`J#QvicIJ(jIrfn?tJdHHFD^Z
z?PesdfBZA&0-b$HdX{;v{z<cG#xGyrl8n81?w_^(c)_`&$9G<o87hC|v)O9)+W)w8
z+qECP^jqIJ>fA3p{-NJKUp(=*KOg9wyJp~}INo>J^WXc)vR5{*d-%4S$KKfZ%+Awl
zGk?DE;pty%J^Yos@1C>I@4mQe+wbHzH{Y_cb>rYe4<B>RsjsYidh?U!npZa5eC-{Z
zYd=j)dRX}bkM8-~yC2W&s@}6Wsri}t`lEYq@&9tiGnt*&cK<ZH?wVEE`x~{|+{gY;
z|KMvkKXyv?Tdz%7vVG#Od~JNpY5vlKgih^8*=Xk5v6ua8wbJ~Wm*T19@BHTVb8}0~
zS?)sfZ>Ki>=$y>V2hyj{9bGv0+~^^hIaIXSznzg;a_#2nhkf_J{2w14vD-Nxa`S!%
zMym(v^VdZ6bFZIBvdvo8lEeG~hrZJK^EopgEfqUzQK{$Pp&i#g?WOi`($l|2Mtb(_
zwNuZYm#o`y{$Oq6wB@xX>t8#%qMZ!{v=UvH$(J`Qe(5J;JvY~OOs`67kGcNt+5<e|
zeM7p6|8}r(yc$Ig+_>$RpV{=%UYYn3Q!0+Fc`lskxt+m5|G~vo>9fVSmj~7|y6?li
z9ok_vyAuD*oQS2IGA~1!KeyT4bN#1J-fQ&UAqL9xlBhZ56E!z47I!`)^Vw(i9X7vq
zviCiu=IpDZ33FtJkGK07y=<r}T{AX(YEvpE&-0kIYo1Pe8-;mm{R-*HRO8-$*Rz+G
z>t@MMs$*R)ccU*?r~9%@X*#;svaeUY>B{&SwGJnji`&|NcwE@lQJJ!Oe0{O*x86Kw
z^f;LqZSG;jPv1{w*X!|+7qP1!@b!4}nrM&JKAOI|CE5L4Q^?baj*j^E_;PC;@8VnC
zm6w?DRwRxQKoT*^VmEH5c;9e_RghycoI>_J{L0a&YouQ_`40I?&#Ht`)<L>+jFBsg
z<_yBu$b1H%gYsirkXy~5%L3asoAk2#Lk={o7khp7Sw_cB+7E=B%(0_VlDSehPI&Xb
ztln5G-(VNWolHzti*L4oF|-lmOB|l7@xj?f$xvPoz_%`5V((a+a|~=MGT;}sx?EBC
zaAvlP=L$JLp=WxIo6A5b7tMvYW2({Fs_y4ekIoy{wW?N}?c-Tvk~W4UUysthq+XEq
zoH^ugNU1x|IeOP6iSzMVN%xX6S@tnP@Gy|cWNC9cO`K%>xeWNdMUSb-av6mQWAK>y
z9z&NgApwGW_&F$eM(WF{xrx^|UFJ!DO1D(yNM{jEW)04ev?$F3Z8ByIdzRohSV>Z}
z9j8kN2a_U?Ow1U24qCFF1`yY;aYz;Syi#FQ{9TF`m2sRqBAp|jHGaXxz`-j>CtM5x
zD?^h}HMGfckR<vNnHJB;RbRw8%BKci7x7|z_zn;9c%3*paMa<|U~owr6pL5tJ(TMJ
z@va@moxMLgFvUeWe2jGs!h?ykB(-oy2n~v{VYb!=IfWpY=^z?Jsv2Sa_4P(vN1+`g
zCXh^FfuKZWq6&}5BU^gF@%#dh4s@-aHXl+dM@=uXnjc9b$#D1J1gPrC1ssh}I*2$P
z54qHgLtmd`fv#mAi0Mt^l`X{DhY+w70bpolnvXQg&qY4NYnq)R!p&(OBbJRii36g#
zw%jxPih8E!lrQ0HSzRGYUOMOHH<#V_>v`|K{^l)Gx$pI5r`&eg{8x6beEbJb{pjA)
z-~HjcD_=P66K{X&qPxES<je2Ae#Z|lx%7vpJ-++r7d`&(Prkft!H?d2_3$_Oj?cS?
zKl0cA^qbrN{pEK)e$g*>?|xzTMQ{Fk-fx!v>_7kgw?{p7>F)2G^Y)u>zWSS^KK1tJ
zAAI{4r@sB2zj*oGFI@D)=bm`=^cTPT)Fs<~aN2FVe{s}5y!6{wuXuIKo0s18!?SLC
z;|o{*`sEj2{lc%eeBqKeIP-JY%A-E|&M7aP@zm{C9QnsTU2^fASN`bpyDxp=bGu(z
zdC9gLE;{1JpS<H!7hlA8eZF(WQFs07(ho1a@{Y6LIehmyN#Ezo<TlbXKVNuKctFWQ
zND{5;P8w0t`9Ugo;dm@+M}Bbj2QcD=#LfJ8^5uS?lz-6GoAy<uHs0wQ^0RXOV;xdF
zZnNaGhR1f-EM;Yd*IiiKbHJf>Q!bY6&_g@{k@2Me;2r7W9W66^!Nin(zSGQS>%R55
zxear!wD$ViDw~e}xD`u}zw3T!ez0rW&g9%F%{YI}=B{SZ_hwA1_upi*IeMunq)|!k
zm&U+$F$1$Q7=fk9jwm*>_7E|fqRlMuFhi2fYtw#z<JMjupU_)p&4#=Nr};fj*O%1!
zaGkt_`t{!d|0{kns`)?B<1Ve*|I1OITMGLBMEx&Jf|Goy?f(5pYN^)k|8lfs4>kK=
zkhbqVfKznK^*zV_(;+if4c`-~{!SMUoul@9Ik`(4^+#fzO<LXX*o7^vvgdd);4U$)
z9?Y<e=<*WH-sSoOO*g?KjygCe@8McdV?zk7yl5hJBS9+XJl4o8p=G)t=%bpiX$}jU
zc)?OttF)>d=i6uZhy^lwJ^O);GmVb3qgJD_#2T#9(eM{jo*s{q7{}Dv7rOf@R&4Vg
zGZPK5<Ygtgn<hM^>|0~166c*U%^j<;06vN7JDf$#WQN%h)(gpm;q@<49ZfPB)NQ;K
zeX_9`8n_)}R3YikadMnQ01ATTccb~piZuFqlK#X`ho0rHk)%5od610Il}X&Zey~B$
zK^PjEcBs>DN+K2~XYimSmR?Wqday=7%37>)*O>gh3M6~*OW9FV+m92gS_jx&K__RN
z1$R7+Sqlqier8<;Ym03|b;Q&uFrHr#E-Z}IbXk;5Z--yw=|rqd)w+OvOdTSE8|f`P
z5l>;-dJsgwO|Xrg(IOfKJPKb<J|N#=L*;d;Gd@N(>C*I(b0STLX~e-PIXX}_u#||-
z-$@)xQ;7jsLt7+EB1d<p1ux$Myq+A}>!m}y))rh-h4Ju~N>gf#^LeNeYeZn7d4(2?
zg}s?APsoi1+U&%d?BxUrGzF2?q`sjgU<o+@Dk2iZy?%<87QK{$(oQ-qPq^EX@1Bq}
zF*(JToj#H(Je}Chx+X00@z`-S9+FzfKAPoeDxffKhzE29zDAJSW)FHEFf0kOG9=x4
zrf1pV#LGSih2uj{&`4lUaDg+f#O`!9`-^iS&s-fO;x;x3WFTpFLh|WIi@^CCB3+9Y
zw;b}h(2<2c(6!(z9Z8eqENYQl!}>(ECt`(717xB%DR1Ho7WHD*C}GmK__&hgq#A{$
zPcNvGro5Em=Gl^?T7=JVcq?qFB+jyy+LsG@Pe*B!qEa(%p_=20oQ;m1L?%BVZfJ({
zz>HU-7Oi(V8hg(`R>(`IGU(mGi56aWZXn*>0-Q)jPzz7>7;?Gkn4r-pPQF1_$c2?|
z4^FG(!9n}hcXNyVtz122VJYTDHxJaAEP6pyEfNNX@@){111n=CqNr>fL<Z*9^4MWO
z$9{zlYHl9(m>n;p_Fy7GNIK2C5qA}Uob%-@E$fUeAP*wwnGlK^{Y8Al!ZR2bUO5S@
zY@HVWj-sKZ5+(%QIZ2<Y40cd1OQar70x*Wn;Zd_Ak*4N@Ju$mBt#jC*mf93j@gHlB
zHm3zvDLq-ku$LogdA`U-B57h~xYeDa(&XzBGb~s6Qg08zqo*^Jg0e9D_@=r7)v@AQ
z(;82>VMeW^9mz~&vmS+m9dXYi9ZVBtmP?$Qe5Mprm*YB?N6A~_puw{a%^N5v5RS^P
z$aRY4jGIaaTknC|0#KiEjJ;`dDphxHPXvFUKFYVXOrQs&2p!@he%KhE*aF7BtML$K
zCOB{7gHc9m1E>i(-yP6IRab<kWE-SbdC*fg_?Bmhi$l;#1bv&6X%He6$nEd^gjg=H
z85&Y@c*^2{M5uvm#sF}}#ym<-2XlfJI;crvOG*l~&Vb-q&JJ3kwAH6mhu~rx@|m@+
zm+zA}h<k-2rj~qQ1(7~|GjWI3&&X;8Ly2u+Jnb}gRZ+(`FqD?BIIcwJEqB_N9^rwv
zZ(>`4_;fp091;fcePXVGA0-Z3WtvsJhA7EEG49OKM}!!SwHS)ko?FGG%+WPh)Q}~4
zo~3D|sukuC<XWg?LcNr=b2xNOyr>EOFGnCLiBq8>8<nAz*L11uKSVRIVjAG`I($S$
z7s^U_#^EWA80s*=fIB=?7^^qZBvsWdhRls6GUXTQ_53AYq3(Nw*Jc#6UB0%+prD|2
z)h81Y@jes;h_uT*R~`<M8b$7K8NUctVG_puXkpX266KG#g3|W3UN2T63vMK(0X9-(
z%4O;^HkAFjO{V0yisap}tsqZ4x{gL_I&)DAe920ujri0c`^`|9r%5?e;k}?_xnSWL
z^TeaqGN6H_x`=y8wVBA%Y<pE*>vZjV7W2OzRaQl;Hv*Pv5%pDm;UpF!3gCU2yCpqy
z@Y){c<+e8(sC#oLHB*XJb{VCyt?yL1T6;OI$|Pe0fR++w$>%qF_;KKaVS~)z14w1&
z&#d<J_UK+hxyF_}NrQ{5@b4PZp&P)H4u{Q2#6^h=4GyKf85yi=mE%b<QpLsM*5qWS
z7G5*x;Ni7ZCZT-2ufg9UN|!u<MwVhrRo-sqYN4t|;~g<`_R>(bC`Z->*MBU8pkw2^
zxgXIFhs5-D_qxmI7A}$1{gQ)CW6>gCg%t%A-C&a;zNT!VLsCb{-pY33rDL0rp^wwK
zjN^D$iM5vbMrRMN?4uf#;(-!oAR9@Xk9dmjqn_)p7PpK%MF^XE*Jx#A-~Ek&Q);@B
zn*He@BW*S|M~00*6??zRXhvz9aYg#dj01)urq<NpjwriVGCen7(poasr<&Md#`S<y
zUtHw*=A*h-r;A-_R^+_V<NXAm>f0xAttNV7*Z;#b{Qm2wvpe2Y?1rQ#x@M1bA^Or-
z&TXd83+j|O^3)iY?%!FJ?+S0}a~PQLWo2i)?Q9$%ah66?I!T7A`Gmtj+0^XMd1Nmu
z@|&Vn&NRX~JKMc~_e}P@tzzPKJz~YN5>IMJ-eRnl(!y{wuP56@qnw}S<3c|2m3>nC
z)g2wOF$R^sp~~sfPa>4o`LGk046ssSG*U-7DmYo<5|=z})P~9^)>4^*S)kz%$x+{`
zDqmyuk+r7Jgm$bjPI7BU3%UR9EP81}+SjJ0g_93N*x)5YBHFx{Ydz7F%#DeBpA1ac
z2d@zf*c}Fq@d#!aQB$uSptB@adL7cjZr89&%0gkm!N2V+H-@9ZTF1KT=6o~BbV}CB
zsF(`$Lqf1JNgWcS_-Jy_D&Tw1S+E>3dEh80fIZ>E9B`z-E4D=zT@>Otx{@!78mewg
zI5!)>#)q42BjGo^zd&;(qgo8=+EH3|EuIx(Vz3EN&uCmjnWcU&a$y}j=}uH0<>OrH
zw09q9ca206Kyet!`AOQ5iXDQQ6!j9Zph+g2@lp%<R~kMROGY4DjylOLU$GfeIL<H{
zlZ-PXp|_0{)Lo`x%b3&1;4ndMAwEB5yyx`bq42Q{tw$*XL4h`2B}fM!wNtnx%}5h4
zT97CkaERd@nbx6)VRjITREf<nZPO%$Fkw<cK?cc6tV7|XQwjrd8`MwzAd6ll7NbYR
z(Z}ffQYsaR-K~}z5e?b{Uh0Oo(i;X7q-NiSSb(@hSJrHt_R!;}Lup6Ea9v|a1dD<P
z#YN(5TOc}(AtJTxmOMce^0r-Dwi2{);1hNzl>pixh3>^9l06oTyOYu=F<!K98{kUM
zjhWQaBw(vP@?&@=op&zqZt;n{_TpkY0zzW!dq|oQniD~<R+!O?@gW&Zix7<>qGF1n
zEupv|TRciTa2l=JP!wSkcsI9jgpNBsyaH9QAl=oGQ?CPHf_VuomVvM(Ie_VkA2U)E
z%a}5(L{PWAFDM%_Nm63N5;WH$QaF_;$xy+Q?!^U-1CRZKPW7d_5wEoMpVVF9$iDHR
zrATCHj|`1^94YDqxU0hih8x?Mxkpy^>*hnu^N<apdb(x*V*)YdqzGOq^MZmt{O<N9
zSG8o0YkhJ&hgao6u;88<3O7<Al}=K%tMXz4lu5S(&Yl)FB>|zT>W#Kc-NHi>KzP~A
zp=5Qe2`KhN;GFI<ls>I;Dj$YGqaj8(p*0T?m^}3$E>BcHKjJ;tj=j>@DL1sKvW{s)
zVvHFgJ!F`>D>3dU2(<sl+PeVAQB?{5r>d(vHIq)LnM{&NNZ@v-6FLuYfB*p$ZV#O>
z2?GomAiO&e5F`k?pu4`fJ#^v_0uC%7DyvNl5as1#6?c8mgcy-UMHe5dt3(#TH-0L(
z>m&L9&aLS%@<qV?e`ltv?mhS1bIv{Y{iv#eVRbY2GdT#YRpqEOs47b|zLs@?^VOFA
zLZQe{UDR+InJ$Bq!c!y(N)9D4>jPn6X_W98t{!0O!RWOd2efu2eL!~{G;n(<s7ehd
zjJn9!Lmu};@TY%J8lOPKE>#S7e){TQ_0*bS<f<O!pZWRoYf!ZX7bUX(sv34G9~vaF
zTDR4$P6-Tn4o}nH8b$KcTgj<K=t#7NBq55xi}sPcNhJ}k1bx^G7r@E^i&<*=)wDa<
zI;Ns$oFjfIW$RTLTf^ys8is)kM02%`<>VT{20h^)P_Tqp3UP<Okx{qvnUD%C{1|Y$
z3V}7~(SyW>{n*c{q*O;#=ATedS>*?Wg$SJ)F&POeT2P`<lu&S3f~bT_i<{C1A=7J<
zsxAc(J(e{~VLTs1uI$@vQt#UX%?Z!9YSbc{GV9xSuS4V%g&qh1;j%s#dbO?uEV6l|
zQMZRka8s6pr&jH@t)>BJB&0~eKU?6H^*uL@P@*a`^fS(0O?X_?ce{A$LiK^S^Yy%f
z%}P<AG8sG&#W*GN=>>W6N7QB(OHe(-K9?m-`Zppy%rgE{pMuf1$Be0hS7Y<f(v0#|
z7xoC$oJ%o^ks|1%AG{vk)U@+&0)rVL%_+Une~UvCy2v4G!B)>VI~oT@JBpsPn)Dmg
zcC<51rA1YK$T2Ag#Nam+Wp1MVY(*T)Np21|Ag)*$w(5$SPBK=>kuyRbW+;74SSw)>
zf<Rz7N+TZn_RB?_3<0f+A60@}lTT(kut8aB9F`6>Of?z7#hS8e64Iv>DT|Jd!#T|z
zN0880@$(VXAx57a_~_&4L@W;>qP3eqP?{n*P*=$m3o6q1qVe^vx+r~s3*A&Q%BSjR
zDx5^N==>^0q(KS=ej3-;WT#^UHK_%oT!@0n)TO<FBNi5jSe{M6ubH8R`jm(?r2+nW
zfI)%CrkGl)CLR+Q&swTJ%o3fULEzv3kp^|CRt&gD{bb#y+K|#=D-SbL6fEEZ+H^=2
zkeO<Hd1P$PC%UpVFiPM(o~Emlxg>tw)1`H`R>WAA%M^Utae5m%j|z<@tKzd!wXt9u
zih_xkTeCXA7a1BxdRIE9_8c5tp{kTV2O^)q5u}-;!4KmlwO%oc+k;j9by6Of{sMe;
z#1!hV9bj$B=v{@r&$lmuso`cKp+dYa+!ZR0{wznj{6B0`pfHO#enCBzODXXY2NlVD
z)o@b?>!~?v-p9pJ^G)ipya(Su(tx+9DB5YgAq+vG>`?cGF4c!}ZnDk?IYYzm2#b`I
z1tX(ufr4HG<87XisfHHG>c~jD&A$Nc^TMbZ&>I?u38PeSmiDMP<}MMT)0w~oK|eJN
z0dy=z3I*^$mCn>dIwTM?7hg{tz*2Q#ARy9It}Fzg0R<F1tyZM+6kM8@zvHZwaxwu#
znnv6}T5vLzgp{IP#EVhV02htj`5>*T;!<yjeAqN4_BrgdNmeF?8>@BRRJKIlPq8u5
zgp?XfAd8{hjD_kd8?dU1g=vgedm3UoRm)NYa5t4mnD%p3QV(IxRoi-ih~PD(jWDm#
z5ZR_A6nr9s!R`319#TJo#&~pgd0iv=%}~Q*s*w)tb*Z+7-x)5jImlm$<``_G<;n+m
zm37INaZOz-hEw!Z(CQ>9yCL$f2>v*#-ZQ{@3h8yEs0G5LO0mwOBYs-G-O*>k56_T+
zs>n|jAV)Q`9aobyRPwFFQok{aKq_cb{WAn;2UvgIJd7lr<Z3dRPHD&(81CfxZonEs
z5pJdk0`l5a7aHClSSL#B)JLhSi_G*5it{xRmBlnTb)dnh(iQZPgt%&TY@(oXX>$x$
z0u*>{h{ggOw$K@EUbP!G#yO{GY4~f0FJs;cN>6XRLlcK24B#`T09_V0WwOIzGKb#~
zUUFI^S!A{N(*dJbBk<R;wDhA|7%~g-tR%GDy_I4t!KWhNMs(#5-U@6L;=ox#oZ3Ob
zPcHiL`{bppXyqi@3I>3q(j&{_(;wiJ*dVwDTReatz&oVf_c$Lt`MSsXOQ<R+UoG8?
zfJr|!i#^M3^0rU$nkwfdJynBihnF(eYCvmP@j#vxE|h=0%QYzE2pN!)4+=y-_+yI%
z^)sj@43<IQLgMRxuQw}B4M@QT3=I+!NzJO&!rLJW#cE4vG`Y=)8-b`Ek%rxn3m{Y^
ze09}hSXw%6FbKp?*p^u4IwjXcv+BxXy@{+P$c6>F7Ja{!_L18N?x2y3uMTrc-EjHI
zbJ4-^tj+Bpv;(sawn*nz0n?8J-J(|BWtfM&nGFR>CSq*>oQ9Z<hP-u=7(B#?Tu>z0
zNjKkL@kSl%C+W<CqLR>71n`n%qHNW+FEWg)ES*}|ee@y%bk7W`uv(Mlu$P>YGhZd2
z0mIKPBPnt~EzQ}&DsBf2Hytw3H<MG|Ba!ndahl)Qo^W+3xDeSs9!YZ=VBCCofHMR~
zt)LG#dxl=VMo_eIj7uTzQTbY)(kZb`;?1zpOi~&(p9{3j91})g@3bK5yH7mLi<4|3
zkol=j=x=>(_T05>0G&M;NJ0kEhV0@GaC%YZJfEcwqph>=tr;yVc&bvrcM~@3aaN}S
zZI!$TFw~QhB`(i|80ZliLW3rHahe}U_Q^2#Q@v?h#-Q7aaJqY=eK>7+cRR@92pto(
z5mnx5TuGk;`RR6%7HuYHCOV?i)3$YMW;DZ+#T%o8>OpOg#AJfSZi>96X6jv9H7JJ6
zZz7AB(5!9*k0Fe670305nVtdTr16cQZ`hOuWO<h%8<MRnqkQJgCTxbfrE`mH`<I}%
z;i9f!Zzp$#53z*D3&;L-g%ovO*m-*w2e@RoD>yJHOSGm-x;i(V5y?GqE$pf!g`T=h
z{%Egpeb!_cqL9<UQgcz6oyMV{8HZLDWhwh{qg5K36W0&w7-5!Udu4Jk!J49-yK;R#
zDVAHodgtiA*c{1jNJ?=vHjG}6d8oc%ZJ4iy_ef`PU4JgydrfRzzIOw&>($kABvUdm
zuUup2%9;A3=S_`Fy)QdqVz^)jYsE>}yPC{d(-U{l_(aal?90pzqDf0mGNGkm`b}Nl
z5ZHL`bV)jQxJj-#(%WAN=TVU-9CKZNd`#@}&Yg6SkgL|5L4O`bt2^rSEm6>KDJ;V-
zJVpi<S37Jr#BXw8vi(+<sdNp`+_c$7`W>J5U8}|3iR~!z8)g5)b;T{ef=b(4k6Lkq
zoC*rVCsQ_h>T%R}QlFz<$!11&0q=Y)P@`<6w<)Gjm8*MXZr#xT#ZT>!lN-c|R#H|z
z=1hE3v?59xmCZ@Zz^|iNms)mmkZeqXlDUVLE0!ZzQpf}ybu;2@FziN;TpF=uld1PO
zx56~*$0pIu$rQHEGS`>^)7)~wp`@@db(9lm#Z?Dtv$nLOs}Kbb9jd+D99oxXYtk3|
z<3riF%-b~`9~JGE?o!i+on0N1it)(MotZdTM9+8ioDEXEW=<uTDurlyD=>Z3hud=f
z@|ZigOy5zr%!^01_6CNHa2F)!y*}=JPdD#p>mKPP`n=|*Ya|@{QnA#E=}0@J(saEw
zlbbUyOEF4jMCG6I2H4J)MAL4aCF}UQ&p{Q6+lnPoVy0C(+~mZp(E6IlQeLvbI^D9y
z8F6vg&Y-Q9))d=iT5;6h{76{slfFvcQs!wTFNb5NEV0Zz!k+%nZ4dKzeH!|~kZRkK
zgI3mL&A)x?@9f!+ALc%ty-c5hi7t8bsj~bVeH#udz3ci1OP4Kr?wBb9^D75!o%V@C
zzIID<zeT@1Y5GN%zPWqrjR(!ye&fgI-gECiy#6QqFQ4B3oxbd{-}GhgyW<~@``KL=
zA7?-G@u>Q#BeHibzIgVg(mVFHKfLjf>WBWb=iz^zzt`3~<{xQiKXTa8qel+C`hmiv
z^<SJb|LNm4Oj~`)hG|#7kejsqGsW4zyX4xLKf3tZ?ya|da^G)%d-J5tm!3KO_T!J6
zx%D@{+3(p0{^jTketF#9J1#wL`cvPzC3?fBJ{BBu>GHj6mo7h|_5I=OmtNSg?~mVg
z$==QVkK4P4@!6N2yndhi_gg#hlb2pJ@fUx*;;_Mg`_>%Wamo};@8GFVOn+?tm9N`)
z@$=bV{PFo|rQg0V>9Hd(Kl`yGcML9j+t6vU?aIY#fB4P4-}JU$cb9+vmi!MtxX;9Q
zR(`$ySJ(XdJ<V_ZdeN`m|Apum_Z&X^7kA8<y7hzSOpNbcboiHk|LLi}c;@+ie{t<6
zrXKg~`A1%G^G|0D-hA)T!Tsg=zqs_jf*s56KJqJHxocweuDciB_w}ngessrOy}O>j
zZ^pNt`^f&g-Zf|9hmQWtneX||&f}i_a(&{P7QT7Pu|NOql&}5#k5j(<g->Ok+yBE8
zpS|po&OcoC^CNzL`1uo`d-#p}KK<3ZXYc&-wX>di*N6A|^gBhKJ$J#rJJ0>tUcZ0n
zXZ!x@f3BF;f87(^_L^^nn%@4UCrxY2zjEqG;fmQm`{NbU;vK(@8Vi5CvUS9oE2^hG
zF|G8C+h4osv^B|&b5_obHoXwJ4~~SJrd*j{JMGGR^!Oo*pB}z_<)%A+u-8*}{CUF0
z4}2iJZqbg{PJZV0p8jV(6+JWZ*|Xw1@110CzT<%7Z`d*`+H1{gA6<L@{B6sho%q=D
zrzRfTcy`jqZaIFhJAZuM?Eks$sovin|6K6hC37a+a`MjX9p@f4;r6c|yVs+gg-q*v
z|C8D4kH4LA`=xWHk8JtyUUu2}N4)C|=XZ|IKQQx{TQK3rPrJ!m-h0jLJF&&FU#4q4
zqqx`SNb_&%3*NJ6(YIutd4l%i-<RlfF_TwZIpg~NHSsp{C3$S~x8#5WFOTj!cukPI
z_=1kXi~i5)<<})$laG#i=N;Hc7A$#U(Y8sop|8zYEc4DiEM9QSE%C<Q-rV*Xhn~6F
zet!9ubx%v@$m0j+I&MB-;}<^Nv-yh$&id(=EfXhPH+RzHiwpVwpS}6W*WNq7_sVU*
zica{zk8{Nj{4z6n&T!|1%n8x{3y+P?pSZMl@;^0a<?2s$Os*f3S@zR<_}<t2r1#hp
ze>VAmBR1rpo%exR2mGwqd+Z74XHRtJ2gfwePm1}U#V6(#B$w?!an|`i9qBDE80ypc
zkfx1?MdkW%O~=-!wn_hvFKO#$a^`|K{;#LYxreTpF&tig`j)aga6!@aUU=Z+QF!nb
z9WHK8oYy@p7oJ&6)-PxrG1575%E!c<{!Cbt;rQv!_3=Yt_?aKc35!3U-`@L~d}B*t
z@(FLeWAd_rr}Ni$93Osa^ZfkB{<S%6+rKs^OulYS$8hoL@MC+ABzH{7^!%~$hQw`r
zI+*yAZBw(26LK4a6T^?ZwwWK9HynkB56ffU*c5Fpo*!Ji<Kk?kZj!H@{gK{}<(tXE
zi{kEJerN9Arf;Gjk>D5P-sKEZ8cPewBZaR0F1~Sd`Gogxz9^c%vCx`u)0Owmm(y0S
zk<+fZvOcFWC<kn-Ml+uMMw0)^l+kye_nx3sop$v<Z2ON}3is^YGw)0LebUyiYcAe?
z-9KOP^>sI0@XZ^)G4J2a&^fJ7UvSme?|R#+|9Vfk`=NVU;r7o*E535uO>Zdd|Hs^&
ziz<6ResT89|85<4%uWBNb!N|w<%_mH_ul-YYwyiHwRpJPzke-iEV?j%-;cj~<TIBn
zn*a1u`yF-lGjoq>Ui=<;>zeQH_rT!83pWj3y>Q263p+k}{>021zIOY8_Cp8Fc<SIA
z=8?V*P2X!LQf?3XTF3U9EB4nv!G}yY$NdX8G8}gAuFdN?t^AJQ)a^AnuXRE+Z)=rz
zJNzB%<gZVzZ1Bm<Fn_gK(08L@dFeu#V+JZ8?dw@SsjsItA&IVZt1cXpPn^@4`^Gs^
z+F@&rS}5;jr)c(QCb}t}CSh$}5d25q5<A*=(6&Y0C++yk%+deo&viT%pI~fpnZ*4$
z7k{jjIsPa4;OW*(Tih>iGo{y>hgZLLsXb;w;llbnJGnm5o?e+~&%0><+n0r<(f=q;
zHy`ZF*7|z)BYl;#T68b(68XryWm!9)X~iY-#_UqJk^{%V)_ky*a(g*507d{3UN_&>
zT!;Jn>#uQg?I+ya>+;3gy4>c=H%Mdfy{*VR#`e*jxrRJCEwW#GJhJ`6L9W^vy=C%s
zrIX|9qHxk}?u>=`b)E6TMi73q-m_P-?W~Sl-Kwv~ZfJYh7`VQpal}RO*BAV}K5*Wb
z!og(==9Icy&y?Q1W%<ZE*^*gc`m4#Nf}MH(O_lCy_De@Rv~(bRI2@Qaca_bDLDc&j
z6VCnAoFKk)FjIVH@S9=Zyb+T-_z~tc50!1==Gcr_(ropapSxMxZ^d-PF(0PhB7qd-
zM>dcJ@p9?w9HG}9bp!5*1`|SOIlfwD*s!LRE3Gaw$>`{b?1r-%mU*m+Gg6*^O=R+M
zRF3l-kCXhm*N1Uqhz*>+a&Lom)#l;w;7k#NfS@tc$aR0mNal=*jcCEh1%rPwwz~F>
zwf?oSo)HS4KFVaj6t}88;XM?skihnsicD$9;K`YR(%)NSIf80CtIQuOVw2!J$uWS<
zkw0vt+34Y(mN1T=_wm3+(M%my@V$&t^7jeG=98_-jdJcgU`i1t;bZzFJ1Zi&qLkvb
zU55|!OVPIK(uiEx$#UBFhGj3N2=NJ5)Jt+r(A8<A?CL?lC~0wixpb_sq0SdwJS<cD
zyM{UzNG0ZU($F9#?l(!0Zv<j3Gk()sS<&U+NuQXN66QNtOERp6aA@X@2TIT^#o^>g
z$^!@5n27=JwZqU^>5&ri+b>CFEmIBF1QX6OMgfEC606qXCJE=h!DS>P!5m8jvTOB5
zOD*Ny&_g2s=OU59EH^{6g^Kl<5MV{q3j{*0Fza>3d(*3iE5u5qQ%V=PJ_lb1D^Lo`
zO(9l?)ex9Djo@cti6<rsN#m;G^fps!6dB>_LBln^A+W^F1>}eU;b)5~Lqjag;Ho^r
z$fye-D&bBYL2r(^b`6A*=xh&g{D_|t^5F_rOB`ZBD@`BQp)_1k8CT(E3DBPcYNNz%
zFH*YXA?#G?qjc%R2y|r{j`|Kexl~T5Ttbu%v6I)+Um|6wVkr&$Aa2h?El5dX<)Lhi
zR8mH<^C6%#nnt8ov56HXZVEc@|L)Nb=rcbj+@J^}JD=S7zDvLV<F|hG!5>_8%dS%&
zeBsKg9$0(kr{A{r?&mLi;e~S_T=R`xJoEG8x2^r$DObJlzMWrK^PPKlt-a*;f46hj
z3rBtCeLJ7K=R05c&My~!;oM!%y>R4bzV)>S);@XfX_wyjPv75l*RI#>`p;k8^}rAA
zJ?)ndKDgq^XLo&W=eK@!*K<!k_qOMDec{Yq4_x)R&piLD2cA3e{<l7P|E^1Z`1_ro
z+jZJ&9=Pi3_n-XroiAMV`!DXg`-N}a|KVL%J$UA2Up(y{pZviOU-$cWy=LECmp%CU
zKR$Qvk>C8MGq1Y;&!3yV>#|+%`2KV6UU=heKR@iwvwwc>H&*)Z_$<8T$$z{5&L2GZ
z?a1^@tBOAuk=JKnq9Ez1Cd`@YHkZFTS{w!D!fGOOqRXR9l*zJh&{M2FRGJ&rvwcya
zIwfB!6{34erKlBkN0r=uapUtcu>Phbay?z_#ZPHmaa)kT;q$?^d!t;mE}Oglqqjxd
zquXSCsXJ^mC9}S;*J0}$8@tw@usB#>dtJD!u`XI~_B!y+1@pqMl}bTaTi+dytf!$l
zK$aa}3b)?T&kLp}&)nD-#q*}llVOU`a49ooc+KItP32=`y$i$j%fKD9ATvCvJmK}<
zWNP~-&NFvpWO(I<B3TLqdJ#=;3KXRjrQWn`jD?K5>1s;~ff;kWnwv8A<uxUCuO?1P
zqXk$Yz2ZnqsiG8&zbbFkZ^Knv+OG7@T$50GF1-5efh`nf`UG+@@w$M1gVtxIf3bwI
z+W41f$WNqU6uGFmv<oTu>Hv|0q9yhWE)re4T7{SN@KR10PvqP=h;c?7SeB8#*wF^p
z0um6hUKbb$!k~n|LB;hgQZBqcazg9lEt}!f;Sm*f9X)28%olf(a&)MrF*)OCa#4eZ
zB5bWI+{2*)TInd4$v}h>TO}HyCD9IJAPQ?UE$^T<BhoR-b4+FAF+75*RL>|gI;frn
zQpzD)!m!*jyiJ{Ck7T3UH**X&u1kL%i6v4DOFnZeTb!zhho5V3D$F=B8Eu)mWd7*F
zXt+rlSgl)=;V36t#r6?YE;`v!N=jAN$U4)-Ce#R`D=c1z(PRUG4YXjCr}WsMU^}$^
zf&+S%IN|wmhXQ1W6mw$Jyjwj8wTT4L^jN|&Bn#VS8=gd>hXU@>$tMrIKi;IBu+^n|
z5Ft3b#JLDu0e8z-qSIiLMRnb!K`d)|PN@IEAmm}_q!g`J%R(kHUpH@|k|0oTfVrv?
z?!YGG9ak?Q(zV@DVeM+f5*%r3FHUTWwlpfjG>5+<RF0N_s9wfJ9;$Xck14~F6_*S8
zc>cw={gcUBI5JM+SM2i#9&O&So`l41)|^H{ic%O!HINNKV4ON{Cm);8OMoF!tDY+1
zBoLO=xT2)#q(C@6(V*MY3uJ@xH$|8>#gQJRa>jwft^|P#rGlR%XlTS3DAXRal9bRr
z80`-rMNU`^N)%@L!N|!-6k#$|LF?TKUzHS;uVO77lnJzFmZmXwAYPED9R$;$IDHaI
zsP7?zlYFSbB%VhYz&M$smBO2|#Hk;!YS#JuP)jqUQz$*$0X`Fe2X2<ZmL@{uYR73o
z`a?6Oj7YM2GX+ixk~ic<;w;Ix#OGNS@{%sOPTeymkdZozWjwe>n3s@m!q<(!Fe-pU
zhdKtt1viQxGObbks#a*rQuHZX7p?Pgjf0#;-oTRtVJHsGl!;+5C^4FexIr{^vEkY|
zOc1m!5u=YuGq&Ch?xu{<DyDB3bFe7$svIr1+2KxEt%hMd?jKVj(he8EW_?y7%kX+b
zf>%Mu9j>2b6QAM{8hxhclncfC`M45Hc!&snBORwGPu>g0SlhUIeeCUeS_NRH!BNO_
zJ$ko#4Yc@FYq-Lo%)A?i8e>RmMc=Zsk)sb9X!4zgWf6nv_z#Q#dbTUdGqf{JC{*8|
z0LqgDjxeq2T5v*{VJz}hg{p{wP2`f2252yi4Ap}Cl>RWS)Q}~OveFmCX*ZKdE$$s0
zVC);=R~<A-gaq6XLrqr!;@I!u9u}mhV+tBbRtez@gvLlAs2cqc8ULJ#JE)*RmQq9&
z;bgSK*MXa8p1Xy{!l0_JU_@CLq=%`>EUj};Nn7`<X8tl98Xg2PNf|UzI<|^{y9o?|
zQN)#ae$<TLU~WdIE7F%^JLzda8ii^8u2>8OPgX$hlj@H&g(xS6p9h=XlF}A+M3~13
zWl*0kQiv)cvRIp?nrJ+4`wB_HW32jJ-War@GUzdGFUBZUVqAViYrd}Kh9zx=jSLXv
zgj!4S0%9Lp3L=NgDMp3VaBC`oz`&5Opx=kUX@Ud;>{vyiFs~s_XeEF^4I-g4I5^4a
z%rH+rILa&Xfqc$s8CDvufW8llzG6gq)8ZhsOx}4ri*=TMgEHr2SSn%9Kx%HngBm+{
z&NJ{l*a!n$NjFHM*bU&RrwI!!Zlr`GbT-WX0E4K}$f-mEtVvVYlT4+Zr)4uCc=Yf`
zEJo{AOSVq5D93>12ZL@khPolu`ul}7!kp9B1!kR?C}D)#4?9&^din<fPb(bEok!ue
z2rxR-a(u;vIdjGMVABB$o@)uptk{c_plFpPGoBi4i0dpw16Z``X?YTgEjH2+j0R1V
z3B^t+slZ+-7~$}&b%aqxL;(YJJOV>%LnIF=rq|bBaci_bP*4pg`$#$UcR=G&UbGs@
z<YiMVnjrSnp@{s8Owed(ivs7aQ78wd_P9_S(zJU@LT0#2X}Nr4SPZd0J)vT53Px1s
zRG#tWjuarO=rwaeRUXNGi29isl5EfXZiAS>F#mUSjRw+`mv$Zz)%-lPLc`H|=Qd^I
zPj9e~9J$D`H%zB(O5#MJ8tFj@TUJY!IMm!l{?fV>t?|>i{7;}sY7~Kn>g^7c5WYJ?
z*|u7G*k_I#RuCV`p-$u*kNW&g%Eam8y%RNBsi>RPC6Zx9Oo<oSlBsldx*5L#G$yU^
zm{$;SfYq?JQI{DgWa*CkOi(0^jJjMhWWwlrk=hYbjNA=DlFi*DHR59ZtO<*8U;b*W
z;bhjN4Lq+H)Lgf8Ci@izcwyV?>df#36&kLqM5&QST2j7UC36UU@{BO5hi0Ykj_9Kp
z^Daq9&g1>r>VY{IZ<c=FPVgl+s>L<bQHuAZs%*59Y!Iu(W=Nuq93SrPEMt~rI5=sb
z7KS~2(sL3uo@9eu(6tTwM8*{4Sc;4r4L){KFs(cyd>DF~7$$lTQx0lXu{JRJQrp=K
zCS`pn3tX#Ww2agL#eG<xZapNQv5y4J%_N!W;;AHMWK&!)G}U#s$jA~I2r?!b$#ryo
zN~CGSxchb*e8*CX2{}{e0xg$Ix9D^s>E$?zwv5><@w~oVCfAT5uI<N7RS8K7cN%+t
zBRf0k25Oo@y$}o;3sdS+(6J6gZ7*&bF1i$FaGuPMGD089O$E~?l?If<D0OO)M`)1b
z9p&?K21z=GgK0PRG2%3iS0ioHf|AP9t^ja!o?Z*Aq&^5sk#(vF9hF!=q=haHr*Wl7
zU=#3AVi$IXg9@B!BZ8iOEjt>|sxZeFQPOcJ!UvRrnzJ`(AdU8!i?-~<GZuCf7V0GP
z0thX?8f*xbc-V6^IHj&v6%A<nO%&y%K0{^o@h(E??lh_fNC7e(zl20AdxWN&m{vV*
zNb_zndx?=4h>VwsGN#m!u&Jq~?Se2UaS4%`_WWWJYjFc<5`8AyNt!`MjgUgb%{oLe
z?qnU06evESxEbwFMU48bn-6aq+fJum5<?mt4U=j`u0uCkGGgg2$SMy;+hl*7*TTKd
z-$oel$IR9eqKz&PTF5-<fWw%+z<`FU2_9bnJt;zA8$hlE3eI2sfqC0!7;B||i&NVz
z!m+1+>?(umAZg`bSQzfZ3p4b`{z4L@#V<VorVhY)*&GSusR>76xIsBUtz}B{jOs3t
z)8Qv8pkQpE<yf<t%>p)y9mHw{8RkbfQWLp{opI0Dipuss_`t70L^vy`LJAfpD6FAU
z38bbz+(W9EQJ0c)>*BRAA#UTp2Su3#*9I(Vgwhmhe(KRK^`!)wdWsNpj(~H`MCjn>
z*=YRGs%U#2PRDP6A2Em2fbf*idB0I2e};txA}v+40z;`K&F%i%xOwFnit-1Hzhsk!
z32>_Z=z^;aF|E!Rl~@8=K7jM@!>SmbKoLeQgyxzQ{$GSJv`}D3NBK(G6X?j7G_nTk
zV3&df-WQORFF0{U2}d;zmW5huqFD?S^m1QQ<P!G%Y)yRx!C<VlNENVZ6c{>Y)fNJx
z(yV#tgi_UQYs$S(2TGJE1#MPR2uvTmjoO#`1~=^uQh=u0hDEEsFw%q@WvT-L1+7NP
z-caq}7$s`Pz;K}j<&h1dM>Wa^2xmuiHl{8kJ-V{2pv*F`)5;t&Pg7jRalz6YD(+Y2
zeO}d6pjIsvr#IVg#B$FlLe$pKgi;#<=cpYNnyli1ayzY@S%W4|1k&O(sKSqlnfhf3
zwIS_bG#)ZSgKPr@vAkKaoe7yy8t;uHN7x+4Weid+p{9-DQYIl@<2s&Jc#Z1k%YagN
zT2&TpHJ|_M9(9w7kcky8X1CPzn4KcUYgJOLWOR_LPIOLMR@tOdwFRqqN^*i=UgV#?
zB@0{>Hh4HkTh_#Qqr<@}yNS$7k_M>2YE<+VW0hWl#g2PHwKHBspBT=>YHY*fi*g`j
zoj7UyWiZS+-;<_gQ!3!J7GhVdT{RSKm|+u)(O2>oF$8(wLC8p~=)+tp!0G2V0^Djp
zy5*Kt@#6tqkp&a*R_SO5kfj)SIxPqZHdC{)X{2l<!L32QmgDI2UVZ)zJE&6pqq1JC
z=3GL9@AqXQ%Tpyj%xQ39Y`^Me#CUQPaHGCrr*jnlOwVQHqgCoi9|sn38QAM|S%C_c
zvtpIWt<2&)j!f2MjKbC<D7gX3k{DkR$q`RBigtu!F4jM+vNF^hUla&8ej!NZ?IRh(
zjqi}FPo0|Y#=3;+pymiiJr0tH0`99%ntNh$HMJo+YXwGLriRC=KS-|eb<+4uC9HQ9
zvVB5%3>d|d16Aw*xa1>z-Yd$EF!>T&r)432Xw=p!op2{6;iweKg&yJb5M@$Fy&*bN
zB`SF>f}Dms%!4+*-=~d}At%X2QY3`Rh+kTM-Xtk6m^xJ>49RSxOA7$=D(%Hpe%<$L
zDkD`U^3BbFSZFoH+HLzhQm;Jm2gVN$w5A0s@EhRb;efHbqt&qL)|LVW4yQ#n=1~#K
z&m#(!J3gm+IakFO;8lHmYAFDKTR}K%WU*#|Ax0~$RKev$qkEYHbJ}_5HzhYTAXcFE
zbVwEg2UT}eMKYsX<T|*s3^`RU(hwjpT!5-J-wvT#QTzn5UC?N{-EO5sZX!6~N88I&
zz${b2J9b$KoGc#J1gV@&$me|!N@tT&q*d79ZYr@=Z47_DI9rwvNE(ep&se%~Pk@%k
z3C9|tV<@k5fXW)cK!FUW?%G(C&EP1wLIU#A!Ttn}02M7wh5-#AQ>4Z{2<qCzNY;Vi
zMU#e`68qoSRr7L^kD-BOz4)$%Ijc@Sc%g!#QXq>ZoSM36{Q5mTDYxk00lh=3E~jD@
zCWe+7LgXw_ts=N;E<z}w<p$WXOL2^iRn9cxf#wt~EvIF<>o_kkn4aFv16^C%WnB)1
zhg8+9_cp<Kt1}KWmk&tfRI4!{pD8ZbnuPNq6m+B6(IS`DnuuH?$au4;t_im0YEzpT
zZdx5F#CoL^5Z}|P$Esg7QH(NDz*^&UbRI`JP!`_J1&7z4_5in6VZG7#ZcJ|!@&p>e
zMVt>!@t#I;k#B?Fex$k^Dmmg)%&G?KHBOOWnq%VN8Tko^r?a+TReq!^;+VkcwP8T`
zfA#SpRr~-~Lmj3CE#pgv2o`zJ_J)H|U)t}J+(>zi@FR(uYu*%nHf?TTEZ|6kc1+f)
zzsXPIQH939<kjv@WkRq~oI0?LasJpmzNQYB6zuMPNh!uzYKTCTQUS^enU2#I%nigp
z)YLCQ3I2u^VdJyRt0}Mu;i*@RI*j_n!37axC=?mfG7C-0*E^(GQ}5VgdK6xwI54pB
z?9!{n*UosOL8ud^cjzUwT<&|EGjA-Uc(4qQakMP`x20z2q6Bnl35YXHw*#d!{LtTX
za@r7C)v_#>Zl$GqSjnrs;%*gVs@(*P0mH*)RlP)@y%#ge#m-bw0&zo|96pGwSk^;8
zI@T?$veIB$mJy9-e0&hj66O`6<OBYa=w$mvs3$`jpj87~yZ#qLXaRi`pT4<~wVFC)
zlDHyCzz{k_7z6N@ZxQhGV00@1N;@XhXf?JdZNOqDy`kR>-=?TbX$R0xZOBc<*jmmT
zSe%N1!uVbSo)kVXESqt$fhCGk#O8*GLP5BnMSw{eSzKN&xB2SU){H`{^-&*XfnA{a
zeA8;AjHO6bRT$B9QpzlvDaJQAzK`~U8!#TU<x)@@Pp2NoudY!ni6e8=ugxbwtBW;K
zS+uG|iDTOYAL(uy;HjLZjvqa%f(!iEz(0s$tRH5u;3^Ttvg8S9Gcd-aF*j*RmFm=|
zUaacShB!pIb{x<Xy`n)Rfy2ZDD%`bv6XDQgY)tJLG`vx@JM$k*gRK&W%D9v50for;
zoA&MzaXmBcVezDD<hLF)crkIP6-HXUiO~pF(;czvr=1MuaNO9f?N538gk)Ug4G>8b
z&%)qZcU!bP5e9^K5rcJKUpMcEstykjb&#TnRq52L1A2;cns=#;G=T6_RrNaU&<q=r
zF0F;gOPg52uokV}7`vd#3U3OOBhoY0JVn{4LR@0mgk3kv5I)tDA4bl5XKJ>f&g2gp
z#Z9f-o-T--Y4{Z5cZ|0HwQyv4Lf<F{<54|4M3(bOPgf5-ndZ6n^mx>n?b1o_g23Q!
z@Cz&n&>mYB^5~e>@Vt(vilJ>Op133^vBs)R4`RNex&dVnigH?rsBYLGmS!dl0u~3v
z=3Ffzl|cmK?i?7W++2`JWR|GzJ(Pw~73-{VVo8HXD_sFE5KZpVWoZp*i9S*sTE!Rm
zd&H{Q1Eq_3+yHE!J}2@oC*q>UxNes{y)i>yXF^S8RZ7^1w@$)=_>gd_n;Ew>YZ|ma
zabGNrZmH7L1tpXzXPrQqD|B?i$vV?#_u4dMc=397Z{M6;AZtddeJ49RSGsv>3+DZd
z2v)RQ#B&m#O_m1NEH&Ylyg4z~eX@MKw{l!Q*s^+LpqXzhUK!~7`=V}lo(#IFZ0Ck`
zIkw02ta^*FVYb=hl8!=^X=J~ZY`8q8GpSF^)hA7-z+&*|h@3N0@7sLPdHo}C-;QBA
znf;58O(`V{^lRV`IT=1;UZIQk+K^H?kJ$>7Kr>WcU5RV4)ViY?H<@nfUuC-EdK9_t
zJX=o%vprm&jIbSTTsSl8JtbJigMP+JS8;uwFY#t31|JW4L(`izttdQIGK(_B;qK++
zYG=4n%|G`nj#Wzd{-7z$<%fmcno4rba6YIrD=1!l>%4u+(s?*LNq14wR!QZs(DL%p
zuq7GU7GURYxfm0|Xe+xjJd|IE@`)CeMDud<DKzJEq*&fKaw)kTCboAd%$RK4<4o1Y
zR)SemI;pVvo8qF-XOeeGoN2t?J|R8%4pR|Z&d9XJn$C0L5;bf^V%H~~q%J;1N+rhJ
z&gL(q@C9aIBp*yG^bf_Q;zW*f&?7|I?&QtVJv+(_ntoZ;+dCAQsX=&KMvowvi5>e4
z^^|PT@qQ_uY$lKn6H%qQdhX!dzYHvsk$G;qksxXCJvP%Lozi!8-<GL1o6pv31p+#f
zt9frqa`_$EYssosk{>Xk3+3dj8D7__QopKm-}sSYi)L>k`(RFr-KN(C^N+|54U6HW
zDKooA#h8=M$Ogl*WSNlB=UF4LmrXRGJl4}&IlMoLzA-6(Cf0R2rl<%fao2Tp)#GS5
z9O>kZ%;u&!lX@0935JImj!HdTSFT6rxxu*84R$aMDn@1IQ+6oJEQFHE1gdxgYrj#i
z<9$X_?9T;1n=J>?9!t0_$QShSo@{20d0eck#>0i-;@o360_Cbb`pn0*_c1!VSI8#`
zKD2c6(km<1bzfBZY^Pf{_tI}q*gR?R@#|)q<7ahm*uLoaAAa+WNv~ZR%q%aTc+R8O
ze}2-*um5yu$=Qb=5g)(L%&pyD+<)NP*Do5Gy>{;{vpe=4IOX%D!802@*U!Fp#Rn$L
zJ#OfXn`bROcVyaK&+I?(lkdDVbNLzTdsd%z!ai3&y?@7OY5$I)*B`r2rE)@d{dfCM
zy5-x4Exh8mGp7}fo7jDI_r`s1IdsCLmB9zQo2$Ow{nQ7p&wl&2>nHUrKXJNw^xrzS
ze)B_fzw^yo_WyKi-_B<Cq=nmu-#72H#<v$8l0AOmC(Y8Mhx%`sw{-Xxb4PIOLZ9Ai
zc;@G+4Ts;~e01TPrp~?KoTa70;^{X}lI+dP&pJAL<`oOGrysTI^Q+$7``Ovmb?Y)0
zJ?tvCPWe>FO;he(zGd&JvtN5o-|RDv@7ZUc<9p8Sp7E>K-1gzGP5S#)|MHV7X3YNC
zsr#1qIcFc4`Q3AF{`=de-W-4CD_izD>co2{z5DIUvhO}^d+yY2Uwh3tzdvDN?U3j8
z={@ECeQtW<O^4ie>;VU#dhV{he|X!Q_x?=RhVEZ=b%sw&*eCwa3B!|r_knY!{>!cB
zOr7}fqsyl~^~mYZZ2j(}x4&^<$tPR6@QW{WXSRR&;Y0rL?7tt<w{H9VwRbElU(tEm
zqIY)w`)lW2d&Pox-u=u1P49o-DDuhSuXP-?>1*?6QpJxtsWf##Fq<!=-@N?SE3z}}
z*+ExdXYZ`;6^mEB^B)V9C%S@6PiB7h*6{X8efxBsRi4~+*0h;D=WL&O)3kW%2}`4F
z|M9i>69>Gr_x+1j?PJbZHaR|HsOQrc4Nkks%&BgfbpOEZlMXrc%Tej=%c3b?UNP~w
zZC{?)HFW>X)BCRPzG>y12Vb}Hxx@ecgw=Z=cg}D2KDa9kAMEPvT}N7HMV;{j@iEhX
zcI%2M$y0XkuKr_YKmEv1?@xE!I;sBa8#9ML{+{s1@4Y(v=lh4Vr!~TZCU1Ut$)UyR
z9d9g7&kqeRn>pztC(YF7UfyyiFKPVPNZ)N+MrOQq=%%H$p6feovVK5h?wpgu+v9zr
zC_bv^z~yhLbOpT=<}SZ+;vF5IJoldm`j?G%9=d*p`9pR%+_`kZX{$2x&(3$ef4LnT
zoxk#|#)^ZM_150nV{$#m(*B-R8CrGrkIwjA{wsSe$oyi$Z>C=-ZyhXzH}ySo*xSw8
zz26#0Zq@9O+{4qqE30l>5)IAzab{L^X(mj1GvCdI(G%78bp6}(k7T-U9qi8Y#>#Cx
z8F_{rGrf7ue;#u8$6K$xGU@EQ^}Av2f@`Y>9dYNfz6+O4n;ZY=;knP=FY^25Q2Y+}
z@S=C!U77d#O4xCpo!mi--0#!QsHmUwyG2ekObMjF@9e_T;en4wVK>Kk+0kD-)a)-N
zw@-<t22pitAxO@?bwV^qE7pk3p;@W*tZYW%ven5@$7(riMzZ=HJ+17)VN;fLJ1KWJ
z!o4eY$}u$wI|fEND+7<@-ha-o!yC@21wZI(%?VDiQ}&LAd;T#S2G^cqf?#Da_Z9k)
zk4USlBe7FYni5X?bJCgp(Z^lK{5YCch;!YS?H9_y6T+!KEw`qhFT>H_ZMm`V%Mm*|
zaZ~lildiTQU(tI#?b4KA7?F3sk8w%TsCBlo<)|`g(qLRZU~O*{)i(C@oSJW*x_$QM
zQ_tCV)9KTuedOe6x7@R`fApTE1G5WnicT)9Sb6f6H&>@^S^cZpKV~)!bsu=kiCfle
zKl7f_ti$8I7N42lujk}@PO93G<)7VJpSk$k$?WE-hn8L#x^wUmx%Pl7k`2>8`IdRF
z`%SGl|Iw-CBR+mo`K%W*3rZJ;2OO}$b;dWgW_EmL!IEP?`{aE~XSvCf8{y!7MSJ~>
z&(}JSd}PxNdoL(Phpq3-@B4uTllRSE5bhI|_Q`EpfBn3RKDJ?6YeT@>M&w{k-^@jn
z+pYPs^j}v@R$O<$sofpNuXg#`+(>HI#HId8aVeL{xyysxx_=0w`PH+7e08Zb`=gb&
zpBSC`QG5J^EhoL9RIJRY4OfExvYD9Ma`_c+kF)ER#FN$~<x7vx&0l)#R?{2Yk{mHL
zxpCmEu8<c|O^!}ZHY{41gqL>M%%xFOK5A)DKI)j$7o0E>FI=<Tbh1?(mg8$ba6x=%
z`Pe^fiXvWB-Qz}1m~KZlOuaCa!y1{!zAm`_=o`b0``QwxI_KVUczExJa`yHQ<^~gU
zJY8`0td_{C<2d)2n6<p*IhwUh2CI)t?*OxjGgx2mlpD;-q}=%khsPKi%^l@@)T$w4
z2D44`gPbh5U|GG`Yln+JoRGX>B$2nsQ1-&3qGoBDH2G4CtVG6vkL=Y~Xfo5k_&_=I
z;v_1aCC#~Yl<n*>cGVT;kpGrQ2d4f1F(enx7g_U_?nd=7#y(5LNln~=o%&{%%OBrw
zblOPa##M6gsJKGONHTZ8N&O<3dxW^xoVQ@8w6OE>++5R`V46|%?4LyLJdX~)+!H;z
zpkcyQvYyq-wd83{pZN*pCpo&+P9~Bk48Pf};G_?u0B2YqJRr0@gOX<q&?)8&P8WAt
z_C7)*Kt8S{^Ww;5GGpt8F|0a6#z!1nc!Z&s<HzuUQ&>E7&N@ZH58g7s_&7FFwK&e{
z7d^vvDseueYXZy@tw^gNvug&j++rT13t~4nV;sjqoZ$>}--6gpm~)=X7EEhSt89ZJ
z%(J00TRUA8FOX<rXJWzwT#gT(&g<-O5xNfX3-p<v_wLUIOvo1>15;y_xY`@qDa>iA
z%szR6eLUpKN#)kqSz*+48}B`0W>mXD$dfqf91YPMr3xYEEO|5IXq?3Tdod0RIIP1r
zVO+?VJ~JBBY2WlT0~*f@*u<=dhB-}uC8WQlC$hqj%`oQY7B>|q%gmu6!34(kJ-0Im
ztyeIAAmNYLy5QSK<PEcgKu+zkP9oe$V`d-4kJwO_hKye^F`UeZ+_c`3P_-al|IE+m
zHw8T$e#OQW?(l<&hd?J(`p4jpaKq215D|FvN1j3KxZ;VF2VU!^%!<RqKu;+$&U%Di
zUUbETdrl5}$}FY9f(q8a&E!>?6rc!j>3qwKp=|0<9$;yu8!0m*!(#C}eh{;2$NCHo
zrRn3ROIxZqlb(#@=(^S%{!AJoRHogaQLrxL4i`TrZ4d^2n+~Uf(f|oO)CQD%jo{Ov
zK6Ow-l+Nj`;Q6R41y4vi*&9mLqApp2u%jpNJk$;bM3V6#$R~WaXs?h)VA|=-AD%z=
zr!sWk^Zq+OpB4Gc^H=@P&eM*5e(m?~xaw!0`@!3H-u&dfFI;*5&2M`0-ZM_v^~7c0
z`_^T@T>G5||7qv0`_H`SU!Q;D5Anb0lzV@$_8kwN`Mn3Pxa1E%IN`ZP|Nh{gE<KuO
zcy_++jXS^d+;eX_`wM4XdgSwe<e8sKcAj$C1Alt*-m|`X)rVK?dg0tZ?)uJUU-;sQ
z&z*DC&JQ2=<egXDz4Nro{^`%(fAHOZ{?)D(-}~KFcYpEu*G&E8nfIUkA3yufo4)ty
zb3gj|-|m{d>$&?+{{A0Md;8A+eDXDa`u*K!Klj{&C;xHhxkvorcjsRE!2f*ioqxXj
z_h<g`SLYt_z!y(EM4xf_yHE1W&;4&Z@>730_jSPy_Za%fHF4Mc%dyF!_SR?~OQmnN
ztJnhT%I2-Rjkm7nv+>jt`4V+niDwQ3*GwAd2`0%6Im*V2Azq#x6sOERo*CmR8}2`3
zCoU<;)IOfNO9ooi*6Fsgjry1`+F6rc@2r}iY{@k`sei|rW99~~Kc76#ffiTg6&7|)
zha)c@=cWFw%3h3Mi11CDJZ)F740Kf3+MW~hbWV0WJ()7o$@FSeK3;Bxr7e@A)}xbo
ze%W=6ZmB2D=A@)9ahIld-yb7#U|DZ-ARJdZ!Tn#Ly0yWLIcyujJuUd-5UJCQ!&uyZ
zg=`$vi%zB2W@k5;zZTz@^){JnJJNcw+o#VKWH;^hDq}uK%-hHvx#NsUaBFDJX%%1!
zIkpC_D}-K&URwoES3sR{ELC(x+G;Tq=hD+<xYjHgIDkW2{(#n$>AKI-q$%<fqQR20
zIt8Twa;)Le;HI8%G)l6;ccq_ZHC}$JwkQ)jZXv}3{RjxcxT7yN9czMUbUAB}8prYD
z^WfDmtG<vgK}a*WT=ex>40;)e)2P_J3>*PY!|M%s933~flTIu0aXO#DVV=SvV`7%$
zRat#gDQ#pzA)<LA^~RuMUr1LUZdgNW0GA1&Qw9Ay(`L2kX$2h&9W9{|;j8#5=<+~Q
zC;BK5R&*I}gy6J2im-*s)uRKE!C}~6>U6reSISDA1p`?2f#pjlv{S}>0D-!~N5Ug3
zJZ~pF28DM-63ts(-Gwe)vo@^p!x>T!R7Q&fF&=7$w1n)UGhU+YW%V#yv#<cDjzcOV
zoBAVUT9WEy5T}Cm#exg!DWU$%4l?t=1Q{R;F6`D*ah?6z%V9>#NP)c7#=0KBz@nve
z^s==qE}4u?mK!=!PBjb#qa>HZpD_bV2}vxOMFhxI5FG})HU<}3Pt^Q@e;3b9=$p7I
zpl2nla7buzTEhi8`im1ZrUcNYY+5aRAx1-b!v@5NGL|sIPq_dXMEyh~-<(k+rCXmo
zX&&~d573gknDnI)dBNW>oRAVQz~CN@F1cKlH4U$?zre_G2FLRwC{iv~^X>))GUB|N
zI2epLfk%LgEYmzzaC%TEkOl%-VP}7h@JPd4DnZFpFp6-)^o+PHI4_Yq(a8+;Ybv~a
zqPw^wE(G#f$ypsAp|jHCPH7ZlQKFpo&OZIB9KpOZhVoK@5&uC)TD~mw_#B^!8Itwr
zN^K-BIi^8T4LT`L<OqX%lB*h|pk@q`5%nNkha-U<^AMttGih5vH5b`oj6aX#ptZ2c
zrF$5vs?#w7_^WY8+$qr#g`P<&&Vq9Ucu0B1YSesSKpCf1$a#xJ(iGH8Xs4)~L<`Xw
z@PUxZeT&$vU>36*g)2{WA*14<R5Z#!?u^d|Cv5RR1JY2j3{G|XA2-9#l5|QCE|Hqk
zVjIQ;1nRf3(;MYOBS~1%t9KH&#Ydquhp^<ZK<_As`~gNUFp|~k*LK3kGWar_j3d_!
z7_gq6YV5~Msfa*IDK+t3D4|j+;fO>ipzg?VLBV{WqbQ@c)-0}6F>P8`w7vs@UI^#P
zTBLdaOA+>L6bTr;C<J3p<9)j?)@Y6pO`8UXSWV38yy{}HlTU>7BLnrd0fA5fD;n=W
zU+!$@jQN;CsFO9BOW)4jcr@t<ykjhhKA#n_JJwjJYA_DmSRxcPmZ-msGiLd5QAWnx
z8bWimTW*Tho<&1|-J%uOhTYEH(lm81LOY#pI>;jTVz4J3%L$`s6{7w&{W!6y;o549
z5xhu8B-geXZUE*qjyig1!*J@byOW}_Qq4WejuEDDUW}*y7kw#FB<4jnl9n(>kfDa9
z6vCZYo(duO!dUBT-veXePQ$6Ic(n*pzl~C*sULIVYd{5>{XfD*96t}lGu}bmR4B7-
zcF6!|^h*6zYUOWYhq{5{fYfR&-9lzo?Aaz^WmJPKzqF*{;z>?~dY~@zW-l8}Fsi4r
z)q-E8GgWSS{!K_L@M3-4XdLC3K=^5WMU#H@r*!@vdUv-;szltTO`%p^rO-EGpe|O{
zC?3*yo<$qQ-KblY^c7J(KEdh5d&Tq{%@ZvP#!Ihs!He3fehI5oQ^bxi%;9EJ{Vd_c
zQ8v(cAdZ@nHVz0(Zs&CG66gXDQplo)RiaS7JxCahLef$8L^NFF0fQ&U_(UbR$%;>t
zREY%iZW!ohBNBSR_Q4q#2q<7%yi=lO5)P?TyA(QjOCe{DoYos<X-#N*tAVART}FuY
zB`a;?dO&EptgmB^xae&l;-*4VeTWkxcU1X$(DR%Dr@}@O19cS^(l3KqUuq#x`zaU3
zvMdP&MOswViL^2bOIv$2hsZF}Sxi!=b$+{B4H~uRjj;+4FlHwqv4GMdjUeTXZg6MO
zK+Whu$04#+#Nku5lTluX;uOh$ie>XwzsW3O0)ztDBb1xAadoS#RdyR*c&zQ(!(9pM
ze~I61n%(Fz#k^m2NWr!pWA}Df(?)BVY(u;4C9PuljfJF)4G3Te?KO#QX(e#Zq~3;4
zHwa~*p!YFVtoi{(jkUMC{ocVv<q_@;ld?#qr0$f;q_?pv;V-JcJ7hflZsbcGp2pD@
zf>##0^FJQkc+Z&o$$K@gQ*gd@z&%!Geg0`$9r>-RXrw%y+d$G*$fn_%$TH3WejcE9
z4wn`Uz(Sx5yfhq`*J2fGzyP#WZH8(rZLcWJg!4BpBppH#X224np%VI^dy!1rO^unT
zvJN-$d^=5ht9-#|91oW3{IO!|yxpD06G;_<1vercGz1g4;8Z^+N|ljL1$-ob$!nMg
zozSIYSG-11tyX|cRnpthvx%*$p<-Ut$9pXp{ekzP-kJK-!snwaJGtwd9&hzpbWU${
zYH2LZzaFd1)sSgSZfMl5r$sz5?aw0Qp$n;iGmYJtRN7V#G#hOdb16pqD?0EtAEop5
zvZ;Z@_e`nVq!!Y6r8KfZpElAP4s_KcLhC8K(M8-Cv$53rpcLh0sZ!|8FSVvug2d6u
zDImjxE}0uG0`O~tkC_sLU<XoGe-Wx4g4&=hda4IGOG6$h3lKEwrcKk9sQrcq=QT0D
zb?||D(kO+*`karxabKDQu)Cv=k;vPZv|TTMZ`<(Ysa_2ITj^hn`IoLe@oD3{g(26w
z;@bYd$jdQyuNF5({{QRN)}zftZG530QMECDd2gqujeV)VjsIKkn&v(6+LJBD^M0xR
z8m4g+-;O(;W=}FS&UhG4KOR5c-KJ^F(6I6D@wDo0)4vqIC%@*wpLDNa9K4d=uN1DV
z_C&KM+&Hnjov%dqO5wX1;ZR$=oUO*wzMT7&c)XI$UoKqp;G>7_*=8@NQ#<U{*keyL
z<I|+>-ZsNmaUVbC`fKDbm*(+t{u<q@kujdnE4hC(*4FGv-k#d~J=yG)Wc+X9jL(Nx
z;{Vd{cAxfAeB1wW`uweOUrN6xJGSNS>8>{Z<}daX^0(n$E={k7)A)4!HMjCnIpf1$
zj(3}`ty}x9asC!N?TL0zxWA^$E758mgq6RHJzm$p40(0Fmy6%F%gb@vQ~Z~Ur(v&D
z?p2=By^=kY?&Y8z|K;>~x%hhu+x}URKd|?-r*!X${^fA5hKK6@YUo}{^HTrI>7ik-
zWTWx<@k+EWm9;1OcHSuMc=!0Yd&0jIr}=T>W#eQ0rF*;`#=DiO?Qh@5$9yH+OT&A|
zA}e0qn&$B|>eq7LrW<b)O_S1&Pn)`xM%N<ReQ7&f@#Eu<cN646<0ySQPKr(AwQ+ja
zxNZJzns&JQ+wNDox2L@KltoVexu(ZI{o$DY?S|CpCynWxt!*Htdu%d67wT(cj9C0o
zsBQ!NboC&1ehoqw(Y>uSEPW!CM-@S-T{)!Z!$xuA1RW@Ossl0<48KGtt`-NN+hfX0
z*W%hbWFb4~C+yL0P1A1)Z>x&){|P9+m-5^b?xn&=mxn#kYCdXO6kf_Z#imycQ`(p2
z`*@l*pYgc1`=w#3(-&T5Y_N7qJLdoH-cHMSxv!=VQE6>^{qH2d7)#TzW7UiPSL15y
z{c32H=5M8M^KG{&ZU4)q`Q^gSx=7?O&Q1R{csc#X=glj{e>Jp!jmQ5xe5!?}`KyP+
zwXIZryaa7D+5zM7FLA#Ll9$B5OY`(naN`hWocl$mdsX^Ce+iA){{?=dLSkLtw9Pb>
zJoSehqLwdzto(*H4bk?spib5+Jtol?iHMq{VRb`)cLKCrs0pHBE^R2{Xz6-pY8)0z
zCC0Dd__0`;9xTDr!mrRaqq1qc72n<|Q}+_%cuGr^Q2bc^W=~J|3AL|GoJ3CVV(4!j
zYyx7Wer`TauT>p*n$8g)H!G7-6_aRRK!D1QY`|h9?ry{JSQ5QbifMvdO0PXdll_kr
zSS*ifICW<yB06i7+(xCxwA<JX#;;zZBl}wLLI1js+pGRIOiNP@msqa*uJZDx4?5d|
zBu%*AU$6n8e+gyH9X%s71}_c2t{vc1LJIA>`o^iEOW)}@U3=GYAxhtlqx9H&H~9EQ
z>8;0&<EMV#z0NW|Xg5dB4UbWKTVXea^wuM~Ppr_E=sjF?qlHm{gVLl$(jS@~i`|yn
zT_<B~s=e-ER*Cr{xZO@&Q{D}T(lc-4cR`iM7;8_~cDLo^2p8vrc3=8W-|h6TAk!3B
zH4TZ;{2OR`cUq8fMvjZ+*S<<cZA3JKLO!C7Wqe{|6tGtFdd#nQAU~Ym_38}4mb*)>
zr}fYCcSHg=f>(EzEO>Q~2bJcyD5-+4e~Oe4ZR+ayi{!?}FkUkr&m(^RE>J@6IXL7*
zV)V?A*I|5rrKc?UxQ41`*=mKcw|q3HBW0t>)g1(drWYDooK$v8;>V3&C<YsNEw6@A
zEUdvoY@iwM#{~=Bksk)Z&Q!Ylf-tQ@WBY7cKKM|FMhG==-~El+hb<AS2;l~j*RiQn
z-;GMlJ`T`ZMbK`<E{*FMkXA8+soe>7JZL!P;pH-pMiquNgtO1=*;btdra+5fK{<n9
zUf)?lJXY1}9EBVQYzF?@n*Nx?fUo-ys*QrNy{@qR47&ArK`*4}J~&P-ND4vA5yj?k
z4jO4`8V8VIe7Lov9qAs-u%;FW2oo!|m@+`4h_}G1-_n35zUN3P1|n}sZc(tw`ZIcb
zTtqc6finY+{hNd%sDwLs2uZ1NLnmm4)RC%ps|o|cvVjTs#FRsSgB7IB&`8KL;be=`
z%x|^0_-YX<b8QpK%DsaGNnlkx1aKgQhCN3fa0M3WlNOKvR&`Z*qvT&v3PaGg;7`fd
z{2gk-jxQggMMpM$INfh|S(#{e@8Kr-u<xWW-lklGiTV&iZw<DZMA$0xsBF52+a0K?
zGQg#$?B!?*tvKNfFfV`^;7MP_kO;0AMaz^GJB;q=DGe^&+%;h%Tsbmm;iWu!dA%Kp
zz)Q4BY&knZ84jp)!D1+_tcMQ|3o-98tui`k^oW>(DKp%5!+^oruWC36N_ybWngBgI
z4du`$BM$As8eiWPt`$t#Xe1&W<hU8B<TehC%B|X0<w5X3y=H}#5j;Skg^7aWK>5QP
zRLDUa@cN^G{@U}p$np?OoY&1t1C^AFl%io3A-wi#2&uSo^LSr`<qx-hktQ(cGn7Pq
zpbTd%{@YulhkDaQMJK(614+=@*yk@v6H670OMJJ67(zsavt*K$yy-FQs~G9*j1Tk=
zQ}Yt7NhmE#YMW#o63Cqlw_;dx4tt9~J0Jm$ZM0>EsAW#<I&U7$BgsEP6vUZ`<No3-
zsIs_N-yVlK0$&SxNJKTkTH3gjNe_qny|4*J8wag%4x<fJrcpRhFk;}MrPNEH$n`zK
zL7Sw+mmrLnrXv!4TOW^A(Uc&vYAIe+UhNCfrl4sKRDv-CC(&>cWojXLSd#9mdrjn&
z4Pv-9A(DzRiL@v-rIYRQ0p8oqYu)2P4tYb%zvk}%*NdWfpv;L%&QpV|1xXQu`PcD`
zh;>xg-bR795%fjQ5+0SPFJ+@Ct_&bY;hKO=cv9x{;hCsB)u2E%Mi>4?-d5t`u)EQ3
zUB{+@ibg9ma42}+KoziX6L%PK@c7CBMUPeol8anUj}UQ`z2Tf0rF}I^A~MrSi*I1`
zaCnLbrYP9jCkz>Q_Q*xFNh5uEYn>tAEzb!wg#x9f6Qk=1$>n`Wsc=%vIICq)VKgv9
z5f#TJ4wEb}fzbx9<QzF!&r(o0u1&j!9D{)avKVUvjwAED5rcOiRHO@Y*o@5^AA&|w
zcG2s?zn6{zPliy<4LUNMk1!sU)X_Fl^MLuunuEBRP#?<DMv@OID4w)fa>O<a?wB!Z
zUmO;eX)s`15+v11Gw$u6@;aUY80}U(GRoym{T!0-Z_xZ9AjlTztdK{t&rh&)(BX1$
z9?|@!#T?=&X`ReMuh5S2t_3r}Rw#K%E<N<COo7QY8szWc80F`T7>Tr$#C=W`GK{->
z2*^d^I7|`MwVo9~?C#sG$=HEqRau-32uZAlZ3$e>!A;1Q*wnzNI|Xa}9b&CuVx(A8
z1O)^SZDu;i!mkjBu{3__B#$gsG&n)|eCmL!aS&-UM_XZ<#;<v4JQ>#P@MPS`SIt<p
zjK8E~4y!UzO|L38;%-Q^qP4j+@KG<%BbuT*EMCGihA$`j1qS1I3Al$YuA@>4xKX{d
zlR`PwBbDpf@+iB7lT*!*$U(mJ6eKh*;M5^9LX|{;@oc<Ok;APnA8nZO+;0?-Xx{Do
zS6qf)6}H?o5fT|ZP}eY>*T*@qR^PYlNJ-TuRFM>*N`aQjS?|;%K<OJ{aX4~Nu}<Sh
z)bT+bH?iCokH}C%L+Bd40{)_TW#by{f(C$sy)`W-kE_?|Wvl?H137f>{Gx)_Q@uc%
zJ;uAOrl6^bXhWv$@a(ecbDB<`9>v)k1|Dy40|^KJykiuFw2kqe^kO5`4R)@Lr0)7u
zB!M<%mSIsK{l0kl5(g*BQjNUxG1P|R6;m#;3`G!mv{i(G7CHW>{uBaV?=C$FUy_EM
zC6?S*@-(hP*>T`4m8N8_0dL^y#FN56(mLXmR3G`2LTJYvdQ(eSBp5|HqWPE-7`%Y`
zJci-47l)tDQH!d<PUKUs14U`qGilgIfrosYcaThlek6b`L!@>9QaWTCW7@G=B8Ch@
zOq7%$;6I{e!cJastMNu@wq2@+_1I?8OW#c`@FIvI>QEWJa$A^bysBPmsca!W1T@Pi
zBpuF^kg+<VF)4{fxN7P&T2U{abDBsc(O^~363~eJO@c&z>g6ak5Ychbp5>kA8Q#~#
zM>AMbYKO}gSr-z!NlT4(U@Z-n)4_*z#tTSQS8@x&3q`DgQEi;Wmuq4x&T)-nIDps1
z5x^M(&M9Xc#3h2!@s%YWeq(6Wv0^~DRg$#Pf{;oR$Gz5;RIQ>00aghuYzgN-?}p$J
zgLn}PGl@8`65RmbrUp5hEnA?2MUJ(w9;@F%-M2ENemXb9*OY8cXvCU~*DbWFD-Y##
z!w)*EX}nQ-hiG<mT0&E0sy67bJ-mU25ikvF8bzOWEBHj|U`P_ZjAfJ&&8H|iD;elW
z3RN0BMi|;l`<D80)Eg#35as-cx=KZ_heXwW0-d!qG*qux^O1*!UIY^5(5VeU4_0;k
z-s`cnp=l2?hT?%R-cp4vRX;$RI&uK@fYhEAmWF0a<7>4U;SS_IKVDy<qZ`L*Z|#t!
z!nyc9LY=lvKp66=4fT5VexMLjtSmu1rK*RkYZ_wzKf>MyOs=9z_&>M0W^!lJ2{%Ir
zh8VP_(+Qn0U=s(-vXQOnbYcgBHX%afW9ftd0|Xh}sI0PU%`o8LX7}GBD7yN8TQ<nJ
zqGnzB@M~!zx^b7?jfl#^D$y5L6cqIDqW_m&d4H$w#MS3{pXWU@w?0mtI(6#QsgGOt
z-fB}vYN(u{xzQz6%p8Rx3bgz)8yO8Saf$NFOP3z{2SwY{UL<5m+d&ifi<x8uq;UbR
zfRiCQec=9%u*Eh4v<*#Ba9pX$Zddh6826BXp_$Mzo!#pz+sM$7MW87$PWa48#6(q;
z4){DwigQh`Xg4q%$nP|)gKp-KBqY{x!_EPx62RIpqNyJ`09WQ~zLFz>f?|yvNfJ)R
zvG9qN_tA)m@Y@EWFYzmEbR_3W2?QKp&2?de<;_G-gYZ-fV<8e)S^^!k59pv1`-38_
zQ^!l9<*`~)Tu*hM51ql!^%FGu*(2@aakz@;%qpoPuI2e^Z0oA@gGsm)T-!y09tQy=
zrrF5JRS6VWQ;JeQ4VL+;GV#XDSE<b+1*RifL05E~x1h8!A8uEJQb4Af({)yre(CX@
z!-*QB&5^AgHRUzj(1a$HmSkpEu2d~6f~Q+1+DE7XgP$kJ4Ibtdv(tZAa(nHAGOZG1
zwrrReQZ(gchsY-AlB6uQ+#fTrbcQW+$2@!C*A_+ge+~H<w*z6(<v>U3vsxA_q8^MC
zu%g2>OSJ0PDhw_p#j?F4oD6E3f~Piq&fw*c%y(&z2)??ct5~nj5fc$LXdqVF<%t17
zoP?aG%5LcE0UvPD4H`;&T6Rc=Vt<uX8qUY$8B(L2IA&I_m5S|^t5@2n8#Yy)=ghp|
ziGw5uH$ZQqP!!tK2>`y5sH1|+11sQ~Eb+uJ4ie0W$QoiH5z2;k9$dot+d57;8iiVD
zin<L=2ZJCAZeBcso^tqT5$#9xlp447(?rWh7-M-!OpFq7IG_%Cu`L(=h+JUPz&F$U
z&fqvPibOa=2-6`S?TDj5zsv(ZPhZTi|C?Gm(Iz0<AukC85h%&!;bc}3v7h00wcDDI
zbQLL{e-ro4W^#5u<n^qn4fBDE=7n=yVj%-TtVD4EM{HooV6yVWJ*y9RXofiE^kifv
zl4?b?`kL<P0eoSzm>m`3urZoweaQV-c7hw!qR8``>0FhwX^Rr0P8*=0ObeX?`}xp1
zGb2N^sfV`fK%1VLtEIz$0*08G=GD+sU3-mCGA9@iQ3~Zv0>DXub%>K}QyPeR#$Lt>
zU60lShwxD+uPiu32IS^{Q1OD&Q(o-lV2#q_`GVZ40R)k{29CgpBjkb<yGbAb#k}^9
zd@ta+L4`!Wi5gdaJxe5C_cK~a2wEIhTH_=9fN=%V8OpfgQO<c)h&cmQ1oRZj;FsV>
zL~JWWjys(C<1bo<xK>P5$Lnf^wg}WXRtcL{X_>-RCT%50CujwzD2089Dk#;*X?Oq(
zB4La`8(a)|&brd9G8GGjsNsVcuMD-sDW)|-^U$Pp5+Kdxc3N=ONI|Q>vx8bTkQi;v
zfKBA_a^#f`Tli^VZKLcp@3{K^4WRj13%(JbRa|BM*jZiKz{n^r8Tr&9^(oRvM2z4l
zM;8opswct$HbLlyzfGbaeN3xrXqY42k}$Md)87T-wFK->s}U>?;C@3E16rbLXNeXv
zs1;kLRLDp!<kcNrryir3k|@1`&aO75$8vLY9uJztHDB3uX8u+;l>z4%j?(Fr-B&~l
zK}B#}`FSp$6H;Lj5L&H@(?vBYu7)x#TN+Rk&~e9dGw3wQ<qQT=9{p0qykJ#^60`T_
zk0=JtKnj5hJCeYtrkEo+q^H43>?X*SIMS#!VrYPzDs6g->IGo92^`g=?U>%J@rY&0
zl&@<@I~B;m7S_k3vB2rM`7f(PW^qIg5R~8_d=zS0#fmk?*EDt14(QQ_0fxc>ACjbt
zaPTD}r+_u7FCY{&Uc5`d0=7;Ej3FIOa&X#SHNsw15!GQDF=?>s#c61*Isx-__?`>j
z;Khy_^=1Q6V>Q(~f<$_lcD$dj#VnwhixTItC#nKY+baj+{8Qmr8|Ym~B(#$le{4vN
zN|U9k1`cI{mvXYQdY}{fgA7#EHXW$Nsva0X#<)?G1~|!iIrI>cI7PZ<B`VlMM6QlH
z(#kg=(g3qIs?+f_S1RQ*fVnassY3^C9YK8FUm=sgMWe=Qkk1A}nx8R~T51GYLmYy<
z@$(39KrH`A(A1++;(;JqNeq+wxIl8=((`^~7_@-AMAEg^+AQ9v7jMvzD$wYxgFzwk
zIF6<|jsiamKXUN|I{C5y&1esEU|{AF^_^6LCmUD%r9Z7IQ$K8=fHnMeS|B+m!pqBs
zee5)(KrH?3aHJ0TTtVKURJ$7l@B|Wvqo#|83RODnJD`F%kP)S8InXhMm{U|{)YqmD
zBtXkqX3B-lSm=ny0Zct0M)?gE%nOoQjKW9HyZyi?W3s1}zRw*qYc1cQhqlvOnv^TY
z%~<0(A3o4C)5$)|`lY{K>644uA6vqPOg8h?g&v+?uU6AFhoqd%*+N2zz4ZAi_X3%-
z4b$o+oDa85vY8R7KGxw-S3RBQoHD<2?T6C-vOgq#Ah;?&TW5ytt<!7|c<xDh!<Dv~
z^d{kvQ2k69o=QipOmdr=95kLqzUQ7G@l19@rM676{>*x;5L+AS+1`CD`+}6&w#l|R
zhd9kjHLLTfHuKv4@&d%m+}e?9#w_H&Z+xk5*15fAk<^y7+gW*Whm&f3nDj-T4i6uW
z3;#9JD<{nrv`lBoJILQx%RX-TfjYx)Ghgl{Wc+qr(z14KW77#|4cAzP-yz$JHW)j$
zaeZ6QhBM(xKU$-GPF?%d*mN-)aaT4tcz9+r;$;`5e&C$p(69w-YA0^r_Rm>!4!Lb#
zO;!yhtz@QHnG)x-zM)Bui%F}Ydfi~3C#N)a^-FCid8@YNy9@{h3tKNQ_bt6;v3==`
zn*<v;YHoke+e&e0`kW#Ugttl1cUcDKXuFGsw8=tdSMY4I#Ag2Vq8`Rnr$v}jrh9u^
z_2ZuJC(Q0<GYd;+o%miN)!PFPC~bO<4Fhr6tiNu_zDyr^vint%ti8r}r~RlgYw2o3
zwlGo-`qIGALdJ0V!L6%T^_*{7KbVz_$M(~;JSI(NvX!pkWvJ7?W1)A0wS(JIeb|2*
zZN6gGrT+Fxvd-5`zqPXUvFyyTTSMARH@-)*OIP^08NX{zxGNg!SRRMGrCFSo&U=!H
zEk4_}*E=c^t~%T&$({nH(P|gBiCNo~*H1Led(3e5s*AXP+A8-?4{RHkx0LuL%-PB#
zt#rwfDo^6P%XZL-7RzjPaM+GE>{E*wIvjf>Bb-y5WJlk+*E80S+73U(*4UIKd*qyD
z{EXw$ZkYA_7!mt{<-YKHB@tJc<hI#u@gqyRBVqkP2CkOrn(ggNE8V`JkB(b^#Q6Z;
z4B4^JMeoL4x9}gAP5kS0Dcsw4v7UWf+fdkEJ?pG&_62*=?f3Q_zpj1Ovg(erhI)^7
zUUTUE?xgisj9*y2Y<yX7s8c!gNEo?$-<6lly=L=;%|p}Gi>7Z`d-q+N-+2G2n>Vz!
zo?j_GvTF41r#4@Fe`WLbLr33oTH}%FvDtkCe|-Dp1I^Zj)5{y@hSKaW`WAh7Ut#%E
z(~rEoz4MWm&))msNguv<X!)M0Z!B-`czn2b^aoCQ^sBd?RC@h|%iNX=hkD<*?W9LP
z^nsP@uRQCV>WLd(?%((R(QRDoUs<?h^y-02wteRPmBu$dw({<iM$Vc$Y4e%S&0x!q
zPgm}~Y(w$>mE*7Pd}ihqlRy7TtM{X+bF{wC|6-&lznVJx@Q-fTxc@yj9ee2KH>~*8
zH(xyCS3kJAwEggkEv4^$W6iUd{_URYuK3$ye)YnN&G&xmsMU?HJoBSncV2q)%=gZD
zS@G}tl8erN#jF1FU6;J|-WQH~{lp)A??QX@Th`t^^xnz6|8dvm^yj}n{Or{~-qpD7
zYgZlo+4r`r|DV5p+5I0ou2|jo!R`BA_{2Lt{GV42Uw^};qoem7Shnwb&%N@>;k%Z6
z@JBy<$D^P4`_2FP!jBg2`PT<tcKwt04eWX1*wxpc{_54GAOF_{kKTXdh1>7#EK8qw
z^|jTHfBR2PfA-yH|LHGoI;r@=OKS(W@L=yht|*pX+&EhLoAcLK-{X&cdPm5D>t$MB
z_f2=wy18QC@SH3fxWm8VvCsU~rH3!O`uyj=^33acUvZ<OJKsEU-FT<8ZoG5ep<8Z9
zx*sdPX3L$0v#!7KA2+Q3-p`uZJ(mvn)84tFblxAW{Ooyl$=;C%i=%5Z85^o)rEPw^
z^Y1U~Z>>)+c=$NCZFkZ$r3cSky}q(z&%S-NvC*B&`sVH*s8;T)54#(7o-z8(3kD7k
zFF3BV_gjOvp8d<yzxe#-^7W4`y=2cbeaWtW{3F*MUeLGvfj^XOW3>w|s#RXT`>~rB
zmpYeMe(|=O?5>^Di;92s#`G|cBA5SgytwYacBGTt$+^ku!7ZK3Z=_RPlj-@sweaT~
zU2momzCYc+|F3WQ!(aI+|5&5YpUoBC(3$JICj0p#gZAg&KmO@mgU8QZe)GW0#_t_B
zv+-4l{mRh=_mx|=SFboJo4Df2743%?uH3VC!>JFi8h*#Kn<}G?Hy_pS{^pg-c1<2!
zv%7WJJ+<T?w(jcu>qQUkyK10ePj{6~%Vc!t=4z?u*F5&fWwqsnZ<_Ug`>%_x@4n)!
z>wE3~^~au7Sby7@3%ASS<F}u3@`%0g{AA)UU;D?^%bq`K-8G*z>mU1oS^sZ;`TO_(
zZ0zK*uU8gVKl|q+)z3b5<$m`t1Kmujb-QY>4y4UpwZYydIqkrv&aSYn!_Tc}cQeV~
zpZ57}>B_OS;o|P)2j9?b%(gq$Bw;*zS?Pw_=3015tupkP3u>zpey4S0WhGtl=3B=%
z96P&eU{z)9M87*{Q+@I@Yy8^g(4pEy?cYwVz2(_Wzqf~HT#JX-au9sK>u+Qu+zhm;
z_EnQ>q_EQ!<-!x5y=!5=otY@wr4!|cJI?sQi;M0rccqmJ$HphVvisahB}v_r>*|$%
zt(@n7@079hkz}xW%G_x4l&9TTrS53B!Dn&5^&s=jBYtrG_m0|ocYVR_yKgw^tce>I
zJyN@)Z~OYNGM(u5@jPJR8SUDJ+jlRS`eLaub;j@yldIPK&0OJ&JIr;@e)Fv3!m%5+
z*S2qHSDxP>)$g0(hkA1-ezwhh-{A%3qC0Oe+m3hsy2DFO|J9q1OP}>y(*JB1hsLTK
zs(ZTf#xH(ME?B-#F4)sO^O!w{Wy#!%^!&Mj6<cbhq<`H_t=jB?MX$+zea74N+-tUs
z$t%XL+qm$I>qfHX_Tk3se)WS*i+*wEf<@QevugPC`|T_D-~XYLK0ouF^P1Typ89Ro
z`i*{t>t}C%lN@;68SDJ(20xoD7;gX7N*S*E#p`<Q%mwi?cNp8t3L`$-JnA+kyR%LF
z7)7tWaJJLzgi}p+a3vG-aC>}xt-j9fXW_PgZalO`C(~Acx%AO9%VUei$4is7?KPj7
zJ#{gSc6;mnTXy=)kF&Vu24qEhc>B{kkC}9X$JV-qC1cgPEuP#Sl+)fj=3d(w8@=-A
zW9;EmZMtXZ_q?>$?lL3x`ed!&cFNXr?NsyjvAYtnhg|<$tJ8lV2`8V?cOIjUpS`Fj
zawYSUeb62wX5ryxdDH!q)m_8B=_d|K;o(_U|F;)*rgKBDopYVK%RV~J+`f5V+l}w)
zC51I}+4NdhoG$rA2Y4duvUJ?JeNr9i`Vp79O2&<)Z@Ei-v-|y#(aPv>%@!vzS+#X<
zxV&ziYg7{1(GF{xo}-e7rCgG^kx3_OO0HI|yY_B<WrJ-XH`H9>?7GU@QfI7f+|*94
zSDrUv-?6q)EEgvG)~>v6WqFK&bJxy}>knCZr<k4P)2C{e55Ko^g`6^RMRR-g@@yz>
za~1XM;`<qkW;ss1Bj)Mboo@WRsp|$j+vfgZE(uP`ho!#D57nO%Vf!ofs;}L__io+m
zq`Qx0j!4<*dxB}X>sYhUzsv13Tg7^yk&IY>N|RfrcCge}wx`awQ)y48)zxp|1?45B
zvKyDg-<u`vJw;a*W6YB5)a_+)Bb)3p*N}Ho8neGIwi^uEb=zmkJXfmK49jm<8%k>}
zgOqJAPmjrVx65VODfE`p#Ma&>MR#5iWvYaFcJVcT#Eo_8HxX^Oc|k>Q3H4`V;KcIS
zB0p!Ri~eTHfiz=jGUyDy4UA2YVUA&0ZzFJk_`A`=GvakH<254FYb*K~bz~TJr!_=(
z+0)VtjyOrzW9ptnYdrfd8@4%a$-L-q;2LWkiyjb^V@KsoI}QJXlJE;c({{Pu&{)~o
z7F185#@R|_OF2PY9)ccE9@2eGEv+C8>Psj;yZ8@Z<N$2pP-Q{TELB;j2`dmuBuM=E
zPZu#|87Dmu){8}^(hy-04#Mk2@d`81#ZdwWd4QQ-L;;GQhm<UOU&I>Fg+b#%b92g-
zLt4aF8jo(e+_ca*nlhj6G%elE1<G}^ekUc;+<baaQXjViI)q$5DJ7W2(~NL|ga)P=
zRUqdTq3`%`<TRnYCW?bU@2N%Yc$IFM?k6ZHYX!y&+=K9l`5loO*E|os!PR~u+()$r
z@U#rAgTu{LgvaoO9$Lz2F_$v*T=Sq&SaRHH{|J>H$0+7=s^}^jZ@fyPx7<!FG>=_<
zkDguprk`qxlNY{y^=;Su%Mai7$N%d)ufOHK^FRITx4!bWXV3b{`P-lQ&bw~8@50Yr
z|IHU~`}IqAp4WWttye$(=o4Ss^UcqFXZO|jo%`MA{^az}eEaJE`p<8F{Lw#o?n@WG
z_|n@?e*9Z6-n09OFKv6{wf8*n(l6hB;^R+Vd(Yj(H@}JWyI%al-+lAiJMaG5bLai*
zOZQy(;=jN6xxc&Qnfw0hAMg9q%|CwW!pHCX`R88x_UFI!lYhDAg8zE%mv6e|zIT4^
z@4orzkGyp4edm7d6Mu5`&!7BXuX*96PaOYW&pdF!6VJW0=DSb6c<mRT_`>mj@(kxD
zKljTu@4xN2SKj@NFI>FtpE<kut`|<c_q)%0`WN5$_;-C*3UauYpySfN9TuJ_d3vzN
zfWN#L1GUXd|LOSjoF-P*L(dNmdyYbEXv4M9^5NcADRjqOGUxq&xJ*`}NB?mzq1%xC
zPQp%brf)!|52td&4o2b2hDgtb$0z7KZ3z>!M!18XF^9(6sM{rO`sbM}xFgGUxOM4&
zv`>`-JJz@d|EgvODn<7XwE;Qj((+8<duMRa?Vw0^q3i7Ew<9Ys=Tin`>y?FUpF673
zeobQK^U})Z23G&EumE<8)0cHQx|Zv=K<oP(P(x8b6FHdN%iMfiz2C_`k8egl%*W=v
zBivA{Vsbm5Ps3xGgsa!@K+Z~0|EGfHC3Evx!n_~7`SPaZ2mkq7Xis|v)NACb+3wDc
zo}r3KN15z!_4XM?Ioq9POjguWp*`i7s|dZW8wv}Ux@@mCyi@cZnh!8taI6<S>3&Ap
zIM1`lwqxGmtzv5A9lJisOha4~@jvTVR~R}MF?y9|H*xft(EYk(X53hp&~ivjqx+Dw
zm>9cK+qR@;Z_1iAEi0L72t4Vub>=hG6Q73|)9Yo8tkC6%be_1ehMDbgCa}nOEp9bV
z>-)N96cY?B!+XZks>yV=yfy1<2QpbaQZ_w3iq-~~7Si<Ay6~VSE47fwe$cTOIwCWx
zZ#<0+!8J1Nq~cxCcJ%w75!dx+rZedcBdCx0h}}KU&WPb<Go7uCv!M!)l=qNU>U>zy
z5sDXeO~R|~r$2n=Nmk_$-=n0YB2H<`jHrj>Y^J*E`a0hP1-2!uXF@CbdVCj{Ni!ai
z>^S^iwC&z93ya`Ab*5qWrhAP~_x8AF4Rz-Wx(}&IBeu;?Y+C7N(&$MAiL|x+yhBB#
zLCyE0AGJ$#7SkJ=&ZcA_mhnoslk|GpZ=hGFnPPz+aS~V3sj?@&t<ycipl4RFp-R^!
zfnq{1jk;q(Nl0jLHedo;EcY44kzTELheEgo6!Wr5<uy4ly(k!&P#O<&G4Mhyg!d6(
z9i-1RRKj!&Kh?KLTF3ETFmkgFnUyJP`b^dcB+hc7v!`Z9RG>AXy%_}Wf7D$$m4#w^
zlxW%fVDOu%igemcE-b7-IqEdxVb7YuL9Y^Kp&A6wG2NFk*XCzy%fx#!a%Kf-#i3G#
zSQCn|NU6HO+)YcIdraHz{r>_1x^!7(|AQ1pUm23bldTen46E5_VZpFLCdPY5oO05H
z6{p^(!7NQQBh1BM^_T#gN?po<7ie$>8O9SEh$&=dW2O_^?fabA@%&ME(1e6E^(9G~
zysTs?QMS=169b+d`Hi~d3AEa}y6f<$L!6D@1(1)tEZdPYTjCH!*)$x_Tm=5Qai{r$
zO9s^5Ya|+4iZ{zw`f)_b4zP-#g6WO2d|G(!)Da688%A^4rAlAx7CW&&d+!-5^dW_n
zX)32hQCDW6B3p-IhOrBis7SilAr-w#if;~WF?gBAi!qmRp0KdC<@Ig!;CKL#P1!)d
z&YY)92aLB=A*-PZA*4aPIG7EKe)I9CXK2B^cjHOKPn_|1@Hc|38c6AT*b~~Ra?M0h
zw0Px%Xb-8es;Gh0G-yC`t1_L75;|^d672(AymHHES_$<qO<teaU?U$vENO7L8YZ5M
z3taT#Ceq^<xENY67SNG<c!<Tk4>H?7i1Dkj_2}C@sEv|xHQRybND)HpHkavhs3OLH
zh-&&ll^Ey`P{&hNji-1qLFKnI90k{zO8H_4e*A-lSo?d(lubl}aa?(M%FaVIV<v);
z&f=Iss)=L3S`JNJ_Ts|M^Rq0*5mxGO3wBi)lIs}UG@V{lr~mgmUHuOvAW|24-gyd9
z2?9B-oiCRTpn9X4ritgWX^v9%gyOoeqV0RyTVu2gzo=t3D6T!Et&s#Ro?A1=UJ3Qa
zHhRu@RS;t>?cIhbI7fTYR2=20_t9=$(x=HJNp!RlnC%SGYJ1WnTsf0BxrVTeQh_PN
z;raq&UqYdE@t$~Y3q0HRF3n~@APQxQgNH9Ka)cA#P5L#3PGtqVk^U;$6W;-aj(G3e
z^VtUlWgv({2ydDO*_cFK+p7R1ETQ2F*b3U!Z<c(d=ywet)JzrJJcC#%e*P~YF*rHX
z_fscKd7CGuze*18fI~Vm9a-yZEFd7+drh%{kn#kx3#wRPJgtH3J&~ZPD!W0q_m};s
z%Bav&ImC8x{Kh8kd?RT6kSD0Fd43R}*Ix|Q_WgVvUHCyOHwbo3p|=w?SpaJ%MDDQI
zIo}$NkR|Z5)us~PAQi@iDe+ynN<XwFsXAUN{U}=#4P;PVBgZb7=$AFICcZn>;7fto
z{*m&buyCi8>8}_cMyj;>p0f7|bsN&Ywpp7b^L|3d=+!##TV|#09{zf#)7|bmeM!=G
zT`Bf2G%mm(X>gl72NO?(g84v-`#)j(PrJYGSQ+U^*|$IiE}g}C1{?6R@yVkUQmr)H
zXR~HPdHu4gGp^R~o=ES7#SFPhNnp<R75$d0M#aVE?c4IIpDhM06Yz8bV;$1c_Gt1k
zZCUGj(x4t%H?&EjB-)%(Txb~IhFv4jcRluw!h@lVX%g2BN)vJ#&v}U1KB&Sg&T$S#
z(osv$Qt8V+@V<?&*JQAtdrLVDWN$Tn*^5j6tZdp09mC^1=3{suXMc+)#6fGFBsXNq
z(V5@6#Ccm_rt!7WO%fV@s;@nrWP8!3xGJx@n#yFC3MDSNeXz{uT7|(wGc4CogvEsH
zoya$1l6F1Z=~2?~63g?zDaKt1`#sN$8nE#)a?!MF%CwV?_o%_k#Bs8&Q8?P#q~DZ+
z)@MBNQ+r3BGR~1)t|ffZ#l00W+knkiRfTSbr*Oyl8Tnd;aX~s2PLKBi`Ipe%{0NwY
zYFi3ft5~Yr@@jrNM8AD)us+U=Ptzrsugr!7-G*%cg9Bc=!p^*8-EgBBE>&Byvnit+
z()4zCJ6USyY=`&o2$mUpdWkX8W&!GbJMgq^NKVSSNM|<a5LWF>k26l^uh|6Yvume(
z+4Jan8K!WDr`1NeS@-c5B$%@k%R14uk+^gcET#*!8o#<+as7rmJ2hT~#cfgEx`dd~
zbpnl`XmPFmidV4eX!nDP7SnlEBclC7$79!xNeQXUZcuG6Cm25qnAw{YCGe(40(|14
zW<kEVY-tA<xi{dY$w8Gc1p(j`Go4Dw+q&|UB%-<f)r7btu~tz|9hK1%geXyLB3)RK
zO>=1m`u-#o6=-N^#i}`g>Gr|f=%`Ip%jwZ~yA%L8b--os-Kf4(Cnn%`G(wFlx-JSD
z!llcCbdHE})atl^&qY+TLYL;>kuvmqu}Y=G&^)*n6?LpWG3{8O$77@{V-*Rlq}pfm
zQPdd4YuoLQqQTdK0b-5Sw~1p72>7TS4Iy7eB^fq~ECfb`G!Tj~jhjv<xZaWDkVZ9P
z%+}ObPsw8>XiX~x2~Nt48OZhDzy~jV#Jr$n@+Lv6UpE!aqDsn7{U*YM6*O-$-L^si
zNm`0^2S?Nc=!Zdy1sS)5+l-_=<?BP)s{n3RBal(+Br=HOof<@DO7N;`n$|Ze#%b8V
zlAIVdw|tm4NkNo}N(T=@6seF%I0)lDmyOfT;{~{S8C5c$Snfrrn`3QfB#;F@h{e@o
zWFVZ21;K>maSGs*<+AGX2ttF}cGdr%K(813*_a}|Rw&AoIHD?>Gr5F^S#;Sc_$pYg
z8u&8fOH9T##0GtEkMw$xOLeYQRN}}Q7nx(UpS4k3o~Zggsmoj}Htq`|k22A@CejQX
zu_=FREDTB;Z6h$ELl~P79|)0)cGj+z4jUKo1Y%Ou0<5PZwq(>yB5ox247cx$A;CHw
zG1~KMYVR4qLd^18PDN{CW*sgU-x2`YEz%7=^rl=Lb%@-t83ZdUg+dm!gG_+_a=KfH
z?_@D<#7W{*RgC*e7>mh^U!0(<ZStuuXS)3P5nX_yMkt+2X@fM>3AB(soA^BR=e%c}
zisC@#l?(ec9yN-E0$t)W8W=DbHJL&d`jr~Z1jQFRnNw5s^kXkgmNSgBnh+sSofzZx
zRu{&Mxy}=^Fs+(E(=hC?UZi6pMjt6v+DRvbSlQfuB;mf-_<3zmE+rb?yHNqmc6cRa
zmDO&*0hQJ_i}xKOVtt79K?Lg+p_21XzEeN)3yK5UQqpfu$gf}40t^$LB3b#QJL)ut
zCbnRPjJB>3ii{f4ylJc+Z<~l=2ZnoLT6lg8L{EJ2;YGn?n{gE6H#_01w>Umgeei70
z;GqLaTv-)zh?N!`m>kik)=FYKU-}&aT2CP1>I)ijT*Pd^4}zw>Bok?km~=y)nSv?i
zoG=n#>NEw2x0^Af<^j+iJ=iH{tE_^ubvttVRRTpLma5J-=)J0eSQT7PxN0yP11^ax
zVik*+($LPK!)VBd-HHg@dg%Q*-$r&cu9OP(R1U|07PZehv_~W0Q6Ob2wxJ$-G$cta
zNWCJC#Q4tub!2o<etDaFZR-F{khL){v=X9NgZds(ZdceHXn^532k?5vMxH#M=$IVR
zRJRP7x6X`NV9pRtVGI!-GTv8(gSNhj@haRxWKv`Jq??=!V!<UiIn0nH)}Cp=&*Qvf
z?zYMmP(SbyJ;nG)tD;jo1!|j;*p3mpT4x&SeiQgjLGFLyTkfhPUek5$rqAG%qbyJi
zeZgrY2dCb&YKj69wn@4$4B+&N5axZazA85cG~(1zkF5Ok2+{?{0)=_@ft4()9+t_G
zR$uC6)Q&oeWH@Oc8{o)f2_rrK3K6erI8qk}(zk*x69IO7talnBLlF}o5X5Qbh6<1-
zPQu>U7%~GADzDzxwJ0cl0|=j&=;-P#>5v>DnjwXgjwlXKi>Py{NUQ%tiJ}d}1gp`y
zF(d|U>z?NGiqu($<-;`bI;qMG;{8$<8!T~ngWww}z3t4w&bRFjjnZF8_sXr|f?^Z`
z|DF`h4Fny(Vw7QJCV|*%76QVc?-W7sH$YANkw{+olnglxm7_nN<C(n+u<=swk7)Ek
zLVzv((}SAt>&~<tH@$h>Qx|Dh;!cLndCmVGb2M)@ju}lKVHbI5J{Rk%#d?neKpK4$
z-O79gC2cOW5fe#{gpfvgMn2w?#m;I{qV4YC6<Mic+Yl)V{^IHe@kGbZ91?>D6L+Lw
zZOcFS6^@n|ASB@F_8P6usJTZ`T<(DcJe0kNa2jO{%XntW9I0T8x}LhK4^>y)GTRI)
z`w?(a9_ze2f{DdM;v<+q!2MPxnkoW}L5uM?A|qILEK=p5{}r_GJc(2$tO#h`P=XTb
zQujAdBji<9ZI(z*^XH<lJr(Ofas=%!*s7;=E;I^Rq2JF_vwBrz<VH{Td0EU1iSw+|
zG@FE6C)Vc?FouhgTk4CBB(Y|>ECfA>BQ+oxByo7;Lf87UA)ZKxuA;5B<=-S4j6g+#
zc2qmBL(_q}=#S7>y^tps=%Is3<9fdV8JFkk<5CF&sLh1Dqz4oe!7-)VuGb79BE*m5
zJ5Q|@qOO=f09wJ^tcwT*&7i>}>GeE6yw$9`T6+}+3XieMKEgSLD$ZeFA*j;4RKSDM
zhSiWXSgqx<YP=~$O_)lI54jZ-nR5eOH`41Im^O0N%xHRpS55PBB#42Zi_0Pk%=-@U
zBRQo`)saQXaK%g_ybKYNFvZ%4VU`r?r)%Ye#e<Hrn#x)_sFy>C4ef|D%(Ntq5r@4a
zmBq`a4zV`6LMVxNS8v$^XdjD%01*Qm$E8LwIXFCO?{%%fKj6yI!_hc&UdP%9(Z?2)
zJD~PYD3FI(nBwyEf5IwzAg{)iAmDNXZ)0!g-ojbM&#;{$QF5welumjF7;{{t7w6~z
zq?DC^k3(Q2@v!;Ls>VR?r{i810ooAIS(MtN63vux%|kU`<^;HC8bgcnn@^+?iJM;q
z&!@}KEVTo)8A~!n2|>v{Od~iNPdlux<`k?9C>wl*EfvgJ^XtIt@p)lK6%xZlrS4Rc
zSi-C~M_%Y59XWEjxIv1^vH}Ym$k$C-0d~^g)OLR0$I3?;s_n2!pT_Z+c~D)Gbvo`}
zI^7TTk)^4KF|<>vGTIPp;?Nv1g=uGbw3gQ|!LXHzfzsWmat0fyenf?QtP5Qb9+JSN
zFu!o_%|tTCyr5f>)JCUd)?i-=^Qz-XlFNCaTtY+nWKJ*=1T5AXjE5w0&u5Ae8Zn9>
z<9hN??8*^e>_Ms3_PErC!Cl{7R}FgTxI^OICuV$7Rc5w4AqsOEvr#o(gM^#n)sFez
zA}*SI6Kv2Vmg|X*<?sl~Lcy}1nESX54FT~kjzPJowf3BeAf5Sg$2FBTjjtO|@z_A3
z?fA0?SQRL<_;4=}@;;yer4R~(ODRN4(_;0#tk9ykBp+vkgD9%V(LFR0tT@O3t92(a
zM8OGG98Lt%y-!Cx5k?suX!42J#2!sn*dKuk0n*uV@quhy3d}G8ubu^iTmem6{Tt8Q
zK=q_`bX-xvq?sOJV--WIIJy;u_$a&9D+i(jJV?tU4s7HX>tS^G;5l*J7q)fE)=cqo
zv7hQfPzyyCr#X&**E0b@pu~B!3!c!S8uIBemTji@G)<h|lV`LY6=Lf*vhu2zd>P2M
zETZz{m+@u|OGv8-o?Sc8T&fGe8zMnvn~72VPUHu=Hs-W03EgfD!zy{-k|}22-b~k@
z&}`25tFz8b$Gho$gAY~odt-Uf-DDcO!hREyW>sX7iq@80BDYeR()da8S;O-M)90GI
zd}?32h(6rqzK3!snfnVj9B#>$&)g<dcR0IDWbbsHJ?xGPE2J)$EgB2q=xmmApj!P+
zlkrU2$rkq754B1=c<$l-rB2?*D0eVxOq-T`Z)g?P&346yvTcdHDy#d;T!GPVN?%4y
zudB6Ju><#Bo+r-mhF^>EZ-Z@4m$TlDj7D`e0&EsnxKl2sw(U0dRlG0xl>6QW--BG#
zzH}s&S6-D)EjKJi8P(d^gtR@Y53y#elfyo9J$<B7qNmi2`~znR{y8-rD7AIw^ff=^
zZb8u;H;8tJocFFPOZ@Ci2^%t#9JJ<|oy7TB+rk)4Gp&zJbjEp?(O#zq%VoZv`2pu<
zcZ&D38%lxg+_dIp_A~TA(paaYNMF;oT(nYX=ya!=Lg-svl^ao$Oxs#lpWC`jZg9cM
zVjsG8r!|Mcft|Suo-GES(YEdTr)~&YsoI~qZOKa6=Y|3=Uu4yO=ls+xkH4GyI!Lsa
zeA)O+Y6CyD9JlvrBAFesG9}q`)*usmW&?w2+WS}N!h|OteSTSHjR|3(#k1uRdj|uo
zOH4P^8&Yo78Zy01LZP0Pd)q=dW_Y=H_}y%rj)_cn8Q=W0lccO>&-bzwztInqoq0H2
z>&<c<BdhFDp5mu|-k>e*wz^%Dwa0|I_;98Ugm#&?6-E+lroX({AKd2Jo?~1>O}tyX
zUH+^whSDnCgx3^rE-lOW6shzN%cz*O^4{Tf((KRt&6ydMEp2(8=ckM8F+9w(ZjpGI
z9&75D(@IO_bV|1E{UAr6%GRx%(Pe$FMq|`=`{v@zZ$IBTUF+Vk!TU7p_hD#~_jQg<
zsfPD{#5ZZm5j(2ie0+c<Dr<^%2x2?;Rf@F-|4rQZulmEiE32J%e|AxA{Eb`F2an5U
zKQ_9&GyOqZ8#(R*H!`p_+;sEurPEWDu^()HnY-+qWnsFr${v^++jqj|S9DiyUM61-
z#E%`j`-IJ}|Lh5y2eU6vud-i0`n0`wy>amVeVdQZ4%{*(8_qpu_G7OYzWvUD<FXAy
zr`hqxhtho~T)%wZ%5|j;=a%HG3y0EwKW6ub?>cpNX~Tu3gU_6GUhk`8qla!fcC_=g
zOSYv~zSi^(lvZw=9;*yr^Lms1<PC%V@mG&F9zSh#`Pt_$9`3tru=RL<>7geJm50yX
zFsSu?B%p)GZz&bOvg54Q58j$~?)jti`Fnmi7|wa^$=fe|_}aO<ZhFOI`@;I!ue@h{
z@6J!ZypyE;{@v@(kP{wQ{Ll~Xy0&y@XUjt${o!EevL6n9>&|Dc8M@++uiMl9^goyG
zJn2&p-}(FNikBW$+;i16%Vs|L`ZNBm@&{{XFMa2-ga3Z?1$*z@aN)D}yll*#`?Aw^
zUvcg5@>OTq-F@#a761MNgOiuO#$|UN?`l8&AF^%pllIw-tK8mqzfGS0mv`20{>jzl
zkN;?3SLaj5SD*UwQuEmVJl2f<_{1}sfBmjAu7CfzuiNr>=brrRqsivhcgN4V{*kLr
zTmJqlR{i?Rt2cf3iPf95zL$KBLGzM7u*D}Iu!rthTg*;foA#ExW=%MC>ELAH-LJ?B
zUwvg*kS_0Z2UtcFR(0IURjm^~{&Fc)&uB~y6-#|9M-L|tuIVNZRvYdW>%^UXQd=%O
zxle{)x656)WwdhT^?TfLyPf<0u6ooR&7^S2$-VwpZ{8bT-E7NI$D}LIIL5D9Ez4IO
zRo$JudpJwpolW+=wUQ-ETy^up#`4jn?O%;-YwR8AugqO@_T{txw0UQD_PA<i;5he-
zXT&@@ZO!B-t{L;6IB{(BQ-xK<zgV)nGW&)>+grML*NnY<TNu3jsc$6x5C2)xuiw3N
zKEWg8Z@+KTw)4;3)C=E}?yE1WPM&u1Nh0s-Yu_}rcCMBTA3UY8F0&72y_GCP|LT^j
zCjY8;ZS7<4S<to{PVS!Y&%2*5-(T&lESOz0PrSZjZhiAE^Qu*1r%rw-dDr&g<oN1E
z?wzNP-T1YaKkNFkb@t>nzp}4dSX?=<dbe9$Ebc2-uD|ojR~O5DOP{W6VDK1iU*9+2
zmake}UB@&ew&L6Zcln1aNon_Aym3?3-twoDe$i>eix+0?eRko&PfWc27tgFIxBlYH
z^61Zwn#jJoacA{)N1xoZN83-ojq&AiG3&o;%|%~7N>1rNrP^Ll8)Z_lTK90u!u5yU
z(Z!J5S{d)Vr{Y%Ka%Q`1j&cinSF{TsJ?69JoyEf|J}}X(lqL_mrR_>#$BJEM!JZ(e
zzNuj^|HJi_iHoi`i?6fhi+|ckKK07|eK)*(Qr>XlOyQb=gMDUQRvBN_uB<$jR|}R-
z^toE8Z(`dXcQG&Ho+P^~#maEfdRtYJJ;7Lim@Sn|7G7Q}A9r%6+E;mg)U<CsF+HKX
zX826MIQ5f9rF&);CxhL7hRmv5&U33PhL;bRUBd$h8XsN!^yJMild$6V+6>AQ&pN*O
zS;07U(_?3jjr`NZ<jBSuH**S~&7RVdk#cMI3V(22Vjmq|)i>x?F1Y%sk(s;aR=u%U
zT6xyp>nn@yZjQWnS@F)Z&m49`rFA2fQmc@SW`%P`x4*l2%yo(DZ`px$vNGMicjQAm
z@2`~G4_A`c-F~Ba-S&Yqw(L%?U}E`Na?ygOnYD|L>AGuQ-P*Bn#rA>YU%lloUwL`$
z#CMd3$1mQredeOpV;|XEo11-gZTO#;W)FYx>|;JuDDL^ZDOIw1Y3*ZQedB4J_bsjQ
zM)SI%10!ZxIF@<ub3N+U)B1hz|7G@adneKxx13p<x~$zEIc3J$JDC*Xx6}Ju<yL_7
ztW^32yYk5`lga9bhgWRhE$+B<UHAAOZ+8nnlr7*nezGL16_!@FnXMDt05*naj<>bs
znBkUW>$Wf0$;xY~pO6oaE-z1yma6Yt++4l+%-u=R*o2n{M$UWtMLyYDO_Nu1>od|=
zv%w7C@J_#OYJ0!Vt*wVA+rtmPVQg-8k@M3@d+>%nS$1H#+%L=5W=pfT^s>_?I<m6z
zjt=BE_xpD6yBKXJ^qZeoy_=9Zc0wx4x3G3t=4*#P?^mro?4&liOHS~9)nN0W9C(P8
z<5Mg?Kk5tSqiy?|eNGlU+?HgvY0bWgWNEEx?`loRD)0M8yH!_eI=QzzDfhmm>G~%}
z`^MT6Nw%|HsZ`QRiH=s;HCLH!KW}%rtnYevU9xMFlm5x7{6ClZO6AgZ(!PA1yQ<wz
z%agsNwvBV6wz!SlDD-*brBZQ4zWp9djjz<1&$l&dsjm=Q)g9WfyDj6pPW*FP#F$by
zF{R1W*1Tyw<YjzTM7sLTk6&@YRV_JoneRI<b*qlK!`pJZCFP1Q+`;(<TidO46Y>6T
zuYaf~W}4fj&+MifKioDS+vf__joY$sOW9AFRSjn=Ub6j@u5az6lS<18uP^tPE^ABa
zvKpWJRLkA#Ot~`TMm#F4n3}2Z?65Y{P2EE-sWobDl^IUUEQOleobYX%ZZ4*dw_r0<
zm1gGBchsEtHV<H%P21j@iA=Vav{*OvYL4@Ix~bVz&1CW%)@5y$RPBN(9u6gHDOSJv
zS;o?@Bgcpjww17b(;f1D8;O&y;Ox|((Qo1{i?Q}J>Twl&hdD-E(B*1bwinP9d1}FN
ze?Dj!KxE6!j(z>qTnClqqn4+pT(bKXU0;=lc*WOLJ~~nvNXqp|&g!d9XG2-C;uv;c
ziq#vorjsm)*o~KpGu2`{iSK=0Z!2pmH}FD5Gw~%PY0ubVI~^Rphyj@wz-Yf&Urh~*
zw5+&JjL)_VE>D>c$0T7XD1ldW2%r_<r!A2WJwY{+K<%wpf;=ftkNXB>A(cv#!KtHr
zpBWbx$d&OPIG1#&djuuP!AfvYC`-elFY?J#eD2{YHSZ?@<PU?8ap$2?$Q9;agVp;~
z&<m!Mi2aS@G=#98i^BBPt^Cc90G{%3VVMS>c@<b?%;2wo^YB{?F%R?>Q_#cjfKqwK
zjbTmt5jhI11i2nGi*7K@N<HoyYDx}i|9pT<$e0)Aghx8_c+HxUh~_<ib?k>UjZj#0
zwR$A$2I_={664g>riyzFcv?063`kL)$Rqb%_(^%}#4qVLKLh{HTJe|f`os(0KJg>F
z|K-lNH=p~?>mK>m6Q6wHm&E_^lNU69`skY;x$TnYcAfjc|M)fE^c?)u8{YBww=Vhg
zuCIUTJG-B|?+?HG+{I@+{@qI+*mdrg{_Q8%-gC(l&z*n9z2AP<1C@)vbkXK(Kk~#&
zKYaTuUpW6=5A1&OlNbNw#~(TKi66fG3om{95AJ*RpPswq%3t4h=8Hc({|mqV_KCOs
z<n<4{?aJrAbHQhRdG6<a{nGC*z2+b9+xnyDzVoM_|Mi8R+x5g3mcI1dJ;cwy>NDSd
z@}yl)e){5{Ja^yL7k~POHUI0IufKNRlMh^U&2xM|^waa#eCEkZPS9^$-uP?2`T617
zPJH3Xvrb}X)yfInaNV`zc1AMp9~vSzv0LylnUOHg7RzRbCQy&#dWw<n?6Nf<8Q>k1
zl<#|LepR3I=0@!0_*Cw)r^$+K%cXCrPwj1+q_XYwU3Y9h-giHOZQkZ(WZPmHsT2>&
zYltuPc4ao$D{m}@!W-DDx~(KDXBJ6YXuVbz3fWMo^d)lOI7ZT-4avKasT{nRUDUg|
zhwPqb{e!O(d3nXiudS7b`>brvY&d%9_{_I98rxgI{r@V_`kq%OcW-Sm$g7)#X#40!
z<A@=gfXS;Hy(38VW68;HWB#vUulA>qXLB+9e{+Hos0{xHaKDQSzZ3o4n0{Mu;6w;q
zPNci`p5R2u&XVMPth@>~;#0N-iuCZPl+YGuYF;-3;|mI1mXr@AIyUi&kWx4aJ!><#
zr8h0%_4d4SBt)r;E;FIT>+>2vkdT9ZwSovc8i7w(a)EfuP4|aq5X2&lm^Kclq&V^s
zA5T~x2q$c&l_DptRLhAp8!!@Sb-Hxy#27S$42g4cHWka_J`l?zaT~O$s?0x5_{yZL
zk2lkxdD-W-ZVN54miv0;1sDnJu+82gu4KeM4aT|@N&Cl0a<<F)G5%=Y!w{9nmC#)9
zW{2%i`*G$g{SAfS>|VN#X6+$>n`U&xR%T(at<Fz3@L7s0By4Lhl<*#yc<ODY44V~R
zKx^%1S*TV1jM<i$BVTpsX8FCNMO@3+&{DM)s8b&rPeKsOl37b5ot-5u*>goO(sIVJ
zIy)#fkR|Gte4(5Z(#l$qXpjLW8thNnt;AazQsY^rG@v1|0hj+k7=v(u?b{4Cjso?a
zGu}I&FFLpmK|4ZSLgFh;eFIR#^8<S!VS~$NheX;^ARnw7UfYj@o!VZRR3Og+j+UoD
zir8ra<6;6{5m^!2(~@aG<}9fp2xRL><r5Q?s*Br<?9DtE5b!7tC#)j~OOWm%a)m7M
z#2SZHAab&w!knq0nhfdpXv{;p|AReX9K;4Vo)s@7u8Z*E``E*y9b@)n37C1A2vPHZ
zSTa4WZYC{oK~-<qM1=4#@6?g-Rfe)0mh^O);lvk1piV3wJZ_qeAPyDuXb~tPv2!aV
z%mh2^d3zlkm%bVSw?s+AI~7ig%h-w9C^~C;>IH!UHE^VXguf%~E$?nQt(Z~-)|=}0
z|JHW*cG^T+38U5}K?i=+k1T!4#$#n^lJB$2u83z~R<eXzPykc1x9V#@U8~wu30YHV
zUgvbHeOBqFlmf14(XlwI5R<MLM5HmiWTaGBq>{(L4lYPt!4k7V)nU!j$l#mutz00I
z1KV6IFB0?*%#g?9Lqc}G*pOL%^@EqMz-!$s=M9O0X$U3mSJmd!2pAX;E*-F8h|j@T
z6fx-Ze)_z~i&sSXtTq=U3N{_mej9`Kuv%4`@cgI`JN=gQ0%~iL#>aY;H`I<zAbyLo
z4<q6|Y4pCDbCRCjQUy4F2fT@<$*5!vS;8-!#JVs}(3iC_P$OE^*KQ{WyDu<ou2V)%
z4!J=m)8CJ#=Nt-@!3wrZF-e_*`1X||+*6qKkcX2F4&*|pqd&(zL=$d#-FcO2gW6U~
zX>B<3X5MDw(S7<J=2x~!sh3)NnKW-Y77sqNi4Ev4aeQmos5tTyO`K4lK3qq`8+;F9
zaF>>ZFvrXGn=y{l4f-J6d!$qzIB2ZmrN8-JPgd<g&bQa9t?|@MpPbIGG*uN{t=!F;
zHI=z>k5~z%VOB%JYI6W9p)|L|xvXddyxomxk-?e=3iajs+8~<J_TBduf;K6`Qv6OF
z^#fx90@-mD9?Gl{hMo2g#)j7_#;K055sC$Dq9vs8XUZg=5~K9gyK+3gGl-p4{=hEL
zEJ3`;tbWc}2X8A2RT{XifM-gQdQ>Pi1eNg-*jzEioHuJ{^b#lpWw<7*a8q@?oL=~h
zBk~JgMoe%N2NTjd_**r9RwtujwPhn67zy+V9n-aL@=-h(9*9fy#f-N4)G`X<Ez2t=
zcMjkT8t^KdHDVl7f>qu$IMq{0Ox73RPft`lKL^oNH^f*fTeX((41tjaMpIPCqxvba
zv!II{+Tc_v7-R{%XB>y8-Z9uJj$}F#Qx2GM=5KvRw}UK!RfGcT+2dmSZd^u$nX%=-
z)|3ql+R`g7(E-D`;62|9c)r`XSt?UsxBj*LKJyM?EMt!`p5ew88sj0%hElJOao9PR
z3>)?kQa9pl(_>;Q_!*~yOZhU+(zSMsP4Uffpcc~Cel$?cDisNczhaPQ2$M+7Eq69P
z9;h4x9xZ+tt|D!m<-U$-Fy5O!UlWVft!2=gi6^Z$U?@9-zG`l4U)c;%LU+0f>mff}
zuMJTG3j#snugf-ZuXCwBI1E@)A>nWcixxTZ1A;J=w9QD`<%J6q7VEs?Ws{Y|Mlkxk
zT~x_x$Id9qJG+2<gxZXxA<(uQ<X*keSH;f?H_@aGSLH!T9A7<6d{i8Ww2Hp7(AA+G
zm>89xp&ejfi=W~hmmw+-mDn#%@nQt_!bOey7tisXh@PZ8JfeL3#!j|?3>a3|nD`RJ
z2!!N3Eimq%#%1+=GQ&njLpp}V-rRun2C{<7lE6c*#LqZeV}|hKNrP4m2h9Q5oARvn
z>pT$b&!`T@cY~SnnM}BX*f-v7`fg8*jst^%wL$x7B(uY%ESbh;WN&q9Cw9QkDJ`L)
z14?OT<vk+xbP6e^6OodsYabdy7U`0{q;DkK5TqFf2hHw5yKY*NuE?tFCLYuzD4%0*
zg~qevL%iXMgiDgL%t-p-v{+UJ4VUYM()iN@#`5sbqEk2697=fStezQvCG`#5r}2q;
zyMm%mhmRbUJc{C6c9yK~sH*mfKg?n~;ecxAOjg(+#brhJJcYKI5$HQZ8H0vd%FTK}
z=EexCl(cRu+Fb8V(+jYRp`%@~>b1|vXaT9ZEL)Bq5bqb3L+D69Z{lpH%VKQu8AKRP
z7!`f8gSpw%y4Edji(L35s!5Wh`aJdqVdj>w(M1LY>ffen948q>?$8i52MJ4FKoF3W
zrRXFsIGH=J5z+$!F;vQ}gyFP~x2~;WDMs^=Io%JM>7Q&UE{UfdLl5J>93VYOsQX~k
zRk3x@^dO2QH)YK-L{2-edBg-QN9u=#{vdrMgQN$DZ`KHB<^)O(jB|{qHZD+gOq8BO
z!a`AoQKNO5ODb9`0D9x`wY&&O2T$_LPB<@>A~8h`1xmpNy;n_Olz?N84-RE1IE|`k
zo<E)4t&Wfi89QS8tPY&hG4581i2*Xk?uu{hC@&<DPYTl0vI&hIA;Nb7xf7I2`R6^5
zCm^pK^?6t&R?xQ10ef;XQw%n}m9I^a*EtVk@!C{AR$sSntT>-&4y`>eAt)PX0?%#5
zL9O5iQ1c|?DK~$CJ3FQI-gsSuXr7jq{RV=_<In~PF{}>3s)M7}M@v_Tb8;Tk(f~8>
zOC4o92gV0V2?%C1u3znVu<U|jOaZ1@%rS^f^ob)yky)caw!9vZ3FT^%I5L<z0a_k$
z156u=XU5X+T*PwM<NDzklA0FcUnXAJM9?-mo6;TQJALK|8fqEPDrqaD8%ZQc$&<ZB
z7^W0k$DwGZG#r+`xG>Uo9&clQT8EG^riV&Q(Y71jq(S<lx&_Gje#|40guohxLKJ8Y
z>ZzOoOE{JiFm$IFk(nCI^A~R@FQOb$<hi4Uax%TYiy?TBNO(R962;?2peP*)y!1H<
z+AlC=EpkMx-nT>;*Ol}<sALI-rM_Oo=6%u6%dtAqf?C?N8g6jK0G{JQ;)*9LBI&Qi
z!3p){N#HORGUW{sHNwj*B3;Qr1?3;ZX1E)Yo?=m!dR`sm@s2HN4dbvL0UuOKr$muZ
zoj{oKvs(=AZ=|ytmL5W|#Y295+1M%SQ(ev$i<Cs>RZ`J}Sjx~6W$C6V{uC8~+(6r9
zJ7sph%yvY1uj8lc$n{Z0hh=6_IHgma3UtcLyTm~zuAG~yb3)!JJgP1ULM>o58dys~
z&$2J(8kDMj=#0#C1e6a4y)_G@>ixaPXCT7Sp(<Jn<FEb!p^P&{`Vku=x{r&QLkrDo
zL^BhvBjq$Jk!lxvhF!FaY5o2L!%eg-PrGP2L32`u*Pl(%yfF9h@|wzo?0B6f*OqhK
z$)OF?&CSYjZzANDz@@BUticGB5rHp=<ju+m=rW`-VP>^dORXt=>T*J(Ii1b>Tvm{`
zU#A(S%5%8fDZ|}c?l%I_*v?272m)#$3L{B~J}C`Vmm@~YMVwe4`n^*W^>W%wG-L=w
z)xev=iLst0aUi_@W4Ay;h_;~RC?5zKsH#Az%B7HUiXGXU?z!Px-fvQXsYU@mU-zbo
zs&@wzNgB~8`#AF}+_!7gOnLo%LkcuiN@BT0(F!b&ai+bFR{XaWhqY+!w$W0`3rXWl
z&6Ghj-ed6UkJyBMrs-M*)2}c5=5k3v>%lw(o`AK)72%o5J64V%pT-UD{Fq|uP?$hT
z3Q0jmLx7$O6l6Il3k^ASerr5(s!SNh-N8KVWV|n7jybXQ8tQSmyw;x5tng}=W<)D8
zqp~{dWQw>+)ORW}`mg~{OsoM&=!DT)-CPhKk{FrSr(!D|Fag7l#8PndRXqg-CK8F`
zPZAN~JUHkT<%jBdy5>(DTJ{8V?W=&!6R1+!VQ@kb{LXC5S5pnbK!?kUlU15F$CdFC
zxDOi3K}Yq#$dJZdutFl0M)SGg^br{_O*vIWjN>1LlI~f2M^RK6x+&}9JziWMc^4m1
zC}9)MWhmIUYQ&6$Elh2a>tKkCjs#Y(q?mZk;O-V=Q9x4_M2Y&zbp8QDk=%#G-wS!>
zdThn>uyG{kmk;SNZ$KpG8c86{H!<l}UWEsO6sQmdYms6SD@hwU`U15E9bA;hbv0GN
zs}t1G^t>j4yt)>K7@ryej`j(8x@WXaoG3Vp6VqcfrYlN8f0z~fXT3xO6NyNS(h*27
z5U&dz7l`E?AkeH{ogCI#8l8W@a}A<Q1y@4=_>;g1+90&g$FYJfo=9z?GE(E{v_MlG
z3DD)ePgC{sAy!lq^>ifFsnc+(T$kX_Xu&~IoRW?cbUaUDT+u`|+}8UL8Hbi=@Hr3f
zHEBxJdvvLW6@q4?(IO8=Ft)Y&3LZ@a3^t&N8nRerb)^0vDP<-qYf8I5ajFi&#1gGW
zqvUR0q1?78(UM#su(T=SNtmx@u5Ty+9~Gh`>8!>v8zo0hRhfgcQ8Zn8D2ZG_MbHxF
zjm@$h0weM$L{C!_>8gwh^GRwF`7902fmD1jGO0dshZljqq&Fjxf1e-mIo8GQ0&T1^
z)Vk&gr0MKJL9o{1@>EYq6Qcl5rvVyLk%602JRb|kBhn5Lr45j;FksPyCW6YA(}Kk;
zxd+V?h|Gs{41W6u6>GQ#W~71dNX0-Lst6-An=3g*!i4<<f?hW;uslG&E!0+z`*0fd
z%BU_u`eGRlVW?_ewcwjE?4eRXhLEQ;VGroa1s)N)xu@<FEGa!Wjfi$609S{pz<=U&
z00iLP)-BJHiVo-)*`mv-Oc7`sV0u16dNAc!ATw*8MFpIvHZw8+e;;CD2te6t+WDxg
zZsNd+pH_owQEPy7-cshx7VrVt6gSN>DdEKg<?Ullp~7!Tn|l{eI0CmBWZ+ld0IReL
ziPkdcej=V$F9#?c@hIuMxU-)+Byxx`m^==*&{5KHv0h_Qx!P{ZXns!j<J2{FMF+kZ
zj~P;1Q<8+gC<c*oEWuMAgErL&?D$2o&|j{#l%z=H@N$$DkHsk?2@Fi4+jMz~_t8c<
zc`D9@u>&|%4H`I49W!5j$7HIxC^pKYNr~KO*pI0<pov2YBTHTBTU<`>=-5gp2vA?%
zL`Q(Q_TnLAC2~fva!luW4?UgLeLY60llLqF^724MDU4>%0aji^K_`e9(i=o7AItNU
zj26ijlt{sGsf;>VY8VFUGsgtA^;mWE3pOStq#Nn5r2W*LiqodhEck&^8x)+d{yhZ3
z%NE?2&57+ff;HBD+7|=iHo>C2sz;EuQ!$8lUZrk$aw1MlfQAA9o~aQGMyn4b8s<DW
zs!!bKwR4(cMDs*6)%K1EwS%+5sAIo_bZxB6i*3RO@a@RJNj*lz=J`lKCM}B+6#Bdq
z=VGh?Q@~LfmCtw_5;09d0>)zF_4M5+DFpqFpljgJweuURjMWYUmu92?$9B|^=C?7R
z=BZN3A{TkOz^Z|&YI(n@a9rLfB0^oIaw=nz-;wBiL%24tMLtJx6b}xYbwUBk41rbV
zO5V{Cg@;E9KDJ|LA5xHq?-)dwbII3?89d>r1$G{F$~4NvA)c=L^Yt(+fVh&-EIyW(
zsCEoC90)Ot7^g%DqG%j6aUcJaj5Rzw_43r|h^eUnB7rL}vz?E3+>$8h6yhlhFDJr7
zP^ZyZb+zWnh!5IWPOIwpi_{uaaI!NOokHT>Tbe)Lb8+Fobk04qi#ePs(~F^4b*M{2
z88GnLxIUQzA7MQA0&#L^Pk~DJWo1MeOd%3HEDAg_5l6*QJ|qy=gWhF0A_MV!YOgX#
zmpH}ds&s=xA4Nx=z6-B7N_bVSN)X%+Ux6n<+a}bQu^Kn{JJWVPitBeG&EL;tzt|9r
zy<wEC{)RO8>?BEKaE-6_HFU~I=UU~d-XMpux+U&*Q%9iDM83?=&A9cx>TM$wTzYuW
ziS#zQFkIpJ($wbL>(pv4tlpKCw(tlmd31G(s<fx`i43#OY^XHtk|EghZ%*bAzA{#y
zR9IKqxwG8r-pPZeLd~l(&KPC-T0*hOaFQl#rF_#=d2poQo$TkCIs%%JMKZ!XHdAx8
zgoUX|oKzP$)-r>>omQ%-<7wIDc)w(U>-+pF6p~i!f9=q*<w>9~o1HQ|{fly7h%P<E
z=dy#RZZuz`L-M{x<1%*Kk&p3OjzP;dxs~^83buWKxvJFfhrcoH)P(u{ANK2mG@Nxq
zjhoG6-$Kv$t7CS#|9+9Kdry0ChK;vlr1TGg!^ua|>@(Vm!N>*r>^CH}Gikp@?=Nc1
z4z~Uvoj7~X(V4w*aIjq->ouyQYiLKiQ(CiOpuZi&-CCM4_vcRoGi}ShH)85ko-;3|
zW@Lm{bA+wY%1kw-FD6F~W(W6FWb06Gt}K{UtvY;@_<#trb;C|WMdd|z&Zc*;mnxO*
zStCh%|C_zH50k5^5`Nb?b*lPwr4mjzozMwk+*PTBA|Fr*Ek=zqyE{d!gs4pj5<b)l
zWUx^NQ5a-K)ZLvT6d{g92pAEyKt2KjMg&AbZ819NFq%O|ctHilSD7oKuPCCT+~3-#
zIwYg_eeV0`eV)6z&pCUqz4lsbul;%U$El!`ZH*O&vDu3Dq|~eAr3vTRW)Llp*Z=_^
zPF!_1IbQ1cHfbTr2eK<ZL>Q%&oXwbePUOkXk(hzHIc%0##?TKWh0~38tfpw>;*yL8
zpP|LIWvn}`Dn)Yj@P=&Ua{=V|D051&fjX}(f7mNg@61YRVS{g~<z@c4w9R3rl9Wr*
zb2UBOxs^DYlj*Ev8AM7l*ta|G@HLuhTx+l>9c^L-Hk4^WIrvp0u}oqVGd9j$Y%O_Y
zf-MXJ8&UO=t;{#^3K+5&MSZZ*NErU)U_*@=sZqg<Ohoc^7d}AS61gCnXl^d^5@ko5
zE<9~@P~l^_=7Py^RML6;&~>!)3&bvKEoFUxE~rP`wdV9#E{#qbXqJVKvc*3N!_k2P
zzro^+TQGmMo(Vbl8j+nr-$-l0{P$n8VCW6!*AGn^tIsP;UUmJFhi6^CWN70wesbZ|
z*$-Ut*(H0oT)Sk&SwUDiYg*oh^A?XzEL*%{Q!uUa554)(hx!-Swr?-rdfUnTo=)$y
z(Qi%6u;2YiVb}a4rrk6D)rXG0etWKV>h|2N*Z+R_(Ob`2eSYS#T%-4)8Lc~yIBVzi
zuO2>k{OWw;(#OL34R@6vy>ot0E%G})*+cu|yL08M?`|%>uz1-il_M_ew_Er<q1;uA
z?^_a_Qkj40y8E|JM0>Y4=PzDz>B`0bbK1(0?bnsxynS=|_W4JI%jYlZ8QuPga<qL*
zS^nXIwVK|O%9Q=>SC?OW`=6(;KYK~x?4K6aF8+tN*RL6R#hMGB`b>T8H$F6W-`l_Q
zhFw3q_n@7hy7utvKXv_4*Ub9zf(>sk{mVT!9^JFz#zRUM{p{06egBu!k`LT=&Y}-|
z`PoH<Gw0p7Gxu!c>EC^7$qPTbsWAA+w93OzedqLhe)jW`3(xpvxZ@kop1%7d53M}=
zzDqYgbN%n9zxdR@E%?LcL*nI^yp&u1?;k96F8TAyr+a?zfyxyhUUuQnKAimFrjIPV
z=Z=Hsja@Rk`tDy$OMW!}E&qJMC&w54`Mk^Ix)Uy4*O_<Fp?`bc?S~)vk?W2==eM_<
z@ce5xAOFxphaXw{+~;4p;*X!7`M2-;%-ikF0~<8GuYW=0ho3z>fBlo0?29)R2JG6x
zz^12VL+h&BXPh5pqdV<Ug`ubO(=WW?hJ)IlZuacB+4Wp==d?BU@Sa@t#-6ZRo)_Nv
zvyUG&`bbajhI_Uys@)tfiViR5+V_8}KKi5a!qcC-c1ioDSM=`v+GVRYy!+Ymov%8j
z+&=wV_4ejHXDl!O<PG;M-j;oI{FAv~pVuyp{rd~%!i&Ez?K|BWZq-``WaFXLc>6*9
zKYsT>XwJASyzuWYOU`XhB)_ViIB>zqo8`KocVvRo=W_0cb7pCrJMzx!GRv;KW#yS~
z3wpmjJ}*~&&t2K`ulh=M;O1@A{&&vQb1#3I6nX5SOs;xs=J*vehTjlxK5qK9`D@-X
z^wXKW<=icc7k}sM!lOUyo!MS{bFP)U`Je}WTsY{WpY-%xSeib4dAPXu!h<H3ym<JH
zg%=M0X?RcbLkF$6B(r4w*K_lC{_B-9c3yJxn<|TY-*{nR)q=VI`s1*^`D>hxS-s%C
zGnbTh4j<dIYkcjQV>hl_aN3z~UN|Rw&72MSAI4*czfh_l{_%O{KSt(OzIw&n#!o-l
z-`G4Wd12+HJ-bIf9-6OyoL?+?a3H^OB0G20B@5pAvqEmetESC7?SxKd`8s~&WO~pu
zbeLo`Z4Z8q_I>kJ<>#-M$R;hzp`CZkw3oehI@?I5@BV77u$Pk#)xr_8<9u+K+tcc~
zs4UsjN^ww;t=X!PC5;<zoNl*mF1Rh*a_!<}hbPDO%pbZqSVFroedox<XVwd|-d<TO
z)7ab4<1Sfct}kthI?HB9JLS^T?_sVxK0mi+*WEVvz_s5nF0|o=<vlXC;M)1SC74%D
zW-V*<B}u&Q>i$+`R{vn;5KeR+QZ@IF3@n%Rv-nVN^v^@nhED%+OJ{XgotBsd{SQhw
z=ij9#4kw0RV2=Ev``d-FZ;ba=_)73aqlI_Q{ci3~p>KJ{h&;VEn3;T?uI7#z*EZ(l
zj=1l`1+)I^^^r$A2YotPI5Yd?4do5HKYnE4{GYGc_VE30tt4-|?BolFOO^g(R>n^@
zk6pfVm5DFB_&T->me^`>$H~9`_G`n&Z;r5oKMU)fVN?F;#HYjB_~F?FZeC`aEX>dS
z@oSITHoVAg>seGO?^$R!HID3g<JWGTHtX7J7cFRAFk{=Xf2x(A`d#+S&u<yNVCdWP
zt~qaO?w^m3<H|gaRt8^*Ui{jc8UMU=>zU8??Tj9tcUAb}dswRYkMYsYvdzgeVg7bm
zDwWz&9r4OcO<z(T%}y@pi{jB(c8<ok?Aa`1+vW)$vN?=K{*YI;j~8j&92U;LG+Erd
z3~I(TBd_e)uts|3x+;?tCze;4|BTjdm~59vTk%<wGY?r~n*;U6#lcvTE#}X^e6gIF
zWRA^AwWrA-ur%JYChEK*PWI$w*TuU^CDU3|Hl1k|`Tn&2PB^V!K32ZUJk;~8Xfktp
zH9lys;Q;fpFrJ$nR!9auYR*ljopZkZD(@1}CRe?B!ScP7&64ZCm4mdd9nYA{xS<u%
z$-03{Pn#4mSIg`M3mIcBU#N`7A8L-o^Bsc#>()mV*U!EKo2~KDh0!)YJiRx$xEhtK
zji|}C8MAy>UW$g}wsfh9jTQ{Xxx<HytQd|nW#)p*aU<YMC2kgbHRi8j>=j8Z%GYGm
zvCVLPtu8%l?F2_|?U}uWk)EDy!Tdf(hc&xuU3vZR$ow#{({ra6j|k7`X~b`rvI#1s
zO?G)HS{*Kk!_AF27&q?tjLf}OE||M9Se45J<=hE2(lb53rgYx9a^md^Hcxzy&bMmY
zvX#Aq1@d%lb1#dqlOsBmdM4?}qxwR^;3SxoxZ(PFGqcgPZT!21(`GLG$zU8VmBNiP
zSwMcjmGHzWud_kIlw#66n-M^SIEE#Wjiabc3hii^VLTCxFghGg#zRxE*+M=H>T-Pa
z4vtfgF~kV4n00nlQ^s<e;s)Q@t=b|30|p6lc)Ye}B(#CSU6fjXz@j_D76xTH^ccyE
za1N#>ld{S2l3KA+c8n9k(Refvq>sp^T3~tIVW>pb>X{#1$2#A#cUb~6#tYF56Ea|q
z_-^$IM3f+l>@My@jem*QWu*JRC25G%B^&`QW7q<HWo?ki+)9WNVMX6H*q1(m?buNl
z$Y|6L|L|bl>oz7CnJuA4T?K7U6=5_3<27g`VKo}a?P7gl2;-g3+>YtLG8u4^U&ea@
zsg%ixEiSH^UufddwQihNM%O1oDKT_Dhy6FlzM2d$%<ee}mLUshayfPAnV$}{-lNte
z4?wF|FF=hL%99crpLIrQ0IMsJLWsUGV)DRAg5MF6QmD^xkw8G-JKO1uqE)|GMH?cR
zLV@^9e<Lb1E|vx^*eV#VbhTA|zd{EmVNtT`n*zq(&@uj3Fj(GrVX6MqB~3vQB}`&9
zTsiyraaRU@KwlYEqc}UE(yjR7pzq_trK=W!lHns7Wfqk6{_c%VTjt7yv?OCZ%EwfW
zo`*7lKku6|&P8kmy&GPjQcx1+y~v-y8463oN3v<4IKK^=VithV{K^&K=nL21oT@Yi
z{=r}kfg5iB!JF>*@_9GQ-q-juKlR&xd(IcX{Jz`neqzy;7k%fh3pRY^A3w1DlYhMJ
z?%&~m;;wa%-G1Ux+duK9U)=Y|y;uJEm$#kp_%Gjk<QK1b(+$_3blVRu`sL?Odg-S3
z9<}|6x888kBe(tV{YQQ2)W<*b#JzVv@va-nPkiaLZ+_*sk3D|-6F2|)KmYvsXP&ri
z{mEbc_?kPu^1GW~dgS)IhK~Ewn^%A3w`+d=o5yed^CMrp@=uT7aKXvX{^_{K9(nwz
zyZ`aihy3Z6x2-$*m)}3<>PNoyu1)80=I32^t$WMQAAZO7NB(Vo`7JlU?H}Ixm35E*
z^5KP#J@KuZZas<L82UM9et!AAg=zpj1M_tf`_j*zUldQ;NSb{?(u@L`v{`ws!JOQ%
z$Yle(ml+IZ6TiWHVyR9lQI(^deu&t}t{@pH2689gF$l9c2`^^txEaXdguf%3mv<~?
zr%zMj67x1s4rk>0ud`d5T?C72w2)aNKWd^$A!zKO319VfBVjX?>vk}MX~a#MUblCT
z#9wWO(aOznVI5^*<e`%N+CwE-NlmDu$8Z?RN*A_z#zT{JV$LOF?IfSraC}u2MXeJ@
zIu$g%SL?il^~EJp-2X9{Zj3>}CR4DVQ&FD1zfBSNr<UXcU_TOfK){sezww<y?|VA7
zGEaHBv|dOgjVNEyvjrd15mOg*CP{*F#Kv|%XVaz%xQbyf9t8GilS~AB+b*Or6l?pH
zaZqJvZ{%=w^4MBpHlPQSW+MnO<dx8-i&RQHB_KbUO%7?OW7)JjjLh7QH*v)Kz3kLl
z21K+p@pV#`<)K-wENkV^l?VuOmIHaQty61ntc=7i8mn$H^drMrWV3588^mTBgf=8p
zS<!QbtSJlaCQDi(rziK*giqHQuXbV3GQ}5;*EJ^Xtn8%;4ucX(IFqX4%B*#<-J988
zc)VE?GU2(#`u?rwmekka)gNnd6(gsc?<R4w^Lke7=Gl$tx^oyVy6TgJ+exmOh-tsD
z#|UxK<ZJX&fr1JmSqBOIdoJv-Zxf7ZW~^Aua%G%jP1G`tl9cxL`!hWs{sU9FgeEba
zU=cQk{;{8%>usQg43d%*;tuh=G=VRTbVCT56yhP=InAcPHi&5hjp1)7f(-)-LCAz-
z#p)85U~zF1T5H&eW+63PWRBh$Re|Md!p~r5Cb1M>RUFw$XUs>MMYFpu9rovzX@vu%
zSi-9-{p_c9AaucFqKX*9j9kz_KAs3v8*R0hgQ4<7XKq$%q%{aks&~NeX22qFzQ5Wa
ziiUWy4k=saaB4s33=AQwDprB5J{6K*a|3>zceF(?-^xO01O}ksZ_yZfIaP;eOB`Kv
z%PKM=b9Ch=^fX|s=RHa0d1`dsN*QDF4+DhxGgXfu3i*DnftV}OpVmX7Kl9@_&6f0b
z2mvf=borW$=9{>31zL)*u|>nTjvZ$4hDHg)S_xbrD(M|7Vo;)Mgasxt23Hh0NWdY|
zq{QlyGI?c~k!C?oq{Cv313L&|GD$3kSQKPqEJW0I*n~QjSuc|&W~P*%VKaf)O0GqP
zvy=!`tD+%HgSG-wM@FPWbNm2%8OP&N|0;ENWFhgjWN8g`I!3|oK&ACjiwX0xR?475
zE3`#8wxIzJ@=8l`uc4TEuUu^r1)!iaT9RToOLkUO7W#6cgB9wes)DNYW!S=E7p)Q=
ztF~dSN@)T|)zXxN(r=+!5HRm8s1V7(4%#&Rc_7*t1w9k;jIJprMKXt!j0REJl>$tJ
z?omKq>PjIzHB*pn5j~+P#<bj6ix9hKK<5~FxuE?jjRaAXKnVhdX@k^u24gTLGj(t+
zBPgY(7kVWtF5!0`XeC&1)XEDB+~k^8Z}kifYBuKh_%PKBi}Z!G#~8vOxZdnBR7>8-
zlSoFjEy+VmV-w`EM74;)8~|?~mWRq_<(Mkymq9@lDM|4<C*r6{=qXg*q%usBXqJbd
z9CS2vhDKaXWyioo)2X<!wI<P!wJg^!i#@Ykf5t`wngJYrU`a+x`e<N4pc{5tlM{Q=
zY|<@JqX>eGF(1;08v;k`E8#Zy)yiP7wst=nj{|#AV>a~_*4mhLOA7k>EoBgqMvVF>
zX444VO1=`OstANWf1j-rAJAlAmWr*UKKA~WF{ap1V`Dq;lPF{(L)1hq&U%2-0$~u?
z-~kbfdo~m8WMSI~^YrjV4F$smqd<tQyFM)bf(Zs1%H6{#FMY(RjFufmx2m`a>@KdN
zWB+DJO94d@3npP8HRT3da-4bhm<0*YASTu5qjdree=r0bqT_DuxL=gZJg8l0a4FaT
ziP|ulIBI(x*_aH@sg?<aI1uB65PS{fy4c~2u&|*_(r2QkDXV}aw4K1LLPRHFvB?Et
z+xIl^CW_;OWO>=fl4MPz<f%6iWr^Hli3ChsPwP>G_L;Isks=abybQ?%Z%Mq=k6s?E
z87AQ|RA1RG8BU>49wc%MD#CG*G033z`TLtYNnf9lxXSGO{Uo`_Yp^3fZC2Z#h&)b>
zgeAdCZX`<hEm|$sQB=&u(f#O!Lg$Cy;wXZZcs2E8d9QXm!9X1rh76#b8W1)5G~Uu-
zn$YsZxk_;<rEP)`ekX)`Mfd5~N2#zhh}D6ai4$q%+ppndN2y5~<09$gs}|KYBtmLE
zyz3e(RsBw+lICof<R&TvjgFA#6)9QNq;pYoxeQvM_6T;gCX0LtZJT^SHiagM{!!$X
zw52n(2uin|jYgKDMahxx2X53vEqx8HlTX-{54+H^3<lvrna~&_6#An)Z*0;DG9}wP
z=qPy2tr2IGFw{s8T9-tw$SQEs3L_U)cFdj}h{JgLxg@-UYB5r`466+=xi+>Z+VEUy
z$~G*?j^MQIlYFoz(JnpAkqbd-lY|fGzy$HjrJUP>Y7t{T{m_NNF;3(>vc>l2kFAik
zwXxSn4`hlGFRU}la5>&AqMepP)`(fvWAUS7^tS=yP9~;B8VT#6j7{?WkufPp7jCB2
z9i5By`Z)ZPS<JTLupJ-7k(Uv<+~nD*X2OU2K7y@BRh?X=N&hux9L=%xZjovnN!=zv
zOD3XCGqFR!v_ffauq!tZP0p<_err*2gYtwh99&vtZ6{-BxXC{<$8t)RRNDE;(7GCH
zQG6LtYxCS7SYY`9;-o`+Gme?+IV0~566X@B36+wgIxJ;Icf?OJVa4dzIDUM{hHGSG
z@qo6j^+B|X27W?qX;>%BMHv&v83rlI;8;LC;LKSZ<?Z<-!qg;xIYK9Vzigt_DA##q
zxRA5CVVUl#4|#l;uNAPs&UX(VC|{}bIFX~zncFwFw9Zjx*kwM4JPFAgL&1EYhz?zt
z(crh}S7Im3rQm2*On6=DvHsydFhOCp#AhodUz(tph!bvfMxKPdd98FTEq?4nuWyKf
zt-Vl)A7%ZnD*_#8SqPx?!Gn5{@`yV0qjs1kN1^E35=tWEkik)BF0n7RVta$KCNlLU
ziP@XNuYlpPfo#gka;iP$0WbD#8SunbTG}p3V?bfWZ4?1)<T8<1t8W50wT4oM)C~mc
zHqPL*ypqGGQqZ0kht^N(5Ves98~_J8F^2w|3up-X+km`PA34%j;*q3dT{!xv8Uzrs
zwcGnU#Ol8|4TxyN^*&`i@p{(rYTmt}rZjCdph4?MJc&==7kSV_*ZqSV{Z;{gFa4gu
zOMV}rckK-$^wQ|ch#cWAS?1&C<)z-Hl#*@$nFZ`Axk==zCeglAOtg<$LgZ4_m<S_-
zPPHFWHBo~He(s?kGYA{)ogp=&h+?U>bh<X#0Hltp=+te($Z4^lc+(}tTYITvsa&JM
zguqW>gey#~*rvRYC44Ui-IH*gG()S30{U8{Dj3>hN*5*EDmp@BYK`vjwxo=!K1eK?
z;Hiv%=itYG5c#x*313{I&tkMy_PM6IIN7cNMnBBD4xaiFP5D-f5H{!{bzlMi;Ktkl
z2^u8BRkNCMYI`(=ypN7M&0DLEVXbsT3=D*n(Ud8gdS*-sBA$f8XMs$_A)M$VBBTN#
zawjV|0<qRIyvTO+1<@l^ZJ=uZgFAEz4ucb`Vx=;PR}G}#u{>k7fpT^a@KjPuOr^@>
zHA<bDwrtQrxPieE=mxauhf$yATq7yQXlqKdMt7}V0RC;Kq~s**J;G~eaBGFrr5J#@
zD_+3W#c0Jp)IfA;fP<n&YlV}b*ult3nA*#t4R}b9#5)C`>i0<&Wuu(>t11~5VK!AE
zLn?!ih`n^NM58)3l`nrj{_*_ss>X{nZLz^+Z|~4|evkAS3Fwk&tazlLWgbwAB4|<t
zDMmTPSthrM4J+FZ-nVE}W=%LR&K9Ab9Q6%FOdO4mDnUvV0=g{kNa#*l-g2f+N7Qzy
zaPAYD6^H^uWhnXT!z&{Q8yiQ>up7Mzsq?g)F|R=VsAhR(9#zg}nW`!6K-+F|T+u0S
zkB7hn{S#rVjKnA@c%D(ssP3@zS~(u%ke;k3CE9`TZXJ=rg^H(<BIS(L)STMz>m-t5
zwcJ|>Xb_Z}(L?nfcIe&c<+vfPYlmzoMPhofso@+ON{|URPY(}ONg_rOMjaYvFuOw|
zhfniy%})_|eS~iqCMKv^gF6L7;c4!{9T4C0XC$m?$7eMhDL}<=Q%y~thvIbX$la-?
zY1;?)3MlmjJp71J{UkZ7Pp3D=X7qvTNW`R#z$pAk0daV@Az%PToTF17N~pP<I#U~{
zM_UAa@U;etfKm<XFU@#6K;GRkP3}4+gN@SHxzg0=Bja%pU?{JT1{$X<Ot;O%2~=%L
z85xI<LX+1hsm+Ca*Phmc<L+dqKP#Z^tg^D=qC5?!)<v{3s)sS$C>zWfYU;GQW|UUn
zGptG=<spo<p-^{)heb$g<uomPpxc3VmYZ)Qpk#-a+<gcB*fH}mNF9lcPAy1aQogD!
zp!#};dWe_ig6gVQ%72jbxzHngzf{L*n0Y6nCP4wsx&Xsb)jJK0JtGxjxGWdoS*guR
z4y{#regzqPZa8HaF~^G+`Xt!}xlel^(JVNPEHtoz%D`g~rd_`ANkQs_+9+>v$)toG
ztNo)Ykb+m(Xp@&k=QidMv6Z4W_6qcMw4=kgjARq?%MleR;Q(<aEcg+fDDA_c;J9d6
zh==C6J?LZ<<8}0^5!XvhJzfp<(-Qe5I_yfEk^4b;?3DE>(lv>kw&Q^2<zu7j(&int
zySKP%*dLw>ivy$hRDvh*y@G0JBTGnNX!TW9$9E@~0|Bs*6`Dz35@;6FjlVom%ByYI
zOTZE`4`r+m8MWx{)TLcjV4`7lla(}mMgo(TOQR^-9lCy$4vXp$8hEB1y;xmYZG*()
zR1L2fBE3_+l6T`G4PsGzHB>tpm{ESoAD>FX_CYtEd6|Jvj)oiZP0^Z>!ou!6t5`gd
zXJDDi(n(6ESjr^t)b!}%o>5n|fDmslm>6QhQDb{x>CqKY%6k+CWABMP1#)$&7Kn=4
zPUn1H{%)^gc)#s}Z{0jqs1qIgK`N!2x~QUR1Sx-yGbt(V&~bA{$BkMxeYGR<0nEe^
zlBdO@0WvsI)>N!_5LamLa9a|P=Aq^%9ID*JlA3gE5R0ycJO69hp1<+QO{%=AStUii
z3dOf;29Ke{@N`_tM<Knd3vqx`xjsp*o4HD%2%{vv$3Plw0PpIGpJG6C2UQB#(YH^8
zXHg>sEj|EsnK2JDQ;G9_>OSQ{bA;ri0*X2UVX)w{Q}uFOUJDkDCJj!I2<E@5x8cLO
zXDEVzVQtEtlvO*c6k@dA`XpPA(Z)0|-T3|y91No%A}$cq-k8{Qgl})*b&OTI<Di!M
zRnLT}TI-GL{c0bS-)HJN<rlx#&v-m{wFs4G7K2h%KW!Dn2NQdMcNX8L`nqRna5j!Y
zZi&qZ0%ptt0LI{CAn3{(GdD_1qtdD1R%ky}kGy~9O2le=9XXAxlB?XiW!9z`xVy+T
ziHE&3A6VSwIWxA#DbqAPw2vd6g;NZ&QHT6B8tR)B(ZLnn9Z|-84nU>@6(BA|ys+VB
zbfbRlEsSSfRNqwb^z0R(eG%otlB$LTY;a{0S(KH~>TDL_COr!>cL8o?>Y~v4F2HpW
zDkv|$ll1K%MA`shSuCo|)%NPA>Ul7xs$BPJ;PcEXX+XHqL1Gt-(vh%9uRmcBC{33U
zF2X~#i)xnVjdr;@Vd0I@<)|nH9fXVWCTYg-1pM-wO}To+gy+c(gD6uEY<f312=lVl
ztzfh>Y<XuX)yW3<Qti~$g;p|!*0D5DkwC0E;1TT5#!-c({ikQ^@H-7wGF5_X!v)|m
znhKvc9^pLZWs`Vbgp4R*3fHOx=g)%NQy1wdRwMXQs~!(F6&d)&qN!Cr>uW9&LuF@3
z2oVi?%FsmL8zku0ai=;lEn(KF(y<ibnPm9>v6E;geJ8E7nu=xsYE6>NPm`8}mWIbD
zhPgn|lb-tkrnVcF5)<D*1_9DUYj1|9rX>a15iMqFJ?rlValQ@ag#;9&Btg4V%BrfN
z)YRn25ueoHA>4y!<6SM8<XQ1<avUbzF>T;K|728otI@hqanpXKeysxPwCB<~bi*Bf
z)nrCnlj_vtLFrP6(ln7jlc;4a*eZXZWq?T=Zwq?aK|QYBHJ9(Wss;+5&yQ@w(Uqq-
zuY~D3hP4xP`opU}K-s2RrZ44cT%$N{X&4^Bn$eUGvw0D(W8y4qdB$Das47M&9c>PH
zLiO7mR+*%^;FaYd3Ybtdwp0hCAdYz2j*XIHU)4N)8U3MQ9V_LkaZXoO@Pa$M+G3nl
zKa>i(>!QSyVZW{jb+HyE^c}v08be_NtjbjItxZVr4p<RH7L8YE!P}6Vf<6%i69wmQ
z`1v0}eKRFQY>pgBG(X(3)NamoYiX&iY{)jfW}p?x*RL@cxUqYIuXsf$q&$t#plG%X
zAYadcl>ZYCGU6tSf^rl?Pqpa+MK<au5}jgUzDD0(l#G5WONvQ(7mYf*)A*q2gxL@b
zlx1(PEZ)mIOORwnS!9hj65Gu6MYNWea$MyN{e03%Vg?5Lvn?5yZLL;iltayh;c%&u
z@ubymBk7dBday2Zlf-Z8%wwAgZgzPz;<%;r_>8VccSXyuACALob{77|P&ccr8pNZR
z-c%MY8<isE%$RU%bc#XRxD7VYuP+EF=be1mZ{`F;?Y_Q{DZjAV!sY=Z#Wr-I>}pFt
z#><*82xr*Vz*@=YX9&Mpuy99}K6jw9)0KQ<(WwP|T@3|w>0wmr!=u%lnMlGhDn!hW
z9}Lb6Ou+ZfIb9;MLv}nV^KEZLo7f5+<q|81WxaC`<>z0>U+If_XYhCpnX?|<9~v((
zkJ8T2z8RTp1^jxEZ_Vg_!d!Nw9GN}QV2zAS=ma}kjO)9cY0O%rn}8O4Or+MAn0qLi
zrT)N00f}E1TG;!%=JZm=Ow4A)5(dkYTVvbDcvA8U)XuCLROG}Si8^u49L>BTOD~uw
zo-1>T%STIam}%^&HfgMS1{G~~D$VT5;$Ve#+Bq%0aV;9AlFc!u6SFyG+|VLrE3DYH
zk_kTi7?>y?pajsDXZq0J9pOftX^<{c$Fx!l>-Kmpa7IgSl})(%dqugG+5*J!kjzZt
zb8TQ`My~8DO;V|?OoCFfCMrP@*(NXgo0ko8X0lUZm59#gI@8ZwD1k{k9ASw)H!~u=
zG#$QJw`W*p3i7+}CrvFg$s)V!L#Cx7ouHDNnOJ`rDrSR-#O2XZ7lgA1#PQeZ+sb^@
zK#}*4as$ItC+CTkXa{=dvkydZew%Nhn#qpAF<SpQrDo7nv5kS*`DAMn%GL#zaaJOe
zalD$rS)4ch{moFWxfruzfYrQAC6^d#b=25)shCd7H0LJL7$$><vi^5|Hd1#hobzdY
z(JZ;<nBwcsU;VLVi#Hy(%zpRUCF_sj%+GO$Rx4+%e$9jZyUP#v?_M(ZtmFDCOIGLY
z&d){bulQVf#ovE(&hq*7X``pi8mK*VceMD3vktw_oRuFvWn!TAz3l_H&i{vLJAbl7
z)}OR}7H58D-D>{5_nO_s;`u8d$~8{do@;e(D}LgRZ1#fHkB6I9K9FmjdvWl+b<OP1
zS&#RZd#~=_dWX#X#`flt6-Qheo^#f5;r+9k(^qZZ5#8Eb4>>v%-oJgv{Mz=bqFaxc
zJb2d;tNTapxGJhW)<1B2arNde&R?Ce4_!5|;rx%6?WRu}Jp*(6$s#Xa_}Rl&yyJ6+
z{pzSMzT#JZd(T1ZPx$>|YtQ)OVP~&j`u>Y9`s~^V7yWV0i;JFH@%{31hkU>PxxZce
z`#)|y`?pVRefqag9eVcfo|=93``&!;rlZ$~=bZc9+3SA&$e}-Z%~Nw<e9akiF8cg?
z|7O#3@B6#o{O)(j_kZ`^<i0=r=c_l}d*bU}Jo=BBXFmJB%-W|uKmYvaUKM=rxpfCU
z``kl4&n*3B@x^zqp8x)TdSu<E6HYqz_Ivve`{BJ4)6e<4to-?N*~7l~-bW68>HQ}i
zyzpZ-bI$hU;BQ><-JWMZeZnEP-242&4}I)C;ZL9YZg}haP7VKj%i9k5;UC_1$Ok_1
zokPyK>-9a2flnG6UE<UGqvaf;Tla<6?Xtz!-8rLk)b4}6_;;sm{P`=+Kls01aqimB
zuGn<!(Xac>!vA&T!_$6W*fa9nP_y(@(zx<Ras8vej~h458=QMran7a_R%JG=Ty^lK
zA73^5>~r0r&-DLj`7`-5R-F5(^ImuMtIj*@(G%ZaeelFDRUe-A$lO~;zBBt7_td-x
z`_7wZGdBhG%{OK5`Q~U(^M(5lYHnOTZ+CHc-rkkR_SS+E;^yr9%<aATnLpipao-0r
z7l$8s%hwM5!0TUs=sBB{{<AmR@Y&D(k3)XCeRWUm>i2|aU-pfIpLy+D`k%eyr2d7k
zIko2lb58Af@uroBEWF{{hYX(o8LHxkN_sA44qZ<5%%0`Hv4<V;t43kP;4!zCPg`{K
ztD?&1URS7mcKPzNd*iX=o?Eoy`2Y2~d*=P|unp$-iw92pR$={;i5X`fdBxnd@A&<S
z7k8g<(2B7?9y#=$^A@g1E}MPd$w%gg-hE1C`72LebkXH+`@4&l{i6&VeL`vZYyWND
zJ+sd^?7{P%?@1c7vUAV9BD?mOqk|v5XE=Mz(Z|hv>*<e8YrXq5JrBS7(VoejBL^-1
z;`T#dST>l=y=O*${=Hj@3qSaS>O-G<OK#ituSefVPK;We(Z2A!w`SHC)*bRa_s}7;
zK00{tEmss~vWd2!X?tlAqlVjTh7F!8hD=nc4&0bjX5BzDck_xwZdnnp@1J{5ZO-%o
z^W#D^`rP8$>VG<VfUr$(94V}ye(K*e^7qb)7d}06XkEiBx1FW@Xiz>*+>G5bXUy6i
ztePo5S~G3ne{5J-{@ChpD6@K2Q_fg)-{9#h21je<%JA&+Z{%pRHhQNSv|nQud?I)K
z@O#4Mf83J0{^|#EPqy0GhsR|4Z<eo)?cc@8NY8P(HwUZdzV%a+1^0zx`zMpVncC?i
zeXACRLHnMyJKCMx0N;w}Z%mxr{|vcT`#tOTud@RSZnHb;#RY%EPYKQ1wepqp%#xA6
z@2p+B@xH>`#<tilEmcO3Oe*y-shoEF@`Iw43zu|GpIE%-^_MMv@V!TyO~)*g);ZH&
z`Rvc#E06qad)hI-YUkV6E~|dKQ(d~4ug<PI@A8=w&)qN2T=$>H)R+BzamCT^DQ+5>
zA3QzzKh3vZIAK}yk8`SHoh#;6{_7jl7j8VH$DG^K^Xyr7%({Q$t(iYOl`OmEi+#)X
z%D>Law>IY%96TJJb6#dvxzsEjdGM8`1${wyZgNHL#_1Ca?<{T(=UzE3xoRSszUUT_
z^FN>TU-0?uud*Cpm5uqeZc*+e(s#&Ma0^>qC+c>%e0F{KLxp%&JfpENm|;uvj;Ifm
zrn&G6*|XpZsVykx>PMCrw13oI+TM8Z(vgjuXT)awpw?#_^IU0pDJ)Gat*nw_tJq$a
zGh1Y>SulUFXw0t38%pJoVy5tpY1R1Vk!6+Mk4+!5A33aH-<UmTY<hODy*XTG@0i8t
zthy!>R3F+oo@*!HoYg4>3!WcgpxWOi7aS+BXU#ibzJB=FP%FGAJDxu#J8p90VosZ6
zM0=me1)Jp%yTuI*m~3PHy!p#bm<)*>dh1|ZerKUrUd<`x3j3AJ;F*kG8uVjDmi(5R
zh0Ap%gatL-%fzNz`4<L~bAo(PIIGP|9#b8CLB2FC2$xA%PehDiY-#ystr^Y7@20<9
zmtSyye=?&ICNpv-X0Hg-8+BI7^HFwd7#?1#%aP&nbFxu!Za8=3su}r>t;3)BkLZ<*
zqD`3%M0>v=tbuX%#;{{zW6U^455`Aq+iJ~AGV%N^RepkSxBeuwTe4URJ>=P_p7}X>
zJtO#da0#y!4Y`nu?SYIk>Wums&4go&yhr%fnqdUTVK71&LYOTjLs*np(oa(Kh1I_$
z7(JWOju~d~;XA7I1S5T=2!tU4i|Bjdk=S7{c^Q$2VPM3%Xoew39$rzb>9tZu1k#dR
zw96&Dx%LZRZNX#<)NK8hyfijcf19SnO}GfX5r&42CERp5r|j4p7mvj=%ISMoPS5ll
z_iHS|@H>+@=F#GU4Xwx-L<P-y5+6CHOtTX7a6XH5SlePMi~U@(c7DpALpRo1ILr8e
zyFN);wIC9k$es&BBjR*?Rm365@j;IF@vz1_%3y=+cQRp&&MP>^a{W>GV_r_;9%)J#
zF16U^$#7uArQ_kyGTcl?`<s#}S>ETHB$RO|850exk}d2elCZ%$uf7e}kdb4pzKjzw
zCL-)yGJ;bfg=a@aZleT{BRWqO_$5Smbpc~Rghywg0ZNfRAh0|f@pve7;6Q?3M(CuN
z(+~u5u_wvrZ`VuwRES0?!%)kGZl`l`*Z>v6Us+@4^lgx?T_yu=$|Zezk65Emr6ae{
z0aJTDDn9-JIu0mhX2PqF%c&O+=J09{u9pefrD*g>QU2*~WFRsef}BoXkSM*Spo&t0
zK~G4F5N|Nk4NSH1%IM5Mh#j0p_0iRiFB@B9`1+wV>QS)%?r%g%7HT^6oicVWhon4s
zlj7sz5+pk`HfIW@BBH<J^TK09w^eRIa?zV^_`qqm|KN?kzWcn}Wc0OnUG%ow-g@D^
zzdPrLUq1D=yH8wn<)7bm(_3Ho;s?*!e$`7~dj205ef*+#edW!6xc&XF`Sr)&`HS;U
zz4znqU-XqzUwZa~M{fVb`)(UL@#Y`=(~%$l;Y&AtV9`}ieDF)>pK$N@-oNNer#ybs
zKi~WO6Ysj|H>ZB#w12<%OK*JqM$Y`4^sdj}{={vk{qq0%)0&6w{=;WpI_b4{J+t~3
zZ~eumzkklJzw*Rw&!4pDBkw=%t_%L_*&m#9#}khob@vBfd)P0I`_h{qzy141UVYVZ
z@4Ei+dk=f*UALX`$7kPm<kg>e>)|WD`=z)2>E~ZL<)zO&zvvS`eB<G_{@}JZ|KihM
zdK+_Dq|-&;f0Fsw>(rhmUK_CYeOccEJr815vRpjspwaaK%1g3viD_gK+qfj=$FH*N
z=?tn<rkx|xlm0n{0mpi5G@L|zN6b%pbnOzO4qk<|r-fUQKqW5LOwz~htb)^-tA1AF
z6H|O(vX|eP92{7m7jx$6vZS>8QtC;xpxMi`5sU3^@bXYMg*h4Q<?Kda#!w4L2IF2<
z0%O^YlI@xNLJ|8$=f(wQl0t1BO)@u%`*h(}I}uH9dgkYn?zf3O;xBIK40ZSR7oi6r
zVxfybj{}hVdxrP(*!|oGI{zZX9T@(<^LbUx6ovQsnpAJ(Whmi|79F4ag7B@2iW#K;
z@&|-mG{3eU(+3r)E|uYip(*WWu_P)<4PF(=kS^A_`ij0@!GgYvcf@3xL`L{F{vLxx
z<HA<M{&|{qC*>w8Z0K9+=a1SnRRc#%i*}I%bP!Uzj#u&$GDen{bZ!V%EFFxH^Qg*>
z8%rOPh?Q+trdu(_*x0Np#e=QPm9)hrP&RUOFi+FO<py;<#6@=ZDYCueBDQLT{74Jk
zAK0MRh%;>3pOjTiotX<c-r0zf%Xbd9;<;u*dm(-;x55TQYb9v&q3W=|B8D%Jm&>F#
zq)1s|w!PI~xSlU0m6%%@k3`y6Fn`kYU&iSi%I~u?{BZZU0Mf9%du`R`XA{ZQ*jy9t
z+{v0hNrXb8rVBdEh@Bmk4I>g8*=^E(_bfRR#bS$s6r7gUk&&`U{qhO6v5ic$L(Z{E
zWDT=z82*_L!g?K-2UwVl8K4G5sI{EDs4R^elk~C74MR-=Oi4!dEJ=V89?Z_UoV1VR
zYO$C*T{FAVlv`SAWB;vRs)pIg@`)eefF=JbghmcGxh>n6Hh`wQ32#!6Toi<qETC$Y
zBRoU+>zGBvIBq^fI|rwE9XrQ-u~Krh!fVB*;a{`4!gicAApscU1kC-=^O%hHSzO3G
zHrK8a%%CG}O;qEcOyc*5D~1Q7B|<A^aTy{`GLVPFOZKq$)ey8j5(%6{9k3327SYsc
zUeUp;v94u)mmwxnQ8E}&No-)ojb#2B_|dv#V6z@kwO)F7CnjX>2eFzKqa;cck;a6w
z4%@|g*Sve*S5+xR$p|@SBAWz!$OeQFs~sT$`b**xAK^KzmGQt>g4xN8I1$T*!|*p`
zFl5pYQ>CTm?=*u@rz9vmK;BoiLkAe^S(@tx&S;YG5)NuJvyypvk~uMSjKd=|{W{u%
zJ+>XGP%+G6u`O%E5v@nEm<{68I}26Nwl=EP*##_)(IV#zzLpDBD=jrhki859sD#v;
zN$jH=BnS>0p|;o>?#AnRnYCDQ`Efesu+WOxjvrS-r{PJzoq&qHue8!F93iYSNr!kw
zSZCFCC@0dHqk7{lt7V#uE*{V_57me8!}ir$<48-@slVI|cIt!JlZ1v*JJ~K3D<RrQ
zu8ErZwQIW|jPnjv#r`-!h_`xEi@a?36g`L~^AZ|>x`Yv-fZ9NAUrc=O70{hNuncOn
zg=9_*d!baimsj1`OHHFrjqZpEhKYJ5=Ov-4VG6MF_i|(jnuJIzVndNuZvZ5YRVggN
zZgfR7u!Luf+j6bKB*x3983LSfzQU_*EEQMF4q&<B29xLNA#GoUQ#h=gC_ReOfDy3=
zgP~&kVlAJdf;;wjTFjqDgea3T6Uvj55p4^oH@+4U2xy{T2GVMvBU#*iP(}tOX};l?
zxRfs3M;_>SI^CUMl{n+fzA!(IhZHMXWvUnFj5U0V7JTm_JmL&i-X}+CpicsemYgRt
zk<Z7~UsP<G^FI5<dUB?YrBETv`K@fJNkkI}R4Xb<b@I?qCodAVYfycqvOa`#IbSb*
zG&PP@(@kg~juH=tj;Tap^y2e4wKtZfOnJ?;>KT*DmaIl5dn`AGvbl}K8Bw=ShaL+6
zB1$p!L!u5comk>3-grGMPVZ34P;ZtCYNg4m+eq2)a9j{r-|RVGHfVkT2igW2uZ)fb
zT5k`&<f_Y1E$T#Uc{DySkV|ZEAQ4&3Y+S2oFs&~o+VpA=6^+WSHIY_~5veMqHm3uc
zj;pDy45lEMg@#l;%8hFNsof$5JvDBbE8U#YjP)Fq)>kA$<^pa5`pTvDKmr|pKI<%A
zOBv?F&j#%jtO+QmVRl$L>g|__*-!`C6-6q&hNPM!#BwQ52cEus6JcV<g<aPu5eLmd
zBdwB>&;vkB{mm)|A2HaZss{~7+s(C+i$Wu%PFBl_ulW|csMSXd{$gZ^-=r0c{*~DA
zuuOvGYzKPPN%$IGVr|A|yK&;p5@|1H9I7F`LqAcV^mi3DG4-|VIG>>hdK4^zEP`Fy
z2B>EAO~$w&&GT_OR+oWDq9*cq50(z2z<k~F*S;<Ed{z_B7LEK%;5t2NUREN~ElIAA
zi5|2KnQx#s3=GmVFHB*NZ#<KLy2=8pp`l-ZP1N26&Plj%0vS=|duus2uHAQ81r<39
zCB0^i5o=+hwraqRHum8S3_I&@fTmw{k;xMK;3JI_7Tl(+mW9Zu@D4(>hc*{b2h{?-
zRJ4hlw0{x?Z0C%Myc)JmS!aZZE3&OlsZ<z@ChgJG->MlvRBc#)o~o4a>%j2Xq$Wb0
zgy{=b=~OQhEieY5i)F+f+$LS$OsqqJxVOJxM$5IYqRZ@I;x#ZShEFo)C+#6|LVt3}
zC|vknZ`2f*qYqa&*0S%EddL1y%2U7GpG38)gta6a#v_*YDF|&4U^nW^&Poz!Noh;A
z;4DWnNyqZ_#11kd=L!Qwk+oYw&Sdlpwyq+6(}lDih=Gy=!ldO~kmO`|c_XpqHtV_C
z!U4R5^QMkX;syNjjAn^M%^7h!r#egW{DUI*zC~SRkJ?+oa{0U^bIAw=XSq=_x}c%~
z1DWQJf}+%I__sV?2IB+Ig#iB4?nw|SLybY4N*cRHp85D1Rat{pu9TOQHDe?%M#H<{
zC`$<nQ}KL|4OM-Ost{=Olx5y}ry@KORn%f$CneXKVY&IzLkMYg8Vs@LMzD|9jio^n
zI{(ny<Onx2MWZpSh-;*X0^WX&J;{}V?LJ`(1YMIw6b6sz-mHYmr?Vd}a$QfVz2@I5
zpH-AWPuk3a;$LShcgH0S(n&5hn0@nptKBYD*(Yi+!fvR5F%(Qr-;k)?@bKYAvAA++
zI{Zuh;y7{+>p(MMq_bX0n7>m6%6fCUYl+@27DsV2{L{vz$_(@Lj7`qcSy-93fznHw
z6M84zJxHU{tE5(c9X&nYE>1-y(s9J?3!ovMG8C+DS?{Lq>PTI|CB%(z=mkuQhVZo|
zeh@5;BaKmJD~QKS5;GYnr$t25npC(68t1|m?3;+>45Z@VtG}gW;^YX)(1e0e{)jYA
zhq}r7aTxgQNMub7H19w4q=tS5I&L)H7R?o!{3KVE_$7Zp$VHleC!bEU@3pX=#@}F%
zO&At)lHDU>9rD7=@P>>q9t<#$i!L^#nsSgrf|t2iZB7&rZuCEZn+vS~w1*&ILR_K%
zye_IE<2~t3{h>HS(CdmLQyUV{z4(-COn`LrpMn-$;xwoHJPjg%wd3g%CdSa#ljj=G
zkmWR|A*`yZ6Z^Ki+{OcB`DTH;gc~&+Ybf*@Zh@ghwuz%UQf6EcSvV=wK5tu45Blli
zOk^>O9v}y(T~cKK4gCS548?fR5`x2kgh0W14RJUElu&oUkQF|y93UcGf!Ua>j$3AO
zoK&ax!7C$W^)h$U<(cAraC+nXj<M>DBqd4X^6k+yyyAnb>ZPt!I4Y^n=nc9+tno_u
z_74RHoElQYH9Bph81KMMG8IL2Os#BjPhHA3RoQw0R0^B&^}PJT2IN2#Px@FLlS>PN
z$2L+{#I>;lqnS&5&mv8ny4@5@A1A%JmLlEDygW_A2fAdB*T#D^S$YA6XT-Bfs}uQp
zq&}6I@XnzO^d*UZ@19Dx()gB)dzP!LUf(m)2Ez1GS-`8Qr}8@BvS}Qp(|iUzVqf#9
z7|TVgp@ml)K?WRMEhFA5)em?R1PM(@m!*ls`4Dbin0iuSdUvqZ#DK#|?W=SH19295
z{;l2&;}K6+!WIhqczGWN>Bdtp^Kj^q(%~ihJm`yzMl)PKIyWC?(8Lhm`M`3QcQdp;
zHJT{LU*rto3T=N+>B)<ldX-^^eCKH!xE)stevH#3PNaTKYK>6K(|W1CMZ~9h>CvzV
z?H-Tes|L_mqN#oW&X>~;M%j5J`b9dzN`d|{(0u%+Rqer!YAom*K77A=s0}3lQ=9p`
z5-6gK`1FUTRuA2+YJzjBp7GRB1HK~SaO!2a)D{&ww=O^cDx@`pjz+u&QDkWBjTcNb
z8#NJ02L+vlyyBxUORO=y+u_iVG!Fc=sUuADc?xQvp@Kvmj;Ey#<6fmc4bgkW*9I*L
znivhC0ia29lp3c*fC1a$>L91?V=2}pWB4_Wq3-Qb6fo)Yz-T_WrXtYFX9{&P3SG*O
z7?ej&1*v(Rg@pVNt8Z;iv^N98UkzRXZeIbhG=vJ(OXV2qozF+SA>^t4K2)B6A$|To
z-@QJn_5q+$4+L)%RiF!or^ihp4tTl)d{Z7@P^LUQ%lo-;#$8<w#Qs&EI{<56_Wh;e
z;`U2iw_v_Z|JPgxB+I-^!4P5!+?3=0)$^|?wO_ouDyc_H&pz-Qs41S0?!){aIL!XE
zX`bzea=8DxMqNd^=|6zR9-y7_KOk5UDNN;|O}#pzrCd`${}S93%Ha4*b~?H~0H#=b
zBuaLpIOUJWDc<NUg(;4PI;7%_qNkAR2KLnz>%3oYYV%LrtFErniS?4Z0|pJaTyKCU
zFy6Tz>#iAP*asl7%g0*Wr-N*D)ljxpwKty9w_*lN3TZar>!v#z86yDyR3e;G_%o-l
zP^|GGp?c&2%gwWJ1X)~+GSk!>LO@#eRWx1;2jG-VM_nlkm4z#fr0BGB^JI7oe;(|P
z^vO`p4^dTNuXD<VHZ*E_F3!_=rEnq5coiWt$g)$CQZkN|hWna1&69y1B3Ujk7l%=I
zfvbT$+fI{PQEqLM>PmBHd?_*r)pSHfLgIi6vLeV~kRDw3iQ*M4Q4W<f5!DE4^VL+E
z78hDx{s_`^_$FV;lA78oiYAne>ZH*WjN${N1y%>T9BQKR7sxDub!Foqo;3P$$6sW8
zfL}+_zQVInNf?802`z5NnV%%=XvZzKt-E>I<BU6M^J3B#l{~DHkvNE(lsk=kpu!Qa
zn*=$+wHjE=qv@W+RHHs!urb5DQANC|slud?z4-pk0@}2m{7mOeUIy?gJiU3es-<AK
zRQ>_rX|rNY8m>g1#*ao0pu`h7ZhryH%eejcT2ElbDU#{ODf)d5?ekM$tg+ACwfR(#
zS`5JAQ{bi?+Nb-(qzIcnx_6_`{bF^c`o3Cap_fuX;`?ihQ!llVb=(MntQ%`TK0b&z
z`Y&?*ecXJ$I*;+cyJ@^FyZwb0a0?sWi*zDEsf>PV!+N*!H)+}_J2EZ-<d7M~_o9GB
zjO9J94ni-lpyR3H`^7Q9N^82}(k4{N;6ijVM9F9~t))1_h6r3pYV+h`V?Q3q<C<8N
zs=MsdoF4|?tFs{O$VJMA)l2Iq_!p#XL}Q|Is<2Arf(!UA3*1QQN(&usW4J@6Q4QC=
zboGH`uHMfdAc<o!uu_F5xct@|n5Lso%wn*a*2c0`GFHW~l#Fp{+jQ!CacHK(#tTcu
zsRywB4$r`9JCPnthLz;F7`>;U`t1XYD=^$t3IYXpg9mOMdwN<kM-iGd;~ia@w(CJ<
zT*UQdC3U7j-GPj=@bLpoSWpP9(x=jRSS}Tw0s<2xd$bW;MA1;(+Mh{S;|Wex^>@d^
za;Z`#C6lt208ge5qc^}c`~v|9@qjLXuOm8d1B;ZcQ};flkY=WQ+EiM?Qo1xx-f`lT
z4C+G%COUpLT>Ho@PTn2G<CIwS>yEr6Fgk;$V7bP)Q54fOt1v~5aM9>%b7h86eiDC5
zq6@Jq%_F)>Sr}PGOma=AKI*Yt1|z^j-_q0z3p~mQ7CvY6AtSCEK?AuQ_OE%Dl5rUx
zWiHQim?y2eG2%2`^ee_!>^SWY37tx}@wp5qzly2x!}PK|xFYI63R(j6<H1^F1C<vk
z-s%lVkK$YJ_Vqy7c$JOEX+3$*8H!W?5nS-lMV-(<*-&br4o_ul+ISFbw?h_{RjAo7
zd3B`)eDkIbt#~EKyKH=eqrzDO;Ld?tGp^DkDC3pMDQTKK2STMOxv#%W{l=b*q8+I@
z)>{2;jtv9L*KDT9LK(EIG<Z#%)?^s8eV<IbYf#!$kqEWZFvxhV<$F&mv5jN94~VLv
zOPpM<Bs4(Gw{9mKh0)rZNAW0YGh8^mG{x;@4N37=32m{Nhlxli6QxOH(Srt6H{z1+
z*nEoRAO9_39u~YZ?iQ`Izc7{%6^cw^V>(q-hba+;@bBXIl>&{#DVYR%L$JQ%$J%Cg
z^|Oj~DLXZ&k}(~b8rgIA$=If3;9=;ct5-FPd}vn}XBpl25WRt1sGN0pWr^&!RZ4e8
zIU%mf)kzLp!f9Mr2Ln3QRko@6dfAZBE*NF3&`z1->mvLluZCDFQ}ay@W0Ox^8icXO
zEA5YBJT0yiGU5y_{Lc4GHbv`jTjp#K`6YG1TUjj)L=G|X-$8X%m{Q2X&L_Zg_Cfw;
zy3TGorvjqhZcN3i<SD?vAE{H1P8m-<ozm?~ih5AM@-SQ;x(cb=dc>4#D!@Pe&2&*U
zNV<vbc0c<f?sKH1X|#Pvnl#mA$`*Cp)(7e)bf3U(T6{d*cVOQXoYxpC73~?Q?LDX}
zly5twze&;HW>U0ZMZ2W-FcL&Yqe5ViX0_b{Z}9^x&U)MF7+g#&PLY;|D>gVP-IkMz
z$;wltm9VZV$1>?3R>RXTgXED3+nSzN^?-+DTkQ(a$Cuca(b|~;CAjI-`D7$HL9Qe2
zo^G}o)pkD^<~642-_2aq0Y52Gq;V`-WN9_6FN-0+SFWLm4a>e~foPCqL8c84is&v$
z6}PV)iuA`ds)|U<_2<^$;G^Hf418bfG=!)f{C+wSA0ITLVbL65ZaB-+;3U2J<e#_z
z?PrBYMa9x)(hNoV_GP^NQQv?Mu%F>5h1w0<D+|3WmuI7n3U${oAOAOzPcL}*^Y6H=
zp>ATw&~WM!QjHv1_Qv3Z0#{_!rF*>`IL%XM#5iJ=J1H*O1VsToECYciwY^OHv=(CG
zAgQCNv^i2+Cu)|<fryYeK#R=?Evn<^N-RJ8!Fikba=))n_Y|lGMk0NVpSDxv!V<|x
z!)3{)LU#6=GjbD!Ic8;X??fS*zH)fg*p6{N_xqsqjhmI72S;~GvZ**QJHDg1$;6rb
zvb}?a=%e2l-VzQ)C)Zc{xS7lMj<$!Jnc>`6``X>sd@IZ@8`u;-U>}y`%tns5OD781
z54G;tn-sDi-7=gj4P9$8ohiAtJ?u7_LWtav$^%KTEcr>{V)R08q;e;YO!b<QJ6`d6
zg+}G>+(_Iw6QdV$1C^_KZ6QszL6QMY^S`pE)Gy^?H1;`Qd<{{XV3m%42*o+gcgm_l
zx`ZiNx;nL@WeXLS)GP1?v@URXz1u&m-npec%2X+hTo7siFYg(nPp=oE8%}-brJsLR
zWx8?|XY`gXQrXU=dPJPc1^fU8b|3z>_iFL*0*;Nh&I?c14@0_1P4n>5u+egq+z|$#
z$?4^hQ95B$w(-`>gOO%b*qZFEN6q;4eG{dsW6Sx(nS7z37)*{LsATxz=Z=J?#z<h`
z3>U?{nSr9|kK@ZPFGbmHL2;xJeLc<<N5X1{102>`iHCzp>zEp;Fgelp5OUcTkKAM9
z{Jd}^8jM@1+$p{KCPI}vKEgBsY2tVMOkj)zUA<PR+$M4-NR#UIJyLepX(Cg4QCR?N
zVl*T5$-_HnUU69V33&+hN#o-5Y0``4P;0xE1~JqdhgYHD@9E?O?Sl1|1!uGfK+D5=
z5~9-hcqj6$79Jab(27c!QV}<D8V^Dq5sibvCypx41C~5A9B}^L#i`qPg!Pmu4?pfR
z*5iEyWuh_^V`wIQUxC}<HTq0-Nma6bqzIN6`vHkaWg$aDjD|&6jJO4>9vu;;ko$W2
zRJNp8JieYr0T-zafU-#wrTO)Gzm~h7NC$zZRZ3)clP}8y?S)gQbf2y_>uG%SDPt4I
zb;Eh!Q}FYWK7Z7Qd83AoB?I;C17A%%FK!s98<%jmkC75vWso{}`UvX7zBx_x%R1w<
zEpA<6t9(3|G?K?-1T5suoQh5Dg%l5=NuN?opN@yxS0UVxx{dYTR1Qv~Ugs|_LcKub
zwezCczCij%N6{5OP6Hviisu2<H&nZ8T(4;|;qzYetMLxcN^<%zshc~bUa7$1u|6ga
zQ{$$v1l~M2IOx4TVvq_z&Qu=T7&+zc-qNW;VAB{c-w~y_5Qdw4HN>L`4+Lr*8^NRd
z5q%}r0Qzw56RFCoi&F+rD_EXR9UPDAc&(J!1C;v#J|D#?&fmb0j{gqL{Sd}7kYR(4
zvTTi~0k{n=12_1o3@$K6ohBUz`9Vk;qD@mOxY%vN>Yki!b(r1vJvcff#PWpHXmBFy
z9w0X#0m0i|3It4nvr{gf4mI`xO11F>Ty`IFpTnds>&I0lwd=k>b&v*4tA7VoKUr?~
z=Y(e;r0#up3YD1(+cM?wt?)jN6W6tcN6}!$iUCw#fRuC;qa{uC*p~(Z;BFM9V7v4<
zjpe50iBPrK?2B<KxgR?2FAm%R(B+}DQ)C90vho?u^RIwSYtPFe_GPEKthUor&Dp*n
z=Uq1Cz7Lz)8n087zo~<=mOf1S=-$zHNK=`DQ5$*Cba-REY%c7k$?#C0a_Dm(Hm>cc
z1=3=lCpNoS&*UuD*X&|s3(9XOk;RvL%g{eW;xKBVcfb;&9}HzI8r2#Y*x-)8%CQ5T
zl%qdgL(Unf>WpQzhT3X6Ra(zQj^VD=SA2r4pK~82$$6HnbuQvMu}+m62`y#E$pbl)
z6PcVaVGTCI__xetfaU$Dwq>nE4m*^&F&5Ts2i6d$uv!e_IeRM(`!U2(d+{z}p$){0
z7DE&6VS%VG^y6#FOnFTZOJkLvj}4P{Y(}t9e4`&S3_UBrc7Cu^c^wGP!vFt=|8HC1
zs-OQ={R6PUX=D3^QT+CS^Dev3zt6EhQ5X4FsP>V22gUs_N>+Rz$^XvhrUF&vE~IMw
z6=g(p@8rW@m?EU=By$7$T2|^RI)B}L2_1<>Lq5VkHcma3tewTHeQf%o_AoD@G&t0^
zin184B4a}ANP}4#4jI&+jBRP9)>OWx-HG%!A*hD*;pe8)xVb&_qnoIs>|iF@#`o<P
z1e4}srs?=mt-6Tg$MR~Le9KiaQFC0!scSjD$ZsssD_T=U%K~l1WY~gaD5yk})ZvOv
zsLvdC%ngLDNkGO8I8N?2=_D+&n7?LE{}{8Tj5ne&MoG@M&dmn%6z*WAOkH?=B`dq4
zsr*PnixRHDt6QmrUL>(H!D3N^dEZu8V)8eU-O|)H7fOR&!oeNM^|N;KBb}UM!lFsy
zWDAqR20mt${=S9@7e|9oBBV|DvX0lRs%xt@mg@!?&{lX8C9UDfY)4P_5?+x~rX5WX
zCxVaW-_Re_c55Wdz94=;P#ax9jV9T2mK1iHWL@l23C2a1MzPQu4agZHk1Kfqigh=_
z!ZG~11~EksCvj1{5L#z)Vl6w4E#KAT>}gm*T#YddbD0cVoabLu6%tvi{dh;0Gkn)c
z%ZgvY&OuW=*Wh2S<3qZ(Q51Cip*K7LV~9p<^2dtPZ=;4TO;%``=U7ep36sO1-zb~Z
z6OOa>DVCo&$2l5)Tvd4bZ-y<yg&3V{j+&v%Q)c1}7?RJtmy@Mv%dkUj0nUv)>W{O@
zfRjyeo3pF^v9SaJIV+4sP9y&+K0hO!OCOy@Tp*c1r=2)lg<CwqchvnF=Fp`Yj=vVt
zePPuI5@a!Nqxsjb@AP4RQq)NL1FQiPs*KBl1cT=I(3~Xh(j-2e0E>b|r#SH@X*`j{
z)|*%Y^^@$HPYA|w7;`0Qo*MNu0tjHCjFBHXWu-#9@o_s#_!a~iIQh_Cs}G~Lp=eD)
z3?7Y?g9khHrlaX1V~y;NCL0pgLxSCqzIiY?U|B+AfdLYSk*$wul%rB9M2?%5caSi#
z%&pPRc%%j>ouyFZ3lVY*>bc0FL#!2q|Bly3RrLUC7~w>_l4eH}n`x-)l3)r-x*E~*
zxK0A<BjFNNN4bZFG7WDyhlF5DBEV6(hP$Hc)I&P-chPpNQK#Ca7V5uu`hBwuD>O(4
zrq)Rzlt8y<JBA<x4@uK7Jxe@J8c*rXC+YZ>o3a2y8a3xy)BvMqgSAt36k`qZZH<>>
zJ$(&y0fh}uJua$8xLm!ZKEh*+h92ne0ba&<yf>4MwG=Gs>{dsS*?>r`Q&AsstyT>}
zpZ2>5tpUkTLg`XUQ`&f#ZE13|p~`|9K{igF4DvZK&QnmNeGUk+cc+Hoq!x5RCEyoI
z9onfBwAPcs$RzE2Hvt4<=}(M4;O)5Y(p<NZKOYJQ=;DZ0$hRdH1k-V`F{p>Fr7z~o
zqW+W&9?PZqLLZToX;B=8pezxm?n7FB+K4*jZJ_xZABW<~a~K@Dr{Hi^#H}F!7)7@P
z{dL~Y61Syol_~<xS_o(!=NkM58YzRI3-r8*s82_0P~L%-Nx>kz6401sBC&=D+G>;M
zZYT^4{1|34?+-phT==94<L`pU;wJwBL>iG2-vLi#6qi{35$|*nFN|U*k;+yG%G3r5
zeK@K<pFgH0+F$_)Nt;Y^lISU9bh5Ha=_Vd&h<3EVTm68Fme4MIO-&iQ5y@&&%Dvq9
zcNzzX^OJroU>!)>DYQZq4uc&72n_nI^ifa~rHBUsktt(3LQ$a5kMe%yaO$N51}1h`
ze;+%fXMvy#s$qHD=+CN9z|-Ho`{)Yd1-?2kHAq6V?bZCFZ5cqk<cEU|nhR^3((wa8
zd0vr>k&!l`d>9CABBJS3h}Kk7@z$XHNPjaxj;ebddr7dJp2BbSN}(0b2;tz8rS%Zb
zNTO-w8!cKB_!MR6oWTLqA)*Hoqsbi0Dhh7s$Gt2;RnwVNN*XTk-@{$!ux$aZ3rM#i
zzVk79oiE|d(3&x9Zcr?4%Cr`-Fa!{j*E)@DwB;CyK*r&iyeD#|6%J;wK2ymx-rO`q
z($k&FnEq-fZ(zK$83{-%c?WayNg*mu%3x02T+>Zd3;609DN?#!%UH|M^<^8$_53uM
zzL;siDBn7%Xv1Rs(1HBWxC>#gV3mZAOLE+~k14;Up_V+b8bWf%`EKTr>z+%GqGND|
zZ-NDZ9XJ@7CAB951bGM|pFi;HCsmnUy~c#Ym;hcAj8_e>o~}?cPKO6sk`Oo6F^W4D
zn{!s7+-GE<%y-a>@QSMaF31K0mO{YL@Bb$4ec<G(%7g!N@7$TayF0skcQV;bHk<6(
z%>*VPAp=HOEs(RD4K9)5kOYX9$^bzFDz28=v{F2~Y{CQr9b$m+N1f21p&~>YAbr(l
z0uckXc12qA!>B={rft+z(MHAkexGw^6YTr@efs&lzh`&O-{(BfbDs16+;i?-ZIis0
zhdPW%LMGSZYFrORprP-Lu)al_%*3<9-2W=@7})YXc#wy}AYUoARJ|duOt$ONCV)v#
zxjQ#uwggf#QyCt?=2;sTaq23XuSJRQp$4WF((y80`_+oPqeDZ5qC=L2o5FPI26`9j
zXP6jKRdXxy6&SsFNpbWZq?$-@Gt%|v+D}CCUEz(Io^Sb4U)p1B5qY80(ETD2l|j{$
zLA~GSwW7?<sE)%XG}2LCt<;Y2qR<u?0C?$Vz%88-T1<X>3tLDlMMjmPi?FEgZ^G3f
zU*F?o{x~!XZEyKosRagZT(lI?8Q&xWz)*WxEG<T0hTOoXEX6DT7Mc<xeXznE;}Io2
zx5g6aM|Tbgr%xeWi+kOwhJ{BDE$BG)u%pl~J|JN*EI)GQK&D;-QLBfVHGL^DbpkTR
z;i-gp`QqPU!USae3XL*GJPd)JX4N4;bKV%cOg^G-p$<yl<MKq=SqhE>ngDG>zN-nD
zJ~<~s7crgH5E8liyFf5#FvvelqprYFTN3&N3@W$YnVPN1Y^Me?G<<nW4%2qZz3wth
zaA5M7fZ<nkh3VRKXz{Cc(7O~{(?-!j;9M#g=BBwsLkS0w;+mwZdqck~W%v6361sG|
zHb?}los?HpWzx_PxVRW%{WqXqke$ddhFe3qNOT|1*x@FXeFSgaVjzei%(QUK#se41
z^o>ZN1r6o%T{SI!@&~qNk|Gh(X@@p!HzI%#9VATBN+fgyto)EM4>x(woXFt_xsM~U
z%)|$Kzz9WYch0BqS#e6CsBt2Ua3D0sw)lmWwHEs{e$ZjO7CIB1n!4iZH=SI}k4Y%#
zgJ40=cp3-q1Ge;x`0*K~ts#(74H%MHlDlz|0MdyHtN{^aB88O%fsGhds0V3Qg@z~}
z8W{Ouk<b^e^8PX)kg|Jjvp7i!IV(=6QIQeF%26R<f}a;05pD+MsWu*CCC`LNl%#aC
zIS9+Q#DGCD()v7yf?>cGQdR_Z;Dq8qrnF+9<^p4qLOZV2QWNuW42gxEutm1v*rlW+
zi7)l)GJT&?Ce#uIHg4)^7|J+rbRcIX904L+g|kXKzooky5p<<N6kDJoaZ!Fmgwy=2
z`^Cabm`Eli?_$B#p7MQF_B5(6Q%Q;rX#;*BNLfkd02eYwNsS#}>cthyOjjxNjeD?S
z7+zG$po2F|yPP5-_dTrxUj-Ek0tJ|<vP$Kh4}*He3`Uh6R^G6L8DzK>n=#C_5kn5f
zNL*50iD0dX#};7e=JY68N1A>YIAu`f1z&JwULlrN%8CPgYo&&joo~v}I9$%749>w=
z-Z;`V0%%2z6D~p(oKf04<wqYG1Hs0LCEi%?VpHQ?^$9$Jy}0Y$oR4wD46KN6JxuA^
zy=q+9eop{lXKMsi=)SbYr#zP%gA2(FQ4pbKi60l`92Tv38l@>tUqdAhF<3MpRx?r)
zggj(~LIaR>LPAaU6algl(kHGK6i~@7V4eARjY{x>b52D_ygx!viJrw#Mo6RLY{eaV
z1K%QtrgP-axK&R~ReB>GizHE!r~H&K7CO}KK<)vP!FZ4cAGA)_Dj*~ynxvA&kHu>w
ztc3mugps2xWDUQ9;0ei7KwF`^VxEbbqC$)q@xBoT-3Ag3Se%-*l@ZRyg;VhISrl0F
zZ^ayCt^w;XN_Y|abD?4p77b#$#Ie8XjX6id=rj$H@{tEMk$Frm<_on3if-5tPL2~u
zkwSAS)(K(IOOyn!(!k}=x~BRVAHUTSSmrm*?@WH9mtp|o4~nV}3tdQv>;aynEcy%T
zC`p(`n(j+5s8vB;gos3A%7`dhT!4<()wuj!(6fg510F|_xH_C@0zPja%@fRsM+(Q6
z%50U)Vl)YSL!8zafK|<YMXO!mFk_2{K(a@mU6k~%PTR3hIw^@%tZfSJnuzEMd}ttp
z$V0pXS2JW~2|5B<5zr{LS!@TfBNC}3*|-FXfL28#x8siK7_p$mlqztTULY(*t{6cR
z&rjqA3e3@{HdYd7Fhg~>P-Tcj5FoI8-Oyqei9{JZZRd=n=tttGWGlznmtcVl{?v&s
z_@3<)X-F(g0V!+1p<0d0@^g8?R>Oi!14v;>+x%}3w`i|HinRKqGZ=JBViF*fX6xBZ
zrPV@He!3At+iHlem78Bq^`*uN20gA65MV5O*bOOMR(DHif%hysF<p>FP$#E>hkMrT
zNs73X1RZcM1GLiB#$Z7REQ0pMAuhe3Y2p+704;{$CyNH>?3Y=q46YQJ#N!y$#Kfn_
zm9n^%2rlG&K`^nO8W0azgoh*2aZJImpvIuFq@OT2U_<vqfNpVbR&jFRb>Itsp%=&t
zl2!WWaqv`C5T6kukg;wDh>j3&oJ8{)kD-T~f&^+QLleJtyL_(Nda90YJTgIeKm_2l
zPRA|+#t9@ep7qA`8wxfO4hRKsC!`um8hBWO8@z=hlqC%c!gMr7Ok93}CBR534~O)l
zn8V@+*99r5HgWImN=1AYBNjz@MRC)~k<d6U5!IKIo`m(g7;o5O(>ApuOLNiq1q@7z
zB9pMQ{NfG}^=bTmosfnM;&Nb>Y#onjt$5{<tb)RE<r{_15l~L6cm>A!N#DbCN4(CE
zvK*NuUiwE%vH+ZC@nZ2ni9})dh;TKaKTIgI22p_K=QxOdjQohVB+}yMcM9VETo`Kt
zoyJ3-{tN{W23TU;$GuEUQaWSDLlh+Plr3x<^_O-M82VP>OF}7CLplK~h7kjTF=>!T
z94!QQoFNp0E_;rIXF_Q(+F~U8Win5u0bBCQ&H<sSQZ;dh2!Tw91fSq!M}@3DuX7qR
z^vUu4LgJV6^F&>6VbqdomagD;a+RdEux05eiO!2cQUw+R4&ci6Py>)#@-E^BLCRpA
z<@3JQI6LXGAhTR$TjTLbM13*FRC?UWZ6s2Q(SW$-s?t#48G>{p7@odSs;N;eun^S7
z<zNuD0gh>1JVp!wGJ<I(VT=~%kN`A}29O7Yk`$`Y6fmxvjH=G<LL^X##JVrxZJ@eb
z3yRbFn7ABN$_)pJ=(MKBhKw>3PM)~H1PA6-sDS3ykCa3>UA&F4GTwubvI;}$k{X{P
zB^aV~vB`!N8=>aPpehT`zJLIJE{iy9qqpso*CI7fU41Tq1SAW@J6a6DT1##vFBa+I
z^f4W)h>G*>(d5$5gy*n?m9!*sb5AMf&##iyqH^Q#iKU0Ya54uSQ`ypp8#e$e>6uYt
zxb+U0;G>;}h|b{(2K6Jq_6^j-engTTdF_ack(aE*%LZWveSvChNr)9g8ZZC_+PRwx
zNjvqFZzMrvEapkj;KjhIlt}yp*f<D+NC|9~wl5OMyo?~^bj)bHadIdVthELQKzE+l
zMoeLw7oViY#7m;U4v{w($T;kI8VbadfJxpPVOR)g5gib5oKpq>H}?$mlmfJ?S4uks
z<K~HiUx%mk_^zDk3pHU<j^DV+$w6?O1wo*_5X-;C2WZA;(X-Wxp@eE&YJ_8%*g0jQ
zU!0ns*o_+DC=Vio)sd0lhV)wL{@8oc%)nIzWej4(4bWpCxvUmNUn!X};^N1HCLg3w
z^^+eyyhq>fD-Wq*XheE#sBM9&fR10<hjg`0b1`k{4N*UdrEd@%q02wxr*C=cM~@1M
zRhGw-WF5ByBVoMT4o@EU5J<d$+>u7Nmf(W(Sl2m4{RE`>8Gf3d0QIw>Mit=IB#;bK
zkS;y@Fidyw6K07)cEHCp8eYN~h?OFEf@ncNmNDa62<6x>5%IUQCQ>-iPEb>cN+uPQ
zJQ8mYc-+k@?@7O9{V;ue4PI7<!H};mF8O>}O{x9YK*OrJSMrFT`Cnj6zrPJ`!~KkG
z7JbmbhIKf;n);(jp!;ozC<)e{e*?a^Bg^i|5PXMJZks6SG_9;b*HylAH|({9J3_T}
z2u5le71_(=GV_($uKeh1S@C+&QPQXn)7<}rdgpo3PM_+xR%N+jQ!%6p)uu``VZ1BL
zDp?t=WI5&>?*ASlFJVvj1wX?#YFn(e)Pu~-;u@=RIaFu;&dDxrQFaGeOBLj#9pGo}
zn4P~_7)-NXb<EEM7u_22zE<Xh)@J!=y<v7^yPJ6??y~9y&GJt3L}+w1phMxwvQ_y4
z^gFGJK3r_;DUR`iz)BF#jKXq1uk?K%b3BgnxE6bn=7qr2TMA;N&yVU+i)RUvhcOeT
z+F!?49+7^YLSKoj7Y^Z!%kn?zd!wRNn|+?RQiY4Vhyb<1fjiAt;YJ284Dwad1QtXV
z_Lust+7HxWDnNFUBBM;gGG&MMc8z0Mlh}+k+^=oUAUg%A*_+U`FGJz4aj&LU{#HW@
z&zDEf9co-f@?M4<@3aLMETc85+h*jufs~n_=#046rfNPk0DsVh8h^PR9^(^oYs+4N
zl=2O>&DMJe3_gyDZ1sJ<ULFQH@K^h9;-hV}6I-`5q+~^MxsxMC6XPvBQwRzb^1uqW
zYExeN17T1jc{ps@I!<MxLS;G)Kb@X_YtdRV*=lmTeQ&3_`lYBx`s=pvY)$J{sRYvj
z%FcMaPGZb8T;mTbb<tR8b2PhPjB057(hbcEHQ$dh<TU6TOSq?IntZn1N~744$m!<5
zN<Attt)o8V!d8?_o6<^8WX2&rNE6ox?R)$6WKxYJlzb=bDxQZLo?hkV&kMFaecGbY
zWpn()?|fjR-5o5Ne7d%%cxiV=zw=$)m0zBA{^XW?bMESv?#hR{Gxd9S&t5%#PWrs-
z!tTO#D;}tCIcL-Umre^FTeNQ0&L53TGvnt>T>Q$$t&ioe+q7ri_4iM{wDqC=tE%Tc
zwqxGRJ^3HZoP5!C)tB*IwB6^--?rnCnWdH0-NS>=29@3U`41gg*nHEn7qj}Jm!i#o
zpKW{S>4~<R20yL}AK<-$bMBq@@-OdAX0KnBDSTj)U*EDd`Lh3%*K>Vq%VYDul?Z0t
z8)T>5n>_CW?`+*QZ`zE~yY9^nU%_|N7Hv;Re)XSI&)&T;I<{!>vJ;QIW$}qmzh&{B
zUp;V!{qX~zUH_FmA3O0hzh9m>f6qUhSbFfRGp8MV6Tgo?-h1%-kN4jEg9~OK{Luxy
zH-F~l``7>I<_G_N@x{IW^_z6>vA&Pocj)R{X1xCN(b@Zdy>s@lpMJ6R^+$HMp1ALe
zOHZuYan7-pwX<G7^T^DDA6dHi(0iA*9eVoM`LBO^?b3&S@qsh0{Kb()$FBX;%<HG$
z)Vt*Jch7$95C3K6>u+o8c>SB3I}W|+lk@)aV;%FpynOX#Uv0YO(nDWsZ@T%PKG}5W
zy-QjTT^l5JfA~=1iyyr*@x@EO+kV~^-)%o~#YEGQ>#~WTeB|7wpZw{)O_JZ&IKOw|
z&mLWM?A@PTwe#75#V5uFPCuS};BotR4=g@@&z_~VFYj4eymtMJ!k?X3w5{*VSqJ6!
z{m17_{`~Qdo4#_vj3qy~pnc6ZZoXsm<2T>^+P8*#Ym0|_H-F}q>961Rkr^i@ukSdv
zdtL8iW51ZS>$%@fd)+)zJi7LC^Y@(j<K`tTADH>o<xjUCc+c)drH6N%vF6^#-g594
zH}!4)#c$`Hc<*bo55MhCXYOvhqIb!?-|gM~&8^M5mThf*ea`90L#fl}ZSDBWM3h|K
z^x97+n)ZJ;XgV~wIq~w<kG1YR<Ko2b{zHj@WtVm22QTZWt<8RX$K}}>$F6v~>FDz5
z3Hf$d`dOYm-SF8}$KLbks>uZp%+I|ymx!(y2`Kd)2l|gS9bY@N`1p0HrIVN4e*Vt)
z4%|WC>6IeeHFECG>E<(|)8C)`aNFv6r?u?7V&S&6*Iv?b-VZLmZT%0@x2=98pSbej
z;*34B_e`(O{x@~xNB+!8|Is(=`G-FdoPXWt51zRwQ~73L;SyhW>`5+6Zocq~i{F2G
zIz6#$V|w^)7q%Sw=bPr&{^^FIG0$aQ{`%JT_y5^F;kv)+Pi#)?^wNnz?~9lHyl>~o
z=H$-Po^Bhswkvr5&*!Dqu8UGPz0|F4`o@ci$1Zxs+w&Rn_8x!b7q6S~wwqRN9h#h;
z^A0Y$n2~jOhvdENT{tfs^UtsK-<7OSe}FNdn#f&arysazXR1E^SaNjPhi4R)otE3S
zd|}J3%Ldf(=Pn-Gy*+(vwkhx3lpIY?G#{T{d-QPU!o-S}9k*TR1?j7&>F@{L>GA8l
z+=c6twZTG4Kbvn>{X4vD>Tqj)><?S4cV$@FaIF8}hT3V>e?FLt>URdgUvF+#w=Hk6
zt)4e=>-yxbe>&Q<<g!1>*p774F8)$_?dCgEH%;817~N;p==VzA&UMDCy^~94t23E{
z7iNd@mt@~oTy0Z(^5@K_M{7Q&mHNxi@t$NG1U9dNZJ%D4*tT(C*}{6RW4%tdE@bT8
zdN@D*(5iu!$rQf}qww`0YB`u#aMzU|KJ%_aA4%!qA7$n~v}^0MD}QLiwHJm93LC?R
zd-~3pwQI>a&Gr2~-J5OC%!lN=W<$yD)$du<oh#4JRPNc*-E;44xvg(bRv+p#sfoAQ
zaN<qXnZa$j9(C`k?CP#ZdUEQK_LrO6+P->Y)brKZEs6B()vZC-@8(^Z{B-Z3OuDW8
z++1?_&AVnybQNb0PivjC^7PZY9=kT1JXYG^?az04<gZWi_v8VFO2hJ-JXWGYqSDnf
zv@V}(E$mOXS9kE_zh5Uu)(*6cm;wJdL!Zn5dUh<h>#O_Eyvsb0(vvGQI(T?%m^)(6
z8kh+GX0$KtKd$FCo8b#)RklvgZLVg!bw;(U9!~m)%sdVt_I0Ok`*=^!GaKjZ=}8B*
zVrchYeRu1`zKC<EQC3aQ^_=HF)xP@D9ogOQ3VLc6HMbR#QDJj%myW{E<no!leSSGe
z=G&q+)lr;2+*g~i_L{S@!HS-qV>2&E>}+{F5!O#r$_DDnI^Tq2@HCd(YMLVR-Kyyy
zlnFt32g7oZ3P);8HMH{A?Dw0)e4vII>gDa*6G_h8QNwp!NG<;lFpNs%Qp#pIp%JX)
zTOx+NW5)f}oIFc=Be+_k1I(#Qe#kY@LH{9t)7W{#m93Cd!L1Ma)p@Nf8oT*+S}xV&
zJun{KTJ>4;rmU@GL;WBNwV9s!-u<VU=)u1VgU|cQpViKJv-Z$$R;!0}O8Eu<`Mv^Y
z$b7$hvEpq@w=?w}Q_uHD#Hq28Qc|X&d^e32>6h6E2@i8xSF=B!mnp1j&RTFRa|iOK
zu_#SY`JHBE-!ni|d3K^@gU0yEk`pCU1)KGaA#!T^EiPFO)sfm*7OBA)e&#$)%^dk@
zj)JmH*+|_M)n<;XiTfdPKM!NSo-*M$lTD99%+1_;u)g-ImiKWo;S2kN)TYx|Y#<Cj
z!?|p#6`S5EWpXK&Gs+w7RK^=XhdCA`O7a@Wchjm%aSZn*!Xc%dfI}vH%&^Sh<@Zps
zGPg>jp{%u95l*&4GDq%wMRK7v$TCaL8wqMym366Bsfy&BDP-WQ)?f<<aV&H3vf_|T
zm`ci$$6EFqm~=xkxQE%RHc?pfdh)75%d%d0mQuRLG?iM*8^?t&+$@2R=X-yYODXEN
zftr4Im@Q<O^P^S6oC<PGKSOL!M|X1`4!sIk&XJYKuc*@nfFUk2;K1Usq84A(m9LG=
zp!*wf(3JGTK2B@J8*gv9^v)2T?%XBPHnu7S2{6udhTwqB%nb*cbb(@s%kUi|tYLoW
zO+*o_Q(&}n3pb&od}rd2S_Z_X#JQz{6WEC+k+FlCfZM3FD>@PgpEv4(c-B*mZ9J=0
zf#`n0Q4`9<xknG=mCBp+G^Nc4W+a+2HBKx+675j})_upvg^FK;<3O4f>lZJfO3juE
zW{nGWrjyg@vM7P9nUoZah%I1<H(DfidK$)lY45uqRcp?CO1_)+1IF5yp1JDLUtaOn
zdyc*1cON;p_q!{8cF(Ur_sc)~=sm}-+Pm`T-v7GsXZPLs<0Dt><-2KnR~_AZ%MCBx
zcgrKMU$OVw$3D1s<*%Q(Wx-2_ZhYkRKi>QDj~DO#qu>1WmIc53_Klx;?W(=2Us(L5
zSLC~C|8?0<p5fbN|MKm{U;5f_K7GsH-(B(eGq3;QPcMIA@0V5(|HLmZJM+HZzT=6H
z{6C-l-6bzQga2bs^#1tmpZo9&kALUJSN4AFvyWY|cgF8N_?eZzed66W-22dX79YFx
zbASBf_w8Nzn<w7A;Ai)I?E}YFJ@N8y7w^65H$QpznJ<0nYxCs0Xg{36_f?<x&&5Cc
z&etBXO=(p(d1bHGsKNS&z16AmAm5|DR;!w*W*K$Z%Oy=yOIYr+_Q3Was>~f&Xy=Am
z`(6{)YeA+?4KP8aN6%Bf(a=-vX?yxWXm^<Li@lL<-q5eA$pYVkSTil>t!p1nhW^5&
zZU1U=jn9>mOett-DRHMG^4`z=aorLg@KeUj>8~$4b51ZXOf2aiQNh?H93xujn@hu1
zJ-8xT_v#!KJQDb_ZZX3ZW$G6y^L2WfWH%4Y!=PMF`{n+?ll=bUQ%Z)J_HvU{u>T44
z|AZj%zOrJunkfzk26deRSNBeN|L<J-|1+8We~*#xGi|x{R9rxJnVYK;#-jg{nltPk
znbBE*Cu53YKpI}BGI}^vI>8sHysV~4cx9d$1m9D9<AYpX&2}$iZCy6r=%8uP?IWEb
zOL*Nc%gd@}A12_lWi<C(kVwd86g2#-bQB4{U%2pncArjNvtKqX=#&sz`J;u1XP3U_
z<CGTMkUi=;s6mrFx7Hgq&m~w$6B2s1FVbZ@Pd1wpL6Y;ThSN|yPS)J=P|~8!t=S{0
zh;W?jNwn-5R+=Fz^wnrc-Q)9T6n(%|8R`oJ5t_3+YoycT`{ta`<x!O%?lMJAkdZRO
zNk>jL$r(xu8P$hywoJa$iM*GmTaCh0S!G7hhia;j5l^=2e0J57h!t4PS-`=uFq>n?
zCTSrct-?#^xY43cr_KySeC2(Di>lZ>1Drs#P^(tvR>6u*N)_JhA(QoLo$MdgisX%!
z`6iW-vL#!Ql%0cCL@G7v;9x*2tmX6ca)AL~5VX|6NX`e!8CxAq(*e|iz!FLnc|!rp
zXME+FM-kFMl<~z9PehAT%%CEu$*5`bWvTM6|3qjgr2FxqJrHV6`RsLp2!)~-NWaZC
zE(pF=+EyhSOu(ScuYxBaO1|<QP>Q<PEcndbf&nFZuklS45x+%-`>gcgX|+YAj2dU|
zAseB7@X#djN(4cV2yC(AK}OAOY`$x17aC!IDnK%bAX<8dw!R^IR%3c81h@Xhv<R7?
zF!Bc+Do$m~$Q&UcXWJQRcq9fTskhK5YfC-0@I$ZKX2a!bE?MBEHX^VJibd-i5Njlt
z=|f3%y6>hPIvqb@NCMENq$0AG5utW9(<Tj^@;M&$8R3?t_WNp{Qr3b)f)SoNhJ9hm
zFwdp6s$g&ge6^LT<!I6%n+>#<q$qUZEuh7S3Y0^_xm}5K!)!pSw7fKj)=IsloS-N9
zvt{e#Gb*Ji5gRt^x+mL(nq$ZcL6DJMJsLEMP@Ey4C=41TxIP$pCP$kV@kAnOf>D6+
z#FX7Ns|>cNNy9sdE7KBcW98(Jsu5fPb(n+@;k-2gwGx#nKuQ8KxQBhIRH6^*lN>D#
zr6B$~m&~wX+~YBiFpxnEJ_@V@d99AJV23kFY9Np@B8mn(oue_3dv`8`Sn4+qkjJHF
z2}J5A$0?uFAQd1Sh%gXw`qf#~77)xbp)R_R2+i5^P+6fz5@|Pjkg`oG=Ga7+1qUo5
zQ7$!^I1eO27DK=g-;#IEs89RlNH}iy>v>m9xI@1n63|z`E(Vc6x-~gF?|{PNNVVx4
z!Y5%Kdcc}DB2oqhKS~Z&lf-GI^Px}>szl6}Z!jW8Lmo+QBtQ5$prjo=l2a6<NJbjD
z9E%jG$S-f;%TXU_cfLiT#04@=px0PNn8*Nha$-xcb}Jm{JC-CUv&m~oLj{-hqsXtd
z#-?^nJp|EyRF;kmiN%;G(nl~FaHq;shnsbzm0w0FmOd{Y><oAmLRIi_&lEep6LR?t
zq7Ly{iE%DLr6D=$E=DHfTFMp(1P2{AP$ftdWav%RAnq~MR~1DSC|b+>LlXuimp$zo
zNMssb_ykrth|gSlpp77*=nQaau<MXB+!BI=)<${&Pe(N(0P7S5f)gn8G!B_hQ`5(U
z@wPEq24HFb=-oHsaUrOKT)33T$2i$wM?Xuj;c!HOaElvg=A4XQ$6-hj*!Yo<@jB@Q
z06I(^_Y5Smk|r6k_b5<824SQ8s+a&i7vMZn!_hYRWAW!egAZSl#ZVE3afLGy0-C;1
ziwmI6#d+~7DMOkp{2dB$p=-abJg?9iL>LKRF?P%Gd)`WxFo7||_0i|`3j)7k&QON*
zP+m*37Jo@eJB`0eZk3h{xo$}N>Nql*&s&!Ri_*h&A{~7Wt)Dic4tLI{y%8^M3xClI
zvm+z8idrGKCpgR-6!QjUY^W;aMS5o;7~PtZ<3J!50w{29%AlC$BmvMjNZ4a5s*q3~
zmo3qdjEs?5z!=4#R|N^$ZY4PA^x;9_tTLBWojk;FDXq1Tr;5tF&O2Kf?R(sllm6T*
zZK6eZesUyakfbg~+-4*XEWO02h)^+X7I{f8yozKUq@cXX*Ao(*ib5+Lwe)}B<Z<c1
z*PhrKqD9|WJdmECEL>N2I7CmLjz&R&sCX66{>ZVfJks>w{QPPR;ic3$mhS;wM<0ET
zuj~Lbx+HyYUZo+M4ZjiUQm9iUa<?;+SGBPqEcp~9S~REe>`!(ZtS|bAHnVqBnNa;Y
z5kw_ltHPtIaA1(Zl%8?Khc+d*ZVXLmOPY(hmdAV6`ZQvo0I#f$x2V%6Z$qF0Wyhkp
zj(kOR8eI?QS>>(o_re{**J&}O!`-18-cA`9DAF^Q=8|1TpW|})+e5~YNKHsTszX(_
z1*bb>gPv*=b&8^4E*&iKH2OemwDr|}$XHOp+EhOn$}+U6LSbC;>S;l{Q?+QSNSH((
z-bYsINA3I4ToKV}N=DglNWGx8{IgLJ_!Cl<j1ERQv(INzBfB%xGx|=(JT3Ynn>V2V
zHLTR5p}z)KKW`TtXS-;W`GH9U%8sZWKcUr*!s_-Y>$4v*pxVoPX$yS@Db;F~hzVGo
zHqL=labYV4A?_NGX3`N7p#rsJ#K#slAf+GIfQBV0=-b4UKJKtM@M+dAG?uu(8+J&_
z2yH4S>UDD^p(9fo3KHc|4#ZjmM@zkxNaE^^8$$-K16QrV)D3@Z(Pmr_t=2N<p?*z)
zM=tmptkq<k`>VvB1RKvPL@uf2tOpR;)8vEX1s|cMfdaZ9E~!HfkkLWtOP*B-ZTBj~
zIFvK_1yLIy4XH|=L>F<8*pvjYOHksDn=aOYL?V8R#V%>Yp_77d>T7$UL6~uxr7h5J
z!PdiY_q9fx*D>(bBCYBdH3%|;lQs@`c|@?{B1-zZM$RNei1!&O2wA6E{QWqw0)EOj
z%zQLikuVExIlzNAC-Qiz*&{R`PqCyUSs?8;P@Ph{nHdzR=rqVQDYc=4L9qcU5#nA5
z0Sy(bFidH;J}FyJ@RzK_QPVY2QRZdb0@-3Lmb4WWXu%0N9*sw--9s1<)mYIOd2yr=
zSpr;Upm{ywFEqh~bpd=q(`S_|2|xiKi*}FfSr_lC!G70!ln7U);m{?c*oF;yEOEU{
zG@4fl(_9EkOy{iNVVu;jDH8zU<T&FjG$}USkW1R-)_;nli&$!03_xVjmW&|>#I5I1
z5hSTpexr-5Dl~l@eaxwM>C$y^dRP(w@Byf@(#?uEQVks#O!-xb)!1r6@EkCgj?>xL
zk3OiX<X$G4E==^K#Nd9Mh|&Q1(iq}47$C9;LmFw;0)cc{+BrpL9Co|d(4xta-3Cl}
znh>y0L6-j03w%*sJ)YK`jHBH!LRvT>;RN&`Bnx%PkC={bpP=JQxLmp**K$r$Q3%%H
zh-`u@VvUMJ#$G^+(aESRwwpPqX1NP8%-(w(>550HB%O^VumNLAyS2Eh05B2y@?#hg
zHby%?vj?m3pH!oXG3XRk9~eyZV>Z|U@23z7UKzs(o(|*tI(VoMUZZm90`;NZM|?n`
zz{^Ty5s-4zxV3^WQ<Fh*yMeHj2-SchHpv>GRff@23V>ur0%d!Ctf4bSrO~QWt1<Xb
zg(=VYHes6)5DB!LxHQNzc9N!Nv_%ZYv=Qo;2qG1RwkZ-%I8iK<LEgu!;U|Jwe#Si^
zLkfWT2xGCxB<WqkZIarEl)$BN5+|_aT|%`)NWoh8IcM7Dt@<*rH({yX!|_T96d}1l
z#t)Ek<`yVDE(C@UVQLP^`5r}_6q<!FZOtQ%q(x>|9~vwgY|Ba;^6v^$=vyWaB5#~K
zag!DvnlPba9sj7JC5lL-(He&)vgG7El~NkBBSrLFMDlNS%S<5yuou$6=NM2-+mexH
zMnxAvJy0+PguPLL>61L*4`^Nhn>1oYs4=p{3tbkvK5Mx^BUz5d;eh#YJl@2d<90^c
z2Kz96Q7jWqPlM0TjkILdd6>Q7kZp%c5u_@qC@F$uXo@N#T?3fNh;m(~iE}Y{4A_Mj
z#p=k~V5fA$kYTW5Nu|0j7N=A+@`xc0wgsg$j22T{F&)tOT>&|d6;$f{)ZPjkaWPpc
zxYLv;q=b@E6&1gN+EI$@0ikX<Fm$;##*&~Zt?LF)PkSV8bbqdc=u@X@LZ)PrZ~r;y
z$E5JAc%054265NMbwNTMm%z7DMPpg%JB6hTSPnF9S3syWAVd=xc{(PleABONU=?8v
zfi-RwSPZIpqbS5jT7w06?%|hq^@9yWB1DuLziL`ZlhZhXD6p<ym43rPpovEo=Z)FX
zsn9tHO;J>2Ro*yM+Ca|T>G{x4@l!o1O{xdNYgkY%loI8{8f!>S-XsX{oGJBP*-jl}
z8DEQD1V_S+;PfTL6pcxT9!Ky}8Hq<f^kZOKNr7A1L5u-iyaI%P>ngWPL$H=Pt`kep
zox|}{+r{f7Pz=_wPNdVcF;Q5^D3@Vv3>q-rkSX?w<c-8}z|_QpR6wK*rlh30uo9F<
z2_hN#XJ2JNO%M~y;;0+sEJ@Jsg9SN`hiH_P<`{!yuHU6kPS6i)ya?n;q(lMIkFuDH
zJ@G)*@Hi}yB2;gY{#Q3};!$!cz>{`M8I#Dy2)K1koG01DofIk~uowrseko2uh$zYO
z`#(WGhG``@&uTsf8Bg4ZiI;cU#DS7;T$-QZCt1#m%?_Kaob(iZCzGIP!6!Iga}$i)
zm6eM1%|Va2TvQXst}nzR;Rf<r`AoP3Ip&RHt;7am2*eKEa8)HpfJ2L#7QwLM>K$&!
zR4k_5E|C~T7a#^gVF(kAVH;~98NxL@VlGocNI40*OTQy_kp|ghdXYz5#wR*Rz>z(f
zT!;}XM-k$?cz<;jK@!H)!%Y_qZYlu?qO(qi@4^Tc;bID6Pl+UMq+yuU9`khF;7Owq
zh=p+G2wo#$!d;7ldQoCpp-AV}Va|pRHvdM0YGnn%jiz{}B%GiHJN{`y<1)-E@SGtv
zFIKILR}M(WIHLOUu{Sn#qq-PU#d(^FWoMT~`xJ<r#Jl@|f#Qi6lQIB9sswtLuFH)n
z2qDmza9L%wQ<mSQ`UoC7$s}WNhSob(zC?$v;E>XU`K;?Xk?T~E3t^~{VJ&RpNkXN@
z@Im)91&>cEb<5vEivTM~423a(BkT?70Y^e=hRC6qKuB&JU>o9Nk1%pzF`-E-_om_`
zSxi$fv`aQcgaFI0!cS-uD_+MMDn=3l<9)IH`zGiX5j3F<Je-`-fjfT3Va!otPUC5p
zDGJ*PhlDbij?uV`3!bo|aAG?0;7Xi&5L@ttN*qNXZs}h<FAk|SB3R=YqF^J~JWoxC
z9(=Y9X<Y2HJ7zwa>{KIy7g&A)jt0bJD9r{vWH2rYKb?)no#SY`2qH!OhS|RQ$QOx(
z8A#}a!B!M0egdSNiFCzQmQ5(gSwdu5pk<;PYYLx}o15ggG(Ran&)|>%(o3sAq5=Up
z;-ab0@Fmnha~DZs8i>NH5QHM2oynXQX2>4T$>8e5qYsIrF{k?PIKUSrO_8uT3l7zb
zV`Vri#!irshw}?k<}TW$5+w=53F5@?z)Sc^-Dy1Jtf;}1*;Sl|HtrsXiPufa48rjR
zdz3)y)Z86UyQ#%V`sgHv3JG|EZ}BbRN2kc%M%=@YR@%g={4#QpMF$Icpw(!;v_dHo
zbc&{`lBN+L<#-!oRYOGS?X@-q-_#J@I9>`B`;NKfn#cS)PA?RMv0tVh*?z>Zj)w$E
ze<_nWmjZ_`iDIxaR{?RVU?xcHs3TMmQ?A)lJV*q=lLCtK_u!3n9eyN4C2<nnvLQxw
z1Wu-cN#qw1K@c6#e2rmdG}74aw4hAE#3^@Vrp2MjlLUQn8QFhfNeakV%aa)~+^{W<
zG+Bj13?{ZjFLAG_#VO$7kPbpXR&}hMjPocSUgLMubQe@}!SFjNh6~7UeZSa3uLQct
z)2|0wq?O0_MA$l3dmi>Un`c9oDpXgkDno%PkAxjgdS%<z`N%Mj-lYmdR1#%)|3h<<
z@^1-B=P{F)XUuTcTjXsRDqpI3ylK;uqb*X8$5c&Xt<nYwnw72}mbrltY7PwNJLob=
zyrI90nC$rr6IC81Y#fo>ScPaF>#eQu*$c^Wn{WHDWKpbnJfbj{v5%e~qibiY{*sBH
zC}T87UZcOJD@=CsYQc6@n#<@_MULe>EHCyzk|!~DvRg>&t$&eeQ1e#l``Fjwt+6?p
zNP4EqXM$k(RYgD4=4s7gmRuB!CWF)6Ak!cDd3kVPR9x~Lpt_jywcEUo0&C7N4Sv<<
zyj-9TTB<674!|oaC4(A%OaD}Or<C7@U>9)}rPQ#g@=}|v^Yf^NE+*9QW2ERT)J%?!
zBDIF+I!p#<*0jpj7I^B)PUJTvL<eUUmHN#E=#>%(rK6lks2Wu;>|Ce{xqf9dO0Dbu
zNYk8au<fMwt&r71pfp*hogv~FY-Il6g<+MK5%!rGoJ&Dh%%6~bq<P4*f@3Fq6On})
z=`9s|)U|C2CFI=`bVPmBb7T8Whtm2@^utBcqiEE_0a!SkMh0;r5eVo|>H=wU+gpm2
z7LWItk<b0q*sS%{d+9^oXTjld9C-th`m`>$dYi05p*cus=%^ZHcpud|>JAJq367Tg
zmhYOYXo;UxEqohbH?M82DSKFYpfJj0%ZmLO$o6NrMTsm+I-AwQ*(l^-jJAP)v34!S
z4|$2tz~+!QE3!Aj9!Ea#l(7+&2-?&STO?}~dN2r8$g!b9_sadUqf~Ej_bfz#%Bt!-
zBH2;lz*SP_N0dS!TPF5OFRW>1k)2Vb6-s^mw8e5K<ngbFRw7k+D(Kkr3;#=_7x`Pt
z?;M|DK4BM?mIRB6*AGt97Y$`h)$S-&$J++Ze|vY~`b5UOv@u^oF9YXu=VxB?1EpCu
zYqmTb6wdc%6wYt$E<G^bWgZycTId_QYv9e^tkNGnd9Qg>wM#$cwXM&4iP4W{y2`7z
zoD=R&&d)va=Je>*)0);dZ)p#AH?<AyPBs_+yfsmrIjuGK_d#3qwBJ^IOKW%W`qp-H
zL3L4SZ>nv{qUKrpFE`CGPusTAlM`(V7Y??rTeNJJd1Xtm`pIf?;bViX0}G#>Rr-r9
z(^vmG(^fyW@lBH7H(kT?vF}7Z(Z4_2d*T<ZOZPm}y43Ey>n#Ug*|K!toy$LZ@Q;>%
zY|Xd7)_eHAJ1#i-=<_oUf8qHVYku*-(!+Z<|NX8%40}tTN_Uk0<Bo+V-aFRu7iZi#
z<CQNwHsk0oD(9VeeB<<i-`q84&lgg2PW+i|Kk?MpKUx0f{k_M#KGA#hJAXC(#NJu6
z2cF;5`}$X^y$|g@^vTKp%(bn5YIEy}r>d=^Kb_Tk;G4la2A+AaW8jI8w;wKf?T633
zziD*F{fj>|>yE{buJGP5I&0IMo6fzf_xK0z>Ma*$%{b@fYuk=|^X1+Xy)XA3>AiE#
z(cev<ee=rw9k2iC%dHnYbX|u%+J3&|_nUvtv&mbMz0r49%--`Ki8DsO;h$0e)y8vk
z->WP={Kpr~j;^|>H@g19-jU~$7wGLT_Ku$M;_PjccImo%Z$EEMGk2#~s5vL@Nnfz0
zY4e=Pf3Hki_x4RQ%1_;O!TQ(ln6d3a|AE}MZvW)S>37b`edGQICbRd<Dy<&tUH{nl
zjP>80Hs{1ws^_l1ZPU^<|9Q_ROBvOE{Hbcw=u;0gop^rQ?6Tk1zH8#+?R&n|-DIY<
zv})bfdpuJ){djj}uDQLvV|4x}dXInLp&8}#9-3C0ySa7eua`Hi>w32L=1)$}F28kK
zZ|-B>jHAOZ_1?U!K4;tameDf%@^bHG(|o0N{=}PJxo|^s<vNae|F!zWXw_>!ao<pW
z{q_}eD~}H?KKM{-f%=pEf2;m@)2^Kzn{ve?2in&BXR6yQPjuJ*eJoS@$LFUN@40iv
zzz;UhsD56}h@MMk){oset?+l7Qb*s*`O&W=dR1mxN?qGJ<M3kduF*@<57_O=gnGDb
z+JUC+(?%|Pb9-4gCCX>FrcT_b+Sk0Nt+o6wUb6g^naxM<p4oEXZm-2&I@Ydky}$eL
zu6ySk-ag)8-s)w7GiLi+ujx_Q{!Q7V(@oR*<fVz%&Uv}@wR3Dv@^<7~+;Lc(?SB7F
z&vwwew2givZ09^XUHT%u^Ph)KKlrT`i!1-yF~5>XD?2#$WO2yL9p~o!!1q_oJAQSl
zyY$V?QDxs(y~?VuZnyXN)70VgH2ZLvIlQd7`^4Y|U)|f(Qb{$<+V%r~n(a*arHk9{
zs4w&$+;z3hRM5e?E9PeoCmwC740ibSA?CxU&GaW1B>nJvZT{hxnZn$YNUXbiW}?25
zA-t5ysIdn#YWp3D!#@nwfo$Msr*BYOha;uNbD5)wl<Mi)lo&|eA5{{$%ug?2``r6@
zW};>I*3qV6JFup2MRAwMBv>Vm(MOJ6=D&4)x_|M(yZv+5U9w<R`C^+ceX#Gm>Kt`}
zzI;LVz=Ipl99_`fy=z5#CaP9?qb2PN2cAiH?@5GnM*DAHs_z;81Klxl@6OAc@6+dm
z=ctRlcJ+_rUFwyM+49}NtaV@UyULGjSXh3|_N-o}(yPDU8Lq$P<JxA%=BX_mT|M{P
ztV&iH6{<nDD+~`!YzWu4KctRzSA*f|w(Nn8w(aOA!(QFdGH2oQo6`eQK4+`e;*2P{
z>)l)0)bmQ+Jd*1uexNP2>ypm4fv96u_2ncdH&w>vPc7&^X!?8C-Pk{4M5}k1%O35u
z?@(`5?^Xkaz~@9^`_f&lL8jQPG6Tl;6tn(0yRxclpsq5x()f95!{Dsixy$d?d5+-@
zwl2}Bbi2(rWf{@3YEu1yNwo)u*V>-i)%HBi9hT9~=5*D&wNFJhuQH4!g$K7z_#1g0
z{kY7-!}Vw1l{+~99@TT+{lUO_AKzLo(9fQsrtiNY;BL%qJ+Ccbvc{Q64y<%!58u<a
z{G;UL+NeEuiPuzEJELv#w1TRq3XFnbD0hCg4KW7!zP95#bA{?oRb~674ktUUz~@8?
zL8acznBU^pixsv8(m4zH%23F2>=w?Yw?@ThNnamU)obdi+A@*Z#eB79NPlVQ@4CE=
zxXs!QZP51lW>wv{P^pcd3U=(fi?r#9{cGB6skOk&TdSIFN!rS+i3!y_#?Nj}*x=<e
zlvm~advz$BS>7J1!~4Qyafz26$TzD(Q|L`JH>=Wnv*F0;ZEB#YN3H2<_T)~_ciAIb
z-MUqoXe$RZB!9|A<7m$Tvhmc}c4?**b8~5At(pJ?<^v4nG)paKge+IA6mhb(W6gwT
zO*T+byVB+5>TYw9s=loqI#d(pKh+Pn4OI<uWN;bSnLZ%5BClIzRTlF0cF=Un@@mUk
z$@Fn2I$%m(u{yVj=l#r|lAFA3gBK_4v_53u9ahL;r!_P4ZdU6DXR2sWX(pk}m0;oV
zpnPVQEt3u03C{-C$b4p5Rt++D81a}dus{<uz}@*#3z?@BJR#bjGk%vZFM`rAkv**<
zp(S;#(#*k2mZ0QJUfj(6HRM}PzfqI}h@O}C(wVSxjOqyrvlP<%xGXF?sl|jjUzR&R
zoLY&zW@IvFfur%ig(qU`h)=Of?_;}?sZSv3m&p2uN$y!y*|SZoM3xCYVWo7G4g(ej
zT%(SvHq0%r1R5>concS*Vx|7+I2n`8lY-}MO}m%-!wmW`lRG~mqWr)>F6R;-(rU!)
zlQ?<vC6W<Va4}+t521vLz?f`Fya6JKf`&6OrXpRkn7_pFlaO`%T>3CDI03jCth&^O
z*jdJgj3-sbK^@a*C%a@%RO+CJsT-UvN%&DFa`Y;Oc}@l<+$U2Y$Ka{-fy7JQWGyij
zY8&!nnIyrY2bbQ_2ve5*AA%~%(<PD8(Qr64l!mh0T7A4h5gK{PSu6uSfU;GnO<094
z_wbN#2ch7&H37DDXFYIeI_Do@i-UxMbMT38uXt(iyH4KuIr_w*8((_nj~@NyRSWKU
z{T-kC$brvZ`ENhF?-lO+oWUKS&#nCR<5w>D*}W@%eB`PxaOdZ9D}VFT%NK0<)QU%5
zyW-Jrzy85zR{rjZTh92|cQ1M5$Q6%r@8+p*{pK_8{=(DWyz!CUSAA~vug>_yEBK*(
z<1=6U?&n_q)tR4I@zUSF>(Sp`wcx4O-u~muf5n}jm!5+6Wee{4?c1OD$iF`R?G;bn
z_sSx8Pv;KM%76Wv@7(z0y(>QO+7(}z{<{x8g8$t&{OrC<=DoH`?)*Hn@;8sKUhvX)
zFPZoHs?V+d?HSK--{|rM<o;~A19QW3-1+&;N6ye=ey3W_nx|aIn6S`n%pILNY(bIj
z16-I)Xcld{#>%+Lt2fq!bJaZbUR~j-2U~dV&K^NQ*)lH*R?}3nl-cCzX>FV+Ot$C*
zBv#S>maqX-2%EyQ@8V8gIv>rUZX8UvYn!&k{&p2@A4sdt9D#RcRR5h>wS@!AZ=xUy
zjI&>CQTps=z9GXw9v0i`b`HG%FN&!^i&b>S8NL<RA9%&H125tzncB&VFGeN;_11~z
z$?8PPx)L=?^1GeFt&IdSkNE!w`hQ3+)$;!UsagNGAQc*jt^a{gq{=Hf>W&Nx{vl4L
zmRV^fTD62d5smpKBf6t0(Aro{(;ts$t2OVdq0!Mna_7dktQ@sRW8#Tial|Q6_BiF7
zs;sC1&R6j&@46SV)TXnP4G$5}4^xa`>}RTe+3=_&Ky@1cq=JPs!ur}~WgJNr>@;4u
zE}zd@qf#|l&T5RYnl$RDR)h;@^|yJP1)vMCorKn@14b0V=AE3GAtu`7vr^tc7~T$_
zGm^v$HoWD`T-472M@fsER{FlMUs+JOrNKI!qhJ!1u&N3>!%mt_t4!JT;}Vng4d=rq
zLLOX2X}-)NcY{JT!hmVLFqdbkPnO(}Bxg=^a(XaQs3c41$a+0l)d}N#6j%{C%{M55
z=|1~ZDR<5s@rPBQ754x_=q|~7$_9ZaW%uiMQdbu;X0m^4G{PcvX~fDf4Txb?ID{p1
z8J%445TeM~NJcb`m$oXA#VQtl5z`O3qs7@(-$=Qb&@W-R0Ybd|fS?vLi73A~1XKFv
zU{LZcRYw)dvN!0+<12Dk%mnGWdn|>20@)~*vfmu+f~_QgGYo8lU~ExRCrL;Fv-xmR
z2x?I$`x`1(AuQb|6i%J#>hUG_vV|9+Jr6JbsiayNYFT6A0C$ED$si|=VIeaC$^+f{
z*g6R03rx5G$_^)fs&bb7I^`P)C6U$QkTX{m-h&gl2Oos+e40QIgvS;FWW&m^MmblW
z0*KBvHk&Wxo!6q_X75GH)@TrgV#Z>jJ?+@Yb5sv@p}Jav1=b1gkapwLV_g_jph0^D
zI}FN%(GU9c%0L>PP@rTg)N|2pP1>cFI0wYaGm0Q!oDIVdA%hgM=v{}ZTBf>@9DHlj
zRvfNg*}H`n#5^svi+9%G=6@H*)KRXhlV}B?Gf)-_r^YF7<;_pT!T6-z>d=adDWCxD
za*OhGE42lW#c&{Z;$Uf<$GWrD0W={gHz|ZZ)sa4g`+0#T3-GoZ$S^V)Qr45u^Q6I}
zPojY+NYmy#WC2HD7_DLj0ckabLp|cYF_nX4RUsZIKP~x4iYPJ2ou5ALhfwn!)TP_o
zp?nQ}6y+I0^|*_|KyCu8jDeIpn4w~g09`3#W%yG>0U<6FgUdIf7|v_jI8LgTOjtyY
zH-c!P=mI<~bofUEIQnOUAA=^5#wl8rmRg2%oJKk|z)GWb*d=kJ2T^dOhH$9BVu;X!
z$4oS)s-12mg7^LL)1ocO62R2Sa=MB+X#A`d_U3GfkXEj|S_2Ja8i|z%M}8QKx+ASo
z=;7h(C___akMC^Ls4Jwb#5ki^ra>5|RNo*k4$4NDDbG49R1;1$5<~_9&YrmpOdy*B
z3(NVqV!tot`_3ohC=&4INC%7>0@j%<O`IKR7ecOG^^fDkB%CbAAi8Lv8;J2Qxo5-?
zH%Q{fGFYyj7Nz%Ya3xG@4C=hWqOAI+1a<R#3;zacRpNyfWmh&z<B;cafpg(;c!XNq
zF&=hH>@tqKlIn3PZYr-LZ$LOQ*082<8QGOK1UN8^bK<c4oI^a44e_{otw|}e7{2rq
zcOZB<uS&ecv{>Q*&$wd31y_qDX=sLGan4x+02YE$4WvLF=-;!P6cWUWSZK#b1brNU
zl<!y*4(juWNLYhPn+gg-3;a<laUO<5TE!lP2;j-%SM1O=4K3~0$hQH7j+8H{DUl*L
zzVTg)m`j}Jm<C4L?-VSdd_@89avA6}39}C8h%3lGm}<rlSu#43n94}|?N{NX!PDo<
zQk$gK^;68dV~CJdD<oba%Sg!JZj`UwS_W9{N<5(X(LP*zmzt=h2CJYh@sW}4zeP90
zcN9DoD=zTFZTWf5B|cTM&TR_H(?#$FRnvB(u%&1yOWq<vNSK{lkA~?*;iH(FD|k_Y
zV#Odx#$cdJ8EZ>{=J}Boi2>^n&wB&D)V+n8cnFp?)`OtR4L>NHW0l(bHt4Ce<WR=>
z!1~rRT6Dsg@aLS$9fbciDmdUcS}8eXvE2IwU&!!cKC2Q=_}aD*33y(JXr<0EL4dZR
z|MYYPlF<y$y(5}5VV;^`x!b6y4>e>I?P&1J$_s2B2V=FS9MxqW6A?c2*W;(c1iVL}
zQ<NH|7TP}L8?6FM=TK#eP}bm&Gd>KG70Sn;XR2W^O#Vlk$(?pQ0!xda;QSr?$PbWf
z21!(BtY3!nk$&9dS6@x~Pm@<XTC*EO9u$345&3*%&Z3NUzT}2i(|{_+@QkNe+<~=S
zNEmk)w`@#`c0>D6zF~BeN~1Xi7z7jSwSkuAs4RI|E8>#OTk8i^Y%T4`lSw=Cpfc~#
zAl;<rx$y$0>zj?(GGu_Slm#CjGB`*RYJ8;z9SMn*wxOgi1`FvJza)yE#cDu2(u+s(
zB9Vg8*&wQ+DRLS~FA4!iq67_^(%uBY8MvKG+OQ*oZTM+^C&3HUS<V9~K@wud(KRl(
zVZc{U(We>_Dm?{S1>0hj8f2f8kXSC72J!<9(dj1w0}aAp+5r3xv=NKC3mxmmSDC^$
zbl~iUUT7hWEV^ahcH%_i23vsHqK@Nfw+Yq{aoPRj#fs6DN(s>X_#CTqN<JiQR^-xB
zlgO7Y)?B2;v^q>;Nv|p(y_*>pjv8M~E^yjdE>%>3&Ip<(g(smVKp53%)VAdMllYyd
zG(XfPcTV80QU;^SuZGWPUXRH5gO_{^$@BcMDB&J5#U#1!Oe}tZl64kybnL*n6+uE5
z@R_r5XRByw16KTOMM)cGv67N_$+wT6_CKlAu*Syi8Xk5aR2npKx%|jE#cjgDrDaSM
zm%Cf$MUp4ASt0`NOVUmYN@xdLBs?Z06k{;TH_`~uuqC7{8V0OO;fSYRxuy{!ZA;)(
zYS%7ZSWGvNxRL%iM2lsWGGYtBrp4vMI`2tiT%t(G_+nk4EdEY$F)qw0njQoX@5gXK
zQwC8ah+JU^8m_opnzeR5M>|#=QC6talUqrq@$3IaPfDFwgH_=NEws&Ap@`e1#n$}D
z9AjN3>xo-7+TRF9JX3RVCqQi^j@O0QcBYO=1=wm>Ii41$<Uv@~#XSYoA_42n*wA88
zhH#2C28~!Yi3r?3b45A8q9x>wsUNQ?Rd^Sy$QQgE1>-6mox12y6J~JhIF%&`5V0Io
zVoNXuG$fdj5RFR$84EG-LEn*=EjfWWg|Lj<wbZMEM4%>6tT+Y0u+AX{MbM}dmh>?R
z7pawK4b#DtEri~Hq;!LKjO9y|b#7<km8=>G4qUJp)Hd^b$rS0Vi+3Y1a~AxxX!%o!
zP;o=c2yOw%Qea~-YFY_6Tw@Y}wNr#C9OJs<NRL=`03?GfR<O1E=UEqSR3m=l+0a;a
zhH#TVS8b#mpOO0m9vUMD?lP+JWMn=Ga!$#C!F1tLRw}HE-$9Jb*(V2Vf2fjHu^hrb
zzD&ehF5`FvB2<J@><5xo<DTNjyug7`fprdNh;H8i;ESwIYENoiqvwfvHjo=N9(sBz
zX@fQvI1QnRGcMk1Sk7ZHgCXS8%_(tfe%O+42L@BJX89R@T(T5Xg6Neg6N5{BjWv~I
zQN$I-rp_RMO@YhVOFu7B2Dh;;-mTXZ2_z$ePq4=M-$5Jb30N@<Kj(M(()i+sG)^Wh
zcLzRxevBniCM~7_X|#m9HX>B=;uq~$EC)d>ifu3;Oyl&cBA<Zc7^jZ|9K9*0&|w&q
z`pfR5^d&M2^SwA;$Cj9;Q6$t2U;IuF1&8nab=r&I*tqftcUMo#*mW>0Z@Y*|G<F$d
zMaop)fyLBTImT;oPe=zPVe-ReYH>d6yh+Ctr7$T+;o-0-pjc$dEvpy!;SexlXlDjQ
zI&2A2b!VQ$6Jm_VevM5(Ln>*221ROU4HH-3C&&g%e!@><Yi23J)VLkjmQc#_sd@M<
z4&`eM`JL3B^GkvlV%N}=m%hq5As&v!Iu^gr&xpf;mbsX~l<uY+Mg$aaR~@F3xH2KR
z<;VQ&4d6O81+SQ%mMBM4jJe_iYRsL&DY;ai3loVN%tfgJ6S|R6+?sx0qK(0D01vH{
z<u?WBT0mx1vCDa_qiW0Ip`Q~l$fTL^I1e-=caC@?K*zRq81NC$jjNX8wleo~si#Ot
zJR}05obVj(qdb-5B$ks@j<=NMejzC-4L{;X#Bw#;N@Ct=1%hm_T8U_&iNlIvelK?t
z@&-8BFS;<t@l>o4XPnPGE|EYPd4G?=A)Hk_uM}4dBB+U-I>x{g7o5iBG>a`Q9gqc|
zBMR+ogQA4HFipHZ8GkaV#4F+itf9>L0fE+-;7@_DswwA}Jq7WKhtr-hFadYcm<GG3
z7^ijF0ws=2I%HjT7IJa78vJ-WsgcmYR-&;_f+nm6J)R>WWrJli{fSbqUg@wHlNx!O
z5{O_aYlyjC$%;ORb8?L1Gk#=wjv*+@cV=wF2vcImkwv&ltVV{DxYAq(!6po_k*5u*
zT=JrDf(2Q!3Wy|;Bk5*rjU;ixhDXp&g2p9;+_MeP`p4s_#>CrrMj~BUsU!o41J61u
z;ifxEi$_?X7sts+fXL-48RXqsOzeWhSmjH57g04*I`-n$;2A*>U>v1fM@V3ue@Y5G
z<wgLOwHTZ&&XL|pSwk1NPtm~*S$Bs@oOTC{#3A1`z_R>UHw1>@KHR|LlS*B&5_-mY
zq2+nFgsO<D>N0jXmjuNmBsSKPLlS%eLGV=CDkHw4!*{x4{R=v1j*g1s@!^fh5TzxJ
zgGO6zj8;>j&X$g-0d61>9lA_Opb=Vu#b`jHE+M|fXo#qB%EzB#u6P=$8-D9TFc8d4
zNf~=F4Zj#%wL9sVa>RD2;nfY>h;7A)VJf~RUM<Fy)p!u7r37QJh>a+*W+f9Y8`hBv
zG~p)36sMHqW$*hvR(XOOV8r&~(bp+GbaOU>-5k1tqd{Aq$0_=3(-=41VD9>Gxt;Hj
zVtITh%7PF9jp$zdtbLrk;uLTt5*PC+ojF9Uw8MC#aWZM0Py?EkSXqQ=aWueJai*Op
zR%ZKC03+vdF(rdUC88{L{~Jgc!fO0{dy*ePA^3oG`wT{6w3Pq{T1H;O(Q|$-^AaDA
ztZpo;OE75xVkCc7&>1Sk4>*Zxv0M7aJ{KCN5U1s5rjY5K@C)(;wgZ<^=qgXj`AON>
zkySh4T0#Rc97JoxvNDbfG!`MQqmuNF2D+6t#vuiVGi6M5+LFwL#nHx5cR3)GzQA(H
zgZ<CAen{!S9fFc3t|u{*$i(d2`#gl65wYBJoW>kVd<__Hu$=P8-gwR>LcdW|OQvHM
zU^@pPC)YELdM2{FT$FH3faO%AIc=i}5YQ4v=*gkmNN9?m^mnfJVU`0Ohv1Uqj(6x?
zEm2BR6bU5K$>A6}qrs1~4d|*+1`_3Pb$qAiE1R7dg5uT9xH|B5A=O9}4=x3DpvAp-
z)MzWR@a_my{$Xk~9NmY@Nl+n%1{kpQ&fXiI`4mS%@ReSJvaQq?t+;<Di<K~KyGYD6
z3OMnddE&xm4raPCh;&XRs31{YQnQz4R3fS}N0q8nB?HDs2Sun+)>Q@z6X%`U=qXzy
z9-_8FtY<lIq>_x^yb~2%+HFbtZ_W4uZF%v8W&Oaql$R@-1TWIa+K1sOFa9yArAllG
zF#+kpV;AZhmTgVns9>2#4YM4$X=cq~DL3$S5Y&wFwW5jF34!O@@&*-+vIl6aS}Rm|
zIS{YUl6TbkC6X`H32z%OWMhrwO_nE^*?OrmO@X;;R;sWq4l?eB!Fh+hXcGPlg#_{h
zk@dD^yif-wu!P^ck^Vu{yEPuN>+dvp_y^?9kNOW;n38A9Z8IFGl1ul4JjTNLtSuOo
zamcdUY9+hq3N?y;btOHnunFh(deY^K4<}vfq0^jNK;MNtyvB$a%2UIJv?e4))Gaw?
zZ;L%vCWFwW)O^1x{TVSfqH<{I!fZcD1ElcnfTD~ov4(f^Af=?AS*Pp=1D6KB;c1V(
zM!^r+wPmgi4jyZW3~kD4lGl|yC+iZS!4^vmLsvMJJ(ZHq(fS7FRvjl*9uoB;Q)vjv
z{*qRKnk=h?&@Y#iZ_7%p9VZRx@~be*hWlSh${qZ{z$XH=Ce<!&GaUIz%btf}tPhIH
zA2orXWvk?s^IGKUb~fAP^&^IJayF=VTF#NEZDJUnuc%~@mn4z#>R7?ufhrF^m$f^*
zMRF%(8f9I$sMD`J=CvKzkytc3_-v+d{j#&`IlFjr>-ZvleWJ5aczbuf#WvObYRAC!
zt=*OLyjf=Dcu?xDrg96LySKe{u-A0k?8wSzgUUiPt6CgvD!psG%XC+#S1uTAtqyqL
zTJ8Xiby@ATR@ZyJS+S4!XS?h`LRH`DwU^dx%9xRQ%I@-#lV@+3T`doGahEDXI|?SZ
zOr)c-*KS4=UG>by>8rQw2$mea$gh2PFjL?1NHF}84R&zQy;fM(YhD`9u66#a{ayO%
zS*6MG?7<)Y!&~Y<*!LF6@0ZZ~fe+l@QM=*pj*;)bxOClf`<5QO^x)DxZ=YPc^WX2d
z`RF&t{_;fPK=01h7kk6&@1CKre_+O%TgE??TXgHE)||Pmcg>r(^_I@w*AdR$*V=N+
z(OE10;@^5F|Khpnlh^O-T$4Z4Q9AEX@7nGcx=Ls5OHD4=)I0eF+dKKz16}pAU+AhY
z_y=xq>^rA=gYB+<G@LW}t9n9yFO>FObztTGt4fE*x}sOdx+Y)SkgDIeAyry+&y26n
zy(d$9_{U9afBxg9*FN;auH#q#sO$3MuXa4Y^3{&lzVYSW*FL+yclX&pNbUalk<`|M
zKkV4?>W@0MJ+klo`jLNdcYc06M4x&?l&CD4**dbnzI4r(UpzOrtUlWgzSvvbaO?TC
zvD?qvnW)d^*E{mQ2WIEqclYd(Gi-0^hVkCq+--Am{rAsaGxvpABmFP*j(ilIeC$AP
zech%Rlkd7?#+rFw?_IO#>usg8JinB=sB5y>&Ylb_GbWeSyXu4WtZCgRdG3m?59iQ_
zXG_~&Xqp^&p{c%Ve{22Hdb8c<rK*R$uITO!?Pk}8mTLcm&-XW*)~@>3rnTe$+H}PH
zu<Nio(zW*5FE_1yb$`eH+Lv4F)%~r*`wpkp+E-KgSHIt@C%@NQz3zG5&~fo>xfgTp
z-_e}v2bvCFXWGn;i)J5q&%W8wb=%rUk4;+?9cW&(?p8Y^9LjZ-U){p*g{JWP^^ODi
zZ9NB@wsoz^zc?c_W`<hxY}TB<FE=uGeD;CUE97aisXA{>qB?KHue{}1o~?)3$yK*!
z>qDD5>#g-!Dtb}bS;kj?z`4n}w6dM_QHe^o?XM*2XRGP;$$FO^G#PuXmsO9Bbsf>S
z`cdDQnml_VX<nL0O@8?OvyZ%bWX5Q1hrheL(Z8vB*kAIY=lmsqyRk`KvoJ|-<MMV_
zL8%?vccj$Dk)(aw;Pj~Ph1m!CzdF0}TrOSxia)zNQE4h~tap^}*p@wf>$6F7-GR1|
zzpl2eS@1yiVB)~^Z9^-jSB5g#1N}B#KWA)asK;ii`PH6kzSLxy5SE7OYJ{^3<{HXs
z)wAAYRPiPg2b*pGi1cstvvhHDZB&=>xY<rO-tEcye8PuJAhFeI#kbpSrmiMb$@|~!
zoePv@S6S!xId!V~R&}LwySmcpZaT@n)g7pW;8emR%0qWmH&ERP!%ZiO$f&nE0Rk&w
zMPV3Z>6%@Y78}MHFCC+Z4pthXhVY1u1f9&9b%VGBbXZM9Bw?YQh%QB8Vt9z7j`REP
zea^k7p4|vC<68TxI%j|T+u#27xBvTb_Ici8h5O{OA@^mMdvj*!*!E?<mA#bj-~OiD
zo|wz`w@0=dyMF($9qNSN@p<8Uj4}7!HS(^z&gAW_w-@u~*nTrL{A{GV+;_a?vi2)(
zziij<=Z*G9IWFuuKH>hYpK>nS+aAv*+uM(GWVv0(fn80u_Ost|#p&;Si*4tPDUK^s
zu9eMnZ8pU>yhoceOQY`DW>@doyiau1;?v#bi`#EHV8%Xjgj-o1?)hBBb<lnDTaFzy
zBgcF`bZ{x(@~*4g<a>_rPS%m^;xkjTd-u17Ck}FuJJURV@&2ja#Wy|5r<=OP&iRRB
zBm1w)is{#mOpf1nVEovT-iZ5AQ|O(Z>;D)R@A5nB6T=ra&6_#&{>&9#-!(UsxNqq)
zGxe6scy6`P9OeG_=+cy%fAdxDAm=F=U-DGlnBjR2WfvaqYJQiWHkbSTh9`F0qm8NF
zuFP_-GiA(w%DTIcXWbqAXv@Uto?dhD>Amg#>7UYl&(8c<aoBAwc4wn*A{%k}=+H-&
zhPLptc3W=B4o%w5=tOZe+k0>*yLf*$+i4#+JBy>{;$Ai%>c;wFr?Y0{r)Ph%XiN@`
zH|F>)zs|v&Z?%Wt@%hL1(MwO6EyV}T1&txzgI*fvS%6V$J~r(iY-IC%Pr_x?mg+Tm
z|Af!<81r&t`H(BjaWiu%@)pNL7OJPW(!Y3E*=0FLVpzTF&EcNg&v|>+^LZ|GS+01V
zMfREDUT%YXzUrIOZSbs6W7uZ&*&)g!&CK%b-y-2%ENKp)iysaf*RmBlD*lKuXXrid
z0LMrCEBLPLv6CjBULrrb<~nY4-MCm79t&Ak9MU^K4}ZlNyMw#m9o}Vck&qR>IZC}%
zC2X6P<ElC#-$~W|U9B=Cce_~_InGvDw$gC13>lsE9FX@E>@neaM8O-6*>=XqDp?qJ
zw>Mmu{GN4j(Fyr7leNqYa21}*_p=$#(qSK)yeq78Gv4)>_r0Nc;ye_>6CZAf@kjxf
zH)etDN-*asNr$V~I%9Q)>xNh`_>5Io28Q0~cYNOPIYgi}n~_G*jUm_k{v|Vw1<KPs
zV#+>Dbxb%5Z{%A02@{@iVW_a$GuKh6@doyIsGA4vSg)yp`Pn76n}T+LUU?GG&aTC#
zEzAzeSFu-_+%>uKqUZbWYv`RH;~R~!EE~<|NA+AMWz!#=n>A)}e)99ProhYM%%%8d
z0eK(c;;|;Oi?s}#oGm5`^(}h=4i`r(n5q)i4x^Ga^iIz&y_7h`6*<N&=_@Fs$Ew$o
z4Ko1+CmlAgX(({I_lJ2ReQNY$T0c8;yXh$np8{DHpDQRnha{weGp<Z@@q)g^Msp~)
zjE#&ERcuMNVnXQUgxsshiy;f-HLjF17VRYyDHTyTrE(HP>$Nf@oK<zrGFwcikg6_-
zbj>!bjSb$9Ah=43K{MbWV>9S<vPJyB7v*(qGUCA=PTMq_$je7pZUm(9pJSXH^h?rR
zzkH9->(MaAkJ3@~<yB7oj?d{6O1JDX^VcuF`}H5ydo>?==pNI4-v@8`;k%FA{QghB
z=EVJ<<#&GW<(;0pk9_|FpXPUb9(nKm|KZ*{f1G!E9(n(#E<bVS$G`ZV>mIn1cY0p-
z+5h!Nm!J6gkKg^S@4e@95C5Ax`5m9HJ@uhK`S{(Rzy6+2J^a)=4}bPok34YyAAafX
z&%gAZ8(#WAh~IPnOJ4n<{SUwQhL7FL`$iu+a?d}#<nj-`>(Cd!??v~1>NO|yzR^oA
zzw?XN-2M8$y!VDzpSbgpr``YWpL)Tq*W7*Nv+uuwvJT(+jO*h&KcD5Do+p0(@TJfA
z<X`^aPw>u<-s$<;pB%pQ^Vj|54PU(Xt1olTw5aSZy#w>6yJ(CBW}a4W#QbMZ{R^GL
zUglh{X%2n3Fo)<%plW!8t1+q-fU#ZMJ>NXb%`k?u?pFV_<|tpAZqDv9oaS{iT8{H$
zrk~JRyZZRbWpCBo$1ftgp=P58#GbC;hRrn1Grc&BFF9ko=vh7@^hQ5vy1qC@L&lqe
zy^&_q6U*q>jJ>><x9w~(^P{xxZA@dF1AS!KjC7{Z;VXF<W`5zXxy;R<WybxS&Ikjk
zz90BZ8L?=Wth(cX+<;xp4TftiMd19iC|fxQD;w(cXQ8~7zP9-AZ0F5P5_-4b#n+(A
zneor+I`twI{pcL{h{C~!3n&h2Ncf*e+US4=`M69$ESo`0MnBUScGeSV&^tIIrBv>P
zu<w%I&H3hu+@6ik{&5OwnpW4qGfU>&8IA##kV(#ygsfoC3rTEHY%?7MAf_<(@QsGM
z&NHtE8GV4hrF1-FO~<*pCTX6?*EHuOUu3<Ijmt+_Y<CdrS`FktdZw*nl%mgUaGgmJ
zkA1$`$~@5ITO6{g&v`b@65D=*%i%F>UNAGc<F1vRVV;olJk>@0s6^3Rwx(z=!1E@L
zrFXu;;vZ!=w|#863pQvSGb6gLh|uih6>9Tqs25Vwwp^G_i%_h^_!PqdQrn&Sura-Z
zjDtnixMo%pmg&%Jj#|O8XHJ$4Xg&s+Uc4^g9qwa-$y9z4Q{2(K2#>*sY&`SGQB)M_
zj?D5G$Pwy3gjdm)(W)bM!xcX(%_*}#90;N+^Qqp|gR&@S+T*c55cg3e%dx&REdOkQ
zhWu`-VLe@pU@N;wxtm5EhtyfEEwf^eXjvN%N5|Seq!9cmOMPcJbRa&iABbc8L0vO4
zmSP+sU<4{!28o&6Z^Of8MF;Pd3<V7jqc(FP8brHhblnBH>`@w3;$UgfX{m!pnr5A%
zwtML9y#MWxX&XYzQJhMo>du0}F~`U-xwptf9a$8S+0n?9;<Yz(M(@nIzza5v1b3uQ
zZjGcvY_c7Q>y9jtiRY>>!$u}Us`EiXr3WE?SaDwHRdbu_<|Kv6YsB4B;4~%ZO@a^v
zC&<V+bXn-mp5nMhNAaP6SYIOtAUyCm6e`t)56#3ST1T4YUtNNk8s`JLD#**8Bj>cn
z5wyf5Ky*d;tRQcz<Y{ZB_c>+E_dBG)LSgO`&u@{0(tMF?xnR$1kH22h)3`*{(guXx
zeApBg2D<khvY)BnX?YllekB<6&H(d6NeD3SDM9`kPLQPIMidu0jT@3IJIh-wicmv^
z`bZw+%guor`ou(Gwop8mG!QF$g+4?ouWX2|-pO}g35#e|E#h-WTPXn~_#BZ}nXZRM
zSu*d<8%spW7kGA|%;2>+F+r-7SvCnQn@IjSF<v`Zuf9hvS#zODe8>=z(e;6;?a-D%
zl=McOs;K;4qDW3hk3M-_YZZk|DuWexK@KKrSja1LJ{@>=HZbIQ+HVK0kOuk{sn)T5
zvqjE3iAbW}G0+iLrC^b(xwA;-*us<AWxGg2WPKC_4`YQScG?9}LQ(j6+CzEDd@iJg
zo!Xxv0EM)S@_q0p$Pg2QupPz|dt)UiEd_qc#rQl&7_)+cUr`cUh<wh<zmVc%61D;~
zrIgf?Y?a^2k7h<7nrz1~?(wKydKs-s%%nwL-}jRmIMrf8iDE?McnQ3A90E(;hmZqh
zW5VeyuJlZAm@4weKhCaj>}&}K;w(-|Vf-Fk<eOb28y9oRZZSpQ2clphq>!hr5vboN
zAw4+75uUK{6b&YpQ4~l%WNh?!<#%EH!pseM^~VUG6au+8n+2Y8?Pf1<{bcgTq2$$@
zA*V*k?5KzH5?Cr-jbCOii8v8<Ay8qN)ie`*!CT}!f*KDIo=C77{Dij>KpJbg9PQ<j
zbyN~M)E1%Rs8-fr_l}~4I0ukJbGjpxK315t85e{`wTIBpHQseBa(NNaK;9XmjYB3P
zZl0ZIgKXGucRHi4pyY~<Y)j?&hY5>icGRs!R*R3vhNmQWmS=a@T+@$9c~Q3H)vV*^
znuROAjC)BMGewxk8x!2a3w6U4`F;C{YpECqU_Ri&x{0(le3vzmGGi*I%c^am=5=tF
z=VtlnaZt`A%gsJ)OgoBfvG%)9mi9XUwz$DcL-!2vWwP)MEb09Nhd%S4&S#oijUlR@
zmN_m~S(BL_SEQWg3OwWDjE+G?n@+r(9~_ys_y&26nXQ=3Kf*mfz-g<KI;;?Jujcs5
z_f&X}-Ocv2axnb!gdoexF`CDk+%|f8huSEwXLP9@&0X_cD`64nyy;N^j^NyXGkh;D
z(@PJmpIQBLNIOP8V>-?7&cZSBk=9cWq~CP2p~7`YUi6vmTm?h96tk^k%zyoaqMTjo
z+|I)-V#t!eMn0^R<e7^(Ls|~sg_CY`M-YXb2gi)F%#}9E^x$RW9R?t$-SC(PZ|Wrq
zFVA~%IvENzz?SL~rl+t|YRoT-&Ww0TLIr3;W8s|6l?da+Obj^!a-kc}ACys~F7DJr
z0x6t|)@8d-y66*znj}SET={|B(7>flB1rh8ro<xUaAJ_#F!{ljomsz<NLc|fFBM~K
z$e|8Ewouxf*gmQ4_WTvm(nn`C%`vY#=e*6BFFfTV*g{aNhePPuESr`>P%HyR>&q_P
zARbU-YxvQAx$$XMols%Y@!P2s$hd$O*i;%69zd}!I!<Se1r>~=0WqsH|08LJOoeXD
zD&4F7H4l~)j7Wv^XU=_s)Q5engOhz|Imq@Hs?K0i{$n^u9f!iIps=CFsCtz^0`a0y
zSQ2B+(HJ4AA9(VKeA6kASD3I<gtKBTk)BL74$3}JV)$BwI`|wcB^SA{;tRcdnX=S&
z*D?%`>xWIH9p-(wihT4k`XeESIloA`1y&(nZh@J~P3{ns#3^NPCTdEELlAKn7_yJU
zX*^l>!Rw%GV{&j4EWLDOEP@Pgt;t<!H!P`1^Gapjv{gAl-_f%?^3Xg;M7WWeA(-6B
zELWF}uI2VgZ$^+(5e0|XtOS<KSm+OZ3^+s+PGXO0rpD^=?gq7D&Scw;RL&z0K89+j
zdnj(m46%=gH)l*+3RY5O+omOY<&G~*=6tM+Bf~HMj`C5ELuZjKnp4T~_g^ae5**Yn
zP#p{kvBtEJ%g3ClmuMseS=RKXWnG3OSS8GC<X!1IBF7d;dUdj)QIx(%VrQ%ZQTZ5~
zE-D!2X|4`RYPB=D4?)<G%sh%+WT2E4j-9t5jU5T%omOapLI?1OBdJm%9YSs4Z17pf
zHu|bnD`FF}VJ}ypGO)UrM28B3#Tc}tsdR}mwqSVD2UbzhptF^hjPtnI4vFNhq#>RM
zGfq_~sk<UQwBzCrgf!h65HUOAfEPQ*M&Fe?p(^UfUJ+?zJd6_ggQZPpY!t9Z)fb-n
zb3B<QF61<Ilg(qyA?lMWaU7;RS4wS8KQHaa+#!Kvx-aFCj;TPzD&L7~=s_Je()+b-
zv0@oergE&}`r(w4Y)u^;gLO~Y$jk8q<Jd$LgKcK<ZiqVVIRtC{68S}Ajz}f`E7`Ix
zGBe^R)xeV!C<mNHVMUQ13B5<5gEf{-J&7b>Q%WEk;xXBs$ijU6o*S4OghlQLc$9kI
z5pwyk@9!*}>&GIaxMzyeu_%t(vTS0OE!gugBKa&6L5RMKIubTG51J(&D>*H0P~i|M
zcLKpiJ~P1{k%){d87*}psjbvM%QmaT5fmTPeAHym0yQW&ylLa2k7|{%7$Xr1^F(Bc
zS#&koBjBHzF!s-7qb$@b=7fhlo8pz{97l--F@dcnye3DANE*M)6=l_s1$`TrZ>5f<
zU^+!0@%=7}B+t~A&%7lhvKz_`$J##mz{Mj->64S_;K0M6p`8m{IrtQ@K@f+KiU%|*
z=OoqfR)^&&c-hVExF>)Z36WG0Cw5M{0uB8j(734B&@Q7r7cd`S$xqcPt6T^pZ+4(B
z@olbh4wVi9xkkH%eefv27>jG^*L;Xao!p^BjClh_WVMTnGSi|aAzs!~lMB8D9gmu0
z6Zu${6PvNKY!&&6DML%>@)%hru#q(^Zyc;2OyS`@kT1NjOqZ8so0ZP1Qn4)!Q`RiI
zK(jFj%OsUUUkx;)J(GzmLP3gQ&p9zQs>@<|`$@H~QYp$}`reRYLt<D9`@ohG7bDtx
z?Od#**gE+^TUG5+Pag0pn#~O)aDpL_u;@p`RuM-R3mP`;%UvxZyUT1jTffJ`uOw?3
zn_fDRSV;L=i8kg}8Z5h}IZ04Dp>f%HvE(I1Y>89`8K{-a({-!f8`N#)%WSR;`-b~*
z7#kzb&>tdO?fZgC?n}p92$@71zS33M;hF{pb4P#dhEZoVzAI<ry(Bpy?5gn+DpM}x
zo#b9S$oBIYCqSx}L2ea`<IT0I6pUI~uCkTm(UCQh?&wA<Xc@;=sm_VvVgd$2`3^Qa
z1TPJhJ2+rS=mt4+FBK*-w8UsrD=3U22N&b!2R>?yt2L4v32C9m?>h}oTlyecqWqW^
z`ioeLNlTb(SCS)i@(;=^yD~p^Og0tb6ex;H@#-|G*n)i6YnP9@!lEiQFF{;?hvR3|
zjl!@GXG-RvuZdu1tMMMXO~3C1pW}{eN;<a_l|BdF4q~K3gI*lwH6L@kkj5^@Q(r~!
zxlR~}HYAK|^nRTB`MNH=i}6mCX(`5SDOXG^SJxtkEqx!(#qtYrHYZ8R3T-pI^Yg;D
z!HYtVA7*~`QY9S&3IlmSaByBDr$!mSMB~Y8OB@DRc^A}>AFrW=Zdq$5PAU26$b~)j
zMS0k3$DHf?kv=n3a$1KAGpD#`TV{i7*c)d<s^X=8lKZ;-tSqZ^+{Sc#L@-!K#yC&x
z_f1=eW<@SCTGv3HEt(ToC$ET&?mAe{CW@==V`9S%IWh9f6F7dHEcoJi7EN*txL9G*
z9ZGCjVV?6pxH_%mIu(j!p`8s_dBr`Ob7j4QpIjG2JQg8RG71BXf(=A5tXcyksAM<>
zQveGI7t%dqku_$2V6+R@UCWr(7R)4MDeXE(O2tb_t0I!aMiDGXVjCm!_=U&0)M7fe
z6;~gOL{3*}<X(2<XZCA>i4ioAw~2V(74d}P0}_N-i}qzl`3cIx1W=h)1}w6b>a6w<
zaaVap6e8WrcC2B4K8*RBOH$E9=fp(o%`A61Mz>0z@S*Ze?}5CGXIh<fxe4!=9F`C2
z^MQq5B7-%;eS1)thR;2ZDzxb$a-A;y3KYb;QR5G?mTxs#D^UPr)N6HfKvN;dlB0+~
zwYNZ6n9OlS+gY0v<5`K*s&&)t!x`1eHg`IQNed6TOZi;`zKGCM1T5Wogbv#_8|`H}
zuSM#(Y(8!HPK|FgTN89gbmm$ab<W|+ds0*RX}g{0Fu77cCkXgRTV^STwN8A*&2(+>
zfHeFuZ{DWddIa-~4(i|@Mse00I(^g=CvQNwIbmiOnJSjh6;u;eP1fcIV$2;_n$0KL
zvUn0P<hJwOuqVUl{FP_tQO(1LN2iDbw(I5j3@$ZKdJyXXCz)@fPc5m=0F*6bTPpyE
zz9}d@Tu%z`^gP4py1!ZOWXN**;=#<!u}~Iei)3DGnGWYaDyoG&eVo-1@obk8KX@Gp
zwqeFFdNVfSf~=urm+_d&L2Dcid&4O;G7K?ho0kV{%o5)ybpSxV#sqSmTefyM#}g@F
z?05$Ze!`5=ho(6`EtuT3f)R|*7}FsggC46+vx05qJryQ5s55<wG)IKqop<@>m?5(@
z-C53koQKs%_qcn7hGAxNEh|QqNAK5ZPcGHEIH&Qj5ZF@Q0b^z?eTLN>{i$#ZJ((bj
zzG1wWJIeF6MTwUicO&)T`Dqg6fN9@ua)M^_N=x;p$cI7xx;}W!_lga<0jOt42d5?C
zc-TeL`DN3z^d_M0alN5w-pHVJ0Xn-xg@60F`R_l89<pWfH$9*Jbbqj`;~t`m{Mo49
zfw4!g-(%g53I8kmF7kgq^)!3*nmx92U{7!4<VF5X_g!RO!F9Y_w&y-Sb!jhu{AvD*
z>`7)D+uW(b<fjV1|F#|eiZjHQCfLT!6`fIk#ciW*{=}r4>+UrCy0_auz1tn?PPl8j
z-|em0<!#n<haQ@62bP{iyy#A~#@pG~bC*3bfv4lAv*pp|!j9a`?wN4@zTwkLzGyDw
zxmg&>-RZX%?YEvPW?HjjcA=BEAG)vLJ)eSSn}<wmeoteD`YL|up>6Hft1dkArYD})
zx$$e~xtpFiPxWo|{^|!ifBL{BoySgH()qK$e`c@q_gD8``NT!Nqi?*R@#v#3F`ZKv
z`KO$EiofO8pVE2xm!CQDns;8(Jap=p&G@Nb^b031a!0>%p?T$FqvqzvM)O<Wd6E0V
z-&}1vAGm~kPcjQ%x$xli@4ot`7yZrd&aIC>$^6Bm&+*wKdwZ{X`$X?mdnU~FPrabI
z@b;!}eSN&U@9(yqZauR1x`k6?A6xjq?AvDVJJeoy`{Zqper?FTa%tP?SNd)3h5N?a
zcRh0P<1=49f2RB8EvFy-+Hm{F{$a;Mzx$;vbD#dgmfqjIW9R#Sh+g`)FCH_0`{HfA
zANYsi<v)MpWu1lpeV*(5pHN@ZdvL4yv+bky^S`j$-hSjVv;R+@=NDdmp6@(yk$Ld<
zb{l(guYV;^m%oCeed`O)GuOWJNoJI~G)`S&TBr6p`}hTB;j!K3DBFu~-(jZCJjXOn
z>@nBgaf#da_^=y#>UMX_<2&4oem!$XAO9X>AKB|)wPT`p^Bwf-cR#(`*)!SP_jOir
zU(c!UxSL%b@6F!FeaKUpU)a;^ow>j83x2G5bZN}FlVj~G-!akdJ~3=&zIxuwqrZ{6
zBfoip|MbU)-S2*BxVQYso?ra{_5Gu3#@(l{8TYsS=7pV+6VJ3mckE|u7JBE$ykhx6
z^YVYVuygb?7j$miby4rJ2hKb5=vCWY@6<$Z@!j<2ll-RFf7@buzj>*7@B>dVmU(2>
zpJyzFTPIEL6&=%CI62|RPj2_;pB!;FFMp4lKl2pxf-{+U<r#i2yF2MFJ3ZvGKNxlA
zFFmQ7eRBNt?D1Xhz+Fv0ci&{Q^%jl|hbNmierAt9dU{*iePFyjd-8nWdK=fUk2hu(
z-00&A`N)|AOWZSlEBA3flAV6*Lz8Ctp`E9fds~|y{^P=b@-V-Bba3eO9g9PD%P(4E
zzN?|Sedjx<-z$G4Gf%!@w6m|9+58t<{!f2_``>RLb&sAHGB@qQN1J(nGBb<6HQYP1
zeb}_R%t=dxC&1>rOz!~c+fL^Gyi>X6H*?GB%gvJ?A2vg0xX1fg?k;<j8L>BHoF6vx
zeqUGD*5<5nb1maubr*BzXPe!r2X{87K9+agJQGTH)Y#+aH(SR|kEv~j3DR0$wDUW7
zB;&1PJ=1HpZEsi4E*a1Dv+mp{vgX7`hkFy(X0CfXla!hKYiju1H^5!Td!18TMofOo
zdB#0H?r-GmI3L>E%YS>X&wpy%>>C+#V^1$!{$u044*e(_;>qNxao3ufbe)rX&FEO8
z{qlz{>b>a5PG_#a*kyk=Zk{^RY-d+ZcC#Pd)-@-#nOXC+?m~Vw-=4hMOfNT1lXkk*
zyySG&+|$msUtwDI0_^SXwf609nh#uPhB7@(vG+9JcW<|*3-j8mcABFTySuMDv32H!
z%#BaKeUcLzo`;>_LtQ6#y4gvNL04__3sVhqV?IKy8miwrpUb>NZT-F%u+n)~!3FqX
zKj$WWcA)V2)`p+kw#&a_3(s61CjVWmHm4i>meQmd`!)1W^1J~*pK>@KH^Xy#JlEvC
zyS`x#zqa8IEwlc&JeM)Udyz*t@8SND$*<%d(UpFz)o2c#+|4n1Pjex=q&aKOqdBS1
z6m`3bw_Wv<EcpaYw#&^@$5~S}PoCgi@Dn?lyzJ23IkDGtr<%>}9Cs#J2RxbIZsI6o
zvS)GKYpUqYo}^MYhu`t}?!PcvLy>lzwcT-JmPWUk2OC>WYmE1nj<Z;x_IhE2UtV`Z
z(<sivn_*XsavUKwe>*nE#!YK+r@7GsVq>RyK6SBP3k_B>=-64-QYyqK?}%@id}d+$
zh_z<ew{q+Ep>4Nk4j=F1klp38@t$WE=;hMqG2-p{a^}Z<i}}WS-o<{a@gK(T9>?#F
z<?!2@TsFm+KVin*l$q>xIAq$}ICk^fle`DBJXZw&DZlw#XUzG_v}cCT9M4QE%UGFu
zGc=E*ECm=ge%R$EpD!%yTHg8LHwZjqi^nr&RpGbU@Ej4wM9xw#yQmS#@_^ctb=Eq7
zZ&Cd%4V~omj(Ep-EG+2&&7nTiS7UvMVsZ{)m+OpO!#WzDSQ}t3%a^IYH<5av*~P16
z^baEP=9uXYO%}@^&hw^|2bMY&h0l35nN6g3e%epQCrh`@8q+49HOtw&=}?X-LOU8W
z#q%b-5oB`Op1V3Zl?z{C<Y%bD7dtca{hsUamTGe4Ur&<ip$63G%81xN81jZbRy1%0
z55qGn96OqMo95$1GH`XYZbO=Se3^GAl{drdhUEy>Jds(YiFQ6-(0;j@>xHOiwFl{Z
z!ts1)j(M%4Jb;@0)CXD6<2k@KueDPRDH}OuLwRMY0#yQ6huMX6LdRATmhmy@*dUUQ
z>vMro-L&BDq2?vIiOn^|^~q%<%FH;qD;q8(Hx#vj#g2OS{!-uwon;rvg+SVn4SPC#
z84@_Laz#a3<AcD(VySg-h-hU}n%YWop}#5;izJ6DlL&-?HjiZ|7c5(c{5I64Z>R|l
zj-)^{>>b7W7>%Cf=Cq>08$!qC<0i8mw)PM^^(c`Id+kEQIT#-|PN**bpx*iUa)!WJ
zb3gCZ=$)VWcYp5iiTjV-b3ec1a|`d)%)gKKZtj2CJ^QcM@A%w(<fHHAy_=tV<h}c^
zzvpwe@LtU${FV;y-F)#~ywh{*Q+em-OZ?8y&mF$|Cf?~ebh+O7c|Gs^TyyttJpA78
zJ5;^%^GC1wRlU>maP6I+f8?E>hk57c#D|XDt9O2Q$LGkQcT+aM^K(DH^P}JKd8yv{
z`ML6)AIc8z{M>o?*4JJ4zy&{1m3`;oOJ8^0JwNydx5VG^Iq^B(0lMy<8^ChZJK^AG
z^bQO^zQ*Q=E^&-ufG^Apo8Rd%VdTu&98bsY<3+fs-R8**kS8-+wB|CiwR@o%0bPyO
zA{%kVeZxZ9cNmj8m)EzL8%@2D$Ad5&EL?`M2e&rIGTzA<eQwk88@RT`ONZC(AlC%#
z!<fGENlnccnzeFIfGx*}w9G^1G1`XLwPu+|Sq-4Twme32<>p`~M=xhC;F}<(Xnl-Q
zZG-Q(Ez>``8j*bp_3g)2GnlNX>Q}M5AY~@0Q%$ulj(lsa=qwVyVS1IaUV-ZAtO0*4
z1pS>um9tKLB4SeS9&p^zzHr9r6qGsHnu?sBy3#m-T*LAtnvZvG^$rI{XvJ+tzo#)Z
z&lH>IPP&;jZ5@ll^J1B-qG+)XIr>j<%PSVfn6cuw=Z-x@`B}pSnc1(n=eUhjeTH?Z
zR7}weHk;nzjYq&YD02d?qfCVPr5R%AZ>6-{TuM?A^0I#5c)rV#1(^-?g@NdUz93XB
zha3#aI<L<iZA-m^MHGHoDK0#NC<8f$i*4oEezx2+dp+v}>8OCVm`LieIu7gF&K7uG
zO=bat&ZU@e2r$=kKIoY&=Etj?XFP{>Eyxy&1qU?MM91my-pH-bP_~BJj`y8mrxl0r
z)<qL63*d~^k|NR&2Xt9cyJLrtu}FqkSA}vNIb%}e*Rq8;GW;t&Gaey!!#*5$LYsuB
z$_6T{d0X{?nzUXPp1o7tQG}y68IJzyMxKJS_8{B13U^|4#hfgl#5=`=))a)9HOqUQ
z-tw@>NT;nezI8;)kpyy9M`}wPYv@=T#Et#LT<|joGYEXkeEd!%alPJSL#|+pN*Kom
zZS(9rFO?{?INWH#U_tuc5gMOyU8nE{Dt&2F7B3ma-&@GMnNb>fH0~aGZ78RdNJ<aS
zVwAn=6DjtH$QLxQu3E}5k;2>wGL@-OUCu-lE0@XwJrz~wa57rjb!5>Na#Z$==P$Ik
zRf<u}DinF`)Oo~El4-bc_9BXsWBQN0FQgEBrEMhkiVvuOZN;dUDk|AZoq?a;N5v5Z
zvSp=QrrWr1k{I&Z(e@*1-{67-c7SK@OHIjZEGp4+Lw|!fZ(>;qSvm!TYBSX1)7KjF
ziHAc%d?`q&s?EA&qjbackX+7*rN6>*bNy(uR=-+JN>qYMXqB3^DqiK^ER>y6->;`9
zY%6;;7}rsaT9xiP3Vl)C_r9>tRIRzWR$m<^XsW$_Snqh0@xZB{to3L;%WJiwferVY
zX4o`wLzC+z_!YvnEpYZ8RQmEwy0lR_8_5T5uNv-Eg4*ks4pcG1!n50i&R$ZLIrgA1
zi&UbsgaMpBxEuA4bMe6UODa$F`tdN@2gx<L*s6K@PE>*wdg}^TXlxc4_`lg0i?#Qw
z4XM3O{JXjob9{#yl2`cM6CWmF)=6A9%%i0avs`??M{#|DO@7D&@>tzZ;kq4C$T>Fb
zd2?Emaa_y6a5HPzO`i@NqkXts_Yt>oT^~!*o!C&vZumYP_Gi2bfmoE}`jO-ikq$>`
za+A-AsYrHqeI_hs;o`BUWwa_GX4#qZbuB@R)ql={N{2O88@{oWH@#AHouV-t*bEG+
zS>JfoEuN2u?;%)J4N`^VRm61_vQBe~Y5jo@z<ZF$o4ve)@*;*_nIY}0ER)nBwisIX
zYroGjY#v#l?%75Ih4cyD_9Jo{(yFp77jB>}P9+C&?0w*ZZtx>U&uKrfKTuy`e;__*
zE_&)p{pe}mU!<{n=y%C0@)fgTh|QR-)TsQfTDrozlA~rTWA(CW(@GpdrS&mW`%NxZ
z>0YB`mnjJQ;9K}UDQ{`}CkN%`4yo6<5tiXap@h8utcaK8h!SpkadANuzC?t{@GdZ`
zY%Dp}MuYOZ{SsNh8%IWn^9ZzJUqL?t#hq31aW6%%SvJ%>d&g$9u9v><==KRkON8RX
zK8vs@dmui6H6tcm1PzkH8!tOhN8`_#>@Bi~tP#e#Qxc=eD-0!(L%hg_g>ztHnM?4!
zV9)hi1QA780`q)kfs(v&k@F;H$_E3f{T}!POsVN4EK4Sg(#p1CmQAEemU;TJkPuQ-
z8s`i}rBOkGB^$L!L8nTOvT8pJV<{r91g@X0WSDycsqHo;TQ6a{R8@Vv>06JLaY4vV
zsMm85lPFTCNKB3W)mJH4l-;6cwx3kli^}avUZE1>$~_=gvE}h;&?Y3<D$(e8_uNN`
z`o5^n$Qj4B)+vv4U0SQUuG&DjUWWB#gB*SC9M#rwzi(nS<5mmS#A(byd#*{X1g>HT
z>wHaIvaJ=OmAYj?gL>|KgE5c)&lNeoU6JU-%072)We?mxH~nv)*0EYq=g_Dt8h%~<
z;zw#0SFk+vLfb(r$0_$`R;Zml5@(OI>qU)kFZSzVQo35DS;cXyiYw~1`v$1OpbC|>
z&U@n8YSI`DvNgNdHoq6&Ia`yufxuCTZymZDjjL~6393dN^9`zH_HUF>lOHR2Uz4q7
ztM<^*cs=q1VV~_YgESkCQCB=LkZjC(m052Ux3TUyq<m|!uNN54x$2V0SD39$=}T5l
zAARwvX=NZ^x6M^fy)SH5ZlxE)jWzozT2uTGj}!efs9rg(l{ce)d7CM%N{ef*Rl-$K
z)w8Pes-&|-H}5ZNZPsfLd+mA_>RL4ifGV6Xcw`#^wUJzAIGHI)?X|p6#lE3X{;sW8
zWn$x$N`uhX_-`Y-9@6U<zsA9JvYt~-*Ee5D*A!DFtO?a#pWM8?>f=cHqs!|!zQ%Z^
zyE@_A@~+PHFBPxjT^}EH`M*@ztL^$yQ1@enj@s+*?pPt(P<Mq^J@WseX7%#F_53%E
z!A3r;?(G}t1-WkAZcb{i=U?8}DXrVS;9JV*{^$B*?%Z2^v#~j-t>4V=%}i{TZ$;Wh
zMg~5tQ13^od{x*_s4=?2yaB1b9(r#`Ty0^)JgZE(Rq=oQ(aiX7VI?-QwUK<&qSan6
zThTJM)VGpW*Qhn_V$X@K8uz;TTwQ@KbFB#CI%?44G`?2!3SX(O@Sqf~CyPn4F|e~z
zkEhN1`3E`@4g4q-)&%jI??5j%OSMY`QI5^{zb3Z?I+v*O%P$}D>(X<1Jvpoo<(Iaw
zUh`$xB?RV}yH=-o!>h9UzAKD*OwZm|76SWC@7y<SAsP6F5%}qQ)@G>=pK50)JWwUZ
zv3a&S*%0vz!9esVAGv-P959vLQX!m-)H+#p4W8u8*ixwq*2`O^`I4#5ZfuB0pH}57
zH3xw&*)s2HpOo5n(U!VZAlp@$6<aC$N~sL(s(2ZddS#-2@4@?+sstO^ffF%4UW%)r
zpV#<-K^lWwv&Y8Ojz4rmRJA<+XU(!L3T;Jvjww9sxX5VExL=%;jeD)maW~0fP6j=9
zf4j__Gu#NX%4ZEbQlcN^v)r(?^49s7*Yv^_2z@t^w-uV0<*_9munqY_UMh}Vo=~$q
zsc5bIu~xV1_(2a7<{|cEo5}Mf`7~lk^Rx#W4+(lU9u*`r*~oh=_!NHaQ1e`Pmd?cb
zI1}>fNl=wp_o=K3HhFO%!*Ygk<)uQh4FuGQO_|wvMv=ON`s7YN6^+7s{942xELa>Z
zeF7pAt0AZKJR)`j4(zZy5^O7<$0u_0lwhonp(;lIDwA))>wB$3nS3(OyB>EOcAXFY
zgmy9#@VzsQ*QUnn5=<WSR4?O+YNJD00tmcRNRh{=_F2j5{t#m4Li-0{=%F+u1`7HP
zu4$`}*9-x~-VrEoVBppM!i;^eOTob>C9y%71#1)ApE4yn&PLrK^0MV*W^=I`lFJ)*
z+@Pfz0dVRmz#DoMAm+7FjQK)dH6d*jGOJI@y4qj)qEDoigjuS?&Jk*p$?#PL)kTHp
zj5*w*H1COGLAI^f=u=25U8#*%@|b+cDYJw1@+lH2;i+S_;~##t6qXI+qUF92Mji<q
zxxhY{QUGOPZ^J(BgbGw$LsOAaX>H!jk|?Tr2L;94QCzvJnDtQ>>p+TCJg0w^a)KH=
z5Q<X;M8RNuz9g&4l-z4qlC79BtouZdt=FfYulm4V$Xmk+6Lp^g4z9H8ePlx3@|l;q
zPoz?GRI<@?<6@T3KdLe-pT_DXg>1Ic4)ZdR3WlL7VcjsaFvv!Gwf@AcayE*2M>bKj
zWm?@^iDJ$&aZRu?HRg@Is_I*7vh)RmysOJxCvORnQqEqNei1O(Chtn0R+oob*`?R`
z<g1nR#y(Mo#_Ml=uq;+jTn8_0DX4;~jJ~|`qiX+^WmKtE_UK#H{`J&BzBT@rnX9~&
zt<@ppwG_#2-S%qDK|Iz{$M1?_zUa-srz*7`R(YeWR$hQ2=3U|Qn)V-*+PB+p=c<n=
z1>2H)@z^cfK(Ri_HuC6`dE{V7D1GvMEivKvTG<%*SMxuN<><e$t9^`>801@FdsRg3
zEW35vrQI6ht1{J6>iOzgwjSy8D?QyPZ(lty(VKevOT1a$L0Xk}rA5*sM2IW9m1l#z
zv8C!c%QUrf5LbC?I=<v%`>P#aAKALyntovW&Je5oSgms|@oy&Yx!C`g(%B4~vz1xT
zTlL$s<vEx1x?SmK|ApV)Tc3(@yoOHYN}WMl_;qs)(rcX&&ANP@j3Id=osHx*JFBZz
zOWKev&AJU0s)T=zapm1OpQ}u-&>6I|+dw{makcG1-oEJpqw)G5V|7>O8z_B4?N!gV
zhTm+Rv_|>=Bf)0aoXyR8-c8%$Y=%~)*X=4PyX#k0Y4oE-BOYJ-2LZMC*~U(luDQCJ
zug@W0$hJ{CS2p{e)tJrFYHFLXZj-c_v>LOsW<WuC&Lv-6r)uZIocnmK@>Jn^zJ+$Y
z`e#Ct$`fV-+`Q!FIxL<6OHlVq?O58kN*hpk1CVI6R@trRtun?uD^h}}S{qb(2et>C
zEm?B+4OD%Lq(M~%S=NaA8A(|OD;Kj?DJxCZ^ZKaR-;-9l67y<5$nE-ikr|{YF1tm4
zjkK;`vfXbR<uT3Q4*_|7VE!plLLecK5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<d
zA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%XfrLOpAR&+tNC+eZ
z5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%XfrLOp
zAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l
z1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_
zLLecK5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+
zBm@!y34w$_LLecK5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbH
zKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA
z2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<
zgg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%XfrLOpAR&+t
zNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK5J(6l1QG%X
zfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y34w$_LLecK
z5J(6l1QG%XfrLOpAR&+tNC+eZ5&{W<gg`<dA&?MA2qXj&0ttbHKtdoPkPt`+Bm@!y
z34w$_LLedVuNHwl=7_0iCO0NCM-LsCvoj@$xl;UdZawgV7tJVo^;PU(uKvy-f8F=K
U;6*{b6hA$R8wO+ME5H1I0gb?#KL7v#

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/hit20v3_time_limited.sof b/FPGA_firmware/output_files/hit20v3_time_limited.sof
new file mode 100644
index 0000000000000000000000000000000000000000..385b2606adb810807b1f8a59e891bcf6f7d3ce16
GIT binary patch
literal 3411934
zcmZ^~1C%9A@Gsb$wr$(CZQHhOO;7i<ZQJ&=ZQI?qZ5!L)|Gjt4?w;K|bt5x>6%n^0
z>)wdW$SM^DaiISS!p{d7NalwsxfwaTy15W4I$PP95sEn2Ia=A8ITNazIlEXn*b_2w
z(KFFA5(>Ln*_slvb1)JzaxpM7GcYqUaS^IW6Uth-nh}bbTDku40)YS_{U~H&lw)HQ
z6%uFVWEEkT5K{pH1uFW1Db?A9#5oih8HJc-6;$M{99#&cqzJ|AjLl3<%}js3-oeDo
z#l^vyP|V)M*~`)O2Xk<9b#!y(`9FffqCbMF&Q^}LW^^i!W<LyKu9jxb_GbTwMOZ|P
zNmffm#md6o$d*vm$nk%R{@^12U%2>B`N7rfZR{O9?0Kkwc>c!#0q&}^y36VZ$AiI_
zedmeaK*&IbKL&gwyg+<>|4*6ukJ12r{jc8tFNJuK_>uc5jQ<gVUV{Is!2ihqS3v<n
z{NFGk5aCY?7>Kjp0+<x&>K){N<NxdYf7H~><;O?^OCuLcdSfg5AEcov^lB&3KD!+5
zKjzz2PBS22tpA!oX<$G=|7#=-%ztjJ3xlPVD>I`z3%#|e6_97vVdka%20QAX?`vvE
zJwaNk7;BuTz&xi8pvr}*cNJSup}$Q->M5!T()&ah0tpGWTFYS&rh%)!Bx#k8al4Q6
zyM^&)ynY*vCoqsA#tmm49OnY1Vc=Qov<MH1)D3VTF3|0P$lC@Oz19fiY$678EZD@#
zGG(l<Vq0A+4f%EFBXNPzuLC7gV8?|Xt`az0{M&fHHT~FruhZ2b6eHHvBtonCbcF-o
zLc*NGLjyCoH8lx}LP00hd|PLD9#Y`C7*o7wymtdVf%}z9rJnCV>uB4C9&W}M&d7fb
zlR%4JkuI^~m&~h*^Sgc1A@2HB_B)wexAQ1dC}Zm2x_)UB)Fi_ZgB&>fZ(MJR9~*(}
zhb@fP?;J>9b4ocVn;ZK&Z#9%J(ezP8upY>!Q2u?^v}T@?y|2x`SM!$3tCdiaqjwAu
zpkuHT?G3&5jZ2x=7s0jGy0LV5!MM8>R&FIRd{4Gk&!U*6QnZ&<SsmQ0NFqGM2RRLu
z>rlq8?RBb?zJf5}e$+mUP^P@7W}-5fkDN56=nm!WGyi6{PPWc{!7xnj=1~g`_{T-(
zk;7rc0hdI}7GCp@)YQ|_<aG9>&u=R{ZQh+a{b5U=CW-H>%_Axf%#Sff2ZsRLh+|fH
z7AIx^6v_}GmWAT3D87``@S@t`y8xbAN1;2mbAN*Dht>Bd2@@CjmcsBW(ims8scI38
zKo_?#=ir%Sg^@wX0X$4OT+5Cyp~#FPm_aNHn{E10{gxBSs&u+|Jz5%kc4dMks>)VU
zEK9H;Qhh$4x|}VU6(vL<&c<4fY>Elzqq&WKMRggN{q!w=F+(~7M=S$JHiJ_<f7w~i
zEE_wNn=OsiDO$MtFk_sX1=`J=(Mo>Gd%2KY;9My&#=3Y}b$*j_e$#M%kO{gu#fJKP
zk#e!TujsE0sx{q@+H|EdmIX<REH07bN;YgUHq5Vv0K;`{fxmOJ>C}J4nTloog>m5V
zE`&;hT=7Isxa+i+U9|^T6`1E#78dnY<5GE>yRWIK^(;3H;7IJ&&xMoZ(haZA!(9L|
zXpb&{8n!)`^BA+KKeKo+F2~DwHZpL$>jd)H#2z>vsN7{+sa>iyTJD{w)mrXd3zg|l
zxL~PWD&<;Fa^Ge$>yLSSC;@8`#(bqQ;Pu>PS5Q5+Li@0bLnV0M2suF=tBY+Tw=vpd
zM$pp}kFuR?G;5{Lor#&7zC~x9IA_NT0XJV86SU&pxnP&YfEbl(JP&N?5sK}*BKuAH
z9&AVDE`gbeDh{dgO50TL;1e4{O;#FyH-BqOx$ma?IO_c@djQ^F@Wtk-B^)0=0>lF`
z+Nz!9+!aT+cPFTbwB6JVHeCUK@7nR=AW(i<jfowHZ%<F%zA&C$Pn4Nk+xKi8vQ2LL
zVr75TI|h_b1TP*rFP<HZ?YFerB%o9(4exDo1H3whjq>xg#B#u=!CHlT+AGT^8F2e;
z1aZE?1>BuQK)J0}iMX(Ejz~q~91y<>($VpH%3z~835@8XMffF#I+-a{<Iu5PuljK1
zo*zoYNQ&ziPU%ki8%E{iH`V{$fe{1$|2QxgThkv0wv;5K5W<K%bnPEeVgS?uY7Ztm
zDtbs*=E=ll1${2wOw&krhAhyT)HfJ9M7y^S?s=X3JaZjTR{8?sVEQWT5}mG@f?)yV
zIm{}IwX~48im3O(cwF0_vT3*DR?-9)L}=52pyRTl=z&<gDqU4R`;vVVQ9+M28d#FM
z9`<~y5&_s{2eYGSgHp~S_qeC*mIeY@F~a2si&a7foFEfgoDq(+%uvj($2P}IK32h>
zfr+yYhJP^taMX1U*=K$g51exW>exa9;-|=C__B#CV3`Xesa>RsW$tgq+J=X96DIxG
zO&gf2MH`hdRT^*u81)R5=qdG;_TUME0~=+L+aHZ;8+10~1BSJX9k%<Z6}DGnD*)Lq
zeo(%kJyEI`pUeNn0*e2M1*#}NvBQ|b%8}t`?3h`Z%$QjijTnq<T@8Nv2IfY_^ezsL
zCRX<54nG5XiKpX}$@#?BBb-^f6~;a6G*6zJ`Kh}h)s?uawUK_xduvokD$AruZ`GLo
z^}GaL*B2-xNL!kbZW@fpjUjc6n@xh}_VsB}9ztQslVRn{n}j_j0u&uuZaq9OGVpKh
z@E=0hcQ@w=EGz{5F?W{WM3bH&rOeB%;+)>voZ72?Ize!4M*eU_!BhdUj*c(y$MwU^
z>E00V$p>JI$I)tCW(dw2<g|(?XyIAzW=3Y_(H67Qu~*sa7tDeq+7wVkg*833nrj}`
za}oH%;tPi7GreW&k}V!bk$It8uzzl@<ndHvbF1EBQq2JP7i`+Ip;bi=JYF6q^)KUD
zj+pPz;?;0njCKCCt$%BpR|x(DPrvTWp3OZ!DaavQH!WcFKZ<#&;PjaAu~k;YWiN2!
zjX%Dm=J-6F7CwpD7#wOlvPrZ94a#SibMm~MYER%VaKU3=&{$CiJs$g;`5wqUi7%~U
z{@@4421^hmq5BGd4;N22hP;xYL=l6z#t>g4&Pfn0>1ZnccBhx57pmm#!h?O&NVE_5
z9@QV{qJ&U=DWcmgZdiOc4i>?al;bb6z&S>k4Q$!(w|U8<%_&`Xj{a!3I#Xm~FN2@0
z`eT{fLdQBXns*1QCXcw-=BlC&m``pKS58aPjCjYamSF59ZbHZot)8l%1q&}k;C?8!
z1l^4L4nZVQ9r^=tMFPhDaU?VnO6{0;UQml0ILKig<R4Mg4xk<eX%-^AHV=4!SlC;V
z{MyX+Coi+b`zusBsdN7nh61_t-Uv|fETOiLbE}SR;HD}}W$vJ|vlZvIPVAj)6NvKx
z{F}4Q=AUxpkg~oF7s$A~BN+I)xOab0@Ei=_PMi8uSZP&1_b6<K6KD>l$i|u%zv<X_
zx1ADC1`ga{af9)&*M_IfGqM*5A(yvy=OO1tAOxcs^8_?~RC+yA#PWh-Yo(X4oSE9c
zocXGKT#w<s0@!vCdlyvcn@|W`Mf>O@G25!_vs8~`#y`c}93PlFY_lZbGmZw)?;ewc
z%T3&2#xDw35Wq<Bi1Alf7$a-QPnVZr$5`i5rgk3xx5`1C<%1v@O{JjtWlxg=e)+o=
z#riW^Z70$EUrxb9K>K(IuLiE2Q_ffZ<4fmjd`r{A{h)F`FtelImFBlfZqFyD#1;n!
zMkoA1=AJ2Yj&1Ut9KKU-w8P<yM{Wx-!)>^)gRcuu4*VN4Mg??pF~4AX%RE>L+;u*k
zKt{|t48YoLh28Nlo;X%#<=46^>cLedsYYLA^nmb0*`+tb5##7o2oIpr$e*L)p!bNo
z0TM=f4&Q_Df&r&t6H14xVNY>%CTz~3@RooCAKay(mT*cd?uc#`i%Swz_+4KJIW@tA
z@b3kf{Z^<|S<cb;tRjMmKL|9)KQMF4(4M;-kO@&aZlJF^S%~VF<C)BJ--b5{^;KZu
zp(XU3npL6X<mWtKZ=7gj3A#7=MuY<WUtq?}Y1?`;bs88xxX9XtHK9{qD!35o(Pf}Z
zIrjA3%Ka?}lcY3!jVO)YOqDn)78Xq;jgXmw5FHL-b#hDzxfNhS{TNPE`=n|)MbJrG
z31T<*Ln9pz3t8on<bHuFH<DULZvjE@M?>I9Vhtg`6^_GEUrepolc6z02JRHkD?zk_
zG@~&nEa8N|3yRtIH^J?qK28hm%ta*VL<XBt!G?2mP($kaz(^4VK&-MTGYPt0by6lJ
z4XqG{k=I_%KLt}(;cU-q^Tazs;JtVUf%J7zBG?`w3KpU%R|_@Y({E@ueCKC@(u8qf
za43L@(L^xIZ5f64E_jTD_dc+pA;vV;^nA_c*p-9JDC7?3*}!h*%V8PqsRazxDu3z<
zAj3qdT5=I~m$JoaBsBqywLaywhJ2IL44mkU0xM#k9B{kzPSF`JKxuTHQ1HSzxH6!_
zQf|O%dQu%0LMUhz3j0YUPay>ASfbIy`VvkYNWxEAP-w;)r^&0xg82mQPY*(xq;)nB
zKaUh=-276lBOw$-LfvsFAH&7#?Ce_dc{ojJd}v8M;)sKwHIx(W;O%y#N&6Tn+6EN}
z7Ker?X=(7xB7`SX5_zJFiQsH<MX^4$q#w4Y`&lBB;eCf_C$&;7Ooh_wF|xlPqc;qH
zYE;VSW#~ZQC7d2hx45_uW^?b-+%6II3-(fk?Xs|Lm_Q)vnz9-`!e69Vb#{CwEg!B^
z{VmiT%lErr0SFjd`ZznQuUt<6wlLzZ(q$mV&3-|D=ocCh1nKM`&Wu0E8=d~cTdp!z
z`pxY;@JpC)6z0c%1$M7MQJxsIY+!)wOz~w8Art%!Lb-DkH19|X(5qO)dYNVZ2GDn0
zFp9Pz&|M^Ib^&q2DJq-_#yEWiwh!sjwnQZn5Bwm$R5QYybxef0^hdfXZ=||z8B*O#
zJaa+&oM9DTPY!A|M6spVovcku0b8}D7)_N2u1!7K&#`PPVdFg)p|5#ODjtb$5`)et
z5#cs29O*0pqwU)>XIv%JvmM6i(S+&IpHc5$Uw~Gfr(cP6EMGOGuF0~@qTf`2u{`iu
zu*U3t6M&Nku02xpfYU4Bx+~L!?|<_h7NG4J@$q0m{wY@s?3rHxmW$kcdn^CAz~Y&|
zj}Ra<<l1B((FCjSkQ&q1BkT$}M<hCegNmojG)HuZidUU{vfJm;<J5U9^L+Hwv5Rkp
z4|V$Ve&@)FBTN6UD`+!YKl<r@Gy>AIm`7B!SH@E_G)(P3!ggk2>g=?9WjOWZxO{D7
zR@hAqVFPt`@2Sa=jLhV6XkL~wS{M>F&rzAYi}28zfAZ!+Fr#e}rcAgOj@RhgxcPp%
zkF>9=5s5^-R<B%<z?z@@Bt~O&+E<adIi$g!oYXYskx$`JzD*8aAKgt3x04s2<CbQ&
z)f4X+M+S*jO;>%!Ke%5>;XmB22@RP)0jH%#3%*&blD#?=kT<B-4BdCcFTY<w4j3;S
zHA;|cD?6_w!C*^4p@j#iLSVF}pxg+zR;nJk``3vVJ4R;(7Vg!YDTcS`;9{8?EC$0`
zw{kLbI%~kNx9#np&@Os&LpM(hW_D<*;9}vPR)OPeIy$*lWz^NDc`j5$a?qi>c4pMw
zrv0i{UjbW5BX3h*09#r0RKc*(B=?kC-Tj00U!^JAX|*(zi4Mc9FSqL19#5o0g~=gG
zu`8G{0r#d8dc<u_CoooW+%Qa;@R$7-V-nw6%JU>NEJtVlccZ02mY5megRIfQINw9U
z&1|X9Nim-13E7YNH?uJRW4_l34a&bE-iM_ix`TX+4Lp@?5d*AtaK4A+KDv|qTE%pX
zyIBpW)VUuNTFvw1T=379hyeuq1^yd%ozc_m${@Blf*;;$ozKa6?|-LY9Mbq6+zbb<
z@@vgdS$s}x(s!%y-!e1@ew0}RH+ugEOya+JlXF&vb*Dh-&x*{XG!=p%__-Z<8zJxk
z_}`fE-#WFV9Tl`Q_H50mi2R}q#vZy0Hq)j1$)VK${WDj|Vh1b#`lT<Ali+k0=`A%x
z2K3>>5UQizX7;>J7fCv7PY+BO=-~tf1l$=Z14OyI(hWvvMk8)Z^5=97=Ec0px+Ccd
z<*J*BO!Un$cr-GuDD$tWqc1d75rD%N=D>g4v>rzC0t7i_#@+*XZiZzFzsQ<-GH1Vo
z(~bb~1d;arNO>*_r!DIp)zDM`sda2z`abv6ref=6u_K%`dPyzAjOJ!1O8q6#XH9~Y
zSBkTdTC<S1zWL9$*l6^$67jZI3)^SK#3Nm1MjZv<v6c0f#cXI?>jc4mw8HpMR#oy0
zB*lm;)dyULu(ZZd3q8RrwGP#J9XZA5QumO}J)d1>x=el_?L}VegIz=Xv5qfz;R*!p
zOYb3dD|7ELcZe8`V~aug{_d&bAIvd7vs4aJ>Xlr29vTs-7RC8BJUh8nf3jQSnxm^4
z>&ENP1PFuk^yZy>j7OFrW}^=gXoO~=;O~7|f)ccLpm?(>_+MU(u6kQf1UoFA!#<cX
z3)~i3sdG6QqY1g;6felZ!S)@TooMq72A%_?$9P^m-HF^kbE2={H>Ef3VPBS;1fv5|
z{KyFo%$rP5zXN|JMXQ^3HJ>E$2FPy;5vVc`$*AhuJ~KoV-hj-FJvR?_+}H!0!Q{`$
zg?B6Ft0$kWQ`v4@R|}8COH)bQr=dg7d6N5zm98PtBvSJcKjHFrF;hur9u6wr>G-)_
z>)9Uc(Z(-Lah2lM&lo*?i50`ePglOUQouy|CQhOKX|zP+*vp$Y<Jydr0M5>M?lu4A
z@rB?d0TJ9Hf$y5aQDm1ik<jLqnsh{E1n3oU(-4AHKU+IP%@{Mp=C^Z-n*Ax2%it$Q
z3^<mEFSxugp(RAQ#VghpF*K<t9fzqJ5;$?cJH`g)Pq4RdVN&kRvNhRkyBD%G-89Lk
zVrRaSNz}ajyM!+>a4VNiNXE{bAZpxlr#Ic<`5W*V^;P}2(aK`H-{N5TkZJQfSGB%S
zNw+wmp%jUQ!iOz$iIerlAIhzwQiLu4*1d9#pXbxjeH@-><gYlZvwi>{eNFHhu#qs{
zRU|iUD=`J~#td1!KOd=zb?D|RDG08lGsG|tHB5<zq!96WMcVk2O$jq0-?f|3>T9BP
zm25$jOwie8?l}wp=X3&h>k0C%7RE{)W{8(c8(8lGN;QiR1M4NT0}M5Mw;;1H2>*FZ
z(f;gxsUc~vi~g<(E<(vipi@#q%`H`^@)vE8QxY@7JyobmkZzDuQA5qcPxC7(2+Fr2
zS}uyxO#fO1x)fv$6d-A)clXo$-~!`#Npf3K;Nm}=A;pxSKJU*}<~*FCXk!{|tofwk
z7{0ea+e8G%dM-&q0dHSuAiF7NXJ?8G?r@}zvv3qaUHnmR8<JU&$Nr;$tBnZyte=YR
zo^V5rjkvCDq?-Uq^B|QRNfR|lEand&^R7r8O|y!ggFY-stlZO3se-bO(mrrq$nf@{
zXvsdnGek+u$#3Z#h1_+o`=p<`Fd~`U)*_l(J)J6-s6unET08Uy>NAg`R`+byxGghI
zevUwkp;otoLXV|Zhwk!Jt>?a>RT?_WOO2#f50fxc8q!vz#!{;SFHQJqI#Oe(RYl5~
z6+|@esxnt-!pM^qMm*k>>#EkHXGx2ronrwG3nCuFgO!zrI#yN5D>M@+DbdubBv6wg
zsh3HirNz+Bk-(#r#N<N%yr*pWq5W%maUy^;NVzd{5>Y2hkF2Lm=-I%=?vJQslp1pn
zPSUkuGGI3f4lAf&cU`@s%q2BMYS93Kz$vJm*NQ(?m);+&=o)XpQTYto5o5-wMFp$Q
z-?D)T<wcirlf|JJy=0!cb@gOR5b!9Cj|$jO$(s6qt;VJ-UqTaoEnb~ZoYMtjnO>Qv
zJU4%FBX<t(W3j%<+S4|i7gzG=H=HX8eU>QfL&JFQK%t;N)EWuBvy*R}4&RB>tnn32
zt@UacwQsc118OdzFAtM#6<X5i230zpDvgN#x+Jyb!n{W>GjKdZh({b=>=MNTho}a3
zd*%G1RnjSpwMXg-i)ZSvRix<&g7bOiG7VY4+#k<e&x9Dt7G8UF^*OVoS7Aux4=D6Q
znQv+B5)mEqFQ8Y)`>5s~{hh}j6G=+7!=+t|<X^9iu(^NO3%(5Qzw}ZGDjb*rWYTQr
z^|)P&=kS{nS=piSb$U*k?no(tvn7auqDUt*mia17S0i!Hg`Ny6G`@h$q<1iD?Vbz8
z)q9!?MORzfalVRPbc@@@7jkJDn-@)m9BwR7ufHj(ca_~r63<BcDjA$mRwl<sA}z%i
ziEPo-@NKDrj4Dt%$#k+PF>{PRjWCg;(W@QUB9ef-jO=JSXC}MZDSKy_G~LujCnJ=Q
zI!A~V$*u#1g*zZ3Bg2W43pd^BULq~CQyaX0^Pt`1cl#KIlCasIBf~CimO#bGF)Fk4
zEM+(H(xi!lq~Bw&l~cKDG4UC4^5yu6EM_3Dr!o~RT&;41Jqe6l&*RL9<P<YqB(n0|
z;mFi3W{ArbOrVfxG_nm6Tm=kLQY5SYbpN*K;(@IxrYKnot6e3FqEsXtZzEMCFckc*
zAYG3bee2Jd|F*8ocwm!~=d(K94iSIy_6P>B@-2v{k#&anbOCAPzn^GGRzD>i$N7Td
z?dwMHWnVPHc((&Q?=N?h6Od*;#$QC#M217|c>6IYWnoTkpw0*}O{lr>O?@y)xpbg{
z`L(~{TLG1KFjZqp*Y65xYD6x~tBdl73+q;;D}cn~ePDv~XV>n>U=p+?W-^<LUC_E1
z3n8DWCx9ucoZs)!Am#*)rV^pXWC2U>&xTDd`CKK|${usyLl0piR3XolV>Sr5F^^!5
z;!&3boAk_}#E6}9cpPUeuwzgQH|X=`A-L0QiCBW<Z8C!3Q#XPSi{&nmTqgV4iPTA6
zxJ^duOI;UKnHx>63HcT+p4#DLv?ZNtoI3qyHZypGNkWhkS{mDM1<$W;b(E}biO6V6
zu8I?^bq)mhPvF1mirIzH1tHUOy^g!cV`ET76cXPEghfjNqy2%VK*0ZPk^uqj|7^>c
z*xH!5I@|s~l5Sc$9{cQw{>K_+yv+!=WK#(j_+fmDn9CHKDKafycStRS)=`t=&K)1`
zF}}dKBZvuhBHnkVHl)!<IMLlR7=ZiO(AX;|1gl>9%8mjxBqRG>CH9^w`Qhrs$g^Yb
zp*l@Tbd_A#G3H$mrcT0CwUr(h@aM{t7-omcbPtXJ75S}+vz582GVNMIKx!h&BJ>ML
zq%G;Z05x|-w#~_kIw`SyLkuF_4Rkv&N*eQTzF6owV*(}iNIpTCSGepfQ-6i#g&nl&
z63gR=uiJ&S*HVO1oh~@X!}r1D1w}@Y$lgd_Wa3HQc1RiTe%E1Smq02=g*|q1K=(q6
z_i`Om%RAqQy)@@2VkKGmcj$Hfz6raAE%|7cqe%3nb1&Z$iSmjK23uE&)p6;c3{BHq
z3C=DGeZN1SahTT2NqWDHM%y$nc!P7Q(0Gc7LdDssY)WkAY^9wUs`sdquw3@zoDpH!
zRv_w@*skVDWxbzP{;H(}#_uZffq&FSdE?zTB63vQY&2!57utB(!wYTMeU#f&3;nwt
zzi|Q5j|&#5JJ)^=S+;GOrk|eF-oVBagVt~OEDSPZ+ZYhP&tqMT0eM!x2`lL(d0r%=
z>&*K)>s^=VaK}B#)p&8~ha3rZ9mV}uiKJ)Sm-{P7fsrO}y8nYKPsP@UQ6Mn>1RGY~
z$k3o@|H4wuN*>I|BqkbX?H5}NoeZr#!DNg`oc20t{=}(j1x0Yuv|qw_d2q)qTD3?p
zQI_f;olur<tR!W4m@qNeBs9_qr>A5|a8(!x3x@9?vhHRaF~T+7u%2wEjf?xmbWH{=
z)p$t7U7tVtf}#7{Q8G(6mgWXmo-C@-xd4iNKK4Y+ZqAEO;uXR2>}hKj=Gci{L7g|8
zg=O>Q9A=&C`&57l%Y1h#+73VA<=;zL@f6U&79v#4nyCF4a|zOL_YwR|gRJFQkg0d{
zo#$Gkkc+E46SwMZPX7nL4NjPd4^#B4hZ^rshb|Ma$F|k(biQCvg%{X=MU)*$bR_lu
za`0&wN_&V$Y6O<{4H>E{OyP$|(WrEwH~7SNCRo1-a~9N;m`#YlqpJl~gFE75z1U4j
z2BDc@<PRqpCJQ?gFl;rAEu+b^>wQ&H_CLd0MT_Hu2I8jIf*Fxo<B3!hW6PKyL7%4!
zJ>gwYWA99@M55ml^T(!#sK)II-+Ha`_45QAsZgUV#?>myd;B2w;-BZX#2PED-IL``
z69u~+-GOnCJ>}oNfoSHJ7nJyfbw|K!es@d1Rwni8W2oaAj4N%}$_&H<nU5KdXGl?l
z<nX*C0pB0OzrLNUTpr{(z>Wp>lvCIr-YYpLVsahOx}firB9%@Ep<*3hnd}lGU!!)0
z1t;Qmx!mwT^tjw?92;^@9g=P;#J(+Pak{jo{()m7qVoFpP{?IQ#X*5<^$W@IFa5DC
z4z<=Q&h+;0oI{g*L57Q35LeM5>n`iE)f5F%sdWCVjcNvGBi1bej#pi?vbA05tP00d
zfSQ8%>`BzrbTSvdd)!AWfaDbkY7I2Kdy0~aCOM%)6?t{H2`wOJf>|jiabZ5oc5Epi
zHA!-`VB2zuFucbyiEM1L;*pDM@77@GygL5Qf)G__8XlBHyhmd2$+VLNdSplurX(W&
z=v#f6<{PMF^zU6V72wAO{`dF+5YQGpFp!ghi<is)-2q;7*|_YFrqF+M1%NNGAl-K(
z{o4$zWmEa504areIbTg`G~NXe{R3^Pvw*p&TQSaZ{PEn#Ocq3{9LN|v$=YS1+hR|X
ztGhCp+<v$4{r1XR<%dAN;K=*-UK`!`R@-d2NPy5k2iOU?^u9#k==rMM33x4vDe1d!
zHQEJZ0E|_!-{pq%e7|92bjt@+e`3Y_iWF$b^}gwm>;Kvb_}t(A*YouybGgvt`=V$Q
zOEL3B>(#LQ;<;R=r?+DBZQ#S7sStcH-1KzOv-}2_n?#Uc3t)t_a9ko-?w<pF1^IA$
z`d;DpmF(WA;+UB^<FJ?-*80i5K4yM%_Q-D~@2U(K&5qPA4I?xk-x~76maqk|_KJ$n
zWm|m=M+yLkHyR>~BzNS5+N-I!kt#IG7Exi!UoKoclD&NPd|ZF6%@XkCSQTpBV9N4;
ziq`-jy59%9ZhQb|CifNo_w`PXr>!T@-5ikQd(Vb9?;!$NzjFO$z6M)^;}N>}Ui{e8
z2eJ<s?)n_D`w7Nm#&Vge8NJBf@C?9PcJW1uq_7}!{U<g-S9|CjG2De$7Q0=S3g8_r
zP~x)CJ|x7uEbryR(H`X!)fQ7=<$4%G*5kU_&+OjSxtTv;136rUur8uIoU}BGo`$AE
zecdWMWL^7oR<GA9DmJ+jlq+yzs;_CHcgkT*w-N*jQwphCsVhjPe$(UvDh=gM_zGgF
zK5z4#4&b%ey^ASQ6y6d?cHRe^z7@c(Y;G`tjvRl#4G5%O?@DZMdqtQ@W@wEkGtP%7
zO~h`5#hg{(r~0MYzvjOwK5~z`sF_aCGm~O*8362)=@wMYkWs>`=ld?8rb>XlPZj1G
zcO(*XDbKddJ~Zq`?kFqB7C*y3-|1!hg5Fkqp8puRpTrz0Iqn!@!msvR&of?>2W<H~
z<AJ^1yw?z^wS;)0HXuuPhWUGAjJN3szy)6$30S_*?A<gU;Hp$BS(v04wL+DQ7^2F4
zXyrk~`hPFM<*MBDM2`&g5>)5OXS5T{GPS^^xiA*Ins{>l*+U>0u|y6W%I^0WJSupr
zeeq`%kZ)JGq9>m$3^VvxQ<)o)T)5F~L6&__yur!osu9u<fDiHHey=i*3$TeS=_g6t
zO<hw_%mfRV3OS|4TrBCc{pBEMg8+c?CGu`Y2cZjC40DL1x}g(wEsP?+ILpYDtF$P=
zY>6?k(QNr+Ar_pmx85?ZLFzAd=fTQJggH4DvV(w(|H?uTecVV&16qX@d=ZEW-rG7y
zk`Z&9=pQ$|;LB?>m{xD;MMyPKmjA^33wlBO=H84KeC+k9gPK7!La^6AC}pbu%lAYf
zK_W%jQ$10GKZ1qfMxXPQjHX%;WYSLK*)ijn4E>=^e0WX6LazMCC*liNoD&c#@CI!u
zltEz`l<L_GtILYB2cFN$+7dDRu~sL1Axa>1>JVoiLw(Gx&hAW!J7c`T`v74GqG%XM
zMIR%2Rbq8quaiM;Pjr~hZu=Tbj@o+zOV;kI+0#0Vg~HzG(|f=XnB$Tu`nv4!Dyl3w
zK<Yrtz#Jg;Yf0d-)A*ADoai5~4<yBc7OC%g845qY7K$YT`Z!&BYu+enXDOHxm{JCo
zy$oWx?^D3I0)N}IU6pvY9(os|N_-gxyuVBb-5)Qo`lVeph%nx>p1Y}HsyTv-a_!wf
zujhX>faJ^KXl7%hNEL8EO5y51j$Y!+2?XVNK(*u9w4p9i0M#qaS%TAt&LzrK;!a{c
z0<?I@t%#}P&!60WNN_-k736g*V@ChT(Z!3*dtZVxjn61Q#{Vz9d>%u<jBldu-`gk-
zc8Ko=6`twLq(7ntG%Fy;4VQ~x+A#aI$u=PM@!)c^;$-Pa0ady%C7RAp^cd~6DK^MT
zQC)0gU)aS^d7NXsz^^O<Hg&j9<oCZ$X@cd^zy$W5;{|ZLsaJQS!Jse=%n|Irsd~>%
z-pO^5D5tr(T;*}O>+x9`@LMgbajp@*qwXl)Z_y4^cvc4wS+$H&7Bs+`|5nN8Ub%&{
zoC(Mc7vB0-z~hHpfJp{?_#Pqb8GYMw`=5%;fDf?rKeI5eyg3}8K|6~j>uR|1x;y1Y
zQBVvghHumiyD$&sKQ%G-ZV@f!pbs`@!czWq9#C>3KQon7@S<F1%DGdV#2it<KT8VZ
zKFpW*Dr?>2Jk0mpou@)@!}h9A4_h}!M341dCi7p88F)%~27WttraxSODNdxH4R(Wy
znHQPc{}6WqT{i1pW;bN`%di<3-99@1S!Y7cjBA$+LbH`Mg;jSU+gG|%;Ph}EDYh7i
zw%C}uhbWiZA9nbr=1eCbSEosq?Hz>3y}f@DQ$kts_n_un>zA@yxtW+7`*?Ly4AD>u
zCFa}CFp9u>Pa|uxgPyIdll?!soax{ex)qU%0xyT459XX{#h*wb3$iS$z=o!lzX-O5
zeLWrnXTIG3%sO-~nwdT>)M1Jdy%n#k*3!|-IilvKMo*PZOWcSz6_@p{$2mldJC*b}
z(^eL;^{BX^)Z?nALSL>r#r-it+cvz>TOU5rkjSn42Q77Q4LjC~>rYW*`1rEh!PW-Z
z?Ji#oZNck&vTL<pY^z9Xym302Q9Yzo3#<;C-k6F<z5nWTUHEu1S$F~WSdC^4musY#
zh&$T9^=hh9VxkBD<QEYVE8b-b2_)*)*=_6rd{r|tRL0yA-_$Z2lBpaEIQY>MtHKrG
zxx5?VpiswQ$FAY;fzT;~LB6m2@{+}QwIp%MC^-)S8}^PwI^a0Su^iO0I}uoPq-HfW
zD=E&|#*P?Tpu7}QYSU#&LP`)g3%v~`GO;2l)S<I<%HSaZOpT=tr_fT>#odnJ-|$+V
zAiyMvwNASJvD#!y5o6^6%!eH;MZXH;GWLbIckqx4!|8vExKiO3(Ci`V!GxWNbBYoS
z2^aZ4ZliP6!JNU>gZ|6gM&zr5k?wrSk3qeZS5Y+*?i{WO%!mT9zJd)O+hmz5z(Zn+
zI2LB)O%2{_M~0ngHuSUy8@N{@<(1l`!!61N1$QU9#HFr-k!sS+$FD||u$Qn&)y1B+
z=3H6DQwAi=nJtQ@{{}3+Ud3UGxf0<P$oyOjRM?3&rzl51(HkXt0Vym7;v&vIgu74|
zk+&g6lIJaGl+C|wzJzPDu7iqZ8TF9PKc4@~BrN2@KzdP7S1Rm0nmHi7$X_Sotbzog
zAWdn|81M^MOrZbL+!3%>he*{I4RvC|WUfKuy}4KqrfSyQ)IyyM;go{d#K7I@f38+3
zNG}3{_JwO>jIjZstVqa|Kv7C$ls_-wSDcd|h&VbDBQQxMWLjXn7?^DDD9A7=ofMMd
z2(cl^*=h}Wypyc4v$UWJWeFabsxf>m7_JU*1&xrfZlE(Ad=idRo-ZmGbPZ~SWDaQ#
znq-{TRsxMy8?Z(P5Cg&J!%Q!;l6kx_XTjv1R72@jIghIJk<de+S{rPlXKz8qZSX#_
zeci@SMBkVKt+mzDkOLlojq5E#F7=!xRnC@YeQel>hzkxE>7PF=@B$_u^Bzm+>LjEw
zs7%B#<&(Gv!_5;V>k)%GAz>|uYPo3>-IB`IOyTt1jB(#+Mw1ftvu>51nPrR&y~sg!
z(f=dp!ncHuid~kvgyOh~78WY}r_+HiG9Dtzqaifb(~<OEJqc~kBh4&=F%4A*xzd{S
z7pbCB4jC@6ydUrulFTY2VbE{7vFGsScz&tzzoF2P+xs^dyyJJcGJyaxrYh82#n-%S
zF;zVc76+p`OUpmxt*l}$i16eu5G}lwXjs}f&1^{SUs4_k_UWG5;O!N3TrYzv&)pwR
zf5;OdB-~iVl;mugbQPGp60l6x-dAj?MzkCCLn0&5yqXu=Nc{i>C&ONI(dKi};&aj7
zc1#57k=PmKqXz$Uc{|hgi~Xt7n@YE%lo=m%NaZwNq&o9TZ_HUIr*>lG=}2VIovULt
zAPx;??Lu&!)$hZ8d|g~8G66tuKq8&)jm*r{=JCbayU^{@d2D59QZYySY4cv&HR*M~
z`C-xEYwDv9r1@8S2G4BApUjRA{e<et09xtd<Je?~vESbf+2Vb1`g}rN7<7W8JJjsR
zvv6x3F2?EGIGUtmj<t$LH{@k(&(KT1uF$OEH!D@NlF(6<5nOK7lMJVXC-9q6(c6xw
z8`&0Aj7X~q#kv+u(VEFb7Ori+O(YF$qTjx!7~v^0C@*blP&9G5t5jNvg?f2tmN#`y
zONTljI^;B`XOyl-G98vT3t3pV&DCUCSel!TP+WP-o0S*+OVeZDs5u&j(oM)_R5@zc
zFjx!0MwJVmPWb>UPe=TA68}Jx8UAgLzprdSl37<Kthg<5h7}7^^iLfqO00Jk+Z(|^
ze9U%c%)L7J%3N{hiAInon*6G_d>*5z*CU-7utP|5{-efu&&D%v;`ae+FfuLNqoR8;
zL0G2}^x1w~KNPt`<gtv?|B_g-Hs*)ut6^LXm0}J;9#E*{T9~sLZaSw#63{sB12-==
zTR&K7h$i1^vZp$aL6Vqz)+X*Z=MtYt0*}CzP@shbyb=%G^0x<6p0-;>;YMPZnOrC*
zjQ<~53gtc02S@W~n@|0|Sim77%E)mE@L((lGs6lX^}jgc;|t!}Y_`;|WD22dTf>Ij
z`L}oY>GuN!{Oi<4ksYR?j&m1om<mOb`1~7}ImQ*j4eZ27Av}?CD)yV0G7}^|%r$$$
zKdZUkC@XQgylzzn?{XxLOi56#^t6hwU#^}P^}0HtG40^Lf@^WQ=J~Y^l=QJZ79t`x
zFz?Ayt_4&_KoUA!bI~hNi_M914|+DIhC4DJlQZopoZ_vFizxn%0@_fJ$ikGWJP2rz
zFbOY!Ra(Lvwc0@yVDx@Z1;;ONSA~^#%WqA_ekXQI3yAFXE(xO-I=R0&Nx%R6Mq(`3
zPX7_W*Y~{i#495!#qv;+W!2M)w9!<OV|F)Acz2f*x}?X*Zh@d@8JOD#zk?>n^G#Uo
z1FJsWdSA&*gyHPcv0xY{r%ct3HYrm3%HPs2`=1P&e+iQW5TUQEY7d(;F2xRFn#ux0
z&JIl-KALUY)<o2=+ZQ%@2kx8%m#{k-3`>^B0-Y4yL+6$cuskk`P;DeSdt*`zreT%;
z?S5TaX2ZhHLLY@RwMFHX`|{0g=$(Lx{s>K@IMc8+bf)x-!25H=nS$a+?P0V85-&dZ
zndQfRq<TiE-;d24p+#xPsy^l2qFSk*rMZ1=cFEhu!Dz@Q(IA8{OBWMNyJBNwfWa*X
z4?;hC5XHsNbP&4CjT0Cb4{n9Z8w)#j5iFzsq_e5TxUXrc^(Ad`DBb0rj*OR=fb4~c
zF|T0-(-iKO**uX2mu#B2pOosrdgow^4P&-lbG$=N;ycz3PIMv}W4rb&)+bw(Y*j)(
zKn_>nE;XXx=`_dNW0hmDlVz~vz^~6flQRH;d^QvkJTrEz6*GGa89dpL5;gblsRw@K
zQy@ghjz5&(#-gYFqq+X0x%*`)7i__><%I>l^d^_qBkqW}(WWehJoTJ#YEo8)&DxPj
z;7x{}oh3w|O`Wo04Chsgs7>1xVNbnpawb^Sp0cqmCsqJ3u}0~>R>a$oOf-djEq%UF
z!|#zF-=i2yk1C;az&-`V@a~fg^~j6j{D;Y>xZb%q=WQOEH$y?rZ8L#!qQbDrqaIb9
zXU-S1u;m*qiT{m^o#4R37-scX?IoDL&hAI<t?v_a?ozK@-%y#z7X>aI!yf*qZW`E^
z;qJ`GQ01|l^XCX@7WkTkL5?qDAwVgP1e5?sdf{O2#E)@tt+ZG7n10a(19Gg4ZZ37d
zWS87rXa6{kX-XMmvmGFwau;3-dI^Wova+^XR#YKvfb-bmM}r5hce(K3h8=@H9Nt6|
z0$6ZJ_t|&?ck+b{i-yNM<<t}A1@AI>VCn+$dmw=6Y7nhkC!3J?90ObrmJ~RG>D}!<
zha3W4j?nQqA-lsq^DYI#23F>c!S*;|x*o-`ykW)r26Mr^Z%&>Kwr;q#5O#(EM!T`<
zdlb=p-ts<u@0jxP#Qy)2KMDA5j^#rQ&Uw9GS${TUh8rpD`CfnVOu4{(O+_HE-d0gO
zkCiCQ6A0O8PG#~n(}wZyj&frCzHB~P$r%ZGWh@IVJe?!}o(j7yV)ude4`Tm6Ye)3z
ztemBT<k+`DV1I_Jj|ShGU-saVy^#1ImFq9S0)p@BVF*fz_ffF^{nsP`oW5#~E3w3;
zp;5F42iod2fJ1F1`lLfz0S%+BN&L+(m75C@h)hQ^P@CwS`IKbFUv^7xwg{Cr{_NE`
z?G~<;+HEXtApe|Ey*5c`jU{n=AH7(=n5cKPD-pMXx1rlkrk%i@fop&?=v_52cyKW=
zt%!vZ-SzesvxD;GyR$y9+=e*6s-K{q!8>7V6LySQ_eh!ddTcn)AOs^}=0FAd`z}sB
zFt^2eL@_7`A?8X)9h`JblxKqn<?I0Ch*)l<@X;ScEh6`&3r+%HR=A^SiDq;M(zc@&
zQt90>ZwiUGmb|$YAtQzv!0QA8xvwIgs{)xZ25+-|eK%2z-;;d;-_f1ILA7NG=M^y{
z^jC@RCOe<;Pe@K1OL4;t*CR>81RH&6-LPSn+z&kr;$Va(1Gkjz<l#`@iCFwGIU!1a
zz<*L?hK!KE76>c?4~cxULQFvp8y&5|W&mTA!mLaKMFmFN4qV8GQW=1`El<b*I8YDv
zoR`=zV%re9bfZsCm`yYav?+e+ftT{BVIJg8mcJj3sGvA9eLYg`Gjp)-T~H!^>3dFc
zn-r~yw;yB+1Vm_xLYt$=sLw;CgKv!Fe%v;pvDm8_BZk63%WcLK<n)2dc%hAS!ZDiG
zYP5OPucq82*Gh!Xv=UBhPKGpPVFDj3R6>R?0%JYFvPqq(j$VHg!FnAA|L(^Ht2ONi
zPFxu7ck>6}Aha@;aKMVB|7KLj8l<20_RMp3XjC%Ogdho5aj<<+`SBL&ef43DE1|IR
zGfld<y;#<^V%11YCDpgStTz-!jLqWhMtB?{_|)C}K$%@E7Enm6_=}Uo)4vqHo*j9S
z2KD+e?J=JQ(jQtN9d`Q8@!OwS@!>leQ<=DAA-g3|2c?6f{1C!X<-w799HEViV}9i`
zNEgs&wS;{=NMW*`mLnMnR?Bxog4kik1QVcqAD)OC$Cg~LePi*@<X!?z4xY?GeFSmb
zN~q)x{#}Te^!B~)-Szgo&6YgrM-qo{B5*fIe1*ZUnU?To^v>e53##s`tLQR4Rsv@t
z^h__knh93=PQDI=0zG}*o6H8zsCYPu)9o{Si8Z0<GYLNiYeIs>>f3MM13+ewMLmh0
zRJ~p}(c*SkF=qDMFa$Ru!sxei!8*LcgI9g56YMWROcD<xf$PGGH=?I!pokI%fDI6(
z$3lg>W&Na}K#h>GOi6}sb#J%xApubsmM<KkrOgr-2w_t1#2iiU`y>H%J<Sp?I!VP6
zm8O3SE+Xwe>Z>6~xIXnHIjD*-ayKG88&YcnJH*&G(BcJ3=M4Ov-t7$*f}3B;;UxW>
z!q_Z6z3tz}Jo!%}8&|71nQG(kx2>>1c#bUo4c&^oCA=KHvE9n<X>E-uUJyq-Gt>c{
zHi4ftfkzNIp;E!qY|5f^b^9~O`IW{Q=K5F_(7i);o*UxRv(F6%6d1C4Lg;HT27C;=
z1zv#gtcmK|8k_RF<7K`1Y+;AM&6~D%F)2N!Bs%e8NjwE*M*-d$W8&r3bvE0Y-98?4
zO!;qW=Nw*6P4RAQ+41vJ9Y1KgF|SET|FWPuP{>}HU6OU*?a$;e=Mpy6!>I*Z1t9yw
z^kyuT5Vj8t{?1;C>ZBU@b&X+ru%Cp0sik<0)yYQo$8BhnyoI4h&)%#x%l74S?4>HS
zQuwUmVAsT2^$>j}rF%(N!A-d{Z}R%sV>~(ELNj8ydjt$%U9*&sM254XS91g?k|m&u
zXnXsNeShf=<z0GIlo<ja_Q5_<5tGEdlxK^t#8NWavMxhJ8jujJ^51TfbwfaPq#Ip|
zRXI9#Cks5Ewmzc%JDk%EC#@v61BmsBQJ)%NJC<qojh4pKAj$|?d#Dod{}mbSw{teq
zccAd~i~K_ba53eIe@nimh8%nI+Uk#Op!0c$&o8?<_Yma@YJU>u@O3hSFnD~mc2Zmx
z--rCF48HjVACh(Zd-~LEr{rQekw|>tmZD~Y=$%3SM$<@$ZQOaeD;N1!8X+tcfj%%Q
znEnUo**inyE2$#JM385>TPriVbpKAmqjq6A_|pwoFA@T_4tz{uJLxZD#rcF=+!x_)
zGP<k}wH&4n@6t2byU>>ep3NH80-|O{>sRdDFhNGR+~j(UUA^?eFBOJC++CePM&g8~
z!wd#eNNEoKf6Ot+C`<!^n{R*I{AMib4HI~1^$64Q1QotegVKEpBg7=B&(oO=hwsxl
z4g2TRHSZ!dG((ty#=sL}x{Wep{4WN|Sb}Nc+lPQc22_oW$8&(Q)1M6C(FZ+23W$%4
z?l7(sT5Zz3rN<+aJw@vJ?-BK~BBpZHwV7cqlQ=B|ob-+VK9#TXvh*(3#%`I{gMtnn
zDGVLTXo=2GRb@o02)!monk)^)KXrBG@nT;#7x8{=!i&4CbE+jOXlPP^?^3!gHKGhT
z)E;!_TYq+s*{Rk0?}&0}RPG2m4FT{vmAk0+L<+F*QL>?zC}!zbp-N%mx*F&Im2yAw
zif=n?x;s^f1u#;UYCrrOyiuuTFY?VN3e6|46|HU+Vl#Cw+17K7F-NMAITV&Z9Gz-5
z0!sx3A(yI=U$bS~4s_lrX4R&2Z+;?cG&(<$USb|U`hEnH1aqwCG)f(P!kmA4IYyjx
zI>rH<vg^+++7H*|?C&L^Dq~N;O}cPy)I5}eZrv(teTmWhHPQYiYkiKt3xtCXqaQ{p
z#^IlGeHo=i4iG*tJVBRKmLOc7mzVK%KjE!L_M{PON)`^vq`Imr$W6&rHP?nPV_?56
zU_%tZ0IyZ3I8WM-MzMsR$0D58)it%+p!<L15Vx!h-+v~erur5u8L+fKO1TE+wd|M|
z&Y3mWYN>XTBWqS&t(P}@l*&j|wAH=2cB;uR=4(MH<s0=OdSXPF%r2&#Ua^iv^5g)h
z6(dL?#33h!MpH9gFhH*Nw)y8VH7&YQ_L;t_MYKn#ONEb9g-_o?@Xf*`90LnSDKxZh
zx^VonQ#LhaRutL7uyPVK^d6;wkP$nSZ|CH(DKCOGZ{^zF#3cP{mpv1#FSCLSdX`gn
z37W+X)xvbA{W;vtg*ihOUudBvvUc39mSE=Qnzeh_=i-|PXZkep-hz1c&Fxr*ppW)z
zXntpo)K?N=1fev`fE^TZ@=SXaPVK~=L3p|3qK#8d1mXfgV)B@meyWr_6<2PvCbacB
zV_(XGU}R#Dy1(Y#pHMNIWrG?#7o}7Kbo#EM1ait}w(UrP7CJlQpeOe@n~!F@zY0te
z!wB)AI~ouN{2g{WH&`w{_EJZQI<24(WAEC3a06^@);Z(0aNbT#Hs)hidM@p9IA1s6
z7w}&mlKZ`4Z++)6O2ZGVjsUFpeZ(mXlMomtlM9n0R!1Rx<-AkAS?2umECfFb_h<fl
zBtNUmK?qp4<tg8by8EWVMF{e4`>Vo_50UgS1X;hWixK$rr%MU}##=jcfpL#M`UQeE
zw#;LJ@z&xGFi5Mh46L|EJI`}e$oy_|c+)U^$}F(8rU6E+-gjn$NwGLJIZM=-QaP}e
zs`T7YNq6Lan&16<Pw+<y9E4pQklj-RGdaTxYtC21OZ8Gou;!Id1}xw8=<wDnk3U;~
zF9Olxp90v&sZ^1f0s=wujBffN|I48lZxJu4vX1GJ>F$g?<Egzxk%~D{?tHJcwU==?
zWV{oSZs?J6IYXpp9J0qRXco6pP}@m-HoV;)=+?gGlvzSMHw!GP2}ge-wIx2#hYEjM
z_&vroaKtm)>anRVB=SxbK(5y!e7QcI<A+lvP#_tJ@X6hBS0-f;JPV1X9K=LuKerro
zjK*!wH1T(?84wJExlO6U{04!*_Mr%IJ#UeUfB1|q2(embuzwO1`J}F7M{g6pR~g~8
zz8LywavQrOluA+4b0eK`mgMMI!c^m~58mEH=&RXKB0X@o+i>PpD<5ogCzUvrii!B2
zOsXkQ1&nwhwj_+PxW+T9P7eclD?(%@`E#?iDZTQd`ZM}iib_1F*1ThveI>D#WBl8a
z3u%+8>6EQbGSY&pURSa!;l8)L200i;5l!J6!oc!8DGgB(-f+;tnCgjO6DTL*)MDp&
zG`_jtBT?iUTilYky@YZVzO(AA&Qj$lk5<E<E7g%==zIPs1oj;L+qC`tODBydMxLSE
z*M^+{=qq8&0>0KGg!TIg$7J>><Y$Sd!V~)!*-`mJBOuV3z8oJGnd=SGo9`%i<n>m!
zJVfVPp~Om8LqmV@UqdHco-y);n*>HLZLFsPp)8n|GZd(2=A1dptabsYA-SJ{MPw0g
z&0hE9JZgf~c`gtkV_YCueD^&F&l1T8ACWhgN>EVQAf|mYSl+!5=7yG<uG_-yjF}*(
z#~6g~c9KL#2o{Mw@l+)U(TyBbge4E*GxkN){W?8SwblM<tRL06<S51qEb}NZ<?n$s
z-0E!O<0^i4r3C#-oH#E&>=CTOGcFPJJ2c6NA5wt?KkqgMI^+_LsgRzjjyCwc%%X}l
zu)Pg{rnBNb8c-qa@srOegF*ORa0u*%$nwh$e3zW`ZSbyBQ*kG^{wkp2-rFM#RTFuO
zS-?l_8%Sus+IV$6yzmO%KOj0L%ipI3!Tzlx`^(65@1zGzh|LfC`y@vHXy?z~0~KbQ
z)A;Y&ex~!@J(f#HEwuW$F4<szPPnE$M$d;Z@f+I5_deGOa(n~WB&BE-9ebz(TO@qu
z2xtie6CuUNTf`R{eVsCzBhN)|Kj0n5q<$BluqQenPon3l2rxvr&oPrg+%e7swoM-T
z0PH7lD2@b@KeHl`eZw*>oA_a#%(NNZF~bZCD^$c3%dnqXfx{%M{+@_X2NzUXu!!4;
z_YuG|Il)$xNd<kgsB-ULkb7^Uh%h~q7QwwZ&myP{GTgTH(_JKejmVZpGB;=ZLYk=U
zb<>{QDvr3x4Ed8x%(TAs{}*rX7+pydwSmUw#I|kQp4j%p_QdvyF((r{6Wg|Jdty&;
z&--1hi$C}Nxoe%(-BnN5KD(=TcNd<$D|A?4e3mnymGJqrfU5@)xaOU1M~QIpzK8nd
zQIYVLvXb$am5tyn!rY8|xX|g7v+Vb=tN)*Mzz{r)pvtiI*69%D@H@1A*!^&eGxn7A
zPl4^1A3M7@WTQI)uH>#FXpnQxyr03c#8`Xb!v(7?VXA%ZFpy@ibf;f<QS9vSZ>+5F
zd2>j;$rQelE^W7QT!UB*)mU)>8qtjS2OwKefy%NisG>uM(m^DUU_l$k{&t|e+!JS7
zhKu68QhAcWm#qRR<d0HmF-Nv9jC54i5ab7W$B2d&C`_P0seg&wv(^y(Z)ZujSwdF#
z%MwW6*Uw-*N}uBW$AC`PTnH);YQ`j!XskCjiMM46p1SkcMDfXqTI?5TZ;8sM$@@U`
z3EkG_oZ~yvO5F+GR9-bKGE4wUmS5R!YL~?8_Yf$S>SF@<7h)ABJThGz^y<(fcX5U$
zK!(c4C{xQe9C^oEHXiQo8&|jrN)b1@Jyeoz&1k|xkm|T3JaIpIz_0b=!i`KxsbeeW
zdXg_XFyN76kgLh^UrZC}*m_}0*i^;#jLWA~*C2%E8rFfjBVdVZ>&;IZKtw!`Q1U*R
zBE7*kg%kiIs83a+!=4itIbgC6Uglbxa#YV)@5%>xlK7^=l461eXlHDgr%ls-F<Z69
zKU}c4tO?5-Xg@#>P`>%K;=#$$+4h$PU(vW*$~sXv9F^likfht?kf`avyOlN05D8NE
zJ10`XPZM;!S}W{sqyfX;z7C5a4Y6H6e~Y@8$Gl<Fyag;|+#w%~y$|;sSW?9ZIo!Ub
zAy2r~T$!jM8+PC=k{Q}hRM-xiSDUz9Lu!u$%LL%Soa^1}mernG;XCWccaA79E55){
zE?nH3se!ed9KJv;vMQ9&DUL;)OLDwa3D+S;03KDEY`F6jJCupkOyJgJBuqz~cUIi(
zw1g5k<HXzDCKck{r*i|3twiT&0ZVjqRAF^`_pxUjN9bOk3_3z*=}!&>YAX8B;GOW%
zI^L;wnbz%oiM_kv49>jxJX7AT75I#gYVSle1QaLEz$c5TT|Ky-DbNhN&u8YroRPKT
zGk20)K7H1hnWwI5+?fE~2+S<8mUMPbpOQbdn+PO0;f1KToiN%)HmcgP!QNuFb&Kmy
z)Hi*W1M5Js4S#$jh|cB5ND*|)Wa4eod)LX2?0?vT28;!iCD2q_S)4v-s2I91Ecj(&
zK6~anl3@*>4MDXqW_{UEiA5E0Wqot4B>Ve=`vVIvJL^FX9c6KEPn;Oo`hhp<N%HzL
zECr;|>9py6_1CnvPWKp4@U+7R=B&xoFV3>vh23yyuV+w!Z6l0l4aUS$kAYuo_asd(
zqFtBMaE?o-JqTo)A_Mi-wCPp4pbo`Ly_$(-1CDq+bxzhg-1-7)eeFL>!i45krNJ8f
zJq&Aew~-SIBeOcOUQgZRAsZ_z`0-!yG@s^j2Id7GbFi5j1=e|s(1VdkzpcN*-3H<r
zn3Rq!SioYEyU=W~mRJSoOZ-1=c}wI-bAFG0GE<UwaFZTn*{({#50q-M3N~0_3ky$0
z{3#Ow_JCn!zc0O>=)$Lla5UU9XRdjZOxkxNT5<2da?I>NbId?nSn-pi&FaqYMvn`F
zZ&4rv%Puiy$^O@*At^HP%w=Kg15HqzQOMYU_g$Pi@jHi$Uy@)0J5%=ltuvy#AV=cj
zD4<(uWZ;!C32f>(2JR#y0|)0si60pCURO^Qd#75A#x>279iQXdx4e8nPTn@8X2X20
z&6BaRqW$l1#%M*4sWKhBrkb>l_D2?zI<4bSce654mO}Z56sN_}6CM%XME&`?qhkNk
z3dk3_kAr;aNjHp7=jz5|qBeetUm|vB^WgNM=#)}BoKU{cXQ^_?r>5av+Eyn#b|N8;
zJ|N19@3G>eoj0>S{S|?FoOAY4HD7=te1<iev)*U!E;)d3eE=pm5;p&47rcbkqyXAx
zGqg{zPt}2ia1zKJsYH^<&R7)yVvpU9T}N@ss$t4_7%nbg{<%MEne3We_&mIQUeb*}
zB6#`44tUsg+L0J3AAe0pq1OvmZ_lZfhGUX1A4{A6g)x&fJ_kitb8D4^x+H~N-Ne__
z<zafz<!Nf}WVq`8$8dF19|zd8!YmkQj`Krd<{m|f+(Bu(Tj0SEPj<b%HNfk%gFU0M
z$@bsXte2&r?Ztp6LUUpFMeoU9%XF1Pph3nK<5sAt5!{ZdjAQcoPPvHOasQ36z5ky>
zaFMS&72RaPv%Ea#bpA|b5y5{fJ%QwOaZ&v}rHPZT&+G2TDprAC&u=q1{IAzLc6~NM
zUyh3@h?&DXUt1*N6afG<coMW%*&9M(N#j>01+yd8V$5H|Qovc{v{`dj2;lRav0GqJ
z2@4tRPuH5syGp+H+u@cdPV9TmtsE=h)hkvw^AQ0bed^`+h-s-VpOkzzRT1N25T9^?
zT6)dk0~hU`X{zVzqbJdARV&yP7Z8y2TF`O|ZoJjBvR0V#YO?N+^xptV_vA3fX4LKB
zqy75mS|TACD{W<1P=-WON~Y06G4<;r+oWbhKm!eD4ve)+B87n!o6M~s>dm`ZIQa($
zpB}2t`y8V`OmmI9`NJGinw1z2b5CtQ6Ot#2adALT*4L+0-!l%$Xsm&I)tv%wNx&!h
z*K1|S49)dPH_9;NV`L!q^Nc32S846j2PljJ4B&kAd18kr4$=LBFZliGUN3%5ts<{i
zhkU5cu#=CG>p)3+1V7$^o(oe*cS_H<bJcepDykMW=3_P<lBp0NB4Z)!9j%y->KQCA
zHl^BXK#z2EB+jfV9FVmFn80F+_WL0uVv{$`FnSadQuXS-j5;fvr=2u`1-*6%YvbNC
zW!;dfc4TwxaeUXFt7at#g}nHP5S-(o96{fJ#)X8Po?>-h_{VA#^Gx^^_YLuLEHL?t
zw+Ude*a4@DnwsYO9MCrMu-I`uA#_~69bkMVV*1G3@j#kYsXn8X*3bWFuh~|mK652h
z{>a?^@O!P=YpzhUsO_zl*Te7II~S_-$I27|9m~O)1$MjgGSe%EE2YZTqT9z_-cb|J
z3-MEE^A{nCu~Ms=awF22UEy}K6BRbUyy`Wlu9U;r?8CpM?)57Fn}4GuKT>)`Uq9WA
z#U6lMFa1_7ZD!<IRawAuUc(JH)fLUOcwg?<%1+{`(uUiHbjtYB2W9${m%hb7b4zNO
zt9GCz>6E)rDT80OCAoISm4;X0aq`bK8R_cQNI7Mw*V2R%PtLpN?WG-ML#69;C%^0S
z&+^JM!>ygAeArKWP%H>hn%nFPxppJFMam;(c1ulgXNO9yKYf~&C**7F_DU<0`W8M!
zOVI%=^Y-sCK8f9p4&FLi9z<v7zbXpTq3Yr+veRjjKUF!kf1Fi><dN@$B(@rEG!vo<
z=eK%3V6+icBX1)&IkQ5cG8hg>1MEl*f8?jbF#mDj8*TQjfOIO8){czSzz8H@+HeH7
zmFw~1!rAiVTGXQYgUFhZxSkztPqYr3*N5Z8rLIX7H<N~>uYD_}@5u(=0v*^`JoAI%
zvjy+VPx+JT1I={!4(tO9yjk%BD7foeak00<Y4h!l6H=XxQEF*S3bhcL2gR@=1w|`O
zAFI#sjJT}DA?Km1#+QCJn0lfDaToJY2NWr#K7WbZ8ET<j6C5QhQ8qbP5YUlOm`!{x
zmk=!yCy)?^(n?g1!h5SJ6<X3eK{TdnG0{!a(_ZEh>PH~<<?HAVFI%dEZFt)#aH=>K
z+$;h6Uzd>)7`>zR3BE4QPo!t>B{cb~2uH)axB0i~7_2(s;-tXR?XK6FD>?U39;sTA
zliK-DMXKi@$3y)n556<Ccku_qe)5+j>#Yi%<CM}4AoQgR>kX~hHH6Se3fNG<=fsPy
ziAxPUlU(Au%^LBYMw|H$<M!8X2XKy!>?-g-n=?OH0=4hSv(#lJdQpOr{D@8&7Tg$x
zN_JeaOb|}-W27LVIJ&7Am=4QEHM)RD{?gnwk>{II1v$`UJMw({t}@W8Hx)H)MxSRk
zXocJRsL8PT3>3xcfE6avchplZ@kw>DKCF4(d+ygL^ERC{;S&+!wXK(nHEB9P{O6t=
z=`o7nd>uyl&=tiw6~^J?72<hoP5QqYh+lJBS~V3lo_5mdhl#1bsl0-Zd?{^E-qX{w
zi{!>A+AHu@`+c)>eX4+g_FFRF&N$nRTVAl!bs#U=jz<lXM5_uT&Z|!q1k>3Y^=T&F
zUz(}6^j3|kgwfD7kgJjD&Cc?gI%#`xp&3ycWz*<bhSTqrT{+?7H0GW+0PwBB<@9h2
zU{g(~IodH1Lspt;)k_43eM9RfWhRtb!r6YbUMu88h{JM_A4Sc0!(*qFo5_><T!9m5
z7DZk{CNSvcI6Mn5##!7Nw}pnzC8S-mT+~~s$uykmo*Iysf{k?PtMBT`C8iPu!9t~V
ze2+-O#riFc))x#jo|xw{g|JQ@Qz-(gpWbzLQ?rVM3F#{x2}p(%bUx<mbB=v2tMpo!
zl{gdKk@5Ohd<xoVdll~1wg}CQzh71h28YL>dorwjV43^fKs+BU&R@83QMrs~>@aqG
zw|;sGZcJ}>*;SImG7TvVCRVO9MOidQR7?RYT|8pNE}|)ZFycfwZbTw2alTr_YN9x)
z;TQwc7?Ix&snA@KYD8>YlYMF~%&503uvgJfi1`c+ivyT_C$B^W4mTxg$oO<l_TgAp
z@V=r_xi=up<_&jkN;k&0An2eG&=oj%kdRj$1hB*8YtlrAJ?RVbN`ajg`131@{>}6a
zbefE(KkR??WdK~j!*bg?sKYjJ3%ve}%ni(+Sza}5G*<G%*XDmzA2LJ1tfu6cY{>ar
zb6(66)L#`5g9ZFBj~{#D?uKM0QH1Gl&7aa*0mn+Ju8H;uBQg97_P+e<mo>mPi`hi=
zz-Aa?dJ{*_eSy3}1;YO_T`>L=ZBGztI3bt&-<-ol0whe(?p|PFCT;;qxc?Lrl!?Ns
z|DcsXG2hyCidFEksVdio-ZtmP%aHqSPDgcSG8nqZmIubXBvrZ<KXKrpu`*E4oAevk
z$u;$y=#^!X3Tra^lj7<0d_Lkmxy=QFr_kT`oWbrU&J-jp_aqmVm|uXE(Ev32so!`A
zQ6#qlB~THjT=d)>(h44cC?uc~At&+n;d)&sUdLDw$z7kt`@5kq|HnM^u}57G7@o_a
za{EL>BjMO`s<_+X=-<r@b?vBnx*wH(ejSS@um<W1Bap`0Lj_{VcA_{#f9tTovFZeT
z*t0A5`%F0DCbtGz!BBNtw15q_Oe*!-j=0GS<6Of{eG(WQxdFKb%SZ2)GjkS+!fH`@
zIxn<U`e@}egfu*)Pi;IagPL;^b|5$TKJ&F1?|LBI_opEyMGWFtQJFoH4qEQm=v~hy
zMmT4`N_pG{Zelk~zN;5H!71^chDH~KhV*~});ow4`YhH-ckpPkF<njuq6LTM>{o@}
z{c1>Nb|3UdUg)V`j2rUr?8G!fEPHiAbCU(hBfm<XFl8WUJe(S<I-|Svlh*~18-X_b
z#Iuxu6-c+W4p^(k4euJVf8*NUy14H5^xuwu*pxOogy?8HQN0q|sn}=UboJ{9W{W}Q
zdJ{vvz>kM1QCQgs+DS65oB0kmr<YjS-e9-5K<>j+PkD5Bzr*my#<O6XGV<^~MbZ2m
zl^{iSmYQ2U{j*x#_nq%eA3Szp3FJtNZ8$NBvnR($o(8`p^$zqYT?olXO=ou&yv1Ua
z8q>ghs+>Cte2`^K<|VvDEF@4+)fc`j^G<*y9oKqKMN~%Op;DOOYCL4x0@Sj7#&!DX
z$L~9{vx!psiP8gJl|GdF^6B2KI7!{vH3rDtY^4wO$v><)+&J7W>gN<c9$j22RXJ{o
zj_$CZtYUi<5$ze5<*7a?)SxDRxRR-skHU|BlhtL9#pn_5?2;0Pe2-j8_~~-l7?O=B
zMD|X}#&J92T>{rY$)nowh9FBbRE&|INc@D!CpFt_fQtHCf8Kij?<xY>qn$F~Rvm`7
z0$GI*`ytv?lxNU2qrF~ZMFVM9T5Zo$9}SoMd%+-bK%Ya%r&{fElYLdu3%%pOxaK6y
zyecokKr$CNfvz2zB@0&`R(KYgcqK5*ny(H&B=A<x!S!B28`3N57cL9~sTXV7q2uA`
zI^NRIoc*^REZ&fp50BevfIKEve>{r6u8LKt3u)CsmPcy=K*emO=C}X}jU&T<tjT>=
zLQpTt+EQa|?z-^#uBDbB-Uy=Kd)eq8!q35_Ptt9uOG|nrV>rtPx^LFK0sCPFnu#Te
z1&Kp!vdn@b&w$@_=!Ry#CYNEx?gAzn1wGhVh!{+k@FL#=_-?nVqfT(2#q04sKTs6I
zFX+xHS%nw&&(H*uhRsnon+!2Zk0~bVAHWlk&~O6j@x7_+aoDisAPHvcd&|ggkiF%Z
zflvm*SL?TnY>xXC+swoU%1>r><cj0N*R#Tc47r~#)s9W0Na&{T*@<49`my8<qfLyC
zK^|I4gb2Ik{0NcQsQXcpSF*{s;uiin-AXQqv3@!nDN*)H1Z3N5$8~V_l!p^&at*hm
zB%yXiBwS8?Zj~hvid&QP<n0j_`$3f1CEwf8G-d99KW~&3;MMu}W2kF|4p8_EIe;(A
zpQN^!gm}r!3Rldz?wtQ(<0a;p2(vJ<48BAwH@0uk*|F;O1o&$aMfPP&7%I__1y0{R
zlh+iCyY-ABY6hZ<1q!78j*d&O+)xS`OmJ|v#arW173H8|u?S0){ASnvwTNW&{+(aU
zL}r13bvt1Zc6$*6VwVD7%(X_X)OSCToTDsUV#hiQjavI1)s<_k-u?%|ayD%Q^?(Ah
zwAp-s#Y<lp&F8N2e8>5I8Z9h#In&rkFqhg^QSmN*-!4~5sbN)u{JJQkY>iJ?lI%R`
zn46J|8+&50_4Eyz#T*QK_vofl_wCYb;n@T2JZT#g;iAbOMI=n01i-!B77e<cWLWx>
zzE8v;Zr$q$9*OhdugnnWl03?bAR4_1Ie2Vb7@|%+&upxjAMIlwgSSa=RPETPUrVD+
z<~H6pZG`888s>%dqmc);ROBJ8B(m$w_yL2)@zNf%02`CYd*wD4B6RI{hqxXebMZK&
z<dm8u7yVq9NB(qi>Ao8icK#n82ji4O$tZ{u%m9x-7w(?-@g82U*d8^<G|56ogJrDp
z02enh<1MrKs)ykmezH3*(p34e&)<2DE`%;RW~+597PwT>kc30*q>TAq;oRBKiQd0<
zV(fDpX7OynG#N>Z9x#b1yak^%@I{vpt0!zVSKjUQgxvCeac(TYQ@P*;iJ}sJd{z=z
zc~W0~*Z$Y*j4kyIdjsn8z3IuC7k^Ly2F)3_#{d6tDND4D$KCtS7wjGwq8BKL4{b4K
z^w$z;Cucb%kLAFYwJgA|`t^VH<@(`mNwVGg-49pgM?>i@j?D<;<xJ!!rH{p2{h6+k
z(QBCq{_b=C7|X=Tk55XlZ=|ifnRp_*ur|j3ZpePzoy$qjg*@+7hI9xBYvw2Ugm3Ck
zbbGw(S2l+0<s9wNS7oe)ZUiC#15S635+bJ7r8k%da2quV>V+6%u+|{kHK#W441$^X
zVg#?yvDqk5cHac?zi_dft2Lt>#hjow&+(ulaYmtAAq?I!>0=xJYK}llXUonOZE5m)
zxS*#TPK@QLYR4Vy{K#`QmSh8eWs=5FCdc^f;P%a$0h`?yf9ORuDEXF=ANQZzi6}~e
zO7hNr^Kj8`=;(ohb{5xJqy64d5;FnTKz^cUiKOn}I6m!Va)6`NlD(p_%tz^%Hz!bK
zsn48sD(E6HZ>FGt&wAljfux-g7l<B_$M<s5ldMgfgr(_fxOBTZ6yWM|*}*$6Ozzl$
zKQYQ1|76LElUIm4MZTZ1`{x5dL$cZTqtr8rrdgmSEX@FO&_A>dg+ykik9GiA?e^x<
zlKqnyC8V4{vG!AiqbmAPc<p-@KKEz(zr%`1+!vOHavtV-;EfrtpP{pbZwXWW#)18o
z4azXAi%a9inD-|jSW#x)ghbv8bGrE^Ah|!cy!G7+kt9QYyHGSi3%TubbslSTfaLQc
z)r9pu@6cFm_=sG_PQjk?lRlQ|sko}(A56OiEXMQW>xOr0xM7<qE`k=Vo#aCW7cdd#
zlM<<9nHI+$+fMh^I~UJ8pqFc-W$#iqp}%%5j1^9Xw;`&oFXc;!Pz8!DH#B_%fn;fp
z^g$}CkSMMX8|JeC<0X_XFZ4ILY?mA_B2?eQ|8R|X!j)TIq1}8Kf0OPBvF`ebRt>QE
zG^h|El&bvz$l`u4$ZB_vi6<-}M<O-bhZ5&RlIcr~{&ID{uazl$zWhopAag(Gt!l!4
z?;K-|1yg<z3~YvEMJ|-7QY9AN*{0#(Qt$py$0kr^cIg$9<(xG&>7?x#<wydOOgG0x
zJ_)rnYf~nY0p*vZSt+5S-3CU`ITg^%fxjD$8%FA!PeDFupZ$Td!iaUdX*q>A>DS+T
z$NzkgDHGJjyufl_P+h_fObQg+tf9h!SVBYjM>d7eD<w9tw90*$7II9ksXD6Jjjzc7
z8bg2QO3uGv0e-)rRc9_2BM{{==JPh|u~u)dCG&vv!z2u1c-E0#W9kPsKzX6J-E^iG
zaF|$)Dd6-|8sm(=>xPxdK^qV8pfQ7lA2QDJLTNqO;}`%S%K0;J0-K#=tA=iE02lpr
z<N8^wdd@zM`ru^i61qB|+zF?VnLnaFd?ETacCV2O9ySrtuk%Hqov2!w6&~<nGN;m0
z%q*>fZgc4L_3viEX+mUyD49QlGxQ}#1bILC`8xhS*6QG`-3K&8_;8dt9xEa*BKDbp
zcI?sxf4Z;Jp(J~|=MHV7oiNN0=C9h*-u8nt`%!#UhbkcvtIR$;O;9`N@%{boZhzk&
zdAagJ`s4Wcyg+<#uCCbbwj`002||hQ!<{LSMa0P17%SGJOP9>bReV<~YAg+6G*tqT
zNA3}S5R3k1e{|w82{Dbw&Egm)inLlrb#o{>-)Vq%4dK9&ji7QcQ&`$fCi69gmk0h*
zlZ}S~b9EBDPJrBy&%zT!y{?ZBLj8W^@d_@(^ZeR(@G+4jXXxoU2AnN{d~?dR^P7Qn
zosog@^32T2OLlDR@Z$)A?q*=tpOLKiXhc%=X({7tla=B4skfmyA>}91i}-1puNU9F
zZhmF3wqGRlq5el@cS@rx&Rz0{p(g8jVJs#Nst;LBLaYv$@v(P#d;^I!V*V}xb=1eL
zwi@MYS&$cA134o1KOw!Ggo){%NDH0(rC%IbGp?P2Z_jyaynPbh9C0~LYMo-Lm=h2D
zDNxy;Z%^%c9u>DiLoz2rxRr+okifB@vC1XFwb0{lH9)I{Vc^n%|KRqH+qysKcW=bA
zqfyJW+xT3<*u1b!Q1`senr<%Q(9P%2z4vY2_8u8EQ#r>8cR7FIm_Qlr7xxZpf=%fZ
zkNtJO@ZYYzVWD47+cyx0jn5GQ`ajqG27=i^8P1cPAW=`ScTPKg7{q?pO5TlzEPHca
zU19c@zVL}HX9tbd`;ALMAuo+L9EmA?;dul&#fqQuTKP%(pb05v!wuA45rj@m%Vdg#
z4$Kb!`eBQ_SarD4j3xiIXxU6-l<!k|uvW{EmmV<QcNu#<sZvASq^?E^wLYBfwK|8a
zba(p73|~r1fEiU^F%B${XH)wj)I5vf(j)G4MP7t&F47~mTHA$<Q@uKs@3~H-e=PnY
zi=Hk&(z@>#8Tlg5wV0&OU~F^N{fX0T%M@>noMFtag;*!i!tqB$4x3W*fV&Z2$zN&8
zi83erIGDa;qMb^XDls2jzVW}$_Ly$W9k%8eC+BJA>#mxCY`+)lKb35lo5dS$XA#7m
zU2dR(E2Bh$pzp+6p8)Q6)^B3k?EK%O4%X=6j=_n+k0T028lsZ|&wc#A<iL6H6LAqF
zwOlnz4+@pVI3~p0_HI=-QmOSlg#8pXlRW>rCa8NRu(Yf&bW=wO6p<WZigL2yLWQ28
z8fg6wyR{L-ZY_02qm|^KJK?vSNiyb}k5)csf!mut-qYQ*PMxW_>i(zSx4FqZBAYBH
zVT&u$<gsl){&jdlTeNv%lm4`wilk)ay<T$Y*%ENF$Pl#O{gQgGoA<G{pv&NIAk-}w
zjIA`bFe}Am3b84$0dVD)j=fHX<xqbvt@hWTwIHXEE73(o)o^s+{>A7Q4tKCfKrqMs
z0kJ{1%KWrItt2K?Fq*?@n#+mwZ%@%zpLFD=eI|wna+pV@16+mR<eQ{J?mIe6yqK08
z$Z@DYh<&86<90SLe4zKgsiQ*LSty~Ti<^#96w8&whWIO!|KW-T8w1G0!O#7RU<*g8
zJ-zA;&d;ES=Q$K5X*Xy$r)9j3PZ0HQXzXBDhka;MZkhvf5nZe9&Kl!W0{#rn3QvcM
z4YU0Z^V5bdjg<VA0vBa0RZ;ZPy#BX5nlmrHAdq8QAXV)u6Oj`FcVMBN<Vj|b;7N)_
zYs}H$wL$Qw{Rj71)5OWMv#4ne8$lw2!3OXnS4+oVaHE?W%}F@TLA`L<o@vKc;GQ76
zZpZCoocK?s-R!Z$i9oK0&S&G0f8}y+m(EWD|ExkBTjVu6)1b!_R_vN*3S-&&ANObW
z?{T!n+l8eCTtS7-f>JreSQfS>+dgCX+f}uBM+ZpNrR&Z08{IfAml*OSETrV2!qbI4
znL(tGC3i=Vy4dx%3W0)fi+QY{1IG?ta^_;Mr79-Kuy-%7`n=={IUo6)__+6EnQK@=
z``QpHg>=f&>d?VMHUH?3XJ-DCk<<V`-<J1PQXIsqEUqa&x!#aPh!iXgaH0m~Z-)`s
zN8}&|Z@`mbLr!jj1(V~8Z_;oApHknD@)HUf!gIBsn1XmqxuK(psr#mMr$%A<cro9g
zBSl;!k@r?OGpBZ|>EPS6AnGXT$DPb{)|k<;T;`-v4>%;alB|9Zt5K?m|3~Vf(;BSL
zEXT>&=@Bi3+1qEt4(OyZ#}@|0fBmyZo0}hrMv74eC(<pi_M>ey8L836SbsrNoqbVW
zFXYIp2^s$HJf(GSwNqc&R~XrJ(8F2-D6(3vTLw+26n!?g3ea1iZHVTdga`+2qODqy
z&+W9)8Oz|SA|RQGFWakUJ-f4dgF|-&g3tB5(*5Gmw~+YDMnjoo3{cagrLQVvDm8*7
zYp_)4B}Q=;3E2#VmwkZgOlhm~IHkJ~rNc~*6AP2}dDk<3Mxww-Fw_+&`;cBm>deSw
zDCCdBnHbkS27x%8sPvWj>o+Y502#WkCly;mZYfz1>ua`3vp)^5t2qMhHiWmqN1bdh
z-QuT_%zK6Sdi^I}oFds}4BZ9*M$O7YDdy`BV5#2HH=&pWy4eq@B1Tp6u|U4U_=(qX
z16Wn;J#u>B;aREH-mVeVBEPW5YtoW1H`hf0eno`LilnSLTQZP?vc;h>aJ3ma#A%P_
z04JSnN|zedIG<b}AXu<Vgo^Vu`d9yOtlpK^Df7Ezi2{0M!$ifXFYCHik~NwB73pK;
zi7YQEuZao^K9~qr^_H}&Ov6f35j#qezH1TilrK~GUC>vBQO`9Fc<MW<;aA3lm;EzQ
zaB6mPL-Vdp>f)b0c-FbFG$DA{v(QX8l_@9~Ltjfdcf7qO09!pCS1HRVqk9=&Q%*O6
z8|a-L7dmx4*oc^EpzCDE3>@nBl+sShZ?ADzSgNAm;^P$e)R?W}e(;U$f1qD_Lkz$#
zu1C3EZ>KirARmkTdsHx8omz4<s_KqJEb*zB##nx#n+EU_0GK@{6>h8Tmm!pUQ4(_D
z>iw$?P#*1X-R;#7;67hXMG*#5J^Uf9Jz|u_PRtASA+R*Ju2YG+1M%BYAl-T_y<1*a
zbwf>iM}a<DT;DDEykOLc2)pTuHe1YPYH4Ax?#~bUijWh!4g8_prNCwF&&p;we2183
z`fP8X&_gxClD)*^pPCb3aGEM5(cZGtV|W^hFL1w*65#)vfeBq<%rq}&W$ss6O?~J6
z1K<u{Nnfb}z4Q8*jU>6U!_yEvD=%7!Yu7uAJzO={m=txHbJ?ru->EcKj+-h<Ha!<v
zFjZ?-W-1ns!`MS^8Nx?kf1`wzV?@U{SZQ)Z+s-%6*3NZS5%cJ%3VtS0ZCvnsb4z5<
z=DQTiizsEAo!K?4rcK$R?T4>L(>EcrY!pn*YF{>u+ANTF?o2+&Zv@*f^-b|rsj^I8
zYRNCPNz}+hBmNTUe%I1GM#YF=>n2k*@M165AUoTrIg~9a?YAM7hm^kfiONS$RvEu>
z!K9!$0jFg{AyHW7S2)g!eoDe2KXk|>xHAvf<gzMR$4<)qu5fQd+-x>36HUUlR~Vke
zc54nAEf^)?0FXYcFwa)tcM<q#p1;qS+8h*9kNghEMbSpGuq*M4lVvXWNx5olaIcdY
zi-Vzw@`jsFftFy+P86f8Z9g?xGY9djd0ny^^;&#|F{&!lwXqhO<@}Vt<S>XuJ&8*F
zT~`yd9EWEaz*REKt7=<yz*?JQ_E(V|Ys9SL&^eI-BzKKTRVMgcJvn1M!C~#ZDDgFR
zan`?aSf?@WrBEi$K8=*l{=O}JfE0yaDXkq{<&|Tn-H2;ce`Srr-(dPBhj76-Jh}<d
z3j6-~JyT`E)xD!m2h4FC$|Th7giusE`xpq?b|V52K@Hios#Ko#_EIT^WX=gm2f3#z
z$eIxHzu%n_?GO{rUx{WUN~F+v;o$6GWq+8z2_cN6X}5lRvTMa#8qdG@?%&A=6x7bP
zFJ>k$V+TJLv!EjJ?(VfyNad}ck0w(DWE%_q;T}3k28&tm%fKpqAfGoxIG*@%hL6U$
zfTnHxM^L6<2q8_LEvYDW(XxsB=(~8mbTM~-{$GZQZ1MoU-q$scrm&@E=`3^Jo-(b}
zAbL&BKQk4%>vy@_Qt8u`nv2bfC-#MA3YV*q>8Af=$uGY*HjV4DD<&g6R+uIDVy0{H
zA&1hb1siEMZzU%cOZ8)66va9Y0jp*7^Hq<|k*>E(kp7y^Y8GR97~)Pl>F`&=?u3$+
zqv+~#TxqE1BUgOo1LX1$&iI)ogx+2Ew);l3y86@B(o{Xp7mLTzpjk4v$+UqfF>cKB
zR4QDS>t^W)@C<Lke(Buc+Lkl(n~EMU__75L)}Wm`jFx;-b8EePNV=;@h;bFS<(Eks
z=C4q%iUXp>ey-8nO;frjlnPv>H|%P9`0+?-9nN4wDy0>^GG^{Gx5FiLL79kvS!ODz
zWJ)67u_@mfb(S$fqO3jQPg$S>9l4t2^n^x_Zwsu^yp=*iWkGXcpN?#gOirwyMtYIX
z$~QQlqXc}W0n-vc6oWtuH}#meQu(Z*w~!_16+VH7JHid{WYHP~!+q=+`|$qYSmf$&
zmoEbq_4P8Vnj}oH^qUHSnE?+ntJ2qH4l*7Bx7)@AIx=O%d*gTO^J<#$N`?g2S?wN_
z>yrkW3&~eqh=Pv#`n>t)^omm96DDBd49|K?MN1*H0aW4*^~k+={Rj@OrMg*a*0$=C
z>m!iKC2^cA%&4N-^%Gs~$babC8<QV(@7sU$H`>b|*%-#)ugu_U7N=&om;W;0GmJl`
z$ku$Wmp1?Fv82)SUDwaZ11B&)Rzs5kM(~6K{>sB}2^|I2U4h>@YR7{|GpaJ1pSi$e
z6T6B<S&hp>y-TXXHCEx<zA)=n^Z9PT<1AYwGeu-hL$lG2^nR?<P-#6A>Q(ei<(9kb
zuIr_k(6Q~7X`<cqg1#3Fc}c5puF(}|7gz7-;k@JNT`5*wR01KF1`6>(6gI40nl=94
zRi+ZMEBf5j`_9#YHCp62{;WRI+O5@LWPVWOwKrMzU=uE>wBC~0HxFh;R`j)I7r3P1
z4&NttF_USePMa|!e2FJnuW<t&eTQf6=3jDk<4jbC8Q^H+cN;Ij0jCXzaP2WCdn(RJ
z?rk-Lp9I(5oA`>IW*Ixp&%BNT$_BR^zMZm}JIiick0>M6G?kvO4xNXN2@aVKofpm*
z#iRT-KM6>f2v3?m#?CEkHfB5yk||x*f9iEfDa%AI&WHP(jWPEhVhqUBy-cw(xAq1r
ztUC?6PP3-lgTkV{0+<52@en7hc+2gln)*xW3*6!<v{3<ejO7Tg{s*#o9K9@nhcib4
z)y>)%^74{;O?v0s0GQySiwhEsvi;^O)d@cBxQ8(=gThf_(MEKHi9Rz|FsPmgdJlT^
z74bCTy(mA@i3Pw**tcuk!(6-xb<qV}m;*llYzPWJX4(|l%fCs7iFlR>u_vQBQZc&9
zyZBu>IWtxAyX>t5IWx{D8-hGW4t4}Nd6kHhxFJtgOG4JJ!b*-i<SN_ZPiueQnbf>5
z$A9Xdy9oM4PoO(38+htpJ8<VrqRhuAw`_~&W~P-En6J0=4W4Gdy`TMj$6qfRX3kq~
zuHGrcJ|V!(eb*2UL~{pcWvr0AZF`eA>HK(2F>8}nb$+7n5!1Zo1Nukk)t8Pa)*qp$
z_4p=)4PXj~JHo^KL<ph+aK6xir9&HIRuj<-Hp>iI%x3N-v6cY_6vzL5OcA;FW8$Cd
zHu}?li=c22P&UODyAsvtE<9Qq0KSf35S^+|LmZ<1(}jr1@tpLabeLc(0!T$+PNfko
zsVkVrTx%l816;TSrYfBW1L1JbDn^}Xxm7uNnhOvA`q3hwgVUx~T*5q96Vn%(U<8O!
zl@wr8W<p{xg?-oXJE2p8ncS8?R9Ab*v`}gfqckF{n;MVG@ty03gK2Hdi$_EPTbrqY
zh6(C)@gOCD8(n{4da~z;HD#Gl!s|u<8(hb=5RTrjy1Cyy=kGFQF1A)lpnDb3=dxZC
z+ps1s{`A=CVUE<0B&##bMvDZEXSlUsZ<sPBM_a};25ho>q{kNRav|b}l>Qr^qnK&Z
zzp*k$LJ(2p7X+0TM5P~rJU%zC>00qfK*N_1&mf$b5EvN!45kYx6ty{a>~W8_<gLNZ
zdxD8Er(ZrEin%Ok`zya|DCobdp}{Q9!IkJXCHL!Y+G96YXe-gJgm#P8vyaQ2FH+5&
zpXj8PGN*Maw=5aH$2#!IeHnqIX^znwiMkWF6&L-)pR57jw@prG!mc5<*g}2^`7;}~
z5ER{7mvf%7?J8Z-5C79<nmO0twrk3H^7b&xkavxLOuxw4ql^2ew+U9l{wCQ91D*3U
ziSf@4GwkFVL^if41)A)1)p<1rBPICKB8Mt=n<nZ*Y`q7B>&OrM;gMSIy$=F`t1Xk?
zk7_lK`nBOMss}klhBJDL5bMGZ7VBl8_Zr=Bqwem*t{*F<7cO)Zjo=H35ld2IQx~C2
z(}h~o#}tmNQC552$wL>3Ok|y4vDba>30H~&L3$~Hlk}_wejoOTXKh=%1-J<ZB6FsD
z!kOEO*LKVlTm%aqHOMe0euYngW|YD@eg4Qb{2oPDAZ?yKk5%A4p=sddX6bktJtf~}
zOkhfYw5vz8s9e{5Y&hncK)4&)n%7}#<99!6X_1^W**J7$P`B?VEp%faJauet&9HyF
zp^9M2H9i0w-O=g$I(vG>;wRK2<774}$~p8f#YzE<>pK#`R$exmkB?s0xKeIS4F0Mh
z;r`H{&|M`bU9rC8M<``-nn-{t?63#W2kGzI0RL*1J=xj&O*e0vtZ6)UP9Xxbrd;<c
zA~xO-rMbw<9b2j57}8a}H`-$_KF%Mzzw-jLU4cCZs98z_)cPDP3n<b{g%=fNa7dAK
zR7jDF3+|M!_sx+xml~YAXg2HV6gUTKRYJTi6O1|h%?xOjg0OkfyRz*y=WuynrTX7a
z9#vUWHWP|;gbYT8j|dct<e{B;mnn}B)lv;x7KyTGEG8Q4Y4yoWT-6jpTv$+k+@MbF
zH!M@=*7gd(k;_ww)|R7^Dp8Gtab^kD!H3f7&IAd+TY|~7-6O1NAR(D=2=!c&(>5Gs
z=wj;Up-vovQ$Y1KADJPfH?x76{(JkF6sPr*=5G)sG+a-|n|zA`g5eUXRfW2lo=1a;
zhZSNWk0_nr?rrVDIl;;RPV{nTnA)G2=O>%7R*uE~hdt(c4;S&!r0TTMGOvoZEUaW)
zx_4?CC)>f!EBuk()*=<S3OMNBNGQpU`T2EhWU89F6Hz`)O}n8wN93w$lB*CryoI-W
zafmhs*i<d_h20Ms#F&wWPr6)RonmF!rg3+!BuAoO8HV<8Br3mj6rk1?v0;X|Xw?f(
zl=!8_iKBfnV(oc~z^<{9=C}iN65y^tshPI);uV2Q`28KZ+K`L~rQW)Bq0U7*!z(}L
z`>wo!o<NNr9UP@LM|(S35Lnz_9Uzsy<po@sLwTj2VgaCon0?9U8>ZwxmY415KR=t8
zMkMMlNZ%26BJc}oljqIYxgyy*1N`_QN%iPwqA~rm*9j(Wi2X|LY8G!{p$S}9f^=}|
zFB$qrNMEoi<9@3J2xAg#`V}^LWdD*|h*8Znq>!#3x^mPKYh5SVIEP9ZA@%GXqRS3v
zj4I^^#C9eWRzOr44=PKfS$<Q3cX<PfhuKdY=_ytqTEQDBkwOW;W!6}SuJ1}Pyuya2
zQ3?MP_n4C+GURzhYS!xGtoeQ);w39i6knk)RHOj>F`hdkGt5Bjv9z{lbEtab_JkWZ
z`wWv4t-|POG%*~E-$PuA2rg<c`D=#j9yhG=++kXEH-4E9dC$5W-LcEcw_+jv&|x5e
zdc+V{*1agWCc8zjko2A|y|66TF}x4gen|3M+o1dy6tu^3Wjvgbw9a=I!te}*#e@N}
z{6S+SAB{<6`Y!jM!yM+~umza%q1d`(DWMnsWVShgA$oXl?#)rKF;yUY$~G!5{ICo_
z4o0rZtDZolh!4I6DE{VyNzG=WHQF93!IseVlQTr7B)pjxcAOGH4c1uo1`VhJW|2T^
zCV`2Zvb%k@e#kRjN_n>mmX)9Njqf?p%U&md5cWFQ$<6^$CB}t52set6LMn|3x8E7b
zg3dt*px;CVXFQm>F<{z2!{<dm&n2;8=7pX@s7I)0#;_6bp}60>w*1~+7I^-uyZp83
z`p5%mlCFSWFxoTCVw@hU-x^^ikPS_d?pGuBpz*i)zy(>1I(}qf$Y5ZU$#o4IF-4uZ
zeM4O6o0~&)$XK+H1RQ224$3nv6501zLZ47$w=}QAT=6k}S7osxBEC|zyM$bITn!me
zn+P?*AH?mSsv(1l$)z~K3@3v^$fnroG)U6@|5!%kWX0eJB>Q_kNH&_S%rsqCCrBX7
zQnJ%<e<;OHT!>tQ9b7Q^$ta(cDO_;K@hHm+m$nb+ywobtd6MhNZU|)8qkQ3F9)~$~
zH@l-eg(mZt_~O4u`COG%am9cC=DSn)Ii<M`I*;mNln*-D6Ld+V0<OxY--%wW7zKIn
zrf4%cJ0j3%T|pXPg7%a|*W?cxRN=)BuJ3O<lee_LKTHT*ue(IG>hLlIS%fuYJd!N;
z0nRnqV%<_7yJbo3{jj5;*fig8iZA4V)CU;&8|#11=Wxh-DgAN}mFtPBnR&Y-c3-kX
z4g_!rcfxmHn4t$ECnR{!apt~P(|I@H87aspV)yEa>Z_;PBOXho=-4k;8;fr0wAqZ@
z=VkV3*ADq}R6XQWxz+i5C`!3xR%H^2g{baXTQqI-hi55R6hLQ!HsR_29i{zul%inK
z4-H5~Fw8N{THcrPOvaPv46Mv5yGRF`*(kJEx<b|zy`CT%$f5S)v;vfaSe&Uoz>Ih0
z+aZSgOf5VPX`f~1kr5+y|JE4Y!HF-#Y?~2N%Aw!^3<1F}Ow<dnw$1`^TLrk`9wtIA
zZOh)MzAI?D*Z2kJh7uNCcHOXDb}?06N~(`FboJZ6dSJT*aCEPyrItF}k{_@3g-*A^
zM}57>Dz*)ys=P9;#jcs9mOB(wAFtFjy6zuB)K9o222Nn|LF07N2}=_7L$&)uBPVLp
zSz8cR@9h8h##{3f=KKiM-ocq?YxqRGIo1y?nUk<{U)qUO)LHI>mgl_mURpNe{5*p7
zvPT%jrIw2Q7V8zIIGiSe<Ba8}3rtt*X#f5x^KeqAA+WQSb7VHQHZnVaA(!xQRB+?`
zNylb78A3^XGr=5_^)tmZI9|I~0cZ#aot&_Cb=I>NkksGI3Z+>`m?0FLOZPe6jc#7%
zfK_RP&g1hgsD7L5yWj(C0S;%(3N*S~M?rC;&u}Af!g#;+$*7Zq0^E(VO;bH@-as@m
zwHY-wj5bScd?S)z?7_{!v0$*KjfI?Aw%1%yeAH^uQyW_gIA+_HKd!DI9kY#vQRGUV
zr{@bwG&T!-NFX@B3Yk6v|7A5k+QoB31i-F2C-ZzZ-bdi(pI?{t^vX(=UFtB$DI{yl
zBQtR!EaFXf2z5c9y+BV|Rf~$5!otk?Ve-guF)U`g_6stOZ7=tDUi8vlXLalB*X|$}
zr6(O(-J9?L71jRmczQQ1kQ?_2n@t&Kts;~#Y42BNwl4`6FIWeph#N}-s`{(AcL<Kb
zWf<q9@V}UtlYGyyFX}(}h{xzx%ng?rEztxBUzb|M&}}gkcvS;#RolXyV^|lwhWeUm
z=~h?0Bhnw|2+3b{DDx>tfQF(M<fp%JG#N<Kd(gzKOAN@Br4-b$sMgL+#YS=lH!!f=
zgB-bl^C3ZU8Tu@~ey5vW`qD#1vd*CFNmz>6@p>5I?cH8XeyS138wk|0@pZ&^7}%@T
zTlt2G2EN`U2EG<}7H87%u6p(67v%IdOWvX%RKqLucw%_mX6^P>OOKZ|GEb0j+*6JW
z$5&ithFj;!Eo<R8OI36tG1OQkxW=a>I56lq2I>~hC*+|WXn32&wYz|Wzvq_Pw<Ff$
zbveFDVhn8|c{Dau+Sm6`)raE&z~5;GO*0sc0EVa6;AONGaqhvUBxDyR3kd_nwf`-t
z1WKxdl9(WLs43}xOZqU^gbU)Vhy!Eo$Ywy<C;NJ%ZZ1rR;jP$r;s%I5WHsTPAOS{E
zc4RCdnHeBh0R$I=U^Ng-2ZBKYjiT+y{(xX@5X=CA(?GC12xbDo*dQ1r{0~U@3JA8_
zV=M}N=4b^T+Oo^zGYCu0F;YVp*rcaGsB$982h(O#6^mld7kC;j$uWInYD@TeORPew
zu&yC2mfl$5AHry>{R*W!Uw;Q*U*vEEUIf5&ruTz`y(leZOimLD3?;F!Ox)gu)m>BP
zc@fik>P7yUlqO^s3TaVv*=S|P^L<&gnQBYZr%!8M(lxxgDESaUUyfr;kh}g!m*W<^
z=_qM$nw3fTcbWz_s7@ETKpTz!Hb`>bAzJLzrbOBFbfapWMCZ&0EtxDJe)i$4Q<%y$
z6Q1IJgXh5t*L}KS*s9-3A;#te$rdv~ojnI3r+E<a95}ZWtT!{OC=OCs%{OyB{tQz6
zk~o$2h%Z<fw;9-B060wsu7Whsz>E<u#5Gj)^yr(}pHwuz<gnEXia{fMvZo3-{}6Ka
zo3TEszr|rYm%Qn=9)>8hX^k1V`3$x!d=lF8My?SxMO}wThH`#m(EKVMLLoJT+zYNq
zax^UUh}DG*rz8ON_Tk?vE*dT7eH%z5yG@eX^F+>|LIS&>LSDUi?SQKw4tJ_8aP3oh
zZ6bpL^Ou(*s`g(F)HtV}%~=M&H`c6NgB`7N#-RVp95{9UX#jeGL)b3WPB;ybvfPH&
z6rKI|{|jRvQ6(up?kH-Oc;%KeUGeGuwaALQ@rDK0XWs$@GEN2BBzFd>-ae~=rx#;p
zK?$yTt<Rp?EIwLAwo*=Y$ZCgDZfw0?y;8~AFvDOw;5br7pSX~ixv>dl|FSbiB{x<&
zC8^iDkEz(_p14?&qnrQuL@PE1Oa&>f22AnUi~qHoHpTd1?1qx_{a-eC4yX{v?BM!J
zZZP$7_c0P@-4mDf@93sKe2_|20aGBtwuTrFw_S->EYgyw+Db!GHR-F-vL+8QJK>a;
z3mcxuH_+PJ;FvUer@K~$_*e>|1dPbRwVcrXuFPoZh{3f6u5nTy=X~D)LPTS4)|6w!
z(lB4n_Svzd!IAbYstW8Pu`tu=0tI5OsXz)8>e6`or8!0^TG`$b0lAey@TKPVgeY#b
zOGtpbp<slm$$qe!;#?JU1SMe}A+%g`QY{oB9l2zJ4P(Dlq>E%u9`iS_Y|%Pn2)HJT
zTh?frz?vu*2c+{v7TI)n)9=CW(Wimn=_a2%;*?2WN?_3z3pkmB4QJ?_!DcZ~Nobw@
zwqnTdDTU2V@vPGXN+?N<JUQX_h*qYOCue(cjoP&g$sF*75bL>zhe)%>iZs?i+@%71
zkd1sNV|c%(qE)8B45MLAv&}`x+eni;6J--*DDx-)9q3~VQHK^#w=7;2mt<r2gp~S*
z3+hA`S@i6bJPn*tRUH9O)+*N3H>w0vAtNUJe4;D@)wG!X|21cFBH6^zv&zb<nKN-T
zN3`{xw|@kf38R0jwAB~d1u|^eQUk{qIvrMejM)+4XFT@GWtSd6?dUzuObhh2fc$Ll
zd#E2CL^#*X;0|u>%`N0%8;f}6paqTSWrJ*NUJM9bMCH9)w%}_sOUk7YUk^{o^MYd(
zB`94IWZM_U&LU{nDT%=k@#BkV6L4(`04&>G)prR{_f-5deKxx79ZZDOb{>#~TMkm1
zcFoZJ7MEb6NUA|53B2TBY?9#OA-OiO<(qN^zv`P3aTA=rMa4qshiJ0s?hfpp*D0nm
zi%4&qEin||nzAq`QXLRB1Is!UhQFtm@6L4wEmK*MCRiz?#|%-QokKKnCffSPh84)3
zRMq@u2tdLHJ%S`U16b{D`E!PF@mFd#?%Lvo9oXoGjjXbZ_d^`C(86-&!RqL>WljjW
zL7EU4?)?|L0^dc*?0%H?!k7KrX1dcDIOfkww%{h{u;9+B5~f-}bI4h<z(Qwg7&}wj
z37MqsvAN4q`kDNlBPVCi8L+mA6t?t`LWYoJV3lG_8bK>smNivxo#&k7H)_o-#n(Za
zLSzRAT(gJEU9<1ZnJoG55_bJY?b8p5Q5zJ>Crd_8v&9PqaPYUnXHS{KrM;*)+wIWj
zRM~S13MNam<O>cdn(8O*5!}mYxEkmt$xI(WGWcIm7F9+$Jj%0_Ocz;F)($!UQ#l8u
zvaXVC75O@M!x%leo>j_1zX&u)*||fGoOkkkD{h_vQ%zgftf?tc9VHRG0<bYl?pJ8D
zD2TA^HAbIBR@Amge=GIWlnIWtx{}?jsgmBTspF0@djuOpGnnqkNh`UlTh@-$ar>CK
z8amGZM=cXkHPF$I+y5x0lowWGn3%L$n@tH_l&5ac{YKJJj^%5mE=uGNd)@-NnzEl+
zlO?R@8DsXY*)y{2IVT|1XLKbg|If9}M*4r#eUGxC4G*sJj79>Jv<-A4{<A93Z8+IK
zBEHL-0-(K)+5<rz`+_*2+2l`0_8bVkjLhI`vIbp%pWq~OF?$Yqp&df}m4S^r4#+An
z@wd`uPiv$kWyb7dV%T%^=%N9Mi{tDKy4(+kq)mV^`}DyP#~<OqHO%j@JHc;E961mb
z#?%dTac`FFIl0FifXU+_=Bz11Z1gcs$qg%RT`9>4d!rjVm;ZNa<NTl0HUe2lCmKlY
z+y7tGK4Q*N(kivnM*rVU+h?qF5X*x5RVro1{w@||4Vy@jDU-)mq*Xt9{;#I3aO;Zt
z3NnN!e+zCF=oxz>gxs}Gf1WHQ@M?w0-shw>#xWscs|>X)rQ|s-kTo-Nwj+WbMo_iO
z+qkcg7Zh4>OG#xZRi{dh$^5X)T4N;ebxqP6v*1?PH|J>*p8=Uh=(XraI!NFW$gnY`
zKiEMAe2<qLJcvR0$g804>uJg6G|D-=Ezm3bvWiAveobUT>2DtsU-yi{`b`)Z8(&Am
zEj<M#LlW=7ro+NDGf_Q5lL-|nVToQkl7~|l<;JUl?c$ptfgZ~n`ClfqZH&$!A0d4#
zuc5B~Ao=v(ciq8jOz<?R+=2Z1(-<ekkUr2p+exvYw@y)oqk|r>4m>B-ombVLf8fk?
zI=E%Mk*N#<NVCF@|F^6HT-g5toIqp0ZYvmzk28kCwtB!3tBt&#g<4(rjXa6(l!X&F
z`psxu%a)OB8MfphM|D+?Z#a1K0EiiKwLeNO(WI9XJTjcty{E=27vH8cN5&B^zLY&j
zN79|7TPC*Fs?(O_;{e;Aq4sp7s4C7<fmu*Y;MQ?8Xs?J|Rd0hiXoE%Q91YRlYy#O>
zaAfxE7mR}Bds$cA9fO;77~*@Cg1{oybsb?O4CBF!iFU8>kL8aqIN;>ol9An=mZPXn
z1$uHIR_K=X8A%;gQozmF*_Hhz$|4^d2@Gc(OV=TA)+J9h<@<8M8GYm0vE>U7pB<G5
z7}*!ib%^GAl5?jbT{E=JJJcJ@>Wd6+C5ko`{_QXZ6W0&WEVG=-koejJGyV@xx@9&B
zP-R&hc6FTAal!0$41iffqD|RyoJax>fbI~2XLNN>lO@;VKg1!!&wEocG#Rxd6G8=D
zw`3`AE<`|Pc8v;xpLO!KH!O<U>fR#5Qns7yV3#S$Cfcq8%44X`E$@Jcp-Y1zZqw=7
zN16w%4j8~PG!uev&Vga`rXx*R-RMlU2sccEaFkZJ-G*VqvH;OWB-bn^LwZhmAXiMX
z1ZNFwH7X9!b8xAS&7&apkvPg$NY3fila7r9?@cibkS)pfEQjwz0mdSI)k=Y3*9v#!
zuSwRh;;`l*0U8->8w&c;RlDkz6K!mImSoz%!83-Iso!t5Vr=4Q-$u0t;|Vrw%*xl@
zA<-NeJ}?OqukN?nWO@GPR1TYb%9hpP+^WT3$aYv&mN`d5Dc6}s^iO@MKiX&(JO-2h
zq(ugQ%l;peP#4R+b_3b?+v0yr!i)Ei?*^{^x5fXM1edE^S_CjM@f3Wma1c&{{wy4i
z{NdmB@)w)^WI517;0f)H>f9rx3&UU;M#G=^UKEJqVi-EgI_EePT}Pr|!8n><QM=7I
z45A`E@C&L4igK%(p!_njb<URoW9jNhjuMSg@a9&&@ho5fD!goN+d0<4sfr`x0RcmX
z<a+8GXIzf0{bIndJNM{LbzGc&h4Er*i^WWhkMuD1$VlSRm8n@SvSf{KrH{d=hUSqK
z7G*?@bx?#u1XNdY-kJzw2oj7EO|Oltu4i|}fTc^$t%{r;GHxBDXedg?2my^~R;z97
zN3o7QcxzjZtRh$a(p61ab&x0HZ3AMh3Rt2uKrA&APuYUgYQb1lZA)F9_mp}JGud8*
z@ghSt_|`T<`mCbGT0vqa?=)B2cEb^~xD?gat^1Trx;==|b=5_nijnH^4KUeK<pMOT
z9dF))pI`WfrF3mwlVJ#j$GL=8H~{8;Mg<#<c;!2it*+^9xmJS76I;lD_fFEac-WiY
zY*}Wp#Id#LtLI4QE`rg~+MAcYGr3*dYhh1>)daP3CSWk0!?!7koqGL@RV?`_l+B4=
zJoCaR7|a;0jg&8MTCv6q4x;?Z7k5iEOwL3A8th#JnIUT9mF%u&;3^SX%h|``@1r}I
zb}3tSS!BwNyeTA&1G%14&Zc2hHKX(2EOW?ox8YBdQCE|ou(w1}XVqsCYvz>F89tDd
z*BUNBX-0Wq_1epnad37=a@CwR@e@Q-fCwjk5imu)6~ja<`J`>$9L5tEaRo2WDt?8}
z$W3W;DRhc<$1jFs&w1=?oRG&-Ui%3$RtF2K@OCk9=jZ1a42M7oK>lN(JQA@&)hs&x
zBcWAp@f-@#&<HMn0t7?}rmZ3(Ci6gP6x)PEOipWK5K>z!6%sWH=T46w5~Z<}Hv$co
z=TBGR?PBMyuC8tvHgyR={zIZX60uxT79IZ~(JHri4vGFBdtck!Hjb?OeSd||oT=I`
z8^^MpOs4MaR8b@)aYB&{N!jt7y2WB7+GdSjJR+6Ed+Pr8+YOKsUu99EED+&V?ZhHM
z01vv+-Dot>MQAwZKMqWy7}HKB(G}|`8f_BAC%`y}jmg8|&{dQL$f2`n194~D=<?k~
z16Xo@0}1gph+;chNteGgLXuRnl$yqg`^b;xapSHwQ$ski*{-Awjz(Kf<WfJp7mFL?
zDTjzd`>6mUhbB}CB?lg+A~>8a^Yain@HG|Ft<esrGDtrHJM!RqN&;)P9hHL8Y*VVI
z(CcCNF{QGIcr>N*7<n|Mk|?=wNEIUD&I?e0k_Wd`3Go{4nJPu~gRmtR{;3qShMQJN
zD2+C)$fYHm9DPe+;pY%Y1{QBi$u+#@`=N4BIAlUzd`|_mYO>#{5Dw4m$APbD4XW9P
z;npx3eH>2IwVu-F#T3e*;YSeUfbnJyB>*<xASwXEB`fk`6cy5|$!1XrAikN91Jfu0
ztJ%g;0!X9HBjZw}x7TrEAm#AzBN7Ur@n$5YAU5AjDulx+L-JxOmC&ro#!@LH-dT|Y
zgDC~9*(Os8N~4V?@zU7i03E|zmIuU-Xeh$Qo86Sg*nGpO7!R*J$&2Y!Mzto}PUV=m
z=SB{!r!=x=n@?#hjkcc#+}z4N;PF=O0nfK`4|utid%)|h+ylOD<<8Nm$>vZ27=9U#
z0|RKl!>!x{4sPYf$nq#@9}jj<77jl`AdieU3n+=O`DRcN8a}y^7lWvnVokP+$`EnR
zhaA{PNnFh~l9EUoYbm921B!w;kZDTYB$~#hqD+A@1XCDR02TKlk1Be@2CSi?QD}$A
z1GW$epLs(BG$M0qrz`Lo71}u(?TqLh%lC#P6CpO9>#~3%ODGR)PkV?Vd~0hjhpmFr
zWf2d@G($U&7kYuE#|xB=&DZcXMUm*s;cD(uFe@o?(3-Q{*e3Y+qZpBUd{7I;Uc-^3
zazAom@)c#X<jQ`?<>70(<}FJs$R*XdF#8he__)DR&G2LT`p-fUxQ8Xd_}!Q}xxtAp
zuEPjqdFMAJ3U{L!vsd*cCE;#Rn7yknmGhDdQ?MwDCs#&AF8^TDm2p`@MJ}nvg(;Xw
zL&y!5YNlY_X_}8O0{5^d8kWwu>84<*9OTRtOo_tXXx4;;tW7rsGY6HqFb0bcUvp(x
z6r2!kx=JoT^vWsaxG)M+2ShnS!;z1$L>%(xB`lC2yJ=^ZGnQ--i+fOz@uVdg;n;AG
zVOlme+)&KtGv&foEKSqOmC;e0OtR_PdTWYIe(A@B-I&cO$rm7wtjBTz$)5pPEKr*6
zVB9JtdGj*n1ZBf*$ef&Px*3_v<;sT{S(c)fFEgYtduHP`_qLp%{L+sPGcuDulP^F#
znUSRel0!4HP@pv56}eqd^5>1ri_4}PlUZrmaAPu^(3T5BvM@(4S4K!a!D!QUc4^8~
zKIz7V;h4-d$`2TBjx-mGL5_~d=4D31-HhczkVmTVaI`rk0vnDco6VOCTd*WWF;`Ya
zQC`)itK%)XVtJ(<7dBx!#VSv5xUmb%L?TBvMv?U3M?3Ru9cJYrKUCwuLd+*K=E6oS
z&C$%2rBR$vw&@CbYnohs>Bohwn9VKA7a(rz#d7h;k=;=&M|jfLJX?)<*~k;+IItWG
z@;P&1I+o|D=F0XcNvPX&eZ4(TFvk?+!hFo-*5wQlHwNSuA<2;qQX)*aQrtY-kOdNw
zE81~jMJ97xb74LfB<<$P>d0muZn}al$)wC9&A2cTH%W+jfx?YZSS0#5vL>>Uf)CBh
zv;CKpdwfuf1B)-0*qaNpuPj|TS9U~Ue&wcX;cZEyxuqT#reG%3GFN!GF$zlsBS&^d
zp$OqfP4jFc=A<G=bZfY^Xc@9BIek-*<h^d}XAzTPIkM$Q@{J-EfZ8Md{E6{!mOLz#
z*1SSWb4Jk!_Fgk*;7;#Z#4`{-JEA@`1lt+vMM9x@^9O8JP^~>vku^!Ziv>eZ7%K2<
z57G^V&mAUt5$HA)G%2zrnr_(=vG<V^Fp0=C9Y6^ZFH}nImhy#65O3C29-``*oB*@r
zPa|0qWz(_mjJ=c>p5JB>*$Ak!-CAm(_QH?^z(b%oH-f52I{{iZ!zdo&NveRSoIt1c
zE6JMBRb@y1Y?}fIc|$jCMe8>llr|cs5COgH!OQn`vFZ7XD5O}HW0-nZwi-?x5oS#n
z2-A0N6=?^ud|(m<O6!d->h^{WrwU3oYao~~`N`U;qE21R*@T6XAPG&;Y}xDyVtN);
zxV~>2py=I^#ldGH(UNx(Hk|c@t_7l6v~i80()GJ3JGN}u4F{%ZqB@dfr>hI51WR{S
zxFd5*<pdYH!xdA|K5~Z;rF&2KD3di5kr|qBC?*D$7cr!UQ>Uk!B5<GZ*--@>6fi7v
z^^s=pXiu<d<so^5_4W*`)GY^KI<Z#_tiMsi*MgB9tLYjD3Xu3C(N=D71rO$6(-~6v
zOdVtqKQ`E=h5wt5DJes;yyb-FsA3Waf}&A>U&Hwg&83fM&dR0<LV^QRX^rSsu*Crn
zh=zjM2X?!Gb%$UpAoMuEB#4fw52=hmukuC33`oue{BQH0MquphkFmolM%$Eo%8N?s
z>RpG?{zLao*&0yG{3dOg7q8{tu}X@xRfN_M4}!urd*TlK)fAF6oEp>>Zpk*f_N{92
zj7dPaO-3UjDh5BmGAed(s!SrIOIzzsvj?)JSg@eb`XixVM=a&3p`k0*8g=`oJ~A8w
zR~fisl0NP0i9PYs;?s>PMVm}LRW}^V1~R>jg~?5Ig5{RjJD^uBNALAOTD*wmnnf(=
z7NRj7`#6V~goHDPLc)E_O6<nu)ImI8X7@}-yc0pwS_7qLH+1R{fh{>364ir>1!27(
z9ws>s)C~}7NL7x|gH=Nu_l4d^lPu7i?dh`QPfmAaT6QII$0V_CXoNr&9G5KOAeZ{l
zpgV+uJl9+u1a?}=jY@$<Yl>#l2O&i;P_(@W;@2`C!l`i}S>!l6mjl8mIxY(w;4-jA
zW%K6c<4IQx!_Y@I2RJIhU~-xuj3FN|fU9IJ6308P)fmS@r53E+UIg+Bvq0j>zB`r<
zld2xT5QP}i=5_%8SwCsEnH&e$YbhM1#}Lo2u9y_bF$`lj81O$fPjgU9U+pP9z0po5
zisPmVjt-Ni7u6}~oz)G&u?6F0dUTjPN4)_e(FMycSV}ge*ntu${>CFp8ZeDj`q3I?
zcNCp>EW!YF&j$*yy*ixWxNQ2|KpWB)G)XX12jpJfy0k1?eN!uGqMje_mL%F;up(2~
zly^HNw{C?o3Z)Oy)^vpS<l7dQn|UCAc6y2`JE|_`Jo_($J3oKRBE1CZMmBBb&*ZT)
z>(=Rx6jdT{n|>}(lluaR2#<DVB3EXkCmF8OZ0Gjn05v9c5$(O%(B4PaA9P2(X1gpf
zDqodE)I6$w>sTM<Tk7iP0~Vfg!MGDg93Fa>{=|r)xIqLJUH>9Te~c`9C~Jqtb21<Z
z01n~8H6+I#U=XgZO3idWXPGZ1nrPs%4wY@ARnInfImOx>s>Sg(x)!lx8eIj#F>DDP
z6WodE2g@eK!dM9L(r7jkSuoYR4UNzpZ<~T<^<=Zzz{nMGj%lm7(rB~{L=#Zg)DxX|
zuFLU&p<UT4IT{p72n$z1Lzx|~=$gJzP2E&@th@x#yH~O6nh&JxhQcOijVQgGu*smx
z?j>w8CY(h#x@uQGrqelpcXI~zLve_~iM0+!ukPnSwHHrLcM*n*S*^mNHg)<@F^EO2
zXv%?0yi;>tbb^ZP3sWIs=_9l1sW`f<kjYsrr#oWPvkxd0%^<;heLS3v66Da3{nKNz
zaLlzmE?kq89;`ED%~k|94>ICCHj>;O;gxGWeaFc6tKyiLQ)5XS64`@P)?fY;ld#BU
z8Qygu3AWH|3az2UCm44;{=#H%ACc;0v)NMqe0kN!=3PR>$g@m`I>noQOKyxt)HO{O
ztD8je6>`oWU?nn%klc4d1-2^Rq%ZK>!IEVXldTN#w10d#A<1?zl<k3DF(ySA**c3R
zdI}%9_CIQlrOLMsBHd+0b;;<8Dg{gstAXk?0o2;`<Bwiosq;s#?Cf#`!%&s9UaLyA
z(}uH^&ao=c%4o+BwERrtjCRTS#u@EwWvBBktU3lWSO)xHkvO7@#1UN-tBM4;I4@bw
zGbI8B)gWE64@s&>rCLu|9SKrJDs`?|4DnB4QY?kv)gl;t@}2CMvNR&@496OABL#EV
z_!016>!qOa158$Jf!OMTX(~5(3#u|~^saCUUc6DqGx6f<9QmYRfxxV$@t9w1<;5mv
z0JHOtH+Y32lrxZpf|N6iTf}Meks5;dQRrhz4m`-z@NGd5nOxyXu_0chD}JO0(RW;W
zUtcpB%9ew*zRYk(T%BJpe`OvRJs9|rV8ir1@M=dfae4Wn*u%g$yo%DW6y}NJJ+{M4
z-vF@%-t~18nG|MYH7b_EWR8km*}j$Wni~MRtG~S1E5?*w$YVR5RdPgxw~9T$dvQMP
zO1jR6i-t(iHSu=Fc71uxJ~mhu*z`iltSMH8><yBw^RCvI#-r`e?}!N?{qo_W)_|;I
zK>})F$a)20UH@{yq>hV@{zti)@xUGprR$oC)IVmn!B;t5CF-Ue0opeJl8y|U@bDax
z{5cBH+|UkViW|P3lcgL>HXIS5Rj;Rr3Q6rU)HTJ{4?S;vYEY5%5W1FQ3d3q=lNy7H
zk1X07P*KWyVc2XyS*9abiD|;H;vturH}mIy$Rs05sv4)RuuXNxqajRs3J?jsUby*C
z2tm3dJjS-ip{jw>AFvCH-p>p3sJ{bwiqG$y8V7KiH4w}=TVlogAs2HtbrPnvN<t$_
zsV9hgXHq-4@v4Io0t`d6%xzQORVJ{Rc>uw1%5_O-&F4CdaoZ~cYv*G4?m`lJ*B`FM
z_kH;^XU)%k3!Vdie!p-?_b86v-liT_8wAHPWLfH)LRFrv)vI>c03<L}AB&0i)gOC3
zcjix@tBt@&`>5%+8jD_?2XF2z-Oy9L2Y38z`Lkx-BLxD*Ti&~4FM{(lojObJ-WgB-
z`swU1e?Iy5Pvhxg{Feiyh9_UWW#BL7|Ng1->v^2?{=eS5IkO+Vv+-g+_r@W-K6_d~
zy}_CH{b><+ld~_+XYSc-F<DK$Gk+e0?i|{?Uo6kUNADldpU@w#rtUH>vhHDUekSHB
zb>|cO&R_mxQ|`=NdeDR^TO-vzTij!TqT1fPp<T`r(fba6&)w<tS;AqTQ)Hz?ET!UB
zGH#>e*7;dFLDRI%!+Hwut?{Ebb76orc#?v(W!A;`7>1UYCA-5akR~;t%g?~Q!Ij9A
zlknpKut@)i^hgRoKd?fW@^O#ipL8G=(O+l3;Yj?RkVe0~B~Kz${*nrX-<A2(3QVHS
z16tslKM5bvFrt6Zhf5f@-$_;Euc*&alhBh`6c!4`hw0*ri@gcFFqVwu2j7y>4T8nk
z2VR_rNXQdQkQ(P$@H`(sE*JB~Dv&1+UXVgIUd+zjDHL|kgT>Pr#><<Y6KbEE_}`z&
zCk1#lU6a|x+zQQx2u;Fj`wGpZq;lqU$<1|jd&tgUaUZslvz45!<YW?DD>);{xsg+B
z$W8a&FIb2#R?D&X1BgwDj4@}zlhDuvcqvHJMInsNy9@fi2H^QPUwqruZ?bNMNl2|T
zsC5Q0#Ev{^=Tc`7{d}u(j+9}EUe;IPD>;I&ACK;|$VJ|2<{w2fUtP4Cxz)_AW^Ofe
ztC@dKYD6Z~bCIj@N72okY2~cZL7a$H;cfgnO#n(DTK@d6v}g5y)GX5fvlZ&UlKTMc
z;%>dktyW}KE0%hbchrj8eaY38;-SuD`aNp3Wvd@s{n+ZqRzI?cxz&$9lzyc8h!Hh8
z^Ja_X^V+eym`_$dba6i6MmK^a^&jRlZ=NE@-@$WmzVgpwV!*Q$J-)_AIAL^Bf$MKG
z_5FytcQ38WF0fYqHbnkL;%VP_7nseCyPwp(E)cs>bp=AVxalwZwS866^p`4akIOuj
zT_66gqHN;YDl}cH>h^5BMAelw@71Pg*Y)k*dQhXD-&DAB`;%F%tz&gNx4m@h1|QY9
z`{>u+gK@<keDiAV0IhI$8r1BON!7VK7yiAE0QgYGgnw6RI;d0lkm{;5Ua#znD%`mP
zi%D23=}CS2IOD!f<0S@|RMW-W38wB>e*AC6YYcDp#hXmLN$~9)u-y9(D=@^M<#Rvi
zP2J$JV8L;*eXUWsogrDkNW{P`Xs%OpbJ}8lvzWrKsb__YrTb9SXx$hMFwH|WH%no@
z&|+?(Gns&l3xsJ@>SZ4kW$JT*{Ig*(13BzxAyZv}u`S(c!cY+zj%<j=q`zFOo>JrC
z7Xqp~Q0NFytS5J#U+vA@@bSFsKPVu<9=v5yl=9W}W#^Y)E<Y4Qq}^cx;b`uMJ2+4y
z=9Q68yQ^golJ5$T-|D7hv9l!1p`Lzop96wm=zb^vauP9hpi5~TO3Ezd4)ZKEVL#^!
zOew=#TF<jDi|Gymv_!fv0cGh=9=u7U*7W=PLXy2KNLkhq6k}j7hHd~)%Y-Osb3c4u
zTf4!zl2QK63Saz!GE<)u(b-+B<`Z}6dx1XBxJ4V|G%Un724LY2rW(Oy##K^CDeFDD
zU;V|B6Xght!l^&@L*X#9j^WVu$HjDF`<X!L`t0t4+tH2!gNR9BvacRt!+;b1^8?^3
zc|P%7UIO$Z_XIa+l1`A*9So@#Q{L0U3Av{J-21k4pH40#YLt94_q#t^%?uBu#QeeZ
z+=;z(=YdP?#9#-pp3X_mGPv8NA9@whv8=T43U5FMb{}f5<?0C+sjIo_%^$+Y9k6v6
zo@!5N$0;WQWC_ztbwh7Her`DLA(C6y53La3>@ty9X0{m2j)v?$P+pHN4?cPYlsPOK
zLFQTh!yKCCX8urg`YL=_aEC7N!qpQ8i>c5@&a39eus7cnpcS9TQw*MF7cyEE@X(uw
zUE-eOgeAXu(<$-Ectk)hy}wr;H(M9q&>lRlI(}6smGp5V&~P9O+W=nn*TkfMR1xhP
zzw3U*<4f-3xwe?5ZyR~Lb6genf@~yw0Yj;_d-F(Tq*|ip?$JlRb9ZpRf1i$AzANZS
z6g*I&`Q^k7U5C)V#xpI@52!Y(wOU{Hi?hDm(v1o|__n17Td7gl0V1X=_TY=RPxD0~
z?q8lmk4l0nB!Dr4|CGgi?s280TZIG2h}GFXsjxx^0{=gI5uhm0f3st`-%Z3|sjLE?
zPj|JaubK|5HQpLxyd8M@3Z|nwbuc5QGa*^YYO)k^_3k97=~wvwU^N~Sd#Bd^q-w6%
zqkGq%9-%w5+C8)grX>j;U7UlhD&aulwyLC6C5=`kD3Hi$yc#dyOVzoPz{W4=Vx#VU
zBx>EcCn%!4`qtmcDtGR~*nJ9DOYfrg0ZCU}wLhI>^`}$XpR`K-?JZS1_$U1fOGh$m
zvb=I&hR^`^`A_&JIw?oCaiZgvG$5J0O{-gc^5lk(`I<;SP!CI9Fkbp!JkW?|0Z6}T
ztOn1|hFNupO7kD6C?mHRC~BxIgs%dkoO3EW)}Q%QprWnZ$d0PtI-r7O`v`em^CGJD
ze3#apCJszp(?^ygOZ{|u+LtqV&TG!UTNf-$ze}j%=p)-0*~iGb`wB2dmK?z_<xeBo
zdYQ>CScE~c=8Eb^_`fcGbWFi6NtvrIikR$8t+XlFWGd6`sf@UrzUNcrZi>3g2YT0S
z^1%*6)F#s{H|SVNrt8n!tY^F|rP_P=s!_6CKEC4e@t~|{v6NyX=h<RaoGP-tpSF==
zvzGg5V-9Ts%!6*HWglp(23s}QJT*u^->L=Idgmnf&~9~zd0$o!&I)>-_k~55N3CC$
zy23Vfkj7un3zofGD0_L4ICRI$#d%j4Nr`cfeJq`Km#G|E*}IB%tzHsr!Ractm2cxi
z4b}IQ&$8r{V5p;hQ~s2%xga~}z6}_Hsn~b<CjP1YvxeF&W$1_l!E`L!l!alwnV){D
zsTJEC$t85CW0)*kH%i#34l<)})iLG1Bguw6$hUD>LmTKJ6m82fi$K&dM%aK1!vr`K
z%a+ZWTbYExIoKH>)_f9$m#rKG<MLl9=-zbB4{qoIZ}-Z#5rAfMr-xRK&+>I+*AK0k
z$ZZ%VTuQvTCn9@3em;%>Nw&9I;#rh8!IPKTc&kmAV_RRn`DC#yru(+Kb620ZtI5kg
z{%n_-@swf&Y<GRuX$yo8EcX81|L#q?848s8ce8g7uz~`9`(Z`rdv>M63YNg1iI46Q
zy6w5MYLHH{*Rlg1yxL}ohwi_6#DgW122Zo2a3oxGNx};-8@||CC@_p9Ts-Y0nwi`|
zMhB1SJxJbDe4WD<1eYu#SOuOK24<Q7>~9_xz>pVDW_0+x@mNd`FX#E{8E*L4TP!Vq
z*7F-Lv@$uv3sZ)d+uEE)CZJ_4FPDoH&rTLAvRuoBpPXM5i$RLuw5DCp50)XCMHOwl
z8UfYDs%^Xodtx%X_X)FYeVza%3*Vt4-go$W?oOxA5)L;nmjynB_tyB)n}N0)Yi{N$
zf!E*5trJ?i5yt*TSgDEfalZIga1kt_T6d3oAM^U`^%*i_f4vkQy3H0lEik%$j%fCc
z;wg{luN=O!TMU0*eYLTUl_Vn583>LO=OM|0Wyz+^F78&vv9IC|4|!xL-ZAL3iNF|4
z1Xg!*j3xqmA>Ua}<Gp$!FipTia}2ME+B{%|JI!pZ6WaV=ZT_zWJf<!0123asJbt`Q
z`_&|eUz_!-&HBZWLTs~swOPMTjiOEZ)fhxSe9|xWLA6=G8f14Iob`+4EBD*1UrkNK
zv|rY*@{MsOKpj8n*DDE)Hs=?kWNA}=H5J{lQ+~Y?3o?}P>$MQK3BMW$?nh4e#j-N4
zn(&KZZQMpJvA-H7{W~z<SDcBede~A?E}d$Ltw=(yO)jo_BBwHy?$nX-qyH3mQ)r>K
zfY(HgJ9U9%bgD6YjMlbO)ATCz+S*=Mw|nFJrt|8&uOXe+CjVGr2VS_Nsi+5AGn%~=
zy%(QhaW)}&ZAK8Tt}Sdcg0z-G12cjwzn7)HsH`GT8ZCF#jA3cJ)vwRn((p@i*<b!0
z%i*=h+6h1ud&?g{7)LPx$d)Ahrp~yX%}s*m0mCaI<{|`-6aL6dh+zFuXMk<&K`)kN
zk#z**tA*9o9yl1-ix?rpadmY@zAXPH2cx~0y|rtZP3TMh%AOsNmAJasxlgz~NBsjD
zVQW6z`)>VZS=Qz1<`Ajtz?+2e#^0xKvBb=7i{*3ag~E$D`b45qmoHo`oUN2}in$wx
z1r;-IDVk&5S++cMhVoE1?;KIrY+17%SyF7h?#oJ3O%F|B=#Z;$X_J<tYwDfTQ&jml
z&92)~w4Q#XOLwJ_pgM+*M|zI|p+8a_9JVgGvB<tN3Wf@kMb*%hqAB)<G{sc;+X<cn
zC&%%1wGJ#9_ux3gsc4ohXrk;W1s5b|l;*x|KsAme_XJqPI0O|Ar6X%XSCx-+E%PgJ
zh$#z_BaKW&>pQomV$04@mkOGbfP{`Hn01V%1&zV*(HpyT<4D(9D}MqOAedqlaeXaU
zTVoS9f;uXw|3l~3I&QW`k|2}S41i8?Wqwa?kq7NDbjUPPRYy_^6b4Fo@}ia|`?4nE
zMQu*h_VK{2TN=opkJrjTu$=B4w4w@H-D)q{jQn{!l|C808mWYWo5(tnXW&+mif(Ve
zI*7@OT0_aI3Bw~Qs;5N|Mg~0|DG&VFY8ss`$Ncj5KG<@^hI6oZz8~vu9;Icp$@6W-
z!?Uf){88EI;+rzJp26^((MWk%aE4G^p7`OS;n#0|K^K?}y{&ffUq)>*0|$5OZgF+=
z;{CK&OkPmC?*HX01E}vZ$(1`b7Ev;p#!d@bx#Zv9=eVh6Fa=@y^>Y<%*r^v4?Zn9#
z4P`xu<46`ao81tL4~73j)EM4=thuv_BKa-Kj<@dE4MKl9eG6LgY3exv=A{pv&c*QE
z#oJ(UAAWO}-rKpq2o%LhmkGS(S8w?i%mD}c^R~oLIDhoMGs)%N+%OenipAuZmq)(_
zl-QA_NUxAW;xzzK*0KEm>~I}+X3fXUB*kbTX|;@xaAn!-W$F|y{@EcB2m=94UGzmp
zLN(yv9(I5QS_0()-qL`8<{8miXkDG=GWM6jpr@Q{TkB8J`lsQdF1AgM0PVyE3c0PX
zlM3%|T*eQCaCtlkufbrez|$6U$-8$~(-7srk%ii8U>Yx;o=*&=wrK+Nu^x$&1>|%W
z=l?OYv%Cg%FmM^GZ*&GTZ#<6HiziCDRG--vc=5ThN{CpcjJpaKN(~FfmmR?;%R)2K
zluskN6`4&!bG&3GL*aAhqG$947DhmlZxm5>dcsgq@Ae)A&ka{gFR19-l_XQPEQf57
zoOR9w=>|83B@!!ec5y~R7A!~9hlZl!hNo^1WHaijqZs&!cISNR8Bkc1Rn<}D8(DR_
zg80!9G)=b!Tfv=R#UdNOSc=pIl~^MKBL<)f$uj7F9c!TUY<NeuaiOp@8XAsZ4INeJ
zl8n1fPd6Pyzm-k+LLQD(C`31volW0$Xj)M3EX8s#a-b&*_6T5ZiW-XM7%KD+s=<eS
zMU!Q+p=$|4LzVHNAzIjk)rB8D;iKG%{=JO;y(0gTaiEx^jV1~hV>(Cy%a$!0|5Bh!
zj;#!_72GgZ$wM2_Vy@gCe2TARsV_V5R=9)Kdxk;AUX^Vb+JP>MvIXEI$J9qqv1355
z4WJ0Nwb>&Sp?OCfnI=ZG+zO_K7307u8Z?Lf5LLj5PbCGq0v`_qQxbLKj{IpkoewzL
zWHZ=`9zoLylF=u4DX(J)CiEQ!pr;DfU|lBqO8R4Dk^NW)dTfkrq)t2vG88a$=u})`
zf`W>6Bbzq-E$SvEQ?>-*f^3%(@1s^S1=L}-hqgXk4=H{?>m?+Difp|vBhSaBN45^+
zF%dZ3jUPdKrY!)9yKK!^7D$}wLRU~}A9cfaY*`#o0hlQS#Ox`e0<^L|%D36KicNV=
zA|1he+FIWpkf;$;SEKg3mZZ|Ki-<LVF{4+a)OAeR(PaBpH$OTC%nsSSp{$z*A@+q#
z<KjRD*zl>USa!BFO(`b#u_96shB6BJh(Fh%;Xh#1NMp7P6I>#l)B15Grf%U>`k1X8
zI0<MK)t>H@BpA*gwg7ByLXm+Hb1m74C8MMPzutUu29~8{>Xl$HdQ$GGY$<(>N|HYl
zj26EIlB<-_O!zCwHF1~XBC4zmQNr4am@0OWEw-(am^+7~&pXtG96Q8$u9)HoI1uOP
zP_}dPB~m>@rEjK*AH7zDzK-%DUw}3!50xHF5ncVLWLZHrO^`UyBUvo?Fp``%f~g1~
zq{`~=2^!!AqRPOm05sD-6t4v{EE21-sOMj-85d`tDT9#6RhlW3d8?Cw1>vN?{4DG<
zm=(@vaUf`YIs3{IL`NOj7^xH|MhDu6ACrPADmucL1p$XfD;8y>grbS2JOnupeTq0X
zTZ+y!6eJ4B^CB`Q${;RP?-!N5$dw&Pg_Y8ReO0l=0m>gcQmv^rV}+w+=iNYbFv2P;
zOb1FIbc-S5MA2^}-nUV>Wy<NQ<PfR~H@YH`FgJlnlt?&Pp!c#QAHYK>N20m1Go1(w
z+MFn;B7)V;=sTsWSbFhiiYQUxqZsiM5Hp!FN#Y4vPD{SE?lhRvXwYQJfT?34)v?^h
z>d6(7U@k~&C5FlqO$qW5usCqnpGAC;DmTIyG|(hE$Px3-F-NLgR2?m544@xkrjRuh
zOq_F(1(+F(Kj@@Q_kf6W3n)4mbu+JkOQ8iy($tHg0^~MK9ZV%lk0GO+qU~o}k3Z62
zO^~wB@;sZEiX}sh(iwEAZH`1VIWuoHFt-t+eHX{_ZIoW>U9VU4R3!#B^uHUw1;YR}
zIR^g_`)+u70iz+RW}*PhrykCj^l0N7Q28J-9K;QM)<-5x0Z|`mNFywo9{~L7#>f&$
z(=`jQ$dNUp17+??CAy}QsZZlHK`q%zaUnu^FpNzxDfa1W-G~eZfMDal)FuY&M<TUZ
zr2q^8#YZHz6Ei1WKj{|CI%HL?r({L5fgdIf-^^=CqYOm!^vH^vCR1V~rla*o_T#wJ
zS_2WQIr}!Y1~MOGSi2#MsF|D_U4<dcvY??#sCs(YFNu8XDjHcTsKDbkwVmS6$a`RH
zWmqIAz<$JUGyx;&b5^l78g^wfw#cAtte|mulj+CiWuzwKamX5zQTdy!b^2)p#2cZ$
z03I>LL2}5`ZJC0hNTuS)6nmMP6HmxwljQEG-`~t&6I4@I#f7gWBWo1!HK3z*dn83*
ziWq}zGm0hmNWda40y8fW21eSOdN)hi=#?!PxfesKv@)Hs4A9U-E~kr=$EuipY@3Q`
z7q1ke5^EiWa|<l>nBwFG*gkjK7Q2cT+G3ntloU%>V~c9cK<N*65KXuifq_C}yUaF=
z8o_>bbue&m^OG<lZM5bnQ`}K0bh8w{*~qw!SWA~EwY)&23K}dkEkH69#59`Rz>F@t
zm)S=^;++jH;=G_EUV!FC6b&i*7}rVBN4T~pGqY^vaihq$k}2F`uya?>irAYR*WM^F
z>&Z;V1x?I(w;(QW?|>M+9{L*6pL{0P+hx{#OTNsTc1q76h*h~Sh<7-9BEf|3N^NoK
zK?9uV2LXD*WJ1x11dY5#M53+TGlsqqH5-AqevKW7988L3jd1-2a~6d!vM}-u+8&YP
zhZF*CfG3h7(_fKVgQYV49Us)7t1|j5<u5`f7U9ac)wTVe`ex9Dr4Mo$D4ysEa#8Gx
zLcK~K|8YxfiCE#FE~GCuthOm^%IM<&h@u{qvOtNEQ&Xw7tf3NrrRo9-V|o&V+Tp}8
zK%70m6|sL)y^+u~g};U!FrDaOF!JmAI{EW5^)mJ9UFS0K>(}+G&e;&1mYY|o&DOs(
z9b_!dN-6q5Cjye1Jcy?hRRW>_To!wAqECpn*NJI>KlC2`!!(i;R9nvzLQi5d6a5^Y
zcgr|x^Pd2B7N~T>^t7-oiHQac-Li23-4#BPVMi(C$e%NujHQO4s9q>#>M$n5Aq+#r
zcZnyP>6)+sqO)|?s0)Un1CuCLL!You3Z6&;?W-F&N%1N6A@>yNL<S12Ftn@*SSqc7
zmF<K-i<+5WLd&**UQV2bpkM56kG%XeQb1j%9m606!~wPvzom+-mzuh0&Bpdyi6V%;
z-)8S@TA@}Uycj^uYU~Y0Ls&)6Iy{j{m8ja~jFkawW|5jKU4?mwtA)rbBMYW_N59Ly
zLN!W1f`-XCy3e3T@bnL{zdy<eGkndIv?^j}z<Z*EELo-QBU)KxgJjHed>0!{G3yf1
z18XPz&>DbHp}*EU7n-x-B`iW~j&*mJ(j0NGIjdt_+<>UCY$^E^)@MrO4#9;qu03#Q
zN7~3D&cS3^(G&sV`lqCTRzkUmSOf)RKvxH$>VR$#<+T%VQ`|Bl*D-c6KX2CsH_l#U
zD?+5S{SN&@uW+*RzN&YLhlmh<OXUN_P^e`_Rm=JXNM~6?Qvh9c1r%BrM2kcm2vm4E
zWPO`_U7!}$?{H?u7TK0Qg1xg#F$$J4`Nl+23|#pmxK6StIesT=5)k!eQW4f23K|+D
z)J-9cz^bPFo-BByB$z2_aZv}hJ-l(ukrp|=l|RWg3R*^F$l|waB~87*C>+XOp=C~Z
za(jX9sP{r8#1-*EJt~k3i<p9Di85HjrgPO_@9ZTXzu!EDp~H=(8#0S}RLat4=%j~d
zS%Su|(aR_}ss>i^x*FnwO6}?-Ja|!|<OYF3-7B!(rqc($RO1FfN5p?BqCvWX{$;AB
z<H}S87P_DT*3*MLjdxjI>I%*pYD1Idr2;E4;f@M^5aF>tAg3qSpU^!pI&H~*97rSC
zihByG5d_|4T-w6vC?y5Ny2&j?NE7ikNL<byC}yfy(sPDOkaZu(`Xco<uH*AirS5cU
zX^_1HG-^;Q69Gla73}$S?_!IUHd3_hmn%bTj7a?Bjt?l}LDYf{qMvNm0Zo*ynP4ms
z3@T`~w3`*ZnpXTiRy@Q)q0ge_zf4s-Lc_)9W~mdk8lUNn_ruYxL|72Vfo$8+)kjn-
zUDZKP=)w;7oigh>!me01;=lZ$fsG87lPZyQTeRb94|IvFf}vo%I_iS?Kn^RGTRJR-
zNkqH(`vgiv;iq2c;H9U|x1COpb&AoSIO4Pz%*#i~*hhnBTXrN($+<Wt!R&p?j}bHv
zE8oErzT^}snR69GjaK1e=7#>5WsrX0Ji5yX#@seLAbkxeJ|*pBk3#GnG+25l?8J~u
zZk%dLENk}e%JKBC&iWEzGUq_s{l)FImGKqI(`O0Co0s%~PvJeeo(=`yCT#a)R|vP)
z*ZqLk*AeNl@6~nW3e=kJ*T<^%xWzYE%faYcI&xHr8%dbC_auMk3t+kTA6C&7C{aSv
z6j6%KF}}^-r&76{WUA1D<~lVumrvsP3K)%a*1zg4=1y$TOP7UdRBGp(R08=Yd%vlW
zsjfieNOzhrR78d~MKmV;<zn^J@Z3l4VR^N)=iRp%&nE--gQbIar{CP?fFKyU-^st6
z7@vpVe%^?y-S@x!oMCuhU@jTn(t4hKSxk2jnjaX3LN9WUR9V?Q?k@{ZhG*LPF885}
z2}2pa$-P$8C@b|j5t-e^YCdt7z8B!#8_irT72+EMu<!>{iC`t;!YHJa#gv@>V#$e8
zgmvK5AN!$jEK80B0zNLLljf)PC4v&z?5jr@k(b2FegK>$&nLdii<dL<NpOQE>G{|Z
zRQ3i5<}l^mE1ZyP>d(DzOZVyIGNMMwH*>%Hv(?P-KuXLXOwXOzm>tz6mf|iMm-mtC
z1^4B=0yuKP9#81}Iids0FU}eRE7a9o_2v)Z;||zZ&XxU?_Lg!YK=881-7~W@>@z?h
zmGZK)>}id`G~bL}dJjH&1(Z1~8bRV&{=*!)#m(%Y==4?iu;30|;DxKF=CfevBjZ)`
zV%VE+3c!lb<Ea-gj2JBnc<9Z;E^*Fr!jRv*>6Cb6JR%*V%kFpqhqmDEs+eW<MWAq_
zjMr$IFACeRCH9xYq<>Tm?Hjig?Pc#3yHpgsw61Tb{O9B8U*5dNxGAh`w}v16r@)&+
z&9$|jsBxz*5Lr=I>rrJpHH<3;jJMw_)hY(x=UU&?xI6MKJ=luAumg!2ck02H=g_0G
zai1<+7xW-m;~uelbelbn-y^^Hj$`IJ<|25Wj~|zd`C=8wxZnNqT7ppgoJ45+Og<?J
zV3P&Ql1-ak+^x;f5SxLp+rB14^l?3kE2?Zq#f4%KmU6W=PAl9aQ}{Z^64dcDo&K~*
z4NiWg1$UJGdtI0`@OoLlv&<Y_^AKGXE2~0Rr-yE<9etu$<22~r)cvxcA;U?2XC_rl
z8Z=(6Lh_g&0vYpeI^M(&nFNg24UoGSQdg%}z5@QNQ)}v<eNTR6(M4ym@kWGdklwM2
z#ux~AwZI7PiJ+IdRD;GMGQ(7c>l+W74@c2N_2Y%3Xa>D;`O`?&#EO&Z@&f+HEV#~L
z;8?^J-43PGD@Utl5G0pR$eKlJU=bc(hk;kP@sY9k(@0R2-W|Dq&yjSkA}kgmtr<w(
zM+~CCVG)%j3L3qns`(V^lbdMBHQD5vAf6CK21WBB5j1%J7bj3u{kHi?Za`Yo>k3IC
z9K}!-9(YaBI0a_il8h7j4Y@EB@L3ip818WO$raUntU025TuFr7$aL$YVmLRV&H)lG
z$&&z8eTl&$qMj^E<a$h+%cJ>#x`HMV_Yp@>I9kqH1}19a$(thSx0pc%VKpC&C96G5
z?1ML<Z>$E(;>2`F!{Z1T@xn%S`JL0PIIWo610cTFy&=_l`)rMnF8PCW#UJBc^GBt3
z`$J+B(R=O?{lXoh58NU8l`ll{XZtYQfn87sSP$%iI>3Hl7t{e31dE`^gp!mSMUpGy
zDZbAA^ng0N0lM595R<#lWEOEoqHEp&z1tTMqj=tPhUXW~@O<D5&#ye;i7jvLAnk1`
zunTE#V}V^rds_=ELLw81go``YK<QPC6KB<+>+lEZl0QgS`$Kwj#c1R^F~0YQ)nPTF
zpV;7g<6;!id+reZ!X2Uy+#&jvFGR65&LOA+%m{Wt9bibX3+ez<f<;htc{{T29Pv(6
zD+aK=W7UA@@CWIVKS)>nLAvG-(!0GOF$(BCZ-9Q`4bTVP0R74pptV<=J52lA4eVmt
z-*8|T)BctNi<k`Ev>kF8q<c{f4f%4UjVxJW99V}}V3)iCyW$ntHLt+l@dwQN9_}R=
z*#}fnAhHjrq99}+P(=aAI3Nx!3kr-w%Yp*q(6XSwIJ7KaP0|%44(AvJ#^D^>S0ply
zX)j7Kj%hDJ$T+6GWFX_1_F7mmj)}uH6`*?0iD?T^e&Gko2Y#UZ$_W&_FjNw3fj=n_
zBhyC}qgWaPuJS#+%|NDp1d{RMJ&NG);@uNOTe*?<xG=d1tOumR+nD$RM(>d46c=}k
z++Mfp?cGhFm7%J##-W)397r$Z<PVxaE~(=Wm(i2BWJNRzE8iR46kvj=R=m5nDafi{
z+SwFjx29rqxJ03MfAeC}Q#8D+w{T@5?=_uR<~Yo|qx46HB=9(&dfm!C8fLMOvr~L}
zW(YLPmJLp!!SvE^Ib3-~W+9g*@1fZln}G2~)G^nCDQJCOV!>~aWD+-+Btziq@<;^4
z(ak&?I2@#Zfw{vMvmqdkm@VG%;p-TEye-EUDrCKN78qP**{04xo=Jq2pp#SGXlD`C
z$WpXEEEb2#P!YR|q?isG6U_&<N!scRm7dd6csTPX+z6_!p<BhVWJ549^{I7NJ+Gn0
zWCp2$B1y7_62r0u&91m-EZYB_zR&UO^5P60u4D4f66=!Wi|ezsuPXWYs`&9`@#9YM
z<BRm;?1lVi@79IauHC|J#?Jb}mvrkT`zmwb_3Yin=ILgLHkFXA#L~tw=%=uSgh)Ii
zx89{bqf6w153jSGpy|*^5JYBFqIjdiN|IyQ!KbP*Bsta2+-dkUosx>8tl?*vIc-ga
zWWVE)>Ey>N?SIPlA)RmiER#Zg{e9BYSOBAwhmlRBeTIGB)E94$7LG}ZBILq8d_}kQ
zvnlUkjzsS>*N`OP$8k}G%n`+R6uzS&64_VfLJS5l{q05ZtO6-iI-B9$^_F*6Ti#u6
zd6z?xcz01q(;R~(wtur9r1JqL8TB&H8;WMju+EnpNxo4;+35*GMZG)w-=XmNtaI`I
zQe?wzu!7!QZew&bY)a(-QmKRu@WjWKcezno$7K`?wT<_%@O^YBXv@1|az@9$%G*pi
zzP40Rj3*JxRXFZNV&|ezOkZRrWcmW;^|PxIg+e!NHWR2$jURnho60v#<p#t+)hIFh
zzxx!W(~|{zWXjRLn*>7(FXN1qMejB<4rL)wNwLp{ga6<wab&{Ok`$5TNJNGolTRWE
zO3K4)8%TAI!ZTHyLFc!+_=e9>^{6+Jh1wO2Q5l#bQy!&Y^bL8lT{uDk(1fuBC%wLo
zyPbV;6~Dl?Wo?k@Lbmv2Sv{Sy7Z>XW2v3_bRdc!V?vOzRQV?Z^q9ECiwJu9Oq>3Xk
z)S$-VvDS2RD5yl?I;J2gdPHnfgn`nq9?+f1Hwc`H-DDFm%6%fyqN1di<ac5Jkszod
zQ@^fKzb@&o%xDmWYb9Hbig!{UUqm09%1|)x@CoAR>Sz9(%9;ezoOR-{h}l1qS!Aqm
z(WCX_ek1svVA&b!Cz7>N-v3BRNtrdV%B3te@g7RwUd3<8ID_WeG}Xzn4HE4-8vmlY
zF5|kgA6;$vs8jY)M3BOdF3LWN$U=FNq=PP$A44E*q<<|#1`_mvjX-nHpNlGusGATv
zMLd=iFxbb41EN{>r)=ubq$=DcnLE+abv#SR|1vMHw!OSOyF7na{Hk+y`L66UK$UrE
z4PrYX*+)VEGGEb@cZf`r6w|(oBml@;Gy@W%mavj^1Lg*dEK0#)Mr5E6NsuV<GV7v=
zhd5cLoN#2iP-jR=SmY6${jatN&xEh8KSc%k|1xb~pS}4tJ>Jn&jm9rAL87?`O9@fd
zKn)-%GPPZSA%B$~YA^&~VvDwJUV|x+E`E7-QBwAbmfbu^2`%z*r}X1auIxo=*@)vs
z?X#0y70F3y8;L$3&~-{O!h@^qgUjrLPWHh?#2i%7L>eSPLn13vk`kuG^@n%Ayvu5w
z{M?g!JtsM*K}nB5kgd7Dw9Hjvij)@GOuy11ogLb`$h4J^@d;A}2MpE=Ddwkjel}D^
z1mwwiMMo>r8MY#Ryh~`o&4a7#gUjrLPWC~>AVbA8b(2;abptTPsp}I$WK-}e``|MB
zAmWWIkcjB%vJu-P@<$UsA#2*TETSHkw1txBX3`kxWVtD?lfg^@6>w_`2F!V<kM^%_
z**)d+TD+0`)g?kLrIE{(ahYZ<)t;pqGHtAqwJCuC<(;9RjldY&jC3@-up(JYr|grf
zvv-*%m$@>X+>?uxu!No@W;HM}p+Hi^uUAyp5%X_^)cVy``K!z9D@zcy0%LCTMJM~k
zOY8L1*B9BZiPuUn`@oO`!4!4luFOED;ws5t8&h0?6{Vn}_1C%XeE9I;@<ZqS#jjVF
zA1=>l{ykZ6L<`oBarG>(6LB3&_9rT?6i3E?PZ#6Ayvf-rfd9bH@%84<tIeO6n?F07
zKQGpQx=Szc!u8L{ILDtX51V2++Gr@7idb#f6fNbJ?VQ1btiK|Dm~_08XQd1re{q%l
zqQIj|pJpAT>+kd3xXxBurUc+siA!|d`^?IH{XDzKi5{nyS)0CRdzo90Z-y`jGil{z
z9$aM~TxK71vJWokgK~R3F^ZW^7g<jm%IE2DQ9#_QJid&gNI$vCJ-N(1>ExbVB>IqR
zugLmIP-@d<mZ$Tuw~q`Q_G0PPIfK7JaM3>^!ASll@{Dcp%3k1=HO~KCtiq>Ncm@g>
z9?}8%Uw^)Ngd>o8u=L!?#0}l`r&pKc`M0GXdg-E1k1nW!#oWs@1KK9@;41R~nt;9p
zador>P)C{1I@t#onFpj(w70aTsIv$n-B&k*ooS+5V9J;l72YRIE>;^ZR3T}*u;OGE
zK6fs9MqfAyy0hPc=fI!eFC5aZ6pr8Crrzy37DN|2Xfm51#-m+NqMC{aMqL!AL!kd-
zVN^B<@<XyI>MkFCCsNn(=P)Gq?%3ND$Co<{;KcjtkG-Bd^QX_1*$9>*ER5EHJoMnr
zy`>v^s`ucIpDllu9EUH9#nf}>dH8W>PaX-grhNn_!x2B7{pHUm|Nd!=I?REQ`Rk{%
zuii577xRDr)cN&1K4<n{Z{D2QkKWmMF`s+m5MG}>Eufa*%=`Ydz%|R4=QH<gwwSD@
z-kCoSLU#^r-Y=GC;iLBt=u_yAS5tQx7g_f*I6o6}mAdl@e&;X$u_<>3Y6Y4wWeZHN
zv&B6YD5~wv8`|Y8A-(VL_uQRMpCugnIYm}V$WlsfCFM3+Ze`_CUQW|959=wsx5kg&
z%!L8g;7JPBmU&tfjK&zWy!6=})=2xP>9<<V=<>60Z*V1Y<s|%ABP=3FOu+SVzW6pT
zp<1^T-MYOTIQr(a47mnZf-7S>Y_lCs3ygG;ph>DOKd?d&)N#%6PdXHf=&!Tia4g_s
z_>}w=q4Aegg#WIf)enHy4`_jJ{v>?-9TtG}5BhKkd_b!re?@(bnt~q0YHAl%=8#oK
ztkB30z7?7q1dFi`+&B@Dl2s*S&NgIKqy*3N@#AtaU#tRo^56w2pyS2t+?_&U_dHlU
zjbZq_={X_(xrzV%nS4?JUy=pOl1-ak+^za!U;UB(5q8^GkVYTZBTA#n_7J8|)2S0o
z-LLBv0r1##F^`{dB0@oA`VaG&H&2nkn|<*n6K@iHI|nTH{=*756Iwp^gP}KDET1JZ
z6H`PgTjssZG*P`tZ85)DOySqmv%<yFeR!>g?7dTvW!<_hnyj>K+qP}nwry3~sI+a{
zthDV)+xE%&*V?i6iP-nyM%;Uz&WsTwM(=%m<6%CG*=GA%YaJ$zgkUOG=+9vi@&hmA
zeCfh?e+J`L8~^8OZ9stbb;CE2AYQv|QM-VKp}Q<>G^a<aDpz)M4F&jXC7N2GE_(w=
z3va0~_DJVT08r!Z4-HhV%T|LCQVKuT<cB?2BGIlU21a9t<`06GYJl4+TS-(dNa|3}
z*GV5(@W8yctoQNof_*WD6gKv7KyQ3mGDZq@kvCA&v>lqNqt%olXE1};00VL<yd}y+
z@u8Ear{D!IjZ#K#Fp9xmUFc1K?BsA2`E%dr&cnVx+M_FgFhbFa$~i~|YyS}+QlDWq
z98>&Td`R6F_*+EgKjK3d2&>kAi4UP_Z1<W(PkCsIk=CcrQ#)fIbcrAdNdktuJ%2(0
z%dSkr`B&|~47z!&mfi(zEx_Qm2_!m4+XGWxdGCO%E#!D@CtuEw1`9{$+a3BonN_6i
z1f-_&rDk*0rCf5`hi9Q<OH_){>0xZp{Mf$vIh8}iS^Fmcts{_Y)z+C*vHOJQz4Wgd
zxK{R(d{f{+z(+qUYtLiD<6~Rb7sPL=#?vIo<yhkOlqttgJzTGoy6O|l@n;MrArj{v
z_e&LOX-(rn&gzE5L*2-O>a>4Y@J5C9G48bFh4#9W0aU;7;2t^#Hbp290fg)FSRtwA
zkVU`EV9P@EixMl`n|t#*aA=4ZfHlmNMOlUo#xm&?o%dE)`HfrGgH8HTU}^sKhsaG)
z?;K%C1>Q5sE?GLMeJz@Dy==!^&M&8!4l4ay$)dD(W6_ha<l?weUHMXx|H#I2$$PHl
zS&QOl0EWnNiQvTAJ%Y`rQJHMy8#p<}_8mFZ?-fi?OXTYc6_bM+I_O5bZ4()81}XPR
zEYuc3&ezimRQL$4>;)1*;JQBwOT{BC#JBC6d}v6Qm^;<LyeC@`;U}-MVY#b{)RNx1
zI9Np*V#igoJeX2N`dP=~06fze(W)|7MQDq1bAx<yaDsB9QW54SFS6lTqNTD?zN?DT
zQjV^2vv{I%<MKZ|sz$Cl{6ysmmV9}1Oi!;F{lmHQWgkp_EVFD6_$tx>O`QrUgAl3g
zd4(-3ZLDxjm`JklfHsBv^D#LB?wtvdIQ|8hm(!rOO(Gr}$8kw+9tiQL+;i(o2y@V`
z;%(r~+}CcvA5JKLiITcTPChKtBGj>Fzg+G}*mi&J;56)hHNf~hj#13WwsVqzHZGu{
zJT6_@DT`t$GxD%<!}0JuTK3VnE+qS9R!>PeH*v*M?+<iuZ+qYfk%mWoK_(ehgh_`u
z;eq}8U!U>6Ey*d`jbK2K67BE`0BxAh$BGM{GR+%rC!H;Ae*B(TjVO;fgr4P`vKJVN
zaU@pM-&FN0B_GB>QbIL35Op27Pc$wtf7Q{|_A4za>ozn<s4;S^_UO#3ml0?PiTJ=Y
z5}6C{^Df00C5E0Fj>I^|URZn?6Huf10`)wWIeN!8)aQb8@3H8Hm~q~6%x+h*uQ|QZ
z=zgR(+5Fy^Y__7WEqCp(CwY5&<LxPu4e5%)yE12G^{{`B?Fj|dBGQE6pk=XZvVDtP
z$#;-isgZ6fk*hC5(^V2K$>qzY?fFq9F;qmp7*0Pr2CvIKZC#!jPVaq2V`9Fn0yEU`
zH)uo=n?`im5xMqnwx-K0;j=;g-;qT}!sD&P3HJ<F;6o3gPgm+7fIyu$=$&9-4+oJS
z)8w+IuW+yVs{p$eU2SxjYgUc95e<{iUpL9HbpyJ@Qz((_u#%hV32iqE4J7EGTk`N&
zlX@T^l_wchfJ8zFH4$*Qn+MgdbPevMqG0&M7?O)Ggq-amRH3iQj2<bk*&D90mvNTv
zgm92v`l<m(6B`VUS!{f9+p^Fk>3m^frBiKOlNdmYB3M|toj0wkgK2Hs1`lUbN4nlZ
z+o%V6JViczI2FTbl)m(?_Ggsr5NeC08KWdFMsS#Vh&j?M7R4v&6U5>9tGDb9#gSls
zEffRK6Mm^Lytx|OJ`Qj$ICX&J>O36oqe=}28u0CTOxdBKHIuS3zpnC>FrXWZ1IDt3
zT}1tV6yP%*%=W->U1dz_B15L9KFtrYnPJnyxhU5M9iJ^6447uO<<ew9bfSkwo3ho;
z+K0BxqMIW533LJ=eVvW#?i<!1Vp;!EARCJ5mLdh@-nUNL{U!NOG-l;aei(iEIltGi
zCr59v*>%+go&O5$K2#*`|M+$@I9q{F(3dea-*T{@x^{^YzAGzab~39y2_uHA4^21q
zG}5*^q1HeboyAOl_dy1BSFGkH88(2hm)hMLaP()gd&<#A(N4|T-TTw}`G7(ny@1Wl
zz9g3VM!}fb+fw9bM%z>hs08|fesYAR@!M1}m6Pw4yz}_YN03m4WplzS^;T*O#pCO@
zPGZK*+}=m12*1y8w3!GpWJX1KsM|?84Naa%iWNsBfko?tqJGtxJs<SzlxJPxp_|ZA
zkZ9msb0ZhXfbD}50^2V@68*ejlP$lx;<CbSK*=qa|9G04{>xM@R17jRT^J$1<a+c3
zB=2d#o}GXo(&=kIF45krezi;ioCr(KSRdO>MC;+d`-fJ`qpD+YX8PUlPXms_1?;JX
zl8d@2#8HO#c({P$dgXnnC8vg2hn})J07FA$5-+?%bpsnXq;lG@hjYG$E-2m~O%uKk
zBwV#^g)!zkWZ%_E;*QKdvZrul+}@hZX{+rDiDY*#kpShw>9*tuuq~N-mA2Y}B9r*n
zNEQ5V0|1U=GomUx*>dJzk{BIY0+m|*Vg1`QLSiXIOli>ap~RFBdlp}&VDhHjl^O?g
z1|`#NI3+=r+OGG~_LITMmDA5X-L|hPdH-i`8{U1f?R6@le7w<#&7-vIfosT?b)9$e
zNTFZwVdK!dDMPTH(ljKR)YA?NCJVoIFgxf|aN2wrGgAqDwB$wRv=;uCwfY1<?3>1j
zvRWbAC9^?k7_`>zZ0h}uW=M#cW=yWS+$DDnpaIH*`_=;<GQ0`gR{gQ>Rpj`Yp|gkE
z$!M?2xDXvtq^sIEKJ~bWUqwd3P)x}G?u@8!{bH!P1Fk`ts6Jc)eFZJf_!la9)(xt1
zd;lJhPv)(RAdPRHzq*2gc&hg{(QuKE3g|*_7eEKYI{>8?y$_zYvSMdfV`LR*=(N|9
z&pve`RPBgd^xmcQp_@5MLoqg5QVV|m4M6?gw?HZ`uFV~sRKHd5wx~zVp^#atn)zzP
zhYZ{Bh~CZh>A;Y+;`@7BFNZ_7_RbR-U050@(dPji>qq8w4jzEs=w0~LZT&Q|2TiL$
z;{89kB;fx6m&BK9%{!5?;;OlY=b<xeSC{l{(tgbBL1giXIqN^?y=qox+gG)xS8Tl#
zcy9n|h3=F+Cb^b=cS(}zyOi1P5BH9c*y*i|c|aV`Uh`0Z(sd3I#ye4iR%hcj!N#n@
ze-=IcDNy528^}ix&OYFq*rcF)w2qS13x<QboB`Es_1x8GKzSYUSlmE=Jj?)U+`V%@
z1*H}eEdavxysMSkaLTORXS3rZ;l+prA0g)gqx&<1&7H+sjRVQ{>K+{e9K7+Hv#y8u
z8<<3xf9aEXLJacW$l^inX64h|_lK42E{!T24V6>xT6$qpbfOjFA3}NpHmM#D)>B6=
z;sWYj7E*fpb<3RvuY`k_gMY5;F3<tVY1Yi#rl?$NYrWRmVTtsp^={6y<3F(kZ?8My
zUU0-7p3}Faw-cnl<~rdDQ)a!Ficu4#R7F{v7*i2xVT>k4X)_WKDe&&<v{mGab2dYC
zWMnM2%dBih3?oGj4<Nc48MB$9my7ZLZn|jPC<&&sw0$>RK4chYv)x!osr1&_vAvky
zyp7*3cqnb>S)5PUhca(cs>n(Qs9cog3vta?wBR#)c8RC*)!DX%wNUil&I-GQjl*<1
z>w99Cva;zw_}lIgd{#s&KP$KQ!qe^6`Du)A`5{x)Q})2tL|I|`%O$Mm<a5hl;6S*)
z)zsHZK!=K0i(nN}V(BL_mRCwVL0Xp-g|;W{?`zIJ!zS!Irz*us-&jVbOoNyHM-lWU
zUB*9c`;^d#c3ao@n$Wsuw@wYAY+jH#b|2TXIars^bg?P;&US6u)FgE1bRQ-3PB(pD
zrK=|oewYXLolhwO;%RbeaPOgFJ`f)#rqjVmNOqfqiPyMB!pQmXuvN5V+8j<jk<2zi
z4Y3rw2nq;tblM{~Mvq26@9!>$)o53X6!{O~EX!%h|KQXnZTJj>Xsj)&3#l5d220KM
zM=do5-9_M{l%DO21P6gNdf444?`1z5JIH|^UB1!i|2|&~coM<kPb@|BR`0%8^qgHm
z5^7L98<$w!iR_Z?QnunQjlU)CG7(u5JBM>BYqpIG_lo;!-eBu%IC|ut7B0KXFfdtf
zC)HdY9F5LjVwr6xMGsp3I~I1*MuJu<bCGGRhG5k}>bSzNyOB}uLC;IKBHTDkFYV;4
zzDx^imp{!c-3qqs4!6&+Gql=cX(jEqsSZCKzm523D*u(?*M~OJOt_ttU5)s$Cl8Xl
zrZMXc+J!;<W34!me^axdkaaLHT;v4l-WoGVnHAZrwD68EnQ{bHO!<1(jn8yR5^K-f
z4YFpZGS$U;w_21R+2lUho+?vQdKp5m=Hz{lIq6d$9@q9pPp68HR_2MM8`AQAqW-Ce
zoU9Kfm5xR5!-PAB>t)ZP>$G9<9AyPpY^A6bp>+9_PON&rSjF4Pu2z;AHJghnI@EHT
zp3K=gpq!d!8D4yB?qQ7b4fl*Wyravs?+1B19E-|H^=7Ny6m}BN1CFrlk_HJkp?%Mi
zM54<tlvjDaNZN{q<6Cm-_Km503#jLomIcm1z7sulPoKxhHnNwZYYk)}LEB2VFvB15
zA5UXh?0t!NIYZf=Qi|+0xO<6YY~IqU677MgOq+Kvy8#!TsQy`u(J)JQ4F*g0B6p8?
z=5wNK^??#FzqP^jKnJ6yFqZ3zGGq+0#`S4nH*Xvrwv<4v{;ar#Waf$+D?|H`Gx#k_
zgv6LKsa>tbe5aHUXugQjT9#^K!F1H09P<n(h-k4vrH>j*Z?%vJ9goKpy=%~Grd(|;
z&j5hR&ker0T~%9J7%yzDO+5_NfUz(^1l`>j{$K)-8TS65FG>FDPXj?Z`3r(kdz*3T
ziQK!>N`r;0hRwt(-l=RYsUt&=<J!%L>oOU8^fI4JWLQDJMG1Ybl^q6?PPL^Zgetmu
zSpn~D`sK?DkjmfN>X|^5pNdDM*&Qd&7SLH*z!Dpe)-HmYlfwbV84?kJPgN1Ff=27$
z5MLlwMN_YyYyrlDNHCg=D>in|1IH_6nXZb|6K|6f(x=fYFLaEcJS2eOt6KCQO^Hk&
zLyb1wHW%F{|GI7Fd94q2yoSd7@)eLC*;Zor^~&%R`%TbPJ_R!%uEZN{EEZo5)3*)F
zykB{Ni2B1Yy6_c0s>JW1msJwB&shQFEf6#}zdRBT2U*9XFeCr+cIRnQ1}P)q**lZ~
zfrhgs(I^2{l_CN`2M$8Sz7fHr?1`Ml_1teP-w4dV=zPUbw1ZDM6H-|G1j<x?<Zlkk
zk!O{EItK<ZL~B`^&NekQmF01u$Wh-d=hfI2Tv9%lkWP8n@w|APItURgGBD~yc@tTX
z&6)50W$8yOYaln9HceNrC#;}dNU|Brsqj*n(D{4AR2u#!csjY1KE>00LnM=X`L<?E
zDIAQ52$pIKSUm=YO^o3mvbC(cGBbVyg^;E|%I%Tzc@+M6sPy9Xz^Y?RYGi6;3B+VV
z7Xgx`5qjtO5K7|l+%K2PfVqYp9W)tGa_Z=i5MaSoh2ZLW73)a!*$`i<jO$=->@s<B
zM7NCYvzf-+EsfgJ<5=X9|4~nkbfeKfBX8nu9)`+l;Ibq39rEIq??+eQS2NOMj7@%M
z-XsiomhLGAss5c2^PB>t<7jOXR`rKj@vokG*Dwz(XO~LjbU;%@HJHo1%M9K4TxB&m
z59hd^Tnj+fQQ8Lth3m)t8bE};R>rSt@JX)S5oVJ~S6fh}NHx5OACm@r!YKB;N)iFp
zy~DtLNy3}0M1GpGN5C=7z<X9&vqa{c0*tSNs<!&{ph&N<!2H3w+W*L@K?VYYV0l<Y
zSry4}K`|iFIh`r1=>-HtI^t!pK2co~6DYI-?FE{p!k-kV(tu9s*M+q3szZ_aavu;8
z1w@*+QsR&H=7_YwZd1WC*BXe-ryD`}9a5?=#(~0_bdDh@FA8i|VrU|PEx*hl0U5j^
zN&%`WV{dI9s|=O06UD`-vB)=D!01)eZB8v0e3uja$?2Cf|6d5IS#Az^RfQq@<>w^G
zhH}nkuJPzC3mLRRAZX*KEIwKhm0Ij6eI`_4GeH_7EaluJ5uuOZv;bJy@<w{Y+LEas
zN69UEYuIu!0V{`?9wh0}c_^Ngo0GalNk(%ZL?gF>MpeelN#B3%r?*NuAgHK@kQ>;D
zNTYO&psuS*Ok@qr9^sq{#^CI7t4TY6V23$5ldreEAky@QN^VOd@p)E(``{dibOYGP
z<5KdZ61Kl8jMfKQr{g>1iq)%M8xV8YfhZyHi~m~OMq=)T5&jjR0cc+AN3IKHs!ptG
zqA=Z~&O|%KtMr2)zJgha{7#h&7^+_);6-D_47hmWe-l*mL-+qib)5&$Nkdjvm_^{+
z0>Q?tQcsFUj37<Fh2Q7Cr`TPwrr?~Hk0ZyQjvUD(4{BBJ(o=pURCC2gQI&*xR2f1A
zBlkNOZz^7kLWxPpasx&P5sj<wch0>RXhCO`MgCyj^}!0(D$cBygv~3rFQ7t{)J%OQ
zS0LOm4%iw`@CJa(+o&pAX-ks@`C%iAtc=iiYI>hFr$XKJ%p{UjdaV%k3=x(loko1~
zle&atThk3w+Jf1f(WG~wF78y_*63j$Qi2|>unAG<AiNml1za7w^=z83Tl^Om0-mYf
zl0ZzVTMUQdLH?;ZgAu?7JX3IGp8jrTBz5nE{<{E~O*@!yp%(vaUulL1s5T^xd_u7<
zGzxx;!Kpr_h9@+}0kRF>y61a5D>84%c?0(}X|ds`e1Y>19m@<N1evJ`Etm<LpXS?T
z@ej2Mo@H)by0c2Z&{t-@Y~N9#ffx2MM_diJVd&`enS~dnk^Ns51~3wFZM=ag@q|Ny
zTJxq~M}AV^pAx}X{1mwZ_Sf4)*C4cLHw8rHs5f=aozN*0UUp`D2oH$0994~gLKq7&
zu#S+ZlhZpBHKqpu!TKs<Wl-lsESsbR)dwf%C9KOz<v4kjXwhFHsIcTAp-P8&r?+@E
z)s@0D!Ot%dQ{7-rL&Rdhsp6~08!lSH3{#(6ZK-34dqICj5-to&A8nge(K<HMn2{$@
z=IJ_55$<+DiKa$T{^O9bCVOMH&qLqLNR5cB&$r8#4iHFShcXXyx<VLKUl;iMK&BWk
zBPBjPYM8)ETJ*rKe(9tH0p9NCE0Fu(PnGV}<*0itC3@sCW$ZLVIwhxFh&1c(M45-T
z3=Hc)%hU4K>n3C4XrS&N&I`7&h2YW%MsYTxb^ExhE(0R^ha~*~-1wXA8e^h0)_o&g
z=!!+ZPNGcwLr5JtbTYYBht7@Gm4!Rpi{O8$pOI&3>6Z;7lhO4)w#_%Ms5H)??w#is
zs<&fmDI5Ke^lJ?=?{5N!M#fw>Y1UW(f2^no3h>Iv`H5grz#^8m8zY&QQS>}1`rBqu
zvt79C0F+Q=MnBC0Fd+}Wcy|AXsq<>r1TPTcm9;&>5h%_L5Hnl8x%ljGt84^se-lqy
znh8}bmPq$6=^fOT^A1nd!L9w)N6`QcIa5wrbHk|)PzMh$u)*VpndP|8eWtoC+J-}|
zTa&FuCC?uMm18~vodc^#5TxE}mXS(un16)%z-N$1ks?Hi&G%Ud5p6EA8SbM?SHU|U
ztj_uO^%beDex9+VHjsPA2glpZJceQO6~fyCbH^j6eMT%`QvW)!gCL#~Zz@p1@JYT!
z%R`E^H`zE{^Of^qI_{qXYlB9Xy9a3_cNNLgEsFhWC21C}w3kPlL&H*CM`ks-cK{Gp
zh?UgH9jv7~X|})me(5iQBLBt<hsyq+Mb+O{KeFydgQNeCb=6VXgv1iR6*9g+S{wL_
zkcvx!Z6u_b&5x6#p^mGs<Dt1E3B*1#cZ{i7Ktvt{DU?DPFkl&4qi=O~M@`#FtpOq(
zLBp@>83<|r(N)vyB3kNg_DV#^)xouuh?6nOn+NBa$n+{&z*Jh3y=yE?fFNl$gWfyt
zGJ|{=x_Rv%l*9v_GG3tnpumT%{q;<vV%)W`AY#SZye)|=aR0&TWi}7l1i3Q=V5w?k
zM~~T0>AAEME?q9XNNZLJt<My>V0=P3A*4+stc&rT3&r)S^N3Qe@QT13rR#OTbc_(y
zLiG3~#$garla`<=at`e-mlQ`*vEU<26=@w8<q>mbSU_Q_L+Gi0@e@xI7@qR}+qo_1
z#M=2&#C)>u@=`IK=#s_EB`OjN9wnKEB&YvXI(&nmHSTv480>{Omc}4QDm7I)A;0!l
z67q~BIT}J_u0QngDZVn!49sytWTt<{ZZbk!OkL!QM+a@I!y};<0%6gG+cBPJaN@5g
zl`bi6;h)!9lz8MJf;3F!noD&2oa313K*!}&xijtfn#8;Ox&7k=XY2cCKuxv2p-kWY
zispNS^DLbRh1#T1Hqr#cKVx`(E(sz{yymtViT<T@i4nDz@-s8|dA5)iAgU|}PsV*%
zBz@8nk&&FW7dz2LF^wZPRqqnb3Nws^La04DR2HWnB0KVrkTg#HiR)0`(Ozhj1l3_^
zrwReu>VwG4Qb~Q7tXUPGo@R6}&mV^j&^Wf#n{gTo1&YbMLS#JL<A}_@(Ym623M{n|
z%Zu=6%9d(mJAILmBy8Z&r@8?TtXaI*MVM>=oP?iB2rzRf_jF1uIBLa|wKJeFwb{7)
z7M<g_ifZ;t@>uEAbSUcK5N^uXLEy0uebKow`wwK!a8a^a^>|=&;?29+ftDZvZWt-e
z_MDOufOWQxQV4UxoiK<g4PX&zl*#v*JBY@cVD;VNUD0RH+{$HKS(=!}bb!&A3uD6k
z@s6NgzMCB@hDFiHHg5-G@K{8MU#)w<5$^C!xk1Nd87}-tMOLKfP#{5&nlu-tA~nS*
zJ+UZob@Imz<}Y+gi!n3yH*FfH!d0SzCS7<jwj}+5?6Ah`G1a{JnkVJ3o`Ptutyf7J
z%LuMR?Fe57U@+FkwVBG{mFxL9YF@cg#wgIBdy5Kg$U_sqzJ=94;eG=a%-Z@sn2)}%
zuIdaBL&{FoBMvJ%nl_)0Sg(e!D)o)xj>sLNTQ$V6yw&%!o~e65=Mbn1$EEt8?Rno+
zo%fGk@*dyz71vD1TRD^TE{G5?C2#P0KnmZl{S>MnWQfOut-%UcM(Z-juv&Ea1H(8P
zgj+cl{l|mXSDW_mUo_-B&ggd!H4`_17Y<d<2%W>uQ})<b);9a)yM^knozS-tIz-sf
zs)aM$9Ygd%blzMuQOH={T%ohHctOCmS)*izP2KQ9^*7Q5(b6;~?r=H|DB0`F0JIZ=
zCg)8c7FS7HzT{YVd;NTNVeA5WbX6sM;zi9|R%^lzRq2`Kq0+w28Be!B0k}{ljLBXv
zmE(df4PXGQpPBNZ-ZEF(hc?cSmD&_P^n=>CoJtYvUlQyT(Z9^3Y9NxfpDzgcQleI^
zw!g{6p2xDEJbwg_`#6xf8i~e{x;m}!jOd;9T&RsU6;aS%ZjyK#g}-}IX4FuO=TKg*
zr)?TgfZn+$(U0S%=^en;9p@xwMdT?sCy8G#nU~s=G@kV@8CmvF|8DHwt`PQ@j0EJS
zNzBb1__+44Ir?!VDSE&L%>pUyBfD?vR+lcfQFI0R%H6<gJ#ktFzm4u6%$KSQB80Il
zN>Eh!bnN@UL{XDofnh+w{xIxIj%_-@kXd~6mx}z3Ll|^_%Oz)@^!*PPd6^y=<?^4D
zmd6LelD{b})o`}_2RPK3{28xKSL<^=oNaNX3ip#6SD)4_Ox*BDcVK_{$io7cZ$9!I
zfB8(--ILk6MT+m9GSEoFV)Czay92Ii+414$`24@c+YsPtR_~%~I%DDQz0$hFlT*){
zouT5kI(&_S{!W$Q_vyw0^w{Y2fBU30-+fXMqLF|4r1KjScoF}diu4B)!sDn(#~Rr3
zR`O5Y*M(CLiBbjSzCScbX+2^$7`5ASmh@)CMTnc#dG7QV^15~&O|S~>kLJ}a*x^TS
zj+Z{C3zzsRC0t`mqKLqAoJp#r%O2fiVNl+9Z;6hprkR#1pR(-g^Uz*47yhMk3LuJk
z{>#53_k-Lr?-qU`9V8Q4Fj)GJRdc5G$#2(W@^i5I!>vvG5#>r29#&PX#dfpn?TL)0
zKEDo-ucGNa9G>Tz%R^Vl&x(#&*5?|SPp_drJx@K(w7lN#emYULFo4{@+BQM}nhE@)
z@~wmbuu!0v{~5g>4+#kZEJxRkHrRmt2_Rns?;X(p_=Dgd6&czE1duk|==P4cH}VMi
z#RXK%`f3MfZF9fv0I@9k)imoD?cCh_eNN-ExyO6sUisG?!1o$MObD>S_qgsVq=w?v
z?r>5T>pBEy#hT!JK2i_TGrqD;QEdf6WN<5!o)#%%n+^Wvwmn%~cr1e~R+#uFyASbh
zF;)$3c&o`FZzwK`&0Ab)m`uWVuNb+_m5L*P4J-g#Ozben36Vep_Zq=wYezo8=8p4e
zz3VE^DHaR!NFk1zE254<fOi<e*pPIr<g*u{m-R6hZM^;uI?(MRp^;_m2gJEZRNT%?
zDkob_ieI8N*w#31O4BpxJ&B)5L4XNKb+tY`vrZz0>9uR$VjSplI^2_v6X5i+X={A@
zV{LrcuItRcR^<}gRnRDt#!DXX(kz@l)`baV?LZ{UnV)MwQ(zrIAOj-aTf|V3I3+^d
z-;k>Mq$rWK_O%a_1NYaIc}OW<V@WD%ErZdZ+9+d1o5Oug?P{tmE#0YM0V+z4IP$7e
zYY`H#e8fS83&n(mmwf;C3mO!ne-dkkL#+w%+J$^37NDMyP{VAU@pWt8*Bg<C$mDFF
z)inuDP$V@*p?*t!MS|U4QUh#d{}#M_w@yWIB}e=UFr;5=1z~^&!v7AdA@p<t;z*9+
zuuU?SMxo^(Jfw1?A9rHhzI0Yd;$iox=|v^2WSX@l^|&qWdFdSehqQ6?yNufp9X0zJ
zVQ{w9-=9w1(XCs>OG}9}FE9WR#9RG6(wx9Pr+d<0L5UtPYuZ7p23l#{QS4MT>AZQ*
z{+o5)#Y&42q+-%}(yRDvMZAJ6)ppx>IZ{PEw+FT2AT@_;eJl$c5o5c{o0#Dx6%C(4
ze_j$Pk^<X9U`2grD_y<{VhEng(NNGvZS?-G3X@|l_`%~)()o7Pt}tcJ@bLAHV9Tv7
ziuVrK^V-IUU%2PQs(jDh(q>o3C^WnIgsIKp*SqZR2-|E@e7k<rM3LoZKQFD7`AwaO
zCvgI@d$TRZE3qiru+2`IJ0emmf{UK)J9@7m^T!B9hvS%(NGE|VluPPiY>Uy^ajNC>
zUxgh@bf-j<$uh%=pGkK#h4so;>%wv`-v$<fj0jpBFyZMWz5^>?H-RrTA>eXa@u_bh
z0Qvj)by?4^DleQMHS=YRu8R%Nvb59sdV7(HyV29Ekm5Th=jX(IZis0wZOX;SjVHEf
zJ#$~}kJot17L=QUV5Gh}V}@<v5>nHqUwP0$`{+cA2~wdIPU2FD^z2}Fj`iw?R6j5}
zH&oqhXN75XSk&%J+pL_%A-DsNXlTCpwj#ZNDC)+b1HHaF*cfteh6+~;-Ny{vJ@kl(
zATS0JTB{7y_>EJ>3=t4Hf`p>COz$-4-EsnlMFtddAE2O+jX=9f`G2`kMfE{s_d(`7
zgz<EDa~Q7kIt8S;)29N#2~2X`yjc(UISt(G8Q<`Wf8-~WtB752<9FDf&8gcOHo7K<
z5{)l~2B+TIeyRm0!QV9AE&3l!Seg3A<5D<{4~XXzmyQ}ffXeY43Gz-wn(c%;NTXfu
z|L{_YrcVndV6r!@uxN#1p`E7NUpP&~0Lg>Hj&0fT+SBom3r5MP6!A8bbvF1ZgzZCD
zgR2fQCyHEWc4E?Eyl$UQGideHFAH0>31#F*S9xfke@>YYX`Y{tVlp2TfgVPlAK5J)
z5Rd0gRU1@uXTTmt{vRuhJHf>GQ$BoPPU3(DU!q)uBmUTbkEs#=%8$%{L`qg>pFHcB
zrZ2aJ%foP9t8D8qp7bH;vD(ydI<vJcscds$^R!>u7^B&Z9vJsgLO8lVt2jDd1o;;7
zW9SAnQFt1ele{o#sQ+qg^H|^Lgm9N$e}UFr)*xzUrLarfh_q4MVx^!HgS?3=?5wO9
zWTmoWl5dpozzQmrRMdT(J&*sD;v?@>a$th9rt9H>(ZU5QJ2CF4S;@*|mywo2qC7l3
z@g}KQ;Ap6u>``TCs2jo*-{Rqs5qY`d;h`4}iXl1vrWv+g*$D%(Y<ggVEpsPgfJHp?
z>6m(d)mzx<kiKxLpr{6BrXy1*wn-#@<^uzv#ul#d)P_=83WlOo74t7U(nXWVBdO&^
z7UToySXIS3S=Q<86>AVBWcV6WDJiW6Cmgyi2qRjkLnc0wDG<Zy_PX6&aXoyO{L!aj
z23u28c!mj*Q#>0BFW1>0FdJVg*g5{DmnzLZ_wPgBx8gXR^2kDDY>60Ofu6=~^ed$&
zl66ZO7MGN1S;O~>!Uv4TCmSVcwyPl{R$OXglXD#>E&1XvVSKQ+5iFtA$^tqd-`H&w
z4K2hL>wHzr4$my38XG~j8G=*<#AU115@8H?E3@EWP)WQJIIrZ%iO&#$S$1HmKPL$h
z;fWbXGph`(#nuv7W-=HO$h1%d^jHoYRtY#MqT%RSuOHjn$pLFNS_~ni!YT*b&e)tA
ze5;|TCq=UH&>iw4q~9zwg26HT(E(fzv#lX=<#e|lwtMIY^}2EddkZWh`gfEo?J`Ld
zn}c>SqjVeD`Yu23B{hR|mmTB)0id(D3H0sY42zU&go{0nx3tE2DY>Eywi@tyajpiB
zKG53~Ils^pK#&4y)UYnRJJ_aAjG9d>8dELS>?Lit?VH|0w)Z>-A2>GagTI*HUDeDF
z*edKCoQli#Y9cY5&vv(hLp0T)v+@+%igk4*m@a>B5X90FZ&wfrpm5`hu;5Xvj*5Ym
zAY#y)xhCLvJ}k~SP-OVi5F+?J7Jg$@CYUVT;K($zI%K^+o`&QUL3`kHk1VN_%@cZ;
zzH9PkA>b55#cNqrTF}_0e@G?|O)29ifEx1d3RmWr<z*7?2AC5Y6s3wn5)AiR-4Xah
zB>;*d-$M`!?LWH6P}iInPZZ$o>&Pq;aEpj)m#L(01WQ)3<z=O#3#VJt2FY(d+0sxu
zXe_oH#3SxSb%aE0ZfuR1Ol&OK?!d=amlY1uYywOp%0Qr%Pz#N)NNOTWZ!Tv+P#b-a
zkS%X-<<VD<$J+nP3sG?x;h%S`eIL~=Pd4g`YMb_MLxKH*Y>V<ce+}Q6Hsp$yIM3~4
zN7H*d#Y*PQeMKFc89c^hq#h)axNO&b!O{bJ1R4w4D`v=E{K&I2haNd<-`pDNv&2Au
z>*<=C^AD4A&TYX^zdlKCSJJCJtJ8I%*1>&fa8Q~O_^*&V)IA8B=gMA@baIEstA_6`
z?Yoc|M??h2CHr=I1Pxxi)z_Jy@WRR0otE?M-Q<MN>j#@-56{IY-_FY~;4Ch;9@#Gs
zRDJuCo-dD^4`7+;+i4~{-oEXu$mc$-RH)Il&#Nz+Kl}J4_*VIARx+{Unr`B{R-V}O
zbK#TRgs~xkCP4;nbE|@caXH^Y(6soohp8Z0!zE{4ZL?w+?$&+dHR9TW2`AJ2h(85!
zkBi014z~))B@6MT{34oM1L|o8_o<%@;p<a%1@i`9KWl0Y`OfI$Z9jSsIL%HBjDkoL
z=_78zddPUmE|t(%phDmlmObG>+%SAkyC1jPv0Pn#?L>a9OS2cT)y9F8Ow3h<P^n)#
z5~<$YB*B!(q|cGcSft-)I@4^;sY;{b!}7R=ET1_gu;GUY(=Hx?C}m89>~QRZ2@<Ze
zvgNuXx%m1E!fNgOfJbn^CfH?;mYFMQ3j&b?6Jrp~Pc%O8;8D!Nr<kS+*rOeg%0Ldb
zG1wv%vFJ5^y-CP#w7>>We>DBQ93b+lmi;@xx936kxBK$UYW9@D+hP>@r;EN|s0&|y
zZY7VWLb_tEC0aLkC@#sO?nf)_u~_{W&u^nEVI=blyv$R>`4k!6!Zk-;;tJ|>7?`G$
z-9!2NJiM8oN*R%21>5&5n><UkUJf7@-XA632nFJtpl7pYetXN-m(-sOSYFA$r!@er
zs>An6TSw2;_XYHb|JGq)ERjnt8NY|3AG$i_(wP>v+LG;Uee%<_AqOXT!}hTy<Kx2A
zuVZ!lzb@xXbURk3DI;7PdL;gSGZ&_OcVTOP3wk!s`CwbW3k8V3OO$4t{+51~<uzt}
zoM!}u+C8FO5#TmIe4X`aeUWtKr=Tq&gYi>wHF9Y+@3h!@qh0pfQF0e*k*y}wup9p@
zIXl%Uo_iJgQJ>;%9gPFdX_5yF>K2?70<W#t`DOnx{t$W#9|-pyL~Rv;E3S(*8v@t3
z18nmQz(v^&gJ(VfwssxB>Ye*vm&I~jtls`A$TrXXiTpRDr)$@MhX_r73-}8Lz^Ye3
zmqXy_!wSD|r)>YHjGZOvyTHe(cIi4`pOjGO2Dr>N>yk8}9=FcEu6Jpc^MVJsNXLl!
zH^Cx@{sI~O=s0<Mli82~frC$IB2)F5RTdz+2uq6sI+ut+oX$A=Vc@$xkl!a-3n1Ee
z0v?w1#Yw}@h#0i5O(l1`XuPg8DBvh;wZ&ZnbWN)fmch74ApBd`4b4VdhW*mx@6_dT
zDYCe7$fRB=AO=Y1FcHF!(I)YIu1k`-H{u}OZ37ZHabMYdV_(u7WdCI2zIx+%Q#3a!
zRxCnRh>i;?R-*54-hqbG2=niLzL0-RkTo=2T~HfB4nFNi=*vV#3HZ)rw|inZ8$@>&
z@IO?=`#)5L-RX~5iZNvN>F*Y8S&Ju^kl~Az@m7!Ee`06*EPwmBM~lM5sS`}~`xqqu
zy!or}o{G^8cux%f{rQh}iu2#vsf~9L3oW@cahQA%gQoj`L{oA4aH+M9N1LW=aHQY+
zsuLvHJbN%rUbDV)!-O4NJM98w371Rv^w1S9kM}2<bn!F%cr+BBPWd$=Hx;AT1O~;v
z7{QH4?H~Lvw|6SVuzjf@R__%3+YS1e3^(FNuEZ-(E8wrEYI~sQdHToY*tZy6R{ZM>
z3+GSl*?`Tbul2X3!)AxV&8s^q=dHE!O(m9i8a>46)lMZ5Dd&95GsgT(>8S-RYR!D&
zZ1F-t#qh44PXK(88=x%#NMp}(*TfM<{~zsm%$RWPH;*Q`kIz3nXYf>fvQBt_tbVX4
zDe}{+uOR}A4lf?1?|gf7Nwgq(hOD!z`v!uF)#13g|9p}^-0^VN)`<o1D!Z)j=rs!y
z_?52Hgb$a3;OO|;Y5g4N{_~PO$$&<(Y`Ot%kq#HkZ?yZxo_QNZhV(Hn>312=mt(TE
zjJrji$}2rG>v3w8Ify{-5fu~~pP=5@+mVr(CK4N@pO(iYwme!hobW(@v|h)|y1AvS
zR^GKzS`0nNiNB<>L;-*1uMRfI*<;R!5eyLK!e6<kz>B}cVyOpUhy#D7*+>Oc2OH*c
zlnfN+5*-g7=CT3x9pdog1&6=Vs@nPcgzo>|Imnp}x4;qZg8f$a?`dE|95qOY!FE$?
zz3(R?qx-85e>tQA*3pjOl_#zyaV9e%bP5)*V{ON>#x&I9QH(1QLC_0na%eF1;9%J6
zDho6#`>Y;9&Tf5ld&vbcglNatcWP~FoE^x<Po~()Lp}HP|ET3GC#bR)KGT;&=AWZc
zW`<;nfe{$A-ajZ9{>dIO!hjZdU{mxGZA_>(54VCFk_bxb2Q|+-v{T11MjS<E6mJ9r
z2G{ZZUMdMS(XGMn8vZg;-3V?}>6NRGSse?a0~KG?E3}Fm!_EZq1@%@%>3<|vSPaoa
z+)bSF@fxW({SMIcT{@30mislN)<jdM`tv=6<2vFNr115P!CK|ZHi@ozPI}xm$*$CI
zVJRa#{I?Tc_eYo>ca0eB&^k7WqcHM$yz@3<)dmIKM|5EG1a)cO4S~5_?ykA6`IDW3
z0U`F3r;W&>e&h<=R@vq3k4%ANte6zg7#$c6*Wg%E5jnlfa4}O%?r8)zzDK!z6PLt4
ztjSgYAaSWU{F_UT(Y^f@#+BF$W-KUqqE0a4iz$_%Nal>&`n6D#<>V#n>fM0)dMzUW
zTXR4DFehW?vnP)Z`nkm3R>$sbaIDbjRtAEAn;hNQM*(GhT||GSh|95??zp2(moF-C
zicdT|qB9=5itfw+!qUG720_vq2<y1cq^*edn8fpo5_dX8vHa9q5W`(~5*zDhZhw+v
zvY?GL+WGwE=9q`T!1?l~mj{m0=(Avl@r+L_IJ5o;8mrtdevwBF?-~`|g1p6n?OH!e
zU@NaLAMNOWGOP{Z1kwKJ*N(#rfkPr5O<I!pbK+H|Ygnj1A3*+KHgMw2D1{s{8Wj!V
z!HgllP%)hA;t;jeNe8<RrjW`vDO`p*iD<^etm5F>FAT2-cca>0U4njLINK-wEaj?S
z$>)KoR2v!mBT=?{f}+B~#bZFw&H-%Bo3&EXsYLJ#j=`7CU`wP)k|iq~ZnyJGp>j#G
zxM4IjjUE#rpnN+DAzPZvNFwRPiyn%{Rk>1;0!T->19;l3U)_^mlKzXaNL=Xl4ZlQM
zomzPu628LeskO1{vVVo32LVsMz=yzX{(bR=Z2P{w=;we=m4j-IIh`z+3D$6q%HpG&
zcRs_(UE+c(J8Qs`{S#$8B4_^Q3h@v=q98m30=OptA+lds)cd|nQ4C*dYZw|}Harjy
z^jAV~9{@o@l0vc+uE;2zXaGqbcc3wC*z>Y;U^1u;zq?(jKEo+Ip>w)LsfRoqQ(67S
z4Y_3RjyOty+&H`E;mH6T=jjHuU~l-1RJ{FA+~ps8qU>!O+e1=BPJPw|+2i=`kW1ot
zc4;OSDtl$iW5rA$G?dme7jSs55xe6+`RQ#?6NmOGE8HZg=Rm2wSaOy-W^tGZ6y$@6
zik(;tHYWyig)7n;k!B*A6e)zxQmey9nI3Cv(uE(iOjPWXOAU#kwxH=2n7j<8`Shi0
zWMyjkzs1CS>h+hGTLfizaUkWKut#5+&m(Vx=rMVHN72Ihm1aA<Q+?spX*Epk&pKOl
zX=L;;7%|lNW1i3gat<;gy%T3Tus3yKe}-msWPGl}<quA4C#8dEq(^-J)WrYbINGD(
zL;91L_eVQQG^Pr#21&Gkfe%YU&K?If_0`aAQ|*b!1TU-V>Fex@_uI0(-4RZ|b)NKb
zbtR#JYli<NoTE2xZmo0h_LzesX!3sLr`x@ulkoMqs_;Pa>2`Jd+&6S}MfYCyG5z&E
zHIV*%NZ*cGaz%Og`m{MEbFuSPdz>!vn5A9uh>?hTbi7O+puWw<`L)?*h-psCHBS3f
zyyo%AjWsm{868ycGEv-Q`-n<9uaUCVZEy;=T+~8hy5^Q5=5I(W?zF#>g|gSR9CRB~
zIB}`TgSYf_X)CB7%iC%RvGQg-tWSI;z8Wi;+}vFChb?;vKT$%Z5fZjA;Cuf}0}xg!
z9qrn>v1Ni+UWVcDu6ZL&8qRqKo<kI)4Wi$zY*9xMbiqp1tugN82N4Ch7cx!t%8$(~
zZ0u8(L(C77XOeF9)%zqq7@Kmq9MuP)D71O~B(b+mW&I=z0zWy!WQ3*<x)z!xouz~b
zHCXJ2DwC6dxFUp4jhlo?OXWuEU@VgLyG|pcEslTZ@d!4-oH9cNVP6)p03n1~#S7C^
zNuR)3nDSravqdzJa7yJ(z9yeSyRcdz((28MPJxapXoR2LCdwbxmdy!d4TLOl{2a3u
z#uV4rj8!-GzWKG9xh*%Ld8&(9tZXbLyB;nPNn%xx6B;icRi%D9llj5dvsT_987%4`
zgb~~`y5ZEvoMvsf)9~!@&W^%rqMAFkZJZ}TAlg@Nol~Q5>W|$&&C^}r=%><<sn}d{
z-h0`Tg~ye$V#M7`^!Az><m`>fl7|-WN44E@MJM}pKYB@K2PW*RO1;SQ`LWf}-FDjL
z6>2m4RkuE_JNvPX|K&;yJ^D*^Iau}vXbR9C*59c&Ru3Q(_zyO~5db?_F9*Qi*>qda
zUXDL1kbkh5B}$tGaO`1QQ^5bVD!|eYc;qi6;qNq~eB$o}kQw9@36u%^x!HG{3H*v<
z$N|}JS408MP{4^sL}0*vL<~9z9SIe~KbGWUhirnMX-OQ<rT?&73Y-*0QimLvG2Y_F
zc4d3HO9A56wOx%~2lhTn<<ARn510#g-7o~~18@w?j|cDyFa!2?HlR2IcLvP;7tk@V
z3}U&BJlH+pB?-{qRZJPY)<ZS+TsV7jh#9bSN}Rt1_O=TCyuCeKBT2k}dW84G_~6l#
zwTwd$f_iPL7Q)=c9pl)wAV5O*^As>(yGh4kqM2fZ^zFqJo<>MwwPpw7XDtYZAIIp9
z>Z-1&A<!F>1A^njg9U79Vl$y`;a2DFYpO`JOX-fUMi#faVXsA(lb<)YbR{CA+m&WO
zjH1WSZtSTs*&SgV_O*e87h>;nS^DCga?R>K#w_LVWfWKgnE9Q<Va3FqKUXcqt=X=I
z+}?=ueRu{WvZ*~%YK=bye1i$^`H_hwGACbtVd*yz)JiN=kz2Q$lX%@zt45i&v;hIM
z*Y;!U?t-=a;6>23wDKuA4G5NZn?7|cqpiZzAs(01!i)3G&+bTns8y+y(KjLQYj{G-
zbG>_FBFz5sU-5z2jE4D0tP}ZKD@Wv<BtPTi%px4DuR}paVG8+8WxZ)<0(%d+9}AE5
zh9_9cv9@$$LLC+26T@@)Sl3wO6ILd`D&VZS=6u!k08g-jnKC)yy?!1Q1U2i+2uU(C
zopBNZ{J~8QKYj0n2%yuhwQAgyU#-UJe%ndM&Zy~RwBJb=**Bfc(-Rm9O0$Ww{$2}!
z1Jbf4*bwYkjXkUkieKwg>1(s^nHVN)Rd_SZqe-O9+&+gmt0`$zlk;@(SqnI5S6wvk
zOpSB<cKv_B@&7?^eDVK3IF1uD#-0eq^rhlI{Uo%x^WE?ag}@FH<@`}Dh@L}Szjhrd
z=)Klv2N$5Sd2z8ko!&KjUsnHI-b}I;F|$n%rfZPxuk6PcQgyl=eLJk0Zm}A33-b`W
z=E=k`>wY=FhJO=z^e|H7o>3qi6BfvmaH*C5i|e4MM`0#84U~nQ7yJT38G91y;**9_
z_NS0$O;stjHNsmT*CNlFKhucgz)gMcYz2W>&Gk;9K8F0&3{gY0`cYVRP6)rTsVl6r
z);PzHKq+cEHC-pTzW#BOO6+?xR-8Olrx=OFlnF6pbEYfzS|OcEaT*(9Su2lW|13S%
zhMmS_%vN^P>2HAi8PanBkeNrvx~8j(z{vBt0%IKaoQM5lK_3&qw@UR$x&Vy<7-P%s
zJJMk3k`xmRZ{`I}>&#VP9|ssp=-amgmZF<a%XNHjU9ep*K0<^D&LK+De|1GPef36U
zVt~2%M(3oEP_iqX4T&ebO^7`mSlC_?y0WA8q|uQU-p`*Mh1WAuFzP=yNfN|MT*sF)
z;aSg)dWknA(3prjFZ-jO9(^LeOIxqY>n+AWZcaOO(&*KY%|^{ddR?WzvFrQOZL*>?
z*SJH{ZnU)Qf}`Y?MeoAa;&x@L;rff&%{^<2@$9TPrmaIFwZlz3y=57?Lo%JKUY`2T
z!pV7a%xH&9YUkFZ%+;nH^_yfmPrWjm38xdK65PYDSsZXDjaSBmP@{!|y#j7@MbD%V
zq9ZWrc5ip&!q`z9$a#tZSiUeL2hs_VRg~nq^chb=#-*8Qv74Gx&lhrW#>dEgF@uRU
zwHr60&tH`=ezJJzmILzTo-U$<%_Te7XBqf@xUh#wQ`J&CIW;Y063(g+1;OMJ12<qV
z28>2Um|g?*o9tjyawZlX14}Y0MOMw7b8$Vg@6H&0JZnU0VWB%jfyeRc5?Ac92p3PS
z;1W6^dmP4HA$x7?UhuE^UI-beRgP~N`OVE*E@yCO#3C+;ft(NwIG*BU$g|-iBC<Gt
z|Ha70;JkofokA%MDT(@yHQ9fR&bwcx(4x~7>73mVihMcDeF^!dhWqh`?|q{6z)S62
zcd8UPZs@wwIYkP3IFIQjk3Jhb??Bkd4~(iOzv2xk*k%b;os6L(p~#NjVB%Z*-X&y?
z3?unQv<z1&x~yVcCN-_S<gI4J+}-vt37ePX5qy-a2ruOJ#vD<?f%)Df)>y}S&DE&&
z=ze+LozbXJo1vR&>8erZZHsAH8GA5|hT@GQ`NHG{d};3HVAph<d5;k7w-dn;KN0J6
zYwvz>+HoG+U8z<q)*MfBT_ygylbC*+(t1jC+ajC3wBzyWS?n0n+f}b1zW3_~Q^@v9
zJ5;ME37xHZ_WPLsaz{pavmnNR3Upi_=f!jrLUj}P9odXW?P7fl>{5i?%=+U1>_R-c
zT)41Z^|-M`Kj8P6>|{$M%;)sb7V~G$>!NShGkd0<ch9M=ZsnuZK|iDFBixWO9c#Le
z3x!`#H@_Jg#*@d5OtWrPFO8sEK{vB`3@-G1$NeOyQc_3arD9!Mk|xK>@3;V0VYKuj
z8>M4N2exf<bWBdBabthEJp#w(_~F}6!fTI^a0qP6yGc-~s3~d>S`T9jcFO>1;G6kc
zx-qzZ^XF%h9B!hWnyrI@`=H*S^dI{pHRVd!;!`!nUE{MC2mJ1>Z5<~)ANZ2*6T+Vq
z@Y#n*s~q}!xn+KY%|B$G*QJj5aDVbfb5TB@R7A9W`qX`RzCwQDcf^Cp*_^C7Nadu1
zB$_cWt#(>|$v9Y2hgosNpvj&fRO$Y?4QCRlzNHoqGwaJDPg^d0dVIZ1*OREeqlQdA
z2r<*BuaUeuyx8RO6=@r7qE<)uWX?b`sIM8{+?1hn1E}Ryuyv|}LOrCJ?l;y=IcrH_
zW7A$6H)l`ggNPl73bb#VEpQUW#dy|@DhXAfLM1N2&b+$g!H$<h3)BOwW`yXin|9BV
z0EkgJCQSsuehY0$1Nk%e)(ig=_G=H$FlG<G=WS3T6Pv7zG;BVR3=S?KRhGA{y>n;I
z=&43pRH1dFPtH-BO)EyOAbtRk7!d){;Fa|gYdb&lIqpPs`XI&^F&KUde4Dy}ANwkn
zF>gl3ERo}tEP7}GyTPILAmO=$2uY*dx{{xEc^DxSAAmF78$DLI(C%rVZ9zJ81tGLj
z`b+9dA?e1$iXAu1k7b^VYb?k$Z3F0mT{rKI>?D#KFJ^F5$+vII5gK||I&QE(;bCj@
zw;q%u!S>Ory{=&QIu$S7V{yN<yEif(5tb75`q-I2lLYu9#PR-KrSjgv3%ApAHbV^*
zWbMur^^AN1m|TB>H(wfvcgQ{04OonbU@Kcf5nsssW7tAYRB@^UHSGS5_;Xz1R)3Z8
ztT%^-NWSs-PB05rB3TIq@gH%Z`-^2GNx6gq#b)LYE2{?ga=Iz4%!@MsIX5lIpO+UX
z5@waT5WEbUTJexDj<z>BPE^#WfC(50XK<U(2q`I7-Tam#$G)mPf}Z_DBM;{CF7cuR
z+%@{fVYa%v^RB<B1e)%~x2z5nPkO=k8u(2uv-WX$FAZb~cU7+pikK7{ri3QpIV#nB
z>KI@)+0_YYo#L`Da;V)?h^s!qUQi-NfED<=AFQWpHfqOjddA~#5L~DtQgoA@S;J0P
z)Bso<Ajj+}zp8G#cwXLwFxc}o#85w%pLHfZ?Xw+Uk`K9pWt|bG&f`1qju1MPcH2TO
z^Mg;Uj-4?pjb%=57~6(NvX79<5SuSs7*jM*M(}oC>Hfmg?0>^kInm2ZZ~Ewg?j2Bi
z9fiU!K@OT+rHf*(nyS5V77mK>>Su>4qy2F;0`);nPd|DZu4>8aqfu-8n+5^V!mUqv
zU7GKF9S;J(X5y_mQ?yQF67<c7ICqq*HXawH4NbTIMb|q9Sr#qpqGj8*-DTT$ciFaW
zciFaW+qP}nu6osbzY}rZz42DYikWld$Q3izpYi3FIWw<}(SD!N;qr2@GFPu{iq~3J
zS#17F#1c9bCJ%M9!FeduH!owE6*B1`%E&0Wqm9vhl4~L+;={y`v@|iY%XFhvMlWgg
zAmW6yZVWPpMt!sAuGk$~p`)&tmz5w_2*UuOi7oT`9mZ%(yFSp4W{x&Tr=Vjlsd4qR
zF*5KvW?qXrg#Tq4E<KAO#YM7i-uBk7{A3~q5!}+Oq}{No$EJcPdSa0gXKPK>R*0Z8
zI|gu80WG9Twr-MP^sCsG`}z-;%<vrH^7WrT=(q~-Z~0}_moojpy6?I@4Wt_ARX563
zsO@cz@KSebvzDWxd&)-QPIS;{MWEUhrBy6A7#MpI{SfygR+afx8U}n(j`0DVtm@>M
zg=-;R(2g@pHAjcxh7)q#La|8;B~7kqm>#GnLMqMI5`k5uRIfst))Ie2NdZomOf14}
zSMa%Y6x5FL8jSg#3d{g8fMUbGiGN{c*CV1DF;Z^3a4Dkv9{Rl=1R>L{fFX0m<2Iz9
zUo4;-on)l8_R}SjEJL1z-40~|tG5d+JR)e(vLzDr4}248yd3ROX5>8YR0Wn*&ZNJR
z&_(=es9@z0&ipBFRp{D={LsElEdZCDUMj!rgrKZ+?rbd?dEFHqGDoaaF~2N`y?*4u
z00t1^4AS)BATTYWY1l>>c*B4w;)8DzM8m+-MJT_NG$`>BoVf!;7>fj;=fIG7LP+#T
zH!~<i*ax&qO6*9xDZhl}N)Ul9QaaW%kSx(MoRYO9k;UE}CS@3oLyceTisosVG09Sa
zKMvwgdq0eqP*@bWm(UEUc~1%uPNMH&JypknAR{yr;yOa&J;IFm@X+_;z`rN3hnCU<
z`}zyw!Z3GhTRQA03?ILbZC=)+F0l$s+^R9ZgZLa<tp_;bwZ_(OO$4T}zYMEa()p1K
zY$gJ*OP2Z;vQ*0R9ce%;)`?*&*D-@mO;Z}4pvlTwt%KSw2*CgGs)+WQfs8H()j^cM
z5r<TK3TUMBJ@_)lKgASMcGIBtb^<7-2jGRw=%zf!1y+UnBFecxBgq1G`_VUc56pPI
z(#RcG4Q7mVQl_$v^;zyRs3JtxyA5W)gtNluG`rA;Kch>CJ7iHM7_q&PhU=I~7EQCM
z(&+Q_@9C8!@ApUl7|!(fOMft}v6D7B%);?P#c|{OX5wkFGDKO#0J8Sv#a3my+r5}J
zUtTPAR|ztwvnmgt+JvaBH9)b#5$JlQ_P=54v_AD-O0mSe)Q?P~UuXWJSz`<c9(6W!
z8fD(`>vB_lsJ0oY8pn9>>_nu)Fe~+6{Hi*W>My8vR9r_9{e#bO^J43Nul}6)DXsPU
zk42!pQD28MR2*b0;o2E0WRPd|PaCApgIIERbv?Q%!PRweCDcw|B?I&!2jBa|Q;xUk
z58BATONLRR>2g`C@<hA{A=HlC7x|qvyKP0O+jrFy`7aWl2Z}g#sh)lNcTx>3riwGr
zNLj1OG*)a3M^wgNr{R+(u=M=>Dlp-J?Mu`e$(#iQ+VbYPQtqHn4%ZRAL>v+ha?}w@
zsxXqw+;muGo$6^_jE0OAU;72$A>7DECm0AX0y{qd!Ffyag>R&8lv8m8doT`hf~CEw
zKnG)Am#yulSO-nUX1I+e_J~M2Ir~@1INzTfPV%@`Z5OV<UT-SD6wfPpimTqtKO@5y
zxym5;6E-r-+!SN#V}6zVI22=0B5LUmNC>8=AM;fD(T4H~i^ye}B5Kpxai~;vM}opt
z_jLRssw;c0n|mWKYl^XpX98nP;%=%k#kAsXtY}C5azw)>L?f=Eow0l88335m1pBFS
z+*Lf+aX;#=npGZuACtK2Qs6z33a_{;802)?V+k@+mR*H+%uR%g+0T}E;ebFB87asg
z8<OEZ2P7&9_x_rmf1pVQ9W)8IMVVvF4a|>2VNA?T1!sT(9n_B<9>ce3;3q#6QEk{)
zZ(v>b(NTClS2`8iT0<=3HfePIQE@tnhHYh2s<FV$lvP<hC@sWpp<Yknbot^d#Ctp2
zaZDZD#ckSDaW=jrzlsr$@B&CS1Ows?8lY82*j@mQFVZXld@LrMjoLTL1tqO7%~-#{
zEIamTTH0omQupkn1128!l#gr)cE=~0Mwnkh|MR3YK_P{nHWN2BD0oSILz<IAns;G&
z6a7pg(0G(h0aUQjD1daW!Q=MPD6|^R*t##$wJXFT_D8-uvRt~zdtAQZkx|#CZI<a4
zsx_{bv`P?oAxQ~`M7_~6QFOCl2&PQi6c5)IVt(rr%uvjBFX(@_#x~}b_ZAF~N^OPo
zP5TWwvA>M(qk<Z}U(zSJk{a^{H`fxeBId0DUG()*V;%tF@RaAxpyTjhx*~#RYo_gb
z;Og*PQ8t?$S2OHv3D@MF#*pXmJ_17&_X=*Qut|7K=ZsKDczg@MY1iNgPXS4I*qc#e
z9&&ym3Csas1^E|%!`^WboC-J;2K=bN2;%NN=VknJ0c3yRNqBbfFn>%MtkmM}@|nFq
z4&v?rj(l(f`Y{i>da3qd1K<rN*RM$UJAk_QNx1OX&57mbSUR8c-~ze<W@jNCnb~Zw
zz*vL#<&~UI3WgYL2?{S7G(Xw*eR7c&Ax+K$Ns5)-c-nnkx;3Hl{VX^I*yR9ZUXb~5
zV->;(2>S<9S4UutT`vy^y#FKV29C7I3_Cv>Q`0PjzVpK=(Ee}=?$32|F|Ax<Yzutm
z=aU1%`>pUH5PRs;=dn_^tYTp}h@c)Mo6W-1E@M(Y`8kt}(B`(DDC@{2>}lw-Ac+p$
zd#;f+%^z!jH9-H5#GCAQB<E*#6lnvy@4TWu#*XWngu9LE4o${B!bv3mV)D?KAGh&!
z8IaWxc2p2~<g4$`$%c*8E1h&3x7<NYpgwBJxUpnk2I*V~4eM7_Vr?O!ea&UYxbylm
zx4ET%-D_nE`_p+_5LmUT?zPX{<%T5%GHdgC-42+dMkz~uf*I&>Fo{KM;zNmFPVSWD
zkD*5m>bveM@Mw+D$AZo23n~n2ShivO4MCV1l#Wk4=-i8YRRgJ5e5qpfYSgLw<~BiQ
z2E7zL<|(k*5VQe@RM6B>!bV4P@|2Hv=N>7CjeHWH<9<jMC65jJ*km}j;rZ3ECP5Lk
zP}uljD%YIJf6^&({|RriARTT$MRvgbs;Q3B4!#Cf^*^$WQn2FcWb=yLXi^SmGrMjL
zY3@p(V`R9zb@nOJS?3PX$QO!^H(rA+n>}XQWEnj%eMBXyknJPp=g;|@u8Oom{m`en
z(PbY~jm7D*+fmdS-+@2?kI9c!#N}ErTJd1Z=;k~(?xBuan2qc!EI8pQmojnZMzuHg
zG|!EmB-k(=vNG!$ld%>L?BLs9JV#;DDZbMwFm+mSu0S4A7NsB3sDnq<`cxx9_gx!s
zVqR&nj>z?(wV4^ykLzjou5C$W7o@DH+!}Xon}Bk69HFrt(pisI92CJA35Oo@nx)*}
zBr~546MzkhP2V6)Dp@ym=4p<9y^luPeqVm9tey-VFkUS7Z7^+<PyH63dZ?wId=H=J
z^RkcIz66sCyrw@f&}UNi{7A5}3PHX^#l0(yd<*Vc!H0sw_%!zFXAU(V^O&SyUsD2p
zgnfI}T@TjQpD6}A!+uco;;lFg@IUWD!+I$7!&(#?78yKDRFca{@qbAxvDtYF@8Ghu
zvg%gRff5p{iN&hzck3gjmNJTdqIj*NhzndVl?&{*r*EI~Q*e9(wpwU84TK^>-*ge2
zTp;g(dS@+slGcHC0y?<;RoFpn#yStS9S%AsFQj!m?gUX=zcijH*peO=Kwd@W^q>u`
z^{l}Hw@$-jS-+%5z1~PjoQ+jnzzRRmC<{8if9W29vq0AVrBg1%u(&nSlnBHVY@JUG
zR4Pr+1<W0^tY6@;ep&QkO-pn}WslvwE{w^t8J6NEFP%JQRfhfQ&Le4>-(_TxUm2&>
zZrS&e&K1o+Ug$=fk4vC{!7Zw!H46Dvwl2+fqoQ2_p4##Q!|$<VKdNtuFeGf6=k0|A
z`>qSak`CXJoL%1QH8C14+*v%46;Bj=za_gN^N<Kh4*)=H;_D0FOoMA|t+M2T2sw44
z|BNmlVdmXmv9QfUcs-ThpX|ebT;`9y`p^HsH5a97M5*{qW$@x`ux7~*i5->DcNxau
zx2@nnH_<2!yRwp1d`jr~6R7CyAo@6N53F~dzbEGb40e<j@Bc_4x+z1m7oR~>cy=|R
zQ#!n0pD<uIs;S_30Tw~-i2=TRS|#hXaOWF#M6f&Z-P<rmF}CjAZwyC9K|Ew5@3!P*
z9<a*cNuTJ!5BA7$x&2+uzs|Mw7><72l6G`*Sx58aYc#)31hAl$PWJ=nIKyAF;op74
zSD*|fF6MvIArSYw;=)QKa@lyKwP~a3YpUq2ED!>>SwC3JujZ9nVBsGY%UWt_vT8tP
zlh&xR`cM;*iHGg82hz1s9ey@k<VU%>=91Mkm_sKny$n5;Eo+*BTg|$&yJw~7)9phA
zQ&F1x%6|ieELzU9vfB`^nbTf4L~*jFN$*5?4~036K5^INb#)@SUGyBGnhFKr^#MXO
z*|^<JuQW)ix~Pndm4VXU#^3h>$89VEXa1{7Ge*q`dpY&7(wRiQ*t)IsEq^g+Y*sO<
zUTiHd{aieO94DeRS?UI*Z!FRuQamj7Du8k%$7IKkO8a(Ht~%<;emxQ+*VUsJf}J}O
z8r&9GZ3^6eJI9W|#v8Xv;COK$8dsT1!?&w&sF5^6nThSkpjI|Zt#1)tO>*1THbMl>
zdFp&h;A6}&BC=gO5+<#md|C{S2kQ5L`q3(O3g5f-K!!di)dP&vvbTS-i&v1mBU*EJ
zO3FS$JNs0C6k#TzNlsN6+{=gnDuHC;;C&cO8}&_Fr80_Nq1_@*z-!k8#&jCy>dBTU
zo|M?cOVB9H<HB;@>qc;_k#ZgTZYC+3wecA-;*kXS>lv#J8~csiApEOQg>;=E(Fr$G
z7Eyk6<;5HsIhl^tz~h|s8EsW3vn0I6sXMW?td0MRo$>+Y{GKmR-hnx|kOAKtiG$a#
zRp}0pi2zIcY7JFnjXFUIl9R`#?Rm{TbjCii6diF^AByG9mdcLweiO=MMh&t2__Mdc
z^3DS#j8D!OI4oN$MHZP5DIx*=&P0lc)9UGd9IgH^J>+{M>#TbEfN*|pbAYTI)v0mL
zF5ZC4LAc>)=qK1-j0lizaI$zRKNi#2)H5x%Nm;<4B<BR2@Yv6xM^#d)48!B}VLfsb
zO^lAY_O64C<@Qu{Tvt<b%J*CrT#QU_C(XM*Qq?eRlAj9OXW!lYiM(&kidLPBASH=#
z->Z;lC)AzNTps6X3RLsD7805^u-g2hm&Etss~bd1Oc9Dn^Q>63KJ}>H>jOZ9PSz>u
z*RE>P%YKIPJxZ%2IegIR5PIjSAXc>VRj9R07a5mZ#mUasI*wfTuP3{$?C+ln_$WU%
zc8(HgL>nlrgB#S*0wQQayeZVm6<if@O8<$O{%b778b=n6ds|^4rpNeJTOp#?Mq>dx
z3=+)A$w)L1-_RHpyohyfSCEc#(KyR_O0&p&k?xaF$5P??s*iC$e=Q$)*-h6}Hds5b
zlFyG{)^=H-U>+v;CEu)p6s-Ws*`|iIMuhVOI^B%Q^uMaU;(n^Wq=$|zg+$a8uXvmh
zlNMNlNDo=WCWr8^GE&ABYZC=YDw`9&yl9QF0H3mu!D8Z0LRtNl!c)O~>%BD2&>E*A
zR?jVdy;Ic?kGV~v5{#K0H4`gMK|_xul@XVl!)nldId65E_7VtOv8!oEft_>y!NCV^
zHPBZUV%iP<+xz8=KPo!cm1YM6Mr3I90D1%hYhjH;dXUoHa~C}OA)3`*dK#h+-!%Fb
z*B!)>ws*6l$@5CT>$D+vg6iS^rzN5KHB#+KYEE@^B6*FGb)WRLG=h4&sIYS(DWj+z
zN0AX_OH-?>z1_>hYnTX=bSj2?GH5m-&j0$-=C=*~wRiuQ=dCy6;V`k3yq-6Av$|Sq
z)9LGN3bPFJ*x6oinVOXj`O2cmSWCV%ayzO?qOTk@iAiozhO5JK)pGksrOSSZx^^A2
zYkVdZn9~(g;Y^OEOtS3Dg8)uAlOAtIgb|FuZiZZp9WbLcGxbl%!$z<VmO)9yp_DMO
ziBNG5x{6KUAw)Uue*p`Stl4j*QOAZ;{@p5pO%N+|1Oh!vEFdF+R(8V9Gb<RZO^mI4
zc?u7vGt_6ga=d~c`~faDOYjY7vd(nCXPQ?$v0KPB&Sf^@Gn1nWf57Ma@dL&Y2)_Xj
z`2K<M?|)$Y>mL~Z_zxKW{s+c?RA7V=pMPNd>mL|D;QI&0zyE>p5ublx{0n%*2Y{LQ
z9~l46Q3mooFTaBXkR;K~LClOpVlecvHtrs2;jC=hE~76y^>9J^V!kR>D*>GI@Uofe
zJF~{Q_!6CUa(d@bvit4cxXIK#ma}nB7HT`34*@QfNflmwHrp=krm)vIm5Pz}H6R{C
z5nsII-Ybk?*W9dA3_*0)se|;xhIbiJy_%m+*q?;p0)FQX1By4kQsYGqs#_`t&K(SV
z<Flv)uWNf##%+PtAsNU`Xx#;xG5ZqYe3ewPJ)4T9R%~R}&H||!Dh;gfcb2V`N)8=D
ztN&p8`rfawqHrTpcBX?qgDseKBJQK0;f}&<@ZDeZfstvSDd<^uOE5uJ-Z=nrZh$nc
zVB<~Phb(Z;FM!onWl&u`N&g8d?vs)|J}QnLvDoN4Qh2i!P?6rr4gUt;H{L9+czI-1
zl(Nr#sMWKjU2Q-#9E6JIDNI>yZo%=KzWx;QDScZjbFL>Et2gC)3gLnal9ORgd!;;}
zbi3{{Q0VMgMImtzK|P7L*@UTHB_#8=w3RB$9kcHK)bJhKD1d<6<7;d5#usf;k&OK(
zHK|rkXi|C88|ZvtuP({$l$#$lk+hN!un@>aZqF!{d)buK>f$eW5tUI;JCUj3suqzL
za5qszuwZ^Py8|;=F^pu&^e$dguW1Uy?Ddn&+~RUJTb=ZsS3lZ9kJ|35@Tu-3GID+x
ze_?<Ci6w;S%XdWp*&UMeBY*%AAb^+)C4d+nwt(<w)=MOS01`mp4Iogv%9@oRr-X{r
z+-@>N0C~<t0U5;&9zh1~%_JY>zr$z02NAHnR`VxlEzS{#0f8su0gLmXcoiZrB!DE0
z86ZrE^o^N9CL(w}jE40s2*Gzp@b<j{4#X$;0NDMh^W%TXRZxfguLjr$kKjFm<b9I)
z>tlw?<R#Z-=|(8J_~)B^BXpgy8?xor2QOh31vlP#(U-J4ZIAN#ff93~{WgaK+AYq>
zr<3&4<_fR7xaZ!<wF_=~xmU<4GDQ99wQZsw*%=zIrXSeZwP&i-*2;g}9)5-PBdbT>
z#n}OyS}}Z$F&C(@n~JHFLZoyM2f~c8<SRq*G|kB+wM?`Ain+7TNisT?7QReF$mx8g
zFLe3${{+#hlgMKlY_qR)QXRE9El#v~{B{-;)|-LA$SS-P*06(>>4P|adrLUw_$bXs
zT3A0OlG&eq^J9EMcIUyoS-yKqnq1QI8)@@KKigyy;r?m}*;!PfApO<&ZDKni^0W8>
z2z-<D!Uy+`M}&Ihre36(*Y)5u^)~kah)}OLm|>4SzRWR?{-+C#DSGd9Q5E--f-wSn
zjN*gV7!QnBrbap}z5X0)yrOva<c5AM4NgtGWk>KPAt;ao6UaVhpoJhNpa8NMaYO)!
zL;Pi4azvnyj~2>4#<rEl_Q7Uhw%Zd9>AAw8iJN5jYdRV3fE|c&|9B+W9;auu&c+pZ
zhY)_$j=^MXCXSL7AV{B(8(<d@0-oO$pbr=U&ooU{@V}bxP0utQo~^oMG+aibY6YAB
zy$U!FtY5fd>6YzFDe*b%sil)sCnAZ6-Jd1YC^=$x&W-(T+wH$s@LG%mxNdKrwVG+m
zjCE^OcV6e?G-rRTC<-ay@OR`!`h?Sn_!MvH!PiKHB5-UbO(vc1TBT(s8CbYtAemcm
zXJ!353O+r5%BsB5uq2GIzNsEhs5>;beoF6LQLIX<68e{TK^@W(XPGzkd@JgY(Lw;i
z;>})M0?B@g@$g-BAV{@dHbXeBYy!J)p)sH4tWF@rTyLaw_D^(nb%cFIx=^idJ_jLX
z>h;Ut^v9_`R?vWRBb4%f0j-$!`_@5Hthcwfc64<DCV>7(C6p15^cYw@Mk7_gT4q~0
zn7Lg)K%<1b2QVBh|Bw8Z50?)oU0B0jZBouiTx5-`jMzt*m`Pe<1+Y%Df%g3;8iYHX
zH3@(}Z@Ua4I8^?Y(r_<1DNr;4X>BM1v{TB5yuNZpfki+^Xhsc{lBWdULfX)WXyLNx
z+@P%coHN2`f@OswNQbKXy|V-~0yLruT8D>c1gKuLtKMu<59P`NsLj+zEes2w4X9ln
z{JY-UmE~bjbiMsq6$X)Yj?UN8JqLgv?MIrZVjhJQFWEi*Tp76}!o-u#h+=~k$Ox@r
zqsE~9NE1~7tghmvyv2VBv;{xXHN|zX9vRRLPyo6gu{LtiCH%u_g8}%R6UPo@hB3p6
zXjSd23~dT+I<7#_>&89>V?Nrwc-)T_@3e~4VJZW>QN-T-+XbNcpCtCunsMM71+=I@
z_FCAKQ7>v+D#srpZ>~H6x-0ENLGjc76ZnQ|0#}tjfN~U{{7c}kqP=U}9r}L)-%&Gm
z<8pe~H+a>k*X3M^SO1~Y&;;nBWQ$JJ;oI)pu5ttj-LDAt(dcfeb2}D(`FnNAxoi}{
zhWHX_spzf62GHW4P<wWJ{FGnVEfK6b9d;TsfUN4~`__~~K)<2^>H+GN?^C<FDzkO)
z;#;oIVD?+oDEKZfxESs90CfO$sDf3KbC+Rj<4*MhM#h+lFKtuwSd=|Om74tf@2MjO
z@or13UA6S|QbTlwDuH^6fM_(G0egUYRKaR^`OC2M<dlDJ!(!8=4#il+EP=<s`+D}|
zRs!SQcZ+(zJSrH}=Q5&3yciN^VALk|J6hrc%md8h2m<sle_IIqnbi+6;66C|5G*K_
zI~RXu0>}f)J3s&dEPPZW68o%0i)s=#s(~vGy8wy9icb<k0Vw|bY=oxyS1gv!x>;LL
zQNTw}fJrk0H{GSi4iUpz9(?$x3@{kE?#&^tG7Q*{OgUj=1Z7$FoaZTmb%?YK;@PSx
zo5=}kQ7mOme+KDa0(1g&HuBqivaD0Sj1%SBAbkmHZ)fa+kDNolK)+~!e=TKiCHr?<
z)_sr>GLXFgOf%|OVbf*!w)mO7wVZkXJYc_a32~b*J-{}H0pf9=PYdD!Xa#5mtw5}~
zuuDDVp--N(8|%RjhH!2H%Yep^MEnjKap)5{7K0U4(~mwPI;IrY>^s!kCEsKLd<k`u
zEc^9RcyAyR?OPquRY0V*xID^$v%U=(8P5f#VU|-VTn=mOll<3_IDS-qk<5S@F0vvJ
zmXv~qwLrJ?vJNa^LrpW$rX~waLoUL&o-MaSC1pGvPDHA9bcOy7uGN0cyS%H!`1gGN
z#8JhQ;PtK{c|ui>IF>01;ii!dj)2IhF0Oc@<R4LS`dSqlR;afvRn??1JQ+a$Po#J8
z2Cr=q_)6lMzhLSjf6SOtMO4E>OC-qhDID%GXQeFB$~t4Mq%PNr@-(<6=`4{Jj=Vs6
zZ25E%VH+U+&M~q;{gz@(>HF!MgfXB%8tYJ!m->LpTW|TV2r|fuaDlP%X|)!bApk7R
zuec~RVS5qi2(?5LRo@;qe4P>QNH8)Bj}AH=u<$i7zn^qP5ZQ|G+A6geN+lDUZXCoh
za}Pu7flm`zTw|~M^}(l>1x-guzoD26$jNu3iGLWoWdAD7c;RNAE#4`eLIf<4?6OwT
zOoxNYxD3}ESs6#UL${XDxh(3m$r9yb1*wFk#EGtrgv;njrA0q~J{L@&QJ^s#g<ijS
zw~I)~l9_vfz?9w8HTLb-1@p%5<Dkgk5G)W_a9Dc9zJT21Js*RK5jjXUNOd@M?Tbwc
zE*^N1s#R0YLWLQpna4am+hD(hkxt(H8mLCC8Mm2NBoItzb9_VII)zu$^qi}lE6~$^
z7@MHJYDo+&nAtSYAn>4QuO-F&srPchI)!K3@SM|}(;%v^S{RPt`Kf$44{5>Zg<ye0
zfkP=0q+!kh@q4+6{`kMiO0Pd#&vVWdzzo4~#m4$oM`eyAt^MNy;^q^%k$+_t#?9+k
z#^d$bF#k38GDp`1(*+~FC&_3Ci`Bx(#>l;1Evij?4mKN?r7zYo(#2VQ1B3>I9{miY
zS1A0G8dkM-=iPp3&Ur-W(MyJwgt*L%0gTZ<i=l}-`d~|$BQmi;j_pLRfo)~<TNgNN
zG62^X*VTGnLT<_!T02jY8|8;6i*QY8Fcx?gc)m9welSDWH}HQ4>l{NCv_#j1)`f0`
z2e(@rSfPtD6E0(pc;W3~>|um5>C!X9(uQSjo;6X@s8Y%3l^|Q%Q?a4Ja+SI2F=1-R
z>XF7WC3`@f&Z3u`vgF`6d;SI4A15hy#P&^EZ!~s-oGlSkAMUoYPAM^;QB<-#VV$nb
zBfy7&?>t?WnkM%B7rYZ--74wwsD#bX+rUTc%9NK2nuWSXK0Y-_`@ZH)H&-{8gYG3&
z?PPTO{z9QizTEn7z`iJL##JJ{^H2c4$Joa?eRBUTSjN}y7EH;fc2zsyDv4P|ww%_l
z^h>iSjSU$q{c<sxI55&J7>mX%osGMKYvpL#I=%I-Fo8*WTg1<@EXf?azUbtDDLXUk
zEA#M5fY*yBjd#!r+p)`!Gy8q2cQ%mfuH?je97cxV<i3^#P<>q&NEfIuqh3;)U!(4~
zSGA11oBV6dn299sl=k9ns()o(wmJw4I17A<Ta)zUMdC)XZfdO*zBPt2o-*&r^zrD<
zg!a8$GMyzV-v-?Y&xsfR^}S|r&2JB#F1sdod@~Fb{GaZWFRe&v^~;{yi2xdt(abPu
z@M+tWI4vgCuelkMmW|nK?0*3M@b>`OlLuE3WFbo&Ot7~h&-1PTtq3wKDG}%~dpO)2
z0~%RC%qI1M^nd`7#n8{2qMG>G>dW7`Men8(6ah1UG6c=668L~AiY2cE3w18vp6EP0
z50dWZ+2Q(%_=<qg5KZsD=g|FX44p?7E5>#%La@TL1h6E~1$NsaY?D+Dx=T-_?1mhJ
zAIq-zNX>dt$^Cc`ZkLtIO+Y%dBy1#RfMtmEHA9&^_n4zBN<ykYF;>6u7yo%6v>r5|
zrkG|VOhuw5%@f;QhNL$+D;#M6X#!m!Q1kf2dLU^%XY2Y*+(G4TT;*}zLmDlcNE4&;
z`J;&;gn4FCKeHV8nlP|6;iu+Ult|so$%SfJ)D%(5JhL(dfK8MMKc+de48jC&-c)m#
zn@}VeqI`jc&jiL^ioZN16Z$YW6-W`jA;XDwV>(xlYGt53*vt&TSK4`lSvjfladYsq
z{L(<{BMwo#;5?L16qA7k3Eo9uWk@UHS^bY35K^VFf5!i;E)MB=@%S3~8YP7HWhImb
zD&V|3V9iNv!X@8oefbkL*|p@E=Gq0Sa)}AV;A~v4(Npfhl9UP?i!8<EN-_M*{>C6u
zPL<3=T~p9(J^X7)QOH$;UxWXaT4+0X%$d=UXOjGrD$daEk(_e#UbTU@kRhKm<HQQ@
zl7Alp^lE(mB6<P*g3{*2dVl@|eI2DAX3@lGr(46GC2~>OT)Ox@ZC!aKzfs2ZVCGZ)
zXUQyaTO;K7VcV%dtp3Ow^LtOR{z>D|=^_#~a!vIxvu?$dQx$r9`u16?owSi|qkGTo
z)|kj!c584NQV~r^j3=FnQN@c^W2kpPx~1*tP}cwyzS8A`8`7`?_mq7r>L7~Ex{hJ!
zFsr(}xfc1Tns($A=kXSSOUTQoMs0fB>7wI>@-Aa)90tBN&TZ5{hkIInp>4!;^-La!
zcYUC64<s&V`1Roy@ie^BnhSm&UeJWyhzA`qewS)W^>vB|D|%#6)uiC!`K*qZL&%s@
zp}TPR*LHhSzzDLv!jyUt-G1@VOfvXnQY_!#^#r>?1+u|RkI`})goz(=ODY_BrjJZ)
zch@FS2d1|4mrLOc@-<lq5{(^`0NhGP>``VHQ(u%Vj-CwDK2>xT<`Swmm($?nM#O9k
zXTP3_Io8R0Qm?!0)!b8Qrv73XH4ST7EZ0$5gV?<!Qyx>vU$~DC+2tGdg{cW_s(H0G
z2`;gl&TKC7Fv+KT*U#P>VtTkFs|&-)XWvwZ`SW<h{LTq%yUpO^z9(6c`=&SvdC5&P
zYU>^kh7>KAf?jD1r<sbiB0p|``g@^zwoG!Zbng#)GO?aawqc@d8LQT+St6yQiP|0y
z7x_oo(Dp+P$S{u7XmUN)>kkXE&epcBGx4%g%Jr!QhD-Czkr#$lvwE&2!XuO{S&hsC
zxCffCgQQ~z@w|_hMC4By{K)eY_D^Vo1U+Zt_}Nxj@~Z~70s&bvbL+i>37dk>zc^B}
zTO~!Z`jI9XMD}Whv<EieMwA*Ju*l?_lR@cb?>iB-_s8)JC*t$DKET}P2ON5&Q>;AX
z5z3=Q$t?PNyf6EPf)K9xeojZOe-?wyl{Tf~oWs*g3Hg3cL^a4;K4{qRQeY%-2E^KG
z_d_k^9vap~t#1J1Ev6oc{UssZHMGz0bMgcZ&qQpp8>tt5ViK?=O`a-c>b;-Tb8?xw
zoxfAk;kY+u``8FAq=MOIa!6XypBW{FUq7@tfw#8(;jJv4mNDTtl^k_fh<}5*c^$8o
z04KV#r)JG>u8i=tr5TeXNXEo-xM4|ibtw#T(Z0SqF5f0!ML{mILX!U(b$dPh9%Qo1
zb<HS1ek`qnlq8sqtxPXBvwJ!nJKAIA@ts(7%*Y!|l#u{xYWXmYI_kGm9h(X&y@H+p
zI(RoezT{$t?VX-Qhi`kj%z;aGt)Z4-@$vCNd_75iM$fY@<vMVf9J&7f8vh2D%$s3a
z3*RsV03-qU_c;dz05Gt$FmSZDq<3($b~H6|Fms^)e^=-Xjr5&N%&d)V09-RJ)ioT}
z*ipQXf19TAUhod2Fq1ay&kznF$hFYMIKLktHW8RxjV2y4f4uYD1xZbknl-oA#7{X6
zwc$u?w|a_+4Y+<|yqx%jhT1!;RGGVDA|BaC*S)H|TF>#8CvUS!1`iS;NqaF85uzjg
z!ig!bJNL0Gycs`%Hri6*P#2B^Ic!|qGGAm&+bzwxQhA-eEw*b_5FD~GF)5i8@ipQ_
zEln+PF3sOwuZ;j51t&t;0k!9dPhkw?iIzMW<ju28ssNz9gm-jKs`jYL?p}IGE7CDv
zY`&(W+wSDh!M5sC?2^+Y4Ss<E-3a$WBAnoEgp?A?lO`Gf(v>7ivTc1IMB)C+&mjXJ
z!cYJ}C`2bXXX}=uhyPZCb~_W)7*-uCZIfn1bt*kpLV_gu0QmmPY=il|@>b@4iIK`I
z1nVv|2Y$d}q6Qx^KaOn?K@S7%5leA^A+9;@(Ns7$Hu9j-k~~eSVB5F04x|;fRt&F1
zYKg&n2>#FguXGCoN`7ci0+r5ZQ5%+Z^hfCWrP`t4(BeqoGy1H6vgMERvgVM?qhEcP
zA%U*Aew`+mWlzxpqk-N?Qe#LwU4DD~;zsz@6;FySzDl)Iu>zUMV4)<ZaU9O*23Qq@
zS@u`R6Hp9ynb8Q~3`Lif0y)xXX1S`>Di&?tZr+-R%+IeV@5D%mZn$FP<{=)_*MbGZ
zu3f~=5b?@%J#@koHBv;hlO6{O=Far57lw3h^JiWD->>$dFZdO)o4AfyrM{LY=;pre
z1+=cZ@G>;D)5mf(2lfH^cA`!K1X-Esr6R@&q|cc`5ht`J=F8m1cxd5?wtz3OZZ^L7
z>Ej++=$<jH;X;=7n$FOm-!N>$yv$kgegS1yp>F)8Pb?X@sR{`;KaI^a;5q*6D5w6a
z6t}i@>;~&O)`-Z(UmYb4J75Xy^P=`{GQh<~!HTIJ5O6hT4JBqAodjS7P=T)v)N>}9
zjWKph$=LPlh*i0W(pKFxTkSfN<zy>&Swz-%`_6Q<2T@UI7C(UERAFIOG^&-W%TpIR
zodlwd22lc`9QE)AdBqCQ4-47ZA{C$#l%MQ}Dy2Yqjvbf?Vu=&%FilN*>}91b-n>}d
zlpEE98yf0Tw9a;VN-@dyYQlzS^NU+p4~oyQ01i=D#ZYQtyHHaOSjA0go;sMHQD5#A
z9ok4@^ue+ww7BB;IQjT&-)dyB2eTp<VC0oSQSCmBsEFdp0!Z4*d8Cd|=n(k!y~hQb
zYpu_0uRR3Fae@H-yFO?qW`GEqH{VEp6giKlmc;ax;t8MQZg;U&WARw=RlrdT{y9IS
z<~rrh2)*@a^BxfWX#mpr>2zRd*-%jzE|FZvko0QMI-ZKIbc%4~^{t<ERaAEl5_fo}
zg%vcag%dj*BNoG59IihmjYN5{f|Mbt$o5n_Qe1&l8$8jMcLs@bP(oovX1Sto7<t`>
z{HR?O_nfpiM-vHyBjPv()Mq#+8muVr(^yA2u?cU`A!e4FYOXR;k}*qGhBmpxv_B&8
z8jbb^I>I5@zu$Ef+Ji&mTAskNmFC(d%}cv}+RAwggca8WzvjT}>>Id3TtiN*F{mX9
zdIRolZB&N~@}fH^k%yHOr*W!@*<Vq1<U`txNd*)g+fNRYVOunYUZ`8I*ze~!BlpbD
z>iGSf|3G|+l2h+ld%(qI*Myrvbi5%1Ghy&5*b7d<zBmgF-fepW4W7*lF2sCIwkv>k
zCTFti*&4uXsjL{Mn4OD1O*!7eaVQ=?+(W8DTEC?*7Tvjbu{aC=U16lbt3YD(hR|#w
zXRpA`LzB+?8#B?<o>D;t<;^u0PZxXgYT#lkEnWe=G~3j(053L%NBK-+Qc+Qj%B(~h
z2y9Ay^j@<nY?G5?yEMMh@$s6HG-<5#cPrH^hi-G+#D<2CFgelddLFz5(_%J=U%k~s
z|3J!Y^{-kUr!CAN+u3RQDf%?@#WruN(=(k$Z66JbWeuzIMg>Y~dd$ShZWHr_FR<(;
z<*+2m{h#9j_dmyjDgpq2osNT>!~Z%Q{&P=fZ)9SnXZ!D5z_qa1V7+s=r-sPyA?;Z^
zZ*(v_YopT~=DE<qC4Xw_?BA`)A+1UtsVWGK!>4`QwlNl$T(J0U!G+D0I7^fy3^(cq
z&w+FOZOfEhON~g43ASwm)6~S40?{#(+<W+p-5ue*=Gl4M-&^mcqbVWBV2V@HiT(IF
z#4M55>HYoo=6>$(LLEW>&b7WC@YOBn&HG%WKgDL0gM{a*A3*7TYoQl`-H0A&^Qu`A
z>LKXz%JJYTC=(?+6>^+@+}(wFPQTyl>Txdmip>xYz=`XLQ?AjtUA&!rDMpkut32RY
z1SJPPjq%Cub>njy-N_)nXUnR}<V`x{nZ$qpt9!4WVTKmw;uE@RAoqG$ur%N@-Ri!6
z+hv=H3uc+#J0oZdoQt&sjvSd3>7r|!t@{{1@k0xzW9xdp`}JJ;R>}?`T&h&px<>i4
zFKVG0+nmqh3ZU*9?&Oz;jV+_60h;>DffVZG3vJx-&Ig+NG$yN~&T(aFfIJ=nZkUVh
z$Q-}7H0b)~YDWwta6z9C;~`}HU&1X<G_V^%h5~;Gq`^K&p6-y|lsv%Z6$ou{{C5hD
zWG1|N62lBYK39BJ70zYfZU-((XWDqm`$Iz_eE=BXiF}40LieENUSaK`U%#-S&DLfJ
zB34CGq&;Z<3h{v&PkZ!mn=&_o{;^#;+nGQ(Sjcs{O`K0M?QB;f;{>?nHZ1vL>%#<N
z+zcSpZMOy>9{cgPp5x^Wesb~#U*>xHv+KTb<2bM!o}o7E^_SIYrPN0l3X={hM8!6)
zY0{`+{s<7ixy$9NLE);+oLo`E$3^anF$dbyySwQ0-{~e$x=DMlNRosgU1n|$UVPlF
z4h=GBVh(hehBa<;q~LZ*|05k|N+7)zM!(tygcIu-Ax~*iZUP~H3f*RcOr21SK{3c3
zbDdwjeyDXmce>%Q?v^)~Z0nb5Pls4)XvtzJn#9M(2E3GD&fZz5-KR_MpLx9+*55;0
z7r=-Fc;y14FSF;5Slzwl;I-b3N7buem<0fQB&B7DA91M6lUUNa0v8I#EPsr_O_Zws
z*yA$lNE-s^!$;)vx5=$K2)m|`(Ys$<Bsa_CwZ*xa30s6QRU4#+V%gD-P)90Lr>U$u
z9?n_)CQcUV#mQWfG{h{WYeNV)z=lu^26pB_RZo<>q1^MG?wKflp+@ivn9o_cCW32T
zp=>EwINw9-fCP>Tqn;__IfKt9u*})11cR49hzLtJCF4n*uuf$|<`yL)3gjRMIu>jm
z^cEVJvsIN#UIo-fMlk6SWsxZ{EzZEXWHwcltz>Q@q<@CzNrRO^8%^(|R4gl)EJGpN
zvKG)c6<ZmO?MW#O3Ix3yHbdYqxWfe=mKj)9%=Hr4KkHjra$e{Qo)&=6-bnyY79KR=
z7exZQ0cE<^kZNfX#;OPs4xiBmDhUIa!_)~=|E?7O+hJ6Gc-5eOHST<Fr7X3=u=mp{
zu3*1h=bV>L43LG`<$xeeDWzXU?Qm7}vnV!$emqQt@y!x+m_;K7(oh33*-WEBGM*t)
z%GfOQud^ZZK7t6XEOCRpSh0=R1&4pE0M!nt>!b<s$MM4^kZLJLbuZ9<<A`VDF^W}s
zSpm}lDXF@UmO-z&xU#6PUgvEYf^Lb>M(!{AoItQn&B|WQ5wt=6f<G(l01;^LD>oNj
zRUlGOr#62%0D2!*oTu2=-Em;I;Dc0soFPEAahBE+*`JElmejZ|o1ic?ELtM)M)E5m
z{E-xNPZ(6zDsL1#j|mX|%JiSRuR9PHeL!I$=rz>ZWxxno0_hYuA0-s{>A&{usF<?#
zyRt}Nh^+PZ$WrJW5dW|hY4M9d19Yq(<r6=(Ih@%g#p~08%*hRYafS-y{33E<XIm!+
zf!;%&Wg*>nE7^d%7kE)x_fRyAJ?gwrNkp{Ee~V}Cfn7j8!u%cyO6nge_JvtqO4gzU
zw1s(nw?A$;U2}1haRNz#_@}6N=C%DHUO?q@_;vKh%YFlY?mkOkOb2D#m8!yUEI*cL
z>@#v_Q8A@mLDK3Agd410klV4lxKMO34@ENT-e=_ZEUmn%9`~7uk7$IajAcA{&iH~7
zBFBf_AYHl|q+gy@gww9y9|0{JJ8hBJbB78Y-yEH`x7Qb`Qj5AQ{3<fypRY;!#tE*u
z00$<RXs^vB^+M*Fv&5p9c37JSDJ!6dV*|Z(g6+kLvS<$S<C1{RB9?ldMvQpOnBfBw
zVH-VG?%CH$wS10cT4k(uJ6y?a`AD`(-fr1Hs`4>I=uH|#3<87QUKc^GFyik;8$=n5
z9xpi!M7Sght^S@d_KJ|(zvR;hLTZw_g7#g}f`aL544yWGF@V@-GfmDDAopDe_N&nr
z2Ib9~qS@H|CBPfT;ySn?rD$p-3U(^GvsK9ke2mo=6PI?U8&<CLXD5h2=C{0~W~rlf
zLN=JtI&aR}gKvvKX~?A0LR?}Q=vm9~KqPq{Ni_IXNsl-zt5-59E;-383$X~AP|RPa
znO*j@@FS6TgOmC{cQ1;&`T1wbdnH>Z@(;$aJ;GZ(p{!9}#UYBZHzc7E(>?Yq8Eq9v
zV^<ZF35~_%plZ1D#e?J&n1M#vjnB$B0f&DLP&=-?MLXc|AhlI`@>!wWP&??@_ums-
z7p2^!UA=U@Ki^FT&P|S&n<Cu*@X-3PAsmE7Q~tC#-$ayk8UpoKR;u|m1d;+!XH0yw
zG=#MFP5+KM-N<)wAIRi}nG@-wz(~*RHQa*1l+=5tYrE)R*^#N_4YwPFxP}tpLDeH_
z4AF@L6#SHKN%aD0DlRo6J<~oo#jO7@#)y&nxhRIwm<80rj|r#BXj;8AHUb@m&d1Wt
zTLbiRRPEoK88Wzj-VL?ojE`os&Fj>$$rKIh`9>i#6bn->L33l@NlCLfP~t>t+r@!{
zODCn_0o+ur(zk|bE8OHEg~o&?fdy{uiA`wMi*P@%k_iF)!B7++WQD#BEBE+IRR{rs
zu&D^|QnA+UBpfeuX*n8J!5wP_Su#zSFsY~srK5emKy#LR8|azx^N)5atNY7hu}ry>
ziI-NI*r&Duts#I5p%*5!WC_1qD1p8Qmrc9&P`>yL2HP(L?5PXP$wN-QEkJq+5k3Br
z0$hzxLTvKkuypQw%>d8Zp@${1!FkzpZd2_XxjTi~Nz_?+4;Ycr84|uZfC{3ZFpdO?
zZ@(s+L8qyR0netwp{G8jWx2$tm7kHKqziKfB22K;QPHCP^UYF=@rRSDoaV~Ylg7YO
z;cQ|0TM#b$w#hNJ(Tel)@6OKOSs-C?!8mrz0svzOW1YZLh#6T|*nc+tv1MA};$#HP
z_Q3NGC!ny<M1kn6cLWaYw**yGoWi4oZ`htPTpLX=6pFjrFLh>!l5G+JiGZ`+xO+?w
z1PwV<erSMrerY{Cv;{Kj2vtX)fZ(w`9CcoSyaPITOBZW~jVKu~;@=By=W%7c87G^D
z1hf_ANmhxRJP6b4JVk<5a*o94<NaMn^dd62?zV|$;Ea&DNSI8<k-)zB2I3B@WO06w
zT(@lItf0BVXa0q;$@4NC(Sg&H`M-9<M4y5-Dr%{6v1yK^pd5e;L5a~6aI}X!xA+rS
zjN|#ppkvERNa;Qh3O*#?T%Tfyr?09^{*Ew0)o67U)<l|%B;LRU5>LItRXBc{(8}sG
z(PCzG;%DPzeOshbj>aw8=AQ~td)U(<)pzf;NX_*LFa$Mh3M5&_HYx}&mlaKW0tuaY
z+9z<62u-wygKVuqNQICUVoQq9&uK=MW$RbAn${rIWay)%JpLYSz^K$VjkVakyO~Tw
zrw!aEL+5Hz=^NB;LCI`2bgC7C`7nh~2xWvIS8BR^T=tI)BQNfTI?<@=pW4EvyT%qi
zN*gyi$vdea!vWb1Us4;k`Lg5Y<<xX9y;$iM)(hwN7p9JU%y*JNEC+H=pL)#2r2@1I
z5?cgh8H!HX5$_VkU<WY*gwXAQGlMs}KPWJ+$8!WS^F7KP_4sufFD+ZApfF>0&9&5j
zx3jcp;j|9%rccI2mL!O_USI*yAmMv)vQt^(s4T)B>Jb>(Z&dqd{{XUU3^lsf?&!Tn
z$zwbxE@41zU|-msQd`-HMgo)d)I?D&VOoL`x*2iRCu7dxu`h2XKSdZ{f1F@>ck*}%
zq|#ZBS{-y9UoWx3zmt1*qpKlNDMQYJY1i2zSye@0XA8Zc2iK8CWxGJ085}iFN6g8G
z@^5p6!*sORK7L5P5!Eva(XZGB#inmar8#%jTk?V`P_K|_Mwj=>am6*04ShaBLhBdq
zv{T;*x?H~^SC#oTlPNsHh%qEADWUupDU}&dk|XB;*7*B8JlZJ~^4aCzvlAyyX$`L+
zweF4kyx0NIO6Yt63qiqhNe~;Ys}us8R01;@w0JJ%s_~wab<Gfk**!mRcD=sbz=+&*
z1i_?f1i8cuPBtuJCsIr0v2gm{E=QFl?qJ_X7Hn1qy;20-@_H~t%VWUyS5QQOC6kE~
zV#p~$WM+r33uNkw+WiL4DF>ce1UxwdaC8D_;{;Gq{O?r@7vR0_|7+61_4T+l{*Q<J
zu;I^L6&(Nn<^QuR7rp#{S(f~ptKfP*&jA`F#A~fGBhc;QBgmPmiVVD2usx`nB<K%b
zrEETa9qLLEn|<>xNGHriLK&LRw+6?A+q`mNSUG*PtBZ!FH|PCA?9VulQ}22!Ygltx
zYdib+-l)<K{smN*j5baQm$ICB4I+OG4cE(nwMV;@ae}lUTT8<(#WX=>#l$<6Qbbr@
zSXv{bQQM9Ei1vC2yU@=!;z&NHm-Z=x<UmguD?deY!+_nTCfKPYZKrHjKrat|@v=Gl
zx`XP}r=!zJ)1yKi(|#2#?Pb@XZFqNPhWidLd(oN_a!aedyOSktjW4eKD4b0Iihi9|
zZ9iNP73h0m_vdS04;3m(@B`V=5g4Kr5Jed?QysAf?*8?58qN4K@u_(|OOt^Un!P{e
zc&9s{^YVMv&exlcEhB{2>V8(6SVjYPhRav$xpE_0zQm4iDzJ3P&%!6ezS!yN;;QrO
z09vKTL9c=hL7mQC?`{rCy`BTwDUq7YNswISHBLZe@2-5+=(#YlV-`YAc_j%yo<q8&
zv#ln`4<ks7)24w1U(z;<{?$^t?AouusxS!d3Cu#PBz4&!u?4kLkwb^dPIv!=s@tRa
zJF1WEIxw1tL~d%>2lIA3`Dccf=IkU+1qPL?5@uv#iXVp#S*X}d!fDZw4Nfz1dmn<F
z@`tK@&lQ0;^}7z7;xNOU>kS9@Bp1YXCwkkxn&w$&W+T1hGoX{S+p*&!v@g0@+=+Rq
z7UW`8p!sjXM(W(PM0qb|(t<Xmvj16p46i}>(VsxhBuku0mD`cZq9uKt{-gZQmc<4y
zbEuC0IA2PZRB4?3kNep^;!ss!*{7T8$CB;qfLkzHi}A*9?iW5-ws`m6|4<MF|D_<B
z0sns}i2uz_UvyeH?6b$weRz2XH8~SKc@Y<F#CevMZD#Qb#3l?<Zv8E&u$Rl=uOV4G
zYM?14Ei3ErnDXI+j7boOYLiDJ1yH??8b6}FB|uIMlP0)5|9*SruJD2{s<-8Sdv6~S
z`P8DtcpMI}eRz3x(W?IZ+He1UT-Whd5v$*MU1zZMA9clA6#a6zd3N#1TOGg9x{S7E
zetGA5VS&opHtKpj&AY97+VM#b{_O64-`i@x_I{VTT=wz!?pnf=%l@SBY6#A**z_z}
z{_1|>PLm6G7^-->=w5i+S2zgCPvgS~MAUo?X|#Rd?*j1A`uJ{qzMj8kJ)ay8e;W=r
z-p`wTnSLw&wq#{=A$?h}#dx^2XuK7=bmLBe4^W%Lhh>OW@H9#4_;p(hzz9_Yx$<SZ
z@hy}UWx{lVWws-?g9fJj&f=a5()~C*jsAsD^@?79TL8Ze7mO}2XMtW8u`Rpx_K1E5
z=Ka{tmjT}GM51K(^Fr3+vd$j#%Mw9K@OD724g8la+Q*yJ8+jLMgy+l2PO~Xz2-m63
zfyXXQAYa^%23g49Mf`=!@KpyOA;b;Q74k_CaI5p>@~wXojYq#>3e{NyRG`3Cb^dpu
z>&=yPd!vjl+;#2Cf!&ibU@WGK^~~yBRUa{m3(~*$asfX<e_^sWhlIWpNveW0!VYdQ
zi7@fw?ssFSs~af!5@&>f7mTPc1=PdN>~(j`t^?R@^Q|k!OFk+Fr4g8&@6ZAmCd4j<
zx(YN~b{gAbbT(E9a(h5T&hYL_I-jGz8bad{lkDpaGsYRi-0|0bS}k%!9)mkz7sxz#
zH~s{jemnX{1RZn0hkJUcq1fy<)VCC0GtjrJ6Z2*p?JD4CC6osN4#?%{i(0)A-(AT5
zaK6JG!CWX$pl(i~r=ov|tuRiO6_s6$>s=m8Ry5exgVF09l>N}a^XfMxEe;oMpzVUs
zYM$(w<*gMX?l-ii81ff|fq!;iiQ2cf+wJjz->)RyQS-=R{xv+I@B1>0eMpJnY#t*3
zm|+xE9N8SW`8$df5n2ogxv`FhKeb?_o^Tr@K3O+I0k1SSimU+eIptP-{_DiDqC%Dj
zySpIKe4aS@W&rmam>puqZ6#lD+tJ0>3GWA2`keTD+_(9~PWZ$!{m53NDUZdwY}}1i
zyQ_B$;zw)fjVrq)v}sV$(gEGVaspOZ9~>cY@L(*q!$htYssR$bo`l}0M<4Yg_>a5T
zhTdKM57y@~60eIaeCevw6SkJf<E%H90Y<q@l|7AGCeY^xHkklfFjIZ!(rzGdSXk5f
z%%&g}fL6Zze}Nc>W-Ph0p91tzD2qZx#(^c&hRn^8^>fU7r$=4E;_fevRJ21;{Cqz_
z)zN}JUuUw5qG<|m^2n+^Q9^=tI&I&QI~sr>#hlvPLJY+J*i-6+i#R4`ep#|!h4f4V
zLP8AoG>w~${YDD-Va>iq7+r|}AEw>{rjlR_*JTEG*8w)}?(XjH?(Q(SI}Gj&GPt|@
z#&vLKaQBTnmvhd`yEm!sR99Cj>2!BeYt{Gv^^>#yXL6kO$PP&ir!g68Wdly>6ZsOe
zKm41O1+?mOu^@sAj4RTa3)CbN79WK!anN25U%(IKpMAHWK2MGNiA|^ABk8+2_`*^r
zvsb3Varo_ualJ}bTvJu1oVe0@^Bl1~YotZN``x}5MmP}<uLl$bOJzFWwK8-80d3ER
zpfDH7LwYI}*ehyr4AB&l0ee`IR3^XlJYS}qPOD!$opf0!>WN6TY{x47cFdEc*VRyr
zt21z|dRd8}5PEfZ1g0yGpXNOcolVLXbau`*Q(XsSFPE5gQm@g;Dd)blzuQqKX_FX>
z1BUcj6#OgSqhI%1-7Z6dXN}%aXnz|95VxY`@37?ty;)2Zj^R5n)D9}X!9dTVW1T*w
zKkZ_?+_Y|Rj-^6Od)m5QGx{{|HAq`ay*0bg6EUnC$mcf`J?penpb)f|z^;{%u_nc*
z+5!<|{{jyRt`}Y8Nx=7v<fVHgtiL1tW>XOQpp!sMo8M$}Na!Z9DkFM|D*W}~^i*IJ
z#)&p){96p!;gh;A=I2YyN(+wv(rUh|$xPHkzBZ^x{Ku4Mz!P-vC&9Qzg5t#=^mO9}
zHA;(Gm<n`l#5_W`Xx39f`H@19ZwV4%h%Z=Z)(53;FH!wcZ;~d}D5koL{vv2)$WJ5p
zH<coZ!z<172}0*uV>8kvVa<cxFT+mxAT&l!{OW139Ly7L<RPA6SHfuA1JA#rIk!qj
zd<)#j_dNJVd>F`jJV$^2vNCeqDs{^BCuL5T3{DSwtq9);2nDGAE%x>P<2DDWQ%4O{
z_NM6&=&kShmd#@L<A+niAhtu_lAhU#{|YN6Zk&fqP^!b<2LvqvmFqJ`5Z_Dd5XtEf
z+^H1{e!;5hQ=ML~Oii_&w}Pg$r2$c>LMvBCA$7D3N&A_1T9BH)jdt9=b(*$AvD<g*
zSux<uCr8{P7@<o&^HAGGt0xcgT8kcXdGuj7)QuTmj1m(JDaAM2lG3c`3L^3Dc{9vr
za?$y#i5>Q$+GdIOglnW`te#S81L(01@&E?tlPrBU4@npG)zj~LUnb$|?L}@4k&_;5
zqAr(@I~XxeY^qCw%ZV0i`pC@$_p+Mo2T36n+7X`_kjtI~Tv*Q9EqLpkW?IoYNb%O(
z;YE#+<4f-Q|JKPtQu@;-s8i`RMYi@c=xM7G(dKEPLnLIYEOv`-<cj|!Uyb<(NN6<E
z`eII{bfg^<#pzlzI5XHs7aioKv0;^WC9jdA@=vT<354^HHR1!ve&$!FYR$yfTw1r(
zL=o9$QByIsmU_8BYyYeW=|i5QUxoxH#b>DcFu4RF%d;1!)fCW)7`t`6YB$d2*ue&h
zNj;berRJH`MV3`p$jJ7`<u1CLeFJMIQzcd=4a$dM%W=1tOvOkHrixx<RYr&jV5+HT
zO)TuFNWaI^(?nS&Mph&;B74euI(RHochO?TeW4^??j~l(30uHGo;&zRz!7&N$1kwm
zLHP$0aU9|lDF7F7oU9eOP`i1?2kjx;-T%`Fdx5s=s~UAAxR6-z&pMhWHfDJRTPayt
zXsY`gbEXePp_QUo>~1?6!gRBdrvt>mtuPZG0CM0~nvAb}iyptIn*h>-_~L@54qlqg
z@DE`vill?2ZMq)b-wNL46@bcK)~xx0858VC`NTUhbM&zcm)LSYaR(~WEc6bF9|qDa
zWj#u<Lt9|J!H!@Z{3+%pcxV3LEx^cN{r)o1m+_2Tvs%CLbf0}N<iF3fnScZ7Mvj+n
zI}7$N66!d_Do`LA>Nr^`5bMtuXmxSLS{Gv-P#UB!XX1s}a^Tr^CxB9(E-Jcto~5s;
zjsv}ff~lpdW|Us=y%P;{rP;GDIB(V<I?+#v9FycVP=-e2;ajR&U@SP=Ok-pa?6LM>
zAH*G<iP3j&EG9~8>F7XHIw*>5oOMldmN;oS1=upUp@on@naPvXKv!BJchblhcqM^I
z@Pk4wB>~v)keYDnWQu5t@I|9l4r8fw8-cX?f$7L*FP27`RLVsVaa76z(hp6%?(s5X
ze3688aOuWq$Xa@=21<JU@*eBe4d$I*+o{!O71a6J-_US0cQKH&#46^aIJ(YTNQ#I|
z((ByXtqcOC8w?uE7#T;$mrwU0wWnwKzEM&+k2xyizu^3$YNY35RDQ%$pp(THaFFc0
zSc@jx^|Wb~k+jMf67f)s!c8Zh(Nk=O41*e&IECf9lGzX;*56#t9U286=3VWV<l{>6
zq8*RE=AC2_$B~Psk5Xqx14k>PnnsHQEA8o9LH$ae69t9RPd!F9Ckn`qM}@(~Z0=rT
z^G)2~%LeX|Ggl$xDS4IVh^y&qvN{?!SXqTrw6cl2qIgg|LAUT#V&dxjXl6(C_>lgY
z<dDf#6|A?IhVQ#u?qm4DC7L`IQpl54P)4zYQ$v|)Fcw>X{_fM0Vp^?T3mh7X?$WU^
zNa}WOz8pU2_%Y?qiFf9(U>oD9Mekr$LlSV|4Z0>7lzmsjYbxE0Rb{%<C6jM^NcI$-
zUdsltwR-XjG{@3uQ#A=_6R7zLw<5ZXeoa~>l6MlilJNKR2P8A;U&ss1Z14ANJPO?}
zyvLTs&B~<c11`Pj1;%|rIvjVJzKx!BLe;`GSV&DZJ0%Rg=@zsxfEd-2A=3k4mYrVT
zQe`GHO+}@vA$XMN)+Jil<M6jm$ok1kL_NweC&!CGV0J#ohAyw&_U2k5_~WS>mibWV
z!hl{ECZ*Qx%nkH~Ib==yxZTv9T81>Ol=2muwz&P+%-!qSC(himPT@y@YwSQ2h0JSK
zHUw5DQg-+{k8mF^?bnDWr9&Oi9ST~*M`e%6Q=C68XK}Oa8g&#|v31t2VR>>Vb*OE6
z=NBaXQhz+}PL2^xt8><{W3%l+jH(nMS@S0^BUuR8OLm438+vr7K3=sl%PeS+*PfM0
zBgqCSgl3=oiEHwis1IYuzZSi<kvQrF(YK%V5vj0c;<HAIcPbi4-;sC`I{5UZ!1IN=
z8aD1ZSH%ZxpRH&e|BQ~Y$K~>%sq4MwTk;&^-T!MLp5d#)&Krgtd?C}!4xEz%VmPub
z{VOZwG|_fjSlO()GYD}*b)&1N@r1EluV<oJjj11>cGD~DIc{GWMGc9-m!7Tq+6r?N
zY<+O+8)@1`dFhj>d1eC9v}oQxH2IWQn2+o=|BY_X?V$in6!d{3i*ID{oGy&Z$>{`B
z3BP@OAzPcx7yFf~pjqr{*j2j9`zT&Q@1Q-Nr`DV7ag20by1z%TQl<>gy>J_2Un18b
zOpNRy5v!zUz6_}_!w@cS+86z7EC|A#kJT0OEAP21mYB06LEJYpIpt!@A3%>eSfg>9
zq-R30`*$4nF#9sTUF^)stK|Fxy@%}Pz4KH{NG1KU(IoZHg4{v!n`YbUid$ok%lt(V
z1&eI#9T}?E`A-s-QDdyLf0Q9G7$_})xc@}ksy2d(!x;K)fK;(Od`PT*IqllNKTG{m
z{lfc$vcu?xZ_m&7QXZB+M(`!sPdWie_1#aspnS4|TsI{NE_7|EpPCx-O1{|3_a>^s
zhb{z}?T~bBU4Q>U+(L^=JkXU!Q7S!;oP{yc0~`XIC-tSmo9z6>OTt(#UBiEl9Y-kG
zVKK5rW1~6CH<=eevA#>C2rFO)g6aEpeK_f>WmlS1wX9R|^7T2m85eOl8&XJ>$AcX=
z-7X2JMp&L^MzC~Hn%*%fTr<0>pa*<8qu8>ranU9)kBU)yX1zTN6b7YZ;|;;XDlXK{
z^xY|4Bk&?jInz;osO|JuK#}~Cdg1=G>o1=a?h0i$!)n9{1nIFmuCi3?Fq?>XrZ3+b
zZ3+e5<Bx?q2RhVao3$J0zINcu?-OmalX92-UADPtUgNn6Ovr?^#^8%b7&{M^Hh9pT
z(`MS!if!0U9Uf2hzThF{5h5qOAz~=1ZNRhIIpeThh9saFqZp!M+_J*hTH(MR@78DR
zk+*nCa)lR}NyJ}mxLW3B1(i**xSw!XZ#T>GwCw(>JUkdVJcx)-|4*1#lZ`#S1MYmE
zBn>>eyQT9v_Jk5Hs3P~ft9ic~aQ=)pQp%p*hJIUhWC*aQ3#exFzb^&SMPda|Tw;7A
zA0W-?nRy^C&hEPq6lJ#8sTD$DM>qD~nXqy`huGSRv-=g|U<Oy7-4So-pg(IT(8!r%
zEysLVx^Q0&F=VTWwXhUx@9JCoEiGU(e7&|)P}uz@R=YfF|HOxZxk&eDXt2qop>>sB
zxn)n&_jn6cR)SWt$r~l6wO1>+!kjqYjKY>r0w}*X*#d#lD>3XkM1ytsu9m)M!96dw
zOi6YoRVU`lgilz>3E4Ji7wnQCL7b<=UeEgm>6*`saOH#mx10SCJc9V(@3>E3N?FCo
zBUd2>e+3~=JDmO)v<XQK+eh`Lut9P%Z=v-D##*O!82u&STuPzjBRDo{tLypuDnTAm
zao4QuxZXM^J+tVa(>>WgJAjkuap3e7_g`+-_z5Eb`W*_vWq731QDlX$aQx&Lg#e!;
zBDHj=RUTtE$^kD=KW59R@P*U)p5Bd~xq8|~p^<{Gj0LS;r+2Q4n{a}7|B5(vtArDV
zC^Ov`3Lz7|f5iL{uzcNF_vAx(o27Ycs;8W`X7tSKqm~-%Tm$S_eWhFc?EawKO#-fL
zwn9$m@Z&!|YCtC>|CnzaueO%EO7oWh@e;yc(Qfk?P7g~Zq#&i~`BZ>U`E&CT$VdRe
zX2%NanKb{IDR-%$benOegz9`c;)Bi4Y<7HAT;AZhOb~DTvH!#{ZF;e<3Jf*_7-Fja
zLvS0~%FyRiz`-Rk5vcg&w~rjb2zU9S9BW5Uy6oaYO3MjyDWs}RJ>V16G?p)bZvDjI
zdz}GN=#2r_m=vrhWN<=SD*QYm{uc=IF?B2|w{f<ydmoV9cnWEWC2|Fx-CDhwHig?(
zHy>l&Y4i>KRG>|Ocd~WD)Qgbs8L$pYq(EcSp2z&V0fXWGa&R}@Mms#_*lg%**f()a
z^Gq*{u3(D!ksaRc57yL%B6v-TFQ(WFykqzv@8N>vjuaI4mtD(B2*xV1u)$UhAFU!~
zx7tUpN6Zq;{`E>MwI?+Eo34^r(^phOef->fAs{PGa_?D=fDft>f9B)qxgXF!@G)e^
zcOv=-IRM}P1`qxDM(Y*!-B6i)S)CwWf5Y;2r01FRf^@f~mPFn_AeKg6pe2GO2O+|W
z<F1#{0)ohN07TVI5eWyGiYpM88=@Qs3A}AJVuFEc1Yidq5c~cPG5dZH<75Fby>}8L
zB4H9IeOBVtiy@UlX&oo|bC39q9bv<Y?;a2@z5=C>wgUp;wb4q@#0kg@?3Z7R^I~<u
zN4+&-fd7yM8W#5-Sw+8ZhL-nC#>HvPlef-;e3Q=N5~3}Ct&a{O&<E`*_(oSEtIn0i
zXgrk#Rd^wkU|9Y7;i0$7KGRXiv<BRh3e_08S<O<kMD>dQ-fqbqJyB<e6!65z8r*js
zkQ4wJmE48t=oOXx)LT0kg%%&I-Qpi&{FNhkJa}IBYzyIdA7x3ihDlBpHrcC+fTsCu
zsZ>8C{@Yc*GrfJvGX$5$A8UZ6!qqtg7YAlpR!`V0A(qoJd^_8h7Y>}n!#s4~nDj1t
zdI6)`1?my9k#JGWXHi+$U+)JXkEjaMQB3ZJ8w<u3EpvNCJQyNVwSF13^ufb(C+~Ug
zK#K`4kd3Z921@P7p@85mi8M~FzHEkzPW!cej;C`&g_9BEB8^9_X0e$Q5C@d6O-~gS
zYDkbGPgXy11*Y>Zz)}W}XJOxhIPWD{^V*^sqf@+HZb!GhJwZ8A$Ni`h&<+3&gZXEO
zY0V>2ejI)YMP4IYrYaoDXRZnyQ^eYvg?B2Pd&8%PG^T`HfP@2tRRx~J2wF1+!l%MH
zn<s*^n9vVkC@Mzo4}rLR?cgUFY93oc{<ttvPWXc7&;Zm}5jxKU5}eH&0ywR&e9K@A
za)x*;0bCnSYylSRBrHjSVDL@?gz5JJf>L1Ktx$#-)M|t?kE*W|RX@%iB;JSmj@Jq5
zD<O}yp<Vccq0c@tQtKT|Kup7pRVp1WRYXCyuN`H-v_b%2P9E-L=*WX4*Wo}{^dE`O
z#ZqE#(X64r^P|JoOz^L#a>P+z=Xi3<cW>jzF;9Vun8qbLKNACD{;p*f2#<wn2iv`f
zJ512jl<aP1e`80Yad(tfuU`<P)DeNwS3!s>l=5F$>t+L;Ww*{PJi5RlwWm^S*2njC
zARX?QAj{uS!bya18l^%uj@0Twk22IXD(s6>4xgHCjg<$?<S=Uy%RjE;p<_F8(~dN{
zm;qL_xqA=~aL$TCo`3P$ju-|+Ekb{=e;^9x)O?RC0Kv%jgLr+JS0$v-EU8xIGd3sA
zWPQzdB^BEhQP#8~Xn<9Mh`o^cQ#Py#8^#s=3^o$Vsm5WC*j4*UDacgXIGd<l?4;4|
z;{QrIYTI-j%o~5(J-wei6@<lzoL1~_tJ<g?V5O(^Eb1w`vvlPTKF0hw7@uLK6Sv(m
z4VGqJwvirB`Zd9zdF!lF9KRr@_x@2T>boV9d+J?Qy!*1tk9b>7LKf#ynl-u@+g9Vi
zt`-@&gHEC$=%`cT4F=bSv41*34Qls;-EL^iYL_W+&UYNhFDtqF^7xmmJlxB=E!OE7
zPK~QXnG$B}JdV#3HZ@&ueQ{QLp6?BU3)pJ&WY3Z8lJ-a)B=!Ah&Kq9V==BXmMt5cF
zB>ETl<K-h;@MVv`z8zY_8`s9HL99pZTWjwCnI&JbtM_~>b@sj4^=#c|)P&3E#~>^r
zZB?m+_LTRvXg?Tw8}ZHneBk$ym;fQa0JN#npbjmhLD}-o)OMxQk2Jbvya=q70dz1)
zJ}WzJuDC-qK%}s=?2)Sx{Bv59(~G6o@bPI*1?w2LiR`6QXG3K8LPyzwtS=!rkj__Q
z*dVagEbc|I8^txy5p^I^YA(&T2ZfSq{poF-D_U_70UYk^2gf~sUURVYWu2R!QSf*E
zXI2QC%T!T12^H<>ly9uLlDmPhlDx*$3<k!C<6vaiYCJFD?mREfFvWji8U_!rz!5xD
zqoS#OAlw+vf%tUSAP6z>g@HT8O>)OAn){R#Y}$`-Blja<C)aY8U~Q8b)*83-U;o{%
zL9`3kYA=gGdjmk{gb6g1%~YQ4MEYE0QMR`Fk0b9JOZ1V7DAEfbKYlMZ9xHLLw|4%N
z!zyP6iah!{g^FI~@ronxp<2fMo?@%_KVuhabssZgt=N@YBF;m*1l>yA)H|#NtF!#J
z-urr`AFZ?=T_^0Lo@JdrQnP&N<wr9h|AU$sSLzp16Ylf^!SsS7<9@NBpA6yw|0~}y
zj#Tb8h<MTqEY}lqWM^+fPxPX54c)$4eSbB#>PF|9E7NL6f6OQ$ji<R%dmGGtb;^^S
zWhGDe>avK~79#pJuB9ULZ%z98t3SyP-8C5Rx-?Tg_W#s6e8A|jMRO{V;FNw}>A7E5
z6)IL18fv>U;s0q<F!CaQFR!Qwd8Y)V%%MDk2Yh$T_bz!d+SweQ3#r^9zTh%|>|fN&
z!sje+Rh<ph6ADX}kKGx)4xnIq5@X7hEM9S%DL{sX0P+I*m2KU<7NJl8s}Qp}kS$xE
zq*8l4uW4pR-y&c5q73YmRt_HYwkjFc6BHU}UyM3;29){4u8piA{hQp&^q41*eoOxQ
zMR1OU5loCtx;Nz=O6tx-pxEvq3KP5%pDlLM(1tTCcwg}MrB+>wu7D@KyG-H775tIj
z!>-;#aOuJJ(I_HgVz%oy$Qrdjqpxj$Au;}rCs~_Q%X|xSQlra9kp~Ab-g47U7t&1I
zcsxb7!*g6q|4yUh+VhpC{kyH&|5x(gqK^<JVEfpDF*dhf89x-u%pYqen3q@l=Za#r
zVCcLy27DgJX=uFS62{s*4Fkf#z0^%9hBAV3G(szRq?!OWi$fPfMBaZB+C$DXBB6pM
zv_LO|bm_lT+<CvWmKK_fgXxc=uqe^1cboPx;bS<edN;U^3K)9zI`5KXvhw*Bd>Nlt
zYMP>;cviS;#+E(E1qSeO1qbmyln9ibj%)0Jl9L2&<n4-=8%XD502^GFoBAAUQ^^OT
z<GuI`8D8yAk2)^rmv;Vs!l&!hX6Ja2?;3V#_&)cIbDVEo<N^Nkwn>~<obPW^z`69n
ze_Ow*N24RU@xFtGYdBAV<$p^?M+kWpWkUs+K=SqRH=qa>AhMjF>YZu4-0S66)i?cE
z@|j_U@-0ZWk^e)vhyDPZsEGUr2~qa?^%@GypB`eU21(>9#9+I1;|zxFoJs6@n1%}2
zU;Ut}D4}%r80APeO5!dNDtyN)BajpLoKML1`WtB1nlC1;K1Ob&#DJx&daak_vmOh{
z25|c6<#iu`_v<BqgQ1ocuhrA{dydgz8`SFc>pVzYwo|;K+$yPErp-U{inrnpS2}uE
zspqp11ghA4Tj7HsUcDq4OXMA0plgl#JxtRLu58VFn!XrcI^sQrEGDj+Q2Aa{gJy#t
z*OycDlN#ex@T}4@r8_#s_^jejR_?wvmiWvj|5M}fzi*M$NtCF@qWtn8p30Q0JS1W9
zwEehfoyV5_j?sjT=_Y|U&o%)$nA5EC8dSJ*EBxOGbJgn<;&aH7(MToQy)T|%c&D1$
z&GmiN>Voc*g~P%Nin{3=NJ(bei|Ud$bP;Zay1!J4(RJsuBZybrd80!&YV396N@-H5
zmgDxR_{Wt0n@5edlXMrhRs**do;*IywK#h`8zT_evl#QM#><SsXkP3VZ#Ymh6G~&#
zt6i^<!qY4AzsHBAhi<TFsUDBC?x@+6;X!fcFQr8fhM!ASevdG=)lN!9nTs<OiZ-KR
zBU(d6h_tXVIFLbZ?D0+?I>#HeA#Ek4)<EW_iPc@K9Ocn&2)|StDTccxPC?el-F)F5
zT0DENdDHfY20S-x1;Aa3WEAkX9wM*ZnzhONu!xEvT~l`B^rbMfykQEAI@<2*&MbYj
z$9oDG9DyOw;Z=fZfBHS9&cnpqOO$MKhtD?>p-dRZ<g1tUkk=1Gv35%x)`1&m$u7@}
zKeTNrNMs%5{=WA1M8n@4zLxcu0HGuu#_X>DQ-BX&J?Yjk;wmsCVMaTI?g{q~w66|S
zc)0ixyBYK>f|Q_Q;CU-?ScYJ1NdPHv$>XmWO++EN6V$waQUoxy?<_qnFUE7%%l=sq
zgBI9DlvpZ{gqm(&SeJUy%l`CcL?IL26SPJ&o5-|lbb}yOD$2QZAmH(YxNjL+DjH+V
zNoS%#bY%uXyn+4Y9UL|*?u8K}{u%|?hyWA@tWP~Y;U_;fUiVV(ZM$RHr()!c+Y-zo
z<Xn3u^j8r3jaVZ`ZyS$o++CP-uz2Sdka>-INtcnu1VZf~Bn#tcbG@V!m02k60shUJ
zec0pt%?%F9E|Pnq!Ec1c7nngxS4V|kHN(3b(9TDU02T_e1zVPHAzQGrH$R!=$J+j0
zbCFE|V(k$(mO0%qVL_+^6oYzqo5MOx;v}onVOPSFF>-minjD{#;oB|M=>n~e6#?M;
zQo~VAJ3!~>#yZBx&O}1yP(l$W4vJ?NAN<|1daDN(JVgseRxyPt+!y7*VNy1KPZU_Q
zI}8PA7{^F2U|?aX5f&W#jFC;Wg<n9ZlOM@-80D=LisznxWRkh`2>p_m6B!px5LO37
z?In7scs=Y{tYu>GdzlHWd0e9Ljw}M3fl9c=>cBypBzEny{`KUra!n#t)op~}TY4tX
zsiGl8r?JV>J>rO%eXQixo3@hh)WN<%GkJ_E0++(D<-cQb7*hct-cAFEK6cmhuyuZ_
z76}n4FX-(bB{az+I5P@j#2z4WUm4ZFiZ0q;78i4pBm-qaQTQ`nC?!*RCL&7uDV79G
zGVU04XrBVr_L{aJ2O8(KOhub*`0GPZgp6WSUP^)aUKN)52OFjkKFWpi%y5`V9Ra#4
zzVc`cf66k5P#{9R;TXps5biQZwG9m9gNGQ*lQfMoi|O9s<jv~%)X%Zt4NtkJyp@B+
zGT;`~$RzVQkQu`}V|Zfogc>@Rf-(plY<Ey#-eLdp&I@35KZW?l;d2AM2T(vOb%U4e
z1hMLmq*<~Bv=Fjo+;NjVC;_Q`MjHM=z#8aGaiZ1n=WeoyG%%1DKu=f;(KaTfPlJ@T
z9J(>Z{O{RWnfmT*;qvfD?MPPOh+6d$2@1b8rj(=cg_6GTG+#)zGDk%ZS~xWTKB>WS
z4;%trj5sbZj4Ut??8gbIGT9iPFQ^Z|s#iPu5k}H{vc`A%Uvs4JI9Bh(q9d5Nw^a<Y
zQp_^{Qnr~$vk@Ri02jcO4vb1C%(cx9SiT>{zbGbKGkt9qlUBwia{$?c^N<Pkj8Q!(
z^Tb`nyE=0OvE`*NiM}&sFF0$&@r;$n|AHYPcI+kKdoaoCFmmE#jPptb)sSz6Gx**|
z!eS(kp%A_!u)VF{U}E!Y&&S&=>ghgj*f?(<6A@>~9DV2AZJm-xu0t9JIJM{ivl2@>
zsKQ1d$rpkXx-|e4DD-8MxMoN;HD!^U-m${vbNi{?wm>B)FQ@^5+DEq+p%)SayTun9
zzBT#W2<PCAV;8SvSRZ4igfxcOC`BSelL)s1K7kU5$^U823&1;PF<~Lt%ZbSPu9bFw
z&@PLGaq$KI%|QhuitC~|qDu18`_Z4{SV9ei#G7DvD!zMQ$jPW7f%n2EqB}>wNw#hF
ztM1&yrL)BkPc!8RSoIw^(QcZC1`qt0%H!8&ZNut!ygi|#nFhG>@mTFY7@=n(R3v56
zS)^l<XY?ey*nwRbo0qf`Y%Ex^JhGzn)ggs0AA;96KNA&BVJb9x`O_Xf=J(#R_&;Db
zO<4ko`fT+Bo>Y~wPIeGkl2tF4`I@$OOi;<0>8a|+i%vp3Ge%iFXN3^Q;Q_BSB(X2k
z-}~_*A#L&ak}6mVcqG4m<QViAWW~JzTkxfe0+!QtRWiDkkL^;T)RtVz0-~sNsx+XB
z72}B!2sRi3YIx6-DYfLuNvfy22M6W(1R|iLl<ve;i*V>Z;1l&ZUdJWhz~2(0b>P_0
zmRKEN%*})$yHut8N&UMDLu=I`OsR0pqJ$&-;Vy*kJU4b=7O698g+StIa8>Ld2zOGJ
zodae?fVKf=YLZU4eb)0-Fl~^XqLASOEIH(OmD2qih#35MHP5N0&AGVv<o7wG5Nrc%
zkcKj1W3ma&VP3dt7DNMV^!b$tNrNpsOKxVkd<v7V4&(r<ZNW8&8m}k+!&BfJ4cl|&
z?Q|m=6{Mxbo;*_{h$Caw7k$#M2hqZy2iC#>ZgjFrk|@8v2#B8Q_dQDzk574(GGF-r
zyA;CX%UzXZK2Ze2l@C4{@O+6?C46Ib{+Ynn$U>X73vz;X<716q7)|P#8XoY%kP5W$
z5f7a>JFBdmpde6``%qg=5`QjJiNs6SoEjc^$*Qg{6&G`fDW1_=bQCZMcye-;`oMRq
zUTm<z-Cl!5iz!H3X9-Kvz_&SDh-yz+H53!oaLAjDs;8^0xfmhS^P{Kk!r~)UvCk9F
z2suD9Y(-dKsbX!?n&gjDRE$=1Q6K$-@msT7=l2nwK8MVJPG{TsU|B<iRoV}O=ASVk
z)VA%lMg?-<Qvl2kPL(HwWGT}eY(@b0;2(awJ}*xcIOJR-IB*Jsz+rxzN%Zr@hkoI^
zrhoP?Zb{b07t5;?2zhUDQXyaVWopaf|Cvqoek66K`>f>&e6-*#YV`zNUCl@$e_Zmr
zWmWvHJ;`^cb&~msPKYWJqe9W9(&3r}Q;rWU<@}2?#J7y0!ODKJoS+K+hhsDR59qW0
zL*0x1Ltw}CO|{3)0d1#}u1+pz8Je~24bs0qjxxe?OG5-5qFX5)Mb+}WZV^4y2hzHL
zmh?t~M}24kN5)29lE?j$bBhx~gcy;ha2}TkwNHb0X%_5o!Fo`467<{Kx}drEO;Nx{
zbmIch?%`uK@9lwB+ISG-gVe|DZ@_{@qTsKO55RpM;B3G5vkbEE+efFeBBK#rz$bD5
z%&$9X5i(z)eNv$76H35AI$u=kKnjZ+o~F16pgfc?1ogTr{^R#6I9qlo)AhWod72^p
zj66rrP*Ht`<%z!?)``KU(y>a9a=yqI(!sIbVm83lt>!en(oJH=b7_z&yAl8%+-vsy
z*!%ftjkK=A%7ri{Ak%fsz86?~$zyeQTqTg90SGZ#$_r1n;v4#fqiD!r@hkX)3gvrP
zgA9x(Hw3rz@sOcSl46dC{=o`1{~s$XJu?0{r_7=6LlY!@6P1|JcheYF{6-*2<tGF?
z{gdIRLT;KV_J3_}{cx>JE8M=R5APPBS54cV-X|gD{aw>k%AJgd=gQq9$0c6@zus$i
zCBibnH&egQ4GdUcx^=<n#t~p+e2E|<#r!sL<cs1q<h|uQrV1dYs0j0)kU;Yd0T0lM
zR=8YBX)}JC4rj`!>I;t|d=r2n3(L?WE1`>QUwDKUI}DMoYVe(bSA(+&>c4mCQ!+4^
zARjNSjVavsHcuhrZ_WfXDPlv9-j9Q=UY~Rk<ooq-3DsyqjdJh`6~5XNif0O|=WFA$
zE(699$A5?A2ffsZZ0}K!il%B`<3YhsNzXrnG+oV>e)-)n-%-A)zL9+T+mMfyaqct_
zQq$fazTO0$lyh#SLr<!9KlkwY_MggooG7zs9_3ckgt=d?R=8*%<??%~oXNYLC^zal
z7D!e~x!yZFpFXfXxe~^{Fs^f|7*Ot*VRa}h(Lb}gkSYFKa(&+c97sA|^PfZ8e{$pZ
zWH=T7w!)oTmgu(MlA&`;DcH1bh+a$jbMjc}*X(x<ydn)Klm83_K1RHLFL<m1Vz<Oh
zAfk_%eJ%5joUG->bktPX5m?R(PQ({J)8Pr)TF-e(TotiI0p#AXHAuK!mhb7ntxL|h
z^;hTV(AzuQN;`BV2~W~R%@&p(nZ}}sJ~w6;;v_zRoiFR{l_&b|7u)*(1b?!3SH8aD
z-Sx#E&c9>2oz}MJ7M(Rq$g5nEscK+?Ew|Ww0VU1e3`z6@OKwwL;%UpuIfD-*Q^U0x
zkH@m>;SuKQ%ZW9c<vcdh+Y?eH)?R2Q0CCqZo`vSi`Go!{a=qDp0<?`DZ95{ExIVjP
z^iK(%SM<7Wj@^!|9cr!^%f{O1W-TqmuCkQpI^4$1-BXGk)H>U6ft8SU=cDO5Yp*G4
zuYS`3=K5S#ojJPn$L|`~7o@?ez6gBM8>@52G;A`*PIl70mehTz;z$a}9_vltH=ILe
zwxC0vF=RHHShyMkuPN;y{E!c!AXa2$!W>Xh%h9`I(qY=0DdssbQg2sB-AKI*@?LL|
z-a4x&{Z3%jP}KpZARM<ChD`cH#~xggsah9vJMc9U19z0P{fw*P<WKH?#?wICUgTNe
zI`LT`x}iFo6<pUwBEERbxz9~y3?9JQk@VPbTAtzC3BtrKZLSA&4mJ0T$8lf_Lwn8;
z>zMAipixtTLIl>jKC&z21tcb69le#>3lIUC{Z_%9?@7PqcZU2BWh4ehc1nAm5;b4`
zk0Gqx`rjVZ{=^>)#;CrdjSlK`w<q)Z)88Msa6HfJe+K35NeAxsJej}I)wRuprWK9Y
zH`yV3RctUfGyXH#Y6;A=mtP9hytHiA?5gytpQJ7#&W{iZ??$@&+6g8tcgC?DjtO!Y
zPeu$Jg0-ETmVUo%RINMrz*mAJ7HP3PMw}B_q$d?_@F4DMUodrj*Y4eU5Sc{x5P$?(
zL~}SqLE5l2@LDi`8HQOg>|0I3aAxa?B>u#Z=!q+6uYOa$C)Y8BWc3)33t@8EM@qn(
zs$(axYrrCGaMhC^cV-iIMKgnIZ+=j5YSU^_CG9^AqvMUORWlNN*ypHSE}fksP*9l_
z#9mc8);@ANG{WIWma0(r>K@@}9L0XkwT#~mj}|#n_Q#uck33Trcda_v(%(fl*@3=_
zQ3DVOTM@n#PHb|L*IYo=hY!hy)FhQk%}9}TtKh;0o3hYx)k==;1g@%%q5-C31<<HX
zK}{=DS8vg9q=UeY7m$P`ufLh?7Y*ygI?+;6z>8J1$u`c7?HMN+>r#(t)svR+UIw>7
zVfJulwXaLn7Ek3{gEWPkgV#5mQ^)lZVKtXz7n&B$MvI~sz>H_Bl46@VV&kyP1-7}J
zr9IgB9jwNQyj#6(SJ!;8VP^nF=4$S&a^P(AUJa?}vXqQ+rbm-*9eqnQbo8RE+19{#
z_4V&!+DIq$jz%^}TOFJytwOT#G009$GcRa{epi0UTMY>wWgKR1?KyLVC6}bfrnEzy
zyJa@*sML6iQca;LjNCC6MH(5MhZ-Np{)Ay9`5jy*cfCpXw~e_oZ7->y`h2=r9FE+T
zR3gTp$Pl-8h2)qGSAA?&kVdmmJlEss$tlf+E6CIXdW{&H&;@Y}XvzQrgU<oQd(Ir{
z3aNF#<6pSxhUpR&3lUpbUxxqr)@eWTU308iWmHRX=q_eqK3z`qCF^!t!<>T^W7&;;
z>93LOSQnVy-+q1c4SR&y&Smr~W9vJY$2I#k^&GC1nGX$bY<zILG5MK`!CuxZ_hUru
zpDf6Io;G`^$yfHi&~gH02%*lR+0`}RqCzbl6o;t(Zq4A=x<5S<rAy2^0>$OKaN)UJ
zdo>EPv2b4ofg=`U^T)`je?v^qN41*)TP^2<#$YgnADj<Sz*ptb<&9=AJJ`y2F?&l1
zg^$-FZKl(@vMl@Ruj9>R2}Hl4F{u?8nRD4eZOuZKX2X*ifMKYRr=vx*%Z`0jvMID<
zo}j3d$kHNr{CDmTd<==z85{@y#csA(Z!=r69Hv`>Gvh<f-14X&irrK`HQY4-#9IOp
zZM;a!(J3M8t`d)sE04&QyNR(@-<6p$)&z+DYj*RdKg;_*2YKjT-wlTAysywQaodDH
zwv^I*I-0m1#%NiS04yo1zPz|_f#5aD(&5Q{>Y%|wjMfA1SaDQrf<Zv-R3$5Hr^!Va
zPVVcMM*zPL^svR`&fd8B3RuHYe^iT@>iwW&o1J(b88g>sFnGY1e>i3h+m8zS)o%*V
zcb~Gi5A`JQcnH-?<8Kw>s$qDm^}(83Rr)<8z!`cm^oV3ed1ck$D4Sf&sZ$4wtF3!c
zIHQgu)3u6qV@#E6Qlz(W!CAIBEx@Gu2$Dvf#W?HaJDO<Ht(68($+{hTOnTrDFRvb%
zC+Z^?<Wvsby37qrE+skRPCGwt=9vZI&#X07eAw89?%9TDng<7Qn=3Y)d$XcFSa}*R
zex>woA0vs*U#5u9nmuS&)!J@b4V;?#yw&#TgB{+qV~?J9WYMr&x@R#XsBC>vdqjPT
zIC5I-CgBvyqy@8BJGkpQ6<Njox*NlYQs3pW&OAVGh{JRmJzAml8%A5Cux|+wLU`NJ
z1?3>aDD9APm$%mMc%_v-V^wrLX))M4L|BRADX0Ab)7|sdzy)YoT%6o}xU>Q`jIawE
z-)8{-u51w$^m_l(u*yOjGA~V>Gnm+_Os)$sa;Ie9x;;Ftr&t$FV>mDIr(<P3K;b($
z*$TKy;xOkuFJx!Qb@nXS@|Y50%-~$?@S^&|w8f>x<&t}0=JVP7u12B7cK*Q)R*OYU
zuN=G^9bu}>jU*omQ{`Bgo79kmP@2&A9F@WiT>S%<GvYNsgZE>oz7c#uFBZLDahDbS
zHI`I7gFH;=;*^#s2P0V_RKR~lbss@^-G!eo$U!<!y493EbfFefdRP(HsO-x?Tx*6h
z{M)~TQT@Ylmo^JuFwQi%*7ffrC_o~asTu4IiepAdUBijt5Ddd1d#(29XE7c)ALErq
z3L{f{#Da74UG4g8ScaxkX|D08uf!;J?IHzduNym4`g0$X)wlML@}i%nqDy}f_0OkD
zKGyL>6S{iGwzO5Ex<%S%gBZ`O*>HIKdE%-DFjIZevOSu&%>y&q_hoB}2e<|s!^mg~
zW#aq+y_#KNQ&w+iD8tG=7qly=ny)!p=rifKoW8^<pwh^^Z;w%^F6#V9fFXdaZ$hw7
z+*PrHDouyjecuLb@3Dta`CtG&3pRz$IGR7%hl@?8F7q_=WtbWJ`3pfA+_Gwerm=qs
z`3?$S;;<|7MzcP8>7nUVL({i71QhH58ayrXDr{yfX>fv>2BC72Iz%qAbck>1@tq!M
zJj3#O1g$a9=|BTIjZkT?PlC0G!v59xty7H{vB)nGw{KVBs?K@lP>H!ScvGW|i6&UY
zDHXmBUnD<TJL%9keB!hH1IG{@-Q`YVrnlLTHJFdT4Dmxoro@IFQdz$&KXCL&U(3AU
z({$M}jZQr@P-of6(0R$6Gek~;H3=qs9)P^`q;lHvv`9ui!vroJ7HCgP{*=}j=eUUs
zvR4eTZusv*<HrB!&oj|8H{OIQ*Eera(V|yw2nbff0M2Cdsp{9^1a4lPqvz&~TXc+~
z%R7T}1i0cCS`)*|P6>oHn7CP+!^#q{ClsDTG1CbsY7CXhQQPFm=I9U}_y$4G9(=yr
z^8Dmr93=1R$@X&?_=a&)ZZFLGAyEukfkW3sn)7rMEhXE^=&v(o-sM0!xsG^D!LsWG
z!VPI}P5mykqrP2Z*&FBlUuvB8)EN>=o>O<$*vOLPl|)!%oO~iuMb-&-+_i<=?IR6|
ztbCB#O+k~4E<fiTecA80eiQoOk);Rb;Mt`{1(QrGyZBeXE|~s`nwj&bokjtWDt~hA
zfrqyxE7b|zCz}ymi`jDH0>2OChp10PXgjOT%U_j-M|e_!n$2Enhf4@V2a=}`)F}UC
zQKgCt;76oJ!tDAJS$BFqB>J-FE(*);MiKnw{URj9^gyl5ABU3YzGm0I-NGi<lVU5E
z>oHj1!=dL_l`FH=D73Fm>gvu(^dHmBZYOHrWL;XHXb&``*-nSu^%K`L0k!+tx^h{m
zo1W^FgDp^@D%7ihyZJ902_#trpNBAn#zD{ELM^B^^1GTD3FYg^<>%_rVRHDKL`bEf
zn;mh*9q!-}S4H!0YTYv(8)c_idGeK(gbm3B;5kZ3Dc@lJCqgoIu<R#vZ;nT>R3<a7
zm*0;6*(}&UOSH-y7&zc`;KP&?wl}-A#V(-Fh8Fty@ZmS*184INvcgCp_xTUI#Q7g~
zX-}J}%<uogOP=O{%{C<;97Wq%)oW}kNsNah(SR(02CLQc|43gJ0EpK<J9mr|M>Zd9
zU}!{bE19_eKf82uDlGvDe%y%(?&RfGH>ST`a&aVm<p4SE<?Hj>-16y#u}2YZe5hWZ
zi$XL0WU~X<H(jvA3hOQscMcR-C4%Sc5_tK9=oZQ<ki<iWiep59w+X}#3rg6wE$PHK
z2s=V<oZ>=^V2?t!vA5kZt7BQOS1Q2AvL)t^WmP&I?vhZPq|XcP)!<O}F8UAop}s=w
zw?fEs{ZfB&T(e?{2b<XydFw;gD?v;D6B`i4s345AtC+Zz)Iw2|4_OW@$YOMvF|g?y
z1(^I`3gGzhD4Ng{6w9rtL7L=Xp>98EAn{&$;>ngfy#O?2ng}|J&tu#z;Qp_wO&<$^
z5oUl9|LwMR9}~_@JXKHAozKHLPagl3BCaVua=mAqMMI%blzMXLh)Twl0AziAWIUFP
zeEFxDm3LJ2UyfS83?p1YkFb73eBqH%${tj?rzdk}TyI2((IJ#7--jjl(x6M8L)oO<
zj{s_4mqihTH)*!p;j<>nE*uF)__#@iCUQ5Q-?cxcfNw<9aUQ$`)0Et!Ze)lLf7~RE
zn?f#PpeMtkCjwfpoy+(6;r2Zj6DHyq^nv_uJH3-IPy?URADCta3=OR<gA#AG4J&B6
z<1`(POljvvr~i{6&CmjH(?nb{8rVs|EB~u6V?(f5D%-ZN0a%<-?#tD|?VW<x9M5Dm
zT5^y7xjz&ZMK#^s6Jxdvq5SmW%7rW7fu?W86sRZ^K8`^vCWsaO0rk;{{uF|nH=pmG
z;62X-2LZfeBSh+|LlG;reP^HLqbU02`P3J5^-USM)a<XY@l=uAZz&w5f|CxX@MioH
z5(J`xJqQst1W90gxgdADH&_0p|3iQbh>pjVWJv<kf7L8Q9E{R8S8)AXS@<j|p)#Ss
z?j|KL3-<_$201R4A!sH@lWoS>qpPgjQ;iH7Uj;{M8o7`_pCk?3Zho72@SD0l#H~mI
zH>WQ?@Cb7D=>H{&#K2nl;Oh5NW7Iq+eo|Q-q<^4TB4>oXfmc4D(S({m<hVAU^M)1q
zfoA@Y+wMJb9@;=tjSW>vr|ay?)w@5>9a75lyMcf?H_hO87vylexvQ0knkf`!g6*cX
zb)c;n0e;I^L5*M*1@x=rx?utSRPQ$+f$lXp8y0mQe+*J8`?R0SvW3xw7ZV|wA+4wn
zI5x+8X#?@?SW=RZ#M{mi<Gw(LuIf!G3&~CE*403r#4L{d$n@(8yv{4jmce|-6W=)2
zUs?*r@Wv%Jd_IOd(C*cfN0;0;M&yr+XKn#HMs4Y!Y0<HbUjRy+v90$p`~yXh&c^uN
z-*HYxjm?R>Db4^aGFErHtHuC|eaesH*0YK1c))2M-qSh!+s_SX$o+M!?5ea3OrNPS
zFX7RzqN|UhB3$y)MOZ}Fa_fx(Tn=I4*y3e`;bw%{L7(#yhC$Bw3ooKYD0T!%{F{h}
z5ylvQ)&O2)#o&jp0djx5A5SfG`In^^KMcY6*QxgS@0svd!Rd4Py8Ge#aepS<uUZQY
ztJs1@%J(c2oA4_YXXgZq1fO$Jk$=|fF;?*69-aK7G@vBY-^G?EZ#xO|9ZW60@8m<A
zkl{qLN?w}qGXWkfa2~t8nV^cw=TNm~aX&e8teuc;kmG&+n$ldk9x-yk8lk201^$<K
z^k~u+T;WY^MVf!y9DG)})z7Rsa!O?1lZu*=>)`lC?5Qa1?u2naf|C;i%(5~EvS+MC
zL!G9ErdEh8h!~DcqnH+;d=_LOP^Z=E`B%(cJHoE``sDL1=kdDt?vNS7kdq5h3)TXO
ztSYv6d!4Q>RWw(w;w$inlQ&NNO{ymo94@|3rZ?d>s*wZN3n>8hwbWqn(GVlB5EMyl
z-i}tym)^qn!y^sxb!{%K^E^$5T>v^(Ez#pb)s&@Ix3KO|u$>~3yC^*qp)VT;AsBc*
z0%_z012`h87JA;L#)p8z%}mKke!jKW7?+=ue&_bd)Sn!PDVnCr(?^7Vx0io2N=Hj4
zt0P8CF7;6OEw!Jw%O^wQ8&_g|B|kP}<^gp<`;))!w~BOr8+x7!&&O(fE`!d_-su<(
zb(6)r&D8E$8@XKIp0P0t`VSs0MbX}0Q4tBV;(uD)5<DgFK&^y?Wp8UWeA+GW%)^<S
z9J}vXwoRo*>$ua|?ph5|M^ikV#vz$=Oy?1acRYr1U%?vX28N3eM*k%&s^hEJ|1d<;
zgkpSW6cGebtiO|>V+X#wLMNQI|Ex*C1<TEd{2AGjPTb&QX*0bj;==223Y`sFPq&aV
z4(0)z0FRwZ2?Xe_q%!*Sc>2Y}=3@Kp{hUdA+uAb)m3ct|xgiY)?CYLb`&#DnUf9UD
z(Lu@bd=X-?@38-&2tDajiM~IR;vh-WQ4ozY>&ueEaGk^E{zcPlh_JKNo%|m|IE4I)
z^pb|?9HZW#yZlCH`^RAu(CX}b^{s*&8?Uk1<7W5)zr^k4MW;Sujk~2=?7T(7enquy
zS)fIeZLdx|d}7I)fz9gGe}Es3F`e;U&u%eXWai*eFs&S1-gZ>@XQ%@MT(?It;8`R~
zK6|<V#A^Py)A>~HdA~)4KRweT38{^t#b(eD{*wmZVuwpqw%mjMeBkEhmw*AUSc$JM
zZvgB!;S$+{7|D7%(>>_`KA43(rq_Wr`v756<MZj<FEgEe&~2-e*b>{Ts5KkYq3BEl
z?Led<ET3WtSEgJwi1y*15_5pRzwkTC&JSq%7v_IM12U}wyM}vP*Yi<gNME$THM%DC
zs<QC+--Ch(02D7GPb9!7x|b%LVdm4U>LF_=k4H_)e=_7--<@2)sKR68({;Ut*n;>F
z{y)7&SCr0Wz}GBDWeCTq$dTsVh++k0=g0nWfvC3rP!4Y#L!62rHr3k%5-+q<>*(dN
zI+Da8z2?5%VMreKYpg=CJCH%F_7fjqxHr6zNd%c#h(Za~-#4{r!6lIt*J`$>rKGaN
ztSq$&V&cl?hss*9v_xOEBe3i<lvqOOWp_1?th+}BDn<>TRWZ+#zkP`ERaB4@ThU6T
z$P4sW_=IurStKcuo;&Mj?^;$t4KI`S$aij+(@M9qd+);BH!C#-z*tgEvxcrRzp?np
z0jl0&;ZI@GiwM#d2;8i_svW7d+|%sFKd4c9Y7AJ2H17uisq=!VS{zG{AI!754Z(eN
zO>Xy3`ZIjYFBI@}ZG7zSsvf}wTv8ku5T7bKO5|S@i`tuLqXw*I$=w<r$>8!+=2Sc;
znuGM=k^G<|O%eTBp72;zm_D<)?wrtgRgHB0r+R}<i`;bmU2>m?qOdyil5%%N(rG&Q
z-*pd4Tk1{f7tiF)ij*3L>LK0YQz!fx-O}UZ%_y)(1t=VfQkvM3y-K8itZD<78zIAN
zb}05v5{bst81YSWnGJqC1x5t%N1vk?y8B}dE_}8bDq<zFsFg8i6{Frv>lz7`#JZP6
z_mxLdE5uwTii~(*f|%9+BwQpLIh%`Ekj!*l3UZIRGX&oFycFqlT%vQ2y+_r2%II;k
z{NwqiW+vCwZ^9tYBJ94wy65%BgY`$mHC{<+eF;$O>?`C+byJJT)l4N+`_KNPsG^~s
zm>mwX9OKgQrTo(!K9+jla=1%{wM5$yjIiiltb00IG51@P)J!rgaWUM$Q8~llpzcEi
zxlnCsM_+f@tV)9Hxvjga#+A0%n%m`^AY>>(P?cQv)LWx?|6g2@7XN-(D~4c&$SDD=
z4`TR|fI}X70}~?`%VOLw9**LWcp;4Ttl7nS^^!^GIN>i{e-j7c;)vrnrB;H8Ml)H%
z;;J(H@=5?1ru?7kb}4sdyVkfEou3#}`5A|&)+Sq;?3n66=kXQ^Wy|}#`_#`0`y>hY
zSq*V?M#lubXdv6$>_)8(F4&*bF*a1>F=E1yXxO~`WFQl<ez&T7U6!p09p;O88|-=#
zAYFZ~<a+I9O<kpkX=Ny;OhQ?!+^Dr9?(AFTl&%h?X6nEGl!IpC`HBrg5qDFAN}F+e
z$#)Ud1Ml~O@!8)h5=;Tb*H17DK}_rkD{WR9n9`F;CGFwA4&CqDgkyG}Bj{EQmVvVf
z`UP#nzi2MltfPw^Crvc5=7|QEEhsDS?LAkq=tT_c7fBlBW3K&q=V|Ss8`PmWkJ@DX
z{482kD*h6<@JAaSzkM8}SFi+RFinCGqf9#H^Hsu%96OUpGjrh@gSZfJYG3&et3s<d
z92}SE)agmJ{`^At#j^23y(3EKGsS?0!g0q_R@Q~HEYn6;$VG&Hs!)3+nmTVVU@%ni
zP=sPov7U#9JU~V<cxJ0jsM6-n!A`v#l(#oCEGw@d{K`g9gEP7$_lS|JC-*K^*V}ej
z&QxnCr^bD(+7>6o6=lYg!mMA<!P+SSKisrPG4S$4;WiLF8cjU{uX|k(S7R!Jw88?Z
z%`%j$-rPfEA3;M+nc_8anzP{N!4CdUx&z7;W=gGUb5^o%2{RUxmB>INwAeWYU*mLi
z?_U9%yW#Ub{l60LrZ9>On=DPP4lmh8E3+#Mb9(c|f4_cSXd&TVSDdN%<d5&Ph!7se
zrkE3{a~NA+Gf~FbUBfMLcpNN~CB$#W6)IBOje{w<b#wT8mL<?=Q#-o3E5>M&Sf@p;
zC7o+a>OqRH{n^ab!2Z2(!<!o+7enH-jj|M%urPe*gAqr|=tO?L?8I7;D!Tk<#nY9~
zuZC?^Mqf<H{QD&Mw2XjDSD&pchG4^79}0!^6r+Jg_U>&YxcJ5Y;q9%0<NASjLDQHy
zW@ct)W@cuNIcCSq%#1NJGcz;WV`gT@jw#Na->rY$+N#}$-IskBol$?1POD4jjHGFO
zy?+(0{*(2B3Gn3J>W1W;{ynmKMLVB-(Kk%46h~%B^0G@W$%TeVw^)tvVBrN*Q!%NJ
zVE^$@yft*SO)84jz(|u`P9%*_L)btAck?lqOER6Qny|tlYYr$in!VAOz&QL8C9zQ$
zyGB=Rkx7PmsW?jTOv6yih8RMt7UW-H-%U;`{}f73C4;>a&8VNyCRRMPio4sZn6)`v
zQY}Y&*~OB#*W{*!(g!21M%dJ3wOv^zmZR}coKo}``~@H5wBVP^!S3RjR&OhPGkx*p
zN~L@Xy{i#RuX&vSHRhQ?iG058RLdv>Cc4&d@;?lWVA_`ROEU`YuXr*=zpX(RH)t)n
z#I}wmx!`mci(um#F3W!=AYZd$&#EIr&0$U%h1(7cA8A4y#doY)I=HEEsSc(<LrTSU
z-b)?(CG+D|v>u6YzZE7*s3Z!)U#CBKFUqov@#kgi5&UKH<!Q;(Ea#>*`hT`d8!cJM
z$5$7%6%QK7^h<BW_-Le;Y^<O=d!NMPF%O%T`NSIpSoo-~Ju9cN#f&2mF?GxV8#B%}
zkRzd7G|$mJYbUg52s$<v=mz73Yv|~Gf(@S^Tnbu!E)tp(zM!_w30rR}9I1gH^3ZE=
zRni?zJ&i3Iny%{WV?Je$gi%;o)pP_GyWImvZLJ|_Rdque1|5i0BrPuWnt)m?i3@tP
z>@)|kIW#Ss!8|L=5I*IcqBSAHC=SaqZ+AbarBuV)RR^!xh0@s?=4|3BDuwAXjrg@v
z#G`k~;;PigWTw^>`ts^Udx_>tqcxkFzbc%o%o=MT7VS~vb281<Xz=+rg<Ky)ZTHX}
z@SWuN>qE~S2h78&viKOAyf#2iOp1o$j)qfG)%Ia>Xa|Zydo7=rv7p;b<MhPAseR3Q
zd)n)v{$!>7bcj##k!?F6dPlC0N`m*M+s0A&({HZ4ph(&}qH=8>MJGrWbc0P4!-p0!
zti`0_@Toy_g2h9T>PLlQ!tPOy5x=k$mwap=9{kcE)eu}nh^+*N?SgNL<rWDP-(a=W
zHQ?;w1^bx7090gKZA#!xUfT2dMn{?KkjzF+8KB>fr9AX2tLmHGwKjHIt+3M2Pc|?E
zU4Q&N*H?$`TF|MhxV+GC;Fx~&w9^q`f__+(_Vwe|3(>g4coe<AegZb!)7H<r?%jiq
zXNy&){<w_on?9uGI8Q>yS`1y7S*N3;u%n(fVZ+`T_m56Tfn*A$E#>O=iHqw*y{<%M
zhBwgRTr(Y7KtJIaCN__=?8l7`6Yf}Yy~`N4@nh+HySb?@Qh8c!C((UY^tr(i%}U5I
zo_v{@&>m0I8RC5mg-_R(76!4dWRjLTkQTG!RVYNH>G?T<PD557g=dPF7zdbQ*CCZ8
z9B4z2k)AjD8w}PTQ}a}VtS*esX9(?&NP0Qt0~{rgb%K{Yy*$v06>-e<l>;F4WuQWp
zw9!pUOT<2ffi<7h9)r=GJHYv~o%<J%G-!I?(Lrc9&*^E~tF_j_!M~7+#T<5XE8><i
z<$<HqFGj!{258;><SBE|NdMtbIsW4}dItHfkPFbEx82ZzjbB#Zv+Ei8aHK|{mcPso
zTOqctk~#l&yuL`$?)tIPVe4Jc_D5gPAZ_^LTSx&yps6Zl^!zF@-`NdwKE^a>G^cg_
z<CR9O@OX-{w*1TQP}#O^(M#?5q=uZK@&(4h0cG%pkz{CLz(CV}Oi^n}=*DeDrW>9s
z0Xnqi&rI3Q-u|!<rA#q#!I<><pwI)E?m6{LNfjQ{G$$wT=LYMqhY^_f)Mc>IVgK~N
z<gz>$LfI`B#7YY^GD%lU>F1TD%w(Um;A9JfS*0hs+y`PvsW!St`e?<Pn7A8S?}+^9
zU}-Q&In5Wy_h#5M)rJc%QA#mY1oWApC~PsBs$Nf-6!6ye!?#onK`Px8M$#y3>FXx8
zLvz2KAz0`Rx6C*ML@?f&IskNFkBd7AKJ3KiE8&Yhd&~jJv?A^R+Fej1=W-bCknGH1
z;iB)4S#?p~3S8aW@In90zL;j9nApp6kB2#8b7G|a7%L4T0M~G5+1@Z^QkJHIaWcQv
z>6s2oq}PRz4^r+XEk_~KWaw&r@fTiriBBNZuRu!uaHNpp(&}T4D{W|Ar8s)tg!llT
zs6Sx3$;E+or?-7>QI<S)>A5e^kmDLPH!+w%N!P8kfiBP<QDuigsFf|z89BA<6#sg>
z>zAAGTvm~r`5s_>;e=qSYx#mFf)Y4lk0lWY^_l<o{Gtd`$hMfq3$d(+rUMG?%$HOZ
zsn-B??Q!$kj5bTnHAMJqkOuxQX^dPp#rjV2cjaN?SzwqtO<y}<Ja4{GGXk|SwRZ$Y
zUETT^3QEn8YA*lrPfEbt+uvzs?isQrcT$Lu4!5H3xRji&hpVa1Qk!FRAzF4~w=B^{
z`+pmZhhK4s6uth9<@<2s*z{`H{6)4mHCTDIl3s7dY7O-86wK1H1-;nT%r}{wf8Gn?
zB=g5YjDVwjm9HaEINXp(8{Bkj+&Di#Owz0Wc}nj4b9Bs-UjExL!Q0=&<@@lX+tCed
zwgUOa!3Hvyb_N5Oz4ahw${4H9?fb5NBktfm<#?#O-8j6pDSHG252@3h-I9U&aU>-w
zf9z$o9oJEcH^Ekhp|6=6niJ7D@^}y@5T;4}rsiGp333|pIHtR}$;`$5e97@HvS_ev
zYDcqdBUIGt%p!Vmr|w5Rum$8a%#YJQ#yNeW?$NS;eT&6OV2RDdQkk{1>CcZ9)6-++
zNeo{1&~7(7JspFh@E#)DD$Ht9;ZR#(x(@#4JXlxgy!lvnZNt(vO;rogK^}iPDjIg#
zFx7T;J%yC6sX4#Zx1R-Mpsus+sO~j!lPFn5@(lek%m(kI?fP)gaP+Q1Loi8?dv^CK
zZnfNSu{N_K1yej+d{t#bh=Z&yhl5;Mej)RCW{AQKthO0oU1(vHHcGJmI3MgZv;wX)
z8V2c{@V+WQNiVr;O22*z?<DioCj@65dr*vC9`JE7?U@`Fwm>6~lgqvZV_5Dnx>KLR
z0UsIgr<7nb5p88z?naf6z6y1H*M3qUV0poaN>oC@a*adEs7JAZDN-rh50S{Nu@@)@
z;0~zX_K0!8K!-P8<r{mTr2-$P8KU#%BP<^S(Sl9ZU0ChX+gQO&|GfX55u@>u;%gQm
zFx*VTo!N}c2g4yys|j&6y^I1A3oXV(8dtn}IM~^Tb%K#jKGVw`$J+71{%*A;XZuvp
zW?}R0*U1x1>gTYs^-}AG9@=Vb&D;!fK$j{p<R$pe;jdjhU?cfxXe+)fJKF!>rID#>
zs&Pc+7!}Qy>LQ_wrb(`R(AW;{e$FxKWb(G^(NCDe;E^EfVkj98_iK+#%)4)VU0P_+
zX?91!0`2h{9_@rF)x;dwK^_LRL*oaTY8=?wSL4<m=kRPA>uHY0znu6vtB~vFEIoOI
zVdD!_kZKJ{x#OFx8<rb?NM(2yMyu}28R+p>>e0edXtQ^9p$3A*-st30>RVpH{<l2x
zQ7B68CSqGPy2KdyV1C_=s`qbY92al8BKbtvi^eOaNm?>v<BVYK@%Q0_B+;XrkHYZH
z-lU(t&*xL~*1miV;ly|04%|3yBA6N;Cwax9h%H!p@MYlY_#<U^#=)Obg;~tfEfs7L
zv9nVX?A*HNN%&2HC}actTe%HZ)4;Dw8Ky_R_$v4Ye>8j~&Gaa4%8?5nc(f+M3_Dg{
z0~YyvTL{t((E&F>{BR_pmgE2yuLg>7<qD>*s$vvHp}bm6mN@*Co<qW973tzjEtHGo
z@@%%VhY5?(;yOMbf;a(qf2o8)SU;zRtk)5<vsU}-iU+$NUHf1ZquXx=><OYBRlBDI
zfL$9y9MVq)&Y{|M1!ecm<euv8`Qsi0$fyL41<j{)YYd8fGv4T_3oV@3K`n(6|Iswt
zTT5q+ms*1f2=r<gs)e-Mdx$o+M7fBr_%Iu9m-MskyJ#y#2L<T;5v-CMkEtK!gEf3q
zoylHG1od}g>hhh%z}&7^Z<%;HS_l&KF!qy;!4mWZMqRojX;XAat1wVhI?SVu%W-xu
z3q6|%mjZ<%68C#dfbzi`l!%!GE54aiCeI(Gb*la!M9DN}kQU)qa>v`kyNw42M?79A
zzWR3hJTzmKU}hvuu^5_dCh)_oiKQ*iGLEb11Ab`aZ4o<G$}YDWC3fL$!?$Eqye&K}
zBU&ErA6X+o&9$TMs{dAERM-A({&?nwG)b37Gn?<9V>V8Y(eDU1<Ie`Lr~A~2{?@o@
zJNkhnN)<PLU{+^}fz^2(9X6R5bK9np@M^$cWWv^94I2dUG;}}|MhXR=P3m-CT^Ajm
zt4`xBK1Ul_LwbfGwwUM&A7VSvZhkPB=p;Q@vdI}LqRMidTf`D7BFcWem4U$a|FurW
zXH|6(sBO7jP}^j76TD$69LKps1$d7)I$kWtTdFLT9!R7r7>K;(G>D`s3y5!+{g+iX
zpmNFF$GO21crHq$7)ZS3EEVCt{8&VYZy;y(DnoHt3;;-Lc+izY+<&&diw;z-@EBB%
zqzTj|SV<6wSVg)Q9|j}dM+iu<T}OqG987eL9s)U_mK+&|=2uxXq#DH=|I6Ve0<;j@
zi{JKQPS9x`C7)47Tvi}ADHx#7X}V5$RuB_lt7*T2y@8lc4vX9bCzmaJ#mx1)4F%uD
zpfW8IQnqE=i&p{T>!<|A>dw9y!AITb1beL}ug>1E(tpYDs*nKnZNqjKk&_TQ2sZf9
z$u|Q%JdvYTJMVyz+O(J#fqzlBzIJVyP7!H-Deg?^_3@Q7$SIi3<}xhwpRqL_`aImO
zQ3@O||0U}#prri2#1oY8NGGcm+VL|i>-9`9v57|=wP#0lIbNWO>n|Cm;X6~V3LEds
z>4EhPq;Wv_2GM_qd4<qk!eBv0Ca)%!?vze;)L{WQc|Ipgqh@P;Vm*<_x=bWqCnJtH
zv1ZN92XC3*VtvrmKwd>nw~p!Kcp@c@8;Y;|SV#5V=G+_Vu!|PB%`S@XE}J;IePoR7
zmQNbrDFp=;RXhIS`HVHTlLnH@t^Dw$eC+7<M>x9G1IZaLJG!ylx4qx9)z8|*htHr3
z(=Gg^;#b9+M(+pY<L66r*}EZUjxAqYQ)R^oi~sPIyh0ij>^S@1d$e3k8;}^f9$q;L
z%=XMc>Phd}9qhTV-_By%ekW>%#njBWRh?$Tob6$RVe_UHj0ra#E^6s7TI*%(bY$a`
zcX55=dqU6QK*g<c)z2=Tl&^$0$D(KqG=9O&1ajkIZCC($j)9cC6Ft6VFy)k8;w__j
z0I#Cjdxn8;4q4XV`8IZf2=@~D_qu`9n^p4=J^AE7M%gb0D!G%G7y+35v=>t^(MUlw
zUk=KqTa5^UBLkOtBxaGV<f~Es7<>H|#znZ1$CyTM(KeUxCY}ZRSuOWj4JY?%%Cy*9
z_Jjv5HYZJhtdc&5NmW#;)+C(oBl<_P=eCL`u^SW0IfuH`Z7=OzQj0Sv=u-DTbnS-4
zq&2CgZe<lR^}Be(*zjY2=!nrDiHACENK=v`)zTtnillU0+A8){K@rBf?8qVMJ2)o6
zaAzDD@Mcb<L$^wI7}Ry7jmmIQtAB8rXp=a!+I~acw+uG4$~bpTXb~O<BHoRz%zRV~
zf^P`E>Uw4QWlmuaee2mbV=l@110=5CL2gz4;`T!_WKD1m$g=G3QCw1aweEkUnb0Hv
zMa<1Ne?~S{bkqU)0#{YFaJZrfab0qAM}87tkqGKC;Zlw|HPl-Rbe6axGv5!?8hzIh
zBxKd~<%y_fe3m;5=H^)-%|A#bFq$EEDM`*E|Aa=VagmdPKLD&)?BWJ#rEA{bL&H=p
z(DD)oVta{bY8mfy^RSG^YiAqg&w|$(O>R*23<P1kOoiJ&;4`>RJIk!f#nx*sg|OL=
zxB+#luYiUL*D$CIGmiA9Uz}!!JC{lAz%cCf8d~8PD$Ft*<MUq_&}i5O>K4u!WFg(?
zxZAA_`%6bRmzLTO)YemtIX`Db=sSadQQJ^z-#tOq9#8q@7o-`q&VOr3rhj=0T0_+q
z=Nef}MEb#LA#Q*K{GY5MD60<2Vt~-m)x`hFdehd0_kcu3(bc5PAaTZ_?S%Xf&f~NW
zyhk|$ByUO(j1GdMs!8iXZLWi0I}qFog7rW!BM8RQ7T=AmCUpYA+#nbq1jm73DFdW8
z(f_9p57Nc{U&K0U@9fy6v1k-kjyTyMn(WgO5e&r;HInEuSz6Svl?u@0oGnH|zOLA~
zXZ+hlGGCf<B4sPxFB17nO(D_rl^Wk*hDv>Ju*woZ?iA6`;QIxwyoKfb-ad>ju$cQ*
zRO@90$v-ho&^d${B;MQy!=>e~&Duar)l77d_0%+KNYh9%Fr}}g=p52gQ)Eksv-e(8
z@D*|3wdi11h(WQTguz!{kc;O8S(d<7K$QL>`5vmaM0tphLsKoW)XQhZaLkF-SZ_jg
zvTzUfSFZk2)`;~DRlVIQV>fK$bKN*~M}}~hAs0H(YUBGD7=96?eKhjDnn@rN4Xh#M
zREryvXqy7=FE^xrkm9cMFk{Kc)EPMPKl2UD7%qZcLR8OB(9P;oQGJp^H?GJ>jPOWb
zs$hMC$=L2E2PvORL-($E(!aYKA}^$^WaJjoS2FX8YpWT%gx8hy9U~gb`b`4(l-&h`
z>j=1(T@YodnVS%5i|NmalhwP%3f6yUw3`oZArkMmN@y<;ID;zj?t?114&Zhrp9ZqK
zQO<&EpUY_z8WfqozLrpS^}17GpTDeS85C^kTe}1~I^|6Q{u2(LJNp|fAt4ZaUu~Fn
z8YN+V2&pT%{O|s&lc1)mQoP-e)hux<E$4gVGJG456!zl`i|#Ja{rEG^`8y@{MkwFE
zYV*&pCeZ`qU4CW%@z7@W)++fv>ePs&b}Z=%H^4n0nWPO(1-1u<Eot<X35Jmy6JPO>
zoiQP?wcaB^wb^${$+q~y$($6`R_`69(Bd~6sIcKT3$Pcvv12m%W^3#Uo}==S4W0w4
z<hn4jxt<$Bwbpk^z|r`^c~%hBTF(okSmQSfas}29<>s<0^Nc}U6;WGnPOK$)Gg{N+
zMqne5tnSGCO$>(v76=yojoHoli7GC-bPy>$Ttp`u!n6|ub~;T&r;c~5=)Z%<llk!$
zf7z2QP{>09c(i7(NP@!b+g0V+gkzxR()o)-T~hPOk*Uh#>{k~VBxz&@%J^m1N5EIx
zy5b}GP=7-vyBP|Eo0=R3sVOYB0KzE<eh~m<+Y%d~TxrcD;%yj)BqJK7^%1e*z!XXL
zm;s@BO<tKJDZ<(k{aoPBAJ`P~T`UzMUlJ|-VDc;<_~hslUuA(3OBV<VhZnzbvPFa>
z;bmZr4q6JJUnW(zHnngv;;3L`Hn&!XPB5EU4xfI5*3kOR^hxY+#SokM$H#~ZFACJw
zfo<jdypSz|XOp-EH&M!S|C=xpay(FiO_WTRI0-R9hD(~ll{~o=ZE^zE%=lIVD4u-A
zE7R6hR?auUrfDJL==dE~*Yo3AS{WM@L<e6I<koXSP>_K_4<B~#x!O2#Y8tE}K}Ba<
zjc_Ts`jEEP+phO3Q#n+^Zc_`T<4n#oJ4)O;yZ!3@kDV3ifetpZWK|hxCJkRcND(t}
zi?BM9L#<MM)#2p{7t2*{=R+^nA)m)e<!MqA3>6t3K0k^EQ{tAfk_Q&|J=?Y?Q8}LZ
z@uFgaLjwIQvV=b`*D>-?@sL%dZc!%sFfxdW>Fsc5i|$T_#rW`vAU3_UyL-sANsD`6
zaYxIb)k>R0;T;)l1Qh^#8c7a;Dvm)iG8xsLIhD7vMXUc2Y5I>Utb?Y3Qs+4tAcR<#
zKVfn4XnxG7RjY<Y+}1Rt!Nz2A6*blEhHRMypFfLGVTcZG=G10UsZ*2eSf?WYlsVQe
zLlf;bcM0FMG;Z=EtnPOZr$J#i2HsBE!g*bolqWey7YbQX3^sJs&pt2Y(gEu449;{A
zSkJS8-x}mhqLp4*U!lW)C33d1??Vyz?=n7W44?A-O0wd@|FGc7su7}GM!m@fT416v
zHcwut?Qv!)`Y&Rz=X{bCT5+`xA5b)R62ewrP=opvHbd1ff~Xp(!k%L}FLXfiM`gx7
z+QmbZiGK}Mpc#nD(+u=t&r$?$l^+^tPXsbd3KA8`XU&vNoM(#_|KBt&w&0SK%u=pR
zm6(*awafxyoU16?TB&D>51oVB7~jXo@fXXll%KVSXa97`QdD}v{chFVsce<9nmR^T
zWXPUVLsn$T#mo5FOw~NeoNZ>6Vob3zbLzoUgPbj9<;st$wX7UYBLWZVPY_NK7^pY$
zM4U6?w}qKNjFaO>1CJV7FRNx+XRGEnE4Ca6+l<g4C(>r!WFG;E47M!Aq(x4UacMca
z=nEGO5#ny8Y}|+?B%~+pqodh=>Cr|dC#+1dHS4ZDACt5uPur)Dj62$f<pVLC5&MD;
z+Gp(HdH&PdG~Ae}dGfmu`K-OsZ3?i*0xd~Fyv5EcMN^_>hN^r#ux8T!F{UgNc#I9l
z39>XYb=K^Sh>oH#ZV?!*1=kzEED|C#8`y)v{GYMYLnoxIp49GVPD=-}W~aGRfEX&>
z6o|eES+mL8N2Fb;Anju7Ksw8VbcTz&)w6Nq7AyWBA>)&?QrAd*TalAZ^)1m#&zfzj
zqlT$WGq7r=5b{u`|2<O{Xnv1`*l%g2K5&pR{eLz2lkKmWQ_Pr13%vhh^ZM7+j{kSV
zMEmfBC>o?3>f4095nMj72c4(c`}zMLbKj)^EjSIjqixn_sH!7vvS#gsC><3+ql9A=
zG>&B|K!$eanY4F=8M-{@mH=0quzy7O?<wYN_GUEtZ<H{=B_+(9w(f&!2C?U?J5e>$
z7I?_wykfECP<D=syU~Kok87xI<CXy$-RO8btqbRlp;CWDCEQYH$|`7{D$|l_-ehVS
zKu?RIGO`+d=ZuxC?{%5h{~6xXAhQoMX8<v*UQgI^K2O=r08x+>&lK|Nd|geE_-t{F
zf1p{=g}6q>Hhds);D~d~%&&XFV?z@%KwqNbRM`g?#$62&*QQ6jJ6qqNQcRpH7!H5G
zKDjd-5+J8Z=H?$Y#7pK57dAyM2XkEMjPMfB#qb#FcK?rX4;36#2n3&pJ1GPYg07Hz
znG!+fS@~8TniQ>qtD;RM#cd@Qx-5HRN2dD;THvK|CdjG(?PsCE?kKTf5nCgMIXnlF
zYvFqfBD8kh(t9Uw(;`rR|6RS<k<LgCVt$?!kH4%U+H<}?1xIB+w(ZX_D3WES_A=wC
z^-)&TV(N38$;FXwdR2QNApGAPwL1FMO8Uvlkk`)9o6AW>RXp+lTT#{^{c>DU7|G+R
zpZF`H_#9$q7Lmwh-zLU_zcrsVm|#%sO?O@1UToVBC2m(^Kw&l3UBQx@;-FY5^!S7Y
zF!TouB2)j#j=jEZA&_*Z!=aWo3v<-{m9(Nt37Cn^GX@$LF+5f#4Y-Xpx)Bms8$N2N
z_c5R4E^^o9>Gj?J2C7B{CiyKIblcQX^Lo-Paf)yCiT4g(dnFCljO>;T^%ISmB)@}a
zTc+c)jr4Pg#{C;kam;##(9p$-FeEH@*JFXngEUz~by9C5piUnkFW?W~|8H~NV)FUb
z^T)*Rr`=RUMJdKfC~eVo(5_Au0$O60VKKy+bxIE*VoXt6SNlXm>P|4>H5=uQ#Fo3s
zJx-PDG(Snvc~e0o(5>qw>abuH98xFTD)?!Zm!)Rct%SB3Kd%z+fINkSpmf!t-E^~o
zL8Jw95(X=URIpqi5uZvoxEZ<)4;$v3w?kw6MHlr$hQN}VBIEa^Y`IkMpE4ZiiF6B}
z^kL5;F!Q87+tPuC>M;Jtbq+h7MtxTdm^g(tB!J&Vm7)8%2!2jFB@#XlkC{!@`(F>n
zF{=0%2Ln46xCT>8t-f32htrAQL9&Tn?)|G&(@*W?E*r<{eKp8udW_)WZNpVfGrV|m
zopTID0hiMc#c@UZteIcfv+S?>U;nZ~yL4__i6_SPu>Orx^jM(0`R`u_=zkKY?8B$Y
zuY<>G3IL4h2|||(h{KMOgg>`Lzs#C{F~IzUWhmTH&GRX7GsR;Vwtr>ci-Bk~MpT#9
zJtK%Hx{|?Qz>$8Uw{3q57Y&y|xelfq66w@b#Q9`va-YipH@~=)iASGTy+76JdtfjD
zqwBGET*tZER2hwW2n-|@cM*I}L(5Q4@MksI$n$Y4=VMapAM$N%9X2Z)qwd1@F{7Bg
zo?2nR)@>U5Q=mLh5q_G4iDfAf=dKbe4yB>(Vw3}G4vRj6u2>&eQ)lft8dxenR~wy6
z#O6p?Vnd@e1`8e+TcfqbGc&;Vd|d0m+Z1i^9|ODPs%U;}J5ppTok`RjSmTNUK@*^O
zHMp~CGrf!Nj`kVKs;d|FNHW~^UT_ofqB$DN4iJ^yvuxn7jwC&EsHUOce#_2w@iHL2
zu8BRU5*tCZ2e!<p$t2ReIe9Ah`WEJ-Be%ZBiCd=Pl`roVMrd+NPN(yof_^W_-d)jY
zycJy`e?yF_$1}N(a(VaAYML#EQb{nn?`M4Itr-qsZLi-2f6CTqFIF2U7-oToDB!=p
z61gZF)$5HLqDyhafcfX6N!U_@CSx`ZCBELP(VSM!iG%gNKRhLdEhr!sOs>deLM!65
zo4T`uswHd~&roCfl^snsOWlCae3~AIiln*(6VJIWd`QJrxOxAqvc$`}5dyMfv$HY6
zddZ{ts<~2Z*vnTk4<KdVREGgHvot6*MmaM$FxH+F+KjPO{<${rs0Sm=&}9|vW)+c?
zzgli`hP@!j>-I5qN9*r#!xFhN#L8_vKh1dDXO2{!Ldnt}i+_=ryEiq!I}rmsy}i9h
z8xT?<j`v{b$k3)WXN!;azUiG{&DWtK#qB>*2a2bfZBCM#v7w|&Hpa-0Sm@w~ByQ@_
zW>hqCdHnpDK@(HjgKpD6AZ!@co{-<&+4(lnP$dukc!!Re6lt0Kc>d}crPVpwEH5EW
z-th^yk6xPT;S$B9D?QjMpLz@S&BS4bjsRR-QZf(%Iwl>}^Cd2O-5puNB>)EQ=qS>h
z|EKIMih)hCT0Xi{a!10~zA~QYa~4mMOrN-{Jb{6aQb`4IT?}RHQ%kUn$iJvyRS|5u
z2(>`iZ%FYb%b%K&5F^>=zDIofEyzpysM2U+%DN`LAF8}GzTIjLj7%ux@${M!6h-u{
z(W(;KbTMj?ff$%c&Z=PWa%e+pcA4Ye7PgF4++^uuBjqj&Jf5{pDjgoRGK=V<ZG9&V
zk<D-=VDc@M#}GvSepF!6K)@H$G*ZLYd&Tps9z-(ugYJ!0@VblG9ys{y!2@L5+N`Ci
zQvr|Ti8cXb+T5x@ll((Q1H>j4(L}3DoM6v8F5-!pArykusX}Az&8b4euHPo@q#j+m
z2lL3#dyS~VVb~P$%JN2jcFSt;1jCom)GguVKU_1^hEa6U!0)r11U}rbofJ6Va7@nr
z8{b{$YL6qo^4~K)V7IP%nI3Djr%tKl=hwuLmCaS55LfdMD0ghciE7g=Zbz%6*j4}2
zzvmd3`brmr?hpjqZcB{?2jR5<ni&=caUt`FjI(5%fIpDqMK?THahI}k?K#tp4bv+>
zn(?Kn)=svm^HSY*CP7}&#?=5%)$!zuZ_2^B+g(t+deVFbo@%!tjT}#i?tjw%39Q%e
zbak_B;?)2PHy%400K>a?21!HoJ6W3q<Tl4cc2dHI6Hq5W)Nl}TWcGcy8lmCJj>n@U
zbY(gzwMA?axlg1pFRJL;&2c3Z$zytQmD_<uB*+%oYTQv}KPqX|3lIk}!ZAfgdnbyc
zcN@U%Dr_(|Ssw!#C5EhbQNiOTayPHweWk)Y;-!4Ze~v%)l1@rQ#+`LB6ilE`LGmvU
znZfRjZBCn37r5z;471KI%pHXpnOr<TSlT^t`YNhYyt{N{cVo=RMH94~GH`pq34PH>
z9TO3+h&8S|Q&esz7-afN0vS4+h+Vv2v+KO4(Ggr^IhkhqB>03tQIpv}GyA@pRiKDW
zWLf;Vt&|*{i(;-=Aar-%6r+az+KgRm`pL?65Mx-~UCN*I91meIOdU?9sU}SeZ@5_+
zq^l&!SN$-Br&>aF2`SB{)$z<e&A<+V+4zPeZ@ulN-k^c(Vg+9&ap2EkCnmO5mJ^&6
zGG%}hG8$3e$;JS$6v<^snL+&XB-O<LC#({(h@kLbLRyCm`RxfEOD6Ge3;Q&#yhr3H
zB+Z1^QgW=beaAQpBR;+(&FNE?iz$72+4qyFa~dTopqoQ4yChZr@1r5dnbXu`1XSrY
z^UlEI`9KCN8bwc*+tlP9Z(P^lrUNbuB_*z%*qIZTli^qfdDZC*T(wNW=7($_Z6y`|
zi}48DtjS-K*d+Ng6Kdd-g}AyjD%p3@+l(}CPg19&mdkOIH7)iXtXWDn(_y5#nZ+6O
z<P^V5S}ypyIV|aZxg8BTE1cq;z#wu<XUB|^NK0Ehu@xUUj=7Ldkgt02Z04c|A&n=`
zo=%4`>LeFs(pMMJ)Y~qvKExX|_AJFC<gnzKrBU;2Z-iNrC6VJ7%ly1A&hu_VZhlN8
zuKHm@dYXdkYD%7dYIFMEaY>pjH$X4DBGZ4})|xp@KS4m{elhFxI-a<tNhcS$u*<I<
z>#;wMav{)(2fXEWvJg%`X}DVYq*AOnboK4#QD>UNyO;`{x?H)0N8&@eL?j+hK+~d8
z8PGcBJ4`^pO=8~gG?1n6)^)NFBP4scTDn`Xqi`FFW>~15CRrI|Ms87z^oSgc(J-L<
z5$Jx?l^u*YJpq2nPYDWDj0TNn$Y0Nf0kzZXa_RYtSo&R-Tkq>i7Pr+B5Y$;xY_sSE
zwsFErgOkYli&a9MOUk_4&|KA$$h$bV^;!^h({uZ1WgbPjUz#Ij8wr3e6mL>!2qJ`u
z{$C?rJn}^8a&|_frM$&9P#*<Z?9SzX7!GkGe-Ww@;|1R!K9dzL^t?fG(O0bHS59P?
z?2ZN(QX^u%x`SPW51k>W^uW5|!)Idv(G}b6qc%P!;4&pFvXKj*qOj>GJ>}oTs3N)X
z=}}al6_f&XAIp<!qM9x?JjX<*5ayklBkiG9fDVkDDn6z%5c{Mmx%i@*CB0w{*`^pM
z4-}dM>PiLbA88hf=T%MQ0d0!lp*@8;ZAH)c$a45d>XCs)FZ*vFT^qkYB{9?(ra^(4
z>GhGQ<6)c25JE5b+oM}xbcI-=AWEOLu-$!z!_@(lIh?2pnV%Ln8mi??r}jf)vWcN(
zHf{DVP^^M6bOw9v2r9pC!$t?K$rh76(YbP;L+b!VdM!WV3YVU{Y5Cjifk-fAHbs2N
z7Uk6lWl-{-njPe>@+VN(UBj5_3qmdtsHHy2uQVx~7)iL<&J0x0>Da6#;p*k(Ib_bi
z?t!WRd<+%_*XJawyYI>k-%m)rLuX$QYgQOxO!ykL5o`KYhu4FX2&*sfVBr&A$rrU8
zodGDPCd;^LAi8S{G-0ldvao+S@wBw!O+6=}XBB4XFu_Ht0mj2`NVBC0Hgi*DaALub
z>fb}owHijjQ6j^GfiNE3LGBSI^d!G|1}GxqD^V(AMd}|VM-gS_0H01DzobmA3E~@v
z>7=$&eWse_E-wuu7Qe**C<5_Rra!41vast<_8R4)TQo!0P*H-1xO@(YK36f4Idbt<
zFdZkkx?XB+A7f=jIuxbIN$H@42iWL5oU0VbiskjMl$v3hN_83v7T(DVjinh*Dhmtg
z*YMmw%7oYmAhmHj%#wu&FQWt>mJXNW=p=I#1U0z{rlHvc6T&7H-GfikH~0&*8Kv)@
zMf3z>PO>E#&asME2_twSGDAbzBgBUMX5_BNj#oqlOsxJWNcVgbUDksvwdQuaL=9r(
z)kj|qi3XVZ;Sf>rBCjB!+RA9gFNA1{6Z{F=l}=$;$ho;_I#yQlw9xaQ{4q|^=x7rv
zf=Q6Ua7dEzzF5E?8Z5AGKnUfbHx(xrBxx6IwFE;d$)eICh;X>hMm$vcgGBe3hc5$i
zh=z{|fncAlLCW&!^zBGi8*z9+nhS=9ZqURfn<SQ$m?f~<f)Rb(r*0KzT&xtUW+xx;
zh|nx@IN2whj+|0OG=Lh0vwZ3S_75oVy)BCXX2Xt_pmZE{zP>IKW0DooTo~tGm`mAJ
zMc(*^R<L(bi8}hI3_cz?r3`zO_B?MDX|NG+<o(kvQ$V^GK(+{&7SfU9D%l7^r~Miu
zm&0R;(|ljVvkbt<^JEwTbDxKSZ|LRA-S4n}-xk4N!s3u+QHMFs-|K2&(DzfP|6Y_&
ze3wqKY1lxfzLENepR)aX7%O}!%F>!!=nLpnR%VVjNr1=CXgdBXrc;5B`4E2LfN8Q`
zs0%4Bhm-l^M)s?<i+Bu8GUptBCY6*Ah$z?u4=XZlt72;0x@G&bmp3p@DtEM-Uf{y6
z^g6Mdbgxx60}GvTn#77gmH(9v@rnNB<ryRv=zM&~H)#SQpY*Sh$f6EWC``kDWHJG<
z3_dh=<72LDB(Pw}2SZ2{<3uK?b#-#HZbH^sAT|%1{U+ozhhoinCNJL6O@gY?2d*xx
zMsqwvz!0lFTrWk(w`G)c#ptj`)Wgz6dx|ELDo=g9LjGMY!0hFuRdY}h{UO1!){oLf
z8{9~$g1Sm-zB_}ABXIHVCT$lEnp9M*y5Mj&expTBzryUU%KOqsbcs8o(K<V!#3p?B
zoLtVL-!4N`A#~jt4U?J9SUcxchHsflXP-N>xEm;=q|l%kfH=KBGa*-v81in(5V4!}
z!XzCoe;1pf#^^1kl4p38pZ1(XVFIzs#D<ontya~4xapFnH0vmNj+9vwtI%bO2LE~Y
z;=!k!Xe9k8AGbKjw1Y9|prRGjv7X4Tg|#QL81Vry>hKTIum60{PrB0{Wo0cNOXi_)
z0jsR(|D;T5n6Sd#bti#qTd;?BC>Wu}`6KW(WZ_JlbZOBHRQvMvUmZU+6dRdnR*2vm
z&GDCajFnp9RK%*zk$Av#nIkr#WQ$7N_7nrO(e0Hm-){{kTcW4bB0jVP`0|oYda$P6
z1R1eXN#X$cVyJ$?6L-A`+s2npwIh@5SWCK3o=4LG6i};!E;+zK4&p}%MkbX{()HKZ
zE>OcNX)Q+8a;?kZ&1rLubPH29<ESm43P-UXlW$|VH};nGPmDEu(Cj+UpC(B>MKL32
zh8We+P#rwXx^wK55YVe6hD|84RWhY|$~wKMCD9s}2F*B!zlKV5;QOm3SzeF%fvlF_
zCAM+nIS-}aPa7V{_XpSHMUP-IYc?SoR{_f!j`vs^mK*1W2N*qG#qrjMqwBnnvV#yo
zx{61v{Tov;igRFAXT(nT@RBsvBnSXnYaGwW<x_G_sE6W(@l*n@#L9!MU=p^@p%gRm
z9vSUV8I+>C&fk4~R&1$^Fm|q42l*X*{YGC?0xUmS?#TzkFMRe_^UV$)AH^FZf_`{m
zmYUMed>i+<4$tZXH-qW9x}svEof)&$U<jKe!0c}Fqd(&026HnG@NU$OrR_}|_u#8O
z2B7WIy@1_~zO^u4@DVfNkx6ooY~gP`pKyL`nCO};BTzP%>EJeT%e2jP>zU&j+Xwh7
zD}Y^OpkTK`Tl8X36kvtdXp^ixGh-`UcATFFq~_qFTraA0)m6&;&6weOr7N$N*hwW9
ziGUVaN;3UMlrNqvEDfHmziF!QV|d-QDb;*3oSdxX@)<*ww9+uVt8C-F@vK%Ei7uH)
zY~4k{ROiNC&0OUnNzw;_PEMB@F$ale+U=N*RS`!^;F#^n>T4S%%R)j{^JoRLt@75J
zBUDxyoUCviftwhfRK_!Od;^(BgHz=l(!+G|!`qbT`45Tm!&{#E5tvdlbTF>9e2tgz
zvDsXi(ol<*tc?U{3*lj3!Iqla$X!J&&@?i=)8X=C3W|#zg#<^blL@Z&%^-r+5ysNw
z#sG28P)6+TeYo|tkNMYW%^T2ZP<?;?4jcJ`X!K!gYh~CrWM3zoLEcZjVye0I=W0BD
zAXNCJIqO5;yLtWD+~<XQD;mysV$Q!>=8M%&`?I}i_&=-u?8pCN2w1D}DG@2~s`l}`
zmUK>Eu55n1&3pJ=|7-5+@hm0aA4fjZSOBkxt=HqKKH$sj>+Tm{fBv}a-M_2Z9QKbz
zethOrS0{p@tL77kOQgA;yJ^XN#koF#yiV)pQ47K6xleD@E?1j7|3*Fp;@$v}0I`6c
z{I2SbiL!{nx2(+Sl|1Ep{($EMhfa3S6VY#F_Hh~?_CFE;(Y8KM;U2v55_kNcf}Z8e
z)Nm1gN=a$xjj7T6lN~Yf{Abn|P>RcJD0aBJ`bW}Er$b<N_Y?rT@tT+iRzyZ-`IiVy
z5=C2)j9)=8A@oVK)Cc3_CP`mt7fBd_{w858Cr3o1!WSY8Mg4RB!%44#q;dW}^7#@K
zpO~2N{q#>KcnU=~kb3($!f?ckEJXne5%f6id$O9x^%e7~DGMn&7+COQ5f_IsF}-j-
zEa|bwFnh_1NWr5UFh;qNG85nA6Y<V;?m38s>#&|i`4Xv7j1tATjArI`XfZtILq=T?
zk4_Zl;acYvKkw#`Qy_Y>>n5+w9K)={L#a$##lx)B)Oeq|j!(<FAT6vLI#Bc{fpT+N
zE^KghX}L+q+f%e$$7Mcu*bF1sSF0Nz;3H)cW0~v+vNkplJs2eyMW|9|JAl8&koUg1
z%zZak+`yJ0ijp<l6}}K0GwJ*m*Gl$C|2}nI>8S<@=Buj)D(MBFQ%S~>+3EXJA@>J5
z>A;+awoqohzCPKzqOm$<g!<JV;0$S(z|t@>?EQ$oo<L@o@x|Swh5N~X2`_%+mS+_B
zgyzruf6nY&{k@D*s*oL;sC)|%sAG<owYdnfHhV#J1S)++PrV}7=3IhZ%SDQ@YaZ{a
z_T|+vYaX@^<^Pks3s#~TZwGEl3u5zz1YqpUWNFRe5su92WA3g!tw9w)6`jogll$oV
zCp}B{SD3%>i@sBRnCW(HZ_ifJs@1HrKR~&*V{6OUke2A`wtTNxOTYEKaW$dV-~O3A
zCR6|KtN4X<RRWG`3cFLAj-UfUcg&l`jX3t%H%B*e8MS|=LQki(E}w(~fHS*)0#wif
z@{31yz7tqd)b1_&4rP7Bs(*+|+<}0#slD)tJsAN)yd<b*;186Pu62MJcU7J9dUM4E
zb4073=F;yBI){X5fiy$nueu`p!%aF4!>UVU`yPqaG|s!#G8^vao4ubZ#rb<$9iAU4
zy0x|D?mq3kE?3aRs~!K&*LOpHj1u`i+1`THItSpbTqnt{b_!#E`9*@gs*HsOXxs8t
zsJ|v&R&f~BU&qjGcSFX=>d;@v`bF>@^(h@uLT73$k8YE)GUV2?vW!`=Jx~p{yAHVA
z3D*pwhNRE`E#P(!84m`GkKVRQop^*>fRm#^wik3N&CY(0d7CwZ?=Q>8WYW47S1ooo
z=NRBXS=?p_dsB$%44bonU}HipQ>{GnQ%S9y2RzQFk0Ks7{0dWW2aL73mBWckT8wWq
z;U<6CHX4<M4>OObd*-U-vErd&*j>y$#q?(33*~$Mg#kcqgtXJallOP^U4K4KpG25N
zw(u*E5X}B{M)~)Bq?@hjyJs)F*rOr%qyA1RL%6Qn`>Y>4Y;fU6-siOJz)BKPsiFXV
zb1MH_<8QMqUiYPYgc;gleO={d=9mj2^cIPphM=$!Hf6Hjvb{ZQ^c!#0siyP-97rEl
zH%Ko%Dk;&tkAvm0ZKS!h*cT_Q&qM6g?Dt&Q`CBu=Umf&&2*16@m^X3iO-cJ$!4Pr^
z2(C&%^p71%@U-81rT<j->-;DpHr3^M9`~mqum-XcY=3oRD%lHvqx;KO<{3v5nF&So
zaf!x+$YUxj4Az!>_HFNkQcU<!**S#j0&s9>A(K=dhJqyce74)3)-BK(T7kAa^Y?as
zjeQsrmo<Pz(9^7b+j}3Ko^?aKtUP7x4z6xrZ%JFkv-?rJo~%b)W39UI=`0d?Mo7b`
z`Waoj@~ZQ4mUw7fu)!S%D|Wi&C^ccSE%>6etB{*mm~%@{jHJDeSdX*-XpPr6W6PQ;
z7`M??xFVMhLo5g}MSvAca?kM36nW=xL@Rpn;_BXXkg#h2VSW0vzF3SHw>}$Yc-LPY
zOv@KfnbkR4cf>|zK-`IFDF%bbbi!%ZO)i&}C@G%)?yhxwwr!M~1E5?UZ5N>?i^~n6
z_#|nH-!<JArt~hox=@(ZeXA|dajcYY8)Nm}hS}~TtzpVMfjorWkZjw%oTwpHMX7g7
z<hShO3Df?Laxrnz9h@)m0}?aaSaEy79rngfU>4$Uplz{U_47#s?A0{kPQ^lq6aUYK
z6udA(616Tfls>Nr4r7e%uM^te6%-X>5IF3w%DOFQ;Ol-}nmmEAI(auK@bqpZ_y1f`
z!K1}K+x62TcF>W+r}*~Y477c2t1brgj%rEAwvx{3O!&IgVVcwUz9qBPQOT2P-x&pG
z`-lBQSvz8F^t8QEt~!kt?DG73f#4RQ<r9cCn94d>9OK%cNl75Ht(DeNRkBzG1wiMG
z&^}uAspR{EzVQk$v|rgtkf`<f10|WNz4y+qd$Q|?(>?9n`^aQVoai>H`LXO>`Q;|}
zk)l=kU^(|n{TD%AnvK5CIeVmTK46G@5tp|q>KkE8Nz%lzgWk?zN-4h3sU6v05kUs;
zL9dg52NCjo0LkC7Mmzywe5+Mby4iq&qS$S-f{MZ>)IRt~m$}Mooq*HjmgqJYa(>Xl
zB@jOS279722V1rEjI8yR<A=#5i1LO&_p)3aM);SdyOFEoahHjyt%Vq-G%;{&!api@
zq8`lLViFBe{fi^H_AKi<SQ3Y#xUs@N^xxH?^f<<KvfJ2YQRL+Aid;^xU>Vy^{*+eF
zjgL^=Lt91n&&axZWq}Rz$W4jy6KF#EsQAC$IZ5#ur5Zkv#+-6()8pC(LPTjvOzCR&
z$Hn?JG0R?U+{;{Q_G>Qe4l{*{f!-^<E!U6^t0vXZIpxq7XZ)@EQg^w>(3^S4tasDz
zgSz7LPkjyNn-#OuYT6rZ$V;zR-h)l;@Rs$A=n=PGtvq+|<g{67jE{|OyM|>=c9u@G
zo9#bk8vy0i8(MvFD4ZI5>O#}W>cNHa?}~5geW$@QwGmt<uw`a@CpoX>FY|b|?Wu+2
z$WY6T_Uc&SZ&v>Am1SD?t`r#yh4H3M_B%AD#e5U7eVXH`AMq6UFC=?omPif-5h^W=
z;|vh0<2a^}Y>40XRT%WS>>Mr8q0daL19hHcF^t+=P-CkD3JZLed4;<QVR|;`_oTqG
zXY+{kd4;Ce;|zt{tjO9;Go5K4PV*zL-(D{)p=6qRpWzdVdf?KHY>#TWOyeE=o=;Oo
zt1@r9FXwi=59_GsKVF*+t;W=&(HeGUWy=Xsg&H<KeExNFUs%zoT<+~?%;CVl-b7&L
z-2u~(>2)9isD!%c&)d%CszmuFji!mb?&WeYiQ4~NqM@WK;0ese4<Q^B$)g(u0`Et6
z#ez&J4$L|;Y^+>ha0vy<{*ZW2zmi1|!ZPVfG$0GGBF=DtZ|n&$1d=kRTe&^<Jm@H(
z)StXv;yS)==+}UzoKN`7Eo{Icgp{z1t<791ssc;KdaW3Yc_l2nCWGm)U%AE@F{07?
zEoFxDC|ac1l9&!Xc;KsJRSrF{K4xs)f8d%OT=T&w5%vnnc0FHxZk5WF(UG~C+o70-
zee6EZXGON+IJsR@2CnW-*5GP)V9f)_YgQ!Qc#M7NJHXOaYJCR661@F9g0Fm*U)Eg@
z3cKwamm!L`&LU42X!0K;zoriOKSuA*R<-f3bY#ic@_hF#4+SW68yJ8sz|oy5o)^vS
z2hs$@QGVz=E&xsl?ZBmD{33?QyanI%_a1F!@G>|rn|MN?Ivbe-bVJjM00YCf%^72d
z(|Ra@GNe25yCR!!{=H=B+35bPD2=m!R!=`{pZpr@Ft>b-XGIo4Im9Ajp*`%Q=o-b>
zRSE@Z>Q6I1a;=;@I~cC?6c)ntyJ}za+_1{EvJbPQ<xMx^S(Y?Vij;`x&{fa1qy25*
z@5Du)j@FpwvL9<r+*SeQ3-)kHfOOeM^fy(_1U)*rQgz09%*pXq#ZgV=eT}lEUOqPe
z-x)#NVOX{?o{B3S+SoE;<#@&8HV!_VicVtnwKt0HAKd;nT=jDwcun38%L$ks`&sna
z(LWp53xTeKJ`ZSE*7!;5R8R+(YeQV5GIq2aETj{cKDwtdQ*;oei?+tIIO%Qre_whC
zk%Xx;{;uvd672HS<bg>vw!edi{=fhWw3iKbx{Tcf8c}!=vGkCcF^Sz<4iUd0qLrAs
zmvO%oU{^PF@IgGT247yr_C=dtnuQ`tuda4#_rK@l#=PYJS#z}DDrA16_i+=^I=nPG
z<2!i4c}B4bb$GqsuYT6Hl+CEl5ihADXGR}G2*@}v3ya#psxDvp2*q~&9VJo9^s7^s
zN1yfr!xbA5fsSfdjbps4+1~pc@dQLw!dp}aY_j5SD%tqC<C#{LO_V*fK+1ivM8zn*
zzQSK#Uhz21(fwU|@#j0jPA7dF)GDi+z~Tow>O1-9py^dILd-RPu}KAswg!?SZMK<{
zthz#4f8IW=vkQT-_SHc04-_LS9?aP$fMP0P>AwGQ?2<qWQpH%(aXwfKPDH^_q1%63
z$&Uy-Q=f7KW>dk(GUV!u?{l@48%^vhrNO5ZB!%SgR)odhMa@}!e-AP3copi`rU`>1
zpenFNcl4#_)HX)pixOh4{40F2BgEDxmrb0sg%&CAVC$#Om<V~n;j_T2tRklcz(Z0B
zc&o~%`01uR<a1Hmew++A=;2NLGOkMtGU46fw~@qb=~^{v!hL&kr1N9@$*Beh;7)R<
zm>sAk!!+FWcgIM<ZVgY?{1(n!QIQ@)5{vj#K$YmV`I&>yApYXy&adGl66wt3!B?1T
z$2Tc`k!rpj7iGSV>PgzNJjQ8i`zOS(tJLtZ=^(Dy5AVZ>nDD*6H-MoD*YCE?-T>Uz
zNkoF}+V0WS#pd;8BUW$Wo3eiy^@s(1-4yG$D>@RL7I^%OHYdpe0l$vQvIj9FF4pHY
zTTIK1G+Mq<n{%W-lf;wjZrgi^GYDaPp{SaBy)~ZB(M2D()9~+hnRCPbz4*;&GkUV(
z3ZWoR%$FB)&>ho0cqsIFTG!L=8h}O<ox=3ZtGa&ok}(q!`Q^+Zs?hoC+|N3By0_Dm
zZUQ4_Qht~4FP@5-bUInD7<AM+n1t^5<G<!{hm9;wV)hh_;-HdeI-$Wd%jUC6^_Exb
z2niBIC=T~UY+Sh2z!19)a4Z|RR0J<+NQi7}3A;jf_w4SCUoav0E=>-#%*D^j!;*&f
zIXz%4-|%UUoBEXKdisCB38N03OpAIULF>chw`I!j_IBro)4&+%RP;iZJ(#_@nbEW=
zek(|LmdRxxDeva_XUxVsZKnbQnbG(zMa}Xwc4X7*Rg^3LoaGRN{R_W3G*WY_<I1^k
zrNP8^7tObcf`eS~jiX3E2}r=foH1=d<9loHJGO6N2v+7Xj%-Rv8Het2XRvs`^Wf(R
z0MoBK*<vdFB#|+>c`l1&XMe0g!VECSG$%6=d=mM-prWyTzj6~~FJ<VC0V%wAo2x7c
z2_Mr`#aHD^Uah2!D$EyLcF|@+-|?+R$KnWEKB=n!-Oj>f1Wbce7y56#IZ|pq(%l3X
z6Gpm}_%K>cVKKa6vh(`IMVa||dlQ`T#BdUP*m+q~^G!FhBEn@}sSdIf@^6blBJddp
zRq;gv@vtvZ&ew)|n<fP=H%3#N3N|4Q351-6uKQwY-&Fp^{*1+b?PFs$WDM7qMG0_o
z1sGZrV3XyMF}&MkV;X5&F#Z^ww+*?TLfTe{@<STKvn9+fyywEtd6tQd>Lx~U{sl|b
zHn7~|%y(Ei55)6UaE!sWHlI*3j=TTG+&c$J^6*=qZQHhOPWQBJ+n%;<+h(<G+t#$F
zZQGo;f6smHzISiDdpGvKjf$wK%*xEFsHliM`8}U=GMsc_C_GiWf3eO8k4rS@sE!Z-
z!*yF;B%r>tA7CH_u-!=bNnd&oES_Zzp*>G(!6V4>26lbm0@okhGYIsc(vM?3A)+t&
zJxp#OJQs+INr+jD5El#u2}Q_>q?J)nn71`q2<;W!Ec*WSiFD#GmG*oVrAqvHrk>`O
z!?K8n5iPodMHCXMpG^;5+aAW21Ab6|ly=^dTFf?q3pk`zV^4xau<D+`&|DVUuEx?w
zfzkl6hWMxRiK_UkEsMW$ysOny&q@}NrpsxcuY;nn8=YA#`mQ9Z;J6~!Lok^=NF{f~
zQuAh7Z=W5BkNU3>XK^OGe3zf}#9Qj%jRE2EtD;ZNq?TY0AMmS*zzise2@>8O^RRtD
zM&npcr5XlG7ddJDtQlIQ&z2%=OaY|?t_J*B$Vmhnd>zE_pO&R!VKS;A=dCwMX4_fG
zlAq~oNS5hFffJLT;7g$|u2q!0GY_2KYZY)zVabH{BX6g;QqmDgNg<Zf&_-4sW@s38
zRYh?+wtw)5>xefF<C;ZR#sh}j!^59&we1n9FfV(UX1gt1iJV(e)H{HkgE%bs9YhVN
zBut^B9V>xGf%GJc0w)wpycc6a2M$)z{Nxh^-4Ia0PDl4QdkfoZHV73pQpI@uh=SkW
zyI?g%LTQ&`4Pmi!VW}g^MoZ5N@quU@c%?%Ct7bIU*9<%<BgG|6+3PwHz`ZqAQV<mt
z$7&?nnX?!ML?<h-%_oNu9T&(WkD5u(XM_fd0DI_(9Eo5L6`y?q8Zg@%K+EftwCZYU
zTDSyWjm0b2m&~f{lP|h(!x6+ZOhZluPJ?WjO|q%pY=+)BU|MCkbyM(!RCmSH$xx0c
zkRni^DPbS<QV&4gp$;Y3)LlzZ0|c{B!Bs`-I<S38ozbNkzhscfX}r-$eL;*Ulqn>C
z5Kmf;w=U;EDC59q%3w3O&=v8du50nN3!zMbTNVx}cmSvc`9UxsuihHN8I=yju!0~m
zMIgD2wz!WZQlcsfhogZXgs0FNLIWe57#e_BgKi;nnobFj5^RA*Aq#Df(Cw+41SB&(
znN|EZLd%27O-`9jl9ii2t<P`8ajKw|o-}jKQI+dW$`pBm7@DUO!YRy;sv(Xzgqp7R
zG<vFkOLw0?M&?!w^@V=9?YA0W<x`CA5E^a6Gcp>mi7d&W`M)j>VkZ&Uc!Saqii8HW
z70kYk1yd89k-}RBf2X_s^*6CJNh~|efHAlm%$)P5bjw9noLL?%vnk5RwW%3Is1QTz
zsVRo}eX4O2`hk$FKhpjT8GK3<aa5xD6X(B#54jp06`fOV25N>?RXiqFS#aD87VTzv
z&|4-4gy#}yIxLt-Sr0omeU16zrTwuWGGaI19$6MRGKTxbX@bn2<WyM66s(ECrUI=h
z&-hNBV5cieDh-bAzERSm{DJL(7+nn)1qQwv_Yy;4K;|<;vn)1PV?Ba_og9PC#$d<t
zx!M!GXz~L=)0l<EFR5AXXN<o)=^|zyX$hAEf=36vG80<43SNd0qq5T;bcS`}2L9vw
zI<|G7)mcT`O|ywf3`h@z^P+8B5tIzFalDOK{Q&{A#*nDN5&1x$gqQNQ88vQq132lk
zkwl7G32Q1aPUhI5v%{SRdSjf8GV<kKijay?VWGWkKrw-Gb{Ek4vD~_$`n(WtbYoPa
z(W#ZSVhlFb=Pm&NdWD2Z!NNLi%}kMWwYCNU;>yMsMXV@h8P7D5mnOtEb&pdUyA}P{
zDN1oFX1I!AkZB3HL}*~TSQ2jfyy-K`JCsCMYrkkVrt=W&+(tNnSd?&|hx!d_<;lb>
zwfcuG+N&B%h&G(-)tM%;SJM6;TyQhKjMKLK2<~f)p~Fjjq{0<pec`vH*&)x)sZ6`^
zG>-+jQ*5w$nrHA^1ao<^^c&rBdO1D|f7DMR0r_+pDx8G;gq3iKrWmi0xmJJ~?F~n5
zJ!nFZWPKHK&9=b|;6@ZftVeL2)bS%;s1N=|M9JihR_RxrN=fg25RS8|SYGjm=*bX?
z4t8rt{kHNpTu0r5AOq+yDxV-jq^@F_`sw~p+X#AOTD--OhvC$vmJnHNA3Pw%#X=<v
zDrQG3nx#~BmAzUOT>(QG`9KBUY%YlKM#wgjC%Xzxl+2Qwl{(N8R6aN{UtN7lKfRLg
zNB6l7h3{vF#}YR#V8QVnrg`lstt2RVSd&`x=ZT1bQWE5CGC)cI&41E}QSJeH{)vYf
z{w8dz&@WxgG0-Z@L+C`(+6<7le{YK|Zu5n@GXs($m!6B!Le4y&U!cvwkl#5V&T>H&
zg7@kanpD4tgto+5EQ3E{!WC>7{=#r;!mEqQA>f=kgX7ZA<ZOU4Y;}VAB-xKDneXEQ
zN=eN>%zuzek~1byfF7F44lG^FUe}OwW3I@GDr2#RF*g~pfb<Zxd6|%wCk9hC*<_4W
z<j>Wow%4kX@TjDWS-rOEORESr|J-?zV?(=06O0L3rWw=SZvj<#q8UcXQjVh9nO)D~
zKTW5UR9wk~=+KPhVQSK^a(&{qrd}p?Dn7@=E&h!C0G0bi{PZl&Z5V2oo~R~z0p~8C
z98X@k=p#ZKWgQ>w5qoV^NNuJ|;%RUhOsEBlMDws>b}Z!7(iJRfF<pOkrIbl}1#j*W
z9fga8o=Q)iH}EDCu|eDxKhg||a4CVSImDe#N1I6^u<?<MHYY`ei5!*h4|j4#q=G*O
z59o3Lv5nFeJKz~%I6A&8*;!tTvK9?bZrLvIJ3*II+fsjIxJ5!9xGwX~$AW2|DzjSa
z0y?GpWdW04S>rF16=;zV4jKT%7*=JMR13Q}aD+cIwMw!+FJ9;NL@m~@M6sPI5g9=1
z2eu-KK|XqIA`1fGm!}!%5Ec{;3htmTLe^MH-cACyO9o>lr)N0pYYF3w<^D}F+ImO1
zCMGx;4yXCyT3A&6j2R-lM%y$6Eq}!@hyR#c9^6KfTP_anXo##lN2dt!Yt^~tEi0${
zVE=i2l*zfR-dWg8F-}VJ4KC;5hE96!h20YyTzsjIW=lm_N1<FdCm52ECV7L1smu#}
zdENP~FU@KL=p_6_UX)EjeXdt#$yq0(qE85ut<TIezVw!1(n<Gwj$>od(4}HPPO+ib
zk4W-k8S>!a;0Uz?QmmAIEe_O@Oxr<TkUg-kGg?}k3%|I?f0eDh5XzEd3nF524Rlxr
zUD|WT9=hQaR8zlbYsAHypkgscjvl@t&0h@O%9JEuqCJqW_e$5g{<m0U%crAhcnorc
z-^MMl=#Ox%Il+gdX`cLu-|VQ-;DLhR)v2zH0QH5)?a|0E4XOvtrjN98D{+gqmkkCN
zfZ9H5_pL8iM+y||9#^~#Z^v7>RdFTH3AFC&ZjZ8=uJ|hYx!6Y<AzNKSzoQa)gKd<n
z&Sd~Yf+`bQw7R%16XBTQu%mQXF;j#E=ihjN2&#`oSp2Ss#n+aV(|S4PH&pR#j3AFM
zD(rWQ8|%s3B5H2TQL^+P`B&z^Bg0Ex_kpx*5^|>+qq2D(ovDpE!bZ5?h}q(9?EUHM
zW{^d8K*Oa)ITwoIK|v7Gh#@&xj^i=PvJs}!Te{r2UrTE`Br->M7M;Cq-7PFVLLP5q
zyYBaiy!O~zN#~~uH#UQ=@~$EFUOt<M?mqYl1Yvr*;xz)*r@lT_Xa3sWK{0sIHN~Xj
zDQyYC8D8>tZaqM$UVjbobpudLNoA3XPw@8FFMMcH)+LXi=`CuMot$3La%=tPB`7~D
zw~VfaAiAA3)5VIPW+chu{TiOLU^32NL}LHLKoCDkhLiMb)?mcVeH-IrD0O{mduLdG
zHQC9GhwYKO%Jy~20|_)Z@umFhXyirU_v%4v>-zKK&M9>v(I;Ts#GUrs^2wBWQ`pMa
z02{V@obR`(DQ5dmM*fU2tktN3C~RTuo{4U?MJoD7Zsg3(VNZSs^&ZTfL)>W{2J}5#
z(7HNksd~AIz?^95!uUjtB*(WXbV^TTwLoRRi?9J{Y$v+9t9>ILOJ7HQ66%2I9?xK8
z56SKe$Ue<G@4e2h7jDv8Fiwlao;W^1)9ZKxYYOxi^%sTT%6?Zq+U=7`(&0GF(;L@c
z)_kl#;*swm7n~?L%*0(H3fkmH4uwrT`+c};fns&)Mp1eEVo&;Rq8dl~P+a)byI+N0
z+P<ehn8lM#t;uoip>BLvdFeTZX;2{L$*DP}^1t9pUO6r%yl&<x^QR2Qp+IKu2#@CI
z<z$Mna(WO5F*XWdyX?EI`C&u(S@hTmL%TmqfT~{Day@|u!{_t;!?u20pse6g!o5ys
z$wlyvkp5=wIFH4&w}82-jnq`r2ZQ09a1SbZ1=Pi88Ep$ueimAt%+(cJFuv!{6$4g_
zWqrJge-g_7y*pwLl{GYdXa6{11hs=<Us?79jC6Mhn273Di>F*JG1Xu(ZG7d+RAPDM
z{qoV?{~B|9Fra)JKp?Z)sD#wd6^fe~5$>?poeMIFfegNyw|V07j{Df-jm|hvkJ_>1
z_tl|4igF>^w|&0<1ub;zgi>(J`dUQgD~mxV&0*u}(8?h!Yz;AB8<q(-Kl(^jQ`W$T
zju|PcF|qWAtNO-YWH$><T4B_Y=hHF^JNrWl_KNELxrE7b=P}XOJcGOAkhp_dO)aEG
zZgxYB_f@2RM02jY{M}TLG&JdBMy4d4&7w;?q=@+^1WU=Lb5{f*3pAD;E|EHOk*!><
zH|U3E>GIUiFoKT>Kvb;JehAbOQMWN>3^US=Spc#gs^GPAIYf-8NoYA7Cnf<0VJslx
zY!p^}9?o<3Uwk1t<<cSeN1Ud8&VFBgIBf@>R4Heynk<pTRc<_c)M6jWk1lvnJNtc7
z!`sq?e41`v$M;;)Q!P;qI-x&I@!sKBA_0RWG}35np5m(a)Qgmu^YPjZ<Me_*h$G=5
zkAz7qZr&K>^2^?A?h`irn@U>I6Mt|;7SQ~-$pkpSOm&b$Q$FB2>Qn7B(kU=)?4Bjz
zR=jFBiJZ12LbWHHE{hM_+lu6XlIbK;0$04D1c{39X{L@{rn9Ap-vhgV%aUA?#^&2M
zWjDi3Ees`bivG4^4uBc3;>VI!^GaWVWE9%gf=?ZeIE@b-MP}LyiMhDrE!B3=Vs3{N
z@UDdvu6Vp#!y(qagFKD=InsF)Cv}YwHbez@-XMMp;T0il6Mmr84?mcFa%chV%#W=j
zSOs?p{_JBYBc+4F5KMq3r{;_#Qy)?G&U!xuc5w%F_Fy8SaLXH~+lv-i=>qn2qaqT!
z?K*~=Wz61v?ZeL1_ZUFc-r5l4SyeH>{M|nS(ixA?f}s&CLV*H}=~fl+yAq4?dltU3
zi};(|FTMsL?BOVKe$36tn-HOL&`RWIeLv#J@PGe$M!&L!6~xn#F9LZ6;tentkxRg$
z@=xwuO}4rBa>~@;47^4wfam{x$d@4JX~H5mNMR$iIj=3C&jH+g#4g~s6j}k?S}wPA
zgjU?uVdu8pK8BJ(dPodr><&xb0~U#A01nRG;kVjo7~-l!sO@9$0Cydxt^1`H(7lhC
z{>=A7f~f(q3?N`as30mh#-ASv67L{@r-gxr6_yGPK2l&R7~o)`*_T;FD}gt|3==)b
z?OG;bg0~=;Z1nvU81EnhIW925jNkM<sXz_;MI-Q-i@Jc3|1p4=jQAn&nu1E@ZdgXP
z3gV|kBvukfBUaA_p>ycvo)sYT2}QO)?1k39JKRYb{_Qal+8a8eY9LC4v@+j9MsE?%
zQZrm(w0GMst#@V#&<d-X#t5^5a>eV7jT5p3=qQa6G89rej7M6asr7JnQ1^i;R=c~|
zDaWh!HZ@X@*~$(d*+&Rne;o}Mm0GxK+U-t=@LTZIPdTK!iJ!*7N$xoCKX#<}uuT~e
zo0q;kOd(mM(&J_e1)UaeJGR|LP6;u{ZW%YSascnglo{7RD$l)j4Fzr!jg#3jNrv{V
z940`87iM|1*mFtz1#t>vG!quUW7h84A6#L6bJvb#R2lQkqGM{CXpqeb`jG@hD@a+|
zF+W36kx*>mqd|v|Qb6L0F3F6~Mv;kVoz=92O~Y4OdSibi--fKBE8H6SjU5>nohhH!
zc<KqqjKe8`iYA)ClZTqZX6ic3YBc@j^~u{`I~>OTu`zUzL%vKtj=5rvtFL-@t9rXX
zxi^}#H;Q>Wx(53?yJZ7or_&j-8J+VO!g#tY{iJ%-cfQscb-8efWJ61=9Z?)(JST4m
z3!UIDX4@_8BbGJ>PN-+jE4WaQKomYzCUPqll0r7x5G1c^Ea6y@)4pKOos$>|sM<A8
z=e7|JG3nh;I6WApz4V)SBF?e<q)QU=x%c_KpaE2v6qX=c<P++%wTx*OhY>3oNpdj2
z?=9N;*hqbC7%Otkx)M*eJL;eqGKD<shSpO^jIySFC<F(=^m!?ITLnU`!jrYT`55b_
z&by_1<(?*-;O?d<v49su-s0CtSac6ef&IubiyLV+SvQl0C)uMYvUd8-6Lj;wZx`IW
zRyp1NRWcd0sSEtx*~ppATIvu;sXQ3|W@t3ltzGfYkSQ8$bM<rGjgK>x#b~FIqu6Ng
z#JUW3kE@DeH05`Ei0ew!=op|Nqi;fP@&<A=-B^hdBE)Iaf?6gQL+GQHHNh!!2r(qE
zM8*8x`;Jz;kOb~!GBMwi1ttv3xF4M?dfmc`U`nhYSw9;Z^mm8W!DL`D5iQ|BLL`(h
zNuC5+YGUvgu7peM0IO=2;BjlmOX#fPV;N^+$RG4*MeKAEWrAXZ2Y8Q0Z7w0;x!`&*
z%I==n&Kw^H^xnP}Q=9lxp_Ug@O}?B4Ow23@DETZFRj2mbt9U_hB_z{O0MS}p41+X(
zQ6wqzV*bcp{j#$YRhh^xPYDsVr--$3aKP_6g1MY=PN?k2O%qh62_KSq0H7%Cz|HV)
z0#O->a&L`NFT-i=lm$}AFLLeJNH--yeG$T}2?eI>8|b~0GxM+PiA=DCY?r<I@U@?b
znkH5D^M#N5zN9a?25Z=7l!?tsTYn`aB{SITCyMDfZV9Be^@i=nxq^=Va4d~Cz@uF9
z;QR%2Fzk0U5b9pOlqo+cio_4ZF--7BjtO}r76maR6ABaA6#3B$L!dka#0WUe=0(!P
zlw~3Di2g`LV_F>z2L)(8m0F+8713;vXYkJdcKIPa_LqgR*0sCqN9PYe^^XcC*Vmd0
zR)G``OL!w*;x%z0AQt`kWVdjcB(#N|C^DciZ8lI8Kx$p0Gw2aSG@Vqxp_oZNl4Ly9
zEz3C|B8*G3B-`GkL&01^O5*@I`?IzMYBspG=BFt5>t7Zd{k-m1cD}87m6#DmW<fwZ
zlr*&BvH(00HA}N@0I^>RffW;&fl*Y8tzHmyJcF-?tD@3VWa=ir1T_7fL+Qi5T+M~3
z<y!c@=w)M)4*IyHC2j;i(VUAE%Ro@&MbP9$kla(h=n$UDya*1NpfCxoaw1B}&|{ce
zZ`Y(%_Qyt&7at{esi0(>K)g*`Z_|{jQDid4AGzM&BsqM4I>wq(;%}jq!6D(6VX2Qw
zU3@uIM8OWmJw(N6e`B|h_;yKK^k4p8pCdR#Bs|RKlB9;?0?IU8evT?+qJ2a2zQgiP
zv=>7cAAWM$fV@t2CyvTb{OeB)9e^OUDJ1d4>^Ih_Njr6IQojr^y8SO0h$)ZKxTjj%
zHNL}pv95%VC2}G9;)KZ*hYU0NrQBj17MrTXX6gXo!<>Trm_DraSZB7bI+8Vs(u<_Z
zMz;*gw04%9jijjLy5L+gGj=AH0s*BVJ2jOR<a@i2#iJ$F*UHHYT4|(a5M$eSQOfsW
zr}Kx!70k8Th!rWO_r7@0el(Z;nkj*jJ(_U?ZDpMR^x}NL<4XIL_sh-ho$&GJaIJb8
zA;YZs7oVoR2<&p4!y{cSssq0C6D3Uzn)ryHJm!9H*Z3Nb|KGmZ+sCKb%FDd8^`E@!
zKN&gvI%pYh2Bv4nxJL8n5VMT9|5#9EMQYfrqR}6wUS{_PRrQkiraN~fnHR(1`8lL~
z0{RN2^UUyzvaatp+h)|XO2BqhBcz=d-lryf?tgTSMG%yxX|DH}du3?H*@ZDdvRWRR
z66lx`>X;EaHy|>c1UY*BV2;d?!_<`5o;W_WR}|Q&{LvE)koeg?!Ph>;cY2VkL-rQ`
zt9I;7Qo(B7G_~};&Mh1c@5$(Ni94uQ(0=|WNx#Gw#a*<`&4l1i3jEAp-KxPuo*$s#
zaEPb=AGJTX`3I0C_%uAOO!h*rjutAV?>^Qi5WAh{4+~){449u;ru|#Sf3!{f@TbUU
z6x6}D0bW!*YW(Lvc?5ilc1d4NeMT23@w_x`V4it`k<L;g8uARC6txrzt19t_p^7Ub
zWHu)%cOFwN@am#<hx+FD88+;JHe|oGwcPDJ7JPmfA#;i%{MKS6sjOr#KoN8J6zSxz
z2387v;77c5R7YjlcEqB~2RGb!H}6x+@a-W1DA)f6Q%yMni=ki(UC0pm+@0(WLvzpg
z+V&|Y^T<bcCykgNH#`V@H`bEG2dpg!`^W8v<jwtF@5g)na0(He3{1Y>PA@83VLpaG
zwtu?#^2N<&e6D11nm-k~ebbi5TU@~_=9A!yDA^v{X|Ott-X1(ovu07_o@Y6)_e9Re
zb4Q;>E*SitfBpGGzTEj-)EyFJ8H4UwnbpgA^LE_6&Is2X&GXgrp_N<u9(c4ji~|6F
zwz>**XHb5>Blyj3o<2wp6yzzJ6bI84AIK?P0S@KV7!D8F`0ndcce~krAIuow>LBEm
z>RhK500wL$`G>``Uv*-C#ASPzti;mtLjFNhX}{4_97AM5BaoW7`{7m(=%tS06OPNn
zzIo14(=qrq6dmjZ!?a6#ErX&cFj*y+*8udu{McWye!mMeMEr6-Lydt62TKoXp<;Rg
zBp+_z)xJPY9s;o5_msQ)*L6Te|FEk&pjzm!v}eB-(H@A@l;6u(!m4<TLd1M;s^>O{
zG@^ZWMk2zKt7wRwT8Jx2$lWvJ2-Txrjqt~kAQ>fq@fppIuh3vRkNb_dLwD~>j)Py0
zDZZY~?<9e}CI9oX>nzUaQT$DO^-@6)$44iQDu#wvAf2I9nerPI<)j7KsXsL$__;3<
z960tsc*JU#OA^5Oz9&nuMfT!~pmFsX#%@p1<b4Gx{12HaX+lvFuF^8)m1PO=O!{Nw
z+n7F3TW%f_mGXY01&>Q4EtE|-+BZ#2eddGq4~!VXY1-u!@X=@r3fjJ7POPk(V9>i@
zP|nyuN-7mv)T>pMR=#@!dz+jdBU3d;Lbd#xp6St0^38qgkq`}u9dWAyNb8u7m%;(M
zX?_FoxsHpZBqiZz=ea6U;x!D>_F0Ju^HkP?-IcNc65QtXfxg@a+0V%4u3^cGZBhrG
z1krvv&E7sX)~=LCw)ckgD`MH7b<w7WgGQz(r(B<3J@LM?QL0D85Kl%Y5I0RSb%AEj
zgQf785XVv@NETRD$%Sv(;S2v8Jv7r@NmrHsH+snM>k*1!tbwAa=#gNv_RDBEVkB5~
zW0CN^z&<-cz4cRzbeo@{1a*D(BBLu7U5^xogd$+{dn5r1Dz`d|=wE&CI^^cDR&gJ+
zwFpnpE|}yTds8qL*~REhl=bFxy*{Cvt0S@)Zh7SUY<`}x8xWuVGd-8LUj6EaeMAOU
zSG+=;UJpx~HeAm>bk0w4XM?ALJFV)pHa*>0Rl6@F{;PoM!8!w-lFu^lDfZ|)mCd=V
zxV%godg6HP6~t<!xvoVvPkObeezxs!T@OTlPq1WeIxN8*&96bcj^T)Ew8Djz-N8U!
z=K#!_v}yDHIq{LoqyD<qZ8U%Myb)zMegh0<9JHIctT5fZ^!;GsUXKN8hY@!Xo|>-S
z6#`CN>;t@!Qx%6xg*L?zT()V<5StU^cMP6WLRI0gQG)iQH=($?n!vF_??w~A;*zb(
znjXBk*IO8ykLKJ%Nk=zM9O8RQQ%zE%tLd~pdUJ2J!(YSg`JkK^Sl;-uTmSgRThXJ3
zaieaWd(>ZQJ<N;=$oy1r0r<C#`qm#!TqHeCueRzEKa}0?Ah9P@MP6^gF^HNe^Z%eK
zz}1t=yK0<j;=H|H6|!MMW`Ma66l1$-seS}i?5Ux)X0|O2Ra4lqGkdRdcT@COv){&5
zN8tLGs18+=*rGdBhU?2A>*wkr>o-TfKz^@u>rfr8rm<CZsEkxZ*U!;I*Ke)(eq;Eb
zV>nbsXv=O`8NEEc9b~3&IbZub=2U%7>qgDXk7mjH0u@hX@bKUDV7Ue~v(!_wBt*su
z2c?(GRLHUcM6@oQ!uIU!%3u0^k_w_^$nO@SLaaxjjn5OC-?PyZ3BCl!t=mbkQZbM-
zV%2^y5<t~70(}>IOIO}E8md_pSieI~G@j(cjwz>)6MLg0VP_^))u&HxA*XkeDByMM
zFYRShbU23wmeI6iW1R&i!L88(Kid?RJ~)RR1W&BQ^^b~k=4-H7A|A0Wn4r&h!6jOx
zXZQT}E2zhjioDVQ?H}4$XPo!vz;QKQnD>%n(|R@IY32YmKDrQ56?Y1?=$^6{9FDyc
zD(dT~{!&oXGn0|gOisaFBVLeCi~*dwc{qF)q?WuzhH&@jB|1%~;nJ+5vHdDrtz}jt
z%fgxp%S@0N*zxX4510|u&8fw6UOLmy58HB{i6en%x%Yq0I?4i)J+3|~=LJWsAjmuX
zg{ZtdEr^cVjgt*qVe|Ft@pHP{uh*URHg(tdb7+PGv&Y*>-!P#?16|oyeY3Obyqfh;
zT!uyTeUEMvT5qvI-8H}J-EMTawKkKNE|A3s=$G@y$?)VxD8S=oFKosrcSdK43yqaQ
zp{i@#Q-)7`m!_xeaR*O}5`tB)>IbFP2zf$LoQF77&Cf2sQ4%PmotV)bKCUvxyh}eZ
z2bKlDIm~GYB>D48pZPhxLU7e=>yf{4t&ZXNPjn778bb~$M<a<tF{Qcm{Zu!hfvXl@
zBt!<X+t%<{*pcq4-Zv*TPt9H#!@}%5K*a3|6*HLg^Xxj@i>=Ayor{PEEnd!HDubvV
z3ag-v2tUk^ViV50UK2iCji}~71Vuz#W;QKnkjfbTtO6azj80R`Ono9$>bvnj@8Q0=
zQvE%{zJ#sO@X09OgEWS0tqDxBSG8%#&{6tEx^B^L$5oQdzS9pfiBy^Naj51U?l;d_
zEYY(cVHww;nZtKcURCGe@B;mwr#s~G)2ZfyC!sU$1O&YtyzHtyVREKSQ;Fa-ZUmgC
zKseEXQ_13g`7gTcIJ^|8ER43~F}JfF+IW@~#}NRv%4vvM9!G&K&J;IBcpRCVePV<7
zTVlrPvLE2LATl4dvt9{N-BQ+ds$w~4yl)H{U^nrNijnFxOKCK<y9Mc-9q*H)l%shD
z9UWfVUIZeK*f){V2|$<6X{h40fx%#QJd<{n<I+~0>SU3;@Hr{s%IutYivG-9T-&6_
zk*xZ&J#4PO`=*}L5K3fguac3%NJp4`96)FLvwU)vj*7N=PHtX4)@~+Q46q70-Rw)_
z=x!BF*u1SogR|Oa(!j?t4-HZytxVo$N@$&YuN9mtZ$E>Cv#eSY-{`i|W2v9sW(Zs6
z+$`*Ugo}y#jmBF@VM6CrRfc<<WHK-nNToUOMHAVzPpKQ$oVfttf6w^V6(4&@9EC^+
zFSIuDK@2%Rd7$z90;I4m3O_jkHI-MD*8|FK`2r`iKbZcSP41I|%gF+u=2>)ja)=&M
z;lof-8n~XN!?J^U<EQ0fgs|4!NkI48X#Z4T4!U6`&UJp-)Aw9Ys+l^wT=-**6sjYN
z$ioF1V>i$}$_iF+5nQif|0|!Q=*Ztf-E+MG&&6h)X?@K5fRcTw`8IXP_4UDME5F;y
znbgFYlzr3oma9~fQF=3JOR;tg$KNhrbOYpj=&cu~C)+TvP76~+;xp5%^5f1nF=rwK
zpMgGVQNIe*<8J3Np)sXyfV=(Z;9IQp8%Q)5^jB<~VY<;O;*uyrcjD(}CV1<_$$V>-
zgR|ja>s1|#J9H;Gp8mzpiCOaKjK+o6!3Aen+ins{u$lizO`rut;z`>znm5q4vObta
zEhULieA2R&(jRd~QGaB5s<mmfBi7EB0q@ZaQM*%3Ws4PMaEDl`SY3N>fxMbe8bLU&
z&I*-ukaRozD=Z-nmI5b9XlH8S4mgC0Y<52O0Edby8@;djo9|ENb)zP_;-#;nhgmr3
zB`pt8qlM#%&E3?g2X3fI^Y*V`M7z^}2}X?n`5I-LiR)5j>P$CI@6k8t!QPti%=C%4
zW?!Y&_zzLiV1ZK3`;RDbo|V=}O@SQ##}mN~c6d<K8#0p6e`#V43vwbiMq`_Ve+DP7
z;HM01?$ns2yqb6h@yXQ`;xG$P4Yz~q8=#<?;h}~VLP?V+Ca-=z@qNUkm2;-7!YKV(
zMGV=8;}5lq^V5-`Y{|QQ>5Ucre-b7ZksBBr`I0>1FA6521X%p>vY+kGHir!I3?x=V
zY)-xJjgM0|5_8q3?Wnl&m7PN}aC#DDm|%-tAZ_a@gq}bCYYt+i;=kn}ex}5=w*;>J
zf6GB!$$8Y98au!7cx%{)G29G1HoTsf{WoF4Xn^&9)+J&Q-0r|(B|HB`l&p-{B%}VP
zC<)`9KPN<paDG!j`o8MQ#T?;5Z<RyfW?VL{SL;NT*o`3qpI4iMEo&B{R5N|8M1Xp9
zq*R@MzZceG9Fikb5WU$(0Qe%i|Mm<??X3zb{eu$bvwrp(By^d&@4vB#=4&VK-bDE$
zv$1)@>MYdatWeG!soeQan4msdr<tW8C80Xn+LTP0#c?<|TI4mn^`It*<aD*<%+^-y
zoI}-(mO!44AWnKIMsPD-yNm!Bd!=Q?F%P4sto=61Cu{U$tIbAPKl4sD<h}W)+obrH
z|8n6Of{HwCB6a?fT(zqeNSzw*C)S?`sp7%x-4)TA7g?Wo?jp%sVK<TqUID9(TFCAF
zkE-TNv45N%*j*>xvYN_)O&|9!J>*2MvPaJ5uaf2M#fqv9)n(?dl6S8#_%zgrz0B9k
zCFkmR>kt!KGELM(>kD16P?IN&V*A5(tp0Pbs7I@**$^rAcfN@!`_RKlL}$p*<3wpD
zi6)OhV+&^YYOg(BKC4C0Eo*H4&9~jcpPU=F`UH&3CtFs{8j^ZUdasjAPP_eo%hpaG
z{csNLyPnkrB{JkQ5I@4ieZW6Y&E!LpQSBB;l5Pl$MbH392-OUfI^0gZQEZ07jff=l
z5oO_}m<$Im%<s%XZ<c=-Xwxo~sEO_&*;O&oZU{7_YPyXB=`O9Rh%4(a28t~V#eV%6
z^bn1MS#-Gr4D^Hk>1x$jZlmPa+)(as|LY5z&J5|Y<D&>UM^*twm}&>vtjG2=G*`9w
zW~Jo%vX`&SxP*gfRrEvBS~KAZ`F&8Qq8is^kKnME{#o|sqMh$ItK!**nZ{a6O~f+0
zgJWTti)>R3^vF*0Kg;uYD`0~vR=TLwzXD}fhQ7Q;c)d}V7{$ttGNIhsDQIeAE4?TH
z49Pr{6>bHYb|f2zS*vUA@HG+kX}<t(4PAhLtt#`CIb>P^bKYB@;H5(8(3=Iz#mJET
z5cSe1;-mWwWl&u`horqbHb~Mq-o^nhc=kt{4OP*76*^@vwD9c7?qlwrx_J89??(s*
z<C0WZ%QgD`wlwQ&f7_BwwV4%Iof_*WQRcYM&FBp0GozjEHimh}@6RFjSF&`^t>5MH
z#>KSNb-CEJBQu|^f37sARJ2T8juVzFWP`sGa@WYxFBU#Ob-gR^qYqnVV2pQpp3g0P
zcy~^vXdg-MkQX-+XmTNO;Du_gxT^?7p9@N8Hd}F@D>H%`N_&FF#(64(#lfytcq|*r
z8-xhY%;!~IFm$`2qH0_lE&hOfUD7ur+{(XUrfy~XI9*8^QF~(y$H%{);RDhIP5ySf
zQp(jm>^H6|+lj)IP8)kSI1i4Rq!iIwFfZ`sF%qoSm;<j;FRU8yeW!Ea)!FR+22j{I
zlhURy8cc=Us0vJ-WINz%cdQ*OwQnr#&EeN#9P_ExLB#r)k3mO@hz-w$q1?OWn4DN}
zm_PPhe)qcI0#fV_0HG7j^L4aYv0F}bnoTZ^`57_|2g2Gc!95om6M5i;F0WTU@bC&i
z<g#6U&sP<xVq%*)mpb|%o+_+KOk9MFW=x=S&QmLhPF9bM*^*2N|Hxk>VC!?>q=4hB
z2raG_SMMjI6u)8F7}Z-OeC6lpZ#wVjIqJTrYP`f?GL~#L)`hdm0|BF1q-cV+i8cNw
zrp#leR=@<lXrr~DD!wH1J^VK${vb*}9S}^1-O>RBe@G0ZWNiZ0->yp5nO|R7SmXm}
zP9W#q<RwZZk}R>-j9hl}Byy}+pzD-KJ-`(Oqd*Of^u%lj<lX}f(a64Rw4Y%65Vxys
zHLGmZD{VE4>$fN%<O=L>GloOIdclm^*(qO-aTTd8wHsntPLw8GP$@MNzpMv@X2<9b
z3<y}qs}Kf%hnopj#m0%#86pkz>wr{LTy6`40JL$=+Kak;A3fccM%pNO*UV%9(PLLf
zncw|1qRfCS;sPi=YmwY@KB*|a_q>LaRbT^Zucy5ED@62C5M-sdKy0)I3TM@|_ARP>
zGdT!J5L+v=l~&lvNSqFXd5@;9na&18(BhLBg)|zHH#QV9jQ()YVSn&OEBrBo&JMzE
zulX-=T)|x28g)GbKJWrg;mJlE7n1WuV%IOtW0`ncFxh1Cx@51nwQrMX$&OxpF)S1S
zfUjH!U5k$95NEzYy_|VnWX-Rm8q^X@u`^jZg~>k!mtC;wS96BPfWe3)gZ?*7jn!c(
zjGkyZ_m^i`;B@V#CaMJFUpO^z!9|(S$|+5YXtafJZ;I@T5J9X86<S26&9;k$mclii
zhRTC@<UhU$7*ne#yr>f#`WxiZ&R`E<ydmO+?tiAKwE+GuvfZTMblNS}AJPE~+$}6a
zYW6tg2L&+}4)t^YK~o!6(^L-NH*K-Pu{>2+PtGAYYbMhJQF52?2S(z9dfEVq)>U6h
zsRtk7JD6mChcQ|M%ZDow|0kMyJ>a&v`UIIRhX~uph?bKnJrLR_3^-qikpb0*{F6D*
zuwO8Y0GAZE95pTw4jc}j2VFfqKOe9;Rs!!A)gd{aOfT3*v|c>)UX~&Q?2>+2P>skb
z97#Cm2_2D7qJ2F%cJFYSPz~xK115L5hTLTS2PD63ayi;GU?_vZ89e1lk<)rKbr`t$
z@Ba~|PK8gtS_j3Vo#t?1x9a^RDS(##OKu3KFMXa?@r<YB!lJ>aGK&x&)GW+;OJP|y
z2<cs@#KD0G)cQq5m5x_CGxNofkd_48km|H3X>ZoW;sp_l{dYS3AXu8jag(o3M7cIs
z3cndGq#THrXmcqqIdtfK7(Gx{mclntuOp4|{+~EC(DGh}CplJhZn77Rwv>Kh;=wFf
z;jmr60gWje>X($G>_%~0I1R0Ea$O5aNu;hx)MW+P(ai42J%J1HD1t*SZ3!0$!Vou4
z^5uqi1jep#v0X_7VYgavPwX9uzCQ;QVhVu_vhHV@iKZZjY&_Q-sV3bEQ(`t}U^x^~
z(Zty`G|mnLV4|-Ih;88~S}iy$9ZF?G*|EMg7N&U~bx{16Y9@8EM`cm~_-;|(2i-*@
zu<}tO7gAGCwvQ<^pfJ{&2*S`9w$swTMh2#$>;wwm4g?`ajc!5$S`<~*1Im%$4b8#2
z1ue&tN&+qZSky!=Sx~29i;>1FftEKOhPD{|y}~F8H2J4%k(RQ}2#omnOlJU;FsX#5
zA&<gazBU{-Wu!0eZBNVqy|SD-d6<G~+dMinIlYW`GF5_ogTS?^B)@-{!qu|M#fA(e
zNDv1lOhveX3+tQQDNU;0M+S+M$_tg)2iTBIiA<uq&^M)ISIrAw!iK|^!D4WxA>l&T
z+U)5VLY5BuTP&jBPDDA-8;lNN<Ix;hzi1*R9I=t{oJf3%cNDMOQPHI-o!Q?vJVR(%
zfyrS;6vM!b=_@~pV-u9*H+}wz!Qylm2tx=4m83FbC`|l1lM7P{9bag)V`NL74d0gp
zE=->C{{U1kj(M)qbT4-5)t;0~!C9a9ar(lB0$Vx4oAB0Oho)gN;Q*{CVEVkzcB3WZ
zIC_9n5J?6FH|ETJOa{=99uq>@1^}<XeYLjHbO~&_jX+U&nyfquM>Q&dUpyIaLw(}S
zCbYvLP>20Y9K%JcrL``kELcE+F@Ke^u&M|n7R^#Xn845o6ISJ>vYkJRw3*K1Rhx4Y
z(WfDN)7iXPYsq6+kmeUiX>BuQBC6A4mkHP6_LXqqMXHW2)>m=Hyx~5eNt8sU4>nFJ
z=pP#CEXq(Sa`m31Nwzy8#ZqBtZrWsRN?%y-2(YxVF`!}U2yby^f%@ZHBTpe*tP=#+
zGz9nWC>G)_CnaP@_T$+p3hy{I&mR_`!a0R}fPWYb(CAP75__wr#)?#-iIu5OE9brq
zmf?`RihcXMgyRrocTv@O(PC*31J(!Sv1%1p0xJn;9^)v~aE!a?*d<}QM==B<h_~IO
zGc8naF*wkJEB`&=Ji;O%jM|>fAV*MX^i*&2U9R1w6fR}$j5b4Gw`d%hglX`;Vaa<z
z^L>9Ihi}7?PB(_Wf*G{<=Y}xbt`-;sOw1+AI-M2R`_fW>U-z{9KzP%9W}%FOc=6n{
z(uW!Cev1*kE@1HvB!R}FZmJ1rTmfmp!V#3U<3i7j5IEwQqb>YCFxDM76IYR~=)_ou
zQj~D_Pwv!IL&|6j$+lF9eU$c-E+4ItouiIdVP6#`D?TP0^YLb2TUR%z(Szs7FA2Z9
z3=O+9&3pP+7P~*xd_hENhdo4FyB85)s6DjJ!{w0h_5eb#6X+ypQBoAPI~?SQ7Kd4^
zH?>7;@U0_uS0YCy>QwfDN8Bk*w4SknF-{9Fkyt_{s5anSiAWhgQ7ib=iHBA&6!W4#
z^A*wj(yvi-5u$A@wl2oKr9IfrhNnR~5RsIgfjVfN0EOD$qkbDG+9YaRWw57F^p!TS
zSuAf{K!7swVmbw*)f8v#HaAqC;xiDK{kS1;`AhpfETS2LoygVR@+}FA%mMvDgmgJ!
zk1|yKKXpz%IUgPwo*ABxHBK2XkLO3K$JXI;lb5uMW?A}~2rL-p#b}@TsKAo41VhS^
zG{A~L3{l-&^OPd%=R<6Lgr0F<hB)KU6*foE1(fv}5x!#b$cbe8Wz&8j8=CpQp%)eg
zTF5AH*qkRvz@61!Btr3v<4OHy>{(KA0s)>S$>oFTaA8;*Vz2+^s{KXV14Z1|u#hn;
z3*=WRu^6G7Yi)PPhD%q&Hk6A{v8kE{<{Bsr%9|k6T2Q~}tjq$T>DNI#xgBr<ed{~<
z?(P;OfL$_N;eybRAXlY6QfV6Wtj+-Jxa)T0kwkC4Y2A%BAzC3fMnLS9^_*DnhUk3f
zHzE|O0IM`sHHf+lQL6@L^dsUL43gSty7V*rPlk7xC8|#-9I@K&yKky`WF7hay)c_;
zkW)solEf9Fi&APVQT2=;kRr+<G4f;7t$rS@kpY>n&UFB>8W;-w?N_5y0k^i^07=u4
zhMODpH1cz3BhSb%d^pTxYNEWMPl?DCl8(gwAJ8z@qL}YaZJAVbS!5zxUnv+1^5m#+
zQ3U}AXBVUjgcAtoaZ$NG8;8koozd0dkFHI$4IZzAYN&+YPrMI^-2>wj?-g6*1SCQ)
z_$i2J!Ud_=s`OcyL^-DLvcS$u=n59fNc1QUL<+ly@sBolE&*DrU4t3e+9tejP){@b
z!&Dj*2imBT%=U+IJ3Qk6Ekd@|DoKIGV@XjBH!2H@cm>W7Hjv89JFkYFm_&n;qG3_|
z)u)>gW^t{97qu_4bt((&1mdV|+hn%KFMvIjS4b-N?)WBnN8uK03X=K|>tmS!1Dz2}
zCi#Q`eAbMrUt?pM_lNI0Rwx2zs_huvnIg4xUO^H;t|>H5uNY(DP8p8IaF$g#EKPG|
z(#?)&NFpv6giCFoXO<k{i&6|O5I*wX@^FY#n76d@%vf4wbd8fhh*cTHJGL!Tj~ZI8
zUuE#JscA4(L&3Z>FM`3NZ#!ZN;&=bQ1gl948rBfSTTu)J@gN&)#MKEEtDRLL`3hip
zH{2$w&Y?PuHpBnk1wnAIXvkHFEZfY-R`Sh}H^77j-kz25Mj9PW(BoqaK<@j`TX6Pz
zHko`~T=W>CfK!@lMi^6bvueAVv|J2bl<$}z9#A?(H*1b&`e+(vxm59m&LYu~NXYa(
zI`q7#x$c@gBRRhsEUX-l!FQk-oB`sorET+mfRlLI3@~f%rH>(ot;C2_L~YegH=ps`
zL1Y{VBB~vV{oiVT-eM1Kja=mrCG#Mo4za{$vT{*7@{+R5eJS$Lh|)}$o(=2A7_QVt
z>udKV{z7%))3BCDS6o`9$+|#}$vvMhVnbG1e?^wRr{o1^W{?)WvKILtZux0|+6he_
z`_2`PqM<HQ^UObUc(FA*@(Me;s**T;p=T~&+-D7=`O5Oq>QrrntynAqS)%X3{XjF5
zdzYo?y9r>5k>abxp;FF+J;<Yv!X7jH37c^ixj2$T0f(M|53RyN=F^qD1J;_ilBpje
zRG(_wZw0K@9CxhyR}h%^X{Q<{UpIv;$JnqLNf39sk(<z!xjOn|O}92M-di2$RgIH8
z%5dwyg4%mlufS6`JPr8FGX0E{a?mQYsVRt+xspXQ5AW|no_vgg|3PQt_ARhr!$@r)
z=5d7D+Siyk`wl7;jx8RGIJ#n<zYgiX>gCU}!VZnl<-y#>0Bfv*O>0!X+Y73R|9c9_
zDp{LZiD$_C?{bz|=IpX#2j-mBFYCNTcep|#BNX?GO7S-PZ4;BK#ymnG?eY7F>$`?}
zOb_xl!K4SDf80?#y8qc7WyY_To*FVhEbx`+SqPMt(gWVO{Dv(ePY@I}YeQ%9NO_pv
z6+Eh!rFHUZjw?9*pa}KD9cwXq6I|2om{*t*Ffqrmk;kgf!_=TG^sI2YF)D`*GVO+H
zy8hn^SsD#aNcUCm4OZ9fVEPif&i@OzJ^G*EHtWB@ZHT;o!0lW)^c92<T+=SW1#iXG
z5vF>(f}}4+c4rGDWi;-Cd~8j9vZPKssj{|LJ8f)T?a(xpoF&hog|?dcaGJ_RU^o^o
zsz+DBcf~%TL*g>_PfqM$816n!YworAm`ysxRYa5Npw8X+a*ba`)>Rx8k9~E$8Jxcc
zzn-AqrSpcoZtHqGves!YYOloB>v}mZYI%}{TO+pr{%-$9cs^a22RL4?P4NCe{B7>{
zi&m<G|N5ndrGxvi@~;(OGbPL%1<mz--)#sZU+fTyDXTw6iU$P?{22WsV#a>91mL5+
zjB*rlT-C<B8!OPXIQY?NOWAA?7MfV@e`QA2#JvC7|4KI+``!Titnzys6{aQ!zYFaX
z_TkUzt~E>H%{tKa?jT{$TWLYYM0T|^7+%5f)htvo6QldEP$E6O6_g+ekNX4W@L;6U
zIKd6q{Uu{0x2cWNxkA7t5(;{~WWxyP05K;5Ipxg}QT%?}*oTvx5$U8cA3&BDPpUy*
z?^vw!na}ykfpY%`Oq{7WGY5Ikv8hq|3*1eCAoIWL49c*+>kNd9&Z2X|NsYei3`U0*
z+t*s&vP`&ca-UnRhdBSKGr)zUqjhir56VByoMH-Ug{=vtYvb^CKgoo3@8KAXS#<G_
z5kYGWqS!X-Znq(n$sPZLh+h}$3$%Vhr0kEcSEc#45w;3F8Xh@1;e|_uu0%vB!vEs!
z#x14Tgzh)T5&;A4=t6I{n#LWmvX<c*j5I;8DOr*gD<$Wiqw;P4og+Vjmg0DTh^440
zEe$tP3Q??8T4K?RIrzc1b&S>j^Hg7hhhGQvbq@c`xJ0inuTH=@4fHnfaJ!_KieIy1
z*Vr<oNS(^`-yZT<XCsii7Y=OuKOXXGfy4)7WWU8e$`BKj|34))C)3ae8azjBiiym8
zZ3p4$g&X}-Gvj!j3!;i6I}b4+yy<l_2OSx~<Lh5XPULp~LW@4zg;5A7@;*sN=h_1j
zej2NJ4V(Fy<O%~~LXn|-OmIoprS>GeieVYc4Zy^*b~|*?>k@Y}XPP-WT^0th)-RT;
zZN`zRI6B#{*Q$+4t8)!Hgi&=Emkk5Hw5rsNeQkfyx{*kjcq85=3>_Hj`4{=i(#q16
z*dKr!8i#oO5^APE6TTRWfNs_%Uzl~XI*`CzKF*+>A2;t!(36VFIG+u3UpS<Bn?gKk
zZ><JK{w%32j~y&;j&X~@_x#f`dr+f#$BRwd;gjj#1)n90vAOg2(#Apl7Z6hx_Yg+J
z1=O(-WxSC*ps_%MxJ?K3cvkfur|-KxL+(G$GERSgVqtZFKGQ_@ZUnGsZ+pCDt@t;=
z7<}Kr5y{;L=2B0m%PW+2vhIMEXB&3ti~q_C4O{MHwo7%Z9)DA{%SZcYRc=}6j~}0%
z>l2GMPfTm;VWhBImsU3HS+%|ScZyd!R&VRi<W_8_-6w$mxAmGc-Jv}9wh)c_TY>CD
z@@&HaRzvy8?@9lYjJs0r>1&3Qzg89kOW@<}$cu{oSh|1T&THA(n1k6BdhVpJr^9e)
z7;!(`9^nwHx3DcEZ4PmXS^3Heur;VAT$@mDSfWiV0}bIHFe^6IhT<^fz(x~?y-{;A
z)0fmjS>O_lqgA9C@M~t6>179Y@RoU#hH3Pf$99%#I-Dxq9f9lGb2)$gC2H*%W-Zv7
z09pFHpiq^nVhP&W`g<h{XW`9k$w8gU4L57oWJ*SCtbvjib^#l1oux%5L=rY|LQ}Qo
zjWM-pdedgX1=HkfxNA~XfQeq#@ZBZL)sL#N+elD9%E_5=0pm@@gc=8-ywgy@&2|vq
z7H?<E<(o}M09Br+s?>Z|)(vSwXse4|X*0L8b!Ts~_Ev|a?7MxcN=z>D<I<bmfcriZ
z+n`8%V&jgfi5}XjLBp@#_@y1I=zdSr{Tsm#;cf5NQzex#GaQ4<Uh~Ac5{{X?hvja5
zGl3910Ub3qg0SmCL~5urN@@;&o{F$#atJ?ueO&^L68Q7o`c2nu9W8*n-4f(}d2}&e
z(45tHVK=jkx1Fjh>WI9h)&#KjOvVKzwsoGzq-MGcvIBR0_*8-uZyv_o{3lccFFLEg
zC=BH*CkOi_!%r<WN)4Mzp2gAGrj0(@6G{3RWy`=TqoK6RR(l;dUDg2_Y&K_!%5|O8
z_nM(H=t5~<)7jpQ!nLw_G7p_i+ZxVkP>V1fnX^z^o6DeuYJDhXCjL7mS|W?SgD!~{
zHY$-r);WuU2RP1>HShV{c>QBe_KvaTwcz_jsaiyH2W8wC;&g|aHL3_FsAv{Z2XlA@
zS-2VDG%z**TirywDBKKhO^_RaJ?iY7Xi>62)hY>aGx(Jx(tD@#?vNzXIAw*NB(efu
ztk%#Z3CN19kww|0h%k#JUMHJp<lMCi`~AHn&(y@M^nF_RF2|vWh+TM6Lrm=8;eoX$
z(Y*#{*1G;B0n{bCsJ$9sZd*=sCOEv<yD#pC?XFzb-O{%u67#NH(8JX(>k?M<toylX
z_8>~E=q0v2gfD#zJQyW#w8x}JF%~>45X}+C$XXBUauwd>;jNw3rpdvK>EXR!*ofde
zcci^fM6a1;SB)NBiXJU~q#b2j?wI;Zsf7YKBG9r~o`2#)wdq#R@rEg*edg?4{*>0@
z^u8)Tx+Z7SS47L`>i62!Sd+E*a&Qez@04nKQ;4=Q6P)Nd@A4Rv^L<FoCK_a5$@p2+
zo@DE;NcpK=OSQIW1LP~kSsSAoigo`fH6MOFmT1hPBQuj_F_<VH{8*|5O=xu%Z~r2T
zk#IlunG&$q60pd!{}F(Wn@_V&++eE<&V0NCT3D4sKDL9oB|qd&Q%PT%eB-ev6e4uM
zJS>vgG3;p)DVNRB9J79D*ahD^3SOh79L>QN--PMAdse4L+RARvG-HD4FxNT?^wrcn
z!tl&T84CeAKTUmvNFGkN(WF!Za;1MXc~}okv?3yHsjr3FLJcv!uZI<8E}pc{AQ^hU
z9`k?k^_Ed>Hc`7URG`I6ai_Su6qgn)?(XizHKoPfA$W1O;981XaCdjt00}2g-*e77
z-=FWtJ<MEt&#VFNtZd(J)>O1|wiTAQ`_N9L>f0inmSOk}bn9>j#;Z^T;f=|4Kc@OX
zGo}G6HVsdMrucjez-qb5HEQ{m`>bo~tV3mK$eO6gtM@Z%B7#4u1HaVW_5R(dT%9!`
z5li^#e7F=in1fC__zLBndk-qsHjkLOCKq}ZS#TuKsupK`-N%%k;n()tf>S$o4SS&I
zI<)>b80~|q)VBsEJx>C7BN_Shu`%^ez_*r?`?9sg)xXoJ_d{)HtqN1*&}sVSTrQb^
zU?d{Q;X}}AWHuk4#F*<3%ck=wHnzm3sD<U&{uoxX_n~H)B1?Sc;7JhKw#3dKJYF@|
zJ!vZNAOFNKMeL4_+tAk*J(ko^x;l!l4epF#9Jfd1R{KU{oK{ECQLl2<8b)+ZreG|-
z%qRYvmJKsFKDw%c_-j&DHoN*vn{CxQf(Y=}@dH%%1be5=6xsEZzwzT6nkLL;=o0&;
z4`&kCKJ(;NefRz?a}}`z(S0iaQ(d-3CV??Vx-w-Tezc~~c|#j5)U9gZ>AhsPOiX{(
z27m}@&mVI<|FwvuCy<;44~Yr!tYtJ51pGy}%4j9ZOfs4&QNo?sM4)8dWA&DG>Pt8X
zkke7Bu}LmCtfD?T5_1i&XLN=7{S*L=4HJL@0wNUyI)N=C>j0|x<>~C_kJ(0_Ct6(Z
zk8g6U5Rp=0PdWJOq7x^~FGAOQAD>rS!pPf$TjDBCUtsG<iWuKf>S)V4=5CrR+(UO7
ziUvMVWi5<SU0Ks>^AdQ_WwB7d@+M@}1V^n@dXl+egNm*<1-KkGx@qX9X#+_uvbm`6
z-*mmRF>;W@-6yl~mg~U6Es?RaB4FZ*BAW)tZZ*1|^c^~Tb!utX=D4Q~HU{i`&jOv)
z)QTq#;eUnvTK|~y(UTDA?&s#~+lIB*-3B2!t!&Vyvk(IV2d>S`pLqjoe<ZFlIOUs&
zs*JlwqP6=5G&nPPt>iMe3SF*Try9IQbUAc>h~2CZu2qlAZv7y@Zqdm3_>FGVLXED;
zC1X@dW@mX13CF1pjHx_q!nA_$i8F@kOD1idY%9+_*5=^@eZP!bLc35g;=Qi7w;?L2
zr;VXv5@DfXdVQ%%dc;{$smf9BWZVk9yM&0lK&bBg#VKy|C~<HBU>8Dia4*Pa9o2-H
zwdzgku|65*Vk~Xxv2a5b0T#%`FKl^R=CL`VcA%n4Ium>RGl05W$XEyi%pb`6GWnUU
z(SMOvs*D99SvUN5Z6Ym$^$hzf`6J?(5Ux_onA2mrBbA-Xc(^P5(xC_I7OHrI!@g_@
zCJX8M`5|@Q8$PG$*9ld3?FZAn2=M4AHr>kKqe`$Sfm*lyE~CyDXaC!?$5mfzJiv7P
z;0E9f`(Vquf>$6n8pHbM<fIgG{UjoTmxG%aG3kU9@=0tp9M6B97CIw^%#El<O#0`F
z+BW|+(a(}-3}X_Ne@r#6tKbVaxrRwZ^!R=F){i?9aDw#}95^8k9*{=HaiS%|XSz6^
ztbIk(kvC5^i^DI*B-kh@cz5b~mW1!P?8GEgq(`^dQ_XK4RD677P^4;UiY8aBP)g*Y
ztf{j5@XJ%{T=e<-rQLpA(ZjDD1zZON3F03UZ`z8`#jIarsa`B01o0yLMi*NkH-h6x
z6zrI#aLTJ9UWCA1*%>4X?l&sLKmPFN{bMplUZF&Mr-hbp_ZmyPKo-71-R<9je-KjO
z8~pQY<`9B*96w2ZcvtF}b$0c$j;z)>wHrJsa5{@rXkf-H_i6UC@eIwvt_9BOB53PR
zLUZT#5aIl70~jkNFI^{Ud$3@S|5F^5!L-e%&x2qqk|yy0{y@=}$mLvgcr9l1kjEQY
z3DTj+*YH&F|6O>Qicga#g&<^Z=?8i(Vm?Jg`}^kjVL^K_MxXxat|L{tg0ff8%S^GT
zpERcNGJx+a*pQekS$m@)W9*YnBnoO#x_DmEL?sk4`8s2rIvY@A8*T>rhm4?A4BU+P
z`tQ7yhVH>?(zB!#Vgus57-<WGD`84lsjwcuy)m_*3rnN+q27!)>tMu@j+YuFSkV6|
zaEoJsLgLibF*c*ukwsbiOv8C@^!u{|N0-jG&G{LSG0(P0yHq}sOa+$J=5Ka+iNOED
zw4B&##b85U++LW?%a~M2J=59Mzjzd2y#%h!aeh1$ccWlVAscUl{d)E41W{|l_gr&2
zfE}^&y?C0#n<tUM=ElFkDC26LlZ;|4k1e6BFRkCYy4VU9uD22`#>6<_5#TbIrO7hN
zV6byT=tu3T$kWXrXic}O^HD5RnID{P#(#7iB!0n@x50~)-R11EmAHYVFm>G>`ibd#
z^+jORH2=dqCdt2;?D^J~v)KuV>lb88a>nXepK$q^Tm9QTOkYxK<If1bK#vr-t)cAe
z<GeyPe%MWu1fOpj$h*R0%M7(4p-{L1{?Zf+H7HY|^6pGXWWn>lA6`y6d|io$;?JO6
zqHkl(s60qEH*31f+s$$iWR)e*oRGw9>SI2VV!cn`mwZKnFeBr;1wC^zLcmIG-AM#0
z@NQg%%wzY#G%P&b-RIPFfJ2yq9V%okEwrz%V!=I<wEb>%i!LOD?X3NURU6BstxP+k
zXb`h@?70e<Ize9A@cD0F421YR(NNg0PhPAFH<^R=_+`>WKl(fNy)uQBKldkk^d!zC
zxtJo4+6o*7S$Zhv+T6Er-SfXu%7Xkn%tp#u1|K|ja)n9i8-$fJRZL=O;cp!|t4aJ@
zJ~8t2&IUKP)-7Of9ZBe~$}u1Q<3n|Ex2XNpJ6jp`m9na8g}e?+t4WR*&N$n^3P<PK
z?#_v|wDxwn3AD6K>ELa=E34cotKg($Td@#0*MlFNH$f2%zWJG~6@IYa!-O3YulLiH
z)TIGxhZo3MR84e^`(g6J%a8*pE>4~G3?m@t%^!uY!Cni8s}-)%hlenjS0ZheSsl9S
zSk|nK$I%!>MLE00`E8y+#Cu(x`I;CZoV>}FGwKe41yf2+F0JqTE=0&29JRgiSm{qp
zzt%xQJESkKd<8<SF!`URO=qksMY;(c|3dn_D|@MgycU?YOq2$G?_9`no=v}$X#@{x
zqlwz^4{3-1lqt%IGNT&e28H<F?($s77iYcowJbY|IR8+@l-0u*W1x|FAsDNaf1cBt
z|KxaH=MUAhGN_+3-#f>QDW>t>t9YD0+|s)>V%m*d^+4`X5qUW3z+7#6iWHy9>FHa=
zeCo+))RwzGqr=;!)s(gx>)|0xjy-jfzCYbbgeMcqwZHQjE{YgBPWFS&moTd^TKOAA
zCiL{2KxMnsLx+&lj7Jp1$>p^@DhKQATx|Xt_(y9A)s}f-9PB0DarriQVE40^yj~0{
zXha~L&Lu;eE}rQcv+}Rht3?PFm^oav_O!wXcc*p#-B9KoW1@|$YLq%1D6EG3Jxwbw
zZD#)43%}uTtbeB8xXFz}nTGi*lgt-Cm3*1Gm;9&2$hs8Ou}}A`oo*q-r_sHmZK2`j
zH7zcU^rQu^dU8}%Oi0+LS{7yIdh>V6OlZxShloE`np}!Or@SBYL3g*gUEW@^){R?B
z-nSR^yspLQB7e5t`&0xgMIY^2K%f0r+FRS(Wk%v~C+8+Zk09Qs^~%0`%VDv0(T@X5
zF0~H+W#mmF%zQ4n6TL1C8qrEebok*ksYOzIF`bdRwc5X@#VWmLN{kv=i4@J$&lYre
zMB4ay(W+$v4F#35Au6Z*BBdI7TG6_ow0I3W?gTvxUnO-kpiMU{<)Fcw(0~X%Qv(ov
zZF6$4b+p3nX%n?k5kJn-GhJeTY8|y)A81*w!e+Z;s2Lkjy4Xc?q<|w>!b;qbsC#@M
zS-H@(Q|EHosUj>mg2o6l%N(Uk#or&(wTB_uMQ!_q;oA1;f9wkg)QdjyzNRL8Q#qcB
zWLI}160WA%(Rqdz>KZuf9Lblzx##}EaY;P=_UOA_c-!X(yE7#ifkQ-;d`7E0=#jZ8
zfsZ1%Sd=LO%40BzHhMqMXE;MU<@DgiG)X}U^sv__3X=TkOpj%WXetiSK7vH@?Vi5)
zZROPwI46&a(cKztA6>d|Qt^a0+9yxqtf2K%abyOn^A+43?|!|~PQX-tbfDibX%G2;
zS`NhZ7mkV~tY$&B;I;s7UZg97`OLO}Pi>;-C8>Lqqn|lIn*5Cf&lrj}qZ#fQTGv!{
zHGlLc?|Un5Di2c4WkYqw;(40Xbtk1SKk4IaRCR?Q&V7YNh+u6$X4uHDaX<PH@NNKO
zEj3ki$7XX?aLm%L`jyNyxeUibO;kIyAUYE%^@V;o*TnAS5D2dmZ`Gc<U=vX1kL{g%
z=MHMyt8$3#Xxe0nMr`Drtl@lKvX-=!y{y4Hkgk5Xyyr-RNuy3=F4p!^_O>G6kx=bZ
zg5C#*Ed9=ETM^EyoyN=Si>I39w$lNfuDz27NO23G=j^S=$Gl3=YUTFP5Ew2OtUc+1
zgzhEWK5p$<RC;7q#K&|$)oNuEvzxuXHq6Z0J%2P8+^q2V?8~Pw?R-sN18$n!dzgXh
zJlQ}Tq0e0~_at!4%cFPZyX}F2yJ^t?aM{%kDP(+Sf7xZKY3y!3^krpGg75{FqqmOH
zSoiY0FIDWB2oqjPf8HntJU>q}pT0cj0FpL=qbohT#g|uYr`@ZfWaI;-!j^zRe@ppw
z(t}cexnFpCLl#Js9(#Peuuc^f-1I_EZxUa%6MxuDNt5l{P7<2doO%^O@LJw?K_j~r
zSjiD)*IYC1$|10$-9C@MoL4X0?7qnL`R2y>Ic;}jjYNve)!(fK#J)%;T2e7&E^6j0
zK-d?nGZ`yEc3SR_vX*>E7-v}eGh0HWFqp4`*-4w%0q@bdM^N*@Ra+$IUBv?5Cyj=K
z=#=9WwWvnPs79_Rr$RQCB7H)^EmQ`rtIgWZQccGtrF@feqpb?fvQn+NDz{<}((1i^
zP*3Ev^5zvwwl!pm%toY%(^6Qq-l-BrKZG;vH`><lSPoz4m^;%K&uJ%1Z=R_H9XnN2
zds9_SdOHPspPs9v^n3@0V>Qjtb>I2>UjfxG?IKc@%lh-AMIim9;U$8kF&8`Y$@ICR
zObwp*Y7c&1>O*9c8A(fi#M_4DGkbPAp&E|NE}tZ77EFNCFCn&}<#wxjnu0U+W?zR%
zZPTCUaF^8QFDMgj4zvDN0Pe6IAh+O~!tGT_B^zE(7?|5fMLW}B3SC-**APRc2FkWB
zo%PI6>r-oX(8rA3iC?B;k%c>P0)5yn{9CG9*s4Q)Tx8A`YzgfoEUA_B-WfM()#2%^
z7aX-)Qe1mJT)zf@Jwf9GS>xPgmm$9GJVSCmuqi0>2K~#aY{KLNO~1!u>~)iQcB@VE
z_dO(k8%)7%8neeuAoREyRq1q1l+hPiaJfye%~!S@e%MouaYr>;)aOskLG(db!5SBS
z5@8bWRMNQE{;jd{#G3wRHkE-Rfuq@7gq5efmr5T*UlI0|^2_fXykM+gI7GG$-zIBR
zij`OM>Dv39igvI!C7kDG8<i4e*Ar!z5@m1fi%#!fL6_d2g<4Lye>M)ldi_}1tr`(=
zuf|!P9?!8%j1^XYB9SbJIX`!w-K}-Q=Gsc~Z~*KXEL3kOf)Ii<F6<-_B;JX^ul8?^
z^#gvje>3>iUSa)rwIBao?G43$S3~&kY6wAah-{l5@!c{_BkLQAq)Xs`2Q|Q_@SoTV
z*srjL&vD9-C`Qj{Q|MorROxMB@yc<$GfOX#wiqniXxEFudha<O#evNwqcbmuN5e7S
zVxB8P6VP%RF5qj4!3@0EiFN(^SVs8Q<Wnj~jM;CYFp4;{>>J*Al11=7wIkJ&ywJ&A
zfZlR$G`MMJJUkzE0p*8ERYf8^aJM=bu6vR#51}hcQynoUFVt_mt_s8C$H>$6Kr9B;
z^&pQHXCH^I*Ne~*4qreo6vDQR!-ta6Ufe5-dv9a1fQy}FG^~i?NP}b$OFWxv@<ke?
z{8+nLOVFHk^86XQL)BnC5S{O={&RNamQ7fyCjTwLK$=)}Xr#*@U~D_@v=yg;$GJ~z
z*4oOi1EGM!l@&L~5P&^x<BG?5cH$+lzI~B2Tc|$t-c_leq8<7?{R-b{pZWSZ7IY7H
zmkOTWi`<bXbP2nq57`#^-xEa}(sIqw`=hp4>PiHbV{Wg1D({^=0pNXVeaUbA!R0R?
zlA|?#B)tm^o)evDgVbXk#{0ic?3;q_ncP=pe>3(xM9FN|%ev3UDXNsfvJ5jW)^40L
z^kSe|(CF!$X9yDhsN~eYUKhEnxBc;2DaQiFxx<U02L(OHrCT5wfVlKGoh5*sk(<u1
z#v08T9ws`@V#+w3s(Mw7oCw}jTlX#X|EV@=_9~LCh~@ze5BT^Ee!Cj>(QYhqxu_=R
z7l93E@t!qs&Ud7{uNvAKY~2--S9f2lwSMtG%kuE?EO?D>f$=9G9bbNa+o0zYw1Hd+
zF&;Li;(N)ye}vw^C(@YvsQtGzSfk;LMTvzTqZ{{geXfnmkutUD$&Hlv&R#m&pr`;Q
zCXiry$a28N{Gyd0we_cy=Rs8*7uQbgrJOeCQOzXGl(8%H>@&ib2pGvDX2eDd_oVBm
zX~PmS8w8^J>}{7jv0VbCC3GcKwf=BY_VUAmkLiozfkmtP;FWDGA@@DhB3~jmN5TB#
zColzu3ta53s*(C9wD%~y|F=9TpZO=`51Yz|mBS@@rrH9`{|Nty=Y0`yNuCoAE}ee|
z48rAd#zma1BhC3%II4TT)a9ga08E`W);9>xT7W~Xb8tp1Ev+&{LO9p<HSX4toB&5q
zbL*Aw0g8+J^`>Ms;lj@82yve$%gxr<U+6ce*Yt*T&$f3TftZA9OS9mEKQ;m%F7B2|
zu_p-3Q&jx)w5^ct7Bj>v!{e!0yjaS&FD>r9_ZK(ph@RHk!k|asN;ynwzcum3)HpJD
za8!RNYrux2x3?EtTEhCQ8ZBV_D$es6_2iHwTX^F{DN-e;;qi@C^ZR}L{RZsViw%?N
zuux&r(1aeQp=PC*a!p)XGmhs1ldTW8Imq)_efh6+RyWM+6<)kgNsBfJDhkXdY^)G-
zfOV}~PeF&a`xnvMTDWvj@b>h<Q}NkB=W?69(aW3;eg_W_`t)ntMko7oIn2HFK@&PJ
z2Qh0}?RHMW?DRR8yg!4P#@*~YyCC<%E{a%ErrMvvzqW+WPU>7cD@g5{JuOfA3qs6Q
zEu*p7g0kyMO|N`tj9z#c6_Vt1*XQ$2F4%nmQ*5&)SBSI=b!uA!*eQlgbvL^Dne4}*
ziul5{Ri@}A`)me-_L_RgF*e5Jb>6bBuDgOO!6uK*k4=!1Y7arY65||!4&qy~F^)-C
z0R~TXYh@|jXY^Caqvxa5=*&G_R$2|dY0*7^8~~oe|JZT-bOx^p^>wOPlnj*+7(l=V
zJ#LSQhwYRKw;KI17nYfgUcrP+5jxiMg$zYqvwy(n<pbk=4N;GHP-7I0>X8@VBOW^P
zPSWQYrH-YcG|!V`ChIa1@CUffb&}oiVTv}{jy=@Pg|U^N+i_u<)Zs;~jgci83b`pc
z6seSx4dCw==WK%_%_O<>P#n1Jq$?w(aOT0~p~Vf`yHcNKrDFaQRLxqFPlsV^ou=|*
znhle6^@X0xjMXm7j4{iNO>J!*<qHYNjfJrXVwIJr^UdzdF?vlP-<q!S#iZl4!f_j=
z%F3+yW>3Kw-=-XGP*dds9JaueGZPpiUiOd9XgY58o&+n_zbJxO=2u6^W@8F!+gaT^
zJeSvnsv5W8@<?+)Hn+DA5&1ki3-7TNM6`t4`@60~fHR+VN4vWHh5u>$TuGzt<%0IE
ziK#6E=n{7cqWsj*tSO?N;c|rES3K+LU}Vt<T&g~syci$(*f*){ga>s4+a5ltI~8tM
z5&_`K3|h29<X#tWt}4CZnV}H$wQ{i{rz=*8l}J}|yHu1U+C7F_c(&&0;h7z*K6@Oq
zwd}Z6Z57~?348n=xfsn~nnSC0qf;3-r<P^fvN|N`%+pe`Z$4fguvW&SSSH<YDOI6V
zNz~*CtRW*4zy#IB$j`cj31BD;Fds703&?v|l*jaxOM#ME1lfCzI*!HZIxH5uQkI(Y
zBg?PnD%`JqN^SJ2nKenW3`wBaIo!4{?PXcy{@FZRMK900zd`l`XLEaa_7R(-rJXGJ
z`*gSWT0_WX0WM^Gu_80z4UW_apVLro<xLvCH57u#F2gZ>NV8n*mT;j;VOB=;quEmx
z=u+C#tt+1VX}yFFWWaYg^>X3Z%Y?SE;u?KC0NQJ7vZq@w=+cC>Lg%x(&WOf_+b%6*
zJ?%Ab59lHFtipx~{)ajc=1yAF*DvK8)ieQTX8Tkk^7{9^uLGT?=9(&RM2STmsR2t}
z9UV}+t1jf}oRvM%@S-jdA8ZJALub^l<qtH(JuT`|-%^?V1~a<#XL0oJ><yir9a=P+
zej)34Zi*@@3eZgnrvVO2Pw(V6l5#F1>F7v3UDvp-os)VxE{|j8yQzvCDoW&|a2z&d
zPmDCt@Eo*57rHx52LMlpHWM#hS?f~kfJbE~=uJai%kA{(w82xc$&1I0wC@Duuv4(i
zzR#!$AUDVAvb3kvHPCb3(_#=b_5^OiZIz~jcDqfd`V^!2(q-_SsxVYKipD;=2T#^M
z=klyONH+g;*cUvM;?v<8&_S*SABTgoyqHB_xbI#6Mg#R`Oz$OJV`%j-7C-VGTiF>;
zyPTRqOYm~k$B&A0IDElnT~c~<spsVu1VyeM8<Mx2xCxggL=IV}j-*;j9vB`mcWd+M
zyDc9dSV{~VShxHFvm%N>d|SVrI0HPHUX%!<0uJx%HrcwC$X1}+kDE=Y@KWqz0NFh)
z2iRn-T_;bBmf<#dqWx$w%d{F#-Bys6STW!$Q~I(WBajkzCy=>UCkc#m#T9<nh}k$|
zH^h6Ttg7cRY>x^p{UYd#{Ittsf$YOv%3;aVM%_P=Gt%9y_y+Yywbd}|jlQbc-LO3x
zq{aT+;q)Zw%KvkD&H#CNv3nk6;qwIDF<NiPchRWwL{NhlMJ_4L3s}1J(>Y&WJCeE#
zQqqFe3N4}X7G=F8XKpWSlXd8ast@@gP7*V0e0~1MuCaI5N47l#rcw=dx(GH!#dIFP
zg{*~LaT3|nNg`#s>M+|wB<XUw!@vLtBox37qDTF71L$8*UQSB&l6jFg8fJTpWYGDe
zgXbj0UDCTgz>f;=qoQA*(3PH-rn%oRWHyq~0NCTTh>gI*)gInY%t#zV7>d||LUdRN
zokDLlU3o~iRx(e9Nc=?vD*Fz7$^!!QpWJymK;gneT1dR~jF%q;+HC`3^lm{*eYlPb
zhT(J}y7@~LwJec$o~O${3v15R^4G8zn)Dd<``0WQRD^{qvsnGpDke3jk>o68dG9q6
zla*ivnrqog(L!s}-&=otK)>%tn$5Vp)VSpqX>U%uCVckYqNCwu0N#VQ_SkMmZaEGQ
zwoW*s`Kw3=Zb3)B?Cpj1DJ=UVzthbJQ`AyQbmX%$HQv86l=}g@Sf(ztO3CLW^YHDe
zbif-2H$5|hd+xVyJgVjWCyFN>QozkwD;ud{a}6@Vc;6k9Mfd0ObQZr%$(%eE&cF1e
zq@Ksc6McvH-XR6I(e>+`2%HiR<T0RKJD`uW@`L4{uUdX$tMB70DKSM(1zLQ_i5i{h
zV7|ZDAx@$DWO(e9#{aRwgUq%MX!g+I=`VV4|2W>GtGo9n=Ty{pBSUBE=w*<VBh630
zoVL?FU&FAiN2}`DsHFn1=)4V1on}51;M&6(NaLBtNs26eCSNj|rvto5AjRxfP|bsi
zFZtSf5})bkNAn@J@8}+FI6%lNiUIFLsxO{V##mAd0l`vi`=~m^x+~wCns3HNBGom>
z`@6off^^4VR<$sBcSNg4OFxn7?Ah31E~vKS(3AKJ#HR1qC`Q3XqyarL*j&Z8%X^^%
zq-8hEm7+1ct)q9+gYss6O5Eo`h#<!P>rYVw?wAZ3vRq6+eHSJdDtKwV?#19^i$#{O
zvk7I|+JZRaDd_2{-(5}JVJLDny34Xr*Aw=>{)YBHIr`37{m9g_OtUy~_bXcl7v|G=
zN5)<5GNIuO9$qLD$c=N!GmC&%H`pn!%x7U7Pdfj3vM7144K+DX^B$B|@s_-GepRJG
z%(DtD{~qpk0zD=#frdB<ZHxpLwF~AP7@sIkFcP~pj#u55kLz0aQfSwzs#2;rK#v2u
zGbmg(%yuRVl1=jvvxxwoYl!${(ZF5P+4l9e1s#ym$J0jY?_BOGaU++Ki%i<&XLm|;
zhM$Jr%}O>YUnc~>_eZl8$9Jm7*yB#B+I%|sBKL}d9c`1)2qt5t>z{`{?RGYS#SQeP
zsYF+$tE4>A;XGeEq^fylX!|QVkp&M{+|^Wavx|roY1=LDt5V(U6jnOJ-SNls+h9vN
zd?!)aIhufXF|CJxdcH)>jqo6ufgWdiu=O$paQ?H{Pnr~sRSx}l&cD8hJLJf+_aI5N
z)WhFa)w(zp={qW_7#r}i9XnDArVJ{5Ci9u=dgkhlHn9cx`;887_8(U9G9?{mQKs0m
ze^q4WdYlTM$(Uu9LG`5Y{YAPPnAO3qiJVRO{V~s-ub;jDdV(e8S>nri|A>`-CB`X9
zqPJb$y;`L-s(OtQ8?j5K3CQeVoH_nOs+TZHP|X)P?L4|4ih|54ZJ$-O^E~n?nK^=J
zwu+qZYgytYDJd?;LM-3Opdp4A`g%}OxHL#yONg2N1DGy#)KO%ZYY&JdKFA9_!&W6f
zj5wiF;nnVtbBeQ@4zZw4hLz)0<L7<QQhz|1470dP*|7eiIQU&Q|3ibq`^hj$B91Rq
zA=bTh=!00%+AFAVPDyUlFe&Ch9o@;W`5r`30u?$uj?=$-A)ks)Q>n3CmXi5UzhnwU
zX+=q9V%j}HiiKV=L(O2tH%-@`O*suDqV7)sMF2mB`$#6pi{z3Q(gcZXx}j4#orIEn
zvJ*uAC3uEbjl9a1wJGImmiEmKGm*Z2EE?2jUC(WKs$`S7v`~4lVo!~6LEmDV*4NMS
zbyVT+JRVh5%B!jv@Y4J**q%uTE_v2mS#*7x#OVY4tA1u}KBH3CY|n+DlQI%fOUBm<
zf8aK8+~ya)R^>=}O8$_{@1gu7i{mmCrv7YrBhZoO*XXdXD`h--mnNsr2a;3DkC`ZS
z1u8Gvg0UI56=<g#;`dC%rvDjtpW%)Mh2O!6Ql~j1&XS5&j<3nf#+m~RM^9xJhvZd8
zBjf(+Mf-3FSM$MiPF%-E3~)KPouqok%vZBU7fQ|Q(UgjwyNwbVo(HVeR=@^C_AM*D
z20v5trgK;lasMptTQ>t&L+bNI18nXCo;aS47?pguDlKY_2}^$zLmQ^s4lzfSmil<#
z1d-BU__gxOe$*vz$RWyVdleZ);PGuHvWS|O#!=?}&ev3Z%U1<Gz47M)s9jfuZ@(4F
z?L+2ftJZB}K|VTz*nf2W?Ro!7I9>7To35-AhcD5s<=*S$i}wn6PeV=4eFM6l7lJTz
zMLTl4;zDk^r!>EBPds*$lI!NdE!dmHU5q_v+b&(RvOO@L`TLyK!`IrElqu;+ysJzn
zE$tz=K>VFbXB*ZI*ql*6<cPn@*QqRwil-+xWO-(A^WLP%b2%2|NcvCy<SVN*CuG0J
zbp21>*tMdu1c*Tf_cVL&Pfaqvxt1HKf1gW(U0WA21%Q{PPAdmoTV$miIg1C3reuX-
zl4hE0;TC4qzQR$m&>8!P?v>wfSM%L0X++kDbd$$0f30iz?*!Xcd_rzSaFyVhQ;v2|
z1|x>lL|lbxXs4S0COV!exvl7b+-uO5WYDyhVs>8(R*vBD+ZuihA9-wIEz}NG8T7*A
z%*LHQATk#ctZqCax7!8!GJ8@}3!%Orm*eA>{0qW$YY%=uF3}0ns;AizM1_DgO}fqN
z+5S!8C|}K|9YH<9Nci+W^}G|LQO5uW432{!;Ni?5#vMT>P!rBoR`N}4ke^k#t-+ut
z9()D&x%pZ3bvPdt!O`6e0*M(_i11AX;IE%m;*7c1!c-&ww9Z}YLEkq8mz(}|?zY8S
z|9hJSZ<z~QlSZyDs`zW%<%{2UmUf<{p0Q(ig*&FsSA{&KUEn%9Z@m4m_`6+TS`ro3
zu$}gUT-Bh~cOidg(L^Y>u;~@ooRGJ18twFF8?jRB6FDgV$xR4UTnKs#d=sZIE!y!d
z!}X9nm0gF;knO!WzZMZVIpwK`1e_e=TDaMxKN_mzCBebk!_a5KpWjUOdulVvG>uhW
z*kBk;k0E_Ykn1HE?<vKh=laIQO1Nk&_dLkkrSLY(k&O)ftiGu4eKd7<@s#S*-qPkk
z>nx2L@?M%Yn~%}0Z#<`Lhm51X52B}*<@__VVcd=$M@nx3X3^1VT3??3BpEqKyPnPS
zw8~*#aR!(<;!IZ+`YZ05Vn>L+Xp(2p+xZ#N?xQKnI4-^XU0!197vPJp<?>ZP(%*Uw
z{;kr_ypnUj09`ybd-=(C-NBj2Obx`i-^qe9k)5F8XrD2y8{t^F$=5;e8n~e)6L}XF
z_a9)c1_$5<75MbF3O-tp*i!Cy+djy_N0d=C%6)M-9i<;mp=q+bE&hvjsuh4~04Lr$
zW1(J=r73opd1Fpt6o^z95_k;5+ivzrzU(Q&+Z);LA=h6vjX~pXwnpw%=m4Vps|y@A
zrYVDAdGb#=$s3063gz{~J&rE=dSKTZKK^+}a^x5)-zo+K`X$|#bi}?i-e|kHQ~9G}
zuJd<FPM#kKi9~k-j$+Q*I!5kpowD3@;@psa!6=mCF1U3UpfI>^lNj#XbU)c`%xFJ@
zY?R-NxSgM|A;|(T@M&KC|M)h|{`od>eE-L{xfl4VON%Bzs<i3ZpTz?=Wbr96pcEq!
zlf6473tKd$=FzBh_GP55x8U^-buk*d&S`T@2FKjrKcAeJekq<80Wy@lZ3oKW|8mce
zLj|?-iC4JCs=QXVM>Ok`Wajy*r<PGR8|<<MHk$a~Ub}zWCRrN?nFmcj**X6eCRxSI
zxlR^o75yf#5)g*GUf+qqB{p><1cSnpmZR8qQR8QRftyrT#>RS`0zV7x;tWEBqL%Xa
zH!I>uI<a2ntPcPCD9Ai#_)!<BCFmlp>rhigp3fwc^^dfuM=#qa+IMU-)k&?f$~w(W
zC!%pB*Ir2{SB#;TdV4lqy^O|`*X`_OHSMMvzQmF-2%hH+8{qlYDcyf~_@SN?C7ufE
zI2-ahyK{VUnajzaj?6dOl4{U^e_OTy(w=7THdy7MK-x$klyGy-obWikpE(w8g4tg7
z3~(`I+SYzIRDZhOfK4;4*ndT|Kh0ab0ulE1<jZNx@MeAHhXN^^z(37S#;ZOixK}TQ
zXkYvtIS(fGFOo8yk7}#GnZY1Ld<E%hcM13v?t<5*_|#u(edV$~SF=(WU!Z+{Hymdo
z{35Y86gkg7+qxt88Qd4;$1v}qmY>Fb7RegWVvj*Sc?I|af(@xQTP0@e4)rp`@X@K6
zmnUaMoq~2<JOC}609w5yi!W0`Imj_xYK*Qa9Wxr}h8C<&sO*dtjy<8?St6rz?%0%R
z>{;_IZSsQ>Hrx9ZsRPgfk0#F)+Dfu0wquOzo)b35-iLFD=stPtwLRC#6MM9921FLd
zq%(YTUCSf-a&t9LC<wCS+t&&beK9{vRMeW@wGuiKDbl%XHV80jH=M7|$p(@tR{3=}
z-hqA-!bOkKwN3=X>S?2F>HGkti9`H9$L^0s*Siqb0LNkrBb}@O#P+R=gF>FZ?dA4N
z1g9UP6o%E?`A(PH*F7aqHxrQlY=J#Wc!lyEX|Jt2g(n7xRG;1o&^-RyhgN7^sLyOa
zcf14Y8m0Aoz&s<l7vPD<UTyWq;b=Lm6UY@bpGiR%%CJ4aJWy199q*o}kKnM^^-Lrs
zgmLajwybkf1iA*6+nhj?YCgj%wNCEDR!+OiJ=&no^RXXu1jeL=y}<f*=jNXm4Vo5A
zzBqyn?}$R&rS31S4}d<89V&HS22rL5ypfG|cp}}+&WiSzv^Z+#Wmoz`k&B~O4Xe@=
zicLWpW;1(J)m>l;5*mkro~N_Q<%WDhu1H_vUyhDQ%Pv=Morx0fTqatgNnu9>pwIW^
z7T&%ITJ6)&C2=E?CkqP>W_hRkh2Y{h1MbyVZ+%8XA<YKk+#)(N%hK!EPOfL^^X#R9
z55fWVqQbSSHSoW$w~0+gB6Rxf#j7>@p_wl$aGL?1d0|!Ul{^GFeyF)H|F8r64f;@L
zk&%vXlEH@G9?o$&r&(aDjN)gJKUFqk=D8CHEgF?HJa>>?hL=}E?iTPQyK2n>wAifG
ze(88xB=8ZW@~Dqm@Gdu@_QSrWNdJ(8z^ryN+clE%lKxhPrJu7V=5`EexAJExFn-MZ
zy(l@Rl>A%+QGW<LpXXgD^md+Og!Dmb!H68Wtn{pQ`qz3&tW!~!u=lQIW9myL%r8@j
z$9H<GHWYeQeVsFWL+83LFwh0O-Mm%wWR*hM|NBQ?_T+!!9(07E>d=)aVy%4;S>F|;
zyKlmb@dX}c(5_+EJN5{ePtlW^W(m*WFMZJ!jA4VvJM_75NM*t;Zu+#urn}APnTG1I
z+p)9LOg+L&-l;I@-|?VcGtQNqu~8n}X@`5!sb<m7LY)HDP3a>FLKwK|GD5?;Or6cP
z28O`11PRo!>m!Tnp5VYLmlwU;e53S3JuE&u>7s#L6N&NwO?gKZKX3P?3S3u^BU}XS
zt(3K#xXFNvptPIaMj*o5|3uI!1Kq5EmiSAl@~A9W1%=yPAi<uVw&<FoVh}#p*TPeO
z1+{VXQOuq`!>big>v6QzlF9Q_=9xi+xFXXVPo%N47dK0Epi-R8V{dZ*&*ifw@R-Gv
z*NbHXdEaybI?U`sg+WboCuLOKAuruEMd4wWi{7>0l{}zfV4-F{fN1UBMl*@$m(1g;
zY>IB`xGdY;)^9&0P03iN%&I+&guFk5DlqHVs&l7D&qdH(K(2b1(hji%Vb!mZ?#M9N
zEOezRMWyXT-3IsB5>jFXJ&^`zS<2Yxbqji$ziVXH6hZQB$(mh}xTdSob_UFKub*v~
zR#)32r9UAw;AziniRq-48QxaSOquAceM-rErUS;plr_~-v=Cq6#y6JuOuQU_dZsX(
z)Ccr9G!jmljEnnG=64qVLVqt{G5hX)-ro;PHGNun`S+CK>NaSJbYYC*9wqKdsD&gc
z>PPC^eP3!w=F7$`D<>JNS2sUu!IV~X3!R9hA}s=@arc)-fqUvcT!P8rEKRFz`{vrT
zEKVMwbdV4CK;&z88^BVW8m8kuvtYbWX2)6e#EN&<eeFx!^Xcztl3V1{wt4FtP9VJB
z)5yK8Wuxlbg(ck`M~B0w^m5kO&`T#smpFu}US|xpZy{z>v<(q0L*-WsvS`qF(PkR|
zX4OJ<K8+B@N3T<Q*c$skHi`uEOTYhY6y<b@y9PwwwdU!CQ{M^kXv{_|d4u0eHm1aY
zd-mb35d*85hv~1|%{p7ZfnUST@iH5_EMD4Ze}V<tAXBzCZ-X}NL|WOL^t%jZQ%**w
z#vYhFTzu{P3}Haf|FKrg5H8S;?<}v9`sWBt^^86KEe`0bP~0DmG~~4)yUX$AI~8x@
zYCm9M7SpoywybB1?9>ZZ$}1CE98WQZ+b%rLmW|q=-RXX~iMacc_pO3u!_Upwbd??F
zqALZ*z}YJF9EHRof~Tb+sZD2v5F^htv~u0^qGiKW|DM{LTHd))6z1bgO0H7=W0S@I
zYq(&L_<s!-)IOfkicdw!WP?stj$1Xkvi{Gp)%GjJ;+``)bjPh7Gp)U+@}h>n_KV&8
zA6EoVZ_cFd-z?{0D@7??r=P&h7Qc2*1sq}xO<T2Q_2keYGiNdB`MpHLcItb-c{xH3
zdTlfE9<|R}OFt=})1da7|Fwhrb7h<6dbQHEJuih?kE^rXd%y<}o7;Jnd`E!`_P6=B
z-=n)1^3UfnvrNKS6iFj?LbKNB$5ZS7KQV`y1ttbj@&?^aPdMcnul%F5{-)37ph!lk
z|5F_xR$;`{JZl4cZ)6>ae-;$+n|;pe>j%y6775#eOzZE^PRFrig=IRdq>+WZW4;M{
zQ6>n)r5qD@kYTs#8lR)Z!*Fi4c8d6=GW9(#o~V@_%TRi~@s=Cjr-07Ev7S0pvY(bW
zXI6-^*haaTFF9-6;tBeKfE8BsQe>SIgV&9i_Lr!@_-efN+?EmHaDy~$?X82iW5V&>
z=ZiK?F#r{ztVYm&2GoY*3rI6(!;lVY!B2AUbbzZgKsnE$*x#;uH4;Um;J4UOOWQsQ
z<585Kf2uR|aFR<ut#g!7ZdO}d5?xqb7MU3Q3ZxyhYb>)$4MFqsJ!kaQLq1mpWUpf|
z2pitLL-`iV$I8cOmNC6unhW~Cv+_;6Pv{gVrK-h87!@0`TyWppaCPp!{~biYrTFYs
zL;h9oJTGgpw2@hssEBXbF6448k<*&Mqo@y(y*3ZFi?%I?J4cGuCQOHm<D99eSF~9^
zQ&O+Id(ZbbJui+YnBBd{?>9KEos!xKt3!v<Tk@YaR3(2EA`4k_0f)p51ZEnUc*|bM
zea4HhUdXWuoH&|7KAHuQlK}p=O;JnRQC0?kHASA}XdQBc%yd9s{gmx11E`U+Rr-gw
z-_mguh~_ThO_5iG;8H@nhqZCw+)tAK0SO9l;7AuAKAmfW14%9=!8gd|n@sSLiJdFx
z1{qFgB!JVCR{p&%Nh%OwH#jlx`ehjx0s)A_-l}CLGQGTl)-N9DWzH3yiU_-Px+8H7
zfbjsff;No^gSvnYDyztzju#<;R;PQPtWc$bsj5BQHYY#&o|>^^_RZWVS|Loq)YId2
zfsf}?uDRxNY(T=*wd4fKk$9nMT^4?>g1ZOq#{l5B4-1!tM;ga@E4=S9SvqP-JN5_c
zud0=(5ZcfE3ZvLYE*?7*N2eAeUH}4y#2!>DDD$;qEL_=j^BtdgEDPys%*kLA9c`lD
zI_dG7w%NAjh`C2aA`bU2Yo^J(k#!g_Cp_Sak8v<G(XpDgVI#VD#W^MQLI=&tyGO_H
z^3IrlgxEZPR%C=&@v8Gmy%~&*^H+9_T_?q-PCqrV9lAfc1zDZUomS+l**1CccJ2_7
z_Ldg~;JNxZ2rGHHF9Gjz-l|o2wQIKWcs%se&EZ%<6wA2(NAvQNHdaWn1`;Ko&k0B4
zfv=yB-7d2ptCNQ<eV0kmr2o^pR4H%%Ih{EUhF}+X78Boro}#t%e6<1sc4SpUC4TmR
zjKp#+o*Axng|v3Vp;SOLP8>IE^GUZ?Hp2rqv+*S9p*E;tE~26V51+QkLQC;`Rck__
zVg>QSn>Rd#(N-R1787LCgOygGxU~eXU-87`MX`l|jPWbmCgVW4GlleA?KU>oZ$3(@
zR=`>0X)luLgUVvo$~DqKo1M98*RHRXP=;7Fi{d7WRPmo-Bwyk<)A7H=O+7G(zj^;j
z21{I1;tj*)l|UFp`9;#tci3OzzDH0bb?loLZmWu~>^cO0l38k$e-mi&?#pXgVow{2
zho2umh)>Nie0t}H%1<P-MA(J&%JXfiSX~T1HI@~A0gB9Avm|2oX%h-X0E80dN-~c8
z=QGw$D23=72<0Fq6A$CB|7VE<q4bf2Kl1QL4MNG7_>7hOH6UzF75+#CI2V5Q>GX~m
znAQaFj!a&S8@&l1s|0dOUw5VPz&vzf{$9enzSEExVGhjqT;6W{u8Iz26z(KT-F)}N
zPGXFSywHPqmq65{I9+&x@Wd{x#6F|f7HyKLI@2RgFD9&)^qGmyg1%3P&V~^OaEH@6
z=NO~DquZte2((j*l+S5bURi=09$b#Ut#dD?{7<k9gVI<nVVPca?m0_z8)1sT5$#N)
zAq|9nrV*o|a{cjF3B+8|;aGY3v9j`AL#0-Kp7L@lJZ@Wg*(cc^1rE%&!lw;u4RAP0
zk_EmO-G~7`1_CMnouJj-45#e;i#q?C0*^W$&y+L`^~ON1&27Ko)izvO2|Q_-M9C!T
zsp;3iG#<km>Ug;FpBWlJE+!TXF&xDnT9wiIm`>=@U1U@{+{zZg+QEKyCxM-y+AER7
z@Lsm%7o`MBLY-e$DzBO(N<!Sv0{y*U9O^=&Q1}Rc0pP@%8>3Ym>g@(_Mj<7z{>5Wa
zj8=H?>_LxO66m%umf-YFP&tH~IuYEi@)IwC7wf1O$(v&EwK&<kE3r7_pF%aZ`JDfE
z30vI_%-qpJUaMC>sYiCwBDpC<Ei6eAI92o>9#m|*v9xe67IrS>Plq=L*7-tCzI~!K
z5DD|LqfN9X(<Wkj9+r@sR2P*2B<$lD^joZYceLk4>KN4N3C|avjqRoGPtpSc*{#qq
z6Ygt%wDsdYA&z>as+?>-P$(>ol!mP$9Gtq}_E3ABMyIOlNULf?+cETO-~O8}dP0+%
zE7w9yB4W)V?6GFFdJwWW=A*cWxh=V_X>APe-%KtGxL92P$24bw4@Ah&1#OTDRIbhj
z4&}R6z*X&8PWcbK!Z_(7@ee-MUPr#e(bV@2E%E*?R85EN*s-m#S%H^8k}y3llC@Q#
z#_jGVg>8SI;)Oq>?DAdWb9}0>euCvu(|488!|QpeQi)DOrq6{-f;Usc)48t8ga+%L
zNPCoIL&ZlfW>g~^VLPt-@~AVDlsRNk4z1Fmeyv_M+=Qg49KUU+`{b$Cx+wue{{l&-
zy)d}>J^@Pih;+1B6m;Xe)S;ul8d^2t{YKFRJ4`r-i@=q;AwvU;7f<X8oF@;KU#?tI
zxD$M|x5t~uf)fFmd)QDtN8mMTL&;YXgG>WMZoA9LKJRjmHCxm7PXL(Fi-15?W7&)C
z`bzJ#L+?wfSNdhtIEfYVAF?Ud7Xa~#QytDB8d<AwkJGbOdZ72;h+=3o2v7LrXrS50
zZ>5AM;}YHnBH2?_*H%AdsY*sAR4dx@_&?<<8Ig+P+_hX&u$nA;j&m(0%(KvUzbfT)
zHDzfT9$KtaK13n>nE7lhAMpf_r%e#ls%+x6w%Mm;zf2rMS`CeyHjB>Yv8ybXCl#zt
z@czWZeVVfX#z_%=&7-@-)8SYehhcYqyuTPZVXHo#LDvv6EIC-y+Iwi8XL>&w`e*_2
z&=s5_blV2X?#F*Crb(_MoyVwN(~6C$Z}oJ0lt0zKRe)*>S2A_r4^dB*K(EW@l9XH-
z&TqC3@Ojh{5x;x8tW}gEfC$B+)4+do#xd9wGcGMEKNJrk^^u<d&u`Nzx76DGKt?5|
z+aK5K7RzWy(Q-x&$;-%(@lif%1)jX|*A=byw^e83svC~xFNdW^{kYzKggmX74enhW
zsg!4H$3G8edwnza7yd@J;nJW|T^bd>Bd=zcIafw*=fk&Evo^dQ?3Y9%Dum?;^413A
ztSy)MJ^FdKtnsl{v1%ZdF|uFtug_-;CAKu%c67-gse@p!_Ok0v#fjT%bN7<Ss_cNW
z07uK$4BmuwFSuqIIpeVjB6Km1F}jA4tmi%@Y_k3eHFH{T=$pl8us$EFqoma8-<o)r
zYoa8Byl7V5^b@6s^`+MJR!K1F9vOedYkWi7*?B7h=;uuRn`v-b=Aqt^m`=LG7C3Yx
z@dt!z%EQ>nTBO{)%Q58VmHh2Dm@Vb@jIqvAYAwL}@S9KD1upm7NaljlyZmyatDQV_
zyoxHsVsw3TvjDv2IodzLBc>6N>dqgF-Zsxw&g+D#<y@|O*FRo!*4j-{yvEy4Qrxz4
zdt^eXtO!gFX4L9*M%Fd1T4!j=?25XdTrG##2uTZJ5UCgp`W{4<E1cVH?jw$PilP~`
zd<@&jTb1mcKYl~es(!DBUNr?3vkz1}rto%9Bng_aXdw@+9Q0Qr(2x4)JRy*|AUsyZ
z;2zm@QS`F`I055A46CevFJ>ICP>Zi?^zp~WRQh-1(sJ7kbXv9&hI5q06k4p(5$n9}
zL5WlWK6*~zv1M!Q8)hKoI+8ZaQ_D{c=59U)xQ8s~j%%06Y%9MPuP=b!O8DCWV<!%+
z8?N5lL?iwyiR80FJ4%ZYLxIfNEt(a>HPiXmw3V*Ni+vE;s8@KcnnIq1$FH{J4e+B|
z=G;GdM;b6CbS$}J14j%}H`{NkA_sLZ9$UkzygGh;(7$T+s^F=HejaD@(eP5P;A!|(
zmNk8pX1#e#S1$Qk-iR)~;m#fVvafpC9DFn{yTbxl_57g!lCZWn^h$fb(xmc7mW=cJ
zlLla|;jI!*y7D4p+LqYnh;iQfuj*e0#t_xn!$zF2ROVm<<%Wiud+$2D9@a8ro|6-1
z-_P*DPWYSG?ZhloU!s;-8FM&;8!UanJMwF!DHE{u$qpQ?JYmUR$k7d^{V=}7NLvRH
z9GF2`ARbCWqJA1y7Xf4dy&@Odz+Xf>KN1~?m?;qvK0n~`#DiCBX`@N+ka&~9E8|iE
zM#ck?hxKmP#J0s7w7D{Fnd7Sr#aBAS`#TvuE7HYRi_1qlZL#Nd@N{>x>8xiY*ZYl9
z^bNhM!PU*vBFSkz7lp9<bMdB>hOF49oQhR{Q!d8kOZCvpS)z|2udp&EqR_;o-tsB`
zSO{Tu{9zkL9reTZ9bXwj1`@#s#0`|HT)cV-tUrxkKD?iirb1WFt(T0}@)EWPSx7U+
z?_{?K0q+fb#wj1gB97}7!>JgZaQYx9k|$$<bSy&Uktb#mqPX9$fm1Sy;1<LA+N1MN
z4F0r@jhocuFxu1`X&~am3V+O265-AsyO~gghGkq^>;M3#a+Jb}osYMG!UCyXupKKl
zFPU(ojV6MDK_6%W$*J&4)KarV`1cD)6}2~VzK%h0oRPa6Ml%kh&MQ>5K*~lUh-Y}q
z#5IWhl@fbzHi>X!QYPPgCJE@BY}ME(eJRd$H|Ms+o9Sn>5cRPNn{V4uoXWX>?WgKa
zR2yRQ1mV8HR9Kb^Z!VS)JTV<lcpLEk%O;m%yTo&p*_%s@9ttn;B0>GrSC5WdM<%36
zEF#8Mbjy(U-(RD+aGxO+1afCTQN<Rx@a2Ax+xC8yr%kkk7DToYxMmS-P2`E1=S=j1
zo*u6raRAM;SNjvH%90ndb1f%nThdv|UDUrA<B=J;oazV9tp018>41ZywM|Zh637FV
zn)zh6QbZp-*Q}rtR{8teySfSdDaPs&T9kLylsrYaM%w{G5s18ZAp{?IzaI0?%(>+W
zCApIzRAF1F1;t1@h%<nTut<@c<%!~X9|bV1e=yHU84Ms^piJ@}31IxR+T(}UqX=v>
zRBpnRbc~pE$>mKuRE?N*i9;$d;d^_)FY}rxkgrt$!wSii+LS?iKwKB=?K)20_8(V+
zKnLsob)16j3qLiRH;UZ?7+dn4hIT&U{MGr}xssBUXvOrT$Q)l8u!<2#k#n%j137~a
z_$P>@_y~%PNs+yUA~yN;N%!|GYe?zPdrzw|S%+vLm-8(<{Mm|2Es;}ys@}alVD|tg
z<Awc}Yc|RKw#}=O8geL@ojnGZYvT|!i0M!hDKhE59bf9oq_{s<V`_A}B<S9{bw<G>
z+3J_9V-OL^g1#qGeCS_iD8v}zkiz}?EBqZT8A(BOvrZb?mL+0D=)fNx7fGAmM9fVu
zDZ<7BIy9XVFCeiDE}GEzC6z&jOJdcHa(IT1_v}=wN^a{ex#=JW)!*ESZVp`RgxL3C
zIO<)Bs0>)7D`)DI8>8nB`x+hb?W{xT^g0ByF?625#s$wh7nR=d>qBx0HUM6Zpa-g7
zaCZm;gCdzUw~Hs%yz~lbZvobDhEfW(%m~Tb^lu{+E`)W#PnuUaD1z60(UE%O3CkC-
zo~!Q;hPelR#C=Ver<?vrZDazk<&~5FzBba{^_jm4Aj#$QGS0Q!JSQS@lc4zN^SXQM
zRa{z(_#ssZ0>p{B#QGsHtzvWEWC>}^_$x`l_Xn4fnN4D@+%@q(;(5rmzUc;Prk9^&
zON<?8>jP*JIAntm-ne~;=uqB4zKDs##U8fqHOD@B&;-n>cL!Z1A(sC7@vGqDE6iD?
zcQVRfC^5c%dCZL={z|K+_S?7j2g<Ae#n@Yh#nA-q!nnIzU~zYMTb$q!Jh;1Sa9Ln+
z4-hOk1eXK|?hq_E!7V^=4J6+rdERrq->-9i^zKY|RozwHQ!O(s!tbh#!|-Izuj5L_
z2Z=)9+qbuEAFYU^bfb&|sIe4OLoQ^6X)uba+wo)%Sr~?s88I8<WL~$~Q(J$>crlf1
zhtif+KIhk?)v(`irJtwYgz(yUEaIIAep2lRwqCFUw9*lsroS6bldhJ8odbqh({Um=
z?{kV)sZK37EWHC1!l>!!gv7dy-~dHs)OO4qPEf4n{&Uyz*HZfmexG^){5TV87=Rde
zM9*>JR;GxpN3>7JaiT=CcwuR{4P48u<?jG}U~c+KNUK)3K;qBSG89Wt$-huE@=EVy
zM?R&pc%j|cqP1$<T|&3RM_lfy&asN$hDuShmYcu6bV1P-(rvioC?i|jfTaL2v<x5n
zN@n@$y#utN8n0!D+n(z^;o`@a=#`ZV?VA=YLw<q$^SSg~vbCh^!zJd7-9PT+BYw#~
z%~K`lAd+*2m`k695Ho?nwilNgThX)9LbK5baxFxuM}r#DxG@XbeBYxzv^AMy`VhWS
zpn0fG&ycE3<I+AlDrI^zf%TU!u<3NxsByW2W7d@Ru)c3)%V6i5z!0UuD5`2)P;=wX
z#MlTCy@&6T-YsPq&_t_}ye@h@FvsX9)qIdRB0xt|hLDn6PXaD34#4q`mAS+W<~p+I
z=)>6#pe4gP+;AwNC&L<rvNgjZ=Eu$=(bmU=XH?7Cv8wjQipfh)#`al{%9mpCrqgQ0
zNME32>mOQRH#+E)qUq8_e!)#uY|E{r_g`+$<9m`g`KAg{u}IN*dAUs-iFoD(hJ~9=
zB1TqLO8-%$j0ZtgmZ1BD9%jLVSNpCo4%|^x7z>uRAj6A_9YoNaWMEa?^-W;`X@*w3
z*`<;$3<AT+=zbbC(TPZL^h~o8JBm$QD3_UqMTH#6)6s#*XKJE#Xb-!n<K>%Ygv&{p
z6Yt>)M0L4~#oeXWsbQ(RV!_}&8ax7>_z_urP4B}J#f-7^IGoR9$(~Yox;bpg?uu_L
zQi3{^!S-;(5GI`l`AC7jwAhgdeC=2!{X{A7caA#jl#lVFvOQKZ3+~A+g_JsFnACpJ
zeBh6hV%8(^Ls3OpecEG3ffSo8*&m0Y7P_aIWhd^wkk`jXw7N;d%GMNZbnVIkly}g#
zRKUCI9(H4P_0b){R81`7ytrYg%pUn-J4_TgcAP<vQF=hkEIndkGfJD<#}`yd2F6Cz
zlZnVfEV;GGrZGadq<f{P_TB@0#%>ol7kzWvIwF(=bRYcmE9$p<8(800mrfNWVA4}+
zOBMMS)f6uVRC=tbX7DVmFna_^Kon`*`{^@U(Usz5hp!ND`;vEv4i}W8c8-cm&s$~C
zC}!z;Dtu~FABXN3m<h)8)ckik@@L_e&?;R_tGEbh9kP2=HT%OYGV1m4_}NUhiM#a(
z_?`4vcG_<m_~kIip*s*VB9gYarre4xu2fBOBbE93!tCN`cjI#~CV8B}q@nD*n~zc$
zZLMN0i-W%Zgz{WKaWv*o6{wcc;eJS>q_wfQVvFJvn`XcKKsA>mgiL@yVZOcr5P><&
zL0-q~AT%6}r_SKu*Que0Xy>ij-=|Y~WSm@Kext+(#zZ&P^7*K!84*ehA*-VvuGOn$
zb6EPwR4D^UZ)b#+KeBzP+5gDEtOMncpRZq6v*))%)GXQf)O{uaZJJ;@CUX%8@EcZv
z=R*}lClKm<A<K^?i8D|CwErESyCGs)R^#ma8~8jqF)OB$(v*TBD7l8-k*fI>lqJN^
zz5;HWl&uhDyIfiXrPed<#hmm70xr!fQdIV$XE9aMiz^uSNHez5r0ETeMz9P?RJO7V
z#lnhuPE`g@0Vl})-agr4d$_0=@($%YLo;=(;)?;;k{ByACM#d!X;GXFEqvB#(Wg3N
zbGMFy?Y*7UIAUf!-9jS2J~U?vi<P*n(UezDF9r#TLKL`DqC_;4qi`=BR3S{-Mk7wq
zo7<mT#3lzP2d%RX-j?6j%^hQCg}46L4lCiNe?tMv1lpVH?K85fE}Ymx9hv%e7&?Z}
z8jmR7Ie(F(qH(<emG#{FXCuh+X4mxMY=~3=>sX6e5?m)jc`#s+kGKYY*!#SM45nH9
zX>tfkWMC{DFkn$exCsKO#gY6JM#3?y`7Givyn`%LF~XF;S~01UYG|SeDP~ZgYZyd_
zB6yQ-Yk+kKzPD>y@w_MfsDKg6lzde=Mu@_Mp#DMVqw%{7!BBL*H)Z-oy}6r8d;?pt
z_Iz)c6iTVR2w&Nwm<(ExU6xAg=^h>nu$QV<7WI>AVQ$@CHj`mzr|h@Rku#LKaN6&-
z=JQq7EZ#rFqX!Vuq~<J)%WAJ{iJ%;Oq?exQY^IxwFA6_$u@{%STGw)6$vw~PL*V_U
zm25U<RJC`V*S5Quns=Qk6WR3b5g9M{HWM6q{UU%dL$o5svaI`k6MBz~2R0Pd<}*Ea
z%5@uGf5TJTG&xv3RE7M#8ItkiG_v+)YR@i3J5U3c*3jcNu(i|C<soH(<*qhUW0=w#
zGbOUU8dS|uJi1a6S_(s|p_x|I^c^Wt0-!~RqB9rXwpRURLc1O7M0)!!H`@Nddp83m
zccm9LR)h53B&zY~s%+N;ts_;MDJ<G4APGi(jw3x@&z*qfKH68nLIERfmCGJtY!h>2
z&jhg_N|n~xyK5N@j_8KSM7@p-%2P@?f7)H4K<lHOC+J$*hT`ZEE3Jmx)7S`p-seWL
zn%JFpJv`fBg?bE2c@L!VgdM8BMql+NM`gAsPkpR<fwU0$VGII_K_2)H+XlAVsW_?J
zvk@??7AaJJ#_4ZIqXym}vwT8a#(L-?$tuUcnAgCjbXOxYn5i)d*tP;nqrGFCIY+-=
zP<Z*Lvr#*zZS$w#FSpn%;rr$c<ja0su({%+9W<TvYr08|qY%EE=JD0_1COui_L8zM
zmiCHj?HL0d4#FgR;jLLu!~NB2Hw{P9glhgp^)DAM55})do|gRQKe(R`a<UzCRr{mi
z;23lYX*3skVMBjXb4zDLS@}|HsCE|J;3qs3t!ZfV6oI%=V`K)v6jjT+epHvA6bU_;
zq;$qEl0X_0Kzkw_vnIFxqjJWt80$r?dQ@MKqN3^wH8rezj151*4t$s3E)Lbo;Q$@w
zW9%@P5-*G8YPvuOG?5&dJTFUAY=Mm`!g+T%nH4J}OC?vOQ+60}|20$${^N%+t1uzi
zOZ@oV@jWVK{B{^{Q5-#}8MgohOqrLB0q*sP1ZnxYGsn)GsA9k|;5Yh2)F9pz@+hJ7
za>mQBxT0zkT^7^x*S-61tB;a`(U=8!Le)drvPR`spR!K^mI@LtRV;t@oHQ<UuWC@_
z7>TZ~TKbSWe|c&1YW~)(W3WYB-zDF<&t$rsr`k2J;z?$0N_vR(wOk?3xTm&=k(7dW
z%IxDh-5Y5;8$>&*EThfUVe7Atx8D$KmR-NU9jbu&@nUezVzYFyq(U<+3*{~mSue_!
zD#Ji%EoN^K=PqS=Z-7}g`xR;)-}Lp2DmS_*QvF!uT<{6aIg53FFo)9?bVQfKLo_vR
zkFwd~!lRJh{)Ok*{az;DUA^_!$>0}R1R{6dc}7=x0=V4YGw@%vjalVzAhl6fCH?qx
zGplvP(Ov2gu*H*8j#;L<U)~s3bUbeLEAcYEmY6mT*G1Od%7y<n+=}P-OPfVIP8o(P
zU}4!Rdh%%O2QJeuT_iaZf+K!Bq+w%h_jPP(nxa+l>3Wfz$_yoiIsAj@DWfRHdN=nn
zRy><8E$7oY<rzx4DdnJOorgiNf0^W7C#%YXn$YKo>C!Zjb0rKJ(q^(?Yx=I_#;o3S
zDpNmhTl2(GmFwJhGv!PqEu@atXM%Z1-Jcq*cqENLX}BU&nWHE#Y)7qjAt;1Rht)>b
zjd7~-t`VGo>RpNqSLg0ICuO{ylwR*r$LCO5er*PdCGgSnNQOw`K{}g=QBg<q-%wV>
zr-;NlSnx4b7|y72M#mkQ4HSfvksOtUKN3SA_OI#a$^ui^7wKgJh#|2KCXrzX-;Mcb
zO5JBfD?O>Go#Uf-jtpTw!LWHfCJ*J!HKu2WCd%<q%+}Wn#@4*XRbVbNft972tF<$$
zvXKk=!P%EO8xhmYLWcLX(oRRCq!?Qh42DBW<H)R3k?s}*krn-_6)*(h&j4E-kS9B8
zlnS^#Lm~+s)!kUd)*%w|+>?-jy~CHySUZOJwf)&sk*aJ~^eBe>ELzqpcmuYF%FRZT
zbLme`@{=FW`tN~-MSk<as${cYQ`emMCdO3WvPh%|o;AOXTBx}4#;8+2K%7DslL1w8
z<Y%EQlwRH8)G8c&g4nT(P+`}|9`uLt9|C9F9)C$O<@Y!hroyZfJ)mT>n-u26tQJ)G
zp7+#k?!Dj1WCIl@dqoP-CBC}k8Xf*3>oE2J9sE9;vVjr6F8rGb;do>wy5&}zVKM1S
z@^$I-+pOrX(5vmuTz69%L(W7#grZ`X=09!sm>|%0GjAi^XXffFEem{LeMMr-@zw7k
z!O%^jv=fVB7On}2!k!}hW+O;d?^MuLfz*4W^97<~H!dSufVIH)Kkav#*@%-GRPe0U
zdcoJzgS2J6KtcUW$$jPOs|8~UGaWbgl4Lk19~{H6$z^&S+ly(bltD{+<L*f)yh@w@
zBa#E_5Av8yC(phf4`($Z{i;bvIs<j;PNiKuXEg%jf=O<U=~*Wi0=>-14fd_BzOjZ5
z;R!7#gbD_1*73b)^Ee1{bh_!)5{f<jK!ZAwa!?7Twi1)&tDBtE@f!aE1}(fvXx~_M
zhk=_tzaSQS^*)t@#shEPlEyaodz@V2xOCAHkv9&iN@2WhZMql+b;0dh390sK1)auZ
zq+i%F_NhF~a`+gNb!jHo<>dYOe2IH!?b4M(P5Tp?DQ9~|=P}8$wb3SnMRTmDPc)3@
z?=Qv3ZUPZw$*|71we+LmN>Pwe2>91bWaKchF$ws^^oon4kz*ia-Q8iu(LaZPAM$7j
znF|qv!#$KPo-9%j!s5`bSy8b?MqF62B|RBOhDVF583A;*vDD`arTG1);g;b08<+gd
zLMyhKaPjzKE#I*@+{=?QIA{#jedm22N7h}Aih>LDw;h1~cEwh2STT}$1vL$VwG-1t
zb}`Z<IwAr}<4*Yyfg(1gYc)xu@w{8VyJr6+emt3%nEE^jLs)g*4PLl7x;(zUV(W;8
z!6BIewh>L*2-|+ssu&4#0*7C$EsfDZs4y>*)t<lp;MS~^%|WQgt~8n)F)!XdbTf~o
zj$><7Cy!5K{#+kYuI|1)-O2o;yBAg4SP%=y3@$#oxOjd>2NVTlItQF@bO8bc#Axaf
z7F5J;zwjB+RD-rpGxf3vgw`k+-yCA7uPJeTh{BI9<8|*V6k~89??qrJZNRqTa8DB8
zvxbD6R7q$Dq~hJpMQTBWG|de07}38dY!CE86gy=xRS37K$d$#)Dx|MuiV{HJVRb0;
z*srbY);Q{MIZVO4G^K$-ZAEICK~K*ZzZi;Kz5&EtYjk&?lr)BcWjQ`c6mvWnEkBI~
zSu&xV3TgNzk5D03M!|;|!nk;{Hs;RcJSq+z7Dqq*(7G*}u)gSW?TW^&{;=8TFB&?l
z=NDY={i~uH>*s4?8sE;Rxq|!Q`-=rod{POq##H1ogv8i%cHFSAHFnP%Kp7FU+(*yh
zURYGIj9$qVRZ?~aCne^FF-b_VFHCu<TOuBblJ~IAD*CUnW<d+VjXHz<KUHCK`i8^#
zu&FQz#e>8&ZVEAk!DS#!Ty~K5JxHV~R9X5C<E9WUs_!6yFfy~6ic*9l#4pt18GiE$
z0cUKap8y9tg*NP71mXzlR<oc%ah3s%6Afgfp{bWe;EZBW5BRG1E62visZjszqy)|<
zQmytkr`(#93mT?M@Bf;alO(^m%+d>*sYp7Qvw8mPcoF0ESmDQx6nhkpFZb=$uv}hH
z_Kww~s|o*=n*7h)k<KjB<)Nsj1G#TazQu{})3v$jjratQA&a`=l2d^#)x)BMSF;^9
zMIolYW2b=Y%Zt^=pq$URXPtf6xS2N-)rTEs3SUdGcNY2Z#KS4llL9r9QtjDqq`yCS
zCbWV-JfffIU>RjEe)E5(p<%m1>|80Ho0xwW=lGd2-<1EDY7W=|*KTUke@FMIpu#by
z3{Sl~_zbMQZM{>hJKi~T5lbi@MrtS_WaU#vROaHp&;tJ;HLkxrjUzs$QxTh#s;jnA
z8=M2d*IB6!p6U9+u+*#&c<C>4I@xMxyw@*&@r$ELZsh`ewuV0$D|~ZFbHUD=Ekn%s
zcvNucSkS~E5GU_YS5}TK#Ye$2!8|B<3;kj!!S57butt)O$u`qgvn&+wkZhmah~0ex
z`I`D=s#%@qgImIwt$M5aoYUlqm)_D2Q!hnuMZvp8wW~>yTMdhoIbn@<!=2;Byy@O<
z6WbQ~*_QjpfNPan!gt1eQ&mUEA0-cmUKarSdWoI<Qa^~XI=yYPYPrdRO55JgpJ9r+
z&rTis-^(_dD*rM+<0M}^J^s0SSG*2<fc)$vhWS`BbyKl=MlTuvD>F#vcO&;lDzBB%
z)a(720ob48LoXSNY(tcAj8;RINwDg!KEL{P%kglx@w1=m+v#uX9hCzPgKV4phb@y?
zEt|pmz`2LnAL~!&E_a;dqcXl+S84gXxi!ZnXX^P>-<*G+npj_^O=SDdY+!wZhFlI8
zK416u_5#}trBVe^d2b(oJB)eu4OvY}{Z)qkqy6giam#<{dF8=8#PJgNkbUDSdD8Xv
ziJ$*CrYmCf^=}d{g?y^pTgH%(?~J};4^dsC*mXaX)JLHdJ}yI9iO%=tt_QBGf&L02
zT~w{Uzgta4PoK?2A6FM%FVQkQixuc<KkOa+em=c0-*L3%Ql*^S_)X#L^6XzS_vy!m
zSD<gm?<?Ko-Qfty-)A9DM+eQKO4#_bbCSQBFFc7}T$Dqh&>sMc@q_1Mx#{ff#_znR
z6`wpWT9=UEY)vMCRi&)QuKSL~m#Yqv2|KK<jVfusu;l@nz#{O`5Uk7JqrZSfQ8_=`
z>>T&0t}c9eRX-LyKl^7d`OkGYOG=gwNV+~X&#!mo{P5|9Zm-7No=Y5`1?5=Of0^l>
zTDbj@`2NeX<d24*ovx=>mIs>C2QL<b3xZJ+B+jO8{k^D?QVq60ZjfU>Vvn+Nk)XP^
zbghm`{y6{i;>E;u;JtW`d|8)i0;&Zx`5Ar~MR?O!H23JX9p&!u?ND-Ed-OHdr~b3d
zpQ0K^9~_NU6SmeiPjj&DfPIYC%P$-&rVoN&y&I;Do;z56`xJCVz(^H31v-5%Q|>EL
zr-p9Yvy2+BbcC7q%_ng5?zlBSXqVtI_%v6@<^K6w17`9GIoqMvAivUCEW^>V0j(!-
zquuy*Nio;5E|&3Gap_{l-Y9L(2_ED3R$k>NwT!KGAIvnzHydpU`0rdcu#JOVn|?}&
z_KC|qkgWS)UB+3pPkdBQOt`Hv>N@!NHT>+M=BL%T-thPOak=%aPZdr5D?T{+H_l$`
zo1-ylGaIKJ4Ni&Nw(GC6J~#K@W!bE29jkFw_p2$8xn;lkW$%(PLgZA(!P~|EEf>WF
z%D}AEgH$SqzEbxFcU@9X{exD9ch=|6$!F0orA{RH9TkAB+wzb<zQ?7*8;rp}+_xYN
zU(2M$p8bqjz$>jN2-6FjIY@102BPSNCj!%lT7iUmWrr*XP`Cmr!jXrd`l0pLJ&4$u
z<ey>8kIXSB*;sSKrb?0d{j%Mh;33G7LVkWVipV_pD1IPua;_ghT8!kqldZgTa=ivu
z<QG4A)kx$~bZDV$7z*lG8Ztcnh+;rzBsL`Gr3U2s5OwTY4ZFB-`mlkZG%K21OFBFv
zg^-Sc$V^&B#+``ZE`riUx+tZD1ErrFt-J8zkeh^(k}^&jewLOeNF5$~0)!WKkAa+m
zTeelUHA99)$!pjD(l~BC*>F;{dOIvyG4UpD*A4nE<Tx}@7b6knZPcJM5s#PMBC!&U
zf@r(9R=6Uzl|f$Sn{Om&Eyw%rQ4Yw!^sm5V)8$9&cMlibZ`TP497WSO^<-6x)lO}A
z=p8VWb;{Q@K60HNO!L_b#?UIzf^+ds89cytk&1Kg*1`G#3_EsJP2|X^Qv?K>jy@%3
zIXQ8(EWlynFtOuS6fa-hl8h&(GlLs*Pa22_QrG#6Wf`twFS)mt;l{W#<nf{6e5#xb
zeRf*h=6Ge50|+=TL1mqA6wcXwh*sukiFGL2c2?Zk=NIKiJqS2TaJNbNjgKlaGm)<a
z(dL4b*mBp7JC3qvRU&ZZOhqx~ee*%8D=j4?Rdx8$R6|#Hm~$SdouHk%q=aJ<{@<o(
z985F941{$ewhA_Vd1klPhzTq1g`k6WT?+Q8#GMg07c$*2a;q#`&V~X6+weGkAsPbw
zEhmi}G==vTJb6&GV>b>Qx`AaWIQqos$WkG4t-?WI7B`8ltjAX&IPBCNC$U7z0~_=3
zJm{eA?vt2ms;4BfaT@J8NOQ`8^L2(Nt){`01DASM)7DZS1#B#{=M-atisu`O(n$k%
zHuou&h<V|IW{go!HN4U<9j}qXqz;gF(DL6Rt9ZFkRLuyl!zq?}rs8Bw@q20JO!bF*
ziIB(B&-<GtYuR>Pu~kkf^f!y(Lm3wg6xmv)2DZn&iO7sTc-|z^FXe<vHyDWyP6@e$
zTMg$KM&{;23>d$5yTQ;^<wJ(kP7~Tx3RiRd;I^is;VlkqW}~gNvsSiTJ@Cm=y#4Uq
z3SShVy05(`!4$$snnq$|Ns5(=xJJ=8n4nyPA?s7HlOmcy77RtY$0frV_-XFN_mm`M
zD-WMK>gEOtV~Zt>Jajt*J=izWpmK|l=__{d77NLGz$etpj@6ngP~&Z;7J@Obhnch#
zFj=i|!%J`z2!wzStmY*b(0O${vLA|j#WP8}#M(p{N-oia<Vt0pGW4Tv^1F0j5oO_-
zD~-A8Qt!99`q+-F_`at~?IW4b&e*9k>^->4^1%vFG#r^X!3#YbyNH#?u%Vq@H_^`&
z3>0`qNQ&PVvVF*JR3*{=C~{S`du|;Q`&h>AKTuH~r5eBR69aumN!-iFukuV_y!fTK
zm%%wREY?6VQLWw2x6`rO?1nRC{M3o&?8Y-?Exiy|c3{G{xpl*bL6((fBrErZzyAo_
zO^7Tjd?LIBtsuF#@<anGL=|?l>S=^AMuo*MJ9&#q*82#Yw`<LZ&xk7R`u&7j+l1uE
zqe|RAM=`H}$f2kl;2ETLyUue*rWHlr8vX5U0%wG&Sl++UW*8pQaROlZowRtZW@<jN
zPsZ8B(1xw{eHj90ye#r7;P$13%63t_PV@79q1}i4;+G`a(lgOC73g}+&+Jxlt>1`W
zk~o^g7QbwtY!o^HWRv9)m*fuz5R;cWJIM+wzg>x@Q(aw&w#gIdz*Q=2ZNW7!ZB1iE
z`P%C7)uIK$juPHd%U&Vph;M`w>1bp$4OuMPM1)<{>lCwCjmV62GMW+LUPb7nvs=AV
ze6P7m&<S!{edF1@-73yL0@rrxt3d0qs{9IVz3iO6Vf9A?E#^0dX~daTpN}&4tyCPb
z8$KbW2(W7|^`P+8tGKEtx4@N@A-BNuK9CEx3DMxG&lH0BnhTd?;_3s^C|pOdoitq=
zVJ*(ssU^Ba$0@cZb@nQH7TA+~i)?F6pk79-4Y!tX+Bt$%&P()X9nP%tE;3@!DS_Kq
z1sa}^V8yDKf2F)P`P&h&o7{#nXWeS-BFc%thC|DU3+*>hB<mb;#(6Bks!0N#nw_lh
z$4?~mc}vkYLB7(;LJhd)k!=NdYP(f~e#AwQ_(mG>mmD&vjID+E2eoyP_!pOouDbMj
zu?vtJy;prj3M|lD;J;E(f%Th_0c!cT7tmPOV0wxJ6^rhc47Y5K*hf9RKFxN}4<k)f
zg`V({v+Z=ZiWl}LZLN4%GuAU3amqq)`@<pCEL$XoIIwlqk(N%<810RCSbg-Gn?NFF
z4GwZ$P2}9Ba?0kTvQQXR`gx0XA9D!{)7F~VxlFp741Nw?osjF%U<516R=QCw5pG>=
zB>s^peGmt3m%;Va25IWPbLqvNGfQHHm65yZOzs5j_c=XEHXKbwKK2o1I62b5B&p{?
zw7&O5XmJ%)?XE(gLL4c++5xOSD_qH#vQT~D(4{S#X)nw#q5Fy?lyrr9eu`e^eeg7n
zIC@wh!FEzQ>t11$QJU~1nK|?t0#&keb32yM=WiD1Z#ZMxTic9o9!}0_UOQhUglC-y
zpcONbkbX@9-ekOSA+>+6+WTI72WpimWJVX|{rFfjH~FD=7Vq-#BwG?!(1FTvbXvUf
zo$&xMl_NB5E?zyoCBgq(Hzfa&h&l3ZW`YSn3)1?H&%+M61e)c6^<*d=-QR_wb$ZBD
zm;VY|9eNOv#R);~FTZaMTn#ZGNTko$^8V%7PTVwdF;Dt>foxQyP}$Jr6J!)me0cBB
zDbrT0%fL#YD#<acc4E{l2-enoPF??5Xos6}hpleG&X}*+?1*c;{Hg3oy0kv+@yI?X
zcLGzD%5`eCX?)?}zIo-(c1a6I-waMqiZ6sER2S<fT=!@imp|Ig&tmVFJ46V-<DjW7
zw;g??mgrFaVf_rw$l1`ww38?wXnD=4eynh#mp9S9lTz@s<NVWn3HK6eHj9wykF=t_
z#HQnj_tu(2-EuWy@IuVfg>t8+<-nbVcbQGYoa61_<QE$jp@$#=+q1rep~prxA9r^(
z{3LLTfirFu?+1g5*&OE|!h}3+lPywj*F`quFHU6x{oc9P#k7LFr9QOLJ`{@&(6QXP
zFlcuV7lJW2Fr%V^coNI@Ke-o{o*j`_9DlNJZ&%;PC4AGD24nSx1zL6!XqUaI9yy~E
zB8ZXv3l)_6OWhw)=q(HZM?Jn&?@Sv!6W?V)C^?c7296Y+`naUUs1X7kf%Cf_XrBPO
zBHK!0*g=`)DiR-w`&o}AU457tWA7&vHG;+rGvtdq{1H_xlH&NGC4>5%zT3V>Cr+Vn
z*gq&EEGai#_=JYGpIjn(u+2||mdu+=4sVZz1F>DmI$_O+JAA3x79njkD8`BD3O$Vi
z^eAh>a_aCXjsXY^Ovkvfn-YjAv5-K5{+So(77AO==rqK753$C^hy6XV3kv>D79B~m
zv5FVkOY@)<-E!HZTO`yPKH9ijVMU!<1I_v!X&aWwgt{*5uBq>niQ6VPJO=L3I!o9^
z;yv3oN*7Zjz)&I3){3aIg?HP$(MO&rheecDg2~a=3YTS#)O}M(lr~;yW@<!h0}Nd8
z9ZkhX46l%KOQ7CP#pVw!lNuB&`N-FBO-+r^By{mwAh`R;PkaasvK^SPK1;}UU(3hk
zg?8{ZqFA0KkVs?LPViaeh|&@f*aGtDmq{Dy0r@I|CXKun5e+`_nF&^B2@|Q2qO|Bt
zzotgmfMXj5dR2ciW#7LPrG<;=pBnl2BVnS8N<@^_^C}d;T+`3nAgw$>>z;@Yq|Gqt
zy<=D<$5rjQ>`IZ#b#t{MiaCL*e$f6#&h4>hQHWbzFKDr=oGwMHQ2|euLqj;NNN@_(
zhu|SjJGDEx4y<SvJ=*S}wMeqQs(O0p30nX1w3MzZ=}Aj7sUGY)AfuO$<$Wj5X7-*`
z(;c||noIcgR-Qujea@fT8H286O@G$`X}vt^uXplJ*!ArOsZD}BACnYD@h<)wcs<&3
zX)RH@Ya)u$figcTZTEZJDQR$cR}Tyi`l`SHpTGwcz;~*h;^4NIK~h6gsG+4U1<8~c
zjUh6~cx@V;Qf|ai6SOX+_kJU$Xb`zIwW2Oi%?m;@vSpnj+^}FmvgGcT?H%e*taL<^
zB_$X(kCf;s@@qC1Gd=l4G>PrY+rdbiZ_qOo);%r^<4-=eo81q^#~__{wd;qU62qv7
zzTHOhNGxxUHK($H-kRrqKo4Xc5|*s@wakma6R+Bi3M<z&?sU?YzYViI9lsB~Ur2~Q
zT+VMWW!WgCE;1;lgG{WJQ5Q*@qz(*3Dd7?6GAL<yjYnf3wkWN<2o-c0Ss(nW#6y<F
zIBFLy0coTTOT8u7L!+;KkqZ`nDrjfcp07b;)?hNx=$1m&f;^TcjiobcvT5dDo144i
z!OS)*QQ@RBbUnjoC{bY(Gr-blX3>e`OJ$Z`*;SQh#XwSl4u9J97K~DAWHEDU^I|xy
z;_OH$r4sz?o+4RNjr^lqD2b9xikQ$C34=-snB*nox|fSORk7qK`P*vJXtEB4X4G{q
zT5K{0QH^wfSuDbl%mtxhs4^aCT`c<7Aso_!d+@Hp!P`Dvs{AXsS3zEhiW-5}ja)}F
zQRC?f%VhB-Vvm0H=ZA0~y%ml#ES6Ki`xS|FTq<64DcqAOk&*NYc!W9>N~#)ebiCYM
zDK-);f~lhD)le%QHi6X9_J!DD+{%<&m_cRQTGHHUp}KtG$Fel>)r6h+cq>Xxz2>Xz
zaGDp2>3FA7`e3>uyUU^%h-fj15@D%D`H}HabVQmA*K6KVpweW!*}{lONH{Q>!D^0x
zp`L~>QVQ)Zn#BDbq$+iLRdg8sE(x6Zcmk5zy^>PIN(<ymjS}aK2FBjp+1Uqs(^g``
zm_rC+lCezd!Wi&iQC`H%;~Elh1+VNq-V2BV-hmTcG@GqFqO?meg7EmKo{Vj_GvQZ}
zO$m}3Z#*@)wk9#g=mqx&DH<l#!mR~($Jpyh>u^;ZDH#-Wu0RGJxiJt_drA_vB7eU^
zzx|@HM$)ioR2vCP&B}ynX?;3cE_45co`EQC5rUL~pd>}M=m)Y;tNO4y3<3RHFFBs<
zcQK=8NCm1$v@qPH6EM4DW-bJD5u_Soq!aUu1sFD<25T-s^t4_l-xpcEd31_MyeaxT
z+2{xW6AnkjGAJ3t=EVve>BQK8H5V&dW^WCh4iayu8|eg+^crZ~4s6XOij>-mL6V7K
zb0Ec&eT39x#f6NL)~g!5#j^w##TvnGNdjDe*&;gpV=-F6+v8^F6`+XPe2mt64ixM9
z!8>E72=+utK$YTpt9nEYh6wI;#xOJ+kh^X@B7qX(+b($(#3pV;mTXLB&0Z(fOf;Ja
zcU>;>r1J1(J2AouIm=2jJ<A-H?CJ<(!imA%Dl-lSBScy$QkLu+T>DD11tdEb{m;I^
z8^L4;%i6eoHQ;WdXb{9B8-G-10K}k4;K>6ln^Z1QvQ#6hNbCqiLbFmMsY}sx2j@)u
z#({aCfKmdnb|ERtn$hPQofw7F;gyVG$iqdFP!OdxgMCPlDq*!lATa=YHp0A^{6hVp
z^({<UZ;pvBw{V}%JeLenF74~u9l7>`B3p6$ek;!OVhu>&!ZQUYV{&W@-C2iD$<eci
z#N%xS5kcFH=Gw^zq*q=|pMM*#PfFlOA5CKR%?q-!Cdux6uBO19LXGeiVx43k%;ChZ
zc7MaBkbI?Wkef#pKkD&@vS#8TrBLVqIsB0VGgiq9p;|K|ap9$YMTxn2ZDRD`o=9vw
zlTRcg1JNmp^R(9|U;>Fy2Vc&*{Bu~Mo2|lShG;A>qiapI%qK<~vYk(kR_zPa58a+S
zQqNO!f*L)Zb8d)96ST^Hk&Li*emZ0?2d<{M2$N7sM*Un!3U_d&_^6XE(cIF-(1?>S
znS?%O0_)ia#RM@lu24X!8+%j@R^myK#i#);1Z9UQ`g}@XJm<JyCLz(r1yIt$>V5$p
zeQ`##nVS<(cfEp5YPvWvl=^hpU3%4s%K6L18@EC6VX+?FI|@tO^gA&+)s3cpk1+Mk
zYIgz&LCnni6QQ;t+YU9hOWbyfjHFQO(I5nlvMb!s`e_BTaAm466y;zrP1%hmhQgqP
zg@SoY(n!>v1P$@xPcAN+driu>`WGd9GHf_AN0|8FwybH_RV5>qs&{E)#J@DyTI3_K
z$Jz11JSuf*f{Z&=5v1rAAm_L<GPvI;i!*3~q~t46V3cYJr31JW8&E`&_1XK-5ys_`
z{RaYYB`CGH!Ut&d5(<HaCl!~EPm4EP9wAPCI`q2gPohBhK(Y1qdkmX^EfgB4zHpxc
zyov&j`@jnBH(MB@q{7RJue6;DG<&qhT%B(sV~_}w-5L-G>0sDuBO}R2Dyg?<ko<v4
zR_^Y&ua0Ibk7~)94rqF6X}6-nqUek}jh)jUNNcq4BtWJreR9_XY4xTo9~h)%n#Pop
zM>+%W==k(C!UqOem6Pl3lu+>qYMG^@!{zAhd|~QXq<?Uj>V+o^9V;i#B=q4ikyo)v
z2gY5_;x+q_3`2O;<=He=Qk0S7f>oy=+w^5aDHfdRo@IWhETTFmecWn<oLh9maalhZ
zgkN=n@hRDSE`%84C)L9Po0p_5^Vm(xP_c+t%@crCM_fNHEO=wxyO%D}VzEh#+Sl-h
zh$yaN8={6pEjtl*D0u`T&UZjVxZ|QWPO{unq?|<v$WUjtA*G$Yw;VzaPEqbtWWc*}
zaVIf_)O-O`a6=OLm$39H@=w|JREXM%PXiYe9EZ`zCFCOCurqjvudYJJigq3vggA+n
z%e;>|c7*lo2+-DOE=G6gb59O0D6oVApFHw^Y+3TY3VK{h$e@xG@I*XFnv`0Gwc^$G
zfLm5gr;u*NN3>05kB-NpUKM2#jdD5|OQc@y=<^&g<@yO~+-o>00JrkV%sl}s$aV&X
z{kr3+M3d0zKP^|iLmyjwmSWL-xYEp7p^Brg3Xx!|`3)<T3wH<~PFC0!QiyiAvn2wO
zqGJgwwS}__^P+r-d40(xo}5s^94<joh?=Uwr<;6h=;kF&Myi2iFZEGCaVO=gG!@n~
zvJz8jlRRm^6*L*8q%u;1qzoU=p6~s1;7{(_<T%=@C{u0NuIa&WLRoB#84MGqZU+<%
zCCwNYN?Bnq*a)9?iIt+Oms?daQ~qJqR3Zv=ByNY+=6J>ES@E%Wa0+tQ7iKSJ5WQF-
z3#@~NG>{2Rd?mBY0!13jI2u$`$2dBc3YOID!a7A8i!qwXARQw*Um`u?Q7e7m>|OUL
zTsc}Y+Eds#U3o)ZjoxoFZ9)&T8$R+7&(idVX_bA}L<&B=nMG(O;oabpe*SC0w?>y)
zs!>(HKUQ|i^b{0aI>3D@I=SqzV$);JKCeG7?$u$^kz9he&cI{fDXQvoVK6nz?ul@~
z)HbD)UN%Rg{2--T)HfK*tkKNT@D`HA#BiSM;r$CXiHL&%w}@=Wg{C@>8x>Vo;8u)S
zFU67!zuNbtfr2yG3E86>Bnn9gAMq(@7vLd<rYreKKM<y!&KE-Kk_5hoL`8b1zqpF2
zFKx68y{uvl46TtF_p#x~9g~y_e;jvVY9naMSFRd!>M*XB;)Ug`_^Mi{GA4k3UV}D;
zz|oe?3p-hTtO|3bEQa4(<M1W@Q!m?->WM%b5+CjtcI1}>O{}t(LGmefV`*Qjh+o>H
z&sri!9X0qg>L*1_XHy=_k6-I2K#v++1YRZ4Yg3Cayxco#0CMMAUogFPIJF_0QpHcd
zol+%ACZGm+Y}OK@s+i=>>n@(z6LGCS7Ed>A$?RvG^j^bUJQGgtMqdzr(Gpc`py(Rg
zPbY~U_m4cQqXs&<(&2ytbd{v{+}z>|mcn(zD`Cds3rbdp4L$|>N%SSS;tPm-#|=IX
z)0T^BN#30@GU5x|At*Qc!!Uq4lpvL)7G6(ry*K2D0X5`fUoB5{QYjrfj8&58HxUEa
z!Z>CuQT;M0RW?0t^x<;Lhw*yE#4}NBjv9d6n74$i?|*Lqivjj+F9)y<*&a5eGgiMJ
z)><h(YJkXkiyun7w~nS1O?vLV^CKB;(Pzx~&|j=yjC4H6bMq=&W!|*QSl?GJmT&T_
z3c`(E2)1<XSM&jIJp`qBeS2)A=~u9zmqs`6+$I@QCH7UOl!fK9`h4se_u+0{Iy7X{
z8W8ZuH_8a9E!v#e(=YAWQs)%NCak*Bl}qg3o065KX}R-3=YL~x1*cEYI+VO|gf*E*
zjo{a$!km%KXX_@4GgA_&KpvTv${#2UsZ08G^v0xpr9AM>=J$dh(x?svZ%E2~Mf`IX
zn2+%k_OId0A#+Mz<8N<O24@*CfwNWYtujlMWGy`ypr|T2d~8gXvxS9`N--9f^cPr#
zv-Dk`>YbDn`cvs&K*uw<$WvG#>Y8lYc&pTzT)zu~o~ho%E36NfB4YZ_D(|YKp`;qN
zu0`!;vMFTGd+c#Am{#Q}(q=OI&P?O&O%)XFjhb-D+k4O?8fLEj#7R!w<s)gJ=)gzH
zq+x7`wH`5HD@EwYl4X<pL3Lj<yYq%k%V$j;UODln`L)Lm2a%S;+IZ1dn`=y+0Ejyr
zMBj8x4o)Q=Ut^$gd+H}<CP8_9#ohogh<ZQZ4C+j1k3h)4X>&)|>xU>B9=VAoXbY^#
zqo-~@Du&;_iZJ0=d;Ha;5@m!;W5}?E3a1jes_$Px8!~2{f#lnJ-nc1{TTa)0!Q(IN
z#+j*$wx+U|0effBi??Y?Y5Hq59;^})7-qNZiigAYaN0)3arg2&gX#CTk%QwwY4r(s
z8z{sqXQv?+m$Tn~3B+1=z5AbeH@K%0LfsY$`<g2LM*eF&->g6_k!^&rS!ZR1vF|_C
zGBrE3b*bBpy0Aht>)!SiXMXqD@Geyq3<I;xI5URrbv%PC>|Iz<n8#0}aa244qXnud
z+F~H-+qZ?GJZqGAT?lQ2k?9*gvUa*S`6Vf)KC3a*nQN^UJsztPSPk>7&qxv0tz94o
zi1R0NMSo{nM9y00ektn~D2}v}Gg?w<#j;|a){4B&^z4FyN>eBL3Es;7U7m@=s@N|n
z)JbXBY8!It4!@zN`T8nrBPGB0PPAj%^nnj#{!vbXX}T{~p}V?6KD@nEOD-g)xT}-0
z)#jh<?dY8(F>At4xrypRPtQQ6&nsUBSYQ9lNvK-1V$!)-xr*KWS|^S<ZB@_tr9_iQ
z(|**<hT=66?NuyKcK&dB@1ayNh7EEb4+*MVTJH&y29oDBYI^SpoiP$^13+?62hT$i
z1y1XwpaX^*p>{mkFAzq|C{bP_U12&WV(eSO@nmDmW%UNpH3DK_d9smZJR;UgQrIH=
zx%o&Z5__$<IAa(hgk888A|9l{q!Z>OpokpidJLOE5KlH~UskW8SSp4MEw>dHFUyG8
zF>QpwH^e#&8~-mIJlWPyVLaIp;ef^(CT_MuEZO-8)n+#7Mu@z|w0gZ_s)=a((v3P?
z*!bGLVqE%&SLafM6SDBSTyU7$y+K38EF?t{^=R^DeJmtlkZLn8rsD7i$`pW(Uuu#!
zYr*r43${E9OExLvD4W7=iuTyD--)q@4oDc1hdDArsUW2}H?*wb)-B}tZWHV-fX66H
z5hkaGdC+;Rp(Z2=$;FsbmTBtom!7|N6~IZqn?x;Q2=c^sHZ2nr#8<x9m#6MnU!wz6
zzQsha_VkpA9pyAG!5!Jy@72I>TjsJG62Okht(pvon4xf%z!4UH`<07{^(~}NaoDEU
z%zsH0_|zr<mz3>4scP}wn71e#tyO|0d(UK((SW!6;OWF+=mNQ1w@GU{$bmtlES!5o
z*%XPN9Fih38F{&<YV=W_+8{S=bUbw*%rjRaoMUIo$C!|UGdUW;TO@4nhQ`N<IT^e!
zK%^e9e+r^q&B+>7^xU`hxO}Twq;J7{N2@hrx9<{K7QSAlGYGaJqI`{90uPbNh9A-C
zgQ3wx^TaV{PZ%nOm}3!DM0W%rj+tW-)Wyu0fu$#Wk74B!B8!zQI0(uhz`JVA328VT
zZmKATcz<MJ1>!3iSo4YTVpdC20s}J7WEkfO1!{kV0&^w3;U|h*vHeZ6$80Jv{)n+J
zsrCp8T`_pS5p#NkjYOZW$rC4ILS}2+iVvj3*i=j+lM_Xl-gu)q=ERBcilwRR%(!+!
z071H8A__SC7o9n6ynT*Dfzz|ltaqZ%gVm-iejqgmdu(PRNHx=LKf<CaCkbiXMgmmv
z_Q9>tO}^KBEN9VFN2J6HcVUW2Ltm^!%KZkTkmfSyP8f2->x#|?>pUHzR;ZG?d_P<u
zp~|V2zxU|Rk5Aml3AVNjp<P*CT8<U)5yTQ`6)awdGCj;J$m=Y}-U<}^lAj3_+gZBO
zJ}6y&KqlX9W$*-3c6UC#v$K3qFft-<3dwo0wY)&)lr+A7z~g-$hT2_}FT0Yx`Pi^F
zk==1W2i<FZZJ4AgnfLR-Ns@LByIj(=o{8s~>vs&M?8ZR|FVC~vrRQUsb8vUfATi^^
zY*((5?x_0bYlS=VmEW8<?6$waKY(rHoOc~mxB1F;&Q^N|u3cxQ#;LGbI78NQo-Oyx
z9*0k}-npDjJT+Wi4(De{{^)wT*xXAx&5|_z{M5kvyz>Ly_b%$w&%X8Gtsg(WJmLCL
zJ01*s`tDlu(bcoB1}_Cf{d6mFr(y^ZgOR`V=fM{EGYMeDeXXinU2=fD`FBau0Jnty
zt8e9MN?j@I&zLK}x!(%c+7`FIVa@t_wL2+kzn~@dz@zcnq&u;!V#*}O@v?Os!t%7X
zSJ-XcnOR{sX%dgt6dgaRbuwXvUa8x(Xzs9_K;`M>o>!AR%ZWQU`L^S{G{9TLIm`RB
zd}v}%a&|J`cta@D<ejklaJu!{^=x5sZIX<@l}6K^=}oh#^TL;n;RhA-*J1;Z5=KL*
z1lU$NgqsqfA+|c~V(1zKI)o)EU-GjQC-XqTW{P$mYg}+O`Yd&QqxVPLTsdwb(GyX^
z!1>Fetj4FbK}TFF>wUwzcNX$e-D4Qxdml*ZVuCVrj{V<^<H1~;lyM68hxm77?)0mc
zYb8?gc4Z%pvl)N6v?U^8duJ0C_Q=089^u;L(mi?I+xP3G-1iNgiC>sr&v};cK?bZY
zf=Js-&qOGe-YOvAw85U5hI?|jk@>kE5;3Y0nse^`I>g|F(H1zW{!ppl1k~_jOE%M_
zN0PMTWr-m%m^*G3IDqVun*|T}yXLm}aPUadgi)8oJ#KbSlCf!7Q=X)`^+2+!MP+Gp
zXz7F=l;BJcTn-N}>0NNQzLywkjZSL7=nYPA?oMi8|G&evA_6QU!%La>B&#x1mbU?a
zpf>+t0&-piCEQ$dxB5#ACC(2oaX*lVUSrQB_6#p+UUK^+NDO&lBW$w?lcr4*#nO22
z`0(W=Sfl)~IyuizcoCMy?aO{>rCLWQM2dv)-AWb5n9=egV16{)_=^wEK5Tnh1Faj6
z4_Iv|abR=_SA?`_(KA260BLbF+gddr;{*{yZHP>SR8)-7^3`{%6SVvUld!ag>Rqc7
z7Gcs)ENVk_^P@{&-FPyo0ZHS&JU)nOLu)OCY1|!pn^q(^6=~ekZutp=$C`|m9^$K`
z*~ps!OV8*MA;66X$UL-~F#Y1qV?zq4mDvku5|P$Wpf<$uWppV`gfviw(NcZW>V#RC
zG*DS>s30z_fzg}i_J0h#$WIXee=v~Ijpr6HumCU+|NmzoS6)Kbrd3UOTEnm>&+U7)
zq3-F?C1N4cp8!^OYFfjGZL1TN{DfdkMoZFgQPQ75jFzuAttL#+MM%>e5!Iq$!$e5&
z5f(@FJ1M<+7#5rI6Z~O-d`Hhq2u?|B;B@D?jZzyrx%q3_9~&_kEhU9WkB_WQuJRJ#
zE7RP~Ja}3KilNV#Jzs_Nz4*Zjw%BV^3YlK?KSP!+``gE-6a(CD_CDh{&Cuc&5@7XG
z3gzLSAAaYF3q-jMJ*%KVp~&cPlvc3zsO{0@25Bf*hi{6o#4na4j_n4tmhfQryvTqL
zEAaq%=wM~OAgr;6l<)+KFKXskyS>OT7@F7Yoj^$(BNJgk7E{>EpV#!a_0cIj?r<0p
zrRU$xAA}8q8COI0>QMacS6&ptChPXR^J1gckI{`4aGv!zz<JvGLZ#N@0O!#IoaZAU
z;5;saVlcj}-%!`$d}-RY^9KNOFIK>NJ`w`nV+43lJK<TlQA2^tplBv=Xd&u)9ERDv
zB&e_R7WaK6u(ToA0U4o5i2`SU%~=YisWdFdB7+wpo0J*8r2YwdqE+^pJA{4TRrSN(
zPjUu?LswN?)ey_0fa#5F(=RuIL@@QAx!=$l{2JOdEcnb_u;TY?=-#6BGq<n!+(xz~
z*E3WY>4&RT7IKK?^Aq$UBI+5_zHW9TyPDu0hn=1ovAd!my%a}*#u8k%TfDi4M@sAQ
z9-UCijFfh}90iKNEJG_DH?3GeGao6nj%FS={r*_9O(vIy53lTBs%G5uNHPt9qv5t5
zQz;6RKr2#yh@dE&w6|7Ywk<r1hA$N$OkkD?!%hLo*_Ec#@bQ$RAVP8431@2xQ{?qD
z;1PUT?+v7BrS+y2lL`4!Z4vpYHQHpd3B8U2=4+E}5TTL(rKS_|@mL`a=4Q4Nq5)A+
z06#Y?la0I^>%w&HrZpn86o|Fd)7X@y8$lyu1|lX5q@`&QT%!1J?MhQn=3#o*(caJi
zFeqNX45w?88R7mxq5OklfHQ&Fbcq7t9_|{J8JR00#PPGcvl8HiO>wuoL~-N(A1Hb_
zXemUB){^EAlp+EdGY~NWk@^R9V_TZ?IQJLo`xnLJN6)`d<-hp;TJ`Ap*Q&B##($x1
z4*o$sL;gZ(h5UoMVf-Jf-v3G{t(2s-{I327>Y0=oh?uC9{0FrRK%M-9Y6PH8c=70d
zChU$%yhNF=#bNkq{E^a|wRBX1*8IOz`kx6HqY@2e^e#~{Kos?|t(EF6BnNjbj^B&b
z4<NK}{4$b#f`1PjejF^X3`BS~s!yYY8BxDHBegHR<CAi03xD^G7q9d#0pUoT);~ZU
zAI_UK@<=?ZPGKF*KH!UD_P<mxkSZIX4tSqYQSvulEyXiZ(z!qj8-z9s%yl$VfH3zP
zFHhMWf&@7Hx*$a>;LAwfH+(*sO+7{Y0C_T0aZH@G+D*pm1O!y^gAa)7X#O()piuvV
zlKFxN^Ft2>FF>u%`Xga<WP$!1UYiVc(E&xou^tJ2!2f}g0idRN8yT)6QBos`(y#Mz
zRP(0$3aasCQ1A`guRPJX@*;_zI`dLMoVIi$<D{ck9=SLbpQ$ItJG{idyDDCJ$oKu1
zIyO$KbouXA#&k-N8ekY7CynaNbNudl4kXM1bo88z=O)Hu6R3~m1t)pgpUqWfP=(R=
z`SQ7B4qe+*y~D**ev&^$=BI$nZRr%3NJsH~{=%s){e#2zk?;F2Re6b23Gd&nOdkLT
zFsLk%Mn&fTfy49BD@7G$&5X>SzL{`Ni(}Mf97u6`t203=QZ!D#%0T$aMGY3=n?U9H
zm4_aJzc6cfXC9%ysTw|<7b^>3kji3&i=13;Ruj#{xB>3&UQO(!haMe32c!`KCjAWt
zrc=rz;~fPqa#2|T<s?A4zgL3-P^JT+6rgSdDD6$B;^a-${`&EMK+-^z7-u<Z*hj*@
zSS5f9a@xve142dsA$xl@ihzJffEw+;00_!R&hmT-JRAToKs=b5<>_0}*wEJS@;8Wm
z?_iDWmHwo1jSatETO&<1uFk8j?a}oPeFs9;cEbki>s>wN+HBsSIJeur>d>9-u_s8T
zDt`}A+=pVe0$SP;1VdaaxY`lkFd(yOX(tdq0%bd*$Qz~?nIpv-u3AW_$uJ#9hi@mB
zjoMtC{4daqBN(FQNG;B%Y+1wA{%_*<0E0cizy>hn0>mk(K-F@C`v!;t;U7M=6dF-~
zL2!^Mbcy1^Kb*a(02Y2De1z#)N0Vll9&J%=lSxHwrkOwx@fBaJ)fhn#83tMiYW&08
zkA$87N#+71|4}0yAe=-nO!-d%KAtc#P`gp@m%sMpe<t!`-OZ8u>+UviCV$;MM~WDx
z-G~~H+L3vrr^xfy#DhAZF+$6cIv~Mlqp^ZB(FSVff0A)+;A&9-qI4jX0(sH+p91m>
z|0?GHvIkH+P7J@|Z-D}@G#CFA=)c^e`IEPQ)cc3T3ZVQAfS`<IRIfh;3h@3fV$CtY
z9sqUZKSZ(|slU!{`%e)Bfd5jpkOASl9tv+5hY8Tc&H_4_|IJ%Fxjz{)3LpXkn1B-f
z6aEO2VVLIkX7vMj|2Hx7zw-H0kbe;Etl;?n)?k1PAb&#G5B2^%5k}Pio(MglkU3!7
z+GGI5J=o`JlL6^~5>qB$yjcl&fM$TiMQ#M)W0?zLChGO$k?@qucgw(R)8Es<CuLIu
z#Yrh%ziwLt#h-oET~G9f(v>1`57Y(!ELb?wmy61{J<j*l^De;xPSU%W@n=0=>b@hF
zi+nG>dZ#Az|MB&fVR8M=A1JOxinX}AySuwX(E`P#xVsl9P+W?;yB3Gy?(XjHviI=q
z?|<*R`(iVhO!Aq@WHNc4-RwC&U+6(^-_J|3Sj>dnj;|G$cExMehXpM4*8>7_eU13*
zP!1dKOp@XI`w-96!g)*Ia0vC;WA6{^T;AGm{jc<#rx_}=!+!htq$!AmWqQ9qMvPs0
zEu-h)$%OvVdRA(kmlwuKFO6s<x;j^Yg7wb+rPwEJ)f2whCBthhI@Vc()IQdD{IW**
z`HSp+#*wckZomAdUI*~*Zu2?{Mzc2+b`$(GmN?8s5{-%34gB(GS7YCy$fX@j<|m26
zb(rzRZJJJThpChdv=n$QIem&VPURS<`$1V_H)SV^)f5tD;>>WFycP|8lHnc_6=um{
zl-&m%Fig9aG_{KR-Qb}#ru%duZ)VEK&Dck`CbK;<2Rz^pWxIvVgz)2fj_Xn}^Ae(t
z>74f$C;}_mk9K3Br*^ylcgKmau|t3id3pQcve9-)k>cz3x3B#8*F9Z&Xkb#yJlWtV
zR_Af9<j+v~3Q1U)*MEelMo)7@2Yo&T<#Fqa8Sjy>9fS0SJ)RVXA3j+xEkl;WCK%Sz
zua`Bh?ZW&V#ez${zf;ZiNO8XFJf6;;IT`cluw=75qa_3$Ygd4~aEN^22CHaskkig3
zLT=0PlpW@Xo2iK#8KJnik?)4&W6pw9!a5z5G2@%xJjAB^bfIW9D3^@PfKPW25a*YS
zqQI*6S{f_7|J65`nDAx%_EPXw(bJG6s^1DXos-p-yaafGV$<Ve>uvU2S)7IekTSLY
z_TOF)mtt8=?!sn#HD-;ic)h)DK2&(zQ&@k=jkq=*;wk0umG<WFzUn_ZRF{X<<FC+f
zu#9~8Rz5irc#v~CYA)UD(;8;W6Ft73h{b)VNGP#d7&^uopvxa9?40^2D=clgw{=}w
zt2TmzqIRPFr8%XUV`Qt8EkY;6x3#`Lts(s$;ivM-{Kl@sUMUmINC&dMy5Z#&sH4r*
z<~yErjabKh<wV11s8%h5GSTfxF*U2Yj5__YSAAaDQH_-q69v3<Yp<rifySQhG05kV
z#2*Yoh!0N;%E{Emj7Ge(hrjzZh;%C`)IluooRsG2Bj#>N&yaGqQg7V#9}l$;vdYA(
z0=Sq{m84WpAAuV&i9^EKN`X;;OzG!MfKlEjjH1oC%q*(;ud2uh!3Z*G^Rt0lYK&A0
zw*e5CKc3Jrc8`SLhkyd#hol`s_onD8W%)?>2IS~Ii*Qq6C{#M?YodfZwq<e6BO;`|
zohd5CD}JYi4enl)9Xmb}w$J{A@ySEjzc%6y7TQ)+gynNQCn;M4NloOB*N~KnZmX-c
zD28MGbr4mJeL~yg;pSZ1>-_fV>+^Brm95!GL?hvv7_QF#=*j)-u%VUf=I|x)V<;!6
z$@`Pd*T>RRho|(8Cq5k-nWz3+ZxLe5)>j(zz==kIo95rlSDTgXA9I_LdcJp`WDC_;
zh;vD;&-n%EJr7m=LLdr&$*B84uoDD^_XLK#%TG;ir?e71wGwG`pL4e{;dK%2u8EHq
zvb4c81070C%@v=w>j=xu>=!D~DeCU308fD7y2p0EyP(INuws}8jY4YU_W7{8=LZIX
z%#@k~?1}0fG~Q54yv#;clW1|X;NY1;iC<4K7FU{OU{5gvS6Xa<sB|g<mqAAZ<A%~&
zxjF=FZ@TuVx3)`?1~lGSUFW78F5Z|^*XB<QJOHp0{CUnBJoKuf9*v9Y?2FZzW^KzX
z&4yhCH1hruKoF7l^EQ-X3m}jeI?fTf;$6=ZI)&}`^&QtUR_isvLlNoinkHaE5%uhv
zh@eAb*)Z+EqO%z{?4%))lXy1lieZtHZ~y|0oCKg1BO)jL4=o8SG{dh46NyXr(61+f
zfJ@f`AXoqi>`7qY(vA5y30-i!CvfC3czCYAMrvJ#_cbJ3e=BKO@V8tOx`=&r5b<K~
z*gJ`_gkX?OEM(+DzkJxpM!68`iFI=N5*tMzJ4IbhM!q2&L4IgnONOtPm?t_EODC%u
z2zx>H41vPNCoLIDd3bP1mX4;VQe)xlHnAto^M_A5G@eo`vEagD(~o@dlU<gfG!GA*
zv}81ZQbmSOpO}|B3MkNuMW&Xmp_7Nk>x?}?<eC6P_<*QC)=7qLaBtWl*>$!{_&53C
zK@AzcN}{or_N7z72Pr@L#ZSMo3}tzEfFF^f=>bG?eEJ3eG119s5kS-d5Xl3<bZQtk
zgnEFs1z;LFQ<Da=Jlep3-}C?+IlfARu@<nx?^u9!|G!v(b&3C3M~;sVsOe91Vgn$t
z07z3=o<G*WROx}KLLeK+0#RiSh>!u%H(4GWKwAW0UM)GkUIXB^M8Iv}uvO%zFtEP0
z1x?*Fj1p)#2$e(NqHiXHyq;H;GFWn>9SHm9{@0FH6eZAp+N)w?$Kn1PR}59L-@mdG
zDN$Ex3TM0fsw>A!C{ZzQhC?7E;SIG{e8e#Dxuv9HJFlb(pMpamhxwxH*C&^4=c|6{
z3?(iYAaeayl0y}lrDP<432hD)-2JNFJO2^m6%Jwaximb7EkGpfP!%KVBL>2~CgxX3
zr5n=!4=Y4g*$+^*@>SgnUwAS)YofKIgi3~#Dn1!s92`gZ|5K7PVxokM04)Hy?|hrp
zG=mr}+m_Xd>;t5t*3e2k420*0|FV}1BUQys00i%R8$5zSKH+SZQt@4nyB;^y9j5Qh
z9rYHF;UH#hJTNevc$a9{zjIZV!iu{~>d;W#xYQ|6=SvC;H|CbBEC#<Pym;5T{N;H#
zgcI|7N~!~wI(3><J0RU5wBg%G+DhWG^ZgGdf$x7XE!Am~m(Gz{ol!2n0Ri77b@Cmc
z-_4y^o^*M~FU|fRezpHQ{=um^uLti^k@7@tR@U;QMzLC_yB`0$CHR1fw9#{ArHNDX
z(zJ>F)(Qd)pl8%t6vtTJJ=K54C=|Ts-v2YktlAS5qcv_JwkyjEL1+7eiwgvAOSs6E
z_+rV2#osiT*bb*dn%@TW_cV;YRJ7whXJQ7&)Ar1P1TRg&5a)Uz?tlK_V=Ky3oaaj)
z%aC912~tWAInfi(1Cpjt1dud;#2`#aB4uQeI1GeA@Z5mo*D;hC_EO~rvK0IC=P~N9
zhIwn^<Et^2QP))lA}4&B8^{Ul(_=3~-4G$P6F#oM(fG;2Ky}SiGp}whyjy{DXTz_n
z)LI&XDHMQ+Ge1)$;)m$n30-bw`Gt9?DND{~P+zkbI>E|vq4CyE_%ano0}P&FW<`mV
z5~^teR(Il0N(g4|PsE{<j1y;dU8Uxf5N{onPZ+iZhS0w@0{ZgV{!g*WKgH;2{}ikI
zPjUP|#rKo{r})|YKgA=LL;op$Hvgws;6KIYy5c<u;0y~9i0HnU2$!sKpF>4kwL`vb
zw+Hc8yJLe0a4@Kk&j@TTBIS$%ka#VBc9x?*bBY#v*$J+#wV-sgJzw_dEY9b`$+s$>
z48ia9V#M$0uaIh4mUrS~KfA8$foSK8{zfpPuCDtwC3({Oh^N)Ww<X)96Zm+7`r4Xb
zlNYGp?p{xCM{S2}B^xN%=v_nC!e(_{O*z+#b$Jp>4(1M*c`DMEv65WRSB9?`GTO^d
z_FB@d$Ti1n!O2$nz12r|SH0}L$@}HW&6|A2T&V8}8@Ap=>F)`TT0lzuuc16=f-_E_
z?5Jmy*;U`7?Ke@IdqPV<)cYz~-UN~wewBPW6P&UK#Y8<vv#t8(ZNHH^-xD4JqUBe~
zr87Yld(gDT3P^4ERq=Keq}Knc=nQbv|H$e;viz!856F67$F=Q2tn~MS)2<*^e1HI)
z{6FISj{q-qnRWrOV%`hd0=?^3K)UO%;{c#;|LZvW>VIVR9{~V$mtV)#S3o(K_Z<@s
zAVhC~*n<%90pj!@QF8sqxquLD?mLw1LBoKdD#Ndgx2qtP{#Ql-S7rJiS^Y<rUl{>h
zmEPA%z))KH`;IAB5G?=*%%4{NA94Oi0Kh315H0lmc#=k;Bj`&>&2zu)akDR-$n5Jq
zV`-D`OHIf#CHWHOs&8d;>vMl)$sgYey0)C_KD4?OU)z@W=f;}jWAoD|o~M@fsIiL5
z+**J=d*a~%*r)%o=TAIK06SDsISqVr>yM8QfTs5z?*p0v_T-7@=znY*FdmT7w6rVG
z0!?#3kB)ym-UsacgDm>r_&b0F1`M1$RWw$diwDGkUKcavGu!CUk~=u4mB^2uMz>cP
z8_$+eI{w@@qBKT}^eB_l9mV^u__~2Mrvp7buN_CYGd#8jZiKYV|H4MA#})5sP}3hh
zi!HsL3JR_Y@LhTM@Z3s%r<z<X%Ydk1M*UU7f&*dX+$S#7It2$mfQdtUZnYsW+W-4g
zjlJcsA{GfG66d}`;ku~>wgC*>q>WxA4*jPy<9c0+c;9ev;OZTlN<dA0h+Gv?eKk4;
z18mSXqa&w4CKDknZ6*Pl_>Pr-t`sC06ZO<D0)y~6BDO!jZGSU4zwy6<lo9msWcMnO
zo@S+5Ug!H8U2V?@RyilDsqWvNm}T6?6k<V>sCdrCByooWG?YH69~YO%Vr{EPE$!pn
zh-+C<$2(3d8o-q)2iQB$(ZW(x^I}q?27fUPB5%hTMO;!?(nb_)-&{Miq<LSyjJmaZ
zl4;k`wR8B~B?>=C%y?f~g)wuF?C#~)(4!nJ-3pG2U@Lzkd|e#MgkEQ%<IW?=?8iOl
zxzVw$4GX!o+S?1AF*@RpY`oqWZ6Ca_Ros5;+kO_>ae3pIlwZT-vZeJ1${~ORr+0eE
z<*%P<%jZug^D?V;&tT~Lele>@x22kz^Ig?Px$E1EHsMTT`4OcJRqh_XjXB9CdUJSW
zKd!F|>%yCd;KKKVUu$m6Is%~Qj=A=GlfBnNtdkFY<K&wOGW|KAA7}-=TW+p+EmOX)
z54R6uHF=Qx>uUD~i+8X{<yKEj)jZnza%B;*gwbCF86xH!c9hp*XpIp)9X`XU+Ol4n
z9q&X?eSm9zY*miJQm{JU_%$U**o%^1!q7)3qnJOyO+N}&k7Ut1X<;a0{$1MChbXMX
zl3Uvm)*tbQMS)-?o{ah`_r8(`jrgpVg@7ev$rwT{x}jP%bLxmYR2(Mh56gzwxhNE|
zgg-H3n)I}?T;J-;idCG_=SP7*1J`vQw|Y#KSjyPXP5r3E5mviStRaOvlHhTyFQeOB
znXM_1xpY?M^i=Mj7r(v9C-^!7qjt4Nf{+v*S?pjN>I>TH{YZhswn70*gH$2`kpg3R
zCO_92H14o;lesc#d92vFW!Ep*60^-enxWBOOFnP$TW3J5tO2|+=1b_}m1{3d)T`St
zk!80$L`>n|H*9=a7UJ24o%oOS7B$Hdlis@dua{y3%nmHD>S(T=Oj`6<+q-pTUmC<e
zwQ(;#xZ6>Iq#{sfBT?diYxIU=IVp=qVqwH|MwiT86RBMOWQ%1Rk`}2_AfJ3FjaP<B
zlu6H<6c<tn^giN3pDpCAV3&flbLr+jD~jSnv{jDen~b(0QEb2TcbH}y5Y0h^zWPO#
z^OH~Ocy^%HR|4Ig%fT&Xup}>pj~n}TAZ}V3-MuLm=R{Q~1K*kXMQ5XO@62NtR!;2N
zhZ6aS2NQ+|fhyER2ZtKQP3LGJ$h{s}E>BZ{g75?)XUeT;K9UGyNSX1j?B%6n8LYxW
zh!$F^!S8n-rz!a6dF|ob?cZF7qORu@EVd(z&*p5E2-x(8xiFvUsY$^<&Eo7#=3G%*
zRH6QgHxO?#%DL1g&HsU66g>pl`@N$@yB$k`OlJkD8`qFz*@lWvxk_+C1hQk&UnTD8
zx5*OE!I{4WZI;;74x_N0PZIL2Hn#LH&0=C4la>1j|J9pcUQ(F}4Ul2&&*KO>zBTJF
ziv=)(KVPwW7WO@>bmN{p9RP^$^%k^5gnd4upP!)&N0PdN?4^+gneN29o34l-nFJV5
zdC-C{-3>#PIeuym4-Q+m@h<g9I2>{=8B|z%WGz)$O2t{_U@h!eN(H%!FF(TV3zFdP
z$Q#9SRZdE>J(Y-I<mzp3Kl-gtexM1m>h<cTDT-V9e7AhKghY7%@^D~Dd^RjN1>@tq
z4Y^yOF4_UDHxtkSEl$?mQF80`qRB^!1QzLl234dg%|<|Lg261bBkYda#8;725e!jn
z7iB9&zvw<J|FC3@&9gP_wuKqv_sn~lqnC~Vi4Ps0bh<PpWxrWL?`)iSR^n_hcSb`P
z_q7!rHKAf{_L!p8OOv#q&WG}@jL$$9pOYgi7+Z4?K|j!`IXYxvqogwAp&v^SH@OdX
zNIuSsYvMrU;!r5}$5Fp%#qCgK=m~b)IBW*q*uAJQc|OXI)}Kp^Kf+=2yE?fyy+wBN
zj){ax(zbC~m{33YT?p7_erp%D=!w2(rN@||W|}b9FHMGR6To5TKS+q7JMEe$Liv!O
zC@mW3mj{J+goz$CV@WOUhw7<DK;kmeY5Ay46k`X88zgJ}5L_<c-nG+9OV6z)Fg?d%
z5KIH9Cw{{Tt1~6%I$T9wAJ2i-{O95x!#&#4nsF|I_KZ#Ah`Qr&;FEeAXyKuiZz2A;
z*baA6B+W=G;RuV2g9_KM@I_8%IT1-Yuk6R0si|!0;dlFnyu_)#LaGxrzLIKu8gO1`
zk0IMwnXagT>#HhN247JW-d++eoT@n9E$jkWTF~zn`>S6)ujvnUrvE&zXxoq<vt=>X
zFcZVQs#Ol@I8=MZ{5YKf?3lRN+duG`Z)G1<d7x<k*L$6C#jqop3rmWGTgNhpWJDnr
z!_<l&6w(>T`;ZpOU;id3;wTeNE|?Wdp^+~Q!IMs%ckw44br%aJ(4#dSkF1!I4EQ{X
z*<~os$xli6X4YTdT`vN%?hmbqUuli2L7H3c)En0bPB!x;S`*&n;8C(vao-P8fbGRc
z=YckMk>M(5X(8KP-*uHbGR|uu#k7Pw|9P>-cpA>eM@Bfpi$$(jqd`VVHzZRXY53xf
z3l$TW(4GA1&++py5;;Cq4e6T*{!DkW5_lNXUVSRcx3TjnLtR=@_-z_?G17=<ALgIG
z31U&U@i}8DwP=5$8yV++@wdG<Px{7t7dR#9`38Gb>8zg%nNKm>F+S*|^h!dhDs+U~
zx<d1OsrRI}S=u7ecjovTh(%Y9{nsm4msim%Loat-dH{@ZTJZ?s-6{<3PxrEaE)Z>q
zG}(BStkl@!rR$XtO;s?-x>J_F3uL&XNWnU_{UXbuW&aq-((Y#@$0<NgIKvA=qFJY*
zM!C{s*=*#LJLS!K+2XTsn&GQ!VOt)8X#`uQM0`tQ%Q0w?GNY?9TUQV)tkn+18Q9ht
zFzZ@WU|WA7tmTwj@~DY6C3~Q)YU_(18Xi(M0<M|!SHf}g45|TLQagPhPJn6{>%8}4
z;U`RWV-w^iG;+S`hCa^a!oojMixYEME3s}UnGPOblnpiZ{AiWC70Epw<mRn{Js;%S
zL&v%J%Ziw29Xk_>_IlDpI;=lsqVq5}Rtq;%UkV89-&E)H{iiVX6X)F}bT%&M&1J9`
z;a9t-FUsHE;i}#7gH)-L4##BKcbgnwO^Qd^tFF)g>U|>LsLoDZP4x0i%wxAw(|U?K
zY@%hqEeS>$$|3hSFIn(B8l-+#OSK%)%o6gb{}Y+<;ND0dc-Vk;>!*8I_A3r6ioC<e
z4;5nm`ensp{Z4sXU*?Ah<MU;2@_P<tN9)+~s~yQXtTa?hBMxPH!7I@PsSuM628jzP
z*{8?jGlmnW9M2V?d3ZcBrJ%b4Yrcf7;o5sBvewIKh3JN{G?u8{W~}x9`a0{0Mw;eZ
zIOCZr{Y|EBOU8PxtfUWi+CO|-huTvqk!~{7EKOiW4negKLDQ(#G=Uv0SwRhN&vG-c
z#ym`)Z~rF8=x%5T&yE~ngp%E?KP5^H?^ydWu*NB@y>;Uz-$-QmT__{r{I)_r9TVQ8
zNAIPCML!vl&xmy!l$gN1@vd>tj$}GITvU(JM+u8zGA^z1)9laxWbuP`5Bo${tK4dM
z*L@r?yI6mpodzBgmE~=;QXnhDQd%Xm6fq?`sw0J)p~D1ry{3x_{`|LIok&LP#-0U&
zn3C-pZ&`GDIgH$2*-OG0|8x0`_kamK>uV9$QbG-^$sn5dz+;2*sP})6{_bi07$!VQ
z_CFp2U`?vg+WG;RyvMujujyzL6o0`z25b_en-Ui7q-R<s&a7P0`y?>BM35Q75BYn$
zb`c5Udu472_N^q?+f3f$@i+T6t5WirD&8u>U|@}I*xR;OS5ZOze|8p`KGG0yQw(`E
zB#U=Q{N}>pF%{=KGLc2M`;2`8gN1}yIMJC!*6tob-yB|_9hh4<!^4ICb+LzgGhp3F
zU8IR)M<lACcDg|3ZU-lJ!Ei{kXwxp~hpv}zbh;aBiB|<qA*Gp%`cnr+KW$6Y7ds}W
z9$_c8JknfgjdXi$`>7SXgmM+-I84hG@4fg&Izii4`HiT;ZRcOH=!(E0yS%9jKVU1q
zNiq<Sl^o{T%`TT>M6*EEFGGE2!Eyf(H`#%BZ$^zGO5xCnPE|NZojXSztX&A1A;euj
z_PKtHYK8~*0&1w(d927;A$#u8k5WmY98sbi5uu&|hR@%@Qjf(_Po>D2djmdR^*CJl
zI9#N>6kIVYO?ymQztV|aUzKs+xHFEbIJt*v?-$kH2RAfwOk9?5Bxwv><oEiw&NX6i
zPs-4{D4HeS4=cQ6cIP`6Ys$Tzq2OMjP#5WVTf8Md&Y6Cl{}O7C>+zDryvB#Q!AF~L
zbtpP7%4zTEY!`)iRzSYTS6^}cyx}V4w?0VRksI*Rf|5xL`-1PhdS@j2a86asxg`e<
zbrdO6>sRM-$@2gYJ9jf9`#15IymnhH&25PGQTpX9?of%Ve*T)2Y@1`d2dUOAL&*&9
ztjc*n<y!H<lvEUYYEk3Y8P%iangL<utj;U!;VQag@^urFn7|w%?zS;Ek93PeXN|dI
zIqgcv4E=p=kMyKlo}{_sfWrCUMEy@DZ47z0e|8R?i}UAAv?^sS+A7>U^nfAibH_3o
zl|d<AXNF@G`G;6w$-@v*xj_tNJv8!)Ce@G`O5Cq_-^T|PPfbz+W5u9H-S`WGLB$Iy
z<I>~c@aOF_jvhTcJ2z=B$qr`nl9kI`(*>mKW-IQ~lc`+zV}B2&#?!(u=9bk2*M^N?
z`LYq7kg#9XIyV2uM1Fo%6WskDlg{!~>@%6vi|i({d$Vo&Jxb$f&rXF?lE>Atsrh$q
zLMwOL&S=co8s7K2J@b59WJ+(xylc+T-yPiA@M%5L8+eBw#x_muqBIcp?NqoV=|aCH
zdTfm=`PMJG`KYfFZkps?EVD8eKmO+O=Ap)n_h~Gt_-axEBQ70_XsH$bH!S>nC0Af9
z+hj)Ax`BsTCJ*)fgu<R5rE*1Kh@2u)y{9D?m2})ev0-sxe51mb6vzy*$KF2lf<_7L
zw)!M)D(U!x>W`FH7;~Sr+yisi9y5$cFXHnGuaw<rR#giz+w-S&3U$|G&#Da<8^@eH
zt-suqvmO%gZa*Y;Z!yu@D#cUGs^&T<rXSzU6fLOkPw_jC9a0B7TWYLjQOSEjH?7Ei
zqG|g(gd3j+zeC-u8Otz4$;(qkFpP_lFTLYr68~rBESFD2Z|HuKd|8q#tlOkLvnedV
z;A?eCcY@2;UDjaQ$M!!ow+TKacIpSE4kbhjnz>$Ixha>t*>U3Yq;J$8WU4FU!w7-I
zqL{NX<i=g;5Px-BGa@XVBbUjI*E%JIiS|CR=60HW_$ZY={lxb<AC?jqR<fZ5i@jT!
zUHRF|_5U68HIjx&zrRsJ_vfeU%0J&|vUzF`J5m^1mCoMAO`I{K@Z*;jju{sf%#9YL
z2SINq;|1gTGqi(*Z+Z=^npN)iQdhp}!Hy?nHo3Zf4M>-dQ)TqUUzNpb$*qtVwB>Jy
z?jo()n(Ii^WfOlzFkrHfB<NRMh|*-}+!wT+h1tj8p+-2XXgdr!?<O?Izb%^5Cfq+C
zL{zjoihXsug@zM5Q)T!j2wKgL(bIFw$O{|NzKoyZ7M}@AsH}96w;tZav0`9Z&9Ja(
z?2C`ImUnOwg>%-d&ud-Jxx&OmU&c_d5m9gJ*2q`IRaT{~I)%}8F4nDY|Bu(BsWf?{
z&sJ5B`6J3UMX=Fet0GQ1Lt)P-V=c>4f3<SFxfCl`&IiIOn-fzl&78x`!N6iPL_@?=
zLBvx=<jco$lc2vy)82rt77F!H!UKM|D}wFKCcp^wQer5E*8hlzm!X817g9-Fzx<(i
z)l_PiBLUaarb7QCXU+OKX`&<-bB!*iM~a%%2*GMWk~HR*6JiUG6ywbV+5|EBn5nad
zvVzo~S0?^H$a&PJmD`~p>&0Y77SeBW6Q$1hjf>^l>)<B&M)1-LlcW<FnIz{9O=8J^
zk0{$aq!=@g5ikRgcdH|5hxtj10gRL0O-yEU2gXw-$?j*k01!&fDE)O|ZZWxv5feWI
zx|t^MDjSC4&YL=-<_SYw5lI_3ejCvPEnJcDWmFtO72+h1#qgO@jy#HfsDXT*aw+@<
z5@#|RcG|-gq82az8m>o~>KOBg`df)S4kG8}UrQ2GwsiU*t(%*5F)!|xxx_%bI97!q
zhkLI^VvQ40>0HN!r3-XWP+7T`3AhaIm07-YOB(mvY@)GtI^ryz)cy~V*T6*M%m&Kk
zkE3arVi9}e2sz@l2dm}RVFM>gsR#S3s*KE(vYZ1gqiv&iO`qr+tcg5H4Sz?LCoexQ
zS%)1{ZMlORdOC1JgatO3o0&M$|JHH@KlER=^5t{q3?is1PejtS|9-)zCQARiLD9W8
zmeKjqh&s9E#c=s5c+Q7?2eBM#czFEkF7d+vj`=bKvqG8zq=?l%4-y=GJ}sB>nQ9@u
z;3)g#6jzmrgpO@aewS&f4+0x=`V;9qA>&rBKV66QlT)!<IW>L0xx5<$nU$O+8kx1a
z<*iKh>Z^9*L`9_$X-ljzeQI^3=S&W!R<?4Ct#g}(i#R6A)YM{^Hjm&J*-rtoG)qW&
z1SQ#}kn9-q2<R5(_w4a6pxK@K)`g2`5W{q;qpJ9m&`n0o!P61<ANrZOF=8}*W$sXg
z+dUZ$r$oFm`s!5f^3QV`-{cYN|6JkDnH<6tRMpCH!u<_6mU%rGs-VBg<&Q-&@sZ*!
z__7lUQEw&lGSO`4e2C8zZCx2zpoav(R<!bW;x4m<A5pI>0W<o>vn6LOrefpBQj*O6
zZ>jT)gn~F}YeD-*XA1FhJJpnIm+L~T@=Z-FOKz(ii$b5C8uG~z6;yWtiQKk@C{n`)
z$<s`)27E&->C*#xDqTIo66k6t%lVlgOHl?xuDLmXOKB(Bv+g+`fKT75zs*>RS%LYW
zfhlIG?1j6rP=HN>nSRibVlIbD);Qr48)E{AR~<CaV^*j%oTu89v-7E5PNrio@i8Y+
zy3kJDg3%${iN<WV74GlJzz$nZh*OS)Q;x!+So&lbPa(RqFvU=|BTVQRHXe_e-9cK{
z{}>UoraW|KaS9r0XbIBrvE@*wHG#bAJL2?4l*3kUsr^$?Z`;aZ(*pX&_NbJM2QO&W
zw)T-DwFz^vIMu3Kh5<IxAF2)CVNy(?49DlziKc&oi7)UF7^i;pL(@SCl4FJV`RzFT
zmxaVHqN-czI`-Tf-#_Lw7q^3KxnW>3pu&g(k$hp6QF9W%DbQg~vC`u&IaY6rV1#hv
z)I(WXHKV+#pF-N%IixA3Y+6bcMtJ||89;*^!FvA)U(O)MnC3Zx`PX$5Gq8-p?SqAj
z#~PW4l8j32gF#pX^ArK5jDX9@^CBoWTe^sCh16|H)NLtP^rlaS^A=*d#(-%3TV;*h
zHS4Zw{y2$U;TgG$8o86=xW9C}{xRxR=$~td#ZT}^on=>dUP;hz>NG9>quceWk`9y1
zTKXhk)vtQHyQ`3cMwKM!B$I{f*&Z)v@J2<QKT*pOl+j3hlVd*@m*l<}Fhc8*^4yaa
zwArr34?X2q0bf6LYNEbyh16^zn&2p-7c(=rOgkgX|HB&s9oa%Pz!BB{cfd5-ED=GG
z>Z6G|%A9Fw`Vf|ujjYG?7MXf<f=q=9r&dv`%-Yvpk>b<C^{SiVN?%$eyONrQ`Jhg-
zjPK}$<(!*rjEIK~6Rj$F%OclXF$@7ecKDxj$#>bTKn4%e`1t-0_rBr*HMLY$zV&x6
z8@TtQ%f8+(cAx{Fhr@OGN1Y`^ahs#aPxIx<3i_%k1eFuKjZZ`sWX~%4xkJ4_!}lH$
zDK^oA!|5Vv*b#?HwW<|reg7=Yr>ZzZ&&~#2^EX_|<}CgVw<W;uff92VEq;0_VG}XW
zmg_>ZXqJmdC|^@wR)hRSQvesfz5R2<0HY`-JMA**(yJZ=(e!TA=t4tHTL#Cjf7qbm
z`8KFjGew)am_SoVdH5+uUSx;^KP5>?M@VfAEX7Fjs9-00_;^X>*Q~jmx<9G3l}r8S
z_?hvxk@+M|R#}Ozp;Y9nqq(pxDn_+f*;New@#2J8^AExM#<Rllb>nNhR>Rag6nXfL
zos5-QOS}msm|sUq)wRYcDpefpQljUBw?|n#F26F$Q_Uu%iaCv#8L$jtuAxgE{hb*k
z^oXA-ydcR{Qa>ePjvU$#-^JK&A3xIkDlH=>ug{Nx%}%?vpC1?(e&s4+iKXeA@3hl8
zGJeO!3wgB^{4Kje@5-UxCD<G4<LSb7JxfW#+Q_lG9+<2cbwPLdPleu3kJ3TiL>jX!
zN~#rPft6;?DctZ0kh2OOEP1MR&y*ENPZf3sH;#+v!+QU4vy?cjjh24V3{}ytKR{H{
zYP{K%*$uBJ3a%SYa`-h>2AHX?9xVJZ(rwqx7^BoJQ|lafiYj%UY4-Qf`0!m<_u-h5
zs#fYxpW|ktu04di{%F^e@FXHg44Myka#wz}ao4PHQI?IEb>h8Wxin?<)MsclvAY5F
zMiyFqJ+t;m^Ztm}pG)y(np{p;8zCBdp4bkJSA5@0E4W4CV)1Gpdx_Hfb)|4!Iy#bU
zjgG7@%um%2++xT>cffM|FZ4-l!#3S6pQabDG(2O_`WU%s*lJRD<r#Y1w%9IhFek01
z++WEI+OjHR;xnX_x|OB4CPw4Rq^XaRe5m(}GE22lZeS*r8ZPBc-yDK5|7ffzvsx@3
z{cOrLwN3KWSkbz2AE|KcO%HVE9gW4a-yfJtAe+IvjG;0`<6Z6b%uG3%zU%cA%m|B)
zaI7aq#u`y;o)!@M33~SReegjYi`O|1?ZCsw_ZGZ;S^Q-C)HChYe%VfV@`erCqwmk$
z-xTbIr+BfruY4$EtR1C$(R`Xd`#K2xGGl$OaJ9af*+E#=|M4nVrVq3NIyT3CTL--z
z-xl_xoQ<9`y4rqU&8%2oZF@bf46EB%UV7dHA?@F7Ke|17y`VnS?q1&qK8&~QiRi59
zfrhys54XqX<NNX}*>zlRyxH`J3lngUdlxQW{T}5j7<YKOxZPb{92{S#4|flLUuW79
zjvOMEE7%bVtgWrRc=>vhE)wo7WU>mk(-y2HE&hGBXiXmNke2L?aWqomED8||H(t{@
zcjtS&W764q-n_PCzwa9cUiE0gE7@}LOocxQQMg|z*)g6t4SKWcR)%k(cp3gQz8)m~
z>I<4}=5bMR1kJmy<MX$>NpfdQdtf50<GFvGFOB5ne|kAJ_llQ8k(?~-a>M3$s=JB~
z_;k*gt<q&(lOFxLO6tkZ*)M4;Bho)?akDl8lD%7*T)6M1II|@bX!GXN<`+k~$n(C}
z%W<$L>p5AxPTGEaS(cx<AO2f26jO#bv{YS&JEHxy!pYP{XxOwourQQKRQqQSvJc@~
zFmow|lDm>gvW3aRN6zEvXVCRqPvv=7Ic;cmjXh@PRG6S;GUoB8TuB0Gv)`daA0E>s
zT6`(+t7SmP2hT;6J{uDsM71szi``iTg+mF?5)C!*ahgD)SDl%)78h56*RMp6(L2$G
zcR18o;o%@!bpab*H4E6EbaH*?rhdvjG%r?H=I{b>f{>#A*%HYxAH0!1FG=~GAuCU3
z4}HvuafD!uWJhv)#JPy&&oGquvuNiKILH}C`IKoJ#rb>I7|Y}2MxJe@20R7V)UmbE
ze0y)%;cBZgvGjD01MdRq+m3NP7r}T>Xn+6jSr0UqbWXu2NzjA9(>my5M>q59-rdvY
z=H1(*Zi|0iB9YC>_Y$dPKg;hlX)wO3h9z)ic3?<FbkRe-(1eaF_!A$@efTHJz+6qc
zou{j{{n&(Xh>(6Y;N<-l8ly5#EJX+N>YIYe!k)0kW*hcT(|Vv&d4Z~;Lm9rst=@AJ
z{DmX+8vaWg>Wl~WU`4>-Om{tsK8AqhCyMb+2xCk-sbPrK<>GIJw!^*g1H7T>6L(w>
z`-Q7Z>uXiE@R85t`a>$Cu+Ys{r>zm=uxo!0?ELoDDib@(_BK2A)<mnW`o}}fZ@&Go
z62>U4GiBiO70@9N9M$waQ|SAiR6AhUf9>6jukek1e2!W<wX=uO)V8)cqfn83+*rD&
zfBq6Q`10~?XAfkrhuZ&p*T>WM_3SK?+fQqfT=2Q{H1#kFdp-l*NS5l5yO<i~__Bsi
zkFl?7_%gb7zXeq}lRxv@(&E9()z;1s_LaQc40Ct4;;<Icui*T4Pu%9iXyx9+2mYwt
ze|I{TVFS~h-u54sDH=9cAFN({J-ZV<k!bl-A}>GrmqjAcfd|6gJAVF7$Pe0F-nzDA
z0INu%SVp^lVoSdg;N!QKtid*s&k#bx<%}+Mm3GnduiBIoL~K7*y&k>PBWA9On8o=j
zabbv^dlU^^cI3G;TiffYxtP?6tbWFd6w6#_l{VKD;<tHw+I$P~n99RjU@D9j*bXo@
zZcDmMS{ynbY{mAeA2W;7vMW!zR?hvHz2087H{Gx0FX)?`mo^dpnOv0cd8=2y=`ieh
zlp|Ybm7%cK{%e#?-Y{ibHARQixBV&8#eyptB|*C1<B4mTZ*HsHVyH`XpMBHm8zQ3h
z;n0TnJ#G2Ce|~Y==8|23^Lu(M4zNFrhHW^TFT#q?bEk2f>ni(APkP+l%9z^ra?11M
zw92sVF}%Ma-pSE#V60n<*zyY3Q1o+Q*?xnba{WXhiA2-~e>@<Rs7`|Hr<_ZDI&**)
zT|ISP&lO*U2Gm*N=BICPZYZ_;CPf;GvH9uFgbiKSC9ZQetp+U(AW@oR@hHm1pv&a8
z9_G8z#z8(K)6Z7+@k&9yH;G-*m)*LGcvp(H0@0e^T0i4^pGTL^|9<`1L}%`*%G^w?
z5?75mw}2A7VUm)W-Ty>B{cG%S;|0^@aIX;o-pZ}l(C~EE-tEii(o2f4Yp?|27EcFD
zE0aV)tVU)Bv_4BB&8pMTBsHV5bp8RYUliA;K@|<sr^YFR$PmmSGPHV(@W3A<!3Zj|
zy1c10MIm&U1r<`GS+g`f__b+b<dIv?(0y@XB*>RMKRy;q!P9?j1T&>d&OT*Bcqa|s
zFMikvrbRZi)CM5|*nb)^MwHO4p;*;ou`L&JFp9FXLIQ9s!!ff$w7-2U$~ILr&I)1S
zNbx3u9#MLtMjTOM5^a|7$F|HV1q#UuDAOY7f&cJ1KEs*<mw<t38-%20W}`EU4#!hM
z!sX!Qk8FlH#2^3qt(7gmk1>kV){d84Os!V#`rjpk3ear2$L}yf9m+<hpM|_623Jg>
zNXai?G6th3Ffv(6xmi#FXy!U|h%!V}{tezDfoO0t8*3^`5b{+Y<AszUgyGq|x1h);
zkZFbB>-tEPAVxC=fZ8C19mL^2ogG9M{0<JZLRMG>j6xRvAR3oH77-+u{|3~O0Unos
zh|V`bi~w|VpAdykc<U`;=MiLUweb%b2Dz#D%rL<>NAbK=Wt*R@z64#8f#DFF2W5Q>
zkbuK6Os9UYELb`q;bfOYzSqrL|08fX*@x(q=0PrBz;UwKvHT^>@5EqmvgJ7}rr{#@
z7X8J|sp}ExMB-}6tKg9Ev8v!~>XGS0s^B6Wq^jVS5xJ`1x=5fRCctW!j6UwUD^X0r
zVZVOZ`^e&fW2ag#Wai?GUXx{+z81Ms_U&Ndc-BF6Ht;rTVBh!*O66`#;pmf!DTQKP
z_w85;QiOO8Lxl?rcx}3ba3>V_bc5{&d5FD>mn$bH7Y`R?hyr^B1PBVaWFi9>MFl8u
zbSSy$c^@I5Cs0!@0|TGNi4f{!^CW=;pQiXN)LA#rgUWOo&W_3??*tU50|`JI820;s
zX_#%G=L*hqHY$|dHLH^f#9q`{UT;$?nX&E}CQGDIv*rkug2|lTY8;i89`ZnHJazl$
z4FoeKkkBjSEy|1_wW^Zm$C(ZdRwE^lnhn%@)Am221d_|-5`L}iK~MsfRm05))>5)4
zfvjubHMyq8wKm@TpZnPnRs_-YkX8hFW6AA6bV4w8pw8FYE-pLJhsHi1DyaMMmk;St
z&zggQEV*|^^&S$J5T&yxcL@6)ZE{WB&00NNA3n5ob9Z8ny)WYfG@Hl-T)rH5Br03C
zMx50IoVpDZP!|CVdM6Wb@_<34bv+0ZaOKr-Y$AX`6L2;)@R(4i?<?72ghVF-m_sMR
z>i{e<y%5a%iq>@j3ybuhIS~^tAKK`#vfVYg<`2x6q9-P3(~fy+w~qqlOH%BD9V4Sc
zbT?OKA~<w6@%}nf<yPvfY<ze#;f)ONg@4Pp$^6{Zh5aJCJV)Ev0R?ifrG7}FSb%#Y
ze@NQ+nkrx);A;_zx$za)xerOe&fWOBWQ;z<H8rk9WDwvt$c_Ld2iOKB2e=BA39t>7
zNw^cR4VCGiZQ#>@tK$7qrqV~6y0{CYEue<e^(8*ixXL)|Gq6<tAigDzpz$Wo$G5}?
zS~*XL?y@|rFr#(d##jikU><0nKpNKleaW-HSD`=1U<YzD;5fMpASE}#=29`W&!ZZ|
z_Rf*=m->cU7a&Dyx_r|g+OCXUP>M>`c1g12bUOI`YAnyKu%42`S;~$iKlLVI)2Z#T
zA+7bHbk}m3F!w3MxmG^NL7BFVnX0deKx;<TMRln4m0jBz&F?~4T+fp<q$tkFef6^|
zRmB{!G(}s^o73M!i$EoaKR><aoTZbp>w3`I<uV%{q&qgN`)$2c7OMI)TfesSj-N1c
zSf39k{fJp!Gjq0BAWLK{p01K?{SjUI^4Z2N&o+3y<dVjxFF^{F{*q>G(r(5M^7-}b
zc%`e0LGgA^A%|V#Yfmp2l`)9@;@)~W#V05d@gk^tczk&UyU&M#_bLh8W{)r6-!nfq
zI`Uo<XxWTt!Qoi2=u@bDjKgqAt)5O}Md2M?un_o>X;ipKX5On%yFrQXl1l%B|AY<q
z*k-|^VX&y(5NL^PgnRGE(a!}4a8wp76zG>Z%^K_%%sH^JswS;(FAQ@RU(%F(b5m*u
zi|SX)e7#W=bN}#~V%XwOP895QHY{lw%j+RG<1_MU*TD{&oUd*c&$>Ny=rhJngI3Ng
z=@N;2BV(P)p)!mvJNo0oXs|BWz8S}&3y9EKrVv0Q(wY-y$8S%?P3=T)4j$$szmmpt
zIf&M|_J7^m@b<em6di+GgLNb1zGi{*OubEgiRriGWEkfpl)OLiM}-i9gCiyi@&hVA
zFgg5DjT}&cB21hp==1lFaKx{aL0^pVKNE-aVSFY|1mmG1=GcIsBGy15q$1uk3x0}6
zHD%T*z3EKhzz&+s=f#4{mC(G2jz!bE5*UJ<rr!*l+;>d=K)0QL>BhK6{bw`TywxoS
z6Jv#Ox%Bq4Vs)Anbnu6bKD$?537(;4=A(0ObB7y-A|9Tg<n+7xvgC;x1d5Tf+wF&s
zk581j)7g&p%ro0vf929_xb!wlkWdXB5|h)Y1K}V^<i_|gguvH#iF^>+BcvyQBH3o6
zWdYT5qviAQd(BvFy$adu(>6WCdM}Fv96}Z_uLA~(DEI@025s0s!=>3R$sdTbT9Pv{
z&?fY*o+GrqKCLyhlC1_$=8Lu?=1Q6cCB<Tu{7gC^LAL3Wb+?YEX4Li0qh|am!pxkH
z|0jZOI(X9Ribcn^)qQ~=Ma4bl=4V*jouzA^@p<VgHoAB2(Jyiibl--ku?$Mv09NoZ
zu`#r`S`#~p&Xj?admJuw{fjLaTt*W)<03=^Xex~INK7h>ETu1oXjB*+3s4BbgTg>T
zj^!_6*d(5%<R@YnWncMQM7Ygr0YA9=gc&@zTjN+L+l?IqAubdJ1K~PO1OY+ZeO@_2
zdh?>e+oTu+Fa3|Pn%&G{>kmm2LTBBPz`~@D<TP&K&Ruq>s@88Ujd|15F>?@`Iaz;b
z&U1()B7N)+buB(Jx$t_#&9cC?3`IV{L481FvX+_?>I4HPH6wugOl07+*+68F98^bS
z@M94MA_S=#79ym24XDXW+#($dbuz7ypfUlZziD2+QwRz1odE-fg!<4!3<dQ8u+kd>
z#ul*B&%SuHW20mS9~4lkpczb0lW-XOL51I7HCFh+W6|ZKq@_50BeAU^^e{1|<A?yw
zsDqtCNTD`eXr=!%8=<ZKmX0z7E+Gc25}x&dsjxj*FR__^$hWwI+f^TsCGO4d+bT}n
zPcD8ZU^S2f$V9w;CkDatM7+s(Vnn=Oj6Mz^hv-1nh=K-@Db8{IPbM<RS7Y!;2+)7w
zTh}8ShiZztFu6YnxiAS*lM(S^a1!#i*X5QehO&jmGNjw%HKjVq*lk3s_Me0deGmWk
zBYZ^(wPfk*Ts4CW#mp6h%5@3VCtmFS=l#4#ERQ6QD#(xR9~z(+usC+U8R+=g#IT}R
zBUaIOHh?X6vo-X#GqcJ=E_R1Z0L2$uprClqv_v|eZDY_DbArpjbrJ38JL{R)^E&IR
zpvJoDtGZx;!s7vG19@hoT2)_QY3oK1pQFLx*NEr+qBf3@`oubb#VbETtaH*oNCq^j
zH5gRn%|f56#H2~7mw#wF%3I2BPZpO8^Dgc98()P<Y$WrN#>Tw+(#_r6$~R8~bA>U=
z{XKciy}iZ0Qy!eNH{=C#1;b9&VXrM@Sb^f0o{CEEnVO1<Lb#L~17ms;6AuH|2n7%0
zTN@G{#_yj;xO4u2My=vh50k!V;e+THQdFl}Q~2<`#!Ki@RCn62Xb4hNFbfc9;g8bU
z0`S4B1}9BRlENux3zX2}PH=={%>tW&^Nd5*C>0_#*3khHaY>6F+oL^m10l4Gv1uf~
zR67#Ms_bbVz`4QuCq-c^w5u2R6hD2N2ZcWicOq1gXM@p#mHDN)8$kPE+Mx<U({_@X
zL(>Y4a8yB9|KP8J_<8$YV=1xy0;}P7iRF(8rs2ok*Y;fl>{g%W3%Hjm05Z!{1<{GX
z)QMFEF`|fYs|7ytX4Ibtrjc~U1ztv=r=Ck?HEBYQFt*^N6C9vk6rqj6Qy0{BSDzPj
zbj)^lPUvc%ATf7uweEQpFc`5Pm<i?+KwpgX0KY-GGXg0H{t^`UK>YwuAx!%KZ`9zQ
zX&`z66lIM-5vT0k!*hZDvk~qE>H>X)8TkcDR1`te>`TD@2Iay=;0EOvey<HmAa|);
zp)Zt6d@DkLu9q{Q$51=U=<HM;_`m>Zdx0!#Wu7V4xwJ4qNhPp`R8J(-26+KrCN17c
z36@D@M(_Z&fsXfAv5S%kUb~ADwHC<>0$4&X2w(}lApR|(qCu<p2D+c3L6rRl`ez)K
zB3A?Wj6g*LNCu$o_QGG$z(+-@j}q=fi7V=7m2)DdoHbzswYI>{IuBU?*;{0YQ4d(*
zLV(Wjf(dr@&A_}*$6?POa7DN93&smnTo&dF6!UVYVioaSry>(@nN6|kzjO8hzE20r
z2jT&K?=!4VKsIr(2W;X7_X9k~1JMIKa2x>w%Ha4HDD-3e_*oYJdIOC%$aWD^J8Tc-
z^DKWcBGq%EgVwb!OK$g+^3}pew`&L)a4P5qW6~@PKb2psDDe<V2*_K7Ss2Ms<yja&
zCX?|8GMS7&kjZ5H|79|2Ad@K}2vPr+$*8j$@_1#yWeA*X@Ts6FwjrpX-w#D-z>25%
zfGw<CtOUPCNd`%Bs^V$<;H*3u%^C0t5<L}|hd^T#b)w1+qe1^xxZV=TB;ygkqTfPD
zVC<bCWe_u9N|1m*aKJ1(0e{SZ0sfc)V_p_Q0{kI_1o#7}{pXJ&aKImyLZD)B3fq|g
zocDaC3<=~bB}gD&y`y}nf}Q~bva6A$P+fmfKT=Z;IqY8q>~7>A&ddP>Rr7y8`v`F;
ztm?-oY0&7f6t++hQ>r*#Y)xojchR^G!K>r<+TC5X2{x=1l=SCeeiL(%ypeh-N;y<^
zFk~(Xb@VvW)jdoI_~AVX+%`Px17CzRM!~%j`^7JG_kNlU5d1sM@;!jl><qSv5ID`6
z2seCy)2xXQIL*#Nfz#|P6gbVEfzxcm=O**n@Cpk0Owu#assEKJ#Rd?z&G|orpM`=q
z_&pl}Vb%FMV9V*^)dp268yb%y5j`f2wX1)aY|ur8VUzlP=zd=OvMWBN3VpXUj|R=5
zfGKYPdb7Xz$tEszp7SHJaiz@56=bH11s>~14-YK`K?J`u;)z5Ct`@}9sn~_^9`p!6
z(3gP$L0<+21brFUzo5qig8n^i06}j64FtUbG_dUqpcniQff~P;0W`4fj%p#?mVavR
zfUULH;&J<xs<`5TSMcbmhZLz5$gYXp`Z>#f-8i~^)Y%}nm(nC5p^Q!IRbmslbcx9M
z+>6VQ=18v~`sd?kQ<#kC9M}!k9Xe)iOo&WyuaGqNO8;@c9N4{P`U4~iVxRz0!`gdl
zSbI+mYyVQi1TK&oZeS*Gfz)sV1Ehu<7}*QF8yH+W@Ee%YP?Q@OAQB)vL=F3^xBtMB
zJM-kRW2jFWeiU2oUZR8ezD~so*F+=D3K!0^r~&EEEL8phf;1;i25z0B)}js?GiY_Y
zk0*c&Y|9Tx8s-Ni5i*dk?7{x}Gpu0!1&{j$6hMgLy@x2?dx+xw3(+5tK!|RE{eT3v
z?3Q0PG4z%nxf?Qo(F6d^_5f{<(!}ugSxtvUz4#laFEWm>GC258I~{u(H`dy|9{jdC
zx8HB9J#^hvJVc*V%mh7n^;#^_%Dm!t`@h%Gvwm{Pt;S7fJ!e0W$ffH5_X$5W1GdZZ
zc)+^*f=>g{UDc~~S)<|e;(w>-f)B?UiM8Oj=S942KwvHf2+;WY?`n~n{7%gP7cGy!
zZ{6kbeEz;Dl!~O=!?PU^t)z;Q%WL+-8VuiFE@z$4j<R?g@ds=~4B87;7L4KZVZ6Nc
zV(eG5tFM!?huQ(4(3a1Y^BJJ|gJ^1R;*6KoZd<wt;-_H`yjCWXtp-xlp2)_OhuZPA
zJ#()*_`<A5;0m1AO@$QG4|6!*up-#@`~Eq^>ApkdWJBmpo!`l4N+iN3pW*YRw_gig
z&t89jJtKTe75(aBq*xeM`+}j&DLNyE%6<*$>p?YwOnyuFeSLjpt;O{o<mB7d;{GC;
zi+K{@Pi-pp)Y0;mJl{@1x=60=OZYbW_<Ug7(~<dVb8{cpk^c5NBeq;2$nRrk``x$M
z)A9Jt3HVO+)YieYz2z;*@oKt1vywV;n=C>7QCcijTcCX93u9jts=`$V{Eav_DE=Ur
zbUzPPPbnr}gS=Rs+fs8)Z>Ls%ujBl)b(}ekeb3rMTjLG;xz)q^@TJ$=DaFxQyR~Z>
z@ZJ7kMC0dBd^{6^n#>TG-yw|pvh8l)ZZ^Cx&aRJB8P}473zXb{YAVyB^*+LwliW!d
zHzi{=1oi~6&RKEI?4aU|;*Z!&uZLthLky>1`Vsca^?-hS-Awj!^nAUr^8}e!tb)nO
zg0b#qm4KT*u^<^2bYlpyT6ZC~j0!ILo4)vU=t;&e?-Xi+WgKeD?~q+$!v>;A)`^U9
z7+;x(>Q(mft&^j}{N}m_xpC^>AE*+uQN1Btr4~N%%i*t|zLlbegX}#U(fbdBTkbhs
zJ62Y`{`efPt-oDQpZ4T-nHl{0_$Bt^Nt=rOx}6}d<nV*qpfFu{OJR*Br?;+`q{;vO
z%~Nl|NzNS9l3SBx-|EX?cA?*RzudcD6{k2QM{!^H7q1U)(y3qgPoNX*A@US{9`7DB
z%~ZN(;u%+B9<PA#pKaHevkx(6M63V0M7jHiJMAar^NLPSr~knFv+SMzsyIEWy5?}C
zUTqo?8|A7<NOy}(47>z2a0a#*MTPJh0<(CWR@Pghpip3o^SegnO_k<%0+;-KjDPy1
zTz{P<e=3r4)z|vtXzB5X^%l6?ziMOt!>A$-o=Yhwj*cjyHf?o1W}B#AIO<zknDp-1
zL_5@HK|X$UTpSaK|A)OV0f_1Q9=~szG9{Umij-GK2xFI2w}cQv$UgR6ktKv%LL#zf
zE!jfIzB47szLUM|OZI)s|C~27DIY#2%jfU=GpF8N&pr3fIrrTC-FN)t`8jp7=B8~O
z-u|IOkX7g53a`f>C%oRO=TvjhPM4cQZA)*R?zO~jV~e<hEoNOhcsBIl<4sS??JHSW
zWS7-vqp`hoU+Sc@_ttt%4h$~5JY;FJYMzh$pq76u)N<1BPk|%He7bkz#@P4wGF~nB
z3F~TXl!z<+&%B~8zOh<4ZPmD%20dmr8rbdl)Q@*Qwr=*S{fpMY$68cuo8;E2MeW$0
z-93kneGqHipuS0o`_uSl4_d@7Z#lJO!TKG{?HZWWBPE!zLL$#Jv#27wU)1cmG$N_-
zpr<KK{FVpyJn8A<FPdI7V(GlX3r<;7T{^SH_)OYjd(`3M6PLd!onY$wZbU-W2wEqy
zYS$wnjq)#=Xn1{7)ErBXnq|gpFVe4E+GhEA+ZM89xJ`J?y_;=SugJ|AF`$2NQd_r8
zSMobm*h@~8pKhZwWAQnc)dd=k3!hX$ubqLxfQn-`wZ6x{sxqzMhPUaQ#rDc?V`|#e
z*iO$~5kCs7)iGb~dKErRD_d{C+k3u?AK7o;cx&oL`SX*{i|;A#vhH?7^5sS*fs?wI
zaOuBm>WzbsuRe0`e<^PN##={gT6`)xJYm_KrpIPKPU&=Q*W`UG<1S3{T*oin$hYj&
z&%$tX#<|z6_k1)f*=w6otI<~{f4b9u;MGs-Hni!{wy^D)hh40K-di+r-_pgWAB*yP
zTB&UB^{3t5lp1mI94C3X_jSr?zb*HRm-|%RYxtZQJuD}Ot~gsgVbpS?#tEZVfiY&S
zQAA`^e8l9t3-z7nuc@;!GkWck_3KCOX)-?Xy1r8-#q}aiRTWufoLsgXzFec?u&ftX
zUhZ8mBibb^sB!NF_Xl=Jnewc2hlzV4ABgYVymH~-(U(nE%vs@gY|NffvK19K)k+-o
zCJ^3beE#ueM7J?fUB?^~zg_F?I?Jlw{%LiJKDHX?ar~J7@!3!7-PWH{=6Y1@`sJP5
z9iQIcc}>@FC;Q47F<s&&?bWaBn;blEdCf}^iyW;d-l$5Ou0GM?LCvE^>%APkP3~{3
zf804D@wI!!_AWY}1q&|KGqxYLwok&i=-mUo0){{DU%6+M-Y%_AR7#tDuck$SuhZsN
z?dR!4EIYon+pJoFbIY3;HEp`*TJ5XH!cLs?Y}Cm=wCk&?`E^_d?%8?Ewa4*_#XopQ
zr<T#p=XWi3+U?z$4h_9_8C`Y$kY=*3z3G<GeVgq|zd6RL&i)F!k_=<&A1*Pv_woJb
znq5qOYI4-ab-YOeE5AaoVE#Qj9o{}FJ9<&Cppb>znr&J3?B)J7#tS7k7B#zB-MU@F
zmk;L{nD{xT*i^1Hx@_ZJZyQ&wyn2QB-pX2wd7t){evZq|jWaH@xWP=>>br{PsXkFj
zA&NehXVysKw`3*nn@7%xCvTSa6{UDx@-<PQH^DBZXTEddeio(T_2rEfN2&#TG=Dgq
zemL1;t6hx$z?sRh^i<H5RqVsC?MF7yQ=_l!U`bOpy#eR0)Ez9SMx29T$#+%P8K(9v
zvA1gE{pK61d#@XJ`8w_XzFA14^Z6%My;#)f(ZPvzIv%hwD_U-RTcfrss(Bwy6zA{f
z%D=nc$8mvWKeyveCdAGj%k`|&?C|2gAD0=8FY0)7@$9iSc4@Ay51$<*8?>Qb`FsH<
z%{CYFvJma;+3(CCT7E*sxLd5PQQR$WS@F%qj%1vL1pSl6nXKIgohfaNUM0oO9o)5f
zb7>z(;#{C!(=&re<n_zrjm^NQbRsOkvgX!ln|m!CUUO?=o8vY5hWQWZ>UZ$O<z`9S
z3j__DJA8o7=3?H5xy{9HPU%~6&G`lA;`)DVe<MM!Yy){+_fziip7Oe)a)o@SDZ)cD
zI!-J+@#-2+i`oqZ|J-tgCYJP>PD|<gOs^SON`K-0i8~q=ItiC(ZZ>qcdA`X-+``>9
zV{zd{ajW=dQnS9NI@}9;9es7X@M7<yEAOX9TNlr)ef?R+>8^1>eNy-NJ-)VWYYo?H
zl~bzD$XIbTaO2Yt3J;yG^9KxYb;;Uy%w+4q)XS>Q?0uzociz``8r9z~{QZNMSC+gF
zeEsNLlR8(g>>l=b-$~D?>BEX&ophmc<&(4fc@J3k_*&NOtF<p*s$DhOdO(Nj-5y<y
zF7_&Y(Gxf8!tEAVU#Ofpt^5+}3xh6}Xm@Nxx5LAy_S=4UTKPH78*Z(tzoq8xd2ilV
zeeN`B-n)e^M?W@+wi~me>Bdh7njVe**u#w9zCG(r>bxbrJWu)eToT){e8|QN-45M-
z5ua6OLrm><*Ovyge*b9c{ImTR_>caS@o~-e>Rp>&n(o|x&FP~fqwZ(PpLff03cr=s
z#J0}*Vx-G?7T40@04wUKZ?|rXo6V5qHsSLmlbkM@)`;Ko(C(G>vW=$Iqs%Q|NsnFX
z7w%B6&+%Kf%iD%GuOIb(@}l=;UG>DiYu*o^@FcGH*#orYgFUbF^?xwYqyHm$`qVk|
z-`1?P#^j?S!^mt=+zq4K))Ce2O>qkRc>C$2IqhCQoX}~;kY-NiLre6z;`+#S*QY1<
z7W>7!9lO4B<om352e!^W6`L@)gY&4U4TB@bMNP3A<B-f3dDx<IpZD%wKD+s><_F9=
z7H`%0$y1|URf|^K{J^yMa`%Bpx9)UmH+@URH!qJ>Y?QojK>XrM;a5xcz1t=-%5V9(
zwmaUA?@~RbU%xy391>>ki5_i~Fmvq)$yH~^fu04E4v4x&_*-=Jb2FZhQKia=!4_9j
zkD3%4U*m*XvGH5)dwNArNq%|HqkXgyShd?nPuZ6t+ckGfy2@Ce@}l?s1DylAM%+7{
zId$KY-mrVq)UlRxSJUgV+D7|s$abwv*&W{42?$!0OH9<uXUQZ+L%ZJ(+xMio@wqX!
z(FJa2$ZA^zMZNd>U?G)1v3e%kr8m~k^Juzd+XLxUrt|fZ(%Y?_UC-f8@a~?Om0i+C
z>RlAQTGVo6;HZoH9-lTF9X<5P`%S^uR(u?p@cPIm-Av~y{kf6HeY?J^`f}{<p7E7N
z&HI>mRcGY7aVNQvk2m`%=4~_<y|S*JnRzW?<K*32TkPk$h$;m~jW3cf*@0hv+PO=}
z<IB@@LLM8^OcOrjalaC1^dI4MbXZoq3gs%D?GaQ+u2*%aUXX759ph>bhKtWt*`Jcn
z_qbj`Bj4k<i-^u`Twh1$+(zduFDAY_Q~Gv`=&+`vt~&?6?6<tU+<AWQ{JzIiik@Dv
zvUq$?fn^2HRq;Juelnz8H_Gzdf(U89w9fmEWfgErSQH#Zy?8sRN&Fpac`4uHa%UZB
z;)u0gR*55KhszQcHI@~O?}>%U3=#^{qR+YKWqgmDS{5%Ee`lq6lQN5nNA*g7(9Om2
zU_;&K7ic?0(3bE|CrW3vh`!r&R2SEm6F;0O{m3Nhc#n&s+Z*R@VQ>2(x85ZNRX-Qy
zax_csGWPA|q`U0xhl^Xg9KB$exZJAx!^~@&be<Op(@z!y*Ajysajin$8s4r#jE~$o
zbjJ8d&y^CL=NH7!6+!3Tm)y3!aca}s7bDu7nBL}u*{guhYLYcXsV2U42lrkPK4ziw
z+0?xiB$KP%pE71t4mH_b%BjWy+Y!&Q)#OOuV|vR~YSO&X`j4%hBce8ZoUm-}l<CCb
zC|~Abi{^dapE}ZS?#*FoXCCa|Vd!!_cuu_=%g$ZBY7~F*+Qrpx#}Dh-=+rCSz1I()
z*nLs2eP+t49c%73-mq$s?!>n}`m9+y-_O2B*CQ!IkEMtj-G6`YKxT+-&ojDpkL~Dq
zqMqBd-QDdf_T76d#J1jmMKLj9!CSy+dBEWP;P`D#SA@SG9Jj4$Pq3C+=+=d*s4^y3
zTi&#Vt3kL$U$5vMV@ypOSk`khK6LV4ktI^yy8gAT58P;6?NQ5q7Z=A!q$UDqw**Jo
z+Yge*C$B8Lpe@H=KhqHOCBzo><^IM3w*fKjc$DtW>W$`q?00ZT_?<JEcLEZk%T#w&
zjIJKUz&I{Vh>ox-nh^bP{j#Q}aW0i&-g&V5CZF^(dxCbnzu?slkU+?dKgwM#g<>T{
zCypM_d9Y&i=!ciq-|jb_9iGtG>3xldiqU$4dQh)~=#gxe+;!|nLn?m1z48$8`!;2h
zfJ|a-Oq=46wz-XSXID6n@}geRp;rfOe0JqyxdW#M%BEDcntbPYxf(t_3pW{%RekhP
z=LVw}m49CK9(?dJI%&eL6BFkgFZ|(d<1<dx9_}wVT>tTowHaw1{f0;Fy=7c5(7oTM
z#Wn9=EBI{hqv&IWmP~Ed@x{JlHBKFv<oc;pb@{x889N$xJ6-j>*PDt1N}RMRwcuLp
zn}e~-%Z~3;th&L{hl3w3@4EfjW}Ub_>m9=1tg#*8FnN)|@#O_=QhFK{s+HJ!*!qR}
zHom<4{{Gto&9-@UOvwlc7*^YA-PpT^N7vWeH1k$Z<D~u)u1jZ@u*AWlNUU44K_<b9
z6X6p#bgI`mL$~69gr`$(9F8^LNF7UVyS_2be)HI{1etBkCXI@kuACzYO*%HUs;G-<
zs`oN*W4q0krp&p^sW?4x{U9@=1w*A$Gri=|k-9pa9~-!5crRdLyD*aomKJnr+l;r5
z4`h5Q9{S07e!Wk#U>2IVC&Q_>$u!52cKKZfES|ceYuURQ7iPTNW92lCH9GJtu6?a{
zel?=XyQh{4co^cft!DcLv*y)2;MQT(hO31f-!v(7x#)o1?<Kx|1@9kO9caD}*6lo8
zI!Gnw$M;<!s(id=+=MY#_1xZcZg3|<H~5KvU|?DP`Q))9-kf>AYt+!Ki${1^ca%yB
zPM9Dd_nW<8!LB3c9-R)_HGJ`*7U8xTx1K!fuzdRSh_Ua6cfK_*<+P)F#)BtA&UW`t
z8aMOQTDy}Q3|dzRvUXYLRxl=D<m_8@Z#?Th*MHcyowju+`?rouEoOJo;`+pK`}Sp&
zTX{I&i?=IMTb&wpBGx0YR&D3PkpU4p6&>phd3ru0=z4`+`wx9G`*_x-&4`-@;}7q<
z^}11{Zb9RKpb4qZtK9B<`}&9qon}fpO;|UlNTkTcI{M9u!GoeN9~@QFalwMeH?tNm
zTrj3=#nwaXUwdFVpIY#SRgWk2xawhQzVo!ljGIjyYSdc#$Zk!yb%n$ee4WCi9$_!I
z<!$H08q8Q`zU{%=4}n`I2d2K?Zx@~#S13YGWtky1FO3(EZ8X_@+Ono@X}fj~pX;n!
zKAElwOy;i3qpNoxeX5Ov*NUvv0uNoL_&nWRdQRAcgC_Z}O?doxwtI_D(kJg1<TD;)
z7aHx*F)h0PXd9pE!M@bNb4)Rx;U)vyXNKEvDq?ZAKVMl|<j@dT`#SsH7cJ>=-{)@6
zG1W)CihWmYK(X>Wqi30Sd|;Wn-*8>2(23(ZClw#~w2$Lj|C^abYn`dwZ!llG!ig;w
ze(s0!O{)8B<#ZRzhgR`h2RxeCoLe})R`d7|mtVE-TBrSrqVJ=7+Vo29@owWR*Zfgz
zZkvFuukSof*=cmTx8KGxbw6||wyW5unj`n*ce?9%{eo%vT5m@b%9=W{N8{Zqo(^3E
z7o&t&EBa+wR4RNV_PVaS{en7X>z%LLx=iFNPm=qb2`kk6QQ2uH;@_S*T;JE%0$#bb
zGj+GU({Ns!Lk?RTb(kMNv$#)co3f#2mR49$BQlX6d+%y7y194PrLz-fa_}zv`11=Y
zv!0W0cw1ewZ0eY{drV5>=xL!3n_CVE>oCAjULfJo)nW|rXCCNr;hmz)mQCYNmohy)
zp_l9U<F0j<K3`So;#AAY#hdHgYhO-eztGP}Rv-#eC^q%(njGA_lW2KY|K64>0&3Qq
z-sp~zUA^>9yB($<HTlqbW|fCU2S!XBwtpuHBtfrllk~=xB^K6RP_SA)&%>*W+NGZA
zo_KAA?x%(YlAjG{u8M0?IrnD1YrR?*M%75~G;!dWxnn*!+RS}-=i1`bkBy#nn?B}t
zcP|n}cGSpc!g_c0nECO}`r8TjTrXAbpH;EC?wjNmbhFW^Xc8ro>00zKT24-<gx$4F
zk8DA!9lGbmmGZi>@X!$0*S~P^$&=z66dlXW4QN>VUAgq4{#SN8vc7;F{Gf7Zc;Zl_
z(Qyw<l5J<X)f}r>G54_RvT0?aYugU<S&~LOH0jVs->pmM$ZmVenOffS-8wtTbYXba
zt_O|IjPHE6N%hf>e22a>e|UM>8NJ8dUOg(^tx{?iC@<-M(V|(mN~L()in<ANF10#2
zxz=FVuf07<9%+6i@|>u1kIqq6@oD25w(@!GU;efy+)I)=Eoraxj;GVa1;xs|(|0U1
zXz8P)T;Tlb^<FqO539cBrsw+h4a1rkEUY`^@T;?Xx1Y^?89eWF^HH5gDypSlBmw07
z@(5%7_5tZ}`z;H5x{Z9^zsmea)vg^m&}o<3hpk<2`(2DY+Pn0y#SSanNOiJvWB^Hn
z1iJD7g=c1$8+V=cH#I3`k~Ab``Q$AV2eocpsGo7A4clLL?b270&@a@Hbq8*VW)~r`
zdt+MmZ4@_U=fbgFqD{j`xtP9ZUFiBUw@Ek%+ui=vvc<lcMLTz~?^wQc#f>iql&kD<
z<3n*zvOUdx{J~|*$zgU2ewG9LEYpPcp*A+%j_p0e)%07@w}#b@S;d!Bd2U`Pu)^kP
z83EfXk*Z_|6!QcYlg?qDlErhk)?#;IZzA;mv7zUmrPz1)P(t7PdD}w|b)L-=x7S&_
zvqnCDVEnXx;z8-2{Yoc1>2iLO^~t*JGFR1qVScgu)ZNL?cGUl1!irL;0HhE6q@auv
z?(?g+aw)VuRBF{J_%0l7so(y=%=YHjxWieEEtfk!>_(6Fm3kM50|h`8^We@FlNAy@
zc=Kp$kI5Ap4j9*d>#N<RD@N@K939;AKo<4fenV0r;juwelEh_PnXe<M(SLHUiGdDx
zBLkj=UvIbg&eO!pe)*3yD*x=wND{!d54=r|0OQ)0jjk1yfBn0*;^*zJq{&`(dVB41
zL>2pwPXlk<Js)^$)6CT`5A`jSUf>C8?p7#9^XId4>UY`PX;MW45?FHHt6sx>^bQs1
zG0DH7gq#0XN7vW9oxI7+jg7gb+$ktVWcB`&!=}urA}cv!cI}b(o}}-(s0Rl<*7jU2
znY(dJGezYRP6sSH7v*@JNMIuC2TV+;`;3%KF}<*NV4!{0t^y%v2j$y;VXu8m)U<_e
zl`ctQEW9s+7IndT5nhB83b~#cv9Hd+qzV_t*RsohWapTZ@eX&o-I+7<c?1dP_Cp!$
zp$xswO%EU?w}tH*dE<%q2h+LHYpm{MHQ-X>Ul>N@KT4)>2LQ1qAlj!#jpJ=<AKQJZ
zI)D6w>*f7{yNw2(cx~4)ZFQD@JHImpiXY7Iznm{?sMVP|m6{HyyXNFJZtd$(*Im~t
zxU4w8<b1~3#bjJqb;sB$#S0tW+Fg2UvrUx^bS~1NX?<pO3(kBJwN}ziykSVNLv^c0
zvuiIcc(Yk>^E!o7mz1?FASx2vuO&aVZAO>Ke9wB1UNg6Bc+>5Zjz~I(CbYB(YPi>D
zrTN}wZsWX@c=JK?y`%0NuHV0G+5BfVcqNzZ^76#`qQ&={8=R^+U7S><_{XF9Td%*<
z*P~ah=;HO~47p?5@LkzQ3yKX0yWXmQBdgk0z9+-YLR$A~<hcE+?u7+|{VaCAQ=N3*
z_~~TS?7&kONP4xga}9#~HE!i-I_2)J)y2C!D?9FdlUtV~Ucaw7bcp+cO9qdRy>A{M
z84^0eeDSfASRciVPK!Gl8bm}Me>8IHjOMR5y3ThQdD5}yusKPCx}KeNtk;8ftLEOA
zYiI0gmQrxc-Th5{wpH$(aC7P0*A<c;yEK_yws_@P#e-X(GPW|SSAS%u(1vf9^xzZb
zT=f{z|B5UmpML98s@2nz<FB4_E;FsnzI;IyU!1uWFsj>=b_YY2#yTcX827Z<wpfqJ
z{tHHgddJONP}g2}Qrgf%&6>YD-fNyy5pkz0`-fT|IT!G_Z|0`%d)D^~^Qk&*zhp&u
zOqe*ZQ$}*b$<<RvgnJLZE2Yo3o0_LCDe&AR#Aj8#nzo5ap1n%XXuiO@i|eVkl?!&f
zEWh#4Wz6Ae>5CTB9MQ&S@x*zG)Qj$NUki(S^zfQ?D|PGNEMs-E>H4vDjz0B>(U_}8
zX74?{%)3pw+Iya^bqoy~XVW|*HF@q#L%$kBR%|J>(rW3}*<R}l@b(Ud;X0*!t_O@C
z(EQefi1A|zemEOs?N`3vF1}-Q_-M(8r-Q0YZ9Ow-`Sojq22T69vvP%1OMALCKWiAf
zFX^s)Lc5yV8!mLW_wgNLJZaiC-J=!<-}b7yeZOtK8*iVN{c!xrLfM#$DSq2aubgB4
z%pp;pQEkTjX7euAIpbTj+VDAM#}b<FHJd9BoKj+w`L=-aUX>(fEkbTpYg}pjeHNbB
z%yrq!n<dIRM1;>?Azj(r-!y}j(Mb$0Q>XKxC|HYLapyu?cc&`#TUH4(Zq#+@E&Zi8
zD|R?m;$-LJt$IxHl3iDvs@ZG!TItSqMT(flUawYnT(crRYdz|hTiK$4OKj4qxL%Gu
zr>|NX3?w`I`0rX?rbMUs9kU#lTqf6(PHpQo{8Z#>ugPt6PImSgylZ)z5=#!*)pJ<c
zGh&cVSpG&gVsEvnGd^toyFxt*cuXjB@~J`3h?s|MN+{wxk7{46$2sW^S8k(T?7oD%
zfsHq&2&W59mmPGt)w#I9#(Z^$h=|!er|eoM@klB3z$dKWlIu6B9ksIb+ur8w!7C%0
z-k3P7m`ela;r^HCVBexv<&Rs}?P>h>Lz?^@Wfms<y58^XO<VQ7b!qG+$l=u8Uc=u-
zuDv#XT|seJGw#{E<psBF>7PH^`j(#5e0ECR!zT3?zo_6+OKMfU?t#AZs+mpdHk==I
z(AjZO{MLhh_dYcl(82%gk`<lJJGAAJXDu6e_Em+ECufM=S0|pAm9rV)HF44Ts^!+#
zn7yUS)9mt;-(bG13lt`*Fu$(<ySQx+;&*Rfy2mX!V%fj|HnHy8J=Km>4l~;rd#l>f
z%9s1b#I9%>w_?t`+0rtz>ovTzIet=w5*7~g>4VtN%Y}>gp6OpY_(Jo_^%@Sk;23&|
zxbI6k5xJ+9hpk<>$;|XN@h9f=vW>OKU)9_xAT;TDr?Gdo-grLv^<493MQiz0l#JWD
z?^4UX1z+r1SYYj&>l-pnM$|5N?)i3MwB31+b>o&JZTDoIuX@S%QH#afTP9B$_q4h7
z$5t*0&mWa|v0pJTVT-72u_KBCo1NOrs%;9R?tDw#Q^$tXlEmISQ+)g4w-aN!57@uz
z)PrSv50twU_pU;js^d?rmkl-;d-c$c!WC;fWi^@FVQYln%iVI1vExqqhdmzR_NjDM
zc#+%F*LFBk-1T_t=mP=M+xJa9y!lN5o5~K8CqH9br+0Z+yB<%Uxhyj-b8>UF2J7Ei
z^?WmR&DM;YE$f`!wJLVpydvGg;txIQHPLT}u|dHpUE_|H*{5^Mr%)%`xt2~3$4tCw
zS?7qaMU{m?6H`4R>dc)Q5%@N($4k@5Ze5pL?B{Ua&~|^4XPJV-&Tsd<-E2Z?a=i(M
zlk24>XHJ=ARC)ch;d9gOM$S!>%#FHI>2w1-JCkZl=fY`LljnE@(Wup)olnfleQNh?
zezy~6s!eNjVAVx;%<EPqztW}4)r#nKW|LWE2j|jPvtnwtX<oS6kfS#K(wbcyDknNy
zJey&+es7QA^UQZ`OH66>vG&LgcjEOgc}#iT{H$4Q%Bi?AI|A~zX?wqF(#kfsTSX0!
z)?BW4tnb1BNuSzI_~d)M)w^+FtC!DhZW&gn(UP0wbfeo2`6_x$?ybv>?LDqr+Xf8+
zd|E47A9dK(Lt1Wj$|26qJf)LtuYB}+=N=uOeyBWuORaU8`%9o^?K@I>W0~8=M@not
zaH#LX`iENHJAJGF)@^}}JC)ko=h?|~`ptUvHno<gG%vHL;+@e^x25vsdTD(Z-fq}Z
z^g1iPUCM?&h5Gg~HtyD2Y$XrBzGF&}?&Sk!)E&93eEtaD$H8#czFAwn>^6)oRzd1A
zIbhX@O*Bh(tc;OanpGLAVky%mnp;g7+<)cV(_0!IT@ZU_@|yMjG0m&kW?gGF-1oX|
zqhg6qf&%v(+gfwrv}GHEx*t}ZQS=#BVRgwn_8-UDNeh_Ot1~?A(#j6opU<i=RQ7ye
z;)SPaD_afg+t>2xl2r!R4F}fSamV)hkpBC--kaxiZGK?J-CkGX&lekMd(`%rv}enK
z%l!{@ys+<L2WJ<j<oi#Hw3_;G%AB!lt)u5|84)ye+u0jc;;k=1S>vq_Cr>(df8cB`
zC4aZxkIWx$4ltj2{N|jq_vgn&SjKN^Q?$~DN^{auTX!64reEy({;kh1)*U~p@#?2@
zhL2vDu)EZRfc2&F72YqMY^K-sg4^Ua%=<~Ak!_7~mHT+?s=jKhechQ`3N35AXjoXm
ztpR8E7kCSn!@xAF7FI#q7S3-y_I3LqE9)%Nd+ccDlsRQ?lRi%lc|;r=bRf$v<mu_j
zdldsK>{T=~ZEI=edn%!J1+k9p%W<!g+=7g|I$v`+K70Lw3zdC(IzGJ`za?Wy=aTEk
zgjrA2do<zchv9`&0_=O53~lCc@4efH!<~jMsnKSfk!!(`eS$K}k8Sg$|CXHrg9Czw
zIlVT^=max{`HidZx#qVedj7S>M~s{*jH)?eV698>cW(GSe!XK{+kA_5S~Tt0<8Z3Y
zpuP2vuUP-CPR)IfvZ~ylGpec2>w_(aL}xac{HCMD(!+OTmRH}IJof*%p@8lA3X_Ko
zaqV#6owal33+EA@FW20Umz-bv{=s0M3!M+1y4GXMhbw6=BTQBX4&K_ney66JJ`QSj
zq2fW09)tH@u3vV`sfv}Kb{|x5){=7PW^Y<IzS^5&$>-fHMF-FO6?fe;%JN;K^rKTp
zzkBoi<;g4cukW!~Shd!%pbz^4tBy85f6R46jgISf-#b|+_F1sVVSm?+J=ch*xhB7K
zT)A)M#c@d<J$EeB9T3%Y?xiXdr%XtW@*Y?tV(m7cRW|<5pFY}ma?EJMDlcUn78Soz
zz~#f^R*P5EYP<+K*~Iyer${YNyXmI|y?zq-!tUggyCYU)1dp&AvglU7%|&)(v`#+}
zwP$$oRf7i)8}{O4r*X&qTAdkHc~`%Aab`D;x-A^nW%-CX_q{H*JX>Z^{9ZU)F{z>c
zuv2M|c3fIHV({M9v#O`A+M95yqW;F7FK)JromFIa(J{8^1500OoDlwM=c`E;%MV<g
z?|Z|)`lY^?o7}7>dYzR2{lkM1=DT<8&pc@HX3zHR#jTt#U+%QmX~f1(m7U%NnC&Vy
zs_ikCtQ%XWG!Nc%?b)T+loxFZ1-mY9XtkxzDMvr2S2|ta-8lX7<BgMJuDS-*C{|#q
zb?q_L7Zo4X{;k{2-ra_Dj66DY{u7;KdElYjJ0|#?Y_g#DW?a*{=REj!x7o#KU)!z!
z@?!TUpNe!obI5harzdMyKc2Da(yKXTikxaTHLIWV>pdfVM|SQp+;Uf7R^^WUGZQ9V
zk63jf`D0h7MLXudbl6(FtJl_#3+@KKINtPpjrs+PKYnH+U$OAOpr8Wx)^xL3Ijcd_
z!ADE(CW=U-iHY#B_`8*wuWmWDcV^7~+rxKQSe~x-^l{fucRN=$O4_>T{qSPJr%oQ-
z`Cx!fxrKL6-FQBJ@VNo=-j_MGYDt#<>8VE#4SU_k^0ec`F7+MvmmL{8wA6+fn@8D5
z26Vr)eSK-Kt4{s=&Trq*uH(z)8+#AzdTf#Jl6_HEsw|8zzo9|LAg2lM>%SQ@Iq}K_
zzxj%G#jac_Hp<Y|;#}vlCOt-7@j5f<VeK%NS9^-il=R%$_3^WdR&n*WoZdYDlx^$V
zFAlDlKefK&npHE*hS%%xyls_{CHF_U41Zn0Xr9-)eb*cL^y+5(aL?Qur5+0}d0x5l
zsmcZO+HXYiGo=sCbbi`;e#G1kGrZ3G4K*0L;YH-xYBiQmsGQb+!esB=^N(a6wb+(0
z=UtQOM|K^&H_Z2ZgLkE!#`X33RMP5sREx=*x*iKHvoha<X%5_MdCcuju`d_sP1)M)
z%Jf*jzN1chJg&5=%C`24&b>=nIb~_<JEcXJ?Uw8)ap_|JHI14CZ+vMrxTBTpy$cP;
z?&u!9rq|1HkJq#w{iM;OgG-)IdSW@_<H$GZLml6DeQ>35iSE%o7Jb@x@X6pnr+4>m
zuQ++{LW38s$8K#77&vs4<GZK#-@Dy=x;MymTZaL=_TSk)toY%qjEbLJtrE{A8k0@=
zEQu0aoYM%Wa{r&PM3gWBh8A*iK*R`7BsoLA?G{Tp4`NJ-l!ytZv;bK}LBu4yD2&*u
zErF~m4s*yx%NZg1c4j$Za^&}wY&jXRkQ2Qe_*$ogb7xXstQjLD5>W`_c`A{LLWvDp
zkWNJbEU8p1=G>^tLb9s39L~?!%0Nvr&XM0&vekrw7DvkgEeHMp4rm+SKR^iDB4{~~
z2M+w78{g;QxBnkS#qpk2tpB-inP#(?A1#*zrmb4gazM)gEeEt5&~iY_0WAmq*Et~l
zU;hEx@@qMu<-jlD0M$-ee+eJ+N`&P#L0<7`UK42XwH(lLK+6Fw2Ywv~v?J|b$4f1x
zznlZ6zyJ5^{{AeqIcPbc<$#t0S`Pe!1N0vu+JOH99MJH5^Z$Wgs=-gt@Ko@(DdBMk
zH4!N>AU0n|rSh+bYeWA?4p0dt#7%jWMMl9*+`hUn%izTSS0f;W7JfMgo)pY0$=r=y
zVPnF|qK0~s4-iA0zHvlMLNeX*no}<P+}Y-e(t2`p02uui#EKlF7^74=bbSX95f^k=
zC38ahxiUmoJSib1qCJEZ!Uzn(wwXr<2c(M)<+xlSKa(vIRki#S-Pz?q&tDJxKiU6%
zo?s;aISEoxED%XZJ!>IR`Wlei+x!xVMKhj2g&}+{W*dPX=VpISsS6bT)ySDGMNCy4
z<k77z4@J-44)li@kaHPF?`BCtPSgMcV2DmAm!%I{ED`ZSKu*JeIse>xZO&|S64ttZ
zJqI|#aS|e<pgHzR&F6Xk8`;Rd5v~pX<2b+(R3fpeJrsdQ6vmT;uMBS#g#Dbh{&Bzk
z&n*zc?k$hNa^mYLcnV_0t_=aS)(uEXa*I_AK|eihWkLp8<3Hj6g?u>B))*KfxuFMu
z7fiLm&;f>a+KP<$Q-RM>Fex?U2#eFF7#3tn#55RW8lD3KopOS6<4hjiKMed2r~Dfe
zV)KbjCdD7G>LStkZNPRL5wWL?d;kK=bRoguPJUNHWPiJ;1x-lS7c&STh{>ZPxVVTE
zdj&e39rAP8G9-$$04N&j@-X!L^}q;29^_)SModvlMG;e!1nUj<#6&UcImWj!5^)wj
zg`^ZivY9Ow^8}}@df6cu{o~nEOpdewcr?`Iq3HSRfvIZzk24~U=ZUwjlEvQo#`+HV
zz%3FqIR{Z)Lb;!vw&ozGb^d-1z%W-manb1wtAn68eD*+?Vg68e^f-H^TK)d=Xmj{!
z4p71*&@)R>j4^~N`&)2>ix7qe0>p}mf=FzXUak4Zb3l(!hP|A7c1i1?3p6%2NPc?S
znwy^1_ir3fjXM4f<vVda1q62`9jVY5t3)anhEeL&aA}%$+Nx&8@3upJHUs{|1S*Eb
zU;(xm7@VfFm?@D0U2&=G3+i|-Mh*hc{ORG@&zANtN{_mQJtM{6tW-L5eFqQ`RWp>g
zX2fe$7@{lM<|kx!QI7bBk!FnLGlmY8NO+8@1e#myRj>j>h!FB~*)kv_&;pC1TU{Q8
z9xV`tJjlgtjhLdAisEWMLhAYGMnWoi`ZOZyTAUEydW=#elg(@?<nXh*tw>OvEkzGf
z2jJ1j6@dX-_$dyAhl<IGe1u27Qed=PWJ>5{VbLiE-D2WGKfT+UgPhj++c_XbfvNy@
z<%k&8m*f)E|IYyH6JjahDV~MV!v72hymGXMJodTRS?2<=_X!e~J%-8^rS<%=98fB!
z0?TKN2JX{+28b0A3R~^+&tY2EAI$-(1H}_oAh4J`NE8}n9_-J+!1)jL{T!`z{dpYl
ztp=(Xi_5@79HzrjYK3LYp{p1}glTJe<#-kSTKL@@K(?bQQOqcZIMDlTKt!CjvT=H1
zGC4s&OpVPar9G^Ji7ZSiW)NhEO*0P<PFtmMtssx=ke|#Ji6Sikibi&M(4z&ykO#S#
ztr1hyQc*~4Vdc<ANF$HZ5tB)^C1U#yAzxv3yf0woV*ih4OEE*F1;C@BE)PYI7Jixo
z_s0|B0bAq<KJJ9X*)rIK6TG<%iL4GpYvDiPz%LldfTBow95=zq7I=iF@f&2nCT=02
z*7&s?_y+&;kO{6psDKK+Es#_mcu@x{?a<s_t?&18fJgFq>Y5^<Q=^y)YyykDA|{rg
zKw;#?VEquzN(d1Uz?7lT|Dg`s61g%2Jv>JJM7EHcAqfDiniL)CY|;If!#`O3eSY-g
zK6BCl&;^l#ol8h+7Bl2FW)g#kVFYysj}XG6L!AiS{|-5`Ra3_lY6=uR7@-B&EdwT`
zBO_oVhSWsIcfnAJs6c+20av|=@=hM4U=I=(B8<S}4-eC&Vu%+LIVXc1I}E{o_$RYf
zQwK`f1<%eF1GSK64yd(Losd^M!2U8$8TIo$_%})C$Xo0D#T*c4_j9mI^CfLuBmTOy
zzr@VDpXEKt-;e^>%|U;ZYtZrC-z@_Sb?3&AfP`3JB8rBX7=GD<Lbynx2ZJj}_>Zn!
zNTgAZ_(ir#T99Kl1^6*oy?#m40Hpp`0s2Pl9)AX)n-pcA^k%SJNDRT`WBx&NBH{R-
z&FmjUzZt;38S^(p&|mN)^+Er{4Frj?NTA1ueT}FNXc8sLHH)vsYs3C54m9*2WQU&6
zCim)R50?zsg8qJ~mMp}LknvxJ{#ifd|5j=K(bsA8^RWA(h?&x!5ZNl!QbNkWti$&v
z5z&~Y_zsS8oW#H;C2cqoQ!Qu6PiCv8j>NIHWS0jcw2*7)lRXCcK3}q>vbv&}T3qFL
zND|scS7I}{EKj<)Hz2w>nQbuLJBCDdfuLOMSB-FfBwICg$d<vAdmx4ZTKGW@DD^^K
z4w9QwSQoaJ_>>})*WnCA!l{=WWToC9!F0o56owXlKL=2Geim>n<fbHoIxGWmGyY4W
z78s?4|Aqtf7i1FxG_W;A2tz{*ON(C|P!ljvyR{=><k0VjpHx={vJzVmi5z7HTAOMh
zyxU5M<3Ebdb8-#^u7&>z4(LNEJyj)TV2fwMZ4zHJxvBvU{mDwC%0+8^mjmkN^Sg-O
zK;SPiLf#k&${N!UkbJ;-SE;+%NpPQ?a@uKYHbZ{D1NDl>Y*ZSB&hG=N9YwS)aD9vH
zBVm}jQ3Navd&<d)L8T*w!{1nE7(BxCLpyCnPW)GZilt^hzSO1}s4IhHY(+xb)J35Z
zwjT~E9qA?IVsMd3T}#|CDr6pvkh{a{H`&!8XSRaW5$(I6&NiDmq+pmTR|L}5!e<Wr
z06%2q;2jKICeWaT#Uus=#|3|;DYzKypDPRnVSEvz_5PV0V4x^+R80Ul2To*QGYQ<*
zuLM+FZ$d0|u|=S&z}yzg?bZ7J1P%x%M0sUNP;|rwOse#QiLE07(}AWyh*$b^nA+iS
z4rcr*PMqI(s|v$`M=eLVHyYb?vGQQBs1V_#-w^Ac@=LVk$iV?rPQt4Kz>RXuG4xWY
zqHsL1(19H3w9Y@711H3AFCHN{Gv)CxAa1qhYE>DWM#SA#oVKF+YT>`&0JfPtW`v`j
zT=KxcuK|TXL`0j|nNePPLU58v)^5b2kCZ6Hb~%oJEAnw9ndkVJTJW(A)NBTi&{Xs2
z__1uUejqIbH3f<uZN)(@{K#&rJ)}}s25|`oN{h&m5D5vcFS5Dpz?0auu-B?)wg<#;
z4W*1ER0TO?R|mCR7^XyO--VpnW>be$3{$GhBSc_;7JiBY(y_3QdM#2(Lmw_}w<Ct4
z=DMoW;1CQ9=TWh#ThX7&NSjz=4lu<pXtUsb8y>`lU<hp>&tv0=x|$O#;F1?D{Lvi9
z-DKjc8ZoN!GQoy};Qx>ze8)<}V+;J_kUQHSr=v~zeGU{Q`a-`3+R5M#1ZU{xP2@sC
z;j$)`C?zBYP{x0spcdo*7YA}Qu#~`;Q6%bHELn_Hm%!kNFcAeLIr$8QK;mCqzx6p%
zGgppmHA|qy$_oehT*#)dgRWeBkVX!$Ck#%Pk{}()7k#$ajdBU*Uj*i&^IZ@BT?{S4
zXAWSG#iJLMLF3L35h*<6`e+Y{EK-UB<69Oa_VWf9>r+>224kns+kHe_O-lUJV8sIa
zTm}#M$!yisk(9dN6g?QBg&&!=BG=SXVZpE{=sC&+!=?{1C!0J<5_Vm}Nz}|{6r)6N
zV`<GyxLhr}I;iEsFdC_81nO+n)G-l5BUc0lXd$m0z_*RF!CfB&R7voPrMkxOQBNK`
z!P)WXBl&Utki4Q4JwFP$vi(sa+H~LK04kaq#DwBNDCeY<f&xjH8bPq(i&oJ5QVBMf
znm6>hNNAhaFWB*0y;XsFFo=v7a#7D;7_amTfzS!_&`64OsNiL)K&|!Xae&WRB&qU+
zWyT4C*vk=5Z$c&#1tB0%MuK^QJ3MkQ5kwS>Uk}Rce?8s5jw0_4KUoTz2tpJf2Fy^9
zt4!%tHn=>FeshB$`rJW3?aPr1pR=3zX~KUA0UmxQ8-oTc-BbA90=W+lKuiUYaa|p_
z8?O+dWD)4+PLy9LoHgA=7@6x<QmIh#0s?v-4PJA6VRcJ$^#6;P$ao%q7_waBX=^Ho
zRiP*(BC&-*H<u+L0aBu@0Uy;&DpCw8EuwnPBFX%na0?ePl@PIul;@AYXc$$Bt*`gR
zghb<P|1mwnY}Ey)=+WvaazV)lf!XNMsBz>~i2R4rM7OXGB^G@#En(C0@gi}MKCxR4
zBj17W<<BEQgm@vRLu#w;matb4lGqTYy2$<?%og)fixQj+{kbY9252F#957WSph3XQ
zdLS?67AgcKa6F0W01b0XGL{=`!V|eQgfl&T9V({0fI=d}cv2MQnP*UEo9Beu1bO5D
z*A03}6c`-Vhjj>8X95*O#Su1jXglTD7usMVqrxdCSp64n3qfVm!XL^3<?;dpiDCh%
zh?F4UK_A7jFvmE?GYJWn$#XRC!JxnTR4Z3t)Sm^|EegQC9HHRKFoi#2437X@3@C4N
zkTGa107V1jDwugRva`)&IxTu0IUtK%ijp!UlAJ?XSVxpGcsZE^jdTEta(qbx#>+~O
z;~bY)`+kqjYimGm#s=p0e$~gaLt)7frl8G1ctV?+-p8I$4?;}08So_C3h+2kQCgn2
zCvo6N$4f#oZHO*!0KPl}%X5mqIRSE*M+Tr|EIw#Z&q4Qu`K^MC6;rrmODdZ}A&8JA
zFmDO#Lqv47h?Bmug1cy$RIHd*P!uEHML78rSf`MtaAamp7-!|mHm9x&l)h%Dv!xh`
z#l!#vEO@T@tPuK_8)^nI<U=tR4Y`3*krU3HOfr=cdkO-B4pRZUIbNMb@ba9lJ;@JW
z!Z|X4!ue9jq2X1Kf`a&1_<n+;;e+*N{_~AyjWYgPWnh>xSA<5S{vIUC5m-Xd9K<>v
zIBn&5LWM+fF!_d{I8sJQm~9A=w}!*Q31m6E{R*-bR`h0oZkeJGwD4bY0NDS1;FTyW
zSg^sTY7fOAFBBewN7XJu2!pj@A~7Y@9zx~VXfkkU;XmYnM!lR+9tI{#4}n)X#LR$5
zB~-bABjsjs@X-ZBrb{KT+Anm6K;8}Hj4xqn;g9A3OGm}T>L4OI5@GrRDv9dLKy}4p
zJ&IBeQED)_0Vq}12f_P;hWH25X_I}215A((11uN<BZ#2|)<cII4+euvNm1TB#UYJK
zk|=lZYvI4-Ko2$dHOUlrTm1_V3sFoV2KW-<<rzgD5~*nz$3*^&lcPTI0>y3OBoc-1
ztY5Yv#5<qR)C&d#{dy3_X1|{7{}M$d>!HM`O%?$vo%-G{K#|~XE58AhQ#MNkYf6Nh
zWK9Z5-iU}I)>dlaB9*ep5SYiZQ2vB?8_4$vtW8K^$1c<u_IPq-tD%4yygUFcI6Tna
zXAjeag6E1rgufls3}VO#!#qt}WAq7cJ{HvU4GM`c3ey=wxaUxQoFlqAo*W4S;%@NW
z1tKz)$Yi$x$HIefiV;Q-0v=WWtCTTP_%3{{GB8Y)E8@Fk{yKy_O<N^8oWuj<Lw8DW
zUyf{oi(FU%Ibl7)LqTYAMGQz=1T6qcu?jqd@`S8{M+<)}2bi$7Boq%M$AbeN3KkRb
zA`&W`35M1Y8%PVnzyzI2hcU4rWbkU?zv4hxo-z{F87Si-QDD3T8eB1v@E}$m4}?>s
z<p#U0B`J|gdDLHfA(V+LW0V&DU=D~vKi}%YF(@eZm@)7`r;2ycf_zblVMiUrt^8;p
z)s9qwDSs^ZgQS#z(^dtD4J=!DP_n|+-`EbzaY;$}o)rc|97X##0x$ZF#Q(=gKS90f
z!SYaQoVE%Fer<^$U)~5P*zs^kxSW`hYtT4j-%HEG$ubBeJ>VfPJiw6QbVv)olLH_L
zf$3x<d>=0F)7GJ|#2`yn7I2a^B^E>7h++?jv)(*VOwd!<ZG}6U<ROHwq6_ELJ`nLZ
zu(1kJ9+P2(z%i9ZfQS?^Q5}UQ0c<q|3T`0+?Y|w=3}VQL$^X1u|Lgq0${^=Kq($_I
zSn{SM1>QzdI3#?e7f+VHG$!`C(L^35s!KDf!=1D+ZN=TzP|mlGK1uutQqPqwQqu?!
zkw;9mD8b3lpDO|bw2*@XiafQB_BtGAq(eBmQy?MUl;4)bc)~J%2U{je)!~>N!&|oo
zy@H)}VZ)BPF+#FJFkB0NDhG6VLOkG6f*uHuhrJpGfhD13m2^=>fGSBC#V;@eh(#it
zxoY9R<bd*G4~=q+A*z><BRS#P2<RcD*h|_#I1->BWdI3-Mi{28!XX!ELitdb)nbGe
zekTVQ5(j-EG3dZP>w7?PHiL)~P)v&0BJ?rBqlvc(;~g&yePReho4CQ_iPKhhaKOq0
zU;|*bJUTcuz5_Y3#X183xghXpAcgD!6$bp>fWt|KEP&-9C4<oOuaKadlar{6N)Q8Y
zd7`IcF+<)<q_7c-T8x<p6INiohzH3EAz)-n7To_1xwBPC7LsIBP)qjT$^0F${_ryy
zj7&)}k_PLwnt%)!b^-FiV-I3epqv0qfx~j#MbFP*OBFm!1Zs=-<|U9Y<vAD1c`J9^
zb7ZTcCXo0yBWJcX0a1Zs1i))T($RtC!3Zt<5C^D`N@+@opt%f#KoMc;tJHmLA3+XE
z4-T*8@DLpaA+YI6@-*PalmJvPwMHH}022BMKsn~3AXE2rXe&Xa+{RIRe}#?NYT+v!
zP<KrXhpL}N@D)sTkOCZPnUPTNsKqIQBZt`$wip5JB*T#nV)5{(21gLA&K8>JAITQQ
zsm@kSfkGH&riGv50Diw721QDN$)TByftD8rP7H<X0kruri3P+m;tf({F%U|jFNXK$
z;Q6hf74DC-m!e1+57I*sGSCzd9%Z(lPXY6wi%b`{UJ*;F$(RPvwea6@Al)qwdBK+-
zy+Qe4oSUB)lEKSz#G?TbvBn@eT_7b4j23`AnW;T_QJRBeiY;J#+$#^6Xi<NJ1NtBU
zrSgDA5#fzCO~~+wG}6$Jc-Do9MpPpqjp3kRCch2W&90tGNR&G$E?)H@s%=cAj3`1r
z<dZ5CX*xvgZY`p@vgL*38W;j1RF2ObIJmLkxgx;-*F*LQ2k#G+z0r^#f>fNX;g&5s
zs0<BDBWuaI_OS1^T%Ti=%sDQ_8JKP00jI(BIVyqMUMQl-bvUBad68In$5{x$P7tYS
z1YfNTY6=WV2nErI)?b3ea57&z4?kAygF|On$l!)3Q_=BY+ki4f8WZkBW5z-_IO4)E
z(i#l_hN@Q6M9?-NKx_OK4j`LVz=KUyZp|!IjTiw{Nk*b4Aym+pY^9-ib_vG5*eD<f
za>cr!h2O}5oXwvg3T)9d1_fYBc#xHfjL@J<W$>j>qJY=t1X0TH?01gJ6QX&Ot8qEB
zh`*ErA|BKZ-jGv}GC<dih)tnZP;gTC6Z2v?6oGdPOF@Szh#Emo!Qgb!sf9n20}5&n
zV-yh-PIxm0v=$co!=PEFqD}CoTo~vmA4-@9AcSQrEUIu0<^3JMj0w%e@1Xp@M^k~{
zwocCz!ztISP7g67!~|3ltm`0OTWESC3qnKdEf(Xnl^5FFIFZOyZYQxPvMHd-Ry@(d
z@8tmYiVU;pw;Wo?Cw0*Iec%yA#}Lj!yy8L>;V^4~`RP&@DQGH8U=CY)NW)%ngu+mX
zio8LX&!mjWV5Cibb%;T|!OA1x42g*0;nAT9@Q8$Yp*m7{5V9$#Bb32^x0%f#Y)kVv
zZ7m>W9;JBFy*Vr~Kx#d_em04SSg@YG*l?JX@OKF*)fsZI7)}&)HJmBtZ^DO<I>XI}
zxw6Hor4eM;!E8}NGAwwm2#rYnRY-Z6wh|vVc<Dv~{P7M!HWR+Ijq*NAMFApV`C(zP
z4;+jrL@anR3(mo;!Z~hiVJ4Dkr#Hy1{}Qkv(-_25OkzM$n2-u~YCyUWg!3CvARc$r
zp~>_RL0fE#A-H-W46Z`d+3<*>h2PBqK2I4a6e{!(rHu>w6x+j49%KzRG>&-Ttg4aZ
zsL&z8f+I$0;ZNlNw7GbiknpMkioqcxoFTz&ST77@h8FN?Pt|U#Qbj>yOQ`U*)*s0M
z5p2+igF&n^rNo#A*d;-3Jct#wR%yT~HA2xR#!eMf75rNG4>=IU;Rsbjh$#rGNIvkg
z<F@>;j06x%IC5qpjF#|RYD<xbtTNzE2rVuH`Lld*IjI5<No3zYt6@f3v^;YFb&6ps
z?C<19bkX@80FC4kWxuP0ggp`y#Rt3?8eYnBk`Q?p9SN7{VoNN#i4`<XR8mJ|93q2F
z91%-`eLqEKP}K1qOa(1wm<Y4w(eYhSXAAb{=@GcIDX1g9OX)8_$TfcyE@JuKkB$KZ
zp)v&9!5J4jLb^vHLy5E=sN{)QB4%z=3G3kkchNqF11}{C5~}ab%V?Ai5y{`c@o>xH
z-k;@y?Xl2YBZ+^57>LYO2YD5?ngT;V%2?aPBPVi#a1l$+fPZm|cta0iw-rW7$VuKi
zpFLqFZp?rd;VoqaK|zN@a7;%KI#!+|$nc<GqI(8ExvYi%lmmj|X_zBuCy^sAWoW{M
zOVHWEAJKzB5)az|OxZ39uYjNvlotn0LM=f1R|EUi1pklFqZ<5<98D%DDeksXRb619
zg^WTx+yagB9zEE%;fbx7;~-F<1PjCg*Gz+4{(+Js+keEV1GJ5RniD@|gNS&60Ioxb
zh}a%12HhKjKF*Ya$G8|s19Tb3ze?c3pf13_7XB~}WJ^dvp=2TyZAoPj8O7aJ81JIk
z#38se0a9hK9Gnd@Tt8%rY`^A?>}<cAglUyFH;=6O-2Simm^x6wOWVS<)r~}ogmqqF
z+Nyy5lZOGa&M0C-^x$?wf47oEm%*V4;Q$=O5{5dRXJC0w@i!;H9!uaDDucYBFrfK9
zKX^o`;|U9gS42`p9Gw3KnCT>mk;`?&q=o@?uy`xwDSVx*b7gPnYN69*iBk#O2x2WZ
zaNqNdnF<p5SKu)g^Fno`@E~Bpd32~F(EYbVHiLvi!nZYKhfo<_m_u*s#HhTiAXTDQ
zlPIK2M;vz7niq#wp#-O`vW3tD+YeX1*esVH15`EpDP{&uGB(tjL9RN;tI`-iXs!s&
zX#FKvLK~^cwAEkDkd~a3Pxa#AbW1P_$3$An6Q(=7LgEul#Hk&*6CpTlz3L4+vW2ns
zAb3nr+Ics#v;8uu=6&v$DYgC_98gOLf<$5xiE|n;RqCtIFjCk_w}D7p_Q&AK=;px?
zK-U8-Ug^%0nIqd=>An@73+b=*@C5lyX<ism2c-q0B_@au21OD|XrV~hJg1D<<Fqvt
z$w|sXBMDw5Gy{vN+`q!oiuHS3)MS}oO+zH%h?@t<48EWZYraCT7{tp<l&1~BgzL5N
zjx9nJIl50?MF4xlUjkyF0+}d*7c8x$RqV*K<%x?(xNHQYCL$H}5(tz8vEuu#!ss*%
zA_&i*MV1&6L%aqAK}PjJsnPYTc+dS)`F|B@Eav|<0CO}1hIkUOjPrD`2o~Av!3u;Z
z7J?|-4(!BlW+)7$ZJDlaa?vMa8F?}%(w0fY0(~(NITGU-YruOAA1TWduz$h!%+^*G
z>;`zKz<)QOZZUX7$O;}FjX-V)t*%X35N}IjKwIXAL`)Q4i*Q|Fua$JJ0N2jC!zA@%
zeu?h0LU2-o=?a-}6wbfsw1REdgpVSa%L3#nTOLzD1rgMpq6YvdMDpmsnv+V^F0}t%
z!1jvb&&LX{QGdq(Q5M6K$Picuj+et4M$ddG9MTHDfa0G{Sn%0=gv(q_sNBSckdLmg
zQd}ogrhu&*5s!HLj6}riECU$>2-&{TLFc~%gJ^Xf%vBlo6~=u8Xd`6iutC2Og{y_U
zbHE#uFkPz4NesQ=LM_JdMGXL1K3h1`L`squ#zcN10tU$Xpu=x;d=(^-Fg=C3aXe$m
z!^;3UfYla0$&n-ED^4NX9N{vxTezbdJ!v5lqWGb`AvLML-c|$y3wStZh(ldQY{4fb
zVbqLJF#{EZN9F-~BaVc&fZ9NNU<e9{n*z`)!?mU8z()Ysv~^dzf5f(s#(YjjKRdOq
zAL9TFdqJciR^faaG^e10lrIL-<dp;!q!M^Qe%=_MONC%DDMZ6Ko(c`OfTtrDER78M
zB^CrID~N;`L-oN<MGM&+0EuV_pBX1e6VB_SI1xlM!Rbv58E&hK#S-i>AqwQ33esi3
zeI1I2!#Pd?F#;%4@+#lIS?X-nwi;JRixo_mGz*s>eu<(+)!N_VfYgS7YN$ZQD;*Rp
zDFrEtp<Pviy;7HiPk`b(>QWi-oKvco8ix@6v-A5dXw!2qn`Em!u8A;sv||0t#o8*B
z`yBEO7l;jx?Mq;^1U#fAU@<}h`)>d{-R&jP#-w3PQ$QF5XirS^O%*{P!{??FUH^hy
z1^gU?K3gavx=&QZ6;whDYKEwM|7Kyf2<aWEU}wwj0Y?mc;SEcL83b(+gVt&RWyz2Y
zx}!Bz8Vblf3nru-41A*c5RzmO;(<Ij+(>AbZX6eOb}Fm@zl|hrZ-Cj;t%&W3lkiT?
z-~#aW#<mGWC#g6k(l;<jhBTy`9H=>HFu$RI%)`TM43wuWFaSU?zFZ`c#RpGko#84O
z!{^G-zum+-Pmu{I7)|w+G=Im5*i1btGF)mPm4|a7NFl|767S49?vb%D$(U&m^Vya<
z#3r!<3}d>8WevRR5V@RjVZmh}Pl>1Q=WHX7>0$csLv|fRh2&NE>Vh*4sEjZDeJWav
zZ*YJy7aqR+2zLpDmBspiFXF&TL}{rmD+?dY4l@&ZhlxXpPFYb)gGkUs>0Fowc@zez
z@bLX~kwr-z(u`sf0d&~|Ugi8b3tA9`$<LAa>r->c0eCe72EEKi@W2-qut5hmg(!;h
zt_zA83Ro1ECIuuIArnJvBJfcHuXg;f&6Fvjo7TclaUfmUGs3&8*d7WXhUFyyF|z;x
zN{EGY3-}^s5Mm62DzPCn@l=o6lByta#_<$lRRAB+Q9FOk#>N>y2Png-b1nQJ2Y6IQ
zl_*roiIl_yB5*D%#yitUI7k(S$SS#uDTP=e6~`q(Qw^RU1S*F~@juckr>*}8)&^+I
z0r*M==L6rrfdp_B9*I;nekI}DzLbaa{9+0tV2G3w24*%m*n>1F9E3rQQl-g`%!7k{
z16Ql4-(ZZU!81WJ{y2PXW<xkxITR5Sc3Y!387J*Z^pgrwV&*O(KEkxsu%w8@6a@ua
z1(OqI?F~CQDqYt!!!Pij&Bz&0Qt$|i{EM(X{--AA#Qq!H$OVQ!6j{NeLlcNefq8^8
z3~{48iJM{-?zX}fT`iu(q!uJ(oW2K5tpgEUh?v5(mB_|JCf=|zMB@rc_*Jfi)QU3T
z7$(Y7wmhbQ`oIdnfkuiR05t`cQA|V(k7Ll!RT-r4zYeHp6n_LZV5*S^djB0{XQd(*
z%1OoIZel7wsw*_8=Q>c5aDfpPq6g<--V#3j1AJRqr=~<A2_Pgf22S(x6y8FIw_PP+
z7gZNa2xpV=og7U7%cqc*g4t;=N^DdqFs;Qi3ZpRCV$e=oHR0noaq#1hrC_`ZQx_(J
zg(U$|mm>-Xa8X^-jY-^jGMezv@=7JF2!yf_Fg)A{89bkt(gLVt01Vcl@-}+CoKMsi
z*AH`5g||oxK7gj3wjv{b7^skv+N=68L0bupOop}=n?N3-sVBCE9K3YZ4Usw6H3KQ)
z)%{^5I}<s01dwns!c8$MuO=1`hccL|S_t@JqzeF&rh-Fj{1^um6qSWS^M?(ihmr_v
zkE1~Gt&CI{DnpEYNnN5xf;nCRd#=GSY{sQz00u`<1&7j*=Wu_=$zZuEn0+yhwh-}1
z&IB@6R<Q37(MErj1He05h!9vP;RW%+xJb|zkR|An3aAJjJT%t!hGHrK3B!K62zo_D
zZuVo<_&zX1VVEh+F>U2l4F*O6VCGuU3at161Nu~DDjv5!Ii=fxn8I9E0iGBfe#xL|
zv<D{3Apn3PmNYaJ_KLvanM;%!34(`YKvH2716N_9TMbN=Kl*tfr4coCVy*p|13m>L
ze4ri)7qv8j38|oyVH^y1#i_a+RlvR*9mRo+ix7IEI1v%J@UQ?Y4KJ$S#i>wO2q9%r
zan;}p0UAR(e942n7P3^Pd4S{*3@OwdbZ7x<JwrB#;o;Gt3CL+MDd`B)R^K7O$%)p;
zWT|*GeBg5_$IZOqDrSMB;I1Y%R!kp_Dam9^B#KNe2&V#H!v0FxT7*oyFBLP)Nyt`{
z-Bv{A;lbTjTA&%>D0l#1w-x41=+bfFh=rmVI{$jW_KG4G1j(R76G&KPD`n$gm>XI)
zMk4=!w;RHg(ZZ8I0q<uh++ml_)JBh{^W_QA$40RyjF}eM!v1T1P9*LPwLo%m+z(`%
zT?fbaa^rbbLDdCU$Z9~g&^~M7hdB@<Vx%NYMrlbP;aA8537s&9PA!%PR~K05=T+UG
zfm9l!=w~A#Qz3%ogIQ`29x6s*{4j{qJ1P}47lpJC@Y?4J(t7g70VW8IhoK8@n@DYi
z)KaD<0;~Ko8;*b<rmdbFND<DC>7yw1;hc;;e1rLChBZ9U5!wf^bApHmp=KYA%Ne6}
zYsLZI6E7O2fGnv476^<1M@68EQo|yj@09ff1UN(tGgv?c=@L*f9$xlg91j6M1eh)R
zT1wbdqA-pATGU?{1`-jfKEvNGM&o->1`rUDN0H$PPL<{`=tYHy7zPedQ{f^XbOWA%
zt|#odGfb?`7VzNM)7Nwl!gGN#TS|Ca2)2Rrm>mE^5=enZACl7oMHZ-7EN1BWF2ME|
zLnIUqk0QmB5CF<|Ho$?+AdgH&7UQ9RiWV+C2_g0nO7Y~2DqBF%M5^j+yD>s|P+5T%
zSdkoLfiLtZ%L5@=APQu?5j_6DCx+bmE+{}j5D~UZVATPHl%EM=O#r_T;Q#`Y<H{k<
zQGH=yQGo&!UU<sSFa%~LB0f7?)n!c(`mdnKrXB^<6=H&01ON%77ry1CBQ(DXAxLZd
z2nVnxsDP>+KV|12_%C!c!}=Ej+9-`V0IjLehzt7q)l@K4RsrfPww=77SXA&q%Pa#2
z%Y)4D;|&am06_Z-4LZ7Dz6F8cfkr|L%Ha+}OY^P?T3{YohoZm*9x7qz1q#Cc4MxCv
z14L2eG#pqEu$Y+Oxj+CBWQE*k=uuv&hors-s%#lvL1D;*u3AW<N8v&*JQ1g>%JzGN
zwDDi(Knw);B1#$A!-gA=N&_<sxbTIFn}ha63hD53b)2xH!ZW~Nlo7&<<hc2wBPYKQ
zcs-~lN+rhEwz9{_zc7oxgcL3ba?FfK7!OOosC%Gz6hzIW94U)FK%n{-u%HkBJe=KS
z1Xe2m1MomwnG}M51_bc|0g*t2N0SG-(0FL!M>zl^PpP5^@#Ml_BI>Ivh*k8iB;h=|
z^MsWRR)~D;y@eK;j-iaaDFHHdL%#wfdjcdP(?zj=24%hY?9Zc%FAfrI2Sn1`^O*Ag
zCOXBRg%uw8%HYumSjGfGUO<=0`_v_5Wd$)0$z;i#I5-`S9WJfF5xCisabx4CecBi|
z;x;P3Sbsde$Dw0Lc*9r0gjUhvM0w8^3kUL3Y9xm~Wx*38&3Q5&&LYZ=;LJ-4JhA{8
zl;%YUMUN&xgF^@@3azMg6%&OXEWkq|&UXkWRXCLpQ6o587?}lcL$1%qllDuE3C}7r
zd(MCo76(ERkEUXt!o@I{EvhW-fdbY5DB$p4RtA9rCf)~Ieipaupi>KK4#@M;)p6b;
ziG3sphnoiJJsR*}iWJ54rKGS(AtkmRL|%h)*AEK^MwbA&wFLbV;Y6op1MmEvO(?0;
zl0p(SR8c9O+MicjxwxN>%b4wi%92+C|CjOky!^O)*n~1T;X>pvCgMOYJdukSYCMdH
zxfrlbv7%IihjOF=Se_D?gW!4=k=mpA>j7&A6iW*^IKby{YwF|(#WSLC!H1B72T4<O
zxq~c&LB1FXvq_L~3^H5>@elx`Vz?Iz9KRHJq{i`JXyHdWz=R<dq?W;~6)x-n7ue9v
zF`k3Amf6D+1%%*wz9$G(t`D!x!LBS|fslFLO-G)4APnjA3Xlx~cC9gJOQF#aR<;Qb
zUM>6x2Y5IX3WFc$)L@rPLB^p%g4TlENHDyq3{zJ^DWNu-#2`x;L6MOE$KLzL*L76)
zqHFfq=Xgt2>@8Wgm5?8!V<jjikdt4n^Mhoh2qO$_Pf`aA1ULz4UJA50kU&BMEXlG_
z(v%8ti|B3dJxNn)LYil2+8Zcsc79y0%k}NY^rflWM_WO2^FkY_;nETyB=7s3z0Z+k
z%Q{<5{<+p!(w;p(*39g))~q$ZXRrkTjOD<*oI#%hu)mZ5_L9Sb@3Jpty2~l8YBz=<
zxcx#**-no3dYV329t>y7;NK+1_P$%3xE3THyu51vI#?GubY_8Vhr#Zx_DbnF{l$|D
zU8#BSR#f7qI}_r0A<NF;_={1%y-rm+@_@c(Adb#Qf1)O@72Cf``Vp&wC7$}d)mFOx
zG`yzv?;W_NHR|t(W>AkpR?Q<PVUYOOp(;nOGH&P#m{ePOw){3I@l+hgev{7G58rhw
zhdZ*#Iv=!r4a=Wy@KAv{Jh@=s)Gnw}oG!p_>-5E>w73($ZO0NE<r07GB$0EUGe&1t
zl<WJk<<Wi~ot$?f2bGUwj{O#%HUaW4Ia|kk<`xD@X5+&<AH{rb-=B^VrwzwM0Sp=9
znz1-C!ftE#3G6V6oQ7v)6*fN(gMXL8@hoQ1552c0kG?nXt>E35M~kKY^KLx2Ldl*N
z3-c6iZ6%U?>x)ftdB-pK=``O$D$1(a8CAb1*zdJ!$d&CJ6yI%?QE(q6K~%vGeF^DD
z?m9da|9PB-yA4aBfS*o{$H5)2R-KPp!DxeL7oB!oPLlp9;*sVs{ZLQ=u0A-FB_aje
zu)L^uY{^k$UsNK?J~EUk7z*(iOxZ?)#89m0wvx4!8{D}NQH=YgfQ6oDHbX}$u@PRV
z;dM+<Ss)g3^L;C{+mJ~cj+Fv62lDLzqj>6Qk~p7EuP3R(UIn2+XQiFBs;$FfqA+7P
zy{mYR4aOMF&5cX8;<5De1}$w^G6igp?UPI0Ae&C6HmqKRK0gph_4Hn--yoDSc=%w4
z92h?vH$_@#VBB)A*bwPNJ~9rT`^NK<^JRn|r3XG88P~U##*Xw~hCYtJnL-Ag3Q@`f
zArQO6K<?WZTf23wmCv&ogwdk|2>1+!2u|)-sg<#G_)8~s$-y__O31#RNd6j&Qq0iL
zp=Ny{kYp34YnPrav)Oft7>l>p^LRBseAlmFl2=yvZ(;ay2Fo8$O3c=f^jQQH+(_yW
zxI0e67%#f5`Y;#`<+tqyqmMkhvd4^HG#*!;jgra2`B=yF1rYoH-VjMYYGZv4z14dz
z#wf;<1&$amF<ZxcvcjNabO4$k{xz&xj_a4FzHReZC=i!I?2e0GV|F8UElr_zRXqx?
z7F*m}!~(Sk`=bsQ+Vzv2R`k8Ws04jzQ9W<$il;H#svmM`q?gdFl~A^tLi`dYyquDP
z7LKNRaNnb%tLVj5T-gSG31SS1a=`<<GH?(|64S4jyDph<T;iXB)*7~BeW!WOiydM#
zvpmnI?Z`_3=Mky;Ab}8%F0jyh!GIXT&oBIS3b%nnJ^j6l3<ku$ljE)V4R<&yRrq}1
zCLcTBtL<7M1<0Cv&|Ja6z-rV-PGGvA?|e+cam<}AbX##67iZObusVBNm-G)g2)8NJ
z;0bWPYE11*GaJIHh=ztY7YSQfEAZ#L4NIf|Tb=;4e*5u?>kjj95K2Io!w`R@5K>DT
zuSd6aFE+(}au6%j;OhnyY#c^O7#N(>Z4IlE2eNF5I*LbWNx|WCFH7qRjAJ>xEuJ<k
zkpd|T!6lsWAtO7*Xq4*Kx*I7xwss=acZ0Eq%;36bS6R&Ggac+zCq|zxgG@nUH|i|~
z2v?)qS~fYeZ)AG}`h5in?b(jpL|S9i4a*)JDL{%*7!*$~P-1miw1LZJq;S_ozRs-t
z(74HO6~pAQn`5c{V71DxoEpjvUpF@STxU=k=Jbx4mdTFWFf6qf_xt&5F#)6q$OTF)
zl#Nszv+~gQ#PCEi^;!hfe7BW2%N{H#KmxIlJ3P4{>D_^&+1FL0%HNoRp1GN{cG0sk
zmFz3^hQXDXZGB8-@^fcLVR*4zQUCmgQF9H>cA2;d2Q=Mxt8;s0Md#A9b^N%)%V6`v
zOWQ-~`zr>wVd)e|SO~sW!nE94FviLNj%{}oA@^s)Qk)cf4u<m`?gtE_&x;JWQ)S|j
z_hK>1_Fn|f)f-0S0JZ`c3&)bcXNwq%=-AL<wv}JfhNV-$rcu~c4Xq^6UEpm!^@|P$
zvWDAhh7dUPNpx(Dm3Yi%v#k}35@T3c><D=?f@cX}=in;rbKU72eyVlmptY?_rhtXm
z#HrQ}eD5?-NHPAM-XI|wN8o1wg*kzgOT;@}22}ebvJ|+e<i_*0e;52Pq=EF0fG&KA
zT|}CXh;V#+q}9>3{6Eq$1_V;n)QsuU#@cUl4~}ucEZiAP3ereU1ERp<g2)Ec<WBC1
zoSm18$n_<`IF&y@X|!Qs3b@QW<-x)@NBU~&#etnBc`<sFaL|by7e#>MD3h0Am!_Wd
zFvy2Dvja-KLhmI2%S9VnP~hz`28`BEw!q4QK~P&e!>QR@#CUH(EL1DvV>SK2T}9kv
zT{AziK+#aN(`!U4d$2`a4b*b26m<muyB}jg=(;w6>bxb)<zw`XLQDMRi(ny6{Pnm1
zp>xx766fTr$V3IxYrUJS*nhuV<m;yyuw|n14@PwFYHZHnyqgr{{6{Zk4U9}~S`o-s
zt3ikT)XQSWn;6_Q2K~t>MAR`8HYJyzb5u}<usEDMSq$PV4oigM@d1{W<ql|GSkS-|
z$P+sOw^{<YG2_;UX3G@Lfd0f#ef;4S#zE6=yV=RmK}@1Q^^Va^@!c-audg=YGiOV^
zwhk;H7kKT3h8G1`Oa`Ej=X$j;R}>kv005=7cLUbh{GKlio|Vw|X$r*8O34CIm#3H4
zfZTVXf8R?|FAk0<--UeIbFm_g1*3izV+6IgDsI8)_@q3&P6B%&&<^xVIJ3ImC0F=k
zwty7(hgN^Z&QZXOdcQf$gPw<h&-O_qYEf|7kdp%Ft0+*N%ZVRB=T#9!g<Q6HZV(3(
zN#Ger5$TVL7yt$*xk9lUmQ*~$6L1(zlZ!R@1`NsxD>0Uj)#Ev_+i04SK$`?#oFwX*
z!9FM(yhB6=dwcW*MUNGVG3$VMo)3K%Nc5#v2(V4APhk;n(Bis$D6K7^3uOkQT0yA=
zUOSi+VEq=#wj7#}*p`Ni`oSb{atZ@YYM27y)1qaIcdr^NgRr3K<U6PiuK+Q$8?qVV
zuL-DTb8*QcMhT??yMB-%zM_$5Go`j=9t9LG&jJ#vF$^~k<4A{t+|070*g!yq%YY4d
zM!|CrPS6KJ2UbTc-CG4Wx6XkP*zNEfj~v#Nqa3qp!vYj=nbhEp_~Jd7D65^Z0Mg-J
zpsC${LL_$ua!%)j8F2M26kCzYdV)xO9X)|VV{oQf#SN+aBLsGH93}Dz2OQS3R|P3s
z7)SPvqrZ#lwk04=WLNh%b1SaU*jG@KTx45DTCNC=KRoy^BIve;yDK<RrzL=e`>r`1
z({dZJnQ>-FqBSQBG138~q6Q+lbr6gn>=$_%n#m{r8<qr*1nBjk>_}mgk?HT+{w<6E
zPpLi?1X}-jI$Hp;Jy1jct8_8;2psGV_I$I`e=I9(Wn8)}Ep700@ZHw4o<Cv0kuQ0O
z;-(8?)~$~_DvuA1PJCiLNh{m74vju`B6zj=Hi@^-;5wAbWpX!(T@#Eq-1zEX*O)mu
z4kv!9eHOl6#JfHqk=wFzl<t<`L>vnPE9re>88<2U2uMqb{}4KsHK_mfpoNOgtMFP;
zWk1S8?GF);2UTu0ATelrl`3vNcbI$aKV2#ipWh8ed_vepbw#kJOgn^IPo6{k_}9W%
z-h%vdf=6Ug@sO(wHjtO+yOy6u5Ew$02JL>IE8c^{0h&iCC<g?~J{TSyHyF8dLU1T7
zS0Ogpf)HyoOD>C;^EEe(oKco1n$7*QIe|`I@NpQw%cL*n-0BGYxC+?12#XM>vNSEE
zTNI8Sw4JCnXJNi;)_)Nj^LucS@MRt3g^d(QrA0m2b5X>m{h(+F*rSXQ(txz~meg5T
z%($`A$593{7#=C(kx@8NlP+JG!xx1DA(-g#_FP7pSkMRx4dJpF4(Ybxa0+PZaTa!t
zW4`S0(1qO2vq}odI=|r1pR)wK&|#Fop^@96VD}h^?dM`Ai@ezZ-~?A+TUds&VgRf3
zQiCgPxxkmAT$sxkDI+g0SG?ckFZ1?5$*L`fHr#3y>q@;$LNniULhU3OF*fQBaini&
zZIzXvESRk;*i>9)pj-4p$Y&Go-ywsObKK2<1uWM4rAJ=cYm$p}0i3oMDd1>ewpA~>
zuS1lMJTQrk$Pp%0J8H##?JS(S8<CRA-4?U0A5-bANo)sksKC&vq1$vVf|6C~xxs?1
zk2*OTWZ5ECd@n@x4wENSOz0AA;zC;+#9OaPuT^JxQ9Q!3VQFbYN(WFiKJ%8fp4iZc
ztzl;GaD2n&Ud*<Bw<pl=tPU8Z?}N@g9G@-nrymwuQ4rgVn5e5FuJ%HISTUHq({Euo
z;l4|CyJZA2vyU_Cf9vRM4Su$jdG$RbfsT`p)bowP2}`CE=-&oVz&XD?KQArrUlE&o
z{utPw#WRA5TEbPzOCax(>WZ?Cjc<VLc*563K3cF6zb@*P?XNU);DpqlQAFNctjoK7
zvGC5t4bHX#V!73~0lF8*ZihCDxywTf1(HYn{qzi;Faf!}m=|QtFapWWXfoA_e#_(S
z@R(rxmmyU=O|VNEtv5k0Vp>tgkC_#rEu$$N7BXY5A4!?BQ1D@X)PM>hvm|MZfd|29
z106*;5MVtr_&iPv!T=QsEnY*2lZC_L?V2K_&P7e$q~oDr=LxD^G}dwr^m2wDPd4QO
zgH5a8g^%YaV=`*PL$d@pz%(a82k$<1hQM?*oTcFA<+TKH!_9=j818;$LTzYGf$;YJ
z)<`J^*h))4G2;nWVJbVG(slTqi2~v|<$bX3rQ%%<JspJlktg1<>fvOA@FfC@gd)o9
zpvDs8FB5chTX)_kf#~|2`f&Rzo!IlFqjM6Q;{^L12|W^qhbV+9MtGBTeb9>DJVyFY
z!5F~2>hL65Ry(acMzswn?JI|}v~KIWP0;y`l@-MA_er#kBPrnMg>I|Ff3;FHLH8pM
zJa*0LVkf?hy`(#EkKB$+Lq<C9b~5qjtekvFC}%u_@x8*vK(>82mIMpcOldoC{sC%u
z`UYd&^(ABrkIGYlOm3zv2cSscNTv&LmE0sM@}h4Gc&(re;73?m+K|!#1z*m5-%fEe
z;6)yA-&l{mRHsR$a?liZfBWs8Eq$1yNwh5Tme_SvzyjU-aw8*<(YnD<RR4)%qBmd_
z#A7cMWhOd3ZAxAJCJEf%=E)N{j(Cso<R!e74nTy*(ZY}Lx}J_UcnY}WYP=8Sq=wej
z`CD`qH&e;`SS&!>-hL1pGPCDgP<R~8njfKI+-Fn+Sr^ORGeGzU@YJCj(&M}Fs{cD8
zyc@o`p$0i`!%`@aQ&u^FG7h<j3~FO9E#q@?K@-ZtnMAl0u=g==oDG}qQEcE)12#($
zB1PYfleMMokeX^sBxtw<s8gFkbn-!HZCaBJ0N)QdU~?2!kLgaErD4Ilboveq)Yu9l
z5E2vxEN=348ZLL9#Ad2(O-o8F4rFFsLHQyWHK>at`_Ow}4%WdB@{K&PcnFj~2qEfG
z0MoS$?Z-n#sG{3icd$Xoy$I8uMxvz^Fxz-4OML<kJHjYoGX+hZG?zV)HIbqpYCx%=
zW^)h(W5=DqtICd0ML}5S#m9+jFbOTBu5Hx1puGSL58Q$SJfIJ_>a&Hzabe84;u!?z
zVt{PVMfj9ii}h2}BG);O?M<YZ79H=^HiSKzO=v15Ch5Y>Z<pjC32NX~@)1mo&loK_
zk+ZzKND^2P?w{HVNmbUMXTeb;13RJMw~==o&#f7h0_=fAw$R87KGky>mPG;Ct^;CK
zdV?%=PWq=Qtb%1b9tBbxj*S8oxnl%s=6Rs=T#GugZ0({*?Z7z{AgPp^^a!%gL7HbJ
zqEmW#Beb+q3peyIs!|Ffd11L~4Pq2vD8j32_|0ZTtR;bM#6VhhNimlZvg2<p;xvan
zu(^&*B<Oimz~GJ>0&RZ>7?xNWoyjt#+w+p1e0%{IgT;^h1|iq1#V7!Z;VJl9tua!T
z1U!xk$X1CM$+TFXz?8?GpY2hjFS`J8fpk3=9I&~5eM6|bP@y*Lj97t4`r&`iSsckk
z=8<Ep@;u@&EPLn3ES$)mDEYzVM_rznDS<p&L4d|P7cIb~K_XgM#<ut<IEa*Ir=`hQ
z%%5SWI#_Fc;M}=$NbDSdqk%HVcQLCk1?|SsVkANsb)i(&fG3}^!f~LMpeI_Z5%>}B
zj79&#`3RPhI9c}gU<N8T`LqdT8cpql`=-_=uyAqA4~jB>_^;v*^zrdp8rL;2yzDm|
z?e}36K*3j12s@=>KZt%<_`*(%w%d5T?yu13?fQZjzNBwuP<!JAzEz~U{e(dFUp6TA
zuZBea`PAEG+f~TwNz{+EA9jac>-ub&eoxK~wZ8l{YEl*|f}_EL*$AL}xr34bB#_+?
zs$awIUmhT0bQ@@D#wEIvr&)qsTOpUlj!}8@2m9q~7;JLut_mgoF3Qc##Za#PA#loP
zihS{zz$g#@@!4+0jLzGjDDr@1HvTjkVh7|SKAeURz}wN$22X*SH?N0T$y;A}L~d5K
z5}vvBft0{kjp9s@4%v`!_B0BDXzCY%@Uu?j-ji9g7AiQ7AaMF+1Rvbx;~4o{b4Blc
zCZ9(2SUio!Ll}%?w)Sfg3K;fTsLgUg_^uSKh)8OoTLJ8Qj9`A-cW5`H;c(QzT%<eI
z<Xxz27F!```ttTXMrYPr2Ci!+m?z@$#L3N1k|&i;^^}^WtsC!4Q?aZ&br6FP;WqJD
z^yeB057uGojzs{lq-@jZhnXlvZ8$0gKpoa~d7;+=Q}JNOu>=klh@>~kDW8&Z1bE6+
z9Gkts3OS!sZi;D&40E<zG`(_I7|Z3rYojcMt>mFKM(SkYa4K_kvk^LVNMr!CobfFh
zMb`y^2|THz4H{PSxIwW;D{5(Akqiri8(CVs<%3PKs{gs@w)V=~!J|Cj{*&pEd)I}7
zjugIFJlFPMyea;tGCHUuVNk=ll@b+A*A&(RPrWXP^?ml5wA-5YZsugO-7g=W<FSaf
zF8fpQE=oAT;?sr&DBue|dyVL}Vk4?wW3&L;;a;7WTB+7iBL2Ntl&=5nr_GZx7|9g&
zK7>*J&#egW>ncNd53bbU;tsoZ+pQ2*-)%KGZZ?xQaZLH#uF$_}Ulfpm#7|`f(N_bR
z==%T!>Y~w?Pax@_6w$rUu3tj86<pDMZ*$`QB#6v^to8J&-G}k1pWGhRp1#~BuJm85
z{KsiwJhcm`CXAE&&PNs7vl$KI-;hv8emkvz*<03c-r*ByZOknU@uO?$6iXuu2pt`5
z@D#A##J#G$dAqHcUlTpV0l~YaJos!6Rk_IPr4T&#GSL}l`eYcCKJ;m^TEGIA4WkIg
zV4|4<;p=y($o|G@rPrffwYTA5D!HNd$|F$I?>NGHd3vP8(4ta_E{Oz)Ib>&>vc}hS
zSP^a<m|BM%jy!_)6p{>KR2$cp`wfh)kyX~wSyH|fPG*~T@MKAeA7{um>y76BS&jvw
z48hH!4C1}3ABM%r5$u2f3eLY$Gw}AB*go;qF`ZV<k#%W+56x>h3{>XDUAB1WstBvt
zS}qEJWnRRCQeqK-=L-NF6Bwh>;F4PSVtbr++s?H8Y7sBC2De874FI|BqDo&9WF=-v
zah4^rXVQ{>xdpc3ap%Lxz-8jY(_YfLl;gKi0zQM$Rk3N?#+RQc<15CS&|C)k5};9P
zmJnqbqIv>X3M79{0JnCd|A?c%SDP!%#h$<N_!?{Utrd~qkL%b6hg8=Xjx=Cz#uml(
zn;Wn{=R|>`#vFQrhOmbRR|TRMWR9G#Bq!c7Mk7n9(|9f=7?1-f*pHlSW8Z&_S4*(}
z&j%RIeQ=GKuU;+s#ji`C=Cn|DpBba|v_a&G-^C`mcVSxBcU#>M8d{kA@!9S{o{wHM
z);eEi%kSe`@pzHP%h5hBfF8>nl)pc`6b+Ys=zQjyZACvNzVRKHJ;7}2V_#kw#-F{|
z*LBy->~K=J7t4Wv*-C<YA7$NXI4kWBci=9RQY<46Ag7+qPAZ>83)yE2WBc1M{CG{C
z(L-b_%`(X7WF^4Tm={2gHh==FMTg&SmoVEpj-#NlWLv@~JL~qq?~|+;E{q(mjYD$7
zff!zVF}cDF%C#W>WLF6KV=QY5Z+#i$w*mS@H}*M~mayif5wrb1Dh29UNDOMD$S<J>
z85!~q^=MGW?qNx1Tjf9?4u6*SVN+RhqnyKAItPH9@=ocV1+`$im-bn|#cWGJT`ZYp
z5a#@E)X3tUgKAWG5Y91Cz8TAciw^(&WaTtijJLwd<Z!b!-hoSCIy|;NJNOdz3@XxN
zP_egwG~2Y4v_NeKlLD3osOAZmQIB4W!2|;pf@Z<Okp!`9ivD_s_jpiBw+PTdUZZ;o
ziLRv;Vuc<l_^=G6;dk^m?gs^1Z4*J8wzlO+3Xqe7cqmp5&*I>k!2{5>R>A@Xd&pmK
z$04b>6A4))gydo%Z<B;`2~gEM3YvU$%%}k|#v`=hSmf=pFt(hknLR5MnXCP3QUGiK
z++w5;v#shKtqd&F4-Q;ChIUX11YQ9FDtG&s8cR`=k-BycJE?6E%-a<4Hx|guDinaH
zkTANf;3@~S8c@Uf!+OK9*qgP3-iDY@erz$cb{HsNAw;MEZ-a167XqvR%?aaIgQNQ=
zL_hbjFuHS-Wwc~yJScX?(pkZ|B1r}30qw^g=z$UBu;CR}qFXV??z^oAFt6*gMWosn
z*2MBgzmuJ5w16F_#5}+<RN`eK?`Y?TQ*;$i8&W#>Rn#|aL!*Vn&I9`BNls3@&B?w)
zmt#2TBv0Yfe_AYskDiJy&VNuMR}81bhL9$Mr%H6)^I+b!n=xhnv=o%NFxCgqZH-r4
zXz6YZjl$rF`l#R9DwcKx_@d$HXoIJKmr?V#8*`F_tF|9pXPo`dxbys3MBe^#i>Pmr
zkC>U>T0z&z13eGy)J$^p|Ji{ns;;mF+lemGzR;?##v6I*6KilnfHs_qypipEsGTye
z)$WVde2lgW6i92ld8As1E}E`C8-UKE@W7d_)^$+J6|`rDZ-5UV9`mNROE}%^wgSDJ
zdU{j)J1J_uXwC6H!m4w8GIiT$=lHd)3sb-adHSr4xRF{vC$1PdO2;C!l)x(E`mm|u
zt-g8df`Scj3P^|eKq5%N`B&4ZV2V~+vbBj0i)X9LUuVpXyS(fUBC}*b9B`MXNC1ZL
zke||nQz~&j1jT;9A6O|ynfl3G^wQ(S8-q{A)#w5!_%vS1r$afmF^HtK3`^QlVu1jk
zmsBngWqCkL-Mau8NLcG&IIs<~rkpqh$>H5hEua@rEO$<kw-!%d-vF4Yu%+M^4>ue~
zeOu4JbI>BgxtRc@rYSPh?N6<3)05a?kUxc_K<eaxCd)XZ=KcWtFJA41RC*?DSbM@@
zWCLpvA739vdde6`KP15(Os?x0F)jzZ%*6q^yEwTLi()p8*O;HiCr9VB%$(WAC^(u(
z6omsW`;4hz>NoibOsEYF3PfY?NM*~-prz@hpb@m#n~2rNci~<O=-+34)uXx&RL(#1
zvQYMZIhOIKS4jNKuVS<*SrLXmT5Vk4`!O5$%tP2twRKFwBCe5q=A$SUh-!n&8k+)q
zLJJ#FKYCJETB+!;s0#z%D?{Ykz5<R&MeB)rK^Km@?0h{PLi}vYpWaerh(s|VBHxZ1
zsY-rpYHZ(uM$(QgXdwL{_U!Vd<dfe8v3qx8&FHtWV&b!xVKnQBA*WNX6?x*PtRl12
zl$OPyk?rKy(!$_VM}(R{6*RwRu@u^2i%|enBqVr3?LwPq!eH=0g5+)81HBIx;5|KC
zK2$F@f$a36<Ph{rQIEU=$3yS!kdpRQTlZ@aCj~$33~M~zkD}BZV}i%nR=O#yZFos2
z03jJhn|BivvuSfzL(gP*_y!adF9X#K@~A>!p>dpG6a$(U4$CltLmRmTjHKb+XnT))
zzQT<%gnrarSvA`tfp+jxC}4q1Ek1yz68bA8xMP2eEEy-5Ms;}63a(-zmQ5WSoFryc
z;b-wMat=su5p}3s^Tx=L=y8gYlcaNhy*3?K5SmJ;m@FL&wjy}SE5vcw$W8*sEHc*~
zQ7TM>er^|fDm58^D^u(qYhgoun$-P$L80U;cBvD!VEd7tYvi<W?B(U_UewR!&AOg(
zE2expF$Nh_!7zdiJ?~NnHbz1!v5HgzJbjGkwJv?iT~MT1Bp>rAMmn?!fww@YImGmn
z_{a%^SUKV!CE4TLJ7HTV57-9MGni)^JY7TW=?=)fnyCje3d@7&#JC${=PnaV4&rE#
zJ`G$n=H$QPLLziqtI|0(pilIJ%Tp51{4|HCSsA6gs@#tcJ+xXK93Bp#W0t(yX0G<j
zQ-J&+>D>%ALFS-tS``AZqq@IGrhn_@u{?8u7ocQsU}~kS%2IjUTsL`FD0<&z1MF;y
z{M}g)(JDl0_p7l@1Kn16bd_}d?z_jFGgxT)rd}o1;(%j-{P)E#Amy3gOt)?#ihCMe
zr5%vhl<A8nvMfSD2;~o@KC`qK8hHSSz6F!q0nz#EQ!GhZi-!DdWO3h(BVn?ALs<Kd
zw@VbyAd{<35xM8yPALWG;r{WTNto<7HIz4?qq6<}4UxX0GuJG7=)W)eNHE|wm!fVI
zE$Zc3)S+nrzQN&H_TUxdF;YPpFO;u^qm}SxxsnAUG!CYd<nQpB2GwurshsF{JkH=a
z0@*0olL5Tsp=b~Yqf!OBJ^|}jPV;>s*cO45sfhl9m7PIYZlZ4Nw@rK7@**hEEDnlp
zD^xfxR`Afz4h-ye81laXe5DYl0C}EuP}>I<at<bIH`-2THB)Thw|XmX3-zFLb7>W;
z9ljU^JcB54V2dN-7!BC{G}|CKn*zp=Ol=hQ*uh|DW`v81vD!&WBU~G5!T&~~07ec_
zg9!r^2F-9)66<orYooNL0EDXsp$s9M{lM<jGzw*|AB>tLzxkkXlk%7$bqOkPDcC<+
z6yt`#Rt#Iz5fo&d7g!gAv|Tg^lth`Lhe9oVx6PM`0$?h+3%Cmk7hu6jj18lm1Pg(O
z<~5aX!1crin0*n%T{!}QA`mNhA39>^glHV8TCmk2I*Nvr8BuApVU_~TazE?U(uUQA
z^5b<OE*x`c3#BQPPeOIs3%=d~a<kjYn%3{ZQH~c>$>Kl5<GZal;`ZNXCPW@M)rea=
zx7r29!k_`R)b?nC&^V4>BazY;KDf)b%3v2qW4S|A0R=#7L#{YHB}h^}!2GCGo`Z<|
zIr@y}e@hw5?cE`A2CfLLJa(7p6=3b1zY3*0g5zc{9~AextE|YxL$P7ERg13^edUit
zX0FEhOk47?wHI4zRnOJoK!2{+Xs_kxTKD6E1hlbeD4yjG3N5I6uwxt?klJ}<a9)xS
zk%b|7dW#JI_IgW_+Jo@@$q6p%dsl}^MuJFo-2}0E3YmOwb+7Kf421VriQWsJYfm$B
z&-uvq5DL|6PRW@u(YihmNOIlBV<~mx`;kJtLUs(DT=C!I=+g$Q-}STsp-(&}YJ5e)
z&V%PUvemt7_&Ry68_dISmE18PIIn*=mh<3v8cp7r)u?b4<9zaU9X75XO{o6{$97ou
z1Qxb@kmy%{7>k9L@G&lTgBY!3mTg#w0=kfAOFs?<Z_2R7Aok7UTl~T(O0;FDSNN=9
zp%EOLN@0Scplm5u7~TobmXMY}OT4irvXR2MNPigL(S{=_phtS;@KH;ov`%(mjJwA`
z-gv}e9U}Z8N5&Ch7`((bx*7(ey0I}@!R#~+IEx5ywB|~hl^Q$zOSmx<iAFRW{^Sf;
z+VB!l0K6-u?67HytfO(U0;bDV5_<K*;(@cR3a&y<$xg)7Yw#xP6%x&NE1=*55|kBJ
z63(Tkz>SsA$yq7MJln5y0rs)bf!!Cs-l3Gn##DATZORee0z8M(0GK8dY3qG@A!3uh
z*9rqHP76m9c_E87J)>|7VpOx#D^jVC<e9B)#&27WN&!s2=w$c^wXEP=JAek|7(I`-
z!8&LosTRXO7_wmI44zTJZ0ogV9D>!ck;qoJ423#M+e%Y)e-o&qcMDJ-{yY-g&ZW)&
zDv(e`no)1^>NLzFv<)vsLiOfI43Nq4-4fVsjepDGB>oYI>#eLF#dTxd!>%{?VUaN8
z@62^kcwc2i>>*Tu2HcNswAie1Q#K@Y`YAH;88o1h>6MYY<0PA70terQ@00ks4t*jn
zqW5$Gzgv?2;r47R2{9KGjxdB_@d&w-3y4UfCgqiZd=<kI0KZ81H(rHJ#qV_DHmnvi
z{1b5DDTwBSsAHeG%nr%;Etm_xzf-jKS{FXk6KHM!SY(%!?c@tXZgfu&$fIkO+1CFJ
z(SQ9yw8P+V^jYrUOM6zs9TP1eu0dG9$?arJ@<G?zJBh96@^zGte~HSHoB;px#LB@9
z#?HK#4Vzy8;w$j%>yU8oW>~IUYW~RuIDTTJTZ-99!uml+c3Py>22y~7OfMRSO^nSG
z)Q(sM1F>h{#aXz^pY(n(>Lfe3P2LMa+_<+`d;w}`1S|oZfPq&c0*a(xABRNl!q9Us
zHBK8|ItpMT40gjXJ?CJI!y2QKRk7E|1b7Kw4njDIMuYcAsHOn4K1}7MD@@fQkPC?O
zfvRzW=|GFllFp5iJB7KCj#s;bq~W(2JcD=~o|Z5b01=M_z_$=K^-<!iatm=LX&J1A
zrw<r_#p01M&k6K}fRXxeG$C@t;|H_=pDl5y=Br3XyV6*rC`gW0eiO58!z_t8D&%FZ
zB~jkP)(Ke(m`h1gmMK7*8Ug*_m{<v2L`_VhV=)s;Q7<@I7u2mqET0(E0s~us<=~WJ
zB*NiD5j<1b#QTY{m3>%*46ig>zLz_k43f-{2rJ~==FslqM8P1$Cft;qkd5oWqU{+v
z2k{57m?a5N*I{!caH6#SJ`3Ee6N`oxYuwg>Gf52!!3hrQ*ix1tY%xHJ+fZPTdW3A9
zPo4NHwS<6*@!!L2+i*-2SWM3yJ<K)pnw4sJ1x@c(mfltf?eMu2$WPcgv24TMXpJ`9
z)rRGWw|XD)v<XYfI&4OpwJ5C&u(Y(nQ-Ji)MxE*$T)F66AtK^ZGL=KWOb6g-gwo~D
ziqO=7X;%6hq#Qd$jL-(Q7Cxub2cz}cfiIYV)@}(EAYw5TVp(R(xqsglsL4ItT!pD4
zB!Pfs54o6lbSf!>(A~iPwJfEwl}Vk`?!rQ}Gz2s1;#*Q^LZb~k!I-{WbfM`4o6GRL
zcMGG&!+^#^Vj*$ILV*{ZZFngtV427emTqUg&Lo^DqOoeQx(H%326kbwXa?W{?rJ5j
z1t%z1098Deo!V6Ny``n0O^no*(A`6$4KD!&6w~3!DPnYzLx)!EKZ9G}aUur_<$m|K
z@cS-v!I>fT?iyxZDPLWsL6dBj-sCsYi!B@JoVkcN`2pe|L{ak5S(Oms<N;ShZf%&Q
zKoM3;C+RXvEBY(~L`-ZU=-jmpa#k<HsqzPq#pnkTCEqK^&<EDy8mc{y!27gV2mTyg
zo8p*+m0i~T*3^1yp7}##Yo9>eq2EZ4pIjuf*&t+#+XzvJhEGey8_FOayR<v(bKR^A
za<&a-6FhEhejy-!oxU2vM0v^u?>R%Hw$>D7$GfnD>eqanT|u!Nb=_MRdp!mhcAVwp
z?>=mdi*bSL_i;+kmwpVaJGV(N46e)g1%VuRy#!jlK;-^c_(Ih>=ljZ5&pFs3lS5rb
zqYra+jp~6FxFp~@Rm=D+oNWMEIEDZ?0T*QC2VNOzMlkAA?+lXKZ*y?hMZFzzrJgN;
z+o~9XS{YgQHk6Y|!DiQBRK_lqM<m&giGXLzGC1-F5O<sz+j;fJtU2%@Tg{cXb2zB$
z`)ENwxPEGPg0ccI&%Iu*Pq#DYN@F=7IsQnn=-6P4;$k`AQ}GF$F?_z*AruusWA{!0
zZ|%fv$_X{M9d-eZP7AnVB?ahFvC!VR<g5xzz1^Jve73$&muK=BJEq=-lmd{Z5rIJf
zKk|dWTLojWn6H81$A6HFg51g)mQ1?`9!9W%3bO2IwUvTF2gtiH=K~Z@<V2F7HS8U&
z4e${q#+M>BRTc-Nz~({BamY5zQh@!*V}qK5gkkLo6m3e=V%=Yxfdt=dWC#4KoDm=l
z&<INC%DB5>>qSI|w`Gy4)nLmF6i`JWakQjh25YDS8m{)+lRTySF%iRnDQdCfIAxv-
z!M$**2hCe1hlCLhpozy5zN;I|^jhChht?4^T$B<;uoa|yv{Iwwk8#2tX#pIof;<U$
z>}6nJ_)RyW*>X%jHM)0Acj(rFSuc2+I(NMl{SegQo=-_{_4hQE)#FGRf%QxJolH_!
z-s?<|ppk}dt1)G;BY6Xk8+{@u=lz7LRELmdp9Eu?7A6_C_=H*6&70D3jHhxB*b1^x
z05W-^qZLr_MjtC_ao2}2KlaloMC^D&CkFL?^a+>TjiJPzFG;W$Tt&CFTb_J{I{O$#
zo%T+nL-O#>kr>@psb7m!c)01+Z({wN1DI`6U9F~6?TdPpPBi$?*ovNq(9#jmXalCO
zsSCMq0RX+0uhauku6dtvmCs*{InbLKS0<i&lc`ViOFZ!7LNxgLuBuGG0AlYsNeaQK
z!Fb;R;N0NQk=<9YF1P|?QRuPi6>E*|zR)p&R$wi&t;Izx?z|;%>{J1!ieXp}KRPj6
zI8*<&2@1Fd6)3d%AgGpy<)GOr+Lv}tegZ9<Kw!*c(l3M1?8#}-1G2~1E;-en+`q>n
zUFYg@uop*n8!O50MAEsnU#z|djoKXGJkG}3Ev1t6v*HOcmDD-&j+Co#w;|KIsV-YO
zIkX5-=X{#Y;!ePAk(vgmuDdYGUmM(lZcP^IxVyr!PsE~Q!5Oa}hVhD*v}$nNYZOW@
z6GC<z<!5Sb$S7cspag|rDZo~!JUko2HX5Z?NcgCz64j(vSK<!20nYS9UGfPAkeyf|
z1LciDql`iHY6%G|3N<N9J+?lQwz6ABT^<No2|wn7jw|UTr094CruFg!+}797LnNX>
z;s_0Nr`R!iILl^pMJAFuosjL=Nwj+oljywwG`_N+3@i*MJ~9%}B2sXZ^lbwvkkV3*
zl^E7j+VTz*KrD_ga#%*JsAnx51O@w0nR+|ty$fImFf|aJfM<hcY50PsHhnE^4hj0K
zP>RxmwNy3JOz(KNcrxYxk+uh<-D0-OuZ@t-X40YMghMRFVj1t$SBF^Rfpf1#=^2#4
z@TX(iS*+~BP+<u|{-DJ?>`*8NJ~Sfw!w%rI2C@%o{L?t8c*~H=eJlJ2qYAGGn%r%e
zLjh1Gv~-iMU{h;wKp|qXHNeWElW=_2zokqW!UC7+x4L_h{W~PwjN>ZFhOuNdnpNkA
z_3K_(F;S^ZOI4>{4oUqBCtr9}>iVypQoQ;Kb0tt02Z!{SZEbHM=;^sa;=U)Wk6~Wf
zjc#i!Lv-a3dmrg|H}1yV7|E~vp}zFfvKR~^kchSY9Y!uc1tSn|vgE5iSJa^EQjwWw
zjPX65>33raX9mjg$CyE@;C@KyyB<9pZgmT`;UtNtHpqc5l`K<Bm%Zf5wi5|Hd|I;%
z>gNU``-U?@v5d{a*#?Zoubp4O?GlIr`qmL!Pf#D};@8BndsR)`2XV|2AlA1!oaGGL
zfnd~`ucOf<zi3sS?8W(5fi+lcZi2U@nzYIY`JlW@<k|JJ<p3LiFf`)wMP4RYxzz5_
zY0(7@Zm^WlLH(hd!V=>8(Nle2nr;nK<`5vSjKOALrPFbk*J1m~jlyHIFIN8AZMgD4
z5Mn6XypgCruA_~4w4p%(YSblymqZ^&VU9rUrQ66c?o)$CHf8uaPj3<%3lRmXSWZgS
zV<jHw(g0JVXz0MV$&J}W5qm*sVmRrqWEjrBcPKA4Yp?j9L$)Td=J+kiI#B~UQ=xn+
z9)LeCAVLFY3i9OOAzUPkDHn|5g1ZUvL!-u8(*=(l>%N%=1RN#7uv0`0%>1&#gMbm6
z78`iBp}~hGQKCsddynIe0CZaw2D+`}E|+$T!|6TLiWW~QkO%@Fd|wq?n<oRDUkWG2
zDqMsbI>jOK(E+nGX`lsfwS(jQiYGy2aF@BYA*Dddpe0hoBCfKXGxd7dc3>vkjidy>
z7C~1BScuXYuXLXQ$NvT51YT>suO<ewt)V=QZfo^V5by5WW4Zd}7^1((j~}-F2Be)q
zFx8u2d1@0*k1ALsoC$8zcllZrKOOAh*n8SD$i#up#o^$i5R*FgpLc#j?mG96Qse@z
zg6#WfE!mH5Yw*-1199btk?gkXVtw)<v6yWQP32!uBtBaT<<3ix?N$`4yY7%qW}AyE
zL`;UzTi(%^o(@lu-HDkZED{z6d%k3dc$~x1yR9S$3WHa$gJY|lJpEI8={SsuJ0B8r
z`V3k`{}UBv-*yqF(6Nu)7Rwi3z|m@buQweDh7<fDrQ4^(XmxFx8k1-NgLdL0SmB68
z!rH$jlCF1qC9H)Jthu?n-EEymz3N)BC>7Ru0Y`QC@!v-14WE{}+dY*z-Jn|yiTaK`
zu<m!xk@YcKHVK~XovyBz5$P%?!9hqS)+W1taJ=*CPx~sf%D_c|Y0dl-b}VC&us@4b
zFG#;!UuTW&*F__@16xu6RGkOiX!z2D6?IW;x6-lFAHh<KJi}4D!YkoSnxn=KLZlJY
z(WF&uo<UF^03Ne(hzTvs8NHgt3*g&f{u5Gn+Z6laXkevmkwlX<>^o}78TfgKu|B24
z+>p8OBAYdG7B7rQDCC*-Wj-hzKxcOh4Q-3dAcHaPboBt8j&5rk=1_ozyhsuQltzAF
zzl4B!aeKbEMUM3(3=hh6`(a5fTn_ru_NV?h>&N!WX88jHkxS2cU>7$Zgydxvv#qHD
zP9s4BL=pQ{ZJ0-a!FjIM4v-K$$pCZ?9PP?E6osm^!*mi1S~3n?01k>yHtb-X!{A>g
zrinwOfZ@3Som@YprE{@aHhni~uII9~L!1=H)&<e`%+6UZwIYY*s^S}inj{5B+)6m<
zE%ElVr5bz~!Cv%E4XnP^4na<_3iu(xs+WN>?q%o<Wrn?ytHLOpHtq^=TZ3E88<^6f
zV4)U*twAVzSK+%|L%JO!#R{)BWE8M?Ph2Qc-UfY2zBXu;g&+O3=h<;gxP8n^;Un9B
z>WA><|6Nsfdp^RZ@5Z<jn=9Sa&cIFHv|ikE4^<{=8<9f=SI%i21N9}WLbdygfnF6^
z>AMNlKr67|-ZpH%t8Lp6*^O1_+fP&uNY?)6WJ;W1@Ttw+l#Ye9MmFtH(PTx={v+rs
zn{T#(T@8YgrrSQSgK6o1!#>Jq&a|d>@MED|waRgn!TseOo#Gxj4VrT-2!ikYtCQr7
z?-Y`MD~>JI<eMv`tLw{*-vTVc@2R6?T%BgCSs9#Uy!$?@V)1qeYXc~76E=z~m-o)3
z6w#JcL1VX8@03l7asY4xav~)Kd>V@6(0fz4N1G<V;13+1?=<nu3XWu{xI-9wkb46M
zQ$pUhal+`zUa@EQ(_?X98#`JJCO(0fbHH=gzQWG&YFj}8#lP2Gj^vm}GI|^Zuysn)
z<CttZs1Lk2L2Jo3Uxo}isNRON50T_3LY<`%S76rg_@dBL<jQf_b7*14A?SiThMfNi
z9-(c30w<%Uvli8=b8zu#4GI)LQIn$Ljv;R`6nJx2+MWrKXezmt>#~+`plkr65P24$
zO^a$3I5Cd3%MT@uPFw)H&D8~nvJ@{6&;kF^1|cmKEDr^i9-Ia1utmI9>;lUaNVd)Z
zavQ-8FGwbACdSz>gK*X{K;&u&fqx5VWEUWTKEz<6ge+$31XA>6V~+BdvgXPU5Kasz
z%)*ej`o?LgL1%117ll9A3yy#ZTn!=9wmannm<v!Sa0RDRm-kx4C`#FfQe#t>XTZn`
zX1C!*P(T^?mYz_Om1!!a8IJIx%>}|59#^2_bV7U*yl~Z#=*3{`bH!oNdu8|FcC2)i
zJ-8Y2Bj9NLAL6QeR?OT&g5V=T;gy_+DcrrMViD>ku8C2<8msyP*XC-IA`m4~!_tE~
zEteu=L#XRHsMMK4Iw)KDQ7WwOd{w_p|F|g01K{#!(d0caQwsGjPw15WuSP5Bg)x=*
z-W8&~J0YHES=BEyle+U%aVPx97YlyH(E-`&U!qb)w>6N<aV;pn1E5!|isay5rYfF#
zVcCNN1y-yzljuKIeYcfE6S-I$VlA-UZ&ZGSPE6mo`g<@cs6%1*U*5S#!fT&5PR3Tt
zRNt)~1Iag54EO)(%djHihuE%j)<>o0>QLb%f8Y1V<RH4O!K#aV&D@$FBR#fkiB`mJ
z*z7}<44t?{XA370mNQuV`0b}*9T0D8oWXXsBpb7BO%$xt$3aMud<5&iU6@HumlQBJ
z6Uj$0=#&&>!VeArt6V+Z7Ug1~V#;+CSI=b%^HxzAU3sO{-!|!$Maygl&-Bc*K%7_l
zYT^$iX&HYRA+UF;{Jma(S=w?yrU5A_RXh!VCg-U>J}HQ-GjRCE%oK3qF`zNXb+aZ_
z+5#}2fC{)JxI%^kmZq^XcOCC}Y|i|b^J|3Fss&lBmzZ4SNyro4+Xr<@U?fGygZ);Q
zNRrAPd>sPd2XHi05C^B1S^?NVM!L{#MQbVYe5U7O;Mm6{piG5fYE4a-^C0@UagK9)
zDtG90tg%b^rM4sG6yvblO7Nua0SiqhIG|YniT){gUO^b76q;G48!a6l!43LX7BjOi
z_6nH}p%Bg~f7(bU4QrdAfFBw1l$b-PmXzt0Gbwu+qytXgoyxCG1Nd?dhE*6|sGFH!
zCN37JRW5hJLc}~!gsf+5Ri9WRQs&ukF8jCEf0Fj=YkNMfx!X&(%Z(eVG816*k4qz_
zLq|f+{EEWFeCXDf)dP7uy~JVT6$Xwk?3T`J!Mf0*GXgjrg(;LVj89BD`-r=>XY?rD
z)<Tl}T3Q?sYv@rn?L3S&OGoO)opo)<DBw`*l{Sum$WUtC7+W}uR!1k)n{QIt^6gi7
z)f(>o%)=h@-KzsP{W|L&e*AI-oQ9pm6T=t;J~=orahsL;xjRGQ;x+tB*xNr5*K~~x
z4vpg65R68oRe?|Es7AC8-ByR-T4&WYl{tQdM7N~@(iU6lK&;=z;!t#3{cLL&i+r9Y
zsa$skram78Drq`>(883-&#cw(zAs1hfk_Ng{9Gia%h@C;kCVq@_Wlr6?<*5iPM~?i
z&a2XH>w#fR?w$OQ=QR_Vg+2EUcf^R&fdkSS-*i6oi6x5J<g^2CxRvfdy1x-XR~w{O
z0uj<~>k_EpPZGXJ0<SvVZpug`?;DE3nN_&(_&O+JyNSyR5%4v%Z4^s_AO2YiR5=RO
zf#dQTIBtd5KCs3_@`}lPdD{+`A~wgJ8}WkChOPb1D4^NfX7AiD%`j^t6xu+>2mK4o
z8Zznn&LQyiQ`HnL34rA&-`&0vx0rgxcH@%6kVt%1inF+h#C(qmE2SppVWJe}QR4IB
z9M_IA&N8#?wvytx;W6K(Nl0c%8nNJVQ0TEMB|`Y5f`cJ#?~xJZ8(p5bi@p{C#sv^(
z?4zN`D?^U}UXz{tV}Z#M)SECcEH<y(iU2=3)Ch0C(aE%+LZnL~MUB{CBmO<jW6&Rf
zzHd6gXRy}L0}<GRqNc}gif-9NpU^kH$=|^)(HZ#U0;Cy1ys7W!FA`?#wzSTrp{G06
zChUf1eQrQ5JC!f!*+unA2IIv9E$UVeRLV7MqVh{1zzlj<#d7g>Cdd%MVrj8O!WE*<
z0p^592eK@(pb4Mx9K2<2JrAo;zJcy%@&=2s`;^PANpd~9D9Mgc^fMSys;3mjqBW5Z
zgXR$jolZqkZ;vOWdOBK6_l|?TI|J}=WYn*TkgtgCn(mmW&b$SK5pKA3j=<Qf&2B4N
zUGpGL3)VcpW$bVh7h1Wg`r5k(ainiCdVjt$-xs~#NNomPlSfW=xH02)Pr(abhg<Hy
zUO)i>69a6H+xux$o^LLi<g9bR)%QWhs)=#Bb_9}oX%KQ=Panl%(=%%eXFG%A2MUUd
z78-C6-6}`N9kbomh~m5LA8Z;BFtiPBB^C*@TGDuh4LIAH2Q)-y1zZvP8c0oa!vG`c
z6&Ij!bh=$r+qND%)KN-C!TjW+aj|c_q%QH}sCl~*3>C%L#!m9T?2pGFzPrHVa~cBA
zbQXb|Ala7T9h=-lCa(&oIctxm0p#&=2aAdkv#lu^{%6NTDe)bT)?~4x|6Me=9vrm_
z^?gbjqY9epb+F^)Es-ltq_;RDo6&8(r6hy8(F79T9UC0`l4W@-xQpggB&RQYIO#1?
zNaURypUj}r_`cxqn^pR41E>8?soNmP!~iH_a~1apR~!!k8^~Z<qw(V%m0`GfTu*dG
zAQpD{l$<1ydqk8D=jAk{)dQ~4P6pvU>(dBX;GGR>F=XQKV0XC3GIxh#87GZf3TdLC
zq@<k1-Q*QZo5%)bQY<V6Y*MshvZQ4atzkRLZflw4AOQ-hUk8SY!j&E?Out$9$G834
zhyTa(Uwr6?A3F5VtZ&2C?6zv)y?hPZ2yDO6js+1qLo9J{<OJB%3LG1}r7r9FS099E
z7Djv=3rSSoV#KBXN-vy#msZ?#ph1iUZQz21Lly4HSjEB7<UZ|31BaMu`k4+^*$7l~
z_OaH1$NUw@)wrWYUta!I84fi-ha^-n7FUP0hP{~dBo#Zb>0;267!4Ufr~;0G_?(Q1
zKzS!2Xm80`#UGgM7_SpP6~t36jOa~@>@GvS9tJwzxjWjd-EmL0!f<a0MAWS(R{CY1
zlCvpXrvXzyws^qVHh==#rBcv>ti~bFx5!L7?%#qi6^vUL3@e?W5muT^n<TJcA5L1q
zQ{#BjO68855y-w3SqF0OCAo{$5DS;QPdE4g*)7>vE&+bc<lzRgtr?6Ou9Px&c9?{0
z1e_(E_;3KaTkVxEB*d|S6G}=#xhyqO$Vl8|PXK`hAE<UA#&|3q^g-c63mddn5C&C>
z^OTs{;ZS?wZ@&DlZ@&G(KijoJxyTWD&ZZ70GMERBE__lOQVI;>6@c=67BsKsqzVKz
zV;5o(jv#20scAUO&JaphGpFU-8?-D5ShY8R+42XpVU_}(ha^%JOj3;b=i7#p05MXC
z501`~B1EnsIIQo;Zife_zaXHT@eznA4}pr2CAip<wdk|@<I|?niV@zku<fcpdE-wX
zdg0&h|E8ItOnZT5>NPsZ&MaHSpa@lZnk@sCIgr?dj1->SAarX0C9&H$6<645nUFgq
zSdG?o=}vftQVguTp%3&<;Do+LHieq_sU6RLYVZn52wo1u5_q)+G@U(kWjyr`>phWq
z8y28|r&Qk3u4SZ<O~*ClhAm)0Q^`ZP1>?Y@l-3Fqg0tcxhX6(+&#mXeSRlireK>v?
zK8J%|`TTb}el6I7$Y~G?Qx(ajaM*W7gI=Pu!1jw2s8MbR(_9^t2WEzVwK`+Po+~ME
zB0m%DlPfeR)lWei_)X(DhM!W4y*D`0-443lut4>WVnt#g4qVXn=;po~480ns`uh}G
z7+qDIXi9KFzw?%c@w=;0A)K8nkw%o``b{!vWqlNrMHsu!M;Utv*C&r<7a%0nR8aOm
zWMg|GPKYq4VF%T<vA74(<rx34lla*ommr5^Moyi)JUA_k;yo^^Co5#l$ImxcT))i(
zrhh>)W2NH%n$^y=n_<U)U*t?<O_LY%z3?^I$>kOLf(b1zPwjZW$nbQ*#(w=_Ub;+u
zOk87s-S{<67QIFszhqd>{X>hBLs3M!Fqw1B&qJpE`J>_vK4o<H`9h5T>kiQ!Xb-dW
zY#AF?^D!KvSv};^j!+BQPk-^tfl(k?Uj{R5<Q<=fYdRRf27Mbq0X-3#aldFo5!+l;
zNpOrA_SaeNuj@mF2hv&@!FfqiHc+g$SEc^?Ns*TuC-rgY%(Zo^&yP#-avYY`%b`9G
z4(9e(f~8+EhVAjgz~PSVVU?hq)!-V-Mqhs1to)`?P8W=l0hC4?=2O6*dp6%|ahD?4
zQtrS?55-t?6gE2J5l`lngBWlY8S^+`$sost310MI2gB^)tV%HsGu5o2PZoVnpt?DZ
zwsng75Tp;vOQJ==@<<LNDKQ;c3uxSHk8y|8Lz!xsp+k5qIysJgOibp$35dsQe(Kda
z?>yXyZ{)Rg^~1dvbZ4KiVA%5WblFc{B2|pF#Rjn)s#yz1DB(E!p^85&T#E*4U>^SM
zD93?(5r_*Gt5?Zi0-N9cvhI_34R6l#0g85!12%>p=XG0U97!^@Hjn}-DP6+~^5=w1
z7*lMdGKojwDjOW525UlgdSF8vb|&qn0*i*R_ih@*TZ?)cYWN7)x%HIViaxuk^s+Qa
zJ0-4uJVR?_kU8yP?jsUgMjqtO{zm)dJO~tE0rD<Dk*ysQE2DQ}a}0!0_OA3XlfS@l
z0|tSDdS}$_Zp7i<ht`Dm)bAJ&c|M#xC)pfJ)XRPEy;*|jEnh$O0XPyf)To^o$gAl!
zAm1#c4hJcp10fc}=KJnBk&bJt-%`b2$hBz}Z$2%daupc)v5qdvyG`~K!WyDHbH8)7
zH?J_kr(WiIM{kNN?%DMceio;Y?tP)dj*XovGSj&Zy7!{UGeIjW;&9!EqM_Q~ql0u5
zw%mz~noxQ2a&&OvjD}3AjbTUGjO}Z7`u=RDf0_}NtHnicx8lBlbML9dIM$yF&}|jn
zjoNJ8Mv+>@lirlp$5Q$KB-FuEF&lqL<gV2*k$=X?-ZxZ@+4sFdT(WkxM2%4cUJ@A>
zeh-5oe?OV;l$UriQsoEkx&%#UTA<qT;aaH&L7gt@pEjVNe;Pb_HW(o-G&e!eZN+H9
zYao7?cBo&k4=U@=I+1gSaQO3(#17oV<cx%S*I3lIw$E_=w-c*9J~BfOLDV0ARVe+h
zqH7_z)4X$zw;SskQ}1?={0yKk@Z}SF6lrguEw{Jp$1nCuH2*J8&<sNRm6WudToU2%
zWT1-VNNbKSgkW+6adNQB82*|)T)4T86k*V&DmM|KHK--d6tWJX&6{9g<I{#F1;`t9
zN2}VJX!9)v%i|tMNv;-4{HZ)>?jkM6NgRs+3=je|Wog_EyLF0vkLUq;0rT^E0}eeE
zCw82;t)XDks0mJt4~d?oWU}d?)+sCpjKP%Vb%+e0oc|{)8OmiV0AmU+qxLAAIzhj{
z!IZ#pO$!6lk&93YHO0d36$0?*sIiw@pES<%h`vV$q=H<1g9%7ol?J8-bH~#wV;f$}
z{GGD1NrW7<ZQ?d90fbXEby844`PqicRDhDh##j|BaaEok5@HD2qxmS9`Y9k=bc|X8
zQo#a5EKo~fd^SSEYu0Dk+e-UEW%M6K{-QrWF~XU(7)~mv$SeD$ccxJGQ7@hn^Mlu6
zu#eN8w}4qQD<EHw3}72n90c2Y9O8UjY&~74?Sk4F7PGDWwrHb*^(icF40isn4qs!-
z+-|G8u_m%_?3l{r;`#j_9ExtMVgE7OeZCECt{(zcakf=Hb0#i%dn2^zUX}`x-Cq)^
z9V|rhlhra9J!fU~U!ZM&21E0E#{<<f*J0}XAhwlXd4W=1b$4Zj>|6B;4F~oVq}VcR
zW;?SZTjh-olS7Oep3UrUKe+;1+u=ZYY6B?HwH1?TcVR*Wv#pKoPKy(!j^MpdgDuGl
zNgyL(?LfCzgHN0+@j0q8aU+&<cYQ^=c_wZAi&!YpH-ly0(-;A)ywEXbhH#oC$^Spx
zxQuL$1C1YNgSiFNp;dY&)6)@G&FQvM=ST6g_#P(EmRV8(r~P8-f_!(q3_=l;Ir)ma
zZh~~pP&^2?1XaGapMhrXCs33A01H#<uL8e-5Z8mUS{?)QyJHaS7Yg>ILyb{-8(_N~
zV@~8_M_s$rAWbLewsP3A0R~IR+c2L3EZ{upInEXY&JR6`3moGmj+t;o;240HV|efZ
zPK}0R=)AIT16Cjth*TJ{0nMf`3lX5Im~|gW?Ted==!5T@httS#o@d(u3izq>Xed7|
zd^6Ts^jW+OrpqEL-xiObZ6y~8WPQxRV>>`r-e~>$VIRbS3iuT)`Z=utnHeB@NF+NK
zkMRjCmTj0%0Z_!!$I)0aSR*yh-;(T7u+k4n__j<ZreT@f@Ij;vTMWH9<K@fJ8%CLi
z0pA^Y-xAbVhw&>5#D*SE<J7ZXkh<C?Dd5ncGz#9rk_W&6G--+HVDaFxcMp$qv62WH
zMIP`{oNgy0(hq;nQli>4)W;7daFTG2t*N13!v;hreW=*89Mgo5a8OUJZIkNJcTKjh
zMoSnlk5osak5a8(-6f@&vSl?{mwjnG{WG~z+|R|voq=`@P7Cb}<MJ8|3l_p}0V7@u
z?9TX_FCtDVoBG9gc<cj3>3XtQH8prI2Fk$eq995>M0MO>qdS8HExn1XAT|7!@tefP
z&wqUQ1RIdj7Ec9FD~M~S^at|(GkrhBK78$KJ)7>lIGC!{(4Bn$+3w`%If2k($x`W@
zFzWtZJT`U(M9di!BjoC{RSU<u+nm%6%sI$qvAk`3xr|+NLLh@K?Y0uxf4JMh`ZaGm
zez81`kFc{oY~%)ZTeo1cn>@}1)h`F4mw=$ZJqQu{o1!0f4=%#g%8vuH`!(m|I+V+z
zzH?<vi@*NrNTxp&+AS`SU;3gcXp{V-9|40`o+?rG`}s1yy$^`W4-5~9v3L_$N-Ez-
z7YS!-!22(2LvI?A;JcXqPJW5>$pPDm^D0o2GoJO!I>dZX=_S>d4{SEy3RJ2?ko#Xy
zD?z7?_6%c8|38H|3U6WnYktp&8w*}~$1j6)9eCC7khx^RMZ!MOrUA|m_TOgC@g8Zj
zsTqdv&^eB_Rm3$WVua)HIl#AjH1M@@AT<@yZtK<GRQLem$56J^hYn9@P*#RQv3;1O
z3*Mk<NTY5|WvdK4VIO#L@YzbFz_J*-Is%<pwxLM@1-*0}&U}in5s%&0A$1tG1A#5n
zv3(D@RItI7>CzcASy6Se%n(6v^O41o0?ypkNCDiJz#$SukLQQvfPz(GISic~_O%vy
zx1mXaZM1>z5EsAFQyVIh{zrv6L}M@ub#t-QXxfY6cp%1?roencRl-st*T`Ib;2D8z
z6C&gQ<k^4-N5G@ZcprRlo23oH%z0~rUP{kgB$_K*h-J&*4$H<UQ^*2Qo2IR5g<y@)
zcW$g%JVpW3y_wU%7bCk0zg02Xk?*5(ru~0D8pH{Ughw#j8nfi1#mWJn7N88r!onu>
z;qvUPWH|YTp%?*fhN1-R!{ndDD4I>h+G^~utjrbH=|*`XzN4`S=-e>3RmKcCN~MAQ
zer=dT0fpT!62`Qr1wZ5R{<(yngL$~st_FLEO94!_ZtydmNI_5khobn!rPJ>kl}FCq
z5pMeyHoA6Wr<`u@!eYefmFXrO){MHpH%wTJEFQn44ez4^qF97FW;>X~vOn!=7rH*;
zo5gj04+>5jNCDE}mxtD1*Z`KEr|8uJ6yZ~!0au7euGH#jrvoYI_f<v|e$rLOjNE-V
zg|q{s`FGxcMQqarF_twc`NC}dB4KW+?fD~kwPJ`OhA#|w%bgd5ZtxIKB2n{IEYoNP
z@O#?eDNqi+%V{#UYtHlU#f>V06Al_?;LHabR<P=~8Z+@+d;cFGcM1G*YrA`7vb1>?
z54JiN372annbvhyTe6keHX+%FQne|qF=lYWS{sg}0NSdBGQH96X-VBibk~%wNK_lX
zY(_VT?BE+)@D#<xjt~QmxloWO;Uw=|zt;8?T{)xYbHeN(tf|1d*3p*@hFUNa56&;l
zS|PMA4h1(Gj^VsHoY6)A4{mW@N&CAs=-uB4OW%kUUPr5E&-}0jT*hk%MF@02AI6&9
zWQOIl&zHyo=^l?>P1Occ<phYSl7_Rqw1GV`?kK&iLr(<4<hMoRm9>MN6J>Cn(hO^!
z%#p2^O2$LxYz#PW&350})X_Fcfmz;odh`wCC5xLwV`~?P6*qLc#Xu8oFe3XJ00&1Y
zYAK^oMxuJX5tip&n%8i4ImJCs%Et@NA&}Sureiv{<KTyu0DcA-<d2gsN4B_VdPlv%
zW4hA>pa!BnE5*4t!TpQ9lk)5ai>B6&G*sTl+l&N0=M9PcRpz<qE6oBi0P4^l<CZ-@
zf-3<4)|+i3rNHbu%uA)O{y=|gx;UWN)nE@U;ZT%`D4FtShkC)cjBoJtJ!hkRkH0>a
zH=Z^g?)?oD>GQaD&ds37P5w-M%DUup*c#=x)c#*bXbmPa9~_phT1q@p5BjkE`CWTg
zcut4sXFO%LjWRkv?lN<M5af%itg)v2M%+OC+*m#eeClJENx>L~tUJd_?O#dIlwFnY
zXS(*zFNv`~U8{0UB+>2PD@aoAl$u{No{@jR;Up-|@5ED;AYGg2lUc-|D$#SU!rhS;
zI|Gu_J?i&gClS_{rz$>NB=&L%(zKYz`V2ahTi1gmzwAY+_3uxxTM7e>&eShM-|>_(
zTSX~+DU+9aXK=oJ6ekLtD|)3~XwgHB#Bu+|EbLFM7FSQXmi%yycu_cFbmQnoxj8+@
zsc(lL;%Wr9-*YHn$zdqTCVS?D9chKsP;f9uBQ>;FG?iA5r#=8y3nq#QLQ#3kQTHe|
znF-w7&~pz^WAIWLrLA^Jg@vKJAM}aA9lLP&;l5cvC3c`Hq72UocMW@pZYyaXcB8xy
zpl~tU>a7_sQU`+@g~5lmG!mRrVEs0cHd_}YmP>v6@d^V?9r?_@rlifscbOA!i~(bc
zh%Drzcu*Xg`k)zqPrCjb!Fi#^x%onp6^?X5Ju4!4lQ{nIs#4<}DWMlCKa!K<H#eDr
zDOFpZjWF4;az@6Iha^51gxhq>OfzD}lm`A1-gS;%&qAszn#E-{U>V!?W68-)tK*5g
zz8sz#%$xr_I#HZ?%#7kBVUJ;PdC4s5O_@41*Q1bBd3VM>1pX|_Ol3WoU%?*93>5pa
z9PKJu(<uwc^TIJBl5~3kO$K}fOS8>dQlW@C?J1Q5x+*XuXNe5#XMZCH)V{StWo&im
zD1eV(wv};c)V>WLQu{<4)l;*jqI{sISN49UL-Z<)8VpUZOlc3{jrGvU7&Qj2y&guB
z-LM}GECZ0bcKkxWY?;Zrt<W!xfLy6Ck>eR02!uO5vF)^=eiCHrnS5OBn!XoN6Lees
zV8Q|4f2=WX<$#3Kq}el<TB(h61kw+gKKKp^l3)wSe+UN_lIxS0`F6b8^>PkZ!9(%1
z1R~aV{|x4G`$f(<X#C9kBdD*NDfsf$GM(cdL3xrel%QI?rs{h%A76DN768wHKYrTv
zJ56F@K#!-s0JfhE<D*Dz3j3C4J`Km`xxfb9)-;DZ@S+lb?Bg&9%`{Ty(M)F^;PQwY
zMkT<&M-R~W8Eu$P0hc*_akp?lFXsWZeULB}u}5GxsN9VZ+8yRv+&C<L$buR1xTZQ^
zWTjt21<aOg%@9~pDt;PQ`qL7^lu{0-wzkPbt0FCmHb{}Dh68R!PwU9nlA9B&nG#cU
zgJ>qFJKRwSfK@^Sf;LPi1L+VE<!({1S-qKNty!m)QF>jYBrTf2G75~U__4o9N>Pd+
zsdE@~bTTNJ3CvXTpavTjM6o^^0{tG>akxr&$WidJglf=(n=MG0Po9^0Bvp$=!mwKF
z-I$`Iikb5bsrNEAZFm?#YN;?RP7+Yi;T{DwwIlH&>fQ#B)T%HXo}<C&(E{fCTRJO#
z#vEE*zB<?pcHYKclG?m;nH&4Vsr253uYeHW_;rX?9(bCQ;%ow4k1^k<6J*X{Qc{Je
zmqDv;r{`~lJ&>ePu`3|33HmpHx*S9Tx2Sh`Baf^(vklU|y@V@fw~FbTq3A;ypOs}f
zn^@b{{gh1HfeUbKc&U+_>kTE@f-s+b(8$K`T-qV*9wj&sn)no#+Ey$eC1bbY@R;O7
zn?u>$ivtcP`<>P<3o+YzdDd-x1{}Ernv{_&o?JS#es#adh4@A+60RhNUhB)kd!CBZ
z6qs$!QppUDYv{NQRij%oTnJ7RyX~*XXXS3OpWX94ar(&%jI2A~_SI*wRuoNHM)g{k
zG4Dgiwst?dsQ<nykWCO<cjHQspNq>I<VSBg<1r)Tf$II3w7CvSBK!%KASbJtk}I9&
zX0v4}S?-{$jJQJ;i-beP*aEHu%LQ8B<YGAps?I>hkqBU(7Io&pBo?K-3CB^~0=0{C
zOzX180*k{*P1xVG<+Z#C(s(Y)kLxXla<h*W*Kihb8|F~J(XKQs9@TovAbKngiqR#|
za>QbgpTY<C5rFj$Xj8#^bOgpY9*Zb*0O7(XKXC0+mWJ=_T4sSK$XRvd&*}KUROcCM
z*w4%Z7D$krF^5_Xv~`9ACsfmyH!aLz+BDP6*l1i*OCJy6JTB+r3{GD1m1lx914(=`
zw!!H%)wY>ZfL*>ph@3OnH{9uRkmXFUbQ0vPI@EL!7T#e`P#U3wSkg^FWpmkq0m8G{
zAYdh#gfB24Ves*VfTK%|dyp7#R5%kMp;4(b^<rp!TCgU}4y`e<NYZDE*D?nX!=R%Q
zg6PBGkst4GL6T%$x`sbgc2vTm7?LxSNLI0wLQCc`fINT|d~`6#YwuHvn5_k8dr%zc
z)e?vZpklDJoS1%WECtc7!BDPqCJkWVGKYk>{;fhwW;;&?F8Fc(79>d^mn9eCg0Nd;
zMrKyXO7$_e!&J)tC6Lb=S=w2TWE*`0Y?r~((R6Ho6W*=>L0+Z2e?ckn*fZA(W|)pm
z+3HhYDQ7TFRjxD0c8#1R)A*h?94iGNa`=Bypo~qa_K+(z$fD2oaLKk=BJI~a3Xm+5
z!T-<R`+!$cTz8_U`?jPWjb^4tqZtGqpd<vy7~>0uWbDPbBm~HKLN4~$CK$&TOfdeF
z-SMB0ag3cKA+R9Cmc2MT_H*)GFq<6{>`c6NmN;ZzgYkZ|`S^CndEUfvl5Z6j`(f74
ztFYND@sjNO{i?d}AN}hVdHe0Nu8!2*Ri{o>-9D#Ib)EW)o2wk@C<E*)f<B5E-h5>5
zYQN{H=?cMVlZ@H6^-?wQ%N;gHG}qUmSTJ(R0OsU=4?W!tEdO#0DgXysOJGs06hqKx
zHS(A!rv1tgF6%yee(98f4=G}gU~t)v&e4evcYGshkP{zH1guXd@L7yy7_FZY5LJe;
zjwg)}z1O8)mj_+6ej7@apXgu#=bV*DX_J#=rJFW`<*TL?S6OJP20D@gZN^f2lx_`@
z5gm}r4cu5#Y$!@Bx#6%&4xIvM<mmODy$DQPn~CDnCaG<@wj3QCAdd|$<<z7y;A=ug
z8x=c$Q7ekg<ekVJC@c}AX%ILS35L^JRB#0yz72R#j)cvwywZgd=doXOnt1}7=c%*$
z8SsAzT*CarQty={eZKy4)Qx9bk?h!*_at{{qOleGi;&;dpER+$p&i$Yn~~S4eA%Zl
zL#_YtXMa3*r^pK<u&s7_>W4M&3;72WmGv|Ju?w~M#fDpQ?0z2eGco@#E%OQsckhy&
zP((4L-m}B<!4fe)fo(=zz>g}b_n(JP?6sK5c4Z$Hj^k4+GiPQkGe)@Rjn+j{ddk2;
zwa>^-C~EzG2FK)$yCw~$s#U*)K?lZe{vLX|8(am+<&18C&5fv(U`W-TsDuV1KJw+e
z1`n!U<>Fvm#n*-*9Mv?4^auNH4WAx^6dtHZ_)1joZmJ^LU*#x)%QlaMXCc_%!$8s1
zXC!j?L8SG4SFmI_z1(N}pU&{5q%fJyPvDy^-2V#w5JNp>M^yA_h)(;|Dp_>ALP;%y
zaVzrMz+ac*c5Q-F0Z+wIWQ&ldgXcoDUXkraU`QTDbaRT>krC`>`oSzM)DkR6V)w7|
zGd7a`rlhq>{x}8|zF#PP5k6?4inSot)gsJ+*`tD~{HPJsNuZrfw^<lfEjhG@t(ICF
zF2-zfWXtX>4<o*CZg?3_9)I&aEnaC5;&c{@X>ob|H&q53f5GgOOl^p5f^ic(uZ2It
zIBsx126N`B!}-$WUPR}&xCN`F(F*l0%&vihmu2zGes2}!hbUaW4MtygL)~+8&N1b3
z%=mO1D&~o*qw$habO7g3G#8vy#{!uc2i^vuG$KdQZnowz{Ii)rC%VmNTvcNHSl?lE
z?rRpu@3dF8NVcW8Nu6Mk2QVn(N-=lyIFx^#V#NoNgLDossl^YX4nv2}Mp;36Vc6r_
zyXKsXYPCmUak8R<f0KPE;yc{V(`^6F&##tX_u?Rwh|QMt59}LcDMa^8k1fNEhCFz=
znG7!VwDsfvrB$DvK!xkzud$PN<K1I5dwxax$GH>86_ouaTwu-J7t5C+N00LWct}H%
zygRrSW3-J)j~$)EXt9TC_U!t{^wI5+Y=3o>B+nb2z1dqTg<R3aUYM<yW%K=Dwo+?(
z>GyYSgZ_xt=g$tp{|u8SesfKxPea-H-D_1k&DQ6tm@UCbxMYmC0?@<gh&cFFfy!Pk
z@`Zj^rJp>?mKy-sQkS;?qB#3WG?spDyS1Eu_yb!htP362uKs?ny>aq}DJPZL5#Lau
zGCn?hCU-W2UHZUaq<<O3;l*c3P)9{w{qQy;Zey4x`!C!%?wdalM;XPnmYM(VwSiQh
z3*|(;k7dF#TZ_wO+v;v2rfVU>@Odo9PlF`f{KJ4uDuf13rVr)fW_^2iE0$)Fv7Qdo
zv?E(@++yy2oLg1ijunyE7{-UYNA*lE4~J@*D_IIFAL>vC822YoHcp@l*n(9#pq|aq
zEP8+fT#2j7RwZpif-rhRA`2$NP37Ad!k;&#RS-(W<kUpzfk-|0487ZCI6PVfqlH_;
zbzPkLl<||-AnAHE*bO}y$QY!7pVwE0EgVJ7ppCm4q!}_XXd$!MU_P%E6}c<E0$Yk^
zp?Gk&_a<yWtc+7n5dHF@EP-)gs?DUj-O<PxK$cqXHvUm`Zwgd6SB<jEK`p2EJHQuL
z?G7>Y%sEWQXe;Y`3$!xG^0qFRX6Tj35JE)s5s%X$&aZ3x5lzyrbbv9-%ea<i1i5H3
z>i$+sMKctqsCr?M$Ym4wy?}E977hG@jn||u(kNqwyve;u>z6ph)=jE=V%5(m&(;X!
z@UAvBT#q?=E?AjE!|k?}`Oda<sMNOYjuQ*U{~{VTcH5}vuOnoMdkSQbD7O0FFqp<e
zC{WZ+dxmkbkIbP6U9jPVHgyD!#3dYU<=GnP%udg#bzd1QO}V6rC4l5%<yB);APQQ)
ziS7mjnEEe3n%mL&^z9GVu%2$a)c+064y^nw#7bI=D|~!EKagS+o?<|%3aV)8HREC~
znh|~M<1SM5d6jgij}x7@l-6-1<3pqJQ<$FScY86cTh|3e&By&&uH<NI?f0=O&nLa1
zLvf`NE}#P#TRZ%ID03&#uXJw%^O*j}h1d<`Wwz67t)9w3UeH=xg@A06X;6jdT#r?i
zbI9Q@PG@9nd3(9BbTHetI)tdMhUgIph_k+X%Z|2kf0jfk%?mJx`@~F(eP-0V7cY=N
z{@R_#3U<E<s(WG^q>!7fj%Z+`b|(dgA8TyT7zv_7-p0lcpq_5Q>Kw4@@P*n+DpcIK
z8}Ks?U>}|1VrI94)FC#Z8kp|_LAbg(fx1G@0H<Me&<l~cI@|fn-mo<>Cb^gv`N+?-
z+*__T4rFt$BbjMKuHm%6qxN*h1*Af+8!+P&K#d}xlyGSb!1WQ=;fOG(6FP|#eUWq)
z2jbQNn}r!sx<Z4S*U~EezW8|8)}0)HZ07KoZ;7OkFP@(yGZVPYQRzISBkpM^?^sC(
z)e0Mwei#n7kG9gS0d9oy-$W*<K{dutcE7@6d#2F2TtZv7oC6cs;du;0Ev`n)l`Rik
z`CKl6&!e5xj&m%=VMnNB)gb!3?8PRf)9{S1Of1I~%O%eO1)+wLg4EL-HNm<;i+_2Z
z*(QIIEf{Sz>1!Z?AK0)`?*+e#fb3IlAbBaS8zPuH-({3cFmtieCx>?ImO91ywh;}F
z_3w@_+G_LtOi3WR2nprTRNEY};)%?Xqv(rv@VQw$LZHyh+lBR%wF`0)yWsA=q3VR$
z8rto@Wcm{{f*aLSOev0hJMBxhMVBGQpUj~BM0sTgAY6p6E(Kiwd)T$tVwnB9k4R__
zRwUYYttQb7M(tQ(TU^O=)fj6RF$9aN6f9tWT$j3;$49#ov(s4?W-2sWeFrrWTj0j7
zEyl8?Cw^BfSC9G~lZqJAz!p7W_`o5E2Bi9?tDLAPt||08$ko_f_RGJbk^bEn_U$l6
z8pj}oKZCKuNy2XGsrmO4A|FDGhu_0_|0Q9XbQhr{&}^MQwAXb$U-w~|uneH?Zs{yJ
zA?ohDC2yBNpGAFE1Zf~+@({Rq=$}!LfNyb0oQLQ;m&cO!7*)>aef2<O<r%CrehVfu
zJ+u8-*xE?6j_MS;ER9P->!TLjSxdWIVEL-RY!#F$z<~b9Sm)Zht>AzekwpXSZm2;4
z7#ALLT~+MdED0XT5c(u&_<FWiI5!OvVF9qVDSeVy+z5Gz@V+(grWImCw2+WuZ-&ZB
zSBqfFm2<%44kwn}v(^)g#KP8ju_OqkX9gp-uKpW<QS)B^{iC?%89pMAXamT3IStEM
z9pFni5n|&Al!6V`o5pWG62`;aSk>1z<33R_*>mdw4xC4`HHAY18=FG0Lg!|oC+0$l
z<n92AgmEY~RSw$g;o{tZy4hy#OeJ?{;^c}<Ol>#|+b3zRcNu2Y2jWB)y}>99n99^a
z0`+x6e}%ujBi1JO%wx^5dqo4aGMY(X?U#-W2w{oJ-1Kf7fKD5-!5TS_fy9u=@F-Z1
zfjIzXetMm>qHcST4h1zNDF&-K&FC~LVfQQZl4N~QZvEthUHnWd(nv8Z7jSKB)jW`M
zYHgN`+Q{fn+E{-xsm4FmlUz5ygFHUmjFAplBL`=&QPT}$ICspV`v6MqU=dFiq28OY
zigpnrJ-!U}HH(BNTkSp>KXBGbkZXTraR!sKZJN=Z$Dl*HCDkV1>>|vCyKb0~<oU!l
z{?re!HA7c*TrI(gv@eXmb)E#HU$|3($97U^+)N9~2(7*OHzlrrA&{95@5FcT1<Wx$
zaaPtcx)Cd>AdBf+kKZBkT-AS&^|4nVS`iFN_{6RFgin1{wIO{CgW|yw;<9}KKm6$%
zN5mAR(k0<;x6p53IC|iAfsNT06o2LV1AFUYMS6ae$i)i}Rj^5EpPS1PGX=73@LEhz
z{pWW?`l+iRZS+|fAaMkPZ$atj8gWuT)DsBKPkD$Mb}-<;K@mVv>;DdQ$=CN{F8O!W
zl_18U##%adCQ*$t-U4vo7I1!H514~V!gpSiq~lPbbpiY5*^o81{$en9|Gv0);6#t#
z9fs4431frS&g{c-s$&P?!@z7i=*!Ss9Lk#@AarXH8WI@z3c#{hyi+0Dmp4?OYf_us
z)gw3O&aEdo05b!n+$0JKm*GeV#hIs;fYWFeqhg%NqP^Nb6HXd7L-5Ri6#p6IpTY!N
zo|&d%S!mo$aV2q&PXs;CC<N&!Q(ef?<pV{<wt2hWX&_U490Nmjm?$Avn4ANCCZXwZ
zTPg`>J;->rp_9T5uuN`G!&j0-0En7K8Jfk@CRK@ukgIt@Xm0Efu_|E7n;T%NLwYe~
zx(t9DaLuS?_-^#7d+C03Aq=8%g91O8pmn-FG@z$w!8SNmAM%)sup(BVom9>YjEWd*
zyrLe;vA_+$EW%81DypF*W6Qu085ia1wj@Op82dX#=(+MRmp!vbRv8o~)fsEE`V?w3
zMlCgBWwMaLW}<p6Sy7R``Y=S?K>cT&l1~xs0NO0^6Rg|GV-x`Br~_p^&kENV`f<Yn
zbD%BERq)&Rr2rw<zI#CQCRo%B!nC#kjKXMZBYDYuJ^VJlRwrR56msU)xHmNCh6ZM<
z1iy~XLYwWg^mLTz$*Y2%_;V&s;yuvJFWPWuX*km_d$9=Cs)xx}&cHr)ry{dQd+fMb
z)~Z@nFvEzr5aDb6CG>w#$jiXmQ@L<!3%~(`(bn-`@@LUu@B{Q9&Rz+1C<4qMoxiCs
ziq5}8M$9!M(MvylrmOvu=eGH#(|g|$B{#jlPxNo`&3*F5K+@~+Id&|+A5*4=ElkX>
z!Tb0PBE!G7U^U%ULLM_>QuZ!Ae8E(50e++ZF0(?wY)1a(htUUW=-2`ta$#{)r$o-^
zJaLvS=1HW1{hhOnykUQk-1k|07{75!4C_;!1&ZkP=fLTO&)|Fg9Vpk|{9Yi9zq?ae
z3+N1jKR@*{?5T7`fXQ%BQg;$%?PVpz%9MWsXR|#1s0@7eDUo!%kNb_gZ0#dR;L7)*
z;q`+6`D_8r);O)GTibf)w<CRdAx}my&iOQ`4xNMJN_GZz`!jnPhb^WC9X#&wuE)?g
zk|W3LcG({eR6d$*<4=}H4OqGQ-!F$?(2Pb!90?9U;m3G=VBB}2z|==0)%RD%<v#4n
zmPMI)81aqFirlt-B3%+{@t)ufAE<}nXpX8l%&IpVDDl`ADOSexlTC<nfHt)^C?~w%
zfZx80$@_T+hNBBg2c1^&Bgz35-oTVeClP^hY!<5*1!p0_Zz`Qox$J&CseYAQ7{PTc
zNFs}NO*yVaVrC6mq)EljBQmcR+>Fm2m@f<X5F)vG(_(&$$j+jD>@u@Z*OGub*S>>B
z5hEtj8=wyEh*}SqAv!|4%R}{oqVhu}J!N=2BOP5rsQ)a?R-1FJ3Ww7}aNRn|0byJy
zYUX|hIxMXe8ZAt$&E|E4tKNdhvMh}@1KBH~^ttq!=q*Ri0R^{xClO?^KG+DgCfM1|
zO0<7guy*$}X7eio9I(s))HPf|Tb=R<8Ja>6KA9zfS(BQU5_h8jOc~yrkmc0$cddhq
zOz--(5pz5W>!z3usnK&m^(aWuxgRuGB%p6g{7M4SJ3<>b*oN7wHSGiLQuaX*>=0H^
zLfrBw=B?Iyt+2H;o?c)~DPf$5RP}4lY;_5uWX;PrP*W(6ncPU}0P$vq>+y1j+#=H-
zsLXw)CqY+W0VHwwMA|pv2i$gz*yCU5w~UfJzne`_*rX$(&-H8z^gS<+<OJp++B2^7
zy|~f+{ehVt6Is0H9PT8HNDn2F-n1)t&@kruppV}SIUan?lo$}^hRo5YdLvD*a?>+h
z!1{@FN9f2Bl<DgSqa^-$nY2$_B@tOx09W7oP=6B9I>nKY!QD5W?aY(uUzE@?=6}M6
z@{eYMKu_!%rSL5~4?^VQ*0#=m5VM8rPkvhTi>HMFm()J>wXjUzp*(2+3XP=R+BQkF
zB8v0?mTGS4dh=~O?_mqbf$#{r@Q&}1^yD3}-t|;gjjqodqv1m!gmsD|A;Hq6pYrtA
zW{UpAWs?evCY0|7a((A$>rsry9Y4olhdVTVZk<31SW+8(5hLo9P9Y#me#3iA42}1o
zxkHYHmhP0dt_Q^;bQw5%w_wI+D8U%~g-`{>>tN$Z1CANYOX4%cMNnK5)*C%jijE2w
zV5qEs2;(;dt=mBMV*-pD;0sl=a2L47ttK)l9KkavRC{{;r?j3EN3AWQa#YtoO)d;W
zaSTXk(9$UYjKl2!cU>zeFcGX%+8LCdVN9*Vj}8X9gHek+!RLcIa>4u6QzIGRG@9|)
zb?#~qsKTM6ZC2`dv_Ny`yWwCLX4eDwiiRa-p<vHX@Lo%dLx%>0p+QU*1r`R%(Bkp{
zu}5(6Y64^jaE2=50UEftxuUBaLQYOyA1spSRq8g58qCsYk5Ok$P-(|(x$`brD-XD)
zO#w&Pe0FlcXlu}b$7bSj((`kUV~9JQtM?!j`}n(i-k_Nj%FwuIZg+4WT6nMf!#y$H
zk8JHqavINDKn}zlZIzdd4|AndwYG0Q8ZX0`bf4)>D~S!h(R1Nhl5OO)WQAH3%U;C<
z7<2|r?;5nTeIqId0{0Q6^wFf5hK>7`onchNDeUr4@8rcN(aBiii;myN_<N>A?xESd
z3?}w&jkabi8J|8{!Q#h{iXMGvR&?K0sFIg)Yc=nEoG1G9jnKHKFz03F6^2B~^OzUR
z=Y224QXje_jP5>D^u*;@`Z)A@|M_)`@toQEHLS}Du~M%3kV*Bvto6fG)`K+d!;tXr
zq5OTLCycTm$_hep*@LfiHNbiabWIp13ERrslX(1ZRHuLEEa@}F?`|;KD%(e~FVn(j
z@j0IQNej8Sk0cZcbGk9(V&P*LTm9-e5}|9t8e%Dh2Ce~a-hKFOLBGEICHUGtfsgW8
znS>C!9;lln{N}g0Ru-2j$LvUkn%fCHZ3R0J4L<=>X$zF2t#T_T3BLqi%cmn#Mq7_z
zwAIKERHv~M{Yu|hW^~fHOxbvOa9(h@S^h=Mx&6pFC<=cZYH-~*7}jg$le2kP!SkK?
zb+xOqiA?u&wvV_))Hu#O+k%V(n0AN;h~f60v#}Pl1zioUvq9_tzLp=Prh>!y$5GK7
zVj?_;6T%1B6$)en9RW68K!~}Q5pb0S*1E2p&0)DF0E;>4F6Sn$dmW+Y{1e~`2E#RS
z$F~--V;mE($KNY+*mKE_L!OiE{FOR7{R5xuB%~FGw1n$S^K#yD*mDjn6?`V0K*x%$
zWzd3X49%^GNyN+cvNo0l6KyXBZUH_|fh8NpV!OP$T%9`)LSzX9sbQGN9B3Rn@vPu-
zs<ayp^4{RW#Bk%zrLvqyW{3(vMcq~e$Rr%-&?trnLBhhP%wi6|*|<27gvc(j66he3
znG<#BF24n)2Hy7g(e6RlrYYjcG)+yzvDrvN$al;tqgdW3pBnBs+&+NPs!uQg*45EB
zr^H0a5Cf&-ib%Z!s2~tr49GTIL?bOQIMWE^H>W8h*<Pf4kqHohf-;blDItuvxuH*9
zE8}Q`*b3G`oCZZI1jVvR5+0ZRqCKg|#WKT4DdTe8+Y&CV7)<L%aaj~N`fPT9?xpzN
zHZey83uyvuo3&F*$b#AKM>@x)9%>Kfd7tkmk)|PL9`2JJS%77gu?6G+Yc-`K;;j&R
z+G<#e(&^#ySb2bDK!?;iFv{T4*^+n*N^u|r&kZD_xgbi#a((-x3=s|WtyvL^$&KgO
zmBExWv5E_|^#;I_meElf4c*L%Ma$yqEI~wcB?JvJ<ZLKRGK<Ph0=9MvV4zN61gHa1
zcS}kqxNN}YdVm1z>}wGaA%HuPCRi5d$U#HGeUj*Lj0Gq>2_~!sb#@`6hAjeQiwO}G
z>9zNuyB`ZZf&~|4ShfYJOm9O#KLXxRl+Gp(w|qZe|1E&W4HIH~g|=%UgqT@>!qN3w
zQ%53?=TVTHvS2*y5wY@l9Y|9;;wo+y|2#OiS|<h<#?iv)vv3pve%}bFISQ1vXi-`m
znC!Xr$T;AqkQ$kSHiWhWTOx{-%~yj<5ergkK_~}VJyx!T{NV6*j|+yXNgYK;8)AK}
zz=R04Ole{+Hf9SPWq~EcgE5)I&4<n0-Tv4Gmj3)%VK5tpf!zxZb%<zH?$pDD&n1z*
z5@%2?4qB1d%yg0+Q3=0w2_$<kc}&g#K@L`4iOO>{Fk&x5aX16TftE@geZ;wZbJA6x
z7Sow~o@Jxm+9tvHt}ODNF+WPw4C!LW%umboF#2%qvlR*6_$H|)#mtCg_H+{;#T-<9
z-`+4i|FXD_NC$DfJH)N}iCNJXK4u2K_b(vYUD!B;GGlei!Iz|Q6C^r=g_H45Z^Is2
z*MxH0HYZ&YtPf|QzOF4^KB?jUX7Q`v^O6XYreOGdQdHNE-!-A`Y{q-fkHp}W8(hC;
zi{D+%$R}j{1mtLM31!=Fy5^1@e-cd?2+;iDL3B{`^+xgEfceSu5dNj80q`&Kj&CJ$
z^7SIK+}!r*5p3wbgoe}IF04epuiAt0!yg)%AT33SWDS2ZvX%HvR_x-I)k?1Lkc(Q1
z({c$>TFLrbop;TfiEiRYvKIue6no*xAc8Y-LqSZ%1q?{^()u~z|D{0X+rLz+sPZ4f
zo`?OPga$7$15^|^bj1y@(Yro;4kun&Y-rmCO~Xd?89jnD)3(4ac2ZN!gi^4W_!7Li
z1S`UR2=TfW;V>6gS;Y6Hg8>y8jeNha(12;y?6qksS%V}Xj<%sHKFnB60*0&)c4aWq
zRFmuP%HVFqC|=rq_rz4m8B@pv+Zc8tG>kUE2)jSk7D)pG6d;swNXxq&BCX?*_5c2g
zJdSL~9UeE+le^Y=;`afv?X;E^1Z@Nei?n2Y&V)8M#OHzabumWW{6li500K;EsFQ}O
zXD@6{5%p3^5ul;QyAcSxwLa70H2Nic?^Gz9Z;DSZax=K=UCX3|G*$vi({w81Q)mx2
z!Q?KKu@XN$r{4TeFqG{MXcu~WS|V8I#Ytq@$utQ^yFBud7(*nOJlenvV*L4uq<BcE
zxak83`Z64_T^lkTh&mb|%E0QYI%=2{Znosw#=zkHp$^@&J$zXHEWYXN5`sM@KWprr
zOOs<g%J$2p6Ux-8nCeCdcNy8cv|}pPz6l##d^tvR3<T%kT4?ZH*bBUIUM%*x83~S~
zu?4dgg`@=3p{{aXf*xoTtL5~lYtrSouJw~cFa4VZwa2$7a`hSDO&O@XJ(Qy#!+{*>
zxf1tY78nS}9^EbmQj<@8ERd7;M-tzAE_Sp0LJ(Cx1VOl&_H*ZnJn(gcJwf^tIr!e#
z-u%d9BEO5+3&q(E$t%wfCHW7b%#b)MewJ=#JEUhtisu%fI>ZFc2kw0&l1tvyBk|dv
zkh&>iOEM@4%vPCxm)QF2afAlv`vDAZEG4J^p>bzL*8l70WZ^gdc&{G)D!P)K6s|cV
zk>d~wvyJ9ng-9@4$M42=4~$$0!FKF2{vIp!dn%mWLYOwZGusnyw1K5(3k16~qftY%
z^-bVYeUC(ibubxvQ^kh0UjY}dmnX)xuY-|?(tjmE5BfDE+8LR~A!Kl5KKlS0)Y&Pi
zPn;6O^&95;VYb%f%2~N@irDo*!`V-nSbqV7LVt)68xO3OJuK>0n<?i-D5G#D!91ER
z*l0)WwRy-oPnfL{%vKXlgD8Z=Tm?&wA;3RnsGUFrCq?nce-B5a2Ilm`i+?vADigDX
zw=5Vm%(kO>=jz@F4}LgImJpm<kkw=u5{;Asu_ao<v(}=Y!LhYJ(m2JYF8Cu~GXTT0
zFLVrRMxCP0Pzp`J>>9Ry9k^hYg+f3QmWB~}Fg&eoD=#QQZtv2<RJwwo2XAR$vSwTl
ziifr|H2q{NV?>k<md;JU-2qN$=vzvOoo)tIAsF=yoU_O3f}A}#wa?sZJk*ty35(u{
z(CzHiMu(ZDPQXJ!uZ7^Zz<3rw*#rw=(06DuMOd3P#xjy8!(GuD%B@uw$?m{v#6V1=
z#@#{*WO{=RNHwuAVNKpdQes&?c&!hHv*Pl6myseihj927Ti`g54#<GKA5&9KZVO@!
zf;!cAU9i|?)?O3u<<0@ox4=#FnohCw_V&to$17oD<kJx7U3Vtvevgb#^FL!@#|;p+
zo<FYIhvl?YED|}4(N>r^C13#wn%)NG*J>)kV_yZy?!ipb^n$`-St6Ssf07$<H0Jo<
znDDW~Fd3e`-W0!40-AG9;mWBVO@Hk-l7Xp@&NG(fjWuBH4jbyJd!uL$yZelM9p&Uh
znAk*i58QQ0V9YUy;2jr;{M)Y!_eKrn{jSBu=<5JgzW0EYsv>pLWx8qUe&Y>B7XGv%
zX`NdIZ2?DHXNNAu8LN+sXbfxA7V@M&&~Xr&qi>YiI#$e?)3AOGV0a@_-7xHb*(HYC
zz#Kk~-Cn+WuakmxQfGheYz<Q<INHk9deP}+R23C{a^o3eGVm6GU4_ZWEI|N+D?ql>
z2mi`g3(ppS14jd!G=3hA8^EBO{I_s@#>6liG1?l*TVtcBh|fy;Oh=7ahm?AL1Pwld
z`J`q%c)b6JYt#5-t$W-6ty-e%7F+|B5~T?h_u!Y&g{&wLY8PB8xG5c!aDokIwD1c;
z>h6FOs5W8PXrkEdWvWvA(i(1;XyzT#pfCbC73F~yA~YszNLj&GF4TQMEP#dq{zeBu
zNl7%WU|htwxrz)a0?JJ-bU&+tTl94=;TB@c<;4*s;LHHOf$PF{8N*7oa5gYBhPH(U
ztERwY!$=gB!mO-AZXp*rp~j^E{9GeAJU9dMG0YhU4db9D&qCIIFlj+O0JAk_9y#PL
zW}D->{z;x&5pyH%uSQd-Ud)loDEJrK6B#9k-U&>J7Ko;}LL>)%C%6tn3ak$Rb>28p
z!eT;91fLxVK!{DD<~vLzlC1)k@}F^r?<%2+Ji=A*U5oM`BxOZhf(Moj6OHGoixie^
zi(}}f`W!+@(NHQ4GCIMvfXl%&Fd+nM4|~5swqi`7qFL<S73dTqVaWjQ%q5Qm9d<C5
zJ-hx9qzA!+TjXw8><`lPB|<T*5A$|<U+wKd*mHqR(I`TMORb<Yxdpo{wDUsv|G+#h
z-<`yoM-iYr*x+~0#rVR5DtaU2gVEMVZ%6H#izXvm@!(d5wx?#~;eb+I0T`{v;Oz=@
zS0WO*aVIL&51@bH`(YCAd&6w50PC>>lM_yp>DoUFqNA5$i-F#M9T|{YT!y7$0i&(@
z8_}p7ybS$H=l1w{Yc635r26e3l=q<pePU?@W)-9!o>@{H*MCIJ@R!&E0A#|obR*k%
z;V!?)4E<dWO0%^wfG(Q)Hv^f+B;i#xp@T~XzQ;Z;w;p@Hag%b-yK<k4H3|!q>N5V!
zmHkr30L#<|PQ$dAe|n1OU!OAQ6Q<N*Lz#JuwhrBV4qO;*ot*jYjttiJT>IKMjuB&e
z!keuIq`WM$P0*#G)9`EoiajO?OZ^&b0P#M2@zRQ>wumhshkAbs`+?Y>kuTHqH1(gH
zaE0L(A2Zd@Nu#H>PqsbLAC5O}0QPVF*Sndri80#BBb9>S2-;B#ePQu3$X>L=9zye~
zcKV=T*||%ry=s{P##I*0T)NjmBLqzH<E1u2KZ9?wuEP<9O^R({VuOel(XIP;5m31T
ztk@~bG{JPv=^hiHTLNGSP+S>k0*B_lwVxm{=#Pq!7O6YTRttm!lRdlsfnEc2yiJ>j
zu(EC9;!bX@#T<*qi;>Tx`8pl3QHu>%GN~z|q-@*7JsMA7sU)Op`Q@8vrA4t~P3vw+
zF~;kZl!7e-kSL2t6^SaY7TA_^%S8^jLT?-|th+-brGR#+2QFC6_eiWY<1RZDC&Po(
z1IF^a5le4NlYQWtcb15gC=__c_ZwC%s9YdyOAS`~wtyT^miw$b*MdI)u&fk#YLHI5
zcIb*YR#%`r!U<z}Sjk*<B#7{%V=;cktXFndn4rF_ptqnpjT)`dFSFRv9ov2O4<@B}
z0^J&t{{tLcGHwQw#Xh9EBIe<<%nBS3ubi<S4f{rpWOD}>{k%mVu-2U_UHgkEF1AG8
z$MIX=6VNo~x&TQQqJU>>lq?;LwrSxyup#*Z=9<N~!_a@SB4O#$K6zOZae3n`n4`T9
zS%as=MUJ~_eC~rk<+j(NTKOZ$TuqA!q>ff*V5!D0psNYN@?06Qg0A-5=}7&1*fC-f
z^1BO%s{`yASH;p>#p=kXqEek?jI`Nd4rZ$>;|6UVK}A*!WF{BE@@a7ekNd&A>VHFY
z{JXhO_5sZA&t<Hja+$bt!#cq&sl{m<GRibcX1gGNcfOV3X@e-RalX#}XBm3%m55$J
zrf!gTu|j0GLp44cm{MGAaf&8r+Tva!i`mqMk9ci&IwVh_jogZ}!bNMj^R$f>B+C%Y
zR=EXq8j6O|Al7%dA3lRaIZ#XB(9m9K_z~P?F}v8?{3w-_vHvRCHjXKK^SwyHe{7n@
zIS?&i1_qbSgv}<ng?|HJ138FKsHM91GMVO&#yGrd7bviH11WB1QVP;GvNv?xDfPDG
z={)1sy`dpt>daIhnYz^uN>57+Y<z>9$c=#oIVCF5K~X~oN()jmT!6_Rk2!B!U}-Mk
zb69P%!tt!>Tg9Q^E9EhQ%ixj=rI!!E=r#luuA?r-(eZ|p)KMHZ0t#aEaN_QU<>C?J
zKIHJH2KpPo0l=@f&e7GkQ1SZIAwC_n<eOtwdA7992O5s;dC<|^<z?RVEpwz0z>5H9
zr(#szv`NqHV=(glY#4q^Tgg_Ktp~BBDuXk!LZACrdm3mB&JJ^RopDR5KI}v^D5u6l
z_S1@H3pk7bR<sUQNi^jwrz2T-sfR(MSGi%qb0j~$5XpPIie9=q3FTI=x;?jInPk_4
z5xI7U#M2O~B{Ra;@?HQ?)$sBCmR-Rzm-dA+_W{PRlN@mS6q==OyPotDt{P|<fo4&z
z?mJ2~2S((^p9SWHOy^2T0#OZ@XjK1pBGM3_?z_I~l1%sAW#kR_v4)m<dNBr%yBrkt
zl^*L2ekW&kKx?!V+=$W6_;$DK0zy7hC>X;lvu7>#Mludd;VUjz)w|9;V$x6k8nz7Q
z+ExYyyp@4Fw(0P2-AMW@=3?~LTs(})qt#8b^^JRd;VhHVCZ@UcEoizNVnYZ0H@K3p
z%^F?*y{i=svC$GG)Np56WU`C16cqNOu9w6OeYzcsM5^o2tPD$0hG@3RL+2rD*gAwC
z@W8o2Ba7&%aEPrN<zm~|FxBQRc7nex@H~d!^-VN=ErNDe7L(a;7;K_GPLef}Tw<>7
z4GXf}a9%&A5jfM+^0!yOkf<z|IV2D%VmUA}$ERa%BK_8}HqvzyJ54?Yvvpk(pZK!-
z6mtntzciyZA~C@AV<4(JnCb7bNL}YOf~H3RRw-psy0M|4R7-BrKx%TBhz#%%HMx7W
z=YR(G#?=DW#ZjL4nFcw=6Q+YyQRmlaG;0UCOFh$g?`9w0OX1<fgJK|&Cp2?a?yTfg
zwJjb?NUhDk(wSADD+AWXD7I^35d?+dG;<4w1NLa~=hy%pi^ie4`ep){tqvdu+uPi2
zvWO`#Tcu~on4ZIZwnr~>`r6svO8%8uFOdctHybirnVP*Bw;y3atZ}2QL^;6uDG=)(
zIofk<XFew&59_+;@EDX6qphy;rP{{fYnN-?8cc!NO6%0lCs33rXY9hH!JKZy$1)yh
z)O>5W&ubF(S0Y>nm%jX$4a`;y^1{PNr6BpO!6~`;KLq$>;DdVCSEntaO+wnTvkJ-n
z-k{8Xu&jkvD#IU3qK5;O`wsQU5bVb~XY0B_)KahFtW!+HcRTk!{>v_od1?aHF*kmO
z*FI74<8n^M45vh$03ButUC~dYI2dA)b2<3XZzRdUZ4%TUK}mqMEa)LNpXiC@tk)Qr
zt#{%~NUVU~f|tsn-RK+ObTRIYRN8C>;gGAbmk_hQtL8ZQK8R;NU$XJk`pi8NO0u+J
z%{tI)d-YMI{4lm8&^@EfLo1j!$*JXw^fh?ff{X)HFkVij3b|r2TbD#l#qjE;^vC0w
z?iHv_vz=C$TRVZmQ_r(?)jAMV{{h!PE3Nj3v8lnc28@B6V76-6mo*uwM)GbiV+t9c
z)lr{<HzwCijSZ%B&Cs<1Mv;fYWQDQ)I(e^5yC2_c74$LAfvxVI^Iw3q;&%z&h{c<#
z;p;*ukZeiF^~8}^rPrn7M_aQLxYg_ms5dcK+q%KgRv*>iaR9r=>u$K*7@fnTSQ?nE
zP*zKdu7`Oj9R@`_;N(Wl-Gxt7#Dvt{X*YV%rZjzcj$i&vqv2Mh<$-JZm4oOkf385X
z@^vtdqG^1wwCYh^eNQ;r8ewf~UDB7Ks5d2Cz!jRU^1>K;94<r8`+GC~p4u-Kty98|
zRVN9f0?nXtp4qtBda-#t4)j?YkL%~H2I2jAYT7u0<lOAXmImj6-S_NC#F?!hP+BS)
zJm4m1mf(XkTmN3dbYEYT-h7LTaZsR251h&6H<+sS$TePj48tf*r^OK*2ABNK`J5!2
zO^-qSUk>`wYEKp`*uwyA=mFy*P2q0d_&H?xd!yl8a9^{wD3|0Wq*BZ=IJCDBK6svv
z8opmsndn&$ve8!eNp<!kh`GCxHtpHtkTJzY87nT-34kUh?Zc^om?Uh7Et_rQw|B`7
z4Dw>3Gq$eiccZOg{n?&gdEaz0^zFxNuyp_qs@yn?dobE6jjKI-$>K5)b6INK>}bU7
z76-SWm6}#yYMcS@(~*<oTFEU2$a14*Yy5*VM`HOn#{C|~cUgULP#RQbzl|2}25M=o
z47&&a8@}g2`NovN7#(H7g3wi-*>_dOfj~c`;Z4GdTuzGruL0veNRs*D8|p?|4a!n5
zfNW7r=e9;$!3F}pL<SF~aO$|q0jTFRBQ@>_N$<($`~^@|mn2M|Rbf~r(1xC0HEcbk
z4Kzqbu)j!bSbF?-G{h_T+8w#Fe0Dvkn{=Ysci*wdiWakE0W7qf0>O$n!TNB-aVi@x
zxB#zB#2}#AZsJI39he})P$Dz9__VkR0ogJqrf%GLjfxjxyr3A6gFD0zJLx4|nA#>M
zh`>|BcMNP^_~}~@-izZB5N=6Bm01uRa|Ga2mucvzr3V~#vQ~P?enUr7)-*#LCV-=y
zBwV%-U~jxzE<&7z;Bv$jITeYXKw`ER$cxnBy8gCbzKt&O6sK_7J~`mEu7D{R7B~Qs
zloG-8Lpkn+DBINq1kHfM2-FI0`*AJe0x7n%Bj$X_eUSrrY;7^MVnDXjGKJ}BjQ|I5
z??76&x=7pQ9Gn<X4bo7zxnfqFR2NZDy~+WE@xKF*ZE?=NTK?bh^Zx&qCwP@w{HQ?)
zcHzbTIDN4ZHx{o-^1R-*s0-+CR`D*NT#e3nn-qHaF;w#6Uht|x9<hEb1oD=<eW10(
z9$`8iFY8Q<zG0~|02|YS(%@=J!jWbejs+};W$@~IhcKiKnC&c<`V7lUk@|EXy%t|~
zMP3i$hnpT3fSgLbLtDC=&G{a@5Ji*026kOAkO+pZU1KM)S^UTeFY~OeGYKiG__!((
zFd2Ed$4$sE;AYYgDI)t%GJXlF8BPOm1Fmpyf#U!<k&2~im4|UE1qM#s*Z_rywk-wi
zK`}$H<;$_{&!FD!E9;KzICa|_I@ZUs?unYm)zG>nR}njNUM3CGzY)1&$y$)!fzt5n
zVC^4{I{uoS?FHkI=lL3U{qQu}#xrY#u8FP%W~drqpRT>ZF+JwL8P#C)5O*Y&LscX4
z$@br{W;&ZZ0R2Okhygc5F4+~jy<tne@%gufzEgd2NM+$EucmjOVcj>@GKmMy<hPff
zJ^)#5=xAbgJ`2ne6dvMmkr-MC=O3ys+M^ixyXPY|PM+K26!SALm*{A{5~N@2#p&wJ
zPeNg0o0@<lagN#Fd^0vC!-z^L*!TOCO0W=*yc<&auau43=G1Uzsey0&F|MbB!{WmH
z{>(PXG4ePp+2ng|QU^sL%+0-467x`BV0xhI18f=~g)jVMEc=ZS^MSpge1@&SEs$DI
zR%;y&(DEodqGHd`Dkdsw_{esQ#l6N-t^qf0X}rQ|5G<uVEG!-v+63!db!e8nvWYC`
z7{?%MgsB{;RR-gR{(^PU9*B^AY;~3reX?9io1Kai#i&AnUWEcV#d6;DZ-&zI5z)Ku
zt6J=xi1U-zkJk(>OV^A5M-><1G3szUj=RMbV3M<lq0?&qo8akcFsQ{cJ1=#tp|}dc
zl6|BEhcVv|cjzqVRah~&1F#_3ZD;F!`8~@?q|WAS#o9ce+*7d&bc7v+U3o$y=>gcT
zNGC9c+si~68>Ca}1wgl{p`8iJH_cRc{g*ZjX4Oh++tws9@H_AWxw&t}vkJ^C6W9<$
zphhIcO~cej)od8ZqE@#gpe}bcB%`iu8#04na7Cqg%}NkvYqH>_DtRhEdsu<U1N>7v
zy(N84XaRmC>Vi361TDLjM(0sS$IQ}{Olh-{>Hj?mjd`@ihV!u7%XGQ7b+cRU5W&vv
z0nOHCVK|b<$KmH4;6>0xU21p$TGLz7aSMLm@k(#?<bO<tdJh_x=5cFzkWMIvl97_h
zY<9Atuzix4+wG;)E8`H3%xuMOKgoC1eb68z-SGm4ZvosdhJsaks6^=XXvcgMYV~A~
z-?L(w#7Ve1#F!tMK7!Wzb7v+nkFd!<=stWJ4)U&5#F?$(>JhsPtL6=##!hnIlbYhq
z4VKN7WAW4Hfcj}LmGcj$zen!MY>JW7W-0kT0{Vfq3<9&QQ(mMVdknf1Hf*-qA6^p3
z#orF1@!vYnM4!3cFzwXrOXR_47Nq{RN{_sw-0x?^%?nmcjV1}~M;7y|-Lkn7uiJn8
zpUTPb{Z<0ZKa}*+2^VKEfFQl$tKorDX*#u_$!=daD+kXvYPQ-X%r*?33#a9oUr}Q@
zyAkj;EVpETwD#j2svg(nceigLcwjR=7*}5wG6kYxy}FySqJtMe-QCO0kEl4r>Nj@Q
z<9}n27_746ge4Ca57ZP#S-WFR7#HXfwFTpj1=ceH514-?Ae+r*oCNQr*$Tk;7?|o4
zB%9Yusg9D6RIH1)p<CGNix8tG6O78tRSXhz!1227hC4hbIAgB`9iA3?xeIy<{(Tl-
z&qgZ43N@i|VNFhl@JwrSOvked-wYDajR?V_F!-P6C&3-(PXI6xk4L?ql`$94l{Xw$
ztax$H8V;H^aFqtgO~k-#HAr9^#7ik!BG-nrEvR2m6iPPGvS^BDO1J;XbP-a1SkY?<
z`5G+fBC6XV(DP)xlS`#o^8P!)PMEFoXHXN&^K`)0(k-*jnP9a>-MLoWTzQbULO6>X
z%s8m@7?)h4m#E4^KIx^YNoz;Ya=R1@=8{R{NqktB-iJbrwh9=*y>A5DYLoyAt%z^K
zXLJ#)oITybPNAltQauxMlRn^8_NMUv%)fdFf#{iuRH@MmxUipTV9e54Uh&FiE1!E@
z&asFce*OATj{nH=N6TA>B|cJ{#rjJuRKM%gzyR0nP<NxP&qGq+L<08nxju|T7ITk6
zPBdH5H;aQ-Tm;3P-&bScsAij#x@wtS{)Q5Db*`lYJGAJ=%+_%vMWgusaE8`$q62TC
zP(`2Y6?x*uKyL1<Oc|QdTYx!TJ%J5Sec|J{0ni;P@_w7e$m~b>AU`p<G)$q&?Ldvx
z7UD&jtuOIL@pc)io@zudVQx6@JHiV3TB3UHVA@MFy6ZvN*sx#9+mS5&PN|9+QzwZk
zZkDmIIA%Ghlkv*>)u~u6V&^f-qpsms7)^@mU;^P$HA{!Ibn*vOCVhQDTsMP?;p^ud
zS}B{=m;=Uwdj<maMIa552)<6>Nh%=JPHfXxXJEy8ze}(gw3Z`s^*Fmvu(Vd@@T<)v
zz6U6WgJ=uKD4=%D?AA(ilj38{AIX>j-r5bkWvor&$1&-ev2jt(%2KkhQcD?>mmhZV
z*_N-FRDlC)AKAyj(ihozmm7r~;NyyYzeC#tPizYk>5^d2>IQ1mS@NqG0%?F~9<AT8
zoOlRQypJ9vrhFQV%v?yv>R^Djs|T%#b@H4=tUBxc8RVF#Beqt0WD+IHRUQ-W?gF~>
z7H^9MW@{2GV$Rp}HA9b=602eJ>iyfUO%!J>gL9Gm{RG9?I#euuJv=X&v&5|g<4`;i
zZjpoGWx<f}iajV(A*zMB8Ei5TxZiuYt~HwkSL0|9NOWWaNtVs}$BQogz(|}rvvmo&
z_1GEyu)k98K(lr7*~|SFb-Vu_(Gks=t#~?nb`o3oQ*RU(B#-tg9mLGjfdRmPlZ08P
zy23$ZA&l3M`oG;3)cTRo@Ry81?C}o`1ajncSikYTt402(y5U-&FxMYDf^fIMY^}A}
zf0?Uai{As2gw>g?m<!w!|Cx*MN!}qqYv{<#R<&@ugW#Bn6Cg3N{cYIA64r8q9!k9o
zghQ8MQ1wTb$EFfb>Z#ThrsIgI4?bf!+8PnV8l=miA+^1ZsbiiIWhM#l2Pq~A55jEK
zu+B-sFHeSnLyc&eij!Z_Hm4`g04=QL@~|HbZ}U^4JcKE>ke%@Y<j*%Uq!?|*kR4!4
ztmrNTA1s+cKvBoE>LLiiTI{?HVnQ@V`@iPg?xy53z`Fa|H-jLQgwo(>6KlM3pO0MX
zHj50L8z}7ANP1b^&G{J5UyH(+Ky_9uR`Ae@fk@H_V_;L5<K~5$ckj3q`~jeO;wzqY
zET?^U#jL;=A*!ggt-z3R!p)^<6~Cv<4=+l7vxFz;WD@mn6Kpd)Mxh)`Io)==oXlbj
z$mJ?HDGc6#D9yPJo^MPs8G8lrmje1R$-9cDrN=`BlM&e$UAGn=gJ!OIa2Gy93IGhV
zAzC^Kc+x1zgy=*&p*lH2rk<-N^R|&_n|n1UB~<_roa`LI&5)2j57yw<bN3<QbS6i4
z>(e(RFGb~bGzf>MuNQlHE!0A87*I_732rIRLSiTXk_ud6e+e^5hha-LIAg2>Hq<ui
zh}rZQjsn^3kv#hGCeAsQZpNd5A25i1uKHwWU^n`>C?6wTL)?Dy{`+?g#`pex<kYv2
z83TVj=dDvWs0up;EWhXTyR5|5;FJ5v9bRdnKcct>B5X`+;OI1DiE-tj)K^hKJZw>z
zj^Z26ik7KEnDJZZjm+O<Bt8D|<mWDWOWCgoVsB!2;MM3r{~oyYN2j2V;9+YD-<1^6
zzYN*cFYfHfOe*O&&yA9YFB^3NY>LZ*N*>52g1b-g1Tnc>l%D0fP237Fz(ivrH$RC4
z0(i1)^$Ymn?;XWBz>cdT_F9!nZAJ2%3{mR|cevTQ(|!GNVrTHu!uMm-<-`Sv<0|(e
zZNfCyQk~cIwmGJ5rX2oZfNY~UH8yzOm5Ekj4@CV^eP__mF&&nce|T1{w11pk4N+Ib
zA2VWXsTUbSpC2hLx+0np0=aS(j%KKq3T<mf*qDQLt{jh%Wh*VB0*X__+>4x)u2p^n
z(Om^~zHJ}|x@W+zc(%;jE5DNSq-?iN+0irvQ=<chJ(CZ1AX}bV%UR^I89|ska=*w;
z*xN~yUhCw&EI6a;t_Rs_vW{7aMoPUrDmp}QIuo)cX2q8SXV$NP&;T_<wDR^M!R<63
z4I;;mER;Xt4H%@bKK1rr^CENl@sBoG!5AAL<Oj1__I;dIkeCd%bTlz-F5(@K@zeic
zb~l^o9a4oXtt(q0-h;nl%;(w7_gH!`+DcG&mm?_iMW7_OMXnC3dlqmKSqGD8^*Z@2
z6XK(YvWTi)mRuoX3L6Dw%6k$0bFgRHp#hs%x22Hn8&K^OtblKixOv^7Jb0eOjoO57
zXkcC_3;g;(IbtrbwXh!pp4*oTHo&2fpH1D`R_lbz0L7I?I0Doxp{>M`IAUBjh7Lp$
zYFi;7vFPZJRMKl8T9%qDTfO#zDfz=20yN)xV{_N_c$F>(3+_NJ+ji4z{pL@~B!;%j
z0SVcM;nuchQc1tr7s<_+Y)k47>|O{kTh~>NmI;3B(->QYK$GzgPPi6yQ!dKjx%Wg)
z&UCK}SN^g}{o1`rdtsRW0{Xf3n{9H_b$$2CXSSPlQ|N}k3oKZTMWz84nNIi3`XeFB
zyg3%Z_M;-k=eXT$J&SXW!E!SwAp*3S(&5v+Gq7)6O*Kzo^$)dnU7&I<S!{{-3r<aK
zP8@$ZnQ}+UO>&~+!QrVqpv#{#`TJWVCU+M-4b^MHP#C<RuweEioQ9JNiOMTU5sOa0
zUSa^&x<`J?ecUXo7%&<aV+m_#ogHEmaApgzC~FaZ*A|R{1wmj99t}#0j$*JF10xlf
z9I*>laRoG6txOv{#+x#wI3tT&2DRML_Oxy8b)6Q;M#!wA2!vQck6(hHk#hF%kkjRL
zlj(xMHaim|FJ%FrLhIPqsW^;o!cMMtB&i*~je1g65n;BJrx`g`gJjW>QmLa@;^fZ`
zp*P98%TbYV@iZAeh6au)|K<?uJs?;0yS_FfHqZoHfM^l6CZHX=3RG9Yt%6F>qwmM*
zvp_{zRD<5F2Ov#X)a)wJx(?;c)<54q6EAYy^p>!k#@atY{{=={jqY_*pETp!wDibq
zc>FZ?B{dmR@=yt*rBR2ZT6H>5ofpH*sj#SShx`E6-Epg3Wkp{#3u%vuZSWAD?gpdy
zp2BRE<BiI!-g(;KFjuCQfpFlDVVy2wV(#O66AHvI7TDcC{B;DlbLcbOnP&*37#Te0
zGP6~QX+~PDZH(Ym;NXRUwGEU!{JW7`(tP2l$hW6ru_#RT&2L*JT9=`EB@D2oZ*cfz
zf2`F$DAQ%lrp~&oNO!(RlE%?fWN2iUBq$6Da!p|>J^iXt8N*a^%Gim^;z=nmVU_Ft
zF?tQ!FfO8#vA;2BZ3xcUA&L1XAoxoZ#_Y4MhvqN@`z1ZTDBC1>$xBy$?bl9lvxW>w
zJ+Cj12DXm1qfx0>UA%rSklP@;g*zavQ!(2Fun18eKVNPLj;xXfo5?EjrioR;h$>SD
z_tm#)q!-SF^5tH`NDiLGXP`P_P+qJAPrfckck>f9St2LF0qT?Tznoa1E3hGFm$8nm
zC9jp^9U%}Y(sp1&^dP=Cp#Dp$xZyX>(UZXdJu|ohgWD$^9UR>ZqmU>>3iH5Q`C5`0
z)1b35ycg3r7cz@uSPW2A7Lm0oLL4!;R?t{c#)xPkIR#x}a3hT4LYYa_?QCrqAaDF{
z0VfIjWvV$lRyRMEamvt7t!Nh#r@I+U?pGfKUk)bg`q3FTnKwso?CF0XGBl<m;()8a
zqX6a77tfB+?(~E_Uy7f-7YB&hE?BA)xo;@(4w%S&rR<oTxZ`Q)8{^IJ)&d(e;E9kY
z^45;u(<1677uNd1Y)$0oHkI_C5jnz+z+y;!C;uK)hHv#7>4jwWD-e@XeLm#99d61z
z(RaZ7RY6z9E=LZHo(K;juXZ>r6Ijv;OgI=+>TbG!dvJHUVYVh1V4J@L<7iiIyS*F}
zcEY5&h@-7`_H@~nwPDT7u0ZDBbGf9?qIFE(GeDW*mp+;VXVY_FX^;CjI_Vn*QOr)k
z=qQ4tb&I|*Q0A#K!iO*y=8?rXNToNHpTG`YT@SNj{{=?DuhV`U2D#U8A@Pv2cM3R@
z?mN%QIUH@p5>}H{dwP6_^uqA9^-=6imy64-Uw+F+(Yg0L5+$j{rMX-b9w%cy3t`|D
zR?IDk`^BA>X&J<r$93Ypqp_Hs705UqElg#z6BsB|tvZQr8zcRH(HCA{b|+z3{HSu;
z3+#=GlaS-o&)kicD0(Nb*46p_Z3&OsKy7?uD_PqTXmjeh@VrtrJO&8@SU4PDk}zzZ
z$w)reo^>ADWlzk72SBE3z#;!Vq?Q!|*CK*&qJuEP@tY_ok>WJ^jsVOtjYpdj=m<iD
z4S_OS!iueNDbCoy+*$rvCw13>!Ri>WioDo;wMBi%`G+MSHneu}^&GW1HQLmZ>OJih
zp`wpi_=(NJIx2aDct~@{`cGt=5iBb?3)sd0zn;Z&3&4TYLZtl$6(u|xmaso8EL&w?
z(NJ9|u}J<oq5`bUvWOV>1+5c99*;|%5>2E(#u*x@8rYHwfr$}QKn++XBcfISvJC~>
z(l|3)+13tyWHX6`dO$ypfnHlCsTFB&Iz$c3(Qr7Fp>!K+)-t<hAMXJnxEfR`8lhwz
zP|pqf9mv^c0DGKjSP8A9aZIPIAz6<>I*6pW7lB4%DwBRogl6i9baRRnD&r!j;+LG*
z+DX{)@wnU?Xax<O{WxxKv1k(y7X{LEgnd}pdH|R-@GUJrchI=nFbhB^Hw$$_<RQ)$
ze-3jPSY(R{gSZ;55Wul69N-RLkY^9d#&t+1&GhnoY|>v3(g<gDpM!vEhF&+Vt-zHW
zuq#nHhFYY#r{igxzLjimg*Ay*an!PUAzUSF3$=m+1{ktxc!Y|#B6xL#QUO_kIzTL@
zkhGR0X94cv$ZT^<in3X>C(+?XQcZB#!l%SABSS}5!-2E;31q|cWEg}>4h>l?W=ZM@
zQFlgYw^VRu{rHrNgcJ;R^~S*nJxV#_)C}M)XYf*sp=|?>>j+%dT1vty2nyga{8SPu
z=c|Un`7U+D(O_Xz2J}9(%pSzVD$`St&Snn=cWRb$fJg@^0nWP*%DlCLnV8n;7znoq
z%;dZu_!wuI@S~YQXSK|Ba68nS9_C*R9M#j24!Voo&rYHa<d!E|01wD~Q4GiIrp}fH
z7i$@@!<kNGbEvO^<FPt}n!a*kv5vmI=qc)c#N_~NI#};^O?B+SZC2EBEPB$d*0^FK
z#}_;?KSqwd97MNhi}L%)w&45GG*+p%^PSTfmrO?W$TcnUjk`j<8+G}PX~wMOWy<cw
zri~_==zspFgK}kK;~D?h#W*?}OnobiM#8yQSsDG)%4Dg^5F<V_)!-GQST+}Eu74lL
z>^5^?o5~DM?<CVLxe>lLXf2XkJRZiqtPhw=1D8+`hK^!Tx%ssyFu#TInr7;V_25O4
z)Q<*p@;`URZfa|BN}HeJhIfh7C-5zN{oBE8j<J*g%k_0`n&A`*gYhx!pS&%R<4??q
z?!K~3TvS}nQnh@VwPqyxBns{(`C=gY#eHKkcL};CGV0IoH~qukMW0IF-r4MkvVwHF
zAlUv2I%j@}4PMOYsN1mmmtrUeuCH4RY)|9-CT$|W3Ry4E&rPw~0TUA)V9Vcj^oHHK
zFG*#pNBU2^x)ryE{to*-2{279In+XTv&;URSV&XiI*bv0077;1LQAm3K>mrM|F^9e
zC@M!~+%YsxJHR%5YkmE+Nm1x9sDhKW42IEUO6^g^b7iV9eislZWCI<;#4&UXm(*0S
zg|bBRHkp)WT_|-KAhRbBgd{rvB>;_V0EAk1jukh4Y)gZ-QCj?(2>s4T;PY+hu6CN{
z+oPM_Dtx6Zgjp9&&u(rYLZRR|vl&Q~t(j$jvg0u|h@B;3CD@gyWf;T4k^~bx^S2!?
z5{nLrWDF$+sc!+QUdIH51~um3w9Z@Nrli5@ae`^PV<u6SrbD*f#zr#FT4t-Z5wGD)
z8Wh`*q%z!DGy>vn1417}k68*&R|B*yf<=kV9Ckq-uM7<4AFiTntMLfqrg97|B%A`-
zv=#L>sLSdmM&k<T65)|kR;vv#H>qAq)BYWb%`^R`;nK=(DU$Bz*FbJ<M|ZK?;z-Qr
zC4EeHhM1eC@#vG7yjKQbwuUfU<0QT<l<6$SzF&$lK8C?{>Jp2GWdOzX$PZzc(6ea!
z#1O+uS#hCULE(99N}2Lx-igF-91n4bQI<NMH~(<f&rR!#@82?8!4N<=P{;DY{_{k!
zY_7D~s@FXXIi-Evl}BXMCnbHSV>QprcF}Q|Nlsh{a5Ikfe*}x3NaZ$$$)!F)3}wuj
z$)qoYg(|GmDo7vvieIJCBWgZ>gKYbkUrUhf&&r`G7`9yxQ;_6gkvqX0E}IKWPYu-f
zYzzBgwgwn|r(_ISdGZ=`LYk%?wsBWKxRCj7X<<#%2}#)3m65BCp^p<LaIMj!S!|W@
zokr}PJyE2XTU9%o`ELP6S;xUvFeAa*Q0wP66tP7`HKXBjyC#Itd~LTVn<1WvMh-G-
zfu%F$tt@D-7#5^9;G{Km#R*8$7SOfM9u2Cp4OS)D;mlSo!wZm8Itgml7Jc1KVp74z
zzGhh>f%OPXaqNWU{?5?Vd>EJu=Td~^-(rhp8fgE9*kopeC8TV33X<5I5J80&@oHFb
z0SQTjwK(+z94ZEsgV_ioNyb2{ZS*R&8DLt{a)EPAigq<?G_j=|nHW(rCeWi{+u~rE
zUSJw?n47%YN{r8McSDNT_bV6e!b~W48nOeu62*Ygc9T(2y42eiutse8+Ffg)+ey}Q
zGZTwy9(~xTSqPSOhRoEUyOg@$N}}7v3PucJvSFiY{s3L`@0y7R{wf%Aj3Tqvg|}4@
z%-slnF2O40itn00`<D<O>+A&rYAI)RdWR!fdAoTfY6T{hBiK(-FP#<TKtl$0Xt#vt
z2&$P7UBllk_xtn6oAjxJ-wVU^DeMIDYnR1|x$cS*?}?d7)$4H5CRWEK)9;&!?a}QK
zndx>Q?cXE8wJ0P_!;%6`o;RX+rUw@*zTbh0M+^#vYvp*gBVtWJ76!w(+H-;Qo;X!d
zoID)-h|1Upu;}C!uL|c5zOSJfzMCKVnP1w5?gV^PVYb@qPfBEp*wH}Uci@-=ZnV`M
zw35ZR^6jVvbzWw_dSz2wzTtbup-?QT4nH`8whbJeQfE*RG*CMJ>OYR)pjiyVJ#nv!
z$zuF2s^Isl3H9RrBXhrbK$v{jgS`UBozyT$TJIIB|Jsyei2e_B!!DA6yS%&@&Fmd(
zU<!>ykG{^OLPhkDeuUadcwxnnM;@PjD>Kg;5A)bRlAwP+9;z*%D~rHiaO4fx8PC~h
zSX19XpUM`119m=RDaYshpk*1p1a;p|vTelE20m-Ns<z?Voa$RSxs+QWVavImE0|#F
z=vLMiRpKVyWTUNB)&pCBHmp)W2JFH#Ar}7va3V44sI03^^9Zp_p-b6_G;&P#462zi
z8F4Ngz_@$+tx&AUR((7Zrg=;!!>Rak1YtZEJ&Ab}IVb4Or(?^#{@uA@Ye`VBI1<@m
z474-IB3%S=&Pxre(Phe^K;h+(E0FCCeK}AU-f?Rt(}C^uK&(cXDpJYQgfB{QtX!y^
z63(D4a2&8B7;S}X4}H3_dL+6X$X5rLP?|gQCwdaYhNN;I5xKnK9G;?wY1f=uwgmxK
z3VgPZrk!u(5sY)p<i98hddi$9oX6g*&j^Od5_o<1pGaUXxB^{HyW3^4`fDrD5r<`u
z?U+Y<#kQy(1<y~iRt}Qmd7Wxp@Q((7CEVKQ`ais9Lw6;0t)knPppf>DM_gngQ`fS_
zuB9eQYSvD?h!W${+BCOCSeKkY`q=DF6VBa+0k);UmU=rsyoSAca0rLyQ8+|bJ-G+7
zNtc_g)h7bBkWp+JpYR7<QE!zPDw?6A445f&W}JE;9FE`OYg;DsgLlnKT`EK2-b>LE
zwq?@U{4|)qTfdc)gt<xS;P*OOKx@B!?HLJ_!R~AgM`xrDlZ2hPzH(U@LtG8R04UF~
zrtr_nFm5uEg{PNV%}8ZHYyVd`sIS^7G?JQ~m(O8TXyKkp|KfO`$ZsAglh7uoi9&<<
zyK})0`#wvvRo#)0MelqVilV<;sgkZgWtXx8tzxv*14Kn>H9@hq*))AG(osje2^_P~
zfAWsF1~=8*!GWYE_H=`TV_zb*+WxX-B#XUSAJ)GZxWVxph_(paS5kR4)Jn*B?PYBd
zZaj@?X(X|$fZJST6?_wgY`=x(H<W(`z<5#%EYE?cHnn&KS$848FARK-;iaKsJhP$<
zG;*czV<wDJmuQ=d9LtPLLUH%01=h=#GO@T;fe!UvCETM7zUE@Io!Byu&|vPmj96V(
zPpp~HCJ%sgYy<CzYsg8%%VGVuw(Y?ND%nIR1eZ{F4&YdpTponaA-=12&XKhX$syLd
zA@ztKZIqy?wP?2R<UkwS4Yk#lVaswN6Kh+v4vx2_-$s%-?Ml?T7;HprvRWdqEY_v(
z(!h2#F_)=el5jD*K-LCF0vURSQ?5njQQQ~r#O)Pcm{E0)`&>)7WPv3B)5`Sl%dI+W
znVX}$;Vh*53aI=a^{g5vGmcjc>mDTdLoq5Y)AO>h;r690^ZJHFtWe|I6G=}{s%Xtz
z7UH}|V6n5Mvy-NeR<uGX4#GB8Jb8K~2GG!}z--eSuke#&3_N9^e)z#G_5B~65t~JU
zpvBM~AdeNp_YCMln1468&CO%)!OrZ-_k6eNx_nTC=7mAX)59lsI1S{j`h;M-6_7LA
zeQ2pfmRN(UHQI`7UHiAVhCnpM1w!Q$<MmQEnKYSg$L~Qvw?k^*gfn@c1Y^>Vh3Azr
zTWc$L_WwYKGSJHgmCj~uNQS4xtOCf^m4{V=R-*E3eO{;!wqQ*TScYf_rNO+k5!PZY
z39T7vWq=c+m!!1}UTD$~JKpp$^^P2ntu{l;I1s@@`2vy0=%T0MUEP<lqfNXK2B`E}
z>+BW8N-#dw$?pz9T96oA4(x!~l&%gryP%?5ib$Q=6vgPWaNBy{0f}0kbzEL6Wr8FI
z-^>6z^1$gNI|~tA0guJi0j?Ub9Viwjb75wPc809xbJ<!i%=&5sTewv@V02aVTF9oh
zpnKnB)$BZWR(F-EONyV>mEf>>0WzriS0`H;k(jJVtsdyHjr9V%CTvL-jAG<N-UUS~
z1x<OvPI23N+}cMY(i@Urd40zDTl|btpW>5VjM|a@n4Thb2BU$wj5|VCc$jT9o0lfA
zme-8c_WM>O(k+POc`I}2$E5M`%cfjiTKM7?6oynR2J!7io@(?t9+S_vEy89&0L~G#
zVu27axte@WMd`7;0pl!{xwJ2ooj;nAF=C6r!uqZM`B{Dk==k=yxulla8pd|NC(DEW
zu7yB)Fxr|-q>#%-*0y$-iOJ#XeDek3iVwUnA?fUuQ<U>yzLIqwC$J<IT(%usGA*W+
z*tl#Fl()Iol?AG6-%Gjkm(jPMk!GdDmmA8s+d;tqjJ76serGBU>b<B&FJ05bT$@)x
z<ptN1#KcgQN8|G6xlwtGkCkAw)q3X<uT<XiojZ*|w%K>t<BIOa5!mmvPf#n0({<rC
zdt)1LSW8{y_#&8qh#pYa8Yrrp@j%SP%H~iD<L9on{8<|7KQOXNP<P+Dt<C{ezjQpH
z%ESg=r-9W8*TeSOh{24RR3yL_r(RSQA{e51t7ss!VM~lKsKR<4M7kna%n8zUW3g85
zZm99~*?$0Lk2&F#;s+bMWL{((xpmWvsYl9Y3&3Vi?_2AR;~q8yNF5840f*O()+#vb
zl5O%p<@=QvY0eF&6X;Mt)P>BZ$%FpaJ*QpL_J3Uln<Hgx$pn$q&oTD?_awoF2etZX
zwnn#B+=K;e>LlT!w_csX@YY!&wig~Fht3Uq1yevvL%39NGi;P*>ssI?zgFnx$18X~
zKlnVl_i@U-+;y>tDf`mnBqV2Pwoc!_D?r)6%u<U}?lDIU0odI^I4#9ExpJ|9;u6an
z<p_z}`S~4@;ml$~Y#I3AgLn9Bx7{B4v=EC$#V|Iqb)8VoLqwMXKT~ACJFOA+V}J7G
zo_2j&n=Oz^T^a18!hv&qRl_sgc&*=J80i>83WP<NB#ceADv`+zS<V@^e>wdQk&nG8
zYgUoA2oAh}5qc2mw_Z>&o?5d~B1(U`pYLOC`uh^z5cZ>(e}qZ68+%(?sHlh`JnYa6
zMdZr=MI7pYhrva#0<(1(+Z7+<>5<b82MmtwMN>I_JH=8KzCUD1YE1t|VwFvO)6ucc
zga*2Lv*gP;a>`5tZANK8XP_{%O+-fJ{ALQiV9bXZ?7`z)B~S4nt>SW{t!DW*8v$F;
z#sSB62!g7G2kvFT3B|G!$GJ3LfqX}N*RJj826X8w2h|4@AK=y(5keZ!k>Dobj!-4R
zRAk<f;zS*naLIUGO!nf~WT-Y3i$_)uLqyln;~<xph0i!l+s&dlgwEb&uf=dq+eT5!
ziDH$3SN@e5<>6b;4RC<WbiMcmaqNol4ndj~!6gt1nwD6z2t;ndlTaD7b^HN1izB5N
zVp>!;j0Up6J_%Iemx{s8mXKE7(VtebuE-^u#Q<j7IhR5iH?PHamNSb>!{XVFbYVTS
zRZFL~SqYO6TQcDzm;N-i5agLB&Qd9U+t`qX+7|y~EG~WKEU2uN=%ZnnO%jfr64}MG
zG9&eQWWp$R@mx%Gf`gkhr8mJ^?zt=x!=N&7Hh&-f4dy1NHj9xp3|zo4b$6mnQk$Fx
ze6Y59m7647dM9B)mxGrRd3yN2^>Ex=D6RwlT^V4*te0WI3m+jCml)niOZGc!`SoW8
zZff{2LyCake<cx9AJ595D<#bUI4rJihHOcp>JOqgN#6<nTw0PHluQer=y9TQh-WBh
zLS7Mj->UZ|V9n`?md>`7%C2m-O$*a>McQ<Br{jj~wIL)31MJOg*9~$5qbk&x44lNx
zij*`DZ-3HCaZTXPV$x2shC7+di_aPaTWC~l6w92eNz1b%=d10ttWrHx>Xr`PoTwXc
ztOX!2^%e48i@F`3(t{c6?YJ#>2L~z;4>m6p%kSkq9YJe&UWzXxWoj7C`F{)EX#>m`
z#zI91Rk`(kgdU-)H0bG(gP^g!u8+tnf?NU?(W$6&h*AhI1qI7bO)!xoL~^dbNkV1J
z2)P(KnA{dv@;5XIm~}Zgla$~}x(|eL6d@uw8AU;laeQPapz^qjA;)y!xSzOd8<Fk(
z$b=X+R@Gvwtf=3(V_bt7khb*QrM1e9*&_8gQtluXMXXyGtJREx$Kcum!6E3nLw3qX
zG2OrfTERyBg^)rlJ+>nILAgjq20qqd_!SpKIOYRjzsLbxDI@?<LjZk{1TmKCNsJRp
zMS&`U)TJIF+X$JOz@>#qE?f3f`QKBN%vShX9H5YvLD=SJ@aoD({ceKN<u$&ETi4;U
z%`>;_(ryLLfCbnZOAJ|&GmY-@Fxw`_kdkUo#^mW(I;fo<+G%oJxo2CMX>*o~+XYmX
z@5pWdw3ZTi2;SNpQAL0{(*zJ71;b`bBU^FT51G{<Q{^I!AyEW?Bm{QcB9lPALQ=n`
zV;mn!I{~VGYZ$2nAln)i;v#iq8(Kj`7NM5L2V&N!CP>ybV6r#$MScN3^)u!-!~yH3
zkwR>Y#m?cX6EuBAaE~Pg#Z(TEI?4!sW>7FjyQRcUh8ps#t&(g8Y`{^^X;<$GWC3V`
z2FMK})h4FM@oo^fGJxH2qxQn!l(r~#mxWub)-WPpx&k%mDdkkBQyEgMJ!VyiF&Pd8
zp$D?XawNPOIGsy>-P5f>vr0U@3dlzxM7P_^Dg;|7&jHH^*ESvaBiQx#eA=`m;t5v0
zv%ZEL1>Z8jjXN#mjBQTiX-!{&fRAPY0kA9qmQ*fbVBFVlikRL@eC04t4?~JTQ}i>l
zlOHR&B+6p2geYU?zsGrq=wfgqUEFME|GRLu#v;wX5@1OKIqBeEN$pz`S2*p(!aJE{
z3YdTB>T)F&nLWm#7G~1OFfr#J>RG=!C#S!;$4i|dMPNz5;&A{8Dm{RXaswF~hwb*;
z5ilTyEYeHRjkmN>Zs-9c^5?90A>&hVTarfNDq@H7H%!%rgPG(IWB#EGEn@6me%a>8
z;-^!1kXgNLu9&)uDO!cz>(z!?kxn8Cn=h9C*;Lf&&Scbkr`*HU-&yz&;yLZh`~?q1
zIIk@z;sE#>M2WAsxG$+GiokGf5utLmesvs?i417e3d~(fGq#%h__WaP8>`6gL{N1V
zczfWwZgrs*GvAROkt`xx(Bgp7$u4=ws9j`4uMLii%J2c1IXkC=VcEgn|Chb@0g~(}
z?*#L`dfi>qYR$YEwWI-$X0k_()QCT75cmWZQg$;ygLOyY6GmpSDCzK=Y&ggGz<3s9
z@%5;IL3TjnfZbu&8<auo)%qMTcHj+pt?)gByrCr&v16Z&eFS?~I9LwbK(u|FJ;BP}
z`~AMmd{xz5UG-`JVY=$;u9ul#ewq2+_vM!_zx?-HjNqt;Ed%NS#ypN+SL57Eup=~G
zpe6u>ce)$sCXwAD#{qA{LxM>>SAQ-?n8W2mq1mB03$N=0A*3GdlkO<n9Z>%gCir@6
z*&P(y5Ubn5eS&?Oi#}9)7)3EE9K~eigU)2lY1<=|7{9ywIL?H2&+Nq8%gt0L6n*S1
zscl@`jxy0(QqV5er(QKk^I`_UZ9F%4+I<SyMmyF)$ER0=<Qt;f=1NfyVv8`6T4Dcu
z!MyjAAF>QHW%1=V)bW{3Jz~<EqO2xdZK%hMz`{kt@OJU~{n(o<tz{!jh~H2sK00%p
z#U8R->!uc}1B(?VMTD{ROu*RJV}A7y=J3%@7@a5D)n0S;6>^U6P=07dKM4sx1^D#>
z+{WMrdSSiH&ed!cVEqm|xH;vbQYW?w;8>WhVnd2D2fd#v*^C3t>(l1p^FL&3Y!S1q
z5ue!Uiotf!8z%lD7S1%$Z;C(_;>5h`GFve$(G9LUFxdY^ZpI_r;+@I0F9*a#i8Nv2
z_azyG6etLlg?bX9jx~sWp-aT{x|<BTSZr@xg%FD*Tyh3J`5wPIa7i%aSI325^;-Fo
zCrA(vbwMgOC&s~L6YPQ78o)-6M2~mx?F|kH&B+5k=b9ZrHSSTpyxDXqWZWEyDH5o;
zSdD6Hr=7`{15${zv8o)_eE=a!g#)v7ErcsNp>gk2nvSn42ixTzM=zMt%@@jLWY}?#
z+0?GhW0Ll@P-WyYha_0DLkPwodf8i)4zsQ4th|5JCq6%g{t&lK1h@bL#ykqG2iW3v
zTu=M6yj*^p>a)g#%gEm*!)c}-+5^re)m1p%#f+gJ-(5%>oNc`m_Ty&ZXJQ8P0Zprr
z0<N)t2L7%epx2wN>mS0hZp?>TM&7;On)*|jT}8mX{NKy6p(dkIz!D}vdW@@+LvBP2
z1Qv_aO!b%`nyuVzNhovB`ys~iGS-k=JU-+CX2Wb<+oG-w0f8#ICpz|HquXrd4mi%{
z=rCl9Ig!~IFfLT05-@z@a`GMBt=EZh3=9J;_M`i)E_HdyH?B1wLyAyKd=4nK=bbVv
z$2}ZRR)FW)5M!SE5m)W~DqlIH3GEKEbxZNXE?UZAw*T(qDw|;mLi}HbiNE!G%qmgZ
zN^DC@?VW(u@N6CR-Z^adwV`Pn$e0vg+RnI+^h_k{r0V!$+%B#ICB$Nn?-Jh^9doDd
z?g|sZmaGx)>)y^-#`Ss}q!D_wHcxD74?{YU-4IhR^?;C<jIG#kqFBJ|^lEBGyr<u_
zT7%Os<=(=94^}@~Ge`xxAGy^X;B0Gb46|uxPb|mSh>hWnyNc#lp{OWSPaVf3mvO{E
zry_-{qEnxo>!Yl2xLW96Bd9{;&n|9v69>V$<6WbUs36Ji3`YeBK+h{7m___&VVz8j
z+r{lJ79Bh;FYXV$g#BsuG&V56>1peqdPRL1v#rA)cn3dwXItG84=GhBN->69@$KsX
z=%o349(sA*$kn^5UZnTK&duxUUSS*SorsBV8wa3U4k(x2mZ;gPhm>xk=^GSc*~DIl
zpM3JuT0eLxzWgd|K<0Td2*7}`(|pl61|UUiDL%!tuNGp=&EG}_m8@kD>;19V=I<uu
z>zu_3AA%7UzX^Cg9FJzJtI83F&)ZNcSnu7Dii+#A7|);p$!uzr-`I>L!ON7W;AhBw
zT{cY2(oZ~K9NbC`@mIcfEe<P2HaBB5LXe6@cGsJcUerjtmqF@i5p}kePf4Z^gd#Dm
z*vuw0Tj$!8Pk=A_H*3jjpWVqA9o^)#-)QILnur?WqF7@d3M*aYoxaNj5l>)u4sh3l
zv!+WtyVF`kk<b%6YRw@8Be)HJoI?zI*Aw@xGTE<!M1~5;f~xZcELrvW_PO>gqz~Pm
zM}@c32+vsxfo&qD*E%4HbOO<r8XLW(>jjN1liFUF=s_OG{ac!@W_PD!Loop^@{KUk
zaX4JMt(sA)hb#BC8i`p(w?U8Ah9*2^lESQ27lTF05^U$TOI+}r*p3+AuvZ>85(8fG
zL==x#*lYoFbRA$Lpb!P;G(-y}sw#R)F;e3OUtD)Ii*9uzCVtO>IezDQxvM>!YQ8wi
zX#kI?a?NQhM!F|2NVZzcS-R$%7>SS>M02+FT$C{S%)OGUoyMEAxC{x78Y5p^XMPo+
zEH==(LMMs(q<m2y+!&$00IhN7z+ZBVs?|C*<+p1LV*>2Q%zWw}OtJvVc}}kZmLHzR
zd@W}9bhh<LobnBwlzneE=^A1!3*iiDUVkdZvf(RGEUe|jUrUT2rV7aV^3|3HgBgoo
ze)sb=QQ0ww5#Hp{xN*HW%O}?r+4mXa7#IqWj{}jzigA~J6_WEQGS1iPd80jhTmRkf
z=jPP6rc%n-lU{X$vzBRyIr8`GiDO_WpjchR3|H%59K+CJDd`vi@3@0j^@P)&`jLw&
z>~NF@0PQWVH>n>N7x%V8cr#tgMdchK|Hx340<`}x&v@P6Ayr#UEp{vBLAUL1ME84y
z8q?D!@1`AB|12~~Mtb<L64=ETXAa2*I2%2BPS2_!Xo(6HLi~m{uU$>ntZL98Sr<7o
zK%dLmMS4n*(l_27Y--Jv7lG~7xN#4}l%WBQVig{4I47xThV;ty$7$707pn|7jVN#}
zW%CIvgsQG$+<Tj8CeTi-O{Sa$zlaM_>%kpYM?8N6R~+6>qWmAo4;x}(wq`;Jh2({)
zWB9!bxWCFnO)RA=I_}#HNd0nIVeVvqssdO~!%E~U#hl?lVysj?R<HHduE2PDZFuZO
zx>VNcs<ZPr{H0zdmr`ZkmX{tVqpMBwhO`u;3x3xMp3><f<T7r2JXRl-(o~pgT-9$l
zH%12+tkV?o&dkhxWChp{>FEK<gYd(il@9%l=9d}B+gBe%myD@yOy<n#g+Kv}e3Ld$
z72pxYJ<vXSrY9T&6VYNl1el?#m&h}jXWw=hKn&}kar@t8js1L*OmS8Z@X~Lj8SL4*
zux+%&tiRT8mHYGa)A*kDZNzZhDl91$t6ORhUzq8x2So1zC{`FnCAat$H9z&EH;!-_
z!J8XruvrUxTfr{;YxAi_X9bQFO86>#4P*1$SlLj_7;ev?xV+hlEWqrhP!M`B)`h9}
zak?&92Wfr(XX?qqRxI{Dvv_-jB9+APn&PLT<Y!3%P|m{96C>y!XZTMa#nZpOE|jW=
zt>_u%lF(iQ#lgW3v>&0Mb1;18aU@eOOzF2ZzTscGDM{1zt>y;o-w=wSy0zS!Ekoxz
z_q{W6yfLo(@f)7e-KhS4C`%Hyxj2I?LI>B9S}*h{2$wTD-yV33vq~atOEE}gS{^<6
z6++cKLQ34z1WFEcOVatTOqFrFdSJO&Sf`6zO;nF(<p@kzZ3w%Q`R)rox{+|&W*LHX
zPndc+=`Jk@=Mv#?S7F^xA>DyX%zI3eK^RTQsI#OWep*I7DkDJXb{SJcEr7^XgxTF}
zkfSso1HMZ<3=IbC&GOT%4wDEmmu*RWUD}461S@kuK<TzC2gO~2%DEQCos<&MqI_Qh
zk>hU{;goswc+lRjD`K+;-4n1qp)m|Jd!E_$goXrmo&@rwf7kVhc?lnF6m##@K!(q)
z=jN&U1yfv$?C&zmQ(F+RyutUVhLi}x88a>K)XHEEEzNSnNGwg5nD1IQ?t5FOG0*MD
z4YCGmCGTUP3J8cKyEXrW-MUuK;DN&Vk4hq<vs#xEsrCC(^NrR_z4;$r=CtkIyygq*
zW~E)TFk7?L{9<A@VD+e0Bk@3hC6&xw^{!R1AY1&8N2&C>Ekoeh51Hl`_hE1uXLu_Z
zpe#th1+vKfC8oBkfFscx@NLfgZ@@=yKgz!Q&>w2oLM^#S1_SorkelXPu1Ms6oLy7Q
z<6(~7SPV^A&Xul^t_rAqTh8T%%AhyS)S+_1!{Lx|26qFbV95^;t;+fe`o`OEc}ab#
zv>%T`Y+E5Gt{zsir+t?*<|k809`-{~s6RZ9;3O(ifx^RFX-rkYMMLbN&Dz)t(i@zF
z$brU)Y&iU55DP5N2wFe5zSM*Bj^_GaVCOcP9%B;0VbmbY%{>7#ien>jD)7bPF-;dh
zIG!~DSF#|Jtn?4{{4b<{5Hqxb<m1D*;NLpp0e&xH0Zhv{V_t;C6u@e0?@G~cB(@l#
zOeAlb%rP6-Q!Kdy6In)H;HWb)BXTEJ{1`phU52FI+eK1z`PHl0H7V<wYZ2pkfn4Tt
z^`TfHVl;?18?4tpiPJu~u|nk^vEg}_FXg$telQCclJjj^DqryE&MJ*Bt4%_mhQ2cu
zYihPTE{i)b<Aul?JP9O`kLlrN0<*AsO_%k*vKYBXr?Y_dXiUqf1&TwHR8(=1aPoHu
z-ur&&*im!BbN3q<I)vFeuf3%$zaVi0zCY?|b8};<xIL+>KSEEky%b1wwJwfiN})S8
zF3=qMgdZWr{^uC8u(iO&sH%9}5P1%UrK6VOQz%|u*W7W|e7#k(G*Z39k6d(q`tGqe
z3C^swJp+&fix$Rax7Lk?OY?}pvV|UG?=0LGp&pGjSeWnSv?n;>s&Zougv~dc&di-(
z;E02VBNsD{GWgFV>84lU=U}8ZwGc=lQBq*$`2n1a?8g-C37qy-t>_ahh{_nZ)IyTp
z-Yz5HaSV(x<g2LRr#%D8_KaK`3aSr{1J;<g`rR5#;eHPXXl=pMoW=!as|V^73qfli
z3h`#E_~@gUw|lbFYxBsVSLWUxbT;159QG`M{6Bp}Sc<p8W7lV~?n&EU0X4>wa%4CK
zMBYL;Hify)+u-94s%wY<;DwwV_g=Kl@I+#d8*-JPk)zz}kSzCFbjnxKB|#Ifv?Otk
zi8mpZ7DgC2^lphLSDi7GPUF?ROf<k2K(LQRp%e|{bn0#qf$D(L^sbwIli)Ql0dP2J
zk_}Xv99$j>4}oZjR8+AHqXG@clRmQAT1G%*G<B?V$QK#sP+_SnDbPTe7g_e50X)xt
zNrlAF0C)&-SYYEjV$9tsaYof=n-N~zMif2fmjv1cA*7CcAisyhKOwnWZeV<AohdTG
z2m`o`CH)z~Hb*||aOW@@<XVVH(J<#r<a_4o%@$_U*)AWhn_A&e1DGi4GN^Y07HbWQ
zO*Qv<XB}wyW6gnNH3Gf~m>C@Ua5HLn0Y)3Yn{gOd(8%pasvLbCVS|S+XfO$62nNIB
zBZTLDu+jjqFh>9Mt4WH%@<SB6#zg5T#iD*_vBK6tb1HBA6r%KgP~Zec=YR@Pli6*F
zg<(cpde{mO94}tp^Z}e+!$rCS1N?o84FwEHG>ICC1B;-xiSudjVzcx)li&(ob1Yu_
zzr-5hKXuD8gn;0pb9M|^Tq++>$YQm&XtNvI0^%kRIUp<0prmOL_Nrvl!gPNjArfwP
z(aCZNkdzGHiK0A4e+C)3DTs&>4Mwa&l6OFgEd<O|y#Ohq=aF17??pve0uH%V(7R5t
zP3E3SIJsccnN$pb#aepC8Vc?iM)%c@%mrbJ0zZrTP;S|&X$@f%U#8kQg=7=EIEB+o
zm)^on8&K<B$oXy_35r0C^@sDOf9iB1Tq9K!r61$7ok%C$xQ(s=8{y1%cd3_URp=tQ
z1TQNOp|`g5m$j!HmuoA&<H7^4R)26zy>KBQt{xuYg12o@H@^ceyEg*;M_du{Xc|Ot
zAc&-RU|WhI!OU!hJC=7Z*uKQ#`l81Q`ES7_>W{Jl5~}cy12sjNU#y$6#f^TMA;Rr7
z2v8&N6$b$V>WPmWT{w`)CqJH>Blp)ZpmnP`f1FXAe9>atSeL{^l>mhP+)PsM{~2L}
zfw!#Bfh~YAFoDh~u9nOQGhM^^LRG^uL&K?;S$=2*5NB!h>m08k22v0n1M{_&*VoO7
zueVH&HG}n=w`z+*2~a4U$l;6FRuQePP|{6#NNN7fJ9ssg7v4{(oR0pnhps(mk`^Pp
zmYg07^CTG9oc3G{vozb565<$``j=|<?uR+lfi`<({heZ&K-phANv|rl_YAuF_WLM?
zAPJ4v_P$bM$|<SV;zatr=mv?zM;omxL-w6v(z>q>3~%_}DU{DK24GcyT_SK^qCVCn
zzZE>y9L%7rkt@5CW7pRNQtg3QGJ>qHT+?NHV;5>j4)d}u$jLLe=D0#|6M1tREQ`QF
z?s^6kLgoqlEIpNg4fQ&T<$X%iEH1<EDy1ANq7F;Ek9-HGhJ%-VeT`%E<TasDYugR)
z?W!EVqxqo<+#45va@DD-F2%kS5-1`j-qr1XMXd5{)PCTe)ek#HxKaq=nK9mD*D62%
ztg%$>C{<0Dg-X$@$t`Ziz(NMBO9OyJm}s>2UXyOSXb)-|j#Vby#EzKpK(v21HFx4s
z(P&2am*(#19q8(c!EZyP#SeE>W^?*r-Q4BH+`+af#virD{ONkgl9&=k>7<p3yyyOy
z;Wqr(2hsGA#cWa?nQ?|EK~#aqj^t+f6EDXLZpMbTFl&G9GR$`#GYy>6V}!XdGrRSG
zF@J!W(jz|(fqTrp%}%lHT4!qq(+mVw8GWykYX4j74i0~)U!91gT7%AHdlhW?@e#{M
zT)3gqgXa3l-DiK{0n>aioLGx=9kUgIRfIjWFPi%M3LMb0{}u`CzX+*whaH9{4xM@k
z>yo>*ci;_>kONtcRBt%OD~bUyqO6=mj57!rAIw%(cS#?44&9;PNa4&e(^~)hJ{6uO
zIgM*qn<|RL`om_ujR~~YPm=E_CAkIjHz;;i&wu$-kM*<_uCAnUZ=0xP$&4P4fJs@=
zg{qIlWSTN=M@87tj*BnAI`v>u4u9GlZz4h}tE$gs@RgYz9!xSWu^qXLSo>);24Ko*
zNO;*CkEqhc;oioY0%u%0#nnU`OkeD@pVTRdt9V2!PSecqs6d+9b{?ooZhMWUun<ds
z&Qy8Sf<)jTbFlQ+tU3^27er;u?=j{BiZ2qoO2%uuz{CrR9_13vsG@Ho*B3iB$mZpI
zRPlBHlAl^t!)fy7fEKj{Z5FF!5GWIA(~!VJ`^wQ%83w;8oZeF9%=RE*nqjtevHQVX
zcVMu83(@v^uXUu1A9T#NxR52nxunkhbU9{QwPmp8OI>3{I7wcyk$RwO%h=|14qxsl
zgX&423{_>sS4nR!dm@w>%(m)=ZpY`TRL#jX)i!K&lg*if^&pq_=P{j%2;spk!t4+s
zI`4M(ewQD)A929cPqnV~AMT*eabAy!mPtPlP^{BpK^4p+wTv87X~b94L>MS{4=^yE
zz<rPTLpLPaK6Z7125^HD186dNsEfJ%yq5~ePu&?TP!$(3%4`^^A3z}m%~oB=w*0qi
zrPRHxi`<55SSVIc;d9J=`bte?=|>LQhj;WZ5;NAYn6<%?)@v?_3HU6L`7_%|`c&Un
z9*k6)t)}&hUUXu9-7A$(NL#lm&~kykd#Inf-bO#&STXE!?{N~{G-Kkocuu=H`ojj^
zQX8*`y;9~<@?01SkUH<lbruv2DRyIpDD#Twxg^*2Pqp43Jw90F3zqVZ1VJXkq1RH5
z$YG{fJhd~Un&tR_gViH0#9|jsq?2jaokc|Vb3?IREyCFyWTKdK2Y&1jU~0NB>Qgt6
zK-Vj-!Xsts=341hkM%*J1(P+=N-9Ev*{YGuse182q>iuX6jj4%9$goT-d@;&?xGkA
zFW4jAzM;(_;7X}SyFS0`#JKKva+ex;ik__UDf2!r)-Vpy$z?~vPE?oA1wVUE1i`&K
z^>tk+R@YV0x}wI%y9$Ov>7Hv&Lze>N(X*>tN+BHT62tWyW@nk&=O8ngsA1U#tBW~t
z<{ON96vFsYEt*82?wT3cwM323V%SL|$Un#B7K5f{2T0j>+7UG#h^;q4IdzfnQ=#I6
z=dAC;0fga5j_a|Z)zhzi#!t~@lq>Bfo?Z$A1_xu}n}qcv7cq2*nK*N*wbGewJ)xh3
z9A2POG<i@=%pG~@y*fte{a|hKN9ec2j4?>vw^xu$%aRY(WD3ra@W>rg{tO=S6cE?@
z`fqE5Q3i7eX6sqV*sAbBDu=%E0kh5ol=1R^d6i0?;o-nyskIJ28`mbouQy(<9wuVE
z;ZTntgM5atWX8wWi(ka4A6s3-CqqQJdKlq*dD;ujR#y_XUXp~s0rTMMADBDvN#HVa
zcTXs`L(rV=_|+F%=+Js>i=6}qazM&hcNl&@3<#Wq&aB2-f^h?_BhGpo$X6JBJ%Y}^
zjr~;&VYnnbow1}2;9ue~1XoM9U5Ih_I?wk}*dR1pr-b5Ekl?}*b0`b=m71m5>Ln1w
z+H^{)_RciU(cB>(jqZPuZgl_3;JQi1-H$WOMq#hAOYO(LjGM=CJuSwZO-xJIjUHzR
z3wzTu^l&P!NlmZ0%qtnOBf)Z@Ru%0@*?*O356Soh{04|icwX?e>61y9`ZTTL@X_A-
z<M2U!J*3`|)fV2jO9(jYF{54+Y?=?5jhb{%)90@H@gAWiSOxqmF;EISGPhU_EniWm
zC(pL<_O#a=@?*ts`VerRMk{>Mpr>?yelW$_w7h+5dUMJ{N;j`E4g|vi#pc=<BPoh?
zN!uq{zQVM;uX;~D((g%^{ZBSw6x3H*X;!`RQ%l%nOYwehryvVGixLrM@{9XS@rN^J
zfeQLN4`Emzn=22_;wuYt``?OlGoMT{sXfoFKKEPBH2>myouUQha7feJ_$6l+`&uj#
zKCfmLiq#yJ5wUiLnFufA4Z_DK`%g8JiZ3}<f>;?G{L_>%!197|2dyRT7Ise|!ruIw
z&(b;XwT+h`dge;Ic<8If3TaVnYUx346xLusvCF6)mc`#r()ZoTyU_XCGquZI%9^!8
z4D*{n;K1K$O|QU?ss1#g=+XlH;>;|?eOBHICZpL+vFruwB0dCNy2)75Qa=1u1QuJc
zeTi`4YM&Y(l{AkWhzA$M*ojLHNTpMI2Jy;;NTEldh?FYa608c*65VO-M^vm#b8}1u
zuY-;+B|=qSbQ&|cbU0w)m1#%kI|Oq5jJBtjOTMf!s1<^>3St~~GaqUiv1lTdqQSDX
zHKnH#ya4$Sf{xGOrOMS!dH%xC@N)6Q1RzZ?!IBZI|H^F!27>t5CLBla_RWlI1+mj2
zcQB@njF(it!~#Cd3q%@h%kEZ{F}s5Jm?j+c&cg)W?9P}^Fagg2fx}i&C2HXr4Ysq=
z#pF$6sg}MsMx+aGWIv26zD9WJ?U{INh3mX@5xI`P)$vYz<UkxNAH)qiC=ziT{TF)y
zlQU}1LS3_B&L=u2_;3PS&{_OBb5f*p)Bvyp!7}!)t}d3mv(#0GsIt+p2#hyCgQzOx
z)haompS_@G5RjQs!G(l@yN-U1xHwgRd<7pz!MxkOb_;W`uzExVGWXY3SGd%F{?oS3
z&jq@3m!;7_V*1?yrCh+y*?nwR1ixbcyKED#!%uUF5m~q&;Kvid2;q~H52x;gjKTgB
zL=1&k860z<C;^riL^u`Kt7puI8FBMgmT*RW8fGg-4X_^-rCMT&tKMo8ouaLJ5|n)I
z*m_*3?wYT9qwaIHEE&bpY%Sc$a5E@*TtP0QJR>}{(ZIB)#9(DtQ}pye_4I*@^B5Qe
zv+?!ZCG?wYon|Y?{2&3yp`Ey-{YEs!C(VUt_E@8c-W4{lqDlrhb<M((_c}UWo;NZ3
z33PMdcxgFwV|VjM{<%H`cxQ%gwZ+B_RG!pkJmx(!XZ1{5NL-U0f-Eq!=)Z;2C!cMo
z#4On^RNaMuw(ngL6K~`|G41%B6V;`N8|XU5Qg^!ahbW_~7pIM^_)yIXJWj<}BmcEJ
z95#t9V$vNsfT}MnhkEA_o4qBhq9J9hV)Rd-M<&)?0z+66wo9d8KGOm<g)4#Mio|Ry
zK7>P<Gb_@ByFD%Ac7=V2+4Sk*TQ<|1a4de9rB8+K1UejujJnh+-)}&nffa8mGMF7s
z3t;ZHQ>fDpaVLB!KFh9w)s$k_J2{-~c*oxN$b%5W(X6NMGn6S)@_vDJ+N*QZTTbd1
z_M^eQY29Y+DRYClG312)lS1?1KXY^ZHd(^nQq>P=7s0GXkw%RCxr1x*GuC~aPSAbo
z@EC(mc_&~1-+0A&td*zvQ3<GjlqKzyl&eAkju(x%i1+5ov9zE`v$zE{T7Ru<umv^y
zzkNalA%Do}yQlCOB`y+v?1*LLa7d5US**UT&HwNt+6p)(o4InH5l-N@xy5ySK_F7$
z<7fEMeq^7t8jz5c!I2!5fqqLrv*c>sm3Gaa4qSe;QH76%y_RPS7YROf#Q9eys#<KG
z!@gbDVv##40}Ip~<l1YTubjW}L7-USCg3@6(yQ7fumiTJ>WvQIQ`{VZ+zN8$BH^Ts
z@k2d;sX2|PoACQ%n9OR(!XFaDHy9jeTS+{xYm+svkfJ?<`UIHXqDZS|s7dzp#o_5Z
zXD;C}sXz)#(ZdFjeusvji_upi5Qc8A()B8&vAnRsr~r#f)9{(*XJZQ7fWP?!x#i_r
zxEMXgF4gE#fr9ISq`?s-f{LpS8M~lFJnO;2Ai?5b-;Q63ZpGZaERA`gpR$K=rE(47
z-R*ghepbrRrxsEKU3K)cA6?MHS^~Y4vx!ySFB56?N*|%gODwjMwjM@>P(YThJ1-Qw
z=3|Tmcj8<+2W(f;9+hn{0?dcVwZGj(7rla+1qE#<LfwdwySbg-)n<PZS23ghsrMds
z`HCL7RD3}3T@_7QTqddSEnz%Z&u3!aXnw}b7Po6lD<-+c591y}Z|QaEX(-?F6_xaq
zw<GC=m(|%Ev{JbmtvmW+1YIP2m(L}AxO#Rz^<KO>)hKO6<Jm~n9+O>7igE*HD_@`V
zyEcxXO))HxUvy>@5yi&un&i|MFVE_C@6Xk2U4W6}7C@T;BlV|J^P0*>G9i_zy-Tzx
zDPCn(vis2*pjcfb411gR(7Iu|Gq}juaRf1`@VQyj?N_gW-OA8#uu90*&OwI~nyq+6
zS|;SgsYbMG*lPns<F{(&49^YL+1B^J-Wr&#`4cOcpVMOb0UWL@t^^>&acst%KxL@?
z#(VU3EyA{TId+7=T}wWs_f{#ly-L)5z^r>6g-{J#FPY4UHo{bxB6fkc0*$<M&T)}2
zmc5wzQgHx#ZrC(`rZ(s6&`AWavbYt<2Rk72cljhHZ(Nqew{!N$k7~j!!H$8!S?vAT
zB67t)YF1qGBkO`-q!wttmsaQ>3-d%VRLlSgsR+yXk+^zw0&&b9A2h>gRwwBO;uLIf
z$J&WUrkKLGOKrWtNZFN%uu;=BED~OWU^AFBYy9Fx4m;=|5J99+^^SaY%?S}$Kx#w0
zgF7c704IuDI$h;X<k<O~v3zDQ-{devT1I*`xF18<Cvl9RES79Db&0n==j+Qj!4}H7
zi1%D8b%;o=fVY9a0{z$=4emiMIkY%>Yf6woiqk!CN<qsB)pjs!ro!B@=L4l%v%<UP
z9l$z1Z)6ssDO8+>8=T9S#8PK0pA{qTrY`J{41>4%Zz4O=rIs($X?jh<9N;<z*bE>H
zVWOqXBt;=8ssTX=@f<*G;RjK$So($mid~YBJH?5-RH_M(O9(ssw37yR?17UYZE}IK
zx|yD#fPp&_76~rw!k$w3VQvh5FIES6n?s0zSlRX-!LQBQljBcnid$rueQy@)%y2-l
z9D~$inLG0$%wY8)mmVV`HM0V;3G{G4D}N8BZ@_c2ZxoS?7J8ta9w`43Z1k0iJyNk{
z;mp0v3w|F_mKjSKd)Hku2b>FXr2H(iiGpO{Abwudignav3Ldyz=s}kjh)U4#*|W;%
z?13<q;{|q&Sh%b#V-6WP%-#}t(PDrv*rBit3cf2zi%t>WqryZjUZ#LvLf9>sIeo!4
zAY}BGEMKSicCW)rQ6Nk%H|=@BGVwsb;x^<C0pjP_?#}YIB^Il*45?dL!wro$bhmzB
zhP9)z10pLyP)QUlug^3oB!@iFo8kmq2iVVPhG3bd6Fta>l&&W)60^J3WFd^H8?2zA
ztS6uxu()n~cX+|9988f?02D73%M}`f3xP|*J(PqIQOQNF7AXr)e8z@EWv(GS?hcM*
zFyGnsl>;Wl#tRSf4hj+=Z-7Y4{S#YYzu>z7I{DJpZ`66RYS+^pGB)5IFbHk_t_A^P
z2ebXB^;`meoE=o|%#s1?AA(A~T@`9LKUDWfMn&Yi4vVtQ`o~R%Emf&Q$h_*!c8(F}
ziWzrk<0aNyM->jM)nLfpnhCx!SQu(*r~phh80z=2p9JU>iyOz3(UE)WscS>Dk3GX2
z_xCe6r@bB<8N_v=dRl0u2WCrWDas%fgx3VP0-i%$!6=`+(OHg2{N?$pj_<<^kLWI|
zBX>x4JFvQD5XY9*%P&z9ITYeTMV%%(azF3F2&)U%G+Ktf{A^w)P;#Ihmj;%Y-95_B
z?&w|xVMDyRzwW6%HDwYsyB>;{r49I6ra6r|aSKF&shz6e?k?g`LjlE<Z?V)RpPCIZ
z;i1bHyl1Shm7BkvT<Q@m^5MJA1u}uVQRc0)36KLxnl_->VR9HMq6K;hAV||Z(<h<r
zgBv?khY5!<0_Qrz2!lDHA_*j$a3%N)nw5m+3%$z?RNlf}BtmeOnoDC8rrB-uS8@xJ
zpD0r!uM!?NE@oTCmyzS>DOC#1TNj@$l@(1Uq+%Y%56UTSx`5AvWKYEI(TngdE=Dfz
zZ6PB|_s_899m?)}E~Uy(#0ots0R!;13|z9O6;qPg`o48opAwODtxybtzN{AqaU(;h
zi&%6~LOJ45%D0RfJ5Lv9ZTo)n((eKTXjtkB#=Amh4R&T8_49PbeA5q3TJslEscFY1
zyK=dwjf=GB%tO~lf96j3Dw-At>Q_eWIJ>Oe7C(7lc4Y+n5h)yg%1mk{D+qqrQf1BU
zx|GmwY%|5PpJicw)U^<E^TYL2Kx#fng9IDtRA;Gtv5U*dU19bqn>i#*(9GmFKjn{K
zL$S|2`wyI1M<eisckh~bj3R_5%V}%r&DN@q9xDSDnh3gD3NZ(cGN6|HEH<{?hlB4R
z<5_NO<3NP}+6Jk)RPi7%7_7i9N=;wkQd+01MabR4q2ZhT_<QOJ19m3d4E*B^l&Xg|
zSv4XE=~rW-kVDR`$n*Cez?z7o(B>x*4I_2hFV#L8h-F5w5FCMaVsWhs2Xs|ipg!tb
z7Z|>EIjoIEqkhIW##Qs1&<*4Osst)X8d`BN&_8h)f~apGS*N~as$W21vNQ=g>IP;!
zDAF=g`(?&B@5!)Gt+MV9%KHaAE^vhg$)&P`Z$_lWienp@QHN4-`VA5I?z#Za)rN^V
zlQ<&zT^vNgY(=php=->bOJSB=xlmG=q1Kr+E6m|?I_Od#V^G0AP;tq0*X^RqQi`|>
zUEPajunT-GX=HZVb;+%uS^*xWW<xH*z;^+fMyKdBr{cSi-w$*a=fmAo-Q0KlBt^`@
zTP?DVFg3?nMhJD+(HCF?uU>7rO)H{CcT3gnN_w`-Kk@4R|54fC&?!1$wp>hCkD57O
zybQR154PLq!E;j_kl*r@)AD?1YWq?wOjZUDAuk5f)95x8FW0(53uw$?UiHb63+u;X
zhi3>+9O9#XyYyIESIY%Rh?FNudYznk@gdjvZIcvVzP`>aRf$E6%`Z-wGw_&Se%rdG
z9mGVs-igS8;1FBpPTA%c8PptH{l3hswJ~PN2uJLggE9y_5d2zfGl#+wC_uPM7gCYX
z`_&xSZ#ksmx_iHmxV>GodL|HF+;z9~H{d$i|8L$=&uO*_GeIIpcOalR*JHNM!YBsN
zY~?9I#^M34y!%!o3yPmyzyXyJIRO?|gR+OjiqQ+F5eysK4)L^TE^;B@q}g9xIIJhM
zG(Lnr4$Rh_iIuYdWw!T4p(e0PIA2>%!#?z08>?CWJjM_^5|6jbAKK_)4hD^bHxK>n
zq|vR6_Bf&ty=Kb<qZBJh9igQjSgM%Dv9TM!5o0IrXdLkJbUle68R(22$>Hh{r!0qP
zkY!~6xaACnRF*a2O>6#0%NG3Rv%CxhE!L@ebH1MD5d%_(-=Y#}JlB~|fGi0xXKJcG
zqo__y+c~SHgV8YvyiM^&CDIBmhyNq?<SF|hb@yPBJ0Sfaf2CrZMicwF+`^pO)Z`Ft
z6CTGv%`Bv%K8D5=RF37dTlEFTmDrsgs^xCLIJ~9>|5H}ANCSBJQErZh6;jF<5OUZT
zrCDi-6^q?iL~0K-S>vs+xery8D3&$G09&to`qnkrnF@%UDkHXgY!_lD|4yc_)A-^V
z$n4wKVH4Ylx+ITcTgAB~wdRZOHJSFG9<^fL^h>TQuOVKGTXRp<6JHgN;x_-X7M8#v
z<;jp*j!N*2uX74}!l@+|KY8F*uSmTbybE(!8yx>3*G5di3ZdU!V4~@FA?6dv_qQ;K
z4!cCxn3|ivmTX}9j*EniJ#}Z2X)Ws1EvDQZvbnzqD=jdqXK()3^)=G^V%L3x{_8NH
zCZO$=c1eqstHFL1Rt2`i%8-GlOOT2n4S$73V39DF@#ZRH7^!#bk)(+BQU}IfhVdm`
z2u>^#HR%oo%^g(7QNUr&<pOk>@%|q%iABKFF1OF1I|1Ji&wZx$Lh>T2-tK%k(kIIH
z;MgJ-n4Q7F&o0?QmQBvK0<0bdy#>#yPs99y*;*aCi=}wWk1)Y(&0U<uMLl(hnm`u^
zI7B~OtY~+4KzB1ro-dOEU!=-6;R-%ypJSmR^LAn(RQMf2E>k*$DnM7UmgH9dVnTcH
ztoO40m_W$^9J`_nIZ<Lp@JJV}Gx)GI<eD2|?d9P95<CvS^kEi3u{RNb*=iQxA01S}
zf-MNFO?51pDRAwsS)*sU$5POIhZ02?fj3$Sn9jw-aBcK6qeBc#s~GhiZcG70ecHM6
za0R~+p$U2wDO_>5037UXQD1pO8k$^`{hkfg#cCtp7O8z*P?UZj(R2n3ml6v}K+*91
z<tQMH@l&*2ME$+lY`H!$NKw#~+eoZ0@E90VSJ{nj%h}HJzp3Nh)n|PS-iv5N75od*
zs{dqM(;fOSb@#m7nVVJ&R-%DmE5#vB|4J!=SuwL=h<<o=V)p6R4VriTIub%$`G%&(
zy>taj;ucI&JjaQm#{9yHk4>h=k`H8h{U;mr4hKk~zILvbX_J_rn`UCGIlLXp$n@ds
z7p8dEv#`aAvu0QlyqsUm>ct<<SZ$d7^xg9v---p(3<Gz>H6F)Vq;7$Ve(<Y$&#g~l
zuQhEQPWLgwSF&Mw?d|yF%)c_TIi4{t@g4rS79?z5=_+G`{kX{!NExw+$#K<Lh%0lX
zQYp{_QupQ7bk@{m!$9z8+Rrf2P_Urbe}gX;J7;}fz!iTI>}}SP8md+~UpO?&Jxh>d
zwRCv6HkB<1E1>#2I(yO+<=fkg)1HLnv=Q~-!WyGe)e7KE&2M5PqB-r^pM_#0{q8P{
zZQs@M`E2e-f8eNZ7xFh4zEX8<^6tsUE#|QM4xbq5Gmg4@RrMaLPPjC?16-+=e4gq{
zz^5Qp@IEx`x=g!>bq8PiH5Pv!VrG&S0W<cFjfbt&^+c?S{OD=t&IZZgYszXzCeu#a
z;!a*@WUYpTN7v1%OfWz}l&=pOIs8&!C9)&g3(VZFv_dOz*yMh0Axf77;|}13tOq7o
zTZtQyeTk=zi6UBdX0i;F7E<6;0koKoBsL~spaOur2{pYVl6qO{Ty1=S7&URh0bQ+2
zPK?Os(U=!9r#?Ha5CzhU=D{Eox)RKin6J`KilSq-R?1?}6V=5(;yJ&^>?h3W3fv88
zU`XJk{C+H&T880M0{TYI+yVq<TbpMdoXVCiJil%=8eJ@UAm|Dps1D{EtEnl_*qggB
zVCc=(S#$G(PtGHmCO{4(Dfm5)!*&uwEeMv%VBYYRNJ+qc%!G{8cO+cR0WR!WulbCS
z<*Tj9?nj%;$-2Yez$fL_XHp%Qip3tRBv)isf9|(XY@1*1IF`_Cr4=R5n==V>XtqPK
z@Q*dPGyZHOew*>k)<~O7!8c3ZVN#W|tpwpeYDr54nBZVMwgK%eFgxsR#c2H7&9Xat
z$eaKs53{YBh#3rrut>OdUd`6Gv$T%AZQ~J9!}HnO6wk-wp^co<jT9FX$EPKyhC+v^
z2&3#F2^F@p{zL;0eK-`t1DH75D&H1!usJO@&bInQN<8?IW09~Z$>#n~q&jnp9#gw=
z`oX#Ht=K#dZ0X2qqzBa0wkwISIgYGGBaJ2j?KI|AN#k^bRl=bKwyH!a*x(Ly^pm^H
z8B1nxb%D5(3lR|;BFEPOqqvBvH5v!dwyJ3QCW}%vSQA`dBq1tKmY(-3;-&-=)mqe{
z1I<t<AW&xjI8^xYP2{lz-G>RiMjRo<Pv{wU$W7W(-jXAPtGqM(s$v0|BPq2HQ0P?!
zu0DR{-jQ%#vzO1p3mGIWcBXnD=GKGU8CWt+AT5rf@a5vxF<pTU9{?A0zFgT*5I3fP
zF&;r3xAF0Vcw%svOX&m&i3+Yyf<lF@-6xH8&@yjNMPe073=DRC_o|NW7{%$KaKR&d
zj*9goB-yKuyf8Uq&eIaa>QD1?)gQC>g{JBJNs@V{hGobpZ_FHDlHdREBEwCybx4*^
zy`lb5bkY(SvfMgT9mL%yt%LgINA8N<(wzip>xP4ld1TGY(m6Aaa}LHEtl;@iyd<&b
zzj9fk{id~VHL9_MtaJFyQbmKh>XE*Purw^u0{ByA&p&v%aq}<0>6M`50#Yk0R~q5`
z>vb?>7pbY01+ni72l=_c<H<jJ_Zj4+I{zEbyPQW>pmBc!v+JM0nLsRPoM9Tw{~TBA
z!fX{VBHj4;itJ!ZXGt5R;-Kzl8CJt`3*-4cpM?DNmtmgfBBGD{^gh#eGuaI^WDkX6
z6DF!849vF55_0z+oW#s6vg9;zJ=n9@p2aWnj6FPL-tymL+LPaAq@0Rb%4-DZnaI&}
z2k_40Y-<s}?ue!`G1t39jnv}BNz;VcRtd$LyJ?M5?S}$qTY2D<|KMbpZEbT>$hZHJ
zZoYhICgVdO@lmafzDso*7{?dp;+tlHP}Rqtt7;@L=@T&;bf`_Lb@UE}mN$!fC-Y`o
z>=r20aYWwGOvZvBuS1)>4Dh@dNgoyZHlJmNJV_X<V0iF*f(=$pYvv?de=cOZSaY7r
zRW0#xRE&f+6KjQp%D@Jr%mF<xL3r!|W~=hR^2$qJAu+NqP%aJ%iC@Nyj^k%)Ht(Gr
z$A>vRw+qBt{IGTja!G<ULQEyN2UL!fhp}=TsgW(s)}*j-3CrG@T)}3cJVt{ZDO{J5
zEW^Kv{EC<-sC^kVVjM4iLM|ktfOh0asy^U+wG-<YNwFF?&Fch84mj}ph2UsdS>}?H
zoTeKIjzTnl?v2mlc7spo2oAkN|3y9q(UtHQ_IP$~9|m%_#MGM<!wuqUFk7wmbxwNu
zl;pd5&|A_@n){KAhO2^m*Gj{jo{GVVOAfr^C5d@fm~E}^!xG;raF{ByN=h8b^vwLP
zwL!!O>+4h8_t^aGkLKlaQ2~+r;P2y2%Gp*P*Mn83nR(HFmz%{Wr;PRA-C<V4!R@;b
zLy@GL!8u<3y^L?Npb~MKxWR~&mkF2@+=*tZ*?4h9WhI#<_o$I!>RlMt2pX1m!+zvw
z!5Xob9mUB4Fj94qaJzM2UfEB%aA#`Dp@~ZH>EBE8aNrY0ARtPB-;{eRJ_Y#|6uaOJ
zol3dwRU#|;WJ}S0G{p^<^r(K3Fq8VX+-YbI*27q0DEIWj^WB}k5Sp4_Brd|aM0lW*
zR8zBO+EmR}<X*=jVTI4U3T?*$RH(PXZBEQqbG2{Lpfi!lmaXe|08~IItnJw|g>|Ec
z<v0szgvEv+DS>`lhK6{SA$?IA9dx9RpJM`KSd7ua-Jf7!+#yPl;!sFOoWVh&Ded-#
z^u~YhF$b$lowRS^kUVVTOo*EkyI4{ODb>px=!)6lEsR!x6n2anOeln1sFk}N+%y$k
zcw9~GnQ||K@ZrcLOOGEAqHlL_9O9vl%!9oxE1{nvreO;sXE0xzBeRx3h8c!BESm%l
z@6EEqjRU`lNnDa%25)W}u1F=VU$=XCAqK@}$Ys&YV{0r5P0Unsf^m)(n$KBc^ApmH
zt<%7hgDbwT(*om$!+G>yaR!=6tTS~n;zE)P9&3;nKD1m%gh8}PXI+vv@CACPlI5@>
zFpxHn0T=XokPQ=6EVhN^Gf84`0*Ogh98xmfyffCaTf7gK*!loJ)^G|>FB~Pngo<eg
z#e;VMER)c}$be|b#v<{=M}TZoix|EcKgVG{{^e+<g)7+{uo~848SsfLy+Z)ST9V8_
zemqXVg`3T^SVYa>Bcd#J0?Gl~%?IfY^!K~|=<hZ5`&8`r`mz3T=5M_UK?MO&Q%C*H
zI9BD*3~*o`#wzp*p#T`F_qxWgCNrXBkzkN35{{!lvG687eeRQ>&<S7^g8v+IUp56h
z9X$BE0&5EJjte_mcscSNi@s=+>=g2t9qAT+c){`&Xi~@Z_UvRe95TmC5xpg(o3+5K
zBhe~ys?_@~kVhx?x(&7xJ8619Nz**Uda{V%SVNtx4#1IC!4Hxc4ty6wMg}SafI{NE
zM>$$yc+MRE8eIkEOTZUX08ALa$)XF)P_tSEW2(RvW;4@17KsJLzR(!QArRIl1&gcT
zS0dn_z@>0tb4Vgttb2nf&~0Mw2Ksv`fEDDjJslAFMntxzqi?+3l#BO#)xHHrM;onT
zMR3O42z@!3T2ovb)70y2;M_A~7_PhslqD2U*9(8|GCiS1W`Ms*ET(o!g2A2!mID`a
z7UPEtcynBVwj9d-31?#}rvr;IG{$az(Q2#39c_LPy$Uldn>t;B_I7jJwJ9ELl=I_T
zR~Y%+r@j5?fNcH}KGksrJm>Ipu8kT{yE3ciUrjS9UaRN7WSH8i)@U~Gn#wqZkYSL&
zjoo^>EBB#C)661sg9?S21hncC(8(7EKDgDRxz3tZ;z{RNQLGrWkC35ZPaIqx+#(q~
z7QfcDc&RR3L;-Cm>iLU5YRv0jx@2ZCeMd}!^@r8Q4Urf3J(^$PSu*>dBYsyUkT`x8
zoi5ZfE%rruwHm_g_A-Q7kh;YYIQ+;(H3)>6&Vj!PO(UQgUTkT*Yh_f{{!hlbf0;dF
z8m+xCe}q2k!&s3R4k>j^G=dy%!oCmA_{)3hrgoBZey#Yu4wq=LH)zAmqQ)2;SVX;2
zsL#RZY=*!P$3<D>89Kl{Js`U?>@%AZxCv+e_MrkW;PB&|Kt&MHg>qX=k}UA5xu}O1
zDSZ<UIAFmg{EY_IfgayYrbAE(S(r3Z=JY}{4M{Z4(k@wqI7yOu<^#W^$*Nw^)UppP
z*q&8iOOgB&-6?5uJ0QxUyCcWYuY3T@62Zf(WQH*T9976&@H{)XbmVe5B=j`!I}g(2
zvoKZJ*G0ogJYt@Ki>f$OogjK0b~%GPWzljEDTDa%Dba<Vgp~JKLufk#e-cQxWY$2w
z$d1^MQ;E0mX?Db{u%!(GHS#tT=ZGGe`@&QKKB%rQV%9~hx+CY?lX?#XIBdA(0)KxO
zMh48*O4^EN56$dp+Zp(K)O<ymB8L~H!`mZJs|TY2Q@k8XdNg?l=u{-H7>$c<jyqD%
zzp-kfwJd*y^^DyRYH2rW-26#tschVW*=?>Ys{)op%HXGh>LHxnis2);#h={fTUdvH
z`St&7%p-r3`({>+oM@1oL9A}Pu%xR3Jl~YXrboWzyupN2`=4X9SVV{(_*5mQy-uT_
zz2HN##vlH=&^sKcX@Xyix*aM*62(;>bIQ|R<bOM`LfhD4@Icuw&*dn_(rK(YY6BA!
zA)n!J1<YR|85SzWp%Zr!AH&i6f!S(!KNA3#*m()CWZxORBe+<2O=?T~Q4QD5u`4G{
zecoP$$fMx*lPC;z$Ldx$_e0b3`bkJ68UdnNjfIM@3&VuD`(f<sK_0Z0gW)_vj(e5V
zSw30l@)YLRzJurVnKZoSYd*p&G{~}7oT5Lhz>&qKgV(kw5Be$rDn;Fq(&8V#sG70s
zdx&up00$&+!K%wuUY7t4{N|P_HigP;KX-1aJIjWfh#h{o=u8|85(I?n4=L)!@*aR4
z2x4m16Fg3bxhQ1I0@sC_>2c$H1tXl_K<>F9RhhBgO&A+KFI2=}{~DE0A)$hPHUu!p
z-|}9ElFJ&z+)5ew`2JTZvo&)m&o*SL<v<%dUmcqMne2UR$=FdJb%+qQDUL(i$q82l
z)u|KYeHe)F!r`Ka%7FW>Ypr;$Phy!JYSob2s+|81JmI|gykD^3pQQcXici$;(uuNi
zJQ{rMXNFkpr(kdC5%bXd&1IVN=CqwLcR{r1KM|;Z=S}-rJ~Z^&UNQbV**|aLsrh1V
zfnVW4Tz`s}3FQAJ%Y<y8NUE8wV5Y^Ssv%P$pkj^50r5x<x%P6$2%KJe8FoY;tDBp@
zZ4Pb%QM9*Sj>T)oj9|8PL4YZXjZG<W{XvUGJ-K_oGY|h+l9rRaoEc=2b+ia)|JVMB
z#|(>og<wA)nhhBDC=PANS|CJ&X9Pc$$|5}grqsa=&WCC(Au<Tx4<4}INbNwDs?<Xw
z%iO9IoBiImQ}cm>x#Rnw*t*G7HX6QSW{gF#mf4OygxOZI*2L37M`H>FR{{;oumhSn
z;l;xiLMbiWd*9qEM2ff)Wab`8u&727O!8uPw9j3l;R`gu>UFFy=(^ZaDgssvRhk}l
zF+~aJ@(Kdb7j2s{dlquGAyamd#K*n`4tKtd3eH&H@77j6S@h{w)Nb-?O-IdfZ_-Qm
zV|C1uZtQly*K5V@&@;^eXLV>SuN)wdZuxPm+iZOWXouejz+!9exaGF20)8%SVZCXh
zBGJWYu)vu>;J}Hj!-_mXx1$n>Qgu^DaXadcWi<Q2fcg^<p^A38*2;CK57CODXLPui
zlSW9-JI98|6B4tq(KGgLrpzH5gp7{D*_|(4wP1H5#w_9Is7Qb_-oZ5>Mpi8pi^f4T
z9}I>aEHg9*9sMo;%L};U4dB$7-%M<W33paltt%b!jt>mS_a6O@3?5P^=}9qpaoMUT
zxfs9R*q%Aj!uK!~Qe3U~R=5gj+Rw5)OF+^;UBPPMTB^;#{m@(3v;Pwb%-g!et%xza
zfU$?akfp*$hlq{+&Go2DMC}fiQ6%Nd)!~PnaNej>F{SHoMg*3NuIjuSVsHM<+<pMA
zX}<buY=t_Os!1b2WGwbLew9GY>h%MeIr8Ji+}`#*;QepSXm974-p@Z>uawhXC+eAP
z)$>EEJTY5pA)!`=Z*p|jzbg@8&lTQmO)Zei%Iy2_c~t}wo-!++dui_2oa&6aer*F$
zRUp6lVZQ{KX6rqaF^X?SvvoZbTP3GGPU9ZKY^%zI54u#zY(2G&Ck^up+c0g4(rdDM
zEXEI65%4<+bbH1UZFRP_IbGpxPI44$<=yKkCso-H*W;!P!5{=M&VTP0z6m(61HTS<
zfpo%sd~A0KU8G4_GknynHqPFUYpUIu5Oi>-LfQrRDeo!}ibYCaSXc27skR$_wzX=8
zRSNw9rIFtI?q*eQOrKCG%F+{vI1?A4Nza)w-)UnVW?L<>5k?S0&2sx~-L%=s=E((s
zCMpI+&a=PQEIfQKOrVPcl7MZMf$W1wbV4o2O_<nWR>qZr<cgXCFH$%j9M&P~$LF*t
zq!!{GFI8XzIcx5&=94ZXl~hSN#x!o^XZJco5d)&)t@t4Ltr3)Ql(U?Le-WDHlm=)^
zkML3fq@-b4u`w@^6VFZ#So5YC4%-d}@zKr{w}Z34D8`G_3sAc)Pt4ATF<J`mC|;~v
zVKAy*T;|f^WzNsG%GKFEbJL2RJ}|gU#0q{s*8`{%C(~rUfVvWY6RO6!eLw=V1yJ93
zUs&gbEP!y*Qx6T7Dru=;qUTf|{=*vgtSKM|*pDli4}A{KWJ16Zo&N7oVodj~Gr+HH
zG-lq2HRrmwbq1TrUt*kPR28r!!eZ3JYL&HLZl)22wR{NcRyR4NE?&4K8*k{aAAE>y
z=s=c8Af#JPoHM0vQ~fI5q$}?=hjd0AMrw{7#)6?M=SY4Eqgcy71>=OvhEV~mt{Bu~
zOBp=~1d;d%M_sE2YtYZN53(+rS6(Ii$`$NHOyE*D(CA5ob=(AswK**~F94n|U2FYE
zE>0psm%UKA75)@bY5umkfTnp72w|g{muI7Tn*LW5i}n`%-V(mCpxz5tX5~jE%eaZ>
zJK+GNx!zF_9DE1fp9KQ{x@T4J-t-&I1yPKqG*38-RSX*pT{6fC^t^selP{Yqv6hq-
zYXaXD4&VTh4p_*Iv#t3v%)a=#?Zome$YXZS;F_f^Uhy-aCv@lIG5xNMP%|2QbI7#Q
z1*AA5zRp};*Du8c2M#P(;sSWu0^uvk%O-y0F+j&41fHomtT9w^@j`S*fVGzW1Q0$N
z4KUMgN@C#*gE&WC_Oa0qW)sfiXX*M2TrHZ2afKj|(I3Aj;r6M#^T_W-F;7gNZL2L*
zEvIq-P0VOP$24N1UEJM{BKUxGC#a_Q-6{5(KQgy`uJ(HA-QB}fnB8>6?N-d`#E}xb
zTr!U$2A|2u<;{jjha=tBxJZ~_moXp@&75|?B-m1G%!>sdVE|-ve+<PN3do!XK3!%$
z?Md_HD=ZaL{?;jCB2Lejk{LoDIjpmp3=9H?ND|U=!S=>9BLY14whm01*5{tNkK?nM
z?t4sci+dDbYs{Z-U7K<FXQn4X6*FcI#Wqg8=E`KKy^K;0Eo>dM{v;?AhfhM{>eBr$
z&5VUlWgN91;jsqt!I1+x?RnAr86F7Gj5@!DVfViXJcTF;6fISz_~`?tre-UIPbnl?
zNV{g5AZ^7Hx>%G;A>;bZf4{GZbi;wUvskTz@BHGz6HI~}@`>5n#XRZq`vaA3QHFJ+
z2l%-bxP8>katgHv=6?xtq&<5YzoN#oCea7p;+3RDO|A-CY9&L{oS1v+&esf*><*$t
z_y`B9i7|iRn{MPVF<W<Mn#o$7uFL?kPE@vr?$BxoQ<D_XtY*R{V95x6ons}ePP|a3
z9sZRb7fTKIaze~dXax#^t5Wu1m!MeYI{`ghC$hoPQ>Et;6HpYcU<iT&gDt&;`eBoE
zC7=VouDxIt+MF;FFUTK8`z`AAiELVH+7Pbb97bhPn09CAHjP<e`7A_G<OE6u3#^c2
z*(=d7)~KAQ9`|-WIK!YqPp(PW2%@scOwCg25IKJOksR7J2yn<~I0y(Ml?|R05+#Vq
zyk~OV$${$3@rnVS#>1A*#@u??>moJ?yV*Hp(jrP?bm@tRKJFTE9E@=Ebb;;iPrTbX
zur#+e6YBo<sNS$k)V{qD0}FqYx)7IO;<QCI&drU+5(%}G&%;RN0wZfMw+h>K8ZtSW
zAI9F+<c0DoMBI|1-=zx(nPdo{lUB9`8IE^i4N5q-08!VqlcxU3g^i$)4dl@Ii`wyE
za4@KS3(LhExxaqMd0Kw?Z*c+sYu68Oy-`pqm>(2{(-VE#pZOu~b_M3ED7Jv5GIc9N
zzO{Xv%ICQKn!-FvEh--OP%f^)V8Tt?jh6^(ktF(2Nu5d9o^Z^<;1C(=_}GEjLjO=G
z&BXoK^k@TlFnq(2z7!WDApD#kZRC>Rdh_f;_HgZ*<qWgnt=lo2z>|c{&0n({A&<ch
ziWMOV>!4pG?EH-*T-viF7;~`Y^TYbnxl)L_0&oi}p>>VE@YLU&hJ%RNb^?jgY$X)b
zDfFAtE%ujx5ufgO<Z74e+T<rOjKD<lxA>x%ryh8nLhjO`pivCa8>gphOD%&F00(kd
zn6@e>=Hn49*4Um6FR9o3Gt5xyhYMM9(|AI&72hDkJQ_cdjCU&j0gnY0)WDESr_!N1
zu%QRwQ)js11+LpZ6g9a74lL5Gbvh)2856ks#D9PZ8YyAAEJJj4^FzS6fE8$ydSy;)
zO<~Ln%zWO$Vqr9-4pB%{vnc|@;b*p!Fcpvs+wqfd<N!OEt&T24bbq%+VUefX68Ig6
z`}Kt#l!=NIsWR+sO_OJssdZwhV-Lg0B{9bxJi|Z)6!+4=VbQr(3P0($f$#((2i8I>
z7Q(vZAjS=JnU0d-z(PNeQj&sb*Fyr4uthe)w<$9!l3nxZNoZ^tL>?^&c8&K?Gw(0)
z6OZS>T89y|{@PKmI_Uns_LRwr+YyH&IjHAUAFS3**==dGuBq2MqmX`-Nzk(a(Y?nY
z(cc2?RxVS`X{+@rT|<wU84Ly7-)ll&%q3srYZ}$#ogZLtNfL9T<~B5wF(A;TNWur*
z_+4j?<HV#YFpsssEi4ko+w|@0i%4Usc`#cKEj*bd^1!WmJe<cR>Bre#;uTz=r`;}I
ze%!p_7{-h*n)+uj!KQ1GPJQbj2P}pIPlC$V5AgksTE+P}6utjl#^4;EgqGCQM6jNV
z<b$J^?b)3;@~9F}K`Ezn|1CKeUNezJ+I<@Fb64|AguvjJ=v4dLQ3%XdV;@@I;F|F|
z7jHL!Z0cO;qcx}M4*G%6F<W62w@$xTiD#dQ55tDR4feb$<utIEJs0^GwpwGT58h71
zv|i>KU9+u}DmpRi>gXlqB4M3d-9puI_oWsKVW7M50Arak&4uT0=oWxZs@;4riv11J
zD1MVy%~P*}-@ieG>Be4R9k~#IbzJZ_3Rs7)eC|vD<>?@y!Y3Noi~-jw7F@3%$49Fo
z2-Hh#3=MQS&dHx;vyObukQ%)<cNMm^!@J7x1iCo@F3CczGvnPI*Vm6DkkE+@E4zQq
zlSrV{O^(6O+5%v;K^-U-@@057jrF3p5DFH}R2@eUq(uq`rL7xW6@FRs*82&ViDOdm
zfGl<iF4}_`#*}A+fPK&gg>@W>=e>v=zcoJ#DMC<wKKmnJzc9NDGO%3w4N77%GX=~N
zVl<I1-bP>`#A2O8?l&MOzq&Lrym1zb`$6t1WBSGxzyZgHPw~sm3PeE-90moNJT7_Q
zxn(U9ldS;E%pd{_4t+Z*h_I+AVo?b8QKU{VU4x!CSHd_JoI=u?h~*CjEf$iScLwPI
zQ@m*9LPfzQ5q|f@Dr#~m67YZruIFI3P*y{sFgRZnq({sm*l3MWJA>zSY$5{5d3INu
z(&pMTRul*^g%DxHurzJFIUungg=(S^ie=swxmzl!RzkgTe?N?v065zNmZ5F99)b{{
zZ2YPx4l)S?7<MN#d7)&{*5bVjV1%V73KU}T7$JrOfld5IE4Iu%R6@rbSZsMeL`;Aj
zu$iM%L99v^>8voQieu>^KDS^zS?;?rmeGlESocI6iUKC4M+ArJ%OFX12jB2gtN;o5
z*InooD|YNJV!&#!2(Kpay$)|9b!Ip~FB+hd<G9QtRZB%vH?xpfLlD6hcOG1Cfxt}J
zOsD)Do6VNl;7gGhle&XQ?E7AhltZBAe6eSkJE}noB@lR0klxQKvg3Pw0wo6oK39gS
zdIYNG`=cQ>xQ*VF73s+#)C07+k}Y~Y?unPFp5U$lpL>wzobXT)z+u$P34Av>fOnZ>
zAw#-N`~<&Voq=Xzp%E@ho#?`04f#vcSk>7s)L?Iq81Z&K;qxAxXiQ_bpsaE=nz4$I
zm`ANKZ7hu_=A5Q^GE0p7b9jFm%2%#GIVsTJ8lpIn(>k2byAyUJUA|%i+vYHWy9I21
z{hZf3_y>SBx=`^Zw87`_^+)$iPy5J*_{pIGNyjb9@qyX4<rk;8G_YE|7bfyMr)tJ=
zEFXZ;_BEZQ`QWYQ3XJ~yVFEpmg)7n0V-WhE>`xZY{sVeX9s_gsqBCdTi_=~-i@_J(
zpH36$PA>V}$2HONqsgK2082YKhp~wz9~}6d#ifB&<SKr9BUXhrelw-Ts1<{KABUfr
zxe|lI7t!D%d<K(sesd)kpPr>$KKP<yUgvyJ9V8aZ#6zJ$3M^D~l;=m77fPU>JNk6t
z<V8Q!#P9^j0kn}*TX@S=0IQ!R60-I8m0Tc0s=R-tp862HVPRrk%pvMDm|fIh$hI-Z
zE^kIDCqaUVoR4VJyoEqTXmMMgZ?TbA0AH-$PbfCVjJpdKQ7(yaMPLO;C8RJbJA1LT
zBUPh(MwnMGdr6YN5QF@9udZi4vPB^|=2jW%0#dsRdB}E`SdTu)M@6}=3NhXfQn#x}
zz`@e~P-f&S+=>2FPZzdxmsVKj9PYd#IPz7jX~siyT$!+m0iS)$8b9iA-TKpl@yO^n
z7lo;>N+A9)JYwd=EC$3-CvSp;ZSbp)?6_HLS!xMljzb>l*&YW=PX(hPba3}x3T292
zJS!+L%M#~u*m8-};tjJk77p`6M%={^@=Q_eE?GU@Xx>L_x;W_IRt9$le7p+eMOPB{
z0z77foP&c@XV#Zo;!xpR7!RKMwqe@LIwFRGDj6sB069!xx<z=IHW}!JWQBsrdYyW*
zD!IjZKkD=**d?^!>Up|h;F#cmFbJ3q^D_zaR4*Ja`CYR6UZZWF0;mY1fif3KATnV}
z?1$s25gl-lJ-85oA^w&k!k`*dDwf@<AX&}OaReAX#W9j?!vwbRQp_DkvTeBjOj?$!
zg_6Tj&B;nPNe;u;$h*&;C6cl;$w_6kIQf{f#@v|UTia-}iW)?47is{ifjM<7LsSK5
zPInQt-^gl|ns4IG4PcY7WZK`;Q)r#9oES3$=;OiFXH`tR*y#EGxR8uv$)33;FYdjX
z!Ws^=Z*|DfZs8Hb^RYr~7BiS``xza|w;HkU?M@4Ev`dy@<V?e)Dei1vk7E5sI-Ghr
zRjD$WbIZ6ta@OJ}pZgbjvp;g-bGabwBeo*5iTR#FwOjt4-oh@KgDsX(WQE#~dK?Zh
zgCTc_e;uSEH~-x_RYrkKcJx7j^(){C0~oWAc+^i)tiK9#yMN^bW~;j#X6qRaR&YCG
zCE(IUcNx0sWa<C;(^#j95_#jR@C3~#t_qAO74do6?OE?YY$y1BhmXSOe6spYSly<U
z+^cn>HyN7BE}g+9NS^k>LrT-x&pd#B)3GFn+3IMv{xhyW<VLzG;5g8jpSrE#iRZ(|
zl8#oiQ>qj(GL0QM#nYTX%&UWf4KFxoSBlXoukT$?2Q|oj|GrDMe(6&a1<Z3ZIcSoV
zeF$+57Le$bz9CR=V)n3;FMRw@k!q7E+0lObfW?;3DpwM8=03{E@1F-6G&&?T>n$R_
z@FFxJE`}RKV5z9COGBSETfONpr0`jjAJ?}z<_Or?sY4j{0%?cADsyd`(5pLaehInd
zMG&$KOa0xBXBRDii=KZZt|(8s-)zmwcgAXf^cc`rkkyzH2ur_1Z5Db6qL(>yW|<yH
z)NGc$GYkfHX&~eKgN^E;MRu93DIzTI$MsM6UBIG7g$Es$nFWFH@&gME+&Q^f0wqOc
z36?%@dVuMn$@Nm#C`KF8Hq^uFKnA1Sx)*bHoGBeIBf?0f+JTwl*#Nj?gXsol^4*V&
z24Qpummo9A6n4iY=1bRW2UOo_Px@g2V;=2@I<1{d)1<h}d_q3}>E7rLnbQl6*@BDu
z{kO@Cx$v{Sm1Ebko7XwU34gQgH(DLm|7KDo&FfI)O}!>GDZi&+dvaH?_F%qW0qB-v
z*{t-Ggy1(EP{qq>&r>Zd3k?sXdz+Yvnl#LZbysIw+t)h7ZFA>8_aQS+gM=ncj$=zx
z7F(>~<Bmgt#l{0HEvR9(@*QAqet0TbXGHiq2jjjUP~j1trrSc}Wmy!MgN}>I90S8Z
zPzfA~IGAuVtbc(Ysdc>Y1pPBVS<bc!nSH_n%T03f;R5X6e@kJm<ER1tk0aqSKLiSQ
zFlezbs~g+v;IIDeKIfPg5zDA0jlubRw_=4EEr#4Q5d7+N_g1>`PmjNsnR&GaINlm(
zH|3pF7_wA!d#YC13;P{sTOVdbQp|-0cDaTFX4~A+{ENWDknO-$$2-W^>M^UMErW@L
z^+Bn=S8=Rf1n^KtruET{zxtT(*EKAPAH8@~Mm)_D5*FG4&bvDM%nc@p1A#FXKZl<}
z)+B-t{xB>cOPu3{pq0aWcfST5aJ>|6Tevs&X$T3+;M+t&pF0M=AFilyIwi;Y*TMAj
zIghmJVBm<Z!>@dtyRi^BzHb@fMaFL=XtgfPQbUl6^qZGM;WOy7(vfyoaB2&Cz3i?7
zl5F}k)$V@R{HsUU!K9^p2a`R0v8_=W;gqJQU|aw8`^#QTos59lG7tguGH3MD3%$x&
zOv~A&NI%f+mYhS4u%NyGJ)st}L#`Vv2j-xWHj<PzF(N9v&QtzlXmWSlv+crkbF2&9
z$J<pK*AT7tO(f%#r-Ht1VxY?v15WrHUeQ5Y!<+^~DAq<Qu3jQnQ<G__-(wE<=TE$w
zc8u;~PQ20YyL(x4y25RRCz#StXng6i_(1;do7dq<AN79KPhE+IaAEGkU~c<<kpBWC
zP;_+_(^JobaE1XXIG1Z4<*on%4;g^oZ~xBWrK_Okw<j)+PeG1Ro@y2nF$@F*Ijz%E
zt(V7-r|LkhH!N?>*gU$7a;?8TNgZ97L$>w6tjiC7E%~f#Um-enfnufj@GHY`5$Fa$
zQ;O@Mp*RV|l4_mH7hz(3d*2-bS5?=-WvSl>*w$(MKHNc9k(Pckf^}REVj*G}I1->T
z$f1i^tsAJ3!{eF*&l}ZRf(XmD(UO9NV2<7FSGn+D7%dh<6T0M>B*Q>+N3mQJXV1_C
zM&f;#uXXgr%1QqOx;e1b9oWTRP#PuNQu@4yIW#*xFH2(b+e6k)gpKFE*fi_f<Q{7@
zl5TfV?7VL4KxJZ_<$_~Ed0vc$zV{c_(+=2<x7XLhrQWE2lp*Wow1$qb2=s({$sYj%
z+-GCZ0U-!&YZjM)z|So+#zFNstk97>vHidT8Q;fb8B&}fo#o}}gI=Nfa*L<0_)97Y
z)1KASQ4$bs9NpK1`p`{?3O|*#4k%g#e9!nW3P_DZIKWxDakwZVcX!2em15OzIKY+d
zLn@e?{~iL1-T`FAUI0FaHT`NXq^W8Mf_P$#!<j%GXx;-qO<sMQKSs+2ZMGv~C`?Pi
zy#b*n33G9d7v4`~`0ILZE3_l^xzzbr!(||?4kBk$=TCHG)ztM_;Q@1L;<i&`MSOn3
z7YrcYhz5A!W^mL$dUu0xo4Z91!`DIJh7nbb@3C0RMCDU;-Rd%g7vK!IZjXn6!!uJP
zWh)-=yE&E-$Awn{*1GV4{1YLc1_Nh|%9~yf1=<6w!Ep?6?|T;qmWdkzGG%y+Eq$)!
zGL*QACooPdk2FD_9}5YPC4TUgARKo2WxYG%5a?n@N%fD&!)HXN$gRK2@^1BZt-n8Y
zteUNDMjbG(2DMB-ay0~?ln20v)6N*ozxthAUz~!NuFfoig8>=XKi)s@*53`;v=2Id
zzeAa|bx62Y&LuaoNWv^eBLOV(SL9=6ed^m{(z7#A?jto<4w#?`$y2{0i`2WoWA4re
zp5%E%X=dC<t(iKQs;nNlAuH0Ka?Sc;O-};FajWmwEM$7?3JCq~)X5!QbC={d5c8Q`
z3h?OSwt>-oB5gOWjkz@Q-#QpaZ(w<8sdS=u@og;6)Xk^Pn*~b(aFb7p+UNxCOm=IA
z1*GdREI*DNNx<CuYtySNBsJ@=H5>b$!rt-r0|?%hU|#RwJsYr8pu)r935Nj)e5Ekg
z<*9%2`~@VzM<vk=(w^OTiF=1-Cja)BIgDbRGcdqlY~|<w!6f3Y!CT>Hty2=*GVi$w
zXBdcC`kzq^>#spO@H?3KyP$1({_NSje)exn;y!T5q-3D^ueVv{!>NmCs#mcHFaL+t
z6kLErpTBPGzebs%SmTIgB5JVUXTAclT6!W0{X>Dwb)@<mh;_3|td_`-RpA&I3b-9d
zqBq>H>j%p*3|(f-2u{OZ__}2447`_nTVbT?A*Gyr-&C^|v#neL#jkCg`2W^wb^qRD
zg53bcwp(eIz5mJ+^M}3)ZXhp0IOa64i84OFKQS8*qgcc)AH-_bvu>X$(&@xJhNIrj
z|F;Ej64i(`iNAqhQ#1D@N^3RNP5ytNRvo_I?@4(!s^Z+IoU=$?`|!Tw=G?cAWttx`
z@@0NW<bJGa{^MG1&Rmn43v0k4rX-16_sqo8b!0sBu9%O-kA!r~yy))&VYWjXBu(Iw
zkggHV6)4XVI2s~k1_sP;`vCX0>IWe8kWzka<B*Q|o%UkTWiQ#MUJ+6baJ1NOqLIKr
z<7POERLNnsI(V!GFv)9^I}<Z2b@7M?A25$=E5h4uVoJC;h8IG*A3i{Q77g^f%uC*A
z&YiGk3H9))f07vazkSLF_ti5wApV8va5l2}&)N?RnP96!ChvhZJ+T5U_#Lz47Hz-$
zFCAA&T9@=be<dpeKx@|xP#n=9YGupFCefCBvtXaTTM<B$=H~`@SWr-VpQyqW;y{V{
zR0@Mxe18S!h&UEd0&i&pd0T_h2=&zkI*<zf&SouO)`_SFxv^0BWGN9H8`YbBwNLuE
zG4|IuKH5x-Q%)pHh!Mtei7Zr{-Ua*)XX=H|;rBFx4fg|4RD=^<bbKgb7!PUgp$8zm
zAV%#R<eMFmaDa#TWQa1Gm@EC*<zbB}k%K_6fON45W|9bBGRp)mein}Mo38qj1{~fL
zfOV{4;h{8Gm6~WCBY6wqfne*a$R~Fo%4r}c=9EPy%f8gQxg8Pd3yi))W`vKga7gDL
zb%I#KWrXwbPuF!V6tvrXTIW8jaT>6Avh@y{3{$|TPh7?aq&PF8*%CPX^rhtPfr}Uq
zkHeAS?^RG)p8(g?Y#{dp>Hvl-XqN??_Q1?7eyQ)lk%)1Qw_#e&<Y!Lk{V_NcklLBd
znwk;N>XV>wg7A_bLQ&5+Y>pGbh^2Kc9FGl-vWx711Pvf5S;UZn3+|;jxU=sv@ctF(
zX?d^pj$Uhey?|?J*_MxVu8YoVkFvW5J0M_<d7nl*bWQ`E3$D2kAN99^aS$)8Rk6>S
z#S*!Fo~C^LEl5l>*gd{}XiDdTky9eHVA;A7#3bgGW)b2-6!2{O0fOcrZF&x|g)Xv&
z|JEBTg;NreJzcPcg3#B=hL#tY>3HA=7n~7*^TNUE;UwXdDk2i!H%f9EshDjg;f<g_
z31MSPl?N1S<!YZxK=pT6ERJN_NN#X0LGF3`Xy;~|(^eAwsN_`gnqp2anA1~u(_fM1
z7k=^#EKUgHJbOB~qBE7AMF)O9R*C+Fl~~Cz#PRRYo4mko_Z_)O{+bVqg|R>5u*wcA
zey}2X-W`MJwn*^{xH0T@otKXrXCBP5{9D(<p#F`!jrmgyrpf1#s0VIY=?RVykp8qD
z?HCCuBnL0<gURrI7waPN{UI?;VGOKOvq<X{GT}cJp;h1m<sW>9Nv_+%#vJ`5<b7Ei
z(`o4690L&#@PR>c4`$*rt>Ahj6A}#vq=rc&=E<K;a2U{nY1J-2#5#!Tw8lx^dUn4_
zY0s|R{d^R{>Ao-5>ggXHGmRgU{LJQ0d=%!#dlp<Xsi6z>Ok*nvHcwW~(*KL*eCv8+
zuKO{!yu8IDB8>T^+0>l7cg?vsAIkIE>w)>Nx6PV=@t%crwT1Z49sB>OdmlK<j;h{w
z?R|Fl?CI%D_Dm*86NjX_(+N!&$jKl041Y|jI~{1^T<u`M7(+P8%Z&liJIWt(l|XgV
zK#Sqp;l<~`<>~>sI`U#1F#5^!qU^+QKhc}VXYfUh%Db=e`eIbTdH%tGfxPdpYM<_&
ze|=6!<l|l4r*{2WwbrUtwQJX^s$F}mYX4$oD+h<iZS>`|-5&zweh#k^ThA|28T)yL
z)(WU3P9BPx+KmF6fo`LtXepuxPM%0gdQe~x@Iu=1+_3g73k|lnzQg?NDt94fYf;_3
z=$jRFTK31eW7#D9-Vdo>*fw0oBbmf@_ZzRk8a-F^`a`E~h0ZI_2*oZ=UW#>0$wr#h
z)~ls#odi`M9JZnV?FE*(ddq|F$<XAS-&(Dr#);Ql$4AfV@enS(!yb|*_1hFYJ<Ef?
zF>PILLx1&LZjXLnZ1~~(hnQ1&sa50C6odbzkA8#32|d?-l40P#FN2NV?$C%7!t})a
zMP{MH3*E<6pqBtqc&<T#zETNEa2%}^o!r!HF*=d-X~5y_1#fGRVU?Y~Y7=KO@H;{{
zP(JrNc_DkY6FcHRevj9itPz!C^k`+bG>q!EA={r$`zE;Qr5pbAeaqItbXEV~thVZ-
zk}81X7xZB8*$rEFZmqAw@_8GP`4;+rPU*0b?K|?rx#w1=8g_BM2N~w6kIkXVXRoVw
z+jZgPrtURZ{hv~XeM7sfyQjGNfw!e24KjQ3_3_X~Z_HQNWvZ!fhOzg2VzQhHJlOqY
z_I&syU2o3wSxlvTgR@+dO{xJV(j~SzCx3`8t)%7#%CIsW1C4T#8m!`=w1*N>br2j7
zO1~@ho?7pVVlWKBTuBhP$Uno+6%Kh+ZSz;-JQRh)!=pxX@TsLoj{+x!6<g$1ThMJ0
zk*{SWkdTXyvUVdTJg!p=6`5eVxrTT?NpS{3-J7CDMd;fHRiG{gWtR}W-7!fcbV<80
zdp0YnJ2q+F{4Va`5La3A;Y2$aubrEd>W4!*E&5>QD;o{6C<g$#KgK<}+1bFP_hd7x
zyZBX&$byDjE>-Ncs<ynAW#eEz@3JDq`xB&yG7|A~f}2BC>{^NZf`yCYS;?IygA28l
za}pvWrs8)+OmR7JdPVzxkC9=kk1S)_{{)UpWl5428w8fpL)ON4=ZWK#K=<n!d$^+3
zZC#tSb))q#Q2#GlkST`mgmg|FKSqS-=lD^9!(||0SY5(65qajLh+&$^M(S8HPUvps
z+${PL2?0VM7!9>&Rd3Ops%MPsbE;+h27z)XcP!or!8aZ*(!op<3^Xu0h;EErNBN)3
z*GAqzk$X4CQR3Hjqi#0=H#5&c%GxV_jP2)mAwZp9E#0YxJkRpjN5;p9Pc^0#UU^Rt
zCq<}oKzR|+VklCG5hruP5-rY&3qY%3dMZ(f5gGt>65SX+%IS5@u=0_u?&xnHY!EXw
zvw>I#-X-0L7-B%9CART8^StGVcU%WBjn&)21P3tfwD9V}{6E=iFk2J8{pq+>;e9c0
zUnlA*+&9B$X`0_<EW6sy;^D$t9bRU)zjB5>J580@O5Pa`R_?VTJjX9Fh0JL9xwf^|
zL*PYorT3@fi4WX(-NXr`-KW*okzjrY1^WU+K^n*MDXw08S?;r4GKbYybcdoRwg4CY
zAH=99VvP4{On)SQYS1zEU)1q5L3pPAG&EN(n?q3Y(n|x)nBjA(-MEw->hEE4=Q1ny
z|KDepjszWL8|GK9U@Dx&I{P1IyRp$n3Xj>EOWEONM_QTom<|LhU>)AWAXq0s9eno%
zyJS}Fcr0jTusF2+a_30kK3sNHc_i30>jJm3+B(L^MDuX-l~#QTwRSJzmCNZ5qy~It
z-`kbR<?>0h>FJ%NonKWCUi{6OK)Leq%k%QUllfKtlV|87J~kabPpcETIeuPdYqg4G
z1nl%~Vcnm@ll_Q~C|<D}wQdCwPO(yEU!jC35Tci-M@xQzlM_k3gHx6i7zDhK-uL45
z#-K12=+&{>mb1Ozdoaru@yBDN_jeaUh1qKL;`vsv{#s2O$*fR}W)1#)?lhix1Hd&0
zS}xym_Ut_UK={4sA*Vc8%Z^s!a_vn%1GDwLOilP=FJ=1%oia?ya=+#Naf*Ka^J!yY
zn}rAW6<(T@I{HDi=Yrh2<Jqva%B&o_HD(GQqK7&AQbr0-Wh3wYl?!LAe)GlgiC~zm
zR>)euZJOcZUo(z=V6SJj)msQ0=XqQOdI=yw)VtlKfKUd4<7gd|E94lRmmU+@C%FHG
zh`kQA%+?q@d|6S3pUmD!z-ily*+1oz9LeN!`@*SNS#ty`XA9GBwHQWVEf-I;@`0+A
z-Nd0dj71pX3qQk!&i!n3Lc&OAnEUe;R3g@L>h6C0G|OOe(0_qu{fRyF%|$hpxw5v|
zM8X*H^n;PyUBx(HGPkjbDeR=u#~eR4&W-;)_}|5NFzE5{xfqZ0PU(TzuCHwP>vU%w
zW=uWSLFSvDt%v!q@XC-hSNrNI#&2k4RA7iA6Ujf8;v4Dyq|1?y<0#6>5%6TR2a>m+
zo5O5Z9DUNX3u81Bo4Cfr5tj4R^Qd!j3q=#l(9O#mpNX(T-@`UL25#!bbln7&5kKBY
z;Ow#2aFqEvvMY0%(0MeXiDAV)pWhTROfs+{pQ(Kb0%CugfTC}JuwFkKVmI@8YUDK=
z5LSBrH#1*QwcMn_-pi%Pp)HR_ED?r%TqY|I#TzRO_B08j)K90mU9#s`rdCyp9^)`w
zxJMku2$esl8XLAnb5!EJR{c~_#E-NHm0=vKra|bI+~_@-<4ADiDm5ZHm@C8&vYncG
z^QybHxj;-(q03>g(-w(AKBl3C?@1IuXCoY42fdUN$M#a6{#7y$3U@KKr@DY+M5T~c
zbhCE5LxPVOa=5u|j3b%WB4Sn6REr-DVLf&;AN;x(p{zh-P?ZX}dYK$i3f_0MLcWfT
z#{0u5d7j8B_fqd7dAU#*({lYFCH9F~)gEi+8;;4eXlHSYQa+^Wfof(0+ADkUmGAlf
zg|1F?DfBwH4Pvdwp46A-QkrD7<OX=myjw~Ri$r*8!b#6l{6ceY;q5_@hWy1wmGsh%
zyLM8Hiwz=GUQ(VE7@N4tqf#WB!}jNM1gPgi6<;<}S&q0U4CNP<&7o$s)fqo0ycwtm
zt~F$_k@Ea>TJcJ3XGc{lC~bZ~$ni+HwmRYv6!$L&ew}n`RY!>EPzeJ8h<@Qkz32ah
zDUT=!7%k1%y;q=HjcEi7Thi-K-RGi54r#Lb3a^+QwtVH1&C_oV0D&ch%x8a&VZ@+l
zzTTJahliO>;z*{s>=n>BkW~!QU~)SfIme!3vuqOX4s|EZ9^aCMXtv&qmdB_mL5S|=
z&U|2#@ad6P?&#+AG_{?FXuaV_Y{4c!$jRq-Q2_U9zecDEzkpWjMcVa?Dd+_|GOf1G
zAHUkVmgCv=Ac>0-S6Xe=-rqq$h~?;8Y^MX;FPw__wEQQ^GH~r~e{132ez=w8acz~D
zxVHMh^}&`~7gq7DMIG0pqiM6f-^kp9r@sWG{=gh8_U%0kgjv;-<r0O}cX!^8NyEFg
z`Odi9C$@9%a&~{dn9n`1+gtT_S@E;~a87lH%vSBz%}(3fybPc!+8pNNCSji~7B1hP
z+2I8ZdTsL0Mt9n^KW=vACBu{R-+MU^hOHDy5_x_%{q8xHU9!rg#m@Jb?RzV1Wwzcg
zi>^UQS|<?r84WSDGzm0VB{Ybh>l!UX27!~)Bjpts1iX+mz0jPlrC|Dmj(i{fPP1zt
z&oZsHj%rKrq1CM0lKoiUIZT&G3`a86T2ViU(WzQjw*IhBjbY2#^Xc<C)UhW|TrOAM
zoL`iOga_hI<g<A+3`vuItE+D#{UxKedxg2N@b_DcRs5r$L85UY*mcJb(vK}=!};_N
zL+h&{fE9*^vi#$FZLE7A+H1X(Tk|7Z&HmvtW!AoaN8BVlHFmo*|8Mgmy9$Y`i>wGn
zvplW>J>=HvB`6@2f#5h=Cn}O3h}0TVK*qS*8e;;+d6QJVhqn9nEOwR2Z2j^?p^mt+
z>$mJEF=X2u$rQ3$wJBTo;Z&?9`z9B4^M_xALx0O|8#gQ59$UOq&FXK6Y{Qx3i@Dmb
z^P!9jv}42O>gRZ~C)ARmu@WzvJM*2NLVbMpEUqvb`y4co_@kjYTm5b(FRx!9)aCa%
z>gI@a@;XqDz}Ejl;Q4b#mHS{-XA+hnu?6Q}Eim#66gNU>uFa()Oi3sM2>M!fI!L&f
z#?)~H77Mb{)5!01lMM`698l-xrQ4WOA48A8GgaUvlar5|Qtf69vN^mxZp8t`dpZ3f
zPK!pO+HBTzk&)j7Oq4K6{aQNDg3@LLk|`~AAXZ8?_8k1{2XB+MHS<oA$_Xf`8FB5(
zvsO1;qw;&HZn(~PbFg5_--_9~(TjBDm!$!qxun3!TqhOXXrmW_uvU4YhpiZEc`cLg
z@LaM_<>nX>yDYHU>ewV)E8B3Y>h$Gy8w}!7RJpZHT?GxvA_RMc^5hJJZt79-2slF2
zG~XQc_j9MxNriGENgLb4QV;cC`kHhPmn+S4Uk#w&kDH4(V324dnP-3}pV=v;D5zKj
zO32MqprC=HR1q`>?)CA6oZazs)9Sfotb6DU!1v=l#0<@fx`&eZM79nJy#&aKps<2^
z6mdib46@*eog=j?F*D@o2TlW|+&P`*NKr*g;zpTe;Xy7VxXljGen3?Wm2aJd3fpnZ
z0}14enNm^Lv`z`gVdMaiQp8~>QhmTnGT|LXtI2e9yl-MRz5D=d1C2CYk}zcO%9Q)K
ztI49VR)nYm`pd4EGxpqN(kMmAoF}GbK6C1zz4Zs!jyMNf^?S=}uM5SjxsyCfV8i(&
zY`Zq087H+r2X*u{0wSA1K>;-J<K*cJfu$E)O#0)olS2z)snA_j$aCm*9#R2r_B^<i
z)Z)j+jjXm=Ix5di3tk`+wqguq{8Sq?Kg;<YQ?rWd2Zu1Fh0~+u6-YtGmH77Zt256x
zP9h5>ZU%@g#CXT42)h&cIwNvB#%dA~eds%3t74?TQg;cZa*ixnW?NYco$GiMf)%?{
zdHMjXC@o41A%Kc@3&$0<)?&0vzZVmVVmGlJ^_6PQ*V;bX4jy%m^9T_1>F(6Li0un)
z(V92g7GgtYf!@VDi3wgcwQE(#UACmsQj`4J+JhmsqkhslTtm{7C6u1lLq_EyyzM^<
zMGX4_lC27<M@x!;kDQ|*iE&ia2?IrpO+x~_l9zTYSfk(-Qj=3c%@0+YIeETiNNfko
zt~<dCRWh`LBqRH%qmGDReGSR{iFBaUqd=X?23i$?umQo#FDB~oV}n-2w*>BK=JH45
zH<BGoB?wFJ%nStam=9@AMVi`BV@okR3F>s?s7U+@J>2Nc0B$ND<SDejh%J4lRwmsI
z1R!Q!Q@b!OE2liY{6X?G<736A3eb4mrem-X(>DPNJ<ldr-Pc|uHi8O$3<Pjo6F0%t
z5eO=k3NB$!2L1#I!H(s40;El&B2{snf|4JI8uw{L)F~G{(2CFqJ;f%0m~eqFN$@;i
z!9XurR~o#M5{C16=ItW3yOo$Bv1O#;PovA~3!~KMP^rC}b3N)X_E5->2MvzUIAB{4
zPVK~trqt@>q2uq3mcS)i?X54=VC?ha16&2AUap2o<^u@`BFCwD(&_@s=nR}3{kPv5
z2Y6!yB1!>DNYs>R#T!8Yc@jz-bCo?VN;(PD#H-zSeo=s!hf(VW&|^s8qdSNbBFz(E
z)>0VHmo>@48d94cS$($3Ac+7LEX|hC!vMhZ45Cx%abkAq3R%Skvi6WD#0P_7A`{ke
zU59`k1E6^RTyDc&&Cv<PU%L>KH+Psef@S18$_5E1+JK|-I>A#ZH6gu9Kci?MDAB9~
zKcMoyQH2B>1j@8FG6?E%IE_}1jUSY?cHhNu?Xd(D9?j)ON1h;O4PYF^WnM8Q9rGUa
za}sIRGDT0Udq&M(q0s!~&*U5nfe6>otron-=DoH{N}M@dijRh4GaegOIlAz>k?TWr
zE=@WEJpf1ZDn*J^kBw+s)vAFNMQ2xSOY20%Vy^ycAQ-qBj-}?0iKw;z<Y~b@3yZ?f
zdS{U~ne}Z(YjKQd#dKX@hoIBD8Jz8+F83A09-zaGi!ZlP9o>sDS>DiO?R(KQp`R><
z!j@p+vbE}Ty^OIIDT!A^ZX@NqUq$^n@tt#6$oXp$lCH62ThkF;sGGvb!Sk8bK6RQ$
zWeE9uuXV!qd$Qc_%65#5?IZL;eqmC*JWUA$fNd{~PakjbbU3rf>=VpjUaOn@0%8V$
zzm=+<5r~aS$7!J(?yr6%)#mozZB-CraamN4iiaxM!+H1$R>0opV*>B5h4zix{oR_7
zx8j{u#TrY-;)`F}`VL-?{E|AaU2!2u`8S1*KFcxxc{Es`n%f<Z7dM0M^^-hm;6eV!
z#`E9^<k<z@M)xyuQO%UYm%U+ub5L4&m;<@!<~BKr<_D=*$A&ZeZI1Vt@>J7oPVY*G
z^wz?rK1)??{cdk_ZzSTCn$RMp`z!x}(7U|VU*VLK>u9nE{<g@&JrF6FP8N#cPg+-C
zgYcjb;hs8Aas9yw<tSQeJ3v4WiIhUZ7zkL5i3=xl!cHPE7=l{lK?TOw=Cl!zvX%$x
zEg|P6xvu^4XHfqW+%dJ@S|sn}k<8`)?L~tzE?M!(p8L&kwN`wxZD%ctyWV?DFIU1=
zr<cy>RPf4Ia<{a=n(!HW*_-ktch=V~u-Uyo<b(eld_Ty$b=6}#^3+#~%*mmw9?Naz
zNpgMZZ4C9Ecz)E^b-P%*xbNLo-*>7Ddt`RM1qE;^R~!=<|Mfea>tsXL{+plS_|$jg
z=Fdfj#pkZIzNP{vTKUoSf-(a-8w_BF&H<^?$+H0l)9Ho`j8W7o=n=`<Z4$&nKY)bd
z2-nWAy*@^)f=5T3J>TzPKhP^^3B<(Kkg<?s?%asg&k1?mvWajnFP%MX?t=XnD#O+B
z>l`HPiVHbn>wkl{5GN)PZOlA9V#wb$G;jA!uu%A7b3;GqZD>C8=6)da1Kg}(%KcgS
z+2UOguHTPyTOM%j+SA>Y*=3aBBj1G?r*Zt=R_-aM%Xi&iBdafBfUn{3li$G|{`0WB
zGv}n2A*5<*LLRd_)8#04=%~=QH-MqhJsC%r&nHW9?L9U&teF#fg(Ztdsn{Bo1S}p!
zJGHh!!54w-%jB~EjE81{EQtUK38*d~eHmCG3-pQ_K#OsLDP<^(Z5Dl@3x<ArKu4I4
zBd-|pu8Gq{M*2GR0y0%xdP3y!3q9*7|Jr;=s@c^Dlk~K9OY(PgSyqB94aYA6^P~O|
zv>4vR{f#1v38_>dvw)fzK)K-UyqF>MXEEy>`w!g@GZ`Tw^rmfz6Zq~k_eWkj*-XgL
zF3j5lanv1VK*&|QY3Gz1=$Q&}Ba7u-8B7jNY79ONC@_!T!~qd*%!XB7I*WDK8m0*#
z(h3)+_=)JEwqszhf*+IVs9-oM^lSviPOO|qq3x)yU3$qS%1!q>`DOw|o2pop7O3@9
z#+J(tjTsBlgMc=p@@{LSx$9!fwXmI<2m1d#xT-Npoo<=)d3+Jukj+xPSvR*Ut|F0j
zIWWky2)Z+`44Z*d5!wY8-R<!`J0fB}@637PBdAmp$qVs_-=wH_TDy-!6WQ-FDBjwv
zZ9jqor}NpGan;a?z)cf7&o87@uVx#c#GE*JG`K2XLpwU<grP}d-Hl2j+bWk0A{0bL
zD1B-(=@LLmVb!Xnx;nEV`q1U|M$u$E!KGY<A@TJ%&J66FquxZ1=As$YdfJ8vMM!UJ
znRQZ7MN7D3@ma`IJ4=b1yS<`pj&*|6qcWD7{5j<WSSO0|iX01nT_Ehypu5GhgM}Lg
z<H24L`zv4g>(H$F>F_tsWve^bGdNm>{5F)cvc0hS#b{?BxPgkOb`?{d^SxjA^Il!0
ztl3x2%^cn$T;M!s<Gq_%Mutp3`ipMt@zcUi=PlU2iQ2}7gLOZ%WTREq?i@{m+{Z#$
zPTC!(Oj$YZa(nZHl`ok|!oJ9{6WnGqUaZL(iCNV%TRSzwb<;sNG@H^h1j#X54YPG>
zP_y+|A)bC1eGen2^Q-S3yeS!C+6o8x1u<+Y*UPVj>aoRSSjJ6a)a9MOcxpAq*)F-A
z`T{p~zBc*X_#%poL9%+}G%Mft+7L5~z^0I&Q`*&!WI<nk9R2Q>hk)d>$|1IU4@O1$
zdiDjDySurAGFsX4ZQM^^e|M1&&+pt>{SuOm{<P(HU9LN7D4_p-P+RAv;~>5;FUJ1f
z+e07O9`D6Fe#Ben!ENS0OH+IFEU5I%*6_vesfy93X04tbDeadSHGcTFFk5dx#zD>2
zelqpaojfW6dN9uqWv{!cm$hS8Vst-8q;_A^kdjV;Xg`t=ew7nmu^%z}&xs?ydXZWP
zs^j^qUN@^VV!if->H!zouKZtbu&IVfq;yh8`$RwTRj6yD;;S~8t&->Nf1V!kh}4<E
zzS{ZCGCWeB=_<@tMo{N5Fvrq<Xx3XD$oo|$3sxS^bBWLgCVYFf(N^&r8T~%9Hoz;-
zWK8y69?`eF$ErQNA!)z<>eS!XVK_I;R&)QbrSR`w&dcSuAo95jv_3|c>K}qA#Nx{%
z;n(U#dg$AQD3{=PTIOQHx}!ew>42|)JFa-eJkSraA5-Og62svLZ=KQ+50lJnVdlo;
zYjYixf!WI1dSkY#Yt9_%83=0TH~mF0dl>Zk^5C>+1KR|bn!aTj%xx(;;WOT{hqC;p
zXtt^!sxC3>+{B_$4fc^OSXSR}HYeR~3PY~s_-<*Q9*wsE^Kvob*F#RjV{flHrF>0e
zwt5eq&*WmZ&c~CmXW45|KesVkqdH>tZ=bX9v{<=J3t&e<h?VM4?WA9Cg9#<-A~4>t
zZA7#=-K;mxKnK{JF>69Sxm(&KiC&H%#AkaJV!)u2h-j^l*(GBZs90%J8L-v*4NDVg
z5WS=fb8_f!`hxqIno19%krd5VZv}&6r}y_7SR3y4B6!~F4Z9geSurZf_cZRtHA3IA
zr^j+|0@>PJL(0=o2!Z9rIZf?5?o;lp2vtqp)fhI+d3SA6C$vQ1l3j$#QBi*Yv3rOd
zflPS^4&*|wkujCmsC9z9jb+PbL&?XF{v708xnJ-V+VzozYT53HlEvphj6A7Rdb2vE
z))+cdnaz&HU_qmDR9b4llBof0!Sg!*)M}@wawI;CP3)@`#US>#3n=T;;}(#Nr&Qe3
z;<;`FpA$OqLa;w5tqO!=EtJm-<X-;1Abr;8CeGw?{|R<NE>gPRTq?m1Vi%-I223I@
zy;rWZ)0Sxj%xBe#;wTvIp&;+3P+DL&<D76{C=;|t6sip@a&_?+8!?o<f=DG%s@gM6
zOu!Qu2o?sy`ZggoYF_7-RN92Q>+$#=>V=pJSMdjHQBx_`a_IE3H#wzEubw~+bDm$M
zscVONe}H!hJi-*g06NfdP(00X+4NG(=1@5&`FP??M?@9s`D<CKN;^lL!dR@?T6{nP
zo-0WuJecQ5acimlJYx7PLD^0Nyurz3M{ETnB1n}zP@#9mZ-sTvM{}2iCgDP~c}q^Q
zFPW~gRdU&dg|yJI`?kB&{C80DL4Xrmmcv&#K$X|##yCqxB+7alxBPQ>jQwf0B>n}~
zGS!xm#<<yDyBOk%h`Yv_{o(oC?!z9VI#}^1?@dhrq)lPuPbTR6soju|s|y$wb~xod
z!5*S6S5NinWs#oQYM8AYQcB%)*;muqVhcKusk*)udzyi&Z1qa9cqTyMV^1}AfW3I|
z^nHn;Ga=f}C+MKKjyCn`@yCSf2}YUiEmer$T~I7v(um(ks9Bridl);cElWjpuzKhM
zI>g)UWkTB&nBds)!1WyWeb6t(*XA&o#98(>FW!ZmIfrrueY42Rtuar*#P-%(EbM!T
zucYjJZD#F%3>*h?W^P~lV(BLzR@wW(6`8qPKx9&?(y2i;#>+C9{?GHxtv;HS_BSvY
z(`%PKv-Qvy|6OHw{G>Pk(6+4j&F?L%58va%2k*{o^v$bK6Gw4Y@jbt!Gp<1a6)9SZ
z3Tz6{a6&kWRw5$TM^Y?%MhsQj=AdDqNL_z>+Jn%{*m+0XkP_bbc3)}Pb4;tP93yJA
z=LVCqhkyBYrp6D3Xtu^4^T$>>WcUT!>%rL47^?sDO<VAAv0uJC=+d*6HAJbVVO!=b
z62<51bdkwyZ96;9s)e7o?9rzv?qe4)-fCNW<wHrUB63pbf^*;3;_{gfZ+@(@n?H87
z>cO2gkI8fob@Bi4(%vs!R!$ec&bzHzC#`vlw)I}7JKA5N$N1VguDbRS%lv0a8s4AA
zkU{)n1?noD9aqP~*c7^?N^61N8m%U%s8~nFvS$P_8xUka0+I??s~B&8l2t=TD0*i&
z&?A!e8|Tohxj$|Gj$qxNY*m=8fgmmQ%QILB$-Ipbn>j_@GH0KZ3Q&aKlUO!_E3Tsd
zuk{6s3ZZ-v&(qp%5AYr$Cq;9U*5_1N_*C%b+_ZMx%;|BkDTFE%tM9NjHEGq};SlT^
zdCgrrgpv9J{7+~jBwY@xt>JnuKKlo#(h;}q?XAT#e&@8j@IQ;lca}C)dJw+dFsb|S
zX@FbDjYVyOj25N%A`X%9#9GL?eTu-#ZZjyC!DWNXWogOivY$q4vSn2#RI86hDxsL-
z>Unf&(!nQwF~weK6QFgK%$P@UF1kHWK+1kFb%@5-6_yI-EzG7IV~(rd5r}4%T6be#
z#YeAoC}apiMbc)tMPO@xhRXA-L2g-RFk(%WT*}K9GB^Y-y2;j2z{LeJ*Q|$*@~u7h
zd7*UB5EkV!=3*+I8}@OrG+d<QO#!xTswQxCAi53?8Y7q>=i)JG=yDzL5kh#-0xwDU
z1?ofyZF&t`g1{7w3kY&Hg9@v-<u$9Iv7p*hP$>Y<i+4`^i>2BQ=w+$~WVUu_#G`o-
zK2w%4UrbHssz&cKbwv9F&@1{0k_L%#L0D2%14YmC5XJDr@vf<?S6%Zll{yGP6(Jos
ze)BCGD!v0f3<A}6V4Ki(W`)ekd2=LiqqPTnBp6%qhis?V()^6{pX|qRMHU54ygCFp
ziE0u`bm#Sg4~xVIZa3LzR<V<X5d+}lEXr|mfZXFG4$f?Xo7>nDA|7Mbid~7lG7$Qg
zfu>;JDsjJ_F|2zx`1qzzjxsw$z1!i7Rz!$TF+z?Auh=d>>eH!C`>WTyvW6_@L7@ky
zL86&nTGwm5k5U5yV-I;&xCT^euxC#j_qST}R(`4}*IyNUqydf-%5g8)rK2lw%5Gvd
z#?4IY8cGGIyrQvrV%dVTm6b_qb7osAt1Yvy+6m=Zfn#NtQUC<n2yMnOf@7jLq9nic
z65$A_o%7d%X|ujkzOtjR{imSGm%DgdmUbb=c^uh%nupw~-roB)G;v!NFk36DZ(k>p
zNT0wJO8wj9{8*l0wvzp?^k5_M3VKw*5pA3R!o?25={z=xUFg%1GLOq7uU(f<GD3#=
zrEq$8${rmazn1t-AuzR1wdNyFY;m?wE`^bwV0*Ed=e%}b{`|sXR;|J@_c&>juxGU7
zqS;zvw)*Of;-lfe@Q%7R348t;?b|bjuqgp?k;dXm7xgp{1Q1zX^KscT>Q)q1pBEd2
z-+MR<_uqJ4Wq0ifR0E)IYi!kiOb%kfAff4FsjQ5!$?}W(fXSBYB9<^Wh0eAYFS_>M
zV=dRPI`uOVS(a2T!K){REGX*A{{yx%*S?5F$s(`6|Ld(G8{Wm3hPB<0o$0bY|457c
z2(2nLW#u{<l)jU}?Q7c>$3C!+>7ui9_2XgmUDN)?e?wKB$rR~<2guzsTUl*o#u>A9
z?$EZ(kGz3><4;*wxB(eQR}1IFXie)1MB%vx1)!aDra(V%LO6~VaX|@@l=L8sfq+fI
zem7_1N~hDZPJyUN%`&|3Hk<xpmwQ49=*=(JIxX}vx+2zJ_p;hby=<{Z#I}3emZ6n}
ztJJXi!}8EMRYg5n+=Bdl|Gk<=WsZCf!2@gZX}}2+SABEq!s7FJiFNy4l4}M^=WUy)
z_#$WU2RUtKf}HK&TwjMcIqxg-`PY0d6z|W5%h7#LWp=^qr|ENTZiH>dZOAQtaEtA_
z8IwH!Uti5pB~Lkf)V44x(~QXD=f?JHWrtz-`;al;@8{K!y5gtex8F>|kk;d!rC8PR
zU0BxxfoKI`#v0_Rh@&C)kw-_JIE2vJBpmABaHrAnRb?lQ=zF_$z5i#{+`clza4;p5
z<*Fo?*&4RkboL57F~-c<^*nih>l|YG0c@*V&vYMWnlNrbo|=zCPpKg)rFYtk6O%IV
zO;{VDl;v(1{OAO#%&iC?qHp*ThazC7nEhE&BEC(*`^V^SnOJ}z^KjB2qJ%5$*727R
zd(+V9{9cu<-GcSYhzX#Eb3B~#e5}UOuCyZfyR`Qr&O9i84}Q}`_ZS%H+r0aa$#k;d
z@il!y%s?!Ueq2Ab0f7N-kkOt>Jx0nk{APvWc$RUA^y9i}uDO`zfoR!}agb*fYe%ss
zgRq|9giLsB2uC_hJU3PngW*6TM_Dk!S;*o-%D$%d`Ct|EfX<V8Gxy!*0NNE04h>d5
zYoSQ&Rva1-Z>gf1cHH`yZE<+0*cGEqR{>)O0sSmE<NU^sThuy<*1I5Y4r1FMq^f~|
zkqL)mfG+dXA$}^UPEJ9gSv9g_lmd|uq1M_e&(s)j*1|I;jYPn}zX&s7rU`C(X`B0C
zL>PtGjrba!#EU2F_~FcAYPt+B=Q3O1xM1(Pgo*{8ZmtYMaiqCi{(dm(^T?=cYRn76
zfeIAFB2NbDoOFT;7f@x8m?}Pw*CoZ8oD%40$d8SP$&ujEh|eH2uU)@Mjy_a$GXlZm
z9Mb5Ml47BuEMS&j^t5eQD?HkyV3QpSvJ_Iv6fyi`IKWP;E^`VD0%Z-Z7iN0{I`VWP
zJ;h0$07u7Fggs>{53z+T@HE8k3>imZhj^Q(3KHJt5UxQ^$f%Uw9M?-3+H(Pdnz(vd
zK(3QV(KO^Ddg0RG#`qW~u^5x{o97Y^$Fn=qlyb_{V14VC*dsRCr~T8SGYxhu9+JBz
z=Op9YShdJIrMS?@Sv;hWm$L>F_?}iV97@bRxx}T>R*+ZVqMKA$MNWaI!h5;Nl|o+(
z<Z?2NYJdS*FFO!}Qx2Tzl7RdTcxbA@9s}I6&c`^;omuBZryb?kfDPreW)iVBR>uaU
z!M$z+stV}p7jK9;nU_K_I;or;shGe!pAu>a1k^25c6LqzqtdV?pVl_sh;66lZu-kq
zy+E88Kd}?~mb_#2cUjONs4v7dz#GWC+|$Y{V#O(==as4s*M`F-$W)zzFjD^`&dMjw
zEkgBTX89%po4+rbm|MW;Y#q>(p$`P5Uz3%NwKym2B8*KSL}71d0HvF)``tc-ax1m2
z5nMQBvBhP~e%xMd-NpIy3A9-USYtG0Px3+^u?*}|K`Q_H1vX8x@Kg`wXpX=j5Kf9D
zEr_&K@A>gLg=t;-Lw-5$p*%tV+1}zp@lFX{$MZ(9ElBV#9V7Z_%f>}aR?jJKwZ#&J
z&~lrY@-03ZNbZ5%PH}x9)ArPte}l7Qg<8Bb^IY_^oN+Iu@j(HWbTb!rSW9Jl;nytp
zPi!&ws<SKm<O+kBYYMBDeuq2w;VeA^!P*o$_gujY)rh|`=_wD?p)Y>2v`&kt@BIa{
zKl#3lwbb*cxG}cIA<}sH&s)v^Ud!fC&CH<>(DRFhir@YwJM<*kLsyhh`22NPw$)ca
z`64#qzCCfUBJBR)gd$pNHJF0YezY@Qo~;|5!rT-@LiMEUG`n>jlB@asSocoeq1bL`
z^-c?2rWUj%I4nr{+kXfgQ0=9U=lO@YE}!u-%ct<@vlsoL$9DG<v%y1fVcR>$$yH4~
zoVo1X>_Py+VMe=5OsL~HN>Ux`C26ydzHG8A=d$x^`|c#i4$!2MO(D?Rx9?=?*A<!F
zJylt^o$?HSxU}~BcNB{|zDG0r)=}BwFqbSet?w*-_o>q}%kIhjqwlgAuh=NrUvQ%;
z@E7AY=HyZF=ibVV@u}}JyO{Z~`Bks@%^{Gi`%>4~UYtBVSj|G_c^R{3boSy;e$^nT
zZpjP-9!7o9gY!>}Ot5G5b&e3@upiTEE1~h#>&9cGg|DVm*L{6gb=664%BIAVyA9i}
z|1S;B;n)~*wi)}O`_jZGhl8#YSdHGAce>(BBD^h8`qw%e3Q-BMO8c8tYOlV?eH<nn
z*`Cd}dZR@KX5m8f_Tl)DkGx{FCEx0HUuEyYe~^2#^9w~t(Q-ef%Ag6XiHgq5e}pRk
z>pXrv)551>(~M{*btKs)pcd4=i?%43b?F)dn>k@EQBM>!7r~`_I0d+U;<$Q^;%tn^
zT8~=@6v#u2(v3C<NL0t1a%6{c8p>X?_wx;n9qw34p&;fwdX@IoX^A0LYY?#kA%qG;
z&N<BT85$^T139_dy|~h+6B?2ufjmFJRi1BcyVTFxv}9-?c%iz~#nD{U&&*@lB9T)H
zO9jE}`V0WJal*w7`@$|BkWfc>Q3BOzPvT)enG?yIj!hJ3*?7ybAs2X1jv#BfIM!Ra
zAKP4YkvBgjZVq}vb+gLHvG>h<o<!)%p4s_9Divd=>l)N*XrMUig)w`@LGEEZrbhYK
z@cMWzdJe4#VdL$6Gsq0T=w^75FxQ<9^^+VMU^x(Q988+S&PlKaG8ad}z86+f0X;Qx
z@3>U>i({y*ArI*3vD282@tfrB1EEQ;sg-5?s-&*s=t=}$PLR{KGeY309d*$mLbV>v
zMb&1k53!4NI|$nlvo#q-A%b!;-BEb1Q5lg5a>aU6tc;Il-vYiQ8<m}zcM5L`u;f20
zXup{_O=}JkD0?<(Q($9nRGB*^CD<L&nQT=1FDHA^x`v+8k=Kb@q_`1d5PzeLlc4&e
zll=({u#@C8$6v2h31^B+)Mj)j0N1fN{Eg|cI8shq!Cv7M;T6#rgqa#2mlRNh)a2!f
zjyyn>&n8b1TdY%n(dyM)g8V>w0Xg|k?lLt$&si1TIo4<<sZPGNAQF*3%B%6y&lR}I
zkq2-b7cwqSharcqaa<WaYfj8WNcHM@I_dhXz`-Y7qEm0nYra3xA0qw@;B|+}HfAe3
ze;1TXyLFF-z>976g;qAF=+<rMF}nocsuaQoLd6#C(<s^vS?rb-aZ+%q2H55g1vE9>
zMGMkm$XRV=&Zq3!!wRPNwrZKJ<Um=E?96uAnRyjH<agTdBhX>#&T+G9{j)ECobO;}
z%DlbbUfK#aQ$|?>n-}eF&yvkZ?#)ww;i(P8@@uTHC)mqjHxz-Ksa`iAG+uYwR_p%9
z(1gzGRrB$P$H#2e1j5w}C&g0>Y}#vkeD-5w#G02(w?6t6ANK;wgb>WFqF;DzRec41
zZu={W&Y}5Mu~qe0zN0WNi}E}+31cATXqHR|T0VZo0srOz+gxnhf1eflssn0^Eh7s4
zmzOzSsSR_XeiaFqF-?Nm>cn>RYqX=#s&;CPu)T`KdDpOYM-SS#yMBCgj!O0XZhr7p
zHnlJ|V;_2Rk^Q$Ub!T7tr^-67%W`|cg}xl~0ej_gx>V4qZq}~fw8Q*U=ki!ThuPH!
zH<+zGl&JOkP73na*{LL9$0-^Bpg4Yg!Gqz11-n#(3JB1D;FAC5eOXs)rJ?m}@fK3r
z=76O&y!(-*IxW2;Ik12AG<77Zz@(1O_nnO)_XH<R)d)|Gmho$id;h?Sw0Rr3p4Kb1
zGKy{YH%FtgomwkRF$sQ(FJj{)E|9Qy>^-)mS8By}Y=51F2fub9AN_lajn|)>rO#a9
zl%>Dbq}TvZh3uvSRpAy3_Ih-mx1%Oc=VcUnB}4^!E1b7sh^@6~d+?<koO)g6Z2Z@(
zJmvPJ5EH+#Zzip0x*OWx7;;Q>WX0Gupj^Cdj&_pjm`i`?-9Wb97<{T@^kQ8aax`0S
zMGpgkEG_n*>>7TU(Gu1vFmGSBae3-^Hj;dH`Ao*d;#BN*u^-U}&$;k7K{1Y?&B~%=
zpyn0m2Vq2PdCWyPuZK?OZuh+}C@7tn>|5S1rGYUysFR?$U1`prcpiDbK;{1+D5HE4
zBD^dF()vS)<tmn3crGMfu#j@RWQuEmgW#qhHtW!-M}1~5+~FBuEna1p5m<wFC0~YQ
zBlc9`&0QQ=I1jt*6Se_u4gcwRoX}Ov-DU)nYg7E7z<On>i+o*@;Cs1KT(allnjI@A
zG(xy>zD`_J0rS#?t>@N&fa)}jb4-Tdun5+NWs%k{_1LmOn9ftgN2&25r+jO9@9bJo
zN?!<6-i)wj<<MqwT1*(Ru~bMkBGafFmOeHsg?S3NSd~0@s63~*HApfvlJo@XDtUu4
z*Ra184?A`RNHy%Oy4V(ztOJlL0*k5<Zyd=5`hN9Ma4R1>70R+q@*2<d1WpD^$9OW}
z_pDR~k7sb`W-HBI+2qMl;$BoI@X^KTs2ubHMZMl9m38`nK*YgN<e0kX?dOb3M|=##
z{*Xq}1B%K=2K-VC*S%%AUMkhPocxnET!!@gYZ5b;Ja?*@=U#!yLT-@rY(X&ZdbH5P
zzz|TUWy7J_SHGT*wT?Bt&)Ot`F{Jjfy{Ku1%)0y{IJur*ugxmFIn=%K!`}%NQZGwH
z6rv^@+9}l0g$X9ys;*hyZL${ydl^)OK_Cbz+T0tuTITuag2XKEP{qg5QvZ=XK#N}V
zJ(0l$+R+Vu{VrI{y<M9XH1U}9tT<{+Y|!`?!KHi@VIzblkS!gRpl08pn&VyV8=QD?
z8v`fvtG|o&A1e+$`gP2qcy~BOkPu<53SQ7)(pN|DxI3Wa)o~62D<FpQkiOcWBFslR
z4xcY!rqYb?9Xl=?z~gtcu@GlE+4Hy#7y?SOnMOH5VbSRvrL7eEt+*}=KZK%gNg{bn
zJ2w!SHT#w?+Yj-=YA;g~{$a_?uFmk1#WZZeNX@caEEtCl`_X$(oy%B%6-vBc*f!=A
z=nvsTA?^jv0;hST1B}^n-&z>9bLKtSW8*}gB*x8=AUl!I>h8>a#d6#bn}o9!vQA&_
zNSuysBw}sm6i<%39pzjIrlH~XW#zh+sj<xd<5rtLr0#!+MexM5N9fJdmc5e06wJ@~
zp(i)?3*R_pIiiN3HUWfJXCKvS&d~hO@@$VvO6pO2T35+;{|9I$Zwcm=6VonU<=+g-
z2X@nifl=S|+_Go3dgYKbe7A2la1Fb@&c^{C<{7r|GgfScNyaAOu>bJ5%vQSzeRMo{
zP{SPrgjhXM*&+s$lXVKnY%SmaHWCN~#Vozlb(}_msE9qLj!mb-rO(g8?D^HLw)mcm
zh1T!%)~$5s^@mRP$)VC^)Z(L8+-cLp>9c3MJ9Ov|o;GVQ|7~x}SIo!J=e17cR5KU6
zHk<JeBGfO>^E&QVo9>kc#WBGP31v^6C2jv#GVgdWv-;NOGOiN}KPj>=IAOppc7I+0
z0li09p#{o-I`nZKK)-t7hCxBXIkBtN*4^J&$h?x9TG`KPt9TUJZau98Eb*$hC7ADT
zrWoo4w$w{10Slp1vPK6g25hHBWE4}CBMsZ$-sCv39H%BAl{VTpW~;exyvM?Mr&_oC
z!>v|-j)(8-eu1~sziP!GgNdz|hNTc}SLd2Lc*XtZ=18VtdeYDTVLlXoc*xn(KT;dp
zcc-IAyDIvdo#pYHo~*XYpbkCBtXd`Xhwn>TZ|m&o|K&nHBs;@fggdsCHgR@iKZr^{
zSZm3!Hy5!(bnPLwSwz$B$(f>b7Yw9b?ot|hxHM6aEgIFsYAfK=hj---dY|GIcvds2
zO&e*6>1^C2tkd%52U~5`?Fd^Jjp8HFf~_cGZ_g<~PdN3^Dk{+ChuO*je0Xl>eT(iH
zV^*I|`F@ay!&_*-zwYo20!#Y9T9IeA-CO2e%(9$~Pr1|azHR|^jD>kw0_(7so2Gto
zp6_C{_47n)A5a65Om|O|jHwB0Z`)ahK<_e3prXA$8?fZ)lpqvxRNpA44_&Vu{Je7b
zb>xL8vBE(Pb**%M0Oin_U*j{MRjMP!01J*-kEcJB4dFNzV&f`dAjsjliOYI+rcfLT
z!9@I>!YNh}g@P()j^v3zirLJa=P5Y6!u`369()19LG6a7Jv%10`Vr|OxrTv5Bp&um
zh&d%+D~u#Xm`Ugoq5+9H-T2$fz1U}TT`<^Sw#M?maxhYy%u*f7f=XwFi}gig^-^R6
z7u^o-ynNadQlnA^4laIaB$ZD|6o~((z>3%mcA5`jYono29@yHt+in)&;L{{zZW#-P
zTLOiFGCOvWCM>dcPm?}aUPEah=)|vW^VT&Db=Ye{L^*q;w(YAKh`~3uwjROe1MD!T
z&!>RH$|A@d4iMB5a!<Y{BRBiBbqpz${EVOwRo9S!oK!pjF#3p)BZ`wR7SYF7!jqqt
z49rDWj^9uGj1(PU)8*HWX?T9Br=J+Hi4&imF}>-iyr)4z!J}@&Z)f!64+J9k=9(T8
z7Hw+rPUS}Y{vd%%Y5|q2CVY23=23GJgqTot+8eDU&Fo(#nYcw&=mr;0S0TW4v=Ra7
z2z4YKh_+E5W1fiv9q-l%6uii{7TC<=mB=_YbQn$|eXsg_lyXBY^`wqU5189g1<DQd
zsz7BMi0?YJL;$Tx59<##g^vN|4|{dDun@&a2s^~xb&tV5S#Sr-iPbNX!L4Js#hr8j
ztt7!2H3`|8fKmaSg|i{E(;TBqtbqm^?P#uo{{~3iC-1U{55H#!J`1;xC$p7FbRTxn
z4GaWlgQeBY{omO`5A?21qb2Rv>c-iBK2hWN+)dEhYRLaUo=>|te&R@`vJIYNLmLhI
zId}&Et+sOD6Rp2<zW3RulLG2<$;$B2j^wpgTcs?@wU7w<M|>x@E$HoSQ)Yi_oLn)?
zQ~l*Grxt`d0Q^a-aK<9*qUz=eEe~6OhPUrHg`%qK{Yn;Ivyf*SX#KbqyJo=;-=B93
zJ8un&RjPWGH+t!3imcvSrp*?!(>67K-cEhi=UIU8S*^BmB<gn^XchjIZ^%?B{UN`+
z2s<CMtLqzw_;!874-bBdK|4mrwMZ-jX7La1czh*i-EC24BMt4o-OFsnkUermG+Wg#
zIaXWAbba8~?+>iDX30E~<pM2Fo@6*&j+UNquzjA7^0>McH^;Hs8vK_+tL(grmU!r6
zthS!AEwiOxfww=iKTBckfAUr4hQ{pRZvSelzo}MaEBiiPE_6RI&L-iX_f~#CWqI&M
zp72Uj?UuYTsN;Iv12<H>8c9E>6luyG88`dU3qkRvSCg|}x_H5=FJ<hyCB3+yOjLy5
z51bGpJFZ@V1f}dpR$J*^jxbaEpHKC@l+CVgZIf{4lQhv|?8o>RSzCrZ@bz4EY!BS?
z3P#!#!dL}w3P~M{Eq4BZ5Uu5R7O4cH1)wAgzl-23^15~7kZRUfcKmy>uiQ6&Ds9Cb
z``#+|hfXc+Vm<O6OJYPSn>mO6*~+DAsIZUIc${rn6!K%QS3|OyaObNEoBgCW``AyE
z+KOl&Qu63tvycBAQ<IpjR{k|gUq)VuOrsBrZ7OhhHQVK0Pub7?goU|Vyz||46w&Ap
z@dgqa<dCcZwTsovm)(z`oZCoT**?=t+wAJ2*%~qK;qLA<4=*UJCp=6ba8J3LLJpH)
z-D^3(Bf`ZK=^72$+l-w;gF>wb#l0%SI!IOd%Jv01VoG-;*)}n`SVd>c*L8T?pD+)Z
zGA@@s9(dMany~$5CF1pSYCd;X?$~YD9r<_5s+LK}+O1ohbwACj`B`+t2fM`FjW*YT
zu6g0b3=g$Q*j`>`7<U`w))24c@g6>r4aGfb{<Yy_Ht*K+f2%%7L_WEv$Rbj4HtN#{
z6|rgrPUqu@1~rw>6>+sH&_B^kD{a^ko})lJxdQV>ZWp}+IoK(nd#9Q_2Il6Q2pZ5j
z2(hgP?ILz(yjiBW%rImvQFM&J?GHsZZ24j=7MoEU_LMQqy38iYUu6tS%;_=PKs7Co
zV>CG<4|$qw3el*fl^MFNTpqyt!#wSi|CzW*1!$oe?lN0-91dri3<e>gjoSG1I5Htm
zH{G)-LB#Wpa9YsTCh)pxMdq#Jl%SZ@D|7Yy`a%%Zpw-q5P|MHjU?C*MRa_ewGiQMf
z`B@&ULixo`BDy4^;ALFz@ecw{NWQA|xj{<VQP7GEz3~^x#m%a80S$z$G-E;T4Cb_Z
zw9IuQ1WYbHl!SP|s9<mg)&530C-%1$%|Ikh*@P40938uYEWr@s8sZ&!Jp~j{wyev&
zXy=)?DUbHDth9q5)6cSCOsvna2(+()br(%)P4X(*AykbX`hnPXM?fsfIqrO)+mP;h
z$E|lr+g6A8+r#*@lOvDjKLYnPEJhHk43-6LlPlmdPkDp5F{sgHb9g?&Dwi9A);OMM
z!K$*j&tig+@ccxxq}Br>SrKHds+Ky41wyL6z%^#_@~BdU5**I^ak^ZMp<YChe^Y>G
zPXM?R*w85GIuf-ZDt5{kwf2QKGdFKpKzUZsZ9DGtAgZEJhO+kfwOgx={y1+Hc9g!;
z1v~D254p$dz1XI~Dw(W5z*cBt8`UK0g3Qr|xO()@-Ql?8MJQkj+pKFY&Fw{$j0p|3
zrWJjHH1AO$^GTsTLzAj{#lF!KtyswLqT|2|6S0V!%Zq>~#&q-%D@i&PSeVg0kQ0cR
zgtE(56dxNzD6v$E-3cdjXhDI#AjyQ(6Cl#+<)Y(=D+*a+AQt_A2S~~MgID=-?8yDi
z$U_wN5?N<Hm&j4TAl|#p=`RCSLWg2KW(#JnGW7@8?uBtgO~sd%IQa((5*xNGqTqo^
z9dvNn9y_0Pg?45`K4VUHG<6UfKpY}R(3*H(s0~D~W4jDmIL%IIQBXtH;43Cnhw#9*
zl`E!3H5mg&L|*iPKC6Xf)qWxjJAEya4Lj`&oaIehVz-AGhI~O(27o%UOSD#nFLoz_
zoJgqmgM=bC2z8@wMBylK3P~FRA6+@e$E+ot)Uz&G5RTY7c^X(x?!}0SMw~T`&xY}|
z`Gt&(Y6Xs;4WPdys$Avr{6tRR<fP;#A;u_n9X5)!QB&&}(HG=yk{*$caeAzei9RN%
zPRk`(k4ZT}ka4Yw#DkvF;tj%4$ERY%fFfM(aZ$q@t}jAU`W?h96SI!lC@RKn<~XS~
z^=|l_59`QI^W-N0FWMv~Q2u8Q>r~bSSGy4u>4KCSU}1xw+c<@SE=5Bj=sHX0SVX0K
z%Mc~dP?-LWt{%ebRr-P&{ZQt3Y*>2IjU>^!D$@`$PeH{G5vl%ee!=o6Gf$^&@sy-_
zVu@j_g8*GmXoz25h-|@vZSFO~8Zi$c>pEK2=?-~_^YnLi0r8H2P4GjOEGV$crGN=V
zMITIo+|Xo9w<Q_HQ<p?Ro{S$cYvU)yIM_B1;Yl9}<TYqbCSvm946EEBs09j=kCLOq
z7?AFxq=#{!_J<Ql7Bl6EPxPy1JGO7GKedG67of_qFvf<GxS|?HgLEY-0OiCUP)(pu
z_|W+|D?FYE=z0w%C)T`uJfdSQ&#W%j-Wn22+nrcpO5FgJv-IA0F&ZrEC?zK^uGP5e
zmhaNFFAN7K92Kbw3<4!QBOAPtZ7d6k8zG1bdSMag;Kq1GiHzmTAxruqyXFgAq_FR3
z<ZmJ5lqbj$_~;JmNMu1sT1x&{@aVO$N7vkzQZS+W#X1F}iP7_Z3)f=f%}pPm8glM9
zLe#gQ8skY(y|oEQd3k%pu212?+^+PLy;_Yaps63_N|7{A=(x5}!nOF1fnLkiCN<r_
z8-Pp>bFGIVVmweFz7UZ*(S4R2?MV4-wsaK#lajt|+AJ-cfN~_s*L^(=`j$XKE6Z4u
z$?TqN$J)fA-TTv^K1}c1;Wmj|16SXJ=R&4`Zc(}VL(Z77wEI}AfjZNKxl^8c)N{50
zG~1^Ih2h(SPlJB-3kb2$8<{L)=lahsvj`S4B=fF^x#_k0VUj~No$;C!{1Wabd@&Sz
zxO3--P{KwizK~fSzfJbGD%u$9LPfMXV=Ed9cL`{wv(e|8h-Z9Jla9m|eu2;Ny}g(m
zh+=$mYLx+XetFquzB^Daq4kC;(-D)JZQr8V|Gj^()$?MT(<9XOA8ye;AIo<TqpgZA
zPV#HXfDLVaAg)FEj@+#tn$U_5ognKqg7~i0<Ce3w5O-j2)x>1r#|lqgwf~|;&wE1!
zli;WQmX^JSyR7;u9WaYP609!-q1`=&o^~*ovgNE;g@@ixA5iQXkDL2C?5%98j)I7Z
z=%rtJUXlMaK2C@5Ua@MqYba-o7hPxLsR@qVs<x7s<?H@w1B&wWgCGR4bMj<z8qiC6
ztYnmd@J?2`#JxXgd5s0P?!x_KR~-XdrD2PwRTD=tb6RRil}{H0lZBUkod<|Cvf5P)
zp1of$%LC|kyS6<J1Y#S%{Q>o{-S50|g<OGOmxNB-f2g8qG&SS%Qj47`n}sKT#@xMA
z!`7K)-~4%Fp3_3D_5=1291ih=w&P{k+biFkvGBub1IU3n%j$>d3Euy5tYB^lTmJgF
z=DDT{{72Z{ofZ2EOzla<N-`C{{={~ULpUpFL#B)Sj+Y*1*LOhbacSu4W~8M&{lJ3|
zhpTJtCFO8&jm0jB)g81oaH=0ErFTI5sr(kUn0)a3MIGuAVO0Wg^X0eEglg(;ZHHix
zq5MV{vCRH-S`Ca*-y0XSH87+NcunGF7YB81Gn|Kd$l3O&(j+*QVKHn4UQRJF%mYAh
z36}mNTPuIq)2G}{KRs0~e$3zA-9^fP@QER>LD~yH%0iCa6Yl_Xi)4P3Up-WuU4LMK
z^JVmcau32!FrD?sh2!1#wCt!_O>hsDyF9@R<}1*8Ab$1iVDTYcp^y5xOFhJAbk($2
z@KHf(OoKuclMIE<)os9`=c+)P>I{Qn1!t4$RzS;9H$Q;DT5S}B^&1QvXc^DdWJwTM
z^yvn`D+uY9XyoC2(HI+1ii}C`X>>S4oVKYLZycukO8$Nz#pr`$b$AWKGZo#ZEFu?Q
zFDkp#j8idt(DOQ#xQ8DT&&6c}to#_4dD2EGAS+CBa-JbLk%l1uHg_13MD&LmluH?X
zvf{Hu6Z0__M{+zwsbkT0GCo~dfM_`yOg(_hTB+$+KH4;*&`Qh-T7x5BU+`e)XFD&Y
z3WKO8O@#ZgI*2bFPDQ*LOKL9XbL26-vbPwUbV&oq=2K3g_5}@$)D}Cb4SIzV=OD6P
z?a2`rl63gip{ADv_vn<I2wHwu?$G*@FZG+I$Vq+{p}Lv376+o&k(jjki*-Ywp$Mt;
zcqwXIF|}Q*1r2G0&oB_1h!Yb%a#%th{C*AKu1)u)+9OQ$6*pmRKtBOm^wMO6<zDn0
z!C}sK7%w9Ct_O?10U)T_iZt*EOFU>CnI2@$%!XsNE{b44j06N!em5Pjv&WjP35h{S
z^b{ydveIU>9I_6P%6jl=`Hsy?6Yma4pol`uX5qYcL&cFZYIChqrk)kK4#EtXxvubn
z;+>qQ1yc>SUu#7%BKJ*vy2Nf)UbQGenbCd7gWLtrVGgq-v6rfZlfopTzMoW2e@iFi
zRg09gwCk8c2rLIJlF$=tjY=${Fq7G;*1ZPOo#W^Esjr+>gy-=RxIROGFGXDk9lP=e
z>%q-^|FmFP-J(CeH+yS-#7kLb3^#Sj<7nxI?10^K1^ei>1U{Ed`Bu{ih625i0bf$M
zAFuV6{kry*unF8k8mG~$VW<H0J{RoEi!n~Md3043t9qMa_mr%zU<a=#`O4ceNWNgB
zu=hu4Ad)!F=^6(YPPy)QyL@Pz)CUsAJQccETR$fV`$^T}1{mEnX*XlGI(yqr#JyrY
z*$FGWd}~sE*f(zB2aDV~-`m+027Ie+1E1r)u_j`DI1>HBshQjT&G#ISccPd*xAM4J
zMTze_$MH!>3qr!^VDxAEJ*T}CvYYnaZ9dd|B_*0eM^K?uUVnZ|{CZ@3o^rs4*F9c~
zKwl`|!gE|~(Nv_RD`xBIyLpAqD?1UHm;?n>LYYHBYht7O7el?g#bmaQ&fiIFeuI$u
zL)Z$TqV2mM?XpR2%X8w!p6U_ao}1#;)qNkG>~{17IErm&J6lChM^YVXSceTFFNxvk
zo1Am<jAKMR`ad$ezdLN%%sY3){v#-55C}q2DV;pXum<mbE&@G<9%@Rw{T+F4^tgs_
zLXYa{(BalZXr0QlA(^cY>U)~80w1Php^mHFe>G%(-epWI?O%L&lCjf|+Sb+I$D*ay
zllsM0nFfI%#7|y(kvWxMgSCv{)vr5MCTug^8CNVbz|@S$wSUKRkaf>0ep_P|ZqLC$
z9D8e3`sJC}QS{?n%y??$HGhnrp0whwpPuv-Cmi@O%j+K)S+T3W4^_y}`BQIeO{*OH
zOBWXILCoSlKAruKc%sOlfyG1qFf%hxU~en1^sbWQg-CBbpHdOw6*~xcAtB9rlTw7>
z!LuQR0XMqJt7YBStLg^<ZRY+mFN59s2C!*yf_s@o!m!jEa1^=49e6prMZS{7kzfd%
zYispKTxIXqe!Dcm<6Enl=l$iFzpt|^BK~npmOBvH-khyw!MZd~fc;XfSWH(e6YLD*
zylLU0GPGQah3iB1<&cl<+r{Usf0jmdQ13nWhssvZ%!aPv_*lCg><KBJ$MmCRH=Mc{
zUijdZRPyd2xG6qCkV-TAqhe;h`y!&=^_(W5cTpwA_XriS`aRw-TXS~J4R%v0Q$Hw~
zm<&Ra;~dT)z;^To%`*g2g8_n^=+7}(6)?ZvH{fL?8bThQMrE#&b(s#b^!+tL{Q!j)
z*w`)Q1VTCsjj7jMgn%g!qDKx`vCo%(iC;9I6{CQ2q*E6IfC|(RH}&(L08c_eTw)Lt
znZa{JK(hy)kg&S^Kxwohj{p@!$USLZq=9KUd2BQCJu`67M8U4vL|~a4lwLOMv#f0s
zML@2CTznU=@LVG(B4pJEIsNg~O_Wy!2KogYM;t|BE(6COQ);4444&vrcc1|3@v6Cr
zn$1#YD%3n-S?h(oS2&Lo5J5ay<0nc$qf2}I5{VRfQg<{}L!P(Dh^!%E>X7#M70X$I
z9gV9~d`$FNCy$<x-V#5K&n%KT#4{RtoX?1=*j~p>&(KMnBN44duv*o$t$uVnASiQ2
zr{O)GrjZ?OFkrTtrxv)GD09}q1+w9g#quZ+xM94LZvgPZLAO!4u$+hJ(Jew+kDwds
zQu&0T*yWBw#5%R6+8ohdat#7LZme_6pwTD;d%Z=Wbkoq7(JhfDJGtVu=7wDFY96x{
zj-iRyB@iZ)qOAy)cWjhZ0_QzSq;U*b1wuRti10DsjtQSM*zKt>)+oi$RjsePA&ZZG
zl`-JxDsb*7#&@OI{%#P8h={e<-6(!N=uwYh_OWFy`e5C(xk4>$oH22NLWbg?AmS>*
z?0SZ>Kmt!VpHSgzmA>Jmp35j>$mpnZPl@d~5H%n;LoEC}Ti5Q6<B*?5L{!Q8)1@8_
zk7|m3Fu08!9re3IdeQCS^i|7xU)-<2c>$;KwAO0t$6u9Ocwa;DUOf_z@ceTxe4wyT
z$L^Q%#vxWJVt>}R1n!eoriln=UoX;9%7sP2B!7T<gjChOh%tIwkJ#O%_m6DL^06YX
zBhrB@GdF)`${!;(bLO8n>sBq}?K+JZ-14Hty}-}f;TL0yUqql-riDC*+PUo|K2j>X
z#lrZQSig<FiYi>IaP#Ny@;8Pe*y=R;IETrKw$3hC1~-l^xju7HgLNWv<Mx2bPzL!o
z1y5@EBn@?y?vSrx%wrx&rR9y=U3}$VuT;G$uC_kOzK|M|0w(4D!@P-DJ;8GjvvpUr
zgUIAK|7A#r%=86Mn`SMy@~aR;uWtTh+AI{U<tdh74TPAG?51kSiEY6lGesEMUY4W(
z9+9<%r8?RDDc+cSWQ$Xl%>f$WS9l}vW>?v*`E)Uq@k9kyK8WG_jUgKyeSE=p7&O?S
z_g`V%S3ED4)^41qbKcQ1zm<kucV{dYTeY}w8Vz}m3oJG>()cSaYd(_sIv=TuoHrAM
zvcRuDNHSq@H7Adh(SshhyXr0e0hCRz(Fdjw1jL=a(^Xj7R*sG;a5VCe*-D}9BVQez
zqVk;=li&Kg)8dXDo2EI$r|q3jQ36(5MXf);b_&F?{U1Lqm7r<=`pjg2?c6vtX!S_P
z&-05FD6=*E!>h9JBp-L_Y`xO*_wiMg1K#p4j;{5`LOwABMEBQFS2@Fmv4fU}!?Y@R
zly92lD4T7Z2J&LZHfySN`C1>m(p1_@R>rm3%0aZBDV%$fPH|1L>^rDqX1-z_yZ16z
z^U1vHn7R(n=Zh+9!i&;o5G50W*hN|=#9kHO0qsXE%ZAuv*R9YqTV?nPTr^wp<a{-*
ztIf=jX}C%Jm3$;#ZR-BZ@f=8O_oTRfuH<`i=h0ZO6$3$tuAIb6F>hMnkm?~j>+$dD
zhFsgdL#ygK;f!S38rc_i**!zq>36v9tP5NBXGfkN5P4pc#6zE)D5f5Np0jXUxac5X
zrgZDXR6TzjY~=9^v#z~sVM)bIu$<>bh&M0cYRF&bX_S5<zbiku6MX^exC%WZ$fHc@
zU6TO_twfw9T(6p1QzH@VC(WAK8@E&w(Ljikg)tE1dVZ>pdc)b01Wyhg{Cq7r8tzRH
z9R?-v>`SmgF_;g;afC;^>kw5b;wru70Z)Hm8ZCeo=Hp>#DJwzOZpev35pW#89{9=V
zqbuh97j<5M3=P23CAuWAx=@l+KsXGao>e%@GS-@c?@zR+x?wMK#)W`vDO>Xb5+q_N
zg4|K|c5u;hT0@-80*BD4c{;8ookpfWe<;j@6sqA`YcUCCxacJ<-M?q>OPo?#<L2D}
z$_ywjG74tzCCT~8QAR0rqML&!Sq2SNTS;Kr$d<q*8O@Y1vptoyTxu#Ltb>y`ZF2WT
zuZ)4-!V_O4Sxbr!INabWd+%Dw6uUY2&60bH=!oE(*;hR{VG7Az!pg`7`Wm8&lu8lm
z4GEyO^APW_;gDX2jX1?doPK^Mgv2(r9NncS7MP)DOdvTh|FOV`b!wd4;+K)F%nuEd
zG7t>gIJ*UkfUcHGO4!pGBixwZ8|!n?x8}5y3XH4XaCW))9s`n(=z!U3k`j=F&l+qP
zC4~WqA`V@}iZE}=Hp_7At>Bae=(?rkd0MWtK;9`FdA)vkHV98l4@P2o6B0_S3gvxe
zX5%;N-s7oL_1_p5^EtbpW<o#C>ETxE+sy(u&vvG381;EI?qgv-ARj3}8(}t7t1Fh$
z6E7xeN0%pi>Pve4bd$8%rIF$UC{oWQzDdw%<PW$N`hgR|EsG(;eyr-}R;{6jQy*N9
z#+%g2T64TNfb}q?>6|Zo^X2J7O_SY!N_@uLsymytQZ}Rv0!~P`SVw!4V@^Bb6Tb^F
zV{ZvTg;|G#i;e#Pi)!Jjl0lB+&ftl<`rpece5_cs(LG0RM_A9i!I$IjUPXDP>@P-q
zx%6-Crsbf>7W+u1+=_EA3Blg^LTYX!6g!5>4y&!-@2}4C>hYFqo<!hiBpukRXxf%m
zkGhf8urbMh71dO%1gnc|Llf9Y^BBK`H~~;vVzragDV2|0*zR{O$=e^a7kGY^HZby9
z+C68HD$9)=NQ3%V4}Bg3l5==^JeKRD8?Hu9KmPxoV$q_k@8p{nigDl$HLI<72LM)E
z17>T;R3z<9RvuR3Yy^2c+6pm&$klgXQozLcqM)_1F*i0fAL@FV_gmh6X5hOiW%vFY
zNArPN)beY28+!XEX6R*3W9*|BWSB-+xT5Zkzt@I~mzPtWr;tc@Pv95XP9EH0#Rm}J
zz^yxM=E<M7e3<lz^4BQ(!QT$%PDOt=vb;0*yBw`4$wziFi?})+A{9~U2SErbrIRPM
zYiS@o0U|f7KimFfii|0nIk7RYJgpUM9sL9N@YXZgMTbwDgd-2xvsY31`Y@-ytr2!^
zeG3DIN4Mwk10r#eH=3=+O*jC=IgDTW3a^2}fEkE5tW94{xh(e1D{U2xrWNM2+N#2^
z!tW2*a8>HGm&pq<SAPDSl8<Zh<p07pN!u4DJsYK}-#@$BS$$&0h2^_r+nt-eB0K;G
zf7R~HwYz~n`t6x{Q4`zhFH0Y;pJ3i&()raLyyMVFMg?-ZUw&4wU5_DW`+d$vFLl=S
zw6MSA_|)awP^G900$xaw9oL}1aj=S+(dAs=zOWk%`djVRWyb(5j%h-mv}uMVz}EE{
zNUet+p^b(uoP2>=9jI<WdLhPZkvGR|m0bNnY@=B{KP(M-?M;q3p-^qKw>_yYU&aOW
ztzf#1f5UrB*L8yZoPQuYxU=d~SU2>jnsXnh#mk26yth8jU9<3}+?i{v6dsSEDu%0D
z&u11?{YUst7m*{y&Lyz@W3*Y_nCW}>ww|>7N;{>v7~T}$R!+eJzCg(+@9$c+<ahf>
zps!P}Q`{7HLacZ6uUB*_eMFtGO{=Gyg3(Ll^csfh4I^jx;+|e=!3)znvM=G8BR)=u
z;{pfMWfPZtj^eL?5*p1m*l<QSYtWP+Umr{jSy1Y@OV=d`Ii2(%T7AI9bmsNA?lG^>
zqVxoXe2ObAOU0_GZ{pUVhEo%4D>CCX$2G_yR!&e1gTQ37z#0@<_63`w)(|)KxJ^@g
ziF#h#Zyf5?i`eXXSQd&tp`n6N08ef*DnzlVfChq<+k=LQlQz$7{c8MH2v3-xk<Qea
z2C4(WY{aTpoUWl6gu}O}3D=3cl7KXDz@rsXwl8N7D6+S&vYWbyEUH}Sn*u#kheJq)
zJhW6&N#D&J+W<nB(4<u69Q-#*;Km%$6fzq3)>R-uaAe?LYDyZMQ$pr&cr{Y3<k<y@
zb?u-eDdh3cVZ`hIf9Bo>y0W9X^WEp%quZxt(LUXlZDIUTl7$hCF~TO`I3Bws3y_Hu
zWYQ3a@xV3XI8H*CCS({VKq$#Fw9S_wCS%qllZ(S-^$^1JWXL=x!+TsD57U|Fm-G-A
zyz-JaN*;>^gs?h1LOg^d@At1d=Su39bZ^@xYqoUHsgGTI@7ncoYFE{%1DT*GNh`+z
z&ID3zPAy!yiRK(*noz{0ON9&x{yDJif2rqlq#Com;wW9EF}1HrG4^ytz@uGrLDAOg
zcq=I5we$*O5>pX_;K2gDe^dpBiP^)`BL!=5xXjx<*=+7qIU^J9R6G|7JsjZN^xC+$
z!mLzrmN`4J1mUnmCL%)A&{otl^`Vd_2>n{6tZjxEA-eiG#o%yYdG$U`Cht`QDoN1m
zQ>z1Zy}1;-NTMJeh*8jG3oOK$3u0oIUF#~X#HDxd>j%k}MB8{egdJhb9#m0bSw8`8
z6)Ius8O-UP8envkcEovdr`a!}lZY{9^Cf0Fkc^+sI1beGJ}o()5CjNipRAMi#;DMD
zBpG(4=2RGW@Z{>LxpGD$Kv)f*MY}|#fJaky7Q&y?>8%r!oy4l|TvqwzxA>k?czYhX
zzDv#l;8Ofz1$EEJtF&*gLeXd4izb(h4`*=jU3D}fovcYMAH*TH>?7t&kg5U!asNFw
z(O2&_!iRu7;b{8eJ{<s%Gqj-qO8fm6(@~7LxexyzVEj_(cOW&*zg=eI2uEhl-|S<t
z#>*CdW6nYRY+DLHw>O&@-}nBd-uEwW!PwnXOLjVvCy4hy%_#~?MXQ-ZL8-S<{rWqp
zXRH>+f~A1aQ@HSLYed|g>MaILj-cLt@dbG{eUhEf2OjrMD{;2(AU!0!DjA*STRDqh
z7(kykk5TL&zA%)tkH8R?_goh#*oz-%xt8*(CEdW?FFZG!b2<r?yt(5yNfIjDJ16|u
z1?%bXDG?k5odCwZ@t?4&!|Nc$y*liS4T66iEZjMs=VJ#^;ETzU)F4z-3A(@EvuO9?
zDtltfJxYcn@QWxNBhjayH)dmpGFu;~4``oj@yQxdgf<9*5F$G{qB^2CmW$saP+J(g
zfg=)9?(i*>iIl8U0)i6lJLvQ(vM*Fzd*5n>2eb3iS3CQW6CencHTDqp{BrvI%$mx$
zNh|_8f+Ge*zWuQ`R}RY8{OmGbC$m-WMC)+dS{{PE{y%dy%I<j<yZ<F?5FBf)jo>SH
z-)H+M&H%~~z!`7;@s_>g8<*_2bJp!d7-5?xpbFt%@RG{Db!*6ueckAV6v7W@EMv@8
zzH_$kGGtUJ!kvQhLDoM0>P7MKWL-@Dttd*fE5ODJp=Ou#-=x5P?87j1w?7B#><idx
z5iX985IM{B>oP~5>gkAs$FQuZCBY6qtvj>)H+pbfjPP{L#fj@QWsW1Rw#qdKG$M)c
zh4dIb%fB(PuPNvWvIT;5UP=jc31qc(l<v-F>g_`+0f*C6Pj&^b()bR)Z@wr@yIJxw
zb)=sle7NwfJM*%L8=w_jD<oo6_Jzv1@|-^UR!8P07R(MU$IvCa;h9^b2l}F9J7J|w
zm33^ahC5+y8=kV^Vw@Dfli#7L($x`atO8Y-ps}JWm&m;Ohptx`noa5O3<+TaFHQZW
z<^$WrrytEELFE{1J3?k=b%B+hfeMJ=>-(-Z1a`<f3j-z{shbbf=%Vy68@BUR0%9)e
z!PF*l&&9kY$@buRRyWpNm=lhRWVXjXvry;G48M=f{B$N=hPslfBzw3&jDwe!c%zB{
zl_$%6Za!;u<%|#(ev}!Bm*IZ8-rlCPX+cAR!&;7c51EUaAe|Bi8o%$837{~vENP(5
zdsQTlsXw3l!q|Gg0)B)jUE|s59>$nL%86w(AhlD(2^fIsBUZM?#6~kbZsNErNyqQf
zBXp#_KDBBB-%|uyRzR>bg4BoA#sir;r7{Ky+lL;RTboUJ)FDk4E2QVXrg5ym#p}RJ
zn$3YN_-ds+3!zEWX&m)E1laltU5DDb_l{a7$$T=WakXpYU2jgYy})WK>=3wL3Is<t
z5%HnG(8%N51kh(LVpG7W&LzpCwM%`P!7El2H&%KSvNO1yqu_hSr3$spc{`=!t9flH
zYCRQK;1u{-lz$5WW$sL%%a`6F{!Ho%QrfO=eYTt#v;Y&Qz=a371d1^-qGy(ehQu#P
zB;PL3A&W@P(iy-QyZmrO4qTmbq@MR`O`)b<1m6}2k?oeC(>=Uu3#rhT|8$Hq4EgO1
zu1Q&g(uW42hZ!TNlie;8%<ggu@_Cy5H*evk`2S4Dy{SYWwd0C+n&lo{ABi)$Y^@!l
zGYp#cy=yLTjyn1O5JVntMbTMw&@!yre#rZusPtkzMc5;Zn+4hJ?M!n6hkCEgjUd;o
z1IO4MFOuwN)h+CAE1x~SJg*bJBQj^!R3}9G3WtF+LzQAXXpHG!WVYrvdkxUHgYG;z
zQrs&YqN{R@;&?Upp<p+i`PFMJb0P!%3wOg5P6V|yA>OpU$Hk#=)AZQyD+6ZwCZRoi
zYcR%uK5i2J_;ubUrOCMdN^G(E+a5b;IkH{F4w_b)T_Li?Jo<~?%gYM0_1<efmKfi5
zg=b|jo1RzlhcEQ{+<aKE)sQc|ZN=Q5&Dkt@vl%{Q7*W1`Nl<sA!=e&_UD=X!IlG_b
zVfIM6@9;^wvlb)%?BDVjxpTzls~;y~KQ(Oa$fO0usj@ja*d&}cW~*va?B%+Oi72kc
z6NP=P54_s4&RL@^`=PhzcI>kjP|Fa2WI<?sb_7K5T<0&Y)PHnW6e5hF0L0?(Epud9
zlL_cZJbE;v^R8)Emth=g0w8E|!;79)Tfgrp6EQPCUi9Lg@jVyt)rs$%RW)m+LvfAr
z9qv+>VB5a%P&q@g-rPMb7U0k#Z+I@+r{4FxwHNGF7g2!gRvr-=W^3N*A=#gvz1Wt>
zi+{&D@GyLR*77$0IU76n_Y9JLD0P%aIvkovZ_s|#CFSUBj~&EEUe)9lqN*@!ugS5N
z9RsbCSue7JZLJWYtg^23X104v_%5AIE@>XSEK4Z32Z9$y&QI(DKOi&5)tw)>MyKv)
z0y0~B)VK!LGk+Fm<6Wt#!0~z+wyVeyY~%gmZ*)xauaJk61ReerviRerYc>fBZAkd*
z(WS_?_rFUG*rd;J@eW%yrnD!Mr!06}O)oPZPJYeOaiA3*<`x7;^1mNaf9=4O$AT69
z!=I|2J$7iXx=TC!CoZ@5=eZr_H9hAD@!v1yZi3>!v*_Ut`u<^2o8si$A7&b}b=2l3
zLyTS@OZVt`0+*P2i9+^MPat(&>qr^tG!#m6ayo_>v1SJOVqF4JTJ;QIiHf6-&ArVj
z8i~nvyih+EBK?H1fZuFR7ap^!`|*(t59ev7Gt{yO5smox)?4iUJ9W&U+uf`}&a!G5
z^1ZZGau!H26+{rhv#1PIc?#4c?FE7p>r>+KvY8~x8!1X-PZ1ns2HQU|TJ4Z$v$hhN
z)DxH;Jv+ksDVcpi(r;KG&vv^s*>a9tEOn)N%6Bn-Ak%njVXu!`YRC+_w|y*@DrB=7
z0cj~UCc%@Vdr?P8BeB@2U8!l>k{0bjTtO7}G6)i8bPl@29a^!E1T%6qb16|Ou=Ld4
zhD?wgZNE(nN?1hVrap(Y9m{^(#JdMpHf75Vio-Efl>t$>QKnF5v+?WRS9XXVF5}BQ
z`09!o!wSkJMHV|%<tA-&Pa2?{JSmV<XZA-3od%_`=!-l^W7=6BL7$7Tu}-VweG1UE
zS2yjAkZoOoP|t6Y>FCOsn!sIy7r7$ZHHgBD)~RqO@tg3sM$eLsItw`+oIK0?Hfw2X
zg5iCt%%UEFnXK(iuLj}NyHmg>F{Joz-9B8OY)}u`wk39bqM#q<0&GNgHxWp2J6vP2
zYQVBsBQyzJlOQ@2Djfk$Q}8`9+3q4yOwx;y3>QP~*!AYDvj(Boe3L5OABZ<10tFZP
ztTvPKKH!ZkHwX9KQM_2{HBPp39q1<-&T$2Uv<LR0hO>)X?A8Z|N;Ha@7$$lwf?+1c
zFMq{kap825LCQJa?E2CnYf!|&aK-*?tU8-!`6wY;TL>S=3S|GTUeE$L{)9RZLfN~N
z<0~)D4`mP4o$1-xeQ}b%r}-LI5+d~Ourf^HT;CtElRx3TEq$7*<<R7Wt8yZWvC6j-
z@}R4}=~&%h`M(>>m(=V@9R46LXKtYecg{t3xr~V)JC#g)xAkT}eQJ2^zt`nU>tinY
zqO1Y;2a^9uTs>)v7tQMM*l4Nb<)3U+@LlO@wRLX2WlOx<%0AK9Hb$bYlh)lz`~GX3
z-%pzi(8<T&WW}*>FI#cWmuxch-bsIWl`~#DwSohTwId}`*p;Osg>@rr=d{TCiciid
zERSs8lx2SXQhe8^r&U-xyQmi4HXq+0wZGZ7T$W22W!u8=xiI6qRTje7s?raJkQY2e
z7<aj6F=yGDnL}IHO@)Qu!1WOpdpp^r*@+*3sHlN$PL9p1t@IX2w?Q!xrJ#D>_VX!M
zow-)ge#Zr?R^3=r5!xUKLg=%TSON!ym5Zu!?fq3UI)yP5ut_+d{m7-3W1Y%O6vSoE
zPf)B{(~PUFDuqQ#;Rvg()&9q=8=n5UV(}(IZ2tRrG=66k!(orLhCfLdf`?CJc?R3H
zU;dW3)`Fwk89gkC(C%Tr_yCg!Ux+5@c`>Mc^>02^WG?JkwQMwB)0DD5s}?+x+4(ZP
zxXhF9%|GpJ?H6omWlSUKR2IEQaI{|;Y?i^JJ-|jaFEVujE{2aSV^F(%+$mH_mqI+h
zh_d#nOD){+VkmsVXB|EKew{gh$Cy5gC_)<qUI;Zi3-Tl{nm8|5?>Ko}Zwfob?tbm@
z%A5ZV&2Y9A`j}ew>@JRsvZhH_$rpYUlb=M{hu;$_cIyW7|HJucwmvd4?X$1AWVS->
z41klMGK}KFKR=BFqTpx8+!+x;9dUQ02gRjl&P<pi29$h#pUs<j6^VYps9wJq0`gE4
z?jZ_p{e#oA_X{@^MRTxnPi8()YW@|c(qdhB)am8-ZNZ&yb5HYBu<rAS*P*!Kk9cM@
zz4Eqch7XLoDLef}H(W~RJ=>Lis(?+Bq8MQ{lh&b}geH`Y5~-S^Tl4-FWBZ8=hQPXq
zCqF#`nik)r+4VlBN{?mQt#=O{;FE#ApMpqNs7l?YphA^OQu1yq8Vp7cT80`q(y86M
z-X8Wmkqc15#7O!8yU^?8Wt-ZvN*=a@8Clpn!Iah8mm>m7(>t$E3Ap%VgIFzNERlhf
zy)fE5Ub!i^5uP5eRTgivDJ(27xGp+$j8Zg$`{0QQ1=F*WEqnxtfE%ViOtQ6osg<id
zX!uz}5AnN=CqzdWK}A(nWVXo49QHDyS(}mm3pHOXIFl{{8J)YWJ{HEu<T8ObgWK%s
zyF;Vce#nNS6P=56?&QZRp7(Ik<w*kys)dtsr-r5HC>d*YeE%ynDPd->!-2lj=V>IY
zO4H9a-QKx)#OM{XI6~I7g|TRZs_hMisv{h>m}RPiJ${r-G@5WGXw25BJo<~`7jzf8
z;}`hhag=owOx_^?Y@gdJ49N?>Q5`0gv~o}+(2?u9Whl50ewTh8B@`x60P%>9r{ofI
zFI}X`yfdLWgHWMP;NsoaEftSffC{i9M>8=KnJ5&vw+HXy-sCx>Yc~oT>kR3XgP(5F
z%cd0sA8*tq(7aG0D0(IpZXGhj%}eoEMEQxr7VCztWT~;&v?o-gUcm|K5)NH6R|jo#
zLmwWD2us)l;Y@eJ*J)3?jo5RX)bBF;cXqRNR>Em0+XR#>d$I`0_?*#6WsfHNab1Ih
zyXbU#3|m-j%`j5+ZmSRB&6CEIK73AkKhn9ZEW=w$XN%9kOkhkuJYZzlLoem>8jAL$
ziwS#U9=4Mq*V;m3w&sCJk9Yvdy2_FhRM|(IT6piZ$dMrQT}{Zg_x1B#m>VH;2Uqj5
z>mpA0gSO4ALo!@#Y@$*1`LR<IW44YNn}qci@Tqb5k4_fWZNg{vO<LR}{JXvhdNTKW
zzQ^0N2t@1eWD(>Z1S_nM+E?#CIA!^#OrMO8aOrd1h-{0+bzT8|_*T1yh`^R$&xx=u
z*~YvH>ARRT$Mzkxz5ns?EbCtS+|)-7Vj1JvO>AH7GJwr_k+FI_=?askEw(RvfY}k`
zk%nc`n0@>jkJ&m|=M5Piy=|&=55G3HVGE!Q(?^Aszx<bGUwf8icW~-Y_CxOxgB-Ip
z3xDac=DwZLB~f=yTm@Tbn(B&^gVk1JwbeJLNF~V>Bb3hPIdn)`*RW#!Vy<60A1b$H
ziHgt$K@dWpT~bF%^WcTNbMuWhq=+sqOMwHg;8xvl@6BW;Hjk8`R6qEi;*ijpc&PB>
z+Uf`1#(KizU`qX7cuXhwTmNEzRDVxqD{Wyg#2jE0yT}$=K<~~=Di`0i#iIj^C6Dub
zn<oEZCRg@T=VBSZ{!43y*;?3FUY<nuN<9qt$EYITzKUgpko#~F588rB@CWD1tj)C6
zu|U|J43$0E%aoN^wLXRtimqjjfT)muPc4+SkFu)yC=Wp8>hNe*hJSkr%U($52^b2z
zu=?zpBo4>Yd5ja^+=Qqb8xr{JJdGoEeEk$Y>s}p&@&tJwd&HAC$48d(Xtp+eq~;IH
z@Ve}vEXw!+90@lZ&=HrL``dGGu+g5zP9&$hi$rpLo95us7-6)b$YfUW67I`)N2SX*
zBz%319y6HZm4xF)AJJ~o@oKAeuUw!gso_43WSc16zp!8o@psBu(9sq5Wvm?o;o-Xx
z?q(dSHBSOUs!|MpbH=W*9Y}~Xp_ofzrQ8HmPJF7Y4ah&c=FmA^-iCp?@)5JShHY(t
zHc585hb*Yh>(^XI1B2s+V_zKUem2ehMqISUXsN_@jpN`tY{=VwOYcdAZb6f;6OsG<
z>c+`nu#rCFEhJ}lGg~)f24&#L0++Bk_>A2?rf|m4g}3!IE$e-)twFRxs(`)pz)u=Z
zX?k^ucH|97!UAVueAO*NN_so)y@VvLc$!j4NV{F@rji}a_!uA5CTvBCo3>IDDnir~
zRv1ND>CtDmU}?kXyt+2f`wa<WVZ_BmEuY!b?QT2~3c3hoM=bNrT1e6H8g^5u+lb7A
z6O}-B9Me6?iwMQ+(vA?30v<@v)1qU+3N>Kg+dWF-`9sajp4vDuK`)>)BV%`Z!j{PZ
z8E2}PH8tmbZklap_8o+vmC?Gec3}=%Q6I-r>@vR;c!^jhp^p^UDmrcV+c9n5+Y6Rg
zKC+;~P_1GPs6a}_-i&#?m^{L-atJgCJ_4;JDO{tg0*|XxOmVL;JA1~CxR0O+*rp=J
zDO5|S%Q#f#p5G}b1b0>2c?@!36)4N3YN!Z(SNI6ABoyaO?BuD#MG1o5F(D-P?r==g
zH$~AJsWSS`EO^jWD&*UDZN->7)dyh|QRHpt&1%!+GG(&pC5JdHaSd{e2g@9Z1_Nxn
zHm_ZqwVHGSEI>IU50E(-r3k^VW}=bc5%y*f)Kw^wf#P@;;<(ZUu7ltogBUdR81+ZS
zy;l<7X2$=@j+z1eK@5>Hb6hp5#ggqRDC1eMP012;JJ?RbjPN^-d|s1&qB0ne>@;>w
zs>4Vds4@A4R#fX7&y6O2oBJ$75Xquh75()j7EstU8Y7s|&_)C!Wke56*1cMsLKH?4
zC0Zw7Fu>M{y0~dv=IbOp>>9RvVY`^*5!)p(5x2|X)g=z)X_Ev4P=%fsN!3(#yrG-(
z;B^dyAl+Y1a=G)FCZfy~;Ui74MWvjS$psrD<?ZZX<<)q4l6`v==}ZQ2FI!3|U=9FS
zoJMOvlHH>HMx=6BZFr?QR8Yg_2q``_mLNyL&&i>DD$x+&BTl?V#o`SyC{c(J@^7$p
z@`{7N>vF2R3L5|t^+|xIFvYeJc{fs$JnV+BHSS4Dww2f>pHuNT7gZ*)kDyX7!B+4%
zPefB{F8Aatr{ks9HkE_-gs9UBTtf^bd>~W-l+^h`Jr0?8K>~fm2;!>Tajn7YF3BRu
zp=V5xPf|Q#a7vjCM<V8}*nyQuXb#dTp4O+FltG>+0n!FfMW(*VYEZ6uJPsDNCq$Z9
zmpk2BdZ2NO6z<2-<(DFYCF@*f(~@#P&z1X(#C3>9OOY+t0nj5J`4aVK;t(xveF|N5
z>5@m!+Mt}2d{M^x9)s?@P3Ww$sZrY)m9djhK;IqEdJwH5>dDI~u40na5jywO>+u^y
z(jd(VM^9c=S`T7Og~oHap=Rdg&<HawQA%)yI(~uQU`UenQ!xrnY0$10i9BT8!Bn=v
zaD@4q7)pZ}p2lyAjc}Z6j}t!0A|S(}C(+v!(<}r60sTa{cZV@HVN6MIDtBI^ifsd~
zPs^LrC;e<<*5>I+)~HrNgOuPmp*P8PzI#RW>fG$*kkS}H7<DET!AfQ!dXxAazf)k@
zc4t-DOJa%zQcp`KPZ}B$#gm|PO4@V~V4t3AT&g~rH&sbAFr7cAaq6zdJ0z&2Y7Nx<
zQ%IdWsM<FWm_}$|P3$S#RK2-{AkRSXY$T;{-c5JoRZZ?`QmDlEx(vA!AXTij$(OEK
zwd*ISqWH>9&_Cq%Me#OMcw+9t9x9wY@|q`<n%P&oi%FXr!duYO1KDDmt%UtjT1xYW
zEZcnUy-tWBt+9L^6>E*fKAAhF_JYSb9IRi*Ztpu#M(<K3DD0|i($<&p-z3eT`rh}~
zl=zUKn2ZEwAnX(Q0(+axQH6r=Y$-JqId=tr@()~L`|f7x=l~xCajP4-yWjGWk9ks$
z&|-fnQr$$#PgCRz*`}JcDH6%f;isW2P#$?Mwd3u4p6w}tvijqDeQ%BV?*e*mSeg-0
zp9t*F+>>(OS1~mn&4R@U0zAL@{8y;OEZeMmwhAibHf;^O`Y2XGZx5w%ofYon{%~4F
z2lF&=goL}PGJD_TwS?gDYMB5E)RNmc<OAK5acx2RsUB+;T`_qH9mC;^&!<7mI4e(t
zC`WthoMn&(ga5`QoFcqpWq89hUq$Z36kgX~{S*^ef1PDvj%R-F_X&w?xd(psf&-fH
zKr)rL+O+4lfzrE&qb_(NIRaUssO+(3l3!GYf-US+f(=kEZbJ``H^Bq$ocL+IKc%(C
zg_DyK8+j?WtG~RGmP_`%Ajzw#3A^=e!RFV=pA()IUoN_fsZzeEG8F~;l7feTtG_*E
ztHPr)*x`>n6BYRuY$vrcsBde;i1@9KY&3Hd|F3iYVmQ3%G9IueLRje)w)*awynA@M
zRoFS-o8%eDxW(qI$3COiQ0^-)IIyO%pRNCW*0cZblFTOlFmpY1NuAr!t8%LX?EM{$
z`{(G%D(X`BOG!qk<JU*=*?U=r_@_vA&q{Is{X9Bux`x5)9V{-2%23d-^TOU#8MMZt
z&D(1!?AoD-nNIv<Rkbx%^fWrBhy(%Q!?z%`4!8A-kEGCeeLkTl8$XLL&cEe=6_3Wu
zhCAaLOB1{6{VR>^)F}Hx5x5qxE&Ho9^#774Ab~5wMGUzWa5buOM{(T7@HwFN(5rY*
za<(X8gTOJ%M1Dq5cF23~-7cx>?U&j3x2dV&q64xdV0dFAoGAWXUf3<a%4{IBZCdj=
z4ZI=T%uIXAdcRKOr$30q>o~OD^i)Bbx}okTk%u6g5UFBi5Ozk+xGpm$@i=<;Vz=7w
zTUCV<D2ti(f_ziDpc)r%gDwI2yh<Y44OxgXV0Xm(E7QIjl~nA}$Mn#z=|{po@216+
z_>qf>)J0#qh_KT|v)H`pC*%WqO1o4UbjV`Vmm-{UwE^VzKqj&1oU3I<;3>%lLUQF3
z_5H)lzCxjzoFO1)=Ty`)^9Kt`ppAUy49dfS5GSm>@i7Vy{p60+9m4jvI;;gT*M6Ld
zu-_vfDlTNRb2+BsGyxL2m<kY>;5<l2Km?V+K&V<i9w4yz5?1ssYpZza`|4zoQ%@eL
zCHl<aLc9()%e;#>T`X-HaFvg~0hbpr$xTa@c_e&Zw@V4&jtuENcbT;t5ahf)`cVzC
zNYGP&7C{%Hz|89!FWdvaCk?R?VYW7eLgN^C59)peO@3x^AIV%s@3Rr;aCaWz(uYvH
z7JR#x`zxu;gz!HEh{GCYYbvukfdU1QZE~V&IVN<AinpoICBX5MaK3DD9TtKRdvw`k
zxWEK%uQe%YYYP;!Yqh<~&ifdlS{0&;K%X2tT`Rk6b5z*udBSeWlz+D+y@VPD!b*ch
zl?b(4jo!(akoKJJ+iau*-*R+52bKo(-C<dZo_`0;4=$<XsPRE=L8L;!X7G5N&fU?f
zh=dA9jI9mo@6G^tz&xA8O5{Usi=j>q$51dV=kE7rGc`r8dz4Tyd_B0MfbGCVk<;NZ
z#8XLXYiB#;VZ)rVIUe^6_O6JDI>RQd@t!ADZGvl^Ws3}(;x4~Cm;sJ)7o&ueXuqR&
z(|e9}InQ)r<!hdy><^%qpF{)eXQJlyWMg+YWPoIWZ%{i3qe;xxG2;`J8}POAsJT7N
z%uS=<2lm?N(Lb>Ly<WbO_inHvT(U|T4~E{!KUkqz(!d|0Z$bVh(YW28XZE?(+?L+Q
z!xgjDZ>Hw_w7h$>Vsq$*`$TTtPd8m29eiEOHxQnXE9GC7LGJ_4ie~GggODGFm=K$j
zK$JrD*GHq{n=dZw_t)w^Nmftwxa+RW?kUG*NtJ{w9r(?=?T>Cd*V%hN;e0&pMHB~t
z1EJS?PZ_5JL<@!G#m}da5u4VCVAGlhtID~|{#tHf?X_0Egt-C?>KXe_msHbZzgNUv
zbLD5=UN>=2cZF{#3rA_{|9ZMA#=G%>?3LnIuZPJO(ZnYiZuee@62w-D4g88jlv(#k
zORv@>tH*QSK>2Yt-oE4MX}CDj+Q;$aFG<2j6rm1;&FrL%211-pz<zWMhVFxaJtXXV
zTz)xYN$f|L(A^LJJZ~*gOLX37FGf5{ezXzrmN)P+J*A-IPQ1+4dCq@v9hz?QwGE$W
z47eVEdU)fDikuu&E`64Lkxz+=t=EfpEBk)ZC3$Y9KRd#)N&4ET{f8UD|BqD=ivP&<
zBX(^1QY-%HDV@y@%-5=SUG04NRaE{sv_3-_1CC$szn$%Ef*r2@kydF_yiIFlm@84B
z`rlz-b|6^j5)hT{<mjXPKGo~t|A*a-f0Z537Tbu@am)+}WhiK9d9cHllDk+P@dgbc
z41~xw{{)$gR$-05G&U9OM|~zEMchF%?zQN)K7Zf{ugw9na4}nT5LbTBA1!-q-9R@Q
zbENoP!DG_}2A)n>nSVNMkUp-{W)}Y{=6WB<oLhgjS0L6YpF#1OwNu`%Zh5o+n>3QF
z`*Kv!%U>a5bU5(H8@m3tM!o}=bv<Qj2&1{@<O{5|J-I!6QxmNFcc@6Ww2CXj(Q>&7
z_l+anf6TIT5uO9VXeCi+G2Cs%dV;>LiH?6FsjGZ?OEMY|{w~#yjRSI02xD<psN?bO
zXHXDmXA!*S{x$YlOq1_*@PJ#ef1Ad(!V8nCpAdB1Jil~_ZIC6og^~I(z_Tx+#Qv`=
zkgUTTF3NVpHP<mKN>UipW@HG%Z3C*crJA(Wvh?GoqKgbxnOtfD+kr%290$}xk>KQc
zDu8+|ZKLNi0p{BS&zsPs=_t=F%I~Zc!e^pl8Aokq|ArxP#j{53wI~Cli*hWaoY3f`
zlfh6W-E5i~Vw$Ey@$4n-EF&Y|<H%dpCoVc0b*=8$L^^YY*aUCh6|@njz#(CpUMFxO
zL2%2Ykgg(N>u`6IHWn&>S`~@f%yXA;PrLf0?ZqZtqk^zgg3~DM6wpv4zOxg~&fzMf
z&5-j@xtms^f!}ne*4wj%(c>>_K%RPH1ycx}U<DS%CNYGtGyG=8vAmiRaKfRCQH7fo
zeF1E}?i!#lBcjq}`Uw;*=>pCPWuar`YD_!9<2gnQy70VEch7uLZys`MRF($LIRR76
zCeh!wdMVU3k=)lTtK#TwQ&`^_Yr^GyFOIO;^Mu{x^2vkWAR$dIS~Od61x3_FwyEUq
zN9#cF@m80<bT$mkfE4nsP-oL@o|n4;kE0sl;`pKLt>w0i_NOS5e3e)`iX1C)3<Hjw
z_!<$q8vxDHi654ZZPjPvlU4?USC8`)n5{msIys7>c;KHYgh_iI6UldR6b4C2pNAK=
zZ1j)Mn$LST`Tp$x4Ma}ZA2GESG}M@FF~1|b^LHFwI3e!m6YE9?MC}5<^)9;ge}XFS
zVm14r^O7DvX+9;<oW3Bgw)R4>`<|)15pWCvNB0(^>-#WZ>5Fp?gz5Qzl+XuW{o}=|
z{V;9)p#xKCi_YdGf3SdWe81xj^-Yym7`<aWkak{eT~nU-2VpW<atEdVFP^H^RxN}w
zEJPvj*zqwCIrlFVqmxIL%iix4QmUsvweg>GcDQ>(h)0B!-zk%}RccqC+_M~dF9lE5
zMt(`=W*=R)Wrei=-1a(9R5x}9Fs?q)DnjcLhB|Mxa{btRe8?8p)swx;XKS+&t!iCN
z?q_`cSC*5vyn6?4JazKB&A!4(L8Y&}4ul!aug(XLg;93roC|$8@t)RH_^ELlyXkxK
z4uX0K+upxwv;QSy>UG>6@l#W<B~-05@Ux$pP{)rj%AAVa^V>kV5#-`$D(?u)-pIiH
zu^Tp_2z6Hwn=R~AOB!g-4=uomgN-I)$9uO%lnuDqY_&aq!XWcYX7>?6lK_on*a9O}
zrBHMh&&tUpp{fqIzAeL&{mE#y#;Qfc?$AYFvRAb9o}aSF8?EIi4;}D~6QOJ$Px;rc
zm=E+uU-}eJxj$t{_02t%J#u~54o^Tz${q-$9?LFp?edkm^$zlg-M2rc>yGaAHg_#n
z7G=@1A0%J<_q#~5Ux44f#E0trbs0y6h@FxPrT0R*-8Q4ZWB(O1p8<*c(r@iG_aU+{
ztYm#!9(u8ibr)biMrfEN-+-&6ik6l>!PtzP$`kvjs9G$1AoGe>N4zd0wW~Ge@Nq15
zAhdhTeb^f(Ej-?G>Lb_mk;q}dMWl78_r~l;=>H?Am#x_b<zkUvNNY+=9OQwwC?4k_
z<6lkn{^q^*>hAN5Pq^w)m>QPuyFuXi(cHp1Z}A+A4I<7+Gl=)&ci@aXgAr5C`>k|N
zzKE0e7a6u~4?l)LQb{<7WAyyoFFAZyiPVz^9~v6IaSU~ruyJ&POq(Ehq>6%t84I?A
z<Wt^U;d8q;p^Z`a&N|K$wL+7MwQOP&iJ_d4D<l91%V4pXsOg$87mT5?AV-T|<>W%F
zaqyf+vd~k=P8wHSA2g^Ysp^XMK$Xtn(ONGp83JB$l}xo|99uzB#wE|K!Ho}U5mdMu
zV|&RNV$hSnv>OsNlg7Kly)H)fQs&uXn>vh+y_*Lg6NLyF)kRLLC1?goz1TGBNR|BL
zn5||VJ$*J2iLu*WYPQ7rFwZ4tcXPnk;YV+#il17b+!O@u$SQC2ZHTZ+kSkfl$+CG_
zJ)HIu(b6?Kces%FO0x6s86A?70G1PGyrlY@io#plZ>4q|A+4Re-6yjyR3hK6+^V2M
z0`lw#UZQPUZ6(7)Kp=+^ZF5;sl&+gq#Y+&>DYj3F4C>q*%U_3s>c9pMrd~WD(W0Co
zV589R>;&&3CwvZR**P#e{KV;nHjOKJl0#P-k_WkHAyrT{3p52A3t4u#71d-56sjfH
z;lLfY(t}#eF$3`uiJ>e`*z!V;P-<AH+S{BWzNiZ8!4URo;1yDJL+oxg#g?1gPuN*V
z1#ll43S|mAW4i>5nOq<OoNXY=J5PikwTQM2&W=Gf$z#ac&o^NnW-M^kKqpK9FZ<I)
zfYq-o^9R_i8?cQvcJ@vv%5gR@+g`OI%uSN#@taAp#?O<Au6%x;JFBfBP{-WOGrS;8
z<Q5S55JO;lIyiz_-~``gy%x`u&2a7K2KUb3cZ{N)+84+3)+5(BtbtU%J0dp`K@OHK
zGkcynx%+Sx?dEeWmobc5Lo~05c(Id#ePLKLjGx>w#!r>qcdpAiZ3r-0s^=PozB2?>
zrU$ZWf0%Hbk6yWK_MBL~!k@Q%xz1rv45Kz6e9$o@=hwN++F@py0zHRvb_+}PFQ!5s
zS8Crx9tMGG(E9t9f)%`H_t2FTVK*hZ_8Im$|33ns3qgt__fa0{703;OGu`W1IK*t-
zQcR?%;dm_SEF1mm57=ngp-wDmXfP~DvTXn|%=T5^Kp$&peA5EkHpr(0v2;0S%kK+O
zufC4N==kulmra&LXznicTJS)lk29R;Vb;`UYf(J(4Vzn;J-=*?{CwtIO<>Tif^F6P
z^|KkZXb&uhx<I`5z8AQl?=G<1=c7DxqVw=I8S7p73X8nX4*jDHgPH+zM#&#}yXDcc
zz2Q|`^u06pZ(YLj+UIyy|5P!xGUiHn@rlxN3Ts`ES@oA^g=K@TA01UQu}p0?@N0eX
zddsGb)hZJ7H5F$PBg&70JU&^3*(JK4r?c8Rb0<?IptgsUE4Ax}ouv*TmbNdyjzEy|
zaj_f6P=IwBmV4+)q+CkUe(7tAC7G>Fgjd7}S#sFMnj;7-m*eICr!M>%R#(<rw*KpH
z%V$*TLxFN|{~edu5$a$$DOymg1@{j~p7UN{nIqJeKgzPmAF)>hCiboCG09c6z6r`I
z%67J=n7a9**yRa(H>mR4s7S|e^jXhZKL5-_=0Ml4I%^{L_x=dO!G)Y>?f(6-dsdB(
zDm510OIBO4v{6%EQ%If8<vR2#jNl6(1Ab3?`&T~}oV%9zm@z^Jf)M-cHdTgT=Zh+l
zfgBG7hlPc8I=a4zJI-169&#hIwT=*B$B%qH9obJ>NUJvr@NaQx+wju6so}$zt&uHB
zdG%r3(al?amwY}>4&o@%-sIQB+6o6U=|9LhhbL(^k6${!H!}I=y_H+%9Bc1gD39K-
zDFdRl9qfU_><vt;+-LR<Y}KMe7uO&%<}?5K9u4#*Ff8X|xXLfVH~+V6In4NH$I)FA
zxaB@$Be{=K%w>$~4(8glJtXX2UY%H5L<&Wus-yeP5Hl5MB{pwc_2SWOsOdE6lM1}M
zkvbTVyb5(lgJ4-#&Vf&rzAnx6#CDBe(qO>V2j93td}Px(x<HU4NzR2?B6C=@p+f#h
zqru<)9#U)APZbS4P_hYzzYYiB=x~^8iS}DrK<@oXg(+5gV2KEg&S66*Nt>AFj!+@G
zxyt%-A}vZoK-di@n2-Bc`Z#bJ5+=agEWu&yL3AG&SGx@oq8Ad;I%_E;uDm+c<03?*
zgEu5B+njk@g?p6<C*AP&P1Qp?J&|GfQU&X%qAB*>jCq~L-vN_1E!nXqE(>4?(4y)y
z*^<FCRrz(0j4)FW@o?rWA484S_DwxY(Rf{6ueR25rikVmCVdl5>0{$FaZ^~YiGDJ7
z-z1i-eNPj(>s@C=*J8zlvo&@}!z*3w;RGs8G$Az_Su*N&^3^*A9Qldg*4SU;?{*7{
zT!s2fN3%s~9z*3Oqa}`p{B1Z!Vd?03VW>F?5N28aB?1W8B|I)(Y(bHuX?9l;y8z@4
ztU!lds6L`OuDCMQibZ~sMc|?-3=2WDS4fF7PP-^9XOtmAyTFh&ZG%D-V8eT=D+zOI
z=q`Ro)?%WA40~NfWNZkC(P_fFlF&X6FBIj#@$>x1@nCSE_&%EYd$ECNP~a8{aC3xt
z=9AXB+X1gD;BHe5BVFN0=3>}@ix>qq1<n`L$y=$I^CY0fS2J|Ka3AYeNyflox~Aqg
zL?v{}gJ=*COLhO>MaaYk5J!PDKNx~g9@y)ax<5}dxWneFFP{}thBrrgZZBWw;OmaQ
zU$jcGHqv2yQLxGx*A_;8rzop%J`vYagV!4g@b3hnjwrB}E&prud39n?r**zJ7Bq}<
zI!XQ!|A%yzuVjj_aA@_KX12C;OZnTe`>)y0Z2#gA83rX(?0zl6DhCI6Uv`i~EIFyu
z*3R|g_NBB~MNl5{>U*c13avOai@}ORP@Q;M(0#GGlNm_AYJJTpv=4h(0PK4PJ9ZR)
zmb5&8Y(+FE63uN62iT9R;fG#U`Mqzl>f!49W2$}M3FdI6lO$zWDws^hsqP2ZBwS)`
zWPBvj+3ceuw$^(oY_H4m$&)t-b1*nipk9OvKgWK;>HxGoPa``(L?~GR^yOO%=hxZT
z{i<{K`{)1Rk#5M^S@lKUrd3)SnaO?m_F#UzwKrc`swNdU09=(HGP^mzV(B6)Z*nt^
z6bm=LbS-=MRYh3(;=B=OJQH79c3Ky5BqErhEV}X0Fr}!QpJw~jH{Je;(JH%OKc$Z+
z@H2!@l4Uq%4pZpdrL*Bch+AkSZ)%~Q$hdg4eJwhLL%^?xNpJaCe#;!jJAS0lYHJzS
zLoqBpg&(KJx)gqzh&cRhIxMZWYH#wKa)e;<*ivO{R|v#ndX~E9&D060Ix%at89nyy
z*Jqt*8-M6GDm(r|u$}mREB^cUr0n)?<Crxx>76|n{`D6^A-FTBO|%Y97Bdgemvcwq
zmH$FSzVn+|W_OP+7I)r0X<k8-D$PH9Ulu#PKl6M>25h<tv+lKw2fp}h%dY$}g8t^l
zLerWl5&n&Gx!r9lV<L73(U8`*&`L>y$etlAHTa)6yEqH`(aA5`C(gxr75?=sXp?Zr
z??@G((30-RqoCL$*y=qVPgrLTnZhj2;mp>^mL6LcOMh=N-+F)ma23CG2zJkMX}8Ty
z3edRhYhWDh*7?l$I35MO)NvcvC3Zp%1Pa6$-wU;BFSK}XIgY+Fdj)3WL(lN$FN(@l
zHh8P-=x7=e7B*j~B__C-^^cRK`EZpF*{kCF@=es{yOc3JNV1_}Lzclw)VYSuXuj5-
zBh)JbMJEWN>-hzzo@WV{hQ@(AP2U&uatr~@a{|sA5ZSI#x7-ZPqkw9U=irMyGv^^^
zEIO{CFn|o>YtuMhoQ6HCF?7(ygOI(Ni>j_b_eEN!oN#res!+@;F-K<P=E=V-v?v+(
z+)<S!vqsNjBh-j(K^Wg1kTAmmTiMZ5g5)UF3}a<>b1B?+(>-3Zwrlsw{P`BJGrS#D
z;4lp)CT=bsM|c<#n_;PCVVq6Ny&Q!y&aCYDl;M$VHWWp$gB0kzDi|w*%R!<BrN2y%
z!yy1vwpTD|dCM4yJE^Wx06McLDAGrrIb7A0<qE-&wGl_PjSwn(7*-Pumr{UFH&WIC
z(ckG&4V#!JdH0AW5_(uBmmIqSnV1E^^FQAaW(y~vKy?g3vNG7@8-Zqyd*!(po_J^G
zMXRlw;3!dpp{Z}hDcT^hi>b$gN9kpme5NWEfdr->pha|UNBDWleo|q(LrBqiPwle}
zp&V|xDcJLiufo-2TFxnNp%<H_nAzo^;FIW`xLLy~)pl*N7Et&@Lf8#2+bwd}xHa<T
z6GpX=B)y?8oXby5yL3uG87tB$frGuFPq<M|KY%t8HdRfDum-_(5iRO`dWUC$`6ah1
zSp&a;;2GqBv}leiBg-PFo2Q;$rn;&Jr3SeXUYv#MvJp%tu_MR2>HD-nE+-VE4!VCg
z!8NLBm^>gk1_A0SgwtjBCPy-r<1@T{h_vA+N&SF6G%vV=M`!PD>qXDWc;&(jYS3Kv
z$k!PS$0M0E$-h1vTbHPi((YI(+sT&(4(r)u8Se5v{|mZcLHAMUSNm3Gj$Uc^`wxz|
z7+T#`t>lMBmPfnumfL%gWe_;(M!3Wli}n3hcG}K*A5><oc$j?p4+U0R+eZ{YiDh=E
zcRkzKE{tzyqL7a=?0*g=d6L!M@CJsEiwM`fAW4`KHP_xvE>?oZKltu;L#YDU7lPE|
z9vz7?%fBOdVw_@c;9X%Yd#?Z2b4)tk_nakrCMFHyg@Tp1kap`5!@I4C3CHymF6YY>
zSD&!ew0w76WzRf0CwjYsN0kngGVTR_lljFOzu+#DX88}#&W>F8Go=@?QOs61`<s|U
zA9~5^>Z31kxg#|E?hz{{-b{J?-q}koKYx<20RZ)>FTHkhV*d$pHOutL>wncNiU0C}
z!tP)j(y^0;3o+zKUio)n6EFQ5uUjhQYcF!<UbJlXvrI+b_)5z=(~L%5agmSRa72m1
z3m2O^KDfL*+m*Y*w}6rgQOzjuGX+F|ql(eX1IB5MSK-@&7FB!iKQGg6-DYfR@4TMf
z*<Ws#0XDgKOmgg26^&H*^t$ar7G*^a!q~_D#%8ttn(=08Tw~vs&8dNEAbffyJiKX>
za7S4?_Q&nG`rC^3EM;uJesD57{!f<=^!yEW^WR;!R*;r;fIXId@%k)3HZhX5?!Ed{
z`aAe1uVE?1^A7t9&oldv`(uWkboslZtKmbcB_!++vX<>H=ZmqPEfM0|4_;F%{pf4F
z-Od8>?7u2P_MwZCWvfIc;kT5FQz-He2SVIjf_QZ#-f)Sx!IGJHYimv0Oe9$Z_uS(g
z$+Xejb0!w)v|4t8=*qq>0q#Ntbi|eMQOov8!aHp|>WGJgBEC5bThWq25_~jR>dJK_
z-(7^=&!O(?+(S37^2eVQHP17Waa8vQb0$ofRD7?CvjQOP4iot#FI4oHqyOPxvk%2~
zZxC{vlgDv}zm%TaK|~mcQzolDk2~0x+Yc&`*HY#zn?2iZ30IY6{-_R<`0hczg|sxZ
zHDpWlR*y!4lu>(C!M<O&Du%pFni1wiYKD27jYy-VM9}!cQOWL0Ue>vjWB6;6ppiFJ
z<~<n*u#6LSs=_LGivsq}vx)ja98ui(lHv-}O4DHIa+Wx6^o0<3Qu)+6Y)<JoECH?^
z!hn#Znox+&x)j9qBf74b$dw0EJ9Mx<17$}_PxJz(Fl^dDNjPl4!u6z`8eT7<Th6Pw
z#*2}i1DSc%Y(bzRpl`kR7<e}jGcINx%RM<F(!h(zKcdoWd*Md*qOgi>vDj0P0y73M
z$Ff<~xsAQo0hCo0NYVCF+#-A7?+VD5tBNAL*?(o}O)O*5!aPp>YABwGBamgvmhWeQ
zCOr1_oAtoM6Fl6bkww`5k`SB2Cdp=Nw~LxKbMh-&>gv24)@eE2tmv^)o1>;6A7xxL
z28jGSfeVVMsdLVupC3)At`al7DnR)*@D4oQ#;`{mQxkh9t&_NszC_!8P4>3x$RG#}
z*%jz<5YS9lDN<F1dYl7|G`zyXqGUK;_)W5i3!&VQ6kRk~!2J&as#QZnufaT3$SwXL
ztWC;xGaNGDdW;OCff8#q^?9h3l!jrt*Gc8^=u4{09hVw{LMc@GNS7mlrbh&{wFSyz
zR{JWZ;$E^8zRNYU$rU(wIAXQN0_`HR@;Tq9OAV7m!N7=+?&&G&Jt}DQ5^9A1Rc|s|
z@37m8-g6{jhy$N>J+7Wt?#=E>WvQ%s&V8ygJ97oO&r$S!=a3>jY-jA&vxGJfX40VO
zd8}&QVQkACnIcIfT%4Rl?bk5hde>xZfIj@=VBy?-cKHJ~_fyNiOV97Kj57^p+}!6z
z3+uK?Th6(GJV6LyhO375#VZ+z|DqBdzhM3DklW3x80xEa-e%3YrC%;R(Nu!_IM!lp
zF1ja=kw3rR=FVF@V83~6Wg&)sw=S__r5Xkcq&7D!tB4pampAc1TaO)5D6XSJI=Ren
zllg+ZZ!OG2j_!_v{1VFHZtI_Dm7SFf3jfeI^5vD@*>h5s9lK@!nqminKI=GBvvs$<
zE2@*twanPwvZv_&E{E~P-NT~unOibj`#8g#M=_vQCppw=39};G$NrO_r3L>UBDY^X
zT!!5Wdx8H$aI4FK$Hu~?PW1iBJyrGUOU!1!Rp)JC|Gv!U*ZTM<zaP}G;xdLHpt=vS
zKE6mFf!R8he~Suzy4EvjszQ2x7BeQtAQ0jfT1uckcQdKtjCSjW*X?s@wN*0^z@CfP
z2U4$xZbZ~(>#8UBZLPnC*3*vMf6>om^NSC(+}%;I$C;QL22cnyu6yYJuH*Q%LnCY(
zb0)+0>XpoTuX|dqlZ~Adsh_=k$sV|gHNfY;lzE^_;ySRg+Da9;K6uSu<k<y5Rbmh@
z;+vT(7U#wbe^lQ|{Dr9c?ul&g)PFw9xd+~8Juezgmz$q9rDHHKkeO&|-_laYZQ;<l
zB>d;WJ^x=Z9{H1rDn2p1@VAu9yFXbaDw(2&0U>TK!P?tT>f|cU#C|k;Y%iT24KuqV
zkvZ`OY7Xn6(v^;MR}XD`n>WRhfuN8jd+4=R__z3wKbo?2F^PH!X_)IeE1i-0$|4en
zbl%=ijQLDmIrglFNEN>+)cG$k#jv!)KTOzF{PMHMZ2byXVc7=D*IbvdLE!0nJmxR+
z%L_NmRBKg62;0}OZq^T!h5yj1yb;#3FX#3fI4R8eVit#Vj@ilp`NY#ozaklK-R~5(
z4TRCKP3Th)<cF>&k(ugR>_+FJH`W`4C75X(Tkcb;*O_%<U?zU&nvb60E=j_8L`>wG
z{HiikeI9R#3N|Uyh>^9IN3CKmHh4rU=Jo9N{Lp;Tc}lSBwam|g0WB@Vs%w&c7{`%<
z4xOJM337Q{!5}DOTErugS(jgA)dmGhJM0(+%NBHb${|TMG}#+sBl~dM>=3H@NsM+^
zH%&+cso5P!207kH8&u9}$j9%`f@4K8^A~`58@cw}hl8}Uz%%GEb$7J%ayrvXF3+&G
z6zn3I7cfRep?HGco#QUaCTzb)b0f>7t=PLRr4I(ajU9KqhNn>%I;s4eij0n2si`1<
z*X1(qlX9?7zr<xaI;jfu%8cpoxhN5i?O^D7wq4?#!q#?**fyL}siD=AIwN3#&MB)-
zzQE5j?iYl3c}L4-j!dpUEH7mof#;&Cz(5GX@Zxo+TtJ9dO~uAH!D%@(i%4n0S|IjB
zx2-lD_cQZetVDB!_B3Ol?ZktD$z(~&ZVO9xN}8MUo^q2gmZ-F$8!oU`2n5kLuy&Ki
zi!!K}@d$iuwjsJtyL3(qc`^ZhsLTz^AywU|T3y1a=~nu+A*$rm=-vFTiInl!jh-a>
zBIW~{jIh=?B*+*Yp^M9&LD5Mzlubtr_i(y&iN<MHrw%yw4YARucurRcY!tSMAU~3L
zZFgCy<WdM6i^i%A3NYU6NOd5I9m6&*-3{lHbGcKJpOK>HI50Svtkd;qeg+-tF*g3v
zs5{0albuLCJUt{fe2%<rYuDkqm@0cR4~%v2#0_mDVWaboskXg%h5BARFxb%)-zEPH
zAHd1-Y7c9>sJ``CY*In@Wy}_Q{4yJPfWqt*Sf1-6J}Yl6*Yda9^2pKmRSV(HW*bFJ
zvE!u*w^1U0Ofh-PR-20Bfg(HuMz3@-TSH39p&nuVI;u)*vTG-v#UT7#6)o-j*jdQU
zj+}9x@VuRsBut66Tqm|I?ky<8czmqDi$S>JH7&;waLAF6Wl!EVek*(CkNx13<SDKz
z4;=m@T>Lxi$M7=lT6d$nqiOUg{PmL*Uw%E-#^b(>$E>dYw$Eja#{3Up?O|)|1+FH_
z@1UpkR28&Dclg`)^f(F1Uv%Nyh!B}qJl)ys2WgLw7Mb1tYh~B5q#Lq*zAE3&G~#m0
z7FRAXC)7cZf0i0D`}NZ9egF9`yn7~g6vsbtgV`@WBeSc%W&4*Q!GNsYa({ElgstHX
z-+EujzcZajk*g2wWk7(j)p?kFj-C@@w-Lk_t#_Op89z24=brme$`D>ejLMZqB^ZGx
zH2+aS@q_GjCsoJpas$z;oW`*qU*LGQ373~lXZ!OG;z2~3FKw9E;am3Gk<T;H6i<Sp
zT;iLl6CcBX7zP@)?e_0@y}umOs6t>ZcjA#uulhdqy1?>typ^{u=l+g)>%4<?;9J%$
zd|GDfzF&2A?6ItH=Sr+$ATDsflI~$-w3^S~A8Vi+83{RNtIgaMj(F5zPIa5<j^fV$
z9PaFW7_2D{s*p;<p%)i+`^U3t_QwciMSbJ-SJ8?nlB2jf>C95b6f^*Y7?mqL(GrBl
zbu#(S=$hUo#eQ^3Ci+2ru?({sqHz5x#JjD)7qaC8Gws)<lb}wLmPD@mlR;S<3dA-P
zM=uKOOxTow{$Gdjw!62~f$KT|ia8)Vhv9MfH^_1rPk#1I`>U(Nl6`L8N>@(R$OCRH
z5BqR*HRkd_@5(rfV=Xsjn62jjRZ|N4)jPMs7@YzeBs|aJ#hUQ%u)A{hEX%`Hfsy;X
zZ75|c=l-x`Yw#KQa=W#UA4?$mhSsmJ9kWU?sl!7*6S(aFOJJjqK-Xo{taN#{6qyE#
zs%&9?hg3TUOV0R^ODJAsc+SQSvJT?rsKNfWx<O2$&gr~F4hFWFViMvo*A7SrQtj1v
z4G1OAaxeFCTtpy)%F7rdU_bea%=ES78B_c;zZplY2iG&4j<OQC6<iW?Yv7stVtK@5
zMdY3+B$<b!w%7M+#M`-d=uNVgcXd#G+nj}I>9d?gp8@6tb(3;n8aF*7x2D_47pO^{
zo=spgo&uc3BY9Fwn6;^ukj>^rVM62p0GRCEA3cl3SUajVA1<>9%;`o!#q;6WPTkqH
zqotLv^~)l(gRh>?3XhAusyP(G1(<m{IX-S)ZVMZBUG#5UB>dEd_er{Pc%xm`HxOrZ
z7-G)`@jj*SmPgC13MrXt?GePM1JZ^7XXC_lW$%p?9wr&K2I>h0uqdER=dk6JXCDX}
z0M7<-)IlAl{4vb|EgBFMQk(Y$jvOm<+?ja?i=2QZDqD!PC-=w(2w$B{Cn&)HSc66o
zPF_%6(W6w(w5sZ31ec2V_=)090o%I?Vds-hI#)&m!hlR;CkHW6l8i)&bR?**XJrEg
z*8q@YUO3z(K%%99)516Q5v1ttuIwNQ3Lp2%9W+Orys{2em}JB&0!A4>?d<V};5nhK
z5mO7zC``tuqmB_VQ85t_yF+9P!6L+-mTxj9{1}weGmfW-RBTCqt4*FAOlGyiebl-_
z7@1{qk^5kHy{a7@CqK)5(w|Z(ZCyx-Nz83*AKLOg>V%qS0W>Rup^$mAr<2tZTHb)1
zAHrMUhcdk++n_7=?hqxjt+bjHJ&DKZljUIxKD2_m$pO$q5+TywoCB9?#`s+#u7!Y*
z#f6Ly*3E^CkNJ&VZHpb4<gI;n0L#rXrfL_-1KA>9)nTi8B%-ez1ihN=g*H9w&=PDj
zu}u`v9qmN&WUyu2YlZdb4^5Nj$IxX^Ex4TQb-CMFAp>Pq&H=!aLZh%q>pUFCYJ4nF
zW8iA!O$r3g3S~qMJihHbvU*Hoi54*wvvsmrYLjPO5l=tSVLTCqA>ZtJMjs;KMRzbD
z*%kpr>&bvJl0a(pa#BJ9r^`mPe5Zj>`<1j`ngbGv%2pJwpqj0mF}g3$M&;~th)7&~
z;~4HPQJ*qs^1eMmzkTpdp@SuJB-Kxo*TaDXEa_xvY0^}hS5xmRUH3~(Y7Pn$)MB9L
z%;Bxe!KYx+8v+`%$d=|Q1`$?b5ko6>d;MVILPDtP0Ni7U?oSxPHYwevO6Hq*0uvyR
zmusG%lVf{0(%C-zj6%JzD|6BW&p2|rq>zC?zp{iDLmU)&Q@0kiq;;qz42O{89Y@7P
zq(|Tk9j50*GeU?OfkS%0=4p_|AZQ2>TTh{A=rQgCw3G}Aa6<4rXxea`pe{e+^x$@?
zJ$iA1Cz|gmRGX5IS+G?e49$eC@OJ`sN%E$9Iwv=XT9H=#Jv3?oOip856hw23ymc}{
zS~w=^*22n8Rm>_B0!&6Aa!OR-aQq^vJGuMDqx-HfOKj4>CR&8KT~qBA2{n!tUFebz
zO{b5mbsT399Mt(q<kKNGARY%1DvC%FQ5sAta+%;a98jo^B8kcSDcWAonFR}(Gl>N7
z5(OhsaqVUCrEp|*_)vzUk(Y7{WiZT1Is}H+9;!x@z1-Dh;1U_iEb}OXYNdhtsP&XW
zI3NnT1uFwiu3AJnH$g*qQ_vG|O063(Tn;zz<w|L~{lGGgqqov+B2lUpACoV|AA5qC
z@Fe#QQSL$RPI`GoGYqsWE;Y<X1xmTD(WGNCDkxc;La6a}y^$jHX86txQw$EN4<+oL
zhi*QN$HxH2{6rT<GcAho#e@=7<!uUALQoOcB3i*h??QB)c6ovtIgQQ}59nOxa{Ed)
z#e7|EU;a5YfpPmtHpx_Ak=s?vX6xi^6NEf`$m4%rHWOc@c<6kN+PXN_X0)c!-;j{m
zwY=@H-jq^I70f-?T==tl%sz2Wq7x1>cQ|_kuNb$3g<oR`TSy?yY%aZP#U>u3X)Vqb
z33<@<ooqa-o@rypg!mFGFXt9sUU>h{&&ljJ@AC?#x4Ht0x%&<`KEEHj1%;V0TE4UG
zt#_#f`*$<e)-iH^e@@hQ8NBGLlB=o&e#5|`Ce`!zUdL>?Hk?iVK&)q1f5%g;&t`Ky
zD=P6w4oR<)^CGH!WO~VJZ~4~T|7my1Yh@s@?Xjpf3<QvL5=b?D^3vD_0vzC7_5Spo
zRq^p_F?LQsN^BpvW5IgAgxzr^<-GRMfb}+FcF*@(cI=B;Se<;j%}m@r3{P;%8>&V2
zriHA%2CYXA1f_fCMc$6wLf#%5t=H{uyP~SD?OA88LbzYMfG7JZDm`z6V|~A};yTaD
z%J6;)p8bdOUKF-yy&%9TRKnM_UEbZHuiS=KgYM*rq~03U@8uo{UKo3RxyZC$!<Qd}
z2GAFMg*N(SDk#M@$%={(!qN^w$GsHcxHi|m)~8a}x=6E-L*!uapxjCInAQHs2W$L3
zg;+}-x23p{bJJhZH9t6#*@vFP!J;=*^PSMbhGmD%Qn2Fq>lhyvC)<Nr3geYuEN%KE
z^1t&Zc$w?%v8xY1J5sHT9pr(zzBg5*)gRwyVc$`UPtWPrOtE+G+w7-rB7Jt{`Dp2X
z@{s=}dVUJ9a3U*(Y%Z5@WslLON<n2j6bR7?v!NyTR=9Ypcd(C7XcY8nGX)DLfU{2(
zS^FcG9#x+@#s;I<go|c{NA-zf2lXglNr@eCTo+-wROg2d4LVj@+n0PINL7Kth$z5T
z5n9Lz+0r{IAD)92Z}MoK$k3CN=Q1AePR^EjYb_hPP0X(F-H5vw-i6${y-Q5W%$N4A
zy7f0qTI;9q0lqvm$6Hp%+zap=DQ8Oe3f7OjVyXv5{76rd{eB3NVn@zXL_Wpf&YT|k
z3o%)UX}#RE2>_jE_28C{3vlsDj&L}Bq4uBYO?5?D*`yioRKkHDQ#&!D@EY(^^)m$u
zjx1p^7F2-w96Q9P`B~<+V&uS!%i7TQ;#nDqBeXxv=W0CtLH%)swk?!8zUH4KrU9gm
zxriFmgy0!1?aDDI(NhWmxz7yvgofKsA?7TcXjC8ABsMW-OUGU6haxp;(8kGV9=(*b
z?_tfMrkKG8Ff6eNLOIm&NC6s-U+8e5Ats;hSe4VaQC_i9p?$b{DKO6}+gF5)5iufq
zp>oR^um_BmiAW;_?s_d*@iE9i;hAar9`r(7a+es@q6C#YkSZOM-qGPDP|MK5AQ%E=
z5DCTmElAxhzFj<CakE(EJX>sL%=Sy19>0TaDqPGMo*>0G5Tb*{WU8<^t~4J&lLvyu
zbQ^F*j}7%8)OeAj4KL=<<DLT{0h)_IlO-+qgq&?}n(Iew=kr#Wo9<AvsFj0(Y}~{L
zGs-I`p!RSQz^7#Dd&H%N>~^XwP{fd4UAo>8L<ox!fsItBYF!DQQg9o3IWxK*^gtEt
z>aI%-VcxX&cSmr<pd?K(rKu*lRnEh~C}^oRoQ@wT)=NFp8WXWtnd`|M!uTvimRcZN
z2t?_Z$?}{-(Nz=%&u-vTr02l#Q2EiuZ1t0LJyWzsH(68ZmE(m?tx<(+n&ooQ$81f&
zB3>B>d9W11cMU?n;){j)$uol@yoH4=jZXYE=0)rz4_0@Pjo7uW6KVBQ33tl0Lr`HH
zrOx1^v_Crl%EiU~C>d3sKa6^X$oImd>A8L`KD`S<VQL53;ooo;uE_G@FSGq#!S>2l
z$PUfgc!w?C_B96T<%Q0&!;_hPey^2BMwtZq!bWEilk9LQ%->7)*gG2T1SPlQs+8-a
z?q+}U0V`(osScoUFQcaXiH>W#AZM6e?KO@KRCf><$Cb9gS5+Kg;iZ1N+<r1q5v3;u
zKBm?+NVl424g7}cmO%8j?<c&?JeuVzzxvPA`Q_E)Y@qyad)QcVovk=X&E9r}kHgLQ
zJ{?SaeSl@*{K<B<j6o7-rJ~gX{y+dR*gd}uTda){9a2hZrISf$74LpMX2>mj80<nw
zX6w>_%5%H&hgK){e`eGk{y>pkdfwGMe|vk2?9=accI3~uQ|~rHT)n_U_2^}M^5)#a
z)*h3l%zpPiTUdOvx8v`|E+%h0JWIRq@|&#PvsP8MD~`lnPAUz&M_6^IF!0}B_{)#~
zp&royiDJVI@-$|kI_tXcR`38&Rq(=TXvr;bx<D$fgm`&|0WYLzCVq)$>ib_JS?uUz
z?BiN*#rGfXi?xJOP&cO?g28F?Y43GEuo7Q&d*g|7RW5cpyH1VQ=7yWeo0pm}TeG;$
z@Eg}ht;DRsHtt~j?T6=L<+S33manf&(zY*J4i6oNNua{MleaA=zF{paZQi%~v#3Lf
zz8m=CV{f$mlZW0<l^<J}nRs0g+wj@8vq#_Hmw)tYb4Mbb)xT|Le7pk_D4-5Z@^bN&
znfH(`AG~JKj=hJ?%CAQ)98zjd48fY|m&?P<%<O+hss=V>b&F4zKCNvl13b<YFcU{&
zk9eyVl&LlskzG3C=Gj_i>r9^!k+DP2>9x5Q2gBISvGe?kEYtZf85_YL;<Y(HJpT@c
zgtnO%?D|zD733#r_sC=6=TcY^{@G-i@z5JTbhEA4k<spQ5B-)G+MSbMWeEjKo3y#N
zA)v)RsGR4bGqx4;o?}XK_-U&d+n_7EDd{sS{|@tM{pHTQpJW+?lWe-rIN~Gnm+4E^
zc@ffnAN-SXUM3OQxUQdVZC)dKieTmm)1jV~IpwGhAZpj6X-YH(MXIlmM+^eLwuU>M
zw2Q#wB#v>RyCpi$@FEtG%_Ex<2FU~eyi*5KQNrE0Rm*w`>v<(3SVyyHSXw12irXE$
zSA35_m+m#Fq0MS(XR-;giSMzF=WM)5amgv*eoU9l5<nHFxRvrWn4xy~(?b8@172@h
z74fqF;&`4VL{7{J+X<4#VqoT-Eg<33sC!@AA3-NM*lS9#JiT4AQ^SG+oGvY0Y%X4P
z88a86r-eKPu3mfz5>9Z2Vbo++cw5a8*-cXzCm2*SdoUQ5r~)#N$V4m^$KXlOTFH~i
znoI$wE-?_UYV=Heeu@XbHpy5=7i4kqM!r?*TcLwDZ`qNpp-;@`>SX=QA$eygQXm$y
zHaaQfVk|@{(PZJ;=}p8)1l`4aZpy`2*y~~(7kac1-BDjn=x%pMByUwFP|tw6&CA>N
z#RS@7Mx-mRl^x=W7QG=T0jsAez&09H8HYkxrt3iPoZ~*CDh%`!jD_Iv^9yySN=VU(
z7+zI95Nk1O&Y5-LyGVexgO^n#rT9%S72T=EYzlq?PG)$XK&m<ky2(B6!0$-PZCNd#
zWg<4fZ8(!Fi>OKZFroofI2C0_zxwe$oT8e(H)@g&{s8S#Ku4Szb9^`*m4K&Yr5S;8
zoY@Ov27_1WFo#jSqsC4dWW6@C^H!SlLHVlKc%f>?YjZ&zN~(gM-iX+Vptt1L2u?$3
z9N!JtCQBV=$cADCVs1Z94PKw4Cdv*4K0aaxrY~AnC#2c-LZrqtrC(vTb`@w{?VY`g
zM%BB)Mo;_}+#W5~X85*7N3nw-Y3Y;sNAx91&&bOwg-($1W3=L{vSYS*X^8n+KIj;w
zT<WUs_c1d4L7xj#1?zZQqs)(tX3ih<EWHc^4^j(03Tpf&`;nN!g_nD?e*v#!XVvw`
zv*wl`3YPVLq3gmyRPxo!5_SI~LT{d|3az&Gp3{mF#;Crl_v<NhDZ!JzdQnj3M3n`t
z1^IUeN{drEUB2&A<)xRM%-oUZyu7OvSAVP*POP6_#5a1i44X-4K5}96>r`DaS$@v@
zEGyqyR)mD9yT4~n=f4zKqgfz!cMw}JF2}%gP%q2nOCkd(RK2gTs<QgM&K>?Hb~0?M
zdtV(ew)R>6Sxn7Yidt!Hd_5aEJk0?5(-%7{84(Wz4@UX<(vD~6mz{YEZT7)@nRIUX
ztjtXuy2t$UDOTmJHOWS<^39m;CtEhBY06`NA8c71KJrmS{vtA9w%TJaapo1;*Sb7k
z{2pk^A(>KlAm1+Fi4&skeOhu0oC>ri<-9@$K|mZ2QfJRa#a>MX+~3>d6($QbeZiAh
zYROXIzCdZ%H2(bmx}vcAKYK+{$nZYAK55IJKHK6Ew=Ywv4}ws$O^flc?Y;k<N|P&V
zUtYZ1+`F!a&Eu)?J!Y$S@583}KYxdw<0~Wfx*JzO#yGs?1Ct?q;Oq$-|7Og`?u=)M
z9{XwZbSN|T;g@j+%HKl=CWp>0?IWKw`_a#!J^eq>E6n}k|C|rqE3@|E@{Kle^ms@d
z9=zCF_4$^})+)T<LCYKz8m%Xkvo55Ue!P`xpL8}5B$*JMFzXVOvjN{YhN9LWGn9M-
z?yLB%izuM=+DD@+UV^Stx+C7(5p-gQ_p&|uY})Z(j9UJI*W^M;pM*@VA+DV^NMd`u
z<slqNWRIUidw5UYkv$tB{IgD_$6I+Q%a%MXmUBsqnXt$FT*t1=mUy$yR<|`EYXX~Z
zdn@01@IXFNU6gfC{7Q;Bw6|J1T24}~`VNoe=#bHH5q8Xewo!bQr5n$zV?;iR$o@q<
z?|+|)=OTIx-`p(ude7wBHpeB5r{Y={&rqa1STxCCN|c8D4i^<ip^fN4Au8IY$~atA
z?kwmt&58ih*fhC!y+U;fW}$-Z4Rwh&37q!m14XCd?T~}vvL5xF%oB3}j(!C%A{W_}
zQ1Zj&c+ET<p`=}@op~~7xfRo94i`CzklPCJwwLk0mK6+^zB(acFy5U)1dIb*bewvb
zDLu4K4gH7n!(G5w{-)^g6Xtz%kt+^vA;*o65_Pzx24GbYEv=nkkkGiEZwD4NK5e60
zr@&pooADnp;}C`UqUy$GGvAoayVq&5pyh-^4{hb>o^}t)yg{{q9Az0qz=@Ndd#X`u
z{00F91(YG3s_IP?9lr~x6WsPwX##ghUts?~ac=`%S#jO@?sM*u`m|a!ryDg0+|VT<
z+A{t?V2C>ohLR9i5aL`s*zWjiZZi%cwrA3|F(DZnm(&8wge0<qU)nQXlWRi!dWcu1
z?Re%fj@RUXi5JP^F`X=u@$<{PCwn;_GO@Gzc^roj$9cbhopZ0GZb|n7p7pkL&#BtA
zYuB#5tLoI(sgursrOK-VF_<t_Tmk8utJ~KgH@{QBA&{qAdFd(mExeUvTM(=b8d>Yv
z%AHf%<K!p#a>{IpBi%d(QUr9ledrzNwP-*{v95q7O6Kh!g3{wlly!NrFT(-;X^Fi$
zN@EhKa_(xDXe@%0$QEo7AI9#+uR=Gu1|RvbydZ+oMw{HiFgqc*J1}kthh{&tD}3)*
z((szW(veU#X#2Q8vlThS^QWtcKC~!;F8}{PtxKsbLYu4Sr^ZeY>k=mO-4dc0j$aTV
zp0hn3yDrfcaP+oTbx`3>zt+jF3#f4_F1$++t3CD-3G<mpv7ywdsm=Hh6_sBcveEhb
zu?3!Se!YN>lI$_bj8wGV5V;_Qpv;)PE+#D(ISa*uDUP!^>5^bI&8)swa5uMNjCk2`
z>M;%RDbOT@Pzl>NMEZ@WH`3Hbbn9{5l<A!euk7Nz@_R$1I7vI#+OG)))m(Erc4aCa
z0~3RF2{-0V|F;7fll-u$w!{@SJ6z2zcgZ$#KreYi@=As<E7$UnjV}^Zq;!SMvD&Ib
z1}b<Pp11OS5C8ZKUqMKDyOsu_eQ~nOzI$#qa7<qTi5=;he6yP)Al>8Ls5>v`BcJ#l
z$Uhc|Cl?vEri*rQHPr?#aodml7xQ-68Gg6TE)@%VXjujRRW`^bVZXy|M=39j<vs><
zFCqMW*WIVXZA|BBH&n&|G*+oho_-*Rs5*<Z(H?sbqXwXOCUM%ynaHkAm_sNp{{X6$
zM~T=g_c_~nvxVww8&~H|Eag|8Vyw^)v_-@g<o9R`a%c>B`J=7NpCsT81{hByi7JyF
zyq2Q#z{Qrm0#g)U-aQ_|uLK)(NcInjOOjXc0{oXcbxCYC2S0ahl9YBNd}QdYEa8R*
z)@^HT_2{{`x#KtfQ6mf~Z)t+vzxAiZpZEhama^KKe(X2Y>H-g5Y*ud)W`J~EVbj8{
z)p~f4lW&}`623oe)P$aUmshR$^{nEcQ&hbm60+>M7+0{r_To5p{N(r8b@#a)NkITB
z>O4Y9>QG!A#tKp1Pr%rpeYvyC4-SNf9(gD}fbwZpTl)epD!Avn#J!Fp9oztip${{l
zS3pp}?6+Owev%6M3#>jo{lAl}o#*VsH(7i4cYGR_Uu<WOxc<y)6AzeoJ6X(Y@NJFB
z6Jt~G4`*Z??{`VC_DAn_F>m3H*Ydg6m0jM^DohQqXY28Ql8`L$`ZusTyJV-YwnhU+
zlFKNa|Kq>a!XsCImQ@BEzbL@wQJxS<4=6E_MyHc4`YDOVk8^C}=jK1_ZT|7XoC4x*
z-4&6tcFt^Ji)#gb<*uYT{r&7C_JzSrq7-Y#x*e+1?lD=g`mArN(W#QGp)C$mhkqGv
zondR62VrP<9k=S|R(^>m;+N8Nij%g^a1SMuc2hEDbD<M|i~C;WbGB6YZPN^prb8NH
zpJF20X2HUbyLo$m=41TfKi}@&(By6N=nH95uJBGqgr^7R=q@Jd(36Y|HePKVMfOt4
ztYLE-btsVRhY2ngDG6Kz+=5OQK#Qk?3sqjc`v2q0vKkRwWd)fT14!nSC(J~A4hyAX
zw>7vbcy1jP{KUS7xvnk(m`aS;<EaYOJdNk564Ib6b8!n~B@npHAaZfuV??-zNoGA_
zbkW0mk&}8{AjBDE`D0T!S{2WX#=7iE*Mg51uabK=*J2W(&Q%EQ8qvosO4bLRNa$zu
z12k?DKA&bV#uBPioRDbT5ag_K6PGxrE6Vy{)+%E@Xgl6z=pb@|SxqEIFK`&_jg2;a
zF#vuoZX|7q97cd3FZtP^Z#wxPkii?!I%D3}dvwd3!a)bNCo}`y;6P!d0I@|PaSmqu
z&tyz)sJU?xqXYT0Aq)^`Q;KQ?)ryFCQE#c5t6jxau303jqn;Y{Lj5TF!M=EO@)4lU
zvMP$_7T|!wbGsYyZ%b^KS01Z;;xLi6_zejqRX6#0etiQG+1!%wWs5pW3IAFG(oceo
zQ-LPM+tn2DcK=|=yl^40>7$?=KOajJjxFIZDcpcbW5+1iQoz1IQnpA?F2F?*CKwvH
zo8;$Jt8uT6b62#OU~s+))wPCk-FL%^72W(;2iyC;%K3EKsWm8<;E_IhLJJDtp;D|4
zxXKYF#pz?O)Z+?Kh!WR&NY{IN`a~Z*YFra>#Kc?$B!JC%opg1gt7|uBE<m9T4JaFc
zZb)^fC!q1+lHD<0g&{_W7r%^m|01>+BVlpz(p^E|)D$mvXzI5ubd>6GBy-WD%UW>0
z_EA{o)&}%)Z#thXG0H~pT?T=78@ry(9HM9q`WT$YVWK)kz!O<nz1#GcNXU99>zPpj
zfpkJWNQE@H6WXb>I3N4%I8O2dB+AyHWc_|FpQhqG_2E_GuQH4UChbZoX502+<?V~z
zP*=N_^DNkP?W^hUG<I}CyOVnz#OZejD!GS!Zr@J^=ZjA=dH<QTp4uQ)I=H+sP&`O4
zgDk#_%W<%2k+j+Rad~JLww;ya3O<rs(`^qS9ZfSZp+;9XXa5;wlXqR#p?i2@zE7ut
zlV2fk@JdjLEtZ$`VOB)qyM0yjGR`Jpo3EBM80#cK<Hw!9@8kH<{pKYMTj6^>KbP(!
znfWt0=;s5jUcTGM=BH<T%%PI+3E`)IHM3v-u}M38_dr@z9190e&ghwrJXe|B@!iDQ
zN7x;xWWBJ`lgt-#P8|5ghs=ItVyxN|ad8s^h@=->|0a0-BQKbzuVKUfpD`$<QjQ&9
zN$SrSfi9iLekE;8{?Zw|aB~<^m!@{hVJk;Nn$4Flt~BMAl7!V(ir*92s$@z(@XPLj
z%)S3Y<9Qv0-^5}Bc7b+&T`sG<_!#bPr<tl*VdF+O(&i2_RZS*90xRFyy3J~<Q$Tj)
z_t{qRjD>}=Hhz46nQgNnzIM9vUBNq=2_-v-V0z^B0j!un82*`bI`T}V4Ml^4zmdBm
zpu5^?=+AB&C;fl&BA(=URz5`DZh339)i4Y!hM}Dk4tx)A^sP7{W6ot1hG~l7!Jkik
zX0E)SbF3EMpUt$sK#h3c&lRkYZ<}uqukgLnV!E*3zGNYcdb`QPUn1LyUk;hxZ4Hvl
z@mtlpJYS;dEq`Gl4f2R&P?xR15qKJ}ZiKh4jefF=-rV7_MyKi2Qz~1t+M33IiI=NI
zBxpsXg4pcxW>S3ZbmhFNTvb7_Xmp%g+(|Y@i^l7YPOAuBH>XP{U{LOBGMdX{yN@Y~
z*@qa=<o_x<slypXeKgd*EpBmIJI_Y#!+P-Lqgi>rdC}kelC)Vey&T@^XY7F5^)GBM
z5|<{<vpr(Zw;FDzo$w;{N`Ii_6BEgkRjY{qR9Mjr@<VH|VU2r3XOwKi5R$CA8g=OE
zx4JeVUq!oB=c-FzK-`6$M|ZWW{(~BcSf+|8EIcVU_om6*(MTT0rjLHY)&tR;N@0-P
z;!%U^ILJ^ss$NnZ$OHg`)I%Ve=yvV*x}6QMQ)V^Z7A`dhFyx3@7Bieu2U5Fd_e<Hd
zMnY=gBJR3rT)C&OP0fx+qa;#56B;1sa~y>0vME%g1WQ+2!&Z;sKyFuIc-6V3i>~-8
zz#>{GfQpsmw$(6mxV;T}b8&4-d3uUj8>Jc}>2hv2FL<^D2pt4^rIwf8yQCq*Il<5W
zbmt)=mQz(d36cFh!!|J9vPDOLQ8OCpV+htKFwi9lJ_ZtwI-*E=Oyo;S<WB5mouwnF
z3RyX&@Q#Zzs@~%eD6gry85@AJS%;ia)GF9*K=qtZkyqJw6n6@xGAVgH|IvM!-BZa&
zDRBzy0#o5U@j6~T@l+^72eIYd5h_cH#b?%JU;YT4_2*bzA{OJL{_SO{@Ify_4-P2B
z2%ZY1VzxEJ9L-i$vZjocj<*Ey>Zss2I`tt2UK}&rl3U%GNU0%d1Q0=5+891Y;8fT+
zY(wmjQ&!wYVQnF^jY9gzDdVmtuUYZniU?m;_d2w?NgaZqi}V`pAWvUF^w1%cLmbwD
zWbhT{xNf|NLl2x^`jJzlSy=AKQju?Qy*!2mb)gxj!~~W>1u5?_N3l*|rHpv}qD&y#
zc-*Yx3NW)wP~dVpNM@k4QzWd=8(+saMpszg|Eb_4Wv``<X)mBRcp8aUo=&p5(c14V
ze4V_njG5ylPf>=nRF6V~RJ#PN+&NZBAI=Rz^_dk(7U<bleX)VW;S{7Nt2ZglzQ_@I
zN4K*a*Ljva{95$*QE&EjpI`CRwvhSjI#Xi9VaOivp{H2`8EbsdPMl}^w)-}*!(WjD
z*iH>67C3m-j-5B)?FJdu(HZ}65>jV*2xsXxlDzaYoc|P4`JK#ox0QLr(Q9fW!e$jN
zp0}Z|EUfx_y24fz{^*XXY8B56FuN<Y^#X(pqLFY;4iMyYp?Jns9A5Wh^EP&pT)&T1
z)To1%M#8X_2=l*6<MaXZO`=v`xrbR0lb%2-M;QaMNjS5MPA1C^gkbkGl|1?mghtC+
z<Yg%pq<?6eH6OSjv9tc)#LB1l?JgHzk`@!HM2)K`d4F0l*z!sVE{^`7h#%pwH!>@_
z+|F9W$oE{C+gHAS#Qg73bZ@u-x-%wc=kjSv)!Q0lyS{t}yZ1kV5I1Lqm!{e;n%0p_
zW-nnd=0U{LtO^qNe{}Zec|GZgMmeQiNoPGlQKNE2sp=y{1QKx%ACX<c%cO_abVCyK
z1}_qpJ+;SuF31DuQK@0;5CM*1Yq2!NSxp1j|M-K~SoqCL%syIf3tv9_UCZ%ErZ{mI
zcNP<=FYr(`+2}iT;OTB_7Ph~yT5VO<bXHSq9xBE!<n3EYAa7<%cNX4{{<yV%@Ro#q
z_vG|Fdl2g#E_RynZw-rA2Xn`gp)A=;VfcU-b@&H9Cz`$AC(e;Vav+(XZ*41V!ezVN
zY-7ZBJ)GL!KcriH0F_GV$LAUA>fP3n{Wj`AM9I*4>E(I!e2T$5)m$FgMfV<n0A?*G
zD&?{&3}jEqy;ax>oc(p&i{0_}xVL!QMC{hVNvZ+?IZdVO>_5rv`=r183g#15)I6U@
z3E*vwDqj4^Q9u3pirlFo_VeG{r9z~VRB$BI$m)76i>u%RKj7B89anFDFFQ@oWjDh!
z>O=_+GWa*|<?IQqawnUZ7Esnh+F1AffXnRr+Y>v=qxPC&SCfk3%>I!6HQ&}Iy@iUW
zJ3e58KT^+Bmcl*hypBrU09qr<wSlWZzX8p9RJU@jM_0zRFdNaz?Y-*uuP55lclxR!
z<lD(3rIyUuK&``<B%D-*J>>^&hmk07f4+c>p^A&tMPx}O5XRx>S3^Rhfzv@A7I8HB
zWu6PbaMo<Pa`(7Sk*QQGds-v#R0e*46XV&VswI)x0E=|OD@icJNEu<5tL|QPAj_Hf
z^cCWit2@R2g1mL&%OuIu0loJDAyT;x<=WDx&dM!FpEaTqDt_aGUSkV3<!UCS<OjqA
zEoi51Rxym|tu8@<PQQkmm0Q39px52$@<+%L9r9d0SO(r-GiC>9uFi;wEGeK;eW0Ru
zR9|5?xjurW#+7AS({!nl8y{zna1HvOvYAJ4b6kYE@abAc@NPougN`7Il-F%@a3M*Y
zIQ9=b-!=oJbalP0ClfZK+z8)^`B)VgR8pPXcPGaeCinv4weYVX4&fyBE$SoH$%<a?
zz94j{9P=Muo(X;>`YPoS?~u4QZ#Py5iQ>Bh&cQOHUZwm5A-Qypde?8#Jfl}M{LJ82
z4My4IKCeedsX5+QiL0Ib-d)4QIK?-Gf6SheQ-bQR2QN2_PR+G83DdZY1qBIQygvVn
zW-z-@rp>PV`8ZT@eJ7&yjI_MrMt(lo!5aJi1D-I8PMxra_#GErFCan(f{zg*=Dvsw
zbx_q3RvxF^6dl$cPvB>spZYO_vy<}nhU^#_%i1)=(NKdjiZ2{P2P_v+AYjX7FdK>W
zBrL!-qet0=qFoD8-?{;nV<zhqx#)MN1V2ab<Pq1P(;<nR9cD4KUr?t=1;W=6s@6&U
zndFP~Hb>41ESW8G5(wKY%Oj}qg2Y*QV;F9Hy9~xab|ieF(sB~cA@zO$LM1biHxsN<
z_5G5sCNqlLvMW<`d`^%jhFa@Fm->%adQT3YZ+Dmbf&y8nc(JqOp|Lduy25XC^>Lr`
z&GcT&`H;^4U_^Z$o$DRacb;XbKVTz%nAT(T$K90Qc2+YV*_DhC*iI7&!=*LP@<NyJ
zZtI(Ec5t0tLlyoOm5#A)$XtbeUe^qx+)GF8(Y;O$gD<Cl+4aRJK*bq6nYt%IB|?5U
zxFrUb!;Bw`!+(*?hu_|3iwr+PT&!bU;wM>~v%Rd?&1#YN(Y;|=?NQuy8hP}%ESA+_
zKz7R=7ixc-jOSkc^o2eUagk)3cl-@qc>;nAR<4}s?TzP-@?>RHefw(}l>A(3jv=J|
z{U!9^JPm6<FnL$gZv4==*$<|Yy!gSq;w=8#tGC<edu_T*C`{w84pfZuY2~l66inJY
zZ_3-7L&<<N<1{WJIN#8_t(?>}gQh`9c$K&!$aBvxNGxUz5WcD{eH1zERb0nQoW$6<
zuW)7+tO|`En@1^L{eTw{V$Dfm^&Cd3BYkgN;fn(dTi<$slXc=UELn;lZH(UoT`D;W
zY3G$8_Ew#2Or)Sl{Xi!9UVjf$QwN{DH*!Blp&ET-rmQ)=xO#*3CO`Ve+o}U0+<%9!
z)HKSA#D4dOnQXc%YSO}Yw>ev!jDfvVzVQ(6$a%W)$pIGT?yz?drF;q#+;?Rb+9h-M
z=Png?|CvnlFaAqE$J#Q}{d`gsrRV;x-F7yb^2K8*n}jbjyZyp|uz)1%+U3!=A=w`%
z<Oe`!{ecLbNISf0ueWyxp@9qdJrP~~Ul<VqY<uBpld37#YU@}FU$}$3tSB|5c`GuP
z=r~_VT-tt3N*Kax+LA~II%~H=ZUx#+?9vnZFy~)F2Y2|S<sPp{VRd40?i?Y2Ywr~W
zVV^*d>jyGBe8!CYHvD(<X!`w9Y9HW@KX0$c2)FIFx8y-_{29BNbJ`d13(OYs$Q_Xm
z?CIBqqv@UI_xMqEN|EcZ=N{*9u;^s*-BvsN(;Hc>bu-KGuMV+uE%Fx%>ij=n2zA6-
zPOri@UE|6{9328?%rK!xxxQ`IioKc%tW0mlbA*Tu)RB7L(vMXW7k(~wtf8mH@rvg7
zrSRuwv;q-AGB#YfJU9J<E`ltZted~e-{TsPdWu-OCuAeSOWE#Bp5hZaei26XbAd!s
z^5#MdqD=kU3WD3MaXVS<VCsPSh8e=zkhSjhlpSBzah!Jd^u9X1HBtG~D7Hj23Dx>j
zErS1)9C|yki4{{mI@T>RF0)Xv`idTE0;Q`ohc_2bWNQE$wegPM1a}4%*&H{_8sk@2
z_Fp8Uos`)7k8Db$P2~z$1kWLU0Cj`EwDR=29<82#Q#QPG*vyH1G<I)%fP-UZX+pS}
zX-cYlAd|b^vJxtZRaYw@aKlL)hDzcjq9}7kz4cYf-VlPY2op2R&GYLA$V^N;Uh1mm
zI}xYqoMYd`07aZFD^$DARgMqwVt<F!W^o1iR#Eb83{K6O=tJT-vpIUK#6oMV<FtX{
z?gtf?G@OQtGa2s8S;<%uWvfKgsWBAk17P76ZcV)>BPtGYn}v^Ts@S2)olP-82?cmZ
z>!esb*vKH#R%A}MXbGo&qGWdbI*<_?=KVvro~((oMiB<T4*2DctLI&ISWy{t8<EP0
z!(_<ug~k}(rBaqwL0sIbcWalgf*S~*x6R72%KxC>UpZ(WX(-Hm^g2}(E`q%^4!w37
zZ?IWB;5rg)ae-mfR;6<W-O*Pg*-{hrrxl~1%;;Nz6>xV!eV{5L(r}tu6*vKfwC*a(
zc#TcF0{R8FE_#d=x^dNQiSPu%msyo;H*_;cYd;-?E6Lx=-H=>jst9qlHE7sc&9?Ix
zeH%7xvWQc@)YLa(aqLFFnEuH&FLD8$Af7%%>JP#>5Pt#fy_H_AfAwOF_23yxdF1d#
z<e3{t3;%4*ZE`nHVr_Ljh6bs{1HKLzDsSXikm9WVa$8>Q-eFJg@Ix(+h5l`bOxgq7
z2JkO9-?k>A6hF5(6wb+CpC4!xY$jGnmJFOo1M9Ms!;kP}V%SPC*brVe#%3TE4>}Ob
zNXPS>@2jh=-?aP_pX>7_Q-(B5vR;L<P9g|L`YPSx8JdN18>=*TB|-IP`N##q-S+dA
zXxQ3(R4YXcX|la{`OM>19nhy%=Hkv`A$oxZO#Wq;IeX8819|u@*7<+~&vGJK`C$}^
zJgx6uYwh1W)5pCmUSp8KSM9c`|57B2V|!^ozCK}2kq+&2IZyaWxqHFgf5_J2*)Lp^
zrdRQZJ@L7!$Mh0*F&=%CCgXP2h0bP`&yLV7{>r;}_wkcw`Q+@I{Lt>O%O1b~?0gRO
z_%WtY7PdEXuNvT$CfSb_Imokk7nSdUMtlW=ir*)Q(2KUiOKt(f)@2>r9QzjKSH@S1
zOBKHH)eGHW6>y6`1K&9BkbL@lYc@ZZrm}*Twu|E@*s85Tsz$i!fQke3mnkh}@<x7r
zfro1Gh7oJt^w}fTpcuq$U%RHx+CFx4K5J<JIi!Nt`cvl2lt|3|LuXFJ_hJv+r)M58
zIBu~x%DpAr*vh?QQ@J(f*!$$?6QYG{$^N%49I)0i1e{L_;m@|E?aU2S3;FK@lmCKE
zwVupuhcvakWT`d@&p&nbk~yW<l}w)W0KKp$YsvZ(3yX@-DSC&O+|e-a4wSg6A@<2<
zB*62A3(O6il!{+9YxaBGSCrbBmf5%YxLR!Ok0!1@hTQ^T{Z$tcuEL35=PCATG6Z)$
zwfy;YSfDD~v9W;Hxrn<dW;Z&`{(5`RI&kV&f^zAT$@eZV^_AZu@#gQGPj&odW<-%T
z$Emc()uMi2UcCt5&k{BRU5?{ceg`-SBV0Uf13wcx{5)85l<}mc#mXy0d@5uun7&1f
zUm#GNVwInce44s)x`L0s9v4Tr7tMMx9D+y4bH{KLpR`t_LX#TRM==~|J(r#zs6)M^
zs3h%m9}+_#TKG|r>JrIA?!uS^h(P*oS%zsaaT$X_`}OkIq#NAAB2x~YfLY$5RCa2J
zIgX#3Y__W024hYpI0~$XCXWih5rs_1_5=!;7UDFRZ&w*QE#SE!VwT1mp1h)TDf%8%
z@rV5~iP596>KH-y;h>C6^79(nRr*T@%ea!E1&UygS0=8mkqgul{Q3e174^hTvXeS#
z#wadECLqvE`n4j(;OdeN2i_)@o0dt2IWZqU2`S9h5ZD6|^Km`h+<<RQ3RFq+fzbT{
zCNog5@;4Y%=F%*XeMVvPk-axx--(e%=laWVN`Gmifc0ek`f^*gc7S?<gxme_eGuYF
z1ozU8zTDHqqYPck)yX-{k4ac+tYtwHYf?+#XBdJ*E%CF$VQpr{DNl}Kkn~RYK^VH!
zQu-V!hj6d!ycz%}TO}kg2Vat9q6eG|;G?Q>faI}DIx((17q3p15WX?^Aq1uv#f|x1
zG_M!eU@mY?k~$H!#*Sa?D~O;a&rnkBi7o>kjY}POxJia68B*ZrYA5q+NC?;xkZc29
zb(EM!P#UBp!rt(fjxefw#L7a9<8>WEXiSGzxoW`b_%RO1F&!g5X{aqs!c{9RUS?L-
zdIQN0dFg<Dg+4e{4Tn{@DCN#cIkc4U8G*`i2T#=sPI=SUoI|C*l$9o>+2+?9*o@>F
zQ`PLIvfu}+IPZXcT=h!utKFB?;E6txpuAb)6?B<js1zd9JHqykWRV2P0EwZJALJ1i
zCr3{RD$amXfp^7A2mwO?rrLeWgHAbC8Rhf>S}|S~8$E2xWxzeS*Cxm}FA95Ygp$TB
z1cW4`&aH4dD~%@S(pm1A709L>w8=KxKFn%JtHdOYowi$w=>a4q?uS`3fIDZLTIPu2
zK_hrPnR#upG=4h*JJBq&l3=C@%#M@)Fi>V%*4NZUZ6Z9I0y%?_-YiiMLKRX>1H24j
zA_pljzEQ;Z3A0Wbq<ReLA&e%@Ca_A@tDN6$D}>fsm(K8L0=s3jBn@;XE-U<c!-1Mm
z0^qKAZ4fO8mu(Pm3aST*f}NstijmwXK}E6#-*G&bdzEZA@ip9o*le8ab4g%BTE8K7
zGh~-qSq-OAsZ#yWz{fheIXn7H(up2#U8QYKU4_&wU|g?|0iDqC0oiR2V5dI4SI9U&
z=j4hx3srkxVL(nOq%WY-dk3YO;=&bj0wfa|d&!gXd}WqLxUC^<9lS|s7^}+Yx?s2J
zYspD>JGRWFJZclD^gM|Xax=?%2!2RF&XbmSRo#}rd|EXE+nPUnv!c>&fUL<cU_ikn
zKLU6o!JGp0q|4)xe{E@EfX`S&(ve^ZnEH8z5JcK6w<4>7u_1(dNXBHd$cvOFiR)?S
z?cyS=$|Hsz<ywkB1!Oq&f+ocxE9u#!``PE<h}8q2C5|QogF33SSnDM*3ce(Vua_^)
z9wWc_E{9`Fn2cWw#e{L9%Ok@QrCa_aS=E3Ah2)-BVhb-W6^W2rLP=<qOB@|uI0HZ6
zHZkH;htCl_^iPPJ9$Ga_ya>aUC?S?mMtM#FAr97S5|!C5VBgx^xp#v$b7U-WCWGcG
zH9>{oYkPWPl(j>Q9+S!?W9-!=kHu!m8_(oH(dFYYsK;eFacw6J9-`-UsNzNxGFjO`
z<EB_DBL)+OX_)KnE4O4XvN6#K9N3x4xxsac9zu}$VIc7F`rI#3l6BEM=}xZ0^y6u+
zA)-S950=bpTrw+1sC`{aR9aZuU-2E1KJLo)N|&y%sa4~&%xgs@K2t>D=T(tvT2<%?
zxtI9~*=Js5twGd0L5FP&cPGO^L#Tvjf_P>Bo-a{yFLqCJl_OreJ;4^<MSgQapRRfs
z%vv<OrK0E<w{ky^>#x>v*a(>0+p~>QJdJB$e@t#C0~XWnk}oP>6_oGielK(1VH=ve
zDg=~_r8Osit6GXL@;yX$$VA}gIqfBD<16aSR3RH*QKR6$yLNW?{PBcOXvkYE{|HHZ
z!ucq~iERm=gapkeJ<Po`u<ZrS3tBn@=CcfWS!10n8_u%n8}qRk)Z>ya?l9H`u+ZOH
z%MPF8L|>lA<qtXdu6QX4e+$pb#Yvj~)%i@apUI0IS2*4sEXGHCXBqN~51^C@&XGT~
z;VZSr2a&TFCZTDuf1$u6e=IzH<r>t!FZSVk@+{J;c`!YrrI&4KLklN>=Qs4>H!MvZ
z_%`iO`C3+x|Eh2f>;Nyxu@i0Hv*wesTWug6kg6#``K-3YVXn$zAh!fj9e+IV-36w0
z7k|`?_#00*(w1KF(i%$Gbq33C|07G{YjeNN$&&})KNcmk%NPR`zpJWxv$F?VR1Hg<
z^#fCnT$qk0yvaWI21>^>jpR0BeQUQZw4PvW@k=kyNAq8x$jrVcvoSvD;r{*-ZwLP(
zp+!O73$J%gRow7ytbg6^P`D|UsO#)kk||fkv#hu1$(4<#qYgx0;6$~KR~>D!g=8w{
zQ4g}Q66pz%)d#Hm2@Tb8IJC7Cq=lT$;XG_#=R+oOIgO)YM+?eLh;J>H+cd>Q5BVgl
z6saEwM}|^=?3!YJcBNq+Qwr{A!=WQj^-UHQa?qp?kGzKI-w!gp+;atw;HBI~OWMqF
z+LHIa(%bSw{iI3T^Ra)V^Y?$Fr`dmBB!_G|M%#Z~(p>&JCu;rdi>+Mzq6FDv;j)!!
zJ32#GB5M!Y;nC?V{NaSRPuzkuBeYxZ+mB=)4Hm>AYF!QqKm32OwNZzPL>mj+55)2!
z!Y;2mR(?E*b_{XVp`_~c3AC;kFuH!C5=4@T!zdiu1XMd1X^4IN`o#+2C7E?#>UWM~
z3_N%8>pR(pe-e$%6XPU>r$yNo{Ov`}%0aRj0i88@-l67|$MzigW2<JA)8*8$2gW(h
z_o8B;Wk;%bJ+71C>H)LwC3%zg{IE}@uq8AZF2nz3mK?+R-X<TsB^$5<jY)7rdTlO*
zl1%c%@%Gkb4tZ+~H4ZRa(^eHY4Z_Poy_<SmgYW34gLuyORDyJ%e{LQPp8~6hgM`c~
zlstHDyW12j$1e_Kix#L=VA8eUWb?&3nx+M72>Ajo5C2q{p#MxRIy&@%9rthqM9$A^
zxSPx|O_W|^K|%e&&17L&q&!~M#E9+`Yg&R5t8omty1YT!u}&b_>41EMhSk1tmz5_r
zwYi96-3l8s(<OM0j+`#{IB~p^o5GRx%OK{G26Unm0Xg1#8IlE-<#`fW)}nSwI4_=<
zRO5;Yw%0SG)NIS+bfxHeLC#kSLuSVvyqI3Lyr~%IP~|`9w|E9Eev3e*2&QP4<`t^s
zQ5!w8c|Bb{+mSrQKxDn4;fO?%CAnpRVx}#hpy3v|IxC|DmS2l~cd;zz$Az^tOrX+?
ztc7Zfhf>mn7@psHSdxHQSdZ+>7bh}Lqs(}QcaYk<)%A3c{ofH-8f^cOvY`U29%_uv
z+Emg)lTN<E4o5}H?J`{jE?&33xN~g)x`RnJScV+#s3HRUR%@UqWtUM>I{xCFa7M5S
z9>J_$(WWTM1?X<Pnqb4*F=S8a#g5-%5;w%r8<7KfP4_FxJ9)Rk^L%vh&TyOoZdg0z
z9COv#^`HZ`)p%;0oAX>&!BtMx=TN&>1GjW_vR@HN;}Jr2yREwYFs{>UnV<uwY*<-g
zD=F5?Qib$;O>EvtKTKRYHS--Hr3zZ+9j<jfgu!UzyA!+6Qz6t6Tfz@m>NqOz=GUll
zdjJBeV^w&$#hlP6FG{2m!}(H-Yv%ST+!pxj!Z8S)iu5}9>fo0-0)6f2@3tW|Vh}s*
zSW{x-*1-N)+Wj56x|A^M!w58->n%B1*g)9E;Que}Hf7oTSNZ+H^i6Vy?5D;|x}`;m
zfIj*K|9cKb!+x@PB`xZe-Dn(hnxxvnc=-tyL&6=6>28pHpwsd%&*)SD0x(TDo3gf|
zb-~`?>}F2n_cG!M=qJ)>8Fun8WyCmb>Q^z-x!Ho1_ko#aHiRBGv#WHZv>Dj{Q$rCz
zNc<#?a^S-`8<p%}6Sll<joe<5wg$IRaFwM;cp9kyd6CpZ206C|Swg}Ekzpgxt@A;K
z>LkhXOnY+Y)$@LWkno#ly6_XfK!T9EiFflRj1uo8+Y-0FU>j$%H2*kx^pTI#q0X*~
z>hZ)3jGOdPNh_z%9JignShr>|k#EgAk=WoAB+n+Ct+|tlUADKn!_#X@v`99F)V*!q
z(rHc}&EHvIyp$5ejd!<N7bUr!wa;7rL=x=JKV2Mhj{TU)WHC9~V(V<dNb1l2A39qw
z4v&r`3|qZx??SA#**9hXaG(e0DJp2l9KT4S`xa0Y*mb;WYThfXSuuW`6h&VEVdz*z
za~MFu@w0a156+vgV}EC9`S||S{@1ISgCR)6)_WMXS|ok=JBbgt_05ywA|mxYY_%i5
zLSc9xn}k+q#z<BoOdz;)Fs!%r=Gtt~-FCj~B%9gn2ghw(sr@|<ywP&Ny=$H$K|Xgq
z(;5#k(WsCfz|q8P*MI*{<}){5%Bboau?2PaoWGD?`at2Albv+XKAk1@O?EWxDiixe
zxN1JV??2{;$H-eTO}{Q`>bu1I-RrHn{A+m#N^+e6b3Os<g_T6HxXRNDqH;yl<yFVv
z{k7V4XMOMY7CMC0#%t!OZw2%4+1B>=JN9*wl2;!>u#$vH4O^4Imni0M301odCca3g
zVQYUmx$OwgFnXFAwlX>mTrH^uzf=M9U!9<-{5Qe_$6s#No{P?K-VZLtQE(ztnUu+a
zhNnY(;cN`+aS8SeM+6^Fh~Zkfe{U4kE$y-7Q$Lnw=>xQ>4wFqvrZF4x_HS{NXEMA+
zA;p2}S@U^&c7e6-hWB6F;{pVyK)7iptVMaA6fX!=l+e+0C?he#>Lsg+SVZu##0kt9
zPUyRcojLIq1RkB}QI;p?P%0}`gECb#4fmS3dO{^CWc6S)7Sh%3qmM%v#EI2I-1LTx
zlS7@*_?h6!CJ|+2HS(%FTV1_)E^r=&vw+L<%WSy_(Z|=+Qc@v+bu}<Ny=SK-sf&#W
z)V0|7E676a_@93ZgZ?=tf}$dn9S8k$1`dmX0zy7R`dEu0Tg*~t{~<x-wxNz}4W(4I
zD=Mmk+TxzrJ;$gQ&JTx5Wsy5+Db5rDG?s<6Y&a2u(aV@GZLTJYD3{WkacL`h*kWH1
zR=!QIBnglw%MUFu!SGYjAM1hJuE3{kH1#SsEHmdy&ht%A-5r052h>t<BX9#~F9|uh
zLCAANdFv}v8*x3Yg+TVA=9ZT>8M=`!!j<uh-Llx!GSYAn)unk34kwiaMX0qE2MbY8
zN<JM7$?HjQLKHR}bk*byFv>(g$)vOm;+aAOpg#?S#2#GCA*Ps;QiyE=`;V645Iny@
zZB3-rywL?&5{dz56V4Lt+%l#RErLTrLTgo2xX#r_M|E}4-Sa{L5yZS#&iY!l`s+~r
zdro7w#?-;cK?RwVCrIP9Dz)9v8VAkksBYL=huXVr=u~0{iRTyi$?&eMD1t0nB^<!W
zg**`w$h1YhFQ_}r12$2v(tAqE=y;WI-I{waRJtG;76U4ubrd_cn-9mi-UTxyYpsnG
zAM2?kG_OnF(8*9I!YTgvM%yPkfm`1_y_5M4iOgB*F*<eD(s1n0{7xfHTdEXa%qOb1
zH7>yudp0^P@2&ghcwMcK%A5S21NgTw23(r8k+sLdlt)Zw8{EvI!{g>&Lxp-p&9Xh`
zwc0v|*Qf4Prl~?_*-qzz#*cA&x+dN7rnlJQ>S~iMJWnQ0#No#%C&x6mK|aEDV*MYc
zElctl2It<}&vTT^F)Gx_dEbV7V(N>jW3|;Lhc5O3#45Pxd^ha)%-Jfs50|2B0tzB^
zi$jJ-_l8Z#)}SeGaY>AOp!{_!fQGG{H|p)cXR^QxRL<fHR2&Op^FK)<AIJhj&E&zu
z2a^zAvWm&V%+fX7H+8C*zxiNhpL^D_Wd=-b6(=4>eub1swur-4P6Em9|6ZOrh22E5
z2jAZ&1(LtzvLu`czvfHZwqUcn?ZD3#YbPy4zY!!h;{I#Gc9);9-FyA4&E49F+Wh|2
zWa6<MHt+{m@7gu`cc~xv%%z20{t$<&Tr_0ckABFe{6j;H{5!jnp`sk};gbx3uG?)%
z`|4!gx>_emuk4RLIn8{9R-o`We!T%6PE>1obz*5m8Cgw&35_$>^kzCFr`}b|*0Eyz
z7=?L)hvuQ3W-q^M+*Uq+B+PC5xH~U?w2_zOc6WxY`K8~EpDT;WdX{LNxVckPInA$1
zaW@BHp8L<I)0H{ax2n;y-F5dx9*r@KX4v}l(>tvBU;e9`QXvR$U_71u$c$YiW^6^a
z>%Z(>>#jj>pSzyU`cX9~J)li^@tMZWVb@+3OdTCOog4#h|7ft!{WlVse{mK*eG6sm
zjjsW{<o(f?4vq|JwN-D3=6BOE&L5+5{3GdZhOORC{Ms*B5R0fY?y;EUA55%ul-USu
ztOt0fhb6*|p$$6bQo$Wwaz|K6oNQFV!~dIAb)bXj>&{p-!mT!^gIj#~Jo9t+4&=q*
zOW2!pC21a|^Ppj?7D7{FB&Uih_*X2^`snKClHCSFdlRI;Q*Ek=k^Ux%>;nz)X!4-G
zzSwzxZgwoQ@N+fi6v^DHl4D`dMLFX~vrldGggae~z(hX3y*9$QjH!k9yGV0zTjJxV
z8^1na=c%_idF;jGuAL{l?dI+Npm#{hW2Y!JflU(~-ehehJGrta#y|D)MxU_S3ZDw_
z{V+jhe|`|^Xe!Z}qW}f7sxQw2qwbmtGece_vr1YtZ>D-EPcJ~WK&i08G3;L!b(<ew
z3-a7L@JL{0r{mGStlE>=-cH^ItkxN#_5r@m%l%_?1@?0sG6+D|vdLvX<u<;gH|mBF
z&{5+)MX6z{YREI~r#%RR%d|aB$uYL$h>6p|XTE9#`&7p19M)qxnFTv#_gHLV)>E9~
zJG~r5%>{&>o<g(*%`fOJu|u}END?wlHcCQ^5f>%*<P4s8;#-2TlZd+qU@g9#@X?f&
zuY8y$0R{n494#sC2uhZIW;LxT%yuhnxoR1dVn~8Y(mW)BRyC-O?#(XBTBVXf8z6E9
zpM^*~EF(o&VB93mA<$de?N|T+Jrz7xqPzR){>Eh^5OI><5pWt5IW(21?zF&-5PG+4
zQ$W;-7%16CZN9ZBWzPVa`$c4_tae4(!7C`90i-{}f<qlH=5je{CxiHcBM7T^$|#QB
z;Kn^fDbFp(UC`vm<EsNDoJmoaAl{lPj<->Ju}A%itMV&pHXJ}k;?piJXL_ZDB5z9J
zNbnVw1^6ginKM|8@heGrUILJEzBHY*nrOh%WiWuYg`{3dqx91NB4}43tU8~&%TvVG
zu_Ngo;I|A9+R#57nh+Iewj*hxQXaqvR!f<S{@!Uq=0%F7)M7WyZG0*L8#AKPMH^vM
zyL&r8@@`rl*~O`D=nbf?K}G^f7-OvQ)#)*t9>$aJvC=6&p5Hj)@d^Wtg|eM0x1gPg
z$D6Abq5x5)ulriacx<nQu-3DYyO!+qAW!P<6{FL1TbRwf5Js2wF+Q)2Qk$r1Pb2TC
z#&YU^4Chy=`C%K(|B}OTv|D%Og2{qJNadBul#Q^lxEyxfN&eFX+XxeN_ZC*tPHJp-
zrP{g*rW%EY(G@h+dwZp{S;3UOA$4*lY=}rhk<kECUCSxjYd27=spb{^sn<{=20bfs
zkEYYwfd?xRn527il4>_MJZg>i@`Ui8DK56jG)eNYVtD!un6}*R%=W?Jq_vAhj@=9s
z^DO4w*HvB3TsJ+dRz9)@(aRY&AxP{M-s~eByOO^zI7WZQI+}NzP_IX0ve*j`*e@1F
zg5zrIjt@@Q!IMQ6$4xu0PJ(u+hQ|4{cki>5mAGK<`6@F-jDz@U!aSqpBYo}ru96?(
z!*1+N4v!{-rt06Wk_`-_of-!Vd;XVfWbsE`m5l_<(Kol8=bnro=D`-miutK?=JKCD
zXnA{imv0i%6Pzffe}YQprxCdN2<oTrvT)1cixQ)!KRS8`=e>{oC!=PvEV%0>nQi~8
z1kxRe4gLnr)-$XNES;Tc*jluw5@s>s*s0^Fg-1!4wnt9Vil`1celb}0Eub#2P;_}=
z4ne#|RvL6FwSHhAiuD0Zxxx$t<Hspt)#v!wb=wud)WmG#U!m-8l1RDDoQAELhMEzh
zRJ3PYk(BIYKgp^C?T_7dhRr-Mp3%oN{NeCQb-HTYoBWM7tK(8rw6S>3esIXf{y53A
zYgkJj^_Jf#?CvYr-4^D(+`S;#{nxYMG4$R3%#SS=?P@Z@UU9-~`L9!38vC@CA3X*<
zn%S<$av!uwcw%zU|JE=y<sYt3?aFsisb9q_B)@jOEuZ*}kGKV;*)^b)In1drbL|%~
z7{?>w`+{yR;ich0h_SqQbRf2o9nV&GHFLm7+zWitoW`Pp2BWlUzb|to=@ab0yZsU{
zujIFqxTGAeNULqbCS#t-`*TE6QR@v=A|YrhF!*W?S(>qLPt=hwKvQZ7)<JuYr}2Bp
zaHi+W@^lQ$m(on<V9^}+fWy+&KT9T(9oY>#j{OU}?1+rOr(hBK+T^7n%|9!|I6rrG
zz^*)UoNP0Nao)(Q>zp~-2n==8H)Z7&Qw>-6fusfXDG<JmMZa^3?5EId?UfiCY0_^U
ztrHqLj*80|UV4eENE3e`kU4c7P^g9kT)N;H#8nWetI?&It1Tg*HxZo2(WcAmvtO(&
zp3FY22NVfne@b);w+jkQ&HG?sxh2n*5VPj>CAk?aHI=m)i>jlQ8S&Yb6%?B!o#q(S
zwt8Q05|$hpKdHy-GY_;Fye%ZGD%pnMst6l~JwIfp;C40M7n@3q>bMU!PO_8JyM@G(
z>xg~0MVaL_r)ouxp=%^2=e2>n^r6geRK`SgDu`CLb^4{9PVAufz7oTmTb;fVEl^Uq
z!=P7(WN_N?s=rmLA5O<$)w9PW76~0dj+%(47)VsFE*s5eTBJ^9x)8Zs#IQ@itL%6%
zIhWuAL3E<Hk^Op<>_g0mP+bTN#?3;1&!TRu-i{WsH+z%S6v|zR6n@ZKo3}EBMs?K@
zM33W%k~{8gu)GAOd^6le^f;P)H<*B%74=r4Q<l6uJz>=R+#^s0QA&NfA$Tko;>{kg
zRq(^XT4+-N>3P^iwFJWhXBz`w9s?kHLc3k{>FUvcqqVp$3j9i*;HH#6<+ylU{IXz`
zWRu|H)^6^=Vl85bzO@&RCu%ZgXKl#F?lohrjR~G7HZQ0NlHndPkct-MpdfcgA91HZ
z8x->TSW}vKe4xlX9OyP4;}Ijv-wOsJfvd?pIl~=l?<qIX+1+unj#-12(r05tO8S|X
zqIuWfJ$Oo#4ZY;BbvCK&rXxQg3fCoz-IVbTZaX|j$7QyRY|WdsO&%bsAvyw{WOIY`
zX;HD-tVqUZjtC-@l&!uXru_E282Bm;tovn@ddsdE#e~D>=|;8e!7<t&z4Uq|zZJTO
z#xa+T_oG!&aZs&G{Hwj*!wMr0)4k$r8w%MPlx+Don1fDQe5ERRWi_=d!TCBzqE6am
z<Uz7}ROfc4+Pjow=j?J49t~h$VwX=a&c&7Fan=CW<`4+V{+z;el5L`P7ds5YV28SC
z@4nB5+<ub3<5Af0Eqj7;d;AhBd@+7~=I1T*RQ2TdX^0gR?V0N+oGn3F^;=RXFqW{>
zCagj=)mcdb8^({7-h1+cfN@H8fGytT*Ul-z>pp~OIdUR$*q7Unejlrr*qk?68Nlpd
zK8<0`!FQmSjJ%DVY*_fxne?aL=k069(*aAb?k7!Z$!pJ>9MvZ)m#5Bge(^ur81eiH
z1&H0v!@O>pAP0%Cd)RSLK6Ukcc3YXTbr{R<*fV4ADaW&UO&(_LiQuveB~Nddcy>N5
z{^3mCll{kOn`>SeV-Pd6ew1$au9r{SoBt(R9@(GJn?t0pU9!E<Flx?kW4}#N<e&R@
zjkyJ4HAimGZ9i{eWeL8n@nmFGy}&O@1dsM+bx|~3aOlL=@v3bYAPE{#9)5<bL!rdB
z22n&-_2@L)w#O-kE(x!x#s){jRt-{{yS`~QUvBg25pXQ)6$}lYv3!1Nn_ps$J?*^P
z+B+8{%W7~I)XVWo4Q<Tho?yIvDe_FmS872hpi<Lz&P7$St%7Fdw}$N6Gww*-Gzd4i
zC!IU%sWF^AAQ1k_(z1n*Z7Ukt`|bAD0|P^fr$nZ{KFtYF!&&jN+m|_0tKe<dzfRNe
z$eBek%+_R0#Q3`}S+cn|%$vX92wX<3sjq&BYc!yf1L33EXXO#!(PtW=r$PdRBGP@8
zmpnB%MwDiMl2P>fG3!95Yo+FshR+WFTnA$bEn+Mfg9->5YQ7RtR}!Ppn77-10!gm4
zmR|Y1kYQ_{-U&UCr2VadhR_~9vn?3~K^I~L%}ENG#$mLuHB8#wHhxGR&#RC5@|T%p
zy28Iih}2!;hb*4;FYgx6B!O`6{OoY^BR1rlGHB8ojQWJ{D`|E~J9RgJA7<q~e4&^c
z{>JtATx$}^nzr&%OWSX^-?Co?Ik6D3u+ZtkgIEXTrcz!=-Ml<of+Xt!j@>~)dV3Bq
zO-C}8Ge$R|ju$k>Q4zwl>27rlK91r+EI8Z&QJ4G!bpJ)tX5^EN(QMLF&0>iK*$ZNk
ziFuzBDSSM)3TrMS{fGb;p|f-qlK2$O%ug;t;-oVtYxf6!;xZcU84dkh5@uZ;D=0?<
zC_C|4?%NE730w%q5P(FyPi$%GkhPiUUkgefIbIlS(Tx}X3h3}N&gdW9vTUkF)mtze
z?lxXGh1=msVeGsGl!xa<9c90}8Ufkjc@|$|vFr5KV#fFmvfjYEixN0=DN#)r3@)lD
zAcO2wtkG9B&o`W~QG3E%IS+||DqF;HNVD?yzIv=0N?LkH>d4^5X+L*vXPv0VvAhY1
z50zNTg93LJ@J89<Eq0V*iMCn}1#bYYh7TK{pBGAvWY3u%aSrj{tds|6RBz?FC@bcQ
zNXJzftGsICFXWd_aRI{1z^IDp(_D5rR__ggXexJ)@S7N1rFXT{mpHl>4VB_{@Y-pp
z3935nv%yekDf^?OzD0Ro7wK>!W7%y&Hd<|`dky(;h^{K-<?2C6ndMPy<c&;D#&8_`
zBcOwXa<LTz<f`P~iYn*L@V+4QMJ1xuM4dWF5;F+TrK&6*4>=uM<Zkjr8a5NHLNS0_
zSyk-*N>nG=ImM`;?MPJ|#L4L*2&9eM%RMM$m|!Pa6dPaQ*Pt<W3hobx(e?~mqpYh@
zM#qj<DQj1NUBhnB__l^pRLN@xUx^$?R*L3qz;Z9w*3f(8WutC07G%B)B@c4Fnc5Q^
zFD@CwRy(=CI|>~5F@FarV5*Tht+u8oXUtmrZ87{vR3t%{Sd&jel6Afhug`Ea=`B@I
z%F_B!d@pb!xS$|enml%Ubs=(4+aP&jCk^f87&Zx_DM$?bIK@qVZ_Rx^gm;nRNIz4D
z+KKcIMZAIcG49#!Gy5qOm<q;dJ_5T9!!Pb;_2uI9;-Q}+J1ehChB$gDHuDdJA-Ze7
zJK`trob^_I#!8NK?+H)l<g*u~n-YYo-bqZqa$%qEwql%=k;}Y}WIF2pO{RBARVMX8
zKfmKOySH;VPq=$(+iVzlHmhm`n}p+L&+bZ`aY$1<1>NhDkbMnXNmirfG>#9-ZPpM1
zm|3}o0OsVPJmqU+?N8t9ubs62d|)Kx{!^F|7(6^KUHLNQlaObOQSkC=Nl1a4f~Q>k
zbkcY{4CK4Bxi_h%@rE4aO1;Gth&}Qv3`p*v3}yeG;`Esd?ef3ancKO(aNeI2>=(}|
zwtwtDS{klop6VU{Va!@TLrm!_YMr};*8|G}zsPq=B)!1X7&sBF<0V9=3yX;D!_QLA
zM9~*On0@kld0@5GwYI%&tVt}#FMNr42jtB>{^Y~^>~fSH{`Alpncie=5B||rvqNCK
z)?dpwT7Gs<2zL)b-Uoyuub4>pzA>a;#AstIu@>vK)su)}Yq`QE;Z-#qJ~Ko$Y5ZtM
zek0R@>}48IyTS7u$NHQnHoal_7>mcYGhdi}l@@}M*t3)^rtZDL!vC???B+IE1~at$
zw+Rn`Y^liJYp(r@Bf<V9(=Jc{kK8=;%}-yMWhYp$3&v<b1;g=+T3=`5qf_GE2dpa$
zE=KScew@?RyOAH86;a<1%zrkyJicVAm-;IxZ29cnCGJ-AyEDeC`NOyFnA2)2(>=VZ
zz_2w-Ryf`iOw%57g+07&Cert~g!DF=Zcg5l4kBcjt9k=OUM=!I*ofoO7-~nS>nz<$
zg$fkg;z{QRo*>Zeb1!pbVY3lr6~A+R>RMK267NQL%+ZLhLil&M|GC|qwDVa>Vthq|
z^J|K%XxX{xw7n@Ew=XtAx^jMPrY2iDc*>)dEg?*-nq^Z$zi};e>mp>Fs2PjRI&2@F
zU1)CgLBJ?2#_?6m(R;b;>xaAP7e+Xsy?IjhZqKFQvTG8@s-@)F473Ngs7iQ6(zP$8
zADybFRH@fh;i1cycblpclVU(+ZLeWjZ@3)Z9x~>0Th6oE8oF_U)bA;&Y>cX9abN}`
zmdh^05lL%~i!!;iltvd9;Wvjpn+L6iP*67qCFyAt*XU?-;%-P0l4Wmn`(4XsyV$9<
z2J)bHkn|L-R*J_dE5RDhB24Q#=mTf`a4cazzye_2rfRIC9rRJ9A&AGYX-j_%qsA^N
zxk+|cW-}>8VurcLKy{gL3HF%ikZyUW>$Oa`Ih2tqIM=0iE-?3i*LP5`r2vs&ZqB?&
z{jN^fx_emXTkmQ3_5K&;!zRxOM)Q2I<d_qT)+sl7?3Db1e$Ez_$zWKdkp_{Cs1)0g
zgaHY~0Sur@v}%Zm+WazVGcgdRakAXkq_6KhB!h(zk+Lytna477KJ^-Q4UX01YA!T@
zXjRMmUF@a~H&bBRv_%_3H1n&3EcAu0Peq7X5AtSX#)BMM$A6$;D_V|6AYPs9%YPcQ
z*(>f&!#*#>!1IU|la`93xz;jp(x7sw>_l*}&eWb51V%Jd-pkQ1JR(9>SN%Lc!J;lC
z<tNNJB^x2Fzkd<-a8$`}fpQf-UR4freM_(>z%PCT#zCoB&Z+6u>`I7`&uhv7hK)m2
zrb`uO`!qj|pgPZmDDHkCdx2vAu%M)W*e|a{gvmGAqu#vH`|$VOXH;o#M++wjZ7J`6
z>DbP>9n6{OPtou#dQK9yY-PaSqDlV9<u=X-VXd?;DD6YuvXiMx!a3cn=VikW(py>@
zd;(na#p7b-la+bQctc1rc45bUwLR#Q>6i%8P=VgXQ$0x%3E30!v88l>nB%dUr`gCu
zjj?Ww7Y&5O&*m0>hGZNoCFxVxv6<PuGv9NsA3>#6Z5d~J?dTOQJi_s%8n$lSEW<Wb
zte;eIdA<-Ux^ychI!V|gTwjog@UpKrto&K5a`weBlGl}iC3|9bS^QSynZIxGNZ*{*
z)-d_>7?Wmk{dJeK`F-<_WT#fz+Zx5Ad!_3>;KLucY}Yf+FVGVh!H6y5T)%Q5&D}m0
z7`|!g(d%gM2{0|`+Hb!-e)-q6<{NhK-oxx}AY_?ecAwL8FA-&LIAkbkfCqS9IxBxK
z&ZAtesI6bVD6>!TWv8R>&6D<n|01!8e`H^9BcHY54@sr3wfyW|g+K9osf8y7Q~Ulm
z@-c?3-ql(U9xibdECmF9an!@GRo%><P_@)u3r2cx0Ys2nB3{JkFTR;7L{I37#TYQI
zs1rlWo(x;bKFhG0ny_tGvBmBgvvPhLt=Co1eE9-@Upz^ew_Tqi+5B+(<F>uulY~z>
zr?`@`vp3oHelQt}`_Cy_!v_{D4L6@(*dnuD8n&iq9Zie9cO+ru_=QRSx)DD*dZK4G
zBSH4&FrJ0)oim$`IJ5TO>yr{y4JZ~eIuI1(Z(WKG-+2DA6+fV#JkKa*_;yR9WWUY)
z#nG90^WPjY`_8_W9iK`Uf*4EdPL6eUQH42rBZldx!q$bsukxz6iE9man$M@O#d84{
zS6hQlZinBkT$ax!sSC`<fD=0>M&h=Y&%cx)mGbg(g0G~FWVN*dhVQ$}MyP#T-n1+W
zVP}yS+JmCMlV6G8;daN_czBS<!Zq_uY)<>6{8l>E(6T4`%Iu11P6Zg?c|H-GJ0`94
zhDATm_bL87$%lMvxfwpF5nXKHtaXIe^j{z1sq@Y`tgxSCf4||Zt&cbjvB^-9E$K0!
zgD!qIZ>QgVG420^g&v9ePx~Gerv$@(W5|+VZsVY>u?!l>qs&@CaP<g3<<+zzyA-Tr
z_H}NI%urs7=D0c$?D{xb(>JE2?^OmBdc!MkuzL+#QDK^_r(oTdVmSwLMgb4%f<CoU
zGY`3*8o9fvLX02MBQ==M4vVZ8Aeu+uos3$h78DP}Dv%QmTZNRlNny~K1*XFQ#!Xa&
zt`kM_^aT%~l^+63v))hkGk$%-6r#_bL5|<aBBaDlQ8-pafy*`kBK5Xt*O*H@A8oYj
zp<r|{8_RhU4^~HCD0q&^H2HgigLNPd+}46mcO#1)DaF0q3x^dmo%_U*Owf-OL$V^@
zI8H^fClA=)au$61>`P?KhbhH2Kh34gaIe8@p8!KA^Rqbg<xoFeYf#GcBCB?|`a}zX
z79vXMt)St3-}c{%4`B_T9PdHW4OS-ek|r=8Ecuv#><EAjn5vLFkX00mBjG7A9LzCI
zInts~XVE4M?W!?j!)p<}PZ;I>$I{H1?6d|xB6le>4aS6(Y!FW1;*~=iW*!Z4vf7%l
zrgG15?9o@sj!66*S(;St0{$8_NfrY$YstP1o0>!g6BA-g(Guty`1t|H6>q%BxjD2I
z|Azzh1RxD%Pf((cU&8P7@`uSP(Ftyg-EIpdQKG23Oa>=pCOXnMeF&x>7_cC+*+}c+
zmA-U+kGD+4rv|Ev+5%=oxVXS2mM8?GvNBtxsMBD30-r#2nR(I8*!Y?hK;%zxA!9Go
zMLCPbOScIUXouOvW<9w@DsN7Bz{Tqey;S4Fjkv6NK&20Fn@{cS8&PeB`|6nGH{VG2
zhq0(x7}9!ew?7kp9S?mYTbcHS|HWNq<Ky1!XJ?FU!%4RCYHHW57<G~XNsPp;7r0`Q
zZ;of%=m*d#5}+`8OS%Fl`JLE_0<WZxvN!dKf1RG@44XNqVGkc(ZP`grAAO(QR=$lm
zOM`VpMcy1TKJH>Z&?<7!z73>JW|wQ28BX#kxj*P^IpJsp`|ftX!;xsXm|hb0Y)8t!
z0dowIlg73BfOb!~XIgdPg@AHKxw>to&C#jpZ}iD3<)zqHpG<BlZ;K-rN-B@Yl}6G`
z_i+NzH!Zur+{VJwRf%`imf&EMPlwEY<v&qYPbTf~rHg0s?eDYX8=r5mNqAp<c3rR3
z8zasicq+Gr@{+pp^H^U&%gDnQSjN~6ypO5%yV8-v*>r0E>;jgHX6IS6;S0t)n?YwB
z7iIb;XRo`$5_fN3R#o?FTaph<+C8H;^QK5_RAcI)wJXV!^ABvd15YFQ@I>xf|8OL+
zyWh-^<_0tGKg?6=_8BYw6!DG?CXNF|to5&<t+j3*w}e-1w!qJ%$`(DmNqKsJcOqEF
zONdZ(S!HdVq00Diy8?QGSdISiA_MM*4ZilxP7!noW9O&Y&<Ds80dZ<#M4J5CnQ`)<
zTBSdT4w$SU2MlE0!2!Ceaeyx#J>c7~2$Q_}9A=>#(!>X#F=-BmY;}_`0Z~mS;Cp`?
zHMJ2Y;Y>n?t@GuxFY-2c!jA8Lh@|_0;xRWjZ}&3<ekk?syJ{R<w8dvbx^!ap&&}?;
zlFYvTpR$qvJ0XPMznUKV7+trMNohy6TXx$&@~C-eC{OSD7+d(RpN?A3Fkt4CzLZJL
zvN_Zi`A!`Zx;M~8K$W6{SJc1Ukymuc`N1Sf%Z6I5o*-`CywrM<-{CVH*9yLV4)cf_
zSSlbkmE_pwc5HXtP%sa>@VyHea4Rop-G5*p(HvWU5EdNUa_S6p8sb|qA{@4NoAOQo
z?LU&bC1jmR84)F)vMapV4@k=wdE#s=^pjhTWJ;zr`!ndL;P-5t#fkEk54m*U0h}i^
zvik0uY%X~ynP>GiK48;oKrKyue7Uf{36?&brrJ{#A?K>!Do7<2+`m4cgYM_<tXyAO
zv$UURYiT?&B+CIZ)d4L@#py6KU?D)E&z_&%<sHBpG)m1wV$z6{qaW~|SV5Gq@8mrZ
zl9yf`oU4G2f_x;&ERdirQQ#tCfsv0^&1_yW_JmRt9AH@!2Z<eo15~>fDrO7^GEYxk
z!#02ezbgrc$)7njf-sm=Q18d4?@baJZE!g?OQmR>NdbMrRL1gJI?;lhEI4i%pQz!6
zLu|a5HC#M}Dq^|hS<-O3^!>e1>ArN!Q=P!x_rduNje~<x_W|d1ZS%nmb#<MSPrxx9
zTwUxj(oCc*5St^KWDBXcmO<VJBta%gvXUH;WU@q@DrPI^ERY4fOU;x_<8Vl2{vDnO
z1y&XYgi{b5FYMZ1lIZh=fJY7>VQ?cex8>;t%jBRPpo&UN4Ruyg;xJVs2euz_+=*!v
zuTAyADAZXPM~}uUYG6EnmIXS(8oegLS#MZQ1Dw#^BD9X5*Gq?hItZ~fU4*L?=o7||
zdDfJ@GaHBGID|p8_wjQ`OoO;~W=uhwz)QeqJ_@X?sssm-#!H67@r&QY338kbNm~xJ
zgvA&-kY~4ZQNO|A(TtDhUUREGDF~S$C<SS<Cq&7ha-t;JN*nS>OTu&29GLd&MC_KA
zchf})QXW*Qo6VX!X;qDkPmo(uHc2d`o@t4oL;y|9hLkci;vJZoD)*BF_Xd)kq=y)j
z#llesiZuW`nKuSV9&J|(N?*05&YL6)kT^sp=}NL-y`en2;x%F(UWh+{1E?*a-599?
zs%<|3hh<?mmi0*HDpliD%#1NmisT5Jl|wNSlCC4E`3^T_mR`VYfJj8@<Pfh8?8UJn
zG`6w>Q9qra&F;fIObPQ6ReyDN+O|a=byeKS(;-$PrJdPCl?WTy@JEaTLj)zOD7}GX
zYtky&!%?+WZa5*O;*rAVaFv9n2-2d3i4(@t!v}4)RT8stww*QFw5$x!4)#p8G|bwz
zL3mBIk|G$qvX}?~YU3%BF_Gdh9`TIN&$cwFVSLn7LdmZx0FU_rFUj^R`z&$s6G<tX
zXap}VU<)zY8dm6JNPx<MIK*os=*=p|QbDaC=%!3MIciXF=y<#w5?S>rg41;!M#--7
zRPcsSk#xB$*$#9#1R=TsN@Npo!fz42CK^=z5ym(jQon{nr45PY)?#0<yOUNgMwuQ)
z{eeThL9LxC5UpKMw5U+$aMf+OtDY<!t&2uk>pY`;)?#W8Z(nAGirBST^<eZi6@=62
zOtEVarAWzzu-q%~x=96{bY?q<)e<1g7N9aoQ{RPd85O3Q+U|ytQcg-<sl_C_AqeEU
zo~<4064;vb^w5~`1eJ`KOWK~i5Adky2~$vraFS=0PtYl!DFv0ZLlB2t0W4(LS<&WA
zTgbu;8XR#f<_;x1*n%ZtKY{8PwAB(0B;wfvs$})Cia^5j!P%5x7Q|u5E@FPSdU}%5
z5GrlTlrknnaoIbzf-MkW>xZ#CJ%M)4ua?B<iE&h{oLuT%D-jY_vZY#Lz5P0cWP#Ot
zurBo~$|?Q0QK-FEW(O5X&eif3B(1nOe!T(7oTw6hU0zs1DOM0{I5^kw^>=T$xK9*0
zM#VHJR*SoyD3Wb?o=cqAoT^gFM@w>>@H`7Lk!VKwB((<ZUZVAc78FV<9bF}Lt4>@5
zWIkfb1pY6p0y(Kci-%gIiU{XftSc)CB4W#nOMPL^vZJD6F>m_Pn!L?@SN!0m5IH7F
zQVW6lJ3|(2zeE)zQj3NQzDknYmf$HGiqZ>wx&eh>heHtQ;W>e$MnrJFcC0BV5tCi7
zo1>+r!;rU1<AZs^P^8E=;LJO6+$T^VPJ>f~4!%R-NU7pnR+A8!X6UD;sjCi}F_hhR
z!r?y7hkzR=Gg&tQm^d}JvcSRAb1bHMM%l7T5A9H1OE$P4k_jTqro+m4FYrj$izbGj
zlJ||`th}0p@9Y$?jVMmRWy^ZKP}79ZIEIO4<&DUGr%D?2DSRT#*<YVQp7(=&8s1H|
zc-dFCkJmGb*`(;KeLltf)^)my_>C^{G*hW3Cfm&ull~FPAE&H*7w1WSkMXXI%lMw>
zZ@fHr$L?BS_r;O0r#(2%GWxhjBxVy`>7eWd1zT9Mm$<*fD2MU|GUU54!q4FSs3RAu
z634Rf?YHO2FmKyaaJQ2NbEDy1#3Poi+*Aa6w#XY-N>^KhTH-37ThnbGD&;sD%<!cl
zH>tVuz5oMFteku?=3~F#)MqL|5AAf8e?QBw5l4<)$*(-YQ*CNnVNbqhrro-O_UgdX
zd@isgUUpYZmLbB2T#~;p(bQT`n9bi88?q`{*hQGvc`>+dTxnSG+I=Ie(l`qzU+e6?
zZ+V;e&xva%j2!am!djn2(uFtE`w3_H_P~Ai<(kKqw=hQZ?DC|Typ&h_cH~Kb9G8W!
zpIO-Ff5%xXV8G^y+%FUyc(~UUcF2-3oByXF{GWI3GT+|0-M%v#iqR8^g->FzTI*GF
zBH=whOZllbhh%T&x%Y%1igmm?QDBvb)yGTTUlT=N0O5!}!5F@DUK%J2iWn4=H{f<3
z{)>Sb)?|WKR5CUKx-o48yzEbCruP28%FfcxtCg(2MCpkncTZ^VyqHg8t7d4$2W^x@
zDW?Zw*4ixOxMP3yin!mJS0kBb`tr@ye%$cnP7Y4{l+RZDm`&=dAMgItFg;z|6Xoue
ztpD25i|CX!nTUHPWMu+VK(?5hK4Qtv1GMZVc8S*c!Y^6zoqfTk{(-0L<S?ynJ2Ch0
zMSQk}cdH)%77ySLW7e(##Y)O^au5)?-0=CqQ_h)C=;@GqBi(hpP9s_o)8_y|J)Pv?
z>oDg9U90H4n2`Q~&Bl#@G2jVg4%p7F;(-w^#|9@!1xy7>mPpE4Z&<l16gJNDtz6TP
z{rQ=7y;V~lUbi?7pAjXJw0^zn3)|1+eB~mbGDle4TX{cy`B{C5vLDDVq?0|8wh}&P
z!p;@xF#@k?_(^MLKKcAbGAi&p+&{1_HUApcOEtb=uoL{n<nO5lt;N~kzEn|eaSd+{
zTZFC;+M1Hul5S10hFe8Q79EX-@)PqkxJtox1j5b%feBIw1J0mJYoW>2^Q$679*mZW
z&>x`F_H9)OC-F+dN<k$na9cEa9Q{=i@|irhFi~4(8f9bZDbBf^g+K?IPR}d2514_b
z$YSX^W#3gG9|++qCiqf(O5S*q+U{kls>WT~S0QLg%)VeL>a;J?4Tw6aBzu{FR?;II
z5S@yOksL#_lnrOg0o~MWT*;SxY>=#g@Wy!+u8!--ADV>}$g>u`(OBU|>+r0;Z+R;%
zkE->sa8r;j^Bd(cC$^CT^31HM$dzhzorloV8y_>`1rVu!4!sg@(=<Sh1`*GT3yLs^
z-~ys3ubhzyf-h@i6WmD+6)11i)-i4#@jOcLg{#(&z-<W=FUYE^tp7jO-Uq(6qq^^1
zd!Mayw{&HDUs<+gW8;x5U(3dU<3Axc;FystKoB<wYQW(Ua<1c0hotnTae_$<jC5rq
z2nFFdscC3)aQxa^m(tsomyb($pKLp%&!K*Kmy{%=pXBpVQ^Lm(;B!Nr;5ZI`-{0(g
zj*fIConzW1o!K*M*37I~^LNe6o;|*09nQ9l_(pY3w6xZe@+7(bRQ-%m<htRNHVlWM
zD#S-oaD<TzoM-~c@_ujC5QNwl+Q=u7J}iON_0JPS6hYD`RmSQ1yy75{+qHldfej3V
zYU(~3>pa`As^Ep@Jp&=Ig!Kt(!~-D-F_Uw3kdRQ?*I08cB+lVOky*@Ekp`YuN46|b
zn)0xOADk%r`$K?Ps>*i(A%@Y4c|VY1r{6um-dcvB{t!uzbWz8>Lv%7tkCt2Ou1Oi2
zl+o^`EB~TtS;=!)kOa3NV3iCUkNjgv@Y6W7!~}vijp6yv8_bpwyHoO7V#+Hzya$3x
zWt=sl6^hq?vX7jx(wM<J?NjpBP0V&oAodq;Fe}}K<hX<H+M-sr#^ELQT78l1Vs*p`
zo8KM4#<s98dA`v+(sa)MCRO*LgJ~4>OR~(qovkJ%@6;1nVV{3hepdUiLunr=Q|@*_
zZGB}jlKopOpRKDSy6zkNADQTffV)Qceq3W(SD<deM-Z04-HRZ97W-+rXkOvLQRUE2
zpLp-g*zwd}tD)EzTvP$pUH7zhMu&mZ2M&ctf6e>k^yu1h%Wd)c*6&>)o6`%){VK?l
zY37by;U1n2K4gD-&P;ORs$2(jxIFM>jvHCA{6_>ut=zrAItZ#FSx216^}B+q%FA>L
zzry94l=N^Q!p)P1*$R50xg(tIQ7|16yZDQAcbn&0lf0+@@ym3WI*GP;IK(f~r$<iH
zXWxmk7tf{<COdj|zBc}c=mCmh5X6&jUq!b`FHNIXrT}^sPg-yLFAk)|t1qH2e0p@L
zOwJp%o4Hm89$70urTO?mQGTw&9XqQRWkstzI3ND+^Yaqlfe=n!YWdfHi)r*zE5Tkc
z7b~QU@DzD_=qd#GJ1aKQdc@h<e*%-u7Vi4rTd{k-@DgVaELrN`PN{!uYIS+zkDIny
z@Sa~!>Z({0rq>Ud8B<JsFSIIN?E67jk?*#+y5x#V!_29#QmmpF3PjkMXe2Fkz%cg@
zy#nd0o3Xfl`c{&Ya`@JF@%#iSy!~yBFSWi6O*|S{zhSrawT<SBhROve3?Ip|pF5E(
zsRlWuF-OnVA=&fbC%yim5#QBk%|HD*vwy*G&<Y2&B0?rlQnj8)iWXu0+<VToKeLOX
zSj79jP+G$$-@4T1UcZXS4PBHby0l2w@MN0%2T=uDYKlj0resc@Ywiu_(ciD4%mrHI
z*IzL+>E1YE?%j8!tLyJblBKaRYff-2M64J}Sn)Yo5`HS<^2J;!5-X3e`+%39O0XA~
z5dDxAFY0#=VQ+91gLJ@P7bs@SHpLcA$^MA01`kf+9dh=~oANn-K8c?|d!zHr(kCd7
zfS|dyw59u_?a7NAt|6dvHPow)j90grVx!mK#c3Yv{*UhQJ$*Jj&A{$$j$s?W>fOBJ
zKe0#|!y1R&AF<PsZ7};o*7O`wdG>ft+SBvNiMVaVl>tnCAK^F&1Cf996$x=si1*ym
zOzgAi;_AvxDQk{%w%lR)H2nNXl7AM84p)jX7I4|m71R4As(Zjl?SBg>|IZKd7X9`j
zbu^v{K;J1eF97l<`61PI>T#_y)v(h1f=kWerfYyI4#z>RdP*znAaE;Ax6xEJyh~hd
zvN7sTF9@Z4FtA=07!I(OtHPxiTxw=3JY_h28=>T&|4=}_Xc3u}X^3$X-n<7lmXZ>l
zrLx_27;8pSV0^|*Ffc;8*))oWZAk?K{4yn-_s_k|3*QAo4+m=5QQmu#Pw5_%=L5_J
zENQ_Y?bSI#l8Ap4q&4wSOjPfZO;Jr1Cf9{<$JucV$Tr+2Z}TpDffa!lw4A($fh^_x
zAdTFenVlxQw3I#|1qkuR{<7<ua?I#z$&&g44v%{%Ahn<Y+(%uMAT9<A=I^LGW!xdE
z<({~uP-*ipiXl?AqrVbl5)s;#1*>66&rmz62b>QB%c65<QVtpX%zzQYy1K;YaRh!j
zVv3-*#DZ*VHI8>wRy#rnoDyXfqiOU`E5&%=MGY{4-#|bbK4pb@1xnwp$mhmGCA@(9
zLn_WL#6)leAw2slzG2Q`S1WewN>;AHkb0Lm+Qka9w5*z*^#Yx%=}*Og(oh?ws(0i+
zM*#vIem<=ebAgO2T{X15)AufV?`zZ~eg_c|*X-=@7~0v2QC19Ay+Q0w`(y2TDq9gk
zs4cU4(y#F~*BUd_<AWJ85fHNO4{cr63i{Iqll^z4%P*|ShcUpT8Hp)<uyV6-*oK9f
zh18apL@kx20;eK%vkXP)qpH|#(DT$*nDbaeH`jE@IBOt~*-h=*wZ~(ewlNg!?6usE
zQ0Gt=D{gjp?B(2Ovc1K(EP7K9&6eK2YJ60Z94YVXudH$tey+i=CU_)cz-^iff0iWn
z0lsO$Yjb=gGOc_g$$rK+9y9y1H|PJE*dIurP@n4U#Eq54k(V!G73posNg^m?B;l&K
z8ftE?4dGqs*!dqe`@hN`r2&14(ZKz)*jGo=eT`#haSrs|mL+-9Th2EYyVR#Iph|w9
zOVckQyQFA7z?V0WM<6%l%Bqh4g!C#;gB?qX%|ojX>7r6|noBTw+y_uw)u#U!KrA|i
zXWFkt`!(731&^=lyLMYsHdVE|xvUT?zh<lY+<g3~q%Lkb@^@rWK4;(UVj{)zXGa$P
zS?fS<|Bkz7-SWJx{`OUi`bgwp@Q_^mv~k7UfspCTk9<M{;LFCGqY^*e?LKCpp!wND
zKUw9?9n5F#u4hy4U-{Z1`O2kBToh2)dZ!twM7cL0pD>M3#;;1aXks*Q#mV9#xR}U)
zI-h?3eb#Az{c^jk6}*MNxpZQDd~U(or<lPdmn8P3H+tzoS^6zr@ZMN8x1!$ZLpS7!
zQ=(LWC`>O$%1`m$kJ>sI#F?mgRwbyox)7uKiY)~p;zcZ7pS_-QB4iSzuVEacGTf8j
z7P<Rn@I{kt_+y*XLCx<TJ_$LeYgfiT|56m5-^3raHAM0Mw@X4)%vPmQ4x8**BD`FD
zk!(FWF-xL>;F0T2mE^J)RJ*OO71f*mICUqVY+8BS1vdNT=`j20=MIL9!wXGbXEc8i
zlh{EJkdL>q%<e7Ra`7;d<eF81DpFY<EO<3CSnCnU@})`poR+bgmrf@ep9!W5ST{cT
za%y6_qTN<!UwU1(>BlazIM?abzHQ|a<9&j`LW%4La5n1294W@i5YC{!t~*Mp8yy<%
zg0f@?C_XR7d<=KuM;7=tV`H+Kx^UY|@&x$yi1W$AFoN3Zw6s^)c}Y9gE;Py_>bf!b
z{zi{bw`<j;+=nE!m5aNy`<p&_U%TtWx-iQE;RsD)`Cqxwj>|gso>e!QQsu&DdF`1C
ze}@9TCy>t_`yS`*3ya%MSSNq!%-r?l<Aw?5$U)Wpa6a<T_u18*hZ$rxlW^`y-I{e(
znr2^Q&G_W1=9LQ_C5te+HB-)Qz@Vf;9{_%UKP^ZUfn_%fvJDF^i8`k*JSC;FB@*$v
z5~3Y}-YgVdRfp$Bz!1c9mCI|DLna@u-*W74Td%xBmrC7&AX~%&3sco_S|J~3qnm03
zp4pfK<Esz0jH7=zYcU^|Xomr%5dtmT?&G(y6+|<^C3&_wL?31-tv8^hI_kUk;A;p~
zA?1jn1)V|+f_xAG6>2bvDAs+|*AJjZN;M==EKAj1_6kT>+LU8n5pz+7icB8yS_N{i
z?**J4E9p|4PrA&~X^~a=t^(|Cl5B}`9|`N@sUjr%X;vaDlRm3P5Sfyf0B^5}QO2ld
zT&5SmxlYhC2?>q?;PGcA=}JA52Gb&(nZr?m<DuPFJ-MAyE`C|S&=(4)d3qR!2mSEp
za3a<rU|_NO80nyx#to%z5K-4(gxYP5MI)p#B=*}TfyLaLns7Ydk;zw(eG%`+nB%z?
zJbe<(3bf%J(Q^o+&34ryiytw|o&aJ2Xhl<wDVuZAf#E6qRfMf>L?HqkmLgeLu4Ig3
zC`jSlS@wZ-<pV8Q%PWEzeq0+Aw}FECn<-D5R_Ea4?ZJ5L@Zd++Q*$^pHkE4%NzQiz
z7m)-_ck>+<*EebKUV)s9{Xv<F;1;d2-%&qx(mxh!tj~`8Rdle3B*}8+HhYY{&sa9A
zT*N{idj-@b*yS0Ms?NdBcfD0ZWGC5rA1fpddxhmWKB*T7So4FIY*9X5`x)c5X0NAu
zbUBpA?m$Z<%qm9W=x^7^N_P$38xTMcVK7{rXcC5oy1>)qxRqa+!?+42m1A|{0_JT%
zj9r!;Q0{Q==G-f6m2efp*}855xofxZJ8%wnBEm<Sh=-3{G(ST|M05_9dgz$(XBtT?
zv#8H<jc9H+&|)@UNn1WW(Mj7)Z|<uE*<2yduXWz;atgjbIC+1Al-$K3rWUWj16SUR
zdUF>tEE|dGlO9{}daMb3<mubI+0UbtJpHSTdG8@r;LuwOx3_4zktnG)pSMi@1`AEj
zJJ<E1?X?z8u(?j@CFyKjK3l$mk#!Xnt3BawvX?-5<w9albG2nh8^nJ_bXnTTRLXF?
z1>5RZp53mFeE?KKID<%4Ocl+{DW8wNi~|FxmqWqm-I;y;<YC6KOD$<Vp{oVyR-|;G
z-@LZN6q7_<Jgv(lKS%vIDfI&lmz1Q^G+)82MVSA>A<O*Pp%O)HeX8wG=QF8Zu+gp_
z;o0~*JCJN)^P2};a^MGMViO4RS$hZK&Cca&9i~xJ&#s1rziq4~2QHq@Xu)G2otsRy
zNmD^~f#QLU18H{F^-1UOE%S_@OR>sI?1Ar=hOC`g`;(X3bc^mcyz!ju#3!9`{TMg6
z>G<-K@8eTUU#GKp@FG5%^)La_>*+*Zo?qycmU5u@y#8aZa0Gu=pdT6xK_qnvcI$~E
zshU~5KlDB#8cKguC`EN_lfjIltiFK)GvEq+CWC8Et2DHDfRf7lpfB`scUYzF=TT%A
z58RkJ$|ZmFYj0+%iZ(h7+ydd!C!VENa0FS>aHPs-CMiIY<&f}3PoMRQ@9-3Q!WV6o
z?@n^Y|F<T%NC?&Dp0Q+P?tiYV`l*9KR0CmA7g45{7U}ZCoRb>kaCz0C&Mp4#ac>{I
zA=t5RQ7Ex=o;@dVjSXt_gAE^Ah>8ES{oIP>@8;CZmtIGo(oA{b<2=7r`y@;!E)ZLc
zrJStFM!0>!%ePk<&LF)3%v%pkR(qvq`0hYlT)BgNV<wv_nZU4+SA*Ai->t6Pzr52<
zPJ=l0;yj3?L~Z2&h;59X`Y;)|4q+7UXKnVJdeS4By&xvbLYUnRpCqf?#N2NtHWrh8
zJ4+;ZbfIID*E+K=%;)0|BtALu5_B<*9W*7~-*=>WbN^a$H`I=2$!j`xVze`7FY%c@
zI<GXf;!wetvE6Z)(s*g3K4$SuL6P#QR(tJCmgpKk5r#LXX>kLzC-v1iad^uWc<v2j
zGkg0z4<DcA-28g~a3Ok`isWk=CgOys4!xm%rV=>ykBY6zXk!n`B+nW&QUp<i&(YZ+
zD$Sk14TN5@VVYOGIosI_F@epk%L&bF4=oG3_oUB+N>_PRsi;ZZ#t6$}J`7CQL8fNJ
zT7Fbl2{5A^)d9=4tTBhetkqM$h=479luQt0ET%bo3s+*xh%N63w<~;r1jDXA&l{QZ
zcAuapyvn(s*(}%N3^XL>pranvpkX0qENK<X!nNy+wK~YuRhX=y0L6uD#{PblZQ=Ka
zvg)T8#t11+17)jPKg%ywvUqF(=lt07bEfNbD8M6d<@HsAaYkASfxVZM@PmP!H}B!Q
z;6MiX(xke|MO@NHk700S!UUG`YTFNLn>p#|ZW|hD6+N0S>0OB<XNCFpw)qObyNN)<
z?mo{43&Tutf}c;GM<`#_!x-Ys{$v@vFYD;&G|f8vq9PlxApXK+p&d!%7!v3gyh5A-
zZKmWB_LWnWynU>lEjp19BM%AeE+JA@i1149MXVfMK<1I~jQF+?!S(E+ii;v8&?(SY
z!%in5mOh?>u{u2d2||Tgg^Vxir)?#*C9oh~ITG1|Y!^@k9mE&GW_AhMkIG^n8v0R#
z?c2y%2|p7!7SRViin$7zuBdfAe`pb8d&qKLvBZO;NG{n`Ak+6V0LR3TuSz;&7UaXg
zkIqZJ-Qp;CH+zoYwm@D;C6KPi(n~PAo(;z(-0HE_8vvEn(`V>th1seSj~sM6Xt}q6
zkFJ6JNJX|SWS`?Y?g69;EQEuRz0l{iyVa2|`DEpbLMco7d8daU)5a;&mcR)xa&<aN
zGGw|f)HX*v7(UY)n3i__qBzVFeJwF5orA!M;4aH2w3llyOoQBlO}=@M{7$rbD}SI{
z2q41Ww&U5f<sw`7;raKuwgjCPi#EM-;tI<g+<7qj!i>tXhBQ4`q>tCD5$CLWTe>`5
zb}x0;%0IPd)CJFa?Y#M_3JL$S>4I$@hpTLrC1d(?AtT(LE%Zg+#nPXg7v3MXoO{`3
zDvz!BDt9c!s2Oy=d3iSZJ1;0=eI7!>)iM5RcaylT{U33(Q5DRp-PSAYCw0Z7^roQ1
zxTF*%btQl)0=rd--Fv;o>nCHq9a>u+yW6$(dZV=E?o!X(@v-&nt$(v-H<M6u;O9vM
zOW<c`U(aUU6C;^57*?NrE=jz~v3V%-Q(q5ZedS&e4S>}+4^o9?9y@y(r<&(dC9v^+
zYRpe?!g-A<>p)EY*S}@1c<myj9T$XA-jX|h*5&@GgUlJPw~dL9+FFo@V!N%l$7Ugk
zE!*>?X6Sxgm@ioX7zjRFhPe<qbD~yU-L9UfdUBwb83G(}p(gqn(JHD--W#7MOTNLN
z7>+%4Irn>*Ih54QD`k~&Tt`(?k|I0uuP(KDmHGz=6dA)~e{gt9J3ZM+R&|N$iMPJH
z;mO4s`22@n-qaT?3VBpwiiJ;Nu?V=fC``_>{sFCxJdzhveww*(W5NruFCZV)7l}M(
zAuK3s!ESwzwU2hjY_$3E#`wu^lhM&dSNgyCNF-&EpYPc!m;|!<+_Y<HU5@OBGN=33
z8Hu8_EZ|#6Yj;?pFr$Q)KP<Kf033Odh%=D~e*X)=1W2#2_P~Xw;*=rV>>eKf{i>ic
zl+-G{K-qO6RY#ookLTl6*Nl*cf=Q-UG1+f7^Q1&u_Sa|z=3?NE?g-<fAo8eyL<Dg>
z%chIeG5Zy4(AGlA3#v=To`Hn8FZeUq>qPn)e<=rGo>`bPy;pB9_lP!dIQ8pQl(XPs
z0f~6|_<Ih7<i1KMasTSzcx%bRXNs0$PtVwFP8ZKeRq<?xGdbJtU%AM%+YP@5&TR<<
z7E~o;t*NNPEA@2Z&CA9Lc{EkVwj8aLEZ*t5f^9`rd+q&jL=mb0&f2af^m@*1tF9`;
zI02Uzyv)vFdU2FRo?K*kIqRbl-I-90OcC!ePh?d-l@;{Tn?9gQ&c4tp>bT2Tf}SuX
zA`lC9J--)M0^*ii9He_-<$SI?xZcXx{F&FB35X;L>r9_5OpJfaxu?zV>9e1Q3rz9F
zT5h9l5&n9!SHyJ*sA+2sQDs;v+&h?ws$4gwa16|VVihd%Yc#D@9I^@5p>H7B7C8T9
zyOotAhOAaS>ks3hFV|dBinEx3Q~{dAL;V;h;ej<Oh)a{!TS1V#E0jG%z8uF0oVtYE
z)g@8w%!rzfBk0K^{0C%G#X*wdIZs$8Q$)VRzMYTp0G{&SA0&-^z<2!yMpO}|=464b
z2wF7rDl}vqV`z5!!OEZfkPR0dOI=jUCc}yxDsd;vKp<HsBD!BasOwR2#4IRgAnA+A
z3n2(#N5;b;74l*%=_zcbLZgg$?E8cBu1gR|VVj6%o6+n3ilF47-zeA(hH<xw!`l2P
zvt%KO%O;UaDh3deV%f>kmeCJsGq{1hh`E{mFnid^eU;iC{@c*1Tds@2a&dydJcz13
zVyQBWr3aBu1+2mKF6KWW%v=}0&yz&7e%E4s7h7+14~fGWCEgdmP&*-G*(D%Qs+kmx
zcIffDld|V-Ytrhy+)OB)o;_GHuYwUX5gcZl1ww#`#jSt|65+;^5M8m~?NttSa-9ml
zWqPb3Y`OQadG5p9!>dB)(jUv4!@fj4&q&6sjyI>4D&*5~dzftkqIr9Fwf%)vwno}b
zvWN~)N&JZ{2Iozq>`D|_M53uYa~;h6A>f_f<t?4*-XVV431{JT9E`ea+QScLSuWhF
zTAoc_QzE`#gbU|EeLcrPPyf56JM6?+w5KtP5h#*90k%hI7b<_BJoOqIE2}_R3^8)Z
z&;N6$TAaG1Gv=*)v#ms*LpN_!#l6VT@Y#m5&Mz)z!c=mQ<%=Istai)J&1Prqvxg8!
zzDwItd=bRn^b@3~*BN_B)}FgQ#7lm6%GclNY*ltgen0ks)n3`pBu&408PdPhR+v)I
zGNiz~x5#D`89Q-fL6+BDNfkc5QV=LDbdQse`vS=ZDNOCJaej|vM^TS7p5>Qa;-bfE
zb#C>si|N~#p#|a!QE@muZTV}?=Ctl>Vfj}lvZMd=0t;{X7RnN8D>)bdNG8lQv#7Yu
ze20Pd$LEx1we#@Ulb2fK>KoluyYXt4rcWS}Zym^1CDOwjE|1N4{5JEy`&-=T^Dkc(
zk34Nvis`^a9I8y4&0cIMV&e6mn|*cMRS<4(n1=)TDmf<$arK~%N_|tMWA%LYv1osE
z!9f69Ve#Obk~UEW1;E37;<k}^jeshq^C0<xXEiOIsufwYS55M5M%31Tw_=M~!oDx~
zSWc>g?6$65`KF`=dAN|Paz6E&Bg&d;2~2_QEtMc9M0D|rW#60I^ex|O2mkIPNtn8Y
z$*XV7&*M7)3iIvMXUHi`d~4nXFSWH!q?1nCt1iwH_UWw{e>cfu@z4CXLRG5>${s?$
zWg2X_@_V>x?lt7rr4vhI4DhXW``z``SyX+UaE2smJ23CdLu1Px#Qxx_<g6~iO8(mm
zS2BTpj3Gf?XBUb~vu>@|#;LcT-ICVrk*M7pYEfk4fN<&`kntO$#^I}uxEtHPPbI6*
zI+jZCM`I^3e*bicmrH{2m4`82oyOUPY?=c1*ZZ;bL8SfkK_oz}VkcjV2Kz%`3}z?}
zF)4S|NIUsNHK`|98otJQaA(G27yN3{!Suzg)vJ{bM{Geck*PZn%I4<}b?n-#Q)E7S
zW%v*?;oH}!g*xHf2dWEUAZIb^zEHI_oQc{N`I+85jB{ACuCq;>Y;_$xDW*f3CiK!>
z#@-ioT?HO=2qu;>6PaFQknRZ`c70NhcacOISp{b+v8^@Oh=V7JP9}h=nQ{&_g)@gk
zms!G)Zf5Uo|BGx7fOQ=g7x<)&p{`qT3#b@VW2Y)RbqBJ59-ge%7*GJ%xhjW#g}`BX
z(jLe^QSHDe<|1(->j9`C1TsM1cf=xQ>gBy&<a=8@D<tBz3#~2_=sI&CePl~Hif^fv
ziaVBT=<++xJXR6(MS^P(co8u9XEiur<D$qKN}?Z^{iT&0=@CQi#pC1@YXs4)PNQB<
zh}Q;f(d=V`du4$1$PbUmv%`Y38yWT!tXvAmyN`LTp|bQMAvmG0mjQ6|r*K4*dTkXK
z_81Ncu*0tcUdXCwx`<t$%*A%a_aSpP9?lJ}4>Qmj<E--AqZM~i3t!fAmI98ANL2g~
zLKj+CRHH+`_`9BaJ!g*)VJ|C^hJd!79<8i9%oe2_B7M+%{lVg%`IOyMaorqZTCy!h
zkLwOfw@sX7e3z@#l9?KAYu;fhlV*-(Up-@P-$A)$I{&R@7omOA5}ZX+azCobB5X+p
zr#J8Jt3CF4%<SV=dBsu~NVSc?%N6*|$x?%_o^G*=s507f^;yzbAww;KK97B@l3E;@
zx6zacav(_iEcx~4v>j{Uz@XjkeTf6KF~>whpQ>>==+(DM4FE}b0I>_9;6sjMLX{hb
ze3B<I{Ji-zPyr$%L{SCexdmR<dZ^mM?zH*snc3-$`%f6-J2y_FKf=LKa96U#Tn^qp
zX8K_D_F$j6g2N#|a@t!<MBBWT+kcX5B8<%>Y5TW`ayS^(w<EK%p>Duj^K|YJ%7x`c
z_657E>a{??51#x;_cn|NlEq~C&v~=VS$nb=SqSdR=*d14=f`U6P!FFhe-Go?NX(Nx
zvzVt>k7Ry+&XXo(+|6VWR>fEsZZW<V$xLrkr#GIUtuMd7unzZ>8fvSHRCo0TlRD5T
zx|UGe_k6g@r<?3{I#sfEC&|O#zl!mXv%f=u2)!tIg>@ZWG=dUPnYBH+kZ|KS?d7Fd
zoh+)IfnWX`Ef)_7hu{9Scqjzi5Wrq;;x~^6X&Z~$)dQxFE}{9|ZJk9NUdeV7DSzlU
z7ueFJdH=h!T^L=SPW^Jjrf=i*wn%b_5VMM600jAG{5oGIiz`(<{OFSw?)PVzeR8(2
zwqDKbCYvozTfiL$VL$#inJs<%GA`Mo?250X*@iAwh>BWZ0vBa=H;hBBTvf5$F(UUM
zV7e?4IGc2ODz2C)W{iq*(TkW(?Pd-Ik*(9pBqdnCaa^rCpn-D5u*;%H&99awewbXd
zuzoj%u2qcpzhWWNJI9ZI^_*->u}N%$K>F=OJTcDFNpbOerVS1@T3NgG;TuPsJ_(uj
z#I#8wV>j}p4NjY{CX?A@_Oq#Tq%d;yWgG;*B|(zsTjmF)Np?gNMSkmj4SVeVm&PFD
zoay$@eZ=e!Ct2)0)nqO67?`U*Z1$GP>K(=aVdvf(LYT!8Mt{sQ?up9FiF7o(wvkC~
zO;+&f?zUF#UG3tvzh^EM4EBA&%ePk<D$+hdUI%8AvMA$hvhv>FJjY%ZPu!MBuX{-N
zfrR1Y981_PF3}%-%5LkOMAOl|!CnH_A>q{#dLnb*V{04|CQ}FJ+5`$%hX5*3Ot#gq
zhr*pfA+lQ!W(~S>uVqU?Jc&GV8r!LRF>Vm<JfHYm>Mrm0Sx;N1?Idg6x-F9ZLENL)
zhr~Wz5r$uw@7Q-Jgu4#2uyKJ0J7xEWH`*d=lCCRTpM<eAD8$rK>N}luCTe2I)i3pP
zsI4*9?$K;7vI_nI)w3H#7x!H}gI0?ch7UNhHS<6;<{kWXknoD?9?dd3Vsxr}K>es3
zQJBl*DR>a>qiV)OXX1`-9BqPbMeE{G&90wfn=W+%tQOp1D2p_DXSNtv6pBH)A+{T2
zuV><vp9m$LlY~@l$8V~?^m6hGvUFT8wiIUs`ukpZ5PqE*$q28kOGLhUmy<rZ=CTSB
zO)V-81h+3mn_GBvNLX3lpRzxi^P0Y&;TXIMjR)ECnklXNDu}bni=vN+Hc3Us$z@oe
zBN-+aMCrAt9+OQ%vLSH<zOqXLUE%<Ve1Q;6_+e0EPt&E*-NRmwbH-eejE9{wl{(<I
z2R(Nc0oX=6?yUu^<SpNT2WGmy$`TlXOWNi_g~ItL?0Df@G6=`PT`!AEQl5&stg0Bc
z8a&UoA0(0Bc82SQubw_6uCfhnie5TkeBGcl9}Bpfm4Ju7;Hhocit!^nJ7g)$V|g)I
zS>PG?JwH%!`blD6#<KJ%AF-*!&r(|s$-yb_dGE34oGp@EmiR3jN6cW=8&0>TY&vop
z4F@y(g3qicU&RGPGbXJ>n6H3vF`?)rS@jM5`BNes1kVGiI+ab3+dYi#E+=F^C}**(
zE2H0Qr#;F%?8I(&ABs+rFSp}&cc~AF=~gVlY|JXikvf3lbG5w^gmS9vd5<AST_$C{
z5C~=%2+mrwBJ}*SO0IG$IbQ_QqW$!X6xXA8!m`#19nQ$CjzyIE-qBzXvo-JmhPqfY
z_#flwckSV7N$??wE-mRrsQZ4>cXH35=blV$MRo#($jvrBoV>cBqkV59RI7u#5{xf3
zGNvuCf7h=5XCRkR6R81>gwwhd<)<`}v8=qAB_(2r?>2>xQGQRrce_cv+V*^4)Y^L6
zH3_e#Og>A9P4c#RcBt-gQWOILwRQ5216dgfKdAI01iNJ+_Ue;%J(kk}aWP3-`Gs{7
zfT+;xXLmFCJkcu5y$h~73g<eR({l(=9h|d2;D&-@%@FAi*?n2dO)t%#@XPj}bC&Kw
za|t-<KWfrpB3xweN><YrJBg^RllGBuZXqGAPq3YO@QWNB?VO!BlyTVWhp9JJHNPLX
ztNqlDfL)@Fm^t>;dG+gqcW1L*pM9QTjazxx`C=b6{VnabhGp%2p>&|YFm!ApZ+7BF
zi?4*`dbbrBK7nprJne0@BwThQ-46=VT!U+ihPskT{6KikX8G!>DnIfqBuM$FY#;d3
zF!$Q|*DWP~aU;8Ds5C3(>q2_=*GTp>2XtRU<;&ljnr|S6`{+qpC%lDu@~Z3)f&f7#
z!k3jJ7XG*ja_pmwDU-C>@fQ~xtzW}e9n|WZsNsv#)Eyk+%pLiKf=yU>klMQO|CoL7
z^&=zxcE%_dZnD<7XBD}!??taNQvF#QZ-kD+G6=%`bXVfXiIU`c(2c5mhlJfj53oql
zoD+?rdh5FnvAJwP?x<L5KU5y$cP6vlZO>Hv#?IHvf+Cx1IpOjDjvN%*FmPOihlzc<
zUt4xJvW~|luWCu0dC@!MUhye!2-}C}M%L1cXSf{}MDo+GVD$nEyRC=Rwgy7`(+H2a
z@{R9IS-CV81LVh6?FkOc*@Ne;p}dUPSX5i%!Gc>E<o{(?ARSk9K6N1Le3W58yRAM<
z*x0qlZRuDE$p@Qpx78dTQD$&fcv6u327>=RMt(Tcx6K&1cZ11uDt>qKI};bX-5Tw$
z5mz<H<L%Yzw=Ms|w2hpuJa*I=`pB!IM!9s5T6~VJz}!G^5RNJK(ULK-t1W**Qz$Ns
z?jJ#79qPuH+jo>YGZbNxN18|Vq*W!=bAajj#!#e8!i`DEDg4OlvA4lN;z?V>(d;}n
zT422NV3zB9?6Nw;Va_jvcd~xClxDU$*39f{j)QfF^TesA{^D7aQuPHsniyi<bshUZ
z|AEc#APC#sFws3Av<<(PqmrAeygLZH3&obK+Hgnn*+O(_^bGubYy?qCxQ2n{n0ZG(
zMaF%v@LGgTh_V)CC7CT3O+3C26;sd$5W27&y0(3ueUVn=YU;rBDx4>ADkinHZJQp1
zQZ3e4)me^27#_@O?Qj}J{iC?TZxCpWMsA$6GU&I1Q&fY%??SL0Cxv8q@N^}jju~99
zn}HA|Ki@>;D$BtB<HedW0#1l6Xv>#{6h31*x|!5R!?(Qmw)s^HRvqku$VI~G=@R)O
zu&p#IkLX(&9%0YOI;AQAgp5PNr6KY`fMi0XDfk?u>Tjsi$#i7m7*R06sjw_vCCFrU
zi<4kQKqOVNc)7K+0%NBFAQQd6eY8Z38ke`j5R7dPu+7EEOqk4J+|!wav?_#cBs(3R
ztU>6ka9EU&$U;#4Oc~wqAV~1Unn5)Oj%=b1NE#!|J?AI{ZnDX#souP|G%O64Y(}!x
zSJgX#xD-3!7+Oh!jz0@ZR*78Agaq3>_%#rYAC=6Zi3I~s*c3LSO|E_5A^bSHkpv!5
z=XBM97JGv{_#uIM%y}j0OgS(@E7@g_5jmR{9k2+AbJ4*yniR7aowTM{1R@cA3@FEb
z@DQFA16VSCj$aKCpR&G1X97OXCAxllJWopdBV2+%jG0d|u|mwDih0C$J*bT-4$LeV
z;AN<gmw5*C_BvUi2SH4h1V<dP2PKOEC_^31l_Z?G&`rdv8&t;(cG7$0O$kFn2%pSW
z@{1Udd&3g10}`BAsLQ#t+bdGKqzn&Tl1(Dx#RN16gUSMCrb;&RMzRY!A}N8WvxSGW
ztvXI@8jC9u=)_qRCQnPfoPz+))MBc*AkO*%93y)DrJ2nZn>+i;KEf?)%PbO-v}%F#
zc!>?ZV`k2XE3whq!>7sFG3COChFQB5-4-UOof*l-@ObS9TgfKb5hUcvRh_K5jTJjU
zXz@cL%5I(E5y-B#lmiV#nxJQ7w~8cXA@F=thdBVmwmRNp`~q<`C+!{up@{S3eDnE9
z%YC3UF+dY1bxhttFC5HJfmnkYr7kUlEz@=iNm0jEio{u)TqI)th)80V$~gVPxeu_e
z-9V!(B4==k{I@|{F7Z_GEBOroAN@<26bgI+Vg{i8QLMl=4~-;VSS21rx()N)CEHSj
zb+U>f$lc`UWD)dusGQ%WNl_}I9_(5ZYCd{IJ<ckOgu6HRGrYDXc!qBmv6HhdK0aNS
zPcLWJ5xoW(Sx<0kA62yo0m}?O=Mc4`)3m^QEXMpO)*nVyFrZW%T{Bt-89oxkbYtv^
zl8vBlxnjpvV_VLWdR?0;iXG;eC9#8`c5b6fNpGoJbNYQ`58YZ8L-shE!zotk-1gNH
zkq{f;qPb-#CqscmxeI98!XUI_Nl57_G{6po5(Xy`V@G8)f@3Z=!IXYUV`bU(Xvu?K
zhzQ559eW`#h&s-nuq+cnNGV&*bp}F7=F#yKd#1Apic5kCn!Snf4ijq*?740txn1RJ
ziHV1tej0a1Ag4&+ZJ6^yXSGvHvI)Wk1y`C;=&F)IWhIx-0!PrYwlEyjPp6pll)B71
z<tvIU7PnRsrdW(okeKcsih;Dqn9{>6J7O?E*@;#Ca`HI{3UztPnBsE$qQlElfx51i
z%`S!7J={Y)L{QhNsDVH-F52Xf2cuaJCZbIoKTaDKS0oFaEW<#kiK;v|Y_)bfCF@~f
zOF31)K=lI;kO&j1PSyA0E_Bcejjo|8H4IEwM5Mqf(SjVy{Ep~K84`(}iQ{oC$(E!k
z(ac2ic*VhF-nKRH?P@&;@B593TdF|20kg0w;BKD%xaodJwC@a;_%lepD+HO}0qPLi
z!u6!cO*+2kI5U7~&xD|Oyp<!-i_<JMNnFqIv8+`=`=Co<4Nc+5uvZkZsj77HctE$0
zet+v7*6!2pi$&r~t{IEla=sXsfR&SCto}MC_uvUOoLP`X5V<@wtsUYYhm9{$()a8v
z2hmj(SGNBJXtO;S{sL)j?v})E5pN!<v2T~0srwbMO+n=-$7x4*A<`CGCamyDxQ>mS
zKvh17aQPIMJ#^ko);{dH|0QQhElHN^81{c`UJj2R4yoy+-bO6L%wD|WI9$k1dTjo2
zEsvC5NKEVV8VfCK{!=v1^?Pm1PjWZGE2su7PDeO|=kOi~o2*MA9A~Gl$cpkpi^Wy?
zJh3mLB0n6MDPE>LisWs1u)kWPRL)Pq1ItOq_{RXC^F4Q-TNJwaYV~C}Hj?qY^BG7H
z=8j@K<nbQ}g}wr8aCRn$ow&zx_KO^w9o^D8lW-d*9uiAHvG*|MH!pAr9ST*oaHr=3
z8#!JF0pt60;jy<mb#*?pF3{G_anpD2?Z~sj90)#puL3EmAs`YSe;H~Ov2UJ!3Gs$<
z{2vurJY0D6#XgE>iI|e~6{$V)OcDZ)@Xc2&6z&9x%(DplrGI2OZ`Kv<^jM%AhJc@G
zI#o@-{`7&&zEV}5@~f#G{q;*%t@yWzmApJ?o|po8D^C6$mX!m})OK56zRZ&360`r8
zmqPr*s9nEO6s`M?n*GZBB%g4*-p75cL=sThdVb6I-ikRGGMk}x#}X8=lIubpmD7%j
z&gcyVK_>=vP*K;e^h$-S1)VHCb@U$V=mg_d;j4@l^R$eZgBlaqzSE5-!+~OtUkr@`
z+hh-uZz<n<LB)7jX)>8%hlga#wAv#i*-g5VCPQBFSBETg&Ue}Pe@|?dfUa?tF6tf#
z4+XYf;;j0PaGVwVD`Qq1;T~GK%GvrqHq>!u``3J#wNR1`zv~%)pKfU7!IEpAOTy}-
z_p&I>aWwbv_wbq5buJR3Zj^3D*L~H@^Ni)<c;<hu)wjXmlHZ-B0YNyA=(m)Dt&l;x
z&Lh<sy)Eoswvl*ZaFg<(<IDOtPUMlEJ~*fQSjM+J)FT3|>LIhn=p#o%LrAW(+4O;G
zjmG>pVs%K$%PFKAnEn3ASs=6*au-u;4klKKoF>^UEyIfXz4cdl7JRfWgb<5M<~+~A
zuoPE4Sn&87%Z3}7=KF$>KY1`Y;eXhh{gPt*sb-i`vTb=jD}!nuZd?STE}VuH-YMQ0
zbvjddGIDKd)g1DMigwF9`O?VY7Ge)uf-IDk{Xp-J`I_VX=xRTrbAg}3oz*xVLDnFX
z5hd_ynr!AU>jry5wgilqg_WSbz{2bUBpD=O{sD4yTeRe^j^bWD^^4`r)2T5i{Ud=#
zff1sY!!;LUk!=`QhKR^Ul(y>&;BhO9vEY*yw!kfFXhfo}z~3pR<OL)@o!H`%cqGOk
z44_DMf)f1S0Bse}F46BEbxl}R0@_>M<~&2QLuYGDDp<iUt0~iuVNq@(6d|#-o5{Fu
z<37cYsyrAH;$SM8Zd`;&W|}@<hzu<8T4RXnw|%vaM6Dnv5t|xEzEI__r_O2(%;z>W
zDn?w(T(^eQq4s{nGGfOkS?H%}*}Wvvs-%!NeUi9X+pLp~1n&JKHGWELJ}EJywIz#y
zV^kgvw_vVoEmYvH>-uh=9R<9G>{AY*C;FjdyA7FEIn$~G(B)MxGRrPc&#y9M34hRa
za8A~Ph*dz(eIek>%Mp4Ad|Y;rEs#uL4BN(i{x>v(M16c_uTlbquQ<zWE#1_PU~pOh
z+aF?(Y9i@~i~2It3y{WKcsmZJP;RN56J8naV8oCiQ6B-^VT)?-S)ghWF6d;WZ(L(z
zICeld6Sae)>l{p&ax`yX9=p-;3_W{B16BNFD<U2Cm>%QET&#iJ)MNa;ItiJ5&}?-<
zmQ2PlK+hh$2zf_T=kf*1)q}Q)WuxoZdLrOiM%0a(kL>f3IMpCYy47)ucBk#8(1-Dd
zTD412trAI$VAlLbEJR6w4cS{&&0>w_ajFWT04;0jdV*0<`I18F_jnz$B6~h&5_X|>
zTR3J*7l%KK<Hi<pA6tf+7&+&33xmodH-<=jU6RDsS|8!yoxua(Us&iSyow@{q1tgY
zFv<h>ZS2{Z`O0U1bB<(Py7|I5_bV8|Bq~86#n*=)Tw}IW2`LL7b7tSX#~R@Py>AHh
zL`KwVvk!6*B;1kM;cgW2*b6o*m4@o`z9R3ctq^BkD`;wNmD>6uukW5wv};**_b=D6
zEsy3-*5guJA6y9LFM%CR-<GeKpZmo4f+ttF`oPQXb|Cxwd)BgN+p-kVszET6?+^B=
z8!T}+hRJ8a8A46LLOe0J$zfDAo2b(8w3XLY^>DNE;WV#KqK)Q3KAzuZrAeWZlXCGx
z&sj2y<(Rw&fsQVIuJHqf8ks8}Ie^yTEu&bcQG5^nHlGXZzQ&j90+J)AERFYkjz5@X
z?aoa(ErlZRS$g#G1BEpip@)HHt+v|ZDW3<a)mBf)J07GEPp%e~+S(3{G<o=iORg2j
z&j~tgIJ4H55Dm$?C#1GM-pG>l)ASohdD)BoNtfNuNbp3G#e=b`>0bY7Z<Q0w-rz(S
zhp!+aCD(-*)h6!-M)7~8iyrVqzx6>hQWN91HLxQ|j*C*fC5=>RocvQxLe#I#6&`-$
z*BW)|bn)W5Oz$9ax8skbw;uY6wILq}G4}GSs4yg3{PdqkStO4g3gO79i;z<@JlMP@
z&!#0ACHvNQ`?w-v3-4RDH>@~~cx?7|IJbzTi{yy8Zl58Ky&#OTpdiA9YtAn0+*d`q
z_Tf>>ev#eckKJ*e)K;_aT_@p2?wOsjE%Rif$fD4H!xF9bOul`}W<SxQfYqZte%Kb4
z?0Dg3E~=J5gCdp8oGd^6lI6u{kz*gw6f$<?o+nEC4meGb(-9|88{OfzyYq%_-H@92
zjl&qenhoDzt$Z_aAb?XV#zz~`U%A_bL_>l`x!FXuOZ;yZ8=@GQe50k$Ct0-3A6(M4
zFsc2HL|t6lzS5?`FJN6qRm$HIumL37@&BGIJ%MAB*YN_lsx#$Oia(DzROYhG;X449
zY$<hB$Q4(jwt58!i^+;Dj;;Bqfd7(>I(t`>zV1*~+Va>$LiLu+`J_kVn6yi4jk5(e
zMg2YT>sFrr5SrT8(sJaMEBsU>+h&|N5Q55h5L7AbL$zsE?QQvyeW+@$(5n}8<g(XY
zNRh)!E`+Zr!!%VhbB?$ph`h_LU#@YEDphqS6=HAG6T7RbC2b-JxMLS&zm6q(%vDvs
zN}n-R6kFixyp3&euAYplT09R3W*w0`8P)ETvhS3mRL$9YSs55OL1alAJK(FCa4T*m
zg+!R_j_9M$!9rctm<kiku7vtfyITkFKOS;BYQ)C0WA_MlVw0M#gsr0KqxT$U-f&VZ
zoiN_0y+8<^Bz`3v@3bn1$L>jv1+Of!98_uY(LTUX2&Zc`JcM(4ZH^O;PLGD00LLH~
zx9mythy`2KlEApl(?S*r;MW~y@hC=S!B1Xa&%tr;3z~hvw;)t3R}LQ^8M$(@Wz8V%
zFk~yd#^*9yFG2daphtVWT`nL`(CDIVY8-mM+hR;X74VVfyEdFcHevS~LlDEl0))Ox
zTr?_MuQTCzjgi}^@i;vNYtck3Gpb`$1}Zd>v^a`6pwh*F(O8#B<<=b>F?KzW`OHU?
zPC|+<;OdFq;jpN-w(Pao98REZ7rR>69~hjnCpCuQ5Q`%7C0skj0)#-ME0t1Z^aCl&
zlE?roApp&Z#f_`aFOXR3y^yd9E{nUZ%mN~{@LLeJtb5t^AaQ;4j(r8V>B9`PDpOPl
zeomGOqL?@x;d`746XZE3LumCm@?VrACfOqfF$jVPVyGzSNZwR*c$A5=KEN@H_Emv`
z6enc|(?yy)qXVp{w@hc|stgF{IpEL@?IIVrJeIb63rHD5sRh-hu5hT);gtCjNnMLW
zl{pmL+9YUuj5OQIh>#J&a5LeWdfS7bU05E6p);17yS}?U9~dp9vSs|dm6ugx&S&N1
zT5JE7dhMocBx=dJ28K)=MjdILyZj&6e{F}SnL-72x$M1B#$lJdDXwjh+vYrlSILBA
z5BeDDs=R4`a?tYj4^`)ox57L_M-ceZgMTN|Jbh?QKAu3!@Zrev>iQP#KDJGETk&>w
z>icZ2tF~UB&RCmWzL*o#))9NU@nA>ur|>Dh<m$7k@@cnqEaZXV0Y%`>b2lbV{m5b`
z+=uKo4vkuPnX@z1)>D@Z--E%}E}$w`{=}OdDg)icE(B+y5_0%NQf-3J7_+$Z1zFq@
zqe6z?Ij24xwuz!6$#c2M?V9B0@g|VRE_POYveAzFdLO=iJ|?TGyg$$g;y&Ne7dvG-
z*UqiriBF+op_AHWAJ%3y(nGQ_+1BSSLnUXbKKo;^{M1M=SkLqFqm|Z^9veb<l23QH
zH9UPqR(93ae^1_igU+h;rG}NCP3WP%)3A~BQi}5rti4i<R7c`lU%rX<4O>&?YjW+j
zPW&}nuf=QV!r5)Lo3Hn6wu-d|0BaTV=D+f`fOP<fvnX7iLA11y8bXX}^Yb4u`&U0=
z)1n**9i3(VimeAxQk3bjr{SDM5ftBeXGHlEynsj=3&)ldt@N|-dN)fddXY@!GN&A%
zwkDqE5`ml+T!q{hI{2a#yQmbi@R1*TY9;2RsyAe9{>^Er6_Gg-iSd2>uV<?QY!*eB
zct)p(h~xG<isa;%&#_5%TRn*V0UZ;y)lEs{Y@v=7KlUo`usg21aOXCx{eky6JNg7e
zW$T$naDRDDnq7D^-<{k<CU6#}zGc}uHQKVxjNR5(GiUms<xd_~?Q2ZfRTov0j6jqz
zH;yp&=O2`F0Ki!ysdXzuEaN(iWWvHM3n9zn3*$9%h{ttRw_Bh;uBX3Gr3FxYz0%1h
ze=xeIl5elX_;uUMRP2a*`>+0QV-+fL0u3(G7@Z6T3Y22{7p@ev-%k{Kl`AdGeVS=Y
z?4j?{^cp*AYxVw`aRR|^9GS&w?bh2czew`MCAS7)2EtM$CA06O<{qcQ0v@ij#RXLJ
zAI0@Cp_ciy&NHm*7~)v_R%8t9Rk@einkka-PPjesOMYVWL%gc;HQsDy{qT&oRM^S$
zeK$!(ycZOb_I}{-T<S0G{fOlk>Inl@B)AcHqIkq)U~>W|S;HCYlTNwAW?G?DdD`Yh
zVI{>fA8kV#NvL|Bn7kYUFN4Hr0u+`{x)Q}l98nIMi-vecStJ7266Y@3hcs4|2octS
z(nrZtl@y8;4I|E$vKc5cm)N;H#hLdw;w6^O5y9nTe~qdvNN=yhSI+;<CiAl3k6J#f
zia!`syI@qjQY`CT?KB2llOL0OdE!w<qF5bO$DO5hu#glJ4$MXyBNFl4AL?WwayBp0
zreDBRyuBEbvYw|1iEa^W`K;(Ur^?`#LAE!kzm|D#EnJS@{!lTOiiiz{4d0`#ZG1X8
z-Vo$yqp2H--9#&owK<Zqpyt@>2^1hr)+l-t+rW58gWvUh8Ot*w7yuP#yAzQ`1QeTG
z7WJ&%$#!5v?ataNJwO!#xjWha2_58YTQ;Cp*`P{mQVpaW60Tu{K$5S#2SN}9b?}s)
z%M8^Oa2!r4BePh>u^gpCm;Bh%lq4C4uwNx{9W#bLg@q&)-$Ov+#9qnT2PycNKpn~x
z1M`T|MYp=EthA{(I>dSt66dNG4S|SwX?)^#p6R2R`9ok*!t4M}A*}5{?djY*2g`&B
z!-%zto1FDSn8Q_v_L647Ppodp<0^hVh+k`*#W@EvzMCE2^WWD}C+nC(DusTSM`C%W
z9~14AWvG$8=jg3q>ZrnsINTq6^v>IQaB8eN^$O=Lv{mIGvVs<6>V!Qy+bGx~h&%!#
zR8DgtzkuUc^PbrOMk2(PX2cTk*ajhNbMEHw71HhIrx`_N;R52P0J2RQ&mag8j6X2y
z;0CyhUwN=%mibJS<mSt0k#}|XV|650fRY+?IJaY(vYh6afUx%2wA5o~NeQ<N0xtLq
zjm`Jg>r18HKn&*4@RKiIY1Id`6{b8+A}_@91i$cVOZ+>9PV6n~dj1hVHXE!wD%Sv@
z#Ktx?8xY*`qg*{fK><_Or%rRk(EQUZEuxNk{vnP#pXWOEj5K<)m9oTK9$nANpHF9D
zD9y?v<~SrA>^^)pUeBWAbw#P`Zv?SvAe3NXPVa9F0F*g}2s_9sLF#~J)E}>Y*CN+X
z9x}g!Y*%N!+e#a`yWqg)@kmrFz9C$OlHT3+)G5`Vq+%kdtt@9<n%LyiSqNY!M{cxO
zi5-rCApTYxXN|_nfAi+Kv9>Qh<y_~ZymWE&>^yd=QlrPB{`eKEc3WpJORW>`$?f&y
z6SnlOBEUx$Ud2Q*L|G0<xVzh08V6UicOZE)|L-p|_n#Yiaq^oKklo0%d-4jiXD&$W
zf$y-uAe!4<!6D&kTRD1`Uz_^>Qd>Go4d9S)vHThYg4&vW=(Cn|g&EHVEGgjXwbiI0
z`#!Lt{KqxeAgah$-7lzjcr9|U<8KUun~XvWVrAed?UdctYJ#ABYwfn)QyyTlhyK`q
zNI0%pcn3MH#wIv39wh#07+a*&qlY~AgSgweavReUVsFnrK}3L(<?9@qD<m7>Cvza9
zZmhg{e)ebI;o6{weHpMnIKDY!DAXy3gcpSv2;rK`VlV3a)8|qt&&!qx()rBaH+$m`
zSfNA0UU4`X=Z^Zh+&7k96FwM)ZpHtwgd1kk#^lLlveSZPwzP`RALdKB);MHi_oY#0
zL4hSqC(DnYWto>{07SX>a)~In!)cs%UZPlsfMcSOng|aRh>bSBQFRz?J?MzLie=S9
zi!SzvN(6}2QSWceauCKv)KErDme}p|k6YAElebsly2*0vCB~<0?to)-AKW5+FQ$t-
zCf;~|qTr~T-$8kXlNxHbr^~`;>37&4U8|%Q-pZw4cTZ;>|HJuIm4DGJvL~?N^J10O
zDEEov3ysodBqyCHWw$jy@k=f{J#KCL8pw^rJTfb>_QA=s7yDd$SV=V5!>fy)r#UYv
z?I9qFEo>un3tP^@(PoukppUB{ikl9hT5c3hK8ci_A*&MPB<pwxn9*`L4NL5{h*nm9
zRR+AAfS1viC!gmcN=eyucX^x#vmXRJyCbXUR%Jv8>v||7b6&Pk=Qf?gv7mHF3Gk7H
zbc`<@9%e#C2u5PyN=POzWHWvZhZCj?aX#6{co)C@8MZrjalyB5?}FbC<+nVW-sE!i
zPN$O(S;}Y0b-?b)aTfm^E`jIg7KM9W;1eg=O$TR8hnvA4lT$@Xol&`y5C*><EX&r0
zk)}v0@~I+g+FXaZEOP_-?+=<Hr5?lbkcDwulU2}GHbcVXqKY>nVb4xFGUh5If)IqR
zDms0{(n835Jh*n-GCQx~R8RYW4}b*M=ibX&$9<-ECD&$%gVMkX(hDEhCsw7b0D*aI
z#1%q?sm!<V&>W8}0ZnfYS);1EvC|2{3PN%+D)E(TZ?hA<sDtjPx!#<jg@o>5?vp8f
zQ6$JSGUw&0Ak#r`&8IR>>k8Vd7?t3odw*liI$Zt3K2g@`5~jg9!V@KsDd(y;g23-)
zS)2@|p=L80?{sl032z7_;bp%{FhUWH2mxX_LPZ&O(KXn3yh~DX(sfnOh5LE>?YRA2
zH5U*ePSe;0X1A!xrzm(xtjp%21EXibKHo(S^_-!ZNEkJ2RmUS>q6=QO!8}Rl#pC1=
zEpg!?`7tz2(-97Y0Ov6}OoyWjR42eilM!=^i7jkw&=r9xiaFA!)h3DhDR%XWYt3F1
z{RzFrGIccZlIZ?$D2gDQNz@fh`I1HS$20wR#VDTa(+#*dCl87tLrsjpd}f@}!+N)=
z;t_pT`eTuuMiV=Aw#`ks7ve3^pVp%bZ@sK*+xr>h#fo|Lsp)T1soBdFF8rjo@l8C+
zo2&B{Qd@b+6vj?F5deqgEz_dZle2N4%r%EWZ+6jhUn4i4+OMs;<~MnrD!+J984jBF
zef^-@z%Kn0U0?*GB!LKJ^+?L&P;VYW80Vx@e#RDx6Li}4VP~rZ8`(HyO?Oq|QCpYO
z&RAWr<-vfkGS@AeDz073^_<!fnW;Qo^`QPD7OIIWk5V;;-)$v02T0T2=lPa4HCrSG
zZvSNGaJ|LX9oLAx(r434^EIv{b>+%GEv)?)jZtPwmK0BO&1VdR@sDq1YjPMM_I!MW
zJ;aM|=@5G*#t&bgqe-0`UqFmQW%NKd4wEQbLGh|bn_WCu*p(0G_DQ}~U*3Fp$^PYE
z%5N})=F4eh&t+DAG^;c^!uZ9@Jj!sbHGaB@zF+UeaTn3KX@KM^G*&okxNAAu`uZcD
zPbYqQf%BKYWp3g%RMCa|on^m}uAsJB_OB^c4Oo0elL6vdRi?pk3q&a;xFt#wjKL(&
z%_UAvD;iM@gaE~nPxeK1?4DP~K&(4N6>J69`uSHC`nHCJ<1eoI=6QBoo2ZMc-Rdyw
z;X!3=H$3|SqlWDdL6w1K5?3|O{tPvU*a1fj{`>hDPN$@HvHKgG(DFl4=J_qJ-WvSW
zr_wCE^M>3${dbnNKX$+_J9?>Bg$ID-^C(}hW5d|_XAg3kE(R!E_+Cpta8_2Vf78kZ
z;hc<@p93j&kKO;5S|9;Odh_?I-vyE*fkVQXD;FC#EBj8WemHS9%;Ves$aNu~A6*pX
z{vghjOFccmnlssI_>`g_7M39lf3cz%y$rLz5<ei-X!VjQ;5Ogpjc;pk?){wUh^Tg3
zznzY&vvNXh!B1>i_q360OeWbR(asMz$Fk)T)Q(>ser}p|J3Q$B1?_0|jI2Nt`bnI(
zKs%Ql%I%HZ%h&p^p+~W&MZN3isF_;&Gxp(YL8bPyNyt8@j{Jg|7`W;>p1v|VBx+i%
zm|<iBLf*OBS_E#VP3kggYaZ2Byv~Xwx70<zGHzZJmsFb>G3Z{#dDC3lMNhPsKlq8~
zQLHhV&}-SDDpS>(pmb6v0%xts#j5#t{V5ioSRTDaqOKvx0z8l88J*%50y7@P5TT)I
zh+<J8>;^^Fu~PJD3W@e3R0Vu5g5ARO;er~zc<jA2@2go}VXp!kb0}}gg5z3S5EJMj
z0v=k|j}45+Xyh0DDU0mPfdY!F7|)|^e`CEm45|18E}H!Y1->Qwevduv4bDJz<Fh8K
zCqSEQIi8-M_T79G#P>1*jun|i=B!zI#)3+kPIQW7vf-m$?!j;oB<y_6#Mo={cEd?l
zd_%*q><$eseyRjIm3Ckirn8ORNq1m%taqIOfC<1BqfOGoBi%?g;vxrqQxxs1VwMy`
zxLs;a>e5{KXE<`lc{=ht4XGu>=6RyhxR{r=>>b3WzIrIm904j>Vv%D9_(L=44%FVx
zs`5oOQ9Sg<r&c$JYDwGHk#f~VIOU?Cbyd)-yj?`V-*+8*J_#1^<h@}Juj^<^TR;rK
z;neR;&;aV-Ae$uye+T8^8&0b|2O^7S2I#{C+7ydn83B1m!)5|$N6-~vQ#RAak!4N4
zR^>{k(M!wyglHs?P9huN_;Co+>%q@l)(m=*tLP413Ux>tE~uzR_<r;L5b&O|Opm?5
zb5LwAzk&GaT__4z%_F;bx?Ko%qR7cm;4Mmq38^YgKd9R5#P$1IE8y+#C!-HAb(WX!
z_J-T&b~-%zt!MPeP&E7e9C3s=ti+f0Zte48@wjrO4C(bIB2Pz2=a*MKhRmoSRfICT
zHHNb#A@Q`00T9*JJnT(%`+51tlWJ(+o2cg_meC(Mn}*u@cJ)OK3MF(W2l(n^(BDWT
zW6xBhDzPHGA9t%^3w%A2<$7OY*04!l2SQACv{>GJo2}Z-3k!7sZ`Z9bTe{rIo$6bW
z@xG<#d)k%p8I9!;mvmkkmK)!K^^-ScssH7$<-3>7ku!JhO2@v*m3ybI=#iygzsb3_
zPLuq>Y?_}MVU$FTc5a1xQ{R$h>UO>THHC`WDuFDgdJFi;7v$&LANq-KpKb6yWPSEu
zB&e++Wrmran6UH0T(Oq)lG?-4$&*|Bk4nh9fMgy{o`<%6BdcM3UG*-s70Q$L<-FU<
z>y07He`dwSlfS(3h~k?P1G~qUuAR8}&a8wI^+S_<EF0wkmed|NxXeBp<LlG0A_Rl2
z>MMYd><b=W6g(Fim&|7ue%mr3fOTyE>fKi3AAY<Jkfszc$ySL}jkx`#%hQc7F!MQr
zu>AvLKKqpmmHGgH!u<;3KKHpSS%2#NowN$#{UROee>iW>PCiWDzWk=#7B@L|d0VS+
zFZj1HZ~lY#(^61d5y&}-*M~E1?@WaD*spRaObf<8cZ*iVYm(Qqa*#jEs~~s2zerYN
zA3m5f-*}6Q!VRMBWd=d0laTrzr`O1#1UDECNnjj(ooT+z67<In1vzk|?`^~S4__bE
z)*}4&D;^t{&bPUAleJM>XQ;H=$1qz!kxjK%+WPEq75rcjRp6K2fA#v5!y<?=d@ieY
z=_%vF39D?xyvZ^1hF}}dHI~btLS7gDraAWquMYOFIp8ecL69H+d(3a%H{mv0XL|)%
zCdBN6|CGA~&dRd&ADNyj-=3}=b<ZW1{Oxb$4?J-=F|SCQ?DF?lt;zQPIWlRlpQ{fE
z|JX%Q>QlVhE44LNacb`6_s0vthAIb$W_!7;GJ_zLw%{~#h-kUNa_aLCAnjDkgeNNf
zF@`wx;_MzSP4cAWv+zD&sjVz%7wCMMJ$;al>f7nsR_squ!`e;U`Y_q^0B_|xx5yPk
zxN&|is;#B2h@t^(dBcpMwpw_FpFj9}&L>MR49;H3OC58o+jNosAlvPm=jLh2r(Kx+
z-&6Z6ue^tBef{OZ{F?(`w`r2V`>0GTlBS#Eb#?-hkWM<zLtL@zKJC#5(qeNwaFjJw
z{|qzQy1r!|1DF3f4vrK{TWVlL?`F`4YgVN+`k`NxqrPq~D*D0TY7#}6QjB%r!WO71
z;?*3&j6j4{j#y%fh+eYPdG(b=7P?yjRfyrtI>{KjbJbQzh(UdS1Qm)zI!0Y%f&Ko=
z@Ltuo<j1OYlYZ)5?d0HMD!Y^C#ui0@cguX;3Rsb@y?A=>aloNIi%AbwIVdwM`b8+u
zI7m7NJ|L92vDnW<s(p<0qDA7alI|{a+AE+sSB&rCe+J4iQLo;02|6xX6_>SbZAPSt
zjK@vyHu%(E!+LB0S&T~#O}~|Yku5k3$MTsR10mED=!p;Xh}+n_xiCt4lA#`|Ff~MO
zWN-L9==nKj=;;9xZJk-u<$nf5-sTcF;m1Q28yP;uk>ER>`BhLFP(B(rgs^bfwNBDi
zh16R_juB^MwbI*jjxWdMTsZS;&#)vY9hQkb3oFv}8+B^^s4aU>3|pvuY+cUluG{r=
zNO2RzK&i*{I;eexj~NWG+rYb$J4N12U?Vx%wGMoS$?;%sZ!<d9*-<P`)5Z(;5Bm`H
z>4o%h?he92>OB*!{e#rLyn<brn5XLZR1(*qUL>GTK{eYf%Zhl)Rvs_AUwfo6&vf7{
zcEZuW;aAlVC8a!T23wJ=kO^%rcpeO3T32O^uD7Cu+Xv8u6xZHxWN)v*KAy7%k=M|p
zrE{(932fG|;AL?#y09z@l-h_L8hju?GBPxMB&>QD*i6x|x?Erx3>4nT?TKXz4eP{Q
z)<INY2{TO>SEje(5x$13+ncV{2v(|?7vqqRt3^a<*4}!w<OubITZp|tYHQ$cFL1ne
zD!;H7!5R3*<~@D5KO=rZGh2#U8vCJ{CI8UHF*fu6oY!$qGf%kv{q)!6FIo|AOFBJM
zDo}*1XlV6fFjPd$>FwFINDU&`4Y)T4hEE@Fv=TQ;cXyXd?Y0-$L;mBdgOfz$X}EZH
zs`<>UHBNtD%qgLY{6ncb(D`rKZ1W4?zH~+H;eRo(1Iri=&^N<X<m{%Rhy*8Q<Pkb?
zlXfi~yA|e3c3U&wd8LzAVXo;OYZb*{4TsM=-R#fv3bg}BRpq%BU(&<kcKGk*bf`35
zJjcqoaK{DfqC~eyE<a7R*1b7bK9x8xg7d$B2K~{qJbwwVJZ;u0P5-pt?tF%g&>_G%
zh}M7RoFshDPatj_un^)awWn92Bl05;lN1$c;AfKZ^<SR1b+$`w{cgfOelX7ub3S<(
zC>|q3@tkGh^nvPyRV3wKb%o_`I?pW?f4RXSGfpFV;%ff-dDfbGO_l7}<ZY{{t(Va}
zZ?!kl9p&v$r`g=Z>uoF^5_Viq8<}UfbzKTIByMy4z`QM7TP$x7-2ljwU;pKp%jF<S
z<x*zAROh#Zuszxz)3zZYmP*O;g4k-`ez{_?U%5M-<l~xowI6x|0}*Q{6Dni9+xquN
zL>jKu9|En)MdH6&u?+<=*`w!As0O9eF-Xwi^5pwJ`GJ@lWzA_*dX99q%J@~c1iR=D
zEj;#9*9KT_n!EWL_~7;8q2TD*NuIxN%+2#|YpgGXYCp^Z(^on5ng85``3F}mRo=oM
z-)`v>hgnI3BzZC0Vv*&Kot1^#k66}z>!@A%Z+M&ctB1MN=xb?pxqwI>|EX&&i)DNw
zv55v{5r|<RT=tP7PF1`pRg<f_94%6|tZ3`|OG5+77~KoY<>xRT_z}sFY16%SJ6f6>
z+r-^@j|WM-r6$dKw-w#EIyTJuVLUd>cpM>*+l{qj|A&&jlhLVUw~|~01X%=X*UC?d
zg$nq*ZP(g+7Fn>Lr0)G5m`)qxui>Hf_puCyW!v~aD1=LG#=g_EbL#-%9fv~NK9{`R
z4~92&s|%Gsp4j=Dx(`+I-S}x9V)>Q}d3o$&uE2Q{!r!<oyGif1+6l`lu5aM@8l1&X
zLi(BM&vP6n-O3N)_k<4Hy?c7%L6!@*AHfbkFE<BYBRZ(S$VTDTqOGbo{pmT;CAnuR
z&>^u6IeRcu1?su?vq)ZJjL|L<#ZH3ICABJm*$_ek5m`UzGPBYfHJ6$Iaov*pS?nj@
zZdV9~x-iNBa+|!WV52;;c_LHcD8V4Ve9qz|8!PI(2Op`UpV9{5LmOW((;-ejq!XY}
z=Tz5-kL|C15jdjuGSHdxnXYHMYw10;QSW-L;Vf)uKp4!6d{w48-AShASRKkC?h4}I
zFGmqoJN5JdSJxW{y>mr6q)80c?$TmGZ}N$d5mF>~2DmoYtAh>hF-%R|sggYw&LHnc
zxNGd*`!g+%cBNF+rl1)36qzf0Zf$mw$zY3sVJkBsZKp2AH5Ouh3vn{F5>d>kR5K(N
z3q-kGMq!3oW>>4pVBXjopo$Q9FHj~2N7ENtoKGo)=O0Zg<!RSgSmP0d-)J*~x(KQS
zZL%U%BF%=6qkBkkI2nTDy;Z8py_XrHhjv@rNSI!<hJX|hy1?<Pd$z4@V2R&_#5ovA
zs1M@DEnrk_1<N2f5K8uU16k;FNgGZJ3ua|37A)~_Ik#7DVOq8p%W_U(G8~e}#Hdvz
zjRw<k@)5AUf~P?Hzy()GDenDY#Kt*LuogwRCuJS$p8orK_{ukpS73>u7TH{LShA$<
zXcFrvJ9u_e@_5&<)V1vUbd|4HPnKTQtrXR#le%jh6-ij^CQ`ZM8k()*5Z={49z%kg
zrE}UjNI3$>k#<tCco{(I`zk37vI`kQ6iFwuX51ENYt#|f3)B-!r{WF)s_qQ}U)M}O
zzbmCC9d?~^JS=b})0n-45O;BD;3G{2J1X+uu7^rXLjy^_eSr6f$aVQ1$B|%4^VqLJ
zvvK~INF&6XK+xM-_UWyb*Y(`}NwUkE?<KO|r%=l(RCqa^)>5}0zst9`c3Y8P70=gb
z56fiIy@vZot^;=jf%`wHeJh$hO>YZK30AInd@{<ZqMLeT0)6EI%IV+04iHsx^Y?|Q
zw!$9pV|Z=OGiw}YP5zCxoIU%Zke2VF$=^o>hoJ``D&o7X?lpB8^NEqXOw!CLf&tL+
z+V0&A#1jfhYWIA9P-_|rCfIGYxwzYk=JMppbY4}Wc@??^r*(B)w7B>V<n};gCOL3k
z%8_6SVWqibn@`eVE6XG+J!mD>oc`G6@k$JX5|`!@j*qR_#qU|vW@4;}<4+O8(}yMu
z*N8MJl3if!Cniz^#hG2hY47#<IO$0qXILohgX_uR7sl}aKWFa)XIWL<`L1*Bxz(qt
zi|*4+0R?GcS5aVzs8>LzQPf>Ufh8fPz*dQ(xhNqFlQ^9O95hCE6@@7YV=4?Wos2WN
zkWOCvXAH^2d`QBZIUxBwlHrrVj59HLlh2fI9G)?Z({En%F-GJ2{`R@&R#kV^y_c-2
zyU+f!_FikR{deuX&ptxv3x40yMDdyjP`t~ZS7#c*zvIQ}()2;+ANbcH+=o|G$?Z%|
zbscM22(V$tf0~Mf*5mjh(9AJ5WEa1?H**i4$5mfww(B3eI18k<POkFx(MGij=Fi{f
z&s-^7yo;hDwY!<W<yX8!S=HVyXAxa(r+oD1;tcJFgfSGTob)bf%w*I>$rt*g?rN%N
z?En2WbF!cHF8KYB`SMZT&vw7pjHOQ9MqAb;P4&rQa0f%T4)QIi*W|t3mv?aFT>MB|
z&XhH$gj8Z8;$=@6&|4dpJ#i9(GxrB;--a@M%l_et)!w^r_L>*{QDXkvjbcRgg;(I+
ziF1mC_<rquh4=5FYjOnKb0xL<>0hqMno!Z>EqK_9`@oJEb2Qzroon7Z*7@&ykuPGU
z|0E}?z{*?xtPoh5ICT^usna2R@e&^o)%d@aD7y%uMm)y#+_inUCz{sgdfnYsoDjS6
z%AR+)CJdk;Bs-Sa?HD!CAMx>!a12YI<`E-FwHq2XNU-xdrCPz#0#CgjN&td69r$kL
zfy~11Pf2SI@k=!Hh>5k{c{=WnKI>eD>{?l3-;O<va8mn-^O9L`Z%>2$Rvqt?l+DJt
ztDTTj-rAlnTFUIZ-h|qE!9;UoJPYBnk)-J_DwZP3pH!ui`x2R*IC!F$LSM^?F;y+#
z8zUoK#FUb$K`RC?3=(n)(*RGWClK^s(TVP8WWI~AB4+}jEc$o527P}5j28lK7VJ>P
z2qUbsmsImA(aQ5Qv&cH=5VWLyphgD7hwmHb)I`>n)J(gOLtm}SE;O&z-b#RYXqMr9
zjV8$`p9@ox0p4>2XO4c$h?IH0gB4cs4|R<s-8oY-1P_FuZCTCAJSt|5ozxbdi(BkN
zTH$ZBqcmy;jxy_2-HEe5^np$c;C<~iFS^ugbLMA@v!W|z*ZTzV0NI$#VW4H^sL@&;
zsDLgWR-!yz<+F=fg(fAOfDyQ_cWAiwiAR!_jpVjeN6JxBm5i4@%L&)TDnMqCP`co)
z;iPCK{ur4IBVJ#h4>9og86hDPGsP?+EbM4!pIk_u?6zVKhQqD+0&zr)GT0JD@f|-O
zyY^E<w;=YcFTp0fB@c1&Qg02)eqP}zHqz2g+XNngA5$4;PA6!UsSeq&47#(_crSH;
zJG_O}A6^1cuFr{IWrQ$G9}&M=|H#u|O9j*zXKf;wc;Msm@PMao2-gz5CsK-26p8C4
z&q1(G!sL_aB;>#jRp#v(QB#f&;oDJCD(4_N3-}UB)xpReWHo~uNoulatn-98cJ<=x
z`ZFG8RIy_bED>>-Z@8?JroWC@JS%cMyWsWIaz$h#=C&KM>!Umy;n7KCK4u5uDK4c9
zfgp>-9g8mMP;~fu1I8Rile|<C%_@IZKeHgd27<_nMwR-CN=GT-m2wUntN3wj!xB(Q
z9ydhzt#boM80V<=t--_DIB`2diPL2v^?@G~8D>jKp4gbzN<jq`k<rwvKy`Ck9ORw~
z%pXR;7g?Bv<s!2QpYer4<~HYstV(TUoJjnwlT1(ww}R{VS+k{sC7G-Pz$NxnF!Mqa
zxtcS%OR*;cM{T_#Am6@Fb~!l&mJ=^s`RXJ`&<dUY2+)yvU9-c`R}leU=R-7+_t<S8
zeNC6FoCBbQY$MdElM+|hDhdngVw_gPZ$lQyjvpq!BHP%9$0KAhG`*_Cz19{p8r*K;
zHyEe`LM$b?vmti08)a`u>VT902Hi8@=O(gVrY<FKku3Y~ST2Pn$Tn?nP(6<~cI7d(
zB|;<0AzssO)0}NTT;CnrJ3)Qn&6)v1PWchJnzOBudeuWn1E4~w5reRmX~0DjqiT^|
z7tB@=i3rv43;Z^rPHofYG}|W1w$#CM!rcs(>r`;^pj(c0+RGt6dYs8)XQ)tQ22r4t
zdoY5n#jhJcf;}nraH3@!zcHyg+{r?^;!NO&WeePD42scqHAq(Ztj%5VHUld3SUd+=
z@g~4KUrm^*6Ih{(n>g5p^;}aMCo*x4L-35%lA-Gy3Z@XDHW+>Gg^vm^aAKPjoP^$f
z0eJv@Xiye>g&np<iUpsy89c=U5Td!&@Ueq(mDduF5Umxutg`iL3|cX#r-lH{%PR?N
zMfP&QRN|ZYLAr)XTXI2u1Ax?)^1uL_s#h}27htO(g@W;<Q~={i;;iH8V4C#8vk2QK
z+*1!KgEDxtoVdj&XH7c}LYq0ny)!gIHCpMV;0Yw$>9&pgNPH<+BT!)&#>_g(Y7>lE
z_zKveXy#;5^&vFz(II0HFxiCVZgg?krAj8DhNG<%=xP(MSzv>zHJP<5vLh1da;ZGS
z^sIxWpajMlq1qA}yR~l8{4y!LoE2m79hCk&zd_(zU_dbzK@hfLTC(o+0H_&0T81`8
zLN)u1(ZnP%OHKSlM&tyXhwf%t!SPt&xGh(t8bW|0FLNZCvJC)IzmZ=jkf72OlvV^%
zIH>y754uFMkT^0N@}zBCk~bWz^Zrc8k0f@r>qg+Ltaoj$K~5U%@uI*q#1KBKSY4E_
zeVOcy(;Z3vS&_u3jtLYjkjkRkqYzV2P$lNEMmUgTJrWD6_S)@vtIbZ=a;R}C+FjS_
zO}R$f>Djj6(#?Rt)JHJxdNg|dK0Ld+oU_kX)yv}NB^1NSXq!#xITT3sr&dqS*7Q^2
zi)_qJ?YUD@ew1ErzFk$}uoK4aeh$f_m0MQl&{Lh7P-F0k_lG4jpv2auXARjwan`MH
zZp~Nzj*9O{D0qo2AfcW-uzE!q2{BLD`ayeJpyF+Z^Qj#tE0NHf3<2&%?BsL0C8DlP
z&O9p1@g^&D=OEt8jg>;El-J{XcQd5g$gy`b;)cnYl<6Bib+t;L#ZN*$qi;hF23IXK
zUJmBX4Sj1yP}t{q)8D<w4`STE$dZkZcjB>^#2zwB?i!0J3^Ibfwef&G|9y12n>WDO
z#wFhDE?cp+y{QF0tH<JCFnbeNiwC7q0{1aUhCNumwH_$0755Zx286dGwnY&92y=w*
z5!xQ<SeTg$SOG`7eYmSzR6e_#4Q;pY6zt`hzCml{d05#AV<*4zi(FF6r7oExG<@m}
zaYl6bJ3g+qv!?C!Vq3~dG=_^0k%4248GV|;I-hw1>q+rGQ*ukz^0>;qyk~Q|uoJni
zpXZa6teF3voqO~+H{w+JNe}<2d!YQv+pFd(erQy&-OPHPA`+WRr)VY*-+3`&`{%eX
ze5tdKy~h(a1pM+lQk_kk=D46{1r_{1*Fl7?**}YHZ+yd|HEwyi+5Iz=(hLklvj3as
zB|+{7`S@e>Sl>Jl+%0EJ+1LJ2;rtg^QyKe-u((dKF1OAxyY?UrSSeq4!YzzmS8e80
zl=_(Y9jSSR*SV~59hO<X%^3R+U;7Sv>Y!pw>dJ4ARIfKOK#!^bV*mx%I^i?DPp5;4
z9r6nIY?)|}#WEa}dezP7-9RD*VGIN>jJ@ZrkE=4oGqAW1-Fbj5*e*YDBS%<~h%74O
z*`o;?Ellrj<dnpEi`MnUvs`if+v`FY1i|jVvSUXl_ayEsKNu(T#K^<l7o}zPsw}kG
zrJnuR2ie6{Zl9%pYW*le7THN3k|>b>`}JPc!9DXJJS-gd*7@hGtDSkqw2j~1mDx{G
z;Z$S7m7KPE@bdxdKnU6R;nbY)MDDa6FCGLWK)w7>po5AP{8g}YLy407`Iriz-wDgF
zO-^v_7OYa5F}y_by*;1CZQzq5T~ew@0dq(=dI9~}RUoUI2mEV8G1BE{HtvN)@2!S^
z7Z-1wn8M2~(cQrh<(zg-lf%|HoA$(0>+dP^#U?NOb>ld@xk+yRy`2|+sL{0N=xrlE
zN0}yu%Uw6}3eS^-`0*IcWk;^bDROdsd1}cC?$!3cI@OLcJ4~C8@Yw!|+43wcpbUl|
z>b%eO$5QQnA<$hfv{FlD(^bq4)B9NEV$E@QYDtJ%Sjm6YvK^>+5IBG*^94a5^(x&+
z9wBdm_1Yc@7FEScB-;=}#1{vNLRH~v<lUdeC=rQ%y=JXlK!@XC3Z9Fek<j7dpPqCU
zYF)-Wl(&#rMJ}pa^0n5eOlya6kOPBY^u=eM7}yWQ;J!vlC|c2OK+hybg4h}km{JO~
zfIV}r<}NI52Bvl~g|;o=vta@Ay3+EM87y{~Uzju(x&Ivkm33wk=Jctxy1&40R|u=B
z&~3|_)ShfYg#?sI%TiJ}PGA^GoRZyyNX;Sa$#JeoivDyO_an8mq#WiqG5gt$*};)8
zv*fnmFfUdHY5hQp-ig~DEGy-r<hy#nx|SF?li1y2nmlCYJsA4ADRU34sxF)ns-D#0
zD_zqVG0bOj4TR7KgN*t<!8-)Oc`rsd!=@x+3b1&Xr|d2yRr%Q+b+?6TXX}WcoNS3K
z#~E8wlSe<$#g7(}byesHkJBZ~a#Y46GPXe)U4=_Wf+R&*Bn7Mfp&4$sMYp{UY>T+n
z!KNrOS}SbLb-hJBERvC>Mp;}|Smj^F8r^Ue(Z?-65I2Ea=CWYyxsEdcOm{h-Wmf$K
zq?JEG_E{dDhBGYO`0aSGf-?}R?E#59LPZp-tK2fh=CGNpV)atN*|jf*u_{bv?|}Dp
zuIstdeKH}gc?t4TcO&`(K}eZsQKeD;Yp4?2xpsRYF==03q8PAFN?eMdO_?p+;?oBr
zQ5L8|Ph_Ho=KOK$NrZ;4`c!gK4+kD1E^^6AMS$%PK;@aL_)3Cf6<-n;NBBh%cq=vf
zGXKOF0v;%pn7~I<nXF|Q-(RbIZKnI||KR(I%1`7V*?7l_7dj`vS}0|@=F}xOHx@<E
z+mqA6BvW@TbWmh#n%bAFphR!$f3l&A7$2EE<{SqVeU&<X&qr3e+1h9(OWZ!QH3o8A
z%XpoDGdQLEpN8+wpLnxt#xRC~v*uI1=a-lNg}Sg6ehkM6O0N7>iIcfuR9kP|vf$N<
zZz8^j5PdkKb02tLI<Ppgm?D}NC7p1Bw%H!>%;UVXjV7gvuE`*FLnSog^?^})>&mHh
z(?|Sh>Ou{PJ3wog<j_<0dlTji5%mcT$?@=a?`cbc$+_)i`snewYNmAace@qoXVH49
zSE_h=ekuG{WLxKi68k_1ipWPevZEVsWF}eRAO7r|7`HX?6VJ-UH@R?lekLMI0WRH0
zV#jf~+c0jRj2G|ny*h^1?r`j{No#}Bd*Xt;r6`Uc)WgSqI(yuQ``8jcYpzIjX=+qk
zFC#4GZGAL;<=+0}bxs=HF%F)gkKRCPUm%5x`O5vobE8>Qj8I!M#}`BF9`5U%ydkM-
zAXt6j`hS>uFN{cT3#!8&Uit=Ctr~0z=xg05d6_ew7=*=Ie^k*faFlSAfDn({wf1;N
zDZ~$Rh6a`SOLK4M?0|g0Wmh^j*<t~ajr6704V>dyto#EOtDYw+4rV5|9%@$~1({RU
z__hX{uRttgo(>{5{(-{UPu*j)H#*`zYc8Cij@|z`g$;%zd(3C<JEOMzg~M=NMOfic
z9KUPC-2X+_Jaqx%H8t99`)6itdt)qh`|?LztPV@M_T%86xbUS1U!4`lxfchu6<*J9
zA%FjvXRU_&MBY?Qg~LJ4{bm;xaRGf0Z>X*05UjXj*X3+8(kvAjrPFWv46^-2Vy_Bl
zr^Mq9hfVQhPt!&TsNNDIV2-XyyTWa|{l%cg&a-=ebhm#1_v9dQRk+im`Q)!-N^PxR
zIi7w$Y2B80)hUPJV_w6Dkn>j&9usk`Y+5pLAhEEwPNV;GZ~kdMs{0YQIF?;pi_R-b
zy1}p*K7h^=rg3hNzoR3e46#m8>g9h4%3B99O?mrK-poAG^o_5*+@ZFPg>z4^=ve$B
zQfE|X9Bz0=8pJx_U+V9q(9`JL-SDe+Q|HZVyCYQ7F4qs?w6LU_MO6NoN=QF}qdyF?
zAcD+h@t>88Hp4Jd&GyLub~w;2l<mGdxdOR$bP;NeHMrWM=MK^!+<Qb<mx&<@+PS$I
zjA6im6w(B?w~|#%dj4>YB}|BMj0MtkSmY3NqUn*%>UCJ5KQ38JNmN1qxp}Nuws9>-
zI88=E+y=b<OwZKI)V44=S_mUl1WpUv*`s>D&h-KpDqHw5+CcP88cuwLc3JgD$-x%o
z`zk3p9)JA=>(LxXTr{O&q0%;77oGe|4Bgyyg;57aob?W~DD=nGDn^5zpM5!E>@JZC
zvuAo|8IG1+Y+Ly(Rf!02D9$0B#DWh{nX(ne_a5^$r03I4oWT3Ih7X&Q4#}YMd9?Nf
z0=-FNx)SP!pd|VLU3;<p>i`kib)!t`Yb=z3#4{X>cxAH-<6#s6%8ZXb)RL-q28S$l
zfm}z(X2||X*FnCkVz1r(pJGs{lYWSguA%fC_Vwr%SuFAptnp(kAMsOI#+R29Cz8n}
zc|7`r-vIEe6*#F=t17q}IcF=fZ8`70;lseHjOZmnuPiw^B#^3kN0yV8!|5=xkYH0J
zJ%UbcI~3oFd3mW0MwH62i>ZxyvTzDwP{K9nn8FJJ@3*1XDc!QgH*B$Qv39VB8h=(o
z`Fp`>EzR$eOi<3UxeS5d$LzU)qKmlrC&Q2rRFfXKo-Nq#sB$)A;RMzja1g5XqQcE~
z(Y&4z64ij!^ZGdmO{~<B<dr;45q-px3p5lVJG&Jf{R}NzcC)e-t(PU|{~&WCPe(Kn
z7y^#I4C0S<Q|L^tIK?^1t4)0GG0}V`*&s7g<aFVtteTQ_x<1wBmPR*0hn<1d+EID!
zX0|UT<nrL`u9ry|n-C{y)%$*dFDoFb+tRjzeW9zm4`dIaC0bU>>yKC*a2`vRYQP%^
zsXuGPW#!djo(<zrqleoQAAW}0Sr=ZLH9E%}{^T}XkJeT;<N{98w}f+&#Kz~IqG?}b
zB_|H;rmLrzB!$$vhv1Vo)g!Q%CovVz%waBARTxTSSI~06M_g7*&TmDO!|!>0aP<pO
zVQc7)c2X;Exh5Nnmsf!C$bWcw?DV8`=v}KPvJWTdk5}XRRo+baQ0_fgV|+@&5>z|S
z{%bz3lvDoIY~u@2^5_ehITSoM&ihHL?p8z~DbQV!LO}{izItWIoV?iN<&shcEbM;l
zUBQk7h!oA`sJ3o=d9U|-DTkY`74ZS!Dg6)rp-t<%A&Xs&E=HN!@AE|x_D`}redD3b
z(&ZoKmJ#aRGhe;XD{p9FG-U*mX79-g$LeGH-j|Iw5C0fV>_-vE+s;{ttNZM>X6&|l
zb4vK9&Yke*`s!{<xpxIm$k)D?_&H%fuD4Slx8qk{__8<}Igeu?gw%q6bZ?xfj79xX
z+l)ZmF5hU_%wAsei)Ad|vmbNIj_0M_-PX{dTHGifpTG+mLiPF}9(@6_=7q86U7Knv
z<#O+#JB#$Wv3K%DG;O2SXAL5im>^=KH<;ai6Yt18>}|63pA%a-@op=||A~+W0KMtO
zpM8yMJ!E8(-PU@Vwel&N*uoXA?M{rQ`NziQtGjKUdjqdk2^F%ld`dLcD#pcBhtB%v
zoO}GivvXU0%$8ff-c0g;%7g})`MA*Wuixb3LPuPhxb@;4*0xV&6wVf|eQCa#OZCay
z;L%DQJI#L^(iVpcykA$j>2Jp>wRIx)vL~6oAAN<d-Vzf^=XKqPCFcUQF)KM!9M!Z?
zg7w3yt%^i1b-vq7omS}o0N<}SVv<|+*@ztt$45Vs<g>{`Ho25cxtIGHmPJ^38cuEX
zx%*>VNc~JW`}yzdB|84;x6)7j545I_G|ZkmlPr<9k@CHPA}y3H^X2E6R-HudfpWI1
zZOV>ZWNkm;xTG{mi;z!@BeS6FHxH8v;1h0qO*kPWDfI`x>aOYB;rk)=4cs~6R=Sx^
zRdyj3w*s@H)Mp^L_~;sGJc|`@^`bDHAS+vucC(Xp)BqP&KyVe3(~}~lsX~fhOsIpU
zg6I!2&twrVuQOqDP=~ym?jj9(1R;2m<^#Gt+!<^^E>T>QWrd%UW%Ve2o}aLz2C`BR
z-*Jw#RCtD>kS2_vfMTBlisk$%o~JpT*Be>7RAy($T7>Q#w3DxwXK*qlO^yI6%XrZc
zVO$$zT&3G^6~kW!0ku@%)j&7r9I<)fXG<u-(Sdz;@Kum&Gt(&=ohTEy4%F?jV%!#H
zV)$u75<_s79%8o@Ns8mPSe{ypnLZ7_qOxf!KJ1m6;<)XFkbaC1s@crefHjaxq5vTw
zSK}etjiV2lKbI2qyiJCD3Uu8pU#$Yu)^uG2WNGDyd_xtqyLms|fhg|^Turj!cMaVk
zpu{g0#B5hAa+KuW^Xw{?n)(B6ep>sLvMzOOXGTyfhk>+O911Ov4|F4x&`U-<V>A$=
zd8)yQPv=K0*PQW*kT@P;bWW9w1cw0@l+zH;ImcWRCBBqEZW51!LDBJu<j1KlW|Wd(
zGHJwWVG|W0W#8eC%ikXbf<sAqj#t-7tEj73SO&s!jX`}l4OT6|Z|OAuojkhaPnAd@
zuQR@mP|v!fTWNcYmPqeJzU`;#h`T<!WCL_NqCL{X^gY`y;$U+D@jJ#rdVAtJbsxu&
z?hqIDigz2Cql)I2U~_T;aN~Jo3t}tK8{9sJ#l@1v(uFS1xI{MYsb(bjgi38T33Ja1
zPaz;yO+u{$2r>r1HQF%FLyhHXOROhyl&^x$(^|<I22v@S=fKTXHj`~Mr}XN)AUU2`
zqdmgu-OKH=eB*#J31JrbH3g8`Y9r<K-eZkf(X#@75qN_@xo=<Gsn9l>J?8Cm&4d$R
z3MSoSqhVW8QLuqxHTMe3mVYh1J^7<EUDCPEd^$B>MXHkA*>v*$5W48|dy_nz8{~}8
zx+HYM9cRY$_2LLrf1Yf8Bu~{PRq$PIm<w-=_S^QJONBnUpYqM8R?=rK<dT;WyFG^S
z;W5<K;N&R69jke|z?(2JsE^^Mv(%2<yKxGNj|~UY?2YI7C8@0|ats5Zd@;({>y!9Z
zK-5Hy-S(RA%vYO>9OJdkk6e5w)y9){@e-%q))lRxcz&^LC6@5#XXteNV2G1{YT%^y
zC0)1pI3ygN_^S(OktD#LW?V1RrQ<Um4+_Mx^))WAT>ruKOTR?Vz47IS*}ofiYsWUK
zmNAg-<a5k-o@c84#Len&D>(NDEdQam2It}b!ufy6fWLf!Wnbn44CToAaaqrn{*KO}
z+!OZwqT@8v_*`lKYroCr3)I4sduJ^DiIrG4rP=C`aHVtqRBm&V@9|zz8U)$o2P}AD
zNqiM&PELzvZ`XN)91jES-x?zyWGJeMVhj82A843Vuq-O=)RM?AiwBX&eT@r@J*z!7
zA6GF>CcXjL5gihqf2h`$2GI6|-$?4&;jg7>Fxn`Q(fopc6UV3F$E$L#Lpd&+Ph&9^
z{`g-z`{SojXFhnDg`>}<IfsN%q<^2FVc@x6%k84?pq+kYe|}cC6@|5T^HNod%JU5-
zPM;ae!y0)D&#?jMl%~iY_Cbe)-6gQ>mcn!zUa}vaH$u_=!)A8bXMT>GYTiG$+*Mnv
za{0xNUP}eN$S10#gJAtPuJAo_r^#@#tV{Fcpo9o7#qsk8;;ho*Y26L^1oJnLWm3>?
zt4}V+PXYAM6^C)Rbt7?FV@r~|2^Lu$63!M>Bm*Fl1t%kQ3*QP6U4-e}ojpGzTgbGP
zDspvtPQJ#+I60ca(73dmCsQ9F^k}kfZeNT}P#-vCXw|<C!bfZ)eSUAHkP81>$%1vh
z!6CCBBNs=`EGBYt>o(rVAl!pBY!WFfFDAMR@xf*HrhGp)kNyb0orB>Zx6K^xs;v$$
zh-KqGVYl^$fxO+cYSW!df?`Fevs}A*_T)OZ#d8;{tNiOuqQHsXDNk?H4RcuZGaqM7
z-O4Qw)-5<9Q1;%@M*s<{Kc47$*fzzgu(z9TyK_0<)~{=7c<VwfSQT%CTdb``er=8B
zy6HtPjtbjNSA2KTc6>x(IhYJeF2o5pc}g>O#0YbED(}^B%GtDbegfwvBvu5_f~$6y
zvW#w`l8@@2lv$w1sT}h%hJfk$xO*r0?+h)xVX<azXQXYu<KckA!v{svfdgfYO!xS^
zRqbEH-7|Hc-?Hhb;o1$|tY}%l^TP<$Q9L;Y!A#p$ZK>fRp6X1fNOz}utiHz(3}0Iu
zDAThX{tVJX(kgC}ia%H5^nZFsPFx3*SW#AM)QpWle3~!QG3H<R&-qExtf9jqlyheU
z%Wfg|V&%=UXH^dth?{2@vD+F0T(<;pq^rEE6+H(Ur7>vtgR*49C>ts5p?+A~!r+hF
zESBu{j9f7b=ml!KyrUK4aXT<S)%AAg;vooa44SRo#7~dj4n*Z1U}`u!4g83uuICFs
zq37sYDA6)9z?kK0QE<h+GSLr02$Ai?+C@fDZUz4Xl#tS*^*7k0q1Cl1z$OI-a2g(y
zPGPDI%j#T;1Qd002Q`4<dC(q*(=InF4j+4v-xg8IwHqvi`SxyMwLdJxMeL&X816~s
z%R+@(%Sx_$$X(&|w)hqZ3(?_fud0+O0`fRK^vL)valEzNR(BLES?U7HQ1%wi^(?Xs
zMwzpzqX6DtS{<C-EEc9yELhD;EL$MP53^NM^HYxyG@qzWTPQRK2b_#i5WV5Sb!j3T
z-=Yt(zl|A^2)yuRQ8!ld8w8mLqdXm}C!%*l>vMauV(C(04ggU{ZDmp2+1TQqY*E{c
zf|D!8&S8;;zrL4~XiRK2-W_<iRbvZKeqJ(QCTMpjvH>Wv_uhB0(i;MLXpgC)SK#$H
z8Cb4ls>$hLIdOIQkxNj7H_tPxxyW%yH-xdq8Fu4S7y7@L|J}K;<v4GJd#dT?eH3+)
zIkWb!n(rdq&a-15;T|z8uKi2Q#yXc4<KeYwn=|2KUU{>pvtKZ}KZe(ba0QzVx2KmR
zN7BWS6?FfNdFPi;%*1|uc6o-Cg=3Xq(&V;uxtCpH?hJa@={9Azg04)d6&Y1Te(A3=
z8UJi<<sEOV>Pv;VyBSIlrKcQye%VIZR24|qSz(JV-S<*Pm5qzCaL;}80nGTXR`46o
z3+zbl&(=milsPY-^a55!|9dP5IR`@k#qr6?juUR8*BUCa<y^BFKV2}ZfMs4MRgLv>
zAf9CX;T2mw@d}QfUYI&Jb0E#Wf>JW}Q{;i*z7QBM)V6)HFSp;lU^*6~VnE&Uw=P8@
z{@?*-#L4@(OzB<Tp7}J2z^^fkpZP3#OR^%RZ?^yD_axJg@5}SU?^*NhjUP<yHxA~-
z!RIWjk&?gmAf^5^iSn<l;vpbU3w`)<PN-xftIE~Km`-M7k))ym6}|fzB;g5P;;HdJ
ztdulNlAr*ynno<+a{273s1Ufj_b1tZ-RI)hBkjREQ3OsVykNRNcjI@j7K%g-8vr7^
z!9+|-v6{$wcaxV_YO}dV_|`?#mI(+-Na=Mp&{UPT`~Q>8mSHSUfAYrcHO2i_uG)xe
z9CDk@UQu?0j<@2gQ~u0b{v!(+x7@L^s`|nNh>xTA;`&$l%iKGYV|K%M>cZVDsf=G1
zto=`#;od7z-&Lc1r?F=Hh#M9BzzuTaOg)YpGpXi2l&;$k1~0<A+nV<lgw$XdqWeQz
zM?OGwLQ^iq*=d0O*pUK-;QE7C65C*->vO(JxrVE-{AZf3-2P@Jg6;F5%f@UL_Jeje
z-qZV*vZcS>8cE2z0Awd>9WbI~)h4gHyH<F9c6}^RySBrRYia`cy?g~BP#k=3G2GHQ
zD;q8DMGSfSp~zmu*~Pdbn@yI~so%g<n|C4Av|^q4R`XzE>0hA>aLsA{ScB?&^BH9D
z4pf#aFUswcNjeH=9hR?`nL{n=t=rN%v&4SVZkY4QRC?n3j-~!x=J4v+;l`?tFMAvS
zON{Z^&p5JX?Nf)F)9@WWA+1{UX@R?XC>8_!yyr<*CDFwWfoCjzpE>!cHc`VJmdswp
zWGYDlb_#R}{?)LC1r<}iTx0iQ;yq{P_#+o}Xoor)XGk!kys6H`eV6&;P0PxbIlrYE
z*0D}`c5J2Vqo_V?22Y?f=~YPPwkb&wFd}1~yhdSQy1ZmJZV6jZ|AL<D<hvY@!;O34
z>JomWP;(c8jo^}CULK!)4d4G`tf?Y*5(nFVFF2FzRuO|9Ug<g6bR@V+)X%_un&5*M
z6aV=Up4|4ChNSQ}OAbRq<TXlSGXmXY5*mzO5|9p9c44(<3%BP?(OiqmINVzm$|vGU
z$=gg9b@xZ^RUkHwK3q5(S*<av3Q=6=&}SzdlM3UT&GQtUpSN-)Vin{o=dD*9hp5T0
z#{f(j=h+IR1v4%wrezW5nGDCzLe;6t+6R`TG%fCoASJ$#=u5T+NwDxc<8ASETkL^2
zEUG8z7Qdb~MN4yF3rVbQg+^PlEga<>zgyyY_6J8WRoVBjlqw)$*hnzP!@oz49yEfi
zC^fNiMMpfV9T#V)#fNreTX8mlFNN`4Y`GV~W?v5($t9V2o6Yiu*X>HFC%5zX1%6!!
z)ib63W^<8SmQg)=tEYkoQp?=qbXOU<qQ^^Vx_F7(wjxGDmfe7FAGUW1b4K^!EbxR=
zSWVU;Hx&3yEMEk;u9nX>eWPtNH84ECUcQk*h&K;AGWz!bw=IsF^0>=b#+v~}24iu(
zZ<SWkco=SOVSIPuL(SD<0dL~(U}L<f^FXtmi5QVe*?F)TT|O*wb1Xwp85K_aTnj@D
zM&M&73^mW66>O)!oF3Wf#q|Siy=R~bB3R}ZK$@=UMc>_xqPTI_z<l-|64UhN>ujAJ
z*>j3qc8UiZ!tya}gRE_QP#kT6?&)D?C>o91R>Ekhapc{Kr|rhOsX?<Ni!19_XhjA%
zeXg@5vD&KKx2f26xv#vc_hen=&}`*$^>ABZgE^GfDYPHu_ct%jJK=05nBS>N!|Zos
zli3>KbbCnca9D)lwHxz!W|iEtG#|12o8kLyX)<yDc{bsBqc>gp_jCZWRId}ZTKa=@
zMklE@M}GwL4<WFUV(z?8MMjSpR^az3hW-;XPaY)u35SH|tM6;xlCN;W`4@!P7s9mH
z_txIDBhuo1dvp8#^B3&!uXE6GVPuG6g}p#pL8#jH3}4V>sXBwA0O_*_oh<A>np7~Z
z`bj*yt@ucz{7@d+pTE%DJwF^6ZTQxpK2<Rgh<!}QX}kM;>)N>`c1izb<z4^4I@|=c
zeld;~n6U|LEb<2Iubt)HvCGqJ`8#`()oVY)R{!@#*+8MZ&;5TLhy$Qlc+_s6p$NXT
z$MaFdm1i#d%Mhb{YX6umzTMf}Z%n7fd)_`{t;f%2N_>PDo9#YJ__hWrjko2`kF41$
zXGS~ET%8uln72p0@%23xnnsEwzY(={or|VYc3Z2h>t^mV6lynsFIA59`$wge3NzN0
zItm5jWJf@8)u8-izA;h<_Ir8-N=-cc*(TpW*}p0`TH1`4<!3KAFnZv53cjSZsA(KM
z-t;1}+L5aH@qc3po82m7wmg4kUXlE8WRErcp6>hAg?2ZQcP?#tqcdIcBjs=ziYZxJ
zL^lrM&%wE#X+!zyOH#c-YQM1JU4XfC^)tbNIsmd0=~o}1pZNN+HST#stS==|0z9V^
zUs)|~(<dQ+I)BEN*I%5aw>@h`o2gRx^W%(4^9Ry}&`6VKUmuEiw!Y0ryC?p@*~WMF
zPAAFO?8R%hPdl%ofitPC?XvX-K6-Se(jNrW>3S>MBtF_dfUn9}=a*Uy9_Jg!meqKM
zg}_?M@;^d|zr&)E;QZ=g?sZtyuWuwlUe5k3W8T~FQd^z**Ertog>2afX}HrmHZ(j9
zW}9{ZIPGp`X3s>j-`I0dUAgY+^8^Ndbb@z7`jc}^P7kJ&%}dgvdH5b1p__3Eu3npn
zwmwFSut!G%YHP~f;SH7*wnG~3NJj0d^YH!sGrYO9b7P!>elkJAj-Ko56DYEmCKsWT
z=JrT3=fk8Q^S7BlJJ3LvUeqm(!}o*}aff=6vMAXi*-mB$mx>BR=xl>nxV2|I<{#42
zkhaC>IYMO%NUik9cBHBwU2#?)x$v5=SG5H6Xu*S7{H0dRV9^FoMgmTomP3P<VB^Gn
zTMS<%kq0whkz`m92~;VX^Gy|F-p+%MFA|_d(++C{J5KTxb1USk^R&MxuT!OsXP6^A
zs>9~7=@(~$JPAy#o&g0i9~rU?YfdfUlb@g~-9;osApYE6h<o!?WpwOp6ssu#`Uyfb
zyGHax5@q190Fc&LTak9QUn+0jeh6^~F{TS=!0mJ=dghv7L>Mt|YQgdjW%PoL4Bx=Y
zO%<#19c21VgvqK#2U7B!0A3l#qLQp3OtVlI8Ie!mzr|C!q#OqESWvR|0q0|qs5zQL
zS5PO)?s4MC=VVk+CT(Qio0+StRx4Terkc~{2WJJE?R2t$Jy<C(OJ122Q!#zHNVcHn
zMfQrSOOp3)!28O9nzD0&brTJ}#CJ>ORDUfjudh>!vn|qDW9ZxjvgBsuY<SaMqCuGq
z@`zFJ0l39`a26tFWvFZf7xSy-8$D!bAeZ(x+Y3n<YMovLu%H$kUnh6c&?D5(u5*V+
zQ9Pj<(BP#g$jud{h0sL{d<!|dgL^VizR3a$4?!{}&2&j98$^U|J_pN*BX%dDCcZ>M
zNW9Q!P4wD&0-D89O1vn1iI+vLzK~h)hN83!(sqAXcmYsLuT2~=;`j-I64g(hLRxYd
z(ML~~+f)Q$6qE(z#q3qSF9_<C6{)Tlk)2vjF|`oQXt+qVO{>X$)n|M(t{-h;>|~3n
zrCtj}fcj%T)w&H)tRvu<W0>-6UMX*m2n(zs$NY~<5Gx9l68sx9wDbtN?g=UTs%=7R
z^Xo}yU5@_X=gzA0eL7;h;i6~uG^1ABL_HnnG#_OlXAa=vD^;aBnhNqZ`w(5b^Y)wc
zDR<-H&TeL!*|_q00&lY<(<H5Y9eI5UkG8gzhXE!<57|{3w6*B^ii*<HI3n4{)PZb5
z$XaJ+df_HXf0X+x^3`xZ%3(`4aUb0H$MysjYE2^T4=GG9vWT#LCPj4%Rq#K~i+o$L
z0!=kr|7Xnk-pb<k$@+WgVe(*n&nJXy@=NVUa#nXAvb3NF>3ly0_&>AQbDr7xa(G~b
z-PR&|vvKPlCCaT$jq)-QzAdfPM-k}@Af67HrT!6Sv4jOC*B*srC$!TeuHaQLxo+xE
zZhFf;k2@ZpWv{GQQnnpQ<|r^O=icD|{`Ea}dwK!>x9oEPMK&xR+gsS)*93dyxjmdL
z=JR{R83?*bcs2WQoMBe#5$qPvrpa2169A{}QOzA|*pUlq2)}Z<rQsJcw|?zGZ;p<7
z`nx}vk5Bq#$7zW{kmQRqti(OF$3~vGAU(YPX_m2x!_VDxSH~9rW>0SOZ*xqQ(NC#p
zGf%$<t{@vGPg*B<l(;kAWB%5>v2I^DG!yms+aEeROW$@VDVCnoRQ>{|L&7@Yytw+6
z(M%{zs0Kk;3aG75c;TtodUYDd=G9avwtRn6;e){o1ypWlzSqisSY5`0{^;j6&{_6y
zC_HLuD5)b7_R(jWneO9?yRGHN|4ndHQd^}h-~7METf=Sg!t3=Lv~kqdI3uGdVIsuN
z;Sbj?acR_NpErA0%u$7MwB;=P`K?l08}thB`>+3q`9Lxj0vN^WkGo19IQqfL-#ie^
z31bggc<TCy8!+AKRo=Hh&0W<~FZFOj?|c7;Xvk#}!j%-F7GnIP+ynl`)`A`TQ%l#1
zrk(R3n%`HyeNISGTeHJH?f5{h;4DbzE>9jpZ9`^5z{2S@8K$a;chjGgq#M`8jwdfj
z+aQGxQ#=!miP*`XAD7EQ`pnCb;N=7!OPp2<&HlSX`Fl5_J_b5!t4nXw)d&si_*c?}
zodjhFNI`V!u}K~{mUzr*S?${{WCTcC_H{ka?a!R0=#RfcN6d|pmpS${$!O|=qNGoq
z9fvj9`$4$)k(fJh{9>l=z6Sry89uDs(MZzH7<m);ea;YQo<KH5q#gTgmL1S6uJdX1
z=l{&TDd8_+<}RDEaGs~`Io@^VlY4MB!inpa-J}djW<$VR1|ZI`HsF=ckgfF;l1NS9
zG}h_!hSl&&3C59AIc|#CCb?5srP0jmY;c?XW&AW_7z)@X-Gb*g?R5|2YfBY0Q}N<m
zV6<{H(IxrEG|)i9Y&AMpxI3Cfa&PV5PACLrs)iQFMdwjl9Vxy^0VOh^L3TktkhRD4
zO}RKZ!!h9~)CY*P&cxYftaNy0yh~VkLezV#kb}sjoP8lSK_`@&t1X!?NH>CXtaM;L
zyU5i(al7GW#fFkS(GAJlc7KTWNlef0@eyzNt1atbx3nbh3H3kVSP6<b&Tl9HQT){m
zrx^};oJiOT!n!3_N^b<+1`q}iGN;Ea{Ne(`0agUkAg}%qqnF@d3Dvk-ML^eykmu8t
zMTNMA)yJtaTdP_O2~)+7@JXB{YtP0PK^IBqqm*PTMWvaF5u*?&SCK$%^+CSTkY#rW
z;Z!VFAv=UoiK&zYVZR{IrO>PJa-bG;Ai8TYN_3PkD`2T|oYD0q=Yc1&&$KbT8mQjZ
zFR^AkUoeC^hR1S$m+_vb!xMTzU*xHHD<pHKpbCh5I9b|Npsc&X3>lDSBUHz)<z-`b
z?{6n0CDk}t)SFz-wDIr3GuS{)(iR3MTDegGA7@?*;QHFD3y<TV9qT+@#hIh#rftw9
zzy1(H4g=f3i?bR+ZTb5=bGIcaH$@T)G-O}p&Q~dl#aor3F6>KHz7Z0;o-DlpSQ4&c
zY#~cAb)3VmmuxplDp-w(5ZyvtLpB!`B*e%Qvp-C$vOA+xgtrCV$Jb;lU5gO%==}kz
zSC@29L50XIh6b4>F~e897}U=q#ZREy6G?AxMiIuO{X8fFH(NdXnPF+G47Ovo&V-M5
zlm1CMjj(NvXglIoSCzY~oN-8)?7W8P@ccApn}zi7elod{B-zIK?0?>trg?dfrTz~B
z;rkKBpUx#TT*P!fq`$#&<1MogQ2GG;-OD}2UD#i-@iaPVsX4|~BzG*yeI1^C?H*_T
z0fmfbQA}ZGxwoXXWWPHXrCy`&@^r66ZMBJYdYqI0B}<y$tnmDs7sJX24<>d$1l)h3
z%|62zz#(CRQ3jZ#P1+i-YCiuP=22Tq`%L2ASvm&vXOY$&Np`}&C_7>&W)@hQ_Gh3_
z-;UZ^q#Lgxh1+b=l+XYelYYA+#QRR;IZP(kA44r12118Y<lR;@m%lk9Ex+&ziimQ0
zHqDN;_PDU`L&ZUNvcY!8>s*}Vv)k%M_Ph?MYbWl|&m^|kV3w7#%XRn}OL=9LpdmnN
zb;w>%|0iUn1r*N)u84Zk$b|UOc3)J1Nw6#nFwPwDcIf<s6Jk_?i&;9J)<jwLaPmhv
zO*WXY&rn;<KlR3R<R{NUIsdMRTK>iTELOdrfNPm$PM?DWe&XjXJoP@$>iQe`!Vc~8
zre`c!{kMCHFmWrKefny?2sBGVS7-Lzb^DWa?2un?{ZBsO()hR)7mvFj=Ci*VvmZwr
zotukf`Wr#|trw0;SA|f6lSTUDC%-ji8~#EYYIv<q>(aMK)9U>8In#)&-fi`op9RtA
zkm-~)i{j{i`+mzPg%I~&_kD&A@g#y(xkS}&qk&E^1c>a|_g@fOdUZ&cR8%n6AEPbR
zl{2X4sP`e4UwNjvr>;#pnxD_SmnE?EbTQ7P(&LYEj(0FspI-6L=ujS+GW!qbu@Lmz
zUUAlsH0`XJe_)CGJ*I#0CgFAN#y<3Spl+}nb!8*-eBEa0@yBS#zx%@o{m)?Q_x3+%
z3wP!A+rRlSYoN9|Du$2g#Sh>-&upo6C=X(O7~m@Iu7Zagq99@{m9YT*vGA`<+V&0g
z_QSx*3aLO%EOi(`#oFC%4cn6_wITS2DJ=@g$G2U>8=MXahg3dMTkfW&H2Q-O-5D(>
ztnMLUS#>*tHRA|^sxL?&8zDWGWSynvRN8DT*;K2Mr==yHAV1Q%-||+4)z?HHCW0;*
zxSg!EKN|CwUDh0DDUc7VzY8gT>1t9an)E>XI&e6Z*(X_KDqfi<&Ck8fibwbOBK$4&
z%Cj`w`FDJE{Aa)qOnQr7ocCBQJKUg#T}9E{+{j(cyh8fGrO6IzD>wC31)v&Rw9Tn&
zO1%vSMHkH%lxVkwyI$0w3L_MG>8Bmi%wy4<&qFAJbKpe%N<jl*i8M%Pc2TJd>Zk0B
z?Aioby5Kb3jF2yB8wp3usK>7*f7HtbJqN;t6^3FvFMCyEvIOQG)1s!5)|o7IQ-#uW
zk+Q?4Y|l&2i)t%#$(0sUH;OcV`N5m{c?{Dp0u@8x{7WiJf0NdT^tVIh0Rx)6bVAbM
z+FNd&-j1}3tCtw<?XcM@Tnf_Jt@v{UmgLl=q#kI|1v88AR-(kEEbX_2>-dpa)=N;H
zyTW*&wZzf^W&6!L%LG6vv5FJyF-dur{I<iCoSqbh0+lBPp_EgVhrlB<CA=KTv}_(R
z${$E-f+6vxJP24_NfO6lJxiVEu16ZaB;}Gd#(eQft%wOFev(P^6N)tiyf^HQB&NNB
zmAsQ>5F7_#))Pxr0Ns$8dyH(&%vUL#g|`B{vn*(rvgLvWhjQ-mHR+E9YXexdXrvjC
zw}EgR4Cg^i;<tkriL;!Ea?>tV3M$cq_GvEVS@LCO(}bY+DCHcAE{Z)!_H63NHzlIO
z*&kdz!OC3_!$hx&+0T*C2<~T6qrZhnsn$A5BN0MdWd9J0D29MBBeL^YnADj*OBNS7
zRiQyigO>KO)0RnvavumWx?=T8a7!e*BGsH_q>^T1u5bgBvv)$)#r>MFoaR|R;VB}x
zR5s~j9i?mpq`KM4JGubAzGekIWB|ik$L1+cvN9Vyh2bRNgeZfcB1;{j$p|+K7*McP
z`nFPPA<M1u$@n>$(lwv5snn0aM2hcva%LCBi;sZUAP5<00qSw{5NL@c3}7Zs8#ZD+
z4~eR3EKD-vs*b>;#&tO}t%bl-5ND*+WO{(qVg8U%aySD;z4)#8f~dp>KoDotD`IYz
zY#nD093IBo%R>!oFf^DLfOwR~7nHv)3ndjJrci7KINQ)bQ&Ucb>O`UP@sRZ*o62th
zKvrlvU=y&{gi9q=5e@_d6ev8L$gqTq@W!~!XDNqem3&sky_Ck>iR;z)_JzY};6m6N
z^zQtf6pxdW4&q{Ki}c<wN`N;`XgMqCR1?np@=9FNF2&V(6xJi~5z>w#8DyO*+$-UX
z1}>Dd1G<7`AvBz2S6NzYB(0#N`@>-q;xgpoKq%TfLXhte)#MZurM9&;oKkd36sSrB
z%eF2<@dCf$$@WrLETvV$wg7p08EKD#Tuw#}zP9vzF7*u^94NLT)I#@i^`s$3kMkNu
zo`b;;KoJcDL_ebbY<O@rDx&Mzw`C*mF-rOog^Q9cgrJyPa-)%WC=j9#zAKmRkRir%
zX2{MI0Lfla5`Y7W{8f;+t|jF>TesnLeRg|P^Ik#|=DqL<d8J!Th}$B-!b>&%8fTF|
z29aA2rtDcQ1BXMi(@GFqo>3CGt3FK6Ami^15KP*N-Q+h*VqPzh4g|(2KLyr(=5>Et
zlO{2%NV5zpOrtWoy|yiBDKaIuS3sr10AfuJNaIt@^*hSTHRSLF((=hL%L0fuB91}U
zdGfB&3V=4<ESCGoff`rPgkvIjeZy`f&Qu)ZKp-U69w!S$1j>r6{h<VrqDs8b8XeCW
zq$<KZ4>GB#F;~f&H*L#M#$8Innq@C5=uD!fg`Q#A=y5@LM1wTZ+&KMsTMNbv7s$h_
z(8XCSee8XqB(xw~URWZh*g%M8*JxOi(~i|)*RB4$*@F`DBc-lf9jU8mL@qIPTnOzj
z%L7l(kpg!s7Rg>>@Ke-`mK;=cJ1jk8D!K+3LM-{k_H!8)L=h9!>uOj7zh3U_T%n=y
zgXALRi!?fZiWqA`3lhUN#^rlDRB`3+MY!SCWp~VMJCt=y*hhD)U`ItSEy3W1A(_xA
zqjni2um$-*7jV`NWWQD@yB!-ci&<($oc=~Q0QFN5dpU|4aL()8B;sBFluiltun^#I
zajXBhvHDTLa?d}5TgPISKs#7l1S(|DZy<zjvaZIg$uf<MdPwbGJ)f{3S?%*srYMMw
zV6{aU0Vz|kJt1^`cY0J*OO>Vv-_hWRYVjtUSjz}VKUzq;0yXz4H_j*HYfoG%6VOE0
z@ziZEQP64Lw2{ywPjEm&w!*r6o2N~z%IptLRU*<k4X?c3DLDwAPfPgUPYWO5v2=lN
zhHoXaLSri^G0wF#KZoeT&r)z7Zkuf!@QJ;G;JZ}|FQ*n1_t?_c&ZEn`d#YeXagIet
zZCVZk=hK^<48p|dE)$mDZ^_c@Nc*IB)r)smb^EZ5^UV8?SUUP?K2!r2P7&=+E%~cW
z-IQD-%OI$Zij^;?Qv83O23ysO<l!u2*Iwgd>~PaOMgFQJwI_XH8?4jnEw*g>{9xfM
z=WSt*kwR2o%h`-$NqXJn0*<9(Cht5@?8Tbd16k&fnc07JF5j374(lMuIrSOyaylZ5
z{2JH%S59*Da?fj~PRH2EC&g3Mq&(~F)b?GqA{=c6CDprDV+r4iv;!Z%)4EIgKhI+5
zci>?4N@tIJvyt5U_}KU)_jow1-RIiK83x)Q=Ed_#dkt*%k77l=jueu&poXyN;N!tb
zmcNUO!3Y=rcy3R9uW5^KhF|(@zYe2;u|5{8`|O_3E$RNmor2$c>A_3y`yTJY-4T~c
zefC;Q+*>Hfgut~Ad$Z5pky`r(oR5E8N8)(3!Jk=7J@LVO{opr}rI0+hU=KbQ*4ymE
z<>wrlai9FKZ9Mf9>rOCt)8v~he6-wSosV8_85g?-JO@EpXvZfqpjPj<;McdfTIbu%
zv3jR#OZYBUw6nPN(tfBx*LDG;Xtj~RE=`!!`)iAo@ltO`1%COE3H37`4Sd$ZlfQ5_
z>loB(HgZ@i+HXVTf{Fy9-i|9h<O-#3)^RckaEETU`Ku{o9Zb~PfgOXa9dC!=nvFbv
ziD%h3N$ign(Rm<O6#v3@tLsX#2kJNNqmS<^{OYGht^LO%?6}1#3MW9kh4#g1SpAUa
zxZ`UM*x~=kr1<Omv-G39rSiKS3H>)SJ9hyE)%X(6%8Qs4{U6I#p7?~*nZdOE<>pwJ
zV!z?(U#47O-hJWKtn)sr_B#+d)%P~Ri}`R{BCx;FO<{rlysSEyE#W&`Vb}PUA%n?Z
zoXJ{|^x-O_+NJ4eBPV&9j1Zvr*G$_sX{iZJdxTNva)ubTDN@_dy!CGLiiDhp01%7r
zHc_YQZ)2n-rI3~1rOuwj10r4=#@!+_N3qN^&0-vF+rjB{dB!BOi-OiCh5*geyq!$u
z=lqOS8%|ZMW_S(TgiG`jOZyX>oo&iHr1rI`p!e9u>`8ZI0{8V^>^MugWSE}uE;d^K
zt;Dt84kt%6ZRZ0=8{_%J2+UvDz7%4Y$97Ut>1%e!p_tq4h`nkd;uG7$`nkGEjd-%c
zUxcOV;o?Ijm8f?BrWtaq!_S<2Xf)<8i^>Su)8UW>VGV{XNInikzje|@<)*@VYDxvJ
z_iS}-fv01tgRtXA1LPeF=B%>xg*wrhlvY|#Tcegr6Lf+4l97l8vg$O_BrA1KRM`%V
zIp&9{XRHwkJmX}M%u~5DOqbZGWKrinGp&ok8LHn9;J4x^ClYW35}A@E(M0UkmETZi
z5!4LEL&!WFx+;!u(SQT(Uo^@#28#pnZkNy#h|wdAP1=2d&?sT%Sw3b)9s?i{?jufi
z6pKV7A*t}zlOn%V`k{crLxwW8K<L>O#}emHJ*e12*kWl_DdMwilm6_HEkO*dnw*7_
zp<%6!P`gTs`V;`vd9}&{PCex{eJgUhM6}s-O>Tk%uhi&U0uQ&0L4QJqQt=*nl-I71
zdwRJzA_#>@71;{kdp)IN4Nj<vQJG#3*vc-hl5;pEUMu;{$<ngx9gnb(ge<hl`cw=j
z2h#r{9|l?B3<XZ*RPu|A#xAdlx6I>og*&i)PhM3j?SPTI2@&L)cOK&>2+<s1r~{h|
z7Q*9;mM!~+D-Po`#V;hbM#auL6ryW$p<-tZPc*qrl{{9j(k8hCq>LF(9fLafh1Ujg
z!C?9bajwg3&8uAO3S;Ode<N}XfD8t9fFM6_H`YON&(w|={B(5;Wo3ci3X=5lRIab!
z7aeWHltr6DS{N@J>fE%uQ8Rh;8r7Ec^xEl?V-5@pmdtCZ{UDR9?m7|O>k!$kiK!lr
zhr(Q05y+AWHmfL;e5PB&dYG9oN*J2=G*VV6nOM<8@fclXv#@<F!JhPvIV(z-uX<iQ
ztG3)rM?QUEc_+kFDcgyg(<)-Q7pD#a4hdXR$L2$INog-is;gY=q;s0KSa^Rj8!31G
z5x(E_7>|+TKfeeIGgrIYhrHEr!QMSA+4GAlbOq`x354V^D|to;zZ~Lhsm>=ZVB;M^
z<2F0w>f7`laVcVQBuagD{C7Z^7hZqZFfN8Lcb&`aZOe?Ljfn0q{g}5qnL2dPW&mbw
zzXtViFJ#ZBlNGp6tfuAn+ynM^8XMfag-4T&3-%UoaY^Rv&gCUTZSBzVQCq=?@LzEp
zOJ-x?R6e_zp`|(D(ka1F1mT8#J|@WInit<L7$P+#qpDCmpE0VSK<nEYfG1P&no|@@
zy+Bpiz7MXOQ_zKbM<;K-#Tav6&oUP3xIPl818qUN?qsE@2yp<QwtBSFr2w^BZS}-i
zuU@GtY*`6VYR>Tt7yf{oT}<dDCMey9>4^@|tU{WtkE>waJ0jcI`a$+&+CB;5TP{eG
z{OVEeZ>_Kw-eAGKe~v!j(xO^A{mxX9xH3uX@qcNKGMa63I3)X9GP?dfR&M9`DA%P|
ztrhO8)aqZFbot~RE|iZ@N%pWdf!d1nfRA2TNE;0ZYY+sq!(|u%PgTNi!H;UIG|JBL
zCSRK18y`afNqHp|)x<p?UQr|+B`kD;@z7t5+tLQphTG0>*g=%kC%(AHR^nN@T9I8Z
zx$Z=In<5RbEu)<#R0idM8pO9XAbSxhocO|TlC_`eW{o^#>U7KH7pHdIyS8hR_q$l0
zUL$Dk@Agmlhu^(wk6ca>D22Yj_Rq=7Eqr2~`g{Ky$mP=`lB0c#x&;v*zV=45Ctrup
z%6VB)Jj2!9{$5)-^s0l_>Tn0jr!H}pe;sDD-HX~9CQhK?E`P!uzxBN+2oKY)NiTo;
z;-tHrL+jIF&LQA<L|hi8vf*T@0ku^+7U$~bY~qr))!u`j0Th>=#C!&Z1$V<xOKK}h
zne@jQ|7yDz6)dyG@0*Ed>8h`7TxD6h0a-fYoJegcorMw@2p~S(Ra;GJE4h*4yJ+it
z9wVM$>?To_7MD~rcn6wllAU*$gGBAJGrjzGNRhLkR-S9Oii`d*7bePceaoKWphd~Z
zK`bTSx;swxvA<_DTM92*u*OLa7xLyHErcG)zud<ClP<FpsZZ^-9b~o6YH_ykvZ?8O
zZhV81cqDOS{;mUUhJUuh$LZ>y=2ph+LDq_S=Wj4)+8hIs*r&lklBc^D1hspe`FR0A
zOl@Yidg^YR_)-6u;Y|gS%AF}$y3Cj=Gsnu-T?kK?SR|W;w(mylOM9lvTdkG2F1Gkz
zjKf)XDnx=?g3MKptd`VD5J&2427|9q9;`Q_LoZ5R<s`LLyb4{5aTDV6`4yxs0#j>b
zOW1M<ra?TGmAt+I!_}obtTb-weGzGtAt_o08ot6%r3jT(g|P`Djyq)TRcvTLa(IZy
z3zl^w(dSU40sYZcX)Lf>hfOC0dCe~mZFw``_?}kA#EM91P{0sSL?LNafks|YMG673
zvmtSHd3W>2_a1vmwzrgGM$DNia#!L#w9_qBJW6fZQ7Q{7F#OvQE5wjd0*XMc%~Oe0
zB0QzOayUtK7tU-YS;7ovKf}WkN0=qqJY}3^zLJSC0U&I7h9IqM4(5v_CamEiq9f`i
zgiR|pzl!J^#Wue_j?km*Hg{VUJ1<Eqt+F)o)UuMGkB^glMG5fj<kM>7qKsuXUrAX$
zeSn(j3HFLrgCe>~%NHM4*C59!S(t>XlU(gB-Qrdy78IFC_lH@ZZ)r~<B2QOQ%2^G~
z9I=?9%ga=NrNX_+cvjCe;z?npm~ljHE<l~K8=ZFaliVHS7YTtq<_Zy=B#CdXa`Z80
zi2x$RPXT|58|Roi-EXjuuVZzev-ImeC|*+W8oV44))@ptHwTrEgxnQ$<<ZYXA{8J-
ziAOo(8J4{|VgZ&-z$@)YNKh5#L^g&#DMejz!!Tr-SBbr_P6Wm*Kv6fLl$&BTd#OA<
z|GBaq<Puy%0&D#A1zs<T@kQxdu@os)YhE~{;AM7F`<R|8+(EE&$J&j^OE3{0-8)sV
zX&JiCfe$COm1zr`gn!+X#Pq&L^|r=eG_84bzb%LN<Fj#%`Ob^bxbGIuWBhLBGi~L#
zp|;{%-qVew(1CD1w?s0pu<%RP+<a}0X7W1L9iE>nUqTA5-iD2-#loaf`XwD;g`d{s
zZSG|;XeM#-+1H?PWfvuW?D;*QE!CetiBW>RhkWxT4Zp&UoQ2QOc*8&CK#MIpn_Q7V
za$CBRKK08Dt{B)uXZUJAn|-<A^SeED@Mgx<ho!b^Y3Y}#c<m879NNBa{2Kzu4`15e
z8Ig}%#M)PSmKT5R$d(RgXZ)&RkqcL;t>jjp&;b0gy{wv{r5!%$(sKFyDckoU7qy<X
zdtUBslq*S5TiHapX;g1=IX2ib?>9&w<>JPHplTk~qi0#kD~YAF054<DUBPbp(<EC)
zx&)-=<f~M#!$55{|C0wDugK7>HACdz+Pvn^V*n&caqBH0{_QK~CnwQUJouX4DFydi
zqp5x1bLMY)Ysd2AuUfX55^{Svojd+?5%ra^8xPUOpUs#(?PneMr{V1SsgS&Va(*oT
z#(@pbZmR}lckFtUao!rtvuR7Fq>T=QsnVn0uEi!LN%$=>$~#`gTnUevq4h^)N&+LP
zpbbL%#5<KL115mlx-|JucoA6vl)@N0hf692|8ZuBu2x&i!2T<0Yxux7Q7MU}LhBEZ
zO;B6o2TnYwaeBhj@eB978IMYzjgxMt^kU&JAR#w4&TE(XY<S7%QCpL%;f&x%e_$j=
z#=1LnKt1^bEE2R>X?pIPRE7|{H@Z)<Tsm97^Q_E{|MWb%==Y80XKq}GP?~9$T@s9&
zY{K-XE@8&_Q{Lu(Kh26y{ACsjz4v$|b5CYR=dAN(PEC;gxSlOxCV%>>jxH%Jlihi$
zLOLI1`u#k;1<vYFz}6T??hUbps*fCcx0M8ZmB>kRv;G%lS3YA$9PBML$CEfHyCv<d
z#%<4yZzF1aj&YZXPd>jF90};jxiqEsR?Qj+Y1y!et=efFBfI?q-XCC-SFl+_HjquL
zLrX~*AGPKe&T|;m+b^>ypr!EpLuQlZxtwPBax&^{Y!p6S9btX>_jz^U9nE|xZ~|`@
z#WrR2dHxJ2=4<MfZ=(Z0L4k*NrXBl6^SJX&;io=5^~X7VXP$euSB|8s%6`Q&!nC7f
zb}lkgL+KAeFI8N%E6&Woda-NNIshfSYb8Tu#|PL%&%skg>AGdUFpI-h@x^C`5RWzZ
zCu76MIta+>Ld0=3X4bXnJ9agM+7h3XWrSO+Zj-YpP>02;^k<sQD!7lCO605HDV8$k
zc{+ZUS&0&0DSQ>vDhK(t_<1aagV)62?NN#HU%?xg<X$ZcYl_6w+2J$#N<w2k&cj9W
zYr$igA@%+cX4FszU=<@iX}5-`Bvl8@GG`>prW8*$ohm>95iA+)R{<z=3Hh2N!y95*
zz%opNLXs@VF+LLboKu~qe0BvECR;Jk#e|}P&|<k=K~aUM9GV4?^pgzf5r9Yd`7W2R
z6Zip8b&Ju~&uCTKeW<O|psf+BQ~?UY?d0SNR4W=iI*Z3}){Y!`vYvhn2{bPgrWM{b
zL(bQ={4Dz`DPm%tA)Y94%t|y4U&WX9;ASPbzQEYMmpt?bN$Dzmw)=$xQ9HzP;-lLS
za<-#-&p$F9n^Kz{=%hssej#b={BEALiNh~K=st&gL@pVsd%(10`b)T?pRy9f%y^I%
zo*`@>wT8I~`jJ_D4miHX=)gem1K=nH36PGG?Qj~^`%AG=T=SOLLMC2F#`EBcCk*BQ
zjg}lm>Q@O(vl5r!peCn6$v6_BWW#i03l9OG#du}{<_B|D(A<^FodE$*WhzL_i=qDD
z8AfW1C0V*@Uxd}mO}-)oaW1$}M$=ZRN|`dMQ0GICZx427u#4im&tB@isE|#<@)jrZ
zQgR(?f58*RJY2>y&NHmqU*^s;yeDw<hb;eUVve-R5W6BJOj#N0%Ve(z1jGwSW8NH;
z=^MOWbC?cb*_;JB%LuOh2<|qW$Z?Oyqv~!`rmIxR2wuDbAB(2w^oI%F(c2Nj!!Nt7
zp1_hLz9B8+;?|D1o1V%P$9kP!>Q|jQ#sDAFFR!K!zZ>SBrUaka=V|_NH3^(o<j($Z
zesxT!&7wi|c?XB>xnw|#{M98hJo<vjhF^B^E&<HYJ0#pXlaQbAsL?9BU&8SizYXSr
zoyo%c+i)z=TeT;BCmdN>DgNf1a@K#Ixz9&W->L+6JA^>Zm`Qx1Ns($ty&}N}Ic)3^
z<_{a!QM`co^W#TH^TfS4nB6tEgm|*wu?MG^K8{(Ty#;$Yf?7(r*8O^$Dc{Zz!ES4u
zuo70d@OI1G8u%L*xjB6LLa^m!+i0Fvw5o(5yae&X(JI@XsqHzBG=~B7luMa~uO1U}
z_wov+=b`#;-?Pm8=YN=7z22Z<c9!&#n?F#Yx})E0&WA7jATL6FCr3fLhnjx@LBl}z
zFlx32a+-ZOQJl#5+b_sbqjUR}va8Q(yDz--2U$`?FY#XlbA)4u1z)*e=i3_TH5Y~A
z=ob#+Gl*>JlZ{(Iy65Np<fM0LJ6x**wBxT`3hpoGlIA}=!&R>+P{n=c(F=?0-+l%)
z^n=0L2QG%q*Rh82Jeyn(?i;iF-@j^Yc3YeO=ZogEr~Yv${clmLRW0Dd^EHV;xmqIT
z$3>(sWQEgiYbq&-B_FZFrWwUgQk{SGk0Z-5q_06z0X4C+H2t$|M*lDslL9=6mKJIJ
zL{wXy-FH=U7JiE-!$@Wm|082NjskqmXH(PnFm!A<J$jr^7f|Z1FS#nv3sGOcbY31R
zW1zcV8z$gqX>Owy6Os%HzVwpByO}x0JLW!Ld&`VHwK(lkbS=03r!4<a76TyhKgon4
zJU+r$eVA)S>1v3yl%5rA{lt8>+}@LQvR9D^rIQ@{bi>xZ!r9XMuQdPL9i)-`Jd*O>
zt`CGi!A8YTo|w+ov|>JS*a!FU-udP$_vTIH?xeQ1_etA<`B+kYS(^@?50~UYNN`lR
zSUKdXLHgs}1Uh&h2(*U^&L_>UQ>&^GilsnXk5YQ(W)`+jg423&9B2LLU!H?teh#0o
z$AbMGIox1gTaMdW`e&?dm6XLm5ZSWfkD#_9AfVl47RIG-ACJ>Dk&SRwG+pAj?y2<b
zc8xcjZOpOjwY(6nAkO0Qr|ph`!fQ8L_es4TJ2^V85oPIddI6GdW|yJfaMEM!>wHpa
z;}!FDyAPM;G!QG_w^*d?woZg}ZN=u(i4cmi*{1N^VLLinzBM#D@AK#RyUgoeXit)>
zm8$QUxeT-08axy0Dwjm2{_yj%0I~}hBdAjuN?lrc>~4n5AQd9(DexMn9)YDpd@^%Y
z&p?fv7IKI2DAY)EnU(`^=~tQsS!mLOAjJAxICea0)Iuo(b#hp@)sHH3z6h$Ytf_k%
z19nT-NGrfHWHsRRgWIQ>U3>Lm1sRJxbUU<3V*AurelY-R1!9PLV_|iMqqHl`BxXbO
zvc>Q=_$TH{26xK~aO^a76W=_+?pCyFOQDLii<$U}&Mv|74)h9f7Mu)3-JVKdUTgP9
zKgCqe8MCLdeIYHG&buhuLrnIQx?yAu=i$DBVuaznWy2ATYAdKtacB9(+EB+WlOl0d
z856`xYd6*00;>j8zKk9>@O@F64@zSh>`JW#y&w20utDCAWhjfLDVm5cr6i+GwqV{x
zUdX#-pw)%Nd<~I0F%%L4n_-=(mU-4+76{j>O%XC5sAHKNF?5E21LvU*2l?~`SMVlj
zEz}(_U95gE6hC`0Fu6Jf<zrP2S*Y}}#!*~rF@s7*7UquukxD^bbxkbNJ%XMQreqFH
z5*`<0Gz7L(PavZQCv+h_!Pf}#hjjPHt@5p@1dCZr?vW=<d4=Vw7ehiZ&oLzUj-^t?
zQI{l-D7$u-)Oz5HEr%d`@s@;j<v6+K*J|;6IB{&zhHGx8N_lH|B`_6A%s*kpiHBHp
zVKLhJ8BRpwnT(yWGKp11px=-Xrs8B{b_;qP+wIt|rN|(Qf>4wmuEP=dy>Ljybp?S|
zIE7WmNW8pUkgx<D87+R1B0UC`p(CVa1-uXlHaS8+sdSWUZpvz(#|tzfw7~z9VkcA@
zQ}EcYMd&SIuJD5;e)Ig8j(Z+JT0PwV&)WOIS9Vl)p6A|orGBlJ?JHSs%TC8G$+D3<
z1|BwK9dMu|%eL&8L^x(JY#`5$LmY<eHXHu*hJPhl7-9S&vd1LNB-uP0C+Tq*reQp@
zo+LAKZJcaR#xv7lfnoTN`3N?{$6*Q6nN6||Az{D2s{5X#Zb|QXK6|8BxBi?ub?VgL
zQ&qPvk4B(=(B-+vs{CD7LUQa3jt($F80qL)(@ROkfTLu#Qui*UvmYoU73b$7UR(9@
zy5y)hkIEt8GJBTyTf>DUquWA(5j&3_@l+o4wMJ`hEIT~u6W@xEDk=4YKqPeuIeE6o
zX9M33+`8LZYOmqjt}r%vxghjrpKW{ypZcR4#XU^&{m1ZF_FR4ZnR3?s%FxvkO5e1D
zD&xtl>DMOR{*^bflt3(i4<u8s9=u^@3CEM+Jyv*m+wC_ro1ItZqyF%;83%N&T%Vri
zty}tU-PCy<2`;@hSm#H5lJuju@vgYR3X4_jt>?@&?e23rHW#VwY20eJ6~8}(_CEqQ
zTS1hSxwxUV@uKc~g<DZ}wwJ^2nh1&=&jPc%>9Fen=~#YgGvfehUhjvRDMWfn_|?BD
z@{F%F+SF+(C&?}}e||a5>B;Lr(2To!-yqqF1BLawtzJ<d`o8IK^>M1(+yx{40oGJ%
ztq0wL(DoBK7ixdp+3RQ#$DSMJ%1+MDIzp%%{h@Pw%+}_PTln&=W#()A$G**nY$~#$
z|FyevzV$&!>kXU>$e8=Aea~0^Yy0wc-r^%m&+~5Ue|ST%p%2)kyE|L4>;db5)$%9M
zW`>UhJOA+&+IrD!iHhrF;i@{FJsyio?(55$`{Jc(g!Ks(eh`p;QElbz*YLS|!9*du
z0)h&k{GZp-(QRSXiwRElTCvm`f%mZ#@C>TmN<^)reAOu%?bJT=PTgbVgwQ=f<pW~W
z{J&luSkF*f9X*UwEH*5Q+5b!zOx3cdKj<NvPKawuH-GuB;BKsCvlrb=$=kiDm8RyR
z*n2=AOo+_6CYu*bGos#qnIu1!e}7(<Ump)bu*d!t8C$t%s66qz)0~M0;Tt~;XAAKA
zH!q#DlOMEB`;G>yjl2as_SrlSc6q#+Ytl*j?>(1k*X{HOny&J1<167$G|$-+0_rpG
z^mFJB%}*>j<!uYNxb68?W*kql8`u|yz*s-m4)#{{gEYzr0S(kQQ7k7|KMZ9zfZSQ{
z9?dJldz}-ue8jt#<40ud2}-sHUqJ$G_I{8`^lLSIX&26QqULw^KFKCQgG8Fk*Vuw~
zTQ75ELFG*$PLEB*<aw64)b$xVKppbF3hz;z(yjlNy*~U?%cw?V;Uye(^B35<|KDvs
zYvc3$tKEn#<b{2Af5<m3C819>#)~MB$6XOGNKr(<Q5a>ToXAcDKO22~Xz(IhwC-Un
zG5-uJ^Jf3%$~~|UJ^aq>fw4UZWY_gslSOsfbv>~N)WT}nvAhx;m{l`NOmFVe#-M==
zCBpzz_<~vBmKgBk>)DBwQwm6lcTotRp9BS922exjTKYZ<4SuwWfGVhDQDUZ-$h5{n
zvV8&%n_RE32WAfl!~2&Il8u7%HY~tM6mDjfGQS$R>tLH@s^{iF{UcbsOSG>?WF3{p
z-VoxBAq`_RZlxrVZi(XI%ZUmX$Mhu@<F#yI{kJo3K`v+Mi8a3(BQT8<(>YXKPYXFk
zcM*w~s^1wuVutvTt!wG~6lQi#@J(5^0*BB?X){Gn9^#>#KqKmiKIOn{Ik<JU#I{z4
ztt9ra*E^QF<H@DyS`hRhDx7O{U*==QjwY8ws~<|TyuwAY!<cP44Vt&xkK!ANgc!t*
zrd)A4ALHcSZDu2(oNc<IIo^o!jTc(^voX3p{krpr7ceJj7Zt5V+<1N|qee}xJ?bps
zB6pG1Bg&=<IZ&i5@Q@3@buDu231N>=dRF=XiqGwW6#bhI63RrykN5#r_-jh48|<b<
zvyDmrsl<Thii_1buyjRnk+w4GVrCNt!+R@znG!etK6+<-FLu<n4Jk@wkr(D7LJ?Y-
zu=~MU86`+uwUhsUAc&+VKdDGP&n|R}xK^#<xAtM65g-+>XAe(~|9<F_iPH8poy9Zh
z2`dXSlsc~K&%_wa-2rW76$4SKOHzR-TZIf2Yuw+(uJ%hw3ubk4Rv;$$mGh{sP9B25
z|9+lp0cB5AhN%0VO4=8~Nz(J`AN#=|Z_7Ec^1WrVuVg)PPS)yP%flzIptfom{wm&N
zZRV$MMr%H=IokNM61iSix^zj$c}11KHD{pFT<MZ#z}y>L3hpo$TXyYX@3)}Ko@dV=
zU@=a!CA|i>kq$2FtBQHKINt6o{XQei@&di%@CXtg6wn=t<!oiHVvy9S=7YCiqdsb}
z^Xlcr1E(`*om=dImG@Ad{$GOeY2?Dp3<G#>jQg1m*sA?y&Uo_%8)o~NL3b!e?FyU1
zJMr(S9p9wF-TsQPh2>XfS>ZyAzqc{67VJKftKOzQ@C*=j6e#ojbmdWhpv>HdFR+hX
z`&_jch*;5|%n*$Oq@KO9u%B&MK9g}_TPn?wyYFa}9<9d?Jx_JO=dP*KbIeVdpLV~y
zFi|T=dnZk@Mv>`ao2EV&801099>Xi(+E3Z7QCrsT?-i%B3PI5jex7;A49etZA9T&u
z0~|2Uc++)ZicAovFL)B1`6d@$-}w@hkoPrx^>{8e%EvyKm+tiCnO%8c+Scxxr=`7W
z$vS_z??Jnl&(W$C`~MrgqH(dCT>9I>tyZWDWWRKN%vw|bBsTOG<XKoge|)y}`);xG
z@Q`I!9WKos&mKv+BX~DpaxwMOpQ8f*7m6<?2c}9=9YW9(5@`Y=rBfb#0X1>>(9vuf
z?bL=PQ$V||ANt(k6Nh3NlyN)%-$+BHsbI1MD!Z+eOI%KfK3X-<A>o05W}kAf;rTvj
zcefS4mg>#u&pNkpVxEAvn5G~nmnnSv(GN~r>sQFtW&0PKSN>c+d*qe_Hufk*4$5F~
z>dRRswbefLs-o?_ovkhs@3z0nv-MAp=i#0owCdJZSY9B8{U;th=)*^tIgsFlBa!ge
zGdaiJDPyGt%gwU#OPzOcgaee^nRS+5hrmvLFO2!W_<>kuR*_j*3stdp1Ezn^vCHr<
zhZrAwd87rVw+YFAD-=~DY<2H$XQ$Wvdl|Ez-GXxzNo^p>2&XB`FZ>{)>um_C%7lG3
z&aszOI%20o!Xw(`<&><q7Y5&+>ZqIVK?Ogj-o<GCY0`h^O|?vpQ4Ipqz;I2o&6_uV
zsr*G^ys6YQb>KoJ`Ydf??0~oM=B%){&&T0&X^2nSJ<eA)ZYOZ*wevMA>zrtrj*SNo
zfA3xPz#PLkyYO*}1j~Fa2bH^(&GvY|IG=5Pa^u&~k*J%oNOX+47rdLLA_tvovz9$!
zYu33T)Ob!$RsRS9)6tUn^@kSY%!2U!cHAb#qzkQLZz<AEr0=_FL_tPvBgXP{KUhNE
zBEkz0vd9wctSE^XB};g0)*WmBDh?fjY;e-{FQ-AQa13T}=&sP9C8jn+r3w7p?M#b`
z*y`*^Hv?6ily`}{Ksd>!2+`MZTHj-XKn;@D-|H3yxT0;o4&38Wu7H-vBy&6NV%ND-
zU^i^rv)v-`P`_>)XJUcyVNY*p4jWl5EG~{&FP9T_2&0Xc4E9$~M@)>Xjm!@U5<-4%
z7_;dum7zr;!_WR<mU;;HCP`BI!74)VVl_62pjc4I3jq)EGR=DgBK!}B?CuzS(dluA
zouSgmv!3!ZPjUsWkkPFP+U&7X5FYDP&{6LQ)4XU4^Inc<7=30hRK7cckN1AX>J)ZF
z=z21G3<#5Sqlwck5%ju6&JJ@fKMbYlr~t?1F7K2npu046pMhV5s($u=C`o?)+~F#=
zN1QGeprTf)Ov6D|bdauh+Z-{RzSpV&MmhA(VZIP>Uf8ZJlcx-2HKrlz@?aq*Uk_wj
z>BSICPr$5Xu?ee8r^cG*R6QAkfy{2g<g61Fk#odq8%N@bmIC*H75h+1$HHz{>k1G_
zUt{iuSo;S(kH?7@9dZr&9*PxSt~NiB>t#u09HCu5lQ87yY9if$J)e>2E*LYEn%hrB
zioH7zKfM)mx<%e1x6bTCJ<hhG>}H==$>^+u8oiJL#P6bjj(2dVgtR=TI#ZFa;N<~0
z8JWj${NngP^}2&vT?GUZ^AhSDJs`p%Q2SKx^+HD<AT_E5+r2)fFAjGG*IT>aIegRC
zzZWLH!$=eMA*vc4I(L7^ei?QJ;lfq%>+@%MZz}q{ReWDZsc&?n9K{1DqplmRgBiZ8
zH1#27Eic)d_7(KOrC-JGI`plLW$N5-a037Ho^RE2z1I5oPcy}!IbD01`KJ_PU|_=2
z<{Or%t<ENHKVLb_!eKky_*%C5I?Z!p2E%I}q&LX@6uYf8>HQDo?eW^qwkI3J<)STd
zT*Pi!8{w2`3}O+&IHyPkepTxw*EO5X4W!zQ7jbqnn&tkHC#V`nhtVq*<Jw(9i~M0#
zX?y*0Htq%h|GIr|Ua_TT8nvF1qO_koz(x6d6H#Q-ZY$6BGg%y8`D!7x3MD7F(`e5s
z+3s75e4{>Puy4}h4pe{YL3XmJHQ3v8ibX*4+UKV13%|qx$KnGy$`*D0^26oip$~AS
z?@Wf)gOb60zIN(YnawVczEi{jAa{QWwlt{bcWI4}U!gep!awDMjwe{!<#MTznkz?2
zTc5g&y!G@*cxVhePCp@t(>JB;Pv5<qw<1bA%e_dAJj4RZUpbWN-0}y$>&vM>i5GAX
zwkP<q^`@cHeyG8B*=AA+MtrylvPh#ue=I|GDfu4+P&7*|Cfow@{(3Rt$Y0Ev{aemf
z##(|tt8Lh&6W?<AvPeGjKdnZe(QCguH?wVzJ^bU;_Jp-JAl^ciA*!tuC2q}};^KxK
zdgl!x?zZ0adRpy<=1YL`){>6JTj7%<H}l=Ur|G>O_3N?r38OEZU~*JVGx1QRoc)uz
zxM%a|8*|5QYaSl{ek<;NnK}E-i+Ria@yp8aPO5f6opWm$YU|xBQ<20i&o`U|GExS6
zI<$u)XHBQXulzZ3FmK-9M}Fon2<6y+yMBNv6Zt##T4oV9=L_~1wCzYMWm;5mpGWx|
zHE(ZwgFP0#`WaGN*;ExU1>Kj>KaXzFc~i7&w-pQpd^Yo#-spAqC!e3iy^*=@{%f1N
zU~{|%0-s*p`u0@BMtEwdv?2ImVBnnyey-`6T{~<7TA9X{iP0b6a7pPpIc-Cupywg!
z_l4ZgfK%%GMSQCjwbUpRTl%<pc3Wrc_NkfuCuVbR$M2)~KF9|}zDnr;ud@ZZr3aG3
zjFz6V|M*xlTcW>?oC)!s%v?1$7Q!oCbI7$gtN9*srMj>;(0lXNE$@-offG0S9dI?R
z3{)9wUf<<n2du4LO}a53WlB6-iLwn3($uMp38Ggtq8l!Kv~<{Aj}}DAfAnU$F*vx0
z>Sf0G(doKlkrt1d%VeiZTX~DHT6ktEr<e~Y{V;HnK1H_$B9VvSC{@LFJhVDoGePyn
z3Nk_bC*Uif!rKN__IjfDo}VUh4v%HUk{ZY$9CiO5#%`9INs^emfKUE8U&iY3vkPkN
zeJ#)9)Um)bI1HepIy}TC#;jaqaMsC^bP6?UFNdQy#8BKXv;V2|JbSka8W{9~veS&h
z(>?THHS0L9LcNRBGbN}NToFzM<R(Wf-3H*W4-OvGAhop;0ZJs*%0*EKI9(o4pke^&
zva72AV1gutx)NRb+)o>|(C~#?bHS%EMCuH}%i1CUF;>bW<t4fL0CVPY0i3gONn{fy
zHDewCU@L@b2WkZ5MOzd^SF1C(@l)O+v}FdQtQ>^sLjHpcBVZ*6UeDoR?2T-pjJ@K(
zV;IKrgUDv8p2i?aognb85<~oENI0dh_<>(Pa6$;&yp(zKreWo3e!OfaZ+>-cX}6+1
z=5>fv1RD~O5*CD5vv{mW2TazWd&nwCt;((VV+f_F1NV3oQ8}Njx#(7=vm?+w4RC@+
z@pR&x(&>^Yi*9wuU=N_^QZ3vpQh9e_rE7`Lu+7!SQ6oEaD*z!#4qa%vWYZ|#%VxkY
z$hqRBwQ8*h!QLM`ZH4s%Pa2FYL2D?Z-PA_NphlivD)du!Guh^q8}nT(D<B>jrF!*{
zV+T9j!J~#S?$yi8lE#u0>T$-3svEe+^CX<L6Zx3Z*{CO*)q&jGJC@H5+QDbhUdGvv
z=Q9<anOo__a{e7YXtz~Iv3NZw9(s*P>Jh8lt^xI{Kj721tu;xDhlDRFLP8qE<dE={
z?i?l~zqbv0+`b7v?P15KN|t7A>4H??*)zc=&;4lg5x1T`##vl@nZM(yZBhF<z68P=
zldSLutUuJqsI9sEc@b{M9pv|rX<OqDDaZ{S1#S=7<hOps)*UL4pg6TJNGCOR1?+GK
z{fxcaMTJbXhmpg%md&oI10U-&3oyIs2xAurmVJq?=*Td7+cjt4sANRq=8c9e{??^b
z^FiPZuW{^djx7cuKQ<M4@L2tCy}7tZFTK`R472np3=&ZlE#hmiM>-tzx$`9+wY4as
zLc%65(ii|#GqtPt)Yqh)CZ*pi9s$+wJYCva>q2g9K5W+MWa;IfH^1K@v=Pg091r%;
ziiPU!AU{SNr-*|<hds0tbH|<C!I8toI)>ENjnkJet7@~*LmJQg%V6!d-B2{=*kx=U
zvBTBhHJZ~uMLnYkL-@i?Vi|pmi<I4qugbVPSDXQl>f_d{tSQ`2ttlR7d-u`hEWO@d
zC${q=xU1o8{8coV=dKV3o6ub~C>(x`FTOfYO3Nm~&NkH6=2iDFEsEM{!f{{Cvhd=U
zlF9d(pQDx-@++6thin;yj4ZXKx7qmf<Wd`<^68$@-Z_~weG#GRppVIJ*=<$5vB{t1
zu<#=*X&bh;r91K4Nb&~48>4(6A@^l_W+)V2q8cIW!QjLqliZr&b$9=i=3|z#9#ek(
zpas#m^%Z0_KQv~OkLJAbO5SdtDy;Qg%6sUC;<@H<G8<tP`BJ8O9m|9LXO^#9Hsloh
zk6vcYV}H16OJA}nKhJPh-s=~XMjr@E$7rO>w~+SBw@$c`kQVZmc*tse%hAPWUjwzZ
z$z62qt-G!M)<!Wgd!NhW3gl_>2^kkggBQ6XYH5Khnd1KIvCJjC?I<N)Q3YNI_?Rqx
z*EXoWIO4eY$g~aX*wT%8v+#?B&A;eAT)Btea3p((YIbDC<1--m84$H|OBTk%dm1rg
z>y#a8YphT#2a?w%k`3?WvyWfk#k!7Yzwh3Vp+w8-a@Lg^WIx#Kl-U<Dyx&$Y=Z`jK
zn*P@y_xG9S1zz0<tl&v_{lGu<3F_v|9OVB^7uOlpXB&7pAG8WLy@!u8(w=Lw7e^&=
zA`3C#Ve|1B4LbN{wu}$)^eJ<r2MY>`^*^HYHAI%Rxty_eJBV}Wjx8|=%HnxAH;Wng
z*K<*E*ZG~|s|h?_IQUSIY0+Y^b&y@J<;89*U6-o`>Ijkmg3b@l!b{=?+$QbDr-Fuq
zOson(^iGy_u{a<3mve9M$^=qOhGGIWLoxfw2eaAfS^HR4*SP|TL%GXa@S1!Y!CR#=
z>(cKqVWbpzK_6aeO^BK|H(PjMjXB`E^#ej1yd)A?_;s^jDNAlY{6u@p8lFjSlx7q^
zYpqO5gg?zMj)y#75Ck%Y9EXEX(InH9)3z*)Hb$(T%*?#_%X5T7$BVxpT<`R_QOif)
z7b`^>J)+t=TbHDB=4Oa8z{m=%X?nTDhA3}=K=P!RXPmD0SOTtounwbvxh{WjUyzAR
zQCQ&*W?_VcbPEEEW~>&JG%c@gzCfUDP#JFMW$aXddDxGNa)_ivWDg+O%&Soh!Ltj-
z5<|+9$l)Xj<m6<TLq*Uz;3dty^*NN;BESWHIgfRc4sy`GtS?*%22Ir54Louh8&y*I
z4T?Df1?RDh6wd6mk)}neLGdJVPnz~oPanNrM_MFxKZmc#Xq76cn&r8NV;q5Kir5#F
z!ejiLFhy%itO7~({AUA!ec|mHWtJgT2Qy%EsfHf0JDBC^<&fYam!e*ToWZ7$PevWW
z3%h)%*v?04xcdOfCNa@-jd;;ojxjP!3Bt=VVl4725l;6gk*uS~MZPOyP_A~a<_t$)
zsOm|PD!qd^v|Ea#`W5g|B0R`y%x#A2ZeI_rv?X3wo<kt8tUjsan`0_9E4(5p`^1_h
z#B=sm)Iovy(M3`12jes@je6iY;VSJe9Ky08$3DDCZ~&llYckLG{J}|SM`DgdRur1L
zS5rM+9s@!n6n2Pe?UeQrM4>-?<i;l@J4nJLd##zy0jUL!Ln{GO7ZUaQOYL84vq52p
ztVoFr;Ye|@jM#jP8zl9<P?<%<tKhVqonlcvMOh-#L3LN>q}o}_$`ecmtw9|>WS!QA
zm>H(zuC?Y|)i^O^BjBE}A_OsWl?_v?9oN$aeSTu09U4t*==3GIs=_{B3}fFLNCHG9
zXWbIqJ%Z|7A4n)NgD?vjHRL>Zr{KG2NFqVcXZJ|GIA@@2O;$MD_;K>tOhjz;;LM1<
zfSoNh6)N5~2Ar@J)~7~pWowj3{8RY+COrknlLFofPL3|;TLaFv_r(gEaonbLFI$;`
zn2z(&Qq(>o&^nr~>oD^k-_5)S<*KFHpk~b?t0TN9l*w%(!@Vmgsfy67fP5=-@fg?%
zz&SxR>zJn>Db$lFvE?pO_es<j4vRzybu<-a%-af<HF?r5^&r`N6K%7~O9n!4vg9&c
zjTW$X<H{=5>BFG%-wjGAXhtzX57JThFf_;|87<0$yLD~W`^=wDcQ~T%$FfeIL4odh
zHfu9CqPP^WlvhO<XVrhgxdZI##`)7wnxs)c9c79=MhNtQmJq?2rK|NB4o$EDFJma<
zjqfawY#p$KXUHj64)9|sG%(b)hbtdIijo~bdQ>_`QN+Ki)}Xc$R4n9wouq?;SiIxd
zuT7$_fQlse&0=^tbQJrJe81i)W5W=S=&SjKW=qkbj5ud`;2Ae2oGg7Iah8(n5hhl?
zC8qL8^_~+;eW9(ZXBs{*dYuWAGm!$xEGkGzC`r3llLNs7olYt5khxxBVOc@_Ks-j6
zL>`fR*8{iXdIPTN&u(X3mGA^EWI<9Ma=3&3BQtVEOEho{24c7OqTRZ~C60=bkU1+V
zf@rD*#h1XV4%X=;ADN!cq}{TK5bgS!QJYgtJ{5&(pV@q2jz@ps#GLSLc?+uBV((cK
z^`3KgOU^7V(Tq40Rqx5vCblYh1Q}h~JzU8pm`)F$9s`>aVi&qZqg%<VdtXimm+PCL
z@I;8FJUP(a8gqX2k=9c47&xmU6EJ{d4!bNs5zN|gp&y4G^Xvexk_f&w*Tw+iwWWDi
zHp$OJU=%jFKtQj>o4PA&o|6K(1~bac@%80cV72!ykMYDzY%oqZUd9&i>Hg67Z)af(
z!Wq^-Bf^uf;jSmHg&8_Mof@JJmn`L4(}cHrX}NBq_$(fvg$vqB<T@(p6OEFMoHFB$
zw)q&+$Ef3L+;|I(@bo5aBBG97;>uI+%0C_+r!0H$Rl2G>E}uH#-^Ubo7Vp4}wih~(
zg&Q9dl$WtUb=*bA;}APCJY)9izzv<}Pze8(UTEo3EPrh=quItw3c|cJb8iuzEl`!;
z<t@CDI_T%Tt=%$JL{U|w;n0C%OkxcJL#_20mT)EM|F8|8z5}--ukl>n<ku6~Z8$qQ
z4*i9<(;ZmQ%6+_Z5zh5>j(gryu6f1awYiqW9{5ctkt5GfnT9&n%rDddynNwZr(Wdr
zjX~W@xvlMiv?DAF%PWXv<A(=i&!oLk;WwUZWcj`9#+B7mG1-{6BOUGy`fW4^-feoy
zvq@r~`>EA>Dy7&1KzK75RTkQRlG)JDsxxAd@3Z4Rlot~40lLh$WJOW_evzHJeaPqc
z{a#Zdb>XjH;_M$im(9&70yJFQez3w<#ff>sht}*VvcLE;<6zy3c)6MSj)cl%o%>cn
z?+fi}HEWjNf+6=SAZJ@5#2poc669B39=j!YXKT>@(iNu|J46bZ&hm&`K_7cH{3?=O
zyd&VTXFK<z$>DMEc?Mg2^s*#<;iXo+=~L*_coc&s8)d5<pU`-56%V5lTND(K&pgXQ
z0m(KG%{MnUmcH*e=Qw`#Rt}I(d2>TWv-zhZ-WI=F*AGSR1I=oh6hB(F?Zh82+is(b
zlHumxjQP1+X=4BU`zYf_;b3i%f<Ji^oZMD6Tc^qpriLf8;sXf%dx$AY>gTPx<wSmU
zamC-JA$nbDFZ>^jN?dtlzYCG(>)~vi^*Dv}0pI>X#&Lbld!1n=fSsxwHG?imZpV+Y
zpz9r7yBno8WBkv}Y{Muv;GBz}6VRzBBhJ2(`gI?-ZSc7*UBStfv-W}fIU(yKNBd<N
z4308#Klx!x+eDH17_XVVl_$xTHihNcnpj7N5nmshj}Ia9EHX_tCtByafWJDAzEIkO
zo{U|^@25as8d{;0=XnDtv&UOp=kha!RlkdP+rPX%5l<S16_}f)Aa6g%+Q<Erg%8$=
z#P0TZ5wdb$@=<*sX^pO0zOV2TpJIP5R8vn3YpHAixZQq+EUeGC+0OQ&Anx|{M>ha9
zp(G`-m$*;SyiRU3lfCG&maBLH0=EH?i=M|BVLksHEP;z3@IEs}O-sqT!l91{A@GaG
zaUOB9@dG9`iSg0;f(-8N5&p2zMggtz&C3$VNmQd_IIci-@k*@dPKt#V!DEga5u%i0
zwZaJa>c^*g=#P048pGtbD|B`ZAs{G`l;vswT9H&`-mgUNY5!tNdC+aCUt#B==GB`#
zsn~ho>9QmX@{8E{^R8^PBWh44qYb>hKserV%Wk{YN=`b2t;oK~!IAM6J7te&uBo7z
zn0~`4npXAWEVCQMomnfo0lPfg42-6nZ~{EaOA8Co5SbKUnJb&ap_mZ`>P-*gy{~fl
zwalrX^i)eUetaUO3X2Vg#85D&)0BS3%eN0W7IgZcD7bA99R$z}!&1YCP5qEq>cHD|
zlL*XF0&dfWKrAxGQ>XKE<iOhn$`2Wd?#GVcC=}8MLL?+4K3TbNCh~fN<$<KH>ZBnH
z?g`yx_hrFdjz|7Fc;Lyc^Hh(s8WJHpLZ|kn3&+No*y2IoM+Uv#qJ{O$I?4dYdaAYY
z!iqGc;N?J1wV)=V0_0N~L?KiiJ4e6yQRzWtzi^3#jnN{w<sSYXmXg}zq730nc@7cz
zj0EME0%GVMM!~T?psu%@h?7jBqIxrnUywhEGN+FadUe<(59X}Ozg+7zb9KPZ4<SYf
z^!2?W?s_^@hWX?ueb*CidiHZ2zEvQ>5sn#W%Dm?{Fi39ph*ioHD-Djn)aH~w@n7p-
zvL>iHxmKXM*{kJXZ8VbM^+NlDKqt3il3l0Z6_Gj-wZ(M>^?`63Rdt4ZK)7k=Cu~)Y
zXjA2j8644#C@HXy>EB1(C-1XDFS=2b3C=^X-*qMuF1`WxEa^S0yQ~GJ>gTicQG9D#
zQJj4hMY7U8u}9rNZKuauZl6iD2Qr>t0(X!GcnKZG<HP>S=%quBOUq>xXUJ^5sSag{
zkHG<6#$d3KA*kO2_gL1n)1Ox5ncxl3$=1^4#e8;{04`e0?Te1y>J|3l&a23hz`c~Z
zeHSAC!U5~ZWB6Ib?=Q~+$6n?$U-uW`<x|?{aW8N2QXi{4oFwdo<5P;TH&nChOd?QQ
zefA%Em@#uIXmkANOi2IdF$RI=m!|yJPUL0r^dU!olwg^6?GAm(a*xxaw%WuutO#Mj
zDUpfxUw)WWzG2nV%iIKu&)r9s4m{=WJlE?jv{vGVn0tZRi#H4QTd!H}CYu;1VB?!y
zSgMaoE>)GSh>Y~6d;T#ur(8)y&btInwTeeS;9Bd12cabS%eE^t!=E$2=q6P6EY<PK
zk*0WE|DAaY$A-)NfybMfyMKR{x4vkr%P%X2Y~nLXq~VXw8?`S}ldA90l5!$NwY5D&
zi=-*Jz$LUwf9-N|RbI@@fWE7ITr;jho4I`<JjL6c<8Oz!`x%h8=B1Zf#gzNg-wl0f
zMFgp>NABQ0Hq^wR_t$`9chTK^?B%{0j}o%V;0b8X`Eis~YRnI<EL*O6lMawxYAdW_
zgjFI=i`qb-tcv>h)b~f~iWFpsf&!=|sdCQASINHWG#|cUQzyHd3F!34xJml5o4KQj
zo+F|NtsgA@m+5#vORPxi?|hNOH+t>Tg8ARMi$pG1u(66dvvv>P5W52@9vllL+pSg|
zM+<!W9UXH-2w$U0=^~-0pT;+*1Jfc->}n6ay0AOHMbmvF*BpJ~+w5dN$x;=}?+v3i
z*8agM?wlI-R^D6-Vq27JaBZ;r(V2AH{C9Uyn)!EWrWNnE((%D1m#h35?;d`IZiep_
z>GOsPXoahh36SyqiaD()PUfeXUxa-~`np)doR0HJR0G0M-u3-@gNg7ZTOx>`qqs>{
ziMX0xu<%zfG)!mIA=KYgmczxxn%Q}r1490&tF+)5L^MA^i#1ks@38Tq<HMa7w_n22
z%PaT4EVO?zZ`<gDl-Cp$faW;*g$7e87y_2;#IW<qe)07+IC>ZT2iY$SR+}HS(fr1F
zT9p#`c<AH{So#*Ln{T7Ga{7W3J)IeKWM@JM^#FPHMC44==!R#3xLA$0WUSH#bjCYS
z-pn7`@@-I<FrT>0k)}_BvBU4b2ZoX|mF6m&1Y%e0>b&{rACh2#>tW5-woQrcB#a*V
z8I~^Ys-m|k%fMDk#9^&WZ%hP=E5RZU35W9zn34uC+r-OZS>absKZNP|0WFC=%TopL
zj;`4ENF|IN%??d8UsjOPZOgI)?6)t(RCfqE)2o7>8}{j<i-P<BnvGbc?BuCnJ3Q6d
z$Zf$j{IuOme)L}8Dfy7et{6P-K|$1*d}KjASaQVUEHp_w!H%qMob$2wh=>iRO4S9g
z2sg$#RBUuz|Gl4~shOmMVJWYhKteWUtDeH+SXJiMtq9#Lx!}6i7=d^`WKLyV1`nZe
z1SMjNh{EW)o7dKiDw$2uM8{4>03A_=v%{3f8kk{Qb%Yo9eyQuT*Rw5wHrkyPkdls=
zu%A0p7cbxU>Vachg5)zx{8|=rSNl*rvb|u?OL^T$HC5v!#hhJiRjpvt-O%+I91Qez
zzXZ38aQ8;$j(1T8c#fz~{mq<Vikdi<c)pg3<*kDxJnvNm5^XjcR>gu#Bn$IxRBR$q
zl$sq?(Z6EWYr~O$uOM$Te3v)Y2Nw~f5H3X9UWN;S1sG*zItVXv6>}R6dG(+$*R$_w
z8TT<53T`L789cqV5ZmT`7on^zE<e0A<#so`-?Ouc5K?8LjNGQ@rY&q*sZjh&m&mcS
z6;L=P=DBPy1QbCz@QjlQ7^5BS#W50U%`3GqJ?GjOfDiNCe%eJo@Pp;xdG;jG>E_`+
zaas_B4#e#~gTsg;PB%hV$SJx~Y1-!xtPV!)^W<**mpb_tY*Fy``3x0Vj9yaDFxvZK
zW920|ZYboNh#{}`O^q^LXlatxu$QvPuS-e?1u%W?f0rYCo4{a1seQJ=AsbDjn%6&-
zwV9wqqI}{jZ{ZoZ2qZ67oVio@BizBE9J0f_2wmEV4_krS3XBgw&MQzXHcy4aIJvXk
z>|cx)Y(GQ!uW`U7_Ze`0`7VSa2(MU4+Yd`G8Zq~hbrW|gi;?-Kn)$)fnRZ)?>@-EY
z6bxq{XmfgTom$XA3D}~xrdX;SPSubZx^W{)NZxyxp0Gpj9~;^@-B4Fte}ODghyl7W
zihxTC6bcLBLC!pB7(3FLv-6qLyYSE@flnfo?JG{-%ZUGDWR7WnU+`cc1+S;=`&ZKJ
z64c^3;!pmljpYBDbEB)deZ0kJ74!CN#!Hi6uEDD3HW0gUoEk}_6+Ej%Vh<A<;SXQz
z@`H~|m+e2!oL$M~p+NcX#zSaa;f9OZIW7}DfAz%r?--YgA2Pe|_ezO0WRFn9sIBF^
zB7BavU4A3a!;Pq5tM86dk8RdpS7qKW9cT_;%p1Ao^GptAiUsk$H;fkTYB6Uxe|h0{
zR$GZ5$n^ZVAC!#xz%0n<`T5LgRzsK13))l#7N7d1*C0vhkGN*hXQ{4yRN<$&>H}d~
z>pS^cK7xk(T=n7d$Ge;FlI>udyd>MBuDx6*>eR(ZAtuXi>*LEWVMT;pI8R_q_S)~{
z7G`Z?mY$M@zbwywg|T6glg1v5z7Sx2URb=F7gU~M=?2MYwD~v8mwx9>+P7fT{v-q2
z+M8{<x_{oXKlt0&TUX(cbF<FdkGZB(yszDo>hCQm@A>>&vbfe42+2S7DVAowHI}(I
z(oWuZd!v|V^{sC~gz4b!`S<i2^K?+B?u;b}wVlAfNlf+!SMl-d>?nv8oFwr1#J!9<
zsM-;F0WLL(U{^M$j6SlReI;`_YHL7k^};QnHW2WAq=*;t9`$ZKsjY9NZoX}wV+xvt
zlJfGij$2tqZNB9@wsPl?UGVRXcDI)lx-_>v+Z0?B^>@|vgffhk7ufMUcB9<vgCzWa
zWP*J|?!b!`ovU1k(BWeyijbc;h<Op#<M&zaCsJQS#=UiP&i_Vk75sFTIsax~hChx|
zKXCVg;YaSye#Rb}dFD5*tXeg9J4aYgZ0;Pm)i<`4*v(~icfo_4Q~Bg}VmFD^GLMI#
zT$Wkmt%aNgGkE~c$47r-X%mGG&N`8t+D1(YIYQrQX%0?gSg>|{ViRY`IIjKGegi%h
zNn@eT&nm_1ls}cphCJyH0#k6mfc^Z{%#M|}i!RgDUQ)BlWP?b+KE{u3&gEv7L2SCd
z=xCGHKrnZ=#ugISyv@hu*q!552!(9-fs}gW+IQ`W!U@^DB6C+^j|!P`3=}GDH<hvk
z_oKnfJ05ITd?$N<*qRiPw#lW6xeGScvK1esg!G_cu`+2!ViO4OL2Y7hr`5yV!QyK_
z>PrMJjtJyIFh^MgSx{T`#MkjqX?LO5mBn7Ui9nj3>0No(cK(C-S=;0ay#C-pA*p%A
z6ohEjMwdcVquMoNTM>4&gBTRhjoszQ;TK{jl|rI>Itn>RZS}~&Sv4HM<4qbjttJ;>
zj?h6NVa8JR-8dq{ESUW*yJ)Gh;A4n*H~~5Xu$NsBWQm`GlJo<=zCdNjwZl3rCUY8w
z8c9hlR)XTAAO#D{=$bhLPIpotJpPVg0u#U)E|F<*k6P_%=9vt;hEI4nY?<Y1672(F
zsd!{KC|0V(TWZs0OfRbnq(4B2_Qy1YeAFz{1w>G-OY9~0t?qSL>OeLW<;x5;fjC#@
zrfYYf2dk@H44=j9^pXk+5G(Lgb0nWG&_~M3SJOFoUob9$<5avcc|CWBB>e*H7{MN;
z-~@<@y3`Jkx{O|6aw=m7SGwamZ8F{~6chbf3jLWFL54`Yo*{zAyxd)of3O)jxnX<!
z2h3yJAtOTQK`Wuq`0bQ%Wl69t=1cL@Cn5WR6M|+-tw#AkxF|%eRGc!OS=0lnfzxAn
zF;~xyTrNLjZ}lbyIh~SqLssy$4UX0}Vl=LF?-qPS-Pv&RKFR=8sb~8HshkcrE6*+v
zFtNnROw?A%i6jNuDn$ZjH^J4pjk0h$tRNZ#fhd(+dTMuh(Q+2J&k;avJ;uf<ADO%?
za9_ZFGW~Z8dE<Guio&(ovQQXsecWwT{SET4)6<swS5UPMM`vxUFvSWSp=(dlxx`WM
z6=R=*;NEaG!6yrMFnp{ai|R8XP;G06lRN5<s2>9X_p{io+yqiG?f0odL*cyT*f70F
zpun`2_?G<ggZDM{HO~Cqovc}~|H@4Nm)TE84?6PL<-9ioZoRLkXnTY1MY%)AY2W(l
ze5O8|tmShhTg~%5&G6%wtd^*)?Nt#X*-pHqlwPyE=N}a2ZN-ZF-ob>0#`eVCX>Epv
zKRm}Z4?dE!@ppZ&cf8aoh(p2_-Z|uK^<Osaa?j^Y$}f<&AHMKIcI*4Hmq(l_*m{n>
z(Sz@(8T(;*F{}?Y_ZQdXnNVW(7hm6WZ8u%|S3W>*|M*I~dTw7Jun*ApRL7|1Ph4Tn
zfg8)V+o_OR?1}=<s21wk7gQ>0g(do<UON{Aek0nqc37Hm+tX|YVY5bn&$XxNAVKwi
zy2wd>ssne{y5=Vc$)VP*8aQ_cAyQ5pz@{iYv?#Zjtmd1=J0AN`b(mzA_rD`|UQ|f7
zQsJ+@659ha-tN|Qu<t)!hGUmG4~i33U$_;FHr2E^@$Cr<SDj1ZD86sr-@f^?_a!l|
zbBN!s{RGJ^aP;i9AMOO@ht8q2w{vXHiA%*&{q>fwdDK={c6c*Oizfg41EsaK+uA_4
zzT@^RU+|3;u=~J5UREa?dH$wf2tFnUz67!Zbd}B>f_h#QNV=azj8~hz86?Aa)g8FC
z?HS>8did~eHy5qh^Y=P!URro{;qh@gavVjKFn2Lo4M@q-|8Mqc2|4G{%>QGy8h2aE
z2b<k#3;x&fJ2V&WEEjzUcY^tQ$gg^xs0{#Bm$AV1unq~29;|&X$cpUoxU0%q{<X{G
zLpQ9BvHRv(MFMHY*6Es&gJiBrnwQo-ZpVw2(of_~JHFqFW0|wlKNdoM<Fqps3Tmqr
z3yRVo%HcnuB$qTq)KIsu=#uY5m;J2)UF7Z0L?mi3y?`^>m;otLQb3i^DxaQA7fy9;
zb-dDiH~ntNS<jek*z`_pL;*(6r4-a;#^N`zBuppge(PX{Shea@<=qe5HUzJpn?e(~
zm6i?(Ykh&7W`U=QC4_<ze-#@Ht!Q>0y=Qq+)=p(yVTn`dBH+2sk8`Fr$8*BLyvJg9
z_b-R(4tO8pw`g5i;OK#ut(8K2DvVy(E|v;^<pD^^yJ(L_@>hEjkc)CH+8UO-Xc-NR
za70|?K9iVgWg!L(X!yixGE*n0m|-|9L<$5*->D0nyQ943txW79X8}yY;)W~F!GWCQ
zLCSe8L>Cj7!`pHSV<KcN*|R`^uzE-C0``=qnU9AI?ru}Q#0e5lp@|<-)V^Jj!{Z8T
z!bM1OCFX7r0z?vYpS5%QLlx@<z-?#Z!cl^Z$E5jAF0L(%d3gtZ3XpQ-VnKgMl~>R<
zbG^vXXJ=!!4V8$f9<7p)pb61whXwXS6sHmuY!yr%6A1Wv+C-q_Um&#17hN9jCdpH3
zi~`DMlUikgFtW|GwrtA^<oBd!GMNUfJ6(IR8H-h~5e^8s8tst|mQZX7uLI6_qzik`
z@I1@u{aIdndh|&)<S;K`x>&f8RE*+mqh1#2wRmzdfMO*Q`D87tRA@M+nH5Ri7_GRR
zWw^X>W8IMj@<y2)d|FmiiL52d3x&qU))*v0;%))Id}WI$$TXnrw6O*3-F~aiEsfOZ
zq^1?rg%R3oJSucAKAN0t<f1+h_`R_LCwBQZ<K9RLb#<%jH3o7Rq0)>|&^jNb{e!_)
zzX`e9_c1vTY>3g*X0y-ym}eqGtbcaEl%BV@#wXT2z)48|FWq2uAnRyTHGei@kMQX{
z6rL42uaXo9KsU~2V;FBE#_qT|I~V3XTCIFfePm#fft{0TxX}DmyXh3W3&od*ZT9#T
zq{y~h58M~_k*|l{J@}Nf9m`6t^iQ*pxXAykl4dx3<WcczE=HXH;Ph&K;voy2Cf)qs
zy~xJ=1wMxCY0wvT7a-2Yh6}qw(SQF{bDqy$$l4bQ6_giR&VRR|-Fa?$MT;vY7wtzb
z&h5dciy|zXTc|a8cX|q??0H@-Yo9|aMnP(wx{S#rBR+>LD-r7phn`z3<~HbU^ViUg
zeIs9yY&aPO<D`($8|J@`Jimc*C|XLy$&#V`U+Y&B%a2YrgZk;9kO80!)lJ@pU*=P}
zDoNnMZ+9%beu%uisu>&}aYttDZ_f+Uqc6Ac8^u`Z_$+|i@AtRn6+zz(Nt_KkxA41>
zv!GJ;U;dtz?Q0uFIecWidF*>uEI)W*jG}0}LnF5pg(BR@fM_KrX3kHUe7NG|G#LHC
zfg;3d^hXVB-Nl4;C_JM8ZNr8J?`Gfnwfzg}NH9ngeprs*MBHcuEmn-3Ps)+8;lp?k
zaZhlBp36p_p5gzzlp2H%D7)iW`-gsrNu<x#l(nEb+)Z}B8tAc!QO9@3Eo)CMb9j4l
zYIbohTe(HC`vQD<kg|_XE<`zn7$d|nz-vW&<>De8)>Kt*AG>e8G5;2GOQD%n4_{%$
zW4{wRj*JeW;HOB|Xcp{{DpH8l3fD1E_}nZ;x521P_691p|2GGW=9BKN4m+Z6h$tyV
zb1$PeRve9$BGfOLn%-?ysao8Ieew;=@PC-sgia?~u>zz%@-&+PVIOK8Vu*pyUDCX=
zZ?P)b&JV8&ugu-Sa)SOg&;{}}`KkC)uD9#)>_VMv?F>F^-O8xyY0$BBk`aa2jj`j?
zC#jTqRDWxf+0+`^_Pe)P<MjXF*1J&)n;EjJk6gNxMf$g&lW`SJp>e=#Uz%<P=%|Mp
zI_a<meuOO`vuN95xGnY_t&y|iv$i*4v18o5JvWOY#qPR8tZGF`k`(%;?5K%><3y2Y
z;wCO9<5nFV2z-q-x=b3mi>`xu*G#stN@f=pW%2wXHykUH=mNjg*|=yM#7GQ>gi1~w
zHqlf~%_gvla02ZJ@-k?60w<jYr@#pwN@09oC|R0;XP8b7>0XJ1WDrpX7RD0WCaz0n
z$7h(d{R5NRPGLO@@(5{Q#fBJ~dUGvgzL}5WFMx#_MnfL%vcg=~<I8+CzH8s}`HW4@
zMT8c8U&wlIN6SxgcCsWGtsUxVS768yzVNhK1?<RyZ9oXZyDK%&SS>tm$1l!VeblVv
z5)?r}-Y|1^b4b{hT(vDJ($9YyZAnO@{2&=m4aXeFZQIbJ&rU`tV<nhY*iI!E6i|!?
za}I9g*c-&FAayBR4-j2}g4zNomhBjTk}B`@Xv!w8^|E9y8=;MTC&q-l31~}qu|6da
z^=jqQn?chKJ7h!j@-l~`wQEqd&M~cddNHjGRQv`32T>?*LjAI8kSq)H<gU<E3U`8n
zd=;+6=3kUY8>A>HtxpIttM(g5)Z?r(zP?9&TPhm9EE&U=4T5eTM=ZqTp5T}t!bI2&
zNfPz^*2PEQ_rk!{=#h`Qze!%TI6{==&gG`D5CYz6+?v+Tj~oVfAd}QqsI-)U1WR2@
zdWPVXNMsQj^J=sB3<i6!Rz(V#(yeJbS%xwUuP_-q#AiwwYqfff8oW6na&!c0OuC`a
z54@3yEhKir_rJj2#?k$t_JN=d^{t4QuVKUnoAJgbtYr35WiLUTMh%_LgB>}qPIyC?
z2zMd72HVDmYUiKv{!u>&AT<80#zF@ynTtW$k63$bKfAx{sBw}e9na|%swXoxL4J%2
z4_cD?yM6R%wuuzmPjvP(RQ&DXm<1nkH-0QSiqEi*b9$d;o>OHCa50oOb<bVq0+M2x
z>zVLbV$+;ay|L!FylNbl{ZM&1cSF3guAr5=;a}*4eD<NHb8j#o+)CAQgLEddez;k^
zD5iS0K}qBe@9??voK%L*k~teU`6ySYiQ$$F`U=UBqptx|M?7O=^5k(fM*}IJFUyn5
zH~L6a+iA=%NQs|Y{UJXoALG9~bkyP32bAog=Uwi3@=C3ro_Kx=d$1w8WVT@)cP_6)
ze#W$?S;3t0;y7b!uQOYn{eJ>=Ab0U>I(5K0g!YFFNwas>fmWCm`Xm2PW?26+M(5zj
z(~og})yYc?hT>4Uw8~cWj9nk|mOb#c;Pk1842{l}&wC615HS_AOMY6Br0P%pRc7r!
zY?#0Q;uS8=4$vKzT>C)AmD6AU#dI#s373oxcjLrz!GRon2i_%${t)&2)0vxvlq!Sc
z5%{eTP|BfgSUdLa+-b@pB{k-HlIB{WQ95m2j%Xt^iJw)2fk6B@Va6I%tF3wA)LBqW
zSu-{q^$8o_{AjFmx{u3;*>csMcuBCS5x-bo$zh_CT>R@n8wlFV^WIh_+1&(vb?JgB
z#X9-E3(WuKNV)&fYtzbioE=o1mmu45d{A4%`b}Iw^%<8>QGaz=RIK#3oM5AF{*~$E
zp=!*+(A4T(?)1lf_}X>Z{>kU8l*}a9y<w#EUKqU+Oz3As+&IIXkajcAqkB1OJ_TRW
ztqk6=ajIk}y#~fteX1parUUqt#A#{(K1&=Dp4EzC`r1as=x;2660)ih4#s6dT+5><
z$AEX&yUjeTr5@j*Zt`v`x|TIc7NrpQ=p8nizR#yvgFuz77F>)V@cX};1u|9npFolM
zBoa9K;SfWjG5j4l_&I%j>Z|9iW=lh814r?U0#W5t$@|~HM>;o$8=BU}<Na&_P408t
zn%X%*h~w86JQz-L-U4BZJzCwF9=p4T2=d}yuqjFlt=K4|cab5=RF^g%F~sKD-QIdN
z$^aTyq>w#L*BzSa42xLv6Z*lY4kyc0FM8M}7<El8u>z}+sc7_&`&*hs3{H5OttNa|
zc+HJ)I4s+s3^<ESQX-zXrj!B2^z5q^90T799!Dr*Ft%xjkpvViyBN;mdqum1*52U~
z<#|9@^eWO}<OIO*dW=W4A%i~J`KY9P-Tok_tADcBx|+IbHbPZ6ZAPhqz)Ln42sPsn
z`&x#G6NLKdHp_Z6glD>etz;>ktMMX3U3<T0SU89Dx<Fm!QecD*3-JxLyXbE>gX8Lp
zx#CVG(X=^=N=!#7g+%5Ys#x1*Qsv-n&Z$+a`FVL-;?*(+I**J#5cUjLDDN_K`^Y_U
zdx5@Z+iHm!#Nf1UBY%pztu8`2=m;zGBqB>(TZ+;kOu+*I#S`0s-biM#YBSE$F4;pI
zW0y$eM>hlGZuY20cIY8N{yF8clo*Np%5M*dI4$$55r>JOo&g<XeK>@0cC#uW-9&9A
z$f_ojCpA}AdvGcHTxn<yN5L;byDoVzxm0*51Qo15kdHwj^&I`N!x<=HTN-et+-peN
z3&LK3JB3|A6PF-Ec6lw9irrQ%ZmdgfjXd<^)g^!`W})tbkyb2=g@Kwwq)-dE;S#-&
zK?`WAaQN4hcPr37s6RC@d0I84sa@h)t@a8#fI9)oK`&Q|cTX(VK7xx;Ln5$?In&%2
zV$$(af{(`bzYE?O-dXPmnr>bKdb_RFW!72x^W28k=3-5~T&v_N4(+y9Xn_>Lb(Fxy
zGLc4EKs!1Y1N#|SW0romYGj@8&SILIgw@{fTx^dqdn=Zh4AnL3^mtwWMQ~%zT#IM$
zls$v8wfWWD$krE}wXbk~s@)aMEi*C7XJ#@x`5R>5Dh<3{Se>#W9A-Wqg7j+Y(hZj_
zO;((I;5aq=z-Tu1A%yaH1D6I9wco$24{o=A9ln1u)s^mAxv+KtO}2Iem5Aoww)~4!
zz@#$lhP&x6dMIOsNs#3?LJaBcwr)^_KYod`C%@Au6jT(imLdmew{?{{z0QSBM78zK
zbKStn7PDU`SyBJ+PliP_7nhqutBH(zpEcrY8i~Z$CSqq66LF}m;mR8=n;%AIx539c
zd<QW!2&};{yRDWvup3k8DZu)7c!~83LuK{$D^fYcniQVCwQV>4KyDp_%lA%Z{{Gu6
z^Beb?d-^9NseCcmu;T!F7<Y<C`HwdL+O<56?C<_{nU9^a#Wm>XaSnlHSD?#!2yx^p
zK_@H<u?MkS&>t(*s+=Rfy=h1fV<$@_rOF^u-EGf`+;`LH44spe3aHi?$)egyBC&e?
zh{^?@$vZx^oCk^bWAAJ}vQsK&`LR8%<%M<ozt9m_5z&dTFkQHqY{#-=J$}B~`KS&c
zvbC);o?S0(^fKZOvDxxEkk$zDXOZ8<LlsH8t?{PK@WaX?ssE>t|J&Oer4re)+j_K7
zHa>ZQHD9+<WNUL5g#6)uk@WZ+`9^{Glk7I-w=?!`z<jmO=g-V?7u(Tnf4K9KtUURm
z#*AOS$#3azVtP9nxgVW&sBCb+FC-K>YtY;NPux4J9x*Z94cPN}v>SR!vTW$Kj2fCx
zz6jeTHeugscBG{0v~H`zgF~^HVPA0J?<e#uuvjq=Z2agN%a)+FM`qKDqI_V3-B!^V
zx!zw-aymIAe!h}u&%|9)8Yw4GI3>&*%h@QU(5}|;8WdQh)NX4M*d_Z%V!V%Ie$jPg
zkA^HL>MtturFRvFSx~d4rz5G(X-`L1s)h|k&ele`+i>6FENa4hwn12D5@vp)u{M0i
z73SNcMQ8Y%qk;GXz{sAfQC_88vpoQ@Z78A6R%e?p)tTHl_0r-`opwDEM0OL;A$RhZ
zqdRcPy%(t5=y+lz9}sYd>0=y+hM4gNg_^d+SPg1NYebgKoRb-=tx}9G`3wM_x)KuJ
zaIJ*UXDU;-Tzp1!DKt@<%9hsKTD`p~?~$=shle!;6Xv<41wVjFnoma?MvJa~CUjl9
zKD`jH-!(V|OxlzzI;uJ_B=$Ga{id~L)9^|O=scDqqjE&>D12BPr(!I`WrU~LI+BR`
z0&k_MJvxtgwz3&&hl>;f=E^xT1$6jb$g0{F`5q`mMes7(o7bqA2IpCFvBDC90`;q*
z2*xDBDFLo1ib0{S&gKJ}wzT%Cg28D)<3PN!cSAZb{RxW;D{&GyM|*G(>JOaZV&Vp!
z9Z=W94xW2@%@FE60&_x>LMEUN!gKOdzM7R)Of|f<g%S9z&Jk~f{a2x`tAR!V^BfG?
zP>DGZ!LiLa(@4mEgfx`JBxU+|66<;eSryZ@F@&Ail%*edp}Q6WjF`<tzk+qIfU9Ez
z>?VYtc;F1DJE2SpypIoXpOS_5(?iSbBf^W&rr|FnwhtPrJ~X@!c{g~srze2Quv3Zd
z7G(hcuv>`)MONU3EI=ok7@@Yf%*m#%v(9=Ll)1dVAUy0J>*br>R>(MZziMhC4s2yG
zh9CqNdySq%6XF1-%X-bevO0PkH~blb^~%Xbb<$p=@GWt`?{RC?^>Mx4u*IkF?5o3K
z0G&60#cYYf+XvW-V({8Sax6FN12{RGsO>(qdcpMUbfVGuY+MCky*^ILYK*r~myYiX
zrN0U;<KF6&-O2e~M0*a46xT&GFSE4wq#Gro*B(YZBuq9!S!p`@tWf;{c3aW6i;#yh
zPaVMNP}z}lEH^IE8QCCji{~(oF;CJ_ge+W~H^ax=9_gGJ)Mf;nYA?2;|EUopuD8FL
z$Y$~2D+_Z$0bT|pWD|?TNw(-9L-++&1gZloPxH;5hwOB|K5G|%5eFZmYgbwRl`T%p
z-pgedfzP=816C^7L=AHU^@XJ~YH}T+R(hV*cf$2)lb=r<^&@vNvMv0v191mGjDJHJ
zjeBKri1d_PrqjAlerdIN>YL{^JLpXrN-A@SZ&+Ua5%0Pdug-EumOK(@Pd=x4;{b5z
z3q^i2c;owC>00Q3lr4+xloguPY{emA6j#e9p64CnJBOyE8}mLYh5pDdnce?fn=KMV
ze*d}FT)#r%91u`j3#qLsmw$RV-ubtFJW(iz-dis<tA&OKe-b@(X5N0Y80*;eFZOox
z>x=qmE3<vJpDna+va0y|^P=Wswnu-8`SJs-k89<gn+)9g*Uw8|zw5(b87AqcBm`*H
zl}Q!=IY@m^nT%qJ-g_FcGK6{$JV<{O1Q}2$9OLE@im8dP{hWNG+A0gx!FgHmxu|zW
zTQ9^81n0i8*;cYAhFC67+A@O>32Kw~3d_=bPXYefU))S~S;QwU+aKI(IWzW-*G4{&
z>42a;@c4ReEVu=#2C#U09=t5|dEZ2{Y9r72w^+IU`H_Hz>x&0oLzZFL@z$-fZ}ZmR
zLnurRpcdk0^JB-&JCXWl2bOG&w|y70X>uT+y}|ka)Ljq)F`R`=kH{$C&+^~Pql}jf
zfRS_lBqU6)hj@?Bj9MC29SL5qJ&k+=_;g~|EC<^1V9<F#wdE+dPyRYWiP|ztEu(nS
z)v((dN3j?X9+lLjE!QxDno;_j@?cjV)5PwDz_ak$gLh|fOl@CE0zl)r`_f`WbY(3b
zM}EC@Yz7B0ICSznd|<iguCx{%s(!plm`7Aw<5x+v_t2pbs!{hu_PKe&`a@ygO48hd
z8n)Pd8WhjM*@Ci@Rs5yekZjQzx^^F($><ezaz=?bDyyXMLLj(^&G1IXgX|r;Wbv)v
z=G=H4=cbDwDqCxzNKqIf@DQ7U-(ZlMXvAe=pf=YoKSCm&ZQpH~^J<0ct^);XirI;h
z+bNY;Z~adAOOau`r(-h!k3JYfoFSBWJOXQ9(ASl=f!}o1A>wBs2vb7q(j%JGucfU~
z+c-kV$eDOmhttcuqHVNM?s)Of78FS4dZBXf3RMazlyRtU^6OK8OAjbI<}S`f2`9hE
z-Rn|9t5L|&e|yn)qo4I$Cczr&p6Q`1L=TR;&31$0Gmx_)1!}?&tHUrM93XYd<vp~>
zk$E~=IilKnN@^=mvXC*2%o6w{xZ1VrBfEU(pdjy&!kgzANUtww)*e<68GKkr=uu2w
z1)B$PLte6=lT!;g$V~2a<nVqW4v~)2A$aXRH1iaRvfnHsqU;DH%i1zQbi4c&nk#r=
zI_QRJEHPQ0c7xrDuV?$Xc|MJ)6pE^$i*datW{!h2GX?Akk3pw&<Y$5`C`GUGz;-Kf
z+hTi2&OD?VESf<)3e{mVP4P<le$SI+Bfm<xX=_k$#=K8`r6_riu?nUf1;0IEhEO2}
zVF}yGlAz~50lTj2yXW)7P(oC8nt^;OA3))|@?)^!y%<TA8soZ&layD6sTFk%Ah>|5
zPUH^XJ%MC9B9L_q>Y}v}@l%E{Gn^8+m-k3evN??wue-xsVp%9B5w7P+;2`inLaQBM
zII|%9qKfgn?78<OGFAlaDOt746UZa_yuHe-%`JwOIftY|=517UbDl_Z6f^+aaK;H3
z)~piqVzI7sLf8XXwIqMUvzoIlxJTqkZ%6`8I|`!O2U>KZLIhPeSjYS*+97i(K%WET
z&v}BVh-EV+5?Ei)yjomI11fzWetw8P%b8myejgxNhZ1ER%&n;>ZVwS}LqRE7b0ne+
zkJ}Nl9F(&OqHGwjkKZhPUX@{CW;y^Mn}Z1G1Z!zLxV=|NF|$!V4w66&*yqhhn$oq}
zmd{7j$zZKuqaiz|%8ENI_e8S%pov=0MRNtzAVr1A&h0ddBR1r!hRYiqKT`eN8^ZTl
z#+<AcF1QlJnIMi!e$|-)XS;p$s$>@Y5O=ROFvP}EHq~0k&m=#w*ycxmj2vLd$MZAt
z8P^_z9D9S0!9k{yb+U+74V9iE*8^ci*e)aG@&y1?_;0$J;ay{HVPz|hmqTnR*}$(4
zgg)V$!G37dzK6~45q4IP7nclg3CPkmfd;%?4C-dqM;8@dc!6T|9<MQ?rD_>s_y9&1
z(K(Pa4N5hTl1MrJ@K;$V5qvTd2|PF91s3dP#IDU@30=qbr`zr{^Eu3%<r_V=`A$ff
z%E5rMI52ky4ec7~vI2oOZDNr9n+h&9JL#w}hloGRuz@|yLrSxK0-83&a*1}E{2WQd
z;dI$NK4cVRd^BEJ5ms=-Eb-hEDk}U0BT`32rkR&$i3JTy+BSnOvolvGvWz1pn@6N{
zOw5Zj6*wiU!EJy7)>qQ@^PBZ+<Qq5`yCQZg+N|=~`P{)YsQ~TA8C(EG84{`%O7P8s
zDjE}H>v)IAG>^-Vk%LN=ZaPjqy&{U$B^Rj-#95sjv4|vEXF=;MpFKQ6H_XYRuC<UQ
zf>=v^ZfJC(y=Sy#Ytd2rsuqAcZTl?jY{r+*E)dl41V{L3n5<zjJ_%B&s{`sSfi8}o
zB%*5xo9dK9inKL&FMGx79x-jb=mw&L0&n&h8!k0Z*dusvORJ#9s`FqyMkRsN7<pLM
ztiAA|_Grz;^^vwMG?(NBj{|`R>&$F~Gh_P5_L;sf)U7!bFdR*{?Er1`!U*ZU)w{7e
zIr$Bm6Q(18c7D7pk}Dg@RpOkDoan{~S(uaE%K)6_!#0IG?i$g)bG76b0=<PPuUND~
zgdZ-$;pFb+z$Kn)KQTtfR)d0q79c3}05b~R1n?67!%&V(6PsZ>+oT}%gFhYGp30v1
z8$&TTx1+FHU9XNYLh<Jxsk3zy_j)Q^aT{>zXVm5QHVYklDZ)O+k!$eY$j+*CLOmP4
zdSFIOk}O7bKnR)ZtUB8mnzN=Soi6wbeb<WM@2#`8cHVsMhqK&@i}PMFZQ|`_(;{V<
z@=oE^tB2@%t$E!zU)=dgE9_5J<((jS@$fjAyp}F39A@L=9|eNWqklNc^%h)EWB!+&
zS!ZI_?k<YNme-2`Kjpdikm^=(YKj;&!`Su!A?^%y1@h;frxj^RVrR57eBJ5&>q@;~
zQGLd5q;5|_ow<YTD7EJMa@#olBaC%)d`touZ2&K$aS2uZ`JvFMeoRN=f`eM!?i9QS
z9O;a)a}|?yUWfUBxX#Z~df@(u=CInNm-mf7h#JK+$nn^32jz_qc)Z4n#W&=}w<yv*
zRpPlX=<^_VJd@9@3UlVLb3Cd`a&IeNan15?mzM$_nka;+D@tdR|9E6B{2FZj))NkA
zBV%tY=yR9tcx3XvAA+;W{PKx?E?4?(M?G8SMS)x2%KFX5O|eXy#P0`E%TtdPgt|2^
zlEW<&s9w@z_#Y4?uv7lRNNPN8<UpP@!ig`1#Xw-Zoab`(EsAUY30We<;~Qlg9(n0n
z+<aNwpb8La<l6stY%5Db+!?NW&fONzb{=GFLdh!H2sP$>4i|=e$g!P4ANMRG(J9JU
z#!BRqudvX1Xn|d`VmdrA%f2i9u?-+NvEjndNM={vRStPM^`aZ#-ksTj|Mim6KJw#r
zMRM}~cTb|P-JV%BLs1R0UeG$ug=yd27qrEsy{D>~9WsB%f1}lY`TAJt^T|J$4G(+f
zfW={-wV%+%mzTr>6T!XVWz8uG*SydW<=H@wI55PF<^SxHbp=s>+l9xoT3Tt}BG}qU
z93~tHzJ;;WeCS8vfE!w})7?n-bS-_JeAbayD|xB2^X7T&imcO{aT<l!LU{3xcepck
z`h^ZAPSBU7Y$}mcd2Vx#`Br|8l^f6S9kM$mjKNCQGdnAFY8``xLjTixn7ui$e}2C6
zoy|iU_#T%?CW6^RIKoOOEHr2Hzhkk9EhcM7Qpc~!&0jR;?|Wd_sB*TN@zIs+kLT9?
zNsS9S-gx|)freHyYG^-j{SbQLWGJ@NonrVNmNIAo#Ft6fRNe$ILKOqZLtz(SLA`YS
z*-NoiXGFJc_oV9MCRsB_It<sgS|uc#tFa>P+!93?NF;k$ZuAf@hGuHqK^}ash-P}L
zP?_I$=URbt?BXSrw=6)aF3QeQa(MY#6-^6DR@-=vqy087nFNJ^Yn@k^b3E7hC1nXq
zKNw9?*bQx_4XGCd%|jNuJYE3yUD_TBt1XeK4A~OktcC@i36Jo#kTGdh-4x^v-)-W_
zV^_1`+#3ljDi-MSVV`%lV}|5JSmP~oarLWEB8VDEn#cIa$)s_F`Z9tPV{a3c##ZVq
zw%Rpr;pgq;1ca>Zocu^cu);HhiR4hK*8O<6mm^(0OtG%(<An+6SHK^Z{Id$<HiTF>
zEd5~O6~q|Y6N~l9<vkJ33|#M)N?Se2CWL5h%iJ13H+Tj#hePrSj5ARHXCR#AydT-t
z0!tO#C6rpC$g~?JOxiSL=@N!RxQpRd0gkE_c&diA7nU#wf+ghLOTn(T!V^s$gf4wv
z3_H;fhB+CfxfHi8mjrT=Wr17zf(-}hTG|+(#>vu#YzBu{^O5sgNwhB<rc_t+K4@9Y
zdmp4;a9HhG&#-jU>7992csK(ICwR<|Bk=XT+P2ptC@@yeZVjcvQ##kjNK8|<*NvA&
zZ#p)~mA*Qd%30j4BaZ~~83f!G{uUJhO{Ce*!Ue2jJ+N8k<TK4+RZ>1P7f5b9SH#t7
zqPHn*b%PB)-~fil8k`j;t!zt0N<q7rXAyVX5yPjqy9aQ+wCN*Ob=eNcM`5m_c7{)c
zB$9Apm;p~2HJ8pGzBnB#$iMmn_zVIYI@HOFEOylSBB`z1zkNf&G%94xx#B8_)EWKE
zQX=R_QD-j7GU>SalPj1nhJzCa(m53|(+|8|LMhb{!fTRag7ZinolN+zTT1{2C*$CP
z+Uiwn8&hlKI!+&*1d=&>eP*loGpzax@S%{4kL5nm{Cegs=gd?%Sy~dB5OxKoRbN!g
z-v%lBGK2g_|7kJgWElXon-Nurm?NpJVnRR1kF3(0d>4i{USw^3Wr6IuPPI>Ulp2XB
zJ!jL3>W}v2s+soAPNR7P&%S_u>-kDyQS#}*XBIau3yM)VD|y!{AIhjCG#uyU`v$ad
z<*oW6I_EbSFB~d=@kY+nKJfP}Tl&P0q;@ORe&D;u>jIcz^=&Jjr@x<i^7%g|k>4*Y
z;1Tm?w~^*G_pRCT&rvw5v);{EBiQn<M}f>rQp58XvqAf31V6Yh*HU<xx#`|0Gym^i
zTa=YP=$v2dqYy=Q4_LGNzMpU0ff0lyQFcKch?hUY?pE|}*zQkAHJ{$NsW>Q7@p>Gd
zTXP@3?s()cZb<CuL|44PCTh6x0N(o;N=^*VQsJ!l{I_V;1Ay<Ik8GWLT~o<AMan0F
z4o-&EYG2CQ6?lew56{Osx6wg+J^x1XHdNaBgA>l)`VY+AJ;SOGwNIJu3-Q7l<Wzc4
zv(LX?a<my4Qyh!?@~ye^ayWjii<VGZ?<wr$)6SOum;Xql)fKN>TP2XrloaZ0)a`Gg
zH{bG^^HI2nw7xQi{DG^E6wdtxwQp{8K~wMk@W|tg1)zDM?vR-fc~#(`(6*cRg@pXp
z_|W0P2$6g>YMuP^8GTJkbb|YwefI!fklH#CK0UOo0$&ZYOk4+mMRd9ddFTCp1ntx#
zlcH!9Lj=t1-`MiDo;_JJW8dDFgXH~F)|kn2)<=&FhfeS=Q5wk9SOQ2yW%HibM@N+U
zJFi)@_LsB_(}f8Mmk~36hzkGk`OR4Z#{NIz-Uqt2qrUI`?R~a%_q~?y-S=8HvN87P
zS~#-#Cv1~C#K1@vSP&-&$0j6?!m;amxukz?N}x9hB_mlj!X=;(XZ7-4+8)43Z&I4)
z=CQh*l&)+W(&c9PvE0-&qz~59>!W@tp{!e0^WwB5d7tmh-bY8$k<Kwm*ZWCl&&+Rr
z^PAuNX7=p)&CH&iZ)Yw;A(r1~-6EV~4dU72Q9D2Rgi@aFwlzo%dCz%HGrk>j5Pb-A
zXS{BUL%=ESg;uSf-ODku5fYEb$#jVz(PzmZ<<SUpENe^Dx()S#PNK_YyWr)2Rc0%h
zRST1Lx}VH(-$qiOZs5v#iqrbfggngh4L%Vg>W~Xn)B^Iinhe~t`2A_GNZm9M82h$?
z1@jnni)kS4L=n1CH_ROVEaF5?KBkJAaT;qtJ{|;4yxTmS)EyqZJJw|ib3jQ%BZ-&i
zG!iY#qqhB9@=Ri%PRi4OYuZ-9*+^BU14v>m2Xr1ewseQN)F%&23zeG;EuEJ@OUM!1
zjIu8=HIsBx!HX;fn9fs1PQM<gEj%LuD+Jap+!N<LQY&#F6JtF6s`oo~R<SiHX$06p
zC?wd5gB>Gbo4Yv5A#|*8dFE9D_Px>;QtK1)5I`9!&wg+%YQdD(L1Zme<F>M<V5b{e
z=56`s?zO@zR)r1n^dY_sT4R64i9Vr8UH6sJryJtwXVWE7V;dML%NpWketjL|ZvagK
z&XXb*?o>uc*NUsCv0=5P>?Kd2s<P?}0~M+kt-jy4Y7k+Ngl1h`1XSGAGv=7Yu|@n4
zFmo6M@7nDvLIC|<ECmm^VmI?z^Z}85bX3$3&GZQl^hCk;#LfpHVy^w1<%va+E|eYf
zDYAI@>KvZ2pdq}rpJisZq8Rhs!&O%-_O$bOTV_O8>kAef*{g_WbawL#f~lzLRc^(k
zqDqBP8Rin3Msbc%luhLn={aBH>%+V{8qoYZ9b9GM3MLbkSgFE7Y=LZ_=qEVH<Dx3V
z@<H*mBptr_yw?222fuU2ZXK6Ik}S08OZ%O?&@nJF*m$w6C^evZIbYi-dOBEi{rLwr
zb;y7c@>c#u<(|5T=>3=N2|Eq8%Kivp>qdg!8>?dbLC}71PD3lC0?!9@F<ZkiwTG$<
zuJh*HvZjZQ6r(Ti%KU>N^^^}iagB=!Zqd7CUz%sN)eY#a8~fVoTycwz6Hra{rm{E5
z(&lVDFSAtxU(3Eu;>K*9w=Z)%ig;%KHyzJ^xTGjouTB<Z%;=Cy&eGfR(0H{e9i?c;
z7u0<Awe=y1kW7TJ&sL+_zVPBmr7CjrL9lq`2TQ-Sa}12RP`}m7$Z>owFl1MJ#;Q=C
zNDFIcdY5?8i~uO+dG$@%R#)DSR?=##VX{>E+=D$>mdldIi&6Zx25$YO7iE~O-W-kK
z)HR>5@}qNs)z-IE@l7d_9tzS=G~B*G4T<s_vq8>pUxgq`R~W0UnF&*SE~ZE6W5Gi2
z7Z7ObQ{K9FvhAI(Y_68yc4b^`Wdp5MJ<C4Pn60*Odn(n$)c@mb<@YZMr}H=1C&leh
zsK|DGW<JiU1W`)=Ei`&?YA<OgN*i;K+oK(5F0*eYKK70y8VUtUpP>a8(Cnv<-&B~a
zv;~UCAOI9KI^iH=I)M`3={eE{9cZ%RlIKtzB!@x|HgGT3q4HmRojF;{D#=?o3|-0(
z>xGL5M?kBsv4{LxGFv^z^&GPg-#y2-a(*t@y)%4m6v?=uMgYBRGFv%~cM;m|sY{h8
zIL`}vn62(#zm0WLO3feeQ}5?E(!WNr=HR|`RaR_$owK&;BesIsT4=RZW-IFy&ivQW
zw~8Hw$8}TN6U%p3S+GTTj|BDq*Zi$UxuPDT!XW$$gl!~`@Vlx>Q!gtuJAT~4?;`fT
z=#917ykSfsikjMd=1+*y0%ms-&y9(0)K&R85qbNOmAd7Q*(w|`wbt6I7Bdm9NM@_~
zCjyNt&kD>|dpP(@f?~%51nyyHOZ{eF{;rhhecq;j{6@aGiit@XLc;z6gCBn>pLqN@
zh%<VluE#BargE9B+Nm=g{%1Hn!YzJ2r3osQz+<+S`Tf<Y($lw(0Y%n3Hk`1}Qf!Bl
z4B_t+?sO`siln9k3^bV4i12L&vah2*2=CHwf&`VVz@P_WEO1Z-WVP$?B<?FKO|~12
zJj94Xpnd|VoIHV@Fu1OI2a>dcDf&<-i1oC@xFovcgrZL6@P3v2n~WfpFh}_*2d1*T
z%c=Dq;V2y!htKPr>bwhf5PF-;LvDJZ#AOViuNwmWH5SQk@iK&JH)=q4J{D#&%*u5(
z=R!+bQ_#{vA`r5_4|rz5PFXLjp4_0=o|uhACdJj14~HgO4;A}>c4o{5QUygOz+Bss
zFPjSM4QjVj_I8I43b9b5&x176zER?+@grpB;NQu-c@pCXbla{|>=@7^0a}U)#T+qH
zlfJARnt5qvt|&wK#Gu9*ZKby184c%JWIr6lcc3}#Bkl<^!9!o}SP(?Tsa#1awPb)2
zM2N_)yqzBV?)K$8!?3@mkmz6|(y~c-1$~SIXHquzqNp}IN~dRTR9}lrH->Mha3h?a
zC)4}&KxUG@MK*DVISg*QHB*35*w@%)wG`UvX09>^N9usEHF;}6EpAXs&-pdc(q`wo
zq5&$IGnZ=~WRlc^^Yq7Z=eq3KvD}x0mSSGQjsOjE{$hX}HHz=G^|iNIsUT`4fU`wH
zF8Xy*lvg3tXKQ!Q3xHJ6cvZTP!cyn0u@-M?S6kJR{%Xs36^|-?h3^k}G%vran9Rv8
zYe^1ueG_|(x)Eamk556q!XjaTe?119i^JU{S0?%??dk-bmQcN<5VKD)`*1gP2yQ!?
zt$3=r9#;XIOe?3>HyXU23ZZRH2hx8o3436C8xiC=$K2nxEW@+2fiq0<o{*nwHT^L~
z@GuRR?KGwZaDgA!o2rZxT9|VGnJV3+pFLsC9UlpXUIN&BSzC~?iWn^|^2WY!>_&;3
zY&_;e*$O}=pP<=XI1Pc|#D|TOpvbc1@%!dH*p%K)90y`mQqT})^QfTkGAadlJfE!m
zKbUp)8-<3{4RlrD_vedoldyFhZ|cn%qowLf4e;0jOx|~8v-aCdCbLzIj7`M^BK-4N
ztfO0@+rNm~Pz*Ro)?u~P51`~tEOiYE#uHKG83(W}s_?*TkH%f0i`%JA`W$3i=tz$4
zSBa1=`k8n!|GszADxYI%`|e9sD`tOtdv?4|r~7*_jNIRwt^V-24t%}LR^y)+DF@9~
z*-b3gxj@YHL$@(-p@S$ox0ur>@1L;sLigEtkh5-n<rf+~{o-qk)9lRuNXPErP!C`I
zi_+HM6TFyx_b>Cgz^@iQZW7*@W&MGjs5uLfRr%g5TS8M6wyyi%zLsZNZH-ScN3+mO
z(EQYU;d|~xd2Ib9X^CGP4~4f}7518~sY}sS3!(Opwd(xbp-grnV?EVJQmrg(e-~Vw
zp{7EOHR$*D{{-p+!cq(A`<v%F!8@W#kU<B-bn6Z+nSi*B17YSfS+)k{Bai-z?7YlY
zQm-vlVOoNRyl_S<iKonl&%c)M!$9hP56kXNcjRt?s@=M~aQU@AXQ#V?5+lcWIjbSD
zNjUTHTRfE>v8Ug6G@Slxf0_GVnNVF54o~>ME?!+Ne<H8^9Nd@QMGjwJmpK$V_f-qT
zHva@ua^>6Y)gF4y8HQ6Kk2>o;^a|^CYbJ<EdpvL%0ghfTzQ<->l<?XOPt#QV)WUf7
z<C&D!XWOxyi2R?03H^&au6NbZ(EpSKvxR-LHK`Iz5&r!pA{`TyZSP0pW6hr|uXmQ+
zr<862vvoQdz8A;wNm|l<JXR_M=UCb<dCfk2+7)@8&33z!zL)z{p|pY#K+|Q$&;Kem
zwgwbc_2mhV>(<}-z-IY4LwW*126(E4GcU5D{=1$-e(AE$yqjDq#!G@)?tS)D9&W&M
zmoskp2=m=X)>D<#-(4K@-Pqp7XmCeTWvW>n2ngj5jNBcumrrQ=AC-Clw$zTLw!&nx
z0`xo4MJcN0_0(7!)JP|0>+Q~#khZz#2~_ru4MVe8VH?f4WWj+iooa41DM_+<h@$$O
z#xPZ$>Vb&EAjC)&BWa$xO$~x_Ic&2SjVOI)-k&sQb;PF;asJQxkzk>X_h_GuF-NuF
zz=oD_O~B<s9R{I^jIs?SR7}^33gO&Pf}zM61d@<p(jx0tsz_WTS*e!3fPQg&qM?AA
zaJNrpj<5Iy3kr-6ow_Z1byAH#@KfH>8~(sA0qY=s(<T3hae^8}aTKFMq(H4kHzqJ`
zq_s02$+@b~R+wLEmvra)2QW(qzX+usH0F4qTL*e20Fe~L38Y)=+1Ad(Qw4Z4zmn5l
zpsZ){w~Z)z54zMb0>%f!t~xoGY#@e$HV})M^c!_G6*kN%j`6|6FwW~Z5(iOrtjk@c
zT1M4PIxGhQ{6<0#iok5C5_&02KZz0e7uy)Hjtg&7pbxI^Ydl^YW^6HxuH1*z_m)8k
zm58Z{iY*DsD5q$w4S@{&qAbt`Br|`UXk6%$mI`j02GnuX{Mu&aQKVDI-EDIu@M*6&
zqsbBA#3NrhlqxFaP>Mq%ktK*=PwQCllvxqWNFKpS^w!&Wl<0xRf2fl*QF{>uT^v6t
zyAKn|R}?MAwVqvWqtZO6MU4VILNoyKUF%g#s?my`$hzTCJyevvWAq!jP-Pio+LCUe
z0ftn_68d6>zGO<M?7g(s!!ytJd*&Kd!?s91V}ZEr1<eWUg<*8NXu_`0ee|j|_l%%5
zeEn+)5K-R$DoXU@xwCJ+6lDPA<455CF6!|@={3opa@%fdLnH@5P{j62?apW|D^T~F
zg3q>T-1Y758D(o*#~Z#EoO6UrK6kbU7B1OhGm-au(EEc-fUXDKU>BTC`%7mn{5OZt
zE5>fd!k!G4T?l4(rh%3D)z?ws-#i-MZFQttu}3~6XO`D-vo1c*seRP!)9ir?in%fK
zM}PRpmIhQe+e7H#{EI8|Z%VC%_=91ku%mw1Jsn7+J4G%ss?{YI=WuXDFHlk8=z9aB
z`)eX~W42c3KmAsw&)%Em+jXbt-gdRCUweK{=WLn%evjpPmhZx;=gqUoTjep^3yYD#
z$cqf7@W2(PQiI-3ttoLpn7B*zy<V%orzcUp%vQgFChy=R)L6FIwsbSBV$o%tt4C&t
zO89oi!yH|!{i@*}jt9Ez@tCUaELFuZY@O<PWU>!A)bL#)>%6llt8ZlX$luKEQ6$^?
zrQc?$a^ec(EnuokNm)wOxvHiEEd9p!IJ@DURL<SUUAB2El7(xmo1bJzl1djd8+y^5
zeg`Rc)nE#yJKif<)Pp>uAVAQvN~gMl@chJq>f-Ah-<3ThEA7mq6CrE21jm|Fy<~AZ
z0osUZvvnX2g@CLtdM>rWDOKf}?Vq<-5Qamk3j7pm>gl$R)-u&R84oEH(>OJO8x&Al
zhrjoUx5aV@cQDWhv^-qB{Qb7(AE$f!R%#57o_T3K`?~9VUj7wddDvxL=Dj@GR^|U&
z+U+mJ5<{}p>bLTI9rovG^dWwd28HBDKai}4Qj*Plql}V;N9SdE(~o~XZZ^Sp7_c;C
zWEY#b7a`g0g<c;a%0q$vAv8oTy@Rkr{!rY;`&lN^=~T>qcXo<xFF_w|jN{*EQD${V
zRbeC^L#+@cAlppV>CS^ATFWsqBim)IX(l+^xMZ84+fJ&t5x8YJ-HCn00B(qPg3%ri
znZjOEIr~i6v*+2B4_!7xANbCr*>w1mkdk>H^%|`Hm!TKmZ52Mewuw$}YoPpvjx8aX
zBeKVHC=~7|vN-~n`tOK!WO;8XK6QmW7}SFQ2f{!j@n&8(gC_c2Rb(NGNrMj&>G0@2
zH>V09w9~?Z0;3_QZWA|;H)?}a(@fzh@s=*4h`<Xn(G8mU+7CP^d`r4Nb^t?vsgUDW
zw(FSlG|9Kg=6OrHUD%t&0VGu+LSSn^DUbrO63A{L#kh#ng{c&;_wEMTIPcGTA^v{>
z_5Gd_pWd50U+0jzf@4H<QbU>ZjrP*S3U*sRh1b2O#vf~?k3PtwF(_)GodA<QDNO#9
zK{`@K*+%t-CR=V~rP>QO48`uHVq3~h;6m23H(ngrmDCc{l6f+|{?gtz>3ple{q0(+
z_6g}~G=*dZ56z-LvO*Mdk*wq6cebsz`P2{*c8I)vmW_vfC3{gr!@Z%{eaL>n_QdpS
zW-6?uC{;Yv0S&~@I_)Izt+$`3MI7js>0VSDcp<P$KLi%~iD&GhgNo9p(c^~3QOZd1
z!n%THtYj)%$2w0DnaWU6J0jpmb!Q=uS%u8a1#U^_Z2;=lAEhCKX+5%7ZKZ*_6}+;k
zMnE9Gv|D$TZ$y$mZ*=g39D>Z&;n}-Ey0QFzkZO?tN{P@syqnNiPVkx3c_?hyvT{&O
zVvH_%Ru?o4LI1+)4HNhm$C)7>`7Sj(MoQGJ$N_(cF6$Q3%}LE|#Jf~jei2r=h6cOE
z{p!?vwNwqwFeePx=w8xW++NH9VX@m*zr(VIAU+r5Y0cJfwO7!J`un(Q*n$m^cB0kS
zD1xX9KDt_4__fA2!pT!vyLO@}GfS7JEbLAt*{U6TmQavIISg`t#1F&o#<?<hK5>BA
z>Y0vykxlk~<?cxFo@~=<K4yaf?u01V#9i9zKZrK2Io@qG|GF|iHuGWb!sS^F7V9hg
z<y7(I{=8i{W@YzUng?S*JEzGDDf3}9ovp&#r7#}_&SowfYPKq&8eWj6H9F-#6g;u<
zLltW$)?*_E;lPPQF3<VTUs33r_HnfeD=o8kd}cAjNM%I6O=+e2lg~HV#?>kiBf&%A
zM1{4H7TmVefEtybiV+z(D%<5Y6P4|pUa5s7rG=yw+1rh`6B-31%^tpmw^5@Bd|T=M
z`Rg%3&AOk>vy<QbJ*UcNK4HZMT(a%yCCYY-9{;QW{LMVrH(x`x-^dE<V8xUlC`<p#
zdC4AWw65YW(BL+HJ!r8mr&L*9z7@;X=iVODoW>|vcEQwd?9^bJf>K8HD~z(IFgjP-
zxI^7ttQ@2Z{8U|0-kRH>ugPenz88(7?7L56w#G?tt+slKra7l57|v)Q+m(88!nM}2
z#BkyuYdI*r8t1~78P~)LOquXK&@&-+oFZ|O40D&=6SHxj72d-k{MK=sJa#9q`MfK4
zcT+3US$8vYZeqrj^G_7qULdHQ4`+XTf*Bez*?zLDCVuG_rY103!($Wnh32-2%~A)H
zr8RD5W{%GMJNwrG4)*AKPQ})D$%l3Oj)Hl+qVu+wuyPBb7qJw929hG8KUHsN-yLmm
z--&Yz*=)yQMoeAG=5wsAPO~EECgS?5BI5e%0Ds9gCVb_@M%({;k~n@6+^ZrLvFg7S
zeKyt4<ct<Z_QCY`rA69(5rc@A6X^W_x8O4;S0`V^QcQO;fLgU{=Y07qRd&AGq5@-z
zf1FkMw>w_`60_CY>hWOVH(anUPtt&zM-~bR>B;mogghc<+>fT3cu)9|G`B)<PFzL+
zjr#olaz#wi1?iJs{RmD?^y!1ha+$5EkbRN@pKn9KS(~Ns-x>78aD68&OjWh$pVbxE
zhB6K$nG^9KRkrz|nT^wyio9V_D~G&FL2x0K!@t=4sf|dYc!9WH&yP9dat+m&1qPP`
zOK%)O<SzPPp}wmoj&Ma|2@%hSt`=qa9R|UQ`k;8<M$E~B3}QbL+(8s^4+cZ1RIy%U
z*COe9hJIsjG1;W7$*gGn<2y0MOtY<XFxg_$0|h)77rL3+Dixxu%RX3O_VR{(*u98l
z>)v3OWvGV#u*sR}<wh1)Z#O)TaYW+ej;OVQA_|&-Ef8;=jt}#i_XwmW+!|QEKT+pd
zt6YmQ&u|U=PQ9AT=q5*Qi1Zf>p|}{1u?Rbyx1v{OtBbzwipQ;Xs90@P#ELGnx(Hs7
za16WSTn8F+N9(pa(FdipCR=V>{2^wmyK9$<A{|J3F>|~-k_j^mc5WKJL<XyyY@<gi
z&jC*!(H}{lOh_r0F?miB6|LMVsCEKoYmB@XziYDNEfYAwEe=TxtV5aAUyp=t#ZkmN
zB=<;|kw|~B;9%$W^tYg9)c+;%=kc+cY>r<GE-VvSEBNLX_d=>Q(9N5Q?DRiaU*fW3
zx{}ElusSu0DERo$rYJLxy)1>^@!)giPPy?R!mP&##Wzfx(PXl}21S}-l$cas6HB!c
zu?0zlAPJRymxgMd9}tLjffVD3KOR+LJ?^!#SG6MclX&~e(adfCB#8Ug+5LJ+s`mWp
zmhv}VRkYrIq8I3?k8h+DTbJz&WY47%R&lj8TFVWM#w0^qbjbawadLLFL5?8JAAX3g
z{UMCl7b#Vk^lSDAJG(Ja=34DuUfAmEEX)4edY(23-@?&|Gi#Wl9F(e8s%F0O;^Ow0
z=>=y~NLJV_h2>HBSJ^x4?-RFK6;Iivd1ItU;^7xhs~K*#B9&TQP&#Sb$ukbjil|*)
z^Gymk_--#d*}LZZ>6x%CmQG`ssmb!K$SjDe+v5|5!hC1hI#QM|{oZ&7%xz!zE`p8V
zPiJxP%~o8$V;k$<Wlb|_$ca`Jpu5NOvuob0G0F(=JgW6>>uR6~^H<yS@-IdMt$Wvr
z!oBj2Wm|ocC#{&&8pN^MYFC`6uKy8P6(20NFk2V1wU24FH81@)JF}kRFI@6`7DD|o
z22me0o0IU6Waa0pd9O*TH(li(6U$LBIb^jp6|P@M$u4D&1tP2$2NX6z(HahXL-+_*
z8Wb#hR+|s-aFUg#eb07gmD3Vpa{v=nN+DiQwq3m_8qL=3Iqhw5ajs7C1pWGx8~qB@
z2Ivp1uJ7I={ZdGKzjrS))g&4PYuB8pV>4a;_NQs4SDR$+UY=R+->^8&hegecMfcAZ
zr&YF%7cYhNdM+!1<{cJ(F*Yp>gxA~SFa0|cn<Dv0G+R-K&Tn?__|+u5O`R@!S}M-3
zc|+Jx#f${3<eg?Ju~Kj#9bLi;gwI~ID&;j0)ZGOTPMt~;>MScxkH4GNeU<evTY*0!
z@0xvUV8-eKTkZqycIITAPT611mKyYgT*>0<orh&e#e5p{nHh69yPzz7LGRD(!VM2(
zy@%{FOyHUDO;+h!JzaCr+OhX!#iiY5G0?)*xmVdva^Kq8$KlnTM560BX?R;TPYr~h
z&W^G{$m<)KGul}!otgb;CvasjIm`8|J!QRoc5|EtXWypHj)1Y6$1Wa8Z#$^Q=0{aq
zLLQ~*V8wXfP)P6A)_8;aPMr0ah@nb${Xxmyt_Xb-Z9gD=T;$syvkwzre^c*y^fY~(
zS9}(-pQU_MOYPJvqrGTdc`Q2DHkPXD(G{zLaHGY$=%6z|%7|pan|Hz({P{QMGII)#
zgnA?e1YsPa0UCBeYtY*V*Z4MYqrl~)M@XC8{4M$wko0(yzUZ(MuMVkPAYU*v<Hr1x
zO)h-~%F{QU(D^}Ze(yj(A0$bH1qnCuo}f?RW!!k|FKr`p_oT9Ua(B*7!;Q9)i6IR(
zUq}^`xOSC+bv?1%#!x6Sk_4H-Q$aUq;B{zG7(NEu@{o_^&BT?$2Lna;3kP*~4r%f{
ziKPqzKfRj3Yldd0)k9F|@C4T=IfrF*W5GQ!@{H7~=vvr{o+jJKri}@$r|<6RoR+NU
zM>U?nNnvATf7C%gt1gv^DsOQ`oq!<3D`kjB)J#$|dRAViPEhb}HbA)p1+{w;Hp=0j
zXcM<2ChM3rc#ZqC-uE!$=_bKpPV7aD#lgdfzQeeDV7h@@$=BkejFKipK)~hp40NaN
zD1zg`6UmzJ3v~`EO1+CwGns(BuouAOngkdH&ZFy|N>ieF0xwS1aaZ33Si?x&DDM#u
zYG}#xV3<ht;e?CLHYjhc>}^F9msNQNtIdm~!EAACKLIbyVGxQS1rM?rPChpreGs;u
za+dK5Yk7JyYi^D?+g^nHRk`J7GdELTWX@xb*rOBdmDb|o<0ncNKH(TY5$IlPX+zsV
zIqbu4XW6Q<wfpwe(>a!G1Rab+0fRIiX-{J#Gi>RtY1i^Tz--;aWgm$U!P%u&gw6G=
zs{Rt1T=c@8I>vX_>|eQH&#t*R@X-NOR=vi}WDD!IaB~OJTR0qd`%=fjR4D&!lCa=h
z;&MW3w=7<9`X(p%ZR?E}22@$ThQ-AyUf67IL*;ZB3^!Xzfp#q@rE1>EGY&WrwfjWx
z|F1`sIB{TjuCs2uK7ix5FX3|(ubZ)(|J%{DxVYVW*nG3xxT5vfF!4dYOrg}{0E7Qt
z=k8bXIk$GfjVF}yekpGks@+bMA8@gq%W$|Uz8Xm;#b<tMEtL%t-E-PiX6}+Vh4kHR
z0*8Tr=yhwG)jE3m@NLfi;U|^h>KF2*>heFmvN*N%OPH-XT&lKXd37rryKgv`XYt)u
z*`%^p;%P<g*47fq*!`OM_?3H+y!67FNO(VTaiY6;_7t0hFAW9xjRKAo*}q9RB~l^1
zyg5JB@mK(%uix{rq*K>)FX9jv$N$4iFvr;>tXDaoe2^2ZrhdF*i?Sd06;j#8k>a@7
zT7Z(9F!55VR`8%e8<9ub7(`mOZ%pz&$t*G9duViHK&ke-b}=8luD@_3SFMmb@BP`U
zXxLXWO!~o)`57Aa1<&raHrx71IR6r6>m}dFm(F3w=M%5D%KcGRw|7I)N;aj|w+?y!
z=&$lvc=&-w?YB-)C^f-R@XI`7cGaK~gi)yui|4bEFWVm<--$SrO&8dY3vnXv@psd<
ze~QIA*^in)lWCWh8-@6eKqX1Mh9*Bt$zmpoy}&OThl8YQ3ib=x@@EE-2l(}!AzJ)D
zv?cow=EO^F$Nw~!$9~9q;a}p>1_-`|o$DK72|hkef2w2PZ(;m@F7vXq^FXg5Zc~`8
zXLcmJk&Rw(EPAh9FKrpwwp%U@vjd$wkM65{I>`gc$BVdjA5Vl+(n-h76bHkYuJa&*
zA?&)MG>bd!<=X{g_Y(uDf*S}ZgIzEeLlMhRb#JUhN;mqhL<a=ajJoA!ZkMd4yF+w^
z3Z_T8Vtu>{JqWUAgKMT;Vi6xyv=StFHNwm-@RYYWlq}Y?08%J=zr;$l3;YoM+c4a&
zR3ie2)Q4X3d6<grmiIz1)U95LgqzudwqqvXHA1PBe?comKRThuxx#%YIBes71ini5
zLTEGU$LO0UJAo0tjOy$;h@OO%s-?0zm=F<SJr#b9K~(f6tf$UcN{u-eftoj}N@pA+
zO{Lr0Sy!@wjZkxKYV+75g^ReuFR`TzClOOc2SxL8*l4&864?zNfdV@K^q!w&_nJVu
z-s5qwlYsEedSY2*&gPkzh?oEZ1^9R$qYFNpTSlDl2g7wFK1M3fxG`W<S*2El9|4F6
zXvqp9n&PNT1)+IH<<Mzgb|g_#a&a!$lX@g<!Qao5d?_at<e^z#UD*oOT>)_iGMz&j
zn+ir}+bQid7)Z&M97?k7Axb<<QUR&WV3xSSz*Zs_j|5ub;u)J1_z#6GV!bF}Ctg`l
zAc2>Y@cIIPs$dk<mqEw_V>*~Q#HEHJFyoLoYu&^NrEj^<Bdb@_R6%T_V!Q|5s|dM=
z5AF-dmR>D!Ux$|%w#xBRoMleV1j4Bxo?k56D%k`DAW4#;I%ZzSFj~zaa8ME8nAhwV
zrP2g^%7F+n5vyY^@KUQwrLEPC93!7qQ`w*?5QPaTm06ON1U=lkn*=|^4KTxCnY}Mg
zSg|Xu!*vwgFT$86l@fvaP>YRLy3g<n{6<3!p{Aw_{<h&8B_UblkRlurKoW69(xyzn
zs8sA)OWB@k62WOC)XEmBlr5gr-?!NoY(|OlL^QpQ_nzYByqh+oN{wk5nI_3j1hcMn
zB*h5$0b?0-%Ids}tr{35F_9#=$SWdbzJoe13th`D3LIfUJqNgUQ0dHL6f{hDj%9+r
zn=NEUwuMOQ{EX$7(WoD@B7`HgP2OVHE^KF2up{h8KWpYlG6G&{#aSy{O?LenJTQrf
zM!*h<?uiI{tEC^26Ycl~ehGvbY*;ORq&p;A@fr$kCZUb(ww}JrTejoKF>NArfpnQl
z>8KSPBZpY%pt41uu>FGdF~at>(UJstMB?Px1qT*s7nK5-tmA^7L*oHTuITI<h`SWL
z0x3QBM<Ad(%QDALPZ@!Oz&X-oPnrcDw%#w$qlG3q5gl?}rytXX5^fJb5B3DCr{Gcd
z)=dhNXu(CCGTI9gxEkAF-Z?Xq4%Tx|0nU^o1=YA97Bm%Jj1{kolcxdSdYn9p_41&g
zm~LLKz{l$tmzZ)0olkPbQftt$%HP@$y1l3lhA6#K$mw0C=|@5%+%Y#p#1j@YuRe|0
z+T-P1yvsaJy`D}tf-!xpWEG5M<gY<cAUF=hY!No68=NLpFOG<mx7UnYK?JrFWg=qI
zCURvG(sNzUAg4Tt)xDE>1@c1I!$FNM=FszaE<s?8dH^ntvcw8110yDQQdfne_XQhs
zn#0@6Yo4?fgGI)`UNJ>gByse(NKaa@VkOA}ZVbph6eL+AKoY4)<Vdj_ROqn*u5qzK
z&CCxh&=m`85{X=<LK;vQ6@vW=Ownw*3Xqeeil8UYcp$bnnAM_QnhH%Z6dC}Jzw8bm
zps(CuIQhG_p_&;DU98?CkS*~E4Kz;+0;be@xH6csg;<X~XH~Wc)Q>9OW8;N@w^C$;
z`7Vx=SBYw<eB>vLnuVZi^Xogvgd2LD9fD1&9}+P>%I_tWFcc}43UBa7dGn|#5Mgw&
z`wpqWyg=9yJGg_B?ocHfw<AQG2u$7jN4TXE0fp1&ry7OVi*w+vqe(~Beu6#6-9+Xh
z>M_cjy`8NhAoKVjtQ9SA@!DL(uT{g2*!$%jOq2X>KWY!Ah~H)mAKHUHH268h<r9p1
zX(qxS#0U!fTJ!dI={4(@h4gMl?=Sm;kEt)`3rxpyeyHcTlctI8Wiu=sj*#6gE-7}K
z(;%fV812w*x9Yer5SgM8<f2-EJ;1j$#)0*vyNoxD>3{v@d1hZ<r_#Jzxye53VUSH`
z%n<1t=D&a9)SYpa<}o^_t;;dypDMV23lTlY3tpL1ZaEXGMONR6_o|Y4<aNaV`%wqy
zZE@BlK5rmoWHcI*9){6*A<4L`o(rr)sIM6fD?v0IopOpTbL)r_l!2-z@UxG8c8$Gs
z6J_}P$I5c%-+XvZbJ}Z9Ug<16cvVq+=D%kvoSQk%dt*G2o(n!EQo>P?mOMCC!$BE7
z{~OA&q<y3z3^L5b*Z87p-kUjZ=2SMjx#kQKT$7ki9+7-xE=DSNC|voGC7#|o3H4JS
zF#Eyne2D`0Zks<^9Nk_iyljj7YOLBnd4p|m%!fVwc<1P`FLLnk$!%}pu@{x~^xb6p
zG%q%i?FPr+_}fv4PJ7WYCQ0j(?63AZP9$0RHYQrefU1NnQmT}Lw}&Gf3(2g}oDL~f
zfk(ld7X_@2#;R-@13hmc4xS~Bm`8ox>oBOUx89i^V{tK7z0_>L)1xj#jJj*jZydPS
zi|RvnrB8Z1^Pk=-UBnK5Ri0Qh)KvfMaTi~kbHZxzP|EfSL=xQaZB|sCyIrV};HQf3
z$?b-(F_iz46AYN%s}v#pA4hzC{MQ3!EVlw>bK$Y8H%t<puCuN3(|?QZ>HSO@^*U7-
zg`83aZhZyXue||cHe_o5VGg&d`@^bZ5>|i6>SdV9^NsVTmB~n$UVfj(f`F9UKKT^h
z4e@J@yHN*)dYU~<uq~z$Sht3KIAT0#fM+{dvHihWb{p!uwSq{>XEE_QenF)f8$zV4
zb>b(GR~O0IRhS3k`+gVH!?7rhwrqyw5>Fqw2mUnk-7}L#`$*dpyC=8;+0wI}IXi!m
z>#_e(F!2rgReuxnDo6af%El*wb7s(hyvs$mqy1Dloqx-3Y0bw;vizG9>)8b)V;#$v
zb;okJ_3SfiTcCiSSmaW!aE4P1j=DG-sDypQvCT(;$T$Y}ksOAgW|rFcGMT-;nP0QX
zbv}T1l#%Xo6ddO5rx;VUT9a*?ek|9wR6Ns$Ls7)p$(=~I<CRZ^>>)utPX4hG=`uTI
zx2qQljsQ#;J}p%DGX?q<LY|Vi_?-^|C+C|kv7o$OX;4zkRS#M{vO;lxLd13%Cq#py
zfNP&1G2F(0L#ZUPes<XyoOY2o@oi4SsPP8RCGS!|c^JW$Wx&lQJy#%`p=`B<7*Hu<
zwr^DMPzfVF8@uIpjn9e+W|Fd^pUWIS2NxN&i)7N=#n9#<3oTXSlGdK(=ap&%Al@dg
zRE1mu7dyl%iLK?6wRs^OIjx8U2>d2xl<Hd{Sr)O}y}oSByqb8gf7n&|ls!lo==7M9
z#I1Qqjn$7VDpd=<_5AtV1)EFy9bgmWU*H#|nqn&5Oa1DQ1nptTDa6(FedBl{Q*n<l
ztl(`%ElskGrKUcn@44TW-QE4rL7p<ukcus$H8!n^8lPHB#z(I`u2is<bD4qiR5w<s
zbC9OWwIT#a_y-lJ#T*hiCRoAIM4OAj&4f(Rt8L&g7s-_M9&mfY3JxI~LX}X3-y5Yu
z3PQY^H@>GCTlxN{MI>>F&YFU?p~Kv^=9F~Id5ocDLb9=79jXwdYbqsUPAq<=PP1l<
z45XYRx-E5eMzs7~fO*ZRR~1-fJVT?X!D>hB4us@&(FuJqCvEzP6m#gc>5q2PgdK5+
zXeE>E<3SPrAT=+yL*GmO_OzGYS#S1*TPa~2+(1`Pff)dW!a#T&@8=?s<1A9|_R!C#
zu*M__8ddp=b{DHl?3%qf_;_kbLwk@D@@IpU-|Vm^^fuIVA;kC0d#C-|K7VAAo;a-n
zajb$G+1aAX<Cb{du(K~;)XUBs%f8?82U%KT()z+%olb4dP)J~)%v0s*V$<$@iJK%T
zB#T4=`Q<*k@*e`eu)Fp}`-q8Gnn{in-C(rAaUc?Y^s{D8)Qt#muvpRU!587*e$?!p
zf7cclw=Z$&0TZ_>Lg)F#{)0qxUSmQeoOpc^oD#rmldLgYQ_E1zIer)pSx`&%3Q#tg
zt=7Xub2}mzKQm|hyBksMg)9Gf!ruI+519Qx72;W>BDmzb%xI$vw{K&!kO|w^uG-KG
zWbWzndFL1=O}6k2WVr?V^^q=5feXx@{yNPYvz1+Q57-3TFK5`BR(|QRw_6X%R^5e;
zdl@C_mCNZIsJ(*h4Huj587QUn--43|RvtZ!S4buB{G22gtH4jt*W{7cxdmBioAnWI
z#XnJz$bo;Iq(jf79f@G#Xs@3rvKVn$*4D*`X0#?wFAyfRe3MQIB7#A9>U8S0BhDrW
zIDRqPb|<IQAJYcK-1l>-uH`=retUz>zW?lN$bZSzc{cUzl8B#Nn{@MEyL-d#`&DM2
zwA--Gr)Vdy$82Rf!F4`ZhPdZ-=2)5k4%j&F@D;vP8ymfLzs4qxLA`RWL!-ykzj5Qu
zwuOe)=dMi;uEV4vZpJUauNo-j5b^+Su)2qk>_uUWsr9R3TJT7_WzW3QvE7cCZ3csz
zAEWxtwgg~wZ0WHK%nQs87RA#reI~v$Z2st1PgJU=2t+Kje)}wMXAZ*jezR54XC^~>
z*J+S;zu(*DTNnjD`#@1{@{oM&ABtpIEh4Y4q@i4T`k7O8$LeDRZ4PVsn0ME#mb|4B
zut}#UjxXA=?ki@aLW*xrV0q~gaUZ`09VvAcY!F_S?TmG@`FuNb&X&f~jrWI{tuXyg
zLDeeQB?XHdnyH`yfz$EY)V<rewPTA&ak}neu!G*`)6gTd4QZ!V)eR1?$X8mDeGGOX
zeApEn9&oCyd43f3<+ft3*=~P~JF3bZ`vkj%;wEf)88TWFcO-pL95~mcE71fMNDOpO
zsH`N4?BsAzweeXUG~~?BMhr8mr(E=naTzFfpIW(nr_i-IN|?a6eB^c;q%qk|NjOMi
zl5z>D^{ZznaZ09svIW<AM!0@~O+P*p6|Y70i3<z!Xg0yl$4nZ;CE6&o4{B|28wZ@N
zIGYUXQlQS?cPcHphjSom^ZLM_6DIQ@XwJbeV778ns<Y!|$h}kPNmHxp^mhbAW^gl7
zPjfBqp|U-H5n0O_2RuY7nZ{~6(A)9$eM8FMkK6GeBb{F10&e>OA;o4y=>H1}V7tch
z(jL3C$OdBTS|y-zwS{ZqMmUam$=6f%k-OXmT<alX@HR$sHBmbPv~*qbt@jW&4{D~7
z@+7(AQDssgL3c1`{&FPyG6SJtQ-R(#lJ;z4#+s8D+58bjPQ@jKWY-NEq1JVh@v4*&
zGUss2--AD@Nufhv*$v$%N;BC7>N@x0b`k6eEH3Xsw6(NE(-qWlcdC#6eV4gGjOux8
z2%=;%)(__Ig-qaEPjU~`P+l+WrW_jjB-p@{IOCpJL_Lw+GwgTh5%HA5MWQf=8$p#M
zU2I_Gdf#tSQz<qzlKCcp;|E`@jO~Ue@F)ne1)bhU7V~bgto!Aye+)P9v90i<SvNa(
z6vJ&wj}A3Br#Ij@J}mBiFxzHy(K$=G-*be%OVI$!jd_;W*Kkus!5Xxp#)2%Ft=zLO
zS#J{bv|u^IGOSmbCj4uiB35)s&_86R347dQ;r3n6<0fjq^Du|`acf?YPqTBS2<Io`
z4R>=l_x|17RG+%y<Liu#oMzpp7z*X~+nA-{eLQKt%>BJO!PMoAizq{TYnu}9jFv8V
zKJR%VK9x4?N_B3pq70WCm(h?1y)H5gypU8V>wfB2#sP#oSKnrfAH8WSXARNup+nlR
z<;=T#-hgxV^xt%dM-%V7gkItUWv^Q&)6Qv^TEVd2r+11NHPiH~N5{!kItdWE_WKy2
zgGm7B=FxJWZ>(jv_W8eMr;*4nDq4*d<FE+0;t?g&AjWRLHa;_iKNvjEOy2wpKFbSx
z%j>K8>KmYdAG+9=Kly(ib)F^j>dAKow>~lN_{2zN{{6S*_T<&JBC|C-a%t6AbWAlU
zTO`x!B}*b#Gs<{ATm7BxUy5JJaqi+vOSg6+Sh*}gM}UXVNV7F|zERmDxWzFYENwd~
z3=fkMo+@?78x(=O%`)uC3C0ZnM6dZ#9u=uxdQquD1}8chduk9~fl(01PHVY#<g0P&
zBvvJ<)zDYHYO9qe{JS60m@`#i%(ncqqbU<eir5T@?a>V6KOE+X7O&Z-vn}^;uUNOg
zu~^O#4!_JdqMv>_nee60z-ccs(&=?y;qu<6ZsiTwazzWXJ^#6j*kO4kaz1a&WdIc4
z$JN%j4$RtZER}>`_|}9=B;T8P!iNKrO%~e~1qY;D6mbAtz~~$kqDF?QMXRj|{_DlL
zg*VI&yx8_xb{NoSC#c(jLlYkDJPpY+SFvqRu&uI0h(Ze~<)FcV2UC2;S68P9MW(d!
zVLuK8BIe*rejiEC-(fdB_Hf=68K1wIdFs~gQU3}Ta!z}hl94`Le>d8_3yPeK>6#1s
z%;J32on&~09j}7xJ;Dk*zShS^PD7%P9K`}~E_7OusGd4bH#{1A+2gCQqk&FgG?6Hp
z`Up!0k+=HVz{8!qqra(HwSPe&8YkZifTU6-Ahq|@Uo0237FsTzh^Ka{F`+Y;+<~i#
z8V14#c^wgfUwnW#P60aIi`?^bb5t%7T9=$DCS{@*)HX6zo(Ecf9dVu?6)iGvjZn;h
zA@l;MWgZ<;LB1{><=n+M5rS(xhdQq~H1>r>`XS^iyK&k{8{v{NFqA1Nasrul6sb_C
znpTO%1`j3avb(LgRf(R0DLDSqr5bpfCbhb{i4ld{-$SA5e6;qIr5FHRrdez)b1EG7
z-KoH?wLo2H(Jwb%6ydo5nPY_RGn;fh8R(d;;7HPLCgLtG+@xo70mVTEFLp}r`OjaD
z=qu=EB5!k5>Y>0Pe12%eK4f40`(pMZBn;B;K&&eTZ?a=QD_4VGw<I63rr3+^0hdZ3
zbOW+=#{&^c8~2NRDli4xK+7R0jLMzdifm&<Fyns@Fr3vrGzN6dSK{>r(LMt&n3hvP
zW#0_eaV2E~H5E#y?3Veh=XOn`XPgzgD`$|W?ZqG>z%fFt@23c81yP?RhJ{V~h&%k^
znv{oAjThS}V^h>oYq*}D>RGVfqR~Jf8DruMoRkn0bh-$z<;Q>~+mKs!4dmfdiAzk`
zZPPPyi4bMc6PC=9I8k9SuDS4lX8XcO$ZAM(gbhWhWueHBCPS5eD#u8gC;H|5GDWDS
zdeM}_Bi;B_E_1x<Og$sBd5<#ynkWz`HeKWadZXJMlUZaS;yuvsD;xX*=Z?5NH2Z^5
zga%z~w>!@U>F#-36M7ZuJ?lJ+i%Ef#VP>P3pG_meofH_sqe0n*BgMJ!{t2hAP<S6V
z38#b%(!6}klN&>_H1d#b9AWb5q;UnL{Rknvp>2pQYKZH|H2*^w_gGjBcQNX};Oj^?
z!wV_b=66)*nWcW_MYB}OTf$rHtSYs$o>!a5d%=f^a9gl&D}4;xsf#mjr7^KL4YL)-
z?_zjyf$HnNr0MoJs85a8bw1!d$qxso=)2&x8wgXZh!qR*<FJyQViP_Pf?}kgxeJ-M
zrp-qV;L0DsMs|3T0rLUdklj=$lkiV5HMK~#sOX(+`Rv6wAnVkQzc$EPF1J4an_l&z
zY<u;0aW~;{7iQynmnOHOZOmCDkUYn+E4Wc)Cy(;`y`NrVPC}u>A-nRzhVTBfm)YjO
z`uEJiKOaAr8*aODYX0VXc+34xP7nL{e}_)$Wiv%ATOCdm-F%^%g0zxKe`jO1v}?6V
z_}5Q}Brm@oL+w7y)?W2|<?CO2`)cf~@B88<@g_Mo|EKX7n#09XEM{xr<!M#fDBhfq
zDx@^Tx}Soh!9(KKzm%R%QQ08G!GD$eT`PxD_80yW2hw01_OR02X)>uE0ecMfms)N0
zgJ!El7zLGwB5{9?s$6Cb6P__!`6ya^eNUOR73j4P8p?a#=)JIQ>4O5Ay%-Bbr~_-V
zYxr{MxgW4Vs;!He?_Qo`mmp=cAG^hso2Ncvr{hYpWekvR&MUQFeYT}SA+A|%W!?d9
z)Nxpd#c#}3S+;rg3_Sq6pV?q@bu0nSVNfi;ukcP3Z4C~k&giU0LfzKD7h3CdyTy>U
zR}|OKBdS)>@<q5>Tx9Z1+7~#fHW{+Djyp+^=$pV$hioH}gS$QlG@pMd&e;qS2h_Y5
z$i%AseU->q86DY-8Mk&J3^H3Mw7A)Oa?+XI-}&QDx{31E?%UL-7OO|}Qf0Q_YYN0_
z>k0wKnOdmh0+TU_%nK&u_|1tto~gwY<5rGj6=v%UW~-m*P7)m&MLzXP7wZ?)!Ehy`
zdjvXpAVpI2fzf*++)j8&UeB+Ri6+SHAty7Ssl+Om$>xagZPjn3flMew-Xi560gm`q
zP@iV0mfNOc`)X%^@dgQNehsudVsLSQt|i#*GFZx0M2^7oxh<C+b57&3NxOFICJKHp
ze#+J~OW1ix3x^?Vv*x4+jk0vSr7!Q`7F;Jv{DQ$5ula{{ZA;=%ONEHl-r<Lcc0-ds
zPPgoiX+p5-E#P<jU^zZi@qT3igMvkP6W8uNNnVvqJ0*hNG;QJ&RV)+lE;OOB9WTmz
z;U45^?LhelA*cxb{8A=q2qh|~OACFf7BS2XHCV^b%SBhJG{J_9EjF2JdOoUcu@FPV
z^91wR9^Ljy?%p6`p|)u5uEZ>TK$x3SqG$(ZUDa$SwCyjR0VATr!Nd1pinhYT!6bWP
zkkKe$f>v@uYIMDXP1mSZVf70M$8|}!mm0m}XOliU@*WDIjom_h=lKa*F{a5Qq9)po
zy^Tq?QbSHhSGl&pYl+37R|yU$1omQBv)<CuE9~0<B}`d>Dfl&21dY=z6EfzYI>F22
z_Wjk?Cx}^xvFC^wvT$NCRjq&>tIc;I91U(X$pA$vgb=~CepUA_h|(!mF`*x&sj{6A
zW7dAmVV+S%&83wVCU?#jL$!l|jgf$sFcLNlY9BX{s)8f59`PCE5p!orYRj;4CcJ`^
z{5(IP!V|*TRzy9EJikDx^vmv^woR9Vc}y3_?{FBU4ZUS~IEP)aWIEBkb_Z4c{=3xr
zeTzxA!nVW~oaI+*_j80-<u^xH+lJ#Tw?eB^s^$?O2AHjDBIA|X*sXfAuEG(*D`y+u
ziPHRC^wtfy)|1@LQ?|Nb_F*-qI4!+9dQa%I#jUtG0tZEfuQSX|H<MSm1+UfCEkb3{
z<NH<BT|68w_^nq&P2I?0!(C32dg?Qww6mVhyHf`3O)D;ho?D(PC*5K(KT*%R&Y9cX
zYTUloGCs(4inwpEArDY`+C|1&mhq+!0}+RMb*w1GO>HWyrKugYo}grk(1DxEG8~PE
zl-}x?ssrL$BJLd=TiSi{oi1iu|9pHzEB<hhCAA*2)ox7wTLlNwxsUvHZ%z!N;qXjh
zUIDW8gObfS8F4Qz*}mb|A_Gw!0=bMsOyFzM7=C6u&WSm4_uP~7o}{Z}QW+;oIt1#~
zPu<E><|=<u7A~6Fc#`iuF5LV4$#cbDnGaTe+sfO|UBtlXH_e@dWHV>NeuDwYqxF%Z
z`0p>yc{S3jl!wEDLjajaB13?v$|jiffQYexW39G|MSp=XDvYBy1=6wSmnHz7Hy;Q@
z<IpKWnFM~uDV^4Rl$*IVTNk%Gv9nU-!Jupvi)%NZXMuz|1_Cxmv}cQlUc#vRxh50T
z(sha_+t5lD(?*eh_@kH}ug>H@92^<)25I%!*I=X~$QBh(yr(YvUdxz|F}4v{waK?^
zRN9q=^Vl3u9QU^JV};efkyq~RSNc`V*06rln|MV_ulABC75}~F>d^7U(xuirwauQ&
z_urOjA2EaG5#WeVRx+L_*?|ehS#9-V@$?Rhnpv^7R(^a3%{P4%n8fDuJJ{$u!K3Gg
z7AZ2f4WN%ij)s_ROBQ}A%xkrEwMEGFH@WnA+d<?3{#U4GuCHEwK=ck;i%j&c886pq
zF%7s1Oa#XVcnf2@bD&S9zL|qrrL>iOtFx9peq{O7>i1Y-ynXCeUr7R)t>-SvD@f9=
z>ADk+^BgKe&3J10K?cb^tL-suy%v{IpocnEvOknAiL6Kcc#zKy&=r0l5WVd{g3(D8
zStl`R&wZdt_hAs<NAC0Z0gS#R5+BHJ2bl)K)9pijCt}do6!dgH-*#JrvHShH)6?BB
zFDVP_>7EZl7MMH2ZAHJC!_~kxBwt?#!jgukDGAk-3#G@p&6sIR^)k)FmrCVKKbmJM
zKqDyR!+~56FDc2~@T3P}RT#k}zi<V18g42-PaFJ#!YBbPaR7q+o-)>SjO<`Yb<NOz
zJZN*k+Hl4^M<3E4jdSJEm5<ng$Uar_G}_7`oXPjZ4GE?pf#s87-c#yYrNfovTVKXI
z%l*0#QA%7>`pcM6EiR?axok^YZC7mB=Db50Omj{s;Tn3&93K6+;cN*Gkc+J*F=`cp
z|B(=Ov_71+I~+X>>&yap&u<q{*utbJwNe5Jx~+#t;6NG*xypA88|{ad=n&T>EieJV
z1b0TY4$=}R7Hp#mAQdq;v|1gJ=*|bEll8L+<tR9%W?IDZ#Gb6Z1)HYGa1+%w&C0Ah
z$Zn0mX=z0wZ)E1grS4OZsD3hryk|o}@@+LXn%~W;pJ>3tqT=0_);9*Qe;%(R@#WOa
z9*A3l`vZy;DJ2U+yzaS_E+Kk(<Jl9xC+G=Bb<*Vb-Dy;0+Qh0HeQw2dds2f<7}aL<
zp3<qtBVbYu!5NqR(3CB>Hi~K!Y;7Q*+F$Sr3RbxjR~q_=h>1j|`pedEV}Rj1gN_5#
z1%4MeLScU~8=5w^pl~Bu6E)01e|ih355Dzn=SBSRmVM5ga8XV>JKMxxRrJ!dzrt97
zwf&bSCLTl8`VVqrwl4}A6y@b-F)~<G6)n;SZ4#ag?_Xona#nBzC^#LXv>(J|`NO>I
z#c6!I<}UV=CQQie)$p?Eg-bSgPbz4zI0NTnyjfdiXERq)lFHtdH4L;#xOYY6!W!oa
zuv>T`d<bPQS~~V6jVrb4aUZ|>qO~e~!hd|?0?RzBmoj>sVo87XXIMTgor9SlCVi7f
za*%)B&Mxl4^#fi_QT2+7$^bjOBY;c;tD8}64%##%!a)1aPF5OS&Fiyt_es2+7Z4dJ
z+S*&w)4*@v%0AnxPc5kP*?j-sPb~od!4R`$S@ywSH~ZVqT=Qsri4bzeO)lCxCw{Uh
zSv~VI9Q<{wE|sMz8&wZXe{IdWU(c4yYhHiMX6|~UaEF6d{o+<!jNRF|EA+X<7n8>E
z0S_m8_6{vX8Uk*yfpo5Z>H)qRLWvgsBWLl{)FhvTH20}X=J_-O=S08P&&!bPz^$sD
z_ZB`mxsl&{tu1u#%-q5s9FH&g#MQ<_MZ>6@+j}Tcw@u;XL7=|TsqjefqEJ~b!Ie%m
zWwbXB`|>l?@$o-!nU*S*Nm#3ocx`#HGmpM>PU?><l5e4q5@95GQJ{^Zt6%Kov><Ny
zB>3%3gwyDHO#!WGI(fuc_o(M*s^bOv2##dx*+-mEBf#g?)bjgW*O~R!Cyv|H^_;T=
z#D=tSOCFbD=^(84v#5dYifpy9Kt~Bv$7Q|QS&f=n__kXQIYU>On%9bjT3_4;|HmE1
zo_8L#zx}n!ZJz(EJt^Twf+K@{rEI&%Hg%0><bB@~C%4}bZ)1-O#aviB;ttZLz4-yN
z?JMlq&RiIzt3){aU9NQ}#FsncHxWfY7IY^eds&#5wXFK;0}&Vuss46)`!-ssBJ>`2
zW`8!7b$#=cXz;@wy<LOZDhPJ|4VYDzE=K=$=H2G?e1+@2Mv4NA$c}0Km5)r4;BtG+
zzIbiups9KLOg5jD^euF^3F?kbL*ngE^P>xX+Rodr(E)s21(0Ps61+<*x4Q{<sU$}2
z$Lvng59NK|9?#y0>17J14tA|2%xx}td38M9!5ZF-oim>|rZR3C_UO^NZa;tKpmqYv
zupfip)B1AnI68^I2&l42C8eGOdYXGLAFsHXGdE2`T2wfJ$`RznCXKyPAh8OZ_qa@p
z6Cj0X?6(|UE+-MB@*yR)9+;F}8$Z-NP2+A-?2m8KZz-n9bwANwOd*7`;9>;3faSJQ
zMVu~28NvH)Jau2l(p)zto`n1cG7LnAw)x^83v!=kc{N7efvzS3T9D>;6({D}#L8bT
zO6YN#Q&f#oh6U&+;@pE)lGB{HZ+iiD+ob9;CSY7tPv#tzSGq1J?%p*ddQgn|;6v(g
zG6#2F00~+#yeJQZc!_Hic&kT|^y7WscbKQuSP;>kS_vv0@<#aDy~!Q8#<U$*hW<Op
zt!4&@4)!j@C?BsOUem>=hyl!Q@1$4wGzxaJc(emZ?;no>XaB`n5oJc@d{~17ZDZ&v
zF^E;UZHeVCRw1dMh+ea<BqMs>$h;5vm3V7@A$2{uIQvTT*Ij&LK*;?VRFrotDu}9v
zFqS9VlPX54t+l1!6R)zdqd*<aG5%g4Gzrc{jkw*3XZyinS^FiT^LU#{x}d;o`Y8_b
zNZDz2(7vA`-^yUk3{BJPSO`oG`n_#NtF3*_rKC|+^T>iCOC+N~@Ed)frqoVOyd)tN
z+y_sOU#pgPCmmlgL<r189`L)^mi9U3^|oIc`OR`j5$a11i?}N=7Ny+A?yX*(w7>Hn
z);^(jA+{9C;*9yiqHm(aB1UiqWEER{6S3Dh^ZncmEQaNG>PZmnX!vwiO8UcLoh)C$
z+{QwuDC~Wq$}U)FQmoq9EN~`r$#Em8B+TF+<q@CRgy*1AEZq6|aKw(=jlOs6*=#L4
zf8z8)N2X>xNLjB=UEt@7VD>BA;3toUN%uup#1UrH6S0TD!*S(y7=ag3YG*-fIpB^3
zvMn$n%8G4~aiFeLk|W4v)EyU|9C6|3x6OO7%A}xD()Q2aU%4&s{@_pho+j%<eVYhI
zLx3bNKFFNeS32=nUcxuG+1f{0Fq;z-GKoEfS0I)RH{68%IJHfe`1PZOec!zAKIMz9
zCuSu4%-ciIM%(i5ebtIn&lgTS$s{j7P&6x)Z%CMFjC8m3%csh+^OI6(?nC`5t2Tb!
ziteYfGJNS(NcI8l<a3>(8xK-`exe)lSCsj*<LuexY;EBZ_Gz=)I!2{3`M%GjY|G;0
z8PG#$EtHmEsH;Nic~fDwBKZ-<1C1t$h{p@{mCf3!)8eAjtDGWzM7GwCJ(}g=fn#wU
z+TOX{-#Rfgw>~m0@?I??KJnt3Dsa2wWY0bmvn3NNNaU2TEnEF8*rlIdwg37}hF1Ua
zkt)CJgQp{fs1AetzMsqNv9GO#@LNAX%QzD!`jXj-1*)>?yOSZnqo=ZUzxNu;pE$m(
zIyTH!vo|pZC6Vj!kZCE^$JJI8Qm7d`$$Un%Y*%Y~`Io%WGFi6W!$eAPOjN(#a;HFB
z%BIjMo~vtpA{YreMM#8~@}s|%H>e4#->G=tBYK<533#7{Oe>O*GG5`f$-j->AOBF(
zCNHFF7)&+XPqv!2jFWLGTU!$4q<Y3~JMxP1>|;>R6}C;*^}m>1vX4x-?&@1%G#VUd
zH!%cwHk-2ERb^-Ob?ycwQYN(qi&|~1RkjFZ5WaUZ@ZDh)gdJ~RydFAQw4NPPixYMy
z#n-#7T`kdyWTlvJR#2*cI(wQo{w{0zMs|l@JhP;+RUb<Af+ABTHc8g~PTJsh{K<!$
zL64ra4nTCAY~<_AR{BI?i>;>#4|hUB$H!Pki%<t{G!H>~wlz}awg5`~j_22cC)N?b
zl}J3`dW1#-vODh~V+f?#B;?nnfq9Ut!bUk*krQ4cpx~58AWx5USu+fZwrqRguoV@H
zapKvP_%)}euvR(EOq8P!1al}j>!~qmoOLiD-V1}HeY2)vEXh1Sr{e4a<Zg74Og-o(
zy_>lqp6);toCY<uEA6g8Mh71==s3M+xC7E@w;4L2eec?+(0Xt)#1ml@@6!%%o;!sP
z2c}+uNotq(FN=^p7LQKWxlc6{fw{Vf1z5&HCJoe;r#vC3=}p<@>Y^CrPCMe2p))t>
zi`eoMfgHkZ$WepOU}hD+QGhK(iH3oLO&`1sYO0Suz*9(^z>iJ2YBl{kFIG_)WK67@
zIxS0SB6OTpO>;nBAx^BcaR<6#FlJ~&hy#Pv-lBX12~rR3!JLWf?<iOeaWpJMLKP8#
z^O~Adm&&JnLKhBk3Q8rZ%D^>2x~bO`pu}zgMWuZk)P7V<!%Ypt*3sR)JSORUoVTeE
z-h8(bdR-2Kg7N&Gc%Sb<#Nghl7)BFuQfU~7b@=rQ{C0!i&r_<O$L@9%C&uQ@i_N=J
z4hfNB3_G`%QWj4ow}16sUKN~siH9GZ_@Xd}Lu@^zOGF_I5a%HCXhp|Pn3&j1!1kyk
z>X|y-z_mA1$|@;5lrA+d;S)HgiOI}PJ_~~-O}oV`=c8&`qG4_rvsqFt<Gf_rWTDy#
zw*5vc{Ex&8CNIR8Q1HEIMid%N3C_lAh}Sg#e)g!F+2TWd^}k$?*s`8$Vn;dQhoE5S
z!Mm*-v~|1h)3bY+2sS4n51ABG{;s_i=@|wyc5=<iug{u2{|eg2uQ>I1BjI|!d;B#G
zicVJVqeHt8E9hA7^`}<zKcqrfZ7mu2c&!J-3Q=q6*vyvK*-U9&8j+8&F5!Bf9PcAX
zxOpb|FP*r+?j>R>%vQ4xUbm9>j?MDX@qB5gV>?(tHXLVeXtWnrf=Z&eh$_S=2qHj{
zHh+O9!KY6=s_^vleEeIk2KlFnh&scxoA-*2+Tf61*==t7!mU0#@|q^wA3G5ny{Ha_
zXjH@_nPe@?U;-rgdY!(&60HqeW4*9kEefybe%XGU;rZ12GP~zjFhGCeW4x~Y``C{n
z83F$G8D7T42+1D!s%2Uq1;WHD&A<Fi7ChUXbDgeaZ@V~}<n#V~Uaa!P&bZq8;re6P
z@gK~3?&*ml{NPKbGfr*F{q~1gki8P&pFbJST}GEY?X25-cPFf0_X>Lxi*@ONK0>mS
zDAz@C+ETU&oIJ=B?>Dc&IN*&DT>A=ZXi~i6n_<rX@10zljMGV~g>-PPC^Qmi>ZPgm
z*Zd>0{eZC=phwLZ;GqdI+voAXUC@ry7KvEh*(6NUa*9^j)Mz}v@c!Sm^312Md1n1L
z|CQxG{+EJYT^t2r`nlVwqOY;ffreC}a$uF*y{yKrEYJyM638Q0Q+LM+P8?s*QtEar
z+b><|WVZV7voGo@QPcY9K2-es--C@XIbD{kf7B_$`;KgRk;G><+zy4vOB51dNLhla
zJAwoo1&KK9vQA0!^DzHZ8n3v>Vq41->ihZtMjL5k*POdJ>qg*0KYk2P%=Q)r8}J$c
zUK^A=H@2u<*|x~)WW}Bmis&c2J$84Mp6zYy0d97N2Zn#vGj?SThOTp6gfaJ~B)b#(
ziFw}o;>8X~Ic|`po7JmKmUd;2sr{xzfp=Tc`c+n}eSS$VwA)hlerl$=81Z=Pb~n$1
zLi<ZOq;d~RJPg0mN1|PIgupZf{(H&G74iCwMI*-uZcAoJ;Lq#fY<PfKUB-e{s4~xQ
zZh&`_QY8vb0e7?&NufcAk|J5D;b}EL7<I7UIZq@RmPqQ2wNXIBC~t36j>@=S1jw?Z
zP5<DwFp&eXDyFDBF7ZiB=du(^pJpI7N@o+I9#b@mvK#gxc1Mp4(XS*L$|2Aqws=bV
zz>f_X=D4W_<%=a#Tq1ju!Y>dwDIqAy3Y90f4_%ZT0U`Y2t|rx|NuJP%0gG|Ki%4cG
zpc<9(z1*5hEHWC1x(KI1tWq{YRkoEmJI!iqV9SwR3yopql~RcOGYedT>YN5o^=`&Z
z)gbfK4u~BI^}!U9HYoaHeDm^*f=3|`p<m<DKDJc8OP#ZMzFqH;lE&;com0fgz3C9F
zC%bReTM=@V8j_&O)e2p&vF5-X49fO?k4iGMQj&@lkLcqfd1NH)$b*KfxWMH_oI_5I
znq8v5gUo|A4%6p)IQV0vlATK<rI*M`J8e!$;w39635<hftG3_^G5}Nd$bgbFu!wX?
zGJWIeF>NK64CGAhL3|q4uu4@~FbUBUW2jEy910$yBpI$3sSpihxMgrHejui$*ysLF
zFmP!nKv25r#1Ee$RAYG_xY~3uRi+9e-9lFQSP0GQ<u)I9WSL7<0mTSVwvfP=VH5L^
zs7&A`f|}2&En3h7rCtDbifXbIK}x&DH@u@{O4}25Bm}yg&JqGYrjNExc+Xm1PO51;
z<$9DV%ND%K7K)<I;K{AmLBubIqvln`d3P3(OC(!K3UM~64gC(SOL*W|;2Xbq3F}3B
z%b0P3<0$BLDCP2=QnraS%n%P`;#{1lv^MG>m&d*c&k!Fv6uYoFk=A<T$>umiWZ*AG
zIOThU-_6Q~A-!!Q4Pj;LQ=)uy(}X-`t7?tB#S1=t!J7z($QA?2+*(H2ikn*!)dl*_
zgGzie4Pkq%zKQhkny`yPX78YQb>1a?I$f)q5qpA&`)yL@^pbT|uH#@9cxRx_T^_&e
z_LxMTK(1-~VMrD@Tr4J9h8tSEirt%Mhz&=)xCBOHkc@=KkxYcCJdGmuq^kCW4-2BU
zy)d+KrK)S1<lYqN_UUIkgy-HAJ0wm~;=UJLix?_T8`(4}k0y3d2l==aBO$GVd3kdI
z!lqy{Efq8d%4#uOe2XElAk1!%SY9Lzw>a@DZd1;zi`%juN3uK9?Wj}-fYU@?HcU|m
zB#2L~7)L^CNa+*s2x^9VIok;{6*v$BHcC;&@5|jSM05LunkaQw<3L$)Tcjr<(q_^I
z5X74ZbBMCeqe~Sa(6em-(5e(Kh_m&{`$Dg4O^fU|9V7{DAb1zWFz2IO<U~|Z9+GL5
zUvOOdAZ(O!P}I<mKE$Jx2N9~{)RT@6Hq$-$qw4BL0gn%_U9i_z=a93`LmZ!bINY5g
z*e*{*D2SM&0l2KEK4`+87HJ&FfZ+-C{ZP%58{FVI3izlZgcXA{XRCZ&8eS0+2Ws+I
zK?F*Q5!0y2E52zx(m;kdGo%JS%&&rEB-Bu>&Y{3OvpCptO%m~4$b$GPlUnRuth<O2
z?<(tRw1lxswjPp@Z;6EGNWMlQCO{p3j0w~(O<r*!p{i^Y)DY-)^0@s{%HMznvk}Dl
zg#)WqN)($NWks<~R`NWUxut$Ig|nmvy$sML-AU1ajU@6P3Vr!F&Qtxs9uRk6fnSW=
z#gt8sQkY<apY&1L&nq|zg0??Rq4O?nu%g+cub@P_0}8cA)o_H6j<cwGx=BmLBa^Qc
z*9sF_Dee^(AhA$4<9a8=rbrg$`%a**qwgf~?ljU<1mCzOkJKv&@v2LUNeCMEToV;*
zq49sGPNC7MKuQ|IFzjewRGz)Or;EPiLJbEewC4w3o+|@Dl?6paP}z9Rx8e!m^ZDFP
zyM%9Kxs%Xp;?v-fH+5CaWL%f-EHBaXSrP2YNQgfVyz4vR=I+5<+Y5m=pd!5U8g7jK
z#>BWIanal6iPB|XSZC0}t2_1Uq?3{088gxrFXYbV*c)P>YwJ!Cc@Z9$qExpx29_L@
z{fS(t)PCzrw-n26v6Iz&PtSeB)QG6VFXYCKw#_T3F1Eeo_4n;2A6!N<`x1lM&FiOc
z@YioxSwBEc>+={-o8BYz)_onhZmWm-U-_M#D2s(l(i?{B-<-}XKaFAd23DasdbQEs
z?!5MdvV-qTC0DFB9)X%f9|ItSN=gl){-qD<Dh{cU#fX|=w{&{u9pu3Nt)yILrnMt6
z*b}cU%U}3YXS`B{`SU&{9Sv!1;d$rl?c2&)v)q8^r--up+#-w-iCun`PA^rqn#y+~
zv2VRQiM;h+K4kV8XZFb=(;)*RA%FG9>9=QJmD|+&JHB0&P}!W)Y8ff2SD1zR!8J|-
zvEuxnS-rAN9Y6U_vVAV+eE^m`AN^oeoxad%6rwc__Vd}VOxeP(J(uyky{yc?@ta<+
zYNdWh{0|0ir_FjcP=j86LC^&S=@i%0eF-rVC`)J>0}r0m7`lJBSlZvXd6h4V*j$u%
z@>0I7@%&CEvDTex{n@pLP}TR4tpro8=Ogn(39)%d8{5scM-ssy3EtmY$$D2f1u`h6
zul^^<<Rkx%w6A~2Wgo9PH{4j~9)gjuaPG!zE0FLQ0?))9gQU6WD~=^PDv0(Qv`;YZ
z9Gv+U+bKVOqzEs+)>Yl#o{c*a_1avlK!3+w^!y}RSEiCIer)8IGjC7**)>*g(F{KQ
z1_qVS+qNi1!j5twb^FM*HSoSP*4Y;~6tTd*^(La1?0Z7Xv^=MQ#8m{I=6B{pc@@{Z
z@pqd=iLj9ovahfYwQfhhH3`Q62HhfrI~%YgsD%Kly11CFeBDU~-2>q8llJOU<}WI3
z{U332-K*K_aB7^Pa471_D^sVRM}f~K&Z|0f`4;oc2v`*(0`=?OGdtf|eW^LO<O}<c
z%C_TkI^yYxr>$3=c_WE$i41&VBW}n4mtZ~J8c*5!1h44m^BW;WkGdva2T?`!M0FoT
zu?w&JR5tovI7utKy^rjgtw8Dfh?IdEsmXhkUku1u5_U8c8Sf;j`=51(5Mw_a9LrK+
z$jwR6Dx6L-9ZVf#LYxHaF^lMO+D{UCvrPmFB)@W<riyEM4Q^IGfwBl5>@=GvHXR;y
zC4&Etwl@H??5OTL>)v;}=k=&1-5HIfmXPG?rWqO`;|CICY!s+&wWJo7<HnJ(%xA-s
zf`xF%x08VRgbld5)rdC8aZ4uq4URWFWbB;~n;jG4k9CNB85Hk0QP?pb#@dau?l_o_
zC75qQY)7^+?C*c--q){ty5D;;-qZbVRh>F@>eQ*ab?a2sts7}tHjE5e`U<32d0*IC
zf>8{=gk90(Q#bQIn#pXFtdAJ#vDAGQUAOEdIzP$VjtGt$_z|MFe2F|Wx&Yp8Bwh;3
zeur44qhLWc!)UmQB|W9E8I3*UTQLiLR5KgVM<|mymP<fnQQ~PfB6t&YfM`E&pkPrE
z@o8NrgDJ18Sq3e>YF4{aM3>(hTU}_ab5`-~B4}GH2e4({t#G^h1-H!S0zHH^R2XXJ
z{kJqR>UbG0>`tUl8cQDm0d#X1c&`0ANvLo28ekBdM*$au-$4asi%#9vw42HwL{m!P
zsqr`L5DoX)fhwz$#$`8UwWm<1X%Nz(IChIQ#|D)v`^h_)$oyN(DwwBDA&XYX8s&W`
z>(V~xlW-`04N)^DKz;<J)0$^O)Kda!mL$=?sPl|n5j9Y%ZBJG%yG4YMtc@kwSVT=8
ze?6D-tuEL3_<nw1HJ;yrD6h&V;SE-3WwG`Tbx>G>;GD0$gU*OmkE~9P@|5Zr+E)`B
z392OSpVT0^Idr3Yg{N#@aG*wo1S(@ou@Y=Ho|(+8HGb9_YT$_xmiU&hlu~$|zom#V
zB=a?c-A+Ftnoom{-SHzr)*=&4{oLNXHcfe93;HH;bpOG&`81y@y?IgT7-#$(mk07t
zR_}9p^>18k5)5&pBn})opShD9KMF)$`tZ@lQto30J>i|?{8+K<PjE6d#-VF{b1?c~
zKW3{bI^~u<aon<oJ`}&(%H|jert?OP!#1SxRhbVz#`4Y5)cuq3)y0f^x>a_%lkUdw
zw}aC;G#J$U9tu1fuGl=>y@GEfeG?<?Nd|-Q#=_;>NoNPklwx@EL{pQyA%(eWi5MjV
z(%V=7p>;(O>gnQLmX5t?nN7l=zOW`Xi0=H869ty3byjB5FgM}cnde^WHSC|_+XT@a
z`d0zm7(hPP9sMF}nTve24(^^bLFtI_Cq5foRKT*8r^z-b@Wi!jLR~?GSG>nffATlo
zbLao{B~KU!#SVeI^EeeJUfij?WOupU17s3A)x>hK_Q7b|%u=>GlJ(P<1-8MJ6WtzD
z9>4X&o^JvAfZ1A{{pdGX2Y!md1%{d(gtCg+n!kds;IY5FEyhpW8Qd>@oMv=Exs3*9
z02YI_fPM|uiK1N7!?Q43+5SMPhE;gaOKq=<2~$V-AigNuoj}Bho7v=nEL`2L)!Ly{
zFP?xEQtl||7<bu#+i0S;mc3Fb;<~qHYyAji68WXF$#cbb=I*KIG2&dyOZTxO?%tcX
zg&qS=eNXPTszdOq-~1!Z>iYF%d4#Qmz0RSqECpI=Wk*)MJDmH%M_ugx+bp>M@^|>M
z%G)QxZ(nFVy86g<u4ASqFOf#Ly?+j^zwi31I1caC%t`(8Jhndn!*QLK8^v)1cuy(g
zny4gzm**mQ;3CX{h_EZBeexfOWvq93Tb!yK9CmtqTbeJ?n_Yxaj={$<TY;cUyRs*j
zyraQm1E!6N@KWUol${GdfpdXrRw5>a*acJ3JJ-FG2JpmsweZRBWA9047r}vniRv1c
z7u#tIWtB?VbIU(Q0dIB7^r>d4S*^<8TyW<uS<V)o-zr;wG+E^x83!+?;hjPC-C{*%
zE8knuuu8AZJ>a@-BjbggBQ!SmxVtGF!@U`8js_pHQAA=xzTX-c1HXqy%uhF%c#J~V
zqD&hxMKCka)4-n<Xv<7poqfTBG_w!X<uV&ODE>c_b|vRTN^1`Lq}YWz;-bRF+k~&R
zxkyXWp=gP{(Lg4#@+~fAn-Zs6*%NlD;6dU-6xbQLF7yJw{9Z11$;ebbd|NJ#C7H;F
zLxd#dJDjc`TlIZit=8^9-0|XTw|vrdK=?{gmJ6SRl;5D;!PFhA7>V8o3hqM3#S~5&
z$80UVS50>r;~Jn(L9nY79#f_gC=EAP>!_j5V|3h|nj)a4!YWL)qfQ29#x?YLw8@d<
zDPm7%tH+pgS#ZZ$*CTCxd=G1c`KL&5*<_3&frXbbuoaP+m1HnuKokwC_?rZ2BpSnx
zn~Vd3)VizZAKsmHLLxI-E-U;nR9(^KVn89s(ytL$x=uznkYjzEx^rP@<Ct|75__HL
zq&WhIK2hQbV7ptC*42=@ym#$dzDdMZDIaJ?b-m(3N4db9hIJWoN=~hpYrFx_&niM=
zvngHC@`EH><DtR8H7;>JNs)O-`jZTzI0(kGZ4XL)FkZy~{5+SAdH1=P>^pc0+6Q0z
z%E3zN$L{qk3?O;~eisOMA$0p32r^rXxadN-rDd<it`z^_K;nUjE2%maG@^Rs^uCS@
z1cV;|FhN~~$F&M4)zp#*M5u|QElAvx{0!>kI+XTU)UEBQ&~5d7qbHeQMDk#K1}=NF
zO-$h9guD9F0qTpqsvXayx{tm4*Ay#$yLhHy%g4XF=@TV_EZl9RsqQXyMhYRpZzgBF
z>jm=l-)@hjN=>~=b*YbenYu2TC-=tpyn3t0ib8K(dP}o8*uact|4TNXMFjRm_}p4>
zrw<kNBPV39z9gG>KeLmn%lIj<fDz~1|6phGg2r_J#ILxgXQ|%zK$k{K$UN<?#cH2J
z_}rcR+0b?$L9z>n$|AgASuX?b@Eqpj!<TXYcxhJsNKkbCL0w0Hl#%m~i!sJP{g?F8
zW9nQBA}9)l;Abu5<aUeYa%zH13SP2ma}>r}y+-+tJZ1Zym(~wMB{~S|Z1sYfd-8Yg
zT+UMy@?rb=p=;TG5t~%0i&s#0^6V<x6R%}ueFe$lRYh^fE1mnrHYyzneCHgqbxn(^
z1*@&?``5n1%B9?2{B&kZx)V~MHs%%fy+@I@IqR}|@AF;v^H(zB{u<d<m+L*kjB{~l
z75BZUtrxTqz7^fgw99+xw&P!2z2@%tSMFoBR6K@c*tbXG?o!sNA{m;3JcxjWX*E<w
z?(e93Kw-2nHy`lFS~(uS`v)^yUB2H@1^fku<y7at9OWyQheE0a7D7A9;SrjHXN|J$
z3B*s|n5qH)!BA(*{5tphnQPrDyi{-A9!_}d#XDSHNpu~}S4MtL>i6=$^LiGSj%RCC
z_OJ`T@RW;>H-d}oAm|Z+*_v-4a8H(Zv)Y<oVPxU7(kp>VZcPib^;GB3R<$w9H21&D
zVlm6nw5R@2^#A@sYjgGN-#+56fJAqL+417my8e!KvA|m1Z~yx9U3te1%uPOHw}zM=
z3_YUyH&9*5gQ-)`d2oCabCFJ@VoF_>T3mF-CLY4}|CpPzZdb8ow`SkQZc|UBI--{D
zTpQ!QG19uc&t$n4RZX4Fg%riin?MJqxFn5*?NYkmSm)a`bi|X}$11WfsOgKScIXFu
z0khSaz-D<rl%mKzHjk8A4B0Ar$ejCbmsO}D`=e00?|R>A9`tREGmkjey)kNuma5lL
z?0P2-ZtaaM_S~!8(d^4b?yE;QEaX<_AsPi?b#Ez0r5GbV)d($bfENEU&&=R{ifXD-
zL|nj~OMb4rSCrrgGPP&%qm-4=eMFtg9M8Oz-5i91VeH~9;N?$`Tf_D*DUVgcUDo%2
zYOLXAgfh;g+up6iq!1?EDM9yWGIvx;f+#?j1?R(IDV@Tt^J`!sM*2h^IR(oFHZ|ww
z^~|qZyS7)A<JZ-GrEGF~*6u*I5&!%^*o#?}itLK}oQ0`96w_2}fI<dNGQH*JsQmgF
ztI&ZkkPX(xRPa2_B8-~^u^Byd-MrzXu0hDnY=vw!bcJWuXfw()4Ad6LIVhuCgj9g1
zJb+5I_w}ci=XiE|_IkG<vvuD2m}OfsFWb2%6^nHV&chVW%0R$Cj@4EqXQen-#3*PI
zLbo!Mb_`y7)2pObT19ks7}U69?hIzDv=Btlr=*aOQx2ujX)gutNI*H(Xrx=4PpSr!
zJncHUGAQbnZ*e<iXP)0+j=E4of|;*TBOK^mU=2JVbeN=8<dUXRI%%}*a$znqL0h|H
z_}<V8lin(uzFUMzQ<t#(7)4$Lp~86eDiLn{eDqw9w{$&7vfxI;uR?e*Gy)w=F&GmD
z1H1j3A&b*r0B1C-h^bPyHTxU+ZOwDBmURx#`zPwnBVCHp0Wll`+?rA_jpO$U9jQ=$
zdjK^hh&T)ULZCf;EO&Qcb+zvYF#-z3M^1|4Gu-A&Z2GCT@bwh3F`9%@Q7jeNF(Qmp
z)}6J%uF@ed;ktExp7C%E(JfFi(t3wGYpKO)IFJX_!yych9*mWMedwlJBMNc4ML<u<
z3qe7Q%U3)G;)QJ$<tBb%hOt10UBPbBzK8KYZri|5v;Q|z_z2K@ga#K-?D-ezcJG6j
zJNMDs`UvwNNgsmkYqMZD;x$++-0fNXkv_ozo{0IzV@8{VQQ|{KT>g<mgM8~`wE-S9
zHq?^FH5`A}bqj~0=dFPm_BHop;Qz{Ok3ln|rRLOyAe%d!)WiA8rE@Mkk0!!kyV#x$
zBday40cqg52NFhCDyj&Ig_pVV4+Uka(lJo?*0}J8e+%~7@AtM}GJ?p8zt7ggXE6N8
zM0Uw}J}#k|6f(iIbJsn{t^nwqPJ0;#82ys%Gqb*0WHE@=iVEQcDB{FtT^1D}B6@j<
zolzqU{AT&^qC{Saf5!UcBiFExxV$oLq#|}GV79tA`yF#Sa?*9<cZj&B+`W8cf@$Sh
zbS5Kz;YjJ$KFHGV+c+@f{m*yd^H(k*GDvL_KK9|cF#puVV~cj!4f5!;7x$8%a(?wO
zp8UTsIW>)8Z>y~;(Fmxtn>am&n^GdEC9<nToK;XFjsqx$vasyAq`k|v1arb!1k9Ub
zM6(m0&7w>@r%XipsI5q@9dgGeKi<B}gNzUVV{0QK7!GisB-?G4-rZpg$6%TSYuTdo
zCfn5JR7kR&@o>#wjoE6Y53K1=URU~ie>rPJADV0SPg!l1p_#s5aUly6u%jgY=rerX
zk+Nwb!pgSFeTO+b>3Uz8RUKz;ndNeK>L2lJz0g|F7WGxT8z9#aN5QscL*g-8R~O^+
zqkHcUPe}M6jw1n8w%6)X+UA6dQXuA-KotQ|*6C601*T&AAejYT5nA@-_^5d|y)Cu(
zL3Z26c|+k#H_$%;?FX->mm38sTc@v3wCz}!?xa;yv&gGW!fj<Mvo-GJcFvu?T2DXP
z#d1+B{PM5G>G=0&msIPcz*pDsZ6oXM^bJc4O+e{xHw%=q^>r7(GX7n(RbQPz>W)>Y
zC%irMiZeylEH+2TfXjL7`T<->3d~lQ$7N`*v$)Z6om4}*)pd=W%PtiY4oyT;Crx;N
zH}=uNeE03;*UVAF&Km`#?iXB$pbPJt)bIKQwToQ@ir))y2N8C>$yW;=H9fu#s|6SL
zk`P9%g3Qg{$6cFEyNb<2h8lY5YsKa_d2R@?swDlGg*^=BWO~LnQcycQaEP7)vto_7
zrj1JfBLwEvMi^9j*y+m!wgyoX4Rc^$B~?1VA6;mWeK8xvP&d}K76z%B8R~dx{dn^&
zKY#kLYoDW72__j-c&)acZz}T^H#d%c8wR*6UFxZU(gbGfa8v>E3)AIyaZx&8fmpCT
zBCuhwK!Wzv7}e^bkCv8;J-ju-F<=)GIjLs{(p`o}Vff~4O@eu(TS{iD&pknbw4_;?
zd_#i^&v<#x`Fv|Su6?*ml;E&aV;=<v+P7nr>j2&tYpx~?O@dmJF3Z4J6?9yYM}+`y
zS1y?E8;x!n+<~rF%-m$yi1HwP5W5*QcVOwF;@q!{!PdH0y;2hew=S#gW4u;X7Ot1x
zZI+tF%V#gKyx<`h#<5#_lu?|XcJEd=Wr?+%vYsT$yR9wFEg1w<Fq=&M*(eOXf!y`j
zCQIWj?12#JZBX8U)o@_K;Sm>Ua9?s!Ehz>$CBZ~j0ab-cOCeq1DNRS%QJ_>FhCbj)
z56Z+;36)U@^6i4cJ-P)VDsKbNShholalb-i+!4W1Atr1WS>?}`C5X!=blnB#6;iqS
zy=^4m`8A*n&)7PpRW>YAr5ne3_NvDKEi?&6xF`0hf8V4T_@H2Ha0j|f1?V_8jIl%#
zE~2a>Y;85k3yFFBn__g^i&1sZvBAfKS-dK~RN)ao@%vTNKKbo^>XO$(KNSAkdIS?S
zCXt@H{A&0;!uo<mA5OX=%tm*v`2N{&xX-d5y~ooo?keW9vK^M$T6{OJV&(P_yeZyT
zH;HOGz94=erLrmt?r=F3W@5KpokHonj%)QF?{v4XDbey>Mx5(oBhJ5;Ip8CKfi_<f
zeaG`Lzpiq@z53nFwwgWC3<M+gqkDDQ&^3U@t1>Y<>n~_Iv^%n##v*@ZhB3y64pHT!
zNGAxosD8?43PsSiUr~6E8&suCLKN<i-(ZP?VSgb^o0Iy($4PN^yiCogFafLkCg$K~
zO??>?EBjxsx87*;L)D$uW3GE5Rkr2pU&DtNPqD6Ql7Wonv9i6<+bsR%tthJDP=+A0
zHM@<+`Ak@we?z!L<ACh<f80AyQhnvVeeQ02$YVCf*6;8dZ2PIHu-MJZB4=Hf;+1O^
zy9{r7VQBmNd8L-(n-Ls-s^wN6;oe?772Mj_?`$8r<Aos}e|jR!4HwI~3WB+(Z*QZ@
zs9iSmA*GOJYxU#t3K>eCVW1|7rNwtbtSY0vWdRhPi>HvbnJ*AX$B4=Up-$&O3E!q#
zcY*a+(?ijDBiO}hz9BOTl&$2mY`0rM$`yEBkVmi7x}X3NKd2qzk#Me!z4M#Q5m;Jc
zLpx_jDQCp0Ej2wk-u)pi6@hnKyYa0*;BpnA%h_5YRqo<oC3yogLkaVYFwlMSqj}f=
z?xn7f*(%YseYs8X%dK-)MI~yp*c|yzMK42V*_(dS&940G%Ztgk9H$Ha70ZHDLm*PV
z&e!rHibj%odH(vKE~U~KFs*JzEql`5BzyhgjD|NoV*fr&f`XB)#as4SSP*@6^O5uU
z*7v4<s!6x6Ydx7_l<kE*B*<f5uz;vi6dMj2ip$-rvaiw2_2DwCpobU<3DUJ6b+L!j
z?&7De@h&@eXeq_^+fz-vP02dcU4mP2y1YZX`aJXzXaPu;0Fm_pCm$(yww?JF^Ov;m
zd6)B|@Y41l6z%*YuIQX-6$|kyKaOPZy)h={e>2ydTwhfyrAw>zJ8Z3XQL90FU5$DN
zq{TDbLJ*Y!e>AloW*|H^6tv2i+r5`=m%S-hg`i^!W`?Bv;{Z|S!m|1XwX;F|0Lh?t
zm7Pj4mXl;F=#lJ3B?ZhWoRrZ?ozX2xCzC7;c(2Y8DjnEo`_0nnixESN>_cpcBSSYe
z*ClO4hB((ORp>dM6uT7%&At%UzHeXrUk}OJN4h(e-0$X*<WZ5kO@x(Sfd?Ipljdvt
zR=C4~=pHW3Gv;MYy`9WfL0$HMF1EPz^HE%aZDF-G-3Rs%_Cw8DT|e?7PoR9T<>5sQ
z5X)#_uo3fVc<w>)&^6a9tiuS}x9YCw)RMaCD1{W6cVMvEeFd`xZfMr73in*Byr{NV
zU{FU#)aYtWhl?GkJX%RD6`s)$A)y=VqMJB}-#!CYCsV<#^m30{sK)d)iH@b58X`<)
z_&#|PKG+qBn0SQECu14#13?#i;Z+`EZl3xwk0$dy*l4nxmYj=&wEOzo?K1KtIZn^e
zc~D!H^2+a&g(M1emGos+awaE=SQoG5tv?BsqN!tBe4KJVT7&KiOL6>+OQZLQF2G1X
z{V5Lo2Z2cu_4wN#4y^C}$-zd&G==l{SA+mmo*+*jBxLA^&}1Z_pV8uY_aQnfB^)0-
zEVjfMK>Eo4o~0P|vNiAo+YLPll*T=~BlZiO;sa8Ywa|J$y{+9uuca6bgvNs_bUBMa
z<>O2$^weV`WUDWlo=7Wv=(EwB+v2qZbzI(*Sz@+^nvHd5_=iASoetvd1JAxjB?FK~
zOU7|wXLMo%qye6v%#GN&@1V0WVn!6LQ&W(92Op}S{N<~1_iK?M>`3s+`Gzv_`P^k;
zFhQ(-ELCzDucm?Ayk?O}dr!_4ShhRVUWavTb6ie)dok?dvO_cAd(q|^M>6?KT;ZMj
z_dZ~<xKxxxbeQeV7|TS`E#$@5`Q!<6OdD>Zy~+wLBK!m~PZe2apDX!f+q>oK10TIc
z%!lC9$z9Y*AOyV&FXiR8c^cej++5;5?3(x1+OO8W^!-30(xtkf$fO(jh5!;^r{tP|
zJ@+9c-1yGWg?ZpVhl5SfMlry)xZlgOc6pvYeakLcucfGb?R)L{>X*(^ob?$=F#=My
zHp9kdRhB$K#M)Z(@3}InNv)W*p_6pH_LPY0&wqmf$*Go|C2g&4<NNPufB3_6U9%hw
zwZBdVBnd3YV76xNSFSC}>HqG^rGN1VeWq?-%Y^;DtQ(*EG@)XSGnc-(HvhbT&iOAt
zwS+dFTz8Xq+)zY)5n{c1k0~UdeJoqoHwJBqw%UAAUViNlLPYrR{>Ps0-5p1%>o=-o
zBOo|;%iI^(pR7`<93T?FE6RuZrH7rTqWnWatgJB%thOFkih(?$dLVY!HJMN&lVIE@
z&fbyKFU?SbTxP2xMg!cVX2}Ec+E5XMCmes522ar{BCK)hTah-Bab%MF=`7u1R{G7n
z%${f!t~@_ZM|{K;KgVk8`r=PpLvpkKRmF1aA9-c^5P%v|`Gx26?9ACnOKH!og?C5y
zl|N-NiYZF>TwYXf{{)j%XewZ~PL-!3<|-`%tsnEh&m_$sUxqDB7?PO%%e!2Ds*`V$
zbU4Jk=#X7|O=MD~mj~4xQz;G7%hgTj*|<+7;)R3K>?2+Lafr85L{Z(GtvbwBsp?w*
z|C$v`Jz4Ycwh-E9`1vckeZO1X@b0>+`~<zFwZxs6eSE=%jp`a6{k=MJ>Gh83Ls!H(
z*`I()a-oHXQJmT^PgG{qwlAZz)@Y{tw_>@)#s{qfr>}mz2x8W53szg5d*JB#t8Te$
zCgSahq;uk7SHyW$(|FL`L+1B{)1B=0sfUXQ2Z{1fN1G(7o&7oN74)zgXoADm*qYG6
zZhz>ZuHK-|3jH#h1ZJtmy9lE3Yp}Bmjvmz};g3@hRM#lbvnI+=ZhHx=iW6u24cB#t
z1zM8-jMXYE^WZRB7Z?uVkyYo9Zr~o3S-48|3;DP{oUxEa4$9pr{yGsXXA$#w5YaGb
z$LNU<2hpq$k#qn<%km(~L42QZBKd-fDcvd<jgns4%VQUL6c<o}iii1UC}<gSB=3l8
zr-@(2v(N<O@*buIVVl4s%xV*$bg6uXNPRQjR><y!Y&dk0GDBA8KWc%K!^@G%L&uRC
z=;TCiQf!tk1U9q@9fGIEVc@jL>$?;*IM$%FM>-Pk^H`S0NH_?AQuxRtb|fr9QEPD|
z?U)4JhVD%5*=i7SDaZ~q0jv4g$9IuF5IWz-jN@Sv*UZ*#A`Wt<=<Td{UY%i6x5Bi$
z(qqnV2f{>;oOw;vb<~}XfKWWF8;H}Xx$D%crhCAfkBhbh-=_flJ|(xGziWAGyBZ9*
zX|+3VX|ZGQce-3WgEs1q2Q3izkwMNAzqCdn<S3xg{7peD201kWKZwlgKx{nyNE4$k
z%atn4MKpcleLSfmViVK%^n?kz3<4Ql*4qc~#HKIBV2V9{EeilNmnG87IYwH`b&1XK
zMCvElDM#1BuD9;^JOyd`Fd^UIld~f!d_R6wKFOxv7|^z7&v3#qS-BuKyL1wT*#+@X
zjM>diK`&?D&_FW|yei7$>Y=GvtkAo42Q{*b%kDttUYC2J$}n9_U@b4z8d=4RwtKYb
zrp~yp$jp8AaPGdsDNKF9Y;~Be?ZZz$Z)tZa`XmD$M)HT}GykUWn~ePb*;I7#pQ@TJ
z4a-RldP}zxuZfX<wr&FM?}c<%Z(hrd`r^bai-*?lp4G?Gmak`h<L-D^CsMf+x3!Dy
ztJ{kZ1rg?J^N|m3W3}XjM!-t;SJ`GNFqDn1txO6?BY}1`ZWFOQ3u!9yQz<=8;Ab2x
z0xK=Ye#|^bt(qwlA0QQN#Mtv%V2dlCMxK{l5YcFOFZO{K_w%1WROrOo4Y(~4Udq2s
zAIoyF*|co4wk2gNu6q}feH9(?Zv~G3{PvZ6nN7moyC-6y;*S6w$y8+jnIcSMPFBZS
z1*K^7s!a4sX=dx)41F+Ly)X-FQ^g#mt-_ORkNM&a?nyl+ZMC)d%lrzhwrV9#@3#I{
zICY8tk-ta_vS`J*Ihn05eIuQ*HB&Id;1|Dsd2}j5U4uqDPaw*Nm~K{u7R6Ygvh-P{
z)mG<~((-tR3*RsQd)V_}b*va=qJ`Pw#9z#%HA;0z$KS~1zJ(Q!Ga6_f8YjB#UOuII
z%3-m<<c8W!FnhK!qmO;j$`%-Ax{}q_S~AjV*)#t5UD0*^4;M_R5&3SN`X0UTc)N37
z`DPIwRAT`?O~I^e6-#Zf;hxY+GTDB>Z3H*%8B*O(|BGa%DV?e19=YC^<*&}h_{3!l
zx!}^#V^zwW2`&#HR{!O1^Db<se+z;d0=Il6%ho88@$yC(8}g9kRP5Nm0^ttS9bb)z
zT835o4DRHmVTa0mkREeyqC&Q_G*GQ>_VKDSlxr-gTJA|B{AwdJp$GU8kpRmtL4UQC
z3T3smLE~OvJJr2Z?b<JRmSskR|I{^Z-Z8T6UiimQza;HoI{6RUrnrKV2sD9+b2H<r
zYzj+kVVN(vzBlfcjL!*|aiJAmuf1u>g5F6&neA}Qiwo-}lq7;YJdS9r5H2avfHoBT
z7GPJdROK#6LC)peg|&dvX|LSUpe!`)iz$a=21>Fxk0oW{*rYk;;voO%n+S7PbY0{|
z-&KfRBs+l_jS4)soD_)Q(JQO0=_Cu9u(c`Ox*8R~8tRn=*A0-a5jKoz0!s!YlCjU!
z&5BEeTZM}pp?wn`lk8vOv8M>`!9W2e+5exgf2DL8G+vzRDmRLj9?(n;Qpi})--$UL
znZi+jkRa&oSb?WIHqQ=o1yf{-z*6z%Tf}Y08ad3N*Nr!^J{pe6hM_9Nu8V7MO=BNZ
z)JzyIt$-WdBz_JsR`H_8K$->Jel2@QDZO4`6%9gYwG{|KS86IJrp&xTBLL28`&DhU
zbX|CwXWWZwMHQpDmt7DQ3c56a0TUa)>zZ1u@Zh?vcvw{1RM4k7&|_IHEBcVz@`GeE
zZp~{Y?ttMV^|C`<nC1u8?RKK}_eJMP&OZW6cF#|c$|1Gh=cco+bo|qG=>z%+x3vOG
z$wb4zIkL4@(W1)QO4Q}Y)*r4(>^DRbGa3`2cMopj423OT<OKHV5cjm>p<D(dEoVBu
zI6H{l>lc;P#Gbm}p_^u^sOQ*Fn%!=MJ2CtE#7DzC17Ew1lgXnj_k)hb)-j=cfqXD3
zs~UB%!&5Rx%N}}oXbfD2M4ebx3g~NJK*mXhsY3~b_~MbRno~x1cgz^VqcK%xdWRc7
zPXXsPV7Z33AdjvVja3F8BiAutW_CX!TA1LWrs<{N$ZMNju}3s7?YhUUH*8X*3goQc
zROY%`n^;^{TZ`=p*X4wx!{PT_=2&fYV{H-^6SD0x;)zF3UcS5UiEqt6?k-^CAP>*2
z9gvPz-I+n$Nq21JzIj)%&4g}pB!si9w#JrK*MISpNGAwTjYn-17WA5|>NS>pO(k<*
zBCgX4KD6VubFX!LYdeIA&m0X|#jaBozrD-@*b+VD-IP1F=6K|~i6>Z~y>Mtzqa}~o
zx-^bxe40eY#C{<Cx4-UPpa(dh3%fX3#7<c&zZkW?6r5BC1U0f8k1a0Z_N?9Ev3VNG
zOO?KhR@)rOH2oUS2|QrW)~!nvL*eXok<F;>_W4ELXxz!xx%YgV*Dh5y8!#Fj%y!wV
zo|(DSFDak*(_5Fz)W!B(wv1j!L+3sgS6h4~Z2CWHdT>%|YG3+-i2i~5k^%0rg5dE_
zT#>o|h0dUTZYqY4wA#hlAEKWBFkf81?@(5<Yq~dg|6;yy-;4YsSnZ*Ege~9si3K({
zx*~q<YF8cSNQ{^LQ!yS5p<D5JI;%m5!$5*a(59cfkQqxFaz_HJv?*ggh>}tQN9{e$
zfjoTCy3*Y%O-6p2nn<L2BlH8P|L9dWmidR@2$t2>v9q=AF1^A^O2F%4X7pR?qDdah
zwqM7xY#Yg{8(RzR*C)BNKc|$VVV+IGv|l<{ge<#m!phsvq++%8&41Th*)p<?>wlZ)
z<0B8!ss8T7lgVuThuP7^?Ur+Q+`ub1=jJqNLN&gE&9~3A*0P%)Vtxuaf@EQnaGbe|
z!HY^T3Rb_yNr@to`n)`Xv|%9mxvuto<9O`u+eP?5+PJWTd+WEYnhL;#!ulP2=^&$1
zS#;a~4^New>94oGH|!)D%cuT-5M)O4((4{zO*6p*J7wnUP<KR!*~*-yt;6q0b8+zQ
zPhAr@;Y^2nsBwH`PYc}U;d`dO=~L7VsM+5`nt;wLdgSvzNW=wFcVB~;3-n${rgI3|
z;p<HH^Lg$Mi8oMApJ;I=8@J1=5@N*l#zwz=I-lyeAAUBTJtb?BrcQjZ32N8LMcEP=
z5&=<X#fbJ%V-kMo)i*V@hpJuPw+|PMaIBcS9xu6WgjkI`p3p!?5berkA$bA?5VWIm
ziSjn!<q5neg2RJ`suQi~C~TD-om70fAG416>r24ZA<~SQ4=89&XbxuZMN}%=-ze0j
z41LC3S1c)qMsSJ*5M5BZxLVa?^S{=6e9?FfT$HOH2;)upp>WjM2Nbd470O!OzNG!w
zeLS9#fnROADQ^WVg0W@TV-T<}eC?<9@R8YU2+S))DzA${UA0(eyADe`hSZWg3W;&e
zy6qqhO{))%*WqjWk1#)$Y%auo2M009q?ubuOTMFFD`zz1a^3>VyjuvQQfXkMnVp_&
zfC+4X1xc-`m;$cW7tgw`x*qKs2cw8QCs7v1%@*!z5EIaQGK|(lQnvV|P_p$dw}|&D
z6JZh5#sR?sTzn#7WFQu!fZ-2$l1hYYIMWJ|iFyL%SVe`IU5GhZse*i@=o28fib(z8
zS<aKljL_0lu#Xu$@^t5i03%sZYT)sfM51KFK|84mNW92kXJX0^)c9gAKE>{PeY2`2
zqd=skUQ{CFYd9-{qUAnEt9cO>Q^Y!RFqEFe%C<*Qtn{WQ5W~T;b>iN3hrR5LHA}#)
z;1;4M0)B8LIO`%;G6`yCjbus-BofC=mzQ@G9OWhC6~;i&dC^XE%qcPOqQXUVnRn#6
z>LwHB%^`PPc}>;0%=;@_3AzY=v#$^}Q7Ka-fRwqFWn}1c%TUMzA@bQqMHc+LJj$*C
z-T7W<41=9-?KH9by2y9}St_w%dC8rW3IT0QKSAeHWkC_rFVo*GJlDB-x2;SJBT24H
znJQ8CY_koi_D;fBAi;J22L+Nm+#)Te?#P5X@EMv)Wiyd)ph7I|p-L%6z_z0Zy>wet
z83nyOJyW(h3fRhat2<6F#K84}o2g>UyU7{1(Wyw5UE<o)_qt_Q<z#Xdzcc(Il~>&4
zCjB<`mm&Q0Lj+7RPJL>hbOpkv%7S_bZ0Dg?u0y$i6tM@wp75|BWg8p(MU;k-o&~|K
zT*lzJheVBZ5ELB;5q*D<FAY*^91Syp+S~}pyhB<M_V21X>u!^hH8oc`ub>JxqVw5B
zq6+U9Y~TA%T=#`lF&YZ-0EG-mWU|9}9-6>SDbm2tWNai4%{-f84TAG}qZ9&LeF!wm
zVhr7;#9Tci6jaFOW79z-1Tf8N8AtqCU4c@VAlP;AqLc<B^xu%Bep{hXqby;p16Gv^
z1R<>G#G@0W6-L>u$pa?H_53tZm4Ij~i$Z;*v8f3Ta>79oa8!@apd<E_;~q2ipky5g
zC)`a8in@8o+!gMyy$6y7wokIwtcd%vkkJPn*4Unc#XLLCfXYJ}x*Eu2QG>K&F=RcJ
zTf>Eskg{b^#Dkq|r{NwQ|2-R|WvlMATa!H6mCk4>5SM3^tq7uP9=l)(xq@HdHyUVk
z)dplX*26>%_*F%!0xxgQZ`0xl2Gu4*X9&oNAJNm$broP$l{dgb!lD3tU=xQ#U*tT*
z;`owzC0CIpP2dM`a*Z(b@O%0wA;*U>K<ewF8mihkuru{yhRr6e=>0^YB#~4z8hot=
z8Ah~?9k_qTJK&S1&~L~Jo^O4yBBO_D5<RE_MnRDW-kGCSCLv={4Wx)20#WlC!m4wp
zIQsM_ctYp9V3hC{gy~ZGNL~futTu`)PE=iM0!YMcN*4zcH?(IajAqm&Ttwh6!hGw9
z0E<}vaIjc+sjU*qI~U~E5HuLB*P$ES5H~7L?QmZR4Yt_vlx@@`bv6*AY?g=^p;l-U
zv%g#OT8p)(&s*fybaFg_9^h~n&&TRU%JhA;WYI@Cc$W+V)ol-TlRoNMG27e)jJTF>
z%;J0m8TgF{%#&;kq1>L0Lt^)fdT2273nskCIJtyYR<)c-?mpT&Ds0p6yaKe~%cfY!
zDZB-|juiQt^C)2qcqs98>^~H>@=bX^lxfwB{0AVjw>5qke7IpCV(Yy{FFxkHJN--L
z`T+Ss-gdsFr^KJv@#m()ASE-QKH4GK@$^(+J*z$8-tP)lLbqJF4AKWUGJ~1Tp1n4A
zx}6o}kCFb9zGT-=R%~(vqWf>yd%y8M@5-0cl|Jr{-E`u)p|8@x%r5eO?#{vXIuNa<
z=PzIlNGouiABa2H+kOWx3XyP4>e9lA01i62WIk*^Y|Fw^Cw{pIQ8AW@JQB9jmaU0b
zIMpjBva;)T>i)WpMKS~?$kqiBX#e3AiPD?k@9_R^s!#PQBSg<SZ01)mZn*b(1uF?w
zwmR+grQ5;^J9~OE-8_lUf!B7ma<qNbhhJVGE%5hVsM1(TA~~+xJ86%DnfcnoTF-L#
z6m+<~o1Yuq?9cI-f6HPSe*3nPy=htTt9(c>F0;r$B0l4oRpso9%3|fM*w^2<Bp&|5
z8{FO3+~q>`^VxpJin84W)A5<h_e@CC@ew^p#C8+{ffXJNB3uwz=As&d#~b;H!%;5}
z5vpU&K{3UWcI2&U1F3HoU%a*kuKzP?rFgOLz+^PQoi>=cm1Z*^;Wd7@u{abwp0tpI
zn_f=Cqc#^i%uQKZ5basK=dKMQthQ#yDeX%4GbBID*srr0R<?SyL)dJd^==W@tA(BU
z9)?mky`4q7bI--c%Nw28ZpTgb=l${tzOC^z$L@ZbZ);4w!@0#LC$m)&1tjZMITLf&
zov3)GF1Gb%oqOs7JYeT1B5D~4;at3=oUCgwN)dw)2>1puj(UUg>=TM@KhUsAQn8XD
zNN<VVEbk4jn0SgF3D{(h-irH72(J#W$mWF^0hX<;`0s4yOG!e-?P#Ed9D}ElP!n{-
z3&p*6GNh@YJaMn<oxD^%Wo~udL>%O<x;F-wb+2FG#kp)P&kB3JBQEH{h~grXFxBz+
zU~oUy^Ao4ZCq5D9U2oC5<rfsL_e1f$?xE+LbKT1~j#GT^o<LbjWRHl&tJY@QD-7LV
z&5hFgIeKPIO+FsPdL+c`%YHbK8sM`7DKaX_U>$oQfMC}&^PRlyL`*=IhSG392gQ{W
zx{eEF#+yji!PF^q7Y>6^h$8gKkbCMdnDg`!#n!NtDJ}#=zPnGyKquMR-fmj(3r(Dl
z_zv-mS0j&0T#j*B#kF=^OOU7jHRNdEehr&cn!xC3p83MrSr_a9qC_KsVjNl<N+mr%
zD+rQZfK)EZBS7>hH(g*Vxt(|O9)BrAfMfhM0u|IZmO^7^AC9ArlO0QMm#Aw6bIHRC
z8HFBm5+pm0FqX-^11Hi*7{j}XOCw7;A{hmurwAc)y@+>F^f8OBC#k#j&pn=bg`*Et
zk$jy0;;MJ!+GK;L)DKhq2O)7pXP)9C^F)CKY%Adz`4nEg7$oyt#)3E&)!0OdopcEV
zyY9VIdl4#*Al{Q)mC)tR>oN{Nm;h^~&N+p<)K3?0zq;?KbF%1+>GZio$dy4C`U|eo
ziLirYeTqGvA`iu~8t=L-KSkffn+Pw1*BaHOre$XOItw4|Xl82+<U>X0L6iJeT2?7S
z+J2dXApZ;zHjpHBT@$HRLouFV0B>>G1IBp|?pXyF8tPg-7YXAVg1#HNuDi3o8o~D_
zc(jZIy#tBJ{{6cm1EGHDP;Su=NV#kPRF!l?X8^q`{Xn3tHb^^Ki#T=Vzys(fu1jAW
z76uYebye<aCb<afVMVP|ZP?GIAnMMZ0gf*;grERWQsL1ph<eo!BQKt{27l3ND+Q~?
z8OdM>K|Ls{DFUuaUc&`z&vaNRjC(=8LqRk_UIvFe<UXJ13^C-=HlrAVmV4bmE=uux
zm*^U;%ctcVSip{9udc0g6TZsI-uh$meZ1WrO9NZ<lkU5@ryhOS`UIsFcz$c{ljw0?
zd`=(9b%1?X(^8FwPX1L;e8q2;z1Jf0%c;|+NMmN}%}jJc&~EqK;l+Ds>YI$is@Jc7
z-^2%KaVMVZm&cOqbB8V>OQqM9%u^MQr(K9e802!=OI?p!PB|#zhxl1bHrql0GKpTE
z@)_TaZ~6gO)tJg%+F}HAo8m@7Ob1ws&I~48ZX(O}y4ScY;C}<kWF3L*_&M$h?V8Ko
zeVfe1f(XJct+FccV%j-o>x6EO5fIO=z;)wC@=oW?2>XF4CI_wY#z$~5Td|GxJiqsA
z%sEug=cJb#^P?y9CfAWmGQM)}ddvShZ)3LVlaM}(n-eSL#{cg9oTOY^DBaYLMtxbi
zT>W>Lfv4_vE10bThNB_=$pL0-Qa=o$n4s+O0Bbt;O4L*({xu~v+gu(+-1Pr)fQtfB
zw%uOR?e>@7$J0lcXLyjvY@K+qCpa2<Sf|m8ZtZgF*b;b60BCZ<DZ<08-{zFblr=4X
zM=G00+`phI&s|%(v!6Sjq!aQ$pbon)n+n+zy!kit#k^&Qx<K8&JB^)=(ZUwDI0lB@
zzrkL`D_P|&%Tul$t0D&Nw(McHYX9Lz`|Ys^Pfpsl-KnE+iQhl%mfmpO@m$K<?$aM-
zSpCi{?>@C_jCY`Hp*ll5Ym^%gq#HkiEprej%?_mUtT7MV0KeJx1Ce#B$u^~X!L4xk
z%!ZfQnh>L|6}#j`GgE2Xpn-2bc447?+9jE|b9csm4l}0@&+{H1*pDpxiwa;|c3+OU
zH&W2^%I`nAO7HmrrK^v%oTb~H=A#=#FS%ZN$V|HDp@q=uQa(gp&mVeDv<cO%A7pIx
z#I%VXoM73{1)18}D&gK?#!s*Fj*d8;EMg=FUryzxCz*yFfPKn85Ifpy+BGsiKnykx
z1i5=+t^I_p1Ktx1g$ssd!qpY(O~(LBsdUAjQC2)4@kYXvVh8%S!qm#>YONb)Enj<P
zvT08|Y6arZ6l;ST&sgdy*VkROy5QWL1H-c*wmgGEzX&;vz7;_30>)BMVzzS2%IEUU
zUGe(|x^x)3YjuCRv9ZDOPUKON)DS}BlN+;>sl;`$&4y%T7}va_kw}GRgsAJYfzYX+
z=SoEOSyiW|fh6#aXQt(IQ+<QLEpzgX(8j$n14OkqGE~JpN+oD{J<Yk0)I`VgAV#X=
zb~DU%R0#QT0TKA!^LhGXS2$nr+8pMo*X@7>w8P+iE1ye+VfM<oCyDSk<)m%+Lpl_e
zE+#~PL8t};BmE7#fm)@D0#xFGj`$)*lObwksj>;=rmcJy9Ot5MN1E)RrtZ2TNFGC?
z9kU-zGZIGnGD=Sj`MnA~y8vymCB#tZ1y^tvL9@iqWX|eJj+U^)l}s|_ATo{E$}J<r
z?}ISZdRybT^N@N7h13s-6AN7LM#`AundMgo7jeddu;2O(%>LTY2=4q|7LxNKFrf|0
z#)Y;>f<o+GmdDFK5_*$0iFdJ|eU)&*RH}=`NJV|XawvYVA3|sSWrfFfum}3`dBl_H
zN)gH#?9ToHw~et)t+v&oi`4;zs$aEsR?O4znLv(#-dM%1=%#nT<4v;Pgk-=5KR?m%
z7G{5dE8JH0Mh^1ci3>a4AwG3F14S61d?+|qnGHFB+~v*vrA(&Xymmp@46_w55#<>Z
z%3o!7&V{*Dg-Y|srkU7u5<#!=1(R?aU1GNGK$Ug)3Ok3ktq#oQ?nLkPdGF56Gch$!
zM1I7(&I>hy-GNL)vUz1y9)HruJE^{ZLyi8|EO6A}(VqJwwg^<u<#nu=Gm*-Bghly0
zihFAjt<0>pa)4u=yZBvhYU_H^e2wSp^7D>Zd0;vm?$Lt5exT%D5fTiN{i#IIK)@ra
zR|!D@I!*f!hr{on1+m(y2+Tt)5mBj?dVV}+(D5JsK-38>!UV0hx`j_If*%2acx5Zs
z{lY6t$Lm=J8Q1HcSxXUQYjtf_kCpAhT5kfgl_kzP?b0e+aqr^>dck!6nQV;qy==Hp
zy#cN_QJG!GOE`KL4p2!VKW`tmd>l_naHBfp;_@q9=>6#tY|<$=dG9~uJk#w%Zt{`q
z+oAj-^|$%FO?`au*eq$<vo8wn>B_q>o0qM#uglN8<e4eI)zu!`Q9$Y9*WXjx8k86D
zU=k$O!M+kP=F-DRSb#!=UX;ygFL<NEikO#6BXlo%Q&B4$Gh3O2skdP4J@_+L>)x_`
zGX<UAc3Z>_2ePea%%N*mTPewh2!3kv##$bWP}34K%I3cFk8dlr+PWk1-+j)!`%cuT
zPpqiD4TYGyy8;w9{@QWgV*53>wti$n4aCj-WSxnQxWR0-aaj;)_*%)=Yu^p_o~vDU
z_jkH8PkbSBm$2Hptku?~CztH7o0~AGL-kiTL^pkMYx($JUFym|zRbJ!pL-w9=%C>d
z5cBARXjIC&1{M4kKwJ{^S2r63F1ogo=hdGEn*vSepNN7t+Gf^2v6I}n|I>31M{9Be
zEQWa1|2M0xP2n&3((7hZl1kBo^O<Y+Q|^1e*91x=%<6g1$+tF<mrz5lmn{a1y_dJx
zGTv=<r<17@X{myV?j)~hu~Z|7x*VnMrsBFM-z!;dy|v8U1J7|KtF4mksC(iv?t6_A
z^l6c={wyB)z3L~AxFg-m+tcNhc@a+!h%1%{z>ge&ccF=xYdmASdW`wH0+q<>s)Hv|
ztqs^tU<ER(4VrSK*7NgVqR`gVa7GUhjQW5}6rP8apwK1TP!mo-AG8y&__pt+sQg?_
zGsM}nf~`Oi`DwqcN+5_)SIZAKD4^QVPXrm&e-!dnw@io<(t!b}Nh6PPd5H^x$tDm)
ze|#F&ZF+S=N272fK&CKB_5ralsFji=YLNT8DNT_0GQbp!TvAyFl5EAyi^z4nu6@X2
zd#xX!V5_nPM?)>DaeNsH8vwuUR=rP%XiiOxpKamov|N+ok+{rTeASNcFNZ{&BKE(A
zY}Ge0Sqtw`$2Kit?1`Z2WL#Uf*{CXlCgtwAh3|?e2kmr(ropeOD!~DPL=<M?Y>s7c
z21M*|$(#@3@{9b2Lm+E`31hxJ7t<8_9UnYG?BZuE2Gi?au7uc|Ys@F(VeFb3qyf)O
zJ9O;a5aR~<l_+}oYUtK(uXg*6#}|2m7V<P;kHIoD!J%#l>?1VNoYmHo<*_NJb?_aS
z!y7Zz1kf++QFpQ|r=we1bZ*5-w=!EdsmMqf+ApD1L=k7v@!X$YgCbYef-8e6{z#@o
zBcQLved%hM_Kn*InPiU>15shXzvI2AXN^r<-vc7MpIaa_F$cRTTZ<2-kpWV|l?4Zg
z5~Z$lyH{J;<j=;xJP@PyF&tLg+L2R07(^JjZbtbAAZkZ!P(!Y>f1eD~K<!Ag%Hs^v
z6>*V@(y77QHdhir%Nq7_H*YdebR_t&5V=wf2S`08u(I6)wG?}>BZ6M>59BN|wQ61N
zlc0331N+oYjF<O53;S<BHp4Di!}x_Mzp72b7BlS9r>KqM-TlJ@sEoVDt`~C&uNcT6
z{1XV{d^vF)2WVYPy9aaBy*FQ_Vli76+%G@huXb*0DzB#eB<?(Yr-IV)5w^mh@}G*C
z|IyhTvy~5-UEz8<q%>aePrB-5^AsP#?OC6Fg6}lAdzdPErsbX}KiEFA_T{6!a{0=o
z(bcN5hKYfK5eAB|rYk?sSbQbJvs+al4g!7Uo(-G16K^$19*$c7Hx2>U<sSs|#r(dW
z0%VeV<s;JV-#G+^qcFg@-V{%m!}s%W90zp!V-!cU<=R)&DJ<K!1Q!%;<cSK@Wy7R;
zbYQjhHP_6pmUNHtvY+>&8V<g+Wmz*@J6C1VU31DS1tnRfPgO}6Sex1E(jcms_G@L=
zwfJVrCG1iDhlu>!&n?~OIhUsV3agh?1&IpV7VG}wZ?=nt5MB85=Wn|8SC(11ofli(
ztK(Qz5%2q3ey5aDMAATC4=Yh9>0vAwSX7NoV~EHv4s)K`GQ;xGZyYscXDHjNMve5|
zZE6yXhFdGu1+Z)q?kaX9)N>dvzWYV<bfhj&66rQP`HoV1sohb`Xhrw{wqPMtCb^F%
zmQ&e0SpRpQ<5sT;rK>)2Ns%-G_CT0!hZUxB+;1Ut8Cx#?cT<vWhYL!D*%}|W)m8$+
zEaum;Z|Ss)8=IGAYQH^6=KkwtA#DPfd#)u)+n1MKzu|8E2A`(<t8C*)i<gjJ@aNfj
z`0YbsoT|vqooU$_t#-Ra^8Oa!I;CZo@_ryStyo0GS^VX%nm5>$3;G7K3u*2l>GbV<
zHj&j<^<Kk4*;ab-Oz_~&ER2|j&8OTV=Y=u;Xa&X7YRD*39RNFi2A=Z8>6dT_VMNmR
zmfqrrUP5&*UugW47FqA@y7iE~y-yy^*PY}Xwrd>x68LtUbKmaXAKcWk=A$m>(eMzi
zzk!;%fd>D?<cAuw)lCP|oxZ&7;!j@T^V2U!?kl}_r|)()rCPJx*Qv7L^3&tg{=UgC
zLXvf7FS6k-9Y=l^=F;w$wx0sb05W%ny@>A^!1YOYd90?quW{+T*E$rDNL8dQ7pdtq
zRL0d?(i(-+c3tNs=9DdN?nLb8i*XgS=a(^W7P|;rELb1hr&grhFU~foDTCYv**_bM
zK-?N0`V5#znkVZvS9lkMwC_W?J0SV6g3fgd+ThWy`G;Ld55I{xjOJO!h5DAfD4B^5
zmbu@fj!l+(CXYf&kUJI7fa8dsJdj&M)VRUbgQ5=m4TP-g(1TB(D+h-Xot0RwL124Y
z9H?4N0z^A_%(~KsY+rXLU4hU(k94xad8qYsKhAHJ4%+y4g$ZeO&Bhz&E6F$++#5VG
zk(VVAZ{tf{upyn^f0!!o@Td>ogDYNW>DBT__g`u_**biEU!4T{a60oY_CsTOe4nn?
zt%ZdpGlQrZgE(2sX{bsV`AiA8)(pg8pqEtq{=hbpof1$K%R!`l5g56}hIdxDJdcoh
z_P2z@F(d^j+ibFm8woq)8e^&R6Rk|Wtg{%VoqdKpXcDCXUSTwXf>}WWY|>DwVnUbS
zDu&K^;VT9L$LO;c@o%khBG7`c2!EGrg>3FxS4^FS{&OI`Vn)EVZ6xzUh&E|1&k_z!
zkip4|8~P1L<Pp@$4mSSPgCo|Mew2}oxJ;@8Gzhh8PGYrcx~=iuox|xxsvnTlpK1vy
z`^_Q6?sN5;{9|0E97O#vRXkJY)34YvC7d?dB7wk1j(Cbv$n=8%t<3Yq2YewlW<K~z
zBmnD(WaSD@5JE6Z2QVBe?L~J*fJz!~xTQP|aV!lj<R1+_k;J-eu5lCkp>`ybs6e4F
zAnr`^8|tgsl3W8y<!AB9Fp3E^<m!nF@60wElHe|^H~wYw<ZiRgN`lJR!$>F}S<|M5
zZNi<ho_Kxywv>cczU9KD%`|euXCIdyC+|+y^>zxQW%IkFO&4E3muo;I=%#mDzglZz
zdpgSxe`A)Lb2>iCyRGy@M?>UX)ngN<*Ia(j2i^ayRINYBtQmmGt2QrR&4=GYB^MYT
zbSJTqN5Z<x&*wh4@2vAp33#eA5hBz-`lGeXv;o(#Ac}BNq&cnR7_LgHA8$F90aqtI
zc63N7yDu|)z<RLp#Q7^+#Dlu)2M~#li<=UU0^fe;?S4^Ia5wuvep1?wnGpCKm=?*X
zgBa(?;qKWS<8W=uT|+NPCY%;}XgwpXP4!jxeb5In7z*XlpN^fY?H$U{`K^|ZpL&te
zpZdMrt<lh=z;(=4-k1G@kVoPwc85ObUyo^{HOr~D#Bh$S#QyAc-rf6^)<)$Hc`JTr
zbt)o!eE-a!Efx2Dxs|WvM?$B3hR-c`_+rQy5TAVTO47e0IxlJz0i-&Vf=+ztj`k+*
zG|alV!@(0hV7B&qvZ!Qmc*)KorEf`ftXfEqL25nfn-<!<eOUd`W<^IaRvEmw*L#7j
z1lPUO%5e(3+6|pMVQF$E_&j_gWn$;wMo8Soy9(#Oo=KDJMgS2`=WaPDY8V`zW&WcT
z+tO1fvIK{Fj%zzOw|vi?sfGP4r<b~?|EC~QE1T0)$=U2`zM^sKR_|?J$c~-)^kshL
zhu)OEp&Q?~HTj1>S-R((cCB^D0>byYU-%xgx!nuiSr`}CkAO)x+kM%rbDz~T2eff7
zef+b2-RzCpC#;+EAhT6bUj2>%J!0K^)rhnZdVx@FQF5F)3K<J7$~M0BaI8~G=j{+~
zNAsxFjt%%GC^9K|fwnTL!18E#7t%G5EkBmtv1<_fxq;#8gaj7&N29r1mdx{!q)=B~
z<GD-!Q#@vygzK_#eDj^9+k7pQpF0{{?*_gXcu9=$%UN7FPkV^Jkp<$SE}6TBmpc)D
z)qRlq!LYaD5_2GgS(@4#Y3j@Ks|OIpu@=U55|=Kx+YhRbg}Q$hxsTHL<W5RnXh>@r
z2~{>R6OCttYne92uxVr`LEMNb;FF{5QGCB_G4QCFSDfd!E=ST02iAsZ4pBrU28t^Z
zc}UK{wRBxRtZdy=|J08n_oND0<V#kZHV*aNnR>oeFY@<uR~ORO#4}?NW-(}^ae(sy
z-mFVR9?(c3Td2)%5PY}gWr}=@;G6Wl+S5Y`20=M?<=vzY)WaxtZ6(7BR;-R?+bH=t
zZb_-4qd?5OW(jwJ@3;c?{#c`ZG#9*)oJC&*@>(WzLE@ENsrL=cW>%3(#)H~FS`$6q
z5F<}2rzhV@^xN*b=<ieX40*TtWs}TJ+#*bd<kNBE!jICbZp)k(&cJiis)>6Rhv#~D
zBEJ#f&9tR0BrWXK1qUbk`DV;Mf|a5vNLP*&EU4_-zl1e;XZqp29+giez_jxL*EtF~
z2B6d?M^O)!g2!qNb++?;gj8;C7N*4&?_JACXEZO+r>ax$<Mg)r$Pk?i7DA3NC;$U8
znhD6f>6awkX+DmUT64>-L`n838l;LII>v@eU81=kXt_+gR86>-5wX!w9O!yt^m^_P
zsC7imj}N;THaA>dtT=>CAP!v%Y#idE`Nz2EKJSC?`;w=(z~_@|f+8-0M5d`aqohAN
zH(%8xAwbcOO)U1idY7*@_<|nR3YvKAq^7Fc0Uhpqwpx`(^>Lsju;9Eq4z;xGWyfzJ
z++B*P*Pzr_mgVDF%$BKF6Rk|GPeccRUsBgA$nzah5++?&zB^y2M3juq!KjP<QK*Ob
zb=a~cC@utZxfnt%kS~#?$R;Ma#Z%U*DJBJUA8#Gedss|_?=RM_w6W&CQ?(cB#w{{&
z$n~Nld((KHK5kUAGKjac>~P0ztlA3F&(ACw)BGEOcdJ+tv(T`M>LoIu1wwZ36`?;^
z{D|S~<}1=B;nSIG#X~tH&QEvSdH3||f@?kCvhpL}3lr^OBhhqsvhDqsCE0|fZo402
zX8KE)&=L+iUYcj)HyNIWdN|DFuEnYJuZ>qFx?MU{`A_~y=4S7^EZDNqa9+fcJs;sH
z+}-TPr23c_dnR$@ihS1Cg3Di-C^yAVnRtE^N51HudcP1zU!2?~#oFZz7T&Q_S48d)
zWXq;oSFDJYS`G#t*ZP&(cX;xhL!MXW?uyFCNYpJww}aV=l-De<-W9U!?62pVgy)d6
zZ??i(rwDjQz!6Rot{ApT!rl*M(FDd{{w^g~T19BJb?fNYf{b*-kn<vs+{+55b?G<6
zOA2@Phf4ReA90bde$ZFHyq)ROB3?S1Iay|J?#=nx^_jv`rT~}xVeuXcneTq?myhuI
z3Z817R1RJSfooC_4?1BGQBsbCie*o&ZYEZ$N?1lEvj{1>dHb|)$T2n1z8AB#bGPU)
zTWva_TDxP+Je7*ZV2{z4ss!Riu4{@w>e5DN7C~GUbKYKMYU0f2Cqop;G?hMk=JvFt
zgvf0+0mMo%!y#ML@lIXzl%aBu%0oqpa}*=|{&SK7fA)LwP-3?FAYPD8U2%%>q29Wc
zrQPjK9qF)rdGe+|W9^7zl-%UWSu?0NyNCSU2){b_RZQc%+UJ+2-sO|=D^9~9E_FYH
zRBxN~y4Bh-Q4b8nZgn19jZd+|uk_d)f#<?SR2Cs@)pBzddjYC=i08}A%7i{rFahSY
zok{fjt=t}02|xPkcSsVi=^8;ByS*PrE1hJxqBj<AtY?8;R_JuFdC^q-N;c#~)G-2D
zye;=sqCx#=ahrYI>Pn9j_)n=;F<Ti{W46*-8jx70)X20hT_PL`soYDWi(l4_h%6{%
z!JUH_a3p;H`Z0n`8NZ$<*#$$6xEygSlW)wA+P5QjNTa+#mvx+`><W*Dwmqm~Zj>rZ
z*pr64x7JwhR5pf%ds<Cw(me9`*wxx-t#Nl{nq@K8dD-1NH7gmgFFFlbz+<a%t}7n~
z>DuUO&8!VTUq8s{R;d#M72ivinoDI^yUaE76`o=*W;Uti7GKRBd^hpgl~`7y=AmM;
z%8{Ddi}TDm-2>w&)NqK_rfOMslM3lQgX<zGe|PMGp-M3|!=C&=NSD$Zr;byhnU`SA
zBGBPPuzX}X+cIpU&D@6lphBXy$b&CUGGhYAU5WlqedqL(ckz{Zl1o}6)np7WY2q^$
z>s+e|9q7*TeHypcY2q7!AFlN^M}#;33-I)*mL=MZTaUkmi$5^Fp|0r0!*rYwH`Cq<
zA5&f-5Go}Gy^hF!LjmJS)PWF>xO<zPYG0z5`F-)DkqZq;t)AF~Rr>CH9Xf`))mMxJ
zZg<==eGp}swpoED*>Jb)(oIPnkLnhw67i(zC;8oi_Qe1}O59OQD*c8nuvt736zZP_
z)7BAtoVaBOSs(@>Io-<5EI(01^lx1Etj34U%=N^)=pu}3`F2O4=r&zl6IUHw1|bpW
zRT$b=Jn<ZteRs|nLBe;1914+f^Q4mi2SP|Hfa=+S1gIg%^|}~{q2%paXz;R1fI8+$
zm%y9i1~?58@A8*4{LCax;_iwhu&T`>4Rp)@t2SFz$ELa_%G^LpoNCw2aaYW)fKS!d
z$3=Wye$0(<jk@mem{!@;u~srpd;AbtrS(3@!?%~M5qSKOpYedzy1Y4JW}!b1vBOn_
z`$7Jy*U+|u<|Oum!mT!MXFagq-H+m8+yg_-{zbf)*UO%!PY`K}N85(ijal!{il90;
zy!|>OsSG>fGQ-}kPl-m{U+gYK^yG2|X@V7A$Ds0VC_LHua(=6vob}jF2-9Bm?z<wE
zHsl6H_F9*}*k3!=XO<&oYkX8mr=$3>n@qJT>6yfB`;WMg%+@cj8FPq;e;0jnH665_
zdcFOL7j6{s1F;jov2m=^Js$GR=TXFn%2Sr}awisM?yB6mB2IjH{zC=E@0*p&a43r#
zw~A1%&8H^PCl2@uTGZQq1%V`tY^-sh*M3Wu2T@8cYmvCd!MPBG(<V#xT#=tLabBJ)
zzUX|EXY$uW@VIf}(m9QUH-#JlvApg}u2>`oSuSUFDi2xa_q`~n@<Ldfiy3xPAlneh
z)5~m~gK72xhDSg8j@iYa91yvE?XU2>Tzy{5y)eUoU8<3DmegbC-ReDsw#kyKCwCw3
zp;|X?U5heX<I(NRMX`d^&HrS^_Z}}xuYKP2^-J9I5PA8rZ)QPn-QGRz!@L)%k}P~9
z^2Fs!NORZvVs+caQ`Mmu1JNVkcdCseZuu6PwHGB~+0}EUkY+#1j-JNG3WP_4Eqh*o
zk65L4Rf>a_Jp=Zv_w{aF*S+hKyi1Y7iPKE|VQN|q^QgZ(aXv4q-?_RhwD)%$s4n|@
zK4Uv>>sMGksg$j0vL|8qw^3&hKh|@@i7(~rQOn51H<`p+ohVG?r;amA`_0QUL>dVn
zlG*Cs`@!PHSG@n><#YFw9dHf~p}f=V+4k1=&<|p^W@e=SMd=>B_H>f$!)Pj(fqx4k
zN4?wnmH0EA$%n6Z(^oi5SU82rTiUL(N(a5xE@x)m=2n-t`AS1`vnaFuA%^bDSWx;k
zCP=qFOLmEBphUNV*;Wl*-oNz{&4Jg;c}CEy?E*O558_(cv+YhRrpS*<d{!{xPpJB9
zv(*+t<6lCu(#mygky_Vi=y7B>+*k5SPo5i6gEGMhhW3uxx{-K2#y*3$VbbW~Q+?Z!
zn4eor5!=($$2Z)$T!kJ1xy;u5f@<^Cw4c@6tQo_h-^b*Y<^?N^SQ(sc=_UTgVlI`^
zXS;UmAy>(4Z6k8-SZ#I7-`;_UXO*tK%Y$?8oLI}wt%S4gcc)@;0s7IB#o*ppR@n)3
z5wFVj(I9MV=&wLDh=bgLMv+K*1C%>`8!Au@l=L>t-QnBS3WX>Za=Nt9Z8Nct(x!l<
zo<Bh<5IIE)danBMq}86*s3&e9T*g2mlbhT`(OZdJhl5^Vv{dcGs?Kh)vv5UF!<;(b
zoX5bbLW#FYn1X?NR15Tq-r~0+bGl5Cx_abtS>T&0c*30WX-Z|@gD#$kC4Ny-$lTZk
zt1Xu!bK8eq=plip6-NPgkqlbtlFX*jbB;W-O3qpV&4RY#FpOtwt@oIAZSZ44MF$V(
zl<k??Y;Ce7BI%>gjF^Y#T0XMgmFE?ePMgh@eekG)Sz?s9CrLkT<B3pS>QpZPdUDs;
zSjo~FP8VPMwEUT-oL5^xw~x+#S#ejBZBDaRqN2Ps-tK;c?EA`llJ>PU=@##~#de0f
z2s@r0HP2y=UX`<Ex-St%a=&zbUy8lRE=8HBk+!zxcPKn1&|<J@EXG4|&f+$}#!sPA
zjia~&R<@`YjgNWYf)#QkbfHKFj*&*YHkW{h3S2Y(hP(yNYbg_j(Lt*!f<>uup%80g
z330$R=$x!R_&F;rL%hm3gmh0b=VqRwn1u9%$QcURj)g9|_^DP1d~B$lRYb(e>PX3Y
zYE-obemuB}c`7~9#QC@;^N9V*Q0y?^;lh%Ag8dSeUU5gMsVL900>779@+uRH@X29Y
z!yZt}H}HAw*+Xz~uwfc4iUy%tsrXq<vQMb^!3=#S=%!Dd<<|Ivs>aW#CDz5)T$n$S
z=>ahUYy{S)QI^p{)+FlVI2jaEifJu_Gv=^5YiAx$FE##>??k%HQV2_di&+U0`8i~h
zcpOL&vq0+$R)o=#wWrmH1n{eimBRJ)m}a9dFIMf9)m<?M1z6o|7@4qrI?eu9EsA+f
z2tsE5dUF|)&C)I}q%JhXzl3g^Qf$8qqKBp;*D-)>c~R7IKI(pbSt$-X7WNF*+bfp^
z4n7j(?!~#6ex`r_kUP98z5Q^Rx8HVL_bkzmyC*WOwqp2<ggk1Wo9c^x=vZ}kO7J*k
z)7~Qk?zXP`Do5Db!tBl2gS;ZgwwIqlNe|H{Jk!dfv3Lr>&R<Q@zs#=>tG~dE`6X<y
zdp)=7Ux4niA9b@IeV}JkpXLd1o>9wOe~Xn-_tZ|__J6PC3uZFB#myhcWG5o>4U}Sj
zMTop<g!rYQ_B--2Y(L)xOd2c5+0PzY%$3RU3*4XOGZQWnh?m_sA6agU)x(F6Ov>sR
zL%qiRw5*LtwyyKBOpfeGHL)VNIZoPm#fH-aPs|HnT*esX<mzluzM#$7NXXm$3?`2f
z{ago&#isMbVK|(_g31btu-ct}c!m9{0s2+Vg|46Gc2U`=K^6f2z~>@mY0^iJy&}n$
z^v#}SzEk55pZA`n$<_ELS5L*OUcL}LX{^|f(z4G+P91Jtx$IV-IpW^mIaEf)j(`vG
zX&xVMqM`O4gVl}-{Si~pQ+aHxznv%3FrHU^S9bKwy)CoN?Y4#WR)q<mLe49t@~{`1
zDYU8o>Aye+RA3q*k!{d)LiM@7WlOY5G8(V}yPi6;s=Vo))=x=rPqxRr%VNqFM#1MU
zJ4|6d!LiM2;=KIQl0M|0BoaO|bAJ2G|0euM$jugg3HNLHE15sVWWqTLckTnQw4KN>
zuua14w`bYi+sH(Vj^#I|s;9AV%_Kir%@+Q@eMhz^g@{CUygfN0i37s>ZUxW9OTB-=
zNzS^Hoje9C-~Tc?_P0&8-PTK`l^T5Q#uptfSVe4tHFlWOyB=A7j|A0@0L3;>D-uP1
z37Fv<fcv?nu-m!~%Dw=TA8F-fMWYx4LbKhZB-`lXTW$Cv<B$e}dfK;pxdzc)wMa`V
zUA%uiVYXi$^oEnS(Dt-1-RaElNS}!Ixdu0Jf#ym*OvI~#*Al931vogz1c!ikTLaEZ
zxj@Q`9rROwe{IvPzTOp-Epva0$;zIVXbOQucKq!)27xPI&pDcBVaxgO!<*~bQz>TD
zH56~88f3O^|D2R7h^dn_e{e)g*fC+koeY_Cdg}XuB)jkQAZh!6Rh5xR>?806%Mv@t
z_pzfqJ3{L2Nz`R8x%4=AJc6k#&yAT8#Q79U)**|j9vR7ceytsDHO+pG7ZS=wajuub
zLhpf9>R&<`sfJJF?Mt3JMHl34qV^2xBBB=xG!Xe{l}73}(eB(FY8*>2sV%Q4ZcwwX
z83w!!R5IE7VmH`>-HIq4n6&sI5CetS5wPW%@sY{}ay1G)f32JC;vdS0_ykWPqf$n0
zLfL>DD$0P^JIats2^B4u>e0C>5&9i+nO5UKd)g*6`Xb7Ha~rzs>14JH;{!31Ezbe{
zZb^Qp0qb2XKgXDv#tJKhVg!`KoX)Y1t+tvnqTxneHhC-5%5!l+Z0bidKdYWB#<4X5
z?c6O<6DxsdHL2V(KVX#~96a+Kkw5gvp$pFQkP8|&*8&8$pkf&Y6$I&DlM|zWYzrs(
zjup{v7*}|&L}Z(r;AEg1f!>m0ZsA5vG%4E<f^zf(qH=WZ-w_}=>_)(ci7$1B6|A=v
zB=<`={C^)DW~99<p`b59II?1>lRFJq7@|UuAsY%|raTL}kz1wL!ai&$@rT8Y#Af*<
z$%uLaTp5HO0Ust_gvycZT;i1yNu3dNjhAl}oS8^ko%sJ)dmre^j{45?ckjD;eWg~r
zZ@1NU+hf`#SvJC$ST>Mp5(k%L#mJ5mWH5>2!<g5O<LOQ2WO{~#X&7TlvJ8Sa8Nry1
zvy(kM8z<@YFd0t<ay+{vJU1lk<n)<zGET<v$(#`^!!iVNlx&!Ez=8dI>)!kH^zS{9
z-JkU8)}LSf>i7Fq-MaOws#_PtJec_^LzG!XBu@HsWx@!_6q1D$iF|^dQ(|Os1Qj;s
zIT6s<2Q(03v7!!U9&%`vS+Wo)t4h%L(i7jLEjj8tEHVp#QVkTc!g8JmW^mMNjVNj$
z%u_K=GkppA<7DcwPRtTZPkoe)gkTg)F=@+5S|+CQ!=UDsrihwiF9YK1Kn1-ndngN|
zE2zcO=QU`om#wDud{~4Esz8`M0Gu5TQl&TpD837)hzdldS0MOWskCn5&Yo$Ljsnz@
z(c|!;zXa4Pc#^Cs%RYiI=R6E1+=}@r?j03#AE;?^ksU_#Rj(MCK2*0`RKEUD7rPI%
zU5cgBD7K?9%|-k;E}tThjY6Cgb+LKe*kOVvJ!Xg0SNDfNH-0&EpRp|1zG=1&LW?Y&
z6l%w8yjX`^An-t>$%b8GLdP03t=CzzXz{g$<Y2Juq+R4X4IAY<k&XO3_c@fUd6T6@
zTOUI^$Y}l~{ZA)7W$8s_YoVAvKz<lVP;M4P3;l0`mO?P5xhoz)1Hng(P~)NQQeRxU
z6m&N@ekMhtYisd~g~S*=lzbgi;0X%!2OpDzTv6Y#SS30+0xEMS*kf^ZR&H<z<xYev
zVI<FHP(n~tx6BH)lu{`wHiA%`d_ocU=;Cxa>r$yxcDz<tZpXxpSk>&FAyk-NR~S_0
zQd|OE&Xq{FTZ)mU@#aW0JmiV%$wco{#I>7XdxBsfR^liFeF5E@d_fN2R2Kggcrgc(
z>rt88UM)5H4%dV@4LzcS<6Pm_ap{8hc<JhyeNdc?E^##?N3nE9TR;y5PaM)m2%)^%
z24_7oR%v^`#0I3|7kF|6by|<@C36R)G58ANUq?Jnm3)OIC}_0QCdG!B1)a)5>NTqs
z3z3GW7|Ie;*a-O+s3MAWHU<v^p##R4hq{I)j}SQHAxMQPGeZ^#Qqqu%pSjSJH>VI}
zQ?d#v$0P(Ye$J86;~50(pcCIKsvw9$O!R=Vo#1M0q<@M4;z*FISAZ!kn-4LN@hqs;
z;z|@A@IsL;y5kTv4wpNgZb}*ia2AA<r@k&b79~z2gyQ4ka?cQwmUL5r`gI`X_pm%l
zYRLoKD96iD$7u~G*A_bQf-@aG?K;^18YFF9aHLlSN-8Asbb8f^ipV6_5Lb_tyqZ)<
zqS4|(HeJA2ATSW<V}gVugC*Z>r3#tABzUQv#f4C;^ztF3a1M7-yN{?i8AvUN>_bz`
z=UdUK%vK^xYOG#HaG-|;c|#2McSboDW**dtTUVwEjL^cZBg>dQxM3TPB;N)ZF&ng}
zs)@y|2A>ISFvLE*7p*HojPzQvDJd~FoN*KuLqA&SZW689>x9blQZR`%G7v(~NW}Lr
z?#hN*=f9J>RlS$MzK9r@FM}aI2%>*Z6*p>=J;-)E_0}25)KIyh)4<j1;Eh3Ww-BTQ
z(ew&zg6VzvM0{;xZE;ilu7T`R4JVEHh|y_?w1D#h4tdS+@frtT1B!8S)@Oq@xp2?C
zzlvKgHR@DscIVIrYL&k8Wo;;E56M<=F@l%SI7ETZBM6H5Sqlb_;RCRl(6YjOkD~5R
zb027AvD#yX-JOmdtJu>lo!yj{6$Ukb1On@LRx>1SGk&#uK|N^R&NCY<lG)l3pR65(
z?b8W$_pmuTmRj}=OavtZ&UmZs8av@8Kv^ixJiM$K*1dpF{YL^{+BSR5P2#Kv#A2AZ
zGEL(b4cF_kdN6kKzV7@hmsD#S4OyHB$8bT6VthT(G<>G7+#?)-&^C4fL$mW{v$b{J
z8&eE#*zr|8AbVqBlkbw+_W;+h;*%^wCl*^}pxDgG&m62>!CHt%qC`)%V&yqZjeR!u
zR7=`}U;a7nn@*S$4{i3N_6+{P(0%id4@Fq^kQLlk{w!3e;QY`97nW!-vvbcsjI>vp
z{ihE&-|<5q98<kcN~NFwjJ+y<(B(604fF)chdJK!qoj7k{FCbsd-ufc*zONH|Jwnx
zh3{)VDlH9wQM(vUj^7q6z*#iT>l{%*Hym7;p)`&6e4Wtu`i4&=>0>C&#Cbf_g)5B2
zo<;j5^XeGU)o|5ornGG1ya-Nz1JUC;+Jk&i1R)nFcI5cWYFvXMIdp*<o8IRqRP3qq
znoA0Cw59w3W~MH>dD*TOCEl-iRLdo6ZP?Os$$$FSprk)ivV7l*!)a)6?5$7-0B7{D
z$1JWq-AL!njzMOdg8PTm>Hj8!mh7F=IPQz|Pf<3C^}p4aESDz5G7kekcI~W9o@0PC
zM2@`kh%4VCB;)i~?G~DWbIZSF$%#%<6j1TBhCwhA-oWn37g<j6p9L2|H)Tq`8kqCi
zr+C|&g2PWP1}&TjM(lxjl@ryJJ)Y3rRAT^pR$WuILvY%EjzT((GKSrCh^(&pzsI8S
z41$|5W>`QG1pC^!F0~{llf|(l_3w#^=hO7=?890v8T#{aUOc2xcdku2tzRvHn&ogS
z2GVaTyVICscV{VqVeJ^?o2{OC(to28i||^<vE9+WBFK}(8ZYFB;(o}uO7maSP*AMr
zvqw`S$q=<PYo9<<^C)cc8EmBPJ8^**nG5@?p~;yQJzjq1Xef78;vWEE=$DwZTf4*2
z5tr(Y(rx4_W-t(H1#Lv{?(?XXxgs?Lpqn#RD-js)u5KWiMunKELPU5u;RKE^Tfw~A
zf+M^a@Cl5|P>9eDy?L|?j4`$sH&eW%;}bd$ZY*0U8*89*<HoJBjDu2Wj$t6s7}y0N
zG>Lf_Qzs~}8MLJZZSd5LM%75d1@wFoF+;|qb3D!~6PH^)G=jiBB_Pe9j-;(lgegTj
z(ooJPJ0%PPN>~z8I|4gss;3jlNWKSX*c=V61g?Ht7L-=PwB%yy(8plYds-$2Br|IH
zXed$AMr&8zN{k*imtRFEO)qaRXqR81DviLqTRcfeLrY~Vn|>Fg&<GCGDs4Me`yc>u
z6^0ixad{tBqKa3AL|(W`f$>#nued;SI(ootrbW^v)YmH4+c-=hpOS?O5f5i$vxot{
zvbur~oEDm^2_pIH6424#4}eZ(9qxkWo53QhVHbpL(JP4y4E0O=v?p1b+zdx;B1ZVw
zFyp;iAw18cPEvS|ri~S~IpYqYYq2&rq8p`(HX`sz;hTYCJ#E^sAG0~OwvJcHiTyoZ
z_K!?$&agEU6cKlxwVS~um4sQtrH;FELwGn-wVQSLCCyG}fxVR_L)7uLKLL?e>P(fF
z31t(AjBDv6znaRX<edX9<Ix^ym`)|TE>hjv5IYcA^ysXMvx~>6Ln~oGE}Be@Iazz+
zmFO}no~glY6A8%Xl-0|@z?<O7QPeGkX|F@^9#Ucj(QI9+>)HoMbeVx(QupRH{tnmV
zaGjk*Cj{!H)cuM)z0iY6G^@#xw=i!VM>tc_#XsVRj%iJPwfJ>m7NK}nH7TJ;UqiG{
zx@o(5{G5{L)Var<yRO7@wN?u|^$K@2ubO_*9v_a+!4jdL`*s*!`<@*!ykbY~w0k}#
zFMMw_7dt6C@`kK)OLaq?V{CbTAGn`pWd5m#UBn&WWW9&Bv3rMyX>X2vVmyndy>uFZ
zLuQJ@2<Yt8^_HTeb$g*<Bd0F)WsVDnmzVgq#*O6&s*KysZAV*l-CL@+3f)&ch@Q7a
zaJA6dg);}^99uhCpP<qXShjexn~Vdz749l~f#1m)Yb?BX*7MfjQ+2-B77m5q55H#<
zWNd#V=w-lhH@IGlc1um{7a13Bn5|{glH2)kGi4){>sl&xiMw7;J++wL@=p$=@qiu=
znmV(LmgBgZ7{VS1UV+B<(L}j3p6$E|J*?3j&__H9V|DzJWK`d%zj3XRo)qo?DBPEL
z0}<*?wf40y?`L8s7JKw+c@nnpYnPv2yO=^S4j0<b`Oe}+hc0=_8P##f!k;lJ&q3{c
zgW2nEUKxC;1m)fp#=1wB1iow1Y5pH6(&m0LG4~d#^$;0@GW&2#IWE*ED#QAlZRU&b
zb2f2qC<)K~d~R3#%~1N)Phs0PuCUAWNyueoLT3!7SPb}W_#Hm!{d3PWvY)^nb4ncm
zK6&lvil2Th#r+am5v>{|WT|ZEN=PYvAZW+n3v2rh2a$3WdaN$|fuD|ni3u{~WT@%G
zDwe-%f#Su1CM(uD2N$ey3^R@7y@3DTzrCET1AvOX1{;vV@~T)LP+2@vrEQB;K4ngM
ziv4#qf!}x)vPs#WqSt=vlT5#mbLFj9GN=`ezQ7s<BE(gGpWSL#sl5R1Uomz6XV-eQ
z66c9XTc1g0qDel2+1fdl`nox+g=8{oH%|w9=Ec|A;?Q@^+0jmjnWXK!;0WSyf|uzg
ze`VI(g~W-<nWNC`3q=^Qi?N7SP9x=6P@%OM*3G7a>_-ryJHYYLPP?sPZdb(GY~3)y
z&Z$EGx=`UE&W<H7%>;YlSh_orZPf28`73igpv@zpu9rOVWB7TE&wKjy^q%ZUF*|E^
zVJWj0*=!P7zKLslD2R#N&V0Z=ysd=o5z9k#>WUr<DMPkOPvN!PZqG`X^8U9;`)7?=
zndA++(8KT%WRfqb*o3E#ow?V=j(CW^x^1gG4oe8;z8Ah1ew3SPg8lptvW^awP$lnv
zaSX^-*jl`B1+C&E8EtwSj9ZGrp4%4RCjz!mS_R^96W!h$&<RO~1OwiXI6Q!pqx;MI
z$K>53Om8YBK_7~cc6pNOS1{xaZkjPAit{Q)9k##=Q#D@>dM3%L4s<Zc$P|#@I~C;=
zDk1l^Z@z3{%bd6$vGO)4;jD_~&r2aI8ZB|15EJ4i!mKvALUfgTOS__mC+ixo5O%#l
z^SYGB-=yCWg$auL9Vt=d9Wk~>a=z|y>L`#SD2)Q*!P;F4M3j7UY-4PgM9{1`)Hw1?
zM!u96Qig+>?xa0J!|jL|s@Rx{-h)@f$}oqGU`572oCZP8E`!ox<XfnHV7Akf$k15=
zd!jU$FuT<x4)<adcS$=3-3KXy`^Va+SOab{mUtAwlMb&w7EN!-G^VV+M42fQ0DoS*
zq{$bsU(LL<+B^C#(YCu@S{G;@pci^W6-sY%KfhbvM61@;yz(Hrz}F<>)x|i39FY<_
z{G59IX?}<iY9R^k4j}dbhGSKdB7=nSt+Ln^#Xu6>p?*B+xMBcN@U~z<H}O>wFUIfY
zgeAL;r(B?<kfvUqK&@z>YER)+?jqqpwfWBx`nfdNT{qbBoVc2yIf0#J%Cf{8nOO(h
zOnKrHNgja~WJkrH2nT-sA*3fztmqdWC-4)vC~x%sT^tsI2S8Bz=57wA$2aFfLkpW@
zb`J#}nR80MOU{rvpUG1JA3Qtc<tG6*%-}FU>H+ezhFw}k1*}-wmcsW8_m{lxlPZ(?
zRzZvLY!~9DU6&sRhFY`d7pn<QinapW$4V$6R-hdCRf}snCNA(&UGfZqf?Iu>8J0}K
zOqbYUBNLByGaWR)XINN-S&TTKW-^q6gNj7*K*?=+CTExKvscDP4yV1)c3U#OHAlX-
z*P^KykyT}MlBr`l1WPcTt<eSKQ%<K37;_A1$NX#_w3SA(d5tPtd6pk#!h*4mvkO0v
zk2zS65{N_}Xls2GXxmS75{P>mx<E9>?<L_(YEy&@d-h`Ponxe)BNz@-M_(DX{PE#p
zp)(qM!y_a^p~PeGWqKJ&SkVQ=!omD(I*}EuDulpMH5zpcgtmVNINz9MZH|Mbd(jn$
z3!%|$?M>O$4}0x@Gc=hp3Xgq&FEK;>yrKLc3=O~28^wj}>=j`&7NV5aOe2XE!+T>a
zuw9Cw`B3(jsrCKFT{{4vddgosmvU9H#o8wu3uv_?`6t&GDRzZ~2OSTm5vJRD#eFqY
zvhhOM(bhCOCyr3R&tGQl_P^QByThCbDq?+MH5A=*R+nAVE?K_G#;KD9%+_eY{K!|c
zi2#Y^&O=w_1q-tUHfa(<lWF|#wPajY7)PTF9req+QuVO4_CGiiif^yby8~h#L(SPQ
zUs+^1W~*%Oe}xV8qEh?9sg>7dBS-SP?mm+)Fa1>P<2Uftp+vJ43;5d2ebxrjCSRM-
z8@@a-ABvwd^k?Sy0U0`uO(sAw^2;);uPa~uzfYc7W2humUiZ_5`R873b4U<-E8_Y?
zn`AYQ|5<1%c7o+;8beO8js*XR8aVIMO}o!g0;Y00<tIwn-t{|dU-<JRTl{_spL{gf
z17Ex$<R@|)+|y|yjaq4|UzlIG=#Z0?oKK0_nq_zLsYfYrK@!VsRWk|0@8*qxmTW96
z+{3ir&R=n4=K(isSHtpz?uPyEyM-J8)Mz)*`=@&6Z^GM?FDCYnK=DNOhY<!Z-~13?
zB{^;0Up-Uy^}Sh|>x5d&ob*Qa^)LPpRJalc5)n^1Ra;#s0}rsq-6`)w@oub;9=b2$
z_-|s%y<};wKJq&Ozky7DTY&~)Y}Fr|NiY}B`Z=mQ{ZTkXX?lMRvz4-ca>kEbMIf%(
z+?BfI_*~p2N>m^4+49hIHMg72ZOBMhPXAjy1XMXDvsDFh$Z#`_Pda1^OvzgM^-I$f
zBU6uvwG4&0jylf@qGs&H;ljHg3yd4CitEw)>*QUpcV`bDnmWp<GgstZ+g^6)@1z$q
zAKg7UAwFO_Q(KTx-zJb6d^8-(Cex!9KTVp#i)GTLd^-pHw&)Fdw$wy_;wOmguss@1
z7&EfvEgmzbq|{@$;8f>}PBH!Ake=ivizseQ5)z?;V|~a`sq_32by)s(YvH#g)_j63
z8zq&fg-#H#xoV;zNPO(ra>9!dJ4gJO3wOYJEKIrj1A`O5GaukYYdgRuh3}#1#;g*g
z!D%}@rX<`Zh$RstA?X2G-DIgUVno+9{d`a`Bv47iFdB%X{)p1wQLzBLR?zfSR2fDY
zj$#9UHX+WUc5IX&;F5+@J)}uFG!LFxAuOCtBqHV(hnL=_;Ze}!2$#Us^D`PzH?L+|
z0Kc?~8*=lGYqloY#%Kzx_$1t|*!2v;W2WWAmHHqtk~=G&J9OD3yS8}0T1kE3YJUP`
zBwg5!<`vcSAx;Sd{ODsaJe=5cU#!S{jp1ugjE(Yih-&KgVzOd&PeqD`5My=)5T<a*
z1<|&`fuFz6vZ-jg5Quf*@Bp*?h}U)mL9AN#!}u8L@2nK8zLZ~cq3lp2H=KN>MKzN8
zvRbAT*Ws5U+r?bte2q?fnP}O{yfwU5ThmM^NgA|XQ?`!!Ko}nVW^;-i44sJ5k}G*O
zsa%nOE1NbxSRVjUUEHdBhHin8>6ndYQn(x6iVo&v|G*xAV#Qkzf2+#n<p>^=*_zpM
za0I4GvsLju&^ABbroJ(4rk{}*^U`8p@OiNSg0GM~vy-&~V_s45@RThOtQ(XjV#*v*
z^dr`Bpzu%ZayiIS8+EZ$BUZ+|cei1@&C!B1^4r5|tG8)Yf=_4$bl>X6E0FJ8mQF3)
z#NNi&Ce3>9SDn7&H7IsoTdArZQB<5lpWc{$Rj>rUfXJ{Vk5v$`+mff^R<HFXD)v%)
ze|Xm|HD>>7Q1aSF*W_*OM%|{-S{`|Pn1_hDQU5h(S?AT^$->X3?BDIkY|SxSr?eG!
z<fvcNXUVv~xm6-(qS_DU!_*UT!x>2F<dr62y)w*m=XY0IPe~nZ?oeG&>GIfxUuMLA
z6EhWShkUYfPw>fmk@!sNZQ=XElg)F~YWccD%wt)*H92aRr6D`>upJDSg&Rv^W$KP@
z+yO?)@)s=KyxN-5z`jJU@jvaG2=S{4=i&<5j#M^9p1LqIFUC+M0`l|xwBOfp?Iw5y
z&R*f;lGx+;$7D(I0eWU=E-+r{yosGY@3ELkga$!*fMr!|?*F10pL8mA>RhtSE19Vu
zy^x%Z=GrXtq{RhiZ4MUAbq>nfHx}XSD9_((kofsm>eCE<P>BeJj`TGQ-FBh1FL{o7
z4X9kJt@b3{b4+-aA+LY_7Iy+{9l+XNeR(LKVc)gBP{9FX7p3`a-_Grhr&Ifh#)F9e
zC01KkZp~j%E17^=aRZwphv%}z=R+ga?pIGjf9UY6R&j^^f*F>L)z(sxaU<<KyLGjZ
zHg*~PiIu6xzs7j3gK2`97;8n*DkBQ1fcSO#A-z`ABcJ}puMfpqPbfT2WJZHtdw=%=
z=i`d0=!rVp%vB_|L{+TM%9-WydbM?=#hgW_ktN?VYQyK*MIWC0;gYlaUtF}I6K{0a
z4lLG9Mzht9zRi;P<Z|9aKej-owpLqp0Bd}D`Ta{prcJ_zv<p(K_ZTQLTQ5eo@M$#F
zJnqar%>W9UG)3!Ew7w8^#$<tie3HQpn}la3UtXLO%J&cCtnhQ$tFgQDca#4dnwKJK
zh#kzYeSe(DtK<4#Pmvt%V-jFZHCA@UyXPny&#?-@f3AE4)Kvi`B#!fkyOStWR4l#P
z2BfDq{P?CU8A}|V1@F@5)1|w!yXc6`UTVx6)4)6;7N<FNXGu&m3%_sPZe)(p6Y2|1
z@?f@dGEvb=JL!`)cXh<aZ2iNL=|)fkV^?j~N!Zi!<4RIYS-G`rBfpj8BWI4WCG~9u
z>*r95T3?3`!1H6ooF%Q5gElhrK6E3LfxtB5(Z@!zu~j;q@QY=s8=1Vrp9EU`)|3sL
zO}<!Be!h;|luJ63T<x+pOB`Rum4P8$yppHn(UOuXb}*C_^`3tXL5;&J)R6;Vlk0{F
zy2b8*vR62jVJDArF3BU{)`L-}-lZP|geeaccitM-Y-LQs0G=N$+v0di5kT1Ju->B5
z$m)gc@i5YQhID2*<-nPnWfIqmB?$(`tx$7Xa<w!C%i-w{nFI>p_{fcXn_<+R2yS!K
zfRI{KfywW;;EBzkxJ~McF^V-Tsr#Y_C*{YwRFE02e0u;Dt84-todTecF1YA}q?ae>
z5jJY0A$P*kO87Lfb@o*_beSWqKg=x$A$X7tb48U9+drkB>M8w$LSkB$+giT446K~m
zIgD%{WQSzuEXZ-Dm2HBB7!l(O!gc)e%OIXu;LpeQAk%FC6tfjVF`<@Wy*exuQ7R}B
zhL^z*Igeyc%J^=0ZaO<WjqnUjV(W|Qas;9l&x>RehCSDC6i2_JsUR@U&&x9ip1~%-
za!DK#_$|mGt0G-Yq1>({VGAn3Mk`gzd(NcXzK})stP~+w8!6Qytl`Q5i!zHy;9gdd
zAt+{iU*PMyy<FZ;Yzm8<pPkIZUF>1*;~Ji$9`E3Y>^93Di5E(0e#?zP<Ti+R>$cc3
zLLBu1%<d8H5?*YdELp6UnK}|!6vTIgNWUz^Rji8f3R>|>C%IQRD#C}hG97b!+@PO$
zkjL@!{8WEE_mu*GZ-T^`MuWhY2oy<U3Z-0;U|C3qWJaW(fj59?4LS+d&FS9n<mzih
z1PEA0k>2bPekH7sTwup~a_ft|#+DZ;GeD`%S>x_<o!lN@=hUMeX8h=%s+Su8!BE)R
z3?0ZpCKLX1+w9~k9WsXGrjnk-;?NWG@fw|TxTpSY*<!riTdBppW`adtTTy)7VQl2t
z;tPbcKV{-3yqV|JX=!N__%d{Qyz*>H+!FA5u0K)yQwE>43btT$gDaZKqcLUctO+fA
z#xuN&+#l5)7xv}j^zN%XeyLha@}XiCjC0wFJOB6nCDA};DfMos4cqBMg}r>Ot@@8u
z#9P<I4VTWIr=t${q#=FHk{!`&XbT_n@p#+{apy}t)w@Z8sA4Jr9_RUlL*mg>IMu#o
zo4R(QnO7e`Sh6cH7}nb5n1}tosiSeItKq!HP<Z84saR>l?AEQGc^dXhHP3&Zr6?A8
zrw3aZA_SajvoGPlG4`$vCPj*42lHx}O2|A{6&qh~{g4={P-5Fnk-YH5u{_!LqX@l8
zDayDNmf1D)U}1+YP;cozhCdJ4EI4tK@bA3S=2n+Dt^3lS<JhsaeK!0<MS7l<IJf*)
zAJC3k*V58t0%!W}g1h}&Bbocc%{scsisfn424~sy7cZU*zs-K@M^UDK`z`jvFMVb!
z7dwR66A`(mks~}HDdVGstEzW?jX{~@JATGT<>1{N0!gYBy~1ig|4DR;{V4dr&0ftf
z#01&1dR_MhOfb9RWFEXwBC4=Q_?_?=-e0&knUZNY5CRy-*ORm}j>%Ei(=?G{T=s06
zYZQ$;F&c-aFIadAO(M!)h7IXk3*W!&l97B&sD0sXn<y8I-)T<!oD<A@gv@!j)lPnX
z*oNjO>4N{J5t4~>Nw@(+c3IC9FQODX%tr8BJAh^2JBh#4_@QDoqVOe3J9~r~z&~~&
z*sZ~?c?--cBO3ChP8He(a>Nl*w~0&2UP#v~a^auHme`xN-M>&r@seq_cKNV1PM0z6
zHD$k$#J5k8Bq1T`(64uXGco|0VygTuSToP=+P4}HDXod_dR4LEU5mKaWLpFXwc+b)
z+7!twX`H0235IX>K46|Umm%~Mb?UCyA-}|eanQ>XIeS?Otx8`5c6hBf`%662+%4f{
zHK+$@Kv=jNJO~Yw+}XkjGHYR6nmSYVZJACWoof9XD)7%hvt>();XFvRqx=R#`7vMc
z>N$b!S;n_V4T{liuGP)dGZ>zX*m=}<TOwkeiopy;V;q(N#L{?%cvp#@rGsx5sBAzG
zCF)~4Y>S+X)<aa2u-!&`f(s(ZkY^lqJ^<o|V;#KWT`XcG_Eg<W64K7&t{_t42yi-4
zB`#M9o6!-DI{AkvxW%E3^^h-Zv4Mhho=$*t28wf$9=Lml!8sNhYkn|RRbqTEu%rIC
z8tt^`eq$Pqt)wEiFmG)>?x3X2wwN0Ys@;%V!rxw?)o@cx-`Pim?ziL!6&qa%Tu4F>
zPHz#IRyiL)2%X-@9^4*pq{``&M7{lh&G=UN+;U}Uw^o=TpOA0pMk}q3<%+O(4X3?8
z!8%HBTC!ZP-JStu#+kFX@CM6^%mK^_;|_jW)AQ8#0MIiPSl(DRDkE^cN3V5=uW%N%
zzt5HOlto8SWi1<>Hfw34BnzjzK;9|maIGEm$lykf&?q%iQQIZ&Mzo4W6FRQIQht@<
zB)#Xy;*Djx#>D86Q(?tIwkYay9(vv6ZiX$MaIuD1x2RUU#sghwICGT6;;Ai9pb)PV
zVYK;qe)c2^S=LQ_f2k=dipHT5#iyUZ8Rv&o)1KJ^sihP^k(jW$^np;O`Kq){m|aO#
znx{vM1#LpvE$~#C;3+?d+b$`^$G)|$=Qdo%<6uZAk|sq3d=b*xGf0RUFBap$c2x{B
zRHYUP7cs6&Qz6Oa<dLQ#l*y-xVDzt>YN|}%>UM}I^T-YSD!`;+6s3oZhXu-ZTya&T
zASm__*X1(Md{VK54@G*nn@hdf`_F@q(d#37X)GgB*rZRgZG})G$PIOo8#wDe`m;FO
z{>h6cHd1!;spQ9#EbrW5!GDb^Tsho|xSy_abn181tFR?6C0P+J&D^0ce6RWXgd@jl
zYvd<oh$W)^K^SX^!>uZ)v)`y*K|Eu<Si6_t={U6!nELjy{kvA(Cp=npTHr6(L&Mfy
zII`4M?!MqG{00w?Reg6-kl0PJ(8JMe^`3oiJWd%XF}0zG%rUy$b?(@}xF~!B@z#dS
zb?yk3d>u2Z(?}hSPo#?6KZ0j1X(cZXPrOP|;q~#(vdr$~HwYY>6olApqIbiQWw2~u
z481Y4f3il?9|Rr*jIq_^#6@h!ywEoP?;EhsUHeAX<CXiwMID`{To#++xoLgKp6PJ*
z)Z8<ia8;YFD;-Y768lh#mL=ZZ!IN}#+zZS!rJ5+qS_!!ubY408Y?I|jF84#-!G68U
z$mizE9p3I%nB+gUiO$%B*{|MAXb@x=;UnvoVuQuu0Y_IUi=UfJ%-#C7>azzwehF1J
zkzyg=%se!UyzILUcG2+(EV>yf1RL*E7Qee-&Elx`EAigrmGeuNxbe)L8@E<+hHtcA
zZbKg0_p=@yq_@7Hhq#d5+O{+Zv)dAoQVN<?Bp7b`$vqCP<0c(t(kra3|8T%VCQw}q
z@z5lZi_5UGXQL)%Kdv?0IL9c3@bJj_SZwRLeOQ#dV5)a~c|;8c+8})=#Y%!}Dtxt)
zsC3#*L4v<p2|dL|*{t}>;DR42_sXCATg;z*N3*$#MxRUeR7hTvA7g#A<3B_nNpU<X
z&HY1)_&lHYTY>Yn52l63CUx=MR!|EMicYyo#B%4vzPA1RgR6GUXBOMx>g(sC_$OD=
z@sLu%#n)FnW~<HI`Y3eCXur+Nw7T|%yl5VllvD2vspqO11TqWp+T(;b>fo5YgV)JR
zsomwg@&x)F)<d;?Y%Q#`8)deZAj@i9-me`RGd2>G@X`!C>_a^_RS^R&Q_%*b;<|Ve
zOT|VCYYNp5*y!yRtI!|N|J`}S#RPkA`qq3UZIyw3F89RPgSVO2`e^v`EHdoL5MG<C
z$=oldKaz|MEnMA^Nsc}m;Vh`nfKlj_tMb{lurC`5_dw(wu-I<er6gPW=Z)o|?Ecj=
zi%+Z9S>|=R;V6Mi*7mOmqd%xYz(*Q*m#YU<fvzX4>h^w9#BKpcLRLProcsy2LK*fc
z)zk&`1tl!0IIuJ(i&NV67KJ&4He4IW8ww48_;A#Ku?tmEfry+0@46{?lo&R#!!15n
zp{N7P*|9qat_#w64XI<#i~^x7c{wIbqF_ZZ;<rgpl;fukNR{K0Fl4E^5yTFur|(uk
zkYae`*&Ss-t^=FPsI5?810YZw>h<K}*9QVfrSkhADapx+HTD7mwyBjdLYm9!0pH`N
z5wKs92Wc~8*g;D%DH{z>*iYb%qHMz6IpDDmN`=VHr2vX2zd4<7Mj^gTRy@%mS(S<+
zqg1ksi4mnk*JWCP?ZsD~9bj6c`sCq6O+IAfttyWiF&1cK0?EU4*7PxVz}3(4mRO_V
zuzf0De1UPArNNV_9I!vGvNQa?;g`4!D_q+Psek?87N`4=8QhJbHv}s1wTEkLaXsPP
zy=W?k3xA)K)^O3HgI}*(sW@Q!%bF*!BqE=a69Ha5o<iF2O>^=7(>}mGL0~wtD`Hv8
zyCzr4w8$Bn%x-7dvk$qN(0G{3x$8t7C0bkYj{k=1Zqv}?o__(S=BJ0CidK{(D2}ET
zqPF--f^!Pb%Q=$z)N}1D(qdK)gmjWxo*hv(AXL{fG{B8o9DwtkBnK)dV*oFkT;O$e
z`~trSnOub2tiYCH!SwO+oj9&9avVa)6!k*eq!}0y8@lx-#Ee_varVW?o}zb!MVm`P
zazE)oI2z!$>Rg-`kZSk@xpY>kUI;0L@N<M~#1LAEEeB#FcyUH$ilO)8iMtwoOq#;*
zsgxPRdvU}<4L*9t%7IKBxi((=`d{J4vo|eujX%7K)z*W$hvqq5sm0YN{_^1BoHnXZ
zN<ks3njxoY*4-%n(Nono93^BeG2TA#$%C24S{5vb7NE=me-dXK6%}8>Cu`5Ik!9fr
z`F$)quHIz;B-UaDEL$I8Ak9!Gsrr`EY&9pdb=oadL>Atwjwto{+)(NlZ|2a<wV}XC
z!gJTr{vS&pe6?q9a#Tv&PVJkSvNbZ^eK0H9$I|7c*W2>Qv*i$lTcsk|=TgePZAOLY
z;zALdVM7h8USR7(sZ1JIg=xX<y7yYT*7*U&7ML_E4o~>y>v^^2!BjPGe+YM3abcKe
z0B^G1v38YBiC@$m&M#e*wJFv)BK9Bz2Qi!<w<9MmDm1+l%~oX;<5xp2L7FTk5E1Ed
zWBQ;#l<gkU`M0Sb$+%BaPF_3W%VeSK2A+ifXSn!v?35fkJ9+c+e^6ApN%+>c9rdd}
zV0pOnNM^SqNy2$c?yW0+ZgutGa{B1a8B3GAw)}Yv<fER>>9-n%4x*h@YvYrUHgjov
zCQQG5arLR8?<z9PR-1qOEBB@hF_B1Xr$RNTk(BC^LUdt~tM(hmjo|VRgveHh&GNEN
zPp!o^!D{P*thBsbZ8hq6o&Kd<ZROimELAoY6B-8=;u2x&iAE7VelrUG(!c^s1gO(I
zuxDaDRhcB(@$*Qdg!&|?Sb<gLmtVJ-zM<!EtJb-TC(?IbUvDqyTYTr?<j3+vo2fk&
z$If+Or<kqg{?p~00K~?LJ5HxG&Opb7wAob4QvVR=aqYXQ<s!>}`$`*Ie&0}V?@J!D
z&tIu8m80;0>HOr~-Y$RA&z{HTdGyvt=@~4^8&_TL_wu;Z!#&vi+vv`rXHo?HVRX9=
zeWb5Dm~LcW&zjmkcdUJFHsZP0pl&TL#?@A$Fk9ziSK0Z^U|L+1X~#D=QGZ+_eChkm
z=0^Q@P^|3RnmXPtgm2Q&NN9F?pEEIey+ZPnQSP8%k}RYh`$(gGt5>i;P-}E^*rIym
zh0;o<?Y?%=vXf}QeS~4K`0|#%aD)c~ad^2uZGnTOqe1;Lx7FG~`(Kvcf$A^3)l_F8
z`^wmiJ9YU|2;WTd?2j(a3J%B(ONKJrBU$Rf8311CqyC8MVOP){s0~tkhb2(URk>><
zFxw>II#d3~<Pb;L=Au{aGfs^ww9HSlV@!i1xRCY?ZAw_Jv3)EyhN5Uta&=n2YcTE#
zL9-M(`gd_=lKnBoYr#sJCh5ORKrp9Dj4(=U(n=7YeXD^eVI6gs5Q{h92G1`IG?8l7
znjV*y0$xx(Pd=%Kc9Q_WQe|C=f;$3RaCVGW<aAGp_J#HY2YJ<a%{;7hRA=n|4UTKM
zT~wY3(%VW>Jmn8?k66>I$mKGLFPb)6Os-1gGG>6gP#u_))p(xLqWBFL>bT7n<?F?|
zR-Im6JJR6$Q#3sQQm=6UV_}K{HMDR9O%2-UiyJW%4mqylnB-E0<G3j%6z(&J*-Aoc
z$>Ha?**m4#O4bM=Pf672s?M0gl9xR=fqRxGcO(=ecXI;A4_DCjRGRU=PT`9AzF8+d
zX*+wf79)_PVP478j9wNcyjr#6m!gUYXRE6YGO|@(?tD0<G_4h@S%pw154uXX<#H?6
zS~+4_2|*R;D7h{*8e1er2qeT_v=f63e@MG^)5U=TCp_ygzGJq!NReoG%_8aUbR{p6
zEieUjABh3($cQKE8HKnOpOsS#bzA`+^!;68KBFHKCY!|T)WOx-eOK9c^VB}ItxYhw
zDKsbm6La89SIiuad_P&`>O_$U#JP$tDcAK?o()O1rtBQ{vpdI^#?(gICfO8-1y!*H
z_M#?e27;5>8Y{#Jx2_az`2a$6R9hveE~zCB%xcAgoT57xX73~8=Td9gNg^tVeI&Lp
zX4=2x^ZQh-%J6s+Zs9TrV(#6L^pa^8=J)r-?c&MfJ2b-dua_))_7}<oIvraZ$A3K{
zJwW%^c{KqYOS@j^wggxqHP4}~0>?!7nYicn@nNf*Kup=qi96r?nD0$b;#S<XA;uZ6
z2n@+8l|__whvGFp6Z~;`QF@UTj7p0!J3KU4-a=+;T&KWn%?{Y7V}0q}*5LOu{{Bf4
z*LaMu6EA(#zjqb#%`Eo^#uiDKr;ak;J{CAEg!=wd&RYtXITEb6di|A}DNGKf&tJSU
zWZr4DRg)!X=)aIKm@}aQe!0AsZka8PzZD_9p1QDTUV%a2KqyXpmk(FGP}rB-%~&Zv
z^zD^Y28@?UgFTS45(jtK1My8j(bR!M#lG(=7Np#j&YS3@9-@BFC69R}4*=)R4IK^-
ze^0p&!<X3Y<^N#G)$51s%p=E=S9Difk#0n?X#;eWt);e?z_x0ob%rs@Ti>x%-!~<x
zo!!h~woYSthetYE_`{+D{8{*Z@`#OKwsLOpUEIBE`$DlFD{(qx9L{{HEuocwZ0(OW
zF5>HS@8enZKYk!PRIdXsuU`+fiL{vhB5WnUWW~9wZOKFXlI9hDFPynp^+m_hK&~id
zjKSNhhws3CL_H-bglzwbzW(L3a2lCWLWrxac;W)`=;_?WI)3J_4%pD^56;8~$Egl)
zHPo4eIuI6qy~pr&Woe~oWDUx$_T}V3Q?Zb>`B#^N%GLR#9G`=du}L^<|G||$6WSmM
zzsoIDZ8+vMrMD;3<kBW#`}l~n`AO$~Z}`@#SXy+7O8tz&U`VA4@h#wJQ2*D)QrgIU
z<g62JDcs>#aFFta!%Lm?`rx%mxTQ}t$NORsTS^!EYNno_ic`0OB0_0DDiC4MbMBQC
zGFzv0u&E>nb$5r~MSB)cHq9No@J+__>nh<79cgsLg7DJSep9A0x{n)vO)`|=x#%|t
ze(fst4Crgp#cSz2jXGwN{LY@J-Mrz*{b}Z+oh_6FCOpw*cx|B0iY1$V3+n(E#n~-V
zI}N(gW5O#(OL{~E_0c(xEFb={wRy2BaU`34B{f%EkE-4X$_tHTrqKC#N`XqOE&0DQ
zm~Qcuj#)M|1uNk@qT+PJAmd`0Yreb?(S<4Tx4@W@dS}>YVV>ev%4DLjTjzu8Vh{F|
zRV2Kj!N?_s?;=JsfKm}W=vkj9d#Tn+II|m+Gqb#n<yk={YKHTXItJQ6kVA1?`9~p+
zFc2CW=BUn%0%Q-M6PwgaLCz<Ey^OY}UPQUK!%#+CsNy|E8)o5m2L5;87oo(K-3K*M
zslb&_2kPN$ph8(~Eu2RLB2tx%K@tkrs<8KXaZZRWIa?uYjVQz1Bij=~(=yfT{Pv`6
zG5$t4#%wL3Y<WxC2av>AlZpN)j(pj)O>hbFmp}(r+;f!slv&iaR7G8TEW!v$3U-)m
z_^?1Ui4oGD=HkjaucH1A7g2LKUhSw_neI>KRV06ipBLH^zw$8~jQ|@Vmj5)QDc|Px
z!P<mujQZgJ8Y<P%9^qN%#5pb6>%&eTvb#YV04kRKU{DWGw@XBesKo2k!zw{@Z`TkA
zP-eZ5TZ<cj4B!z!P<h6=%=2nNP+$<Orbc!eBH~auBi`7Gnc}7|4z<3VlIH`=+(I#I
z!i#O1e7v^2K(P=ZYpGwan?Rj5gEvlfVOn~u@JIzL@`J9y^5FY*734^(;h{w!@T<V<
zN}-PUu!u)x_J__T5GZVvZ%z0%d3gaLQeA+n#WKNpM?wPz_2I>i$CEL-a5jW+Q<UMA
zMK3)dGwKyngFwZqCdRy~6SZhg4j?bJTsRUk5&%kzVnp3gY$P9uG*qs<pb(sbo5A1`
zdp<0}@S~Qpmx2QYmX?)Eg-r4D{A|RviQ%QPo|t81QzJkDV<ES;{cxR0CNDhP=!3+k
z*Ycpy(p}?{^4UU`k}lWX;mb4uO7LvGh??kCVn^&zHFgRP!tOMBQaW(b0F^Z-bOgj9
zgp>z`GQruJ614a1I1K8KA}Cj;iJ0yrF-DolRvxNBbU)}&tP0IQT2sNLnFHgiDp*O~
zVp-9l7!PKWQpKn61UkMH>qB`%a#2V|PunR+cmVv6jUKm=6P>hWDOxX{v7<p*81`kS
zxvjhc$3kN@+3zjC+fv_2D2WxeeBE*%njK4DN4|EF2Mr^$lV+~da49^@9zA76Ctx+D
zH`z7QYw(=x^9cn;-XYu%eu^XYN$+T<lwNd@lv_c{iU3c8U<0MwtWci7MHfd2n;<9@
z3lVC!VJXJ(+Y6M%%I#9GijBE9CG?@^`=srVgl!{kgOYl=-6jU@b_=SqSk0D?A)MW1
zk0>>j8h!U`xhB&kw*z7>8(qpu)w=frLdzKm1qsY8q|DAdE-)|Ny?iKQLD%wz28lr)
zL8mx@ZYf{k#)tt<?09(^g%U3oTQUx1sVw+1rF4@7t=5~q>Vyz#pP1egi02?oc`C0w
zPEL~Q!2(31K-^F$rIxtTDM>2I^NY|^72Z{GkrySzVRj5vDFZJmt_QsQdQf?WX^``(
zf|{8gysh2_hymf$t&YJ-J4lv-fsY;*X-0w`7J=sp2~3M|tdyn9txsFqQNR)B%7;)w
zVIy9d_FAmdb5zB8OWJY9v0^+}7OsiK8s!18Sgy!cQg>XV!lk>Q(9f2b_;v?BP1+bw
zZYLbks#e}%;E*j-cX8mBWO|GObNrmc5h~)9MWlENLY^znX97yDcCwihW~_W71HYJ2
z*S;XmMEEEp#vn`;2RMEr--Tw^w?|J$*$>3ALwHVkDCV(kc^!|nc;cc`U?z9UMojP>
zL=|g$g6k@w+hHek2#4(nmqp2izd22l?rpE;I0#Ng1VoT+(gln&C}gGnNO07ZVg300
zP>s{EmGXok=|4zh>HUPpnxZDLJwIy(veP<r9Kd08G6`x#SK@aJA{*iFPD0s(v(9Wu
zsB|UYW^i>dPHhp0{Y*##qrdMAS{v2S*`9N!eInQ(wV+aL7r5=wXS`{;aXWjwqNn)n
zq^EJDO&p04JayzsZ*+4RD-q^#nMDqX!=s;he$y#;_dT34fgwAtNPCJt(81YI4DH3)
zu5RVh)Ls`@py>Jsdp^w#um<02?<q;MO2g(tudj2|(!l%!mc+R*UIAm&c1KA3olRAa
zx6a=p%6hl&7+fGb^(v$_O+t4eL|^+SJrny|8;XvHjIc>i`vP$b<3(&=W%{n}YRc!%
zq6lnz$!vW#VmcM{+SH6)jCpuddLqX9uiw(6(r;y!Xse=q+MThrBR)HIFdg-LV>{87
zKK38lP<sg*kNvo2Gb}N2h|ibrMY6jXX72&&%JSQA{p0)T)`?clXhyoep|)Z6Mg#@2
zH>S?<HH?R^IuPl1caQaM63gSpuC=S!Bz7egq4&mC{>H{V`ICJ|=(;ZW&?c}a2#dVu
zsIpila&^6Gq#Bg{{jW>46oe`Xlnn>ZTi@qm{}_H8DPvyYewOc8<=$HI4}v0p=OXJA
z4+jn@^?7}C$%mn}@}rjeKc+i9`&O!jhwI#dQ$Zg`WU2$ItKS~VezEfbX)3ZD>`$)8
z+<&*V^p07%Bk(-)Cue@aW!WhX_Wwy+eq?+k&yK#k7OpRE<s-y{6UVu#!5W-Aiw8p-
zQr^DS@Y2aZ&~Yb`b5-RkjX^N{PBYInW#K8QTS<^6U)N5G8&#umCF2vH&VwUX%M?Cl
z61Ba+7rsmz`~VL!6&oMnaH|TO6NP%cD~OG51=edJ{`rQi^Vojpd2KEUm;A(D%CzNl
zZjDjVI-}i43n_u{OT#R4zLM&?kJ6IkSzy~^n2i;9E^)TV&8!y90Xlx>O~+>K_!@(~
zmz!2x^z5v65E%K3>z&IV3^TXCz`eQu)7kXnblKsiefBGl-n6G$utt;i()uGRRrpn}
zgs*(am3^dw>vHx2=V~N2++}N#2}c*jokO^#30DCLv3mVqPkgTI?TJ}vPx-Q8b*Kw6
zaWqxL9_Zxu6!)S%UJS*}e7*SR7<5zYHqZ`nugWz0VsG1No4NMyyGP5Un7*5nkK}>0
z)BL&&<NuF=Z3K|)%%?mGy#;N1^vpLb@YwOzAw>$&8+AFKGWzJ^H^$8#TJ&#iAB##^
zwP*J)HSHbXK7B0@1STr{BzpN6r(=a{O9fHP061umrXB`%hO!n&+bg*^92YIGtU<mW
zz#J&SY23>IGNf*lB?@p4+v}JhRWXhR5ZeR(G~MHN$0z`~eVvoc5q6WTPTzC|Ic<xB
zuqk@yfG3(8A-E|Rb`A4A<GjKXDP}U2pFJU?3c&IKPFiffhctk8QWG%3ugJW-<XbXp
zh3HLeHO96Xb3tl)t9TJ<2geZ?c8D*dsuWbeH>jA5D-jN^1tD=|b+!n^=FuhB3?Yq&
zn}8Zfjon4c1`mO^idq@m-3_b(%~?wb+okrCBus3JKYU}|H)Ua?7>)wXWsePgICd|h
zxI2*Tc+lb*O*Dwt$i0N_l-6h53);=^qi@<KrxxMnZgog4#?c&aF;32O@g=?VDjdBa
zk7pUFhEtvgZib)YTXOgf246Opl!A5!uV}Ag_5?I2oiU$<#OhkL=djbG#Jv=JEV1D;
zn(PcJvEkuvWlJ+J_9E}eKV4yoSl~Za%sv~*r_luwCDerkOm#7<t-VgywjARVn&^1S
zCyqd0$XDm<^fsQNQ-wx@=C-x*(8P(&t>Q!<ddw4|9TB;sIdD96mOPUL?J+gI_IaJ~
zJo9TT8_eq!=Anu2jusSWrI^hc49B_!YY&jPuAy9FyNyh09p2M^qYgIWclTj(IRq;f
zm4ly8ZG~S6n;RRI?GE=)n$waxcQ->x@@>ZLLEGkS^~R7pYEIV*eC^qEEn}-%EmLBY
zo`gd^xi@9%3EWxx)n*+(F&>#_fD^CSnC^3dl!98(#aT(W@Kr@;t7$b{Cs{WGRQR(r
zD!nDLNgSB8NdcPAmDfGFt`{p*yp?UN)GcRRRDASe?%;1VeRJ`j!`Po5JS1toa9(0W
z)&pKL#=GXI`|joIupd#w@XQ<R{^3xf-J3i6^GABJ4Dz<FaWaahYP{*%^SOgX8oudL
zovE@=N5-qaA&SOO_R7-oiLncx=bR<aIg^9MrHURP&-BIAgobzPAySapI@1o%AI5B@
zl8NlBQPOD=mmJQ$=ImSP^Kna0cw>^=ov)raYX5?iug~D{m8$S*dYYG6D8_6(^Td1T
zZT{Fa6Unsb&rEpX3<7Dsl`o~^J%~Q~<?3-C2QlG=gK<M(OzG$76()btPtR~#C_?eC
z0*<c_NxIlfT2b>PD5bOZ70^HaK0^QP7$3fQR|p=zb|kvv=R=uE5rd$5bIO?$rl<p|
zwazN%qF(g0VTRBlDM3RM&(Hq#E1Xb#Sk*`Qh;T8MH=B-j+RNg505C#&XOJzLVYWIi
z(+co1TYvCQXS0~C_N%PI*^faieu+}=f23Dte)?Mui|)<V`NaEX+c&(J1c!m-t~fPg
zGoo<I8?h5!X7&HBUvSoZ)@CqU*;7v6&T8Flm2|}H4ijSk<X0F&>wc0VYM77*5?*sA
zacf|m((me(s2ziE_;PN`rP*3s_upL-6R;oSY<LhB(iiRacr;Q=v-RMEmN-(TWyosV
zqs~U%3xv6o`}5=vUy;VP7s@Oi(YzSH9e$=Ini7h-0#`o%kIP0^o2@>gbY7W-Q8ybL
zxC3Bi8Cz6eJPB#dF!c3p691?g(gPe{_;FfMG|8K%L*D9?6=*NMFZHt+)OW$z+zo-z
z5qHBAP%DdV9P@VD&t%qmp4|oy|F8Dq<u|0hbNE2^x~FcQFgo^u5SNH_0&Hx_y-ifr
zyaDSQ-hsaO5y!=MIm_3eEBFi}2tlhE;<a`%`)BEL(ox+Bwf%}%=)4Tsw)W^H6uYO2
zU4C}9u)8kxHR1XiWN+(Cl^tO9=c~xMaz3sUKI~(hF>j-Oha8)tTIui+Y|*9kG<QSI
zurU7PvL1`P4R{ArxW%dqQMNPpGHPs@%aOL-xsup(;KJEx;wG@T6Ph_U7cg&p!N~dF
z<ca!4gr7T*q<+$F-T$W-`{c~^5oM4Qr1uc}{eGyrVfPFR6{c^OT>wG9vP*8Bsgp`-
z$%%C;j})An)39kq;k`ggvBjo_EYSex<3+yOqiaETk@ZHDe(^BPFfMFQ+7bhSDf9e6
zSGjuWGYaw(#30+)sw;=E(|TH`6;n3h%Ya_5=}>`ONU9kk9~yX-swTC3;#asT<5QHe
z-J}ri7U)#rvZZcGEQ8sm%Z@19B6$I_;UsIM8{&LnT<VCO!v?yuj>sR@O5FH-$EM1{
zZXhESzJsy3k#&nN6f?B<P-~4;)DDaWS&$+6U3BFLt^00X7Rp+QsYmV5!dWZ76%iwL
zb$nR~dDF*6iKIThOHaQPC_S39WX?iCO#VDRPX+QJiV1Z<;n9+Ckct+y5ZQt$uLr*%
z2{`#EZSp6;%@ifzjhsrCWq3EYl&D9n647nJziyv*+mN>4l)+MAu#&i32VyiUtRu=U
z`*AZMVA(%|O4^+7CU@}Z?2Nq?+q79`HMD4tZlDDOFPHM2t~f#02n)5RyoOD|gj&)~
zG6+)Y1G*U^EK%r+B%k0{oe7kXp#4NiX_KBLWriP+Qo9v5uxzTc1v&TOjol4q>pWpG
z&*^JCL+~c4Yy~`y-=3lT(rXtT4flfguo0!`jUC{3;@@wfG|{EfR`wp{`5{oV<vM1n
zrrym^NA$VIW5$9IJinyUo%~UGHEo4A0hnFz{s~6Q?seUW0UqV$c1*^(hKTE}&GmUr
zdQ;+JsR4Y2d_vdHoE%^Q@6!9Z4d{qpSK^illELvprj0vp+!*JZmM%qKKPPk(%bhlL
zFczyo9?da4ht4xJ-8(SJZ(|QL4Emm!M+2WC`~qVC^Q8_kK?MYUW}Tm<o75Zn{+`TX
zl*LGI$Jh$6j!<z$GRF0HrcWIl&+QMWy|p2)m-3<-&Y5#zA2-5lcgjt%rJy=ms|#T!
zKK~Yb=SaGVn>>fvpmO@q0;8p1=igzA41uUSR;^^VE}ylLZw((ViYGFv>w2sz)|S)h
zM$zb8IljQcY-cEP#$ka8TS$si*Tcj6+GPRZ>sXfSR51p1$p@wqCu$Tn`(O{NC2~J^
zQ!6PEJr~x|=mYRPw|G$Bp%?%Z89-Uc9?I?1e`Ay6RR>~!c=&=Zm*_6}3ao;`(~h}9
ze$j3^dj&T8#}9gY{4JJx#mYb`F3fl=gHrQE?hX{&nK@wjMNdy;lk10qR`ryv_)_qX
zbQoQ-$eTDKVyr6ME6`o6dlgJdTTZdJ+?Hqgyz8xLMQ;ah_EFhj3y<$llfPuanD0Es
zdi`Cx(jUBqe)L--mj2&`lL5!L=becxT-L*HX8Y3xG}V!{{6>wAhjYhj>s0=2P*l)o
zFF%^={LU9w_i?o5dfJ%&$&AAQPV>>hZ$$(l?GBz9K}p%MH<f2J^wylC-A$t%2%?9_
z_psU;Qk#UNKeYdi-tPJGNNKN;yIyS_d-&!gnyrgOM#br)jjDymJ2RJt_!^-jW#tj3
z1nzimlFp!qc;5+sH=tNsZ~wh4#Kr(t;HO;r&GGZPi4O4#{9>_A9*T`9{xQrSp-B3b
zf5#_su^$!g4<`%G)cN}icGr`31})Y{85vW^W4D_9#&|(1`CzbH4$Q~V&%eZMwaIgd
zrGG~Ieg4}sK`pxY%WpGg{`QzHz1+-oW^LO+VFDw#IQm?E=suaP=~2GYeM6cC9@0~v
z{LCJ{UNFVyhhj5*8xo@59aX6KJuiDkTswbJ;lsPw_O})@`>HE1#wTBsN?*Q2!^P&K
zRndm+lm8M9U?W2D3irw4pX5%aU0HsWu-k=$rcvmIb?Pd_SUbIqb%Q|s@S=j@_xwhz
zJ^oPwI)h~p_#(^JUhO{AU2T<}E%+3_u;9a4Yq)Z=C=rLx+{^au2kd$KGF8>N(#GQg
z_WHiy!*4N^d?*QbQ><#ka*SX|Fmduld5V<PRv!21=&)}e)Vt{eq2_*P$p>cN9f56(
zy)?@Jv;RXpX(EJian8Rl!{%a*E0FPH;O7sy@-9-`Kyb1CKOj8iufW%yZC8-A-84eX
z;4747ytb>*?w19YdF&ZV<t_v(N~q_GnX{DcHQ+-9V>)O{Fr8hESiby<g42C%olAIN
zvAK2y|A?QinlRQhXJs?I#>SH^foAwQJiM0YswD%3{{H~<JP3S+(6Tw+v4N4J@%gFP
zAj#v&2)YXLA)Hwx52R`=nY230uLz3QTbe$Wpp#5VgTR9@8f><OdY{4{_-z8IrmU=<
zXujLmm1r@>JKQv}Hd|(#J=}x3vv<r|2^^*vAt2-dhp-@CGCYeCK^}9@@xvE9fe(ko
z=?fJuZy_O?!e{9WDG@ZgnP_4^VJOvE;K8;){Iw#$YwNU=L6Di-6{VZvh0+Xk1$%|*
z3b84D0v)ZkR@vJ@F$y^TQ*|;NW1Qrp!6Rg)66^(!KQ>cj91PRc+I^}yzXdlV(kU*;
zsUgQR!VyX_9N<r|8eQta;mIm?tGFF6Wrk%$m{NMDi<AX<RZS|v^D}Ejw|tq<o#);b
zx3k|3W7xZy>VEQmTPZb1AF_Bm-SsuiFytm<Jr-aGpOLaq5$bmdUa2~nX+w-s*v%CV
zt%xb?-9cpoLA1u~coIX=Dd(1A!bT*%>%it;l^cTYC?6F;PSJ96I2Akic7v+eZgRWp
zV+R8M&W3DN%5=Pj(pGmHIu|n?&r5#kmdUUx-=<5oZS_?|s+*le<uy1w1)pxD)4~%Q
zw`vh^(cz_(Ai2ajtF7K6eyJ^Kf{;y;?1VDQF{fNYd}5#ChS(+ysaqfkzK+RiPt@Zk
zO`T&b+~JhWF2-&imB_Hg*-ehds@Vm-ByX8L1-GFxRkAgWNd*t2Y2MjCYsFu9M0-y<
zj}>T1N5{z=D?A8oRt9ok%Bu{!Kv`_$FKAJ<3+E83)r^w>dCDf?O10t$m3BV0TB>$A
z7G|EvVBr(!^$2ep4HDO>uY7<!aeQ-(+i{&I4+Sn<%Om?(Hd8!3QeZVRDbX2qoCL^-
zX(|t7pviw_-$y1{AkM7ertMBfdZ#!5#9kPgQ?g;UrbEp};X0W5dM>a@7_N>voB3z9
zCXBw|G|{Eo`V6D&4NM<z5nPSIaK1znK5@X|9So0GTVGr5zg$gM@@9R5EC1e?T_P*(
zkEBj578P*n%1y!zTYT%4sXg=AgPaG66&MX!ER|Rpi>y}Jz-onPT=^1p$BCbHLxA!0
zaVW&6o4(EwNvSG5zw}LfzDQCBZ9gS%aPkj*m-iq1hVzQ)3xTD+cwh~ytu93b4s%^l
zjz9Piz4GrT+3eFlYq$Q+JN@^J$3?rBDRw_|3#c^Qvz7-w=@D%C2}`D5<Y4bVx&E-b
z?%lRLD+-^zeBKqyxnJ&F>YmHoM4Q#tJY0P+NwvJY7k$Kg(?3mF{8x4BMB1WTn|5<+
zw8OoC7t&k#8iow+MXFMe|H<%@=X$5g(7n3IFYbFjwJ;N=;4>HM;-jyd^;1fs*y6x@
z88h-tMCBO>v+&0r@=^j(&!{1_8!=usPWTB*pt=IzPYL0VSSpQm95)FcDQxu@Ng5^n
zHy%nHsQn>KE@v2;+EiZTV)(jKF+=zq1KIbVv82V*b&5|yQtV{b1hu%IEnCx#pMtXo
z?Q?3sx3j2z!`)x?_R$9q<~HiwAqS1=zc^ULv9N!dd!5x*_xK%9`Kx!N6Hr;|&sNDp
zG+R$BG={q^c~h=VRh!xRrs$mm9qLDr&wV0I`Gkgzu9Yzhmztvk^f48u@*LzT{MYG(
zVvD$Kc&&OoX+?5!^`}Q#GFwq|e^9ZJzfd-!h)sRz8;xZ`jDa74DpH-Nv#H;yXlu1~
z?rn5QD32|h?oPYi{calZ`Z&D${5A~Dkg6kw;eGx$hcwhnew;0D`H`I3<T)7imJE4)
z?{SeBzW2x;2P|Bjjg51Ep^a&?_FK}_e5?e{Xx;C|it`BmH2n#yt+&nmN<KC6r-_?~
z3K<5#6?OW_UAwwaqwL}8DjX(5ti#mKl$i@Lu2Uyf7?MG?D;5``pN<)s%FSxzlloh;
zlhlpJ-yd9=9I657R^%D9sCg#-flW%8L31*}bXj#c5jw1i`(LR;yIv2ARFOhGL7Xut
zyQ+-R;vp5%6+|>|q1@${GHRgHa^z(O2?O;loYe?>v0H%*vk#!eC%$i@CbJ-?DcodE
zZeK`6q5_Gw4KVFiW8`SqF@0Nx7;#eC<2FA-s2!OoLcl*6Q{_m*EqR*0I{Zj6`i&|U
zxonY)3iOPCV#>}ATR6k^6vs;~Xio_l<N^hF1q2CulQH*!EZ_k2CwBfY=;vW2D5ft=
zm#OvafNv*l=c5n>7I)sn&*RrFQ5hT#ha32D1LsdJ6ZhC?pmHlsReeaYGD{2({7kyg
z*5~0{Tb3;lsTZn5gSHZxj^14zDa}J-f$n1qC^xa;Z0xu~a9h%M57zeb5IU9S#10L!
z1l2WcS3s)Qmc2Nc664hC3%R2QUo)ib7(2*mhM3C>?+Cwcaf*nW%ehYJwNr^z=!Du$
zD6l+4$<C7+p;cXXzpRuk)0Y^0W3@sZ4*H-7c5xMs9pMzcg?8`cXU#4Pe?XE$we4v<
zfvF@l-WmK6yz*Xx_vaKGx79YoPF01bbDUq4X8=gQo=kl~6kXm<`y!QzEnRx)iSceF
zDsdA`m7#oAS4N3FfQ_!^px>TgURYj^irbPc(^{rEe&hUr>2hdR25_a?ZMnLsJ9^S0
zD84S~h6>3sD)*H?#A^(3JTzxxdi5GeM!b)GFdho#nb~m_8Zl-ex)ra{UplY}`XHF-
zhrs67xJk_Z{QIr=+@-!BZkeV&JzSbJ?Iy~8e0Z5Lh>I!bY_jxl8)c7k#v4z5nXPPf
zX%yD^zG*@%T_s$OcCNy`m&$qR5Qnh*3j%{cg3i4?)V1kre8ndihx6n2-C4%@dmQ%T
zIJ=8}nCS+l-fPJ0-Byfz(tH_ly8gsgoxa1>jjyoU>SD_10wW}yv#PEp+>->E<aqsT
z*cT#(rSF5kc5~eOkI{{u<6*r158aG?n#%nn`i}L3UiCXKA>cZ7T5NWBi&({LWwX21
zo}96y#1Y=k;Kpk?Hqw3VWhG8KTGMd+yk(&kx2)7@yIy^1KbFJ(5MNjY7yHq#C=U!3
z*aH|aR2Sxl)B0nv@AV|flF|sHGFub2quP^a7n_c_!O(euwem<EwZ`T_9^FSvn61UH
zJY+ODMn#`Jn8>!s*VY?$vNnevCnZ^)%FO*ToblhxA4J20ln4DHe;J0!Zg2SqoT_?(
zycF_v))ZNY%)COs^Uf@esQj0|ZNshKJs5uAuW#lEtuKYJ`nO2TYHNPuuN}(&(VrY(
zDHZ&A@t+n2TaF9=K_Z^Yrl*2VSWTgx=eH9jynet<5;qZeAt6aX5z()(<HxrdecY|<
z2@D2E#C2k>vD1rnOtv`7pzKkTU*b+yKzeiXP@_|UtAFGTX00!cN8Q>LCxgwbsre5A
zifetDqkDhv-R4!5K^ag2r-tVGUPlH(w3g3){$Ms1i)BXSh6F@C|2#jN9b2&TKga^H
zvdbFfVb>qpNf?nW>bMD2S}rMp^Q|F!Uhig4uP3fEeytbHxW_Da=|>}DSv?Wcy7ibX
z9RJUSJ@=7=KELF+ExH#IO-6Y)`Xe^$*Y;D#<Szawv8DBoF#uc}w<ZyN!I7Hr(^Z^p
zZwJrnT!CXs-UE1%pnDOBti|22x>gj*-MZWMpLEK)3rS}b-1`%?ONLB;%Vj+_HwAYG
z6&s#<n7SRB?QO_j#$oxr4l;w}ZJrJ&!s$|8sjLKdy-jsAc8kD$G!VuDh4p-IGq0q~
z{=vcF6iGbGuzqazK*^HIJzf@S;f1*TjBJ_znPMos$7XHeXNyDaha3am#$w_upA4U}
zU>D|t6q)c!s~=$|P#qA041jvX+6QfnX6~Y8&<AOUB#FT<>a89U28C2+uksb5pDIZ(
z&B~k0b+U#~i7!+7yMa2Rf7py$h0-`OuJUJxN>7LvHHaEK_gn=IeNWYaU9apc!fffG
zKsA)0L+~6zX~~$|G~Qj3X@>5w8Wwt~#^dG=6xRk(JDhVis<BK%?z<5P;z490xMozF
zua#3p|D7(=?7wI;%~sRi6A@S}=NMRYb54?>rkHcmCe_+}40N3vOIzE*3{kh$sR7&X
z)&u7DR<v$&w6aO&6{#+(>5<GzoLU>e_C4B94><hYk~UH4LE7vsWV)3%&!!AVq10jT
zOj`@4ECu1OU@4{YVkIZ$PQvmk2{R`emJDCc=&A$1ft@YOFp?~SdL#>?gal-C&;^bL
z`~x5#gaWC~SqockuidD+G9k{<2l+?C)#7M(P-9<4fDNP;9kQgg4z={#P0N@C9{{dQ
z_chwKXAg~2#-Y>HL@U+>5x3Ros4df4Q+$}-F%&|qq|9xk@9djc?X*a7<mXa?cvTDY
zw2??Av0EblF))X0GCw;@T+^mkFBT>D@OL!<0QL?O=RN*L8e%&P`1O??QFi`X$E7b!
z^i3@j;p&RA@I4?$ltkQjVPLIfN$4V%p4hYTc@u1qmTgVkg1Zr<W;Vl?lFR-ws!@2G
z?l8ido^W2~getyW*S=79hAhPU$C2u5jEy2!A{p`IyQEa4LQEbhi#M0Vh1&Q+uSguG
zhce${5IM|BbV9YSDl?IK)wx4kvF4&9=Km|)ODlfq0Db(WUFLQtDYh{ab<j{pUyN8-
zd(Q@Pz27%`JfX5mz+}}MM6ZDFILofsPTeSEF1Q1(#O&u%Y!)=he^bQrIv>3k;`hEr
z+9N#1{%sl0-n10kxcXqGKQd|d?%YPM=DF_Qi0)3iKze@&Y6+)(D|z;ws)ejiNbizl
z^p>yb@OJnrmVHa4l109^$9F?!Ws={QtkZKWTyH*nhP1m>nKWUR?YymCIpN|n`OK}U
zwO*Ne5GW~-nYTHDug82bdS@q8`i1It@QO-5rZ-cm)y`gyWTGA()B33F16ilxv$scy
zp<h6uoLpf`B_nu75+u23q+W6v$IG6$$i*9om}q&2<DY0-=kssg&e*mXh(SH|88zbQ
z&XN<~6(y1r_!UFED|+h1tIWwZ7DttB9Pa~LIdLgZf+_Rv1Om^{Bq~b<#6D0A&t)=O
zJO4Y?#{UPktygg3B39T=x6R|vC;mMyda*ybC6C26(<|AgcY)7czU$|5`|8bU^2B=&
zty&}ZtCx8!+h-bK4ztybeU*E5dS4OLQl7AV?WGeJWp>$Zs{{vtW|Sr6obcdGcYDxP
z;Peke>HJSE<!f!0uJ!_@*;*}ohNb^Al8u^F?y8KaY|5qtHJOJm;som09IBW&i-B$@
zq2`Di46&Zx#0G4w_;(k1S#9<FXA~Qk%R8Un$507sr|zapsOz|s5x{KCSAQ^LP}-!9
z-w>G_SS$@G>dE5pt7;6L(+5Jkd6WH9r~LodFb6HjbL;Efue<bZX5YNBJ%-sjb!zqf
zW^a1q%6RcrHxj<OZ<W<ndv@Z*SJ4b|A5R-@!KQ{kBX_UNga8pgdQGW2QQQ^U)Z?S=
zk~7s{tmCcNskY?UOASqg?*Y!C$=D-mmF$zlzRIGSjR2RuIy+79<gbQQFL#!}#`Ss^
zNxL?JtE4`cb<*5xk|AEo@RhZ!gO3D3&J&UR{Jv@u@juVrwb9$_26fj5Tf2-Ur|0*N
z8J+n5OWNB&S9Vl)zWbbeq&}^dyN_hqmQ6#K)Uqwihh;FNF$R}p*%sh|OVSWO0_L{k
zI1ORe>k#lX83QF*ZHvSqGV#nbvnG>^$CGpj!#G)<S)NQLIkuU34$JR7hd3EOUe+wZ
zVt5V#o)!;C4{@CL``0=5O0p&0>&cexIrXt??_Ik-PVK5Xb*4MwDDk!shk3OA4s^^`
zd*{BP<jj9^RXB2~9`SNE4@%7j+nIBdDM=O<I1b#uio*On58UtWwS9Jc!qTISrs+*b
z|Ld4SU!doT;Ip8+x4sI&TPuLOD-_nU$0>~YU9sxOCM`1V0ixZ<4BaPL1d>l>>-cR3
znIKyrL?3}JW=T!0ABbmW>_uAv>?P`nC%KC$MQ0+q7==l&pkXg9vkK#SqsB{Zc?WEc
z7#CXd><Zqwj*bI}o}Wa0fW0qNXv<q-+pWT69Rnd0EL5??4z?FMk6+}CUlU;`xw#?7
zUQ=p<^Psqyx}AklM9m={=)R{!ba$9k>APKUkZhG`c9Vx_wd{f#qXM#NRW-gRhAeg%
zZ}42Y;A_|8%5|*qGwgC!;BwT%pv5{}VQn4yRAJj**>OA5iq)pFm>pPw-vGY|Ue}i(
z*n}K|=5Tf(?3LGxJ!c(8U|OITp!mmCet?VD>XNGr0=;@2HYKtW27Z(bkZUE`2NsAQ
zX|X0cp&-~+oGTP<qp*y>zz;Pw+~g5roMfJz;?e`a3r;vKU3P;$>aUX5VpWu?QfYa7
z8Wu*7^nu?ubdOoaOsKL%h*l&kD9P93>@ujdQU~sM<AFFngIy;jY=XR5d!&!}ebo>H
z8qRfM@CQb0)BreDn;csar`P2ky^Shp>5`7tf>KBHO{y$<>3F+i5;s3a-Y|+n`*BcG
z%vQBWJ0(oou-sKONl}pJr=;#kRGkybIj|b8nt*V30k=!smZ%mPf3dJ_TN9nInUXwi
zb3k-c&<An&7ewqB5K?pPt;L!bo6_g8C#jQ%&19T>sj;@>6&!0|AK6uF68Obea&5`E
z0o{t~t1#wO$Yn8SGSVse2)@3@Y8~r=BjgmnR2!%#aa_jZ>lnl)+m$Z*kc(7Z?zne?
zbtYB)jN2)CbGR>Bm(au21s8Y6DtbNW8kxmftQ_bU_#y4h%0&mteN}My>K;amuj(rs
zekKmmZb_nQM2Q|?DRJIy<j>Di2%Qnm@f#{73AK1wrr^hlAhT5?s+{d>f4roqU4fHe
z<11C4AI)!Uy_J$!kLay(IGF!VI!EnbwbdtH!HfRro(1}XWO0pCR9V1SO^zNwQ-9zx
zTf2^D`9+gje)ciD{=7N9M3$vV%+&`Wom|H;BIJo7VPBwChV8*CIOSKI&207cRi~n`
z-N3KTRLh=r3208cV}bZ8r|x7()x)VwWwr)SsE;QJt3Xr+Z(Y07oY;=97ioFyAK>Z@
zK9s-8fy|%CyaO3g=~iw0E2nL46@NTzuKgq$;U!bXm}YC`p3KL*;aUCL>!aDKZ<t5P
z_;@`Oh}j*2vz&92{1c4MUjJ2Rqi03h29)XHvsvclyX!qjLf*3cW5E{C=g9ZYV>K1j
zM?doGxzoDdBsO0Aung*7@U&(Oga3A(W#_K#wRqU@1%HzyQ<f~<`?cY0eE5#!1w%}+
z*#ZGI=XVr53CK^K%UE56<#f502gt#XFZyVWDxep1R$B|%=9<G0$e{CbL>`Ke2j+2y
zt&G&1qq2MqInhk+%A^^sNUnYVawX{vVmp1q`>8qL27aE_8rL*q);Rd+$hV33z;D%T
z!Pqcc+t+h?$xLeZy_Usv%+@x_ZX0FM6SSy0{n;Ce#y>p5D3x5oo{C*DxtQeIJsg7Q
zjQz*F`QX#^zJwH@mj3LyW?#Q1+p9|7PL6Vt@DV>Y!DquQSqKNC&emkMj*lcou<R74
zv_5p(uOU`HlA+wT6JH_6>LyPIo_R@b;Y!oX^L;{%xEd$&*7(-B(sfo_BaN#!DCxC(
zKR(0$2$`)>+~lttxy;r^G&)!M$%5#?*13PMQ3pJAsB5+cw)NY`sORN5UEWR1R$t+t
zAuu>+YoFy<vB!UvqM_+@t9LiW3mn6;Z_U5U=EtUOEL6Fi*4$_pin5^^287F!%${1b
zv}}aAi2B@=rB7b!3p7<y+LXh~JmiqcsUW1Yb*dMTxpqF2+fk-bP-h>KDUl7u>rNMX
zh*;d4gxv|XvMs9OiSi*TxI>kkRVsR|t(9kRs8gHNe1QSS1-IwciITGiklWP?MRbr>
z*^eX(Td`PxjH^qbgeos|))mYW>m#bMjz&6$-wSozZnsEOC6bXtl?F-M1g0|^sVcHO
zhU+k_S|<gB)Y5tK7b5CFl(v{3z<xOcrEu7SN?K2<h*D6XLUlgk_qvF~ZgBlPI`9d#
zvKMAWC1Y1lhh92Pet}@#Y7OA)=(2;Qd!)S-Lk1b<pdEpq8xB5FsQf!$!!U;4t(}T2
z4*UXUUQEp;Si@^kB;Al>6E!6uhXRfi^wH7tGHrLlFcy(9CKip%ak(gNN9r1Cxxyk$
zHU`V7XvQQOM&-ffAEY+@T*J|hExECbMeC!4$s|c6yt|Q?UUVlo%}QLKb6k3Xq}c+I
zDtd^j72!vbAdg+?7Q7uiB>#+}$Z{B~ROLIUn$U3a$kGVhLxBCrIIi(ptCco1{x4}_
z5ndo+75u{M%=3b7?f8kv;pAe`IfXXR(nd8c6_icsYDg9#i}|lT+upJy5YCZIUPW0+
zsnp5|K~+JIo93J<7%@<F>{fV$Upi<bu8z?{owJs<TUB(biTU9)*zAn#t;C6Lk{%-?
z))T6nbSswdeO;`Z(@O8umCZqYx!V<1SAQJ}LE%mp0aDW)L}$E&tm21_qRPY*v404g
z=uE@6LpLRS%e;p39il?f%Ugk;Wt;_)i$*uPgSO4xGvu)#TrRVbvx-$PVBzsAxCefa
zjlgNowpz8_>Z#{!mWTy@fdPzc*{qGnPctr`!qI_*%{=CaP-j4<COQ#2-<eIWXEwIO
zDdTS4?+&odxf;@LhqNWkwJzc00F43Sz=3zbBvJionC^Ng=YC|C&>}M#sT$b~mYwE$
z{DM5Sn-iC=oRf`omT0%|*v1pj&18}vnq6qyy0awQO~7B$VA_LwTc&aKNt(sO*RQ~&
zZbn%)>f`#zR6-A|k;=(|&?$^AxosUM9p=ag<#G)f<yBgqSLdE}T(zrX-HK6Vt19cG
z=?F4Vd@oB~!oqCIM-^5${Md$BmoCD4n7n+-FDI+N8Y)gtK&<sEl=`=l<1ENJR$Ecb
zTPzC|y$WlG>t2SUsJHRLXs;la20wM=$-O#IslR;c>{QEG-E>b3oS9i<ea?8ooh9RP
zWp6GhWPmTQ#M=25)>aFS;bo2T)joEMU*~;J$F5U<)!)*cmzN5=Hv}PKZM2<mDO_rN
zw3e4j<oWa;dRAKrjVp0?6t?yt?WMCxI7rIjc42Lv9?9%Iw1_*bvT8+aHvn;_^;Smi
zgV(_Bo2E|TfsfH5@44Mle{#;*XD)Q{Wfgzn$DC{Z?!LX3z*Y(gWpa1Ey8H&$itExB
z9~ySUx0|urnqQKRkIz6Y{Mm`~7FN!G<8pBC!j6{FcjI{C;n5qgyi>n+n3w;+?K}mP
z%<&74U1rl*e_pGZRnMWQogw!mOgai<+0(0wCHD(NRQ(Y=7UFr%s&oz>SNs{Pq|w5~
zTnr!n>MKGa^^gA}Dm^HhWx~5Xcm>x-XZauxfZ$USJT3vns)amp5T!-luG!kU>LOQf
z5~eRq`IfNe2teowV<6g<Kg*u7#yNad_!nZm?Bp%I;`23=AVTx6cGNXO_@720=70Z-
zb~l<@SpB=DylxFdePe*V;;3=x_T-pX!e4$LJ2pb<kSy3YZ$xK(wANHO6H*@RqF5r;
zg|$6XMjsjU-at2S7e`eFb&u_}>?yLCV18?&*h5!AMdIdgfqFDf?fqw487=j&`-$a<
z&_^a}+ATebJAEFGXtu6LMdFjS43i2@aw|Js)T<f$xVT9;VH`Y$GzWGVG1sZ<+m-PQ
zsm0fZJPGNdj`xe}QFY#Odl#99$pYxk+@)NmC$dULdiwA!loIyXUbem5vNtB8GNXin
z)G5t*#gh08up!7NZ65gks3j)`D-A1V7jTNxpx?{!0${i}t2iDU9fiCAXKMhYs3PFk
z5V&KuZUn?|ur}y*o<2?~JsBZNZQQDz|IyXQh5Qy?>^FhyxPz};qpO{ec&~*RZH<|;
z`>QAwP1u69lZV~1QOOk*u1=Wp)!9{tnN^`V-#ejC5<&zCx<qOp?#Jj*8Zfc1ldwo4
z#{_?C!h}Sw6k9x0N#$tJ3hV)q;Ep&~TDlncvJMCpiyblRh`_zcm*FZe$K%KqD&MB-
z^Gf-8x?FSK_<g#n&CI~r%$NG=2|Hw6tE<jV5Zk3xRRjrraW~kskGinnV#shX+J||0
zxHPQ9inw3C9&l9n!__Roqz{RU_^i9d`;}QFS$V375@rQQ2Z%(ay5|0v?hU8Ky7+EO
zN}Y;v(RMmT<aDcghB(~OY^}0`Z&yfnj^$OANZn+@Ikz)nH|7DOpTXxD+R;Y6@)a2<
zFVm3ol3CB_CL}`&x|(I+2WpxHJrWAMZPi^BgWKG!@ox)a>%@tHY-Gzz0VLM<exp3q
zlOTtM&jM_-^C?pYljXf6s^+GG%D?8AVtDk{o>xB9u!^~0-ob9vc@q<fGK7uZgmKUd
z1x{94S_lVJlEKN_c%Gy|(@2>Mpa7o&CF*Yx%*hmy9HbIrJU_<|kCT+Uf+uB6rPkxc
zOaV0{<cw!LMM12x&>Mb=3<c>YMSPwHV?iQ`a<y54Yeqy=x}>C_8No~kI1ygStr`Hs
z6t+|i@A38m*bYIf$uDRQqt3UNid1!)6jMO2u?{&=Q+dNglIb%{%gAS>1(ddmlW#W&
z>R#W<8^|ERNVFp3u`)~AHmQh|yb*J&P#c5{IH%mAQYMauNYLaR^`K)a^$=)-&-={P
zJc%FV+4LG8K$*;97-xw<g=cdD$z7qX%0_k3s~$0zgK^MUrNJ;DFn8X(DqCF7+Lc<I
z)!1*Nb^<L0b$XdiNnd5+ITr!P3HqWKaS+cMyiHqYX+~}k<YJ9bgibgvJ2owShJ93W
z^?-&-ub>vJ`Yv^n)NHl!A)p_SkjJk@7G(Jd<C0P;dKo-Va3^iGa^Fs7aP@*C#<B~D
zm};29G(RN=t|nh=qI<wQBD`f+(^A{$IAKVX9XE4j+Dc(NQ9NnmJ`6fbE0iMvh1f8Z
zeF=reew!O#xA8KtQo&Bfv?#Td(-R&xR5=}zec(b%x!j_~LBbqAlayOx6!=1jwbiI*
z)>5SMsbU3!C~S$~X<{Wm>oO5)3=x^A*cZiC@_Bxdt*8TCwqCxJUpE)>bU_?l$Cvw>
zP$yvfdy^um5tRk$oBs$^-rx`)Uopt*DxS4M<gIxsmjbU#2PMc;=~J#31xIUIBoevj
zL6<0vhJLC~7!#gkcl>hofk4s`T^>O<bCGX~`U}?$s~88>rfj1eV!9nK6{4>)#B<Gc
zF(Ydt)C+fuUa`$C%JUuJ`2pMcC2sJF>F5qla&~LZ6d7=7oQtfBoSrd4sBT<6KV}Uh
z_>RV%&_WgXKXL6UawDzpI@<x~0QGH}O7ErNo<MU1u{z2XrKKTdgp1_Ur1VM3cqaAn
zLj!?b>l}YgHzulDlmeAc*aSi}Y#QLlly2f@iS7wvE5xA;>fE6fLDqjI59FH01AoaF
zq@n$a2}p=wLC9bb2N27~&*+qQXLy7tRUa>I`Z@2pVz=;XIy0}(tnhVbHy^DxY&Qzc
z<t^C4Tmy2i0efT%wV>?NqvIq@<BMs~yvkW9bsfRA3zWpI^7H(V!Npw4T|s`UX(OI*
z@}^3EV<yC`I=-4h(e|}VH@T%pU1CI#hjzB4KDU%_d^lL*aHuOCrcR`C_X1K!wmu?8
z7N+Mw<u3_kxx_}Vz#)Kar-7I~$OzWQ;Lhbv>2I;)+xhNar#Lp+mMt=|phpgXENPk`
zH>#lU>c&g?Pc5@bGyOr{V^pU0j@SqbIc@(1_24rUa!73c0o-f+<}`4GLQ2=}<+NL+
zsF290{(D2FmP8>eCBeTqVlB{7-JN};!U_+Y&}vR98!|dOwJB;xCx}%A(0v0K2-e^`
zj_$o11)DTK#||c2CQYvFBJS+)o1(^&jf#>kjoEaJjD;{FG!0r7s|L3e@VjY+s_Z4m
zkK<(7N;7?a1*LOZ9-*(MWqWpWNHWzKETtC%A{@3)@FkZf&n(eJeq{Uj7leij{id+r
ztdv()6`51wT#RIwN33+divEXG8x~)3TSIVv5rHQuR3$3kRB2)p$$p%#t&kpkV^%R(
z$KM((d5w?r>(>ZdIlu#<24B9?LdZjI_hnJXE<K$ztArh#?e9q(@Vd8{OTIPBn|}?P
z1Tp-L{gVAV&aC0f9vWq*o<OswCZ>;utH{?=mSuYUc)bAgqlET&w>kGg3iF+>$nDI2
zPOfHNDboig?fs4mN1k%jaN=aJzNR0!)XeJ%Op-qjMBu$FqLeJj4Bc>O>Uq&Sc)K5}
zQ2ae_ih5<XeIg;7`KE;&Gbao&8UF|cxcnc&iTIM$V+Z)S#2q}GSbZ4U^PVYk)dvU(
zRq^Zumj8p-&0o>5pCKX?XZM=s-_wCNGbOM-Yxc-hE>XD(&o9wTiqPPNi8May^Qk9d
z7f9UhaEn{V>by5|`Dg!;@#fzJUijx<mh$!b5ndHzQ8IrAZIu$UcFD})#g{K;2XD{I
z<L5E$c>hH<@$hpl#3iP??r`nbJ&iUJ-icG!&5k>|;NKuuW!nNqXqw$`BQu}PM65Tk
zd{#|kD3{Gm_(7Rwfnw~$T4HA&`(RYqruc20alK$FDr^lsu{`0;rr0mJ8VfLfTVt)^
zEL9mpp<3*Cv$a~FGKk`gl*I#@RWQ9s*Y+$$#r0tPyTX}MUo?B)*OL16#)#XBt2C-N
zoc1yk->2L2vbcFat`>#JM3_H?jhw&J2mg8wi$b!vo~JzY06(s^v#;Jd>g<W>B#51Q
zrN4Te27k25l8SWCrMMfc`!&Beuy|K~l+S8hGwXN}H0U!Nt+#wKx#BM$|E+M@?;Y~R
zXP#?>@Gj08Vn15SVqKVH_0sQc&6g6s_1OP{WdCN7&wKX)#ZnrA@RUoAn~}2%)kiMA
zb3Kpoe!eoHiU3qqeH|B8H0oK1AI`ux*;!E$mh{J5z8GSpH$asxEPd#0HGz{nS=fKr
z9~?iBzS6&m!AHGQFQ(FRx!BSZD#G!t508s+IW;wMlg|#$gb=O{?$pmlFYK?j6B|#;
zDsY?YO2LzZwR3*1#RwIF1^!j;x~RsrB&cI%{LRN{lgkuFLs@&fl`L_$6}5+NYq<0b
z3VZlcYlSyX*}&0((OZIN+VM8VvY=ETWwzeSR>AWt71zN#-ll0bi=EhJN3u?U<PbD*
zq|x;vE^%^4#foM-OFCXYr%Qwu*BlWvhR*}{2yLmfUhK&G9r@|qo84ucsL5}-F(TF+
z3E}}{vI6ukqoW@P+S98B!6bA|W}JCvWoe0)LX7uhWraMK_F-Pd1I=k5t`~EbiLnW%
zyaJntjg>$Og?LM{Bo3rh0ewQ)8ISQdVhonW;tW?w-#0j6GRz9PBTh88pis>QD=-4&
z$uC;C6-`DMw|(pl0oeN4p5Z<pgL_<N%*`!UGh~}y6ZBCJtE-wC#k561!vi$vjqfhh
zR5OXWNoNhGg6$2m`Lykdq#Ni>3T~E&@xmOTM7OY40>d;ZGk|+PW#ybxNhZ81IBc!u
zS27uMX~WOGfhPv}sDOLkrp$--4_nb{5eRMBPkjI<bD`}TQf5gv!!6O{qHvqTcXbEF
zI$bz$^<LdKftNcn406>F1N_DK!f^1hR9&N@fg1V)UxN31?2W7qTJSS<yo`oQ2$3Gg
z@bGl_s$znm-+b>*IHba%#;D-(e7u1JK<z#d7+Lcc97PLETe}#gYT@GyH^fXd40+sG
zrWwSx!JH~qX^}p$Q!ZD|p^#E-{C(!<sp9OxutDaITN`qV>`nli(9L_;220<an3T4r
zw~5?7NE!9pM^&L61$J-{LOQAB2vyB@OuqBX+1oc;h`f+%H)}28w7l>$9iHkSJ0Rw{
zY)7XM5vrZhwc~|32ea$c&8o|lrvsub|HG6`+6k=kM{uc-`GlD!M#_GWXGc&7JiV?m
z9_~ko<UR`&F~ID9MGs%Bz4Gq@ZkITsQv0uW1zT(655+;p?#NYaxX>w2?dS`Cm26~+
z_CTO3T7#y_$7reZRnZ^67PIy07-qJ15gn6&Bl%K)$VYe2OZY66bKQavE9#U}S+^fs
z_cm0%nj!TEI)v(PMdI~7T%1kvnQAwH*&2b*Zxm`!y<shJt(8~VY-o&pDk<+&0**NF
zZs_#h<}4n}(8ua(@)XBDl{eCsKdOS|#Tv|38~hd?|57loMs3d~D+6|%FF0iRnmzdL
za9{X$sbjjTJrwq&<BR_ov`O$^EHt+y5P^f}VfHP*N&z3Lv%Cdm8_#C5b$I_P*wv5R
z!jqcR4tVV-AA^{Whm^u3T=)rswIlHo?%}Z^hc+l)f336YAHvlS!1gBIL2Lg9Axl)L
zYwgZ@+ud0dc`vUs?Z0N(9Fa5F7L#H!%g;Z0q50x|7tPj&(oR2-_=tyl7YJBT6zC(b
zo*jPtT3Xs#Y*g_q5#^2EIkaB+PAer(_PLTr%d!35#!p;}WQWaRw%Sc=qgi?Ho+0gY
zYr1C-aI_|CBRN%#lR#4U*hRq?rCZYOJwN|C8*AUPi#(g6#vGm$9Yj@n?i~m?v;og9
zUMCvM%XMOQy@Ts96Oo*z@;iT<>T%L3z>3G|hQ&6lGM3pI^v;>g)>!IKt<u<}TfV3g
z!k_lpT2)T=-mjf9eOtp+gP`3tTlL!9TW9ytnbl@%33@)}2CF<B+dsn!+df`p<atNh
zM4LU)ZVzx-5ocGzV4-RnCMin6U%k%B0QXC{!|)GMCz_u1&%Ghf_{1D4m1JX&><>4g
zsp3n|vKw#kL^8_@hW^o3G+V8hd2bR<eT|3f-qx7$VUS>to|qeY@NGTCk_axUGRP@a
zIyp8VM2j*SJ;#3{5kfCmsB%`Bi45F^H4sc2w{4{Jn0dbIO)y(ssX=O}sycHD`$k)e
zPfk(`-1+g@BLD6{uV(&Dbo1+7JdSU!hI(VsT0S$)RL9GFj2?c7Ptg?KmZOp$B(27n
z;b*I~K@Wu4%DwA#BtAJ-2BT&!N~>HBV74|<!@QEhBcF;i+E=knl$`=|80kYu7VQ47
zQr^<kcUJ<|S$ZSXGJCvHFpuCC(?7Q<b;Og>R>tFH-wDQf<wdC~NiT3!G3<<1Aac-2
z8A!A<*7IYWsiY{8dKhSl--HrR3k_u*(pGJnmK?YQ^9ds*fl4$#9G$%{YWw84n%{}&
zAqki=(dkutf0;t}5sjS0%;;qpl*jV`g>@^NSDc0cy@08KNGEk&%vcG1<t0l*G-InJ
z#5<Q^wrU=@g_lZZ3yh>wNu-iWNSoo&lwY8nZD0uk8P#6n$$=K+Eb!|G@@Pwd>9)l#
z6*?HB`q}Xk5#vR27NKP>NSc%fPYmXQ(z<RwFN~xm*}1b-E0Xg=qj475j=kQ}ASL$%
zSuU`0Q13v%5esn@NA9@zW3jfO&hhxZ%mQHmCON5!Tzhh2HDH^Qr0xY2L&IsOUB%N6
z1{cV;uj*qgE8K+z5kiurRNkJ%fl5{7rVyEJI*f@t{GzNZviln;>`ap|`a-$~lk?bc
zw7`fsBG&^Dtpcx`GNTH-37o1*Y&V+%dpIHEL2(IYt5Dy~uPaanIYZ_yAaAB47<im1
zjK#}~V_d`Hciy`ab`xyp&|7H&C~bhUBj{A!3?@}P-Pv>%*F|7j-FWR%MHEQrHbrmm
z%<ZB@aX`SY#nw&6NF9_DimHO+P;xlSoS8t+SGA20&i_V`)FxEMKA1NoOVg#KSQ3GG
z@STT(M9hg^meB2)I5}S6><xwZ?}jQKRe2-+i-2R+5_Xq#*YN@}9<<n3y9y`Zk8r{k
zxx32K^D0$g2tE%_+CiIDD^#T18#LA12hGoOj(gK73j7EWuXb;LD>4xWycp0~%Bjny
zTx%PKNif0k5~w*ntQXtkk|nd@q05MoWcQE`6>xk%F&y+?<g{8_<0n`_$W+u~vxq@E
zUSJq8cR~nuN3iqDM%{Pqgtj@nyV@FN*j8~1Lxu>xlQ-0Of!#&eOcilCvuV#timR(q
zZG~}1mjgVkG1SZ0^$~qNF6Bp?%;jU4wg!C{wcKY8&p5oxOs~y_+dY1utXNc@CtnJW
zWHie<W~<f#uqk^$?om1&f!8qjR!$u)4_7I80}hisNN$%hMgxzA_tXRqw;b$~c1x-S
zjPkSo;q*s5J&*3m^YDv%udrulr+&&7I5L>7*dDx|WH*b*pkrQ&C-2*+{*wym6RKgw
z^N~g1<$uYs2W!`Q+bEUiqiyoj+CtZCy`LAg-u_AFiPujQoO;7h-k^Glk00+gWrGL*
z5--F4LLrzmEH~m<^LJ-M=`|abov`fzwsymNsOy*|@i0spLm=!%Ud8hgTyn|s8{YqH
z7A_$`_G26?%*ylJ`>AAs;pYO#h%)BZ_c`T$cR2SE>=cTJZy~$mM=i%}^-8h)hQPam
zNvw|x`8#H9Sh+n`4&=il?1b3+ca$$*k8FPVO{x9<-wn=&hp+cT`;S=LJxfJSPE&X^
z>JQztuizY0cAS=OE?Bmb-*stWpSxEadI7RK;V2JMrRUdyAn*RGeRAT-f%L=I#_>ca
zZil<7hwMj4P0N0i>E{U34<4bwa-8zGTSQ3N%@vfb5~c7C8Ec*9Fl7CZ^l<-&h&uIZ
zq4j{8?aJvN`m70wMAUg0O>l{O30RZQ7O+c;-@3-;MX&rP7|AdhcX;fluS#t1JAE?y
zf0*V1jH7kTD`Hn@r|r}6Bpb}uoGh%$7FFtfRL`fsH<CR<-rB=I7>pIujh|(|mWOAo
zzw3!FzH?DJcKVZcvA^RdL-yz=msxqYf4yWsh8Z;DY~~A%G>yt^P1&qX(rAl@&Bz|=
z1#PO9av6juRg!oMB<+vm|Bfx$=|9~Pv9qV!W3N}Wg_h$x*w=R)oqNdFRHIZA0)-d>
zLl)(ri+5*9cKlAs*9X9M)efcwO6)=;6McMJW9f{`oFATFP{8omuf_bz&G0hev$=m@
zd1tjX!+xyoZz1dep>18WwM7=jqAiLZ&rG_(aEtk&wIn2w9TY;ME#Yn%r#{1R6250%
zYoGIniuPTfNA>G_!W7@uaQ4)Ip3;d+{v1?t71bBi$1oNfAhDWXPf%e_cd<4U(G7|Y
zM;lNN)f+m`ERYi~bTI%tKgX|vZds+&q^)$p4?@bA%3G!#_Pg3T4~w<1InM$0)Z8Q2
zJGstugeaoLqi_~;w6Dme9*-bQR`*`lEr)3o8THpO@@gtsn_`4J?XEV~hzenjc7vU<
z%Fclh4}Om0Rf();DQ(Bk+#jE$?2!By1TLngTsdjTgHTy%ExCF?e4Oo!Q`%`aJm@EG
zQAe^_McXG)PU=o`o;DYCyi%bCZozXw#QMU0hH?wF%nm<5U(H}q*$5(aNq=mQkP_^`
zuY#@vZ>WY{S=q9z$^^=_P3@X0L_idmJFi^0u3P@?p>Q)<!)36|tQ5+i*Hx0o8Az`A
zlejBMd`fm;>(`Jct)!R)H58XofaP&JIC)9Kv$|*5tkjsGCuK?#%X%gSoH-4};f`un
z+zwD%$~(k%f*UqrdPS&T$gk^QzP>VB9sVea??fo8fgiQmtR=?`7tc>)?n)62@_`;E
z71$FX?@O>$9HS5wiP#nt_B0ojB3ZzWkw+?GU{*0wD$hWPDh39y)Jty>%lRr(jDmtl
zbZWws#i^kfi90V^LI=eXHVNmq2$8&T{_TXv>6eg<UL;#tr47G33qvjZfnTSiDpZt)
zhJ;8Rh}RyM-E%<4vKk4nS*oLhoeBCX%5B03aywlB{{m*Ef|+lh-a@?Vq2-P^q3jBt
zSSU-afnU6M?g(E&V#~2FTv3-VXjh17I;|lbTqy3`H7o2Yu6FNoo2pG!y-hG^ztpZX
z*W`28b8He$?^oIZW*Jn55!#ZI=3P}DDpBlv>)a+2as>XCRiLlJ1AfdIX<DgAR819e
z?*&<9;BJq`(qM#Q?NYPyquy_iwkb3!_Cn@D)<ZGP5XjkI^1uMfw~?Qlaa5E1!Q#fQ
zwE=6EH)3b}wJYOiFBm5SmuI?$YDMymcBET63f>OX*1~6<wxETyMvy3c!J>K&*f;i-
zoL(Btz1dP*J7u=Up3Q(vboiurCj`EcSZB4B?Q8l(R}ToRY#CXwHHrgM9Ci(Lt^@YL
zWy*!JEbsJ;TUKg1r}w6V;XQdsKY6cR#17yGS(mV6eJ)tIA!Hmfkfu-VnHUUTmeoE%
z>Q^ubyO~yXc9OwQmU(-dW9Xh~ieh&NG5t<BS{jsgzVYBtidmS|wQ48yI{eXtj4ZJa
zLirBM_FseMs9<YaiQ~)<c3;jf5s<PHm&Dz=$M%QmgU=)bN%o0Ms$7i=Y_JXNxiz=%
z%~Kxyo{&Uq`K-$WsGTn%$;4VxIluRNmW1+dJAe86Nn8^1cV3p;v}ZPtt=G1He5EMv
z_pA>hEd^6qquh6gOGIn2Z4-Gm_^m%3Nyuf8zW)3bOeOqiB(?v}ITF)<QqgQ*%%WYm
z_>dca{FAKeXb15B{m~`99%=63l2P>XALafd<-npnf+3l={PZlsYmGa7=Z_GccD;BP
zt?M_36PuadT`ppM>bN$fd`aZ_bs)&G|1wMBTB#0>=?g&A(VMX-$A0VMvGa=*Fu@jB
zTnzd)qwB1#YL1}Xe|2tSgv3W(SbHhD#gNtB<kiL>^~Kb};eSXDYPOk*5}4vQ5G_9<
z)*eTb9kv`rWI+XZvG6YaG-)wg{YgAZD`j)*0g2~Bo$NNh{eq&g|9_ORzL2E&E53z#
z(|TcLxyLWv^ZA5RW2mK=trn;>lTZB7T--kp{`8_WZgOwEuQ5?P`hH8U2tv64$()T%
zl++qF2~)=NHiym{LrsX^&ty{{FjTCi&;rQiij!kAtliAc<=e>h40Wd`V0mUBX7#3A
zX0mUrnm80<pGt&FpTHA9jX>F1`%OV1T&N8LKTkc!I>TDNo_W(fs&PF)v>x7{jzPV(
zX|*-PWTgbhhEJN;Syr?41F&^5noI6L!ECitS9gN0-ewrkiR;{3%cj>$P&Kdig>eQw
zsuk1}|0d@be@OQ)Cf>OisyCU*>2lMry&A`D_GJ3O#JnU+zm=@m`cI}=(!S1ypE_^8
z2;?LE=w)FD;Z@DrJiJ(gZ6?mSSP^TIJKRnnQ@Dz*d?(mcGxB0!C#+6*z=0H#Q>Y3j
z^@KZ>X1-dImf!J<un_LoeK30BoZ@tJrgT+8)bDd7-XuYc-{ulxSkAnhdjYzyC`An6
zbvLszc?<-83}7<2IhME0ynf_?@qr}R4Ia1TaGjxKnvwT7q$>O-w~!u5WA2(R1}>Xl
z2%IKC=`*)REhA&O-Gl@q!e+!qKoEgJ&ub-y42$$So`4oxn{27XmA(V%xc7jlvyjI=
zcstaECyg&e48jFre6k(N^TQA<OmqTUCW&HMlVuN`5Z_u&vknG&36H2SS~UYkFsj7B
zpf`VIpSDI+R$!EwFwP80U4z%A^N=*n4Tn@=AVeFgj^|d;*7%c_d3-3mXt?yjtY>!F
zdfPxoWv{du&Y1Sf#S{TKxhUNEd|7O)E^0p}?mD)V7Mx{_{hKpvHd{;zn;N!LcH9<-
zH}7&=*794Hszz%ipTb!REF<OvJfz?t`TGE**I*E3z7SlC>5pW)m>1$!A<|uV6nEek
z4RO&1us|nP=5RO~Xj@Yol!CcV4?y-vBTn7Eqftg3FT^VmyMd~@DRtndhPW!WEK+!G
z$Wt%-c9{@rit2#Grfh;uaCertek!rff~cs>kjm!y1vw&k%P5PL79LG!@$)z%<dY*j
zsG5|q$~?p{_&*XIT&AXxK}LZ;*Y-Rv$!J;5IYI}LO>`8oJt&_QBpt`*JIWHZ7YiyG
z$4OC=C{&4c%Utc&eZ>?jRR~;&H!iB6`n@O!U2NBN$uZO2(9vPECA#AYA?gk<&A}R{
zQW{jF6S>=6OQKyBMn|Pa=$-ZyfWM+neJ)LpK}zM*!=j!CO6{KbY-1vX9pFT(N4APc
zL=Kjjwnb3sDjD<X5F>WG=#da1ka#n=j^|lelznB96siRp0}QU?;oI|p5e348R20g8
zM<sj$K2Pm8|G9?EVe`!vb~z@<$qDdZ%OiMg5yt_#Ozqz~e!($)ZKF59Rt8=dL`0BH
z4(@HTd)TrsUYlYZ67&a|Wot={)yXUo3V&Xu1!oseS$HEN=W~|&7`gK$n9U_eFVFJQ
z$Nr(ZAa{ghIyL{EBuP%DnQz}tN9|8lF`P4M8IMoKaZE;>8Ox;lJaJKmAe?a|i@wat
zI78J=ZartJ;Kkfv94_1uU#Q!I3r-QE<<PwJUqevm;8kb*D?h+jkJqlPo{pXPUGMRA
zOub9$23_1I3O1V|6T6#b>EfHg%J7psKiZjR87oZkk&9@TXlw0i+_$QeLi1;{;%n_a
zHY;j<fi^Kq6@g!hqCEHG-#TD(vS;7$6-u>ayo}v+W@>%0dLt7i5$(r6|3<YQK7TQb
zvGu?o(U_!pDoZaIJrQ`d=cgB(6Y^YzF77sg@>d=^;Im<vgu!Q%WQxfrsno`Azs`Jn
z5;4i>JHKtK_YwHoVdt6swlDz7vAuWb#3b{1I$8`%vj6hnp#M_#=G3|2!+3i_NF6xY
z&x|wMg2VFzQeBqNgSI4ZZ1Gj-t{@VKRhg~0b0n8kT89jJ!Bd81ON;)>(oJWAO2L;h
zQX|hJ>(*YvZPLt%A0+7%MsO5Hfja_hG4QN-@5dX_O7>8n0o&c)usa_+luy0#WJoIO
zp3pc|!aazs!(os7VPg4>NHTCyT73NwMWxVQ5I{Khug5H$gS4?Ip`er!xF|FC$Il$F
z)ji7F_2;MMXMO}KZW|;-A4i$`n?qhhf|e)nt&M}h^VN?e9Q_S%cfHP?af}Z%lszS-
z-ulN4C!M*GU%Lx$4+zL3LAY0vZF;xW%j%N-m|$b|37zqeI^qbSeqmMJ-SHb}07Qf@
zau^*E)8QXiMOM8)D=ESc&v8{kUBA@$ij3gi#R}WJl(qcxRqD=Z*8b?|Tl3XReCGcn
z<km$~aCNL|l&EZD85>OquuR)#`qo{1;>T1(RpCU(PM4-4e#mcd6Na=247f1jY~;?>
z5iyy0QvL6JRw_y=js1UimP3?r&MT}q$~)@z!4w@d@}#^<&$A5}vu`XCLwB?ICsjdh
z#BJk>l5N847}PbYrXr)9i3+%Xh-oN|z)yuT&Ck){1vVCCfilpT$lJ#L>LPRaXknqs
zjtG#A;9neH(GW-_;tM$WoVE0kx!D+^VX{$<&j*<n756%(Ki=_F$}MG3dCDosq<)$$
z{E3eF05V+w$0}iv3ADk_qYp=besjW6<QBNr=<v)F_TZNA9Xw?n9(13sJ>6T`ePVQj
zdOH~QH*FETs<3ci&ZNA<S7rDd-ts*`XWeSFhytEA^RdRyHQcgrC<2Ogu+qZ|GN{OH
zAgrz=GoOkP&RoDzn$Ldbby!Vp`q)kimohsYJ+Q54zn=FG38C%=mHf(NEc8Yv#jba!
z*mFZi$PeS|vch6cO8i7lttK55LMpvvc1hf#EorhA8AhBm&PlwRo>{f8%`esnKTM^(
z70*1)xsqN{J3-ipD55hhmpefohpT_w`hfrvyLG)WPjfBm6irzS5ym0sa5YqdN051n
zdn`@v5oC;nm?nA~KIg@p4J}nj+gw8xmY0>lVly>WD>r`$ky1ofA(_{`qv9&8VdpBq
zyDEKEos?#Gh#Z=dSz9YekCoiyeq~JNC3%sz&_FUnqyi(F_MfARr7OpyTs%PsOFt@<
z!-*$NU@!yjSi}3_5u1}_0X-GuO8pslfy=HiovgwvzobU;&+lw2n!A#CL1b92HRw{Q
z#=iie8k{X=HQI)e8c`)np@gp@Hv$*0eOy2smcUhtBBluO%Ei~k-0@3So4{A1It7gf
zUDLL%eL<+O3Y&>cM2bAjrsVydYMN^NL6RxQj^akmQ9RlpFj>_*x)v7QFlV!492ApI
zC<;<hGVTzoz%SK~U2c-YDZZm)xi`Z}*;oC71F`sd25)DBO&`5<%Vsgnw#RZVp8B-;
z#oMWwYpO+;qrsCEgTU5W=k0QOF0plLHZN0-dVs6rv#&N5l@A|oUyMN|I}M@Wv6gdo
z4-@v<>SL&pZJo-l^i`ix<WHu-!Y?Jcc=qOtVU|A_hu(4a#M?6s8VT)<t!|v7o7$Q8
zk+*kQ3fm-+U{RNi=a@r$=G^Q?`{-1(<A>KTO`O&NlKZZ;p|*`T?W62&JCm9#KM)J1
zowr^^$F0rBb#ckDGmwpe`2nic{;D!(WuvO)N+Ke0rAr=U>kSh9C*D72#TUXtm><OU
zBLK=?NmEu{d0-Szh6D4q|BiG~Ru7v`Q=i|FP6_ojEZ;5ZBYXSBcI{htr$=Q6^#pN|
zd~bMWv>k+f{x3@QTi>>Jm~GbA!1J4?&pkNV#?DDIi@zELt0Ws5nTV|?9A_x}1vfhb
z%7z-Cv@Li-C%?-S-#(rwWU{!$9~NT4Te`&qJb^;;ez$nzyC4NyKSfOJ4D;uTTi2eu
z+x!hT+k>OuWC#EHf%*TEy*a<~w*ND+@Dp!>+WNqC{__;e{o~0^lH|$X8(gSXsLg_y
z><XUqh#$CRgil;w?j@NWUn9E$7Q%z>(wLK1dg=$lzxrQ!(fPU2x+tq8mp~yrc2V5y
zldY}qG5e<<XDa+GGM0G${T~*5vXs-C2x)a@4eZ1N)VF@wV#EjDuTF9g$JX1}2o6MR
z`Of`ciZ5QX#O-3?OHJjy=aV<=$5^$F(HScDk50~7@pV;$&ntN!u=@WT=93@?#yWaZ
zk~sg-EVHD1=D=L|K3~Qey!%i{i*Jvth7&CEe*c;<KJm9nu&*7U!~d8~wtmzYE5H89
zeCEivy@fZ>WuIb95heTFakg7g#r@H1skw(NomsOd`;bc|W_h?5<x+w=-pLY`h;j)G
zR=28*VpmfK?0j3L;fIGd;-T;Gc|Ii+^eidtfxSFht}`8cM4QAa4o8Aj3!!z0OuLZ&
z*F>+*bwt6{3(Ai=swnJEyie7!njAdNPX6+B{=5ydRWa|qAQcn6WNOL7)ea7hLStL~
ziAyJ^Z5A!|0uMs?u#MPXY<*6R#oit@+DN0ASo?or;@*@7cUiJzD>s{4dk3c8Cv9l#
z>}&Jiw)0%R^rHb^Jh{iE_Q6JJ7qQk~4l}G``ZVRGjRp@dZ=X-w(QMV2sb^J}WDy>p
ztsS>1m8(6~t<unzpj|z~JV8B$`2tw+b<i(SwuOfMs#BwZg3xGQHObf2i6zj9j-5$x
ze~`1Fi57IE?GaZc(M`uhx@BBY1jGuq^Y_szk{F^IeYAFI{FXa~bmBS@+uc2Z1$3Sd
zjsjQLuwQn+cAILv>}Nqs!xUG~W7Z+57Kqcp+Y4cYzFYgLA~<tCvtW7?M`EOxRpCBx
zr(AnOh$yTbNXZdY-?u<N`P)dqi~<i8asns^fEVr2*Pt&l7cw>3%v>li%M(IesS>>k
zMI_`DaPgWlrf*4QUCCnbE|<lQqze_2S6?$@a|;h9E_BA-L2=oIT!Prb1Qf5p4y;rH
zcf7mZJw(XqhVlZ~ttv$v>=GG#db|$Z%d~{!Nfc{xrrn`eP%XyK2{v=9%`2xPyzD!o
z7nyCA8ScX2K$+EA<y*OTsYmxNmt$3&uTiKXyCC-$70Mc~&Am&G{xrlALfL%fa#Zaq
zf|DUPB&YU|9F#+Nv^_aDnpEZ6;fnqQAzsxWfxr(<#_5hIhsSNgRNw|wKFYWP`pk~A
z$KAD2Iggw~nvaAH*Oa{;pEu9JY<8<+s5f~)9#}6v&?3Mq@35`wpIMtc&npqsV!d`3
zHcA~fT;K&r*-|qdu$j3S@b|xL)5-K8O5VJ3I)wC|y9C+-SP+xl0Q9L0R}ggjFkY8f
zGis{}e^J+T8*GJjt5`Q)p{L?tf^NTwAo%B`M318<_?#ERs6(6RBC@0&v+*QA<XqgV
z{L&_!JK)8zN}$RV<QZaxLH9?P3QHg*YLn&^1T67G7XX)T)sufWI80>N86mwbW-#y_
zYPU1irkGOhREw%{byMxH12<O=j%0EcZb>a$8wg1`OrifESe4ziC_i{7d1KV2L+mVO
zpI2`P9IKJ~Y`uf|2bH6&_R6K{`eaau=Z9ouxEwCzsDZI>SV3p+Wtu37FA9TFNz_5v
z_U`vK8ETqyF}5a{+XwbeQv!!)S#7<?PBz|R;pf<j)5=0xzH*klU2EC1<6)Eq;yha)
zZRgDkMt%7G#G9SNG}Qs>{GYp~oxuzU@0+MfKU|PjCuTO1M&5^H3`NiLE#?ID#B1^`
za>u=@F{n7?zu<GP04-Yf1@L^!=r=8mb_({|F;aP@jGKhHug+Xx?YI9&&j^0ehP4y<
zLto3hmr^cXpQtK(en*!3zheB)n7*H4jflm_Sx<2=vCX<9H<pPHGaq|RzQDVRP7wx^
z6OL>RXmhLxdw#a0?aN;uweUWY-S|-?Q>X;$1wY^3n-n)pC)1*}P+{liUt>u-uod>P
z1Gzir4u%o?UqRPAb55H6G>+jrEM54-BnLyVKs<65Y0^EmI(%e?Vwg>ff6L2s!$0Rs
znXSpA?~O%~-&gXfl;t-d+0-6OT*YXYt4}bG0&@b@T)01tb*;Q2X22yo+E8_$4>%z*
znXtft!M<FfJ=T*6GMmCHE{|l3wFl?S?mpxyvsFnxedVZA0ou&}msot~SZrmt>7g|(
zlwRN{r*QD&$*c!6+ru_pmEia3+z!9WMawTLT}+soh}LqVa&!Fbzq7xS3|sjn^8V<d
zd6}*Kjf7`Tli`nCU<=U7CPfQS3wURl`SNRfGQ01N2`lbCv?{jYw4Fa&4zF8w%QyB~
z<M2D|_)VX*dH=&kk@G3QFcUIgS?y=jDP=$XdA43iGFDsdtq6bQGxsyJQb;eLCugpW
z7Y&rl*3%lA8p^DJK2p%Ey?xy1_;QXwy3c-eewqaJQNV5drr#bVEbNOsaNJ9MwQW|h
zYgbW|BI;|#yv`PGMz$w63nIK-K+CcmIq&WhPIBUai@0CmCGm$fOl9|Q%u{5d2g4dw
zCZg!_{kPTbdkZ^f{Zc|^XQ#YkdV<vRU}M;G>ngi7Xwxpt=Gg)>c0v0`9n;&%YwZE@
z4cp-O-Xlg}o44S~Lrlv5wH~LpvU=Ap<`X2d_Wpc<=g^8h{Py^C&g>hDXmyXxg<JS`
z6U_PnhSH}Ns+@fo9c%#y#}^9>LBjLWEaG38u6WpTi=EOAn>^Z(=6E;_)_s`jmLY>H
z<>+cko_-*oudssaU_&D2pw32aZN&`OQqaAI$hG5{F5n;c7IZ>(ya$?uQ>?V+`At!`
z<OV`EU}I&p&&P>-iXgH-%I@5zjO66yYDk3mHpx+jLV}&a;9BJy+Y(xYGB9Ees=<9!
zh>-gMNMw~T5UHiA(v|%r--7e{SQ#Ukft0!&#S+b#8qKSMx5$oiqOkB~J(ZlC8hq#!
zo>{pE{T5Lav@7I+>J&SdS&KItq{HH^-*P4Kol!MeZFn)M3Of=U>=s4z=I$trd9dxu
z4Y?zY)OTi0@JDD>Z=57z0wJf|<}*p^Wo#)+#mcg#Yk2I<QtC;{JhXUao&hlB7RTia
zgDN{`Mj-cL^T&_L9Um?V+8yF}kjhhm-<rWHP%Qh0aceA;TD<@qN)+e`sY0BLzCkbf
za{o&)F9fyt-NMiF)BB(G)4UD{{qPT}#w9-~!(3HpuHogYHZ6<n45UP^Sr>bZ)sE~2
z9bg5-7U5Ll`sgX5>I_Vnrd+LI^8p7U1pUV<#)@m!a!`9YRSTPRB<2=mPhh(GC)h5@
zpr7M28cvg8qS=5Z?HEevPZJX$4kDJ?#SFF4D`Zy)5}?XKaB@Y7Do5v97tJ;?9gOGQ
z)rZB-0`Y*c>V~}0OGv<tCb>kA&*DW665A0u$cVBgv#vL2w_bz}9gol1Y7~Aty17h2
z59zu&A_(vu?%0p=A12;yNUNZoL9{{?8ix~J;74e_xWpU;tMi<$#cnKR#nX{0*2>Gs
zr&PqKEi(;2o=PokK_HBgm^@tR2^2&{dO4P$AV@;I?S65JmJ|_<v3R^c{}M0@m4QB>
z`SU!vzL>PDA<!RGbjt=QKg(8^C)giy;#a%{)=v1$Og2;w({@-}9cPWQtjHh8-eV_c
zc~h!E{+JoBLVI0b#^JW>j5%7DfO$13frkevsGE5QXuT362HN^wGK}rih49gY*C2qK
z5HnnMt=U7EhQ1rWvm=}5>D7*DL3(B%Ev=Tf7)}d5<@2fZqo{ZB_EVPr;WBX|$_)PA
zv-{GlJcRGNA)8pg+wNWb#mqOFdzwRTjyZ{=ly=z&CE~P5VIxxqcu(#R^yp4D+Jj<t
z0H^TW@8^1wTDyu|9Y`RmKEU&9)s{*pZs+??+`M8(zTh+7CH3*dT2NUMW0~g7>3g(E
z_{n1fe)67Yruk+F9FFa0zt0`u$kcSIVR4f%A&<8AGr~WVcp`g3h?dLQz44slxZnoY
zuPt1gdm@Ik0N54{m3I54Ycn>V)&`wIA4P=N>TXW4Dw)=t`PWF+541*@{C>IKjsd&n
ze_8Z3_uOjJdj>WM+w_Sn@#o)RN2mU6(zc(wsrdE$*}@(_+enZ8`QO>_>T{|4rS%I6
zJO5#C4?R6=_O5e^m*@Y3FVdm2!6lvzlI$z1@8C#AG}H>L^YqccmK~{*iw}*m-#WL)
zAKX`U=8Q`Nr5dNlg&}LSKafH`^zn%WHs!k6sxo9wNku`qM_z_Q|J+`46NcHMVp#U9
z`mwlwcZN<$X6uO`3=FnN)SreUbt;3Xt0<Lfk{ncQF{8aWQEX97kN(p`xt;&Ux@j$5
zXxSU)d1(D-6!x3{JoW#)+J&GLyTesa!s3@_$<LL+X4(mlz{ovs28;o662?xB$Vd;a
zxn{}Yle~p}>hCO%%bybY=})@H{qM4^RGPwUwZ&tX2PuTlFHsGCXNZ%zkn+Ui?7;vf
z6n8E6r4Ut9_b11%3p)QlZS7C;*k0>SYXC7_%vrgq8OMNKFIOamRyXV2x)rf51tRRk
zj}=+CJ)f(n)CJDB$xu3GtCkyQ>`Sx+67}<Ftxs-$8RRzDigpzd&FG3%ELCq~htdDd
zDtq9|Gs$e>)3)6!-xU_h3%y)DA=n2``D79@?RRi;02>4JXvDna4Y%1(DJQP|c5>og
zm4@*9Xz=XM!uB`ZN_ra`ILO;@`5S2J%zm3B5mX9qg}(oDz*2Rd$(g64`m^wjMd}YI
zi;pA=J;hRO23qOSbFv{mzDdKG!0)&#ysFvJp>akX7X7<j{A870rKxvYp9iWRkXnH`
zlb;cau$8vPg1|&oA0kR$m$tft0@UE^%Fw0YHWPrGM|pJ^!xm3K77%rTxlQB`j^3{~
za5Ax-uF#74u<`ciA{CROjs3B6%Nly0uM4UzC6RKA@fVPQB1YuVO57mfC#eU8-IWA&
zF8QJZ*W*+g)fz1&_J(;-rUva2rs$fm3rZoyR4zGQG=!z3sFs$Uh0sYpBb5vIm<!Go
zp8YQRkrf9@@Ys)9txCzLtuUq!EI=3SzPgE`l9%*=i`RH5*a57Nn5F2HQjT0`OC-pn
zf>4!PBGW!5h-D#`2-Fi=4L=o;N?kQR16sONIk5%hEg@tXCdRjN5_YUi2bGLUsI4LD
zzrf)@S#(t7tWuKK5s6WP%Fk;0^sLCIt}0*a0ZO*O<wov-|Je=vrkp81ZGvsf(+gI?
z4z-aQkMj0dVoEd?f=W2IQ+UW|W$TM~mkFq9++GG<8ZZSk&`;Xjdjf1hgm*@A&1Ct3
z_-u(&5J3%L9;VaWVG_4fRhu^?sl@Y2Npck}jRcqE=m{^6w7gJLTZB>`sx%s&NEE-9
zGU!gm=9xzdA|^5zz{Kmd_!I$n%_}9TB=gqxgd&)&W`SM<M@pzu$lgc`M=y|M^B_4P
z(#u=!<%*!3wna3Cn{?0%K9tnTqYFcB<uoQyQtBw;0aA05CK>dhW%UnjVeulj1&xKt
zb9Eh%I8p6NwHv@ze7pn|+h&bCz`ZI=qNN;Wb|^NYV^a~9B#UX~sYEuum{7#tPGP$M
zD?agC(IN0zRT6Nfi?EwELZ$%GaE&RwjX#<NJeCDZTmv=(&ZCeKM5a|%3h_`|=_LA0
zT^fO0Nv<JBzhy{92i*rCnb4;~8|4BQI%TbbgIGz9zQOb`KN2%v$Lx3;mX16k`!vxv
z98XXY1$!9oqdZq)vFMMsRQSL^JFS?w#c`n$qGyOJ)>J#ucy>g&>Itxwe6Z#Fn9%2l
z^q@r0pi^6rJXORAMnhtoWoFJ*C{^n%;l{=zL8`GyAH}+cmZch<PPwKUbpQvj&f_+y
z8^4;Gy2h}tSQpzpJ{!E6>I-VHa{>o+(xduD%Mu29`8o|Mq8v1vS!3r_av<y-K4Dp_
zOr2ILY<%4eDwf432jq8#HS?iCPY*2zE$M$kb+-c=Hw1Y^YDSLTfxH1umxLecuAej&
z1&2Q<VoUqzGHDTmQq^+F0Y5|g{j-hob=W#32SmZi(TR{ddL%<BPlu!2QL>gCDwo~C
zCoLfeQCaZ(A}ww$xdq*b%G<rdGb5KS5F*JopsSjVpcn7jO7i*X6&p)R%6U;B;R3&Q
zb+bv_j$eeX<f0uEl*M|3Lv48lo?fAGAQ>HfTwD|s9f>+h4!UMJYf}~DDyI&8Mm-iz
z@ql{3E#T#=h;0dffyXN(=u**^tL7e^-3$GX+?%kfDF1@c&YVF|%!UkJULeHl-{X>r
zh*U5}jc!ZtoIBJTW<VLBKbl4YuWZzZMz)o7fJf;xPimiJV>~RJo^gE9hZyXHBAQoC
z@?M2dI5E-1O4$o$(5B3lGbHyK1Dvi>v~?T6PekemQkW3X<Nybl=&|kjGgYPP$t85u
z=_=NhZ|AFymT-!OK`c%$4<NJ6$-#1}A`;9dUv>H&)WEX_r3#N63%By%KuRk@s6r>@
zQ8a_h$fGU1p3sOH>tt;PS|QRAdm!j8LXKa*;I%6hDKvP9pJ(@Sx1gpw{nBFW{0`%e
zPq2`*h3$CnF|b7-I=Rq;Ps`Ic6tMkqwN+mysh$De4>ekyv72J})Z~mTjyjJ>Mw<pm
zI^rc|GU&CK(jQ1*w;8p>L*m3HhzQYD<)lr77!}3bITl<?f;N2nE$}`1I8qVmjXIVt
z+k^Syekia}rFxR8FJI!9W)NJ&(F-J%cm*>TZ<lPSrB*w^{X=5=(=N7L<ZBBcS31p7
zNi4q@qmrN*-AJ``WDAf$|8o#isyH`54K!?c#TO=bZt!QE8KWhsWGUoeX1G6qmhWQ9
z6?4GxSU5-MmSS}781&+d^o0_V%4R0dD;3}2e4oT5^^y>|EBt&XPdl-A4|L~_B)x&;
z>NL(5?j-s58%bV^dyRLd%Nsp2S(_p@P_}XXWW%xcP)9tm3E`v<^5verY1vnkG;dLZ
zB0SXa7QQ=}*@^#D=qPnp1@}7%U14)A8-cgu80D_lL6_&#_FtF6!1T)&Sqf5CffGMT
zC;LMjr;}KrZ1IZ&7OR6k^JU-Vw>p*A$ar>xFjDa8$_<Q2aD51i8}*0V0}8y5qI>}D
z`gifsulpF7&yHa?-aO%0q{_$6HhgpKznK@?Z2lZdlQij57q3jTIaAFa9pQ-qggflF
z;}=78qIN%k_`&S;Wb2RVzC&EdsM1xN#Lf-LvHc7^?&yaYIMW|+6Ml`oO419PvJ$1!
z1q#7)Pxt*HFSf0-twZmxNu3X_9a!SbdT-^ifuMz)Y?@G8e22yDd~){$^jV7SxlD)W
z#aSN{Xqn*PyPZAr<wnNYsK`Tbdv<_f`R`|mX4|7=Z~5ssXUO|qgOuoVlWDn-s*3l7
zX8VzOmNlphPPjEWmMfa8c0Dcaj%<m8I1)GWEJpe*dx8yLX~k`Bz#eK~N}-U_pFNcM
z-#av4tUh;Fc)WE(@z9OGn<rBxt@F2sg5|f{5*(bp?dF_Zv3zrSs;5*DA#i<k_#@uj
z{9&_SxO^j3)Wg|W>eQq@JLCx}!`LP3<Pe?y1AT%K&`O3DB|Z{0sdbB&{yB@2zQK$H
z+R#S8xHh-;&^t_vFH(Q=>3h%5X}i_qH<H=q;$Yjl^>)^0;mjV`h^j4ofr$J0C`h+z
zEqmg^4Ht!>*ZiA$Xf=EZPyQhc>njeMJN?1LTCdU9J^BFuFK@8?e1@+=fBKm{F_l_?
zr&hDukT-AE=!Rc;Hl+UXhPR=wI4i#0uuuK%kI~Kl&0NaYBZJ-fK?^UxJ+tf1-c65r
z4P*CjvT6C~dDeX33QL?J?*wPqkgH`sK9rKfp712>sJy7M`K4O_oit%jP>=ZHK%2Sa
z!mT>uf`t>oFdrMJj&ivT9}%v69UC9MTX%wbL*pO@cQ(N5!krUZc%yAkL812vVw)VT
z3M15Pd4hNs<@wIVH5sgWN|=uLO&I_Gv_j7e4Fu+)i`%qOtVuT~G5dlq59BYuXN<}x
z@OziyIR0fe7IO9{xpVwrxC*;lhs@k{Mz6__f_BH!2|m0Frux&{%ux+jhV0K6e?MoL
zEnn*N%1YosuI9CCS4Gmz@z3l@_mC@Q;?DJ?>Ins(7pC}I{Koc84Y86`J#UmyE?><f
z$lEWJr0WbkePyo1q=oEnK?bvu>}-JFaMo6442WZwji}vSo@fRpTVS&5gQXzEE0;*R
zE)Huu$HT!_IHf0gNtd1wzz7sp2QuwrX_?ciRfDIfkFA(kuX9Pg^hx1)bt#N}?7>P3
zJg#A_B|=vMS{It*w;`;8W-`c$m!f+@2T56q+3HH^Xl%v|)Qf`>^r1m6qx=OjG>sc3
zNy#0tLYy=T)Si4eI5Ber4X-#$ria6I>UJv_x4C)FT<aTr{hD-~H!Q?fRzXSUl@I#j
z$8oO)E`ldp@u}kE7Ic(Q`RH8;@?AxALbttdV6i&mjcP^SaFEsGFkv^t)LVGWC~a_N
z_n^`kymtyEWqvTY*9>&FZ1Lf;Df*I$*q<Q0`xJyUK~Y>GO9`E2d7!dv@D$l?A<05l
zkq(TFBoYM?75F0HL*TYzr?x4PIDE)dNzMFAxRjb{?tt`A!C<LQsv6-3?$1}Z;<g8g
z{cf@49zM%Y0le><wP4%At*L_uuD<*F&ey6yVI;MY_oZ&s?vCoH;O9U6%Q{gu6Qya|
z;Gc;)JmzL7Dq{7)&dhFQX}j6*6MCVq@yAdZ%tFE-c_?jzQz-A=Y&Plulp9L|=2arf
zS}&mRCgbB~IbsHzi}#JB^Svl+AHPAM8{hPDMlsoq7kfdP#WoNWregPU{5`;X5?7`Q
zTHS!K;f$_;s$3oznb3sBrkn!L?N+vkvh4-ydt$g#UpjS=JfV9xw}J{VTZ2*#ClD4~
zz^`!sJ6B4o2-4CS7*U8>xYe9Pko3tRyNRX=3|bm=2VAMEazPK!8_19O3eAHb3Ooon
zLC|acy8XqSRb2nqlM@Shxi2UisjV|rh@-rb%Xju3l|ZT8jBsC_D3YK&DrD_Erhx_S
zKgAoy-lCtZzpW7o)WJL6H283QLIdh*Jg^mnahtZU@Vp};#E=+Tv2Aq%a{D-sy~%XK
z%J&CY&)wgN>3#PvotwsNZEwaLd?K^d&*a`dusp??dqqC*z<J4)XHi7*teY8Xjudn2
z7xUD8igWARpUz*~{3AP-oEZoO`<yN=|H)gNJ;m9WrdQp5kOa+Vq))zywXk)*U&ng_
z<~MWO$qk}sD<{~b2n(K$0=4rmv-L!iwLuk3rz-A5r5hec_iNY2I(0<$qf#H^EQy1>
z*y!P47%<Hv>y7!P^3tmM=?x-{EsCdk5sB4DN{A4SEsbpD?+wW3*qgQ(%e6LJ!|z-(
zlpg#<n}~D$L<$j@7*-E`1)DFNsKPm2`9zj4tn9PFN8g{?(KX2kI9+y!v|Ob2etXnX
zCq(5Gz&goJr&G4F{~GhZ$qQ6=<XH>h*()=*j9t-wnnk~l{ff0;`Z2SwJ-E;2{`634
zN4}R&-2451mfN?d*uGX?Pz-PmjbHi2EO?dUwMUDkQFc|X%wAmSEOOfU(hSes%@gR&
zsekYX7iabhn<jQP>462xok?to$v=H1(+f{7vZDp{U}*)SWwyF_rV5^E71!zKQhk3j
zzFOvw{K!}JChka#Y&mR)&tC9F)Hjo&A5a~P+f!ldYO^(dW^zB8jP-^&6;)2}MXr;#
zC3%)7ysbS)!mmlPZ%uN-!(oN@glYdT5A3z`ITS!cf>7b-XXdD3aPYr#D9!aH4g11#
zyzYCt!BjI_ffaJ^`W|Mpu35EX-$=6I|LcGc`6p9*WO39k`O!g+NdF?#%00F;b_-<;
zf$H-ycbG2&R8%>8fd|3;=6D)@k1UqZ+Wfc+u>!8u`&N39B0kvKFHQvePU_TmbnQpX
zrs_;iktiF+4nG%n2<rT+oUb26K9;U4UUdjVHid2H*wPrh>!loq_iYtQR-3K41aJR3
zS~y9B-lqdXyw(>V?`yy4`Pz`Tv9m9sc$PtFvR>7X^6blO2DvBOLX;W8?15AHGW&cF
zmRd=N(C<34w~vlknc|?HWzYV$x%TB`@~C~z{sPI$_j{KFGk0>3>(3FgmW1(~8CKH_
z7&<!-!~Qc?VhmTxB7A4aVpQ|PRO5s(1B%!N9FM5JVMh6oFkKj>(@W``;&umLcf8$L
zp}KY@2U@QL2rg*ypYK_9@%nLer6;ujNdPSp0^4kXjNvmdDTJa2G<ry5Dpkv#pqfI?
zwt&NTPil8^8y{uIvM87OY5@IpEs!M)X@S@h=eRG@Q*-{g9aiY*r|9O;*_@}tovX3{
zks))>XC>?%0Ld1JVzSI9G1&{!ZYiQ2sC0u%2G+@78Dc<S_lg{lTzHxybGSn_>}Om<
zY4Qi#Mk|SVrlSx>4dWe0KX)%Pf3QkkgiRElwiU^re}-$7zs=+lc}jkn>;YzixW}_q
zYGo4C15z)9rY>Drl`GXzhjwejujrv$oKHr%Gatn#v}V|UC^f5|=L_)4LUO_p5N0IN
zDC1~PsL!a10|dl;1x2M{<Prt+33W}b_63qgOaVx_=zvLo&_Wta@~XLd91;d)l`R{d
zm0JUQRO~`f?G-G>V7WRWa&sP0eJZ4Uy}${f;dMo7{%R;bghQF=@=!!Nv*l4!<8qte
zht-h<OOSbYa6}{Uf@rDcD8Y2CH`O8jLWqUAX!%5m;nI}dNtb}d6^5p7HFF71O4(mU
ziHG#XYoJ+m8pEWAXr*|rqQ%h(@rG+Ra9}H*RFk@AP=ZNbg({?ywsO6wYs_CIU`!|B
zmH7w(LoRc2(pQM1d43Txu0bJk#3<c+fd`>Yqv>+!I*5=?L~#o&Hn(`?0Z(mcEOoep
zLVAN&MTj4~51WyhTY_5kMrSgoeHa3&dlpoFrFFq2pQnr+epq`iM-&#t1Yec4o+A7x
z8^F1E>vfr`5HipBmC70<f!j#*7me#Q*5Nq9jj-Kaw^@tPNi38rb=nIxGr?>P>3^=t
zh6{t)kA~(aTZ4W+%DT2#kxWB%`uj9Tlo+F>WK*@+ohdWsX~<Ux->TwE!*?TDC3&Tt
zWMARrxlxnq)=Pz&eLz~TVYZbj895)D2`qai=eRtX>%{JQ_peH)%ZvD6?j|hp&N4%>
zFQ4c2#sS<bd)#!;VEGLCXpXE5h0FLB3(L>vJ-m-|Pu}OI!nZ~;^RJ`%2hi3M^KEE0
z&U5$UMTaaE53Wx-H?z6EDry%P4xcCG<1aV!uU_clWw=hX_XHN$7PTf6v)+x}&fy8n
ze<2tjI*gBZ$7wH1LOizLjr_~olO!VOw2bEcX}LUefj2Sfn60*4?$H!@4Dr<qQFwZS
z2ZPgS!rC(xTN{7!*Ia6zn!&{L9rTk=++96nRF;9CefrJLJ2_Ma7oK3%MxH@Foz7~j
ztu{G;Kmof#W(%0DnSFQE5;dm<(E=#GaGLV5;Xg9pDp`yDslQz*m%=54ILjY+dQX^n
z?Cs1eA({WtFZ<+&zhToaS>wHeV>c9I=UkbikXhUJ+Z5~5e{8{nB~yP!FP+^rb5BSk
zm)$O?Fc81@`rk>cwZh}%u~%=PEBW{r2J<#_Q!xET)DA8(=c9GX@-)x>@JdNeeuJ(=
z#DU*41BYyYi0O`zTHf^Rz6H}zaP2-mDXvmS{dxH(d!~`74}h)CW3_4KFc@u<mi2mW
z`f<1|-ShWZF{sVf;0Y}L)yF}_5%{%-*QiK1@@x6L%;|4c3kE$oqh4ROXhg3cwoi3v
zL4_J7U7gDpr&t6mzL(ij4Dp9u^XoTLqrbOgr#`c1F@4|~SBR}Orp+Jxm{0t(2MYW5
zFR_{NFQyr$ei$A8+(eWtT#P{t6<^xjO0hd2*)txLG^+BO^iU;M@@8<K@NToe4>tmA
z^w?yq3yKgN|KE5FDq=l)xqKk6>P-4AX46{KbHLfc|Iga{z*$yQ_r7cIv-|Y!o@QqE
z&;tz)P~9}xAb$@3yrUAR?rF3kBp%49#9(qDe7F-$@+L+J#wgWIgAF0t5RyB|i@66v
z%t(liUgIN%=mAMSByVEo`9Z_=<Gru1k821)KOH|NP6)#L{%W7o-2*dy4)?v)efF+D
zt5&UAwW@Zls@k<*#!C!7^2O`b=Mb&aSXHapI?Pro=xRgHcv=B2UU!uzghw~r!~+I-
zg`YR&jBmT8gsY;uL9iMqqb0+gLD&dJvkz8HCJt_%o*sK}*z3@nQB2`r&wUj9GgF_}
zhppcH-$I(iECx}`_ggc3H!Rt~(|8cPhhR*7@j;uVKUwOZ-VBv{l3+`H3h4zhL|Ki8
z4KA1Yv=e#BNW)rVfYvJnA<pUI`61I1Tw731L*bM$U}Rcx>?PF=b)?_mRxGMGKt^Ts
z2+mxYm6A5_tOLjd9loJQR2y(8r-&E0>lc9;cfX3&2|VhZacm!SLy4dqBKY9ac<{gT
zo`B0S9gU}V(m+*2y=K%5{a>SbO_?UMX#_&ujxQhuOn@*cCZ-^*h1LkJ<Ctv+Y<QEp
zwIS%9i{2_E6_?Ht5>`VtbYzFehV{vai)Bd9vosf?9}4ZfDjZ=%K#;z#WzXW}m8+5>
z`se_)89FyKGi~D5Gc|Q>^cG8$a*v@Ut7Y>IsSx1#A?uQ}5os9yA~pvFZwP)hmOMKE
z!-1bfAFjYUnX(qA{$reKtYq(vXi)*ZJq`~lttZRm&cwC!Y!1<nqo&q03QFXo#=|Y)
zNH!40nA#y~Bk)Yqi8A8MIDB0j8p@uklSnK^a52ZWXM-C811e2XjU2|iE)B~{YA4`%
zR3Y?T8XVeEJCl%B<7g4xQZUfDm%gso3XMWYp~Uo<ldgfntC~W|(Hc!JZaNv1oG~ZT
zYJn>mc<Uy-s1RQBvsn<G&g@BBACjm|BD^(NJ~1RS_CmYT?k0sF3UgT_G8&Xm)p5zw
ztmW7rSiNi?&-=*QG*XM)jG99~fGoJ6dpCgIG{Q*ZQvx1J?dYVE_O|$e)eA66651q8
zyaLz((2;D6yQ<MaK@Q%R9@hzbRd=x+Az(`YXsIC3a3pVkM)bBXVj^(y^0%u%&Ipd3
zx)F+jP&$r&E#KiT<}pgyQ);VaRtAvId8L1DNCKROpTH(zx?y}oi^+0Y?Lu?uOcH`a
zEBI0WM1fccO)RQr2u}jn2+j6=qZ`~XnpWa*+Rc8uALO#615kSe0WJ5@_60Y_jwL#e
zdU1-m5so=sCCZmUQ4BNYwC$^<lUKh`$p;3S);PVrcXc@lr-8s$l+6-DS?&T`SK#Ay
zql@cAy5q`jHa!r9Va<;Rv%mM5wSLt8po3(cMP8P4-Bk+pqw2Qh*yhas4kPKHo|xT0
zbG$7Uh3xtgvy+5QsHkO4D(HIWWPvv9&f$r(_8p(;Km#|(K?8329A^oZcJj<l64%)s
z6X4-sfA*liAaL5uud_lt6b5V@IkqZc>(WI_`uv7ZFk7jaE&xW6jq&jQGsotrp#h!O
z0A#2Q*Gm#vlyR`po7qaDpt1b&{=wlW;NnoJBy(Fb+x}rY-Gd<$EZf1h+4;D~l-}8`
z+-hEkt-0ep+w~~Bep;eMHl=<Lupvmx`3Q$|6se}&n2GtNTNx0a^>b9$awWEssIsBG
z$eX(rLJ_n-<3R9U)CWg%+xrh}{rg8YvMQh(gooe4KE^j8Cp8CX2}l{{RpoELG%VIu
zrXHQX<~zn}E93g1mC3aE-x53ZAJ5GukyPSe>JR_1S`6#>knH|L$LI44|CU+pT1d$r
zyYt;*{<UUbekZRDv5GrayUV&)D@-gsG31gV=C7K~#QLs7i%JQsmqUMW2)8G4vQF8|
z%`kHgduAY-t+uGu)_XtS7v~)cMX;hCrV(~sM0dRK8l6{931rd`;v`coH%4l>yMj};
z_dQQN&7C<dWe~*G*3bR<Ks-}LLLVW*c}0;)thj(XKkzz&aoA6sloZ!ITJautn}&jq
z3i)%pHu=H+KP|i%UgW2mo%L)>NYY?`aA|Q~{d;{D9(plPJuz8&byjG#m1!61ct>XM
zf9X84f8LVJoVCZl`MM|2e$Fy7j>wJ0pS=C^mN?`xAeo^Ch30vBg4hjdzx8jv#6*{}
zdj%{f8fy0d%p=4_)#N)n1811{X{^&YkkD#tKzK4Nix!;uHx0OKrK2i8XI?37?$DA1
zUW!z!t%FQkb_cTc5pl+)rn6Mqpw-qoG(vh~-0$Vp@I_w`;+2c5G*4@m9#^x>_hr8H
zb-9LwaZMPWH-F6GI#Ab0Fn@Din;C-AnGR#`Gm)0lYjgFu?;6fH{{^Z13#EPLr@VPK
z`-FYT-XeFk&_PMV>!dGe3o=VETP-=zo5ICZ@r~-%rMSs%J?Kf7aS)APA9!?k6j@|s
z0SW4{kDQ|<B~Tyg9bw{KpHa(2nz{xhmjeXdmgMXL?V1W@T`8*$cpS~>3GvEBj#sqA
zRc453fS|`+H*irjbW4zH3c1YK<C^AoD}(wa3?|A}x8-69CT9ue<7%zR25fkQgNVZA
zfp&WaX~!I95RAn47=$Ts(~*&(XnA=tp2o*y8Qb+5nCpt>M*4~(=S*|>t_0R0Fvjy3
ze}qt!KvRNbpqBFD_HtaeRd0x~r7~6_Xq-J9lP@NrGDjL2p*mYKd18utQ=aY+KnbD~
zXAdJj9Ys*Kc%0+X<QJoz9P6NPZI4iWX|}G5KB`k6vrikW%uyQ@F+#j8VK}RD=gVLW
z1T_#eX2GV^o19>Y&&<1w;T2s3PhKeGti+MpTLvv&r()CuDk0$T10_Ep)@k>O4Oy8=
zwlYv|$&ssskSwv!5qAT5w8J*ONwBnUfeyFOcRJVL#5HHx4rA^?p}4}rdRztemL-T2
zyKOYSQd?IR%6^t#2fQTNflLJz;Zl;prLLTUaczvf<vq%y9dzVdvZQd%46T|n$f;w&
zL0zb``!3`jYXF(d-OoTnZ4nVS5)MTRq$zwK%xZGb@$Und2DnnIKuScyM-Y{!s90LB
zLv?*Y2tNvV&S5J{sq9tOqeHcOIh9yg!zGoiPAtKkFa0mOI{XxZNnimkJB^<TIm^#0
zcw>%0SOu_^U@UO){Gv~H0p`ERmmpyYg7DkHDSI!QlC8pCMXsIl#blF83zQi+HU^h|
zA7i6iE|uvD^TLz**W$|uNGe0U8UzEeWn1tMbli?}XTTp?D@DZH;DVLh=tOr)Y!=!<
z`L(Zw)VZ+p)l)lIN54Cw(wmdkiEPTXrH|t~z_%ny{IZ5xJAL$LD<y|n_##DHmH<|;
zMFIon<l-#Y@@ZDSphbjau^~9ces#<S9^QgAc5>N;E1TApZmR}qBfA-RG2jS7%)&dE
zF1Y|HDcdFy=?_q@ec0{s=(K(FEv0R@SzJd0Hj&206K-kuPPWrTF*!i`C$-k_NMAec
zQ#|4LWWDfQQa{FfpB2;T`!^N#%&CPJQp(Q6Bnx?ctd@WUUhCv|yz!FNj$I7PCn2v7
z={ZhJyl!+!`MQMtAtgJL&Y*Q!2Q@{R;!2#oS5wgpuKh_L_MO-b?}5)cX8M+eO}~C&
zj@8yh(04+_sUBrNYM!I~lmz#&yCxT~dgf5#L!6a>ML8o&C0fgEv(<yv9kzeS(r21!
zo~B=l57VF|Sbih<ujSctb7x_XT^sbg56xD;C9L8NpSD7;5)Fr|%pQOK)YRsQFT#AR
z{zyPXjt;V6Nbp@Oh|`5N_mfd~`MRS$;g7%5RWI>n9lYVWbYk8X*tyN);*(De<oVd3
z-NkW5;|HGaFZ-q1ivu=4HNxjKc4#OCpVysecmK}v9X5qYGxqE)&hGt6Ifv&Jy&+W6
zJT&^9JwUZO=94Um=w(Zi__2U}v>&ya*%cfZAN}H(@d|6x=FZVnK-6bhX(ONiVrXg`
zuawbk-(4gg>}a+|VZ<e6Li9z7g7so{amj2|NH=gGpbXP)?`51=yCrDqL=gDTM4@rR
zunnqc$9&x~uK<;;wlbd0{~j$sD2`vcbFu8Lr}1<Ll-~>MUvGg{@C#pU#ZIzs=;xSM
zdiHhMjg?c%f#cjsHx*&_bE!9FORr$Rbyb%6?9bD**_yKooUv|%(%W%KGFZzqJ;WZZ
zon|9LpGxe3UBe-?KO!14R6#ZdvT2=P8L+GWg@u9@4x0Fk=EBxPr?V<&pVr45!L4V4
ze<S1h8*#k5GW@yLMWu!;V?TybreTP{_#)RI>UtQQY}4|mjVdL-*!ILjN)N+0nkPPr
zwisJS`n<N&@)4$0)Uq3V*Ki;toO$q~_!aUP>%!}~f5oO~t8JJpvLI(q%H)}r6SA%J
zPq7z?hvOcdCBTsB{Y*eG)R)!R;O5QVL}&O;ABdEX-z1mCGg)(ce_vgpf<_2dyv`o5
z?J?0)o3c7b>kKBB(bd=k{<ENXezDu*esq8{vj?-NK+N^{NxNq1Fl;*M0L^)GhXrrw
zDJQ@|iSM%dvR-xAi-(d;)wuXEE>U*G`e{57?nn_uYK4nFMii-VN?#1x=(5Db4nv?#
z=E5e5k6YkG!CR0!lA1kV4zdj%Q9mG$(*>AlH=5G-YOe8_=Q&Y8g=KtZ&D3=KY>~Fw
zWQc^1jBMpV4=3jItwK7<8A(OV2#%$lhIaWO1aITUQt_QUnVsSx&@-e;-vQs2NA!DL
zqaphQ!_zc|b-A?6?x0A%TnkGAZf4Sr<J~mf)FIJK>h9i7P9Bnj`$}uUGKUYyYRKv!
zj?hz4o&qy5KU1qIF|uu!sfF94oOJ~<npx8(^OzL5n)Uh&nnH8@JObVrLZ>jL5i?eH
zL!?QTyyc-t8?=W`8Dk!ir%rBI)6TU(r+12TFkuE{2Rp%lA)RB2{&_DS`{|>_5)*f~
zTFb)o4iJUp+W_oDU#(*)o)6_iT9lPzH;4tzod$dn^tBLP1I&h?q=1;62=j{pIC;i!
zHIjNq0jF^nLD33s^qwu)dXBU2B6#k~1wh+X-<^vbf|#Y6_fUwaJb^<@0vj-*3%qO$
z4Uq<F<t<(V>4ROPGI^*AYKgU|otPtgzio~%1d`Yd<eXK44WsV%+m??st<@(t6e1)L
z!!I%?*cj|Zvlm}UxI{YAwNVOMQGs6)_bkY_9v~hI86s!vV~*_hi<3mSGO}6TeCqU&
zbNoENOhPZ8dbX{FJJyIz;fUo@NX(Xdkf#@jI)fS(bHb*Dib4w0rS7gL5lT<2dXJQZ
z>E_8Rj$F)_(XZ;7XD#8kW#kPaDgH#+4{|?4r7uHvED%veoax=vdIo#R6@;(~S3&`r
zm$TWv%WeM?Er<+9-^Q2BlQKAvAU^6OfWwn6m%`8O<~VRAegg=^P1PwId%^AxzvC`s
z*)@`ThN+**jqQ|ilQ5>8j%0F%HDk+DTvjYp7-L8-p&Tu3v1{4;E1lgKf>H>`*6h;M
zvXxc&Vn!Ehs$vHsUU|u%Oc3>e?N5I`ceYe<thR>Lc(JrG<ndun5iSPrXXh9wmJl9z
zZ9X|e2L*YaNC=?sp`<yvm|5X3txOKpUq^4I8v0?zu|mhXfDu;M^BK>LtqTv3#3#RB
zaW2gAPWsv7sV4ci(qBhjMX{?qs6yY@d@ZQ@*g#y5=i`NVBV<q*lW9j>!nYamcL8a|
z<v+OGX7_HI2-qpD+9OfH!lP$S+u$!-)l&giX^-QvoYlmB$?Sol_tc}2+E*OPoIb;0
z%Ele&%O~glGdji&N>SYqgn*_`Oz+*4*+(uaFpBfQ+=3Wi>ex+#l1B0EG$E#}^y}|_
zOKx|Q-Q>Rp`<rKZk@@TIit24b=`K8|&x=&{;oQbQgZ2?17=6L4_2jwb$gz3n7+Z<H
zo?CcxY7ZQ^#WnUkMFW{T+52C3DY)qu`V*IKv$^7>;kmh~kwQ}5+Wfl#bEgjGVf4S-
z9>08iNZ+y_nKjENVk_pd(IxSIVfiCDZzntZgxzNQ=FWAod3kDF1!FoP7Si5+3)5@8
z0QTc(+{}I7xt48zU*8_|A}C>;W#E1W69C!CyNc6TIrLglxB9*byQU+4WjmmX3jAUn
z>)sXmF2TN7uGs!t2jTtKB7V7EOCiKh=k-wYiX)RmwsH9Rt!4`sJ8SGqW;ml^B6e0n
zsS2$NkOcU_&rDnGP(IaaWfGa4{bHZHp}A?Hf!Ugl2I@I~N2PV;*KrY_Yei*m(U<#A
zTpH3wE7?{{KFWG3eNC(ApS3sBW7L+dm`~_Q7yglP)q$jCAINR+3Cv?p;_g5;URdAz
zpr!RNTW_`c<xR|$su$uGQw4=<Vu9uC0$UhEutc8TlRm(rYE%-2ZeFjcMs-eG74M?i
zdVs2<+f9s`*PLGy%I+1^Um5ZW6a{Em_B*!89^NuH2(3(E%jGK+9)9X%ONeIlR^ein
zOupja?Gj7bx{K6D%bjzp7#lj0wvbm&v1&MuVbGqF0ttM$(4`CCV4OnP%uSA+-wGEY
z!1t8I$OfQC&h}ke%-Z{tkUn@TG7tpx;^1k?WO(DT&gSm5)0TgmJoNCo80B0>ON13g
zD#y{GM5(;cUoTt6auUjx9&N0(bl|P^&TGN1bg7-epJwb)6Kg~!#I)q>_(eb>sh5}u
z3%g+5%NgKW!-c~c@1Ycturf$eEoiq>h-Z-%xXv#Q3QHzC-TP!*stcB;wtX5oylQY|
z3Tmp%&(Q+_agxM>iyoD26~rpNZQ&hdCXGw4Qd~K7<LQJr0{*~IE7RmHD8ZB{(kEbJ
zaAjT$|7w~oa7x<AUR12k+EFBNaCLCKF-2?f6*SLqNN6D>aRRso&G2|!mLc>w#+!>t
z;c+HuLsw(a-(r#mcLb7^Fe@^VR6F2kH{ViB6;d_c{OvTO((=RLuC~*O@OIoTW+k=K
zxZCpsA_E~hd%Z;2Tvx8E@E~lnN+zC<rB5_$vX*FCVyS$duThN)z>kx$1GRuVALE#J
zNC(l4f|d7R)?|R7!eauR4wX5akY)`Ladv^!gXvgNE!2Sa=W#8)Oe3Cy=)5Xu(B9&k
z4x|bxkJ(P@M#rK1<Lf-(UOZ<jAeZ<{9hVnq@Iz(00wT=a1Zah7P2l4-UP@=XBtA}#
zmb%)+=nvkUjjjqRv^o<Rt3hjoUg;816p2xZOTrKpz#M6d%&RKNdBO)HZ_y?)8Xh`y
z1r=5EWIGsgPW~d4c;kpoq*b5|N!2nN*W>6IOSr~K=8Du{T&TT6$$kb)K+NW4X%Cb0
z%i@mYO>JUbuqd|Ley6)Mg(9tuNtP5EA+kdBEIuAqFRS7b=cw1%dz&MEvcy5D)&Xi;
zf?F48`|<d)hbqc>sl*o6BW&m<Wz@QK7j@%0s-zODe5U+Wis%`QtT8fY9Fas`XvdO;
zAn}aj>0}}lPm*AokZJCYyVG2i{(1+O=;Jy-ysS@`+9PQ#zKl!gHFk5>Bi$Fg%WJ$V
z7Dp%h7y|(8_Z{RVQzthkThd(}kkdlE#$``jD11L`JmM4@%0Up>_5um3!FOi0V-dtp
zBhCZyA(u0ZQnRFe9P35J@ni4MJM7JNF_?EJ>7W~+Sgf|%o}K2o(JFlJ@)L8pJ<G)0
z3;lPq3>fe?vja3sb|QPbIJv?04#3Yt92&wPsn27urdJ&khMlD&>8}*lM}ovIva$3<
z4JuDVHMSK{EyA=vSxqe&Voi7JS+(|}0_eR!;>P?%84Z8llI1Z{d`$24LmXX`K{CF=
z11PcJF&S!#=nC7vZez21E19L2CgJK&yO^N;y+`NeliAv_A2kPr*?Mdoz4$v@3>`am
z5DRP=?Jp=rcbGZ*L)Ii)%hFRgbNAaZMKZS~)vS@jlH#}&N<}5dRmPx9PJeui!)7$j
zxr*=0J=|Yt_lIA4zQQAo+KF=5IOjr$!`Yjx_|upALe7CjK+sa=eCsW2_WAI9z&gp&
zj@fFv+=5L!J-}J<dA@7+Es0vGUG?i9x0&-_9Gse;9@;uG^ntLa>668Kv`Ki>54bC=
zVt#y&6p}?S@Vj>>%tqX?RCPA;w7Ju<?e3YoRO!n1K4nqv_-Y#NfmOHg=Uy@0LCdl_
zFnIqQY_;vj*4K}>kr<)$n5{v(hiBz^%R3A4OF21kh&A>g*=ms&O$AizJpuLPIWV}D
zAq@vDYLl}y(2@>6HHk_5c+op<8?&>A*rWY>G|eCTHP)Ot5z8M-RgQiQp@8AVM;FLF
zWwmOZA{>0Pg}K`#I?bTOm$tL{lWbS<G<3G#RJbe79V<_jxaU6`tMz^Pg+n`r7iCaq
zUp{AM>7+e2G39?eANc6aNd0?hc(m3R(z8CCCyg5`!Ns-ygHD{eE=-lt{^?tJ_w#L@
z%?TF5-S1FnDNI>i;h$U_cTFvx;X@AvrN7npb#H{oyWatslQo}BH65QRq8$9RD(D~f
zBNCwR`#7`M+=Lo5e^|qpU@cE7_EkVMTZ;wFA7;?1E9qXcAlvd?TO!I#6l3G)(#71r
z!c)Rg;kJueg5nK{wSFt$!!5<=0Rl<M<#<qUP)U%PZU^|ex7y6q%E&&gwmx9*$sA#f
zsNgiCNA}HMWE@T<Y7vi3!fuR3f#QrtI^Ac_7N^-$n?`K$tqeOa;In1Oj1||wg>i}8
zUEzCR)cd$xj9m9eS+~<nhH-1D`~o*sEgc(Q9sBVk4W>ln=`|(#3_^0b^uonu%{3xL
z+@Qu7(NP_oWK+fjcg-3~Pp*Rc39*r)H02gj=_jud!~%GjN<EYuKVSz8DUAAiT_+5;
zCD@Rj&>mp8g99mmg~+zqs=+Z3smlShg@`Ly%a~EJR!+7&-YgriYzj8>J4upnBV>YM
zWr9_UX2o%!_q>xvSpvyKpa&?}N|3F?bL-qVkx-14A-cxe;W&r+p1{}4*mKM#%dz>y
z2PN;=kE+&4PKKO3YNbwhz-zUt4Q+|Ij=$SIJPL-dhA|<I%yVfon|j>MYH%?(EQr`+
z)ClyGlx+}o0>d$w^EEhQmWd}Zu>{8y(b?^Sbqz9=>l~;du{=<c<Sf-}C8!ep8VSdi
zXf|l131c_)gt=-i->2sukNF0OOqe(u&^}@c0aJlbq{sASnL;m|Imi@T*y$7CqAhmr
z9l^+H6OF@Ii(yB;fapYrJ#%sIa_qt>WO{?}m4S4-#p2>twSLYsa(8nNim|GVD_bXb
z43MKIXn-|Q@f;<`({x?ZR+-wDH+-RVadoOdj6<9gFy#;+u$C5SZwQ`Ip%7}u=~+oT
zIsTRct3i~q1x7pVvJsfnES+J4JNg^c31%aDQ^yg5;#=${Nc7`Ngt%QpHs-Zj9ihAx
zp?r#U<%~4o+*hhW6nNR85MEL!sg~EW-0MS*;FefK4&<o?tm&nQ<Nb*4w2uztzU^`<
ze@C2+c3|fgqdJ}*?ihC=nxAf6$|fAmw&l~w2wLjYeChWHuptq0YDfoGyVy>^EAOEb
zG-2jC?s%6k@KE53l6k_oVpW_@!U=78XP!L|s{#+6k$UW}_|i&x8$<Sysu%=966SbT
zPVk)R2~ua);1@v|_|h4<ykKf#aJeI%o7)jxZcM6^LYsvB2fZcVD3kjWgN7{(o3zpK
zchH|ha~XR*DBkr~IX=yRP*;jpa_}6l4-W|Zb#d<g#^~wc0)L~s`<Zq7i^<SNPoco*
zjm@{;VuN1{Jdm|*{tKpTaJH|I*~-`DQ!CsiYWc~!i)dVYTl5|OQSX_y;@V#^J}FV+
zCSmvZIn(AIr1Vo`1h2TIIJb{8vG3+Z!x@u=?@v-|{w`fb2@dTW=EMlqoio3DGWWjm
zxSTlbe^od`LDybjiQ}D6Cd~l+<v?G(H7Lyzg!`jqu)-1<%wZYyR!ojS5=-om?0;8k
zZ(Q-xukZ)#9?yR{QH0D^pTFU&31ePHkDvOm=^aI$EQjD=`eQOkJf#B4)mDn$3*;|k
z>;>MExc-aERXv`lnO>>I+6c3|w`8k!)4a&3Y>h*=u>uG~dw(+6WA>xDt1^Y4Vg~&>
zg1~(=D1va~R$PphKFJBdILjVi;>@sxi}R%UHZqWnF@I;`Et|;v>3^OyWw!bg_N3O@
zUzxpJB~-Qx>MYLsRrBBWNxt+;$FKwJG4zX=%BEB1v)Y5UHQ=$>qUG2C?p<R0LYx8k
z77YCC*_}SY$613>URl<nWxDy&tj+ZXw21P*{l$DDuC{7X^{ltgiRVRrnev!aV%d+M
ze2M|S>X_&xDva{gHfM#zLdxiD^&nf33<hGec>}uAcMLMYaD<h}I1!D=PgG6?^NXEX
z{SnaFB%ChnbL<#S+(kke{kPI=#n~08C?MSf!?Tqvh!2XR+#AhJLpJ@>?05JR`ua0k
zX!PF`N7?dXeqkxFC8YKJFL@h(k>$I}W(HZr`lohAl%ZPF()q{wvwKHsysm@3gcEYp
zE)yn`ODei;2z9mi!Cxv>s=eB(ppZAJ!J0SS=IDrnmA$}*l*&l|yG%2v$8K@>ZR?^a
zMe(eOyb`b<z5h62EA4=_+krLbWbd1VNu&xfyQx@6d0XSSXgE^SVmt!;hzEh!rF?Fl
zv!G4F^Y!H~5_EHn30w7g->ZWxo3hq~UrnUk15cmHncuR;eGe9r<}{}R&kG}zmysl?
zHqQyQ^g~4N+ZpxPY-UTxS|9VaGQh`xX1)2#_;TiEv~v~GRo8}&Kw%kW%WPeieDISQ
zggQ^?6o2i`^^}iFk1>ERWem~8mL*Q#;RC_~2JqxTpo?Bz$S*3YZtI{!X<g9KowU6s
zvAH8vDA6KW^RX~xNW9K+4eR`|8%b|~Em&$y$C%N>;*aPF9aS0VCw{cAB+5`z*-o?B
zCmQhS4cFtNv?WZ#PFiKu%OWp}=r+ugc~&_K@}{mNZx02``Cx$`Cex}c@bv_c!EU2!
zp&rQJ$5ey_t28F@IIT7H)TL{5pQJK!FM>N*QNjpMwiU5iin_?xj8x(ivNnD`;_5>8
zV=2t^maS3<*=jc45q8HoP;l9vE2Xo%Ud2{ZnW^nOTQ-H;DXywZ53nShmN=CD*YG%g
zSfJWM=y9rooD^F&Pzeq;XF8nC4OYEgfkOWLTox>F2VCI!ImNJIQoht)zphm6f-2(Z
zAet^d{on=#<JtkQu1fjU6_U!;1w5K+<NRdJ1j@uZqUWlO7J7x3xo130QO)o;30sd9
zz2>kQ;u$|-U3s0Up7JL$8w1%26)DQT5iWB!x_PDv!d4t;m^BroY$u`bW&Nu}USVyI
zULzJEr#wOG0uPW_%mv|1;PFv2xe)3I4axu=Nf2J7i8C#6yd26R^5E&eDx|J^_$AOr
zh>8@_3H2m|DWgG)R6Nd&LCiQ%0-4yPhZgrXXd7ZkscE&nCfDw;zfW~0etEKR_eq&*
zB*e-j0-F-mNr<4vd_ZHom<Cmx>(k2`cn7UyD`}|*ir)xgwv@XMq)Cet01>^Uz_ri$
zQhrjhl%KeuY-kfDcLof&n$4DtOuEzy%t8yi@?;9nCRP=~C^Qj+4c5pLv?=xGeL}D_
zK9)_Z(V6#1YFv`?CWFi;+cQf`6!tdZ$h<hC(e}aXWF!t=i9+;-z~<c&(IZOW1~2U?
zVGmpc$fw&O&mZn?P%|OUS%MZao^&4axZx=)92Se|8MK2TRg6e&D~tX-IhdPoc%Hy$
zaFOpJ(@+T<_CvB)n{C3R?5t}kPk{8rGBn^P$#xLn`K6ngA>3n2tpGx%6MvTpZF7dj
zQE?n-s*r8~+YxaE#L(ZOU}0QoT9t-Y6e^4e(H*tN7WLakT?Ex>_Wg8*F@$OuxdTCy
zEeE`S9TSNM@e4{CIlCFpDiz!tLtxfmGeq}*hA6eohszo?<V^YL5fu1!0UzUou1e+P
zXp5L4loaTctk#K;5_x&zQ%|T0Y4D37uRhz1l#X9mmu(BbDMHx>erq5sW#Ywe>^t!U
ze!W0nClhjnkc!Z56fuH^Mg*XKHHMVTwNY2IO%aWxgX)z7iB)Q4@!>4WtV2bp8-wo)
zLJ$KDIihgoI2<PNhH!Y;QGH%98N8!t@%hTFWV_`3WnyzGYag-=daloO1S9zrM1`L7
zO#(?w9iijS<BY2#<2C`cd|--STt|{e6HKchmg}p&UK}J?2W4^>LlhHB+lf~p1x;N%
zzjpn@Fj0FHdKi=j7(rgaDvF>(rSxrZRsOycKi_e*c^V{d7Kqi=7mRgQ@z&5@?rIS*
zl6VVxlxQs}KJ6{zF*XT>R#_~KXC|}2=Yt5-FaT-R^(^L*3jxh@5t6pErG~me3xqfp
z3zWPM53~eOSRa9);U`_6NkV6+?WaL3mvRG39^EzuP2UEgWc<7wYHk$AMK_ny%jP?U
z1b&22Y&kTJL%j09GKl1tuscvA8DFAQDflcXfgdY=evOI(HiQmm?Hoip6;b&GI$>B4
z$RdrdE|-whbQFDT{ades)H~aJt)_Fhsukl66`+%k+$DJMV@^@LWZN@PpT+VGkX)bW
zR+4)ir4g&C(;LMMszKfIG;ee`t*fOq(oxPvjN}sxJ!cFeCGO;!r#{hgU!66fGK_p2
zII*m-!OL5CAz!{J%EO%jQ|j_-s<8%r)cqMaW<)?Tfa!5<`fo)~&ljiXORUXU_B9Tn
zKwJlUDktR`4rPke!Hg2Msg|MbYi-r%)x7@y0B5a0mv)6e0x@?O^I&8;PjseUqDstx
z2?D!Pey>aW8l6YIxH3lN^ZJ%i1ge6Hg&>Dc>8?jx5zdNnTpTf8A|B=MLIPk}i|<Vo
zEa>T<&0*|kdx;59)USj{s^jV5o{S^;8OGmY?{FyI_wmBVpyh2xh&~*-^o{iUtaT-2
z`VRj4(=_WKu>nuuw8E1-bE#$Q5G*5u#>cC$V!m|8Nw41OJhx?f_9r%*_mA&HWUJtk
z<;xgQewbeUX0P#PJLcKb!=xX|iZDTdz5-^OrPpJYw3wpB8=F=exy$XTD(5n3qfHwg
z{(T<kze7RyrOYI~oruZf-PYPx%R=EZo7tA1W%nZMs|J$6{7Os0xrrZq=2*C1oX<jV
znbpUpQ@aH7ol@BfQ|l~#T_v-tch17e)(Dp7c9*!icugc^JbSRwX90dQ=E|3x5W2yh
z|9RQG=JJ#6-@oJO>342I7fH@9uF{A)FW%YmBK4i}C3tC4Q{QIvIN+PbmqUdQMl;VY
z$(&nR9Xlxgs8F~SlxFOM&aV8BpYh;1er?7r+&Va@y=g9<^GPOl@VlXCeeL)no8cMf
zW?<{q&7S=>-u!=@j(mXB1Bh1bdoB$(q#>3P{|%oZ^s(*1)t@WET+-j*n-aJBtH-PM
z@cHZsnQ#0DP|sxB<5S5#OHLk}eBwRD?CcBuX*S5(?4FR={DatFBOfjnD1OWSjcVmp
zL*ELUwKKIR@HT%6$MRutg_)7es+WwfCPQB*+UsaE<U_0B8#{!kg%dmOLbr9#HE|G8
zuz}PKf13!>I)rVFZ}tsq|6!($fYW;`E}0NnPH4&Eu044u0qv_tI2KiZa*k#bm!b|N
zUg_e#)kACvyN>m)2QIOsvyh{0kJ-~ra(M6Ql<od`hG*N@u`uSWF>^sMs@Y2ey8=j~
zi_e1n?3>NLeR5=1n=Zp?=Xx88n;eOF?^9D&`?HMi$a;q2H&u$k=@B>bXPm+met5i1
zKJ=wvH~et87<zPbGBo>xfuv>W@a$vTlcM$vll>Cr_GW(G^<Sg;_QVxzPd>`=D6?-%
zZ2GTh;cvf|jMu}8QPL_Q+N0MK2yr>F`tplB7hZ^3G7g1fk_%$;C@vb6%_OZ#kl8+>
zJ$frKvQ^>ns9k$)IEH)AHS3aZ?!<JFeSf2QuB<>=Uu1mc)Rb?`p-(rLL(37ewd}i7
zlYKiXsSp3IY?AW^mK#Xz`qbg=IorT)?aXd}kTJHu(37y-blK?VVM!+Rb<7q$hbTTZ
z>^Q1v+NHljsM~52;YH6UA;+?GneDZ9OB#%GM2G!Fq@frCjn^{Kwgd4mCqd7IiSTZ?
z19}t4!DE|)ej5{~Pp9`!)>VV+AY}zh#MngG8#NRc9xaWjkmI^X6v69ZTy!%Ap}}mv
z6Oj?<qo>{pdNp^w7ZLg7Xrsf@=^&eE1$RQ7Ik*%H9S{##b9~((hWbu;m%CFu$(9=2
zDX<{$TS%!qbDYksl2l?0LD+Ma&TzLg`0WN)5@JTqVy-T7j|^t{<xL%9qHx9yN>hpF
zE#v444h&5-!9q#-uxD8qA`~c$mfRb#jS(#?>`^POFRI?|BUwXyGgBMZNce1A8yV-s
zw0;q4<;|Bjcv_9=glu?!jRmp|QmPKf*h$=|jV&NAo-ysbgflo4QaA(Jxo~R>6_+a*
ztn>r{?9+#IZG&2dN<z@RL-aS|CXjWk^{uoJTlBb-iW^-d_KAcxc`)&F%%c|Z92zja
z-C#owhn9wP<fW9~#|a(<b^}Ug6EuH8a9pH2M*vv#M+kmpP)J;uK_c!3I37nC)M_Xs
z0t;){Csusl0;Z6)%2k>&rie35AU@W?Tv`)WC+Ns`%_n%?Yt0&pCzZ+}*+#%@4H+)|
zR$&q*IaqX@uA-Uy)!>f)j==H8fanBb5r+9FN~soJ6ewGh2V5XaH(zH{DFeFndLpbv
z{np3npd22JJob4U>_3dg^SmY?#QSaHH6(>P;371j(_!rJQh@bJNb`3><I2cSN=HJ;
zOF@cq8^}p8I#=GiUVRiE1U7dVIM`0JCRNvN7o1YO7HE!gjCG}d6a*Gy%))9UKDX*Y
zW8;8)Eg-rYL8T3)4)7F0!zU)KHXb8=yl!|wVroKBe{?H>(OFo)={B*|hsg~egD1;K
zUA?kO9A;0HvZJ00`0$%8_@HXVEXWlyD`fo(rSoPfVLd?@6I#J!kamJde;l=|Fd!U{
zA`y~&lc8o$Fv2+ktt*)l`2p(H+Eh|{gz@hknn>@!?&C3sv8?P<Q;VGKGDlYfcI!vt
z6rhX6ji`GE9Odf)mSDX3F4)#-G`y{cAQ<Mg_i8Sm=wl&?&^&b;4)!g$FoA+SLD`z;
z$b$UHV!Hn}i#hg~FSLTnn6CA6n6MWvC#et5lGh&I*c+T@e<5b8j~PFFszcIAYIQp3
z72GyDZhePdgLHnLR?0ay8U$!6)RNCJANRy=)-mS>EPsq?s~!PF2n3hk!^?qzosmU|
zO_$`V1P0ehWSUPxuE~Rlqr#qVOifp`1#SDTr9D&2$0{}Z-?H?qrj!Pccw26M1W8=V
zQ{}6viz9eXsP+G;V^%cw8l`4oD`dMB(+wK`l?PDe6epuN<Lx*e+)((ind2T#Jv&jh
z;Yuv2pmM~rarkK!v$cq3>v#C*!K7yw$X=emy%iNYLaaCY>1AdXHIuD2Kqi_0_qt;u
z)1~tdZ>9v_@8_c@7+=bE?{iffT9{<Oq1Wa<kf*l~TxnaMcz!37T&$h%|43i4RQWL%
zo7d^@L}1t5<+6voCBDJjVvn5VHhuDNT3@WF24QL4%P0~IW~+<5i=m$2{Czy#^_tqJ
zE^!>GO4FeLdht&7>{6{i#GRZs-_~ap%+`fCM<Bw{*yAISvDTF+W{b+jyZjqM$6795
z-NbMdAcIjNd~53euw4i}=#9Ymlu_B1n-wg|DpSGFS+Y1q^H#mM?WacVn-EGjh$Cst
zR;D?ib?mPyTfhI%e_}L!E|ZDxw&j`g-(!7yFk20?b#k&*)Mjt01m+rS`r#LCd~fm=
zpFVzzuQys_dF3aDFk8QzH+I@NS^fS?@@(n)t^V<;&Gwg%|4ZT;HJ-EN;JR@|e45;W
zofl^SlJUfUVwX5u2P+oV`MNtpc+>E>b_~|T4oKZtrU?D!Wj|&_=-}re`xlJUR>cQ8
zVhNKP0Ci;d@ft?`FF>Tu{z&IATkB~%TL=x4ZI*owp#w$S4;h_Ys^7RQvmM8#3-);=
z&?*(TZl6!*VLYsVVsug*`R=#nS#^cDqOWXAU**++>)8tH-{v!WI&q1WW-B=?Q8B-g
zEt>sNa^)Omt37#{*)v<{G2ah?$w3=#j#(B^slHvOIo}#$Z^~FD%l8dto?%#AP$X4X
z*p)tUs@EB<%|QQA)R|~H9M+ntKRn{dzR(V)fW-`M`8~f96e@K~Ed)Yb`^SyoIc|D`
z@_!Yalmqs|P)SR4LVHs3$TZy&6&Sk*Zn1~7Kcu$~_`KuN6SM`Sg@YXq^$AHBaIoRu
z!`R5^9S$n2L#liRkXtGf8+qtKS|n&QFU`e8qrkh6O38Rj9mYLo<DiIQoW<qV158k?
zqDm=bhcxK4AifTULhPE{DqHK~j_53yd{Z4+iywq7lzrP66xfKyM4=}jtp?uuSE=w!
z>KezfH6AbW90pWU55PNUZWL*>%*E_ilOWfDQ5*j2Sc0lg7=&`F8kZ_%8*kvic#SN~
z;O5hb9tx3dc{c`6bgL=K2+cLP13VO6b|HhzKt$}N8B@gj(j=j1E;EIeEn3CR&(bO%
z<3U66m}`at6mfX21aV@YL0|e<KtN3kg#_AGBW1NAxOQxiNL{KTQv)SHrXiPDRNg(o
z8MJ#Pn@%d;NZ7<1_=(Yy{lN<H>Te%sz@kC0vkE@UR%L{*4Pv9$Y^M<zDq8Xy(?hpt
z%B9s-An4MTN`1kqUY3bl&25TUf?V1Xn_VHaF(`tisVb}usSmu~l1@D-f1CR(#cuWZ
z1Gg-3xWvkobk?Ef4H_qsPaH+yV}n#Ku91*Ls(MYBF%Z|D7&8E6NdA(nV5&8SpO*&A
zt#TubRUoD}a3xyY<u%<dm!ugwTs4(Pn_Td!JLM0A<nT;L;5BOM0b+G6wJS{;5+M@D
z<yNV*F*4;pPYkU&s$0v;$CIeRtw(Sro)+7p^VYJkg$fayhll^gR2r*n4=S1tmTOdd
zI$Pdc{)5t(aS9CMuxjXt!!gIBaZ-UaZX0}TD~{g4#q1I~z{7gFcJc!@rDN-Sq_r$o
zdx7O7*~GUjI0ewRY^jO^c!b|F@99R*&0Kf?O!GlL32F8Xh8f{MF>}#ksk!wdK4Pq1
zRO7vY<Lt9%-nn&%kyj?OwGBRDk+-_sK5#&RF2+28g#B4eO--P}%+zyO**FWbFjx$f
zT+&Z<179LM$jyC>%eXzD>e7L%{?F}lTS+I1$=@ZSajsp}*vskcRAcJ5@x&QQ_S=(v
zVS1TUE|OdLUQKh5hr+wEWS&-OdyXHf>hopk?UMSIe1^XIy6XJi-i{U^iB0+cS}Ve*
zz1$S;{<+e@Rfm;?*2l`{v<_nF4lu#WR}tTw+P>RvTYl!$n5g|x$?^%K)z-$N%p9ke
zGRSy__x@V_mU9FrX6qZ1I%*x}l?qum#=7ST2H7_EB_TY@uBbSs-&=`Q1BFbByy4d0
zb@8#{p`8$w)tCFy)<14ZhqT%{F-W2RpG)Yg`95Xq`Au4_W&qO-)c%ys64e@-7`uP_
zBTi`=m%r9*(@9A_dMNix7gDz6{gtBfrnCH3l`Y);9~LLG(`W1xFI~1c_|NA~<O45d
z)_Q^_{n)k4CCyv1_xs3Vp=pVGqcv~kMX|fiXe8c`k()B?3QR3~_5jZ;eI&usI?jze
zR9j1@meOeTJINuT59{7?nxuH+Ghr6%6wzH`TVKC?fp}<W*>lG}P1^#U(_V%(X93a4
zX!CUzLixrf4`tzr6XY-}_lD3U_BGGY=zpny%tl_<X^>dU(1$`@dgG~MbNn<GQMQg*
z14}=9IRnpsp0n_mn|at$wGB+LOekGJV@x3~zB~7RFC{+q#Cav!|NX?8?bTL4^~W$V
zaV>+5F}^o5x!all3=JgRZ-&{*YU{Z+{~N!Sd#99@6TLg}xt;DxOAGg9b_6b6&vGKn
zAI!c)zf2R;GphY~QG%nupiK{qZDHE$*Nk<y>5y<r>S1vEH{KTgGhE$aF-P%)@ULwC
zKs0qNd;0H`XbpO_@WCiqE00|vJY|k8Lb{@xy5<h33SJdVHg7_twPVO;%WQ33QpuhE
zzr3vrSIr(k_jXk5q_BgC?`x4)E49CP>eXC5zaGKA4Rw9)E}Ja2l_|dZnnu>3n&WC~
z-`iVF;{z=tOIz}QdAij&U>9{o3t#k;_QF(f;R;{!m+Bzl<1J&gHF1qC^~Kg*<89_Y
z?Hs4Q#fNq;Y^AAt6A#vtk%!)%4B}=Tkeymj@8B%BHg=KV>GWk(R9IXkQ&%wv$|XSn
z3qXDSYF23seN~s>LDvfyYT;$IL<erDO~<i^B7!dKA*9xl-|084YXsN6Z**J3VO+ov
zX-6l(YZv|7Y0M`cz8DEH`mJg{0vq@8JC6XwQ0o*t6R%nan1**BS&Bowin&J}xPn;F
z(s}f2ji@;Z83?+x-EsoQgn4&(NEv?QtK>+>Cc$Pc+!^+;=N_Tr%DYGK6veKQH|4k1
zsdRGkih_unlcOudY@H@xlDVzW)$q^r6LCTOaE2T$UDm;zHA>$YH+9YuZ%ZEXj@OMY
z?an%o&W5<|ZX;)YI-CzL1bMMWd$E)aX)d}8{Aq*iib~TabU<+X%{m>WsRw_-ydqt8
z!w{0Xv)tTl;10wB1<~9X;E3)Z3tEta6gdxdWMQ6=z%Pe9U*zN=%)KkbLLwd45Em7{
zD%%*L<WB$atBtg<?z9ZmhV3>-H&w!FU?+0JJ4N-k(FK!j7FB<Jawf=KnJqLf6dkWi
z6%K2Z5!52^O(%ysoS}$WU3!KVf?uFQItfDB;(#=s&#f3D@=|rUsuPe*QD`0$RTv6E
z7}+>7R`-3m+40M269kWsI%LyK;@gwO)NV!~mUxU&_+8Bj&r!fJ?-O6eN}6PEiD^b_
z4J7$cdSeS)i#ehzTMNzl;%A^a`>P#Bb%n!;ml2t1X9hW&Y}Z8H(%~SD-5AJ%4=lut
zIPPj8B6qSaQ-;(Sw5)c-u{|T?1$qpQ<*?id4UB4-#34y^2fv0=&XdU>lNL$LT|+8C
zlE9v4pdNjm`b4a3tHk>`erV*hQ&f-)2(6!K4XMCPW6+w|m@R4E1nd<p)kk;mv5!n<
z)|suLOr<<I5ycv(`!b-YNG=;gQ1tQ`mn~@g57N{gK29^GEPFb3koE-*DaCs;&s&ZW
z)oQERcQG;>rx(9L$bw(`+yuobK^*i3L1@hxG+85_zn`A!G<byzlICWb@Qv^TNZ||0
zHfMW2R^<M4CY8QP*B7p^8B0IXNbJ{z)dPr7ga>uKOcfHLc(`i&>^$^iWqxnrwxrEu
zKW#HyOswC!<W`O!`GvW0PECH{wmfBtcP#nPxN6iNDEJzZ{j;|-v)4ProGp^uQS`;#
zme|=l$L)QuwNl}_sa@pkYsF`8d)_yxK@{STEkykxWjskTS}O3f=lT96Zrvf;DRUnS
z##aGtc{VmRhpodl-mwtvS&h17Tln<S%q~2b-=I~zLMMSt-FgZmM)C+0GK%T+?irRC
z%|*11LtWfi?6vmoR1&nKAlYwRyrfThKop>831wS+Y>pQNALmHd<_u{oY)gD*r&%kM
zX6tG#Dala*T2_1whNq4x8ODG8<*!Zcr!dL+rhT}(!5H+%t~u5IX8PnjT-~IWp2sH5
zY8+nj!#<9a{b`rq@luGKCFyy2vghBDG#FDf*&CN?n5~74!P#>=ZP|aJ8pM2WFuyHu
zv}VFlI{obb9vgS1LYG%rlr9>bKb-1l<Hlrnd^JQ%%Qk-@Xth<?Ud#+1iq#dnnL=x;
z+9YiIUQF!@p>)hv?ZAtLyj_WC+m2gT2(@R@1*u1fn}pl=9SSmAL#*Q!vK32Y;`kmY
zoMF(_{(0Dzwk|k-7iMcS>C1%@y5=dINb8ra_BUq^4s>>1sB9b?WPNAcwAE%0Rh*4I
zgmx!89F~T;-T$sp^RbrHp7Y_h>-s09^q(CgyJJ3d3XkBML*s8lI=gA}sB=pfS{~BB
zvh#<UQ|81G8OF9K_lEE&!p+}D=TF(~6T9dj*TagnT%$_J^(sLZ*h75yCscnKv$c5=
zgRvW93MvPN)CsjgZywMv)Rc!i+H$is6dQ5n5FF+ygN|@jwsW5^f);sQ?1*26l);aS
zVPz)4<4M!+PUYJIg_hYW4ZtO4#-g+PrP>xS6St(K!a7NA<O}GO&Dq!NbLk6&reAmA
zxGE@er_XPCRF6^m+9b)@_TpDreguIOyOJ!#@d3Q}-{tMOFc79E$Cb7O8G{=GN}L`%
z)|ve(c*~Yd);mJBQpjpJX-Q*tV^WG`CbVq>N~3CPBb1obmz7k*lPDlgv6~wUWd__1
z)5F6&k-*U|5i>}#f>)}7H%bv9iS<^x+gHy$=<U*>Ca$>Ia6gVC(TTyUm$2&ctFE>q
znWIml=AbNlr5(EZ>1%gYY1FkeVj7=N^lp9<eQ@F?iign&DHCkig(V(LZadK}e!h&w
zbu<WI6E`7Urj^RjdYLeXf^y7@yduP2fY%$5Yyt<aFpU&CiPSVZzzD_0YE~?Xfmjds
zRZ%4M6rhELHlFKRf(}9GP<~7`vMs~f1qt|+K@cg&PiPS^XBrdUGI=IbZVS>YCTAxc
zhLTM>Mf3nrR$dEFcW^1m`QtIu8edITC}t~HFK5UU;$y!MVu+tc@`?gNavJBZWsIC3
zgP9pgy-sLAP9Y-ndP!B-P$t?*qH>30Cv~&xBY(aV(DfdKq3M7I%&MAzSZ`6xTK04b
zs(7_+of5c%wZ<5t3(?Ud=lPa~RgVI?K=2^=21lT)my!oa?q<+1QM$RJGj7yQ%~}ds
zBQ8rZSdtM7ddXpAT4+awF-Mes6oslRoMp}E!_Rtt_ARo9WQikD1RhU`RYUeZ@kf-l
zW4JM5O1#A8h0f4C#JK{o0+YcqN5?mwc(vbZBjRj$K>!H1T!<0@hGs9vA6AHedFavn
zv+E+#$+jobEXCxJyIBj0NsJ_SHIx#9OuKaqOm-J-J7rz>d454Rhoc0{0~|2}L>gh0
zL)Q)nDXTuD^liV3989d^qaE>z+t_N$R}=~EfK~*awuwi!v38s*1JNmJ@)~o2dqqr9
zKCeN`*2tzVrx8k+c{u9BAGwwNOWlG_3=us+=ySqTHZT?BUV}Zyko6<z%JOAvfk$%%
zEa*hT7B&ed_V)qvd1s0Hh?|VxcJS{ci<@C^H@j5B3Eu3^F@`NVl$HI&TbI}e6M1Ny
zZhr2cP`Vzojod4%mVF1J7{wXgTr$E5q|1pjJJ$qt4bnpEA|Lb`SHTB7ZcweKBlIrK
zAD@Xhwr{+=(-UqCd6Kk>U1_Y5w81Rt+`q0R2tR@-znCPG?I2H2S`YKymWnWtPT7OB
z-XA6tS1oS}X1gp!$}p50J}b8Q_Z#nnvB&9~ebcr)=s-z5ugb#ax>f+{kpVKt*?+GG
z#X5vrwb!XIr9zO?>=W0aGT9~Qvn+!ipunU_Wu4BP^!5RpUXB{tWCZU-A^gD>=HfA1
zpKkVN@g2n-tne(g7>!~{&0U>tn;0Y80!zi&=GXasy=H4pyusq&S>LymO~R^YxA{!E
zd|AtUTO$_gisg@3@sVxWQgLY5?jhSg(5!LxRAxI*jxEIhpUu>j>WvULgx$oZC)yie
zxDLaa9rwnX5_o>ammlVp$9ox(DnKE_x3dPiH4G<90VTTY;*gHN#Fs?=eM=ffZ*q)B
zfWNvneuc+}Mt`3F-X(5n;%{laJI`hb<fdlfpZy3^f;El8y1-coV*V5xf-_r?aPPV(
zA;`sK1DNmsV}CVGWwvg`=<EssjJR8u`{%CY10tPTk#WdJCBuB<7_<%J@aE?$@!O1<
zzOCUww><~Xu=;OZj!qFWMSvrb(~L;hUMGOv-X!dg`{)-#F;QB}w&_Bv?RX~mMGyju
zyw{7L{a?Pce8t5Rnm+b_7e(!BQ)vi8V^RfcEN@CB1C9DNhJ9{v0{z_%fBPGs`w6Q{
zPJMJ0SCU?d2R`7f_2Q|CIXngSsojkJTrn_hS5Pzg!IzwC%~jLZ!kb(G#oGrz&DxGW
zEdsj<^Zo9>`~!{rldSgKdvTh&Kct02SEM%vNlYK7i7(f(I-lMC@zn%Anq!|DwyaSN
z3+%Oxs<;|`Bu8C=7k6ULsV7=O6&FEjdjTE&yY6<H;TyEaw=(3c*jSuDj48g8S{jV<
zYDQ5&qN);gtyZ!P(I{RfFaO4TPDZh+sD8|tvHGj|aX;1?f)f0&4M)^VrOzHep1xs_
zbeDCq`2{MQ=*$UeBRIy!au$qLJ{OkhmgtD(v41T`3$A!u+UR?+BtcVUg~%)3>rgu6
z5x#^S<k16vZ^ZHTFyEb}_|x)M^hRdu0@!?TrkD)+6yn*XStRZ@258#SCii8DGCV!q
zGDnMD1z+G45#4)+m`Z7C4kqJ6LsjES0^`t&Uul|&MKr=YY|c{HJk#)?4O(*!q2udv
z_o^1pAi!lJI8mbK0q0Wb)-~i_8AR#Ji=eXmn9H!N6sEBjkvn2~fDx3PN%}Ts+8Ci^
z@tLDS0cxdDSCm^LvF+Jwa4<Y|G5=|6dHimYi(LbbDx3CLg2NvM#UL_FGF|12;M(`2
z-ar_#g$3$zYA&_k^tAicG-MZutxIjkp`eA19zbOf6sWMTdhP<p&j&b58xp=%TQdA{
zbl7cHTWpE9tt~~XIeA*ms{rIVh}4S5XlH39cqMJvP;y+wnd}{)XrvInr)JRria~*E
zWH?Jo3G$5dUP7dvyFoVZY8{**oAuY>5$Cj7WkkUn9^$1^iJVi}JULF`!^4CVO*pXo
z1T=a11x~`7$Lk<~-z^e07&04OCw<~J1`_JD$bEFM$`^H!#kmgp{eqLXtekZbM|6^Y
z9ZdSRNBpr~%Vo%tM;&*g79Q2T#V;sYA!E8nkaQ54FMZvvWE&FaobaUX*T@0S%JCj9
z6DnI<ESVp*ospsa!qJgTq&6oHbvZ$%dc9wLW)}$YZPpUWSA8F5E2nwL?>!e9V`-lB
z>3wgFmxpIXlfz_O<cv~_!C0GRuPsp=j6v-l1HRHKGNTThYrteE6{o~G>NRLm#S-UX
z1tjNQR+f+u?udC=I3XKBtBedmeLRp*f>@-YEHQH)gyt#~G0~$+v@6SEMqV&RfD?7;
z5lWqElTaFE8z|M>Dgh+wJtO<o05YitDv=PM-6MR(-KS)0NUPW{cPt{734SGzx}B41
z4MMaKTn&{mBI#R2LuWZ_iZeFun=cdcf<~JJH;{pb_l&+SZ_6fe3}_8uCdn&i0YQER
zgvkBax5@~Y_`@&`kjI`sQ4xW?ys_66N}eo!Cp*1XVvP{ubve%dqt7=FIBUJGlv}#u
zEDvvik5(miSIzkSE=Ef}(bpP#0vRtO<)C0)S49iHATT0-4P&#o$UDYpJfUJg6N%Ee
zfbedb_ch0uv+MCqE`-z%_tAC5mxqLKba2IV>i?Sy5hFX-`Q&;>eOk6}-Z&z}$!yIg
z{d+wabA&I_h7OE7YizM<xOCX%PijiQ>?iG(D0qL+X9OIO4&0y!;KY9Kn(U=ccTvRO
zi<3|tp_T|oygI(Z?ze?m8Ru3%eS%@^@G2s<#cb=kzC5-$tu?jV-YUW?9G(zIk!o{n
zEgt=a+!O$WjElAzhg(m6e3TKqyK<QqX2f7|h=*E>Dw$obOpV8oZ(E|h$*XUsio%BA
zA+!G*+u~{(rMDUZ5wvf0&%ufY``Dz|O;`F;bN@#tjl|ZoD4fl^SppuK%3Wn(YcjNp
zw}yScO>f>BH<y%Dj&@a{jyoaWPAxQ^*!>Z+&wtodfY!6*`1bSCq0u`j@pq7#51VJJ
zx7UjKJ>Lrc(b`9;yIXwv?$&@+(1Y-gw-ke(gq7-h>HGO0$Gl}rE}N{`jo%$J_sNsP
zOn#G_Z+*o=@y=T3X+nadK}L7*M}KOgqlfyh4#sga)epy4hK29dR+uC3YIF&__Xa{#
zJ++4Z*vbY$jmm751=_m%_4F;6t<j#9YD?Ij`*lqwr)nI@q<V=V<$+2h8YQ3`xNG+1
zC<E&8(J#`|mao(n)f0Vw>>;E|@;Fyldw$GPErcqQX%YSEU&MXHHh1@yqD4hDuCHJ2
znadt~NZf4<3B4(;0a~rbaCKr#W-H*#n&G<5-X=fbohQIIzIj?^W4G{9+zY7I+!axz
zgGefml6puxfZxT0$)E8J<{i^T&4=G~GF$C?b9B~Yn;8ke$%frMWOp4Of9VQ&VfUOp
zTF*vrqN5tz<n8V6Qi)^A5L2&|G<u-5KC@+t8$O*%GOA`5)I(x{+O_>q+JcZ}KSnsY
zQ;#?KtJ4;Gz6uSEo0O;r2y-7ynBOEre<Ej5+*m4xJ0BJ<F0GDO0{?irpx#~(6w<e=
zKMr4bIp&TSYU$fjkGzp!H{j7J5E+I_^zJb16awvZe<f}5y`)sWKD!ZW=v*`W{v!UA
zU0$VNe6pOlZ24n0V^0$F;;~81{x7nARwKwdhinme%u{FBb>WIU@s}s{WdEi>b$0<|
zUhGSK5q=NEJFnnE`z;^aE+%CF=TtF*&b{<)a78g9#QxkxXPoPl)1|IMs1%%I@)p3O
zUSV|@VG)@K&#yZ;`X{jF>7g|IDH|v~+7!+>EOc!e!wiChHRO}XF&wg{JUn(&@eLob
z|4pP*8$&sN8+$iWO;NWIysn&yoO$z3Zb3efG3bFA$HkE?dc@C^i(UuyFeR94=uj9m
z0g9Hg88OKaNff9;JjZY>32#FPmU|Rual#r-h{|pKm_st<B}GL6oqOrq_{u}u3jY{L
zDL-Uw&5F0C2DY=JT5VI?FJ=MX0&}Yl%s@D$KE7Mw?PxhS1YdEgR@#Jme&q>pD>Oe)
zhl+Ouw5r~QYmzJAb;(P&2CXt`Vw(8uAW1ivPaIfo9K0~VTNn*eFEIUz-!bTFQ5hYP
zc{ON_2m_IfXLXIh^4$~YnGTCm-6_3OvWSr~jCN0{;m&mI8lC7|>pI4P(uf@wAR;;<
z92J9m8>CII3Zig_+9Ul=sR#^E2^qOejzxN|Y!od$IT1hL%Dxd-kXPH?kwecABAp50
zt1R`lOy}{4Cx5D9%=?rKLrd;5Te--bsd##e3=Vy$k*1|Y8v|>it5u`}_?%@;a-bFx
zPva+XDAFoUL+2nF(7Z{>S1)0uk8#fwX=B>;4Gd*mp5RwWqZSrW3^d%3P%5njc;c)|
z$+|;;;(f8?^ta)NWr3pzM~pmD4yqq@Vy=@CzoSEew=!@kH8&xTp#6v<(yzm}K^P0`
z14`_pUgP^%G1jfa33BVf-hpyfR&;lFg37zM24XFBi|7T(ctZ#a28-F_LUR0&<Xo9Z
zYJt`a+K}fyFAtSsHV!`9U7V^`wrXy-l8V5NiiJ~SwJTs+8pDA-(vW;kIHYprjca!Z
zc0V02eS|x#B>Jo>yH<}k@#wmfDKRE&d5+D5C&BK`aMb#B1t-Y`mh~<7C9XA8@CGTC
z_<pLM({|5G?;K0B#_2SZ&u+C)(qJh$98a!~9L7&4?#TCS<(M)exp^$eg%ErkZ;@@@
zx-wj;N&f5$$5IrnB&?vLjN@j>rUb@F*Xo<)xgQ8RMq>=YcZHGG$5pj-2Tz_$8@wsb
zsiY&vV4zEj-|LW^My|Ux%Gg^oj=o!p?_f8-5PbT>IriJWHJJU%eGTGa`FHTF&`-Hj
z68K|caWHdz;fi9w-ir`1TWw`i8gYfc5zP6glRXxu@9Se-e!(75=TL$g=Thq}QY_2I
zI-%X}vRuO4B~w@~MWM~8fM57CSS7+?KSq=0^7FO~>mb_cFMQ8})>ae$)O7sbFe0L<
zFluCxH@=wNEyFVYfd|IQ2NDL;#8eq}uRbby8re>fEuW~&_$c37CX@71o}!1SRmv8J
zYfk8&d=1BRKba@H{m!EC*tO=x$A;hwJ~43O^uzSF{wa5kv+5fcNx&y+Q)^uPCCukP
zvb6Qr+X`!Zj?viQg*L;<!WM?J0iW$i!^BIN?*DX37B0UfX?bP!SKGx|pFOs8eE!;O
z(phuMlqF+Z5;u7hhq=F=YQ4HfZA+6jgv5$X+lu7BaMah6U;Ef>sD4rCrJl;7Z2SxI
zg-R|t^aL!bA}~_jJ2~c6mFjV*z!VD6N>g?D{RjIp%@LGlt15p2R7)=5JK(>JXjlce
zLC(SLD%%cEP<KHdsGHN>f*r?M+U!l%5m6zHuhiE225l!}nrJO6+kWa`|K14;_f-==
zba7^lZ?o-Z=ib$MK+!xZB=CIp?wbp{VYr&v-=CQ52etVWq5Zk@C;Vbz{za_0+VwnW
z?z^;R1CQCvtle(*txLn`{+Fh04*c1N@HGC8L_fP}GMw;M2G#T<2RRG0w)alU!WY=Q
zz3T&6n7EFK;=5`5o<v>YlV@V^W48L){(+R$R#y%&tQ9+}#ki3vtXo9gm|(l(gGU<w
z>Jdnds?D$-x|}VuKMS*Uz`jE^wTe&69?^;r7edER4WFO`3~~N&k2>O>;bJi^K#V{G
z<zf`Xc!7wNnU45Mt>4Ad=9&MU_}CFs()x!Ov*k%E+r<eUO+F54*BA4|FOFwiyTFe|
z2K}{3Gs_c~`5%!Ar}o~#aAK@5_U?!82HtjL)qZrP-y9a#+&s%~lLz~YtL84%0~Bb!
zHLHbxz#%rN(Gh$0EbFr|TI&^re3OB1lcQn$<!Kmvg5veS*)02G+)y-I_ra2*nXN%~
z4G(-*`h5??B4#i#XEkfm)IvwKGLk1wTd_KzB4sHTM@$S<)1;!kuj5!IDrV_pT=z>v
z22E5tpzg|J{WDD)^WkLPnnVvUprIo{g~S8hX#`qV>G1J;Ev0*dE3~jAodabjzua>P
z{NN=UXmp4Xz&b*kG0K)vu@SF6su=WpW*&!Nj-R@KlzZfKRxXm##d9aKnZUg}w51{C
zoF>clLZMEN30Q#wvg!?lC~hfafTh&q5-1;67Q-=0Z)E``w9h6%&o_n8(eq@96&)ag
zwQ(f~y#oDdgqC^!N+8Qw(~=mI`3j6urz9iUq!7eW!?FNhh1W76Yt1>nB~%YB>|Wx~
z#tCtI^O-m3``D_kRwVB*vLI_yDx1bhsiStbhGRmKG;Ah!Z9au#q3Tm^)j4(o<sKC{
zU7^Rp9~zL3lU}6D>X}q=HiQsIz@Ws{R&S)eqn%)umbwa|Bem6#qd1}xj1Jj6@%dom
zWmufSf(-fPqNj4S(4!CwB=O4;K_abD2x)b9@s?>`c|8v{LK1R)Q8i|3=9}YEEix*_
z)J~*~M-I}c3H1qTxynf!;fOb{Hqao&Y?^s5hE*D?n8v-RC__K`9>?c?JVmx3{4t`k
zSuP4FnToPyyU{fqIGjGAD2>O(!2{(Xbj<Lga*?IneCW=b#0Dg2^?Vu<oHH@t<rnDo
z2EL>i*04KC+ufYD`!FTJPijM?kD5?3y0X25;3&64b7#u^{}WJt{+Y*FPempTl_yad
zf(7U-f~L1(O``#GM5QJT+!)fLE{Umv=+O1Ml|(@yj$fMDgxmrjEpROH++9a*QAnJM
z3Z5Tu8J}hCWBLSMJ+vYu`1<~bPDW3xg`s24qanyG5S^7cU9WscWZJdO*0nSTvV@a_
z6RA3ny3@K+DG`<_>hj5Ce=Ur3&PHOsUUZ#(8b)shqxGXDb~rSJ!dDsfKm6N#5_8T6
z4l;@%Y!Z%=r+lvhGN_00g)Kz&Zst0!z14JXCf2ey40JkTMoZ}z<}GEDuum?Svviq?
zZN59bI-ML(iv64BzwUqC5@+2(t+Huf7)*1&gI@dDIVBn0-*1WkxWjs<r5t4DDtTy_
z{736X!7(ZN=7nbVLf=#p&P+o*!17@YYHrV*txR*Y&^ux;!@x~bL|Yb=FtOiHcwy%h
zW;^k91??`ZE~0D)U(0yr4b9aAT1ShPO01BTUTBfltxPq;ttZad3Ewf<DU(Wv*_up<
zFiT<%dsfSREIbh~`cRT#e&qJ8S^A={EHQ_Bh~BB(By1-*P?UXFaKa!fKE0CK)N&<q
zyZPA(+w(v&Y}cK$6iu3$#Wdl)$2>XzvzF;loOqDX4J%`OLtw~-p(hz%{B@ezPn^hG
zr`^>l7fxFLtThgf^99pSU8JTK8hf|ez&roK2J6oa4$STDv!roOlBd=8S#tH_aJc7_
z#}~0ojUV=<eP2Gu+33oQ`3GOi>E1Q(G1QiW31!lm`^u@VufjI+pKLMb{QAV%{H5Ku
zxx$3Qq~xjagZXf9s&A}%*Cb&jB;qknC&abVPH?xoT38Sg_TyGjo8m|5PgvEGXg^9z
zWVUYqP;y7iL>8_k=j5eDDFT1=A@xB$g1Y#<yxVG@e}Sgg*1^B|X}bCc$J_jXp{)Sn
z4<F>{wA~?L*`5=zE{sotF!yzqOhzuU?Eas*!xrCgY){!{_9t(R&;Oj&*35p2?3BsU
zv9vKX_L>i}QSR~Fs<pcjKp&e+M*UXT`hQ7#7x2oC>dtrVeYT`6wYqz^EZef<M@g2A
zY>a(uOk%KOm(;Qmjzf+^+vzYojveEeXPW1A1~4UAZiM3mK?pSY$mH1RFA<JII$W5`
za3O4)9zGA_``v~i#FtCH5qu1vLkQF1l8NI0xxatybM$DpbdG11boQ>ts<l?FdhA+N
zwQKWAwEYkU%3G=5<JVei5{G@|Oe@~-9*5a_kNp~}t!e!$(-wa2{V4M@R(s6{o!M)a
zELFjDh4C{R+9W*H{JUDwcgxvyycNJ4IL<FrM$dYQ$Cxgc4Exaur=mk9=!oNbC_N&Z
zzxmZsYq%mSA`?PFGVxscv~!43rW^N1$FsP|>}!qrdZbRe123k_WtwK4#2q+`MJvkB
zQ-_qd#v9x6*;%B0-R#uDFW17Jk0sf9nr&QTO9f9*K@O9~D=K%RP14WM?|i_rBFqJH
zI^<LZR&0o^8BbL*5e%&Ec9r8!*!nNv{@!T8Y43##()sTzSG%x@UV`H@^d&tNYv?Db
zRN1l_=6XD?PEK*gIu+L|<>?L{6#anZ>c+LoZLmJ#0@c}*$vDWR!Zs%&nrGV>d03Pu
zAy^<)JsSXh9D%cGSSTGUgW;(8nT<52=d|$!IlQa{%+=6|bxvuMc8-fm=1$~E?;)UK
z^28Lr*%!Hu>8&}6a@x|Ez{hKoVu<St$Yu8b#4xn&a7>~bG4lK(cogEm?}N0;A*g;8
zALMyTplC}&jLo_M>Kt_pw%iQMLGY!PAjDcKH7sW?NC*Gxu%E}c^OUJb=?y?DVdbzZ
zN`(lrd$}kkZ+5B!p56e_eJRTqM>Xyq%?9Zaq__x<>+)r&CM2=gGS{?h;npg09?OzG
zSe|+n((M|c3@cz(O7|AXimdQrq|I_7#u_6+94UEi>B-0(u?iIM%IT<$%|tS=4K!C<
zpsHMsdjZ`9D5v2jE+wd-XR&;7ZwqvR5CETA6X!k}FmFR2EFAG(1HK-rNOhu-5Ith>
z=Ol;dd3~!~jnBg<q=g~^M>G&JoV#ibQm8G&w#Zh(C)Ca%=W%s`3n7<hA$A3@Wu-Y&
ziX>84L7E2skP=iNQ&0@K<($PPD7-`<Y{$<SU0EK$jmQew29_ZhsFH9bxh^U(iQ>&X
z#)YL$UNSjHB!R5KI)xavG|`#2q%Ph{hjwZ$b&E3uG?<oFsZ!)#)m|vEt%}OpW0Ihg
z!!p5MQNPU3!6nF3ffp^65n@Ocx^;o_G$Cpskup=gYQHNRDWoJ;8*==JkX~UfaTOC$
z2}!)fS4acQz`Z+&tx}*S*m4n3pg~X-5yX~?+ea5M1%^+?Dz>0dH2YOJps2?ibbLAm
z{O;gX?M(cr^xlab%?$1^sq)5k$P;qLvO<a~xBcE%Djg0eBse5<B;v<Z11L*0Ro~XS
z+D4SjfP^0uD~1Z#67JN*0MvLS#1dRi=F<*xnLra?et@TBsD)1WHun-8)riLqr$M?P
zNhDRIfRo{cD^^h-5qWl{azSjufH=@_6_V2}6DGE_XWu(p=tSxcTE;Q2_)*@n4|vnF
z=<{G3HKS*G5aSHCpztL$iOhgWC>d!ro}1;`4M?wnUnzB;!-l5guoCPF2|4D$Cb}B5
zB)bF0Wf~{FlDG6MZ~1XE9|rJT&Es#C4kFP6{#{m1D^YD%u(1P(8SwO9jg+f+B$=o<
zD0YE239;^?WJn3ExO&k^g?#9jUsECQ=mx^C5DV@>o=lfE1xgDwq6vO6qArIL=^4Hj
zvc}dcv}d**>OrYgQ30=uB50iz+f7)CbrL|KLJo52!4xG^;MTy)Gejys5tM~y<&4}F
z5#+Blu;x|JCh!}5K^~=Wa!57*6QC9R?hqnMuPiiR@g1VshT(W5pvX;><jJLv_=r=&
zd45%G^4z7mULf`?C^<-%%+<&Cns^aN6{IG5g2Lkbp`xAvZj*@5h~6Tg1rtRr=;C#G
z22{B{A=q#BcX+$a!OzmSo;qq`J@r(EaD7<CL&(@z58uW`%MxNxVU9Y_lMbB%Lut^k
zB_U!gK44pVe)gqIa{53ylM_&@XVVmS--j$i@b8^1?JQhC(otGpi@QK0gGR6nwyyoa
z=kY1pQ{JM@5mCGcPs(gK$qrj>%<c+xFj5A55tp$Rc@9bxFH|fd(j;ia@A1STEGi)y
z1{pV}o7fgyh%mc|pOb^hidZjwz#$YBjpt{nF5N(q^))4c>m-Lj$8M~;E)Nc|JpybO
zMHMM3ldeh^V!uShN>BhDmISSOSn7g{y>QZzf{12m`-3ogf*addAtV)Z`AfYF(jUfS
zT;S^Y$!@CHqFkZGwIrOyj3Nk3?rWm+s<0HaHB71BjWEU#w=^X)y<Ln=oX3ZBBQhNh
zg|L_%3S#Qyfpr9zsRBf3#@@dr)i|#j36keyl`6@4)|Uk5CVP75gU=XH!&5Kg#(P|V
zc>gcJA*F4<5V%IBuX0s$wQ|RtcA{Mim*WGd3Jr@17aZJr1P`9DN$xkMnu;}LYa+az
z9_1j7`fIbB`PJ1Xq|0Xoi3%cWE@(t3o5uM_p`%VTtg~jVtqS52YIIfP5z(?oxo68%
zyE%G0(gn$J5j~vaPwR9i=nemN;NmO<rV~TbO?V9C5*<?7GlT&Md=B*YsVZMu8PB|U
z$8yPn*=xz#syHys33x_})75Cv*tlo!qUN&Zlh~`0sql&CM2)+M*~0}b0H^M_u3(wS
z%e}H=Y4X7HhN3$jnpzHr_UILTM%Xn@mS4<oVX#q!U;`yDNoNtX8@T@<y(l+kFK`@q
z8eO*f@64v(o-W$zh+T0&+aZti)7LkJ+23cYua4P@3b%00xN#0mv@bdJ2JNrp%ek?s
zt$KpI#jfKlCYS`?T%<<W+bebzr!B9J{MYgk8{!#o4({WXZiMgkpK`7uTh5w6A-zDg
z;&V-5=Qr3!#Cnays3!Rt!vD@+dZyv$<3f&lVZNkMvm`wiBpt*u_8yzL?oh2D#HPj`
zwi&hib&0m&A1D}MruF|uUj<trT)C1iKlTBXArf)+pS6V|e-{SbDw~W_La$y(v!}~*
zoqcQ~EMLF_J|t%+?zboHXfMU8Ea>U)?En3JOUdOT=M#jF@3yJAe@yL>Cpp;VlduoJ
zN+lXQHg301?{LK*pKEnW%`Xu#^R@T5;EwN!bC$Mrx#i_6e!*%puPVYwE7+kl%fg~t
z8gs=!E58aVOaJx(FO7BqXL+O5JUX-^cYJTN7<+13nH7v`u_K=z=IMjn?c;E&sO_#^
zk(A0H>r2`vDsRqK!Yr=R44mx)5twIvUQ1%l15fR3ndA(syV-U6!Z^DcKee*V*1+JE
zyaxz#)93NF!>OEb4|TECgC&1wqVGKx)r)rosLr)^eb#)ZjNMs}gqh}Q&Drl1vtySZ
zXSd|vlJ>iuNA>oseR1(sAvh6!<MR@G!@E^|me}q%;^g}DTgKTUcMrK;+T$#{Ez4Zk
z6Rh?y3pocYJpS0rtof$XvZVNFHFnMqf5|>7Y8djUp6b#JY#rTIrw6+?ZHE7kn1}yj
z&2$sumXIC(IBy>wN3+l4P4=;ObV`*3chGNqZ-;bF$v$pQj&2}rl1r5)R<w@Y0t&6@
z##NeQmk>b2@Hc;<culEZ`l~XB_#$HV5;m|a1h4078=;@xL(1t1T=Ii#xpv?qMWn7z
zdI*l4J;8^QrcsYxqyUCjiD>-+EbhX``cYOsU?ED@sM`m_&+-&1Uc>B3e}+<ffN(J!
z1+5FLWp8%4Tr%3{EB-&MrK8s?dvv2i_A-ylJ6%fu2b{^e!c+DNUapz{!d^wWv_4$D
z(UGoP#oKd!ns(7=muI)<*G(s=LNd3O7<u;q`Rb?(>0NvkbL!=3E1b14$-F~^IGm-y
zrj@80<F|4%Etr<ng+TWg^HCwn1ZWf`)54B9#k7w;0E2Rn@nMAcidWHWd*ZFEJl(Ge
zLmc#XC1q3rG=pmo0W+rFV|Uq9rD3~0C_z;<GM3s?(jT(lWpfFc>`zCK%=M7n4^Lsd
zpzn$r_cn}(aNw6W2irkD4s{YbCB=<dsqpiTlGwcj{xT(<f;>O5j-n|b$RbQ*IKGSG
z0dorP3WdtDX*#h87~hCbmiuFMRNi}sJ3*D%K%RnUBMT&CnTZSH<8rK+MRF5*^28|e
zmiidRg{GAf+$r!*@YeTP7*0Z4Z^yNZOU25tWETf-A;-jo5{vEEr8C}Z!uE+w5G16Y
zw3$!{bgRd3I7oH{RS`+=>ad?mikUGy%B@nS{jBH2SVFxwZw@ADYS%xABNsOfQ5m^6
z{R;fUm+%Ba(gIwzRxSA?$Z&9T4arQ0&d)MaqHf@&=QIe-LAx%;I!Me8L|HqY?e5tN
zXsrR}Nwxnlii9SU*5wElNV=fz7jPQjr*Z|bJr5MQ%@b;mP)0E-26ef#s2&l1x1DE?
z?<h-j&O)SFt|(gPLon8Maz|bzpJ8sN(9seh%t{@%_Glc6a^R=+mm~=sp-YHVMzyTC
zK-(3z6B&pRx;Dw&r|RW|LQ~IHVqwX5r|Cl!Ep^#$p`CR$gAw`xMQ3ff<?aEpeN&Q*
zS%jvrPgJFZiI8<1-R`955D9Czj%-m=`)*Q5z${nMZGuG@=qR%aJo4~+w$Q12O3EUa
zgb%7iK@vI2ZLOk;Q(e<%?fFyrV-fcYrNyr+1TX^6lE}1FQ;gyVY08Z`>L(65bX}Pj
zp%todVq?zY7a|rkQA!%0Rw$WX{>|9FFFG<?ozOKO=fEg+bjMPx9YXI4<L3B_wA2ZQ
zm>@6r+DQ1Qmn<!Xh(k{>9^M&bow|H!OwB(Iqek9_r5fHrm$Q1E^{>9F-7l22^plZj
z^Af91&$j7@k2*`fF=)zNZ@>|pDm||cPOb^ccrv+NM;fRXTD_O(58=FvZj5b@C2#BT
zirbEsWv9g{iOJ*@r{-z%rG(y?PAX9saEcH1y&8^hEnE0T-%$cw{<;)V=shu8Ppiz<
z>tS8&356@%6sM(3W<S+h7L{!N3pom^2DiBemg$ilE(>S#tfxehJ5RGdf0HZn2G5b!
zP?p(s<0_9{Ahprunm7AB>gp3pfE!@{mX~Fah)(E)DrP$fME39c9^J_CJz@UiUx;lT
z3dON-PG-BF&J)=dE48yn^d$o9#{owh2F}|xXoEj220i&nV4Gd}WG#6>F};8+7oGR-
zFF4MpIg(1+s}_p%;PTl;PDC_YLv1I$;k)d>>}pL+oQ*wcSxA^b`P7^0u6aRX*?GU?
ziW@JWi9w_bxY%%}m+01ii!6>k>6M_F@D;f;8mW~}UccNiTjAuBzAxH{w+miwkA3Q2
zr$Z3(_u04PkXGHq3}&m9zyAxCed#Q>zi0)U|M}AgZT8JpOgu3^Y5z=9-v4WAciq8F
z-4u?ON8X>?!l~xi0GV{MgZd%7yXwf|9=-0=tcWkVVYY@Vk0(A(O^_<SoTfM6242Zr
z-FLC=WY2c?AFAhaF=TX-9*t7hjzp(K(><_^C>2|rGK$yOzSS^WcZ`_ojqKUgg?{t9
zUNjh)h%K*1qREHuVSnzgYPihKwQ!oV&s~zaNOrr6x53uvo4tYQ!}J(qZP)?f=J#6b
z;AK9!<DGkL@;|Z0huLbAU;BKp2|w<$+K?qv?{ILc<(hW!mw(^g7DzaA_)C~pMQu7y
z@(ItJ*F^J3Ew@*_Aoa!fa~EIeliAu6{QHZt`mIm!(En|gTX!-8&`uRFlaPoxAO$4H
z+reFKaRQB_m&x5bilJ(nkWQEx$o|La36Jf1KnJ(f^Fxe}O1i4#u8Lr$SH%j4Aqm?i
z7G;px>bh`SkA^yhg8dYY;?*c~NvAeq->9D9Ek#&kZ+?C2l@(hx;X;zx%}nO{SsZF=
zEkav&CKsyxYzsb{>Tm5%>L8WrMCSFPbA)|;`B3>PoRevm-=QkSmh$}A*%X|!l2$$W
zsQq5B^m`Y08TdEYLor#f`fv+cxi3tQSnm&qm4QcIFdJ-c{DtV^$j&9-%6oh=wSL1-
z*c-;JSgN`6Hmj1g1Jv9vrfIupmU}z6PpHO2gG)7$JQdM1u4*33j*B8~bb>5!cl^jh
zyfXNpZdFha6HBTS(B&?+ZOClMwVh);<f0r-)-pq~*>PS@!|ZS>4j@D;3`gD>{Vpn4
z@^*nrIC2qTxUaE>e?dp^JtAI#o;Z8jgA}KrklI0oz^a^YDI@}xt*7KYcTvfInS3ej
zB)@c=mN9f;#M}M?ai^^S(+&kIFI6ch5%d^nI61?jqIv=l(<Y)OHOC80))x|zD<$M6
zV*~*aL^7q$@MMBFCifySvL*}0H5mp{u=5pFsZXx$VWtl<<Gh|#N(~iw-sGy%dx(pP
z{U>6kV^zfw7&yR4qWEYeds?yt%t|g@AXPoBz;O%ImC6^wS1Ub+E2Kos8FeFO*P{t?
zD^a*B>NeB&)GKf$_j-TG=8!HSGr8mLxz8u&nWbvyB$5PmJ8+(d-C>e0VxZeSl;ere
zi~(yII5GMJzZ28TqGj()0xy%_D0rpG%*_+HUxU^*?5XA)hV9-Mph765hmxO)pjXhB
zsbl5oBnTy?a~?ib+X#_%)2gv2f-b=%XIdb{dQeS!f{3EE|F0XMXY!^?!lHMQlyaiU
zVY*N5@q<k%cB%7B^whP{jB*c@@!mP%NiyoiY%qp2QZMVkSzgpUE~^Yx<V_KC0`tAF
z*(^k}zLObJYz<yf)Qmtjiha>niK_5*Xs$cAcX>rud*$rTs7CyQ3gn@|Wl!u8gZvd#
zUq523>PglH*Ks_HdsE44_b5f#PR6h{y4DI!UStaGc;i4aM!fg}X-`q89GQrWUMBB$
z5G-jD-=b8arYl}z5W*o@EEH9;s4}OVLA2RPP$L#hwCc91y>gsLyAIi-2Cm9DRAy_8
zVqw67Bh+1&8Wg)h5D~EXXS$;Tjdmhid2>v=^X>RhkY^)*`A-g7x^%bk%sARNr$tri
zl=WHycY3p{pv^I-8EdPNT)qG=n4}i=b4n+#x~a{Sb`B^Ev3iFxOD9`DOSN82?B(rb
zfvLHnX1`mmJ_^!@VlK@~|5d4tOqPGc?AosJv}hU)c1)u+<#>){eN1pgr0p&v*@)-t
zI^*P+toRmG9?ydC%X6&s91UTsXIjnvnu2fk>nS(G(3VfL+QrdG_SQH(`B3Ys56p5B
z*b+*&L_@A*1yzL4&A~n`?5UCTpsxi6bu`r0MRWtdG7e^Ua0$jaXPXXMcty@qMyGVE
z0@rsJrZ5?Zp%!<g21c|k{`l@-cYbv+)O0E(fJu{;U->!P@u4?ldbi1GZB<p(=03Z-
z7W8IU_|tRQE&Z+{ctS0`R(4S6rD}pLwtq3Olx6>x%5!`g-4H<dS&Ji?mgp9<Yx2r&
z!d%OD-hHp%3qs?|XM4MH0oNX?((onT9BJ%N&&|@gM^e`{w<YZ<ztdKHYbL$@9;yMk
z9EL!+m9r=Zk8$+LfxU%YfBJ%j%WCvkkLfviU)D&kFuoWFUUGUdfA~G-o8Os_B3u4^
z%IzU$5%|7GTC_^e@uxmK{7`Ybd-)!he0+B{l<%blbOTTA)JHAKhv0ktKE7%DRP}&U
zLanwIl*=UQpNwW<H*x`vkn}o1B)Rh8A`R^nor7BntTfg#dBT(f)e~2?v7;2m%D*~Y
z&otN`r(?uyt!!Nay6QKwU9IW0Z)(s}*uxduX!w4)wGexscudV>Jn#HV|J9QEYE4f%
z%g%aa-X2~06>A<mb2j!L(QLiH-UHh^8LJ|jYrSJnYyPjWXF6tU{W*(vkZ*N<@-2H?
zcGd6$e8Tx-&KCb=x^PEnbhRP3f=aXIzS_b~fARu$PW-E85UE*<{{XokC)v{YMUBI(
zwl0>B?QnkP)s`LmDs7l^Xl(SMq^mv{t>sB}o6j#pmBnkuvIQht?|klnRY`eAc)We@
zcB6Vl$n0*^R)OqCPS52R2H^R83VoHb!>^BS#8yk~e3_~Qa2KN(7D8LtT5E%t7_r@@
zV^)Vm)@cW1lm4K3HD8C6mU%J6Hb;(H^M5}PaguV}P$O>MjS%>qEv{~wV0pKN5Ow8k
z-zk>z`g4n1#zFlOO9jzv{b8Dp&YfZhP4&$q$KE??=rf-U_zR<5+Sk&2e|V7-g4yba
z-TgD~xu-}!GY|r+t#x~1Fy!Tcx9|}Cz!7H1Vik?Z+g|d4{L4K4P;T*=%UQ!ZLnGG?
zs0yu>a{6r%?Fxw95R&RtkfQ>>rfsU7?}P@PC!My1z?CM+5b@b`EO%UM5_D2+fA^Ry
z9dMdLchmA#RH;ZD!BjX7FUTrxo+p^46r#6<h-Mkf1NHGLRw=iFV&ucmBMz-Bl3VOD
zdQcaUbD3HYjnnf!>SBoiavP&vyz0`*;vhV*V$_ClB>WCUCm@?exllk-DpoJIIEVy!
zx_}pNS0RNsw-F0P0f>dUqbrc{tAvW)lVALX;H=h^m7-jCz+01fB>B9~auDSS#*1}@
zFxH!n3>fsJi}*ctzT!<q*&aO6Sf^9mLISpaf<T?|T$l93D>N(~vl%P#Wc|LXErDK&
zk?W!-Y(mum)V?@JQ1K>YOOQ$cr9w{*M%9r2XOO$3QyT6Mit0xSJ1@VPj&Z{Lgff{b
z%d7?@4|;@>JC$w&b%Te*WF&bZ=2u`kbBd)*$s&Yl-oo3UPeM)(5FuhIOUqby_jq%g
zlZ|QYCV=vlm8<*pPEgztzUci7)H=rZ1IW)>OETGsy-!l3&mElr8>T{pPU_79t>J8T
zIC;@fXy3g|s*-nCTm8W)EW!$f??CeXHETw?k#!ZB9@YIYSp~(<HRanDLhdDF;8*A&
z6U=$h8@8FX<8|8f$&9lbqe5VtHq}?F?&Z$1K)p!81IHGf9zG3X8cHdRcz$W%f~n%T
z#kRtITcCmv55YX(h!yWd{EIpPzT?>PPI^b=QadxqSc#?9A~NW@mh|HQ7UQ+f)yb8$
ze{xq4jeVR^{hh#*-rHg?5b4HjY(yPuBVuMAeUdvsHAVk@^kvx;Oxr@nNL?oMBnO4)
zwjvd}4Yd0NVW`0LGNovGer=w(a2t{1az#0(6PxiVk2*<6-g1_Iu0)s+ds%hmw6LIZ
zuioS&5$R(wdp){ctPg~21N0Bj5j#J{Oo<nPHi#?1|L3x9^iyoV><ZAb<^?{Fn}p{$
zqq>vgI5V)#3((r@^N_91TfX}8$tsR5!AfPRKXatTJyf+(^W=~7j00jnBFB~x2`Ixr
zezsl5C&heFAgird%Q3o)*VStXZMc*%NxKf$U0cc*ExQWkO(^AN??K!iTsj>Qlq#?)
zO?4jNLX*8e=&ni(d?ag6avedK^0_KLwi2vVy9GvqYWq!WBwqcc38LJ-Jk?7g4Nve)
zpyC8;U1f<i2D2N&rF!7z&8`DUr<!mV^BwunpcPkTFJrVyO3`dz2Y#L{Ww<d&Bz||$
z@>(u4@xW8#IaMV>`{0(m{GBUYJg)LD&f8fHfU%pVhD7<uAF;7linvKBIEZCX%XbU7
zE9EJ48wkXymDz-9!F4xA)GHT8lJYB@Ak&A}@eB7pRII%ApRB&>->)r2tb!d%=L2{9
z*yq$EGE-aQ9qM0wrH{2)5nDpY3Y}i;Js1x2-kx~6n3en1OH8l$7!hIc;8lSx>aIKt
zHhJQ$@|F9c{Tzw$!?dNm^&h^-ynA9W&3>|*8Pk$}X7C1YDIG4WtvN|8J^FcQJ~3~_
zBbNqSdDKb*yTYOlyD1mR;@(pkJ$x5O)BxAxEOy^>$wcf0doo+ath4NyG#*^Ec>-jk
zXic+OzSm~SecU8GU#DWL6yAQgk6|E2>Lb&qSJSX!TTh6(cpnd9?!AD&^#Q(fgY52w
zPp7dmpw}s}ojF96kDHdEBWt-BCBv=NB-cuEI#rr~^m7xLEnwh`tt83v8_&1w@U5ij
z#y8}9Y#)e@OfPD+^^L!IkKBQTBL^?DzUDj6YlYw4kpzXL`&c+~@4U&`ujTCJB*Z_x
z!v>x{x4G2#q0_6UKL7r;!QXn{v@MM9E)s1LF2BjsHGQ?sz3d(=+tmTSt<jQddVuV1
zpRh@|CFKrF5o<s*wmUVcC3w8LZF?=n62vKPi^+$~uVG_9vLPhf)8xS#4NKNmEBXHV
z3>Qy(u}=+9MFnCDxbofVj(UK|_8Xn-{;lg22s4nRmf%>+6|92Q`bFoGH|{}cHG9yC
z#r@i?Yq!Uz8A^O9uSAt&;}^D5Y<F8scvOq8r;`ZIUuLjgl)orn<(R{v<}UBXfdsa{
zw2AW7pw{IBlBYSJ`S^2KihZcoR6y;?ON+tu=7BJ_JiwFQPtyVX0$ZI2jxwC`2kbbf
ztmS>M=mzv0&A_~mR5@C&g*+;vO65C=+qz9FrFTM4c6S>BJ$WnIonMn7#4!1Ynpf*h
zF*ah2#huUdQ^M<MK&ld<VpyO7si`}-h~gz*c(gq*2{Fti3FZ=H=R{19l1EJpSo&r&
zN5HDM#jN2Aa{Bl%$Jqt+{SI?pSOxi^Q*d%ekla2A%5Z!%L<1vo@oAM?p`|gWD<o{;
zbId+YC^(R4B0*<3L?K?XK#Slh73^XKZ3`NZF?5(=-9jpLh!%M(QAm;CXKmqw=g9|z
zc<p}a;CXjB$U#LbU~Q_rT}C_R=-e2~8FhsstK%k%G8RbC6Hg7t4)dL&S8y-o=?WN3
z6;3VEBU7*@XqM_Uz9F?+-ov;vG0&f^&Ah0>Eg?k91>vStuH{m$Z6Rw&c#_h)Mwg3%
zqeO(B($i;&rilQ6mp~k+G41K^=_%m7Go%yKb|V=M@<)MmUm6=B1U2L|ivkXrpX33|
zT-*oIOfR42A?wqSTS%!Y@I~kA;5*JzCl{gqRwtm_eHH|_8Ohs00zw^?J)oFjiOm<k
z<gUJ&pxigf1ycz#3Pr3~&T@8#(2+a{x6<T#s;uqwig5h&?pifYZO2fg)pSPm(^5L&
z+ukP+D7xlbeh(?ili+rYG@fR5R?HI3r!&oB1q$h>_B8{_*EuC~aUw*`*?S}%B{C9?
zSLFi3tUB2=25)sy69tqFF9|xzQ6QYwp^dm6u$@cDzJpMaygy9R(?GJXtxjcxa@Iw4
zS0W1zI!)M2MfbD0Y!X%pTN_g+ZBMXrq7y#Xaa4CyK;@3G<RnkqQw42(oxudAJ-{JN
zEPr2{lO8lD0Q3?`IZaQY-KIb+&BdnrDMqbHljp^h!y~jWQ#lv8OP6ZqYIUXdQ}nks
z*T)!t!e!{O&k&-McJsh%p`>bqsFgKe`M<$F^w5ia(@yS49P-sZYGMTohx+rWuMKdX
z%D)hBh-XggY&JB%t5cfi<gRIYaq;hI({~QIs*oSAK9-|gZx3S2E47k2v(;0v^Dm7F
z)=TqhHBcUQt9OHR2a)%k$?5H{swzWYNJcFASS7r=(K;txwzCrHoc!V-Xy31ev4wMQ
zd$71{+4@=s;U9$EsipM7ZE*G!;?!$Ax=#%sRA7GWPq;2D)w6w+^pls)upuG~NqS0=
zg@2@_{h-fZ;m#yO&v(}M<oWrI)}@)Vn~TuDM!ik@#9MR7oc#)gx%4wc-Mk!x5S2kn
zzxteN25bM5^z~Q<JwX5~4iYAgQ>)sFE&hjNAatF%U02L%xi1T~Yl|@Tw>1=l9xy+q
zwf<@sKSjs<$cw9ofy~zXdg2LEv|JFnka=W$iBh0a3uGi@*HqnVxOb=wgKxF;hELW)
z4Yn0ZIck3R8fWK&KY7pZbA(cyxx?25!XMndWVe2qhv^?(OY8WFEUTbQXR2bJpG!qT
zYRG>xvj)c2*bO)5L6s-`GrQ6$D4S%3eE6TK)l1&&(fL#S=oe4ThsTcEe8A|k@4V2G
z$)^%u|2WIh_urDlFRGJ%Yp8QZ!rZT5M*YWA@~N3Kt6Zj09wbt_&a!9u<sHL~tqHYb
z$U}UERe6z4mzkOn$ZU!cFMhT2S`RJ1^&IlfjE^HWuC12y{dOuLxk97|t=74iNCDdd
z>}G@z*-{xgb+Dt`KFt+e`J~Oo2nxS>!Ervf0F$Wx8<n=7-MUA<&t#fBfBaCDd%3p+
zN6Z^2w)%hT>kqGCo@h93@o^#f8ia`yLJcMr&C%67hGhSIX})|VJUuZ(Ut(|ZO~Exk
zO0(IMeWys9VK5{Z)Kg>4(QxN#E!YRyzP$Wds2m%x4}FL)Ad+r-XtJ9sdp=eCZGCw%
zolh2Hzqy`30#z2JtiM(1tP6N0IbI=A&Bz?qX@qmE6(igq@UWmqw7Fm6LInkyT3hAI
z5x-7hvULGxXs4o_+SG)%B}BHwii)-%PiouC1}Nf|lkkr5R1y6#=B`TD9lX*)ZNkDz
zJCm&;?=}!Pxl_;2Bh*5F98DkDl@0qp48LsVu;cv6QY^Luzdr--&RD3)v>3^GtAk_l
z@+^@3y)G@46>p=gAqU&nSNi!&(C3qV)8pY6eP?;<WIU>{(JXI-q1nv8f(G&;zTF*O
z;X)hTb9a^7rSzxsZBG@n)iq#F@LPjSt{mZl2HRAVwHP^~R$V(t9~LZ<7^Jdo1Du}?
zz{-QqgLEC{)ODbKXDT&G<SaP1hM>^G=5kMW&8nb=b?cF9SSNFU?53dwzc80rb3uZq
zc3P$_E$bk(K5IrRo@fnYno%)AVOx{eJzdVw&@U#z=7$*~?UhW4Eyxt~qgDn`bO3z(
zx~%ZGgLE+kmBCr^L&%6#>bVF4KbgzQry$x|m2<mmg5vm9KrTgdo`C*g^46?m)mym5
z*Z#_?FANAnJL}S<#1+|f2xu`{(LDjOR*=%=Haed6J)<qBjWeT4p$XA7x?U*wLKGeT
zdAT80k=sGCK*P(g1V!md?K;?<y1A?X-w73`c|1j^LWUWx`8hm{02pAAiI@*ZUy!E5
zYQ2@tGKW(yYDNWBX}7u-S!<3eLV^x*-JKkluFIc1W<#jMtv-(Yg}^-u$X$>V;W*AP
zB~pfEyFR1rD-=M8-QHw+APS;Br~``~$Ch_TOh^8RG#n;SUW8N;o8*8|1yK+=Q}dpi
zSDH4eiw|A=+dyRL;_T8#X;KYPLpynFASWgTrwt47-tVXBye2KE3(JD$iHDKN#SuM%
zxTs8bD!L2^HYM>08|_pVyj#FQAtDMbAHZxn0nfu`4ca2F`L}fJBgQFKg3zNy5NWRx
zhos-Y#}U}>n}hNZ(<lho#J&pZ?HW48<Ja&vuxy8|=gs**bZCbwpQ@ZaL7Gq|%56oz
zP4lG1TG0zhm`4X=arrq&J@mb*MA`2_g1bv1DL(2E%h!|4@v~Bwb(>MXtsoPHNhTQ!
z8P$<oSj%l3$Pk|%=MrAL6^#wysz)r#R@L$lPsMV$66x_6k<BLUO>2Jc<*pUkeO9Zu
zuafgpet*yU3Tz!mG9AKeeOjXJ3b5@9?`00-a}{c{^#|)|h*(J!vC5jI?dHsp4G^Nc
zI44_S`N0paCVa%|e8O(mN%~zN5TD*uq&ef8R(L^PY^VxrEnv+tl-{%$2_~!4RPF?6
z{qt;`0bYOhqn&nZ>z9&a6feiA)&_Y&%d-MUS%()dWi~NwiN6=6Tuj27*&@&lf}Y%s
zy*C(Zxvk<OJd&mVHuyt3s;QPyedMAXP)q9qAS{-YzZxjkDckQZiJJ;f`EHtgs2uQi
z+Uw^L&+NZEuzNmsb4`Exgv?f+H}AJ_@m)ddXxa6IXjVn1@CdyNz*h3LvTM>vT}Cl=
zl=+4#0!u0n8&85Vk9=wr6_Y9Q)_?cx$YsaR<6|usO&5nY*aKVghI%-(pD{h=z5VA?
z3ynhpqSX26IhetO$D`5{;`e_o5nD_CeK9`Nz&I^GaH*SJ{Fl6NKixB({=;q^Se=ZQ
zje%g;W6PKSaN3@b*0am(%83>vl3kPb+qZ~b7htG$`)}Wk_4T6~)BUGUvwgXe!{`bf
zxt2f~TTGW$KlPj_U>AaB%^&UM8=9cCOC=`2Y;~)7>Q#W+t-JcjYd>NoJmQkBmOaC~
zauDBkeLV4E8~5DyzQ{|0xELRe;_37CsFt-{_uQqXOe4O^Y`wZQ%A7^0m=NmurP_{t
z<RB<`?EVWSKzGPSA584X?4C5d{rz^Y`YK@2Zm~4xO+E<G=>j{C@U(n9X}N(pn|ks$
z?84?>3}oXo2WE8qj}KrBpLJVt+XFu$`%D&u;dfa2A6HUde<i9oYPT-hfQ?UnHg0Ys
zXd4L3V_bi2vf%F6>9b^4>c-|I2YlAcFbuQBv`Fsj^J;@#AuLtH9S3H7VKt^WhlfU<
zENR&@jb`iUfQC@OU3M&?7c)*v@&okQLvd=4h|#s3#SyRP%hjmzo9#YS_O_tOBb$6p
zsUx<PHxi=vb~i#65=+8!!yXVqv(!lqJwR^fWtsgXZCE&s+*NAJli*_7N)c;h0<Jss
z^c-1ASKm+nu+lf%$5Rl)C<^0Zol5VXD>;$MJ`#9vWQ~f{p=5%Di1^~EU3RpqXj6$f
zyMck=&D7<oTEqOoqAAXR>RY@1c^REB?*SIfT26Rvt%-_F^D8l=yfh0poobP$NGd2C
z^D~+%PlLQ`z=l&t>ID+?2$i&vx(X3+vDM%xTuc78J?o+CqPLwvxxEWqgA!sKa_tG6
zu%?kQI^+RPn?0dK2`jAW1NTHjBrIG+uyI}1SP{GId2q#LgWxNQ>!Vm&Rccr8(ee1;
zAmP?95yJDU<OvFhy6AB6N+r+o3JVkTX%2?nAsY^f+lWS?@V)F14VaOpS@pu-m}Q}(
zQttd?$mXkY!mtv^T2@spZqF9RDjPeHPKrZ|ZD1_dRMkoduEuqp7~P$@`A+s_Wp{-p
zGYccW-)E>h`=FAxIr(QMRczqTW$Y9tzKD+r3FC+nI0as$g;F5>U5sH;EO_}`;sc*W
z@`*h358WV{^h{o<ZoQ3<T}aVss_QeLf4x>cBW_bbe{h@p@|0C^dF-=zxQWVm@UUXU
z%f%TX-V~f`!X!nQmnf<OJvY`7QY^<*?G<&82czCPY6#IG)g-BR+#-A3D^N_FWFjKD
zvlF__eX?n@T9x3KNDH(jl}iLqzFboCi|dJ-F!THg=y_S;?&oYp^+w37o@?;3%51F~
za`2H>sd*)6LoV7(QdI-wZjd<AaWZMaNy1L-wt{BZDrQr-Gj}q?QLn;9sHBtA#EF?S
zDg4r~WpON025xFo#hN1eSwqZuMzXe^*V>Ue0zE(7D_BFJ?P**U`-x2=v=N_q<B^>q
zA7kKPlN;K1IGG|DUC=lgpv*%EbpvhIY;KcGC}Tyvxk3X*7PkmP#hG-^7w`mW_S9B6
z05kO41<Rs;rYJoV7<BY2^uVQ2Q_n;=A;cYfQ>zo?eaH0)zDU+!plz=uzgiESdpYyZ
zcaaYU2WICm+H3s{j=wHu^3VKS>_QjuIvK%db%<<tcbg)^{z<epYR4-H*tA@IgHuQ}
zE*g?M4c;5z-sI{e8D5gEcTe7!uu!%+ego<TXG6P6(!2U*KaAO`&SD*!SQM)-D_kce
zpZ@{<{^x2a(_1sxVo_s(*xSc~w+1I$gd4I8sp(11*mstfeOtD2Fz2n;Bn_XK3HGDJ
znLj5z;@@CN$T~!~yf-hxM7R9O9sLip+G>4l5|*B6GjIpeKa5psuAJ7mrU!UzhCQ0%
z>!@*zgCbn{Rr2vZ>gk97(&CX!;Q`iG<0l~x)ldvpPv|?>r5E3l<jn_C02Qd=gz`B)
zQs{PB6hfP=-jg*bROk3`XVY?&$EmF5DLVI^@3AK!q7WVU*}&a}wHnj;@;t&^*l2nM
zc7yP|+h+VK{b=!@&-9(9Cnh#^Ah+fbIEaZtl9hMTC;fDX6}t{OtGALF?06nVpUA>n
zzVqHzcHX&p{?RYzHuv#MY)&ux?)g5F?HP9I;Y-XRS+ED_?DF44i`^jfC3E-xbe1t1
zWyxx5quL})GNg&i(Fnwe%4S;jjIFjCNg>9*T=t{PL@4;PUOUg~)sA@^IMvB)4bgtQ
z|MMea5@fdWg6}{WjjOH4sl$YbZJ5&*-(EmRMyVafS6D^8PAZnmbp*2Wn63WGuU7Kd
z<L@f%z%h1ZO8sh{<t=Q*{Sw=k>px18r3=qbPTj{h>tlIzWBrLMI57AJ$*JLdmKZ<d
zBYGKL&BO@x(%~({B=CEbkDS^h?t0&lPshAnhNfKp)w5GOWp#)J+JW)(rJqlI%e~hv
ze2Y_?Fk45ID_1)+<j0PUhOn>CW{z_Datm@@!1Z5$?YMKdPh0lLE>2~cbI9SUM0a%t
z9CXAzEqlgf$E(EgNMD(W&<o|;={laygB^Hv7{hE0(S8hrb~*NAuHCvt42i3)uvG|M
zGj;s&4z(_K&2Ng+8e30o!thO*HVb)^8X5j>dRnj4a_Akj{$6_q+c5ttmQ6J^YPrIa
zoVg%I{=xNBtiG6YcC6-YnKRfN!%dO=bZr4P6%_5exAKz3fQS0RYDRIC_Y96>O+85_
z!)I;D{%W`9)%j?P%-WG#Yy`8lV6_#h^<p7RB_aLh^Tw}Vy_olWy2D~-uOsC?M*MDQ
zWW*obkR(L6OHkJ0hTv|_PL{m27-U!2t5SH3h+`7V2zD_lq*L^s9{tD7tmb2AjC6WF
z^af}zPKZ_56k;p7ysjyH>0m8VOUoFf%LYg@1bT2mofPJ?1oazYw{tp>LlT%lghJC-
z;{dGzlAVp|T6j8HcRcvL*24FAp*Ra}5>0)OaeT2Nv;_Uknwx!$T0nPFxRm!a$s#Q9
zZ5~i6=$Vl5B8+{Q3hIU#n~<M9oyy>O_(l9cC~Vy`6Q3-kJ+)6E25nW2u#`kK4JJ*I
zQN$URqle-p8suAFrNj(=J_IbO7FjT`l#NgcfonTZ0^df^hU1thRDEm=<}=DX$gq}W
zuJ%2em2++EDi&4g<8RH7u&ZnC5gSW4MsMW~^N6>Le4O{Q(X{eWNo-<?`j3~jq$P||
zWXx2cD(DDO%bE(Qxzz2j4o7dSzlIMi6EV0mNMYXNHrbuvgn*n~z}rh244ZitCOSiA
z^H{EvwqzYL?+@lX0o&gDt+iedDm0+vm&sk{hiGgEBd{qYpzJ8+Sd~d$!dD0sf)_5x
zx_1R3u0yp2*?U6nR|FjVeTk1YZ0-o4@S>V<ZU8t((Px?jMyWPLZs8nNCT4VoR5%uA
zhbS=XBdmg;8<A$s&WJvC27J&)fiANPKICw;xeX&EpkX@>w`ie15S6v?m{MSbTIz9Z
z3zHtSXn<42z+`@}%Gu^rF|%`<!?yIfXT-!Da0y;fkywRuLA*Jx0mb)|fki~9GP%Ot
z^Xm!130T1q5E)5d)EM(*Y?gZj-@ZTdrtkA+LE%o9E`Y3A>Oggpxv#QC1H9Jrm~0@C
zND<_#m|;|jvpLvOteg=b_t?($R>6W!B}LV3mf9pt_uSre&`Gq#z2DS~l#SqKxUWl8
z{+8Mj0f%=l7Vd11y9YR+Ra4ZMtoDuXDfya!e8-X4Pt7kT*pI`j^VTSDB=qQvW#xI6
z8i&!|vdWg-<f|h$j+J|DA7dR)q81wjV|vlp9yYyuyQ(oBa6I>MZ(1~4UlF$eTCh9P
zZ^t27IKxFOUGB82AMoiaYh><CJcIAj%xrh?$#uc9nI!egKTglcT2+d?IqlnNL%gfp
zhU~#g6$`};3)a`5mL2<b!V4SBR{Ijo?VESPES49-+bQhtT=#&p(U4KNmNB5-(ZV|5
zyGzYpG;&$3;hQ7(oiZ`(&t4d{Z;!?*1@&mspmGZ@dKwYF(#zg&Qmsz!d`XIQsmvqx
zi3UyH6;EY(xhHeg22vtecyj&~Ke2TGYK>ln)z(luJF~OzZnJ&#EGFBv$Xmy>>jkiH
zt2ehD*nd`gWz0I3l!pS7qSr8;a=2sCyp^f>)xBQF6{9Cu>(_s`h1-ww!o|+_=YE)P
z<n#jh{#yrw53C1rh?1T06R%>yG^rYgmm39g<(K~xdE<X-=-)7STeh3nB)phD{9qal
z$?T(p#X$}%NPTjOjeYUvrTMY%vqw6ebdP5j6@GG-=k3SuGxyl*`9wveDY{!iBfJ0Z
zc|Uu!=EwOqpdEQq5>()HllR7VPrFsEjrRafW~+&>6gJ;Zan{>{j|-=NdM&RaKZO?S
z13r@uDEwuwoyg_FZl7wk^++RGraGX9wzb?D!nJ9g^yWOl@%akdqV=}ZV>VbOrn$mR
z^(M+w@;<egyyftDZDkWJ6sv*Kco1B9`mYF1_im70{d}|56N$C@&drni@Aj$<u`0&A
zDY*n$RA_d@tog6>0<XW2@7@1~C7w|1cuTK@*(0}6e-D3QJgi!6BptsL6APQWDP@kl
zlHu5AZTX-LcsqJ=-cq`5&=`GlX5(QxFUEh7o#j%clB65b6_+KseWS0Z3cP7sZ=@tb
z{++3h+b+EN-mCesd$<}U-$l;rHE;H*9mCZQnSWYHt8K%aBG#+59L1F?1umOT3hg1F
zD_3FS7~sLDoULNMlv)S)ajXL|GHPBZWA>p!r2t%KF5b7lcxzrC8al>skk?B%Unv|A
zo6gQ?C2rF*=(UjVe`8AR>bWqq`d>TR9G;q_)1S7+tEnJ*e$A!})|v<s{!V4THu_@I
zCSj-5R$KWpXG*LQ6^D}okHD7(pT0c}BdwH?VtgpUvPxMg1@nfGj?zv_=9z(^69lEE
z&a9!TKyGY7+EvFKIWW+dVa8zziH$fiUreu8Df}Hl<k}Xf)oZ|(qJ?zL*LJkHlZD{8
zBS&a=kN5<k-^PL@i_mAT?W+9SU0bsq8Qq$WDzkMhmDAt_BhD|jQOTo^4V&<M$m40@
zS|R&>9#hjRxLFC4PV`&OgDeCB`^lAae-<@|cRP5lIh&-rbd0eE#Si3cQ-Y8b!G?n(
zx`SsP+KaF2;NpP-+2Uc{q|ET^OwbCD(+)%@3l07;TnqiBZ(&}NN#wvJ%wu$yOEe)m
zIEbIlRi3I|x^|=GWMfpQ7$^sB5!z{eep6@PddZ|uPtcZaj@*u9L95aL^foInlKPqz
z9!F>)+&p)SD&Q$B$g`a7wVuC}sBl`l_RY7y466Bw#19f3VY0eycZG~Cw=kvH@n(K`
z)7OyHrdokZ=2T2k4t(3dVd9+d^czC<hQ|Sjx+6n2PS$0Ud3jQTDYm2q27?=gu))2^
zLbbnwnxIi&cfN<AEyRF=B3m!&#)o%BffZaok0bXUw)79tiVJ2fp@3)0Ra$w2Ibvcc
zw{5}ev(TC&XrzI35c;I>y_LF2>O4~fQ11gZVN(Ox*a!*fve;?R2zVAP66yjM&SbGU
z9G+Maw1SB#{E`e5ImECVAX$Y-d#sX+RvQxMX#Wy}fFa)w-S);9PZSI0zk)=OFn~{x
zWypITB4R`KMvY;HqNMmdQ0TD^#SlC(_ac#YNGN7YfNkobi?X=NDhR^$Dr;p3iYiQ)
z1Sy9OqtA(n0|iLow9H#gAsZXB$zX{~yd>xXNBYRZ1<Had)jW20m0&a!iIbB)iU?;}
z#-$4J?Yt#K^YR-CQ8f!lModeBD&{d_e1C({5~0gT2SU4KH$H3>cvA35H4l4+Yv;0m
zc^z*67FXi+=F>zCX+3Hy7fh=b7krQaXH~g@f*xffG(|-Oi8zV+(FGk>b|umM8QOQM
zv*as=l*%9j;vN82yI_0(wX~^cD2TU!JzpWiaUg0YXkW&pTcwB-IyLg<n{6gaOK`1K
zAo9HotdzVP)J-EW-USQs03=Ld7n5j2xGLAKmNvr8YL;+LsKHPvFLk88gh6@^p5vC4
zVPMtz&oWLFvZ;`;5JdJZN>)R7J{oB=Qf3NDv5L;5m+c`>pamkseyK9jN;f1?{X_by
z4)sv1lno$6FNaE&CrtzivnfKF3yM;r$mAIz=&PC{652LUvDI_R3rlQ83s|Gjluub(
z%SDw)!MKK<(!x%aS7}RrUBJiqQrC{2f;>Pc(~;wbc{>TPmP;WzT{fvk0c$AhGAg)d
z*tacah7_)&hR%K46pD<99eF}WaztMw(kTlx8mcdPR4!vq<9R4*VJ@KMYNDL%f=mPN
z4LXS;HV<egN4&@(d9*aMITzx+3C87nM(8G#6FeeFC%Xol631}mc&(a6r-D1#athH!
z0(<W35O8jmmjKVND~P!7V0AdjuO6c%2jg;^$^wta_~~>7Z39fPN5ml{Z3Ih$Mkk^G
zInPj==Lr!gf(SnPO<0T3158ZMJ|2oVTFT75IHnMTL_GlQG$Lv&)?f!^NUKtX0uiW2
z4}7NU*v3ag8g&72+H48rNlWFK^5B9-IF&BQ)dfoOMsm^OkTADiR4Jh_g&Y+)<rXf$
z%YPC?JtG9{D&1Vf<3dDyU(pLe)cB{1C;u5Scv8Gjk*^zk4Fn;2k7Jgf6M@K4w+KVE
zQu~||7kynWb#*@_KNXNNEq9a(AwTda+)~LOzxd8w?$W_O_QD})RDEs?Arp0?djn}v
zFkDgZc%w3_m}+!sA;_CsyvZq0A1cnl?cvUdu15&SsANN)9N=dB5MjQ3*CJIcl`Lx|
z&bb(A!#5}yOOt)#26$(ufyYTdS;}r)>a+LbiT6|NH&$&3sv2``<bb;?fU>L%=NEt)
zg>f5Iq4ZLb=K(w+PdD%<M{tkLQuCm%0UwaWim8_AOZh_(Z#D|Y3@aqI1Kp`~&mI;!
zCDXaHRUkw%?SK$Yq#KqBbA}j`9-NV0cp`MZrxYe{vCT5(ZL6yG;KtN(^rmbuf>DkE
zJ^WP-A~dU>=9C6L_b3@ZgV*IVwu`U}B1rw3uhFTi0F7mg8qgK|D8(ABk*ZX+tMmj&
zKXZwt;cX{`Zsp~aPE8Z~D*pME?5&|fW*cX#bC3Z`Ek*b?@rMReyYr=~w>yOVIr8x7
z=a7B2uCc~K`>oNYJ{lC)4FWT5u0m?|+emn)gGN;`pm2a=PHpPw`Dul+icG8LOr&;4
zP?F#eXph2y{&9O(ea76OEV0=W%Up;jgTFW>m|c?(*->Jr&RkN_a58hJ)lzhSKQV6h
z!s%nxJe%2>(?Ssx9MEqi75Vt-!QA)ev%!Fd*aei>KKo#@a>|2&V*HSO2Fi^Krklx;
zWN2_7ZFxeew}<)cX5K0bxi@=r+Ts<w^$hWNW$wdnU!B|0u=k$3RNtObjCEQS;Vev>
z4e~F(FsR!5&tGKO*Biy)mB;eAdDaY)mtHkK!b?V08$XAN^wxPA<uwH(d>$q2`_n9U
ze_R>R8cQ#*z8J%LO}guKG0m*5P)LjKQtrog6>(^z*XF`KXWCgXu^BL?-}1J^u6WA%
zaB*hC*(GMpeLD|F3f(UCr)%>o&)c1kJ$(20Lis5jpBvIqM~hcVs!w+DkIdQVJF~*g
z)_4zt!W=w0n0iI;J!dkxY&C6$pS;(l{a58SVGIMNhcWry;Y<c%(f`8vqVd_mEL=3e
zxa`WJKK|$9Hm<~7z)gOX0pj>CF(dg@`at;@I!&u2E!J4{{@REZ*a}uuRF%5HavwVe
z)oo9DP(z#4`H$05zxdo^IyYyM6&|1b{<~*~w2-q{4p@y<v!>KPqL8@BQtN0=yja)k
zg>5ht)_Gb4t@C;OsyA^~T%Qej>@Ba4SxZiN%3R#`s0!@(v6GVrBq%qeST|o{MR4R0
z!M%Xa7mDjOw_Ho_($ecLPWrnNq2s8l_PncnWE<+`Tpr%^VjI5rr@=n;-=|ylch3!W
z=;^^^=Ero-m!Cq32MRNpWY^N?SoQsJ&Fb^_S$gN&lEfd^X3pOO<sV=u!MBIzNaKG`
zZT{Q4l8Njt9~H5dfOUxYwMM;KrWc8OgYsmEcW^HMDx*;rC0cP!reJ`bTy0ayYC@4x
z6KZsxx3@!lA0c4dvADL}1K&+WAG8=l%}Q!_XwYpGG3yt}N~d04%~m|vb|BD2<#CB4
z3@y-7N1S)EfO~@HGss3yjWEXO;N3OSN1$Ze5N`Bs*AYtm$2VHz*zWvT_$Ms76>ZHE
zJY6s2qECy8ZDGkS3PZu$dzR2wYG3v0uzr;Bgzn?X{F&VMvR!-M{6&j?_(0;VHSCY2
zccA2TSggbg3dv&+wjQ^oE3CytomRd;Xr@n9>k|o4rOQl@C4}mfzvYNT*?4=9OHh%v
zf#T@}gjNYFA{1&xGI4~%FKC236EXThgj3;(2(yX?=9H?D+Ija^ZN3WadTrN@Y$0XK
zVX6Z=+mcHZn8d-i?lI3SkJC>$N*8Hasn-A)6o`Zd4bbC3RH7VvASWrp!<mf+(#TBw
zt-w*Z;FN*%T>)~zPVKYN#}YmpIt9K63x*<Zh#DIKd$%;|RqD;x{wPb(luy8%(#Fp$
z(YIg<ZFTe@vkV2We_LxToQ>>o1E?fL#O{F9@z8B5v=vQA>XDA3GXi|T-6WsNnin~0
zzIpOTSOg(Ayyx1|fQQ;Qhr2r@H7H2nfXY)U%mY=Lpqm)Up}H%zdfo2Pi1d2)6}tUk
zAW(~$#UO>`*=sqS>T=~-%(JxArezCLh$>o>I1&%Vx+l5|kUy)+Y$jrccwM_l5mCX&
z-WzN}6m=xZYL2A|n{iK|0ZR$g4;aVhYflH&@rJ}ND&)HH7|R76D386vT7KFbVoHx@
z(*9TgS|10XYfcUz#4DEvRqdEQVcfE8lbz7*?vzWi2U>kIoaiLPs4uw59mq)qRo?0o
z_*BMIG!(YJ@JYzY<8VKW3iM)??VwuhlQ`ojEhB&tTo6hB<<$HlC@lhkHkZnCl4}EN
zRFyfibe105Q>7|(gbm13ZFlFsA*yF*Glh26<SSa<kw|j}Q4J!X9O)r)Ms(A{m;^@_
zg+40~ozUc>Ea<)o8gXyJh9K#!0<<)R0+-C3ER&>(OnEoeDQQrhq%y?$&1HqG6P51-
z@Cdf-`fP&m`of%IQ>ssHPR_j(nzDkxq9x`ID@ZDuR^?ERfcSKp`+DWs{>s_($pnwQ
zs9gF-4?1<DQp^y~TC-BG>%S@wID3F|=mW`dEuu1_5NJb)Ki9_Z{Q;kTZXYAcCKo;X
zFJ=Dfjx<<!CnKg$zaQCOl>6FUv5|VdL>UVz64~YwI&p2s)zQD+abUJ4jbZh9l?tmP
z`R<x-C%b;m+l`<gq_YXXk{0*2W4hh`c1IY<4;1E)YGpjahLXLs9aP?E&Soji<Cikn
zb+lDp;~pyia1w{#LpeHqpkPYaSw2NkygmI2R(pZDRW;4rPuhOQe3rgqu((~1j4m)f
z^dq`;d!1}83$`*Msgjt8YslXk*wR1|VKT&mk1^X__=ux0T>!~1{s%AI<|C(jyYD@j
z8#`7@7cglM*hZVj#xq`^;&b7g7Mh&)BP}K+N%-QW&hj5;s#zATQBmjyO)8$)qBVfC
zNL8es-%yPBE+=dJ-s#Tzm>_k8!j}1=cUkcAq%WiOd^b-PZay`&hwm=j?SG!6O4k(*
z93D&p#^IhD-<?HT5}UluICYrwztrxNZoj}%-e9)uCw#kQ%m*vSCoKITni_4@e3;Ir
zi_9(99d0m5lBvw)2V9WVp7p<IJ`NIsW7#shqG-BLjJK-N*;Y26)>}LC@D(f!wfILa
zuXZIXO+YVkBjDuY$#VY4RSN3?+Ggvr7q0gE0Wy3;jkbv<_5K=!iKu^jA$|1gA1MkM
zsWMyRTZ^Sf_u3lhBm&g9_W&TK%7N#X-|{L{8!5Ca`@77)_JOK$#@ZP^uyghz;W&QD
zdH*)pNAFD1(rVsn99VW_zEib{-VR>=6D!LP|6D$L8dmQWtt8^6`<X{rE|4C8NibEB
z`T_?7Ddfga8;h|?wshXB`Sj*LIQOk1oIU$(6jHRN?S1*Mvx8R`#T8E^OUpN%oj3CX
z=5D0(%Wl9*`@nZCTN1f#0X_vC)bh7?S!?l%a68}D*o<GQ7f?t1?MF99Z0Re}9ze^X
zzG6Q{xC>nu_d2}+x1#-rg(3oFXS}(qBS~q|{XE(^P<7~Ub_{9%p&-6U*Cr7Iw!Xl2
zEw_o$=L3}_a&gE^@{QlNp^iK|-xkknQWSNMeU2^;d4jWgNHZ&|>JekNxr9agAH|*>
zWzF5xI=dC@-RDV!K1x!(>LfQWHAHaqP?=)r=b5rk&O<$P#$k-Uccm|9{*X$!Kb^E$
zw(9w7EK7cvx?+Wq1|#h#QBn3gn}2>%s`hRR0Vc^q^JR7*nPn9M^9cQ)2rxIqt<DBI
zG4dIHN#5Z*w;|T!R;HOQjQ70qWU-H7$Z~2MHwceGgm3#t+xITFsIYaMjs%?$muQe?
zojG#cnfw)yR`|X_myNq%YQmpDuY-ERJz#d+nb^S~o9!jEi0RlW_AgT!#C1S{B}Lt8
z2NVSZ=+|K3V(U3KSflAmznOU<Xu-0@cs<Aih5!oAY)miH`EWrD+U7!KI!5$JAD_Ot
z$co8`8YOEd^5oJ~u5jz^X;UY`8n{YODCD7zQtuIM1WlR|#RV#>-QXb}2;s;9mz*(X
zeRCqArpBC0k1)DcmtumYG;r_aMD8#gW_+_P52e_*7K=b55-J5rX;hKC_guSzt2vZS
z*#?&OhWbUK15~7rGgJ=Oi9KYq%5mKs5e@^vQa{dmB_q0YkO}ohgW!;cM!1}jbKq@A
zq+Rd~kHObeN+)0PZUu==JH>f^dFtb6QTbC&OKvEb(nt2*RLpTFQG8NI2%a2MM3}9~
zZAS^J5$)?XhttQp=p9ah3&^Y2=8n1Ohb0~bJ`0G<+xVo6-f8@g^|LHkZ%5D_gtl|T
zO^ke>jlhxS)(d!)k`7xqK)<Pqs4l>ZOeeXc0&NC|Hx&wR*ws+*SmLng6rk#qI_h$U
zm_A9Gs@S+tf#}Ip@$Vy`pOEb#v(x4oz6|qG7U!sR3|4%mBwm+w@Y1bY_iyJ4)j++I
zpAD(@thFdc=(Pq!f(XS6GM~T{S$bs&=7|tcgh09R`teCm@o>i!p*}JSC??9AZn9Jr
zIf9al&`uwtw!Dln-w3UUOU17{*oliep_p0G?6ilm3EUps+~Y7Fup=H$a!2r7)q6*e
zy5&yX6i%N!n%Xarx>e;VB5id!Wzm#{!n{Ey<5!o6A_@F?b+hGbnDAm0)&uyo{CQX5
zH7|(wIvLCAwb|4s<ls26HuZuY^JHm5vhOxtPE+2l#-=~SaZ=^5AF{jXm}2tY*j5~M
zb<GQ$j&zSu)}%#xn#Zl2I<OONk1ke|wyWnPzQU=ln5`=2PZBs`3(Np*jNHaOn!w<i
zvDDtZCmjoCX6+FIWYo=Xg4I(O?f5S5iI`D@E6+7&-wzZSU2H3izgbPHuqMyNuiw*1
zKC^duWc6Ii;<GNvj=jK5g=^4cqi@`ixC^u_`_XkFX<a(SAp_G7@{O+kwG?ej#a5rB
zH_&M>T|uQY@FHg4xU*VSeFG48Jk;aE4Tk~a?Su8xU9tNM+1@w&*|@y``!UfARPl{A
zt)p?CDfO8UPap<THH#+qmLPU$H?m!<4+L3dY9-j)nhPZ2yOxw6=+B2wdqDFIJX~sL
zyV#mMo`_QC_|%Y45;tC(S@ZJPSQNJnz@mBY`F79qc3bmjZc57Lk7|k7QhUV2MHy6C
z6k@GoNyy*18?$v*Q{KQ2uiZ0o%6ISKt@G#P;bLe04jX*r{Mztv|M2Ub*B1rthv(YT
z2S3YN<=3ubj`5-*oxD9+JWq+Yh4X`qt^7}uo%X)LTc|*{r%?tH%>|^3a}$-(i9lU}
zv0c%r3|`pMDKK%Imp!7{`c{bQ;Fg1DWP?{eoZ6$)_wv;~89JD)p7NQ~Lg=H?gX32h
zwXOhLjR^GFtEn5n9>XYhh{7*MI7Kv%*M?+9hgj#Rc6zP{q0D~kH!SR=BF+6@I~cXm
z;P!kXjb%dQ*3cq({U5FMXp^tRK7O^0(L0H@(F@(sW@6LINi@mpCH?EqW30Ww@k-!-
zpEjx-Q%Zi&rte6Zn&7;%D_2<Gvz<%3vUe`K`V&c>Cwz1kv(;v?gcnezKlF55eG<{F
zp_STD@q^;nA}17;vsa_W<M4V0+(kcm=eh0~;U^0yN(!wFF_Us*Hqiy&>$KV$zs;B*
zJKuZzX`T#!6HUrUt<yDEu$p)|BuGd%P*Y$};Fz6MQ*76%s<Bu&Odt`F@LE(P_!f1~
z^!DkJx97=h4Zk|s6Q?3+g=F||@3B4M4YNw&b;<ao1-C%1Y+3<nvp?WxK=JR$Rh<x4
zTQvwpmfMo7pGQV^7Za@RL$1vB@Ei)PAYr!V7@Uv<F+A)I85w6z4bo+IgFM-v{G0{z
zJNfk2C0Ss-JZ7788kcq4&dIZ0Uh?${VGS{h;|E{)y`~S%(cjW)D*9np6-8hhKv}CA
zov^L%o+uiwN;Gh*bS%d+Xrv0=00Esf<=5thA~Z<q<n0kA0)m#xPb)IpU-%PJ>gBL7
zPM~rf0*=86F8+2dD&DAQ%vQHR3A^)A40S8@dVf*C1Vvo^z*$ZOh4cb93&}|)Zkw{4
zD5&2XmcjKSn_?943;?}uesi#N%6e^Hw^=!J41Qto$gKH2zJ2lu0Yrs(vr5BqYfRq*
zL@C!x&o!aG0lbrkFHt5<3v$M%YSd)BR2uX76uGBQoXz*r^ZAIl-KCOkyupZ;$`rr+
z$Z*RXX<~!IqN|`Y(Gq=4*1|K|Z6(8eQlzBue%K~`&TBsq&1UAz7BqWuPaSffl<0~1
zSY!9Mv)ZP-#Z8C(R5fJ~)#t@%TAl>6=F${vw0V-KX9Ve#PUJiRYQDK}COIj^43?vH
zTdGj#sDk4cedH;SrAi{*)tNatx&nw5kndRkl(9BcZKu=6D=?uPCROzMNg#pOeS+E%
zRTnQYeA`PA4)cmz;*s;^6{3gc1CR>xO04L><#5~Jg?gI`$j}4>TsvZ3-acMPn$poP
zEF9zxnVe`!B9WqueU?f%I<~-ddvIdvt;yNL9ydlhz73#SMLleC4GHwSfQPGck%8y<
ztwU9_sc@qqAvB~`Ye$w&0Y;5JBhD=?<5BtuQys^)cYk6mk~TJkxsH3jlZ6L6A-ac-
zhanFSuQka!!CT#<l=Y0>($YRgVBiIQWMFMWQ<XGkzK9y}3K?N3rwEoX;;IIya#xvl
zLb!>NSU%qx*$SRnet?VD`>2kgGXWYyPI}4u10O<PL_kiWux#!^%}@(GKh_9CdIxpu
zb*F=HSs<tjC~f)kl5ripoXeMRd6i8rd?R5zFp!SeYY9Ij&lqKWM|#6h>nb`kpwBK%
z>d_T1uUdC*>52+H!;`cc=B}BoYbhSjT2t&z7SyZv|4$fTbB-xuhhMj`@Rv7Dt)<(}
z5!4n(6F+V*cV<VcCkVAExK=i<gt0WaABzu9K5l{4{)=;FucjS-?jzYB`BSsP{_pu^
zCi!Rf$3E-sGhE_4%Kkci+R7=eY#tOLN}0gs_yh+)y!m}oO@(X+ftr~eJ>OY)9jx|E
zr>RetNRY(JaqBL2lfTs_^o@G^lWV2C?obSTy2{WY;UZz+hT)qx({q!#Gmnp33j?Nq
z*B7$5$1(huYkAgS^{|%cTaNnFkV!+ORLycpPu4QXG9es#%Ukj+zR>CBbxHZfO~UL=
zmONssuiR%8$_A9Nrv_PJ<GU8ab(0*u0cLCV;M<|~@K5K1Ck@;}pEGr%Qe%~qL~NTa
zy#GSp_TT)H?AHIvo~`fxn_}Pcx2a73NQJxK1^eTFMY7*I!yg=e{R8I1UhBX76sPes
zW!|4>M}OY69Q&D-qwOKJ=46>Hp8CkJ&+}VoYD+T+6JjD=TM`JPlXK2bsNNCfB$sgS
zB~xL2GNHma@N_Mi5{2PgLeg1n<sejEbE1q}T5X;Dqj#hJr_AEFH3(^cs<TJ7T9)n1
zVK_JNN-xHa-xSJBCC}_C-M$uiDSTH>vl2$$-Xaux^LvmClx8ap6P)&v*B5*GM55&%
z{VIbS<}mVGF0}c}Tk$#7#B9~b#|P1diI0U{EbqzUbjSCvwnS#@9+mpozT9S$G|}!8
z$0s38iSotI?J4f~PGT$bXEqqaS#$ab!vFHAmXH0}VrNYU#H}E+xikNa(tPqcmZHjh
zE3=is4s^Q$Mxougn?X4?U<b$`T@>RLQ7BNLR$FC1h6HoXR+Tx;AMU$9OXB%2?U48y
zaMCl|h}dC!jDBVl5Rn}xL~OY^`{s@{jF5h<+9cfSZ_I=g6hs=ASlhz^wgiq(yJRR?
z%x`Pmofql5)7z9J%NF9TlRRp`#x)WPmNi$O!_)Ym5*NoUb^`@p?20H1swyQHfg@*a
z-(IRj1!;J~wdx1{kHruk;`2*uqIcp?xF5Iam;C>vy$zUU#d+WPo^wz4oNk)o%uEA4
zXn^XbK`n%&%ZKc-z*2S7pcW?fMIOszMN%%9#aND$v4oY;N|vgd2DN3yZn4-NJ5F*z
zSUV<KdE^K0gB>S1Ae=>h*kq)jk9h58TV6dZCYGLwRzyUR@c#aF&gs7M)%PlSyH9<-
z_10T&eVlr$>eLO7-e{>GnRf_xO={~Iz{OGV3=t;>h3NIGbZ!dS9~Wb^3*?swR+KtR
z@I5>Q8-jMO8a0qOj0pV`*Cy=Dc8I~7G7zD{DGWJwqAcZ!UQA_<gjW@^2?)vu&rnXt
z8qLxx?EoN+10_H**L@FEP41a<<#tdt7$MX)1gjItMMlldBLwcXsp1l%B2x%NP9U%O
zUueoi$6i2qw&-XyK8;A*7?HD52+qe_{_6~yB%xu?w{3jA3EkFiS1ek$!4hkuwkU7!
zp@gax_gy5S0;-}*M9T6%%Mz+dr&4+TprhQYHjQI@fDQ;DBIVtx(i}c@gAj;t6Xxa^
z>pcO+lr4^zatlY96sfP%lg1~`h5*l{31B<>ymcI<44y;?bramCi>6-9u`|lNR_A0{
z6|V#FR2UywMSmwYL7({RDqYQHkwof<^Lj(35osI4+qpgouFc8a`9k@oW#~sI1VH?J
zvRdUB1GY0LRK(meM8OxO5-rMrtNiuYDiXr>9$ORCx;rtQeI$mEZHFDn&kZbvuvyip
zcHF^Ug?eChrbGA`ZQM#oPmYGI^Q2wGbP{y?eWBko!0l{gES7|&vik5Qv_n9x;I@bb
zrB*pDI0`FXJOY|uZ#lO{Z@tm05wP~LhZPaD9zfVUucFzF1l+xO5<f|U?-HIWWEk)u
zxjE5F>Sm^p1|mm|CrujH+3lbdu0OsTJ-)89I)<`TK+jDB6<L8YaJ9R!hN@KaOtqZy
z7G+7V7n>E13MTLpRF}Y?N;HbU!99(I&4@ENdTNghHMYA)mBkhfan@v9pgIiDiV7hN
ztg@L=FtJb+{VrL8q1mw}L#-2XiQGK=r^eDml$j%~A*NNx4s{s-M8rwVt{jKfrm(Fb
zxPrULp}Y~i>npCB@H5(xz`LY+Ho&*7a6a|;1(EeayRGMh-()QL6EKb>v+ntqU6R}-
z0kF?t8<%6ej)yIc3(9ktsJ%YJHvq`C&9}EsXd`jPb3;{>vSqzEd;11U`G?M(kv{9w
zjr-`os^<zk6W7=hngGc}?~MTv6kjCV_3`V7@Fq4RAANO`#8E=}-n-2$ILaU4bAP9j
zs`r$(w{x7Mz|PV~jcNHPRX=Gi#htFbA&hxjV6>S^yuGW~oqejcIO5K+@X(c%YGVlf
zCMdr{T16hu3;(5=P)UP8c#>uyjZ$ANn%lvrr$Yhzqwz>zpeeBJ=^X8GW2rUbVLIiK
zQmZ~dd?VAoXOhrc=DMn}_j-Pii=T0nCRJ&a@AY^3je9M9^F_mDn||cd)oL${OG?v`
zH%3-rd>NG{xBW*GW4D#z`H#G3m(jQ4Etw#BA=X-t+EyF@gOg(z=yhIcYfrpxy>s-x
zEZV{h-&j*KG{pS%-=Q=9-mkfk`^8A}sP4KfB+@DW@zDJYBK?s|=)qrPiq;#=i|pMx
z`^fi?Pkb8DckSx=kQQFsh*O{TzSkQ~?RT%E`JQ<5Q_vp>hq=fzw<lg(bSHi?1mA}r
z<c7p<hrRMyJ{J{J+k#4k{y4Yqp6MvCTmpl_FFcaOUK_^){Z7RCjTbq6*lguj&*R*)
zkc2w<66tZ5g#5v5hqeW^!SzbE;Xl0Ap@~{aRR+GV7USl445m{pcM#!}N!b5|R87mL
zn<)R3MF6qxg`e_}rIUMG2*gf(k8R|Vv+VV$W_5>1Vej|g3Af(3F{FrBvf>Vtu5jIO
zd2p?(%zn#T+5Ox(*Kpwy>xl>?h>d;i^}_kv?7r!X(oZkFxVyLXQY&4$g$_Je7|Mct
zg&6E78Fk#q$=|jT(Lk{E(YeNRc3XpQNy+^6i5Hf(JtKTMm9#2IPhj8kPf<Ot#j$jm
z1P_2Z!a(e!M}B{R6?;(|2+DSj%km?Lx_ixR<>6cn4u0O2BA(z0J3<zIZngSJ$Qp&#
zBt|3!K==}g<JlfMM7ulq5!Q{wW=c+}kyI%KMRIh!jIPEg;!6hKtPin}tnPAnpT0V2
zM=9ii9}JmJ>PQ&Vw6W=yn#kijocUj8=jr9_!Q#*>r*}2vwzc7`lIer@`5pWDmDB15
zhboN<C<roAi@(eu=V0*W9ZMtPevUbSpvp!rFAu6+2ZuHv)2FcoPU>RJbY0#IJcm8c
zGaRUPBTQPcRCB+mUg*d)q{=x$VCBW?_&R9IBHQ7?(=B#0w%Z;a%_sx^b=9)mtDFgl
zB+Gd6!*t>@N@J{poA_!)0EH`n8)EPFq|1B)A+{3JE@%`Y;U#X7648U96bj$rlhjEB
ziTn|of(Q8+)~93WV1u5W#FvO=brL^HgK2<a$+f%D=UukfW~zv;W${N-$tZ$%=4UgK
zRZ^)#&uX=qoG6klsKUAwL&64vO0kjHnwnS6lN2pHs2?%<j7Hd!!5QQG0$Z@D->?ik
zF@NG{U7k#eWwQ30xKT;3d<D0l_^^(G|Da=Kb}Hiqtc@J%EzZ@If01OtE5rrqdlR<H
zv;{moXUd98V!9q>>tWtH@(VImvI?J|bZVy9#l1ZQqLr%Tfus0fX;Qefj-$&1cQr7^
zNNw$dmD=5NI0BEGvUCA^dk7%IpZ8m6R}dDPsMv9Gr#xOhrX6;Lg>#~_HiBX`=zTws
zBe2AJCbiX*Fr~7Z^rGkFkr*O`q#JFIN#$UTkdCDznt5=`gh<vgQJ2}4GmaQ2K$vNf
zl-2hLfq=mPXR)M_BIu*BMq;|qq!weo@eF0Rh4oe**xv+KyP_Rx4+S#>12`E#kTD~p
zhCJ)1(uAI7gH+X76_ZKV2SPN7bc$_cJiD2#qS-0!8%$z?Ar0uQv!+|AgC*Tf6P1+2
zVUs{TXl(jzRh?+WifKzixSQ}LW;EiA9i2L1I%?S(D0~B<w-~QKB1E<#9vuUWIAfxJ
zjRh)ieG7R3C)-U?q;3=oZFC?wVO#=>Ct!k2Rf$rN-Mxc#HO{6rg=GG~s?&xvE533Q
zibidhZ6q;6jtx)ytfcq&f4Nx~!a6fJHSSA5d?u?3AKp+QqHhO&Rq?UpnJm%Xf+N@`
zhsM~c`Oz&>MTdEvDmp@B09Rwz!Dq0@D=RMbF8?B};&4`^k6)1J9Sh8DrfwW=;y_}a
zsE)E4fAq&$99ia<$i5R8TF*~r6FM#6yC<A6WX^Px-VdxVR62L^q@prA#@7%V(^U}_
za#lzYB|qOg9<H1ov-gnlug3Kbsz5tkn)qzIa2_jLXnz9%&Ybj=;-!L{mpJBE2`fC`
zJI}Hw-w|RJ1(DHCoI5dHpunW7WRg2jGo4$F@?;-v)o<*v?v5W`x_X#w=ix7resBcr
z-htm+!K(D_`0E_c+0wC+pMMiSy~i#~`6)MDu7MbN(rYNP2E4#?l~5c-z}g->sgHdp
zS?)b?p3{zC_m0n`YF4EvT%ok8(kL}TGRKdG<|^J?`SCmbfgN+nXuGiWmy=!V4_sJW
zKG6-C6ASNOvdMiL-nyUL!36SB7D^r__*D}t@g~~#iCVP~{j-5*dOce%+uRcjS#$rj
zW&ZgY7z60HLAF@biR|#%@gVnLP-CbC=4p4aY^tv6^e}sxUNlDE$YSl+@4Z8nKZ(wl
zr8~~&M)Q}*wyZSDy#3;?Ahk6}Is@VLZ%Vnbi<Zw3<b-UgDHo5DFP|4If7kT<Z5zyD
zh^T%m5_-&r!4ctqn)rt0AeM)yQzZkA{nqXSPd{*lWfWnux53&6bl-ewo=*L5$*%HQ
zHsJP6dt)U5nqNeU*ej25r<Sv6@1_r1Huqs$e9I-Nvz0fs?Bjp?D~{rabRY9Dsjc>(
zX)#ML&N@#*Te+xb?e7gGjaY=h&Be|hyurFr5Ksu()ZGLfdwKkRx9Q*3p`o(@3696H
z+t;a14_{J89seX>`rUzN1Cf>*AP)UQPBX>z!;10TKgC5G{nYBDXSUW-S1`;o5R+X6
zx^FMUW5xx)^@!RUd!V*-#a9qgmDS`cR^<@{waCFeHR9Ij`H3I1EEeJC?W2Tc?uQ*W
zp7A>IiDPpkScGt;m+jn%e@L$D=|bM)cx~VV|CEkk8?UpG<u}0lhImRfO0s12_#S3s
zzaIIu_N*gt?!FRpI7m=i6EA)KuFV80dOu9|d$x6lCe}9&)$9b!71*@|r=nUHm0L$B
zx#dpiJ>k}%&E%m)tO3q@<}dvXGC(QQMviMYwN=KJR_Cy3k@)+EU>1y&J2`CY3UXNz
z4eh%T5h<dewPy)|HJ%7CA}9ieAHm^-iGG<pEpiQb>A!03qa+mpV9FjwbrSV~Pz&J#
zrF3d+O##(x1-kXdX{OjOt}5zGX2B$-2`?JQXmqGjL&GAc4_Yqa0;VxfPK(whiUNv_
z3K*TevK<!EC6;I;RKJ;`;#d>G4xeJw!F~GUCgLfLhc{9ml`X8(Tpb~*lqJt<G*!2b
z?>)F)k+O9Oui)mbL98fxquwZ+L)h&UBeOe&m4rAS4)DF3X^Dfa)ohJPf+B6)+-h_T
zVR+%hkw>$QwMr0Gx~#II*;W%t`U1}CtXqRFl!|~%1zl6XLUh+MyD#a5xt(~rgpRju
z!3ia7X4~={IT#ki-`zqcd1%Y5fZf)arO5cGRfP+6F*Z>m;%@j*eC!H}s#;=2WE+z@
zRhKfRiqKt@j2an=ic^$eeKk20V`e#v#>c+SiH(vm$_tOB-d|PQI!?4bF>4bYsI1(U
z+pEp1D+3s;PvRJ=w~}@2<XvS$*}RYT8H}?=^y9*ffZ4vR%@*o5Cq7=`YT!Us_aV9^
zNCkgPzFMYU?xA6>9}`tz6Xq*dx6ak{nf}SZM4x~mYjP{;5+%74-IAfyGOzwuAjKwU
z2{dnzL!U>1ffui(Yg7^kj1fCew~|Y#`_+TRH77zJ=_Aq<fZzepsp7pZOz?8|CH?&>
zZmMjhrB(N)R3T?K*(7AM$-V(sHF)f)$6GA-zKiFXEXF9%(!XeB&R$0wJS+)3Kkt)`
zX&mRp55_}v$axrTS;XvJ(0B$rFm^BB5rd+9*>te<1f}xT25XW3#l0~$M3V%rvwPSc
zP$y}uj(s=rd!Bz+SX+1>Go(;u*u<V{f25YlPf%wM@3fJE4cE{s9^vOMbFTy6d{%K&
zQh1KJd^ltEiq|bCuD$(@tGmZh$IMEi8U~IfyIk+@bIrheJYV<MT9GQZ)>NYQrwy&4
zAQ9r#N7?fgIt7tk`d{Nv4JsIl<%$9nVTXFJw9DgZ-4EjZcR$Rl_XJGW+1gkCc*n?a
zpVUID(w3h~v%p#4;?sZ9Q6{%gm&uMF4z~Lxv!}oK&tta5dwQ*TlW^2&JkR_LW4#I-
zcp_&`jv=7aJ$iZmNOEqL=0D}^$roBt<|>=xi9Tf_n%Ob>bPPGTXyx6<TDyKK<=d4#
z$H=xV9q$9Fdk>Y_8d)p4`QI{&{>;7nz~p4HzWX^#gQz@)s^30wS)?fccF^m6En%v{
zdB(B-nj{<5%vwbb+C|h6Q#XBrSGjhbhk{ru(oWGI)fm)*4|QnEiqN}Kd-Cy1*8SgM
zHKp7U;ss3hZ}~kKb|hoATCC_D`dVxE)k-uJ^k*BFnh>R0$vkRnvG<p3Hyim${K!<>
zo?lsJ#BaoJKLkT{9fw5x#&_8e*=BEDv-I<Ku(k`s-hF2}gJ$nX-ackWzA(;>-R9#=
zR5HkGwbk1rZ_JBc7%OJ^q}zVyNxRv1?&Up7t3LQQx&8X|ft5VtH5}E}+b;<$bhxB+
zT+x-DPqlt8@k1~M;x}Em-}vT#wC9U<d`&1_uw)}~I=|~tI&*GmBXAffg(&T`9uZ@j
zZ_{9jxD1civ6t#ca{oH87DfXvnRF!O0pxrGC+rC6k}aQM)7K)kNMe8iVs$oI**0*P
zhDF3oc+hv!PxA?IcQhyy7GZYwRoy=ui@mH#1&dWRZw8#ru}DLmOFNe(2Vr>3FG@u*
zcj#io_o$m~Qnlqs!j&!tOuzKHWSQPv=5Ff2346$`+gC2=*~U(9_QEnKw2a)Z9;D;4
z+VSIQYX6+d;0U4F<)F;nB-aq|N2Gc7HOtxl-?7>9tJ3}=1VkbSeni3Hfz=p1!0^0b
z9HVKZLi&cB#<-IS<ToM#Pcx0Ufm~vKM>UZLvXI!WD?pKF7|1-x;y7L1)UbnyEfVHd
zA-cy;G1&f@G!nF+9>LfZ_@>m{y;#kNT^+NnRU#TvPS`ZrYV{EaDGNkI%&W*-;2S45
z$b=(^wM*N|=FRID=@ud%D~M|va@Y>+AcFaQw`0P55%<$lJVSw}Y&{6)4s9!t<ZC<v
z4$4)9_M`9&z0k;@ia(2~j03#&gCF$_uv;Ona<;nF!7!4j1!l7t^eECt?nz`nP+<->
z+m?p_TAE>yz1%>>NZXub?-l1G?Y+F_RQWN!Lc-S%zTb0px6`75-S%f-%pyhFjd|rp
zPg8DN;0cMK_s|M^REsEFbbw-912-39&H4)xZ*L(+!g#1h%ZmqGO6xk4NS%34jA93a
zCsm*|IF#rRQmqA75MMpf*)Y_^Y-__cZ52L*)l?-EI-=6B6h#{ihF>R4FXQ7RQy~Sx
zT7Icb-x&_LUM?2epvu?LmNdyO;-k^0<e_nz+W#`QW>Uu|LFALdf4`86c}nbWhhc=+
z@lbHAee{@(5LMM}SB_pH6L9RbWv#Acu{#z!PsOxFUAu$ha-NRe!69LArprazYCh^K
zS<Vp`cm~0G03(XhRj9Sq*Vshr`v-T1B(WzdoFcs<)Ch4IymISx*W*!}kKi#wbPY7Z
zW}A^bTN+*jH&s?`Dv;@T_ifnSIxJduGHx_-?++j74uw-|8Hs#0zaqyehNfX<P>9_E
zN7ZiVq~sJ<?q+St%hjqj_tQ|FBlc>6s_C}6XtJw1T5c-~v`C0`h82iGs2s;oPpw-8
zo@)L5upC<HXqM;|vmIztHSV@{ui*QG>IZQ0_8zDGT6K!vh(0n6e`L-$t($JVftbV7
zOpbIm?FhvzZ}p`eMlS1DFn;XSYilq#fBh<xG|BGG(7MBKCPDMFMAN9Qy6d$`H!EI&
z<8^7ktiaQpQu^BW4-?;lVY?^`c6h!!ww~(EX!h53`S^idRreww#IZo7t>Aq^N{f3p
zelxSx?`A#gNFaZlq`5KOCD}r9U~P%Uy-Obo2m9LjrFHprTYEJ^d71_^1mw0cR=hjR
zrSZIVmW{eP(K;&4I+N>k_LdFWQ~D+`GXy;Oj==VskIGodZk3YNx=t3~uTm^~6MvMo
zq<*Y^ma8-MLnf#+nP>YblO}bpLjH;mV!dwk86s0|g8C)yt9dST;t#F-=!Yqenkca2
z7w3}Q&jnj+?{NC)b@iU_kV#aBY7}=R!)WIvL`y(P%P_|?6m;KnV{-IQcNTN(w)&?}
zv^2MQZ0DN_YyWPNITf9nF!Ey-bs{Mx434(mRF<}2?p;3|!qm&t*@JfBm`(0ay1&4!
z<Hv5y7bf=p7p{g1sh_^_K-l++Zw6c4Pt=2d7_9r1^B0HWtbKwrJ=59;es8di_RUSA
zcsG)E!FL~eWF$$3)*qX)NIP}Zihv@mYf8MRLPoXqC;v6g@;RjVvuv+xM_n4OHbRRd
zN}v$cdT3qhtG2Gt?EwCAWLqu>30eVbTJGOPRl4e)UHQg?uSN4?sbv523#nA{s4Y8H
z=3i3E=O=vnmaoF{qkNh_T$T)q*ZfUkPw&3m9{bY281Mbzr(4`JYWC(!lSwFqfLk>R
zKRlE+4>P>(E^xNXeVRiQ|KFR~75Mp9cE{(=***KsH~RgAxmE3wQ~aX+wez0{)0d{k
zj|SP&0dB-vV2(FM>l+5L_KVZmT6e^?Si?vU&HiMSNb=u64AJ*xR*1^@f*6KkgL48$
z9Qd#g$3P#=sJ3<{(x5Z3Hu-8wE+sYWFl~go3P&MIboY)pwXFiTGvTkOUlcvj5{Ucp
z^=ne|9|%SI0_{o>;e7;Cw!Ez7O@;jqqe$-vO4;~CV#jyuZ8<Dlnan5OLgev~&1#j(
zotw|%3i2@yL<ssw#91*yPKRA;|Ess`#3#)BPdLkTNcf&tt_acP-#z!19S9`#&%*Ee
z4z3>KgmZdS^Rij5W7I=ICKWU9aCx%*S++lvb)w8-Gpl?dnagbzyzc`LDMdik6~y-8
zY7a%C)F}lgSRVj(EI~4aC?LM#wNViGfW($u460L})tazHPh`a+A7b|*&MG4C%+$<~
zJv3eXucJJ6%)8-N{$U`fgxRdx)N3vH9%-02`G?P#ma2(TO(}BLWVcGtZV$fBy4nNM
z<LOhHRgEoh9MpFS1*SWMR^o~NAq+I?3z#_;lI=(%MP{vI$D@a3w&a>2$ee`2CxDWi
zwJS;Y#i?X>SL$OtrRqxps$6T_(D1-yFdeeDQgZ=15xTWqS=n+(P}bmQ#@Vdqr8D_H
z`YM@Zu^o_W5b7$A;|Ze}ZJuFZEqjG!{%Lc39TiV*Ng<*4RS;C7s;N|A9R4*%gHf-{
zi=?N>ECi}-vBG0uobTw33`!t!4FY~dHO^~t-I9%B$hn=Lm)@~N!dkd;2^>$DAvf_A
zcm-l@59^4kCn`d94u)tc0#WFBjGK7o)KV3}y0dwquP85F%{-33Lr_QwDGExKn}obQ
zDBGZ=7#+-<3plH5o*`&S(5W$<k8lhSK7rDlx2jdiL($0-fJR+V910x>uL6zF(O9%1
z?E|2%iwg)P__GBhpv94CWlV5vHOI68m=Hn+iC3s9sX&hj@<_x^j{A7fuFcDnPWvs+
zz!(hTOo(2nqqrph8nO_AlY7KDHwQCG9dUMxZJ;P7mWuM!X_2l1Hey^J8ZHTA)a6#j
zjui-=Oj4Wez<$vFYvxrn29FW&=6D7J+0Ib}ufa9-qCOoHX>K42K0#jNUcy<XZV4e<
zWm1(XvaAG(5zAqyNmF?Nv<^ZmnDt17oML%9w!^{%MDHv;nE;Wdh^syKWQ|Z~bL8Wb
zK+Srwya+WCK`j9VYCW`>z|z<#p=nuDnRwg=gE*TA%E#55sfpB}*XxGfya_M<>U**#
z>TEV+#ePt|Izvin4%LXN?fnFo2@%=}iUp-uWTCvtf|HdYFi?#$cW!SOnmCE5<=opq
zAX_r^Wuj#WPK!W2C=v4`#G8AMTxch0afopJSyi?Q1<nl4FvOWyW@43L4S-UJ7&q7z
z%)ofroEPE*=>)4OP|$}|)kX%{Mw*shW&cqk4GCu<xwkTNk>#BsojPGz8Cs0a`z)jQ
zIVdo{-^Oo8W_gQ61Km;TLo4t;83ZteD2t5yj4Dxbuvf!)Ka}!_l#^q7K%PKbhQy>M
z(&Z6|f+B(<l!xcBlt+mI&woEu*?u4C8|Jo2B9sA8q0kiLs#q!P`i0SzyUE1MQ-K8H
zYxh>UH-&pzivM2G3}7BM#L3Jiiw#TL*iI?b$55bYUR8}Ph=SM`NE!Aj6{9Y-iZ64#
zOO=j372hd1D{!uH4P)!27C`iMLt#)hhd+Yohv*`>nlMD)|Cj;yA{;Aergop5;@U}3
z4xeg3uY^rdReFUAzV8NGCEGMbCv5sO$g3+=cb@iCBO^{h1E5X(2+thsM%FYTfNoD#
zjDT<z;i?yGK=4(ubh~2*PZh#<W4$6M(JWyDAZE)HlWZlY-K;mo0`%k`$ro)db*bk<
zD<&vhtZyM>9>uR`@`mwXP|QkzL7t3<CZ@0fKtJ_DS>ciVL)~)q5^(roCDwCwno=PF
zCQZficw!b#F1@4jlu%KLEgL&1`7D^u#r7XJ6Y(m+Ab>L`#1zEHnTsj9(X5S$khHs+
zjSLG8s;CeVypm1Wjbu{|QEyOi*)+p8o&fuV*vd|DvkUM<n6S(9Zq*Z-ptIW<Uk~vz
zu6j$^m#Rw`{G^;))ma39aT3}3r=q7e9CqB!T*NVaK|v0@S#D-3TcjS}2G8;SvlXFg
zHw1$j;bZ0k&iEEyNtma@Y--P<$aEOIvR&~7g|xUyV$Lar>Ks_&A4jZt`3FLpQK4n1
z@ce1$C91Gwapbg^vjsRJB;p31mZK3?tVA@9IPg%Y8q|$W11A2e_aPt?hg-mJ&-a1j
zw@%^5IfXg%YgqmKA!v>v5EP~nTqA#6gTbfNPrkN``$#ljAUQ?Kd<VBG4#DP$ub6SM
zCIcL(hiD{>g%25cD?C6?A<IU{%5EzaGU4VRQZt)F*Pq0=P|gNf-m+IKQX3g3L(I6R
znc^4jtGGBh{*1mNiN76rNlY9u!hSbXe=QKI@97>%)|f4Vaf73ci`8%3XgYwmi#-;}
z7Ww?&T&?!?){w=xmA2V#^>mj&VxJyqQss8o74~kX#GPM|{D9+px)6>|Ga}dE-$Gry
zV8I=uWpO`gglsdqK|9@M`{3%;`lXS_>bX*>{+z)ILJosUm|K;PJ*^!RI&G6xC$X1k
z0SDIkHl^qlo)b#;mq{-<v}3LM;fy3(WcXn;UL<DyJbM*ZVb`bt!W{;V??4W7XfYd%
z7fY99n`@3DGRqVG!_Gz9_aXDcP>TabT+7#@I*nDGF#L=2k}UqHB>s3XasPJ;U8CW3
z0FIC3*lXB-+_EEWj>N70kT(Zj_$)i<`|hc#82|P#_22BFxJ{(Jh5euM5gQpN`FG8A
z%X<s^alXzJKjkvJ8vItmoD&Wx{+B7Gzdte04<_0=>(r}6%qw;P6yg75<i7BY!T;fj
zB#-X^QXG6fdvF;$lK`D>g_v#l-lYt&Z%hmK7nh-iO-;|waUrbtGj=<-Q%)TFhS_g?
ziwkNV`8P#!XJB0{8F!2MZNa)v|4N3|W@%@AEDL|Ft}q0I<tyyr?D}cvPRs{341ANO
zpk6q}ihN7H3Pt=UP1hQ%Q*EcReDY3KAQ9N*b)Bq3!HAf=;spBX@_8ZCzME<x+wqs#
zTiCYAm*-xhj2kUyVp}0clxX7Tm`j|R$C>=_mukmH8*ZUau^O}GK;WU?yyZXlnk?>x
zRGHA`+7G8$5UsB<eD<z|!M#^3gr|?K+WbaqxLlul`zLJt`kxMVWN)(e#Ft*F3M}US
zt}S;TOH<!Ezvx5(?mgtJ`?tSVy@-kxAHrqKAXcyUwqd&-lB7oV-)jCz&Jz^B!s)hO
zSoiVnnBMC9dp7&UWh;K+;$U;{wlua}@jL+Lp1OtWa~IHdr@q930Ntel7aI2l`Nln#
zCTgJlzC^XFnv9S|3UVH%*k#MKC+~GIF*(kUG%_@GSN$uJpsk%WrqD(XiMkuN1Q!Da
z7}Y_=!_2;*z6nt1M8?0}%8Fj<v?o86kcn0c;(89IPYz#^j)gmBLh=Ibp`$OGK~b3p
zLUuIkwdY3j*L1Jmm5dknDnS;0J$ECIa(m?QS2|7p$>N=q>gDR);%T@H-dc3LC-h}A
zYQe<1|0O=O;xoaCjU=2?{wNc$pRlZWoRy|fdK*DzLqYZ^CGd}>=Kd2b>2N{~lJ90m
z(Fv!biP_Fp3Le)!87cK5TvMoOyHiym8}-cYywF4J;&K7t#*-s;nksM`lWmhExH(oK
z`;e+O;*ef2Ta?f9h?Rh<)9`~=5LwjhrYE$a#wK`FWwEOfj5|Jdmm*_MJZFKsX2O%W
z0Kdp|DRXkxBCTYQ!py@2h6N}wW+?Z3gplHxE*Rjq*&QLtBP3=9*7fbJ>LGl4P?6WA
z%+)zo*xo^pZ1r;FN^CiX1=^ZB374Bgqs$0Yi36RADV-c$%T^<5YKNTDie3a*N~S0k
zO+K<vg>GY(h~+k+QXA_HUbWi2WFw<~fyrRD9u%XmG08R{Y-jzjRs815y8hTRy3-K1
z0G;~T!Hbv|zycrb+8p&9y1YV_iuwj7!m^W{vTJ&s?5B}0b~1|*_!Lh2lYVyAa!-Kg
z*Dfrdmm~Enr~?vUP>SXa4$}5epua?70hTE9sX!|tbZxk9qxNR4aueCh4@0}e{U$t1
z(8DKbB&7;`DqPt;HRNpmJ1orIMkMkP1Sx-!hi+ZVsIB@zzABQspNyK5<SOB|cPUNn
zkrd2F-(Vw6ud^#WSN%Q|63c{7Mk`i-F%Z*_Al;DCGpIMskBe-C`|sGA%qPiO>+SQd
ztkt_NB>X1`-bDf2RZ#5U5#JuBad;Q72SQJ{H0AYBbqudEog`ux11zoW%D1gqk*HDN
zio*EXcQ%W7#Bnl&C?$7t;8}e-tH)KXJhQYyu@IB1?MR#}kq;bQ>p3jf#ps734G8ll
zeV-;mo9(h6=TvvWRPvx|a~It2v{IiF`>J-kp<fC|Nf|Qn;dtd#WKdg`NgNR!5sM?%
z-4zrk#>Mv|w7!JFI8rJofRE&f8493$Ify<Y$MSFyiXg}sWzvBLG%xo+s3h{Zm}2%J
zLp<HR6VV<XiT+Z7c4Eb@3~$D91D}flqxOxFpovUV4TRn9-by0H4gue`Ww1iZT+ErI
zSb?{1!$ErwzIP=7GuUyJwMaZ>gmDgBOKr6WQCp9NKdltbCU$$<k7Ta5lOJok$8yJg
zS!$a6S~W%gpZc%GdO2e_t`*J+e=d@CEMC0qNm#g+)YkMHEvL2dcc8VqEZmnT{G!R2
zeQ-4FI=0h@h|tqoYEpZ)vqCX@;lkYVAKbKPA8E~|OYe#;gA}pNIY&3nmpQ33ciV7d
zy1I$~>e4y8GRoFmWn=UIIv?Zo7{%eON`w@cjZmJ)`A@#vA`>h2AD<sv<zmrT1clfq
z##uG{;Bei>_C1^0yi%o?rmp?_AC)r-;Hu}>9a;hFbKKBClXc<tonv;@yYpq&pxmuK
zhT7^-TeJ1O=GGK541~|{BQkeQxp3^WycUxQKTWDV_vPWq2kTMTiOli8^=U{JtFm?7
zuI${_qqO($X+dzejXr#ly?ytWbHAQtH*;z(a6=1??sh(Pqxi`k2U{arE<UcMBGlGo
zK_mx2zTV|y&}_eT+O{XGOke8eniRG8m!A6k4`zkL-$ZO@do`>>FVY4Q9I8rqiKqOU
z3e<7Y7}2a*1bw5ZPVIGWRkg0yxGz6{Vd_aV9Q^2qvplM;4Rz(qQ;Nc&jaGQ{-q-q=
z?ccm`PId5(Od^WiNnf76mU8bM^~KZe-CBJe3S7ByV{X@6mfLUdO;^7%vl?3xB`Fq_
zo|2?Rz(I&@y!^VfYSCey%Lgva*B*Jbrv>TM>CPE{?%mG(cQ0fy@9$auL#1=UZkk^e
z^X*SD%8X5Ae(VtMGJS(M4BYfQH`cG5&yn^AvZTBtzLZEOP6RjbEQ!>4LsqL2*;6W#
z0CgA`*+2t@!d19CIUn9tzwUbio*8zlOt7T3R<fo^FvH}KFo}kPa4;N<2Nj{-tFx_A
zio(}-Pw-nGS;Y^MR7{W&;qcAgp1cE&U*O1V=Ob||h5QFYKHAItxmS()qutLG?PO}4
z-x=_A$*a^?x%FLjz{`os#@bdoV)jxipV>H&n4h7fM_&=x-w&34$2mLx<`rY_i$wh1
zTrB>VLSaW2NIFFoJX6sfWKOO=&eYnUpIWzzOjEstw!llgS*#-;r(|1E+qn89;_5Q3
zfW984s4mwunGV&xuFVNbOZ@@NMz_ETk42ZQkO8jo{+g<@-Ao?$v|>{wrq#qoianW5
z2HeHw3}@zfhJrvP`6qcFd#1Of2)<5Ma~|fyW_HRTVn`upB{K=qS73`8_nvHh#+8_h
z2T(PaQoEUV7@r)AD%fmM`(-6}GKK(MdwI~+427rrQ+P45mrn=ESl<4qv%9^G`lT2h
zFjYF<U7ZE&86Is#W^2j1TBCp|Lo==vS*Th>Al#8CE1AJ=3WdP4LevkKTB^_=UqMRP
z5lZvS$4d7=o5@&!Br69l7Ar<KhVpgtsK5fTJp_abkF65j%%3VXwNw|QNl$3VCc=%r
z3UC>pT5=k>j(!iVIq5RcY7m)q<m}DK5)&TvBoxWjc$O>tc~{v3&Ezg&=9+qs)y1lY
zsU~IET^_PZ;7!okY(LY)P%E221-eZS4p+*@oHvuOBb1n$W%WS_S9fh<xO}^o-6Elm
zBUGptqU1%ZD={N<XcH}{vaQ^;nJE)J1?+b!JdzCq$^O^db>a6C#!!~PXJeA6Dk)#L
z)i~18Qorlzg%I_c*{(D(O+i3pF=}d_DMth^lRiA@oUM9B<a`%<9zmf^8KQfDkt&-I
zz+!1+ITojVQW8Z~yNA)Soe@rpl(c}_su*)*#fv4j>?}$#;8FSdA;h9A^#^U^&O(!g
z1FP>SZHQz8V|-dA_q~%c@>Qtyu<12$%5Xk3q@Gj`%6VDU87XH&U7b}vfgnAerv;PT
z$b<_RUAqRK+CPX+ArV4iB3K%Rz|%Iv*fOq4>x_Xz7!ZB67Gb=&Iq3x#6ZihU9kj0x
z+fWX}MtP&L?dgk}eNN<^%!SMToXMzWOX07WGjH%P7w}gT;)SX5@Wb#-vA!Jpox-+-
z6#h2S_MUZJf!Z^u*YGj>GJ{*mzF+5^ao@hQL(;<kL|N3pZmUUcEl^tnYHNi4!KOhx
z)rQt9C$H@7oDbu_Xe%98-zdM9dSQm%8;Vkn3Oav}pf@eAjVDEz&Tq9_?WK83%UR~g
zKSW(0MXwD%Y4@YH7MWKw@D$>km$@k}^IX<9f0m6V*L8KabQo~|h*Cbxb7aiMkM=cG
z@-oNcuig1k+xODu4*l7QdZO|VW*M3bQ_FW~A|T*s?ypr{(aVcKd;6cCUPf(ACqB)O
znnb;XPu=`-pW5o|U%Y8N-}kdhF#tUA`(EnCeZJ($cLctidWaxLnap1Ev%73*<1({{
z4>Y^27mR6>*E?c`lCI4%UqNk6QCkbtR>^b-Kt5|LJ8j`ECaCStlIWcCG#{|z-<eqq
z*daR{U;<@XV&F!}VBdOEUNE&vUGl4JH@@HQ_CB?{{>wg_D88I`<L;$4n>TEEm7ffD
zHt~L2@#s*KXtvgQls%j_D$qcHvvB*4B3->9)fJ?<UA^^FdJ;c10-K-Tv6@b(MGb;E
z5(w?kBZ*$pp;4B~`3pG*!U3OYQ9zQ#(XS+S>jtm9-?(^}XKBKw_Px#7E%9O)P?YV8
zwg~x(axlbfQSj=!NVz)Y<(Mc?I`-uGX6eP7@@akVM@!GEpM(UV5;oO(PgGm+?j6m$
zPq)2!XbmiGKt79?U1&F7f1?jy+1pC_6;8?*Z0;~~R_JdEFeO{>AEn2Tq<t{hQz2y>
zd*lN)*|R-qcH33+HgSkV$!KQxcE;?-%a9&VS?HLUqs1&PSGRBEcd%L~nGFJQ))k`8
zG5k~*2~Rw*<Fw*r*;1>p?mq~FsKt0F0$;AI=*CDMg96}XMDQ1nuzrY;z0RXaH@1Hh
zG!XZ}5ngj;HCyfrJ+o66O~)%ZCrg$4GwTgn7YfVv6bBAtgesG4`@!3xn*(Yq9KOIT
zz4MWidGAL(-TgwA7IPP@?DJRiYJHJ1nO*7sNhQNgI@Bt){iwFta4i4Ta(+%Aqpw`7
znk42ZO9GwmIiLE8vW<olA$|6hXgo_vY2R+eDHg9s#-9^?LaY$aXr?Nqe&flWIE13}
z^k!oS{pjK_*<`an=B#dQZS|!%skJx<k9CDjt<rGwDU}d(HS8_W1XcRbU~m-*1A(pb
zY_0w=#5)w57_U;A=jmrmUJ}Sq>XY(U-~cFeQBwT+hLk(kXVh+j3lzmG<)n-TVy%|w
zq?4nTtz1VH6OznOv###nGb`eOh|ZLnh_kjhTW%}NapKzZf@LBw6u52{drfeps;<r;
zUC^UUZsFB|b;?h65^_2;bvGJ1F|z4uQ=BF}1*ohEB%sn~EvKxCe3tYx3X7mt`xTxt
z`nEGj_LO)`VOpug_FSFdxa?8n(T=&{o(Qgv>$Ai;v(l<+@9&E^yVF-0dhCvC#bX13
zdUC2*O*=(03J@D;WD%$!&*Mr0DQx`dUJgAL47kLRCY9NqvR~#qm7wpi;=+}`SHW2y
zMfuMN9zt1IRveNL0qjUsL0hoPb>XsaHnkOXs>>;WF5juglGyyYu1oY!0eUIIrVSFu
zBFI|B0D*Dxn@@y$i>~ckJVVM;2;uG0@*SA<a8)5luw7`2A13;#i@~EI_0bW<Te)l=
zHcH%G9;bAUXD|r!^=!x$Njr4a_3)QGveiCWM2ogxS-}?}sCY;jbXIv;C1e6JO1}Hk
zXOYE2Pz>PBBDcvX2b6@I#_EaiB0DVj1$K;JDMC0YWgY4R+rGCBL9b3c2WyLc=nhVs
z465L9`<)P5Nn)=O!y5dig6yVIM`=hhLqN<{jf6Rj+-NgF9)ZR(_(70i(P5jTqpa3V
zcay0Z7UwuP$T5c0CgO`=@K6VHB6xs`<3-`q`)OHKTb|8sBO>O(4c9%~6Oo6|^ccop
zEuMLDjI(6CvC@1z`2bg9tZYP3*lXZ_jtP|O2#;rbsKthWFLPi@B-2%js#FT}d3c@6
z?CbrzhZW9grqJVA;IcLU2&?TZs#LIXNj(U#?b$=IEbKcl9+;km|3n+yxZI_-cAxRH
z7qv<xiS@3VVeVCw;%ZxPiv2bw+Ubw-<B810w3rNN8g+P{2*${8-BMR!cKnj*F=OU$
zU;X8({HU!P&2DS2QClPGwgwc6?iKt(<IdnF?x7g|w+ly#<fA)~R|CsBUvqRZpX;{k
zg8XrdYWq>fTE}|U^FLzRZS{8IGEz*f7WOBZWl7%Za%Qi(V`2Tm>B2M5w`=YXMVuZq
zw9jU%?B(mNxBLg$V)D6j0^g)o3_VT+uG}f*pI(`u7A|LXBT&%UA%E|(X~Qi~{|&{i
z@WOp>D1sUwyGjK&NxG!{lx0Usq`vdjOHpl2_kS<Rs$aP`>pF15tFPq82Y+^cOF|W~
zGn@MkBq=|_;o_WL3X`C^_>^o>=x=#5lYRJEDi`=b5w&%<dkOhU)TphSyRA07+Db}}
zX=XWU>rr-Fv+xPZgG3L0y|h5&q&Rnu(=eUCp*YuMMX8Y9U(!WCg4#OeAM*aY=VTd&
zgp1;v7M|FZQKeMiY=EtVj~wz3<{T1kSr=iZopqb|czNCeGzLR>V%4>>$1Q1p?Z%9*
zF6mbg4{sx&XTNyiWO#6{@J+<Fw%9uK;(d@piWM=Z)4C)53jp!Dp6&~;F#GLa@|{=<
zb*)=<f9P{jWacK{uzP*m?CMB|cIsKx2r1cyeP42ch-Q<wxSUI73btXTM$i70r#6xP
z7}u`EX+@CQI(sb%_OkQ+belTHJrtB*xy;=4KV6i^_b!Cv3nOaAlAyo+Tdhnx-)cxf
zgF4Gi<2H^+!|rb~vpaEVJ~G+M*azl(!tZe@-re8!u6yh<n+9cW{bgrgL~ZRY{;NEo
zj6aetPi4v4mqu)1$lccVLf|(CIV3!PkS6lf1MjGd!&ENzcWIObYcIVY3w6vk);`5)
z;Cre<QsV?%4)Y^1q6*;EaS5-|HT1D!gff#!NzCr3wsw&%H=@v+6Z5^lW7N|CP`0I}
z)rYIYXrcVW;FN}Jbx1g=w_&})_#|W`zSX$~tnwF!ZcajZ$6IXbg{Lj+{2!Xd4gsYY
z`wLe0=SE#V|C#h?_80dC!b+u0dZ)}U(Rv<m5@}%{Txe&{w^+8xShFdoQ#(2nvflM}
zG#uTr+krA3{^f|bXLoe0_ffkjdEcI(mX>zT_mkN(qCNm3XC=Sz#v$RnJft5Uytgk2
z0<R!rHs<nM2MRc~9<9N6W3DtwYrAf^_%fV9t=d;3U~xKCCn5qdaEf?h_$h{nvsW@p
zf^bSy^pb<#wfSr{p)o!OA^hLgsOz%3GQ`PNnH91fxELAP>qK+JCYb^?p{<Ve*(WN0
zG)wW22IjPPkblW<W(#{U#$^?rw3#(~nx2Hjvt$mvr>89*hHbqMV?mP|w@Ps)6U;z3
zRxFKwfFGvYESFPU!ZU>y216^GF(f%Fc#$0Ki>^fJjEJht;;IMJeDbd2v#RDg#%K>>
z#@|jcq<}s>CbLQg)&NLisX+=!B`h5hE}4Qh8xFw{8IOlyJNQuRs$dn%$*Ih|9K%7d
z#5b6t*4zR*QSH1&a&>%2d>7{x%HblLW^Bscq~fUl^?=P(m!on(nskLSCPq}z9jSrw
z2q6}$PQw6m#D!@Kymp*!?c9QPRlIy|f??Wig>UPs@WeUw5&BWPROH(gp*%c~YbyUf
zJcu8BLMACe=I~gh>D)O?ceSjm6u=bJJ5R85vQYV>Br7MT=ZUlPt@^Cv)ZGHlGEXgp
zhCM>g0x994d!5}+<reYCA$6dV6gFzfx+9tb2WqQ^SxS8`?SK}Y%yw<kC9Q5i!^z#}
zNV8VuxFQDpYm(4fLKI2b@>!2XltgR=9(_f(J(P(M$r^TW>QH&V${UY{NCM7d3<X<7
z06m<Xf2NH3>7Pnb*#oUug33LlxmitmFM4WbrcM}YI~G!IcQQ|esK-1=hl!uNjaHW%
z54EwW;y5SDyCLfE*<-Q%)Eirz4{*u8CU7wWMMg<`n4A9trgy|RBVFML?<zrTaA1Yh
zIF1J1Iv!rZ;4x^HcyJ8`jz;2zd8LufCU|@y{I{_M`_{P}j@myJ(qT^PIuSTL9r(z!
z^RQiVQWc|tjxZ$N>r*Z%jf?!6Kg1Ml2<GX?35rOFg%7~d#^u&2`G72W+u*h-B0iob
zF7LHWzpb(Q=VN416)ZVi6)Y$u-d-9V*Ct!sEokI>9+|P*iZ&PHhcFhvSv*k8E$^H^
zmffR~KdzbC=p(qE{fACF$tRO>8iDc`TQStz_r{nb2R!l3yfaIVOvCi~=Emc4`5LwU
znicjF>BPN%x8!0f3{7;lhm=z?tRMNW9@^!`laWrRL7#wuo!2qKtS$G#tC-tzF0|c5
zZfB=DKsq0{*WRSTr~>%#``%`uK0unM#Y_A?0eh>NgsbhetavFWWJlt5KAJAiogl^S
zJM(<+-(|=e0(60;wB?XXg_t^#WHY?8RD5ZE^Vmfy<2lO$Hrstpy(IRZutaV8k1*|K
zx3zbi-B$W;GZG8uEI?(1XK9)5W6Aun&(aZ;9kBnqS@u+MuH|pLe%+ixB!<9~WuHuw
zYhHe3Zp&-=uYT&o!MyPkHR*4IvSP(=J(FerlaJbnv-#9^aM{tv-ewtE&y0QYB6@R8
zW!mG|7IwS!l^g$#w^8SEXUn1ffLpT8GCux|8YQQ7O}oxr31(Yxa4)qLTeZUE8Jofe
ztk%vCuf>Su_MIULt*T?9V&#v2(87jq@#eUcY!Pdtbb>Gd9Pcw&F4R06*^Tg%kb<Y?
zclgDcpXvxetbF)8C)P12K@V!{uHLozf?Z6%c)smZPv~Gst@zo;)7)SC(`>QrZ9Td2
z@D*B+PWK()Gvq(xw!FJ8(R&k+7`z;u>h!ET*s`Cr@TE76Ot}$;*JQs(4`D0ycdj&l
z*{kB~-!Xe-di7SAWn(K}ez#qf-|g&~c3ODFYzt|4vYRm`wwR2uCg7I0usPOCA*(~e
z7fx5&=vM5RUA(2-rgqw{#+pq`|Mtq660s1SCpP2cxP<2$m*=|!12N#FbSm3w<`l!u
zV(8@vBrIEY)FO54CBkFBZ#O|<43AfU?_bZ1Aqt#6G-_G6qgAHQFXiX^j}SHtc-qj)
zr$%h|Rild|{%V(vPgbm!9MumS$wTI^ps$?N?*m10S1wS^v#IMboY@E`>iF|M^d?t6
ziXOk7t$M;O<ry!=wCKktI2@~qi_f;aV0#q39l#mwHSt$IyW^<tH1H=QYhLWRwZ~=&
z4=2Z+-M1d2Xr(#_+Yg6K_2h_H?GKKjyA`77*s^5<E1YENRL((WRv}bxok%POL>45V
z3aE&BZL|sLw*wxhCNL!I>Vi0$(WpAHVZr`Zx3tzI-?om-fU?C79=~A0)!Z^wrmvco
zC5TDeJY9`l58)G~2qTz8gH#3b(;am)t`W{)1%+wu#~O&7eLyDWy7V}Hb<buz3=uFG
zJSgg>s?pS8G*F5)Ag-v1IQnB%yxZmBVe2G}Y3jI)$N09@o-Xaw*|efghtLE?5mJxw
z#rX=BRgX6UVpHD>O?l2X=+SN@c#V8yA0a?wFlYwkh1Rn0Q}xtmJ?VLm+Um$F*hz4!
zElDogW?Ne-VdyGetahDcyN@M~Mf1=VdR)?|nJV~6LC<J!g^yAp)(z%tTJyKDac8sZ
zjx827)ks;?5xw7q9d?GqW8oYGWaz+=Xgp7>TiJqcG%F+WT;fjE@B)uYYvUUA+l;!u
zf<21JIti_yk-9L>40SnUjR?D}(2%XoY^KlxV*{s>42sxw1eqZ_FFHJtoFdKw8#Myw
zoU<%xtGze{m1>})-WHsK*jkWLfy3${Og9nK`_^qWwY1mt=Co?UDouMH!8or*n6{kG
z3oTfco%f8M1E5RQ0T5D~b1N)KoZP{cML^y>Cr1!|R)|%k7SjKAO<~5XnA1FtCqlE<
z2K$66Hy}wO1*So?s&o^jiafhnCF+Y0R>q;BFX${zWn2WO5s^9hS&&W(c7(V!1%I58
z<)|F0LcVm*nYWG*b|0d}Ith4@&eMEVt!l-Ho<|Hg{&`>lpGOx=1D;gubQH=X2+`cu
z@b;jp-fL=>M4oU)5HmMGbc5H?(Szw)`rg$#W*aMr0jY`YJz0xsOT!8GwZj}goFVW$
zfyX8ThY|HcXSWsaGxXSSAxS<&I;pKkFShlC{1Zam9)h9|H!nr5=&=({K}GMKUUm)D
z_np4--Qe0yc*=rZk-q?EJq`(@wz`qy=_c<D*6FsY!(Uz;UEY}-OMlVaT^sKX5$h4w
zhO;->oy+f|_8$94rrL{b&fCWb`PM5eb=pKfu)vMDy#4*W;YS1OB)y4pFSDp;FYUO(
z2U~tU;g4QOckL)QAkSR1w>74cRmErBu8of;zdUn*!<L%~_>qfr_QW1TZC$gu_nh)V
z+C=Mfh<AR3Ba5Hvp&qH%1+DJJlblj4g-l&)+8=5KCbt<Wsc4i73UNFCQxW%H!}4n%
zoXvltmWUFb4XSKyb^(L~s7K7{r9-aw?tK?W;R*CS-57y8;K?_&Fmle0&NANJkLwLB
zTmQmd^J~8`YU7}74<rcx@gIA8-;~oK;T8MSap^a9{dZQw@w>U;<$~{|$vqn?8<;D^
zgzS?=a_r?+_SR%6&!*lFH<L4#zO_iM0;LT9;CC#4Zh~J+EJ>u5!)LgP;*M}HGAqJc
zL_6G`CD(1w7P0((Tfo{i`qN2p)?)aphYXJ>{@?R?Rex{Z%8y@Q$%9&k9tIFt)u2#Y
zo7qZG!ks@C)JUt*L~U>5#E#qI-s+y0SU|YyFqhX6n*Q0P3sE}y-AkLe(su|P3~)E;
zKwCl}S~?Llif^1g%@M(EUsWAj3L8;O!n@~xv7~oxFuVBv++Ju~ddt7BmW&j+4Fp^I
z&*v0UTW>qEmpRj+D<q@2Prc99x{tltCp7G$c-D<;nL0MDETu5*Z{FfU3FZa+83{AC
zC6l=YKQ^D3zl%X)&&{mi{;g*l2e|oT%#eJt`|1(IUsIuP4~F#4$7z=^aB%+v_SR5k
zpV(_j>wnmpo1yC8v1817KPGt%1KMpB^uJi;-*~%|)d!D2va1n_(LV7X$YKszd7)J;
z=t$yh;~ylIr!U!dPFF=<Vm&!F60eU$HaSlkeO8fPMg-JW3wNAzJbj)uQm?x%f2R7n
zxQ;)Il?0zYvd}B8x<AdjS5J15pGq9nR{H<E-VPh*t89Tqkfh=z5-Ds>%e2nAczYj8
zuZ%re^~Ji^D%-z~U)c_P&=GrtpDxCdQfe!2SvA56wp>lfDRy9RU;WgW%^}>>cQx%5
zglK9DCYaZ6e#WnC>%ak)ZW5~Mr|zm1&q_s+8;F54O$Ak4cFensKBO5&RSnE3GKAop
zG~bWyA~Kx;>b^?ItQhbvnld(_c_{~lI3CYq;$<N4E1dl91w9l=bxBjkR9($ztKTGa
z5UYw)(Q?#rISX+ivP1~x43o5FnxKc!iWk}^nkr~F(&2Zl6frD#awS_S?UbJi=}QQ6
z)!C(LT=rY_(}#2hr?crgw646$SJD7`I5)Gndjei5ouk+ZgI<x|P4p}nDl)?|hIXCh
z845NT4E1bw3c3x%LWJ5^wWKDhY0YBf`-W_BiH#OM&-Emo5wofGdQn?d&-}JQAP9(A
zcAM71Wf56vt_X}1`8AfUtSfH{AhaS=7u|%cOcUB<EL|X!>z)P!*l9Y4EZ>S~m1+}c
zDhRuyVWR>Km&3uy@(FcKP9g5ILP^YZJA8~Um@k^+*#<u%ZW)Ix$~6W=0nqf7y4!7V
zrffz|e;QF&VTAbYKtQT70LMV6+WU2e%9^xumOJ#bt1ehO%uwXuP|ifd$tY#aSa#&T
z#K#j}D@3qTfT=Gy0*qND;54}wRLP7Wns|zq+oCiI5rn}~sZnVoS!Ufv{xP+SW_2{k
z8ilzE8({WE&VYc{>tnEoE47#itn1u+s}y25Fk*a<sMS(FBvEm9CTcOh&zM9!@nDk5
zyn#Cqps+Qb2=`U~#@lD3e`F8J@1$q4sV6=-V>B4tG_xC4OxQM}1jk4)8%4fqOnWju
zaPyIeQwinC4htrh*TrI}8es0H@qAPvf_a|6vtGTtf__mjvKU7=oZEm4yzpE>V_4`k
zXt9As&kY&7!rX|mxpv>6Y-2CRI8N*8ZY0u25UY8@*OBbDqG0@%IRe61*b#zzuqt^g
z-Yw}KN3q+LIDQh+b@GoEYw2BS0CxzuD+(ea^5s-)hN=BNeyPy{|AERr-SlrE>;*7T
zTV333U5E3z(-BV(;VPA0Z|8D1xyRDGd#~Od+v7(^lGnKLtl$Hx(9}|$RO9`Nmr*^b
zc{|X`_<?Ie;zjmgYPYrAOSinMu7vRVm_E<#iKR%v<qtX=*y0?$<iG{qeAiiWDB0w}
z1#*^Z$7#oWE}pfGR0kXS;TN_&FAJR3&6`i6CXj6UsxKw8aVPG{ecn@iw_N_1tz=iH
zxl?AlU-GVec(hkcTsN1q!M57^>z#q$F|?JznbJn`_j0K+IjamS@iHI=pm_c42kX0<
z&UxobTT&0AN3~Id0GwIeZAER(QCq!sTLYe0LBiM$9{jxv##T8boPOrBWPSNL#`M?!
zU*Dwpu8bCoZ@V4^T*;ekUG^E@`+=9Kw_l#~Yjf|XZl`9_kiLQJj%OC0$((;~!WT|=
zWW$-4+Inla!qT@xLR8jn&%#^~&27PPOW+UsV&_j=^1Jt3=DbQN&?v8M&;4KEMoM;D
zbtKs-VgPs{YTJ_q5)_?!+cPND&JTuyb%#0v#d4#!P-sFl!9oPz9KY<f3(iu@rOe%)
zv*NFQ{Wr~i^^FTkI}l2;-Mo@1snk|ie*Vpo@ywBa{oY4Yom@4~V`SS1JJ>yYLUHt3
zEA8T&bN_rBMezrjzX@d!_=nQ<#q0kczW>^Lfi3^fm*-DI|KbmgFLt$(-FhdPJe%mM
zq9)rSwf5g|T3{`+;=vong0qpM#qGrZGUZ(Qu`BKKm;GDI_Iz<XU!n5d%^ypOKPcIU
z`>BihSO+R)dj_p)5L?85^)OgJatW8JFd&B{n<cDD7k1EYxuDsWb})AEY19zZXk$_n
z@1i6nuX)tO&9`#zogB70Tu11T@W?l`6eQ3TAzX*&g!NKoONdV=cQ84B`%tZk6#T#^
zXMwwww#?40%CPin{+#9wQaoN=UQkVQh}?ohHygXHBg^UYENS>1boifP_Blj%jpuvw
zxzXj-`Oh$vc9=BrQV)+Y_uP3C$6hX3VmPRZSjm)&moj_Qui0Xj-4WhR%Sxuht~NhG
z>JttaUYYJTDm?Radb;V{EyWn=UM#xYhu{z=uzY_w=@elMJl$}1L(((HCD9v)W{9qt
zFe#b3JT-<mEd0a4mN=m0w|tRO*rcI;8jBp#YFu<NZVP`Tstaw+r-lI?eh3bp`$2VE
z#3HG+ZpNLtEXvyPMC0i*RKMa*g=#K)fFdlAk8<GK3f)CAdO+jB!&Zi^BpQ?D1yd*B
z+Ud=pcllnb&`TZQIteRQOI%`xQN|S+=<|t9=&dZczv*?A_spisox#KrZIdkEo7u!;
zn9wd_K0Y<v>#a&i`%HVZ+1N=T5E^<VtIhb8;qEGwqvo?x!8#ITNV*KiM0ag9z>C+i
zME)flo0ZW}I*TpJ)+65}B<pgc_##ytkIC1Ll9KC8;1#Hx=Hvi^WtC$)6GppBUhK1S
zNa5lO@iS7IMXIBVWs}fH;7-c#KuhVFy5uGgqrtB@IGYCVN`z2S7e<V7ufAMQ_<_kO
zXh#T`vpzbvGb+}dP;Q6VL9(U2M9@|}`M7|v%{zFnkYnWbhKH24-ranSSEc0Ec==Ug
zum2rBwj707k0cG~GzLJnNtbh#=m~?NOKw)v$V(Qvm4sHZL4=LU)8G5VLO%p~8qrms
zmN^9t1Gj6RHA~t|axBoTXh=>KTWN8t@D;>Y;K{GE)VFYO@k%mtyUxtDx~r-_U)q`%
zpCMK#7VL)ED6E!ad<JT!lewOJ+d>+<56PLwRV`@~y`~b#yJ9Ld<=#X&o1>9hR|wfA
zmd`fdvkFVdvnR)?!)&ON_^c;^IN=Ndp}}#nNyt~C84L$=)}^C{1y7DjRQQ4Eg4&Cd
zbY?du;j*AY1sw6P3)tJETev_Ks(sdtCPAO2^ThI{qa=^*7g3O7E`>l)mEM^*@e)Id
zI2OcM@0Qds2EarI1P}w|sm{nX2{_s0h&qQ{G+VkW?UKuo(B9*EXs4N-sG34K;X-=r
zG7Wf7xFDWHJK=ic?qV`v-z3=}hF=v(S((mz%M)*jxj26jl6q=JavKP2@*)p@cgNW!
zd7-(OnfLw;9<{Y@jp4WOJX6W6GHa?SYOBj$F#A}KH(dIsNckN|uD^HJn5S7+Gq;%w
zJH1W(VxDHbt6-Q$`baAuvDdiQ*nefLrHzs=G<iZW=Eu*Dg|7WB-WP4L$OAQZ3z2Zn
z&OrY2Ph4cq9woN$NoVEtXg`lKb1ZfRf(&G?^=sa;3ONh(svVRcpsBXb%T&h|OnS>c
zWcI#qEprUy*Jw)br4<eXYF^rH9Y;IWQO2P1=w#{CKgz3bTe<5u(RYvKS5ZIsc+u5Y
zGBL|zCoW_Ek%F;T`ib+#yFbqnzM&xhZpzI|sGX=s$^PSeU^c9O;yjj=zY9N5)Zy6X
zkZ>^SRdS5d&iJ-9?zTFqt?ahi%BT7_U4(XKC|2fQpZ7Q<9N2BOtAAwYjGEBF?|Li$
zct_%Y<4-J^{peVAPH#nQWX{=L<?@OpToQfNp_IMt@zqv(k!3~TXFaqL`P>6OyZlim
zVy!%%f9CRFakq8lVC?TMd>pOkq(*sW&fsW=v&sLq&ixb9Rhx>4h~?g&SS`>W1Dlp%
zTuT$ffG5w)3A2B<wS-?N#Gk0)kg#QA?=|Z_(b9;;N2b)VG~90Yi5t!S>|MJwY%ImS
z(hFZ5o4M$13$duP&#<D9P=3@_hZMsX{uz50+^MCANGG;A5h7dlESf)XCyn6pf5MyZ
zVur}O>81YPTjCWn2+9LAgg0E4y5HW*G#qTbPv*Mpw*KY4+;i|w-(LUAbaiDj+m(a7
zH2*eZY@946zVu;s#`KGK%j^f_cXP+?kyc3dyo$5uFR!8l0nH&{2mf(AUVu5~Py=DE
z`{IScj~5FQw|$fD(%?%>PhCo`Xq3r@Ch^TCYJ;(jy%gj6cUz&Lk4&Xl+WGBPaOkta
z{#*xKj7)C8BxKS4oI)Pre1w8^NVwRzNWvcu0^0H#6hp=^PrX4(KmB+ftEzWxOW`oJ
zSzen4d%j2}-2_GdnbgkNHc1oti~0OHb62>~y?XwMI?VfvcRB0rvF!LIDDM|HsMzty
zVDDvpk)Ea2lYC?InS<MpQeV%2vzFx+u1_)wLdzRd@kb1nDv(1>axnB(!#QeY$q)G&
zIhbi#iK8FAIs_5X?i<fAwxbYzH4;cuWXqxoVEDpXHASx=LcB4FTG-5mHtpuXt!EV#
z(sm|-SZ-3Qe?Xq9!io}7!1nO8qNjP%ArnabTX;fJ4*b=nK~Ub_%1?hki%hE;s7%n1
z!5W@iTo!Fx57@enLw1DpPEHofHDCEL89cTi$f?u=fuA`=7<uX#v}$A@?Jnt&a~R)i
z)5n>@uGFyuEw5rouD!ZOygXm2)Agdn<(UY+3QJrq$BCdFtEnm{-f_MhvJjDuvK93*
zR0;vyuS?fq-?7Ol;+@Ix1WKM!rjlF9GZZj|;TI%X^Q3xeU@%f4shSiXs>U5_=O#is
zEf>}}B&-~=iP7MvP>`N%p%Q%(O5iJzXRRVa;Vko~9@J1l2SFA@D+jgWtKuT2N+{o&
z1tL<G#0C)}-lI#0lwLXsQT|atRaVak9NE>oCs@xiBG4cldBse}b&ibD!5r9eqDKf`
z!bY<`h7@}SAX_>n^3#~pOUNp#D0v~La6ZX8K_E0{J4c|OH+|4-!b6N$stB*<2zp%=
zIJSdFh;(E|@~RnoY{3B@Co+l<7BpQ&Qz6RM^AJrauE?3n>GDM5OEoY$Fyi2$nTD6A
z=FG|779wZDP<BUoypt<J2Q#FQL|Ei6=?sEnnghVKXw2d8b%HF=kBpZF?Wd8ScB51R
zN2wecCrEp|q&35Rkm@+;9f^j4m@UcFGh*#fg@Q@%Ar0RN9>~KF(W%ox5X#0QW|ez|
z64Oe0BpCvhsv>mMR?|7UTh+yUvPgu}2joQ-AmzP?i6-nNh*UD_@ke;#7%9UpoD*pj
z$a->-q+Zu-Yo%(5HD?tS2n_(LZk$5H0JOl(0!9t|f*?f?DtcxcRl%FMv)FCsIcmT=
zC}3_&R%)&V?6X;f7bEycFh=-_#Y4n~RxrxtB~JA@cxe%=9_NP57DOXkQHN4p{F;Iy
z)S8&TFuJw4?re%|%a{pDkIL4hCAj6-Yf{J{Q2I+?_JpLgqtpjXPHD<kS6j_3B96qe
z`7$9`G(jx`T&Bzs+Z#y{G>x1%Y!ltGg+_A;Z_-1Sg@8atE6(T%%vC4$n>kTQhU09H
zO1Zl(CA5?s**D<i5Kn3?Lx4XSr#RUwai0QNzdy*M5GRLVvyoQbvzb0dRA!A6YWpM#
zr}9(doN6^`PYplSpG8D5+~uJjH|IA&GSi!~E9og>XmG+*a)FQL_iv1Bn<Vv$P8mEj
zyZe41j<1=ENk|{HNuzPbS}Vl0o}8i9I~+n`o}mz=q@Z*qv7l<rJaI#T2P<dl66cN~
z(j<UDA{LOXBg*vRbyXPV|2WJ-q9-!Y)da=KO&KDDXsU3h0R!<CxU;r5FQkTCli-X5
zo5<5`p%;-xwK~aFeGJbl8lE%0J!qev;?$6mfXVb21r54{DYv`Ru5h4m0dF9^E0@QJ
z;P$`J)d^m`PY#mF6S@yDX#SKD(jz1$()U1w4T2Jc$>1g5+%Cs6my@HVVFv%Ct0P93
zl*|zs366WKszB81y5E{D1p)_yroc)ZlS^(AAmCKVBTO7?x|!OOP(cRGsiK6cXr_wQ
z)UB%!rlzq6c*Tn|^#EGv$($+O_MmOwdwHZ{dQWy01gMqDcC_L(^a#g27}gsUR$4;i
zmMxMZ@ATm2i)~A?B^=ctMK|M`)%a5cA<oV?WEqrbD407FR-2WoNJ05>&1uA$sf7|w
zN&#BzKXD+T(`8|~k;O@Pr+74?2<9c5QCn0|a$bz8$NY#f4`LIN8mi$q&9yzs?6w^%
z+N#4EU7OfVLd`11kw>14k%C2K(JodpeOcEBG=d?7LK0!Eb(A^EsUSoX(s3I=VsIx>
zuA>K8w6Q*rM>%P6uK}l)<6?mHK7uEl;xvQ<=NHVu!<JO4(81<bzP0{ZCyA8w#*47Y
z2W2BBw&~0fmCW<ZRY-%(kb2S41JhK6YSa~+ZCKf$Gz+&8uvKE33z$ym_fql9gMc1S
z!ATfLSwo3OZKI_!fD)l9PhB}<a5@wyb*^ErAycRNb4JAO6}jgkPfkvV^TEI&9rWmO
z!kqs)DOf+O(`6hbjLFk@Ngd8He|=hH&*17_LC)(tnW+9NcsQ}!W!+Im-#aMr#!Wt^
z8ellGjg_XmQ61S<lKATa3S?W}N(O(L&Jf||xqT*QBd71>Hk$;S8?*INM{oXF!f&Ya
zHT6&pxwCJ<!nJIg9pR%2H^(a+c>I#yT<FbpSje177yl$mmDd4~^wMPR_@(w1c;fvw
z0%u)nDVgtB9)cCGpPsazu^C%Dw<=8brQF7Q?}{%*FYzt7<Au$N)b_v&?TaWQpIvri
zvu`@NC<jl>uWCynuvT8U6ZNXc_T)f(hDpiouPu^^d)_j8%aL>9h#?V8>$e?XEz`9t
zUSxKBs7QA`mnL!FV&lXsY;?yT`+4p85Yn^%{X?DExV0nP0gzqsOcGalbpCLL{Ub+$
z)~~+NE_Ww(Rhtff|NZ=$1sh8VJ3P6*&07;qILmquSTHt5F8|yWd_D8;2z?KQl@td8
zFA~pfrt4oI)%YVHNLT3~Uptm2{{Ls~ec&uRs{77!@4Maey48~Ij9OAl8BlerB^n`{
zhlGg0LR9y(q!uXglPt`b7<iH=li|-M<JeZlMkduw3tED(Err-4l9(r1VaE<m#*UH?
z!NmJU7W+{W?S95AVA+d5X=e#52=JLD*sI6__WP^4?{)V~_j?b2a=PEWRi{p!I(6#L
zty5LE?nf@Sz0bY4*LOGuhQ1k4LG63SS?9%9FfN>#DGxt4wwT|uw!SpxmmwK1?mTd_
zg-@`DtJAtPonzW~uT6)M3v%kAEqPkA-MY_@&x_q4_z$13`oUm}f3S`!i!IdJyvItH
zYoZ4=<fScPyE@wt)>Tg02$;KyPFd0_O^{z{IQ^;>p2hgiq)upwTNMx9k&<e@<#OsT
zk%ofEon*CMV@KQbN~DN87^`G;OifI-x3J{tcr!`1e!aIftxFu5f`k^EzrI#?1Pp|+
zd5&rM(Yp(4edVHT<~Q#S#PBCyJg^$RenHbs{Nz6K&DvN}1KG2&jxR8mIcD%8%P#xD
zh^;i3jCjKF>GR@zW+2(re8&@J?>Wg%BetX3@g+UHN7fd|j(0GyE7?`C*{KV&GlWxf
zr9QOMc)qb>w~odkLq&;k%#Q33&%fF^@(x&}cUkOjwO+FoFp0MTpM(t3YT#{Uo}h;r
z%yw$lvDLN-ZAah8Q2Fdg+c<3X+(a2w$xiSU3I%0Bvk-8AUC>s51X~xDB4*=Js^X&v
zek0G_j#id_O*5H8z&?g`_0Ai;J<w)Q-{in+!P9KjUm0Zu^#>$fjHcWu!21B%H=yEf
zk9{CCWs5c2-siH*?C}fME^zzm$HIx}dRA``VHPZpqb@L9`h<(h>0)-dFWKnT)K|7a
z<jXPuUMoIl!(2qP&PMO%M-29=Z-zQKd19r8DvyB7)kAbu7quLv?&&rE5+IezIBLeY
zK2|9<ERd|LxUGr=e0>q6D*XsS*N^jC*PDLI>LFDM$8Q)Yu2h@Xf!N~xTNcd1NIq^8
zh!RUhhH?*r(HA{}*99_46wAqS$yh7Y==k^J@rE7HCS)qB%CpEE-k2e7T8JME*pQ^_
zmG*)ZJJXF4G8Cfod0Sn~(03|**1^6xxg|zM&O_zz-YeCj;55o>m@-;H%huMjTIhNQ
z+-pt*A)ps5jm~r+LoJ*rqww6rDK3IYAP1=?P}aLxxl@oEqH@7}qI@F5PDnb}l)SZJ
ze8OR<Nrb(H)iyWvg3&H16<xi|YTo@6rtLz&+Zja$M+gewbTG@BL>4#CHFX^+33L1n
z0n~^YI54v;_CRG^*fZ2>*t(n)N#lnBWcw=gu9751B}-v;8x#7U2vD0ZXd$dtG4YwQ
z!*Lq4pY<Oy;i^u<%fYmfGK33g#p_O&sz@_hc3M2Tdnc;haEG2IM90$*JLdOD&9!KP
z<ND@Iv9K-LDJVL^G&o=-N4i;J%pS4*?20Gb%061qii_H?tzXA%1k)8EO%W*~@2@`-
z!;)v0>v(2#_NS8as2EiaC18h3y@kRRRT=&t4ZdO+RFC${6UAWH-l9BF6y^aRmuGlL
zS?SV`G`lWC@w-FTt~MikG|MlfS)JV@q>!NR8uIt?yYN#^3nir^3EqeNEzCpj#i|Q_
z!loeDD94$|T%TkST{&$N!Gn%DZlx_5bj00A6Y5C|TUbws(8c$;i-tHVw7i8}t1O_b
z(5G1E7H{@1YOB_|v@;QYkM9QnpoV~r5yTK2+pCiCastja_WHtJjq_MUaA8MCgrJd4
zr<PlI)NwZ6mG;Vr{v6jQYhVV$93;Uacl5-!HDb#P_j&BuOxYv!SQ1MfX+MI3TzYl!
z6_vH`>h|$w<*umu-2M^IjVCgv!Py0Fralkp)FY!sIQ`hXg-_4ZB5%?BXQhWc=Q-4T
zg>xW+eUbjC(+arf1Fy}s!UoZc_ZEwGB1b9#W@~9a(85%-a4B{EcUO8*>;~>k>B3hZ
zu<NEiR`THzMTrf?Zv3=!;oe`d@}nrt_0YTVsqpU1a-3Be!94Pa83Bn_^ksx{`Nxs)
z{-WW9&N&@HNj=#4@vzTt?1{%$*ufK4tSGp+xwNCF^@i^d;H0PJ3-eKGiksiyIZmVt
zeu*s~-MwjJ_gAaG<dC7E=*>%4IcBSkJis`aI2}JWQ<gJ~UYd{$gj*@Gx4&2~Ryb9)
zzDkaX(c)m7s}E2bQ(wjkeFWoB*jN_(LU1A5vtY&S%v7s$OMT>?HIkjreuvlQ%zdXU
z!tom@#uE&qk<2h#3zvO@U0#c&roP~Ev~&`F0Ql^~d!3v5PF8fN;Poe7RSjOK9oO<j
z%+B9EZ(N6!MD?SOfe<$;E{m*ZCgN7i8!?sQCoC1fM=s2M<JI%=*cG<hQ5M4J4ZDN)
zEyt2vx{c#QPJTNFJp{;XMYlE$cfFJsqr8p7j0x}opO>0qA_}9}ddklK;a?k%Br0Q$
z&f1&XAIUWsg1wa~^=pq%U&z9}(v$H?l#T4x@THg6r?0)!+?zi@-ktDDw%#Gx->&i8
zyU6l`Ke)=m<g8s>yf(Ml_Fiv~GB*0?RAyR{)x*}NUX$}M{Bg@xKbP6nAS}Bv4=Ho<
z?FvQsFJrbic0b8IM$aQ&UFdudL-+)_Z}ojFb;;8`Zd8;reVZ{M)pC5e?}Ik7p+y_Y
zE_TE-xz}#PJbzYX>Y6*0uUD4^j2(TM^LAo51sm3>*EHcg+|wsC#N!I=#G7K3BverK
z|1NsEmyOF}+x8LbrGsCa4*6m?c=vlb_4Cuk?_;*MWqE7D6Bgydw=#bTU)KFp=if11
zPmk0C@54N!WZDl!<HHAdv5L&@wOc5zIg*7*=Jp}~H?H-Hl>1qv`BE+46E2T>a0T<9
zm`+2$nIdS7-$q_6PMy`f)mM#>TtfRHn3;%NA`H=kT*C2u2@8R`ye>~>I2kF;%%wo;
zvHmmSI`b<c0glJ&;G%noOZ7Zlw~>mt!19aQ=psm7Ec?M6!VTF$M4{>7$nPCg$BZQ)
z4LO6xCKNJ1uiVAF;sG4lhGJy{+i5;nCwFQ{P!>}$oKxuUOb%^Fsq~&FOezFQ^s3lu
zE97oBQYqICksKgSn-H=_G^DHr$sld?qLC9y2I#1y5|9Q7)Ldc{^O}=e?Bw7~IcFEB
zYT#VMLLf1mKr3FY@aaC_T62=#C8|+hXGfYiER5A$t{&H<9rXh|M{S+o4$xJg+aYX6
z6q5RkM}~_Hs0EGVS9I*2>zFloKpU$HTl5*o2m!NoU8TN&*}9k4V;p9yvMk-#yAwEN
zplU=}xM)j&LkDY2T}2oTE;;&Mqe-(2$&7_fLN(KlyrZ3r)F#`#A`-G61Oj6=S_mB-
ziMm6UqH4{7nCGW&P%NpI7Dzv1HA~0!fM~`%H4uSF9>kD9!FpHG#-g;m>$T9bYolbb
zT|gOPBBCata<q!38-i9BId+ARLh^Nqs5ksvRU_%1;^K9%GLR5qT>#^3)H3!X6m5_z
z#v!}+wydsC(Wq+3x(R_x6t06K3+IQ$y0a;F5k8=B@z(F+RiQ2OOXfTUDftp~x(?XT
zSI$#ueh7#%ox98HGd&hm(ga>ARF#=SB@4o#1MR8rLA_$uL-cp}?ZJ7k`*q#i(f<tt
zQL?^-E{29Vq+M;HI?bneaAYT+XX`ciS<(-6w&5i3+OmK;mA?n5J#(@9SWAIrR}~6%
zE+J{la!6fSrHExA`h$zXD$yc`YpE<Fm5*pU!;ZwJI>!$@77-QS6u8T^!Lnx|!Ge9k
z`E5i`)?y=NJv5(JK*wI5C5qP7zOc_;K&yQx_{E~b6}XAtS2R&NH0bR2V`Hw~`ACcs
ze$-j9LB=BdA=>GD5T{mKEAYBcXtlM1rp-*ba%i*F|5M+}{cXPJe9|7uKBpOJKlL6g
zwe{yw>K|v$7Ds$!or<=(;PS=us}gJy<Sb_c^?Y52l=}5kY^8m#n(CxQsk1M0eB+6i
zyNU3068V%{&;2mvVBybvJzu`EZnHWUb_>X4IQ5S%9k)wJ$q_J^9kR$w%p}vxe%bR#
zNFc^XH$I#`(l!2b7Qbt%<3?gVWEIc**2&8Q7`pt^<?4!}6*uR0wArociP6qiC94o#
z>(c?2POr@gKKed~Nkiu)dG`P0-s$wY2d%b(2>MB~6IyK*iB#w7Gj=a#t7g9XgLqtW
zS>4|Lf<4`NWVF<)XDxEn>g?HDuU+o!;PXuPt}_z$VkGUAr_FcP_vAUNt=4*OY%R}N
zJ*)fWcu1-L0$VCRaYI-S`64SdWD2vD$Ls~X2zVz{;_{(5#UocAK(hLOWVQ7TAEoiE
zU*Wb)J%(seZhYgsI7g6Gqs%_M2x{|K)QK%YWFPyz`o38?Sf(RO)00&|QGK*gOWP?C
z*?f6p<4OyEaK(z7y0_B9o4;Hv-uV1@GxF$nX%i?Ne*&{LEvjk;f_m|`cNNCLr%4`?
zRpGCz0KK{Z&rix8e}o0rfV=)x)!+9K{zt2+Du`lNpy21`r{-*;Ibw&Fs61c0*o(Mv
z@OFFbsyEXM{G!?IAb2tY5~+S9%l-0|JX8+`JN^SIVxtIov0>S?)v{OpB7^EXrn1bx
zuqVzD%WTa%_g<Q*|8sD0v7L)sUl`~4eHB@pxHYpoRK>|<53ne0WbKtEvvskD9q2$u
zfHVKuZK|2ji+6&0Cw;V${Ij;IL@?Jn#er`zuQGG1J>@^?r2(tAIF)7j&z;;u!iGB2
z3n`+*DT3ecQ&*06l4N&=utAfHFg3qo_J8C>-1f3F@iuJ8ufyMbqt91gc!kych$>g`
zf5>U>&tF<RxqeeL*|tVeAMlOQQ|3@~`^5*CZ(x$jS<&Pjn>;>s{65=f-%m}Gbv=rt
zd8JXRXw=MCKW_bD$%<?8TBAXFXEtX_t2mO9fgT{&P|y+82tSHuYaPK86cnXn)gO<J
z4MU&a2`#`A$bnZTl!Fj&Ew01Dcw8+Vg?v6m!EE(CIRZM|1=JZire8A+aT@ecVHd(}
zXc1|ht-iukdZBMvAbQAxmQPfPTo%i@8^;Ob(F;vDj*)TODC3#3Xv1U{htFW}({VYE
zFvb2y{5t%8I5-6x)Zfb9PP`?>-CC*VCPFz)N<)^a$YjI;OE8XgRjLH<!17OVd42&p
z-V!slu7D~mccbiKV%A(9i~xF2{#oeoE4T+hS2`5zy!l8SxV9KmgUk3u=rgEB7DXgw
z>V%8b1237)N?RGW=zboBL=P(?aN)bNV-0ir0s)a#R<R0}Tuzm)K2{6%N*=5f8nXhU
z!FSD8<vkL*oQN#ejjzfZQNpN)=ns*U@wtkiFt?4E)G}ofe&u7^Li%}@yMYp*t54xV
zR!+w-7Zr$eiv6>myFn`IXvoGmEalkB>)0Wy0-ICNFc7E-&8>t8AGZ4K&J2}p6)J`*
z5u%<2=a8KhjyD9f?mOm*A8apGql4f+cLo%$BR4Mf1gXeQ%Z1rG>9{lUWeGCO=N?W4
zgj12w>OsQrlU${-<umjqgM#=CA(;%|j8$20fe4Q))+S84raW{oo4CF%WZ9LpdKY(l
z{7ng!C8CdAUAO%xKR$G7j(gxY0Ej0D)o*J>aNr_%u1>CsSk4~QS1KnXM>Y7Nz*{-T
zl)bW`)>P1HBe0pITwrdxS~%Uxi?r!-T@r!mqYwkBeVYBT#}cWJ&oH@{^vdW3T5YXZ
zCxU@jA1UU^>gFrUF5*<DUw~QIlb7LjS<s_?AOultBoR1EV2c7d%Egwh$jJag9?nzQ
zH-F6YK+iiRhnqYw*0{*q={M4Gwi*5hEI<1`w*1E4!Icx<Odm7w>u}_Be$4y0aw{aK
zt4<)#wA_Mvhoe?G?Zri3b*WZc@%dk#_BK<uOOGO`WbF$o&r)OGZ)fZI-4}*cB_};y
z!#i~TlQ^C|rw+CA%uZiu&OVBAnpr;XEWgo4P#Lc?JiC!)`!HLx+2hmovCgaD@MRqY
zN`|@+aD2S$+4YVQ?8_Fd{6$Dy&ulGigT{04(|ebH1(U%|{?ejzyYe_IK&!1(t|0rd
z;j2K|7DrV}_&1#dqJW~t2`=Reg{?OzMAqhtzgfG1&qaTGl%4H+a=YMFcJ%5qL)KI_
z37_I)_VsH?wvct|l)}wSxt*CWW3nm**|T+4&%7E(o1gR^S6fjx9mJhB;_KIx#wQ_%
zgO$q)J9xUxI+L&CDRy&=)Oxa3%OARt-sx)=mWA@V<owE$j!nXEg7j0CwVs<sA#>}t
zG|#w>LrU#Ch{bBFtv*Zr`0jhlLS}1RZKcjeE)Fit7!L-2Q8QS1Vmh3<_tJVhH85#_
z%^de9J?OO1zr=3cfAf25adlIpVrA*|XDpAqhok+7Vab!5_Cq3XM%ldT`4OM9ZTLi7
zA_Q|t$^P~?^A)HDLQpyBSeQE8>x~U|b#RE}Ti!nHm{W-#m5f<)WJG1G(QB%6NLK%Y
zJBYimN3-&1@$lYxkuWhZ7#jca{LKFdtMj*P)I#>q#i}m;iT{#~E@%Vv`+hl<Mazj(
z%<a8de(0r(+<5*6RHBW7r{*N1#0>+*_zJVNjoE6S4|`TLymS8;$sV$ix?4SABXIE!
zE<+Wo%l;b1`Tf>8bUTlU{Iv8_!OJO+GcXV85pU{Z``nKz>?Zoc<D?#L#B*$udig%8
zoC4@7^*#j(7LW**6%v1od|=2%%qSS`BC+f`7xe*pcZkU<c!NhB+{41R(wYq~T$~>T
zC!h;n4%OQp=tCRV*^}9fh#u_xZR7w_1&_{MFO<SKxtR0UDGQCG7c)q)V7KJ!ljNjr
zKRaWp)SD34{t{k10HUnl^4N>hIQ+UgVr)XD-B~eS@%zG5@eQd6G5x1x0`k5e5hb(N
zWw2x@u2|UX_2P8BSiXg^#-!L);KX1oBrQaa-H=`GB-+sf9<I_2@=D+?gc833xKUuU
z3TojgGQ{-+nF>|GnxUw`C+e<u$NOd>#nim-RvA`XQAO6+Dn{6m1&J@jB4{I79@*?n
zw}}lnb53JCgmGy61qLVzUFLXq&8n6B7No(@V|NeI1k}k-5L}28|Cp_KgyBw${HUCY
zL?!8h>pIN$T)Q~}0pgS~I70yfotv2;fO(~A%{^jY1y^Ca-dv<3du;B&VC`jy2sIa+
z;(5dFCm>VG0RajeG8dhDt#k@zy&z`G7VVIl0%XI1Y&1a__3m!&EmcUW%8dATK_l)R
zfOZ~54}`VECb8Oqaw|%58jlk?1sCe^IHefeq9##YyQ&lpoj6F%&JP}yIu5W5vPtuz
zBeNAw!I>8&5M<#+^*PShd9b-i5v$His8Gx)tS@+!yUzz`POyC}_d8{$+kgjigN;Ch
zi^@TcD4x3@fGE@@Ir+NK!4dg;(F4s>@#gI$A8R^6q-Km6k-J}V<=5-dqTA{6LaS12
zh{+OwW{s{9=vYHH<u=+~BEzkJ=vfC=-#QpDOR{B6D9nuV3Jr59u`sBgb<M$$qtNBi
zbEvE$RrnxblBm-{VNDTUPK1kTSR$A~fDY=55bcnboGi;`yHw0bnJzAaSI#xfE%~j3
z`by6|(L$1WOYEJUF-uXOQU0h)C?&J6VsxtemYdY5;_wx&S*6yEzJ>H0=bWu<!R3YO
ziAxx-TfA_OIjX081^iL%G#Q4=monaJGefja%sPb|+A(~<MYZ5lg?Z1+f=yFm^m*$@
z>|RMglsqLyQx27jde<r%1e4*V#gaNJCb3!u916ima&;#QtJ|RP7?N2*77G3bK*)T6
z*quWb)9PV|87+x87<<&e@?ewQx_L%6g0bw`6=GuJV%DV8sUOQABw0o(#@;l{t6$}k
zMoVSO&QL~^H`r{Ln=b4t=Ph{=_k&OcmT>p>hYPu0VU4)Y6|H<@9`}VsJO9IlkVjk4
zco?qT66FeEZiGSa?MtqHk1PFR{?)w17CU`yjNbpE;`2YYP%OWlF@5Jvr4PU7yrSe&
z<7Id>#7ZrH#+MK%#8l9f&TDMheKeaNe~E_Pj_1CTQGits-{vIw+&Sur{ka!1f{)kd
z&s$ir*Y?<^pq;MuBD>NvlFzY|y5Qw#@RKBgALba#MRE)S_cSRqc7?_%y7`T?TUXq*
zlM};|F6(}0^B}MvIj84qjE*~dY%gnb%#&4?)W;8fxET53O}_cF%>&fk0T5>3E*i|%
zrI)>%)~W5O0Cwb>_9n+&s{7yV^>K%!?a#i5uAvB%4QE$}EVz%<i?ky681_Kg7b+J0
z!Jqd=R&IaG{FffNl_&Z&E<o=Cy{I^J6}WWT<xT^r3RCP2#ntsi_Ywov-?%Va8+(6d
zp3s==qt|1jl{_0h^tpWBRUnzjGT!E<)W3@{zHqU0IRNGezl&l;xkbROro~<Iq`Kwh
zs201O+<hSsdhq!bv9KpU_S(>jn{x5|FK@(Xf60OZ)={>G#CARM+WsSE*nFv6dWLN0
zcMh1{Mk~-lzJ%%v0aZp7Qau9Pi+C0(QP5-&SAR9#p}B(YM)3SNhx~dm{oq^omW{A#
z>nGWcQnbvjK2x)a+D-I;gFqec&pcS#`<^h@y1iB(UwNBvz~ocDmOn6mM|_kY_2T0A
zc?{X5SUS@)bhA8r5qV>okj})Jy&?(WmLD<u=o4Vdl_-2C<_Z$^(dBClH9d9>MLr1T
zEDt|ZxAW`G%(eEOmlSbMq_8K5l{+WkY(x`8_;bs+IotRpGI1=CG~dVl>(k3z{WR;L
zc|vpTe9uisvsD;!;gccz3@!KQ%dnw`>HnKNiWFUDtM(?>v%}G=OA!}&k7rJMll85S
z3LdpI-QZtlWw5M1@?5UIZ*|;8mJkH;fiMC^8<E|<G9P*2wsm`YWCcA*l-#~?Y3#1T
zCKnzu>xvOvp*v-pz$+;!q;9P}Gr#WnHj<9V*;;sBl-X1HN?wFpqeqC{;rzWTSp##6
z&4>Riw5OADb|4Ra2jp(31+h_t<-&r^Ml$DSK<%WfAU$MmA(C;)@sTC|Ip_orAa`F#
z1nt~Hm#mjkGj$QsqzuyF_F<$(vA`m~1y4`na0onOpP_(OXI?K1bz(0&hBpfj2ashG
zxBM-B7WmRcEWn?_((7D8K0R1dpYU2MyF#s!S05NC&9@Y~4KfRRc_0<pG*ziTly*BW
z*LsAIcrzX4g_hm}Cl?oue};q_<bdx`<$d)Qc8hHJTFg}p%p-*^AuBmyg5EF4Cs@r&
zup!G^(ie~BB7p4+ZZkCe5yDz-u3h04xVJeHGq4*dqNI~`-us@ISDp?jcbiZtjH7$~
zCbGY)I7t^#XC&yD4b)SFyTzeyFJ4D3w^=<)we#F_5rlZ<Qs+rJEsvvEb&sGr?xKq-
zkm2%<%K%smE}9iQlZs$UZY%h%rwm!w+3y}}zMGZ)j<je8-D-6sHAeA#EKj+%!6<Ku
z2%)NN9exw!fKgk?nju35e*NJfoVyfCRxr(v)Yj#8$`>o@SwWR;5+0tiCCq=YvKE}h
z?_qR34)ib(Aj*h*niTKGeL|5MdXl(l<9KKSD_hEHj@c+%7J+(;d@63Dh+ZzOY9W#!
zt&k$$C}o|p(U|sGmyU?6<}fQtLHC6)Z3`lxWyKQMCl*1N3c4)4RM75X2i+wR(mb;H
z{5V^ZZh1pE*-ayHjk$5SNs)2#c5xEPfNQ9$6q8mWX}GnDAuTt0YKjBwj7Kb_Df@KB
ziYDQfw@Xzq*x{BRA+_0gLPFK4xkNRO&Z@NoGoIQNL&xly^JbR?EZml2^->CIq-49e
z+gj3hf=hLiSH~aF*;A%l@|I}MzGk`4!a@M;)G%Un-K(g9(~`Ve4x^Fjc<X<m^BcSK
z{9?3ohd28|saLB7A-i|U#x|sF!C`)#m>i1Gg5csrJtcy>)Js<Nz>qfFM=+6Q!1jkt
z9iXLe8NGNc8x#N>AH$2iWuN!PPGq|T<B(O6dBjp8tW4S=-W#`{aqQ5czxXFvAXY3}
z-FF8^Q1jB_P<XFBtQ1|~iD{gsoKKBC(fnU6Jn%yCv@pS5qP_S>eZb>p>`gv|1NF{$
zr&f-)FJyk{MNa@^%{MlR(Z59j`j=HD_cIs7pjh%nK0fle{X97t1Z|0PHw?pSMn%BU
z1p@ewr|?8Rj$wbdSh_Ul+&w+!%)do7T9n%V%Qg){F!9&lWHU2o(68j<D+{L<**hBR
z&~=YLWt}gw;_O98`N$wCLg&@kYA;PY)=F(wA^pG?&zOT?1n%Yj@47eu%E?RtyL2Yd
zk5gRtE!)wPm#;<R@OQtHlL*+?9$vI|g9+FN#)_OV&6tj4$_~F?Z;TIsg6g_(U#M$+
zG(cM{zDl#;<x<G4eqfRhSA2opZep_deb)RQ-(N_jou{+Wm9Tmb%g=r}nyp#=2Pykm
zZ9j+UU2oYJ@BLN2c0t4&_D*XNAvH2@=Y?Y7;;i?EfLQMcvz~tZr&g_Oo2|fm1zvgy
zkDTS1Dh%OK*%Nw2R0$1)8(&<B%bqe5i<77K#t3iwzKvtHDw81^metgR-E!ICY~-8%
zyvak+!i_o5;`{NMTgF;mdBgWI-mo12aFxOWIpFpAm!{2`{t>*I+|YDK+C6-R;S`C4
zxTGtR4_;i>r#g-|Qdzb?bTtw0;eeX|>9QFcT&_g_hwO9y->=SQ-;6u^H#(3~2YqMu
z+tXkU9*YWe-hpkr5}TA7?breAY;<xpPCAD#zK!~T_#$y?4SKg#n*in?zg(R-vLd`l
zFyf}|l^-5BHv?r8VR*OolKL-N$HO60UU=unK66eH-V{Y9co2M@4s9cS%c5@I%BG>O
zH78*F?r64}qeraQj@juPL(cr$e94}Xb_Pau9nktK9kKdIvwMBa60Uv_yIm1@YbPch
z<s@>riORI0j`czWJBBBM5&;_ijcx4=xyH)#tLe+zDH`qM9tzg}PxEJ#IaRD1f88=1
z^PJz3edE$q^ZU1!!HMz7NoGrP`~DgirzmzL`>tZ7Vk<eL$}+bve;hl$oNQhkLrU%0
zp_~x4piYLh(noy13x%g;^1?3miM@zDXJ+mYsp{=_2-%8q#uk~1S57WtMNud6arg>C
z#V6Jq+#9xr$ryti-8bN@qnnsG)x1&p27s#dx@b`3VwaY_(9~OyloAz9h{;NnN{n<b
zK0}xjLC()uhYz|B0#<~?&xg-(UE&w`Rj^t#t>e1Bim|+;fL)priosn;<O$04mN5D7
zrdk%7%3k3kvfsrSo4yN=S+_YOwKbJ~ad!^$-8tY63iG2rs<8$CvgTulTyG+0hsZ%%
z1lH{Q5F~r=Rbh6Op`ey|%vL9oL4ZjCNz_OO#&l&793=^|i0g5uB29X?HGU^2)|NxU
z(rE~?Cac-8Sa~u<W(mLhl?jN6JeI^3a&Mi5Dy^+C8|F#Ed0&Jvm1|6hOVUCVfo@XR
zx~~(z*U+bW%mRTJ<bw-{=S&0pe?4=GkszjrQ}>QgB<yq_5?mo&QYr~Nw?^e=_B(;^
zI><y8P;iX%pafPnC&By<_w^5Et`RD&Z${a{6>AUp+1B<zM^6@3)%hGr?J{Mh)1}ff
z*W6~)jUW5tVQaVhE=Auv9e(~46DAr`N5UwFbJgQyy~5SJkC-ncW=#8|QWkGwRm@t*
z5S0!Vqm)&_Zf-pECs5`_EMsV}!zi+W5JbW86J|aR&KvS4@Z7vuaDLG6&_v#7n<H6b
zR@JS5P@%_XYlT}<BR&}OrR2I<s%W=T_M)HT2-`3_3d~f{!=hR`OD(Jo_N-Q`KjQEr
zOB^ra><`O4WDZH?2N}<hb#2>TS3awUn2S}Zn}xbhd27`@cJb4Dp=(%hN`kK|^SUeh
zUXOH%h3$cmPQE79a8{1K5NZtsaA#$7GYYeK`cT;Qo0x&F360u~w-IYEJ;l4EH5F5U
zLpHK89V2^Pa{?mdk1sB3WRqtaKZVOe+^trIOU)Y(to+GZXvGpw<bAJ^E<e`GP14ZD
zNOr_7WOn9TSU{Z*dLMc4-fo02!HhxSi&DPucewnM%<f$O5o-xC2%J6Ec$`_6j`^!?
zE<}a5bJo$Pb+}Y`yvXNZ!2ooW34U!#WF+Y9O#~glM()%&p!x5tgwD59I>Bxz!pM7R
zuE(l`C*pkq6(U?R^<Rs#m%|vm<K?2xTbCx80SGCSO@lasDl9qm8eIF;e`}coI~274
z1Ve$<)_nh$IX`vdfQCT<4sI6PLIUYQ=Y7v?{coB3c;~`A$D~QCoaGCiqnh{R%jrm_
z53fm(f#9Gh;LaXcEthHfO}!afRI<o}JzFkB!-1?dwcHm7waLStY2hT9z3_vvTxRQm
zr)~l>47`P@zJs^t#qq;?_PW=mQt-<R)wJ6B@Hf>U$+Z9M)hwl6&d#Q<<@bC(8_f-~
z)kU-QFD~Ro$-igzH=uJLc_SxH-#~wU(_-qi99X`N;??Mb-#Fm+E?iuHa-cqZU_<&_
zDZ#JhdvU^x)2#$NGh+YY<-z)!dhW%6%tXq`OQ(ZM#q(~fxhFSjs;;fuc*&Gm1{d(;
zag#90o<-R*<n;Qb&sFMrY!uhNVA=ffn$PxJp4rK-B-@R6{eg0d-2KO%^yZ+Y@a&=e
z-d{=qw&QB+t5BR0A=&V<caO!T_U!VX@ayHHwGgzTUEBl7JrkiZ|L^*z)(!1EHty!W
zd37yTB>SaN=LmVs*FLnWcUz~9*rErKyIZd0dyklP+7dm_i>vn3RMCi4>w7eS;(0r+
zi0#i`;4oWj*81&QJUgRaekiv<h!y-!{$RSW|MqGdVt<;AXaDs_lX6v)qcZTSr|&|W
zJ~EVcFRvAMQT^`WFYHvYk=dAk!;;Uw<sz+n2e<2OgX-+lCSmNydWYp|3^_KrAa`~w
z_Iuv^?~;dSp+9;BHR+n!wAC%L>36vaONlC-ZG1LT1zj6|l}F@F42h2ONLu@!kzc(V
z$y(=z&?XV)ocCr7E!{t}?^C5XIdhzsjGdJuD~dlD^2vpqTut&Q>x|r3Gx~^elBpZ-
zwp!;M^Xp=fhu>tPpJeNp<Zk5qc6_AuDeyND^wMRsNbL-nY@~h3O75il6IU*AwJiL8
zc%>W(ey!FlzI(tV=s@7zni-vU)s}Mm!CJq-Enz`Nrg%@{*=lNl1U5?K_7#=GMNY_$
z5RSPpw1S5WMkq-N-LRlTf4Y4+IT4(Dl_3~`WV<#>xSRqNoQT)Wi<fm@RQ|AuN0#}@
zx40GC&ppv>5!~2LvK;7w)=Fz3P0D4-l6o<Ht2qlfmnqW#D~^uKI%B!ijK<JFGij;3
zx8hjWy`#%qWrWU0ro!}rCm1^ToQG)C;}$}{#cgb7Zf*7N?rzoGD!VZ=|9O;@jdmhs
zD_%D*%$?yW`AO;-+OYIrMr_C$nPkaZRs`<uAv;?%u;)TZsHYg!F7!g{vl&ZbYvhql
z56AfcAz4+jAu}%`I2W@S&;2~AFNy>DtWpx?&Tt)ygO^(&xDGSrz`@pW33xp}9HZX!
z254BzKonuVbj)33scL2ADG>o~+KR_@ALWJFh$*=R*y<<VL5SSaq)nvQ`BD_qOv>cw
z)#eIwI}@RY^#H#iAw&(ep)Rso%v@Ac$lz0?ti%a`--d3fBQlk-1dj)%f$=u#1CbhO
zkyqu=A7CpGk9!ooa*OYp1Si}d;V#J@)uqF)g1Y3Ii=H`7DJ_W}<Qq1_`6*SDQR_4m
zBR&c#AB{}}u@_P271SW9b3$kkP8$^<St-eg=*J)-3rS5*NI{TAtQZlrNm$t&1bJ!m
z{*<V8qwe9`gLtKIsf{McZwVQDWkOdY`!qHd-Ib#RDFW{4t}1Cu4!`O)1Bo7?e8YmT
zcy-h7)l1h+q~e5JU70jB;mqrqwmd&%Leq0P1*2&#T89<EC<cCWT!6{#qI;DNU9;?Z
z9#4_P7nP%thqUycB=#}1x)728*<rbzYd37m-9;N9>a|xPVzBF~Lp~nu3_7-ABF)a1
zpXMuLd~jwh|K-59V01<>@Hvi4e)0fWx-d(H*kRL2c+~D5IYaIO!wX~oZpkA)voqf6
zr#Y`C+*i-e*Ezr`#?Gm2$1<|!0Am{ZMZ!B>SSAj8I}>a@uSQFg3|l5g&%`h~<8@Lj
z{37}Sex2?Ov-LHdsY=X5wd*wxOZji)kC;EtI1;2in+Vw?T#&a_`}S%?gv?MLd9&4T
zT%6Cb6JtF4?}>E0joQQC$1`_HxWK=L&0Fua1>*?JF8C~@h3Qb*tDLdgI(fJo*6;2w
zCRB!TOMTWBP%#F6uDF?}$FnG47-&7QJjrTnu*?7Rn0>?VsVNdmbot4RTHP&Q7-A{S
zZ`@|(Q~LuiS9<$6wsBmFN?U7RVA5;(LU;WIFOl}M45pIG`zP)QZY;BE8%>Dg@%@#8
z%3@cYK>|L=Q`YaNf8DsqVXk3pz2IWrY=ZjxH<f}CS-aOt|2oDIhks(II_&KyIo|1y
z8~Oa{&+f^dn$@$6oGjC9pW5%&uRBe%7p7ycpacGC-WS_o@o=mt-~6#_7R)K=PByVV
zL$S90%57!y|Kd2|<8QIfN@q_ng!hr;^Do;sqMH5tly4ogRnZ0ki@TRI^|i6jLgP{=
zUa3#u`A_^=ulVXM=s!2t0)*TJ#_swwl2cBdzyAJgUp#gT%7?JGvC<UabET1%wq>?r
z$i=PNan?Y~jly)=Kf}of?=W}cX`@_+fNmXJz2wQHFmDVrSZzIcCMyCA!X?*O=q>5a
zeVt@CFgN)!xZU-H&mTU6Sc|_<H}?qHee1D|_(Q<I|Iroy?4!&#KbY6+zogTt$(z44
z*ERxw?VVZfg_%~#j?86@hIv2vg+1)h+Ru#0hixQ$@zT_%I?*ZncRYb)FQJ+L?R7<y
zT)A)^s}9mx>nAd7;%mx}BJv>Mb+QYKk^Kwg@Ho{v_4g>@?09f=XXAGA2m8GT==dOS
zPZ8m8Y6hJLXzJ?96%c`dXg|^;{(Ll2V;|W-1oe^j$J|f<8i$|%1)1y$6(jC^={2sY
zjhi<q!XA!hxGz=ja^syVGFwBE;FATty&iNo%m#ZLy&WSJ^@w(RNQ&NM)5kS)Uiq;z
z6Z8Nte%P`bFN$^0qrQvD$w&R)Pe~`O7E1&u#qS4Zx!y(40Yv%kw2&1j`);3OhG>ma
zlrHeIsWGz2!ynKh!mV+oF$VR$963PnFL)W}2^xs;(>p{NLc81QLy6`h1Z;8S+^((c
zK@eV8K`a)J_%mcgqY2OXZ?fh(ev+r_@Gyeu={Ly(63rP50x4w3lh0Oxb5(YjwoYrX
z3o*cRo!cT<MZN1S<uM?5x!H)8JEYje0$uanh$<QVET9H;eeJgSlKMpQT|lDzUi0!k
zu4}sz@#^YMX9L#p8wi;yC{<%oimjrXilfahf|qY-aGZw@v6r+(J{r7YQc9+8*^sa3
zkHdb($ey<2V-25%raVqDMmSF9-66xw)XY{a@+xGPTj=3CNqO@7>6omG9fl*Io{xG3
z2($qtXb|dhd`_rJw&)x!e7q076zduN2`_ZHO<K6(30oCMCaz8dBO!B2YflPhp)KLH
z2|U*Pdf<7Bsum+Y^nwfg)3y)6hk}Jzi`==?Vps-5SjJIzTn51_Az0$)MHr*YflH=M
z-GVhe+08Mk)<LubmjV?y*?p73WHe1R05IBF5hHa?KzzHvD=GSi#9gse57?bS<lJYh
z+tkT|b_U0Q(mQMWFoMps;jk5p-0GgB9VB{(K%}0PcW(V*9SMW9cDIoQ(hC)R6G!lP
zv@BFQ95CY?4oC{<OJodEj)E0xnVPRB5<40Y6A#h`$4w*=rnzd-#8<VULhpP-GJxbf
z3A^nyUfz^OMp1P6ZztOB;|+um<@H)2&U52!QBgGc5g<!K$v`p!rXI|^^gr$#LJ$-+
ziZnJ3zG=%uic>dW`U0P-kR}RvwN*XD0#HMMg93~IR663iiGa<WYQVHraYX{?3Ba0}
zoCAR4F6RPWj?S1I_s(dx%2vG0DMQ&EoOb3sP9}%M6H>m|2}#pjS5uB;M~Ot|HAgo5
z=pB%_X}Hl0qB4n(@QLr>DlQ4UB(vOS6KU#$Eh4=Pb>zB$OdjPP_!|tJNJx7_YA13g
z{B@JPAEe#=cs7LA-;I>H2SF0R9!R%f_7O$gh%^v3Agl#(j|pdy7qO0}WZBt@$EiUf
zPmvPwd3FK8ZM9SiBZtJ{;X5W2JQl7a$^bxT$IQ1nJSb`}w~MCER6DX5#j;-73-D_h
zRvnl-5-BR3I%-8H)SQj-rRl~-MzXB#OdPX`RtF0=XZIW=lTU>j-Plb$F*eL4lB0Hh
zYk*h;U!dgRRcl#|!8MYtdC)sUwljJwHj(HW8=it<nN@1q#-R#G^<`V(1;rD_$+0bx
z5a)nbOW%ZT9-+G&&IwRp1<0$exF>Ig?srqY`%A#KjP=yiWfbJtMk0jQWq24)GB1WX
zed<s!Pf7aNPJ-y;L&_(?5(l5qMeLh#(?M|_2EZC)oJ(CMR#p(j#fBZj6uujH1?&wf
zJ%%nRDW+Ed-_Uhi0RC<r(nCDLL)G2Kdly?F``^e?kQQeXS?EJevXN9(-gW8p!1eOP
ziyQ(8@8p1egizhL#Oz^qcDQrP)<rJDdp&B#dF7&M5w|mo9+pl+gn<wB*remJ!PjFI
zI8GwXA}~_O85?B{IzPHTzCy{G**p&+yH2F~f`QD7pk(<%rgzqKHZKPKAtsB`@<P+F
zzBh|JPBg|ZHIj`1S=*DHm<Z!25}}CcN}afCFScq|kVh4BAT*#LK}A>hE|2HR1?(aY
z2QqL^ok>M1;xdgZrQn<&Pu@&)sEkO$=uzmo6P*D=Rmef~;xZ5<nZS8*Ao{9&9B`bN
z$`f5;I23rE{_(LMluuNabAOKACmwH$UjhP{|BM5*tie=}@|r|$$s-HUp=9cS)t!Qd
z0SUQ|epI-fDgvegYU39&M}_G^%_kS4VnwmC9pi$VqCqvdSK*1O&vnsfxhpajBJat?
zE6Q3Zr`~El#F2%fJ3ea#0iXkv$yHIyg9IxWtEa-P)Z_SW511tp@q=S;P#(YGn6jgg
zKG0z|rSIlK2?&(0AV&m>V0iGGq&JccU-`GZ+KtR1Wf0Q2*g$Yxt9TSg0+h4L(Fw77
zs+SrX#JR^@v9?5ZJ@yJ%&;^(%Tj<=^aCWmVbkJo8h?-|ZuGu`V=u$&~5EBYNB1=Xf
z1@_YRX3O|v)o&6$-%GY@v=bUM{^z(RoPdj0Gp`=5o)4vv!d8e?E>$eV0U5WzBC}6D
zp|;?6bOzQ7e5M_P_S0`EYa1U(R8OEab}%Z9IewnA)zRT$K1SSn1pmt=v02*=2kO*C
z#Td&Ud+mvZoJiF`M&Y|dlrM|3lk>Itw5cXiOCHq7VA7V(yM@zdQZd*OW?~~e6XvaX
zVdkotO<x`ream{ytfJfTmif5_Utij{n%i&lMlV@W4(l_Ba~Lgt<HxJiKxUoTC0nrY
zQ+U5$Sbp@wmbc%u$vC&eD^~wBW>EPHmgUb?dyKMc+`}*onRl3O_w9Av(%y`DuIs`4
z?lq%iB~P#3L^7`{=sG*gkY+e2bxtL(Fkuxvk-3%H`41wI-T2Z>t{sf(9aZ<j^gTZs
z;>R62pQ+7c`6oeBmvZe^)6BHKQkXSf%sKysbsj|;0AU3Jk}dMapVU^gUV|S?fytD{
zo+2+kfIQ#Lg4f<O71%f1w-uwxa<gr|LmMcH4`jx>dBI*!4V*gT2pbGV{m<=|cV9&}
z`8Qa|x$}0}Zk;llE2or`_pOnF5>ei)-XU*tKlSn{_L`Mh`0k}e{?#8$OCgbDR*{Z;
zxn3@Q@EzI2<=<JLm*(5{t2bH0;jpXb?3#(6$fmtK1Hc`8uLUoKBS3FTLy?>=2;?~<
zc8<jkFX0A3@$@?Tg0+`2RtAbvRU#JGMlE>KSk`vCH45Le|8VK&H?q!&<!k)tDunyu
zK`dvoGJNniDPs<g{pvSrlYUT|gcl2v5AGbZ%4;VitBy}?W#h~N>_DF0H$HE<UYiT5
zCEcy9b{V~t&uSl^AKzE!BNv&4C5Bn6|9u9c!BG6lHNj5)t=zKzc)l;6xmxO~2ToTB
zm%JwPCpYl&AC^y%=Hh#qZ#u(hsYa4hek45OkoR#U+xyMi7{75c6bhMaJPcN2Bnj{N
z*;7~8N%hZReAUWZe@h$(!d&*%Uo5Dm%u28*q*r#&1ug#$+P$_J>uWQ`7#&~QF|LeJ
zW4jzAs%7+ubv6R(*sU`A7CqKy_oS~d<h;?gEDL|?Gkhe5uDNMztir414S<tf`Hr-I
z*HM;RvL5??D$(+N(=lKURw1qy;qY{LtQuC+N*nK*W(2>?`sXDB(yM~&OiGT2>z$3Y
z$MfQhsuGoiqI2zcl_CGuYMc-?`gEQ!Z*JWclVv$(Qv20%jVDgCe;~Wx90Zo35UQ19
zjlV(JcHygP8Up6B?rM*hF_nbb{d(t#JG@>FG`*9!urr<CGRE1NVk<UV>iVdom3Tg=
zM0)|kc8tvAJTh+KTNH_`(W8&~bWo8`)I1EhNW^sku0DFw#b<h;2hO|$yI}Z$;NmT5
zJih5awbn)=M5e`8VS{c|i3Sro?0IFClo77ZMpHo+JY?Or$m5Z3NVo~3)-NfuD=FVT
z_O^sF>m(9%<&&5xLb~#8Zjhy(v%^4{H!%tTX?|y@+e8?W8$B32>QH;fSWdCp0dX#`
zICzsG%pgxWa``CUhUFd)G2)frhK&|P%FBtcG}QF0C!JYhyNs4WHB}9AksDk1W^uW_
zJTfC73lnnHk6YEmXe^d(L>=%^si6j&=1(&;?LPXS7T*N=Oa}TY{6ZIFU`#KNDfMoQ
zs2s0Jm<VNu3IUNcw7Rt{7P|&cZeJ9o*JS{7QZn@ws%Xq{Melp@?(VsUbVQNXGv`K7
zSx%%*HzH|l2TzusW32BsL)g(CrtG{JDI0}cHKQ+tX~vDz9uWodpa)SGXgifL!CkUM
za5bMC9iH%1tunrj>tZtvTQ!=fcD-tsRmp;Zq~E8cNI?>qhZTuLw`xwTZRQ98*7(&6
z?KD!};=6ooAXOxlpVRUKds`@%idj{vkhu4Nasw4Y_pv1If^Kb&9%mumx%?2h>_$nf
z#KHThSG(JH!{S{$(E!KlRt_gm1r6Qnb@gd``GrI&<SyXSD#b3LRlS(x7%e5)N@Rh;
zj39lw5S=_Jv#4x*QM!ojb7@mVp72nj>=wnj5;g8S;EL=jN<8}UWmL6pZ3`NqYu3&$
zOwc23>Nhhj7Mi^iPL8{v2wnH2b@;5e6%RRr2Y?!U0^O?=g4wTb&DNQPXl%MfIN;j4
z+K$`x%ba&uE3%DuCO%KFVT^#fea_7hKj?ir6&np%@6++=asda`^Gx~7U*-CK#~^J6
zN`?!Y`HoaOU4jTv7O;`oUEG`$D?iDy?a^8G-DTdLxC1=wZGANM*);L_P++!tp=nm@
z8D=Y=l0x2Lz~7ynzU<Apf4uxSB0Q3!;A;Bsk-cwp$2uEtAcJr1GJFchi32G9E*9Qy
z=9LEguED0v`9E8*$xmm2!D8v`Kb%+RNEj;2HOLE$zOWa{`z|Wihfv5v`G;yP>%2t~
zyRa1X;pHWFItfGt5t8nO-5nfeVm;{1siUV4V5eN}M0?{)j{R?Y$}$=-;)eaG;_~ww
zm)dInrr1qI%;JXMliPVOXEdo~JFFQ;7GkqII0$nFis<Lea#fzGc_`VAl5H)bWbFVW
z*<$1Q14W#Fnfj)!b&Q4^<8t1H%+~VY!VsDxvC*l+V|i<qC%_l}DVua|Pm`WHFLB~d
zo4;pmp%{<V<Ll$0So_IR#p7+1Z?N6?ot&>TPx7ILn+rZY2|POH%kz(VYkk?uCia*+
z{+}66zLiOHNP>eR{Ni{$O#FmR4^<BP50rWDm8w+XW2q)>$|<9Bk^4}PSm_&@U&uHc
z_d-Xkbf(Hins48JTIkQdSmWXH>O~9CWfGY0VHDv@|B|QH{V3sguE>4V3?co%6F7&p
z?5PZ$6}=q?h{OB_#RP|gds8h*W8JGT=x8qNM!O@kr9*5<UbvX4{s++HDjok5HxJWA
z@GY8Oxu!mS@*fv=@@KDbmdsX+hV$zaADZJ;zdz$8$UpdT^8dR3#Jm7iOS>&Y?W34e
zNBOo-K&*Xt+En99w;6SDHXbt5xR<$uuk)eP<9z(apUCTb?|MgwRs8s;n5X~Lbqu%$
zmuqRCzA2xad6uE@*LjOHR#F#LqDz8kbap)h?`NQ(M_ib`xt`m<u1R<C;Fb{rB#%xD
zjqk6uFjCE)URbpwdn`VUTlo35#sZW3yyJ`6+FpK~fx|Gxs+g`d$^iH#I%ACD2ruVl
z7RiG|(OTZLXOBg!x#r@kt<2bD{sd=&GM}NBHP+dF-WsO42FH;7j&Qv_o2^`u)y{l0
z8Ub)#%TBzjwA#~IHW~En{7UAUF}H^$%BA5h{|*|^#tmqrxm?<e9kPsb{<ZBeELk!6
znTuMvKaY%@D4aE!LBZ6Y%kH=$$M{{ytIVYw?0ofRf17j<Q#(J?s|2ytY@zoEH9Tk|
zg!D*jpg??zC@poTItWT7tb2qBo2^`dn9Fjn^UGl5<QV`fTf=?ieTtN0_A@pEcY{Oh
zfxEuyuE`Ef4NMJZ=ARYYJH}X9vxc>*EQXl)B>6rnLXFR5>H)l;uHyl+Hm8Q-_4Y70
zDt_z-J($r*cY73Cd=fY-Or1#Nt{L8P@2%aiK6gJyvyec0GagAiW6p(eE~*bkGT#fU
z(pn|2NBp`-1F}w4aU63n0bd|zNIB{op@Fs8sDjC!75lEUg&4_M2%#6Uo5ODg@SzH;
z2jxdUB{30HzX0aVDZt29i6r&W7qEjUrP0NRcu43#*DkQmUP~fd<F6n9Z{KhL9T^1<
ztmszIix!BGuUI)VYu0Lkq_%r4GnDoe6o?%ruhV>zda1$~PIrNaL+IcMT|}Sz0m4ch
zHt4nzm41tFQEn*mEx28s9zyGtk;)h#e@>bHyZgC_&C~=<(&31})WnFFE5@riPoB(m
zgb}yFkR)>|wWwRg?}7wJA?dX_?joX$eO?)ZF)_vRXtd0Hsu0Dps0KpIiU(<tnq9HC
zNQwo1SqP1LbqBF2Nedl-lqsfBwvURKju>m{mb*8DMiNbA&U>M7Mwkt{NtrE1=}w-$
z00$3~tY+pQbTAe03QBUsYpnOUy7w(XJ3ATLClI@ov3eGfAVM!J71??s=%Pv4m2*_#
zN)$6XxB*ZJ=0(<vmf}QQS35CRsaU1f1X}QR#g>z7JpC!ntQ+3<&cYAjr9F@mt}o$p
zRcUZ<ro2^^`>sH!^6zMe!BIwq2eCmRsGQY67sv|h5@1tIXo);i`8xZiNH8a6e+Xit
zk_DujmK;df?J%RS7=0G9uqT^~-a!`#ndJ9#<HvcAyfcxW$|o)%BbSn6Ivd*<u~$6*
zhMC-sd9#xrtdDfwn3ztm{+ds%e+-G<k$FB6i9}ad&1+DyG5q?h!C9mp>$FEc!srco
zf@K@p(fR5s;4`DkdVg&)ta(l_xVqqV;>SvRn$pH>Rfq~`Fw|Zu=BM7AuRmTsNl%X1
zIzpVfcUC)`x3c%_Syu@~a57t^*SzzxfIaGp;^-75`6j=X-?{8rXqn6WpZN^4wa7fr
zYrSD{ZR`AOB77DV{6FW7xV1k)y!-xPGcoLUt%u4=zUV^|z-^`V@_=QvHE_U(My-Q@
zDz+*@4s}UyPRUFJ8o!IGFf4g(j$OHDmVJBrM|h0fPaXaD7ud+2&!%0hfd#<E#+mc#
z`6WLU7}FQF%vx!;-tL|_6hWb@uXi33Vh!swwn<&qIu|m*iW!YP>$2qw)x%M<md>k>
z#JBZMm=DJLP<K;*TKB>SvvuV7bz(OFJdcR|?<UqP_4xmO`AWIou&DCvA(ZxWw!m)A
zESaqk*wVX8N`(Zz@UHw|BTx$(MX=R36^+^FYWbY@(@h+;L-%}{W~Eo%Sk}zL$<a_R
zK2zS=_;1;I`@Q>1fBsMCOS=PrWNe9A<U=i%;I&a3RV1f7!<$t^ob&Pwf<Tkp=p67`
z19#Yuj@3<1#c&j0or7DPo;I=dX+3luWrw4uM;OGsX(5$MLGUyd<!qcaxOcT!+(58F
zK(e_P5!{33FqY*3RDg$ktsKF+&*SQEV~>9}mNE7td87Tzdzm$LyY3>hfAtn+mp6Yt
zeXApE0L;PRL)Qe?c$D|~nO!NKyG$_xtF2Qev-ODw=qQv(uz$dSSIeIyTh{7%_~sAB
z?3TN0XzB{{2RA|yAe+$HsF<zAi7S!(xdUdMa<o|Z!aL~A{|j6eR)c-|#v$yzBfJVg
zE|0qBYCZ}eMVtdajM?h!k83=wMp5Za=6Yr#AE@oUwiWqrWQ>U>aDHn!xA&-@?7=bP
zWAl_|^IaI;XL{%%9a_uX3aj5<b~2+Ev+GeW_N>-4Lw-0lEHp>HbLK|*oUiL#6<7wM
zAQ}@mhJfjMv)=K1vWCN+E!&t-wTvU;60<efFLYO1nc!}=mD|JA>iR)5|Hf>p_{|x!
zjXjL8UaZEL$~9&yuzz1t-Qwi>#Lw^PTpRu_4bBzz_V!mSCL*GKaFAT)c6WTGY%AU7
z<JFn(Stna5c63uO@_dX!42%IP3Xeq5+2k73U?U(X51F7PFqbg8sba;5yhFW=XT%Bf
z!@xQ8BsAweDYe8perzVw_db9Yvr-LIopmGWzOImAz;U#N!_dswPm#7fGxmXR{&BK2
z&LT$4t8%>90qxp!BwqVuX_YZ-i6BQ0VN|8~)s?WwwAieAv~dXln&F#;(_HqAu-Zyi
z;>0<(zM!qKI{V#6s?nWj+dQB|H5fdbXC^{^2;CHpng_Ue#ZLx8<>pq9V3S)p%3c80
zRu^JW!IhMXw&=-HKm)0uWAJVlza=1SapMe!&JPD7iow2<Bb$e#Tve7lPGD=XMnn=n
zI(NB{hYtL-K7Qw%1t;mr2b?%o3pWlGBza-4>1v1as)h+Al;zB|T)qCus7Au<lZbJs
zYc4uUA;)m@J!*~iR1;2HU_bRBfb(gs>5hiXSG3`rINcD42SXbY3E639t>CG!9z=(q
zG0Py)BCHc2wT3$h?_tfM2-#X3rld$dp8vvgBE}i+5>V1sXj4;Vl}EF6g<29~XpL1?
zIi54Wh-BSDZs7`%q^=?DK)4sa2Co%u5{BCITRY!!o0mJMH)0z>;1$WS=|zI#(1PqP
zlJ~NfcZ%x^uvPtH>Jtwdh%e7YCronuwi=SRUij2}lXv$k?+DTqvzk}zEehT}M!%3s
zz*tTNrJF<SQv}~M@1K)9<EPx5l!r_$tmxJ&+d27wS*T_;2FYWLh}-2-CF>NdX9t5H
zfmce~U>`mw%$&JgG63oiZ0$cFs(M6$0;In|0DJa71X$7y<5aiF^eE4tH1EI$Xf-$&
z87jFbr{`@*rW5N~6LJra(3L6*#3d`(mq`a2mEs)tHe}W|&%tiG4}@uHEmv~xuW?|_
zsa}LiQ_;^6mvODM7r3iKdcis^nag*ae1b65rrc+FpT@lmrZ+{|A;ap3yR|m%Lb30x
z#})$yY)9Rnwhe!K#ICA#7Vny33{bK?I6k)NJ!5Tsog+fN@c{P=>tl8dYwAeXTx%~g
zHoI`S%}8q&vz4h_+HQEQb1_oCizu?yg|%@vYX98-m~n_*suJNjp5KS5jqmwz-8?&G
z@4^fXIU~VKI_H@W|7jX^`yxB~;c`7DuuNe^IL!6anh|r$J|b`}xj#o|FIT0Q;W>Mz
zo{m7Of_J<*P3A1>Jga@Yt#CS3GFp`dM*3b+q@sOaBcs@l@(+Z#?1|YrcHf_5*@zZZ
z0ofLvKYbgy*4mUX%j}}mCm}mWFlI47QX>|oxj|#oK`b|(ei);3+Zb6fcZMLeB$NqZ
z{0qt#cr}_2XPk}!*iAK(ox<4i8|?#{+^2DW6Ul6pxF2AM#^ifLn}m=5Gmyi;%jSbS
z@?Sq#*m*C@+{5>jfleoU=|bn~Kj(d`UE@{y%V*6_eN4H{N%tc2Um&+fgW1Xp>_3-e
zS9j+3VGcp^bC$E(I@`L92B3x&?*1pX#wOvqyKtGeNnXhU=NHW@PJhVmwz(sL8blT!
z+8dmBnLQD&PS=<k_qd2E#2{GEp(5HOyzd28BU7myL0-4CQ43L%QC<RySjH$juBcOQ
zY_Bj^Yen+Zo0gPGxA3oO^~;-s(j?qdps{*jw$=j(l^GoTfsLBoBYFPH3DhKcFzEJ8
z%YIberj};xsXt<l_9^V5llP#BL&SXTE5vXxbUx;S%^u9G`CEL*<~QEIcVA{Lj;EiB
z2e4|jH7anKlc{nx3CB9eYHMM~-(OO37MykfccwO0Es$6k{jtz&94_ptKYcaAQ|6uf
zYIFYam-|%4`2&_0H$-=T(E<fO`F>k<&s}Nd=j*b{lR`GP#&sE-={ow{J5toM*axjq
z<U~(hvlYX)$hL9V(8EYg`Iw}qCgfO@`s_tC?Is_g{Sc{MJgx!p0Eo##ANR*ZYZ(P9
zj_hp=-%|2e`~CFJBs<>WX^Poefwy*`#m*f%Z;7MrI2HW5TY|MF+Ej!AAd1kmKl1lq
zvSiO+>9G>6VQiJBqZ=iW2lJ;Hzyg!@m64gz_CqL}WG8t_S@@%X5X``BunD^TqNtEz
z?d|nPR_?HS>n|Lra{c!TyXg4~;*gI>1p|~fwC}PiFvZ&G%BzXtd<Lj@vwf~$|6HW;
z+bPTBJqx>?Ciz^vvF3yl%T(Xf=X7urrh!GOHDqvHR0(p!&xOz)E``Y3NzOi3m%`9%
zo$&<a1iK2wnww3_4azHZ3F4S2r~oN5PqLV;^{l-$eO2)OkSo{~3t1R}bD?CI*wAH`
ztK%<-B0`ZYn974)?@LFAwju;|nm7RSAu&}vUIHgwO~L3D@?bsjkciD#w?2@2O<6K7
z3m%5`*e#tye&soseh8XExK{+MZZ>p}5~FZ^;S#TYal9Jhv;bBQe?i5pFwfOOtD(Uq
z<5PwRYpX&H1BFwqV6sQeLJ;`96?xDLQ1gLda<;T6&z|6QGxC-WJW8eLA~LYdHmVvm
z5IXSAp^6Ez+U<Q6<!NcZV4qs_Gdd4oG8+wCuy7-m%M%R0%eRXbSb8K?Eygj-=qUez
zII4BF$PdWD_(Yr#yIeIE=dgxsG^n2Sgi_i)2)^eW(lHBNj$x_-6GXm&elSEY7l*t)
zCQ@^Ol$W~!>F#B=cA-u9AegGUDUzr}pCd|#R3=BmSX<E@zrfF@@^Xnzd-846Yr#LQ
zt9x;1K{psyBTr6V0w|Z|+|&XS6ldMLc>05~n_G+=$G|B_lvxPeyLq+Y5*&eF50v?E
zo;e?SsDX}RC93Q_j3dS%Zp)YQyBRfXI)`+jQfe-?VJ$_7b<yGOwSa;rP{l0vh*>Yu
zw$P#a$vq6j1QKDfjXu2(98sbP{EkN-+5C_kRgF>LlvOI7t|$iINGzo{x5+BT@?9~i
zJ5{A?!#I+zQf+w;b=*Cs{1=!6+;#x;#sq5@sE7k#F|7|WtdA;pBCq22iU3n-WdNIQ
zu%u$OH3VLQEdKRX_>z4SC;2&nG=OpZ=vpsKMNwb>>olOh!ss1jj9zDFYt!C|KF&bg
zN+$>^%I<)8MO@?+$p)j(1R=EfoXk;uRq-ZUR40!aT}(!6Iq$wf#_Cn0iONrXa+-H8
zscUEGX6$g-a#(JRc<#k12hD`<gd4Cw=uOXtRIH!b@?;Hxt!ojQ44vjL&e*Kit>XXG
z#~I)l+AT)ksWJBXe%Bbs_)W3<TwPU#>T}~`3(zH1rwGpLp3{!C(iP+x24q5niT~G`
z+sN{URyWc4MPK6(K?0V^W#Po;)Em|i*6jH+=N0An2Pi<Y5i#={v~djCu#eSNy)0Q(
z1jX6~c;tvXLj;J=z$mGteA)k3%Q_E_QpIjAf>UJ7=vmpu{%)2mC0h9<@^)g>{8wLP
zTB*(LFF2zR!w6GC5&D25Z0>Hy3st~VW#-nuAXiFVdGq{YdFHQwgNtoam@=muR>21Q
zu=Ag~CdlfEFBz?jJ<Aw}kSLj^o`QZ~ou;mSZ@%Jte^I2|5wsh)ERS{WncqCmi`TaI
z4V_|%h3XPUXSZewy$isC<>`D}(+f!MqnQY;GRfPgl_tN2tiO1Ee2byf<U#oTPjV4U
zY0~ivzkfxDy4Cy3LiUH;JZrfY7p!kQVMVCO<0`$9jjO*P|NWotnM#H4r!5*EQT>pV
zZ`kioMrBXzF{cIDsN0IsjyK0cs}i^zxu;$h&s^q382A<4oJ0i*6C!4ur_H~;VonMv
z<Ef!nz7m(3&9j70v}~_~HV&7%6+?0~QZ=ABpc140uu)uNqc^kt?I<sZs0799EC@3~
z<Y&%8@8tDj@h@2A5416$=$ft3*W++KW0~gdLC8#ooUQAjwhh)lRHheVp9Q^xP}_)O
zvLY0OznGp&F0Pt^B-yg1)nCC<dMJ2*XZ~jSJGzMEs*Tq$qexB6K9sR8GZFFqFO1SR
z;p7EvOYgP{7ph)xGd#9Wo_M^5@j^A?kbyt4UKArT@S`0aQgw*2O0L?KdM*r7hwNl)
z>G7A{U+<_$#OoaJ2{V08z%Gcji1#Tpq+7gZOR8w3Ddd7`OQ>qzM8R+&f$p-i*wE&^
zP<~*sLKH+PAo|(aj#KI}XRfeSFDm-6Y+GJAoamrRbrY~j20+C?v5x4{<o8;B%7K18
z@Y{Se%7?oMMCE8k2;2PXjt<)67yy;d`cc)}uv{ZU@fqNDB$fChL-0zGdEu{UakkKW
zmsgbqr^D>YMyT+;QJ-T;*(ViAl_GDv2F(W?l!Ns~K=^ltkQ+zk$5QcDYlSXVz-SxQ
z(JQXPbf&6j7sAb@Bo%@|Es|~)KTI1gwaIJ%Kp>h0k@2)#*S+GAYPJv&x}_LB&Z><B
z6Bs&(y<&NYc05vS8c30}dm$s65H_8=xo8%uD+^>q_Z`7?v1hk}E`IY~k+R!hUl4Xv
zb9hEM(UF_y$C%3IV=)*Vl7lQrA<ikR>Y`e53tTMe<lgz}gr;l->uA7>7w(SL_dX>g
zNqgO;MHl(kLX<6HLlL5=D-UKZyWJ?87MJb93vo8&z3i2qVRq;Ziy=gcz;6rmw3lLe
zYFv~m4<cs#k_w=uD2OOIx_Odw3-mZ`!EJXg)ctk@DJAtJ^i^9!-B!<TZV8Q;D^YmV
zy9Hd!ZSmQ3*AvB5)?&)%Jk?S;bcuJoE21ld!j!HYRW2OP1l?>^1KecL#iU(o=;y_c
zbUo6gH_-iILBYkSI0d@UIL_HUhIYCD%4hZzr)@3Dr`6=xBRlF~TbKl)@FH}Tcl&Mo
z<70bR@{RIDp@uiOxP;kqO&_KJab{)<wx6?GkHUQvXwMikALIP|s~L~n<bpg|n3{}s
zWZwA*-ghbw|B~OaG1?e)l_QxVIGnH=0QI`7+n%aEY>YU*+)<xL(W7hArrphoKAYHR
z9D%P4X-cWBAj51uIQ=>M&vrLqom$ZHLx{0r@Gcj~>?yymK6zx`PGPp%2vs6ho>%V_
zH|Y6$D=$WQkE6U`8k5}3byTpdab)2d9nhB`vrg>2@Ldv{M>ine-9Uweq6n-hhg_;W
z8yJ5VQOx1ZR^$z0bHV*V%WJt*IEP=db;1RlXP8!7-N}FcCe&^WiZ)0&uC`)PX2~Gg
zGmk-%OuJPgI)43up=)?IroD!r?#whx&>Y~3`^N8OSv0Yvh*^oDk8V(N?9j;rX{zUF
zK;*lL`0eSU?%s;LfBJd`8hn1Er)0=?1Tq!sw|m!ll6+#e+UZ8jJ+^wxTdK{moMCIn
zk3D972G_nO6PAH3H!{h;HsPnPdUj;areEzP^PGot`VzQlND*vL)|T*2!eaz3N_b_h
zFRT+`;(m`wdB9o-K!Tg#<cuQTkN)Ku2E1r*yBwPvsXige0R(BN0LMRaF_VffP{t3x
zj`ObwIQjy|=#Kn@e08}4X_W)3lWd%tfE#%m1e}ctcdzP^%WQ?0Cr;c-&Sxf5y;0UW
z^OxH1$3zyhWz@t-Wq~>&l27S%To5Z`tKO;hiL5{PNVHEUFS&b|*MH`+5QuTwzqRP)
z#FI$G#=hVED%$z)S1{cHooAA%yz*9F(|f^|6j719dpe7={K|gt!cs2rDZVNXB=INr
zuHYM%O|-MJaVDc5;C%CQDndui_~oe~?8@e>fM7?@_ewu@FR`zcoBb!&`Ij^)*81(I
zYk?61jxSt!I{(ZSsCXmuO)!oh`lpZtq8S1Z`;3KXEn~JGk+rNc(`u`1(ppHT4;1#~
zMZ#O|o3$A^cpir!5<3>wg+OTq^|I=#6K0odPgmc%tyw=gdPrug6NB%@G*Yat(?@UT
zhS8=?Ou7{IoNv3e)sS9aNhsUveg1K|717BdNXqOwx;$ghP8TGj$Eg?oJ2kcn=W}g{
zLPgk%Tz1)0ZH5BRvZr=t*(ASiq>v<yhLmu;{4HRqGUgz9x|cc~pi}w-JHjePfJfHM
zZ7qq~(}MRQH^<LM!eHi8VPxUKDyrp<UaupxuTU|%Y^`CTSHP8~Vn?%EWcCwhtrVy%
z>ctD6dp$oAgs~t2T=h#xu2HJ8=k4oYNP&4X2N&vU*hVU~GcD=YK}VL`Li>4&_n32$
zKuw(yS-i@AY}tO5K(f+=b=pL6wcYwmNYA{g>@koOniM@aaUV@j?-Zlf_D`oy4j<z!
z)eOfks$Q$DxFg?`0-Lv0iPjbD6~ud}h_sfR!(7`133ts_vDr+0$LOw$#Y&ZqONW+J
zTpT_X&5*E#qD$MoD<~<oi`n@Ot0`~Rp*yzGDyKVB4u=gQYyAJLy$_UUM|Iy>@Ad1R
zH?7vpn^6n3<Uy)#wL~KXYW?Bt7z?OwHKHZU@lPOQ9UI6`vVvtG@fZjZ4#w4^1{xyU
z4XgFa33h&9Z9K@BGtQD6l0)JrS>z~L#hF8}O?={WdY!eSIM_SM21g;R+0XaZd%ynm
zzu&KM_ICeXRo%LE>(;G$_3BpDtH=3ma@!Uk6llTPC7V6W@>Y?^`N#u`T`&?bH{+>J
zE2MHC0v4uIZ(XJqM2gs?Ds*N`<EQdzR2iWtvsIpHt<w~>9x{xlG7l;S*X91jHxg|8
zKwa3e<sNdebmQ?+IoqH*GYArkH+i`NMbu(lzJ$ZezJ?mO1SIP>XllveurJG}gmjkG
zU2Po<ur}}fZp6^Aih!6_9bq|<rs^6@MuuJ^J?C3&D>wyBokOjdt}fK`p@4^YUx7+M
zwl}gh%i9xHLcuA9_9kuW0Bpzp-7-RZf(hbc>l@-e?%Z4?-g|y?A}o0O2`BLL{B}Vr
z-q}HX7z~*Idaek+0=EX*gst1+4{&XUUGs;FVK2qvWt(}jD4T9{FUdZb$o5e8piU1;
zT1Jw>U0jX|2Y#NPbMYDmXz$3~G%pIy#~&zWRRRs(H*z-8MrtC@2x;wB&PW*N<B8tg
zvgQ~qc_q;=KSxbnIOg#Jn9)`5rKKX^dn~!`Day8$Ex+Mu-7Yd)v0-EWN<96BW(oGY
z1ebRpc5~jzZ2j;jjVSnA(7+&USH=o4dT|wpJ!Io<;pwaBJ>DS|9p?*?B+CEum``c{
zlrIDhaxp(7VGnX21RpDyoId)=D?av;)Tp;fY}u$;U~_RBKip?#;$Qmd=)CBV0=HxY
zZ#`k8@(K{)+;6_7(z(HzY>SnD_7>)ZAyqMa*m~5>JafvQ)@`LTVh@$KvMp}=o~ra0
zX&msPKX709os+I!X2Dl&h6TVZj$PwzIMY2(7l3Zv=2P&WV%+=r86Rb~#?NxoZ@k4D
z0|<sfSa{g;9v)8=nXT1bmUE>htqKWBt4t(M!hG4e?whDqDmpxlwd~(<sq6V$vy!)N
z3pMMo{Ng3H%gt5aNG10se9Hxr@@}yk4p}&QfvmPL08r)1cDq6kN@)UpkiJWMe-8s%
zmc69k7%*F(BNc^wuKptOzLD(%tf*@%ITidmj;r}5%6`S`eX2XHa-Mndd))$ND|a)c
zBwJO`Ncj2-zsw%Dm!jSmIVGmCmVfC(2);Gu+ug%1e(_f<TQ)AiUS)giot&<C$z;{}
zm9fIhpnm$@w{W1)jn?``<?8e454pAOd^VRqpdw!BNfBc8%5AgNGEr$Uo9MAITV3C5
z<q@1+`_EjaY}dNS=iTQh{y*qs6YNKg?*6~w=L6*SZ64K2RN!;p+|1`kS1SdZFV`MC
zKYl_2*d}46-U(N;hwb^Dr~^YR%Z7Hf)y!6Ft|EWJ74D3VBH~@pbZF9X_ww*8n-mr%
zOwedY>AJ6wqGr<~NrGiNdthb*5l`|=zVLo_Ah2}VKa%Mu>b^ZYK}7AAE+v+GQ^Q?B
z-IG<V-^`up?RIkfEdpJ39R}PH;GMghhpDFd&rf{1S#2#en%y-{VRBHl>YjPEJDV@s
zSdq{lPplRj!r$)B=v<$P_;s}NY~Hm|NAHJ~LNF06F}}dNm4kblEPCI|1fS%t+y~u?
zZjO9klC)#;fVllqa0tSF=we0K+C{(0sTQA5R}{0jjHLZxpbt6G$Wd5Ddos-idyxIu
zrY?ov+cDekZ1n~ul0M)^ziJh$WDC&iIfhN@12a$9pd-9CNjG7>MuD$t9>NXsU?({D
zu@!Y?@X?^2oaf?hWfifn5lX93q1AJb1`(zuC{`x83O9yTd<LyV)`26lU~&H3%aiZm
zYa;bZzSycZ>?V&w&?x1MhN<YoAeB{*A)+fDbkXbz)~p5IW|4BAw%$=fa9XWeLOUi}
z1TnB*K%xC0_q=WyXzxYLq+meJVl%6HvIq*@jp$34u{_9Oa<(*A7f3Qf@qsa)6O3vC
z#gmE|3Te|>9z}$m)Y5jyt=9(3^^5^6H@o;Ij#-Ct4nL<zMOj&SA%!fFbp%V(@*WI5
zhX(L~L^~u@C%W*8H9FaoqA%y3n4yS?pd+n|%he(;N4Fj~@N*N<8gsz0$pecik=WYP
zq>AAA<zqc-oOlUPmT11A7qXd11bn5fVMw?ZjtEY?Gq9<NdEW#Wd<ck3Y4eG*qy;kf
zPB~teVL;32T6}jIiQ^8^?KT5?M}Q315-Hp7@D!Vf9Ag<%y$w`e$Zb@iWj_z$dXnxC
zf+0)L<OT_>3nK9U1DL*y)e79U%j9PVnAav`EsVF*+vF2qJ8pX1MSg)FM|J8t419`=
zG;48<g9)0rM4@Xhc^8Z1ws)Csh-PeNk~Oi1bk1c~D<L*AtFPDz-6j|Y(1vT}h_o-D
z4es=Ej|9agut#qj*w4+~{S!{_-7M0>qrpAWSfY!0F!xZGm8p+M_Xpk;TViIT6NW8x
zOc!274c`iGD_irumy+otP}P^@wYyTJH@P3ekUdd6e1x$vrzL^v@un;r-|>wC7F8iR
zeV5C(Fdv$1Coa<VySf*@M4yH{owTGYW|f)6(fz2)Irk~Jr>C+f-PW2b{ask1kLYoG
z7<j~aT4E6}TcgZYT1RD>SZhrjitVb>YODK-sX1~wW%eq}R-L&Sj)rE}v<8c*7QUSx
z9UsmXtce@1z%>q5ead0)wR|*0H@SJu_7ZMO6C@dWIa<Bwp*bXc^##5$^ZD1gvH6QM
zs<cU1D{-A?mwwJouYY&YHs079yM}Y=SniWK<lb?$7bz9U=G+(ROR9IZtF677+B!_N
zZq^@V@XsJv-#`guyMVkp)G01rvB`0-CE1!hu=`-)YR}piWpht_U+#25ZTL%9x><jb
z;nY#KO|p+T)WnX2@`I&&*4<!cYbCQ)U`v^}K>;#JmXt~no)v~wCGJcg-EklO=p+hx
zeq3g&cdEzl+j^O^ectCkf7V41Zv2MS2|H?AFALc$mLi5gC!6`_MR@rCyu)g6F?9rq
z-pf(Lk+M4q90u-@eQRdxi)vT^ERMG8wU@k&)z&{ELWZS`RNJbp1DJ%F)+*;MTiN*8
z-{wVi%U0Y@9wOhZo;Gu{H~DLSnmd~jA<?Hk<g)I6VDkkL=}0D8i4LhQ{C(rL!tWk?
z5@p}_MwkEakD%;d%Ut~_o*@rik7UImvK0+xt8)*OF1&EPO_RlZIz&axi-8mv$-@cb
z-{n!p6Qu@dG`>8~wMlsM7a-vk{pru$#<o^=O}p_K&qDOk)G$7SsjqG~^3&em{)k=S
z1E8EN{9JYBx8cSA;A;`73xHeNtxI|u-XY+5Xy_3a%uG!5LF=`EXCg1CBj%l5a;vpE
zNq6TK#~3yVqs}w@3HkW9!-Q6yiQA#z_m)<Ywfw?-t^QwHbU#sa-IM4Ld31oWQ%9^!
zN;WAJR-ACsyYZ(e+swqmLVQVdn5{gLXiSHO7%nUF^Sr#g^_cF$!hPgKq1z+!Q}rcK
z#zp;Vu0EY-*dx<2-z>_A9%|E2Z#*tCk;pB?N0!{Xo9Do}Jdi4ZNBH~`ZRlWk)s+up
zF@5<J2a^yJhQ{uSw1<}UaJwR`okby;1}%Cj;KR(5VJDP9SRm-)TV;3x`I6~K_+gN{
zlZ<yaA~ca2wJO6udzQ@9)J?%e%y|WX{xHHTw2Hw+Y>?l~)=CE&jRe&d8D@je;U2u(
z>@C{)<RtcdQ)24o1~Ivo2&3zQi6o5cSa%eEqoHV=@1&KbB(y7bOvP+rCnJ>GAnM%_
zL&HI_U6o+Wr$Q5s1QqZPyM@9glqgOXz{s|!JdY!({azu!=<utLlo5X*RT1!vf;bgZ
zubGYck_S+Tq|}cg!>lJY-rzY&hr(K=$95iwNU|10mj)}5dj~pxBLS`=&Un#I_ovp}
z1i1yK%s+UE1XNlBRG{fC_8;<|2nh>sH4Bo|x;4_EPE^|v=mk~(qu>J1Fzy|iheX^7
zdOioC#;JmZVrS&Op(nw5#fX`-)nS8=!rD9T<x#|>i^eyqWR(K?RB4A$%%PJ`qLPnu
z6E6h!AmQQgB)ofc0l~8M!F7TXq`W<u20CJsCuDg+wmxMmB0acgHZ4bX`Qh<mlJCCb
zM7j$CyBuQX5g4I^19Dx&0S^=ZdeJL2-t%Y4KZ_<q)|ECy>V?yQUz!U1Xx*IP?wi0#
z6H}5Y9s(jrp*g7$fMgN?#=3ZZ%B}&!g9!=`;1xUon8j3`b=<5frg^|gA_|_4j#C7g
zO$Uwc5O>_G0g_cg0<Ubwg98&u1ms@VQLyTA6+{y?QFlsngHxHDFBha>l#_2H!<0-I
zEp;g~*f8NaNrFH}X=O+}<R*|Kk~PsoAr`cy#}L?s#H*oxC<HhFm@XE<i<c^!F#J^7
zpnzJ}W@ZXG>53Q=$v814nWUBsdJ;!D1%al;;2R3ek&b;NeY09^I}8#tR%M32bhU&z
zX1W=S-p@ZKNoeWF5z(&Wj8c&q2cb>B5SfTuip&^1+8&Wp3>>!<P8ds+A1>Q?S<3cI
z%DA6xP<eRhGLOC~d6ezE-*WWMlU{G&JL~1?LAz8dLKj^==Lfc%^`E?i4uaE6GG#nQ
zkH@3NtCpUCQ|`km30st+6iBYzV9J&~Ap9P2>%mB`b|+@exaqSI>;y-CE^cKNMh}x@
zN>uaS&=?j%NvUc`iu@GVEw`}VWJBm6IGrtSq1Eh&%gRUGRJWDvAo@{wHK<f)UY^|o
zDB2<vsU~TlCh3#6xu!<C12r^|_PC|YAsomyD&3BV9oag?i@fwyX7Uj_9H=GGL_|En
zPXPmRNRL=TD#<`mEi`!Xg8}oW6b)ZtyrG**7z`Zf@6cWq+44GoP!Hd}ZVsRsKvS+f
zFrtGkUhf3b9S^t=L&~l4x}^=o*{kd<=%ZUVXW~dpwIU{nI~2f&u@*ToTyRsCN{=&%
z?n@$)5KXpeC9uIM&frArftSSk&S5`I@)Yp<aS9-NiqMDxsdqu!07KXnaj0N0`K5np
zasYbDN-I_iC_5Z=V*_yqczIVYWDMbTGEc`v7w4=YCl1&$M06O>)I8}>+cdS%(}E7O
zJ|gAWhb&~9yK%p$Ez5bJuzSk8Cv(P}WIGLa9+H(Ck2Zl3$aW2*ANCf(m@4Klo2HyW
zI#U(+=!%GIJHI_5yS&nL<zl~v6}d0eG(fS52yMKQ{&)(Ji6R0&BFHO`TD8Zk){=7-
zY2>#}mpPxfL1ElHC5Ob`F=PV;v?3vP5$|xgV9{}#i0qJQ7wGUPKw3By)Vzk^cT=ig
zs*zIVMY2L7^B9Sak8+WzR1^7e%c?t^v6`@Q9zI`E<`coC{oMq{eAw;|3HKEuS)^FN
zGwVeTy1|=*FDDhOrudOpP9AlBUKQ2{-}h~MTIEqr(|`nEl8N)sRgLaCSHzh4?N>8B
zT!S-sV*7>?X-wGR*ORQuPox3q0fcHCV)vau>6psf52lK?e0M9l$6;_{?$7Tc_P&o;
z?)yf2f@5$ZvL1Cr#jWodUo^E<Z#2~^VwVRVhfS^0s5ELiG^moKo^qkzRJI$UaU!P^
zXB&Pwfu>s995jql-j7qq+luz+riGmeVr=mTyU$gWKG09>OsWL+6yq|%7r)C}k^AK~
z?6Aw99&uwj{%r^Fy~p_Z@q~*1ksf^uhP~H%#)i6uwGn1Z8*jAc^Seh?(#ZT_2=a}9
z$QyS>fT(g`J(lTgR4~l7YFp*o=?I=LyuQxiiRdW8`Mb-Q<CdSw%D_gzkZWd95a-Em
zYb}j}66(OKY7;%(Q%$?yL5Zup2t*Ar9b)+HOYeI&gN0^}Iu^D~2hsK)x*sj(T>M|%
zQoMoUKc0QU)!!e*mibPmg$41?3%gr`g}C_T)_1Ury?3JYou3LCc<%(wzaxeVpPqA>
zbZ{sT;pq$O94q=VYsEcgyaTdieDBfCe5Gd!_dk1^%lyS9HeqW@pLGDH{e!*)&k{5H
z1W*0gk|Pmsp)sf*ysg0P3t6)zF4$KJ*S|Y@$o}BsW%)xy@KF%-#wQ{9B7yG^v+2es
zOY7wy{w+pv+6efMA9Mv1?k?QP95D+yo4c!qxIK^tLg;C}yrZbXbu<X>{Gta3`4luZ
z#rv8*M4x&t?^DN1EZH7?g4U#UiL+1M;5xoO65SsjFA5TQJ-D5ex%qAXridHW8a%(l
z!2Ml!#I3)1D(5KHoo4GgoNR=4-9_YMtx0)|1YQA*1?x2nX)|h~*DB2dOsp9Pgj+({
zN41di^wJes$%=}MU8fCr@#pI!!A@CevmKcw1iAa`zXALAy7cOs>X?y{vOV|dn{vk&
zSX}qh98>erS1-HEh+5B^H`*2-K!@MOhgI(R8CRRg@8y#z)h{*mAvVL{*T2nR?~gwU
z!&&eAkEWW;xy{rRqf+Y5bARvt6NWka5Qpl_zo*BmiCIst1ls!1-B;(~gxc@<Z%(?$
zA<w5~(b4-*82@hLof;y*N&5f9zhB}oB|O8SSKj=|Y;)sjdaJ2xU31%8l7%)Qi`{r@
z+S#E1Lao>Iv|~_$7&IM0U!Jt)eJhk-P*<&P7bsZsSyb1Y_8+#{28$ee$!US*7g+IO
zn>mD0k1Lpq!zZr~b3{1zd*8=a)mJKlVcVv4gm~}bcd^>c&pfd)W1AdLkLBGAfmZv%
zE5!k@_8UA6t7~FbUlrpsw=St3ZsWe)LCz@rWK{JA_b)XjzDpywJMs!mU7=T=Rs8F^
z6K;lY^9q8~xwY=!YV_{nGd<1D0jgs6^qXaCj)drz{G&d*_=Zka?HEK1ri`A@dh=8o
zjM&#-`28{#i|uMo38O^CnxG|HUj;U~<Iej;Vsk!?cZ5Tm31UdAXepzPUzxIbMNnmz
zi|Gn?`f;_}X#Z}i=#X|LHwl}zH%Ihnh^vUtq2^GEA3*Yf4%|e^+$M8Tzyu=R;ufFv
zsghPy+>nns7FslWi45ByYY>QynCZR`#($gWKwsu!FoANq#sjJ1fib%y7M<6^iOM<n
zJWhUL4Z5xNXWZE4S+q&{016joTrwC@k4AIAXaiEy_1F7I&9Po1gC&>%yi&!D5jP_i
zIr|Tz>x$hVM34w<xtHrr3>yK%hFcz_8{#kd09Onyggg=X9kdOSJb-ljrT7h}l~)R^
zC8ok8!*)<u(DA-aIjb=Ec?lWtOxboVVGjn)@N0X>EUpXt(-D=lzJK&i><qzY`FWwO
zR+=%TB5HohNWIXkTy6H8xC2j6NF|B#ytB#BE8o$1SFSh1%>w6GaznJ>d2UQz)r3rx
zTiU2rfx-FQsfVtTz=~&N$|x?re4F+FUv8Qgapobh5H4E-6f}s9%QLBkfCot#KB^VE
zjqsJiNs6YRMf|W&J&G5R-Neb$UROiwJILisamw=yMb5lvl$|G+Jz#R|!45&hy(wZ`
z%G{|!5s?wnvQm$`+RL>|#1qeQ0jPH%)#&JY-LCovEZz1cY<qY5G{kS(9TM>*c+BG_
zFk`a~3~|wv27%Gm_R1R=YEe}k*sQdPygY4vx5(7m^>FV>3PsNi(#Y=>VNH}wDtrA6
z3{ZVqPp#pw*;4R5LMZ+I)SUM6%lpUdgN;{4#vqy*6zD@02@1aV7~=2ID|D|%75`yu
z0eqO~y$zi_vJ@LC?%jHdbCrMhl8!L86Xd#n+%V70)(|42rA!Jl;8i@#Ru`He&*|F>
zZ-HJyl@7Bty0<gmqkT9UX<@eR`e0fj-Tz8MW&Fi=#r~;_8f2Y?%-b+*2R&AdpljE6
z*fnsHjd$){j;Ejv@ES3<UbUq7vU<(;8XZbX&jWG-#>Q8&(ak*8lX-UCWbcNC#h^oe
zE8@VgU$dEqf}jH<7xgWR2>n#?Iuj;P*6|~+-l%3?$U3$+?Pp)-DLzUZyJos0vo%vQ
z5Qfh<x{0YDb9une&N8HsXE=oH2VZYznUwZ^op=Fy6>mac=b$%oYlQW=hukabubxY<
z8Fw*TE15&D`6~z`OB=Jb^6wbegwH4lneVN+;y25Xmp@*(rR%cjNmJ0k<hqO>To$zx
zZyZc|OS*jTlGUKT2oe7_4_M4ry9)v&6rZXfkze`LB}^WJsOV6iPz<G-xqkkHJH(?k
z=H2-t(f!Bc_DS#J9?C9Z1W^|$Nau$-{s*2~irN<fJ2{<u>)$|fb_@n2heI;jzs#<E
z*^g4Td*d}}I28TyaQ69EY*<&+(R*Xhtli|+?)>i?(UZX#+~U%{Iqg7Bo`1zpYkD5;
z{JP0(b!VQuHtyKl*^zOmI)2t&pUQUg1ITyRE8Nsuuga5T|2r0s<cQ)n0^;UVoK=xc
z``Ptb^z@^Ne3J5#Nt&U9eOXM<tMgw*U!2JA{Egr|l!az{9-GN3z0lYBgR8o3@gL06
z&Us3i&R+Y8reT~(rE;p{fBmPNLvskp_)_f*gJ>ECyevDM9WZI<hweZP3)EDayDjS5
z8ojb>^SzSCm0P#EYh^#$F{l1gFQhB}<yu+AyUovq*VXbb{4F<oZpO6F0=~E%1{MYz
zUDK<%Z!!GY!2x*^-B;O?EXeOdhxg~5^EG2>I}qmdSU8v6Zjqxdv4}V1vFxt9rTR7N
zn5`kDxY^Tawsl#$&Konuc#hPG?%Y#}$~HIplkV5e((W+PWglO&0i4?0FIpNB&1i6y
zV8Q)Cyg5nUqV{!tR-Y$gn)2@lG&+IxkZMDRg|J{Ln-qa$c$uYhLH?s#96O0?pgOOz
z$Tf1mD47mxI&Up9Si=Q%cz_)XbE_!<9F?=Kd!Z3dcV(<5IUry$b-byo+)F<M)4wGW
z&)6sR@<q0oH<`IP>I(T1@Kje_({jBG_jwoesHpO}CcfWccp)f7tZ@%Do+BFr-#%S^
zgV^D;R6CIS25zPlkwFKdYqb+;tz51*!IvrjXZU!Pu*;BOGNqr)k+-NVploK`xJfU>
z$&+@|THKJ!c*gT<1vbhPFdweAB*~0!b*gL&33PNO5#o(fY>wmmC^q}|h&c?TzT`*@
zBvvk|!peL{+MrNZ7eQ@TE{k-h@^cbM;hC7=TjOa%R;tZBls+Rmrh`UB$^8W;?&O{#
zc3(3WRs$A)-A43v&?4kc4F*Q~=Lhqa8UYp9*N);#R*ED<ET%Z0BcReoA>e2URaY25
zG=~B&s#bDKWeN{T@SxZPlS_@~(H4_yk7*|mY|_(JO2m=SW(Oe;(?Y>y?KmHIBn}un
zErt%sQ9JymFsQ*sH$h4d106D>b-C<1VnbhqK*#_xC9t0%4!npm(XAaw^B0IvO?KOK
zP1She`mz#e1dn*#y4SUVD5`lZT4!sfE&5=$XB*s5YD1Drr9ic?BNdGEkT8v-meUFq
zl_QWQ?P~K6yYz3GSgVZWo_LX7&*_~ouV78nDJI-U>`@s(Fc(w=iR;y<cm^;#6WU^&
z*DR5sSThlInW5!8X2@ZezGRvgI1m;uvz+3A1Un+$j+oCEn!GabjjQuUqYVx~@V0;H
zHKpI(dQEoP{YilOOFohI{txF_ZMF1c46(vQ%VDT{b)J%U8*<WDy}Vd}!%TiL)G6^T
z^w$Q3-Cb@5v(?$U#6{3LQYKsvg}pVB2!~z0A`Aa2YV~($F?X9fx#h|&MQlU7g|;H7
zdLg)*J{IJ!F{n?n+RD1>6)x9mYw>tSA9FiX|AO*HbC?Icvq`P+ufNfE3_tu*7F*--
zlJK*1BhKl!4U$ClIk>>K9lM`TjaIgW7TnfEKn<_p1o@vi6{_mRqtq>6?>1dL8scwG
zR{1H+iEWGWH&1z1ThXuRIHE*MheMOCM;)se#p}<IEl@r4Lm2eWyfvD=a#pD4Kj>yW
z?)b0W;7_S+GFuTD%T|)rN0?c@%<KKNED$>!xGOyr)g?dYJgcn_hk2{Jyy*Et5mp(>
z#NGCRT)Jg&M8C570apcK^S?{`xs@IpYdL4NwVEgYz}k_v6f6ckp!Hw%Vz*UhaoyJ}
z4<#Q0taaRWajkGa@+x~QBvm%_Q7#Iq^le6oI9k6N1ZlPP)O{;v17Zpqc&_nLHm%v2
zvd#N+m6ko@uOH8*kNtEWG>efb2Xq^FYmqN{UnI}JevP#^@Iye^Vgq`sryld=WE;TE
z-p?wW%xEI!g>e7=>R`qATK8pz%I5g+VsZ4!tLgsgqssw=d*(8i>64}-p~uLpy1;7a
zCyKyotMk1dwa#}Uua+&7C>F|u^K<B4@x*N1SO3>*kxVf^aYH_i*?Kg*gFO}84f*0%
zuj_nF?-44I|1^T50ajbH5O7s0xA=AWMnI3^U&XCb*GG!lc<oBiC7icrs|ZFzO+Qlq
z6X-7PY6o9DKC@ykg+0#_Ry^Xo@mkEvZulYm-3c~L1I3ogLXm8(G`5EWC~624?F(-4
z_x@H`OoW~ALD)$iAlTKtR@w!EG63Q|j216eRgW~$Fl7I3cE%hIY(p8ZuVwXXdcCt+
zJq8L@+5q@#DccXJRJKmF_2V1p6j+$_)0nN=>=O$V^49nYi0J>5qVF|P<6Lht3q}v+
z!|u=G=ow*(@|Z1L|MTP31gSi~ec{Z$*nN=P7y3+_sd2j*AZ_5DIXadWDpES#TL!XD
zc(NyjE0Ot_edIL@mM&)-vJno?Y5)Z+_v8^|(LI9`xPQsQVCHPZMN5@j-3@ZRawI!|
z`_{{CrrFJV&?Q;~%%&Ue4x_CjmTwtM0$Ek8CQQYW%_fLG1a57YN39s$jXWBXB*kQI
zNkpNggd~|ZK~j%`+6DMpNe?Cs;o!Kzm@L&u%>0s@iv1Xmk6S3O&PpH#^5Fr~rV*Sd
zK22}tpve`cOd-??5G3G}&J}ea!1XA-Ez>k^6@#fQcHkxerM1`Ob6rBJJef2-QUOs}
z2o~)@8DPPbC5cQLi#g!J1OhB{vguK`>_SumYZ=ZCZ|U2F!5Ax6()6M|I`Mh7pa~-m
zw{%ld&j#z1vCjjgH~G@VLM#qJK1#GI73toC#=$0~M|l1Z2`CJhNjaxdrj)Q)t=qFb
zZg$m@&{}O(Y0He2CrWH3$lPCPit_|zxsa>uqkt1XJEHOQ6n$aoemRqAuA}8tEyJ?a
zyr@M5gt<hvRWKZ_0;}!)WSRgN;9}$lU1&oPhglb;?3P6>auq(v1H=t3fnSydKI>}B
zY?2DO+=|M#*p_(8sc(Uu>jtNo4n}cWpc5YW)KYSXUKdDJ<ZjIxgI$J_4~+~>EM2GF
z6#EbtMO$=>^tv*5nKh5He+;`#B$1!Zv`JmVAy{;4Dt4_9Rx>GCVe#U!o~x4vYW}1$
zgFs$bJG*x3+}K7R=r#<zi#p#hXSH=NM4@=VjBV(xG6O=+Q$8hsi1EI^3y+#4NYF0G
z{Il*h)dqA?F$SRGK(IycatkG|3O326hPFfH4Xw?#_jV=RKWK7XP0k-r-wl}<7<zEb
zDTBc$IfC9Kdw+X(+ytvPT~=J>Zp~)PCywT`8}9=12*yKw$y(1{o#oQQP*Aq<HY15A
z&S)(3r9{6t=BF=wBX|pSulFwgS&?F#v?uu1wT1209mjk{GIygpPUoj#OHlL>h`KqK
zv~B8D?oF7jwaiwkPB{dnlQQS{g|r>`jTtcyLVC{~jSz3IZeg{xVz3wxS-A_A`RcY3
zolDPnT4JPlN3!;Qh+QwTArO`KH`c;f?{uQtQLPF{V_^$Rq|G$Z4Y^{Bbt;a2I4c?*
z>H=^HvS;(t-$b>-9Q(=U2G!XvGamxOie$+L=qvZ>OJ@V$v<O<h)81b%`jPO)zq}IA
zY5C0BFBL5E=2EKc?d}~{m0tIWE%F|Fjmta%_b5i8%2xmRv5<X+S-i#gXpA7T^?zTU
zv13=1XgCDtJ8L2T*FWnWW@{Oqk(#*k$;_+7jRMQ^^Y2^h`8U6TQ)$bi#p*-p=F}o@
z_|&WO6_ZRB9f=U2)LWsfu|D;^{ugpeRMjq*LCyYGz0h$eK(ap{&(6O2_?%7x31J{n
zlwYj8JQDFRP+>oYm&$AvHIfUoTQ~mdO`hsX%Jzzo-X2HZ^09w7VP-3n72N1x!_U7j
z1h1SiI+-H{H3CX4U8XjuPeP__&wMj0;?q~@gYU^~wdHbKO3eyyW$S+Xy3&32oo-|G
zhq!C+!({xk*Ppf7ixC;7=$S2YcwlM)vz1}W?W$IqV&w@rAI~32naFIlMVm;f;>)iO
zXL~$Ay$ov1R&UGCZ~AST)_*J9bC<JfjMmFuFY_w-MA>yQz-|)Wc6cxEqK|}d%O_nC
zfB%Ty5u=|UNk5bTtyGI+Avd!X)1=+ZAq%wd$I9659_~lj+Zyo|))R3-F@g}U2^vdr
zH;o17%{Syiw(Yqr-RvR(Y(SyhvuO7pzvNBp3K>|0GSPMcL3}-$JD0o7T94+ZctXB-
zEuKaWQ5*<oT)feDPq15+5Bt=wi7xQ?LH*;!37--@fyE;5T^^P#lv_VZmLZ=l>oNCL
z&-USoi>|lO8E2q&dM&!@XDjN@1+3a8$wt-=8{8U_`Iggx?itDzdferId=v$w`)6O`
zxG#1$vZcBYp>{#C7sw=6M##P4Xhwp_&r{HJv!&qzffZp4I<4m*H>L>Pt5l53>V{Pi
zLbkn?O@RWPSRi*FQCQIu#$YZ;3ZiG@UillEL5Hba1!pC)?jO%6$Xov!13}^D<O&#6
z*wwk-I2JQGowx-=<Z~K0NKvRFo6UOG>wvA!C{Eba#GzNv=eiC9G=VS-@OhCR@eIgd
zFZjKvgE84!maG>@l13%SZB$+_<LRIby8Nsfa3iLe**O%?LqMW`L!=dDdsDdZ2SUxA
znd%3o`Fd0SI1%&NMHfHmn}qell$U)#++LJgSp`?CsulERKe}-;_G5kFnv@4PSst)g
z=uSIuQn~cw!;-mNn=@;xU{$5HK%|(;7?DjmfxN2uRiZ&_n|dA7%^5@_$<oiZ7(-Hq
zvn^9a9|$o9B^+-EQbi!4M1u{3^E&Z46t`ryHoPP`e1n22S05IsWdnU&vx`qAIeUWA
zx^5Z*ju`=y1Fb|UywA1j2C$*#vMC|OTaxpm0#TIo-AZqAknIk6d_c>3i=(TpVry1x
zr93RWvngL70f~J|7ugc$)|0=z`feKwW|RG6)_q|PdiNR8NDmKCA6n_?7d$9N1(1fW
z<~IW3&o?)e_uLrMu2Cha;y}u(T^b$09nx!T`r-{FYGsS*!I3EpU6i(W(W^WoK&kj`
z*s{Q+c(wdf!l~^_Ow6M@K};{j+O^0+Gi1z_;b7DN)n0F%P#;nIZQE{0xHyZa&;V!~
z2+TF1cr=%ko}Y5Oz*uR93Wz5;Vw$j9_SgsV?1Zp0xKGF^I^+~0m)uJ-gPyM1!}SQ2
zeZ#;5-(nBCnC`B&Ce@Jq*Z}F<iGDumJGlRlG*E869g0T^8YjRcf0jELvhT<roUHG#
z(mJFV4(P37E%)U3?_G*gG+MgVT1j3@Nmo)s=U~;<P(K-m-t}I$o9hY^tWbWIJ$bcj
zEoD6{->Bxdb;3*XN%y<`3TPR#wEQ#iZ@X;Cn6y|9ALuYf1xE{9*Ct^%PoQ*vb~Jb2
zdUPSg-)HyuACl-zOO)$gABhd3Pw>Rifk2Dg<;E$#XMNwtiisW%_!#mF{Y`qRAdSDv
z59Yr6h0Cl9+vdHC&0w(0(&db9h$!r_*DuNmx|m7xNBR6&1&;m3g56l39ee4?P<{)H
zxa)AxV(t6M_PyLVTSual8;KYW3ow7?6rU@2A<NcSx(qrV69`*(u*~*W@2ao6*cyjt
zJuEjf`Z|>{@KYwPdWsRyy?m>HWlyum4pZ7Fft~90#<vtP;F3y{4!Otg{>^dcsV94!
zRdZ?ukQPTDvRP->;Y$GS@4VWrZ9rO0e2;T~|J!46WA=FE9(zx8VS}%)e*A5jX6x!G
zcJK}C?8U4d0nt_WcHc=})Zpfgcdo?F76XbT=xS7AGm@Xrg2^t#P(V>Es+QNc3M>EF
zhbT5`(vLh!s;gSnYU{83lsz(iL{!Vfq1%GRcYhXIO-)!LyXk^3!$8?dY#GI?BBTYa
z<9PjB<9vT08;HmxLrqLgPo&i^NK)FFd#hMKN#>BC|3g4b0^2mlrfmvn62YMmhxjGV
zv7#=vc}4|3_p2nS$0khVd!BSIfDG?^Kb3)}-sFr{)$tj(Wb<&Pnfk;e$zGIi1Vq<m
z!|}A+cz(5vsM7mA3AkffZ4G<y`y$kbf03K554Dxbg0j*|dc-QHBX%9`7J-~}qyQeB
zAKJBux`|e0jfUpYF{QO!OF>6mq@;CLkA;)&8}XB{31XEb`syV+sxIajlHT1rftC~O
zh;ETP+>Syl%T6)Tc#`E|HLjiTd0U?uz**i~A4igJQ1<|<t?45VRfm@d49<_OX7RNQ
z8rR1RQ>s)=oO^@&hfMg5g3eer5pT#s_VFy7K$U)P0vj#Gz4#%Rg@MYL>88QD$kP!z
zcx?C|qi`b4=^^E}ae@Xi1{zT>n$Pr?ko#YKLUW_0;^$28w2EkyZ3-Q{3zs){@aj4%
z{9K~j5j8Xrt(~Y8*?kQmIfllYnDztaK_80FuTSV;b_@Q>!bRb(pBZPv3!#pN@qz8j
z7GoFBy3>=}!GnB-c0rXrMU!2<x4|`ILlLBW<r@Zz?yN<tR&-~m#0~K9YL`ym$;YgX
zpR`{$4Lz<9APJV)e)=F{IDAa~D-gPHX-9dtAa`scjJc7Rbmr?{y!qxQ`-nq$5Y``M
zd5yH3xw$Jr&$(;aeYP7azE{4Q$38m9Co&@~wOIF62EorwL|fd9G3f*?0ResOWvQ4Q
z5Trpn+q5T@d}T*u3i!aI@Nf_zORrd1{^?ums;3r0>tRLx@2N(u6YiHuh^ULfSO}?_
z_NjxG#@xttu&m0l*9g6Ve{~DZSZ)Mb2m|d6TnF38O~i6$u_0)iMN7ZeZL*ZXUA@c2
z)$1S`EUZ$@^4pd38R3zxgTrFzpy0F*eG+o<CtRR0b_2?^j*Vbq9UW53x*iTQMW7{f
z$RgivE!id`1-31_O&ODJ+u&$-yJ+fA<9-RaCHP!m6VuyOZqN;8&9ZJDv-|N$xVW9;
zZoQfws6po98}Ln<UHb+w8Hw;Q#eOGOJ?p%*u6BZ_z1;(4*OuT3lWwr~@+AmoiMH9U
zqD?@lXG9jw%p}!z8h9C?kHu1%42P<q=cuZTJG_@cN?v_X*cg}fwSDApk0&}Xh?8}i
z;8t<zLr*Wg3PSJw3`#Ll(@wN^pcDf$TQx|Nf*!tNvSPRpEjaAbbJgYUYR*M^zU8y~
zwmHYZX^=y{F~u`y0DAG8=palX-tF7k93a@otD<1v>SG`mFk3C}!CQbyzDQAHYA_Tv
z@S|%SpPZgvI2m$#{=X~j{U(C5n*aQ|yozsI`bX{$moj(O`(BhXfkr*}zV<Wyc4IO7
zUdXq2>yfoP=(4i-z~o&6M6$7xM5|jE_>>{l$N<S6uW~=~IzHX>NBKPwzhD1uIqK+B
za=y+1Q(%Hc3@z4SesG_>7Yu3R^<Z+$R_&7YTL_i2b~~skCEW`}fIBO3C;rH-ZV=sr
zSEs)c2cr5qt0TC|WX9v>d(76Gzdf7B-UKAC+nxndk^><Sa~)=DB|H0-Z&_IoLOLQ7
z=lNy-4<nw1ni~hqyt-&q>Uv*Vc0JDS%i{zV>8JSGTqHswyN5W3tT#)me(XK80af2`
zUd?o|YetmD_p$70D2GGfGpXm#W#!bB6VAj6ExmZjZ>%n6K>{5PK6?`jgjlCqL!5u~
z)k^2Fp=;TX8<Z1yfscQ{YujwF?bg!dgkC#6een&P&_yG{)|zQwsTKKf;GNM$<#UR$
zXh87nSFTxB3a<+hW%>S4P|r#0Wb0z@SjV1PURb4_d6@UlpI{SFPCz7w0$aJYZM_u1
zC!OV!^nRAfeG?oa>_hPoJUi9zmsx~qeEtI*zEo%P?hYP#w%Ur+Sx#U6>)&>3U;E;b
zRVS@?i)^jTzKc~50)d~GWT!upW>@hJfy`HnU*wi~9&Ntm72Xt4h>3UsseF&5z~QcQ
zbGhd0D!r63`@T!7D52hg?&`r+kqd7yWpWapbgFK*%bgP6@9g_S`r3x9<wgqpBOoY#
zy8b6La6z~|a`pTSPGGj~s;N&q&R^aEGzs@xbI<O;jS8gYVa(PEiZBbcCgKZsTO;>x
zm(~4lB`%0f?A?&K`Fg7B+&3O2<kxb4l5YkBW090B{pMLU#@0i-pNguA<F;z?8IdHo
z!!|p%q5a*U^L$@7UAm87?y{a%qzrtYTE5T^9l}F_;-*xXi&%pq^SF#cd!d|KV&IqX
za&Of0h9=}myFpBZ#uH$cML?S#1?_mUo7QV!y)u}@yWVySQN9Q$F%rZ9PfyxCJe;5;
ztB}tsNt+T=z{^h#S|svbk*;RZRE0w)*22!pTXcmHWX|)e*Gw*n2<X*0p9B|1KhK&E
z&IpJ_B*UO01}4c<hPZt|EKUzKf<A7j2azXY%$Swc(6XDpS}%!mD@>D?4EqMhwtj;f
z^D2yl-v*mG-VPq%%P7aA>=(1>hujp~%?zgL1K1U}-HN=><oOA?gFw&8ImmsClz14(
zX?1zv8LC1WRBqnfMuM`>(`53s+uU?{6p0l*kx4@$jAEyT>}dwZC<x0hK^_{<FvolM
zU9dR~jmW*_GpK({JjP9Jo<m-qlYDI{qx>L(+##?dSCd0YknS+hRb%MZ<kIM}pU8S;
zA`-_wTAnsX>!N~m$9ML2P>c%rn8oZ;rSGaaju|}?ROVf4`aT=Ewwbv_h_rFvwhi=1
zwr+V&IIphF&1eZqo?<LSjsoIgud_f<VCjW+q0h;J`(C`eBJxZ|l5x*1Us!$YrHt<T
z4v5)HyBp&hMA*%Nj1%m%G=#Ik3_>l@HKz#+xx>H+MIdI)1GY~;50Bl|9eb{yrX{40
zX>`|OMz}%ojha`uU%SeMpPrljc5VJ0ty+2x$=YdkAo9SYIm}V3x>*Gh#^l}{AWL6|
zu=oQnOsq^Z{dm#^&-Th4c@L!dBnwFKO6vU(5O`xV-5K2ppSRnoY6it^VsD<?n<qcV
z6=$riZfb=TLw3m`HD0a?)_Im41N=h)tF0KtE$OYK+%65Pt=oD@!kt@4Zkr&D+T5}H
zklCel3+~^(%q`VZJ`4Z#2%oMwLJ^$fA^D$E{P9w)tX5z}7XwU5SN!o2%gAfBRWKgZ
z$~Q{q<4?H=B9?KIlrv`+vx!+!2yXYTsI#Nme>ej2SWN#dpY_JrFv4q=BoCIN!&SVL
z`9m+z70UcL421leQkILYR`D_;GuQCkdNiH&sfZ1+A!6}5dDsP7l<$o`vz54u>1bNZ
zw%)j6-Rbz@rck0j7+7sRdfAI7OeK79QpG6wrF*9O`m9B$!KLR(HWe(BKFQ`s3l{@h
zTP3gOcNmEOu$Rr-M%JnOqI>Xv$yb%CcsNfS)~<1kMrptB?07{<r8BGJ`NQ9OnMoFY
z;nl8)AX&*-cHNb%h_lD%Bw1YDy4JbRywxqA{0K7>B9R%`4H+k1DKrcU4y^s{EGscv
z%jd4tBxC~!66MA9nl-S;c@sC>vDHnMJ!Q7q90BBBNhlH(*tDBB{<PoJi_J1y^(O1d
zDyRJ4eQv$lY^}gE7sl6=Z5fq%II#KXIM(t9(FXT;{_{U<<er=Z@7g+<twAU<v8mBm
zPfx3CeaSFexvd_WOCpcdn|KK>d(l<x>U_Wd&O2tdc4KzAPdz=^s;{mh?$|x^oW)gV
zh2DwJA7hV802@x8Fp`?p)-Zi1E2ImKh3|2Wn_Yc2GZG13-nuav#BCH*=l?~XVYXJ~
z{FIyXM$Wx6kSwt6B`Qoc9Rg~RUCr+zzsSr2S6zT0dp3c;H2CaR{99S9%xuM<ul-H-
z*kT2iV7&X2aZ_(vhi=jx=(O3gmg|e~;kE!lyFGH5t*tUtna=%{!e-hB*iGiq>9nIH
z@<7B;FK0+)2;B7HiL}ryDzL9gB(Gh4^83zW_{Q9-0(!UA1S+dpA3zk@`LQzVohm<<
zhn&IG$0FxtZHUy=pS!0@OK6ybFP)0RqL}l^ma>JrVmN@%AAsK%z3v{QP7qdy&Mc@y
z=|ihpOwno$4Pp$rd^1hSB%***=pK#h>>2bzcKfLm+81JnRPZv;c&i<BD0hOX_e;^u
zHN+i3kH|pK<?!ISf1tJ;C~gbYiDnGk4u#u@*8TAIJrcYI659Z;fI{ZM<cqK`RC+uK
zysKTW*M<&qquvXQtD%jzyQ2;C-HCpDA9b)t60B#DQMKD!9gou~TGB2;XX;yYHd3Bc
zO2k+<H$5$bsU|{59Fo>7-9eXotp}5W6R}Sz!KNdk2GYgk&*lbjv>gNjvBWR-#o0k|
zV1Op{0F|2$F!WhN{osyNR?Cpu8(ex5*Fa4$@>BlKUFkmNo&k|#{Syr7v8tE`W@933
z!~40>8bd|D*^$+hbh48$T2PJh(C`c<lUT8I+3)-MR);v9Ty!rHx2S0?Yl>Y$o*y$#
z34Df7r{y1A4Ca`mv8VOwC1oCzRi&z)YfIKPTZmMF4YaqmPvJBtF%aL<?QxYL1}^f1
zfTMt*uSgy!_jEx7evzLV(A1n<lcj3SBVqLJfhL7wR}9CZio-;)L5xu@i5C03En>e*
z&<?!Vs=>=D_#cOBVUZ?UV(zk*Uu->%>s{Vrn$FXLp+%b8PrU=XPoN=;d!oEBydTh(
zvArom++()p!G#r(Z%byOLtISL)QQX^jOIrlN@?P_ZxaW3RARNWbp<NkiCxkw?|tAS
zr(zU+!Yppg544Y#Y9_Y6VJ;1#3Y>I)^owFao1Yz2vS!<JCgsTM%Iz8&#;+6pa&Ro&
zentlkF>}v!N&^_a7?zEC<NMb%T5|1_KAo{P_6p-}k{A@51B{hzC-2vP!)afKjqVdq
zUKaG7o6f)?l(%8ePP=p0x-m<2I}4*gwQwz^?ZedtbJ0b4S)2`#O~MA_{n%lit?N+B
z@jPUY1kUQPJdS$*Xl-dOTpG!C&ZYtlq0&|E18&&{j$TynN_8CZE~wtGivMpFvOm0I
zYx2JDBY0!(iP_9}>#C`Lv@{xG?WP|s%N`#kj~bUg)!y{@l^%m+;qI+5FSC_qcnG-j
zzGCugeAg(}Z*;w57&<`EMTV~}W8r`L*atDZFD~&^dQ})FlT0gdC+9Aby{*4Ov!Vlx
zu|~5))hes4lc&Gw^qm`?ue{p|+^x$qr)aoecV$!nYq|2ce(mV2Z88c3WQE1fv$UbL
z$6VAV;W=slFtBhDa|!FTJo+t4`Sj1Jshli487TD!eu}!fz&wo5U~H4HXW#Wo0O2O8
z_5AOAFY^!hqmeA!5incnwtvE9FWfhI*5{|vT;bXK#x+=B0DmD%uXf-c0zLPh-_Gg`
zvo*YMy?ZuHzHCFaDTunjsyO_zr&1`nZb_M~oX#v%yIkHxfQX7PvlYTgO++{<B2w#S
z+9_LX^Sf-a!nhG024=Rpdwz;R7}*Y3%Te+an5`}-y=99VpXK9(%Ea>%N&ehV^OkT#
z2>uUQrxa)A!c5p$<P52aSHzRNa7|i&f*l>=u)2Qb6+KN1o$T|B#Jjitb%-LQqHZ<`
z`_-#nN+R}{USN}Oyz{#&=P!(xZtdeqXZKjC@PG1;y?Bg->hz0eSI%PVx%*C5){-qr
z(^tx0YOVAy02fKq+JJiBqaKT&@3XN8bq_#ZV=&`Jy;JJ(n8GI=m1M81f*%bvwOQRv
zheEdcyiPL=QaK`voBRZ=Jnju?*JHwR&9|<hs|&G@IFu*r{Y~tB+1W4rq~Bg1o?lL>
z?^|-2-^J6r^OLJFe}jz}so#^NL#`9m8(kLvdzBUE$2JyvbZoA}bYj%pqd>|8mg1bX
zkrWzo_3r&Nt&bngOYEm25qeXsn(bd4&}S*#hQvlA)P{TFxe;*#SX(}{Rup||!HGau
zp;=1aMjYe|%(9BtddiJz8l<GM-D54rTpG+y=n|Y^E^Q}vbSMT)3I36FDdU8HOL4yy
z2QPEQZZjBe;9>>JJeXkrcm$q6-eVtm<ny9aX8j3iI!G;DRQ2lLmoo~U*A51V!oUz=
zw;t)q_UPdtzOV_3%T<Y8Mk^9a#U6Z3wI=NPEHyT?L6YN+>jRj19kw$-*pJ)mk)d#w
z=N#n9cqc@*RvL!&%V3_|ElH-GFe}UAI|Gam9q;6xrO?O7BMv4fyxcG31Tl+>Wwn()
z+bx~Lui;Gfh9+i7O6JQh`Fsr~Fq_*yz^ex<ArCV%BQgM0#=S*UOh*?*shWG9%P81{
zIw}cbFt9^R%>x3exnAJ%VSWqZs;L#-MS-7E<Y5Vqh?Q+T%LNO7KjTGc2#{@N+?nBa
z=PX+|0%V&-HF(XtlC9=%E+N~JAbgR}a_k23<s*Vt(1evBqu}KblmVt5k20(_xj4z3
zr1niF*-p$F(UuO^OiDGnC`qIyuaAzcId3e(SulAKl4K?<h>`GeQNq-#i#!4OKyg54
zo}GVgoIJ`%<Vbio>n{+6j24^+)sT0Bj6ZP>3TPh5s!nRu-Q3e4&$c;okcKN_OsO=a
z*RH#OAj84KJt|uYA@z31PLQ#G(d1FU^o|o1D1uL!h>$sTrByT2O<%Z(e>BuD;eMdS
zOFW9ep8iEk1S)aRn<-wX0gOn2aek(d36?|Ex;L{W-Cd=7C^+7PCxu9o8p&W1)ftz(
zQZ0=FZU_}ONrtEGt&~om!|>P}=;&y18or}}j*|%=A9zS)#~1;^-jZp)|1`f^%Huc|
zBB~JS!ITA6>Ep~9RG~kH^o84kglwg&q!@({hGVW2_dumJ*(PaOWs~xd2T-<Wc#uc+
z^b2vW+QM~`?0!tgKnFhd5|@<_#K_LwT(Lu;b}~zfeBRAz>(ZL`F`xi4AwrqVyCZ%J
zm$Ee&jfA>c6-A0lrI1dUBN<0T6m=Z)ZsK<LM74#v=U8`|I^!<w*63mE82ex@LLQIQ
z#RTbw!<Gy2NGK*wxp4&WE`yh<xCL4Zng)bilxH|p7VULK7%OB@0FW@^5O+kV^hy-@
zxvnl!r?Rd2S+-uD;h?^&k#7fgkjmEci~Nk8+`Zsqi}Uh`%V>a#e@!e^p~+!KBHfM$
zK-*}d;-y?K&%W74#faoPfQFF-2z!#*h)oR7@=G<ghh{IrdvIbH`B6*em{?+wsX&AR
zj#Z)DXzDi_1%aqbAx!`K7{VL?=_%PpQl{V&hX~HMc)M}MQX*7(whuxa3>?0+OXOC;
zw4PUb>l}748Wo5VMiTW}%56oXMDIb9g()=PerKQ!FG&+Ao!Y<UIPHRR<N<5>r`Q9p
zi^S-WxB#ypX_|*iFIt2iW3Gvy>+J+GxgLq9BR)MoI?-iO*8DWTo@IL&4J+HrJ(G8N
z<c&@OZMJybc)19Vm`XQ^<E1B2HI2ETbisKrQS=4hw(x7_Rd5K5MR<{T7MgxLCa;1p
z5xmbxq#|0(K(;y07t2=BEd+>TMrlkkDZG$mF2e_^2*DV)<OjQSf?mlR$U^IBF}QpW
zKvEtK9#T2gwMw#@Ewt2+fp6R<;{Fs=g`7v~iGZh?2+4Ac3h*-s($XOyibi|w)PMI=
zcilZ22lvAgPoSsvAV_n(>(SM9SCmjAAf};Wld?0IU3#Q!r;pj0Qm-;!CltqI7c26Z
zQ0mz{0oI@0*;WWo;1-apHJ7Moic7M}cMwEcOynI|nuYF;1itk&Zj8>@?LzMx)CsOF
z%p+`4VvE^!Ly&M}KLA~-!?&1~){-tqm%_4%;?&S?$Zvq)p2se~K^S8Wcrc9LuX4#O
zeJjE)iv5EPv4#U7ZRVhI8aQc@p$!hWwIRJQZT;cx8iLVv$DVubMiNzyf!8RQvE68(
z*d-;rR)reOVIbw|RTW3N=Z(e&BKGzE*Rd?q(u-|-`Fz$2%_q1MgPawW%sn}_#tKiy
z=d!(XTTEj!I~Lr9pCzOw#v!Gyr$c6}Qsf*47RP9s+HLcvvx)q8HtD{c&AZ;6{p3E)
zA3l|)t^#<8Rk@8j(bi`9fCz<YYD>Wbfv#Nx>D!@wD;-qt`=dx1M@#zxjKhg}JC$mn
zD&8j2UvewTrTm<BoGZ6Qt{0Ay;Qb7*A3wh2!vE9=u{gHz8A_Gs&lmH|ie}t{BY_p4
z>rO7jV{SG3SG$O%RL?K+v3T2Awkv-B;Hihpu>8bW&ZK(bPJb>K6(uM*Z<LDTpM{*G
zr@uAF=^IC)?WOY<*HG+>RjAj{64_R^ws7qYX#f)1ma%_^!g_0v`ebFPZ%3X!2SY%6
z<=*{)aUagZSM`K)^(Gg4ac0A&r?*y5u+HGgZ}B*OhrUcB{ioD;MgY8C#^)|S#B=2S
z%kzahrq*sGMHOi}N_nHF#j?xHcs_w5RW|3RF7t8xSY=Ov?(eWi(<FOh!^Ib=;g8&&
zXSaPh+ZcQL(&7y&dHSNs-*qKlgb17Uacc(PheCe#v*YfLhxF3O-+>Sr`e5s5glu0O
zYb@P<%rMWfU!8S}7x-i)tb)G$2t>TO73m^aDZ4$nWaW~}^GXXjRxexOvMep%DUtRc
zl5KgI)@jXSzUBV5|0V;Ul|i+V*D;#>8l9_(W@=K@os7+>z%t^`|I&{-->qL(#(#Hw
zHIZy_LmdXRS~P8oLNB^dKkx(A0LvAZ1*KNRVyx!uc`uB{rSZbAuDSY~M~d>E*(@x6
zBJbHlro0Dn-DO30j5Wfm{*YVVv7R_}J<Whp75B2dBb|M-IZ$2fhe7`EXRitqw@{1|
zck$K?r2P_gCoJK^wy&<9I#eq`?AN=Ghd)uj4)nJfrWV^_2V*B4`=qWCIC193G0&M8
zRZm3cN#<lr831kPBU@4&252kUBM{bO%s%|OQs~9Is1sy@`zpQ1E>J5o2)=h&UOUfo
z{(_zzf{V!+eH9@c@f%pS=lwuhk&7>>qHX!M2r5I(sR4P%>nn<K^1qOi$`x0=#np~i
zHPoYw!)+nHCoIqo^Nv-9c72{Z8*_WSOtHn(QVhL>ZvOc@(7^TQZ|pr8FYKaii!RrP
zU6BU`eSvlJz`n7S1kdOPVaH>&0d{5t8)gNnS-5_uYx!;m8~Xj72s-9w>Ei1%-=CP#
z>43J`_R03sjroi-N)Dpm7vE5CP$rXlc@EdJ?%gm?okMC-+wH3MVpj7cm$|p3fafRT
zjSiEg8_TZll)P<h^Be{9qOyx4(P@MUW)ye`?&xwE4tXG+N*N6`LeTOO#LS1rn;gpK
z@x_Q_vW#7qkEE+fE-Jt+yJYbe;5jEUHx(^7{1OyRwwy8$dXa3EvdK&lC2B&AKoc`i
z8taawwnb;MKoq6p(NIXw-9%Tk3%p+Qlghs9f}*BRQ)*k`P)JaO61yh((>3CdCCOIl
zbnZkUS{B-1@|FD&N%N6NjNo{f4{4!9dO2l#Fqnu$`=qIZ2`#4Eu!{;kx4rE!C@dDH
zu-Z}N9obqus_&?{R^%zSJl`cSPyq_<0~@(cBrsUxy82ubkki!#vvp^ioJeocDlWlQ
zNLE~FRz-_CgloB`7Rm4x7M?`vBUQA(BM}0>sCAy5(C<bICJiVov&sgwKHggJx=>^{
zR&?P<xSb){POQ#oXGyl>27NrlgSY#J24oS@t~*q2m_uJqHn$!LDAj6{F3P=*pE&m=
ziv;=*<ohJQC{OKz8~}9<2UxZ=6uW6TJCZE=ewGb>%<mvTrj=7!RJZpXfXdRJgY*PQ
z9=OXkXrF4)m2g&Kxe2%nXKK7sdbpX(3Z0i{h!<4wuYj17f~fflvvpY|v%*DUsC4J<
zm1hKWJWo0gQKWt`a|{qJsp(=0Ga5N8l<vQtNNGtC-0!7HBm9&Gs4vN$#>w5q$%+qe
zsiks1ZH?3UKJV6VjBgZC16x<q;2)_%y1!fO{;mytHCjrw*T@ZR=^pXU^{(HUtcY$l
z?nIr-V;(NAJ{{=*H3;%MqYnthBgGBw_F|>nnx#;xBET1nySZy4mQ&_F#^9%Esfq-q
zy)a2q%vKlv6J!RL<m2&%z_$yIXPw>)pnj36SScbO`16D)PPd$zNnQ&dcv-+~{okJE
zL%-Q?^=YK+=ydhMt^J%eLwQF5qw@PyolMHAl&4?#Wn+=C_Y47T_gF@Rz9As<BWjEI
zGW!pM$H*xoMp-}GIQH6U$9BGAiG(9T+?Tg5!)E7UT)h~gvPW6D4n7?;TU}2PQ$D7$
zL1N7&IIQgVu+4sR?I>Tcc%z9y+)(fmSZ{@G&Rra%GL1Ov#G|P*pL%UP-E%Y(Zp<nw
zQY!87bd+SKknZo0`w#zOs^rL^-Tl2Ac*cL356ZlEGR&-gKf=%DE*ra5>(R_t+yXCg
z83Az(v(-IBr_tMOwxXD#QU9S>Sx)iTYdjywL~IrE)Qcv<x}xOM;XGaudTq}3(v4l7
zhh(<Cmv3MGqf7Fx>Vp!53qM9{QX<c96!eUcY^UMQhE2<UQ>hxW^=Xrb$}a;*e`gg7
zsVV9ol9}E&k?gZqc}Zp@M2?33CP(RM4SKaMl4n6_-}3gD?n!IW<fInOw971GD!Pwi
zi*IB-ScL4l<5i}vJpAK1ckjP@oiDHaI!hiGelg~s`=|MapSae2B0HUUum0U@=-o!a
zeDLATKOVxJ)3Lm;m=|$Z0;cwOP;RLr4hg>ZPoR89Lmj?HB^rQ7l610XPs%u4eBY0w
z3d~kvs_coX7P0axis|o?pN&?@8F}rHZB$*&W8it*)Ig52S$MbEN~{JSDJMG{HU1=%
zP1Bdtt>}Q7Ljy%nj~xbfo3rtyDfHImncs)gBjYZw-w?90B)3)O5I6O1w&1T_>pAVK
z$LCr&jIfK%ckw0~-=madc|Nt2>|cbM+i(<6xTknU^L}5vJkGm%A9AbG@1UU6o8M*=
zTEB7N;)5~7v|CD4Mi6_nRUesfOvu0JH4ZZ9^NQ?dio00OWb|e&gw|sXD)vK%@lb{8
z@q;ynz}}gqv|U@_#a#?c2?;l^bk5VT&_~(nfSp7;8&{=9Ro+&(IdDub6TLtyw5CEs
zSR%90K;iCKre|2P#=D1p%xkdIAMEXk--D>#hJ#hGh&Z@|Mi?Zb4I-_|!qZ}*+uSuS
z3eC+%L<2L;L4l^~7P+sRZal2hn4;mH)1;+{RsMPN427krZO^ufqfrJ;wj<wn01<)J
zhD~*PsJp<gq>EK4JiiTo17PgOeAbK~)5~XMIv0(oh|FP1NsRn@t$d|1b@N7%UFy~r
z%{TN?cIW`;{My#gC#L1}fjNRhuxiM=DjPgaRW+^^1$PJ3O~{S{J)5=78ujPWh+u(+
z{M^2YQ~bbnJ^3e<EwK75&7YJJf8gixc7UvaKy06rC$zaaP2~_#qK$C4T$NtX*Ugk$
zuPtdc+j8)iKwz~l%AkvLeg#xmY*eh~u;O78^PFl$alV%!J1^}KGsV8WE@}D@rI-=W
za}Q2TxVdG>W?Irsd14!C+<xhI;r9*3L98DP$lpp8EF#rJ6(xd!Cc_&D>!y)cx8Z}_
zI1thJ?WhK!EnMtbZDrJ~*g^1tUH0iL{Xz7h{n2hKs*vfO(4_ikpsB=q4-Xnot5MrY
zkpd5Kuim5XjIYaO&rtoO3yyAQ&UBU&>~eDPYMXQq+ZLhodXj%RP$oMj2toKCge^X)
zcX)V&b*6eO^Xb@?v`?Z*9pqAKGPt<xB&I&vxZ!^PQOmK;7<_C)?^0*N?UH7jV3%)|
z*E$;7Czsl|+ubAFg+01~25Q_`(A)b4(Kwq7yL+13WvJ2UWGBJCAp~AvRO#}qHQ2t!
ziWIRGtsd&MV4-K`piaMiX_@t|(e?=7b0?^}|CELGKbUvZXD-QK+51)Za`*U=?0%+h
zLilSe2UM?w?(Ig+Ci6REdtWq|{hT7_y!?~D<gbVOw%M8}m9OU)ul=juy3~Xoat*{`
zTLc^SKXb}6mZx0;w6DnXxd;kS_8fb_M+J)4mDOU8L-kc5YnY3?@07B2AHI6|Ml>>T
z`zpac5Wp#)&>lkhJ>OD}&ZYs7XX~Ex%yN)zR3^W`&pqb-IWLbSv$W@kf6IByR;o2B
zW+W68p+3$8;fL~k{vx|A{^~1rbGpvv(Zu1QZ>*aF?KX+xr?Peb?-M?L<0f~bvc+u8
z-LGC<#myJo+08F98}y|c^6oAFA}d|C!K3+auDiPzq_Ar;(@=ch@!~V$G!#zxy#4`R
z&nj*X(=uDJleYnGCeY(r_LM*)VF3!g`sUG$>2%{O#t;D$2O^}&Xe)<zEAY#&FFo5|
zbDOjaB-KN4S<7Q-trQpka8S0APwSG_L#_UeJCuTK<1NQ-<JF>p)z*b&MU632qbi6B
zDDC<C_;TyNe!aGh(LVT%govPBCT*h@RZn8JMiPR%XCV|mDEY*F(JijwX?a=;{rhKW
zI}3Mevpv(r4;Dp!;&|yk_UF}X{lxdX?2fBl`M3XIGOqv3e6bG6rk6bTzBK=YxZFK6
zHdsYq_5q$~q5IiMm!13&1BSa?7WW}a%bxp2?1QXob+V~F1lM^fy+A5fSDqHq%Au%M
z-c8^4XR~dDbd&mN*ILVyqsx&}PqLP45UTr<hilk+d)di$o2_N%rqCym=O|ylrEeMQ
z-M9liBJhRyr&%qt^-guf3F4-E)~f~phN6Li50zuk(=|p0>BUpIVFG3=XR+|L&+2ii
z`Q4?zv_9sS<9pD<Tv`zlVbI4aQ;M%2b3ANEK<<{^=ieNP=_5-gdh_<dmHko_4bT1J
z_Q5T*I3$U!zbR=OY+Q!=>+;6H#q+EA1%3i+(ALyb_z>5S3h!11Xk&!+ybzLMQ69W|
z8q106CVB1)-S9BFQ5Rm2PEd9Fq#-t5<rVT1JNVV$B0qy3S7M9MwIKZz`SUTj(7eji
zV9i<4b<EAGA&dl!;XAr0_vk$>>F&l55F@sc!`;H7w=1x4=lcWS9VsLIf)t3^N^>3y
z?6@JMgoV)hF*FZyWO<H&lr5cJ$krjP`*ml5g(9B__y(cd1X9mJ0dr-xDAS{XmS-E@
z>js`(O5c7J(Cl#|OJ=LQri$IHe8%aNDsSrkqjNsT&ySC*KPW+%(;(5uK&Eys*1>r3
z$jv!0WH^x6U+SWWeBiPo-vId5uV!~R=pvtl?1=oUcJrC^g%_fQr}2o&?j6ilbVH%?
zBLk0tjMY}l*62h#1VTTK!pCR$fzT>~AOy@-Ybn9Pc8TkKzp#ND#PbD<XX-xs5FQUr
z7}QNji7E}~JrT_2SEi1H*EME~9SP$VXq<eu!Yebi5VuVe)-6Y(z017Y0Rxj`JMaSm
z-zg?SsZGMx7Ct!;C2!EB*5z<u;=E*Y;Q3^l-B*y<XGwIdQ^<RYhH+*PlG9X93haB$
z>bL`M28ABnJhu5oCe%G{f{Eme`6jHL6Dod;y7kuk*pVLC2Z*e}v?Yw-*gWGTvm*Iz
zZ+j+;FgX|fq;M8w-5Rdds9d`nn$dsIR6-G{8<88(S9do$ZRkMvyq1iD+S~GK?z~Bp
zh^>N>cY$M97UZ>>Pq_WBUg+PYpTIHwOgzc(U&xz4HRBlt1E;-sdB)wB@NA7YHTl(7
z+1j#V7%{ya9_%b`47`Ng@9JA5n}h?_G85!y4aexMV0SYUamPYZ&BeA1w*<2$D@*!_
zcX`O}be(G$m^@!ZAybTe2Z1=oBe8H_@@$1;MX!OF9wcOad){>!?|lpcUw53HqpHvW
z$@9-;t2HY%Y8K%nV=u=h;j>fcui&^t-v5n1IO{Z8n&pcjM7dt+k7Tn_?@-7gKJ(fl
zX0JF=xPO&a%sfrRMUtsL2=Fq>&&API3ZcP`Kb9>8d`QJ=>$jHIgk=LMYh{%c#VNv;
z`xL{HSm`e^T$b2%{AiK2*~Uk&atlgyD3I>hPMfnCHHdqi(aSt=tkmx2eC7PLsmUwb
z4e^^^EW2JFsmK;&Kg$U7%|9I-TXE;kD&{bN*~+l)b?E3KjKmA5dS<pp>{(3;VymeP
zQBjnw@{UIhq_)Qtvz1$lN`)kDVzskLxb%x(8-LD!^ocV5n;+yr;QPkhowj2Y(#_w!
zqF5HEp-{Pp>d#D6?w*(NWWj8eWGILcIAH3>ZS6<lMuIo9RfXg**{EetpwGc8L|lI3
zPlY@!Rf3SR&5-T>$M4D~+Y)TN{8Cq=hqERO6vH65#&D56D{!AW^}Z}ZZP_AEweYp<
zX_<S|k|z-3$LQbs$|i$iQS-@<avId?4`k;}GRQ_jcp&_UKPrLm|6It|AXn?sSL=h4
z5@8#tPFR~W441`oO;;w7UrpZ<f9;r0`-nfo+wdRx9zJjMb+B>Tmyi9o;+#J*CbKoW
z7cS>kzj}xB;xrW2F<bu&<$2Rgbe+54wJ-G+8aWi4V$em$7jyNu^oZ$g4W2f;IppyR
zL|$x}-Y(D8Y+~9VCwii28GdzE4eJnasx9dwb}PmUEb_u(UWV@^@?_0wYbeO%eq-3V
zX=w-JGK@p^>?OR9a5-IGU$PxUI|DUYV759<crL_u5dxCLsz!hwdOrD@t2Dw+|Mez_
z6Yrs;TDZErV5m>$bBi@QWms)p1TpLCkGL{!cr#lg7@vQ9O0(7@pjf<r?VD$V`})g@
z5T9(M*_}q;uRI`X7ilU~G;H$wwuDY{4nPP=zuY~|7^bJ#HI&<jeA{H`<M#8UtoFvR
zCgZ&G9?iRY2N5S14CF(~NLze}7elH>7{8a>ZVV(8&Ij-rYXortkA^^$sM2*+7aP1;
zP@zH>S0fQ10q|rwyXtMLJhzqC(BkB?h!YY;Ok}XNj6lu?B^(MqFIcjg?Jx>o6X9uo
zUY;EwQTvkZh}j!ZS^U%l^o1+Rc#s4!!?Y`6;Y2`Tl?A{D=!0|7&svB@NK5Zi=rGsx
zDrwBBWl@W(H0k-ikix)bavn_1_BH0wliOT_iQ6&5eAr-XWtVz%V=fC&Mt(qUjic*|
zHHqN7E&`f?pzyjjMRz^$Nvt9+1;dWT3d>d}?9UYEVWD)<5_7p%iAMsbbSYUOeqoS$
zkwW?w(f727gIoyhSkaE!X{*dWF{SqsucqGb!wvjgPgx6SsVNB$yKN{s+x~-m%xX}0
z_?Q|+g<pfOZ3$*5Wvx-QRIc{h0Bc|*W4m=%_5>9ZtqsREewZ7@>o$J>fb15qj{^P;
zuI&Dn1PugatK~<U^^MG{{aS34E(~h!oM<!3SpAvZngk(=M5_;&U{^c$mdXd0;jl`w
zBBm<!)|Bbjx1s;u!#3*BzSvUksuUX=EHZq&aS4i}qUx7zPry3iZS^RAKUm&Is>oJs
zQb`3Z#DW<d1x%bqrbWWRMy1H0fWZ_u394*DLmf|SOcaTwnyTPrnm00kfSnfTjdZR=
z3I*%|vp!I^se+z7iL5J+VUHu=wFj<sD-*Bai~`z)HEeiD8F?#Y6z3n~rrCl=eNVuC
zwBa1sA>b8<nK)fvLK&_M-R)08rc}klS5Sw1CS&6BNw!im<mDC_soe`y$5zi>cawT#
zz^ci7`(Gq__6X{#(FM@ZM+x3fJMOd?|9rvdM#kaoEEs)(bz!_8%U?<Ub_Dy?7<^BC
z#B{r(twFUHAj@Ao;vS|53sY|!i<#-kMOTi+|BtozfzRzI?>pz5_el3#S+<X4*$D5o
zJ(7hH#tFiP)DQ<ovH;mQL3XZ#Lk)fLx{m9#-J67@m&G(AS%5HXBV32v(6o7Rz1_=g
z+Fla6A2;Q*pJU^6P1n17p`_c*cK0K?gb$%9t8|^kq1j}=zh};QC0$?Xea&Yd={+;^
z%ri63JoERNnKNgm`xm@Iq{1#Xm)GPf9255ZI9czFx!~?kGLR3PWfb<?+$;T?dR&&E
zqIl4}%i=U`fO%X|oFPp73t=#4RDh9l>DH?`c3b0&zb_@_N$8TddepH+(^RB>2saqY
zp9_30@R8;&(r=pJoFWxB+db}~l|FFuS1-yVh>B}Or)N-Gr9dMQVR(3c(siwAr&1Q?
z0Px_CKJ3`5xmDswwVEVzRIGwzi#x!TOI$3w^{b56HE(F5QC9xH&RqT{oXh=<pNOuT
z<wx}akD~hHh7ZCFg!rdNg1#H#7T$YVE{#rb^Ljb=(fi)+I^<+)2DU~fo>UJ@-TSrA
z2IudFH8#yQ$A0FsloKG9r@vE%m|x=E#=|bZk*`jScgD-p>dc<I@uI4{>vDHm`@nVm
zjxcy0Np}-J{m~@KCw>ZXeqzicMU!myvCH#S344v7p=2Hk9$$t1!tWz2m~RWDueQ#M
zKuZ(HUVK~m&TSeOWxS|FOl=L4=#lsO{@|u_)q}w^_5869dFMsCH(9wYFS5-1QeHeq
zEe&5_>{8XL{vK!NIgju3r5;;Outk&L^2OuSkAXmG^fm7*zdKe(aSxpOqmHk?@Gf3h
zz`;j1T)b#C4?$k*RpG7vp5_w0;s)ovuwwbSJ6v8n4x#XFt2_1QW7WC;?rQgGG5>|$
zBGuq}A5_NS_>m+o><0r0ubv?;F|c}DwivUkb_bOcKN1cOc|o742Alnk@9rbm&Kh-5
z*t!#PKH9rr${{@>GYtW+(DRJ$-22R_9L0T~sxb709?T^=y?Y?u1H`2|6k3#@?s1P+
zJQ7|09%M(d^EyE9{)}O0RiZwLgHF6yh@{+XhPHt(Xa<$WPV!py4~9+65rqq{3`PEE
zs?t7f!~UubCq3oJf;n}>?)J@Do(a0&2rM@6d-li5`QBTqUh!wy?WzGTTXkORhY4u0
z1HqDL3DKO(toqcRKtZDY{vcd9m@>nP1-~GRpv(i$4Sp@I%9MwutEs@IP@*^hvZ6@q
zo^I|u3NJVPu<MSe`dWRQ*Mbq3aJB34lvTYJujD$U&Rj?7$$v03=NY3{$1ko6=R8+U
zlAXnnf@5@9?X~#u-M!XsA)UZURC>ld<#fe6mg&*S7O`k$W(y<Lm{qe4@erYJ=~n3(
zLhI=6@$fBjICC`a-;1JKw`?gIYtd)3YWyQbq%gqT&Tl$qA#P$p28Efj3vwhq0N8w~
z>1`;iU6@bY2Vvx~xj;-YTd><Vd^bgk^nr8yOwnAxQaK;Qtj9hO<|!wlby7^MShuiy
zoEU3LRY0;7j%>`Xrd=kB{DLffV6kdcZ@`XGevo9jj%LG$ffO%`?(IrY=Ya-7n}sfv
zlUb_2O`uPvVRc{>eFEiB(DBAl%as!|U4B`omwaj*oQ+G&Qli*e;Jx8o^xC%ZhHT~2
zQoO`OG3dILGML2rzHx&Xs{W4iw3~HxqqcIDZGw!Fri>A02U<yQjnSekg2y@lJoDKi
zIzh#;9A?(s1y7zL1x8C8`&s$K%zK#zIufl9?y~q5wacaS_JGR2$%0>IXbN-P<ZA+0
zp=z3Qe=hfg?^`|9Oj%fP<59@XGFHWIFnH~gz6^_ZWNe-QSPWz~70yRtN(#08rjxl-
zniPW|TTf={n)^l2A`djrFaCHwrE&w&w%^SnGbvKdEu+4nxB7N|*n`~ts5s^wnoUUM
z->XkmMjL2sWyBqXlYsglUoV#eIXDVAbx?6vsET0^ZI{b7`)Mk~!C=AhUZDp_v13Me
z{W^29-Oa)P@^FZ)_rH60V!d@c4%X>itEs1GSU?=zq;>FO=saK2aK#tiiN>)*hPtDC
z4DJ_#j>HwCsI7P8Cl{5;!y%G!ZeCg{7djG8>gHK}NZ;!KLCkR~d>G3ujG*6`LH@UZ
z-u?(v9$It8drnpT2$-u~mnR=68^IU^N(({>FS_6DlyJH(dtP?R$*H$B!8JF^o-dXg
zr^`w(1!}8vcegl20F-k_oOLcN<ubdwl9q5%Z^v>oBYVh4b$r>KK<8G9heGLQM;5Mi
zOKaDYpZ}S@$dXGz;thYp?Y_=P9*RSwlBb%BGW*cVks=^VLtq3H2i`6WZu{(Y_Nk`o
zsqZaiXgy(R<4w_hV4D-R)r;QQbv>8-m&{G|7A1i;wU1^+MJxvbQ>^md59TY2d@iu<
z*`ui6|AWCo2kcpXjJe0x>FCCfFdO-s>;deM$bb69(w0n?wmGPrzqNFKXC0E$408j4
z(2-AFNG|@3AGs`4pFpLcQlYlSc<L421ZGMqZ+V7@SFiYN=4Q?i@J@<vg<=h09g?z%
z)LQp1Ri?Giu4Y`RbyegVE9OoUqoJ^Slz!L6j~>6g^a^t*P;X9sW~6XWUhh^sYO5uu
z5P{#)y(ITdE?B6Kq!Zcl7z8z$Tt4wa7OYO`6;|LB0%*^4*XD8TuVijjA8mx+{N~d|
zn7;SJi;H(cCynwaRX?IaYVUR+^q{!p`mCCxGB72wW9AAZZMkR;ExT;y*Qp`Y5+y51
zrj7iO8`O<t)vHv-T28owkw@An&cP7=ti!|^MRWR3$Evty^TKlc4_w~;{AIyv*z~V3
zgqBMVfdK1OnNK~Nv8y1p^^MMXVU^T94>L8~?)dBovArkG<ne`9M>pQ{`2+uOB35vw
zv0LR5hT+Vk-#Xg|-eRtD>T}mPGEH+KiZ>it7}0B|N4JNGhyc6r)wN}F@S<q3w?89p
zgR=hl#V@FpOm%4&@jpdae!a;W7u`$?MLphH4>P0Vd<+ZZbn`9rWP$OrjUn%S8qC%F
zp0`SiMIEtDv8_6Pr>U*lAnv*_jW!zOHxNeu+__mX>_3dig6$$y)j#!9**8+}?0WCy
zYE<{TzKJTjB62SrYU@h2ef_FoX$Zjo5t0&I|5*7^JHh_KBK_`6DC28cfP*vD#33Pb
zPq;H7m?(R51e(fF7o$Q4ew#A4sJ;=)@IWotR}rFus;=#UV0M;q5eYw1^<FhfkOdyf
zY|lLR#Rc}IU~y-jetYjGYEOjpwcv>-NyY3Yp(w?PL}nfJE};{XL0!dgU~%$@r(v35
z);~u$6zyO}KMt=A{RXOlg%q^dwBQ@01+p$=1&m_#JY`l{K=Toqx8@-nvKk1Y3;d$g
zNg}P*F$D#SmPv!+TLopp4f)JRooV!{AHE6GZOp_JyRBX_^`5Pb(CKbU5x`CUyLtkf
z$#DMK#&WQMlxkOcb$Sae6`g>J)bb`={syd3BBK4bLN3Txo)r=^<Cg;G5V&};Fhjr;
zaaCQinRh}Yb;42?v&f0wm>jhJN!88-UFieNBMOXXq36E=&zSc%)DSs&z|56y^sd^G
z1N0n_1uNEE=f}^PoMbr!bbPrCWLYdR2JU8vOvZRf$V0qnb%fpr3#n!VL;9MyRq2ew
zjm)cDv>loNr{%|7-ehIggCFJl;XAaH0YV9g*k#D+OuK(ZHg@=<%qa3K2Fh7`WemD{
zP(RpSl5GfxMa+Zcl%m`sN`<NUF^#_vKpJD_k$BW4+Wic-v~kmH@Lj}lcUhE+w>WTH
zM&u+rZ8nqh!cQ*-7*$<E?DvxO9mBNyy#e>xV=kvXn$sY@MKlFjPLrQ%AG;yZi*N`)
zUUPeLz8j*#8s)??b3&GV;FAmWszKM7HW_W)hZ}y^o7G1b8t2wa$}63HL8<vTLHHLi
zT}>9AbGl`RAwE?t>9ib-wR@pMiZ&)vsYQ(>6XM`!cNISsYq=y*hK4e@FXmOTz1TQk
zmSHyu?+H=g5i901nLC>_X>U4(2(p_ZTNIblUp#uTiok8?!7$?U`VLw9{FvjwN9Vib
zp+>)P@8b}`&Ln9e+t+bQs1I*+OIny;IQs!hXikg#(mPk(NECT03yuISqCSURk@q8b
ziKRC}@G)M`Jw5g{77bh;MY2(h%=|$2I$42}8w_R7C%c}D8ER{3dgQ7SO;E&tH&<52
zUsY~^D~mO*5#PQtQ*l5$IfLfc5DsNjF1m%wGJVx@4z-ojk>81yR>&9t-oiJWcW?^R
zG^@d}icqI@yW+{@hspH3()F`TU%tfD*3WSiH&c%vq<;MDxf$pF*?)A4(a}dqo*oN(
zr9sISw_EPO9tOvbGr8ElmLUlJK*v*=5M`z<;|vPPZfm7`bK*VpPnO7^bNHTZ&+xp<
zP8f+2`V0Y4pCi`6AhmUj*K_^ZkFeX?d8O5bSDs<xbm2&|yLrn<L`#ea8j#v5MK(ii
zjpN4)7lb9*vic*G>Ql^~iK6o1BW3Te9ZQ!DKX;ZP?H%{5n=m&a?=36PVL*!U)1&@z
z)K+($)YeyNs|rwg{5NlPl{(+ZPx@n!IS6tHZ~U3wL@cBOHkHBjM{S&*cwt0+ZCplw
zEYr=$*SP7szOlybO~-?(1G}x4`+Vv}*Hs{if78^z0qGXwzeQz0ZOt+$Np=f^7-Bk^
zt<dbYrY+qUUdtqt!vD2DcSZeIZ*=~FusC_bac-Py5PmfCVeyQ<T{Q$qIZRg{e-m?J
z#7?$cm5R$-V@n61zaEqH)~m`_&(f+r$3!=7cHS!ySPnNo%l+6ZA9dL?d>crC>OZ@*
zD2pDw%UAG6nB~1c(^Lb6ITSoK`KF7!d*aQU8=#$=DBI3E+_1RX4_)u+&HBifTD;cl
zy!-CjW;!ICD8{!nj&RqQ`)Z`11XsHr9dVDl@#1QH6QxoANG43|oOr9(O;DzEigKD<
z4TPe15&hZ&sb>*2nbA$c*e<2v3&U<}$JAD8t{r>X{`HBVTjRoN;4Y2`cXZ;e8whkp
z0fvDyo)ENtyH$!qWY~P1Pjw<aO*fv%A4|E|ibXtw$MKPsERKf&y@67XZmn2xU0n)!
zi>uw&{<DyIzvUPIh&8c=4$a`7C0aMrn1>h@vPesyy*Za9LG;Ou6*X8vI%AdWhdz}Z
z&o5;QOHZwzmCYigydg=j0@~J!Xy=iKEobLAs&GY`Sy^fHX+?iw;OMH-nkT-c{S*-=
zSEccs6Hf)AYan3q8=($+tWj%eIV2uz2I6Hw@!t}`G<{1!u(9SlD=K0j6pFLItx?&U
zI0c1Q;>@U^^NnT2<krKLQ#T!TW<|t6I`}Wl0AK+RiXf`UFGx9W;r_iJ6353lX*~}#
zMd(JOyPRA#+@u12+C0LN3|{k7^=u$eL-U9%*ZIwK-LmR{Af$@1(a;@ec$e|<1ZG{9
z11n$WaVU7;PtenD>l$=U-A-3126i)^h0{kyqqT4cA8AN4uVEft$xgfJ#4R9(SYUcN
z40=2*NB6U<3~8zYaJR33m<YRxiLn$!A4jdw!@RG_0OOVkvs}Y+VkJ*B2S16LZNEnY
z6rNwz+(d^}naqtBa}53P4Q1Gyw%G5=qtorYxr15rYove;*r@r*qLnr)k5P$cIM^3c
z3T*+2A@pOIrZv~NGL}lno4OE#CXeEZ_9l}1ToJGhhS(?R5sNQf6h`IXMpf1gL?xjr
z#(Cm(mHLdW?s_+GS+oa%*da{{b)1KE<zmXeiv>9<d~TT>qeBswgCM%m2uFztVu+SV
z6Dr>T^L@f5;m#BHc`>zduLuw4`tD<seOnxmgFZ5-qdXkim>Md-hdQ=)q$%kbRIv@g
z%9^l0r1P7}OB~Q*eB&O@;GGCT(5Qz1KN*@fw<olvn5no^3GeZel@$@5!2)iHwv}B^
zeK_0|9wdBYY+*YTd?s%OxD-ub*iH-z9e*LP?9}eIo)l^rfN*NzGL&;IsyFgM1C8!v
za8nN+@j?b}5|)V!zDR=Gh`jjD$c8YLyJ<1-xrY+9HE3_8*u#<tE(pvJa@t@=YXW`n
z?sff2%90k_CENrR?VAqn7Lq-6)Q$S1Uc0Tdv0GgcUl~Kej*OJqT{-mQyRfA~Z8e6)
zy9y)Y7(&ry|FI7RYP2A@>jSScNZgvot(GQ!^D4fFQI5}=L;KKg-@X^S<~?rmsN;}u
z+6VYr?!rtWI`mnPg|w&4ZmU~;-EMv^`O|6=m4P>9@F>|f8Ui94gr)Qpj|#yk)db-s
zQyt@-+pa&x=`FT|P+-*O2B{yDe&@2vz3H4!OL|gdrKuzZ30-#xh+Z3jrXGpSCRyL8
ztt3Myw)7VEreAb^bBg|!WFv``@hFbx@DAI24fL6N-DA@u(RN!~*6}+S*6=EHNcdGS
z9IqW?uE!zauaz6NZ>&1y`LUDCLzZGDtNdoh%Q2U(7v((?03eos^?Q}8KXptM-MO>%
z+j?6+eaX|mcJ${m_b($YoI}EK^2OldgCB|X)dL}>ePFU|yRDzN__2NvRJ+@B$!`>9
zh^SIP5o&w7Y-Nf&^2^Kviw+4p-ac(k*k0q#z2X0+;#j$CcYJoymEOvQKpJfnRF44w
zVert<QaF^Gh@%W@N#$jk`E{6j7_x_|A}4QI^^YjgUpwli9$@LmU&^*NoQ-@k&x>$I
zA7UO1WjOw^;QrN>zO*Zu{^=DepzPQ$IPJE&QCwM4TYt`lMMby1MHhO8KG9ziW*dQc
z%iqmU!<oyyyZwDpwJ+2st|9w+q5FwPi05b)?T|2>4FxFFnUwQv^|lb|&mEyJ13bT|
zui4%t*UJVvV(EYvs_{{WghTjH=(LA~`6M3i#;`F<*GxFnRvS!>kC&TrB!GUqfEsOe
zLuzX}iTtI)T~FQ$K2@Vz<G4c37pTh&MX-$8T6Eo+b}qgf&xLJgNNxG5ux@(xYMK(n
zFA^uat%9V0leY$Vg*jdiKgaDx=oTw;t5}RI^v~C{O=2tD|K1rtPG3FmeqQ`nJsz&-
zSio{{IT+4BV!6~(`P8c;F6+jqu2_(@Ky_EK4}?^bv46wLz5oFiF)`sok)qf_%wd~V
z0Be<T9q+2-(*^rV)N1LzXkO~r&)UA=R8bmmA99C_<YQFU6i(FjJY;Yt?gR66jG+KR
z2JKU>Mmx1US<+!C5{IQ~ZlVgdn8S5MTZ;Ge1%&BW@aQa~*1!i$7H)Y-3<bV%y}*%;
z2=@DcR}coyMxV2cSp@s5Y#1ieX!&4JrCRO}fCN*yX&JhQ{wR^ESBQ`Dv)5obYE=5J
z(EGseb6wb>$l7JF+G1|#LQB5@Ke16;Nu)q>X%WM!tQ(Dy1CF`w&G8A-1{`GGFS${^
z#Alh8#We?fy&Bjqbcs2G)K)Hb(YrRS_%JyaOt>sQqbQjp$*sbs^6=n`rGr5<fvgDF
z+}#_b1Dj*`tY&$${$^AMKQuj$1hOf3uRwOz6-Bx^xYOhuwp}mcQIP074#pf58!bi%
z<2|Sh;XjIF6+7p5Dn)oGm{uUFH~1(qmhL0Ukj0Smbze<TqwA7CcnIPlk6JU6jC{sJ
zVUrxNbQUFcp$5Q{_#2_3(6O;rt+99&pFBpl=x(H^l57@bY+?)Rc&X3sCp)Q7Kvc0x
z7644(>XRhZb&sMZnhU{cf_tUDL0F47_Q@nwa~YRR`1(EvTF!FnLrp-1Nxc+r%9+LN
z)tW}UPh4h2s)pn+RfHgn)ggjJ$v~%<iOuApNDhWr_+Cm-PoG2rd0{RrBR-^LwL_kV
zRAXX3J?ZWbI=T>B&X~k!%trHCd<}xX2;nv(vs)tz993_c895nuTp>vwSf9}PUw{*r
z6P<F^<jrv<$x;%JimiriHx|;OU(8{1iV$8cTQZ%8GGq|m2zD@U$4Rd1jgaKLn+lPL
z5~zkpHdNd(xZ2)7LbWvKnPkBT84h^ayL5Gy2#^%KdF4VL$|&q{l+K;N5&0!d%6dQ9
zCXl=jg`3rJ`pjvHr`YQ~$!^O-e<nO7pqbNIesOd=^>|)~>@|75hm6*_FCdx0IS7#X
zl@M;ZO&3RMuK9oqpw7E(BIKm#+L>?;M&f13j?@LDqtqr?Is#TK$4)n$o;yK#MwR9*
z{AvvvM_@h)GZ0GzJqRLeg;(=J#}0&1C3uUwZf_XB*D-`W?9xbp=R**p^@wuxA;T8s
zD)@O>S_rM>U~|>#<>7>FvU_47O&u1m2)IA2m{Bbl0I<rxdSCvDi{G>?<U}!OsP|5`
z*kG{kAq^CpFfF7&Ud#|k{3^CuHf;>~h)Y^xJB7e`5EM~9BJA#sOGqNh1DX~V&CP=N
z8ydW27;;8sG05<i7}J2}J=wG=3)p}MBn;lly<<w;Q`R-uCdPu$gCUebL|P*1OM}wp
zHI|}__;Yb_eo=XFVys@}@qGgEhBe<0Y&Nkj=;@(^>839LL22)YVy_eL7#oCdX%XB&
z2%<1LkHr`e#--WH7<pc$Pl<d2nyz6Xc^&qw3Gq1RuX~gyW5PINLYF)iO$=Tc9pUc|
zJc4RU$BmVz+-it7a7%X-reIj|ZZ%S{6tO!VFOd23S*Ss9zaN{oSVlYwM8M)0*g$B+
z>nU>@lq%wmVot+ujgQNbR~nDO=intjtmjt&u;&AJdPLz!gv80`tX$6dz=Qg19t-8<
zIEh-E4QW9-V}-YrAeECqgpZgm=pmE_=S_3q1wre@SUCuE+em1MqAV7L7<x`FB`6q4
z#&FL_>sQy5fT)yj1MVAb#nr}4lN^<w)-GsfUIP6po<B<<915IRlKnuqh(TH%l!53~
z2b(EOLUvWQsh`Y?I^iVPr7i4hL1DW5G@)RQJetx5F#uS?fZ}Pg0MA}IW#*Tu`-_S)
zK^BgB*`5&(MG&F)5yUR+>A~TE*obT9@hqs45vg0|hp3qF-L)rTLtf~yFzwcSG@q#L
zssd)B-{t5+VTQqpofcwiA?nnbFVG8wHW86#uXWD<02YsAmsRAEpLM7G(h}kTSOMSG
z7Z)0$*qCPYl61@-?Wu<)bR~(((h~*_vX-&rKK$v;TOpp}C{uwcd(3#(!hH0&$W^N8
zea7UYx#K>lDy!YXNg(8Aq)q~eI0>w{hlMCYuQUbcbRT9vQ#&NzZPME1F;Nb9{uB6q
zKt13dY0I(At0giSw(+zRf*v90^6UqXkZtYxd^3iudtJmv-cB90SApd?3`#y<JyW>X
z84YLU**TEpZrRKB*MehlFbkF??H@&Ep>Zx+s}`%7eKk@&jcu2J83-cGcOZ-JcALE$
zRZ@XVF?{C!1(sAm7=Ci3hv66o(m50k1R{*g^K3w`!8Kc6#P-TCo;`tD`@)1<-FXM$
z0<ySeC2Aw5Uwzx47ch-5kGBM-+4KXwThqh?%A?hbER-(1!cQs7a~BAEL6jF(Yxz26
z7~}vH!*#4t#4mj&m2>#xcah2FgrFUt;{F#3kk2u$extMWs|!cygOG|gaxAn(bKoOZ
z{(oiZWQ|D4w6~LQ#6R*DS9k?dO)WnNKikxuyC^u@QK?_e8F@C$7CObV6OjA{-<`A-
zg`Dk@;oylY*)@AHRLa8Uvo}XVRo$brE_?ec($(I=xI4CT6)B_}xor-;V)>0EyR#S*
zXZSqy)UA9xlk8I;tNQ83<4UoR^RW@$dHYZA<%ZSntub7kyUaLKb_PHOXJz&GqKkh$
z5ALHrhBkn0cF2MFX){9tgr${}iqfY*L0M7^^&k8tE2Zh?iq@#xLj87+H`jajaDmVJ
zFNyA|<Iyc{b1ua8SYAvq41Bg5P1ZyBM6Oo{OY=bJT#Ca~jEyDtl^ISRyoV_Tdm+Vd
z-Np-xnJ>gL7YVUWHAWPlyMBneq(tt#s<>D?Pu+_;mHW(9ChzXQ9qGkuA1!TZxBEfz
z-sIM;mP^r+)k}izvh_TVibVCdw{w{*Ib6tltZ*m2>j=uj!s+O0w+zWb5fw|M!LVRA
z5PHf&X%`xOiMsptg*{=?F1WMKYG6cr2>f}+-1c-Em5n~oo@8(ZbX#cYe(%!t%suQr
zrK5^V_5U0F?$*vNMkLY!z(y0|iG3=hd6e!pvmK~yE-8)g!S5uMZv0lZ7AE5qhYRO3
zx~Tb}!4wj^Qf4jlOr-N3u7MEq(@aOSJ2Ud_Te<W1hq6(HxkGI|Z5y$FquD;mCQt=G
z!%``nF%Gp@HRaXy?TqXPaJ^j5a5GO$`W7!?6Ctp0E}7MIspNAooX)#<A>66#v1+Rd
z8_xHGL{tr;M-rCHU5`G+g)Q)+g~JP`|Is!`%bPE;rJg@19I(jmXt%|>8Q}&(G>M!?
zW-IU!<Q@r%L?tW~n=eW-VoeWOE)<dB4}64>yr!FEl=spUW$NytTzv?P00MCq;`zfQ
z?}jDsGQx(hk|TP0?97Wpyywo(Od@*eGfbJ%WFGhQy<@{p8l6D<zSkfNSDCDk!(e5*
zmw37rp4IBcXKp-3*sbRR2sU!a3{H~sJY6<6D`ODQX}2V?5w5}~xlLnzMkDMfB3Xbg
zW<9SL$}AxXm??MWYOTB$F-8K)Iv6}8F(a8WZirfZ2N$Z$Hx3#t-bz{!vu;{p!N_s5
z@Vg7rojDkp5ZQXyBJ*;07J2xdVwrMN(SjzjgP-Iw#wIdRm94~UJiIV1LiV8`HhD3g
z_Hs@p8*z2IDaoJ+l|X?w9=j4t&94tkEQWzBu4mrFVAM*|^Q+92?6K>52q;Kp@W<=M
zhcL735%vlz<1W~cd$x>P@4@D%F}z&V+**<Lt(dijO_nuwBMC%vb3ZDI-X~@&u25@%
zQjX4DtEwhT+FXhmagJC9R^*`_;p`lU;h=8FCcOkNXbL0AKB0zw#&s8ZeQMQ8U^kP=
z-BdYM@708fw!S#ucw4#19_!em4mNwx*<?fU8IXZ<vM3`$&L#tqXE8ON>%lr@5bq#+
zPY<m|%u>;19~z=0-DHF4bX8cK*$qwJ<E{&vZ<*PPwGrNUtzcyp&U(mhCctus6|%=0
zS|V!-XK&#1?J<jsiwwg+ZO?8$)g5y;kL?lqs$pSU&F+G5srDV&mw52qR<69*#(G|S
z2e>Y4g?2RLdA`>awWZ&HBtICc#2rPn2foOhs3|kP#)I|Lglp8+&|8S_jyJ@)=+nKV
zm*)ETc9HR=)Tx)FwpP4eQn_bemyf!e)-3G@JGYI7YgQ5;sN^*0Pgrp^m{%~Ny`Em{
zxGGo+(?#qFLj|#R?)`$S=3NxoGg&|xr%Pit)@#EYX4ZEQb|>#?PB=<(b8XA2UR2Em
z6gQWYhNj&Kbuf6m;<f)(P?ees4V}dx``R^5<yvglM>ecnlm3X7TR-)&V)U7Ny)Gbe
zTXuga^j`nNRHqYv{4tcev}>%k7qR=|EtMyR)F#UhvIcx(rwmWfA(3oclh%XU%9TGZ
zw^MWF&#_i924B)fhXS<79EKO`t<hpi2PT2=S+)n?{)Qw*KDt3`+wN#ZF<~s(C+RBu
znJkLsOcgy$vRinDk2Or=*z#}iMRC$Q?~a!7$8Rp@uDZV(yW<psfHUi5pgJ7hb0w3M
z7lT{>>m;n?S}?U0h9rLLA6t(@P5KD;wa0!eRfd^{)YcuaCw&&>P%4-jl5VFdrKA?7
zl#N_!7?q2yl+UZwmFt1<)PL;M>kF(kP=hu+<d{`ISv>s4En{w$WUJ4SZuu^!dr<QH
zw{CN5|Aw7b3ER}xg)wq~a;P{4!ib`hoVve!pR2CB%vkOACK$x$x$>Xz+o!oW*9YkM
z4`s;bLdE-$>kPF&zM0<_m4sFL-<~PUr?29LzFVQ=t-+NWf6-MZK84KkJD7cRE1iCg
z+2<|_#cLGka4@x%+kr9{UPZz`F%@>{rM5O5vERiGW81kk5?LR(U&twE<WkQ|8Ng2_
z&kW6KVT43tF3f}1+}Udu(7Xt8wtwqdwgFJZ`&bJ*l@gtXIMP>nl1*?b^S4QDwM53>
zndvha1^S~aZtjHQ=@Cxx!&wezH1ip{4(eGG^e|&Zo)rvtN4`yu=_Y~@&UrUIKcB4b
zZ_PaE-2K<d6?3;jojF57t0OGMTP0}7!gRh`{kt5UM|pUjXg_&m!S^=HZ=maCW7AdC
zLGUX7)}({Kfgpvts>0>8$j9=0<oMkAA@-(yzTfcfek@}OLt^A<kKkA=(Eh8mZ=2?e
zr~zgl10jlHu16{DiBq`t%`ApYy0(Oo*zUo{Ttr?5Wa-UiO$t|PKn-e;(M<$-H!T+8
zihCx(xU{6d*v1klSAmQWqpX60BYGI+5_Lih8VAZu44glF23iHko@6&M_t*wOMaF`N
zv}V<HEL*h@>G?_S`+;ev71mwwNnX+|8fcr5CC+YSu)R69kMu&Ay*ZHxJAPlCZiDYP
zm1D+=mNJkf15dJR*sLnmSjI;~W|uLnWj)g$14tJ-E(_C0zE+(oqVo$Tb@>g3I%ZoW
z9gAm>mYS^KY$`Wd<I&)>(`$B;^^EL!H~IG~d#qiIPy~Ariz@RtG7OFkU^bGQ0aJUN
z1A(DEMg>fuB_Cj(%ViScWj@0m`aRL^Vpp{qC?I<YF4hVk5KBtks+G<f8GIa%UEW&k
zOH5{#P>t@zD|QukAG)q*g`cH$hlKae?baLL1?g2k`n3=H0Lb$xqu|?|6zj6tLpHfT
zhBg;9-gyy}Xzn78J>XZMY9VF;>(shXg-Vv<oKUEKMG)#Bh<Hpnt*$iWO3nads2CFU
zdCz^~jOTea?yxs{?;-NJG9j=I$86%}Uz_c)hqcDUa5#@{FDt3S@{CO;NvWwdhH2Vb
zZ-4zbFT$5N=M%<i2U8_Mm3bL`U??q8;;!q#>W9<;)gglgkPS&fT*>0N**LQk6N)Mk
zTH6q2Ra^dCP#`<Blmemj^plk!jFIGZ;M2>8+f|@_z%8bV>=f7_#c-0*>|33tEOzqX
zPB2q(TQ~Zid!Gw@_F{H-Z((~ag&g?Y=3WloulsVFmh}a!{<kpZzUIC3$FzaG1AhBw
zc!PK@Vj&TfoH@PF=YFG_(N&<sf$6vC*~~WyI`1vic83i7DsI5XS5R8)wrcTTV&1dc
zdP=LLE#ws+S3VV)qk>!=Vej_M<!g9r(4kfHR>uRmn_yQVxcAL=+aQOTAuzko&X6zE
z*06T{E^YN<>7tyfMRVtMX~Mr0m`r+MwcE;WmAV@P#o!e~hD9n(T|uD|U`sdDi+{Ha
z;g6_7_J-Xzsh%}21zDgSE!PeLV)Z*~c4vn5F>Q#AH~GRVuqFE^jNscOlGN4_7kBW~
zZmU$Qk-vL16#69O_79TaGspG_ToGIdBz|pvO3z+@?8m~{-}vV~Ko~yH!BOqIDUOYr
zuMmWi(c5x+ZZxi+W_3clt+tbFoGFl>WfVEa0@aJot~}i=UgRU6&u5wc96B_@%$AOK
zSZ=x|%@hc7FtFXTc;@nKq556kqCjoUlw1pT*$$~kW2nU*X7=zTFSgqnnxdq1Le|$G
z|1wi0d0dAildvBqOA_|U)hwer#NyNkx!_%jcPp9w!_)=RSF$&sD_kV1oY;d00nE3_
z*55)?+<16alH3~k9HZd#q#tf)72>yU3uBVx)7dhdp-?ZlkyI^H9EUvVZZh^Xqjp>0
zf7@%b>|g(0>7nly6R!Nyct|x&c~iYnZX*Ma57j%$t@WD=x3Cq&aumzejsKSWsxmf!
zZm4Pc3N*U9t{PLHnxVbJ*@AlekJDfV*En^AU%Ap1o8NZ+j*l?~9lfbP<OMC{ks>L-
zOz=rNO`$Bl*iL-6_&%(`$z<3e7o8c2`FEMS*JQ`Nk`d~87Pz~kF%b>%4Dmyn$)5*J
zvW1&?t?Qz;E-)}KRr~R9#n!90*qr0Em%1oBW}UB740IuN?u*37d68YnDdkY_`Q;-o
zW`Qr=s7fF-+QGMSH3opZRjra9ai5m9>{my8w8bTn0D1l$YV{?50qX*a0D(r9bxz_Y
zzK8K^6aFZi%^ICaNVdZv<`1pKUbs9I?n^ZK_>sfOhw`n|zp8FEpptEK+2UwZSVN<v
zE((3r@p`ETQ{t6>Idx(@8~KRj5U5@EJl|FN4GSBTkjHnFc4!lDIFj3-?7>PGEeIU|
z&J#41uXPSGgEGjyT|N<J_hZsJ4br^{eP<s_eTYG>lxQp+_w!)yhTD>wYxwBt$P+h2
zD4}lM8F&r=LKH0n6EP=^zTSZ_1_VCeyO9biL}N<?9>Yf-N8#55jlC2iMx{ZDXWeLs
zej#BgTD-jV6^N$|0rJ97xlbaJW_q@V#A6pDQ^)XrR)VHnCl|o1Wj&s*A2Xj^ba|{@
zB+Yt`1|tpzK_j-a8C^f^9`ZKSdZY>^$2eA?&?D%f+~!?l%ohm6Ah1o~<`x_SJ!~pu
zvFhB?Ptth>@twn&_$E8(er+;BToB;Q^B)@yNqnlG)!II-NCIGEAA7-Q&PVR48Ld}e
zHI|%1)~Us<D_3x_!GV<=L{>47Z3CJ*dVcAcMT0!ZP!3GHn6(gzOi4w4_|XVlkDFmh
z4YhUaX%L>@Jio}#X}9%67t0d6)hzH?5P2L9%4p56D0s07xqF2pk+aNl%mYK&4bd#M
zo(z-}(d_;tLhjY1ya?txE>;;UGb4eIpljp>9mqg}IP%g8+<5I8@k&(O8uuOirWTk?
z@A|1raCWNPEPH%*Y4+LRK+v=2{s&h}CJ&2>YG<PJBD%+UKdyQ+LJ7Q{d3l@>8hDO6
zZ12aI>%d2otcX<yO<;--hM$wEUr+Ls1(=!DGq9jEPeafZc*hfhC+#JIXt)&mAP9Rr
z2=61Yhb9H%TmGwhu=BWSJhGYwPu{ROxsCEQAjyCwBOvd|Cmf^zF^=#npcoc{5$3U_
zhY9uw<PsN8(q7_`wF@-8mi|05%DqkadVJ3sq>x{ver}VGT9rqzHCic&(smL~Tr;te
z={{4wO=fe9`S>f5tLD&gwzGg34hKk?q%r%1jDx;h&{B6)j4``u&5xZrns@PFSBW3W
zY2B5~cM#S&#`|zx^kbRoueNMXvd&ld@`|B$TTRaI%el<2SaS6*Id)s!T&6@W>uMTB
zA{0mWIxM|>ji*6TqLZ@QD#8Schl{lkhhHE76DoZY(#8Ayj$50FuD+yL)W?h@uM`TZ
zL!qP>A`1mq>GX`Sck9P7$s{3f{!^#VUZne=ym=4t@H;coA2&_N!2+OkyoLT{hfebS
zmjv_J{?@B)zF4BR#%I>(h1rVA-9>L%<7_h8GRf*X%*^k!qtD?<v#ZzHQl^VBQ<$hC
z05Rmd%Hf}|5OC_EvQb;PsNzAcxA_<2E??l1($3nYyeIjv+gQ%V!tlGTra^s^>iXCf
zUdc)9%P40TJ##FO6VEAY&b5asua2rLs*Tb37;394Uhgswf&ei|YML?g9X}h~x##mN
zQX=F3`1RiTb4S+Q`)^=szU=ZKa$=dq90*CFMsbTG{it^zP~8E--~E3w7i2U25sG0z
zTguI*D&!_p%tiwZQBkPYnIbpxqnp}oO<LN_P8LtI+p5jW7{m@a7^W|Tium{}hg+vI
zq}ZR&JUD5~)EmXc8=~yCMoaedQ$_42d)M9W=&3*F&;()i`HeVtH;w7es|Ya!*!@Br
z#SJP-`vwVte)GxfX!$?>ptsX!-LXqpfYQC<D)H%uM#?*SoB)2}%_(ndN`wU2QNOi_
zBix9x@`23V|H4nZ@<yuWq%MS6{0Zl;@YR(6lZ)MraOM?e0Ql<8tMY=~R*BLr-+p=Q
zH;?f8O03Y2P`ymGGuI)H6O!sps0!ODpw<r!EQWoBbQ1hih{E<(cQDxqE!l0I(&nWg
z>QU)25J)zf+PXJcRf>2d_8BixTTOo~?~zx#lf3#i7vFz*$TW87^Bd9KUFeW7k3m2k
zQm5{TE870(8~7@U;A`Y-Gq=6DUhFM^IsQnOC;17qm~AYp9MuPc9)huYmhYCiD<<9Q
zG56WnqZXXX;zsXGbtBqve!KfBL?50JXL*6|U^tyeb;L7bX<~;pyFLV>F|d;nQYHrg
zy{F29!dT~LTsP6#@%B_>`*GxUOQyG3cBEEH+T%8xRp8Y=ol~tk46JjhgNLSW=$d3V
z159MS1}UQmBW^j$)`xRcifGKXs3vslys$|SDx#+8kw4T{+#7ndq3^;j$41Q9UZ<!-
zH@zG+;zV{ntc8M4<&bTKH$}%}*ppT!?LIj7h;oWK2y)09P-KFBiZGM*r@YXux9kI;
z;yVW^@z})g+Ym%<#Z@wxa{Wb;$F!Y(SJ^G_BiX{}EmI)I_zeb@0X>UuNqMD?APIw`
zFmC<Nwv?ICpqnIJ+{l=)r5grQjyXW2J5{KC@Zo(5JNQW@L?Nu)t5`>gx?zA+{ivJ8
z{&uZ|#DWX5qGXyCxB|W;>u$%AfWmH}h;Rlh1U>V>!*!wpZ<2y99>=}=MxA^QflY~W
zgS-cRMMeW^<Uz%61Ur?2FSZ_s#74cx*YnGWu3s4vzd`_Acdt}C`aB##7y}NOtWq5!
zB5;VnMPcXl2znd_6j9vg-|_AzL5Oihg-+Uv&*N;Mr;4O3YG~_2h5#j!mj}Ero%NKI
zLC+Iy(?5}&9;pZFob5XX<qw#Xa9Fn453!ZGD#sO>m#?DjVq}!a)-=L3$;#(Ih}ITR
zTeniBwU^rZ)XkN;DVqHUZ~8RnSv>AI>q6L9l8WKH94zcI*Ho7XQ3J;@C2)gX!WQ#V
zbF~px>*E(?BV-pN@@uQ4U&65qi0txxt5c-fGw*tr=wMq+UK`>yC%Gy%%z_wcJdH$(
zOLW2PJm@~udRwMiG$acnZk|XY4IdCe&())jzbU>Yz2%AjuZ$1szhZSy6Xl$hFa3j6
zj)Z)2#3#!ay&GG&tvXM1$#3s7%E1QV>h?oT{<tj^_Bm!&ILmN79-{jlsGhpSEwQKh
zS+^4q#;?$_o_gzMn#ep)2$VgZDPK0)%5f0H4VJ^UwI(Gv$<On?px~AyxjcTxoX-7e
z#`}c#gw#N{U%w;;H#B~YF&b^I^AeHor^3~zAZM3_5qh~sKu=vZyK(Nzs|paAZqk>`
zkII$p5uj&GK5inhMJdrzlm9omoo~#6em%!T;-V|KJ~i(>geX3oRg>LLHxImSm^wlQ
zH~=`-$frf}$&Kf;ki~ab_hi*XXlZ}=d(~o;L%UVoKctgveGW7I^Bm&)(xYyUT-)ar
zFlURu*^F1b=I8GH;7s<7vy<zg)tfjH%=ECAyKesL<n5c$l)cv|xmlMc8Hc5a?3}kx
z{z*)_8+H2yRA7LQU9cmL`Sc~}JA(C}{gTUXJVvtu%WkWyp426!IIPyGpaS(<v!8yU
z$@4&f@aRG;i}-s#;HvS@Zi?{PfU3X506-!YF9*A9`|))*kxy2eng~VFjBiJ8pM*4)
zK?HfMUlm>ThqTo&2h%f^<0FXq##hER<M@Lc?wNo7F{;4tg<R|%3iCPZQrB?d>GS#0
zGc^p{@Q_<;Lmc}6H`vM{ikrVW+u{#4BVHyj%E?}I_6;pDtV*A?0#q$Iu}wc@TkTK;
zQJpxq=w@GaF?(}TWQDoz!xr0M`9_E@BX*f@zv8zk<Q++?uPwV?_Z^4{gn4|Oq!nrS
z=xf))6L&Oa49fwM=`JhF+C&`;ibLsa{>!znh`E{{ix{qZ->s~EGDjA{t=o+1U9>3o
z^?RA;f(iVzI+G+Nu1Pj{PNVgn=4Rew4`+FOmOf<cc(#eo9iDr9)K~xDEirm%--yiO
zz}Bh-D+zb=zYLa~y-G{61}x+y=|mb+{OP>KA8f9+UfU^P<LspqEa<Z=1%lHm-G6w*
z*?XEeHL(HygDcAI%Y5pHg{Y3q$nbg`3M89eVTHKp{m8~bySv$?L$#2roOCfb$(rU)
z>h^4t^|DhF&E#@hoB@$lx=fp>17W10=#9l>J3g9HTh8xuvs3=GVM)!oH)VzU&AdrL
z!{u}evFADJx@A|#r+=8EFW+!avW#5j8JCon$ED)lZX-j5%)*r46YPRkaaQXi9AAs(
zpLaDoOc0oEsCEhRUOIJ<T!%fCF+`%?=6r~bd?k;Nxea~^qKv?ge!H-#o)EzFVya3>
zSP6HbXGm8Bnpfex#TE7tvRKz<#AcwC_PkuAGGwY!EgwyYn22{nH26ad|Axl1;ndjn
zikHbs(A%w<*R^?jW(mj$2=?SL>*Cv12(SQNYe0!7#nT&cOY<Ptj8xg15ch`yXWA4&
z<+`?=68W6oN*iD^b5F}|3~&^unXtFs2bjv3rtN*HL=auckj|*ZqF@JI9S61#qhZBK
z1DpY?Br7D6B8h#PgDi#Qz}2FZRqe_dWn;r=(+-qQsWuQGZ9$U--#S={F{@V}_d{4E
zm!Y7{7A#Vx_M0g{?J{pWHI0Hs@og0B#x>oN5k)I{ldasNYEBi!O!}~eazF0wSOzCG
zFlVcnc^5G0T{`b7$H8Ee+mg3C-3Af3qI({x#U)%%)oma&Wf?S~-VbwDstt~7)hT1E
zCKkeSh+k~{<1CiG@>sO!#`mSh=HAjV?_diX653|Am9gB>LbsH?idJ)?&LTw0(R+?%
zlv!5-)k?-tyRET}6Y|Hg&r^EdaFJ-}W~odOeU`#XvuzVL@f%D^AKHb0RU12auNsy(
zk{Yut=Y9O7h!ZF04`n$FVyE=ETeLcp(Qy5O3;XEBp8+!&-&hA5u_5W#Mcn<Euuo>5
zr+)pV59}8L>UXH)g?#qnn%cAnwbf6$u`o+Y;2Tr;XkCbL7F;clK<%qoaI#VtVmO%a
zE-bCE&b4HPW@)BEvuEYJP?;WHF$NXiJ|GKT<-CHVX5_QQ`m4;asV6)JeBB}enF$MZ
z7?i6&hPM|9RV5Fky&GnSc+tA>V~o%j3kCvVC1PK*TZ}1tRD9WWyRo`k|JrC*E9Bad
z6qQ>*Np-Gf_uO4wR--$4L~X6Q_Nj{PwL~Mj1A*zh{KgzxYwRtI6}?B3*luzQ7q4^{
z$KsoHObDnV0)8J<XK>Iu?tFTI-V*)M*Yu(8Zm?Id8pI0uVDJseC?fOjZNa(glkjG9
zCJ^@~xw&)M5)GNTtou-P8A&9t-PY}qzOenoV>cPgJ@-9CWv}*LmNCx)5N4U3WQj@+
zIFnQl2OnLnERbB~PmJVo?L*5{lLWS*#p{DTMSkM<-?pb@T9Wh3fP0po*C#Yc-3tMP
z$3GOvIiP%%F9f~jH=jLoZw$&jJCbx%+mBGMu5kq~WS06O1)r)wTsv9tkQ@r3C@L=s
z=JYe1?ez6~E?Sa%<Da>ivoB`r4z<;!Q9G`=mAbY?vFfW6`7$b|zRl=)^VMxW<mS8X
z_95SGl~^Q`g&6Y9`*_Xr4Sz$~bIUJKgMQ+D>dHyv4~}u)(l4*O$s?C@1Y8(?Zt9Km
zrflVe2=pY~<+DdtBeBKRb5*rjznVRt_p7!5@BhJ&AALCQT9!DKY)E+=2yiy`#FcJ|
z<if@aukhKYAGSfs0`zwzB?p!9P(WVF_^a=-m*IN831Tr|r?`T<<hQHI6ZcG1`n;ip
zy{a>@UH|1HjUwCZzm9$E=O@rL82JXJ8;PdB$@{n7Kpp(!k!KXBpKO=7RSGwrp;=S-
z;o}dnE3n=1?ym8T>cy{Ln}q%387k2j(^hdd45(D9@et<g@=?D?a!SN><IKf)^jY3}
zpLoJO*xh(z<z9bHmUC)%AwZI^-<*}FxYRM?(B^v~wbe~rlNaNtts!s~@K5}FQmC~L
z?B4!bU(7rYi8#X;05Q+Fb*w7G+Usu@>Bkm&yCJyHXLJW=Bwm)`RQZO3Vv9`+piRGH
zF$lxL;+;K~Qr!P?Yp{+OT$CbNgulGJniScqnIP=A;7(lZa)lWJ)=y_QF*t7XGUfL7
z*f@DMlfcFJyoFx<+bNQGec81{!re?hcBp1B<lVdM6*}gHHc5G9m1~F?22_gfY=F&A
z(#^EFJeh*#)fg(lxM<!1H;+#GJX~IwPzpE4&dwDUJoU0}6h0p9xX)HU%)EV-FslVs
z-Z7+ZXK|wUP%QHYm@&cGyM;a!7=rToP4fTBhU`QVgIs}hfEj-2N+!7mL1+k4c{FUV
zD6+UeXmW1!kyPBQ<U%v@AJZ*HQ+!)v3xDP>10h@iNl)t0xV|-;s(H-m3lxJBAL2-6
zmm!=)NM?5`8YD(%`3>er8#K%?kIHq!0vd{CnUZ*$0?9Fls{g2A$r4bmrDTZQhA80#
zp1~^U!icd{2T~9+UTL-gOsWT+jM#|2T$*SJ<aa?}c0e`)vvB`$2$UB>CfLkE5`;NB
zA{-L<1XNJcVK4ob9NJ~C-Sp9VG-ivqqXZ3@GPBjgR*MIqbX}eUr}83|3ITXyy(Saa
zs^$Z87_$82E8RrI4E!3ROjhh(Mjm(o8_7^qF9UiUU8GdpTo)-S-gfQ7Ghd-js^5sK
ziZHcQEdD`#Hm~gwOa`M?*`mk-zv`SyLqarAt}Yvm-oB*f8=<wHFEuB#Igs(Q;)b6O
zZh1dZ8*wl5vyH&_6P)MrF(HmRPrS*#`&0~dS8i$vZ8*WlNu;Mt9#g~oT7%UMNAV*t
zrD?`Mh){f#-$IvAe2iqKzybJ33;|U&m@_FFE=0ssh`-7$bGKLW!wGa;hoc~Ez72KY
zBg)4fvcPbHZj6N2FWXg^;l&~~DK5Zl%y!pz#KBRo(DXRAO6aI8aMu9UU^BSj$}2&{
ze#>jU&o_fM{$llXsv3dg?qLtfMw(v=(@1HL=Y_2yp+k&V^xF&3@|7^Y>}!%U!pN&D
z%U-Z-QIB6XaBzAzOjt)|p>;E7GI43YP{^iCv3Y)gmt_y9hCJZ08<??hm!=;&HUwQT
zG5NQCt;zhw6$M*K){g`x$^K4J=59T2i?vHM@p6{Ymhh<eRuxgc1Y(ve;ecAYG~&Gc
zRY?+zJ{OU6qqdeSuWrzTjO~$_oi6Eh9@z8V^et6s8MH&f4-mzJY_I~}p79k~F~WsI
zlkRGci0{yJyVtP}_eDHWTeDds8t~Y*_z})YA9X8na=Hi0QyIgyD!Jg-Cdx0^JOce@
z9<?<*y#RJwM~f~^ZJ^*vCMk!*L$Q;jKf=+xs9^re$z_bm*u&^*|NE(HnW_iJ%Wy5s
zWBH$2$7;p_*0D;yKAz!wWb(jbd3X@cN>iw}ZY`GG`}#e38~UYYr03WkXP5Jd(J3kC
zOWFF-XIiqef4Js0(I2hi|I7<WX9y_mCDX6`W5%tYvn3OS@p^~P%Vzp4?`eLcK2og`
zVL&3DBf(J{vwk&cQoMG$aKvxv3yU*5ouF_7!A=t+hOTY{{`b9K($q`sG0r|u^L+Yh
z7RiXCD@p3b)mCkFsI4d@Yp&q3s6?U<&)9vv1Jg{?q*%R}xhUd|H$@E?Pe03LE)v$w
z=OQ`bg5)|Jsq%bs(#Dfbkrv&|z5b`LsN^2}F!!-M_u4?he5LHGM`Hvz{+-uqjt&L-
zShjMvtLlG$kz1C8<b60qpZ_eK++*MN;px+(KEHfsmtN%(a0W%il}EcihuJjAsTW7`
zQDkat$xOx7Fm%cFTXuR_ms{mpJg^hCQucJ_R)>VW6xrgj_f}Eb=<Wz~NV;k;J^7;p
zx)Z%Dw`7r@t*LaI%DM1<Ixv!rcE>J>ptc5A{ce`_fuE!eFN~m9u-h6G*+5XKtSqu|
zKK2Rk-f_3lD<|BEY!%z<x?<=5kOAjb&akbJQV`MTLUgAVMtf^=Jo!UTS1a4XlP}*5
z2`ZXjx;M?|>&Hjk@zD<i*WJou%q}jQ7q%4gK!^*Uq9Tuf(3N5JGS`v(TWFOYQ^(?c
zm9j7-{M%0INFa|25)mtkZ!NpqejoFa2Y899W(}1@a-Fc%QI#k~R)>Uh)0US<YaKaO
zn;Qt?tu`tfdA{3e#~*!)ao)9RtGkV%i)7Q5?hfXunf2pq*Rw~mO%yCSGLczy<>}m~
zj@6<Z^guf)9_3iDFBhX|$%!syTP1I0euh=caK{pFyIwhY(e^bx5dbrc40FlqcFq*8
zb28ORw{>~m8>QFvq1`GzK9PssyMlMC6Jyigx~Lka#(B3g#+^+6+-2@~QROE8CbeBd
zYDs{zVS(+SejNxFsLY8WPgWM&9;a`)Q3?fBS#wYFh`Gvdw+z|kk!S<+35)^Y@n05=
zI<6_qC<jo`&-b)i+`w8$ZJ>2u$fVcSjAcj=lXUR2-DX>Eo+<E?ptK$z+c-GSiM7uK
z^hMqJEkIX5IwwSMKD&qGz>H4)ma(+Kj{4FHjNebKOp}y0@BwBJK4Wy<Nckw&TEf`o
z-$USs?1EEZPTa1v(F81Ae#*U|d(K5~Heu+F&4W+ugnX3@CS2Mm@LtZS$KjBAHe|)X
zMx4DP^@cfc^DS)jdigYfzDS(emY&{uVU=^8s*G|J5p5GQi37_3=y?b-$|Edmmyb@P
z;PFE={q@YNT3I)u<o4{um3ldGk4Pt=%e#sNz5`}nu{#?Hq$-o6#HM-j8Z&%vhqKJ<
z;77!(T1PIV|A@T_Nu&mKW110L>|W%B?9sUx8AUvvQF#(9I2{MK+`DLgWGPeKH44S8
z*G}<DU1=LmZZ|mPNT+9{4YhZnbtaRRQg<0<5t+01o7UM9vGghu&80tb`SH=NQAgD@
zHMQYEI<RHSdkfU*v5=y6lGKV(<&$nTf7;qLBzieHW*!>=@3HIzv**f4$!d;M?GqER
zaM?3mEX>AYK#b?|ed59AC6J|{H5C+Vf<2X}MZHW@+?<#6QfT9VZ!No|K69>L95k{F
zDI~bRF_WP_bpTj*-KX)cS`2Mm2`e2r*e^CVnW8xo&x_v=HAN$2A3o_QI1M3cbUi~8
z^IYHm^|Uokhl+vz_VN<G-YBMWwx6-hnoE!S@F6y<S`oL6LIHm(bZdJeI~Xdh%y|5Z
z{3S&BP9BAvXVT%uw};c@JZt$C-+X2^dC~=@K-4_up1+VqEyIiR%6-`7Mcv`W+^dnn
z^Q7Hnt#9hVOIZ<S=&(D9*lyg^yRF(8xDV_=;5aR9QE<|G_Zd5z>~V!+n|EE~o2fEi
z4IZ_1^Ecx=vPpJZdv+F~UVw<*)~u(*AINi^v>9G)-Cl%RIXpE(@*h;?anq+i5&yNj
zo0aJv`R$H|I8C{UyPo^@wYf;<-M4t6Y?;gbAqCid1)}+tt(#ev+Nx@%(Qa!o@+8#t
zb6on#i0CJM;HsxBZ|K7xZ`dB^(wG<7usm61l!N$8z=vJRC@W`e(_T};ANox1l5z)+
z8+#Z9T<-=_Z!URwWm1YI%`{F;e`SU(u~++$zcnkWZ{};K7LJs~c73b2T$&chl}uY)
zs3bio?_aKPNWwYCX;b5qdbGTGX+}4oN*<+?W=|ugtNv#2-5;V?eCEd^Dh*!jwz?;2
zXI$y)-RCG)X>`kKyThuj?muoJe#&N32i8CRa1e|2SSNSizTCTob0i|YzjjATcGf4{
zPxin-(ivx;ZsG61B3yHTv~b<8-&(n)S8${7M~mXC-D_s*sfEmYe7C-GJ)AvU#b?4J
zZiR!@g|Gu4ETXpNlTZ0_i(~h3{3Pr(fPlivHszu!^>TJwUHvJ<sEB+Mm7Vg&z9F{`
z38SUi8^$?_bnONrDSLLZ6^u4QNfupe$YgtTe@S3&^ta=*Ua5T>i1u)KR8tteg_C5D
zkr!>3e|aY*67ITzME((BZ~0_md0~vbAYKd=r-L9mmC6cLrJm|6y8r&o7C<>!`<+Wd
z|G0B5Ofgc<S9Z0pi2nW?Y2bHI$+5@Z$I<=vQK}!V%_TTn>}2<m{nbj|^$~Z2WcGpa
zB%#wF2SMdfTc=lkeuR~fM>aeE!!KG-m_l96Or7i}pd%h0b~^jVD|*=gPcg;7sbqR+
z%Y^htJGN_>cDL2Beh78abz8kCg+1UYfh0KnBh;q{lAUCwEi>%>eclSyYsj}nLxlJ-
zq(>svshJrUuRwg$V|oFRR8jf$U7KNm`oZwjb)*>R8oC#+TPX6DZ;AP<&55^Ea){{M
zn~2XbN`~u#`TNy>h~L}PzW`yem~!7kJ+kZzvz@uX!Rlu;UP?l7S=hrNptch1xTl`5
z;@thwz2rK`NRI!1fXeyZSR&S_TnfBOWJWg4Cag9nf5Q4`mcVlW#3cxPBC<1snZg5}
zpHeF8+=YN;4c$?QAo*I}A`V%!>}Qb4>t)0GYUwuHOwIFY)7jUy99dlY8n(KWmx4D`
zbbFIcMQqW5_S69hOyTFkMXIa=psW0k(c5Blm;$Ew6e#dhTnRcp*PLQFm`*Q1$ClBq
z^;AvR8q>F&J%ZyZO9YIL`PLs{auHM(Y6MxwH^PT*5X?dlpLSbb_ZzifR<r_FGZ$^3
z3JXc4(c7rhAhFqcdNJeqy)200GBiO<m%&cEcaknE;;ukvb+gF{rYm$u4*-!*^ynDP
zF;6t9Z-%i(`bX=p$d577y*|+!>0u8G87*~J%y!-8Zn+W<bGAqUtAE&oKRCYEK&H}H
z^*25rZ)kOdc?J8bMrszdtfBOj!mG%~gTZlJI}k?XMdc;f%&~~4WH*I86kdbxl~v@F
zh+-%1Ed_VHE2bFA=%_CwjNUpQTxzu)EZ#RMjz$~~N5)fM@97S+VyUT8a6o4^1#ioN
z%##y*`KP|1W(pG`kC8wHAWyQp5{FlDWpV}hbxh*uR_xNaD47>HyrS_&Bf1pUYzIAz
zGg8@wepf_cGF&J|Z7D~IYarBiN}o@SK<OPiPQ%M8Dp*wBir`&O(Tu>b(hYiA%w&i<
z6jL1{L0d_TLzF4uCJ6@=(Gfezj(8`~qC!;U1-~9Y_eyXn*?UOV8%YuKg&dZd?MovZ
z>E>9k74-o4tEx1<VR)M>WN40ptXe{YnZd&&wHgLSyl>jaG0s{+vOs?tQ?ZG&b&+s?
z6sRCg=tcsrx&TR;yZdX;F@D9en)8k1Sp^#a)B($-j2qcdUzO||2r@Z+=}u7jqZ|XF
zb}n|J#OU3&D%cTi(o1-X0gq#N=+7y^oB7q$P!a($!;vrkNOY1w7Nn5p;jm5j)Pdxf
zn^WwH$&&3et~k8n7~#0-JZaRqFGym7SrW;Ngp!b)eatHE4~mt$$8Csu0E{!VP*E+e
zD>xx}wxPc$9wi3ykt578C43P%C0S>rD%Ktdm=VhkN#W2m@@6-d)h3Y0CKQO6a+M(_
zq7uo8^S)IF>H>g3O}GkviMz`tpnJ&T9=ilT5Ozu6bRT%RTJIo7uE#zQ2KFgVpkEYi
zAR#XdL890NbL@@1jUiZ?N<pBJtMtxw<zQke;hvYYd=3U8O8<$3QciJUYD8a%JS-7R
zr^5&fva}d4hvZHLVBiOgBw`WCxR(c<i!%-UfnSPOmcwDn;_?thiwjGaUjrHQ$x`AK
z<k?<HCENv{EIGhKMR%f5Nm@N|73BgV(^1?_#G+~-cixH>??UY4-Z8%JA!rFNWUfaD
zb7WftOG<_0b0nEt44QA?QS6P)Lt+Wa{Qkfz8G+>{kVpfxdl!A{>YJ?)qcD4UNfAgu
zn#7CE;6($_5fhhefOYW6dhpYj@$x6=3a%i#L7>|RDw~dbl<KnDkGLhckV)-ZrRv4p
z%`sY?b-fUc_c3~5#Squ2a8u4}q~qS*@&*pncS(dZzP+6F%Mm71^U#s(IQ>_bK-!WS
z1ePpW*KCP1lo_#06gG@8uBZNeDu$GYDcUG)Cy#2MR{Ek{bnR%5BZtL-pvEV{N|V7w
z98D3EPAX=vSTau91^E=-k`+eEPT;#%1kdonz?t<~5vqZRAHJz*MLaZTihx`;hEF!0
zox0^y(g^lRzP{%{mVifZA&Jk0Q6r1bIOVT_t*r9%<8j<;t}aF;oo*Pnx9St&Q97Nf
zW_*&S5`58wJj77j=*mB42x7cRA9qO%cFU|hGtT14Or4*4wq@2|T@f>w@Hl}oa{dJT
z(BLf-Hgtx>Dbc~UvL#S=6Q!9)N;9MrzDO3DT67IC{q|T18X~4AKVFsur!ybyHTL^)
zH(6-?4m1~>>H}((=V(h~Cx1j>=@xiZF7(S-qz6L4C-S?4-yXOl^d0Cn%Q-ZPb{FV8
z6B8}UV_A|TF(KO_uqW)a1m;?aH52<e3oELgCMpf6c{J4_m5sUEpyoLIAyU74Ca2BP
zESAwo%xelBo_BG=>kORaXh3e`MBnA+*M0-W*awad?((4Cg?q>>Q;`5&N<+LFzoXQU
zfe`5&A{8qx6Q{TYVNkiJbQtOCBFI@Sqw@^`-d6nLhfGQ#P2LFhokiDSPbR^=9rAon
z;k7B@>erI$)f`#cPS@740DhTIt8V}JTDal;s?dZx#PC(OJ>Rp!6>!^EM~I7T$HC7#
zus&oGVjlT+pR=$?<Lo#W-ifTf<m~(*$B3GGMYCPBQ+|gex7SM>wfrAL<lin<ZjjeQ
z{C+}jD6h~vOqPpWFDl9M`&M&E-~E*67<3GHeQ&mR&$7!$n7?<Az}e-oK-+CZ{zbas
z<7?G>++UuabRS;ZtwkyH1)q;b&OlyXztd&CYsy{>8-1$nm3NX;t+s>O`qo?f9*0>%
ztP$fSFKl>EnXqzC&Cmh7H5RP#z{M+7Yx(BCx(5C6VfujW4vRc|0kQX`u_a&rY2mf!
zQ|h*tn}5S`H|p!60u6+%_I%`t7qYT`gym4`_7yLBl0_{jsAe8ad{YPc>)hR`PT`*5
zg~Bb)nWop~SZz0w*LXM1YjeYanop3DuD9b>Kff3itn*Iq=6|ZgoZzC|=N|;~JGb!N
z`;~5ZdQ)enK%BaXWb<PzKH>1czgRqRH!pj!$RE33e`nzyxPoIAXh{*@Fv24L!h7h*
z9~pCV;}7~`2ze~HFJDJcggf)mHwX8(Pg_F7M$JA)hk$sz@t!u=%;V5UAi$j;yPIQ3
zkgYeQwkM+)lqK!SJYG{LbwW^EExa>Ht9|ILOXFAkbj3azn;jetRFC6VVQh$8I8U+`
zd+5hbLW)7BRP*)srey1tF;{QA+U5QXJ;CS43%7YAgBgkJ?)A*WxwcD&0uj!QaX01H
zX|k#>%oyV$J?c0ep#SY#OMmTV?lvZlRPK)Nx~zNWjEU5J@=5AjZ_EyA#K-=xKye}v
zE~5Rw*`1NH^9Kl|tSJ{o`1kpOf^ro<KzC=GU&0Q6VwuAi{_>IQ@<+zJoBpd|m;OI!
zSSKdKJim({Y^&d8G@)N2ym-fUxfeFrj><Nh!Zo6xM_et`BRbxRUfq6A+{#b7b2=K>
z1IHD|oW@rL836r+$~N{UKw-P|;o{k}ku$eO1yX8v(?#8rbF0rNssxGXjCLX!4Opc3
z4+We|joDIgzd42&Uui+cSG5!}U*_t{SrVm$o*zMyx#tG0F_DBkOj6}~RWJe9*Jio<
z{37^e+<)lZ)Ngk@6?I0meq{AkT!NupsLx-%Y@9{m2SDLpQ@Kaxi7!qD=dQuhhrM=W
zyx-ZUdWj{d-#))A`htghoqTqle<+g@B2%CVEj!zqp$Z6;dCb9J;UM#=M{r?J5auS{
z(I~}2k<%K>K>7kpWfi%5X2o7rPGHYALc<*VFj{$U>d|DnAT{riX!#mp4H&YWCs~pB
zgi`hrlo4V)J(k$H4n=GJ+CCMpVBww5HMEhn(ZL`Z2EI>;(zC?9sj6l$+MlB1RKpq;
zs;-+#<<o?SS(I(9abjHUnwc2VQ%2eGrFlN%Dvv8i+pr=PeIXTgAS^+loCKph?`FpB
zF4#<Mw1J#h1<gt_vh)_5VP5D^GuN?ZCD-AQMBIfae}ur%s7G=}!iJZ$ob&ORx%q02
zGl`Z0E(j8_dSy?r#Gl~`oO7-#!8rUF(C}Qz++{OgBajb<KlH(@h#`;;D3D9du1)_E
z^815Y!6=m=vxQpBwGfr1akt^~MhXFo+fu!`Uzko{VH7FX+(>3&(z6YI0W(Mp4Qyo#
zrB<3GZvCE9->O=YAeJ6W9`k?!#j-e6@K(p`qFVZ{{Dy%pMEs0_fL-t)si!)N!%96|
z?5YXzw5pL8EPDJVMgx)CDGTiyHBiN5nKv_VR3m!=&t=-%d>7`&1`5PY&_U7jQ5m%I
z=n!Q;cAUG=#d=|%U7CHiAlGh)JIs@;rR7b!hm>O>f*w&1$(Ni<Yuf|bs2m22jK0=r
zRnwKDChVLc^~js58|3i(m_T?@DufQ@#9U##9794?EVI2>!M!I$<VRmsoT9|n=5YX&
z9K-ArB0x9QRBjid_G*AlYgBkeTC`Xwja35X>tKUu1ZY0Va>z5Bl_woewVWAQ5mdcj
z3K4B^c=)1^`-s1@x1_caY<M#nJvk9X)l5%b2k$7d*;AKfTs+|>MxJ~%UD>bfi)RSO
z)Gy_CwNW}ccC_Vr_ifgV1gNbs|A8V@rxA^2IHR9lawBKwaz1il<>9o3Ji+<H!srJ+
zq<K?W>s8xkV}nK~jQ<Iu-*EWcPWboni|-}3_g}V@o#xg5bMGhapF-ko<m2!Axa-FE
z&ZmWwdG(*?yf0=8;~~Z~P;T>8!@4S_J0Esm+c&<ok(_59MQvSm^USX8+)a61za|Ay
zs$wX8ost>~qNw__@TMx<eELgC*Ab(BXVJwk{TG!->nQ^Wu{o}@X&H)a=-$>Tb?aim
zCp}h_?Bx-fL9ihLVxK(w`%;hIWkZP=@73=JdGW*atT<}aR=3GQ!O|JheCFQZw%$PA
z?inpA`!*va>vwwZlcs`e0ED9t`=qwsbu}0L5*7bm%Gt3+Z8?rDT_goOKJuBe;!}ua
zeOG7M{h##1rnV|_6UeV;<@!gs15#~r@s}?ui~MotUr$_{P{e=mh3Kx^xh%y0y!4af
z-x`U_3OE4#bJx*X{PML+uJhI@uWr353LOnh4i)q_zV!*~(+0!_Ur_jOzU64YGAQ)1
z4|L3<f0S@jwS+9?H{d&k9471gM%V=S#X|3m*<B{Z^j~pVI)4bw;Sgs<sOn*A>$9pN
zgpjs;{}=uuofv1+CSF9W8;m(t=SZZu^QyJ@+%GaEJ2MuJz8alS)!@`TQxcI317}q#
zH;xqU#((%ak~6i{Z9aHS?#Dl{==|77ul(FYbnL%##4Q$cn{NJ_x1P?#*&Qr!h8|r4
zEW54mx}tvS2ru0HjZn=08@^og@gHPN{G-J>;OqN`CnYnf`W6V|Fj$!zkJZe#*IfRU
zcNIY&^=u&OXrQ3hqj-{=SY;UwUe%Cor!e6|%0Cd*=B0u)9;%M#s#-5r?Yz#tdgVPa
zoj+XYgxdW&V%}-rw}<c$(D#vQ`J38We&M1C<`=8<KY4tVH}}Gi=A+#6>G|#uOK|G+
zl{Y%#b?QOLc%#j2UDRZ6lr@UoPF!*Rf26$)lx0VC-@DJbr|+EU>5)#)w4|0mQgy2(
zT0+3p2Sk97s#`6oQ3SbC1`q`B9U{b7V7~za8OMODds<Q>u-)Rx&cyMHFS6o{apE^&
zv9e^svyZ;=grAl(No0pdoV+$qk40qcHO3~E!8q^tuXApHjHd6s#Jl^}sgGT|cJ2Dy
zRdwnNfI$CfYfqZ1)Ye%$C&_J{^@P9+!%BqebPmLwnZKjjjo~b?C7eH3l@D2Y$!@=Q
zeAnpo>K^t5K7!wajlyyFuo7OALfupK!&EtD(>0?C-4VRo&F1+X>1|oLC+MBTtq`_2
zHuRn?emh%L@l~ysYZSNfq#KOQVog4EX~#U@;yCd$&01dko`~|47vw-$9|klNijW-U
zkvbY3kw@7sn8S^vW3o|g#Tp!jStpt}c@8738ol>u)s`7@GOvu~Vw>DRYg7b#)jPw#
zfG39SGr{a4M}U&Tx-N((4lq%y9d(_8IKwIevcgvwgW-Om@S^F#1wL%y<sfziO<(aS
zj}fK?m8%!p|5=r4PxlLn%BO}lP4kXPDmdUJ?6k0bb}cWcgi__*<V1ai-Ex=i4MUWw
zPd0c)mv^=#>KSVRN&?2S4lcNl-Jkq;HxE-B9OW0K#_sNB{+=?A|FDn+iF(486X)k+
zq~^R1L$##$)PmR@2w@83T|`(>2Ki7{bg1~z+F^uWuu|(1!Q7UT&{qU`7ue?f(_oRK
zfv|>FL~o(SZh0VuLT76tG(29l-I{*7XC3BQ<>sy$^(mg`^rA(kEmml}$dbgmKF3{3
z4)Hs!8e}!Duk+oDI>d7|>BIvP8>r1P|CJUl$qtBfGzzvfha@#Wj)`!PHFFAAj^{ia
zgy<T|@bL{iV&qvZr2m$hSBgO)ky1<^M^%)iJTs3ISmL+HkvO<?az`G%O2vqrxq^vP
zP(c$TdmqLjq4WjDZG~$MBg<{to}!9H2C7)CE%pt;R6zsGs#rsfrOL65)F@ms?o{CP
z2xNGbr4^xCCS!P*-9|gUD{S*yqC<10PTxoI#IS(rNGs`J5rvc=5Zp1$+7W$rG(r_p
zWmfjeqm2793oLO|YSmsV3pVrHUisqWhwx=p@&H3;vT9z|=u066IVwHI!(0@~xvWqT
zGo9I%TOpnf!Hj>-T*iQqqL^=y|6|R3ESxX>8E9V_afUO(8>hA-o^l)R8C~3xX+|O7
zn-(N~5w`V<9Jl37J(Tc<U5UGErz$-z49o`DJ#hB!2N1&9NH5l#&^Y`mWOc8r#sk#W
z2iZw*aUv5QAmj`6qMdeIV?r%YS+GPu41|b8r#Kxg|KgH>lnQ?qr#iAZ+S<G95e2y8
z9Y>Mf$CV(Tv9Xf}7oys#xAnY&?R&d<ck&{i&3!o4Aq^ORBRyC>Omo}Ic%~WV=(lt<
z^pnX!dYOSBwY6i{`*zyB$aasA%bpbDZfoy_sPad5oq4d|mH=W3@)*0;Av)?yO^Y|+
z!jb|&KyRXNXuN4OcJREn<<WX_TWY*1X}<jJ3HxYF2PtZscu{3L3}iOaqn>^EQHIr}
zUyiw;ZoBdzpZM6i+p0}oF6khJCr}0V{a(%TqZF$nv2X{*P`j-jL`@^T4vdQ7yMDi_
zJ4erc$nJVavfC%D&MUyZaV#w+J?DBtBeVY(wxZg4yvZzB!S7kJm66}Dm%sU=sVz*h
zrgrpAA?ypyqzgagEgUnr>=YTCd(GU!*rAa?l>XouV4h*_+qsy=(|A{sbEnN>QpY)b
zaw^jrK~NVE^~e6iV1Yb%kec<@`(mhKgt52hsmJa>2>U3m@<%Ubbq(dv;Ttd946-!8
zoJ4I|x4rm_k5si;IqwTfc1{>P<6iD^DK)B^3Pr|ITMO07^4R!V`slSJ%O<aq4bR-f
zG$!r?UyQ0Fly}3^P--jvfx%nqM(uO6+Av0KoxyKu>3*MH`C4a>_~e)bI1`@U<%_Xv
zt>}2PMBdiR-#VErd392-{9y6zoUgRP^2FcbvLtp}Fa1LzX=L@rHLA7R%7hY>g^z8v
zJJLEch_e~`5N<OqlRy23jNBg+sT%&6G)r0*;G3sv&tV>Uh+^G94JW_5VaFo1b)r#l
zpL6ZoB9T~l@l`jyS|%U=QxbEWKh$_bJvNnM4?bNvCTeRn6=%!5-F+ILd-#z^u=kS4
zvp8T`)z`9j$n0?@`vAy8G7@RkYO7_>kLA{VfoPL_!Mtn)OUu3E<Lkf6K~PWCg~3_B
z&m2Q6bqkn!J<n&7ydCyXlI*tT-yxDc<)TcI4)a-LHaoH|=0~HaqV<E;9>-VpQgV6z
zm(vyV4~^cn1s#oGrRS_z=(+knHM?Kig5kJeXp1uzVM^<%iml?l3YQOs3hPcD)T<$(
zhgm;eFB<NO@tXZgZS|Eaw@!r@W7Qb8l8w}y^@t4jl=Lgmu@*N+PVzX}ab~wHLp`WO
zaPSX|_AI`d3ui1jxzE9wV+Sa#<>oyDbp_9vXKKd?K8<_Lpfv!Lk}@&(6wP9{h6*Pi
zLDT2g@o=)EV@1qp-_h_JAt4H;=k6xXHb8A+Y_cL3`AeA+N4Z*Ab@+LgnIw&%m{TNO
zBikRmwLBQ=df3%-9Ln7S=uH&f$`&7`*5o@kpgkPS2X$9Tr(&qmA4}DR$lJDPr#ZF?
z#38-4#1)6C9HCWIy-Z*Opj15OKRS*ZGP)ri5iP|08Dp;e#+fO_{=x-0XDPlOmDFgx
zZA~Db;&-3N=nGjzu}eiOKy)OxJCepxP+cU@5Nl!6WBp+ufb6%3CW&P5j9D5Bna92X
zL1kAQtlcMAX|j?bU+%3$<n9koC`oF2n}_EYWzS%0H7j#iO{dJ`6BJMV#g5t<c-Rud
z9Da4Rlg}VPPHQ2xsrGYVl3dUcP6q5CCntMvQWE3I3{_Sd3mD29<Lj;<Yg~v5T4Hdj
z8sabT^Ej$5j)L)$S&ZAk;RqfCsn$V88+Ep6HyiU^SL;nx72?$LAW~J;04u=3Hjo>}
zHlb@FW_#1;a#<zc4H)I1vFh5!bb2G?bW6k{zw)2t*F|g($$_7Sly<^YrsBz0Y|O?$
zNb~;k+#Qu8wlG_U3`6BGu#qF)$|HYDz{NrfRWoau^HX?gY|}^CSWE+0=ipd7KDdHB
z@R>~%kG?;OaGIe{Jm=F2HTFnE+P;L^itYZD=#tNlkod01Dn0$6rS@6FiAK`J>Z9}I
zS&`#t-_cNlou-fB$@-Rh@GSF!u&d^0onz3R>DdOvZO`&{6on)Bwf193k^OqLx3IDy
zzKsZ{S+?XePmd)Fw*ILK;}j2)&Ev6Md7aW!=$hd2Q$7p+91BcE(j=UhYPU5)r<E+W
zhf-Tz6+wrD!&y{%XU}G943BnPGW?0`tJ#5L#eH@|mbTrk!j1U|x0HX#DER^E9%`#(
z>ayQSf-5^yHuvtEmeTiKJn{^_S@LB~o8VBptz+w#23vh=NRzj9tGZ6mj^GGEZ7uBT
zY>s(ccqDvb%Wmse&#HDCRN&>(#g3*t7#{7N*6r=;1#-h(l<5~rM5=7eqJphF$=4a^
z?NR)JC*B>Rw!tA`dbDGW)>3*S??`^Dku0lLb%oO(MuNgcUAMigH1>Y}0QTa=B7VYt
zHv6g693HLjf0A1O-pRD{2ye6MDwmUghz?io;!GTy=t8l7e7*&)0v!%CU{M>*e)Yl`
zPcD~`r@i^d3xD~C6Z`6chMoV!#iV@S1v8c}&X?Y}w)Bta9i!UHB{OQJ+06ewmo*OZ
zn&fT{y>`}FF;D4%-|*#?;+V+)>X+PO5@zeeV~PFD+j&t_3HAqX?6$hj<XNdlJ<40<
zCVDIvw63^mxqj*>EDZ)06FBA7yn&_VZz_uwu<hyRWR*Vq`cq5k(zhNcszbu^P571H
zI6EHB%}?lTGFqT}`A5l<f`<S<hcra}o#Q0S-KeXqbjKC^$Pa33SCupT05Qh1$!{CU
zoHjzgdQ+Xqoxc}r9}^tPcqp}1Yzgs4zleyW0x$k}<TQLWbMsj%o0kAn<?Yk2d)O^#
zx3$$Bd2sb()P>KUp9H_8>sDy3Yb^OjP5V)2_6WyFX6HV{)dy|kK25H=Bv-}c511)U
zH63bey<8TP+R-Sc7w#+y7zpuB8(l6VMk1(3ERmLa#F0nOGepuKO2z|pKyN26gWYSk
zAgfOm1Y{OIo*c6Az1AtK4u7!<(hCHri@E*rRL1(D&G_$Az7o0$q#uy1wq+~oymx2z
z2UL+Ba5gzbZB@H6`xFx}l6C53xq*~LmR@e@5ykS%X!IFIZDmKKDg8EF$IS)Ovx{@+
zU74@7N0vSBfUIdqi89OEBYuQL%|AkBt{Y4Cxcx!rvtr_-s6m%&aj?_HBVBk|hj)&=
z@vb2;Xc@?iR|w}4zI$T&>Id-#0566&*=<c=pvcgY#~5y=HsS=?7PPXOV;xK_vH>Cz
z^jQf*TOg(9gHA;8xfi?1mf(syK0$K0nqP*@oiMrs6Bb%(8p&k~lGcKVt7y?F6u&A|
zCkIC5!dp-|lq>_RJgOL#t)Cf5iF&YE6m=+cRxA80a7bDcpkgh0)QvWoi5oR`yQ|5@
zr{73c8tGo<;vSZ`sobxk6bU>$`XrF0AZMM3tUEx(8T*7G&bAz^L8OMJp=x3Oyxe=O
zU3(9Fcqa`5P~`0}D`&$8nHoT{4U}xsnoIx*;Sjt>+kmNJnFcW&csMUzg<I^tfP$?g
z5+}w<r_K}z`)*SnA-@T64t~f;TjH2B7fPN(LaeB{U0b7*9|pc+f;v`M6MZ`RQ$tmg
zSF$FvQhb(|6C;T*NBKq2ZHSd!67qy54$B-r(bEQ-Cqt{n*I{!_z5~E3e2fzGnfVYP
zxD6&D69p8FZ9zLY;JmAkcalLg>McM(kS7xtjtXrF&?ow0Md;``emV>C><^xVnl|30
zTd9;{1R^S4(VC(7;_DDokfYZ&d*YO+C}Yn%dIT*cHm~OLLvavEDMnOZlrMZzEoLjT
zRfge*nKJ#dKp%6gz^7f3brO0{1hZ2Fx%h8|Gsty7v0teoR5>De5L8Uj;n|`nmxJ(!
z4fma1hRzft*%lZbUGNt8IetGZ1Pd`D;;F%_YSrKZmJtml5duQjkx{{%3`F3)!#9c>
zi@-&52m_rnVg*MUp-nkJE_0bN=fm2|Xuz&tg#3xxBJ7*yDb$DLLm>#(*q8;VUOh;X
z+#d5+K=@8kbXAJI&@()F?{EZfx*?xb!TD;mY{b+;_$i2OyqS6iDjQy6EU;4Uek;x$
zqQ95<EG;)4Grpe5{W}wK%)SuVp~`lgP`!rgeovrkHG*+S7+cj>MvELf!ah2H!>=Lu
z8m>n>#)-#}FXIXc$zFN*O<3<W&xbP-_sj+1-S!=i53tUxJpE6ZhF@@Bzp}V{!shev
zs;Sgo6%qOyj$r>Gw^EesBicKivu?GZkzW_C_jQ4Kf=K%dfmf;?k=-U7xd+zl)B_5#
z#7;CcFU9fUG-Tg;8OQ#)e#oBBlcaMQL-uj*r3sXBSPZFs`)EY%Yq&JohuUhz74OJe
z_Fo-UH>9yx)0iT2NL{7)qG#HFYhOwmfl)tL`4UAdF9u6S*|6`MHl~0s`aswH(s>C7
zX|)?bUFDahzfJa*&JK6$)FaoHqR76y-~tH?4-*_pjJ~i;U6{L>^VY8?*=Lh1{g)IN
zx#Hr}mGYtHZgyMI_t7@G2Y<%Gt9~*_nr6TMBNO(;f8&xTCMb^P8?CtN)JRyGI@>bN
z5f25;{4bO2ruCa#GCGm@6My0jxt;j6xAJwzLmZ5QhR4H-KSuj`=X1D3HB~F&x%#Jk
zoF(gWHxis7DLTwQU$uk&Xr9iqINbhrV#}-nB-yp(>gl=EZsPTp3x6_dZKAU?xWZ3p
zxAlDwHhj|HO}S!OANlYxhLfq(bokZt)UQ9JG=c8Rve8}dS&ZABp+*;ll3_opt=FAo
z`HV8QiF@a}hhMxTZs|^j|NB)|=<VFN5lXV7lzQp=r&ouP>=Pf^la2B$CXc%;)c&eB
z>)k!OljZj?Gkp<y@4MBqUpO9e#}{7nr5{i1`1j`04mv~gP9%Mjg@|%>S2Fg|{WXPt
z4@aPSQR>TD-gwij<sDp9L&~Bgz&W`j!1A11Ec=Z&q#ac)?Z2u<7v+InnKe)GM%j0B
z3lIJrgU}~X0@_KMaDFdb{?kajJ8d)HxUq0AJ8t&1?_6vX=W>cYQ>y*Ik;)897p=cK
zI|L<n>|5a__<8S$sif2wyz=mMO7G-ZbYs_7{itF@3g2T+7bwl}Q%n=rL0x|<LH{8Q
zBT+YQ&*3_oDKu}pD$c;vgcKnrd%VIgy5HZTcq{np4Hm90^v$@*`wVYDuixMzAI0*h
zUF$ElZWD~zw)t6q)lI>kVpKZ(Z>^=g^o5CD=n*VlRjO)8W5=qft{2Xi)f!1=cTpNT
zZ4+~=us>nQG(5ZCm||y!!|1bTvB&dCzF$QZu|SV=|MwQm9exG;{uUo5y6dL3sc<33
zNHz(d**3wDirQ-a_jxBeCKtl#n4aL%{dRVPnmDv937MP%@GS_q9;V}sSymrJ!FR}H
zh#p#9XD<%lEBQ?+cmoFaI`OW%!YRE-S<{6&Sx@Vb&Jt%#UFOBvIp%!ijD!nSAXp8K
zXPCtR>Tfnzj=`p@YT(MW==IR4+7|dZeuB#!M%BusuLuIa&LnLQX^Hh_$SU+iH(($Z
zFAQZQpMT2AP$V|-xtXD=J8UrBASNm3?l!19?AsvVQXxewJ^MmFX1iHK8e`kD!V5h3
zdCZ1$I64g{2}FDLXwzo7T1Wmi{vf{I5iceuFAw5S>7vmm^WcU?!$n=8i$frOs6Hf1
zc?I<F_}L5Y1WH|;y;y5vn$aIeHO_Nwkko=70?-Sqt;>4wIzjqk+dj)rl2!IC!&oq_
z1Grw{lPtgy{YDvI*<&7&f12rTN_44gmMt+-v^pq8oO8&Ns-*Jt*%+^%QOpNbu(xI9
zJX_C2&K-kjTw6f(9Ply*gNukEBBrOKGi&e2FOcVrS}l*tK_){-0+C2muJV3@U$50i
z>lqD)FKZZ1F`)j0V!KK|@K_n_YC$99Y(XBH`vT_%qD*Fd{>@rZ_#x4@r#Kh_Vh(G?
z0rbv3)|yCxf{HAM$t@z#LS9{2<0hWSH-ja5r52W%7Dvcw&_1-QB?zHVv0uxRx96>s
zi(8vy0u*uk7|q-%ZDluN(Mjf8n87bp0Ym0gBI!6EX>Bo-(XHTn4kt@AWC5aFYO9&A
zY=g|M5M5GZPsU}LUM{AHj2L2F4cLX6)`5Xfj!_7Q@N-pR7WNb<G>dfT469j%z`flb
z;e}qCkkqEE)#4%Wi9@MHR}qBy$f2x+d#yxd0SBO4afK~wT)l7>*IaSWFXKmpwyv1%
z4|EH3=xbV4t|6c8_5GE{zaoiK^S#gkPu0hhw_;qw5B+f)@S3W_BV_AyR^{&qQ>XGM
zQokq*X3PZrf4U^3_(*N7fGL)%tvf$>0pCu(n#5Vu-uqt~c2_x8_!|A%s4c&c2e}J>
z5u@pMJ{QCMTE4mx>=m|0y|$mh_$a^dGl=iaSO!4=!JpTY*4!#*7#AMGZ<Kvw9;6n|
znvNDbt}9+ApQs$`KazRbTCuLFpcd+e?Ee9S?H5P=6Kh{dI^20i%e|7|ukbsNSo2%|
zmD<)$k~qlVw<82%qP7Nhj${D;Wj>8h3@^(+zp>H`f*h1^e*hs&@zuqZ-=zLOn<TS!
z3{^p?G;}eHsiztu6&{W^`mAenk&P$gQ;cD(_uiwv)>ubMB=7!^`0({PYQ@M6g=@7h
zN#pTUQi4K=niTK0#@Z2{elK&fzmy<>e|w!xPL`IPoGo%ULlgaHPm2Gu^Y(Gl9GF@0
zxA=cr>?GR1U$C<BXE9ETEjq6%{rohtlsNP8myKqV|D{r7-6PC!iQ5kTX68#*(5$AD
zc;;**zavTfW1}M+5-!I6?w9vi`J20P#}`eyeD%XtAHS%`7C)q92LLFusIB359!%3K
z#K4KasAEX}vcjnLV{$LYFyK`mZoMFg^Ukp<Mlp&$wtfoTMmxIKeXnVcQN~6ZcH+Bq
zTWD6{@jpbpVzGi!XTpHbZc2R?YVmdMiq1}En!0!vnCj8fmV<C%JO(7o7Z&4DZ9UP<
zcKyQjmOBL>yg18IsKX&$pZ`U^)A#lBeO7jM7535ngPVjX6wgmpZ^X_1%BYii?^Kac
zTkZA_W!BQ_HveHsr?@75VqC#&aZFCf*6CHfoA084{{WnY^V;dJz5&kK53PlxXWQP@
zXBO7K-AdEs+<hav$Jh5+dFr>lWsmHel-veDUT`H7pMYt^smi%`c~vh;L}k1MVig&J
zT#OQow<ER_;8GWRly{6e&A_g6F&ouZkViQRd!SO}7WXeCsIBwy*h|R^$ZYa<MK7i;
zOCNZI_06u7(fAQ2AyT9VcqpJ4@$a#jsJ6b7qrm<KM<8(Z{-Qvko=6+q;d@sj1plv+
z7N>Rn$l+Te!eHZ6g%Z*iUzSQaSFV#|6s5Z@m_J#s38r=*qm7hwLHit|JOQqH(>NQF
z-|#l}G$(+M--Yu0$%ajI&YRAIbl0Wx+^bM*EWE+48hdBM?&z{kiMv0{&a<s_dHUeS
z$sG@cD3Utf_QL5;EQS(0!s%s^cBv}S(^bRRa;&l77NoJDIBC#?aEi{%vu2P`i7Nh2
zCnenNP|t5t^ZYTS(KdSEQ_BJ=sLN5-%wKJ5z9#8b@Syovx&%rHa*!<ll#7f3;B|%j
zBOqyOX2cOmQCU_Xb{n&<l1e&Zi>Q~8tjZV-Nj~btg>f16w@5vCmMh{eN8XrH#eC7=
zOJ)&kS*7}ev?EM)$xj6$ra9p@h&jYZsSO7p&UBQwO;`)EkJ+-DmdqM{3+GK75xA1c
z$&!kp2`cxJT!IY_E9aTbF@)h1L_-+cf)eEDkSawlLiytgRJQ1(vcNOmLJ10@Y?u#d
zbWx<eoa4VEgg}s}(x94gcvP$ls!Eh6nV*lO@Y8AXz>|4wi-959IKJ$}imyFxhmPW_
zAcCX&R8AJ!IQZH@>D~z~f<u)}0(S;h9wR132lmzy^F2nYNWDqdcHf-|O4G8b76^!U
z8%*??P<7*74C_R*DuuJKS8goInIJ@SSc7Rwxq&OG2$C{OuHLL>Dul>nd?fnTs>AAF
znV@d06LWY}cv$*@>Td;-QvoH<lSQ2wC}tR&FyHCfFNg_(NmWy_)=grNTdFXEdr+3Z
zuS90cBi4N6voPck$~tVNRea&>1S?q#$tZ(Za9Q=(iartK8Y-7nG?#fSi<M)$sZ0Pl
zx3QiMDo8KSiX+(&%~bXL8=6k7Weda(0e7%ARVu&5IwM|A$xNJuq4TS%I$Qrpqkfsa
zR35fVtbk^fw*dKh7337l$ew4Lta}D#yADTJ{kJ8ddM!b8s4&vstov_qWbzpd87G(M
z@stYZ^hDs%?UBN@3adbp9}MMd=1^N>EWZ_dJnX`G4Q2NSJ(BP5SqPZ0*C2@_-l~=9
zi(*u-3zdcf_9bJz>?G?O%T$h-ZlusR&R?j6JpIhO!tS~6AVLLoZ!?G5UgSv5muzDh
zFO~h>@Gl`WjM@smPmj3uw7kSJZeGf=@9{L(SiO+W^NwjH8Tip+*6*FR#y!za{zL4Q
z)_6HTV}j=_hh^&?nd4<I;soxuTzjpjyGzW42do*=n=EVZox8_glkKyQ?6>8LP(L%7
z({3x*G($(VDL6gj;O2R_2Yw{P1{`oix$*1^`dpx2d41S-861wluRt+BrwdEj4_$hH
z_f~xwCoH`4BUwUTV#RJ7*C=KAUzzvo?1||jBbF*WN~ezF4~F}tR3Oxx4^Dch8v^o5
zHvHnndEQf7SN@RxZSP+e%bt*1ZfVbVuU>O=OgYgpX}42P!r>Hp)=+9Ikrpe>o7pw5
z=dQM&QpL5Er3drbyY3==90`21oxXCP|3rvB*1T#w3gp<g#PX*|_SBpOZW2!OpYV3?
z3pZK&$u}h7b4$6cl%R}F*}VH&!mRjgd-Q^zgzCWd#SwlE31_#h>zZa{(5m;)B^U=+
z;XhvFrH*-sRZQ{h3%wUbd-`KUhL3W+{JS=S+NuCA)h^Qs+r#bTsX{M?mWTckZ^_+Y
zho!bolY_WzgEs2@bl(K4z-?;l*MI&$^^&!Dvc{E6EbzZbB8T6`ZtL|`-W-Y8hd!An
zew6b6VzWrrXt7<@57bsy(d}yn>Dit)NDEEHXU~5-^-4m7!n2>yi_B)z1Xy|b$YS~%
zU#^n1@84*Y5$ZVi2^pG|O~To+Wn{22#mR}sh;heco=(2U(sfJil4Xt)6yJ6$|9)=7
z?tJ#j;(XB^0G%MUwNpY%3_SDKKGdmK5odn^KF_a8bYLZkQJ%$&{Vmel2HN)QXfV3o
zGJR$@LrFFJi)p?o$Ix!)?Bc<>1k~1(Tssi(vVhVV)aC|(u4J-|WF6EG*#v^EAw!?d
z{Ch%NSTr<0sjV@LL@34o!MNK<laagjTh_ViKHCdtqlcRi8VblldQT-DXBSu7=uoh5
zdo>@A1#Qp05@M4J6~(U{t#ibYHR`~Ox&O|x#h)Lf_=WK9<X|$Z-sT_Sc(QTZ%tB!!
zc7@GyVOBfs-plJW&>sYjn}l0*_U(w+`KRHu2)uSXTr=H_M^;X!vJt2pdAYK<rj13t
z1o>lOTNNvc!Rsk+uoYn_NKPt7*_+BkOKt&s7cM?Ui%y`3>Y{w`_j7?~M?sF?1iQX#
zVnU9AAjDYNs~X=4icuvSt#U?;%V?i&A-dw6NH)eHJ)E(ENSw5kYZ2d*nQYap)8C%k
zq%V}KChv6gykmGjLkulg2wq4DT}exp9^i1;^&1WxL)7fORq3RuT44=-EEK6zrs?l@
zi}4cOLcCT89I~7uc_9>Dr77u1*mY4y+m1#+2ZT#@(@BzZ)APx6C0|c~?<f(7(^cln
z4B7F$v<^EeT?ck#;BH8Jk)K4RKqkIsOI|xdC`t1qduNeZWVHmUBPZP0QEk?AdvO;-
zO&?a8bJ2Hi7@3KO23Sxd#VnBHadMoYy!y2$bk%fPG)u)~Eglshcn`4#L5Ext*YaaL
z-EnN&fK2{S;H~Migbapds-3Eg!1K$RGEt4gW*Re;aT$GMo%fX$J`|CpL(gO2Gj9gv
z8^J=|Z$)o1Wx0wh)~RM?MkoS|z!P3ckVmY9gWr#?B37mn>_Hwvv<BwgB0rNRRi&QM
zM7z?j;6?dL#R4_jJJi-Rm{{Y7ua=+u6k4`G^)!rX4bE2h%_5XQ&86Bav>*5?SK>p7
z1Du3AEkZcW-QOt|9sS3e&_-p{K&8uE&rv_QodpqZaOv@O3hGq{*~y-0_5&9at*|77
zz;7!F)KuQPtSK;)Nb!g;=l3!gn02jP6~ScjjQPCFOou*YFhr4q7BXf4Ya6)@s+O5k
zBGhe7BC2fl2!;*I?M8BPE!I^{jZCmRrPs?nwyPlHcmlzu^q8%3D(emqvo}@}kv=^_
z9{a})bY@Em=x%rnwD>D2zz>3UETOzKDFU9g(oX(tE$U;t5#`xwm|xfz5~pK33~An8
z!yvnHgYSFI%R63$kq^uUm?vM2ESaQ@u8#zRmXEcc02JR5d%?|MwNd}x#LvgOHgLK7
zgQb6s&{d(m5I)A0eC{j`#SE#ow!<!(X4&wxA%{*L*LoL;-@56?pxdHqcuqW~!DYdE
zCD^5SBD{OAi;85vejfvc_5rBmC}bh^SG752xX-f5`|X_4My@~^_l}RjjoK$0cWSmX
z0MKYyAeelt;ktZXXq7M0#gbMmFC!`>JcAs=K>6R!UP^!V+BJ4tVRGr`VjNzGOn5uC
zl5{*SD&1oBuPyET(Pyf9n#)J0PQ7BF1?rHnPRTmC2g3T?*=f$cBxgIR@S+7ZQCKZ+
zCE1PL){FARv7gL#&nf(M++cO*5BBJmS^7*`v3rv4Zv1TLq_z$P-+B_&Z=Dq8Uz^z4
zKaSJCho*j-QSe2Um-UsME6$~Z|D!9aH+gB3X1nTcwEQ+DncbV&^r?hz<Xkj5vN~VP
zc3x<t_UrFuaQM!02+2g2eZsNWc4~Lv12|j|av&Rqv0?<ZwLN!W4~rTXhskRn-;6Yc
zHN5gQReu(>(ao@(ZR=m&!zA`%b}PQws|;a54RTYlRDe`F7~FUHvt&tXYxu@U@aO)O
zB|38(%Oyr4VsoRS?VPHA^PfUPh|*4j5TUz~ENW{UkjfKHv!2>&jU%Y~2ZC;RF48Y@
z6zbUd$<pKOw&olXcA_x|C^jmCO6BNnX?|B3H$=+My&`<}$__ipe%wVi!t>1{yY>so
zf)l}Chf_G4UH>bhKf*bsNmjj{__bZd!*55Sb@wD$c=|Wkbor<yereSF`=|!{Ut~Y}
zUUY7$`olnq+S+M-?Hxs+iYNI(9j7PC*|X~2{@G!O38&l0M$jLtV=r4Hox(wY*W0IY
zM=}Q9gQ?ES4quopbT6bYL)e=KX@%3{MfM#aO&^N`d5GHS#vmtbCChGW1@EL`_0(2m
z%lz^-0vf^6yY?rScCNzb84BreGjUaf!RAzC*zaQ`d}yUYA59Cc-+Pz+v*1;;3cKUe
ztbR4?*~{_soR4^aO}0<6U+8`^*yzOHrY7C%g1zmiC2Ppfvv9K<sE%zbD^>qMlH8?H
z?V%XEui?!xnEJn9WG`8bspc>6Lf$GUdKQ#}VSstsJa~bh=eHFq0x4m1&&(GAPf8(n
zmm{{~@F3x!r+zgY%X+q*pP=|&Xxg*r>3fq<)f^M0{juF*;iG(Qa_3s`<tpBS)Yb_{
zAfZEo5XsESJe<cD|HvTvN?Tdc)uaG2akJI*UQYT}J*ZCWb+Qujxz9M-_mv8UVA8=0
z$RY&?jTwH6v&<i7Av_d3M6KofTyf$>?3nv1A}^Ur6vG4hqvh{2ACo3)TOpfuk>}V4
zRRKXdUk%CpbM(q_lB#S9Tr`I;GODEn5Hx{RId!*WedeI8R5VyWB0GE%OU}$(*qCN_
z@HkfoGT5o~*nb%Cm5$9a2aQXOQ_57)^(4iB9bw6n=}O0H)m}Enk%115PQ$tAr;6TV
zI~}pZ9#%QVX)^^w2j9=JEX-kn@qs`*A$q%`W&3#BxhGKhDw!aQ=*)WA2Ee0)JK;#i
zir$t38_m-k`SsGSnJE)M!pk5_5f4n8%_|-0WD}_+U8!~>{G7KX;`WC}q2q$3P$w~>
z_#mF8K6!#HDe>nT(&*63ft6zKs}xNr7Wfe(uuY0Z+W#Q%>g!c*LJf+XDScAMv?ld?
zjl6X{GdCAgA~fe06rS>PBohJ_p6oPL&nPw@!xbV3`YA#I9{=-L`$FUlM2iZM=c!)}
z@}CVJFBnUEzI~s64;><?FyU9rELkO;NMY1T08KH7ZVXmeM3tG@fM6y-?vj@HuCta^
zxgRXxMcu6=>b}apwoCz%&27|G>U)sS1W9&fNsy3E3i*Vh(3*V9=7<Z+V*wEhWgwgw
z0dYkPtFG=RIYvWZqTF3k7=iOV(0%Yi49PN6s&XsNfYDCPS*l3<y3}(!-?iW@fin+^
zQ*WN6fg9(bE0lQ<2SJc1p{3-WfdS9T<pwZpE93f0;c2jR87x!~yca;B2GObVX=MV1
z6!&5J9Re}}W|Z~b&Zw84tAwFsuR}dA6D*1}5MUfc-X;VyCY)7KNLB&WBsesJgr^KU
zvps>gm@M_4?kPRj#wWWr>cfb)bT+U%YQsRwtdn5u4tai;-EL*tiP5g)P*O)Z+Y@$k
zr|^oBr7ukw8%BJB&q9?qy{&%&35Q)?0?BM0hwY+;T}MqT8&3DIj5Fms#tSH60;T*i
zP=<l)tU^2+2AF_Wv!>G`syM@GemglUdCGJ`QNe75Dj1($fLExBPKhW}=4IIi8<Dp8
zZgY%8f*XjUzNLC1upVqn;fKjskHFTauN{M`p4((*XVeYOHl(pNsqF&W7IG#>`%H4&
zj+i(LZiDRhurs>i0d)pzAm+kh36gBid{GX7eps?k1Fe)%w8)$osk4@8gCM2Xv64vi
zivvNl)ZTq)i8cdcp1bH*vd%z2tT)R6ysc%qhJWNNqV^2d*?&mT0O0F5G0QTP&~)v|
zgKjVFh`9zGmhuM7FeKF+DF<Xf_sT{udI@_%$;j38l12^2YwPeE0M)|wT$P-Q$(1pR
zdSx%$2&v6t^>d6K1A%0{&i9Ryt9G)?`)PSRN;3;HG2lVcXlEe{+z(3M<meJjACP&b
z8geI`Pw=S+Awr0xV^#xzuTwC5Opq+&dawlQvx+k7O%!yoYNwjLrC2qCAwU9j{DH0+
zlxi0LVkb&i*8WfuTu_mGx};gemDcs07(;o}1tUQdS(TA?j_|?l<>046k10_Xb$p2=
zqgU<id9D#2<lbn=CI)?#5e4iBWiLd8Q|d}vX)1079Uk>QM8!_+zw?8N=+!8B&#-2`
z#+{70z|jnhC_vyaOGZ7A7!4tKQ`)oQM3stz197bGA>i5>Rwr#?QNgGJ`TiCbkr7PV
zba;Hz8D$rGfy|pa-H=*x+fyVzZ&s>dtW+_FFd5D(?mr}nQ~gA^PTd6&@cbwi)i+n^
zH}At5K^u`}H8qYz6xRm~*yE9QG$&YHd}fQ_OR;}}a0Y;bicpGA``U&>)nfx(&*poU
zK~GeceC~84Vk>U~x13g%B6QK*qa9f!%gUI*^(@hav<E_3<wAI!ZO9=BB34h0v5_~O
z)Q)hO<Du{%Cx*9GSQAGTSMu%yL18`8p+^-z0*Vz3Mi>m1>GmxWS~wg)Mv4)7&**6E
z=CK04pQ;K{{cq45dp5RD8h}eR*SBraV%(P)Wu>5%+@w~8#fr0uc7$G}WQH8CJ>T^1
zV`GupR{eYy&V!Ve32WT)wV|?|)T-uJoW6b$8pq!hSM>4uQ7Zef-3#pb!1j^3VuEjL
zR1ta<D%Tm!ynK@~3>^MBjBA3dTyyFY|8E=z&Uz$%(n@YPoQZk$MV8p7lC0Y?h5{Dk
zvXc_xzoyT+w1+P${orTbOenW{B+NHc7>@C-nJew^lq!$~JK}g;J(VU0ZpI=Qaq*#>
z;dXOLDR&FpT&#7!F=8X<Jdo}Qi-Gf1DDRVW?5?$FS$BTM@y;K!>3li+S4TJB(5uLt
z(M;`kCHcGO5#_ks(!p2dk$)m%g94RIuPhA(DVK_z{9aPV*VK4z&JoKi<^w-pwSjW(
z0mmy~mYsMsNmr7yGZ#zmXE|TQ)=p@!GR+qjS%!$8L?B|XIf%$k(B1W}8P$)XT)HSP
zR({h`Fx$FNbJv?#{Q34A0tU|gsVsTj^GWa$e_qlB|25|tAHh*vWg(o!D%1Vf+nhTn
z<RQR4on*7xnA-h`RQolwFIwE|=`xNabnQ4eNy+(#EAV-Hq9texZ=Q<+aklR&K6XL9
z4<|XLam$;WUHf~KIA6JM&i?l#@srabyY*^Yy6Xq2*C!T}&t75awa-I$7`XJGm@8gM
z|H#QmS7!UNUZfz)?|#x%8x&%32w1ZZU+nxZ{S>P^WHN{a2x^PNX|GHL$h9kRyKnTm
z|IlRDj5B4F@r3<tu29zIi+skkP2rRrH~NGjl1>X%2A%EX(<_$0;|2}Rv7LmYZ{?l1
zk9+eX_vAS?dDnN4B=&F?!}-h)Ud1ONZMyr_OD(<W9=vb5$bWI|EnFs#eGpt9H>qIQ
zK6@oceD71LQ23`Dx%+07NG#*&Ca+Pqo=dWz;4!MP<C#4Db9T$>qn5QhsXzGZ7kOJ-
zPSenVTK0w9|LgBTja=RQ=@+O5feQDllXhI+BguvsAV$aE9LnV-<|l}MqT?I$q__nx
zK&_^O86K87yKEoz+BolS#DYRR<rh7^{z~dDOTmFVb#?C9Yg58b{)qipay|1_e6;z_
zP(r^}HtZ}fTYpIPHOUEGqMDrIIDt;;_uvo*Q|)8P-ExoI{T7?HzYMZ7f?b!}<3F7Q
zeKWv1oa0@2y7`6pcEtMm!WagwVS==t_@sPmd(>_Y$Pls5GO2wX4Mk8!R?zIiE2}qs
zc$GCMpq-wi0KKHulJm;UFVW)noJg|b_-l|sJ84XiEA!`g$e4F_HQ&#^zPg}O6#7DV
zlx+K|o^ezyomUIn0*<=jl<?31D=rT5F_T17IRP7;scKH4lVm=aEyFJl;6C`MP<uXj
z(uBPN`-7{3yVYZR4*UY+pH7hUAjD1s7oQ;}frwofLUs6RgVA1$ot}?Z0isZp4kOXD
zC+5BEG2!snWe?_cZdc%X*<`Skn|A{VS?tZyF7rs7X;yGV;`5`50kH)A$U~(F2k{va
z=8>Nuh~y@el6cc^dJJLH^v%szt*t^&HO%yC#{Aw8D(?ns;IxzQJ92jT#bb)<p(<YF
zO$l5QpZyKqR|%C~!ZpFZ!@J+$cNM2)P5ZP&Q-Rc{F1=ucdXqu+07{VMN4XwE&!He`
z_<#l_a&6K<{*XbGtFrP_E0g}I+S!8=N33HKh?14091l?uS|~X^oJRdn-a_%2<%ehn
z`3R1pS78X;33|e|APgmPTK`jJatKO_4-=HrIkI>eTVc|cBK<)2y#kbl_$i6InW*`e
zz1>bIef@eu@YpTsx#ZXZNVe`}delL@TgZt``4Wn;B*{ipZerV{U-X{3<cVUB^8<D-
zR01iAUiVe`?_ll|vlVdBH<N_Ba5xHxlJX>01LI6!#XdymA<WpOQxirZPpLBA!=jUG
zMgq_at-vK@ev;c`!U{*ZLy#BlK_F64Wn7_(1I%*ts7)Gbof5={g%GP>#nhHKa}uE3
z%7=Qnn6l{dOQ!=CL71+do2K8=eQx@0v)zF!M4#Ayt<`~&Ig(3m<BqB*!Zxlo4lz`E
zD@$SYO=~*xw|@aPn29($2FlPt^ctEr6POh`Vz(Q%jPF`ZQTc-^86@K|$MP=3S+KCe
zquPeR60IwbM4N>!DAPAr4!ctL31=K0m8GnGcYb&~iKZr8`&^C1P0gh2YnL7Pbm&=!
zdzPQ9@aQtOL%6nbr-7LQBfsZktys`9{ZrGA`0$P3cdzpzCw}TdVP7Orf;(~yg7Bpp
zqtcd>m?ykaJ0EEtuPB=P;F4uu-6PRja+AK!hgg-sBT`#i2t#+O_yo1JDg)eoAY+c^
zcf|?c?XF0=^I4#JI6vp?nUOf6D6;2jwvHuVOGr&{WU3RN<;85&d;qK4#R$sF8g}AV
zr;uXq{W!urHq{&F@+;ftxu(tKtJyKFiw=g*XTNJ<yu97%N_TGyPT8qsBJ-{fCN?K3
z!_WdPB)h&IBq}N+5G$)P#-Q`S|KsAKvfhB>gdoQwPch&!gP;8DUlaV+H}WytQ}j+G
zD<=HhI%^5~NaPR@l3Rb-#bo0PW>Oph4;Sv98)y&TP9i@O54<w9*7Mx{Ng~<mvs9hz
z+?;QR)3_EvMr}p4qBEtAEBAw-aA(8t(vQ$Det)U+6q27Io%=tLXPxiv^%*48LbLo?
z6tC{FIn&4}J+kzo{NI0i$)9)&$-a;8C$7voJ8_D8RY7r|{>VdC{`oF@dwR-W*$!#Y
z6+_RR^;)MdhU8gYM@3@?@Y6HY7kzm#8~ems=DY0l))4eu_-QhU_=n0R_#q<3Q=#jP
zIDr!tr;x_QjQiwo^Zen9sIPM))wea`xmB*FwdE4UJ0p%FNpCBv-bAjQAvFFDYAc^&
zl(x((i4oIb#&0x^e%wbj+KyhB*!kay6L7P$PT10sYmzj-obQc4b7^V|A8?i(z0en0
zBN(b4i{Ws6X64WPmL-S&U0fBL+jD?+_c<yOIWcm=Wt8s-cFl{Ht;q4azg-E$mR^-|
zEq7wKJ)3&ts~=hWPnYO@o0dHKSW>vJjpWCF?eEx?QD))q(JfrS9OOlWNpTE>eQ&np
z<T>XR84MIxhiy@Ovbu=Jk%2@u5aM9tIWb<H_uKGCOov{9>!KL2R-HejBOd*O&(LHv
zdUlvJu+(@6Eim%E5aX6F>C2<{ON~QkCqc=M&;*mPOVbJ;u{hH>f!f+djkb{)zSHae
zGDI%T-jEmJt4Ugn71I-)pP>kzo+p?uSgfC4RFPkr&NiRpS{sddiZ4>WKTsK5-X5Jj
z#v2xMQov(hQ<Q3^zghP?r+z!un3ESQ-)4#52e)6aPv<iaSQf5h-u}@`vq`>;wCq2^
zpue0hiT<R$z&p9_in%!rUN>#y;fxOFQCnN-!wvU-!V^Dz$?3IppNnhZXN<jrrw&vA
z)RPK)&tg^kt?tHPnifZnHGFLql&+F~M7Y~{aPk=fkeYYkrNpi!Sn;4#A}<7Jf*Y1&
zaAAj6gV`LRn-E5kVO{E*zB}1M6|n4PnFOa6>SS|fx;`PSdcRdjq+jY8Y41}4;LebB
z0L&$hgE+^coJ;9zoc080?K5>ol6R%T;8ewfn4O{K=pa5uR#zZyEKLR;TY<Yen*?w5
z8fagtYiSQL#%|ekEG?-t2E%c?uf=Aae2bGEOd#;{{8ZEt_Vp~4^Ni*QFGbibaK8br
zXG1GMpb2u!qL)lpw;`;{Jx=da_63KSuth#AXJ0e8)CcYMd(hbIjoKZKIBdA6hg7NJ
zM=35vVkOqv7ilZm-p@1eIN`8{ojB>Ls5EgA6Kkr8-8>3awcsJNKHx-?DwI|_Zqu?j
zBMx=W^eE^D>uT7CP%nr~{$7bAavq7-Aq0>+pc!OZG$+P_UE0BwTxIT2Ws*8nL5d?D
zy6t)F{2UL6@Rll^-PYY#RVx6|Ljh&YPNzcI=zXM;cQVpRXF#cdYT$bIA)eLAJzrx+
zbyO8eIiZ*-j0&<6vOYRHRnB|bXB*yvW)FUi{N|q~uBiC;SG%pTrYt%0IzpHRLUM=E
zA2P0X&?K4$6og5q;R;!t41jz`JIM|UAyz-HiXb&{D|q@{!Ga9OFTjAFtX)>R`IZGn
zCEX=mKQQe`A%GsCBN0?hfX6HugTh3wx};2H>fKgu6E0~EAO$fy%dac-Qt@3Z6zqK=
z(C<b>&qY~_TF?Tp$DWqXqsp6Hj@;y_f`Rmz>UpNaCIu7&!4$L}@FtN^&|3VQ)m|`z
z<{+RW7mB*Y>w35_k@f7=vus#*yH6ii`GaL<OQSZ@X}WD_)ijFhb`M|p_ySXn7@8k{
z&*Ea-X$c>^$u!5%{3$YJ<!3Cli|`o&((<)F)<-+6U4!d4qlAwlmg7^k2kKh#%+cEM
z+;n2u8Vy!%)YkpaDKX+oZ5<B2bvuiOY!CZ)JdV^GBaw4Wqt<UWmygbfO2@b!AlR`t
z$9(O!w;>=w_yin(z??0-g>|`c1|v?LCfz+V<Bj*HQ<I!Fe4N>mqj(%2HUs~ss36Z&
ztH_Z+AEWvhTsh_|oM)#uag{aL41WE*&E8})_zX4)b{8v$nuY7lsj<3#c;P<r?hyCg
z_{aq#`Rje`OqP<1L(UA|kDT>NdJ4VjcJS4ulXTF7=(TQ)#|0FBXHX5l^%w1GC0{Px
z;J7*^ChQgE){AGPwk`(j6Tk4vG&%A7NcFD6l_e^O-r9PEcE)b2t&K@-{Z!)ILB$*d
z$fx_!gilAHO|8BovGTKwR=|C)caw1=a`$VZ0NHK*2Q#kIZlorWzWljN(=?YXUw|I;
z7V~B2;%s4M*7mtk{6EhjutR^EF_ldVwD#=s!(}objyLVvbHCp%I?s<grO_XfVD27-
zqW9G#%JQCuWD_CCj2|E2+3NKP^4t-$(i%xgJH_7Xb{uwXoW}jo_1~dA#cM>rNu8na
zi}(uIXU<vpw02wXFDqp)DAFuy>m!myU#OF9lLM9k9w@T6UleoUs9+fsT>kN!XT3=L
zUvFSY`wq!sZ~e({XUUAQBBvw%&s>nVZ~FiQ{{Fe?=-M?NgaObcTntNX9esX^R{8HP
zi5dRPvA8%Cf(R&Y(-*wf+hZ>v-p6*i4UyW?gH(qZvwOe#nZi9$*cI<O>9aKi65jfz
zB7Rzgqa(?EFF(xYPWW{WHd75qaHD`k{*2ING@bl5$(?had-9goQib$R;#QzX+<<h$
z*3W{PSZQ*nBb8bzMQt5<a6HWeWhb3)^cZ(?YVmFM@T=(j)OoINvJkY}Iuv9i8^Gj5
z*9fEJKj=mBS=sRMUF7J~*_%skjdp+PJbI#>avfuLl-*WuPqR_izSP<JX}cW}{|v?m
zJ$8#c`SvLdtnZhEx+5oVT+(bQR1wbBN7tH53rS~uE}3i4sK?@<2LkB+PD<%GIqu*N
zth_Z&Ol7Wngvj^MyNsPp$9$blBrmYUjM}OXgLF3KQ>AbwbJl&_@v#e}*VWBLG~Mm7
zTwI?9Wq4rP;bNT%+v8*m3r>e7r}?ca%tr(lO>2b{SX#_v%gDk8ADt?^pP3N|(Fob}
zhDa+92!&`PYeMoB<rZIT>M+zsr@AVEM13aSW8mqA_s~+(RHTB;#3?MU+&OvnU<rlO
z;ZWMk(X-~Du*-0!@DNlFBo8-YGv=z<&eAIK3T7-eqg{6uE-fWbW0Kf*29(IKK(Jn6
zh{^>#oCe}1J<V?iC&>#|_|S3Wvv$jGqJ>fNb6l|I92S~Mgyboj=~##UDs6OaMgms6
zOB9H%tH%HU9qMJo8VfN|F&#n4R$kHRvYh1SsxXpdYdhMPVl1qk&7q@*w8N7m*i+Gc
z8%*aZu%9Jw9R$@eNBQ93M?hXvPQ5$=Y!)tdfj!Q$y>wuN%qLuo?S;a@flASvvTVr`
zmt2`y@<_)fi-J+JwG5rUz+A(bi}mQyQkl$7L+@CYoaQyaIjJ>`8eGpJ8U)w^zt}EF
zr(8*pF&S(V8WJ|U6RJa$f(I>vlc|UUz=1Ro+dqedGX|3dRdB&H+pu<$tT`O~v=&zb
zjPMPS$WXSpURlPqdNDy^4U;MrvrdI-&jgTYC?cc+WdaUir<5yL4fsUqBGOHn!WsO9
zD3ldNC4yX3H$qPEBVLg(t#itOW1w>0AT<bb>ndk8CY-_3CR9h$Bk@ho9c^AA0iJ5`
zJqu4y3SPMuEb$Bc;u26?2XVcG5o^^G@{GK+Hf1BPGk}*20#i%E+ScLyCS=90f{^;&
zcOX4JYl-D_Za`|;xLAdm-HdkmqJz#d@jQ%m2p9l$HhqOAzI(9$8Btlr$s5pdxpK<U
zd->xvLZPRR99Yg=&UIkuXpx!YF415k#7@8oU}?2u!rjGyit8vzvVi6A?+f%E$RdD~
z5<}n|G-H~2nDM2==ux=_m@t=?{|ACSg{_8YYwc&9{k>TSGs`=dIfVuL(or64&?HB6
zPW^r9RByHv!-W%*ZpzjVViH$jo}wc7F>3#pr+gK`hw$fAdd*29d@yid`^#zv%LVb&
zT*s)|sIA(1zRzA)w57HV%ym%fyN6r5T8)s~&81JsC6L+2t(7wqYzEWmGwP=M)kRCz
zr-&ifcU_lfc%o%KXkJtt7{U3C%x6zu2q$}-GdxDWv)}gE%RFn?j4SPPl8JDIJ<SDc
zj>!EXDEP$7@}fH$-=5BG-A3sa6RJ(@N9^Tqx5Q(QEsEzL2)64DtJSn$sC8Yr?HDTC
zR+UBp?(oS*(pdUsZaDaa^Y$BGvE%O4Tue5oReMk*Ty`5psy~eWb8c2CUUXKzaIuwF
zUX8#a1uJg7cp}^X?eW+_*e|>`wG+=LdZCqr=7;VG96n9rZmZN*?Y4&dzhdL=U|pm7
zC(0ms4Xx@QUml9P4qC>JAldSE?h9$c&6c@cng>U@I(vDG=5i_t2$ofee`sAV!qctP
z)^4Z&xSOji-~J}&XZ}5rKF_WWx4kSbzSwAV9()hqMp?D#uRq)@9zUyV#bpQXOIou7
z*dn-d`1yu4er+^%c+MY^2t$k(&9gp8U6axyISd19M@QRKhD(AMwx|J@o?^Rv{EgfJ
z_7miLy+HsPJStew-m1#jZ|t`A?tk$!ib=9VWP&{_wB=@RFZY65Ugz6HhVerCwHb$m
zgFNgr7ba~E370{RKmQ<GIR7JQ+OMVNb9AgXe;_ZiOIX)gdyB#cgB$-Q(oz;CuD9fU
z_g$Ki;i7ln(Fz)<@@6x?@G|R4!;P!$|H8o;zTv)KW(5B*^P~m(qX*w;OJ92d-z#>d
z_Ez3ca37uW;Yl+8$NxEL&7C-E<BfAd&i1aaF0q0_A81Q$efaqOp(_S1MZk4YRB_fh
zBuq!q=|f>l5ZSQD&JJcbM#eWojxbz);gZx<>xb6WZfg-&_|~Bhpf|Gg6gMyFzQjtQ
z0A@>p#{f{Wt@@C#I%0S7(kc`5a2%WosIAF$qS11ElO_4fuqKC{+Uwilw;SQy)}CoG
z<dUbCxt)QN8|&vMNyS%0JhO3_mXM%%$C0D^WArRHM?@A)<Iv`JlM?}ZboZsX4nQkk
z)-7eSl^S&7=KLhHX+xQ1*>UN8J{f(ONZliAg?%~U2I;eA-KiUWk{-{UE@_-YLRxg`
z4{&Cvt+S@yy@s-9sh+;z8MgcF<f_orx`JYD&V1@-+v~~or8T3!fq$lXrBHRsld=u6
zZvpb{wm8ph4bfZVDjQ}@9*@LfP$}a>O{XxriYa*lK1Z*pKq`tNwV6<*z1Y3LGe1cX
z_B=IjUkOHeyVg}|nCAH<eqt&D8CIq%AR0lbT`9|o99SmpU%*hb&sL3`U2x0qb82XO
zi`SU6FLhxvY|v56GXW}`H?Ig4A-dx2@RXd*u-&t-s|EYZ^nKgXhHD_$vLOb>ZtrlW
z4OdM}5R3$ntJI6Yd#XAk7r|$WH6-LUW)^rUiHHK1wJ5El==+FDiDbK*<_sn!%1LcX
zFLoUc$tsp+Ckh-EYYK$z2tjqET`{{FHM5V<<947)uUe@{kQHQU6V%tsTJn=lUtEhZ
zB32Lxp1wtQ>~VT}@**P#X;*x9ndlsXnPgrYPYlknW)jdB=B#v{47G(7%eOE3P=Ow-
zv?|I$_!6Gur?saFRO(amiRT1*zI~s(@S*7ALfVq7vZP;lqOSc4=bUCsPr-2;MajXk
z9EC00k^-p$p2q;V+V~C?>qmR(&NJ9mOWO)k$?qmWFE3lz2=UlPDPtJrjc%3%Hy|)d
z$T2fbQEQZ@JVp{`=q}Ad%!1R>#-hjQ3oZ)*94DmPNxG1w>K3Byf6{=YKRv3_5yWS0
zKW!YR^=ttush6|jX-mLMtRePqn~InOQbSNt0b?67M>z~zNy=Vh3FmwSF7R83R6Z{;
zeZFtY%CQ=f-yp1H<?s;aQHwa*G^z>?RdsD6iu^WiyiJXXxr#i2kyU>$l;$KfVXyM*
z5BVy1p;KpJ!lrwdQ+NBv+aVOW#7U9fZ94sH7+L(f<EfO~Z-dtm>4<!;p`Tn|Vm(+}
zg!csIUL5q?_#~t-c7jEbT=CwXMQ`bBpC|el>3CgOOwzor<ck@eV*<kPpPFZTMKi6|
zno8q(PVCN5L@{DNW3re^j_uBQD=Z)P<6J{mtV!&O$b;^tyuC=%g%a!a(L<iV$E@Ui
zsif=QolV%+LiCfdu=hZs)(C}mnsLW{;oM=IU6(er+o}*TpZRFt*$B3KUf+%stviiz
z!5-9VKW=0lef9MGEZx$N$-N^y@$O*zUfj*J{}mfiJlOdYFZZZ4o(>O?{G2SPADl5I
znU&YOcy2X0_-cE#^q}WYFeE(j@`xqOok2{d53v{aO^T_fRN!|TKM&*Vwie+Rd9q2C
z+f{#(q)~01JV3Cgz;FF|P+nwh;(mGvedMBh5T=CR7g9fq2G!NAs_i!~!fU&so--(K
zm-4#`ooiw8Im$wNb5r;*dYWH7w6+>`ynXKp*8b*l)tnWn^{#WAq`vx=Pv$m%Y>zEG
zaK}FT&)-WeFs03-%$^-th;vQQcZ866|Jr}HcSf`pcK_L``7az5a_kI)Y>|{KV8oy7
zJAy<J%gN|KIjw6C+$gD<lMw@?w#tEb)_XCO8Ghv>MYhrc@yS2j{&W>dp?v|(+7eFd
z?A}6M5uCcQr*+-y$9<h_r7bg^Xcl4SlI;AA1JJNO<2eRz`!BT7lh*{r?+<~_d~!Ls
zHQz*fKbqU+Uw;Mpa>`rL`oRUZ{Pa8WhvQqi=>^r{{52?Me8;{L$XBnVKmN0o(&HO-
zgq}dOA?v<4nWV35tY$Z(jJw-E)9?<uw*Q;f+1m2)dMO0@>((DQTRwgki~Kj_54)G*
zZ2I&KjA-g9%BsIhbtu=|zl{FTP(V~$H@s?{FTsP^g|;lV?6&6i7kDX>Q&>M3QJL+|
z7oa}T!xPa6>y2(|-wl-`><U>-<PXkHotwt<NHr~u!Qlhx($&QSHd~$_r%+X#oy_)p
z@$;X*iNln0_Z98@cUXnK+2~aR_`%sDJW3s#r8nYDGd`osLj{u^|5U9^9v_`5JQJcC
zg0`O*bn2&Bj<KLz8kKt=^e$qu^E=rpE`WQVD*;E>nT@u*U(N48;+o+t8=`nAc1820
z{x9+2VEk6UjT5)dkUjU}ZU#yMa|omI*^)pWDzBjZVsFX7+UbR_p2EKb72m?{rE3)m
z5O-N*$(Zgs=5IlcEmenGg`>w1IzgCZmbn7<jAI3s5jotfxQaOsWu&=aD#5hZqboEN
z=5kM%!(rsl_gEvVL5c5Mn_`ASU_PUWlVDDReo**=6V;=S8JK=UtB1Jz=03PX24&#U
z%h>(=n(yQMa$UE`TWkT2=O)A*`shUd4oOItta5DdCZTxmHu2AFgSJBmp$_dmySP~=
zZ;pq=stI@pqSkO#u047NZZTHx?eawFoRRd00Lavllax*(D2nGFf<A+x6-w<+kK&X1
zD$taa3l_j4YHHcyTGEz%1DuW=8=ZPKngvIM<<BFOWEE1LOh_?`-%#3!u!Cjyo#w{l
zstQpfAm1|pzS|i%15RWfwjzZt2&pFN%Aq&{LNqZpn?i<bO5Wq-*vTSrGSW^w_ZejG
z3p4;~x!Z>0@H1-Eq{LLh#c4fPz#FwSo~V|!2DcBEbM_hP6Q@1@Gd+(KJ|qeV=JjZD
zh@nf&Ye_J*uI98%NC6?O?U#*EaPxG&p+dKPSsB+bVn}7=94U*C!m#7?k~_(R%(zbF
z&)3sLuP+=A+I>__P7)ub?sun>^xp_vFSg1z#Q(|%`)S~DJ1S=dr>8ul41}@KUU<J}
zr~*%`lqzw-rrKJ$Roj$oR<&XzjYIdjQP8@ElSB1A#6C|C!yXP@?B!;y8w?$yCv}w|
zq4B4BM^5<xqa>iB3emOQh{=kxl%G$)gT=r^tVearRA76|m%5m*NTL&K3X<&%a8Z33
z`5A&Xyqq|{sFH}tFgsy^8r871|1@#OD930OyxTfvN5r${PlEDx&qOBk6SKNe@1iVh
zW=O$j0H^PAuJ|g6t!itl;ZEr7SUX;~m0skctM0u$w~{_H4$A;i4EAuwX#P5^GkkDP
zzI}lmJ{I}icz4Y4F36r>vv-PxS-WN~WT&RA2zzke1G!!fZtGeS{BwLl&L;6jC1Wbo
z3uK#VJ@HOQjvMz7r)(_W&X##dyO%wYo#cuk!D)R?^n0n%?5=7Bz}&sd-abT1C-y(M
zfh9uX)61uRuTa*VK}DI~m}ri(78DU35Tex!h_a|I5>VA0biT>OsP*U&G}kC4ju4Kc
z2E8nqt$&Fxij!=d`YT{ZpgvprxwwAF?Ss1_b&Un6SU%O;vBkHmWJ@vVMCadAYLh?C
zgyoNx)jT6-E-W(K-G9Byx}U4K6y}cLS6D6JW!&k%{j=u3=547AB4k}@CwD*E$lR0c
z3+d~QzL#uq2l5<ydy*a;rBD3EMLsS5KeT1V5(=M$47D2QZDGA(30he3weQhf=PI>z
zb_V)F?+bp$u9`Z9juSug@QFMvC#xP^@(+rt)EvJ=;vWX?<1ja8z$i*#lTX<lKT**7
zPwsIjV6%*M61hnM#wl;Pv@1DJZ7FW@qR<b9SrVHQX;8h;p{@iRzwqRj!|JBmichhQ
zn0|?l;;mmAwHa+~Hy#XhjI3V#t%PGG7X~}|mK6C70>0BJMU$_&c%20<U^u|I|9k(H
zg@r$UnT6lKIgCE~1@gxJYka4CNhF)UK2@|v=2mQ+H<cG3Z)~t^lPB}8s%7%4H~8JH
znWI@a=X@QBNv0nE);<@rq;@eFrl_+&7`Y?-nm*ffLw>-;D07vBdeO<N4SiZSzxSW_
z;>Bl>sjj0(!OLSiprs*yKKU8Fzw|P5(Q*%yG&WI(fb721oi@h_RkYk5YqHe--Js>4
z8d`Lo|Bla<bvaATX`9?u<N6If;|H?EmU~4o)K=HS-tp;GZ!~hSoR^@T>iml)_C<Sa
zNiV*rvN3ZS^-RljAgl+gZ%_fHZeo?Zt?yA?tRdVGoE8TU*cE1FiBjO2hfZ4IGkdHz
zWAEYidwK=V@;h+Q@7`2f9}ReQ_-%t^n`;M$qmx<O2xE2|i?s4siH|MWz+DU5V+{x=
zf~y`f*>2p9zZrD8Z42IJ2?{ADo4HMVUx}E55qYS5Kf4jwRwshCVw*$WM%YU%@qNTE
z;oW7^*wj$5$1#IpVFCLzzt}`#Tcx2!S8Jb7f+KI<oWg4e@&K|7BJ)@Z-BFK{;wBJc
z8l@`EyZrh?2vx_GaW<C`$U*RL2x$w&tkokT`ShTY<wimFyth7Mu}=2RXlB80spDJm
zUSiMfb=8XLOG1o~f~0}oy;tfkY1G0LLm~62;>3)5**fM{A|KITK085xJ9^N-D4zVh
z`Kr*&oJUuui0!jbNEfi=9gKB;5!PfjV;#=&ZsMb7G}?)uGY-#%IaRGJn0GKXAK48H
z0h|yy!_prDU+`}D)k4^7ba`82!BiyJpTbK*xgXd2p6^Ea_B^&ecc?>SVgFMRE$uQ3
z+!~>eJ>xSX8{BUrjL_3kO@Nk?Xh&UusbU^u^}`p-8de1{o>*3@tMcg&%cDU8%R`ZL
zh}_eRMIi=AJ$IX{D>X3>AJRzy4!Uf<r5JsxYm}HkyZMHXaeWSoV>%U8{gA9xc>T>x
z-`i|^jcs!l;LXG6%0`@+(GAy-mSP+lj$Z}CmW&z-fW#xjXU|dl^?QWPKBCt!h0gVI
z<Hj2=i?kncGFQ{^dW!s7RhlYV^vtA%Z@|8|xnP282WVIR!MfC$UsR53h8^Sr-%r@m
zVQzF>O=f3TSEx?$w{O0yBm@C`Ckwr(w_D^R7eH?_5F~*jwh1RS7ta2tN^)yDS3&97
zYJ%eJE0u`LJsX{1MD>`u98OOqD$pW7KCb&Bk0axpcy0zSuda;#z|iHlV?-zOE$9Eu
ze5eiyUl_9P_iHRCjrr!An9QIKp=lqA{@QH~k4^cJnZ%e*4S+mf%hqoWGwY`;wdd03
zvg(j<V%IF)JrY%N)s?r2%JoiW4IlFyiKA@%yYZ;k?^CQZ+4@M*(Kj;FBUF!OGkKJ)
zi|H(|l;U3DoucRO+?5Sh`0SZ(eu9Cg9J6=YNA~Tu&OcG)YMoHxR;hS?Fg_e~-tp7v
z?zq1sd~HerY%V6LD5x?AezEd6*;SEZ(Py7ZC*;%pk7u!u_6Y`~KYt(&d|l87L6)ZH
zByKBpPm~3n+THagbPL@i+<FC~x`Lr!#Qs+b@X+6fv-VMQTz(vn%&^-^!{A&fYO78Q
z4g@FlXz8XrU%Bu=7SNKFlT_*&S0`omu^Xptkz)0Tq2okNB3(Tc(Bt=T+VH(AR{Vu!
z0nfOy7xxG&J)W+sm1fx!?{<rKgv7!f_f;~x>aUinLLp8c2-)-k)768oW=`>E=F0U(
zF**?<3CwCk*h&1us;xp~I3O?8ZfnuT9yL(16bo=pbT`Vl+-1m~@{Y%bze%p+ast)i
z@H)o;q_&cgLEw|QJmn|_$qE(fynSp_zd4fXUE9ky)z*tGU;7`V|6}yAW51P}J1~+7
zrJy2tc3YW!vLSnt7m0%i^@ncG=4V(AXBEYP%U$}#ReeQ*Pfh-B*$Gwb^76g=N=mdF
z*Hkv@+{$&Op|)D%!#6IvV?U92Nk}YblRseFh3t<uukdp!<8)-Ud-wUb%ssKd#ZgYV
zg045@H2{2a;#qG?m){?vLfzFdZ({dii5EfM+eEFL{mc@1MtBypx7&J8^a;`2Zcuj0
z78P<AGP%ZPqy_5z4Guj|XHr{l8k`H_yUnXph#DdF2Sye}LA$NhP)Q<bc_X2}tLf>K
z>H)P(Jt7_Pa`?csIZ)VbO-2HKeIe-G7}QqoVzz1jg5}|ROwRz{#E?GA`&oQ<7z;F`
zBq<oP_1m>!O6R3=>Ykqjc?#Gm<T%u^#NFBbUo5Z>%p6;2N++a=A_q<-=e-$TjC5v$
z?|ObAetC-=@_|qLh>uC130czqp<!~Rin6q0%x&p~hz2iSbGKD~^p4vw&O~R%5)fnQ
ztDq_(n~1pxxY`|aAsPGD<`9$5*P)tUhy>uGImifVXA{{hGcRELa>%172Fiibuxzy&
zcP#e`uEFyR4l|FN0vm0}nK!YgX>vG@#WN1j!MSiJ+CN!T$p?4bVHpg8BdL}yivh$K
z*?VaucpMH|@D>3nFW*~<xLf&bn&qaoCq*)$HtVIg3A|-KTEyKT@Ybs61Yt%)7Dj{f
z)pC}TB8i37K`xS98bj5+XJtXYEuh&-Y&P482-v3N><@WI3x8=W3%G<~M+83hnYAgI
zbiZZJgTRTZEr+JLePGo$W3j4gxw*|W7<8l#5v8r|C4Kd7Iy&JxYYFe}6#8Da0nnj1
zSLjLdGUg`?Kpzw=-Mj)AaQxSGzvoN0gS8T2?dSFEsNO8eCS~05XtKam#U7$c`7`2F
z!@-J`NM!>dKs$o7&+56rk1+;T9Ri)Xmd1e(G93g3U1DNEBUUBp)N$~T?;{W~rkn?x
zbI`um{r|MR51egBRqwg>KD+zw?%TQ9_okC{LP)ARozS_2a7e%xAwYGfAx(_f!GMv8
zdTxv%D)X5jn0Hm4ue#Gf6C*a6s2AmZ<|IVD<RS0spo5O%Y_8D{IvMAJs0`|7T0Y2!
zhde%a9G)*PFgo8~)jp?B=XUpL@H4CX>|M2L)v8si{_I*+wQHwbhs(s$Q^rNh>mjTv
zw=7%&8tA&Xxmn}|<%E{QW}u7)Qd?pz3AGngb|Ml&<2_Y2(sttYTfHdVo=TkZ7sW|g
z=<}q=8-cldc_K9N@=o$P7w<m#cE1K?y%BypRsY4ZiP#axz`=S(L=|`NvlI>02~{#q
zd5BNg>NvDv&@^xh)4V9HY;+ZUJw>}ynbGNIu|BOtHPi|kwRfAsc7hvCnn9{@p3Tl9
z*$PJm6xZVVW+3zu2qk&iJtsk_?F(H0OF7{d8|68$K(s85Ne1GlO=2K&)>b3$DZ9b9
zvD@reJ&s~zwtk$|*6;!E-0;N1MKp@Ou2gVdsoi%VbM^Dd*GalJju`gY@1f*P2-_3r
z?#D$#Z`l1aVtgUbwAy;#%F)c1thO@IGZemr*$UC6JOb{u+j&Vf#bC6QdlKp1i68q$
zn=tyo*RcyED#uIAR^I(gLpcTe?2gPIW`q;+fAfBu8vUj9Q*ODK&sRpf`Wks0DCwP9
zBp(W!F_-lrI)k^Ci;3Lnwt<?043b$dFRI;#9VfyoY)lpO(HcAdssF_S?nPN?;t-pL
zbY5`2uOlRv0i$AwN7~GuU8(Hvt_35rb?JgiuSR->4u$;D)XxSe^)S|bvwME-M}K^g
z)z*=a4uHjOa%U;A=TT*r{!1&b(c)|W;(6YtzT!-)t@cOP+WcdWAcA_yVSw3c;mTWm
z&_>qH<!H8Q-T2r&HeH49zST#w)ryxg?m;eU4#~bLScf-6jvV>EbvyOZJP%3*k+n%U
zb1OfGA;QLO-_EUdD<4a3KV0T0lM{q_D};Aui!rANdqWXl6aJxzMO2wpJ`yYOq!<UQ
z!pVm<s=7BEVmVPN9@6sQt1NJL{Hk67dORE<1qMgp=b{49Xu?n(R4z8Bg-{}G?O_AC
z8<f~8B|FBw7ln8+AKSO?#~xr1A~RY6`i4y49uB?KGWXF3ZRKZQ?83xP*o^-+y49O6
z4;g0bA{4{GMPBtZUs}22n!-+<r;M<h{P|QQG82xS=j@}87jaI-#oWpyzvzY2UUq!`
z-s_yL|I<P9N=K6EW#5&Yhb!|L-BYuS^2ols>~-evd~Dpm29o@OMtDWp6L`uO0cncG
z>8f-lpjcxAik`+<r{PCJ?R9Nzz(jK9qY^g(0o}&wWXPQZAz?PjadaJLWF>Ac;rG5e
z&x7m|o!&SA$8jULkDG*_PEF!n%_JpkMf;cN>XQ=Ym#tiVOW~}(+6v58Rjgs)#4Ffk
z<9-^ml|^%XT_aSVxh`_vw7asRT>g1m+Un+Hl82X5=&U3cT5a9_;JZmFzAn!BS*WK=
zKEy`$?{_Qtv&*p@(!*;%vW1UoO_UC@+duNqB?Sn(1^eLzHFeE*npmo`=hTlTY^k~T
zZlZJYjI!zxYc?7H%BtFW`b5kwmt?j!HDZfKHH4>96Poa1pWt#rNO>S{j4xJtp+oOH
zK-38IInxbW%Tg1U+>a|@)J9kFq)t`{pn$xZAw4A$gpq(-fM^oNNgYMaWg{~exF7B*
zEbrpm7u?gM5;I`g$J^kAsYN>%J4mtRUI~q&TxY8?O4!_UIR^q6(+>^v<7{E;$itW>
zkL4@RFzCu`rDppuKv|9YoWabv!zMM?XpylwP64w9Y!dcL!)0i1Hex$eBo)klz{4xc
ziO*1}T2grgqItWmJ({8yY)G5}-2*cChE+US3NPX@!LAp|UDFe5$q&iMOK?7z`5+dx
z(0W5Q$T1XJT_>7&XzvBvs3Trkl)Ah8hQbD=6GWx%ZBCAPUD7MW-C)daN3Z2xd?oEN
zMqD78W<q2=<6xH<7-upDyRz*G*b_GLU_qQmh)%NFCyh%96X0;DBkpS2KokWjb=5^F
z#VU}ZvM3qUj3uT1he9|?EXn8tjE<UXW^yuGA_2trjtheytquaqW=@P}_{Cr$SqW{D
zmB$C+h%}KzX?#B3L-Ot8dW~q5OqM5Vl2c{{lEBF!!~kBXUEr<y!1D-#qNE%V$w-9A
zA&^h`loCQ`L0nTJ3&J=9!^4KFQ_x7fD(WzBN|wSDx7>%QCdC=4@>sdNJnVIf@`Q}M
z+yi;nNH*0!M_YKfwDCZ1fqdNd1H2r=jEPNpYKfFMqV!|wv9jhBz(yu9lNzE_%3BwY
zUDAyeFZXO*?J0!q&^!<(eZkHK7>#sPMLpFWPhLlzk)WO#LjlS3!MsU?K(YbTkC>Vg
z*%Sv2C~h1+wE-0mR_dv%CF-I0j0_%h!-0+j)f2$t4A~5HC?w*PNH*1An1SO}iA@!3
zW?6Y7{D#Bpt-O=8n`HU)aTA3qAq&lU`7biwa^No;!OIhr3=^hh;5np4Um_6}k0cuk
zo5ldG=0I7yn!Uw{doaYY(JAFkMSLwRy8PG=2kB@nbF~nul654@+*Xb!DFl*M&=Dy)
z3YkkQ1jnJTTaE*j5nQ<n2RzqdunEC|Weu-Tt|U_l?gs7M0=Do~bULm<!c)prw*;fy
zA_oNsI=U!VR4W<_(9uO26`Pu0gncBdLQ2q2)-?!fI(b7LezA%;a+zFSC_$1sxkbNU
zNI8+f{VXV#Ku4Dt;QM)lT4rsZG$&c*Es899RpjlFdOC|FQf3749RisX!8XZ+_?JS6
z43zDG9?cD^Z(9nU7yrx&rRu)UFE}m{;$Wxe+4ZiZrc&97#y92ID^%ea^5*Gj_Xj~<
zUNkH^5|G?yC_Af#Roq?WOaxokhEM`~VP{f(335kp$l;Td;f{m^LcDTG3dwt3-5ZbZ
z;hbDbCh&`}jl754>AnDRi66@CL#+SuQ@_j$&APH~dqbPx5u}}CbOO7Ip}$j%Zs4M4
z?i_cyIfujRkyC^jJTW!qUD87+KCi$A<&sDR?!7_DPCBzWIvgJdMG`wEJ8C0L@>ej6
z*^?;(A)L__|EZjng7b}JvD*eQ9H<X|1u_JWhFoZ(M4f3lF$SpB%=%znggHr-&g9YK
z#>GxL7@(mOSgKd989qn?%BLbmF@r*)n3l;o1dz-Tw-3H??I&(O(soDEsATYUtQ8h|
z1P+Ji7kVi^foBUG&U@OnD)D25a=JTde;9P)h&I)WKJ7#>>*xumhpHelZu&{N!J<2d
ztHZCz5bl#mDCv3<;@lO&BD^|nVz$xZT0?hQ9K=1hiEflA#FTp9@5{RSQe-vDcpu4J
z?4V*)mwRtBgq`BJwM(VOdn8|yWSr4ogg{b5Arwfao)6kiuPkx@O910P0g}xv_B=b@
zCHr;&)5s6LR1vtISlbD=`G}IQQbnHwVTR7#gKRrJ(gs0^s6YdS8KJ#^mU$DL;u)u<
zl*<Xd=T$L))?@IPT+#f4#pI|ZUK_)MLW??9QCzWZF{BJ69`HMU)+8?{ks4nzx4NJL
z(asbWlBOK&!vg4GFl(K%L?My(Ls0K;N@q8=x&Iy}bn8aL;d3kGU>o?JFUa9_NpMyp
zQXu^OYJ+((Sw23P>juBWZH{wA&#fZeS2}0^31xQQmqw(DsZW#@^(#=IS2_G3w|jH5
z(=B^+S$Y5bT2---vmZdk7xUbBrWKgwEbQd@MXZ8PtHS8;nsv8mx9fzxE_PP@M5Vai
z{&VzUj#;m_;h7tJk8qhM&WeoTuVwz`nwRi$BrA)HeDD`y?<umocwx%RF$Bsp?9j3~
zSK33*(V(*C6g%U!gL8GJkaM9ZfB1E7Y4ZiC%}t$+JUtxr#F8RY0IDtn{#6n=GA%5#
z+)H2>?f?5G*_H3YI(ervKRoTgTWN*!icSf|R^g~1t@E?;vS+f~pQ4)e0#@qxSoW1y
z<kr#2y#M`sX+3YZ%zxp<bJYwDZ0i5E#jqB|7P~#+4_E2~`PxNoXPvdHn0dJ@Hpj^?
zT6X5xi*52F*M((QW;0fubj<J`NDqPbomshZ4fg5!@#)+@dhwQI^?h%2_QX+^Y?j|u
zj32u$`0=+}zPU8oa!+2E4o?VoH(d6Vi;>HQ_MlE2WgDlqR1IdQr-vXG`>VbpWaVo{
zG2*sJR;z$smX0|2NW*L0%~O11O(JDLqrI()Ugc8uB25;e83x64sth^FPN^P{%4a`?
z&LoffEG<S^i)W*rx&=*M&a0Xy%PhR{MXPynzq$6O#;p7sav3H2w#<$VOHtw4TRFqh
zp~d~PTAcxR$$i0|IyJhHwJ!Jm#6#re+D-4h!nADlypIIVWSV8J@_%$T_bmI@qGW{X
zy+`{FdW>IsmSOoLg|njT?Eb04t8Er?G!m@p>Hz5BFn>=s_wzYlm-yVVd~*Fs*82X1
zfSeKNh-+3<1QVN*d;kLGb*v~oyqk!jPjhuIiXkrF)L0tm(L{>fF2T7JM6v>>%hCaK
z#DPinnO3SAQJ#|*Qqg$iX1@*RH>o<=!jtrfo$7=0;c+Aj;VqRDdKl=y>+VcPPt+TD
zg7B$ax~07S8wNukT{HX4b=i5H*AVDm8A9Ym|8MTg8Nx6h-F*n$;M+09SrFyJRj`xB
zn7NfLmrPBDI@`##kOT0=5E&H1;f~_jV*I@N7t6W8o@>6z5l1P#c&_L8X6~_6nh0KZ
z1||JbRD+MmzB>)*?RBX?x)C`dtdhC?gO_%xEPf!0W{oPzvyIU_h<4@Gtz~RpJ8bP4
z3VNikuVrzdScXB@vny2GX^=t01szMMnt=~>=1!$eM`6xAlq8t5S`QVD`G^sSN8BwK
zBc!sf`32#!CahS+6WuFYq<gwVd?o3&mv2QfC-GAHDV9&SZ{k{04;x@!l6lWLD&RSV
z8hSLnJK1N1K|RbnJybuxsUi2!JKmRTWRDS|1>Ddu_|0p%V}U2lI7{p({>%r$a*mEm
zB-6T|%$9XS=zczue}`)s&+h1;v}KC3Iixf|sHoFCyH$C0Wh&KilYW(;*J~j35|x{5
zBojV?w>4&Py@b7zUp4KEVD4opPz}U#&t)hmm-GA<u<aa?qJoFU+Lhq$!H{~;v$xw5
z?0YpT%8hP#05O`|J7NsY-<k^50$v|cC`MW9@XLB;YwU0dcOW5cduAzGA^KVj22>t3
z$`6FzagM@4J_o$E1I9K!1}}_|X@{RWJV%QyR|{L6b&^Y^9IM+TWolU{W+$S*U`pRK
z6`dfo(mGER4{kwG7bR^*{kT06k>IKQbi$8|aF)5rE_>@s&KP&GTzd-cCHXDgqh9xn
zxs}Y8iwM1UnjCKDVk_K>&5RV6=afu@9(~M6W(!MnMouAK7a(`KqG)N9#e^O(tYQI{
zryec2$D|jw<6XTFf{!vOY1-izVCY$t@+<>tQ(~?Z7IaBKmrp5HzKd54HB+fmW(gd1
zuuU`8hdw;aLPY_tm)6OzwU9`ZV6l<hdtKuLX@vwf6yu~~#oYGO+KL>uoO`*B$I2AQ
zC|u9xTT%~18tf?(+GkG}NAhqWe;@vka6hL^lEHmxm_`tZQ`E@9)oQMP$=0CmXcQ-f
z-G9JYjh#7hKfT?_?*e(8V^`R1qAywJ_F38=X6xKi!)cG((d)za&{#LJIa^+7XWeV(
zl}s)z`VnXDRaCUU$<h)lYBlTr<cdxFW@Us?)NkWAcY)i=-tveq>-OQ5@lDjPZ~Cqt
zvyD8@H>zcZ^btCv-MB8^cz3(GcIWEy(d_Rj&4=isY7LuIvdz`Wp&|wy<Q@vx2f>R<
zIjo*Zvn34&+X{f)il~&7(+>-wmPw;Qh7+cW1`>DN!(sfsB0fq|vMH83b{(Iy_>V=m
zXSSwokH3S8-myt4_g^q$e}Bcy93of#@&(H-9kumK|6w%Suh|-+4K~5|qq>d~{0^<J
z(f9quOcvh%ZU$X1b>=t;wK@zoC}^~un|m_Lf90C8tk#cbt1?^js3}4*Tm86Zw&R|`
zKP-J`%0I~a0PnLa^9!cfZNTFJ8%io023~|Czwqjf<+C>s;Rh%DTrWy5wIIZPc*Tex
z{rwQjsjX6(Iv#OBSG^nP<jDA`@+>Q_(dH92nu{k|!G7T`ucGu}6$VPyDR>wZM`;xz
z>T$=qiAw(u-!OMo-)x1T-h}TzVrpLh598rXK3Y}R{-fE;KAs&8e>3azhk38m|Eage
zA`;8pAV0?2on~KrSstoiaTeY`8mC-j8{gVJnB9H)0p7p-b4;FSEsKlH)=NGT>=Tnk
zmOaImgS$`Cw>2WW$PJQGXSCLjOjMP0c8WtvuYK<!7bnrMlbzp9o&mgvmw)3Q{4<*&
zk1>822-)V`Uz1Ukkaq4Y$M@^}FRN=$5PL+Nsx3VTI{&1B%UM@@+CqEzB9$ct|FLV<
zl;N-~Mnin=t<zY(10m5`?oKUx%+^)0O7Q=<!j5CMhF3Xjt>odm?V;SWN3hO6nAvZ$
zBO9}ojx$Qpi?h>x+!i@jx^DYlu@QF-W1q9w!#p!(8;8$XQQR{!-3gp{8yf2!G-m7c
zm#GSRU93A!3BB<(eb%K8sTRq6#uFjW53aodoh^sD^@u%mLDa&dI`Q?q>3)=59X_7X
zeb0IH`|m5%0shNDEm81XW^Tv+G*y^xj6tS!?-hLS-h_P%H%FW*4mCqBHYn}Zud13+
zO~`GOk#;qM?lnl#aiE?*U55gj>svO`5gq$7R&xetNn)=CI0Nspa0&%dotwf{YD|?I
zeRKn%=ish20IAPQ5o;RMaSs`nGK=++1YEx%K)5U9aZo+w{|Jg+f$T~=JfPmPN5t)v
z??u6pcGRS-_t2Dn6f;N_MZ)$dj>M<V7Uga(y1roU+|Vh@!rzi?HR|&i>=TV{PEKE4
z8pku0XAY+NjW(#jo=^#%YMY351?Dr7!dP1dq8k?+eBKHk)Rc>b0VaV%PV!XwOI2Lh
zlL%fYa3h6t?O<(!DKDYP=V!!q)D|59({o%rW5Awv@a_&GoSkQBNm3;#MZDE_?jCi=
zkWQ~`QfN6xKhOg&M^khSZo99Mcq^0p69Xo&?klfhO>bqH>ln6S&umplv89%-c6-e`
z8k=`?jM1pAp+~Jg*f4PLO5*25Z0c%MK;SzGxpqcj$;^PNXm&8=r|m92z#YS{n&xvC
z)$J{B_!CTEHLz|g``K4xlneESl0Y(THuJG?NO1V#lCve+$~+Mm{V@SMBmPPz$nh<L
zY`8vbZFw8%;|3kQJb93z!(||HJx(Sp8acY}3L$3L4@Ql($D8jqx=3bg<Pb5Wb3{HF
zsHEtG^qxyzSZUMd_R(6sGs#EIo2j^;B>MbG91Y|wcD6i8xBw<J8J$+B*F{MZFUZ}8
zIOOWcbbbT4uJEGUAa<<lN97TAPoO>(=0u|NrFoq_QA^5i89v=Gi42}CdOVFv*N0eK
z^7V3S8N-E*yfYffLnQ1nVAX1CpEzQ7zOcK7N82E%7Hz(q(WA`h?z{Uz-oh=Y^GXmO
z9HG0r7PVbMs+&h_nbp?L=x1lFpg~;KkFlGh3cl)G?Tt#|ZTb9_@y>Oz4D!#tX1+M{
zg5n~(p6QJ*>5u`&IfB3g%Aa>)ETDAS-{LCcs|!+43|-b5%}sn^-H(jjYcFQXmD7r?
zK1kcYB-RCIovU3x!d{N*%*Bf%VI95x3_2JDsnZD|eQggCb_ej_F8k>vn^%}hxBXOw
z=vy4TJPJ_73H-=%OvDxX+Qy0Y#qKY_IH#bS-&t}<hp2~uC%jzBP4}wD9e23$JeNni
zX>heQ)Kr(X56@T!i_$)PowGat+0AyoG*kH_JmshU!Jg1-b5FrwZ+O%e^<8?K{D#f{
z*fP9szHW8}UA_5BnLjZ-TDpn3wb`rBPFr=s7xQB$U>1s(<~kZ>W#yVVrjLHg470V2
zGbJdb#B4<&EF-r6vsTl28!{Tyn>2{iclnG8;Pn~8!S=DUgoU-v1Qt1No5_8fWBs?)
z_@07-;!6EP0a@Llqew1FGMJuLO}7CD-w%+oZ-v135|P>J=7l-%D(_Y5r&nH_o?T+J
zCy?xHanuS2m4`aM^ut|dt3UL6$TMKJIxk*I_6^}E?=BUU-RAPVQxoBpt*qd+xqSXl
z6NM;ug)quAuvGph-wUrZ9OAPQ$9_Nmkq5@+mJYwr%8PDr;nFonfstFUtdVS}{+W+_
zBALDGH!K_cq=%2It(dJk^0W+(AlacSZRY;jmMj1D6-zN!n5|)`K0<Eu3wk;5P0wF1
zH;!EzrzUpI$NmB~FW;&GWF^8Dra{!KY0?X&R@>k%Pd!3)=DMb5_*iRe61<_=^|oZ4
zX+?9}C^peR_xYsWthOq&FN-%q50)z6Sya|R`yb50$9Qe72ygLQbcF8=t~Nb6tn-?T
zeP!tKuj6EV@Gr3}f7aQY{~`9AEGY8j@#{h<gDd|l2uW7+H6D&~Sr&mHu-dvIvvoOs
zU@{-e-dx?-^`W*051))90qd$eA4%kUUcCs5>MC1#?0s~Nf2?g)y8w-1Kj8O6G@#xd
zd0_CE-0#&5cP!qJaC=`}FE~a~TTc*lD<4CLF+e^IEF188E5lRH?c8BNM66@WpU1Vu
zBcgY_oI+QyhWQi7>p8=DgZT(&Ubql+E%7i4v&`Y~`~Y8E5SuklVw2B7NM>s!rM24q
zQI2Eh^;QXU%a=Ihd?>sm%7uX?O4856ek#K*Y>8j@1b7a~Icf?J4?yU-JCZ`cmvrMj
zPZCD=&X>Y`Ft-)fL8(3NwXJi)obQ+F7FATUruKmfOC`jhE~%+zyXf2N0?!i@md_f^
zk|B^HWTaZTY{OqCT{74kVXzb8J8|NaWFkR7WySiuEm7iL0X+ys)gk3h@|W|q9N65F
z-pP$M8oV5Pf+rO7h=jCDn=yKBryciy0d$C)HStq6@bn!`z_wer??V(?j%HT`*cr|l
zhe3MzhCqk#e&$8nB-!a`@QK;_kO<W8*UifVwRQt)ka$1hdWkH3Q!OK(bOE_L1Uo!Z
z1m@m}b~59oKiSC%#BJo1+Q@@K)ciErFQ~Cq;wIq*$>>^}5gRWK0f;&4PMV7ci{9tK
z(;nPW?kwj-2u;qCZ@24Xqh5LP9)fIoH>!Q&VKj;qi8`#rs)A>aPNUUuuA94s#tP&y
zVzHKn;Tk4c-ibmf1E4Yn)|k*kGi(x$L}13#X6QU;q^Lv$y$&HnD-?Z%eVnGi^O%k;
zW68k8`#x2QlvACZ=vi1bH$#A5<q}Dj<)DB%k8|a7ao%$;axM|PbyQ?ywL0Q}OFw}6
zK_sVZVP3Z(fYI6<Tfo4~rttQlr-Yt=Uw0>}<B2qc?}NwLrrF2>1$N}>6r!zOSqu(;
zzYtGIH-BlRO~TE}frxei2R=u`JqSHVeVa4BW#+AWU0g`^F+gLedI{%06(lIhd`>x-
zIj=7HdoQZuYO64N!VE3x9cn|5w#xD4)>zfOHqmcdUHV_}6Jf?#wt3hbXSFt*TJPc+
z{%%rpO#Z%&xFL2JF%;W(gxL`{vSMGmrnuBzoG-WTwZ+kigL%2}^W_I3kvp)^<JGX-
z;g%!W8EhpEtT~F=s-`AL&lyE`{9@~GDnH&KP=3RqM`GT35&LkS@j>(}eEvfmygVeT
zp2Y$`lCr|dq5YUEavXXgk)IwZ!-wJ~;oQjlPza^Z``oKoNOb4NSpK~1zT${hTl0Rh
z%hZ5-W^(KPGsgeQ6`4(Siof;9lO1J8=`Vl8ihZuOmiFnYsLDe}?fs{gv#!1Dx&`%?
zr~ct*?2&If5Xx&m?D?WO;*+;55Mpc7NHs%eaLt@^>&Hh<`>(ZpU$XkqH`(OFvydzk
zDK0j@J!3&4ukJqGe01={-3PoF4TB;Cj;#2|^;Nk0256;14G#r<J;;Ol_Xp8z<qQ*A
z8Z`oY4bX~i<j^~$G#PT6%)i7$zDT8IMKX>+<BFupWgXM*LM2Nn41;p=qfc7qARB3t
z4Y=P6hdT~ENneQBngWdJ+LPmX$tK~veZt%)H+URQY>pXmH{9Pb$eDP+a^Lhg@YoYN
z+9X`9@(JJX4Q{6Xtx?In@bEvHt53EH|EBNZk@`jY{Ajk4Tg%@V*6-{Zn}io_qPP6q
zlPoN3w&L=08PB0XXJMkV(0#{j=5^XjoL0O|)~MT4s2J#FP{(stPaT`;tby~xBke}P
zW5z|Z_1@GTWv@jzA!Q2)NN_pnob7pZBq_6F8_^#Qgm^DE(|+w9(eC%l^qSmJ_b?RF
zE6^kh2fz8MVq9h`orRBK_C#yya9~v=o1iPa{dsvWl4+CfW8s5*81E+QCfdEOlhs=O
zwAJn&PBUFu&D{92H;X)9{tbG8je=sB=Libsc#=FZw<9#$XAfuNI!V5cBgCx~T-+qw
z84VrYHMRnsxi$meP|tJvMGG#1r}<o-i>^H`SXHBEt?Mv>!(;E$5ba+Cd5pc#=r*z1
z<{5mthQXvLcHcK!V}KhB-rG&G<zN-=)gfYeO1fIJ;A*jGx}15O)kd&@-EXs#PC)|Y
z9$wzZ>aoW-PsGIT#5;6dmuAa&IYQuFXdWF{tRY0)Dp}u9aLunnDsw_7dbtuD_Ea(<
z)o~T&i>PrtuN~G(vtq)YH$Ead1YE3?+8$?&7SbHwbBbXIhjW5!1fXa2F(70<HU(CV
zd#ZLRKq{uAjvgFR64EE|@e%L!Mrs6?ZhKzOU^jLf3Ll!<Gldv6dZlR&Kx!kCN^TZ|
zKl6p1C}Oz8X5<{l-vbeLbIxmNJUdO{WVc|Rwh=cdD^Z{J*sKcX9wA7>uI1FiFsDS>
z_szaa=RFa7%HDuTDzK#v7nSP<TQ8TmKh!O}4~~IWl<~Rs0E(S~dcNezPfoC6)=`k1
zX@_B5BAACokkj*X{LrKq+jyDcVTr{Nw^MdOq6?SmZWJ6jJV-^-tN@wx@wWFxH1QcM
zMfH9vzz#n_f3sdslOdwdvxP{KG3^>>Gu0F#$xt;cRrV6`kkso?zeXNv26@ZfXno}V
z>toxemYg9=+D{yt8ToSq)y!3nXe<1t)Ebm(mtUAfcwv#w>z06E7Y8jp#9sFe1xh-X
zZt{MM5QyjcYLSqhUk_q{)JEQ78ICt0Gx6T5ie5hHK=Dm8273c9yg}d^q7Ye=!ZvW*
ze0Y$hTwK7x6h&|7JV^6g27_UZ`@DHMB&0GH_>pv3aJdyH3|ebEAJdwW0(+ns30lO$
zMCFM~EiTOW@U$*M92FJRa#U5w?IUqc<Mw?>=ER5zked~C4lYUa@Yn$&`yKE-luHB^
zd()V75j<TK%0qoy^x-&YAM>xk^9;k&a7)AntF*8IR6ODnoXD!>%{MomVK=Al>R$9)
zztGOGX4}(RY3K7qN`u-^+4sll5oMICvVVLLbz%JQ?ZzXlypKUJqqazMI9%LkvU}og
z)~?Z*1d75onGYtHik@{Br+MMokGKceoA4Vg4njP;U=!iMig@`kH#YE&Q>PUkx6iCU
zVo&DI&RlGn`#EMrj;n-cDn_8H6J?X3@@jAOuX>O}peejD`*z-wc_{POaGV2CP&rqX
zk?z!_)ZNRyCpbctF%7PB7-biHG4(^o4(R~47{C!X|HM$`BacJ_CMNQ>|2!=%8|!E<
zXp((8bK%PGbTN|T*b|(yvG~PBlC@loFOg>}Y~CFEMrs5t?c|J!5E!Rj+}E=re3&!T
zZu?=nx{vXS+v&@^NS0P>4)fnL$rRXvkoPX&=guCs?ARf%On>^TnLh)E?z{hM-oCz@
zu{Hl0>u%KN+vCd0<6pXROQrs=zpJnhu@d*$PoMTrg^Olv?bqh5bJK-+xl$I(JcV5C
zTXBe0wBN%aug7{7e{b=Y1L42<@b3iM#B6oHPTqTEsEqaW5LnyoDriq|l#Glqoy4k_
zOk=4KqdxZY&SEXWo{eVqWp@~7%91}e2~XVkY@Ykee)#6#q4hoW*MI(tbU&{em|G)s
zM{rc>QK#+>XdTbuP!gvMUoA>^+)XK2_7;%<zgTF>TYYlW%Bzofd&yhKE>v$8$<k)a
zd+vL~__4#<vzs;hoWlx+rZPG8`3dXXJ83^kPUimVw2NxE-xE@fE?afuSDXbr_Jw~&
z;r|D5NY={R7h?8fYq;~jAXyllRqdN{=U?R|Sw8U-En9?CyC(MrvZ9t%KKSp7xiiPY
za`^CtpmqSKIkvEK*cSODa@IWRW5-w1bb4@Cua41G#@)m9E2)SdWq);N6wH70V1GOj
zZ*{~Kn*o&UY6{r>szL2ZU$!HKPwl-U&!!Xx2h7-zBaaI5Ik5P%8?EXZTVA~(&F99%
z^0TaUKZo!fuWvD8f11e~vfxRG@w7hTNKW3%<qv~r;WU)t?pTG)r}(d7=>0%)+S!B4
zW<O-_ir(<o37c~(!q>gezII--5Id3y$@g1csVYZahk>MFPN18;<JEzabrIkW9<w`x
zvMKVtU`rKR&L{#!*UL|gI%hU7CSf|+Q}ff}Mm^B^qruAqxOn9f2Q)Am3PtJQ5tAUn
z+*<-nKqS(M4wnBBeMk?VLT9-VCq<*@P7pOWJg1R3@8*^trY<KS{YKW}b@Wza7xGXf
z{p=1;c;u^KM~z`kHi9G9acu#gNAM=^lVDG&M<G1^YVLub=a(*W>;<Gd7BZ58r()=~
z19-9bI|OV)Ib-NXgB7w(jEuYTGiALIFQMN?qY26{#pwvt_Y|EEncRSjS2V;HUtcp7
zw~x-BxmMyeqW8a%>Mliq&-TP_!&hqU!y>K><IrlMMs)!sGMhb-dKXPZs(3l<baNf$
zRnYA3BWhVPBk4Rz(_{JANr*2F@5ya~N!EcG2rtREQE{55Tuwe9Fhm&5C2y_Cbg30H
zKFYr>6QbP-98!?-gjZmWL@|ANz6I#%Mp38isQ5*o0R2qk)-8O3%j9TCxd<6*kr;h}
z10Hyd&vkeSFjV;Vgd^q&kAg@0zE0GmBpYEKO=_hz)OdSZO+lQZ<~n42q2<yuMsoDa
zIMM8K?Pji0hDmpo<`+ap<LEF#Tdziau$O{R$_nU#-`ZZAP(kyaW1nDPu%;8;a<E;6
zNcO<bEwwr^XG`$$r@;&d7t?iUmz`=2xsObS$K8oyTLFZq>>gR@mst;k{LUp$%|e!S
zwkv>4qzQ)96t-fW>&mxM%CXk?xxq|0iM1lkAhux>GRXNfky?X5g&<b|Jp^2_oG9{G
ze_{l3sU>p2DK)wromJU@j|~S;ufCyntHzl5hJ^Vl^C8meiJ*sJR2dG5?Y7w9+YbbY
z#No#EU9%#_!y)8;i>Utbtw^;x18lJ^IGfwtXD+ul2{SR-I^4-WI#Dowin{d~-$b-e
zzJAGCPaWCfvK4!~E0#c(-<s4nnU+o?$!(k(eJ{_ynmQXU35+8gjssg7Dll7%@G>3>
zOM`ibB<gZ|I?wSf!3IKSS2Kh_;LQF*q{zE`lj96enQ&D8gYl*0AX47YLkF89L3k9R
zqI-znG6Rk;s32cfnftk-ILO}MtZsRNV)bH}^@|qpYzQ+PqzLytRk3o^X5(sWJH}2C
zRSHhdjGrh6GcNo&P|;tCP*W^+%bP>f0OEHSrkX94(FC&#p7B=uUvxo<-2ZnBFs}ay
zS?Dj{oh8jrV2t1O|BBTRs64CgJ~i1<3YAlNG*&}!-qdBeZ^3Wg5-llKe;Gy8=V$RD
z<)GM*+4?jO*v>2|Duc15)-O)8c=&gRtmwciw?|*;?W(hxi-sHI?O(~mCnqkj?h_R2
zk9~RGiD$*u*44+Key3&ASh!N@vJ_I+ydm>A%S}ffAMxRC#9aF|c9h>Vk{|iIu`Eun
zEtIddH@y3K^HH)ByNfdrLXZB~OAgqy1aO$G<@1iGP|vNONui|vq2Q<#+bhG{W1P?a
z?G<h-Kug<XDaf*lM(T~94tyo--ri~}QP6|e7T@uAeY^R6Bx^-)>GCz~n+)H6dyEtO
z$VxhriCPkF9*@Z;e!aY5wq|xOhSZI}T*NVPP_^`Q%$=dh7GZ@f`2O<n2~|q7@V(46
zb?$}F>dS3n`716=z4c#*lq_azj@jA?B7Ev)ai|;Y6R*#U@{R@Xg_UGyKA)R*c_*Do
z_z%B2en;(8BoWy#@Z=)CIDG1ucPo!X$tdk%(RL1x{Y^h8<V?nO;h!zFVzpR~L2W(7
zsi0bIjYewtdoUZ{H?2^oi=f2l^m)xwC`*XluRbtu#}2?4Ev#dxeW03`r&|#De169%
zrD}9T2QBwuF1i-aTh8u(Z8jcm;H?!ffghhGeyvJ(2+-(8$iiG;{xHgTB7UrM!v1{C
zM*r{)_1tH!BExKA%j{#lOpGjE+c#V5w$n4#*-Y-u{>m2d_?T|E9{LkmQ0?SBT&^K^
z%AVu5ZwNN~uNJ@eu|qavpX8Yqv$jKI4YG$pRP8pRd3>0#QQVF~w5H1=q&FsEy_pV4
z0WJ``k}F;^JECkncjTz>b6}%DBMo-0x)YatJXE;`u@i4-5JgiuUakgWD+sbZKiNZZ
z*QwdVAS;6utts1+4Xxu&-imH&bybcdNH*^Y(XS7#$)?6iA!zt3VIv&0dd(|+DXoHm
z;~wOZ@cRZg78mwp{E^14G5t`6RoNHKR0%?o%$f;w`J;`OcQc$5A;+9`Y^f9)W$3!8
zOCO|Z-}mk2s9fT#@OC6R6)Of?ajnLW#laV&I0-1oS_b0P;c(C6Qu8ZhsSHAVtPLX0
zb?f!0?GWU3`o~t0dlvCaYo}+qtRHWkR$Zkhf71`aBwvNLTvQA}hhN3JUT=_`EhK~F
z$Z9N?9Lzo-O6K7izlO{MIm=`8=SEdk*$>oxqA6>-CNS!2wn0trD+xRNx^ot`NaMiX
zgYHM-kvJSWsd<R73jCT(v~X`#H9QTVrwDQ0p+hk*v|ObHx(M{DQI(B%*IP^^HlTOm
zteAli=o1g~2mDOhPLEtYwhAQSE&Y}ivk|2iUR7a|_hz1ui$`wFM3XWi=w$O;y`1V)
z_6rV{>gt?7NBw;k`>Z8>`XP=Y^(j57sibBn|6od<4uq;U96HP(G({D3zFlgR<{i~B
zPSqq9eT_B_s#YN5Kwn>~L{6AKtvowIk)9omz+n+0&yT$!6t$0TylsBe@OY){?`|AC
zVIa@BU?n~1S=H+W=w4=Bu8!ah2C|vTrO6Vm{ecU&n(4HOvK;HJww@dFI3Fb~&PDHm
zX+|eeJ(_KAATr56#}l^0+KG@OU&B;j=auqEb-u~zj&5JfM%sUqjfLpl`?8#WEfR#&
zY*E6MM_ym*nEAK6JFLDLTpFZ>l!==fEn&7AW-DtpdiGvUw6n;h=DJPI5S$CN?{FY2
zDuelntnE!l1ha^KGM{Om$!y+kD($?f*(6I2Pv4#6(X=^2N`k+{W^wCFtNwOBWnK2q
zR6i8)R!&YX-BMq7M13`Hb5zB}`XVN>Ii<CG+e@+2^_~NVefX)46+e?X-Wg2U^~6`&
zPBh{r8!HJT%pM?Zcz$eU#A3i91#>8HRFeYY^w`V4bY+f_n$91&XZ=EYoG-G88ih`1
z0nkBrrPlSP?jCc^t}jr#Lnx2ssqKv4k9`ovW3tobf|cyB#tdOD=?X?_&m7(e;!^x{
z%3HXdp7ZIe=;&stXDuzrK7$ZgqqP&=-rxhL5+^-9O%K81u2l6Kf3e`}i3^IHoVd<i
z6e2_BAkr}V3d`Kt70aNjme_21`Z87{9-qv7`{YQyvCg5+Qu0iJFmHKrqqF?A(dPCj
z)33m3czuJ#dix?<zliM$PuyU^uKEE`2-hnQ-Gfj{ZB3400AYNngb%%#_MfO_f%cDN
z3V-ke;jNdw17)+}HGLBD8AipbH}jB>sv5*(vD>Qm{XQ&&83x5Q7MzH(^H7PG3&B|n
zKlE>db<UE0+DnaUHW{J8vaHs!d9AkEYpMS){pE=ul46dyl8oC>n2EetZOz!$8}z~|
zf`?1)v&Y|h?^LlwK>N-!j;{c|(+X8B`_MarRbOKzTCDFNq!Zq2BUgP_J~#CalFc4W
z*}w7Evtyc>sUAJ*tIcOG4mN#hl~3JA4P2jDP~4&5p~zl4nQ<f&BEbt#8SVg7x^DtD
zQp1nqg-s5ft$Urv1|{cT!HNPKUek=)O=5ewx$WFpyv+Tjnct4x(dR8(KGulGiJvy9
z2N&7Ng84V2>g6Sii@cc8(OOoR%C@k@*KHiE-pjFeH&6#_>RJ4h_|w!ZRjoZ?!51TE
zd3JV2sqkbWBbUp>sQ<<n_J?pF!0Z9WKh<4_D~$ADcbuO&_eAiKFY|*;u%Ydc2e<rJ
zt~K)IQ7SROTjaIYZr>38+bnzV-&W;Rr{$;zl*?Bo`2N6IxIUli9&)*O?E!lRo)hn~
zkT*C^LI`qtevaWu5F>Js2ks(DjOFtD`k?Ww@B4;1E=vSXO{RfjLym&d#eq`HdoI1|
zS?j6S8#9B)gTY0aFhA4@x($aYIa%={ozaEVbL#9W$SNMVJJra;R;if%ur4ydF?kbL
zq~-DUaX!&IuT-5`Sfxr3uWfS*BbC*d61?N4B#^@a2|AH#q^IGX;<)`~w29iL+e2%D
zK#OHJXH^C~1p)b5)}BYq5FD80mLq$#%0*C!(o9ZF8MA5z!J1G*K!n6@#+}&)y}MQh
zH>mZ?Zkpstm99Y)y-s6Us#IT63yT)fArHE=_gbjoFr{VLj_6uM?L)iP>yXZa09$dZ
zCUt>ymOJ~dxB{L(bB~PLMNi>FAt4e=mU3#!Rux)6R<NPX8{;~-?GuzJGeEZuA$LQ<
zw+BnXQ)JaQ=!qaLYe78aGHOywl}^|QHCN{LQk(jaP|S;D9r8)Wh5!_u9*OcpQAV$(
z1UlN@DHX?uL653`r;PIsKHu^Znb8)%i}>v$SxK8<BPhoLaD`DMqroO$f|s=O^|3}C
z>efsgFuF(!rJ_-hJ>zCuz`k|?gi{{)`DyMxYsE>8>=Td_Oqz&de-PTJLMgaC>F4$i
zCN3v^_c**3dAIUyWtWa1nrf0cf<m2KWIZ*~=#w16kfV500~!KO;iF0b2(i5<x7V%e
zl1~02IeXBX<iQ_YS2c)FR-{1EbkQX_hQTrff2@2^A=niP5Iv>e)x>3MP29BnU1$N4
zz&s$3nyw(0pV3GuIn#K*oATPrFgBNt|4%GApK6kHoWuW3K+gACNOw0l?kv7PvRn8z
ze2tv`ZSxG=VyEs->OI%vaA%V+#-V1&^Qz6)V>p4x)oC9Y8)>y$t;E>l&3y(Rn;PqU
z8s#W+L*UKX*U(=CZ4xfmNYB_#5*WLLkZS{{eLuLft4VS7gYlV#X2&zvGh2I>EfFz2
z25Lv-yW@r3#Ad%oX=zMSPdE|fkIz`ip)Z9!;C*)Ld`7!pem6YXU>JTfyEnV1sekrH
zQ3IH*Cs&_k$)JWT!g2GRjRl`F-fk^gxNN?%Yetuf`f3|(i1xgtlDw&CPy9?4mg|Ae
zSRqbvr6QRh`%rJv24nfme(m|u7FF-t&8~3GdyiMzdj9GR<IovaPc9>sgL7#;(Ohg_
zT$T~@^hnNuN*M<{9X2l+hQZh|M%N;Wn}k;r`8?a?KllJ^^MA{lX56Lvj4f{{><iOb
z%-g9CkC$aMTTd(QtLYk^nXcBbRQ6S@(Qqp`tc90xi&E>2K>Lp^KQqDiihkjDGW)IW
zN^Tpc?elyqXJzvBKb%{)Go3o$^&g=`6#=u=rcOS@Lgj_!q_p0->AY3@!9&SDy!FIE
zBzvQ+{n(dX{ir*X#`uc22ZTon^ipL<X6vy-u1}ofQg^T>3>3}D8S?D`y~+??_;33M
zgRIMJ>aB;aeCk!amhcW+?b(m^@n=bjdgJFeTRv7EB^&sCl4LnvV~^yTpbOX9R1bMF
z4n(=}SVV`#k;8Gdb?z)IqS;F2^mp8XmCUegg9ZBfBt?PQn!WTbIZcabV{hk#s(qTR
z`4WWjVR^wbj0}`ZSWMkL;eYsEp0L_IeB&9Gj_xB_HXifPzQF9xuTZ0vy@?x9`k}E9
zvgcQE|9K=qvdQXQ+2Qcv18f>`<8Je-bZU}}?Eq_jIUY+Hv$y9(${oqCsQkt;=fjZ;
z6R|rd&iU5eS3MzOiaa-(_xrKbMJ1lu(buBW|Ctx*&-N0z+aWexb2ROG$aL3Q>2P3H
z_4_+6(N)u>y+2tkD--lsOjX4N%UTaGCGupVv-<Y~J67Mz(D!u|`VDvhk7b+d*`b;>
z6nM9_A-svNU!KUkgsuOW*7b*znd_*##B61Y$B}NP-1;Af?E^S~={O`Wu(rPR-NBYG
zbdTkYLS{owsfWYUuItT(qr?#)S!E|ylV|AlEX4Jjn65m8&Gy&SZ`GxS(?Dd9e!#nz
zvnkCY(xj_7c^da+al0Pb^+Nj71Q60S9*Wz+m5}reyX|2+`>+?C-wK+|+R2l1D`G%M
z2wm%(I#W%{xh-Yn-_Nl}C`#&YAZA+0kfSv&K`Jaa@R2u%8vqqR^lE$C7}v^Eap1eN
zGkIh92*s$%%_#ex?Q2oG#G75ogboFl9wKw@VUea8NiXMi@OUNPzCanm23%DCu8~PV
zP4gam5MwSHmfdwGor(!OQP!3ZWk7Taw~<|RfUk9Rx(tCDD)A#(C6`uPRa$kE1_6$M
zWsQ0xcoK|OPfR2qO<3loT)AC{CSa%A7GcY2G@LI%r9$~7En3f$z%<DV@%}<<%Z0h}
zFiUYDA`ps4f?UZwf8>V8oY44E_VE~lEJx(Z#ARPVF59=k#z8#})7$&8f?NeZ$4~5r
za`fYg(DdLBiqH)Dyf>Y(U1=^q1<Xp%MNnmwCc3;5PVk&FVd7kmd1Yrop9dcTO4hF9
z$Iv5-YHEtkDIyyj(FQ3ckAu7AK^`&oa?r$u&Ag*#jhCJyBqY`lP-kAv#QeaE!gD^d
z#8{;cD{_`Iq>!U<kSd*wLRK;3H@gO$Jn_qkIpJNpkD!p4<;Vh$gT{LtZ{W8tcp~wK
zmTZWZ+lnTxLEeO4Xc7}<HwcAu=3z$MIU7M18ThG3iLEJf1ccK2jFBmY!MrQ|5N9bD
z5t9>K*)+*kj&3M-U4t2-?G2&uT@{}Q**_`?;xM2<fG!HpM%vVv5EP&q!_!pB+B!|w
zSLAtBvqYIK1@tG8RZWJ&5@~kC@gQZfjC$%^k$i^2t|u3uVru}yPTAaPQlbzh&9HPu
zJVLUc3`81TBa%~?A|cs5-ZIxJ#!w?e$6&cv_V#7%*?&V8g1V+$^_S$l*e1B2ThK6r
z@tkd<UT#Bxq1~nkwGCH)HCxOSg?tj=6o5^M>hy<*n&{p@zYu`QO$I_rHsa`ZKnw?s
zC}{|AAG15@Wa}pL*OG)&vSXnlpiqFdj)Y7rvLR53in%b;_E{CAhT=}fF+T6a!=tzK
zuv_}*CZqPiYbpeCSj<|K*Js3-BtxgDHvzr+8lEjk%Tt_68d#?rl}fuj6|w_hZ!}K8
z<NJX5A!b;6S}$(o>0D=%D;n}KX3jmz<O`N|m})l+D7DMsb=Is7Ei%RmlN%OikMQL^
z!v22@TBfRygWXf0G*z?OkwPWlR02}}IS?pt5sQ8ZB&t3yI-n>=AevZ<Lq{%BPhLs6
z1zt{tRr~_Ktu)V(tWP4c;V>w?cx_L3Fus=}hJhXx5H{e_JxY#TejD>`sYObf3@{2I
z>dymDSf?1?os&t?4T3TqVbxkmO7fMI3A*wruz!u27IL2734U@9fMRZwbs%gfrx!Bj
zve8k%@A-B4ZNWJ#gTe}Or+fwlZyT&FD_9_TtDX`DODu-&b`fFhdvjb(+L5IKoMMUP
zWTEAaAy5<kD2<}4fvq;@%#|HQ2^s`WDj;7O<84j?g4aVR=S_tvo&iD6V#LrGLl3rP
zA0x5CNXSsAq2N8`tSicb5q8HqQC8M#Nfy40$0%_PR^h8!5PN;@7TXvZjI~FRT*SsE
zB-b9GaT%vCS?QDlJQ_P4uQHU%!w1spDm3Grud<-9`N^;GLjob9JK&Hf))GCU=cdIf
zp}=N&@CqFU?3j+#q)!*fkMHsBW1}PNqf;M@;rbrzv$25BlNtS@isMP4a;t$>g_PdZ
zsfdi1khN_;+pyWN2|c-YzKQJOT^(c`i^fFl>WJi0M@QfUE3_6Ue9Vuk?nEq?m{Aq}
z5coZX*ZiX3@X`vDm;R<0G5ryE9<kFEmDgqPq&r&9ktC?5QCbP8R}Sj<o}#lPs8^ut
zioh{OapY}Loc9kThdL4jYKhuP;@u$oH$uND7#(D@v@L4e+}uhp*b$T;-4?#(ahWN6
zzkq&Iaikiu61Q@$Gy~%uIRy=6!nyqYxv1SSlxBp$mEEMp2o;x7o?wrzx14hyqK=*V
ztd6YD2FRQ*(DrK`&wam!;(tUT6oGq~)t@N5N>hFFI$hXWQ1JdBc<3fnfr7?op{H%!
z-x~Oe!CUbE1~D55KWbUAiFP9#=lb!Brdd(ReME$dsaW;F04DmIi`v4ZrsxNeySYz{
z6<VeUxo`DqY1VzP$;-(fpr60DVHCH$Jk3hoXa6TFf{fz7K#f=*dB!5uSo;FBez_hY
zLm||fi|oz#u@;qL9A%=#zlXZ=*^D)r7tGAq=MON})&}^m-aMVJ&CaHBeNyC$<~R>#
zOb67C`G4mrck9}<qjtFFY+Moe?)ebCm0ABMTWYqpD(nylw((okg@>pprzVTV>{YHG
zL1_p1Na=`^V?VQ25C*sMKTv5upUvK;SiqrwpT{FYsF(!2v*IL>7W&X<20+AB5Wo2#
zPmX4*VgPF+EC}5HcYNrU^oKzikH<WAh>E@3Eabp{&6SxWYWM`__LQ9S>GAM+ilEa%
z7s6j3Shin1>a6{vki4JywelOZ2<Glt$PwXCn9Q^mb>tb|<PvT1)3La2``E#GyI~^C
zUGl~8Tf-xVY_xNVhwkaSe0k#;3=WE^P?q>4q}dB^Ez9+vWW@aCgRR#1jp_aD@HD{>
ze|%}xaj*XD{CuMP)DlMZ%}7T7j(|fU`-3YypXMm?m0!&)n|#3cW2hU8KD8DEW>0fJ
zY*z;@m0f!ZX6Yq3-T7%HLv<qXiz_PkpBb_4r(PwdW_Lf<;@zevc=e}s9_8}RUb0sZ
z>6vDhMiKV_7gzN}P`H8z?1dU1m7hkK7?4erL2Fbx05*L0D+x-8FhaYO7nqjlD?T_D
zC1aP~N?hxSCA3G13R<0ui$b{4S`-4~?0kWJ#~*;pi{2h)>(8?K(*B#nxxS3~(f5Ac
zuHXFK2P>0GA9>u_#>xxwvUo{uS1*rcSFK!9O-dn4@1ej?KR;?ctnx*iPu})&>vU_d
zN^oBQ?da6qX18u$%JA`d8@onw6T1d&1xTv(<UL<?A(o`RS2O^U>_5#~d6Y3lgwJuX
zQT~_odLKVXC7@r65cE3mO*qAK2n2mRF~O~&sTP(ko?<}G$_kSVusYu+;zG`SE8VTv
z<^l@#>J<N!XprQAi5cxboK4*Jyv~a7R3te|*NMOYQ<XD%cq}g1*DV`40V97V5An6>
z>QRq+Qupq|pN-T!SbfXC-kH6%)hRb;jMBhbc=_b%R_84NWdI!Gnz=t^38RCD1iuNm
zz3kdE@O&ytwsXYL-5I|l7TT(CDadnkja!&X;!b;dJ!L|$AWV*OOAYGLLBy&!J<jBd
zs9i1r!d_6&K@7)|kB{D_09hUo#h)=BmmEBBiFgs0uIe4dFV(e3a52o{83Nu|-tHx=
zR{$f>>FCcEZs)-{MTZj>NUexXPm@p2ff;Ji{T_j!u!l)H0o!DzoCFfojHJ1Rvcq6X
z{o($A8sMN@;MbS#+?e}fr=o~(nyVz$trKs}rPh7a`|#3Uu}%bNM%gG!K(V1<K}RyF
zZtf>t>^Ufbz|S@5s^4G~Dv?-u<O=BcOa(Vgx7o8bBhEFkfFL*}Jp`PH#ePnNX*yR@
zuedh;khwTBorfYUlB||J9D`HKGE0zo?jgAeLZ-(^I>CJ)R3I5s<bnGP>9|D^U6}}m
zUY)84l6h`^R-T<93cqtu!fp%%cC3gwcHq9vULQlG%WyXV$I#i>6l2AdK|jMMP(?^^
zFUw4RICN3vUg*7nT^qe<_rXG{!D<n#1@@_;$p%ElX#!i&CdV<!iO}o|RTyndy~Z$z
zdJ|DFHFkIjI@HZDWfv^gJS6e2$KmT5JejCjUVya3sfty_gSj%c#6*PfG1ZWYqEJRc
zn6QdLF+)M?I?3-7@jk9+Aod6cRJqqJr7YJs1HA+36lcWJ@?pcNBb<bGX4iT$PmzY{
z7<dno(k=R&&@EV}NiQRh)84(kL7Rbl0FzZ^-tlYMgO0itaBe}^az@t-Lh;-h1eJ4p
z9~y8`GF1K?&_+i(V5(E~Bjha>Yn5oEfi#Uqp$05fUntvM7C4I6WVSM=;G@*4klTe#
zuId0z5gotan+l722zc6#D%RoO)N?IU^pyPecu|1usB?Tlm{C3lVg9L^7%Gj0yLIhx
z{q!nhqtU~*{E8;8Ou$u>?sA)rME%Quq^$pU4o^|Ohd{8+>4u~lUu#?=MndD&gIE*i
z=gW+iTpDl;d?wAp+@jAgTaRM4rkyd|yxr<-AE{CrmuEhv)*0o!iyNZT!oh45vo#yV
zY;E0fTSR(oSh4J@Xu3{47pl&gR9v#$FJ@(Vk`vzT(bZVN+H<49!V6ouWGFYUpws@b
z_muXl?XboW-$#b~xGcv{dDJg}^xIWQleTpY{7gmc<k&|}W6jhk`~yGxPa$~40$%@$
zJagQyQR!ax(|I&o%hoGhOe*~D6}jL1T5BZM8@6!8WGCMDD#ynW*n-n5d;)fbt#9v9
zJ?9&;k3F_-_dm-ZP=}O`zq53H^JWJ7uTD7(qI&Jictl{fb}?K1*gH$R6{J7-#=;&^
z@ZNx(0%M7{-o}hs`yF-0W&Qcqa&ZIw{+(YuZJ(XIsGRgr96WtjWiLN7zVi8F2g*2R
zygz%Fx7KZ?D<3FlI=?l3bM_&)sV#;-<?`sX#d;pT&TD>C516YrTlrPLaLInO0Sn5i
zz&OuCJu+&K{#TRcBdCDATu|&wwW1Ya735%>;Ui8C`1d%h*63KZWCr_D--+ldkuP=g
z67{q6^5>Y)G1*OOHMVXgqw^uL7y=)JFeO{e$(o7aZ+&ACe)F$6Fh$9ZcD+8XX{QdO
z@tDY0uQdDa3lC$qGN5`Z`i%8gl2I+$sXPQ+<&_0KLTax6<{zwod^0P<2d2vn0+#%#
z2Wb;$Gd}`p@xiZOXtybED5Q+9eNNBvRrZ&%N9R|v+TMFvT440=d7arGZLnYOcaf#K
z%lyOFS?202*dLr1hKSV!XFQcZ@Hy;&Cl4MO(X_!%5F%39-Um2nTvqd_e-5!vyS%~X
z$N9c9r@cgu*;n5M>ZwI5T%P>_&aTdX(ME86T*3$3!@yykx<s@Tdc;*&#`)xeDcSKU
z%pT?sX}0XXjqvrNHa?a(>Syu(X;0eYc<PqTJy-Y?XW+Vyn=CwmU8#+VzA;-d$-T^0
zCxdf&bx{_Lc(z-?#iR1bo3fq7&HB=J_rII=_Qts|zMh8jU3+<1&)q-5!}q%EFpo3u
z1D2HUAmV0!Y)HgCAZC#s`?2it+)0(Yf{&!T2B(029d`p0+Pyd(?Pf-~0#`%2rMl9B
zMzj4k;v&)hF2T)Bpj8`*<XyKF>&~JJUlc2`G_uCFptF@$1<~p(Bt(!G2#t8bW)fo0
zD_=ZG4Ucj)R%l9^ljf*mxwU^#Nn^o&N(h|*Qh20nvvDm5(<F8^Z{@UE83_8mhepc@
z)^kbA5tiso?Aizx#%9WM?cPNH+-re`X&I_|@8!3p=xu}@e8Yz>%LB2WB1UT)4?Gf4
zKU3|wUJe1xIxk0&-N?4Cck0qnZnVE>C{*M?6-E%^b@1Z!w92f;?h#v3+p4-*2LzUF
z{DMW)*n(6b6LUtidqRkz`6?3L*CS+RV-@?~W0I?us#r(#z%AM@0kfWkQe*xUQ*jCl
zo|~g#wlzJTEeZ=b_0qa?eClE4fL2R7T;TdmfD<kGE>r`Pc`e5`1-(*@>KlmJMsGcD
z-AS%&mED))uaO5eYg?JJqBCn6Xxp`Q$Q+}^VF2&3US=^W`s)!Siy7Q}^Q|K;i7Ln$
zA%|o-2pdnCZLqreR7(ah&vl0UiB+juFvD*WUO^u7i<qsGRHOtfu)$vqk*uhUOBEBY
zis+%j>Ew^4C<ovx2e*@2e<~+}HnBz7y*;m~y^(6K3(0i?#Yhk4h^;QkHBD--Xgh`}
zcY^@WU4h;ygibFwDp8j{rWbM!q8G4rM?3s)2Wbm%RFoK|C)|z@Q?6?BDOB;){st}Z
z9pm+p?0oj}Ec0{xm_b3AL0kA$!#amms(S#56^M9>0uCz+_yob5Js4g8TdWPRZu;sK
z>c&2SH|3}W9Z^p&svZeQ>RSZPqQja#p7|6%aB#~YGsX}3mvYv!zE<gw0dMiOxw^%a
z%l8kY7#_g$v4eKc0B(2Z3Hmlc;NjL!jM@L}E-fDL$wCcV^7^1vA+4T8>dbEPCbM-e
znyo~aT3z_SKC&N*>8^c$Q+)zMZH7Q`3&NLHt;B4#@VN_Xo$Y*8LEd-+B>0$S&2l3!
zXLoQ9=M}+zj6FbKZuz`Aysi+Z)z-%Y>rK2h*j~n;%Hr|7oUGqyF}CRTf;_77tJ%EO
z7f)Dta*I|12YFG6SnmT!5kfwX%o0uc&b;tVoVX+=w?rzxQQ6aa1?iS6IPCh1wy4+U
zZeC!u)o)vEJ@k{s%Kc{!_E!TMUOU{B?9-U+;yzU$rlLp)1g8M+zmpad<@rYLSv})B
zu8pY~pvXtBD_#2+nTo}1js2Ski)rPD*J`DJ*&4?aC+b@`;rVxBr21rDb#9pO%Ts5A
zZM^Q{>0)W~N>`k|E3Pev)0nMErCM!$+p8-ZyPJn*_qu$1;Z<>%>9yMW?$M9UcwWLo
z`0?DUOZm=E-eT3la_n6s<nBPTN3z1-`IQ46v(>WOUbN7sR(vmC&QE#R8fgf-19ZXl
zDnm<e$IXCHrMUZ5AqK4C?q2l5A})K%=8Kx-EwPYwpCyyg3WUb<i<bV&PtMA@H+0EG
zwdR{4Xqz%_=<~}gkMjH@pYe=u>z&Q4$eLuAq4M8-A+IVenatL>BRiL68?rstJNmNl
zLCI8K-VUElI$FwDT}Jy^Ox6!f&%`C&rGWOF;*hr>mEIajnbg~OlJ&n?%2;M=`^}7|
z&_JqM?><~i{?X-0nX<VZN~~t;tfubn0~j4e!V^Ea>X$b0o&Jp5HQN54Heyj>w)SCh
za8uLfvrK`|Bg*EBke@XQX7O-7*)wD#ntm;WpGqV{uGLYEKNBnlX)-}m5wmwNEQ<0R
zCn0N+6-iYwX7jTg)vb9Qpp2I7MN_*ziW6BPwMlx{I4KzIYy=kgr);U3)CW8+x8Gb1
zld4$MZt@nQi`)vba1=Rz{`|7j{VqC~H%@N!i!8i+)Z9H6XYT@YPqvxx`9dePuo!#T
zC91%4xL*DYwdI~9**TFSRbN}@1n-D&j?tJTQGF-^&ITL@!iFlK!}T7@EAO|G!0a@R
z<%IU!LbZ@Q!>;|p?7AN5RAUBqnejq3&SoVIwGB@KQuWDf?d8oAkRP-~(GCMO>U1_<
zP;@Qq1~CtIwI&br1{{z$&&k<<@|s|Zb6w<`c8V#WX+`<YP$G_Qr5W(y2sC!aA~5DR
z42neHC75<*^$wcZ9?wN@5^#ISHs6-Ku`fws^tdc$Y^{dXDYqIiHZT!8nY!56)<imn
zY%Lec(4*V!u4G#cRXsq|VG~;8mD$R))~JtuDJM$dIyhvuR=vf#Fd8)Gw9*l>H{5Jp
z6=BGnhcLYyf+!@J!2uhYU8)3Bt6T(yy5QK$*3rSGO{_xFV7~U%5sNi2jP?W=U(p^}
zlH)-}$I59pu@P!F$f#n`qzuxbcbPeUJ3s*E{SE=oMfGEMtcX^fglO9%A#m5uXWzl0
zeh||xPb_0s2}bagE<9@#sSKgdPMAGFgwdKhX67_^B;ae4$uSXZ#3kp}uK8Ms>-nkk
z!#I?83+gTBZmz@14o_u%O2;+jf=07~&%7*thRjl~W#tH6;iuJB5au@Ik>-KYle{^)
zC5NgOBZ|851V4voY4p7QG>~6Y=#nn`gr&%1Z{o0bFrj2qVn<-LHQ?_doRG>%Xl&U~
zV7A6CXBlkFE_J_*!v-%pI88Ujf_E=aG8~vwb9H@n;n@PZFL~zpMg4At*lLVTaN&Dc
zRkMwrXV<&8_M%Ee;P`od37nLW%G`M2Yf!a?b*#f9uMf3d2oq9kOIu@6OagVk)x$+>
zt9Rhj!($)~VRi$r_(7lcDBZZ#Re*3g634toSGp9NSvItq1PUXOv;L8NI-5-%un!zF
zIN*ITjPK=MvlFG}ZTtLbqcCr=t}sPB0g%wFb2W0wY~38OdmZ<^ASm!mtC75FZOJ~<
zs69OG$Kz}}i7@|ODnbJ<8S&Zi#b&j&!5s-72$~?+8`z-g?fVPUfG@#Kv0WD7XmOE$
z5B=ZM#bi<ctEQyl-sG=l`N-O@HRPKYvYt1-sPOe{<AN&lSG1+FP|c0nYv#wXIp6WK
z!F9C`EBMuRyt#PY>q7o~bq5XO&_b~4Wue)=OhRNz$$^Q_J#F#zjlB<Q513JvS~-7>
zMO6(U5*&IbW1+Jv=A-@icFPwxUx3+qsn>2@(<WgKdA!-~`!aj3m8`zLXBT~=%JhZB
zeSup;Iu&BMnD>)in{(zAJ(@J{beJJGleNLs)^~rqvo@0!T5Y{g8N8JY$K9{FBJKsg
zD!o=)k38eUFF{yy;AzgcvNkPuj@8y>zH%SJ``>Mu7n{?UInD;*8CsoJRjPS$f%p@Q
zD<}o$*DtbzEk3?X_T7d?<qv;*`DnMD<(B=d8ZG=;ZB@Cb<cEUKFJ*OLEkC?^$1MdL
zc$J$}n|1YyFBGepp*N}!Zdd4)llB64<Bn|PRPKAVgf<BV<4`u=oD$hwdR|_T$*N4V
z7%ABl>6sL9*W`Ku)oH&J@U(7oW8O8`)v2ny@$7uQLA{YYM-&iV@<JbT=tcD>lioJ|
zJox&aBk_IkzGMpA8>;e8lG%#FyhzDqo7>|jT3T)8opUPlSNwz4A#XuutN*}HSe`6g
z=-Ow3g`22jkKQz9?(Q+$_|*CHn8Fm`yO|f)*}0dT^mhmUeEY=OZx@H%7ub0^f8Hqw
zhJsoaV!hp)|4hptgO{r84nU0_3J4P78sa8}#*W+A->Oms)Y=0V9Zg4E;|bYEwM>IW
zc{ufvu`+d2B$5?_J%MC%d$wn&yI6r@1fF4ecp$UX|4Sahy`$;Qb;A}hSvx;JQZR>E
zx`;=zXpQ!Xc5`eHfWTdD6~B#MF7pQ#s$#MQj`;-ptn{hfHkhqu|0l1&pXDCmB-cl?
zeAzU@xP1mqL}SN_)tBd|sVXbB^7~nB*0C%cw9oiE<`<f`0AuvsFWCE|Qf0Uc3+(YS
zr!!E2><Bb6wX?l|n$`>kka3_qil+Vd<IX8`ptyVt;ku?mRE0G>5%!g=)Y|mHjMshi
z^)CSyc^GW<apE?HtHbs@ghJjYr-o^q@&><!+1WL2fsY~$#!O=}>4}13$mA69u?@2z
zN6c1QZBD6qJ0b%KyM7)6RbBO3tRN4G8lk034o5KYajSUN!IiUI_J+^|XBvoOWI5!D
ziJu!SmiDeiK0q%);SoNOa6a7}Rc;W}U~Ymk!bBRK=3YK!M^JUhWb}mSA986ym6XLH
zs10pLOI@w5-3T|jNuSVZlW=kimEVfeWVZIA1+1Rjik>%7?sSb>4n2XPm`zl*^Gbxh
z7%|LcqbL{1y;a&_*^f~${?AvGG8Jh$kYY9?La0M&Yb-W<TbQyjPieY>48V6Lh+-(T
zX`wj-l_?9IO``7{!3iCra61!3tT%H_upgvtns86C4GFikTy8FIx#?a)#0aaE>;!|X
z8r1e1g+LCT&(CwJ6=B?fmogezAu{90VDk|LTYdI3g0zbh1@<DOHP)#0e0Zr6RT9>u
zRwq_m6Y$>dd_bHma`EuLWXc?2TXn8*#5;jtz->{aw&bd8iRUmiT59?AY?(W={!OW@
z8$Ij3AVxUN>zK;Az{l%zFT0fXbI73DMhH_uh}S_!LWHfyxC5i#HW<xfeQ?{5J9>h;
zKW8D}5LDABJV-O#y+-6tXadSWfb@p~0fOTjdvZ76oI{q-$lk;5buUzR1~Tpg95f9W
zZ%V06AzBe|u0bmB##RYL45MAJj-hxpq96n!n&*#MO+vCZLuV(fDtd&5L-Oo=4MNW;
z$%Cvb$>Vj|5js0!2asVgc?NRWbgDa!xBL|`L1X)rcXqV3Rmjm5o;>^s@f+MTFp$`m
zGXz>)r_A5rucOdLumbp~1;M#}*Mc!x^48^1r(sKe-&j5u-V;okY4yi(n@LgQp?00}
z+2`5E{QtF&)vqR(dHCFU#^E?QQV2lP`S~MuRsPlql_ucGME$qk!bd{%TbFM%j{oPM
zwW@m%9lVY2P=5J_(h>I3%sX?ewo=ZEbN01&g;w~^!#qV8k##PJRdEi_-q1)kXI&o6
z%NINOeUuD`YIERc1wSXpFouDLya+4Q<W)4^!4IC@czh>rBOq35&%L_!9VwA$r20o%
z_9Lp4O7;<cw)o1Ftm5nm0XkP*X~knl-N=hPM+Q}g0<rQ3K5pKfowrp!oDs@*I^X$N
zZVNZ?R$<H=i@YgsXRl1X@wKmAv89tUY*AsJU|)d1b5mbh`Q(Y0u}mX90d>f$^2#yu
zzxjCTOzrfg4_W>*Rq_9^_BLRaRcD>=yZ703dRKMP>?*3EAV5|X1*x=z6d!Rq1d~<O
z1r`aK12zfa!FXUurp;u08pRo+L0455q(C%9B$?KUnFFG?<r;76WPFg(+#P6rI?A2t
z$xR%5p5#uMo5{2p$ES_aL2u05-+%3M>Z7ST=fuogb=F=V?|R>Nz3cm9uN_8zJ4BWG
zsed+aGp*#w=5M~q{AWM7<eM!9Z&35APo>Gqi)cxj{FO6w&j(mMM2YT&M(xHFl!eHp
zyWyKcJo<N&w)Djh#rN1krOXZW8yHa!-6;`D)QI@eau>IU@NO$>7%@_Zf)FZAYTBwW
z<TcOFoQ%!W*7)5^slPM0mUUYQ)=H0mDRH3~PBQJ+zjvtiyrj`=dG)1vE6GT^mm)uN
z?f|=Jm$r}MikKujkKc+MnX9|zuTPjAxcKarS;1$4L{}1qAJA}`mi=?rM~uT?N$gkN
z$QOlJ%nXOVw7aOgwY{ayo)a8V{H%~znwT8_q$Ocwz}fQqW^JayvdfJhj(c6fKb#bU
z_1k<l^KxQ;_ykoK`GX^#D$K27+7)uf6u<m479M#y_n#qoLrUdNkZaW56&juFUlV7h
ziOB;y;lFpAfDqsRjFUZuHr_C$N6cASb_Cdtg{wyHIfnrWFJ+jsfeJUavNt3?S$h|E
zko|IY+#aB_KGP<ohHeWK`)?ucJIJ7CHR<dHZ6;P6cNOaVjj7k3&7WJEe>|aLJ<+ms
zg%alfSulHUl#J`Z@@u?*@)=Go_;XTQdpo)Ppgo?R9Lh^!JbZmRtMQikq2U=j_)!&y
zY6EOk!98Js;l$c#;KU5SgG)W|DKh=Sk{6~TI9axVB%ZL10V)Fm#}B)!2ADK&0grD3
z>Xts0TQCkGL_!qW7<(YTi9<s@jx#XTl$N#yH}o!QMbup<)3(Lycvc#5Sy@#F7aJeA
zPiyMyDy$_RD4RH@+iTX*yAq*hHiwfeCKAN5Np)Qfl#nyyaREnQ4m|C6YV?SsYT$VE
zf-&1|P3AXJX;(;)qC2!JyVO_Gu05IhxEA)xNNvQ`Eg{(q&cNZ6=-b>l2)+et8;1mM
zE?|ttZzoXGawjiC3#?yFV+R61pSc-xSg=O3ZAhMW1r2=R)v}3R%2<yb5*K4)46iB{
zOR+Gq=N$(a1KF1ay4!mR;9AlR7|c-7G2D#y$4PQnfI!%s2g7cH0mdLV8<%P(pKix>
zeM**%uO{9g(b!<Rovk;yJKE8PZ6Xo&E1J0uSyHe8p`FK@4hYvhpT%q|It?4B+uPVl
z0awF{#n3e7CZJ{fpg<{E#asuknPa;p+d(=XT0-xc+90fT;P4>!_SYb@#)a+pt{(g%
zMJpqX>{e0K=c*{9czAW-F?oX>6@cPFXwR}k!Y6XfCT8x%FQZTh?ecyk%jpc3KLa*r
z4l%ny>AHoU71kYhOK5aRV7EzNkMD=@qtu7^=whtIFzSp?T(n{+TdT@J7X^6UjKh!O
zQnh6AYr`h4qv^DCm)OK?C$z68Ev{P6(K!;q(?KD4zB4hp5Z(B|JM{$3NU%2K#%BZ_
z{L<Bo_7ce!QG<^4y8IC-1W12f1LVveemcSBD5hTCy+E-^N(4ph0`TntX<O#j@AW`b
z@KW4=#NsrvNy-{CGj7z(&LEH<PC3~+a(5qOKpC<TTc$5uQ}^?L;?&R;z-)PFEuk8}
z9^G8ZC)WMj%(J)a>t_gutrHeGU4i$O6wju4;s15VtIN~1!<6RCUv7i$%V9=-J}DAE
z>iJ?AYiK7v!Bxo2s-E&U<FkB|5KPln8~VmM2a-5j$tRNRbZubF?{z-AlS3XlBn*~M
zUK+@UTHil;vptyKqpgCLjju}^32keT`9=8nJcGj_UUx61wje1NgM1{nYyWuc3?58J
z@Iy!TtVU&d9BS%16fD6ZxjcyO`HKS$6KO3q66E~uC|_&LMqXy#`Df?mnzk;vhzd?O
z@aU%bxf?UPkJZEcn;AKG!Gc)oknqg8yx+a}_OS5MVVm<`*<IMR7qfr|lK|UHXp<ry
zB`e8>JCE2swKw!J;)G9<5|i<52>)fz=;%#v(F&H8$6sXwm)&er`pW0${XjEq`dXU3
zV=QaTd?T1pG;JL{+=Az2d*+kz+bNMPE;xSQg~{WmK9{*=rmf48?8|?CPC5OvtX2;n
zA`;tu_N$kA{CfaVYY$&yLwpg!2PILoI?z_X8YT4$n@V*D<Lqa^W4$o^+^0j#V<EkA
zw^hDOQsX!BJoX8vs8P4L)>^5vr{1ia75abxPVv|2QaM8rT6Tps{Sifb^i3BpRJ-&C
zzsKB7-(}W(ftt&<XQybzvuW!hmzkrHY|xti(a)wqvh)OyJj0p%&jU)@z1I`L&-_JV
ztv{JE`}j{<>lS>P?u!#)=&vq{shtrHUq5xp_^Hgoi~qVvZ~4?*#rEd6v5p}UAL3ir
z^~1&TH81--yk{V!*);>j+Bax_e}Q}6z~~Jq_xy$Tb1pAks&a5^=58V&j@=<NHp2b&
z8+k%==g~m95h`0*TX#FzJPg8c^!tk=9MinqsiyY>6BeG$ZFfEilQl+ulU2mEH`?ps
z?(Z#0;#&ib{m;unGE?)S*%Z#^VodJj9G7{p_DFJi)YMh>1Zg<%qgOwG{5PajEIV+*
zYWc@!t!AHEp2khUEjDJYk8G@PTz>Br%xOODX6!^lv6!-yY3rY+&vbI^`gD9i6Qt%4
zUCY56iy``%r1rtOXHytb{Q%141kpsQ(`{`%cc}LheJf5Cv#qR6WLCDKwOw14dKL=T
z(ngi_Svtci@#j#5AXE>#W7V~3B;qy44d98YYNx;jL~NrH3=}`Y`yQ<<*5=Bms|m3V
zcq~;_Gn;i{!YC+ogipzrO|0lE7CF!F@l$JGjFSC~T|3nZi%)HQ#9;{o&?p#kA!@>;
zs87+V0kxkc7S|I%XGaJ-hHL~--;hK`sWRLK*RgDQUSocXd((V~6N^cc%Ck=4EX1u&
zALvV5wT5wmvwPlx7e<pGQ|-XRA&+$I&92^DN8M&EsUTV1&teuCk@|vG#L^-Nu>x5W
zh&nd|=T$oOWqf@CTLPvwXr^qjH$mY~@dQBzLjlZ1kQ+S1EYnu%f2pnO?B7@OA))mF
zQ{b#X2cEtU^gdA_D2m@6up*MiC9+cO<Hl}le^d&19`MZyIp`r3rDiTV5_34cPI*_C
zZ$<f34BJgq+?(K97Vj0WKTy;F;i~Mk%Vo{x({WpD6sjfl;D1awK(X~GnAGDK_3~gv
z3BV&h8SYwftA=#+y?j;OXoDHoU0BJP1ROnq7?W99p(V|p=)DjEY6N`#B&G9YPyP4=
z<U%nN&vBH;%Tc9H*RVpWqA2gKFdh4xqZQ72WeXjhxoVZp78)eD!(fA8?9tWOO~>8W
zFi*t3;TGx^`d961ORg+alCG-?6P2GFPLx<>UW71i$L(nn?Uis~=HhlE<5jysOVTmu
z-D&|u5;p-3RD2Nfw*fA%hATTo@jC^)!vFNX3G?qPNY_R(I!G}S<#3(Tx-qpQGw0=*
z=S%PknqY{<v^B<Ok5pdW!Q0w7b4g33`ddkACl9C+Oxyp2+5^0-$F%i}>7@glLRq3o
z`@E}&g<UDit4fu877ipM$w2r;XZ}C+!LuS_dDwFR>viT^Uyf-@_qptdALVSy*L<Fw
zU_WW>YpJ#Tt6cz3zxX<k<p+_D#9d@Rn%ruqcMpx(C6gRP%%-N9wvIQo>+%D%#`!Jj
zqv`wEqnfFO)zwSp$=W`k<cp15$;9CclDrutV~|J2&+*Iq85|1HCSFI2_6`-gs^)bl
zDASw@v;x*=J(2GmH~8MMn^g?4eYpHydX?V`EeC27qZfqcDTI6N@Tgt+)0C*Sb2GJV
zAA1Y?$S+);EiE#4efco*{KlSQ=(fF`-Bvzahh$oWS4FeIX>ap~zE*RCAA6OTUvEfB
z--XM86O+3>^08mN!7Il5Ej4%9&Bb)_n~8na4<OI6$)bMK{i#O6E`TDocHgg@li9y|
zZP8eGux4LYk=*wxr1?Y^-)*(Wt`F8cGkd~*fGPa+?Zt#Yy1N+p!*`n_Zf|&ayeQ85
zsxp<jDs~-nL;ZM3*{cfc0YQl6?7(EoyQDh#8}W4|kOGd%B_57n_+>WkU^1m+v*}^p
zZCyM<+9F$gn6_5xk3Qgcg_-}6@J0_iGuh?dnum`><ha}V=$wUvRE#TLM>}`!fvomx
z*Sm_zd&v|~JO`kCAj15+C(N3SWcA7y_Nck*3Bi7CUv*lbe5pQ1ZfeM7hncpPe{!#7
z<M)g>KlqO=Zyp?2$^QG#CE1nt2lJHF*^B-W1Km&B^6E?H*e%0TtG55IS=6}k!&NUE
zZxVjr`AqQw=Z)WeyX`?|!AYKf^5z*mdV+iWqI{ZfN4m8qYMtFy<-j(e<%<5`i?zVV
zX~Crh6g2B$o4BicrmEmG>N-x0r0KKgk~jfA)_6~}_Gg5*a0|*<woo0k<=s$0Y|5`f
z+jmiSn~&hbezzU%>?vJK84?Ohj4Df(w;abxAH10Y+|O>SN+2(tE19YNdbXkwjd}s5
zqCb#+T!Y;6(uMlZDd9gj%K%8*pEK|W3f(`@+8080|7#f*?c)<74emuaITUvceR_TN
z%<E>(BmZrzWd{f56({JIJ}qk>kgbds35&C-{o!IS^h%~~Se*i)v^ot<J09Cd0-+5Y
zw%edyDcQzvRiNg7Jzzbi7F6Jva7j}Yh1Sk{mvO;|1X<uW&Fd`bL=~!dD<U7|XwBfP
zw`KMfMxUlnZ9;>hPOM2LzLVU_=22_$5wb%`$Pyhsj-aN1MkLHp{1y>;lyC9IP2eR@
z$kY7Dks|vTK`jbRE6NuQ>7x(u9F<WG@nA3Yf!`0xA_q334C?gTpmd!DXz{7G7kKqx
z2}fWhbf7z60T5fHqFT@uoI;xm6s1vD65Cnu(F-H5l~&4e%2tXMQJgXF<RSeej%QYr
zS;3HJLzbc5=u*e0>(db`i5J?U3i(BnI(HqZQ1AXQzrc?Rz%4tus1GAn;HEqQWbb7T
zd<s{XpceR`(kF`3{BSfiq<@~mVWbKeuz9a%Pq+pQt#71h;3}`Ku+lY@K<y_AP_S?E
zl)yWKifn`!sfOI^KAn*Mo>E0T;{(Tg<F_n*^igsGNduBtO1!MRc8Xu_=a4RHF`^*y
z6zWXdB4<gJ5=H0&6_VrXhf3|Mu?RZt8>b73m(_z$>ZxT;j)cM$8NjKP(y8Mq64MgJ
z8rV=_;E!yU@T;sXU&-?nKbsY1-x^{CU{SGv#9@3V5Zc)a4gYP^DclZGdM<&sd4Z<}
zI}OnB=owwDSE82et9xbQhl0X35^{KG^|f|5cNB)h6>4|WSHTnsV1k+_&6B~iyn!KW
zK`C+akz`@kR~AfeU!+Brmb~L3Tvs5}2%W|_HWxeT1_BY};~TFEC!R9CPk0nOM02_C
zGeQqEu4F>s2P8v;bxX&i{k$|jL%fn{>{*>#e|I~idBrAFrN0NT%tL8k(>l9ZY4`km
zh0kv5;2L$)?Q;#z%7wH%z#!@WaV>p7J7Kis>~}Nc9C2c2TxthAdV3Z{&PcI+!?C4w
zKriFk<cKFyHqA~E)7DWtIb~V7Cl6+vLOXT)k_`-3qt2Y&)^g|@TArRG#;p^K;)l{<
zKA?Rs`ELpDwmxjvCZ5rf)wMGVBI!DS@ovQH4dIXd!6LC|=KKtDYyp*uARm=_$8Wly
zasnb(GI3W9hjPi=2(e`&K;nf=x#Xc3za9h0oOfFjTRT2PsU==yJJY$gsEQ=BE2J*j
zl?|}l>IY|6^VyR`2eO|^T)f=&clNOc`%P!fwOuxvUXUck7Z^#D=ce)SX`F?9fEann
zC8Kv9N!`-ph40F*3JkH@U-N&UC%ugO;&ccElponWpPYA-3)lSD5I#S5c}Ur`%WUpW
zipy{KsM7qzkIviiR+3Nu%;3C@Hy9cGx81pY<b0C<p^5BK-fbOQexrNh4R<bnrud_w
z;c@2VGqVU^*L<vE-oqTdhz-I|nhyyxc;#RR+Ul>Gh?t|BLpxY!KVz=Q^L$1P?RQ&E
zC2T!FR2;wX&{a-lQ~T$Y&z6l)rmbwWwCIHTV*5W`XkD|Xp?pePf3eF{zBOB3{pwy@
z`o#e|aR2_gxpxj^*{}UXX2Tz>PV3I1riQL74$Ue0RR_26+LHbL^g=8b(C7~00_Iey
z#!{&Snvb$T%pqa_t`9tPviT%yM~7_I!U6EEyni`(;oQSG_u0=)`|#vVvD(ZWrom1B
z?XZsuS$KHFh8}&+6^&;G7sJ)`E2yCO)j|4@f6}=xS5$Ter>*Si;e)ejX`{X)+0OX=
zhpfGOsk%#G$0&!+ZD-h-4$2JqyAGPRI%*BIxEBNq$C70C_ySttZUejB2Bh#N9jslA
z?ZssqDmn9SHwH~x@umI8-*u*~EcXvAvJ@~8Q2R%cEDil-E0hG}#$08Sd3Y|hk0+UK
z@8R86-Obb>U-r+#_jnuY;74=EY_+gs6`x7Yv?O+nk1PRU>3VO|<rM^fH>YPVv>;!;
z$l+Ggr^lTfy`e;v{)dPfmO>jF{@X%ix^2i7Plt;i*Vbcc=Nz`Pzz=Npps>b*x*2_(
zuBvqFwO}*)HueQYo#q#Ju8RsokC1UXG?2(uFdS+eCJXe8Fs%?p<+~h+Fv~^1j^_+M
z{ef5z(~}8p2<lBOy_HRhR+TE8!<IFC)n?%WzlA{^pOlh-P-r&D|2pV%10jQIT2?s0
zO(1B#8D|}N8_O)IRGnxu*ksv?ye{`v?^n1SKEAXdA-(J!!VMf7z_&ZA02-O-yJddm
z?<T2)SDo!ftZi*RsWnw9CSe=%D+tZ=Yp@3=AI1$D29<W-4E>D=x0%AB-9)fmGA+-7
z&Zv{=pmhV0X+uKwjNn-1%Xqid;nGDbi?C&-L2Or9BZxR=^H@r!_)!)fTAHmiT*vn?
zSDvbn2D-8mB~(D9`E?R)zwI9m?~pW=j;&g+(k(`TpNM%qyTWS;9dZZ~uqdy%l|kS&
znumf?Sd|)0T7sAgYg+e+6<G-<1|b=#YoQGiqxnjx(hAy+AhzRF5w`@nAtp-b14yGf
z#Kc7>3+>vh2omK=yzxzg1jttWhGZHn@!uO(i5Zl2orDGK${HvnUQDKNI(puiT|s#A
zAw94KGCZ6t2@hQ+=jDKEM2Xvs@`%&yHVHY2)dM71h32ZF5;h`uS=&4;$kChLD2PZ+
zo`n{Xv&0c?6J=3w@=5qj^P81JOws}3$;Zo7cUss8)Br{54x=HY4c?q88S${J0(Ft3
zn2G|Kc`xP4;bHn9MIIcp+8maSPppC)6q0#QTzoGq*wzaeJ%Q6-IjQk_3<X_~S4A3d
zeB{rL5O51AX)drd<R(ZJD~HK&dp-;CFwD`9ECfg_wI##XQyr0vCC7-uwTt(9nwi=a
z=uDE)uoKV&knCib(A=H*F;a<E2g(E+NA&D4zp!~M)4_Pfb4`dr8R7T?c2(!R4%5Iy
z3XDu`tqMTDEV;FrAS%kCwe;STGIAy@j%z`!Kekk94dTaa*_sLW*$;T}V0^NIN(%)T
zD$U}@So!Qz<~-;7lJm)R9A(ISl3q#bTM~MA$cLwGXjTNe!!Y;G+x;Bu1MPfXN^7+1
z*Y1$0xFqcWlCT?$J7|x~w3%*FX{)e{5qnK+cKHcign&ZG18MzC^ldQILb6h=H``sx
zi$nq40m&W!k=>sm+Y_oB>>i_QsIOQmFA%P(2K6dNvwCbYr483{Bgj7-+H5H&Z4l|r
z@QQ%Y4jp!~v=x>6w#Zvbw-B}mC2=#j&5l0oVk^nKa62LgIWigF0c@7+JEesfUJ6-?
z7EyDtHH|vmmUwkQ97MHcKtiPkd)8ym(#lW%y}?y^L&dCs+P<EZ(q4p)<~r_}drmG^
zL(YO%;GPxUaXMMFC=r1L!nTc>nQYK)C%?Voot7O0o=)LTk-U5>DnT@={u&Yvhq5`?
zge*|e3vm5_^B~?@syolN;7hO|A9*|42Od3uUCIV1K@yHRqgks!eWjC?bi{<x&{k)&
z#Kb3fx5Q<D-*oiB$k^#})tC`iH=ud&X(`3f;L?|dcAjP&6mv~a02!V$&<-h_<_In3
zd^K!YfbNWFOR`3QkW?yJdV-=|<_0JoP1Yz;dHa}ZNSD=vswW~K$yl5SplYh(c*;(o
zuO2d^-QgFDa+DqIWFCB#nAZ_8j^-ufTVsSCh9o1R%B>z^2PlRAP!JhT4Dv-l*QSQY
z*)T1SrsZx6r*JR6PC+V=C)F_u=xBRG-ABon!X}C*6|Ek~X7sAyc_fNTQz`TODuZW`
zA}AaNn%HHL8kX)LW|1H)=7b7iPk)j(ZCTC{ZhJ|;Fi3WnA`QBTYe*T>=46jH6=x{9
z;N#N<W?9`%hRo01L5wF!)tm?(<L4R6_l71sC{Kd*q^w)EMjzRvvaKPna5-e0-hs>p
zGTR&-XtC7o6v0KG;0S8BHmIy05UpfPgCp9NiTE%JO@2$M?ShC4V^-$JqXyf-XFt4j
zoHMlQud8>8FTTNSLSlw0*RaL5&5?_t((8EL#wMeGW#|&0Qf!Vm&Sp=QbUot<rH>X_
z6*S3-7A7tBY9d?R(B<lzNOZM|u_U`{z2!O!y;77s`)Jf%7FdmK{S6csj^smS7xj4i
z+?*H#+O`RAPcwU<orUG^k)UU8QZ@%{J%OWNuW@|soa*woEb_P7{qmW>P9^K8;n$$?
zx=SqM{Gs_vQQJD4scd{(qi_SsAm0%`NsjnVwOYs9*+K>|y8l1@VLc@=Oq|`!?CH0b
z?EK<Q^0|&7{s$dXjSlPIO6|(VfHQlX6u;*Y8*06sV=wowvQS(ze|+2)!ktStQQqXo
zlQ%8q_6;tQfsR}JK>k!)X`<T&Zk^@T>6+EneyFX}Hm=uGV#qu2>j!)&Kg124H!R!X
zZ@~WUJ(1=*g(w=U?>S-l#Sfxm5!IJ8?DsFqv;3QFpIy%tMe)~dwu;mP($#}x*!+E|
z&3to_w(pIxERMXKgr$R1`SAQ3cwzL1lRSK2fx`J8=G$x`TD&|E)0T3v==7BB&TL}P
z7x~R|z6ZxDSXmk|KSX0oDudjMALeG!DVtn)X=tANVrE?!7~-w!KQrfTclBCS<7-(`
zzV8jJC|>8yokp^Uh9<%z@8=ZMN}Bm==%$NL@?zMn>`*-RJxRf3A+ZVHbNZX+;L#ga
z4kF1>((@Ez#Z0K;j5<A0KlQ&Ydn%tEz-EkZc8(c_3YlhR6NR($xMFgYjjf;?TAbpr
z`(O(<jzyLAwHsKjA>7;;6K}qz6MpTA1TN#c9JI-iwEVW)ZSnZ$Y?%!}Z}&bsYVH{n
zCniGC{!z|Gj*YB%TPb&OXYZ%Hr05Ckotbxx_KMwmoZWGMj1ZQf`_)_6<(Q|MNrB-5
z=lF#epJfR3DH>S$OtXh{_czX?=YKq&H7}n3JZ!IfolhL0*(DG2&iXqFJ8|krKKRxj
z%9&qVcywhTJE9MR^aI)OU;0GbXUQUCEc73Cj^%a^+6XxVh33{SAlnGt$>#Zl4>^iL
zB9wIY{-c#$YUl-H;kb&<HNLuQ?5SakMetJY(Z7LWGxJblPqLMntU>JLWnl7oph8Tv
zk)w&fcGS}e%RDH4Hzxw|?gKiVOpz}k@E@$iD4)8JkJs0;v~%c^0rstA{gt6{;I8&?
z$A8RU7h01xy*iRRA~kLH!pvIlvl$#AKV1ZCyp8;QEkohJyOmJ~H*y6r47>Dek$p7s
zHNGdxRoo5TY4E=e+)kwY_5tMlmdsa`UULyQYzf#tI=;0)wagh5RXV`O^D9t@0x~&Z
zF=+$loa`M?{=4||d=)NQC}6Vm1u9K~$N2f|Ld?45&&vm~V<tM8PqO3%YG5=L!LM+G
zK(ffkAKM;wQ|y==p^iaaxYL5}iV37<W?>Rve(G7AU4hvTIFJ_k(Fb%z_Z<nkVo~Fp
z-4Qm0O3(<7nv;IneC3L-RQ1QLih!v?$*;Ov-~f#s$GeKeof8xgG~G)BHb;}hPEE9N
zX>6z4X_5<GzA8`ROdj-xun8r@?i5=xlyUptJ3|bcs1^^kHMbR_x~nJ(NZZMu6e$6@
zDr@ER*wV7&!qE+y3QXz|MIv;AzKY3aB2rJ((Y92ZTYQHtnO*lGVqW&AS%`SjorO~R
zVdtw^u%H^HDDkkmmzhS@1Z<&+D+*TWlN+1yjZ(H1TohC<A5j$23vL79T|`)*tcZ(8
z_N7BM&vu`;WlmyF1-2Fg-k}l;9KjMy;TVh0(`r=i9yb@oq~XjPc=+4uWzI{Rysiv>
z;FljV=j7-K9t{0}@2ws?ntsQSc0h9~$QDwWK<8Pxx|%PdlMPi?lHcJJrLVmdGsls5
zn~2pV=feCBGiQF8jxD{JddPRiglE+{a0g>1;#Q*iq-8#!xXDgv?`NA;g3Nlm%>q&O
zL$07MPQ>WSxofl*wYf2Lj$9(nqG|tU&RBTBwMxV=Ply*;Id}w65DQy@PpXif0OBee
zgjE4%jRXkMe5KJY&94mD<dcUF;rd;EYZI{~b|N9!+3-Mn`z-pme#xAUDs~#bvG%l;
zB%U4bm2Nhz?`9r<&6A8Y>W&x-N_+hb#+vjkctA>dJ(kY2b!`^PT4CX}IYycs4rHBg
zbZv;u()-kg_Xj?rHU1S0IhQY9VcM=|+M12+W5#U%u9)E9k~3bBTTV;58Xyffuvl~I
zHCTTO&hyDs+IoB9{kv9U@GR5TYoNrj!@V}Y_-QRVcAAgdhvp(qPvZeFn!BAb7;9&N
zk8z@@)X6vSGpVW<==&Ia=OB$=jF3hZTfarc6a^;>0n9Dh-I<uYaO6_9<vK?dBiqij
z)e+na!aSsJVes!(CW761L*!JvJQ1EB-c{7T$`=lrFI?`I7tiHj;hA~!qW5*g+W&Z(
zhLZ6&(Ot`Sm)TzprS+o^xFC#P;3*dcoi-WuJ)zO~?~`0PWYhom>xVUMwZor3P}tip
z<z(pq=SD9^yMFCRtb+OBPgqhe)kg|;0F!1I49gD<<w^b%%1V}-n6~;+?BVolY_R@}
zTi2Pp<HmSvo>+E={DUlF9ly-#``CGu{yX4giR$O+`4uF+7dQ`wd*^><5%guV&_-8%
z^RlP>#3S%)#cwlWiA>^o%sP`1C!dFgoUQzXkC7G>sTcTf9boZ(CYZjj7;2eQ1dUMq
zJ`R1=UTxv%pTc(kUT5>~anmuFv^icVv$-|u&^_-Abb!H@etg$Nc<ic5ToLI8zbTD4
ze%W7Ll!oDhF(s=fu4Bsj^Ax17%(hyKsP!nXY4~9pd*>EoYW<-v=C=0MTG4pN-bQ--
zm`}?u>?)>CT;px}H|dBkp}XJz<IbKhj}*yGuTH`>e-U{5s?I3l4UtDTp<-Az{G0Zq
zj>+b~Obgt-y+aSZK<Px6QYcx}9m*{O!=s70W0%auDD`L0OKbiM6~EkdC!^3-_*Ol4
zhg~rpeurdOJarhO4Lrvq(1IlAPIBas#&zwj!NnkqOt*byXRv*KZ%%d1yd7uG5&o!y
z(EZsda3`}COH9RIN`2GWtv6Cr>){rgOw;Th&BQ}SQgVCLx2sLCUt&Z58FI*7W0|dj
z!XE#^v3;J`=8D_W(>^`!ZVa~kUFM4uud%D#KN6K=Hnj46S%)b;JHzyv&YY_uZdEGX
z8MSvvs8A3-P9fTf*fE~7=`CTbVRqaZ<)b+tNJ1|nofvwKo3~OCQjZaVODrL=z&qV)
zG0DS(S23y}xoGHo<;rg*qQ^&n!LfhRKX`i1oK`}@BC>?H62@%$lBJ?EM?%Cl_i~vz
z8)CN(6qvy_uqmo;B%ii$_p%VgpJATH#+<*Zs61R=UEvF%J2*HP$-vMs>pKG9j(x8U
z$8T9k;+>(~BBI^{I?1TFU4y6M=tDW=cBaq{@w3w21S;~`P4r46V{(?TkT_Q#wptwi
z%(4GG!+jz4ykdbXXvyGO1*uN6P261XBlSY@+W@bmup(JFMYRd?v_NnlxOX7Jq~{@~
zcvYa!xmM$+y2au^9P=>@F^$+kJFMx%-E6NRjBAh}N!990GNNWyj}+^X&p;&oofzp1
zA{}XKZVgI)TWU>dU>%g5O-U{ow<F)qv^8;-g_3w#2-HnDCsGYQA+39C3>rdG6id9g
zG|#|OK9pic$$D~zSezrw>FSJW;(4^#8=4)I)RIZrQMnSeuSuFy9J;sWM)mQYUT#(x
z?PBX>_xxZ^LyKV<KPk=gdvuM+R;yd$Vok>Z-P92~zZ*v{@SZf}H77jL6ohE58|tef
zRE4YK+U9wz@>9a1pdu*8PQd5xH^K5UDNx!3dX9Gliat9Vk%d$Ed^Ba-6jkL^x2zOu
zjgnPdE$J-6x`ayG7-J?ztNzKj8Q#X|_Gonig9iGjoF^&wJ`7k|DhUp+ToyPov<0T4
z$x`E;2y+)AudwzI`1tM|0V$|6OBDv@KJ#`<M;J}PNa?&^5AI?KRhXOLIn_}HGHe5W
z8^7(n!cQKdCTP;u&ej*V#rs?ty${6I_BB2iX#c|nObYB@Qsthx>4fZ+k8IuGu|p*J
zsmE=2KJ^y9FP5q>T+7GS?&EC4hex<eKUlrIESP^?hfZANN1Neac6|2c?`WNyC&8y_
zl%wOn)00>5A~>Dz=`?ePzTdRlYWkL0S^OkfQx4<v;}z;yd_05MAVOeQhkFq+%io8{
zw^IgwW85t;ZCwdBP>=7uAPY}EQ(a4t#l@Lhd)BRr4U7Da8xArnFPV~0+4e>nKp89*
zh4zm}7eK^7@Hu<vQQ|vjTB!#3j$jfkAdo;nO6%;l`t&W}9od)L#ix_h6JqZ~<JxU)
z$<Y&_S{}o=cpua!SsB0l)soxBA9mr?@Gd@Mzu%IX7j`B7Ro~BG_>VKz8-VmJ?BZz_
zR%)h=heNEecu`SI-`pA52yX}Q_z!-QF_*%>_EQ>|RWN($T=>~38}V!B(Jk(sD75LE
z-*NXNjaeZeTDa|xMzq_S*}b23)*M`9C-L00ICN)b3oErmyRGBJCtS9C_=2K#?|04E
z6!DT<7dVsp{!Fi1b_Y*z{$q>YGlsUW{&batohVKgsh?^f*_~Q}t`JhoyfCzNiNf+Y
z7bO)?@KpeTol>H2GondAOgg&t_!R0L?ZN|*Ew&y2Tl0?gYi=e<F8UU<j$Nu;8X9Cy
zde6hV*lqpsv^e^w9852N$%$=nBFS!Ro}V04+O%ICTw}@S;qG0mQ|*%gJz$!$0Grlv
z=3&L%d&~{%AUV4Y6ZOUPy+0ppvh`t&yX~PT?)$gl=k~mzc;daEy0%K~p*wBzv_H?1
zhsT4>oXnD!zOc(?PJG>8?VyldSm*M!``zScj$M%*{P!sA!c!dFq4c@>GsSEVxneu-
z=ig^dc3Xp8g7TGv{|g{c{NuEhxhN3$d46X@XKyw7uSL{o^~!m_y5Vtl#BJO&LzXjb
zop(RY=;X#&c5aJv(i`ZUW^Od?<fe97G&^i*BMWnBh}7~dU0}D>hK@7kZN0s}_o}3>
zBs~AUfm^W5H~!K^THi==rmdvlUqs3n;}lijAn-0qpupemvgGgP9Lt^1I3}OuvE<lL
zwG=)6wFWZ(U!17@3gxCrJ}rKFWRO)*x4ZTFYOjwN-N8MIFf_zQkKY~o$#dT(A@SAj
zX6<yey|+F#O{kh`oWNDZu3(ZHNTT|LnjK+CqElafOEiZ<ncu`wOMuo8`5I!TTQ#ZK
zM4!0xfp31R&Sle^0=ilQld>5k_v7ZqVs+&}Yt^s?^NKpjkHv}>qoq&{W91zfJO`ds
zCGU;(BLu3dm3+gE%+rwJJY=b^`u-h=c#2_AnePRjWY4S3y9vyUBGv`gHNF#$Z?7ga
zL2z{KasIs%vXxsxw2&ZJXELRXj?k;T`4}ztDbv=p=JOWrIC^IdN0~%;V6w1=H&Aw1
zOhx)WdSVnTCq&SvYsOt=?`Dz<5$eGfXUvv1;m&@B8z>+*8RQ9~3!for9><D&Sddc2
zk0{Oncw(I{oB55pMYtnd6xmq(Y^v+d?Q_+H2)}MXe_s;riA%MAxEm^A^&a6{f<xle
z_Pi1#r@%Ek`mNkXIS{lTcESSb0Z*R2!N=w7(dEQhf(jHf@EfWJ76;^@YN*JR8MB}m
ziYn1#HIZ~Y1qc^-aeRBpE0j&97ado5>}vA#qDjv^-GmY^SGp%~o|@Ak36D+a>%}&(
z2BnH856>@kWOqzNERy(e(2o#CpDiMWz(3D%FDgBu$$o(YYo#g}*#6<rZXQA!N#s*q
zDUlqth;5)ot|vIA66eJ+%#%yqp<?ToVe7|i0sWK}2{T8`;<J@Jmi!xBG{@O1TUcKe
zCQnNl<^o3%+ezuhxGmNsI9?TS0|Hi8h~&Bo_SWfLXYgsu5+kVa9cgf{iy9cOkX47_
z6EZNh;j8bowb%$G)l@M^MQ**^gSi7RIH1h1l&;;@;KDl39q@a26FrT)t-|}%?jG3o
z-#2GixDplUA{H(wjS=hBAz`XnFFGk{ZA>{eI$1XVedJ9$9cPHSmdx_K1r7y0AhNHw
zS-aG4O6D2PdE%c%9)3Q%t+g*dXpKd`Ih$hO*@mlXpS(TaWyP>+;kLQQirUR-IzD}Y
zU&hn9=5P35%keM{GFHGVEtmUC>35x-dSs@~_Yx2K+k>TN3OmKL)dpUhW_e?8@q~MG
z!f?>Sdu(Abu?Kr<Lpe_$^x&kWO}=pFeCM2;kBp-!1t@`mUtiFfr`X|B2hz?q$~pz5
z$%&4HyZHY0+(Jz3k5ESbL52@pQfm05?L)#rfjuF7_ny>lc*;hu97&e#k^N(I7+LZ1
zAPWJzEL;8^?`B>&kOf^*dYa7kA{f*5GQ}BtBFS2am41P*l-=^+dPj?Q7f^}t3jf$$
z)6&z5><8XFQE0by?TG`~I83}<b`@J~v#Z_{8hdb1efhr2=>YaM($;TLJ3o1@&sN?;
zr}zO*a4>Ckjj#If{1fM=4-LO%vgwGJ+|CGo`h)oiiP{r}PY3O`PFcNR?JT0Z4O8l0
zmpyuSH9|~eL0XDu|1OORlMq@W^vX~IHcH8Fd^*7k5R>wU|D~U-(~qqCuo3EK3Gw`T
zf<Jw3p50S88-3YUA1=8936*gI*y#lDTc5g~Q-6P&+v2f{oqzgknRg<{v~{|DNH|2v
z8lj-In9{u)NlO?#VgAQ0b6`zhHeKln`|=xix%`Ts=WE#KChpin?6y8~_c@c#Ja%Ok
z)0QUS9D9#X*E~D2bMJ7r`nTu%6N`UL_wYSK{>fiKS?spXkKcz<zA~9*KX8#{uljr4
zVp7j+nd1O`!TcLDPK@)8!aw^FvqLxbRTOq0Tqa>X#MzhUqk}@>)_pfyT-aZgqRMk@
zSK&{;xr!5gPW_3O2HHifLfY0Wg?7eU(l|~TxB>k(<5+EkHOXT-0i4fVJ{#=AEG^x&
zXhY4RP?0Is`Nj1^Yx_8+tq%{{(EckoOIBgO!c@=Ss%{gtWWQSyg6Eg7&RW{6`-_+O
zkcc%kNxmxyY5DK5SjDOIx6{f}?rr{~cs*-bt`{J<qO0H|AdRup`xnFE8(SYqpUOzp
z-q~q8M*CY1<nQAc$4sQt&A3=&=;4qi57yR_{iL!e`$*4@6y27Ppi0{v3d;C8I2uB?
z?(*w4%Qmdr+MHhVwq5D@mM=VyCW9s$u|!xxa%9VwX*w8%a7pQa&8YbiRD_k{AW>;5
ze5hubRRe=x7ucG*4o#K9Xm>D<HCZG!C7}{5(k+n6KEiQ2xh5IQg?s?%y(V<GqKjJ*
z9?AA=uTmRIOU^jWA>{55C7Th?Wy3z7nu}xZ?y>p`ZPuKZ1X7xyxhXl7Pg(Uul|wU%
zP#Vc<Lm&mCE;{;1NTP)Ea)+iz37k?HflPI}<`k<4MMFBQL~-WuD%k4^Q4bJkfkj-L
z10A{Lvm*qEDsB_*6%C@JekQ4~Mz8l?ZKL8=U}wa;0qyk)dC<8>W}zLL$l~Z-=XpLZ
z+N3JjQfle!R-Gwi2PmcadQj-Yf$HMBq-R~{!rl%LoS}*d51lGII*Hv58$YGgb;3Nc
zHeBVVkPgQ7PvXH=rod?;8fH;um6A|N9q?$+^~bZi#2U55YNn3JEkp@I;g{Mhp?$$z
zg*E8))O{di5UC!pIWjVZNl-vanTwWD+QSYg<?%Ib@I8(&=FhR<5H=t|T00eMnI(>}
zrA|E0o~<b%eL(I8&1qCK6_)y(hIgeJW;($wMC=X{aiJ}z1G%1Ewh=)$xw;h}lm}fQ
zqey!X$^bpkbgs8Xfw*4SBx!2XHbX@(;Ps;_c^x>fV~NkIFl_O9r300(!xR~!HR$O$
z&obs(1Ub@nFV8A7Hleqzd~-5}vfCO}k32K^dvF}D;xnd#0_9VQ2^x8ZIBdYu6To&0
zM2Lu$4yLz@<hS$O?8nmURQZOs&wY>$=S*!5-^PBX(>k;Us4};2sJTer3wo|W5DDuF
zWK+@Liwd^5N`*`swsvRYs~FC*tJMGkYmg~*x@8`R?n)2S_?)2;4D3sU7wG4Y#?vnD
zMGh-B6{RaUg+4(4nMvjEhWpc3e8lC;$;si-#Gjg7O3K|f1&*_o?`bFD>%(a!Ohb_c
zQnVjn6<=?S+<V^qV0pl&EwZjYk7QHEp#9B>B`5dJS$WHNVh2ZJw62CD^uTPoIz|IL
z>Wb{&gn^|zK@OS$)Cus6ZCQ{b8nWyJ`}jW7DaO(g-939CvCFFAIHj$M90L?v$y65l
z2jCzk_8-}RS@_`%w&_P+w3|bctt>eOcY}Q_&K$hJ*)6|izB#rxEdSZK6LHx3aB|95
z@|>X^xO<Pw7H(gxzN)x%2`DdTw!|kP?JE<A%u9oLvM-B=mAf%q4`ZIq)dBF=>$#)f
zBu&g-7q4d*pS>Huc3GUH`tX@OKBl($z!3XH=wjyBU{r{IY`S6Z`3f7vfB6&S{*PIs
zJh?k>Twg=7r<QEdWzE&GpPq27uOz`Pd$nbE{NUm`^RAZMx7=qmW_|Q()*A!OdX)pp
z+)e67O1Zm3N>aYY=RUsrY3jol845i9n%Dxy3?yn(8MvOukG+L2UH$^aojlINJYCW9
z8(h<g1wL#8^NzONgSO?<4WR0|e8}dgGR3phzBcm0?QE94=Mz#o8UM^=SS)#gc5JQ6
zKr!)R;)Q-2Do{mu{_ZR<u3VE>4{+!y?%bZCJ7x-OR~|Yi1oG^&yXZ5oF8rhjz+^mp
zH)HG!2L}s6qO=V%#w{<MOssxUu$k68mzie8r#JzeH&3CEOCIKS2%p+p|6Oe~|LRYG
z@+BKCpFQ8j50!{)S8yb0`2WqdTM_J&S2>&hte9>OVSDdQzCPj3u9lIx85wyM`FC8s
z!A`&w%#v%<C50Du*?<j|`;emp^i$60;V8M?L2T_<Z7+>kW7?h=D5XJx*Gg*2k5+a(
zT!D2>O;Ntg+3c#LDqs>ou);A#ijcl4j(ld?&Yd4Lan;W41LRyODXABAe|o6gJ3n~(
zgwf4*pb_&D*8|KnkjwjzBJ>b)y3sT&K8Mna;rV23-%9?%-t(62bUvFFjp9dbB`p)L
z9iC?fneKeZW%MGxLv_a|k|p{g0l*6(LwV_FQg#G}B0V7U>j;Q4FNZ4XPEZIxmLr}K
zLi<ThILS}jkz3T?dcbxTFby3srFaqr&0-7usK0{RM7>f)gHCqRgSR;yJ~r15yu@P=
z^e`g3l=9RMgh*NqD;AfPma30;j`3%GJwEkMEt1M;#oEPK?Qj){RpRg{MgrZyl-ANG
ztZBE=a4tYvif09oUEIkEkMQ1*25|JFOt}e%Wd}gu9#GhDXrUImm?)=RW=hWvzzhhD
zZ>Czfb<`HCD)X!myUpS2p_?rsFUE&M9GysW_6z)?`sf9)rrsNK544xk%HqQ^Z9RtI
z0>y*lQcwuOjF7wP*~2Uqp7~tmMen}(Jwa3k=Ce-GAyd3@V2U45_cCEu756v@LE_-W
z_TH*`dvX-{9R+(Hiyw|7Wbb$czk-j7K~G@J<%Dz%ziBBWu0+dcGk6@mD@~L5Oi9`i
zon{tEXuDqVa81?Jnn%qfj9`bg%8$TjFRUbZCG+WRkn9f5tOZ6?T%cr*4_p2jTqT|-
z`L!HIgyA?v$TF)nE9{^ns}=p*++q?-b~5kjbK5bxJfPqSPRKNExI~!oiNkAIBV5J`
zY|hbUY#|n`f~-Ybj5RD=X(1>B;Z7N;d1FzMa}#oLNEowt97<CEkV~n<?M6u9J3y-G
z(8X-`dLblSWZux!`8$B-S*uA=x^3xY_@X=?3u6>N2+zq#Sj1$il8;hZ<?aq)J$MPC
zdE%6zA`eI*n;~SJX(=i24&MVX($j(rJD;DUuC1=emTwPmv1WCU=JZt}&+#&wq)aP;
zAw=rU4hAeWskt)njLba*vL~$M$@<|88gU48O(lQR1yT^m(s07OrSX_Ph`j&-g5%Ae
zg2BE)vkQbSVO5Y`EjabRRrh_{;StW!|5Iey0UEY%*0N)%m0>Zp#&POQQip&*W1Tt!
zs_6#By(dij3MD+ZYC~fP;eV)7%8S{O#ogZ<To6i{-{GoCoL)f%Z>-Xo+-L)S*w5R4
zBz$eelM^mqDw9-N?+QVojF!g6MD$XNEYqW@3%6i>uel4$pD}mp_fp!{4+~d?xPmPC
zMwU-Mk#NtCrp~R4JUwcfrtc>UpS|A77B2z_^BmhdIqu%P;6Ms<Yu_IlcCcNK+myC_
z1bn^Cmgk32bp|;9vrjtd@dQTdQfz4dcys}}t`l?TRAv3W_fsXF+&!YSbSP-rZcYT~
z(z4ty+5+z^+Vh;wwjTt2@W3MS08jB&QNdOe<Gu=Co;!jPt-x%**<ofIVe!?mFmN{6
zRWGjoR7GYfxr0sK@<?d138{a(gNboDy4RBVt5duDOf5{;@+E)eP0ov8R}c%n(=pvl
zQkO7oU6F?p__G%ke)?cO8FvI3pT`Zrn5Q255DCslzeP1ZnbmFh(2^ZrsnIK(>zDJt
zTF#$;E}b`~t<&hTDF1ku{W8<Q{Blw_{9oVAe%_DJgZBaiad~sLXtF$NqYd6x`)g?&
zKs=|X9LgBq{_*Gnv=M8q)Z5&pMam&zA9vKj?@-uMO4ybx_D`_@P{1TCK00fDdBVmW
z`1-a+vT(Is)2zBZd3AxIY{tKQ1dXAJ{bW!09afFty7DyyU#q!Armc^ug^h=ndF#_A
zUrfrGn6?js!VoG=FD-0!>9SNaTbsY4lDP}dDu`(-^>QEz9De<uPq8)R%EvjD{Hrq|
zo_??Kam&>|`SD%)!jTzdt)|otKH&2g$0*1*-I3(iw&sSPKnxUO_T`hcLA&Jq&y1n7
zL-U^R)!%lBB}YG3OPBuBu10v`s-7}Mg#59m>qRrWnwkG4MRw?ZEn<?}6scE$N@I7B
z=zo_lnR~T4wmr#Y8kZfTteg{k^4?gNgFZswld^-$nOke#MAU)o4?2E5o;nP4H_Dk}
z@b{$wNm6*tHO^oQF`Ka*O<Z#!3&SaFE4Y*gO+scD*g)8aZV{Q?lN^b9!;lUf2OIf(
zg20b?%FCjyrN?)#rpLxv9-)P{XRlpEk|X{sVt3*8bn|{J+ZUcQ7lXs=mTc)dJC&Yp
ze>ae?xVVw*yQg_wnK{nqlf;GHz8}FjS)xT~;T})D`H!pU?VJ;l`_4vi&^nKuy)G0s
z1;s0R;?hosWatzfU9^tI5bI>U6S(tJ{SEDn71~Mh{Io$A!OPrIw#aE6+e(5$09KGO
zbiH;EW}<uooQz%|4f`al#`G5E=4fFZ`z_3OP%NZ?YR~x<6DAFXCWx0O9wa3cQ0han
zKGMZALp}LW%Ss9i86&icES4@n;coJ0g9*p{8h0a&>w?`g$kEHk9SdeI$UNRHe?c6P
zn4O&5RGel=PmuW3qbkAJy8;zIhWi?6!R8e^Du7o+=gh@G6&e(7=CZbrPzHGYRi0T<
zb7D8*%6LPI{CYsJX&>cd*84bRg%UCCV6t=)a#NWlKFU81naGzXK7v&liQ<A@I@k(k
z@>7yS)@gpr!=e3370M)4S(6d*0Kc9PU`HZ>HesLljMEjN?nf9<XL%rz<jP`KWb?Ih
z9l?90Q7VXlW-5_Hs28|;(8PO*vhF(ZtOdO}>iX1-p>UDOW0nsmu2yos+v;IOOA~-&
zO}IjVNa^M719C4UnhIsa!Yb)rB_;}N{A1--%?BDT>K=tN2veXkXWEzrq-uS5BSeug
z@v8Yj2CYmF81>+G@>~sx9^mrSY@;u@4lGGlRgj&d#4^2ea13c;`e=)W4;%LFY+5CY
zz@$W}TdvX}ublKYII7)<dXGpu8=gBKJi*JFhrYOumwN*8g^t^)66<axC#?fBQj;ux
zy)4M3^3hLXBas0{BhiAKi<dbHQ%Qelp@o}_2w{fjSy_QIdk4M6tvnaGIYkwe;k4;+
zZ(&&y{MBq{Ioy=C2>HkbNQuvURWK^wolPy88Imy$pTLrj$+<0Lv7l`mwAqtQ2>Wk{
zdvvg{H4RA2Z4Qohr8q<z)7A*tvn=POx962_^m>7os6p&aUeSL$qiCF?0d>BRO~sZ?
zI4!>SxLR-{QqC1o{+zX0Qg;UoyrVXppSI%KaTs{IXkKC7UO=;Ji(EqR>uxBN6U*Ci
zd8OY2j>RAKr0=#gJesT)-tG=}u$A=Z2WT??5wrLQ?YM;pW6ZD~Kl^%SuWgLY<%?G(
zE^npTMPY&S5aUHFJzaaG#k4ilTQ^a(F0h11F8{_rK7S0Ir4PjJb)C?Tmbe_5Uc{$j
ze$Zu$i|ukn`|TA)N+-R_gWzQ81t-7uAy+JaS8AHM*hK98eVYP#O?1ak-B9G@pGiZN
z5AULSth~c)mXL}q>mz~YD^sLi5F7_Ev-b!8sk=cHbzt=wek<DKesjibqh=2!<KA9d
zCdRatW#RiZZ6)C|yIeS-snwapF0WCOuDp4jMn!2SldF%Xn`0;`eRcZMFMfSDBd*zp
ze(YTDhYtn&;m_9Q8@0VlY54s;@oKe=v_1ZJD>^FYXQuweO!`|ZM;w~+mfsSr+2R&F
zrmdXDwSyrYn0$)l=U2CG^dmRtbIJHWPsrWg5XNs#p7$yOe|Rv-i;u+dWK5J(<aPBc
zn?dRc{=QwTmQWVfUj`-$nj$(N3hR0N*c)jL(WLu(HbdEM&E5QW<<uPD*Y?p@U2U_z
z&PymxK0Ux6r#YXaZMc(PSc;8=F>Q5P60kpDzEyl-pqjR3|J;l1s@3RNbx8Paprl_$
zELJa6ekn<7?b6+YYkWO-|3ER3Xt(u_f2yb!=jy-xCU4*U`$?A9DA*<M%MxIz6FsSP
z_n`qR$By{s6&J1KM;}hzB3D7D_4~85`O?)kaY=pQ=np;^!Yv-*uXrb!{G~y^c=L&{
z=cb>wMMev~;V&jEZRSM3e9#WPj$+!*fmg=VQcy2w+OshQrfDm!TD#tC8!em@;^JHW
z^0lC`+xphlqiw`vlV;67;Ih=dhJA{3@VwOgLo~7I*Pbbs#MtlkX`HsMq1JH4gr=={
zt3Q8$Uu-i}0M4)gcsO6pc%efO__o|iwDmUN7ND7yHO4q!SYD#g4w2}FU6joD|Dtlt
zK+cXIiIh~j1;Lvn^J<4!2yt`sHgqhTwAQ&{+72?GIjzGCW62oPR+e=J><-8Ggy~g*
zxAxf;uHCvc%@ARk_I<+K@j1oa9zySI4aA)D7=V}2J&Kx!2&4~S)*UKabW+RFSP|Ne
zogafjNgVhrNyM|s!8Sl60w*~d(Qn2M^9)hNTbLQH5K$7I>jU!Wv!mfv`#5+^Ld7CV
zV%+yn>reloDeH<Z1Io&?C^R)woq(f8%B90HTsqnoEN)7&CFUm&QcY<##?@YBjsbyp
z=CJn#E`a8yQikEXDM2$kMncZ+5E#%62e0&LQ;^rdy5ZA(vz)Jl*iC2QIov_YC0nC-
zXNAAg$-y%sdDyymiZx;oTXT!bq&<>6Vi&(muV)Dp9e#H>oMox!2`pA<m7|*(AT<j`
z3JMvh+dyqr3;VWg1kqUP(DO(bHx~yJn@M%v6r5UUl80nukZ4P#Hgcfljz!@^EG%xf
zHQf|KWhbcV;?xs}&B};*h`JG`ITB_Ec!g+Z<N4IHc+Iqd9}3gwE!V-V+qPJ0-bZ(=
zJlKj!IaM4=?NVl%_$h(k7C>wY9ZBg{FFW$gIJp7#8<fX_lAlB_Bz8zv^M_y-MXJgs
zzTM#cRbW;SD}08JV&G;F8_60H#0DaJ*D&hsa18hYcXSdp=Bbz2JYKViqUOuNI`e-(
z^3!@qrOOt-^<}e;rsUThlwT5Jxd&SJ;228jY&Ul3aI*xyXJi^sq?qd9WfTgB!j<Cg
z;3^e0IAa&m3N^&^P=}gTs(7KWN}_@}MH3<1h)T(2dGRA|!EA+W<ySh4KH+fnhP0-X
z?@=oiilok+OO;e%(L$tH5sMAbH1=?7eEEV=p?E*SepcY=`MFlY!WdHdI!*2b9u$>)
zZq-V5*{Ti}te&7luFhrbp#*R%VYZ8uBs+&~;0H!0akO+&%j~ajYj7ic-4>$lm~<(K
z)7E#aM0<SODSaVMTU~#%Z@VH3;SjMu!S$}rhe(I{4VT~~7Ji!dtFEI5EN{VQo*##V
z*<wbaXNs1-*~6%Y>XgkF>;(FFjts9p-~l>rnxs?gwp#iZ12!;Dxvmw?Pp9`1-KRmj
z*vIZ#evC)p2U{Thx}~q3D(2=F+008DH-edEZ?*Y!jT>cKS!<jc)(Wc(WBs(fnR<NR
z%}Z}v8y<-pBPs^HAoU+AmXk0<k@%s)+nsak5xi_7A+-m7j$cm*<@fqDdvjs#D<n|E
zexOZ(031#}Dj>>nrmYnd)3h~zCqDRAXKqnQ$+d|-$fpN{gsJEJRk^wUkfb)Kp%!ev
zfZ+L<vtNA+0k`9K_a5$!ZXXiP>xFAy$@C$#z2A*HLu7UYA7&G^2fuc(rbln3f~UGw
z>dsRxRqye_&vF*@ZxI}O^AD~Y$-=FBVrq}cM^j1Od*qGGRy`Q+X(!F2$z*<H$mc6R
z8A56GBxBk-&a_n*(JnqU_Lh9<@@H8SzVWJH7yhkAVZGt~cO9VowkE0Z7ZgR~lN&Ld
ztn2ERzN>1rfw7&f`8CZSF9?;w3O*<V$WT2oiPXvCSZ?F3K^GDpR$#UK1{TVNC$=ls
zWI8<J2m48fzw2#9`sjUh0FMnOs|WW+QR9oNM}GjeAEnlkw9+mfO|z?+QQG%rk;#>Q
zkgoJYmfm(9#|XY^F5JUgzS>0X2f`EAQSmi2QTe^)15xnjAKw+`e*1cxaJLTH)k;Ya
ztxk!ak<ZC5O<6hjXyO0&@j*NKFhixr_mK@0lIF{VUvkCl%FVYYrx%{AT{F(tgoYbu
za)0zU&$Va9ZWx*rwVseYm1oVF#Dyat&c~+T-p1cnl@h2Igcbw#6Ko?Unznv%m({n4
z5%aoA@O#bKu#$Y)2x{L~920sBZ)#XSK$3a%gz){$|8hq0S{Td@wk6e^^h<T>Ahj@j
zjImcz<7T93ifGxPc$nO6q4dLVr31UxIOUMc=W*`a!RYdIYwufTpcOJJX=@tykp%NY
z$9ESCc1Py@y+>lv*@l2;eb>mJf{WkT&6`bzzIij2Jq(b30)?GsmDukMmINk2O+3Qy
zvOYOJF=g)U%mVv?Joj<*mNYL2KK3%wYFjT`2rO@#*IQ8J`1vN{3N`6Ey%B1xz0Z@L
zpqZaz+8TYM(ZnQG=9Xj4+X&dfHakLNxauI$k=-$^09oTf--$FIEhvhYlcRSj56x`j
zo1=Jh>rR6F8anj@oYA*M6~n}HCm(z19-bP{LMbF0JEv#Sat<*s19iVSrZgZcUXfu*
z9JqcKgV8cQidm~=o(DA9RS416%gC6G%rnt#YH)GTn#)9h_CFZtMXbpT&?vr?|9)Vm
zjpTW{wp}`5a<cB~VWChcsyBv9WJ-lC3L4KK4^Sgu+!nDhug!drUkC}~i3&0sta;CB
zTbezDkK*<LEX|`W7&7u}N71^(OBRpR7XcD(TXibCB2b9pv{m}D<}KzYR%HA6!~zd@
z_#ex~(gdY&4pJ-qEcNN^sfUaY^H)P7Qdl=s2EAMoL8{tTJ|T4AX)Hnv@({MGB6lbx
z0Y3tK#Y!2lK&sfh7~k;8iB7@D*pYG+wThVH?FdhU=m-s#P!zJD)juG&+BEVo)C^C+
zNv#t9RgN{5gr3o#;ep6ZDX{40l-i|84@(#DLl901`VgW;S`5y7@ca<tDPk&DW7<4p
zDq{i;YGPh|#H7*`wv6Zw597AuC?5E@Qv6nUuJRMOXhOReAQ@zo7|$;ym3p>8@jF55
zVsrwxe=e}J;TU>ADnQRLMaA=5rx4_T6H-!>21tmQw0&GmmE~cviZtZb>z<Hy0NB<e
zTcg>=F$HbFi@}g%s|_iFv^W-)ttC;E?PBYbc~B@t4LpNJsbj%FQJd2Xj?*GCY_)+#
zhn9~~Dhf0-1CAM5z)wD)!uD_*RjEsz&h;Q!3W1ojHTsJSotAOP{5nnDHI7V8kZgFB
z8FdI8vFfLDK(ZDTp_L*)PAYFfiZ*C6x1V2`VDytt3+L$ob;AB4`W^7>Z(#w}DUd1)
zHH?e-HAQ#O(}if1ET0xX6Wcp%*~%2l`DnZ+i0zmkiK`$XbFYGJOOeXd>5_E~i8!4)
zfX|g^HwNtvgD??FGqq7fY8cIeMCRkfNH#-QF94^RFo@VqH?}}NAuy#vOs)`xgn%3-
z!xh^qwdMJ3l@^ss55q0gT1x(at$}ZQg0#+?t~xSwvFAlydlaSc{*8v9WkUDb6Oe38
zBdc@C(g!4&RQ?@6A1u$JuDn|Zzi#{XEN!+<u~b$z1BG@g_^nP{LUA2m)#3iYZ$cxN
z_-8y&rAK3mQo+>OxROdIBcD!c1Fi(Nxihqm$SG{q%PSzZ){bZ37lmueqJ&Afl3x$-
zqDpkwbp!}!>!k;Yt-(P~2_F+FN9JVi08YrDCrULCY__s&HYHgP2=rQ!t&7tJ<H3Ii
zQW8l49$l_HLdPHPPMau^fxu7Q+qVH;xZ+SnQ>!NBdw$zMrwOGRRp6xVjNbx3FEJF-
z;1|K;atd~pn<Yj?=mWg)Ci$(?!mje~`I#6=;J~kURUUS!5Tl$<mMDW;r?53Z2?#D!
z=n++%JU`eD63J=IAqjfGuwyX^Y7B~)xiVfDh@}(?3ka?N*H+9N0fh(M1xEjr1*cYC
z*4(e+D8-M#0o`#=02kV6=7p(oiHoVNrZ?I}@(LNtOO^n!sJJw3YIB05fV07ilHk+=
z+L2uhoSFfV-!2N?TcK<_eP~;P5nm(Ke<-NhJs;x-jv_z`2r^y)t4TB9S)|R4pdxm$
zUh+E?q5?`G(%8V+$%fX{jFqInV(UerMm`=TWVjx9qXM!Sg(WJdNho<p`5^;jS1gEN
zwzDUC_B4h$pf03l%_oj0z+BeTAhY01h*L`uPYzC0q0xkq)x5M7C<jfRze;I}r!|o&
zZs^zy@8OJ5!IHT;NOhYmGw4o(+YhkNZ%T1Cozx<}SZ)Ize*M6`R2LvfM_mgSuM&0W
zh4$vj#JWbE9bQGSc($N})%EF=DMS~`0g-9*R%)15m~-+d8JzMs3nHoz5$N(<%C0nV
z7TWes-fgV{3a+73DH&L0$8|3HWp+zA4sX&|y{OS95o72hINalGO|eS@K@I_3TPbeg
zp(F&)Xi6c;yQ&1`i|t_idH`p%q=PBYoKu><6L>eWKAYKeIY1+N)kGIkckQA$@A8yG
zc9cuTs`ky<4fJdn&3dw<4?y^bLAw);KCKpXRoR1vSe-7}JkTxf#i@*bO@qloG+$4#
z+eN7<cQ08W6Vewm%L4+f&3Km{W&IJPUXTfiR^MFwhUIgwo?uveZ?d2H3EM#`DlMB_
z;_)|*0WH-Ihy{pO&Ycgs+x=S%mhKo>@kz?u>Km5?wwU~k)-Y|R2vhz)J5-cTri}rc
zYCSh#+3jju`hfJ$-j*i|nQxVMPb{Z5X;-ohO1)fOZmDTimR_KnHyY19Zs9+2ljQP`
zc;RC>^$n`N7WheNqwe6M+24N{CI|4j{~SJ)@IQAYw$Ao_?CM|ZL$wa6NIL_szFoUy
ztDl4V!lhg;%Bnr^)-~Q?dib_cJMYg?_d(Q}{Z!g=w-2N&%%?{`3tJsuOP;@rb)m0X
zx>~-Tdpum8x)%o$iO~z<wSM8Xw4M5@<so0QLoh!0Q<fZVU9P#O<>P;Y3eW#{zTwV{
z#Kt`?61=#Q^0D0?g6-$ev+$0~Eq`&s4$ZWZC41o$Y~yibMtMiAHn3}N(wO=4QIGJ!
zSTCBL`qp`A)fRS_ExrF6iL==&Z4bi@KIbOoR}l1&dYmkX7^Y?E4h1JC<K}s`a2obY
zZ;JGsB0*tGDJi%{bU08+CYL9eTwXMo4Hm!REuiaomx=rR><Q|T=IlLT)qZTq+e=p@
zncvMDg}f-HC_2*^-bM7BmH&ADki8I_c__8@i*bb#H($n^3@8%T7H%4)W`DI3w-;Z}
z*~*niq!#V?T=%p_UY7m0i$iksc{Z={fBx5xW423lbCJ|mDt%@ztAm3@Soo2eYmQvT
zp`S4yiZ3R#x{T;gT;p5UwFXu!Imepg|6gh+o9U!q;v%H0zaB@-y#%w7(bi~Ke)$6C
z(bwhnsi~yiGfFoEugf@FU=+!-_Ov!~R6)0erv2?i%Z`5EiZ2PDUSSb)ak6Tt^iFFY
zF7&((?5eV`ErrdVW9;p%4Tr*h<@}a4uCCZV0LE2nfAmp=GdP;0j`ohGR)tI;l(H65
zJL)O81=p`lvFUJa?2r`R6>>G|xz@L|<1_o8Ue$mXmq(-rpS<UCV;RC*Yfsf`ItB2;
zWE=J^+So~u{RKWBXfP58leAM;5qhuP<__t?rUw^SQ$K6VVI;HUx$~`9eh<35mLkvx
zG+kh%^euMXTmQix3uUcK9Ld}R%BrD_ST)}{_poiGl4LeD>P}-h0EgF4)4(%0b8#H$
zsrc!_wz0Q*dNW2I6?pZbn?#NN<RmmV3759oDb*w=Lh%TXCGAdVP5QN!XHPRy5A8xS
zEA;bW1cj9!#U65VklX~Biw+79Kyh%M=cv}E7LBt@EnI+S2Qh>oYf56Kcrqdgt0f`U
zW~RU{;KgB?ffDCYDRNz6^+Ru_qtanpm~Uz$X-8o2r;{SdOGGKba!r0pYJNf~R>iso
zZyjLn0a5_*HefjRV0AoawDO;jFlAmd=Br~+Rpq;%Q>-}A)oW?mHbr?XXm2}O-XOnj
zOI@@&R&mp!?$c2Qz)fRd+?H9Ybx^ASW-7)JT+=MbhEhW)v1GChkJ~K6=^~%3GuNJB
zI8AIvA#J!SiKUlMAK?AWdfCo=;&zPE7HG%t$d}>)OwU?9OpKAo-yQ^`&uK%g#f$hh
zGQ@j4J%EF@^uZu$U!>%X3(LHsq`uNYX+`jL>R}}h%L45RDmANmu0v$iB9}VaUk};V
zB6J6>Nrg_;e6nom6Y`tpraQGVEBscCqV2In2r}u$C(?G#i<$0QT8+Ur9JFnSmx8&A
z&JkpeUjw`+5m)x!0ErNbZWGIp`9Oh_*EX=wJ6~h0X${p9_y?W~(W@UrS8DO9*e2A)
z03E-{qpOu<+Z4YEVa@SVLlO81q^S<fSgT|0JOhn5_EuGS2J9t|t2Y$3f3|KuL)+q8
zBuG#8EQwZBq+{~7q(CoY9V9A6VwUH!jo6w3VlD><>fIuT@BwO+QgYIpbG!#U7&r*7
z8F)_!sfCDizp!Vjg2UiD`kifvT@M%vzW_$daUS|yx<^eDcYta6*UQ>s70$HPCwEL#
zj%W_kH+zNl!PZ)D0`VhgV>mMx_C*4AOffIbK4mR*$edKK%>lRYW7;Z6O0*dgRJ(_U
z`r<24_U~p{QmZZZH9gF3y&0u>2)&ngWuJSsoou;ZOn$pqvNL>F4sUPoY_}XZfc7!W
zI5FZTR$l2?q8`2m8Q$VjYX-7V$N2w$*4_ucva7o9UFX~*&5^7bpOH0Vd2sA4jckN*
z!u6l{GbIMLWZ4ME3D+<NmyqPn#F#1ZYli}<X#?yl%SM=?$i}2Yl9r2c=rDE2q@jHT
z@|t7g<W1<*9rB=c`^tNQ@~GodIv*ZQ9ZK>0{`R?7(#%NrisUWnp0od~z4uyc|6Tjv
zxoqZiR?>)sB)yqXJ}<Yy%H9@-b#C@zsvl${|8sjf$2e{zxqG3Z%cYS(5<}^!LhfZF
zuCRspoIQD|xBCB74@G&)UKwjiHwL6fH2h2~I~l%?_=Gd^Jz5F(=7ixOwwUbOFkGkk
z$F0DBq?2yEhQ_uz=d#DDY_0Y*qDE_b6t}%3MfOUDXVRcs(w1S(uiS(ZvTRB5{@e#!
zWY5Vft*DQ`zaxV_Nl*QDl1XjVjhji+?-g6=$Y(k5a%aWK(j{Nb`~c2J9bSdDv5B|Y
z6&3<-DQu|zlqE~a6?|0TISa0yq_x^5qi+1QEt_f1E=)Yx;6wmqE_~y{V(iE(3Oo4C
z0gmNt0o)H~Y`OJ2Zk+EX2LC;F;B^88y;sFAVe8iqiYM3vI{xm|X8GbtHv2}e08S5u
zj@c!P5~+X7TVT#KRU&p3ecy=}Zb}zq(RC;8OA8jhfMr@PeW0G~NZd0Yv;5ZMwJiNE
zMHA2!vI8HSUbdlMVS~{(FDUGS!!(jh3^L1Y9o|q|<59Q#S!e#t1$@ekV(?R;)hE4<
zH|e-iGk{WCuWj$*o|)pnw=P>e`KHJ7q!eRQ-(3ogPogagbzwEx>&TlcuAUt@a*$b!
zVsGG*Qg1u|`_8e}f&bm?2-SCDX;<3*Cl}hG>GxWy&&N!D3Cgbdw`tYl_oHv$!<L;c
zw}tGn&s*Mp?vBmzH8$uA#W%zZU43>6+>#o*Iov?*-fN*kSb7Y#l}l)&tt6?IMnP}R
zw^lgq*w0zEGQwc!cXr#@y;YP^OFTBr;Sb9B;OT(t5t@;!h<Bx1L_tkUsjbL)@Ow-|
zgl%@E%~7GZ08Th4`ZP3D!`c77lg#tRs4ubia?1TTcMLa<@m(L=f0@cN&`q{{>jb$>
z%TYY*vjwTG9&I_9G#5ukrTW=vJ3SoUln4KDX9K6KoLr$OCda+v=?lTH<R?>-8$Wi;
z*%N=OZ-CwiO|9}XVv<xe$+g_gwHVCD=lTcIosvCt#Oykrt_qhSrRd*r-uRVk!XeK{
zPV1FE)1HwmqIx|mBN(Jnpcn=@Qh6c-$4eF`G;JdE9RId(C$=qvN^)f3N~z3o_h6WC
zq@43egH=rxuP#7Inc9)1X<I2~@twy5w_u-O<|K94P<&@fVwjmTXDVcA!m+JSQuG(_
z?FRt_rgtne3dj-Kik+=~L3;QPq;vI19~zUYcGI$Kc^!VI%tko|+(%PZIoJ8yN(?5!
z=Yd8!ILlzCA0&RK6g+|CW49841WgPTB)(ExnX-|CTg}vnQjdj@>QQ}ugOF*nyChSE
z@AdR(xhKceQw$O=n*o<yGvotHCMsR50ym||R-nO!2&f=*3=LUDu|SIq#RvWrwN+~f
zON1P0a2u$XKy&j#=?{reqyk4&qINO_$ofkFk&N2{0mX$EovJ~bLnczYz<%d=Jx68t
zl(PaVGS~Ir{2i0+Xi|d~K#VoSw2`TEc#Y00V2^Rsbz-Z6tX91P<bpzukPq!v;<m<r
zAZ6zJJi|U?AQs?V(;$;t9<0yd7!FqPPgSqAr&s>cs1lB(Vr~Cp*~q-nd1CbkYUcd7
zoXAUO-s5OPPDZ))gDZ%12vYoQHXjrw!-2qm8E`2rQAmkxHGJ>7)>QVdff_)8N4`Pt
z&W~3wa3pBq{tk*$K?vP^t8y8ygr%8?M=KqtJY-n|+HKnIDp|&`F06TNZVD-WZ7aJo
z3H5|dgOJ0Xg3Yf3j-27Q4yc6!k+2w==8J}e4j?-p>jdV2Q@F3B1!AJv^GBC9%+xvW
z{y-gJDUj$pzd1_C*&MINfw22RTD}6D$DyelU?4HsE5L~#w*d_`QXy5VtxRfnA+J-D
z&b+p3?emVB>KCcp`<2NzDu-C!qKOZ=H#?PO7FS!ZL+jTJVOMRna&N>G4G(Fw)bOr0
zMOHBm+6u5ND_x)6eLHQO>Au?vvg4l;*_qmcq^P^`8s_%7RyVd--ts50dabrDEf8RM
z&L^w}+Gm+UUfNExb6K|E!h`fHW7B3&?=bENEG#@4(BZa+innfjo4t?Cr-Sx8Vc6~%
z*q@BBF|!K_F4DXlprAh#=4_UZy8fBL;qY~+IrYCeLq1+X6$4C@;ec|lc`Df{{n0BC
zliGUV1&#Hv$mPzvd3^WsG0&?vNR$h&$n3;{fl!u2G4gkp+eG3ypr4AKc+H1aTNnRY
zn4I!pu-Y1D=(Jd;V^OYX@3rOf)wVdcH`o=&w<0=l(4e@42i|motNGmC)Vs{C{(ay6
zXLrtoij!Y;W{*wVG_SaGBdEcie}KT({-U?~F-uB{!`R4;)cZFLF=pB`F>?up`P<Lc
z8vf@lx8ZBPX{`m_Co(df9BRI6NZocHpy_G8F=1iwWj6h|u6{~pS5Kk`g_Zc7#<P&o
zl0#1zhH@#~OMD~MFAb*-9ncX%zlurTUY3~09DsbJ4!zR(2H|aF^tZKi0!mEwi^*_a
zi&?G^JwW|;GVFcsYr)?zWa;ZFEzKQAbB3NGO7b(H#TEW?o!VNr3(H7y{I&+lVR6f7
z7;ikBMsj<ksm9lCjm4C^i%VDt6H6_cz9hNj8J9fsT*XOt<X_BGy9pyI+76vJ0=aH1
zDLx2U^M5C?Lt1TpVBFg!rxUO1Q(LI5&QVrBaR0E~y!}~w$(K%El-T6UbG!Cy3y<~9
zRwzrZ38_~RcaOi^6%*q~c{5np%wwIq*FNL6e=|<sxriQ0^L3lRbokGXMa~3oN`f89
zILLO~MP$#j;V*;!tk7wx{*a?OhQoJe7T(HIN@KvsAa^(#cP1iaNgoXOZVMQxpesri
z@Fn5~C2o6(H?QSc_UMe8tw--IJs7e^7W|8ehr|xEZfs3uqgo6K6B}<ju%B*Q5Z=oB
zB$dE^j^VS^R=a}ZS+C58C6EGwJXmh@*%ytENNp8m*Y1BSMd`R<>kqE1PtGUevOS+<
zrN*C|f!oaEY<G`UzX+l8-r(hhMGH-zQe*)F#AUh;F-&N{s=~b$VBZc??7oZI88S_;
zqs2&L3I9@2PDVt>WDc&LbiI!*5HLYlGU`VFt-qwS@!VEXqTMKw(AdXwnYfGl#hZY*
z*8vyb8F>zc01+@HT?P$(cUDf(Jq8MwGSxwo;|sM*uH(`3<w<w}3|K83)O1PMAdo}s
zy@9}W#6~2;$`Nb!LigIj#eT^Ux>#qkJxFEOm50jh-cThQ?<$Jf;XCNczOGJcBY_hb
zm51v_8L~lNp~R#|Yz74F=xhe~=mQKSCORl(ryMLcQJCo1;#om|R(KH>_cN|@g*_-i
z1LJ12icRTbYX6Jjw(#~bHL<{95J$!|$)mtxz?8RspdpTCSH^7{hKA7R_1FaZ$`{%$
zA#5qJ4F=s_qvEv+Vb!$GkWH_%ScT%Dh-RbBr6=jxdA%NYy_tz!tOei42(frZztl^O
z7CqxL3=3fu@qop|JS~A>cZ~-qUjGw9f$;l5nT*CQJt)6Uh<j3>Eu=oZwi7C43L%YV
z;&qX}j*qFl37DzydaI(xl2O=p=qG)#Ul9*AaajHsfkH@%IidCi3QR-ExLHL;TsUk7
z6_K0yM&USo)l{eis4y;^g`KRo;p=0J6;m`fV{|vGX-p#uPaIS0!)$2w(bb7?eqmLB
zMCC*Di{z}D>d};Rlhs?~0%hDQ7>CG}L$4=7t01fvJvSC?S{!u81KoFp*sfk=6DfLD
zTPJYH8a!~wXoM}`>Y!{cw#`S$$Gh=0O<gRRUFk%r^1C-c8ES=ZgY~H9W~Yf*#oN3d
z=K^W>2DPcIwkGzC2h5&gu_^qNW->Ph<pLc#LWRx{p3rLR_XbQtG1Ewvi&#QaEz+v|
zqSyJ47*nIgd1Q9iKO*cusIuvpBD*YWT0LWGnu*@z4>-q`{0y$+F;aT78dc>N%-Q~g
zCD7~famC&CKx=X{vcaezblzE^QRcn;rvH9MM6XM3j3o@Ferz%dvqC(oY$Nyd$RFc=
zFMm6P|1gv_KS1NJoNMz5-jg3jK}BjwNmJ_o?<_D{N++9F`jO=KhK#){3ssw<Xf}Z$
z_cWQ`#!$2oetxo%)-Q56B~TYjkV=1*#g(+N^#e9+HkO|a7EW(xitcwKy4O=Nh_S#g
zGUsIYakdhZNQi2yYqzRmFi*DnyVJC|_8oaW2(LGUD|HgI{xD;{MJ6<)FafKpt@S0Y
zJSyLB*R$H1Ihw{WfI1O*Tj3I)^yB8ozM`#uQ_d&^zD-td2^?7ABR9M0{0D_K|0U`a
zTNnmduZ<p8To|eh&Op-|A%Zo{bk*nobc)7)e_)evuy9~-C_H{uXu8JEkRL!LoGvqe
zTXT0hzin3-F20q9#rifsedNXvuK)f_AhQ0@o<e(SecbH%|0S4K^(13Kd`5y~gP<*e
zi|fSiK&C51MIJkX=@(--tCSSz{7;Q+%X1}SFCVd?(=UvzC40pSH`%cP6u~W}{nw|d
z1BWg3RGaM4mn%lD>tQqN&V96BCv9qG|2FnHv0&K<ua299edG;c-~T_^#qpaYEs}jo
z|IGJOVg&sj+$=;HE-z2p6r|$d|C5Ab#){+nQ~TU=wh##Zs1ni4b}Z3P?4V-DWW%m@
z{)s(kbqBMeS?sl$gBRD@<EQBc9vLjO+8U<nNx1&MUYL&Lf4<;O{#k8#{MGN}y67LC
zHCQ3ujUl`|a4?HfcB_hb^D{cv@RtUN&S}-!I{L7>DR=YO-i>bY?i~yp1>@`pYW?9l
z<nmSNZOok|nOo<$p;3+CrQS;a553*bWQ|2VkRihztb`m(Cz#!!`uzGF10|u77g~q(
z81<bKrWh}$?@-cbShmZ?l9zZNDx!q38656-WM?KYUC7w(ur47o*Lb5nU`_5A#2j&|
zCnen;==O_uSW-Oy`qUN2vZB=(m?=(kuXgws#kC{*x6d??VW2--w)U<5WN{fI>*uK!
z;ll7{*7swSJs+a1Jlwh_^#iS0%?Y&L+Y7(h%M-s)`6mqT98JK+u)ZFo#urko)8J9v
zfW3M+enF+2O~PbC9{>{wss);8<iGQffmr0>`1zPL?Lp2!h9M_T0hX&5Pe`8dN;RW|
zv~lPS;<Cb+@+6_ilYAtjJWL17RC?mqV?B6fJjsS6@SZJfC198xQMacohsJaUNg%^$
z&l9K`XLd7LqRQkYC|!BUxG@kmWy=wsyESwYi<?Wa+&GSNT<eNP%;+=K&2w_a<BkM6
zAU5{c0z|Arv(k2^a0piFOQ_`f^s4vf25G0Xxb&9+*>vzoswt1f#EBkkbe;&XI8E~>
z@Z_L*?IUKp4ILzsV}O>CHS3A0a5s9+$dOLsDFTv!pFAAolIMf)CP|Q52Ue=LcouJQ
ziug)%SRB?Sa-lr<Np?-o2Bv3-!n;KVM>J@4;b)&fm@~s^@cRkV4+029gW*PYn!pcc
z#+YnV=*#P{g^s{rHWDj-BLtocw297`EF*8Fz5w_-7ey``97J>!`flDNt1(1`4Ikj}
zIp438v|CdW!8Kgcv97fUOe<PYvYkP-K0lgxqDobW2|)hxfHEOum_+3kASh*icOkzb
z?)sf2W&(DYHg{05T*Gex=c$q4rsUxDP?D@K+kz}w>Iq5RK~A<h*BEeiksM}bb`nfq
z6x;%IupFpL#PjO`x}&Byg!SG*GV`$&kaH4RYUUDk`K7EwHm?ua4=h1@r+<YBBrX`G
z{f)3Tom$y9dTK@$0CjBMf_TyAfYv~~p)C|XCI3>JSNb8S0y_*Dp(Q)O7jI5%jLdQh
z(ib9$9yETwR2(uWsI*32)O_X-RSyL|K1Hh}b4<3(f_LTvM!A_Vz1q!X*~FJqB9hr>
z<*UG_`1J<oBI5Z-?em?;iB2cDkzaH}m-qGyxs$~;N1#_^bm8Z`4U~(_er>ly;ir<+
zZhwuxX+8_Lg^N3RkYAEqvsdWJEfYLzu=rKp{gUN721R)}CH+Q<#p%?XHHT8AToOZs
zHc>WyGBN*2#Jq$ALmn2>23cIcsBrcRi5o;%`S_01t(>qa=G+ls9|-v8D{5DOo1U7m
zEG8HG%u1@|h}|CbSqP&OoiQot$}j3@%~iC0o>rkvTJ6s->vo=u_G5h6Up7<FfW~q#
z9SK={ncWpqi{`$gjd0syLqsL}emSeY?<1Rqsu7W3M6>4?BaD&CvKbsAh*sh#c*V)L
z|02tbPN>1_xj+i1zmc%a@*xY~<8-9^W-S~2r9DZ0@+LS&-ZpWnCYdruc!!Oatq-%)
zl<L<P;Jo(T_nBY*`un{;s+a9(nj;kY3Ih;QZk(R5e}8D8u*awE)6G)@rA=IA+0|uH
zDRhwRQ4Z5G$%?7W%~{h1RL%NAm^jlydUTXW-pf}lSD5c$NUe~LjIskiQ7jIz+UmKh
zwa_O$!k1aNM5He2krL-e{zH+3M{jT?o0bYkkDM}+a6@bo_RuflW8MAA^0tZAsU|Y(
z)M|om4uNF`CmKF>fqNav`I!n=2`Y0dVLKTTJ^Fzto?tx9n=eLOY|YUjuP{!Jmu$EE
zul>KwnY5wqjk}=lhhWt&rlEQzf>fF(7N{pT(gE*B+i2P~ZTrMkK5Z#<FHmy-@?|9Z
ztFZ7uEl67y@V&>1@SIVG{|_}yS@Ai8Z?r<Ij-r!Mzg?T<hGbtmhHbW~58K#euSNI1
z5WtA5^TLc-d4}W)r!{%%Bkd@O{2Og|ZeH-F5btU&f0JIQi%OA;l5+l+Xmxk9d*Q^B
zSK1O^yS2HyoUNSR?wwGE?sVxdpRA1*=|!3U!lQ1nJ9@!yV+aq_i~85j&B2Xvx8gbg
zoyCufZs55oy1Kn<?eL-7`B2wyz;k<yj^%$vlYEs0JNXtaqoO1TZuXkLyG+Kb1}Nh&
z)gEMjl^l8j$=WkF@wg29FA`~!n_Lv&Zav6RmO<L~otorr1MV97D%LdP$?94oK#cZN
zUuI)r?z-iaMV4m5&KOCwC(zCXA$F$+M%3Pp`!L-JHJu$zoKER-Xhq+Vy^$XM>29>3
zc7d;M&??zA6P$0wt#Q9)4obuI$&4hqpXueXK#7@r>L-03{%$u|k9R}u<yA8hi|@-u
zk9fLX(<#yTDAE$bV0;Z=&&^N;Pe8JVOW&pp1m?6`s%+~^VD2D@emqEI&JkfhaKx#;
zNbd^ZD}uQ44n1Q%E!i@zN>#s@febT)fqS22Odl^*mgw2{A<;*WAyh`2?7X#S*sDFC
zf3WJuDrFSJ)nLM`$PV=QSf&^(LNS;WHi0h!M0%P4CRT!I?*o3xkoH+A^a?TE%Ts=k
zAvMv-oRDQ5a9smh3m=&XE}La+lUUOalNs)I^Bu-;J(5bi5h%PdbK;{L#YXQ@k87%Z
z+ej<iM0C1UE`kIT@Zc+C^nlm`2^Jb^0!Q`89D^1}u98A^%^dAvmmpzm4n@tJCnZPj
z8Hp78(pL-H>0um6SRq!=-&p0OqPLN>Q^JP1oeHSfPJ@N;e8fd&VQjnA25A-21aDRU
zzTm7G`XWUHP0sd)039p>BRncX8X^lUD0U&iC61DVO%c~r<&HA3#%fH#*(|(~>q3Z;
zRhXMS15%N|$_|2eeE9%S4D@9hNr%8o0=<QX6Au|Bw=S%jf^;Jwb9(j!7$Yu;d4Mn5
z!4M)REtP#QQ<Q%sUktV)YKR`|A0EE|MIGTv+xJ2x;2e)+8O}n=sPlTdw0IN9bo5^z
z$GPV5mRv$~Zg$?$veCmSsh&Xc#O7mfQ)uUa=vylbaVZlgFNr5=dnYO7^m=IY0ZgD?
zag<@4rs_dcc%pCV3<yTy&Voz|pRaPKDp}5)vUZGXY-5z`xluQ6sQk5pwuaQl3z4uz
z@D9Y3n>$Q&wAaT=dJ&S><0|oZSxbJQ<8!3b6PUgR5n(Alq2Jn^<q5Lo7DT+ATob08
zHv=w@S?85@;$7#o-nbrhz5ANkA)N9h98tq5Kg{y!6IVpf7}7mVQC?b1-10UbAd~YX
z_h&D%tI~%3cVES!%UJUERmkYx%<bCG7QVXcpQ<Xhu_(iZ9|6NQ;#yI`@tN&r8-zp|
zMa|gTNvuI}UI?#qmW-8X9dVF$#^L>WOI8k3<Q|wI2l|0fR$3@5&)e0$#8TFhM%!T^
zotS|aGO)foZKdItccQiq*s#;uU%V~!CZPdK)a1kL#0Vo?M1tL&NLw`Rh~VUlXk@-t
zvG4rAQ0}g>1r5*i>kVo8Cn6592(qrBvdUE{d65ZP(m|_yH+rgRo#jFm(Zbo*RQD_q
z8u<Y)8VYv$kIfeUh~u}rKbu;+1d;uc;Wb(`Ld^cr{jbihxj&!td|}a*T)~rka*tQo
z-at@$lIl=APv^=JR@>pS37UXI+{L3FAzXX9ut!?AkjR-NxCW)Jbve8pB*~S%jI+?D
z6!w|ffoyirwf5b8wjef6-Q&#FKfc}C;cevJS>oCzF^QARk*ap7zCpWG?boiiosMOm
z@DP6a53($-SqiuQq<uZyfa}QQyg{?My+5I5#u{@^pm{xgdEx1CZSmg>SR<P(Mje*E
z;1_)1;4N}7(hQh7K*j_aNsv4Rl%@Lh1dlIj>rmcgN92i@n!id@=$#mT?xMx2l(cGv
zZM(E>^#ukk<u*$mdwH-yF<C6$R}EwS`Excpy^H11kFnWKG4uoviJ#t+wEyG`qb1gh
z^N!kjWtmjVC{kN*+t1YE4e+%uh_^AW*lC)zZQCQE#x8YK-nn}$ZPo7E$sG&9;kN})
z`E3c0k`ix#a*zurT87PafVPy{I#{dJR#)CL8aF-00ftGOcT#KpThlc8)Sd=)0?H2j
zA{)4>f?=b{o@E=q!^+ZLO3mV1FZE{&ud3D?3YRxN!-@e|`DzYIkQ)WXxetuceW11;
zF9Kh&I7O|cIhn4)<n}m|t(eE`ImYeoGW(lJLTk7p<`|(yG&d=k0PWEQp5Df}nkvYl
zC#a{~pM*51{XNC6IauL0DJhuH`_iV(U7+t}11mG%Wg?o{|I$5}I*$wDry*{HFS2Gj
zGExk#oJjgNO^Qk&xe0VA!?H9)3y%<aD@EKpE49_x(=Ill`{WJd-pVA5*<?D!cN;q4
z8cB>WW<Wt-f2w%V^7z0>FU2QK!;Ln&QQmX{SFciv-b>f=uwFU4vygsNOR$DDO>uM?
zUX4Knc^XVP44*bXA7n!E;$09LG0YWI`WY^BU@P<nu|&-CACi;Kw+4B2lAf_NBDy$S
zk<sy!1T}7r!=fSwg`u>|PcsE6A2$zLU)h0K0m;VZv$83M)#SOxUks}>19{-#p-k`U
z;kp$_jCMg0MmiOG4r59fj7;0mAZL$t%4`??{CBX4+i(p8vl!X=C_k!;)K*}Mv0KzF
z&I=#qHAhB9yaGyN>!VsFW}^2ZQcnlHG0@l|VJeUzsk?~Z<Oz5NEGE`M;=3gWc2g_@
zd`PTxWbSSsT{zncQHz9f$(FM<mdMEJpwFt3(#cje4W$aLw``}?Ts32&l)N4taC#&B
z&ip-_p<*!*-EEqxz*`Mzo40xtAGSbQI)!dG0rnQ9r?`7UJvMV>&jye#FcN^m(%KH;
zL2AMrffk9gkxmIbY?)|@a;X`8@WwGkl=Tm-7Za}qXWqrtP5CmU)k_}IUVPA7d#UwS
zo_hHOS=K|F+1y3w+!}N!uLh{DirOit6rQPrGC9j)UL+&In=k^utN2BrE(Z)(S2jw?
z?BPxxXMCmS6LN-_@UTiQ&6ueh?+tAlhQztvNUOfFT&~(SHuxmW(tT*w%Lh=>w9^6!
zJ!roKBi~#;i@RgZ^n=iut+tWOj)8|HmKi0oW5aAl>R><c2}M}~n-QiA5$b72=*~;C
z5b%_I5Y;Lc7KIn=WFJ&m?@>ATdiwRAL6wu}^qABm(}OHtYq>fuk@;zP$sf@sP2N6*
zK+g3|E~_yQNr<(Sv&TMaYDBlM8y^2np%fKcsMS>jTZu6oV%F-5lqh;CF4n9#B)D^<
z!3Mt1@AMm;*{?7nRDTkF##{1zS21V*V`rM4F#>8g5w9`3-ZHTJK^P>ZAv@!Ia*SYH
z`Qu}dRupTLP14w<rr4a$QRr-INbe4$FN@X|&amF{&hb`uU?shaCL|6ZaqbBo$+<O*
zI;(2ksWV(BNhIzb_U->c-W^T2%XX+!rb?P3Je}?5`Pk&*Qn+>|(rW&-GnU+u&Esxm
z@!%wD7@18puY4$DRpIajD>Jzh$-N=?<gUo(IcN>+kW$qr`Sp)VSimfY+{Qzmg-56;
zbJ}czZXu5sW3Rtp>Cr!D+?l<L#dJ0^JltYhVEk9jN1mErL-Bhz?dkYQ$9(Z#`o^&o
zzy6S4`>RoH^$QerTl{?=2;;{tD5fDiD~>sP;*mk8L>AoeeJCYN6vT6n?O8@7ucA+U
zet>Q^V}AIPo*Ht0<i20Jev)z_%s7njM=w}Zu8|1&MFZSIgU)|I{TsY~F>VrGjA|=h
z@g^uJ^Nr(08rp-|gWr5Nhhp)uFS1(wn{Nme*R$8Ni}CnS`ryF}%`g5w<?|T^`%ZYh
zAWMfnQQWkegMKC=`$$@lxl3ZjB@Fb11L%O4zCAqQ|266V?FS;h8&2%HpJRvqA>ZPg
zdMU?bevEP5u`I5(7LUIdESR+4_|rijK00Vm#VeWqkPP~>4`<_BX-w*0=4!II+Iqt!
z{(#h0XpPqdi{|b7Q{Q}!`}zm3No^nNUP~p?(e_#G$Sxq+kKE#s<c?(a;=|e1M}z9!
z7GU{!ng!tv-e@y%cQ*s<5B^v+cc){jx)Zt3>Tk}a!*=qXYokarQC1UWN4X`)?-?$N
zH;hd*PP8Z>?q~Bqk<{yL)a>8+32)PX$68-1x8=7#{k}LU??ZpmLSFxJZ7vW^HwTw7
zD!~mvsr7?#S|Tgo4cc30`4Z$*?6m?-Dr#%Y9}Q#jm)efTp=3H?hU_i&x??-qF2)<U
zFV{ZnEGy}2?2aqAhy6v?_R+7;<3_bwYE0kCui5EQ@2vtk|BIO)XipxU&Wy}UU~dJ5
zhDF{Fq<4cNlIv$eu4OSDVa%O({Y6K>&|=&}R}zwZUp}J6-Aim|T3!}Bo@#c3gA=x2
zYIEF;w9ijRciO-XWg~tr9}853DVl66<=f`lX}qqn_u!IVkc@?$juZKdu6Ea}qcG1J
z6DY(6Koh`8<qbUkQclQh0Gb(G``d|NMUkv83ywnw$ZK2JWzOTL2CNADEDno=+TaJc
z{Bg!FIB4Z@3s9v}p$59<%7j5-NphOk6N-BxF#2H8Yr%Cq6AVIYLJRv##+jsb=BGO=
zclh-Kico-H1#h`*5{B#DAX$sj6MN}p2u#{t_w{dxi=TvC0wYw7mWsdUH;|zha6f>S
zXg`2`T!Rt%3_bgR?~F_PphfSAen=#EeH5XGxk%;N*{blmujd;1Pt=-P#j`19JFCUJ
zjABZ-Ar;#Y22oqtz?UJh{t%O+AyD>(+g9-_U2q|B8iWhbOl#hC<mTlfi$dGP9H$l?
z1&OZ6+tvVrRaV@XIrk_AuGPD?+0kaGx#r00K#3uV8Z^Ld7x1Wn5><iYHI<H6b2VZ2
zU=UT=9FLtTkCI=6xsHC;wQux}d*Ih^OxOsi>n3URgv5Lmmv+qsn-gJGAZGS3%ie*4
zmJ1`2<T;f!<-C+Qy%=`!b7@oPp>Lv~N?^%QDRlm#+Db49%<+R59H~?e1sQvE)Z0Xp
zKvMwGxk_vTwSQIG5n+=@5b-(-4HQit%f#Y%cOe|a)VziV<Ag4^GOa>vR~%N_&7__L
zOz9yuS1HaZX19Z<=Bhz(I0T~a(u}nSEQ+!&5d5zM^iCFLOXVM8@#BiSBOme^B4g|{
z)E!9M=4abdTO$<aLZrH~hv?}1dI~GV^Pk{+L#~vTcx#K2b=X%6g~;#_)*P$W64Xvq
zaC1^=Ie0h0p#BZTpq1}dp1PM>|0GGlULV4VlhNpfp`;=1`i2hAi`3<&$F&L%k-mws
zyIFcDaD5(aSu^vA?NOs94*S5oaid!Wz7HziQ(f|UpcY{o+K*8_)SHxbBVLXQu(s?v
zy;auS=5pVH55|kL<=<RjTP)Iupb<s=CLZ@{o-Ir3e$f}{7Lpxn4kEEL<Q>V5pteRR
zX(NFmw4F^iDd=H$>oIl}v9oWawUqj{MoY-8?xnVp<PDyY4HG8m#a*f6+6z{a#E!8|
z*8dkS<16=?Zx%bbuDDJZ;#Ggbl}vXgf8bnqwRJT%!~-nRCl^Ur43EzHgiXRl;A2nz
z9&W0^bEf!>v^8+%LgV-=8G3Cf*kPT#bT)?U{a|xkMDXXK$(_h7`jAS%+!xYWF6%w<
znME!%Bm6tZ(?CE!iTO&h8nK6P&E;uv+eAvI)>?k#0Nd&h-G(<@j@EyJ_&+w}Q1<ev
zm0~bYC-r^Kt-wE~Ka~m*7875fR49~|QYD_OI8BADk0qm@LJd6V@JoKeQZ{a9vqxFg
z*~SD&@%#+ubh30-TF>FBq_veqN2RBPFaJd0w?ChgT+R7lDO-ZgK?$E+L4ZGiG2%p}
znL)dyoOMO20c~1;%#wwtRm>;}+9d35;={K&hv__le>&a6=BRH6Tl%vHtTr;87R~P^
zvv~A}sZ)%%A_3s~b@)MMXcCE4<1ryaA8->4`G-Jy;szF7AH96QVRpZ4`SO2E%-#8R
zHX{GUFPXo!-nQk3T3>pCO~PYGUd71<n6y2wK}u)7!eqrOZ4^B-xKF>#VoQ!^PbmLM
z;sbXfn}3@2fB5jcupb+JaYcB3Fc0_KdU0m&xKbI2$cvw}KPK~?RL$^JW<+vtX|qU^
zbX%R)BQRFm0?^P9mwvl%^hs1(v51qnd$`oJ3#H_oO~RcM%~9y%cZ777O~SPY{~>|c
z8XhJtY^A4Ofy`EFnGJl%(&=AekI6yyFb$4p`RKQZd@E4@@=^#wT+KmQRHV*<Fe{9H
zFtl&`lmp30e@q{*MNO;xX;?i&676x%nR=#!91bfZlqS^HMtNZsYY0<#KcJphF7NWo
z!_VGiIBfw&F3PHFmELNJi@cDdJ3DO9Fq$1_7H3~ApG%naWk}?u8@srV_}L2(@o8^i
z2fK;#Y3G_gQQq{0Re?C}W9jZmo{quP4XnUl<fOAnm@Dp-=NER!6P`q$U7I;_kUsM&
zipifkTo1L)zk4zy&5tl<x@0m-97~35O<kaSQBmp-;pIs<2g_A?e2(iD<LjVx%S8g~
z#3!Xa54YP2ZyTUC#|g_>&MD8rdo_z4(}U<px5TQ<n2N4jc;uc&K6qi0wsb|z56K!K
zr0f6_lz56b9hozNNc8!PH?^O(bDjZH{;!#f#dT}ogeG);Gk3`XOj^(@chfkln6@DY
zk^rTrUjz(dbT;}i%JEnyx!T6z7+y1<vdMyIRmLs~j6^0%+>i0=2aQj4H^3>;4l|wC
zxnZ5!);^HbD}>;oc#7gt5O2kg&58rhPh7=p)woFD<5NRr;VxL{bU@NFmL>jvaOVxo
z1Bb+Q@oqb(xp6vr8muY*)M-Q`S|VXV23k{>LRYmifP<^FT>13@hkug*OTuHCCBEQ9
z_l-uz7*E-psaN&lmgPZcsnT}zr7Df~Wysg$Qs%KZ{jTOg3;|o+1$qjVj*!s$;n5$M
z#97sDLwXjzlPzWeZ@-#5a@_=$iNGs}A|gv5rh=T8FDzU2C?)sId-K7vkR;8j$;b;I
zxeCdcqopR0((eZ(tKgm3GtfJslx&a+_&V~kSj1T#Dp5`g>}m}(U*Uz9R<0GvilZ;Q
z1dPa-l8zBO1Wz;xuE+3njzkiv8hq%{GV;u0#^TURNmdp{j$KJfI|N#37H2W=NIWsG
zM`64mlzt$}JSn({2!|rG17gj|jQ@IfIc)+isrb}u*n80nmsJeYyuB<EXoE3QkeAAB
zTdS(8g&+%-w8agbjZIfUK<Wh~OYF#iWEE+{hD5Us;Bqn~X!AsOEe^}cOR8kEpk$Q@
zuG4Vn6=2xqgq;CJZFoN@cUw?<KIXmRB4^t%NP{{2AXDa*XT;Rt0V?JYaDl|cRU-9j
zu0*oN&VhlO-Q`VROJQ=^d2t10K|PozSjl(c_6LN^cdu*=Q95CZxh}8>LRScE<F`+S
zzVNf!ZIeNX7bPe<oe+vaB$kSQH>sSUxQ0rkY%A4F_+g<AG_>C%<6sjl$OR!M&{p_h
zru<IxRti_MrY8`hV1Sh7X#nxaW3p{z7|86wF&khg?l|V-)yd}G)840}p_Y>cA*3-k
z6h#jx%@h}_X<`BPhRTF{W=Q=g9t4~+>T6QBow$@CBW=lGg<rDGvo?UCOd6I#zSs{4
zx=8m~T9k<`+Kyn^KFga}ti}>Xe#U6pwpFEo5ItZ8VG!5gr8eLQu899i(3#o@iUc;!
zg5oUOdW&CgAp_RI=7H8BQ4-c*eX`2tjbl(EUV*wOK^BE|GN|<RhYCwIOXK@eanaTa
zntCLdQJboCVw_4$E^Ap6WD&UdJoh2u!?})Iuy^P`OO#s()*nS2R1mrb=enl#Z&6-`
zu1jqZQyi{%@s7w68k2rd^=ut1Ix%|AdXQD0lyK{Y*&P&KOI_n61}96D!H+D6H9o6&
zVymX&5%@(2op&rjtI4WS5d`51yyNjGKlS_}U|8T6q183~NN;-R$XJ;qtKnk#msNav
zIg?m_sD}hZ#H#Yjx0f(RL3st0xl{ZSEE>h*zB3(6#^fRXoUoOW`baMq{rW=PNH)<I
zF`Sa^WRY3G9S_Y<J1p3)pJIsUiBO3YIPp&+kmY31lwBOmh|a!1p>v8z<Mlczg-!@D
z;bczn;6I6z(B9)Rl<^4s1foF@;*(cf2GKuFY~F;c9}x7A*~!osL|G?f%mA+tk&^R+
zM!)l&&vQv{=hG$DEsl(d92}ek4S_k`yIS)i+6Kc6jv1NXg+VWgFw#c@aU;QD2%9yd
z-7wX=31U)f$}$n2)C<V?i=Y(784#5*&w?0?pwt9$70E%F?rYTcai0dc_XXl-#4hkg
zv5MuXgo9L0b$$*GvX&KX?UW1po=Z2)fNuohdeIlDx*kRr5=y&byE;Y~y(6ln@&&ms
zphe9pzC0w(y9(V`uXCTBZLH@ypKDJY%-Ss$qQ2ktEe5!;ecId<WAC`78xN;}-4KRG
z7Yo+ml3!_z9r+ZhMFFjOZ*CfP_^pdbm_crAJVO`&BT<|fK}eNe2ZOfkAjZ!yogkqH
zBU{(`Z*FXMyykgVaVGZ7vkH@3OFXkChO@vWP=-qeO2PTP5Y^1n)Yh+1TX7AGM0+K2
zE1qHmJPc*y3k~k@*-AD9hOKe$8=^E?tH{(@$*;3ONPqZo<X7BpV~x?UitH$=cF!c=
zvad~Mc7SnS#@OO8yP4b<AomZulGs<XiS}`DXI?`dTrt(~@1Yi~M$^L(Sg{_{))l9z
zq*GO$@HSfsJEXxpm*m;Q8Egi}?WKxqC*9A5sEO~ZWm!5pz-nyHHyi^gs#Wd}bT!;f
zXn)|s@aJn`xE#@1lN)^ICS@~l9r?DBcnjazPR1}A4O5ke<CR6e8XvIj%MW7x(gWHF
z0vxLi+okL;;nd&~*Wo2&U%KcaUo5da&u3C>Zr4`E8blMWuursK&@R?-bBebMO2x^d
z^btP!-yf!z-oU!o30T<snziQhL&TMT!<+v+E3TsjC6k6WTnm$nzw6EY&V)9OQmlWI
zooiE96^UD-xt^hbEWNjXlEMf-e@&7!?&c<rhhe01n@7R^;w%#0p0oq6f0K8YLQ~M5
z?Ch2F{|K7T1*X}__vKUQJl;OI)5S%gmR;|+lCIYlG_B5zooGxfa;b|%G<WB>%?E<l
z_<%><o!J>|{B+U?<%em)Mp=Tyt1HsXe>%;R*^h>Q|L}jZ5FpNOd6gZ0OFlGv|Ceud
zmt6Ypops;dW&@LZxb<yu$hW?-t4+b|3t9O3hus68dR1D~J(X2C*aZbwp$&4#)WNU!
zmE%Tm&qpkEZyrdpf5!;v86Q!?1B4v;DfO&CTrN4B`O-7vU;9N8c^+4ZzbU*Y{||<)
zxRkqok|`Cc?p9K@KOQCc-PG0=YXn-z0d&iX2xmtotG!<y&g|63Osi+Ku^fVwb{N8r
zg>=x_*xSc<k>S(H{4{OxN`23k61AVvU9NAq%v=4>Ez`+AL8k`z+u3c{ri3-C{g5P^
zvVK%89)hNxAT%eK==u<g_T!BV?V7s&$z4bV@1qbuc%*KvyM8@!qxWCNT*R-^ik+!3
zK<NwN?RWWYbL1Gw@C$td^hG#4$OPR3S+IX}4XShp{YlFjo~a5T41T}n+Wr;X1fp4!
z^4Fm9#txc&kzR$#f8CkIA#6luZ5N5_B5e9T^b(|b9Yvrd)6^mZX=fpsE;qOQ*ywV)
zqC4QuAbGWjaYXD%J|AscC<B_s&xT<R&5aG{oaPq5#j|;~jW|9POzSlSQ?6Ff9K>=R
zJg^^fEUsVet0Czd<5;RA^PPKjzML$k7Fgo#ipFoL`v=&xxIfGnMRLdJoSnR=xSCk@
zg%ejgO?31FpM8HFA-%CfZ|_y#W0)i^py~Cj%#1fHxD=M0dAYO4Xz5W+7GqPPa=hx5
zU{a%i07tvQW!VgBcGw*PeO5(*)YZ1EgP^aV&)Hq(9j-_Z2vte0Mn@0GwPu$tGSo;t
z>-jNh+X9dq(`2TfYzVnh(_-o>7=9trQYkKRG$_aD9Xi>sapg$pB$pD20|f&3q4qgp
zC-|;5q_gtv2ZiEOq(PYRA;ZQ12U~)W`m}@S*98!t6=Vz-gfVYTIfw=}I*UC$Nv4L|
zo=$NKTS&Gj6>u=<3E#B#UPj_lmu-Xm>Nty0Kg5*)6Xfw8<|%MzX@N0&KuI0~B~%X4
zfM-7-YgV};BcvbmpsnQR_@&D=Ph2F+GqZzwcj|LY9E*p|Tw#=v%l0<Q7ep=vKJ`dw
zX#sqaaT9@Q#*ZZ-Ove<!=mCwZM?&o-U4&H<yAEf+yPD|Pu4ma&*vh=rR>pGcqEo|B
zmE_Jq&RbfQ-bdDl_faavGIB^p!i1|vQtL4`H1nlm@`=JwLCGgH$WG7nGF1VYsCuA}
z?k{aA=5c4*sZcIfAo^0;&=mws4=1T^0RkD|gbmDAFI$b%*Kv_&@f5T~-?~l4_o`r=
z`REgAH1zm3ftJL65Tb^4NfH!Vyfs2v<+1#F!y-vLp@@hzApCi-O3Zmas}4Sf6Cw-;
zr&5}AJhiz{<)>?R9rvWUUfayHU&704R`MN?*~!`qh%&`rzX(K8$tgr@Oz{>@Kv%w$
zm}@(xEOZQU^91HBF!R`GU~>HWf&;@>$yNz+^=g;DSdD|CSangn5msHWrJjs$(?2C#
zE5?(nl?!ty3X!2KnPwsP2;=Kg4p*7y-V03qfcq1&t3ismo#IZENaj2kUr)_>zLi66
zs1R1L0mohBS8+}ZVZ5iZmi7y&3!aNQPVX`cpQm=u+}z2AIh}|Uti<%8<1R}>|73#;
zR}rebz*na=I&0ZpUEBL$Dx|X|YU}=}wz^5z8KfzZ3z-_Z+lEK$7cqQ0Fz4=XCGG2*
zgYEu_5?J5qs1WNj%%EtUK67?vvQxsYYr)C=pq-gDYhLLpwRL5en^0I%&+S<{@#P08
z8T<J)24<J+26Do0_Z5a8T^v4+eiMGa5e9N^6N@)5$)_K9Yi5#p1sz_hm!3}Uq#woZ
zW$6Ry(J81pQ497D$Y0G2sMx&%(N6!xoOy-TRiKSB4@bXxe`eo))x?RZ27O_HPjDCR
zjABCBv+(+T%;dd8?puKP5ssDnm{0vfOZJ5XA<@Hax8|Yu<%yr+8+WgNQ?PMp3XX;(
zZVe3gu^9qICx1uMoRy~XK}K%lM;>I3k43F5B+Br4+wAp{Q}f#h>A((8^tZ(ga0;!%
zVOO5P<D%!S5%0}JZCyL;g<zcj+uPD?c2}s^kC*o3M|a!OrT@(Q;qNmuA*mnxyF~rq
zt=Z7ims?tYza<|yeWC4kio7?>h2On6#D>Fxs3F%XNHS5_a*4FBdi5}T`!=Y3^Y*0m
zbq)!43QV{=W$P|#>p`{_<?qN{p1;sC|F;HH`{Gz)pNo?f#92Q5BGgu9SoWPpQTg13
z+0r6vYr98kt6q0~q$4n?ty1uKhS{;gK6RB%NNo+DzL0~oS0?P^O<nR0b^{hGWC9tu
zpsj&%UubKX0Tm}QZ(Sjew*v6WVDIOH3Z>VjE{@rccxX=^Q8z{bPp>|dq|%o2-+PVK
zCDH|XkNu=2cU_a@Ii+vrk~@Nx|E6ZIe$)G!*7(O03lBkDdi?~N`~IYS$%iOw^Y5B-
zC!b;QBo<l4uo*072fX}1tg6dqh+B5g4{J8<0iyh_N<s&&<&2Hg)&*l!a=p$7zACkW
zFN{zYFHXGwBOmcb?f)bX=RSpqb`7QWwVF-luGxvA&+G7Dh&#rsOQA2Tu<ydHeJl5D
zHS+nf@b4)%BleCsi10_Cvd*7Qv@w6Eu#NH2f8~c!4t?ARUPZB$=cT!p!3%m0=QRxM
zq^{Y*L6lS)_xJd5;`GVBnpcGJVg6<tNs7_=(bw&CX$ZmWKYN!`HY`k9Jr!a*6i4hH
zpC-p@*~M&)%90}^T94`rbA2&Z5yGmehe6b|6CN1ONnXXY;;3-=*O5fFTPiE<Vi$K2
z6pi+M@PwBsDk!-2hP_?yYKEq=G11I!1m{$iIFFZ2QB_@}LjHk41;gD;#8yy4;c`^C
zh$2S%LRG1!od>h2D5s0`Zi*(n2?9T#cpjsAST|1fOG=4n;D>=37^YM!g!E#$2$-bS
zD`hb(x1Y9VkcEb<A2^rwLs|6?3#-OHhAj1BV9YA6yV$J8kZ1e?`>*K5cq0qWMXWWm
zA;B$|PMcIGv&fGv!AW5a`m7D#-YTUyFqI#d=$sO++g#KiixD=pIvj}E^Ac#?8bW|a
z^>FC1dT$MyT{Mn%F<`BRB61UN6~Jx2BhdVJ?26sx6d>NSIL3Kv5w%R95%v!FDt*4{
zvb4j39iW|?!zm33w02`9@Wv1nRR_fS8Vs))e*}}HLk&Uyt2W|dYv2~5bIhT(K0c)-
zCWZrpes;>)10j&DT~ZZ8(cVcF%SS>><ON*%0D+q3Ew6PlDiF#MCbKD1giSnvNq*yy
z78?jTR4~OXNaAIV`NI2AE4`5W!<x`Mv4F2FQ(c;sH2Gjw@{26j#ZU*j<uzch+J{;d
zTLXup*v)eq!`$sgpgo$)hy^B8ABe@WIkf5Q0HuGFU+5&2Z$*|0cn*Y){d%GjKPB9V
ztqx>uQ3$9Few??rc?8bjFrW8W0asCga5S+Zx>U{jK#2Znsh5&9{Uin0P!s+o83fmm
zG%v?N(`a9P<Z*g}Rl;4O*Wu1o&W{LH)>t~Ba2hK5uHh>ff-FFF7*wXnDXlCCMuKmP
z8IPq#CPrB1nIQz{{|2UluM85#X$`gy5R*#CDq<za$XB0`n|X&66@m{{xa!!%`_|#z
zvt;RWFNHFRx=fdB`NgF7ZaSa2mo3tb0MGyAthKLbnEm{WHS?Q&R=d~By)Sf<tvT&r
zJXFoU6DXs>`lFr5g3mrQK05mtoF&t45+4pcaG(svHCpobTM}1l>sgYV%Cc!bMb<aT
zh`^vo*^=8A6c0;$HB#?DHCj5Fz~mX6!nVYPDGaO24>9M5!*JsPP(noEi2N>Fg#Kll
z=Q0a_ueFksKfM_2Ur^;fmo3}=cjfTY51?rgwDt>;y0ft}tWHi9;WG6BkAGBKr2{_s
zW^X4x?i5RmVf-)9R)4_E@8IQ`op>(K!;>6m(z54?gY>9mw=Mpc!7zFCe<9hg4KRH>
zo@QK9S}KB`;PG8TV7kDvxc2pov%jTo!0h%BKQ?}lj$kRx7Jjylfoupn2b`{fv8zvU
zId1Fn<f_~=7(aSJG5ph`c0226^9v7+cqH8i;4GA{jqO5FZ|s~PF3Xr36DNV6%ifz7
z)fFMnJ88H!5Y^UGWHjVWQ>XHBX)jy4F7j6YhD%mTZbckv&s+QMfiV4v<K;;HD>a+_
zM9p@;`XAY3{b*_7F1DETp^JLsYT=2o31hW&EeE@y#8{U^=-mQLgCn)IZuc9PlzMJ;
zReuwiw5fkihqoWWw{C@>x3k*n(z*1LzmOJ3KMoE|vi)$6B@3*f)gM^Mf?b^iX_S3|
zWW!w_2~AYbU`cN6OUsz6kC^mGf=^;kYTH>Z`VVe;US+PMQHGY^#d)PBc|ab20JSwA
zDhKRY<8v$hk`2hmgM{uK=NqC5Y(7khlNo-wrd{Gn@`%({lFfeaHC%l9Ep8FPJEqXg
zli_q`yK|S!2LIImg>*i}x6dhBMF7J+&d$5HylWy)KK-J?{`&ju?Qa>|!fGp&`SN(m
z)GKkU<{;*cA<AlFuQk`hgU-sY8+yi%<)00Au6fv1?J)bk*~QVx;e3p5Y(K(A=a4oY
zF}FgImn_H~b3C1ef5M9c;YDmCG4}&^c#sjxy^#rU>vTjwNTT2^ZL;H>g;X>2%k&gA
zg<2cu4~IR2)Sw>zZhS`n75x$2Z2HBsre#3g1lB5!mWS24`nA?2=_b-X{T{DvIP9QT
zpMD(!Il$?`l;J!d@FmzsL&*NCXQ=34;yQDp*4p#r46}+ukEYHy?kH^Wxor$Z`axk2
z+xP!|EI0j7x9AUNWKM|fZsKWIY5F?Q7AH+CaTq|6iUszl=8!|TWzl#b=5Xo;HAsNP
z0N$2>ps5!o1vGYz2|B6h0S5F=5S8Ptlo1(KDJWlDbTp2V+Y<7PMT0ItIDH_B9&$a~
zd@4HYOjKglhza+l=$MgSCfB&~7AhK)P=x%LM!YnZqr@i4@__tYUX_@-hbzy$KrH7%
z8DlBGg>0ot5RrZnpyaOvS=Ea|R!SvEx!wZ_uR)PjynALD0?r}T0R?)tW;bDkSx4C<
z_Y1E}VZ8<aYiki~Vj|fRuVT<w!g8HtQ4B5SP9-Ac-m(oKA~Jh1#sztNsg>kX3-}@a
z3m^%+c&|!C+4SMp`FKhYdiDZ&kal@-O%RHj;|7R?FFTIdj6W!sb-^%(NMQmE0+Fzk
z?Wt8|yRBM`Q+k+wq&3AxWVR<J&N|58ZVYAW@o@aA5pg}5{(pD`H$f~-e!jz{hoNrO
zQ7u(cWoB2PwsHt4!6xvqDS)3rxjLH57)^BD{82whlnK&^@XQ*bs*Tm~SY$p4p^qni
zFt|rjT)8eno;$DQ5%n8xdGi!7moAw1TBGO>l$US=IW-OC9UfTEFS1p^N5`i+5fyby
zeV0|aVfK0peSFyl1D`jtDF@@Cl|7|s(i4cV#TJq|kQh1$SJd|e9nGuShKS~RB3ri{
zZi=-^a-EJY_?UdhEkKZ;CM1r#h-p!gu-Z>K<UqgOBr7mf@PNBKp;9eDn+1M-fFv?B
zUgfImqAF-7?4-;Y%MK*%>=tuDiKv}^#LR1kj)#CM2W7c)(bn$~BZ)}&>8YlcDCC+I
ztCEtV@7l1a4O@jBDh{$IQ#8Q3)H7r9W<ZqrB~{(byc>XMG0>3OIwjooQLM(b-q7&=
zE!Z8u`StGN@O&7j!1n})Z#dx1>KCwMw|;gUGw*>)!O8_;%8u{0iPKk5A^*a`soKE^
zb8JDs(Qz4oONXc5hU<G&K>L8hKi;lY-e+TB+XQOjf`Yhwn91>nWPH8zczJulBliy@
zBI=DXDtE;`j|^|pzP9wX(+4tdt)1;OUtG%=1>X>qA8}B$LV5ba#mtQU4h=)%>3TZ&
zH=>fS(4*KXI01DU#^Jx)Z%<?S-0-CNKPJGJSjh4$lC)VTM`ibJ{xikt**l2t_@2?R
z;+4xGe2#O5{tmmk6Z__`)L9m`iN3Rdl8qfw%<+p^tOB=IJmtCxJadA^_2dUryYF_!
z@*t@!h|lfMrVtGL`A_BU#B+f!%yaQ13e1V7I#Wfy^akd6viEY1u+2dAw}-vG`8@+I
zh3O0PSCTuD@00JSv<;GNw`f+ED6c-yOTYf(91ee>X3Mp0G*O?+ZQ^T*wf|@ut;Z|u
zHuLut!S)>q@zWPuVisLADR;lzx9ij;ZDcJNB|Y;Ui)GQrCEYW4psysMe81VN5r}Sk
zi2^yqz}CO%0^7gmB6`sOlt@A1M8FT{f~)UM+;35Nm;S~=KJz8|{hKbMw>TQyN8hz;
z+1mZ2QP}IGC6AqzgWa}Uxh>{`ViCrcfP4xko=(yMsjbJ}MpIhFkUw%`(r!{G?1L9N
zV@=bZI)1^h-vMh<?Glw6Kfp+DVVOf#&yy81S0Mgo<`hF8$ZYY&2&_beEb{tlwbe>(
zN}ZYv)^1O5C+5p+U|*Rp_>e9R==RcjNNoY`ExX?P!{kf8cPPy+eNC}+(q`E)(I2SW
zG>($fC@kp0(=g}k>R<7({LUy5@wO9sg34UNYHM3XT`TIbg>v8D7VPHj&gTCnm9_Cw
zD;D-mSp6vrk9=~6dt{ONe&Ag<oBP1qXwu%s$7TNA-YsNBp0xdbRCZCO#v&kEng5bN
z4bfy=Vc)1_Qd`^YUs#JN{EUT#w{a!-$&1XfBH0co%)5#P8H)5PAX|PMljkCq-1dLS
z4HVwHShTws8@+WLs-&V?liwL(P_}_Ixrw}<rJHZ4Cw*;R(p|Y=T=UdqKxXNjr$r>x
zRgm1Uw8&l;%rV?d!(fb{=c9z!4ur>HVOrnjjdlF*#TLpHBocLFaVx?K)K;e;er^8n
zZ!;B0iE8^dPPFZ~Z@VxVvhY)_G&wQUn#ljwtfl+2Mt&TDF28wsGX0KkucfQFHiDGZ
z$m7iRY~**ITd;l+ruvL<tl&v392qqstQHer#fV)fYNxbGm~RU+ns=3-t*WgZJA+m5
z`T#L@l6^?KQe%Q7LF!&1QLC)*q8*<_F%d^Mp;{A(C^!ZcYfk}jE~GZ;u=NIqcWo8L
zXKg7ZC^@R;uH&9BRt6_7CitxaG*!^>sZpy5?0G<3;WXN8V-W|%A?e&W+XUq=kmTvu
zw#s`maPg+l&3w;w5B^-24eVtk&60Lu3wX!U+d&(5$W4xckrJ<j8Afk&%#S+W5pZ{E
zH`2DO612;MjQxOmSQwSV#dCTIHBUljT98LLt?27KqFU8iLYcgn@lpdS0<E^CkVYC@
z$VAgMjaae#2;jtzR`rUIg~X|ytzfL?=owXnfzafk&PH%+^+Fb89>EJwt5Q^1S9#60
zq>lv%qu@_Y?v+4jTSDdA=Sk<+O{oVaY}1SMK&ZULor=^JAr&gA7v7Z$l6kkRH&rIa
z<Yeg&nZ&|<;(BNoId^+UNv(y%dE9n|=%AKS(5i&JNSG|LhZ`4eRpfUaB4*!5J3s)-
z!>-x@U{l$kr(6jVZ__1j$M3}TwosL53&D$K0aBff1~RWA+d)G{zNAeY25ZeGjZv&2
zPLVo(eIRP#-u1!SvUeqnuvPqK^&ufBPO?sz5DPk637j0N`05?MO<y{;zE+yln1%JY
z%UE2H6!lvLCau#_nB9EFM=^<%Zl<gvZ^01fFQoZW>-K{mCqjraGT~-$NlAaciYZjA
zb)#LgVPY&*go63Q1-#qSaFek=lAVZ)FwvZAuOWAXpZoR-Xl}i8Tb6TDUGLw+?AWyo
ztX6)J6{V#22EZURo`6EYai}w}vU8F#M(QR0VMF~9WRi0)a4O3{@dM9n(GxA&_H#J@
zr>T85{5<C~u45r5kSvgCePd4mHGL>L@F=LjP{8;~xzGpF^>SN*<Ti8!GEc3>X_Pq>
z@XTJrx|_BQ>syuDBphsIr}=g#ZgEH(o7veso=7O0L{qz$bHdG9@l@lod~)%d(3-tr
zeX5;U&V5Z5*;sh7y08j5<+dVNDLJ`A@mf~NVKZps0in(dA*J0Tw}Q;w7`!ZaC>!mO
zKYnd)Q@>}ex7dqud7j;;BNtOtUr7uv5F+ji1y8#qdV<4OI8VKI2YE!)#bTip*OL7l
zo4=lXv-#zZp+A+#7v72!EPC4&d-Cv`^9fBQFnDiK6c1U(Jzui+1s{YG<;2$t19wpB
zT3+co<sq^dPKs;4mspUJBRx`QTb(<jrO68`lIIn{o7kwVJP5KVw%_{ZMYjCq4?BI3
zqj~eEZ*f`r%HmjYJh!87xY!A+H}G|f<pZP;DHCdxMkf!u;t#kxVe|zD##vEyG9)PE
zc^>7j*GBBomlxsT7j9aJ-z}M2sa3gt;svIOJAwLTD#Y3Jb`^$6g{aZ3PM5@ERSXhu
zdp~XC%q1wMOjX1=3$3;;e<n@iZAEkMQCL{NZ+I>Y{UAqw+$-k$04Scs6QMHSz=3Nu
zyMFrQh<l>R6{%X%brdqcFmfm)G1+*w71VGlULhdT0aAA3@3vWw*~QrY5h&V?`;`Ov
z{Pk@#z&}F0pWZ)Ee}btA-1`87(5J>;zlGISA0vvw>JcSnynmW&;ZI_03^0kn_Q@o+
z#%DU7<;P9zMd+Wcv1(B`E0|3#W>KbV(;E$#_O^|wn@FmLIQ%j$t;8km%bcZNu@J2I
zc%V7OyB~ORV-5J`Q1Ubx<e2)n6P4tx!D+UTLPg7T`W2R;wzg4Qk<WE-`@w<O{jP>D
zZ9mO!2X?s&?Xm1$`k}z2jJ;>?d|F-?-VoGm9Z!F&i?-?8zklBBxvk{?rcs>jku9HP
zU(K41tJ8a(G(HmDOA15g%*(<VJH5JaZP(EAO^pyZ1+9veJ1buot672=w~rY<4rbt&
zQ>b_e!kX$F&ZWD;*!am*f*`~vO+e%$QZc4dQh`?~UA1*x&wBf_Y!m@5xscNoKLYD>
zt$r5i46kf~y6kZ(Y(v4f0IomI*-4&lt7N_!Nsv66in8Vqi$sr#dPokq&sOg(J-wuw
zCs6<y-zKt7%h+vP686%hsI6m4G8qXu$u2SsZpUJDdudL|IH;XP_E_@JDJgRA1HOYA
zj8i6*&xd4}c0wYar$DQuBcaQ!_XcH6d9?YFtQFIY(s)<UwC3ay`e=K`8jFt&hV-!k
zv&Czwvg50(|GKyvzIDWZ3)<+0VK;Exz0M5@D)PRNEg|eW8Jcr@ey~&poyi({J-}=J
zrLTz5i9E=0U9Li>f31X|cPuyQcz0oZ5QjR_Y_XJM8HqP7qgcdd1o3eV2{cS%=mTz@
zKe5=-ND$=<BBmJh9p3~S?&H(ggI0|?;JSv@H(B3-<;2@KhjN~fJww^@L>xF<=oX<e
zq~f3#xPYeYXWG4Rek8xJhP}0HrPwmvrV}{`dKS)O3<YxUMCI}52OU|txS>8|pa;o$
zJ*a@4<&;RmLe=WJCFHXqdCyCZO@2Qrz=CI#63Bw|b!35ZsX>NT)Ol=TvO`3$85JP`
zr1F1u6*w9x0eP0)Q31a&0p<wPU(KwjB8*`-d5BxTiQjq7REplfMi(K#%a$QrlBC&X
zpr?29sMmZI@`un~)=>T!684243<el+!Jt@P&O$W<khAD;BFez+Znse(lz}MvEPnYp
zDCMg7OqFZ3YL;I`hIy9#c=h!xVfO%J=bj((5o2V9_?!m9EP}tBqOq*Pah=r%=J%q;
zerMamoNWzKTeF0W%8pT-yU<`$K{oh|@7l@wVwwti#3lCb#AnBTgKNltgHaeGvH^R;
zYROo`Ki9+-g~VU6R#2i0x=13-$pXbf@p9-1DvhfJMRCbN(22pkEM1R4K~1L^7Eb*)
z{EOd9)5W*YyeO6C3yeg+{*t-$+lOlk+Z$Mg5BlPw=c|APeQ3@UjY1`@%hO0tb0<q;
z>G)KnCzOnte`3;``yQ^XVfvxlldC-VjX&Q-v+-4Lp^g6A7f9md5BFCDyEA*^8Z8n_
zmk*$$&T|v{;$QRbv#721*H1HLRNuzF45_WBlKh%WV6-c#*<0Q;l{dbdBtc2S{`f&Q
zzUIGunJr%O&ijh;!4zeD&&+V+8!S4#VVm<p>j^Wt`?ZI*jTYS;WR9u=&ug9dV`{GQ
z>hW~sUpK1NtOP$Oj6ANCL1}bZN>S~?!v{Gj%!=d*ZKQ3!juqDv+&i^|LO(Yr9i$($
zZNiSc7>Rz#PTK817EhNdwJ>*M5*~Rrx5vK8Oh<PDK>DK-Zy)=&qiL{9A^E=z`DSB#
zrMBh=XU%s=?w7EYmoVV$%Bj4k(zQ>Hut<CZHCMW^^jYy%zl~&#)z;_|PI(^%;*`W!
z_vFc;chZE&qS)U4=gu#@WLtjmk@uGQ!SC&C*$22Gdi>x(yL=}nLxt88oK43)$%;!g
zt5so3`#K-|`A+A!fT8?ag|)HWsuLA-%}icPe=LtIELSU}r>t$KXK|5g_t{08Zx1Mc
zwg9x)D5Z1)E_I5ltuRbNI6o3Bxd)3dBAn^GKXDa?0NcJ`(AnTZJH{ou?VVBHp@Y=t
zHB#NtEv#vK+Ogc^%l5c$4!l*vdU%tPTJaXu*83`#kq-_ex632KF{Z%$rLnkI4#^jg
z<0AuDewuu~Gi9Rs_O!HH{gfT6yZ#apr>D#-ve@tNcCgCpF9q)GP@!8d&vssKW0)5n
zUGIQ-y0R;<iol`D+V{!bG7*QHyVpvWBG9kRucOL#b2o@j8U!-6uqphNok3S};J!6D
zT}8fzToiLeRskhM5F8I@zG|f~<75@36sTzDF>YnoXm-5<Wj0v3fa}$l+-cqi64dF?
zJ}^mWpqom>mJ~LGv#>VAIJ>S!l&~=(uAN-KBtcJ0d1k(#lgJAFrMVEy;nx>3B*pY|
zM-FRJBMx%YNstV!BdZK2LnU}ub8|{@?leUUKh3sJA`4HLEkl@HLq*)aYttyW(v2}J
z#Zfo;-IRCDpIaCp&)GUoy}8WTgC#nLr_odxS2KiEK5;!gsC^+_WbVSRM+@sM>&=^b
ztVcpLePFGXX3svto@8_%Xt0zooxsHmHS5k!Jic4{d&OI_0zDs#M>S`@imS51&1h|U
zCPu=g+|@Elupx<++SQxJj%vA)$3bgJokON_>Iq@hH^wy*Jj;p1z-W5VJ9w+W=|u}~
zQ>d+R&msHIXHxLw9`uaK$1Y1PuhX;$B=VNDyc_~_*~Hjj+}e+0FDNC)5Y|vs$o^`e
z7<)qG01SUXw00n0X6+;LIfTELDX7cC5?mLl_gic<W0@gz)+J+^Xfp)D3Z^B$yDo;w
zm<Fkm1nQ1_aPhnrLH`jz;Uiq6r((5{QN5(?H2FpFGrZ>cH7Yw^BC$>gUkx+;T6xFh
z(eJ!4_%-NT!$6RY0d=>J!nP^++d$4DEt}%3c_`u^1!BCbY@Zu4b1aJmhAsI6iFrE%
zGmJ5+G>+ri9)O1}!)2C^jj(ByO~C`<Yuf43g+P(tG0<kU^%Hi+DG}0WyVO=%ys0#`
ze``21c~{=Wvyo*3wp)49A1Y$O8(AUSq_)CsirT6VQZ^Iz-K~kX$qwK!h1by}E7~`?
zSa`C@48?a>u=Ln1v1W3}ke2rKBL8Izmi$V_mnI)H@1L@E@_8!VA}2_566pz!EZu*z
zU&AR!0tJY|LP*i<WKk?i$Mfq8tB7I<(h=V|F?2ja)F0=#S9T)G;r$8P-i580Z2b;+
z`|@z5bgmxJ?v?h*Gwert8#F%3Es3YUQ;oMp_%w&^4n1*!&e}rH^Dz;!!9f|zo;E<!
zzx4M~@#d3Xdfm9ypWVs+^Qxilm7x5VgPu`N#1$UG)S5QbR+HMwcIV8Lk3rKofsZ3f
zZEd?#6xSacWXz0fa}P=1vL~}^AEyJr!7skJ<=S7lAe;W;4nBhOcUVLIQkvS8JEyF1
z)Y6m9i|4`W2So@+Y4lff@Bncs7gUrw;<q3tFk<nNxhJef)h!HQ2ZcD#1N||v*WE$H
zZ}B0~#@?v5YHRJ$pF#01k*&5ID{x<kOYeU~k^BJFf9YiI2odHkO==_8kJ@Lyxs59|
zE=PZSN0mtTY%3iQqpcmkYfU$o@D;FqoRBzJWHT!@FY^0>mWKz>PP4e$de61gI_FLv
z33>B|OF|;GbtiEIZHcbb)<1#UZ{c!kI*YppPdvjy-50O&Vf^rddIE1xUS#<jzhb@&
zJ6w5$HRQWbC-c|-*=ucl>3x=d`OLN~Zd2+*+C+JRGJ94IRylBfxMcZ!x4)9hH<4uH
zW{UQRrR}(pR%&Z=kVWuI=s{K_SuLW9y1oD+YAabfi*P;~J2u;|Pe8nkV)~SQC|&*s
zu3Bw9MO?J@>`1}jv*b!Y=ILDtn}s4@J{jWn8~nBa?EKXhnhfpqE>>FwS^H=x2HuJZ
z4}%9vNarTufzH`hu4+rFPPX>@lj;Z-{y*a02FQ}DIuksZFRMDcR8nWRN}`2@bgR46
z6hgoQ3EVcl=vJu^g)G~JEU|*Y%#$o68MEUym~lG-<5Q(V6reSQtO+-389%YIEo&j7
zS<AC9;RvUGJkxmEa@zqcp52)!2$oTJcO%-~9lITa$NPQfX6AdZs$OQc(0WeQ%e+75
zo^$TGKY7o+H*d!NUE-NUz7xTQ{>q`O^Z$MVnfbIVV*W6aC)cFEa#`jkPNjX)Yyh9i
znRqW7(n|sUf{5UO$^@1uc5tCPh!yt{i00jhztO`Hk1x~2K<7_Uz82`=5mYBuBm)~<
zIcOllFB1oO6w|sWi)L6MihTjC#C7WFoZ@8$#0cnu`@GLq{oP$d#G}7L6y$O1#4$K6
zxq|G?zKhO>gCv3N<tW=GKH~K_^V0;^g~w(Sn#C`*!fK5)t&;SJjqW0KQI=p~$}9ZH
zq}?5Igw@Z4IJJOLBh`ziiGfyHvk1Jdl-nYzS_F-m`=O?&<G={Y&IQxzBG8*mMm;WD
zV`yR}hR_C3uG|7T-rIc6M7lwuq=1Md6s)mDfW5;8)ItB#=R7-X7W7ROVA7<6B_J5V
zD8Ec@#&8)V=T;9%zc@m*Ss}2LS&`d;YlqenOM}@ev>)BZu-WQ`>R{RQ@M{5FF$Hug
z)D25*6N9ppdCogPP5KNGQ22{z2Ck1qFFc2XiO4%(0zZ~6qUmh}AP#`_#mW@LIjJFB
zqs>U47TDxO<&217gux3WLW!OVn5kK<eR>phAcgw7?YJJ)I=*6^qrOk!>IB7I3qHio
z)glcdspwjOc~!)h_ZoD^Ton*!s9Nz#@J;10WcM^%0hx_D3cPVQUqoQtN)oua=f|K=
zKfA9T;Q0-sLlEIECSZBa3z*{6Nc?2C6c#>mF#(GZP8D)82?GU(wyq<HK^)|d!jO%x
zie?e12q`O52~PSzT4HNY-~>b-ueCU&T64o(%LJo$=E$ueKS3L#k=uR6l<M~25q~X9
z9YLLN`=Ct>TWGe59>bTeImW=TE9i0%(#O+KPAr%nMiTDoxfl7r6Bdzdt|Kppf*xNz
z2YN1%`Co%>KDUgMB)#Y9zZ3WX4jxodw&1aTB==%wDTfKfHXpy4+CAcNX$H*Y$MM$j
z><t*+`LNoWRA%cX7)E9C^;d8Fl%BsPC);4QZq3R<zv@`<@e$**kvQIYxhFb3@z(qM
zAHekK9e6J&kE0F!i}c~-FE87iTX~-cMk6du=qnu`1a1c^*;!}=2h{|fHG(6eCmOI<
z%0ezFEEEw|RQ5@j<fEA!g6S&X{1yy9ek6v5Z1=7t_3yYCjSiLp>TENZ<#HYPOx^&#
z8bn>it9SD`dg#>-o>w=b<)4qdy=01$pb~fHtv-7iGa~7Syew|rgoc30p|hXeL?^iO
zecxS0pyeIkdmef^w^tP(QeJr4%fokx<m>2Waqd(0hFfru_shS4rBuG#dIXxr2}3@E
z*=j27eQGjEDeTJM%97%qFtd+6F`>~<{EFy9@4QK#d0|g-;K5g@yz7r-edDu}63qdn
z0sQ*I`_@v>GDA<O{}RZJ<)RD##sP;*BaDy=ZKk3ij>*ZREPPKRb@Oh#kz{7;y;IVI
z-6kio_5LJrX^pmmd%mkw7^Va8xZGGa#u~v0pYBb{Q-6$z&d(y^Kf7X+FqmXd#<J<L
z$h!WQP`2!I@)%nC3qOPTfq&pUR15G=^4S5z{V3Y!9^I=<a~f~Eag(r_t(;I)ZW3PJ
zLIdR{VVoAtO~UpPpFH)}i9#Vi8LJ0w&)&K{3zXX~OCFm3it6JZoE5odANGC!bfo@E
z9cd%lV!rvdAX!y{AdXyqA5au#8wv-YbUckB^pV{6aweWMYc;>Z7pY;5+R{Z6F&s7)
zw!LK6VCmxPR(GJV@F<J^5Bf1zljBYIiF2T(@XMd!oKL?3{#P%<)bf5t-wTWNBFOSz
ztkE>_MEsM5lFbBu9`pF9vHgP^PVSQhd!!f*Y!a4;Y>%SXu#GvNTD8?fi8zNz$bKz6
z-)Xgrd}dmcQ?q#M;82=H?}#AyrP;K<Y}R3hHQ+N%4X8XH8vYQDg3FM%bRzhr24509
z2uBPJb5G^GGV}uK2GLOy7g$v2v%TPXN>>2K8%O)=!CzddJtm-*R%nm-Wq3X4(6d|q
zfj9;f;X&Jwnz<+;nh!3&@P;y|Upk6=$;p=)&a&HKIA;+?Rr8YV1zLI!MoWj_Q1lI`
z`bEmRn~N|jybaOso?ymC;Je3-gto=AvcpK;h7S?)hjp<nP)d;{HHykL4{y%;i=rT4
z^`~YRD9R`3(_Xlk6+Dla92bW|(^%e5Z^x0Ni*mTXg#I3La>h2&h;OU60aO43BhRY2
zX<nUUM6YPcn1{lOW7wN)-9)O0ElS^Op{)#}q2s`hl4UVA{t$dTnR^WJVl1tD)J}~<
zc>PtAP-l0;QU)Sk937CntWWgr3ZAuzStO>%57HPoy0%3)obWEevP|$vGU?1YIS6ek
z+sa(*!8VE&8fnZ3+3GCFFYi~r;)*W<IFJ@`T)<`WG*Qt@k(ZA5p(S#jiBdXB7URb8
zg$E6!uuxnZ;BkSi9ZQlk$vTid2(c4jSL|?CvS39snpqA<$pB7zz!rB;4`m>#GW(X?
zA<PnZi9BKij|`ZwbTz=^j1Q_T^5d%%1&^V8Ql?ta#N;tqDtVD2!Ot-zDO3><8acQW
z89|We8BDRWJjKd)vJ(|N<q|5r0gNqGfXyp``m&{f7SLqS7foPW(P=aVY$eAr<KA0S
z(HM^@3~az;5zjSb_q03!IZzH^;i!SD{1eO(dLB5T_(L8NTmhchjlm?tiGS!#9cV6t
zW{-Kp0*2tE2)<n4fQx1rW-vTGF@7sZkL*WsPcD(`Or~;$gMo&mp30kYxHJN?{|0BO
zq-4;)=QY4_+_ZxW#;US~Uo#wy0^%N^9>p)GB!G&-NCZw8vQA4UJWyjue>qBF1vyZb
z?+o(X!_gchP!C|+<ILe+<@78jVu~~~VBp!gU!;PKKoa@*6jo9}>=b@ri|<)ULMCCj
z;t-0oF;EJ@5ilO0n*-WI7VhaNOLATvbDXn-Vb8iL=+r0j<la2)#hnA%!6ZG{CQjmG
z(D@cTvd2qWX^M+y$AQ7n_^9^rt;*zMa!EhMJ64IyJ5HjjU@|aWEoeugE3uUmv_c6U
zlNeci(XevCDcz0~7DBByi(jTK*|Ic;#os|e%M{hULfM|S!Wi#BQQ}`5G0JKHkJ3+Y
zb}cVNH7HTdQ&hkr3O6@!zIa!~s}+eB*p-?F1b0Y2h(g2g=%j{JVQ~oA3q|3%L~oy$
z1}G#$j~xK2E1iRs9(*{kBzP7-Q&rVqBy;Vo2oeH#yW)Z|*H-EFrGp%mo+a>eeA4nz
zkBTj0M!+k)2a2+%`$dA=CEW_cm{CUuc|gPCMIjO)hcY=W?CGIi%OnMbGQwGe5{qT$
z=*VO_Q>L2tLcH*96W&!vTm$5iplfnqtkfRnWL?ja908T(bv%~nqdW&uUz8c*`H<)`
z5sJfIQyed;9O&HOZpE;*M-=q1O@P6GdW=jamry%p6>|pQ;gJfuQV!=+U$AyDLL>a<
zpb%o%j&ZBB)DUBNSNseduh%3P&x5MxF^xM=3~$_pk_nRIAGrjOw-0`Lhe4NzeRXcg
zpxfhX)HJD%Q{>@GP9dGQELY-eC$__{lpEl9L8FLor2|AYQffrvo-Bb2GDkBc$4@48
zoj29UBBXmQ%L5h#E`0u8AfRe2ZaPckrg5gI8eb?j7;s>lKh3h91WQDn4CK{hG3gN)
zvmB5>@db3@St(t)H&XW;<$5LN$Z%tph*S?{a~i>Fk!}Qk;Hk*DLD(1<rSs%O)c5Q_
zQq#(g;D!L^AF6Y%z_SA&I-$!A_8~DUKnJ-vhZLJdh(C>uNN{U~(cV#(;(Ynkps|Oo
z<jXX7l;t&G9dqmr@F6g4r?Vnur~^JmiVh!#^Oz=6#ni+liw?#8Dok5L-ey21d>4G%
zfNz6T;OIEqZ4qaXC44R$XPL4&WA2VHv6(3E7=Z6*{cHr4EiU^I?%y*b@rE<^&*SPR
zyu*o=BL94LF1)RA6$qX|%<)@r`9<jZJ!MbwON%QaF9*w_)fti6%T?&hafC}pe@!M7
z3XgF%_Y0zZ52KMs3Z!#igd@LbHL<zThf(CZXAPUDxN-{E_|XILB95&fO#4TpbOMg-
z){Y$1-;?L$_K*3gFMnGOEZmu`#ZTgdzwBSME33Z#z)FuqcR+>^g<7m*aB#ri2&p3q
zS+i>TA{Fc55&VWDthiQex7G_NReaL|69;&`jcoJf11_+|c0OrQtYMPh*q#vQiz6tL
zABN%c<f=LxJAzf3$oZ|eft<bV6es%gnB-5eS~UM-XtYc_{WXbmvYX5(aSMol6NPXd
zddl(bNPaK_;IYb>90p0ATa%yNliA+1_u&(j;Y*ZU^Z9vn$&ScRUnTEJzZRaz^72=B
zW`FbH{h!8M*jHwy_r8fWS-m8iN&gF;)8E5v|DWTlkxbVBo6++>2?2nm#2n5|Q7%EP
zzz84zAyyp}q`Z-G1ttq-gvUH1K80C)E~hO&5~15X1I1qP7EQR2(|Z#<mgqcIx9DgB
z(=Czao<vdVVZ%T0bC?hO`W3SJQ?Hctp&Ot{Fj@OQUkf`rN5{N{&yc(mP1C9t%4PbI
zFC*>7+cBN^MP|MQM6a9IjrYSi-s)(C)fo;y-1V3<`=LuQF@n5#5Sc%<5>4XspXeiS
zcF+P|36vl1SOLl!s{@t(zC4PtLD=1o>LB^4!<c2mIxr<$ed|Qxf92S$|2*Cj1B$5*
zNcFH8{RT#C!12VZ)1VtJb0XIQL=abtaZrEV*+#(ldQ7G8n-=J`P>Z>cbKkVQ+7cgY
zAX0IFeQ)5{xB1{+negGH_0!npr?>P2lP~Xac=n=}o#Ug=Bg@wVeG39(a!2D2qOJ9<
zgA7D!uZq<DDI^6gtj<t<?t!~!MIMc!z8xupkf`&wxbh*hHJ!Q%^#9%YBUCx$1l!x_
zlJ{W||L#l8De@htTK6C&CHopq=8}IZSI7ruZ<%@K2e=l}2zuZJ)T>4`B4n-=+65pb
z{x0##1j`<(!M`jFo2gVe*fP8kP=EolMW}@Ddk`>Z=gq;>ve^)X&n}WBP_;^jfu`b6
z&QLb$d5KcQjlE495kx0FYa8D6iCc=S^Z+6ZUxF152C)%8#qddq^J`5A%{<C7@eDPy
zKvGq>F;hKx077S<k5ra10?S&J13u+5TM9vv;{jw}1VGlYph0<f@X7Rq3bZ=8S|FoK
zB49$Xm4YYH6h@#N^>(m@4-uCJx|2{3H;HM~Js{Ic1txP-9S@i6@8b!F4OO}cIm$YM
z@Op5O#go?kaQX200oS!q=S}$2iDa_~h*kr##YvGbN@t*oaW6X&!kVDM%l?kf6l(D~
z5<~X%Gkokj#5X_=!zfO->ty#t-fH{qaYg8`*a+HQq}!F1NDeHI>45MtQ1rk`9OWiU
zf`VYSY|fg?3gQNw*PT@PaoDY-s582{_Z}F1h6E-!ffT*%Bw{%Ajtx!Ag0(n-*_uXi
zZ+~)7F89E?K;WBy(q#r5DC`fZF$`RxJXU(S8J>v1j!Wi~FrjF_o|3Vg=|QyT1NXpM
zAHh1UqIYAaJHoMkxJa>Im3ZSJr7B6VWD`)UIy9Wp4|{fVZ%<`v975by%(@rG8DCXH
zt|$VblI3g}@?40hy^b{L4Jh|)V8u;m0Z!pIUwVYGXqVJdb~|5L_MwaRJR1qIY8Vyz
zg*enn25JB+A-ut7<Kq!kIF#Xn;ebCp0oI8F6?#aPth1+r=N&5QUxkQ;6k^V!+!@*k
ztW?b8Fu0vTh}L10ac*BmRJ_a5DI<pN??FD!AqC9VgD~w7^WGx&n-r-W$T+wgVQaNO
zS&Ek=|CD*0!y|SBpI3f@qp+{z*X^M8UPZR>_{2kv@f;+C>3kd^Uzu8uHyBgez;M^Y
zRfX<)N1&iN6veOL@EEKQnb~?q@ZqNa9z99k0n7KseLE7(P%$dDQpekZkZ3#1y=*$w
zH%C7DgrMCghq`k9fi#+*ihgh9HwInN_EbaugJB2JPzaoX5wFS!O77^W`ZjuY2XzdO
zkdWo-i-Z*g<gSds{M^;3*yn-!HNisY)?p~+>ac!9vsFI!6^YzAR68bWfY@GrBjP9D
zkH*pui`hvJ{7<i@tAF>;oGgFX*?U{TY(2kM*Y>0El52g>ZQ%X22y39ze*=--gYmoD
zE@JiK8-uoRgiFGA;RrNa#mv_4B43}GO!Ss5eD{;q^1-)b&ak^D6PT@iN94n=K4h)W
z)58{ETJK*j+4SqZT(hz-b3cI>9bWN^5dJqH)}fbU|8q@CAsK`C#>9`5U>Q-A%YfTV
z8B=plKq^xrpeWVR0jT7qrz+!b!E9Z=BZ_YMBo03gdj|K33uY@8PN@e9W(jz&gUxSY
zF@EJ0u`GQUyKGamP;iCWdQ0~8z4F!Qb1)faQO4(>@#xsRKm8A0mjBhSq*?q9**x%V
zSyTCM@J8Ezhq16<#W}+B%zO*5lVd(2b9~Q_N4W5dT<-cA(Z85O{e=N;Myi>uL_Ko^
z4@jW;AAZ0wZ`p&<<)}@sjt}(iyezi*d-2`TGrgzcB)aVtcsOWBH@*eScIHOued&{t
zbpGR~!|0<ywzV|6IP3)Qz#Mr*?MUfaAPrEKnIoPR%D4m?a{>w79bPqKv7bOW<lHN1
zW~-$9TH_?b{aeRT7zy8pF9LcrZB5r7LN!uECMzF9*D#;WV;q#ebBmShg!B;M*S0<_
zQ8bMrfI)SQe0~8wD78<14kiBtPIzqv5IES`XC#N&>MxH}^=?nI)v+HuYLk@mw_r=u
zEpB>%**Y_S#K`y3uSG7?YaI`yF_sJ2`!Rfca@tAqp#0=r;(trdt?H%yeV8ZvPcM_?
z)TOb#J!#3uU6%dB@qzu0vi+mOJU9-Nw+v-k0BU&&X~ar0z$wFbzb`TvCFlJ89Q=mn
zhO6hell9fXg$Rs?(w@j6p%eY$0gf&lei1JOA7aei{sImFXX0YeQvgEAMI{2+q6?s>
zvd)!=4j7xBE`a0ZcKlGjo|t&J;__qocrb1=@ofxhfY&2F2-JXB81uDQE50^*TjWt>
zRw*{kR!KZMVu&(}>;obbiW+H_Zp8tshY}LZ%LG^w(?=>(G+VjGim{VmVKu?_Jy49g
zGC!>Ww-dX0$Lf>FN!UA@t~z*HR`o^Dz;K?eum`8Lb>VT9Bq-dH1xO@;Asge^V)_bT
z&j5%SX5qdl_2l3*QeYX8W|;R^KqT0`QxM+wnSx5G2N3GY&AZ^t?-E9PuO5(*LbQ6k
zDpt)kDL8_Kr8mSOv8;Xu`CX~7YaBXI*gA%Gd4YNfG^x~DOr>WL%Zf~L{Nl-c5vspL
zHFEesiipDxX<bZ|_W8(}ie=O#1rG<7Wq2^BL87>UEu<2ETHpgJ@`^c+0$jMeS<VU+
zsg&AK8e|(Xtt@Z1!~l+N9%~d0rwz`5i39R5IAc5<($amXl56(_BLYF@qM8=Eur!|K
zlNBmX>1l>f29!c2LHOWt&|n(hgm@?<@x!DXJ?JZKTEIOE52f??LGg-#_=^C3rwP!D
z4xtDNa2vOkxqwXUk&Khg9vjMtQW)a!<J*JMqdXiYJQho=_;eHZ%fybwUki>TU~Q3a
zl_}N=K&2#l4DKo&FWo({5yhz_KFHP9SguM~AF-&-#(K<QV-Q7ahFrGZN-aPQE4XeP
zu&jGNQvHO#XX8gf<_>jXwe`IyIINJ~;JCe-bHCi+n6tO+A=6L14UV%rbC1xSpuf4?
zhvn@sEuSP%B$7Q7y&%HX))cm}lR22J#Ud{>{4hMd$rPt#mb5;NMozK&FNcU$`;h2%
zjw9cK?)l_iIFdCEsGL0Ws}gTsVKj(Z1DJKRp(qJ&gNQj(1}6Bq-O8DfBY-0h90Mrf
zP&FwjY>R+GQ!G3s`Z(~h+PWMpN~AptvvrZLRL!4TfVT-EnF*E)5D&h9vnW0f(tznL
z2>#@%L|E^VTknXR-@==S@zoJmNL5!Rq7-JUoWhYZa@T8pcJSOn+WR`J$~f~(Uk}vJ
zzrImc51i*Kco>MoY|UhEQkt!4cHaB^?8{QDwjS1`G+TMvi{69p>pGG*0}0!c^HVWq
z84&=ge*KY~Rj&L)d>r_j3vu@+u9NuS;{IoDIkji~$l_I2@0oNw97m(L_kVDtH7LOn
zy(kw~a$6aC@|8HF_ddKMq#Ob$Ya#D|2O~n^e~4SIC*ygRON2~1vc3OJd(-&ymtlX`
z`4-iwFV6GxBqvFfXZkw(@Sw=r(L^@a7UgLUr6y5JO50e{JFwRUU2tZ$G16+BIC=0$
z7P$;_6stdrf^GtK;Ir4Jvhn`ZR&HUodJcfx^_cDdi#cazt0xs(Nw(G2BhiArHur{`
zIymbVPuwRSv}V(He|9k*{RlCwpTMVi9(?zj9{ge^`Y$lfd+L<T_BQv5Yqi=6$y`xi
z#Dk{kpZ6iqA@@t~<ccH=NDw{&N8Sk>;`>Cd!<_Ik-a_*e&0M|OJ7`4Ycs7?%Djsh!
zuRe)Pt#;5iV>ZB!ktP#;f2#PbaeP=gc0ML^_^xcSg4s&NM2^fXHa@<{3edk<1YgJv
zbCE|osJF0N@4iW4wn{a9m)S~kSZx*MYjf#!la?Hv>qHn5`kyNTcw58Lu~U3}di7ce
zfBQA@Tz@{z<CO!OQ>|88y{_*?E?IAy0mJzJKfr<LgB)s5iY1RrIBp*=S6D4$IW@we
zP%DY2C}Z&`ClXBixN`{P;59lP8bgp-RUL$|byzJhMaQT^b{bz%F&J43Mw1wU_%n{x
zf*-h}rQ=}t066-YKt-w4tgJO<%6uN4jj#+Ha6W;6W&CiV+_EOze~6IP`yubg7*h{H
zmU<l1Em49cS%+N7U57Lr*Vo9wulOaN7D52fi6&8r79@7))uJMJ+zlNSge)r^o?4Py
z#%%HoFD;<X#0xnTjp9y~_TvK}>e1_gA_8Ol(C|<*Fe*;GgV$RSgU3U}D39ic4A9-9
z-x=pJC+1noQDYqE2Mmoxm%_te1sjO$RlZ0c$a}I5+gU?f2A^zGeC*kua<QTw7UY8t
z7^tExK)q$81!jpdB6%4&eAgU#MBeewQYqzSy5OeDh7*i+4@7%t1I;9!HOxf&krPZ1
zNB6*w<9b9mLU3m>ulmfSH!fNz8wj+5;@&Jo=^*Yxf%OF&7VknUgBgyqh(N&O$4;k5
zk3Pq;L>Uk7yomNACW83H5aorcuz`_-sGAHyqqm8sLl7Q$XoAW3lQH%_63x1cT70dI
zWu!^gh&7CW?BKv-7fmxO1+YN9UoA5i#496ryMrw`_Xly#1yK?QJ-THKO?0^GI?M`r
zFj;~+O|3|oFEDvTG)28QKwmBRow3;pE2KDzlR7#*eilZLMDVXL1aoO~7J}?scFSrE
z6z6-0^7t*|y#ovZFhWQ1AV=AfBJ}>@oWQ>mat3MK=WP^%Rz}0B#<VTC@+yeI<MA`_
z#l7YhKZ(fs*g>td&v^{{yAg64{3948velS}z!UZ@Y6z5Lg(DkC3SgE0W{kaQ2fafp
zNiZZM6JSOc!-|?nb@hWl*+PSPVsZb9b&}a@kb?;$MiS$}N{g!!gx;jL)mF?QmS(G$
zb6{rh<yR)_T)>!o7+&3jhIC1(rT4pR;e$x@?UxtoMfTGz<ihRq^YWbuiS^<rlM`!M
z){k8#Z;YanYC(MGZG)Bha+yU8>r4r7BPm0aK~S+c{06lSo^jw9L8Snjk4uA+LKzYA
zMDZR*v1;@lXmV>0xc(t}u|LO1_T+x&*MCQ_+6vi*MGN$HUdz?i>|OcWC12$r1vUHz
zd@<?Ki$wqEEpdAA+0+LnSRp-%RX<&Q6hpLMjC*GF{18Uu=`D$PbYCm~^5@#{1c!20
zGgezAthUZpn}oCMe2Q8M*g}C^#{I-tZC&O`HZ)tkW7M;kByR67?)CooO<{m|7TMRo
zzA~Lz{~b&VpPh}8XJ704SNu&X&%Wme<hK9y4l4>Kt%Gdp!5bq~f}s*D%a5h#nU?Ce
zY_`cOa5818swm+uDCpWq#1$zv)!xy;lL!+4l|{Mn&e%U4;{jwA<-d&_6E}iw5<Ul>
zw`0|`Z?+65VC>%2ID0OBEz0<Vi-8I298L>WZ0yA{&ZfA7e;@f(a!B46EkE|ZW5S|y
zvXNmx_}yzk_{X6qETKkNZRH7e?s`d|_zQd{!OpD#o<G%(CT-r~)+5mz*!rKi8$)4g
zbNw?f%Vhl+7RP@cO_Gw404-a0^DC0*_1~7{k(*$c%{b{l)?dwJ;_B2Btrjp`iJrwq
z@sSc7n<8OJ)xq)IBF77H3F;E2xSm?uP$WEoUk*k0ZLqNZ_yjtuSg*-?2(JfY3ro*P
z^rvQ_NXHZt$?b5eJCx=(;gQA`OeO$_9?@ZH50E8k|1G*g=lyuj!NknaciX|;466aO
zPkG`Hx|dhNaR&5`b{v-c6mLRBFk3S|Qtk}t%hlF=T4e%k<EN6yVsM5_B+F2Qe@{&9
zDnk=kwwvzOStn0Vxm@0vesU%2txd}ZrsT5IH~AS)q&nElqRVnf)(V;m)oR+vYi9K+
z5?K<qL@#m^?*tF)%rVE+9KVNp8i17&9lr*4ZWf&Yi2@j;j9$dA%W^FlNz#pkZ>}H2
zb5%3G0wf{53ixwMy#cg}cQLR7;l&<!v)TYGka;oS%a>%JG~3WtOPGRq-RKE!d#nH(
zim|ap(m5Dv%V^RP1{jK?)zAW~EL8a09BO`M`=x@F5kf<fT5d-ovFs`F8c<RjgJT!8
z%;Ohw95RXJwA^$tns7HC23?y_C&}SYmei0)*?CTNB#r@-KFDF@F=z_Fxgh{9W_Tp#
zZd4wVbcq@{hZ0ojffwxJ4TQyv=(E8ZBz_KND@+b5gg;iiVIa%3LBPd|7qW0F1B#U6
zWHe||cLuW&KsnGnVhV^;t#Sa0o)Xo8A4K{d`jUZnH`hTqtPjh4n#3MYL+tWKaYQ+d
zz6#s)(8yLW$QY!VPO)%~KG#6Y2oGHj6p|zI5ktVGAN5inJP&E7<JeH#kdjNhUGInD
zKS%iGXzZI^lnlz%&|Z!vc^a-DR-h@Gj~J|mhzr;isfrLS?oJ~+-K5G}^e~p3v~6(}
zRKEWk1vF6A!c}`qx(UoXw9ieTIUbeer>Z>ErW}c^*oM&IY?tkYtz%pF<pTCB!nyy}
z04KFT5Qq>dd+cUV+okS_Xl#pSsPJ?2WX0-nSNzICHs{cV3CW*5E!aZ<UH~3W%8}e<
zUI>PrZwG?=#a)M0)0%>6f!d#tcg3%1qH%T(=-4DS@9?&Wy>_JkMs?!Y!Vp7Plx0gA
z3LSMSbwSgUuy7gLWPTA!rhu*RT*9VlZz0$Khe)iphSNfS27%laXJcoNVwfk^e^@u%
z+6zi;My^zjmT*e+WJa^qGX=S0wY7*i0>}N>Fvu7)$$OJ69^8hFg54WUxj(f!m&)m1
z#e@V7{cHr*C&1m|w(ZLF$}nop(a}UvQILlCs*8E9rlKPXP*H$Fp#!UjSgL#qB)@^7
zMDJ~q`Fp4EVTmiFZ1Y>u5L;|b#8I^MpdM_whmq7j@&5gOVJj$+Y`fTIjKPs6r~g?L
z0TJCG%vLjpcv|RlZ-iwlH{odnV=~S6N{?yxVQG$u8(|7d-}Vk=@xcs53bUKSCSg2H
z`2k4m4h@a@;1{7%Sh!|VI8q-`2(V1Y${6rh*NYPQ7^X3x0(Yj5q4xtgq_h=)men3Z
z4|xg2SE;|`)<}*dtTKE6NsinGQHmrb1tOTf939XkmbS(DQ;^p^d06D_ug3fmbnFr9
zktm`18$p2qM8|ueeui6@f+i`?+H){xX11arkF7&~1PoAsVJGr~_*%+qk@Z{WUEIAd
z7WZ>$?2xV=pdVf3cRGOPiOQ2lW0{#dhow2Z+sgNLb1P%e^b=%@cUu(}t~cpSQ%pyt
zJ31mz1hvfLuFOF9T$DYt38Nk;nfvCdp)jHzC=qB48c=hRI)W=@<ey6R?rblq*TLq#
z#i{-+{s~!%@Ob5#CHB%&`vxI3t<fehwj(dW-n%VH?|}?!)>I!LM{|TliGu-98nBH;
zA4oh}1zv28bVaZC;p{8Jt-G*upU>FY7I3t)z657<0{VOuj{>eF(@32FO%JyI@~vr<
z<r&d3#qM|D6exOZbymK$FQzVHe*&_$g5t5$3KzAiQ21DMKN7=9*n04eIanR4OX}_v
zH<BnG(%VSHkcU*tLK_Mman6tULQ7^jV_ySfCInLg(l;tVHIs|sF9vjw$PaD8CAZL<
z1($huyLbi`N@0Oc8vX_YF@93qUs6B?Y=EJ1&l?r}Mv1X%2DF5E2w9z6N5Bx3j%ziZ
z#}cHgMDvoU9}yK(ZiuxR2V$+ESynB=a}Ca_4jQcVtSY|AhPOm*fbMX7ukc_+!R*=1
z$T^k@$_2l!AS=k3<9_0L2#E}*=c1zCu}3wlx<2iTh^17u0IR<Q-zy5L3>dk4`Ucqa
z#-7)0(8$s7mvJpc^9&g&QwD4w?By0%UW&9a_PHgCtRGk?EaS%C6;W7Jt+Ii4p^dL~
z9gHZ!326c}XW6ubklrRbTBfMbv~s;P4rgRMuH4gFyhv|h+b%`!>_#=z<+jktHVVVu
zy3_&B4{3QgW$A_tdFt3@pxs)zlrc?r+gae*8L&)Q77jmv+LafNU!aNT&?zyv0Z0yt
zi5_pj`@W-_vm0}s2r$1FE1Yjc?XL%pD((|Ee->Goc>)*x_#wQ~I>@=>CgCP3*eQe*
zTN6dyxEE|Ou|EuZbs64|9xe!TN%su&%h8hUYs=y|d*NrJXH1jJxaLm}Cm-W>kaw$i
z24}h_@;VnVyBGwcTgQ-W&56DZfuxCdTQh9%MXCVipt?pXr6Qn@pRl5ceD$)d)P~aU
z@KgNi!G&mFVhsuo)aX&hkgzL$xQz!7Ovh+^Ttd!Zn#<DzC@EMGF&iGg-Wm?T*!)rP
zdOz2#pG4OGHTL~&epV7iG!vzV&OPAit_6=+Tb7OBumf{oxsYYS7CT)qqjB(;1KSL5
zeZtg4jp7G9__fC4$ty+vZeKc`-sGa*9H@M|`A`F+?mmR4rs*k16~QK979R|lEWF!#
z9(l|6XlyjG%9voa)vp4@^5$@lzzh#hlT4W!Uq=^F{7m?Jaa_-Spj-|V^$7Gp859!H
zb_3>{l8n$YM9?bLzfxi}($j*}=I0>ly}t@e%V_Pw!y<kcYQ;xsgo}$kTW$T;XA}ME
z@l-t18Qb$AkMxfPMT|`^5W|WRW-Ead4ty6HdEsTTJcLOI$58IpwS`cywI$ty+F8-$
zNE9Uwho=8JD12fsW@Cxl0J`^Zp(oP9YAZM@a}wTd{gBu)Y_Ch2V5@(^cUz4u2#+Y;
zkrP>#T8Aijbe~<F(}fAgT&2Cw&ju7kG=lY%B`t~tK>uX-Z5PmPf`F1d4?FPqBuAEY
z@B&n^azG_MN30Y0O{4qL|7h7O62fe4q2FY_+9Zs0IQh}WoFt*x_$%_4P+^YQ00ZpS
z&AI=?R$JK-_dLvo*F#wE;;B{a+?LZkN}>%c<ET2rLl!zm9}rK^2`n=_x&Yo+Sa07K
zCCzR}<1KF3vfSc9W$DIV9Aoq?xSaYJoq!MTadvNU(cN%D;qHiO)^DIjYoU){gJ$Bw
z4%UhtG@Ce-gh%2M(t|D88aG!Yt4uLPKp!RzNOwKl1{=lQ^KRUs_M55bQk0QTf)&_1
zZ*E6WA!`nH1UpWulAjws2vtDvj=wsQIl+1*EI`VqVf);8{1+Ef=D8;Iaut_Xu5k{m
zwidvG<!WmpN5qZPhK?Jky2Re~PDFsWYoS!SUB_c<yoFX}hR!HjL69;SxSig7ijD&=
zj3}u3E*4E0*91wo#F*ApdhnpcTxqt#tBDz@fhO4^tU8+u?s{+wogOjxa;`~>rAzw%
z>w)(@Nl;kzK;1d~nBCaJA&2nmro3Jle2fYs^ze&2J}zg8Op~Di#c)ih99TneT)dSk
zOS9uL9IVn34$5jl8wp^xf`f7=GWLJ2y1XDVN1AkNZpWb&!Sy$)Ca3U}C86Y~8!Pl#
z2I>>P<gpr<`ax#vSVU6oPe7(+qL@%pUzccXT#-rz1Kkk{&@<bMb!CX$1s2yZ(Ckkj
z@(qYx!nkG^q}_uQ!B%&M)U7>~gF}SlVxje57K>2N61q@erPxGe!A*<h#|tG<gU@GX
z8;D@G{_)xy1L}4)TD=WX{{&0U_ldmf>;Zh+!pzn^iWj72M?1h*Ew<sgRj3P{AzU;F
z3OKnp!@AtO=$i|TD!*`cPSLQjLMnd{CsQ+;Wa<5wo90mgFfnKJlV$3LyP2(Axdqrs
z!gS;hp!8_#oP&oSfF#Y3?S~n%r+vwujAD-@1dUH$3SIvGLh!!0D>zdSWoj0T!*3qH
zMsQ5{8Eknt^YT^kK&OIB3e>n`03+n)_j-ZZDyxs6Et%Q+hDRl{PeL-fNR-Xe(*Q6k
z4%>sxza34j7d>eBMuE1@r9XthEq2m)20!y2h<HB2vL`f-7ihB{`_2fv!C2mAVlG~`
zWT-^11v6XE2R+S{M>1_;aE;YgyxTe}Cvy}cX~r=K@kl1V23zLML^ch1vLQ;T^_0S2
za|W-ULpX0bdkm!hH>?A<f?-<5j;TC;mHJDJO~y2ViN)2{n;$AxH<6;GpiEtrG403u
z@v!h&M<(4J6Ltvq<ENjUGxi}7RmKEOko`T%iAa3W+1@3EyJAb@<(~f~6Gx0{wG|tC
z`6997d$Ibp{}zK87d_Jbb&P(n+Dgnu(7it;GdBMLTJn2ewFJRzy$5qL9}@SYi~!BR
z_RNt^TeFqI$D12*w#jYfR6%!TB4N8|2Sgkx!QkB`ad<ZE60sxbPw{mj``X=(nBf4}
zkLax8K8~e<-FOFN$D6E)d~O)0&1x(0^)0MV1X`!}nrm=D-H{be=n!(SHM8{$8Vk%;
zZzk{e_QYxTx;RsQL-(i|MTT8}S&lue(;3V~;yr<m;+nv0-HP#Ut4BnNh#ae}80>)U
zOz5+LR0}LagT$?;&%`GqzXES0zqC+<|5v=tx8R+^NHxG%DL9<C;Ha+HAXK?)9c8gv
zg)WP*OktXuD}B6M2p!SwyoND&wY|o+q=xW@t4BP4)-~`Bu%j?NYLPc@aZ&T({TeqM
zTIY6npdN~c5>$DtOLf6<5VSSqLz>$?Q5V6EQPi*&YTiUv7*;?B-c|!Owm^d7*XN@e
z_aVSg$evmjbO<9?QxFS35#Mpfyf=g7Q%H-(s!6N7A`2?O^rYM4r2ytlBS#~3!G_@n
zVEw3)=(OU}4m=bz56SuL$9YnkfEKK5US2}*O|&*EgxK}0XRiWwbvT6bDVF22Ffl!X
z$A}E=A~8KMya_5q&yTKv<S6K<SI)xE2akcJ#W;Ye(zxS;sTkrKuHhspAh9xZ#cGGC
zoe>!mGh(u&nGdQK<C+1*$pswT0;QFr8a1bUi7`rzK0c(kaV#{b0nw&ns)3Fwv`Dv9
z+{fOkw>rjRn0AXbLn3WwAzpHZ-;C1mbU0qxK$%}o6$oFeFqmi6Dx(nLE!0OBP^?yz
zmMnK__i%|yvO{6*ox3I8Eo@hcFkADrH|nl&gFt^7w0j@?=V^~U0qVVzYe#vu@PN_D
z!YCP}8tV#0)yY={qmuyz!{=Krzfgu<1<yGIE5B#|2Tr)8D{gKsi#YqdjMtglnypFB
zFOd>xo$8!9F{SS!n5|(L)tmIm70a<=kd|<@73(l;z`Fr6;PCVK8KlX{2sP!#jWR%<
z@vo@dFVaDIm1#?ML)vEW?%)`V)z<XPH3I=F3Q(IhNKdTazRJs4EU)O_?@7hqjz<Q*
za__(V@y@z3+7g|aNHQ2cjbI%hOXo@tT3g}qQ?Y$DM#6Xgg2bM5!Y1K`!hWPVbnXF>
zKf<>D6t61xo&gHXR$?|n@~b!r%k;zz$490G!+_<5lNU*JDay`{o9gaSe7+u(!1nf&
zUF5d=GB;4^utHMQGB>RC%)xB^#NpS8?K||;=R0rbpuPowmLH~7Bnd-7PaiNsokT5f
z1S3^!685e@FDWSfm9jaR^zMUE^jw73Gu)G%P5F^mW6$_E9K=WVEzx;6;AsTgfK4n?
zKV^^Tf#CVd#fg03&7m!fuC_jNCGu7>ndxI^88!(^TeDSOgSk&?#VQgv2?NY*#U^22
zE$M=$nzhUi;Iv$A6=uKtl~mTg&DjgozV1qt$QLhScncV=FGh=L)P&uZ+HdoZ_wwC>
zY_FY&Fdj)VMJ5kOf88E>cX+g@MR{Ze=iUqeW~&Z-<6J(R{a!`q+p6>vh}rrv4e_*=
ztJPNP5y2$DJU0m|N5axCg6eONl<%aS1K!b2sP`w}eiTJeF#%0y*7DZ0({i=7o^XiO
zdG*qJ2kI(~ahk3D*tJQxD^4+N*dB*|r4d+32yR}SIqEJIhP%5!V?QK^hSNYhCC%aB
zZEhwrpkjePJDdh24194HI&9>@u7&7U91c}6#pWBrL((R*z9VynPWDF2e8pu&v}z^{
z3J7P*+2LW-@orZLvdNctCT@#B^F_n3PKJnV4!OrU%cMR>(Gsc0%dXH3JtpE5se<ko
z!K16e%|snns)N3<;Dw8-CB%s@op#4(Lk?Hvj*w(kVYZ@+V9m!Xk3|FUFk8dv{;w~^
z86h*q!zVukPF$}*nDl(7hq(e1dlHmYg!ya%RafI+bV2aLGwVz>=`C$L8bEc1zVlMn
zL1h#KltzlLDi9s+_NCy^D~Zxi3XTqvVT7k@=fDLeGAYyRiV#4-HdcD(mUep_FlGqI
zmNVmyVLV2#C}O3b9e}3;3poW_gish*gpo3a!Z<o88Pkq7Gsf%!n;@eMC#@Baw4B`l
z(B4uyZo?1rAZVW;irjLm0~r);j_DkJ#x^Jf9#EwWA^RRU4gt6zY`vhufI6ULMyQ}A
zI>7dHj)YT;dN>dW5V6<675O6sO~Jtkho41o0nJZh4m@V6$WgtR2*)W^qinr20oYPd
zQtyk$3Rzh6F}Bn2CwUS%0Z<-eYmF413=1n7L+jjT+2?|6<ebbamD~g$;M@M*{)Ftq
zaUNjO#qyPw5gt*2Es;StcHvc8CH-v*5ugB&B<O4!_%lcZ$?!o%<cFU(Y6g?6unbFD
zWvZM6_*Tks{IpXB*WI@YM2s#`JdlEOMu3U}BeodAh&%Diaqyi?F&`HxKie~fbbg3!
zk^`v;w!n76CwL=Yuq21eMQWKhwiBMpn1p8L16wl5nb|4j6hely@Sp<*ibE*0ey4bN
zn*bGZMc&FRpl1SdU&12oUbq?IV+e3S@J=2%En|5|$rh;T?g}}I*b%KmP1)p?s3%(y
z4luvO%_k>>GByDuJ0aeU(rQXHKHi%)$H$L}VU;z=aMj=}uB`~RV(Uw~WMWXY6#Cda
zJss_#B7~<XXjQpD*|GST6J=<KsIY^#JsV1Pfl%?fz;t8K{cu$(J#}I+E~idyP+`j0
zMmkPb8;jPn$8uFd;_tEm<45#Kq-r*wj4NwweK#>G;@cdKL`^`5;8m3Iq&v_oF=p`8
zb$o^Rt=<rLX$6#JnV8g6av_qfFx58j^iwjWgMvBJKYeuo!_6_C8O3G;@$>)+3guI#
zh@g}!yhIS%$|k{dic>#e>k-}z*hBAFJvilx4K7Hol%Qby3}%foe5DUKo}nCsW!fWp
zEI5Q3;ZL)H;qj_O(Nw16TZvf@T|~zic4Zz8(pop=Q+Rxh)g?IR0WmlWJ+P$?s8SnP
z(c{d63yaLt6XQ3k^%VvK48_9{hhz*J4<;F+M`+<`-~yX%2`NiUP>k-^>hXIZ)dMHW
zfX1aB_bVeOy+t?*U?YZpn!#E-(IWitXxRp_l2?U<91a14Q8-B1!}d?j<Q^%i#SqdM
zr-rg%Y+jrr1@5lLK`Q~nKQE-&qmK)K2x$q?GO}}OLOkx`e5enhgc~VP4Xg@75L3}Q
z6ma2AZvAS8HxY{hgkh8=aJW|LH!34VU^o|kIfz4WY^GyOQiaM_FyxFaK7rxYhHD?#
z+jM8?QAvit_9Rt)Z~3jfHI76U#ban5>L5RI<cPi5hJazVK?K1T_0004{W)NNV^ELb
z+XWVW6@l0q;<m`Yk6kZv)hd=&maOjx#oasNc30eXdirq-ae@_}@O_M7jCqI8?Un&2
zP!c(2R`m)6H^lUgpcZdpIPAe5M+vE18!KgM1V4Q!ksOCz01{iB0fBtl$MSZBbT3uB
zBnP{d#}nB$oMl!U9x_u0o{@>Z`w-T8ZiX(dbsO^U_ohkuBZ*^FLvo@Rjx$$vv7%w$
z0iYOcGKya-P+;jC`l0U6zz8fPs3?%M!_U}$^$d=yd>)>^?gH-}m@_|pe7|fxxG%n&
zY-uvsnV%kx21v@yd@1&(#hA<YOi;0%?vd@w!V8t@_mH<OG)C?}oU#3f_>AKta|)D>
zJb*2eviJS$kz2sVN<oVPb5kK$y1QPBxyLy~ob2FmudDHRA<gtdQFs-v`g$bk7YcEv
z5H@_zP*6*=FCzP&*|!qk`U|e>{sCuhJ$Cg54*@$)j3&S|4^B5B7A2!1j00}2beG&5
z9Zleg@IT`m!Ot#7Ug-fa;Q}4t;mJekS-%Sn<zckO|LN*P^sf@xxaY*CxSvM(QmIU|
zbOI?%C?*&W$s)_ia?p?CRqoUSl!D782V>d%jE|L})yBl?wK;ALeD}*S)OrYOb&sO8
zCT}d2zyvjr98SGsd~t*eop|q2<hxL*y#Poiq$%sz(Q1oBw(Svkp2#LL?n+Nl#)Isi
zeqmoC?|fMpr0dr&!|8`m8Bv>n9e<FlROR>-#ApS_4hv5Bt1O0*G=sX4zkCzN^?>Nt
zpjMdA=)QhJ&c;77jDBp`Q|CTcMLK*lWmM9xT<-kSuP6h{jfvGl&KabgzfAmsJ0#Kb
zDwlh7$ZcS1eog~kZtuc{ylsKe@k!_vS+WDf<au>bK8?b=-pNeP+_r=06e#+M1xNH`
zWuZj{C*}nLt5zFe?s!P47RbK1kKFofh7LjVPyk0slh0u^ihGzhWf&ozZJC!6&8wvw
zy`(WFk-9}#z(i&SHOxdnv=%6?xHsPp?N$T$oF?$StJHDO(8teHfAjb?K$#PngNiVS
z+e~t#fQaibeqVa<%_M{7pe~h;*HXTL`i3dwl@jq7?S>*&sM^QF!s9h!WT+9)6asX7
z;=p%%8u)#QqSa6vp%~Bv@jUPLxj@M=zA9xe6OFxd(h=ZFlPErj=S|L_Nzbc9t{iH{
ztg}Ocm~YHwK7>biBQKsKE(2DKe{`tI5h~P(XCK!=&mw(+Qk4sy9aS|@M5foY$xBce
z(8&|DDiZJl5)BOoIyIq2NKPtZ4IE8Od!141WiRk~s}OV9D7niAWT~)Ah*Ho*h#O(d
zxO#vvkt7>z{E8n==Vic)2De+vOB)ILG8vA+fwL(Oj_7uQv<0BOpDNwxliPrY3QIu4
z@N^HSq!`nX$B&c8g$OLW*wDQX{7N3U>);K(E_RnL*EcG0K=2;SL10{8_8dNiW~LSg
z@fYUOQLR*o+h&y;@a~Vk(Rc)>13|vg0MiaUaH_nVK%S?EMii-HP}zzt5dri3c;W;{
zCnN9%FnFpAIf1&LABOKL{LbOyK`THvWowF~K-uBJY{j)1yj&!qO3)U4IP|^wv|BN=
z)$G};FeeF`3Cvb|6%U4Ns|*?Q_dF))?6q-tDxLnMWccElZx(BJ3~#-sC8x~Px#A~|
zmj+PA-wu-#W^2_!RTL70Is8nE>54@8n^3I$%0ef+?G(!`CypehDod2VtyQu1V75l~
zt#FvFGtphIW#WP0kDQRm{T39D|DlsWc-jli)*CK~Za2xYP83Yc_h+jl&<N>|tM|lW
z7HGB-DznvWE<~)sY)xRchF9^3Iz}N#>`9^0`szNn{M_%0a|oQc>oxtE<#(+tF%ylz
zs<S|>l2)0*(LoZ#@c6X?Ppl7OTK(Yb<4_skuPBr}lvro}{*d&ah2zgKR8)Qw@dGC|
zGj~0B7HoaFFO=xDuuRhv)OF@OE_rCW#umEuuf?8KzHX_cLHn_?DD71@xi;j!+eb70
zzyWdJncZM9H^So&{Z6s6VP@+QitUX%j<|7$&f&4h2+|B@D^GiAXSQO+LykX}?^%m~
z4DUT=-#f6j{?n6oes!Z%hCulpU4<&?+#N7jZ3)NlnQ=d76{RMHLUO%JmS^tYi-mN2
z6Okum#XQlo1lyxG!SO-^XmqB;fT0_2MOt`gxXUj)xf=Oz{k98X)<c&TrEybd6;DO?
z-g5Etc;~zCEuf$={>DuU1bY`ww(N|E)V7izpHvUCRk_=+BhTZdX|ly@b4g3Hl?_0X
zzn;+>+<nO;PkV`O4~M%O$A8p|hIv=E5^OnWo<hca1<MxT?1~aGM+mc^g(9NyriP)M
z#Nz54ZN&gqE4aO>V#4ZFL?Y0mw~FXRaN-IFwb}|?fra@7xWY4?D|`mLX>j6NwF-=a
z+JXn7hhTnPdGJB|gh=;Nfe$-Jtft54`|9cD$fsq0Le|PWAH?FNdX&qBfCriK#7|hE
zA~?Ejxg-FU0H&?y@aCp^@vMWJ!(KGhGOgg_*`6k5j$bGsIO<{EqGx!3rB+fq&C67b
zu<Fg+%488tAse7;@wy6KByvBVFcsWhxh~k@E;t1f_(Us#kx8pt%82n0_lvloMkjZT
z;7;b1u13N~JU%&yHSz+0j{|cISfVaC*;!VN1%VKglCFd>jSiwo0|jg1Gz@zp8^el3
z#5l-Y6_XD&%$|5NTc=n{P(?!JLU&y0r%G1i(8-*!2R3;HIQ*W_Ptn-`ig>pZXP|<e
zapOY@;ejxV-@rF61x;HwlF^$Tafi8E00YOvHb#CNW>glHc7b9Yg<V1sGu4U;%Y%_4
zVlilU7)*#kih`P94y8{5O$HC=Y<Gggp$-GRLxb|kqhSWah`YLVduX&hz=}wB2JgTN
z+UU<=IQ|W;A=Sb!!OZR^>dk(X*8%;iPvW#tOoEoswKGymU){YhTZ>74n!rO!&IO`B
zQzqwVDQ5}4H|q1<ysl)ZU&oNgnT^Cg+#*-R0~yL>yWVGgp_KPV3bR!WX&;7Av~{|C
zbK@$kkil%7vT6Til6|is?SAnL9`Mc{gZJ9EI)>tHjm-P+qX#At5zh-bu!e2Y(+GGj
zs)&Am2{ytFjb`hezl7n+ov)OI_(o)(!~TDF4s2n*yMpbC9!my!9Lqid&-`_v9AUO%
z=OveDg5XNW2i)d~{#|guMwRq?F;-jOhP=^!Jdd;y%(3L7+418mNXnJb<y)EO2JnbK
z_|>S;)77x(-cD6zvijrYYU@SVQg)*htF0f2OS83RlW+>Eo?2I!M525(>GmI#)WH)y
z`#DLMe{u=V2Jnbyz2=>?DAo$y1jh^OVu9h`!GJnYknlwK;AGr|*%~W7fbBe>T)_H=
z6LDX-NaX3OL^rrXx=t(b*jp>M&Yy_ABW@iS+mjt<Ip``!JXaFmk?kT~hmo&SKe|w`
z9Wh%!0+9=oS5AEkX+Llv^UuvPX#>nd?bkUU^u&sE2FIHsO<}gG;M*EjTNBa@FTDMF
zk~pI7t`Jlx@5q&8fa0I?9lWD|nP$JYA;}sv<P*H}*9eeIKua7k3tDu(XwZ=I7`iw=
zXTsNz%4vf<xQ5C!F&8?|?sckbcTu7MJoZJeDSfr~Gi7X_Yw&yr+Hw{y9C7DI3XGfs
zDt5#ptF7>B-o+K0HT)LtZNOCnCU)vu#Yk-nnmj%!YE1HudeXGhXJEGKr1k%8sDr{c
zB}wwj<4jS=IPFDlNk1L8N_qiEtYS^DOoW5b4EhjtP1uIe<p};RphDoxx|`u-H%0bN
z@Nm#hw`WjM8~m!mz^l!?p&L7<Gr&ZSM=eV=c>CejeC_T<X4xc`hAMHIqj!)AG#67@
zj~Gw~{#rqi5yOpVA=C<|>m2;B-r7$I1zv3mEntql`q1Pp9%ie+UjsQ`)kr)(KrE>A
z&<=FbMd9d5nMgwhYl{fD9w`T=C+KiKVmMJx9^zD73E(s7ISohhV1`CkVmp3*eEAuZ
zr9>ZhAJV=f&T2HkJPT(ZKYWm34d43>5q^zUSXT}O@2*#l<c2`q7G*(&%WlC5BVg%=
zV#hg$Bs(x9)Hw7D3D+nKPq>;y)6jmOro@7^69-g}D!#W$qR_+1$~WE-wp1`ajk<!F
z(@{8L1(>CS>_U5Maft*bbo+TIFP>HgFMD2FKv>8t<{ON!XR4lYEYk;?@O7M>FH?p$
z-7~1;2_WeMkyBJv{tuZ6P09I;dno|TpoF_245g@n2;J6%IN$-Ez~|ph>+{1YNHE)0
zfrsOR8=s#Z4m1j|Sac|GHbH=|0xBlRx!aH66hA~SON<T#jjN4DOw9+7sseLs@H$&*
z^@R#7YmBH@Nk}?$_5C!G#c3p;IV8C=@rI(uIL9&>DxfN<j>RrfpcBISDpy<21W(O%
zDN6XlVE9}%);~2q0qp60fefxbd?c)iFY#fvvS<LEWKv#NsnLS`#o5HbY`qs@)oAG)
zQelH}CVzm?^_k38TRYx0@f2}JnstJWo!{wr*xVwoLt>h(7#pqYXR)0C{m)*xH%{Z_
z*mIE=mv*p;*X86??9;D*yes`nu>JePg9pY~5^nbxZ?zZKK!QcA^t1sb?hSZab?-$B
zER<7Gptc>!FyhV+?H8J@a@!BXd&O%Hz@kjC+KN(QL0KX!q7uCcbS>Y<S79&$m79VI
z40px$JKsg!xeFmA#@)L9<VAP^{SSe{)z%yqNAi}$tjbNAt@C*+t{5Bs_yWtwC8SlZ
zw$gy%CgEGRZjza2u5{gEld$%BbD$evo#NqNsB}ajMVC=!e|dd%--P_Zzf%ADe~<Sy
zUOgoTm*0^sB5gBlr-c;GQrXq?0I%ndmj;MD5&pPS>}!Rag74s=2$bnJW8UEluQsz)
zboxfLmisnO-Tf>&UFO~rJ$SXu61M?RPDm9)^sYwwoE(EQu)T$j-^P0yr|v2>i6t&u
zZ8iJxL)dSy71C<<_cuv?&jC4{{C@11t`U;0psjiC1-{i*Tf=_!BY0h*V#3u{wN1iU
zZAGWLyF$FF%8_S*^7!Ik?U9vF9_z1nzvKEFh}f8ZbN?tY8o{<g6RTu5Higx(v9XBA
zNrJEyg;$5^X6ft>{>ShLdoadZ!!%n@pj5iI;>GZ*4zVV%i~z@E!SP-PV5>YFG*lqB
zH`-gx{f1=NgaP5Y!82(Grm(k1AIbAWvx##dMjpEsB+f|cJs<f^U^5=+8qt=mQ_rW>
z(!jjL;nP0HBPA@u!fZ{m96cD!){rg38@h}rscOnD`Chg^IgSBe)QvfibcaF352f4P
zX_BGKXbGn78eCV!si*i&_*gDs3TT1#!DEckM}Ur01)H}a)_8E1ri|BU6`V)(R7RC|
z$fYqPbPP~1&w3QKQfG#kS^`WL3aIOfEQAjvScH(+0GKy|1FH)IkI(P&$(-a^L!M>Y
zW~qop-IrH$)?eBY4K!BjNm(q`R%y1HVz5ul@}J`kCo5%RHr=WVMx(gc-WVlS$1fl3
zHxdI8yzqp9ZU_Knm^41D(KwNdHS94(IY%^GX@ito{RSj<b3s@OcDN>wnf&yt<h-#I
zs?}Eb5(V1}0jvWjmJuAgfP4Y)d5}Y`DCDiMh;&deZBh$9^~3SYZrFDrZWeS-3k`aB
zyfLB291IW>n^$PS&ZNhUu6UT<7MK+HFm@YK?ucHBt8y&N)*UECz{To<tK%A4hA&bu
z``+qI4;lM}M4O1vwJvJy0Hwm+)qyD)JY?Ep?@D42*c&XLHsoNCrrxzNm^K)X=nzGI
z8jr_eOwN)BYeJ|628w5vK~tqI(8k;jVPokS@CZj$8h{R*+gyy{k1#zKj3>doj^$1n
z+8QQjCos{7k=*wUag^e{s6Ym9yil5!PlN5OufoLM9WXRF`e=kTVD!+~{E>wQ+`Qvy
zHllc023JKoc`l@wm;Yx~C^>&Ca-uBr5WD*o^RocuCEvUOwWXlNfKk9`XIk!646X3p
z;NcB;qiCZ(^uY2F%$Mm=iDcpJX|ln3>x}6r=60V$K>T50hIXpY6PrX>I*MO2Oi85o
zqta6;H*ir3|05I_;Yf$<D5b~GP_~8KD0=cqusxHcIZ<k1N+urZ?#bl2>xQT!MJ0H}
z_6Ob)$(iF5@zT~|u)Psh*m)Q7_Ah@Z@eXMcNTz$SSl0*&3}#`0m^a<HAp6gU_CB09
zI}NcgTT%CDwm$P7JpGYGnXZy-IFTvj;Db=+TRsl6=|(*BGi)H5-N2x-x5#9T;J^7%
zCkq}!(o+9r5=X}fw=!nz9VGk@qRYUEpDQP?aBEs%juhbTSu)frle8%R<g-{SExvg&
zmZL?0?JZk)TK>&1V>35Gj27-Y*yi~jyb=ConeF}7#TXs|<uvw2c--aRVxv9Nt^>u*
z-OZo|aEPx2Ha&fW<A9zbJVFHDp2kLS^n!f1b<K_!<-w=5tF1z+LF*rcWdHn9Nq_sF
zZXU&VVX@Z#s62)l#Aa|nx#vwH{c~>}l;GH8%ylhzWFx*0Ibx64d%b8ac3otShyB)c
z)=whzL`?v;wij5w{I(|4El8Mm5-+a_MUrjeqcR4)UkUdVC_Za54jy@0BJp(Cxf96P
z^<H%6Hc9!s%x1Kf^?FbKLnt-QP3_6w0)O*m67?|0f%Az|jEH+RNs1^;F-E5@ns}Fd
zgw?ANTHt6Pl1cyjDAYm_@6wKZ$`yLAmChH(LbQ-@9-Z?-q>0Tm3Z7N#XhDisA+6T-
zi${V@)7P>Tw<Fr6OGOxIfssJ=p;aSPc3M)(;3k-YWbXnJ#GJ=NT)jtH=@tvPO{o#T
zNu0>x(f~YruNJgGfO0n=xo^?ZcBkj$kURkj%zm#$QI%9|cBS;}dQb7FHdE4iT%b5N
zN5q~~llzYT7LYDhNE@gb2Bn6qim(&`dAVp84n75Uiw%)uuNpaz$o;b*>EMWvw@wT`
z)JYr2He(!bQVP~4#W)-na^(@P5XQterHxBa7k(Cx#(v^ksK9|tP~lJw*fl>GcldjN
z9d~*u$PevB?7}k&jf{s&2mPw%qv<Q3muU^2m5!tJ-x{6(rbC{lzJ#*${IyFu$h)>k
z0NGoBSGE}_W&BqLT2Qe^A4^GHE9`*u_5tot30Hw0<P;_(pEz*WscBOj5$a%xiXMVd
z-ynk3hdY1_Hs=aQn;VPAMS^264O`PysHNxw8q?njjK)cP;AkTyZVP@SOv#D-d?Wf;
zguv-x%o=<|+{#$AGJ<-;ND<(8G4REG^wzr>ofuw2oxwoHV}yf|RxGd4J+Nx<LLI@$
z>u|j{UJshIu-z{@2sUSeHG&-@l*kTXg4r6|ZZ&*c<0+V}?b?UnX~CN3P?lR0QF<K4
zPAqFh84tMca4AC8eiAd4DG6)?Pe1Dm8lDxY;$9D!6jA6SMq`lQdKQ;LHzfsOgu@RJ
zYMr2`hfECB>NVULB80`uuYK)hqx&9+xdXsO`Av&k@2aR9@f~clKb_8Cw(gI6_rjix
zZ^RV;`9x^-#Oq&iL9$h>@AB2iMj-W4;K=m!-FSnkAWjuwJCSL&Ch12oZ8?Xh08WCk
z(U}r=NFkOeOumAe?aB)%y*XRq>;C79)0O$<%rjjrKr%i3e?^hM6r0aYvLSRw_lSr?
zk-IxVV(EE^N>XR9h*z{gD|27*u!!L-=_*kfGEWChJM6iY-lz78XFvla{weVMn_ph5
z>L3&BV4Gtrc|7f4&@B~TRh;)yY!bdY)ZcZao1=-@3MlYX&qngZ$DR}|DuXhm<&E<(
z$ca8(zT0|~@3zvA-67c^5mOgh_xwhtOkRoYPr4`5|9di)@B9M=Yyn?Do$bd9cFM&3
zR9ymA&w9XW*!q28B;ow)12N{{LLthLovrD3X5#wI=Es93Q6}&9_&!pnX*{y^D)i|u
z!1`M<ku;XGhr;)VLMI*+zHAG!O+rH*mc!L=0rSgy*4B1R3gX??m^qQ>9mc~j3-o$u
z!wlIb;ufzc(@F7f@|e7W`=dD3@`Zg?=8efG`#+mb;k<-K#88<V(b!M{dMMmq>~#(a
zy~BmG%*}9HQNx*Hcc|*5L(zG(q7n_AF}S3%Q3izj{HV9y2MRV~*I~4Iv|lV2CKl$a
z7*vHqM^#X*BOogY*hHXdr8Y$o$sDszH9-)t7Aw{=+Lw+ObMGRNvZl2)eDU5RbFtjW
z%ytHks5OQ1@mb)}ly1~p@5>V#+i2uQ@i1gXh&PkQ=Ny$H1gI_a7@kE?fk$#r0jUkv
zhdX(11<a+k!fc1s3uwwrT`;VaDRNBDB$IjHmjShRC=8ijti=hD5$eh!YccJ|JcNZY
zC-v}sK#sJmTP0ZOfr-krdg(E^<AxDR#M-;!IgOkhuSMD|(#}#}-!0}vh51N>esFT+
z_W_>Olhw4fB8a>zn0`ZyMviTov$@ycHxHdHnPmiz;%BgZuD1-|es^Vn(g9kdj~-+|
z$+~L|4UU``L&Ct@1j;e<>@v{OJ}#ckeQZ7vHv}G>TIo)Q5{+?g(rgXz;n0naL97i9
zBw)5)ckqZDY?Y1Pq?_L{WZBNd^(RtY^ox4=xn;c1if=ROyPb4ww8S}hgHJ;lCuT43
z0ca`DX`nE2y$Y&@*@_K#&Q@EW+P)r8>T4ub@Jt8{BHh5iXLe{}c^AYTLH>bX;yhz_
zM}&9=vB9y(6~DYj07M5^Uq{^}qI(vXqMnu%LIe>R!Q%4x8IzF^OhcI2s`)o0=`(c`
z*pb7}eL*5e%yDe>Rj&YBuhO%f$Tv!K^otT{{x&SfeMN+6)77h`$JN#)5^92xEO5gy
zVKi^pBpX&+zb9d}6`O=BmDVUE=nTf#b&ir@MgVlR+{a;zYA)$%?6=M{j0DRPERjKN
zRK$0bF*Wz-mLCLneqV9(3av()qq#?NB?&8hI;aPwqY4RTYe(*X<af*2UdE3HZ1nZf
z|M>3)b&#k#*oM{Cqe*nbvme9GFMJ*1{BcyRt&ZbC&OzBZ`sC!ucupfRmB7pbzx)VL
z{A@mEXp`_8P;Y(+jpx@f1Z3WJNXA6W{z1nwG-?RQ7djgK2Q1;(hc2=I8?$4fB@n$9
zu5?kihwgu(q%{sZljf@8dvYH{?%@&8!%15&8gdM2wxEKw>)R4Jhqn%&2rDEtT(=^5
zcm7kd5^>v$;FG!fZx(Sj9^BRuGY}}W3syoO!jRTrM5_`DFVG?<GxlyP%+_ga5=L1e
zZ;hbLcVAZUiqicV*0PxJqp0GoR$GmFib~5tVKcC9wuGb)#1fx5eG%XtG8eb9s6pM4
zgRfYzaCQM|%Vn@AS&NCB3xYB*a)#{-Lio(!g@fCkgxq`?=-92=48|DQO2i#^3<Fer
zsIzWkNA&IinV@m6?jAQ1>PLLLdvrLs)bWL815bKinyuRNW$hRyJ>sVJlt(KSk7-6S
zY!}E-j;Jl@O~{0TfxH%F8Soi+65+vjA=hn5CgHc0-KvU^?S%nVxX#{#GZB5JZLLi9
zt!<DGH6eM^rII<oErffkYnAgAqVv%3968a+9Ihs|1B3+F^?+Gs^sf*u?0I5~waVuZ
zHj;Y8Q%@7IXo$KK2}}qF`95`zu8!xm6`YlM%eMw>Yw6D1rlAm8ceQLq-8z)^aSpZo
z))IZ}w%HP4%w0oxCJu9|R9O@FqU4*)!ap{NYG1)LW|xM%RX8fu1;T7p<kk--By9>;
z$Oq-L1!e_}yWCP`uNp*s)V<a%9+Q;K)9K*SJYoV@TWvjtN63fM#@0PPiyVBI*@_P&
zwJ27Z;D{%`BGU0B8IyNB_6B3fawm>mf&KWD9D|mSHj+Q!R1Q(NzH@MOTidm$noIU2
z6yQ105tQ2_ouZM-lZ5#JoCR(Y?(1j$2v+48$>-zAlT*<(*k2MV-S<F2r|DkvRf1Z_
z6^M18+==2DL_%bz_&JA56P$$E8uLZb?z2EGDrreU5`;ODU<B3Z@e9pmGz5n<o$O)_
z^)G?XL``5vGTnQrI!8>>0_<e_10Th5-*Fe`*Bu61?7sc8Z@GkNA#x!Z&jC(vZMPaY
z$U^5bhm~6wIzF(rygi8lU;LX;-d<EByi%L>o<S6iznzjnWJ~RVL4|1cpYTxiNxI1F
z_n){ZNxyhWD)TF?8Xzj>QeSe9uQ!z?NV){a3l&tUzm0wup9i5}woWaqA~nfY6iOb7
zKp83HogrsFE7E&p!ZbznI`9iy(A?oy4Ji!hC0i}o=C@y#$-PIV-+dN`V1aaICkZ31
zj+m_v{au@m2^^{{&=#E<n5`DkJqGPD!ajh5dXw1)aE4b~_m`3>b5~I-wZ7PUrNn>z
z%S*C?4rLt}*$s|}E#M1Idi}4za!`Wf(~w&eV6_#cF{!TiC99LJDZ$wIE%b(ZeG+kg
zr5VlvWwYo<$7A1)EaW%MqW_KIdO6-Cz5>Hbre!B?utgNCb6*H(SX9M<VZ*8X=P-Ma
zqq@Otg;MrOtk(l!XtkA%whog1lEimTfNZQ*Nu{;f>SaUZ4px*Vz@Wbopc6ut_U-<C
zUCeBiUK_UHL(WZV0*af*mM`EsHf3whxVS=R)?hq6$vmQ)z_YCtfa+Iu{vimHxh^Md
zg3fch?*#(nxG4t@#lOdev`lU|8-Xu(ur@UV*tCLH#F{86^)xN3%v3Xk)z+$X#xFAX
z9IA;YbB8K0Bc~!KP(S(?Su!TbBKaO{Q9;mhED0~Jat$2uq-tfh8o~^QXMn~&g-DmO
zC?Q%RvcUqPRL0O8^fZ98GTjB6rRbSB#t->ax@+Na#8M&1&(M<s?t(%fks!d~2T?OC
z2oF6nBu0oeoXDmi9s((9zY#tU42PeRO(H%}hr3{l9;}K$&>B1@C2;xA{cvPGBr-is
z;9)>mDq5w=!Xi6><K<fXrk6#$M}%iclsRK-9-;;r;HX3<+d}J<YY2rN$IAst#@u<5
zEF>!lY%f`c*8s8+<V8N?m7pe|dnO4H0tEmlw4<ZU$o3HI3SiZy=7wdWcPEgo%lJjp
z31w_h$u4Z~@xEY-24H!MumkoDKIRN?tSo-+Htz=^NvZ}mlR#_Ycqa48vb)Y0S9zO2
zxupsUi7HU%kXwgZt1k8es8@&yI^`9Tc~RQF3DP(wY=l!2KwKOs*AJ)Q7~&{?d4x-=
zF@$1xKtvQMinWiACc^=!C>)1}NEWe$yOc~uL+-?|FULDEm~Cn?UQ%>e2Q&iPEUu`7
z_D;4lpz9-Od#azBlwgAIJ^=R=RHsxlSJ1ccYld!txHrGtHlp~L*$a8=VcV$e^>4z0
zJq`(&SBD2WIFQpas$gEKbi6{elg7~{8fV8PQH7c&smv|>n!zN)j>CN_NmYW)$;M(#
zgc!#gCI3ePux(eB*+6#!(;86Z-BAjJk=yNskCg$?Ra99z3h<~f){ABq;EQ1EdP{fH
zy<M($Q1K%8f9W97l9m&3p=9BDk<h+kcygc?9UTU)xNo~b$GTR8^*tO8Kfa3K%JOV!
z?uT}b#5gwBt{@B&6oTOCn4`<#$0nnS%MyNVVYbXa?<L)~iO1u4Mv)w=o8rgbvmR(^
z5+ilU7#)RVB?U<k=E?{v($ixy6LlzLFBZ#sqFy?VD77%{p|m*0>w-hnkzyy?7!q)6
zf_JNA%kguMQZoD?gn5RcTm*2n3@tJTDh2Mb_&B<CAi(rRPT~-OUKi{2oY`jlDo~@=
zn<J2@gg7XZ3>zUQ1`_xf`o?{T3}Z%Nz+yCfyU&pjX!`Z-F>U>xh^$1I*Gv@mMmT5~
z%`3CXn&Q!#Osk*jF$qL9X>;yMi1FkN;M#S@P}&es;O%e^0-`R4FN(5`rnRjONyjT{
z2-Bgq<`HtJ3~dX&Ruur$SoBSxqRw;K6XQ1@blsGsHeUC(+*DgjWe^!1z>sKzi_(>X
z%UrF|xGEw0lYzSo+i}+&Av*#<+*O>c0u{rL9hf@;oXq36C?rliDva}}X&Y$sZI#MW
z^$R<w?g&WA{O^bv3h?&2-#HlkU!zg_A|XD3gwvO%X|G)!-N0lZHs<kcgL*iI%$|Xc
z@|&PCGU;}ZhM#f7#8a}hZ&l@bw5a|CN&Y(Hnc?*k&@nKT%F#!0XxIt#xH^Z>Ekt4=
zC;tE1yZ@L;(z`(H)jd74?~ccIue~;7V@%C@aRvj&fH||iSh!}rn04@l0nD8_A@YJ8
z!zujX;8WsL9C&6uHp_(^%MYD47v#K02w70jZFHx|Cq+t!AChzO5hntPlQ?M{A&x&z
zWa5iX8xGifzfX15+x`CN?wOtaWj@c$+g0_{^Q%7fbag*n)zxt#XGpe8eRNXyeslA+
zKhr$%Xwx-qbc|X1M6>vZ@q?1r<7mE9`2ERaCl6n;^1gjB6NQx+v~Le@i_ggC&)mBx
z@k5<MN9ZzJW=^dVe@*(gIWttU7SrX=UhIErGMWDOXXf1w#Cv&t*$1DDn+cXIG)s@r
z<-=OF|MF7o$PZ8U4&LzQ_;@paTch6mGA<2#sJ!+@dHPk&tKvGc`9}`!$qnBcCT%9k
zpU{ZpZFe&VYvZ<+@`m_qfA8b7ws~)Sv$ehTiste9wYiU;)Us%Dz8@Ju=8HdylZB7X
zADP9iO}n3oI~V-=k9>0*{o`sT+8z#m|C6Qpn#a4tJ-EzMa=Oajef4t9hRMO@cb?h1
zKQF-RKKx+55vifg$6*I{xv+*^_rhvS8z(#32jU5I@SU%Z7wF8nCA4{-<fndV1uQbO
znQ5)sGjVa@lVAAO7@*GLb@ZKag7m+OCsRG6^6_}l$n<gUsl4&mcBnEFuXod1HCGw8
zWD&c$e(~<3Z_TbA<LJ2COO0tW^IFRyQ|-Sc*Cfafv~h30Gmpj_ylYn<?)Ki??EkeG
z!Ow5x`W?dm@pm3<%71xoWe@I<>GUL%Pv<y1&K!U8x0)w%1Me)ny6F~|U(xLSb~CwN
z_xhG%W{Y_F>0WdA9BWU?khj3;CeZ=nt;pWBMZN|2x@noj8I?sexzsHCK~Y}c*7@6f
z$b<T7xS2aHYHJ=k6B6%=ncvROj56k=aM<`<8~5azOyg(r?vJihN-jSYrwZD&-vT(P
zlx5uFr(>JuuiL?{Td()TG8fA<wcnnYVz<Z=$ffC`b5HLL=N&>9pU`$Yq>CHdTrTID
zy1nyBRPu0SO1l1Y%3SzBEbJUsP)c5bUqc&@@z(6IgD7o!ITlLx@HiA_IP#)$jH-(?
zCH|tLHhbOM;^_Xpaome!*V@;|8`6l~9v+Kou4l4ir60>12-`z8e+b?746|k0#gL~?
zOMOLX9%<s5=_3eh>5eV5$6}5|%;GK#UB>Or7E$!{T-hu2K$RaT_Mz^lh}_=znto-s
zE?*rZx~r@Dhf?<YnQ07+Yp6!C*ZVLK49nxRi@EdDwjNvhZkRErCXaPvD9f$ci`SZM
zVRZvePJ6D4_`UsH8O6;X%9%R}`;n=OlCpo7oet#*Hg6t}$5X<x@%e%EN8+z6>4&Xe
zMBGZ)-%W3sqwfH1KD$l~`Qs=h6J02q42QO?m9acW+hyd&+-tdFp+2X^zIt@+%5t~8
zqvY#g-N<q+X1bNkTV~s1>$62&6!NJPw{|soS+;9q^OmKwd2E~>)O*y%TbQw!wMw#&
z?C@M|hkdk`c`WjjnNx?YWi3N){^jVZ55({&ZV=Gzx6$s~8Ma=Gt?PE#jAo--ZPXJF
zU&|MeTg^f9`SE>lU2}U69}cNFI^O^JpDjCN%rxI0S7V$qY+dQH@wO%IwAq~h?0dQx
zw%%8kHz|!n+vjFYzjq=@yiw~v72Kijc*Prb)Z!Dz(#LI1+om73J{fO-V%QpA#XFYj
z^oSd?gK}_g`VH^;cjis`)xGYO`61*^;nvlrX&*izY4+Fbk6o^d!pbfMcCU#yIQ5R7
zuR7D5U-pBcgxIDiCjM#%X>(?%B!A<jIgI&eGg-{yGP|F9>$JbYTc+I<^7^vVhOPBw
zvt;f+ycC}_G_T!j-tejzIK(LI>dp7Ww!M4S-1mpgjhbZkEz{;d{;wl#wrpEyGr@Ph
za_Mw)ZP>cpwvWe?rVd*_7Z)VOur&v=Bk2Z^E{lHbue33sj(5M$d|mT9|HA{N*`Hp`
z`0Zi;)|u(-%ultK$33{rQ*yeBT_ZAbV|eG8+3WIRzWpBxm}N(3Ge<Iwb>xb*eO!|s
z#^kk~|8~+m{hwXFS|aK85JS)Q{TC;PV3DQGY-`o#ur<GIQ(k#be4Zbb{7=6z3A9(o
z*_+`rf*iI!ePz1Hyj#LSzX^-jo3DRc)5X0=yUa0eTdt_X)_)W~{rQ?djAMS>?PZoR
zZKhjm*_bKU4C;H6_r(XDfBaRkRWV{bcPp;ZExCS&@IU_XEUscb+uv-l-ISr^FmFq^
z*2J(iFXn5`{?@S{1KW~!b#)Bw%8y^(kBha-s~%ikaq|3Ur+G17d~BIi)%E0bC5Ek+
z+8c5FjhC%De*E-3SM$=qSvEOBTfga79&CQHcEK9A?crv84WoSU(Kp41g565mdHu97
zD!CBD*6v!pmDg`K^AD~LTUTBlR&wTSe3ThK?LD1O+U|AD#Zq4(;(nIx?0VhABdL!s
zUjKI^-EZEX9pt%(()DF@C8rPc3%fj)qluzDHSR_X-?xWFB#Bd|-PV+kM~V{1;XcGC
z5qT9;AKK-#pOm$w?F(IdLYgk)rfoh(DD|;FN-bx%Pp12kri)TyFLiOSD{U<A5=z_c
zl5CeWXCGTDs@)~eNoh(xRc3KVp(`;N-jJM>aEyzD`Aluchz&Dsju`i*T_!nKA9MK8
zHp|ezCz%h6J4`Pv_gKj$tcFRvuEtMJ?q}SYF0aDN5HmZ6Hd4;-O^ukTN6VbqImFqI
zyAtA3ojiPG=+?F|-FFUM?x1`Y&37?~)bT$<>FQ+DLo}-GQ|)KA>GH`_GS4*jLLb`Y
zbkih%B6Kap%fQ;;Klj3Zrnu6yZBApq#17gmbdfBtdy3FTrp4s(p$~R7a_d7TD_c`V
zf~_yD2YnaM$1aYDai6j~4Cj_DdT%_7zTq~?SaFX1byCRBX5;%TO{wq1N-nhda3r)x
zmQP-cE^;K?II^6J2hpR4l-&vIPmby-<8!wDiCSCP&Em(kcDp-DWXmnh=lR_T{jfDl
ziec-rX?IX=4EFAC&b0ILZM(MX&GT~Fuyv*WxDfBc=ki&W@B4E^8Sj?jY-?PVa;xi_
zr}DIG{XjlOEi1WpnvLrh-ZCU?`<YkIuGC-Wh<9L@&p#Pu$FMcOHn)2y(ac|Mx^L{_
zCjAHTEScT6>#%ilb~bCi{)C#chb3y4>uM*@nN49H$F~Qf<+(c_i(zXNTtk<SSwgNT
z@wdnoZT!`4T=(31%%4WJ*P~JI_`cF*vW+22&ELm3ZP+?i+x*C9;=-l>DqgJ5Uhd*|
zC!>;^KM}8bUpbB6)|fQqGdUpnu}KbFmmkV+syBC2u8-+7Heq?TwO%|lixmg;D^*#^
za@acA`(zAT&+UD*J0u-IvZsxut*GBu+9&?c`?~U)56sJ~-J8VO)-F<R3DKhc=4#V?
z_l1YsaStx@l$@^B7O6LfJm~(5Uy4sIKOW`&P<-J(c4Z#9+su}^$2wN`ajj&!9uq^m
z{b%FHE#B~V4-a5j$cZ7V&9klVe{1ZgOp#?pX!BvM+IPf#KL7p~+UB!A|BmKHjvsHv
zH`+?(-CM-3joyr>Zhq76GyPyEv!5OgVpZKMA9!7L+PjoLp%G!ZC8d1eFE@Egw>1Cg
zeO;by?PAy(S5fUgY`y+3qh%K#Db3<?{MhTid2`!*L&+Mpgo9|<(~rl1w~O-{;~qRM
zQ+L{mwfJAiZF_UPe~q)PYb$PJp^c$kdF<Uc;-`X2zoWKfF7@kb?RO{hrf~B+1No<8
zSO4RDR~nT}<0Na%JC9>{{o34qysj_e_ZItIw5hOR-3Q`4e1yHDN7qUHZeDcjGY`e>
zs3-4=6u%u`(OVt14n>?YJ%8&=Jn0wF-cQB>;g8<YUH*X`&$hPZ@};YjOSw-sg>CDH
zyt#qxclKA@PJc4GaShvv%36|@y^~jI?iAv)z#V$PL(zK|ZOIbjlwX8WAG_GT*K~1g
z&ZRc~y7=23@_Ct|)Xk2W+=`XP$FB@TX+Iy=G-R0n=yKXmPJWCc%djR&eN!IJvybJA
z!sRHt<nqoTHtQ~g$>PL9+7n|pL_Se}w03bROxk99(<WI|o2KoCLi<(mIcXdvFE;na
zlb~LFdO6}>Q*v)CJJ52nwWJ`fX<{r|_vGwczZ^TJ9adz_eDZ^JF&-l6ql?4cHbftp
zjty9Lka@n(%B_p<2=y<EM=~5;tocfb=u44dYuFB)P43dCWO>7rb!)*#6YSTBc#L7|
zqj|mk){x`;dERnoTPTrkHoefiCEirjP%6SAcg-}~K7?H=?b9xYeckF?=aM^N3|E@z
zB4f^8C{6pJW%P2NjfqZ}$@dKV*%{gxw&oVru*;r`ttpv!tr<1<2@l&gwaYvuAL8T8
z{(7tN?Mokf>SH^sS*fGUYH3?{Ygf-p)_%O*YVZDN+Al_JPsIT@lF#Sa`L5(`I?|xT
z-_3;E>*8T!h}LCT<U>7p=gdktSec*4aIJ>f__0sBviii?_Hx(nm3GoKP5b$2En|Lh
z`)=)9mY+6G_D?K&Ei!H`zB$A$De-B0y!DuNIc#0oMVm7oTl=wy`Ta9-AI9Zp_s0^f
zMr1YRo^r4ncgp;`rX}~m-r^H6{ctmD;w{;{`Tkj{AC0x~Tk>_-dUJ<f9tG6Ue)jGC
z%;d^zo3@{guF)T<y5?hX1T7Cn^v$!~y)kUPcekIJj10N^&b3YXzq8DCK5q}2?(F2=
z?R&LkhCFZ`{6{%=B;=;0SeNnJ3(Hi|`TL86XWh@ouyyE}U9QOz^2t=<FFd2AIWttU
zSdWP_l8Zl&AGi3y@10!9WLrXMe*Lv^TK3sx>C5L%m$}xeJ@;d=t<5LnY|Wcv+ddkf
z*nTR00xHkczO!`G#eH#uklByLyPR9s<MY1lVR9+b9DLz#w&~Qx1;@!%x9zRBV#DJ9
z<Ml@+^K9!^-MZ9Vk6~*+TF!K9Ez2gi85@~;^~w4Bnsc#LPe1z;O?mi{DEFaD&CVAI
z@Bh{KeCgL-ap`amX5kS^KCEG9#Mbc6_!XXd>hi;}50{;x&0J%9b75_hvXbL5?cccC
zlrN8A>rUZ2|7z2G_Q#jE+&Qh<?qAQJXnyt!XQt&sT(0`zkHzWS-*{zHe&u}EylF9M
z9?qI_*gF5kJnZcdYBycP@cP`_n%PNbTid)6x%s*GMVWsX$LkNp{*7U4+h*BEL9W%(
za?PQ7yt+R6Y+Ug2$6s0A^KZVqyEjK+yM*%epS`F2{4?LSQr0fnPEK=AM1ML4ae3<U
zlfP9?PPB9E*EQGf|6&w!uq{Vcn?uB=t5l~a-z(o7=epzb!{%@Ao$ul&A<OjB^YZ$q
zq8qermnFnolzgSRue;VS)u@dR59UeL?(q*kn#0y^E$Pikxf&zjc;!A5rRSmgbNS?X
zb@R1r$xdCk7F%@V*PA$&ls|8#_doNNXy)Ga?G5`#lz9EG%$mvn_pPUvy|Q9|W&Whu
zvW%R^0clu2&O}5zL~fhbV_BbQmR)#rDAOF*^@py_DWmJhSI)aO4h{K)xDtOQFICT1
zhqlzkJQ$Yv%gEhAUv)bf8ahmC?i{ubp$s#-PP?;lA?1F2m9dM1SyWS^nWe2w-&jQD
z>t-brMUUMQE^k>su6}Twi<#W&WhleUDbw}!vuJ<Y+-UOd3tL0(l9ie^q_2G-E<c<7
z^XU2)&c)>hnfMnc2RX^UvA5SAdDiu7PJ4V~bKl+*{lTs)(JMyCi_N^m``<S9%rfK{
zWf3QOhviMv+?rV}Z9b3v6tl4qIcFtib_s2`{p>CYx20*X=NGW&&F?fNc1MIO&4bx<
z>VAoKm5lq^WBTJ()?Sur#+aCIGh$<C-%~FLSx+;TwTy0aI#k`|!hSvsA@)ljuEgYM
z-eKL*X^Dt9Arx)=;iIe8mb1(nB560YVTju{t$5oKJ%{xVZqIvW_^y4M7r1trp}c-&
z&%}@Q%`&#c-(i>yv*Q+wF}WsRoVJAasZ5ZA_pylOOqVM%bonrJmy!z^qLqEf8uyp;
zhlLCgr%dY`{VX$|MVrI^uzLJZVTjl^U9;Gh_<32sh*IMs;d1s*VoRTh_FRv16>Gio
zR(tyuuN81|_Pw~{=i!>ob<A#NfnOhY>iO`HB?de7L;kw_Klia)cU0-q#p6GWzj#x<
zA-ro?_v#m7CzYYL6Q|kGz4+^L?bfZ#M9sr-QCeKyeDSG!OZn8KdGy@d=50iG@s}5a
zbPxU6nMsL-CbzE5nW2*7F<q|CYV&VnXdjrzu%xR`vJxq0OS>*}W$t|DmiVicJa{WU
zc&}&TKH4>1#?~LXcqZPz=fdn;CbebDGBWD)(B`TrtGoB(ZC_R_XU;bM@&?Z(K8uK$
zID?xpP5fTRI_X-=YLdvbElHNNEwq_nt*m8^lGCAyHN|qp>65)~*2G1^&4s@m=ThRg
zHQxFgZ>*csMwWxgEBBfYe$S=;_R*`@iz+z8<cA|Q=B+VvB^$Oie5Op-wqQTX$})!%
z%39})tGt^ML(ShAx9tmgwl&h{+1CBxCZ$^smL)0~_DbzYZ4_}O-dPV@5($<+V>HHG
ziJ{n7?Hc-+Br+XK(tnOQB*_#TLy5IR%MQ!hm}TS2*G(t)e>%>Lls7f`wTZoE|8?_j
zxo7smzUlsYw(a)9Vr%lV%`{%XcMdszyt&d}E`IS$*Ej1{tSLDNUU`kKOD8>CTZyb4
zb7gs)P2H97WWBq`O2qRryV|nt6|`HEJo@NY#oLw=XIt|vd9`W7FEhs8%}wl@tMPc3
z!~19L?j?3P@{5kJnxj<x*f(9oUe1R*2&eAawX&+qTFgs-VQEz+T@!n=X@0Oe_3geA
zlhVxZ(naQdnd9TQliD%rw3)77(H^cp+r&NNBgD^1_WQK9{c!#Ex$z)>H0iaY5igzP
zy2;s`apttPm9~vld(F+*f3@#^<Key7OT1Q<%-H5bhOyt)eX>TGF<D!QzxtK#Iz8>7
z<SC=okY$afudY~|-(N13{Lc61hgEU$#P+N;@s7zN?UkYM7ihYB%d$arPi<;hX&z|%
zw_g{7H4eMe_&2=jrS&UfZ#^=UF!qvK?)ZGm)fv;~%-YV*h?7ETCiMf{9Jbal^on6Q
zr(<nnWPBdf4_o8qVY;?$cYN}HEc@6@8Mg1>*s2#fVr|P$Y)iY>oXPLD#<2B?y&SeS
zPpzbTb9ACVf6Ge5-I{H4mwo@~J)o>rwD)A*3FQ4Nr#-tbi~e)#e6&77dD~j*4GY7L
z$|Pq_OV_V>*F2xFU5u8a+S?E9kY$`1B2J#Jw(MAnbjmI5a!sVHTb=W#hDW+-lizK<
z_*B<C7Q@!h{&IX#G(wjTaT#y(nK%zoa$)W1SPMQD)8!MkX3q?p!XxwM+Au6BnQ++w
zyPS^_>TM}YF64>_@}kclc-3CX6QNzk{>i)VtGCuEF~9hw*sX2MYz<wcXfst5cjy%J
z$F?Mftu<-6a{bluS#%`n;;(L7cF2+o$1-&po14FyBtER(A#{<Z&2&dwmT@H?)@sX$
z%^}K(v#rhhzc*U`&6CF`?|E}x6<zC?#k#V$xH@@%MEr2J_qFji4pQ^0=i?SE)~e0M
zZ47Z~SzA9|h*Vvs%(9{xIc&{Ms~-tuwROd7o{5+kwl-NwO%i!)k}g(U8rqS`w}w^n
z``cymT0&Nm%UQ{}vCrM%uyx$3dO|jf-5OR~R{c-Su{d?juwoV;0DpS&aC2~B{(-ak
zZU6S3=4#xy`EbV^&JB6CP9NQx;zpcvS)6(pJd(XEuW4zojVpG}JLcFvGk#i_Nn<En
zYL+Jtx4-1xUkhbz=>=QZ-&)gbI?cB&*P?f|nK+JZIavwa*r!(_pX==2z40M`J}q_$
zZ8WZ|C7kt7h7B)}Ysq(8=;|*q4rwnBGcU{OysOPF`D4#H_k+!YYuY7tb6ruB-L;3>
z?~it%4W&=wGPJd3)B-kSxcyZpmU!V}^Vsbd_2TDvZ60GLlSMoo>h8SKKWVdJB_F!@
zdoX7*bj!bHBp9j3m`t~Qe;s79BVjD-Nc>@oh7~1dO4iuMo4qky9p|>pbVt_bhPO2?
zt~u$~UD;(L`lQDm_lKC}<*38r-J9-k+Vfh<EV9ZE#*S=rW_8%wG`~>4t(oyPlzdEx
z8pa)%G2?z2S1(f?o0LhMMu^xv{*Pf<R+kY&FDbc@<u2l{#9tql_)RxN<n*!Cg;VC+
zj4%1H60-bmxm?!T-VN<oN&OO-ZHMjO)Rq{wwr78@nN4EYy4U=Zhs#>xw_jgd+-afR
zmZ~)O9xU(Xu`Ow?zj^g&sy8=njVfPu`<E^pEo)`@VC-k_8g}p3kDYZT-3vRLJ8|rK
zJ9V_K)U&Pa#edZ{*JIdv<x}sfU|lvmOPK%Mr0?CinQi<vLnZYoyB5>s>daJfW^;(M
zt>4$yqjkxIS$c#nA8NHRExAyuy%lv1)pi*>efM6x!HFb`Z(AnG*j+-KiPp-B<yuLu
z_?6hLbvG`Dt@Xt0Kw3^{S!P-*?Reue$u6PIL~CU&bCsNqP0SQKg?FBrHn03o;*-Pw
zy(^D=_usG94`j}Ndv8;|;$L6=U&rxdm5ddOtfX#a4rELG)tEMBYQwfy9a|qm&-%^#
zE_0>E%CNOcj@1ss)^o#`Os|Z;%~<ai9p|~n7lSNpQy4bk@b^KRIA0q%>WZgc)ifV^
zYb?dEbuVHb9Y@P;7P^K$X38}IQZGJ;B&B{p-DT{MB<Ht=p=DWC({4?^Ey4Ytj!R~n
zFVC~B(N(XVosDDGKaH&Ap>6q(ukVgW9gn%V^U!k~wti^*l4;(~sfN$RXT&kY?6!BL
z^%k`IV_B;!K5)IuyA)r@VQcP_IR5Wka-V*+wC8I+FIw3W%B6fc`L1Tart6j&+FXiX
z2YKRkO_!fFHC;w*2<sKqC-a8Xv8o+k#Wts_YrDf|<Fe@C8zuEp+`aYMcPKEE<g?>=
z$k;ai##hu$WsixnoVA6Fc>cnsHZ5zdPLECcx4W|sHQm^nNpr6G2hF_86ek;uN!Mrc
zf}m~T@xh^%yg5VM&SKhsx3%kPxmSkL^PT?wuy9+`McsKvvc#V0hHdSe6qgMjNptGr
z@!h(4t4=Lw>x%77>T=|8J|0RIHtpiNp1nN#mEmH)<+E?<7grv$x9qPh_pc&lh}mB4
z(aZi5;3!Kw6qnQaP-XV9JP%w$doCu&o3~uMandy>d^a%*-(UW1%>Cl7%w}#3Wo7N(
zi22wdXNE6z24B;?GTu3KD~bBq<K<?|xL=O1K2k!7XT@4q&YgC&Gjv0y+=;&#fBP9x
zvkiH>WlR|&a(QcL`xJR%c|D9DA1qU>uYJiZ-QR2lj@=l;*6!>dymv1z67J&EWw&g9
z>E3X;Is5ICk!)D8b^F?_DKf$LkKJHf@|$t$A>QGP7YVm{<Ift(J(KwQQ&}$E*5tQN
zN*$LoHlL1rQ8sTMxB8@HFKk>kC9S%w_GnkkxD&#3UeC6Ev8fjcmtX#-Sr@7DZ~lwl
z*EGNP(_K?yAv;KEb7rWdcA2%9E?3uTcQF~yd}Xd>_v>;#OUP$#iNC&*_>yT1hvKu6
zkCxi9u3jXZNfvRkF2A+dX4+jsn~Ab{e`$YyzRQIOS$mr^*S~VoeC>Cfon)DBs4<yz
zjdZ<bnQ0|SyLMsfVY!)XTWB-EN?Bw2l5;~7cX`{==ZuSl%W#o!^NFvRUWw>7SN#`z
z)9y`w)HUzFd8T6DyEaIz{6oxGZEaXKZcCVE!pRy~RMJMSd8{bIiv7BepNW{Y)1H48
zr}raCcQtE?Bwb<;FSr?ZY8duPi5=Iq%Vb%}Ykw^U-%oyW*~5<YxtcUub{qTnu!AnE
z**qCqc1XE7{pPi2bJ$w)BH^<?6z?k+=MG=><~bnG*PC0Li#WQrI~sAq@^pM1J7MK|
zR6lH8Iqlgre>A<cp60ff+C{#JUJ2#zML+px`4%ig3|n8`p^hJ~#Ww84v!#po^Led7
z+i%k&ahIuP_Q9sPde^rx`(}M+pIUNFk!#!jDY86HM?^O{lC?zSZHKm2P{w>+om+%L
zhEgA2z7O^Ct4~b!pU6#k^albh4}g7`O%LK8^^+t0I=?i$3`6H0miy_I^~F<{+F>Mh
zVv2T*JrlEWg#Gs-qRZoDhHOHqdwPi3wbq(F?z40x<on{i;Uv(0GaEN@|470YezDCe
zbAyMMrd-|_9uJf*)2C4FzV%Ko_00JsR^)e3yWtH?-1sk2wec5~?DrjdC8iy!&A83s
zscDH~qwZ-Gm(`ZO%~3+Gh!E>?#iZ26btS8<ug8a#WHs?QY{W+5T-X}Edby!pmi0hn
zS@z(PInO=ZZ(EssQ`?jn%hxj7T(?HLY*{3U5M>M?eQ90B9!rvu8^c$}+GAxcbDS2x
zp}@B8#b%LTSj)ylm(Oje5093sF?tBwX*(b6S1Mobjg^>T>o?T5T(zvW%f-PU=Z6xy
zTo_iAxYJfMi|fVP{G>3GT#obpU2SrkJAZkKDOPL_i}*>fOfl=a<{)RXtO#{W;$y7l
z{t~BwlXon0wpe~`?v$2A?qlj*mU-CtT-p}KmPNug6E9nqv(200?`F>A>-|GHvo*vC
zi%eLiZU3902g?qeC44Yi+)b|KS@lW(i&1AHcC6$hnQtxTwyM3HpKWF9qY1V2n2Zfy
zTTy0<yg(xk5ZTAFl1Jmthl^>Om#N2XUz*4Jc4Pq?!(!RsuWcTPvLb1g6`^j)*={f1
z9?qI}axH)B<zlJZ_F!|ay_so-ZCh{IiJN~sNfxj%EKZ`_m}B$GaM~Ek#<h36GOFEH
z^Geyd2M%BGW8wC)AC|QG95{?UoEu-e+97VO+9C3Jm~Ly?omM%vf7&0Y?zEg;^Tl=?
z`CPbc$QtXqcqTPX+b4QDCM8}vB4m57<jie^y*%^Q?AILQhWGiG_pa@_Ww)Eh3&4vV
za-WYqE|2b8!<Djp87OURXoR>|bxyi`n8u;6o$Tj|mHQSCl^ik;G0RMubxX+okX&h3
zvdy^=q05JC_;N*`sw*X9^NO5hk~3|52PdkH_&!OSGh0I(GuuownY7KkEX#`Jti6pR
zZ~YPZ3ndzmHMQ{<)gB>TYgtV)*`6d)Yz||~BH6f=>o2im0oS^5_SBghS;)D#t7}YW
zwg2aa^x;i$9r%8i^SPyWHS}MljUu}&w#|p-cc%K;)yH$uvTs<8*k4^(L>W7`t`5~6
zjO^v;+pOHP{X6|w8D%y@nI-05tk9iYarUDvAy0TsE=Qu8HU^T9$9(q4gWzgoU(bh6
z)gx}l5T$Gj2ZLJFutV6GD&EB3PAHLhKi>9^J8mWOC+mC{d%p~^?J)DQn$FI=FP`>K
zeEVLPUz=<G>EUx`@k3YRUV`8L{A^a9j5$0tv{|g=*CyV+n&xAN3$yqIiyGoNy)`Tk
zpzn&O|IL1=6j}NXR_=+x)1MBV?N-y}o80`pj?D97hBiBGn=QyE-p2l&iI!pZRQxK)
z{%7M?AoE1dlmFNJdgSinul#S{-8K6M=i_&SBWZ5jlbIzed27xriB@86quMS`#zZw)
z&QN+hf36HAJRI@+xuTv)SiE`~AI!H+8xj3^fZ*?9A@lCde|P1nm601lS90a-TV~CJ
zx31^dG(&#yJuiz_H`5#Mj_-SA)cl$FRg9dOeaqf(;aN}GWo))=ZS&iVjl=r!Ytu@u
z*(H=rw6+I_T*qqbn?0;Pc{=}FuWcq*{@_wG`xmqLdR5%*CBkF*aO3Nm$>sOo)A#C(
z?lN|$<nV=kh$*pl_qUB}Td?edS;G3J)oO2^iEAU47Z+xdGF*RH_e=g9NEfj?g)URo
zvYzQXL++iSlIFX<r|X}bW1p)xK8++L{!VCF#;$JuT9W$qq01z@gf0`Um9<N*Q`3Cc
zN6y6?q92X*zi{8Yi4!?v*njV=On<IcHO6h5$#&iKa4SlT1966u5BUQgE8(_Z`=hLG
z5(nZ8V}rAj@ppR13)A;^IkeY;Ubu%6$F*(Y$+ty{8!=jF&)1~wbP-$HKb7X~<ut6F
zd2=~sb#=)M+d`Cl7`mJtfnz=oGh?;!B3JS=>ZdbRhPFPgKCI?ljXyeH`iL$khj-EM
zBl}u&zSi9JvHho}{rpShvFzB6(wvL$PGsT|pAg4J)r`NH+d1tHjhnU5zoS@2<)Lg0
zu@7!DRL7NF(`No**T(F;{NN#aUe;89TO$)i=o{J3Z+*;4x=gj!{8-+L&e$&3)yq?}
zO&RX&TGc-9i}#q%%iPF{dUMh5(PeY?>NU7^%`&DZ85W+y^!TM4x7!znW<7DotyrtE
zKiFO<cU;;_E8~4}^qXFeHpO<uOKCh)mxIoOJQ&6OXs`4;e%b0Zie=oLOxoMev_E7y
z$mj7G)|xlQ?lN;y&NeeH;;&n)Bx7GPVZ88tV~cXwy8q?PKd!^p-<!utuRbiA_Qv@y
zuDv<gSkAa|IDCx}C(Im7KeqkWP0M`c+hXSJllq<cKI&s}SLpaXj6U4zmNU<3Qs0t&
zMSK_OX710=)sf0`D)6pl&feE%Y1y!}eKZ#~hO15YD-XsH@#(kJyS<b*{;TFj9^JBp
z#}{$4(x)D7+Kk9&X^FokD|u`DwHfnd{Eac=pmT@bbZzha$M>2pa_0e}j!t7TmXIs<
zhZXA=7uIe2)7ZBBJ&fA2XW};mBmE-&wuTZZ7HdusQMYaJ6Y&dm|7mPj+zItc{_a91
zt=rb-%s|@ZLajEYB^TC8OZ6^e*OFw!woo#`T3JJmwW2b`*3dO?h+%6f?}%aRH178D
znhPJO?}tm~yzx+M<nO++|19WOd;7PGneJG%Nw6_=llEYJ=-DSPIa%AZT5WtMt{=8O
zvy}Yh|D~O@ku*P=m<~hCa}lvMbeZD2URMsgX)M=DZpM44$9^Zuj7pkuC>+Dqd)In&
z8*4Z3<Js{fnP*$*GQk?<wj3MQ?=|1`k@q&QX@0aR&8P33JlOp=hl#t{BUhU5ne6%r
z-<WahUhQ|z?nn2}#X0nPj9d;i=bw#_CNd;={W*}F?h<kb#_05`n&W-oR;+k1yHu@Y
z7z*znPnaca3Vj`$Qas0XWo!PfsqdD$Nr^kDMe1qO)}vzojG5>AhUxWV?X2ZKG8BHS
zGuPF_+Eb?Iz9#m`qiY=?dTLgCJjA>7lCi&(&B^z3QR4&k8I!U5%e|ZPw;9%}%k8+*
zE{hnZea~4&zC<Qvhj#Rv7Jc$kCXSCK^7^})@i*gEd3jW5*YGn{0@Nc{PBTf3DY=lv
z)tOv4J!GDGCh#yxw<+WGtRj9AvJan+s}S4e{K`d;L(I16{xU&XO}JN=viWUn|9BSQ
z&il-2;dghw-CErFF0LnP+B5NlSOoQa(JXQ|?e`f=yo&5!i^qP@)5c7b`?x-RQ(z2h
zPv~}xK5b??%g;XAwf?f2>saR)x=t;y8<uLViy9XXYo!g5yH01b#p5+?Ia*A&YY{J4
zx^{a_k42LE>lX>*^h4LhHkHFn^%i-Di)(Y;+S1xWyS8-F!mK+U+kbR<JU;u~dMLTr
zzhtbhcn(Wz{c^3GZf)tMuyAo}Bc`(tT&=^_*EaWeuW4q@pX@bXv&>cg^B5SG*Ie3K
z$dLry=|n@yGwnf~ZH@l4OSls6mg-@DOuV>0&PExZo8?Hm97f&I-0YL>S2b_%ni#f5
z=Z-gNeOSIp8x~)TX&$=TtT>)?hcA5@aavfk&Fp;_o9=Hu{gzq&BxHB-shTv$kL92L
zcxi6NTgLr7=GD`lxh^YtYt9TYiy@|Fii7KTHA|*CF?6%{?ZsE$x~sW%IHE=$97<@q
zh_BUtS<IBhcQp0#huC?2l7F^%UwkbxLgdXM=B&j0BK|gqS<^n5DWbt2Y;z`^B4nRg
z-2bL#cH^G};H|uS@*g(SlB;HMuhuqaGHG_#F8;<Qms~ie-ev5tRVA|I{N@m4luWT!
z){tc=>aiiku;SEdK+XT(3vF}d_xfRL^UD5gYgv}iw(pPAVX;YvXAXx-#*M6>gs04q
zDf4a)xqr3}TW5phBRAuKyLz^@`GaSJKdXo&Wf->R^2Si2>0PE6HlgG~gxp>GfAp#5
zy|t3xjcpl*t^3dAZ0jggE7|mLYRfid+O#gd3|!B){zxSH^kmkqo^6e&uKBsFvhPMY
zy*r_uT-aMbW4fu_*{xVxhpo$0=bw7TjWI(R&y0>yJIs{qGpnKetvGd+m6Tu2=;g5W
z?EbmcL@$l`ym)0xnEt)5jua(s$Xh>jh_66){eJB89Zcd`k#AbNnyQcNpOz0V7wV*4
zT_~#yr_Fy|tmxL-SG&(Ld9KLkPz~`BQ~X%_%9*$}51T`hZkg&iPaYpjh->!hFVNM9
zc8q?JXUb6jD%23SKE2TMl<1Rfj`K?lTjMn@qWdsA(;Wg1k^TFZQGJXaW}=WS;lW(r
zttVPtY;)CE%7v1PD`6IQ6l!xhlRVykg(w%dgs%U7T~^*^&SeEp)NFfY@?e`CHV^nE
zz7o=A^!{Pz%Ejj^ba%VpawSTf#<onm*s0eRxnZ%@`H&-sX43Y3V|x$D)P2|`?d2iy
zZA{B@Kji-C>U_S_U))9she@-n)plmbUJrHiBdV-NzZ8~Ee?~1^_lfMP(|RWECnu#o
zP4o3-7O`zS#Ide9cqA2LW<7N4i>phSdvmzDJ;@0LoID&lHmW@#XCIYYvl>=+YrDFl
z8y8~VuB{nY+})X@Eqjiox6^~BiDB#XiMKSf7`8UeA3WB)ZMD#AuUuW)ZGLNKYMZvK
znr<n!eA(oQ$-5%M&9jqhHSLF|^~sv=Y)an#V7KS~T9r@UyVsYsth_&^dwscdYc1`T
z_N}abKC<Ogpv^jRo449#!hBxFMZ#TNBs`tPu(i4P#R`_=$6CT8Prs)>SPg^J`b2(f
z<~$ZNX4+o$<m&njEVHaUpk}rC?CauhKZ&v%A1v;PVe7ZVw%v;L@&9m0GyTfx{Jv-Q
zV&Co<GGUiam-BZzvaI;aO4d*5&Yx-fGLMmVk+vCHR&rrANy$y`GIlLVMr;cu6Regs
zW>_mKQ|u7lc>m7_+LeDgnV$VZy!XgqYi?}j%o0BGAH*A}h^YIxi|N?j;{(}}t20x!
zV{>TNx8U-!Bb3aQCA2v+R(mrJg)yRRD}SyThrDrv)8TUKHj{4+U8ack#TTICp`Xuf
zo8A2Ux0gCL{=F~6ejfJD<QQoic@A5a3mcQPT_)KjbeU+atkZIBf7NMc&9%ju=JDx&
z*z7l7j0+B8*xIfZSN?isUX9v5pN-oX+U0KCnCNijt(eVM{KGJusa>2YhmqUn7ANfZ
zA^W`fyRR)-$+zD8NE{!QMRm*Rolkb#(34uWR%cmVDs?Ej8gq0$ez)~<biNWBJbguz
zAM5N-7O_|I8Iz%n?|4s!uG>cqk6q3TJFw)!kf|<Y#HnF#em<)0!%)On*05p}i64fD
zBlG3H{C?MTeWIbpV|j-%)~4;+((#2^{=h?t_`Z(g37)r@c3a8o3A$~`hwq@AYi2cP
z?BCQZL%wu7$gLcWhcz{(8<xhyV@8xA_S9)6KN`BD5hLzU|JV~2Lvy~VzAQG)vAjpi
z+P=J3?&~f!Z4`L(l*Eso62CDzK!umKfIalm-apTwbyuE4-j_|*lMbf0(fF5X_dmFe
zO?+7<eQvw8+qliwHm-dURzA0leGwXbCsmH`U+yIHZh2PTrtR;R<1VE-ZQJq<r0`q?
zPCG_FpHG|9_GoO&^I7e4rMlDne~~+CH=vC>cAOd3d}&PEY5SsV$oSF43tRhe*cdnZ
zMQX<jyVWmrZRLfou&?hg!U3xrXv>#g&mFgI*v6ce{<F)~sF%ZhTzq&3&Ajt{y7D%6
zmwLO^L}hj1F3xwSmla>_jy)S8PH27UhdVzob+?DJ)(f7mcPv{v>GM_X?Md9_)a(19
zz00M)l#2UO-nL`T-LV)Ee{lrb=W|ob^I5pEUo3&=`s(&v^S@Zz{bJPnrEAsS7yHF9
zz1wx}xR1KwgO|Hq{~eXL_BQ#BN?6TwxNXy>-^{yP{%T$33B14pck`LM<I&;;-oh`{
z>dKeuhV8grU#f@UEg!(_sPnQ-*1c?7uHj#T0%hLL_9hR{^R;bnZ~9ni+to?ac6;;b
zjb&t9j(wxKRAY`$cEWjhS>HH`Tv1+M?NCA)8gaamXiJ}JY{!sk)3k2lSY<9n>am1j
zgVti==KW0@xAH%n49U8e#eq5QtMypiXDZt|d8E0oo6XlJab9Y27}<1j4M@gx{bY4%
z6YQ`qq~g252{ugPqLNu(?W{So-&|QV7v?MVWnEdxte@mkhIvFrzU5Ml+VrqeWo&6I
zMTko3mMk|RmTE=I`ufQubuw8tqF;(kFN?6b_dR~{Hmtu3USB#n$7!+MxMC7_HJHwu
zlU~kGc%yunZ!F;SnLNLC`{9&rzx{%4FUQ5WDZuN;EKkQE`dNVh0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk&y&FGnm3(qmf^>*HO-_cSDNPG
z_CizUL;UgStoz7QW43<vym@cVl$(!Dn+HB~&|I9v(mfgVct*7m^`=}}Pu1-GrOQq8
z*elNW88cOlsu^opH7YZ<@mKE4xv}_+YWDJB8h<5cYVl)KZA6>#>rv;PdG^(1^5@T<
z*)PvN+g!Z)?7N%YqO$nfi2Yg2)#6{OQP1-RolyL7iOF<2+ncvtX(ksgHhUL8@}6@)
zT)Wl$Rn4uYnK#o}tlDd0Cp69dP4iPR>8AhB%}MFr^|9tk?$rzN*PMyJMb1RuJSnQ|
z{pKg`X*1*Fnel=7tKZyYR5O;<W>gm6ye0m+q4<+B-n*8umQ^#3Wz}|#Wi7I6tw)uJ
zS&7<|@vvR%sj_?3rXDFipH*G1JFIa%>IAP^)|jgLZ)*KvjkA<UuNpN!neb5cFym-n
zqv|$}QFYgz7Ii}FUlLK(YZCoy>^V(I(bK}Tedq&c*H@lzrspE2X8YloX)ngZ^!U?g
z$EY^T%EMtj5;c!sID2Bo)l|zGGb-D@(um_x^|?Hxst3B0T7Uc*KRqeqv7_y&O&w~y
zou;0kdO{;kh&mx-jT%%pH)1_in}kDD@0B$+kAL=B?CNifV_V%r8C8~1E5#2PPl+ni
zv(woVm;T%CdNVnDK8~aNaU6|uBfP5nNIj0eanYQ+(wxbHqORtVPfZV>xczbT*0W#P
zocYsd?^(prc5-F$?2k7W?qXDZf;2z#58~+bq01`=r}5}f8_`A6j<l<0%v8;In5wO>
zhp8Ghf5Z9ykhfmen6VyXn(R4uyg_4Ghpj)MtTEN$fo`{`SLNo7t#9W4{>Pg2sE0Da
z31ywoh~1)2DC<t6Uf+CqH10dz^EF@dwSVm$SKs^1*REW-`i<l4!;duIRQFu&ufN>y
Y!)C8}DE^w}P1zMA>^1pH{=Vz~Kdr~6{r~^~

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/output_files/stp2.stp b/FPGA_firmware/output_files/stp2.stp
new file mode 100644
index 0000000..07c4aed
--- /dev/null
+++ b/FPGA_firmware/output_files/stp2.stp
@@ -0,0 +1,860 @@
+<session jtag_chain="USB-BlasterII on 147.142.18.133 [USB-1]" jtag_device="@1: 10M50DA(.|ES)/10M50DC (0x031050DD)" sof_file="hit20v3.sof">
+  <display_tree gui_logging_enabled="0">
+    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
+  </display_tree>
+  <instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <position_info>
+      <single attribute="active tab" value="1"/>
+      <single attribute="data horizontal scroll position" value="480"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="setup hierarchy algo_top_cl_cali_rms:recon" value="3"/>
+      <single attribute="setup hierarchy bkg_subtraction_pipe:bkg_subtraction0" value="3"/>
+      <single attribute="setup hierarchy m10_rgmii" value="3"/>
+      <single attribute="setup hierarchy q_sys:q_sys_inst" value="3"/>
+      <single attribute="setup hierarchy q_sys_calibration_ram:calibration_ram" value="3"/>
+      <single attribute="setup hierarchy sensor_algo:sensor_interface" value="3"/>
+      <single attribute="setup horizontal scroll position" value="0"/>
+      <single attribute="setup vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="32"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="4080"/>
+    </position_info>
+    <signal_set global_temp="1" name="signal_set: 2024/07/25 16:46:53  #0">
+      <clock name="ddr3_ram_pll_ref_clk_clk" polarity="posedge" tap_mode="classic"/>
+      <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" tap_mode="classic"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" tap_mode="classic"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
+          <node data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
+          <node data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
+          <node data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
+          <node data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <node data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <node data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
+          <node data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
+          <node data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
+            <node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
+            <node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
+            <node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
+            <node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
+            <node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
+            <node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
+            <node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
+            <node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
+            <node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
+            <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
+            <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
+            <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
+            <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
+            <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
+            <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
+            <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
+            <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
+            <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
+            <node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
+            <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
+            <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
+            <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
+            <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
+            <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
+            <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
+            <node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
+            <node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
+            <node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
+            <node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
+            <node data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
+            <node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
+            <node data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
+            <node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
+            <node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
+            <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
+            <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
+            <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
+            <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
+            <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
+            <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
+            <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
+            <node data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
+            <node data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
+            <node data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
+            <node data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
+            <node data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
+            <node data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
+            <node data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
+            <node data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
+            <node data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
+            <node data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
+            <node data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
+            <node data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
+            <node data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
+            <node data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
+            <node data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
+            <node data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
+            <node data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
+            <node data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
+            <node data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
+            <node data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
+            <node data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
+            <node data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
+            <node data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
+            <node data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
+            <node data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
+            <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
+            <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
+            <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
+            <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
+            <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
+            <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
+            <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
+            <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
+            <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
+            <node data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
+            <node data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
+            <node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
+            <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
+            <node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
+            <node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
+            <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
+            <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
+            <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
+            <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
+            <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
+            <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
+            <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
+            <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
+            <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
+            <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
+            <node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
+            <node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
+            <node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
+            <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
+            <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
+            <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
+            <node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
+            <node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
+            <node data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
+            <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
+            <node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
+            <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
+            <node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
+            <node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
+            <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
+            <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
+            <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
+            <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
+            <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
+            <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
+            <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
+            <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
+            <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
+            <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
+            <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
+            <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
+            <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
+            <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
+            <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
+            <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
+            <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
+            <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
+            <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
+            <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
+            <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
+            <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
+            <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
+            <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
+            <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
+            <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
+            <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
+          </node>
+        </unified_setup_data_view>
+        <data_view>
+          <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
+          <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
+          <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
+          <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
+          <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
+          <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
+          <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
+            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
+            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
+            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
+            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
+            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
+            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
+            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
+            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
+            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
+            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
+            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
+            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
+            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
+            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
+            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
+            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
+            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
+            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
+            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
+            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
+            <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
+            <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
+            <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
+            <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
+            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
+            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
+            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
+            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
+            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
+            <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
+            <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
+            <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
+            <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
+            <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
+            <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
+            <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
+            <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
+            <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
+            <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
+            <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
+            <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
+            <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
+            <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
+            <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
+            <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
+            <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
+            <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
+            <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
+            <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
+            <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
+            <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
+            <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
+            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
+            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
+            <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
+            <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
+            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
+            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
+            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
+            <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
+            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
+          </bus>
+        </data_view>
+        <setup_view>
+          <net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
+          <net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
+          <net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
+          <net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
+          <net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
+          <net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
+          <net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
+          <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
+            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
+            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
+            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
+            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
+            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
+            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
+            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
+            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
+            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
+            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
+            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
+            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
+            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
+            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
+            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
+            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
+            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
+            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
+            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
+            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
+            <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
+            <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
+            <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
+            <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
+            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
+            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
+            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
+            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
+            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
+            <net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
+            <net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
+            <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
+            <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
+            <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
+            <net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
+            <net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
+            <net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
+            <net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
+            <net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
+            <net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
+            <net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
+            <net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
+            <net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
+            <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
+            <net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
+            <net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
+            <net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
+            <net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
+            <net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
+            <net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
+            <net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
+            <net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
+            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
+            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
+            <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
+            <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
+            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
+            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
+            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
+            <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
+            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
+          </bus>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2024/07/25 16:46:53  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="256" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="yes">
+          <level enabled="yes" name="condition1" type="basic">
+            <power_up enabled="yes">
+            </power_up>
+            <op_node/>
+          </level>
+          <custom_flow_control>
+            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
+            <flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </flow_expression>
+            <power_up_flow_expression><![CDATA[state ST1:
+trigger;]]>
+            </power_up_flow_expression>
+          </custom_flow_control>
+        </events>
+        <storage_qualifier_events>
+          <transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
+            <pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+        <log>
+          <data global_temp="1" name="log: 2024/07/25 16:46:53  #2"/>
+          <extradata/>
+        </log>
+      </trigger>
+    </signal_set>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <single attribute="lock mode" value="0"/>
+    <multi attribute="column width" size="23" value="34,34,799,74,68,78,95,96,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
+    <multi attribute="frame size" size="2" value="1920,1017"/>
+    <multi attribute="jtag widget size" size="2" value="306,137"/>
+  </global_info>
+</session>
diff --git a/FPGA_firmware/output_files/stp_clu.stp b/FPGA_firmware/output_files/stp_clu.stp
new file mode 100644
index 0000000..025e7d2
--- /dev/null
+++ b/FPGA_firmware/output_files/stp_clu.stp
@@ -0,0 +1,402 @@
+<session jtag_chain="USB-BlasterII on 147.142.17.251 [USB-1]" jtag_device="@1: 10M50DA(.|ES)/10M50DC (0x031050DD)" sof_file="hit20v3.sof">
+  <display_tree gui_logging_enabled="0">
+    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
+  </display_tree>
+  <instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="2040"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="setup horizontal scroll position" value="0"/>
+      <single attribute="setup vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="16"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="8184"/>
+    </position_info>
+    <signal_set global_temp="1" name="signal_set: 2024/01/26 17:22:13  #0">
+      <clock name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|clk_clk" polarity="posedge" tap_mode="classic"/>
+      <config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|clk_clk" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|no_cluster" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~0" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~1" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~2" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~3" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~4" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~0" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~1" tap_mode="probeonly"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|clk_clk" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[10]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[11]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[12]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[13]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[14]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[9]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_valid" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[0]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[1]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[2]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[3]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[4]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[5]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[6]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[7]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8]" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|no_cluster" tap_mode="classic"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~0" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~1" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~2" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~3" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~4" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~0" tap_mode="probeonly"/>
+          <wire name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~1" tap_mode="probeonly"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|no_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" type="unknown"/>
+            <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[14]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" type="unknown"/>
+            <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[13]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" type="unknown"/>
+            <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[12]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" type="unknown"/>
+            <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[11]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" type="unknown"/>
+            <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[10]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" type="unknown"/>
+            <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[9]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" type="unknown"/>
+            <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" type="unknown"/>
+            <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" type="unknown"/>
+            <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" type="unknown"/>
+            <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" type="unknown"/>
+            <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" type="unknown"/>
+            <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" type="unknown"/>
+            <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" type="unknown"/>
+            <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" type="unknown"/>
+            <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" type="unknown"/>
+            <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" type="unknown"/>
+            <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" type="unknown"/>
+            <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" type="unknown"/>
+            <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" type="unknown"/>
+            <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" type="unknown"/>
+            <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" type="unknown"/>
+            <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" type="unknown"/>
+            <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" type="unknown"/>
+          </node>
+          <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="7" type="unknown"/>
+          <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|clk_clk" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_valid" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8..0]" order="msb_to_lsb" pwr_level-0="alt_or" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="10" type="unknown"/>
+            <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="9" type="unknown"/>
+            <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="8" type="unknown"/>
+            <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="2" type="unknown"/>
+          </node>
+          <node is_selected="false" level-0="alt_or" mnemonics="states_table (2)" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states" order="lsb_to_msb" pwr_level-0="alt_or" radix="mnemonics" state="expand" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="state machine">
+            <node data_index="36" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="0" type="unknown"/>
+            <node data_index="37" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <node data_index="38" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <node data_index="39" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <node data_index="40" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <node data_index="41" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <node data_index="42" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="6" type="unknown"/>
+          </node>
+          <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="probeonly" type="unknown"/>
+          <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="probeonly" type="unknown"/>
+          <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~2" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="probeonly" type="unknown"/>
+          <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~3" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="probeonly" type="unknown"/>
+          <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~4" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="probeonly" type="unknown"/>
+          <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="probeonly" type="unknown"/>
+          <node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="probeonly" type="unknown"/>
+        </unified_setup_data_view>
+        <data_view>
+          <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|no_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[14]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[13]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[12]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[11]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" type="unknown"/>
+            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[10]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[9]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" type="unknown"/>
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" type="unknown"/>
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" type="unknown"/>
+            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" type="unknown"/>
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" type="unknown"/>
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" type="unknown"/>
+          </bus>
+          <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="7" type="unknown"/>
+          <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|clk_clk" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_valid" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8..0]" order="msb_to_lsb" pwr_level-0="alt_or" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="10" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="9" type="unknown"/>
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="8" type="unknown"/>
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="2" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" mnemonics="states_table (2)" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states" order="lsb_to_msb" pwr_level-0="alt_or" radix="mnemonics" state="expand" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="state machine">
+            <net data_index="36" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="0" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="6" type="unknown"/>
+          </bus>
+          <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="probeonly" type="unknown"/>
+          <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="probeonly" type="unknown"/>
+          <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~2" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="probeonly" type="unknown"/>
+          <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~3" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="probeonly" type="unknown"/>
+          <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~4" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="probeonly" type="unknown"/>
+          <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="probeonly" type="unknown"/>
+          <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="probeonly" type="unknown"/>
+        </data_view>
+        <setup_view>
+          <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="44" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|no_cluster" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="45" tap_mode="classic" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15..0]" order="msb_to_lsb" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[15]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[14]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[13]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[12]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[11]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" type="unknown"/>
+            <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[10]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[9]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" type="unknown"/>
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" type="unknown"/>
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" type="unknown"/>
+            <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_data[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="10" tap_mode="classic" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8..0]" order="msb_to_lsb" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="combinatorial">
+            <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" type="unknown"/>
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" type="unknown"/>
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|address[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" type="unknown"/>
+          </bus>
+          <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="43" tap_mode="classic" trigger_index="7" type="unknown"/>
+          <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|clk_clk" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|data_in_valid" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="0" type="unknown"/>
+          <bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8..0]" order="msb_to_lsb" pwr_level-0="alt_or" state="collapse" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="register">
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[8]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="35" tap_mode="classic" trigger_index="10" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[7]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="34" tap_mode="classic" trigger_index="9" type="unknown"/>
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[6]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="33" tap_mode="classic" trigger_index="8" type="unknown"/>
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[5]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="32" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[4]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="31" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[3]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="30" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[2]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="29" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[1]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="28" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|size_ctr[0]" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="2" type="unknown"/>
+          </bus>
+          <bus is_selected="false" level-0="alt_or" mnemonics="states_table (2)" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states" order="lsb_to_msb" pwr_level-0="alt_or" radix="mnemonics" state="expand" storage-0="alt_or" storage-1="alt_or" storage-2="alt_or" type="state machine">
+            <net data_index="36" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="36" tap_mode="classic" trigger_index="0" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="37" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="38" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="39" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="40" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="41" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="true" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="42" tap_mode="classic" trigger_index="6" type="unknown"/>
+          </bus>
+          <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="46" tap_mode="probeonly" type="unknown"/>
+          <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="47" tap_mode="probeonly" type="unknown"/>
+          <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~2" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="48" tap_mode="probeonly" type="unknown"/>
+          <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~3" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="49" tap_mode="probeonly" type="unknown"/>
+          <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan0~4" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="50" tap_mode="probeonly" type="unknown"/>
+          <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~0" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="51" tap_mode="probeonly" type="unknown"/>
+          <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|LessThan1~1" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="probeonly" type="unknown"/>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger CRC="281E7B14" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2024/01/26 17:22:13  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="no">
+          <level editor="basic_or" enabled="yes" name="condition1" type="advanced">
+            <power_up enabled="yes">
+              <power_up_expression><![CDATA[alt_reduction(alt_true, {((mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last') && variable(1))), ((mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster') && variable(1))), (alt_reduction(alt_false, {(mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP') && variable(1))}))})]]>
+              </power_up_expression>
+            </power_up>
+            <expression><![CDATA[alt_reduction(alt_true, {((mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|sig_ram_last') && variable(1))), ((mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|rms:rms_but|has_cluster') && variable(1))), (alt_reduction(alt_false, {(mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_FIRST_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_HAS_CLUSTER_KEEP') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_IDLE') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_LAST_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER') && variable(1)), (mbpm('X', 'q_sys:q_sys_inst|sensor_rms:sensor_interface|data_interface:data_interface_dut|cluster_locate:cl_but|states.STATE_NO_CLUSTER_KEEP') && variable(1))}))})]]>
+            </expression>
+            <op_node/>
+          </level>
+        </events>
+        <storage_qualifier_events>
+          <transitional>11111111111111111111111111111111111111111111111111111
+            <pwr_up_transitional>11111111111111111111111111111111111111111111111111111</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+        <log>
+          <data global_temp="1" name="log: Trig @ 2024/01/26 17:22:21 (0:0:0.0 elapsed) #3" power_up_mode="false" sample_depth="2048" trigger_position="256">0111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100011111001000000000000000000000000000000010000000001000111110010000000000000000000000000000000100000000010001111100100000000000000000000000000000001000000000100</data>
+          <extradata>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
+        </log>
+      </trigger>
+    </signal_set>
+  </instance>
+  <mnemonics>
+    <table name="states_table (2)" width="7">
+      <symbol name="STATE_FIRST_CLUSTER" value="0000001"/>
+      <symbol name="STATE_HAS_CLUSTER" value="0000010"/>
+      <symbol name="STATE_HAS_CLUSTER_KEEP" value="0000100"/>
+      <symbol name="STATE_IDLE" value="0001000"/>
+      <symbol name="STATE_LAST_CLUSTER" value="0010000"/>
+      <symbol name="STATE_NO_CLUSTER" value="0100000"/>
+      <symbol name="STATE_NO_CLUSTER_KEEP" value="1000000"/>
+    </table>
+  </mnemonics>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <single attribute="lock mode" value="0"/>
+    <multi attribute="column width" size="23" value="34,34,618,74,21,78,95,96,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
+    <multi attribute="frame size" size="2" value="1920,1017"/>
+    <multi attribute="jtag widget size" size="2" value="306,137"/>
+  </global_info>
+</session>
diff --git a/FPGA_firmware/q_sys.BAK.qsys b/FPGA_firmware/q_sys.BAK.qsys
new file mode 100644
index 0000000..df7c3f9
--- /dev/null
+++ b/FPGA_firmware/q_sys.BAK.qsys
@@ -0,0 +1,2495 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altpll_shift
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element button_pio
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element button_pio.s1
+   {
+      datum baseAddress
+      {
+         value = "403846528";
+         type = "String";
+      }
+   }
+   element channel_adapter_0
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element cpu
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element cpu.debug_mem_slave
+   {
+      datum baseAddress
+      {
+         value = "403843072";
+         type = "String";
+      }
+   }
+   element ddr3_ram
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element ddr3_ram.avl
+   {
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element ddr3_ram_resetn
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element debug_uart
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element debug_uart.s1
+   {
+      datum baseAddress
+      {
+         value = "403846176";
+         type = "String";
+      }
+   }
+   element descriptor_memory
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element descriptor_memory.s1
+   {
+      datum baseAddress
+      {
+         value = "403832832";
+         type = "String";
+      }
+   }
+   element dual_boot
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element dual_boot.avalon
+   {
+      datum baseAddress
+      {
+         value = "403846496";
+         type = "String";
+      }
+   }
+   element enet_pll
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element eth_tse
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element eth_tse.control_port
+   {
+      datum baseAddress
+      {
+         value = "403845120";
+         type = "String";
+      }
+   }
+   element ext_flash
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element ext_flash.avl_csr
+   {
+      datum baseAddress
+      {
+         value = "403846464";
+         type = "String";
+      }
+   }
+   element ext_flash.avl_mem
+   {
+      datum baseAddress
+      {
+         value = "335544320";
+         type = "String";
+      }
+   }
+   element ext_flash_clock_bridge
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element frame_timer
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element frame_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "403846144";
+         type = "String";
+      }
+   }
+   element msgdma_rx
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element msgdma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "403846400";
+         type = "String";
+      }
+   }
+   element msgdma_rx.prefetcher_csr
+   {
+      datum baseAddress
+      {
+         value = "403846272";
+         type = "String";
+      }
+   }
+   element msgdma_tx
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element msgdma_tx.csr
+   {
+      datum baseAddress
+      {
+         value = "403846432";
+         type = "String";
+      }
+   }
+   element msgdma_tx.prefetcher_csr
+   {
+      datum baseAddress
+      {
+         value = "403846304";
+         type = "String";
+      }
+   }
+   element onchip_flash
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element onchip_flash.csr
+   {
+      datum baseAddress
+      {
+         value = "403846544";
+         type = "String";
+      }
+   }
+   element onchip_flash.data
+   {
+      datum baseAddress
+      {
+         value = "403177472";
+         type = "String";
+      }
+   }
+   element onchip_ram
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element onchip_ram.s1
+   {
+      datum baseAddress
+      {
+         value = "403767296";
+         type = "String";
+      }
+   }
+   element output_pio
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element output_pio.s1
+   {
+      datum baseAddress
+      {
+         value = "403846208";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element sensor_interface
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element sensor_interface.csr
+   {
+      datum baseAddress
+      {
+         value = "403846336";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "403846240";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sysid.clk
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum baseAddress
+      {
+         value = "403846552";
+         type = "String";
+      }
+   }
+   element tx_multiplexer
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element udp_generator
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element udp_generator.csr
+   {
+      datum baseAddress
+      {
+         value = "403846368";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="hit20v3.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altpll_shift_c0"
+   internal="altpll_shift.c0"
+   type="clock"
+   dir="start" />
+ <interface name="altpll_shift_c1" internal="altpll_shift.c1" />
+ <interface name="altpll_shift_c2" internal="altpll_shift.c2" />
+ <interface
+   name="altpll_shift_locked_conduit"
+   internal="altpll_shift.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="button_pio_external_connection"
+   internal="button_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="clock_bridge_0_in_clk"
+   internal="ext_flash_clock_bridge.in_clk"
+   type="clock"
+   dir="end" />
+ <interface name="ddr2_lo_latency_128m_auxfull" internal=".auxfull" />
+ <interface name="ddr2_lo_latency_128m_global_reset_n" internal=".global_reset_n" />
+ <interface name="ddr2_lo_latency_128m_memory" internal=".memory" />
+ <interface
+   name="debug_uart_external_connection"
+   internal="debug_uart.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="dipsw_pio_out" internal=".external_connection" />
+ <interface name="enet_pll_c0" internal="enet_pll.c0" type="clock" dir="start" />
+ <interface name="enet_pll_c1" internal="enet_pll.c1" type="clock" dir="start" />
+ <interface name="enet_pll_c2" internal="enet_pll.c2" type="clock" dir="start" />
+ <interface name="enet_pll_c3" internal="enet_pll.c3" type="clock" dir="start" />
+ <interface name="enet_pll_c4" internal="enet_pll.c4" type="clock" dir="start" />
+ <interface
+   name="enet_pll_locked_conduit"
+   internal="enet_pll.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_mdio_connection"
+   internal="eth_tse.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_rgmii_connection"
+   internal="eth_tse.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_status_connection"
+   internal="eth_tse.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_rx_clock_connection"
+   internal="eth_tse.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_tx_clock_connection"
+   internal="eth_tse.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface name="eth_tse_serial_connection" internal="eth_tse.serial_connection" />
+ <interface
+   name="eth_tse_status_led_connection"
+   internal="eth_tse.status_led_connection" />
+ <interface
+   name="ext_flash_flash_dataout"
+   internal="ext_flash.flash_dataout"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_dclk_out"
+   internal="ext_flash.flash_dclk_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_ncs"
+   internal="ext_flash.flash_ncs"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="frame_timer"
+   internal="frame_timer.external_port"
+   type="conduit"
+   dir="end" />
+ <interface name="jtag_avalon_master_clk_reset" internal=".clk_reset" />
+ <interface
+   name="led_pio_external_connection"
+   internal="output_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_if_ddr3_emif_0_status"
+   internal="ddr3_ram.status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_resetn_in_reset"
+   internal="ddr3_ram_resetn.in_reset"
+   type="reset"
+   dir="end" />
+ <interface name="memory" internal="ddr3_ram.memory" type="conduit" dir="end" />
+ <interface name="ref_clk_clk_in" internal=".clk_in" />
+ <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="sensor"
+   internal="sensor_interface.sensor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_status"
+   internal="sensor_interface.status_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_synchro"
+   internal="sensor_interface.synchro"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <module name="altpll_shift" kind="altpll" version="18.0" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="15000" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_UNUSED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="button_pio" kind="altera_avalon_pio" version="18.0" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="9" />
+ </module>
+ <module
+   name="channel_adapter_0"
+   kind="channel_adapter"
+   version="18.0"
+   enabled="1">
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="inChannelWidth" value="1" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="inUsePackets" value="true" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="outMaxChannel" value="1" />
+ </module>
+ <module name="cpu" kind="altera_nios2_gen2" version="18.0" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="12" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="12" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18080000' end='0x180F0000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18120000' end='0x18122000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18122800' end='0x18123000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18123000' end='0x18123400' type='altera_eth_tse.control_port' /><slave name='frame_timer.s1' start='0x18123400' end='0x18123420' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18123420' end='0x18123440' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18123440' end='0x18123460' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18123460' end='0x18123480' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18123480' end='0x181234A0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x181234A0' end='0x181234C0' type='altera_msgdma.prefetcher_csr' /><slave name='sensor_interface.csr' start='0x181234C0' end='0x181234E0' type='Sensor_interface.csr' /><slave name='udp_generator.csr' start='0x181234E0' end='0x18123500' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18123500' end='0x18123520' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18123520' end='0x18123540' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18123540' end='0x18123560' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18123580' end='0x18123590' type='altera_avalon_pio.s1' /><slave name='onchip_flash.csr' start='0x18123590' end='0x18123598' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18123598' end='0x181235A0' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="2" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="288" />
+  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="2048" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18080000' end='0x180F0000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18122800' end='0x18123000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="61" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="onchip_flash.data" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="18.0"
+   enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="50.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+ </module>
+ <module
+   name="ddr3_ram_resetn"
+   kind="altera_reset_bridge"
+   version="18.0"
+   enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="1" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="debug_uart"
+   kind="altera_avalon_uart"
+   version="18.0"
+   enabled="1">
+  <parameter name="baud" value="115200" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+ </module>
+ <module
+   name="descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="18.0"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_descriptor_memory</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName">/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</parameter>
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="8192" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="dual_boot" kind="altera_dual_boot" version="18.0" enabled="0">
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+ </module>
+ <module name="enet_pll" kind="altpll" version="18.0" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="2" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="0" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="2" />
+  <parameter name="CLK3_DUTY_CYCLE" value="50" />
+  <parameter name="CLK3_MULTIPLY_BY" value="5" />
+  <parameter name="CLK3_PHASE_SHIFT" value="-3000" />
+  <parameter name="CLK4_DIVIDE_BY" value="2" />
+  <parameter name="CLK4_DUTY_CYCLE" value="50" />
+  <parameter name="CLK4_MULTIPLY_BY" value="1" />
+  <parameter name="CLK4_PHASE_SHIFT" value="-10000" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_USED" />
+  <parameter name="PORT_clk3" value="PORT_USED" />
+  <parameter name="PORT_clk4" value="PORT_USED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="eth_tse" kind="altera_eth_tse" version="18.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="true" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="nf_phyip_rcfg_enable" value="true" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="18.0"
+   enabled="1">
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="FLASH_TYPE" value="Micron512" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="UNIQUE_ID">$${FILENAME}_ext_flash</parameter>
+  <parameter name="clkFreq" value="0" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module
+   name="ext_flash_clock_bridge"
+   kind="altera_clock_bridge"
+   version="18.0"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   name="frame_timer"
+   kind="altera_avalon_timer"
+   version="18.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="5000" />
+  <parameter name="periodUnits" value="CLOCKS" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="false" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="true" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module name="msgdma_rx" kind="altera_msgdma" version="18.0" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18120000' end='0x18122000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18120000' end='0x18122000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module name="msgdma_tx" kind="altera_msgdma" version="18.0" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18120000' end='0x18122000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18120000' end='0x18122000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="onchip_flash"
+   kind="altera_onchip_flash"
+   version="18.0"
+   enabled="1">
+  <parameter name="AUTO_CLOCK_RATE" value="50000000" />
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="CONFIGURATION_MODE">Single Uncompressed Image</parameter>
+  <parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
+  <parameter name="DATA_INTERFACE" value="Parallel" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="PART_NAME" value="10M50DAF484C6GES" />
+  <parameter name="READ_BURST_COUNT" value="8" />
+  <parameter name="READ_BURST_MODE" value="Incrementing" />
+  <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Hidden,Hidden</parameter>
+  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash</parameter>
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="initializationFileName">D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</parameter>
+  <parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
+  <parameter name="useNonDefaultInitFile" value="false" />
+ </module>
+ <module
+   name="onchip_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="18.0"
+   enabled="0">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName" value="q_sys_onchip_ram" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="output_pio" kind="altera_avalon_pio" version="18.0" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module
+   name="sensor_interface"
+   kind="Sensor_interface"
+   version="1.0"
+   enabled="1" />
+ <module name="sys_clk" kind="clock_source" version="18.0" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   name="sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="18.0"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="10" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="18.0"
+   enabled="1">
+  <parameter name="id" value="-87110914" />
+ </module>
+ <module name="tx_multiplexer" kind="multiplexer" version="18.0" enabled="1">
+  <parameter name="bitsPerSymbol" value="8" />
+  <parameter name="errorWidth" value="1" />
+  <parameter name="numInputInterfaces" value="2" />
+  <parameter name="outChannelWidth" value="1" />
+  <parameter name="packetScheduling" value="true" />
+  <parameter name="schedulingSize" value="512" />
+  <parameter name="symbolsPerBeat" value="4" />
+  <parameter name="useHighBitsOfChannel" value="true" />
+  <parameter name="usePackets" value="true" />
+ </module>
+ <module name="udp_generator" kind="udp_generator" version="1.0" enabled="1" />
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="dual_boot.avalon">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123560" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="ext_flash.avl_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123540" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="eth_tse.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123598" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="msgdma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="msgdma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="onchip_flash.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123590" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="udp_generator.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x181234e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="sensor_interface.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x181234c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18080000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18122800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="msgdma_tx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x181234a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="msgdma_rx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18120000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="output_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="button_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123580" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="debug_uart.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="frame_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.data_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_tx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18120000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_rx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18120000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_tx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18120000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_rx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18120000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.instruction_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.instruction_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.instruction_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18080000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.instruction_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18122800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="cpu.instruction_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_tx.mm_read"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_tx.mm_read"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_rx.mm_write"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.0"
+   start="msgdma_rx.mm_write"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="sensor_interface.data_out"
+   end="udp_generator.data_in" />
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="udp_generator.data_out"
+   end="tx_multiplexer.in1" />
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="tx_multiplexer.out"
+   end="channel_adapter_0.in" />
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="channel_adapter_0.out"
+   end="eth_tse.transmit" />
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="eth_tse.receive"
+   end="msgdma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="18.0"
+   start="msgdma_tx.st_source"
+   end="tx_multiplexer.in0" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="sysid.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="sys_clk_timer.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="cpu.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="output_pio.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="dual_boot.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="button_pio.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="debug_uart.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="onchip_flash.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="tx_multiplexer.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="channel_adapter_0.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="udp_generator.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="sensor_interface.clk" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="frame_timer.clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="descriptor_memory.clk1" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="onchip_ram.clk1" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="msgdma_tx.clock" />
+ <connection kind="clock" version="18.0" start="sys_clk.clk" end="msgdma_rx.clock" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="eth_tse.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="enet_pll.inclk_interface" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="altpll_shift.inclk_interface" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="ddr3_ram.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="eth_tse.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="sys_clk.clk"
+   end="eth_tse.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="18.0"
+   start="ext_flash_clock_bridge.out_clk"
+   end="ext_flash.clock_sink" />
+ <connection
+   kind="interrupt"
+   version="18.0"
+   start="cpu.irq"
+   end="msgdma_tx.csr_irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="18.0"
+   start="cpu.irq"
+   end="msgdma_rx.csr_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="18.0"
+   start="cpu.irq"
+   end="ext_flash.interrupt_sender">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="18.0"
+   start="cpu.irq"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="18.0" start="cpu.irq" end="debug_uart.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="dual_boot.nreset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="onchip_flash.nreset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="sysid.reset" />
+ <connection kind="reset" version="18.0" start="sys_clk.clk_reset" end="cpu.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="button_pio.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="debug_uart.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="tx_multiplexer.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="channel_adapter_0.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="frame_timer.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="onchip_ram.reset1" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="msgdma_tx.reset_n" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="msgdma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="udp_generator.rst" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="sys_clk.clk_reset"
+   end="sensor_interface.rst" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.soft_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="ddr3_ram_resetn.out_reset"
+   end="altpll_shift.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="ddr3_ram_resetn.out_reset"
+   end="enet_pll.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="18.0"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.soft_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/FPGA_firmware/q_sys.qsys b/FPGA_firmware/q_sys.qsys
new file mode 100644
index 0000000..a99ccc7
--- /dev/null
+++ b/FPGA_firmware/q_sys.qsys
@@ -0,0 +1,2812 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altpll_shift
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element button_pio
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element button_pio.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863168";
+         type = "String";
+      }
+   }
+   element calibration_ram
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element calibration_ram.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406860800";
+         type = "String";
+      }
+   }
+   element calibration_ram.s2
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element channel_adapter_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element cpu
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element cpu.debug_mem_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406857728";
+         type = "String";
+      }
+   }
+   element ddr3_ram
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element ddr3_ram.avl
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element ddr3_ram_resetn
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element debug_uart
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element debug_uart.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406862880";
+         type = "String";
+      }
+   }
+   element descriptor_memory
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element descriptor_memory.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406847488";
+         type = "String";
+      }
+   }
+   element enet_pll
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element eth_tse
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element eth_tse.control_port
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406859776";
+         type = "String";
+      }
+   }
+   element ext_flash
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element ext_flash.avl_csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863136";
+         type = "String";
+      }
+   }
+   element ext_flash.avl_mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "335544320";
+         type = "String";
+      }
+   }
+   element ext_flash_clock_bridge
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element frame_timer
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element frame_timer.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406862848";
+         type = "String";
+      }
+   }
+   element glad
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
+   element glad.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406861824";
+         type = "String";
+      }
+   }
+   element msgdma_rx
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element msgdma_rx.csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863072";
+         type = "String";
+      }
+   }
+   element msgdma_rx.prefetcher_csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406862976";
+         type = "String";
+      }
+   }
+   element msgdma_tx
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element msgdma_tx.csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863104";
+         type = "String";
+      }
+   }
+   element msgdma_tx.prefetcher_csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863008";
+         type = "String";
+      }
+   }
+   element onchip_flash
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element onchip_flash.csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863200";
+         type = "String";
+      }
+   }
+   element onchip_flash.data
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "404750336";
+         type = "String";
+      }
+   }
+   element onchip_ram
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element onchip_ram.s1
+   {
+      datum baseAddress
+      {
+         value = "403767296";
+         type = "String";
+      }
+   }
+   element output_pio
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element output_pio.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406862912";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element sensor_interface
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element sensor_interface.csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863184";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406862944";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sysid.clk
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863208";
+         type = "String";
+      }
+   }
+   element tx_multiplexer
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element udp_generator
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element udp_generator.csr
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "406863040";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="hit20v3.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altpll_shift_c0"
+   internal="altpll_shift.c0"
+   type="clock"
+   dir="start" />
+ <interface name="altpll_shift_c1" internal="altpll_shift.c1" />
+ <interface name="altpll_shift_c2" internal="altpll_shift.c2" />
+ <interface
+   name="altpll_shift_locked_conduit"
+   internal="altpll_shift.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="button_pio_external_connection"
+   internal="button_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="clock_bridge_0_in_clk"
+   internal="ext_flash_clock_bridge.in_clk"
+   type="clock"
+   dir="end" />
+ <interface name="ddr2_lo_latency_128m_auxfull" internal=".auxfull" />
+ <interface name="ddr2_lo_latency_128m_global_reset_n" internal=".global_reset_n" />
+ <interface name="ddr2_lo_latency_128m_memory" internal=".memory" />
+ <interface
+   name="ddr3_ram_pll_ref_clk"
+   internal="ddr3_ram.pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="debug_uart_external_connection"
+   internal="debug_uart.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="dipsw_pio_out" internal=".external_connection" />
+ <interface name="enet_pll_c0" internal="enet_pll.c0" type="clock" dir="start" />
+ <interface name="enet_pll_c1" internal="enet_pll.c1" type="clock" dir="start" />
+ <interface name="enet_pll_c2" internal="enet_pll.c2" type="clock" dir="start" />
+ <interface name="enet_pll_c3" internal="enet_pll.c3" type="clock" dir="start" />
+ <interface name="enet_pll_c4" internal="enet_pll.c4" type="clock" dir="start" />
+ <interface
+   name="enet_pll_locked_conduit"
+   internal="enet_pll.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_mdio_connection"
+   internal="eth_tse.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_rgmii_connection"
+   internal="eth_tse.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_status_connection"
+   internal="eth_tse.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_rx_clock_connection"
+   internal="eth_tse.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_tx_clock_connection"
+   internal="eth_tse.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface name="eth_tse_serial_connection" internal="eth_tse.serial_connection" />
+ <interface
+   name="eth_tse_status_led_connection"
+   internal="eth_tse.status_led_connection" />
+ <interface
+   name="ext_flash_flash_dataout"
+   internal="ext_flash.flash_dataout"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_dclk_out"
+   internal="ext_flash.flash_dclk_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_ncs"
+   internal="ext_flash.flash_ncs"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="frame_timer"
+   internal="frame_timer.external_port"
+   type="conduit"
+   dir="end" />
+ <interface name="jtag_avalon_master_clk_reset" internal=".clk_reset" />
+ <interface
+   name="led_pio_external_connection"
+   internal="output_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_if_ddr3_emif_0_status"
+   internal="ddr3_ram.status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_resetn_in_reset"
+   internal="ddr3_ram_resetn.in_reset"
+   type="reset"
+   dir="end" />
+ <interface name="memory" internal="ddr3_ram.memory" type="conduit" dir="end" />
+ <interface name="ref_clk_clk_in" internal=".clk_in" />
+ <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="sensor"
+   internal="sensor_interface.sensor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_status"
+   internal="sensor_interface.status_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_synchro"
+   internal="sensor_interface.synchro"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <module name="altpll_shift" kind="altpll" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="15000" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_UNUSED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="button_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="9" />
+ </module>
+ <module
+   name="calibration_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_calibration_ram</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="dataWidth2" value="16" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   name="channel_adapter_0"
+   kind="channel_adapter"
+   version="19.1"
+   enabled="1">
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="inChannelWidth" value="1" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="inUsePackets" value="true" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="outMaxChannel" value="1" />
+ </module>
+ <module name="cpu" kind="altera_nios2_gen2" version="19.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="13" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="13" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="2" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="288" />
+  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="2048" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="61" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="ext_flash.avl_mem" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="19.1"
+   enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+ </module>
+ <module
+   name="ddr3_ram_resetn"
+   kind="altera_reset_bridge"
+   version="19.1"
+   enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="1" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="debug_uart"
+   kind="altera_avalon_uart"
+   version="19.1"
+   enabled="1">
+  <parameter name="baud" value="115200" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+ </module>
+ <module
+   name="descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_descriptor_memory</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName">/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</parameter>
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="8192" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="enet_pll" kind="altpll" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="2" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="0" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="2" />
+  <parameter name="CLK3_DUTY_CYCLE" value="50" />
+  <parameter name="CLK3_MULTIPLY_BY" value="5" />
+  <parameter name="CLK3_PHASE_SHIFT" value="-3000" />
+  <parameter name="CLK4_DIVIDE_BY" value="2" />
+  <parameter name="CLK4_DUTY_CYCLE" value="50" />
+  <parameter name="CLK4_MULTIPLY_BY" value="1" />
+  <parameter name="CLK4_PHASE_SHIFT" value="-10000" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_USED" />
+  <parameter name="PORT_clk3" value="PORT_USED" />
+  <parameter name="PORT_clk4" value="PORT_USED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="eth_tse" kind="altera_eth_tse" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="true" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="nf_phyip_rcfg_enable" value="true" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   enabled="1">
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="FLASH_TYPE" value="Micron512" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="UNIQUE_ID">$${FILENAME}_ext_flash</parameter>
+  <parameter name="clkFreq" value="0" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module
+   name="ext_flash_clock_bridge"
+   kind="altera_clock_bridge"
+   version="19.1"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   name="frame_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="5000" />
+  <parameter name="periodUnits" value="CLOCKS" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="false" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="true" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="glad"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="0">
+  <parameter name="allowInSystemMemoryContentEditor" value="true" />
+  <parameter name="autoInitializationFileName" value="q_sys_glad" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="glad" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="msgdma_rx" kind="altera_msgdma" version="19.1" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module name="msgdma_tx" kind="altera_msgdma" version="19.1" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="onchip_flash"
+   kind="altera_onchip_flash"
+   version="19.1"
+   enabled="1">
+  <parameter name="AUTO_CLOCK_RATE" value="50000000" />
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="CONFIGURATION_MODE">Single Uncompressed Image</parameter>
+  <parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
+  <parameter name="DATA_INTERFACE" value="Parallel" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="PART_NAME" value="10M50DAF484C6GES" />
+  <parameter name="READ_BURST_COUNT" value="8" />
+  <parameter name="READ_BURST_MODE" value="Incrementing" />
+  <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
+  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash</parameter>
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="initializationFileName">D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</parameter>
+  <parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
+  <parameter name="useNonDefaultInitFile" value="false" />
+ </module>
+ <module
+   name="onchip_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="0">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName" value="q_sys_onchip_ram" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="output_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="sensor_interface" kind="sensor_recon" version="1" enabled="1" />
+ <module name="sys_clk" kind="clock_source" version="19.1" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   name="sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="10" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="19.1"
+   enabled="1">
+  <parameter name="id" value="-87110914" />
+ </module>
+ <module name="tx_multiplexer" kind="multiplexer" version="19.1" enabled="1">
+  <parameter name="bitsPerSymbol" value="8" />
+  <parameter name="errorWidth" value="1" />
+  <parameter name="numInputInterfaces" value="2" />
+  <parameter name="outChannelWidth" value="1" />
+  <parameter name="packetScheduling" value="true" />
+  <parameter name="schedulingSize" value="512" />
+  <parameter name="symbolsPerBeat" value="4" />
+  <parameter name="useHighBitsOfChannel" value="true" />
+  <parameter name="usePackets" value="true" />
+ </module>
+ <module name="udp_generator" kind="udp_generator" version="1.0" enabled="1" />
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="sensor_interface.calibration_ram_interface"
+   end="calibration_ram.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d20" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="eth_tse.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d68" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d00" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403ce0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d60" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="udp_generator.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403cc0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sensor_interface.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d50" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18402800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403ca0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403c80" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403c60" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="output_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403c40" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="button_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403d40" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="debug_uart.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403c20" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="frame_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403c00" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="calibration_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="19.1" start="cpu.data_master" end="glad.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18402800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="sensor_interface.data_out"
+   end="udp_generator.data_in" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="udp_generator.data_out"
+   end="tx_multiplexer.in1" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="tx_multiplexer.out"
+   end="channel_adapter_0.in" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="channel_adapter_0.out"
+   end="eth_tse.transmit" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="eth_tse.receive"
+   end="msgdma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="msgdma_tx.st_source"
+   end="tx_multiplexer.in0" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="sysid.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sys_clk_timer.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="cpu.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="output_pio.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="button_pio.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="debug_uart.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="onchip_flash.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="tx_multiplexer.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="channel_adapter_0.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="udp_generator.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="frame_timer.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sensor_interface.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="descriptor_memory.clk1" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="onchip_ram.clk1" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk1" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="glad.clk1" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk2" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_tx.clock" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_rx.clock" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="enet_pll.inclk_interface" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="altpll_shift.inclk_interface" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="ext_flash.clock_sink" />
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_tx.csr_irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_rx.csr_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="ext_flash.interrupt_sender">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="19.1" start="cpu.irq" end="debug_uart.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="onchip_flash.nreset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sysid.reset" />
+ <connection kind="reset" version="19.1" start="sys_clk.clk_reset" end="cpu.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="button_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="debug_uart.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="tx_multiplexer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="channel_adapter_0.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="frame_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="onchip_ram.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="calibration_ram.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="glad.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="calibration_ram.reset2" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_tx.reset_n" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="udp_generator.rst" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sensor_interface.rst" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.soft_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="altpll_shift.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="enet_pll.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.soft_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/FPGA_firmware/q_sys.sopcinfo b/FPGA_firmware/q_sys.sopcinfo
new file mode 100644
index 0000000..a6459b7
--- /dev/null
+++ b/FPGA_firmware/q_sys.sopcinfo
@@ -0,0 +1,45271 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="q_sys" kind="q_sys" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.10.11.10:10:09 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1728634208</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>clock_bridge_0_in_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>clock_bridge_0_in_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>clock_bridge_0_in_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>ddr3_ram_pll_ref_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>ddr3_ram_pll_ref_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>ddr3_ram_pll_ref_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_rx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_rx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_rx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_tx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_tx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>eth_tse_pcs_mac_tx_clock_connection</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SYS_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>sys_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sys_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SYS_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sys_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module name="altpll_shift" kind="altpll" version="19.1" path="altpll_shift">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_elaboration</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_post_edit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTENDED_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_CLOCK">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIMARY_CLOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>20000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK1_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OPERATION_MODE">
+   <type>java.lang.String</type>
+   <value>NORMAL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_CONF_DONE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMPENSATE_CLOCK">
+   <type>java.lang.String</type>
+   <value>CLK0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_SIGNAL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_HIGH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_LOW">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INVALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_LOSSCLK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_VCO">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_TYPE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FEEDBACK_SOURCE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPREAD_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DOWN_SPREAD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>15000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena2">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena3">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk6">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk7">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk8">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk9">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATAOUT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ACTIVECLOCK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKLOSS">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBIN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PLLENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKSWITCH">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ARESET">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PFDENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANACLR">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANREAD">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANWRITE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_LOCKED">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CONFIGUPDATE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBOUT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASESTEP">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEUPDOWN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLKENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOOVERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOUNDERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_FREQUENCY_CONTROL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_PHASE_SHIFT_STEP">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USING_FBMIMICBIDIR_PORT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN_MIF_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK">
+   <type>java.lang.String</type>
+   <value>NO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CONSTANTS">
+   <type>java.lang.String</type>
+   <value>CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_PRIVATES">
+   <type>java.lang.String</type>
+   <value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_USED_PORTS">
+   <type>java.lang.String</type>
+   <value>UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_NUMERIC">
+   <type>java.lang.String</type>
+   <value>IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_MF_PORTS">
+   <type>java.lang.String</type>
+   <value>MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IF_PORTS">
+   <type>java.lang.String</type>
+   <value>IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>inclk_interface</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="inclk_interface" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="inclk_interface_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="pll_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>inclk_interface_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface name="c0" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>250000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="areset_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>areset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+  <interface name="locked_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="button_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   path="button_pio">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CAPTURE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>9</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EDGE_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_IN</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_OUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_TRI</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IRQ_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,pio-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>gpio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>pio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,gpio-bank-width</name>
+   <value>9</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.resetvalue</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="bitClearingEdgeCapReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitModifyingOutReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="captureEdge">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="direction">
+   <type>java.lang.String</type>
+   <value>Input</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="edgeType">
+   <type>java.lang.String</type>
+   <value>RISING</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateIRQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="irqType">
+   <type>java.lang.String</type>
+   <value>LEVEL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDoTestBenchWiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDrivenValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="width">
+   <type>int</type>
+   <value>9</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="derived_has_tri">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_in">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_do_test_bench_wiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_capture">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_edge_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_irq_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_irq">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>4</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_port</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="calibration_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="calibration_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>q_sys_calibration_ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>640</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>16</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>q_sys_calibration_ram</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>onchip_mem.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>640</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_calibration_ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>q_sys_calibration_ram.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="s2" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address2</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>chipselect2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>clken2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>write2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata2</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata2</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable2</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk2" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset2" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="channel_adapter_0"
+   kind="channel_adapter"
+   version="19.1"
+   path="channel_adapter_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="inChannelWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inMaxChannel">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outMaxChannel">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inBitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>java.lang.String</type>
+   <value>YES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmpty">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inSymbolsPerBeat">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseReady">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inReadyLatency">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>in_channel</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>channel</role>
+   </port>
+  </interface>
+  <interface name="out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module name="cpu" kind="altera_nios2_gen2" version="19.1" path="cpu">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>debug.hostConnection</name>
+   <value>type jtag id 70:34|110:135</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIG_ENDIAN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BREAK_ADDR</name>
+   <value>0x18402820</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_FREQ</name>
+   <value>50000000u</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ID_SIZE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ID_VALUE</name>
+   <value>0x00000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_IMPLEMENTATION</name>
+   <value>"fast"</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
+   <value>29</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_BYPASS_MASK</name>
+   <value>0x80000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_SIZE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EXCEPTION_ADDR</name>
+   <value>0x08000120</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_DEBUG_CORE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_DEBUG_STUB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_LINE_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_SIZE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INITDA_SUPPORTED</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
+   <value>29</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.OCI_VERSION</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_ADDR</name>
+   <value>0x14000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.DataCacheVictimBufImpl</name>
+   <value>ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.HDLSimCachesCleared</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.breakOffset</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.breakSlave</name>
+   <value>cpu.debug_mem_slave</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.cpuArchitecture</name>
+   <value>Nios II</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.exceptionOffset</name>
+   <value>288</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.exceptionSlave</name>
+   <value>ddr3_ram.avl</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.resetOffset</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.resetSlave</name>
+   <value>ext_flash.avl_mem</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,nios2-1.1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>cpu</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>nios2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,exception-addr</name>
+   <value>0x08000120</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,has-initda</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,has-mul</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,implementation</name>
+   <value>"fast"</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,reset-addr</name>
+   <value>0x14000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000u</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.dcache-line-size</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.dcache-size</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.icache-line-size</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.icache-size</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="tmr_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_disable_tmr_inj">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_showUnpublishedSettings">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_showInternalSettings">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_preciseIllegalMemAccessException">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportPCB">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportdebuginfo">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_clearXBitsLDNonBypass">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bigEndian">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_export_large_RAMs">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="register_file_por">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_synopsys_translate_on_off">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_third_party_synthesis">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_add_scan_mode_input">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_oci_version">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_fast_register_read">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportHostDebugPort">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_oci_export_jtag_signals">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_avalonDebugPortPresent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_alwaysEncrypt">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="io_regionbase">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="io_regionsize">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_support31bitdcachebypass">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateTrace">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_allow_break_inst">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateTestEndChecker">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ecc_sim_test_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_disableocitrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateMonitors">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_HDLSimCachesCleared">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_HBreakTest">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_breakslaveoveride">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_useLimit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_autoAssignTlbPtrSz">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuReset">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_removeRAMinit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_tmr_output_disable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_shadowRegisterSets">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_numOfInstRegion">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_numOfDataRegion">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcOffset">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOffset">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionOffset">
+   <type>int</type>
+   <value>288</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuID">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakOffset">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="userDefinedSettings">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tracefilename">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetSlave">
+   <type>java.lang.String</type>
+   <value>ext_flash.avl_mem</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcSlave">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionSlave">
+   <type>java.lang.String</type>
+   <value>ddr3_ram.avl</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakSlave">
+   <type>java.lang.String</type>
+   <value>cpu.jtag_debug_module</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_interruptControllerType">
+   <type>java.lang.String</type>
+   <value>Internal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_branchpredictiontype">
+   <type>java.lang.String</type>
+   <value>Dynamic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bhtPtrSz">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuArchRev">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stratix_dspblock_shift_mul">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="shifterType">
+   <type>java.lang.String</type>
+   <value>fast_le_shift</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="multiplierType">
+   <type>java.lang.String</type>
+   <value>mul_fast32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_shift_choice">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_32_impl">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_64_impl">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="shift_rot_impl">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dividerType">
+   <type>java.lang.String</type>
+   <value>no_div</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_minInstRegionSize">
+   <type>int</type>
+   <value>12</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_minDataRegionSize">
+   <type>int</type>
+   <value>12</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_uitlbNumEntries">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_udtlbNumEntries">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_tlbPtrSz">
+   <type>int</type>
+   <value>7</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_tlbNumWays">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_processIDNumBits">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="impl">
+   <type>java.lang.String</type>
+   <value>Fast</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_size">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fa_cache_line">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fa_cache_linesize">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_tagramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_numTCIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_burstType">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_bursts">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_victim_buf_impl">
+   <type>java.lang.String</type>
+   <value>ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_size">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_tagramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_numTCDM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportvectors">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_usedesignware">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ic_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_rf_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_mmu_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_dc_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_itcm_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_dtcm_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="regfile_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ocimem_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ocimem_ramInit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bht_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cdx_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpx_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_triggerArming">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_debugReqSignals">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_assignJtagInstanceID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_jtagInstanceID">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_OCIOnchipTrace">
+   <type>java.lang.String</type>
+   <value>_128</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_hwbreakpoint">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_datatrigger">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_traceType">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_traceStorage">
+   <type>java.lang.String</type>
+   <value>onchip_trace</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="master_addr_map">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="flash_instruction_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="flash_instruction_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_0_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_0_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_1_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_1_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_2_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_2_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_3_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_3_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_high_performance_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_high_performance_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_high_performance_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_high_performance_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetAbsoluteAddr">
+   <type>int</type>
+   <value>335544320</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionAbsoluteAddr">
+   <type>int</type>
+   <value>134218016</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakAbsoluteAddr">
+   <type>int</type>
+   <value>406857760</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcAbsAddr">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_bursts_derived">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_size_derived">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakSlave_derived">
+   <type>java.lang.String</type>
+   <value>cpu.debug_mem_slave</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_lineSize_derived">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ioregionBypassDCache">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bit31BypassDCache">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="translate_on">
+   <type>java.lang.String</type>
+   <value> "synthesis translate_on"  </value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="translate_off">
+   <type>java.lang.String</type>
+   <value> "synthesis translate_off" </value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_onchiptrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_offchiptrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_insttrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_datatrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instAddrWidth">
+   <type>int</type>
+   <value>29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="faAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>flash_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="dataAddrWidth">
+   <type>int</type>
+   <value>29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>data_master</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster0AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster2AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster3AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="dataMasterHighPerformanceAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>data_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instSlaveMapParam">
+   <type>java.lang.String</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="faSlaveMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>flash_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="dataSlaveMapParam">
+   <type>java.lang.String</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>data_master</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster1MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster2MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster3MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster0MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster1MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster2MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster3MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="dataMasterHighPerformanceMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>data_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instructionMasterHighPerformanceMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamilyName">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="internalIrqMaskSystemInfo">
+   <type>long</type>
+   <value>61</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>INTERRUPTS_USED</sysinfo_type>
+   <sysinfo_arg>irq</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_a">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_a</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_b">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_b</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_c">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_c</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFeaturesSystemInfo">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN">
+   <type>java.lang.Integer</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_CLK_RESET_DOMAIN">
+   <type>java.lang.Integer</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+  <interface name="data_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>debug.providesServices</name>
+    <value>master</value>
+   </assignment>
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>d_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>d_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>d_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>d_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>d_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>d_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>d_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>d_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_debugaccess_to_roms</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ddr3_ram</moduleName>
+    <slaveName>avl</slaveName>
+    <name>ddr3_ram.avl</name>
+    <baseAddress>134217728</baseAddress>
+    <span>134217728</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>avl_csr</slaveName>
+    <name>ext_flash.avl_csr</name>
+    <baseAddress>406863136</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>avl_mem</slaveName>
+    <name>ext_flash.avl_mem</name>
+    <baseAddress>335544320</baseAddress>
+    <span>67108864</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>control_port</slaveName>
+    <name>eth_tse.control_port</name>
+    <baseAddress>406859776</baseAddress>
+    <span>1024</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sysid</moduleName>
+    <slaveName>control_slave</slaveName>
+    <name>sysid.control_slave</name>
+    <baseAddress>406863208</baseAddress>
+    <span>8</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>csr</slaveName>
+    <name>msgdma_tx.csr</name>
+    <baseAddress>406863104</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>csr</slaveName>
+    <name>msgdma_rx.csr</name>
+    <baseAddress>406863072</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>csr</slaveName>
+    <name>onchip_flash.csr</name>
+    <baseAddress>406863200</baseAddress>
+    <span>8</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>udp_generator</moduleName>
+    <slaveName>csr</slaveName>
+    <name>udp_generator.csr</name>
+    <baseAddress>406863040</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sensor_interface</moduleName>
+    <slaveName>csr</slaveName>
+    <name>sensor_interface.csr</name>
+    <baseAddress>406863184</baseAddress>
+    <span>16</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>data</slaveName>
+    <name>onchip_flash.data</name>
+    <baseAddress>404750336</baseAddress>
+    <span>1441792</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>cpu</moduleName>
+    <slaveName>debug_mem_slave</slaveName>
+    <name>cpu.debug_mem_slave</name>
+    <baseAddress>406857728</baseAddress>
+    <span>2048</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>prefetcher_csr</slaveName>
+    <name>msgdma_tx.prefetcher_csr</name>
+    <baseAddress>406863008</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>prefetcher_csr</slaveName>
+    <name>msgdma_rx.prefetcher_csr</name>
+    <baseAddress>406862976</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>406847488</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>s1</slaveName>
+    <name>sys_clk_timer.s1</name>
+    <baseAddress>406862944</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>output_pio</moduleName>
+    <slaveName>s1</slaveName>
+    <name>output_pio.s1</name>
+    <baseAddress>406862912</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>button_pio</moduleName>
+    <slaveName>s1</slaveName>
+    <name>button_pio.s1</name>
+    <baseAddress>406863168</baseAddress>
+    <span>16</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>s1</slaveName>
+    <name>debug_uart.s1</name>
+    <baseAddress>406862880</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>frame_timer</moduleName>
+    <slaveName>s1</slaveName>
+    <name>frame_timer.s1</name>
+    <baseAddress>406862848</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>s1</slaveName>
+    <name>calibration_ram.s1</name>
+    <baseAddress>406860800</baseAddress>
+    <span>640</span>
+   </memoryBlock>
+  </interface>
+  <interface name="instruction_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>i_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>i_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>i_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>i_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>i_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ddr3_ram</moduleName>
+    <slaveName>avl</slaveName>
+    <name>ddr3_ram.avl</name>
+    <baseAddress>134217728</baseAddress>
+    <span>134217728</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>avl_mem</slaveName>
+    <name>ext_flash.avl_mem</name>
+    <baseAddress>335544320</baseAddress>
+    <span>67108864</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>data</slaveName>
+    <name>onchip_flash.data</name>
+    <baseAddress>404750336</baseAddress>
+    <span>1441792</span>
+   </memoryBlock>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>cpu</moduleName>
+    <slaveName>debug_mem_slave</slaveName>
+    <name>cpu.debug_mem_slave</name>
+    <baseAddress>406857728</baseAddress>
+    <span>2048</span>
+   </memoryBlock>
+  </interface>
+  <interface name="irq" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>cpu.data_master</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>csr_irq</slaveName>
+    <name>msgdma_tx.csr_irq</name>
+    <interruptNumber>2</interruptNumber>
+   </interrupt>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>csr_irq</slaveName>
+    <name>msgdma_rx.csr_irq</name>
+    <interruptNumber>3</interruptNumber>
+   </interrupt>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>interrupt_sender</slaveName>
+    <name>ext_flash.interrupt_sender</name>
+    <interruptNumber>5</interruptNumber>
+   </interrupt>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>irq</slaveName>
+    <name>sys_clk_timer.irq</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>irq</slaveName>
+    <name>debug_uart.irq</name>
+    <interruptNumber>4</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="debug_reset_request" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>none</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>debug_reset_request</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="debug_mem_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.hideDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>qsys.ui.connect</name>
+    <value>instruction_master,data_master</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>2048</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>debug_mem_slave_address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_debugaccess</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface
+     name="custom_instruction_master"
+     kind="nios_custom_instruction_master"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="CIName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressWidth">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockCycle">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="enabled">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="opcodeExtension">
+    <type>int</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="sharedCombinationalAndMulticycle">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>nios_custom_instruction</type>
+   <isStart>true</isStart>
+   <port>
+    <name>dummy_ci_port</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readra</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="19.1"
+   path="ddr3_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>ABS_RAM_MEM_INIT_FILENAME</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.map.memory</name>
+   <value>mem_model.memory</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.class</name>
+   <value>altera_mem_if_ddr3_mem_model</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_PARITY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0</name>
+   <value>0001000010001</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_CALIB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET</name>
+   <value>0001100010000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET_MIRR</name>
+   <value>0001010001000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_MIRR</name>
+   <value>0001000001001</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_CALIB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_OCD_ENABLE</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR2</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR2_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR3</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR3_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ADDR_CMD_DDR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ADDR_RATE_RATIO</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_ADDR_WIDTH</name>
+   <value>28</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_BANKADDR_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CLK_EN_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CLK_PAIR_COUNT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CONTROL_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CS_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_DM_WIDTH</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_DQ_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_ODT_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RATE_RATIO</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RLAT_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RRANK_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WLAT_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WRANK_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WRITE_DQS_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ALTMEMPHY_COMPATIBLE_MODE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AP_MODE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AP_MODE_EN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CFG_TCCD</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CFG_TCCD_NS</name>
+   <value>2.5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_PCH_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_RD_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_WR_TO_WR_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CUT_NEW_FAMILY_TIMING</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DATA_RATE_RATIO</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DAT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_DEPTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_FAMILY</name>
+   <value>MAX 10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_FAMILY_PARAM</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DISABLE_CHILD_MESSAGING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DISCRETE_FLY_BY</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DQ_DDR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DUPLICATE_AC</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FLY_BY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FORCE_DQS_TRACKING</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FORCE_SHADOW_REGS</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HARD_EMIF</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HARD_PHY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS_SIMULATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS_VERIFICATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HPS_PROTOCOL</name>
+   <value>DEFAULT</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.IS_ES_DEVICE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM_EXTENDED_CONFIG</name>
+   <value>0x000000000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ASR</name>
+   <value>Manual</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ATCL</name>
+   <value>Disabled</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ATCL_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_AUTO_LEVELING_MODE</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BANKADDR_WIDTH</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BL</name>
+   <value>OTF</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BT</name>
+   <value>Sequential</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BURST_LENGTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CK_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_EN_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_FREQ</name>
+   <value>300.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_FREQ_MAX</name>
+   <value>800.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_MAX_NS</name>
+   <value>1.25</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_MAX_PS</name>
+   <value>1250.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_TO_DQS_CAPTURE_DELAY</name>
+   <value>100000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_COL_ADDR_WIDTH</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DLL_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQS_TO_CLK_CAPTURE_DELAY</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQ_PER_DQS</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQ_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DRV_STR</name>
+   <value>RZQ/6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_FORMAT</name>
+   <value>DISCRETE</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_GUARANTEED_WRITE_INIT</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH_MIN</name>
+   <value>13</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_BANKADDR_WIDTH</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_BOARD_BASE_DELAY</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CHIP_BITS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CK_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CLK_EN_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CLK_PAIR_COUNT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_COL_ADDR_WIDTH</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CONTROL_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_PER_DIMM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_PER_RANK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DM_PINS_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DM_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQSN_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQ_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_LRDIMM_RM</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_NUMBER_OF_RANKS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ODT_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_RD_TO_WR_TURNAROUND_OCT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_READ_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ROW_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_SIM_VALID_WINDOW</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_WRITE_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_WR_TO_RD_TURNAROUND_OCT</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_INIT_EN</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_INIT_FILE</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_LEVELING</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_LRDIMM_ENABLED</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING_DEC</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_DIMMS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DEVICE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DIMM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_PD</name>
+   <value>DLL off</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RANK_MULTIPLICATION_FACTOR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_REGDIMM_ENABLED</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ROW_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RTT_NOM</name>
+   <value>ODT Disabled</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RTT_WR</name>
+   <value>Dynamic ODT off</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_SRT</name>
+   <value>Normal</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TCL</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TDQSCK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TFAW</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TFAW_NS</name>
+   <value>30.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TINIT_CK</name>
+   <value>150000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TINIT_US</name>
+   <value>500</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TMRD_CK</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRAS</name>
+   <value>11</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRAS_NS</name>
+   <value>35.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRC</name>
+   <value>15</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRCD</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRCD_NS</name>
+   <value>13.75</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TREFI</name>
+   <value>2341</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TREFI_US</name>
+   <value>7.8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRFC</name>
+   <value>34</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRFC_NS</name>
+   <value>110.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRP</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRP_NS</name>
+   <value>13.75</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRRD</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRRD_NS</name>
+   <value>6.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRTP</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRTP_NS</name>
+   <value>7.5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWR</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWR_NS</name>
+   <value>15.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWTR</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TYPE</name>
+   <value>DDR3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_USER_LEVELING_MODE</name>
+   <value>Leveling</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_VENDOR</name>
+   <value>JEDEC</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_VERBOSE</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_WTCL</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_WTCL_INT</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_BL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_BT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_CAS_LATENCY</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_DLL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_PD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_WR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_AL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_DLL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_DQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_ODS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_QOFF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_RDQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_RTT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_TDQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_WL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_ASR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_CWL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_RTT_WR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_SRF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_SRT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR_AA</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR_RF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MRS_MIRROR_PING_PONG_ATSO</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.NEXTGEN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY</name>
+   <value>MAX10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PINGPONGPHY_EN</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PRE_V_SERIES_FAMILY</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RATE</name>
+   <value>Half</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM_CONFIG</name>
+   <value>0000000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.REFRESH_BURST_VALIDATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SCC_DATA_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SPEED_GRADE</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SYS_INFO_DEVICE_FAMILY</name>
+   <value>MAX 10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDH</name>
+   <value>45</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCK</name>
+   <value>225</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDL</name>
+   <value>1200</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDM</name>
+   <value>900</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDS</name>
+   <value>450</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSQ</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSS</name>
+   <value>0.27</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDS</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDSH</name>
+   <value>0.18</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDSS</name>
+   <value>0.18</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TIH</name>
+   <value>120</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TIS</name>
+   <value>170</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TQH</name>
+   <value>0.38</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TQSH</name>
+   <value>0.4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TRK_PARALLEL_SCC_LOAD</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_DQS_TRACKING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_HPS_DQS_TRACKING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_MEM_CLK_FREQ</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_SHADOW_REGS</name>
+   <value>false</value>
+  </assignment>
+  <parameter name="AC_ROM_MR0">
+   <type>java.lang.String</type>
+   <value>0001000010001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_MIRR">
+   <type>java.lang.String</type>
+   <value>0001000001001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_CALIB">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_DLL_RESET">
+   <type>java.lang.String</type>
+   <value>0001100010000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR">
+   <type>java.lang.String</type>
+   <value>0001010001000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_CALIB">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_OCD_ENABLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR2">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR2_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR3">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR3_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_BL">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_BT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_CAS_LATENCY">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_DLL">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_WR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_PD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_DLL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_ODS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_RTT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_AL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_WL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_TDQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_QOFF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_DQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_RDQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_CWL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_ASR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_SRT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_SRF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_RTT_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR_RF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR_AA">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_READ_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCC_DATA_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN">
+   <type>int</type>
+   <value>13</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_COL_ADDR_WIDTH">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DM_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_PER_RANK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_NUMBER_OF_RANKS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_PER_DIMM">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CONTROL_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BURST_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_LEVELING">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CHIP_BITS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CK_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CLK_PAIR_COUNT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_MAX_NS">
+   <type>double</type>
+   <value>1.25</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_MAX_PS">
+   <type>double</type>
+   <value>1250.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRC">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRAS">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRCD">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRP">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TREFI">
+   <type>int</type>
+   <value>2341</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRFC">
+   <type>int</type>
+   <value>34</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TCCD">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWR">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TFAW">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRRD">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRTP">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY">
+   <type>int</type>
+   <value>100</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY">
+   <type>int</type>
+   <value>100000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ODT_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_WTCL_INT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLY_BY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_LRDIMM_RM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TYPE">
+   <type>java.lang.String</type>
+   <value>DDR3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ATCL_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_REGDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_LRDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VENDOR">
+   <type>java.lang.String</type>
+   <value>JEDEC</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_FORMAT">
+   <type>java.lang.String</type>
+   <value>DISCRETE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_PARITY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM_CONFIG">
+   <type>java.lang.String</type>
+   <value>0000000000000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM_EXTENDED_CONFIG">
+   <type>java.lang.String</type>
+   <value>0x000000000000000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DISCRETE_FLY_BY">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_DEPTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_MIRROR_ADDRESSING">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ_MAX">
+   <type>double</type>
+   <value>800.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ROW_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_COL_ADDR_WIDTH">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQ_PER_DQS">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DM_PINS_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQSN_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_DIMMS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NEXTGEN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_BOARD_BASE_DELAY">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_SIM_VALID_WINDOW">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_GUARANTEED_WRITE_INIT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VERBOSE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PINGPONGPHY_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUPLICATE_AC">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REFRESH_BURST_VALIDATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AP_MODE_EN">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AP_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BL">
+   <type>java.lang.String</type>
+   <value>OTF</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BT">
+   <type>java.lang.String</type>
+   <value>Sequential</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ASR">
+   <type>java.lang.String</type>
+   <value>Manual</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_SRT">
+   <type>java.lang.String</type>
+   <value>Normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_PD">
+   <type>java.lang.String</type>
+   <value>DLL off</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DRV_STR">
+   <type>java.lang.String</type>
+   <value>RZQ/6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DLL_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RTT_NOM">
+   <type>java.lang.String</type>
+   <value>ODT Disabled</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RTT_WR">
+   <type>java.lang.String</type>
+   <value>Dynamic ODT off</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_WTCL">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ATCL">
+   <type>java.lang.String</type>
+   <value>Disabled</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TCL">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_AUTO_LEVELING_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_USER_LEVELING_MODE">
+   <type>java.lang.String</type>
+   <value>Leveling</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_INIT_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_INIT_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DAT_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TIS">
+   <type>int</type>
+   <value>170</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TIH">
+   <type>int</type>
+   <value>120</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDS">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDH">
+   <type>int</type>
+   <value>45</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSQ">
+   <type>int</type>
+   <value>100</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TQH">
+   <type>double</type>
+   <value>0.38</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCK">
+   <type>int</type>
+   <value>225</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDS">
+   <type>int</type>
+   <value>450</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDM">
+   <type>int</type>
+   <value>900</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDL">
+   <type>int</type>
+   <value>1200</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSS">
+   <type>double</type>
+   <value>0.27</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TQSH">
+   <type>double</type>
+   <value>0.4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDSH">
+   <type>double</type>
+   <value>0.18</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDSS">
+   <type>double</type>
+   <value>0.18</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TINIT_US">
+   <type>int</type>
+   <value>500</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TINIT_CK">
+   <type>int</type>
+   <value>150000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TDQSCK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TMRD_CK">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRAS_NS">
+   <type>double</type>
+   <value>35.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRCD_NS">
+   <type>double</type>
+   <value>13.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRP_NS">
+   <type>double</type>
+   <value>13.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TREFI_US">
+   <type>double</type>
+   <value>7.8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRFC_NS">
+   <type>double</type>
+   <value>110.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TCCD_NS">
+   <type>double</type>
+   <value>2.5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWR_NS">
+   <type>double</type>
+   <value>15.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWTR">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TFAW_NS">
+   <type>double</type>
+   <value>30.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRRD_NS">
+   <type>double</type>
+   <value>6.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRTP_NS">
+   <type>double</type>
+   <value>7.5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RATE">
+   <type>java.lang.String</type>
+   <value>Half</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MEM_CLK_FREQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DQS_TRACKING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_DQS_TRACKING">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_HPS_DQS_TRACKING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRK_PARALLEL_SCC_LOAD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_SHADOW_REGS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SHADOW_REGS">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQ_DDR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_CMD_DDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RATE_RATIO">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_RATE_RATIO">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RATE_RATIO">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_ADDR_WIDTH">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CONTROL_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CS_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DM_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DQ_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_ODT_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WRITE_DQS_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RLAT_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WLAT_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RRANK_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WRANK_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CLK_PAIR_COUNT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYS_INFO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRE_V_SERIES_FAMILY">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPEED_GRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ES_DEVICE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DISABLE_CHILD_MESSAGING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HARD_PHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HARD_EMIF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS_VERIFICATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS_SIMULATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HPS_PROTOCOL">
+   <type>java.lang.String</type>
+   <value>DEFAULT</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CUT_NEW_FAMILY_TIMING">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPORT_CSR_PORT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_ADDR_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_BE_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH">
+   <type>int</type>
+   <value>25</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_BE_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_SYMBOL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_SIZE_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DWIDTH_RATIO">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ODT_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_OUTPUT_REGD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_MULTIPLES_40_72">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_REGDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOW_LATENCY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTROLLER_TYPE">
+   <type>java.lang.String</type>
+   <value>nextgen_v110</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_TBP_NUM">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_USR_REFRESH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_SELF_REFRESH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TYPE">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_INTERFACE_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_BURST_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ADDR_ORDER">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PDN_EXIT_CYCLES">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES">
+   <type>int</type>
+   <value>512</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_WRITE_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_READ_ODT_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCAL_CS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_CLR_INTR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ENABLE_NO_DM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ADD_LAT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ERRCMD_FIFO_REG">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ECC_DECODER_REG">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_STARVE_LIMIT">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_1">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_2">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_3">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_4">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_5">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALLOCATED_RFIFO_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>0,None,None,None,None,None</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALLOCATED_WFIFO_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>0,None,None,None,None,None</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CAL_REQ">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_BURST_LENGTH">
+   <type>java.lang.String</type>
+   <value>BL_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_INTERFACE_WIDTH">
+   <type>java.lang.String</type>
+   <value>DWIDTH_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_STARVE_LIMIT">
+   <type>java.lang.String</type>
+   <value>STARVE_LIMIT_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_TYPE">
+   <type>java.lang.String</type>
+   <value>DDR3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLR_INTR">
+   <type>java.lang.String</type>
+   <value>NO_CLR_INTR</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_4">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_5">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ADDR_ORDER">
+   <type>java.lang.String</type>
+   <value>CHIP_BANK_ROW_COL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ECC_ENABLED">
+   <type>java.lang.String</type>
+   <value>CTL_ECC_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ECC_RMW_ENABLED">
+   <type>java.lang.String</type>
+   <value>CTL_ECC_RMW_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_REGDIMM_ENABLED">
+   <type>java.lang.String</type>
+   <value>REGDIMM_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_USR_REFRESH">
+   <type>java.lang.String</type>
+   <value>CTL_USR_REFRESH_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTRL_WIDTH">
+   <type>java.lang.String</type>
+   <value>DATA_WIDTH_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DELAY_BONDING">
+   <type>java.lang.String</type>
+   <value>BONDING_LATENCY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DFX_BYPASS_ENABLE">
+   <type>java.lang.String</type>
+   <value>DFX_BYPASS_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DISABLE_MERGING">
+   <type>java.lang.String</type>
+   <value>MERGING_ENABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ECC_DQ_WIDTH">
+   <type>java.lang.String</type>
+   <value>ECC_DQ_WIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_ATPG">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_DQS_TRACKING">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_NO_DM">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GANGED_ARF">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GEN_DBE">
+   <type>java.lang.String</type>
+   <value>GEN_DBE_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GEN_SBE">
+   <type>java.lang.String</type>
+   <value>GEN_SBE_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_INC_SYNC">
+   <type>java.lang.String</type>
+   <value>FIFO_SET_2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_LOCAL_IF_CS_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_CORR_DROPPED_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_DBE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_SBE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_AL">
+   <type>java.lang.String</type>
+   <value>AL_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_BURSTLENGTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_BURSTLENGTH_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_CS_PER_RANK">
+   <type>java.lang.String</type>
+   <value>MEM_IF_CS_PER_RANK_1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_CS_WIDTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_CS_WIDTH_1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP">
+   <type>java.lang.String</type>
+   <value>MEM_IF_DQ_PER_CHIP_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DQS_WIDTH">
+   <type>java.lang.String</type>
+   <value>DQS_WIDTH_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DWIDTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_DWIDTH_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_MEMTYPE">
+   <type>java.lang.String</type>
+   <value>DDR3_SDRAM</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_SPEEDBIN">
+   <type>java.lang.String</type>
+   <value>DDR3_1066_6_6_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCCD">
+   <type>java.lang.String</type>
+   <value>TCCD_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCL">
+   <type>java.lang.String</type>
+   <value>TCL_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCWL">
+   <type>java.lang.String</type>
+   <value>TCWL_5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TFAW">
+   <type>java.lang.String</type>
+   <value>TFAW_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TMRD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRAS">
+   <type>java.lang.String</type>
+   <value>TRAS_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRC">
+   <type>java.lang.String</type>
+   <value>TRC_22</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRCD">
+   <type>java.lang.String</type>
+   <value>TRCD_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRP">
+   <type>java.lang.String</type>
+   <value>TRP_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRRD">
+   <type>java.lang.String</type>
+   <value>TRRD_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRTP">
+   <type>java.lang.String</type>
+   <value>TRTP_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TWR">
+   <type>java.lang.String</type>
+   <value>TWR_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TWTR">
+   <type>java.lang.String</type>
+   <value>TWTR_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MMR_CFG_MEM_BL">
+   <type>java.lang.String</type>
+   <value>MP_BL_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_OUTPUT_REGD">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PDN_EXIT_CYCLES">
+   <type>java.lang.String</type>
+   <value>SLOW_EXIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT0_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT1_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT2_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT3_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT4_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT5_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_READ_ODT_CHIP">
+   <type>java.lang.String</type>
+   <value>ODT_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_REORDER_DATA">
+   <type>java.lang.String</type>
+   <value>DATA_REORDERING</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_0">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_1">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_2">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_3">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_0">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_1">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_2">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_3">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_4">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_5">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_TEST_MODE">
+   <type>java.lang.String</type>
+   <value>NORMAL_MODE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_0">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_1">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_2">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_3">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_4">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_5">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_0">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_1">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_2">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_3">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_4">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_5">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_0">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_1">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_2">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_3">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_ECC_EN">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WRITE_ODT_CHIP">
+   <type>java.lang.String</type>
+   <value>ODT_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_IF_TREFI">
+   <type>int</type>
+   <value>3120</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_IF_TRFC">
+   <type>int</type>
+   <value>34</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ONE_MASK">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BURST_INTERRUPT">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BURST_TERMINATE">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT0_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT1_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT2_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT3_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT4_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT5_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTINUE_AFTER_CAL_FAIL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX10_CFG">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="POWER_OF_TWO_BUS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SOPC_COMPAT_RESET">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_MAX_SIZE">
+   <type>java.lang.String</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BYTE_ENABLE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DEEP_POWERDN_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_SELF_REFRESH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_POWERDN_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_USR_REFRESH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_AUTOPCH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ZQCAL_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_ORDER">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_LOOK_AHEAD_DEPTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTROLLER_LATENCY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_REORDER_DATA">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STARVE_LIMIT">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_CONNECTION">
+   <type>java.lang.String</type>
+   <value>INTERNAL_JTAG</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_HRB_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MULTICAST_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DYNAMIC_BANK_NUM">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEBUG_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_BURST_MERGE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_TERMINATE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCAL_ID_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDBUFFER_ADDR_WIDTH">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WRBUFFER_ADDR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_PENDING_WR_CMD">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_PENDING_RD_CMD">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MM_ADAPTOR">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_AXI_ADAPTOR">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HCX_COMPAT_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CMD_QUEUE_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_READ_ONLY">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_DATA_REORDERING_TYPE">
+   <type>java.lang.String</type>
+   <value>INTER_BANK</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_OF_PORTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_BONDING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_USER_ECC">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>32,32,32,32,32,32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>1,1,1,1,1,1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>0,0,0,0,0,0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DR_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_USE_DR_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_2X_FF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUAL_WRITE_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GENERIC_PLL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_HARD_READ_FIFO">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_FIFO_HALF_RATE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_VERSION_NUMBER">
+   <type>int</type>
+   <value>191</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_OCI">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EMIT_JTAG_MASTER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_JTAG_UART">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EMIT_BFM_MASTER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_VALID_FIFO_SIZE">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTRA_VFIFO_SHIFT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_RATE">
+   <type>java.lang.String</type>
+   <value>HALF</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_IF_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_PLL_DLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FAST_SIM_CALIBRATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_NS">
+   <type>double</type>
+   <value>10.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_PS">
+   <type>double</type>
+   <value>10000.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ">
+   <type>double</type>
+   <value>150.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>150.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>6668 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MIN_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MAX_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MIN_CACHE">
+   <type>double</type>
+   <value>10.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MAX_CACHE">
+   <type>double</type>
+   <value>500.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>150.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>6668 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPEED_GRADE_CACHE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ES_DEVICE_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RATE_CACHE">
+   <type>java.lang.String</type>
+   <value>Half</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HCX_COMPAT_MODE_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMMAND_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQUENCER_TYPE_CACHE">
+   <type>java.lang.String</type>
+   <value>NIOS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MEM_CLK_FREQ_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CLK_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CLK_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EXTRA_REPORTING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_EXTRA_REPORT_PATH">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ISS_PROBES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_REG_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_SEQUENCER_BFM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_PLL_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPORT_AFI_HALF_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FAKE_PHY_INTERNAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FAKE_PHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_READ_LATENCY">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_USER_RDIMM_VALUE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRACKING_ERROR_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRACKING_WATCH_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MARGIN_VARIATION_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_USER_ADD_0">
+   <type>java.lang.String</type>
+   <value>0_0000_0000_0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_USER_ADD_1">
+   <type>java.lang.String</type>
+   <value>0_0000_0000_1000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TREFI">
+   <type>int</type>
+   <value>35100</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REFRESH_INTERVAL">
+   <type>int</type>
+   <value>15000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DES_CAL_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRFC">
+   <type>int</type>
+   <value>350</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DES_CAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTRA_SETTINGS">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DEVICE">
+   <type>java.lang.String</type>
+   <value>MISSING_MODEL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QVLD_EXTRA_FLOP_STAGES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QVLD_WR_ADDRESS_OFFSET">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQ_BURST_COUNT_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCALIB_COUNT_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_PHASE_COUNTER_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_PHASE_SHIFT">
+   <type>int</type>
+   <value>9000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_IN_RESERVE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_OUT_RESERVE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQ_OUT_RESERVE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DM_OUT_RESERVE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_EN_DELAY_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_EN_PHASE_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_NS">
+   <type>double</type>
+   <value>3.333</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_PS">
+   <type>double</type>
+   <value>3333.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_LFIFO_OFFSET">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_VFIFO_OFFSET">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_OPA_TAP">
+   <type>int</type>
+   <value>416</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_DCHAIN_TAP">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_EN_DELAY_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_IN_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_IN_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_OUT1_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_OUT2_DELAY_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_STANDARD">
+   <type>java.lang.String</type>
+   <value>SSTL-15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VFIFO_AS_SHIFT_REG">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQUENCER_TYPE">
+   <type>java.lang.String</type>
+   <value>NIOS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_HEX_FILE_LOCATION">
+   <type>java.lang.String</type>
+   <value>../</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NEGATIVE_WRITE_CK_PHASE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_T_WL">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_T_RL">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CLKBUF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_LDC_FOR_ADDR_CMD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REGISTER_C2P">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX10_RTL_SEQ">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_ONLY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQ_MODE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADVANCED_CK_PHASES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMMAND_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VOLTAGE">
+   <type>java.lang.String</type>
+   <value>1.5V DDR3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_LOCATION">
+   <type>java.lang.String</type>
+   <value>Top_Bottom</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_MEM_INIT">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE">
+   <type>java.lang.String</type>
+   <value>INVERTED_DQS_BUS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQ_INPUT_REG_USE_CLKN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_DQSN_MODE">
+   <type>java.lang.String</type>
+   <value>DIFFERENTIAL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DEBUG_INFO_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIBRATION_MODE">
+   <type>java.lang.String</type>
+   <value>Skip</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_ROM_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>13</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_FIFO_SIZE">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CSR_CONNECTION">
+   <type>java.lang.String</type>
+   <value>INTERNAL_JTAG</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USER_DEBUG_LEVEL">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DERATE_METHOD">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIS">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIH">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDS">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDH">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIS_APPLIED">
+   <type>double</type>
+   <value>0.32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIH_APPLIED">
+   <type>double</type>
+   <value>0.22</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDS_APPLIED">
+   <type>double</type>
+   <value>0.16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDH_APPLIED">
+   <type>double</type>
+   <value>0.145</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_ISI_METHOD">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKAGE_DESKEW">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_PACKAGE_DESKEW">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY">
+   <type>double</type>
+   <value>0.2443</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY">
+   <type>double</type>
+   <value>0.21929</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN">
+   <type>double</type>
+   <value>0.02286</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED">
+   <type>double</type>
+   <value>0.02286</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX">
+   <type>double</type>
+   <value>0.04429</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED">
+   <type>double</type>
+   <value>0.04429</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS">
+   <type>double</type>
+   <value>0.05</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS">
+   <type>double</type>
+   <value>0.01806</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS">
+   <type>double</type>
+   <value>0.04246</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW">
+   <type>double</type>
+   <value>-0.01152</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SKEW">
+   <type>double</type>
+   <value>0.07801</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW">
+   <type>double</type>
+   <value>-0.04709</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CORE_DEBUG_CONNECTION">
+   <type>java.lang.String</type>
+   <value>EXPORT</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ED_EXPORT_SEQ_DEBUG">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADD_EFFICIENCY_MONITOR">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABS_RAM_INTERNAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABSTRACT_RAM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME">
+   <type>java.lang.String</type>
+   <value>meminit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_DELAY_CTRL_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_OFFSET_CTRL_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_BUFFER_MODE">
+   <type>java.lang.String</type>
+   <value>HIGH</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_CHAIN_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_DLL_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OCT_TERM_CONTROL_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OCT_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_OCT_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="pll_ref_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>pll_ref_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="global_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>global_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="soft_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>soft_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="afi_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>150000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="afi_half_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>300000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_half_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="afi_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>soft_reset,global_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="afi_reset_export" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>soft_reset,global_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_reset_export_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="memory" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>memory</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>mem_a</name>
+    <direction>Output</direction>
+    <width>14</width>
+    <role>mem_a</role>
+   </port>
+   <port>
+    <name>mem_ba</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>mem_ba</role>
+   </port>
+   <port>
+    <name>mem_ck</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_ck</role>
+   </port>
+   <port>
+    <name>mem_ck_n</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_ck_n</role>
+   </port>
+   <port>
+    <name>mem_cke</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cke</role>
+   </port>
+   <port>
+    <name>mem_cs_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cs_n</role>
+   </port>
+   <port>
+    <name>mem_dm</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_dm</role>
+   </port>
+   <port>
+    <name>mem_ras_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_ras_n</role>
+   </port>
+   <port>
+    <name>mem_cas_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cas_n</role>
+   </port>
+   <port>
+    <name>mem_we_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_we_n</role>
+   </port>
+   <port>
+    <name>mem_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_reset_n</role>
+   </port>
+   <port>
+    <name>mem_dq</name>
+    <direction>Bidir</direction>
+    <width>8</width>
+    <role>mem_dq</role>
+   </port>
+   <port>
+    <name>mem_dqs</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_dqs</role>
+   </port>
+   <port>
+    <name>mem_dqs_n</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_dqs_n</role>
+   </port>
+   <port>
+    <name>mem_odt</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_odt</role>
+   </port>
+  </interface>
+  <interface name="avl" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>134217728</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>afi_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest_n</role>
+   </port>
+   <port>
+    <name>avl_burstbegin</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>beginbursttransfer</role>
+   </port>
+   <port>
+    <name>avl_addr</name>
+    <direction>Input</direction>
+    <width>25</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_rdata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avl_rdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_wdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_be</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>avl_read_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_write_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_size</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>burstcount</role>
+   </port>
+  </interface>
+  <interface name="status" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>local_init_done</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_init_done</role>
+   </port>
+   <port>
+    <name>local_cal_success</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_cal_success</role>
+   </port>
+   <port>
+    <name>local_cal_fail</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_cal_fail</role>
+   </port>
+  </interface>
+  <interface name="pll_sharing" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>pll_mem_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_mem_clk</role>
+   </port>
+   <port>
+    <name>pll_write_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_write_clk</role>
+   </port>
+   <port>
+    <name>pll_locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_locked</role>
+   </port>
+   <port>
+    <name>pll_capture0_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_capture0_clk</role>
+   </port>
+   <port>
+    <name>pll_capture1_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_capture1_clk</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ddr3_ram_resetn"
+   kind="altera_reset_bridge"
+   version="19.1"
+   path="ddr3_ram_resetn">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="ACTIVE_LOW_RESET">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNCHRONOUS_EDGES">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_RESET_OUTPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_CLK_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>-1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="out_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="debug_uart"
+   kind="altera_avalon_uart"
+   version="19.1"
+   path="debug_uart">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BAUD</name>
+   <value>115200</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_BITS</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_BAUD</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PARITY</name>
+   <value>'N'</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIM_CHAR_STREAM</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIM_TRUE_BAUD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STOP_BITS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SYNC_REG_DEPTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_CTS_RTS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_EOP_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,uart-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>serial</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>uart</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.current-speed</name>
+   <value>115200</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="baud">
+   <type>int</type>
+   <value>115200</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataBits">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedBaud">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="parity">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simCharStream">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simInteractiveInputEnable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simInteractiveOutputEnable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simTrueBaud">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stopBits">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="syncRegDepth">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useCtsRts">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useEopRegister">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useRelativePathForSimFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="baudError">
+   <type>double</type>
+   <value>0.01</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="parityFisrtChar">
+   <type>java.lang.String</type>
+   <value>N</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>begintransfer</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>begintransfer</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>read_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read_n</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rxd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+   <port>
+    <name>txd</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>debug_uart.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="descriptor_memory">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>q_sys_descriptor_memory</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>8192</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>q_sys_descriptor_memory</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>8192</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_descriptor_memory</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>q_sys_descriptor_memory.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8192</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8192</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>11</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+ </module>
+ <module name="enet_pll" kind="altpll" version="19.1" path="enet_pll">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_elaboration</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_post_edit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTENDED_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_CLOCK">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIMARY_CLOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>20000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK1_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OPERATION_MODE">
+   <type>java.lang.String</type>
+   <value>NO_COMPENSATION</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_CONF_DONE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMPENSATE_CLOCK">
+   <type>java.lang.String</type>
+   <value>CLK0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_SIGNAL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_HIGH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_LOW">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INVALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_LOSSCLK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_VCO">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_TYPE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FEEDBACK_SOURCE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPREAD_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DOWN_SPREAD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>-3000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>-10000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena2">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena3">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk1">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk2">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk3">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk4">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk6">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk7">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk8">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk9">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATAOUT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ACTIVECLOCK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKLOSS">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBIN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PLLENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKSWITCH">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ARESET">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PFDENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANACLR">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANREAD">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANWRITE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_LOCKED">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CONFIGUPDATE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBOUT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASESTEP">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEUPDOWN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLKENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOOVERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOUNDERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_FREQUENCY_CONTROL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_PHASE_SHIFT_STEP">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USING_FBMIMICBIDIR_PORT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN_MIF_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK">
+   <type>java.lang.String</type>
+   <value>NO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CONSTANTS">
+   <type>java.lang.String</type>
+   <value>CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_PRIVATES">
+   <type>java.lang.String</type>
+   <value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_USED_PORTS">
+   <type>java.lang.String</type>
+   <value>UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_NUMERIC">
+   <type>java.lang.String</type>
+   <value>IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_MF_PORTS">
+   <type>java.lang.String</type>
+   <value>MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IF_PORTS">
+   <type>java.lang.String</type>
+   <value>IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>inclk_interface</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="inclk_interface" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="inclk_interface_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="pll_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>inclk_interface_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface name="c0" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>125000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c1" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c2" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>2500000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c3" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>125000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c4" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="locked_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module name="eth_tse" kind="altera_eth_tse" version="19.1" path="eth_tse">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ENABLE_MACLITE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIFO_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IS_MULTICHANNEL_MAC</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MACLITE_GIGE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MDIO_SHARED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_CHANNEL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS_ID</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS_SGMII</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RECEIVE_FIFO_DEPTH</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.REGISTER_SHARED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RGMII</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_MDIO</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,tse-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>ethernet</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>tse</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.ALTR,rx-fifo-depth</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.ALTR,tx-fifo-depth</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="deviceFamilyName">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="enable_padding">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_lgth_check">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gbit_only">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mbit_only">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reduced_control">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="core_version">
+   <type>int</type>
+   <value>4865</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dev_version">
+   <type>int</type>
+   <value>4865</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="eg_fifo">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ing_fifo">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reduced_interface_ena">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="synchronizer_depth">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="isUseMAC">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="isUsePCS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_clk_sharing">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="core_variation">
+   <type>java.lang.String</type>
+   <value>MAC_ONLY</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ifGMII">
+   <type>java.lang.String</type>
+   <value>RGMII</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="use_mac_clken">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_use_internal_fifo">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ecc">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="max_channels">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="use_misc_ports">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="transceiver_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_hd_logic">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_gmii_loopback">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_sup_addr">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stat_cnt_ena">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ext_stat_cnt_ena">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ena_hash">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_shift16">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_mac_flow_ctrl">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_mac_vlan">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_magic_detect">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useMDIO">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mdio_clk_div">
+   <type>int</type>
+   <value>40</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ena">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="eg_addr">
+   <type>int</type>
+   <value>11</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ing_addr">
+   <type>int</type>
+   <value>11</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phy_identifier">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_sgmii">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="export_pwrdn">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_alt_reconfig">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="starting_channel_number">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pll_type">
+   <type>java.lang.String</type>
+   <value>CMU</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pll_base_data_rate">
+   <type>java.lang.String</type>
+   <value>1250 Mbps</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_en_synce_support">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pma_bonding_mode">
+   <type>java.lang.String</type>
+   <value>x1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="nf_phyip_rcfg_enable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_RCFG_JTAG_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_USER_IDENTIFIER">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="nf_lvds_iopll_num_channels">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_timestamping">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ptp_1step">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tstamp_fp_width">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="control_port_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_connection" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>control_port_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="control_port" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1024</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>control_port_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reg_addr</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>reg_data_out</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>reg_rd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>reg_data_in</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>reg_wr</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>reg_busy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+  <interface name="pcs_mac_tx_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>tx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="pcs_mac_rx_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="mac_status_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>set_10</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>set_10</role>
+   </port>
+   <port>
+    <name>set_1000</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>set_1000</role>
+   </port>
+   <port>
+    <name>eth_mode</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>eth_mode</role>
+   </port>
+   <port>
+    <name>ena_10</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ena_10</role>
+   </port>
+  </interface>
+  <interface name="mac_rgmii_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rgmii_in</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>rgmii_in</role>
+   </port>
+   <port>
+    <name>rgmii_out</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>rgmii_out</role>
+   </port>
+   <port>
+    <name>rx_control</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>rx_control</role>
+   </port>
+   <port>
+    <name>tx_control</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>tx_control</role>
+   </port>
+  </interface>
+  <interface name="receive_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_rx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="transmit_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_tx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="receive" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>receive_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>ff_rx_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>ff_rx_eop</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>rx_err</name>
+    <direction>Output</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>ff_rx_mod</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>ff_rx_rdy</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>ff_rx_sop</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>ff_rx_dval</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="transmit" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>transmit_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_tx_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>ff_tx_eop</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>ff_tx_err</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>ff_tx_mod</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>ff_tx_rdy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>ff_tx_sop</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>ff_tx_wren</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="mac_mdio_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>mdc</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdc</role>
+   </port>
+   <port>
+    <name>mdio_in</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>mdio_in</role>
+   </port>
+   <port>
+    <name>mdio_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdio_out</role>
+   </port>
+   <port>
+    <name>mdio_oen</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdio_oen</role>
+   </port>
+  </interface>
+  <interface name="mac_misc_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>magic_wakeup</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>magic_wakeup</role>
+   </port>
+   <port>
+    <name>magic_sleep_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>magic_sleep_n</role>
+   </port>
+   <port>
+    <name>ff_tx_crc_fwd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ff_tx_crc_fwd</role>
+   </port>
+   <port>
+    <name>ff_tx_septy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_septy</role>
+   </port>
+   <port>
+    <name>tx_ff_uflow</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>tx_ff_uflow</role>
+   </port>
+   <port>
+    <name>ff_tx_a_full</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_a_full</role>
+   </port>
+   <port>
+    <name>ff_tx_a_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_a_empty</role>
+   </port>
+   <port>
+    <name>rx_err_stat</name>
+    <direction>Output</direction>
+    <width>18</width>
+    <role>rx_err_stat</role>
+   </port>
+   <port>
+    <name>rx_frm_type</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>rx_frm_type</role>
+   </port>
+   <port>
+    <name>ff_rx_dsav</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_dsav</role>
+   </port>
+   <port>
+    <name>ff_rx_a_full</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_a_full</role>
+   </port>
+   <port>
+    <name>ff_rx_a_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_a_empty</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   path="ext_flash">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_TYPE</name>
+   <value>Micron512</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IS_EPCS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_SECTORS</name>
+   <value>1024</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PAGE_SIZE</name>
+   <value>256</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR_SIZE</name>
+   <value>65536</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SUBSECTOR_SIZE</name>
+   <value>4096</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,quadspi-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>quadspi</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>quadspi</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.IS_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX</name>
+   <value>1</value>
+  </assignment>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="UNIQUE_ID">
+   <type>java.lang.String</type>
+   <value>q_sys_ext_flash</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="clkFreq">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clock_sink</sysinfo_arg>
+  </parameter>
+  <parameter name="CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_WIDTH">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ASI_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ASMI_ADDR_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_4BYTE_ADDR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DDASI">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_TYPE">
+   <type>java.lang.String</type>
+   <value>Micron512</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_MODE">
+   <type>java.lang.String</type>
+   <value>QUAD</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHIP_SELS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFeaturesSystemInfo">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clock_sink" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>false</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="avl_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_csr_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avl_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_csr_addr</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_csr_wrdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_csr_rddata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_csr_rddata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface name="avl_mem" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>67108864</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_mem_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_mem_burstcount</name>
+    <direction>Input</direction>
+    <width>7</width>
+    <role>burstcount</role>
+   </port>
+   <port>
+    <name>avl_mem_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avl_mem_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_mem_addr</name>
+    <direction>Input</direction>
+    <width>24</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_mem_wrdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_mem_rddata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_mem_rddata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avl_mem_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="interrupt_sender" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>ext_flash.avl_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="flash_dataout" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_dataout</name>
+    <direction>Bidir</direction>
+    <width>4</width>
+    <role>conduit_dataout</role>
+   </port>
+  </interface>
+  <interface name="flash_dclk_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_dclk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>conduit_dclk_out</role>
+   </port>
+  </interface>
+  <interface name="flash_ncs" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_ncs</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>conduit_ncs</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ext_flash_clock_bridge"
+   kind="altera_clock_bridge"
+   version="19.1"
+   path="ext_flash_clock_bridge">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DERIVED_CLOCK_RATE">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>in_clk</sysinfo_arg>
+  </parameter>
+  <parameter name="EXPLICIT_CLOCK_RATE">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_CLOCK_OUTPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>false</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="out_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>in_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>clock_sink</slaveName>
+    <name>ext_flash.clock_sink</name>
+   </clockDomainMember>
+  </interface>
+ </module>
+ <module
+   name="frame_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   path="frame_timer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALWAYS_RUN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.COUNTER_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_PERIOD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.LOAD_VALUE</name>
+   <value>4999</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MULT</name>
+   <value>2e-8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD</name>
+   <value>5000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD_UNITS</name>
+   <value>clocks</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SNAPSHOT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
+   <value>10000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="alwaysRun">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="counterSize">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedPeriod">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="period">
+   <type>java.lang.String</type>
+   <value>5000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnits">
+   <type>java.lang.String</type>
+   <value>CLOCKS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="snapshot">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timeoutPulseOutput">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="systemFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="watchdogPulse">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timerPreset">
+   <type>java.lang.String</type>
+   <value>CUSTOM</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnitsString">
+   <type>java.lang.String</type>
+   <value>clocks</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="valueInSecond">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="loadValue">
+   <type>java.lang.String</type>
+   <value>4999</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mult">
+   <type>double</type>
+   <value>2.0E-8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ticksPerSec">
+   <type>double</type>
+   <value>10000.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave_address_width">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isTimerDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>frame_timer.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="external_port" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>timeout_pulse</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module name="msgdma_rx" kind="altera_msgdma" version="19.1" path="msgdma_rx">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_WRAPPING_SUPPORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_FIFO_DEPTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DMA_MODE</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ENHANCED_FEATURES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BURST_COUNT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BYTE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_STRIDE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PREFETCHER_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESPONSE_PORT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSFER_TYPE</name>
+   <value>Aligned Accesses</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,msgdma-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="MODE">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPOSE_ST_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_FIFO_DEPTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DESCRIPTOR_FIFO_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESPONSE_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BYTE">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRANSFER_TYPE">
+   <type>java.lang.String</type>
+   <value>Aligned Accesses</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_WRAPPING_SUPPORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENHANCED_FEATURES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_STRIDE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PROGRAMMABLE_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_READ_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = -1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 28</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="mm_write" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>mm_write_address</name>
+    <direction>Output</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>mm_write_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>mm_write_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>mm_write_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>mm_write_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ddr3_ram</moduleName>
+    <slaveName>avl</slaveName>
+    <name>ddr3_ram.avl</name>
+    <baseAddress>134217728</baseAddress>
+    <span>134217728</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_read_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_read_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>406847488</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_write_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>3</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_write_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_response</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writeresponsevalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>406847488</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+  </interface>
+  <interface name="clock" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_n" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+  </interface>
+  <interface name="prefetcher_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>prefetcher_csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="csr_irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>msgdma_rx.prefetcher_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_irq_irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="st_sink" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>st_sink_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>st_sink_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>st_sink_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>st_sink_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>st_sink_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>st_sink_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>st_sink_error</name>
+    <direction>Input</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module name="msgdma_tx" kind="altera_msgdma" version="19.1" path="msgdma_tx">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_WRAPPING_SUPPORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_FIFO_DEPTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DMA_MODE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ENHANCED_FEATURES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BURST_COUNT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BYTE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_STRIDE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PREFETCHER_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESPONSE_PORT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSFER_TYPE</name>
+   <value>Aligned Accesses</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,msgdma-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPOSE_ST_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_FIFO_DEPTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DESCRIPTOR_FIFO_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESPONSE_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BYTE">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRANSFER_TYPE">
+   <type>java.lang.String</type>
+   <value>Aligned Accesses</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_WRAPPING_SUPPORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENHANCED_FEATURES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_STRIDE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PROGRAMMABLE_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_READ_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 28</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = -1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="mm_read" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>mm_read_address</name>
+    <direction>Output</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>mm_read_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>mm_read_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>mm_read_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>mm_read_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>mm_read_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ddr3_ram</moduleName>
+    <slaveName>avl</slaveName>
+    <name>ddr3_ram.avl</name>
+    <baseAddress>134217728</baseAddress>
+    <span>134217728</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_read_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_read_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>406847488</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_write_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>3</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_write_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_response</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writeresponsevalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>406847488</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+  </interface>
+  <interface name="clock" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_n" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+  </interface>
+  <interface name="prefetcher_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>prefetcher_csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="csr_irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>msgdma_tx.prefetcher_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_irq_irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="st_source" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>st_source_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>st_source_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>st_source_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>st_source_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>st_source_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>st_source_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>st_source_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="onchip_flash"
+   kind="altera_onchip_flash"
+   version="19.1"
+   path="onchip_flash">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BYTES_PER_PAGE</name>
+   <value>8192</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_ONLY_MODE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_END_ADDR</name>
+   <value>32767</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_START_ADDR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_END_ADDR</name>
+   <value>65535</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_START_ADDR</name>
+   <value>32768</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_END_ADDR</name>
+   <value>458751</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_START_ADDR</name>
+   <value>65536</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_END_ADDR</name>
+   <value>753663</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_START_ADDR</name>
+   <value>458752</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_END_ADDR</name>
+   <value>1441791</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_START_ADDR</name>
+   <value>753664</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.FLASH_INSTALL_DIR</name>
+   <value>APP_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.IS_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILENAME</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="DATA_INTERFACE">
+   <type>java.lang.String</type>
+   <value>Parallel</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_BURST_MODE">
+   <type>java.lang.String</type>
+   <value>Incrementing</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_BURST_COUNT">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY">
+   <type>double</type>
+   <value>50.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONFIGURATION_SCHEME">
+   <type>java.lang.String</type>
+   <value>Internal Configuration</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONFIGURATION_MODE">
+   <type>java.lang.String</type>
+   <value>Single Uncompressed Image</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ID">
+   <type>[Ljava.lang.String;</type>
+   <value>1,2,3,4,5</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ACCESS_MODE">
+   <type>[Ljava.lang.String;</type>
+   <value>Read and write,Read and write,Read and write,Read and write,Read and write</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ADDRESS_MAPPING">
+   <type>[Ljava.lang.String;</type>
+   <value>0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_STORAGE_TYPE">
+   <type>[Ljava.lang.String;</type>
+   <value>UFM,UFM,UFM,CFM,CFM</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initFlashContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileNameForSim">
+   <type>java.lang.String</type>
+   <value>altera_onchip_flash.dat</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_onchip_flash</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="INIT_FILENAME">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INIT_FILENAME_SIM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PART_NAME">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_CLOCK_RATE">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="DEVICE_ID">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_START_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_END_ADDR">
+   <type>int</type>
+   <value>8191</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_START_ADDR">
+   <type>int</type>
+   <value>8192</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_END_ADDR">
+   <type>int</type>
+   <value>16383</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_START_ADDR">
+   <type>int</type>
+   <value>16384</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_END_ADDR">
+   <type>int</type>
+   <value>114687</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_START_ADDR">
+   <type>int</type>
+   <value>114688</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_END_ADDR">
+   <type>int</type>
+   <value>188415</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_START_ADDR">
+   <type>int</type>
+   <value>188416</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_VALID_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_VALID_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_UFM_VALID_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_UFM_VALID_ADDR">
+   <type>int</type>
+   <value>114687</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_MAP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_MAP">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_MAP">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_MAP">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_MAP">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE1_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE2_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE1_OFFSET">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE2_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE3_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_ADDR_WIDTH">
+   <type>int</type>
+   <value>19</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_BURSTCOUNT_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_READ_PROTECTION_MODE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_SEQ_READ_DATA_COUNT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_ADDR_ALIGNMENT_BITS">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_READ_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_RESET_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>60</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>17500000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>15250</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARALLEL_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_AND_WRITE_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WRAPPING_BURST_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_DUAL_BOOT">
+   <type>java.lang.String</type>
+   <value>False</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ERAM_SKIP">
+   <type>java.lang.String</type>
+   <value>True</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_COMPRESSED_IMAGE">
+   <type>java.lang.String</type>
+   <value>False</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="nreset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="data" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1441792</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>nreset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1441792</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avmm_data_addr</name>
+    <direction>Input</direction>
+    <width>19</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avmm_data_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avmm_data_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avmm_data_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avmm_data_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avmm_data_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avmm_data_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avmm_data_burstcount</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>burstcount</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>nreset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avmm_csr_addr</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avmm_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avmm_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avmm_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avmm_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="output_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   path="output_pio">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CAPTURE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EDGE_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_IN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_OUT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_TRI</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IRQ_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,pio-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>gpio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>pio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,gpio-bank-width</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.resetvalue</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="bitClearingEdgeCapReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitModifyingOutReg">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="captureEdge">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="direction">
+   <type>java.lang.String</type>
+   <value>Output</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="edgeType">
+   <type>java.lang.String</type>
+   <value>RISING</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateIRQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="irqType">
+   <type>java.lang.String</type>
+   <value>LEVEL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDoTestBenchWiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDrivenValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="width">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="derived_has_tri">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_out">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_do_test_bench_wiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_capture">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_edge_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_irq_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_irq">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>out_port</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sensor_interface"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_interface">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>s2</slaveName>
+    <name>calibration_ram.s2</name>
+    <baseAddress>0</baseAddress>
+    <span>640</span>
+   </memoryBlock>
+  </interface>
+ </module>
+ <module name="sys_clk" kind="clock_source" version="19.1" path="sys_clk">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockFrequencyKnown">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inputClockFrequency">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk_in</sysinfo_arg>
+  </parameter>
+  <parameter name="resetSynchronousEdges">
+   <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk_in" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>clk</value>
+   </assignment>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>reset</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>clk_in</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>50000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sysid</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sysid.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sys_clk_timer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>cpu</moduleName>
+    <slaveName>clk</slaveName>
+    <name>cpu.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>output_pio</moduleName>
+    <slaveName>clk</slaveName>
+    <name>output_pio.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>button_pio</moduleName>
+    <slaveName>clk</slaveName>
+    <name>button_pio.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>clk</slaveName>
+    <name>debug_uart.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>clk</slaveName>
+    <name>onchip_flash.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>tx_multiplexer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>tx_multiplexer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>channel_adapter_0</moduleName>
+    <slaveName>clk</slaveName>
+    <name>channel_adapter_0.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>udp_generator</moduleName>
+    <slaveName>clk</slaveName>
+    <name>udp_generator.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>frame_timer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>frame_timer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sensor_interface</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sensor_interface.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>clk1</slaveName>
+    <name>descriptor_memory.clk1</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>clk1</slaveName>
+    <name>calibration_ram.clk1</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>clk2</slaveName>
+    <name>calibration_ram.clk2</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>clock</slaveName>
+    <name>msgdma_tx.clock</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>clock</slaveName>
+    <name>msgdma_rx.clock</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>control_port_clock_connection</slaveName>
+    <name>eth_tse.control_port_clock_connection</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>enet_pll</moduleName>
+    <slaveName>inclk_interface</slaveName>
+    <name>enet_pll.inclk_interface</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>altpll_shift</moduleName>
+    <slaveName>inclk_interface</slaveName>
+    <name>altpll_shift.inclk_interface</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>receive_clock_connection</slaveName>
+    <name>eth_tse.receive_clock_connection</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>transmit_clock_connection</slaveName>
+    <name>eth_tse.transmit_clock_connection</name>
+   </clockDomainMember>
+  </interface>
+  <interface name="clk_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_n_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   path="sys_clk_timer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALWAYS_RUN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.COUNTER_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_PERIOD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.LOAD_VALUE</name>
+   <value>499999</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MULT</name>
+   <value>0.001</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD_UNITS</name>
+   <value>ms</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SNAPSHOT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,timer-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>timer</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>timer</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="alwaysRun">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="counterSize">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedPeriod">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="period">
+   <type>java.lang.String</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnits">
+   <type>java.lang.String</type>
+   <value>MSEC</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="snapshot">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timeoutPulseOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="systemFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="watchdogPulse">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timerPreset">
+   <type>java.lang.String</type>
+   <value>FULL_FEATURED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnitsString">
+   <type>java.lang.String</type>
+   <value>ms</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="valueInSecond">
+   <type>double</type>
+   <value>0.001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="loadValue">
+   <type>java.lang.String</type>
+   <value>499999</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mult">
+   <type>double</type>
+   <value>0.001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ticksPerSec">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave_address_width">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isTimerDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>sys_clk_timer.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="19.1"
+   path="sysid">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ID</name>
+   <value>4207856382</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMESTAMP</name>
+   <value>1728634208</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,sysid-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>sysid</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>sysid</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.id</name>
+   <value>4207856382</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.timestamp</name>
+   <value>1728634208</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="id">
+   <type>int</type>
+   <value>-87110914</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timestamp">
+   <type>int</type>
+   <value>1728634208</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>GENERATION_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="control_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="tx_multiplexer"
+   kind="multiplexer"
+   version="19.1"
+   path="tx_multiplexer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="usePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmpty">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="numInputInterfaces">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="schedulingSize">
+   <type>int</type>
+   <value>512</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="packetScheduling">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useHighBitsOfChannel">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="symbolsPerBeat">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="errorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>out_channel</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>channel</role>
+   </port>
+  </interface>
+  <interface name="in0" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in0_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in0_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in0_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+  <interface name="in1" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in1_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in1_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in1_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in1_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in1_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in1_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in1_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="udp_generator"
+   kind="udp_generator"
+   version="1.0"
+   path="udp_generator">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="data_in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>data_in_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_in_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_in_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>data_in_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_in_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_in_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+ </module>
+ <connection
+   name="sensor_interface.calibration_ram_interface/calibration_ram.s2"
+   kind="avalon"
+   version="19.1"
+   start="sensor_interface.calibration_ram_interface"
+   end="calibration_ram.s2">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sensor_interface</startModule>
+  <startConnectionPoint>calibration_ram_interface</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>s2</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/ddr3_ram.avl"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x08000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>avl</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/ext_flash.avl_csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>avl_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/ext_flash.avl_mem"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x14000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>avl_mem</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/eth_tse.control_port"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="eth_tse.control_port">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>control_port</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/sysid.control_slave"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d68</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>control_slave</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/msgdma_tx.csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d00</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/msgdma_rx.csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403ce0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/onchip_flash.csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d60</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/udp_generator.csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="udp_generator.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403cc0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/sensor_interface.csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sensor_interface.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/onchip_flash.data"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18200000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>data</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/cpu.debug_mem_slave"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18402800</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>debug_mem_slave</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/msgdma_tx.prefetcher_csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.prefetcher_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403ca0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>prefetcher_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/msgdma_rx.prefetcher_csr"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.prefetcher_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403c80</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>prefetcher_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18400000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/sys_clk_timer.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403c60</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/output_pio.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="output_pio.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403c40</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/button_pio.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="button_pio.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403d40</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/debug_uart.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="debug_uart.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403c20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/frame_timer.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="frame_timer.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403c00</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/calibration_ram.s1"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="calibration_ram.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18403400</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.descriptor_read_master/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18400000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>descriptor_read_master</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.descriptor_read_master/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18400000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>descriptor_read_master</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.descriptor_write_master/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18400000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>descriptor_write_master</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.descriptor_write_master/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18400000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>descriptor_write_master</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.instruction_master/ddr3_ram.avl"
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x08000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>instruction_master</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>avl</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.instruction_master/ext_flash.avl_mem"
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x14000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>instruction_master</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>avl_mem</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.instruction_master/onchip_flash.data"
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18200000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>instruction_master</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>data</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.instruction_master/cpu.debug_mem_slave"
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x18402800</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>instruction_master</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>debug_mem_slave</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.mm_read/ddr3_ram.avl"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x08000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>mm_read</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>avl</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.mm_write/ddr3_ram.avl"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x08000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>mm_write</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>avl</endConnectionPoint>
+ </connection>
+ <connection
+   name="sensor_interface.data_out/udp_generator.data_in"
+   kind="avalon_streaming"
+   version="19.1"
+   start="sensor_interface.data_out"
+   end="udp_generator.data_in">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sensor_interface</startModule>
+  <startConnectionPoint>data_out</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>data_in</endConnectionPoint>
+ </connection>
+ <connection
+   name="udp_generator.data_out/tx_multiplexer.in1"
+   kind="avalon_streaming"
+   version="19.1"
+   start="udp_generator.data_out"
+   end="tx_multiplexer.in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>udp_generator</startModule>
+  <startConnectionPoint>data_out</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="tx_multiplexer.out/channel_adapter_0.in"
+   kind="avalon_streaming"
+   version="19.1"
+   start="tx_multiplexer.out"
+   end="channel_adapter_0.in">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>tx_multiplexer</startModule>
+  <startConnectionPoint>out</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>in</endConnectionPoint>
+ </connection>
+ <connection
+   name="channel_adapter_0.out/eth_tse.transmit"
+   kind="avalon_streaming"
+   version="19.1"
+   start="channel_adapter_0.out"
+   end="eth_tse.transmit">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>channel_adapter_0</startModule>
+  <startConnectionPoint>out</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>transmit</endConnectionPoint>
+ </connection>
+ <connection
+   name="eth_tse.receive/msgdma_rx.st_sink"
+   kind="avalon_streaming"
+   version="19.1"
+   start="eth_tse.receive"
+   end="msgdma_rx.st_sink">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>eth_tse</startModule>
+  <startConnectionPoint>receive</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>st_sink</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.st_source/tx_multiplexer.in0"
+   kind="avalon_streaming"
+   version="19.1"
+   start="msgdma_tx.st_source"
+   end="tx_multiplexer.in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>st_source</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sysid.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sysid.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sys_clk_timer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sys_clk_timer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/cpu.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="cpu.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/output_pio.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="output_pio.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/button_pio.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="button_pio.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/debug_uart.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="debug_uart.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/onchip_flash.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="onchip_flash.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/tx_multiplexer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="tx_multiplexer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/channel_adapter_0.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="channel_adapter_0.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/udp_generator.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="udp_generator.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/frame_timer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="frame_timer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sensor_interface.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sensor_interface.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/descriptor_memory.clk1"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="descriptor_memory.clk1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>clk1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/calibration_ram.clk1"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>clk1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/calibration_ram.clk2"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk2">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>clk2</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/msgdma_tx.clock"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="msgdma_tx.clock">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>clock</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/msgdma_rx.clock"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="msgdma_rx.clock">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>clock</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.control_port_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.control_port_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>control_port_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/enet_pll.inclk_interface"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="enet_pll.inclk_interface">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>enet_pll</endModule>
+  <endConnectionPoint>inclk_interface</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/altpll_shift.inclk_interface"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="altpll_shift.inclk_interface">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>altpll_shift</endModule>
+  <endConnectionPoint>inclk_interface</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.receive_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.receive_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>receive_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.transmit_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.transmit_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>transmit_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="ext_flash_clock_bridge.out_clk/ext_flash.clock_sink"
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="ext_flash.clock_sink">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ext_flash_clock_bridge</startModule>
+  <startConnectionPoint>out_clk</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/msgdma_tx.csr_irq"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_tx.csr_irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>csr_irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/msgdma_rx.csr_irq"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_rx.csr_irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>csr_irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/ext_flash.interrupt_sender"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="ext_flash.interrupt_sender">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/sys_clk_timer.irq"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/debug_uart.irq"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="debug_uart.irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/onchip_flash.nreset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="onchip_flash.nreset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>nreset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/sys_clk_timer.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sys_clk_timer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/sysid.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sysid.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/cpu.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="cpu.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/output_pio.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="output_pio.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/ext_flash.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="ext_flash.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/button_pio.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="button_pio.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/debug_uart.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="debug_uart.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/tx_multiplexer.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="tx_multiplexer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/channel_adapter_0.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="channel_adapter_0.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/frame_timer.reset"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="frame_timer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/descriptor_memory.reset1"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="descriptor_memory.reset1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>reset1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/calibration_ram.reset1"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="calibration_ram.reset1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>reset1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/calibration_ram.reset2"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="calibration_ram.reset2">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>reset2</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/eth_tse.reset_connection"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="eth_tse.reset_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>reset_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/msgdma_tx.reset_n"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_tx.reset_n">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>reset_n</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/msgdma_rx.reset_n"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_rx.reset_n">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>reset_n</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/udp_generator.rst"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="udp_generator.rst">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>rst</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/sensor_interface.rst"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sensor_interface.rst">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>rst</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/ddr3_ram.global_reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.global_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>global_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/ext_flash.reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ext_flash.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/sys_clk_timer.reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sys_clk_timer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/sysid.reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sysid.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/output_pio.reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="output_pio.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/descriptor_memory.reset1"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="descriptor_memory.reset1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>reset1</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/eth_tse.reset_connection"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="eth_tse.reset_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>reset_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/ddr3_ram.soft_reset"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.soft_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>soft_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/ddr3_ram.global_reset"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.global_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>global_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/altpll_shift.inclk_interface_reset"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="altpll_shift.inclk_interface_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>altpll_shift</endModule>
+  <endConnectionPoint>inclk_interface_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/enet_pll.inclk_interface_reset"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="enet_pll.inclk_interface_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>enet_pll</endModule>
+  <endConnectionPoint>inclk_interface_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/ddr3_ram.soft_reset"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.soft_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>soft_reset</endConnectionPoint>
+ </connection>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altpll</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTPLL Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>27</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>24</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>24</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>9</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>20</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_pio</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_onchip_memory2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>channel_adapter</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Channel Adapter</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>6</instanceCount>
+  <name>avalon_streaming_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Sink</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>6</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_nios2_gen2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Nios II Processor</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>9</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>interrupt_receiver</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Interrupt Receiver</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>4</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>nios_custom_instruction_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Custom Instruction Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_mem_if_ddr3_emif</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>DDR3 SDRAM Controller with UniPHY Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_reset_bridge</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Reset Bridge</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_uart</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>UART (RS-232 Serial Port) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>6</instanceCount>
+  <name>interrupt_sender</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Interrupt Sender</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_eth_tse</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Triple-Speed Ethernet Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_generic_quad_spi_controller</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Generic QUAD SPI Controller Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_clock_bridge</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Bridge</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_timer</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Interval Timer Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_msgdma</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Modular Scatter-Gather DMA Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_onchip_flash</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Flash Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_sysid_qsys</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>System ID Peripheral Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>multiplexer</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Multiplexer</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>udp_generator</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>UDP generator</displayName>
+  <version>1.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>32</instanceCount>
+  <name>avalon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Avalon Memory Mapped Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>6</instanceCount>
+  <name>avalon_streaming</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Avalon Streaming Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>23</instanceCount>
+  <name>clock</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Clock Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>5</instanceCount>
+  <name>interrupt</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Interrupt Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>31</instanceCount>
+  <name>reset</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Reset Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/q_sys/cali_ram.bsf b/FPGA_firmware/q_sys/cali_ram.bsf
new file mode 100644
index 0000000..87ff5c1
--- /dev/null
+++ b/FPGA_firmware/q_sys/cali_ram.bsf
@@ -0,0 +1,200 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 384 496)
+	(text "cali_ram" (rect 167 -1 201 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 480 20 492)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "cali_ram_clk1_clk" (rect 0 0 70 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_clk1_clk" (rect 4 61 106 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 160 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "cali_ram_clk2_clk" (rect 0 0 71 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_clk2_clk" (rect 4 101 106 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 160 112)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "cali_ram_reset1_reset" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_reset1_reset" (rect 4 141 130 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 160 152)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "cali_ram_reset2_reset" (rect 0 0 90 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_reset2_reset" (rect 4 181 130 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 160 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "cali_ram_s1_address[8..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_address[8..0]" (rect 4 221 154 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 160 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "cali_ram_s1_clken" (rect 0 0 74 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_clken" (rect 4 237 106 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 160 248)(line_width 1))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "cali_ram_s1_chipselect" (rect 0 0 92 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_chipselect" (rect 4 253 136 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 160 264)(line_width 1))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "cali_ram_s1_write" (rect 0 0 71 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_write" (rect 4 269 106 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 160 280)(line_width 1))
+	)
+	(port
+		(pt 0 312)
+		(input)
+		(text "cali_ram_s1_writedata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_writedata[15..0]" (rect 4 301 172 312)(font "Arial" (font_size 8)))
+		(line (pt 0 312)(pt 160 312)(line_width 3))
+	)
+	(port
+		(pt 0 328)
+		(input)
+		(text "cali_ram_s1_byteenable[1..0]" (rect 0 0 115 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_byteenable[1..0]" (rect 4 317 172 328)(font "Arial" (font_size 8)))
+		(line (pt 0 328)(pt 160 328)(line_width 3))
+	)
+	(port
+		(pt 0 368)
+		(input)
+		(text "cali_ram_s2_address[8..0]" (rect 0 0 107 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_address[8..0]" (rect 4 357 154 368)(font "Arial" (font_size 8)))
+		(line (pt 0 368)(pt 160 368)(line_width 3))
+	)
+	(port
+		(pt 0 384)
+		(input)
+		(text "cali_ram_s2_chipselect" (rect 0 0 93 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_chipselect" (rect 4 373 136 384)(font "Arial" (font_size 8)))
+		(line (pt 0 384)(pt 160 384)(line_width 1))
+	)
+	(port
+		(pt 0 400)
+		(input)
+		(text "cali_ram_s2_clken" (rect 0 0 75 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_clken" (rect 4 389 106 400)(font "Arial" (font_size 8)))
+		(line (pt 0 400)(pt 160 400)(line_width 1))
+	)
+	(port
+		(pt 0 416)
+		(input)
+		(text "cali_ram_s2_write" (rect 0 0 73 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_write" (rect 4 405 106 416)(font "Arial" (font_size 8)))
+		(line (pt 0 416)(pt 160 416)(line_width 1))
+	)
+	(port
+		(pt 0 448)
+		(input)
+		(text "cali_ram_s2_writedata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_writedata[15..0]" (rect 4 437 172 448)(font "Arial" (font_size 8)))
+		(line (pt 0 448)(pt 160 448)(line_width 3))
+	)
+	(port
+		(pt 0 464)
+		(input)
+		(text "cali_ram_s2_byteenable[1..0]" (rect 0 0 116 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_byteenable[1..0]" (rect 4 453 172 464)(font "Arial" (font_size 8)))
+		(line (pt 0 464)(pt 160 464)(line_width 3))
+	)
+	(port
+		(pt 0 296)
+		(output)
+		(text "cali_ram_s1_readdata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_readdata[15..0]" (rect 4 285 166 296)(font "Arial" (font_size 8)))
+		(line (pt 0 296)(pt 160 296)(line_width 3))
+	)
+	(port
+		(pt 0 432)
+		(output)
+		(text "cali_ram_s2_readdata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_readdata[15..0]" (rect 4 421 166 432)(font "Arial" (font_size 8)))
+		(line (pt 0 432)(pt 160 432)(line_width 3))
+	)
+	(drawing
+		(text "cali_ram_clk1" (rect 82 43 242 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_clk2" (rect 80 83 238 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 107 348 224)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_reset1" (rect 68 123 226 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 147 360 304)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_reset2" (rect 66 163 222 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 187 360 384)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_s1" (rect 91 203 248 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 165 227 372 464)(font "Arial" (color 0 0 0)))
+		(text "clken" (rect 165 243 360 496)(font "Arial" (color 0 0 0)))
+		(text "chipselect" (rect 165 259 390 528)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 165 275 360 560)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 165 291 378 592)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 165 307 384 624)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 165 323 390 656)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_s2" (rect 89 339 244 691)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 165 363 372 736)(font "Arial" (color 0 0 0)))
+		(text "chipselect" (rect 165 379 390 768)(font "Arial" (color 0 0 0)))
+		(text "clken" (rect 165 395 360 800)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 165 411 360 832)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 165 427 378 864)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 165 443 384 896)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 165 459 390 928)(font "Arial" (color 0 0 0)))
+		(text " cali_ram " (rect 344 480 748 970)(font "Arial" ))
+		(line (pt 160 32)(pt 224 32)(line_width 1))
+		(line (pt 224 32)(pt 224 480)(line_width 1))
+		(line (pt 160 480)(pt 224 480)(line_width 1))
+		(line (pt 160 32)(pt 160 480)(line_width 1))
+		(line (pt 161 52)(pt 161 76)(line_width 1))
+		(line (pt 162 52)(pt 162 76)(line_width 1))
+		(line (pt 161 92)(pt 161 116)(line_width 1))
+		(line (pt 162 92)(pt 162 116)(line_width 1))
+		(line (pt 161 132)(pt 161 156)(line_width 1))
+		(line (pt 162 132)(pt 162 156)(line_width 1))
+		(line (pt 161 172)(pt 161 196)(line_width 1))
+		(line (pt 162 172)(pt 162 196)(line_width 1))
+		(line (pt 161 212)(pt 161 332)(line_width 1))
+		(line (pt 162 212)(pt 162 332)(line_width 1))
+		(line (pt 161 348)(pt 161 468)(line_width 1))
+		(line (pt 162 348)(pt 162 468)(line_width 1))
+		(line (pt 0 0)(pt 384 0)(line_width 1))
+		(line (pt 384 0)(pt 384 496)(line_width 1))
+		(line (pt 0 496)(pt 384 496)(line_width 1))
+		(line (pt 0 0)(pt 0 496)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/q_sys/cali_ram.xml b/FPGA_firmware/q_sys/cali_ram.xml
new file mode 100644
index 0000000..59707a1
--- /dev/null
+++ b/FPGA_firmware/q_sys/cali_ram.xml
@@ -0,0 +1,343 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.02.15:49:43"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="cali_ram_clk1" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="cali_ram_clk1_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="cali_ram_clk2" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="cali_ram_clk2_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="cali_ram_reset1" kind="reset" start="0">
+   <property name="associatedClock" value="cali_ram_clk1" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port name="cali_ram_reset1_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="cali_ram_reset2" kind="reset" start="0">
+   <property name="associatedClock" value="cali_ram_clk2" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port name="cali_ram_reset2_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="cali_ram_s1" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="1" />
+   <property name="addressSpan" value="640" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="cali_ram_clk1" />
+   <property name="associatedReset" value="cali_ram_reset1" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="640" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="true" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="1" />
+   <property name="readWaitStates" value="0" />
+   <property name="readWaitTime" value="0" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port name="cali_ram_s1_address" direction="input" role="address" width="9" />
+   <port name="cali_ram_s1_clken" direction="input" role="clken" width="1" />
+   <port
+       name="cali_ram_s1_chipselect"
+       direction="input"
+       role="chipselect"
+       width="1" />
+   <port name="cali_ram_s1_write" direction="input" role="write" width="1" />
+   <port
+       name="cali_ram_s1_readdata"
+       direction="output"
+       role="readdata"
+       width="16" />
+   <port
+       name="cali_ram_s1_writedata"
+       direction="input"
+       role="writedata"
+       width="16" />
+   <port
+       name="cali_ram_s1_byteenable"
+       direction="input"
+       role="byteenable"
+       width="2" />
+  </interface>
+  <interface name="cali_ram_s2" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="1" />
+   <property name="addressSpan" value="640" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="cali_ram_clk2" />
+   <property name="associatedReset" value="cali_ram_reset2" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="640" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="true" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="1" />
+   <property name="readWaitStates" value="0" />
+   <property name="readWaitTime" value="0" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port name="cali_ram_s2_address" direction="input" role="address" width="9" />
+   <port
+       name="cali_ram_s2_chipselect"
+       direction="input"
+       role="chipselect"
+       width="1" />
+   <port name="cali_ram_s2_clken" direction="input" role="clken" width="1" />
+   <port name="cali_ram_s2_write" direction="input" role="write" width="1" />
+   <port
+       name="cali_ram_s2_readdata"
+       direction="output"
+       role="readdata"
+       width="16" />
+   <port
+       name="cali_ram_s2_writedata"
+       direction="input"
+       role="writedata"
+       width="16" />
+   <port
+       name="cali_ram_s2_byteenable"
+       direction="input"
+       role="byteenable"
+       width="2" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="cali_ram:1.0:AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN=-1,AUTO_CALI_RAM_CLK1_CLOCK_RATE=-1,AUTO_CALI_RAM_CLK1_RESET_DOMAIN=-1,AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN=-1,AUTO_CALI_RAM_CLK2_CLOCK_RATE=-1,AUTO_CALI_RAM_CLK2_RESET_DOMAIN=-1,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1719928182,AUTO_UNIQUE_ID=(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=cali_ram_cali_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=cali_ram_cali_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)"
+   instancePathKey="cali_ram"
+   kind="cali_ram"
+   version="1.0"
+   name="cali_ram">
+  <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1719928182" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_CALI_RAM_CLK1_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK2_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/cali_ram.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/cali_ram.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:cali_ram "cali_ram"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/cali_ram_cali_ram</b>"]]></message>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram"</message>
+   <message level="Info" culprit="cali_ram">Starting RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cali_ram">Done RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>cali_ram</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=cali_ram_cali_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=cali_ram_cali_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
+   instancePathKey="cali_ram:.:cali_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   name="cali_ram_cali_ram">
+  <parameter name="derived_singleClockOperation" value="false" />
+  <parameter name="derived_is_hardcopy" value="false" />
+  <parameter
+     name="deviceFeatures"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="autoInitializationFileName" value="cali_ram_cali_ram" />
+  <parameter name="derived_gui_ram_block_type" value="Automatic" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="dualPort" value="true" />
+  <parameter name="derived_set_addr_width2" value="9" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="derived_set_addr_width" value="9" />
+  <parameter name="derived_init_file_name" value="cali_ram_cali_ram.hex" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="derived_set_data_width2" value="16" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="derived_enableDiffWidth" value="false" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="derived_set_data_width" value="16" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="cali_ram" as="cali_ram" />
+  <messages>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram"</message>
+   <message level="Info" culprit="cali_ram">Starting RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cali_ram">Done RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>cali_ram</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/q_sys/cali_ram_bb.v b/FPGA_firmware/q_sys/cali_ram_bb.v
new file mode 100644
index 0000000..bc874bc
--- /dev/null
+++ b/FPGA_firmware/q_sys/cali_ram_bb.v
@@ -0,0 +1,40 @@
+
+module cali_ram (
+	cali_ram_s2_address,
+	cali_ram_s2_chipselect,
+	cali_ram_s2_clken,
+	cali_ram_s2_write,
+	cali_ram_s2_readdata,
+	cali_ram_s2_writedata,
+	cali_ram_s2_byteenable,
+	cali_ram_clk2_clk,
+	cali_ram_reset2_reset,
+	cali_ram_reset1_reset,
+	cali_ram_s1_address,
+	cali_ram_s1_clken,
+	cali_ram_s1_chipselect,
+	cali_ram_s1_write,
+	cali_ram_s1_readdata,
+	cali_ram_s1_writedata,
+	cali_ram_s1_byteenable,
+	cali_ram_clk1_clk);	
+
+	input	[8:0]	cali_ram_s2_address;
+	input		cali_ram_s2_chipselect;
+	input		cali_ram_s2_clken;
+	input		cali_ram_s2_write;
+	output	[15:0]	cali_ram_s2_readdata;
+	input	[15:0]	cali_ram_s2_writedata;
+	input	[1:0]	cali_ram_s2_byteenable;
+	input		cali_ram_clk2_clk;
+	input		cali_ram_reset2_reset;
+	input		cali_ram_reset1_reset;
+	input	[8:0]	cali_ram_s1_address;
+	input		cali_ram_s1_clken;
+	input		cali_ram_s1_chipselect;
+	input		cali_ram_s1_write;
+	output	[15:0]	cali_ram_s1_readdata;
+	input	[15:0]	cali_ram_s1_writedata;
+	input	[1:0]	cali_ram_s1_byteenable;
+	input		cali_ram_clk1_clk;
+endmodule
diff --git a/FPGA_firmware/q_sys/cali_ram_inst.v b/FPGA_firmware/q_sys/cali_ram_inst.v
new file mode 100644
index 0000000..a82c29e
--- /dev/null
+++ b/FPGA_firmware/q_sys/cali_ram_inst.v
@@ -0,0 +1,21 @@
+	cali_ram u0 (
+		.cali_ram_s2_address    (<connected-to-cali_ram_s2_address>),    //     cali_ram_s2.address
+		.cali_ram_s2_chipselect (<connected-to-cali_ram_s2_chipselect>), //                .chipselect
+		.cali_ram_s2_clken      (<connected-to-cali_ram_s2_clken>),      //                .clken
+		.cali_ram_s2_write      (<connected-to-cali_ram_s2_write>),      //                .write
+		.cali_ram_s2_readdata   (<connected-to-cali_ram_s2_readdata>),   //                .readdata
+		.cali_ram_s2_writedata  (<connected-to-cali_ram_s2_writedata>),  //                .writedata
+		.cali_ram_s2_byteenable (<connected-to-cali_ram_s2_byteenable>), //                .byteenable
+		.cali_ram_clk2_clk      (<connected-to-cali_ram_clk2_clk>),      //   cali_ram_clk2.clk
+		.cali_ram_reset2_reset  (<connected-to-cali_ram_reset2_reset>),  // cali_ram_reset2.reset
+		.cali_ram_reset1_reset  (<connected-to-cali_ram_reset1_reset>),  // cali_ram_reset1.reset
+		.cali_ram_s1_address    (<connected-to-cali_ram_s1_address>),    //     cali_ram_s1.address
+		.cali_ram_s1_clken      (<connected-to-cali_ram_s1_clken>),      //                .clken
+		.cali_ram_s1_chipselect (<connected-to-cali_ram_s1_chipselect>), //                .chipselect
+		.cali_ram_s1_write      (<connected-to-cali_ram_s1_write>),      //                .write
+		.cali_ram_s1_readdata   (<connected-to-cali_ram_s1_readdata>),   //                .readdata
+		.cali_ram_s1_writedata  (<connected-to-cali_ram_s1_writedata>),  //                .writedata
+		.cali_ram_s1_byteenable (<connected-to-cali_ram_s1_byteenable>), //                .byteenable
+		.cali_ram_clk1_clk      (<connected-to-cali_ram_clk1_clk>)       //   cali_ram_clk1.clk
+	);
+
diff --git a/FPGA_firmware/q_sys/q_sys.bsf b/FPGA_firmware/q_sys/q_sys.bsf
new file mode 100644
index 0000000..5c70fdd
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys.bsf
@@ -0,0 +1,640 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 624 1568)
+	(text "q_sys" (rect 295 -1 320 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 1552 20 1564)(font "Arial" ))
+	(port
+		(pt 0 112)
+		(input)
+		(text "button_pio_external_connection_export[8..0]" (rect 0 0 174 12)(font "Arial" (font_size 8)))
+		(text "button_pio_external_connection_export[8..0]" (rect 4 101 262 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 256 112)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "clock_bridge_0_in_clk_clk" (rect 0 0 105 12)(font "Arial" (font_size 8)))
+		(text "clock_bridge_0_in_clk_clk" (rect 4 141 154 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 256 152)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "ddr3_ram_pll_ref_clk_clk" (rect 0 0 103 12)(font "Arial" (font_size 8)))
+		(text "ddr3_ram_pll_ref_clk_clk" (rect 4 181 148 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 256 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "debug_uart_external_connection_rxd" (rect 0 0 147 12)(font "Arial" (font_size 8)))
+		(text "debug_uart_external_connection_rxd" (rect 4 221 208 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 256 232)(line_width 1))
+	)
+	(port
+		(pt 0 344)
+		(input)
+		(text "eth_tse_mac_mdio_connection_mdio_in" (rect 0 0 161 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_mdio_connection_mdio_in" (rect 4 333 214 344)(font "Arial" (font_size 8)))
+		(line (pt 0 344)(pt 256 344)(line_width 1))
+	)
+	(port
+		(pt 0 416)
+		(input)
+		(text "eth_tse_mac_rgmii_connection_rgmii_in[3..0]" (rect 0 0 181 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_rgmii_connection_rgmii_in[3..0]" (rect 4 405 262 416)(font "Arial" (font_size 8)))
+		(line (pt 0 416)(pt 256 416)(line_width 3))
+	)
+	(port
+		(pt 0 448)
+		(input)
+		(text "eth_tse_mac_rgmii_connection_rx_control" (rect 0 0 171 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_rgmii_connection_rx_control" (rect 4 437 238 448)(font "Arial" (font_size 8)))
+		(line (pt 0 448)(pt 256 448)(line_width 1))
+	)
+	(port
+		(pt 0 504)
+		(input)
+		(text "eth_tse_mac_status_connection_set_10" (rect 0 0 161 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_status_connection_set_10" (rect 4 493 220 504)(font "Arial" (font_size 8)))
+		(line (pt 0 504)(pt 256 504)(line_width 1))
+	)
+	(port
+		(pt 0 520)
+		(input)
+		(text "eth_tse_mac_status_connection_set_1000" (rect 0 0 171 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_status_connection_set_1000" (rect 4 509 232 520)(font "Arial" (font_size 8)))
+		(line (pt 0 520)(pt 256 520)(line_width 1))
+	)
+	(port
+		(pt 0 592)
+		(input)
+		(text "eth_tse_pcs_mac_rx_clock_connection_clk" (rect 0 0 177 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_pcs_mac_rx_clock_connection_clk" (rect 4 581 238 592)(font "Arial" (font_size 8)))
+		(line (pt 0 592)(pt 256 592)(line_width 1))
+	)
+	(port
+		(pt 0 632)
+		(input)
+		(text "eth_tse_pcs_mac_tx_clock_connection_clk" (rect 0 0 175 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_pcs_mac_tx_clock_connection_clk" (rect 4 621 238 632)(font "Arial" (font_size 8)))
+		(line (pt 0 632)(pt 256 632)(line_width 1))
+	)
+	(port
+		(pt 0 944)
+		(input)
+		(text "mem_resetn_in_reset_reset_n" (rect 0 0 126 12)(font "Arial" (font_size 8)))
+		(text "mem_resetn_in_reset_reset_n" (rect 4 933 166 944)(font "Arial" (font_size 8)))
+		(line (pt 0 944)(pt 256 944)(line_width 1))
+	)
+	(port
+		(pt 0 1248)
+		(input)
+		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 4 1237 82 1248)(font "Arial" (font_size 8)))
+		(line (pt 0 1248)(pt 256 1248)(line_width 1))
+	)
+	(port
+		(pt 0 1288)
+		(input)
+		(text "sensor_in_adc_data[4..0]" (rect 0 0 102 12)(font "Arial" (font_size 8)))
+		(text "sensor_in_adc_data[4..0]" (rect 4 1277 148 1288)(font "Arial" (font_size 8)))
+		(line (pt 0 1288)(pt 256 1288)(line_width 3))
+	)
+	(port
+		(pt 0 1304)
+		(input)
+		(text "sensor_in_trg" (rect 0 0 55 12)(font "Arial" (font_size 8)))
+		(text "sensor_in_trg" (rect 4 1293 82 1304)(font "Arial" (font_size 8)))
+		(line (pt 0 1304)(pt 256 1304)(line_width 1))
+	)
+	(port
+		(pt 0 1464)
+		(input)
+		(text "sensor_synchro_ext_input[7..0]" (rect 0 0 127 12)(font "Arial" (font_size 8)))
+		(text "sensor_synchro_ext_input[7..0]" (rect 4 1453 184 1464)(font "Arial" (font_size 8)))
+		(line (pt 0 1464)(pt 256 1464)(line_width 3))
+	)
+	(port
+		(pt 0 1480)
+		(input)
+		(text "sensor_synchro_serial_rx" (rect 0 0 106 12)(font "Arial" (font_size 8)))
+		(text "sensor_synchro_serial_rx" (rect 4 1469 148 1480)(font "Arial" (font_size 8)))
+		(line (pt 0 1480)(pt 256 1480)(line_width 1))
+	)
+	(port
+		(pt 0 1536)
+		(input)
+		(text "sys_clk_clk" (rect 0 0 48 12)(font "Arial" (font_size 8)))
+		(text "sys_clk_clk" (rect 4 1525 70 1536)(font "Arial" (font_size 8)))
+		(line (pt 0 1536)(pt 256 1536)(line_width 1))
+	)
+	(port
+		(pt 624 72)
+		(output)
+		(text "altpll_shift_c0_clk" (rect 0 0 69 12)(font "Arial" (font_size 8)))
+		(text "altpll_shift_c0_clk" (rect 533 61 647 72)(font "Arial" (font_size 8)))
+		(line (pt 624 72)(pt 368 72)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(output)
+		(text "altpll_shift_locked_conduit_export" (rect 0 0 132 12)(font "Arial" (font_size 8)))
+		(text "altpll_shift_locked_conduit_export" (rect 4 61 208 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 256 72)(line_width 1))
+	)
+	(port
+		(pt 0 248)
+		(output)
+		(text "debug_uart_external_connection_txd" (rect 0 0 146 12)(font "Arial" (font_size 8)))
+		(text "debug_uart_external_connection_txd" (rect 4 237 208 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 256 248)(line_width 1))
+	)
+	(port
+		(pt 624 112)
+		(output)
+		(text "enet_pll_c0_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_c0_clk" (rect 545 101 635 112)(font "Arial" (font_size 8)))
+		(line (pt 624 112)(pt 368 112)(line_width 1))
+	)
+	(port
+		(pt 624 152)
+		(output)
+		(text "enet_pll_c1_clk" (rect 0 0 60 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_c1_clk" (rect 547 141 637 152)(font "Arial" (font_size 8)))
+		(line (pt 624 152)(pt 368 152)(line_width 1))
+	)
+	(port
+		(pt 624 192)
+		(output)
+		(text "enet_pll_c2_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_c2_clk" (rect 545 181 635 192)(font "Arial" (font_size 8)))
+		(line (pt 624 192)(pt 368 192)(line_width 1))
+	)
+	(port
+		(pt 624 232)
+		(output)
+		(text "enet_pll_c3_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_c3_clk" (rect 545 221 635 232)(font "Arial" (font_size 8)))
+		(line (pt 624 232)(pt 368 232)(line_width 1))
+	)
+	(port
+		(pt 624 272)
+		(output)
+		(text "enet_pll_c4_clk" (rect 0 0 62 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_c4_clk" (rect 545 261 635 272)(font "Arial" (font_size 8)))
+		(line (pt 624 272)(pt 368 272)(line_width 1))
+	)
+	(port
+		(pt 0 288)
+		(output)
+		(text "enet_pll_locked_conduit_export" (rect 0 0 123 12)(font "Arial" (font_size 8)))
+		(text "enet_pll_locked_conduit_export" (rect 4 277 184 288)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 256 288)(line_width 1))
+	)
+	(port
+		(pt 0 328)
+		(output)
+		(text "eth_tse_mac_mdio_connection_mdc" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_mdio_connection_mdc" (rect 4 317 190 328)(font "Arial" (font_size 8)))
+		(line (pt 0 328)(pt 256 328)(line_width 1))
+	)
+	(port
+		(pt 0 360)
+		(output)
+		(text "eth_tse_mac_mdio_connection_mdio_out" (rect 0 0 167 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_mdio_connection_mdio_out" (rect 4 349 220 360)(font "Arial" (font_size 8)))
+		(line (pt 0 360)(pt 256 360)(line_width 1))
+	)
+	(port
+		(pt 0 376)
+		(output)
+		(text "eth_tse_mac_mdio_connection_mdio_oen" (rect 0 0 169 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_mdio_connection_mdio_oen" (rect 4 365 220 376)(font "Arial" (font_size 8)))
+		(line (pt 0 376)(pt 256 376)(line_width 1))
+	)
+	(port
+		(pt 0 432)
+		(output)
+		(text "eth_tse_mac_rgmii_connection_rgmii_out[3..0]" (rect 0 0 187 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_rgmii_connection_rgmii_out[3..0]" (rect 4 421 268 432)(font "Arial" (font_size 8)))
+		(line (pt 0 432)(pt 256 432)(line_width 3))
+	)
+	(port
+		(pt 0 464)
+		(output)
+		(text "eth_tse_mac_rgmii_connection_tx_control" (rect 0 0 169 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_rgmii_connection_tx_control" (rect 4 453 238 464)(font "Arial" (font_size 8)))
+		(line (pt 0 464)(pt 256 464)(line_width 1))
+	)
+	(port
+		(pt 0 536)
+		(output)
+		(text "eth_tse_mac_status_connection_eth_mode" (rect 0 0 175 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_status_connection_eth_mode" (rect 4 525 232 536)(font "Arial" (font_size 8)))
+		(line (pt 0 536)(pt 256 536)(line_width 1))
+	)
+	(port
+		(pt 0 552)
+		(output)
+		(text "eth_tse_mac_status_connection_ena_10" (rect 0 0 164 12)(font "Arial" (font_size 8)))
+		(text "eth_tse_mac_status_connection_ena_10" (rect 4 541 220 552)(font "Arial" (font_size 8)))
+		(line (pt 0 552)(pt 256 552)(line_width 1))
+	)
+	(port
+		(pt 0 712)
+		(output)
+		(text "ext_flash_flash_dclk_out_conduit_dclk_out" (rect 0 0 172 12)(font "Arial" (font_size 8)))
+		(text "ext_flash_flash_dclk_out_conduit_dclk_out" (rect 4 701 250 712)(font "Arial" (font_size 8)))
+		(line (pt 0 712)(pt 256 712)(line_width 1))
+	)
+	(port
+		(pt 0 752)
+		(output)
+		(text "ext_flash_flash_ncs_conduit_ncs" (rect 0 0 134 12)(font "Arial" (font_size 8)))
+		(text "ext_flash_flash_ncs_conduit_ncs" (rect 4 741 190 752)(font "Arial" (font_size 8)))
+		(line (pt 0 752)(pt 256 752)(line_width 1))
+	)
+	(port
+		(pt 0 792)
+		(output)
+		(text "frame_timer_export" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+		(text "frame_timer_export" (rect 4 781 112 792)(font "Arial" (font_size 8)))
+		(line (pt 0 792)(pt 256 792)(line_width 1))
+	)
+	(port
+		(pt 0 832)
+		(output)
+		(text "led_pio_external_connection_export[7..0]" (rect 0 0 161 12)(font "Arial" (font_size 8)))
+		(text "led_pio_external_connection_export[7..0]" (rect 4 821 244 832)(font "Arial" (font_size 8)))
+		(line (pt 0 832)(pt 256 832)(line_width 3))
+	)
+	(port
+		(pt 0 872)
+		(output)
+		(text "mem_if_ddr3_emif_0_status_local_init_done" (rect 0 0 181 12)(font "Arial" (font_size 8)))
+		(text "mem_if_ddr3_emif_0_status_local_init_done" (rect 4 861 250 872)(font "Arial" (font_size 8)))
+		(line (pt 0 872)(pt 256 872)(line_width 1))
+	)
+	(port
+		(pt 0 888)
+		(output)
+		(text "mem_if_ddr3_emif_0_status_local_cal_success" (rect 0 0 197 12)(font "Arial" (font_size 8)))
+		(text "mem_if_ddr3_emif_0_status_local_cal_success" (rect 4 877 262 888)(font "Arial" (font_size 8)))
+		(line (pt 0 888)(pt 256 888)(line_width 1))
+	)
+	(port
+		(pt 0 904)
+		(output)
+		(text "mem_if_ddr3_emif_0_status_local_cal_fail" (rect 0 0 174 12)(font "Arial" (font_size 8)))
+		(text "mem_if_ddr3_emif_0_status_local_cal_fail" (rect 4 893 244 904)(font "Arial" (font_size 8)))
+		(line (pt 0 904)(pt 256 904)(line_width 1))
+	)
+	(port
+		(pt 0 984)
+		(output)
+		(text "memory_mem_a[13..0]" (rect 0 0 96 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_a[13..0]" (rect 4 973 118 984)(font "Arial" (font_size 8)))
+		(line (pt 0 984)(pt 256 984)(line_width 3))
+	)
+	(port
+		(pt 0 1000)
+		(output)
+		(text "memory_mem_ba[2..0]" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_ba[2..0]" (rect 4 989 118 1000)(font "Arial" (font_size 8)))
+		(line (pt 0 1000)(pt 256 1000)(line_width 3))
+	)
+	(port
+		(pt 0 1048)
+		(output)
+		(text "memory_mem_cke" (rect 0 0 82 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_cke" (rect 4 1037 88 1048)(font "Arial" (font_size 8)))
+		(line (pt 0 1048)(pt 256 1048)(line_width 1))
+	)
+	(port
+		(pt 0 1064)
+		(output)
+		(text "memory_mem_cs_n" (rect 0 0 88 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_cs_n" (rect 4 1053 94 1064)(font "Arial" (font_size 8)))
+		(line (pt 0 1064)(pt 256 1064)(line_width 1))
+	)
+	(port
+		(pt 0 1080)
+		(output)
+		(text "memory_mem_dm" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_dm" (rect 4 1069 82 1080)(font "Arial" (font_size 8)))
+		(line (pt 0 1080)(pt 256 1080)(line_width 1))
+	)
+	(port
+		(pt 0 1096)
+		(output)
+		(text "memory_mem_ras_n" (rect 0 0 92 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_ras_n" (rect 4 1085 100 1096)(font "Arial" (font_size 8)))
+		(line (pt 0 1096)(pt 256 1096)(line_width 1))
+	)
+	(port
+		(pt 0 1112)
+		(output)
+		(text "memory_mem_cas_n" (rect 0 0 93 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_cas_n" (rect 4 1101 100 1112)(font "Arial" (font_size 8)))
+		(line (pt 0 1112)(pt 256 1112)(line_width 1))
+	)
+	(port
+		(pt 0 1128)
+		(output)
+		(text "memory_mem_we_n" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_we_n" (rect 4 1117 94 1128)(font "Arial" (font_size 8)))
+		(line (pt 0 1128)(pt 256 1128)(line_width 1))
+	)
+	(port
+		(pt 0 1144)
+		(output)
+		(text "memory_mem_reset_n" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_reset_n" (rect 4 1133 112 1144)(font "Arial" (font_size 8)))
+		(line (pt 0 1144)(pt 256 1144)(line_width 1))
+	)
+	(port
+		(pt 0 1208)
+		(output)
+		(text "memory_mem_odt" (rect 0 0 80 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_odt" (rect 4 1197 88 1208)(font "Arial" (font_size 8)))
+		(line (pt 0 1208)(pt 256 1208)(line_width 1))
+	)
+	(port
+		(pt 0 1320)
+		(output)
+		(text "sensor_out_adc_clk" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+		(text "sensor_out_adc_clk" (rect 4 1309 112 1320)(font "Arial" (font_size 8)))
+		(line (pt 0 1320)(pt 256 1320)(line_width 1))
+	)
+	(port
+		(pt 0 1336)
+		(output)
+		(text "sensor_out_adc_cnv" (rect 0 0 86 12)(font "Arial" (font_size 8)))
+		(text "sensor_out_adc_cnv" (rect 4 1325 112 1336)(font "Arial" (font_size 8)))
+		(line (pt 0 1336)(pt 256 1336)(line_width 1))
+	)
+	(port
+		(pt 0 1352)
+		(output)
+		(text "sensor_out_sensor_clk" (rect 0 0 94 12)(font "Arial" (font_size 8)))
+		(text "sensor_out_sensor_clk" (rect 4 1341 130 1352)(font "Arial" (font_size 8)))
+		(line (pt 0 1352)(pt 256 1352)(line_width 1))
+	)
+	(port
+		(pt 0 1368)
+		(output)
+		(text "sensor_out_sensor_gain" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "sensor_out_sensor_gain" (rect 4 1357 136 1368)(font "Arial" (font_size 8)))
+		(line (pt 0 1368)(pt 256 1368)(line_width 1))
+	)
+	(port
+		(pt 0 1384)
+		(output)
+		(text "sensor_out_sensor_rst" (rect 0 0 94 12)(font "Arial" (font_size 8)))
+		(text "sensor_out_sensor_rst" (rect 4 1373 130 1384)(font "Arial" (font_size 8)))
+		(line (pt 0 1384)(pt 256 1384)(line_width 1))
+	)
+	(port
+		(pt 0 1424)
+		(output)
+		(text "sensor_status_status_out[7..0]" (rect 0 0 123 12)(font "Arial" (font_size 8)))
+		(text "sensor_status_status_out[7..0]" (rect 4 1413 184 1424)(font "Arial" (font_size 8)))
+		(line (pt 0 1424)(pt 256 1424)(line_width 3))
+	)
+	(port
+		(pt 0 1496)
+		(output)
+		(text "sensor_synchro_serial_tx" (rect 0 0 105 12)(font "Arial" (font_size 8)))
+		(text "sensor_synchro_serial_tx" (rect 4 1485 148 1496)(font "Arial" (font_size 8)))
+		(line (pt 0 1496)(pt 256 1496)(line_width 1))
+	)
+	(port
+		(pt 0 672)
+		(bidir)
+		(text "ext_flash_flash_dataout_conduit_dataout[3..0]" (rect 0 0 182 12)(font "Arial" (font_size 8)))
+		(text "ext_flash_flash_dataout_conduit_dataout[3..0]" (rect 4 661 274 672)(font "Arial" (font_size 8)))
+		(line (pt 0 672)(pt 256 672)(line_width 3))
+	)
+	(port
+		(pt 0 1016)
+		(bidir)
+		(text "memory_mem_ck" (rect 0 0 77 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_ck" (rect 4 1005 82 1016)(font "Arial" (font_size 8)))
+		(line (pt 0 1016)(pt 256 1016)(line_width 1))
+	)
+	(port
+		(pt 0 1032)
+		(bidir)
+		(text "memory_mem_ck_n" (rect 0 0 88 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_ck_n" (rect 4 1021 94 1032)(font "Arial" (font_size 8)))
+		(line (pt 0 1032)(pt 256 1032)(line_width 1))
+	)
+	(port
+		(pt 0 1160)
+		(bidir)
+		(text "memory_mem_dq[7..0]" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_dq[7..0]" (rect 4 1149 118 1160)(font "Arial" (font_size 8)))
+		(line (pt 0 1160)(pt 256 1160)(line_width 3))
+	)
+	(port
+		(pt 0 1176)
+		(bidir)
+		(text "memory_mem_dqs" (rect 0 0 82 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_dqs" (rect 4 1165 88 1176)(font "Arial" (font_size 8)))
+		(line (pt 0 1176)(pt 256 1176)(line_width 1))
+	)
+	(port
+		(pt 0 1192)
+		(bidir)
+		(text "memory_mem_dqs_n" (rect 0 0 93 12)(font "Arial" (font_size 8)))
+		(text "memory_mem_dqs_n" (rect 4 1181 100 1192)(font "Arial" (font_size 8)))
+		(line (pt 0 1192)(pt 256 1192)(line_width 1))
+	)
+	(drawing
+		(text "altpll_shift_c0" (rect 369 43 828 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 67 724 144)(font "Arial" (color 0 0 0)))
+		(text "altpll_shift_locked_conduit" (rect 102 43 366 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 261 67 558 144)(font "Arial" (color 0 0 0)))
+		(text "button_pio_external_connection" (rect 73 83 326 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 261 107 558 224)(font "Arial" (color 0 0 0)))
+		(text "clock_bridge_0_in_clk" (rect 127 123 380 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 261 147 540 304)(font "Arial" (color 0 0 0)))
+		(text "ddr3_ram_pll_ref_clk" (rect 130 163 380 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 261 187 540 384)(font "Arial" (color 0 0 0)))
+		(text "debug_uart_external_connection" (rect 68 203 316 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "rxd" (rect 261 227 540 464)(font "Arial" (color 0 0 0)))
+		(text "txd" (rect 261 243 540 496)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_c0" (rect 369 83 804 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 107 724 224)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_c1" (rect 369 123 804 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 147 724 304)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_c2" (rect 369 163 804 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 187 724 384)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_c3" (rect 369 203 804 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 227 724 464)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_c4" (rect 369 243 804 499)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 353 267 724 544)(font "Arial" (color 0 0 0)))
+		(text "enet_pll_locked_conduit" (rect 117 259 372 531)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 261 283 558 576)(font "Arial" (color 0 0 0)))
+		(text "eth_tse_mac_mdio_connection" (rect 76 299 314 611)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "mdc" (rect 261 323 540 656)(font "Arial" (color 0 0 0)))
+		(text "mdio_in" (rect 261 339 564 688)(font "Arial" (color 0 0 0)))
+		(text "mdio_out" (rect 261 355 570 720)(font "Arial" (color 0 0 0)))
+		(text "mdio_oen" (rect 261 371 570 752)(font "Arial" (color 0 0 0)))
+		(text "eth_tse_mac_rgmii_connection" (rect 75 387 318 787)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "rgmii_in" (rect 261 411 570 832)(font "Arial" (color 0 0 0)))
+		(text "rgmii_out" (rect 261 427 576 864)(font "Arial" (color 0 0 0)))
+		(text "rx_control" (rect 261 443 582 896)(font "Arial" (color 0 0 0)))
+		(text "tx_control" (rect 261 459 582 928)(font "Arial" (color 0 0 0)))
+		(text "eth_tse_mac_status_connection" (rect 68 475 310 963)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "set_10" (rect 261 499 558 1008)(font "Arial" (color 0 0 0)))
+		(text "set_1000" (rect 261 515 570 1040)(font "Arial" (color 0 0 0)))
+		(text "eth_mode" (rect 261 531 570 1072)(font "Arial" (color 0 0 0)))
+		(text "ena_10" (rect 261 547 558 1104)(font "Arial" (color 0 0 0)))
+		(text "eth_tse_pcs_mac_rx_clock_connection" (rect 28 563 266 1139)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 261 587 540 1184)(font "Arial" (color 0 0 0)))
+		(text "eth_tse_pcs_mac_tx_clock_connection" (rect 29 603 268 1219)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 261 627 540 1264)(font "Arial" (color 0 0 0)))
+		(text "ext_flash_flash_dataout" (rect 115 643 368 1299)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "conduit_dataout" (rect 261 667 612 1344)(font "Arial" (color 0 0 0)))
+		(text "ext_flash_flash_dclk_out" (rect 109 683 362 1379)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "conduit_dclk_out" (rect 261 707 618 1424)(font "Arial" (color 0 0 0)))
+		(text "ext_flash_flash_ncs" (rect 138 723 390 1459)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "conduit_ncs" (rect 261 747 588 1504)(font "Arial" (color 0 0 0)))
+		(text "frame_timer" (rect 184 763 434 1539)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 261 787 558 1584)(font "Arial" (color 0 0 0)))
+		(text "led_pio_external_connection" (rect 92 803 346 1619)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 261 827 558 1664)(font "Arial" (color 0 0 0)))
+		(text "mem_if_ddr3_emif_0_status" (rect 85 843 320 1699)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "local_init_done" (rect 261 867 612 1744)(font "Arial" (color 0 0 0)))
+		(text "local_cal_success" (rect 261 883 624 1776)(font "Arial" (color 0 0 0)))
+		(text "local_cal_fail" (rect 261 899 606 1808)(font "Arial" (color 0 0 0)))
+		(text "mem_resetn_in_reset" (rect 127 915 368 1843)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset_n" (rect 261 939 564 1888)(font "Arial" (color 0 0 0)))
+		(text "memory" (rect 210 955 456 1923)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "mem_a" (rect 261 979 552 1968)(font "Arial" (color 0 0 0)))
+		(text "mem_ba" (rect 261 995 558 2000)(font "Arial" (color 0 0 0)))
+		(text "mem_ck" (rect 261 1011 558 2032)(font "Arial" (color 0 0 0)))
+		(text "mem_ck_n" (rect 261 1027 570 2064)(font "Arial" (color 0 0 0)))
+		(text "mem_cke" (rect 261 1043 564 2096)(font "Arial" (color 0 0 0)))
+		(text "mem_cs_n" (rect 261 1059 570 2128)(font "Arial" (color 0 0 0)))
+		(text "mem_dm" (rect 261 1075 558 2160)(font "Arial" (color 0 0 0)))
+		(text "mem_ras_n" (rect 261 1091 576 2192)(font "Arial" (color 0 0 0)))
+		(text "mem_cas_n" (rect 261 1107 576 2224)(font "Arial" (color 0 0 0)))
+		(text "mem_we_n" (rect 261 1123 570 2256)(font "Arial" (color 0 0 0)))
+		(text "mem_reset_n" (rect 261 1139 588 2288)(font "Arial" (color 0 0 0)))
+		(text "mem_dq" (rect 261 1155 558 2320)(font "Arial" (color 0 0 0)))
+		(text "mem_dqs" (rect 261 1171 564 2352)(font "Arial" (color 0 0 0)))
+		(text "mem_dqs_n" (rect 261 1187 576 2384)(font "Arial" (color 0 0 0)))
+		(text "mem_odt" (rect 261 1203 564 2416)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 227 1219 484 2451)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset_n" (rect 261 1243 564 2496)(font "Arial" (color 0 0 0)))
+		(text "sensor" (rect 217 1259 470 2531)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "in_adc_data" (rect 261 1283 588 2576)(font "Arial" (color 0 0 0)))
+		(text "in_trg" (rect 261 1299 558 2608)(font "Arial" (color 0 0 0)))
+		(text "out_adc_clk" (rect 261 1315 588 2640)(font "Arial" (color 0 0 0)))
+		(text "out_adc_cnv" (rect 261 1331 588 2672)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_clk" (rect 261 1347 606 2704)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_gain" (rect 261 1363 612 2736)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_rst" (rect 261 1379 606 2768)(font "Arial" (color 0 0 0)))
+		(text "sensor_status" (rect 173 1395 424 2803)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "status_out" (rect 261 1419 582 2848)(font "Arial" (color 0 0 0)))
+		(text "sensor_synchro" (rect 164 1435 412 2883)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ext_input" (rect 261 1459 576 2928)(font "Arial" (color 0 0 0)))
+		(text "serial_rx" (rect 261 1475 576 2960)(font "Arial" (color 0 0 0)))
+		(text "serial_tx" (rect 261 1491 576 2992)(font "Arial" (color 0 0 0)))
+		(text "sys_clk" (rect 213 1507 468 3027)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 261 1531 540 3072)(font "Arial" (color 0 0 0)))
+		(text " q_sys " (rect 594 1552 1230 3114)(font "Arial" ))
+		(line (pt 256 32)(pt 368 32)(line_width 1))
+		(line (pt 368 32)(pt 368 1552)(line_width 1))
+		(line (pt 256 1552)(pt 368 1552)(line_width 1))
+		(line (pt 256 32)(pt 256 1552)(line_width 1))
+		(line (pt 367 52)(pt 367 76)(line_width 1))
+		(line (pt 366 52)(pt 366 76)(line_width 1))
+		(line (pt 257 52)(pt 257 76)(line_width 1))
+		(line (pt 258 52)(pt 258 76)(line_width 1))
+		(line (pt 257 92)(pt 257 116)(line_width 1))
+		(line (pt 258 92)(pt 258 116)(line_width 1))
+		(line (pt 257 132)(pt 257 156)(line_width 1))
+		(line (pt 258 132)(pt 258 156)(line_width 1))
+		(line (pt 257 172)(pt 257 196)(line_width 1))
+		(line (pt 258 172)(pt 258 196)(line_width 1))
+		(line (pt 257 212)(pt 257 252)(line_width 1))
+		(line (pt 258 212)(pt 258 252)(line_width 1))
+		(line (pt 367 92)(pt 367 116)(line_width 1))
+		(line (pt 366 92)(pt 366 116)(line_width 1))
+		(line (pt 367 132)(pt 367 156)(line_width 1))
+		(line (pt 366 132)(pt 366 156)(line_width 1))
+		(line (pt 367 172)(pt 367 196)(line_width 1))
+		(line (pt 366 172)(pt 366 196)(line_width 1))
+		(line (pt 367 212)(pt 367 236)(line_width 1))
+		(line (pt 366 212)(pt 366 236)(line_width 1))
+		(line (pt 367 252)(pt 367 276)(line_width 1))
+		(line (pt 366 252)(pt 366 276)(line_width 1))
+		(line (pt 257 268)(pt 257 292)(line_width 1))
+		(line (pt 258 268)(pt 258 292)(line_width 1))
+		(line (pt 257 308)(pt 257 380)(line_width 1))
+		(line (pt 258 308)(pt 258 380)(line_width 1))
+		(line (pt 257 396)(pt 257 468)(line_width 1))
+		(line (pt 258 396)(pt 258 468)(line_width 1))
+		(line (pt 257 484)(pt 257 556)(line_width 1))
+		(line (pt 258 484)(pt 258 556)(line_width 1))
+		(line (pt 257 572)(pt 257 596)(line_width 1))
+		(line (pt 258 572)(pt 258 596)(line_width 1))
+		(line (pt 257 612)(pt 257 636)(line_width 1))
+		(line (pt 258 612)(pt 258 636)(line_width 1))
+		(line (pt 257 652)(pt 257 676)(line_width 1))
+		(line (pt 258 652)(pt 258 676)(line_width 1))
+		(line (pt 257 692)(pt 257 716)(line_width 1))
+		(line (pt 258 692)(pt 258 716)(line_width 1))
+		(line (pt 257 732)(pt 257 756)(line_width 1))
+		(line (pt 258 732)(pt 258 756)(line_width 1))
+		(line (pt 257 772)(pt 257 796)(line_width 1))
+		(line (pt 258 772)(pt 258 796)(line_width 1))
+		(line (pt 257 812)(pt 257 836)(line_width 1))
+		(line (pt 258 812)(pt 258 836)(line_width 1))
+		(line (pt 257 852)(pt 257 908)(line_width 1))
+		(line (pt 258 852)(pt 258 908)(line_width 1))
+		(line (pt 257 924)(pt 257 948)(line_width 1))
+		(line (pt 258 924)(pt 258 948)(line_width 1))
+		(line (pt 257 964)(pt 257 1212)(line_width 1))
+		(line (pt 258 964)(pt 258 1212)(line_width 1))
+		(line (pt 257 1228)(pt 257 1252)(line_width 1))
+		(line (pt 258 1228)(pt 258 1252)(line_width 1))
+		(line (pt 257 1268)(pt 257 1388)(line_width 1))
+		(line (pt 258 1268)(pt 258 1388)(line_width 1))
+		(line (pt 257 1404)(pt 257 1428)(line_width 1))
+		(line (pt 258 1404)(pt 258 1428)(line_width 1))
+		(line (pt 257 1444)(pt 257 1500)(line_width 1))
+		(line (pt 258 1444)(pt 258 1500)(line_width 1))
+		(line (pt 257 1516)(pt 257 1540)(line_width 1))
+		(line (pt 258 1516)(pt 258 1540)(line_width 1))
+		(line (pt 0 0)(pt 624 0)(line_width 1))
+		(line (pt 624 0)(pt 624 1568)(line_width 1))
+		(line (pt 0 1568)(pt 624 1568)(line_width 1))
+		(line (pt 0 0)(pt 0 1568)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/q_sys/q_sys.csv b/FPGA_firmware/q_sys/q_sys.csv
new file mode 100644
index 0000000..e37e369
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys.csv
@@ -0,0 +1,1000 @@
+# system info q_sys on 2023.06.07.19:46:46
+system_info:
+name,value
+DEVICE,10M50DAF484C6GES
+DEVICE_FAMILY,MAX 10
+GENERATION_ID,1686159938
+#
+#
+# Files generated for q_sys on 2023.06.07.19:46:46
+files:
+filepath,kind,attributes,module,is_top
+simulation/q_sys.v,VERILOG,,q_sys,true
+simulation/submodules/q_sys_altpll_shift.vo,VERILOG,,q_sys_altpll_shift,false
+simulation/submodules/q_sys_button_pio.v,VERILOG,,q_sys_button_pio,false
+simulation/submodules/q_sys_channel_adapter_0.sv,SYSTEM_VERILOG,,q_sys_channel_adapter_0,false
+simulation/submodules/q_sys_cpu.v,VERILOG,,q_sys_cpu,false
+simulation/submodules/q_sys_ddr3_ram.v,VERILOG,,q_sys_ddr3_ram,false
+simulation/submodules/q_sys_debug_uart.v,VERILOG,,q_sys_debug_uart,false
+simulation/submodules/q_sys_descriptor_memory.v,VERILOG,,q_sys_descriptor_memory,false
+simulation/submodules/q_sys_enet_pll.vo,VERILOG,,q_sys_enet_pll,false
+simulation/submodules/q_sys_eth_tse.v,VERILOG,,q_sys_eth_tse,false
+simulation/submodules/q_sys_ext_flash.sv,SYSTEM_VERILOG,,q_sys_ext_flash,false
+simulation/submodules/q_sys_frame_timer.v,VERILOG,,q_sys_frame_timer,false
+simulation/submodules/q_sys_msgdma_rx.v,VERILOG,,q_sys_msgdma_rx,false
+simulation/submodules/q_sys_msgdma_tx.v,VERILOG,,q_sys_msgdma_tx,false
+simulation/submodules/altera_onchip_flash_util.v,VERILOG,,altera_onchip_flash,false
+simulation/submodules/altera_onchip_flash.v,VERILOG,,altera_onchip_flash,false
+simulation/submodules/altera_onchip_flash_avmm_data_controller.v,VERILOG,,altera_onchip_flash,false
+simulation/submodules/altera_onchip_flash_avmm_csr_controller.v,VERILOG,,altera_onchip_flash,false
+simulation/submodules/q_sys_output_pio.v,VERILOG,,q_sys_output_pio,false
+simulation/submodules/sensor_interface.v,VERILOG,,q_sys_sensor_interface,false
+simulation/submodules/q_sys_sys_clk_timer.v,VERILOG,,q_sys_sys_clk_timer,false
+simulation/submodules/q_sys_sysid.v,VERILOG,,q_sys_sysid,false
+simulation/submodules/q_sys_tx_multiplexer.sv,SYSTEM_VERILOG,,q_sys_tx_multiplexer,false
+simulation/submodules/udp_generator.v,VERILOG,,udp_generator,false
+simulation/submodules/q_sys_mm_interconnect_0.v,VERILOG,,q_sys_mm_interconnect_0,false
+simulation/submodules/q_sys_irq_mapper.sv,SYSTEM_VERILOG,,q_sys_irq_mapper,false
+simulation/submodules/altera_irq_clock_crosser.sv,SYSTEM_VERILOG,,altera_irq_clock_crosser,false
+simulation/submodules/q_sys_avalon_st_adapter.v,VERILOG,,q_sys_avalon_st_adapter,false
+simulation/submodules/q_sys_avalon_st_adapter_001.v,VERILOG,,q_sys_avalon_st_adapter_001,false
+simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
+simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
+simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
+simulation/submodules/q_sys_cpu_cpu.sdc,SDC,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_bht_ram.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_b.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_mult_cell.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_nios2_waves.do,OTHER,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_bht_ram.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_a.mif,MIF,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_debug_slave_tck.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_test_bench.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_b.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v,VERILOG,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_a.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_a.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_bht_ram.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_rf_ram_b.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.dat,DAT,,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.hex,HEX,,q_sys_cpu_cpu,false
+simulation/submodules/mentor/altera_nios2_gen2_rtl_module.sv,SYSTEM_VERILOG,MENTOR_SPECIFIC,q_sys_cpu_cpu,false
+simulation/submodules/cadence/altera_nios2_gen2_rtl_module.sv,SYSTEM_VERILOG,CADENCE_SPECIFIC,q_sys_cpu_cpu,false
+simulation/submodules/aldec/altera_nios2_gen2_rtl_module.sv,SYSTEM_VERILOG,ALDEC_SPECIFIC,q_sys_cpu_cpu,false
+simulation/submodules/synopsys/altera_nios2_gen2_rtl_module.sv,SYSTEM_VERILOG,SYNOPSYS_SPECIFIC,q_sys_cpu_cpu,false
+simulation/submodules/q_sys_ddr3_ram_pll0.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_pll0,false
+simulation/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_reset_m10.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_reset_sync.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/max10emif_dcfifo.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_iss_probe.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0_flop_mem.v,VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/q_sys_ddr3_ram_p0.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/altera_gpio_lite.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_p0,false
+simulation/submodules/afi_mux_ddr3_ddrx.v,VERILOG,,afi_mux_ddr3_ddrx,false
+simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c,OTHER,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h,OTHER,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h,OTHER,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl,OTHER,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/sequencer_pll_mgr.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/sequencer_phy_mgr.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_write_decoder.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_pattern_fifo.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_inst_ROM_reg.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_ddr3.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/sequencer_m10.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_ram.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_di_buffer.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_generic.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_ram_csr.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_ac_ROM_reg.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_data_broadcast.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_dm_decoder.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_jumplogic.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_core.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_lfsr12.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_lfsr72.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_datamux.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_mem_if_sequencer_rst.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_data_decoder.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_lfsr36.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_read_datapath.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_bitcheck.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_di_buffer_wrap.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex,HEX,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex,HEX,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_m10_ac_ROM.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/rw_manager_m10_inst_ROM.v,VERILOG,,q_sys_ddr3_ram_s0,false
+simulation/submodules/q_sys_ddr3_ram_c0.v,VERILOG,,q_sys_ddr3_ram_c0,false
+simulation/submodules/mentor/altera_eth_tse_mac.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_eth_tse_mac.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_eth_tse_mac.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_eth_tse_mac.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_clk_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_clk_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_clk_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_clk_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_crc328checker.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_crc328checker.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_crc328checker.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_crc328checker.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_crc328generator.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_crc328generator.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_crc328generator.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_crc328generator.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_crc32ctl8.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_crc32ctl8.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_crc32ctl8.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_crc32ctl8.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_crc32galois8.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_crc32galois8.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_crc32galois8.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_crc32galois8.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_gmii_io.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_gmii_io.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_gmii_io.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_gmii_io.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_lb_read_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_lb_read_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_lb_read_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_lb_read_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_lb_wrt_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_lb_wrt_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_lb_wrt_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_lb_wrt_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_hashing.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_hashing.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_hashing.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_hashing.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_host_control.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_host_control.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_host_control.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_host_control.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_host_control_small.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_host_control_small.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_host_control_small.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_host_control_small.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mac_control.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mac_control.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mac_control.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mac_control.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_register_map.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_register_map.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_register_map.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_register_map.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_register_map_small.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_register_map_small.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_register_map_small.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_register_map_small.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_counter_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_counter_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_counter_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_counter_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_shared_mac_control.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_shared_mac_control.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_shared_mac_control.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_shared_mac_control.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_shared_register_map.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_shared_register_map.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_shared_register_map.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_shared_register_map.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_counter_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_counter_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_counter_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_counter_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_lfsr_10.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_lfsr_10.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_lfsr_10.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_lfsr_10.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_loopback_ff.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_loopback_ff.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_loopback_ff.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_loopback_ff.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_altshifttaps.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_altshifttaps.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_altshifttaps.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_altshifttaps.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_fifoless_mac_rx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_fifoless_mac_rx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_fifoless_mac_rx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_fifoless_mac_rx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mac_rx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mac_rx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mac_rx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mac_rx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_fifoless_mac_tx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_fifoless_mac_tx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_fifoless_mac_tx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_fifoless_mac_tx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mac_tx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mac_tx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mac_tx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mac_tx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_magic_detection.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_magic_detection.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_magic_detection.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_magic_detection.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mdio.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mdio.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mdio.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mdio.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mdio_clk_gen.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mdio_clk_gen.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mdio_clk_gen.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mdio_clk_gen.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mdio_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mdio_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mdio_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mdio_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_mdio.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_mdio.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_mdio.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_mdio.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mii_rx_if.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mii_rx_if.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mii_rx_if.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mii_rx_if.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_mii_tx_if.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_mii_tx_if.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_mii_tx_if.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_mii_tx_if.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_pipeline_base.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_pipeline_base.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_pipeline_base.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_pipeline_base.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_pipeline_stage.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_pipeline_stage.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_pipeline_stage.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_pipeline_stage.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_dpram_16x32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_dpram_16x32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_dpram_16x32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_dpram_16x32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_dpram_8x32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_dpram_8x32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_dpram_8x32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_dpram_8x32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_dpram_ecc_16x32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_dpram_ecc_16x32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_dpram_ecc_16x32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_dpram_ecc_16x32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_fifoless_retransmit_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_fifoless_retransmit_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_fifoless_retransmit_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_fifoless_retransmit_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_retransmit_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_retransmit_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_retransmit_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_retransmit_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rgmii_in1.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rgmii_in1.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rgmii_in1.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rgmii_in1.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rgmii_in4.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rgmii_in4.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rgmii_in4.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rgmii_in4.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_nf_rgmii_module.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_nf_rgmii_module.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_nf_rgmii_module.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_nf_rgmii_module.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rgmii_module.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rgmii_module.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rgmii_module.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rgmii_module.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rgmii_out1.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rgmii_out1.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rgmii_out1.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rgmii_out1.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rgmii_out4.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rgmii_out4.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rgmii_out4.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rgmii_out4.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_ff.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_ff.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_ff.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_ff.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_min_ff.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_min_ff.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_min_ff.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_min_ff.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_ff_cntrl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_ff_cntrl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_ff_cntrl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_ff_cntrl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_ff_length.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_ff_length.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_ff_length.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_ff_length.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_rx_stat_extract.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_rx_stat_extract.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_rx_stat_extract.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_rx_stat_extract.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_timing_adapter32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_timing_adapter32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_timing_adapter32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_timing_adapter32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_timing_adapter8.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_timing_adapter8.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_timing_adapter8.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_timing_adapter8.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_timing_adapter_fifo32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_timing_adapter_fifo32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_timing_adapter_fifo32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_timing_adapter_fifo32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_timing_adapter_fifo8.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_timing_adapter_fifo8.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_timing_adapter_fifo8.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_timing_adapter_fifo8.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_1geth.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_1geth.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_1geth.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_1geth.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_fifoless_1geth.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_fifoless_1geth.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_fifoless_1geth.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_fifoless_1geth.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_w_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_w_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_w_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_w_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_w_fifo_10_100_1000.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_w_fifo_10_100_1000.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_w_fifo_10_100_1000.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_w_fifo_10_100_1000.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_wo_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_wo_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_wo_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_wo_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_wo_fifo_10_100_1000.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_wo_fifo_10_100_1000.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_wo_fifo_10_100_1000.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_wo_fifo_10_100_1000.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_top_gen_host.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_top_gen_host.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_top_gen_host.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_top_gen_host.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_min_ff.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_min_ff.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_min_ff.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_min_ff.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff_cntrl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff_cntrl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff_cntrl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff_cntrl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32_shift16.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff_length.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff_length.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff_length.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff_length.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_ff_read_cntl.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_ff_read_cntl.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_ff_read_cntl.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_ff_read_cntl.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_tx_stat_extract.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_tx_stat_extract.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_tx_stat_extract.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_tx_stat_extract.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_eth_tse_std_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_eth_tse_std_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_eth_tse_std_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_eth_tse_std_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_eth_tse_std_synchronizer_bundle.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_eth_tse_std_synchronizer_bundle.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_eth_tse_std_synchronizer_bundle.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_eth_tse_std_synchronizer_bundle.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_eth_tse_ptp_std_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_eth_tse_ptp_std_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_eth_tse_ptp_std_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_eth_tse_ptp_std_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_false_path_marker.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_false_path_marker.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_false_path_marker.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_false_path_marker.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_reset_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_reset_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_reset_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_reset_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_clock_crosser.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_clock_crosser.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_clock_crosser.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_clock_crosser.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_13.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_13.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_13.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_13.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_24.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_24.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_24.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_24.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_34.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_34.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_34.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_34.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_opt_1246.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_opt_1246.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_opt_1246.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_opt_1246.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_opt_14_44.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_opt_14_44.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_opt_14_44.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_opt_14_44.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_a_fifo_opt_36_10.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_a_fifo_opt_36_10.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_a_fifo_opt_36_10.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_a_fifo_opt_36_10.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_gray_cnt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_gray_cnt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_gray_cnt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_gray_cnt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_sdpm_altsyncram.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_sdpm_altsyncram.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_sdpm_altsyncram.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_sdpm_altsyncram.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_altsyncram_dpm_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_altsyncram_dpm_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_altsyncram_dpm_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_altsyncram_dpm_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_bin_cnt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_bin_cnt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_bin_cnt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_bin_cnt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_sdpm_gen.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_sdpm_gen.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_sdpm_gen.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_sdpm_gen.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x10.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x10.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x10.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x10.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x10.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x10.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x10.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x10.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x10_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x10_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x10_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x10_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x14.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x14.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x14.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x14.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x14.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x14.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x14.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x14.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x14_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x14_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x14_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x14_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x2.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x2.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x2.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x2.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x2.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x2.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x2.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x2.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x2_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x2_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x2_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x2_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x23.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x23.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x23.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x23.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x23.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x23.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x23.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x23.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x23_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x23_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x23_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x23_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x36.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x36.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x36.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x36.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x36.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x36.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x36.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x36.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x36_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x36_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x36_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x36_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x40.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x40.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x40.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x40.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x40.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x40.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x40.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x40.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x40_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x40_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x40_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x40_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_dec_x30.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_dec_x30.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_dec_x30.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_dec_x30.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x30.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x30.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x30.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x30.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_enc_x30_wrapper.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_enc_x30_wrapper.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_enc_x30_wrapper.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_enc_x30_wrapper.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/mentor/altera_tse_ecc_status_crosser.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/aldec/altera_tse_ecc_status_crosser.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/synopsys/altera_tse_ecc_status_crosser.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/cadence/altera_tse_ecc_status_crosser.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_eth_tse_mac,false
+simulation/submodules/altera_std_synchronizer_nocut.v,VERILOG,,altera_eth_tse_mac,false
+simulation/submodules/altera_gpio_lite.sv,SYSTEM_VERILOG,,altera_gpio_lite,false
+simulation/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v,VERILOG,,q_sys_ext_flash_soft_asmiblock_instance_name,false
+simulation/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v,VERILOG,,q_sys_ext_flash_asmi_parallel_instance_name,false
+simulation/submodules/q_sys_ext_flash_epcq_controller_instance_name.v,VERILOG,,q_sys_ext_flash_epcq_controller_instance_name,false
+simulation/submodules/dispatcher.v,VERILOG,,dispatcher,false
+simulation/submodules/descriptor_buffers.v,VERILOG,,dispatcher,false
+simulation/submodules/csr_block.v,VERILOG,,dispatcher,false
+simulation/submodules/response_block.v,VERILOG,,dispatcher,false
+simulation/submodules/fifo_with_byteenables.v,VERILOG,,dispatcher,false
+simulation/submodules/read_signal_breakout.v,VERILOG,,dispatcher,false
+simulation/submodules/write_signal_breakout.v,VERILOG,,dispatcher,false
+simulation/submodules/altera_msgdma_prefetcher.v,VERILOG,TOP_LEVEL_FILE,altera_msgdma_prefetcher,false
+simulation/submodules/altera_msgdma_prefetcher_read.v,VERILOG,,altera_msgdma_prefetcher,false
+simulation/submodules/altera_msgdma_prefetcher_write_back.v,VERILOG,,altera_msgdma_prefetcher,false
+simulation/submodules/altera_msgdma_prefetcher_fifo.v,VERILOG,,altera_msgdma_prefetcher,false
+simulation/submodules/altera_msgdma_prefetcher_interrrupt.v,VERILOG,,altera_msgdma_prefetcher,false
+simulation/submodules/altera_msgdma_prefetcher_csr.v,VERILOG,,altera_msgdma_prefetcher,false
+simulation/submodules/write_master.v,VERILOG,,write_master,false
+simulation/submodules/byte_enable_generator.v,VERILOG,,write_master,false
+simulation/submodules/ST_to_MM_Adapter.v,VERILOG,,write_master,false
+simulation/submodules/write_burst_control.v,VERILOG,,write_master,false
+simulation/submodules/read_master.v,VERILOG,,read_master,false
+simulation/submodules/MM_to_ST_Adapter.v,VERILOG,,read_master,false
+simulation/submodules/read_burst_control.v,VERILOG,,read_master,false
+simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
+simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
+simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
+simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
+simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
+simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
+simulation/submodules/q_sys_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router,false
+simulation/submodules/q_sys_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_001,false
+simulation/submodules/q_sys_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_002,false
+simulation/submodules/q_sys_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_004,false
+simulation/submodules/q_sys_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_008,false
+simulation/submodules/q_sys_mm_interconnect_0_router_009.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_009,false
+simulation/submodules/q_sys_mm_interconnect_0_router_010.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_010,false
+simulation/submodules/q_sys_mm_interconnect_0_router_022.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_router_022,false
+simulation/submodules/altera_merlin_traffic_limiter.sv,SYSTEM_VERILOG,,altera_merlin_traffic_limiter,false
+simulation/submodules/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,altera_merlin_traffic_limiter,false
+simulation/submodules/altera_avalon_sc_fifo.v,SYSTEM_VERILOG,,altera_merlin_traffic_limiter,false
+simulation/submodules/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,altera_merlin_traffic_limiter,false
+simulation/submodules/altera_merlin_burst_adapter.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_default_burst_converter.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_avalon_st_pipeline_stage.sv,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,altera_merlin_burst_adapter,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_demux,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_demux_001,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_demux_002,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_001,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_001,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_002,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_002,false
+simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_014,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_cmd_mux_014,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_demux,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_demux_001,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_demux_002,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_demux_010,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_demux_014,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux_001,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux_001,false
+simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux_002,false
+simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_rsp_mux_002,false
+simulation/submodules/altera_avalon_st_handshake_clock_crosser.v,SYSTEM_VERILOG,,altera_avalon_st_handshake_clock_crosser,false
+simulation/submodules/altera_avalon_st_clock_crosser.v,SYSTEM_VERILOG,,altera_avalon_st_handshake_clock_crosser,false
+simulation/submodules/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,altera_avalon_st_handshake_clock_crosser,false
+simulation/submodules/altera_std_synchronizer_nocut.v,SYSTEM_VERILOG,,altera_avalon_st_handshake_clock_crosser,false
+simulation/submodules/altera_avalon_st_handshake_clock_crosser.sdc,SDC,,altera_avalon_st_handshake_clock_crosser,false
+simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,q_sys_mm_interconnect_0_avalon_st_adapter,false
+simulation/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,q_sys_avalon_st_adapter_error_adapter_0,false
+simulation/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv,SYSTEM_VERILOG,,q_sys_avalon_st_adapter_001_timing_adapter_0,false
+simulation/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv,SYSTEM_VERILOG,,q_sys_avalon_st_adapter_001_timing_adapter_0,false
+simulation/submodules/alt_mem_ddrx_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_addr_cmd_wrap.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ddr2_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ddr3_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_rdwr_data_tmg.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_arbiter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_burst_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_cmd_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_csr.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_buffer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_buffer_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_burst_tracking.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_dataid_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_fifo.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_list.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_rdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_wdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_define.iv,VERILOG_INCLUDE,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_decoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_encoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_axi_st_converter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_input_if.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_rank_timer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_sideband.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_tbp.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_timing_param.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_controller.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_controller_st_top.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv,SYSTEM_VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
+simulation/submodules/alt_mem_ddrx_mm_st_converter.v,VERILOG,,alt_mem_ddrx_mm_st_converter,false
+simulation/submodules/soft_asmiblock.sv,SYSTEM_VERILOG,,soft_asmiblock,false
+simulation/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v,VERILOG,,q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name,false
+simulation/submodules/altera_epcq_controller_arb.sv,SYSTEM_VERILOG,TOP_LEVEL_FILE,altera_epcq_controller_arb,false
+simulation/submodules/altera_epcq_controller.sv,SYSTEM_VERILOG,,altera_epcq_controller_arb,false
+simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
+#
+# Map from instance-path to kind of module
+instances:
+instancePath,module
+q_sys.altpll_shift,q_sys_altpll_shift
+q_sys.button_pio,q_sys_button_pio
+q_sys.channel_adapter_0,q_sys_channel_adapter_0
+q_sys.cpu,q_sys_cpu
+q_sys.cpu.cpu,q_sys_cpu_cpu
+q_sys.ddr3_ram,q_sys_ddr3_ram
+q_sys.ddr3_ram.pll0,q_sys_ddr3_ram_pll0
+q_sys.ddr3_ram.p0,q_sys_ddr3_ram_p0
+q_sys.ddr3_ram.m0,afi_mux_ddr3_ddrx
+q_sys.ddr3_ram.s0,q_sys_ddr3_ram_s0
+q_sys.ddr3_ram.c0,q_sys_ddr3_ram_c0
+q_sys.ddr3_ram.c0.ng0,alt_mem_if_nextgen_ddr3_controller_core
+q_sys.ddr3_ram.c0.a0,alt_mem_ddrx_mm_st_converter
+q_sys.debug_uart,q_sys_debug_uart
+q_sys.descriptor_memory,q_sys_descriptor_memory
+q_sys.enet_pll,q_sys_enet_pll
+q_sys.eth_tse,q_sys_eth_tse
+q_sys.eth_tse.i_tse_mac,altera_eth_tse_mac
+q_sys.eth_tse.rgmii_in4_0,altera_gpio_lite
+q_sys.eth_tse.rgmii_in1_0,altera_gpio_lite
+q_sys.eth_tse.rgmii_out4_0,altera_gpio_lite
+q_sys.eth_tse.rgmii_out1_0,altera_gpio_lite
+q_sys.ext_flash,q_sys_ext_flash
+q_sys.ext_flash.soft_asmiblock_instance_name,q_sys_ext_flash_soft_asmiblock_instance_name
+q_sys.ext_flash.soft_asmiblock_instance_name.soft_asmiblock_instance_name,soft_asmiblock
+q_sys.ext_flash.asmi_parallel_instance_name,q_sys_ext_flash_asmi_parallel_instance_name
+q_sys.ext_flash.asmi_parallel_instance_name.asmi_parallel_instance_name,q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name
+q_sys.ext_flash.epcq_controller_instance_name,q_sys_ext_flash_epcq_controller_instance_name
+q_sys.ext_flash.epcq_controller_instance_name.epcq_controller_instance_name,altera_epcq_controller_arb
+q_sys.frame_timer,q_sys_frame_timer
+q_sys.msgdma_rx,q_sys_msgdma_rx
+q_sys.msgdma_rx.dispatcher_internal,dispatcher
+q_sys.msgdma_rx.prefetcher_internal,altera_msgdma_prefetcher
+q_sys.msgdma_rx.write_mstr_internal,write_master
+q_sys.msgdma_tx,q_sys_msgdma_tx
+q_sys.msgdma_tx.dispatcher_internal,dispatcher
+q_sys.msgdma_tx.prefetcher_internal,altera_msgdma_prefetcher
+q_sys.msgdma_tx.read_mstr_internal,read_master
+q_sys.onchip_flash,altera_onchip_flash
+q_sys.output_pio,q_sys_output_pio
+q_sys.sensor_interface,q_sys_sensor_interface
+q_sys.sys_clk_timer,q_sys_sys_clk_timer
+q_sys.sysid,q_sys_sysid
+q_sys.tx_multiplexer,q_sys_tx_multiplexer
+q_sys.udp_generator,udp_generator
+q_sys.mm_interconnect_0,q_sys_mm_interconnect_0
+q_sys.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_tx_mm_read_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_rx_mm_write_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_tx_descriptor_read_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_rx_descriptor_read_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_tx_descriptor_write_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.msgdma_rx_descriptor_write_master_translator,altera_merlin_master_translator
+q_sys.mm_interconnect_0.ddr3_ram_avl_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.ext_flash_avl_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.ext_flash_avl_mem_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.eth_tse_control_port_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.sysid_control_slave_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.msgdma_tx_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.msgdma_rx_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.onchip_flash_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.udp_generator_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.sensor_interface_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.onchip_flash_data_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.msgdma_tx_prefetcher_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.msgdma_rx_prefetcher_csr_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.descriptor_memory_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.output_pio_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.button_pio_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.debug_uart_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.frame_timer_s1_translator,altera_merlin_slave_translator
+q_sys.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_tx_mm_read_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_rx_mm_write_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_tx_descriptor_read_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_rx_descriptor_read_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_tx_descriptor_write_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.msgdma_rx_descriptor_write_master_agent,altera_merlin_master_agent
+q_sys.mm_interconnect_0.ddr3_ram_avl_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.ext_flash_avl_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.ext_flash_avl_mem_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.eth_tse_control_port_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.sysid_control_slave_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.msgdma_tx_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.msgdma_rx_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.onchip_flash_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.udp_generator_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.sensor_interface_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.onchip_flash_data_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.msgdma_tx_prefetcher_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.msgdma_rx_prefetcher_csr_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.descriptor_memory_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.output_pio_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.button_pio_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.debug_uart_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.frame_timer_s1_agent,altera_merlin_slave_agent
+q_sys.mm_interconnect_0.ddr3_ram_avl_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.ddr3_ram_avl_agent_rdata_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.ext_flash_avl_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.ext_flash_avl_csr_agent_rdata_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.ext_flash_avl_mem_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.ext_flash_avl_mem_agent_rdata_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.eth_tse_control_port_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.sysid_control_slave_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.msgdma_tx_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.msgdma_rx_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.onchip_flash_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.udp_generator_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.sensor_interface_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.onchip_flash_data_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.msgdma_tx_prefetcher_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.msgdma_rx_prefetcher_csr_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.descriptor_memory_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.output_pio_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.button_pio_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.debug_uart_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.frame_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
+q_sys.mm_interconnect_0.router,q_sys_mm_interconnect_0_router
+q_sys.mm_interconnect_0.router_001,q_sys_mm_interconnect_0_router_001
+q_sys.mm_interconnect_0.router_002,q_sys_mm_interconnect_0_router_002
+q_sys.mm_interconnect_0.router_003,q_sys_mm_interconnect_0_router_002
+q_sys.mm_interconnect_0.router_004,q_sys_mm_interconnect_0_router_004
+q_sys.mm_interconnect_0.router_005,q_sys_mm_interconnect_0_router_004
+q_sys.mm_interconnect_0.router_006,q_sys_mm_interconnect_0_router_004
+q_sys.mm_interconnect_0.router_007,q_sys_mm_interconnect_0_router_004
+q_sys.mm_interconnect_0.router_008,q_sys_mm_interconnect_0_router_008
+q_sys.mm_interconnect_0.router_009,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_011,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_012,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_013,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_014,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_015,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_016,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_017,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_020,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_021,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_023,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_024,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_025,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_026,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_027,q_sys_mm_interconnect_0_router_009
+q_sys.mm_interconnect_0.router_010,q_sys_mm_interconnect_0_router_010
+q_sys.mm_interconnect_0.router_018,q_sys_mm_interconnect_0_router_010
+q_sys.mm_interconnect_0.router_019,q_sys_mm_interconnect_0_router_010
+q_sys.mm_interconnect_0.router_022,q_sys_mm_interconnect_0_router_022
+q_sys.mm_interconnect_0.cpu_data_master_limiter,altera_merlin_traffic_limiter
+q_sys.mm_interconnect_0.cpu_instruction_master_limiter,altera_merlin_traffic_limiter
+q_sys.mm_interconnect_0.ext_flash_avl_mem_burst_adapter,altera_merlin_burst_adapter
+q_sys.mm_interconnect_0.cmd_demux,q_sys_mm_interconnect_0_cmd_demux
+q_sys.mm_interconnect_0.cmd_demux_001,q_sys_mm_interconnect_0_cmd_demux_001
+q_sys.mm_interconnect_0.cmd_demux_002,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_demux_003,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_demux_004,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_demux_005,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_demux_006,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_demux_007,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_003,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_004,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_005,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_006,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_007,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_008,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_009,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_012,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_013,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_015,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_016,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_017,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_018,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.rsp_demux_019,q_sys_mm_interconnect_0_cmd_demux_002
+q_sys.mm_interconnect_0.cmd_mux,q_sys_mm_interconnect_0_cmd_mux
+q_sys.mm_interconnect_0.cmd_mux_001,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_003,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_004,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_005,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_006,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_007,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_008,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_009,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_012,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_013,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_015,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_016,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_017,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_018,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_019,q_sys_mm_interconnect_0_cmd_mux_001
+q_sys.mm_interconnect_0.cmd_mux_002,q_sys_mm_interconnect_0_cmd_mux_002
+q_sys.mm_interconnect_0.cmd_mux_010,q_sys_mm_interconnect_0_cmd_mux_002
+q_sys.mm_interconnect_0.cmd_mux_011,q_sys_mm_interconnect_0_cmd_mux_002
+q_sys.mm_interconnect_0.cmd_mux_014,q_sys_mm_interconnect_0_cmd_mux_014
+q_sys.mm_interconnect_0.rsp_demux,q_sys_mm_interconnect_0_rsp_demux
+q_sys.mm_interconnect_0.rsp_demux_001,q_sys_mm_interconnect_0_rsp_demux_001
+q_sys.mm_interconnect_0.rsp_demux_002,q_sys_mm_interconnect_0_rsp_demux_002
+q_sys.mm_interconnect_0.rsp_demux_010,q_sys_mm_interconnect_0_rsp_demux_010
+q_sys.mm_interconnect_0.rsp_demux_011,q_sys_mm_interconnect_0_rsp_demux_010
+q_sys.mm_interconnect_0.rsp_demux_014,q_sys_mm_interconnect_0_rsp_demux_014
+q_sys.mm_interconnect_0.rsp_mux,q_sys_mm_interconnect_0_rsp_mux
+q_sys.mm_interconnect_0.rsp_mux_001,q_sys_mm_interconnect_0_rsp_mux_001
+q_sys.mm_interconnect_0.rsp_mux_002,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.rsp_mux_003,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.rsp_mux_004,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.rsp_mux_005,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.rsp_mux_006,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.rsp_mux_007,q_sys_mm_interconnect_0_rsp_mux_002
+q_sys.mm_interconnect_0.crosser,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_001,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_002,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_003,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_004,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_005,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_006,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_007,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_008,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_009,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_010,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_011,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_012,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.crosser_013,altera_avalon_st_handshake_clock_crosser
+q_sys.mm_interconnect_0.avalon_st_adapter,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_001,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_002,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_003,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_004,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_005,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_006,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_007,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_007.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_008,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_008.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_009,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_009.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_010,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_010.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_011,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_011.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_012,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_012.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_013,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_013.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_014,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_014.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_015,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_015.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_016,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_016.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_017,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_017.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_018,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_018.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.mm_interconnect_0.avalon_st_adapter_019,q_sys_mm_interconnect_0_avalon_st_adapter
+q_sys.mm_interconnect_0.avalon_st_adapter_019.error_adapter_0,q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+q_sys.irq_mapper,q_sys_irq_mapper
+q_sys.irq_synchronizer,altera_irq_clock_crosser
+q_sys.avalon_st_adapter,q_sys_avalon_st_adapter
+q_sys.avalon_st_adapter.error_adapter_0,q_sys_avalon_st_adapter_error_adapter_0
+q_sys.avalon_st_adapter_001,q_sys_avalon_st_adapter_001
+q_sys.avalon_st_adapter_001.timing_adapter_0,q_sys_avalon_st_adapter_001_timing_adapter_0
+q_sys.rst_controller,altera_reset_controller
+q_sys.rst_controller_001,altera_reset_controller
+q_sys.rst_controller_002,altera_reset_controller
+q_sys.rst_controller_003,altera_reset_controller
+q_sys.rst_controller_004,altera_reset_controller
+q_sys.rst_controller_005,altera_reset_controller
+q_sys.rst_controller_006,altera_reset_controller
diff --git a/FPGA_firmware/q_sys/q_sys.spd b/FPGA_firmware/q_sys/q_sys.spd
new file mode 100644
index 0000000..e940927
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys.spd
@@ -0,0 +1,3346 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="error_adapter_0" />
+ <file
+   path="simulation/submodules/altera_epcq_controller_arb.sv"
+   type="SYSTEM_VERILOG"
+   library="epcq_controller_instance_name" />
+ <file
+   path="simulation/submodules/altera_epcq_controller.sv"
+   type="SYSTEM_VERILOG"
+   library="epcq_controller_instance_name" />
+ <file
+   path="simulation/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
+   type="VERILOG"
+   library="asmi_parallel_instance_name" />
+ <file
+   path="simulation/submodules/soft_asmiblock.sv"
+   type="SYSTEM_VERILOG"
+   library="soft_asmiblock_instance_name" />
+ <file
+   path="simulation/submodules/alt_mem_ddrx_mm_st_converter.v"
+   type="VERILOG"
+   library="a0" />
+ <file
+   path="simulation/submodules/alt_mem_ddrx_addr_cmd.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_odt_gen.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_arbiter.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_burst_gen.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_cmd_gen.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_csr.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_buffer.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_buffer_manager.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_burst_tracking.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_dataid_manager.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_fifo.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_list.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_rdata_path.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_wdata_path.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_decoder.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_encoder.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_axi_st_converter.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_input_if.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_rank_timer.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_sideband.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_tbp.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_timing_param.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_controller.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_ddrx_controller_st_top.v"
+   type="VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
+   type="SYSTEM_VERILOG"
+   library="ng0">
+  <include path="simulation/submodules/alt_mem_ddrx_define.iv" />
+ </file>
+ <file
+   path="simulation/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="timing_adapter_0" />
+ <file
+   path="simulation/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
+   type="SYSTEM_VERILOG"
+   library="timing_adapter_0" />
+ <file
+   path="simulation/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="error_adapter_0" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v"
+   type="VERILOG"
+   library="avalon_st_adapter" />
+ <file
+   path="simulation/submodules/altera_avalon_st_handshake_clock_crosser.v"
+   type="SYSTEM_VERILOG"
+   library="crosser" />
+ <file
+   path="simulation/submodules/altera_avalon_st_clock_crosser.v"
+   type="SYSTEM_VERILOG"
+   library="crosser" />
+ <file
+   path="simulation/submodules/altera_avalon_st_pipeline_base.v"
+   type="SYSTEM_VERILOG"
+   library="crosser" />
+ <file
+   path="simulation/submodules/altera_std_synchronizer_nocut.v"
+   type="SYSTEM_VERILOG"
+   library="crosser" />
+ <file
+   path="simulation/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
+   type="SDC"
+   library="crosser" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux_002" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux_002" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux_001" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux_001" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux_014" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux_010" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux_002" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux_001" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_rsp_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_014" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_014" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_002" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_002" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_001" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux_001" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_demux_002" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_demux_001" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_cmd_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_demux" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_adapter.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_adapter_uncmpr.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_adapter_13_1.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_adapter_new.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_incr_burst_converter.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_wrap_burst_converter.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_default_burst_converter.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_merlin_address_alignment.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_avalon_st_pipeline_stage.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_avalon_st_pipeline_base.v"
+   type="SYSTEM_VERILOG"
+   library="ext_flash_avl_mem_burst_adapter" />
+ <file
+   path="simulation/submodules/altera_merlin_traffic_limiter.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_limiter" />
+ <file
+   path="simulation/submodules/altera_merlin_reorder_memory.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_limiter" />
+ <file
+   path="simulation/submodules/altera_avalon_sc_fifo.v"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_limiter" />
+ <file
+   path="simulation/submodules/altera_avalon_st_pipeline_base.v"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_limiter" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_022.sv"
+   type="SYSTEM_VERILOG"
+   library="router_022" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_010.sv"
+   type="SYSTEM_VERILOG"
+   library="router_010" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_009.sv"
+   type="SYSTEM_VERILOG"
+   library="router_009" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_008.sv"
+   type="SYSTEM_VERILOG"
+   library="router_008" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_004.sv"
+   type="SYSTEM_VERILOG"
+   library="router_004" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_002.sv"
+   type="SYSTEM_VERILOG"
+   library="router_002" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router_001.sv"
+   type="SYSTEM_VERILOG"
+   library="router_001" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0_router.sv"
+   type="SYSTEM_VERILOG"
+   library="router" />
+ <file
+   path="simulation/submodules/altera_avalon_sc_fifo.v"
+   type="VERILOG"
+   library="ddr3_ram_avl_agent_rsp_fifo" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="ddr3_ram_avl_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_uncompressor.sv"
+   type="SYSTEM_VERILOG"
+   library="ddr3_ram_avl_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_master_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="ddr3_ram_avl_translator" />
+ <file
+   path="simulation/submodules/altera_merlin_master_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu_data_master_translator" />
+ <file
+   path="simulation/submodules/read_master.v"
+   type="VERILOG"
+   library="read_mstr_internal" />
+ <file
+   path="simulation/submodules/MM_to_ST_Adapter.v"
+   type="VERILOG"
+   library="read_mstr_internal" />
+ <file
+   path="simulation/submodules/read_burst_control.v"
+   type="VERILOG"
+   library="read_mstr_internal" />
+ <file
+   path="simulation/submodules/write_master.v"
+   type="VERILOG"
+   library="write_mstr_internal" />
+ <file
+   path="simulation/submodules/byte_enable_generator.v"
+   type="VERILOG"
+   library="write_mstr_internal" />
+ <file
+   path="simulation/submodules/ST_to_MM_Adapter.v"
+   type="VERILOG"
+   library="write_mstr_internal" />
+ <file
+   path="simulation/submodules/write_burst_control.v"
+   type="VERILOG"
+   library="write_mstr_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher_read.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher_write_back.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher_fifo.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher_interrrupt.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/altera_msgdma_prefetcher_csr.v"
+   type="VERILOG"
+   library="prefetcher_internal" />
+ <file
+   path="simulation/submodules/dispatcher.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/descriptor_buffers.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/csr_block.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/response_block.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/fifo_with_byteenables.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/read_signal_breakout.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/write_signal_breakout.v"
+   type="VERILOG"
+   library="dispatcher_internal" />
+ <file
+   path="simulation/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
+   type="VERILOG"
+   library="epcq_controller_instance_name" />
+ <file
+   path="simulation/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
+   type="VERILOG"
+   library="asmi_parallel_instance_name" />
+ <file
+   path="simulation/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
+   type="VERILOG"
+   library="soft_asmiblock_instance_name" />
+ <file
+   path="simulation/submodules/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG"
+   library="rgmii_in4_0" />
+ <file
+   path="simulation/submodules/mentor/altera_eth_tse_mac.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_eth_tse_mac.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_eth_tse_mac.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_eth_tse_mac.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_clk_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_clk_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_clk_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_clk_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_crc328checker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_crc328checker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_crc328checker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_crc328checker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_crc328generator.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_crc328generator.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_crc328generator.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_crc328generator.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_crc32ctl8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_crc32ctl8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_crc32ctl8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_crc32ctl8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_crc32galois8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_crc32galois8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_crc32galois8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_crc32galois8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_gmii_io.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_gmii_io.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_gmii_io.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_gmii_io.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_lb_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_lb_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_lb_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_lb_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_lb_wrt_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_lb_wrt_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_lb_wrt_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_lb_wrt_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_hashing.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_hashing.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_hashing.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_hashing.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_host_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_host_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_host_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_host_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_host_control_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_host_control_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_host_control_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_host_control_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_register_map_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_register_map_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_register_map_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_register_map_small.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_shared_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_shared_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_shared_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_shared_mac_control.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_shared_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_shared_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_shared_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_shared_register_map.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_counter_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_lfsr_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_lfsr_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_lfsr_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_lfsr_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_loopback_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_loopback_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_loopback_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_loopback_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_altshifttaps.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_altshifttaps.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_altshifttaps.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_altshifttaps.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_fifoless_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_fifoless_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_fifoless_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_fifoless_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mac_rx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_fifoless_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_fifoless_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_fifoless_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_fifoless_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mac_tx.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_magic_detection.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_magic_detection.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_magic_detection.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_magic_detection.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mdio_clk_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mdio_clk_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mdio_clk_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mdio_clk_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mdio_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mdio_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mdio_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mdio_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_mdio.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mii_rx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mii_rx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mii_rx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mii_rx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_mii_tx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_mii_tx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_mii_tx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_mii_tx_if.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_pipeline_base.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_pipeline_base.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_pipeline_base.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_pipeline_base.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_pipeline_stage.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_pipeline_stage.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_pipeline_stage.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_pipeline_stage.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_dpram_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_dpram_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_dpram_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_dpram_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_dpram_8x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_dpram_8x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_dpram_8x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_dpram_8x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_dpram_ecc_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_dpram_ecc_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_dpram_ecc_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_dpram_ecc_16x32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_fifoless_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_fifoless_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_fifoless_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_fifoless_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_retransmit_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rgmii_in1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rgmii_in1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rgmii_in1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rgmii_in1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rgmii_in4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rgmii_in4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rgmii_in4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rgmii_in4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_nf_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_nf_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_nf_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_nf_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rgmii_module.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rgmii_out1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rgmii_out1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rgmii_out1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rgmii_out1.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rgmii_out4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rgmii_out4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rgmii_out4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rgmii_out4.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_rx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_rx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_rx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_rx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_timing_adapter32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_timing_adapter32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_timing_adapter32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_timing_adapter32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_timing_adapter8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_timing_adapter8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_timing_adapter8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_timing_adapter8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_timing_adapter_fifo32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_timing_adapter_fifo32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_timing_adapter_fifo32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_timing_adapter_fifo32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_timing_adapter_fifo8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_timing_adapter_fifo8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_timing_adapter_fifo8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_timing_adapter_fifo8.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_fifoless_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_fifoless_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_fifoless_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_fifoless_1geth.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_w_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_w_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_w_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_w_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_w_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_w_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_w_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_w_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_wo_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_wo_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_wo_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_wo_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_wo_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_wo_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_wo_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_wo_fifo_10_100_1000.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_top_gen_host.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_top_gen_host.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_top_gen_host.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_top_gen_host.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_min_ff.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff_cntrl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff_cntrl_32_shift16.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff_length.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_ff_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_ff_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_ff_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_ff_read_cntl.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_tx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_tx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_tx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_tx_stat_extract.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_eth_tse_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_eth_tse_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_eth_tse_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_eth_tse_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_eth_tse_std_synchronizer_bundle.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_eth_tse_std_synchronizer_bundle.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_eth_tse_std_synchronizer_bundle.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_eth_tse_std_synchronizer_bundle.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_eth_tse_ptp_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_eth_tse_ptp_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_eth_tse_ptp_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_eth_tse_ptp_std_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_false_path_marker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_false_path_marker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_false_path_marker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_false_path_marker.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_reset_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_reset_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_reset_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_reset_synchronizer.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_clock_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_clock_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_clock_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_clock_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_13.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_13.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_13.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_13.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_24.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_24.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_24.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_24.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_34.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_34.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_34.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_34.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_opt_1246.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_opt_1246.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_opt_1246.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_opt_1246.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_opt_14_44.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_opt_14_44.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_opt_14_44.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_opt_14_44.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_a_fifo_opt_36_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_a_fifo_opt_36_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_a_fifo_opt_36_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_a_fifo_opt_36_10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_gray_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_gray_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_gray_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_gray_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_sdpm_altsyncram.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_sdpm_altsyncram.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_sdpm_altsyncram.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_sdpm_altsyncram.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_altsyncram_dpm_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_altsyncram_dpm_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_altsyncram_dpm_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_altsyncram_dpm_fifo.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_bin_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_bin_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_bin_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_bin_cnt.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ph_calculator.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ph_calculator.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ph_calculator.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ph_calculator.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_sdpm_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_sdpm_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_sdpm_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_sdpm_gen.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x10.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x10_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x10_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x10_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x10_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x14.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x14_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x14_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x14_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x14_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x2.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x2_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x2_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x2_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x2_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x23.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x23_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x23_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x23_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x23_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x36.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x36_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x36_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x36_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x36_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x40.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x40_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x40_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x40_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x40_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_dec_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_dec_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_dec_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_dec_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x30.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_enc_x30_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_enc_x30_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_enc_x30_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_enc_x30_wrapper.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/mentor/altera_tse_ecc_status_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/aldec/altera_tse_ecc_status_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_tse_ecc_status_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/cadence/altera_tse_ecc_status_crosser.v"
+   type="VERILOG_ENCRYPT"
+   library="i_tse_mac"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/altera_std_synchronizer_nocut.v"
+   type="VERILOG"
+   library="i_tse_mac" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_c0.v"
+   type="VERILOG"
+   library="c0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c"
+   type="OTHER"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h"
+   type="OTHER"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h"
+   type="OTHER"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl"
+   type="OTHER"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/sequencer_pll_mgr.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/sequencer_phy_mgr.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_write_decoder.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_pattern_fifo.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_inst_ROM_reg.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_ddr3.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/sequencer_m10.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_ram.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_di_buffer.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_generic.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_ram_csr.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_master_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_ac_ROM_reg.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_data_broadcast.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_dm_decoder.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_jumplogic.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_core.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_lfsr12.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_lfsr72.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_datamux.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_mem_if_sequencer_rst.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_data_decoder.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_lfsr36.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_uncompressor.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_avalon_sc_fifo.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/altera_merlin_master_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_read_datapath.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_bitcheck.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_di_buffer_wrap.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex"
+   type="HEX"
+   library="s0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex"
+   type="HEX"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_m10_ac_ROM.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/rw_manager_m10_inst_ROM.v"
+   type="VERILOG"
+   library="s0" />
+ <file
+   path="simulation/submodules/afi_mux_ddr3_ddrx.v"
+   type="VERILOG"
+   library="m0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_reset_m10.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_reset_sync.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/max10emif_dcfifo.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_iss_probe.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0_flop_mem.v"
+   type="VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_p0.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG"
+   library="p0" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram_pll0.sv"
+   type="SYSTEM_VERILOG"
+   library="pll0" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu.sdc"
+   type="SDC"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_bht_ram.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_mult_cell.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_nios2_waves.do"
+   type="OTHER"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_bht_ram.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_test_bench.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_dc_tag_ram.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_b.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_a.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_a.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_bht_ram.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_rf_ram_b.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.dat"
+   type="DAT"
+   library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_cpu_cpu_ic_tag_ram.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="simulation/submodules/mentor/altera_nios2_gen2_rtl_module.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu"
+   simulator="modelsim" />
+ <file
+   path="simulation/submodules/cadence/altera_nios2_gen2_rtl_module.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu"
+   simulator="ncsim" />
+ <file
+   path="simulation/submodules/aldec/altera_nios2_gen2_rtl_module.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu"
+   simulator="riviera" />
+ <file
+   path="simulation/submodules/synopsys/altera_nios2_gen2_rtl_module.sv"
+   type="SYSTEM_VERILOG"
+   library="cpu"
+   simulator="vcs" />
+ <file
+   path="simulation/submodules/altera_reset_controller.v"
+   type="VERILOG"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/altera_reset_synchronizer.v"
+   type="VERILOG"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/altera_reset_controller.sdc"
+   type="SDC"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/q_sys_avalon_st_adapter_001.v"
+   type="VERILOG"
+   library="avalon_st_adapter_001" />
+ <file
+   path="simulation/submodules/q_sys_avalon_st_adapter.v"
+   type="VERILOG"
+   library="avalon_st_adapter" />
+ <file
+   path="simulation/submodules/altera_irq_clock_crosser.sv"
+   type="SYSTEM_VERILOG"
+   library="irq_synchronizer" />
+ <file
+   path="simulation/submodules/q_sys_irq_mapper.sv"
+   type="SYSTEM_VERILOG"
+   library="irq_mapper" />
+ <file
+   path="simulation/submodules/q_sys_mm_interconnect_0.v"
+   type="VERILOG"
+   library="mm_interconnect_0" />
+ <file
+   path="simulation/submodules/udp_generator.v"
+   type="VERILOG"
+   library="udp_generator" />
+ <file
+   path="simulation/submodules/q_sys_tx_multiplexer.sv"
+   type="SYSTEM_VERILOG"
+   library="tx_multiplexer" />
+ <file
+   path="simulation/submodules/q_sys_sysid.v"
+   type="VERILOG"
+   library="sysid" />
+ <file
+   path="simulation/submodules/q_sys_sys_clk_timer.v"
+   type="VERILOG"
+   library="sys_clk_timer" />
+ <file
+   path="simulation/submodules/sensor_interface.v"
+   type="VERILOG"
+   library="sensor_interface" />
+ <file
+   path="simulation/submodules/q_sys_output_pio.v"
+   type="VERILOG"
+   library="output_pio" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_util.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_avmm_data_controller.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_avmm_csr_controller.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/q_sys_msgdma_tx.v"
+   type="VERILOG"
+   library="msgdma_tx" />
+ <file
+   path="simulation/submodules/q_sys_msgdma_rx.v"
+   type="VERILOG"
+   library="msgdma_rx" />
+ <file
+   path="simulation/submodules/q_sys_frame_timer.v"
+   type="VERILOG"
+   library="frame_timer" />
+ <file
+   path="simulation/submodules/q_sys_ext_flash.sv"
+   type="SYSTEM_VERILOG"
+   library="ext_flash" />
+ <file
+   path="simulation/submodules/q_sys_eth_tse.v"
+   type="VERILOG"
+   library="eth_tse" />
+ <file
+   path="simulation/submodules/q_sys_enet_pll.vo"
+   type="VERILOG"
+   library="enet_pll" />
+ <file
+   path="simulation/submodules/q_sys_descriptor_memory.v"
+   type="VERILOG"
+   library="descriptor_memory" />
+ <file
+   path="simulation/submodules/q_sys_debug_uart.v"
+   type="VERILOG"
+   library="debug_uart" />
+ <file
+   path="simulation/submodules/q_sys_ddr3_ram.v"
+   type="VERILOG"
+   library="ddr3_ram" />
+ <file path="simulation/submodules/q_sys_cpu.v" type="VERILOG" library="cpu" />
+ <file
+   path="simulation/submodules/q_sys_channel_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="channel_adapter_0" />
+ <file
+   path="simulation/submodules/q_sys_button_pio.v"
+   type="VERILOG"
+   library="button_pio" />
+ <file
+   path="simulation/submodules/q_sys_altpll_shift.vo"
+   type="VERILOG"
+   library="altpll_shift" />
+ <file path="simulation/q_sys.v" type="VERILOG" />
+ <topLevel name="q_sys" />
+ <deviceFamily name="max10" />
+ <modelMap controllerPath="q_sys.ddr3_ram" modelPath="q_sys.ddr3_ram" />
+ <modelMap
+   controllerPath="q_sys.descriptor_memory"
+   modelPath="q_sys.descriptor_memory" />
+ <modelMap controllerPath="q_sys.onchip_flash" modelPath="q_sys.onchip_flash" />
+</simPackage>
diff --git a/FPGA_firmware/q_sys/q_sys.xml b/FPGA_firmware/q_sys/q_sys.xml
new file mode 100644
index 0000000..ec03f53
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys.xml
@@ -0,0 +1,21598 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.10.11.10:10:44"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SYS_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SYS_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SYS_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="altpll_shift_c0" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="250000000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="altpll_shift_c0_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="altpll_shift_locked_conduit" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="altpll_shift_locked_conduit_export"
+       direction="output"
+       role="export"
+       width="1" />
+  </interface>
+  <interface name="button_pio_external_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="button_pio_external_connection_export"
+       direction="input"
+       role="export"
+       width="9" />
+  </interface>
+  <interface name="clock_bridge_0_in_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port
+       name="clock_bridge_0_in_clk_clk"
+       direction="input"
+       role="clk"
+       width="1" />
+  </interface>
+  <interface name="ddr3_ram_pll_ref_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port
+       name="ddr3_ram_pll_ref_clk_clk"
+       direction="input"
+       role="clk"
+       width="1" />
+  </interface>
+  <interface name="debug_uart_external_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="debug_uart_external_connection_rxd"
+       direction="input"
+       role="rxd"
+       width="1" />
+   <port
+       name="debug_uart_external_connection_txd"
+       direction="output"
+       role="txd"
+       width="1" />
+  </interface>
+  <interface name="enet_pll_c0" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="125000000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="enet_pll_c0_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="enet_pll_c1" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="25000000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="enet_pll_c1_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="enet_pll_c2" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="2500000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="enet_pll_c2_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="enet_pll_c3" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="125000000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="enet_pll_c3_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="enet_pll_c4" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="25000000" />
+   <property name="clockRateKnown" value="true" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="enet_pll_c4_clk" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="enet_pll_locked_conduit" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="enet_pll_locked_conduit_export"
+       direction="output"
+       role="export"
+       width="1" />
+  </interface>
+  <interface name="eth_tse_mac_mdio_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="eth_tse_mac_mdio_connection_mdc"
+       direction="output"
+       role="mdc"
+       width="1" />
+   <port
+       name="eth_tse_mac_mdio_connection_mdio_in"
+       direction="input"
+       role="mdio_in"
+       width="1" />
+   <port
+       name="eth_tse_mac_mdio_connection_mdio_out"
+       direction="output"
+       role="mdio_out"
+       width="1" />
+   <port
+       name="eth_tse_mac_mdio_connection_mdio_oen"
+       direction="output"
+       role="mdio_oen"
+       width="1" />
+  </interface>
+  <interface name="eth_tse_mac_rgmii_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="eth_tse_mac_rgmii_connection_rgmii_in"
+       direction="input"
+       role="rgmii_in"
+       width="4" />
+   <port
+       name="eth_tse_mac_rgmii_connection_rgmii_out"
+       direction="output"
+       role="rgmii_out"
+       width="4" />
+   <port
+       name="eth_tse_mac_rgmii_connection_rx_control"
+       direction="input"
+       role="rx_control"
+       width="1" />
+   <port
+       name="eth_tse_mac_rgmii_connection_tx_control"
+       direction="output"
+       role="tx_control"
+       width="1" />
+  </interface>
+  <interface name="eth_tse_mac_status_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="eth_tse_mac_status_connection_set_10"
+       direction="input"
+       role="set_10"
+       width="1" />
+   <port
+       name="eth_tse_mac_status_connection_set_1000"
+       direction="input"
+       role="set_1000"
+       width="1" />
+   <port
+       name="eth_tse_mac_status_connection_eth_mode"
+       direction="output"
+       role="eth_mode"
+       width="1" />
+   <port
+       name="eth_tse_mac_status_connection_ena_10"
+       direction="output"
+       role="ena_10"
+       width="1" />
+  </interface>
+  <interface name="eth_tse_pcs_mac_rx_clock_connection" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port
+       name="eth_tse_pcs_mac_rx_clock_connection_clk"
+       direction="input"
+       role="clk"
+       width="1" />
+  </interface>
+  <interface name="eth_tse_pcs_mac_tx_clock_connection" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port
+       name="eth_tse_pcs_mac_tx_clock_connection_clk"
+       direction="input"
+       role="clk"
+       width="1" />
+  </interface>
+  <interface name="ext_flash_flash_dataout" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="ext_flash_flash_dataout_conduit_dataout"
+       direction="bidir"
+       role="conduit_dataout"
+       width="4" />
+  </interface>
+  <interface name="ext_flash_flash_dclk_out" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="ext_flash_flash_dclk_out_conduit_dclk_out"
+       direction="output"
+       role="conduit_dclk_out"
+       width="1" />
+  </interface>
+  <interface name="ext_flash_flash_ncs" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="ext_flash_flash_ncs_conduit_ncs"
+       direction="output"
+       role="conduit_ncs"
+       width="1" />
+  </interface>
+  <interface name="frame_timer" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="frame_timer_export" direction="output" role="export" width="1" />
+  </interface>
+  <interface name="led_pio_external_connection" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="led_pio_external_connection_export"
+       direction="output"
+       role="export"
+       width="8" />
+  </interface>
+  <interface name="mem_if_ddr3_emif_0_status" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port
+       name="mem_if_ddr3_emif_0_status_local_init_done"
+       direction="output"
+       role="local_init_done"
+       width="1" />
+   <port
+       name="mem_if_ddr3_emif_0_status_local_cal_success"
+       direction="output"
+       role="local_cal_success"
+       width="1" />
+   <port
+       name="mem_if_ddr3_emif_0_status_local_cal_fail"
+       direction="output"
+       role="local_cal_fail"
+       width="1" />
+  </interface>
+  <interface name="mem_resetn_in_reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port
+       name="mem_resetn_in_reset_reset_n"
+       direction="input"
+       role="reset_n"
+       width="1" />
+  </interface>
+  <interface name="memory" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="memory_mem_a" direction="output" role="mem_a" width="14" />
+   <port name="memory_mem_ba" direction="output" role="mem_ba" width="3" />
+   <port name="memory_mem_ck" direction="bidir" role="mem_ck" width="1" />
+   <port name="memory_mem_ck_n" direction="bidir" role="mem_ck_n" width="1" />
+   <port name="memory_mem_cke" direction="output" role="mem_cke" width="1" />
+   <port name="memory_mem_cs_n" direction="output" role="mem_cs_n" width="1" />
+   <port name="memory_mem_dm" direction="output" role="mem_dm" width="1" />
+   <port name="memory_mem_ras_n" direction="output" role="mem_ras_n" width="1" />
+   <port name="memory_mem_cas_n" direction="output" role="mem_cas_n" width="1" />
+   <port name="memory_mem_we_n" direction="output" role="mem_we_n" width="1" />
+   <port
+       name="memory_mem_reset_n"
+       direction="output"
+       role="mem_reset_n"
+       width="1" />
+   <port name="memory_mem_dq" direction="bidir" role="mem_dq" width="8" />
+   <port name="memory_mem_dqs" direction="bidir" role="mem_dqs" width="1" />
+   <port name="memory_mem_dqs_n" direction="bidir" role="mem_dqs_n" width="1" />
+   <port name="memory_mem_odt" direction="output" role="mem_odt" width="1" />
+  </interface>
+  <interface name="reset" kind="reset" start="0">
+   <property name="associatedClock" value="" />
+   <property name="synchronousEdges" value="NONE" />
+   <port name="reset_reset_n" direction="input" role="reset_n" width="1" />
+  </interface>
+  <interface name="sensor" kind="conduit" start="0">
+   <property name="associatedClock" value="sys_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_in_adc_data"
+       direction="input"
+       role="in_adc_data"
+       width="5" />
+   <port name="sensor_in_trg" direction="input" role="in_trg" width="1" />
+   <port
+       name="sensor_out_adc_clk"
+       direction="output"
+       role="out_adc_clk"
+       width="1" />
+   <port
+       name="sensor_out_adc_cnv"
+       direction="output"
+       role="out_adc_cnv"
+       width="1" />
+   <port
+       name="sensor_out_sensor_clk"
+       direction="output"
+       role="out_sensor_clk"
+       width="1" />
+   <port
+       name="sensor_out_sensor_gain"
+       direction="output"
+       role="out_sensor_gain"
+       width="1" />
+   <port
+       name="sensor_out_sensor_rst"
+       direction="output"
+       role="out_sensor_rst"
+       width="1" />
+  </interface>
+  <interface name="sensor_status" kind="conduit" start="0">
+   <property name="associatedClock" value="sys_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_status_status_out"
+       direction="output"
+       role="status_out"
+       width="8" />
+  </interface>
+  <interface name="sensor_synchro" kind="conduit" start="0">
+   <property name="associatedClock" value="sys_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_synchro_ext_input"
+       direction="input"
+       role="ext_input"
+       width="8" />
+   <port
+       name="sensor_synchro_serial_rx"
+       direction="input"
+       role="serial_rx"
+       width="1" />
+   <port
+       name="sensor_synchro_serial_tx"
+       direction="output"
+       role="serial_tx"
+       width="1" />
+  </interface>
+  <interface name="sys_clk" kind="clock" start="0">
+   <property name="clockRate" value="50000000" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="sys_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="q_sys:1.0:AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN=-1,AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE=-1,AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN=-1,AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN=-1,AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE=-1,AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE=-1,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN=-1,AUTO_GENERATION_ID=1728634208,AUTO_SYS_CLK_CLOCK_DOMAIN=-1,AUTO_SYS_CLK_CLOCK_RATE=-1,AUTO_SYS_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=1,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=15000,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=,CLK3_DUTY_CYCLE=,CLK3_MULTIPLY_BY=,CLK3_PHASE_SHIFT=,CLK4_DIVIDE_BY=,CLK4_DUTY_CYCLE=,CLK4_MULTIPLY_BY=,CLK4_PHASE_SHIFT=,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NORMAL,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_USED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_UNUSED,PORT_clk2=PORT_UNUSED,PORT_clk3=PORT_UNUSED,PORT_clk4=PORT_UNUSED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT=)(altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=false,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=true,derived_has_irq=false,derived_has_out=false,derived_has_tri=false,derived_irq_type=NONE,direction=Input,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=9)(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_calibration_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=16,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_calibration_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(channel_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=1,inErrorDescriptor=,inErrorWidth=1,inMaxChannel=1,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outChannelWidth=0,outMaxChannel=1)(altera_nios2_gen2:19.1:AUTO_CLK_CLOCK_DOMAIN=14,AUTO_CLK_RESET_DOMAIN=14,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=3,mul_64_impl=0,mul_shift_choice=0,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=0,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=)(clock:19.1:)(clock:19.1:)(reset:19.1:))(altera_mem_if_ddr3_emif:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=true,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=true,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=100.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,SPEED_GRADE_CACHE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=150000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=300000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_afi_splitter:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:))(altera_mem_if_pll_bridge:19.1:CORE_PERIPHERY_DUAL_CLOCK=false,CUT_NEW_FAMILY_TIMING=true,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DISABLE_CHILD_MESSAGING=true,DUPLICATE_PLL_FOR_PHY_CLK=false,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,NUM_PLL_SHARING_INTERFACES=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PRE_V_SERIES_FAMILY=false,RATE=Half,SEQUENCER_TYPE=NIOS,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,USE_DR_CLK=false)(clock:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0))(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_avalon_uart:19.1:baud=115200,baudError=0.01,clockRate=50000000,dataBits=8,fixedBaud=true,parity=NONE,parityFisrtChar=N,simCharStream=,simInteractiveInputEnable=false,simInteractiveOutputEnable=false,simTrueBaud=false,stopBits=1,syncRegDepth=2,useCtsRts=false,useEopRegister=false,useRelativePathForSimFile=false)(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_descriptor_memory,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_descriptor_memory.hex,derived_is_hardcopy=false,derived_set_addr_width=11,derived_set_addr_width2=11,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=2,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=0,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=2,CLK3_DUTY_CYCLE=50,CLK3_MULTIPLY_BY=5,CLK3_PHASE_SHIFT=-3000,CLK4_DIVIDE_BY=2,CLK4_DUTY_CYCLE=50,CLK4_MULTIPLY_BY=1,CLK4_PHASE_SHIFT=-10000,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NO_COMPENSATION,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_UNUSED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_USED,PORT_clk2=PORT_USED,PORT_clk3=PORT_USED,PORT_clk4=PORT_USED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT=)(altera_eth_tse:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,XCVR_RCFG_JTAG_ENABLE=0,XCVR_SET_CAPABILITY_REG_ENABLE=0,XCVR_SET_CSR_SOFT_LOGIC_ENABLE=0,XCVR_SET_PRBS_SOFT_LOGIC_ENABLE=0,XCVR_SET_USER_IDENTIFIER=0,core_variation=MAC_ONLY,core_version=4865,dev_version=4865,deviceFamily=MAX10,deviceFamilyName=MAX 10,eg_addr=11,eg_fifo=2048,ena_hash=false,enable_alt_reconfig=false,enable_clk_sharing=false,enable_ecc=false,enable_ena=32,enable_gmii_loopback=true,enable_hd_logic=true,enable_lgth_check=true,enable_mac_flow_ctrl=false,enable_mac_vlan=false,enable_magic_detect=true,enable_padding=true,enable_ptp_1step=false,enable_sgmii=true,enable_shift16=true,enable_sup_addr=false,enable_timestamping=false,enable_use_internal_fifo=true,export_pwrdn=false,ext_stat_cnt_ena=false,gbit_only=true,ifGMII=RGMII,ing_addr=11,ing_fifo=2048,isUseMAC=true,isUsePCS=false,max_channels=1,mbit_only=true,mdio_clk_div=40,nf_lvds_iopll_num_channels=4,nf_phyip_rcfg_enable=true,phy_identifier=0,phyip_en_synce_support=false,phyip_pll_base_data_rate=1250 Mbps,phyip_pll_type=CMU,phyip_pma_bonding_mode=x1,reduced_control=false,reduced_interface_ena=true,starting_channel_number=0,stat_cnt_ena=true,synchronizer_depth=3,transceiver_type=NONE,tstamp_fp_width=4,useMDIO=true,use_mac_clken=false,use_misc_ports=true(altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=Micron512,IO_MODE=QUAD,UNIQUE_ID=q_sys_ext_flash,clkFreq=0,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1(altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD))(altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None)))(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=4999,mult=2.0E-8,period=5000,periodUnits=CLOCKS,periodUnitsString=clocks,resetOutput=false,slave_address_width=3,snapshot=false,systemFrequency=50000000,ticksPerSec=10000.0,timeoutPulseOutput=true,timerPreset=CUSTOM,valueInSecond=0.0,watchdogPulse=2)(altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = -1,AUTO_MM_WRITE_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = 28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=6,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:))(altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = 28,AUTO_MM_WRITE_ADDRESS_MAP=,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = -1,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=1,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:))(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=360447,ADDR_RANGE1_OFFSET=2048,ADDR_RANGE2_END_ADDR=360447,ADDR_RANGE2_OFFSET=0,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=50000000,AVMM_DATA_ADDR_WIDTH=19,AVMM_DATA_BURSTCOUNT_WIDTH=4,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=50.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=50,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=60,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=17500000,FLASH_READ_CYCLE_MAX_INDEX=5,FLASH_RESET_CYCLE_MAX_INDEX=12,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=15250,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=114687,MAX_VALID_ADDR=360447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M50DAF484C6GES,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=8,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=8191,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=16383,SECTOR2_MAP=2,SECTOR2_START_ADDR=8192,SECTOR3_END_ADDR=114687,SECTOR3_MAP=3,SECTOR3_START_ADDR=16384,SECTOR4_END_ADDR=188415,SECTOR4_MAP=4,SECTOR4_START_ADDR=114688,SECTOR5_END_ADDR=360447,SECTOR5_MAP=5,SECTOR5_START_ADDR=188416,SECTOR_ACCESS_MODE=Read and write,Read and write,Read and write,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff,SECTOR_ID=1,2,3,4,5,SECTOR_READ_PROTECTION_MODE=0,SECTOR_STORAGE_TYPE=UFM,UFM,UFM,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=q_sys_onchip_flash,initFlashContent=false,initializationFileName=D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)(altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=true,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=false,derived_has_irq=false,derived_has_out=true,derived_has_tri=false,derived_irq_type=NONE,direction=Output,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=8)(sensor_recon:1:)(clock_source:19.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=499999,mult=0.001,period=10,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=100.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2)(altera_avalon_sysid_qsys:19.1:id=-87110914,timestamp=1728634208)(multiplexer:19.1:bitsPerSymbol=8,errorWidth=1,inErrorWidth=1,inUseEmpty=false,inUseEmptyPort=AUTO,inUsePackets=true,numInputInterfaces=2,outChannelWidth=1,packetScheduling=true,schedulingSize=512,symbolsPerBeat=4,useHighBitsOfChannel=true,usePackets=true)(udp_generator:1.0:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d20,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x14000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d68,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d00,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403ce0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d60,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403cc0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d50,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18200000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18402800,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403ca0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c80,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c60,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c40,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d40,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c20,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c00,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403400,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x14000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18200000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18402800,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(interrupt:19.1:irqNumber=2)(interrupt:19.1:irqNumber=3)(interrupt:19.1:irqNumber=5)(interrupt:19.1:irqNumber=0)(interrupt:19.1:irqNumber=4)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys"
+   kind="q_sys"
+   version="1.0"
+   name="q_sys">
+  <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1728634208" />
+  <parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN"
+     value="-1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN"
+     value="-1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN"
+     value="-1" />
+  <parameter
+     name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN"
+     value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="-1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/q_sys.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_altpll_shift.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_button_pio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_calibration_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/max10emif_dcfifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing_core.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_map.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_assignments.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_parameters.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_datamux.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_bitcheck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_broadcast.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_write_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_dm_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_read_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_pll_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_phy_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_generic.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr12.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_jumplogic.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr72.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ddr3.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_list.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv"
+       type="VERILOG_INCLUDE"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_debug_uart.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_descriptor_memory.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_enet_pll.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_eth_tse.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clk_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328checker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32galois8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gmii_io.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_hashing.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lfsr_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_loopback_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altshifttaps.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_magic_detection.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_base.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_gen_host.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_false_path_marker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clock_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gray_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_bin_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
+       type="SYSTEM_VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_frame_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_rx.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/byte_enable_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ST_to_MM_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_tx.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/MM_to_ST_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_util.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_output_pio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/div.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sqrt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ram4bkg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sysid.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/udp_generator.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_incr_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_default_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_irq_mapper.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.sdc"
+       type="SDC"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_interfaces/alt_mem_if_ddr3_emif/alt_mem_if_ddr3_emif_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_pll/altera_mem_if_ddr3_pll/altera_mem_if_ddr3_pll_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_phy_core/altera_mem_if_ddr3_phy_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_mux/altera_mem_if_ddr3_afi_mux_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_qseq/altera_mem_if_ddr3_qseq/altera_mem_if_ddr3_qseq_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller/alt_mem_if_nextgen_ddr3_controller_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/altera_eth_tse/altera_eth_tse_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_gpio_lite/altera_gpio_lite_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/generic_qspi_controller_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/sensor_algo_qsys/sensor_recon_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_multiplexer/avalon-st_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/udp_generator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_clock_crosser/altera_irq_clock_crosser_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 0 starting:q_sys "q_sys"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>24</b> modules, <b>97</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Info">Interconnect is inserted between master sensor_interface.calibration_ram_interface and slave calibration_ram.s2 because the master has read signal 1 bit wide, but the slave is 0 bit wide.</message>
+   <message level="Info">Interconnect is inserted between master sensor_interface.calibration_ram_interface and slave calibration_ram.s2 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>3</b> modules, <b>5</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces sensor_interface.calibration_ram_interface and sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0 and calibration_ram_s2_translator.avalon_universal_slave_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces calibration_ram_s2_translator.avalon_anti_slave_0 and calibration_ram.s2</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>7</b> modules, <b>17</b> connections]]></message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>25</b> modules, <b>100</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>20</b> modules, <b>71</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>49</b> modules, <b>166</b> connections]]></message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx.mm_read and msgdma_tx_mm_read_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx.mm_write and msgdma_rx_mm_write_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx.descriptor_read_master and msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx.descriptor_read_master and msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx.descriptor_write_master and msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx.descriptor_write_master and msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces ddr3_ram_avl_translator.avalon_anti_slave_0 and ddr3_ram.avl</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_csr_translator.avalon_anti_slave_0 and ext_flash.avl_csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_mem_translator.avalon_anti_slave_0 and ext_flash.avl_mem</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces eth_tse_control_port_translator.avalon_anti_slave_0 and eth_tse.control_port</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx_csr_translator.avalon_anti_slave_0 and msgdma_tx.csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx_csr_translator.avalon_anti_slave_0 and msgdma_rx.csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces onchip_flash_csr_translator.avalon_anti_slave_0 and onchip_flash.csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces udp_generator_csr_translator.avalon_anti_slave_0 and udp_generator.csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces sensor_interface_csr_translator.avalon_anti_slave_0 and sensor_interface.csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces onchip_flash_data_translator.avalon_anti_slave_0 and onchip_flash.data</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_tx.prefetcher_csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_rx.prefetcher_csr</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces descriptor_memory_s1_translator.avalon_anti_slave_0 and descriptor_memory.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces output_pio_s1_translator.avalon_anti_slave_0 and output_pio.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces button_pio_s1_translator.avalon_anti_slave_0 and button_pio.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces debug_uart_s1_translator.avalon_anti_slave_0 and debug_uart.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces frame_timer_s1_translator.avalon_anti_slave_0 and frame_timer.s1</message>
+   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces calibration_ram_s1_translator.avalon_anti_slave_0 and calibration_ram.s1</message>
+   <message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>103</b> modules, <b>479</b> connections]]></message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>132</b> modules, <b>574</b> connections]]></message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_traffic_limiter_transform"><![CDATA[After transform: <b>134</b> modules, <b>582</b> connections]]></message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_burst_transform"><![CDATA[After transform: <b>136</b> modules, <b>589</b> connections]]></message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>193</b> modules, <b>717</b> connections]]></message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_width_transform"><![CDATA[After transform: <b>195</b> modules, <b>723</b> connections]]></message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux_001.src0 and cmd_mux.sink1</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux_001.src1 and cmd_mux_002.sink1</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux_002.src0 and cmd_mux.sink2</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between cmd_demux_003.src0 and cmd_mux.sink3</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux.src1 and rsp_mux_001.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux.src2 and rsp_mux_002.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux.src3 and rsp_mux_003.sink0</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info">Inserting clock-crossing logic between rsp_demux_002.src1 and rsp_mux_001.sink1</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message
+       level="Debug"
+       culprit="com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform"><![CDATA[After transform: <b>209</b> modules, <b>807</b> connections]]></message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug" culprit="limiter_update_transform"><![CDATA[After transform: <b>209</b> modules, <b>809</b> connections]]></message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>217</b> modules, <b>1037</b> connections]]></message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>26</b> modules, <b>110</b> connections]]></message>
+   <message level="Debug" culprit="merlin_mm_transform"><![CDATA[After transform: <b>26</b> modules, <b>110</b> connections]]></message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_interrupt_mapper_transform"><![CDATA[After transform: <b>27</b> modules, <b>113</b> connections]]></message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="merlin_interrupt_sync_transform"><![CDATA[After transform: <b>28</b> modules, <b>119</b> connections]]></message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.017s/0.022s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_001">Inserting timing_adapter: timing_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.timing_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.012s/0.021s</message>
+   <message
+       level="Debug"
+       culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>30</b> modules, <b>126</b> connections]]></message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>39</b> modules, <b>154</b> connections]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altpll</b> "<b>submodules/q_sys_altpll_shift</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_pio</b> "<b>submodules/q_sys_button_pio</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/q_sys_calibration_ram</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>channel_adapter</b> "<b>submodules/q_sys_channel_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_nios2_gen2</b> "<b>submodules/q_sys_cpu</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mem_if_ddr3_emif</b> "<b>submodules/q_sys_ddr3_ram</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_uart</b> "<b>submodules/q_sys_debug_uart</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/q_sys_descriptor_memory</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altpll</b> "<b>submodules/q_sys_enet_pll</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_eth_tse</b> "<b>submodules/q_sys_eth_tse</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_timer</b> "<b>submodules/q_sys_frame_timer</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_msgdma</b> "<b>submodules/q_sys_msgdma_rx</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_msgdma</b> "<b>submodules/q_sys_msgdma_tx</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_onchip_flash</b> "<b>submodules/altera_onchip_flash</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_pio</b> "<b>submodules/q_sys_output_pio</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>sensor_recon</b> "<b>submodules/sensor_algo</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_timer</b> "<b>submodules/q_sys_sys_clk_timer</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_sysid_qsys</b> "<b>submodules/q_sys_sysid</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>multiplexer</b> "<b>submodules/q_sys_tx_multiplexer</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>udp_generator</b> "<b>submodules/udp_generator</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/q_sys_mm_interconnect_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/q_sys_mm_interconnect_1</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_irq_mapper</b> "<b>submodules/q_sys_irq_mapper</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_irq_clock_crosser</b> "<b>submodules/altera_irq_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altpll "submodules/q_sys_altpll_shift"</message>
+   <message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
+   <message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
+   <message level="Debug">Command took 1.307s</message>
+   <message level="Info" culprit="altpll_shift"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>altpll_shift</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio"</message>
+   <message level="Info" culprit="button_pio">Starting RTL generation for module 'q_sys_button_pio'</message>
+   <message level="Info" culprit="button_pio">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="button_pio">Done RTL generation for module 'q_sys_button_pio'</message>
+   <message level="Info" culprit="button_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram"</message>
+   <message level="Info" culprit="calibration_ram">Starting RTL generation for module 'q_sys_calibration_ram'</message>
+   <message level="Info" culprit="calibration_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="calibration_ram">Done RTL generation for module 'q_sys_calibration_ram'</message>
+   <message level="Info" culprit="calibration_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>calibration_ram</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0"</message>
+   <message level="Info" culprit="channel_adapter_0"><![CDATA["<b>q_sys</b>" instantiated <b>channel_adapter</b> "<b>channel_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/q_sys_cpu_cpu</b>"]]></message>
+   <message level="Info" culprit="cpu"><![CDATA["<b>q_sys</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
+   <message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Testbench</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Instruction decoding</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction fields</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction decodes</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Signals for RTL simulation waveforms</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Instruction controls</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline frontend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline backend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 29 starting:altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>31</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_pll</b> "<b>submodules/q_sys_ddr3_ram_pll0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_phy_core</b> "<b>submodules/q_sys_ddr3_ram_p0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_afi_mux</b> "<b>submodules/afi_mux_ddr3_ddrx</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_qseq</b> "<b>submodules/q_sys_ddr3_ram_s0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>submodules/q_sys_ddr3_ram_c0</b>"]]></message>
+   <message level="Info" culprit="ddr3_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3_ram</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
+   <message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
+   <message level="Info" culprit="p0">Generating clock pair generator</message>
+   <message level="Info" culprit="p0">Generating altgpio</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
+   <message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
+   <message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
+   <message level="Info" culprit="s0">Generating Qsys sequencer system</message>
+   <message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
+   <message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
+   <message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
+   <message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
+   <message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart"</message>
+   <message level="Info" culprit="debug_uart">Starting RTL generation for module 'q_sys_debug_uart'</message>
+   <message level="Info" culprit="debug_uart">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="debug_uart">Done RTL generation for module 'q_sys_debug_uart'</message>
+   <message level="Info" culprit="debug_uart"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_uart</b> "<b>debug_uart</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory"</message>
+   <message level="Info" culprit="descriptor_memory">Starting RTL generation for module 'q_sys_descriptor_memory'</message>
+   <message level="Info" culprit="descriptor_memory">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="descriptor_memory">Done RTL generation for module 'q_sys_descriptor_memory'</message>
+   <message level="Info" culprit="descriptor_memory"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>descriptor_memory</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 31 starting:altpll "submodules/q_sys_enet_pll"</message>
+   <message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
+   <message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
+   <message level="Debug">Command took 1.135s</message>
+   <message level="Info" culprit="enet_pll"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>enet_pll</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>14</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_eth_tse_mac</b> "<b>submodules/altera_eth_tse_mac</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Info" culprit="eth_tse"><![CDATA["<b>q_sys</b>" instantiated <b>altera_eth_tse</b> "<b>eth_tse</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
+   <message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
+   <message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name">"Generating: soft_asmiblock_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Info" culprit="asmi_parallel_instance_name">"Generating: asmi_parallel_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name</b>"]]></message>
+   <message level="Info" culprit="epcq_controller_instance_name">"Generating: epcq_controller_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_epcq_controller_instance_name</b>"]]></message>
+   <message level="Info" culprit="ext_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>ext_flash</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
+   <message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
+   <message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
+   <message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
+   <message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer"</message>
+   <message level="Info" culprit="frame_timer">Starting RTL generation for module 'q_sys_frame_timer'</message>
+   <message level="Info" culprit="frame_timer">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="frame_timer">Done RTL generation for module 'q_sys_frame_timer'</message>
+   <message level="Info" culprit="frame_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>frame_timer</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>dma_write_master</b> "<b>submodules/write_master</b>"]]></message>
+   <message level="Info" culprit="msgdma_rx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_rx</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
+   <message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
+   <message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
+   <message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>dma_read_master</b> "<b>submodules/read_master</b>"]]></message>
+   <message level="Info" culprit="msgdma_tx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_tx</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
+   <message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
+   <message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
+   <message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash"</message>
+   <message level="Info" culprit="onchip_flash">Generating top-level entity altera_onchip_flash</message>
+   <message level="Info" culprit="onchip_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_onchip_flash</b> "<b>onchip_flash</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio"</message>
+   <message level="Info" culprit="output_pio">Starting RTL generation for module 'q_sys_output_pio'</message>
+   <message level="Info" culprit="output_pio">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="output_pio">Done RTL generation for module 'q_sys_output_pio'</message>
+   <message level="Info" culprit="output_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>output_pio</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 37 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_interface"><![CDATA["<b>q_sys</b>" instantiated <b>sensor_recon</b> "<b>sensor_interface</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer"</message>
+   <message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'q_sys_sys_clk_timer'</message>
+   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'q_sys_sys_clk_timer'</message>
+   <message level="Info" culprit="sys_clk_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid"</message>
+   <message level="Info" culprit="sysid"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer"</message>
+   <message level="Info" culprit="tx_multiplexer"><![CDATA["<b>q_sys</b>" instantiated <b>multiplexer</b> "<b>tx_multiplexer</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:udp_generator "submodules/udp_generator"</message>
+   <message level="Info" culprit="udp_generator"><![CDATA["<b>q_sys</b>" instantiated <b>udp_generator</b> "<b>udp_generator</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
+   <message
+       level="Info"
+       culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
+   <message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.007s/0.008s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.009s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_007">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_008">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_009">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_010">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010">Timing: COM:3/0.020s/0.048s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_011">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_012">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_013">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_014">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_015">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_016">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_017">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_018">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_019">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_020">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020">Timing: COM:3/0.006s/0.006s</message>
+   <message
+       level="Debug"
+       culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>218</b> modules, <b>742</b> connections]]></message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_008</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_022</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_028</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_014</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_014</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020</b>"]]></message>
+   <message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
+   <message
+       level="Info"
+       culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
+   <message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
+   <message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
+   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
+   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
+   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
+   <message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
+   <message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
+   <message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
+   <message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
+   <message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
+   <message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
+   <message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
+   <message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
+   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
+   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
+   <message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
+   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
+   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
+   <message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
+   <message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
+   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
+   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
+   <message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
+   <message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
+   <message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
+   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
+   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
+   <message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
+   <message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
+   <message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper"</message>
+   <message level="Info" culprit="irq_mapper"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser"</message>
+   <message level="Info" culprit="irq_synchronizer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_clock_crosser</b> "<b>irq_synchronizer</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>timing_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001_timing_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
+   <message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
+   <message level="Info" culprit="rst_controller"><![CDATA["<b>q_sys</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=1,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=15000,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=,CLK3_DUTY_CYCLE=,CLK3_MULTIPLY_BY=,CLK3_PHASE_SHIFT=,CLK4_DIVIDE_BY=,CLK4_DUTY_CYCLE=,CLK4_MULTIPLY_BY=,CLK4_PHASE_SHIFT=,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NORMAL,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_USED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_UNUSED,PORT_clk2=PORT_UNUSED,PORT_clk3=PORT_UNUSED,PORT_clk4=PORT_UNUSED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT="
+   instancePathKey="q_sys:.:altpll_shift"
+   kind="altpll"
+   version="19.1"
+   name="q_sys_altpll_shift">
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="CLK1_PHASE_SHIFT" value="15000" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="HIDDEN_CUSTOM_ELABORATION" value="altpll_avalon_elaboration" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_UNUSED" />
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter
+     name="HIDDEN_USED_PORTS"
+     value="UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter
+     name="HIDDEN_IF_PORTS"
+     value="IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}" />
+  <parameter
+     name="HIDDEN_MF_PORTS"
+     value="MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter
+     name="HIDDEN_PRIVATES"
+     value="PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter
+     name="HIDDEN_IS_NUMERIC"
+     value="IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter
+     name="HIDDEN_CONSTANTS"
+     value="CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT" value="altpll_avalon_post_edit" />
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_altpll_shift.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="altpll_shift" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altpll "submodules/q_sys_altpll_shift"</message>
+   <message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
+   <message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
+   <message level="Debug">Command took 1.307s</message>
+   <message level="Info" culprit="altpll_shift"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>altpll_shift</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=false,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=true,derived_has_irq=false,derived_has_out=false,derived_has_tri=false,derived_irq_type=NONE,direction=Input,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=9"
+   instancePathKey="q_sys:.:button_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   name="q_sys_button_pio">
+  <parameter name="derived_do_test_bench_wiring" value="false" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="derived_has_irq" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="derived_has_out" value="false" />
+  <parameter name="derived_has_in" value="true" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="derived_has_tri" value="false" />
+  <parameter name="derived_capture" value="false" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="derived_edge_type" value="NONE" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="derived_irq_type" value="NONE" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="width" value="9" />
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="direction" value="Input" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_button_pio.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="button_pio" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio"</message>
+   <message level="Info" culprit="button_pio">Starting RTL generation for module 'q_sys_button_pio'</message>
+   <message level="Info" culprit="button_pio">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="button_pio">Done RTL generation for module 'q_sys_button_pio'</message>
+   <message level="Info" culprit="button_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_calibration_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=16,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_calibration_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
+   instancePathKey="q_sys:.:calibration_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   name="q_sys_calibration_ram">
+  <parameter name="derived_singleClockOperation" value="false" />
+  <parameter name="derived_is_hardcopy" value="false" />
+  <parameter
+     name="deviceFeatures"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="autoInitializationFileName" value="q_sys_calibration_ram" />
+  <parameter name="derived_gui_ram_block_type" value="Automatic" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="dualPort" value="true" />
+  <parameter name="derived_set_addr_width2" value="9" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="derived_set_addr_width" value="9" />
+  <parameter name="derived_init_file_name" value="q_sys_calibration_ram.hex" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="derived_set_data_width2" value="16" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="derived_enableDiffWidth" value="false" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="derived_set_data_width" value="16" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="dataWidth2" value="16" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_calibration_ram.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="calibration_ram" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram"</message>
+   <message level="Info" culprit="calibration_ram">Starting RTL generation for module 'q_sys_calibration_ram'</message>
+   <message level="Info" culprit="calibration_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="calibration_ram">Done RTL generation for module 'q_sys_calibration_ram'</message>
+   <message level="Info" culprit="calibration_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>calibration_ram</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="channel_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=1,inErrorDescriptor=,inErrorWidth=1,inMaxChannel=1,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outChannelWidth=0,outMaxChannel=1"
+   instancePathKey="q_sys:.:channel_adapter_0"
+   kind="channel_adapter"
+   version="19.1"
+   name="q_sys_channel_adapter_0">
+  <parameter name="inErrorWidth" value="1" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="inChannelWidth" value="1" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="inMaxChannel" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="outMaxChannel" value="1" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="true" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="channel_adapter_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0"</message>
+   <message level="Info" culprit="channel_adapter_0"><![CDATA["<b>q_sys</b>" instantiated <b>channel_adapter</b> "<b>channel_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_nios2_gen2:19.1:AUTO_CLK_CLOCK_DOMAIN=14,AUTO_CLK_RESET_DOMAIN=14,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=3,mul_64_impl=0,mul_shift_choice=0,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=0,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings=)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:cpu"
+   kind="altera_nios2_gen2"
+   version="19.1"
+   name="q_sys_cpu">
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="dcache_size_derived" value="2048" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter
+     name="deviceFeaturesSystemInfo"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="debug_offchiptrace" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="debug_onchiptrace" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="internalIrqMaskSystemInfo" value="61" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="exceptionAbsoluteAddr" value="134218016" />
+  <parameter name="icache_size" value="2048" />
+  <parameter
+     name="dataSlaveMapParam"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="stratix_dspblock_shift_mul" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="setting_ioregionBypassDCache" value="false" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="translate_on" value=" &quot;synthesis translate_on&quot;  " />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="resetSlave" value="ext_flash.avl_mem" />
+  <parameter name="dcache_bursts_derived" value="false" />
+  <parameter name="multiplierType" value="mul_fast32" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="breakSlave" value="cpu.jtag_debug_module" />
+  <parameter name="exceptionOffset" value="288" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="breakAbsoluteAddr" value="406857760" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="resetAbsoluteAddr" value="335544320" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="debug_insttrace" value="false" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="14" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="14" />
+  <parameter name="debug_datatrace" value="false" />
+  <parameter name="debug_hwbreakpoint" value="2" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="dcache_lineSize_derived" value="32" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter
+     name="instSlaveMapParam"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="shifterType" value="fast_le_shift" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp"
+       type="OTHER"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="cpu" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/q_sys_cpu_cpu</b>"]]></message>
+   <message level="Info" culprit="cpu"><![CDATA["<b>q_sys</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
+   <message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Testbench</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Instruction decoding</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction fields</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction decodes</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Signals for RTL simulation waveforms</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Instruction controls</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline frontend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline backend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_ddr3_emif:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=true,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=true,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=100.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,SPEED_GRADE_CACHE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=150000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=300000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_afi_splitter:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:))(altera_mem_if_pll_bridge:19.1:CORE_PERIPHERY_DUAL_CLOCK=false,CUT_NEW_FAMILY_TIMING=true,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DISABLE_CHILD_MESSAGING=true,DUPLICATE_PLL_FOR_PHY_CLK=false,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,NUM_PLL_SHARING_INTERFACES=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PRE_V_SERIES_FAMILY=false,RATE=Half,SEQUENCER_TYPE=NIOS,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,USE_DR_CLK=false)(clock:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)"
+   instancePathKey="q_sys:.:ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="19.1"
+   name="q_sys_ddr3_ram">
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
+  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
+  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
+  <parameter name="MEM_ADD_LAT" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="INTG_MEM_IF_TRFC" value="34" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CALIB_LFIFO_OFFSET" value="4" />
+  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
+  <parameter name="IO_DM_OUT_RESERVE" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="DELAY_PER_OPA_TAP" value="416" />
+  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
+  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
+  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="AVL_DATA_WIDTH" value="32" />
+  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
+  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="CFG_READ_ODT_CHIP" value="0" />
+  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
+  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
+  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="TG_TEMP_PORT_5" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
+  <parameter name="TG_TEMP_PORT_3" value="0" />
+  <parameter name="TG_TEMP_PORT_4" value="0" />
+  <parameter name="TG_TEMP_PORT_1" value="0" />
+  <parameter name="TG_TEMP_PORT_2" value="0" />
+  <parameter name="MEM_CLK_NS" value="3.333" />
+  <parameter name="TG_TEMP_PORT_0" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
+  <parameter name="PLL_AFI_CLK_MULT" value="3" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="CFG_ENABLE_NO_DM" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
+  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
+  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
+  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="PLL_DR_CLK_DIV" value="0" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
+  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
+  <parameter name="DLL_MASTER" value="true" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
+  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="WEIGHT_PORT_2" value="0" />
+  <parameter name="WEIGHT_PORT_1" value="0" />
+  <parameter name="WEIGHT_PORT_0" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="MAX10" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="WEIGHT_PORT_5" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="WEIGHT_PORT_4" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
+  <parameter name="WEIGHT_PORT_3" value="0" />
+  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
+  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="PLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
+  <parameter name="TB_PLL_DLL_MASTER" value="true" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="LOCAL_CS_WIDTH" value="0" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
+  <parameter name="PHY_CLKBUF" value="false" />
+  <parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
+  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
+  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
+  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
+  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
+  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
+  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="IO_DQS_IN_RESERVE" value="3" />
+  <parameter name="AVL_NUM_SYMBOLS" value="4" />
+  <parameter name="ENABLE_NIOS_OCI" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="CTL_OUTPUT_REGD" value="false" />
+  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="AVL_PORT" value="" />
+  <parameter name="TB_RATE" value="HALF" />
+  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
+  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="PLL_MEM_CLK_MULT" value="3" />
+  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
+  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="PLL_WRITE_CLK_DIV" value="1" />
+  <parameter name="CALIB_VFIFO_OFFSET" value="12" />
+  <parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
+  <parameter name="MSB_RFIFO_PORT_2" value="5" />
+  <parameter name="MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
+  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
+  <parameter name="SEQUENCER_TYPE_CACHE" value="NIOS" />
+  <parameter name="CTL_USR_REFRESH" value="0" />
+  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="DQS_PHASE_SHIFT" value="9000" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
+  <parameter name="REGISTER_C2P" value="false" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="DQS_EN_DELAY_MAX" value="7" />
+  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="CFG_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
+  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="DUAL_WRITE_CLOCK" value="false" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_TBP_NUM" value="4" />
+  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="CFG_ECC_DECODER_REG" value="0" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
+  <parameter name="REF_CLK_FREQ_CACHE" value="100.0" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="READ_FIFO_HALF_RATE" value="true" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="true" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="IO_OUT2_DELAY_MAX" value="7" />
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
+  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="CTL_SELF_REFRESH" value="0" />
+  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
+  <parameter name="PLL_MEM_CLK_DIV" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
+  <parameter name="USE_HARD_READ_FIFO" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
+  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="PHY_VERSION_NUMBER" value="191" />
+  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
+  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="CFG_TYPE" value="2" />
+  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
+  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="CFG_INTERFACE_WIDTH" value="8" />
+  <parameter name="IO_OUT1_DELAY_MAX" value="15" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
+  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
+  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
+  <parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
+  <parameter name="CFG_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="IO_STANDARD" value="SSTL-15" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="SPEED_GRADE_CACHE" value="6" />
+  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
+  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
+  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
+  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
+  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MAX10_RTL_SEQ" value="true" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
+  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="FLY_BY" value="false" />
+  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="DWIDTH_RATIO" value="4" />
+  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
+  <parameter name="CFG_CLR_INTR" value="0" />
+  <parameter name="ENABLE_ABSTRACT_RAM" value="false" />
+  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
+  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
+  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
+  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
+  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
+  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_HR_CLK_DIV" value="0" />
+  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
+  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
+  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="LOW_LATENCY" value="false" />
+  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
+  <parameter name="CFG_STARVE_LIMIT" value="10" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
+  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="CFG_ADDR_ORDER" value="0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CTL_ODT_ENABLED" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="VFIFO_AS_SHIFT_REG" value="true" />
+  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
+  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
+  <parameter name="PLL_DR_CLK_MULT" value="0" />
+  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="RATE_CACHE" value="Half" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CTL_CS_WIDTH" value="1" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
+  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
+  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
+  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
+  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
+  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
+  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="VCALIB_COUNT_WIDTH" value="2" />
+  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
+  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DLL_USE_DR_CLK" value="false" />
+  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="ENUM_MEM_IF_TMRD" value="" />
+  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="TB_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="REF_CLK_PS" value="10000.0" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
+  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="IO_IN_DELAY_MAX" value="15" />
+  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
+  <parameter name="FAST_SIM_CALIBRATION" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="AVL_ADDR_WIDTH" value="25" />
+  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MAX10_CFG" value="true" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
+  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
+  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
+  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
+  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="AVL_BE_WIDTH" value="4" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_MULT" value="3" />
+  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
+  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
+  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
+  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
+  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="GENERIC_PLL" value="false" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="REF_CLK_NS" value="10.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_CACHE_VALID" value="true" />
+  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
+  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
+  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="PLL_HR_CLK_MULT" value="0" />
+  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
+  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="AVL_SIZE_WIDTH" value="3" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
+  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter
+     name="CPORT_TYPE_PORT"
+     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
+  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
+  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MEM_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
+  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
+  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
+  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
+  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
+  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
+  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
+  <parameter name="MEM_T_WL" value="5" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
+  <parameter name="MEM_CLK_PS" value="3333.0" />
+  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
+  <parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
+  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="DQS_IN_DELAY_MAX" value="15" />
+  <parameter name="LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
+  <parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="USE_2X_FF" value="false" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="PRIORITY_PORT_0" value="0" />
+  <parameter name="MEM_T_RL" value="5" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="PRIORITY_PORT_2" value="0" />
+  <parameter name="PRIORITY_PORT_1" value="0" />
+  <parameter name="USE_DR_CLK" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
+  <parameter name="CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="PRIORITY_PORT_4" value="0" />
+  <parameter name="PRIORITY_PORT_3" value="0" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
+  <parameter name="PRIORITY_PORT_5" value="0" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="PLL_AFI_CLK_DIV" value="2" />
+  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/max10emif_dcfifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing_core.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_map.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_assignments.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_parameters.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_datamux.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_bitcheck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_broadcast.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_write_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_dm_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_read_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_pll_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_phy_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_generic.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr12.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_jumplogic.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr72.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ddr3.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_list.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv"
+       type="VERILOG_INCLUDE"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_interfaces/alt_mem_if_ddr3_emif/alt_mem_if_ddr3_emif_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_pll/altera_mem_if_ddr3_pll/altera_mem_if_ddr3_pll_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_phy_core/altera_mem_if_ddr3_phy_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_mux/altera_mem_if_ddr3_afi_mux_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_qseq/altera_mem_if_ddr3_qseq/altera_mem_if_ddr3_qseq_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller/alt_mem_if_nextgen_ddr3_controller_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="ddr3_ram" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 29 starting:altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>31</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_pll</b> "<b>submodules/q_sys_ddr3_ram_pll0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_phy_core</b> "<b>submodules/q_sys_ddr3_ram_p0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_afi_mux</b> "<b>submodules/afi_mux_ddr3_ddrx</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_qseq</b> "<b>submodules/q_sys_ddr3_ram_s0</b>"]]></message>
+   <message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>submodules/q_sys_ddr3_ram_c0</b>"]]></message>
+   <message level="Info" culprit="ddr3_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3_ram</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
+   <message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
+   <message level="Info" culprit="p0">Generating clock pair generator</message>
+   <message level="Info" culprit="p0">Generating altgpio</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
+   <message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
+   <message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
+   <message level="Info" culprit="s0">Generating Qsys sequencer system</message>
+   <message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
+   <message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
+   <message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
+   <message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
+   <message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_uart:19.1:baud=115200,baudError=0.01,clockRate=50000000,dataBits=8,fixedBaud=true,parity=NONE,parityFisrtChar=N,simCharStream=,simInteractiveInputEnable=false,simInteractiveOutputEnable=false,simTrueBaud=false,stopBits=1,syncRegDepth=2,useCtsRts=false,useEopRegister=false,useRelativePathForSimFile=false"
+   instancePathKey="q_sys:.:debug_uart"
+   kind="altera_avalon_uart"
+   version="19.1"
+   name="q_sys_debug_uart">
+  <parameter name="baud" value="115200" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="parityFisrtChar" value="N" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="baudError" value="0.01" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_debug_uart.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="debug_uart" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart"</message>
+   <message level="Info" culprit="debug_uart">Starting RTL generation for module 'q_sys_debug_uart'</message>
+   <message level="Info" culprit="debug_uart">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="debug_uart">Done RTL generation for module 'q_sys_debug_uart'</message>
+   <message level="Info" culprit="debug_uart"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_uart</b> "<b>debug_uart</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_descriptor_memory,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_descriptor_memory.hex,derived_is_hardcopy=false,derived_set_addr_width=11,derived_set_addr_width2=11,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
+   instancePathKey="q_sys:.:descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   name="q_sys_descriptor_memory">
+  <parameter name="derived_singleClockOperation" value="false" />
+  <parameter name="derived_is_hardcopy" value="false" />
+  <parameter
+     name="deviceFeatures"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="autoInitializationFileName" value="q_sys_descriptor_memory" />
+  <parameter name="derived_gui_ram_block_type" value="Automatic" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="dualPort" value="false" />
+  <parameter name="derived_set_addr_width2" value="11" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="derived_set_addr_width" value="11" />
+  <parameter name="derived_init_file_name" value="q_sys_descriptor_memory.hex" />
+  <parameter
+     name="initializationFileName"
+     value="/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="derived_set_data_width2" value="32" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="derived_enableDiffWidth" value="false" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="derived_set_data_width" value="32" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="8192" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_descriptor_memory.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="descriptor_memory" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory"</message>
+   <message level="Info" culprit="descriptor_memory">Starting RTL generation for module 'q_sys_descriptor_memory'</message>
+   <message level="Info" culprit="descriptor_memory">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="descriptor_memory">Done RTL generation for module 'q_sys_descriptor_memory'</message>
+   <message level="Info" culprit="descriptor_memory"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>descriptor_memory</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=2,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=0,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=2,CLK3_DUTY_CYCLE=50,CLK3_MULTIPLY_BY=5,CLK3_PHASE_SHIFT=-3000,CLK4_DIVIDE_BY=2,CLK4_DUTY_CYCLE=50,CLK4_MULTIPLY_BY=1,CLK4_PHASE_SHIFT=-10000,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NO_COMPENSATION,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_UNUSED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_USED,PORT_clk2=PORT_USED,PORT_clk3=PORT_USED,PORT_clk4=PORT_USED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT="
+   instancePathKey="q_sys:.:enet_pll"
+   kind="altpll"
+   version="19.1"
+   name="q_sys_enet_pll">
+  <parameter name="CLK3_PHASE_SHIFT" value="-3000" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK4_PHASE_SHIFT" value="-10000" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="CLK1_PHASE_SHIFT" value="0" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="HIDDEN_CUSTOM_ELABORATION" value="altpll_avalon_elaboration" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK0_DIVIDE_BY" value="2" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="PORT_clk4" value="PORT_USED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk2" value="PORT_USED" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="PORT_clk3" value="PORT_USED" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter
+     name="HIDDEN_USED_PORTS"
+     value="UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter
+     name="HIDDEN_IF_PORTS"
+     value="IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}" />
+  <parameter
+     name="HIDDEN_MF_PORTS"
+     value="MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DIVIDE_BY" value="2" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="2" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter
+     name="HIDDEN_PRIVATES"
+     value="PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="50" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter
+     name="HIDDEN_IS_NUMERIC"
+     value="IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1" />
+  <parameter name="CLK3_MULTIPLY_BY" value="5" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK4_MULTIPLY_BY" value="1" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="CLK4_DUTY_CYCLE" value="50" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter
+     name="HIDDEN_CONSTANTS"
+     value="CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT" value="altpll_avalon_post_edit" />
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_enet_pll.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="enet_pll" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 31 starting:altpll "submodules/q_sys_enet_pll"</message>
+   <message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
+   <message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
+   <message level="Debug">Command took 1.135s</message>
+   <message level="Info" culprit="enet_pll"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>enet_pll</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_eth_tse:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,XCVR_RCFG_JTAG_ENABLE=0,XCVR_SET_CAPABILITY_REG_ENABLE=0,XCVR_SET_CSR_SOFT_LOGIC_ENABLE=0,XCVR_SET_PRBS_SOFT_LOGIC_ENABLE=0,XCVR_SET_USER_IDENTIFIER=0,core_variation=MAC_ONLY,core_version=4865,dev_version=4865,deviceFamily=MAX10,deviceFamilyName=MAX 10,eg_addr=11,eg_fifo=2048,ena_hash=false,enable_alt_reconfig=false,enable_clk_sharing=false,enable_ecc=false,enable_ena=32,enable_gmii_loopback=true,enable_hd_logic=true,enable_lgth_check=true,enable_mac_flow_ctrl=false,enable_mac_vlan=false,enable_magic_detect=true,enable_padding=true,enable_ptp_1step=false,enable_sgmii=true,enable_shift16=true,enable_sup_addr=false,enable_timestamping=false,enable_use_internal_fifo=true,export_pwrdn=false,ext_stat_cnt_ena=false,gbit_only=true,ifGMII=RGMII,ing_addr=11,ing_fifo=2048,isUseMAC=true,isUsePCS=false,max_channels=1,mbit_only=true,mdio_clk_div=40,nf_lvds_iopll_num_channels=4,nf_phyip_rcfg_enable=true,phy_identifier=0,phyip_en_synce_support=false,phyip_pll_base_data_rate=1250 Mbps,phyip_pll_type=CMU,phyip_pma_bonding_mode=x1,reduced_control=false,reduced_interface_ena=true,starting_channel_number=0,stat_cnt_ena=true,synchronizer_depth=3,transceiver_type=NONE,tstamp_fp_width=4,useMDIO=true,use_mac_clken=false,use_misc_ports=true(altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)"
+   instancePathKey="q_sys:.:eth_tse"
+   kind="altera_eth_tse"
+   version="19.1"
+   name="q_sys_eth_tse">
+  <parameter name="enable_clk_sharing" value="false" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="gbit_only" value="true" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="synchronizer_depth" value="3" />
+  <parameter name="use_misc_ports" value="true" />
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="nf_phyip_rcfg_enable" value="true" />
+  <parameter name="reduced_interface_ena" value="true" />
+  <parameter name="deviceFamily" value="MAX10" />
+  <parameter name="core_version" value="4865" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="mbit_only" value="true" />
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="nf_lvds_iopll_num_channels" value="4" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="isUseMAC" value="true" />
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="eg_fifo" value="2048" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="reduced_control" value="false" />
+  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="enable_gmii_loopback" value="true" />
+  <parameter name="enable_padding" value="true" />
+  <parameter name="dev_version" value="4865" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="isUsePCS" value="false" />
+  <parameter name="enable_lgth_check" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="ing_fifo" value="2048" />
+  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_eth_tse.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clk_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328checker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32galois8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gmii_io.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_hashing.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lfsr_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_loopback_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altshifttaps.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_magic_detection.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_base.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_gen_host.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_false_path_marker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clock_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gray_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_bin_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/altera_eth_tse/altera_eth_tse_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_gpio_lite/altera_gpio_lite_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="eth_tse" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>14</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_eth_tse_mac</b> "<b>submodules/altera_eth_tse_mac</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
+   <message level="Info" culprit="eth_tse"><![CDATA["<b>q_sys</b>" instantiated <b>altera_eth_tse</b> "<b>eth_tse</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
+   <message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
+   <message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=Micron512,IO_MODE=QUAD,UNIQUE_ID=q_sys_ext_flash,clkFreq=0,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1(altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD))(altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_UNUSED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_UNUSED,PORT_ILLEGAL_ERASE=PORT_UNUSED,PORT_ILLEGAL_WRITE=PORT_UNUSED,PORT_RDID_OUT=PORT_UNUSED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_UNUSED,PORT_READ_RDID=PORT_UNUSED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_UNUSED,PORT_SECTOR_ERASE=PORT_UNUSED,PORT_SECTOR_PROTECT=PORT_UNUSED,PORT_SHIFT_BYTES=PORT_UNUSED,PORT_WREN=PORT_UNUSED,PORT_WRITE=PORT_UNUSED,USE_ASMIBLOCK=ON,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_UNUSED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_UNUSED,PORT_ILLEGAL_ERASE=PORT_UNUSED,PORT_ILLEGAL_WRITE=PORT_UNUSED,PORT_RDID_OUT=PORT_UNUSED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_UNUSED,PORT_READ_RDID=PORT_UNUSED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_UNUSED,PORT_SECTOR_ERASE=PORT_UNUSED,PORT_SECTOR_PROTECT=PORT_UNUSED,PORT_SHIFT_BYTES=PORT_UNUSED,PORT_WREN=PORT_UNUSED,PORT_WRITE=PORT_UNUSED,USE_ASMIBLOCK=ON,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None))"
+   instancePathKey="q_sys:.:ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   name="q_sys_ext_flash">
+  <parameter name="clkFreq" value="0" />
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="DDASI" value="1" />
+  <parameter name="UNIQUE_ID" value="q_sys_ext_flash" />
+  <parameter name="CS_WIDTH" value="1" />
+  <parameter
+     name="deviceFeaturesSystemInfo"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="ASI_WIDTH" value="4" />
+  <parameter name="ENABLE_4BYTE_ADDR" value="1" />
+  <parameter name="ASMI_ADDR_WIDTH" value="32" />
+  <parameter name="ADDR_WIDTH" value="24" />
+  <parameter name="FLASH_TYPE" value="Micron512" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
+       type="SYSTEM_VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/generic_qspi_controller_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="ext_flash" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name">"Generating: soft_asmiblock_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Info" culprit="asmi_parallel_instance_name">"Generating: asmi_parallel_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name</b>"]]></message>
+   <message level="Info" culprit="epcq_controller_instance_name">"Generating: epcq_controller_instance_name"</message>
+   <message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_epcq_controller_instance_name</b>"]]></message>
+   <message level="Info" culprit="ext_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>ext_flash</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
+   <message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
+   <message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
+   <message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
+   <message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=4999,mult=2.0E-8,period=5000,periodUnits=CLOCKS,periodUnitsString=clocks,resetOutput=false,slave_address_width=3,snapshot=false,systemFrequency=50000000,ticksPerSec=10000.0,timeoutPulseOutput=true,timerPreset=CUSTOM,valueInSecond=0.0,watchdogPulse=2"
+   instancePathKey="q_sys:.:frame_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   name="q_sys_frame_timer">
+  <parameter name="loadValue" value="4999" />
+  <parameter name="timeoutPulseOutput" value="true" />
+  <parameter name="period" value="5000" />
+  <parameter name="periodUnitsString" value="clocks" />
+  <parameter name="mult" value="2.0E-8" />
+  <parameter name="ticksPerSec" value="10000.0" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="valueInSecond" value="0.0" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="periodUnits" value="CLOCKS" />
+  <parameter name="watchdogPulse" value="2" />
+  <parameter name="slave_address_width" value="3" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="false" />
+  <parameter name="timerPreset" value="CUSTOM" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_frame_timer.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="frame_timer" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer"</message>
+   <message level="Info" culprit="frame_timer">Starting RTL generation for module 'q_sys_frame_timer'</message>
+   <message level="Info" culprit="frame_timer">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="frame_timer">Done RTL generation for module 'q_sys_frame_timer'</message>
+   <message level="Info" culprit="frame_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>frame_timer</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = -1,AUTO_MM_WRITE_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = 28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=6,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)"
+   instancePathKey="q_sys:.:msgdma_rx"
+   kind="altera_msgdma"
+   version="19.1"
+   name="q_sys_msgdma_rx">
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="CHANNEL_ENABLE_DERIVED" value="0" />
+  <parameter name="MODE" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="ERROR_ENABLE_DERIVED" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="PACKET_ENABLE_DERIVED" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="STRIDE_ENABLE_DERIVED" value="0" />
+  <parameter
+     name="AUTO_MM_WRITE_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_rx.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/byte_enable_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ST_to_MM_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="msgdma_rx" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>dma_write_master</b> "<b>submodules/write_master</b>"]]></message>
+   <message level="Info" culprit="msgdma_rx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_rx</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
+   <message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
+   <message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
+   <message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = 28,AUTO_MM_WRITE_ADDRESS_MAP=,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = -1,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=1,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)"
+   instancePathKey="q_sys:.:msgdma_tx"
+   kind="altera_msgdma"
+   version="19.1"
+   name="q_sys_msgdma_tx">
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="CHANNEL_ENABLE_DERIVED" value="0" />
+  <parameter name="MODE" value="1" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="ERROR_ENABLE_DERIVED" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="PACKET_ENABLE_DERIVED" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter
+     name="AUTO_MM_READ_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"
+     value="&lt;address-map&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="STRIDE_ENABLE_DERIVED" value="0" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_tx.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/MM_to_ST_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="msgdma_tx" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
+   <message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>dma_read_master</b> "<b>submodules/read_master</b>"]]></message>
+   <message level="Info" culprit="msgdma_tx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_tx</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
+   <message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
+   <message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
+   <message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=360447,ADDR_RANGE1_OFFSET=2048,ADDR_RANGE2_END_ADDR=360447,ADDR_RANGE2_OFFSET=0,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=50000000,AVMM_DATA_ADDR_WIDTH=19,AVMM_DATA_BURSTCOUNT_WIDTH=4,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=50.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=50,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=60,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=17500000,FLASH_READ_CYCLE_MAX_INDEX=5,FLASH_RESET_CYCLE_MAX_INDEX=12,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=15250,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=114687,MAX_VALID_ADDR=360447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M50DAF484C6GES,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=8,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=8191,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=16383,SECTOR2_MAP=2,SECTOR2_START_ADDR=8192,SECTOR3_END_ADDR=114687,SECTOR3_MAP=3,SECTOR3_START_ADDR=16384,SECTOR4_END_ADDR=188415,SECTOR4_MAP=4,SECTOR4_START_ADDR=114688,SECTOR5_END_ADDR=360447,SECTOR5_MAP=5,SECTOR5_START_ADDR=188416,SECTOR_ACCESS_MODE=Read and write,Read and write,Read and write,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff,SECTOR_ID=1,2,3,4,5,SECTOR_READ_PROTECTION_MODE=0,SECTOR_STORAGE_TYPE=UFM,UFM,UFM,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=q_sys_onchip_flash,initFlashContent=false,initializationFileName=D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
+   instancePathKey="q_sys:.:onchip_flash"
+   kind="altera_onchip_flash"
+   version="19.1"
+   name="altera_onchip_flash">
+  <parameter name="SECTOR_READ_PROTECTION_MODE" value="0" />
+  <parameter name="MIN_UFM_VALID_ADDR" value="0" />
+  <parameter name="AVMM_DATA_ADDR_WIDTH" value="19" />
+  <parameter name="SECTOR3_START_ADDR" value="16384" />
+  <parameter name="AUTO_CLOCK_RATE" value="50000000" />
+  <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="17500000" />
+  <parameter name="SECTOR1_END_ADDR" value="8191" />
+  <parameter name="SECTOR4_END_ADDR" value="188415" />
+  <parameter name="initializationFileNameForSim" value="altera_onchip_flash.dat" />
+  <parameter name="MAX_VALID_ADDR" value="360447" />
+  <parameter name="DATA_INTERFACE" value="Parallel" />
+  <parameter name="AVMM_DATA_DATA_WIDTH" value="32" />
+  <parameter name="SECTOR1_MAP" value="1" />
+  <parameter name="INIT_FILENAME_SIM" value="" />
+  <parameter
+     name="initializationFileName"
+     value="D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex" />
+  <parameter name="MIN_VALID_ADDR" value="0" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="SECTOR2_MAP" value="2" />
+  <parameter name="SECTOR3_END_ADDR" value="114687" />
+  <parameter name="CONFIGURATION_SCHEME" value="Internal Configuration" />
+  <parameter name="SECTOR3_MAP" value="3" />
+  <parameter name="DEVICE_ID" value="50" />
+  <parameter name="WRAPPING_BURST_MODE" value="false" />
+  <parameter name="SECTOR5_MAP" value="5" />
+  <parameter name="FLASH_SEQ_READ_DATA_COUNT" value="4" />
+  <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="15250" />
+  <parameter name="autoInitializationFileName" value="q_sys_onchip_flash" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ADDR_RANGE3_OFFSET" value="0" />
+  <parameter name="ADDR_RANGE2_OFFSET" value="0" />
+  <parameter name="SECTOR2_END_ADDR" value="16383" />
+  <parameter name="SECTOR4_MAP" value="4" />
+  <parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="12" />
+  <parameter
+     name="SECTOR_ADDRESS_MAPPING"
+     value="0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff" />
+  <parameter name="IS_ERAM_SKIP" value="True" />
+  <parameter name="READ_BURST_MODE" value="Incrementing" />
+  <parameter name="READ_AND_WRITE_MODE" value="true" />
+  <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="60" />
+  <parameter name="SECTOR5_START_ADDR" value="188416" />
+  <parameter name="PART_NAME" value="10M50DAF484C6GES" />
+  <parameter name="ADDR_RANGE1_OFFSET" value="2048" />
+  <parameter name="MAX_UFM_VALID_ADDR" value="114687" />
+  <parameter name="INIT_FILENAME" value="" />
+  <parameter name="CONFIGURATION_MODE" value="Single Uncompressed Image" />
+  <parameter name="PARALLEL_MODE" value="true" />
+  <parameter name="SECTOR4_START_ADDR" value="114688" />
+  <parameter name="FLASH_ADDR_ALIGNMENT_BITS" value="2" />
+  <parameter
+     name="SECTOR_ACCESS_MODE"
+     value="Read and write,Read and write,Read and write,Read and write,Read and write" />
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="SECTOR1_START_ADDR" value="0" />
+  <parameter name="ADDR_RANGE1_END_ADDR" value="360447" />
+  <parameter name="IS_COMPRESSED_IMAGE" value="False" />
+  <parameter name="SECTOR_ID" value="1,2,3,4,5" />
+  <parameter name="READ_BURST_COUNT" value="8" />
+  <parameter name="FLASH_READ_CYCLE_MAX_INDEX" value="5" />
+  <parameter name="AVMM_DATA_BURSTCOUNT_WIDTH" value="4" />
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="SECTOR_STORAGE_TYPE" value="UFM,UFM,UFM,CFM,CFM" />
+  <parameter name="ADDR_RANGE2_END_ADDR" value="360447" />
+  <parameter name="SECTOR5_END_ADDR" value="360447" />
+  <parameter name="SECTOR2_START_ADDR" value="8192" />
+  <parameter name="IS_DUAL_BOOT" value="False" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_util.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="onchip_flash" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash"</message>
+   <message level="Info" culprit="onchip_flash">Generating top-level entity altera_onchip_flash</message>
+   <message level="Info" culprit="onchip_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_onchip_flash</b> "<b>onchip_flash</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=true,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=false,derived_has_irq=false,derived_has_out=true,derived_has_tri=false,derived_irq_type=NONE,direction=Output,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=8"
+   instancePathKey="q_sys:.:output_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   name="q_sys_output_pio">
+  <parameter name="derived_do_test_bench_wiring" value="false" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="derived_has_irq" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="derived_has_out" value="true" />
+  <parameter name="derived_has_in" value="false" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="derived_has_tri" value="false" />
+  <parameter name="derived_capture" value="false" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="derived_edge_type" value="NONE" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="derived_irq_type" value="NONE" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="width" value="8" />
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="direction" value="Output" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_output_pio.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="output_pio" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio"</message>
+   <message level="Info" culprit="output_pio">Starting RTL generation for module 'q_sys_output_pio'</message>
+   <message level="Info" culprit="output_pio">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="output_pio">Done RTL generation for module 'q_sys_output_pio'</message>
+   <message level="Info" culprit="output_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>output_pio</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="sensor_recon:1:"
+   instancePathKey="q_sys:.:sensor_interface"
+   kind="sensor_recon"
+   version="1"
+   name="sensor_algo">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/div.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sqrt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ram4bkg.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/sensor_algo_qsys/sensor_recon_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="sensor_interface" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 37 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_interface"><![CDATA["<b>q_sys</b>" instantiated <b>sensor_recon</b> "<b>sensor_interface</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=499999,mult=0.001,period=10,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=100.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2"
+   instancePathKey="q_sys:.:sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   name="q_sys_sys_clk_timer">
+  <parameter name="loadValue" value="499999" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="period" value="10" />
+  <parameter name="periodUnitsString" value="ms" />
+  <parameter name="mult" value="0.001" />
+  <parameter name="ticksPerSec" value="100.0" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="valueInSecond" value="0.001" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="watchdogPulse" value="2" />
+  <parameter name="slave_address_width" value="3" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timerPreset" value="FULL_FEATURED" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="sys_clk_timer" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer"</message>
+   <message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'q_sys_sys_clk_timer'</message>
+   <message level="Info" culprit="sys_clk_timer">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'q_sys_sys_clk_timer'</message>
+   <message level="Info" culprit="sys_clk_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_sysid_qsys:19.1:id=-87110914,timestamp=1728634208"
+   instancePathKey="q_sys:.:sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="19.1"
+   name="q_sys_sysid">
+  <parameter name="id" value="-87110914" />
+  <parameter name="timestamp" value="1728634208" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sysid.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="sysid" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid"</message>
+   <message level="Info" culprit="sysid"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="multiplexer:19.1:bitsPerSymbol=8,errorWidth=1,inErrorWidth=1,inUseEmpty=false,inUseEmptyPort=AUTO,inUsePackets=true,numInputInterfaces=2,outChannelWidth=1,packetScheduling=true,schedulingSize=512,symbolsPerBeat=4,useHighBitsOfChannel=true,usePackets=true"
+   instancePathKey="q_sys:.:tx_multiplexer"
+   kind="multiplexer"
+   version="19.1"
+   name="q_sys_tx_multiplexer">
+  <parameter name="inErrorWidth" value="1" />
+  <parameter name="usePackets" value="true" />
+  <parameter name="numInputInterfaces" value="2" />
+  <parameter name="schedulingSize" value="512" />
+  <parameter name="bitsPerSymbol" value="8" />
+  <parameter name="packetScheduling" value="true" />
+  <parameter name="errorWidth" value="1" />
+  <parameter name="outChannelWidth" value="1" />
+  <parameter name="inUseEmptyPort" value="AUTO" />
+  <parameter name="useHighBitsOfChannel" value="true" />
+  <parameter name="symbolsPerBeat" value="4" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inUsePackets" value="true" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_multiplexer/avalon-st_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="tx_multiplexer" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer"</message>
+   <message level="Info" culprit="tx_multiplexer"><![CDATA["<b>q_sys</b>" instantiated <b>multiplexer</b> "<b>tx_multiplexer</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="udp_generator:1.0:"
+   instancePathKey="q_sys:.:udp_generator"
+   kind="udp_generator"
+   version="1.0"
+   name="udp_generator">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/udp_generator.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/udp_generator_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="udp_generator" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:udp_generator "submodules/udp_generator"</message>
+   <message level="Info" culprit="udp_generator"><![CDATA["<b>q_sys</b>" instantiated <b>udp_generator</b> "<b>udp_generator</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mm_interconnect:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {sensor_interface_calibration_ram_interface_translator} {altera_merlin_master_translator};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_W} {16};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CLKEN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {SYNC_RESET} {0};add_instance {calibration_ram_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_rst_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0} {calibration_ram_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_rst_reset_bridge.out_reset} {sensor_interface_calibration_ram_interface_translator.reset} {reset};add_connection {sensor_interface_rst_reset_bridge.out_reset} {calibration_ram_s2_translator.reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_calibration_ram_interface_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s2_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_rst_reset_bridge.clk} {clock};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {sensor_interface_rst_reset_bridge_in_reset} {reset} {slave};set_interface_property {sensor_interface_rst_reset_bridge_in_reset} {EXPORT_OF} {sensor_interface_rst_reset_bridge.in_reset};add_interface {sensor_interface_calibration_ram_interface} {avalon} {slave};set_interface_property {sensor_interface_calibration_ram_interface} {EXPORT_OF} {sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0};add_interface {calibration_ram_s2} {avalon} {master};set_interface_property {calibration_ram_s2} {EXPORT_OF} {calibration_ram_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.calibration_ram.s2} {0};set_module_assignment {interconnect_id.sensor_interface.calibration_ram_interface} {0};(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=2,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=50000000,NUM_CLOCK_OUTPUTS=1)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)"
+   instancePathKey="q_sys:.:mm_interconnect_0"
+   kind="altera_mm_interconnect"
+   version="19.1"
+   name="q_sys_mm_interconnect_0">
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter
+     name="COMPOSE_CONTENTS"
+     value="add_instance {sensor_interface_calibration_ram_interface_translator} {altera_merlin_master_translator};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_W} {16};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CLKEN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {SYNC_RESET} {0};add_instance {calibration_ram_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_rst_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0} {calibration_ram_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_rst_reset_bridge.out_reset} {sensor_interface_calibration_ram_interface_translator.reset} {reset};add_connection {sensor_interface_rst_reset_bridge.out_reset} {calibration_ram_s2_translator.reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_calibration_ram_interface_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s2_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_rst_reset_bridge.clk} {clock};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {sensor_interface_rst_reset_bridge_in_reset} {reset} {slave};set_interface_property {sensor_interface_rst_reset_bridge_in_reset} {EXPORT_OF} {sensor_interface_rst_reset_bridge.in_reset};add_interface {sensor_interface_calibration_ram_interface} {avalon} {slave};set_interface_property {sensor_interface_calibration_ram_interface} {EXPORT_OF} {sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0};add_interface {calibration_ram_s2} {avalon} {master};set_interface_property {calibration_ram_s2} {EXPORT_OF} {calibration_ram_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.calibration_ram.s2} {0};set_module_assignment {interconnect_id.sensor_interface.calibration_ram_interface} {0};" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="mm_interconnect_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
+   <message
+       level="Info"
+       culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
+   <message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mm_interconnect:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_instruction_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_mm_read_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_mm_write_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {ddr3_ram_avl_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_W} {25};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READ} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINBURSTTRANSFER} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_LOCK} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_mem_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_W} {24};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_W} {7};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {eth_tse_control_port_translator} {altera_merlin_slave_translator};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READLATENCY} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READ} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITE} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_ADDRESS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_LOCK} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {eth_tse_control_port_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sysid_control_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READ} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sysid_control_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sysid_control_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {udp_generator_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READ} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {udp_generator_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {udp_generator_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_data_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_W} {19};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_data_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_data_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_debug_mem_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READ} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {descriptor_memory_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_W} {11};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READ} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sys_clk_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {output_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {output_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {output_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {output_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {output_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {button_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {button_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {button_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {button_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {button_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {debug_uart_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {debug_uart_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READ} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINTRANSFER} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {debug_uart_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {debug_uart_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {frame_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {frame_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {frame_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {frame_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {calibration_ram_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_data_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_data_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;7&quot;
+   name=&quot;ext_flash_avl_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d20&quot;
+   end=&quot;0x00000000018403d40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;6&quot;
+   name=&quot;eth_tse_control_port_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403000&quot;
+   end=&quot;0x00000000018403400&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;19&quot;
+   name=&quot;sysid_control_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d68&quot;
+   end=&quot;0x00000000018403d70&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;12&quot;
+   name=&quot;msgdma_tx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d00&quot;
+   end=&quot;0x00000000018403d20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;10&quot;
+   name=&quot;msgdma_rx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ce0&quot;
+   end=&quot;0x00000000018403d00&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;14&quot;
+   name=&quot;onchip_flash_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d60&quot;
+   end=&quot;0x00000000018403d68&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;20&quot;
+   name=&quot;udp_generator_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403cc0&quot;
+   end=&quot;0x00000000018403ce0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;17&quot;
+   name=&quot;sensor_interface_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d50&quot;
+   end=&quot;0x00000000018403d60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;13&quot;
+   name=&quot;msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ca0&quot;
+   end=&quot;0x00000000018403cc0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;11&quot;
+   name=&quot;msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c80&quot;
+   end=&quot;0x00000000018403ca0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;18&quot;
+   name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c60&quot;
+   end=&quot;0x00000000018403c80&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;16&quot;
+   name=&quot;output_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c40&quot;
+   end=&quot;0x00000000018403c60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;0&quot;
+   name=&quot;button_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d40&quot;
+   end=&quot;0x00000000018403d50&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;4&quot;
+   name=&quot;debug_uart_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c20&quot;
+   end=&quot;0x00000000018403c40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;9&quot;
+   name=&quot;frame_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c00&quot;
+   end=&quot;0x00000000018403c20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;1&quot;
+   name=&quot;calibration_ram_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403400&quot;
+   end=&quot;0x00000000018403800&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_mm_read_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ID} {7};set_instance_parameter_value {msgdma_tx_mm_read_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_mm_read_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_mm_write_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ID} {4};set_instance_parameter_value {msgdma_rx_mm_write_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_mm_write_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ID} {5};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ID} {2};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ID} {6};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {msgdma_rx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ID} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {ddr3_ram_avl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_DATA_W} {121};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ddr3_ram_avl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ddr3_ram_avl_agent} {ID} {3};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {ECC_ENABLE} {0};add_instance {ddr3_ram_avl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {FIFO_DEPTH} {33};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ddr3_ram_avl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {FIFO_DEPTH} {64};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ext_flash_avl_csr_agent} {ID} {7};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BYTE_CNT} {256};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BURSTWRAP} {255};set_instance_parameter_value {ext_flash_avl_mem_agent} {ID} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_mem_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {eth_tse_control_port_agent} {altera_merlin_slave_agent};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_H} {31};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_L} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {eth_tse_control_port_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {eth_tse_control_port_agent} {ST_DATA_W} {121};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {eth_tse_control_port_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {eth_tse_control_port_agent} {ID} {6};set_instance_parameter_value {eth_tse_control_port_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {ECC_ENABLE} {0};add_instance {eth_tse_control_port_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_control_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sysid_control_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sysid_control_slave_agent} {ID} {19};set_instance_parameter_value {sysid_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_csr_agent} {ID} {12};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_csr_agent} {ID} {10};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_csr_agent} {ID} {14};set_instance_parameter_value {onchip_flash_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {udp_generator_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {udp_generator_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {udp_generator_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {udp_generator_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {udp_generator_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {udp_generator_csr_agent} {ID} {20};set_instance_parameter_value {udp_generator_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {ECC_ENABLE} {0};add_instance {udp_generator_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sensor_interface_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sensor_interface_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sensor_interface_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sensor_interface_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sensor_interface_csr_agent} {ID} {17};set_instance_parameter_value {sensor_interface_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {ECC_ENABLE} {0};add_instance {sensor_interface_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_data_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_data_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_data_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_data_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_data_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BYTE_CNT} {32};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_data_agent} {ID} {15};set_instance_parameter_value {onchip_flash_data_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_data_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ID} {13};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ID} {11};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {descriptor_memory_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {descriptor_memory_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {descriptor_memory_s1_agent} {ID} {5};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {ECC_ENABLE} {0};add_instance {descriptor_memory_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {18};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {output_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {output_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {output_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {output_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {output_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {output_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {output_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {output_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {output_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {output_pio_s1_agent} {ID} {16};set_instance_parameter_value {output_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {ECC_ENABLE} {0};add_instance {output_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {button_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {button_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {button_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {button_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {button_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {button_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {button_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {button_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {button_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {button_pio_s1_agent} {ID} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {ECC_ENABLE} {0};add_instance {button_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {debug_uart_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {debug_uart_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {debug_uart_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {debug_uart_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {debug_uart_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {debug_uart_s1_agent} {ID} {4};set_instance_parameter_value {debug_uart_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {ECC_ENABLE} {0};add_instance {debug_uart_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {frame_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {frame_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {frame_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {frame_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {frame_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {frame_timer_s1_agent} {ID} {9};set_instance_parameter_value {frame_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {ECC_ENABLE} {0};add_instance {frame_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {calibration_ram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_LOCK} {51};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_H} {93};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_L} {91};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_POSTED} {48};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_H} {84};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_L} {80};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_H} {89};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_L} {85};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {calibration_ram_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_agent} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {calibration_ram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {calibration_ram_s1_agent} {ID} {1};set_instance_parameter_value {calibration_ram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {ECC_ENABLE} {0};add_instance {calibration_ram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {104};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 8 15 5 2 6 1 9 4 16 18 11 13 20 10 12 7 0 17 14 19 };set_instance_parameter_value {router} {CHANNEL_ID} {000000000000000000001 000000000000000000100 000000000010000000000 000000100000000000000 000000000100000000000 000000000000000001000 100000000000000000000 010000000000000000000 001000000000000000000 000010000000000000000 000001000000000000000 000000010000000000000 000000001000000000000 000000000000100000000 000000000000001000000 000000000000000100000 000000000000000000010 000100000000000000000 000000000001000000000 000000000000010000000 000000000000000010000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both both both both both both both both both both read both both read };set_instance_parameter_value {router} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18400000 0x18402800 0x18403000 0x18403400 0x18403c00 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 };set_instance_parameter_value {router} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18402000 0x18403000 0x18403400 0x18403800 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 0x18403d70 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {121};set_instance_parameter_value {router} {ST_CHANNEL_W} {21};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {3 8 15 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18402800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18403000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {121};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {3 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {121};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_002} {DECODER_TYPE} {0};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {3 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {64};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_003} {ST_DATA_W} {121};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_003} {DECODER_TYPE} {0};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {5 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {64};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_004} {ST_DATA_W} {121};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_004} {DECODER_TYPE} {0};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {5 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {64};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_005} {ST_DATA_W} {121};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_005} {DECODER_TYPE} {0};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {5 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {64};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_006} {ST_DATA_W} {121};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_006} {DECODER_TYPE} {0};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {5 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {64};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_007} {ST_DATA_W} {121};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_007} {DECODER_TYPE} {0};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 1 7 4 };set_instance_parameter_value {router_008} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both read read write };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {64};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_008} {ST_DATA_W} {121};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {64};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_009} {ST_DATA_W} {121};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_010} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {64};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_010} {ST_DATA_W} {121};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {64};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_011} {ST_DATA_W} {121};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {64};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_012} {ST_DATA_W} {121};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {64};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_013} {ST_DATA_W} {121};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {64};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_014} {ST_DATA_W} {121};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {64};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_015} {ST_DATA_W} {121};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {64};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_016} {ST_DATA_W} {121};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {router_017} {altera_merlin_router};set_instance_parameter_value {router_017} {DESTINATION_ID} {0 };set_instance_parameter_value {router_017} {CHANNEL_ID} {1 };set_instance_parameter_value {router_017} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_017} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_017} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_017} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_017} {SPAN_OFFSET} {};set_instance_parameter_value {router_017} {PKT_ADDR_H} {64};set_instance_parameter_value {router_017} {PKT_ADDR_L} {36};set_instance_parameter_value {router_017} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_017} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_017} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_017} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_017} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_017} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_017} {ST_DATA_W} {121};set_instance_parameter_value {router_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_017} {DECODER_TYPE} {1};set_instance_parameter_value {router_017} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_017} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_017} {MEMORY_ALIASING_DECODE} {0};add_instance {router_018} {altera_merlin_router};set_instance_parameter_value {router_018} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_018} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_018} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_018} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_018} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_018} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_018} {SPAN_OFFSET} {};set_instance_parameter_value {router_018} {PKT_ADDR_H} {64};set_instance_parameter_value {router_018} {PKT_ADDR_L} {36};set_instance_parameter_value {router_018} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_018} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_018} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_018} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_018} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_018} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_018} {ST_DATA_W} {121};set_instance_parameter_value {router_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_018} {DECODER_TYPE} {1};set_instance_parameter_value {router_018} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_018} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_018} {MEMORY_ALIASING_DECODE} {0};add_instance {router_019} {altera_merlin_router};set_instance_parameter_value {router_019} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_019} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_019} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_019} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_019} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_019} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_019} {SPAN_OFFSET} {};set_instance_parameter_value {router_019} {PKT_ADDR_H} {64};set_instance_parameter_value {router_019} {PKT_ADDR_L} {36};set_instance_parameter_value {router_019} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_019} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_019} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_019} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_019} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_019} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_019} {ST_DATA_W} {121};set_instance_parameter_value {router_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_019} {DECODER_TYPE} {1};set_instance_parameter_value {router_019} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_019} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_019} {MEMORY_ALIASING_DECODE} {0};add_instance {router_020} {altera_merlin_router};set_instance_parameter_value {router_020} {DESTINATION_ID} {0 };set_instance_parameter_value {router_020} {CHANNEL_ID} {1 };set_instance_parameter_value {router_020} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_020} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_020} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_020} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_020} {SPAN_OFFSET} {};set_instance_parameter_value {router_020} {PKT_ADDR_H} {64};set_instance_parameter_value {router_020} {PKT_ADDR_L} {36};set_instance_parameter_value {router_020} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_020} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_020} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_020} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_020} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_020} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_020} {ST_DATA_W} {121};set_instance_parameter_value {router_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_020} {DECODER_TYPE} {1};set_instance_parameter_value {router_020} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_020} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_020} {MEMORY_ALIASING_DECODE} {0};add_instance {router_021} {altera_merlin_router};set_instance_parameter_value {router_021} {DESTINATION_ID} {0 };set_instance_parameter_value {router_021} {CHANNEL_ID} {1 };set_instance_parameter_value {router_021} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_021} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_021} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_021} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_021} {SPAN_OFFSET} {};set_instance_parameter_value {router_021} {PKT_ADDR_H} {64};set_instance_parameter_value {router_021} {PKT_ADDR_L} {36};set_instance_parameter_value {router_021} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_021} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_021} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_021} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_021} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_021} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_021} {ST_DATA_W} {121};set_instance_parameter_value {router_021} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_021} {DECODER_TYPE} {1};set_instance_parameter_value {router_021} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_021} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_021} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_021} {MEMORY_ALIASING_DECODE} {0};add_instance {router_022} {altera_merlin_router};set_instance_parameter_value {router_022} {DESTINATION_ID} {0 5 2 6 3 };set_instance_parameter_value {router_022} {CHANNEL_ID} {00001 00010 00100 01000 10000 };set_instance_parameter_value {router_022} {TYPE_OF_TRANSACTION} {both read read write write };set_instance_parameter_value {router_022} {START_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {END_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {NON_SECURED_TAG} {1 1 1 1 1 };set_instance_parameter_value {router_022} {SECURED_RANGE_PAIRS} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SECURED_RANGE_LIST} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SPAN_OFFSET} {};set_instance_parameter_value {router_022} {PKT_ADDR_H} {64};set_instance_parameter_value {router_022} {PKT_ADDR_L} {36};set_instance_parameter_value {router_022} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_022} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_022} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_022} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_022} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_022} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_022} {ST_DATA_W} {121};set_instance_parameter_value {router_022} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_022} {DECODER_TYPE} {1};set_instance_parameter_value {router_022} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_022} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_022} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_022} {MEMORY_ALIASING_DECODE} {0};add_instance {router_023} {altera_merlin_router};set_instance_parameter_value {router_023} {DESTINATION_ID} {0 };set_instance_parameter_value {router_023} {CHANNEL_ID} {1 };set_instance_parameter_value {router_023} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_023} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_023} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_023} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_023} {SPAN_OFFSET} {};set_instance_parameter_value {router_023} {PKT_ADDR_H} {64};set_instance_parameter_value {router_023} {PKT_ADDR_L} {36};set_instance_parameter_value {router_023} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_023} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_023} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_023} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_023} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_023} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_023} {ST_DATA_W} {121};set_instance_parameter_value {router_023} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_023} {DECODER_TYPE} {1};set_instance_parameter_value {router_023} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_023} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_023} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_023} {MEMORY_ALIASING_DECODE} {0};add_instance {router_024} {altera_merlin_router};set_instance_parameter_value {router_024} {DESTINATION_ID} {0 };set_instance_parameter_value {router_024} {CHANNEL_ID} {1 };set_instance_parameter_value {router_024} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_024} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_024} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_024} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_024} {SPAN_OFFSET} {};set_instance_parameter_value {router_024} {PKT_ADDR_H} {64};set_instance_parameter_value {router_024} {PKT_ADDR_L} {36};set_instance_parameter_value {router_024} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_024} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_024} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_024} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_024} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_024} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_024} {ST_DATA_W} {121};set_instance_parameter_value {router_024} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_024} {DECODER_TYPE} {1};set_instance_parameter_value {router_024} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_024} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_024} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_024} {MEMORY_ALIASING_DECODE} {0};add_instance {router_025} {altera_merlin_router};set_instance_parameter_value {router_025} {DESTINATION_ID} {0 };set_instance_parameter_value {router_025} {CHANNEL_ID} {1 };set_instance_parameter_value {router_025} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_025} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_025} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_025} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_025} {SPAN_OFFSET} {};set_instance_parameter_value {router_025} {PKT_ADDR_H} {64};set_instance_parameter_value {router_025} {PKT_ADDR_L} {36};set_instance_parameter_value {router_025} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_025} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_025} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_025} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_025} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_025} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_025} {ST_DATA_W} {121};set_instance_parameter_value {router_025} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_025} {DECODER_TYPE} {1};set_instance_parameter_value {router_025} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_025} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_025} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_025} {MEMORY_ALIASING_DECODE} {0};add_instance {router_026} {altera_merlin_router};set_instance_parameter_value {router_026} {DESTINATION_ID} {0 };set_instance_parameter_value {router_026} {CHANNEL_ID} {1 };set_instance_parameter_value {router_026} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_026} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_026} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_026} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_026} {SPAN_OFFSET} {};set_instance_parameter_value {router_026} {PKT_ADDR_H} {64};set_instance_parameter_value {router_026} {PKT_ADDR_L} {36};set_instance_parameter_value {router_026} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_026} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_026} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_026} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_026} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_026} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_026} {ST_DATA_W} {121};set_instance_parameter_value {router_026} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_026} {DECODER_TYPE} {1};set_instance_parameter_value {router_026} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_026} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_026} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_026} {MEMORY_ALIASING_DECODE} {0};add_instance {router_027} {altera_merlin_router};set_instance_parameter_value {router_027} {DESTINATION_ID} {0 };set_instance_parameter_value {router_027} {CHANNEL_ID} {1 };set_instance_parameter_value {router_027} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_027} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_027} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_027} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_027} {SPAN_OFFSET} {};set_instance_parameter_value {router_027} {PKT_ADDR_H} {64};set_instance_parameter_value {router_027} {PKT_ADDR_L} {36};set_instance_parameter_value {router_027} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_027} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_027} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_027} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_027} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_027} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_027} {ST_DATA_W} {121};set_instance_parameter_value {router_027} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_027} {DECODER_TYPE} {1};set_instance_parameter_value {router_027} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_027} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_027} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_027} {MEMORY_ALIASING_DECODE} {0};add_instance {router_028} {altera_merlin_router};set_instance_parameter_value {router_028} {DESTINATION_ID} {0 };set_instance_parameter_value {router_028} {CHANNEL_ID} {1 };set_instance_parameter_value {router_028} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_028} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_028} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_028} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_028} {SPAN_OFFSET} {};set_instance_parameter_value {router_028} {PKT_ADDR_H} {46};set_instance_parameter_value {router_028} {PKT_ADDR_L} {18};set_instance_parameter_value {router_028} {PKT_PROTECTION_H} {93};set_instance_parameter_value {router_028} {PKT_PROTECTION_L} {91};set_instance_parameter_value {router_028} {PKT_DEST_ID_H} {89};set_instance_parameter_value {router_028} {PKT_DEST_ID_L} {85};set_instance_parameter_value {router_028} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {router_028} {PKT_TRANS_READ} {50};set_instance_parameter_value {router_028} {ST_DATA_W} {103};set_instance_parameter_value {router_028} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_028} {DECODER_TYPE} {1};set_instance_parameter_value {router_028} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_028} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_028} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_028} {MEMORY_ALIASING_DECODE} {0};add_instance {cpu_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_data_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_limiter} {REORDER} {0};add_instance {cpu_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_limiter} {REORDER} {0};add_instance {ext_flash_avl_mem_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BURSTWRAP_H} {87};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_MASK} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_VALUE} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {calibration_ram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BYTE_CNT_H} {54};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {21};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {4};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {4};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {5};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 1 1 1 1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_015} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_015} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_015} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_015} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_015} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_015} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_016} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_016} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_016} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_016} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_016} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_016} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_017} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_017} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_017} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_017} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_017} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_017} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_018} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_018} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_018} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_018} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_018} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_018} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_019} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_019} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_019} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_019} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_019} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_019} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_020} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_020} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_020} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_020} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_020} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_020} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {4};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {5};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_015} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_015} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_015} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_015} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_016} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_016} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_016} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_016} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_017} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_017} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_017} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_017} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_018} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_018} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_018} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_018} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_019} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_019} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_019} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_019} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_020} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_020} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_020} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_020} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {21};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {4};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {calibration_ram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {calibration_ram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {67};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {88};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {80};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {121};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_004} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_004} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_004} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_004} {USE_PACKETS} {1};set_instance_parameter_value {crosser_004} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_004} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_004} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_004} {USE_ERROR} {0};set_instance_parameter_value {crosser_004} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_004} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_005} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_005} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_005} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_005} {USE_PACKETS} {1};set_instance_parameter_value {crosser_005} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_005} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_005} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_005} {USE_ERROR} {0};set_instance_parameter_value {crosser_005} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_005} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_006} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_006} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_006} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_006} {USE_PACKETS} {1};set_instance_parameter_value {crosser_006} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_006} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_006} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_006} {USE_ERROR} {0};set_instance_parameter_value {crosser_006} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_006} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_007} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_007} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_007} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_007} {USE_PACKETS} {1};set_instance_parameter_value {crosser_007} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_007} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_007} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_007} {USE_ERROR} {0};set_instance_parameter_value {crosser_007} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_007} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_008} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_008} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_008} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_008} {USE_PACKETS} {1};set_instance_parameter_value {crosser_008} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_008} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_008} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_008} {USE_ERROR} {0};set_instance_parameter_value {crosser_008} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_008} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_009} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_009} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_009} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_009} {USE_PACKETS} {1};set_instance_parameter_value {crosser_009} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_009} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_009} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_009} {USE_ERROR} {0};set_instance_parameter_value {crosser_009} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_009} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_010} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_010} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_010} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_010} {USE_PACKETS} {1};set_instance_parameter_value {crosser_010} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_010} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_010} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_010} {USE_ERROR} {0};set_instance_parameter_value {crosser_010} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_010} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_011} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_011} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_011} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_011} {USE_PACKETS} {1};set_instance_parameter_value {crosser_011} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_011} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_011} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_011} {USE_ERROR} {0};set_instance_parameter_value {crosser_011} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_011} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_012} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_012} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_012} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_012} {USE_PACKETS} {1};set_instance_parameter_value {crosser_012} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_012} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_012} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_012} {USE_ERROR} {0};set_instance_parameter_value {crosser_012} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_012} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_013} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_013} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_013} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_013} {USE_PACKETS} {1};set_instance_parameter_value {crosser_013} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_013} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_013} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_013} {USE_ERROR} {0};set_instance_parameter_value {crosser_013} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_013} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {USE_OUTPUT_PIPELINE} {0};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_soft_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ext_flash_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ext_flash_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ext_flash_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ext_flash_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ext_flash_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {eth_tse_reset_connection_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_avl_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ddr3_ram_afi_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {150000000};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ext_flash_clock_bridge_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {0};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {msgdma_tx_mm_read_translator.avalon_universal_master_0} {msgdma_tx_mm_read_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {defaultConnection} {false};add_connection {rsp_mux_002.src} {msgdma_tx_mm_read_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_002.src/msgdma_tx_mm_read_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_mm_write_translator.avalon_universal_master_0} {msgdma_rx_mm_write_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {defaultConnection} {false};add_connection {rsp_mux_003.src} {msgdma_rx_mm_write_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_003.src/msgdma_rx_mm_write_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_004.src} {msgdma_tx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_004.src/msgdma_tx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_005.src} {msgdma_rx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_005.src/msgdma_rx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_006.src} {msgdma_tx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_006.src/msgdma_tx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_007.src} {msgdma_rx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_007.src/msgdma_rx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {ddr3_ram_avl_agent.m0} {ddr3_ram_avl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ddr3_ram_avl_agent.rf_source} {ddr3_ram_avl_agent_rsp_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rsp_fifo.out} {ddr3_ram_avl_agent.rf_sink} {avalon_streaming};add_connection {ddr3_ram_avl_agent.rdata_fifo_src} {ddr3_ram_avl_agent_rdata_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rdata_fifo.out} {ddr3_ram_avl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {ddr3_ram_avl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/ddr3_ram_avl_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_csr_agent.m0} {ext_flash_avl_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_csr_agent.rf_source} {ext_flash_avl_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rsp_fifo.out} {ext_flash_avl_csr_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_csr_agent.rdata_fifo_src} {ext_flash_avl_csr_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rdata_fifo.out} {ext_flash_avl_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {ext_flash_avl_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/ext_flash_avl_csr_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_mem_agent.m0} {ext_flash_avl_mem_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_mem_agent.rf_source} {ext_flash_avl_mem_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rsp_fifo.out} {ext_flash_avl_mem_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_mem_agent.rdata_fifo_src} {ext_flash_avl_mem_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rdata_fifo.out} {ext_flash_avl_mem_agent.rdata_fifo_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.m0} {eth_tse_control_port_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {eth_tse_control_port_agent.rf_source} {eth_tse_control_port_agent_rsp_fifo.in} {avalon_streaming};add_connection {eth_tse_control_port_agent_rsp_fifo.out} {eth_tse_control_port_agent.rf_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.rdata_fifo_src} {eth_tse_control_port_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {eth_tse_control_port_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/eth_tse_control_port_agent.cp} {qsys_mm.command};add_connection {sysid_control_slave_agent.m0} {sysid_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_control_slave_agent.rf_source} {sysid_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_control_slave_agent_rsp_fifo.out} {sysid_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_control_slave_agent.rdata_fifo_src} {sysid_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sysid_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sysid_control_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_csr_agent.m0} {msgdma_tx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_csr_agent.rf_source} {msgdma_tx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_csr_agent_rsp_fifo.out} {msgdma_tx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_csr_agent.rdata_fifo_src} {msgdma_tx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {msgdma_tx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/msgdma_tx_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_csr_agent.m0} {msgdma_rx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_csr_agent.rf_source} {msgdma_rx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_csr_agent_rsp_fifo.out} {msgdma_rx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_csr_agent.rdata_fifo_src} {msgdma_rx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {msgdma_rx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/msgdma_rx_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_csr_agent.m0} {onchip_flash_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_csr_agent.rf_source} {onchip_flash_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_csr_agent_rsp_fifo.out} {onchip_flash_csr_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_csr_agent.rdata_fifo_src} {onchip_flash_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_flash_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_flash_csr_agent.cp} {qsys_mm.command};add_connection {udp_generator_csr_agent.m0} {udp_generator_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {udp_generator_csr_agent.rf_source} {udp_generator_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {udp_generator_csr_agent_rsp_fifo.out} {udp_generator_csr_agent.rf_sink} {avalon_streaming};add_connection {udp_generator_csr_agent.rdata_fifo_src} {udp_generator_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {udp_generator_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/udp_generator_csr_agent.cp} {qsys_mm.command};add_connection {sensor_interface_csr_agent.m0} {sensor_interface_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_csr_agent.rf_source} {sensor_interface_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {sensor_interface_csr_agent_rsp_fifo.out} {sensor_interface_csr_agent.rf_sink} {avalon_streaming};add_connection {sensor_interface_csr_agent.rdata_fifo_src} {sensor_interface_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {sensor_interface_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/sensor_interface_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_data_agent.m0} {onchip_flash_data_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_data_agent.rf_source} {onchip_flash_data_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_data_agent_rsp_fifo.out} {onchip_flash_data_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_data_agent.rdata_fifo_src} {onchip_flash_data_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {onchip_flash_data_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/onchip_flash_data_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_prefetcher_csr_agent.m0} {msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_prefetcher_csr_agent.rf_source} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_tx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_tx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {msgdma_tx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/msgdma_tx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_prefetcher_csr_agent.m0} {msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_prefetcher_csr_agent.rf_source} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_rx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_rx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {msgdma_rx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/msgdma_rx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {descriptor_memory_s1_agent.m0} {descriptor_memory_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {descriptor_memory_s1_agent.rf_source} {descriptor_memory_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {descriptor_memory_s1_agent_rsp_fifo.out} {descriptor_memory_s1_agent.rf_sink} {avalon_streaming};add_connection {descriptor_memory_s1_agent.rdata_fifo_src} {descriptor_memory_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {descriptor_memory_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/descriptor_memory_s1_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_015.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_015.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {output_pio_s1_agent.m0} {output_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {output_pio_s1_agent.rf_source} {output_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {output_pio_s1_agent_rsp_fifo.out} {output_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {output_pio_s1_agent.rdata_fifo_src} {output_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_016.src} {output_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_016.src/output_pio_s1_agent.cp} {qsys_mm.command};add_connection {button_pio_s1_agent.m0} {button_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {button_pio_s1_agent.rf_source} {button_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {button_pio_s1_agent_rsp_fifo.out} {button_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {button_pio_s1_agent.rdata_fifo_src} {button_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_017.src} {button_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_017.src/button_pio_s1_agent.cp} {qsys_mm.command};add_connection {debug_uart_s1_agent.m0} {debug_uart_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {debug_uart_s1_agent.rf_source} {debug_uart_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {debug_uart_s1_agent_rsp_fifo.out} {debug_uart_s1_agent.rf_sink} {avalon_streaming};add_connection {debug_uart_s1_agent.rdata_fifo_src} {debug_uart_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_018.src} {debug_uart_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_018.src/debug_uart_s1_agent.cp} {qsys_mm.command};add_connection {frame_timer_s1_agent.m0} {frame_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {frame_timer_s1_agent.rf_source} {frame_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {frame_timer_s1_agent_rsp_fifo.out} {frame_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {frame_timer_s1_agent.rdata_fifo_src} {frame_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_019.src} {frame_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_019.src/frame_timer_s1_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_agent.m0} {calibration_ram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {calibration_ram_s1_agent.rf_source} {calibration_ram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {calibration_ram_s1_agent_rsp_fifo.out} {calibration_ram_s1_agent.rf_sink} {avalon_streaming};add_connection {calibration_ram_s1_agent.rdata_fifo_src} {calibration_ram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {msgdma_tx_mm_read_agent.cp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_mm_read_agent.cp/router_002.sink} {qsys_mm.command};add_connection {router_002.src} {cmd_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/cmd_demux_002.sink} {qsys_mm.command};add_connection {msgdma_rx_mm_write_agent.cp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_mm_write_agent.cp/router_003.sink} {qsys_mm.command};add_connection {router_003.src} {cmd_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/cmd_demux_003.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_read_master_agent.cp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_read_master_agent.cp/router_004.sink} {qsys_mm.command};add_connection {router_004.src} {cmd_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/cmd_demux_004.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_read_master_agent.cp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_read_master_agent.cp/router_005.sink} {qsys_mm.command};add_connection {router_005.src} {cmd_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/cmd_demux_005.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_write_master_agent.cp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_write_master_agent.cp/router_006.sink} {qsys_mm.command};add_connection {router_006.src} {cmd_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/cmd_demux_006.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_write_master_agent.cp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_write_master_agent.cp/router_007.sink} {qsys_mm.command};add_connection {router_007.src} {cmd_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/cmd_demux_007.sink} {qsys_mm.command};add_connection {ddr3_ram_avl_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {ddr3_ram_avl_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux.sink} {qsys_mm.response};add_connection {ext_flash_avl_csr_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_csr_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {ext_flash_avl_mem_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {eth_tse_control_port_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {eth_tse_control_port_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sysid_control_slave_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sysid_control_slave_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {msgdma_tx_csr_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_csr_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {msgdma_rx_csr_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_csr_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_flash_csr_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_csr_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {udp_generator_csr_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {udp_generator_csr_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {sensor_interface_csr_agent.rp} {router_017.sink} {avalon_streaming};preview_set_connection_tag {sensor_interface_csr_agent.rp/router_017.sink} {qsys_mm.response};add_connection {router_017.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_017.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {onchip_flash_data_agent.rp} {router_018.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_data_agent.rp/router_018.sink} {qsys_mm.response};add_connection {router_018.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_018.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_019.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_019.sink} {qsys_mm.response};add_connection {router_019.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_019.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {msgdma_tx_prefetcher_csr_agent.rp} {router_020.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_prefetcher_csr_agent.rp/router_020.sink} {qsys_mm.response};add_connection {router_020.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_020.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {msgdma_rx_prefetcher_csr_agent.rp} {router_021.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_prefetcher_csr_agent.rp/router_021.sink} {qsys_mm.response};add_connection {router_021.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_021.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {descriptor_memory_s1_agent.rp} {router_022.sink} {avalon_streaming};preview_set_connection_tag {descriptor_memory_s1_agent.rp/router_022.sink} {qsys_mm.response};add_connection {router_022.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_022.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_023.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_023.sink} {qsys_mm.response};add_connection {router_023.src} {rsp_demux_015.sink} {avalon_streaming};preview_set_connection_tag {router_023.src/rsp_demux_015.sink} {qsys_mm.response};add_connection {output_pio_s1_agent.rp} {router_024.sink} {avalon_streaming};preview_set_connection_tag {output_pio_s1_agent.rp/router_024.sink} {qsys_mm.response};add_connection {router_024.src} {rsp_demux_016.sink} {avalon_streaming};preview_set_connection_tag {router_024.src/rsp_demux_016.sink} {qsys_mm.response};add_connection {button_pio_s1_agent.rp} {router_025.sink} {avalon_streaming};preview_set_connection_tag {button_pio_s1_agent.rp/router_025.sink} {qsys_mm.response};add_connection {router_025.src} {rsp_demux_017.sink} {avalon_streaming};preview_set_connection_tag {router_025.src/rsp_demux_017.sink} {qsys_mm.response};add_connection {debug_uart_s1_agent.rp} {router_026.sink} {avalon_streaming};preview_set_connection_tag {debug_uart_s1_agent.rp/router_026.sink} {qsys_mm.response};add_connection {router_026.src} {rsp_demux_018.sink} {avalon_streaming};preview_set_connection_tag {router_026.src/rsp_demux_018.sink} {qsys_mm.response};add_connection {frame_timer_s1_agent.rp} {router_027.sink} {avalon_streaming};preview_set_connection_tag {frame_timer_s1_agent.rp/router_027.sink} {qsys_mm.response};add_connection {router_027.src} {rsp_demux_019.sink} {avalon_streaming};preview_set_connection_tag {router_027.src/rsp_demux_019.sink} {qsys_mm.response};add_connection {calibration_ram_s1_agent.rp} {router_028.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_agent.rp/router_028.sink} {qsys_mm.response};add_connection {router.src} {cpu_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/cpu_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {cpu_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_data_master_limiter.rsp_src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.rsp_src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {cpu_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cpu_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {cpu_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_instruction_master_limiter.rsp_src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.rsp_src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_mux_002.src} {ext_flash_avl_mem_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/ext_flash_avl_mem_burst_adapter.sink0} {qsys_mm.command};add_connection {ext_flash_avl_mem_burst_adapter.source0} {ext_flash_avl_mem_agent.cp} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_burst_adapter.source0/ext_flash_avl_mem_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_burst_adapter.source0} {calibration_ram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_burst_adapter.source0/calibration_ram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/cmd_mux_014.sink0} {qsys_mm.command};add_connection {cmd_demux.src15} {cmd_mux_015.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src15/cmd_mux_015.sink0} {qsys_mm.command};add_connection {cmd_demux.src16} {cmd_mux_016.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src16/cmd_mux_016.sink0} {qsys_mm.command};add_connection {cmd_demux.src17} {cmd_mux_017.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src17/cmd_mux_017.sink0} {qsys_mm.command};add_connection {cmd_demux.src18} {cmd_mux_018.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src18/cmd_mux_018.sink0} {qsys_mm.command};add_connection {cmd_demux.src19} {cmd_mux_019.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src19/cmd_mux_019.sink0} {qsys_mm.command};add_connection {cmd_demux.src20} {cmd_mux_020.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src20/cmd_mux_020.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {cmd_mux_010.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/cmd_mux_010.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src3} {cmd_mux_011.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src3/cmd_mux_011.sink1} {qsys_mm.command};add_connection {cmd_demux_004.src0} {cmd_mux_014.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_004.src0/cmd_mux_014.sink1} {qsys_mm.command};add_connection {cmd_demux_005.src0} {cmd_mux_014.sink2} {avalon_streaming};preview_set_connection_tag {cmd_demux_005.src0/cmd_mux_014.sink2} {qsys_mm.command};add_connection {cmd_demux_006.src0} {cmd_mux_014.sink3} {avalon_streaming};preview_set_connection_tag {cmd_demux_006.src0/cmd_mux_014.sink3} {qsys_mm.command};add_connection {cmd_demux_007.src0} {cmd_mux_014.sink4} {avalon_streaming};preview_set_connection_tag {cmd_demux_007.src0/cmd_mux_014.sink4} {qsys_mm.command};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_010.src1} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src1/rsp_mux_001.sink2} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_011.src1} {rsp_mux_001.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src1/rsp_mux_001.sink3} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {rsp_demux_014.src0} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/rsp_mux.sink14} {qsys_mm.response};add_connection {rsp_demux_014.src1} {rsp_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src1/rsp_mux_004.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src2} {rsp_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src2/rsp_mux_005.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src3} {rsp_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src3/rsp_mux_006.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src4} {rsp_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src4/rsp_mux_007.sink0} {qsys_mm.response};add_connection {rsp_demux_015.src0} {rsp_mux.sink15} {avalon_streaming};preview_set_connection_tag {rsp_demux_015.src0/rsp_mux.sink15} {qsys_mm.response};add_connection {rsp_demux_016.src0} {rsp_mux.sink16} {avalon_streaming};preview_set_connection_tag {rsp_demux_016.src0/rsp_mux.sink16} {qsys_mm.response};add_connection {rsp_demux_017.src0} {rsp_mux.sink17} {avalon_streaming};preview_set_connection_tag {rsp_demux_017.src0/rsp_mux.sink17} {qsys_mm.response};add_connection {rsp_demux_018.src0} {rsp_mux.sink18} {avalon_streaming};preview_set_connection_tag {rsp_demux_018.src0/rsp_mux.sink18} {qsys_mm.response};add_connection {rsp_demux_019.src0} {rsp_mux.sink19} {avalon_streaming};preview_set_connection_tag {rsp_demux_019.src0/rsp_mux.sink19} {qsys_mm.response};add_connection {rsp_demux_020.src0} {rsp_mux.sink20} {avalon_streaming};preview_set_connection_tag {rsp_demux_020.src0/rsp_mux.sink20} {qsys_mm.response};add_connection {router_028.src} {calibration_ram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_028.src/calibration_ram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {calibration_ram_s1_rsp_width_adapter.src} {rsp_demux_020.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_rsp_width_adapter.src/rsp_demux_020.sink} {qsys_mm.response};add_connection {cmd_mux_020.src} {calibration_ram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_020.src/calibration_ram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {calibration_ram_s1_cmd_width_adapter.src} {calibration_ram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_cmd_width_adapter.src/calibration_ram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {cmd_demux.src0} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/crosser_002.in} {qsys_mm.command};add_connection {crosser_002.out} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_002.out/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/crosser_003.in} {qsys_mm.command};add_connection {crosser_003.out} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_003.out/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {crosser_004.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/crosser_004.in} {qsys_mm.command};add_connection {crosser_004.out} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {crosser_004.out/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_002.src0} {crosser_005.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_002.src0/crosser_005.in} {qsys_mm.command};add_connection {crosser_005.out} {cmd_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_005.out/cmd_mux.sink2} {qsys_mm.command};add_connection {cmd_demux_003.src0} {crosser_006.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_003.src0/crosser_006.in} {qsys_mm.command};add_connection {crosser_006.out} {cmd_mux.sink3} {avalon_streaming};preview_set_connection_tag {crosser_006.out/cmd_mux.sink3} {qsys_mm.command};add_connection {rsp_demux.src0} {crosser_007.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/crosser_007.in} {qsys_mm.response};add_connection {crosser_007.out} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser_007.out/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {crosser_008.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/crosser_008.in} {qsys_mm.response};add_connection {crosser_008.out} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_008.out/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux.src2} {crosser_009.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src2/crosser_009.in} {qsys_mm.response};add_connection {crosser_009.out} {rsp_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_009.out/rsp_mux_002.sink0} {qsys_mm.response};add_connection {rsp_demux.src3} {crosser_010.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src3/crosser_010.in} {qsys_mm.response};add_connection {crosser_010.out} {rsp_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {crosser_010.out/rsp_mux_003.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {crosser_011.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/crosser_011.in} {qsys_mm.response};add_connection {crosser_011.out} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_011.out/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {crosser_012.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/crosser_012.in} {qsys_mm.response};add_connection {crosser_012.out} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_012.out/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {crosser_013.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/crosser_013.in} {qsys_mm.response};add_connection {crosser_013.out} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {crosser_013.out/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {cpu_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_021.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_025.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_026.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_027.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_028.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_burst_adapter.cr0_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_004.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_005.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_006.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_007.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_008.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_009.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_010.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_011.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_012.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_013.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_burst_adapter.cr0_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_004.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_011.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_012.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_013.in_clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_022.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_023.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_024.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_016.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_016.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_translator.reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rsp_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rdata_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_005.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_006.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_007.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_008.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_009.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_010.in_clk_reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_021.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_022.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_023.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_024.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_025.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_026.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_027.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_028.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_burst_adapter.cr0} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_rsp_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_cmd_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_004.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_005.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_006.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_007.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_008.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_009.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_010.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_011.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_012.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_013.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_reset_connection_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rsp_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rdata_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_005.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_006.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_007.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_008.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_009.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_010.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_soft_reset_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator_reset_reset_bridge.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_burst_adapter.cr0} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_004.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_011.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_012.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_013.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_reset_reset_bridge.clk} {clock};add_interface {ddr3_ram_afi_clk} {clock} {slave};set_interface_property {ddr3_ram_afi_clk} {EXPORT_OF} {ddr3_ram_afi_clk_clock_bridge.in_clk};add_interface {ext_flash_clock_bridge_out_clk} {clock} {slave};set_interface_property {ext_flash_clock_bridge_out_clk} {EXPORT_OF} {ext_flash_clock_bridge_out_clk_clock_bridge.in_clk};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_avl_translator_reset_reset_bridge.in_reset};add_interface {ddr3_ram_soft_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_soft_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_soft_reset_reset_bridge.in_reset};add_interface {eth_tse_reset_connection_reset_bridge_in_reset} {reset} {slave};set_interface_property {eth_tse_reset_connection_reset_bridge_in_reset} {EXPORT_OF} {eth_tse_reset_connection_reset_bridge.in_reset};add_interface {ext_flash_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ext_flash_reset_reset_bridge_in_reset} {EXPORT_OF} {ext_flash_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_read_master} {EXPORT_OF} {msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_write_master} {EXPORT_OF} {msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_mm_write} {avalon} {slave};set_interface_property {msgdma_rx_mm_write} {EXPORT_OF} {msgdma_rx_mm_write_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_read_master} {EXPORT_OF} {msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_write_master} {EXPORT_OF} {msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_mm_read} {avalon} {slave};set_interface_property {msgdma_tx_mm_read} {EXPORT_OF} {msgdma_tx_mm_read_translator.avalon_anti_master_0};add_interface {button_pio_s1} {avalon} {master};set_interface_property {button_pio_s1} {EXPORT_OF} {button_pio_s1_translator.avalon_anti_slave_0};add_interface {calibration_ram_s1} {avalon} {master};set_interface_property {calibration_ram_s1} {EXPORT_OF} {calibration_ram_s1_translator.avalon_anti_slave_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {ddr3_ram_avl} {avalon} {master};set_interface_property {ddr3_ram_avl} {EXPORT_OF} {ddr3_ram_avl_translator.avalon_anti_slave_0};add_interface {debug_uart_s1} {avalon} {master};set_interface_property {debug_uart_s1} {EXPORT_OF} {debug_uart_s1_translator.avalon_anti_slave_0};add_interface {descriptor_memory_s1} {avalon} {master};set_interface_property {descriptor_memory_s1} {EXPORT_OF} {descriptor_memory_s1_translator.avalon_anti_slave_0};add_interface {eth_tse_control_port} {avalon} {master};set_interface_property {eth_tse_control_port} {EXPORT_OF} {eth_tse_control_port_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_csr} {avalon} {master};set_interface_property {ext_flash_avl_csr} {EXPORT_OF} {ext_flash_avl_csr_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_mem} {avalon} {master};set_interface_property {ext_flash_avl_mem} {EXPORT_OF} {ext_flash_avl_mem_translator.avalon_anti_slave_0};add_interface {frame_timer_s1} {avalon} {master};set_interface_property {frame_timer_s1} {EXPORT_OF} {frame_timer_s1_translator.avalon_anti_slave_0};add_interface {msgdma_rx_csr} {avalon} {master};set_interface_property {msgdma_rx_csr} {EXPORT_OF} {msgdma_rx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_rx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_rx_prefetcher_csr} {EXPORT_OF} {msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_csr} {avalon} {master};set_interface_property {msgdma_tx_csr} {EXPORT_OF} {msgdma_tx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_tx_prefetcher_csr} {EXPORT_OF} {msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_csr} {avalon} {master};set_interface_property {onchip_flash_csr} {EXPORT_OF} {onchip_flash_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_data} {avalon} {master};set_interface_property {onchip_flash_data} {EXPORT_OF} {onchip_flash_data_translator.avalon_anti_slave_0};add_interface {output_pio_s1} {avalon} {master};set_interface_property {output_pio_s1} {EXPORT_OF} {output_pio_s1_translator.avalon_anti_slave_0};add_interface {sensor_interface_csr} {avalon} {master};set_interface_property {sensor_interface_csr} {EXPORT_OF} {sensor_interface_csr_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};add_interface {sysid_control_slave} {avalon} {master};set_interface_property {sysid_control_slave} {EXPORT_OF} {sysid_control_slave_translator.avalon_anti_slave_0};add_interface {udp_generator_csr} {avalon} {master};set_interface_property {udp_generator_csr} {EXPORT_OF} {udp_generator_csr_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.button_pio.s1} {0};set_module_assignment {interconnect_id.calibration_ram.s1} {1};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {2};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.ddr3_ram.avl} {3};set_module_assignment {interconnect_id.debug_uart.s1} {4};set_module_assignment {interconnect_id.descriptor_memory.s1} {5};set_module_assignment {interconnect_id.eth_tse.control_port} {6};set_module_assignment {interconnect_id.ext_flash.avl_csr} {7};set_module_assignment {interconnect_id.ext_flash.avl_mem} {8};set_module_assignment {interconnect_id.frame_timer.s1} {9};set_module_assignment {interconnect_id.msgdma_rx.csr} {10};set_module_assignment {interconnect_id.msgdma_rx.descriptor_read_master} {2};set_module_assignment {interconnect_id.msgdma_rx.descriptor_write_master} {3};set_module_assignment {interconnect_id.msgdma_rx.mm_write} {4};set_module_assignment {interconnect_id.msgdma_rx.prefetcher_csr} {11};set_module_assignment {interconnect_id.msgdma_tx.csr} {12};set_module_assignment {interconnect_id.msgdma_tx.descriptor_read_master} {5};set_module_assignment {interconnect_id.msgdma_tx.descriptor_write_master} {6};set_module_assignment {interconnect_id.msgdma_tx.mm_read} {7};set_module_assignment {interconnect_id.msgdma_tx.prefetcher_csr} {13};set_module_assignment {interconnect_id.onchip_flash.csr} {14};set_module_assignment {interconnect_id.onchip_flash.data} {15};set_module_assignment {interconnect_id.output_pio.s1} {16};set_module_assignment {interconnect_id.sensor_interface.csr} {17};set_module_assignment {interconnect_id.sys_clk_timer.s1} {18};set_module_assignment {interconnect_id.sysid.control_slave} {19};set_module_assignment {interconnect_id.udp_generator.csr} {20};(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=1,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=1,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=28,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=28,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=1,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=1)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=1,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=1)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=25,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=3,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=32,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=150000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=5,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=1,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=24,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=7,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=1,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=1,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=9,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=1,AV_WRITE_WAIT_CYCLES=1,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=1,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=0,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=1,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=2,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=19,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=4,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=6,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=1,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=1,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=11,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=2,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=0,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=1,AV_WRITE_WAIT_CYCLES=1,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=1,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;7&quot;
+   name=&quot;ext_flash_avl_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d20&quot;
+   end=&quot;0x00000000018403d40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;6&quot;
+   name=&quot;eth_tse_control_port_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403000&quot;
+   end=&quot;0x00000000018403400&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;19&quot;
+   name=&quot;sysid_control_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d68&quot;
+   end=&quot;0x00000000018403d70&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;12&quot;
+   name=&quot;msgdma_tx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d00&quot;
+   end=&quot;0x00000000018403d20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;10&quot;
+   name=&quot;msgdma_rx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ce0&quot;
+   end=&quot;0x00000000018403d00&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;14&quot;
+   name=&quot;onchip_flash_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d60&quot;
+   end=&quot;0x00000000018403d68&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;20&quot;
+   name=&quot;udp_generator_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403cc0&quot;
+   end=&quot;0x00000000018403ce0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;17&quot;
+   name=&quot;sensor_interface_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d50&quot;
+   end=&quot;0x00000000018403d60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;13&quot;
+   name=&quot;msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ca0&quot;
+   end=&quot;0x00000000018403cc0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;11&quot;
+   name=&quot;msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c80&quot;
+   end=&quot;0x00000000018403ca0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;18&quot;
+   name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c60&quot;
+   end=&quot;0x00000000018403c80&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;16&quot;
+   name=&quot;output_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c40&quot;
+   end=&quot;0x00000000018403c60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;0&quot;
+   name=&quot;button_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d40&quot;
+   end=&quot;0x00000000018403d50&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;4&quot;
+   name=&quot;debug_uart_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c20&quot;
+   end=&quot;0x00000000018403c40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;9&quot;
+   name=&quot;frame_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c00&quot;
+   end=&quot;0x00000000018403c20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;1&quot;
+   name=&quot;calibration_ram_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403400&quot;
+   end=&quot;0x00000000018403800&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=1,BURSTWRAP_VALUE=3,CACHE_VALUE=0,ID=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=7,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=5,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=2,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=6,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=1,USE_WRITERESPONSE=1)(altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=3,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=1,USE_WRITERESPONSE=1)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=3,MAX_BURSTWRAP=511,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=33,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=3,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=64,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=1,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=7,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=9,AV_LINEWRAPBURSTS=1,ECC_ENABLE=0,ID=8,MAX_BURSTWRAP=255,MAX_BYTE_CNT=256,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=6,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=19,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=12,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=10,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=14,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=20,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=17,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=6,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=15,MAX_BURSTWRAP=511,MAX_BYTE_CNT=32,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=2,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=13,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=11,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=5,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=18,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=16,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=0,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=4,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=9,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=2,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=511,MAX_BYTE_CNT=2,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_BEGIN_BURST=78,PKT_BURSTWRAP_H=70,PKT_BURSTWRAP_L=62,PKT_BURST_SIZE_H=73,PKT_BURST_SIZE_L=71,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=61,PKT_BYTE_CNT_L=53,PKT_DATA_H=15,PKT_DATA_L=0,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_ORI_BURST_SIZE_H=102,PKT_ORI_BURST_SIZE_L=100,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_RESPONSE_STATUS_H=99,PKT_RESPONSE_STATUS_L=98,PKT_SRC_ID_H=84,PKT_SRC_ID_L=80,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=47,PKT_TRANS_LOCK=51,PKT_TRANS_POSTED=48,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=103,SUPPRESS_0_BYTEEN_CMD=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=104,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_router:19.1:CHANNEL_ID=000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SLAVES_INFO=3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read)(altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,2,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18403000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18402800,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,7,4,END_ADDRESS=0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=00001,00010,00100,01000,10000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,5,2,6,3,END_ADDRESS=0x0,0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,SLAVES_INFO=0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write,write)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=103,TYPE_OF_TRANSACTION=both)(altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21)(altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21)(altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=3,BURSTWRAP_CONST_VALUE=3,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=87,OUT_BYTE_CNT_H=79,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,ST_CHANNEL_W=21,ST_DATA_W=121)(altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=511,BURSTWRAP_CONST_VALUE=511,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=70,OUT_BYTE_CNT_H=54,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_BEGIN_BURST=78,PKT_BURSTWRAP_H=70,PKT_BURSTWRAP_L=62,PKT_BURST_SIZE_H=73,PKT_BURST_SIZE_L=71,PKT_BURST_TYPE_H=75,PKT_BURST_TYPE_L=74,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=61,PKT_BYTE_CNT_L=53,PKT_TRANS_COMPRESSED_READ=47,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,ST_CHANNEL_W=21,ST_DATA_W=103)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=21,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=5,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=150000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=5,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=21,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=46,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=70,IN_PKT_BURSTWRAP_L=62,IN_PKT_BURST_SIZE_H=73,IN_PKT_BURST_SIZE_L=71,IN_PKT_BURST_TYPE_H=75,IN_PKT_BURST_TYPE_L=74,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=61,IN_PKT_BYTE_CNT_L=53,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=102,IN_PKT_ORI_BURST_SIZE_L=100,IN_PKT_RESPONSE_STATUS_H=99,IN_PKT_RESPONSE_STATUS_L=98,IN_PKT_TRANS_COMPRESSED_READ=47,IN_PKT_TRANS_EXCLUSIVE=52,IN_PKT_TRANS_WRITE=49,IN_ST_DATA_W=103,OPTIMIZE_FOR_RSP=1,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=64,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=91,OUT_PKT_BURST_SIZE_L=89,OUT_PKT_BURST_TYPE_H=93,OUT_PKT_BURST_TYPE_L=92,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=79,OUT_PKT_BYTE_CNT_L=71,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=120,OUT_PKT_ORI_BURST_SIZE_L=118,OUT_PKT_RESPONSE_STATUS_H=117,OUT_PKT_RESPONSE_STATUS_L=116,OUT_PKT_TRANS_COMPRESSED_READ=65,OUT_PKT_TRANS_EXCLUSIVE=70,OUT_ST_DATA_W=121,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=21)(altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),IN_PKT_ADDR_H=64,IN_PKT_ADDR_L=36,IN_PKT_BURSTWRAP_H=88,IN_PKT_BURSTWRAP_L=80,IN_PKT_BURST_SIZE_H=91,IN_PKT_BURST_SIZE_L=89,IN_PKT_BURST_TYPE_H=93,IN_PKT_BURST_TYPE_L=92,IN_PKT_BYTEEN_H=35,IN_PKT_BYTEEN_L=32,IN_PKT_BYTE_CNT_H=79,IN_PKT_BYTE_CNT_L=71,IN_PKT_DATA_H=31,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=120,IN_PKT_ORI_BURST_SIZE_L=118,IN_PKT_RESPONSE_STATUS_H=117,IN_PKT_RESPONSE_STATUS_L=116,IN_PKT_TRANS_COMPRESSED_READ=65,IN_PKT_TRANS_EXCLUSIVE=70,IN_PKT_TRANS_WRITE=67,IN_ST_DATA_W=121,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),OUT_PKT_ADDR_H=46,OUT_PKT_ADDR_L=18,OUT_PKT_BURST_SIZE_H=73,OUT_PKT_BURST_SIZE_L=71,OUT_PKT_BURST_TYPE_H=75,OUT_PKT_BURST_TYPE_L=74,OUT_PKT_BYTEEN_H=17,OUT_PKT_BYTEEN_L=16,OUT_PKT_BYTE_CNT_H=61,OUT_PKT_BYTE_CNT_L=53,OUT_PKT_DATA_H=15,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=102,OUT_PKT_ORI_BURST_SIZE_L=100,OUT_PKT_RESPONSE_STATUS_H=99,OUT_PKT_RESPONSE_STATUS_L=98,OUT_PKT_TRANS_COMPRESSED_READ=47,OUT_PKT_TRANS_EXCLUSIVE=52,OUT_ST_DATA_W=103,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=21)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=150000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=150000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=50000000,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=150000000,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)"
+   instancePathKey="q_sys:.:mm_interconnect_1"
+   kind="altera_mm_interconnect"
+   version="19.1"
+   name="q_sys_mm_interconnect_1">
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter
+     name="COMPOSE_CONTENTS"
+     value="add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_instruction_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_mm_read_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_mm_write_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {ddr3_ram_avl_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_W} {25};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READ} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINBURSTTRANSFER} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_LOCK} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_mem_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_W} {24};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_W} {7};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {eth_tse_control_port_translator} {altera_merlin_slave_translator};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READLATENCY} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READ} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITE} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_ADDRESS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_LOCK} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {eth_tse_control_port_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sysid_control_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READ} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sysid_control_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sysid_control_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {udp_generator_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READ} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {udp_generator_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {udp_generator_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_data_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_W} {19};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_data_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_data_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_debug_mem_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READ} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {descriptor_memory_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_W} {11};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READ} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sys_clk_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {output_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {output_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {output_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {output_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {output_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {button_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {button_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {button_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {button_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {button_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {debug_uart_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {debug_uart_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READ} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINTRANSFER} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {debug_uart_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {debug_uart_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {frame_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {frame_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {frame_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {frame_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {calibration_ram_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_data_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_data_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;7&quot;
+   name=&quot;ext_flash_avl_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d20&quot;
+   end=&quot;0x00000000018403d40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;6&quot;
+   name=&quot;eth_tse_control_port_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403000&quot;
+   end=&quot;0x00000000018403400&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;19&quot;
+   name=&quot;sysid_control_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d68&quot;
+   end=&quot;0x00000000018403d70&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;12&quot;
+   name=&quot;msgdma_tx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d00&quot;
+   end=&quot;0x00000000018403d20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;10&quot;
+   name=&quot;msgdma_rx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ce0&quot;
+   end=&quot;0x00000000018403d00&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;14&quot;
+   name=&quot;onchip_flash_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d60&quot;
+   end=&quot;0x00000000018403d68&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;20&quot;
+   name=&quot;udp_generator_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403cc0&quot;
+   end=&quot;0x00000000018403ce0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;17&quot;
+   name=&quot;sensor_interface_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d50&quot;
+   end=&quot;0x00000000018403d60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;13&quot;
+   name=&quot;msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ca0&quot;
+   end=&quot;0x00000000018403cc0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;11&quot;
+   name=&quot;msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c80&quot;
+   end=&quot;0x00000000018403ca0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;18&quot;
+   name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c60&quot;
+   end=&quot;0x00000000018403c80&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;16&quot;
+   name=&quot;output_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c40&quot;
+   end=&quot;0x00000000018403c60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;0&quot;
+   name=&quot;button_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d40&quot;
+   end=&quot;0x00000000018403d50&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;4&quot;
+   name=&quot;debug_uart_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c20&quot;
+   end=&quot;0x00000000018403c40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;9&quot;
+   name=&quot;frame_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c00&quot;
+   end=&quot;0x00000000018403c20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;1&quot;
+   name=&quot;calibration_ram_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403400&quot;
+   end=&quot;0x00000000018403800&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_mm_read_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ID} {7};set_instance_parameter_value {msgdma_tx_mm_read_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_mm_read_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_mm_write_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ID} {4};set_instance_parameter_value {msgdma_rx_mm_write_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_mm_write_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ID} {5};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ID} {2};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ID} {6};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {msgdma_rx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ID} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {ddr3_ram_avl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_DATA_W} {121};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ddr3_ram_avl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ddr3_ram_avl_agent} {ID} {3};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {ECC_ENABLE} {0};add_instance {ddr3_ram_avl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {FIFO_DEPTH} {33};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ddr3_ram_avl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {FIFO_DEPTH} {64};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ext_flash_avl_csr_agent} {ID} {7};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BYTE_CNT} {256};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BURSTWRAP} {255};set_instance_parameter_value {ext_flash_avl_mem_agent} {ID} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_mem_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {eth_tse_control_port_agent} {altera_merlin_slave_agent};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_H} {31};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_L} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {eth_tse_control_port_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {eth_tse_control_port_agent} {ST_DATA_W} {121};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {eth_tse_control_port_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {eth_tse_control_port_agent} {ID} {6};set_instance_parameter_value {eth_tse_control_port_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {ECC_ENABLE} {0};add_instance {eth_tse_control_port_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_control_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sysid_control_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sysid_control_slave_agent} {ID} {19};set_instance_parameter_value {sysid_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_csr_agent} {ID} {12};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_csr_agent} {ID} {10};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_csr_agent} {ID} {14};set_instance_parameter_value {onchip_flash_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {udp_generator_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {udp_generator_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {udp_generator_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {udp_generator_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {udp_generator_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {udp_generator_csr_agent} {ID} {20};set_instance_parameter_value {udp_generator_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {ECC_ENABLE} {0};add_instance {udp_generator_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sensor_interface_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sensor_interface_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sensor_interface_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sensor_interface_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sensor_interface_csr_agent} {ID} {17};set_instance_parameter_value {sensor_interface_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {ECC_ENABLE} {0};add_instance {sensor_interface_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_data_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_data_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_data_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_data_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_data_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BYTE_CNT} {32};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_data_agent} {ID} {15};set_instance_parameter_value {onchip_flash_data_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_data_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ID} {13};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ID} {11};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {descriptor_memory_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {descriptor_memory_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {descriptor_memory_s1_agent} {ID} {5};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {ECC_ENABLE} {0};add_instance {descriptor_memory_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {18};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {output_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {output_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {output_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {output_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {output_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {output_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {output_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {output_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {output_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {output_pio_s1_agent} {ID} {16};set_instance_parameter_value {output_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {ECC_ENABLE} {0};add_instance {output_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {button_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {button_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {button_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {button_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {button_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {button_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {button_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {button_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {button_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {button_pio_s1_agent} {ID} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {ECC_ENABLE} {0};add_instance {button_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {debug_uart_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {debug_uart_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {debug_uart_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {debug_uart_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {debug_uart_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {debug_uart_s1_agent} {ID} {4};set_instance_parameter_value {debug_uart_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {ECC_ENABLE} {0};add_instance {debug_uart_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {frame_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {frame_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {frame_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {frame_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {frame_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {frame_timer_s1_agent} {ID} {9};set_instance_parameter_value {frame_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {ECC_ENABLE} {0};add_instance {frame_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {calibration_ram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_LOCK} {51};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_H} {93};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_L} {91};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_POSTED} {48};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_H} {84};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_L} {80};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_H} {89};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_L} {85};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {calibration_ram_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_agent} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {calibration_ram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {calibration_ram_s1_agent} {ID} {1};set_instance_parameter_value {calibration_ram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {ECC_ENABLE} {0};add_instance {calibration_ram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {104};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 8 15 5 2 6 1 9 4 16 18 11 13 20 10 12 7 0 17 14 19 };set_instance_parameter_value {router} {CHANNEL_ID} {000000000000000000001 000000000000000000100 000000000010000000000 000000100000000000000 000000000100000000000 000000000000000001000 100000000000000000000 010000000000000000000 001000000000000000000 000010000000000000000 000001000000000000000 000000010000000000000 000000001000000000000 000000000000100000000 000000000000001000000 000000000000000100000 000000000000000000010 000100000000000000000 000000000001000000000 000000000000010000000 000000000000000010000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both both both both both both both both both both read both both read };set_instance_parameter_value {router} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18400000 0x18402800 0x18403000 0x18403400 0x18403c00 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 };set_instance_parameter_value {router} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18402000 0x18403000 0x18403400 0x18403800 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 0x18403d70 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {121};set_instance_parameter_value {router} {ST_CHANNEL_W} {21};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {3 8 15 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18402800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18403000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {121};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {3 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {121};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_002} {DECODER_TYPE} {0};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {3 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {64};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_003} {ST_DATA_W} {121};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_003} {DECODER_TYPE} {0};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {5 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {64};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_004} {ST_DATA_W} {121};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_004} {DECODER_TYPE} {0};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {5 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {64};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_005} {ST_DATA_W} {121};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_005} {DECODER_TYPE} {0};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {5 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {64};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_006} {ST_DATA_W} {121};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_006} {DECODER_TYPE} {0};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {5 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {64};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_007} {ST_DATA_W} {121};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_007} {DECODER_TYPE} {0};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 1 7 4 };set_instance_parameter_value {router_008} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both read read write };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {64};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_008} {ST_DATA_W} {121};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {64};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_009} {ST_DATA_W} {121};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_010} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {64};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_010} {ST_DATA_W} {121};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {64};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_011} {ST_DATA_W} {121};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {64};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_012} {ST_DATA_W} {121};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {64};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_013} {ST_DATA_W} {121};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {64};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_014} {ST_DATA_W} {121};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {64};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_015} {ST_DATA_W} {121};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {64};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_016} {ST_DATA_W} {121};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {router_017} {altera_merlin_router};set_instance_parameter_value {router_017} {DESTINATION_ID} {0 };set_instance_parameter_value {router_017} {CHANNEL_ID} {1 };set_instance_parameter_value {router_017} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_017} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_017} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_017} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_017} {SPAN_OFFSET} {};set_instance_parameter_value {router_017} {PKT_ADDR_H} {64};set_instance_parameter_value {router_017} {PKT_ADDR_L} {36};set_instance_parameter_value {router_017} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_017} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_017} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_017} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_017} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_017} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_017} {ST_DATA_W} {121};set_instance_parameter_value {router_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_017} {DECODER_TYPE} {1};set_instance_parameter_value {router_017} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_017} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_017} {MEMORY_ALIASING_DECODE} {0};add_instance {router_018} {altera_merlin_router};set_instance_parameter_value {router_018} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_018} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_018} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_018} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_018} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_018} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_018} {SPAN_OFFSET} {};set_instance_parameter_value {router_018} {PKT_ADDR_H} {64};set_instance_parameter_value {router_018} {PKT_ADDR_L} {36};set_instance_parameter_value {router_018} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_018} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_018} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_018} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_018} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_018} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_018} {ST_DATA_W} {121};set_instance_parameter_value {router_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_018} {DECODER_TYPE} {1};set_instance_parameter_value {router_018} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_018} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_018} {MEMORY_ALIASING_DECODE} {0};add_instance {router_019} {altera_merlin_router};set_instance_parameter_value {router_019} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_019} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_019} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_019} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_019} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_019} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_019} {SPAN_OFFSET} {};set_instance_parameter_value {router_019} {PKT_ADDR_H} {64};set_instance_parameter_value {router_019} {PKT_ADDR_L} {36};set_instance_parameter_value {router_019} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_019} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_019} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_019} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_019} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_019} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_019} {ST_DATA_W} {121};set_instance_parameter_value {router_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_019} {DECODER_TYPE} {1};set_instance_parameter_value {router_019} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_019} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_019} {MEMORY_ALIASING_DECODE} {0};add_instance {router_020} {altera_merlin_router};set_instance_parameter_value {router_020} {DESTINATION_ID} {0 };set_instance_parameter_value {router_020} {CHANNEL_ID} {1 };set_instance_parameter_value {router_020} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_020} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_020} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_020} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_020} {SPAN_OFFSET} {};set_instance_parameter_value {router_020} {PKT_ADDR_H} {64};set_instance_parameter_value {router_020} {PKT_ADDR_L} {36};set_instance_parameter_value {router_020} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_020} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_020} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_020} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_020} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_020} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_020} {ST_DATA_W} {121};set_instance_parameter_value {router_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_020} {DECODER_TYPE} {1};set_instance_parameter_value {router_020} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_020} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_020} {MEMORY_ALIASING_DECODE} {0};add_instance {router_021} {altera_merlin_router};set_instance_parameter_value {router_021} {DESTINATION_ID} {0 };set_instance_parameter_value {router_021} {CHANNEL_ID} {1 };set_instance_parameter_value {router_021} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_021} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_021} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_021} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_021} {SPAN_OFFSET} {};set_instance_parameter_value {router_021} {PKT_ADDR_H} {64};set_instance_parameter_value {router_021} {PKT_ADDR_L} {36};set_instance_parameter_value {router_021} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_021} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_021} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_021} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_021} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_021} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_021} {ST_DATA_W} {121};set_instance_parameter_value {router_021} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_021} {DECODER_TYPE} {1};set_instance_parameter_value {router_021} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_021} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_021} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_021} {MEMORY_ALIASING_DECODE} {0};add_instance {router_022} {altera_merlin_router};set_instance_parameter_value {router_022} {DESTINATION_ID} {0 5 2 6 3 };set_instance_parameter_value {router_022} {CHANNEL_ID} {00001 00010 00100 01000 10000 };set_instance_parameter_value {router_022} {TYPE_OF_TRANSACTION} {both read read write write };set_instance_parameter_value {router_022} {START_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {END_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {NON_SECURED_TAG} {1 1 1 1 1 };set_instance_parameter_value {router_022} {SECURED_RANGE_PAIRS} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SECURED_RANGE_LIST} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SPAN_OFFSET} {};set_instance_parameter_value {router_022} {PKT_ADDR_H} {64};set_instance_parameter_value {router_022} {PKT_ADDR_L} {36};set_instance_parameter_value {router_022} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_022} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_022} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_022} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_022} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_022} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_022} {ST_DATA_W} {121};set_instance_parameter_value {router_022} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_022} {DECODER_TYPE} {1};set_instance_parameter_value {router_022} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_022} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_022} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_022} {MEMORY_ALIASING_DECODE} {0};add_instance {router_023} {altera_merlin_router};set_instance_parameter_value {router_023} {DESTINATION_ID} {0 };set_instance_parameter_value {router_023} {CHANNEL_ID} {1 };set_instance_parameter_value {router_023} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_023} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_023} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_023} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_023} {SPAN_OFFSET} {};set_instance_parameter_value {router_023} {PKT_ADDR_H} {64};set_instance_parameter_value {router_023} {PKT_ADDR_L} {36};set_instance_parameter_value {router_023} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_023} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_023} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_023} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_023} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_023} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_023} {ST_DATA_W} {121};set_instance_parameter_value {router_023} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_023} {DECODER_TYPE} {1};set_instance_parameter_value {router_023} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_023} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_023} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_023} {MEMORY_ALIASING_DECODE} {0};add_instance {router_024} {altera_merlin_router};set_instance_parameter_value {router_024} {DESTINATION_ID} {0 };set_instance_parameter_value {router_024} {CHANNEL_ID} {1 };set_instance_parameter_value {router_024} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_024} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_024} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_024} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_024} {SPAN_OFFSET} {};set_instance_parameter_value {router_024} {PKT_ADDR_H} {64};set_instance_parameter_value {router_024} {PKT_ADDR_L} {36};set_instance_parameter_value {router_024} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_024} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_024} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_024} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_024} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_024} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_024} {ST_DATA_W} {121};set_instance_parameter_value {router_024} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_024} {DECODER_TYPE} {1};set_instance_parameter_value {router_024} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_024} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_024} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_024} {MEMORY_ALIASING_DECODE} {0};add_instance {router_025} {altera_merlin_router};set_instance_parameter_value {router_025} {DESTINATION_ID} {0 };set_instance_parameter_value {router_025} {CHANNEL_ID} {1 };set_instance_parameter_value {router_025} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_025} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_025} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_025} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_025} {SPAN_OFFSET} {};set_instance_parameter_value {router_025} {PKT_ADDR_H} {64};set_instance_parameter_value {router_025} {PKT_ADDR_L} {36};set_instance_parameter_value {router_025} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_025} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_025} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_025} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_025} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_025} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_025} {ST_DATA_W} {121};set_instance_parameter_value {router_025} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_025} {DECODER_TYPE} {1};set_instance_parameter_value {router_025} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_025} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_025} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_025} {MEMORY_ALIASING_DECODE} {0};add_instance {router_026} {altera_merlin_router};set_instance_parameter_value {router_026} {DESTINATION_ID} {0 };set_instance_parameter_value {router_026} {CHANNEL_ID} {1 };set_instance_parameter_value {router_026} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_026} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_026} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_026} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_026} {SPAN_OFFSET} {};set_instance_parameter_value {router_026} {PKT_ADDR_H} {64};set_instance_parameter_value {router_026} {PKT_ADDR_L} {36};set_instance_parameter_value {router_026} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_026} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_026} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_026} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_026} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_026} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_026} {ST_DATA_W} {121};set_instance_parameter_value {router_026} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_026} {DECODER_TYPE} {1};set_instance_parameter_value {router_026} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_026} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_026} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_026} {MEMORY_ALIASING_DECODE} {0};add_instance {router_027} {altera_merlin_router};set_instance_parameter_value {router_027} {DESTINATION_ID} {0 };set_instance_parameter_value {router_027} {CHANNEL_ID} {1 };set_instance_parameter_value {router_027} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_027} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_027} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_027} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_027} {SPAN_OFFSET} {};set_instance_parameter_value {router_027} {PKT_ADDR_H} {64};set_instance_parameter_value {router_027} {PKT_ADDR_L} {36};set_instance_parameter_value {router_027} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_027} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_027} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_027} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_027} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_027} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_027} {ST_DATA_W} {121};set_instance_parameter_value {router_027} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_027} {DECODER_TYPE} {1};set_instance_parameter_value {router_027} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_027} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_027} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_027} {MEMORY_ALIASING_DECODE} {0};add_instance {router_028} {altera_merlin_router};set_instance_parameter_value {router_028} {DESTINATION_ID} {0 };set_instance_parameter_value {router_028} {CHANNEL_ID} {1 };set_instance_parameter_value {router_028} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_028} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_028} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_028} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_028} {SPAN_OFFSET} {};set_instance_parameter_value {router_028} {PKT_ADDR_H} {46};set_instance_parameter_value {router_028} {PKT_ADDR_L} {18};set_instance_parameter_value {router_028} {PKT_PROTECTION_H} {93};set_instance_parameter_value {router_028} {PKT_PROTECTION_L} {91};set_instance_parameter_value {router_028} {PKT_DEST_ID_H} {89};set_instance_parameter_value {router_028} {PKT_DEST_ID_L} {85};set_instance_parameter_value {router_028} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {router_028} {PKT_TRANS_READ} {50};set_instance_parameter_value {router_028} {ST_DATA_W} {103};set_instance_parameter_value {router_028} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_028} {DECODER_TYPE} {1};set_instance_parameter_value {router_028} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_028} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_028} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_028} {MEMORY_ALIASING_DECODE} {0};add_instance {cpu_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_data_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_limiter} {REORDER} {0};add_instance {cpu_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_limiter} {REORDER} {0};add_instance {ext_flash_avl_mem_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BURSTWRAP_H} {87};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_MASK} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_VALUE} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {calibration_ram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BYTE_CNT_H} {54};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {21};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {4};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {4};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {5};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 1 1 1 1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_015} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_015} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_015} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_015} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_015} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_015} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_016} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_016} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_016} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_016} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_016} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_016} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_017} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_017} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_017} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_017} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_017} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_017} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_018} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_018} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_018} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_018} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_018} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_018} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_019} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_019} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_019} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_019} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_019} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_019} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_020} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_020} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_020} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_020} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_020} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_020} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {4};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {5};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_015} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_015} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_015} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_015} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_016} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_016} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_016} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_016} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_017} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_017} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_017} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_017} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_018} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_018} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_018} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_018} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_019} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_019} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_019} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_019} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_020} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_020} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_020} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_020} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {21};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {4};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {calibration_ram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {calibration_ram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {67};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {88};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {80};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {121};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_004} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_004} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_004} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_004} {USE_PACKETS} {1};set_instance_parameter_value {crosser_004} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_004} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_004} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_004} {USE_ERROR} {0};set_instance_parameter_value {crosser_004} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_004} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_005} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_005} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_005} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_005} {USE_PACKETS} {1};set_instance_parameter_value {crosser_005} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_005} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_005} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_005} {USE_ERROR} {0};set_instance_parameter_value {crosser_005} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_005} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_006} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_006} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_006} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_006} {USE_PACKETS} {1};set_instance_parameter_value {crosser_006} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_006} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_006} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_006} {USE_ERROR} {0};set_instance_parameter_value {crosser_006} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_006} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_007} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_007} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_007} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_007} {USE_PACKETS} {1};set_instance_parameter_value {crosser_007} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_007} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_007} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_007} {USE_ERROR} {0};set_instance_parameter_value {crosser_007} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_007} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_008} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_008} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_008} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_008} {USE_PACKETS} {1};set_instance_parameter_value {crosser_008} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_008} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_008} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_008} {USE_ERROR} {0};set_instance_parameter_value {crosser_008} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_008} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_009} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_009} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_009} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_009} {USE_PACKETS} {1};set_instance_parameter_value {crosser_009} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_009} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_009} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_009} {USE_ERROR} {0};set_instance_parameter_value {crosser_009} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_009} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_010} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_010} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_010} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_010} {USE_PACKETS} {1};set_instance_parameter_value {crosser_010} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_010} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_010} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_010} {USE_ERROR} {0};set_instance_parameter_value {crosser_010} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_010} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_011} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_011} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_011} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_011} {USE_PACKETS} {1};set_instance_parameter_value {crosser_011} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_011} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_011} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_011} {USE_ERROR} {0};set_instance_parameter_value {crosser_011} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_011} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_012} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_012} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_012} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_012} {USE_PACKETS} {1};set_instance_parameter_value {crosser_012} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_012} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_012} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_012} {USE_ERROR} {0};set_instance_parameter_value {crosser_012} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_012} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_013} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_013} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_013} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_013} {USE_PACKETS} {1};set_instance_parameter_value {crosser_013} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_013} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_013} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_013} {USE_ERROR} {0};set_instance_parameter_value {crosser_013} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_013} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {USE_OUTPUT_PIPELINE} {0};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_soft_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ext_flash_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ext_flash_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ext_flash_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ext_flash_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ext_flash_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {eth_tse_reset_connection_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_avl_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ddr3_ram_afi_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {150000000};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ext_flash_clock_bridge_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {0};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {msgdma_tx_mm_read_translator.avalon_universal_master_0} {msgdma_tx_mm_read_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {defaultConnection} {false};add_connection {rsp_mux_002.src} {msgdma_tx_mm_read_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_002.src/msgdma_tx_mm_read_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_mm_write_translator.avalon_universal_master_0} {msgdma_rx_mm_write_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {defaultConnection} {false};add_connection {rsp_mux_003.src} {msgdma_rx_mm_write_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_003.src/msgdma_rx_mm_write_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_004.src} {msgdma_tx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_004.src/msgdma_tx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_005.src} {msgdma_rx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_005.src/msgdma_rx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_006.src} {msgdma_tx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_006.src/msgdma_tx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_007.src} {msgdma_rx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_007.src/msgdma_rx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {ddr3_ram_avl_agent.m0} {ddr3_ram_avl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ddr3_ram_avl_agent.rf_source} {ddr3_ram_avl_agent_rsp_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rsp_fifo.out} {ddr3_ram_avl_agent.rf_sink} {avalon_streaming};add_connection {ddr3_ram_avl_agent.rdata_fifo_src} {ddr3_ram_avl_agent_rdata_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rdata_fifo.out} {ddr3_ram_avl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {ddr3_ram_avl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/ddr3_ram_avl_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_csr_agent.m0} {ext_flash_avl_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_csr_agent.rf_source} {ext_flash_avl_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rsp_fifo.out} {ext_flash_avl_csr_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_csr_agent.rdata_fifo_src} {ext_flash_avl_csr_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rdata_fifo.out} {ext_flash_avl_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {ext_flash_avl_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/ext_flash_avl_csr_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_mem_agent.m0} {ext_flash_avl_mem_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_mem_agent.rf_source} {ext_flash_avl_mem_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rsp_fifo.out} {ext_flash_avl_mem_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_mem_agent.rdata_fifo_src} {ext_flash_avl_mem_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rdata_fifo.out} {ext_flash_avl_mem_agent.rdata_fifo_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.m0} {eth_tse_control_port_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {eth_tse_control_port_agent.rf_source} {eth_tse_control_port_agent_rsp_fifo.in} {avalon_streaming};add_connection {eth_tse_control_port_agent_rsp_fifo.out} {eth_tse_control_port_agent.rf_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.rdata_fifo_src} {eth_tse_control_port_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {eth_tse_control_port_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/eth_tse_control_port_agent.cp} {qsys_mm.command};add_connection {sysid_control_slave_agent.m0} {sysid_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_control_slave_agent.rf_source} {sysid_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_control_slave_agent_rsp_fifo.out} {sysid_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_control_slave_agent.rdata_fifo_src} {sysid_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sysid_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sysid_control_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_csr_agent.m0} {msgdma_tx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_csr_agent.rf_source} {msgdma_tx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_csr_agent_rsp_fifo.out} {msgdma_tx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_csr_agent.rdata_fifo_src} {msgdma_tx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {msgdma_tx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/msgdma_tx_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_csr_agent.m0} {msgdma_rx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_csr_agent.rf_source} {msgdma_rx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_csr_agent_rsp_fifo.out} {msgdma_rx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_csr_agent.rdata_fifo_src} {msgdma_rx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {msgdma_rx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/msgdma_rx_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_csr_agent.m0} {onchip_flash_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_csr_agent.rf_source} {onchip_flash_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_csr_agent_rsp_fifo.out} {onchip_flash_csr_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_csr_agent.rdata_fifo_src} {onchip_flash_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_flash_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_flash_csr_agent.cp} {qsys_mm.command};add_connection {udp_generator_csr_agent.m0} {udp_generator_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {udp_generator_csr_agent.rf_source} {udp_generator_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {udp_generator_csr_agent_rsp_fifo.out} {udp_generator_csr_agent.rf_sink} {avalon_streaming};add_connection {udp_generator_csr_agent.rdata_fifo_src} {udp_generator_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {udp_generator_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/udp_generator_csr_agent.cp} {qsys_mm.command};add_connection {sensor_interface_csr_agent.m0} {sensor_interface_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_csr_agent.rf_source} {sensor_interface_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {sensor_interface_csr_agent_rsp_fifo.out} {sensor_interface_csr_agent.rf_sink} {avalon_streaming};add_connection {sensor_interface_csr_agent.rdata_fifo_src} {sensor_interface_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {sensor_interface_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/sensor_interface_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_data_agent.m0} {onchip_flash_data_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_data_agent.rf_source} {onchip_flash_data_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_data_agent_rsp_fifo.out} {onchip_flash_data_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_data_agent.rdata_fifo_src} {onchip_flash_data_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {onchip_flash_data_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/onchip_flash_data_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_prefetcher_csr_agent.m0} {msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_prefetcher_csr_agent.rf_source} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_tx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_tx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {msgdma_tx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/msgdma_tx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_prefetcher_csr_agent.m0} {msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_prefetcher_csr_agent.rf_source} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_rx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_rx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {msgdma_rx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/msgdma_rx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {descriptor_memory_s1_agent.m0} {descriptor_memory_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {descriptor_memory_s1_agent.rf_source} {descriptor_memory_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {descriptor_memory_s1_agent_rsp_fifo.out} {descriptor_memory_s1_agent.rf_sink} {avalon_streaming};add_connection {descriptor_memory_s1_agent.rdata_fifo_src} {descriptor_memory_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {descriptor_memory_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/descriptor_memory_s1_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_015.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_015.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {output_pio_s1_agent.m0} {output_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {output_pio_s1_agent.rf_source} {output_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {output_pio_s1_agent_rsp_fifo.out} {output_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {output_pio_s1_agent.rdata_fifo_src} {output_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_016.src} {output_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_016.src/output_pio_s1_agent.cp} {qsys_mm.command};add_connection {button_pio_s1_agent.m0} {button_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {button_pio_s1_agent.rf_source} {button_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {button_pio_s1_agent_rsp_fifo.out} {button_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {button_pio_s1_agent.rdata_fifo_src} {button_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_017.src} {button_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_017.src/button_pio_s1_agent.cp} {qsys_mm.command};add_connection {debug_uart_s1_agent.m0} {debug_uart_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {debug_uart_s1_agent.rf_source} {debug_uart_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {debug_uart_s1_agent_rsp_fifo.out} {debug_uart_s1_agent.rf_sink} {avalon_streaming};add_connection {debug_uart_s1_agent.rdata_fifo_src} {debug_uart_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_018.src} {debug_uart_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_018.src/debug_uart_s1_agent.cp} {qsys_mm.command};add_connection {frame_timer_s1_agent.m0} {frame_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {frame_timer_s1_agent.rf_source} {frame_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {frame_timer_s1_agent_rsp_fifo.out} {frame_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {frame_timer_s1_agent.rdata_fifo_src} {frame_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_019.src} {frame_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_019.src/frame_timer_s1_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_agent.m0} {calibration_ram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {calibration_ram_s1_agent.rf_source} {calibration_ram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {calibration_ram_s1_agent_rsp_fifo.out} {calibration_ram_s1_agent.rf_sink} {avalon_streaming};add_connection {calibration_ram_s1_agent.rdata_fifo_src} {calibration_ram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {msgdma_tx_mm_read_agent.cp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_mm_read_agent.cp/router_002.sink} {qsys_mm.command};add_connection {router_002.src} {cmd_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/cmd_demux_002.sink} {qsys_mm.command};add_connection {msgdma_rx_mm_write_agent.cp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_mm_write_agent.cp/router_003.sink} {qsys_mm.command};add_connection {router_003.src} {cmd_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/cmd_demux_003.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_read_master_agent.cp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_read_master_agent.cp/router_004.sink} {qsys_mm.command};add_connection {router_004.src} {cmd_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/cmd_demux_004.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_read_master_agent.cp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_read_master_agent.cp/router_005.sink} {qsys_mm.command};add_connection {router_005.src} {cmd_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/cmd_demux_005.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_write_master_agent.cp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_write_master_agent.cp/router_006.sink} {qsys_mm.command};add_connection {router_006.src} {cmd_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/cmd_demux_006.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_write_master_agent.cp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_write_master_agent.cp/router_007.sink} {qsys_mm.command};add_connection {router_007.src} {cmd_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/cmd_demux_007.sink} {qsys_mm.command};add_connection {ddr3_ram_avl_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {ddr3_ram_avl_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux.sink} {qsys_mm.response};add_connection {ext_flash_avl_csr_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_csr_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {ext_flash_avl_mem_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {eth_tse_control_port_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {eth_tse_control_port_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sysid_control_slave_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sysid_control_slave_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {msgdma_tx_csr_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_csr_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {msgdma_rx_csr_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_csr_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_flash_csr_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_csr_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {udp_generator_csr_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {udp_generator_csr_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {sensor_interface_csr_agent.rp} {router_017.sink} {avalon_streaming};preview_set_connection_tag {sensor_interface_csr_agent.rp/router_017.sink} {qsys_mm.response};add_connection {router_017.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_017.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {onchip_flash_data_agent.rp} {router_018.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_data_agent.rp/router_018.sink} {qsys_mm.response};add_connection {router_018.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_018.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_019.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_019.sink} {qsys_mm.response};add_connection {router_019.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_019.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {msgdma_tx_prefetcher_csr_agent.rp} {router_020.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_prefetcher_csr_agent.rp/router_020.sink} {qsys_mm.response};add_connection {router_020.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_020.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {msgdma_rx_prefetcher_csr_agent.rp} {router_021.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_prefetcher_csr_agent.rp/router_021.sink} {qsys_mm.response};add_connection {router_021.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_021.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {descriptor_memory_s1_agent.rp} {router_022.sink} {avalon_streaming};preview_set_connection_tag {descriptor_memory_s1_agent.rp/router_022.sink} {qsys_mm.response};add_connection {router_022.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_022.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_023.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_023.sink} {qsys_mm.response};add_connection {router_023.src} {rsp_demux_015.sink} {avalon_streaming};preview_set_connection_tag {router_023.src/rsp_demux_015.sink} {qsys_mm.response};add_connection {output_pio_s1_agent.rp} {router_024.sink} {avalon_streaming};preview_set_connection_tag {output_pio_s1_agent.rp/router_024.sink} {qsys_mm.response};add_connection {router_024.src} {rsp_demux_016.sink} {avalon_streaming};preview_set_connection_tag {router_024.src/rsp_demux_016.sink} {qsys_mm.response};add_connection {button_pio_s1_agent.rp} {router_025.sink} {avalon_streaming};preview_set_connection_tag {button_pio_s1_agent.rp/router_025.sink} {qsys_mm.response};add_connection {router_025.src} {rsp_demux_017.sink} {avalon_streaming};preview_set_connection_tag {router_025.src/rsp_demux_017.sink} {qsys_mm.response};add_connection {debug_uart_s1_agent.rp} {router_026.sink} {avalon_streaming};preview_set_connection_tag {debug_uart_s1_agent.rp/router_026.sink} {qsys_mm.response};add_connection {router_026.src} {rsp_demux_018.sink} {avalon_streaming};preview_set_connection_tag {router_026.src/rsp_demux_018.sink} {qsys_mm.response};add_connection {frame_timer_s1_agent.rp} {router_027.sink} {avalon_streaming};preview_set_connection_tag {frame_timer_s1_agent.rp/router_027.sink} {qsys_mm.response};add_connection {router_027.src} {rsp_demux_019.sink} {avalon_streaming};preview_set_connection_tag {router_027.src/rsp_demux_019.sink} {qsys_mm.response};add_connection {calibration_ram_s1_agent.rp} {router_028.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_agent.rp/router_028.sink} {qsys_mm.response};add_connection {router.src} {cpu_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/cpu_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {cpu_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_data_master_limiter.rsp_src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.rsp_src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {cpu_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cpu_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {cpu_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_instruction_master_limiter.rsp_src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.rsp_src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_mux_002.src} {ext_flash_avl_mem_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/ext_flash_avl_mem_burst_adapter.sink0} {qsys_mm.command};add_connection {ext_flash_avl_mem_burst_adapter.source0} {ext_flash_avl_mem_agent.cp} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_burst_adapter.source0/ext_flash_avl_mem_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_burst_adapter.source0} {calibration_ram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_burst_adapter.source0/calibration_ram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/cmd_mux_014.sink0} {qsys_mm.command};add_connection {cmd_demux.src15} {cmd_mux_015.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src15/cmd_mux_015.sink0} {qsys_mm.command};add_connection {cmd_demux.src16} {cmd_mux_016.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src16/cmd_mux_016.sink0} {qsys_mm.command};add_connection {cmd_demux.src17} {cmd_mux_017.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src17/cmd_mux_017.sink0} {qsys_mm.command};add_connection {cmd_demux.src18} {cmd_mux_018.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src18/cmd_mux_018.sink0} {qsys_mm.command};add_connection {cmd_demux.src19} {cmd_mux_019.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src19/cmd_mux_019.sink0} {qsys_mm.command};add_connection {cmd_demux.src20} {cmd_mux_020.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src20/cmd_mux_020.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {cmd_mux_010.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/cmd_mux_010.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src3} {cmd_mux_011.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src3/cmd_mux_011.sink1} {qsys_mm.command};add_connection {cmd_demux_004.src0} {cmd_mux_014.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_004.src0/cmd_mux_014.sink1} {qsys_mm.command};add_connection {cmd_demux_005.src0} {cmd_mux_014.sink2} {avalon_streaming};preview_set_connection_tag {cmd_demux_005.src0/cmd_mux_014.sink2} {qsys_mm.command};add_connection {cmd_demux_006.src0} {cmd_mux_014.sink3} {avalon_streaming};preview_set_connection_tag {cmd_demux_006.src0/cmd_mux_014.sink3} {qsys_mm.command};add_connection {cmd_demux_007.src0} {cmd_mux_014.sink4} {avalon_streaming};preview_set_connection_tag {cmd_demux_007.src0/cmd_mux_014.sink4} {qsys_mm.command};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_010.src1} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src1/rsp_mux_001.sink2} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_011.src1} {rsp_mux_001.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src1/rsp_mux_001.sink3} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {rsp_demux_014.src0} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/rsp_mux.sink14} {qsys_mm.response};add_connection {rsp_demux_014.src1} {rsp_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src1/rsp_mux_004.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src2} {rsp_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src2/rsp_mux_005.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src3} {rsp_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src3/rsp_mux_006.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src4} {rsp_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src4/rsp_mux_007.sink0} {qsys_mm.response};add_connection {rsp_demux_015.src0} {rsp_mux.sink15} {avalon_streaming};preview_set_connection_tag {rsp_demux_015.src0/rsp_mux.sink15} {qsys_mm.response};add_connection {rsp_demux_016.src0} {rsp_mux.sink16} {avalon_streaming};preview_set_connection_tag {rsp_demux_016.src0/rsp_mux.sink16} {qsys_mm.response};add_connection {rsp_demux_017.src0} {rsp_mux.sink17} {avalon_streaming};preview_set_connection_tag {rsp_demux_017.src0/rsp_mux.sink17} {qsys_mm.response};add_connection {rsp_demux_018.src0} {rsp_mux.sink18} {avalon_streaming};preview_set_connection_tag {rsp_demux_018.src0/rsp_mux.sink18} {qsys_mm.response};add_connection {rsp_demux_019.src0} {rsp_mux.sink19} {avalon_streaming};preview_set_connection_tag {rsp_demux_019.src0/rsp_mux.sink19} {qsys_mm.response};add_connection {rsp_demux_020.src0} {rsp_mux.sink20} {avalon_streaming};preview_set_connection_tag {rsp_demux_020.src0/rsp_mux.sink20} {qsys_mm.response};add_connection {router_028.src} {calibration_ram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_028.src/calibration_ram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {calibration_ram_s1_rsp_width_adapter.src} {rsp_demux_020.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_rsp_width_adapter.src/rsp_demux_020.sink} {qsys_mm.response};add_connection {cmd_mux_020.src} {calibration_ram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_020.src/calibration_ram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {calibration_ram_s1_cmd_width_adapter.src} {calibration_ram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_cmd_width_adapter.src/calibration_ram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {cmd_demux.src0} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/crosser_002.in} {qsys_mm.command};add_connection {crosser_002.out} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_002.out/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/crosser_003.in} {qsys_mm.command};add_connection {crosser_003.out} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_003.out/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {crosser_004.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/crosser_004.in} {qsys_mm.command};add_connection {crosser_004.out} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {crosser_004.out/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_002.src0} {crosser_005.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_002.src0/crosser_005.in} {qsys_mm.command};add_connection {crosser_005.out} {cmd_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_005.out/cmd_mux.sink2} {qsys_mm.command};add_connection {cmd_demux_003.src0} {crosser_006.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_003.src0/crosser_006.in} {qsys_mm.command};add_connection {crosser_006.out} {cmd_mux.sink3} {avalon_streaming};preview_set_connection_tag {crosser_006.out/cmd_mux.sink3} {qsys_mm.command};add_connection {rsp_demux.src0} {crosser_007.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/crosser_007.in} {qsys_mm.response};add_connection {crosser_007.out} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser_007.out/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {crosser_008.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/crosser_008.in} {qsys_mm.response};add_connection {crosser_008.out} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_008.out/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux.src2} {crosser_009.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src2/crosser_009.in} {qsys_mm.response};add_connection {crosser_009.out} {rsp_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_009.out/rsp_mux_002.sink0} {qsys_mm.response};add_connection {rsp_demux.src3} {crosser_010.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src3/crosser_010.in} {qsys_mm.response};add_connection {crosser_010.out} {rsp_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {crosser_010.out/rsp_mux_003.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {crosser_011.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/crosser_011.in} {qsys_mm.response};add_connection {crosser_011.out} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_011.out/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {crosser_012.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/crosser_012.in} {qsys_mm.response};add_connection {crosser_012.out} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_012.out/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {crosser_013.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/crosser_013.in} {qsys_mm.response};add_connection {crosser_013.out} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {crosser_013.out/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {cpu_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_021.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_025.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_026.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_027.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_028.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_burst_adapter.cr0_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_004.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_005.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_006.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_007.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_008.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_009.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_010.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_011.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_012.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_013.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_burst_adapter.cr0_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_004.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_011.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_012.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_013.in_clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_022.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_023.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_024.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_016.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_016.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_translator.reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rsp_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rdata_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_005.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_006.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_007.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_008.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_009.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_010.in_clk_reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_021.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_022.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_023.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_024.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_025.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_026.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_027.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_028.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_burst_adapter.cr0} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_rsp_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_cmd_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_004.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_005.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_006.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_007.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_008.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_009.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_010.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_011.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_012.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_013.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_reset_connection_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rsp_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rdata_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_005.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_006.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_007.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_008.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_009.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_010.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_soft_reset_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator_reset_reset_bridge.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_burst_adapter.cr0} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_004.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_011.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_012.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_013.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_reset_reset_bridge.clk} {clock};add_interface {ddr3_ram_afi_clk} {clock} {slave};set_interface_property {ddr3_ram_afi_clk} {EXPORT_OF} {ddr3_ram_afi_clk_clock_bridge.in_clk};add_interface {ext_flash_clock_bridge_out_clk} {clock} {slave};set_interface_property {ext_flash_clock_bridge_out_clk} {EXPORT_OF} {ext_flash_clock_bridge_out_clk_clock_bridge.in_clk};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_avl_translator_reset_reset_bridge.in_reset};add_interface {ddr3_ram_soft_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_soft_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_soft_reset_reset_bridge.in_reset};add_interface {eth_tse_reset_connection_reset_bridge_in_reset} {reset} {slave};set_interface_property {eth_tse_reset_connection_reset_bridge_in_reset} {EXPORT_OF} {eth_tse_reset_connection_reset_bridge.in_reset};add_interface {ext_flash_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ext_flash_reset_reset_bridge_in_reset} {EXPORT_OF} {ext_flash_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_read_master} {EXPORT_OF} {msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_write_master} {EXPORT_OF} {msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_mm_write} {avalon} {slave};set_interface_property {msgdma_rx_mm_write} {EXPORT_OF} {msgdma_rx_mm_write_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_read_master} {EXPORT_OF} {msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_write_master} {EXPORT_OF} {msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_mm_read} {avalon} {slave};set_interface_property {msgdma_tx_mm_read} {EXPORT_OF} {msgdma_tx_mm_read_translator.avalon_anti_master_0};add_interface {button_pio_s1} {avalon} {master};set_interface_property {button_pio_s1} {EXPORT_OF} {button_pio_s1_translator.avalon_anti_slave_0};add_interface {calibration_ram_s1} {avalon} {master};set_interface_property {calibration_ram_s1} {EXPORT_OF} {calibration_ram_s1_translator.avalon_anti_slave_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {ddr3_ram_avl} {avalon} {master};set_interface_property {ddr3_ram_avl} {EXPORT_OF} {ddr3_ram_avl_translator.avalon_anti_slave_0};add_interface {debug_uart_s1} {avalon} {master};set_interface_property {debug_uart_s1} {EXPORT_OF} {debug_uart_s1_translator.avalon_anti_slave_0};add_interface {descriptor_memory_s1} {avalon} {master};set_interface_property {descriptor_memory_s1} {EXPORT_OF} {descriptor_memory_s1_translator.avalon_anti_slave_0};add_interface {eth_tse_control_port} {avalon} {master};set_interface_property {eth_tse_control_port} {EXPORT_OF} {eth_tse_control_port_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_csr} {avalon} {master};set_interface_property {ext_flash_avl_csr} {EXPORT_OF} {ext_flash_avl_csr_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_mem} {avalon} {master};set_interface_property {ext_flash_avl_mem} {EXPORT_OF} {ext_flash_avl_mem_translator.avalon_anti_slave_0};add_interface {frame_timer_s1} {avalon} {master};set_interface_property {frame_timer_s1} {EXPORT_OF} {frame_timer_s1_translator.avalon_anti_slave_0};add_interface {msgdma_rx_csr} {avalon} {master};set_interface_property {msgdma_rx_csr} {EXPORT_OF} {msgdma_rx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_rx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_rx_prefetcher_csr} {EXPORT_OF} {msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_csr} {avalon} {master};set_interface_property {msgdma_tx_csr} {EXPORT_OF} {msgdma_tx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_tx_prefetcher_csr} {EXPORT_OF} {msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_csr} {avalon} {master};set_interface_property {onchip_flash_csr} {EXPORT_OF} {onchip_flash_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_data} {avalon} {master};set_interface_property {onchip_flash_data} {EXPORT_OF} {onchip_flash_data_translator.avalon_anti_slave_0};add_interface {output_pio_s1} {avalon} {master};set_interface_property {output_pio_s1} {EXPORT_OF} {output_pio_s1_translator.avalon_anti_slave_0};add_interface {sensor_interface_csr} {avalon} {master};set_interface_property {sensor_interface_csr} {EXPORT_OF} {sensor_interface_csr_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};add_interface {sysid_control_slave} {avalon} {master};set_interface_property {sysid_control_slave} {EXPORT_OF} {sysid_control_slave_translator.avalon_anti_slave_0};add_interface {udp_generator_csr} {avalon} {master};set_interface_property {udp_generator_csr} {EXPORT_OF} {udp_generator_csr_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.button_pio.s1} {0};set_module_assignment {interconnect_id.calibration_ram.s1} {1};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {2};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.ddr3_ram.avl} {3};set_module_assignment {interconnect_id.debug_uart.s1} {4};set_module_assignment {interconnect_id.descriptor_memory.s1} {5};set_module_assignment {interconnect_id.eth_tse.control_port} {6};set_module_assignment {interconnect_id.ext_flash.avl_csr} {7};set_module_assignment {interconnect_id.ext_flash.avl_mem} {8};set_module_assignment {interconnect_id.frame_timer.s1} {9};set_module_assignment {interconnect_id.msgdma_rx.csr} {10};set_module_assignment {interconnect_id.msgdma_rx.descriptor_read_master} {2};set_module_assignment {interconnect_id.msgdma_rx.descriptor_write_master} {3};set_module_assignment {interconnect_id.msgdma_rx.mm_write} {4};set_module_assignment {interconnect_id.msgdma_rx.prefetcher_csr} {11};set_module_assignment {interconnect_id.msgdma_tx.csr} {12};set_module_assignment {interconnect_id.msgdma_tx.descriptor_read_master} {5};set_module_assignment {interconnect_id.msgdma_tx.descriptor_write_master} {6};set_module_assignment {interconnect_id.msgdma_tx.mm_read} {7};set_module_assignment {interconnect_id.msgdma_tx.prefetcher_csr} {13};set_module_assignment {interconnect_id.onchip_flash.csr} {14};set_module_assignment {interconnect_id.onchip_flash.data} {15};set_module_assignment {interconnect_id.output_pio.s1} {16};set_module_assignment {interconnect_id.sensor_interface.csr} {17};set_module_assignment {interconnect_id.sys_clk_timer.s1} {18};set_module_assignment {interconnect_id.sysid.control_slave} {19};set_module_assignment {interconnect_id.udp_generator.csr} {20};" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_incr_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_default_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"
+       type="VERILOG" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="mm_interconnect_1" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InitialInterconnectTransform</message>
+   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
+   <message level="Debug">Transform: DefaultSlaveTransform</message>
+   <message level="Debug">Transform: TranslatorTransform</message>
+   <message level="Debug">No Avalon connections, skipping transform </message>
+   <message level="Debug">Transform: IDPadTransform</message>
+   <message level="Debug">Transform: DomainTransform</message>
+   <message level="Debug">Transform: RouterTransform</message>
+   <message level="Debug">Transform: TrafficLimiterTransform</message>
+   <message level="Debug">Transform: BurstTransform</message>
+   <message level="Debug">Transform: TreeTransform</message>
+   <message level="Debug">Transform: NetworkToSwitchTransform</message>
+   <message level="Debug">Transform: WidthTransform</message>
+   <message level="Debug">Transform: RouterTableTransform</message>
+   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
+   <message level="Debug">Transform: ClockCrossingTransform</message>
+   <message level="Debug">Transform: PipelineTransform</message>
+   <message level="Debug">Transform: SpotPipelineTransform</message>
+   <message level="Debug">Transform: PerformanceMonitorTransform</message>
+   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
+   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
+   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
+   <message level="Debug">Transform: HierarchyTransform</message>
+   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.007s/0.008s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.009s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_007">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_007">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_008">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_008">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_009">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_009">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_010">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_010">Timing: COM:3/0.020s/0.048s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_011">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_011">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_012">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.clk_bridge_0">Timing: ELA:1/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_012">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_013">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013.error_adapter_0">Timing: ELA:1/0.004s</message>
+   <message level="Debug" culprit="avalon_st_adapter_013">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_014">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014.error_adapter_0">Timing: ELA:1/0.002s</message>
+   <message level="Debug" culprit="avalon_st_adapter_014">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_015">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_015">Timing: COM:3/0.005s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_016">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_016">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_017">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_017">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_018">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_018">Timing: COM:3/0.006s/0.007s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_019">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_019">Timing: COM:3/0.006s/0.006s</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Info" culprit="avalon_st_adapter_020">Inserting error_adapter: error_adapter_0</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.clk_bridge_0">Timing: ELA:1/0.000s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020.error_adapter_0">Timing: ELA:1/0.003s</message>
+   <message level="Debug" culprit="avalon_st_adapter_020">Timing: COM:3/0.006s/0.006s</message>
+   <message
+       level="Debug"
+       culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>218</b> modules, <b>742</b> connections]]></message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_008</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_022</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_028</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_014</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_014</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_001</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020</b>"]]></message>
+   <message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
+   <message
+       level="Info"
+       culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
+   <message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
+   <message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
+   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
+   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
+   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
+   <message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
+   <message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
+   <message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
+   <message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
+   <message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
+   <message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
+   <message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
+   <message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
+   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
+   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
+   <message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
+   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
+   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
+   <message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
+   <message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
+   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
+   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
+   <message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
+   <message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
+   <message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
+   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
+   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
+   <message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
+   <message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
+   <message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_irq_mapper:19.1:AUTO_DEVICE_FAMILY=MAX 10,IRQ_MAP=0:2,1:3,2:5,3:0,4:4,NUM_RCVRS=5,SENDER_IRQ_WIDTH=32"
+   instancePathKey="q_sys:.:irq_mapper"
+   kind="altera_irq_mapper"
+   version="19.1"
+   name="q_sys_irq_mapper">
+  <parameter name="NUM_RCVRS" value="5" />
+  <parameter name="IRQ_MAP" value="0:2,1:3,2:5,3:0,4:4" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="SENDER_IRQ_WIDTH" value="32" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_irq_mapper.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="irq_mapper" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper"</message>
+   <message level="Info" culprit="irq_mapper"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_irq_clock_crosser:19.1:AUTO_RECEIVER_INTERRUPTS_USED=-1,IRQ_WIDTH=1"
+   instancePathKey="q_sys:.:irq_synchronizer"
+   kind="altera_irq_clock_crosser"
+   version="19.1"
+   name="altera_irq_clock_crosser">
+  <parameter name="IRQ_WIDTH" value="1" />
+  <parameter name="AUTO_RECEIVER_INTERRUPTS_USED" value="-1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_clock_crosser/altera_irq_clock_crosser_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys" as="irq_synchronizer" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser"</message>
+   <message level="Info" culprit="irq_synchronizer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_clock_crosser</b> "<b>irq_synchronizer</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=8,inChannelWidth=0,inDataWidth=32,inEmptyWidth=2,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=1,inUsePackets=1,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=32,outEmptyWidth=2,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=1,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:avalon_st_adapter"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   name="q_sys_avalon_st_adapter">
+  <parameter name="inUseValid" value="1" />
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="outUseEmptyPort" value="1" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="outUseValid" value="1" />
+  <parameter name="outMaxChannel" value="0" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="1" />
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inEmptyWidth" value="2" />
+  <parameter name="inUseReady" value="1" />
+  <parameter name="outReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="outDataWidth" value="32" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter name="inUseEmptyPort" value="1" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="outUseReady" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="inDataWidth" value="32" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="outEmptyWidth" value="2" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="avalon_st_adapter" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=8,inChannelWidth=0,inDataWidth=32,inEmptyWidth=2,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inUseEmptyPort=1,inUsePackets=1,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=32,outEmptyWidth=2,outErrorDescriptor=,outErrorWidth=6,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=1,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(timing_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,inUseValid=true,outReadyLatency=0,outUseReady=true,outUseValid=true)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:avalon_st_adapter_001"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   name="q_sys_avalon_st_adapter_001">
+  <parameter name="inUseValid" value="1" />
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="outUseEmptyPort" value="1" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="outErrorWidth" value="6" />
+  <parameter name="outUseValid" value="1" />
+  <parameter name="outMaxChannel" value="0" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="1" />
+  <parameter name="inErrorWidth" value="6" />
+  <parameter name="inEmptyWidth" value="2" />
+  <parameter name="inUseReady" value="1" />
+  <parameter name="outReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="outDataWidth" value="32" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter name="inUseEmptyPort" value="1" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="outUseReady" value="1" />
+  <parameter name="inReadyLatency" value="2" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="inDataWidth" value="32" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="outEmptyWidth" value="2" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys" as="avalon_st_adapter_001" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>timing_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001_timing_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
+   <message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_reset_controller:19.1:ADAPT_RESET_REQUEST=0,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=1,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=0,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
+   instancePathKey="q_sys:.:rst_controller"
+   kind="altera_reset_controller"
+   version="19.1"
+   name="altera_reset_controller">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.sdc"
+       type="SDC"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys"
+     as="rst_controller,rst_controller_001,rst_controller_002,rst_controller_003,rst_controller_004,rst_controller_005,rst_controller_006" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
+   <message level="Info" culprit="rst_controller"><![CDATA["<b>q_sys</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= &quot;synthesis translate_off&quot; ,translate_on= &quot;synthesis translate_on&quot;  ,userDefinedSettings="
+   instancePathKey="q_sys:.:cpu:.:cpu"
+   kind="altera_nios2_gen2_unit"
+   version="19.1"
+   name="q_sys_cpu_cpu">
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="dcache_size_derived" value="2048" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_top" value="0" />
+  <parameter
+     name="deviceFeaturesSystemInfo"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="tightly_coupled_data_master_0_paddr_top" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave" value="cpu.jtag_debug_module" />
+  <parameter name="setting_branchPredictionType" value="Dynamic" />
+  <parameter name="exceptionOffset" value="288" />
+  <parameter name="flash_instruction_master_paddr_top" value="0" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="cpu_name" value="cpu" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="breakAbsoluteAddr" value="406857760" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="debug_offchiptrace" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="debug_onchiptrace" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="resetAbsoluteAddr" value="335544320" />
+  <parameter name="tightly_coupled_data_master_1_paddr_top" value="0" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="internalIrqMaskSystemInfo" value="61" />
+  <parameter name="instruction_master_paddr_top" value="0" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="exceptionAbsoluteAddr" value="134218016" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="debug_insttrace" value="false" />
+  <parameter name="icache_size" value="2048" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter
+     name="dataSlaveMapParam"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;descriptor_memory.s1&apos; start=&apos;0x18400000&apos; end=&apos;0x18402000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;eth_tse.control_port&apos; start=&apos;0x18403000&apos; end=&apos;0x18403400&apos; type=&apos;altera_eth_tse.control_port&apos; /&gt;&lt;slave name=&apos;calibration_ram.s1&apos; start=&apos;0x18403400&apos; end=&apos;0x18403680&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;frame_timer.s1&apos; start=&apos;0x18403C00&apos; end=&apos;0x18403C20&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;debug_uart.s1&apos; start=&apos;0x18403C20&apos; end=&apos;0x18403C40&apos; type=&apos;altera_avalon_uart.s1&apos; /&gt;&lt;slave name=&apos;output_pio.s1&apos; start=&apos;0x18403C40&apos; end=&apos;0x18403C60&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x18403C60&apos; end=&apos;0x18403C80&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;msgdma_rx.prefetcher_csr&apos; start=&apos;0x18403C80&apos; end=&apos;0x18403CA0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.prefetcher_csr&apos; start=&apos;0x18403CA0&apos; end=&apos;0x18403CC0&apos; type=&apos;altera_msgdma.prefetcher_csr&apos; /&gt;&lt;slave name=&apos;udp_generator.csr&apos; start=&apos;0x18403CC0&apos; end=&apos;0x18403CE0&apos; type=&apos;udp_generator.csr&apos; /&gt;&lt;slave name=&apos;msgdma_rx.csr&apos; start=&apos;0x18403CE0&apos; end=&apos;0x18403D00&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;msgdma_tx.csr&apos; start=&apos;0x18403D00&apos; end=&apos;0x18403D20&apos; type=&apos;altera_msgdma.csr&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_csr&apos; start=&apos;0x18403D20&apos; end=&apos;0x18403D40&apos; type=&apos;altera_generic_quad_spi_controller.avl_csr&apos; /&gt;&lt;slave name=&apos;button_pio.s1&apos; start=&apos;0x18403D40&apos; end=&apos;0x18403D50&apos; type=&apos;altera_avalon_pio.s1&apos; /&gt;&lt;slave name=&apos;sensor_interface.csr&apos; start=&apos;0x18403D50&apos; end=&apos;0x18403D60&apos; type=&apos;sensor_recon.csr&apos; /&gt;&lt;slave name=&apos;onchip_flash.csr&apos; start=&apos;0x18403D60&apos; end=&apos;0x18403D68&apos; type=&apos;altera_onchip_flash.csr&apos; /&gt;&lt;slave name=&apos;sysid.control_slave&apos; start=&apos;0x18403D68&apos; end=&apos;0x18403D70&apos; type=&apos;altera_avalon_sysid_qsys.control_slave&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="stratix_dspblock_shift_mul" value="false" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_top" value="0" />
+  <parameter name="setting_ioregionBypassDCache" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_3_paddr_top" value="0" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_top" value="0" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="data_master_paddr_top" value="0" />
+  <parameter name="translate_on" value=" &quot;synthesis translate_on&quot;  " />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_top" value="0" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="resetSlave" value="ext_flash.avl_mem" />
+  <parameter name="dcache_bursts_derived" value="false" />
+  <parameter name="multiplierType" value="mul_fast32" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="debug_datatrace" value="false" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="debug_hwbreakpoint" value="2" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="tightly_coupled_data_master_2_paddr_top" value="0" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_top" value="0" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_top" value="0" />
+  <parameter name="dcache_lineSize_derived" value="32" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter
+     name="instSlaveMapParam"
+     value="&lt;address-map&gt;&lt;slave name=&apos;ddr3_ram.avl&apos; start=&apos;0x8000000&apos; end=&apos;0x10000000&apos; type=&apos;altera_mem_if_ddr3_emif.avl&apos; /&gt;&lt;slave name=&apos;ext_flash.avl_mem&apos; start=&apos;0x14000000&apos; end=&apos;0x18000000&apos; type=&apos;altera_generic_quad_spi_controller.avl_mem&apos; /&gt;&lt;slave name=&apos;onchip_flash.data&apos; start=&apos;0x18200000&apos; end=&apos;0x18360000&apos; type=&apos;altera_onchip_flash.data&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x18402800&apos; end=&apos;0x18403000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;" />
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="shifterType" value="fast_le_shift" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
+       type="MIF"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp"
+       type="OTHER"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_cpu" as="cpu" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
+   <message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Elaborating CPU configuration settings</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)   Creating all objects for CPU</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Testbench</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)     Instruction decoding</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction fields</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*)       Instruction decodes</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Signals for RTL simulation waveforms</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)       Instruction controls</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline frontend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*)     Pipeline backend</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Generating RTL from CPU objects</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*)   Creating plain-text RTL</message>
+   <message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
+   <message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
+   <message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
+   instancePathKey="q_sys:.:ddr3_ram:.:pll0"
+   kind="altera_mem_if_ddr3_pll"
+   version="19.1"
+   name="q_sys_ddr3_ram_pll0">
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="FLY_BY" value="false" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CALIB_LFIFO_OFFSET" value="4" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
+  <parameter name="IO_DM_OUT_RESERVE" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="DELAY_PER_OPA_TAP" value="416" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="PLL_HR_CLK_DIV" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
+  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="MEM_CLK_NS" value="3.333" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_AFI_CLK_MULT" value="3" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
+  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="PLL_DR_CLK_DIV" value="0" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
+  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
+  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="DLL_MASTER" value="true" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="PLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TB_PLL_DLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
+  <parameter name="PHY_CLKBUF" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="VFIFO_AS_SHIFT_REG" value="true" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_DR_CLK_MULT" value="0" />
+  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="IO_DQS_IN_RESERVE" value="3" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="ENABLE_NIOS_OCI" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="RATE_CACHE" value="Unknown" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TB_RATE" value="HALF" />
+  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT" value="3" />
+  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="VCALIB_COUNT_WIDTH" value="2" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DLL_USE_DR_CLK" value="false" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="PLL_WRITE_CLK_DIV" value="1" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CALIB_VFIFO_OFFSET" value="12" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="TB_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
+  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="REF_CLK_PS" value="10000.0" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
+  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="DQS_PHASE_SHIFT" value="9000" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="IO_IN_DELAY_MAX" value="15" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
+  <parameter name="REGISTER_C2P" value="false" />
+  <parameter name="FAST_SIM_CALIBRATION" value="false" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="DQS_EN_DELAY_MAX" value="7" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
+  <parameter name="REF_CLK_PERIOD_PS" value="10000" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
+  <parameter name="DUAL_WRITE_CLOCK" value="false" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_MULT" value="3" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
+  <parameter name="READ_FIFO_HALF_RATE" value="true" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="GENERIC_PLL" value="false" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="REF_CLK_NS" value="10.0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
+  <parameter name="IO_OUT2_DELAY_MAX" value="7" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_CACHE_VALID" value="true" />
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
+  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="PLL_HR_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="PLL_MEM_CLK_DIV" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="USE_HARD_READ_FIFO" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="PHY_VERSION_NUMBER" value="191" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
+  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
+  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="true" />
+  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_T_WL" value="5" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="MEM_CLK_PS" value="3333.0" />
+  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
+  <parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="IO_OUT1_DELAY_MAX" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="DQS_IN_DELAY_MAX" value="15" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
+  <parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="IO_STANDARD" value="SSTL-15" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="SPEED_GRADE_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="USE_2X_FF" value="false" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
+  <parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="MEM_T_RL" value="5" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="USE_DR_CLK" value="false" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MAX10_RTL_SEQ" value="true" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_DIV" value="2" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_pll/altera_mem_if_ddr3_pll/altera_mem_if_ddr3_pll_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram" as="pll0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
+   <message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
+   instancePathKey="q_sys:.:ddr3_ram:.:p0"
+   kind="altera_mem_if_ddr3_phy_core"
+   version="19.1"
+   name="q_sys_ddr3_ram_p0">
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="FLY_BY" value="false" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CALIB_LFIFO_OFFSET" value="4" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
+  <parameter name="IO_DM_OUT_RESERVE" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="DELAY_PER_OPA_TAP" value="416" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="PLL_HR_CLK_DIV" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
+  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="MEM_CLK_NS" value="3.333" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_AFI_CLK_MULT" value="3" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
+  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="PLL_DR_CLK_DIV" value="0" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
+  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
+  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="DLL_MASTER" value="true" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="PLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TB_PLL_DLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
+  <parameter name="PHY_CLKBUF" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="VFIFO_AS_SHIFT_REG" value="true" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_DR_CLK_MULT" value="0" />
+  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="IO_DQS_IN_RESERVE" value="3" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="ENABLE_NIOS_OCI" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="RATE_CACHE" value="Unknown" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TB_RATE" value="HALF" />
+  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT" value="3" />
+  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="VCALIB_COUNT_WIDTH" value="2" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
+  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DLL_USE_DR_CLK" value="false" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="PLL_WRITE_CLK_DIV" value="1" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CALIB_VFIFO_OFFSET" value="12" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="TB_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
+  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="REF_CLK_PS" value="10000.0" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
+  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="DQS_PHASE_SHIFT" value="9000" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="IO_IN_DELAY_MAX" value="15" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
+  <parameter name="REGISTER_C2P" value="false" />
+  <parameter name="FAST_SIM_CALIBRATION" value="false" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="DQS_EN_DELAY_MAX" value="7" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
+  <parameter name="DUAL_WRITE_CLOCK" value="false" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_MULT" value="3" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
+  <parameter name="READ_FIFO_HALF_RATE" value="true" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="GENERIC_PLL" value="false" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="REF_CLK_NS" value="10.0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
+  <parameter name="IO_OUT2_DELAY_MAX" value="7" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_CACHE_VALID" value="true" />
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
+  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="PLL_HR_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="PLL_MEM_CLK_DIV" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="USE_HARD_READ_FIFO" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="PHY_VERSION_NUMBER" value="191" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
+  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
+  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="true" />
+  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_T_WL" value="5" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="MEM_CLK_PS" value="3333.0" />
+  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
+  <parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="IO_OUT1_DELAY_MAX" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="DQS_IN_DELAY_MAX" value="15" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
+  <parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="IO_STANDARD" value="SSTL-15" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="SPEED_GRADE_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="USE_2X_FF" value="false" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
+  <parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="MEM_T_RL" value="5" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="USE_DR_CLK" value="false" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MAX10_RTL_SEQ" value="true" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_DIV" value="2" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/max10emif_dcfifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc"
+       type="SDC"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing_core.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_map.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_assignments.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_parameters.tcl"
+       type="OTHER"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_phy_core/altera_mem_if_ddr3_phy_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram" as="p0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
+   <message level="Info" culprit="p0">Generating clock pair generator</message>
+   <message level="Info" culprit="p0">Generating altgpio</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
+   <message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0">*****************************</message>
+   <message level="Info" culprit="p0"></message>
+   <message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false"
+   instancePathKey="q_sys:.:ddr3_ram:.:m0"
+   kind="altera_mem_if_ddr3_afi_mux"
+   version="19.1"
+   name="afi_mux_ddr3_ddrx">
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="FLY_BY" value="true" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_mux/altera_mem_if_ddr3_afi_mux_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram" as="m0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
+   <message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
+   instancePathKey="q_sys:.:ddr3_ram:.:s0"
+   kind="altera_mem_if_ddr3_qseq"
+   version="19.1"
+   name="q_sys_ddr3_ram_s0">
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="FLY_BY" value="false" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="CALIB_LFIFO_OFFSET" value="4" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
+  <parameter name="IO_DM_OUT_RESERVE" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="DELAY_PER_OPA_TAP" value="416" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="AVL_DATA_WIDTH" value="32" />
+  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="PLL_HR_CLK_DIV" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
+  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="MEM_CLK_NS" value="3.333" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_AFI_CLK_MULT" value="3" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
+  <parameter name="AFI_MAX_WRITE_LATENCY_COUNT_WIDTH" value="6" />
+  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="PLL_DR_CLK_DIV" value="0" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
+  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
+  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="DLL_MASTER" value="true" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="PLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="TB_PLL_DLL_MASTER" value="true" />
+  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
+  <parameter name="PHY_CLKBUF" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="VFIFO_AS_SHIFT_REG" value="true" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_DR_CLK_MULT" value="0" />
+  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="IO_DQS_IN_RESERVE" value="3" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="ENABLE_NIOS_OCI" value="false" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="RATE_CACHE" value="Unknown" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TB_RATE" value="HALF" />
+  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT" value="3" />
+  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="VCALIB_COUNT_WIDTH" value="2" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
+  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="DLL_USE_DR_CLK" value="false" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="PLL_WRITE_CLK_DIV" value="1" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CALIB_VFIFO_OFFSET" value="12" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="TB_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
+  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="REF_CLK_PS" value="10000.0" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
+  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="DQS_PHASE_SHIFT" value="9000" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="IO_IN_DELAY_MAX" value="15" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
+  <parameter name="REGISTER_C2P" value="false" />
+  <parameter name="FAST_SIM_CALIBRATION" value="false" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="DQS_EN_DELAY_MAX" value="7" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="AVL_ADDR_WIDTH" value="13" />
+  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="AFI_MAX_READ_LATENCY_COUNT_WIDTH" value="6" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
+  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
+  <parameter name="DUAL_WRITE_CLOCK" value="false" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_MULT" value="3" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
+  <parameter name="READ_FIFO_HALF_RATE" value="true" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="GENERIC_PLL" value="false" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="REF_CLK_NS" value="10.0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
+  <parameter name="IO_OUT2_DELAY_MAX" value="7" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_CACHE_VALID" value="true" />
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
+  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="PLL_HR_CLK_MULT" value="0" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="PLL_MEM_CLK_DIV" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="USE_HARD_READ_FIFO" value="false" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="PHY_VERSION_NUMBER" value="191" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
+  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
+  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="true" />
+  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="MEM_T_WL" value="5" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="MEM_CLK_PS" value="3333.0" />
+  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
+  <parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="IO_OUT1_DELAY_MAX" value="15" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="DQS_IN_DELAY_MAX" value="15" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
+  <parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
+  <parameter name="IO_STANDARD" value="SSTL-15" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="SPEED_GRADE_CACHE" value="" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
+  <parameter name="USE_2X_FF" value="false" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
+  <parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
+  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="MEM_T_RL" value="5" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="USE_DR_CLK" value="false" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MAX10_RTL_SEQ" value="true" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
+  <parameter name="PLL_AFI_CLK_DIV" value="2" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_datamux.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_m10.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_bitcheck.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_broadcast.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_write_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_dm_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_di_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_read_datapath.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_pll_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_data_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sequencer_phy_mgr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_generic.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr12.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_jumplogic.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr72.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_ddr3.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_lfsr36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex"
+       type="HEX"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_qseq/altera_mem_if_ddr3_qseq/altera_mem_if_ddr3_qseq_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram" as="s0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
+   <message level="Info" culprit="s0">Generating Qsys sequencer system</message>
+   <message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
+   <message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:ddr3_ram:.:c0"
+   kind="altera_mem_if_nextgen_ddr3_controller"
+   version="19.1"
+   name="q_sys_ddr3_ram_c0">
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
+  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
+  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="MEM_ADD_LAT" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="INTG_MEM_IF_TRFC" value="34" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
+  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
+  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
+  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="AVL_DATA_WIDTH" value="32" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CFG_READ_ODT_CHIP" value="0" />
+  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="TG_TEMP_PORT_5" value="0" />
+  <parameter name="TG_TEMP_PORT_3" value="0" />
+  <parameter name="TG_TEMP_PORT_4" value="0" />
+  <parameter name="TG_TEMP_PORT_1" value="0" />
+  <parameter name="TG_TEMP_PORT_2" value="0" />
+  <parameter name="TG_TEMP_PORT_0" value="0" />
+  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
+  <parameter name="CFG_ENABLE_NO_DM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
+  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
+  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
+  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
+  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
+  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="WEIGHT_PORT_2" value="0" />
+  <parameter name="WEIGHT_PORT_1" value="0" />
+  <parameter name="WEIGHT_PORT_0" value="0" />
+  <parameter name="WEIGHT_PORT_5" value="0" />
+  <parameter name="WEIGHT_PORT_4" value="0" />
+  <parameter name="WEIGHT_PORT_3" value="0" />
+  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="LOCAL_CS_WIDTH" value="0" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
+  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
+  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
+  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
+  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
+  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="AVL_NUM_SYMBOLS" value="4" />
+  <parameter name="CTL_OUTPUT_REGD" value="false" />
+  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="AVL_PORT" value="" />
+  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
+  <parameter name="MSB_RFIFO_PORT_2" value="5" />
+  <parameter name="MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CTL_USR_REFRESH" value="0" />
+  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="CFG_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
+  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_TBP_NUM" value="4" />
+  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
+  <parameter name="CFG_ECC_DECODER_REG" value="0" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="CTL_SELF_REFRESH" value="0" />
+  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
+  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="CFG_TYPE" value="2" />
+  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
+  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
+  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="CFG_INTERFACE_WIDTH" value="8" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
+  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
+  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
+  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
+  <parameter name="CFG_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
+  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
+  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="FLY_BY" value="true" />
+  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="DWIDTH_RATIO" value="4" />
+  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
+  <parameter name="CFG_CLR_INTR" value="0" />
+  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
+  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
+  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
+  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
+  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="LOW_LATENCY" value="false" />
+  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
+  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="CFG_STARVE_LIMIT" value="10" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
+  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="CFG_ADDR_ORDER" value="0" />
+  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CTL_ODT_ENABLED" value="false" />
+  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
+  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CS_WIDTH" value="1" />
+  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
+  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
+  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
+  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
+  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="ENUM_MEM_IF_TMRD" value="" />
+  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
+  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
+  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
+  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AVL_ADDR_WIDTH" value="25" />
+  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MAX10_CFG" value="true" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
+  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
+  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="AVL_BE_WIDTH" value="4" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
+  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
+  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
+  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
+  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
+  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
+  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
+  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="AVL_SIZE_WIDTH" value="3" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
+  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter
+     name="CPORT_TYPE_PORT"
+     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
+  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
+  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
+  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
+  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
+  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
+  <parameter name="LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="PRIORITY_PORT_0" value="0" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="PRIORITY_PORT_2" value="0" />
+  <parameter name="PRIORITY_PORT_1" value="0" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="PRIORITY_PORT_4" value="0" />
+  <parameter name="PRIORITY_PORT_3" value="0" />
+  <parameter name="PRIORITY_PORT_5" value="0" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_list.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv"
+       type="VERILOG_INCLUDE"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller/alt_mem_if_nextgen_ddr3_controller_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys_ddr3_ram" as="c0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
+   <message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
+   <message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
+   <message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
+   <message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true"
+   instancePathKey="q_sys:.:eth_tse:.:i_tse_mac"
+   kind="altera_eth_tse_mac"
+   version="19.1"
+   name="altera_eth_tse_mac">
+  <parameter name="CORE_VERSION" value="4865" />
+  <parameter name="CRC32GENDELAY" value="6" />
+  <parameter name="ENABLE_GMII_LOOPBACK" value="true" />
+  <parameter name="connect_to_pcs" value="false" />
+  <parameter name="ENABLE_MAC_RX_VLAN" value="false" />
+  <parameter name="DEVICE_FAMILY" value="MAX10" />
+  <parameter name="RAM_TYPE" value="AUTO" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="ENABLE_LGTH_CHECK" value="true" />
+  <parameter name="MBIT_ONLY" value="true" />
+  <parameter name="CUST_VERSION" value="0" />
+  <parameter name="REDUCED_INTERFACE_ENA" value="true" />
+  <parameter name="ENABLE_MDIO" value="true" />
+  <parameter name="CRC32CHECK16BIT" value="0" />
+  <parameter name="ING_ADDR" value="11" />
+  <parameter name="CRC32S1L2_EXTERN" value="false" />
+  <parameter name="ENABLE_MAC_TXADDR_SET" value="true" />
+  <parameter name="EG_FIFO" value="2048" />
+  <parameter name="use_misc_ports" value="true" />
+  <parameter name="INSERT_TA" value="false" />
+  <parameter name="EG_ADDR" value="11" />
+  <parameter name="STAT_CNT_ENA" value="true" />
+  <parameter name="REDUCED_CONTROL" value="false" />
+  <parameter name="GBIT_ONLY" value="true" />
+  <parameter name="CRC32DWIDTH" value="8" />
+  <parameter name="ENABLE_ENA" value="32" />
+  <parameter name="ENA_HASH" value="false" />
+  <parameter name="ENABLE_SUP_ADDR" value="false" />
+  <parameter name="ENABLE_SHIFT16" value="true" />
+  <parameter name="RESET_LEVEL" value="1" />
+  <parameter name="ENABLE_MAGIC_DETECT" value="true" />
+  <parameter name="USE_SYNC_RESET" value="true" />
+  <parameter name="ING_FIFO" value="2048" />
+  <parameter name="ENABLE_MAC_TX_VLAN" value="false" />
+  <parameter name="ENABLE_EXTENDED_STAT_REG" value="false" />
+  <parameter name="ENABLE_MAC_FLOW_CTRL" value="false" />
+  <parameter name="ENABLE_PADDING" value="true" />
+  <parameter name="SYNCHRONIZER_DEPTH" value="3" />
+  <parameter name="ENABLE_ECC" value="false" />
+  <parameter name="ENABLE_HD_LOGIC" value="true" />
+  <parameter name="MDIO_CLK_DIV" value="40" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clk_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328checker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32galois8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gmii_io.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_hashing.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map_small.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_register_map.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lfsr_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_loopback_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altshifttaps.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_magic_detection.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_mdio.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_base.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_module.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_gen_host.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_false_path_marker.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clock_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gray_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_bin_cnt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc"
+       type="SDC"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_eth_tse" as="i_tse_mac" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
+   <message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false"
+   instancePathKey="q_sys:.:eth_tse:.:rgmii_in4_0"
+   kind="altera_gpio_lite"
+   version="19.1"
+   name="altera_gpio_lite">
+  <parameter name="USE_ONE_REG_TO_DRIVE_OE" value="false" />
+  <parameter name="gui_use_hardened_ddio_input_registers" value="false" />
+  <parameter name="SYNC_MODE" value="none" />
+  <parameter name="SET_REGISTER_OUTPUTS_HIGH" value="false" />
+  <parameter name="REGISTER_MODE" value="ddr" />
+  <parameter name="gui_set_registers_to_power_up_high" value="false" />
+  <parameter name="INVERT_INPUT_CLOCK" value="false" />
+  <parameter name="USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY" value="false" />
+  <parameter name="gui_enable_invert_hr_clock_port" value="false" />
+  <parameter name="SIZE" value="4" />
+  <parameter name="BUFFER_TYPE" value="single-ended" />
+  <parameter name="gui_enable_sclr_port" value="false" />
+  <parameter name="ENABLE_CLOCK_ENA_PORT" value="false" />
+  <parameter name="gui_true_diff_buf" value="false" />
+  <parameter name="gui_enable_oe_port_off_shadow" value="false" />
+  <parameter name="ENABLE_NSLEEP_PORT" value="false" />
+  <parameter name="gui_use_ddio_reg_to_drive_oe_off_shadow" value="false" />
+  <parameter name="ENABLE_OE_PORT" value="false" />
+  <parameter name="gui_enable_nsleep_port" value="false" />
+  <parameter name="USE_DDIO_REG_TO_DRIVE_OE" value="false" />
+  <parameter name="INVERT_OE_INCLOCK" value="false" />
+  <parameter name="gui_invert_input_clock" value="false" />
+  <parameter name="gui_bus_hold" value="false" />
+  <parameter name="OPEN_DRAIN_OUTPUT" value="false" />
+  <parameter name="BUS_HOLD" value="false" />
+  <parameter name="INVERT_CLKDIV_INPUT_CLOCK" value="false" />
+  <parameter name="USE_ADVANCED_DDR_FEATURES" value="false" />
+  <parameter name="ENABLE_OE_HALF_CYCLE_DELAY" value="true" />
+  <parameter name="PIN_TYPE" value="input" />
+  <parameter name="gui_io_reg_mode" value="ddr" />
+  <parameter name="gui_enable_phase_detector_for_ck_off_shadow" value="false" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENABLE_PHASE_DETECTOR_FOR_CK" value="false" />
+  <parameter name="gui_use_ddio_reg_to_drive_oe" value="false" />
+  <parameter name="gui_invert_output_clock" value="false" />
+  <parameter name="gui_pseudo_diff_buf" value="false" />
+  <parameter name="gui_invert_output" value="false" />
+  <parameter name="gui_invert_oe_inclock" value="false" />
+  <parameter name="ASYNC_MODE" value="none" />
+  <parameter name="ENABLE_HR_CLOCK" value="false" />
+  <parameter name="ENABLE_PHASE_INVERT_CTRL_PORT" value="false" />
+  <parameter name="gui_invert_clkdiv_input_clock" value="false" />
+  <parameter name="gui_enable_oe_port_on_shadow" value="true" />
+  <parameter name="gui_use_register_to_drive_obuf_oe" value="false" />
+  <parameter name="gui_enable_aclr_port" value="false" />
+  <parameter name="gui_use_advanced_ddr_features" value="false" />
+  <parameter name="gui_enable_phase_detector_for_ck" value="false" />
+  <parameter name="INVERT_OUTPUT_CLOCK" value="false" />
+  <parameter name="gui_enable_oe_half_cycle_delay" value="true" />
+  <parameter name="INVERT_OUTPUT" value="false" />
+  <parameter name="gui_enable_oe_port" value="false" />
+  <parameter name="gui_clock_enable" value="false" />
+  <parameter name="gui_use_register_to_drive_obuf_oe_off_shadow" value="false" />
+  <parameter name="gui_enable_hr_clock" value="false" />
+  <parameter name="gui_enable_aset_port" value="false" />
+  <parameter name="gui_open_drain" value="false" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_gpio_lite/altera_gpio_lite_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_eth_tse"
+     as="rgmii_in4_0,rgmii_in1_0,rgmii_out4_0,rgmii_out1_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
+   <message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD)"
+   instancePathKey="q_sys:.:ext_flash:.:soft_asmiblock_instance_name"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   name="q_sys_ext_flash_soft_asmiblock_instance_name">
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="CS_WIDTH" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles/>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys_ext_flash" as="soft_asmiblock_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
+   <message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true)"
+   instancePathKey="q_sys:.:ext_flash:.:asmi_parallel_instance_name"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   name="q_sys_ext_flash_asmi_parallel_instance_name">
+  <parameter name="PORT_EN4B_ADDR" value="PORT_USED" />
+  <parameter name="USE_EAB" value="ON" />
+  <parameter name="PORT_READ_SID" value="PORT_UNUSED" />
+  <parameter name="gui_read_rdid" value="true" />
+  <parameter name="gui_page_write" value="true" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="PORT_ILLEGAL_WRITE" value="PORT_USED" />
+  <parameter name="FLASH_RSTPIN" value="TRUE" />
+  <parameter name="EPCS_TYPE" value="EPCQL512" />
+  <parameter name="gui_sector_protect" value="true" />
+  <parameter name="PORT_WRITE" value="PORT_USED" />
+  <parameter name="gui_fast_read" value="true" />
+  <parameter name="PORT_SECTOR_ERASE" value="PORT_USED" />
+  <parameter name="DATA_WIDTH" value="QUAD" />
+  <parameter name="gui_read_address" value="false" />
+  <parameter name="gui_sector_erase" value="true" />
+  <parameter name="gui_use_asmiblock" value="true" />
+  <parameter name="PORT_DIE_ERASE" value="PORT_UNUSED" />
+  <parameter name="PORT_WREN" value="PORT_USED" />
+  <parameter name="WRITE_DUMMY_CLK" value="0" />
+  <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+  <parameter name="gui_read_dummyclk" value="true" />
+  <parameter name="gui_single_write" value="false" />
+  <parameter name="gui_die_erase" value="false" />
+  <parameter name="gui_ex4b_addr" value="false" />
+  <parameter name="gui_use_eab" value="false" />
+  <parameter name="PORT_READ_DUMMYCLK" value="PORT_USED" />
+  <parameter name="gui_write" value="true" />
+  <parameter name="PORT_SHIFT_BYTES" value="PORT_USED" />
+  <parameter name="PORT_SECTOR_PROTECT" value="PORT_USED" />
+  <parameter name="gui_bulk_erase" value="false" />
+  <parameter name="PORT_FAST_READ" value="PORT_USED" />
+  <parameter name="ENABLE_SIM" value="true" />
+  <parameter name="PORT_READ_STATUS" value="PORT_USED" />
+  <parameter name="PORT_BULK_ERASE" value="PORT_UNUSED" />
+  <parameter name="PORT_RDID_OUT" value="PORT_USED" />
+  <parameter name="PORT_READ_RDID" value="PORT_USED" />
+  <parameter name="gui_read_status" value="true" />
+  <parameter name="PORT_EX4B_ADDR" value="PORT_UNUSED" />
+  <parameter name="PAGE_SIZE" value="256" />
+  <parameter name="gui_wren" value="true" />
+  <parameter name="gui_read_sid" value="false" />
+  <parameter name="PORT_ILLEGAL_ERASE" value="PORT_USED" />
+  <parameter name="PORT_READ_ADDRESS" value="PORT_UNUSED" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="" />
+  <parameter name="USE_ASMIBLOCK" value="OFF" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles/>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys_ext_flash" as="asmi_parallel_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
+   <message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
+   <message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None)"
+   instancePathKey="q_sys:.:ext_flash:.:epcq_controller_instance_name"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   name="q_sys_ext_flash_epcq_controller_instance_name">
+  <parameter name="ASMI_ADDR_WIDTH" value="32" />
+  <parameter name="ADDR_WIDTH" value="24" />
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="DDASI" value="1" />
+  <parameter name="CS_WIDTH" value="1" />
+  <parameter name="deviceFeaturesSystemInfo" value="None" />
+  <parameter name="ASI_WIDTH" value="4" />
+  <parameter name="ENABLE_4BYTE_ADDR" value="1" />
+  <parameter name="FLASH_TYPE" value="EPCQL512" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
+       type="SYSTEM_VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles/>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys_ext_flash" as="epcq_controller_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
+   <message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses"
+   instancePathKey="q_sys:.:msgdma_rx:.:dispatcher_internal"
+   kind="modular_sgdma_dispatcher"
+   version="19.1"
+   name="dispatcher">
+  <parameter name="GUI_RESPONSE_PORT" value="2" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="PREFETCHER_USE_CASE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="DESCRIPTOR_WIDTH" value="128" />
+  <parameter name="DESCRIPTOR_INTERFACE" value="1" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="RESPONSE_PORT" value="1" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="CSR_ADDRESS_WIDTH" value="3" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="DESCRIPTOR_BYTEENABLE_WIDTH" value="16" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_msgdma_rx" as="dispatcher_internal" />
+  <instantiator instantiator="q_sys_msgdma_tx" as="dispatcher_internal" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
+   <message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0"
+   instancePathKey="q_sys:.:msgdma_rx:.:prefetcher_internal"
+   kind="altera_msgdma_prefetcher"
+   version="19.1"
+   name="altera_msgdma_prefetcher">
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="GUI_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="ENABLE_READ_BURST" value="0" />
+  <parameter name="AUTO_ADDRESS_WIDTH" value="29" />
+  <parameter name="GUI_DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="MAX_READ_BURST_COUNT_WIDTH" value="1" />
+  <parameter name="DESCRIPTOR_WIDTH" value="128" />
+  <parameter name="MAX_READ_BURST_COUNT" value="1" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="DATA_BYTEENABLE_WIDTH" value="4" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_msgdma_rx" as="prefetcher_internal" />
+  <instantiator instantiator="q_sys_msgdma_tx" as="prefetcher_internal" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
+   <message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0"
+   instancePathKey="q_sys:.:msgdma_rx:.:write_mstr_internal"
+   kind="dma_write_master"
+   version="19.1"
+   name="write_master">
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/byte_enable_generator.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ST_to_MM_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_msgdma_rx" as="write_mstr_internal" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
+   <message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0"
+   instancePathKey="q_sys:.:msgdma_tx:.:read_mstr_internal"
+   kind="dma_read_master"
+   version="19.1"
+   name="read_master">
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_master.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/MM_to_ST_Adapter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_burst_control.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_msgdma_tx" as="read_mstr_internal" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
+   <message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=2,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0"
+   instancePathKey="q_sys:.:mm_interconnect_0:.:sensor_interface_calibration_ram_interface_translator"
+   kind="altera_merlin_master_translator"
+   version="19.1"
+   name="altera_merlin_master_translator">
+  <parameter name="SYNC_RESET" value="0" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_0"
+     as="sensor_interface_calibration_ram_interface_translator" />
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cpu_data_master_translator,cpu_instruction_master_translator,msgdma_tx_mm_read_translator,msgdma_rx_mm_write_translator,msgdma_tx_descriptor_read_master_translator,msgdma_rx_descriptor_read_master_translator,msgdma_tx_descriptor_write_master_translator,msgdma_rx_descriptor_write_master_translator" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
+   <message
+       level="Info"
+       culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
+   instancePathKey="q_sys:.:mm_interconnect_0:.:calibration_ram_s2_translator"
+   kind="altera_merlin_slave_translator"
+   version="19.1"
+   name="altera_merlin_slave_translator">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_0"
+     as="calibration_ram_s2_translator" />
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="ddr3_ram_avl_translator,ext_flash_avl_csr_translator,ext_flash_avl_mem_translator,eth_tse_control_port_translator,sysid_control_slave_translator,msgdma_tx_csr_translator,msgdma_rx_csr_translator,onchip_flash_csr_translator,udp_generator_csr_translator,sensor_interface_csr_translator,onchip_flash_data_translator,cpu_debug_mem_slave_translator,msgdma_tx_prefetcher_csr_translator,msgdma_rx_prefetcher_csr_translator,descriptor_memory_s1_translator,sys_clk_timer_s1_translator,output_pio_s1_translator,button_pio_s1_translator,debug_uart_s1_translator,frame_timer_s1_translator,calibration_ram_s1_translator" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
+   <message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_master_agent:19.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
+&lt;address_map&gt;
+ &lt;slave
+   id=&quot;3&quot;
+   name=&quot;ddr3_ram_avl_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000008000000&quot;
+   end=&quot;0x00000000010000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;7&quot;
+   name=&quot;ext_flash_avl_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d20&quot;
+   end=&quot;0x00000000018403d40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;8&quot;
+   name=&quot;ext_flash_avl_mem_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000014000000&quot;
+   end=&quot;0x00000000018000000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;6&quot;
+   name=&quot;eth_tse_control_port_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403000&quot;
+   end=&quot;0x00000000018403400&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;19&quot;
+   name=&quot;sysid_control_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d68&quot;
+   end=&quot;0x00000000018403d70&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;12&quot;
+   name=&quot;msgdma_tx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d00&quot;
+   end=&quot;0x00000000018403d20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;10&quot;
+   name=&quot;msgdma_rx_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ce0&quot;
+   end=&quot;0x00000000018403d00&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;14&quot;
+   name=&quot;onchip_flash_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d60&quot;
+   end=&quot;0x00000000018403d68&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;20&quot;
+   name=&quot;udp_generator_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403cc0&quot;
+   end=&quot;0x00000000018403ce0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;17&quot;
+   name=&quot;sensor_interface_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d50&quot;
+   end=&quot;0x00000000018403d60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;15&quot;
+   name=&quot;onchip_flash_data_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018200000&quot;
+   end=&quot;0x00000000018400000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;2&quot;
+   name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018402800&quot;
+   end=&quot;0x00000000018403000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;13&quot;
+   name=&quot;msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403ca0&quot;
+   end=&quot;0x00000000018403cc0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;11&quot;
+   name=&quot;msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c80&quot;
+   end=&quot;0x00000000018403ca0&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;5&quot;
+   name=&quot;descriptor_memory_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018400000&quot;
+   end=&quot;0x00000000018402000&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;18&quot;
+   name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c60&quot;
+   end=&quot;0x00000000018403c80&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;16&quot;
+   name=&quot;output_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c40&quot;
+   end=&quot;0x00000000018403c60&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;0&quot;
+   name=&quot;button_pio_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403d40&quot;
+   end=&quot;0x00000000018403d50&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;4&quot;
+   name=&quot;debug_uart_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c20&quot;
+   end=&quot;0x00000000018403c40&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;9&quot;
+   name=&quot;frame_timer_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403c00&quot;
+   end=&quot;0x00000000018403c20&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+ &lt;slave
+   id=&quot;1&quot;
+   name=&quot;calibration_ram_s1_translator.avalon_universal_slave_0&quot;
+   start=&quot;0x0000000018403400&quot;
+   end=&quot;0x00000000018403800&quot;
+   responds=&quot;1&quot;
+   user_default=&quot;0&quot; /&gt;
+&lt;/address_map&gt;
+,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cpu_data_master_agent"
+   kind="altera_merlin_master_agent"
+   version="19.1"
+   name="altera_merlin_master_agent">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cpu_data_master_agent,cpu_instruction_master_agent,msgdma_tx_mm_read_agent,msgdma_rx_mm_write_agent,msgdma_tx_descriptor_read_master_agent,msgdma_rx_descriptor_read_master_agent,msgdma_tx_descriptor_write_master_agent,msgdma_rx_descriptor_write_master_agent" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
+   <message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=3,MAX_BURSTWRAP=511,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:ddr3_ram_avl_agent"
+   kind="altera_merlin_slave_agent"
+   version="19.1"
+   name="altera_merlin_slave_agent">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="ddr3_ram_avl_agent,ext_flash_avl_csr_agent,ext_flash_avl_mem_agent,eth_tse_control_port_agent,sysid_control_slave_agent,msgdma_tx_csr_agent,msgdma_rx_csr_agent,onchip_flash_csr_agent,udp_generator_csr_agent,sensor_interface_csr_agent,onchip_flash_data_agent,cpu_debug_mem_slave_agent,msgdma_tx_prefetcher_csr_agent,msgdma_rx_prefetcher_csr_agent,descriptor_memory_s1_agent,sys_clk_timer_s1_agent,output_pio_s1_agent,button_pio_s1_agent,debug_uart_s1_agent,frame_timer_s1_agent,calibration_ram_s1_agent" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=33,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:ddr3_ram_avl_agent_rsp_fifo"
+   kind="altera_avalon_sc_fifo"
+   version="19.1"
+   name="altera_avalon_sc_fifo">
+  <parameter name="EXPLICIT_MAXCHANNEL" value="0" />
+  <parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="ddr3_ram_avl_agent_rsp_fifo,ddr3_ram_avl_agent_rdata_fifo,ext_flash_avl_csr_agent_rsp_fifo,ext_flash_avl_csr_agent_rdata_fifo,ext_flash_avl_mem_agent_rsp_fifo,ext_flash_avl_mem_agent_rdata_fifo,eth_tse_control_port_agent_rsp_fifo,sysid_control_slave_agent_rsp_fifo,msgdma_tx_csr_agent_rsp_fifo,msgdma_rx_csr_agent_rsp_fifo,onchip_flash_csr_agent_rsp_fifo,udp_generator_csr_agent_rsp_fifo,sensor_interface_csr_agent_rsp_fifo,onchip_flash_data_agent_rsp_fifo,cpu_debug_mem_slave_agent_rsp_fifo,msgdma_tx_prefetcher_csr_agent_rsp_fifo,msgdma_rx_prefetcher_csr_agent_rsp_fifo,descriptor_memory_s1_agent_rsp_fifo,sys_clk_timer_s1_agent_rsp_fifo,output_pio_s1_agent_rsp_fifo,button_pio_s1_agent_rsp_fifo,debug_uart_s1_agent_rsp_fifo,frame_timer_s1_agent_rsp_fifo,calibration_ram_s1_agent_rsp_fifo" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
+   <message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SLAVES_INFO=3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter
+     name="START_ADDRESS"
+     value="0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter
+     name="SLAVES_INFO"
+     value="3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter
+     name="CHANNEL_ID"
+     value="000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000" />
+  <parameter
+     name="TYPE_OF_TRANSACTION"
+     value="both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read" />
+  <parameter
+     name="SECURED_RANGE_PAIRS"
+     value="0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter
+     name="SECURED_RANGE_LIST"
+     value="0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" />
+  <parameter name="DECODER_TYPE" value="0" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter
+     name="END_ADDRESS"
+     value="0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="3" />
+  <parameter
+     name="DESTINATION_ID"
+     value="3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19" />
+  <parameter
+     name="NON_SECURED_TAG"
+     value="1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
+   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,2,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18403000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18402800,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_001"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_001">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter
+     name="START_ADDRESS"
+     value="0x8000000,0x14000000,0x18200000,0x18402800" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter
+     name="SLAVES_INFO"
+     value="3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="0001,0010,0100,1000" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both,both,both,both" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0,0,0,0" />
+  <parameter name="DECODER_TYPE" value="0" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter
+     name="END_ADDRESS"
+     value="0x10000000,0x18000000,0x18400000,0x18403000" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="3" />
+  <parameter name="DESTINATION_ID" value="3,8,15,2" />
+  <parameter name="NON_SECURED_TAG" value="1,1,1,1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router_001" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
+   <message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_002"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_002">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x8000000" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter name="SLAVES_INFO" value="3:1:0x8000000:0x10000000:both:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="1" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0" />
+  <parameter name="DECODER_TYPE" value="0" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x10000000" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="3" />
+  <parameter name="DESTINATION_ID" value="3" />
+  <parameter name="NON_SECURED_TAG" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router_002,router_003" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
+   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_004"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_004">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x18400000" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter name="SLAVES_INFO" value="5:1:0x18400000:0x18402000:both:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="1" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0" />
+  <parameter name="DECODER_TYPE" value="0" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x18402000" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="5" />
+  <parameter name="DESTINATION_ID" value="5" />
+  <parameter name="NON_SECURED_TAG" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="router_004,router_005,router_006,router_007" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
+   <message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,7,4,END_ADDRESS=0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_008"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_008">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x0,0x0,0x0,0x0" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter
+     name="SLAVES_INFO"
+     value="0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="0001,0010,0100,1000" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both,read,read,write" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0,0,0,0" />
+  <parameter name="DECODER_TYPE" value="1" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x0,0x0,0x0,0x0" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="0" />
+  <parameter name="DESTINATION_ID" value="0,1,7,4" />
+  <parameter name="NON_SECURED_TAG" value="1,1,1,1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router_008" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
+   <message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_009"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_009">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x0" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter name="SLAVES_INFO" value="0:1:0x0:0x0:both:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="1" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0" />
+  <parameter name="DECODER_TYPE" value="1" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x0" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="0" />
+  <parameter name="DESTINATION_ID" value="0" />
+  <parameter name="NON_SECURED_TAG" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="router_009,router_011,router_012,router_013,router_014,router_015,router_016,router_017,router_020,router_021,router_023,router_024,router_025,router_026,router_027" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
+   <message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_010"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_010">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x0,0x0" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter
+     name="SLAVES_INFO"
+     value="0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="01,10" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both,read" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0,0" />
+  <parameter name="DECODER_TYPE" value="1" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x0,0x0" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="0" />
+  <parameter name="DESTINATION_ID" value="0,1" />
+  <parameter name="NON_SECURED_TAG" value="1,1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="router_010,router_018,router_019" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
+   <message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=00001,00010,00100,01000,10000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,5,2,6,3,END_ADDRESS=0x0,0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,SLAVES_INFO=0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write,write"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_022"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_022">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="68" />
+  <parameter name="START_ADDRESS" value="0x0,0x0,0x0,0x0,0x0" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter
+     name="SLAVES_INFO"
+     value="0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="64" />
+  <parameter name="PKT_DEST_ID_H" value="107" />
+  <parameter name="PKT_ADDR_L" value="36" />
+  <parameter name="PKT_DEST_ID_L" value="103" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="CHANNEL_ID" value="00001,00010,00100,01000,10000" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both,read,read,write,write" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0,0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="SECURED_RANGE_LIST" value="0,0,0,0,0" />
+  <parameter name="DECODER_TYPE" value="1" />
+  <parameter name="PKT_PROTECTION_H" value="111" />
+  <parameter name="END_ADDRESS" value="0x0,0x0,0x0,0x0,0x0" />
+  <parameter name="PKT_PROTECTION_L" value="109" />
+  <parameter name="PKT_TRANS_WRITE" value="67" />
+  <parameter name="DEFAULT_DESTID" value="0" />
+  <parameter name="DESTINATION_ID" value="0,5,2,6,3" />
+  <parameter name="NON_SECURED_TAG" value="1,1,1,1,1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router_022" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
+   <message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=103,TYPE_OF_TRANSACTION=both"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:router_028"
+   kind="altera_merlin_router"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_router_028">
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
+  <parameter name="PKT_TRANS_READ" value="50" />
+  <parameter name="START_ADDRESS" value="0x0" />
+  <parameter name="DEFAULT_CHANNEL" value="0" />
+  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
+  <parameter name="SLAVES_INFO" value="0:1:0x0:0x0:both:1:0:0:1" />
+  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
+  <parameter name="PKT_ADDR_H" value="46" />
+  <parameter name="PKT_DEST_ID_H" value="89" />
+  <parameter name="PKT_ADDR_L" value="18" />
+  <parameter name="PKT_DEST_ID_L" value="85" />
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)" />
+  <parameter name="CHANNEL_ID" value="1" />
+  <parameter name="TYPE_OF_TRANSACTION" value="both" />
+  <parameter name="SECURED_RANGE_PAIRS" value="0" />
+  <parameter name="SPAN_OFFSET" value="" />
+  <parameter name="ST_DATA_W" value="103" />
+  <parameter name="SECURED_RANGE_LIST" value="0" />
+  <parameter name="DECODER_TYPE" value="1" />
+  <parameter name="PKT_PROTECTION_H" value="93" />
+  <parameter name="END_ADDRESS" value="0x0" />
+  <parameter name="PKT_PROTECTION_L" value="91" />
+  <parameter name="PKT_TRANS_WRITE" value="49" />
+  <parameter name="DEFAULT_DESTID" value="0" />
+  <parameter name="DESTINATION_ID" value="0" />
+  <parameter name="NON_SECURED_TAG" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="router_028" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
+   <message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cpu_data_master_limiter"
+   kind="altera_merlin_traffic_limiter"
+   version="19.1"
+   name="altera_merlin_traffic_limiter">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cpu_data_master_limiter,cpu_instruction_master_limiter" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
+   <message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=3,BURSTWRAP_CONST_VALUE=3,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=87,OUT_BYTE_CNT_H=79,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,ST_CHANNEL_W=21,ST_DATA_W=121"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:ext_flash_avl_mem_burst_adapter"
+   kind="altera_merlin_burst_adapter"
+   version="19.1"
+   name="altera_merlin_burst_adapter">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="PKT_TRANS_COMPRESSED_READ" value="65" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_incr_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_default_burst_converter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="ext_flash_avl_mem_burst_adapter,calibration_ram_s1_burst_adapter" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
+   <message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=21,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_demux">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="VALID_WIDTH" value="21" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="21" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_demux" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
+   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux_001"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_demux_001">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="VALID_WIDTH" value="21" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="4" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_demux_001" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
+   <message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux_002"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_demux_002">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cmd_demux_002,cmd_demux_003,cmd_demux_004,cmd_demux_005,cmd_demux_006,cmd_demux_007,rsp_demux_003,rsp_demux_004,rsp_demux_005,rsp_demux_006,rsp_demux_007,rsp_demux_008,rsp_demux_009,rsp_demux_012,rsp_demux_013,rsp_demux_015,rsp_demux_016,rsp_demux_017,rsp_demux_018,rsp_demux_019,rsp_demux_020" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
+   <message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_mux">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1,1,1,1" />
+  <parameter name="NUM_INPUTS" value="4" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_mux" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
+   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_001"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_mux_001">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1" />
+  <parameter name="NUM_INPUTS" value="1" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cmd_mux_001,cmd_mux_003,cmd_mux_004,cmd_mux_005,cmd_mux_006,cmd_mux_007,cmd_mux_008,cmd_mux_009,cmd_mux_012,cmd_mux_013,cmd_mux_015,cmd_mux_016,cmd_mux_017,cmd_mux_018,cmd_mux_019,cmd_mux_020" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
+   <message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_002"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_mux_002">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1,1" />
+  <parameter name="NUM_INPUTS" value="2" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="cmd_mux_002,cmd_mux_010,cmd_mux_011" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
+   <message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=5,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_014"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_cmd_mux_014">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1,1,1,1,1" />
+  <parameter name="NUM_INPUTS" value="5" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_mux_014" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
+   <message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=150000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_demux">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="150000000" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="4" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
+   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_001"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_demux_001">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_001" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
+   <message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_002"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_demux_002">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="2" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_002" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
+   <message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_010"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_demux_010">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="2" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="rsp_demux_010,rsp_demux_011" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
+   <message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=5,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_014"
+   kind="altera_merlin_demultiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_demux_014">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="VALID_WIDTH" value="1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="NUM_OUTPUTS" value="5" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_014" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
+   <message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=21,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_mux">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter
+     name="ARBITRATION_SHARES"
+     value="1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" />
+  <parameter name="NUM_INPUTS" value="21" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_mux" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
+   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux_001"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_mux_001">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1,1,1,1" />
+  <parameter name="NUM_INPUTS" value="4" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_mux_001" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
+   <message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux_002"
+   kind="altera_merlin_multiplexer"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_rsp_mux_002">
+  <parameter
+     name="MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter name="ST_CHANNEL_W" value="21" />
+  <parameter name="ARBITRATION_SHARES" value="1" />
+  <parameter name="NUM_INPUTS" value="1" />
+  <parameter name="PIPELINE_ARB" value="0" />
+  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
+  <parameter name="ST_DATA_W" value="121" />
+  <parameter name="USE_EXTERNAL_ARB" value="0" />
+  <parameter name="PKT_TRANS_LOCK" value="69" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="rsp_mux_002,rsp_mux_003,rsp_mux_004,rsp_mux_005,rsp_mux_006,rsp_mux_007" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
+   <message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=46,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=70,IN_PKT_BURSTWRAP_L=62,IN_PKT_BURST_SIZE_H=73,IN_PKT_BURST_SIZE_L=71,IN_PKT_BURST_TYPE_H=75,IN_PKT_BURST_TYPE_L=74,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=61,IN_PKT_BYTE_CNT_L=53,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=102,IN_PKT_ORI_BURST_SIZE_L=100,IN_PKT_RESPONSE_STATUS_H=99,IN_PKT_RESPONSE_STATUS_L=98,IN_PKT_TRANS_COMPRESSED_READ=47,IN_PKT_TRANS_EXCLUSIVE=52,IN_PKT_TRANS_WRITE=49,IN_ST_DATA_W=103,OPTIMIZE_FOR_RSP=1,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=64,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=91,OUT_PKT_BURST_SIZE_L=89,OUT_PKT_BURST_TYPE_H=93,OUT_PKT_BURST_TYPE_L=92,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=79,OUT_PKT_BYTE_CNT_L=71,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=120,OUT_PKT_ORI_BURST_SIZE_L=118,OUT_PKT_RESPONSE_STATUS_H=117,OUT_PKT_RESPONSE_STATUS_L=116,OUT_PKT_TRANS_COMPRESSED_READ=65,OUT_PKT_TRANS_EXCLUSIVE=70,OUT_ST_DATA_W=121,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=21"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:calibration_ram_s1_rsp_width_adapter"
+   kind="altera_merlin_width_adapter"
+   version="19.1"
+   name="altera_merlin_width_adapter">
+  <parameter name="OUT_PKT_ORI_BURST_SIZE_H" value="120" />
+  <parameter name="OUT_PKT_ORI_BURST_SIZE_L" value="118" />
+  <parameter name="IN_PKT_ORI_BURST_SIZE_H" value="102" />
+  <parameter
+     name="OUT_MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
+  <parameter
+     name="IN_MERLIN_PACKET_FORMAT"
+     value="ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)" />
+  <parameter name="IN_PKT_ORI_BURST_SIZE_L" value="100" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="calibration_ram_s1_rsp_width_adapter,calibration_ram_s1_cmd_width_adapter" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
+   <message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:crosser"
+   kind="altera_avalon_st_handshake_clock_crosser"
+   version="19.1"
+   name="altera_avalon_st_handshake_clock_crosser">
+  <parameter name="AUTO_OUT_CLK_CLOCK_RATE" value="150000000" />
+  <parameter name="USE_PACKETS" value="1" />
+  <parameter name="BITS_PER_SYMBOL" value="121" />
+  <parameter name="MAX_CHANNEL" value="0" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="AUTO_IN_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="USE_ERROR" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="21" />
+  <parameter name="USE_CHANNEL" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
+       type="SDC"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="crosser,crosser_001,crosser_002,crosser_003,crosser_004,crosser_005,crosser_006,crosser_007,crosser_008,crosser_009,crosser_010,crosser_011,crosser_012,crosser_013" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
+   <message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
+   <message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=34,inChannelWidth=0,inDataWidth=34,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=34,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_avalon_st_adapter">
+  <parameter name="inUseValid" value="1" />
+  <parameter name="inBitsPerSymbol" value="34" />
+  <parameter name="outUseEmptyPort" value="0" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="outUseValid" value="1" />
+  <parameter name="outMaxChannel" value="0" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="0" />
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inEmptyWidth" value="1" />
+  <parameter name="inUseReady" value="1" />
+  <parameter name="outReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="outDataWidth" value="34" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter name="inUseEmptyPort" value="0" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="outUseReady" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="inDataWidth" value="34" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="outEmptyWidth" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1"
+     as="avalon_st_adapter,avalon_st_adapter_001,avalon_st_adapter_002,avalon_st_adapter_003,avalon_st_adapter_004,avalon_st_adapter_005,avalon_st_adapter_006,avalon_st_adapter_007,avalon_st_adapter_008,avalon_st_adapter_009,avalon_st_adapter_010,avalon_st_adapter_011,avalon_st_adapter_012,avalon_st_adapter_013,avalon_st_adapter_014,avalon_st_adapter_015,avalon_st_adapter_016,avalon_st_adapter_017,avalon_st_adapter_018,avalon_st_adapter_019" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=18,inChannelWidth=0,inDataWidth=18,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=18,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter_020"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_avalon_st_adapter_020">
+  <parameter name="inUseValid" value="1" />
+  <parameter name="inBitsPerSymbol" value="18" />
+  <parameter name="outUseEmptyPort" value="0" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="outUseValid" value="1" />
+  <parameter name="outMaxChannel" value="0" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="0" />
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inEmptyWidth" value="1" />
+  <parameter name="inUseReady" value="1" />
+  <parameter name="outReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="outDataWidth" value="18" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
+  <parameter name="inUseEmptyPort" value="0" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="outUseReady" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="inDataWidth" value="18" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="outEmptyWidth" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </childSourceFiles>
+  <instantiator instantiator="q_sys_mm_interconnect_1" as="avalon_st_adapter_020" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
+   <message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
+   <message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="error_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
+   instancePathKey="q_sys:.:avalon_st_adapter:.:error_adapter_0"
+   kind="error_adapter"
+   version="19.1"
+   name="q_sys_avalon_st_adapter_error_adapter_0">
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="true" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_avalon_st_adapter" as="error_adapter_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="timing_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,inUseValid=true,outReadyLatency=0,outUseReady=true,outUseValid=true"
+   instancePathKey="q_sys:.:avalon_st_adapter_001:.:timing_adapter_0"
+   kind="timing_adapter"
+   version="19.1"
+   name="q_sys_avalon_st_adapter_001_timing_adapter_0">
+  <parameter name="inErrorWidth" value="6" />
+  <parameter name="inUseValid" value="true" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="outReadyLatency" value="0" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="outUseReady" value="true" />
+  <parameter name="outUseValid" value="true" />
+  <parameter name="inReadyLatency" value="2" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="true" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_avalon_st_adapter_001" as="timing_adapter_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
+   <message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6"
+   instancePathKey="q_sys:.:ddr3_ram:.:c0:.:ng0"
+   kind="altera_mem_if_nextgen_ddr3_controller_core"
+   version="19.1"
+   name="alt_mem_if_nextgen_ddr3_controller_core">
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
+  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
+  <parameter name="LRDIMM_INT" value="0" />
+  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="MEM_LEVELING" value="true" />
+  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
+  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="MEM_ADD_LAT" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
+  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="INTG_MEM_IF_TRFC" value="34" />
+  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
+  <parameter name="AFI_DQ_WIDTH" value="32" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
+  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
+  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
+  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="AVL_DATA_WIDTH" value="32" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="MR1_RDQS" value="0" />
+  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
+  <parameter name="MR0_PD" value="0" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
+  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
+  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
+  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CFG_READ_ODT_CHIP" value="0" />
+  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="RDIMM" value="false" />
+  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
+  <parameter name="MEM_TRC" value="15" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="AFI_CS_WIDTH" value="2" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="TG_TEMP_PORT_5" value="0" />
+  <parameter name="TG_TEMP_PORT_3" value="0" />
+  <parameter name="TG_TEMP_PORT_4" value="0" />
+  <parameter name="TG_TEMP_PORT_1" value="0" />
+  <parameter name="TG_TEMP_PORT_2" value="0" />
+  <parameter name="TG_TEMP_PORT_0" value="0" />
+  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
+  <parameter name="CFG_ENABLE_NO_DM" value="0" />
+  <parameter name="MR1_TDQS" value="0" />
+  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
+  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
+  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
+  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="MEM_IF_ADDR_WIDTH" value="14" />
+  <parameter name="CSR_ADDR_WIDTH" value="8" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="RDIMM_INT" value="0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
+  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
+  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="WEIGHT_PORT_2" value="0" />
+  <parameter name="WEIGHT_PORT_1" value="0" />
+  <parameter name="WEIGHT_PORT_0" value="0" />
+  <parameter name="WEIGHT_PORT_5" value="0" />
+  <parameter name="WEIGHT_PORT_4" value="0" />
+  <parameter name="WEIGHT_PORT_3" value="0" />
+  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="MR2_RTT_WR" value="0" />
+  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
+  <parameter name="AFI_ODT_WIDTH" value="2" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
+  <parameter name="MEM_IF_DM_WIDTH" value="1" />
+  <parameter name="LOCAL_CS_WIDTH" value="0" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
+  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="MEM_IF_CHIP_BITS" value="1" />
+  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
+  <parameter name="MEM_IF_CK_WIDTH" value="1" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AFI_RATE_RATIO" value="2" />
+  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
+  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
+  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
+  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
+  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="AVL_NUM_SYMBOLS" value="4" />
+  <parameter name="CTL_OUTPUT_REGD" value="false" />
+  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
+  <parameter name="DQ_DDR" value="1" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="AVL_PORT" value="" />
+  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="true" />
+  <parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
+  <parameter name="MEM_TDQSCK" value="1" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
+  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
+  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
+  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
+  <parameter name="MSB_RFIFO_PORT_2" value="5" />
+  <parameter name="MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_TREFI" value="2341" />
+  <parameter name="MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
+  <parameter name="MEM_IF_CS_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CTL_USR_REFRESH" value="0" />
+  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
+  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="MR0_BT" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
+  <parameter name="MR1_AL" value="0" />
+  <parameter name="MR0_BL" value="1" />
+  <parameter name="MEM_TRCD" value="5" />
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MEM_WTCL_INT" value="5" />
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
+  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
+  <parameter name="MR0_DLL" value="1" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="CFG_WRITE_ODT_CHIP" value="1" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="MR2_ASR" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="MR2_CWL" value="0" />
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
+  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
+  <parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
+  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
+  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
+  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
+  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
+  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_TBP_NUM" value="4" />
+  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
+  <parameter name="CFG_ECC_DECODER_REG" value="0" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MR1_RTT" value="0" />
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CSR_DATA_WIDTH" value="32" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_ROM_MR0" value="0001000010001" />
+  <parameter name="MEM_TRAS" value="11" />
+  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="CTL_SELF_REFRESH" value="0" />
+  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
+  <parameter name="AC_ROM_MR2" value="0000000000000" />
+  <parameter name="AC_ROM_MR1" value="0000000000000" />
+  <parameter name="AC_ROM_MR3" value="0000000000000" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
+  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
+  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="CFG_TYPE" value="2" />
+  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
+  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
+  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="CFG_INTERFACE_WIDTH" value="8" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
+  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
+  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
+  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
+  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
+  <parameter name="CFG_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
+  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
+  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="MEM_ATCL_INT" value="0" />
+  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="CSR_BE_WIDTH" value="4" />
+  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
+  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="FLY_BY" value="true" />
+  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
+  <parameter name="DWIDTH_RATIO" value="4" />
+  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
+  <parameter name="CFG_CLR_INTR" value="0" />
+  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
+  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="MEM_TINIT_CK" value="150000" />
+  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
+  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="MEM_TRTP" value="3" />
+  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
+  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
+  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
+  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
+  <parameter name="AFI_CONTROL_WIDTH" value="2" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
+  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
+  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
+  <parameter name="DATA_RATE_RATIO" value="2" />
+  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
+  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
+  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
+  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="LOW_LATENCY" value="false" />
+  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
+  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
+  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="MR1_WL" value="0" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="MR3_MPR_RF" value="0" />
+  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="CFG_STARVE_LIMIT" value="10" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
+  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
+  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
+  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="MEM_BURST_LENGTH" value="8" />
+  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="MEM_TRRD" value="2" />
+  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
+  <parameter name="ADDR_RATE_RATIO" value="1" />
+  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
+  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
+  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
+  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
+  <parameter name="AFI_WRANK_WIDTH" value="2" />
+  <parameter name="LRDIMM" value="false" />
+  <parameter name="MR1_DLL" value="0" />
+  <parameter name="CFG_ADDR_ORDER" value="0" />
+  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CTL_ODT_ENABLED" value="false" />
+  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
+  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
+  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
+  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
+  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
+  <parameter name="AFI_WLAT_WIDTH" value="6" />
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CS_WIDTH" value="1" />
+  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
+  <parameter name="MR1_ODS" value="0" />
+  <parameter name="MEM_TRFC" value="34" />
+  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
+  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
+  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
+  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
+  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
+  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="HARD_PHY" value="false" />
+  <parameter name="MR2_SRF" value="0" />
+  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
+  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
+  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
+  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
+  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="AC_PARITY" value="false" />
+  <parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
+  <parameter name="MR1_DQS" value="0" />
+  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
+  <parameter name="MR2_SRT" value="0" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="ENUM_MEM_IF_TMRD" value="" />
+  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MR1_QOFF" value="0" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
+  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_TYPE" value="DDR3" />
+  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
+  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
+  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
+  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="AVL_ADDR_WIDTH" value="25" />
+  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="MAX10_CFG" value="true" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
+  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
+  <parameter name="AFI_RRANK_WIDTH" value="2" />
+  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="MR3_MPR" value="0" />
+  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
+  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
+  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="AVL_BE_WIDTH" value="4" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
+  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
+  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
+  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
+  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
+  <parameter name="AFI_DM_WIDTH" value="4" />
+  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="USE_SHADOW_REGS" value="false" />
+  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
+  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
+  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
+  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_IF_DQ_WIDTH" value="8" />
+  <parameter name="ADDR_CMD_DDR" value="0" />
+  <parameter name="MR3_MPR_AA" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
+  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
+  <parameter name="AFI_CLK_EN_WIDTH" value="2" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
+  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
+  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
+  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
+  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
+  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
+  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
+  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
+  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="AVL_SIZE_WIDTH" value="3" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
+  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
+  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
+  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter
+     name="CPORT_TYPE_PORT"
+     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
+  <parameter name="AC_ROM_MR1_CALIB" value="" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
+  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
+  <parameter name="AFI_ADDR_WIDTH" value="28" />
+  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
+  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
+  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
+  <parameter name="EXPORT_CSR_PORT" value="false" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="MSB_WFIFO_PORT_0" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MSB_WFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="MSB_WFIFO_PORT_2" value="5" />
+  <parameter name="MSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MSB_WFIFO_PORT_4" value="5" />
+  <parameter name="MSB_WFIFO_PORT_5" value="5" />
+  <parameter name="CFG_TCCD" value="1" />
+  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
+  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
+  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
+  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
+  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
+  <parameter name="SCC_DATA_WIDTH" value="1" />
+  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
+  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="USE_DQS_TRACKING" value="false" />
+  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
+  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
+  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
+  <parameter name="AC_ROM_MR0_CALIB" value="" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
+  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
+  <parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
+  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
+  <parameter name="AFI_RLAT_WIDTH" value="6" />
+  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
+  <parameter name="MEM_TRP" value="5" />
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
+  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
+  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
+  <parameter name="LSB_WFIFO_PORT_4" value="5" />
+  <parameter name="LSB_WFIFO_PORT_5" value="5" />
+  <parameter name="LSB_WFIFO_PORT_2" value="5" />
+  <parameter name="LSB_WFIFO_PORT_3" value="5" />
+  <parameter name="MR0_CAS_LATENCY" value="1" />
+  <parameter name="LSB_WFIFO_PORT_0" value="5" />
+  <parameter name="LSB_WFIFO_PORT_1" value="5" />
+  <parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
+  <parameter name="MR0_WR" value="1" />
+  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
+  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
+  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
+  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
+  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
+  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
+  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
+  <parameter name="PRIORITY_PORT_0" value="0" />
+  <parameter name="MEM_TWR" value="5" />
+  <parameter name="PRIORITY_PORT_2" value="0" />
+  <parameter name="PRIORITY_PORT_1" value="0" />
+  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
+  <parameter name="CPORT_TYPE_PORT_3" value="0" />
+  <parameter name="MEM_IF_DQS_WIDTH" value="1" />
+  <parameter name="CPORT_TYPE_PORT_2" value="0" />
+  <parameter name="CPORT_TYPE_PORT_1" value="0" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="CPORT_TYPE_PORT_0" value="0" />
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="PRIORITY_PORT_4" value="0" />
+  <parameter name="PRIORITY_PORT_3" value="0" />
+  <parameter name="PRIORITY_PORT_5" value="0" />
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
+  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
+  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
+  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
+  <parameter name="CPORT_TYPE_PORT_5" value="0" />
+  <parameter name="CPORT_TYPE_PORT_4" value="0" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
+  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
+  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
+  <parameter name="MEM_TFAW" value="10" />
+  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
+  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
+  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
+  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_list.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv"
+       type="VERILOG_INCLUDE"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram_c0" as="ng0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
+   <message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false"
+   instancePathKey="q_sys:.:ddr3_ram:.:c0:.:a0"
+   kind="alt_mem_ddrx_mm_st_converter"
+   version="19.1"
+   name="alt_mem_ddrx_mm_st_converter">
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="MAX_PENDING_READ_TRANSACTION" value="32" />
+  <parameter name="AVL_DATA_WIDTH" value="32" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="AVL_SIZE_WIDTH" value="3" />
+  <parameter name="AVL_BYTE_ENABLE" value="true" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="AVL_ADDR_WIDTH" value="25" />
+  <parameter name="AVL_NUM_SYMBOLS" value="4" />
+  <parameter name="CFG_DWIDTH_RATIO" value="4" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="q_sys_ddr3_ram_c0" as="a0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
+   <message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD"
+   instancePathKey="q_sys:.:ext_flash:.:soft_asmiblock_instance_name:.:soft_asmiblock_instance_name"
+   kind="soft_asmiblock"
+   version="19.1"
+   name="soft_asmiblock">
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="CS_WIDTH" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_ext_flash_soft_asmiblock_instance_name"
+     as="soft_asmiblock_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
+   <message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true"
+   instancePathKey="q_sys:.:ext_flash:.:asmi_parallel_instance_name:.:asmi_parallel_instance_name"
+   kind="altera_asmi_parallel"
+   version="19.1"
+   name="q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name">
+  <parameter name="PORT_EN4B_ADDR" value="PORT_USED" />
+  <parameter name="USE_EAB" value="ON" />
+  <parameter name="PORT_READ_SID" value="PORT_UNUSED" />
+  <parameter name="gui_read_rdid" value="true" />
+  <parameter name="gui_page_write" value="true" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="PORT_ILLEGAL_WRITE" value="PORT_USED" />
+  <parameter name="FLASH_RSTPIN" value="TRUE" />
+  <parameter name="EPCS_TYPE" value="EPCQL512" />
+  <parameter name="gui_sector_protect" value="true" />
+  <parameter name="PORT_WRITE" value="PORT_USED" />
+  <parameter name="gui_fast_read" value="true" />
+  <parameter name="PORT_SECTOR_ERASE" value="PORT_USED" />
+  <parameter name="DATA_WIDTH" value="QUAD" />
+  <parameter name="gui_read_address" value="false" />
+  <parameter name="gui_sector_erase" value="true" />
+  <parameter name="gui_use_asmiblock" value="true" />
+  <parameter name="PORT_DIE_ERASE" value="PORT_UNUSED" />
+  <parameter name="PORT_WREN" value="PORT_USED" />
+  <parameter name="WRITE_DUMMY_CLK" value="0" />
+  <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+  <parameter name="gui_read_dummyclk" value="true" />
+  <parameter name="gui_single_write" value="false" />
+  <parameter name="gui_die_erase" value="false" />
+  <parameter name="gui_ex4b_addr" value="false" />
+  <parameter name="gui_use_eab" value="false" />
+  <parameter name="PORT_READ_DUMMYCLK" value="PORT_USED" />
+  <parameter name="gui_write" value="true" />
+  <parameter name="PORT_SHIFT_BYTES" value="PORT_USED" />
+  <parameter name="PORT_SECTOR_PROTECT" value="PORT_USED" />
+  <parameter name="gui_bulk_erase" value="false" />
+  <parameter name="PORT_FAST_READ" value="PORT_USED" />
+  <parameter name="ENABLE_SIM" value="true" />
+  <parameter name="PORT_READ_STATUS" value="PORT_USED" />
+  <parameter name="PORT_BULK_ERASE" value="PORT_UNUSED" />
+  <parameter name="PORT_RDID_OUT" value="PORT_USED" />
+  <parameter name="PORT_READ_RDID" value="PORT_USED" />
+  <parameter name="gui_read_status" value="true" />
+  <parameter name="PORT_EX4B_ADDR" value="PORT_UNUSED" />
+  <parameter name="PAGE_SIZE" value="256" />
+  <parameter name="gui_wren" value="true" />
+  <parameter name="gui_read_sid" value="false" />
+  <parameter name="PORT_ILLEGAL_ERASE" value="PORT_USED" />
+  <parameter name="PORT_READ_ADDRESS" value="PORT_UNUSED" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="" />
+  <parameter name="USE_ASMIBLOCK" value="OFF" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_ext_flash_asmi_parallel_instance_name"
+     as="asmi_parallel_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
+   <message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
+   <message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None"
+   instancePathKey="q_sys:.:ext_flash:.:epcq_controller_instance_name:.:epcq_controller_instance_name"
+   kind="altera_epcq_controller_core"
+   version="19.1"
+   name="altera_epcq_controller_arb">
+  <parameter name="ASMI_ADDR_WIDTH" value="32" />
+  <parameter name="ADDR_WIDTH" value="24" />
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="DDASI" value="1" />
+  <parameter name="CS_WIDTH" value="1" />
+  <parameter name="deviceFeaturesSystemInfo" value="None" />
+  <parameter name="ASI_WIDTH" value="4" />
+  <parameter name="ENABLE_4BYTE_ADDR" value="1" />
+  <parameter name="FLASH_TYPE" value="EPCQL512" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
+       type="SYSTEM_VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_ext_flash_epcq_controller_instance_name"
+     as="epcq_controller_instance_name" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
+   <message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="error_adapter:19.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter:.:error_adapter_0"
+   kind="error_adapter"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0">
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="inBitsPerSymbol" value="34" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="inSymbolsPerBeat" value="1" />
+  <parameter name="inUseEmptyPort" value="NO" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="false" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1_avalon_st_adapter"
+     as="error_adapter_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="error_adapter:19.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
+   instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter_020:.:error_adapter_0"
+   kind="error_adapter"
+   version="19.1"
+   name="q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0">
+  <parameter name="inErrorWidth" value="0" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="inBitsPerSymbol" value="18" />
+  <parameter name="inChannelWidth" value="0" />
+  <parameter name="inSymbolsPerBeat" value="1" />
+  <parameter name="inUseEmptyPort" value="NO" />
+  <parameter name="outErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="0" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="outErrorDescriptor" value="" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inUsePackets" value="false" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator
+     instantiator="q_sys_mm_interconnect_1_avalon_st_adapter_020"
+     as="error_adapter_0" />
+  <messages>
+   <message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
+   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/q_sys/q_sys_bb.v b/FPGA_firmware/q_sys/q_sys_bb.v
new file mode 100644
index 0000000..95d10ac
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys_bb.v
@@ -0,0 +1,132 @@
+
+module q_sys (
+	altpll_shift_c0_clk,
+	altpll_shift_locked_conduit_export,
+	button_pio_external_connection_export,
+	clock_bridge_0_in_clk_clk,
+	ddr3_ram_pll_ref_clk_clk,
+	debug_uart_external_connection_rxd,
+	debug_uart_external_connection_txd,
+	enet_pll_c0_clk,
+	enet_pll_c1_clk,
+	enet_pll_c2_clk,
+	enet_pll_c3_clk,
+	enet_pll_c4_clk,
+	enet_pll_locked_conduit_export,
+	eth_tse_mac_mdio_connection_mdc,
+	eth_tse_mac_mdio_connection_mdio_in,
+	eth_tse_mac_mdio_connection_mdio_out,
+	eth_tse_mac_mdio_connection_mdio_oen,
+	eth_tse_mac_rgmii_connection_rgmii_in,
+	eth_tse_mac_rgmii_connection_rgmii_out,
+	eth_tse_mac_rgmii_connection_rx_control,
+	eth_tse_mac_rgmii_connection_tx_control,
+	eth_tse_mac_status_connection_set_10,
+	eth_tse_mac_status_connection_set_1000,
+	eth_tse_mac_status_connection_eth_mode,
+	eth_tse_mac_status_connection_ena_10,
+	eth_tse_pcs_mac_rx_clock_connection_clk,
+	eth_tse_pcs_mac_tx_clock_connection_clk,
+	ext_flash_flash_dataout_conduit_dataout,
+	ext_flash_flash_dclk_out_conduit_dclk_out,
+	ext_flash_flash_ncs_conduit_ncs,
+	frame_timer_export,
+	led_pio_external_connection_export,
+	mem_if_ddr3_emif_0_status_local_init_done,
+	mem_if_ddr3_emif_0_status_local_cal_success,
+	mem_if_ddr3_emif_0_status_local_cal_fail,
+	mem_resetn_in_reset_reset_n,
+	memory_mem_a,
+	memory_mem_ba,
+	memory_mem_ck,
+	memory_mem_ck_n,
+	memory_mem_cke,
+	memory_mem_cs_n,
+	memory_mem_dm,
+	memory_mem_ras_n,
+	memory_mem_cas_n,
+	memory_mem_we_n,
+	memory_mem_reset_n,
+	memory_mem_dq,
+	memory_mem_dqs,
+	memory_mem_dqs_n,
+	memory_mem_odt,
+	reset_reset_n,
+	sensor_in_adc_data,
+	sensor_in_trg,
+	sensor_out_adc_clk,
+	sensor_out_adc_cnv,
+	sensor_out_sensor_clk,
+	sensor_out_sensor_gain,
+	sensor_out_sensor_rst,
+	sensor_status_status_out,
+	sensor_synchro_ext_input,
+	sensor_synchro_serial_rx,
+	sensor_synchro_serial_tx,
+	sys_clk_clk);	
+
+	output		altpll_shift_c0_clk;
+	output		altpll_shift_locked_conduit_export;
+	input	[8:0]	button_pio_external_connection_export;
+	input		clock_bridge_0_in_clk_clk;
+	input		ddr3_ram_pll_ref_clk_clk;
+	input		debug_uart_external_connection_rxd;
+	output		debug_uart_external_connection_txd;
+	output		enet_pll_c0_clk;
+	output		enet_pll_c1_clk;
+	output		enet_pll_c2_clk;
+	output		enet_pll_c3_clk;
+	output		enet_pll_c4_clk;
+	output		enet_pll_locked_conduit_export;
+	output		eth_tse_mac_mdio_connection_mdc;
+	input		eth_tse_mac_mdio_connection_mdio_in;
+	output		eth_tse_mac_mdio_connection_mdio_out;
+	output		eth_tse_mac_mdio_connection_mdio_oen;
+	input	[3:0]	eth_tse_mac_rgmii_connection_rgmii_in;
+	output	[3:0]	eth_tse_mac_rgmii_connection_rgmii_out;
+	input		eth_tse_mac_rgmii_connection_rx_control;
+	output		eth_tse_mac_rgmii_connection_tx_control;
+	input		eth_tse_mac_status_connection_set_10;
+	input		eth_tse_mac_status_connection_set_1000;
+	output		eth_tse_mac_status_connection_eth_mode;
+	output		eth_tse_mac_status_connection_ena_10;
+	input		eth_tse_pcs_mac_rx_clock_connection_clk;
+	input		eth_tse_pcs_mac_tx_clock_connection_clk;
+	inout	[3:0]	ext_flash_flash_dataout_conduit_dataout;
+	output		ext_flash_flash_dclk_out_conduit_dclk_out;
+	output	[0:0]	ext_flash_flash_ncs_conduit_ncs;
+	output		frame_timer_export;
+	output	[7:0]	led_pio_external_connection_export;
+	output		mem_if_ddr3_emif_0_status_local_init_done;
+	output		mem_if_ddr3_emif_0_status_local_cal_success;
+	output		mem_if_ddr3_emif_0_status_local_cal_fail;
+	input		mem_resetn_in_reset_reset_n;
+	output	[13:0]	memory_mem_a;
+	output	[2:0]	memory_mem_ba;
+	inout	[0:0]	memory_mem_ck;
+	inout	[0:0]	memory_mem_ck_n;
+	output	[0:0]	memory_mem_cke;
+	output	[0:0]	memory_mem_cs_n;
+	output	[0:0]	memory_mem_dm;
+	output	[0:0]	memory_mem_ras_n;
+	output	[0:0]	memory_mem_cas_n;
+	output	[0:0]	memory_mem_we_n;
+	output		memory_mem_reset_n;
+	inout	[7:0]	memory_mem_dq;
+	inout	[0:0]	memory_mem_dqs;
+	inout	[0:0]	memory_mem_dqs_n;
+	output	[0:0]	memory_mem_odt;
+	input		reset_reset_n;
+	input	[4:0]	sensor_in_adc_data;
+	input		sensor_in_trg;
+	output		sensor_out_adc_clk;
+	output		sensor_out_adc_cnv;
+	output		sensor_out_sensor_clk;
+	output		sensor_out_sensor_gain;
+	output		sensor_out_sensor_rst;
+	output	[7:0]	sensor_status_status_out;
+	input	[7:0]	sensor_synchro_ext_input;
+	input		sensor_synchro_serial_rx;
+	output		sensor_synchro_serial_tx;
+	input		sys_clk_clk;
+endmodule
diff --git a/FPGA_firmware/q_sys/q_sys_inst.v b/FPGA_firmware/q_sys/q_sys_inst.v
new file mode 100644
index 0000000..6f4c83e
--- /dev/null
+++ b/FPGA_firmware/q_sys/q_sys_inst.v
@@ -0,0 +1,67 @@
+	q_sys u0 (
+		.altpll_shift_c0_clk                         (<connected-to-altpll_shift_c0_clk>),                         //                     altpll_shift_c0.clk
+		.altpll_shift_locked_conduit_export          (<connected-to-altpll_shift_locked_conduit_export>),          //         altpll_shift_locked_conduit.export
+		.button_pio_external_connection_export       (<connected-to-button_pio_external_connection_export>),       //      button_pio_external_connection.export
+		.clock_bridge_0_in_clk_clk                   (<connected-to-clock_bridge_0_in_clk_clk>),                   //               clock_bridge_0_in_clk.clk
+		.ddr3_ram_pll_ref_clk_clk                    (<connected-to-ddr3_ram_pll_ref_clk_clk>),                    //                ddr3_ram_pll_ref_clk.clk
+		.debug_uart_external_connection_rxd          (<connected-to-debug_uart_external_connection_rxd>),          //      debug_uart_external_connection.rxd
+		.debug_uart_external_connection_txd          (<connected-to-debug_uart_external_connection_txd>),          //                                    .txd
+		.enet_pll_c0_clk                             (<connected-to-enet_pll_c0_clk>),                             //                         enet_pll_c0.clk
+		.enet_pll_c1_clk                             (<connected-to-enet_pll_c1_clk>),                             //                         enet_pll_c1.clk
+		.enet_pll_c2_clk                             (<connected-to-enet_pll_c2_clk>),                             //                         enet_pll_c2.clk
+		.enet_pll_c3_clk                             (<connected-to-enet_pll_c3_clk>),                             //                         enet_pll_c3.clk
+		.enet_pll_c4_clk                             (<connected-to-enet_pll_c4_clk>),                             //                         enet_pll_c4.clk
+		.enet_pll_locked_conduit_export              (<connected-to-enet_pll_locked_conduit_export>),              //             enet_pll_locked_conduit.export
+		.eth_tse_mac_mdio_connection_mdc             (<connected-to-eth_tse_mac_mdio_connection_mdc>),             //         eth_tse_mac_mdio_connection.mdc
+		.eth_tse_mac_mdio_connection_mdio_in         (<connected-to-eth_tse_mac_mdio_connection_mdio_in>),         //                                    .mdio_in
+		.eth_tse_mac_mdio_connection_mdio_out        (<connected-to-eth_tse_mac_mdio_connection_mdio_out>),        //                                    .mdio_out
+		.eth_tse_mac_mdio_connection_mdio_oen        (<connected-to-eth_tse_mac_mdio_connection_mdio_oen>),        //                                    .mdio_oen
+		.eth_tse_mac_rgmii_connection_rgmii_in       (<connected-to-eth_tse_mac_rgmii_connection_rgmii_in>),       //        eth_tse_mac_rgmii_connection.rgmii_in
+		.eth_tse_mac_rgmii_connection_rgmii_out      (<connected-to-eth_tse_mac_rgmii_connection_rgmii_out>),      //                                    .rgmii_out
+		.eth_tse_mac_rgmii_connection_rx_control     (<connected-to-eth_tse_mac_rgmii_connection_rx_control>),     //                                    .rx_control
+		.eth_tse_mac_rgmii_connection_tx_control     (<connected-to-eth_tse_mac_rgmii_connection_tx_control>),     //                                    .tx_control
+		.eth_tse_mac_status_connection_set_10        (<connected-to-eth_tse_mac_status_connection_set_10>),        //       eth_tse_mac_status_connection.set_10
+		.eth_tse_mac_status_connection_set_1000      (<connected-to-eth_tse_mac_status_connection_set_1000>),      //                                    .set_1000
+		.eth_tse_mac_status_connection_eth_mode      (<connected-to-eth_tse_mac_status_connection_eth_mode>),      //                                    .eth_mode
+		.eth_tse_mac_status_connection_ena_10        (<connected-to-eth_tse_mac_status_connection_ena_10>),        //                                    .ena_10
+		.eth_tse_pcs_mac_rx_clock_connection_clk     (<connected-to-eth_tse_pcs_mac_rx_clock_connection_clk>),     // eth_tse_pcs_mac_rx_clock_connection.clk
+		.eth_tse_pcs_mac_tx_clock_connection_clk     (<connected-to-eth_tse_pcs_mac_tx_clock_connection_clk>),     // eth_tse_pcs_mac_tx_clock_connection.clk
+		.ext_flash_flash_dataout_conduit_dataout     (<connected-to-ext_flash_flash_dataout_conduit_dataout>),     //             ext_flash_flash_dataout.conduit_dataout
+		.ext_flash_flash_dclk_out_conduit_dclk_out   (<connected-to-ext_flash_flash_dclk_out_conduit_dclk_out>),   //            ext_flash_flash_dclk_out.conduit_dclk_out
+		.ext_flash_flash_ncs_conduit_ncs             (<connected-to-ext_flash_flash_ncs_conduit_ncs>),             //                 ext_flash_flash_ncs.conduit_ncs
+		.frame_timer_export                          (<connected-to-frame_timer_export>),                          //                         frame_timer.export
+		.led_pio_external_connection_export          (<connected-to-led_pio_external_connection_export>),          //         led_pio_external_connection.export
+		.mem_if_ddr3_emif_0_status_local_init_done   (<connected-to-mem_if_ddr3_emif_0_status_local_init_done>),   //           mem_if_ddr3_emif_0_status.local_init_done
+		.mem_if_ddr3_emif_0_status_local_cal_success (<connected-to-mem_if_ddr3_emif_0_status_local_cal_success>), //                                    .local_cal_success
+		.mem_if_ddr3_emif_0_status_local_cal_fail    (<connected-to-mem_if_ddr3_emif_0_status_local_cal_fail>),    //                                    .local_cal_fail
+		.mem_resetn_in_reset_reset_n                 (<connected-to-mem_resetn_in_reset_reset_n>),                 //                 mem_resetn_in_reset.reset_n
+		.memory_mem_a                                (<connected-to-memory_mem_a>),                                //                              memory.mem_a
+		.memory_mem_ba                               (<connected-to-memory_mem_ba>),                               //                                    .mem_ba
+		.memory_mem_ck                               (<connected-to-memory_mem_ck>),                               //                                    .mem_ck
+		.memory_mem_ck_n                             (<connected-to-memory_mem_ck_n>),                             //                                    .mem_ck_n
+		.memory_mem_cke                              (<connected-to-memory_mem_cke>),                              //                                    .mem_cke
+		.memory_mem_cs_n                             (<connected-to-memory_mem_cs_n>),                             //                                    .mem_cs_n
+		.memory_mem_dm                               (<connected-to-memory_mem_dm>),                               //                                    .mem_dm
+		.memory_mem_ras_n                            (<connected-to-memory_mem_ras_n>),                            //                                    .mem_ras_n
+		.memory_mem_cas_n                            (<connected-to-memory_mem_cas_n>),                            //                                    .mem_cas_n
+		.memory_mem_we_n                             (<connected-to-memory_mem_we_n>),                             //                                    .mem_we_n
+		.memory_mem_reset_n                          (<connected-to-memory_mem_reset_n>),                          //                                    .mem_reset_n
+		.memory_mem_dq                               (<connected-to-memory_mem_dq>),                               //                                    .mem_dq
+		.memory_mem_dqs                              (<connected-to-memory_mem_dqs>),                              //                                    .mem_dqs
+		.memory_mem_dqs_n                            (<connected-to-memory_mem_dqs_n>),                            //                                    .mem_dqs_n
+		.memory_mem_odt                              (<connected-to-memory_mem_odt>),                              //                                    .mem_odt
+		.reset_reset_n                               (<connected-to-reset_reset_n>),                               //                               reset.reset_n
+		.sensor_in_adc_data                          (<connected-to-sensor_in_adc_data>),                          //                              sensor.in_adc_data
+		.sensor_in_trg                               (<connected-to-sensor_in_trg>),                               //                                    .in_trg
+		.sensor_out_adc_clk                          (<connected-to-sensor_out_adc_clk>),                          //                                    .out_adc_clk
+		.sensor_out_adc_cnv                          (<connected-to-sensor_out_adc_cnv>),                          //                                    .out_adc_cnv
+		.sensor_out_sensor_clk                       (<connected-to-sensor_out_sensor_clk>),                       //                                    .out_sensor_clk
+		.sensor_out_sensor_gain                      (<connected-to-sensor_out_sensor_gain>),                      //                                    .out_sensor_gain
+		.sensor_out_sensor_rst                       (<connected-to-sensor_out_sensor_rst>),                       //                                    .out_sensor_rst
+		.sensor_status_status_out                    (<connected-to-sensor_status_status_out>),                    //                       sensor_status.status_out
+		.sensor_synchro_ext_input                    (<connected-to-sensor_synchro_ext_input>),                    //                      sensor_synchro.ext_input
+		.sensor_synchro_serial_rx                    (<connected-to-sensor_synchro_serial_rx>),                    //                                    .serial_rx
+		.sensor_synchro_serial_tx                    (<connected-to-sensor_synchro_serial_tx>),                    //                                    .serial_tx
+		.sys_clk_clk                                 (<connected-to-sys_clk_clk>)                                  //                             sys_clk.clk
+	);
+
diff --git a/FPGA_firmware/q_sys/sensor_algo.bsf b/FPGA_firmware/q_sys/sensor_algo.bsf
new file mode 100644
index 0000000..a9ae241
--- /dev/null
+++ b/FPGA_firmware/q_sys/sensor_algo.bsf
@@ -0,0 +1,38 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 64)
+	(text "sensor_algo" (rect 13 -1 61 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 48 20 60)(font "Arial" ))
+	(drawing
+		(text " system " (rect 45 48 138 106)(font "Arial" ))
+		(line (pt 16 32)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 80 48)(line_width 1))
+		(line (pt 16 48)(pt 80 48)(line_width 1))
+		(line (pt 16 32)(pt 16 48)(line_width 1))
+		(line (pt 0 0)(pt 97 0)(line_width 1))
+		(line (pt 97 0)(pt 97 64)(line_width 1))
+		(line (pt 0 64)(pt 97 64)(line_width 1))
+		(line (pt 0 0)(pt 0 64)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/q_sys/sensor_algo.xml b/FPGA_firmware/q_sys/sensor_algo.xml
new file mode 100644
index 0000000..f2d4ad8
--- /dev/null
+++ b/FPGA_firmware/q_sys/sensor_algo.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.17.13:03:39"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="sensor_algo_0_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="sensor_algo_0_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="sensor_algo_0_rst" kind="reset" start="0">
+   <property name="associatedClock" value="sensor_algo_0_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="sensor_algo_0_rst_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="sensor_algo:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1721214219,AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN=-1,AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE=-1,AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(sensor_algo:1.0:)"
+   instancePathKey="sensor_algo"
+   kind="sensor_algo"
+   version="1.0"
+   name="sensor_algo">
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1721214219" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
+       type="VERILOG" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
+  </childSourceFiles>
+  <instantiator instantiator="sensor_algo" as="sensor_algo_0" />
+  <messages>
+   <message level="Debug" culprit="sensor_algo">queue size: 0 starting:sensor_algo "sensor_algo"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="sensor_algo"><![CDATA["<b>sensor_algo</b>" reuses <b>sensor_algo</b> "<b>sensor_algo</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/q_sys/sensor_algo_bb.v b/FPGA_firmware/q_sys/sensor_algo_bb.v
new file mode 100644
index 0000000..a5cda4d
--- /dev/null
+++ b/FPGA_firmware/q_sys/sensor_algo_bb.v
@@ -0,0 +1,5 @@
+
+module sensor_algo (
+	);	
+
+endmodule
diff --git a/FPGA_firmware/q_sys/sensor_algo_inst.v b/FPGA_firmware/q_sys/sensor_algo_inst.v
new file mode 100644
index 0000000..2b9006c
--- /dev/null
+++ b/FPGA_firmware/q_sys/sensor_algo_inst.v
@@ -0,0 +1,3 @@
+	sensor_algo u0 (
+	);
+
diff --git a/FPGA_firmware/q_sys/st_splitter16.bsf b/FPGA_firmware/q_sys/st_splitter16.bsf
new file mode 100644
index 0000000..e56f5bb
--- /dev/null
+++ b/FPGA_firmware/q_sys/st_splitter16.bsf
@@ -0,0 +1,213 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 480 304)
+	(text "st_splitter16" (rect 205 -1 251 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 288 20 300)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "st_splitter16_clk_clk" (rect 0 0 79 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_clk_clk" (rect 4 61 130 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 160 72)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "st_splitter16_in_valid" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_valid" (rect 4 117 136 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 160 128)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "st_splitter16_in_startofpacket" (rect 0 0 115 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_startofpacket" (rect 4 133 184 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 160 144)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "st_splitter16_in_endofpacket" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_endofpacket" (rect 4 149 172 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 160 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "st_splitter16_in_empty" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_empty" (rect 4 165 136 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 160 176)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "st_splitter16_in_data[15..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_data[15..0]" (rect 4 181 172 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 160 192)(line_width 3))
+	)
+	(port
+		(pt 480 72)
+		(input)
+		(text "st_splitter16_out0_ready" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_ready" (rect 357 61 501 72)(font "Arial" (font_size 8)))
+		(line (pt 480 72)(pt 304 72)(line_width 1))
+	)
+	(port
+		(pt 480 192)
+		(input)
+		(text "st_splitter16_out1_ready" (rect 0 0 96 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_ready" (rect 359 181 503 192)(font "Arial" (font_size 8)))
+		(line (pt 480 192)(pt 304 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "st_splitter16_reset_reset" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_reset_reset" (rect 4 221 154 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 160 232)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(output)
+		(text "st_splitter16_in_ready" (rect 0 0 87 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_ready" (rect 4 101 136 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 160 112)(line_width 1))
+	)
+	(port
+		(pt 480 88)
+		(output)
+		(text "st_splitter16_out0_valid" (rect 0 0 92 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_valid" (rect 363 77 507 88)(font "Arial" (font_size 8)))
+		(line (pt 480 88)(pt 304 88)(line_width 1))
+	)
+	(port
+		(pt 480 104)
+		(output)
+		(text "st_splitter16_out0_startofpacket" (rect 0 0 126 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_startofpacket" (rect 320 93 512 104)(font "Arial" (font_size 8)))
+		(line (pt 480 104)(pt 304 104)(line_width 1))
+	)
+	(port
+		(pt 480 120)
+		(output)
+		(text "st_splitter16_out0_endofpacket" (rect 0 0 122 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_endofpacket" (rect 324 109 504 120)(font "Arial" (font_size 8)))
+		(line (pt 480 120)(pt 304 120)(line_width 1))
+	)
+	(port
+		(pt 480 136)
+		(output)
+		(text "st_splitter16_out0_empty" (rect 0 0 100 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_empty" (rect 356 125 500 136)(font "Arial" (font_size 8)))
+		(line (pt 480 136)(pt 304 136)(line_width 1))
+	)
+	(port
+		(pt 480 152)
+		(output)
+		(text "st_splitter16_out0_data[15..0]" (rect 0 0 114 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_data[15..0]" (rect 336 141 516 152)(font "Arial" (font_size 8)))
+		(line (pt 480 152)(pt 304 152)(line_width 3))
+	)
+	(port
+		(pt 480 208)
+		(output)
+		(text "st_splitter16_out1_valid" (rect 0 0 90 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_valid" (rect 365 197 509 208)(font "Arial" (font_size 8)))
+		(line (pt 480 208)(pt 304 208)(line_width 1))
+	)
+	(port
+		(pt 480 224)
+		(output)
+		(text "st_splitter16_out1_startofpacket" (rect 0 0 125 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_startofpacket" (rect 322 213 514 224)(font "Arial" (font_size 8)))
+		(line (pt 480 224)(pt 304 224)(line_width 1))
+	)
+	(port
+		(pt 480 240)
+		(output)
+		(text "st_splitter16_out1_endofpacket" (rect 0 0 121 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_endofpacket" (rect 326 229 506 240)(font "Arial" (font_size 8)))
+		(line (pt 480 240)(pt 304 240)(line_width 1))
+	)
+	(port
+		(pt 480 256)
+		(output)
+		(text "st_splitter16_out1_empty" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_empty" (rect 358 245 502 256)(font "Arial" (font_size 8)))
+		(line (pt 480 256)(pt 304 256)(line_width 1))
+	)
+	(port
+		(pt 480 272)
+		(output)
+		(text "st_splitter16_out1_data[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_data[15..0]" (rect 338 261 518 272)(font "Arial" (font_size 8)))
+		(line (pt 480 272)(pt 304 272)(line_width 3))
+	)
+	(drawing
+		(text "st_splitter16_clk" (rect 66 43 234 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_in" (rect 72 83 240 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 165 107 360 224)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 165 123 360 256)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 165 139 408 288)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 165 155 396 320)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 165 171 360 352)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 165 187 354 384)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_out0" (rect 305 43 718 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 281 83 592 176)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 244 99 566 208)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 249 115 564 240)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 274 131 578 272)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 283 147 590 304)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_out1" (rect 305 163 718 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 276 187 582 384)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 281 203 592 416)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 244 219 566 448)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 249 235 564 480)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 274 251 578 512)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 283 267 590 544)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_reset" (rect 52 203 218 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 227 360 464)(font "Arial" (color 0 0 0)))
+		(text " st_splitter16 " (rect 425 288 940 586)(font "Arial" ))
+		(line (pt 160 32)(pt 304 32)(line_width 1))
+		(line (pt 304 32)(pt 304 288)(line_width 1))
+		(line (pt 160 288)(pt 304 288)(line_width 1))
+		(line (pt 160 32)(pt 160 288)(line_width 1))
+		(line (pt 161 52)(pt 161 76)(line_width 1))
+		(line (pt 162 52)(pt 162 76)(line_width 1))
+		(line (pt 161 92)(pt 161 196)(line_width 1))
+		(line (pt 162 92)(pt 162 196)(line_width 1))
+		(line (pt 303 52)(pt 303 156)(line_width 1))
+		(line (pt 302 52)(pt 302 156)(line_width 1))
+		(line (pt 303 172)(pt 303 276)(line_width 1))
+		(line (pt 302 172)(pt 302 276)(line_width 1))
+		(line (pt 161 212)(pt 161 236)(line_width 1))
+		(line (pt 162 212)(pt 162 236)(line_width 1))
+		(line (pt 0 0)(pt 480 0)(line_width 1))
+		(line (pt 480 0)(pt 480 304)(line_width 1))
+		(line (pt 0 304)(pt 480 304)(line_width 1))
+		(line (pt 0 0)(pt 0 304)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/q_sys/st_splitter16.xml b/FPGA_firmware/q_sys/st_splitter16.xml
new file mode 100644
index 0000000..d7f08d2
--- /dev/null
+++ b/FPGA_firmware/q_sys/st_splitter16.xml
@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.02.15:16:06"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="st_splitter16_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="st_splitter16_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="st_splitter16_in" kind="avalon_streaming" start="0">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_in_ready"
+       direction="output"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_in_valid"
+       direction="input"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_in_startofpacket"
+       direction="input"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_in_endofpacket"
+       direction="input"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_in_empty"
+       direction="input"
+       role="empty"
+       width="1" />
+   <port name="st_splitter16_in_data" direction="input" role="data" width="16" />
+  </interface>
+  <interface name="st_splitter16_out0" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_out0_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_out0_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_out0_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out0_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out0_empty"
+       direction="output"
+       role="empty"
+       width="1" />
+   <port
+       name="st_splitter16_out0_data"
+       direction="output"
+       role="data"
+       width="16" />
+  </interface>
+  <interface name="st_splitter16_out1" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_out1_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_out1_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_out1_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out1_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out1_empty"
+       direction="output"
+       role="empty"
+       width="1" />
+   <port
+       name="st_splitter16_out1_data"
+       direction="output"
+       role="data"
+       width="16" />
+  </interface>
+  <interface name="st_splitter16_reset" kind="reset" start="0">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="st_splitter16_reset_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="st_splitter16:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1719926165,AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN=-1,AUTO_ST_SPLITTER16_CLK_CLOCK_RATE=-1,AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1)"
+   instancePathKey="st_splitter16"
+   kind="st_splitter16"
+   version="1.0"
+   name="st_splitter16">
+  <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1719926165" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN" value="-1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/st_splitter16.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:st_splitter16 "st_splitter16"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" reuses <b>altera_avalon_st_splitter</b> "<b>submodules/altera_avalon_st_splitter</b>"]]></message>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
+   <message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1"
+   instancePathKey="st_splitter16:.:st_splitter16"
+   kind="altera_avalon_st_splitter"
+   version="19.1"
+   name="altera_avalon_st_splitter">
+  <parameter name="NUMBER_OF_OUTPUTS" value="2" />
+  <parameter name="USE_DATA" value="1" />
+  <parameter name="ERROR_DESCRIPTOR" value="" />
+  <parameter name="USE_PACKETS" value="1" />
+  <parameter name="USE_READY" value="1" />
+  <parameter name="MAX_CHANNELS" value="1" />
+  <parameter name="USE_ERROR" value="0" />
+  <parameter name="EMPTY_WIDTH" value="1" />
+  <parameter name="CHANNEL_WIDTH" value="1" />
+  <parameter name="READY_LATENCY" value="0" />
+  <parameter name="DATA_WIDTH" value="16" />
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="QUALIFY_VALID_OUT" value="1" />
+  <parameter name="USE_VALID" value="1" />
+  <parameter name="USE_CHANNEL" value="0" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="st_splitter16" as="st_splitter16" />
+  <messages>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
+   <message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/q_sys/st_splitter16_bb.v b/FPGA_firmware/q_sys/st_splitter16_bb.v
new file mode 100644
index 0000000..30904bd
--- /dev/null
+++ b/FPGA_firmware/q_sys/st_splitter16_bb.v
@@ -0,0 +1,44 @@
+
+module st_splitter16 (
+	st_splitter16_clk_clk,
+	st_splitter16_reset_reset,
+	st_splitter16_in_ready,
+	st_splitter16_in_valid,
+	st_splitter16_in_startofpacket,
+	st_splitter16_in_endofpacket,
+	st_splitter16_in_empty,
+	st_splitter16_in_data,
+	st_splitter16_out0_ready,
+	st_splitter16_out0_valid,
+	st_splitter16_out0_startofpacket,
+	st_splitter16_out0_endofpacket,
+	st_splitter16_out0_empty,
+	st_splitter16_out0_data,
+	st_splitter16_out1_ready,
+	st_splitter16_out1_valid,
+	st_splitter16_out1_startofpacket,
+	st_splitter16_out1_endofpacket,
+	st_splitter16_out1_empty,
+	st_splitter16_out1_data);	
+
+	input		st_splitter16_clk_clk;
+	input		st_splitter16_reset_reset;
+	output		st_splitter16_in_ready;
+	input		st_splitter16_in_valid;
+	input		st_splitter16_in_startofpacket;
+	input		st_splitter16_in_endofpacket;
+	input	[0:0]	st_splitter16_in_empty;
+	input	[15:0]	st_splitter16_in_data;
+	input		st_splitter16_out0_ready;
+	output		st_splitter16_out0_valid;
+	output		st_splitter16_out0_startofpacket;
+	output		st_splitter16_out0_endofpacket;
+	output	[0:0]	st_splitter16_out0_empty;
+	output	[15:0]	st_splitter16_out0_data;
+	input		st_splitter16_out1_ready;
+	output		st_splitter16_out1_valid;
+	output		st_splitter16_out1_startofpacket;
+	output		st_splitter16_out1_endofpacket;
+	output	[0:0]	st_splitter16_out1_empty;
+	output	[15:0]	st_splitter16_out1_data;
+endmodule
diff --git a/FPGA_firmware/q_sys/st_splitter16_inst.v b/FPGA_firmware/q_sys/st_splitter16_inst.v
new file mode 100644
index 0000000..45a2827
--- /dev/null
+++ b/FPGA_firmware/q_sys/st_splitter16_inst.v
@@ -0,0 +1,23 @@
+	st_splitter16 u0 (
+		.st_splitter16_clk_clk            (<connected-to-st_splitter16_clk_clk>),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (<connected-to-st_splitter16_reset_reset>),        // st_splitter16_reset.reset
+		.st_splitter16_in_ready           (<connected-to-st_splitter16_in_ready>),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (<connected-to-st_splitter16_in_valid>),           //                    .valid
+		.st_splitter16_in_startofpacket   (<connected-to-st_splitter16_in_startofpacket>),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (<connected-to-st_splitter16_in_endofpacket>),     //                    .endofpacket
+		.st_splitter16_in_empty           (<connected-to-st_splitter16_in_empty>),           //                    .empty
+		.st_splitter16_in_data            (<connected-to-st_splitter16_in_data>),            //                    .data
+		.st_splitter16_out0_ready         (<connected-to-st_splitter16_out0_ready>),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (<connected-to-st_splitter16_out0_valid>),         //                    .valid
+		.st_splitter16_out0_startofpacket (<connected-to-st_splitter16_out0_startofpacket>), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (<connected-to-st_splitter16_out0_endofpacket>),   //                    .endofpacket
+		.st_splitter16_out0_empty         (<connected-to-st_splitter16_out0_empty>),         //                    .empty
+		.st_splitter16_out0_data          (<connected-to-st_splitter16_out0_data>),          //                    .data
+		.st_splitter16_out1_ready         (<connected-to-st_splitter16_out1_ready>),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (<connected-to-st_splitter16_out1_valid>),         //                    .valid
+		.st_splitter16_out1_startofpacket (<connected-to-st_splitter16_out1_startofpacket>), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (<connected-to-st_splitter16_out1_endofpacket>),   //                    .endofpacket
+		.st_splitter16_out1_empty         (<connected-to-st_splitter16_out1_empty>),         //                    .empty
+		.st_splitter16_out1_data          (<connected-to-st_splitter16_out1_data>)           //                    .data
+	);
+
diff --git a/FPGA_firmware/q_sys/synthesis/q_sys.debuginfo b/FPGA_firmware/q_sys/synthesis/q_sys.debuginfo
new file mode 100644
index 0000000..77f8429
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/q_sys.debuginfo
@@ -0,0 +1,63314 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="q_sys" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.10.11.10:10:45 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1728634208</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value>hit20v3.qpf</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module name="altpll_shift" kind="altpll" version="19.1" path="altpll_shift">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_elaboration</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_post_edit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTENDED_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_CLOCK">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIMARY_CLOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>20000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK1_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OPERATION_MODE">
+   <type>java.lang.String</type>
+   <value>NORMAL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_CONF_DONE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMPENSATE_CLOCK">
+   <type>java.lang.String</type>
+   <value>CLK0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_SIGNAL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_HIGH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_LOW">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INVALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_LOSSCLK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_VCO">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_TYPE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FEEDBACK_SOURCE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPREAD_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DOWN_SPREAD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>15000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena2">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena3">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk6">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk7">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk8">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk9">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATAOUT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ACTIVECLOCK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKLOSS">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBIN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PLLENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKSWITCH">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ARESET">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PFDENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANACLR">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANREAD">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANWRITE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_LOCKED">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CONFIGUPDATE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBOUT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASESTEP">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEUPDOWN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLKENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOOVERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOUNDERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_FREQUENCY_CONTROL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_PHASE_SHIFT_STEP">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USING_FBMIMICBIDIR_PORT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN_MIF_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK">
+   <type>java.lang.String</type>
+   <value>NO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CONSTANTS">
+   <type>java.lang.String</type>
+   <value>CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_PRIVATES">
+   <type>java.lang.String</type>
+   <value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_USED_PORTS">
+   <type>java.lang.String</type>
+   <value>UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_NUMERIC">
+   <type>java.lang.String</type>
+   <value>IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_MF_PORTS">
+   <type>java.lang.String</type>
+   <value>MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IF_PORTS">
+   <type>java.lang.String</type>
+   <value>IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>inclk_interface</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="inclk_interface" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="inclk_interface_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="pll_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>inclk_interface_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface name="c0" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>250000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="areset_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>areset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+  <interface name="locked_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="button_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   path="button_pio">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CAPTURE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>9</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EDGE_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_IN</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_OUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_TRI</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IRQ_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,pio-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>gpio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>pio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,gpio-bank-width</name>
+   <value>9</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.resetvalue</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="bitClearingEdgeCapReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitModifyingOutReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="captureEdge">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="direction">
+   <type>java.lang.String</type>
+   <value>Input</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="edgeType">
+   <type>java.lang.String</type>
+   <value>RISING</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateIRQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="irqType">
+   <type>java.lang.String</type>
+   <value>LEVEL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDoTestBenchWiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDrivenValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="width">
+   <type>int</type>
+   <value>9</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="derived_has_tri">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_out">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_in">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_do_test_bench_wiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_capture">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_edge_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_irq_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_irq">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>4</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_port</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="calibration_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="calibration_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>q_sys_calibration_ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>640</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>16</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>q_sys_calibration_ram</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>onchip_mem.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>640</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_calibration_ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>q_sys_calibration_ram.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="s2" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address2</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>chipselect2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>clken2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>write2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata2</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata2</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable2</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk2" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset2" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="channel_adapter_0"
+   kind="channel_adapter"
+   version="19.1"
+   path="channel_adapter_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="inChannelWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inMaxChannel">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outMaxChannel">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inBitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>java.lang.String</type>
+   <value>YES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmpty">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inSymbolsPerBeat">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseReady">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inReadyLatency">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>in_channel</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>channel</role>
+   </port>
+  </interface>
+  <interface name="out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module name="cpu" kind="altera_nios2_gen2" version="19.1" path="cpu">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>debug.hostConnection</name>
+   <value>type jtag id 70:34|110:135</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIG_ENDIAN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BREAK_ADDR</name>
+   <value>0x18402820</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_FREQ</name>
+   <value>50000000u</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ID_SIZE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_ID_VALUE</name>
+   <value>0x00000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CPU_IMPLEMENTATION</name>
+   <value>"fast"</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
+   <value>29</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_BYPASS_MASK</name>
+   <value>0x80000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DCACHE_SIZE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EXCEPTION_ADDR</name>
+   <value>0x08000120</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_DEBUG_CORE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_DEBUG_STUB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_LINE_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ICACHE_SIZE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INITDA_SUPPORTED</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
+   <value>29</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.OCI_VERSION</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_ADDR</name>
+   <value>0x14000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.DataCacheVictimBufImpl</name>
+   <value>ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.HDLSimCachesCleared</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.breakOffset</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.breakSlave</name>
+   <value>cpu.debug_mem_slave</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.cpuArchitecture</name>
+   <value>Nios II</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.exceptionOffset</name>
+   <value>288</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.exceptionSlave</name>
+   <value>ddr3_ram.avl</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.resetOffset</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.configuration.resetSlave</name>
+   <value>ext_flash.avl_mem</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,nios2-1.1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>cpu</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>nios2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,exception-addr</name>
+   <value>0x08000120</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,has-initda</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,has-mul</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,implementation</name>
+   <value>"fast"</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,reset-addr</name>
+   <value>0x14000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000u</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.dcache-line-size</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.dcache-size</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.icache-line-size</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.icache-size</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="tmr_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_disable_tmr_inj">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_showUnpublishedSettings">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_showInternalSettings">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_preciseIllegalMemAccessException">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportPCB">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportdebuginfo">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_clearXBitsLDNonBypass">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bigEndian">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_export_large_RAMs">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="register_file_por">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_synopsys_translate_on_off">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_third_party_synthesis">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_asic_add_scan_mode_input">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_oci_version">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_fast_register_read">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportHostDebugPort">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_oci_export_jtag_signals">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_avalonDebugPortPresent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_alwaysEncrypt">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="io_regionbase">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="io_regionsize">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_support31bitdcachebypass">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateTrace">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_allow_break_inst">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateTestEndChecker">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ecc_sim_test_ports">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_disableocitrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_activateMonitors">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_HDLSimCachesCleared">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_HBreakTest">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_breakslaveoveride">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_useLimit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_autoAssignTlbPtrSz">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuReset">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_removeRAMinit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_tmr_output_disable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_shadowRegisterSets">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_numOfInstRegion">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_numOfDataRegion">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcOffset">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOffset">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionOffset">
+   <type>int</type>
+   <value>288</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuID">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakOffset">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="userDefinedSettings">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tracefilename">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetSlave">
+   <type>java.lang.String</type>
+   <value>ext_flash.avl_mem</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcSlave">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionSlave">
+   <type>java.lang.String</type>
+   <value>ddr3_ram.avl</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakSlave">
+   <type>java.lang.String</type>
+   <value>cpu.jtag_debug_module</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_interruptControllerType">
+   <type>java.lang.String</type>
+   <value>Internal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_branchpredictiontype">
+   <type>java.lang.String</type>
+   <value>Dynamic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bhtPtrSz">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cpuArchRev">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stratix_dspblock_shift_mul">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="shifterType">
+   <type>java.lang.String</type>
+   <value>fast_le_shift</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="multiplierType">
+   <type>java.lang.String</type>
+   <value>mul_fast32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_shift_choice">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_32_impl">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mul_64_impl">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="shift_rot_impl">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dividerType">
+   <type>java.lang.String</type>
+   <value>no_div</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_minInstRegionSize">
+   <type>int</type>
+   <value>12</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpu_minDataRegionSize">
+   <type>int</type>
+   <value>12</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_uitlbNumEntries">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_udtlbNumEntries">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_tlbPtrSz">
+   <type>int</type>
+   <value>7</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_tlbNumWays">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_processIDNumBits">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="impl">
+   <type>java.lang.String</type>
+   <value>Fast</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_size">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fa_cache_line">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fa_cache_linesize">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_tagramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_numTCIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="icache_burstType">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_bursts">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_victim_buf_impl">
+   <type>java.lang.String</type>
+   <value>ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_size">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_tagramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_numTCDM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_exportvectors">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_usedesignware">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ic_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_rf_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_mmu_ecc_present">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_dc_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_itcm_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_dtcm_ecc_present">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="regfile_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ocimem_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ocimem_ramInit">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bht_ramBlockType">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="cdx_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mpx_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_triggerArming">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_debugReqSignals">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_assignJtagInstanceID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_jtagInstanceID">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_OCIOnchipTrace">
+   <type>java.lang.String</type>
+   <value>_128</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_hwbreakpoint">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_datatrigger">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_traceType">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_traceStorage">
+   <type>java.lang.String</type>
+   <value>onchip_trace</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="master_addr_map">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="flash_instruction_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="flash_instruction_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_0_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_0_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_1_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_1_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_2_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_2_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_3_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tightly_coupled_data_master_3_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_high_performance_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instruction_master_high_performance_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_high_performance_paddr_base">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="data_master_high_performance_paddr_size">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetAbsoluteAddr">
+   <type>int</type>
+   <value>335544320</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="exceptionAbsoluteAddr">
+   <type>int</type>
+   <value>134218016</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakAbsoluteAddr">
+   <type>int</type>
+   <value>406857760</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mmu_TLBMissExcAbsAddr">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_bursts_derived">
+   <type>java.lang.String</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_size_derived">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="breakSlave_derived">
+   <type>java.lang.String</type>
+   <value>cpu.debug_mem_slave</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dcache_lineSize_derived">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_ioregionBypassDCache">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="setting_bit31BypassDCache">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="translate_on">
+   <type>java.lang.String</type>
+   <value> "synthesis translate_on"  </value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="translate_off">
+   <type>java.lang.String</type>
+   <value> "synthesis translate_off" </value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_onchiptrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_offchiptrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_insttrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="debug_datatrace">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instAddrWidth">
+   <type>int</type>
+   <value>29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="faAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>flash_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="dataAddrWidth">
+   <type>int</type>
+   <value>29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>data_master</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster0AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster1AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster2AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster3AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="dataMasterHighPerformanceAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>data_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instSlaveMapParam">
+   <type>java.lang.String</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="faSlaveMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>flash_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="dataSlaveMapParam">
+   <type>java.lang.String</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>data_master</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster1MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster2MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledDataMaster3MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster0MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster1MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster2MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
+  </parameter>
+  <parameter name="tightlyCoupledInstructionMaster3MapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
+  </parameter>
+  <parameter name="dataMasterHighPerformanceMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>data_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="instructionMasterHighPerformanceMapParam">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
+  </parameter>
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamilyName">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="internalIrqMaskSystemInfo">
+   <type>long</type>
+   <value>61</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>INTERRUPTS_USED</sysinfo_type>
+   <sysinfo_arg>irq</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_a">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_a</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_b">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_b</sysinfo_arg>
+  </parameter>
+  <parameter name="customInstSlavesSystemInfo_nios_c">
+   <type>java.lang.String</type>
+   <value><![CDATA[<info/>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
+   <sysinfo_arg>custom_instruction_master_c</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFeaturesSystemInfo">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN">
+   <type>java.lang.Integer</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_CLK_RESET_DOMAIN">
+   <type>java.lang.Integer</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+  <interface name="data_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>debug.providesServices</name>
+    <value>master</value>
+   </assignment>
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>d_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>d_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>d_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>d_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>d_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>d_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>d_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>d_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_debugaccess_to_roms</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>cpu_data_master</slaveName>
+    <name>mm_interconnect_1.cpu_data_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="instruction_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>i_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>i_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>i_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>i_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>i_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>cpu_instruction_master</slaveName>
+    <name>mm_interconnect_1.cpu_instruction_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="irq" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>cpu.data_master</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>irq_mapper</moduleName>
+    <slaveName>sender</slaveName>
+    <name>irq_mapper.sender</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="debug_reset_request" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>none</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>debug_reset_request</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="debug_mem_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.hideDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>qsys.ui.connect</name>
+    <value>instruction_master,data_master</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>2048</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>debug_mem_slave_address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_debugaccess</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>debug_mem_slave_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface
+     name="custom_instruction_master"
+     kind="nios_custom_instruction_master"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="CIName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressWidth">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockCycle">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="enabled">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="opcodeExtension">
+    <type>int</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="sharedCombinationalAndMulticycle">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>nios_custom_instruction</type>
+   <isStart>true</isStart>
+   <port>
+    <name>dummy_ci_port</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readra</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="19.1"
+   path="ddr3_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>ABS_RAM_MEM_INIT_FILENAME</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.map.memory</name>
+   <value>mem_model.memory</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.class</name>
+   <value>altera_mem_if_ddr3_mem_model</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_PARITY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0</name>
+   <value>0001000010001</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_CALIB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET</name>
+   <value>0001100010000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_DLL_RESET_MIRR</name>
+   <value>0001010001000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR0_MIRR</name>
+   <value>0001000001001</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_CALIB</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR1_OCD_ENABLE</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR2</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR2_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR3</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AC_ROM_MR3_MIRR</name>
+   <value>0000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ADDR_CMD_DDR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ADDR_RATE_RATIO</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_ADDR_WIDTH</name>
+   <value>28</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_BANKADDR_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CLK_EN_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CLK_PAIR_COUNT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CONTROL_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_CS_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_DM_WIDTH</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_DQ_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_ODT_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RATE_RATIO</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RLAT_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_RRANK_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WLAT_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WRANK_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AFI_WRITE_DQS_WIDTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.ALTMEMPHY_COMPATIBLE_MODE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AP_MODE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.AP_MODE_EN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CFG_TCCD</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CFG_TCCD_NS</name>
+   <value>2.5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_PCH_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_RD_TO_RD_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CTL_WR_TO_WR_EXTRA_CLK</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.CUT_NEW_FAMILY_TIMING</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DATA_RATE_RATIO</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DAT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_DEPTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_FAMILY</name>
+   <value>MAX 10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_FAMILY_PARAM</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DEVICE_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DISABLE_CHILD_MESSAGING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DISCRETE_FLY_BY</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DQ_DDR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.DUPLICATE_AC</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FLY_BY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FORCE_DQS_TRACKING</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.FORCE_SHADOW_REGS</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HARD_EMIF</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HARD_PHY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS_SIMULATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HHP_HPS_VERIFICATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.HPS_PROTOCOL</name>
+   <value>DEFAULT</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.IS_ES_DEVICE</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM_EXTENDED_CONFIG</name>
+   <value>0x000000000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.LRDIMM_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ASR</name>
+   <value>Manual</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ATCL</name>
+   <value>Disabled</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ATCL_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_AUTO_LEVELING_MODE</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BANKADDR_WIDTH</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BL</name>
+   <value>OTF</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BT</name>
+   <value>Sequential</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_BURST_LENGTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CK_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_EN_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_FREQ</name>
+   <value>300.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_FREQ_MAX</name>
+   <value>800.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_MAX_NS</name>
+   <value>1.25</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_MAX_PS</name>
+   <value>1250.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CLK_TO_DQS_CAPTURE_DELAY</name>
+   <value>100000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_COL_ADDR_WIDTH</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_CS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DLL_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQS_TO_CLK_CAPTURE_DELAY</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQ_PER_DQS</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DQ_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_DRV_STR</name>
+   <value>RZQ/6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_FORMAT</name>
+   <value>DISCRETE</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_GUARANTEED_WRITE_INIT</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ADDR_WIDTH_MIN</name>
+   <value>13</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_BANKADDR_WIDTH</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_BOARD_BASE_DELAY</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CHIP_BITS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CK_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CLK_EN_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CLK_PAIR_COUNT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_COL_ADDR_WIDTH</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CONTROL_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_PER_DIMM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_PER_RANK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_CS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DM_PINS_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DM_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQSN_EN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_DQ_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_LRDIMM_RM</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_NUMBER_OF_RANKS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ODT_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_RD_TO_WR_TURNAROUND_OCT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_READ_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_ROW_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_SIM_VALID_WINDOW</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_WRITE_DQS_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_IF_WR_TO_RD_TURNAROUND_OCT</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_INIT_EN</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_INIT_FILE</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_LEVELING</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_LRDIMM_ENABLED</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_MIRROR_ADDRESSING_DEC</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_DIMMS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DEVICE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_NUMBER_OF_RANKS_PER_DIMM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_PD</name>
+   <value>DLL off</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RANK_MULTIPLICATION_FACTOR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_REGDIMM_ENABLED</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_ROW_ADDR_WIDTH</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RTT_NOM</name>
+   <value>ODT Disabled</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_RTT_WR</name>
+   <value>Dynamic ODT off</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_SRT</name>
+   <value>Normal</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TCL</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TDQSCK</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TFAW</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TFAW_NS</name>
+   <value>30.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TINIT_CK</name>
+   <value>150000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TINIT_US</name>
+   <value>500</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TMRD_CK</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRAS</name>
+   <value>11</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRAS_NS</name>
+   <value>35.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRC</name>
+   <value>15</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRCD</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRCD_NS</name>
+   <value>13.75</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TREFI</name>
+   <value>2341</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TREFI_US</name>
+   <value>7.8</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRFC</name>
+   <value>34</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRFC_NS</name>
+   <value>110.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRP</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRP_NS</name>
+   <value>13.75</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRRD</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRRD_NS</name>
+   <value>6.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRTP</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TRTP_NS</name>
+   <value>7.5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWR</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWR_NS</name>
+   <value>15.0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TWTR</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_TYPE</name>
+   <value>DDR3</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_USER_LEVELING_MODE</name>
+   <value>Leveling</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_VENDOR</name>
+   <value>JEDEC</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_VERBOSE</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_WTCL</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MEM_WTCL_INT</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_BL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_BT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_CAS_LATENCY</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_DLL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_PD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR0_WR</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_AL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_DLL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_DQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_ODS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_QOFF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_RDQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_RTT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_TDQS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR1_WL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_ASR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_CWL</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_RTT_WR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_SRF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR2_SRT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR_AA</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MR3_MPR_RF</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.MRS_MIRROR_PING_PONG_ATSO</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.NEXTGEN</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY</name>
+   <value>MAX10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM</name>
+   <value></value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PINGPONGPHY_EN</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.PRE_V_SERIES_FAMILY</name>
+   <value>true</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RATE</name>
+   <value>Half</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM_CONFIG</name>
+   <value>0000000000000000</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.RDIMM_INT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.REFRESH_BURST_VALIDATION</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SCC_DATA_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SPEED_GRADE</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.SYS_INFO_DEVICE_FAMILY</name>
+   <value>MAX 10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDH</name>
+   <value>45</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCK</name>
+   <value>225</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDL</name>
+   <value>1200</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDM</name>
+   <value>900</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSCKDS</name>
+   <value>450</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSQ</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDQSS</name>
+   <value>0.27</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDS</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDSH</name>
+   <value>0.18</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TDSS</name>
+   <value>0.18</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TIH</name>
+   <value>120</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TIS</name>
+   <value>170</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TQH</name>
+   <value>0.38</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TIMING_TQSH</name>
+   <value>0.4</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.TRK_PARALLEL_SCC_LOAD</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_DQS_TRACKING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_HPS_DQS_TRACKING</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_MEM_CLK_FREQ</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY</name>
+   <value>false</value>
+  </assignment>
+  <assignment>
+   <name>testbench.partner.mem_model.parameter.USE_SHADOW_REGS</name>
+   <value>false</value>
+  </assignment>
+  <parameter name="AC_ROM_MR0">
+   <type>java.lang.String</type>
+   <value>0001000010001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_MIRR">
+   <type>java.lang.String</type>
+   <value>0001000001001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_CALIB">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_DLL_RESET">
+   <type>java.lang.String</type>
+   <value>0001100010000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR">
+   <type>java.lang.String</type>
+   <value>0001010001000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_CALIB">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR1_OCD_ENABLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR2">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR2_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR3">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_MR3_MIRR">
+   <type>java.lang.String</type>
+   <value>0000000000000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_BL">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_BT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_CAS_LATENCY">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_DLL">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_WR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR0_PD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_DLL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_ODS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_RTT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_AL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_WL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_TDQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_QOFF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_DQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR1_RDQS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_CWL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_ASR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_SRT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_SRF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR2_RTT_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR_RF">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MR3_MPR_AA">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_READ_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_WRITE_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCC_DATA_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ADDR_WIDTH_MIN">
+   <type>int</type>
+   <value>13</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ROW_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_COL_ADDR_WIDTH">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DM_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_PER_RANK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_NUMBER_OF_RANKS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_PER_DIMM">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CONTROL_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BURST_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_LEVELING">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CHIP_BITS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CK_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_CLK_PAIR_COUNT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_MAX_NS">
+   <type>double</type>
+   <value>1.25</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_MAX_PS">
+   <type>double</type>
+   <value>1250.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRC">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRAS">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRCD">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRP">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TREFI">
+   <type>int</type>
+   <value>2341</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRFC">
+   <type>int</type>
+   <value>34</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TCCD">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWR">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TFAW">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRRD">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRTP">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY">
+   <type>int</type>
+   <value>100</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY">
+   <type>int</type>
+   <value>100000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_ODT_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_WTCL_INT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLY_BY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_LRDIMM_RM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_RD_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_WR_TO_WR_EXTRA_CLK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TYPE">
+   <type>java.lang.String</type>
+   <value>DDR3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_MIRROR_ADDRESSING_DEC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ATCL_INT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_REGDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_LRDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VENDOR">
+   <type>java.lang.String</type>
+   <value>JEDEC</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_FORMAT">
+   <type>java.lang.String</type>
+   <value>DISCRETE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_PARITY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDIMM_CONFIG">
+   <type>java.lang.String</type>
+   <value>0000000000000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LRDIMM_EXTENDED_CONFIG">
+   <type>java.lang.String</type>
+   <value>0x000000000000000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DISCRETE_FLY_BY">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_DEPTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_MIRROR_ADDRESSING">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ_MAX">
+   <type>double</type>
+   <value>800.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ROW_ADDR_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_COL_ADDR_WIDTH">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DQ_PER_DQS">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DM_PINS_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_DQSN_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_DIMMS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NEXTGEN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_BOARD_BASE_DELAY">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_IF_SIM_VALID_WINDOW">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_GUARANTEED_WRITE_INIT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VERBOSE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PINGPONGPHY_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUPLICATE_AC">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REFRESH_BURST_VALIDATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AP_MODE_EN">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AP_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BL">
+   <type>java.lang.String</type>
+   <value>OTF</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_BT">
+   <type>java.lang.String</type>
+   <value>Sequential</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ASR">
+   <type>java.lang.String</type>
+   <value>Manual</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_SRT">
+   <type>java.lang.String</type>
+   <value>Normal</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_PD">
+   <type>java.lang.String</type>
+   <value>DLL off</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DRV_STR">
+   <type>java.lang.String</type>
+   <value>RZQ/6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DLL_EN">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RTT_NOM">
+   <type>java.lang.String</type>
+   <value>ODT Disabled</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_RTT_WR">
+   <type>java.lang.String</type>
+   <value>Dynamic ODT off</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_WTCL">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ATCL">
+   <type>java.lang.String</type>
+   <value>Disabled</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TCL">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_AUTO_LEVELING_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_USER_LEVELING_MODE">
+   <type>java.lang.String</type>
+   <value>Leveling</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_INIT_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_INIT_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DAT_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TIS">
+   <type>int</type>
+   <value>170</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TIH">
+   <type>int</type>
+   <value>120</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDS">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDH">
+   <type>int</type>
+   <value>45</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSQ">
+   <type>int</type>
+   <value>100</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TQH">
+   <type>double</type>
+   <value>0.38</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCK">
+   <type>int</type>
+   <value>225</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDS">
+   <type>int</type>
+   <value>450</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDM">
+   <type>int</type>
+   <value>900</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSCKDL">
+   <type>int</type>
+   <value>1200</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDQSS">
+   <type>double</type>
+   <value>0.27</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TQSH">
+   <type>double</type>
+   <value>0.4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDSH">
+   <type>double</type>
+   <value>0.18</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_TDSS">
+   <type>double</type>
+   <value>0.18</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TINIT_US">
+   <type>int</type>
+   <value>500</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TINIT_CK">
+   <type>int</type>
+   <value>150000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TDQSCK">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TMRD_CK">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRAS_NS">
+   <type>double</type>
+   <value>35.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRCD_NS">
+   <type>double</type>
+   <value>13.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRP_NS">
+   <type>double</type>
+   <value>13.75</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TREFI_US">
+   <type>double</type>
+   <value>7.8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRFC_NS">
+   <type>double</type>
+   <value>110.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TCCD_NS">
+   <type>double</type>
+   <value>2.5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWR_NS">
+   <type>double</type>
+   <value>15.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TWTR">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TFAW_NS">
+   <type>double</type>
+   <value>30.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRRD_NS">
+   <type>double</type>
+   <value>6.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_TRTP_NS">
+   <type>double</type>
+   <value>7.5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RATE">
+   <type>java.lang.String</type>
+   <value>Half</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MEM_CLK_FREQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DQS_TRACKING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_DQS_TRACKING">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_HPS_DQS_TRACKING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRK_PARALLEL_SCC_LOAD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_SHADOW_REGS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SHADOW_REGS">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQ_DDR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_CMD_DDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RATE_RATIO">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_RATE_RATIO">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RATE_RATIO">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_ADDR_WIDTH">
+   <type>int</type>
+   <value>28</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_BANKADDR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CONTROL_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CS_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CLK_EN_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DM_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DQ_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_ODT_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WRITE_DQS_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RLAT_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WLAT_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_RRANK_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_WRANK_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_CLK_PAIR_COUNT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYS_INFO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRE_V_SERIES_FAMILY">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPEED_GRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ES_DEVICE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DISABLE_CHILD_MESSAGING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HARD_PHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HARD_EMIF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS_VERIFICATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HHP_HPS_SIMULATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HPS_PROTOCOL">
+   <type>java.lang.String</type>
+   <value>DEFAULT</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CUT_NEW_FAMILY_TIMING">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPORT_CSR_PORT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_ADDR_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CSR_BE_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH">
+   <type>int</type>
+   <value>25</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_BE_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_SYMBOL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_SIZE_WIDTH">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DWIDTH_RATIO">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ODT_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_OUTPUT_REGD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_MULTIPLES_40_72">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_REGDIMM_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOW_LATENCY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTROLLER_TYPE">
+   <type>java.lang.String</type>
+   <value>nextgen_v110</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_TBP_NUM">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_USR_REFRESH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_SELF_REFRESH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_TYPE">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_INTERFACE_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_BURST_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ADDR_ORDER">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PDN_EXIT_CYCLES">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES">
+   <type>int</type>
+   <value>20</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES">
+   <type>int</type>
+   <value>512</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_WRITE_ODT_CHIP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_READ_ODT_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCAL_CS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_CLR_INTR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ENABLE_NO_DM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_ADD_LAT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ERRCMD_FIFO_REG">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_ECC_DECODER_REG">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_STARVE_LIMIT">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_1">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_2">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_3">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_4">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_ADDR_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_NUM_SYMBOLS_PORT_5">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALLOCATED_RFIFO_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>0,None,None,None,None,None</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ALLOCATED_WFIFO_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>0,None,None,None,None,None</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_AUTO_PCH_ENABLE_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CAL_REQ">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_BURST_LENGTH">
+   <type>java.lang.String</type>
+   <value>BL_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_INTERFACE_WIDTH">
+   <type>java.lang.String</type>
+   <value>DWIDTH_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_STARVE_LIMIT">
+   <type>java.lang.String</type>
+   <value>STARVE_LIMIT_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CFG_TYPE">
+   <type>java.lang.String</type>
+   <value>DDR3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLOCK_OFF_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CLR_INTR">
+   <type>java.lang.String</type>
+   <value>NO_CLR_INTR</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_4">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CMD_PORT_IN_USE_5">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT0_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT1_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT2_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT3_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT4_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CPORT5_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ADDR_ORDER">
+   <type>java.lang.String</type>
+   <value>CHIP_BANK_ROW_COL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ECC_ENABLED">
+   <type>java.lang.String</type>
+   <value>CTL_ECC_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_ECC_RMW_ENABLED">
+   <type>java.lang.String</type>
+   <value>CTL_ECC_RMW_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_REGDIMM_ENABLED">
+   <type>java.lang.String</type>
+   <value>REGDIMM_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTL_USR_REFRESH">
+   <type>java.lang.String</type>
+   <value>CTL_USR_REFRESH_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_CTRL_WIDTH">
+   <type>java.lang.String</type>
+   <value>DATA_WIDTH_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DELAY_BONDING">
+   <type>java.lang.String</type>
+   <value>BONDING_LATENCY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DFX_BYPASS_ENABLE">
+   <type>java.lang.String</type>
+   <value>DFX_BYPASS_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_DISABLE_MERGING">
+   <type>java.lang.String</type>
+   <value>MERGING_ENABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ECC_DQ_WIDTH">
+   <type>java.lang.String</type>
+   <value>ECC_DQ_WIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_ATPG">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_DQS_TRACKING">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_NO_DM">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GANGED_ARF">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GEN_DBE">
+   <type>java.lang.String</type>
+   <value>GEN_DBE_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_GEN_SBE">
+   <type>java.lang.String</type>
+   <value>GEN_SBE_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_INC_SYNC">
+   <type>java.lang.String</type>
+   <value>FIFO_SET_2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_LOCAL_IF_CS_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_CORR_DROPPED_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_DBE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MASK_SBE_INTR">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_AL">
+   <type>java.lang.String</type>
+   <value>AL_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_BURSTLENGTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_BURSTLENGTH_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_CS_PER_RANK">
+   <type>java.lang.String</type>
+   <value>MEM_IF_CS_PER_RANK_1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_CS_WIDTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_CS_WIDTH_1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP">
+   <type>java.lang.String</type>
+   <value>MEM_IF_DQ_PER_CHIP_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DQS_WIDTH">
+   <type>java.lang.String</type>
+   <value>DQS_WIDTH_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_DWIDTH">
+   <type>java.lang.String</type>
+   <value>MEM_IF_DWIDTH_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_MEMTYPE">
+   <type>java.lang.String</type>
+   <value>DDR3_SDRAM</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH">
+   <type>java.lang.String</type>
+   <value>ADDR_WIDTH_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_SPEEDBIN">
+   <type>java.lang.String</type>
+   <value>DDR3_1066_6_6_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCCD">
+   <type>java.lang.String</type>
+   <value>TCCD_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCL">
+   <type>java.lang.String</type>
+   <value>TCL_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TCWL">
+   <type>java.lang.String</type>
+   <value>TCWL_5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TFAW">
+   <type>java.lang.String</type>
+   <value>TFAW_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TMRD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRAS">
+   <type>java.lang.String</type>
+   <value>TRAS_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRC">
+   <type>java.lang.String</type>
+   <value>TRC_22</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRCD">
+   <type>java.lang.String</type>
+   <value>TRCD_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRP">
+   <type>java.lang.String</type>
+   <value>TRP_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRRD">
+   <type>java.lang.String</type>
+   <value>TRRD_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TRTP">
+   <type>java.lang.String</type>
+   <value>TRTP_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TWR">
+   <type>java.lang.String</type>
+   <value>TWR_6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MEM_IF_TWTR">
+   <type>java.lang.String</type>
+   <value>TWTR_4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_MMR_CFG_MEM_BL">
+   <type>java.lang.String</type>
+   <value>MP_BL_8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_OUTPUT_REGD">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PDN_EXIT_CYCLES">
+   <type>java.lang.String</type>
+   <value>SLOW_EXIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT0_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT1_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT2_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT3_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT4_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PORT5_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_0_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_1_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_2_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_3_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_4_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_5_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_6_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_PRIORITY_7_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RCFG_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_FIFO_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RD_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_READ_ODT_CHIP">
+   <type>java.lang.String</type>
+   <value>ODT_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_REORDER_DATA">
+   <type>java.lang.String</type>
+   <value>DATA_REORDERING</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_RFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_0">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_1">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_2">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SINGLE_READY_3">
+   <type>java.lang.String</type>
+   <value>CONCATENATE_RDY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_0">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_1">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_2">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_3">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_4">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_SYNC_MODE_5">
+   <type>java.lang.String</type>
+   <value>ASYNCHRONOUS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_TEST_MODE">
+   <type>java.lang.String</type>
+   <value>NORMAL_MODE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_0">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_1">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_2">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_3">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_4">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR1_5">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_0">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_1">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_2">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_3">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_4">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_THLD_JAR2_5">
+   <type>java.lang.String</type>
+   <value>THRESHOLD_16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_0">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_1">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_2">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USE_ALMOST_EMPTY_3">
+   <type>java.lang.String</type>
+   <value>EMPTY</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_ECC_EN">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL">
+   <type>java.lang.String</type>
+   <value>NOT_FULL</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_FIFO_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WR_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_WRITE_ODT_CHIP">
+   <type>java.lang.String</type>
+   <value>ODT_DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_0">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_1">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_2">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_3">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_4">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_CYC_TO_RLD_JARS_5">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_IF_TREFI">
+   <type>int</type>
+   <value>3120</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_IF_TRFC">
+   <type>int</type>
+   <value>34</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ONE_MASK">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE">
+   <type>java.math.BigInteger</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES">
+   <type>int</type>
+   <value>10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BURST_INTERRUPT">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENUM_ENABLE_BURST_TERMINATE">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_0">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_0">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT0_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_0">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_0">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_0">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_0">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_1">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_1">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT1_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_1">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_1">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_1">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_1">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_2">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_2">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT2_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_2">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_2">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_2">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_2">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_3">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_3">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT3_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_3">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_3">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_3">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_3">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_4">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_4">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT4_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_4">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_4">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_4">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_4">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_DATA_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_CPORT_TYPE_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_WFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_LSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_MSB_RFIFO_PORT_5">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5">
+   <type>java.lang.String</type>
+   <value>FALSE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_TYPE">
+   <type>java.lang.String</type>
+   <value>DISABLE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP">
+   <type>java.lang.String</type>
+   <value>FIFO_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_ENABLE_BONDING_5">
+   <type>java.lang.String</type>
+   <value>DISABLED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PORT5_WIDTH">
+   <type>java.lang.String</type>
+   <value>PORT_64_BIT</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_0_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_1_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_2_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_3_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_4_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_5_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_6_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_PRIORITY_7_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RD_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_STATIC_WEIGHT_5">
+   <type>java.lang.String</type>
+   <value>WEIGHT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_USER_PRIORITY_5">
+   <type>java.lang.String</type>
+   <value>PRIORITY_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_DWIDTH_5">
+   <type>java.lang.String</type>
+   <value>DWIDTH_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WR_PORT_INFO_5">
+   <type>java.lang.String</type>
+   <value>USE_NO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TG_TEMP_PORT_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP">
+   <type>java.lang.String</type>
+   <value>CMD_PORT_0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_0">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_1">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_2">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_3">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_4">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_5">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_6">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CV_INTG_SUM_WT_PRIORITY_7">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTINUE_AFTER_CAL_FAIL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX10_CFG">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="POWER_OF_TWO_BUS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SOPC_COMPAT_RESET">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_MAX_SIZE">
+   <type>java.lang.String</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BYTE_ENABLE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DEEP_POWERDN_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_SELF_REFRESH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_POWERDN_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_PD_CYCLES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_USR_REFRESH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_AUTOPCH_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ZQCAL_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_ORDER">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_LOOK_AHEAD_DEPTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONTROLLER_LATENCY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_REORDER_DATA">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STARVE_LIMIT">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_CONNECTION">
+   <type>java.lang.String</type>
+   <value>INTERNAL_JTAG</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_HRB_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MULTICAST_EN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_DYNAMIC_BANK_NUM">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEBUG_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_BURST_MERGE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_ENABLE_BURST_TERMINATE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCAL_ID_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RDBUFFER_ADDR_WIDTH">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WRBUFFER_ADDR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_PENDING_WR_CMD">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_PENDING_RD_CMD">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MM_ADAPTOR">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_AXI_ADAPTOR">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HCX_COMPAT_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CMD_QUEUE_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CTL_CSR_READ_ONLY">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CFG_DATA_REORDERING_TYPE">
+   <type>java.lang.String</type>
+   <value>INTER_BANK</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_OF_PORTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_BONDING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_USER_ECC">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVL_DATA_WIDTH_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>32,32,32,32,32,32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIORITY_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>1,1,1,1,1,1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WEIGHT_PORT">
+   <type>[Ljava.lang.Integer;</type>
+   <value>0,0,0,0,0,0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CPORT_TYPE_PORT">
+   <type>[Ljava.lang.String;</type>
+   <value>Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CORE_PERIPHERY_DUAL_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DR_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_USE_DR_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_2X_FF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUAL_WRITE_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GENERIC_PLL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_HARD_READ_FIFO">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_FIFO_HALF_RATE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_VERSION_NUMBER">
+   <type>int</type>
+   <value>191</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_OCI">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EMIT_JTAG_MASTER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_JTAG_UART">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EMIT_BFM_MASTER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_CSR_SOFT_RESET_REQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_VALID_FIFO_SIZE">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTRA_VFIFO_SHIFT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_RATE">
+   <type>java.lang.String</type>
+   <value>HALF</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_IF_DQ_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_MEM_IF_READ_DQS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TB_PLL_DLL_MASTER">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FAST_SIM_CALIBRATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>100.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_NS">
+   <type>double</type>
+   <value>10.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_PS">
+   <type>double</type>
+   <value>10000.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ">
+   <type>double</type>
+   <value>150.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>150.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>6668 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value>300.0 MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>270.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MIN_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MAX_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MIN_CACHE">
+   <type>double</type>
+   <value>10.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_MAX_CACHE">
+   <type>double</type>
+   <value>500.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_DR_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_MEM_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>150.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>6668 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_WRITE_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>0 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>3334 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>2500</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value>2500 ps</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_NIOS_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CONFIG_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_HR_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPEED_GRADE_CACHE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ES_DEVICE_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>300.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REF_CLK_FREQ_CACHE">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RATE_CACHE">
+   <type>java.lang.String</type>
+   <value>Half</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HCX_COMPAT_MODE_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMMAND_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQUENCER_TYPE_CACHE">
+   <type>java.lang.String</type>
+   <value>NIOS</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_MEM_CLK_FREQ_CACHE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CLK_CACHE_VALID">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_CLK_PARAM_VALID">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EXTRA_REPORTING">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_EXTRA_REPORT_PATH">
+   <type>int</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ISS_PROBES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_REG_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_SEQUENCER_BFM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_PLL_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPORT_AFI_HALF_CLK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FAKE_PHY_INTERNAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FAKE_PHY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_READ_LATENCY">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_USER_RDIMM_VALUE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRACKING_ERROR_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRACKING_WATCH_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MARGIN_VARIATION_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_USER_ADD_0">
+   <type>java.lang.String</type>
+   <value>0_0000_0000_0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_ROM_USER_ADD_1">
+   <type>java.lang.String</type>
+   <value>0_0000_0000_1000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TREFI">
+   <type>int</type>
+   <value>35100</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REFRESH_INTERVAL">
+   <type>int</type>
+   <value>15000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DES_CAL_TEST">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRFC">
+   <type>int</type>
+   <value>350</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_NON_DES_CAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTRA_SETTINGS">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_DEVICE">
+   <type>java.lang.String</type>
+   <value>MISSING_MODEL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_SUBGROUP_PER_READ_DQS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QVLD_EXTRA_FLOP_STAGES">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QVLD_WR_ADDRESS_OFFSET">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_WRITE_PATH_FLOP_STAGES">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_AC_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQ_BURST_COUNT_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCALIB_COUNT_WIDTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_PHASE_COUNTER_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_PHASE_SHIFT">
+   <type>int</type>
+   <value>9000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAYED_CLOCK_PHASE_SETTING">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_IN_RESERVE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_OUT_RESERVE">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQ_OUT_RESERVE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DM_OUT_RESERVE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_EN_DELAY_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQS_EN_PHASE_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_DQDQS_OUT_PHASE_MAX">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_NS">
+   <type>double</type>
+   <value>3.333</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CLK_PS">
+   <type>double</type>
+   <value>3333.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_LFIFO_OFFSET">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIB_VFIFO_OFFSET">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_OPA_TAP">
+   <type>int</type>
+   <value>416</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_DCHAIN_TAP">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP">
+   <type>int</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_EN_DELAY_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_IN_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_IN_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_OUT1_DELAY_MAX">
+   <type>int</type>
+   <value>15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_OUT2_DELAY_MAX">
+   <type>int</type>
+   <value>7</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_STANDARD">
+   <type>java.lang.String</type>
+   <value>SSTL-15</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VFIFO_AS_SHIFT_REG">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQUENCER_TYPE">
+   <type>java.lang.String</type>
+   <value>NIOS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_HEX_FILE_LOCATION">
+   <type>java.lang.String</type>
+   <value>../</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NEGATIVE_WRITE_CK_PHASE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_T_WL">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_T_RL">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CLKBUF">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_LDC_FOR_ADDR_CMD">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="REGISTER_C2P">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX10_RTL_SEQ">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_ONLY">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SEQ_MODE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADVANCED_CK_PHASES">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMMAND_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_CK_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MEM_VOLTAGE">
+   <type>java.lang.String</type>
+   <value>1.5V DDR3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_LOCATION">
+   <type>java.lang.String</type>
+   <value>Top_Bottom</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_MEM_INIT">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE">
+   <type>java.lang.String</type>
+   <value>INVERTED_DQS_BUS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQ_INPUT_REG_USE_CLKN">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DQS_DQSN_MODE">
+   <type>java.lang.String</type>
+   <value>DIFFERENTIAL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AFI_DEBUG_INFO_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CALIBRATION_MODE">
+   <type>java.lang.String</type>
+   <value>Skip</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_ROM_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NIOS_ROM_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>13</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_FIFO_SIZE">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CSR_ENABLED">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PHY_CSR_CONNECTION">
+   <type>java.lang.String</type>
+   <value>INTERNAL_JTAG</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USER_DEBUG_LEVEL">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DERATE_METHOD">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>2.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED">
+   <type>double</type>
+   <value>1.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIS">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIH">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDS">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDH">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIS_APPLIED">
+   <type>double</type>
+   <value>0.32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TIH_APPLIED">
+   <type>double</type>
+   <value>0.22</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDS_APPLIED">
+   <type>double</type>
+   <value>0.16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_TDH_APPLIED">
+   <type>double</type>
+   <value>0.145</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_ISI_METHOD">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKAGE_DESKEW">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AC_PACKAGE_DESKEW">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY">
+   <type>double</type>
+   <value>0.2443</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY">
+   <type>double</type>
+   <value>0.21929</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN">
+   <type>double</type>
+   <value>0.02286</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED">
+   <type>double</type>
+   <value>0.02286</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX">
+   <type>double</type>
+   <value>0.04429</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED">
+   <type>double</type>
+   <value>0.04429</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS">
+   <type>double</type>
+   <value>0.05</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS">
+   <type>double</type>
+   <value>0.01806</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS">
+   <type>double</type>
+   <value>0.04246</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW">
+   <type>double</type>
+   <value>-0.01152</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_SKEW">
+   <type>double</type>
+   <value>0.07801</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW">
+   <type>double</type>
+   <value>-0.04709</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CORE_DEBUG_CONNECTION">
+   <type>java.lang.String</type>
+   <value>EXPORT</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ED_EXPORT_SEQ_DEBUG">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADD_EFFICIENCY_MONITOR">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABS_RAM_INTERNAL">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_ABSTRACT_RAM">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME">
+   <type>java.lang.String</type>
+   <value>meminit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_DELAY_CTRL_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_OFFSET_CTRL_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_BUFFER_MODE">
+   <type>java.lang.String</type>
+   <value>HIGH</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DELAY_CHAIN_LENGTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DLL_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_DLL_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OCT_TERM_CONTROL_WIDTH">
+   <type>int</type>
+   <value>14</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OCT_SHARING_MODE">
+   <type>java.lang.String</type>
+   <value>None</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_OCT_SHARING_INTERFACES">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="pll_ref_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>pll_ref_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="global_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>global_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="soft_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>soft_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="afi_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>150000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>ddr3_ram_afi_clk</slaveName>
+    <name>mm_interconnect_1.ddr3_ram_afi_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_controller_006</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_controller_006.clk</name>
+   </clockDomainMember>
+  </interface>
+  <interface name="afi_half_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>300000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_half_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="afi_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>soft_reset,global_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="afi_reset_export" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>soft_reset,global_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>afi_reset_export_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="memory" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>memory</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>mem_a</name>
+    <direction>Output</direction>
+    <width>14</width>
+    <role>mem_a</role>
+   </port>
+   <port>
+    <name>mem_ba</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>mem_ba</role>
+   </port>
+   <port>
+    <name>mem_ck</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_ck</role>
+   </port>
+   <port>
+    <name>mem_ck_n</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_ck_n</role>
+   </port>
+   <port>
+    <name>mem_cke</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cke</role>
+   </port>
+   <port>
+    <name>mem_cs_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cs_n</role>
+   </port>
+   <port>
+    <name>mem_dm</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_dm</role>
+   </port>
+   <port>
+    <name>mem_ras_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_ras_n</role>
+   </port>
+   <port>
+    <name>mem_cas_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_cas_n</role>
+   </port>
+   <port>
+    <name>mem_we_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_we_n</role>
+   </port>
+   <port>
+    <name>mem_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_reset_n</role>
+   </port>
+   <port>
+    <name>mem_dq</name>
+    <direction>Bidir</direction>
+    <width>8</width>
+    <role>mem_dq</role>
+   </port>
+   <port>
+    <name>mem_dqs</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_dqs</role>
+   </port>
+   <port>
+    <name>mem_dqs_n</name>
+    <direction>Bidir</direction>
+    <width>1</width>
+    <role>mem_dqs_n</role>
+   </port>
+   <port>
+    <name>mem_odt</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mem_odt</role>
+   </port>
+  </interface>
+  <interface name="avl" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>134217728</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>afi_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>soft_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest_n</role>
+   </port>
+   <port>
+    <name>avl_burstbegin</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>beginbursttransfer</role>
+   </port>
+   <port>
+    <name>avl_addr</name>
+    <direction>Input</direction>
+    <width>25</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_rdata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avl_rdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_wdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_be</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>avl_read_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_write_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_size</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>burstcount</role>
+   </port>
+  </interface>
+  <interface name="status" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>local_init_done</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_init_done</role>
+   </port>
+   <port>
+    <name>local_cal_success</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_cal_success</role>
+   </port>
+   <port>
+    <name>local_cal_fail</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>local_cal_fail</role>
+   </port>
+  </interface>
+  <interface name="pll_sharing" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>pll_mem_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_mem_clk</role>
+   </port>
+   <port>
+    <name>pll_write_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_write_clk</role>
+   </port>
+   <port>
+    <name>pll_locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_locked</role>
+   </port>
+   <port>
+    <name>pll_capture0_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_capture0_clk</role>
+   </port>
+   <port>
+    <name>pll_capture1_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>pll_capture1_clk</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ddr3_ram_resetn"
+   kind="altera_reset_bridge"
+   version="19.1"
+   path="ddr3_ram_resetn">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="ACTIVE_LOW_RESET">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNCHRONOUS_EDGES">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_RESET_OUTPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_CLK_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>-1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="out_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_reset_n</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="debug_uart"
+   kind="altera_avalon_uart"
+   version="19.1"
+   path="debug_uart">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BAUD</name>
+   <value>115200</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_BITS</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_BAUD</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PARITY</name>
+   <value>'N'</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIM_CHAR_STREAM</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIM_TRUE_BAUD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STOP_BITS</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SYNC_REG_DEPTH</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_CTS_RTS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_EOP_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,uart-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>serial</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>uart</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.current-speed</name>
+   <value>115200</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="baud">
+   <type>int</type>
+   <value>115200</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataBits">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedBaud">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="parity">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simCharStream">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simInteractiveInputEnable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simInteractiveOutputEnable">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simTrueBaud">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stopBits">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="syncRegDepth">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useCtsRts">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useEopRegister">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useRelativePathForSimFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="baudError">
+   <type>double</type>
+   <value>0.01</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="parityFisrtChar">
+   <type>java.lang.String</type>
+   <value>N</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>begintransfer</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>begintransfer</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>read_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read_n</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rxd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+   <port>
+    <name>txd</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>debug_uart.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="descriptor_memory">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>q_sys_descriptor_memory</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>8192</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>q_sys_descriptor_memory</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>8192</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_descriptor_memory</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>11</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>q_sys_descriptor_memory.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8192</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8192</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>11</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+ </module>
+ <module name="enet_pll" kind="altpll" version="19.1" path="enet_pll">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_elaboration</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">
+   <type>java.lang.String</type>
+   <value>altpll_avalon_post_edit</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INTENDED_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_CLOCK">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WIDTH_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PRIMARY_CLOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>20000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INCLK1_INPUT_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OPERATION_MODE">
+   <type>java.lang.String</type>
+   <value>NO_COMPENSATION</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PLL_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_CONF_DONE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="COMPENSATE_CLOCK">
+   <type>java.lang.String</type>
+   <value>CLK0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_SIGNAL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GATE_LOCK_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_HIGH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="LOCK_LOW">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INVALID_LOCK_MULTIPLIER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_LOSSCLK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SKIP_VCO">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_COUNTER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SWITCH_OVER_TYPE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FEEDBACK_SOURCE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BANDWIDTH_TYPE">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SPREAD_FREQUENCY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DOWN_SPREAD">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SELF_RESET_ON_LOSS_LOCK">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>20</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>-3000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value>-10000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK4_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK5_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK6_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK7_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK8_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLK9_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK0_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK1_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK2_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXTCLK3_DUTY_CYCLE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena4">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clkena5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena2">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclkena3">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk2">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_extclk3">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD0">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKBAD1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk1">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk2">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk3">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk4">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk5">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk6">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk7">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk8">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_clk9">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDATAOUT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCLKOUT0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ACTIVECLOCK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKLOSS">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK1">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_INCLK0">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBIN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PLLENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CLKSWITCH">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ARESET">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PFDENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLK">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANACLR">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANREAD">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANWRITE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE0">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_ENABLE1">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_LOCKED">
+   <type>java.lang.String</type>
+   <value>PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_CONFIGUPDATE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_FBOUT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEDONE">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASESTEP">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASEUPDOWN">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_SCANCLKENA">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_PHASECOUNTERSELECT">
+   <type>java.lang.String</type>
+   <value>PORT_UNUSED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOOVERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PORT_VCOUNDERRANGE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DPA_DIVIDER">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_MULTIPLY_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_DIVIDE_BY">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT0_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCLKOUT1_PHASE_SHIFT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_FREQUENCY_CONTROL">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="VCO_PHASE_SHIFT_STEP">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USING_FBMIMICBIDIR_PORT">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SCAN_CHAIN_MIF_FILE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK">
+   <type>java.lang.String</type>
+   <value>NO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_CONSTANTS">
+   <type>java.lang.String</type>
+   <value>CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_PRIVATES">
+   <type>java.lang.String</type>
+   <value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_USED_PORTS">
+   <type>java.lang.String</type>
+   <value>UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_NUMERIC">
+   <type>java.lang.String</type>
+   <value>IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_MF_PORTS">
+   <type>java.lang.String</type>
+   <value>MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IF_PORTS">
+   <type>java.lang.String</type>
+   <value>IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT">
+   <type>java.lang.String</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE">
+   <type>java.lang.Long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>inclk_interface</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="inclk_interface" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="inclk_interface_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="pll_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>inclk_interface</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>inclk_interface_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface name="c0" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>125000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c0</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c1" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c1</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c2" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>2500000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c2</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c3" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>125000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c3</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="c4" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>25000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>c4</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="locked_conduit" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>locked</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module name="eth_tse" kind="altera_eth_tse" version="19.1" path="eth_tse">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ENABLE_MACLITE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIFO_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IS_MULTICHANNEL_MAC</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MACLITE_GIGE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MDIO_SHARED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_CHANNEL</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS_ID</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PCS_SGMII</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RECEIVE_FIFO_DEPTH</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.REGISTER_SHARED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RGMII</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.USE_MDIO</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,tse-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>ethernet</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>tse</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.ALTR,rx-fifo-depth</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.ALTR,tx-fifo-depth</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="deviceFamilyName">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="enable_padding">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_lgth_check">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="gbit_only">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mbit_only">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reduced_control">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="core_version">
+   <type>int</type>
+   <value>4865</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dev_version">
+   <type>int</type>
+   <value>4865</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="eg_fifo">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ing_fifo">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="reduced_interface_ena">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="synchronizer_depth">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="isUseMAC">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="isUsePCS">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_clk_sharing">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="core_variation">
+   <type>java.lang.String</type>
+   <value>MAC_ONLY</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ifGMII">
+   <type>java.lang.String</type>
+   <value>RGMII</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="use_mac_clken">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_use_internal_fifo">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ecc">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="max_channels">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="use_misc_ports">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="transceiver_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_hd_logic">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_gmii_loopback">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_sup_addr">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="stat_cnt_ena">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ext_stat_cnt_ena">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ena_hash">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_shift16">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_mac_flow_ctrl">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_mac_vlan">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_magic_detect">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useMDIO">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mdio_clk_div">
+   <type>int</type>
+   <value>40</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ena">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="eg_addr">
+   <type>int</type>
+   <value>11</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ing_addr">
+   <type>int</type>
+   <value>11</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phy_identifier">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_sgmii">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="export_pwrdn">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_alt_reconfig">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="starting_channel_number">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pll_type">
+   <type>java.lang.String</type>
+   <value>CMU</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pll_base_data_rate">
+   <type>java.lang.String</type>
+   <value>1250 Mbps</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_en_synce_support">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="phyip_pma_bonding_mode">
+   <type>java.lang.String</type>
+   <value>x1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="nf_phyip_rcfg_enable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_RCFG_JTAG_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_USER_IDENTIFIER">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="nf_lvds_iopll_num_channels">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_timestamping">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enable_ptp_1step">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="tstamp_fp_width">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="control_port_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_connection" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>control_port_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="control_port" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1024</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>control_port_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reg_addr</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>reg_data_out</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>reg_rd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>reg_data_in</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>reg_wr</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>reg_busy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+  <interface name="pcs_mac_tx_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>tx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="pcs_mac_rx_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="mac_status_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>set_10</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>set_10</role>
+   </port>
+   <port>
+    <name>set_1000</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>set_1000</role>
+   </port>
+   <port>
+    <name>eth_mode</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>eth_mode</role>
+   </port>
+   <port>
+    <name>ena_10</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ena_10</role>
+   </port>
+  </interface>
+  <interface name="mac_rgmii_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rgmii_in</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>rgmii_in</role>
+   </port>
+   <port>
+    <name>rgmii_out</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>rgmii_out</role>
+   </port>
+   <port>
+    <name>rx_control</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>rx_control</role>
+   </port>
+   <port>
+    <name>tx_control</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>tx_control</role>
+   </port>
+  </interface>
+  <interface name="receive_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_rx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="transmit_clock_connection" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_tx_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="receive" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>receive_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>ff_rx_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>ff_rx_eop</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>rx_err</name>
+    <direction>Output</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>ff_rx_mod</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>ff_rx_rdy</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>ff_rx_sop</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>ff_rx_dval</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="transmit" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>transmit_clock_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_connection</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ff_tx_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>ff_tx_eop</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>ff_tx_err</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>ff_tx_mod</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>ff_tx_rdy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>ff_tx_sop</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>ff_tx_wren</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="mac_mdio_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>mdc</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdc</role>
+   </port>
+   <port>
+    <name>mdio_in</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>mdio_in</role>
+   </port>
+   <port>
+    <name>mdio_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdio_out</role>
+   </port>
+   <port>
+    <name>mdio_oen</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>mdio_oen</role>
+   </port>
+  </interface>
+  <interface name="mac_misc_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>magic_wakeup</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>magic_wakeup</role>
+   </port>
+   <port>
+    <name>magic_sleep_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>magic_sleep_n</role>
+   </port>
+   <port>
+    <name>ff_tx_crc_fwd</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ff_tx_crc_fwd</role>
+   </port>
+   <port>
+    <name>ff_tx_septy</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_septy</role>
+   </port>
+   <port>
+    <name>tx_ff_uflow</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>tx_ff_uflow</role>
+   </port>
+   <port>
+    <name>ff_tx_a_full</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_a_full</role>
+   </port>
+   <port>
+    <name>ff_tx_a_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_tx_a_empty</role>
+   </port>
+   <port>
+    <name>rx_err_stat</name>
+    <direction>Output</direction>
+    <width>18</width>
+    <role>rx_err_stat</role>
+   </port>
+   <port>
+    <name>rx_frm_type</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>rx_frm_type</role>
+   </port>
+   <port>
+    <name>ff_rx_dsav</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_dsav</role>
+   </port>
+   <port>
+    <name>ff_rx_a_full</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_a_full</role>
+   </port>
+   <port>
+    <name>ff_rx_a_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ff_rx_a_empty</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   path="ext_flash">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.FLASH_TYPE</name>
+   <value>Micron512</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IS_EPCS</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NUMBER_OF_SECTORS</name>
+   <value>1024</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PAGE_SIZE</name>
+   <value>256</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR_SIZE</name>
+   <value>65536</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SUBSECTOR_SIZE</name>
+   <value>4096</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,quadspi-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>quadspi</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>quadspi</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.IS_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX</name>
+   <value>1</value>
+  </assignment>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="UNIQUE_ID">
+   <type>java.lang.String</type>
+   <value>q_sys_ext_flash</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="clkFreq">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clock_sink</sysinfo_arg>
+  </parameter>
+  <parameter name="CS_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_WIDTH">
+   <type>int</type>
+   <value>24</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ASI_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ASMI_ADDR_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENABLE_4BYTE_ADDR">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DDASI">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_TYPE">
+   <type>java.lang.String</type>
+   <value>Micron512</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IO_MODE">
+   <type>java.lang.String</type>
+   <value>QUAD</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHIP_SELS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFeaturesSystemInfo">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clock_sink" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>false</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="avl_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_csr_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avl_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_csr_addr</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_csr_wrdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_csr_rddata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_csr_rddata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface name="avl_mem" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>67108864</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avl_mem_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avl_mem_burstcount</name>
+    <direction>Input</direction>
+    <width>7</width>
+    <role>burstcount</role>
+   </port>
+   <port>
+    <name>avl_mem_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avl_mem_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avl_mem_addr</name>
+    <direction>Input</direction>
+    <width>24</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avl_mem_wrdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avl_mem_rddata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avl_mem_rddata_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avl_mem_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="interrupt_sender" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>ext_flash.avl_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock_sink</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="flash_dataout" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_dataout</name>
+    <direction>Bidir</direction>
+    <width>4</width>
+    <role>conduit_dataout</role>
+   </port>
+  </interface>
+  <interface name="flash_dclk_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_dclk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>conduit_dclk_out</role>
+   </port>
+  </interface>
+  <interface name="flash_ncs" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>flash_ncs</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>conduit_ncs</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="ext_flash_clock_bridge"
+   kind="altera_clock_bridge"
+   version="19.1"
+   path="ext_flash_clock_bridge">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DERIVED_CLOCK_RATE">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>in_clk</sysinfo_arg>
+  </parameter>
+  <parameter name="EXPLICIT_CLOCK_RATE">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUM_CLOCK_OUTPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>false</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>0</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="out_clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>in_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>clock_sink</slaveName>
+    <name>ext_flash.clock_sink</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>ext_flash_clock_bridge_out_clk</slaveName>
+    <name>mm_interconnect_1.ext_flash_clock_bridge_out_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>irq_synchronizer</moduleName>
+    <slaveName>receiver_clk</slaveName>
+    <name>irq_synchronizer.receiver_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_controller_005</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_controller_005.clk</name>
+   </clockDomainMember>
+  </interface>
+ </module>
+ <module
+   name="frame_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   path="frame_timer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALWAYS_RUN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.COUNTER_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_PERIOD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.LOAD_VALUE</name>
+   <value>4999</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MULT</name>
+   <value>2e-8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD</name>
+   <value>5000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD_UNITS</name>
+   <value>clocks</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SNAPSHOT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
+   <value>10000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="alwaysRun">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="counterSize">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedPeriod">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="period">
+   <type>java.lang.String</type>
+   <value>5000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnits">
+   <type>java.lang.String</type>
+   <value>CLOCKS</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="snapshot">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timeoutPulseOutput">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="systemFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="watchdogPulse">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timerPreset">
+   <type>java.lang.String</type>
+   <value>CUSTOM</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnitsString">
+   <type>java.lang.String</type>
+   <value>clocks</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="valueInSecond">
+   <type>double</type>
+   <value>0.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="loadValue">
+   <type>java.lang.String</type>
+   <value>4999</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mult">
+   <type>double</type>
+   <value>2.0E-8</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ticksPerSec">
+   <type>double</type>
+   <value>10000.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave_address_width">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isTimerDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>frame_timer.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="external_port" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>timeout_pulse</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module name="msgdma_rx" kind="altera_msgdma" version="19.1" path="msgdma_rx">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_WRAPPING_SUPPORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_FIFO_DEPTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DMA_MODE</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ENHANCED_FEATURES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_WIDTH</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BURST_COUNT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BYTE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_STRIDE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PREFETCHER_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESPONSE_PORT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSFER_TYPE</name>
+   <value>Aligned Accesses</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,msgdma-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="MODE">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPOSE_ST_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_FIFO_DEPTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DESCRIPTOR_FIFO_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESPONSE_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BYTE">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRANSFER_TYPE">
+   <type>java.lang.String</type>
+   <value>Aligned Accesses</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_WRAPPING_SUPPORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENHANCED_FEATURES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_STRIDE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PROGRAMMABLE_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_READ_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = -1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 28</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="mm_write" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>mm_write_address</name>
+    <direction>Output</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>mm_write_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>mm_write_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>mm_write_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>mm_write_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_rx_mm_write</slaveName>
+    <name>mm_interconnect_1.msgdma_rx_mm_write</name>
+    <baseAddress>0</baseAddress>
+    <span>268435456</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_read_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_read_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_rx_descriptor_read_master</slaveName>
+    <name>mm_interconnect_1.msgdma_rx_descriptor_read_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_write_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>3</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_write_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_response</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writeresponsevalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_rx_descriptor_write_master</slaveName>
+    <name>mm_interconnect_1.msgdma_rx_descriptor_write_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="clock" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_n" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+  </interface>
+  <interface name="prefetcher_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>prefetcher_csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="csr_irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>msgdma_rx.prefetcher_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_irq_irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="st_sink" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>st_sink_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>st_sink_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>st_sink_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>st_sink_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>st_sink_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>st_sink_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>st_sink_error</name>
+    <direction>Input</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module name="msgdma_tx" kind="altera_msgdma" version="19.1" path="msgdma_tx">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BURST_WRAPPING_SUPPORT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CHANNEL_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_FIFO_DEPTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DMA_MODE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ENHANCED_FEATURES</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ERROR_WIDTH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BURST_COUNT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_BYTE</name>
+   <value>2048</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MAX_STRIDE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PACKET_ENABLE_DERIVED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PREFETCHER_ENABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESPONSE_PORT</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.STRIDE_ENABLE_DERIVED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TRANSFER_TYPE</name>
+   <value>Aligned Accesses</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,msgdma-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>msgdma</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FIX_ADDRESS_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EXPOSE_ST_PORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_FIFO_DEPTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DESCRIPTOR_FIFO_DEPTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESPONSE_PORT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BYTE">
+   <type>int</type>
+   <value>2048</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="TRANSFER_TYPE">
+   <type>java.lang.String</type>
+   <value>Aligned Accesses</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BURST_WRAPPING_SUPPORT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENHANCED_FEATURES">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_STRIDE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PROGRAMMABLE_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="STRIDE_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PACKET_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_ENABLE_DERIVED">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_ENABLE_DERIVED">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_READ_BURST_ENABLE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 28</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_read</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = -1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>mm_write</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_read_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP">
+   <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+   <value><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH">
+   <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+   <value>AddressWidth = 29</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+   <sysinfo_arg>descriptor_write_master</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="mm_read" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>mm_read_address</name>
+    <direction>Output</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>mm_read_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>mm_read_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>mm_read_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>mm_read_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>mm_read_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_tx_mm_read</slaveName>
+    <name>mm_interconnect_1.msgdma_tx_mm_read</name>
+    <baseAddress>0</baseAddress>
+    <span>268435456</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_read_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_read_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_read_master_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_tx_descriptor_read_master</slaveName>
+    <name>mm_interconnect_1.msgdma_tx_descriptor_read_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_write_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>3</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_write_master_address</name>
+    <direction>Output</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_response</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>descriptor_write_master_writeresponsevalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>msgdma_tx_descriptor_write_master</slaveName>
+    <name>mm_interconnect_1.msgdma_tx_descriptor_write_master</name>
+    <baseAddress>0</baseAddress>
+    <span>536870912</span>
+   </memoryBlock>
+  </interface>
+  <interface name="clock" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_n" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n_reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+  </interface>
+  <interface name="prefetcher_csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>prefetcher_csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>prefetcher_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="csr_irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>msgdma_tx.prefetcher_csr</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_irq_irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+  <interface name="st_source" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clock</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset_n</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>st_source_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>st_source_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>st_source_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>st_source_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>st_source_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>st_source_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>st_source_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="onchip_flash"
+   kind="altera_onchip_flash"
+   version="19.1"
+   path="onchip_flash">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BYTES_PER_PAGE</name>
+   <value>8192</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_ONLY_MODE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_END_ADDR</name>
+   <value>32767</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR1_START_ADDR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_END_ADDR</name>
+   <value>65535</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR2_START_ADDR</name>
+   <value>32768</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_END_ADDR</name>
+   <value>458751</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR3_START_ADDR</name>
+   <value>65536</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_END_ADDR</name>
+   <value>753663</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR4_START_ADDR</name>
+   <value>458752</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_ENABLED</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_END_ADDR</name>
+   <value>1441791</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SECTOR5_START_ADDR</name>
+   <value>753664</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.FLASH_INSTALL_DIR</name>
+   <value>APP_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.IS_FLASH</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILENAME</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="DATA_INTERFACE">
+   <type>java.lang.String</type>
+   <value>Parallel</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_BURST_MODE">
+   <type>java.lang.String</type>
+   <value>Incrementing</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_BURST_COUNT">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY">
+   <type>double</type>
+   <value>50.0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONFIGURATION_SCHEME">
+   <type>java.lang.String</type>
+   <value>Internal Configuration</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CONFIGURATION_MODE">
+   <type>java.lang.String</type>
+   <value>Single Uncompressed Image</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ID">
+   <type>[Ljava.lang.String;</type>
+   <value>1,2,3,4,5</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ACCESS_MODE">
+   <type>[Ljava.lang.String;</type>
+   <value>Read and write,Read and write,Read and write,Read and write,Read and write</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_ADDRESS_MAPPING">
+   <type>[Ljava.lang.String;</type>
+   <value>0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_STORAGE_TYPE">
+   <type>[Ljava.lang.String;</type>
+   <value>UFM,UFM,UFM,CFM,CFM</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initFlashContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileNameForSim">
+   <type>java.lang.String</type>
+   <value>altera_onchip_flash.dat</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>q_sys_onchip_flash</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="INIT_FILENAME">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="INIT_FILENAME_SIM">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PART_NAME">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_CLOCK_RATE">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="DEVICE_ID">
+   <type>java.lang.String</type>
+   <value>50</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_START_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_END_ADDR">
+   <type>int</type>
+   <value>8191</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_START_ADDR">
+   <type>int</type>
+   <value>8192</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_END_ADDR">
+   <type>int</type>
+   <value>16383</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_START_ADDR">
+   <type>int</type>
+   <value>16384</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_END_ADDR">
+   <type>int</type>
+   <value>114687</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_START_ADDR">
+   <type>int</type>
+   <value>114688</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_END_ADDR">
+   <type>int</type>
+   <value>188415</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_START_ADDR">
+   <type>int</type>
+   <value>188416</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_VALID_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_VALID_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_UFM_VALID_ADDR">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_UFM_VALID_ADDR">
+   <type>int</type>
+   <value>114687</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR1_MAP">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR2_MAP">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR3_MAP">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR4_MAP">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR5_MAP">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE1_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE2_END_ADDR">
+   <type>int</type>
+   <value>360447</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE1_OFFSET">
+   <type>int</type>
+   <value>2048</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE2_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADDR_RANGE3_OFFSET">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_ADDR_WIDTH">
+   <type>int</type>
+   <value>19</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_DATA_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AVMM_DATA_BURSTCOUNT_WIDTH">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SECTOR_READ_PROTECTION_MODE">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_SEQ_READ_DATA_COUNT">
+   <type>int</type>
+   <value>4</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_ADDR_ALIGNMENT_BITS">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_READ_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>5</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_RESET_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>12</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>60</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>17500000</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX">
+   <type>int</type>
+   <value>15250</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="PARALLEL_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READ_AND_WRITE_MODE">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="WRAPPING_BURST_MODE">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_DUAL_BOOT">
+   <type>java.lang.String</type>
+   <value>False</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_ERAM_SKIP">
+   <type>java.lang.String</type>
+   <value>True</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IS_COMPRESSED_IMAGE">
+   <type>java.lang.String</type>
+   <value>False</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="nreset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="data" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1441792</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>nreset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1441792</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avmm_data_addr</name>
+    <direction>Input</direction>
+    <width>19</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avmm_data_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avmm_data_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avmm_data_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avmm_data_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>avmm_data_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>avmm_data_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>avmm_data_burstcount</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>burstcount</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>nreset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>avmm_csr_addr</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>avmm_csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>avmm_csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>avmm_csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>avmm_csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="output_pio"
+   kind="altera_avalon_pio"
+   version="19.1"
+   path="output_pio">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CAPTURE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DATA_WIDTH</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.EDGE_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_IN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_OUT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.HAS_TRI</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.IRQ_TYPE</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_VALUE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,pio-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>gpio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>pio</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.altr,gpio-bank-width</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.resetvalue</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="bitClearingEdgeCapReg">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitModifyingOutReg">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="captureEdge">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="direction">
+   <type>java.lang.String</type>
+   <value>Output</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="edgeType">
+   <type>java.lang.String</type>
+   <value>RISING</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateIRQ">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="irqType">
+   <type>java.lang.String</type>
+   <value>LEVEL</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDoTestBenchWiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simDrivenValue">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="width">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockRate">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="derived_has_tri">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_out">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_in">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_do_test_bench_wiring">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_capture">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_edge_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_irq_type">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_has_irq">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="external_connection" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>out_port</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>export</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sensor_interface"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_interface">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_0</moduleName>
+    <slaveName>sensor_interface_calibration_ram_interface</slaveName>
+    <name>mm_interconnect_0.sensor_interface_calibration_ram_interface</name>
+    <baseAddress>0</baseAddress>
+    <span>1024</span>
+   </memoryBlock>
+  </interface>
+ </module>
+ <module name="sys_clk" kind="clock_source" version="19.1" path="sys_clk">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="clockFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="clockFrequencyKnown">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inputClockFrequency">
+   <type>long</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk_in</sysinfo_arg>
+  </parameter>
+  <parameter name="resetSynchronousEdges">
+   <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk_in" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>clk</value>
+   </assignment>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>qsys.ui.export_name</name>
+    <value>reset</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value>clk_in</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>50000000</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clk_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sysid</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sysid.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sys_clk_timer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>cpu</moduleName>
+    <slaveName>clk</slaveName>
+    <name>cpu.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>output_pio</moduleName>
+    <slaveName>clk</slaveName>
+    <name>output_pio.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>button_pio</moduleName>
+    <slaveName>clk</slaveName>
+    <name>button_pio.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>clk</slaveName>
+    <name>debug_uart.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>clk</slaveName>
+    <name>onchip_flash.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>tx_multiplexer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>tx_multiplexer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>channel_adapter_0</moduleName>
+    <slaveName>clk</slaveName>
+    <name>channel_adapter_0.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>udp_generator</moduleName>
+    <slaveName>clk</slaveName>
+    <name>udp_generator.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>frame_timer</moduleName>
+    <slaveName>clk</slaveName>
+    <name>frame_timer.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>sensor_interface</moduleName>
+    <slaveName>clk</slaveName>
+    <name>sensor_interface.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>clk1</slaveName>
+    <name>descriptor_memory.clk1</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>clk1</slaveName>
+    <name>calibration_ram.clk1</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>clk2</slaveName>
+    <name>calibration_ram.clk2</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>clock</slaveName>
+    <name>msgdma_tx.clock</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>clock</slaveName>
+    <name>msgdma_rx.clock</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>control_port_clock_connection</slaveName>
+    <name>eth_tse.control_port_clock_connection</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>enet_pll</moduleName>
+    <slaveName>inclk_interface</slaveName>
+    <name>enet_pll.inclk_interface</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>altpll_shift</moduleName>
+    <slaveName>inclk_interface</slaveName>
+    <name>altpll_shift.inclk_interface</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>receive_clock_connection</slaveName>
+    <name>eth_tse.receive_clock_connection</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>transmit_clock_connection</slaveName>
+    <name>eth_tse.transmit_clock_connection</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_0</moduleName>
+    <slaveName>sys_clk_clk</slaveName>
+    <name>mm_interconnect_0.sys_clk_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>mm_interconnect_1</moduleName>
+    <slaveName>sys_clk_clk</slaveName>
+    <name>mm_interconnect_1.sys_clk_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>irq_mapper</moduleName>
+    <slaveName>clk</slaveName>
+    <name>irq_mapper.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>irq_synchronizer</moduleName>
+    <slaveName>sender_clk</slaveName>
+    <name>irq_synchronizer.sender_clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>avalon_st_adapter</moduleName>
+    <slaveName>in_clk_0</slaveName>
+    <name>avalon_st_adapter.in_clk_0</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>avalon_st_adapter_001</moduleName>
+    <slaveName>in_clk_0</slaveName>
+    <name>avalon_st_adapter_001.in_clk_0</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_controller</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_controller.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_controller_001</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_controller_001.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_translator</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_translator.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_controller_004</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_controller_004.clk</name>
+   </clockDomainMember>
+   <clockDomainMember>
+    <isBridge>false</isBridge>
+    <moduleName>rst_translator_001</moduleName>
+    <slaveName>clk</slaveName>
+    <name>rst_translator_001.clk</name>
+   </clockDomainMember>
+  </interface>
+  <interface name="clk_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>clk_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_n_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   path="sys_clk_timer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALWAYS_RUN</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.COUNTER_SIZE</name>
+   <value>32</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FIXED_PERIOD</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.FREQ</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.LOAD_VALUE</name>
+   <value>499999</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.MULT</name>
+   <value>0.001</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.PERIOD_UNITS</name>
+   <value>ms</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RESET_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SNAPSHOT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
+   <value>100</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,timer-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>timer</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>timer</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.clock-frequency</name>
+   <value>50000000</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="alwaysRun">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="counterSize">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="fixedPeriod">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="period">
+   <type>java.lang.String</type>
+   <value>10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnits">
+   <type>java.lang.String</type>
+   <value>MSEC</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="snapshot">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timeoutPulseOutput">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="systemFrequency">
+   <type>long</type>
+   <value>50000000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>CLOCK_RATE</sysinfo_type>
+   <sysinfo_arg>clk</sysinfo_arg>
+  </parameter>
+  <parameter name="watchdogPulse">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timerPreset">
+   <type>java.lang.String</type>
+   <value>FULL_FEATURED</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="periodUnitsString">
+   <type>java.lang.String</type>
+   <value>ms</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="valueInSecond">
+   <type>double</type>
+   <value>0.001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="loadValue">
+   <type>java.lang.String</type>
+   <value>499999</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="mult">
+   <type>double</type>
+   <value>0.001</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ticksPerSec">
+   <type>double</type>
+   <value>100.0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave_address_width">
+   <type>int</type>
+   <value>3</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>java.lang.Boolean</type>
+    <value>true</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>java.lang.Long</type>
+    <value>50000000</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isTimerDevice</name>
+    <value>1</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>NATIVE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write_n</role>
+   </port>
+  </interface>
+  <interface name="irq" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value>sys_clk_timer.s1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="19.1"
+   path="sysid">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ID</name>
+   <value>4207856382</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.TIMESTAMP</name>
+   <value>1728634208</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.compatible</name>
+   <value>altr,sysid-1.0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.group</name>
+   <value>sysid</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.name</name>
+   <value>sysid</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.id</name>
+   <value>4207856382</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.params.timestamp</name>
+   <value>1728634208</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.dts.vendor</name>
+   <value>altr</value>
+  </assignment>
+  <parameter name="id">
+   <type>int</type>
+   <value>-87110914</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="timestamp">
+   <type>int</type>
+   <value>1728634208</value>
+   <derived>true</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>GENERATION_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clock</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="control_slave" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>false</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>false</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>8</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="tx_multiplexer"
+   kind="multiplexer"
+   version="19.1"
+   path="tx_multiplexer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="bitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="usePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmpty">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="numInputInterfaces">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="schedulingSize">
+   <type>int</type>
+   <value>512</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="packetScheduling">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useHighBitsOfChannel">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="symbolsPerBeat">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="errorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_n</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_n</role>
+   </port>
+  </interface>
+  <interface name="out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+   <port>
+    <name>out_channel</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>channel</role>
+   </port>
+  </interface>
+  <interface name="in0" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in0_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in0_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in0_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+  <interface name="in1" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in1_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in1_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in1_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in1_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in1_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in1_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in1_error</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="udp_generator"
+   kind="udp_generator"
+   version="1.0"
+   path="udp_generator">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>32</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="data_in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>data_in_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_in_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_in_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>data_in_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_in_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_in_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="mm_interconnect_0"
+   kind="altera_mm_interconnect"
+   version="19.1"
+   path="mm_interconnect_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>interconnect_id.calibration_ram.s2</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.sensor_interface.calibration_ram_interface</name>
+   <value>0</value>
+  </assignment>
+  <parameter name="COMPOSE_CONTENTS">
+   <type>java.lang.String</type>
+   <value>add_instance {sensor_interface_calibration_ram_interface_translator} {altera_merlin_master_translator};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_W} {16};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CLKEN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {SYNC_RESET} {0};add_instance {calibration_ram_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_rst_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0} {calibration_ram_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_rst_reset_bridge.out_reset} {sensor_interface_calibration_ram_interface_translator.reset} {reset};add_connection {sensor_interface_rst_reset_bridge.out_reset} {calibration_ram_s2_translator.reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_calibration_ram_interface_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s2_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_rst_reset_bridge.clk} {clock};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {sensor_interface_rst_reset_bridge_in_reset} {reset} {slave};set_interface_property {sensor_interface_rst_reset_bridge_in_reset} {EXPORT_OF} {sensor_interface_rst_reset_bridge.in_reset};add_interface {sensor_interface_calibration_ram_interface} {avalon} {slave};set_interface_property {sensor_interface_calibration_ram_interface} {EXPORT_OF} {sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0};add_interface {calibration_ram_s2} {avalon} {master};set_interface_property {calibration_ram_s2} {EXPORT_OF} {calibration_ram_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.calibration_ram.s2} {0};set_module_assignment {interconnect_id.sensor_interface.calibration_ram_interface} {0};</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="sys_clk_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sys_clk_clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface
+     name="sensor_interface_rst_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sensor_interface_rst_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface
+     name="sensor_interface_calibration_ram_interface"
+     kind="avalon_slave"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>1024</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>sensor_interface_rst_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sensor_interface_calibration_ram_interface_address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>sensor_interface_calibration_ram_interface_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>sensor_interface_calibration_ram_interface_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>sensor_interface_calibration_ram_interface_readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_s2" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>sensor_interface_rst_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>calibration_ram_s2_address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_readdata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_writedata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_byteenable</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>calibration_ram_s2_clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>s2</slaveName>
+    <name>calibration_ram.s2</name>
+    <baseAddress>0</baseAddress>
+    <span>640</span>
+   </memoryBlock>
+  </interface>
+ </module>
+ <module
+   name="mm_interconnect_1"
+   kind="altera_mm_interconnect"
+   version="19.1"
+   path="mm_interconnect_1">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>interconnect_id.button_pio.s1</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.calibration_ram.s1</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.cpu.data_master</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.cpu.debug_mem_slave</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.cpu.instruction_master</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.ddr3_ram.avl</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.debug_uart.s1</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.descriptor_memory.s1</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.eth_tse.control_port</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.ext_flash.avl_csr</name>
+   <value>7</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.ext_flash.avl_mem</name>
+   <value>8</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.frame_timer.s1</name>
+   <value>9</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_rx.csr</name>
+   <value>10</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_rx.descriptor_read_master</name>
+   <value>2</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_rx.descriptor_write_master</name>
+   <value>3</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_rx.mm_write</name>
+   <value>4</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_rx.prefetcher_csr</name>
+   <value>11</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_tx.csr</name>
+   <value>12</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_tx.descriptor_read_master</name>
+   <value>5</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_tx.descriptor_write_master</name>
+   <value>6</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_tx.mm_read</name>
+   <value>7</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.msgdma_tx.prefetcher_csr</name>
+   <value>13</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.onchip_flash.csr</name>
+   <value>14</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.onchip_flash.data</name>
+   <value>15</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.output_pio.s1</name>
+   <value>16</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.sensor_interface.csr</name>
+   <value>17</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.sys_clk_timer.s1</name>
+   <value>18</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.sysid.control_slave</name>
+   <value>19</value>
+  </assignment>
+  <assignment>
+   <name>interconnect_id.udp_generator.csr</name>
+   <value>20</value>
+  </assignment>
+  <parameter name="COMPOSE_CONTENTS">
+   <type>java.lang.String</type>
+   <value><![CDATA[add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_instruction_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_mm_read_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_mm_write_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {ddr3_ram_avl_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_W} {25};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READ} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINBURSTTRANSFER} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_LOCK} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_mem_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_W} {24};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_W} {7};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {eth_tse_control_port_translator} {altera_merlin_slave_translator};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READLATENCY} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READ} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITE} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_ADDRESS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_LOCK} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {eth_tse_control_port_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sysid_control_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READ} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sysid_control_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sysid_control_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {udp_generator_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READ} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {udp_generator_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {udp_generator_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_data_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_W} {19};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_data_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_data_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_debug_mem_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READ} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {descriptor_memory_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_W} {11};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READ} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sys_clk_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {output_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {output_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {output_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {output_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {output_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {button_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {button_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {button_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {button_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {button_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {debug_uart_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {debug_uart_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READ} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINTRANSFER} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {debug_uart_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {debug_uart_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {frame_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {frame_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {frame_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {frame_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {calibration_ram_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_data_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_data_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="3"
+   name="ddr3_ram_avl_translator.avalon_universal_slave_0"
+   start="0x0000000008000000"
+   end="0x00000000010000000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="7"
+   name="ext_flash_avl_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403d20"
+   end="0x00000000018403d40"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="8"
+   name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
+   start="0x0000000014000000"
+   end="0x00000000018000000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="6"
+   name="eth_tse_control_port_translator.avalon_universal_slave_0"
+   start="0x0000000018403000"
+   end="0x00000000018403400"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="19"
+   name="sysid_control_slave_translator.avalon_universal_slave_0"
+   start="0x0000000018403d68"
+   end="0x00000000018403d70"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="12"
+   name="msgdma_tx_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403d00"
+   end="0x00000000018403d20"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="10"
+   name="msgdma_rx_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403ce0"
+   end="0x00000000018403d00"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="14"
+   name="onchip_flash_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403d60"
+   end="0x00000000018403d68"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="20"
+   name="udp_generator_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403cc0"
+   end="0x00000000018403ce0"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="17"
+   name="sensor_interface_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403d50"
+   end="0x00000000018403d60"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="15"
+   name="onchip_flash_data_translator.avalon_universal_slave_0"
+   start="0x0000000018200000"
+   end="0x00000000018400000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="2"
+   name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
+   start="0x0000000018402800"
+   end="0x00000000018403000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="13"
+   name="msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403ca0"
+   end="0x00000000018403cc0"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="11"
+   name="msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0"
+   start="0x0000000018403c80"
+   end="0x00000000018403ca0"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="5"
+   name="descriptor_memory_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018400000"
+   end="0x00000000018402000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="18"
+   name="sys_clk_timer_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403c60"
+   end="0x00000000018403c80"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="16"
+   name="output_pio_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403c40"
+   end="0x00000000018403c60"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="0"
+   name="button_pio_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403d40"
+   end="0x00000000018403d50"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="4"
+   name="debug_uart_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403c20"
+   end="0x00000000018403c40"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="9"
+   name="frame_timer_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403c00"
+   end="0x00000000018403c20"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="1"
+   name="calibration_ram_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018403400"
+   end="0x00000000018403800"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="3"
+   name="ddr3_ram_avl_translator.avalon_universal_slave_0"
+   start="0x0000000008000000"
+   end="0x00000000010000000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="8"
+   name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
+   start="0x0000000014000000"
+   end="0x00000000018000000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="15"
+   name="onchip_flash_data_translator.avalon_universal_slave_0"
+   start="0x0000000018200000"
+   end="0x00000000018400000"
+   responds="1"
+   user_default="0" />
+ <slave
+   id="2"
+   name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
+   start="0x0000000018402800"
+   end="0x00000000018403000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_mm_read_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="3"
+   name="ddr3_ram_avl_translator.avalon_universal_slave_0"
+   start="0x0000000008000000"
+   end="0x00000000010000000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ID} {7};set_instance_parameter_value {msgdma_tx_mm_read_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_mm_read_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_mm_write_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="3"
+   name="ddr3_ram_avl_translator.avalon_universal_slave_0"
+   start="0x0000000008000000"
+   end="0x00000000010000000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ID} {4};set_instance_parameter_value {msgdma_rx_mm_write_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_mm_write_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="5"
+   name="descriptor_memory_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018400000"
+   end="0x00000000018402000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ID} {5};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="5"
+   name="descriptor_memory_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018400000"
+   end="0x00000000018402000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ID} {2};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="5"
+   name="descriptor_memory_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018400000"
+   end="0x00000000018402000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ID} {6};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {msgdma_rx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
+<address_map>
+ <slave
+   id="5"
+   name="descriptor_memory_s1_translator.avalon_universal_slave_0"
+   start="0x0000000018400000"
+   end="0x00000000018402000"
+   responds="1"
+   user_default="0" />
+</address_map>
+};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ID} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {ddr3_ram_avl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_DATA_W} {121};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ddr3_ram_avl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ddr3_ram_avl_agent} {ID} {3};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {ECC_ENABLE} {0};add_instance {ddr3_ram_avl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {FIFO_DEPTH} {33};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ddr3_ram_avl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {FIFO_DEPTH} {64};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ext_flash_avl_csr_agent} {ID} {7};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BYTE_CNT} {256};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BURSTWRAP} {255};set_instance_parameter_value {ext_flash_avl_mem_agent} {ID} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_mem_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {eth_tse_control_port_agent} {altera_merlin_slave_agent};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_H} {31};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_L} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {eth_tse_control_port_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {eth_tse_control_port_agent} {ST_DATA_W} {121};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {eth_tse_control_port_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {eth_tse_control_port_agent} {ID} {6};set_instance_parameter_value {eth_tse_control_port_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {ECC_ENABLE} {0};add_instance {eth_tse_control_port_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_control_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sysid_control_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sysid_control_slave_agent} {ID} {19};set_instance_parameter_value {sysid_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_csr_agent} {ID} {12};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_csr_agent} {ID} {10};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_csr_agent} {ID} {14};set_instance_parameter_value {onchip_flash_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {udp_generator_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {udp_generator_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {udp_generator_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {udp_generator_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {udp_generator_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {udp_generator_csr_agent} {ID} {20};set_instance_parameter_value {udp_generator_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {ECC_ENABLE} {0};add_instance {udp_generator_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sensor_interface_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sensor_interface_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sensor_interface_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sensor_interface_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sensor_interface_csr_agent} {ID} {17};set_instance_parameter_value {sensor_interface_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {ECC_ENABLE} {0};add_instance {sensor_interface_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_data_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_data_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_data_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_data_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_data_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BYTE_CNT} {32};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_data_agent} {ID} {15};set_instance_parameter_value {onchip_flash_data_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_data_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ID} {13};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ID} {11};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {descriptor_memory_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {descriptor_memory_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {descriptor_memory_s1_agent} {ID} {5};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {ECC_ENABLE} {0};add_instance {descriptor_memory_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {18};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {output_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {output_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {output_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {output_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {output_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {output_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {output_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {output_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {output_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {output_pio_s1_agent} {ID} {16};set_instance_parameter_value {output_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {ECC_ENABLE} {0};add_instance {output_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {button_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {button_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {button_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {button_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {button_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {button_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {button_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {button_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {button_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {button_pio_s1_agent} {ID} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {ECC_ENABLE} {0};add_instance {button_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {debug_uart_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {debug_uart_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {debug_uart_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {debug_uart_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {debug_uart_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {debug_uart_s1_agent} {ID} {4};set_instance_parameter_value {debug_uart_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {ECC_ENABLE} {0};add_instance {debug_uart_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {frame_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {frame_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {frame_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {frame_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {frame_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {frame_timer_s1_agent} {ID} {9};set_instance_parameter_value {frame_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {ECC_ENABLE} {0};add_instance {frame_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {calibration_ram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_LOCK} {51};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_H} {93};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_L} {91};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_POSTED} {48};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_H} {84};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_L} {80};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_H} {89};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_L} {85};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {calibration_ram_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_agent} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {calibration_ram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {calibration_ram_s1_agent} {ID} {1};set_instance_parameter_value {calibration_ram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {ECC_ENABLE} {0};add_instance {calibration_ram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {104};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 8 15 5 2 6 1 9 4 16 18 11 13 20 10 12 7 0 17 14 19 };set_instance_parameter_value {router} {CHANNEL_ID} {000000000000000000001 000000000000000000100 000000000010000000000 000000100000000000000 000000000100000000000 000000000000000001000 100000000000000000000 010000000000000000000 001000000000000000000 000010000000000000000 000001000000000000000 000000010000000000000 000000001000000000000 000000000000100000000 000000000000001000000 000000000000000100000 000000000000000000010 000100000000000000000 000000000001000000000 000000000000010000000 000000000000000010000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both both both both both both both both both both read both both read };set_instance_parameter_value {router} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18400000 0x18402800 0x18403000 0x18403400 0x18403c00 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 };set_instance_parameter_value {router} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18402000 0x18403000 0x18403400 0x18403800 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 0x18403d70 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {121};set_instance_parameter_value {router} {ST_CHANNEL_W} {21};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {3 8 15 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18402800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18403000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {121};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {3 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {121};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_002} {DECODER_TYPE} {0};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {3 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {64};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_003} {ST_DATA_W} {121};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_003} {DECODER_TYPE} {0};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {5 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {64};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_004} {ST_DATA_W} {121};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_004} {DECODER_TYPE} {0};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {5 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {64};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_005} {ST_DATA_W} {121};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_005} {DECODER_TYPE} {0};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {5 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {64};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_006} {ST_DATA_W} {121};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_006} {DECODER_TYPE} {0};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {5 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {64};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_007} {ST_DATA_W} {121};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_007} {DECODER_TYPE} {0};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 1 7 4 };set_instance_parameter_value {router_008} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both read read write };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {64};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_008} {ST_DATA_W} {121};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {64};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_009} {ST_DATA_W} {121};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_010} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {64};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_010} {ST_DATA_W} {121};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {64};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_011} {ST_DATA_W} {121};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {64};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_012} {ST_DATA_W} {121};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {64};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_013} {ST_DATA_W} {121};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {64};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_014} {ST_DATA_W} {121};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {64};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_015} {ST_DATA_W} {121};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {64};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_016} {ST_DATA_W} {121};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {router_017} {altera_merlin_router};set_instance_parameter_value {router_017} {DESTINATION_ID} {0 };set_instance_parameter_value {router_017} {CHANNEL_ID} {1 };set_instance_parameter_value {router_017} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_017} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_017} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_017} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_017} {SPAN_OFFSET} {};set_instance_parameter_value {router_017} {PKT_ADDR_H} {64};set_instance_parameter_value {router_017} {PKT_ADDR_L} {36};set_instance_parameter_value {router_017} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_017} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_017} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_017} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_017} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_017} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_017} {ST_DATA_W} {121};set_instance_parameter_value {router_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_017} {DECODER_TYPE} {1};set_instance_parameter_value {router_017} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_017} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_017} {MEMORY_ALIASING_DECODE} {0};add_instance {router_018} {altera_merlin_router};set_instance_parameter_value {router_018} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_018} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_018} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_018} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_018} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_018} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_018} {SPAN_OFFSET} {};set_instance_parameter_value {router_018} {PKT_ADDR_H} {64};set_instance_parameter_value {router_018} {PKT_ADDR_L} {36};set_instance_parameter_value {router_018} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_018} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_018} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_018} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_018} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_018} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_018} {ST_DATA_W} {121};set_instance_parameter_value {router_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_018} {DECODER_TYPE} {1};set_instance_parameter_value {router_018} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_018} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_018} {MEMORY_ALIASING_DECODE} {0};add_instance {router_019} {altera_merlin_router};set_instance_parameter_value {router_019} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_019} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_019} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_019} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_019} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_019} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_019} {SPAN_OFFSET} {};set_instance_parameter_value {router_019} {PKT_ADDR_H} {64};set_instance_parameter_value {router_019} {PKT_ADDR_L} {36};set_instance_parameter_value {router_019} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_019} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_019} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_019} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_019} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_019} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_019} {ST_DATA_W} {121};set_instance_parameter_value {router_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_019} {DECODER_TYPE} {1};set_instance_parameter_value {router_019} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_019} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_019} {MEMORY_ALIASING_DECODE} {0};add_instance {router_020} {altera_merlin_router};set_instance_parameter_value {router_020} {DESTINATION_ID} {0 };set_instance_parameter_value {router_020} {CHANNEL_ID} {1 };set_instance_parameter_value {router_020} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_020} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_020} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_020} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_020} {SPAN_OFFSET} {};set_instance_parameter_value {router_020} {PKT_ADDR_H} {64};set_instance_parameter_value {router_020} {PKT_ADDR_L} {36};set_instance_parameter_value {router_020} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_020} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_020} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_020} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_020} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_020} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_020} {ST_DATA_W} {121};set_instance_parameter_value {router_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_020} {DECODER_TYPE} {1};set_instance_parameter_value {router_020} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_020} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_020} {MEMORY_ALIASING_DECODE} {0};add_instance {router_021} {altera_merlin_router};set_instance_parameter_value {router_021} {DESTINATION_ID} {0 };set_instance_parameter_value {router_021} {CHANNEL_ID} {1 };set_instance_parameter_value {router_021} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_021} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_021} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_021} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_021} {SPAN_OFFSET} {};set_instance_parameter_value {router_021} {PKT_ADDR_H} {64};set_instance_parameter_value {router_021} {PKT_ADDR_L} {36};set_instance_parameter_value {router_021} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_021} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_021} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_021} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_021} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_021} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_021} {ST_DATA_W} {121};set_instance_parameter_value {router_021} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_021} {DECODER_TYPE} {1};set_instance_parameter_value {router_021} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_021} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_021} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_021} {MEMORY_ALIASING_DECODE} {0};add_instance {router_022} {altera_merlin_router};set_instance_parameter_value {router_022} {DESTINATION_ID} {0 5 2 6 3 };set_instance_parameter_value {router_022} {CHANNEL_ID} {00001 00010 00100 01000 10000 };set_instance_parameter_value {router_022} {TYPE_OF_TRANSACTION} {both read read write write };set_instance_parameter_value {router_022} {START_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {END_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {NON_SECURED_TAG} {1 1 1 1 1 };set_instance_parameter_value {router_022} {SECURED_RANGE_PAIRS} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SECURED_RANGE_LIST} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SPAN_OFFSET} {};set_instance_parameter_value {router_022} {PKT_ADDR_H} {64};set_instance_parameter_value {router_022} {PKT_ADDR_L} {36};set_instance_parameter_value {router_022} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_022} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_022} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_022} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_022} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_022} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_022} {ST_DATA_W} {121};set_instance_parameter_value {router_022} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_022} {DECODER_TYPE} {1};set_instance_parameter_value {router_022} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_022} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_022} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_022} {MEMORY_ALIASING_DECODE} {0};add_instance {router_023} {altera_merlin_router};set_instance_parameter_value {router_023} {DESTINATION_ID} {0 };set_instance_parameter_value {router_023} {CHANNEL_ID} {1 };set_instance_parameter_value {router_023} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_023} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_023} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_023} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_023} {SPAN_OFFSET} {};set_instance_parameter_value {router_023} {PKT_ADDR_H} {64};set_instance_parameter_value {router_023} {PKT_ADDR_L} {36};set_instance_parameter_value {router_023} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_023} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_023} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_023} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_023} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_023} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_023} {ST_DATA_W} {121};set_instance_parameter_value {router_023} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_023} {DECODER_TYPE} {1};set_instance_parameter_value {router_023} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_023} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_023} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_023} {MEMORY_ALIASING_DECODE} {0};add_instance {router_024} {altera_merlin_router};set_instance_parameter_value {router_024} {DESTINATION_ID} {0 };set_instance_parameter_value {router_024} {CHANNEL_ID} {1 };set_instance_parameter_value {router_024} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_024} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_024} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_024} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_024} {SPAN_OFFSET} {};set_instance_parameter_value {router_024} {PKT_ADDR_H} {64};set_instance_parameter_value {router_024} {PKT_ADDR_L} {36};set_instance_parameter_value {router_024} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_024} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_024} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_024} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_024} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_024} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_024} {ST_DATA_W} {121};set_instance_parameter_value {router_024} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_024} {DECODER_TYPE} {1};set_instance_parameter_value {router_024} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_024} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_024} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_024} {MEMORY_ALIASING_DECODE} {0};add_instance {router_025} {altera_merlin_router};set_instance_parameter_value {router_025} {DESTINATION_ID} {0 };set_instance_parameter_value {router_025} {CHANNEL_ID} {1 };set_instance_parameter_value {router_025} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_025} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_025} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_025} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_025} {SPAN_OFFSET} {};set_instance_parameter_value {router_025} {PKT_ADDR_H} {64};set_instance_parameter_value {router_025} {PKT_ADDR_L} {36};set_instance_parameter_value {router_025} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_025} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_025} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_025} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_025} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_025} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_025} {ST_DATA_W} {121};set_instance_parameter_value {router_025} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_025} {DECODER_TYPE} {1};set_instance_parameter_value {router_025} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_025} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_025} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_025} {MEMORY_ALIASING_DECODE} {0};add_instance {router_026} {altera_merlin_router};set_instance_parameter_value {router_026} {DESTINATION_ID} {0 };set_instance_parameter_value {router_026} {CHANNEL_ID} {1 };set_instance_parameter_value {router_026} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_026} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_026} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_026} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_026} {SPAN_OFFSET} {};set_instance_parameter_value {router_026} {PKT_ADDR_H} {64};set_instance_parameter_value {router_026} {PKT_ADDR_L} {36};set_instance_parameter_value {router_026} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_026} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_026} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_026} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_026} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_026} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_026} {ST_DATA_W} {121};set_instance_parameter_value {router_026} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_026} {DECODER_TYPE} {1};set_instance_parameter_value {router_026} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_026} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_026} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_026} {MEMORY_ALIASING_DECODE} {0};add_instance {router_027} {altera_merlin_router};set_instance_parameter_value {router_027} {DESTINATION_ID} {0 };set_instance_parameter_value {router_027} {CHANNEL_ID} {1 };set_instance_parameter_value {router_027} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_027} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_027} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_027} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_027} {SPAN_OFFSET} {};set_instance_parameter_value {router_027} {PKT_ADDR_H} {64};set_instance_parameter_value {router_027} {PKT_ADDR_L} {36};set_instance_parameter_value {router_027} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_027} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_027} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_027} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_027} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_027} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_027} {ST_DATA_W} {121};set_instance_parameter_value {router_027} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_027} {DECODER_TYPE} {1};set_instance_parameter_value {router_027} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_027} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_027} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_027} {MEMORY_ALIASING_DECODE} {0};add_instance {router_028} {altera_merlin_router};set_instance_parameter_value {router_028} {DESTINATION_ID} {0 };set_instance_parameter_value {router_028} {CHANNEL_ID} {1 };set_instance_parameter_value {router_028} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_028} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_028} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_028} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_028} {SPAN_OFFSET} {};set_instance_parameter_value {router_028} {PKT_ADDR_H} {46};set_instance_parameter_value {router_028} {PKT_ADDR_L} {18};set_instance_parameter_value {router_028} {PKT_PROTECTION_H} {93};set_instance_parameter_value {router_028} {PKT_PROTECTION_L} {91};set_instance_parameter_value {router_028} {PKT_DEST_ID_H} {89};set_instance_parameter_value {router_028} {PKT_DEST_ID_L} {85};set_instance_parameter_value {router_028} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {router_028} {PKT_TRANS_READ} {50};set_instance_parameter_value {router_028} {ST_DATA_W} {103};set_instance_parameter_value {router_028} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_028} {DECODER_TYPE} {1};set_instance_parameter_value {router_028} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_028} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_028} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_028} {MEMORY_ALIASING_DECODE} {0};add_instance {cpu_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_data_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_limiter} {REORDER} {0};add_instance {cpu_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_limiter} {REORDER} {0};add_instance {ext_flash_avl_mem_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BURSTWRAP_H} {87};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_MASK} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_VALUE} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {calibration_ram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BYTE_CNT_H} {54};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {21};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {4};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {4};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {5};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 1 1 1 1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_015} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_015} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_015} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_015} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_015} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_015} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_016} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_016} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_016} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_016} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_016} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_016} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_017} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_017} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_017} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_017} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_017} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_017} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_018} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_018} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_018} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_018} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_018} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_018} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_019} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_019} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_019} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_019} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_019} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_019} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_020} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_020} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_020} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_020} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_020} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_020} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {4};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {5};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_015} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_015} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_015} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_015} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_016} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_016} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_016} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_016} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_017} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_017} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_017} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_017} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_018} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_018} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_018} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_018} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_019} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_019} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_019} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_019} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_020} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_020} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_020} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_020} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {21};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {4};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {calibration_ram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {calibration_ram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {67};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {88};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {80};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {121};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_004} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_004} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_004} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_004} {USE_PACKETS} {1};set_instance_parameter_value {crosser_004} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_004} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_004} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_004} {USE_ERROR} {0};set_instance_parameter_value {crosser_004} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_004} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_005} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_005} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_005} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_005} {USE_PACKETS} {1};set_instance_parameter_value {crosser_005} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_005} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_005} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_005} {USE_ERROR} {0};set_instance_parameter_value {crosser_005} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_005} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_006} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_006} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_006} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_006} {USE_PACKETS} {1};set_instance_parameter_value {crosser_006} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_006} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_006} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_006} {USE_ERROR} {0};set_instance_parameter_value {crosser_006} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_006} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_007} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_007} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_007} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_007} {USE_PACKETS} {1};set_instance_parameter_value {crosser_007} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_007} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_007} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_007} {USE_ERROR} {0};set_instance_parameter_value {crosser_007} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_007} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_008} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_008} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_008} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_008} {USE_PACKETS} {1};set_instance_parameter_value {crosser_008} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_008} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_008} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_008} {USE_ERROR} {0};set_instance_parameter_value {crosser_008} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_008} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_009} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_009} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_009} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_009} {USE_PACKETS} {1};set_instance_parameter_value {crosser_009} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_009} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_009} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_009} {USE_ERROR} {0};set_instance_parameter_value {crosser_009} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_009} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_010} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_010} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_010} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_010} {USE_PACKETS} {1};set_instance_parameter_value {crosser_010} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_010} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_010} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_010} {USE_ERROR} {0};set_instance_parameter_value {crosser_010} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_010} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_011} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_011} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_011} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_011} {USE_PACKETS} {1};set_instance_parameter_value {crosser_011} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_011} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_011} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_011} {USE_ERROR} {0};set_instance_parameter_value {crosser_011} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_011} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_012} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_012} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_012} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_012} {USE_PACKETS} {1};set_instance_parameter_value {crosser_012} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_012} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_012} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_012} {USE_ERROR} {0};set_instance_parameter_value {crosser_012} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_012} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_013} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_013} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_013} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_013} {USE_PACKETS} {1};set_instance_parameter_value {crosser_013} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_013} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_013} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_013} {USE_ERROR} {0};set_instance_parameter_value {crosser_013} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_013} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {USE_OUTPUT_PIPELINE} {0};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_soft_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ext_flash_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ext_flash_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ext_flash_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ext_flash_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ext_flash_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {eth_tse_reset_connection_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_avl_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ddr3_ram_afi_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {150000000};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ext_flash_clock_bridge_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {0};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {msgdma_tx_mm_read_translator.avalon_universal_master_0} {msgdma_tx_mm_read_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {defaultConnection} {false};add_connection {rsp_mux_002.src} {msgdma_tx_mm_read_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_002.src/msgdma_tx_mm_read_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_mm_write_translator.avalon_universal_master_0} {msgdma_rx_mm_write_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {defaultConnection} {false};add_connection {rsp_mux_003.src} {msgdma_rx_mm_write_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_003.src/msgdma_rx_mm_write_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_004.src} {msgdma_tx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_004.src/msgdma_tx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_005.src} {msgdma_rx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_005.src/msgdma_rx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_006.src} {msgdma_tx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_006.src/msgdma_tx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_007.src} {msgdma_rx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_007.src/msgdma_rx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {ddr3_ram_avl_agent.m0} {ddr3_ram_avl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ddr3_ram_avl_agent.rf_source} {ddr3_ram_avl_agent_rsp_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rsp_fifo.out} {ddr3_ram_avl_agent.rf_sink} {avalon_streaming};add_connection {ddr3_ram_avl_agent.rdata_fifo_src} {ddr3_ram_avl_agent_rdata_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rdata_fifo.out} {ddr3_ram_avl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {ddr3_ram_avl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/ddr3_ram_avl_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_csr_agent.m0} {ext_flash_avl_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_csr_agent.rf_source} {ext_flash_avl_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rsp_fifo.out} {ext_flash_avl_csr_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_csr_agent.rdata_fifo_src} {ext_flash_avl_csr_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rdata_fifo.out} {ext_flash_avl_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {ext_flash_avl_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/ext_flash_avl_csr_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_mem_agent.m0} {ext_flash_avl_mem_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_mem_agent.rf_source} {ext_flash_avl_mem_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rsp_fifo.out} {ext_flash_avl_mem_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_mem_agent.rdata_fifo_src} {ext_flash_avl_mem_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rdata_fifo.out} {ext_flash_avl_mem_agent.rdata_fifo_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.m0} {eth_tse_control_port_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {eth_tse_control_port_agent.rf_source} {eth_tse_control_port_agent_rsp_fifo.in} {avalon_streaming};add_connection {eth_tse_control_port_agent_rsp_fifo.out} {eth_tse_control_port_agent.rf_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.rdata_fifo_src} {eth_tse_control_port_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {eth_tse_control_port_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/eth_tse_control_port_agent.cp} {qsys_mm.command};add_connection {sysid_control_slave_agent.m0} {sysid_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_control_slave_agent.rf_source} {sysid_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_control_slave_agent_rsp_fifo.out} {sysid_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_control_slave_agent.rdata_fifo_src} {sysid_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sysid_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sysid_control_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_csr_agent.m0} {msgdma_tx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_csr_agent.rf_source} {msgdma_tx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_csr_agent_rsp_fifo.out} {msgdma_tx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_csr_agent.rdata_fifo_src} {msgdma_tx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {msgdma_tx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/msgdma_tx_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_csr_agent.m0} {msgdma_rx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_csr_agent.rf_source} {msgdma_rx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_csr_agent_rsp_fifo.out} {msgdma_rx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_csr_agent.rdata_fifo_src} {msgdma_rx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {msgdma_rx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/msgdma_rx_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_csr_agent.m0} {onchip_flash_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_csr_agent.rf_source} {onchip_flash_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_csr_agent_rsp_fifo.out} {onchip_flash_csr_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_csr_agent.rdata_fifo_src} {onchip_flash_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_flash_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_flash_csr_agent.cp} {qsys_mm.command};add_connection {udp_generator_csr_agent.m0} {udp_generator_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {udp_generator_csr_agent.rf_source} {udp_generator_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {udp_generator_csr_agent_rsp_fifo.out} {udp_generator_csr_agent.rf_sink} {avalon_streaming};add_connection {udp_generator_csr_agent.rdata_fifo_src} {udp_generator_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {udp_generator_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/udp_generator_csr_agent.cp} {qsys_mm.command};add_connection {sensor_interface_csr_agent.m0} {sensor_interface_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_csr_agent.rf_source} {sensor_interface_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {sensor_interface_csr_agent_rsp_fifo.out} {sensor_interface_csr_agent.rf_sink} {avalon_streaming};add_connection {sensor_interface_csr_agent.rdata_fifo_src} {sensor_interface_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {sensor_interface_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/sensor_interface_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_data_agent.m0} {onchip_flash_data_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_data_agent.rf_source} {onchip_flash_data_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_data_agent_rsp_fifo.out} {onchip_flash_data_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_data_agent.rdata_fifo_src} {onchip_flash_data_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {onchip_flash_data_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/onchip_flash_data_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_prefetcher_csr_agent.m0} {msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_prefetcher_csr_agent.rf_source} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_tx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_tx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {msgdma_tx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/msgdma_tx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_prefetcher_csr_agent.m0} {msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_prefetcher_csr_agent.rf_source} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_rx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_rx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {msgdma_rx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/msgdma_rx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {descriptor_memory_s1_agent.m0} {descriptor_memory_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {descriptor_memory_s1_agent.rf_source} {descriptor_memory_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {descriptor_memory_s1_agent_rsp_fifo.out} {descriptor_memory_s1_agent.rf_sink} {avalon_streaming};add_connection {descriptor_memory_s1_agent.rdata_fifo_src} {descriptor_memory_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {descriptor_memory_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/descriptor_memory_s1_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_015.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_015.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {output_pio_s1_agent.m0} {output_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {output_pio_s1_agent.rf_source} {output_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {output_pio_s1_agent_rsp_fifo.out} {output_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {output_pio_s1_agent.rdata_fifo_src} {output_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_016.src} {output_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_016.src/output_pio_s1_agent.cp} {qsys_mm.command};add_connection {button_pio_s1_agent.m0} {button_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {button_pio_s1_agent.rf_source} {button_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {button_pio_s1_agent_rsp_fifo.out} {button_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {button_pio_s1_agent.rdata_fifo_src} {button_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_017.src} {button_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_017.src/button_pio_s1_agent.cp} {qsys_mm.command};add_connection {debug_uart_s1_agent.m0} {debug_uart_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {debug_uart_s1_agent.rf_source} {debug_uart_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {debug_uart_s1_agent_rsp_fifo.out} {debug_uart_s1_agent.rf_sink} {avalon_streaming};add_connection {debug_uart_s1_agent.rdata_fifo_src} {debug_uart_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_018.src} {debug_uart_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_018.src/debug_uart_s1_agent.cp} {qsys_mm.command};add_connection {frame_timer_s1_agent.m0} {frame_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {frame_timer_s1_agent.rf_source} {frame_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {frame_timer_s1_agent_rsp_fifo.out} {frame_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {frame_timer_s1_agent.rdata_fifo_src} {frame_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_019.src} {frame_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_019.src/frame_timer_s1_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_agent.m0} {calibration_ram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {calibration_ram_s1_agent.rf_source} {calibration_ram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {calibration_ram_s1_agent_rsp_fifo.out} {calibration_ram_s1_agent.rf_sink} {avalon_streaming};add_connection {calibration_ram_s1_agent.rdata_fifo_src} {calibration_ram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {msgdma_tx_mm_read_agent.cp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_mm_read_agent.cp/router_002.sink} {qsys_mm.command};add_connection {router_002.src} {cmd_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/cmd_demux_002.sink} {qsys_mm.command};add_connection {msgdma_rx_mm_write_agent.cp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_mm_write_agent.cp/router_003.sink} {qsys_mm.command};add_connection {router_003.src} {cmd_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/cmd_demux_003.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_read_master_agent.cp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_read_master_agent.cp/router_004.sink} {qsys_mm.command};add_connection {router_004.src} {cmd_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/cmd_demux_004.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_read_master_agent.cp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_read_master_agent.cp/router_005.sink} {qsys_mm.command};add_connection {router_005.src} {cmd_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/cmd_demux_005.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_write_master_agent.cp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_write_master_agent.cp/router_006.sink} {qsys_mm.command};add_connection {router_006.src} {cmd_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/cmd_demux_006.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_write_master_agent.cp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_write_master_agent.cp/router_007.sink} {qsys_mm.command};add_connection {router_007.src} {cmd_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/cmd_demux_007.sink} {qsys_mm.command};add_connection {ddr3_ram_avl_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {ddr3_ram_avl_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux.sink} {qsys_mm.response};add_connection {ext_flash_avl_csr_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_csr_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {ext_flash_avl_mem_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {eth_tse_control_port_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {eth_tse_control_port_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sysid_control_slave_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sysid_control_slave_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {msgdma_tx_csr_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_csr_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {msgdma_rx_csr_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_csr_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_flash_csr_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_csr_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {udp_generator_csr_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {udp_generator_csr_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {sensor_interface_csr_agent.rp} {router_017.sink} {avalon_streaming};preview_set_connection_tag {sensor_interface_csr_agent.rp/router_017.sink} {qsys_mm.response};add_connection {router_017.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_017.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {onchip_flash_data_agent.rp} {router_018.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_data_agent.rp/router_018.sink} {qsys_mm.response};add_connection {router_018.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_018.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_019.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_019.sink} {qsys_mm.response};add_connection {router_019.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_019.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {msgdma_tx_prefetcher_csr_agent.rp} {router_020.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_prefetcher_csr_agent.rp/router_020.sink} {qsys_mm.response};add_connection {router_020.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_020.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {msgdma_rx_prefetcher_csr_agent.rp} {router_021.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_prefetcher_csr_agent.rp/router_021.sink} {qsys_mm.response};add_connection {router_021.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_021.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {descriptor_memory_s1_agent.rp} {router_022.sink} {avalon_streaming};preview_set_connection_tag {descriptor_memory_s1_agent.rp/router_022.sink} {qsys_mm.response};add_connection {router_022.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_022.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_023.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_023.sink} {qsys_mm.response};add_connection {router_023.src} {rsp_demux_015.sink} {avalon_streaming};preview_set_connection_tag {router_023.src/rsp_demux_015.sink} {qsys_mm.response};add_connection {output_pio_s1_agent.rp} {router_024.sink} {avalon_streaming};preview_set_connection_tag {output_pio_s1_agent.rp/router_024.sink} {qsys_mm.response};add_connection {router_024.src} {rsp_demux_016.sink} {avalon_streaming};preview_set_connection_tag {router_024.src/rsp_demux_016.sink} {qsys_mm.response};add_connection {button_pio_s1_agent.rp} {router_025.sink} {avalon_streaming};preview_set_connection_tag {button_pio_s1_agent.rp/router_025.sink} {qsys_mm.response};add_connection {router_025.src} {rsp_demux_017.sink} {avalon_streaming};preview_set_connection_tag {router_025.src/rsp_demux_017.sink} {qsys_mm.response};add_connection {debug_uart_s1_agent.rp} {router_026.sink} {avalon_streaming};preview_set_connection_tag {debug_uart_s1_agent.rp/router_026.sink} {qsys_mm.response};add_connection {router_026.src} {rsp_demux_018.sink} {avalon_streaming};preview_set_connection_tag {router_026.src/rsp_demux_018.sink} {qsys_mm.response};add_connection {frame_timer_s1_agent.rp} {router_027.sink} {avalon_streaming};preview_set_connection_tag {frame_timer_s1_agent.rp/router_027.sink} {qsys_mm.response};add_connection {router_027.src} {rsp_demux_019.sink} {avalon_streaming};preview_set_connection_tag {router_027.src/rsp_demux_019.sink} {qsys_mm.response};add_connection {calibration_ram_s1_agent.rp} {router_028.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_agent.rp/router_028.sink} {qsys_mm.response};add_connection {router.src} {cpu_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/cpu_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {cpu_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_data_master_limiter.rsp_src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.rsp_src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {cpu_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cpu_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {cpu_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_instruction_master_limiter.rsp_src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.rsp_src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_mux_002.src} {ext_flash_avl_mem_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/ext_flash_avl_mem_burst_adapter.sink0} {qsys_mm.command};add_connection {ext_flash_avl_mem_burst_adapter.source0} {ext_flash_avl_mem_agent.cp} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_burst_adapter.source0/ext_flash_avl_mem_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_burst_adapter.source0} {calibration_ram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_burst_adapter.source0/calibration_ram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/cmd_mux_014.sink0} {qsys_mm.command};add_connection {cmd_demux.src15} {cmd_mux_015.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src15/cmd_mux_015.sink0} {qsys_mm.command};add_connection {cmd_demux.src16} {cmd_mux_016.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src16/cmd_mux_016.sink0} {qsys_mm.command};add_connection {cmd_demux.src17} {cmd_mux_017.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src17/cmd_mux_017.sink0} {qsys_mm.command};add_connection {cmd_demux.src18} {cmd_mux_018.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src18/cmd_mux_018.sink0} {qsys_mm.command};add_connection {cmd_demux.src19} {cmd_mux_019.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src19/cmd_mux_019.sink0} {qsys_mm.command};add_connection {cmd_demux.src20} {cmd_mux_020.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src20/cmd_mux_020.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {cmd_mux_010.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/cmd_mux_010.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src3} {cmd_mux_011.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src3/cmd_mux_011.sink1} {qsys_mm.command};add_connection {cmd_demux_004.src0} {cmd_mux_014.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_004.src0/cmd_mux_014.sink1} {qsys_mm.command};add_connection {cmd_demux_005.src0} {cmd_mux_014.sink2} {avalon_streaming};preview_set_connection_tag {cmd_demux_005.src0/cmd_mux_014.sink2} {qsys_mm.command};add_connection {cmd_demux_006.src0} {cmd_mux_014.sink3} {avalon_streaming};preview_set_connection_tag {cmd_demux_006.src0/cmd_mux_014.sink3} {qsys_mm.command};add_connection {cmd_demux_007.src0} {cmd_mux_014.sink4} {avalon_streaming};preview_set_connection_tag {cmd_demux_007.src0/cmd_mux_014.sink4} {qsys_mm.command};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_010.src1} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src1/rsp_mux_001.sink2} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_011.src1} {rsp_mux_001.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src1/rsp_mux_001.sink3} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {rsp_demux_014.src0} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/rsp_mux.sink14} {qsys_mm.response};add_connection {rsp_demux_014.src1} {rsp_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src1/rsp_mux_004.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src2} {rsp_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src2/rsp_mux_005.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src3} {rsp_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src3/rsp_mux_006.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src4} {rsp_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src4/rsp_mux_007.sink0} {qsys_mm.response};add_connection {rsp_demux_015.src0} {rsp_mux.sink15} {avalon_streaming};preview_set_connection_tag {rsp_demux_015.src0/rsp_mux.sink15} {qsys_mm.response};add_connection {rsp_demux_016.src0} {rsp_mux.sink16} {avalon_streaming};preview_set_connection_tag {rsp_demux_016.src0/rsp_mux.sink16} {qsys_mm.response};add_connection {rsp_demux_017.src0} {rsp_mux.sink17} {avalon_streaming};preview_set_connection_tag {rsp_demux_017.src0/rsp_mux.sink17} {qsys_mm.response};add_connection {rsp_demux_018.src0} {rsp_mux.sink18} {avalon_streaming};preview_set_connection_tag {rsp_demux_018.src0/rsp_mux.sink18} {qsys_mm.response};add_connection {rsp_demux_019.src0} {rsp_mux.sink19} {avalon_streaming};preview_set_connection_tag {rsp_demux_019.src0/rsp_mux.sink19} {qsys_mm.response};add_connection {rsp_demux_020.src0} {rsp_mux.sink20} {avalon_streaming};preview_set_connection_tag {rsp_demux_020.src0/rsp_mux.sink20} {qsys_mm.response};add_connection {router_028.src} {calibration_ram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_028.src/calibration_ram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {calibration_ram_s1_rsp_width_adapter.src} {rsp_demux_020.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_rsp_width_adapter.src/rsp_demux_020.sink} {qsys_mm.response};add_connection {cmd_mux_020.src} {calibration_ram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_020.src/calibration_ram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {calibration_ram_s1_cmd_width_adapter.src} {calibration_ram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_cmd_width_adapter.src/calibration_ram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {cmd_demux.src0} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/crosser_002.in} {qsys_mm.command};add_connection {crosser_002.out} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_002.out/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/crosser_003.in} {qsys_mm.command};add_connection {crosser_003.out} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_003.out/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {crosser_004.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/crosser_004.in} {qsys_mm.command};add_connection {crosser_004.out} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {crosser_004.out/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_002.src0} {crosser_005.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_002.src0/crosser_005.in} {qsys_mm.command};add_connection {crosser_005.out} {cmd_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_005.out/cmd_mux.sink2} {qsys_mm.command};add_connection {cmd_demux_003.src0} {crosser_006.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_003.src0/crosser_006.in} {qsys_mm.command};add_connection {crosser_006.out} {cmd_mux.sink3} {avalon_streaming};preview_set_connection_tag {crosser_006.out/cmd_mux.sink3} {qsys_mm.command};add_connection {rsp_demux.src0} {crosser_007.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/crosser_007.in} {qsys_mm.response};add_connection {crosser_007.out} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser_007.out/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {crosser_008.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/crosser_008.in} {qsys_mm.response};add_connection {crosser_008.out} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_008.out/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux.src2} {crosser_009.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src2/crosser_009.in} {qsys_mm.response};add_connection {crosser_009.out} {rsp_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_009.out/rsp_mux_002.sink0} {qsys_mm.response};add_connection {rsp_demux.src3} {crosser_010.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src3/crosser_010.in} {qsys_mm.response};add_connection {crosser_010.out} {rsp_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {crosser_010.out/rsp_mux_003.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {crosser_011.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/crosser_011.in} {qsys_mm.response};add_connection {crosser_011.out} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_011.out/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {crosser_012.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/crosser_012.in} {qsys_mm.response};add_connection {crosser_012.out} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_012.out/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {crosser_013.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/crosser_013.in} {qsys_mm.response};add_connection {crosser_013.out} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {crosser_013.out/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {cpu_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_021.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_025.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_026.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_027.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_028.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_burst_adapter.cr0_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_004.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_005.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_006.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_007.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_008.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_009.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_010.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_011.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_012.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_013.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_burst_adapter.cr0_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_004.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_011.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_012.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_013.in_clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_022.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_023.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_024.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_016.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_016.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_translator.reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rsp_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rdata_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_005.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_006.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_007.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_008.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_009.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_010.in_clk_reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_021.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_022.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_023.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_024.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_025.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_026.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_027.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_028.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_burst_adapter.cr0} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_rsp_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_cmd_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_004.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_005.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_006.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_007.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_008.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_009.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_010.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_011.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_012.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_013.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_reset_connection_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rsp_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rdata_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_005.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_006.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_007.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_008.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_009.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_010.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_soft_reset_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator_reset_reset_bridge.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_burst_adapter.cr0} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_004.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_011.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_012.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_013.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_reset_reset_bridge.clk} {clock};add_interface {ddr3_ram_afi_clk} {clock} {slave};set_interface_property {ddr3_ram_afi_clk} {EXPORT_OF} {ddr3_ram_afi_clk_clock_bridge.in_clk};add_interface {ext_flash_clock_bridge_out_clk} {clock} {slave};set_interface_property {ext_flash_clock_bridge_out_clk} {EXPORT_OF} {ext_flash_clock_bridge_out_clk_clock_bridge.in_clk};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_avl_translator_reset_reset_bridge.in_reset};add_interface {ddr3_ram_soft_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_soft_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_soft_reset_reset_bridge.in_reset};add_interface {eth_tse_reset_connection_reset_bridge_in_reset} {reset} {slave};set_interface_property {eth_tse_reset_connection_reset_bridge_in_reset} {EXPORT_OF} {eth_tse_reset_connection_reset_bridge.in_reset};add_interface {ext_flash_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ext_flash_reset_reset_bridge_in_reset} {EXPORT_OF} {ext_flash_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_read_master} {EXPORT_OF} {msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_write_master} {EXPORT_OF} {msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_mm_write} {avalon} {slave};set_interface_property {msgdma_rx_mm_write} {EXPORT_OF} {msgdma_rx_mm_write_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_read_master} {EXPORT_OF} {msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_write_master} {EXPORT_OF} {msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_mm_read} {avalon} {slave};set_interface_property {msgdma_tx_mm_read} {EXPORT_OF} {msgdma_tx_mm_read_translator.avalon_anti_master_0};add_interface {button_pio_s1} {avalon} {master};set_interface_property {button_pio_s1} {EXPORT_OF} {button_pio_s1_translator.avalon_anti_slave_0};add_interface {calibration_ram_s1} {avalon} {master};set_interface_property {calibration_ram_s1} {EXPORT_OF} {calibration_ram_s1_translator.avalon_anti_slave_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {ddr3_ram_avl} {avalon} {master};set_interface_property {ddr3_ram_avl} {EXPORT_OF} {ddr3_ram_avl_translator.avalon_anti_slave_0};add_interface {debug_uart_s1} {avalon} {master};set_interface_property {debug_uart_s1} {EXPORT_OF} {debug_uart_s1_translator.avalon_anti_slave_0};add_interface {descriptor_memory_s1} {avalon} {master};set_interface_property {descriptor_memory_s1} {EXPORT_OF} {descriptor_memory_s1_translator.avalon_anti_slave_0};add_interface {eth_tse_control_port} {avalon} {master};set_interface_property {eth_tse_control_port} {EXPORT_OF} {eth_tse_control_port_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_csr} {avalon} {master};set_interface_property {ext_flash_avl_csr} {EXPORT_OF} {ext_flash_avl_csr_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_mem} {avalon} {master};set_interface_property {ext_flash_avl_mem} {EXPORT_OF} {ext_flash_avl_mem_translator.avalon_anti_slave_0};add_interface {frame_timer_s1} {avalon} {master};set_interface_property {frame_timer_s1} {EXPORT_OF} {frame_timer_s1_translator.avalon_anti_slave_0};add_interface {msgdma_rx_csr} {avalon} {master};set_interface_property {msgdma_rx_csr} {EXPORT_OF} {msgdma_rx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_rx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_rx_prefetcher_csr} {EXPORT_OF} {msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_csr} {avalon} {master};set_interface_property {msgdma_tx_csr} {EXPORT_OF} {msgdma_tx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_tx_prefetcher_csr} {EXPORT_OF} {msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_csr} {avalon} {master};set_interface_property {onchip_flash_csr} {EXPORT_OF} {onchip_flash_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_data} {avalon} {master};set_interface_property {onchip_flash_data} {EXPORT_OF} {onchip_flash_data_translator.avalon_anti_slave_0};add_interface {output_pio_s1} {avalon} {master};set_interface_property {output_pio_s1} {EXPORT_OF} {output_pio_s1_translator.avalon_anti_slave_0};add_interface {sensor_interface_csr} {avalon} {master};set_interface_property {sensor_interface_csr} {EXPORT_OF} {sensor_interface_csr_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};add_interface {sysid_control_slave} {avalon} {master};set_interface_property {sysid_control_slave} {EXPORT_OF} {sysid_control_slave_translator.avalon_anti_slave_0};add_interface {udp_generator_csr} {avalon} {master};set_interface_property {udp_generator_csr} {EXPORT_OF} {udp_generator_csr_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.button_pio.s1} {0};set_module_assignment {interconnect_id.calibration_ram.s1} {1};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {2};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.ddr3_ram.avl} {3};set_module_assignment {interconnect_id.debug_uart.s1} {4};set_module_assignment {interconnect_id.descriptor_memory.s1} {5};set_module_assignment {interconnect_id.eth_tse.control_port} {6};set_module_assignment {interconnect_id.ext_flash.avl_csr} {7};set_module_assignment {interconnect_id.ext_flash.avl_mem} {8};set_module_assignment {interconnect_id.frame_timer.s1} {9};set_module_assignment {interconnect_id.msgdma_rx.csr} {10};set_module_assignment {interconnect_id.msgdma_rx.descriptor_read_master} {2};set_module_assignment {interconnect_id.msgdma_rx.descriptor_write_master} {3};set_module_assignment {interconnect_id.msgdma_rx.mm_write} {4};set_module_assignment {interconnect_id.msgdma_rx.prefetcher_csr} {11};set_module_assignment {interconnect_id.msgdma_tx.csr} {12};set_module_assignment {interconnect_id.msgdma_tx.descriptor_read_master} {5};set_module_assignment {interconnect_id.msgdma_tx.descriptor_write_master} {6};set_module_assignment {interconnect_id.msgdma_tx.mm_read} {7};set_module_assignment {interconnect_id.msgdma_tx.prefetcher_csr} {13};set_module_assignment {interconnect_id.onchip_flash.csr} {14};set_module_assignment {interconnect_id.onchip_flash.data} {15};set_module_assignment {interconnect_id.output_pio.s1} {16};set_module_assignment {interconnect_id.sensor_interface.csr} {17};set_module_assignment {interconnect_id.sys_clk_timer.s1} {18};set_module_assignment {interconnect_id.sysid.control_slave} {19};set_module_assignment {interconnect_id.udp_generator.csr} {20};]]></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="ddr3_ram_afi_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ddr3_ram_afi_clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface
+     name="ext_flash_clock_bridge_out_clk"
+     kind="clock_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_flash_clock_bridge_out_clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="sys_clk_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sys_clk_clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface
+     name="cpu_reset_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>cpu_reset_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface
+     name="ddr3_ram_avl_translator_reset_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ddr3_ram_afi_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface
+     name="ddr3_ram_soft_reset_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ddr3_ram_afi_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ddr3_ram_soft_reset_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface
+     name="eth_tse_reset_connection_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>eth_tse_reset_connection_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface
+     name="ext_flash_reset_reset_bridge_in_reset"
+     kind="reset_sink"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ext_flash_clock_bridge_out_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_flash_reset_reset_bridge_in_reset_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="cpu_data_master" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>64</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>cpu_data_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>cpu_data_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>cpu_data_master_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>cpu_data_master_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cpu_data_master_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>cpu_data_master_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>cpu_data_master_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>cpu_data_master_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>cpu_data_master_debugaccess</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+  </interface>
+  <interface name="cpu_instruction_master" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>64</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>cpu_instruction_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>cpu_instruction_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>cpu_instruction_master_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cpu_instruction_master_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>cpu_instruction_master_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface
+     name="msgdma_rx_descriptor_read_master"
+     kind="avalon_slave"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>64</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_rx_descriptor_read_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_read_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_read_master_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_read_master_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_read_master_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface
+     name="msgdma_rx_descriptor_write_master"
+     kind="avalon_slave"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_response</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>msgdma_rx_descriptor_write_master_writeresponsevalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+  </interface>
+  <interface name="msgdma_rx_mm_write" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>268435456</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_rx_mm_write_address</name>
+    <direction>Input</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_rx_mm_write_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_rx_mm_write_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>msgdma_rx_mm_write_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_rx_mm_write_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+  </interface>
+  <interface
+     name="msgdma_tx_descriptor_read_master"
+     kind="avalon_slave"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>64</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_tx_descriptor_read_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_read_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_read_master_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_read_master_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_read_master_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface
+     name="msgdma_tx_descriptor_write_master"
+     kind="avalon_slave"
+     version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>536870912</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_address</name>
+    <direction>Input</direction>
+    <width>29</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_response</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>response</role>
+   </port>
+   <port>
+    <name>msgdma_tx_descriptor_write_master_writeresponsevalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>writeresponsevalid</role>
+   </port>
+  </interface>
+  <interface name="msgdma_tx_mm_read" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>merlin.flow.avalon_universal_master_0</name>
+    <value>avalon_universal_master_0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>268435456</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>64</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>msgdma_tx_mm_read_address</name>
+    <direction>Input</direction>
+    <width>28</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_tx_mm_read_waitrequest</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>msgdma_tx_mm_read_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>msgdma_tx_mm_read_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_tx_mm_read_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_mm_read_readdatavalid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+  </interface>
+  <interface name="button_pio_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>button_pio_s1_address</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>button_pio_s1_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>button_pio</moduleName>
+    <slaveName>s1</slaveName>
+    <name>button_pio.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>16</span>
+   </memoryBlock>
+  </interface>
+  <interface name="calibration_ram_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>calibration_ram_s1_address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_readdata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_writedata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_byteenable</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>calibration_ram_s1_clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>calibration_ram</moduleName>
+    <slaveName>s1</slaveName>
+    <name>calibration_ram.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>640</span>
+   </memoryBlock>
+  </interface>
+  <interface name="cpu_debug_mem_slave" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>cpu_debug_mem_slave_address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <port>
+    <name>cpu_debug_mem_slave_debugaccess</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>debugaccess</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>cpu</moduleName>
+    <slaveName>debug_mem_slave</slaveName>
+    <name>cpu.debug_mem_slave</name>
+    <baseAddress>0</baseAddress>
+    <span>2048</span>
+   </memoryBlock>
+  </interface>
+  <interface name="ddr3_ram_avl" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ddr3_ram_afi_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>ddr3_ram_avl_translator_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>ddr3_ram_avl_address</name>
+    <direction>Output</direction>
+    <width>25</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_beginbursttransfer</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>beginbursttransfer</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_burstcount</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>burstcount</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>ddr3_ram_avl_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ddr3_ram</moduleName>
+    <slaveName>avl</slaveName>
+    <name>ddr3_ram.avl</name>
+    <baseAddress>0</baseAddress>
+    <span>134217728</span>
+   </memoryBlock>
+  </interface>
+  <interface name="debug_uart_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>debug_uart_s1_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_readdata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_writedata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_begintransfer</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>begintransfer</role>
+   </port>
+   <port>
+    <name>debug_uart_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>s1</slaveName>
+    <name>debug_uart.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="descriptor_memory_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>eth_tse_reset_connection_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>descriptor_memory_s1_address</name>
+    <direction>Output</direction>
+    <width>11</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>descriptor_memory_s1_clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>descriptor_memory</moduleName>
+    <slaveName>s1</slaveName>
+    <name>descriptor_memory.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>8192</span>
+   </memoryBlock>
+  </interface>
+  <interface name="eth_tse_control_port" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>eth_tse_reset_connection_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>eth_tse_control_port_address</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>eth_tse_control_port_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>eth_tse_control_port_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>eth_tse_control_port_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>eth_tse_control_port_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>eth_tse_control_port_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>eth_tse</moduleName>
+    <slaveName>control_port</slaveName>
+    <name>eth_tse.control_port</name>
+    <baseAddress>0</baseAddress>
+    <span>1024</span>
+   </memoryBlock>
+  </interface>
+  <interface name="ext_flash_avl_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ext_flash_clock_bridge_out_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>ext_flash_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>ext_flash_avl_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_csr_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>avl_csr</slaveName>
+    <name>ext_flash.avl_csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="ext_flash_avl_mem" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>ext_flash_clock_bridge_out_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>ext_flash_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>ext_flash_avl_mem_address</name>
+    <direction>Output</direction>
+    <width>24</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_burstcount</name>
+    <direction>Output</direction>
+    <width>7</width>
+    <role>burstcount</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>ext_flash_avl_mem_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>avl_mem</slaveName>
+    <name>ext_flash.avl_mem</name>
+    <baseAddress>0</baseAddress>
+    <span>67108864</span>
+   </memoryBlock>
+  </interface>
+  <interface name="frame_timer_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>frame_timer_s1_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>frame_timer_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>frame_timer_s1_readdata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>frame_timer_s1_writedata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>frame_timer_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>frame_timer</moduleName>
+    <slaveName>s1</slaveName>
+    <name>frame_timer.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="msgdma_rx_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>msgdma_rx_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_rx_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_rx_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_rx_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_rx_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>msgdma_rx_csr_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>csr</slaveName>
+    <name>msgdma_rx.csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="msgdma_rx_prefetcher_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>msgdma_rx_prefetcher_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_rx_prefetcher_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_rx_prefetcher_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_rx_prefetcher_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_rx_prefetcher_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>prefetcher_csr</slaveName>
+    <name>msgdma_rx.prefetcher_csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="msgdma_tx_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>msgdma_tx_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_tx_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_tx_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_tx_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_csr_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>csr</slaveName>
+    <name>msgdma_tx.csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="msgdma_tx_prefetcher_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>msgdma_tx_prefetcher_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>msgdma_tx_prefetcher_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>msgdma_tx_prefetcher_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>msgdma_tx_prefetcher_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>msgdma_tx_prefetcher_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>prefetcher_csr</slaveName>
+    <name>msgdma_tx.prefetcher_csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="onchip_flash_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>onchip_flash_csr_address</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>onchip_flash_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>onchip_flash_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>onchip_flash_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>onchip_flash_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>csr</slaveName>
+    <name>onchip_flash.csr</name>
+    <baseAddress>0</baseAddress>
+    <span>8</span>
+   </memoryBlock>
+  </interface>
+  <interface name="onchip_flash_data" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>onchip_flash_data_address</name>
+    <direction>Output</direction>
+    <width>19</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_burstcount</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>burstcount</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_readdatavalid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>readdatavalid</role>
+   </port>
+   <port>
+    <name>onchip_flash_data_waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>onchip_flash</moduleName>
+    <slaveName>data</slaveName>
+    <name>onchip_flash.data</name>
+    <baseAddress>0</baseAddress>
+    <span>1441792</span>
+   </memoryBlock>
+  </interface>
+  <interface name="output_pio_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>eth_tse_reset_connection_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>output_pio_s1_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>output_pio_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>output_pio_s1_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>output_pio_s1_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>output_pio_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>output_pio</moduleName>
+    <slaveName>s1</slaveName>
+    <name>output_pio.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="sensor_interface_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>sensor_interface_csr_address</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>sensor_interface_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>sensor_interface_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>sensor_interface_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>sensor_interface_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>sensor_interface_csr_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sensor_interface</moduleName>
+    <slaveName>csr</slaveName>
+    <name>sensor_interface.csr</name>
+    <baseAddress>0</baseAddress>
+    <span>16</span>
+   </memoryBlock>
+  </interface>
+  <interface name="sys_clk_timer_s1" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>eth_tse_reset_connection_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>sys_clk_timer_s1_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>sys_clk_timer_s1_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>sys_clk_timer_s1_readdata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>sys_clk_timer_s1_writedata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>sys_clk_timer_s1_chipselect</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>s1</slaveName>
+    <name>sys_clk_timer.s1</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+  <interface name="sysid_control_slave" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>eth_tse_reset_connection_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>sysid_control_slave_address</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>sysid_control_slave_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>sysid</moduleName>
+    <slaveName>control_slave</slaveName>
+    <name>sysid.control_slave</name>
+    <baseAddress>0</baseAddress>
+    <span>8</span>
+   </memoryBlock>
+  </interface>
+  <interface name="udp_generator_csr" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sys_clk_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>cpu_reset_reset_bridge_in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>udp_generator_csr_address</name>
+    <direction>Output</direction>
+    <width>3</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>udp_generator_csr_write</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>udp_generator_csr_read</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>udp_generator_csr_readdata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>udp_generator_csr_writedata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>udp_generator_csr_byteenable</name>
+    <direction>Output</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+   <memoryBlock>
+    <isBridge>false</isBridge>
+    <moduleName>udp_generator</moduleName>
+    <slaveName>csr</slaveName>
+    <name>udp_generator.csr</name>
+    <baseAddress>0</baseAddress>
+    <span>32</span>
+   </memoryBlock>
+  </interface>
+ </module>
+ <module
+   name="irq_mapper"
+   kind="altera_irq_mapper"
+   version="19.1"
+   path="irq_mapper">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RCVRS">
+   <type>int</type>
+   <value>5</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SENDER_IRQ_WIDTH">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="IRQ_MAP">
+   <type>java.lang.String</type>
+   <value>0:2,1:3,2:5,3:0,4:4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="clk_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="receiver0" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver0_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_tx</moduleName>
+    <slaveName>csr_irq</slaveName>
+    <name>msgdma_tx.csr_irq</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="receiver1" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver1_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>msgdma_rx</moduleName>
+    <slaveName>csr_irq</slaveName>
+    <name>msgdma_rx.csr_irq</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="receiver2" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver2_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>irq_synchronizer</moduleName>
+    <slaveName>sender</slaveName>
+    <name>irq_synchronizer.sender</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="receiver3" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver3_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>sys_clk_timer</moduleName>
+    <slaveName>irq</slaveName>
+    <name>sys_clk_timer.irq</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="receiver4" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver4_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>debug_uart</moduleName>
+    <slaveName>irq</slaveName>
+    <name>debug_uart.irq</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="sender" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sender_irq</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="irq_synchronizer"
+   kind="altera_irq_clock_crosser"
+   version="19.1"
+   path="irq_synchronizer">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="IRQ_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_RECEIVER_INTERRUPTS_USED">
+   <type>java.math.BigInteger</type>
+   <value>-1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>INTERRUPTS_USED</sysinfo_type>
+   <sysinfo_arg>receiver</sysinfo_arg>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="receiver_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>receiver_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="sender_clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sender_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="receiver_clk_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>receiver_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>receiver_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sender_clk_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sender_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sender_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="receiver" kind="interrupt_receiver" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>receiver_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>receiver_clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqMap">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>true</isStart>
+   <port>
+    <name>receiver_irq</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+   <interrupt>
+    <isBridge>false</isBridge>
+    <moduleName>ext_flash</moduleName>
+    <slaveName>interrupt_sender</slaveName>
+    <name>ext_flash.interrupt_sender</name>
+    <interruptNumber>0</interruptNumber>
+   </interrupt>
+  </interface>
+  <interface name="sender" kind="interrupt_sender" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedAddressablePoint">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>sender_clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>sender_clk_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedReceiverOffset">
+    <type>java.lang.Integer</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToReceiver">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="irqScheme">
+    <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
+    <value>INDIVIDUAL_REQUESTS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>interrupt</type>
+   <isStart>false</isStart>
+   <port>
+    <name>sender_irq</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>irq</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="avalon_st_adapter"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   path="avalon_st_adapter">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="inBitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inDataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inMaxChannel">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inEmptyWidth">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseValid">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseReady">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inReadyLatency">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outDataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outMaxChannel">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outErrorWidth">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseEmptyPort">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outEmptyWidth">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseValid">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseReady">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outReadyLatency">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_clk_0" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk_0_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="in_rst_0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_rst_0_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="in_0" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>in_rst_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_0_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in_0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in_0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in_0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in_0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in_0_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+  </interface>
+  <interface name="out_0" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>in_rst_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_0_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_0_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_0_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_0_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_0_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_0_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_0_error</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="avalon_st_adapter_001"
+   kind="altera_avalon_st_adapter"
+   version="19.1"
+   path="avalon_st_adapter_001">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="inBitsPerSymbol">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUsePackets">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inDataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inMaxChannel">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorWidth">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseEmptyPort">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inEmptyWidth">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseValid">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inUseReady">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="inReadyLatency">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outDataWidth">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outMaxChannel">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outChannelWidth">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outErrorWidth">
+   <type>int</type>
+   <value>6</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outErrorDescriptor">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseEmptyPort">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outEmptyWidth">
+   <type>int</type>
+   <value>2</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseValid">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outUseReady">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="outReadyLatency">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="AUTO_DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE">
+   <type>java.lang.String</type>
+   <value>10M50DAF484C6GES</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="AUTO_DEVICE_SPEEDGRADE">
+   <type>java.lang.String</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX 10</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="in_clk_0" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_clk_0_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="in_rst_0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_rst_0_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="in_0" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>in_rst_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_0_data</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>in_0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in_0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in_0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in_0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in_0_empty</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in_0_error</name>
+    <direction>Input</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+  </interface>
+  <interface name="out_0" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>in_clk_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>in_rst_0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>4</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_0_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>out_0_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out_0_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out_0_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out_0_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out_0_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out_0_error</name>
+    <direction>Output</direction>
+    <width>6</width>
+    <role>error</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_001"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_001">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_translator"
+   kind="altera_reset_translator"
+   version="19.1"
+   path="rst_translator">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="ACTIVE_LOW_RESET">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNCHRONOUS_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_INPUT_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req_in</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+  <interface name="out_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_reset</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_002"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_002">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="reset_in1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in1</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0,reset_in1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_003"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_003">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>none</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="reset_in1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in1</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0,reset_in1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_004"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_004">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="reset_in1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in1</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0,reset_in1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_translator_001"
+   kind="altera_reset_translator"
+   version="19.1"
+   path="rst_translator_001">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="ACTIVE_LOW_RESET">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNCHRONOUS_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_INPUT_ENABLE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="in_reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+   <port>
+    <name>reset_req_in</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset_req</role>
+   </port>
+  </interface>
+  <interface name="out_reset" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>in_reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out_reset</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_005"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_005">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="reset_in1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in1</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0,reset_in1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <module
+   name="rst_controller_006"
+   kind="altera_reset_controller"
+   version="19.1"
+   path="rst_controller_006">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUM_RESET_INPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="OUTPUT_RESET_SYNC_EDGES">
+   <type>java.lang.String</type>
+   <value>deassert</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="SYNC_DEPTH">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQUEST_PRESENT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_WAIT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MIN_RST_ASSERTION_TIME">
+   <type>int</type>
+   <value>3</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="RESET_REQ_EARLY_DSRT_TIME">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN0">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN1">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN2">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN3">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN4">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN5">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN6">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN7">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN8">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN9">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN10">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN11">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN12">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN13">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN14">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_IN15">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_RESET_REQUEST_INPUT">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ADAPT_RESET_REQUEST">
+   <type>int</type>
+   <value>0</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="reset_in0" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in0</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="reset_in1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>NONE</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset_in1</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset_out" kind="reset_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedDirectReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedResetSinks">
+    <type>[Ljava.lang.String;</type>
+    <value>reset_in0,reset_in1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>true</isStart>
+   <port>
+    <name>reset_out</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <connection
+   name="sensor_interface.data_out/udp_generator.data_in"
+   kind="avalon_streaming"
+   version="19.1"
+   start="sensor_interface.data_out"
+   end="udp_generator.data_in">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sensor_interface</startModule>
+  <startConnectionPoint>data_out</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>data_in</endConnectionPoint>
+ </connection>
+ <connection
+   name="tx_multiplexer.out/channel_adapter_0.in"
+   kind="avalon_streaming"
+   version="19.1"
+   start="tx_multiplexer.out"
+   end="channel_adapter_0.in">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>tx_multiplexer</startModule>
+  <startConnectionPoint>out</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>in</endConnectionPoint>
+ </connection>
+ <connection
+   name="channel_adapter_0.out/eth_tse.transmit"
+   kind="avalon_streaming"
+   version="19.1"
+   start="channel_adapter_0.out"
+   end="eth_tse.transmit">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>channel_adapter_0</startModule>
+  <startConnectionPoint>out</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>transmit</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.st_source/tx_multiplexer.in0"
+   kind="avalon_streaming"
+   version="19.1"
+   start="msgdma_tx.st_source"
+   end="tx_multiplexer.in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>st_source</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sysid.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sysid.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sys_clk_timer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sys_clk_timer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/cpu.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="cpu.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/output_pio.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="output_pio.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/button_pio.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="button_pio.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/debug_uart.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="debug_uart.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/onchip_flash.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="onchip_flash.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/tx_multiplexer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="tx_multiplexer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/channel_adapter_0.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="channel_adapter_0.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/udp_generator.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="udp_generator.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/frame_timer.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="frame_timer.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/sensor_interface.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sensor_interface.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/descriptor_memory.clk1"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="descriptor_memory.clk1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>clk1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/calibration_ram.clk1"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>clk1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/calibration_ram.clk2"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="calibration_ram.clk2">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>clk2</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/msgdma_tx.clock"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="msgdma_tx.clock">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>clock</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/msgdma_rx.clock"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="msgdma_rx.clock">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>clock</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.control_port_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.control_port_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>control_port_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/enet_pll.inclk_interface"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="enet_pll.inclk_interface">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>enet_pll</endModule>
+  <endConnectionPoint>inclk_interface</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/altpll_shift.inclk_interface"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="altpll_shift.inclk_interface">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>altpll_shift</endModule>
+  <endConnectionPoint>inclk_interface</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.receive_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.receive_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>receive_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/eth_tse.transmit_clock_connection"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.transmit_clock_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>transmit_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="ext_flash_clock_bridge.out_clk/ext_flash.clock_sink"
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="ext_flash.clock_sink">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ext_flash_clock_bridge</startModule>
+  <startConnectionPoint>out_clk</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+   name="sensor_interface.calibration_ram_interface/mm_interconnect_0.sensor_interface_calibration_ram_interface"
+   kind="avalon"
+   version="19.1"
+   start="sensor_interface.calibration_ram_interface"
+   end="mm_interconnect_0.sensor_interface_calibration_ram_interface">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sensor_interface</startModule>
+  <startConnectionPoint>calibration_ram_interface</startConnectionPoint>
+  <endModule>mm_interconnect_0</endModule>
+  <endConnectionPoint>sensor_interface_calibration_ram_interface</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/mm_interconnect_0.sys_clk_clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="mm_interconnect_0.sys_clk_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>mm_interconnect_0</endModule>
+  <endConnectionPoint>sys_clk_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_0.calibration_ram_s2/calibration_ram.s2"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_0.calibration_ram_s2"
+   end="calibration_ram.s2">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_0</startModule>
+  <startConnectionPoint>calibration_ram_s2</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>s2</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.data_master/mm_interconnect_1.cpu_data_master"
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="mm_interconnect_1.cpu_data_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>data_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>cpu_data_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/mm_interconnect_1.sys_clk_clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="mm_interconnect_1.sys_clk_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>sys_clk_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.instruction_master/mm_interconnect_1.cpu_instruction_master"
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="mm_interconnect_1.cpu_instruction_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>instruction_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>cpu_instruction_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.mm_read/mm_interconnect_1.msgdma_tx_mm_read"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="mm_interconnect_1.msgdma_tx_mm_read">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>mm_read</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_tx_mm_read</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.mm_write/mm_interconnect_1.msgdma_rx_mm_write"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="mm_interconnect_1.msgdma_rx_mm_write">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>mm_write</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_rx_mm_write</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.descriptor_read_master/mm_interconnect_1.msgdma_tx_descriptor_read_master"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_read_master"
+   end="mm_interconnect_1.msgdma_tx_descriptor_read_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>descriptor_read_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_tx_descriptor_read_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.descriptor_read_master/mm_interconnect_1.msgdma_rx_descriptor_read_master"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_read_master"
+   end="mm_interconnect_1.msgdma_rx_descriptor_read_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>descriptor_read_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_rx_descriptor_read_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_tx.descriptor_write_master/mm_interconnect_1.msgdma_tx_descriptor_write_master"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_write_master"
+   end="mm_interconnect_1.msgdma_tx_descriptor_write_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_tx</startModule>
+  <startConnectionPoint>descriptor_write_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_tx_descriptor_write_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="msgdma_rx.descriptor_write_master/mm_interconnect_1.msgdma_rx_descriptor_write_master"
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_write_master"
+   end="mm_interconnect_1.msgdma_rx_descriptor_write_master">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>msgdma_rx</startModule>
+  <startConnectionPoint>descriptor_write_master</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>msgdma_rx_descriptor_write_master</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.ddr3_ram_avl/ddr3_ram.avl"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.ddr3_ram_avl"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>ddr3_ram_avl</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>avl</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram.afi_clk/mm_interconnect_1.ddr3_ram_afi_clk"
+   kind="clock"
+   version="19.1"
+   start="ddr3_ram.afi_clk"
+   end="mm_interconnect_1.ddr3_ram_afi_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram</startModule>
+  <startConnectionPoint>afi_clk</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>ddr3_ram_afi_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.ext_flash_avl_csr/ext_flash.avl_csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.ext_flash_avl_csr"
+   end="ext_flash.avl_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>ext_flash_avl_csr</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>avl_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="ext_flash_clock_bridge.out_clk/mm_interconnect_1.ext_flash_clock_bridge_out_clk"
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="mm_interconnect_1.ext_flash_clock_bridge_out_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ext_flash_clock_bridge</startModule>
+  <startConnectionPoint>out_clk</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>ext_flash_clock_bridge_out_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.ext_flash_avl_mem/ext_flash.avl_mem"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.ext_flash_avl_mem"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>ext_flash_avl_mem</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>avl_mem</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.eth_tse_control_port/eth_tse.control_port"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.eth_tse_control_port"
+   end="eth_tse.control_port">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>eth_tse_control_port</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>control_port</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.sysid_control_slave/sysid.control_slave"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.sysid_control_slave"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>sysid_control_slave</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>control_slave</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.msgdma_tx_csr/msgdma_tx.csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.msgdma_tx_csr"
+   end="msgdma_tx.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>msgdma_tx_csr</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.msgdma_rx_csr/msgdma_rx.csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.msgdma_rx_csr"
+   end="msgdma_rx.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>msgdma_rx_csr</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.onchip_flash_csr/onchip_flash.csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.onchip_flash_csr"
+   end="onchip_flash.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>onchip_flash_csr</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.udp_generator_csr/udp_generator.csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.udp_generator_csr"
+   end="udp_generator.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>udp_generator_csr</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.sensor_interface_csr/sensor_interface.csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.sensor_interface_csr"
+   end="sensor_interface.csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>sensor_interface_csr</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.onchip_flash_data/onchip_flash.data"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.onchip_flash_data"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>onchip_flash_data</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>data</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.cpu_debug_mem_slave/cpu.debug_mem_slave"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.cpu_debug_mem_slave"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>cpu_debug_mem_slave</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>debug_mem_slave</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.msgdma_tx_prefetcher_csr/msgdma_tx.prefetcher_csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.msgdma_tx_prefetcher_csr"
+   end="msgdma_tx.prefetcher_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>msgdma_tx_prefetcher_csr</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>prefetcher_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.msgdma_rx_prefetcher_csr/msgdma_rx.prefetcher_csr"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.msgdma_rx_prefetcher_csr"
+   end="msgdma_rx.prefetcher_csr">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>msgdma_rx_prefetcher_csr</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>prefetcher_csr</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.descriptor_memory_s1/descriptor_memory.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.descriptor_memory_s1"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>descriptor_memory_s1</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.sys_clk_timer_s1/sys_clk_timer.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.sys_clk_timer_s1"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>sys_clk_timer_s1</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.output_pio_s1/output_pio.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.output_pio_s1"
+   end="output_pio.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>output_pio_s1</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.button_pio_s1/button_pio.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.button_pio_s1"
+   end="button_pio.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>button_pio_s1</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.debug_uart_s1/debug_uart.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.debug_uart_s1"
+   end="debug_uart.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>debug_uart_s1</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.frame_timer_s1/frame_timer.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.frame_timer_s1"
+   end="frame_timer.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>frame_timer_s1</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="mm_interconnect_1.calibration_ram_s1/calibration_ram.s1"
+   kind="avalon"
+   version="19.1"
+   start="mm_interconnect_1.calibration_ram_s1"
+   end="calibration_ram.s1">
+  <parameter name="arbitrationPriority">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="baseAddress">
+   <type>java.math.BigInteger</type>
+   <value>0x0000</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="defaultConnection">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>mm_interconnect_1</startModule>
+  <startConnectionPoint>calibration_ram_s1</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>s1</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_mapper.receiver0/msgdma_tx.csr_irq"
+   kind="interrupt"
+   version="19.1"
+   start="irq_mapper.receiver0"
+   end="msgdma_tx.csr_irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_mapper</startModule>
+  <startConnectionPoint>receiver0</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>csr_irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_mapper.receiver1/msgdma_rx.csr_irq"
+   kind="interrupt"
+   version="19.1"
+   start="irq_mapper.receiver1"
+   end="msgdma_rx.csr_irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_mapper</startModule>
+  <startConnectionPoint>receiver1</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>csr_irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_mapper.receiver3/sys_clk_timer.irq"
+   kind="interrupt"
+   version="19.1"
+   start="irq_mapper.receiver3"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_mapper</startModule>
+  <startConnectionPoint>receiver3</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_mapper.receiver4/debug_uart.irq"
+   kind="interrupt"
+   version="19.1"
+   start="irq_mapper.receiver4"
+   end="debug_uart.irq">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_mapper</startModule>
+  <startConnectionPoint>receiver4</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>irq</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.irq/irq_mapper.sender"
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="irq_mapper.sender">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>irq</startConnectionPoint>
+  <endModule>irq_mapper</endModule>
+  <endConnectionPoint>sender</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/irq_mapper.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="irq_mapper.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>irq_mapper</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_mapper.receiver2/irq_synchronizer.sender"
+   kind="interrupt"
+   version="19.1"
+   start="irq_mapper.receiver2"
+   end="irq_synchronizer.sender">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_mapper</startModule>
+  <startConnectionPoint>receiver2</startConnectionPoint>
+  <endModule>irq_synchronizer</endModule>
+  <endConnectionPoint>sender</endConnectionPoint>
+ </connection>
+ <connection
+   name="irq_synchronizer.receiver/ext_flash.interrupt_sender"
+   kind="interrupt"
+   version="19.1"
+   start="irq_synchronizer.receiver"
+   end="ext_flash.interrupt_sender">
+  <parameter name="irqNumber">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>irq_synchronizer</startModule>
+  <startConnectionPoint>receiver</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ </connection>
+ <connection
+   name="ext_flash_clock_bridge.out_clk/irq_synchronizer.receiver_clk"
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="irq_synchronizer.receiver_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ext_flash_clock_bridge</startModule>
+  <startConnectionPoint>out_clk</startConnectionPoint>
+  <endModule>irq_synchronizer</endModule>
+  <endConnectionPoint>receiver_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/irq_synchronizer.sender_clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="irq_synchronizer.sender_clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>irq_synchronizer</endModule>
+  <endConnectionPoint>sender_clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="udp_generator.data_out/avalon_st_adapter.in_0"
+   kind="avalon_streaming"
+   version="19.1"
+   start="udp_generator.data_out"
+   end="avalon_st_adapter.in_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>udp_generator</startModule>
+  <startConnectionPoint>data_out</startConnectionPoint>
+  <endModule>avalon_st_adapter</endModule>
+  <endConnectionPoint>in_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="avalon_st_adapter.out_0/tx_multiplexer.in1"
+   kind="avalon_streaming"
+   version="19.1"
+   start="avalon_st_adapter.out_0"
+   end="tx_multiplexer.in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>avalon_st_adapter</startModule>
+  <startConnectionPoint>out_0</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/avalon_st_adapter.in_clk_0"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="avalon_st_adapter.in_clk_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>avalon_st_adapter</endModule>
+  <endConnectionPoint>in_clk_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="eth_tse.receive/avalon_st_adapter_001.in_0"
+   kind="avalon_streaming"
+   version="19.1"
+   start="eth_tse.receive"
+   end="avalon_st_adapter_001.in_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>eth_tse</startModule>
+  <startConnectionPoint>receive</startConnectionPoint>
+  <endModule>avalon_st_adapter_001</endModule>
+  <endConnectionPoint>in_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="avalon_st_adapter_001.out_0/msgdma_rx.st_sink"
+   kind="avalon_streaming"
+   version="19.1"
+   start="avalon_st_adapter_001.out_0"
+   end="msgdma_rx.st_sink">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>avalon_st_adapter_001</startModule>
+  <startConnectionPoint>out_0</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>st_sink</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/avalon_st_adapter_001.in_clk_0"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="avalon_st_adapter_001.in_clk_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>avalon_st_adapter_001</endModule>
+  <endConnectionPoint>in_clk_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller.reset_out/altpll_shift.inclk_interface_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller.reset_out"
+   end="altpll_shift.inclk_interface_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>altpll_shift</endModule>
+  <endConnectionPoint>inclk_interface_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller.reset_out/enet_pll.inclk_interface_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller.reset_out"
+   end="enet_pll.inclk_interface_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>enet_pll</endModule>
+  <endConnectionPoint>inclk_interface_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/rst_controller.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="rst_controller.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>rst_controller</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/rst_controller.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="rst_controller.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>rst_controller</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/button_pio.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="button_pio.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>button_pio</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/calibration_ram.reset1"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="calibration_ram.reset1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>reset1</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/calibration_ram.reset2"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="calibration_ram.reset2">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>calibration_ram</endModule>
+  <endConnectionPoint>reset2</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/channel_adapter_0.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="channel_adapter_0.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>channel_adapter_0</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/cpu.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="cpu.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>cpu</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/debug_uart.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="debug_uart.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>debug_uart</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/frame_timer.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="frame_timer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>frame_timer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/msgdma_rx.reset_n"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="msgdma_rx.reset_n">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>msgdma_rx</endModule>
+  <endConnectionPoint>reset_n</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/msgdma_tx.reset_n"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="msgdma_tx.reset_n">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>msgdma_tx</endModule>
+  <endConnectionPoint>reset_n</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/onchip_flash.nreset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="onchip_flash.nreset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>onchip_flash</endModule>
+  <endConnectionPoint>nreset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/sensor_interface.rst"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="sensor_interface.rst">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>sensor_interface</endModule>
+  <endConnectionPoint>rst</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/tx_multiplexer.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="tx_multiplexer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>tx_multiplexer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/udp_generator.rst"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="udp_generator.rst">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>udp_generator</endModule>
+  <endConnectionPoint>rst</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/mm_interconnect_0.sensor_interface_rst_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="mm_interconnect_0.sensor_interface_rst_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>mm_interconnect_0</endModule>
+  <endConnectionPoint>sensor_interface_rst_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/mm_interconnect_1.cpu_reset_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="mm_interconnect_1.cpu_reset_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>cpu_reset_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/irq_mapper.clk_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="irq_mapper.clk_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>irq_mapper</endModule>
+  <endConnectionPoint>clk_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/irq_synchronizer.sender_clk_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="irq_synchronizer.sender_clk_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>irq_synchronizer</endModule>
+  <endConnectionPoint>sender_clk_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_001.reset_out/rst_translator.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_001.reset_out"
+   end="rst_translator.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_001</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator.out_reset/avalon_st_adapter.in_rst_0"
+   kind="reset"
+   version="19.1"
+   start="rst_translator.out_reset"
+   end="avalon_st_adapter.in_rst_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>avalon_st_adapter</endModule>
+  <endConnectionPoint>in_rst_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/rst_controller_001.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="rst_controller_001.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>rst_controller_001</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/rst_controller_001.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="rst_controller_001.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>rst_controller_001</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/rst_translator.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="rst_translator.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>rst_translator</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_002.reset_out/ddr3_ram.global_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_002.reset_out"
+   end="ddr3_ram.global_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_002</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>global_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/rst_controller_002.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="rst_controller_002.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>rst_controller_002</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/rst_controller_002.reset_in1"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="rst_controller_002.reset_in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>rst_controller_002</endModule>
+  <endConnectionPoint>reset_in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_003.reset_out/ddr3_ram.soft_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_003.reset_out"
+   end="ddr3_ram.soft_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_003</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>ddr3_ram</endModule>
+  <endConnectionPoint>soft_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/rst_controller_003.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="rst_controller_003.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>rst_controller_003</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/rst_controller_003.reset_in1"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="rst_controller_003.reset_in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>rst_controller_003</endModule>
+  <endConnectionPoint>reset_in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/descriptor_memory.reset1"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="descriptor_memory.reset1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>descriptor_memory</endModule>
+  <endConnectionPoint>reset1</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/eth_tse.reset_connection"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="eth_tse.reset_connection">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>eth_tse</endModule>
+  <endConnectionPoint>reset_connection</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/output_pio.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="output_pio.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>output_pio</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/sys_clk_timer.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="sys_clk_timer.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>sys_clk_timer</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/sysid.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="sysid.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>sysid</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/mm_interconnect_1.eth_tse_reset_connection_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="mm_interconnect_1.eth_tse_reset_connection_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>eth_tse_reset_connection_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_004.reset_out/rst_translator_001.in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_004.reset_out"
+   end="rst_translator_001.in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_004</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_translator_001.out_reset/avalon_st_adapter_001.in_rst_0"
+   kind="reset"
+   version="19.1"
+   start="rst_translator_001.out_reset"
+   end="avalon_st_adapter_001.in_rst_0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_translator_001</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>avalon_st_adapter_001</endModule>
+  <endConnectionPoint>in_rst_0</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/rst_controller_004.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="rst_controller_004.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>rst_controller_004</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/rst_controller_004.reset_in1"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="rst_controller_004.reset_in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>rst_controller_004</endModule>
+  <endConnectionPoint>reset_in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/rst_controller_004.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="rst_controller_004.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>rst_controller_004</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk/rst_translator_001.clk"
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="rst_translator_001.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk</startConnectionPoint>
+  <endModule>rst_translator_001</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_005.reset_out/ext_flash.reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_005.reset_out"
+   end="ext_flash.reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_005</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>ext_flash</endModule>
+  <endConnectionPoint>reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_005.reset_out/mm_interconnect_1.ext_flash_reset_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_005.reset_out"
+   end="mm_interconnect_1.ext_flash_reset_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_005</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>ext_flash_reset_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_005.reset_out/irq_synchronizer.receiver_clk_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_005.reset_out"
+   end="irq_synchronizer.receiver_clk_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_005</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>irq_synchronizer</endModule>
+  <endConnectionPoint>receiver_clk_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="sys_clk.clk_reset/rst_controller_005.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="rst_controller_005.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>sys_clk</startModule>
+  <startConnectionPoint>clk_reset</startConnectionPoint>
+  <endModule>rst_controller_005</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/rst_controller_005.reset_in1"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="rst_controller_005.reset_in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>rst_controller_005</endModule>
+  <endConnectionPoint>reset_in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="ext_flash_clock_bridge.out_clk/rst_controller_005.clk"
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="rst_controller_005.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ext_flash_clock_bridge</startModule>
+  <startConnectionPoint>out_clk</startConnectionPoint>
+  <endModule>rst_controller_005</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_006.reset_out/mm_interconnect_1.ddr3_ram_avl_translator_reset_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_006.reset_out"
+   end="mm_interconnect_1.ddr3_ram_avl_translator_reset_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_006</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>ddr3_ram_avl_translator_reset_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="rst_controller_006.reset_out/mm_interconnect_1.ddr3_ram_soft_reset_reset_bridge_in_reset"
+   kind="reset"
+   version="19.1"
+   start="rst_controller_006.reset_out"
+   end="mm_interconnect_1.ddr3_ram_soft_reset_reset_bridge_in_reset">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>rst_controller_006</startModule>
+  <startConnectionPoint>reset_out</startConnectionPoint>
+  <endModule>mm_interconnect_1</endModule>
+  <endConnectionPoint>ddr3_ram_soft_reset_reset_bridge_in_reset</endConnectionPoint>
+ </connection>
+ <connection
+   name="cpu.debug_reset_request/rst_controller_006.reset_in0"
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="rst_controller_006.reset_in0">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>cpu</startModule>
+  <startConnectionPoint>debug_reset_request</startConnectionPoint>
+  <endModule>rst_controller_006</endModule>
+  <endConnectionPoint>reset_in0</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram_resetn.out_reset/rst_controller_006.reset_in1"
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="rst_controller_006.reset_in1">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram_resetn</startModule>
+  <startConnectionPoint>out_reset</startConnectionPoint>
+  <endModule>rst_controller_006</endModule>
+  <endConnectionPoint>reset_in1</endConnectionPoint>
+ </connection>
+ <connection
+   name="ddr3_ram.afi_clk/rst_controller_006.clk"
+   kind="clock"
+   version="19.1"
+   start="ddr3_ram.afi_clk"
+   end="rst_controller_006.clk">
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <startModule>ddr3_ram</startModule>
+  <startConnectionPoint>afi_clk</startConnectionPoint>
+  <endModule>rst_controller_006</endModule>
+  <endConnectionPoint>clk</endConnectionPoint>
+ </connection>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altpll</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTPLL Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>45</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>49</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>33</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>9</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>20</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_pio</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_onchip_memory2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>channel_adapter</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Channel Adapter</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>8</instanceCount>
+  <name>avalon_streaming_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Sink</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>8</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_nios2_gen2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Nios II Processor</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>31</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>7</instanceCount>
+  <name>interrupt_receiver</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Interrupt Receiver</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>13</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>nios_custom_instruction_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Custom Instruction Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_mem_if_ddr3_emif</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>DDR3 SDRAM Controller with UniPHY Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_reset_bridge</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Reset Bridge</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_uart</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>UART (RS-232 Serial Port) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>8</instanceCount>
+  <name>interrupt_sender</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Interrupt Sender</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_eth_tse</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Triple-Speed Ethernet Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_generic_quad_spi_controller</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Generic QUAD SPI Controller Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_clock_bridge</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Bridge</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_timer</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Interval Timer Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_msgdma</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Modular Scatter-Gather DMA Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_onchip_flash</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Flash Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Clock Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Output</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_sysid_qsys</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>System ID Peripheral Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>multiplexer</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Multiplexer</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>udp_generator</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>UDP generator</displayName>
+  <version>1.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_mm_interconnect</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>MM Interconnect</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_irq_mapper</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Merlin IRQ Mapper</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_irq_clock_crosser</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Merlin IRQ Clock Crosser</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_avalon_st_adapter</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Adapter</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>7</instanceCount>
+  <name>altera_reset_controller</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Merlin Reset Controller</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>altera_reset_translator</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Reset Translator</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>4</instanceCount>
+  <name>avalon_streaming</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Avalon Streaming Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>23</instanceCount>
+  <name>clock</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Clock Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>31</instanceCount>
+  <name>avalon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Avalon Memory Mapped Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>16</instanceCount>
+  <name>clock</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Clock Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>7</instanceCount>
+  <name>interrupt</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Interrupt Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>4</instanceCount>
+  <name>avalon_streaming</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Avalon Streaming Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>69</instanceCount>
+  <name>reset</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IConnection</subtype>
+  <displayName>Reset Connection</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB000001927AA0D224</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/q_sys/synthesis/q_sys.qip b/FPGA_firmware/q_sys/synthesis/q_sys.qip
new file mode 100644
index 0000000..8479e52
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/q_sys.qip
@@ -0,0 +1,8602 @@
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "q_sys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../q_sys.sopcinfo"]
+set_global_assignment -entity "q_sys" -library "q_sys" -name SLD_INFO "QSYS_NAME q_sys HAS_SOPCINFO 1 GENERATION_ID 1728634208"
+set_global_assignment -library "q_sys" -name MISC_FILE [file join $::quartus(qip_path) "../q_sys.cmp"]
+set_global_assignment -library "q_sys" -name SLD_FILE [file join $::quartus(qip_path) "q_sys.regmap"]
+set_global_assignment -library "q_sys" -name SLD_FILE [file join $::quartus(qip_path) "q_sys.debuginfo"]
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "q_sys" -name MISC_FILE [file join $::quartus(qip_path) "../../q_sys.qsys"]
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXM="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "cV9zeXM="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyODYzNDIwOA==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CUklER0VfMF9JTl9DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CUklER0VfMF9JTl9DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CUklER0VfMF9JTl9DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERFIzX1JBTV9QTExfUkVGX0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERFIzX1JBTV9QTExfUkVGX0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERFIzX1JBTV9QTExfUkVGX0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfUlhfQ0xPQ0tfQ09OTkVDVElPTl9DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfUlhfQ0xPQ0tfQ09OTkVDVElPTl9DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfUlhfQ0xPQ0tfQ09OTkVDVElPTl9SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfVFhfQ0xPQ0tfQ09OTkVDVElPTl9DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfVFhfQ0xPQ0tfQ09OTkVDVElPTl9DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19FVEhfVFNFX1BDU19NQUNfVFhfQ0xPQ0tfQ09OTkVDVElPTl9SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNfQ0xLX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNfQ0xLX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNfQ0xLX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXI="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1JFU0VUX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIGlucHV0cw=="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUUFVUX1JFU0VUX1NZTkNfRURHRVM=::ZGVhc3NlcnQ=::T3V0cHV0IFJlc2V0IFN5bmNocm9ub3VzIEVkZ2Vz"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lOQ19ERVBUSA==::Mg==::U3luY2hyb25pemVyIGRlcHRo"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRVUVTVF9QUkVTRU5U::MA==::UmVzZXQgcmVxdWVzdCBsb2dpYyBlbmFibGU="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX1dBSVRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCB3YWl0IHRpbWU="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUlOX1JTVF9BU1NFUlRJT05fVElNRQ==::Mw==::TWluaW11bSByZXNldCBhc3NlcnRpb24gdGltZQ=="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX0VBUkxZX0RTUlRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCBkZWFzc2VydCB0aW1pbmc="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4w::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjA="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4x::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4y::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjI="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4z::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjM="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU40::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjQ="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU41::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjU="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU42::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjY="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU43::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjc="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU44::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjg="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU45::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjk="
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEw"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEx"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMg==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEy"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMw==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEz"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE0"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE1"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU5QVVQ=::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcmVzZXRfaW5wdXRz"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURBUFRfUkVTRVRfUkVRVUVTVA==::MA==::T25seSBhZGFwdCBvbmx5IHJlc2V0IHJlcXVlc3Q="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYXZhbG9uX3N0X2FkYXB0ZXJfMDAx"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::U3ltYm9sIFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MQ==::VXNlIFBhY2tldA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MzI=::U291cmNlIERhdGEgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::Ng==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MQ==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::Mg==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::Mg==::U291cmNlIFJlYWR5IExhdGVuY3k="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MzI=::U2luayBEYXRhIFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::Ng==::U2luayBFcnJvciBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MQ==::U2luayBVc2VzIEVtcHR5IFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::Mg==::U2luayBFbXB0eSBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYXZhbG9uX3N0X2FkYXB0ZXJfMDAxX3RpbWluZ19hZGFwdGVyXzA="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFRpbWluZyBBZGFwdGVy"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::WUVT::SW5jbHVkZSBFbXB0eSBTaWduYWw="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::NA==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::Mg==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::Ng==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::dHJ1ZQ==::SW5jbHVkZSBWYWxpZCBTaWduYWw="
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::dHJ1ZQ==::SW5jbHVkIFZhbGlkIFNpZ25hbA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYXZhbG9uX3N0X2FkYXB0ZXI="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::U3ltYm9sIFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MQ==::VXNlIFBhY2tldA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MzI=::U291cmNlIERhdGEgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MQ==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::Mg==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MzI=::U2luayBEYXRhIFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MQ==::U2luayBVc2VzIEVtcHR5IFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::Mg==::U2luayBFbXB0eSBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ="
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYXZhbG9uX3N0X2FkYXB0ZXJfZXJyb3JfYWRhcHRlcl8w"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::WUVT::SW5jbHVkZSBFbXB0eSBTaWduYWw="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::NA==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2lycV9jbG9ja19jcm9zc2Vy"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIElSUSBDbG9jayBDcm9zc2Vy"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "U3luY2hyb25pemVzIGludGVycnVwdCBzZW5kZXJzIGFuZCByZWNlaXZlcnMgdGhhdCBhcmUgaW4gZGlmZmVyZW50IGNsb2NrIGRvbWFpbnMu"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVJRX1dJRFRI::MQ==::SVJRIHdpZHRo"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19SRUNFSVZFUl9JTlRFUlJVUFRTX1VTRUQ=::LTE=::QXV0byBJTlRFUlJVUFRTX1VTRUQ="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfaXJxX21hcHBlcg=="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIElSUSBNYXBwZXI="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgaW5kaXZpZHVhbCBpbnRlcnJ1cHQgd2lyZXMgdG8gYSBidXMuIEJ5IGRlZmF1bHQsIHRoZSBpbnRlcnJ1cHQgc2VuZGVyIGNvbm5lY3RlZCB0byB0aGUgcmVjZWl2ZXIwIGludGVyZmFjZSBvZiB0aGUgSVJRIG1hcHBlciBpcyB0aGUgaGlnaGVzdCBwcmlvcml0eSB3aXRoIHNlcXVlbnRpYWwgcmVjZWl2ZXJzIGJlaWluZyBzdWNjZXNzaXZlbHkgbG93ZXIgcHJpb3JpdHku"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1JDVlJT::NQ==::TnVtYmVyIG9mIHJlY2VpdmVycw=="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VOREVSX0lSUV9XSURUSA==::MzI=::U2VuZGVyIGludGVycnVwdCB3aWR0aA=="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVJRX01BUA==::MDoyLDE6MywyOjUsMzowLDQ6NA==::SVJRIG1hcA=="
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzE="
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfYXZhbG9uX3N0X2FkYXB0ZXJfMDIw"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MTg=::U3ltYm9sIFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MA==::VXNlIFBhY2tldA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MTg=::U291cmNlIERhdGEgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MA==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::MQ==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MTg=::U2luayBEYXRhIFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MA==::U2luayBVc2VzIEVtcHR5IFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::MQ==::U2luayBFbXB0eSBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfYXZhbG9uX3N0X2FkYXB0ZXJfMDIwX2Vycm9yX2FkYXB0ZXJfMA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MTg=::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfYXZhbG9uX3N0X2FkYXB0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::U3ltYm9sIFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MA==::VXNlIFBhY2tldA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MzQ=::U291cmNlIERhdGEgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MA==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::MQ==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MzQ=::U2luayBEYXRhIFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MA==::U2luayBVc2VzIEVtcHR5IFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::MQ==::U2luayBFbXB0eSBQb3J0IFdpZHRo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfYXZhbG9uX3N0X2FkYXB0ZXJfZXJyb3JfYWRhcHRlcl8w"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9oYW5kc2hha2VfY2xvY2tfY3Jvc3Nlcg=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEhhbmRzaGFrZSBDbG9jayBDcm9zc2Vy"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Q29ubmVjdHMgc3RyZWFtcyB0aGF0IG9wZXJhdGUgYXQgZGlmZmVyZW50IGZyZXF1ZW5jaWVzIHVzaW5nIGEgaGFuZC1zaGFraW5nIHByb3RvY29sIHRvIHByb3BhZ2F0ZSB0cmFuc2ZlciBjb250cm9sIHNpZ25hbHMgYW5kIHJlc3BvbnNlcyBhY3Jvc3MgdGhlIGNsb2NrIGJvdW5kYXJ5IGFuZCByZXNwb25zZXMgaW4gdGhlIG90aGVyIGRpcmVjdGlvbi4="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MTIx::RGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::MTIx::Qml0cyBwZXIgc3ltYm9s"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MQ==::VXNlIHBhY2tldHM="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0NIQU5ORUw=::MQ==::VXNlIGNoYW5uZWw="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MjE=::Q2hhbm5lbCB3aWR0aA=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0NIQU5ORUw=::MA==::TWF4aW11bSBjaGFubmVsIHZhbHVl"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VSUk9S::MA==::VXNlIGVycm9y"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MQ==::RXJyb3Igd2lkdGg="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfU1lOQ19ERVBUSA==::Mg==::VmFsaWQgc3luY2hyb25pemVyIGRlcHRo"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRFlfU1lOQ19ERVBUSA==::Mg==::UmVhZHkgc3luY2hyb25pemVyIGRlcHRo"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX09VVFBVVF9QSVBFTElORQ==::MA==::VXNlIG91dHB1dCBwaXBlbGluZQ=="
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19JTl9DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19PVVRfQ0xLX0NMT0NLX1JBVEU=::MTUwMDAwMDAw::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl93aWR0aF9hZGFwdGVy"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBXaWR0aCBBZGFwdGVy"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgYmV0d2VlbiBBdmFsb24tTU0gbWFzdGVyIGFuZCBzbGF2ZXMgd2l0aCBkaWZmZXJlbnQgZGF0YSBhbmQgYnl0ZSBlbmFibGUgd2lkdGhzLg=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0FERFJfSA==::NDY=::SW5wdXQgcGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0FERFJfTA==::MTg=::SW5wdXQgcGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0RBVEFfSA==::MTU=::SW5wdXQgcGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0RBVEFfTA==::MA==::SW5wdXQgcGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVFTl9I::MTc=::SW5wdXQgcGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVFTl9M::MTY=::SW5wdXQgcGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVfQ05UX0g=::NjE=::SW5wdXQgcGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JZVEVfQ05UX0w=::NTM=::SW5wdXQgcGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NDc=::SW5wdXQgcGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX1dSSVRF::NDk=::SW5wdXQgcGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUV1JBUF9I::NzA=::SW5wdXQgcGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUV1JBUF9M::NjI=::SW5wdXQgcGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1NJWkVfSA==::NzM=::SW5wdXQgcGFja2V0IGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1NJWkVfTA==::NzE=::SW5wdXQgcGFja2V0IGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1JFU1BPTlNFX1NUQVRVU19I::OTk=::SW5wdXQgcGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1JFU1BPTlNFX1NUQVRVU19M::OTg=::SW5wdXQgcGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX1RSQU5TX0VYQ0xVU0lWRQ==::NTI=::SW5wdXQgcGFja2V0IGV4Y2x1c2l2ZSB0cmFucyBmaWVsZA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1RZUEVfSA==::NzU=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX0JVUlNUX1RZUEVfTA==::NzQ=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX09SSV9CVVJTVF9TSVpFX0w=::MTAw::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fUEtUX09SSV9CVVJTVF9TSVpFX0g=::MTAy::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fU1RfREFUQV9X::MTAz::SW5wdXQgZGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9BRERSX0g=::NjQ=::T3V0cHV0IHBhY2tldCBhZGRyZXNzIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9BRERSX0w=::MzY=::T3V0cHV0IHBhY2tldCBhZGRyZXNzIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9EQVRBX0g=::MzE=::T3V0cHV0IHBhY2tldCBieXRlZW5hYmxlIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9EQVRBX0w=::MA==::T3V0cHV0IHBhY2tldCBieXRlZW5hYmxlIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFRU5fSA==::MzU=::T3V0cHV0IHBhY2tldCBieXRlIGNvdW50IGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFRU5fTA==::MzI=::T3V0cHV0IHBhY2tldCBieXRlIGNvdW50IGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFX0NOVF9I::Nzk=::T3V0cHV0IHBhY2tldCBidXJzdHdyYXAgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CWVRFX0NOVF9M::NzE=::T3V0cHV0IHBhY2tldCBidXJzdHdyYXAgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9UUkFOU19DT01QUkVTU0VEX1JFQUQ=::NjU=::T3V0cHV0IHBhY2tldCBkYXRhIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9TSVpFX0g=::OTE=::T3V0cHV0IHBhY2tldCBidXJzdCBzaXplIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9TSVpFX0w=::ODk=::T3V0cHV0IHBhY2tldCBidXJzdCBzaXplIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9SRVNQT05TRV9TVEFUVVNfSA==::MTE3::T3V0cHV0IHBhY2tldCByZXNwb25zZSBzdGF0dXMgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9SRVNQT05TRV9TVEFUVVNfTA==::MTE2::T3V0cHV0IHBhY2tldCByZXNwb25zZSBzdGF0dXMgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9UUkFOU19FWENMVVNJVkU=::NzA=::T3V0cHV0IHBhY2tldCBleGNsdXNpdmUgdHJhbnMgZmllbGQ="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9UWVBFX0g=::OTM=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9CVVJTVF9UWVBFX0w=::OTI=::SW5wdXQgcGFja2V0IGJ1cnN0IHR5cGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9PUklfQlVSU1RfU0laRV9M::MTE4::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1BLVF9PUklfQlVSU1RfU0laRV9I::MTIw::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX1NUX0RBVEFfVw==::MTIx::T3V0cHV0IHBhY2tldCBkYXRhIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1BUSU1JWkVfRk9SX1JTUA==::MQ==::T3B0aW1pemUgZm9yIHJlc3BvbnNl"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTUE9OU0VfUEFUSA==::MQ==::UmVzcG9uc2Ugd2lkdGggYWRhcHRlcg=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OU1RBTlRfQlVSU1RfU0laRQ==::MQ==::U3lzdGVtIG9ubHkgaGF2ZSBjb25zdGFudCBidXJzdCBzaXpl"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0lORw==::MQ==::TmFycm93LXRvLVdpZGUgcGFja2luZw=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fTUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAyOjEwMCkgcmVzcG9uc2Vfc3RhdHVzKDk5Ojk4KSBjYWNoZSg5Nzo5NCkgcHJvdGVjdGlvbig5Mzo5MSkgdGhyZWFkX2lkKDkwKSBkZXN0X2lkKDg5Ojg1KSBzcmNfaWQoODQ6ODApIHFvcyg3OSkgYmVnaW5fYnVyc3QoNzgpIGRhdGFfc2lkZWJhbmQoNzcpIGFkZHJfc2lkZWJhbmQoNzYpIGJ1cnN0X3R5cGUoNzU6NzQpIGJ1cnN0X3NpemUoNzM6NzEpIGJ1cnN0d3JhcCg3MDo2MikgYnl0ZV9jbnQoNjE6NTMpIHRyYW5zX2V4Y2x1c2l2ZSg1MikgdHJhbnNfbG9jayg1MSkgdHJhbnNfcmVhZCg1MCkgdHJhbnNfd3JpdGUoNDkpIHRyYW5zX3Bvc3RlZCg0OCkgdHJhbnNfY29tcHJlc3NlZF9yZWFkKDQ3KSBhZGRyKDQ2OjE4KSBieXRlZW4oMTc6MTYpIGRhdGEoMTU6MCk=::SW5wdXQgTWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX01FUkxJTl9QQUNLRVRfRk9STUFU::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvciAtIG91dHB1dA=="
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9TSVpFX1c=::Mw==::Q29tbWFuZC1zaXplIGlucHV0IHdpZHRo"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FERFJFU1NfQUxJR05NRU5U::MA==::QWRkcmVzcyBhbGlnbm1lbnQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX211eF8wMDI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MQ==::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX211eF8wMDE="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::NA==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMQ==::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX211eA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MjE=::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDE=::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX2RlbXV4XzAxNA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::NQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX2RlbXV4XzAxMA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Mg==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX2RlbXV4XzAwMg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Mg==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX2RlbXV4XzAwMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcnNwX2RlbXV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::NA==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MTUwMDAwMDAw::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX211eF8wMTQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::NQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwx::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX211eF8wMDI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwx::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX211eF8wMDE="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MQ==::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX211eA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::NA==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMQ==::QXJiaXRyYXRpb24gc2hhcmVz"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX2RlbXV4XzAwMg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX2RlbXV4XzAwMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::NA==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MjE=::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfY21kX2RlbXV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::UGFja2V0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MjE=::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MjE=::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9idXJzdF9hZGFwdGVy"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBCdXJzdCBBZGFwdGVy"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjb21tb2RhdGVzIHRoZSBidXJzdCBjYXBhYmlsaXRpZXMgb2YgZWFjaCBpbnRlcmZhY2UgaW4gdGhlIHN5c3RlbSwgaW5jbHVkaW5nIGludGVyZmFjZXMgdGhhdCBkbyBub3Qgc3VwcG9ydCBidXJzdCB0cmFuc2ZlcnMsIHRyYW5zbGF0aW5nIGJ1cnN0IHNpemVzIGFzIHJlcXVpcmVkLg=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::OTY=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::Nzk=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzE=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::OTE=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::ODk=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfSA==::OTM=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfTA==::OTI=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::ODg=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::ODA=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NjU=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX05BUlJPV19TSVpF::MA==::c2xhdmUgbmFycm93IHNpemVkIG91dHB1dA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5fTkFSUk9XX1NJWkU=::MA==::c2xhdmUgbmFycm93IHNpemVkIG91dHB1dA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX0ZJWEVE::MA==::c2xhdmUgZml4ZWQgb3V0cHV0"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX0NPTVBMRVRFX1dSQVA=::MA==::c2xhdmUgY29tcGxldGUgd3JhcCBvdXRwdXQ="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX0JZVEVfQ05UX0g=::Nzk=::TWF4aW11bSBvdXRwdXQgcGFja2V0IGJ5dGUgY291bnQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1VUX0JVUlNUV1JBUF9I::ODc=::TWF4aW11bSBvdXRwdXQgcGFja2V0IGJ1cnN0d3JhcCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NUFJFU1NFRF9SRUFEX1NVUFBPUlQ=::MA==::Q29tcHJlc3NlZCByZWFkIHN1cHBvcnQ="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9TWU5USEVTSVM=::MQ==::Qnl0ZWVuYWJsZSBTeW50aGVzaXMgU3VwcG9ydA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRV9JTlBVVFM=::MA==::QnVyc3QgYWRhcHRlciBpbnB1dCBwaXBlbGluZQ=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9fV1JBUF9TVVBQT1JU::MA==::Tm8gd3JhcCBjYWxjdWxhdGlvbiBzdXBwb3J0"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DT01QTEVURV9XUkFQX1NVUFBPUlQ=::MA==::SW4tY29tcGxldGVkIHdyYXAgY2FsY3VsYXRpb24gc3VwcG9ydA=="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX0NPTlNUX01BU0s=::Mw==::QnVyc3R3cmFwLWNvbnN0YW50IG1hc2s="
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX0NPTlNUX1ZBTFVF::Mw==::QnVyc3R3cmFwLWNvbnN0YW50IHZhbHVl"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURBUFRFUl9WRVJTSU9O::MTMuMQ==::U2VsZWN0IGJ1cnN0IGFkYXB0ZXIgdmVyc2lvbg=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl90cmFmZmljX2xpbWl0ZXI="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBUcmFmZmljIExpbWl0ZXI="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "RW5zdXJlcyB0aGUgcmVzcG9uc2VzIGFycml2ZSBpbiBvcmRlciwgc2ltcGxpZnlpbmcgdGhlIFFzeXMgcmVzcG9uc2UgbmV0d29yay4="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::MTAy::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::OTg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::Nzk=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzE=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::NjY=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::MTA4::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBNU0I="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::MTA4::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBMU0I="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0xFTkdUSA==::MQ==::TWF4aW11bSBidXJzdCBsZW5ndGg="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX09VVFNUQU5ESU5HX1JFU1BPTlNFUw==::MzY=::TWF4aW11bSBvdXRzdGFuZGluZyByZXNwb25zZXM="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVE::MA==::UGlwZWxpbmU="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MjE=::VmFsaWQgd2lkdGg="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5GT1JDRV9PUkRFUg==::MQ==::RW5mb3JjZSBvcmRlcg=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9IQVpBUkRT::MA==::UHJldmVudCBoYXphcmRz"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfUE9TVEVEX1dSSVRFUw==::MQ==::SGF6YXJkIHByZXZlbnRpb246IHBvc3RlZCB3cml0ZSBzdXBwb3J0"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfTk9OUE9TVEVEX1dSSVRFUw==::MA==::SGF6YXJkIHByZXZlbnRpb246IG5vbi1wb3N0ZWQgd3JpdGUgc3VwcG9ydA=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVPUkRFUg==::MA==::RW5hYmxlIHJlb3JkZXIgYnVmZmVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAyOA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MA==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NDY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MTg=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTM=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTE=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODU=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NDk=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTA=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTAz::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAyOjEwMCkgcmVzcG9uc2Vfc3RhdHVzKDk5Ojk4KSBjYWNoZSg5Nzo5NCkgcHJvdGVjdGlvbig5Mzo5MSkgdGhyZWFkX2lkKDkwKSBkZXN0X2lkKDg5Ojg1KSBzcmNfaWQoODQ6ODApIHFvcyg3OSkgYmVnaW5fYnVyc3QoNzgpIGRhdGFfc2lkZWJhbmQoNzcpIGFkZHJfc2lkZWJhbmQoNzYpIGJ1cnN0X3R5cGUoNzU6NzQpIGJ1cnN0X3NpemUoNzM6NzEpIGJ1cnN0d3JhcCg3MDo2MikgYnl0ZV9jbnQoNjE6NTMpIHRyYW5zX2V4Y2x1c2l2ZSg1MikgdHJhbnNfbG9jayg1MSkgdHJhbnNfcmVhZCg1MCkgdHJhbnNfd3JpdGUoNDkpIHRyYW5zX3Bvc3RlZCg0OCkgdHJhbnNfY29tcHJlc3NlZF9yZWFkKDQ3KSBhZGRyKDQ2OjE4KSBieXRlZW4oMTc6MTYpIGRhdGEoMTU6MCk=::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAyMg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MCw1LDIsNiwz::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDAwMDEsMDAwMTAsMDAxMDAsMDEwMDAsMTAwMDA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxyZWFkLHJlYWQsd3JpdGUsd3JpdGU=::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MCwweDAsMHgwLDB4MA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgwLDB4MCwweDAsMHgwLDB4MA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwx::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCww::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMDAwMToweDA6MHgwOmJvdGg6MTowOjA6MSw1OjAwMDEwOjB4MDoweDA6cmVhZDoxOjA6MDoxLDI6MDAxMDA6MHgwOjB4MDpyZWFkOjE6MDowOjEsNjowMTAwMDoweDA6MHgwOndyaXRlOjE6MDowOjEsMzoxMDAwMDoweDA6MHgwOndyaXRlOjE6MDowOjE=::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAxMA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MCwx::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDEsMTA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxyZWFk::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgwLDB4MA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwx::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCww::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMToweDA6MHgwOmJvdGg6MTowOjA6MSwxOjEwOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAwOQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MA==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAwOA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MCwxLDcsNA==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDAwMSwwMDEwLDAxMDAsMTAwMA==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxyZWFkLHJlYWQsd3JpdGU=::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MCwweDAsMHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgwLDB4MCwweDAsMHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMDAxOjB4MDoweDA6Ym90aDoxOjA6MDoxLDE6MDAxMDoweDA6MHgwOnJlYWQ6MTowOjA6MSw3OjAxMDA6MHgwOjB4MDpyZWFkOjE6MDowOjEsNDoxMDAwOjB4MDoweDA6d3JpdGU6MTowOjA6MQ==::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAwNA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::NQ==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgxODQwMDAwMA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgxODQwMjAwMA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::NToxOjB4MTg0MDAwMDA6MHgxODQwMjAwMDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::NQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAwMg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::Mw==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHg4MDAwMDAw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgxMDAwMDAwMA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxOjB4ODAwMDAwMDoweDEwMDAwMDAwOmJvdGg6MTowOjA6MQ==::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mw==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVyXzAwMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::Myw4LDE1LDI=::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDAwMSwwMDEwLDAxMDAsMTAwMA==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsYm90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHg4MDAwMDAwLDB4MTQwMDAwMDAsMHgxODIwMDAwMCwweDE4NDAyODAw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgxMDAwMDAwMCwweDE4MDAwMDAwLDB4MTg0MDAwMDAsMHgxODQwMzAwMA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMQ==::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzowMDAxOjB4ODAwMDAwMDoweDEwMDAwMDAwOmJvdGg6MTowOjA6MSw4OjAwMTA6MHgxNDAwMDAwMDoweDE4MDAwMDAwOmJvdGg6MTowOjA6MSwxNTowMTAwOjB4MTgyMDAwMDA6MHgxODQwMDAwMDpib3RoOjE6MDowOjEsMjoxMDAwOjB4MTg0MDI4MDA6MHgxODQwMzAwMDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mw==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzFfcm91dGVy"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::Myw4LDE1LDUsMiw2LDEsOSw0LDE2LDE4LDExLDEzLDIwLDEwLDEyLDcsMCwxNywxNCwxOQ==::RGVzdGluYXRpb24gSUQ="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDAwMDAwMDAwMDAwMDAwMDAwMDAxLDAwMDAwMDAwMDAwMDAwMDAwMDEwMCwwMDAwMDAwMDAwMTAwMDAwMDAwMDAsMDAwMDAwMTAwMDAwMDAwMDAwMDAwLDAwMDAwMDAwMDEwMDAwMDAwMDAwMCwwMDAwMDAwMDAwMDAwMDAwMDEwMDAsMTAwMDAwMDAwMDAwMDAwMDAwMDAwLDAxMDAwMDAwMDAwMDAwMDAwMDAwMCwwMDEwMDAwMDAwMDAwMDAwMDAwMDAsMDAwMDEwMDAwMDAwMDAwMDAwMDAwLDAwMDAwMTAwMDAwMDAwMDAwMDAwMCwwMDAwMDAwMTAwMDAwMDAwMDAwMDAsMDAwMDAwMDAxMDAwMDAwMDAwMDAwLDAwMDAwMDAwMDAwMDEwMDAwMDAwMCwwMDAwMDAwMDAwMDAwMDEwMDAwMDAsMDAwMDAwMDAwMDAwMDAwMTAwMDAwLDAwMDAwMDAwMDAwMDAwMDAwMDAxMCwwMDAxMDAwMDAwMDAwMDAwMDAwMDAsMDAwMDAwMDAwMDAxMDAwMDAwMDAwLDAwMDAwMDAwMDAwMDAxMDAwMDAwMCwwMDAwMDAwMDAwMDAwMDAwMTAwMDA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsYm90aCxib3RoLGJvdGgsYm90aCxib3RoLGJvdGgsYm90aCxib3RoLGJvdGgsYm90aCxib3RoLGJvdGgsYm90aCxib3RoLHJlYWQsYm90aCxib3RoLHJlYWQ=::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHg4MDAwMDAwLDB4MTQwMDAwMDAsMHgxODIwMDAwMCwweDE4NDAwMDAwLDB4MTg0MDI4MDAsMHgxODQwMzAwMCwweDE4NDAzNDAwLDB4MTg0MDNjMDAsMHgxODQwM2MyMCwweDE4NDAzYzQwLDB4MTg0MDNjNjAsMHgxODQwM2M4MCwweDE4NDAzY2EwLDB4MTg0MDNjYzAsMHgxODQwM2NlMCwweDE4NDAzZDAwLDB4MTg0MDNkMjAsMHgxODQwM2Q0MCwweDE4NDAzZDUwLDB4MTg0MDNkNjAsMHgxODQwM2Q2OA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgxMDAwMDAwMCwweDE4MDAwMDAwLDB4MTg0MDAwMDAsMHgxODQwMjAwMCwweDE4NDAzMDAwLDB4MTg0MDM0MDAsMHgxODQwMzgwMCwweDE4NDAzYzIwLDB4MTg0MDNjNDAsMHgxODQwM2M2MCwweDE4NDAzYzgwLDB4MTg0MDNjYTAsMHgxODQwM2NjMCwweDE4NDAzY2UwLDB4MTg0MDNkMDAsMHgxODQwM2QyMCwweDE4NDAzZDQwLDB4MTg0MDNkNTAsMHgxODQwM2Q2MCwweDE4NDAzZDY4LDB4MTg0MDNkNzA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzowMDAwMDAwMDAwMDAwMDAwMDAwMDE6MHg4MDAwMDAwOjB4MTAwMDAwMDA6Ym90aDoxOjA6MDoxLDg6MDAwMDAwMDAwMDAwMDAwMDAwMTAwOjB4MTQwMDAwMDA6MHgxODAwMDAwMDpib3RoOjE6MDowOjEsMTU6MDAwMDAwMDAwMDEwMDAwMDAwMDAwOjB4MTgyMDAwMDA6MHgxODQwMDAwMDpib3RoOjE6MDowOjEsNTowMDAwMDAxMDAwMDAwMDAwMDAwMDA6MHgxODQwMDAwMDoweDE4NDAyMDAwOmJvdGg6MTowOjA6MSwyOjAwMDAwMDAwMDEwMDAwMDAwMDAwMDoweDE4NDAyODAwOjB4MTg0MDMwMDA6Ym90aDoxOjA6MDoxLDY6MDAwMDAwMDAwMDAwMDAwMDAxMDAwOjB4MTg0MDMwMDA6MHgxODQwMzQwMDpib3RoOjE6MDowOjEsMToxMDAwMDAwMDAwMDAwMDAwMDAwMDA6MHgxODQwMzQwMDoweDE4NDAzODAwOmJvdGg6MTowOjA6MSw5OjAxMDAwMDAwMDAwMDAwMDAwMDAwMDoweDE4NDAzYzAwOjB4MTg0MDNjMjA6Ym90aDoxOjA6MDoxLDQ6MDAxMDAwMDAwMDAwMDAwMDAwMDAwOjB4MTg0MDNjMjA6MHgxODQwM2M0MDpib3RoOjE6MDowOjEsMTY6MDAwMDEwMDAwMDAwMDAwMDAwMDAwOjB4MTg0MDNjNDA6MHgxODQwM2M2MDpib3RoOjE6MDowOjEsMTg6MDAwMDAxMDAwMDAwMDAwMDAwMDAwOjB4MTg0MDNjNjA6MHgxODQwM2M4MDpib3RoOjE6MDowOjEsMTE6MDAwMDAwMDEwMDAwMDAwMDAwMDAwOjB4MTg0MDNjODA6MHgxODQwM2NhMDpib3RoOjE6MDowOjEsMTM6MDAwMDAwMDAxMDAwMDAwMDAwMDAwOjB4MTg0MDNjYTA6MHgxODQwM2NjMDpib3RoOjE6MDowOjEsMjA6MDAwMDAwMDAwMDAwMTAwMDAwMDAwOjB4MTg0MDNjYzA6MHgxODQwM2NlMDpib3RoOjE6MDowOjEsMTA6MDAwMDAwMDAwMDAwMDAxMDAwMDAwOjB4MTg0MDNjZTA6MHgxODQwM2QwMDpib3RoOjE6MDowOjEsMTI6MDAwMDAwMDAwMDAwMDAwMTAwMDAwOjB4MTg0MDNkMDA6MHgxODQwM2QyMDpib3RoOjE6MDowOjEsNzowMDAwMDAwMDAwMDAwMDAwMDAwMTA6MHgxODQwM2QyMDoweDE4NDAzZDQwOmJvdGg6MTowOjA6MSwwOjAwMDEwMDAwMDAwMDAwMDAwMDAwMDoweDE4NDAzZDQwOjB4MTg0MDNkNTA6cmVhZDoxOjA6MDoxLDE3OjAwMDAwMDAwMDAwMTAwMDAwMDAwMDoweDE4NDAzZDUwOjB4MTg0MDNkNjA6Ym90aDoxOjA6MDoxLDE0OjAwMDAwMDAwMDAwMDAxMDAwMDAwMDoweDE4NDAzZDYwOjB4MTg0MDNkNjg6Ym90aDoxOjA6MDoxLDE5OjAwMDAwMDAwMDAwMDAwMDAxMDAwMDoweDE4NDAzZDY4OjB4MTg0MDNkNzA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mw==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zY19maWZv"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFNpbmdsZSBDbG9jayBGSUZP"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lNQk9MU19QRVJfQkVBVA==::MQ==::U3ltYm9scyBwZXIgYmVhdA=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::MTIy::Qml0cyBwZXIgc3ltYm9s"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSA==::MzM=::RklGTyBkZXB0aA=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MA==::Q2hhbm5lbCB3aWR0aA=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MA==::RXJyb3Igd2lkdGg="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MQ==::VXNlIHBhY2tldHM="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJTExfTEVWRUw=::MA==::VXNlIGZpbGwgbGV2ZWw="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU1QVFlfTEFURU5DWQ==::MQ==::TGF0ZW5jeQ=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTU9SWV9CTE9DS1M=::MA==::VXNlIG1lbW9yeSBibG9ja3M="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NUT1JFX0ZPUldBUkQ=::MA==::VXNlIHN0b3JlIGFuZCBmb3J3YXJk"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9GVUxMX0lG::MA==::VXNlIGFsbW9zdCBmdWxsIHN0YXR1cw=="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9FTVBUWV9JRg==::MA==::VXNlIGFsbW9zdCBlbXB0eSBzdGF0dXM="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYUExJQ0lUX01BWENIQU5ORUw=::ZmFsc2U=::RW5hYmxlIGV4cGxpY2l0IG1heENoYW5uZWw="
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQTElDSVRfTUFYQ0hBTk5FTA==::MA==::RXhwbGljaXQgbWF4Q2hhbm5lbA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV9hZ2VudA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIEFnZW50"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjb21tYW5kIHBhY2tldHMgYW5kIGlzc3VlcyB0aGUgcmVzdWx0aW5nIHRyYW5zYWN0aW9ucyB0byB0aGUgQXZhbG9uIGludGVyZmFjZS4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZXhwbGFuYXRpb25zIG9mIHRoZSBidXJzdGluZyBwcm9wZXJ0aWVzLg=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTIw::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::MTE4::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::MTE3::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::MTE2::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::OTE=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::ODk=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::OTY=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::ODg=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::ODA=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::Nzk=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzE=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NjU=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::NjY=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::MTAy::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::OTg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NZTUJPTF9X::OA==::UGFja2V0IHN5bWJvbCB3aWR0aA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfU1lNQk9MUw==::MA==::YnVyc3Rjb3VudFN5bWJvbHM="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfVw==::NQ==::YnVyc3Rjb3VudCB3aWR0aA=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fQ01E::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHRyYW5zYWN0aW9ucw=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9GSUZPX09WRVJGTE9X::MQ==::UHJldmVudCBGSUZPIG92ZXJmbG93"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEVfQ05U::MTY=::TWF4aW11bSBieXRlLWNvdW50IHZhbHVl"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUV1JBUA==::NTEx::TWF4aW11bSBidXJzdHdyYXAgdmFsdWU="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "SUQ=::Mw==::U2xhdmUgSUQ="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUNDX0VOQUJMRQ==::MA==::RUNDX0VOQUJMRQ=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfYWdlbnQ="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBBZ2VudA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VHJhbnNsYXRlcyBBdmFsb24tTU0gbWFzdGVyIHRyYW5zYWN0aW9ucyBpbnRvIFFzeXMgY29tbWFuZCBwYWNrZXRzIGFuZCB0cmFuc2xhdGVzIHRoZSBRc3lzIEF2YWxvbi1NTSBzbGF2ZSByZXNwb25zZSBwYWNrZXRzIGludG8gQXZhbG9uLU1NIHJlc3BvbnNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgYW4gZXhwbGFuYXRpb24gb2YgYnVyc3RpbmcgYmVoYXZpb3Iu"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTIw::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::MTE4::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::MTE3::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::MTE2::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19I::OTc=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19M::OTc=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfSA==::OTU=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfTA==::OTU=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfSA==::OTQ=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfTA==::OTQ=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfSA==::OTM=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfTA==::OTI=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0g=::MTE1::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0w=::MTEy::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::MTA4::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::MTA4::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::OTE=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::ODk=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0VYQ0xVU0lWRQ==::NzA=::UGFja2V0IGV4Y2x1c2l2ZSB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::Njk=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::OTY=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::MTEx::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::MTA5::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::ODg=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::ODA=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::Nzk=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzE=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NjQ=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::NjU=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::NjY=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::Njc=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::Njg=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::MTAy::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::OTg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::MTA3::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::MTAz::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTIx::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::MjE=::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::Mw==::QXZhbG9uLU1NIGJ1cnN0Y291bnQgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MQ==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTIwOjExOCkgcmVzcG9uc2Vfc3RhdHVzKDExNzoxMTYpIGNhY2hlKDExNToxMTIpIHByb3RlY3Rpb24oMTExOjEwOSkgdGhyZWFkX2lkKDEwOCkgZGVzdF9pZCgxMDc6MTAzKSBzcmNfaWQoMTAyOjk4KSBxb3MoOTcpIGJlZ2luX2J1cnN0KDk2KSBkYXRhX3NpZGViYW5kKDk1KSBhZGRyX3NpZGViYW5kKDk0KSBidXJzdF90eXBlKDkzOjkyKSBidXJzdF9zaXplKDkxOjg5KSBidXJzdHdyYXAoODg6ODApIGJ5dGVfY250KDc5OjcxKSB0cmFuc19leGNsdXNpdmUoNzApIHRyYW5zX2xvY2soNjkpIHRyYW5zX3JlYWQoNjgpIHRyYW5zX3dyaXRlKDY3KSB0cmFuc19wb3N0ZWQoNjYpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2NSkgYWRkcig2NDozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fUlNQ::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHJlc3BvbnNlcw=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "SUQ=::MA==::TWFzdGVyIElE"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX1ZBTFVF::NTEx::QnVyc3R3cmFwIHZhbHVl"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FDSEVfVkFMVUU=::MA==::Q2FjaGUgdmFsdWU="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVVJFX0FDQ0VTU19CSVQ=::MQ==::U2VjdXJpdHkgYml0IHZhbHVl"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV90cmFuc2xhdG9y"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIFRyYW5zbGF0b3I="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBzbGF2ZSBpbnRlcmZhY2UgdG8gYSBzaW1wbGlmaWVkIHJlcHJlc2VudGF0aW9uIHRoYXQgdGhlIFFzeXMgbmV0d29yayB1c2VzLiBSZWZlciB0byB0aGUgQXZhbG9uIEludGVyZmFjZSBTcGVjaWZpY2F0aW9ucyAoaHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvbWFudWFsL21ubF9hdmFsb25fc3BlYy5wZGYpIGZvciBkZWZpbml0aW9ucyBvZiB0aGUgQXZhbG9uLU1NIHNpZ25hbHMgYW5kIGV4cGxhbmF0aW9ucyBvZiB0aGUgYnVyc3RpbmcgcHJvcGVydGllcyBhbmQgYWRkcmVzcyBhbGlnbm1lbnQu"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::OQ==::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MTY=::Q29tcG9uZW50IERhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0RBVEFfVw==::MTY=::TmV0d29yayBEYXRhIHdpZHRo"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::Mg==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0JZVEVFTkFCTEVfVw==::Mg==::TmV0d29yayBieXRlZW5hYmxlIHdpZHRo"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MTA=::TmV0d29yayBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mg==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MQ==::cmVhZExhdGVuY3k="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MA==::cmVhZFdhaXRUaW1l"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfVElNSU5HX1VOSVRT::MQ==::VGltaW5nIHVuaXRz"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MQ==::VXNlIHdyaXRlZGF0YQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MA==::VXNlIHJlYWQ="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MQ==::VXNlIHdyaXRl"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MQ==::VXNlIGJ5dGVlbmFibGU="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MQ==::VXNlIGNoaXBzZWxlY3Q="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MA==::VXNlIGJ1cnN0Y291bnQ="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MA==::VXNlIHJlYWRkYXRhdmFsaWQ="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MA==::VXNlIHdhaXRyZXF1ZXN0"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFQllURUVOQUJMRQ==::MA==::VXNlIHdyaXRlYnl0ZWVuYWJsZQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FWX0NMS0VO::MQ==::VXNlIGNvbXBvbmVudCBjbGtlbg=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1VBVl9DTEtFTg==::MA==::VXNlIG5ldHdvcmsgY2xrZW4="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX09VVFBVVEVOQUJMRQ==::MA==::VXNlIG91dHB1dGVuYWJsZQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::Mg==::U3ltYm9scyBwZXIgd29yZA=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MA==::QWRkcmVzcyBzeW1ib2xz"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVRVUlSRV9VTkFMSUdORURfQUREUkVTU0VT::MA==::VW5hbGlnbmVkIGFkZHJlc3Nlcw=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::MQ==::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfV1JJVEVfVFJBTlNBQ1RJT05T::MA==::bWF4UGVuZGluZ1dyaXRlVHJhbnNhY3Rpb25z"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hJUFNFTEVDVF9USFJPVUdIX1JFQURMQVRFTkNZ::MA==::Q2hpcHNlbGVjdCB0aHJvdWdoIHJlYWQgbGF0ZW5jeQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfUkFURQ==::NTAwMDAwMDA=::Q0xPQ0tfUkFURQ=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlUX0NZQ0xFUw==::MA==::QVZfUkVBRF9XQUlUX0NZQ0xFUw=="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVF9DWUNMRVM=::MA==::QVZfV1JJVEVfV0FJVF9DWUNMRVM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVF9DWUNMRVM=::MA==::QVZfU0VUVVBfV0FJVF9DWUNMRVM="
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xEX0NZQ0xFUw==::MA==::QVZfREFUQV9IT0xEX0NZQ0xFUw=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfdHJhbnNsYXRvcg=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBUcmFuc2xhdG9y"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBtYXN0ZXIgaW50ZXJmYWNlIHRvIGEgc2ltcGxlciByZXByZXNlbnRhdGlvbiB0aGF0IHRoZSBRc3lzIG5ldHdvcmsgdXNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZGVmaW5pdGlvbnMgb2YgdGhlIEF2YWxvbi1NTSBzaWduYWxzIGFuZCBleHBsYW5hdGlvbnMgb2YgdGhlIGJ1cnN0aW5nIHByb3BlcnRpZXMu"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::OQ==::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MTY=::Q29tcG9uZW50IERhdGEgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::Mg==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MTA=::TmV0d29yayBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mg==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MA==::cmVhZExhdGVuY3k="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MQ==::cmVhZFdhaXRUaW1l"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MA==::VXNlIHdyaXRlZGF0YQ=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MQ==::VXNlIHJlYWQ="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MA==::VXNlIHdyaXRl"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MA==::VXNlIGJ5dGVlbmFibGU="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MA==::VXNlIGNoaXBzZWxlY3Q="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MA==::VXNlIGJ1cnN0Y291bnQ="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0NMS0VO::MA==::VXNlIG5ldHdvcmsgY2xrZW4="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MA==::VXNlIHJlYWRkYXRhdmFsaWQ="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MQ==::VXNlIHdhaXRyZXF1ZXN0"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::Mg==::U3ltYm9scyBwZXIgd29yZA=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MA==::QWRkcmVzcyBzeW1ib2xz"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::NjQ=::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA=="
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lOQ19SRVNFVA==::MA==::VXNlIHN5bmNocm9ub3VzIHJlc2V0cw=="
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbW1faW50ZXJjb25uZWN0XzA="
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_NAME "dWRwX2dlbmVyYXRvcg=="
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "VURQIGdlbmVyYXRvcg=="
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_AUTHOR "TS4gRHppZXdpZWNraQ=="
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "udp_generator" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QSBibG9jayBmb3IgbWFraW5nIFVEUC9JUCBzaGVsbCBvdmVyIHJlY2VpdmVkIGRhdGE="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfdHhfbXVsdGlwbGV4ZXI="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIE11bHRpcGxleGVy"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MQ==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "Yml0c1BlclN5bWJvbA==::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlUGFja2V0cw==::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::aW5Vc2VQYWNrZXRz"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::QVVUTw==::aW5Vc2VFbXB0eVBvcnQ="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "bnVtSW5wdXRJbnRlcmZhY2Vz::Mg==::TnVtYmVyIG9mIElucHV0IFBvcnRz"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGFja2V0U2NoZWR1bGluZw==::dHJ1ZQ==::VXNlIFBhY2tldCBTY2hlZHVsaW5n"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlSGlnaEJpdHNPZkNoYW5uZWw=::dHJ1ZQ==::VXNlIGhpZ2ggYml0cyB0byBpbmRpY2F0ZSBzb3VyY2UgcG9ydA=="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3ltYm9sc1BlckJlYXQ=::NA==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MQ==::aW5FcnJvcldpZHRo"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfc3lzaWQ="
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "U3lzdGVtIElEIFBlcmlwaGVyYWwgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWQ=::LTg3MTEwOTE0::MzIgYml0IFN5c3RlbSBJRA=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfc3lzX2Nsa190aW1lcg=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "SW50ZXJ2YWwgVGltZXIgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "YWx3YXlzUnVu::ZmFsc2U=::Tm8gU3RhcnQvU3RvcCBjb250cm9sIGJpdHM="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y291bnRlclNpemU=::MzI=::Q291bnRlciBTaXpl"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zml4ZWRQZXJpb2Q=::ZmFsc2U=::Rml4ZWQgcGVyaW9k"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9k::MTA=::UGVyaW9k"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHM=::TVNFQw==::VW5pdHM="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRPdXRwdXQ=::ZmFsc2U=::U3lzdGVtIHJlc2V0IG9uIHRpbWVvdXQgKFdhdGNoZG9nKQ=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c25hcHNob3Q=::dHJ1ZQ==::UmVhZGFibGUgc25hcHNob3Q="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGltZW91dFB1bHNlT3V0cHV0::ZmFsc2U=::VGltZW91dCBwdWxzZSAoMSBjbG9jayB3aWRlKQ=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3lzdGVtRnJlcXVlbmN5::NTAwMDAwMDA=::c3lzdGVtRnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "d2F0Y2hkb2dQdWxzZQ==::Mg==::V2F0Y2hkb2cgVGltZXIgUHVsc2UgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGltZXJQcmVzZXQ=::RlVMTF9GRUFUVVJFRA==::UHJlc2V0cw=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHNTdHJpbmc=::bXM=::cGVyaW9kVW5pdHNTdHJpbmc="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dmFsdWVJblNlY29uZA==::MC4wMDE=::dmFsdWVJblNlY29uZA=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "bG9hZFZhbHVl::NDk5OTk5::bG9hZFZhbHVl"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXVsdA==::MC4wMDE=::bXVsdA=="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlja3NQZXJTZWM=::MTAwLjA=::dGlja3NQZXJTZWM="
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2xhdmVfYWRkcmVzc193aWR0aA==::Mw==::c2xhdmVfYWRkcmVzc193aWR0aA=="
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_NAME "c2Vuc29yX2FsZ28="
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "c2Vuc29yX3JlY29uX3Jtc19jYWxp"
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_AUTHOR "UWluLExpcWluZyAxNy5KdWx5LDIwMjQ="
+set_global_assignment -entity "sensor_algo" -library "q_sys" -name IP_COMPONENT_VERSION "MQ=="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfb3V0cHV0X3Bpbw=="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "Yml0TW9kaWZ5aW5nT3V0UmVn::dHJ1ZQ==::RW5hYmxlIGluZGl2aWR1YWwgYml0IHNldHRpbmcvY2xlYXJpbmc="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGlyZWN0aW9u::T3V0cHV0::RGlyZWN0aW9u"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRWYWx1ZQ==::MA==::T3V0cHV0IFBvcnQgUmVzZXQgVmFsdWU="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "d2lkdGg=::OA==::V2lkdGggKDEtMzIgYml0cyk="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NTAwMDAwMDA=::Y2xvY2tSYXRl"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfdHJp::ZmFsc2U=::ZGVyaXZlZF9oYXNfdHJp"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfb3V0::dHJ1ZQ==::ZGVyaXZlZF9oYXNfb3V0"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaW4=::ZmFsc2U=::ZGVyaXZlZF9oYXNfaW4="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw==::ZmFsc2U=::ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw=="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9jYXB0dXJl::ZmFsc2U=::ZGVyaXZlZF9jYXB0dXJl"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lZGdlX3R5cGU=::Tk9ORQ==::ZGVyaXZlZF9lZGdlX3R5cGU="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pcnFfdHlwZQ==::Tk9ORQ==::ZGVyaXZlZF9pcnFfdHlwZQ=="
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaXJx::ZmFsc2U=::ZGVyaXZlZF9oYXNfaXJx"
+set_instance_assignment -name MESSAGE_DISABLE 332060 -entity altera_onchip_flash
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX29uY2hpcF9mbGFzaA=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBGbGFzaCBJbnRlbCBGUEdBIElQ"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE9uLUNoaXAgRmxhc2ggTWVnYWZ1bmN0aW9uIHdpdGggQXZhbG9uLU1NIFNsYXZlIEludGVyZmFjZS4="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9JTlRFUkZBQ0U=::UGFyYWxsZWw=::RGF0YSBpbnRlcmZhY2U="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9NT0RF::SW5jcmVtZW50aW5n::UmVhZCBidXJzdCBtb2Rl"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9CVVJTVF9DT1VOVA==::OA==::UmVhZCBidXJzdCBjb3VudA=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09ORklHVVJBVElPTl9NT0RF::U2luZ2xlIFVuY29tcHJlc3NlZCBJbWFnZQ==::Q29uZmlndXJhdGlvbiBNb2Rl"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SX0FDQ0VTU19NT0RF::UmVhZCBhbmQgd3JpdGUsUmVhZCBhbmQgd3JpdGUsUmVhZCBhbmQgd3JpdGUsUmVhZCBhbmQgd3JpdGUsUmVhZCBhbmQgd3JpdGU=::QWNjZXNzIE1vZGU="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5pdEZsYXNoQ29udGVudA==::ZmFsc2U=::SW5pdGlhbGl6ZSBmbGFzaCBjb250ZW50"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU=::cV9zeXNfb25jaGlwX2ZsYXNo::YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSVF9OQU1F::MTBNNTBEQUY0ODRDNkdFUw==::UEFSVF9OQU1F"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19SQVRF::NTAwMDAwMDA=::QVVUT19DTE9DS19SQVRF"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0lE::NTA=::REVWSUNFX0lE"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMV9TVEFSVF9BRERS::MA==::U0VDVE9SMV9TVEFSVF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMV9FTkRfQUREUg==::ODE5MQ==::U0VDVE9SMV9FTkRfQUREUg=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMl9TVEFSVF9BRERS::ODE5Mg==::U0VDVE9SMl9TVEFSVF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMl9FTkRfQUREUg==::MTYzODM=::U0VDVE9SMl9FTkRfQUREUg=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SM19TVEFSVF9BRERS::MTYzODQ=::U0VDVE9SM19TVEFSVF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SM19FTkRfQUREUg==::MTE0Njg3::U0VDVE9SM19FTkRfQUREUg=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNF9TVEFSVF9BRERS::MTE0Njg4::U0VDVE9SNF9TVEFSVF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNF9FTkRfQUREUg==::MTg4NDE1::U0VDVE9SNF9FTkRfQUREUg=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNV9TVEFSVF9BRERS::MTg4NDE2::U0VDVE9SNV9TVEFSVF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNV9FTkRfQUREUg==::MzYwNDQ3::U0VDVE9SNV9FTkRfQUREUg=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUlOX1ZBTElEX0FERFI=::MA==::TUlOX1ZBTElEX0FERFI="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1ZBTElEX0FERFI=::MzYwNDQ3::TUFYX1ZBTElEX0FERFI="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUlOX1VGTV9WQUxJRF9BRERS::MA==::TUlOX1VGTV9WQUxJRF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1VGTV9WQUxJRF9BRERS::MTE0Njg3::TUFYX1VGTV9WQUxJRF9BRERS"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMV9NQVA=::MQ==::U0VDVE9SMV9NQVA="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SMl9NQVA=::Mg==::U0VDVE9SMl9NQVA="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SM19NQVA=::Mw==::U0VDVE9SM19NQVA="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNF9NQVA=::NA==::U0VDVE9SNF9NQVA="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SNV9NQVA=::NQ==::U0VDVE9SNV9NQVA="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQU5HRTFfRU5EX0FERFI=::MzYwNDQ3::QUREUl9SQU5HRTFfRU5EX0FERFI="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQU5HRTJfRU5EX0FERFI=::MzYwNDQ3::QUREUl9SQU5HRTJfRU5EX0FERFI="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQU5HRTFfT0ZGU0VU::MjA0OA==::QUREUl9SQU5HRTFfT0ZGU0VU"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQU5HRTJfT0ZGU0VU::MA==::QUREUl9SQU5HRTJfT0ZGU0VU"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQU5HRTNfT0ZGU0VU::MA==::QUREUl9SQU5HRTNfT0ZGU0VU"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZNTV9EQVRBX0FERFJfV0lEVEg=::MTk=::QVZNTV9EQVRBX0FERFJfV0lEVEg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZNTV9EQVRBX0RBVEFfV0lEVEg=::MzI=::QVZNTV9EQVRBX0RBVEFfV0lEVEg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZNTV9EQVRBX0JVUlNUQ09VTlRfV0lEVEg=::NA==::QVZNTV9EQVRBX0JVUlNUQ09VTlRfV0lEVEg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VDVE9SX1JFQURfUFJPVEVDVElPTl9NT0RF::MA==::U0VDVE9SX1JFQURfUFJPVEVDVElPTl9NT0RF"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfU0VRX1JFQURfREFUQV9DT1VOVA==::NA==::RkxBU0hfU0VRX1JFQURfREFUQV9DT1VOVA=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfQUREUl9BTElHTk1FTlRfQklUUw==::Mg==::RkxBU0hfQUREUl9BTElHTk1FTlRfQklUUw=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfUkVBRF9DWUNMRV9NQVhfSU5ERVg=::NQ==::RkxBU0hfUkVBRF9DWUNMRV9NQVhfSU5ERVg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY::MTI=::RkxBU0hfUkVTRVRfQ1lDTEVfTUFYX0lOREVY"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA==::NjA=::RkxBU0hfQlVTWV9USU1FT1VUX0NZQ0xFX01BWF9JTkRFWA=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::MTc1MDAwMDA=::RkxBU0hfRVJBU0VfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg=::MTUyNTA=::RkxBU0hfV1JJVEVfVElNRU9VVF9DWUNMRV9NQVhfSU5ERVg="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSQUxMRUxfTU9ERQ==::dHJ1ZQ==::UEFSQUxMRUxfTU9ERQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9BTkRfV1JJVEVfTU9ERQ==::dHJ1ZQ==::UkVBRF9BTkRfV1JJVEVfTU9ERQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JBUFBJTkdfQlVSU1RfTU9ERQ==::ZmFsc2U=::V1JBUFBJTkdfQlVSU1RfTU9ERQ=="
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRFVBTF9CT09U::RmFsc2U=::SVNfRFVBTF9CT09U"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVJBTV9TS0lQ::VHJ1ZQ==::SVNfRVJBTV9TS0lQ"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfQ09NUFJFU1NFRF9JTUFHRQ==::RmFsc2U=::SVNfQ09NUFJFU1NFRF9JTUFHRQ=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbXNnZG1hX3R4"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TW9kdWxhciBTY2F0dGVyLUdhdGhlciBETUEgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "TW9kdWxhciBTR0RNQSB3aXRoIGNvbmZpZ3VyYXRpb24gbW9kZSBvZiBBdmFsb24tTU0gdG8gQXZhbG9uLU1NLCBBdmFsb24tTU0gdG8gQXZhbG9uLVNULCBvciBBdmFsb24tU1QgdG8gQXZhbG9uLU1NIGRhdGEgcGF0aHM="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TU9ERQ==::MQ==::RE1BIE1vZGU="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::RGF0YSBXaWR0aA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJWF9BRERSRVNTX1dJRFRI::MA==::VXNlIHByZS1kZXRlcm1pbmVkIG1hc3RlciBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9GSUZPX0RFUFRI::MzI=::RGF0YSBQYXRoIEZJRk8gRGVwdGg="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9GSUZPX0RFUFRI::OA==::RGVzY3JpcHRvciBGSUZPIERlcHRo"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEU=::MjA0OA==::TWF4aW11bSBUcmFuc2ZlciBMZW5ndGg="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBTlNGRVJfVFlQRQ==::QWxpZ25lZCBBY2Nlc3Nlcw==::VHJhbnNmZXIgVHlwZQ=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfRU5BQkxF::MA==::QnVyc3QgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5IQU5DRURfRkVBVFVSRVM=::MA==::RW5hYmxlIEV4dGVuZGVkIEZlYXR1cmUgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX0VOQUJMRV9ERVJJVkVE::MA==::U3RyaWRlIEVuYWJsZQ=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRQ==::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRV9ERVJJVkVE::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxF::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxFX0RFUklWRUQ=::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MQ==::RXJyb3IgV2lkdGg="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9FTkFCTEU=::MA==::Q2hhbm5lbCBFbmFibGU="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9FTkFCTEVfREVSSVZFRA==::MA==::Q2hhbm5lbCBFbmFibGU="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9FTkFCTEU=::MQ==::RW5hYmxlcyBQcmUtRmV0Y2hpbmcgbW9kdWxl"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9SRUFEX0JVUlNUX0VOQUJMRQ==::MA==::RW5hYmxlIGJ1cnN0aW5nIG9uIGRlc2NyaXB0b3IgcmVhZCBtYXN0ZXI="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9EQVRBX1dJRFRI::MzI=::RGF0YSBXaWR0aCBvZiBEZXNjcmlwdG9yIHJlYWQvd3JpdGUgbWFzdGVyIGRhdGEgcGF0aC4="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9SRUFEX0FERFJFU1NfTUFQ::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9SRUFEX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gMjg=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9XUklURV9BRERSRVNTX1dJRFRI::QWRkcmVzc1dpZHRoID0gLTE=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1JFQURfTUFTVEVSX0FERFJFU1NfTUFQ::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1JFQURfTUFTVEVSX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gMjk=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1dSSVRFX01BU1RFUl9BRERSRVNTX01BUA==::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1dSSVRFX01BU1RFUl9BRERSRVNTX1dJRFRI::QWRkcmVzc1dpZHRoID0gMjk=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_NAME "cmVhZF9tYXN0ZXI="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "UmVhZCBNYXN0ZXIgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QSBtb2R1bGUgcmVzcG9uc2libGUgZm9yIHN0cmVhbWluZyBkYXRhIGZyb20gbWVtb3J5"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::RGF0YSBXaWR0aA=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TEVOR1RIX1dJRFRI::MTI=::TGVuZ3RoIFdpZHRo"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSA==::MzI=::RklGTyBEZXB0aA=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJWF9BRERSRVNTX1dJRFRI::MA==::VXNlIHByZS1kZXRlcm1pbmVkIG1hc3RlciBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX0VOQUJMRQ==::MA==::U3RyaWRlIEFkZHJlc3NpbmcgRW5hYmxl"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfRU5BQkxF::MA==::QnVyc3QgRW5hYmxl"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBTlNGRVJfVFlQRQ==::QWxpZ25lZCBBY2Nlc3Nlcw==::VHJhbnNmZXIgVHlwZQ=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRQ==::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxF::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MQ==::RXJyb3IgV2lkdGg="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9FTkFCTEU=::MA==::Q2hhbm5lbCBFbmFibGU="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEVfV0lEVEg=::NA==::QllURV9FTkFCTEVfV0lEVEg="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEVfV0lEVEhfTE9HMg==::Mg==::QllURV9FTkFCTEVfV0lEVEhfTE9HMg=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19BRERSRVNTX1dJRFRI::Mjg=::QVVUT19BRERSRVNTX1dJRFRI"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUkVTU19XSURUSA==::Mjg=::QUREUkVTU19XSURUSA=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSF9MT0cy::NQ==::RklGT19ERVBUSF9MT0cy"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lNQk9MX1dJRFRI::OA==::U1lNQk9MX1dJRFRI"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX1NZTUJPTFM=::NA==::TlVNQkVSX09GX1NZTUJPTFM="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX1NZTUJPTFNfTE9HMg==::Mg==::TlVNQkVSX09GX1NZTUJPTFNfTE9HMg=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::TUFYX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VU5BTElHTkVEX0FDQ0VTU0VTX0VOQUJMRQ==::MA==::VU5BTElHTkVEX0FDQ0VTU0VTX0VOQUJMRQ=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "T05MWV9GVUxMX0FDQ0VTU19FTkFCTEU=::MA==::T05MWV9GVUxMX0FDQ0VTU19FTkFCTEU="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA==::MA==::QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ==::MA==::UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ=="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0NPVU5U::MQ==::TUFYX0JVUlNUX0NPVU5U"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19TUEVFRF9PUFRJTUlaQVRJT04=::MQ==::RklGT19TUEVFRF9PUFRJTUlaQVRJT04="
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX1dJRFRI::MQ==::U1RSSURFX1dJRFRI"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX21zZ2RtYV9wcmVmZXRjaGVy"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TW9kdWxhciBTR0RNQSBQcmVmZXRjaGVyIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "U0dETUEgcHJlZmV0Y2hpbmcgYmxvY2s="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5IQU5DRURfRkVBVFVSRVM=::MA==::RW5hYmxlIEV4dGVuZGVkIEZlYXR1cmUgU3VwcG9ydA=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1JFQURfQlVSU1Q=::MA==::RW5hYmxlIGJ1cnN0aW5nIG9uIGRlc2NyaXB0b3IgcmVhZCBtYXN0ZXI="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1JFQURfQlVSU1RfQ09VTlQ=::MQ==::TUFYX1JFQURfQlVSU1RfQ09VTlQ="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1JFQURfQlVSU1RfQ09VTlRfV0lEVEg=::MQ==::TUFYX1JFQURfQlVSU1RfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::RGF0YSBXaWR0aCBvZiBEZXNjcmlwdG9yIHJlYWQvd3JpdGUgbWFzdGVyIGRhdGEgcGF0aA=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9CWVRFRU5BQkxFX1dJRFRI::NA==::REFUQV9CWVRFRU5BQkxFX1dJRFRI"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9XSURUSA==::MTI4::REVTQ1JJUFRPUl9XSURUSA=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19BRERSRVNTX1dJRFRI::Mjk=::QVVUT19BRERSRVNTX1dJRFRI"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUkVTU19XSURUSA==::Mjk=::QUREUkVTU19XSURUSA=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "R1VJX0RFU0NSSVBUT1JfRklGT19ERVBUSA==::OA==::RGVzY3JpcHRvciBGSUZPIERlcHRo"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTUE9OU0VfRklGT19ERVBUSA==::MTY=::UkVTUE9OU0VfRklGT19ERVBUSA=="
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTUE9OU0VfRklGT19ERVBUSF9MT0cy::NA==::UkVTUE9OU0VfRklGT19ERVBUSF9MT0cy"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJWF9BRERSRVNTX1dJRFRI::MA==::VXNlIHByZS1kZXRlcm1pbmVkIG1hc3RlciBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_NAME "ZGlzcGF0Y2hlcg=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TW9kdWxhciBTR0RNQSBEaXNwYXRjaGVyIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "U0dETUEgc2NoZWR1bGluZyBibG9jaw=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9VU0VfQ0FTRQ==::MQ==::RW5hYmxlcyBQcmUtRmV0Y2hpbmcgdXNlIGNhc2Vz"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TU9ERQ==::Mg==::VHJhbnNmZXIgTW9kZQ=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTUE9OU0VfUE9SVA==::MQ==::UkVTUE9OU0VfUE9SVA=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9JTlRFUkZBQ0U=::MQ==::REVTQ1JJUFRPUl9JTlRFUkZBQ0U="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9GSUZPX0RFUFRI::OA==::RGVzY3JpcHRvciBGSUZPIERlcHRo"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5IQU5DRURfRkVBVFVSRVM=::MA==::RW5hYmxlIEV4dGVuZGVkIEZlYXR1cmUgU3VwcG9ydA=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9XSURUSA==::MTI4::REVTQ1JJUFRPUl9XSURUSA=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9CWVRFRU5BQkxFX1dJRFRI::MTY=::REVTQ1JJUFRPUl9CWVRFRU5BQkxFX1dJRFRI"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJFU1NfV0lEVEg=::Mw==::Q1NSX0FERFJFU1NfV0lEVEg="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::REFUQV9XSURUSA=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9GSUZPX0RFUFRI::MzI=::REFUQV9GSUZPX0RFUFRI"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEU=::MjA0OA==::TUFYX0JZVEU="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBTlNGRVJfVFlQRQ==::QWxpZ25lZCBBY2Nlc3Nlcw==::VFJBTlNGRVJfVFlQRQ=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfRU5BQkxF::MA==::QlVSU1RfRU5BQkxF"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0NPVU5U::Mg==::TUFYX0JVUlNUX0NPVU5U"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA==::MA==::QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX0VOQUJMRQ==::MA==::U1RSSURFX0VOQUJMRQ=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1NUUklERQ==::MQ==::TUFYX1NUUklERQ=="
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ==::MA==::UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfbXNnZG1hX3J4"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TW9kdWxhciBTY2F0dGVyLUdhdGhlciBETUEgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "TW9kdWxhciBTR0RNQSB3aXRoIGNvbmZpZ3VyYXRpb24gbW9kZSBvZiBBdmFsb24tTU0gdG8gQXZhbG9uLU1NLCBBdmFsb24tTU0gdG8gQXZhbG9uLVNULCBvciBBdmFsb24tU1QgdG8gQXZhbG9uLU1NIGRhdGEgcGF0aHM="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TU9ERQ==::Mg==::RE1BIE1vZGU="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::RGF0YSBXaWR0aA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJWF9BRERSRVNTX1dJRFRI::MA==::VXNlIHByZS1kZXRlcm1pbmVkIG1hc3RlciBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9GSUZPX0RFUFRI::MzI=::RGF0YSBQYXRoIEZJRk8gRGVwdGg="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVTQ1JJUFRPUl9GSUZPX0RFUFRI::OA==::RGVzY3JpcHRvciBGSUZPIERlcHRo"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEU=::MjA0OA==::TWF4aW11bSBUcmFuc2ZlciBMZW5ndGg="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBTlNGRVJfVFlQRQ==::QWxpZ25lZCBBY2Nlc3Nlcw==::VHJhbnNmZXIgVHlwZQ=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfRU5BQkxF::MA==::QnVyc3QgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5IQU5DRURfRkVBVFVSRVM=::MA==::RW5hYmxlIEV4dGVuZGVkIEZlYXR1cmUgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX0VOQUJMRV9ERVJJVkVE::MA==::U3RyaWRlIEVuYWJsZQ=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRQ==::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRV9ERVJJVkVE::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxF::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxFX0RFUklWRUQ=::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::Ng==::RXJyb3IgV2lkdGg="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9FTkFCTEVfREVSSVZFRA==::MA==::Q2hhbm5lbCBFbmFibGU="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9FTkFCTEU=::MQ==::RW5hYmxlcyBQcmUtRmV0Y2hpbmcgbW9kdWxl"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9SRUFEX0JVUlNUX0VOQUJMRQ==::MA==::RW5hYmxlIGJ1cnN0aW5nIG9uIGRlc2NyaXB0b3IgcmVhZCBtYXN0ZXI="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFRkVUQ0hFUl9EQVRBX1dJRFRI::MzI=::RGF0YSBXaWR0aCBvZiBEZXNjcmlwdG9yIHJlYWQvd3JpdGUgbWFzdGVyIGRhdGEgcGF0aC4="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9SRUFEX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gLTE=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9XUklURV9BRERSRVNTX01BUA==::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19NTV9XUklURV9BRERSRVNTX1dJRFRI::QWRkcmVzc1dpZHRoID0gMjg=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1JFQURfTUFTVEVSX0FERFJFU1NfTUFQ::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1JFQURfTUFTVEVSX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gMjk=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1dSSVRFX01BU1RFUl9BRERSRVNTX01BUA==::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgLz48L2FkZHJlc3MtbWFwPg==::QXV0byBBRERSRVNTX01BUA=="
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVNDUklQVE9SX1dSSVRFX01BU1RFUl9BRERSRVNTX1dJRFRI::QWRkcmVzc1dpZHRoID0gMjk=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_NAME "d3JpdGVfbWFzdGVy"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "V3JpdGUgTWFzdGVyIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QSBtb2R1bGUgcmVzcG9uc2libGUgZm9yIHdyaXRpbmcgc3RyZWFtaW5nIGRhdGEgdG8gbWVtb3J5"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MzI=::RGF0YSBXaWR0aA=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TEVOR1RIX1dJRFRI::MTI=::TGVuZ3RoIFdpZHRo"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSA==::MzI=::RklGTyBEZXB0aA=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZJWF9BRERSRVNTX1dJRFRI::MA==::VXNlIHByZS1kZXRlcm1pbmVkIG1hc3RlciBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX0VOQUJMRQ==::MA==::U3RyaWRlIEFkZHJlc3NpbmcgRW5hYmxl"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfRU5BQkxF::MA==::QnVyc3QgRW5hYmxl"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBTlNGRVJfVFlQRQ==::QWxpZ25lZCBBY2Nlc3Nlcw==::VHJhbnNmZXIgVHlwZQ=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0VUX0VOQUJMRQ==::MQ==::UGFja2V0IFN1cHBvcnQgRW5hYmxl"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfRU5BQkxF::MQ==::RXJyb3IgRW5hYmxl"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::Ng==::RXJyb3IgV2lkdGg="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEVfV0lEVEg=::NA==::QllURV9FTkFCTEVfV0lEVEg="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEVfV0lEVEhfTE9HMg==::Mg==::QllURV9FTkFCTEVfV0lEVEhfTE9HMg=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19BRERSRVNTX1dJRFRI::Mjg=::QVVUT19BRERSRVNTX1dJRFRI"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUkVTU19XSURUSA==::Mjg=::QUREUkVTU19XSURUSA=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSF9MT0cy::NQ==::RklGT19ERVBUSF9MT0cy"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lNQk9MX1dJRFRI::OA==::U1lNQk9MX1dJRFRI"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX1NZTUJPTFM=::NA==::TlVNQkVSX09GX1NZTUJPTFM="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX1NZTUJPTFNfTE9HMg==::Mg==::TlVNQkVSX09GX1NZTUJPTFNfTE9HMg=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::TUFYX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "VU5BTElHTkVEX0FDQ0VTU0VTX0VOQUJMRQ==::MA==::VU5BTElHTkVEX0FDQ0VTU0VTX0VOQUJMRQ=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "T05MWV9GVUxMX0FDQ0VTU19FTkFCTEU=::MA==::T05MWV9GVUxMX0FDQ0VTU19FTkFCTEU="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA==::MA==::QlVSU1RfV1JBUFBJTkdfU1VQUE9SVA=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ==::MA==::UFJPR1JBTU1BQkxFX0JVUlNUX0VOQUJMRQ=="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0NPVU5U::MQ==::TUFYX0JVUlNUX0NPVU5U"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklGT19TUEVFRF9PUFRJTUlaQVRJT04=::MQ==::RklGT19TUEVFRF9PUFRJTUlaQVRJT04="
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RSSURFX1dJRFRI::MQ==::U1RSSURFX1dJRFRI"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNUVUFMX0JZVEVTX1RSQU5TRkVSUkVEX1dJRFRI::MTM=::QUNUVUFMX0JZVEVTX1RSQU5TRkVSUkVEX1dJRFRI"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZnJhbWVfdGltZXI="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "SW50ZXJ2YWwgVGltZXIgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "YWx3YXlzUnVu::ZmFsc2U=::Tm8gU3RhcnQvU3RvcCBjb250cm9sIGJpdHM="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y291bnRlclNpemU=::MzI=::Q291bnRlciBTaXpl"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zml4ZWRQZXJpb2Q=::ZmFsc2U=::Rml4ZWQgcGVyaW9k"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9k::NTAwMA==::UGVyaW9k"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHM=::Q0xPQ0tT::VW5pdHM="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRPdXRwdXQ=::ZmFsc2U=::U3lzdGVtIHJlc2V0IG9uIHRpbWVvdXQgKFdhdGNoZG9nKQ=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c25hcHNob3Q=::ZmFsc2U=::UmVhZGFibGUgc25hcHNob3Q="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGltZW91dFB1bHNlT3V0cHV0::dHJ1ZQ==::VGltZW91dCBwdWxzZSAoMSBjbG9jayB3aWRlKQ=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3lzdGVtRnJlcXVlbmN5::NTAwMDAwMDA=::c3lzdGVtRnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "d2F0Y2hkb2dQdWxzZQ==::Mg==::V2F0Y2hkb2cgVGltZXIgUHVsc2UgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGltZXJQcmVzZXQ=::Q1VTVE9N::UHJlc2V0cw=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHNTdHJpbmc=::Y2xvY2tz::cGVyaW9kVW5pdHNTdHJpbmc="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dmFsdWVJblNlY29uZA==::MC4w::dmFsdWVJblNlY29uZA=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "bG9hZFZhbHVl::NDk5OQ==::bG9hZFZhbHVl"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXVsdA==::Mi4wRS04::bXVsdA=="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlja3NQZXJTZWM=::MTAwMDAuMA==::dGlja3NQZXJTZWM="
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2xhdmVfYWRkcmVzc193aWR0aA==::Mw==::c2xhdmVfYWRkcmVzc193aWR0aA=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXh0X2ZsYXNo"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBRVUFEIFNQSSBDb250cm9sbGVyIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VGhpcyBjb21wb25lbnQgaXMgYSBnZW5lcmljIFFTUEkgY29udHJvbGxlciB3aGljaCBhbGxvd3MgdXNlciB0byBhY2Nlc3MgYW55IFFTUEkgZGV2aWNlcw=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "VU5JUVVFX0lE::cV9zeXNfZXh0X2ZsYXNo::VU5JUVVFX0lE"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xrRnJlcQ==::MA==::Y2xrRnJlcQ=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NfV0lEVEg=::MQ==::Q1NfV0lEVEg="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9XSURUSA==::MjQ=::QUREUl9XSURUSA=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNJX1dJRFRI::NA==::QVNJX1dJRFRI"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNNSV9BRERSX1dJRFRI::MzI=::QVNNSV9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFXzRCWVRFX0FERFI=::MQ==::RW5hYmxlIDQtYnl0ZSBhZGRyZXNzaW5nIG1vZGU="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RERBU0k=::MQ==::RGlzYWJsZSBkZWRpY2F0ZWQgQWN0aXZlIFNlcmlhbCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfVFlQRQ==::TWljcm9uNTEy::Q29uZmlndXJhdGlvbiBkZXZpY2UgdHlwZQ=="
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fTU9ERQ==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXh0X2ZsYXNoX2VwY3FfY29udHJvbGxlcl9pbnN0YW5jZV9uYW1l"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "cV9zeXNfZXh0X2ZsYXNoX2VwY3FfY29udHJvbGxlcl9pbnN0YW5jZV9uYW1l"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::Tm9uZQ==::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9XSURUSA==::MjQ=::QUREUl9XSURUSA=="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNNSV9BRERSX1dJRFRI::MzI=::QVNNSV9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNJX1dJRFRI::NA==::QVNJX1dJRFRI"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NfV0lEVEg=::MQ==::Q1NfV0lEVEg="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hJUF9TRUxT::MQ==::TnVtYmVyIG9mIENoaXAgU2VsZWN0cyB1c2Vk"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RERBU0k=::MQ==::RGlzYWJsZSBkZWRpY2F0ZWQgQWN0aXZlIFNlcmlhbCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFXzRCWVRFX0FERFI=::MQ==::RW5hYmxlIDQtYnl0ZSBhZGRyZXNzaW5nIG1vZGU="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfVFlQRQ==::RVBDUUw1MTI=::Q29uZmlndXJhdGlvbiBkZXZpY2UgdHlwZQ=="
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fTU9ERQ==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2VwY3FfY29udHJvbGxlcl9hcmI="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "RVBDUSBTZXJpYWwgRmxhc2ggY29udHJvbGxlciBjb3JlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VGhpcyBjb21wb25lbnQgaXMgYSBzZXJpYWwgZmxhc2ggY29udHJvbGxlciB3aGljaCBhbGxvd3MgdXNlciB0byBhY2Nlc3MgSW50ZWwgRlBHQSBFUENRIGRldmljZXM="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::Tm9uZQ==::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9XSURUSA==::MjQ=::QUREUl9XSURUSA=="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNNSV9BRERSX1dJRFRI::MzI=::QVNNSV9BRERSX1dJRFRI"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNJX1dJRFRI::NA==::QVNJX1dJRFRI"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NfV0lEVEg=::MQ==::Q1NfV0lEVEg="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0hJUF9TRUxT::MQ==::TnVtYmVyIG9mIENoaXAgU2VsZWN0cyB1c2Vk"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "RERBU0k=::MQ==::RGlzYWJsZSBkZWRpY2F0ZWQgQWN0aXZlIFNlcmlhbCBpbnRlcmZhY2U="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFXzRCWVRFX0FERFI=::MQ==::RW5hYmxlIDQtYnl0ZSBhZGRyZXNzaW5nIG1vZGU="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfVFlQRQ==::RVBDUUw1MTI=::Q29uZmlndXJhdGlvbiBkZXZpY2UgdHlwZQ=="
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fTU9ERQ==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXh0X2ZsYXNoX2FzbWlfcGFyYWxsZWxfaW5zdGFuY2VfbmFtZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "cV9zeXNfZXh0X2ZsYXNoX2FzbWlfcGFyYWxsZWxfaW5zdGFuY2VfbmFtZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::QXJyaWEgVg==::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0JYX0FVVE9fQkxBQ0tCT1g=::QUxM::Q0JYX0FVVE9fQkxBQ0tCT1g="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVBDU19UWVBF::RVBDUUw1MTI=::Q29uZmlndXJhdGlvbiBkZXZpY2UgdHlwZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfcmRpZA==::dHJ1ZQ==::VXNlICdyZWFkX3JkaWQnIGFuZCByZGlkX291dCcgcG9ydHM="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfc3RhdHVz::dHJ1ZQ==::VXNlICdyZWFkX3N0YXR1cycgcG9ydA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfYWRkcmVzcw==::ZmFsc2U=::VXNlICdyZWFkX2FkZHJlc3MnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2Zhc3RfcmVhZA==::dHJ1ZQ==::VXNlICdmYXN0X3JlYWQnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfZHVtbXljbGs=::dHJ1ZQ==::UmVhZCBkZXZpY2UgZHVtbXkgY2xvY2s="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3dyaXRl::dHJ1ZQ==::RW5hYmxlIHdyaXRlIG9wZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3dyZW4=::dHJ1ZQ==::VXNlICd3cmVuJyBwb3J0"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NpbmdsZV93cml0ZQ==::ZmFsc2U=::U2luZ2xlIGJ5dGUgd3JpdGU="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3BhZ2Vfd3JpdGU=::dHJ1ZQ==::UGFnZSB3cml0ZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFHRV9TSVpF::MjU2::J3BhZ2Ugd3JpdGUnIHNpemU="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9lYWI=::ZmFsc2U=::U3RvcmUgJ3BhZ2Ugd3JpdGUnIGRhdGEgaW4gbG9naWMgZWxlbWVudHM="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2RpZV9lcmFzZQ==::ZmFsc2U=::VXNlICdkaWVfZXJhc2UnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NlY3Rvcl9lcmFzZQ==::dHJ1ZQ==::VXNlICdzZWN0b3JfZXJhc2UnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NlY3Rvcl9wcm90ZWN0::dHJ1ZQ==::VXNlICdzZWN0b3JfcHJvdGVjdCcgcG9ydA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2V4NGJfYWRkcg==::ZmFsc2U=::VXNlICdleDRiX2FkZHInIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hc21pYmxvY2s=::dHJ1ZQ==::RGlzYWJsZSBkZWRpY2F0ZWQgQWN0aXZlIFNlcmlhbCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9CVUxLX0VSQVNF::UE9SVF9VTlVTRUQ=::UE9SVF9CVUxLX0VSQVNF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9ESUVfRVJBU0U=::UE9SVF9VTlVTRUQ=::UE9SVF9ESUVfRVJBU0U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9FTjRCX0FERFI=::UE9SVF9VU0VE::UE9SVF9FTjRCX0FERFI="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9FWDRCX0FERFI=::UE9SVF9VTlVTRUQ=::UE9SVF9FWDRCX0FERFI="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9GQVNUX1JFQUQ=::UE9SVF9VU0VE::UE9SVF9GQVNUX1JFQUQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTExFR0FMX0VSQVNF::UE9SVF9VU0VE::UE9SVF9JTExFR0FMX0VSQVNF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTExFR0FMX1dSSVRF::UE9SVF9VU0VE::UE9SVF9JTExFR0FMX1dSSVRF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRElEX09VVA==::UE9SVF9VU0VE::UE9SVF9SRElEX09VVA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX0FERFJFU1M=::UE9SVF9VTlVTRUQ=::UE9SVF9SRUFEX0FERFJFU1M="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX0RVTU1ZQ0xL::UE9SVF9VU0VE::UE9SVF9SRUFEX0RVTU1ZQ0xL"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1JESUQ=::UE9SVF9VU0VE::UE9SVF9SRUFEX1JESUQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1NJRA==::UE9SVF9VTlVTRUQ=::UE9SVF9SRUFEX1NJRA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1NUQVRVUw==::UE9SVF9VU0VE::UE9SVF9SRUFEX1NUQVRVUw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TRUNUT1JfRVJBU0U=::UE9SVF9VU0VE::UE9SVF9TRUNUT1JfRVJBU0U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TRUNUT1JfUFJPVEVDVA==::UE9SVF9VU0VE::UE9SVF9TRUNUT1JfUFJPVEVDVA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TSElGVF9CWVRFUw==::UE9SVF9VU0VE::UE9SVF9TSElGVF9CWVRFUw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9XUkVO::UE9SVF9VU0VE::UE9SVF9XUkVO"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9XUklURQ==::UE9SVF9VU0VE::UE9SVF9XUklURQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JJVEVfRFVNTVlfQ0xL::MA==::V1JJVEVfRFVNTVlfQ0xL"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VBQg==::T04=::VVNFX0VBQg=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FTTUlCTE9DSw==::T0ZG::VVNFX0FTTUlCTE9DSw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfUlNUUElO::VFJVRQ==::RkxBU0hfUlNUUElO"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NJTQ==::dHJ1ZQ==::RW5hYmxlIHNpbXVsYXRpb24="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXh0X2ZsYXNoX2FzbWlfcGFyYWxsZWxfaW5zdGFuY2VfbmFtZV9hc21pX3BhcmFsbGVsX2luc3RhbmNlX25hbWU="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QVNNSSBQYXJhbGxlbCBJbnRlbCBGUEdBIElQ"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VGhlIEFsdGVyYSBBU01JIFBhcmFsbGVsIG1lZ2FmdW5jdGlvbiBwcm92aWRlcyBhY2Nlc3MgdG8gZXJhc2FibGUgIHByb2dyYW1tYWJsZSBjb25maWd1cmFibGUgc2VyaWFsIChFUENTKSBhbmQgcXVhZC1zZXJpYWwgY29uZmlndXJhdGlvbiAgKEVQQ1EpIGRldmljZXMgdGhyb3VnaCBwYXJhbGxlbCBkYXRhIGlucHV0IGFuZCBvdXRwdXQgcG9ydHMu"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::QXJyaWEgVg==::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0JYX0FVVE9fQkxBQ0tCT1g=::QUxM::Q0JYX0FVVE9fQkxBQ0tCT1g="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVBDU19UWVBF::RVBDUUw1MTI=::Q29uZmlndXJhdGlvbiBkZXZpY2UgdHlwZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfcmRpZA==::dHJ1ZQ==::VXNlICdyZWFkX3JkaWQnIGFuZCByZGlkX291dCcgcG9ydHM="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfc3RhdHVz::dHJ1ZQ==::VXNlICdyZWFkX3N0YXR1cycgcG9ydA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfYWRkcmVzcw==::ZmFsc2U=::VXNlICdyZWFkX2FkZHJlc3MnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2Zhc3RfcmVhZA==::dHJ1ZQ==::VXNlICdmYXN0X3JlYWQnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3JlYWRfZHVtbXljbGs=::dHJ1ZQ==::UmVhZCBkZXZpY2UgZHVtbXkgY2xvY2s="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3dyaXRl::dHJ1ZQ==::RW5hYmxlIHdyaXRlIG9wZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3dyZW4=::dHJ1ZQ==::VXNlICd3cmVuJyBwb3J0"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NpbmdsZV93cml0ZQ==::ZmFsc2U=::U2luZ2xlIGJ5dGUgd3JpdGU="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3BhZ2Vfd3JpdGU=::dHJ1ZQ==::UGFnZSB3cml0ZQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFHRV9TSVpF::MjU2::J3BhZ2Ugd3JpdGUnIHNpemU="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9lYWI=::ZmFsc2U=::U3RvcmUgJ3BhZ2Ugd3JpdGUnIGRhdGEgaW4gbG9naWMgZWxlbWVudHM="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2RpZV9lcmFzZQ==::ZmFsc2U=::VXNlICdkaWVfZXJhc2UnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NlY3Rvcl9lcmFzZQ==::dHJ1ZQ==::VXNlICdzZWN0b3JfZXJhc2UnIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NlY3Rvcl9wcm90ZWN0::dHJ1ZQ==::VXNlICdzZWN0b3JfcHJvdGVjdCcgcG9ydA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2V4NGJfYWRkcg==::ZmFsc2U=::VXNlICdleDRiX2FkZHInIHBvcnQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hc21pYmxvY2s=::dHJ1ZQ==::RGlzYWJsZSBkZWRpY2F0ZWQgQWN0aXZlIFNlcmlhbCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9CVUxLX0VSQVNF::UE9SVF9VTlVTRUQ=::UE9SVF9CVUxLX0VSQVNF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9ESUVfRVJBU0U=::UE9SVF9VTlVTRUQ=::UE9SVF9ESUVfRVJBU0U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9FTjRCX0FERFI=::UE9SVF9VU0VE::UE9SVF9FTjRCX0FERFI="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9FWDRCX0FERFI=::UE9SVF9VTlVTRUQ=::UE9SVF9FWDRCX0FERFI="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9GQVNUX1JFQUQ=::UE9SVF9VU0VE::UE9SVF9GQVNUX1JFQUQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTExFR0FMX0VSQVNF::UE9SVF9VU0VE::UE9SVF9JTExFR0FMX0VSQVNF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTExFR0FMX1dSSVRF::UE9SVF9VU0VE::UE9SVF9JTExFR0FMX1dSSVRF"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRElEX09VVA==::UE9SVF9VU0VE::UE9SVF9SRElEX09VVA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX0FERFJFU1M=::UE9SVF9VTlVTRUQ=::UE9SVF9SRUFEX0FERFJFU1M="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX0RVTU1ZQ0xL::UE9SVF9VU0VE::UE9SVF9SRUFEX0RVTU1ZQ0xL"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1JESUQ=::UE9SVF9VU0VE::UE9SVF9SRUFEX1JESUQ="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1NJRA==::UE9SVF9VTlVTRUQ=::UE9SVF9SRUFEX1NJRA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9SRUFEX1NUQVRVUw==::UE9SVF9VU0VE::UE9SVF9SRUFEX1NUQVRVUw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TRUNUT1JfRVJBU0U=::UE9SVF9VU0VE::UE9SVF9TRUNUT1JfRVJBU0U="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TRUNUT1JfUFJPVEVDVA==::UE9SVF9VU0VE::UE9SVF9TRUNUT1JfUFJPVEVDVA=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TSElGVF9CWVRFUw==::UE9SVF9VU0VE::UE9SVF9TSElGVF9CWVRFUw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9XUkVO::UE9SVF9VU0VE::UE9SVF9XUkVO"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9XUklURQ==::UE9SVF9VU0VE::UE9SVF9XUklURQ=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JJVEVfRFVNTVlfQ0xL::MA==::V1JJVEVfRFVNTVlfQ0xL"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0VBQg==::T04=::VVNFX0VBQg=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FTTUlCTE9DSw==::T0ZG::VVNFX0FTTUlCTE9DSw=="
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxBU0hfUlNUUElO::VFJVRQ==::RkxBU0hfUlNUUElO"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NJTQ==::dHJ1ZQ==::RW5hYmxlIHNpbXVsYXRpb24="
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXh0X2ZsYXNoX3NvZnRfYXNtaWJsb2NrX2luc3RhbmNlX25hbWU="
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "cV9zeXNfZXh0X2ZsYXNoX3NvZnRfYXNtaWJsb2NrX2luc3RhbmNlX25hbWU="
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fTU9ERQ==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NfV0lEVEg=::MQ==::Q1NfV0lEVEg="
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_NAME "c29mdF9hc21pYmxvY2s="
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFNPRlQgQVNNSUJMT0NL"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VGhpcyBjb21wb25lbnQgY29ubmVjdHMgdG8gQWx0ZXJhIEVQQ1EgY29udHJvbGxlciBzbyB0aGF0IHRoZSBRU1BJIHNpZ25hbCBjYW4gYmUgdXNlZCBhcyBnZW5lcmFsIHB1cnBvc2UgcGlu"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fTU9ERQ==::UVVBRA==::Q2hvb3NlIEkvTyBtb2Rl"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NfV0lEVEg=::MQ==::Q1NfV0lEVEg="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZXRoX3RzZQ=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "VHJpcGxlLVNwZWVkIEV0aGVybmV0IEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "VHJpcGxlIFNwZWVkIEV0aGVybmV0IEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX3BhZGRpbmc=::dHJ1ZQ==::ZW5hYmxlX3BhZGRpbmc="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2xndGhfY2hlY2s=::dHJ1ZQ==::ZW5hYmxlX2xndGhfY2hlY2s="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z2JpdF9vbmx5::dHJ1ZQ==::Z2JpdF9vbmx5"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWJpdF9vbmx5::dHJ1ZQ==::bWJpdF9vbmx5"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVkdWNlZF9jb250cm9s::ZmFsc2U=::cmVkdWNlZF9jb250cm9s"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y29yZV92ZXJzaW9u::NDg2NQ==::Y29yZV92ZXJzaW9u"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2X3ZlcnNpb24=::NDg2NQ==::ZGV2X3ZlcnNpb24="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZWdfZmlmbw==::MjA0OA==::ZWdfZmlmbw=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5nX2ZpZm8=::MjA0OA==::aW5nX2ZpZm8="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVkdWNlZF9pbnRlcmZhY2VfZW5h::dHJ1ZQ==::cmVkdWNlZF9pbnRlcmZhY2VfZW5h"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3luY2hyb25pemVyX2RlcHRo::Mw==::c3luY2hyb25pemVyX2RlcHRo"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::TUFYMTA=::ZGV2aWNlRmFtaWx5"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "aXNVc2VNQUM=::dHJ1ZQ==::aXNVc2VNQUM="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "aXNVc2VQQ1M=::ZmFsc2U=::aXNVc2VQQ1M="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2Nsa19zaGFyaW5n::ZmFsc2U=::ZW5hYmxlX2Nsa19zaGFyaW5n"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y29yZV92YXJpYXRpb24=::TUFDX09OTFk=::Q29yZSB2YXJpYXRpb24="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWZHTUlJ::UkdNSUk=::SW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlX21hY19jbGtlbg==::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgTUFD"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX3VzZV9pbnRlcm5hbF9maWZv::dHJ1ZQ==::VXNlIGludGVybmFsIEZJRk8="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2VjYw==::ZmFsc2U=::RW5hYmxlIEVDQyBwcm90ZWN0aW9u"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlX21pc2NfcG9ydHM=::dHJ1ZQ==::VXNlIG1pc2MgcG9ydHM="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hkX2xvZ2lj::dHJ1ZQ==::RW5hYmxlIE1BQyAxMC8xMDAgaGFsZiBkdXBsZXggc3VwcG9ydA=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2dtaWlfbG9vcGJhY2s=::dHJ1ZQ==::RW5hYmxlIGxvY2FsIGxvb3BiYWNrIG9uIE1JSS9HTUlJL1JHTUlJKg=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX3N1cF9hZGRy::ZmFsc2U=::RW5hYmxlIHN1cHBsZW1lbnRhbCBNQUMgdW5pY2FzdCBhZGRyZXNzZXM="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3RhdF9jbnRfZW5h::dHJ1ZQ==::SW5jbHVkZSBzdGF0aXN0aWNzIGNvdW50ZXJz"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXh0X3N0YXRfY250X2VuYQ==::ZmFsc2U=::RW5hYmxlIDY0LWJpdCBzdGF0aXN0aWNzIGJ5dGUgY291bnRlcnM="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hX2hhc2g=::ZmFsc2U=::SW5jbHVkZSBtdWx0aWNhc3QgaGFzaHRhYmxl"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX3NoaWZ0MTY=::dHJ1ZQ==::QWxpZ24gcGFja2V0IGhlYWRlcnMgdG8gMzItYml0IGJvdW5kYXJ5"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21hY19mbG93X2N0cmw=::ZmFsc2U=::RW5hYmxlIGZ1bGwtZHVwbGV4IGZsb3cgY29udHJvbA=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21hY192bGFu::ZmFsc2U=::RW5hYmxlIFZMQU4gZGV0ZWN0aW9u"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21hZ2ljX2RldGVjdA==::dHJ1ZQ==::RW5hYmxlIG1hZ2ljIHBhY2tldCBkZXRlY3Rpb24="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlTURJTw==::dHJ1ZQ==::SW5jbHVkZSBNRElPIG1vZHVsZSAoTURDL01ESU8p"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWRpb19jbGtfZGl2::NDA=::SG9zdCBjbG9jayBkaXZpc29y"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2VuYQ==::MzI=::V2lkdGg="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZWdfYWRkcg==::MTE=::VHJhbnNtaXQ="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5nX2FkZHI=::MTE=::UmVjZWl2ZQ=="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::aW5wdXQ=::RGF0YSBkaXJlY3Rpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0laRQ==::NA==::RGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9uc2xlZXBfcG9ydA==::ZmFsc2U=::RW5hYmxlIG5zbGVlcCBwb3J0IChvbmx5IGF2YWlsYWJsZSBpbiBzZWxlY3RlZCBkZXZpY2VzKQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9zY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIHNjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3NldF9yZWdpc3RlcnNfdG9fcG93ZXJfdXBfaGlnaA==::ZmFsc2U=::U2V0IHJlZ2lzdGVycyB0byBwb3dlciB1cCBoaWdoICh3aGVuIGFjbHIsIHNjbHIgYW5kIGFzZXQgcG9ydHMgYXJlIG5vdCB1c2VkKQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9pbnB1dF9jbG9jaw==::ZmFsc2U=::SW52ZXJ0IERESU8gaW5jbG9jaw=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9oYXJkZW5lZF9kZGlvX2lucHV0X3JlZ2lzdGVycw==::ZmFsc2U=::SW1wbGVtZW50IERESU8gaW5wdXQgcmVnaXN0ZXJzIGluIGhhcmQgaW1wbGVtZW50YXRpb24gKE9ubHkgYXZhaWxhYmxlIGluIGNlcnRhaW4gZGV2aWNlcyk="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::bm9uZQ==::QVNZTkNfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_NAME "YWx0ZXJhX2V0aF90c2VfbWFj"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "YWx0ZXJhX2V0aF90c2VfbWFj"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5HX0FERFI=::MTE=::SU5HX0FERFI="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BQ19SWF9WTEFO::ZmFsc2U=::RU5BQkxFX01BQ19SWF9WTEFO"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NVUF9BRERS::ZmFsc2U=::RU5BQkxFX1NVUF9BRERS"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYMTA=::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5TRVJUX1RB::ZmFsc2U=::SU5TRVJUX1RB"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5HX0ZJRk8=::MjA0OA==::SU5HX0ZJRk8="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VDQw==::ZmFsc2U=::RU5BQkxFX0VDQw=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1JDMzJEV0lEVEg=::OA==::Q1JDMzJEV0lEVEg="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VOQQ==::MzI=::RU5BQkxFX0VOQQ=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lOQ0hST05JWkVSX0RFUFRI::Mw==::U1lOQ0hST05JWkVSX0RFUFRI"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BQ19UWF9WTEFO::ZmFsc2U=::RU5BQkxFX01BQ19UWF9WTEFO"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVTRVRfTEVWRUw=::MQ==::UkVTRVRfTEVWRUw="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBVF9DTlRfRU5B::dHJ1ZQ==::U1RBVF9DTlRfRU5B"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VTVF9WRVJTSU9O::MA==::Q1VTVF9WRVJTSU9O"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1JDMzJTMUwyX0VYVEVSTg==::ZmFsc2U=::Q1JDMzJTMUwyX0VYVEVSTg=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUJJVF9PTkxZ::dHJ1ZQ==::TUJJVF9PTkxZ"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUdfQUREUg==::MTE=::RUdfQUREUg=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09SRV9WRVJTSU9O::NDg2NQ==::Q09SRV9WRVJTSU9O"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1JDMzJHRU5ERUxBWQ==::Ng==::Q1JDMzJHRU5ERUxBWQ=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUdfRklGTw==::MjA0OA==::RUdfRklGTw=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVEVUNFRF9JTlRFUkZBQ0VfRU5B::dHJ1ZQ==::UkVEVUNFRF9JTlRFUkZBQ0VfRU5B"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BR0lDX0RFVEVDVA==::dHJ1ZQ==::RU5BQkxFX01BR0lDX0RFVEVDVA=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01ESU8=::dHJ1ZQ==::RU5BQkxFX01ESU8="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BQ19UWEFERFJfU0VU::dHJ1ZQ==::RU5BQkxFX01BQ19UWEFERFJfU0VU"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFNX1RZUEU=::QVVUTw==::UkFNX1RZUEU="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1JDMzJDSEVDSzE2QklU::MA==::Q1JDMzJDSEVDSzE2QklU"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xHVEhfQ0hFQ0s=::dHJ1ZQ==::RU5BQkxFX0xHVEhfQ0hFQ0s="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BQ19GTE9XX0NUUkw=::ZmFsc2U=::RU5BQkxFX01BQ19GTE9XX0NUUkw="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NISUZUMTY=::dHJ1ZQ==::RU5BQkxFX1NISUZUMTY="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NZTkNfUkVTRVQ=::dHJ1ZQ==::VVNFX1NZTkNfUkVTRVQ="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVEVUNFRF9DT05UUk9M::ZmFsc2U=::UkVEVUNFRF9DT05UUk9M"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "TURJT19DTEtfRElW::NDA=::TURJT19DTEtfRElW"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BBRERJTkc=::dHJ1ZQ==::RU5BQkxFX1BBRERJTkc="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0dNSUlfTE9PUEJBQ0s=::dHJ1ZQ==::RU5BQkxFX0dNSUlfTE9PUEJBQ0s="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "R0JJVF9PTkxZ::dHJ1ZQ==::R0JJVF9PTkxZ"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BX0hBU0g=::ZmFsc2U=::RU5BX0hBU0g="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVEVOREVEX1NUQVRfUkVH::ZmFsc2U=::RU5BQkxFX0VYVEVOREVEX1NUQVRfUkVH"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hEX0xPR0lD::dHJ1ZQ==::RU5BQkxFX0hEX0xPR0lD"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWZHTUlJ::UkdNSUk=::SW50ZXJmYWNl"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlX21pc2NfcG9ydHM=::dHJ1ZQ==::RW5hYmxlIG1pc2MgcG9ydHM="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlX21hY19jbGtlbg==::ZmFsc2U=::RW5hYmxlIGNsb2NrIGVuYWJsZSBwb3J0cw=="
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y29ubmVjdF90b19wY3M=::ZmFsc2U=::Q29ubmVjdCB0aGlzIG1hYyBpbnN0YW5jZSB0byBwY3M="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZW5ldF9wbGw="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QUxUUExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLWNvbXBhdGlibGUgSW50ZWwgUExMIG1vZHVsZS4gRm9yIFN0cmF0aXggViBhbmQgbmV3ZXIgZmFtaWxpZXMsIHVzZSBJbnRlbCBGUEdBIFBMTCBJUA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NVU1RPTV9FTEFCT1JBVElPTg==::YWx0cGxsX2F2YWxvbl9lbGFib3JhdGlvbg==::SElEREVOX0NVU1RPTV9FTEFCT1JBVElPTg=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NVU1RPTV9QT1NUX0VESVQ=::YWx0cGxsX2F2YWxvbl9wb3N0X2VkaXQ=::SElEREVOX0NVU1RPTV9QT1NUX0VESVQ="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5URU5ERURfREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::SU5URU5ERURfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0lEVEhfQ0xPQ0s=::NQ==::V0lEVEhfQ0xPQ0s="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTEswX0lOUFVUX0ZSRVFVRU5DWQ==::MjAwMDA=::SU5DTEswX0lOUFVUX0ZSRVFVRU5DWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1BFUkFUSU9OX01PREU=::Tk9fQ09NUEVOU0FUSU9O::T1BFUkFUSU9OX01PREU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1RZUEU=::QVVUTw==::UExMX1RZUEU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NUEVOU0FURV9DTE9DSw==::Q0xLMA==::Q09NUEVOU0FURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "QkFORFdJRFRIX1RZUEU=::QVVUTw==::QkFORFdJRFRIX1RZUEU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9NVUxUSVBMWV9CWQ==::NQ==::Q0xLMF9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9NVUxUSVBMWV9CWQ==::MQ==::Q0xLMV9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9NVUxUSVBMWV9CWQ==::MQ==::Q0xLMl9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLM19NVUxUSVBMWV9CWQ==::NQ==::Q0xLM19NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLNF9NVUxUSVBMWV9CWQ==::MQ==::Q0xLNF9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9ESVZJREVfQlk=::Mg==::Q0xLMF9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9ESVZJREVfQlk=::Mg==::Q0xLMV9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9ESVZJREVfQlk=::MjA=::Q0xLMl9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLM19ESVZJREVfQlk=::Mg==::Q0xLM19ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLNF9ESVZJREVfQlk=::Mg==::Q0xLNF9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9QSEFTRV9TSElGVA==::MA==::Q0xLMF9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9QSEFTRV9TSElGVA==::MA==::Q0xLMV9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9QSEFTRV9TSElGVA==::MA==::Q0xLMl9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLM19QSEFTRV9TSElGVA==::LTMwMDA=::Q0xLM19QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLNF9QSEFTRV9TSElGVA==::LTEwMDAw::Q0xLNF9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9EVVRZX0NZQ0xF::NTA=::Q0xLMF9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9EVVRZX0NZQ0xF::NTA=::Q0xLMV9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9EVVRZX0NZQ0xF::NTA=::Q0xLMl9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLM19EVVRZX0NZQ0xF::NTA=::Q0xLM19EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLNF9EVVRZX0NZQ0xF::NTA=::Q0xLNF9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEw::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEw"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEx::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEx"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEy::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEy"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEz::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEz"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmE0::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmE0"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmE1::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmE1"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsw::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsw"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsx::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsx"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsy::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsy"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsz::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsz"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtCQUQw::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtCQUQw"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtCQUQx::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtCQUQx"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsw::UE9SVF9VU0VE::UE9SVF9jbGsw"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsx::UE9SVF9VU0VE::UE9SVF9jbGsx"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsy::UE9SVF9VU0VE::UE9SVF9jbGsy"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsz::UE9SVF9VU0VE::UE9SVF9jbGsz"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGs0::UE9SVF9VU0VE::UE9SVF9jbGs0"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGs1::UE9SVF9VTlVTRUQ=::UE9SVF9jbGs1"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOREFUQQ==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOREFUQQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOREFUQU9VVA==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOREFUQU9VVA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FORE9ORQ==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FORE9ORQ=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9BQ1RJVkVDTE9DSw==::UE9SVF9VTlVTRUQ=::UE9SVF9BQ1RJVkVDTE9DSw=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtMT1NT::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtMT1NT"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTkNMSzE=::UE9SVF9VTlVTRUQ=::UE9SVF9JTkNMSzE="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTkNMSzA=::UE9SVF9VU0VE::UE9SVF9JTkNMSzA="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9GQklO::UE9SVF9VTlVTRUQ=::UE9SVF9GQklO"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QTExFTkE=::UE9SVF9VTlVTRUQ=::UE9SVF9QTExFTkE="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtTV0lUQ0g=::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtTV0lUQ0g="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9BUkVTRVQ=::UE9SVF9VTlVTRUQ=::UE9SVF9BUkVTRVQ="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QRkRFTkE=::UE9SVF9VTlVTRUQ=::UE9SVF9QRkRFTkE="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQ0xL::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQ0xL"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQUNMUg==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQUNMUg=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOUkVBRA==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOUkVBRA=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOV1JJVEU=::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOV1JJVEU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9MT0NLRUQ=::UE9SVF9VU0VE::UE9SVF9MT0NLRUQ="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DT05GSUdVUERBVEU=::UE9SVF9VTlVTRUQ=::UE9SVF9DT05GSUdVUERBVEU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRURPTkU=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRURPTkU="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRVNURVA=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRVNURVA="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRVVQRE9XTg==::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRVVQRE9XTg=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQ0xLRU5B::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQ0xLRU5B"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRUNPVU5URVJTRUxFQ1Q=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRUNPVU5URVJTRUxFQ1Q="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZBTE9OX1VTRV9TRVBBUkFURV9TWVNDTEs=::Tk8=::QVZBTE9OX1VTRV9TRVBBUkFURV9TWVNDTEs="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NPTlNUQU5UUw==::Q1QjQ0xLMl9ESVZJREVfQlkgMjAgQ1QjUE9SVF9jbGs1IFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrNCBQT1JUX1VTRUQgQ1QjUE9SVF9jbGszIFBPUlRfVVNFRCBDVCNQT1JUX2NsazIgUE9SVF9VU0VEIENUI1BPUlRfY2xrMSBQT1JUX1VTRUQgQ1QjUE9SVF9jbGswIFBPUlRfVVNFRCBDVCNDTEswX01VTFRJUExZX0JZIDUgQ1QjUE9SVF9TQ0FOV1JJVEUgUE9SVF9VTlVTRUQgQ1QjUE9SVF9TQ0FOQUNMUiBQT1JUX1VOVVNFRCBDVCNQT1JUX1BGREVOQSBQT1JUX1VOVVNFRCBDVCNDTEszX0RVVFlfQ1lDTEUgNTAgQ1QjQ0xLM19ESVZJREVfQlkgMiBDVCNQT1JUX1BMTEVOQSBQT1JUX1VOVVNFRCBDVCNQT1JUX1NDQU5EQVRBIFBPUlRfVU5VU0VEIENUI0NMSzNfUEhBU0VfU0hJRlQgLTMwMDAgQ1QjUE9SVF9TQ0FOQ0xLRU5BIFBPUlRfVU5VU0VEIENUI0NMSzRfRElWSURFX0JZIDIgQ1QjV0lEVEhfQ0xPQ0sgNSBDVCNQT1JUX1NDQU5EQVRBT1VUIFBPUlRfVU5VU0VEIENUI0NMSzRfTVVMVElQTFlfQlkgMSBDVCNMUE1fVFlQRSBhbHRwbGwgQ1QjUExMX1RZUEUgQVVUTyBDVCNDTEswX1BIQVNFX1NISUZUIDAgQ1QjQ0xLMV9EVVRZX0NZQ0xFIDUwIENUI1BPUlRfUEhBU0VET05FIFBPUlRfVU5VU0VEIENUI09QRVJBVElPTl9NT0RFIE5PX0NPTVBFTlNBVElPTiBDVCNQT1JUX0NPTkZJR1VQREFURSBQT1JUX1VOVVNFRCBDVCNDTEsxX01VTFRJUExZX0JZIDEgQ1QjQ09NUEVOU0FURV9DTE9DSyBDTEswIENUI1BPUlRfQ0xLU1dJVENIIFBPUlRfVU5VU0VEIENUI0NMSzRfUEhBU0VfU0hJRlQgLTEwMDAwIENUI0lOQ0xLMF9JTlBVVF9GUkVRVUVOQ1kgMjAwMDAgQ1QjQ0xLNF9EVVRZX0NZQ0xFIDUwIENUI1BPUlRfU0NBTkRPTkUgUE9SVF9VTlVTRUQgQ1QjUE9SVF9DTEtMT1NTIFBPUlRfVU5VU0VEIENUI1BPUlRfSU5DTEsxIFBPUlRfVU5VU0VEIENUI0FWQUxPTl9VU0VfU0VQQVJBVEVfU1lTQ0xLIE5PIENUI1BPUlRfSU5DTEswIFBPUlRfVVNFRCBDVCNQT1JUX2Nsa2VuYTUgUE9SVF9VTlVTRUQgQ1QjUE9SVF9jbGtlbmE0IFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrZW5hMyBQT1JUX1VOVVNFRCBDVCNQT1JUX2Nsa2VuYTIgUE9SVF9VTlVTRUQgQ1QjUE9SVF9jbGtlbmExIFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrZW5hMCBQT1JUX1VOVVNFRCBDVCNDTEsxX1BIQVNFX1NISUZUIDAgQ1QjUE9SVF9BUkVTRVQgUE9SVF9VTlVTRUQgQ1QjQkFORFdJRFRIX1RZUEUgQVVUTyBDVCNDTEsyX01VTFRJUExZX0JZIDEgQ1QjSU5URU5ERURfREVWSUNFX0ZBTUlMWSB7TUFYIDEwfSBDVCNQT1JUX1NDQU5SRUFEIFBPUlRfVU5VU0VEIENUI0NMSzJfRFVUWV9DWUNMRSA1MCBDVCNQT1JUX1BIQVNFU1RFUCBQT1JUX1VOVVNFRCBDVCNQT1JUX1NDQU5DTEsgUE9SVF9VTlVTRUQgQ1QjUE9SVF9DTEtCQUQxIFBPUlRfVU5VU0VEIENUI1BPUlRfQ0xLQkFEMCBQT1JUX1VOVVNFRCBDVCNQT1JUX0ZCSU4gUE9SVF9VTlVTRUQgQ1QjUE9SVF9QSEFTRVVQRE9XTiBQT1JUX1VOVVNFRCBDVCNQT1JUX2V4dGNsazMgUE9SVF9VTlVTRUQgQ1QjUE9SVF9leHRjbGsyIFBPUlRfVU5VU0VEIENUI1BPUlRfZXh0Y2xrMSBQT1JUX1VOVVNFRCBDVCNQT1JUX1BIQVNFQ09VTlRFUlNFTEVDVCBQT1JUX1VOVVNFRCBDVCNQT1JUX2V4dGNsazAgUE9SVF9VTlVTRUQgQ1QjUE9SVF9BQ1RJVkVDTE9DSyBQT1JUX1VOVVNFRCBDVCNDTEsyX1BIQVNFX1NISUZUIDAgQ1QjQ0xLMF9EVVRZX0NZQ0xFIDUwIENUI0NMSzBfRElWSURFX0JZIDIgQ1QjQ0xLMV9ESVZJREVfQlkgMiBDVCNDTEszX01VTFRJUExZX0JZIDUgQ1QjUE9SVF9MT0NLRUQgUE9SVF9VU0VE::SElEREVOX0NPTlNUQU5UUw=="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX1BSSVZBVEVT::UFQjR0xPQ0tFRF9GRUFUVVJFX0VOQUJMRUQgMCBQVCNTUFJFQURfRkVBVFVSRV9FTkFCTEVEIDAgUFQjQkFORFdJRFRIX0ZSRVFfVU5JVCBNSHogUFQjQ1VSX0RFRElDQVRFRF9DTEsgYzAgUFQjSU5DTEswX0ZSRVFfRURJVCA1MC4wMDAgUFQjQkFORFdJRFRIX1BSRVNFVCBMb3cgUFQjUExMX0xWRFNfUExMX0NIRUNLIDAgUFQjQkFORFdJRFRIX1VTRV9QUkVTRVQgMCBQVCNBVkFMT05fVVNFX1NFUEFSQVRFX1NZU0NMSyBOTyBQVCNPVVRQVVRfRlJFUV9VTklUNCBNSHogUFQjT1VUUFVUX0ZSRVFfVU5JVDMgTUh6IFBUI1BMTF9FTkhQTExfQ0hFQ0sgMCBQVCNPVVRQVVRfRlJFUV9VTklUMiBNSHogUFQjT1VUUFVUX0ZSRVFfVU5JVDEgTUh6IFBUI09VVFBVVF9GUkVRX1VOSVQwIE1IeiBQVCNQSEFTRV9SRUNPTkZJR19GRUFUVVJFX0VOQUJMRUQgMSBQVCNDUkVBVEVfQ0xLQkFEX0NIRUNLIDAgUFQjQ0xLU1dJVENIX0NIRUNLIDAgUFQjSU5DTEsxX0ZSRVFfRURJVCAxMDAuMDAwIFBUI05PUk1BTF9NT0RFX1JBRElPIDAgUFQjU1JDX1NZTkNIX0NPTVBfUkFESU8gMCBQVCNQTExfQVJFU0VUX0NIRUNLIDAgUFQjTE9OR19TQ0FOX1JBRElPIDEgUFQjU0NBTl9GRUFUVVJFX0VOQUJMRUQgMSBQVCNVU0VfQ0xLNCAxIFBUI1VTRV9DTEszIDEgUFQjVVNFX0NMSzIgMSBQVCNQSEFTRV9SRUNPTkZJR19JTlBVVFNfQ0hFQ0sgMCBQVCNVU0VfQ0xLMSAxIFBUI1VTRV9DTEswIDEgUFQjUFJJTUFSWV9DTEtfQ09NQk8gaW5jbGswIFBUI0JBTkRXSURUSCAxLjAwMCBQVCNHTE9DS0VEX0NPVU5URVJfRURJVF9DSEFOR0VEIDEgUFQjUExMX0ZBU1RQTExfQ0hFQ0sgMCBQVCNTUFJFQURfRlJFUV9VTklUIEtIeiBQVCNMVkRTX1BIQVNFX1NISUZUX1VOSVQ0IGRlZyBQVCNMVkRTX1BIQVNFX1NISUZUX1VOSVQzIGRlZyBQVCNQTExfQVVUT1BMTF9DSEVDSyAxIFBUI09VVFBVVF9GUkVRX01PREU0IDAgUFQjTFZEU19QSEFTRV9TSElGVF9VTklUMiBkZWcgUFQjT1VUUFVUX0ZSRVFfTU9ERTMgMCBQVCNMVkRTX1BIQVNFX1NISUZUX1VOSVQxIGRlZyBQVCNPVVRQVVRfRlJFUV9NT0RFMiAxIFBUI0xWRFNfUEhBU0VfU0hJRlRfVU5JVDAgZGVnIFBUI09VVFBVVF9GUkVRX01PREUxIDEgUFQjU1dJVENIT1ZFUl9GRUFUVVJFX0VOQUJMRUQgMCBQVCNNSUdfREVWSUNFX1NQRUVEX0dSQURFIEFueSBQVCNPVVRQVVRfRlJFUV9NT0RFMCAxIFBUI0JBTkRXSURUSF9GRUFUVVJFX0VOQUJMRUQgMSBQVCNJTkNMSzBfRlJFUV9VTklUX0NPTUJPIE1IeiBQVCNaRVJPX0RFTEFZX1JBRElPIDAgUFQjT1VUUFVUX0ZSRVE0IDEwMC4wMDAwMDAwMCBQVCNPVVRQVVRfRlJFUTMgMTAwLjAwMDAwMDAwIFBUI09VVFBVVF9GUkVRMiAyLjUwMDAwMDAwIFBUI09VVFBVVF9GUkVRMSAyNS4wMDAwMDAwMCBQVCNPVVRQVVRfRlJFUTAgMTI1LjAwMDAwMDAwIFBUI1NIT1JUX1NDQU5fUkFESU8gMCBQVCNMVkRTX01PREVfREFUQV9SQVRFX0RJUlRZIDAgUFQjQ1VSX0ZCSU5fQ0xLIGMwIFBUI1BMTF9BRFZBTkNFRF9QQVJBTV9DSEVDSyAwIFBUI0NMS0JBRF9TV0lUQ0hPVkVSX0NIRUNLIDAgUFQjUEhBU0VfU0hJRlRfU1RFUF9FTkFCTEVEX0NIRUNLIDAgUFQjREVWSUNFX1NQRUVEX0dSQURFIEFueSBQVCNQTExfRkJNSU1JQ19DSEVDSyAwIFBUI0xWRFNfTU9ERV9EQVRBX1JBVEUge05vdCBBdmFpbGFibGV9IFBUI1BIQVNFX1NISUZUNCAtOTAuMDAwMDAwMDAgUFQjTE9DS0VEX09VVFBVVF9DSEVDSyAxIFBUI1NQUkVBRF9QRVJDRU5UIDAuNTAwIFBUI1BIQVNFX1NISUZUMyAtMTM1LjAwMDAwMDAwIFBUI0RJVl9GQUNUT1I0IDIgUFQjUEhBU0VfU0hJRlQyIDAuMDAwMDAwMDAgUFQjRElWX0ZBQ1RPUjMgMiBQVCNESVZfRkFDVE9SMiAxIFBUI1BIQVNFX1NISUZUMSAwLjAwMDAwMDAwIFBUI0RJVl9GQUNUT1IxIDEgUFQjUEhBU0VfU0hJRlQwIDAuMDAwMDAwMDAgUFQjRElWX0ZBQ1RPUjAgMSBQVCNDTlhfTk9fQ09NUEVOU0FURV9SQURJTyAxIFBUI1VTRV9DTEtFTkE0IDAgUFQjVVNFX0NMS0VOQTMgMCBQVCNVU0VfQ0xLRU5BMiAwIFBUI1VTRV9DTEtFTkExIDAgUFQjVVNFX0NMS0VOQTAgMCBQVCNDUkVBVEVfSU5DTEsxX0NIRUNLIDAgUFQjR0xPQ0tfQ09VTlRFUl9FRElUIDEwNDg1NzUgUFQjSU5DTEsxX0ZSRVFfVU5JVF9DT01CTyBNSHogUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFNCAyNS4wMDAwMDAgUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFMyAxMjUuMDAwMDAwIFBUI0VGRl9PVVRQVVRfRlJFUV9WQUxVRTIgMi41MDAwMDAgUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFMSAyNS4wMDAwMDAgUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFMCAxMjUuMDAwMDAwIFBUI1NQUkVBRF9GUkVRIDUwLjAwMCBQVCNVU0VfTUlMX1NQRUVEX0dSQURFIDAgUFQjRVhQTElDSVRfU1dJVENIT1ZFUl9DT1VOVEVSIDAgUFQjU1RJQ0tZX0NMSzQgMSBQVCNTVElDS1lfQ0xLMyAxIFBUI1NUSUNLWV9DTEsyIDEgUFQjU1RJQ0tZX0NMSzEgMSBQVCNTVElDS1lfQ0xLMCAxIFBUI01JUlJPUl9DTEs0IDAgUFQjRVhUX0ZFRURCQUNLX1JBRElPIDAgUFQjTUlSUk9SX0NMSzMgMCBQVCNNSVJST1JfQ0xLMiAwIFBUI01JUlJPUl9DTEsxIDAgUFQjU1dJVENIT1ZFUl9DT1VOVF9FRElUIDEgUFQjTUlSUk9SX0NMSzAgMCBQVCNTRUxGX1JFU0VUX0xPQ0tfTE9TUyAwIFBUI1BMTF9QRkRFTkFfQ0hFQ0sgMCBQVCNJTlRfRkVFREJBQ0tfX01PREVfUkFESU8gMSBQVCNJTkNMSzFfRlJFUV9FRElUX0NIQU5HRUQgMSBQVCNTWU5USF9XUkFQUEVSX0dFTl9QT1NURklYIDAgUFQjQ0xLTE9TU19DSEVDSyAwIFBUI1BIQVNFX1NISUZUX1VOSVQ0IGRlZyBQVCNQSEFTRV9TSElGVF9VTklUMyBkZWcgUFQjUEhBU0VfU0hJRlRfVU5JVDIgZGVnIFBUI1BIQVNFX1NISUZUX1VOSVQxIGRlZyBQVCNQSEFTRV9TSElGVF9VTklUMCBkZWcgUFQjQkFORFdJRFRIX1VTRV9BVVRPIDEgUFQjSEFTX01BTlVBTF9TV0lUQ0hPVkVSIDEgUFQjTVVMVF9GQUNUT1I0IDEgUFQjTVVMVF9GQUNUT1IzIDUgUFQjTVVMVF9GQUNUT1IyIDEgUFQjTVVMVF9GQUNUT1IxIDEgUFQjTVVMVF9GQUNUT1IwIDEgUFQjU1BSRUFEX1VTRSAwIFBUI0dMT0NLRURfTU9ERV9DSEVDSyAwIFBUI0RVVFlfQ1lDTEU0IDUwLjAwMDAwMDAwIFBUI0RVVFlfQ1lDTEUzIDUwLjAwMDAwMDAwIFBUI0RVVFlfQ1lDTEUyIDUwLjAwMDAwMDAwIFBUI1NBQ05fSU5QVVRTX0NIRUNLIDAgUFQjRFVUWV9DWUNMRTEgNTAuMDAwMDAwMDAgUFQjSU5URU5ERURfREVWSUNFX0ZBTUlMWSB7TUFYIDEwfSBQVCNEVVRZX0NZQ0xFMCA1MC4wMDAwMDAwMCBQVCNQTExfVEFSR0VUX0hBUkNPUFlfQ0hFQ0sgMCBQVCNJTkNMSzFfRlJFUV9VTklUX0NIQU5HRUQgMSBQVCNSRUNPTkZJR19GSUxFIEFMVFBMTDE0MTg4ODI4MTYwOTMyODIubWlmIFBUI0FDVElWRUNMS19DSEVDSyAw::SElEREVOX1BSSVZBVEVT"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX1VTRURfUE9SVFM=::VVAjbG9ja2VkIHVzZWQgVVAjYzQgdXNlZCBVUCNjMyB1c2VkIFVQI2MyIHVzZWQgVVAjYzEgdXNlZCBVUCNjMCB1c2VkIFVQI2FyZXNldCB1c2VkIFVQI2luY2xrMCB1c2Vk::SElEREVOX1VTRURfUE9SVFM="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lTX05VTUVSSUM=::SU4jV0lEVEhfQ0xPQ0sgMSBJTiNDTEswX0RVVFlfQ1lDTEUgMSBJTiNDTEsyX0RJVklERV9CWSAxIElOI1BMTF9UQVJHRVRfSEFSQ09QWV9DSEVDSyAxIElOI0NMSzNfRElWSURFX0JZIDEgSU4jQ0xLNF9NVUxUSVBMWV9CWSAxIElOI0NMSzFfTVVMVElQTFlfQlkgMSBJTiNDTEszX0RVVFlfQ1lDTEUgMSBJTiNDTEs0X0RJVklERV9CWSAxIElOI1NXSVRDSE9WRVJfQ09VTlRfRURJVCAxIElOI0lOQ0xLMF9JTlBVVF9GUkVRVUVOQ1kgMSBJTiNQTExfTFZEU19QTExfQ0hFQ0sgMSBJTiNQTExfQVVUT1BMTF9DSEVDSyAxIElOI1BMTF9GQVNUUExMX0NIRUNLIDEgSU4jQ0xLMV9EVVRZX0NZQ0xFIDEgSU4jUExMX0VOSFBMTF9DSEVDSyAxIElOI0NMSzJfTVVMVElQTFlfQlkgMSBJTiNESVZfRkFDVE9SNCAxIElOI0RJVl9GQUNUT1IzIDEgSU4jRElWX0ZBQ1RPUjIgMSBJTiNESVZfRkFDVE9SMSAxIElOI0RJVl9GQUNUT1IwIDEgSU4jTFZEU19NT0RFX0RBVEFfUkFURV9ESVJUWSAxIElOI0NMSzRfRFVUWV9DWUNMRSAxIElOI0dMT0NLX0NPVU5URVJfRURJVCAxIElOI0NMSzJfRFVUWV9DWUNMRSAxIElOI0NMSzBfRElWSURFX0JZIDEgSU4jQ0xLM19NVUxUSVBMWV9CWSAxIElOI01VTFRfRkFDVE9SNCAxIElOI01VTFRfRkFDVE9SMyAxIElOI01VTFRfRkFDVE9SMiAxIElOI01VTFRfRkFDVE9SMSAxIElOI01VTFRfRkFDVE9SMCAxIElOI0NMSzBfTVVMVElQTFlfQlkgMSBJTiNVU0VfTUlMX1NQRUVEX0dSQURFIDEgSU4jQ0xLMV9ESVZJREVfQlkgMQ==::SElEREVOX0lTX05VTUVSSUM="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX01GX1BPUlRT::TUYjYXJlc2V0IDEgTUYjY2xrIDEgTUYjbG9ja2VkIDEgTUYjaW5jbGsgMQ==::SElEREVOX01GX1BPUlRT"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lGX1BPUlRT::SUYjbG9ja2VkIHtvdXRwdXQgMH0gSUYjcmVzZXQge2lucHV0IDB9IElGI2NsayB7aW5wdXQgMH0gSUYjcmVhZGRhdGEge291dHB1dCAzMn0gSUYjd3JpdGUge2lucHV0IDB9IElGI3BoYXNlZG9uZSB7b3V0cHV0IDB9IElGI2M0IHtvdXRwdXQgMH0gSUYjYzMge291dHB1dCAwfSBJRiNhZGRyZXNzIHtpbnB1dCAyfSBJRiNjMiB7b3V0cHV0IDB9IElGI2MxIHtvdXRwdXQgMH0gSUYjYzAge291dHB1dCAwfSBJRiN3cml0ZWRhdGEge2lucHV0IDMyfSBJRiNyZWFkIHtpbnB1dCAwfSBJRiNhcmVzZXQge2lucHV0IDB9::SElEREVOX0lGX1BPUlRT"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lTX0ZJUlNUX0VESVQ=::MA==::SElEREVOX0lTX0ZJUlNUX0VESVQ="
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19JTkNMS19JTlRFUkZBQ0VfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGVzY3JpcHRvcl9tZW1vcnk="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "YWxsb3dJblN5c3RlbU1lbW9yeUNvbnRlbnRFZGl0b3I=::ZmFsc2U=::RW5hYmxlIEluLVN5c3RlbSBNZW1vcnkgQ29udGVudCBFZGl0b3IgZmVhdHVyZQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "YmxvY2tUeXBl::QVVUTw==::QmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRo::MzI=::U2xhdmUgUzEgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRoMg==::MzI=::U2xhdmUgUzIgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZHVhbFBvcnQ=::ZmFsc2U=::RHVhbC1wb3J0IGFjY2Vzcw=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg=::ZmFsc2U=::ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5pdE1lbUNvbnRlbnQ=::ZmFsc2U=::SW5pdGlhbGl6ZSBtZW1vcnkgY29udGVudA=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWVtb3J5U2l6ZQ==::ODE5Mg==::VG90YWwgbWVtb3J5IHNpemU="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltQWxsb3dNUkFNQ29udGVudHNGaWxl::ZmFsc2U=::QWxsb3cgTVJBTSBjb250ZW50cyBmaWxlIGZvciBzaW11bGF0aW9u"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltTWVtSW5pdE9ubHlGaWxlbmFtZQ==::MA==::U2ltdWxhdGlvbiBtZW1pbml0IG9ubHkgaGFzIGZpbGVuYW1l"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg==::ZmFsc2U=::ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2xhdmUxTGF0ZW5jeQ==::MQ==::U2xhdmUgczEgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "d3JpdGFibGU=::dHJ1ZQ==::VHlwZQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZWNjX2VuYWJsZWQ=::ZmFsc2U=::RXh0ZW5kIHRoZSBkYXRhIHdpZHRoIHRvIHN1cHBvcnQgRUNDIGJpdHM="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::UmVzZXQgUmVxdWVzdA=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU=::cV9zeXNfZGVzY3JpcHRvcl9tZW1vcnk=::YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::TUFYIDEw::ZGV2aWNlRmFtaWx5"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXM=::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXM="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aA==::MTE=::U2xhdmUgMSBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aDI=::MTE=::U2xhdmUgMiBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aA==::MzI=::U2xhdmUgMSBkYXRhIHdpZHRo"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aDI=::MzI=::U2xhdmUgMiBkYXRhIHdpZHRo"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU=::QXV0b21hdGlj::ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pc19oYXJkY29weQ==::ZmFsc2U=::ZGVyaXZlZF9pc19oYXJkY29weQ=="
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ==::cV9zeXNfZGVzY3JpcHRvcl9tZW1vcnkuaGV4::ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGVidWdfdWFydA=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "VUFSVCAoUlMtMjMyIFNlcmlhbCBQb3J0KSBJbnRlbCBGUEdBIElQ"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCByYXRlIChicHMp"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YUJpdHM=::OA==::RGF0YSBiaXRz"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zml4ZWRCYXVk::dHJ1ZQ==::Rml4ZWQgYmF1ZCByYXRl"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tk9ORQ==::UGFyaXR5"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltSW50ZXJhY3RpdmVJbnB1dEVuYWJsZQ==::ZmFsc2U=::SW50ZXJhY3RpdmUgc3RpbXVsdXMgd2luZG93"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltSW50ZXJhY3RpdmVPdXRwdXRFbmFibGU=::ZmFsc2U=::U3RyZWFtaW5nIG91dHB1dCB3aW5kb3c="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltVHJ1ZUJhdWQ=::ZmFsc2U=::T3B0aW9u"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3RvcEJpdHM=::MQ==::U3RvcCBiaXRz"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3luY1JlZ0RlcHRo::Mg==::U3luY2hyb25pemVyIHN0YWdlcw=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlQ3RzUnRz::ZmFsc2U=::SW5jbHVkZSBDVFMvUlRT"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlRW9wUmVnaXN0ZXI=::ZmFsc2U=::SW5jbHVkZSBlbmQtb2YtcGFja2V0"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "dXNlUmVsYXRpdmVQYXRoRm9yU2ltRmlsZQ==::ZmFsc2U=::dXNlUmVsYXRpdmVQYXRoRm9yU2ltRmlsZQ=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NTAwMDAwMDA=::Y2xvY2tSYXRl"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "YmF1ZEVycm9y::MC4wMQ==::QmF1ZCBlcnJvcg=="
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_COMPONENT_PARAMETER "cGFyaXR5RmlzcnRDaGFy::Tg==::cGFyaXR5RmlzcnRDaGFy"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGRyM19yYW0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBDb250cm9sbGVyIHdpdGggVW5pUEhZIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::ZmFsc2U=::RkxZX0JZ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::dHJ1ZQ==::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::ZmFsc2U=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::ZmFsc2U=::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTX1dJRFRI::MQ==::Q1RMX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0JFX1dJRFRI::NA==::QVZMX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19DU1JfRU5BQkxFRA==::ZmFsc2U=::Q1RMX0VDQ19DU1JfRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFdJRFRIX1JBVElP::NA==::RFdJRFRIX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09EVF9FTkFCTEVE::ZmFsc2U=::Q1RMX09EVF9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09VVFBVVF9SRUdE::ZmFsc2U=::Q1RMX09VVFBVVF9SRUdE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::Q1RMX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9XX0xBVEVOQ1k=::ZmFsc2U=::TE9XX0xBVEVOQ1k="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9UWVBF::bmV4dGdlbl92MTEw::Q09OVFJPTExFUl9UWVBF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1RCUF9OVU0=::NA==::Q1RMX1RCUF9OVU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNI::MA==::Q1RMX1VTUl9SRUZSRVNI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSA==::MA==::Q1RMX1NFTEZfUkVGUkVTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RZUEU=::Mg==::Q0ZHX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0lOVEVSRkFDRV9XSURUSA==::OA==::Q0ZHX0lOVEVSRkFDRV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0JVUlNUX0xFTkdUSA==::OA==::Q0ZHX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0FERFJfT1JERVI=::MA==::Q0ZHX0FERFJfT1JERVI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BETl9FWElUX0NZQ0xFUw==::MTA=::Q0ZHX1BETl9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==::NQ==::Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT::MjA=::Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==::NTEy::Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=::MQ==::Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==::MQ==::Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1dSSVRFX09EVF9DSElQ::MQ==::Q0ZHX1dSSVRFX09EVF9DSElQ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFQURfT0RUX0NISVA=::MA==::Q0ZHX1JFQURfT0RUX0NISVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfQ1NfV0lEVEg=::MA==::TE9DQUxfQ1NfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0NMUl9JTlRS::MA==::Q0ZHX0NMUl9JTlRS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VOQUJMRV9OT19ETQ==::MA==::Q0ZHX0VOQUJMRV9OT19ETQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FERF9MQVQ=::MA==::TUVNX0FERF9MQVQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VSUkNNRF9GSUZPX1JFRw==::MA==::Q0ZHX0VSUkNNRF9GSUZPX1JFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VDQ19ERUNPREVSX1JFRw==::MA==::Q0ZHX0VDQ19ERUNPREVSX1JFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=::ZmFsc2U=::Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NUQVJWRV9MSU1JVA==::MTA=::Q0ZHX1NUQVJWRV9MSU1JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fUERfQ1lDTEVT::MA==::TUVNX0FVVE9fUERfQ1lDTEVT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8w::MA==::UFJJT1JJVFlfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMA==::MA==::V0VJR0hUX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMA==::NQ==::TFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMA==::NQ==::TVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMA==::NQ==::TFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMA==::NQ==::TVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8x::MA==::UFJJT1JJVFlfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMQ==::MA==::V0VJR0hUX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMQ==::NQ==::TFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMQ==::NQ==::TVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMQ==::NQ==::TFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMQ==::NQ==::TVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8y::MA==::UFJJT1JJVFlfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMg==::MA==::V0VJR0hUX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMg==::NQ==::TFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMg==::NQ==::TVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMg==::NQ==::TFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMg==::NQ==::TVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8z::MA==::UFJJT1JJVFlfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMw==::MA==::V0VJR0hUX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMw==::NQ==::TFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMw==::NQ==::TVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMw==::NQ==::TFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMw==::NQ==::TVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF80::MA==::UFJJT1JJVFlfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNA==::MA==::V0VJR0hUX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNA==::NQ==::TFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNA==::NQ==::TVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNA==::NQ==::TFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNA==::NQ==::TVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF81::MA==::UFJJT1JJVFlfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNQ==::MA==::V0VJR0hUX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNQ==::NQ==::TFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNQ==::NQ==::TVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNQ==::NQ==::TFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNQ==::NQ==::TVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1JGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFJlYWQtRGF0YSBGSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1dGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFdyaXRlLURhdGEgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfT05FX1JFU0VU::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX29uZV9yZXNldA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfWkVST19SRVNFVA==::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX3plcm9fcmVzZXQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX1NUQVRJQ19DT05GSUdfVkFMSUQ=::RElTQUJMRUQ=::YXR0cl9zdGF0aWNfY29uZmlnX3ZhbGlk"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DQUxfUkVR::RElTQUJMRUQ=::Y2FsX3JlcQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfQlVSU1RfTEVOR1RI::QkxfOA==::Y2ZnX2J1cnN0X2xlbmd0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfSU5URVJGQUNFX1dJRFRI::RFdJRFRIXzMy::Y2ZnX2ludGVyZmFjZV93aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU1RBUlZFX0xJTUlU::U1RBUlZFX0xJTUlUXzMy::Y2ZnX3N0YXJ2ZV9saW1pdA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfVFlQRQ==::RERSMw==::Y2ZnX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMg==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMw==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTFJfSU5UUg==::Tk9fQ0xSX0lOVFI=::Y2xyX2ludHI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQwX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQxX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQyX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQzX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ0X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ1X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfQUREUl9PUkRFUg==::Q0hJUF9CQU5LX1JPV19DT0w=::Y3RsX2FkZHJfb3JkZXI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX0VOQUJMRUQ=::Q1RMX0VDQ19ESVNBQkxFRA==::Y3RsX2VjY19lbmFibGVk"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX1JNV19FTkFCTEVE::Q1RMX0VDQ19STVdfRElTQUJMRUQ=::Y3RsX2VjY19ybXdfZW5hYmxlZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfUkVHRElNTV9FTkFCTEVE::UkVHRElNTV9ESVNBQkxFRA==::Y3RsX3JlZ2RpbW1fZW5hYmxlZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfVVNSX1JFRlJFU0g=::Q1RMX1VTUl9SRUZSRVNIX0RJU0FCTEVE::Y3RsX3Vzcl9yZWZyZXNo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVFJMX1dJRFRI::REFUQV9XSURUSF82NF9CSVQ=::Y3RybF93aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERUxBWV9CT05ESU5H::Qk9ORElOR19MQVRFTkNZXzA=::ZGVsYXlfYm9uZGluZw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERlhfQllQQVNTX0VOQUJMRQ==::REZYX0JZUEFTU19ESVNBQkxFRA==::ZGZ4X2J5cGFzc19lbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ESVNBQkxFX01FUkdJTkc=::TUVSR0lOR19FTkFCTEVE::ZGlzYWJsZV9tZXJnaW5n"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FQ0NfRFFfV0lEVEg=::RUNDX0RRX1dJRFRIXzA=::ZWNjX2RxX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQVRQRw==::RElTQUJMRUQ=::ZW5hYmxlX2F0cGc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR19XUkFQQkFDSw==::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfd3JhcGJhY2s="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRFFTX1RSQUNLSU5H::RElTQUJMRUQ=::ZW5hYmxlX2Rxc190cmFja2luZw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRUNDX0NPREVfT1ZFUldSSVRFUw==::RElTQUJMRUQ=::ZW5hYmxlX2VjY19jb2RlX292ZXJ3cml0ZXM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRkFTVF9FWElUX1BQRA==::RElTQUJMRUQ=::ZW5hYmxlX2Zhc3RfZXhpdF9wcGQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfSU5UUg==::RElTQUJMRUQ=::ZW5hYmxlX2ludHI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfTk9fRE0=::RElTQUJMRUQ=::ZW5hYmxlX25vX2Rt"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfUElQRUxJTkVHTE9CQUw=::RElTQUJMRUQ=::ZW5hYmxlX3BpcGVsaW5lZ2xvYmFs"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HQU5HRURfQVJG::RElTQUJMRUQ=::Z2FuZ2VkX2FyZg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fREJF::R0VOX0RCRV9ESVNBQkxFRA==::Z2VuX2RiZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fU0JF::R0VOX1NCRV9ESVNBQkxFRA==::Z2VuX3NiZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9JTkNfU1lOQw==::RklGT19TRVRfMg==::aW5jX3N5bmM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9MT0NBTF9JRl9DU19XSURUSA==::QUREUl9XSURUSF8y::bG9jYWxfaWZfY3Nfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0NPUlJfRFJPUFBFRF9JTlRS::RElTQUJMRUQ=::bWFza19jb3JyX2Ryb3BwZWRfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0RCRV9JTlRS::RElTQUJMRUQ=::bWFza19kYmVfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX1NCRV9JTlRS::RElTQUJMRUQ=::bWFza19zYmVfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQUw=::QUxfMA==::bWVtX2lmX2Fs"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQkFOS0FERFJfV0lEVEg=::QUREUl9XSURUSF8z::bWVtX2lmX2JhbmthZGRyX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQlVSU1RMRU5HVEg=::TUVNX0lGX0JVUlNUTEVOR1RIXzg=::bWVtX2lmX2J1cnN0bGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ09MQUREUl9XSURUSA==::QUREUl9XSURUSF8xMg==::bWVtX2lmX2NvbGFkZHJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfUEVSX1JBTks=::TUVNX0lGX0NTX1BFUl9SQU5LXzE=::bWVtX2lmX2NzX3Blcl9yYW5r"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfV0lEVEg=::TUVNX0lGX0NTX1dJRFRIXzE=::bWVtX2lmX2NzX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFfUEVSX0NISVA=::TUVNX0lGX0RRX1BFUl9DSElQXzg=::bWVtX2lmX2RxX3Blcl9jaGlw"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFTX1dJRFRI::RFFTX1dJRFRIXzQ=::bWVtX2lmX2Rxc193aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFdJRFRI::TUVNX0lGX0RXSURUSF8zMg==::bWVtX2lmX2R3aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfTUVNVFlQRQ==::RERSM19TRFJBTQ==::bWVtX2lmX21lbXR5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfUk9XQUREUl9XSURUSA==::QUREUl9XSURUSF8xNg==::bWVtX2lmX3Jvd2FkZHJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfU1BFRURCSU4=::RERSM18xMDY2XzZfNl82::bWVtX2lmX3NwZWVkYmlu"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENDRA==::VENDRF80::bWVtX2lmX3RjY2Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENM::VENMXzY=::bWVtX2lmX3RjbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENXTA==::VENXTF81::bWVtX2lmX3Rjd2w="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVEZBVw==::VEZBV18xNg==::bWVtX2lmX3RmYXc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJBUw==::VFJBU18xNg==::bWVtX2lmX3RyYXM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJD::VFJDXzIy::bWVtX2lmX3RyYw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJDRA==::VFJDRF82::bWVtX2lmX3RyY2Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJQ::VFJQXzY=::bWVtX2lmX3RycA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJSRA==::VFJSRF80::bWVtX2lmX3RycmQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJUUA==::VFJUUF80::bWVtX2lmX3RydHA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdS::VFdSXzY=::bWVtX2lmX3R3cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdUUg==::VFdUUl80::bWVtX2lmX3R3dHI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NTVJfQ0ZHX01FTV9CTA==::TVBfQkxfOA==::bW1yX2NmZ19tZW1fYmw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9PVVRQVVRfUkVHRA==::RElTQUJMRUQ=::b3V0cHV0X3JlZ2Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QRE5fRVhJVF9DWUNMRVM=::U0xPV19FWElU::cGRuX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8w::RkFMU0U=::cmRfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8x::RkFMU0U=::cmRfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8y::RkFMU0U=::cmRfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8z::RkFMU0U=::cmRfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRUFEX09EVF9DSElQ::T0RUX0RJU0FCTEVE::cmVhZF9vZHRfY2hpcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRU9SREVSX0RBVEE=::REFUQV9SRU9SREVSSU5H::cmVvcmRlcl9kYXRh"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMA==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMQ==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMg==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMw==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMg==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMw==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9URVNUX01PREU=::Tk9STUFMX01PREU=::dGVzdF9tb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMg==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMw==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMg==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMw==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzA=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzE=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzI=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzM=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX0VDQ19FTg==::RElTQUJMRQ==::dXNlcl9lY2NfZW4="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8wX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8xX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8yX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8zX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8w::RkFMU0U=::d3JfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8x::RkFMU0U=::d3JfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8y::RkFMU0U=::d3JfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8z::RkFMU0U=::d3JfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUklURV9PRFRfQ0hJUA==::T0RUX0RJU0FCTEVE::d3JpdGVfb2R0X2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQVVUT19QRF9DWUNMRVM=::MA==::bWVtX2F1dG9fcGRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMg==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMw==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1Q=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1RfRElGRl9CQU5L::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0X2RpZmZfYmFuaw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19QQ0g=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcGNo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19SRFdS::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcmR3cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfcGVyaW9k"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0ZPVVJfQUNUX1RPX0FDVA==::MA==::ZXh0cmFfY3RsX2Nsa19mb3VyX2FjdF90b19hY3Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9BTExfVE9fVkFMSUQ=::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfYWxsX3RvX3ZhbGlk"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fcGVyaW9k"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa19yZF9hcF90b192YWxpZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19wY2g="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0JD::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9iYw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19aUV9DQUw=::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fenFfY2Fs"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa193cl9hcF90b192YWxpZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19wY2g="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0JD::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9iYw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJFRkk=::MzEyMA==::bWVtX2lmX3RyZWZp"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJGQw==::MzQ=::bWVtX2lmX3RyZmM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BU0s=::MA==::YXR0cl9jb3VudGVyX29uZV9tYXNr"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BVENI::MA==::YXR0cl9jb3VudGVyX29uZV9tYXRjaA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVNL::MA==::YXR0cl9jb3VudGVyX3plcm9fbWFzaw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVRDSA==::MA==::YXR0cl9jb3VudGVyX3plcm9fbWF0Y2g="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0RFQlVHX1NFTEVDVF9CWVRF::MA==::YXR0cl9kZWJ1Z19zZWxlY3RfYnl0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19QT1dFUl9TQVZJTkdfRVhJVF9DWUNMRVM=::NQ==::cG93ZXJfc2F2aW5nX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQ0xLX0VOVFJZX0NZQ0xFUw==::MTA=::bWVtX2Nsa19lbnRyeV9jeWNsZXM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfSU5URVJSVVBU::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X2ludGVycnVwdA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfVEVSTUlOQVRF::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X3Rlcm1pbmF0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8wX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MA==::YXZfcG9ydF8wX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8wX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MA==::Y3ZfcG9ydF8wX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzA=::MA==::VEdfVEVNUF9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8xX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MQ==::YXZfcG9ydF8xX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8xX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MQ==::Y3ZfcG9ydF8xX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzE=::MA==::VEdfVEVNUF9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8yX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mg==::YXZfcG9ydF8yX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8yX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mg==::Y3ZfcG9ydF8yX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzI=::MA==::VEdfVEVNUF9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8zX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mw==::YXZfcG9ydF8zX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8zX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mw==::Y3ZfcG9ydF8zX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzM=::MA==::VEdfVEVNUF9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF80X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NA==::YXZfcG9ydF80X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF80X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NA==::Y3ZfcG9ydF80X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzQ=::MA==::VEdfVEVNUF9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF81X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NQ==::YXZfcG9ydF81X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF81X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NQ==::Y3ZfcG9ydF81X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzU=::MA==::VEdfVEVNUF9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=::ZmFsc2U=::Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfQ0ZH::dHJ1ZQ==::TUFYMTBfQ0ZH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9XRVJfT0ZfVFdPX0JVUw==::ZmFsc2U=::R2VuZXJhdGUgcG93ZXItb2YtMiBkYXRhIGJ1cyB3aWR0aHMgZm9yIFFzeXMgb3IgU09QQyBCdWlsZGVy"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U09QQ19DT01QQVRfUkVTRVQ=::ZmFsc2U=::R2VuZXJhdGUgU09QQyBCdWlsZGVyIGNvbXBhdGlibGUgcmVzZXRz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX01BWF9TSVpF::NA==::TWF4aW11bSBBdmFsb24tTU0gYnVyc3QgbGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEU=::dHJ1ZQ==::RW5hYmxlIEF2YWxvbi1NTSBieXRlLWVuYWJsZSBzaWduYWw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RW5hYmxlIEF2YWxvbiBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RFRVBfUE9XRVJETl9FTg==::ZmFsc2U=::RW5hYmxlIERlZXAgUG93ZXItRG93biBDb250cm9scw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSF9FTg==::ZmFsc2U=::RW5hYmxlIFNlbGYtUmVmcmVzaCBDb250cm9scw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19QT1dFUkROX0VO::ZmFsc2U=::RW5hYmxlIEF1dG8gUG93ZXItRG93bg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNIX0VO::ZmFsc2U=::RW5hYmxlIFVzZXIgQXV0by1SZWZyZXNoIENvbnRyb2xz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::RW5hYmxlIEF1dG8tUHJlY2hhcmdlIENvbnRyb2w="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1pRQ0FMX0VO::ZmFsc2U=::RW5hYmxlIFpRIENhbGlicmF0aW9uIENvbnRyb2w="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9PUkRFUg==::MA==::TG9jYWwtdG8tTWVtb3J5IEFkZHJlc3MgTWFwcGluZw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0xPT0tfQUhFQURfREVQVEg=::NA==::Q29tbWFuZCBRdWV1ZSBMb29rLUFoZWFkIERlcHRo"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9MQVRFTkNZ::NQ==::UmVkdWNlIENvbnRyb2xsZXIgTGF0ZW5jeSBCeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFT1JERVJfREFUQQ==::dHJ1ZQ==::RW5hYmxlIFJlb3JkZXJpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlZFX0xJTUlU::MTA=::U3RhcnZhdGlvbiBsaW1pdCBmb3IgZWFjaCBjb21tYW5k"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::RW5hYmxlIEVycm9yIERldGVjdGlvbiBhbmQgQ29ycmVjdGlvbiBMb2dpYw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0hSQl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIGhhbGYgcmF0ZSBicmlkZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::RW5hYmxlIE11bHRpLWNhc3QgV3JpdGUgQ29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RZTkFNSUNfQkFOS19BTExPQ0FUSU9O::ZmFsc2U=::RW5hYmxlIHJlZHVjZWQgYmFuayB0cmFja2luZyBmb3IgYXJlYSBvcHRpbWl6YXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVCVUdfTU9ERQ==::ZmFsc2U=::RW5hYmxlIGludGVybmFsIGRlYnVnIHBhcmFtZXRlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JVUlNUX01FUkdF::ZmFsc2U=::RW5hYmxlIGJ1cnN0IG1lcmdpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFQ=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IGludGVycnVwdA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEU=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IHRlcm1pbmF0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TG9jYWwgSUQgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRCVUZGRVJfQUREUl9XSURUSA==::Nw==::UmVhZCBidWZmZXIgYWRkcmVzcyB3aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JCVUZGRVJfQUREUl9XSURUSA==::Ng==::V3JpdGUgYnVmZmVyIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfV1JfQ01E::MTY=::TWF4IHBlbmRpbmcgd3JpdGUgY29tbWFuZHM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkRfQ01E::MzI=::TWF4IHBlbmRpbmcgcmVhZCBjb21tYW5kcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01NX0FEQVBUT1I=::dHJ1ZQ==::VXNlIEF2YWxvbiBNTSBBZGFwdG9y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FYSV9BREFQVE9S::ZmFsc2U=::VXNlIEFYSSBBZGFwdG9y"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NNRF9RVUVVRV9ERVBUSA==::OA==::Q1RMX0NNRF9RVUVVRV9ERVBUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9SRUFEX09OTFk=::MQ==::Q1RMX0NTUl9SRUFEX09OTFk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0RBVEFfUkVPUkRFUklOR19UWVBF::SU5URVJfQkFOSw==::UmVvcmRlcmluZyB0eXBl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09GX1BPUlRT::MQ==::TnVtYmVyIG9mIHBvcnRz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JPTkRJTkc=::ZmFsc2U=::RXhwb3J0IGJvbmRpbmcgaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1VTRVJfRUND::ZmFsc2U=::RXhwYW5kIEF2YWxvbi1NTSBkYXRhIGZvciBFQ0M="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVA==::MzIsMzIsMzIsMzIsMzIsMzI=::V2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVA==::MSwxLDEsMSwxLDE=::UHJpb3JpdHk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlQ=::MCwwLDAsMCwwLDA=::V2VpZ2h0"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JU::QmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWwsQmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWw=::VHlwZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::ZmFsc2U=::R0VORVJJQ19QTEw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::dHJ1ZQ==::UkVBRF9GSUZPX0hBTEZfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTkx::UEhZX1ZFUlNJT05fTlVNQkVS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::ZmFsc2U=::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::ZmFsc2U=::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::ZmFsc2U=::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::SEFMRg==::VEJfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::OA==::VEJfTUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::MTAwLjA=::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::MTAwLjAgTUh6::UkVGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MTAuMA==::UkVGX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MTAwMDAuMA==::UkVGX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::Mw==::UExMX01FTV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MQ==::UExMX01FTV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MTUwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MTUwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::Mw==::UExMX0FGSV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::Mg==::UExMX0FGSV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::Mw==::UExMX1dSSVRFX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MQ==::UExMX1dSSVRFX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::MC4w::UExMX05JT1NfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::MA==::UExMX05JT1NfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::MA==::UExMX05JT1NfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::MA==::UExMX0NPTkZJR19DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MA==::UExMX0NPTkZJR19DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::ZmFsc2U=::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::MC4w::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MA==::UExMX01FTV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MQ==::UExMX01FTV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::MA==::UExMX0FGSV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::Mg==::UExMX0FGSV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::MA==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MA==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::MA==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MA==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MA==::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREVfQ0FDSEU=::Ng==::U1BFRURfR1JBREVfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::TUVNX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MTAwLjA=::UkVGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::SGFsZg==::UkFURV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::TklPUw==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::ZmFsc2U=::UExMX0NMS19QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklYX1JFQURfTEFURU5DWQ==::OA==::Rml4ZWQgUmVhZCBMYXRlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MA==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NA==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MQ==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::ZmFsc2U=::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::Mg==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::OTAwMA==::RFFTX1BIQVNFX1NISUZU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::Mw==::SU9fRFFTX0lOX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::Mw==::SU9fRFFTX09VVF9SRVNFUlZF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MTQ=::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::NA==::Q0FMSUJfTEZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::MTI=::Q0FMSUJfVkZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::NTA=::REVMQVlfUEVSX0RDSEFJTl9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::NTA=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::Nw==::RFFTX0VOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MTU=::RFFTX0lOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MTU=::SU9fSU5fREVMQVlfTUFY"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MTU=::SU9fT1VUMV9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::Nw==::SU9fT1VUMl9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::NQ==::TUVNX1RfV0w="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::NQ==::TUVNX1RfUkw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::ZmFsc2U=::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::dHJ1ZQ==::TUFYMTBfUlRMX1NFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX09OTFk=::ZmFsc2U=::R2VuZXJhdGUgUEhZIG9ubHk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::U2tpcA==::QXV0by1jYWxpYnJhdGlvbiBtb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zMg==::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yMg==::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xNg==::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNDU=::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC4yNDQz::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC4yMTkyOQ==::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::MC4wMjI4Ng==::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::MC4wMjI4Ng==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wNDQyOQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wNDQyOQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMTgwNg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wNDI0Ng==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::LTAuMDExNTI=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wNzgwMQ==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::LTAuMDQ3MDk=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREX0VYVEVSTkFMX1NFUV9ERUJVR19OSU9T::ZmFsc2U=::QWRkIGV4dGVybmFsIE5pb3MgdG8gY29ubmVjdCB0byBzZXF1ZW5jZXIgZGVidWcgaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RURfRVhQT1JUX1NFUV9ERUJVRw==::ZmFsc2U=::RXhwb3J0IHNlcXVlbmNlciBkZWJ1ZyBpbnRlcmZhY2UgZnJvbSBleGFtcGxlIGRlc2lnbg=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREX0VGRklDSUVOQ1lfTU9OSVRPUg==::ZmFsc2U=::RW5hYmxlIHRoZSBFZmZpY2llbmN5IE1vbml0b3IgYW5kIFByb3RvY29sIENoZWNrZXIgb24gdGhlIENvbnRyb2xsZXIgQXZhbG9uIEludGVyZmFjZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU19SQU1fTUVNX0lOSVQ=::ZmFsc2U=::RW5hYmxlIHN1cHBvcnQgZm9yIE5pb3MgSUkgTW9kZWxTaW0gZmxvdyBpbiBFY2xpcHNl"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU19SQU1fSU5URVJOQUw=::ZmFsc2U=::RU5BQkxFX0FCU19SQU1fSU5URVJOQUw="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0FCU1RSQUNUX1JBTQ==::ZmFsc2U=::RU5BQkxFX0FCU1RSQUNUX1JBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUJTX1JBTV9NRU1fSU5JVF9GSUxFTkFNRQ==::bWVtaW5pdA==::TWVtb3J5IGluaXRpYWxpemF0aW9uIGZpbGUgYmFzZW5hbWU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Ng==::RExMX0RFTEFZX0NUUkxfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTQ=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGRyM19yYW1fYzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEREUjMgTmV4dGdlbiBNZW1vcnkgQ29udHJvbGxlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEREUjMgTmV4dGdlbiBNZW1vcnkgQ29udHJvbGxlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTX1dJRFRI::MQ==::Q1RMX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0JFX1dJRFRI::NA==::QVZMX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19DU1JfRU5BQkxFRA==::ZmFsc2U=::Q1RMX0VDQ19DU1JfRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFdJRFRIX1JBVElP::NA==::RFdJRFRIX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09EVF9FTkFCTEVE::ZmFsc2U=::Q1RMX09EVF9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09VVFBVVF9SRUdE::ZmFsc2U=::Q1RMX09VVFBVVF9SRUdE"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::Q1RMX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9XX0xBVEVOQ1k=::ZmFsc2U=::TE9XX0xBVEVOQ1k="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9UWVBF::bmV4dGdlbl92MTEw::Q09OVFJPTExFUl9UWVBF"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1RCUF9OVU0=::NA==::Q1RMX1RCUF9OVU0="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNI::MA==::Q1RMX1VTUl9SRUZSRVNI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSA==::MA==::Q1RMX1NFTEZfUkVGUkVTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RZUEU=::Mg==::Q0ZHX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0lOVEVSRkFDRV9XSURUSA==::OA==::Q0ZHX0lOVEVSRkFDRV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0JVUlNUX0xFTkdUSA==::OA==::Q0ZHX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0FERFJfT1JERVI=::MA==::Q0ZHX0FERFJfT1JERVI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BETl9FWElUX0NZQ0xFUw==::MTA=::Q0ZHX1BETl9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==::NQ==::Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT::MjA=::Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==::NTEy::Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=::MQ==::Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==::MQ==::Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1dSSVRFX09EVF9DSElQ::MQ==::Q0ZHX1dSSVRFX09EVF9DSElQ"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFQURfT0RUX0NISVA=::MA==::Q0ZHX1JFQURfT0RUX0NISVA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfQ1NfV0lEVEg=::MA==::TE9DQUxfQ1NfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0NMUl9JTlRS::MA==::Q0ZHX0NMUl9JTlRS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VOQUJMRV9OT19ETQ==::MA==::Q0ZHX0VOQUJMRV9OT19ETQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FERF9MQVQ=::MA==::TUVNX0FERF9MQVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VSUkNNRF9GSUZPX1JFRw==::MA==::Q0ZHX0VSUkNNRF9GSUZPX1JFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VDQ19ERUNPREVSX1JFRw==::MA==::Q0ZHX0VDQ19ERUNPREVSX1JFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=::ZmFsc2U=::Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NUQVJWRV9MSU1JVA==::MTA=::Q0ZHX1NUQVJWRV9MSU1JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fUERfQ1lDTEVT::MA==::TUVNX0FVVE9fUERfQ1lDTEVT"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8w::MA==::UFJJT1JJVFlfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMA==::MA==::V0VJR0hUX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMA==::NQ==::TFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMA==::NQ==::TVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMA==::NQ==::TFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMA==::NQ==::TVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8x::MA==::UFJJT1JJVFlfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMQ==::MA==::V0VJR0hUX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMQ==::NQ==::TFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMQ==::NQ==::TVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMQ==::NQ==::TFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMQ==::NQ==::TVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8y::MA==::UFJJT1JJVFlfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMg==::MA==::V0VJR0hUX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMg==::NQ==::TFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMg==::NQ==::TVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMg==::NQ==::TFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMg==::NQ==::TVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8z::MA==::UFJJT1JJVFlfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMw==::MA==::V0VJR0hUX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMw==::NQ==::TFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMw==::NQ==::TVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMw==::NQ==::TFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMw==::NQ==::TVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF80::MA==::UFJJT1JJVFlfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNA==::MA==::V0VJR0hUX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNA==::NQ==::TFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNA==::NQ==::TVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNA==::NQ==::TFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNA==::NQ==::TVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF81::MA==::UFJJT1JJVFlfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNQ==::MA==::V0VJR0hUX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNQ==::NQ==::TFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNQ==::NQ==::TVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNQ==::NQ==::TFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNQ==::NQ==::TVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1JGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFJlYWQtRGF0YSBGSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1dGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFdyaXRlLURhdGEgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfT05FX1JFU0VU::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX29uZV9yZXNldA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfWkVST19SRVNFVA==::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX3plcm9fcmVzZXQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX1NUQVRJQ19DT05GSUdfVkFMSUQ=::RElTQUJMRUQ=::YXR0cl9zdGF0aWNfY29uZmlnX3ZhbGlk"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DQUxfUkVR::RElTQUJMRUQ=::Y2FsX3JlcQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfQlVSU1RfTEVOR1RI::QkxfOA==::Y2ZnX2J1cnN0X2xlbmd0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfSU5URVJGQUNFX1dJRFRI::RFdJRFRIXzMy::Y2ZnX2ludGVyZmFjZV93aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU1RBUlZFX0xJTUlU::U1RBUlZFX0xJTUlUXzMy::Y2ZnX3N0YXJ2ZV9saW1pdA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfVFlQRQ==::RERSMw==::Y2ZnX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMg==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMw==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTFJfSU5UUg==::Tk9fQ0xSX0lOVFI=::Y2xyX2ludHI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQwX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQxX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQyX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQzX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ0X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ1X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfQUREUl9PUkRFUg==::Q0hJUF9CQU5LX1JPV19DT0w=::Y3RsX2FkZHJfb3JkZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX0VOQUJMRUQ=::Q1RMX0VDQ19ESVNBQkxFRA==::Y3RsX2VjY19lbmFibGVk"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX1JNV19FTkFCTEVE::Q1RMX0VDQ19STVdfRElTQUJMRUQ=::Y3RsX2VjY19ybXdfZW5hYmxlZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfUkVHRElNTV9FTkFCTEVE::UkVHRElNTV9ESVNBQkxFRA==::Y3RsX3JlZ2RpbW1fZW5hYmxlZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfVVNSX1JFRlJFU0g=::Q1RMX1VTUl9SRUZSRVNIX0RJU0FCTEVE::Y3RsX3Vzcl9yZWZyZXNo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVFJMX1dJRFRI::REFUQV9XSURUSF82NF9CSVQ=::Y3RybF93aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERUxBWV9CT05ESU5H::Qk9ORElOR19MQVRFTkNZXzA=::ZGVsYXlfYm9uZGluZw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERlhfQllQQVNTX0VOQUJMRQ==::REZYX0JZUEFTU19ESVNBQkxFRA==::ZGZ4X2J5cGFzc19lbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ESVNBQkxFX01FUkdJTkc=::TUVSR0lOR19FTkFCTEVE::ZGlzYWJsZV9tZXJnaW5n"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FQ0NfRFFfV0lEVEg=::RUNDX0RRX1dJRFRIXzA=::ZWNjX2RxX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQVRQRw==::RElTQUJMRUQ=::ZW5hYmxlX2F0cGc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR19XUkFQQkFDSw==::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfd3JhcGJhY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRFFTX1RSQUNLSU5H::RElTQUJMRUQ=::ZW5hYmxlX2Rxc190cmFja2luZw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRUNDX0NPREVfT1ZFUldSSVRFUw==::RElTQUJMRUQ=::ZW5hYmxlX2VjY19jb2RlX292ZXJ3cml0ZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRkFTVF9FWElUX1BQRA==::RElTQUJMRUQ=::ZW5hYmxlX2Zhc3RfZXhpdF9wcGQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfSU5UUg==::RElTQUJMRUQ=::ZW5hYmxlX2ludHI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfTk9fRE0=::RElTQUJMRUQ=::ZW5hYmxlX25vX2Rt"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfUElQRUxJTkVHTE9CQUw=::RElTQUJMRUQ=::ZW5hYmxlX3BpcGVsaW5lZ2xvYmFs"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HQU5HRURfQVJG::RElTQUJMRUQ=::Z2FuZ2VkX2FyZg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fREJF::R0VOX0RCRV9ESVNBQkxFRA==::Z2VuX2RiZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fU0JF::R0VOX1NCRV9ESVNBQkxFRA==::Z2VuX3NiZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9JTkNfU1lOQw==::RklGT19TRVRfMg==::aW5jX3N5bmM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9MT0NBTF9JRl9DU19XSURUSA==::QUREUl9XSURUSF8y::bG9jYWxfaWZfY3Nfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0NPUlJfRFJPUFBFRF9JTlRS::RElTQUJMRUQ=::bWFza19jb3JyX2Ryb3BwZWRfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0RCRV9JTlRS::RElTQUJMRUQ=::bWFza19kYmVfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX1NCRV9JTlRS::RElTQUJMRUQ=::bWFza19zYmVfaW50cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQUw=::QUxfMA==::bWVtX2lmX2Fs"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQkFOS0FERFJfV0lEVEg=::QUREUl9XSURUSF8z::bWVtX2lmX2JhbmthZGRyX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQlVSU1RMRU5HVEg=::TUVNX0lGX0JVUlNUTEVOR1RIXzg=::bWVtX2lmX2J1cnN0bGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ09MQUREUl9XSURUSA==::QUREUl9XSURUSF8xMg==::bWVtX2lmX2NvbGFkZHJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfUEVSX1JBTks=::TUVNX0lGX0NTX1BFUl9SQU5LXzE=::bWVtX2lmX2NzX3Blcl9yYW5r"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfV0lEVEg=::TUVNX0lGX0NTX1dJRFRIXzE=::bWVtX2lmX2NzX3dpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFfUEVSX0NISVA=::TUVNX0lGX0RRX1BFUl9DSElQXzg=::bWVtX2lmX2RxX3Blcl9jaGlw"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFTX1dJRFRI::RFFTX1dJRFRIXzQ=::bWVtX2lmX2Rxc193aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFdJRFRI::TUVNX0lGX0RXSURUSF8zMg==::bWVtX2lmX2R3aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfTUVNVFlQRQ==::RERSM19TRFJBTQ==::bWVtX2lmX21lbXR5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfUk9XQUREUl9XSURUSA==::QUREUl9XSURUSF8xNg==::bWVtX2lmX3Jvd2FkZHJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfU1BFRURCSU4=::RERSM18xMDY2XzZfNl82::bWVtX2lmX3NwZWVkYmlu"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENDRA==::VENDRF80::bWVtX2lmX3RjY2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENM::VENMXzY=::bWVtX2lmX3RjbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENXTA==::VENXTF81::bWVtX2lmX3Rjd2w="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVEZBVw==::VEZBV18xNg==::bWVtX2lmX3RmYXc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJBUw==::VFJBU18xNg==::bWVtX2lmX3RyYXM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJD::VFJDXzIy::bWVtX2lmX3RyYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJDRA==::VFJDRF82::bWVtX2lmX3RyY2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJQ::VFJQXzY=::bWVtX2lmX3RycA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJSRA==::VFJSRF80::bWVtX2lmX3RycmQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJUUA==::VFJUUF80::bWVtX2lmX3RydHA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdS::VFdSXzY=::bWVtX2lmX3R3cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdUUg==::VFdUUl80::bWVtX2lmX3R3dHI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NTVJfQ0ZHX01FTV9CTA==::TVBfQkxfOA==::bW1yX2NmZ19tZW1fYmw="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9PVVRQVVRfUkVHRA==::RElTQUJMRUQ=::b3V0cHV0X3JlZ2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QRE5fRVhJVF9DWUNMRVM=::U0xPV19FWElU::cGRuX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8w::RkFMU0U=::cmRfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8x::RkFMU0U=::cmRfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8y::RkFMU0U=::cmRfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8z::RkFMU0U=::cmRfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRUFEX09EVF9DSElQ::T0RUX0RJU0FCTEVE::cmVhZF9vZHRfY2hpcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRU9SREVSX0RBVEE=::REFUQV9SRU9SREVSSU5H::cmVvcmRlcl9kYXRh"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMA==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMQ==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMg==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMw==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMg==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMw==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9URVNUX01PREU=::Tk9STUFMX01PREU=::dGVzdF9tb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMg==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMw==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMg==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMw==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzA=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzE=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzI=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzM=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX0VDQ19FTg==::RElTQUJMRQ==::dXNlcl9lY2NfZW4="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8wX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8xX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8yX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8zX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8w::RkFMU0U=::d3JfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8x::RkFMU0U=::d3JfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8y::RkFMU0U=::d3JfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8z::RkFMU0U=::d3JfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUklURV9PRFRfQ0hJUA==::T0RUX0RJU0FCTEVE::d3JpdGVfb2R0X2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQVVUT19QRF9DWUNMRVM=::MA==::bWVtX2F1dG9fcGRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMg==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMw==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1Q=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1RfRElGRl9CQU5L::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0X2RpZmZfYmFuaw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19QQ0g=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcGNo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19SRFdS::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcmR3cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfcGVyaW9k"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0ZPVVJfQUNUX1RPX0FDVA==::MA==::ZXh0cmFfY3RsX2Nsa19mb3VyX2FjdF90b19hY3Q="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9BTExfVE9fVkFMSUQ=::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfYWxsX3RvX3ZhbGlk"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fcGVyaW9k"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa19yZF9hcF90b192YWxpZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19wY2g="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0JD::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9iYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19aUV9DQUw=::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fenFfY2Fs"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa193cl9hcF90b192YWxpZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19wY2g="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0JD::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9iYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJFRkk=::MzEyMA==::bWVtX2lmX3RyZWZp"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJGQw==::MzQ=::bWVtX2lmX3RyZmM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BU0s=::MA==::YXR0cl9jb3VudGVyX29uZV9tYXNr"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BVENI::MA==::YXR0cl9jb3VudGVyX29uZV9tYXRjaA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVNL::MA==::YXR0cl9jb3VudGVyX3plcm9fbWFzaw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVRDSA==::MA==::YXR0cl9jb3VudGVyX3plcm9fbWF0Y2g="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0RFQlVHX1NFTEVDVF9CWVRF::MA==::YXR0cl9kZWJ1Z19zZWxlY3RfYnl0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19QT1dFUl9TQVZJTkdfRVhJVF9DWUNMRVM=::NQ==::cG93ZXJfc2F2aW5nX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQ0xLX0VOVFJZX0NZQ0xFUw==::MTA=::bWVtX2Nsa19lbnRyeV9jeWNsZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfSU5URVJSVVBU::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X2ludGVycnVwdA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfVEVSTUlOQVRF::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X3Rlcm1pbmF0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8wX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MA==::YXZfcG9ydF8wX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8wX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MA==::Y3ZfcG9ydF8wX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzA=::MA==::VEdfVEVNUF9QT1JUXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8xX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MQ==::YXZfcG9ydF8xX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8xX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MQ==::Y3ZfcG9ydF8xX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzE=::MA==::VEdfVEVNUF9QT1JUXzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8yX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mg==::YXZfcG9ydF8yX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8yX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mg==::Y3ZfcG9ydF8yX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzI=::MA==::VEdfVEVNUF9QT1JUXzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8zX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mw==::YXZfcG9ydF8zX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8zX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mw==::Y3ZfcG9ydF8zX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzM=::MA==::VEdfVEVNUF9QT1JUXzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF80X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NA==::YXZfcG9ydF80X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF80X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NA==::Y3ZfcG9ydF80X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzQ=::MA==::VEdfVEVNUF9QT1JUXzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF81X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NQ==::YXZfcG9ydF81X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF81X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NQ==::Y3ZfcG9ydF81X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzU=::MA==::VEdfVEVNUF9QT1JUXzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=::ZmFsc2U=::Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfQ0ZH::dHJ1ZQ==::TUFYMTBfQ0ZH"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9XRVJfT0ZfVFdPX0JVUw==::ZmFsc2U=::R2VuZXJhdGUgcG93ZXItb2YtMiBkYXRhIGJ1cyB3aWR0aHMgZm9yIFFzeXMgb3IgU09QQyBCdWlsZGVy"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U09QQ19DT01QQVRfUkVTRVQ=::ZmFsc2U=::R2VuZXJhdGUgU09QQyBCdWlsZGVyIGNvbXBhdGlibGUgcmVzZXRz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX01BWF9TSVpF::NA==::TWF4aW11bSBBdmFsb24tTU0gYnVyc3QgbGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEU=::dHJ1ZQ==::RW5hYmxlIEF2YWxvbi1NTSBieXRlLWVuYWJsZSBzaWduYWw="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RW5hYmxlIEF2YWxvbiBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RFRVBfUE9XRVJETl9FTg==::ZmFsc2U=::RW5hYmxlIERlZXAgUG93ZXItRG93biBDb250cm9scw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSF9FTg==::ZmFsc2U=::RW5hYmxlIFNlbGYtUmVmcmVzaCBDb250cm9scw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19QT1dFUkROX0VO::ZmFsc2U=::RW5hYmxlIEF1dG8gUG93ZXItRG93bg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNIX0VO::ZmFsc2U=::RW5hYmxlIFVzZXIgQXV0by1SZWZyZXNoIENvbnRyb2xz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::RW5hYmxlIEF1dG8tUHJlY2hhcmdlIENvbnRyb2w="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1pRQ0FMX0VO::ZmFsc2U=::RW5hYmxlIFpRIENhbGlicmF0aW9uIENvbnRyb2w="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9PUkRFUg==::MA==::TG9jYWwtdG8tTWVtb3J5IEFkZHJlc3MgTWFwcGluZw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0xPT0tfQUhFQURfREVQVEg=::NA==::Q29tbWFuZCBRdWV1ZSBMb29rLUFoZWFkIERlcHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9MQVRFTkNZ::NQ==::UmVkdWNlIENvbnRyb2xsZXIgTGF0ZW5jeSBCeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFT1JERVJfREFUQQ==::dHJ1ZQ==::RW5hYmxlIFJlb3JkZXJpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlZFX0xJTUlU::MTA=::U3RhcnZhdGlvbiBsaW1pdCBmb3IgZWFjaCBjb21tYW5k"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::RW5hYmxlIEVycm9yIERldGVjdGlvbiBhbmQgQ29ycmVjdGlvbiBMb2dpYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0hSQl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIGhhbGYgcmF0ZSBicmlkZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::RW5hYmxlIE11bHRpLWNhc3QgV3JpdGUgQ29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RZTkFNSUNfQkFOS19BTExPQ0FUSU9O::ZmFsc2U=::RW5hYmxlIHJlZHVjZWQgYmFuayB0cmFja2luZyBmb3IgYXJlYSBvcHRpbWl6YXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVCVUdfTU9ERQ==::ZmFsc2U=::RW5hYmxlIGludGVybmFsIGRlYnVnIHBhcmFtZXRlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JVUlNUX01FUkdF::ZmFsc2U=::RW5hYmxlIGJ1cnN0IG1lcmdpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFQ=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IGludGVycnVwdA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEU=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IHRlcm1pbmF0ZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TG9jYWwgSUQgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRCVUZGRVJfQUREUl9XSURUSA==::Nw==::UmVhZCBidWZmZXIgYWRkcmVzcyB3aWR0aA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JCVUZGRVJfQUREUl9XSURUSA==::Ng==::V3JpdGUgYnVmZmVyIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfV1JfQ01E::MTY=::TWF4IHBlbmRpbmcgd3JpdGUgY29tbWFuZHM="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkRfQ01E::MzI=::TWF4IHBlbmRpbmcgcmVhZCBjb21tYW5kcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01NX0FEQVBUT1I=::dHJ1ZQ==::VXNlIEF2YWxvbiBNTSBBZGFwdG9y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FYSV9BREFQVE9S::ZmFsc2U=::VXNlIEFYSSBBZGFwdG9y"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RF::ZmFsc2U=::SGFyZENvcHkgQ29tcGF0aWJpbGl0eSBNb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NNRF9RVUVVRV9ERVBUSA==::OA==::Q1RMX0NNRF9RVUVVRV9ERVBUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9SRUFEX09OTFk=::MQ==::Q1RMX0NTUl9SRUFEX09OTFk="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0RBVEFfUkVPUkRFUklOR19UWVBF::SU5URVJfQkFOSw==::UmVvcmRlcmluZyB0eXBl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09GX1BPUlRT::MQ==::TnVtYmVyIG9mIHBvcnRz"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JPTkRJTkc=::ZmFsc2U=::RXhwb3J0IGJvbmRpbmcgaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1VTRVJfRUND::ZmFsc2U=::RXhwYW5kIEF2YWxvbi1NTSBkYXRhIGZvciBFQ0M="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVA==::MzIsMzIsMzIsMzIsMzIsMzI=::V2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVA==::MSwxLDEsMSwxLDE=::UHJpb3JpdHk="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlQ=::MCwwLDAsMCwwLDA=::V2VpZ2h0"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JU::QmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWwsQmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWw=::VHlwZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::ZmFsc2U=::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_NAME "YWx0X21lbV9kZHJ4X21tX3N0X2NvbnZlcnRlcg=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIE5leHRnZW4gTWVtb3J5IENvbnRyb2xsZXIgTU0tU1QgQWRhcHRlcg=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE5leHRnZW4gTWVtb3J5IENvbnRyb2xsZXIgTU0tU1QgQWRhcHRlcg=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEg=::MjU=::QVZMX0FERFJfV0lEVEg="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEg=::MzI=::QVZMX0RBVEFfV0lEVEg="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TE9DQUxfSURfV0lEVEg="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0RXSURUSF9SQVRJTw==::NA==::Q0ZHX0RXSURUSF9SQVRJTw=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTg==::MzI=::TUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTg=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0JZVEVfRU5BQkxF::dHJ1ZQ==::QVZMX0JZVEVfRU5BQkxF"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::Q1RMX0FVVE9QQ0hfRU4="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::TVVMVElDQVNUX0VO"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ=="
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::Q1RMX0VDQ19FTkFCTEVE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_NAME "YWx0X21lbV9pZl9uZXh0Z2VuX2RkcjNfY29udHJvbGxlcl9jb3Jl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEREUjMgTmV4dGdlbiBNZW1vcnkgQ29udHJvbGxlciBDb3Jl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEREUjMgTmV4dGdlbiBNZW1vcnkgQ29udHJvbGxlciBDb3Jl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTX1dJRFRI::MQ==::Q1RMX0NTX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0JFX1dJRFRI::NA==::QVZMX0JFX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NZTUJPTF9XSURUSA==::OA==::QVZMX1NZTUJPTF9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xT::NA==::QVZMX05VTV9TWU1CT0xT"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX1NJWkVfV0lEVEg=::Mw==::QVZMX1NJWkVfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19DU1JfRU5BQkxFRA==::ZmFsc2U=::Q1RMX0VDQ19DU1JfRU5BQkxFRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFdJRFRIX1JBVElP::NA==::RFdJRFRIX1JBVElP"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09EVF9FTkFCTEVE::ZmFsc2U=::Q1RMX09EVF9FTkFCTEVE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX09VVFBVVF9SRUdE::ZmFsc2U=::Q1RMX09VVFBVVF9SRUdE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfNDBfNzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI=::MQ==::Q1RMX0VDQ19NVUxUSVBMRVNfMTZfMjRfNDBfNzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::Q1RMX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9XX0xBVEVOQ1k=::ZmFsc2U=::TE9XX0xBVEVOQ1k="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9UWVBF::bmV4dGdlbl92MTEw::Q09OVFJPTExFUl9UWVBF"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1RCUF9OVU0=::NA==::Q1RMX1RCUF9OVU0="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNI::MA==::Q1RMX1VTUl9SRUZSRVNI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSA==::MA==::Q1RMX1NFTEZfUkVGUkVTSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RZUEU=::Mg==::Q0ZHX1RZUEU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0lOVEVSRkFDRV9XSURUSA==::OA==::Q0ZHX0lOVEVSRkFDRV9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0JVUlNUX0xFTkdUSA==::OA==::Q0ZHX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0FERFJfT1JERVI=::MA==::Q0ZHX0FERFJfT1JERVI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BETl9FWElUX0NZQ0xFUw==::MTA=::Q0ZHX1BETl9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw==::NQ==::Q0ZHX1BPV0VSX1NBVklOR19FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT::MjA=::Q0ZHX01FTV9DTEtfRU5UUllfQ1lDTEVT"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw==::NTEy::Q0ZHX1NFTEZfUkZTSF9FWElUX0NZQ0xFUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA=::MQ==::Q0ZHX1BPUlRfV0lEVEhfV1JJVEVfT0RUX0NISVA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA==::MQ==::Q0ZHX1BPUlRfV0lEVEhfUkVBRF9PRFRfQ0hJUA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1dSSVRFX09EVF9DSElQ::MQ==::Q0ZHX1dSSVRFX09EVF9DSElQ"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFQURfT0RUX0NISVA=::MA==::Q0ZHX1JFQURfT0RUX0NISVA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfQ1NfV0lEVEg=::MA==::TE9DQUxfQ1NfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0NMUl9JTlRS::MA==::Q0ZHX0NMUl9JTlRS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VOQUJMRV9OT19ETQ==::MA==::Q0ZHX0VOQUJMRV9OT19ETQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FERF9MQVQ=::MA==::TUVNX0FERF9MQVQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFRfSU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U::ZmFsc2U=::Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEVfSU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VSUkNNRF9GSUZPX1JFRw==::MA==::Q0ZHX0VSUkNNRF9GSUZPX1JFRw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0VDQ19ERUNPREVSX1JFRw==::MA==::Q0ZHX0VDQ19ERUNPREVSX1JFRw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k=::ZmFsc2U=::Q1RMX0VOQUJMRV9XREFUQV9QQVRIX0xBVEVOQ1k="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1NUQVJWRV9MSU1JVA==::MTA=::Q0ZHX1NUQVJWRV9MSU1JVA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fUERfQ1lDTEVT::MA==::TUVNX0FVVE9fUERfQ1lDTEVT"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8w::MA==::UFJJT1JJVFlfUE9SVF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMA==::MA==::V0VJR0hUX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMA==::NQ==::TFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMA==::NQ==::TVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMA==::NQ==::TFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMA==::NQ==::TVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8x::MA==::UFJJT1JJVFlfUE9SVF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMQ==::MA==::V0VJR0hUX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMQ==::NQ==::TFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMQ==::NQ==::TVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMQ==::NQ==::TFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMQ==::NQ==::TVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8y::MA==::UFJJT1JJVFlfUE9SVF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMg==::MA==::V0VJR0hUX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMg==::NQ==::TFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMg==::NQ==::TVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMg==::NQ==::TFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMg==::NQ==::TVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF8z::MA==::UFJJT1JJVFlfUE9SVF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfMw==::MA==::V0VJR0hUX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfMw==::NQ==::TFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfMw==::NQ==::TVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfMw==::NQ==::TFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfMw==::NQ==::TVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF80::MA==::UFJJT1JJVFlfUE9SVF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNA==::MA==::V0VJR0hUX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNA==::NQ==::TFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNA==::NQ==::TVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNA==::NQ==::TFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNA==::NQ==::TVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::QVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::QVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVF81::MA==::UFJJT1JJVFlfUE9SVF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlRfNQ==::MA==::V0VJR0hUX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::QVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1dGSUZPX1BPUlRfNQ==::NQ==::TFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1dGSUZPX1BPUlRfNQ==::NQ==::TVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFNCX1JGSUZPX1BPUlRfNQ==::NQ==::TFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVNCX1JGSUZPX1BPUlRfNQ==::NQ==::TVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1JGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFJlYWQtRGF0YSBGSUZP"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxMT0NBVEVEX1dGSUZPX1BPUlQ=::MCxOb25lLE5vbmUsTm9uZSxOb25lLE5vbmU=::QWxsb2NhdGVkIFdyaXRlLURhdGEgRklGTw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfT05FX1JFU0VU::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX29uZV9yZXNldA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX0NPVU5URVJfWkVST19SRVNFVA==::RElTQUJMRUQ=::YXR0cl9jb3VudGVyX3plcm9fcmVzZXQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVFRSX1NUQVRJQ19DT05GSUdfVkFMSUQ=::RElTQUJMRUQ=::YXR0cl9zdGF0aWNfY29uZmlnX3ZhbGlk"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DQUxfUkVR::RElTQUJMRUQ=::Y2FsX3JlcQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfQlVSU1RfTEVOR1RI::QkxfOA==::Y2ZnX2J1cnN0X2xlbmd0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfSU5URVJGQUNFX1dJRFRI::RFdJRFRIXzMy::Y2ZnX2ludGVyZmFjZV93aWR0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfU1RBUlZFX0xJTUlU::U1RBUlZFX0xJTUlUXzMy::Y2ZnX3N0YXJ2ZV9saW1pdA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DRkdfVFlQRQ==::RERSMw==::Y2ZnX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMg==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfMw==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNA==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTE9DS19PRkZfNQ==::RElTQUJMRUQ=::Y2xvY2tfb2ZmXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTFJfSU5UUg==::Tk9fQ0xSX0lOVFI=::Y2xyX2ludHI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQwX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQxX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQyX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQzX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ0X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::Y3BvcnQ1X3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfQUREUl9PUkRFUg==::Q0hJUF9CQU5LX1JPV19DT0w=::Y3RsX2FkZHJfb3JkZXI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX0VOQUJMRUQ=::Q1RMX0VDQ19ESVNBQkxFRA==::Y3RsX2VjY19lbmFibGVk"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfRUNDX1JNV19FTkFCTEVE::Q1RMX0VDQ19STVdfRElTQUJMRUQ=::Y3RsX2VjY19ybXdfZW5hYmxlZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfUkVHRElNTV9FTkFCTEVE::UkVHRElNTV9ESVNBQkxFRA==::Y3RsX3JlZ2RpbW1fZW5hYmxlZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVExfVVNSX1JFRlJFU0g=::Q1RMX1VTUl9SRUZSRVNIX0RJU0FCTEVE::Y3RsX3Vzcl9yZWZyZXNo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9DVFJMX1dJRFRI::REFUQV9XSURUSF82NF9CSVQ=::Y3RybF93aWR0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERUxBWV9CT05ESU5H::Qk9ORElOR19MQVRFTkNZXzA=::ZGVsYXlfYm9uZGluZw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ERlhfQllQQVNTX0VOQUJMRQ==::REZYX0JZUEFTU19ESVNBQkxFRA==::ZGZ4X2J5cGFzc19lbmFibGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9ESVNBQkxFX01FUkdJTkc=::TUVSR0lOR19FTkFCTEVE::ZGlzYWJsZV9tZXJnaW5n"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FQ0NfRFFfV0lEVEg=::RUNDX0RRX1dJRFRIXzA=::ZWNjX2RxX3dpZHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQVRQRw==::RElTQUJMRUQ=::ZW5hYmxlX2F0cGc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQk9ORElOR19XUkFQQkFDSw==::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfd3JhcGJhY2s="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRFFTX1RSQUNLSU5H::RElTQUJMRUQ=::ZW5hYmxlX2Rxc190cmFja2luZw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRUNDX0NPREVfT1ZFUldSSVRFUw==::RElTQUJMRUQ=::ZW5hYmxlX2VjY19jb2RlX292ZXJ3cml0ZXM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfRkFTVF9FWElUX1BQRA==::RElTQUJMRUQ=::ZW5hYmxlX2Zhc3RfZXhpdF9wcGQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfSU5UUg==::RElTQUJMRUQ=::ZW5hYmxlX2ludHI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfTk9fRE0=::RElTQUJMRUQ=::ZW5hYmxlX25vX2Rt"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfUElQRUxJTkVHTE9CQUw=::RElTQUJMRUQ=::ZW5hYmxlX3BpcGVsaW5lZ2xvYmFs"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HQU5HRURfQVJG::RElTQUJMRUQ=::Z2FuZ2VkX2FyZg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fREJF::R0VOX0RCRV9ESVNBQkxFRA==::Z2VuX2RiZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9HRU5fU0JF::R0VOX1NCRV9ESVNBQkxFRA==::Z2VuX3NiZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9JTkNfU1lOQw==::RklGT19TRVRfMg==::aW5jX3N5bmM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9MT0NBTF9JRl9DU19XSURUSA==::QUREUl9XSURUSF8y::bG9jYWxfaWZfY3Nfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0NPUlJfRFJPUFBFRF9JTlRS::RElTQUJMRUQ=::bWFza19jb3JyX2Ryb3BwZWRfaW50cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX0RCRV9JTlRS::RElTQUJMRUQ=::bWFza19kYmVfaW50cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NQVNLX1NCRV9JTlRS::RElTQUJMRUQ=::bWFza19zYmVfaW50cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQUw=::QUxfMA==::bWVtX2lmX2Fs"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQkFOS0FERFJfV0lEVEg=::QUREUl9XSURUSF8z::bWVtX2lmX2JhbmthZGRyX3dpZHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQlVSU1RMRU5HVEg=::TUVNX0lGX0JVUlNUTEVOR1RIXzg=::bWVtX2lmX2J1cnN0bGVuZ3Ro"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ09MQUREUl9XSURUSA==::QUREUl9XSURUSF8xMg==::bWVtX2lmX2NvbGFkZHJfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfUEVSX1JBTks=::TUVNX0lGX0NTX1BFUl9SQU5LXzE=::bWVtX2lmX2NzX3Blcl9yYW5r"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfQ1NfV0lEVEg=::TUVNX0lGX0NTX1dJRFRIXzE=::bWVtX2lmX2NzX3dpZHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFfUEVSX0NISVA=::TUVNX0lGX0RRX1BFUl9DSElQXzg=::bWVtX2lmX2RxX3Blcl9jaGlw"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFFTX1dJRFRI::RFFTX1dJRFRIXzQ=::bWVtX2lmX2Rxc193aWR0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfRFdJRFRI::TUVNX0lGX0RXSURUSF8zMg==::bWVtX2lmX2R3aWR0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfTUVNVFlQRQ==::RERSM19TRFJBTQ==::bWVtX2lmX21lbXR5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfUk9XQUREUl9XSURUSA==::QUREUl9XSURUSF8xNg==::bWVtX2lmX3Jvd2FkZHJfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfU1BFRURCSU4=::RERSM18xMDY2XzZfNl82::bWVtX2lmX3NwZWVkYmlu"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENDRA==::VENDRF80::bWVtX2lmX3RjY2Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENM::VENMXzY=::bWVtX2lmX3RjbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVENXTA==::VENXTF81::bWVtX2lmX3Rjd2w="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVEZBVw==::VEZBV18xNg==::bWVtX2lmX3RmYXc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJBUw==::VFJBU18xNg==::bWVtX2lmX3RyYXM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJD::VFJDXzIy::bWVtX2lmX3RyYw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJDRA==::VFJDRF82::bWVtX2lmX3RyY2Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJQ::VFJQXzY=::bWVtX2lmX3RycA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJSRA==::VFJSRF80::bWVtX2lmX3RycmQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFJUUA==::VFJUUF80::bWVtX2lmX3RydHA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdS::VFdSXzY=::bWVtX2lmX3R3cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NRU1fSUZfVFdUUg==::VFdUUl80::bWVtX2lmX3R3dHI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9NTVJfQ0ZHX01FTV9CTA==::TVBfQkxfOA==::bW1yX2NmZ19tZW1fYmw="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9PVVRQVVRfUkVHRA==::RElTQUJMRUQ=::b3V0cHV0X3JlZ2Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QRE5fRVhJVF9DWUNMRVM=::U0xPV19FWElU::cGRuX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8w::RkFMU0U=::cmRfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8x::RkFMU0U=::cmRfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8y::RkFMU0U=::cmRfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9GSUZPX0lOX1VTRV8z::RkFMU0U=::cmRfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRUFEX09EVF9DSElQ::T0RUX0RJU0FCTEVE::cmVhZF9vZHRfY2hpcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRU9SREVSX0RBVEE=::REFUQV9SRU9SREVSSU5H::cmVvcmRlcl9kYXRh"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMA==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMQ==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMg==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TSU5HTEVfUkVBRFlfMw==::Q09OQ0FURU5BVEVfUkRZ::c2luZ2xlX3JlYWR5XzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMg==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfMw==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNA==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9TWU5DX01PREVfNQ==::QVNZTkNIUk9OT1VT::c3luY19tb2RlXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9URVNUX01PREU=::Tk9STUFMX01PREU=::dGVzdF9tb2Rl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMg==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfMw==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNA==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjFfNQ==::VEhSRVNIT0xEXzMy::dGhsZF9qYXIxXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMg==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfMw==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNA==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9USExEX0pBUjJfNQ==::VEhSRVNIT0xEXzE2::dGhsZF9qYXIyXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzA=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzE=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzI=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VfQUxNT1NUX0VNUFRZXzM=::RU1QVFk=::dXNlX2FsbW9zdF9lbXB0eV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX0VDQ19FTg==::RElTQUJMRQ==::dXNlcl9lY2NfZW4="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzBfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8wX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzFfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8xX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzJfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8yX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XRklGTzNfUkRZX0FMTU9TVF9GVUxM::Tk9UX0ZVTEw=::d2ZpZm8zX3JkeV9hbG1vc3RfZnVsbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8w::RkFMU0U=::d3JfZmlmb19pbl91c2VfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8x::RkFMU0U=::d3JfZmlmb19pbl91c2VfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8y::RkFMU0U=::d3JfZmlmb19pbl91c2VfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9GSUZPX0lOX1VTRV8z::RkFMU0U=::d3JfZmlmb19pbl91c2VfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9XUklURV9PRFRfQ0hJUA==::T0RUX0RJU0FCTEVE::d3JpdGVfb2R0X2NoaXA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQVVUT19QRF9DWUNMRVM=::MA==::bWVtX2F1dG9fcGRfY3ljbGVz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMg==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfMw==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNA==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19DWUNfVE9fUkxEX0pBUlNfNQ==::MQ==::Y3ljX3RvX3JsZF9qYXJzXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1Q=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19BQ1RfRElGRl9CQU5L::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fYWN0X2RpZmZfYmFuaw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19QQ0g=::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcGNo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FDVF9UT19SRFdS::MA==::ZXh0cmFfY3RsX2Nsa19hY3RfdG9fcmR3cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfcGVyaW9k"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0FSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19hcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX0ZPVVJfQUNUX1RPX0FDVA==::MA==::ZXh0cmFfY3RsX2Nsa19mb3VyX2FjdF90b19hY3Q="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9BTExfVE9fVkFMSUQ=::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfYWxsX3RvX3ZhbGlk"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BDSF9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wY2hfdG9fdmFsaWQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9QRVJJT0Q=::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fcGVyaW9k"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1BETl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19wZG5fdG9fdmFsaWQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa19yZF9hcF90b192YWxpZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19wY2g="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0JD::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9iYw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1JEX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa19yZF90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19WQUxJRA==::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fdmFsaWQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1NSRl9UT19aUV9DQUw=::MA==::ZXh0cmFfY3RsX2Nsa19zcmZfdG9fenFfY2Fs"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX0FQX1RPX1ZBTElE::MA==::ZXh0cmFfY3RsX2Nsa193cl9hcF90b192YWxpZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1BDSA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19wY2g="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JE::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0JD::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9iYw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1JEX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b19yZF9kaWZmX2NoaXA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dS::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19FWFRSQV9DVExfQ0xLX1dSX1RPX1dSX0RJRkZfQ0hJUA==::MA==::ZXh0cmFfY3RsX2Nsa193cl90b193cl9kaWZmX2NoaXA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJFRkk=::MzEyMA==::bWVtX2lmX3RyZWZp"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fSUZfVFJGQw==::MzQ=::bWVtX2lmX3RyZmM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BU0s=::MA==::YXR0cl9jb3VudGVyX29uZV9tYXNr"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfT05FX01BVENI::MA==::YXR0cl9jb3VudGVyX29uZV9tYXRjaA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVNL::MA==::YXR0cl9jb3VudGVyX3plcm9fbWFzaw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0NPVU5URVJfWkVST19NQVRDSA==::MA==::YXR0cl9jb3VudGVyX3plcm9fbWF0Y2g="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkVDVF9BVFRSX0RFQlVHX1NFTEVDVF9CWVRF::MA==::YXR0cl9kZWJ1Z19zZWxlY3RfYnl0ZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19QT1dFUl9TQVZJTkdfRVhJVF9DWUNMRVM=::NQ==::cG93ZXJfc2F2aW5nX2V4aXRfY3ljbGVz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5UR19NRU1fQ0xLX0VOVFJZX0NZQ0xFUw==::MTA=::bWVtX2Nsa19lbnRyeV9jeWNsZXM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfSU5URVJSVVBU::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X2ludGVycnVwdA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5VTV9FTkFCTEVfQlVSU1RfVEVSTUlOQVRF::RElTQUJMRUQ=::ZW5hYmxlX2J1cnN0X3Rlcm1pbmF0ZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8wX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MA==::YXZfcG9ydF8wX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8wX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MA==::Y3ZfcG9ydF8wX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQwX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDBfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQwX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18w::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDBfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzA=::V0VJR0hUXzA=::cHJpb3JpdHlfM18w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzA=::V0VJR0hUXzA=::cHJpb3JpdHlfN18w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMA==::VVNFX05P::cmRfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzA=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzA=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8w"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzA=::MA==::VEdfVEVNUF9QT1JUXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8xX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::MQ==::YXZfcG9ydF8xX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8xX0NPTk5FQ1RfVE9fQVZfUE9SVA==::MQ==::Y3ZfcG9ydF8xX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQxX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDFfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQxX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18x::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDFfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzE=::V0VJR0hUXzA=::cHJpb3JpdHlfM18x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzE=::V0VJR0hUXzA=::cHJpb3JpdHlfN18x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzE=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzE=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8x"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzE=::MA==::VEdfVEVNUF9QT1JUXzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8yX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mg==::YXZfcG9ydF8yX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8yX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mg==::Y3ZfcG9ydF8yX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMg==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMg==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMg==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQyX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDJfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQyX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18y::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUMl9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDJfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzI=::V0VJR0hUXzA=::cHJpb3JpdHlfM18y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzI=::V0VJR0hUXzA=::cHJpb3JpdHlfN18y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMg==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMg==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMg==::RFdJRFRIXzA=::cmRfZHdpZHRoXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMg==::VVNFX05P::cmRfcG9ydF9pbmZvXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzI=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzI=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMg==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMg==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzI=::MA==::VEdfVEVNUF9QT1JUXzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF8zX0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::Mw==::YXZfcG9ydF8zX2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF8zX0NPTk5FQ1RfVE9fQVZfUE9SVA==::Mw==::Y3ZfcG9ydF8zX2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfMw==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfMw==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfMw==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQzX3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDNfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQzX3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR18z::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUM19XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDNfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfMl8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzM=::V0VJR0hUXzA=::cHJpb3JpdHlfM18z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfNl8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzM=::V0VJR0hUXzA=::cHJpb3JpdHlfN18z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfMw==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfMw==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfMw==::RFdJRFRIXzA=::cmRfZHdpZHRoXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fMw==::VVNFX05P::cmRfcG9ydF9pbmZvXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzM=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzM=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV8z"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfMw==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fMw==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzM=::MA==::VEdfVEVNUF9QT1JUXzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF80X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NA==::YXZfcG9ydF80X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF80X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NA==::Y3ZfcG9ydF80X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNA==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNA==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNA==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ0X3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDRfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ0X3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR180::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNF9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDRfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfMl80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfM180"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfNl80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzQ=::V0VJR0hUXzA=::cHJpb3JpdHlfN180"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNA==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNA==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNA==::RFdJRFRIXzA=::cmRfZHdpZHRoXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNA==::VVNFX05P::cmRfcG9ydF9pbmZvXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzQ=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzQ=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV80"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNA==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNA==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzQ=::MA==::VEdfVEVNUF9QT1JUXzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZfUE9SVF81X0NPTk5FQ1RfVE9fQ1ZfUE9SVA==::NQ==::YXZfcG9ydF81X2Nvbm5lY3RfdG9fY3ZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfUE9SVF81X0NPTk5FQ1RfVE9fQVZfUE9SVA==::NQ==::Y3ZfcG9ydF81X2Nvbm5lY3RfdG9fYXZfcG9ydA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0RBVEFfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81::MA==::Q1ZfQVZMX0FERFJfV0lEVEhfUE9SVF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU=::MA==::Q1ZfQ1BPUlRfVFlQRV9QT1JUXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ==::Mg==::Q1ZfQVZMX05VTV9TWU1CT0xTX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1dGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1dGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTFNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTFNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfTVNCX1JGSUZPX1BPUlRfNQ==::NQ==::Q1ZfTVNCX1JGSUZPX1BPUlRfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9BVVRPX1BDSF9FTkFCTEVfNQ==::RElTQUJMRUQ=::YXV0b19wY2hfZW5hYmxlXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DTURfUE9SVF9JTl9VU0VfNQ==::RkFMU0U=::Y21kX3BvcnRfaW5fdXNlXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfUkZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3JmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfVFlQRQ==::RElTQUJMRQ==::Y3BvcnQ1X3R5cGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9DUE9SVDVfV0ZJRk9fTUFQ::RklGT18w::Y3BvcnQ1X3dmaWZvX21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9FTkFCTEVfQk9ORElOR181::RElTQUJMRUQ=::ZW5hYmxlX2JvbmRpbmdfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QT1JUNV9XSURUSA==::UE9SVF82NF9CSVQ=::cG9ydDVfd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8wXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8xXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8yXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfMl81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV8zXzU=::V0VJR0hUXzA=::cHJpb3JpdHlfM181"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV80XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV81XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV82XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfNl81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9QUklPUklUWV83XzU=::V0VJR0hUXzA=::cHJpb3JpdHlfN181"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1NUQVRJQ19XRUlHSFRfNQ==::V0VJR0hUXzA=::cmNmZ19zdGF0aWNfd2VpZ2h0XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SQ0ZHX1VTRVJfUFJJT1JJVFlfNQ==::UFJJT1JJVFlfMA==::cmNmZ191c2VyX3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9EV0lEVEhfNQ==::RFdJRFRIXzA=::cmRfZHdpZHRoXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRF9QT1JUX0lORk9fNQ==::VVNFX05P::cmRfcG9ydF9pbmZvXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9TVEFUSUNfV0VJR0hUXzU=::V0VJR0hUXzA=::c3RhdGljX3dlaWdodF81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9VU0VSX1BSSU9SSVRZXzU=::UFJJT1JJVFlfMA==::dXNlcl9wcmlvcml0eV81"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9EV0lEVEhfNQ==::RFdJRFRIXzA=::d3JfZHdpZHRoXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XUl9QT1JUX0lORk9fNQ==::VVNFX05P::d3JfcG9ydF9pbmZvXzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEdfVEVNUF9QT1JUXzU=::MA==::VEdfVEVNUF9QT1JUXzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzBfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8wX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzFfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8xX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzJfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8yX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9SRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::cmZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfRU5VTV9XRklGTzNfQ1BPUlRfTUFQ::Q01EX1BPUlRfMA==::d2ZpZm8zX2Nwb3J0X21hcA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8w::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMA==::MA==::c3VtX3d0X3ByaW9yaXR5XzA="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8x::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzE="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8y::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMg==::MA==::c3VtX3d0X3ByaW9yaXR5XzI="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV8z::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfMw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfMw==::MA==::c3VtX3d0X3ByaW9yaXR5XzM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV80::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNA==::MA==::c3VtX3d0X3ByaW9yaXR5XzQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV81::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNQ==::MA==::c3VtX3d0X3ByaW9yaXR5XzU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV82::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNg==::MA==::c3VtX3d0X3ByaW9yaXR5XzY="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19SQ0ZHX1NVTV9XVF9QUklPUklUWV83::MA==::cmNmZ19zdW1fd3RfcHJpb3JpdHlfNw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1ZfSU5UR19TVU1fV1RfUFJJT1JJVFlfNw==::MA==::c3VtX3d0X3ByaW9yaXR5Xzc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw=::ZmFsc2U=::Q09OVElOVUVfQUZURVJfQ0FMX0ZBSUw="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfQ0ZH::dHJ1ZQ==::TUFYMTBfQ0ZH"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9XRVJfT0ZfVFdPX0JVUw==::ZmFsc2U=::R2VuZXJhdGUgcG93ZXItb2YtMiBkYXRhIGJ1cyB3aWR0aHMgZm9yIFFzeXMgb3IgU09QQyBCdWlsZGVy"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "U09QQ19DT01QQVRfUkVTRVQ=::ZmFsc2U=::R2VuZXJhdGUgU09QQyBCdWlsZGVyIGNvbXBhdGlibGUgcmVzZXRz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX01BWF9TSVpF::NA==::TWF4aW11bSBBdmFsb24tTU0gYnVyc3QgbGVuZ3Ro"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QllURV9FTkFCTEU=::dHJ1ZQ==::RW5hYmxlIEF2YWxvbi1NTSBieXRlLWVuYWJsZSBzaWduYWw="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NUUkxfQVZBTE9OX0lOVEVSRkFDRQ==::dHJ1ZQ==::RW5hYmxlIEF2YWxvbiBpbnRlcmZhY2U="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RFRVBfUE9XRVJETl9FTg==::ZmFsc2U=::RW5hYmxlIERlZXAgUG93ZXItRG93biBDb250cm9scw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1NFTEZfUkVGUkVTSF9FTg==::ZmFsc2U=::RW5hYmxlIFNlbGYtUmVmcmVzaCBDb250cm9scw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19QT1dFUkROX0VO::ZmFsc2U=::RW5hYmxlIEF1dG8gUG93ZXItRG93bg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1VTUl9SRUZSRVNIX0VO::ZmFsc2U=::RW5hYmxlIFVzZXIgQXV0by1SZWZyZXNoIENvbnRyb2xz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0FVVE9QQ0hfRU4=::ZmFsc2U=::RW5hYmxlIEF1dG8tUHJlY2hhcmdlIENvbnRyb2w="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1pRQ0FMX0VO::ZmFsc2U=::RW5hYmxlIFpRIENhbGlicmF0aW9uIENvbnRyb2w="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9PUkRFUg==::MA==::TG9jYWwtdG8tTWVtb3J5IEFkZHJlc3MgTWFwcGluZw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0xPT0tfQUhFQURfREVQVEg=::NA==::Q29tbWFuZCBRdWV1ZSBMb29rLUFoZWFkIERlcHRo"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09OVFJPTExFUl9MQVRFTkNZ::NQ==::UmVkdWNlIENvbnRyb2xsZXIgTGF0ZW5jeSBCeQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1JFT1JERVJfREFUQQ==::dHJ1ZQ==::RW5hYmxlIFJlb3JkZXJpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1RBUlZFX0xJTUlU::MTA=::U3RhcnZhdGlvbiBsaW1pdCBmb3IgZWFjaCBjb21tYW5k"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VDQ19FTkFCTEVE::ZmFsc2U=::RW5hYmxlIEVycm9yIERldGVjdGlvbiBhbmQgQ29ycmVjdGlvbiBMb2dpYw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0hSQl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIGhhbGYgcmF0ZSBicmlkZ2U="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVVMVElDQVNUX0VO::ZmFsc2U=::RW5hYmxlIE11bHRpLWNhc3QgV3JpdGUgQ29udHJvbA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0RZTkFNSUNfQkFOS19BTExPQ0FUSU9O::ZmFsc2U=::RW5hYmxlIHJlZHVjZWQgYmFuayB0cmFja2luZyBmb3IgYXJlYSBvcHRpbWl6YXRpb24="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVCVUdfTU9ERQ==::ZmFsc2U=::RW5hYmxlIGludGVybmFsIGRlYnVnIHBhcmFtZXRlcg=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JVUlNUX01FUkdF::ZmFsc2U=::RW5hYmxlIGJ1cnN0IG1lcmdpbmc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9JTlRFUlJVUFQ=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IGludGVycnVwdA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0VOQUJMRV9CVVJTVF9URVJNSU5BVEU=::ZmFsc2U=::RW5hYmxlIGJ1cnN0IHRlcm1pbmF0ZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TE9DQUxfSURfV0lEVEg=::OA==::TG9jYWwgSUQgd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRCVUZGRVJfQUREUl9XSURUSA==::Nw==::UmVhZCBidWZmZXIgYWRkcmVzcyB3aWR0aA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V1JCVUZGRVJfQUREUl9XSURUSA==::Ng==::V3JpdGUgYnVmZmVyIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfV1JfQ01E::MTY=::TWF4IHBlbmRpbmcgd3JpdGUgY29tbWFuZHM="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1BFTkRJTkdfUkRfQ01E::MzI=::TWF4IHBlbmRpbmcgcmVhZCBjb21tYW5kcw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01NX0FEQVBUT1I=::dHJ1ZQ==::VXNlIEF2YWxvbiBNTSBBZGFwdG9y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FYSV9BREFQVE9S::ZmFsc2U=::VXNlIEFYSSBBZGFwdG9y"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RF::ZmFsc2U=::SGFyZENvcHkgQ29tcGF0aWJpbGl0eSBNb2Rl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NNRF9RVUVVRV9ERVBUSA==::OA==::Q1RMX0NNRF9RVUVVRV9ERVBUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX0NTUl9SRUFEX09OTFk=::MQ==::Q1RMX0NTUl9SRUFEX09OTFk="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX0RBVEFfUkVPUkRFUklOR19UWVBF::SU5URVJfQkFOSw==::UmVvcmRlcmluZyB0eXBl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX09GX1BPUlRT::MQ==::TnVtYmVyIG9mIHBvcnRz"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JPTkRJTkc=::ZmFsc2U=::RXhwb3J0IGJvbmRpbmcgaW50ZXJmYWNl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1VTRVJfRUND::ZmFsc2U=::RXhwYW5kIEF2YWxvbi1NTSBkYXRhIGZvciBFQ0M="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEhfUE9SVA==::MzIsMzIsMzIsMzIsMzIsMzI=::V2lkdGg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJJT1JJVFlfUE9SVA==::MSwxLDEsMSwxLDE=::UHJpb3JpdHk="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0VJR0hUX1BPUlQ=::MCwwLDAsMCwwLDA=::V2VpZ2h0"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1BPUlRfVFlQRV9QT1JU::QmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWwsQmlkaXJlY3Rpb25hbCxCaWRpcmVjdGlvbmFsLEJpZGlyZWN0aW9uYWw=::VHlwZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::ZmFsc2U=::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGRyM19yYW1fczA="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBRc3lzIFNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBRc3lzIFNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::ZmFsc2U=::RkxZX0JZ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::ZmFsc2U=::R0VORVJJQ19QTEw="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::dHJ1ZQ==::UkVBRF9GSUZPX0hBTEZfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTkx::UEhZX1ZFUlNJT05fTlVNQkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::ZmFsc2U=::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::ZmFsc2U=::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::ZmFsc2U=::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::SEFMRg==::VEJfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::OA==::VEJfTUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::MTAwLjA=::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::MTAwLjAgTUh6::UkVGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MTAuMA==::UkVGX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MTAwMDAuMA==::UkVGX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::Mw==::UExMX01FTV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MQ==::UExMX01FTV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MTUwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MTUwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::Mw==::UExMX0FGSV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::Mg==::UExMX0FGSV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::Mw==::UExMX1dSSVRFX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MQ==::UExMX1dSSVRFX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::MC4w::UExMX05JT1NfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::MA==::UExMX05JT1NfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::MA==::UExMX05JT1NfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::MA==::UExMX0NPTkZJR19DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MA==::UExMX0NPTkZJR19DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MQ==::UExMX01FTV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MQ==::UExMX01FTV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::Mg==::UExMX0FGSV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::Mg==::UExMX0FGSV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::Mw==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MQ==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MA==::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MC4w::TUVNX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MC4w::UkVGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::VW5rbm93bg==::UkFURV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::VW5rbm93bg==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::VW5rbm93bg==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklYX1JFQURfTEFURU5DWQ==::OA==::Rml4ZWQgUmVhZCBMYXRlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MA==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NA==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MQ==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::ZmFsc2U=::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::Mg==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::OTAwMA==::RFFTX1BIQVNFX1NISUZU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::Mw==::SU9fRFFTX0lOX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::Mw==::SU9fRFFTX09VVF9SRVNFUlZF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MTQ=::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::NA==::Q0FMSUJfTEZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::MTI=::Q0FMSUJfVkZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::NTA=::REVMQVlfUEVSX0RDSEFJTl9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::NTA=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::Nw==::RFFTX0VOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MTU=::RFFTX0lOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MTU=::SU9fSU5fREVMQVlfTUFY"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MTU=::SU9fT1VUMV9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::Nw==::SU9fT1VUMl9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::NQ==::TUVNX1RfV0w="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::NQ==::TUVNX1RfUkw="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::ZmFsc2U=::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::dHJ1ZQ==::TUFYMTBfUlRMX1NFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX09OTFk=::ZmFsc2U=::R2VuZXJhdGUgUEhZIG9ubHk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::U2tpcA==::QXV0by1jYWxpYnJhdGlvbiBtb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zMg==::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yMg==::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xNg==::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNDU=::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC4yNDQz::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC4yMTkyOQ==::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::MC4wMjI4Ng==::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::MC4wMjI4Ng==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wNDQyOQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wNDQyOQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMTgwNg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wNDI0Ng==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::LTAuMDExNTI=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wNzgwMQ==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::LTAuMDQ3MDk=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Ng==::RExMX0RFTEFZX0NUUkxfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTQ=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREX0VYVEVSTkFMX1NFUV9ERUJVR19OSU9T::ZmFsc2U=::QWRkIGV4dGVybmFsIE5pb3MgdG8gY29ubmVjdCB0byBzZXF1ZW5jZXIgZGVidWcgaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RURfRVhQT1JUX1NFUV9ERUJVRw==::ZmFsc2U=::RXhwb3J0IHNlcXVlbmNlciBkZWJ1ZyBpbnRlcmZhY2UgZnJvbSBleGFtcGxlIGRlc2lnbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREX0VGRklDSUVOQ1lfTU9OSVRPUg==::ZmFsc2U=::RW5hYmxlIHRoZSBFZmZpY2llbmN5IE1vbml0b3IgYW5kIFByb3RvY29sIENoZWNrZXIgb24gdGhlIENvbnRyb2xsZXIgQXZhbG9uIEludGVyZmFjZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX01BWF9XUklURV9MQVRFTkNZX0NPVU5UX1dJRFRI::Ng==::QUZJX01BWF9XUklURV9MQVRFTkNZX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX01BWF9SRUFEX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::Ng==::QUZJX01BWF9SRUFEX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0RBVEFfV0lEVEg=::MzI=::QVZMX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZMX0FERFJfV0lEVEg=::MTM=::QVZMX0FERFJfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_NAME "YWZpX211eF9kZHIzX2Rkcng="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEREUjMgQUZJIE11bHRpcGxleGVy"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEREUjMgQUZJIE11bHRpcGxleGVy"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::dHJ1ZQ==::RkxZX0JZ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9FTUlG::ZmFsc2U=::RW5hYmxlIEhhcmQgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZQ=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGRyM19yYW1fcDA="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::ZmFsc2U=::RkxZX0JZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::ZmFsc2U=::R0VORVJJQ19QTEw="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::dHJ1ZQ==::UkVBRF9GSUZPX0hBTEZfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTkx::UEhZX1ZFUlNJT05fTlVNQkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::ZmFsc2U=::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::ZmFsc2U=::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::ZmFsc2U=::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::SEFMRg==::VEJfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::OA==::VEJfTUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::MTAwLjA=::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::MTAwLjAgTUh6::UkVGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MTAuMA==::UkVGX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MTAwMDAuMA==::UkVGX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::Mw==::UExMX01FTV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MQ==::UExMX01FTV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MTUwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MTUwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::Mw==::UExMX0FGSV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::Mg==::UExMX0FGSV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::Mw==::UExMX1dSSVRFX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MQ==::UExMX1dSSVRFX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::MC4w::UExMX05JT1NfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::MA==::UExMX05JT1NfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::MA==::UExMX05JT1NfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::MA==::UExMX0NPTkZJR19DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MA==::UExMX0NPTkZJR19DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MQ==::UExMX01FTV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MQ==::UExMX01FTV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::Mg==::UExMX0FGSV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::Mg==::UExMX0FGSV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::Mw==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MQ==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MA==::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MC4w::TUVNX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MC4w::UkVGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::VW5rbm93bg==::UkFURV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::VW5rbm93bg==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::VW5rbm93bg==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklYX1JFQURfTEFURU5DWQ==::OA==::Rml4ZWQgUmVhZCBMYXRlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MA==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NA==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MQ==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::ZmFsc2U=::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::Mg==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::OTAwMA==::RFFTX1BIQVNFX1NISUZU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::Mw==::SU9fRFFTX0lOX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::Mw==::SU9fRFFTX09VVF9SRVNFUlZF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MTQ=::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::NA==::Q0FMSUJfTEZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::MTI=::Q0FMSUJfVkZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::NTA=::REVMQVlfUEVSX0RDSEFJTl9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::NTA=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::Nw==::RFFTX0VOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MTU=::RFFTX0lOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MTU=::SU9fSU5fREVMQVlfTUFY"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MTU=::SU9fT1VUMV9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::Nw==::SU9fT1VUMl9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::NQ==::TUVNX1RfV0w="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::NQ==::TUVNX1RfUkw="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::ZmFsc2U=::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::dHJ1ZQ==::TUFYMTBfUlRMX1NFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX09OTFk=::ZmFsc2U=::R2VuZXJhdGUgUEhZIG9ubHk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::U2tpcA==::QXV0by1jYWxpYnJhdGlvbiBtb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zMg==::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yMg==::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xNg==::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNDU=::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC4yNDQz::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC4yMTkyOQ==::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::MC4wMjI4Ng==::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::MC4wMjI4Ng==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wNDQyOQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wNDQyOQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMTgwNg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wNDI0Ng==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::LTAuMDExNTI=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wNzgwMQ==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::LTAuMDQ3MDk=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Ng==::RExMX0RFTEFZX0NUUkxfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1RFUk1fQ09OVFJPTF9XSURUSA==::MTQ=::T0NUX1RFUk1fQ09OVFJPTF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_COMPONENT_PARAMETER "T0NUX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::T0NUIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfZGRyM19yYW1fcGxsMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUExML0RMTC9PQ1QgYmxvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "RERSMyBTRFJBTSBFeHRlcm5hbCBNZW1vcnkgUExML0RMTC9PQ1QgYmxvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMA==::MDAwMTAwMDAxMDAwMQ==::QUNfUk9NX01SMA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9NSVJS::MDAwMTAwMDAwMTAwMQ==::QUNfUk9NX01SMF9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVQ=::MDAwMTEwMDAxMDAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg==::MDAwMTAxMDAwMTAwMA==::QUNfUk9NX01SMF9ETExfUkVTRVRfTUlSUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMQ==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMV9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMV9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMg==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMl9NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMl9NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SMw==::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SMw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX01SM19NSVJS::MDAwMDAwMDAwMDAwMA==::QUNfUk9NX01SM19NSVJS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ::ZmFsc2U=::VVNFX05FR19FREdFX0FDX1RSQU5TRkVSX0ZPUl9IUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JM::MQ==::TVIwX0JM"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0JU::MA==::TVIwX0JU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0NBU19MQVRFTkNZ::MQ==::TVIwX0NBU19MQVRFTkNZ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX0RMTA==::MQ==::TVIwX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1dS::MQ==::TVIwX1dS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIwX1BE::MA==::TVIwX1BE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RMTA==::MA==::TVIxX0RMTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX09EUw==::MA==::TVIxX09EUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JUVA==::MA==::TVIxX1JUVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0FM::MA==::TVIxX0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1dM::MA==::TVIxX1dM"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1REUVM=::MA==::TVIxX1REUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1FPRkY=::MA==::TVIxX1FPRkY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX0RRUw==::MA==::TVIxX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIxX1JEUVM=::MA==::TVIxX1JEUVM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0NXTA==::MA==::TVIyX0NXTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX0FTUg==::MA==::TVIyX0FTUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSVA==::MA==::TVIyX1NSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1NSRg==::MA==::TVIyX1NSRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIyX1JUVF9XUg==::MA==::TVIyX1JUVF9XUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9SRg==::MA==::TVIzX01QUl9SRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUg==::MA==::TVIzX01QUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVIzX01QUl9BQQ==::MA==::TVIzX01QUl9BQQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::TUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSSVRFX0RRU19XSURUSA==::MQ==::TUVNX0lGX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0NDX0RBVEFfV0lEVEg=::MQ==::U0NDX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEg=::MTQ=::TUVNX0lGX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0FERFJfV0lEVEhfTUlO::MTM=::TUVNX0lGX0FERFJfV0lEVEhfTUlO"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JPV19BRERSX1dJRFRI::MTQ=::TUVNX0lGX1JPV19BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTF9BRERSX1dJRFRI::MTA=::TUVNX0lGX0NPTF9BRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1dJRFRI::MQ==::TUVNX0lGX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9SQU5L::MQ==::TUVNX0lGX0NTX1BFUl9SQU5L"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX05VTUJFUl9PRl9SQU5LUw==::MQ==::TUVNX0lGX05VTUJFUl9PRl9SQU5LUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1BFUl9ESU1N::MQ==::TUVNX0lGX0NTX1BFUl9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NPTlRST0xfV0lEVEg=::MQ==::TUVNX0lGX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JVUlNUX0xFTkdUSA==::OA==::TUVNX0JVUlNUX0xFTkdUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xFVkVMSU5H::dHJ1ZQ==::TUVNX0xFVkVMSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU19XSURUSA==::MQ==::TnVtYmVyIG9mIERRUyBncm91cHM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NTX1dJRFRI::MQ==::TUVNX0lGX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NISVBfQklUUw==::MQ==::TUVNX0lGX0NISVBfQklUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JBTktBRERSX1dJRFRI::Mw==::TUVNX0lGX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRX1dJRFRI::OA==::TUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NLX1dJRFRI::MQ==::TUVNX0lGX0NLX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19FTl9XSURUSA==::MQ==::TUVNX0lGX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0NMS19QQUlSX0NPVU5U::MQ==::TUVNX0lGX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX1dJRFRI::MQ==::REVWSUNFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfTlM=::MS4yNQ==::TUVNX0NMS19NQVhfTlM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19NQVhfUFM=::MTI1MC4w::TUVNX0NMS19NQVhfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQw==::MTU=::TUVNX1RSQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVM=::MTE=::TUVNX1RSQVM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0Q=::NQ==::TUVNX1RSQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUA==::NQ==::TUVNX1RSUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJ::MjM0MQ==::TUVNX1RSRUZJ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkM=::MzQ=::TUVNX1RSRkM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0Q=::MQ==::Q0ZHX1RDQ0Q="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUg==::NQ==::TUVNX1RXUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVc=::MTA=::TUVNX1RGQVc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkQ=::Mg==::TUVNX1RSUkQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFA=::Mw==::TUVNX1RSVFA="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ==::MTAw::TUVNX0RRU19UT19DTEtfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ==::MTAwMDAw::TUVNX0NMS19UT19EUVNfQ0FQVFVSRV9ERUxBWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX09EVF9XSURUSA==::MQ==::TUVNX0lGX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0xfSU5U::NQ==::TUVNX1dUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkxZX0JZ::ZmFsc2U=::RkxZX0JZ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU0=::ZmFsc2U=::UkRJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1N::ZmFsc2U=::TFJESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fSU5U::MA==::UkRJTU1fSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0lOVA==::MA==::TFJESU1NX0lOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0xSRElNTV9STQ==::MA==::TUVNX0lGX0xSRElNTV9STQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU::Mg==::TUVNX0lGX1JEX1RPX1dSX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU::Mw==::TUVNX0lGX1dSX1RPX1JEX1RVUk5BUk9VTkRfT0NU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs=::MA==::Q1RMX1JEX1RPX1BDSF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw==::MA==::Q1RMX1JEX1RPX1JEX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw==::MA==::Q1RMX1dSX1RPX1dSX0VYVFJBX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1JEX1RPX1JEX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs=::MQ==::Q1RMX1dSX1RPX1dSX0RJRkZfQ0hJUF9FWFRSQV9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RZUEU=::RERSMw==::TUVNX1RZUEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw==::MA==::TUVNX01JUlJPUl9BRERSRVNTSU5HX0RFQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0xfSU5U::MA==::TUVNX0FUQ0xfSU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JFR0RJTU1fRU5BQkxFRA==::ZmFsc2U=::TUVNX1JFR0RJTU1fRU5BQkxFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0xSRElNTV9FTkFCTEVE::ZmFsc2U=::TUVNX0xSRElNTV9FTkFCTEVE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFTkRPUg==::SkVERUM=::TWVtb3J5IHZlbmRvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkRJTU1fQ09ORklH::MDAwMDAwMDAwMDAwMDAwMA==::RERSMyBSRElNTS9MUkRJTU0gQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TFJESU1NX0VYVEVOREVEX0NPTkZJRw==::MHgwMDAwMDAwMDAwMDAwMDAwMDA=::TFJESU1NIEFkZGl0aW9uYWwgQ29udHJvbCBXb3Jkcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQ1JFVEVfRkxZX0JZ::dHJ1ZQ==::Rmx5LWJ5IHRvcG9sb2d5"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0RFUFRI::MQ==::TnVtYmVyIG9mIGNoaXAgc2VsZWN0cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX01JUlJPUl9BRERSRVNTSU5H::MA==::TWlycm9yIEFkZHJlc3Npbmc6IDEgcGVyIGNoaXAgc2VsZWN0"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX01BWA==::ODAwLjA=::TWVtb3J5IGRldmljZSBzcGVlZCBncmFkZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JPV19BRERSX1dJRFRI::MTQ=::Um93IGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NPTF9BRERSX1dJRFRI::MTA=::Q29sdW1uIGFkZHJlc3Mgd2lkdGg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1dJRFRI::OA==::VG90YWwgaW50ZXJmYWNlIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RRX1BFUl9EUVM=::OA==::RFEvRFFTIGdyb3VwIHNpemU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JBTktBRERSX1dJRFRI::Mw==::QmFuay1hZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RNX1BJTlNfRU4=::dHJ1ZQ==::RW5hYmxlIERNIHBpbnM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0RRU05fRU4=::dHJ1ZQ==::RFFTIyBFbmFibGU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9ESU1NUw==::MQ==::TnVtYmVyIG9mIHNsb3Rz"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfRElNTQ==::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBzbG90"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX05VTUJFUl9PRl9SQU5LU19QRVJfREVWSUNF::MQ==::TnVtYmVyIG9mIHJhbmtzIHBlciBkZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JBTktfTVVMVElQTElDQVRJT05fRkFDVE9S::MQ==::KERlcHJlY2F0ZWQpIExSRElNTSBSYW5rIE11bHRpcGxpY2F0aW9uIEZhY3Rvcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1dJRFRI::MQ==::TnVtYmVyIG9mIGNsb2Nrcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NTX1dJRFRI::MQ==::TnVtYmVyIG9mIGNoaXAtc2VsZWN0cyBwZXIgZGV2aWNlL0RJTU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19FTl9XSURUSA==::MQ==::TnVtYmVyIG9mIGNsb2NrIGVuYWJsZXMgcGVyIGRldmljZS9ESU1N"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUxUTUVNUEhZX0NPTVBBVElCTEVfTU9ERQ==::ZmFsc2U=::QWxsb3cgdGhlIG1lbW9yeSBtb2RlbCB0byBiZSB1c2UgaW4gQUxUTUVNUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVYVEdFTg==::dHJ1ZQ==::RW5hYmxlIDExLjAgZXh0cmEgY29udHJvbGxlciBmZWF0dXJlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX0JPQVJEX0JBU0VfREVMQVk=::MTA=::QmFzZSBib2FyZCBkZWxheSBmb3IgYm9hcmQgZGVsYXkgbW9kZWw="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c=::MA==::TUVNX0lGX1NJTV9WQUxJRF9XSU5ET1c="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA==::ZmFsc2U=::TUVNX0dVQVJBTlRFRURfV1JJVEVfSU5JVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZFUkJPU0U=::dHJ1ZQ==::RW5hYmxlIHZlcmJvc2UgbWVtb3J5IG1vZGVsIG91dHB1dA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UElOR1BPTkdQSFlfRU4=::ZmFsc2U=::RW5hYmxlIFBpbmcgUG9uZyBQSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX0FD::ZmFsc2U=::RHVwbGljYXRlIEFkZHJlc3MgYW5kIENvbW1hbmQgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9CVVJTVF9WQUxJREFUSU9O::ZmFsc2U=::RW5hYmxlIG1lbW9yeSBtb2RlbCByZWZyZXNoIGJ1cnN0IHZhbGlkYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERV9FTg==::MA==::QVBfTU9ERV9FTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVBfTU9ERQ==::ZmFsc2U=::QVBfTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JM::T1RG::QnVyc3QgTGVuZ3Ro"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0JU::U2VxdWVudGlhbA==::UmVhZCBCdXJzdCBUeXBl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FTUg==::TWFudWFs::QXV0byBzZWxmcmVmcmVzaCBtZXRob2Q="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1NSVA==::Tm9ybWFs::U2VsZnJlZnJlc2ggdGVtcGVyYXR1cmU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1BE::RExMIG9mZg==::RExMIHByZWNoYXJnZSBwb3dlciBkb3du"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RSVl9TVFI=::UlpRLzY=::T3V0cHV0IGRyaXZlIHN0cmVuZ3RoIHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RMTF9FTg==::dHJ1ZQ==::RW5hYmxlIHRoZSBETEwgaW4gbWVtb3J5IGRldmljZXM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9OT00=::T0RUIERpc2FibGVk::T0RUIFJ0dCBub21pbmFsIHZhbHVl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1JUVF9XUg==::RHluYW1pYyBPRFQgb2Zm::RHluYW1pYyBPRFQgKFJ0dF9XUikgdmFsdWU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1dUQ0w=::NQ==::TWVtb3J5IHdyaXRlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FUQ0w=::RGlzYWJsZWQ=::TWVtb3J5IGFkZGl0aXZlIENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RDTA==::NQ==::TWVtb3J5IENBUyBsYXRlbmN5IHNldHRpbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0FVVE9fTEVWRUxJTkdfTU9ERQ==::dHJ1ZQ==::QXV0b2xldmVsaW5nIHNlbGVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1VTRVJfTEVWRUxJTkdfTU9ERQ==::TGV2ZWxpbmc=::TGV2ZWxpbmcgaW50ZXJmYWNlIG1vZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0lOSVRfRU4=::ZmFsc2U=::RW5hYmxlcyBtZW1vcnkgY29udGVudCBpbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJUw==::MTcw::dElTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RJSA==::MTIw::dElIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUw==::MTA=::dERTIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RESA==::NDU=::dERIIChiYXNlKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNR::MTAw::dERRU1E="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRSA==::MC4zOA==::dFFI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDSw==::MjI1::dERRU0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RT::NDUw::dERRU0NLIERlbHRhIFNob3J0"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RN::OTAw::dERRU0NLIERlbHRhIE1lZGl1bQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNDS0RM::MTIwMA==::dERRU0NLIERlbHRhIExvbmc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REUVNT::MC4yNw==::dERRU1M="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1RRU0g=::MC40::dFFTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU0g=::MC4xOA==::dERTSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX1REU1M=::MC4xOA==::dERTUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX1VT::NTAw::dElOSVQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RJTklUX0NL::MTUwMDAw::TUVNX1RJTklUX0NL"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1REUVNDSw==::MQ==::TUVNX1REUVNDSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RNUkRfQ0s=::NA==::dE1SRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQVNfTlM=::MzUuMA==::dFJBUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSQ0RfTlM=::MTMuNzU=::dFJDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUF9OUw==::MTMuNzU=::dFJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRUZJX1VT::Ny44::dFJFRkk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSRkNfTlM=::MTEwLjA=::dFJGQw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0ZHX1RDQ0RfTlM=::Mi41::dENDRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXUl9OUw==::MTUuMA==::dFdS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RXVFI=::Ng==::dFdUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RGQVdfTlM=::MzAuMA==::dEZBVw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSUkRfTlM=::Ni4w::dFJSRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RSVFBfTlM=::Ny41::dFJUUA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw==::ZmFsc2U=::Q09SRV9QRVJJUEhFUllfRFVBTF9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RSX0NMSw==::ZmFsc2U=::VVNFX0RSX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1VTRV9EUl9DTEs=::ZmFsc2U=::RExMX1VTRV9EUl9DTEs="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFXzJYX0ZG::ZmFsc2U=::VVNFXzJYX0ZG"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVBTF9XUklURV9DTE9DSw==::ZmFsc2U=::RFVBTF9XUklURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "R0VORVJJQ19QTEw=::ZmFsc2U=::R0VORVJJQ19QTEw="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hBUkRfUkVBRF9GSUZP::ZmFsc2U=::VVNFX0hBUkRfUkVBRF9GSUZP"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX0hBTEZfUkFURQ==::dHJ1ZQ==::UkVBRF9GSUZPX0hBTEZfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01BU1RFUg==::dHJ1ZQ==::UExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX01BU1RFUg==::dHJ1ZQ==::RExMX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX1ZFUlNJT05fTlVNQkVS::MTkx::UEhZX1ZFUlNJT05fTlVNQkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfT0NJ::ZmFsc2U=::RU5BQkxFX05JT1NfT0NJ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfSlRBR19NQVNURVI=::ZmFsc2U=::RU5BQkxFX0VNSVRfSlRBR19NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfSlRBR19VQVJU::ZmFsc2U=::RU5BQkxFX05JT1NfSlRBR19VQVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA==::ZmFsc2U=::RU5BQkxFX05JT1NfUFJJTlRGX09VVFBVVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI=::ZmFsc2U=::RU5BQkxFX0xBUkdFX1JXX01HUl9ESV9CVUZGRVI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VNSVRfQkZNX01BU1RFUg==::ZmFsc2U=::RU5BQkxFX0VNSVRfQkZNX01BU1RFUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF::ZmFsc2U=::Rk9SQ0VfU0VRVUVOQ0VSX1RDTF9ERUJVR19NT0RF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA==::ZmFsc2U=::RU5BQkxFX1NFUVVFTkNFUl9NQVJHSU5JTkdfT05fQllfREVGQVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0=::ZmFsc2U=::RU5BQkxFX01BWF9TSVpFX1NFUV9NRU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU=::ZmFsc2U=::TUFLRV9JTlRFUk5BTF9OSU9TX1ZJU0lCTEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc=::ZmFsc2U=::REVQTE9ZX1NFUVVFTkNFUl9TV19GSUxFU19GT1JfREVCVUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ==::ZmFsc2U=::RU5BQkxFX0NTUl9TT0ZUX1JFU0VUX1JFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw==::ZmFsc2U=::RFVQTElDQVRFX1BMTF9GT1JfUEhZX0NMSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NQ==::TUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9WQUxJRF9GSUZPX1NJWkU=::MTY=::UkVBRF9WQUxJRF9GSUZPX1NJWkU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhUUkFfVkZJRk9fU0hJRlQ=::MA==::RVhUUkFfVkZJRk9fU0hJRlQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0NMS19GUkVR::MzAwLjA=::VEJfTUVNX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUkFURQ==::SEFMRg==::VEJfUkFURQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX0RRX1dJRFRI::OA==::VEJfTUVNX0lGX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI::MQ==::VEJfTUVNX0lGX1JFQURfRFFTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VEJfUExMX0RMTF9NQVNURVI=::dHJ1ZQ==::VEJfUExMX0RMTF9NQVNURVI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RkFTVF9TSU1fQ0FMSUJSQVRJT04=::ZmFsc2U=::RkFTVF9TSU1fQ0FMSUJSQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVR::MTAwLjA=::UExMIHJlZmVyZW5jZSBjbG9jayBmcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1NUUg==::MTAwLjAgTUh6::UkVGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19OUw==::MTAuMA==::UkVGX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QUw==::MTAwMDAuMA==::UkVGX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVR::MC4w::UExMX0RSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0RSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QUw==::MA==::UExMX0RSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0RSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0RSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxU::MA==::UExMX0RSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVY=::MA==::UExMX0RSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUQ==::MzAwLjA=::QWNoaWV2ZWQgbWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TVFI=::MzAwLjAgTUh6::UExMX01FTV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFM=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVH::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX01FTV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVA==::Mw==::UExMX01FTV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElW::MQ==::UExMX01FTV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUQ==::MTUwLjA=::QWNoaWV2ZWQgbG9jYWwgY2xvY2sgZnJlcXVlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TVFI=::MTUwLjAgTUh6::UExMX0FGSV9DTEtfRlJFUV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFM=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVH::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0FGSV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVA==::Mw==::UExMX0FGSV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElW::Mg==::UExMX0FGSV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVR::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX1dSSVRFX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX1dSSVRFX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxU::Mw==::UExMX1dSSVRFX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVY=::MQ==::UExMX1dSSVRFX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVR::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FERFJfQ01EX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI=::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0FERFJfQ01EX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxU::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVY=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVR::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg==::MzAwLjAgTUh6::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI=::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc=::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0=::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN::MjcwLjA=::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxU::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVY=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVE=::MC4w::UExMX05JT1NfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX05JT1NfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BT::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX05JT1NfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFQ=::MA==::UExMX05JT1NfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVg==::MA==::UExMX05JT1NfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0NPTkZJR19DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFM=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVH::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0NPTkZJR19DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVA==::MA==::UExMX0NPTkZJR19DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElW::MA==::UExMX0NPTkZJR19DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVR::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX1AyQ19SRUFEX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc=::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxU::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVY=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS::MCBwcw==::UExMX0MyUF9XUklURV9DTEtfRlJFUV9TSU1fU1RS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVH"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfREVHX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVA==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElW::MA==::UExMX0MyUF9XUklURV9DTEtfRElW"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVR::MC4w::UExMX0hSX0NMS19GUkVR"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1NJTV9TVFI=::MCBwcw==::UExMX0hSX0NMS19GUkVRX1NJTV9TVFI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QUw==::MA==::UExMX0hSX0NMS19QSEFTRV9QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUc=::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19TSU0=::MA==::UExMX0hSX0NMS19QSEFTRV9QU19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN::MC4w::UExMX0hSX0NMS19QSEFTRV9ERUdfU0lN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxU::MA==::UExMX0hSX0NMS19NVUxU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVY=::MA==::UExMX0hSX0NMS19ESVY="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVE=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVE="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg==::MCBwcw==::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfU0lNX1NUUg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw==::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFRw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1NJTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX0RFR19TSU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFQ=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVg==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX0NBQ0hFX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE::dHJ1ZQ==::UkVGX0NMS19GUkVRX1BBUkFNX1ZBTElE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9QQVJBTQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9QQVJBTQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01JTl9DQUNIRQ==::MTAuMA==::UkVGX0NMS19GUkVRX01JTl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX01BWF9DQUNIRQ==::NTAwLjA=::UkVGX0NMS19GUkVRX01BWF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0RSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0RSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0RSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0RSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0RSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0RSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0RSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0RSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9QQVJBTQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX1BBUkFN::MQ==::UExMX01FTV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9DQUNIRQ==::MzAwLjA=::UExMX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::MzMzNCBwcw==::UExMX01FTV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX01FTV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX01FTV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX01FTV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX01FTV9DTEtfRElWX0NBQ0hF::MQ==::UExMX01FTV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX1BBUkFN::Mg==::UExMX0FGSV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ==::MTUwLjA=::UExMX0FGSV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF::NjY2OCBwcw==::UExMX0FGSV9DTEtfRlJFUV9TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0FGSV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ==::MCBwcw==::UExMX0FGSV9DTEtfUEhBU0VfUFNfU0lNX1NUUl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ==::Mw==::UExMX0FGSV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9DTEtfRElWX0NBQ0hF::Mg==::UExMX0FGSV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN::Mw==::UExMX1dSSVRFX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfUEFSQU0=::MQ==::UExMX1dSSVRFX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX1dSSVRFX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX1dSSVRFX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX1dSSVRFX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX1dSSVRFX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX1dSSVRFX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FERFJfQ01EX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FERFJfQ01EX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MCBwcw==::UExMX0FERFJfQ01EX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FERFJfQ01EX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FERFJfQ01EX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF::MzAwLjA=::UExMX0FGSV9IQUxGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU=::MzMzNCBwcw==::UExMX0FGSV9IQUxGX0NMS19GUkVRX1NJTV9TVFJfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ==::MjUwMA==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF::MjUwMCBwcw==::UExMX0FGSV9IQUxGX0NMS19QSEFTRV9QU19TSU1fU1RSX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF::Mw==::UExMX0FGSV9IQUxGX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU=::MQ==::UExMX0FGSV9IQUxGX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX05JT1NfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX05JT1NfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX05JT1NfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX05JT1NfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX05JT1NfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX1BBUkFN::MA==::UExMX0NPTkZJR19DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0NPTkZJR19DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0NPTkZJR19DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0NPTkZJR19DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF::MA==::UExMX0NPTkZJR19DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX1AyQ19SRUFEX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX1AyQ19SRUFEX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF::MA==::UExMX1AyQ19SRUFEX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU=::MA==::UExMX1AyQ19SRUFEX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ==::MC4w::UExMX0MyUF9XUklURV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU=::MA==::UExMX0MyUF9XUklURV9DTEtfUEhBU0VfUFNfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ==::MA==::UExMX0MyUF9XUklURV9DTEtfTVVMVF9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF::MA==::UExMX0MyUF9XUklURV9DTEtfRElWX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX1BBUkFN::MC4w::UExMX0hSX0NMS19GUkVRX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX1BBUkFN::MA==::UExMX0hSX0NMS19NVUxUX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfUEFSQU0=::MA==::UExMX0hSX0NMS19ESVZfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19GUkVRX0NBQ0hF::MC4w::UExMX0hSX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ==::MA==::UExMX0hSX0NMS19QSEFTRV9QU19DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19NVUxUX0NBQ0hF::MA==::UExMX0hSX0NMS19NVUxUX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0hSX0NMS19ESVZfQ0FDSEU=::MA==::UExMX0hSX0NMS19ESVZfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX1BBUkFN"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfUEFSQU0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU=::MC4w::UExMX0FGSV9QSFlfQ0xLX0ZSRVFfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF::MA==::UExMX0FGSV9QSFlfQ0xLX1BIQVNFX1BTX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU=::MA==::UExMX0FGSV9QSFlfQ0xLX01VTFRfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ==::MA==::UExMX0FGSV9QSFlfQ0xLX0RJVl9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNFX0NBQ0hF::ZmFsc2U=::SVNfRVNfREVWSUNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVRX0NBQ0hF::MC4w::TUVNX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19GUkVRX0NBQ0hF::MC4w::UkVGX0NMS19GUkVRX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURV9DQUNIRQ==::VW5rbm93bg==::UkFURV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SENYX0NPTVBBVF9NT0RFX0NBQ0hF::ZmFsc2U=::SENYX0NPTVBBVF9NT0RFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ==::VW5rbm93bg==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NTUFORF9QSEFTRV9DQUNIRQ==::MC4w::Q09NTUFORF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX1BIQVNFX0NBQ0hF::MC4w::TUVNX0NLX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF::MC4w::UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ==::MC4w::QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF::MC4w::QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNFX0NBQ0hF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEVfQ0FDSEU=::VW5rbm93bg==::U0VRVUVOQ0VSX1RZUEVfQ0FDSEU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ==::ZmFsc2U=::VVNFX01FTV9DTEtfRlJFUV9DQUNIRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19DQUNIRV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX0NMS19QQVJBTV9WQUxJRA==::dHJ1ZQ==::UExMX0NMS19QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYVFJBX1JFUE9SVElORw==::ZmFsc2U=::RU5BQkxFX0VYVFJBX1JFUE9SVElORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0VYVFJBX1JFUE9SVF9QQVRI::MTA=::TlVNX0VYVFJBX1JFUE9SVF9QQVRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0lTU19QUk9CRVM=::ZmFsc2U=::RU5BQkxFX0lTU19QUk9CRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfUkVHX1dJRFRI::OA==::Q0FMSUJfUkVHX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NFUVVFTkNFUl9CRk0=::ZmFsc2U=::VVNFX1NFUVVFTkNFUl9CRk0="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::UExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0FGSV9IQUxGX0NMSw==::ZmFsc2U=::RW5hYmxlIEFGSSBoYWxmIHJhdGUgY2xvY2s="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q=::ZmFsc2U=::QUJTVFJBQ1RfUkVBTF9DT01QQVJFX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA==::ZmFsc2U=::SU5DTFVERV9CT0FSRF9ERUxBWV9NT0RFTA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw=::ZmFsc2U=::SU5DTFVERV9NVUxUSVJBTktfQk9BUkRfREVMQVlfTU9ERUw="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZX0lOVEVSTkFM::ZmFsc2U=::VVNFX0ZBS0VfUEhZX0lOVEVSTkFM"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0ZBS0VfUEhZ::ZmFsc2U=::VXNlIEZha2UgUEhZ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::MA==::Rk9SQ0VfTUFYX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF::ZmFsc2U=::VVNFX0FMTF9BRklfUEhBU0VTX0ZPUl9DT01NQU5EX0lTU1VF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNUUlVDVElWRV9DQUxJQg==::ZmFsc2U=::RW5hYmxlcyBOb24tRGVzdHJ1Y3RpdmUgQ2FsaWJyYXRpb24="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RklYX1JFQURfTEFURU5DWQ==::OA==::Rml4ZWQgUmVhZCBMYXRlbmN5"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1VTRVJfUkRJTU1fVkFMVUU=::ZmFsc2U=::VVNFX1VTRVJfUkRJTU1fVkFMVUU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF::ZmFsc2U=::RU5BQkxFX0RFTEFZX0NIQUlOX1dSSVRF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfRVJST1JfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfRVJST1JfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJBQ0tJTkdfV0FUQ0hfVEVTVA==::ZmFsc2U=::VFJBQ0tJTkdfV0FUQ0hfVEVTVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFSR0lOX1ZBUklBVElPTl9URVNU::ZmFsc2U=::TUFSR0lOX1ZBUklBVElPTl9URVNU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzA=::MF8wMDAwXzAwMDBfMDAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAx"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUk9NX1VTRVJfQUREXzE=::MF8wMDAwXzAwMDBfMTAwMA==::Q2FsaWJyYXRpb24gQWRkcmVzcyAy"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJFRkk=::MzUxMDA=::VHJlZmkgeCA5"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGUkVTSF9JTlRFUlZBTA==::MTUwMDA=::UmVmcmVzaCBJbnRlcnZhbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q=::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FMX1RFU1Q="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJGQw==::MzUw::VHJmYw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05PTl9ERVNfQ0FM::ZmFsc2U=::RU5BQkxFX05PTl9ERVNfQ0FM"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0NTUl9QT1JU::ZmFsc2U=::RVhQT1JUX0NTUl9QT1JU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0FERFJfV0lEVEg=::OA==::Q1NSX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0RBVEFfV0lEVEg=::MzI=::Q1NSX0RBVEFfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1NSX0JFX1dJRFRI::NA==::Q1NSX0JFX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0RFVklDRQ==::TUlTU0lOR19NT0RFTA==::TUVNX0RFVklDRQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw==::MQ==::TlVNX1NVQkdST1VQX1BFUl9SRUFEX0RRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw==::MA==::UVZMRF9FWFRSQV9GTE9QX1NUQUdFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UVZMRF9XUl9BRERSRVNTX09GRlNFVA==::NA==::UVZMRF9XUl9BRERSRVNTX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg=::NA==::TUFYX1dSSVRFX0xBVEVOQ1lfQ09VTlRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM=::MQ==::TlVNX1dSSVRFX1BBVEhfRkxPUF9TVEFHRVM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw==::MA==::TlVNX0FDX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM=::MA==::Rk9SQ0VEX05VTV9XUklURV9GUl9DWUNMRV9TSElGVFM="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw==::MQ==::TlVNX1dSSVRFX0ZSX0NZQ0xFX1NISUZUUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O::ZmFsc2U=::UEVSRk9STV9SRUFEX0FGVEVSX1dSSVRFX0NBTElCUkFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX0JVUlNUX0NPVU5UX1dJRFRI::MQ==::U0VRX0JVUlNUX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkNBTElCX0NPVU5UX1dJRFRI::Mg==::VkNBTElCX0NPVU5UX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1BIQVNFX0NPVU5URVJfV0lEVEg=::NA==::UExMX1BIQVNFX0NPVU5URVJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc=::Mg==::RFFTX0RFTEFZX0NIQUlOX1BIQVNFX1NFVFRJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX1BIQVNFX1NISUZU::OTAwMA==::RFFTX1BIQVNFX1NISUZU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H::Mg==::REVMQVlFRF9DTE9DS19QSEFTRV9TRVRUSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0lOX1JFU0VSVkU=::Mw==::SU9fRFFTX0lOX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX09VVF9SRVNFUlZF::Mw==::SU9fRFFTX09VVF9SRVNFUlZF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFfT1VUX1JFU0VSVkU=::MA==::SU9fRFFfT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRE1fT1VUX1JFU0VSVkU=::MA==::SU9fRE1fT1VUX1JFU0VSVkU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX0RFTEFZX09GRlNFVA==::MA==::SU9fRFFTX0VOX0RFTEFZX09GRlNFVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFTX0VOX1BIQVNFX01BWA==::Nw==::SU9fRFFTX0VOX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fRFFEUVNfT1VUX1BIQVNFX01BWA==::MTQ=::SU9fRFFEUVNfT1VUX1BIQVNFX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT::ZmFsc2U=::SU9fU0hJRlRfRFFTX0VOX1dIRU5fU0hJRlRfRFFT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M=::ZmFsc2U=::SFJfRERJT19PVVRfSEFTX1RIUkVFX1JFR1M="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19OUw==::My4zMzM=::TUVNX0NMS19OUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19QUw==::MzMzMy4w::TUVNX0NMS19QUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfTEZJRk9fT0ZGU0VU::NA==::Q0FMSUJfTEZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJfVkZJRk9fT0ZGU0VU::MTI=::Q0FMSUJfVkZJRk9fT0ZGU0VU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX09QQV9UQVA=::NDE2::REVMQVlfUEVSX09QQV9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RDSEFJTl9UQVA=::NTA=::REVMQVlfUEVSX0RDSEFJTl9UQVA="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ::NTA=::REVMQVlfUEVSX0RRU19FTl9EQ0hBSU5fVEFQ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0VOX0RFTEFZX01BWA==::Nw==::RFFTX0VOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0lOX0RFTEFZX01BWA==::MTU=::RFFTX0lOX0RFTEFZX01BWA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fSU5fREVMQVlfTUFY::MTU=::SU9fSU5fREVMQVlfTUFY"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMV9ERUxBWV9NQVg=::MTU=::SU9fT1VUMV9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fT1VUMl9ERUxBWV9NQVg=::Nw==::SU9fT1VUMl9ERUxBWV9NQVg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU9fU1RBTkRBUkQ=::U1NUTC0xNQ==::SS9PIHN0YW5kYXJk"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VkZJRk9fQVNfU0hJRlRfUkVH::dHJ1ZQ==::VkZJRk9fQVNfU0hJRlRfUkVH"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRVUVOQ0VSX1RZUEU=::TklPUw==::U2VxdWVuY2VyIG9wdGltaXphdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19IRVhfRklMRV9MT0NBVElPTg==::Li4v::TklPU19IRVhfRklMRV9MT0NBVElPTg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw==::ZmFsc2U=::QURWRVJUSVpFX1NFUVVFTkNFUl9TV19CVUlMRF9GSUxFUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U=::dHJ1ZQ==::TkVHQVRJVkVfV1JJVEVfQ0tfUEhBU0U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfV0w=::NQ==::TUVNX1RfV0w="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1RfUkw=::NQ==::TUVNX1RfUkw="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NMS0JVRg==::ZmFsc2U=::UEhZX0NMS0JVRg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw==::ZmFsc2U=::VVNFX0xEQ19BU19MT1dfU0tFV19DTE9DSw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0xEQ19GT1JfQUREUl9DTUQ=::ZmFsc2U=::VVNFX0xEQ19GT1JfQUREUl9DTUQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA==::ZmFsc2U=::RU5BQkxFX0xEQ19NRU1fQ0tfQURKVVNUTUVOVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA==::MA==::TUVNX0NLX0xEQ19BREpVU1RNRU5UX1RIUkVTSE9MRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA==::dHJ1ZQ==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF::MA==::TERDX0ZPUl9BRERSX0NNRF9NRU1fQ0tfQ1BTX1BIQVNF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA==::ZmFsc2U=::Rk9SQ0VEX05PTl9MRENfQUREUl9DTURfTUVNX0NLX0lOVkVSVA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU::ZmFsc2U=::Tk9OX0xEQ19BRERSX0NNRF9NRU1fQ0tfSU5WRVJU"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfQzJQ::ZmFsc2U=::UkVHSVNURVJfQzJQ"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS::ZmFsc2U=::RUFSTFlfQUREUl9DTURfQ0xLX1RSQU5TRkVS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUFYMTBfUlRMX1NFUQ==::dHJ1ZQ==::TUFYMTBfUlRMX1NFUQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX09OTFk=::ZmFsc2U=::R2VuZXJhdGUgUEhZIG9ubHk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0VRX01PREU=::MA==::RnVsbC0gb3IgaGFsZi1yYXRlIHNlcXVlbmNlcg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QURWQU5DRURfQ0tfUEhBU0VT::ZmFsc2U=::QWR2YW5jZWQgY2xvY2sgcGhhc2UgY29udHJvbA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UDJDX1JFQURfQ0xPQ0tfQUREX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgcGVyaXBoZXJ5LXRvLWNvcmUgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QzJQX1dSSVRFX0NMT0NLX0FERF9QSEFTRQ==::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgY29yZS10by1wZXJpcGhlcnkgdHJhbnNmZXI="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNWX1BIWV9DTEtfQUREX0ZSX1BIQVNF::MC4w::QWRkaXRpb25hbCBwaGFzZSBmb3IgUEhZIGNsb2NrIHRyZWU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX1ZPTFRBR0U=::MS41ViBERFIz::U3VwcGx5IFZvbHRhZ2U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U0tJUF9NRU1fSU5JVA==::dHJ1ZQ==::U2tpcCBNZW1vcnkgSW5pdGlhbGl6YXRpb24gRGVsYXlz"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF::SU5WRVJURURfRFFTX0JVUw==::UkVBRF9EUV9EUVNfQ0xPQ0tfU09VUkNF"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfSU5QVVRfUkVHX1VTRV9DTEtO::ZmFsc2U=::RFFfSU5QVVRfUkVHX1VTRV9DTEtO"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFTX0RRU05fTU9ERQ==::RElGRkVSRU5USUFM::RFFTX0RRU05fTU9ERQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RFQlVHX0lORk9fV0lEVEg=::MzI=::QUZJX0RFQlVHX0lORk9fV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0FMSUJSQVRJT05fTU9ERQ==::U2tpcA==::QXV0by1jYWxpYnJhdGlvbiBtb2Rl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fREFUQV9XSURUSA==::MzI=::TklPU19ST01fREFUQV9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TklPU19ST01fQUREUkVTU19XSURUSA==::MTM=::TklPU19ST01fQUREUkVTU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVBRF9GSUZPX1NJWkU=::OA==::RGVwdGggb2YgdGhlIHJlYWQgRklGTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9FTkFCTEVE::ZmFsc2U=::RW5hYmxlIENvbmZpZ3VyYXRpb24gYW5kIFN0YXR1cyBSZWdpc3RlciBJbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEhZX0NTUl9DT05ORUNUSU9O::SU5URVJOQUxfSlRBRw==::Q1NSIHBvcnQgaG9zdCBpbnRlcmZhY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFUl9ERUJVR19MRVZFTA==::MQ==::RGVidWdnaW5nIGZlYXR1cmUgc2V0"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFUkFURV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgbWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEU=::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURQ==::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURQ==::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURQ==::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0NLX0NLTl9TTEVXX1JBVEVfQVBQTElFRA==::Mi4w::Q0svQ0sjIHNsZXcgcmF0ZSAoRGlmZmVyZW50aWFsKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NMRVdfUkFURV9BUFBMSUVE::MS4w::QWRkcmVzcyBhbmQgY29tbWFuZCBzbGV3IHJhdGU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRU19EUVNOX1NMRVdfUkFURV9BUFBMSUVE::Mi4w::RFFTL0RRUyMgc2xldyByYXRlIChEaWZmZXJlbnRpYWwp"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1NMRVdfUkFURV9BUFBMSUVE::MS4w::RFEgc2xldyByYXRl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJUw==::MC4w::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSA==::MC4w::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REUw==::MC4w::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESA==::MC4w::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJU19BUFBMSUVE::MC4zMg==::dElT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RJSF9BUFBMSUVE::MC4yMg==::dElI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1REU19BUFBMSUVE::MC4xNg==::dERT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1RESF9BUFBMSUVE::MC4xNDU=::dERI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0lTSV9NRVRIT0Q=::QVVUTw==::RGVyYXRpbmcgTWV0aG9k"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1U=::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT04=::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUU=::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTg==::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRQ==::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fU1VfQVBQTElFRA==::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChzZXR1cCk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX0VZRV9SRURVQ1RJT05fSF9BUFBMSUVE::MC4w::QWRkcmVzcyBhbmQgY29tbWFuZCBleWUgcmVkdWN0aW9uIChob2xkKQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX0VZRV9SRURVQ1RJT05fQVBQTElFRA==::MC4w::V3JpdGUgRFEgZXllIHJlZHVjdGlvbg=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX0RRU19BUlJJVkFMX1RJTUVfQVBQTElFRA==::MC4w::V3JpdGUgRGVsdGEgRFFTIGFycml2YWwgdGltZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1JFQURfRFFfRVlFX1JFRFVDVElPTl9BUFBMSUVE::MC4w::UmVhZCBEUSBleWUgcmVkdWN0aW9u"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RFTFRBX1JFQURfRFFTX0FSUklWQUxfVElNRV9BUFBMSUVE::MC4w::UmVhZCBEZWx0YSBEUVMgYXJyaXZhbCB0aW1l"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBEUS9EUVMgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUNfUEFDS0FHRV9ERVNLRVc=::ZmFsc2U=::RlBHQSBBZGRyZXNzL0NvbW1hbmQgcGFja2FnZSBza2V3cyBkZXNrZXdlZCBvbiBib2FyZA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9DS19ERUxBWQ==::MC4yNDQz::TWF4aW11bSBDSyBkZWxheSB0byBESU1NL2RldmljZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX01BWF9EUVNfREVMQVk=::MC4yMTkyOQ==::TWF4aW11bSBEUVMgZGVsYXkgdG8gRElNTS9kZXZpY2U="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU4=::MC4wMjI4Ng==::TWluaW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA==::MC4wMjI4Ng==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NSU5fQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVg=::MC4wNDQyOQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gQ0sgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA==::MC4wNDQyOQ==::VElNSU5HX0JPQVJEX1NLRVdfQ0tEUVNfRElNTV9NQVhfQVBQTElFRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NUw==::MC4wNQ==::TWF4aW11bSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRElNTXMvZGV2aWNlcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE::MC4w::VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9ESU1NU19BUFBMSUVE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfV0lUSElOX0RRUw==::MC4wMTgwNg==::TWF4aW11bSBza2V3IHdpdGhpbiBEUVMgZ3JvdXA="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX1NLRVdfQkVUV0VFTl9EUVM=::MC4wNDI0Ng==::TWF4aW11bSBza2V3IGJldHdlZW4gRFFTIGdyb3Vwcw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0RRX1RPX0RRU19TS0VX::LTAuMDExNTI=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gRFEgYW5kIERRUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1NLRVc=::MC4wNzgwMQ==::TWF4aW11bSBza2V3IHdpdGhpbiBhZGRyZXNzIGFuZCBjb21tYW5kIGJ1cw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VElNSU5HX0JPQVJEX0FDX1RPX0NLX1NLRVc=::LTAuMDQ3MDk=::QXZlcmFnZSBkZWxheSBkaWZmZXJlbmNlIGJldHdlZW4gYWRkcmVzcyBhbmQgY29tbWFuZCBhbmQgQ0s="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkFURQ==::SGFsZg==::UmF0ZSBvbiBBdmFsb24tTU0gaW50ZXJmYWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TUVNX0NMS19GUkVR::MzAwLjA=::TWVtb3J5IGNsb2NrIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX01FTV9DTEtfRlJFUQ==::ZmFsc2U=::VXNlIHNwZWNpZmllZCBmcmVxdWVuY3kgaW5zdGVhZCBvZiBjYWxjdWxhdGVkIGZyZXF1ZW5jeQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0RRU19UUkFDS0lORw==::ZmFsc2U=::VVNFX0RRU19UUkFDS0lORw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfRFFTX1RSQUNLSU5H::QVVUTw==::Rm9yY2UgRFFTIFRyYWNraW5nIEVuYWJsZWQvRGlzYWJsZWQ="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX0hQU19EUVNfVFJBQ0tJTkc=::ZmFsc2U=::VVNFX0hQU19EUVNfVFJBQ0tJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VFJLX1BBUkFMTEVMX1NDQ19MT0FE::ZmFsc2U=::VFJLX1BBUkFMTEVMX1NDQ19MT0FE"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "VVNFX1NIQURPV19SRUdT::ZmFsc2U=::VVNFX1NIQURPV19SRUdT"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfU0hBRE9XX1JFR1M=::QVVUTw==::U2hhZG93IFJlZ2lzdGVycw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RFFfRERS::MQ==::RFFfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9DTURfRERS::MA==::QUREUl9DTURfRERS"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JBVEVfUkFUSU8=::Mg==::QUZJX1JBVEVfUkFUSU8="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REFUQV9SQVRFX1JBVElP::Mg==::REFUQV9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUREUl9SQVRFX1JBVElP::MQ==::QUREUl9SQVRFX1JBVElP"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0FERFJfV0lEVEg=::Mjg=::QUZJX0FERFJfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0JBTktBRERSX1dJRFRI::Ng==::QUZJX0JBTktBRERSX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NPTlRST0xfV0lEVEg=::Mg==::QUZJX0NPTlRST0xfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NTX1dJRFRI::Mg==::QUZJX0NTX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19FTl9XSURUSA==::Mg==::QUZJX0NMS19FTl9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RNX1dJRFRI::NA==::QUZJX0RNX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0RRX1dJRFRI::MzI=::QUZJX0RRX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX09EVF9XSURUSA==::Mg==::QUZJX09EVF9XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSSVRFX0RRU19XSURUSA==::Mg==::QUZJX1dSSVRFX0RRU19XSURUSA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JMQVRfV0lEVEg=::Ng==::QUZJX1JMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dMQVRfV0lEVEg=::Ng==::QUZJX1dMQVRfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1JSQU5LX1dJRFRI::Mg==::QUZJX1JSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX1dSQU5LX1dJRFRI::Mg==::QUZJX1dSQU5LX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "QUZJX0NMS19QQUlSX0NPVU5U::MQ==::QUZJX0NMS19QQUlSX0NPVU5U"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw==::ZmFsc2U=::TVJTX01JUlJPUl9QSU5HX1BPTkdfQVRTTw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::U1lTX0lORk9fREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UFJFX1ZfU0VSSUVTX0ZBTUlMWQ==::ZmFsc2U=::UFJFX1ZfU0VSSUVTX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9DQUNIRV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA==::dHJ1ZQ==::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTV9WQUxJRA=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYMTA=::UEFSU0VfRlJJRU5ETFlfREVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWV9QQVJBTQ==::TUFYIDEw::REVWSUNFX0ZBTUlMWV9QQVJBTQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "U1BFRURfR1JBREU=::Ng==::U3BlZWQgR3JhZGU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SVNfRVNfREVWSUNF::ZmFsc2U=::RW5naW5lZXJpbmcgU2FtcGxlIChFUykgRGV2aWNl"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RElTQUJMRV9DSElMRF9NRVNTQUdJTkc=::dHJ1ZQ==::RElTQUJMRV9DSElMRF9NRVNTQUdJTkc="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEFSRF9QSFk=::ZmFsc2U=::SEFSRF9QSFk="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQUw==::ZmFsc2U=::SEhQX0hQUw=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19WRVJJRklDQVRJT04=::ZmFsc2U=::SEhQX0hQU19WRVJJRklDQVRJT04="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SEhQX0hQU19TSU1VTEFUSU9O::ZmFsc2U=::SEhQX0hQU19TSU1VTEFUSU9O"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "SFBTX1BST1RPQ09M::REVGQVVMVA==::TWVtb3J5IFByb3RvY29s"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q1VUX05FV19GQU1JTFlfVElNSU5H::dHJ1ZQ==::Q1VUX05FV19GQU1JTFlfVElNSU5H"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX0RFTEFZX0NUUkxfV0lEVEg=::Ng==::RExMX0RFTEFZX0NUUkxfV0lEVEg="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX09GRlNFVF9DVFJMX1dJRFRI::Ng==::RExMX09GRlNFVF9DVFJMX1dJRFRI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQlVGRkVSX01PREU=::SElHSA==::REVMQVlfQlVGRkVSX01PREU="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "REVMQVlfQ0hBSU5fTEVOR1RI::OA==::REVMQVlfQ0hBSU5fTEVOR1RI"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "RExMX1NIQVJJTkdfTU9ERQ==::Tm9uZQ==::RExMIHNoYXJpbmcgbW9kZQ=="
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_COMPONENT_PARAMETER "UkVGX0NMS19QRVJJT0RfUFM=::MTAwMDA=::UkVGX0NMS19QRVJJT0RfUFM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfY3B1"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TmlvcyBJSSBQcm9jZXNzb3I="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE5pb3MgSUkgUHJvY2Vzc29y"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dG1yX2VuYWJsZWQ=::ZmFsc2U=::TmlvcyBJSSBUcmlwbGUgTW9kZSBSZWR1bmRhbmN5"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlX3Rtcl9pbmo=::ZmFsc2U=::RGlzYWJsZWQgVE1SIEVycm9yIEluamVjdGlvbiBQb3J0"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93VW5wdWJsaXNoZWRTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBVbnB1Ymxpc2hlZCBTZXR0aW5ncw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93SW50ZXJuYWxTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBJbnRlcm5hbCBWZXJpZmljYXRpb24gU2V0dGluZ3M="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19wcmVjaXNlSWxsZWdhbE1lbUFjY2Vzc0V4Y2VwdGlvbg==::ZmFsc2U=::TWlzYWxpZ25lZCBtZW1vcnkgYWNjZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRQQ0I=::ZmFsc2U=::c2V0dGluZ19leHBvcnRQQ0I="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRkZWJ1Z2luZm8=::ZmFsc2U=::RXhwb3J0IEluc3RydWN0aW9uIEV4ZWN1dGlvbiBTdGF0ZXM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19jbGVhclhCaXRzTEROb25CeXBhc3M=::dHJ1ZQ==::Q2xlYXIgWCBkYXRhIGJpdHM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaWdFbmRpYW4=::ZmFsc2U=::c2V0dGluZ19iaWdFbmRpYW4="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRfbGFyZ2VfUkFNcw==::ZmFsc2U=::RXhwb3J0IExhcmdlIFJBTXM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2VuYWJsZWQ=::ZmFsc2U=::QVNJQyBlbmFibGVk"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVnaXN0ZXJfZmlsZV9wb3I=::ZmFsc2U=::UmVnaXN0ZXIgRmlsZSBQT1I="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3N5bm9wc3lzX3RyYW5zbGF0ZV9vbl9vZmY=::ZmFsc2U=::QVNJQyBTeW5vcHN5cyB0cmFuc2xhdGU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3RoaXJkX3BhcnR5X3N5bnRoZXNpcw==::ZmFsc2U=::QVNJQyB0aGlyZCBwYXJ0eSBzeW50aGVzaXM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2FkZF9zY2FuX21vZGVfaW5wdXQ=::ZmFsc2U=::QVNJQyBhZGQgc2NhbiBtb2RlIGlucHV0"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfdmVyc2lvbg==::MQ==::TmlvcyBJSSBPQ0kgVmVyc2lvbg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ=::ZmFsc2U=::RmFzdCBSZWdpc3RlciBSZWFk"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRIb3N0RGVidWdQb3J0::ZmFsc2U=::RXhwb3J0IERlYnVnIEhvc3QgU2xhdmU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfZXhwb3J0X2p0YWdfc2lnbmFscw==::ZmFsc2U=::RXhwb3J0IEpUQUcgc2lnbmFscw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hdmFsb25EZWJ1Z1BvcnRQcmVzZW50::ZmFsc2U=::QXZhbG9uIERlYnVnIFBvcnQgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbHdheXNFbmNyeXB0::dHJ1ZQ==::QWx3YXlzIGVuY3J5cHQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW9fcmVnaW9uc2l6ZQ==::MA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zdXBwb3J0MzFiaXRkY2FjaGVieXBhc3M=::dHJ1ZQ==::VXNlIG1vc3Qtc2lnbmlmaWNhbnQgYWRkcmVzcyBiaXQgaW4gcHJvY2Vzc29yIHRvIGJ5cGFzcyBkYXRhIGNhY2hl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRyYWNl::dHJ1ZQ==::R2VuZXJhdGUgdHJhY2UgZmlsZSBkdXJpbmcgUlRMIHNpbXVsYXRpb24="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbGxvd19icmVha19pbnN0::ZmFsc2U=::QWxsb3cgQnJlYWsgaW5zdHJ1Y3Rpb25z"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRlc3RFbmRDaGVja2Vy::ZmFsc2U=::QWN0aXZhdGUgdGVzdCBlbmQgY2hlY2tlcg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2Nfc2ltX3Rlc3RfcG9ydHM=::ZmFsc2U=::RW5hYmxlIEVDQyBzaW11bGF0aW9uIHRlc3QgcG9ydHM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlb2NpdHJhY2U=::ZmFsc2U=::RGlzYWJsZSBjb21wdHIgZ2VuZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZU1vbml0b3Jz::dHJ1ZQ==::QWN0aXZhdGUgbW9uaXRvcnM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IRExTaW1DYWNoZXNDbGVhcmVk::dHJ1ZQ==::SERMIHNpbXVsYXRpb24gY2FjaGVzIGNsZWFyZWQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IQnJlYWtUZXN0::ZmFsc2U=::QWRkIEhCcmVhayBSZXF1ZXN0IHBvcnQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmVha3NsYXZlb3ZlcmlkZQ==::ZmFsc2U=::TWFudWFsbHkgYXNzaWduIGJyZWFrIHNsYXZl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNUFU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNTVU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1UmVzZXQ=::ZmFsc2U=::SW5jbHVkZSBjcHVfcmVzZXRyZXF1ZXN0IGFuZCBjcHVfcmVzZXR0YWtlbiBzaWduYWxz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::SW5jbHVkZSByZXNldF9yZXEgc2lnbmFsIGZvciBPQ0kgUkFNIGFuZCBNdWx0aS1DeWNsZSBDdXN0b20gSW5zdHJ1Y3Rpb25z"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZW1vdmVSQU1pbml0::ZmFsc2U=::UmVtb3ZlIFJBTSBJbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ190bXJfb3V0cHV0X2Rpc2FibGU=::ZmFsc2U=::Q3JlYXRlIGEgc2lnbmFsIHRvIGRpc2FibGUgVE1SIG91dHB1dHM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaGFkb3dSZWdpc3RlclNldHM=::MA==::TnVtYmVyIG9mIHNoYWRvdyByZWdpc3RlciBzZXRzICgwLTYzKQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRPZmZzZXQ=::MA==::UmVzZXQgdmVjdG9yIG9mZnNldA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uT2Zmc2V0::Mjg4::RXhjZXB0aW9uIHZlY3RvciBvZmZzZXQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1SUQ=::MA==::Q1BVSUQgY29udHJvbCByZWdpc3RlciB2YWx1ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtPZmZzZXQ=::MzI=::QnJlYWsgdmVjdG9yIG9mZnNldA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRTbGF2ZQ==::ZXh0X2ZsYXNoLmF2bF9tZW0=::UmVzZXQgdmVjdG9yIG1lbW9yeQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uU2xhdmU=::ZGRyM19yYW0uYXZs::RXhjZXB0aW9uIHZlY3RvciBtZW1vcnk="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZQ==::Y3B1Lmp0YWdfZGVidWdfbW9kdWxl::QnJlYWsgdmVjdG9yIG1lbW9yeQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pbnRlcnJ1cHRDb250cm9sbGVyVHlwZQ==::SW50ZXJuYWw=::SW50ZXJydXB0IGNvbnRyb2xsZXI="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmFuY2hwcmVkaWN0aW9udHlwZQ==::RHluYW1pYw==::QnJhbmNoIHByZWRpY3Rpb24gdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaHRQdHJTeg==::OA==::TnVtYmVyIG9mIGVudHJpZXMgKDItYml0cyB3aWRlKQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1QXJjaFJldg==::MQ==::QXJjaGl0ZWN0dXJlIFJldmlzaW9u"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw=::ZmFsc2U=::c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2hpZnRlclR5cGU=::ZmFzdF9sZV9zaGlmdA==::c2hpZnRlclR5cGU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllclR5cGU=::bXVsX2Zhc3QzMg==::bXVsdGlwbGllclR5cGU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXVsX3NoaWZ0X2Nob2ljZQ==::MA==::TXVsdGlwbHkvU2hpZnQvUm90YXRlIEhhcmR3YXJl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGl2aWRlclR5cGU=::bm9fZGl2::RGl2aWRlIEhhcmR3YXJl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW1wbA==::RmFzdA==::TmlvcyBJSSBDb3Jl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3NpemU=::MjA0OA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZmFfY2FjaGVfbGluZXNpemU=::MA==::TGluZSBTaXpl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX251bVRDSU0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBpbnN0cnVjdGlvbiBtYXN0ZXIgcG9ydHM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX2J1cnN0VHlwZQ==::Tm9uZQ==::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGluc3RydWN0aW9uX21hc3Rlcg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0cw==::ZmFsc2U=::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGRhdGFfbWFzdGVy"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3ZpY3RpbV9idWZfaW1wbA==::cmFt::VmljdGltIGJ1ZmZlciBpbXBsZW1lbnRhdGlvbg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemU=::MjA0OA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX251bVRDRE0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBkYXRhIG1hc3RlciBwb3J0cw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnR2ZWN0b3Jz::ZmFsc2U=::RXhwb3J0IFZlY3RvcnM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ191c2VkZXNpZ253YXJl::ZmFsc2U=::VXNlIERlc2lnbndhcmUgQ29tcG9uZW50cw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2NfcHJlc2VudA==::ZmFsc2U=::RUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pY19lY2NfcHJlc2VudA==::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gQ2FjaGUgRUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZl9lY2NfcHJlc2VudA==::dHJ1ZQ==::UmVnaXN0ZXIgRmlsZSBFQ0MgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19tbXVfZWNjX3ByZXNlbnQ=::dHJ1ZQ==::TU1VIEVDQyBQcmVzZW50"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kY19lY2NfcHJlc2VudA==::ZmFsc2U=::RGF0YSBDYWNoZSBFQ0MgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pdGNtX2VjY19wcmVzZW50::ZmFsc2U=::SW5zdHJ1Y3Rpb24gVENNIEVDQyBQcmVzZW50"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kdGNtX2VjY19wcmVzZW50::ZmFsc2U=::RGF0YSBUQ00gRUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVnZmlsZV9yYW1CbG9ja1R5cGU=::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUluaXQ=::ZmFsc2U=::SW5pdGlhbGl6ZWQgT0NJIFJBTQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::TU1VIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Ymh0X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::QkhUIFJBTSBCbG9jayBUeXBl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2R4X2VuYWJsZWQ=::ZmFsc2U=::Q0RYIChDb2RlIERlbnNpdHkgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB4X2VuYWJsZWQ=::ZmFsc2U=::bXB4X2VuYWJsZWQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZW5hYmxlZA==::dHJ1ZQ==::SW5jbHVkZSBKVEFHIERlYnVn"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJpZ2dlckFybWluZw==::dHJ1ZQ==::VHJpZ2dlciBBcm1pbmc="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGVidWdSZXFTaWduYWxz::ZmFsc2U=::SW5jbHVkZSBkZWJ1Z3JlcSBhbmQgZGVidWdhY2sgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfYXNzaWduSnRhZ0luc3RhbmNlSUQ=::ZmFsc2U=::QXNzaWduIEpUQUcgSW5zdGFuY2UgSUQgZm9yIGRlYnVnIGNvcmUgbWFudWFsbHk="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfanRhZ0luc3RhbmNlSUQ=::MA==::SlRBRyBJbnN0YW5jZSBJRCB2YWx1ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfaHdicmVha3BvaW50::Mg==::SGFyZHdhcmUgQnJlYWtwb2ludHM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyaWdnZXI=::MA==::RGF0YSBUcmlnZ2Vycw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJhY2VUeXBl::bm9uZQ==::VHJhY2UgVHlwZXM="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWFzdGVyX2FkZHJfbWFw::ZmFsc2U=::TWFudWFsbHkgU2V0IE1hc3RlciBCYXNlIEFkZHJlc3MgYW5kIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3NpemU=::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::Rmxhc2ggSW5zdHJ1Y3Rpb24gTWFzdGVyIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3NpemU=::MA==::Rmxhc2ggSW5zdHJ1Y3Rpb24gTWFzdGVyIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ==::MA==::RGF0YSBNYXN0ZXIgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfc2l6ZQ==::MA==::RGF0YSBNYXN0ZXIgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAwIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAwIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAxIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAxIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAyIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAyIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAzIEJhc2UgQWRkcmVzcw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAzIFNpemU="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDAgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDAgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDEgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDEgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDIgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDIgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDMgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDMgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ==::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEhpZ2ggUGVyZm9ybWFuY2UgQmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfc2l6ZQ==::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEhpZ2ggUGVyZm9ybWFuY2UgU2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl::MA==::RGF0YSBNYXN0ZXIgSGlnaCBQZXJmb3JtYW5jZSBCYXNlIEFkZHJlc3M="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9zaXpl::MA==::RGF0YSBNYXN0ZXIgSGlnaCBQZXJmb3JtYW5jZSBTaXpl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRBYnNvbHV0ZUFkZHI=::MzM1NTQ0MzIw::UmVzZXQgdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uQWJzb2x1dGVBZGRy::MTM0MjE4MDE2::RXhjZXB0aW9uIHZlY3Rvcg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtBYnNvbHV0ZUFkZHI=::NDA2ODU3NzYw::QnJlYWsgdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNBYnNBZGRy::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0c19kZXJpdmVk::ZmFsc2U=::ZGNhY2hlX2J1cnN0c19kZXJpdmVk"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemVfZGVyaXZlZA==::MjA0OA==::ZGNhY2hlX3NpemVfZGVyaXZlZA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZV9kZXJpdmVk::Y3B1LmRlYnVnX21lbV9zbGF2ZQ==::YnJlYWtTbGF2ZV9kZXJpdmVk"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ=::MzI=::ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ==::dHJ1ZQ==::c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29u::InN5bnRoZXNpcyB0cmFuc2xhdGVfb24i::dHJhbnNsYXRlX29u"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29mZg==::InN5bnRoZXNpcyB0cmFuc2xhdGVfb2ZmIg==::dHJhbnNsYXRlX29mZg=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfb25jaGlwdHJhY2U=::ZmFsc2U=::ZGVidWdfb25jaGlwdHJhY2U="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfb2ZmY2hpcHRyYWNl::ZmFsc2U=::ZGVidWdfb2ZmY2hpcHRyYWNl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfaW5zdHRyYWNl::ZmFsc2U=::ZGVidWdfaW5zdHRyYWNl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyYWNl::ZmFsc2U=::ZGVidWdfZGF0YXRyYWNl"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdEFkZHJXaWR0aA==::Mjk=::aW5zdEFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZmFBZGRyV2lkdGg=::MQ==::ZmFBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YUFkZHJXaWR0aA==::Mjk=::ZGF0YUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgdHlwZT0nYWx0ZXJhX21lbV9pZl9kZHIzX2VtaWYuYXZsJyAvPjxzbGF2ZSBuYW1lPSdleHRfZmxhc2guYXZsX21lbScgc3RhcnQ9JzB4MTQwMDAwMDAnIGVuZD0nMHgxODAwMDAwMCcgdHlwZT0nYWx0ZXJhX2dlbmVyaWNfcXVhZF9zcGlfY29udHJvbGxlci5hdmxfbWVtJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfZmxhc2guZGF0YScgc3RhcnQ9JzB4MTgyMDAwMDAnIGVuZD0nMHgxODM2MDAwMCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5kYXRhJyAvPjxzbGF2ZSBuYW1lPSdjcHUuZGVidWdfbWVtX3NsYXZlJyBzdGFydD0nMHgxODQwMjgwMCcgZW5kPScweDE4NDAzMDAwJyB0eXBlPSdhbHRlcmFfbmlvczJfZ2VuMi5kZWJ1Z19tZW1fc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::aW5zdFNsYXZlTWFwUGFyYW0="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgdHlwZT0nYWx0ZXJhX21lbV9pZl9kZHIzX2VtaWYuYXZsJyAvPjxzbGF2ZSBuYW1lPSdleHRfZmxhc2guYXZsX21lbScgc3RhcnQ9JzB4MTQwMDAwMDAnIGVuZD0nMHgxODAwMDAwMCcgdHlwZT0nYWx0ZXJhX2dlbmVyaWNfcXVhZF9zcGlfY29udHJvbGxlci5hdmxfbWVtJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfZmxhc2guZGF0YScgc3RhcnQ9JzB4MTgyMDAwMDAnIGVuZD0nMHgxODM2MDAwMCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5kYXRhJyAvPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MTg0MDI4MDAnIGVuZD0nMHgxODQwMzAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdldGhfdHNlLmNvbnRyb2xfcG9ydCcgc3RhcnQ9JzB4MTg0MDMwMDAnIGVuZD0nMHgxODQwMzQwMCcgdHlwZT0nYWx0ZXJhX2V0aF90c2UuY29udHJvbF9wb3J0JyAvPjxzbGF2ZSBuYW1lPSdjYWxpYnJhdGlvbl9yYW0uczEnIHN0YXJ0PScweDE4NDAzNDAwJyBlbmQ9JzB4MTg0MDM2ODAnIHR5cGU9J2FsdGVyYV9hdmFsb25fb25jaGlwX21lbW9yeTIuczEnIC8+PHNsYXZlIG5hbWU9J2ZyYW1lX3RpbWVyLnMxJyBzdGFydD0nMHgxODQwM0MwMCcgZW5kPScweDE4NDAzQzIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdkZWJ1Z191YXJ0LnMxJyBzdGFydD0nMHgxODQwM0MyMCcgZW5kPScweDE4NDAzQzQwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3VhcnQuczEnIC8+PHNsYXZlIG5hbWU9J291dHB1dF9waW8uczEnIHN0YXJ0PScweDE4NDAzQzQwJyBlbmQ9JzB4MTg0MDNDNjAnIHR5cGU9J2FsdGVyYV9hdmFsb25fcGlvLnMxJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgxODQwM0M2MCcgZW5kPScweDE4NDAzQzgwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdtc2dkbWFfcngucHJlZmV0Y2hlcl9jc3InIHN0YXJ0PScweDE4NDAzQzgwJyBlbmQ9JzB4MTg0MDNDQTAnIHR5cGU9J2FsdGVyYV9tc2dkbWEucHJlZmV0Y2hlcl9jc3InIC8+PHNsYXZlIG5hbWU9J21zZ2RtYV90eC5wcmVmZXRjaGVyX2Nzcicgc3RhcnQ9JzB4MTg0MDNDQTAnIGVuZD0nMHgxODQwM0NDMCcgdHlwZT0nYWx0ZXJhX21zZ2RtYS5wcmVmZXRjaGVyX2NzcicgLz48c2xhdmUgbmFtZT0ndWRwX2dlbmVyYXRvci5jc3InIHN0YXJ0PScweDE4NDAzQ0MwJyBlbmQ9JzB4MTg0MDNDRTAnIHR5cGU9J3VkcF9nZW5lcmF0b3IuY3NyJyAvPjxzbGF2ZSBuYW1lPSdtc2dkbWFfcnguY3NyJyBzdGFydD0nMHgxODQwM0NFMCcgZW5kPScweDE4NDAzRDAwJyB0eXBlPSdhbHRlcmFfbXNnZG1hLmNzcicgLz48c2xhdmUgbmFtZT0nbXNnZG1hX3R4LmNzcicgc3RhcnQ9JzB4MTg0MDNEMDAnIGVuZD0nMHgxODQwM0QyMCcgdHlwZT0nYWx0ZXJhX21zZ2RtYS5jc3InIC8+PHNsYXZlIG5hbWU9J2V4dF9mbGFzaC5hdmxfY3NyJyBzdGFydD0nMHgxODQwM0QyMCcgZW5kPScweDE4NDAzRDQwJyB0eXBlPSdhbHRlcmFfZ2VuZXJpY19xdWFkX3NwaV9jb250cm9sbGVyLmF2bF9jc3InIC8+PHNsYXZlIG5hbWU9J2J1dHRvbl9waW8uczEnIHN0YXJ0PScweDE4NDAzRDQwJyBlbmQ9JzB4MTg0MDNENTAnIHR5cGU9J2FsdGVyYV9hdmFsb25fcGlvLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW5zb3JfaW50ZXJmYWNlLmNzcicgc3RhcnQ9JzB4MTg0MDNENTAnIGVuZD0nMHgxODQwM0Q2MCcgdHlwZT0nc2Vuc29yX3JlY29uLmNzcicgLz48c2xhdmUgbmFtZT0nb25jaGlwX2ZsYXNoLmNzcicgc3RhcnQ9JzB4MTg0MDNENjAnIGVuZD0nMHgxODQwM0Q2OCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5jc3InIC8+PHNsYXZlIG5hbWU9J3N5c2lkLmNvbnRyb2xfc2xhdmUnIHN0YXJ0PScweDE4NDAzRDY4JyBlbmQ9JzB4MTg0MDNENzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fc3lzaWRfcXN5cy5jb250cm9sX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::TUFYIDEw::ZGV2aWNlRmFtaWx5TmFtZQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::NjE=::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::MTQ=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::MTQ=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfY3B1X2NwdQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "TmlvcyBJSSBQcm9jZXNzb3IgVW5pdA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_INTERNAL "On"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE5pb3MgSUkgVW5pdCBQcm9jZXNzb3I="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1X25hbWU=::Y3B1::Y3B1X25hbWU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93VW5wdWJsaXNoZWRTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBVbnB1Ymxpc2hlZCBTZXR0aW5ncw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93SW50ZXJuYWxTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBJbnRlcm5hbCBWZXJpZmljYXRpb24gU2V0dGluZ3M="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19wcmVjaXNlSWxsZWdhbE1lbUFjY2Vzc0V4Y2VwdGlvbg==::ZmFsc2U=::TWlzYWxpZ25lZCBtZW1vcnkgYWNjZXNz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRQQ0I=::ZmFsc2U=::c2V0dGluZ19leHBvcnRQQ0I="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRkZWJ1Z2luZm8=::ZmFsc2U=::RXhwb3J0IEluc3RydWN0aW9uIEV4ZWN1dGlvbiBTdGF0ZXM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19jbGVhclhCaXRzTEROb25CeXBhc3M=::dHJ1ZQ==::Q2xlYXIgWCBkYXRhIGJpdHM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaWdFbmRpYW4=::ZmFsc2U=::c2V0dGluZ19iaWdFbmRpYW4="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRfbGFyZ2VfUkFNcw==::ZmFsc2U=::RXhwb3J0IExhcmdlIFJBTXM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2VuYWJsZWQ=::ZmFsc2U=::QVNJQyBlbmFibGVk"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3N5bm9wc3lzX3RyYW5zbGF0ZV9vbl9vZmY=::ZmFsc2U=::QVNJQyBTeW5vcHN5cyB0cmFuc2xhdGU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3RoaXJkX3BhcnR5X3N5bnRoZXNpcw==::ZmFsc2U=::QVNJQyB0aGlyZCBwYXJ0eSBzeW50aGVzaXM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2FkZF9zY2FuX21vZGVfaW5wdXQ=::ZmFsc2U=::QVNJQyBhZGQgc2NhbiBtb2RlIGlucHV0"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfZXhwb3J0X2p0YWdfc2lnbmFscw==::ZmFsc2U=::RXhwb3J0IEpUQUcgc2lnbmFscw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hdmFsb25EZWJ1Z1BvcnRQcmVzZW50::ZmFsc2U=::QXZhbG9uIERlYnVnIFBvcnQgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbHdheXNFbmNyeXB0::dHJ1ZQ==::QWx3YXlzIGVuY3J5cHQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVnaXN0ZXJfZmlsZV9wb3I=::ZmFsc2U=::UmVnaXN0ZXIgRmlsZSBQT1I="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW9fcmVnaW9uYmFzZQ==::MA==::QmFzZSBBZGRyZXNz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW9fcmVnaW9uc2l6ZQ==::MA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zdXBwb3J0MzFiaXRkY2FjaGVieXBhc3M=::dHJ1ZQ==::VXNlIG1vc3Qtc2lnbmlmaWNhbnQgYWRkcmVzcyBiaXQgaW4gcHJvY2Vzc29yIHRvIGJ5cGFzcyBkYXRhIGNhY2hl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRyYWNl::dHJ1ZQ==::R2VuZXJhdGUgdHJhY2UgZmlsZSBkdXJpbmcgUlRMIHNpbXVsYXRpb24="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbGxvd19icmVha19pbnN0::ZmFsc2U=::QWxsb3cgQnJlYWsgaW5zdHJ1Y3Rpb25z"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRlc3RFbmRDaGVja2Vy::ZmFsc2U=::QWN0aXZhdGUgdGVzdCBlbmQgY2hlY2tlcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2Nfc2ltX3Rlc3RfcG9ydHM=::ZmFsc2U=::RW5hYmxlIEVDQyBzaW11bGF0aW9uIHRlc3QgcG9ydHM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlb2NpdHJhY2U=::ZmFsc2U=::RGlzYWJsZSBjb21wdHI="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZU1vbml0b3Jz::dHJ1ZQ==::QWN0aXZhdGUgbW9uaXRvcnM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IRExTaW1DYWNoZXNDbGVhcmVk::dHJ1ZQ==::SERMIHNpbXVsYXRpb24gY2FjaGVzIGNsZWFyZWQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IQnJlYWtUZXN0::ZmFsc2U=::QWRkIEhCcmVhayBSZXF1ZXN0IHBvcnQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmVha3NsYXZlb3ZlcmlkZQ==::ZmFsc2U=::TWFudWFsbHkgYXNzaWduIGJyZWFrIHNsYXZl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X3VzZUxpbWl0::ZmFsc2U=::VXNlIExpbWl0IGZvciByZWdpb24gcmFuZ2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNUFU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNTVU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X2F1dG9Bc3NpZ25UbGJQdHJTeg==::dHJ1ZQ==::T3B0aW1pemUgVExCIGVudHJpZXMgYmFzZSBvbiBkZXZpY2UgZmFtaWx5"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1UmVzZXQ=::ZmFsc2U=::SW5jbHVkZSBjcHVfcmVzZXRyZXF1ZXN0IGFuZCBjcHVfcmVzZXR0YWtlbiBzaWduYWxz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::SW5jbHVkZSByZXNldF9yZXEgc2lnbmFsIGZvciBPQ0kgUkFNIGFuZCBNdWx0aS1DeWNsZSBDdXN0b20gSW5zdHJ1Y3Rpb25z"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZW1vdmVSQU1pbml0::ZmFsc2U=::UmVtb3ZlIFJBTSBJbml0aWFsaXphdGlvbg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaGFkb3dSZWdpc3RlclNldHM=::MA==::TnVtYmVyIG9mIHNoYWRvdyByZWdpc3RlciBzZXRzICgwLTYzKQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X251bU9mSW5zdFJlZ2lvbg==::OA==::TnVtYmVyIG9mIGluc3RydWN0aW9uIHJlZ2lvbnM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X251bU9mRGF0YVJlZ2lvbg==::OA==::TnVtYmVyIG9mIGRhdGEgcmVnaW9ucw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNPZmZzZXQ=::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9yIG9mZnNldA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRPZmZzZXQ=::MA==::UmVzZXQgdmVjdG9yIG9mZnNldA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uT2Zmc2V0::Mjg4::RXhjZXB0aW9uIHZlY3RvciBvZmZzZXQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1SUQ=::MA==::Q1BVSUQgY29udHJvbCByZWdpc3RlciB2YWx1ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtPZmZzZXQ=::MzI=::QnJlYWsgdmVjdG9yIG9mZnNldA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRTbGF2ZQ==::ZXh0X2ZsYXNoLmF2bF9tZW0=::UmVzZXQgdmVjdG9yIG1lbW9yeQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uU2xhdmU=::ZGRyM19yYW0uYXZs::RXhjZXB0aW9uIHZlY3RvciBtZW1vcnk="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZQ==::Y3B1Lmp0YWdfZGVidWdfbW9kdWxl::QnJlYWsgdmVjdG9yIG1lbW9yeQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pbnRlcnJ1cHRDb250cm9sbGVyVHlwZQ==::SW50ZXJuYWw=::SW50ZXJydXB0IGNvbnRyb2xsZXI="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmFuY2hQcmVkaWN0aW9uVHlwZQ==::RHluYW1pYw==::QnJhbmNoIHByZWRpY3Rpb24gdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaHRQdHJTeg==::OA==::TnVtYmVyIG9mIGVudHJpZXMgKDItYml0cyB3aWRlKQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3B1QXJjaFJldg==::MQ==::QXJjaGl0ZWN0dXJlIFJldmlzaW9u"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw=::ZmFsc2U=::VXNlIERTUCBCbG9jayBmb3IgU2hpZnRlciBhbmQgTXVsdGlwbGllcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2hpZnRlclR5cGU=::ZmFzdF9sZV9zaGlmdA==::U2hpZnRlcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllclR5cGU=::bXVsX2Zhc3QzMg==::TXVsdGlwbGllcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGl2aWRlclR5cGU=::bm9fZGl2::RGl2aWRlcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X21pbkluc3RSZWdpb25TaXpl::MTI=::TWluaW11bSBpbnN0cnVjdGlvbiByZWdpb24gc2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB1X21pbkRhdGFSZWdpb25TaXpl::MTI=::TWluaW11bSBkYXRhIHJlZ2lvbiBzaXpl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3VpdGxiTnVtRW50cmllcw==::NA==::TWljcm8gSVRMQiBlbnRyaWVz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3VkdGxiTnVtRW50cmllcw==::Ng==::TWljcm8gRFRMQiBlbnRyaWVz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3RsYlB0clN6::Nw==::VExCIGVudHJpZXM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3RsYk51bVdheXM=::MTY=::VExCIFNldC1Bc3NvY2lhdGl2aXR5"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3Byb2Nlc3NJRE51bUJpdHM=::OA==::UHJvY2VzcyBJRCAoUElEKSBiaXRz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW1wbA==::RmFzdA==::TmlvcyBJSSBDb3Jl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3NpemU=::MjA0OA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZmFfY2FjaGVfbGluZQ==::Mg==::TnVtYmVyIG9mIExpbmVz"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZmFfY2FjaGVfbGluZXNpemU=::MA==::TGluZSBTaXpl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX251bVRDSU0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBpbnN0cnVjdGlvbiBtYXN0ZXIgcG9ydHM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aWNhY2hlX2J1cnN0VHlwZQ==::Tm9uZQ==::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGluc3RydWN0aW9uX21hc3Rlcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0cw==::ZmFsc2U=::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGRhdGFfbWFzdGVy"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3ZpY3RpbV9idWZfaW1wbA==::cmFt::VmljdGltIGJ1ZmZlciBpbXBsZW1lbnRhdGlvbg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemU=::MjA0OA==::U2l6ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX251bVRDRE0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBkYXRhIG1hc3RlciBwb3J0cw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnR2ZWN0b3Jz::ZmFsc2U=::RXhwb3J0IFZlY3RvcnM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ191c2VkZXNpZ253YXJl::ZmFsc2U=::VXNlIERlc2lnbndhcmUgQ29tcG9uZW50cw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2NfcHJlc2VudA==::ZmFsc2U=::RUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pY19lY2NfcHJlc2VudA==::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gQ2FjaGUgRUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZl9lY2NfcHJlc2VudA==::dHJ1ZQ==::UmVnaXN0ZXIgRmlsZSBFQ0MgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19tbXVfZWNjX3ByZXNlbnQ=::dHJ1ZQ==::TU1VIEVDQyBQcmVzZW50"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kY19lY2NfcHJlc2VudA==::ZmFsc2U=::RGF0YSBDYWNoZSBFQ0MgUHJlc2VudA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pdGNtX2VjY19wcmVzZW50::ZmFsc2U=::SW5zdHJ1Y3Rpb24gVENNIEVDQyBQcmVzZW50"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kdGNtX2VjY19wcmVzZW50::ZmFsc2U=::RGF0YSBUQ00gRUNDIFByZXNlbnQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVnZmlsZV9yYW1CbG9ja1R5cGU=::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUluaXQ=::ZmFsc2U=::SW5pdGlhbGl6ZWQgT0NJIFJBTQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::TU1VIFJBTSBibG9jayB0eXBl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Ymh0X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::QkhUIFJBTSBCbG9jayBUeXBl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2R4X2VuYWJsZWQ=::ZmFsc2U=::Q0RYIChDb2RlIERlbnNpdHkgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bXB4X2VuYWJsZWQ=::ZmFsc2U=::TVBYIChNdWx0aS1Qcm9jZXNzb3IgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dG1yX2VuYWJsZWQ=::ZmFsc2U=::dG1yX2VuYWJsZWQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZW5hYmxlZA==::dHJ1ZQ==::SW5jbHVkZSBKVEFHIERlYnVn"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJpZ2dlckFybWluZw==::dHJ1ZQ==::VHJpZ2dlciBBcm1pbmc="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGVidWdSZXFTaWduYWxz::ZmFsc2U=::SW5jbHVkZSBkZWJ1Z3JlcSBhbmQgZGVidWdhY2sgU2lnbmFscw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfYXNzaWduSnRhZ0luc3RhbmNlSUQ=::ZmFsc2U=::QXNzaWduIEpUQUcgSW5zdGFuY2UgSUQgZm9yIGRlYnVnIGNvcmUgbWFudWFsbHk="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfanRhZ0luc3RhbmNlSUQ=::MA==::SlRBRyBJbnN0YW5jZSBJRCB2YWx1ZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfT0NJT25jaGlwVHJhY2U=::XzEyOA==::T25jaGlwIFRyYWNlIEZyYW1lIFNpemU="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfaHdicmVha3BvaW50::Mg==::SGFyZHdhcmUgQnJlYWtwb2ludHM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyaWdnZXI=::MA==::RGF0YSBUcmlnZ2Vycw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJhY2VUeXBl::bm9uZQ==::VHJhY2UgVHlwZXM="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJhY2VTdG9yYWdl::b25jaGlwX3RyYWNl::VHJhY2UgU3RvcmFnZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfdmVyc2lvbg==::MQ==::c2V0dGluZ19vY2lfdmVyc2lvbg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ=::ZmFsc2U=::c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWFzdGVyX2FkZHJfbWFw::ZmFsc2U=::bWFzdGVyX2FkZHJfbWFw"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA==::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA==::MA==::Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ==::MA==::ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfdG9w::MA==::ZGF0YV9tYXN0ZXJfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3RvcA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ==::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfdG9w::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfdG9w"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl::MA==::ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl90b3A=::MA==::ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl90b3A="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRBYnNvbHV0ZUFkZHI=::MzM1NTQ0MzIw::UmVzZXQgdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uQWJzb2x1dGVBZGRy::MTM0MjE4MDE2::RXhjZXB0aW9uIHZlY3Rvcg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtBYnNvbHV0ZUFkZHI=::NDA2ODU3NzYw::QnJlYWsgdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNBYnNBZGRy::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9y"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0c19kZXJpdmVk::ZmFsc2U=::ZGNhY2hlX2J1cnN0c19kZXJpdmVk"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemVfZGVyaXZlZA==::MjA0OA==::ZGNhY2hlX3NpemVfZGVyaXZlZA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZV9kZXJpdmVk::Y3B1LmRlYnVnX21lbV9zbGF2ZQ==::YnJlYWtTbGF2ZV9kZXJpdmVk"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ=::MzI=::ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ==::dHJ1ZQ==::c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29u::InN5bnRoZXNpcyB0cmFuc2xhdGVfb24i::dHJhbnNsYXRlX29u"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29mZg==::InN5bnRoZXNpcyB0cmFuc2xhdGVfb2ZmIg==::dHJhbnNsYXRlX29mZg=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfb25jaGlwdHJhY2U=::ZmFsc2U=::ZGVidWdfb25jaGlwdHJhY2U="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfb2ZmY2hpcHRyYWNl::ZmFsc2U=::ZGVidWdfb2ZmY2hpcHRyYWNl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfaW5zdHRyYWNl::ZmFsc2U=::ZGVidWdfaW5zdHRyYWNl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyYWNl::ZmFsc2U=::ZGVidWdfZGF0YXRyYWNl"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdEFkZHJXaWR0aA==::Mjk=::aW5zdEFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZmFBZGRyV2lkdGg=::MQ==::ZmFBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YUFkZHJXaWR0aA==::Mjk=::ZGF0YUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgdHlwZT0nYWx0ZXJhX21lbV9pZl9kZHIzX2VtaWYuYXZsJyAvPjxzbGF2ZSBuYW1lPSdleHRfZmxhc2guYXZsX21lbScgc3RhcnQ9JzB4MTQwMDAwMDAnIGVuZD0nMHgxODAwMDAwMCcgdHlwZT0nYWx0ZXJhX2dlbmVyaWNfcXVhZF9zcGlfY29udHJvbGxlci5hdmxfbWVtJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfZmxhc2guZGF0YScgc3RhcnQ9JzB4MTgyMDAwMDAnIGVuZD0nMHgxODM2MDAwMCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5kYXRhJyAvPjxzbGF2ZSBuYW1lPSdjcHUuZGVidWdfbWVtX3NsYXZlJyBzdGFydD0nMHgxODQwMjgwMCcgZW5kPScweDE4NDAzMDAwJyB0eXBlPSdhbHRlcmFfbmlvczJfZ2VuMi5kZWJ1Z19tZW1fc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::aW5zdFNsYXZlTWFwUGFyYW0="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdkZHIzX3JhbS5hdmwnIHN0YXJ0PScweDgwMDAwMDAnIGVuZD0nMHgxMDAwMDAwMCcgdHlwZT0nYWx0ZXJhX21lbV9pZl9kZHIzX2VtaWYuYXZsJyAvPjxzbGF2ZSBuYW1lPSdleHRfZmxhc2guYXZsX21lbScgc3RhcnQ9JzB4MTQwMDAwMDAnIGVuZD0nMHgxODAwMDAwMCcgdHlwZT0nYWx0ZXJhX2dlbmVyaWNfcXVhZF9zcGlfY29udHJvbGxlci5hdmxfbWVtJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfZmxhc2guZGF0YScgc3RhcnQ9JzB4MTgyMDAwMDAnIGVuZD0nMHgxODM2MDAwMCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5kYXRhJyAvPjxzbGF2ZSBuYW1lPSdkZXNjcmlwdG9yX21lbW9yeS5zMScgc3RhcnQ9JzB4MTg0MDAwMDAnIGVuZD0nMHgxODQwMjAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MTg0MDI4MDAnIGVuZD0nMHgxODQwMzAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdldGhfdHNlLmNvbnRyb2xfcG9ydCcgc3RhcnQ9JzB4MTg0MDMwMDAnIGVuZD0nMHgxODQwMzQwMCcgdHlwZT0nYWx0ZXJhX2V0aF90c2UuY29udHJvbF9wb3J0JyAvPjxzbGF2ZSBuYW1lPSdjYWxpYnJhdGlvbl9yYW0uczEnIHN0YXJ0PScweDE4NDAzNDAwJyBlbmQ9JzB4MTg0MDM2ODAnIHR5cGU9J2FsdGVyYV9hdmFsb25fb25jaGlwX21lbW9yeTIuczEnIC8+PHNsYXZlIG5hbWU9J2ZyYW1lX3RpbWVyLnMxJyBzdGFydD0nMHgxODQwM0MwMCcgZW5kPScweDE4NDAzQzIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdkZWJ1Z191YXJ0LnMxJyBzdGFydD0nMHgxODQwM0MyMCcgZW5kPScweDE4NDAzQzQwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3VhcnQuczEnIC8+PHNsYXZlIG5hbWU9J291dHB1dF9waW8uczEnIHN0YXJ0PScweDE4NDAzQzQwJyBlbmQ9JzB4MTg0MDNDNjAnIHR5cGU9J2FsdGVyYV9hdmFsb25fcGlvLnMxJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgxODQwM0M2MCcgZW5kPScweDE4NDAzQzgwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdtc2dkbWFfcngucHJlZmV0Y2hlcl9jc3InIHN0YXJ0PScweDE4NDAzQzgwJyBlbmQ9JzB4MTg0MDNDQTAnIHR5cGU9J2FsdGVyYV9tc2dkbWEucHJlZmV0Y2hlcl9jc3InIC8+PHNsYXZlIG5hbWU9J21zZ2RtYV90eC5wcmVmZXRjaGVyX2Nzcicgc3RhcnQ9JzB4MTg0MDNDQTAnIGVuZD0nMHgxODQwM0NDMCcgdHlwZT0nYWx0ZXJhX21zZ2RtYS5wcmVmZXRjaGVyX2NzcicgLz48c2xhdmUgbmFtZT0ndWRwX2dlbmVyYXRvci5jc3InIHN0YXJ0PScweDE4NDAzQ0MwJyBlbmQ9JzB4MTg0MDNDRTAnIHR5cGU9J3VkcF9nZW5lcmF0b3IuY3NyJyAvPjxzbGF2ZSBuYW1lPSdtc2dkbWFfcnguY3NyJyBzdGFydD0nMHgxODQwM0NFMCcgZW5kPScweDE4NDAzRDAwJyB0eXBlPSdhbHRlcmFfbXNnZG1hLmNzcicgLz48c2xhdmUgbmFtZT0nbXNnZG1hX3R4LmNzcicgc3RhcnQ9JzB4MTg0MDNEMDAnIGVuZD0nMHgxODQwM0QyMCcgdHlwZT0nYWx0ZXJhX21zZ2RtYS5jc3InIC8+PHNsYXZlIG5hbWU9J2V4dF9mbGFzaC5hdmxfY3NyJyBzdGFydD0nMHgxODQwM0QyMCcgZW5kPScweDE4NDAzRDQwJyB0eXBlPSdhbHRlcmFfZ2VuZXJpY19xdWFkX3NwaV9jb250cm9sbGVyLmF2bF9jc3InIC8+PHNsYXZlIG5hbWU9J2J1dHRvbl9waW8uczEnIHN0YXJ0PScweDE4NDAzRDQwJyBlbmQ9JzB4MTg0MDNENTAnIHR5cGU9J2FsdGVyYV9hdmFsb25fcGlvLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW5zb3JfaW50ZXJmYWNlLmNzcicgc3RhcnQ9JzB4MTg0MDNENTAnIGVuZD0nMHgxODQwM0Q2MCcgdHlwZT0nc2Vuc29yX3JlY29uLmNzcicgLz48c2xhdmUgbmFtZT0nb25jaGlwX2ZsYXNoLmNzcicgc3RhcnQ9JzB4MTg0MDNENjAnIGVuZD0nMHgxODQwM0Q2OCcgdHlwZT0nYWx0ZXJhX29uY2hpcF9mbGFzaC5jc3InIC8+PHNsYXZlIG5hbWU9J3N5c2lkLmNvbnRyb2xfc2xhdmUnIHN0YXJ0PScweDE4NDAzRDY4JyBlbmQ9JzB4MTg0MDNENzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fc3lzaWRfcXN5cy5jb250cm9sX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::TUFYIDEw::ZGV2aWNlRmFtaWx5TmFtZQ=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::NjE=::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8="
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfY2hhbm5lbF9hZGFwdGVyXzA="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIENoYW5uZWwgQWRhcHRlcg=="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MQ==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MQ==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MQ==::TWF4IENoYW5uZWw="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::WUVT::SW5jbHVkZSBFbXB0eSBTaWduYWw="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::NA==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfY2FsaWJyYXRpb25fcmFt"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "YWxsb3dJblN5c3RlbU1lbW9yeUNvbnRlbnRFZGl0b3I=::ZmFsc2U=::RW5hYmxlIEluLVN5c3RlbSBNZW1vcnkgQ29udGVudCBFZGl0b3IgZmVhdHVyZQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "YmxvY2tUeXBl::QVVUTw==::QmxvY2sgdHlwZQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRo::MTY=::U2xhdmUgUzEgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRoMg==::MTY=::U2xhdmUgUzIgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZHVhbFBvcnQ=::dHJ1ZQ==::RHVhbC1wb3J0IGFjY2Vzcw=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZW5hYmxlRGlmZldpZHRo::ZmFsc2U=::RW5hYmxlIGRpZmZlcmVudCB3aWR0aCBmb3IgRHVhbC1wb3J0IGFjY2Vzcw=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg=::ZmFsc2U=::ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "aW5pdE1lbUNvbnRlbnQ=::ZmFsc2U=::SW5pdGlhbGl6ZSBtZW1vcnkgY29udGVudA=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "bWVtb3J5U2l6ZQ==::NjQw::VG90YWwgbWVtb3J5IHNpemU="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVhZER1cmluZ1dyaXRlTW9kZQ==::RE9OVF9DQVJF::UmVhZCBEdXJpbmcgV3JpdGUgTW9kZQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltQWxsb3dNUkFNQ29udGVudHNGaWxl::ZmFsc2U=::QWxsb3cgTVJBTSBjb250ZW50cyBmaWxlIGZvciBzaW11bGF0aW9u"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltTWVtSW5pdE9ubHlGaWxlbmFtZQ==::MA==::U2ltdWxhdGlvbiBtZW1pbml0IG9ubHkgaGFzIGZpbGVuYW1l"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2luZ2xlQ2xvY2tPcGVyYXRpb24=::ZmFsc2U=::U2luZ2xlIGNsb2NrIG9wZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg==::ZmFsc2U=::ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2xhdmUxTGF0ZW5jeQ==::MQ==::U2xhdmUgczEgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2xhdmUyTGF0ZW5jeQ==::MQ==::U2xhdmUgczIgTGF0ZW5jeQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "d3JpdGFibGU=::dHJ1ZQ==::VHlwZQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZWNjX2VuYWJsZWQ=::ZmFsc2U=::RXh0ZW5kIHRoZSBkYXRhIHdpZHRoIHRvIHN1cHBvcnQgRUNDIGJpdHM="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::ZmFsc2U=::UmVzZXQgUmVxdWVzdA=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU=::cV9zeXNfY2FsaWJyYXRpb25fcmFt::YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::TUFYIDEw::ZGV2aWNlRmFtaWx5"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXM=::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXM="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aA==::OQ==::U2xhdmUgMSBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aDI=::OQ==::U2xhdmUgMiBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aA==::MTY=::U2xhdmUgMSBkYXRhIHdpZHRo"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aDI=::MTY=::U2xhdmUgMiBkYXRhIHdpZHRo"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU=::QXV0b21hdGlj::ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pc19oYXJkY29weQ==::ZmFsc2U=::ZGVyaXZlZF9pc19oYXJkY29weQ=="
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ==::cV9zeXNfY2FsaWJyYXRpb25fcmFtLmhleA==::ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ=="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYnV0dG9uX3Bpbw=="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2FwdHVyZUVkZ2U=::ZmFsc2U=::U3luY2hyb25vdXNseSBjYXB0dXJl"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGlyZWN0aW9u::SW5wdXQ=::RGlyZWN0aW9u"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "Z2VuZXJhdGVJUlE=::ZmFsc2U=::R2VuZXJhdGUgSVJR"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "c2ltRG9UZXN0QmVuY2hXaXJpbmc=::ZmFsc2U=::SGFyZHdpcmUgUElPIGlucHV0cyBpbiB0ZXN0IGJlbmNo"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "d2lkdGg=::OQ==::V2lkdGggKDEtMzIgYml0cyk="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NTAwMDAwMDA=::Y2xvY2tSYXRl"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfdHJp::ZmFsc2U=::ZGVyaXZlZF9oYXNfdHJp"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfb3V0::ZmFsc2U=::ZGVyaXZlZF9oYXNfb3V0"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaW4=::dHJ1ZQ==::ZGVyaXZlZF9oYXNfaW4="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw==::ZmFsc2U=::ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw=="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9jYXB0dXJl::ZmFsc2U=::ZGVyaXZlZF9jYXB0dXJl"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lZGdlX3R5cGU=::Tk9ORQ==::ZGVyaXZlZF9lZGdlX3R5cGU="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pcnFfdHlwZQ==::Tk9ORQ==::ZGVyaXZlZF9pcnFfdHlwZQ=="
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaXJx::ZmFsc2U=::ZGVyaXZlZF9oYXNfaXJx"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_NAME "cV9zeXNfYWx0cGxsX3NoaWZ0"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_DISPLAY_NAME "QUxUUExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLWNvbXBhdGlibGUgSW50ZWwgUExMIG1vZHVsZS4gRm9yIFN0cmF0aXggViBhbmQgbmV3ZXIgZmFtaWxpZXMsIHVzZSBJbnRlbCBGUEdBIFBMTCBJUA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NVU1RPTV9FTEFCT1JBVElPTg==::YWx0cGxsX2F2YWxvbl9lbGFib3JhdGlvbg==::SElEREVOX0NVU1RPTV9FTEFCT1JBVElPTg=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NVU1RPTV9QT1NUX0VESVQ=::YWx0cGxsX2F2YWxvbl9wb3N0X2VkaXQ=::SElEREVOX0NVU1RPTV9QT1NUX0VESVQ="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5URU5ERURfREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::SU5URU5ERURfREVWSUNFX0ZBTUlMWQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "V0lEVEhfQ0xPQ0s=::NQ==::V0lEVEhfQ0xPQ0s="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SU5DTEswX0lOUFVUX0ZSRVFVRU5DWQ==::MjAwMDA=::SU5DTEswX0lOUFVUX0ZSRVFVRU5DWQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "T1BFUkFUSU9OX01PREU=::Tk9STUFM::T1BFUkFUSU9OX01PREU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UExMX1RZUEU=::QVVUTw==::UExMX1RZUEU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q09NUEVOU0FURV9DTE9DSw==::Q0xLMA==::Q09NUEVOU0FURV9DTE9DSw=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "QkFORFdJRFRIX1RZUEU=::QVVUTw==::QkFORFdJRFRIX1RZUEU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9NVUxUSVBMWV9CWQ==::NQ==::Q0xLMF9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9NVUxUSVBMWV9CWQ==::MQ==::Q0xLMV9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9NVUxUSVBMWV9CWQ==::MQ==::Q0xLMl9NVUxUSVBMWV9CWQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9ESVZJREVfQlk=::MQ==::Q0xLMF9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9ESVZJREVfQlk=::Mg==::Q0xLMV9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9ESVZJREVfQlk=::MjA=::Q0xLMl9ESVZJREVfQlk="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9QSEFTRV9TSElGVA==::MA==::Q0xLMF9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9QSEFTRV9TSElGVA==::MTUwMDA=::Q0xLMV9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9QSEFTRV9TSElGVA==::MA==::Q0xLMl9QSEFTRV9TSElGVA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMF9EVVRZX0NZQ0xF::NTA=::Q0xLMF9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMV9EVVRZX0NZQ0xF::NTA=::Q0xLMV9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "Q0xLMl9EVVRZX0NZQ0xF::NTA=::Q0xLMl9EVVRZX0NZQ0xF"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEw::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEw"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEx::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEx"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEy::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEy"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmEz::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmEz"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmE0::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmE0"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGtlbmE1::UE9SVF9VTlVTRUQ=::UE9SVF9jbGtlbmE1"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsw::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsw"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsx::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsx"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsy::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsy"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9leHRjbGsz::UE9SVF9VTlVTRUQ=::UE9SVF9leHRjbGsz"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtCQUQw::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtCQUQw"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtCQUQx::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtCQUQx"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsw::UE9SVF9VU0VE::UE9SVF9jbGsw"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsx::UE9SVF9VTlVTRUQ=::UE9SVF9jbGsx"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsy::UE9SVF9VTlVTRUQ=::UE9SVF9jbGsy"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGsz::UE9SVF9VTlVTRUQ=::UE9SVF9jbGsz"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGs0::UE9SVF9VTlVTRUQ=::UE9SVF9jbGs0"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9jbGs1::UE9SVF9VTlVTRUQ=::UE9SVF9jbGs1"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOREFUQQ==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOREFUQQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOREFUQU9VVA==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOREFUQU9VVA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FORE9ORQ==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FORE9ORQ=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9BQ1RJVkVDTE9DSw==::UE9SVF9VTlVTRUQ=::UE9SVF9BQ1RJVkVDTE9DSw=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtMT1NT::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtMT1NT"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTkNMSzE=::UE9SVF9VTlVTRUQ=::UE9SVF9JTkNMSzE="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9JTkNMSzA=::UE9SVF9VU0VE::UE9SVF9JTkNMSzA="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9GQklO::UE9SVF9VTlVTRUQ=::UE9SVF9GQklO"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QTExFTkE=::UE9SVF9VTlVTRUQ=::UE9SVF9QTExFTkE="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DTEtTV0lUQ0g=::UE9SVF9VTlVTRUQ=::UE9SVF9DTEtTV0lUQ0g="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9BUkVTRVQ=::UE9SVF9VU0VE::UE9SVF9BUkVTRVQ="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QRkRFTkE=::UE9SVF9VTlVTRUQ=::UE9SVF9QRkRFTkE="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQ0xL::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQ0xL"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQUNMUg==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQUNMUg=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOUkVBRA==::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOUkVBRA=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOV1JJVEU=::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOV1JJVEU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9MT0NLRUQ=::UE9SVF9VU0VE::UE9SVF9MT0NLRUQ="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9DT05GSUdVUERBVEU=::UE9SVF9VTlVTRUQ=::UE9SVF9DT05GSUdVUERBVEU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRURPTkU=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRURPTkU="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRVNURVA=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRVNURVA="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRVVQRE9XTg==::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRVVQRE9XTg=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9TQ0FOQ0xLRU5B::UE9SVF9VTlVTRUQ=::UE9SVF9TQ0FOQ0xLRU5B"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "UE9SVF9QSEFTRUNPVU5URVJTRUxFQ1Q=::UE9SVF9VTlVTRUQ=::UE9SVF9QSEFTRUNPVU5URVJTRUxFQ1Q="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVZBTE9OX1VTRV9TRVBBUkFURV9TWVNDTEs=::Tk8=::QVZBTE9OX1VTRV9TRVBBUkFURV9TWVNDTEs="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0NPTlNUQU5UUw==::Q1QjQ0xLMl9ESVZJREVfQlkgMjAgQ1QjUE9SVF9jbGs1IFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrNCBQT1JUX1VOVVNFRCBDVCNQT1JUX2NsazMgUE9SVF9VTlVTRUQgQ1QjUE9SVF9jbGsyIFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrMSBQT1JUX1VOVVNFRCBDVCNQT1JUX2NsazAgUE9SVF9VU0VEIENUI0NMSzBfTVVMVElQTFlfQlkgNSBDVCNQT1JUX1NDQU5XUklURSBQT1JUX1VOVVNFRCBDVCNQT1JUX1NDQU5BQ0xSIFBPUlRfVU5VU0VEIENUI1BPUlRfUEZERU5BIFBPUlRfVU5VU0VEIENUI1BPUlRfUExMRU5BIFBPUlRfVU5VU0VEIENUI1BPUlRfU0NBTkRBVEEgUE9SVF9VTlVTRUQgQ1QjUE9SVF9TQ0FOQ0xLRU5BIFBPUlRfVU5VU0VEIENUI1dJRFRIX0NMT0NLIDUgQ1QjUE9SVF9TQ0FOREFUQU9VVCBQT1JUX1VOVVNFRCBDVCNMUE1fVFlQRSBhbHRwbGwgQ1QjUExMX1RZUEUgQVVUTyBDVCNDTEswX1BIQVNFX1NISUZUIDAgQ1QjQ0xLMV9EVVRZX0NZQ0xFIDUwIENUI1BPUlRfUEhBU0VET05FIFBPUlRfVU5VU0VEIENUI09QRVJBVElPTl9NT0RFIE5PUk1BTCBDVCNQT1JUX0NPTkZJR1VQREFURSBQT1JUX1VOVVNFRCBDVCNDTEsxX01VTFRJUExZX0JZIDEgQ1QjQ09NUEVOU0FURV9DTE9DSyBDTEswIENUI1BPUlRfQ0xLU1dJVENIIFBPUlRfVU5VU0VEIENUI0lOQ0xLMF9JTlBVVF9GUkVRVUVOQ1kgMjAwMDAgQ1QjUE9SVF9TQ0FORE9ORSBQT1JUX1VOVVNFRCBDVCNQT1JUX0NMS0xPU1MgUE9SVF9VTlVTRUQgQ1QjUE9SVF9JTkNMSzEgUE9SVF9VTlVTRUQgQ1QjQVZBTE9OX1VTRV9TRVBBUkFURV9TWVNDTEsgTk8gQ1QjUE9SVF9JTkNMSzAgUE9SVF9VU0VEIENUI1BPUlRfY2xrZW5hNSBQT1JUX1VOVVNFRCBDVCNQT1JUX2Nsa2VuYTQgUE9SVF9VTlVTRUQgQ1QjUE9SVF9jbGtlbmEzIFBPUlRfVU5VU0VEIENUI1BPUlRfY2xrZW5hMiBQT1JUX1VOVVNFRCBDVCNQT1JUX2Nsa2VuYTEgUE9SVF9VTlVTRUQgQ1QjUE9SVF9jbGtlbmEwIFBPUlRfVU5VU0VEIENUI0NMSzFfUEhBU0VfU0hJRlQgMTUwMDAgQ1QjUE9SVF9BUkVTRVQgUE9SVF9VU0VEIENUI0JBTkRXSURUSF9UWVBFIEFVVE8gQ1QjQ0xLMl9NVUxUSVBMWV9CWSAxIENUI0lOVEVOREVEX0RFVklDRV9GQU1JTFkge01BWCAxMH0gQ1QjUE9SVF9TQ0FOUkVBRCBQT1JUX1VOVVNFRCBDVCNDTEsyX0RVVFlfQ1lDTEUgNTAgQ1QjUE9SVF9QSEFTRVNURVAgUE9SVF9VTlVTRUQgQ1QjUE9SVF9TQ0FOQ0xLIFBPUlRfVU5VU0VEIENUI1BPUlRfQ0xLQkFEMSBQT1JUX1VOVVNFRCBDVCNQT1JUX0NMS0JBRDAgUE9SVF9VTlVTRUQgQ1QjUE9SVF9GQklOIFBPUlRfVU5VU0VEIENUI1BPUlRfUEhBU0VVUERPV04gUE9SVF9VTlVTRUQgQ1QjUE9SVF9leHRjbGszIFBPUlRfVU5VU0VEIENUI1BPUlRfZXh0Y2xrMiBQT1JUX1VOVVNFRCBDVCNQT1JUX2V4dGNsazEgUE9SVF9VTlVTRUQgQ1QjUE9SVF9QSEFTRUNPVU5URVJTRUxFQ1QgUE9SVF9VTlVTRUQgQ1QjUE9SVF9leHRjbGswIFBPUlRfVU5VU0VEIENUI1BPUlRfQUNUSVZFQ0xPQ0sgUE9SVF9VTlVTRUQgQ1QjQ0xLMl9QSEFTRV9TSElGVCAwIENUI0NMSzBfRFVUWV9DWUNMRSA1MCBDVCNDTEswX0RJVklERV9CWSAxIENUI0NMSzFfRElWSURFX0JZIDIgQ1QjUE9SVF9MT0NLRUQgUE9SVF9VU0VE::SElEREVOX0NPTlNUQU5UUw=="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX1BSSVZBVEVT::UFQjR0xPQ0tFRF9GRUFUVVJFX0VOQUJMRUQgMCBQVCNTUFJFQURfRkVBVFVSRV9FTkFCTEVEIDAgUFQjQkFORFdJRFRIX0ZSRVFfVU5JVCBNSHogUFQjQ1VSX0RFRElDQVRFRF9DTEsgYzAgUFQjSU5DTEswX0ZSRVFfRURJVCA1MC4wMDAgUFQjQkFORFdJRFRIX1BSRVNFVCBMb3cgUFQjUExMX0xWRFNfUExMX0NIRUNLIDAgUFQjQkFORFdJRFRIX1VTRV9QUkVTRVQgMCBQVCNBVkFMT05fVVNFX1NFUEFSQVRFX1NZU0NMSyBOTyBQVCNQTExfRU5IUExMX0NIRUNLIDAgUFQjT1VUUFVUX0ZSRVFfVU5JVDIgTUh6IFBUI09VVFBVVF9GUkVRX1VOSVQxIE1IeiBQVCNPVVRQVVRfRlJFUV9VTklUMCBNSHogUFQjUEhBU0VfUkVDT05GSUdfRkVBVFVSRV9FTkFCTEVEIDEgUFQjQ1JFQVRFX0NMS0JBRF9DSEVDSyAwIFBUI0NMS1NXSVRDSF9DSEVDSyAwIFBUI0lOQ0xLMV9GUkVRX0VESVQgMTAwLjAwMCBQVCNOT1JNQUxfTU9ERV9SQURJTyAxIFBUI1NSQ19TWU5DSF9DT01QX1JBRElPIDAgUFQjUExMX0FSRVNFVF9DSEVDSyAxIFBUI0xPTkdfU0NBTl9SQURJTyAxIFBUI1NDQU5fRkVBVFVSRV9FTkFCTEVEIDEgUFQjVVNFX0NMSzIgMSBQVCNQSEFTRV9SRUNPTkZJR19JTlBVVFNfQ0hFQ0sgMCBQVCNVU0VfQ0xLMSAxIFBUI1VTRV9DTEswIDEgUFQjUFJJTUFSWV9DTEtfQ09NQk8gaW5jbGswIFBUI0JBTkRXSURUSCAxLjAwMCBQVCNHTE9DS0VEX0NPVU5URVJfRURJVF9DSEFOR0VEIDEgUFQjUExMX0ZBU1RQTExfQ0hFQ0sgMCBQVCNTUFJFQURfRlJFUV9VTklUIEtIeiBQVCNQTExfQVVUT1BMTF9DSEVDSyAxIFBUI0xWRFNfUEhBU0VfU0hJRlRfVU5JVDIgZGVnIFBUI0xWRFNfUEhBU0VfU0hJRlRfVU5JVDEgZGVnIFBUI09VVFBVVF9GUkVRX01PREUyIDAgUFQjTFZEU19QSEFTRV9TSElGVF9VTklUMCBkZWcgUFQjT1VUUFVUX0ZSRVFfTU9ERTEgMCBQVCNTV0lUQ0hPVkVSX0ZFQVRVUkVfRU5BQkxFRCAwIFBUI01JR19ERVZJQ0VfU1BFRURfR1JBREUgQW55IFBUI09VVFBVVF9GUkVRX01PREUwIDAgUFQjQkFORFdJRFRIX0ZFQVRVUkVfRU5BQkxFRCAxIFBUI0lOQ0xLMF9GUkVRX1VOSVRfQ09NQk8gTUh6IFBUI1pFUk9fREVMQVlfUkFESU8gMCBQVCNPVVRQVVRfRlJFUTIgMTAwLjAwMDAwMDAwIFBUI09VVFBVVF9GUkVRMSAxMDAuMDAwMDAwMDAgUFQjT1VUUFVUX0ZSRVEwIDEwMC4wMDAwMDAwMCBQVCNTSE9SVF9TQ0FOX1JBRElPIDAgUFQjTFZEU19NT0RFX0RBVEFfUkFURV9ESVJUWSAwIFBUI0NVUl9GQklOX0NMSyBjMCBQVCNQTExfQURWQU5DRURfUEFSQU1fQ0hFQ0sgMCBQVCNDTEtCQURfU1dJVENIT1ZFUl9DSEVDSyAwIFBUI1BIQVNFX1NISUZUX1NURVBfRU5BQkxFRF9DSEVDSyAwIFBUI0RFVklDRV9TUEVFRF9HUkFERSA2IFBUI1BMTF9GQk1JTUlDX0NIRUNLIDAgUFQjTFZEU19NT0RFX0RBVEFfUkFURSB7Tm90IEF2YWlsYWJsZX0gUFQjTE9DS0VEX09VVFBVVF9DSEVDSyAxIFBUI1NQUkVBRF9QRVJDRU5UIDAuNTAwIFBUI1BIQVNFX1NISUZUMiAwLjAwMDAwMDAwIFBUI1BIQVNFX1NISUZUMSAxMzUuMDAwMDAwMDAgUFQjRElWX0ZBQ1RPUjIgMjAgUFQjUEhBU0VfU0hJRlQwIDAuMDAwMDAwMDAgUFQjRElWX0ZBQ1RPUjEgMiBQVCNESVZfRkFDVE9SMCAxIFBUI0NOWF9OT19DT01QRU5TQVRFX1JBRElPIDAgUFQjVVNFX0NMS0VOQTIgMCBQVCNVU0VfQ0xLRU5BMSAwIFBUI1VTRV9DTEtFTkEwIDAgUFQjQ1JFQVRFX0lOQ0xLMV9DSEVDSyAwIFBUI0dMT0NLX0NPVU5URVJfRURJVCAxMDQ4NTc1IFBUI0lOQ0xLMV9GUkVRX1VOSVRfQ09NQk8gTUh6IFBUI0VGRl9PVVRQVVRfRlJFUV9WQUxVRTIgMi41MDAwMDAgUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFMSAyNS4wMDAwMDAgUFQjRUZGX09VVFBVVF9GUkVRX1ZBTFVFMCAyNTAuMDAwMDAwIFBUI1NQUkVBRF9GUkVRIDUwLjAwMCBQVCNVU0VfTUlMX1NQRUVEX0dSQURFIDAgUFQjRVhQTElDSVRfU1dJVENIT1ZFUl9DT1VOVEVSIDAgUFQjU1RJQ0tZX0NMSzIgMSBQVCNTVElDS1lfQ0xLMSAxIFBUI1NUSUNLWV9DTEswIDEgUFQjRVhUX0ZFRURCQUNLX1JBRElPIDAgUFQjTUlSUk9SX0NMSzIgMCBQVCNNSVJST1JfQ0xLMSAwIFBUI1NXSVRDSE9WRVJfQ09VTlRfRURJVCAxIFBUI01JUlJPUl9DTEswIDAgUFQjU0VMRl9SRVNFVF9MT0NLX0xPU1MgMCBQVCNQTExfUEZERU5BX0NIRUNLIDAgUFQjSU5UX0ZFRURCQUNLX19NT0RFX1JBRElPIDEgUFQjSU5DTEsxX0ZSRVFfRURJVF9DSEFOR0VEIDEgUFQjU1lOVEhfV1JBUFBFUl9HRU5fUE9TVEZJWCAwIFBUI0NMS0xPU1NfQ0hFQ0sgMCBQVCNQSEFTRV9TSElGVF9VTklUMiBkZWcgUFQjUEhBU0VfU0hJRlRfVU5JVDEgZGVnIFBUI1BIQVNFX1NISUZUX1VOSVQwIGRlZyBQVCNCQU5EV0lEVEhfVVNFX0FVVE8gMSBQVCNIQVNfTUFOVUFMX1NXSVRDSE9WRVIgMSBQVCNNVUxUX0ZBQ1RPUjIgMSBQVCNNVUxUX0ZBQ1RPUjEgMSBQVCNNVUxUX0ZBQ1RPUjAgNSBQVCNTUFJFQURfVVNFIDAgUFQjR0xPQ0tFRF9NT0RFX0NIRUNLIDAgUFQjRFVUWV9DWUNMRTIgNTAuMDAwMDAwMDAgUFQjU0FDTl9JTlBVVFNfQ0hFQ0sgMCBQVCNEVVRZX0NZQ0xFMSA1MC4wMDAwMDAwMCBQVCNJTlRFTkRFRF9ERVZJQ0VfRkFNSUxZIHtNQVggMTB9IFBUI0RVVFlfQ1lDTEUwIDUwLjAwMDAwMDAwIFBUI1BMTF9UQVJHRVRfSEFSQ09QWV9DSEVDSyAwIFBUI0lOQ0xLMV9GUkVRX1VOSVRfQ0hBTkdFRCAxIFBUI1JFQ09ORklHX0ZJTEUgQUxUUExMMTQyMzgyMzc4MzYwODk1Mi5taWYgUFQjQUNUSVZFQ0xLX0NIRUNLIDA=::SElEREVOX1BSSVZBVEVT"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX1VTRURfUE9SVFM=::VVAjbG9ja2VkIHVzZWQgVVAjYzIgdXNlZCBVUCNjMSB1c2VkIFVQI2MwIHVzZWQgVVAjYXJlc2V0IHVzZWQgVVAjaW5jbGswIHVzZWQ=::SElEREVOX1VTRURfUE9SVFM="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lTX05VTUVSSUM=::SU4jV0lEVEhfQ0xPQ0sgMSBJTiNDTEswX0RVVFlfQ1lDTEUgMSBJTiNDTEsyX0RJVklERV9CWSAxIElOI1BMTF9UQVJHRVRfSEFSQ09QWV9DSEVDSyAxIElOI0NMSzFfTVVMVElQTFlfQlkgMSBJTiNTV0lUQ0hPVkVSX0NPVU5UX0VESVQgMSBJTiNJTkNMSzBfSU5QVVRfRlJFUVVFTkNZIDEgSU4jUExMX0xWRFNfUExMX0NIRUNLIDEgSU4jUExMX0FVVE9QTExfQ0hFQ0sgMSBJTiNQTExfRkFTVFBMTF9DSEVDSyAxIElOI0NMSzFfRFVUWV9DWUNMRSAxIElOI1BMTF9FTkhQTExfQ0hFQ0sgMSBJTiNDTEsyX01VTFRJUExZX0JZIDEgSU4jRElWX0ZBQ1RPUjIgMSBJTiNESVZfRkFDVE9SMSAxIElOI0RJVl9GQUNUT1IwIDEgSU4jTFZEU19NT0RFX0RBVEFfUkFURV9ESVJUWSAxIElOI0dMT0NLX0NPVU5URVJfRURJVCAxIElOI0NMSzJfRFVUWV9DWUNMRSAxIElOI0NMSzBfRElWSURFX0JZIDEgSU4jTVVMVF9GQUNUT1IyIDEgSU4jTVVMVF9GQUNUT1IxIDEgSU4jTVVMVF9GQUNUT1IwIDEgSU4jQ0xLMF9NVUxUSVBMWV9CWSAxIElOI1VTRV9NSUxfU1BFRURfR1JBREUgMSBJTiNDTEsxX0RJVklERV9CWSAx::SElEREVOX0lTX05VTUVSSUM="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX01GX1BPUlRT::TUYjYXJlc2V0IDEgTUYjY2xrIDEgTUYjbG9ja2VkIDEgTUYjaW5jbGsgMQ==::SElEREVOX01GX1BPUlRT"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lGX1BPUlRT::SUYjbG9ja2VkIHtvdXRwdXQgMH0gSUYjcmVzZXQge2lucHV0IDB9IElGI2NsayB7aW5wdXQgMH0gSUYjcmVhZGRhdGEge291dHB1dCAzMn0gSUYjd3JpdGUge2lucHV0IDB9IElGI3BoYXNlZG9uZSB7b3V0cHV0IDB9IElGI2FkZHJlc3Mge2lucHV0IDJ9IElGI2MyIHtvdXRwdXQgMH0gSUYjYzEge291dHB1dCAwfSBJRiNjMCB7b3V0cHV0IDB9IElGI3dyaXRlZGF0YSB7aW5wdXQgMzJ9IElGI3JlYWQge2lucHV0IDB9IElGI2FyZXNldCB7aW5wdXQgMH0=::SElEREVOX0lGX1BPUlRT"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "SElEREVOX0lTX0ZJUlNUX0VESVQ=::MA==::SElEREVOX0lTX0ZJUlNUX0VESVQ="
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_COMPONENT_PARAMETER "QVVUT19JTkNMS19JTlRFUkZBQ0VfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
+
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "q_sys.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_avalon_st_adapter_001.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_avalon_st_adapter.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_irq_clock_crosser.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_irq_mapper.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_handshake_clock_crosser.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_clock_crosser.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_base.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_std_synchronizer_nocut.v"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_handshake_clock_crosser.sdc"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_width_adapter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_address_alignment.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_mux.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_rsp_demux.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_mux.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_cmd_demux.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter_uncmpr.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter_13_1.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter_new.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_incr_burst_converter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_wrap_burst_converter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_default_burst_converter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_stage.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_traffic_limiter.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_reorder_memory.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_028.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_022.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_010.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_009.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_008.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_004.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_002.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router_001.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_1_router.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_mm_interconnect_0.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/udp_generator.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_tx_multiplexer.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_sysid.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_sys_clk_timer.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rms.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/stl2sts.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/calibration.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/algo_top_cl_cali_rms.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_interface.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_rx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_tx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_algo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/bkg_subtraction_pipe.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/cluster_locate.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/data_caled_ram.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/st_splitter16.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_splitter.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/div.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sqrt.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/ram4bkg.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_output_pio.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_onchip_flash_util.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_onchip_flash.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_onchip_flash_avmm_data_controller.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_onchip_flash_avmm_csr_controller.v"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_onchip_flash.sdc"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/altera_onchip_flash_block.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_msgdma_tx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/read_master.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/MM_to_ST_Adapter.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/read_burst_control.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher_read.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher_write_back.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher_interrrupt.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_msgdma_prefetcher_csr.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/dispatcher.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/descriptor_buffers.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/csr_block.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/response_block.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/fifo_with_byteenables.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/read_signal_breakout.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/write_signal_breakout.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_msgdma_rx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/write_master.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/byte_enable_generator.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/ST_to_MM_Adapter.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/write_burst_control.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_frame_timer.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ext_flash.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ext_flash_epcq_controller_instance_name.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_epcq_controller_arb.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_epcq_controller.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/soft_asmiblock.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_eth_tse.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_gpio_lite.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_eth_tse_mac.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_clk_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_crc328checker.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_crc328generator.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_crc32ctl8.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_crc32galois8.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_gmii_io.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_lb_read_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_lb_wrt_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_hashing.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_host_control.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_host_control_small.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mac_control.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_register_map.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_register_map_small.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_counter_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_shared_mac_control.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_shared_register_map.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_counter_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_lfsr_10.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_loopback_ff.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_altshifttaps.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_fifoless_mac_rx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mac_rx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_fifoless_mac_tx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mac_tx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_magic_detection.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mdio.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mdio_clk_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mdio_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_mdio.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mii_rx_if.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_mii_tx_if.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_pipeline_base.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_pipeline_stage.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_dpram_16x32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_dpram_8x32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_dpram_ecc_16x32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_fifoless_retransmit_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_retransmit_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rgmii_in1.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rgmii_in4.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_nf_rgmii_module.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rgmii_module.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rgmii_out1.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rgmii_out4.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_ff.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_min_ff.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_ff_cntrl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_ff_cntrl_32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_ff_cntrl_32_shift16.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_ff_length.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_rx_stat_extract.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_timing_adapter32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_timing_adapter8.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_timing_adapter_fifo32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_timing_adapter_fifo8.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_1geth.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_fifoless_1geth.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_w_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_w_fifo_10_100_1000.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_wo_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_wo_fifo_10_100_1000.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_gen_host.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_min_ff.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff_cntrl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff_cntrl_32.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff_cntrl_32_shift16.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff_length.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_ff_read_cntl.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_tx_stat_extract.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_eth_tse_std_synchronizer.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_eth_tse_std_synchronizer_bundle.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_eth_tse_ptp_std_synchronizer.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_false_path_marker.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_reset_synchronizer.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_clock_crosser.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_13.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_24.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_34.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_opt_1246.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_opt_14_44.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_a_fifo_opt_36_10.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_gray_cnt.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_sdpm_altsyncram.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_altsyncram_dpm_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_bin_cnt.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ph_calculator.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_sdpm_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x10.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x10.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x10_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x14.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x14.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x14_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x2.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x2.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x2_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x23.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x23.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x23_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x36.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x36.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x36_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x40.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x40.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x40_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_dec_x30.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x30.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_enc_x30_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_tse_ecc_status_crosser.v"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_wo_fifo_10_100_1000.ocp"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/altera_tse_top_w_fifo_10_100_1000.ocp"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_eth_tse_mac.sdc"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_enet_pll.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_descriptor_memory.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_debug_uart.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_c0.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_mm_st_converter.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_addr_cmd.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_addr_cmd_wrap.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ddr2_odt_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ddr3_odt_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_odt_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_rdwr_data_tmg.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_arbiter.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_burst_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_cmd_gen.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_csr.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_buffer.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_buffer_manager.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_burst_tracking.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_dataid_manager.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_list.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_rdata_path.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_wdata_path.v"]
+set_global_assignment -library "q_sys" -name MISC_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_define.iv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_decoder.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_encoder.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_axi_st_converter.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_input_if.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_rank_timer.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_sideband.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_tbp.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_timing_param.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_controller.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_ddrx_controller_st_top.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_make_qsys_seq.tcl"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_core.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_di_buffer_wrap.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_datamux.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/sequencer_m10.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_bitcheck.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_mem_if_sequencer_rst.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_data_broadcast.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_write_decoder.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_ram_csr.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_dm_decoder.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_ram.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_di_buffer.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_read_datapath.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/sequencer_pll_mgr.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_data_decoder.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/sequencer_phy_mgr.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_ac_ROM_reg.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_pattern_fifo.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_generic.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_lfsr12.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_inst_ROM_reg.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_jumplogic.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_lfsr72.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_ddr3.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_lfsr36.v"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_AC_ROM.hex"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_s0_inst_ROM.hex"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_m10_ac_ROM.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rw_manager_m10_inst_ROM.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/afi_mux_ddr3_ddrx.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_reset_m10.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_reset_sync.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/max10emif_dcfifo.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_iss_probe.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_flop_mem.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0.sv"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0.ppf"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0.sdc"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_timing.tcl"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_report_timing.tcl"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_report_timing_core.tcl"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_pin_map.tcl"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_pin_assignments.tcl"]
+set_global_assignment -library "q_sys" -name TCL_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_p0_parameters.tcl"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_ddr3_ram_pll0.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_mult_cell.v"]
+set_global_assignment -library "q_sys" -name SDC_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu.sdc"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu.v"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_bht_ram.mif"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_test_bench.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_ic_tag_ram.mif"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_debug_slave_tck.v"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_rf_ram_a.mif"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_rf_ram_b.mif"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_ociram_default_contents.mif"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_dc_tag_ram.mif"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_nios2_gen2_rtl_module.sv"]
+set_global_assignment -library "q_sys" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/altera_nios2_gen2_rtl_module.ocp"]
+set_global_assignment -library "q_sys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_channel_adapter_0.sv"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_calibration_ram.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_button_pio.v"]
+set_global_assignment -library "q_sys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/q_sys_altpll_shift.v"]
+
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_TOOL_NAME "altera_reset_controller"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_reset_controller" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_st_adapter"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_TOOL_NAME "timing_adapter"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_avalon_st_adapter_001_timing_adapter_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_st_adapter"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_avalon_st_adapter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_TOOL_NAME "altera_irq_clock_crosser"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_irq_clock_crosser" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_TOOL_NAME "altera_irq_mapper"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_irq_mapper" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_TOOL_NAME "altera_mm_interconnect"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_st_adapter"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_st_adapter"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_NAME "error_adapter"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_st_handshake_clock_crosser"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_avalon_st_handshake_clock_crosser" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_width_adapter"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_width_adapter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_002" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_mux" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_014" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_010" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_002" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_rsp_demux" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_014" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_002" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_multiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_mux" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_002" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_cmd_demux" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_burst_adapter"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_burst_adapter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_traffic_limiter"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_traffic_limiter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_028" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_022" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_010" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_009" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_008" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_004" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_002" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router_001" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_router"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_1_router" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_avalon_sc_fifo" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_slave_agent"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_slave_agent" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_master_agent"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_master_agent" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_slave_translator"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_slave_translator" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_TOOL_NAME "altera_merlin_master_translator"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_merlin_master_translator" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_TOOL_NAME "altera_mm_interconnect"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_mm_interconnect_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_TOOL_NAME "multiplexer"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_tx_multiplexer" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_sysid_qsys"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_sysid" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_timer"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_sys_clk_timer" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_pio"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_output_pio" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_TOOL_NAME "altera_onchip_flash"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_onchip_flash" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_TOOL_NAME "altera_msgdma"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_msgdma_tx" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_TOOL_NAME "dma_read_master"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "read_master" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_TOOL_NAME "altera_msgdma_prefetcher"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_msgdma_prefetcher" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_TOOL_NAME "modular_sgdma_dispatcher"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "dispatcher" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_TOOL_NAME "altera_msgdma"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_msgdma_rx" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_TOOL_NAME "dma_write_master"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "write_master" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_timer"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_frame_timer" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_TOOL_NAME "altera_generic_quad_spi_controller"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ext_flash" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_TOOL_NAME "altera_generic_quad_spi_controller"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ext_flash_epcq_controller_instance_name" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_TOOL_NAME "altera_epcq_controller_core"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_epcq_controller_arb" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_NAME "altera_generic_quad_spi_controller"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_NAME "altera_asmi_parallel"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_TOOL_NAME "altera_generic_quad_spi_controller"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ext_flash_soft_asmiblock_instance_name" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_TOOL_NAME "soft_asmiblock"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "soft_asmiblock" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_TOOL_NAME "altera_eth_tse"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_eth_tse" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_gpio_lite" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_TOOL_NAME "altera_eth_tse_mac"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_eth_tse_mac" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_TOOL_NAME "altpll"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_enet_pll" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_onchip_memory2"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_descriptor_memory" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_uart"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_debug_uart" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_ddr3_emif"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ddr3_ram" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_nextgen_ddr3_controller"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ddr3_ram_c0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_TOOL_NAME "alt_mem_ddrx_mm_st_converter"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "alt_mem_ddrx_mm_st_converter" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_nextgen_ddr3_controller_core"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "alt_mem_if_nextgen_ddr3_controller_core" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_ddr3_qseq"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ddr3_ram_s0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_ddr3_afi_mux"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "afi_mux_ddr3_ddrx" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_ddr3_phy_core"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ddr3_ram_p0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_TOOL_NAME "altera_mem_if_ddr3_pll"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_ddr3_ram_pll0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_TOOL_NAME "altera_nios2_gen2"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_cpu" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_TOOL_NAME "altera_nios2_gen2_unit"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_cpu_cpu" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_TOOL_NAME "channel_adapter"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_channel_adapter_0" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_onchip_memory2"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_calibration_ram" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_TOOL_NAME "altera_avalon_pio"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_button_pio" -library "q_sys" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_TOOL_NAME "altpll"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "q_sys_altpll_shift" -library "q_sys" -name IP_TOOL_ENV "Qsys"
diff --git a/FPGA_firmware/q_sys/synthesis/q_sys.regmap b/FPGA_firmware/q_sys/synthesis/q_sys.regmap
new file mode 100644
index 0000000..2d750e9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/q_sys.regmap
@@ -0,0 +1,769 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+<name>q_sys</name>
+<peripherals>
+<peripheral>
+      <name>q_sys_sysid_control_slave_altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>     
+         <name>ID</name>  
+         <displayName>System ID</displayName>
+            <description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
+         <addressOffset>0x0</addressOffset>
+         <size>32</size>
+         <access>read-only</access>
+         <resetValue>${sysid_id_value}</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>id</name>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-only</access>
+        </field>
+       </fields>
+     </register> 
+        <register>
+         <name>TIMESTAMP</name>  
+         <displayName>Time stamp</displayName>
+         <description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
+         <addressOffset>0x4</addressOffset>
+         <size>32</size>
+         <access>read-only</access>
+         <resetValue>${sysid_timestamp_value}</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>timestamp</name>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-only</access>
+        </field>
+       </fields>
+     </register>            
+    </registers>
+   </peripheral>
+  <peripheral>
+      <name>q_sys_sys_clk_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>16</size>
+        <usage>registers</usage>
+      </addressBlock>
+       <registers>
+         <register>     
+          <name>status</name>  
+          <displayName>Status</displayName>
+          <description>The status register has two defined bits. TO (timeout), RUN</description>
+          <addressOffset>0x0</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffff</resetMask>
+          <fields>
+            <field><name>TO</name>
+            <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
+             <bitOffset>0x0</bitOffset>
+             <bitWidth>1</bitWidth>
+             <access>read-only</access>
+             <readAction>clear</readAction>
+            </field>
+            <field><name>RUN</name>
+            <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
+ a write operation to the status register.</description>
+             <bitOffset>1</bitOffset>
+             <bitWidth>1</bitWidth>
+             <access>read-only</access>
+            </field>
+            <field>
+             <name>Reserved</name>
+             <description>Reserved</description>
+             <bitOffset>2</bitOffset>
+             <bitWidth>14</bitWidth>
+             <access>read-write</access>
+             <parameters>
+                 <parameter>
+                 <name>Reserved</name>
+                 <value>true</value>
+                 </parameter>
+             </parameters>
+            </field>
+          </fields>
+        </register> 
+        <register>
+            <name>control</name>
+            <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
+            <addressOffset>0x1</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <reset>
+                <value>0x0</value>
+            </reset>
+            <field>
+                <name>ITO</name>
+                <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
+                <bitOffset>0</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>read-write</access>
+            </field>
+            <field>
+                <name>CONT</name>
+                <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
+                <bitOffset>1</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>read-write</access>
+            </field>
+            <field>
+                <name>START</name>
+                <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
+                <bitOffset>2</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>write-only</access>
+            </field>
+            <field>
+                <name>STOP</name>
+                <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
+                <bitOffset>3</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>write-only</access>
+            </field>
+            <field>
+                <name>Reserved</name>
+                <description>Reserved</description>
+                <bitOffset>4</bitOffset>
+                <bitWidth>12</bitWidth>
+                <access>read-write</access>
+                <parameters>
+                    <parameter>
+                    <name>Reserved</name>
+                    <value>true</value>
+                    </parameter>
+                </parameters>
+            </field>
+        </register>
+        <register>
+            <name>${period_name_0}</name>
+            <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
+            <addressOffset>0x2</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_name_0_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_name_1}</name>
+            <description></description>
+            <addressOffset>0x3</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_name_1_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_snap_0}</name>
+            <description></description>
+            <addressOffset>0x4</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_snap_0_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_snap_1}</name>
+            <description></description>
+            <addressOffset>0x5</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_snap_1_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_0}</name>
+            <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
+            <addressOffset>0x6</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_1}</name>
+            <description></description>
+            <addressOffset>0x7</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_2}</name>
+            <description></description>
+            <addressOffset>0x8</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_3}</name>
+            <description></description>
+            <addressOffset>0x9</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+    </registers>
+   </peripheral>
+  <peripheral>
+      <name>q_sys_output_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>32</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>     
+         <name>DATA</name>  
+         <displayName>Data</displayName>
+         <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
+         <addressOffset>0x0</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>data</name>
+           <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>DIRECTION</name>  
+         <displayName>Direction</displayName>
+         <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
+         <addressOffset>0x4</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>direction</name>
+            <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>IRQ_MASK</name>  
+         <displayName>Interrupt mask</displayName>
+         <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
+         <addressOffset>0x8</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>interruptmask</name>
+            <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>EDGE_CAP</name>  
+         <displayName>Edge capture</displayName>
+         <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
+         <addressOffset>0xc</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>edgecapture</name>
+            <description>Edge detection for each input port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>
+         <name>SET_BIT</name>  
+         <displayName>Outset</displayName>
+         <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x10</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outset</name>
+            <description>Specifies which bit of the output port to set.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>CLEAR_BITS</name>  
+         <displayName>Outclear</displayName>
+         <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x14</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outclear</name>
+            <description>Specifies which output bit to clear.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register>            
+    </registers>
+   </peripheral>
+  <peripheral>
+      <name>q_sys_frame_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>16</size>
+        <usage>registers</usage>
+      </addressBlock>
+       <registers>
+         <register>     
+          <name>status</name>  
+          <displayName>Status</displayName>
+          <description>The status register has two defined bits. TO (timeout), RUN</description>
+          <addressOffset>0x0</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffff</resetMask>
+          <fields>
+            <field><name>TO</name>
+            <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
+             <bitOffset>0x0</bitOffset>
+             <bitWidth>1</bitWidth>
+             <access>read-only</access>
+             <readAction>clear</readAction>
+            </field>
+            <field><name>RUN</name>
+            <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
+ a write operation to the status register.</description>
+             <bitOffset>1</bitOffset>
+             <bitWidth>1</bitWidth>
+             <access>read-only</access>
+            </field>
+            <field>
+             <name>Reserved</name>
+             <description>Reserved</description>
+             <bitOffset>2</bitOffset>
+             <bitWidth>14</bitWidth>
+             <access>read-write</access>
+             <parameters>
+                 <parameter>
+                 <name>Reserved</name>
+                 <value>true</value>
+                 </parameter>
+             </parameters>
+            </field>
+          </fields>
+        </register> 
+        <register>
+            <name>control</name>
+            <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
+            <addressOffset>0x1</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <reset>
+                <value>0x0</value>
+            </reset>
+            <field>
+                <name>ITO</name>
+                <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
+                <bitOffset>0</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>read-write</access>
+            </field>
+            <field>
+                <name>CONT</name>
+                <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
+                <bitOffset>1</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>read-write</access>
+            </field>
+            <field>
+                <name>START</name>
+                <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
+                <bitOffset>2</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>write-only</access>
+            </field>
+            <field>
+                <name>STOP</name>
+                <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
+                <bitOffset>3</bitOffset>
+                <bitWidth>1</bitWidth>
+                <access>write-only</access>
+            </field>
+            <field>
+                <name>Reserved</name>
+                <description>Reserved</description>
+                <bitOffset>4</bitOffset>
+                <bitWidth>12</bitWidth>
+                <access>read-write</access>
+                <parameters>
+                    <parameter>
+                    <name>Reserved</name>
+                    <value>true</value>
+                    </parameter>
+                </parameters>
+            </field>
+        </register>
+        <register>
+            <name>${period_name_0}</name>
+            <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
+            <addressOffset>0x2</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_name_0_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_name_1}</name>
+            <description></description>
+            <addressOffset>0x3</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_name_1_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_snap_0}</name>
+            <description></description>
+            <addressOffset>0x4</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_snap_0_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${period_snap_1}</name>
+            <description></description>
+            <addressOffset>0x5</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>${period_snap_1_reset_value}</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_0}</name>
+            <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
+            <addressOffset>0x6</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_1}</name>
+            <description></description>
+            <addressOffset>0x7</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_2}</name>
+            <description></description>
+            <addressOffset>0x8</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+        <register>
+            <name>${snap_3}</name>
+            <description></description>
+            <addressOffset>0x9</addressOffset>
+            <size>16</size>
+            <access>read-write</access>
+            <resetValue>0x0</resetValue>
+            <resetMask>0xffff</resetMask>
+        </register>
+    </registers>
+   </peripheral>
+  <peripheral>
+      <baseAddress>0x00000000</baseAddress>
+      <name>q_sys_ext_flash_avl_csr_altera_generic_quad_spi_controller</name>
+      <description>altera_generic_quad_spi_controller</description>
+      <registers>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0</addressOffset>
+          <displayName>flash_rd_status</displayName>
+		  <description>Perform read operation on flash device status register and store the read back data. </description>
+          <name>flash_rd_status</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x4</addressOffset>
+          <displayName>flash_rd_sid</displayName>
+		  <description>Perform read operation to extract flash device silicon ID and store the read back data. Only support in EPCS16 and EPCS64 flash devices. </description>
+          <name>flash_rd_sid</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x8</addressOffset>
+          <displayName>flash_rd_rdid</displayName>
+		  <description>Perform read operation to extract flash device memory capacity and store the read back data. </description>
+          <name>flash_rd_rdid</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0xc</addressOffset>
+          <displayName>flash_mem_op</displayName>
+		  <description>To protect and erase memory </description>
+          <name>flash_mem_op</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[1:0]</bitRange>
+              <modifiedWriteValues>modify</modifiedWriteValues>
+              <name>memory_operation</name>
+            </field>
+            <field>
+              <access>write-only</access>
+              <bitRange>[23:8]</bitRange>
+              <modifiedWriteValues>modify</modifiedWriteValues>
+              <name>sector_value</name>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x10</addressOffset>
+          <displayName>flash_isr</displayName>
+		  <description>Interrupt status register </description>
+          <name>flash_isr</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>illegal_erase</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>illegal_write</name>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x14</addressOffset>
+          <displayName>flash_imr</displayName>
+		  <description>To mask of interrupt status register </description>
+          <name>flash_imr</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>m_illegal_erase</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>m_illegal_write</name>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x18</addressOffset>
+          <displayName>flash_chip_select</displayName>
+		  <description>Chip select values </description>
+          <name>flash_chip_select</name>
+          <resetMask>0xffffffff</resetMask>
+          <resetValue>0x00000000</resetValue>
+          <size>32</size>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>modify</modifiedWriteValues>
+              <name>chip_select_bit_1</name>
+            </field>
+            <field>
+              <access>write-only</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>modify</modifiedWriteValues>
+              <name>chip_select_bit_2</name>
+            </field>
+            <field>
+              <access>write-only</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>modify</modifiedWriteValues>
+              <name>chip_select_bit_3</name>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  <peripheral>
+      <name>q_sys_button_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>32</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>     
+         <name>DATA</name>  
+         <displayName>Data</displayName>
+         <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
+         <addressOffset>0x0</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>data</name>
+           <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>DIRECTION</name>  
+         <displayName>Direction</displayName>
+         <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
+         <addressOffset>0x4</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>direction</name>
+            <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>IRQ_MASK</name>  
+         <displayName>Interrupt mask</displayName>
+         <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
+         <addressOffset>0x8</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>interruptmask</name>
+            <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>EDGE_CAP</name>  
+         <displayName>Edge capture</displayName>
+         <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
+         <addressOffset>0xc</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>edgecapture</name>
+            <description>Edge detection for each input port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>
+         <name>SET_BIT</name>  
+         <displayName>Outset</displayName>
+         <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x10</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outset</name>
+            <description>Specifies which bit of the output port to set.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>CLEAR_BITS</name>  
+         <displayName>Outclear</displayName>
+         <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x14</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outclear</name>
+            <description>Specifies which output bit to clear.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register>            
+    </registers>
+   </peripheral>
+  </peripherals>
+</device>
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/q_sys.v b/FPGA_firmware/q_sys/synthesis/q_sys.v
new file mode 100644
index 0000000..a2940d1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/q_sys.v
@@ -0,0 +1,1638 @@
+// q_sys.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys (
+		output wire        altpll_shift_c0_clk,                         //                     altpll_shift_c0.clk
+		output wire        altpll_shift_locked_conduit_export,          //         altpll_shift_locked_conduit.export
+		input  wire [8:0]  button_pio_external_connection_export,       //      button_pio_external_connection.export
+		input  wire        clock_bridge_0_in_clk_clk,                   //               clock_bridge_0_in_clk.clk
+		input  wire        ddr3_ram_pll_ref_clk_clk,                    //                ddr3_ram_pll_ref_clk.clk
+		input  wire        debug_uart_external_connection_rxd,          //      debug_uart_external_connection.rxd
+		output wire        debug_uart_external_connection_txd,          //                                    .txd
+		output wire        enet_pll_c0_clk,                             //                         enet_pll_c0.clk
+		output wire        enet_pll_c1_clk,                             //                         enet_pll_c1.clk
+		output wire        enet_pll_c2_clk,                             //                         enet_pll_c2.clk
+		output wire        enet_pll_c3_clk,                             //                         enet_pll_c3.clk
+		output wire        enet_pll_c4_clk,                             //                         enet_pll_c4.clk
+		output wire        enet_pll_locked_conduit_export,              //             enet_pll_locked_conduit.export
+		output wire        eth_tse_mac_mdio_connection_mdc,             //         eth_tse_mac_mdio_connection.mdc
+		input  wire        eth_tse_mac_mdio_connection_mdio_in,         //                                    .mdio_in
+		output wire        eth_tse_mac_mdio_connection_mdio_out,        //                                    .mdio_out
+		output wire        eth_tse_mac_mdio_connection_mdio_oen,        //                                    .mdio_oen
+		input  wire [3:0]  eth_tse_mac_rgmii_connection_rgmii_in,       //        eth_tse_mac_rgmii_connection.rgmii_in
+		output wire [3:0]  eth_tse_mac_rgmii_connection_rgmii_out,      //                                    .rgmii_out
+		input  wire        eth_tse_mac_rgmii_connection_rx_control,     //                                    .rx_control
+		output wire        eth_tse_mac_rgmii_connection_tx_control,     //                                    .tx_control
+		input  wire        eth_tse_mac_status_connection_set_10,        //       eth_tse_mac_status_connection.set_10
+		input  wire        eth_tse_mac_status_connection_set_1000,      //                                    .set_1000
+		output wire        eth_tse_mac_status_connection_eth_mode,      //                                    .eth_mode
+		output wire        eth_tse_mac_status_connection_ena_10,        //                                    .ena_10
+		input  wire        eth_tse_pcs_mac_rx_clock_connection_clk,     // eth_tse_pcs_mac_rx_clock_connection.clk
+		input  wire        eth_tse_pcs_mac_tx_clock_connection_clk,     // eth_tse_pcs_mac_tx_clock_connection.clk
+		inout  wire [3:0]  ext_flash_flash_dataout_conduit_dataout,     //             ext_flash_flash_dataout.conduit_dataout
+		output wire        ext_flash_flash_dclk_out_conduit_dclk_out,   //            ext_flash_flash_dclk_out.conduit_dclk_out
+		output wire [0:0]  ext_flash_flash_ncs_conduit_ncs,             //                 ext_flash_flash_ncs.conduit_ncs
+		output wire        frame_timer_export,                          //                         frame_timer.export
+		output wire [7:0]  led_pio_external_connection_export,          //         led_pio_external_connection.export
+		output wire        mem_if_ddr3_emif_0_status_local_init_done,   //           mem_if_ddr3_emif_0_status.local_init_done
+		output wire        mem_if_ddr3_emif_0_status_local_cal_success, //                                    .local_cal_success
+		output wire        mem_if_ddr3_emif_0_status_local_cal_fail,    //                                    .local_cal_fail
+		input  wire        mem_resetn_in_reset_reset_n,                 //                 mem_resetn_in_reset.reset_n
+		output wire [13:0] memory_mem_a,                                //                              memory.mem_a
+		output wire [2:0]  memory_mem_ba,                               //                                    .mem_ba
+		inout  wire [0:0]  memory_mem_ck,                               //                                    .mem_ck
+		inout  wire [0:0]  memory_mem_ck_n,                             //                                    .mem_ck_n
+		output wire [0:0]  memory_mem_cke,                              //                                    .mem_cke
+		output wire [0:0]  memory_mem_cs_n,                             //                                    .mem_cs_n
+		output wire [0:0]  memory_mem_dm,                               //                                    .mem_dm
+		output wire [0:0]  memory_mem_ras_n,                            //                                    .mem_ras_n
+		output wire [0:0]  memory_mem_cas_n,                            //                                    .mem_cas_n
+		output wire [0:0]  memory_mem_we_n,                             //                                    .mem_we_n
+		output wire        memory_mem_reset_n,                          //                                    .mem_reset_n
+		inout  wire [7:0]  memory_mem_dq,                               //                                    .mem_dq
+		inout  wire [0:0]  memory_mem_dqs,                              //                                    .mem_dqs
+		inout  wire [0:0]  memory_mem_dqs_n,                            //                                    .mem_dqs_n
+		output wire [0:0]  memory_mem_odt,                              //                                    .mem_odt
+		input  wire        reset_reset_n,                               //                               reset.reset_n
+		input  wire [4:0]  sensor_in_adc_data,                          //                              sensor.in_adc_data
+		input  wire        sensor_in_trg,                               //                                    .in_trg
+		output wire        sensor_out_adc_clk,                          //                                    .out_adc_clk
+		output wire        sensor_out_adc_cnv,                          //                                    .out_adc_cnv
+		output wire        sensor_out_sensor_clk,                       //                                    .out_sensor_clk
+		output wire        sensor_out_sensor_gain,                      //                                    .out_sensor_gain
+		output wire        sensor_out_sensor_rst,                       //                                    .out_sensor_rst
+		output wire [7:0]  sensor_status_status_out,                    //                       sensor_status.status_out
+		input  wire [7:0]  sensor_synchro_ext_input,                    //                      sensor_synchro.ext_input
+		input  wire        sensor_synchro_serial_rx,                    //                                    .serial_rx
+		output wire        sensor_synchro_serial_tx,                    //                                    .serial_tx
+		input  wire        sys_clk_clk                                  //                             sys_clk.clk
+	);
+
+	wire         sensor_interface_data_out_valid;                        // sensor_interface:data_out_valid -> udp_generator:data_in_valid
+	wire  [31:0] sensor_interface_data_out_data;                         // sensor_interface:data_out_data -> udp_generator:data_in_data
+	wire         sensor_interface_data_out_ready;                        // udp_generator:data_in_ready -> sensor_interface:data_out_ready
+	wire         sensor_interface_data_out_startofpacket;                // sensor_interface:data_out_startofpacket -> udp_generator:data_in_startofpacket
+	wire         sensor_interface_data_out_endofpacket;                  // sensor_interface:data_out_endofpacket -> udp_generator:data_in_endofpacket
+	wire   [1:0] sensor_interface_data_out_empty;                        // sensor_interface:data_out_empty -> udp_generator:data_in_empty
+	wire         tx_multiplexer_out_valid;                               // tx_multiplexer:out_valid -> channel_adapter_0:in_valid
+	wire  [31:0] tx_multiplexer_out_data;                                // tx_multiplexer:out_data -> channel_adapter_0:in_data
+	wire         tx_multiplexer_out_ready;                               // channel_adapter_0:in_ready -> tx_multiplexer:out_ready
+	wire         tx_multiplexer_out_channel;                             // tx_multiplexer:out_channel -> channel_adapter_0:in_channel
+	wire         tx_multiplexer_out_startofpacket;                       // tx_multiplexer:out_startofpacket -> channel_adapter_0:in_startofpacket
+	wire         tx_multiplexer_out_endofpacket;                         // tx_multiplexer:out_endofpacket -> channel_adapter_0:in_endofpacket
+	wire         tx_multiplexer_out_error;                               // tx_multiplexer:out_error -> channel_adapter_0:in_error
+	wire   [1:0] tx_multiplexer_out_empty;                               // tx_multiplexer:out_empty -> channel_adapter_0:in_empty
+	wire         channel_adapter_0_out_valid;                            // channel_adapter_0:out_valid -> eth_tse:ff_tx_wren
+	wire  [31:0] channel_adapter_0_out_data;                             // channel_adapter_0:out_data -> eth_tse:ff_tx_data
+	wire         channel_adapter_0_out_ready;                            // eth_tse:ff_tx_rdy -> channel_adapter_0:out_ready
+	wire         channel_adapter_0_out_startofpacket;                    // channel_adapter_0:out_startofpacket -> eth_tse:ff_tx_sop
+	wire         channel_adapter_0_out_endofpacket;                      // channel_adapter_0:out_endofpacket -> eth_tse:ff_tx_eop
+	wire         channel_adapter_0_out_error;                            // channel_adapter_0:out_error -> eth_tse:ff_tx_err
+	wire   [1:0] channel_adapter_0_out_empty;                            // channel_adapter_0:out_empty -> eth_tse:ff_tx_mod
+	wire         msgdma_tx_st_source_valid;                              // msgdma_tx:st_source_valid -> tx_multiplexer:in0_valid
+	wire  [31:0] msgdma_tx_st_source_data;                               // msgdma_tx:st_source_data -> tx_multiplexer:in0_data
+	wire         msgdma_tx_st_source_ready;                              // tx_multiplexer:in0_ready -> msgdma_tx:st_source_ready
+	wire         msgdma_tx_st_source_startofpacket;                      // msgdma_tx:st_source_startofpacket -> tx_multiplexer:in0_startofpacket
+	wire         msgdma_tx_st_source_endofpacket;                        // msgdma_tx:st_source_endofpacket -> tx_multiplexer:in0_endofpacket
+	wire         msgdma_tx_st_source_error;                              // msgdma_tx:st_source_error -> tx_multiplexer:in0_error
+	wire   [1:0] msgdma_tx_st_source_empty;                              // msgdma_tx:st_source_empty -> tx_multiplexer:in0_empty
+	wire  [15:0] sensor_interface_calibration_ram_interface_readdata;    // mm_interconnect_0:sensor_interface_calibration_ram_interface_readdata -> sensor_interface:cali_fac
+	wire         sensor_interface_calibration_ram_interface_waitrequest; // mm_interconnect_0:sensor_interface_calibration_ram_interface_waitrequest -> sensor_interface:waitrequest
+	wire   [8:0] sensor_interface_calibration_ram_interface_address;     // sensor_interface:address -> mm_interconnect_0:sensor_interface_calibration_ram_interface_address
+	wire         sensor_interface_calibration_ram_interface_read;        // sensor_interface:clken -> mm_interconnect_0:sensor_interface_calibration_ram_interface_read
+	wire         mm_interconnect_0_calibration_ram_s2_chipselect;        // mm_interconnect_0:calibration_ram_s2_chipselect -> calibration_ram:chipselect2
+	wire  [15:0] mm_interconnect_0_calibration_ram_s2_readdata;          // calibration_ram:readdata2 -> mm_interconnect_0:calibration_ram_s2_readdata
+	wire   [8:0] mm_interconnect_0_calibration_ram_s2_address;           // mm_interconnect_0:calibration_ram_s2_address -> calibration_ram:address2
+	wire   [1:0] mm_interconnect_0_calibration_ram_s2_byteenable;        // mm_interconnect_0:calibration_ram_s2_byteenable -> calibration_ram:byteenable2
+	wire         mm_interconnect_0_calibration_ram_s2_write;             // mm_interconnect_0:calibration_ram_s2_write -> calibration_ram:write2
+	wire  [15:0] mm_interconnect_0_calibration_ram_s2_writedata;         // mm_interconnect_0:calibration_ram_s2_writedata -> calibration_ram:writedata2
+	wire         mm_interconnect_0_calibration_ram_s2_clken;             // mm_interconnect_0:calibration_ram_s2_clken -> calibration_ram:clken2
+	wire  [31:0] cpu_data_master_readdata;                               // mm_interconnect_1:cpu_data_master_readdata -> cpu:d_readdata
+	wire         cpu_data_master_waitrequest;                            // mm_interconnect_1:cpu_data_master_waitrequest -> cpu:d_waitrequest
+	wire         cpu_data_master_debugaccess;                            // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_1:cpu_data_master_debugaccess
+	wire  [28:0] cpu_data_master_address;                                // cpu:d_address -> mm_interconnect_1:cpu_data_master_address
+	wire   [3:0] cpu_data_master_byteenable;                             // cpu:d_byteenable -> mm_interconnect_1:cpu_data_master_byteenable
+	wire         cpu_data_master_read;                                   // cpu:d_read -> mm_interconnect_1:cpu_data_master_read
+	wire         cpu_data_master_readdatavalid;                          // mm_interconnect_1:cpu_data_master_readdatavalid -> cpu:d_readdatavalid
+	wire         cpu_data_master_write;                                  // cpu:d_write -> mm_interconnect_1:cpu_data_master_write
+	wire  [31:0] cpu_data_master_writedata;                              // cpu:d_writedata -> mm_interconnect_1:cpu_data_master_writedata
+	wire  [31:0] cpu_instruction_master_readdata;                        // mm_interconnect_1:cpu_instruction_master_readdata -> cpu:i_readdata
+	wire         cpu_instruction_master_waitrequest;                     // mm_interconnect_1:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
+	wire  [28:0] cpu_instruction_master_address;                         // cpu:i_address -> mm_interconnect_1:cpu_instruction_master_address
+	wire         cpu_instruction_master_read;                            // cpu:i_read -> mm_interconnect_1:cpu_instruction_master_read
+	wire         cpu_instruction_master_readdatavalid;                   // mm_interconnect_1:cpu_instruction_master_readdatavalid -> cpu:i_readdatavalid
+	wire  [31:0] msgdma_tx_mm_read_readdata;                             // mm_interconnect_1:msgdma_tx_mm_read_readdata -> msgdma_tx:mm_read_readdata
+	wire         msgdma_tx_mm_read_waitrequest;                          // mm_interconnect_1:msgdma_tx_mm_read_waitrequest -> msgdma_tx:mm_read_waitrequest
+	wire  [27:0] msgdma_tx_mm_read_address;                              // msgdma_tx:mm_read_address -> mm_interconnect_1:msgdma_tx_mm_read_address
+	wire         msgdma_tx_mm_read_read;                                 // msgdma_tx:mm_read_read -> mm_interconnect_1:msgdma_tx_mm_read_read
+	wire   [3:0] msgdma_tx_mm_read_byteenable;                           // msgdma_tx:mm_read_byteenable -> mm_interconnect_1:msgdma_tx_mm_read_byteenable
+	wire         msgdma_tx_mm_read_readdatavalid;                        // mm_interconnect_1:msgdma_tx_mm_read_readdatavalid -> msgdma_tx:mm_read_readdatavalid
+	wire         msgdma_rx_mm_write_waitrequest;                         // mm_interconnect_1:msgdma_rx_mm_write_waitrequest -> msgdma_rx:mm_write_waitrequest
+	wire  [27:0] msgdma_rx_mm_write_address;                             // msgdma_rx:mm_write_address -> mm_interconnect_1:msgdma_rx_mm_write_address
+	wire   [3:0] msgdma_rx_mm_write_byteenable;                          // msgdma_rx:mm_write_byteenable -> mm_interconnect_1:msgdma_rx_mm_write_byteenable
+	wire         msgdma_rx_mm_write_write;                               // msgdma_rx:mm_write_write -> mm_interconnect_1:msgdma_rx_mm_write_write
+	wire  [31:0] msgdma_rx_mm_write_writedata;                           // msgdma_rx:mm_write_writedata -> mm_interconnect_1:msgdma_rx_mm_write_writedata
+	wire  [31:0] msgdma_tx_descriptor_read_master_readdata;              // mm_interconnect_1:msgdma_tx_descriptor_read_master_readdata -> msgdma_tx:descriptor_read_master_readdata
+	wire         msgdma_tx_descriptor_read_master_waitrequest;           // mm_interconnect_1:msgdma_tx_descriptor_read_master_waitrequest -> msgdma_tx:descriptor_read_master_waitrequest
+	wire  [28:0] msgdma_tx_descriptor_read_master_address;               // msgdma_tx:descriptor_read_master_address -> mm_interconnect_1:msgdma_tx_descriptor_read_master_address
+	wire         msgdma_tx_descriptor_read_master_read;                  // msgdma_tx:descriptor_read_master_read -> mm_interconnect_1:msgdma_tx_descriptor_read_master_read
+	wire         msgdma_tx_descriptor_read_master_readdatavalid;         // mm_interconnect_1:msgdma_tx_descriptor_read_master_readdatavalid -> msgdma_tx:descriptor_read_master_readdatavalid
+	wire  [31:0] msgdma_rx_descriptor_read_master_readdata;              // mm_interconnect_1:msgdma_rx_descriptor_read_master_readdata -> msgdma_rx:descriptor_read_master_readdata
+	wire         msgdma_rx_descriptor_read_master_waitrequest;           // mm_interconnect_1:msgdma_rx_descriptor_read_master_waitrequest -> msgdma_rx:descriptor_read_master_waitrequest
+	wire  [28:0] msgdma_rx_descriptor_read_master_address;               // msgdma_rx:descriptor_read_master_address -> mm_interconnect_1:msgdma_rx_descriptor_read_master_address
+	wire         msgdma_rx_descriptor_read_master_read;                  // msgdma_rx:descriptor_read_master_read -> mm_interconnect_1:msgdma_rx_descriptor_read_master_read
+	wire         msgdma_rx_descriptor_read_master_readdatavalid;         // mm_interconnect_1:msgdma_rx_descriptor_read_master_readdatavalid -> msgdma_rx:descriptor_read_master_readdatavalid
+	wire         msgdma_tx_descriptor_write_master_waitrequest;          // mm_interconnect_1:msgdma_tx_descriptor_write_master_waitrequest -> msgdma_tx:descriptor_write_master_waitrequest
+	wire  [28:0] msgdma_tx_descriptor_write_master_address;              // msgdma_tx:descriptor_write_master_address -> mm_interconnect_1:msgdma_tx_descriptor_write_master_address
+	wire   [3:0] msgdma_tx_descriptor_write_master_byteenable;           // msgdma_tx:descriptor_write_master_byteenable -> mm_interconnect_1:msgdma_tx_descriptor_write_master_byteenable
+	wire   [1:0] msgdma_tx_descriptor_write_master_response;             // mm_interconnect_1:msgdma_tx_descriptor_write_master_response -> msgdma_tx:descriptor_write_master_response
+	wire         msgdma_tx_descriptor_write_master_write;                // msgdma_tx:descriptor_write_master_write -> mm_interconnect_1:msgdma_tx_descriptor_write_master_write
+	wire  [31:0] msgdma_tx_descriptor_write_master_writedata;            // msgdma_tx:descriptor_write_master_writedata -> mm_interconnect_1:msgdma_tx_descriptor_write_master_writedata
+	wire         msgdma_tx_descriptor_write_master_writeresponsevalid;   // mm_interconnect_1:msgdma_tx_descriptor_write_master_writeresponsevalid -> msgdma_tx:descriptor_write_master_writeresponsevalid
+	wire         msgdma_rx_descriptor_write_master_waitrequest;          // mm_interconnect_1:msgdma_rx_descriptor_write_master_waitrequest -> msgdma_rx:descriptor_write_master_waitrequest
+	wire  [28:0] msgdma_rx_descriptor_write_master_address;              // msgdma_rx:descriptor_write_master_address -> mm_interconnect_1:msgdma_rx_descriptor_write_master_address
+	wire   [3:0] msgdma_rx_descriptor_write_master_byteenable;           // msgdma_rx:descriptor_write_master_byteenable -> mm_interconnect_1:msgdma_rx_descriptor_write_master_byteenable
+	wire   [1:0] msgdma_rx_descriptor_write_master_response;             // mm_interconnect_1:msgdma_rx_descriptor_write_master_response -> msgdma_rx:descriptor_write_master_response
+	wire         msgdma_rx_descriptor_write_master_write;                // msgdma_rx:descriptor_write_master_write -> mm_interconnect_1:msgdma_rx_descriptor_write_master_write
+	wire  [31:0] msgdma_rx_descriptor_write_master_writedata;            // msgdma_rx:descriptor_write_master_writedata -> mm_interconnect_1:msgdma_rx_descriptor_write_master_writedata
+	wire         msgdma_rx_descriptor_write_master_writeresponsevalid;   // mm_interconnect_1:msgdma_rx_descriptor_write_master_writeresponsevalid -> msgdma_rx:descriptor_write_master_writeresponsevalid
+	wire         mm_interconnect_1_ddr3_ram_avl_beginbursttransfer;      // mm_interconnect_1:ddr3_ram_avl_beginbursttransfer -> ddr3_ram:avl_burstbegin
+	wire  [31:0] mm_interconnect_1_ddr3_ram_avl_readdata;                // ddr3_ram:avl_rdata -> mm_interconnect_1:ddr3_ram_avl_readdata
+	wire         mm_interconnect_1_ddr3_ram_avl_waitrequest;             // ddr3_ram:avl_ready -> mm_interconnect_1:ddr3_ram_avl_waitrequest
+	wire  [24:0] mm_interconnect_1_ddr3_ram_avl_address;                 // mm_interconnect_1:ddr3_ram_avl_address -> ddr3_ram:avl_addr
+	wire         mm_interconnect_1_ddr3_ram_avl_read;                    // mm_interconnect_1:ddr3_ram_avl_read -> ddr3_ram:avl_read_req
+	wire   [3:0] mm_interconnect_1_ddr3_ram_avl_byteenable;              // mm_interconnect_1:ddr3_ram_avl_byteenable -> ddr3_ram:avl_be
+	wire         mm_interconnect_1_ddr3_ram_avl_readdatavalid;           // ddr3_ram:avl_rdata_valid -> mm_interconnect_1:ddr3_ram_avl_readdatavalid
+	wire         mm_interconnect_1_ddr3_ram_avl_write;                   // mm_interconnect_1:ddr3_ram_avl_write -> ddr3_ram:avl_write_req
+	wire  [31:0] mm_interconnect_1_ddr3_ram_avl_writedata;               // mm_interconnect_1:ddr3_ram_avl_writedata -> ddr3_ram:avl_wdata
+	wire   [2:0] mm_interconnect_1_ddr3_ram_avl_burstcount;              // mm_interconnect_1:ddr3_ram_avl_burstcount -> ddr3_ram:avl_size
+	wire         ddr3_ram_afi_clk_clk;                                   // ddr3_ram:afi_clk -> [mm_interconnect_1:ddr3_ram_afi_clk_clk, rst_controller_006:clk]
+	wire  [31:0] mm_interconnect_1_ext_flash_avl_csr_readdata;           // ext_flash:avl_csr_rddata -> mm_interconnect_1:ext_flash_avl_csr_readdata
+	wire         mm_interconnect_1_ext_flash_avl_csr_waitrequest;        // ext_flash:avl_csr_waitrequest -> mm_interconnect_1:ext_flash_avl_csr_waitrequest
+	wire   [2:0] mm_interconnect_1_ext_flash_avl_csr_address;            // mm_interconnect_1:ext_flash_avl_csr_address -> ext_flash:avl_csr_addr
+	wire         mm_interconnect_1_ext_flash_avl_csr_read;               // mm_interconnect_1:ext_flash_avl_csr_read -> ext_flash:avl_csr_read
+	wire         mm_interconnect_1_ext_flash_avl_csr_readdatavalid;      // ext_flash:avl_csr_rddata_valid -> mm_interconnect_1:ext_flash_avl_csr_readdatavalid
+	wire         mm_interconnect_1_ext_flash_avl_csr_write;              // mm_interconnect_1:ext_flash_avl_csr_write -> ext_flash:avl_csr_write
+	wire  [31:0] mm_interconnect_1_ext_flash_avl_csr_writedata;          // mm_interconnect_1:ext_flash_avl_csr_writedata -> ext_flash:avl_csr_wrdata
+	wire  [31:0] mm_interconnect_1_ext_flash_avl_mem_readdata;           // ext_flash:avl_mem_rddata -> mm_interconnect_1:ext_flash_avl_mem_readdata
+	wire         mm_interconnect_1_ext_flash_avl_mem_waitrequest;        // ext_flash:avl_mem_waitrequest -> mm_interconnect_1:ext_flash_avl_mem_waitrequest
+	wire  [23:0] mm_interconnect_1_ext_flash_avl_mem_address;            // mm_interconnect_1:ext_flash_avl_mem_address -> ext_flash:avl_mem_addr
+	wire         mm_interconnect_1_ext_flash_avl_mem_read;               // mm_interconnect_1:ext_flash_avl_mem_read -> ext_flash:avl_mem_read
+	wire   [3:0] mm_interconnect_1_ext_flash_avl_mem_byteenable;         // mm_interconnect_1:ext_flash_avl_mem_byteenable -> ext_flash:avl_mem_byteenable
+	wire         mm_interconnect_1_ext_flash_avl_mem_readdatavalid;      // ext_flash:avl_mem_rddata_valid -> mm_interconnect_1:ext_flash_avl_mem_readdatavalid
+	wire         mm_interconnect_1_ext_flash_avl_mem_write;              // mm_interconnect_1:ext_flash_avl_mem_write -> ext_flash:avl_mem_write
+	wire  [31:0] mm_interconnect_1_ext_flash_avl_mem_writedata;          // mm_interconnect_1:ext_flash_avl_mem_writedata -> ext_flash:avl_mem_wrdata
+	wire   [6:0] mm_interconnect_1_ext_flash_avl_mem_burstcount;         // mm_interconnect_1:ext_flash_avl_mem_burstcount -> ext_flash:avl_mem_burstcount
+	wire  [31:0] mm_interconnect_1_eth_tse_control_port_readdata;        // eth_tse:reg_data_out -> mm_interconnect_1:eth_tse_control_port_readdata
+	wire         mm_interconnect_1_eth_tse_control_port_waitrequest;     // eth_tse:reg_busy -> mm_interconnect_1:eth_tse_control_port_waitrequest
+	wire   [7:0] mm_interconnect_1_eth_tse_control_port_address;         // mm_interconnect_1:eth_tse_control_port_address -> eth_tse:reg_addr
+	wire         mm_interconnect_1_eth_tse_control_port_read;            // mm_interconnect_1:eth_tse_control_port_read -> eth_tse:reg_rd
+	wire         mm_interconnect_1_eth_tse_control_port_write;           // mm_interconnect_1:eth_tse_control_port_write -> eth_tse:reg_wr
+	wire  [31:0] mm_interconnect_1_eth_tse_control_port_writedata;       // mm_interconnect_1:eth_tse_control_port_writedata -> eth_tse:reg_data_in
+	wire  [31:0] mm_interconnect_1_sysid_control_slave_readdata;         // sysid:readdata -> mm_interconnect_1:sysid_control_slave_readdata
+	wire   [0:0] mm_interconnect_1_sysid_control_slave_address;          // mm_interconnect_1:sysid_control_slave_address -> sysid:address
+	wire  [31:0] mm_interconnect_1_msgdma_tx_csr_readdata;               // msgdma_tx:csr_readdata -> mm_interconnect_1:msgdma_tx_csr_readdata
+	wire   [2:0] mm_interconnect_1_msgdma_tx_csr_address;                // mm_interconnect_1:msgdma_tx_csr_address -> msgdma_tx:csr_address
+	wire         mm_interconnect_1_msgdma_tx_csr_read;                   // mm_interconnect_1:msgdma_tx_csr_read -> msgdma_tx:csr_read
+	wire   [3:0] mm_interconnect_1_msgdma_tx_csr_byteenable;             // mm_interconnect_1:msgdma_tx_csr_byteenable -> msgdma_tx:csr_byteenable
+	wire         mm_interconnect_1_msgdma_tx_csr_write;                  // mm_interconnect_1:msgdma_tx_csr_write -> msgdma_tx:csr_write
+	wire  [31:0] mm_interconnect_1_msgdma_tx_csr_writedata;              // mm_interconnect_1:msgdma_tx_csr_writedata -> msgdma_tx:csr_writedata
+	wire  [31:0] mm_interconnect_1_msgdma_rx_csr_readdata;               // msgdma_rx:csr_readdata -> mm_interconnect_1:msgdma_rx_csr_readdata
+	wire   [2:0] mm_interconnect_1_msgdma_rx_csr_address;                // mm_interconnect_1:msgdma_rx_csr_address -> msgdma_rx:csr_address
+	wire         mm_interconnect_1_msgdma_rx_csr_read;                   // mm_interconnect_1:msgdma_rx_csr_read -> msgdma_rx:csr_read
+	wire   [3:0] mm_interconnect_1_msgdma_rx_csr_byteenable;             // mm_interconnect_1:msgdma_rx_csr_byteenable -> msgdma_rx:csr_byteenable
+	wire         mm_interconnect_1_msgdma_rx_csr_write;                  // mm_interconnect_1:msgdma_rx_csr_write -> msgdma_rx:csr_write
+	wire  [31:0] mm_interconnect_1_msgdma_rx_csr_writedata;              // mm_interconnect_1:msgdma_rx_csr_writedata -> msgdma_rx:csr_writedata
+	wire  [31:0] mm_interconnect_1_onchip_flash_csr_readdata;            // onchip_flash:avmm_csr_readdata -> mm_interconnect_1:onchip_flash_csr_readdata
+	wire   [0:0] mm_interconnect_1_onchip_flash_csr_address;             // mm_interconnect_1:onchip_flash_csr_address -> onchip_flash:avmm_csr_addr
+	wire         mm_interconnect_1_onchip_flash_csr_read;                // mm_interconnect_1:onchip_flash_csr_read -> onchip_flash:avmm_csr_read
+	wire         mm_interconnect_1_onchip_flash_csr_write;               // mm_interconnect_1:onchip_flash_csr_write -> onchip_flash:avmm_csr_write
+	wire  [31:0] mm_interconnect_1_onchip_flash_csr_writedata;           // mm_interconnect_1:onchip_flash_csr_writedata -> onchip_flash:avmm_csr_writedata
+	wire  [31:0] mm_interconnect_1_udp_generator_csr_readdata;           // udp_generator:csr_readdata -> mm_interconnect_1:udp_generator_csr_readdata
+	wire   [2:0] mm_interconnect_1_udp_generator_csr_address;            // mm_interconnect_1:udp_generator_csr_address -> udp_generator:csr_address
+	wire         mm_interconnect_1_udp_generator_csr_read;               // mm_interconnect_1:udp_generator_csr_read -> udp_generator:csr_read
+	wire   [3:0] mm_interconnect_1_udp_generator_csr_byteenable;         // mm_interconnect_1:udp_generator_csr_byteenable -> udp_generator:csr_byteenable
+	wire         mm_interconnect_1_udp_generator_csr_write;              // mm_interconnect_1:udp_generator_csr_write -> udp_generator:csr_write
+	wire  [31:0] mm_interconnect_1_udp_generator_csr_writedata;          // mm_interconnect_1:udp_generator_csr_writedata -> udp_generator:csr_writedata
+	wire  [31:0] mm_interconnect_1_sensor_interface_csr_readdata;        // sensor_interface:csr_readdata -> mm_interconnect_1:sensor_interface_csr_readdata
+	wire   [1:0] mm_interconnect_1_sensor_interface_csr_address;         // mm_interconnect_1:sensor_interface_csr_address -> sensor_interface:csr_address
+	wire         mm_interconnect_1_sensor_interface_csr_read;            // mm_interconnect_1:sensor_interface_csr_read -> sensor_interface:csr_read
+	wire   [3:0] mm_interconnect_1_sensor_interface_csr_byteenable;      // mm_interconnect_1:sensor_interface_csr_byteenable -> sensor_interface:csr_byteenable
+	wire         mm_interconnect_1_sensor_interface_csr_write;           // mm_interconnect_1:sensor_interface_csr_write -> sensor_interface:csr_write
+	wire  [31:0] mm_interconnect_1_sensor_interface_csr_writedata;       // mm_interconnect_1:sensor_interface_csr_writedata -> sensor_interface:csr_writedata
+	wire  [31:0] mm_interconnect_1_onchip_flash_data_readdata;           // onchip_flash:avmm_data_readdata -> mm_interconnect_1:onchip_flash_data_readdata
+	wire         mm_interconnect_1_onchip_flash_data_waitrequest;        // onchip_flash:avmm_data_waitrequest -> mm_interconnect_1:onchip_flash_data_waitrequest
+	wire  [18:0] mm_interconnect_1_onchip_flash_data_address;            // mm_interconnect_1:onchip_flash_data_address -> onchip_flash:avmm_data_addr
+	wire         mm_interconnect_1_onchip_flash_data_read;               // mm_interconnect_1:onchip_flash_data_read -> onchip_flash:avmm_data_read
+	wire         mm_interconnect_1_onchip_flash_data_readdatavalid;      // onchip_flash:avmm_data_readdatavalid -> mm_interconnect_1:onchip_flash_data_readdatavalid
+	wire         mm_interconnect_1_onchip_flash_data_write;              // mm_interconnect_1:onchip_flash_data_write -> onchip_flash:avmm_data_write
+	wire  [31:0] mm_interconnect_1_onchip_flash_data_writedata;          // mm_interconnect_1:onchip_flash_data_writedata -> onchip_flash:avmm_data_writedata
+	wire   [3:0] mm_interconnect_1_onchip_flash_data_burstcount;         // mm_interconnect_1:onchip_flash_data_burstcount -> onchip_flash:avmm_data_burstcount
+	wire  [31:0] mm_interconnect_1_cpu_debug_mem_slave_readdata;         // cpu:debug_mem_slave_readdata -> mm_interconnect_1:cpu_debug_mem_slave_readdata
+	wire         mm_interconnect_1_cpu_debug_mem_slave_waitrequest;      // cpu:debug_mem_slave_waitrequest -> mm_interconnect_1:cpu_debug_mem_slave_waitrequest
+	wire         mm_interconnect_1_cpu_debug_mem_slave_debugaccess;      // mm_interconnect_1:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
+	wire   [8:0] mm_interconnect_1_cpu_debug_mem_slave_address;          // mm_interconnect_1:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address
+	wire         mm_interconnect_1_cpu_debug_mem_slave_read;             // mm_interconnect_1:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read
+	wire   [3:0] mm_interconnect_1_cpu_debug_mem_slave_byteenable;       // mm_interconnect_1:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
+	wire         mm_interconnect_1_cpu_debug_mem_slave_write;            // mm_interconnect_1:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
+	wire  [31:0] mm_interconnect_1_cpu_debug_mem_slave_writedata;        // mm_interconnect_1:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
+	wire  [31:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata;    // msgdma_tx:prefetcher_csr_readdata -> mm_interconnect_1:msgdma_tx_prefetcher_csr_readdata
+	wire   [2:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_address;     // mm_interconnect_1:msgdma_tx_prefetcher_csr_address -> msgdma_tx:prefetcher_csr_address
+	wire         mm_interconnect_1_msgdma_tx_prefetcher_csr_read;        // mm_interconnect_1:msgdma_tx_prefetcher_csr_read -> msgdma_tx:prefetcher_csr_read
+	wire         mm_interconnect_1_msgdma_tx_prefetcher_csr_write;       // mm_interconnect_1:msgdma_tx_prefetcher_csr_write -> msgdma_tx:prefetcher_csr_write
+	wire  [31:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata;   // mm_interconnect_1:msgdma_tx_prefetcher_csr_writedata -> msgdma_tx:prefetcher_csr_writedata
+	wire  [31:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata;    // msgdma_rx:prefetcher_csr_readdata -> mm_interconnect_1:msgdma_rx_prefetcher_csr_readdata
+	wire   [2:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_address;     // mm_interconnect_1:msgdma_rx_prefetcher_csr_address -> msgdma_rx:prefetcher_csr_address
+	wire         mm_interconnect_1_msgdma_rx_prefetcher_csr_read;        // mm_interconnect_1:msgdma_rx_prefetcher_csr_read -> msgdma_rx:prefetcher_csr_read
+	wire         mm_interconnect_1_msgdma_rx_prefetcher_csr_write;       // mm_interconnect_1:msgdma_rx_prefetcher_csr_write -> msgdma_rx:prefetcher_csr_write
+	wire  [31:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata;   // mm_interconnect_1:msgdma_rx_prefetcher_csr_writedata -> msgdma_rx:prefetcher_csr_writedata
+	wire         mm_interconnect_1_descriptor_memory_s1_chipselect;      // mm_interconnect_1:descriptor_memory_s1_chipselect -> descriptor_memory:chipselect
+	wire  [31:0] mm_interconnect_1_descriptor_memory_s1_readdata;        // descriptor_memory:readdata -> mm_interconnect_1:descriptor_memory_s1_readdata
+	wire  [10:0] mm_interconnect_1_descriptor_memory_s1_address;         // mm_interconnect_1:descriptor_memory_s1_address -> descriptor_memory:address
+	wire   [3:0] mm_interconnect_1_descriptor_memory_s1_byteenable;      // mm_interconnect_1:descriptor_memory_s1_byteenable -> descriptor_memory:byteenable
+	wire         mm_interconnect_1_descriptor_memory_s1_write;           // mm_interconnect_1:descriptor_memory_s1_write -> descriptor_memory:write
+	wire  [31:0] mm_interconnect_1_descriptor_memory_s1_writedata;       // mm_interconnect_1:descriptor_memory_s1_writedata -> descriptor_memory:writedata
+	wire         mm_interconnect_1_descriptor_memory_s1_clken;           // mm_interconnect_1:descriptor_memory_s1_clken -> descriptor_memory:clken
+	wire         mm_interconnect_1_sys_clk_timer_s1_chipselect;          // mm_interconnect_1:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
+	wire  [15:0] mm_interconnect_1_sys_clk_timer_s1_readdata;            // sys_clk_timer:readdata -> mm_interconnect_1:sys_clk_timer_s1_readdata
+	wire   [2:0] mm_interconnect_1_sys_clk_timer_s1_address;             // mm_interconnect_1:sys_clk_timer_s1_address -> sys_clk_timer:address
+	wire         mm_interconnect_1_sys_clk_timer_s1_write;               // mm_interconnect_1:sys_clk_timer_s1_write -> sys_clk_timer:write_n
+	wire  [15:0] mm_interconnect_1_sys_clk_timer_s1_writedata;           // mm_interconnect_1:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
+	wire         mm_interconnect_1_output_pio_s1_chipselect;             // mm_interconnect_1:output_pio_s1_chipselect -> output_pio:chipselect
+	wire  [31:0] mm_interconnect_1_output_pio_s1_readdata;               // output_pio:readdata -> mm_interconnect_1:output_pio_s1_readdata
+	wire   [2:0] mm_interconnect_1_output_pio_s1_address;                // mm_interconnect_1:output_pio_s1_address -> output_pio:address
+	wire         mm_interconnect_1_output_pio_s1_write;                  // mm_interconnect_1:output_pio_s1_write -> output_pio:write_n
+	wire  [31:0] mm_interconnect_1_output_pio_s1_writedata;              // mm_interconnect_1:output_pio_s1_writedata -> output_pio:writedata
+	wire  [31:0] mm_interconnect_1_button_pio_s1_readdata;               // button_pio:readdata -> mm_interconnect_1:button_pio_s1_readdata
+	wire   [1:0] mm_interconnect_1_button_pio_s1_address;                // mm_interconnect_1:button_pio_s1_address -> button_pio:address
+	wire         mm_interconnect_1_debug_uart_s1_chipselect;             // mm_interconnect_1:debug_uart_s1_chipselect -> debug_uart:chipselect
+	wire  [15:0] mm_interconnect_1_debug_uart_s1_readdata;               // debug_uart:readdata -> mm_interconnect_1:debug_uart_s1_readdata
+	wire   [2:0] mm_interconnect_1_debug_uart_s1_address;                // mm_interconnect_1:debug_uart_s1_address -> debug_uart:address
+	wire         mm_interconnect_1_debug_uart_s1_read;                   // mm_interconnect_1:debug_uart_s1_read -> debug_uart:read_n
+	wire         mm_interconnect_1_debug_uart_s1_begintransfer;          // mm_interconnect_1:debug_uart_s1_begintransfer -> debug_uart:begintransfer
+	wire         mm_interconnect_1_debug_uart_s1_write;                  // mm_interconnect_1:debug_uart_s1_write -> debug_uart:write_n
+	wire  [15:0] mm_interconnect_1_debug_uart_s1_writedata;              // mm_interconnect_1:debug_uart_s1_writedata -> debug_uart:writedata
+	wire         mm_interconnect_1_frame_timer_s1_chipselect;            // mm_interconnect_1:frame_timer_s1_chipselect -> frame_timer:chipselect
+	wire  [15:0] mm_interconnect_1_frame_timer_s1_readdata;              // frame_timer:readdata -> mm_interconnect_1:frame_timer_s1_readdata
+	wire   [2:0] mm_interconnect_1_frame_timer_s1_address;               // mm_interconnect_1:frame_timer_s1_address -> frame_timer:address
+	wire         mm_interconnect_1_frame_timer_s1_write;                 // mm_interconnect_1:frame_timer_s1_write -> frame_timer:write_n
+	wire  [15:0] mm_interconnect_1_frame_timer_s1_writedata;             // mm_interconnect_1:frame_timer_s1_writedata -> frame_timer:writedata
+	wire         mm_interconnect_1_calibration_ram_s1_chipselect;        // mm_interconnect_1:calibration_ram_s1_chipselect -> calibration_ram:chipselect
+	wire  [15:0] mm_interconnect_1_calibration_ram_s1_readdata;          // calibration_ram:readdata -> mm_interconnect_1:calibration_ram_s1_readdata
+	wire   [8:0] mm_interconnect_1_calibration_ram_s1_address;           // mm_interconnect_1:calibration_ram_s1_address -> calibration_ram:address
+	wire   [1:0] mm_interconnect_1_calibration_ram_s1_byteenable;        // mm_interconnect_1:calibration_ram_s1_byteenable -> calibration_ram:byteenable
+	wire         mm_interconnect_1_calibration_ram_s1_write;             // mm_interconnect_1:calibration_ram_s1_write -> calibration_ram:write
+	wire  [15:0] mm_interconnect_1_calibration_ram_s1_writedata;         // mm_interconnect_1:calibration_ram_s1_writedata -> calibration_ram:writedata
+	wire         mm_interconnect_1_calibration_ram_s1_clken;             // mm_interconnect_1:calibration_ram_s1_clken -> calibration_ram:clken
+	wire         irq_mapper_receiver0_irq;                               // msgdma_tx:csr_irq_irq -> irq_mapper:receiver0_irq
+	wire         irq_mapper_receiver1_irq;                               // msgdma_rx:csr_irq_irq -> irq_mapper:receiver1_irq
+	wire         irq_mapper_receiver3_irq;                               // sys_clk_timer:irq -> irq_mapper:receiver3_irq
+	wire         irq_mapper_receiver4_irq;                               // debug_uart:irq -> irq_mapper:receiver4_irq
+	wire  [31:0] cpu_irq_irq;                                            // irq_mapper:sender_irq -> cpu:irq
+	wire         irq_mapper_receiver2_irq;                               // irq_synchronizer:sender_irq -> irq_mapper:receiver2_irq
+	wire   [0:0] irq_synchronizer_receiver_irq;                          // ext_flash:irq -> irq_synchronizer:receiver_irq
+	wire         udp_generator_data_out_valid;                           // udp_generator:data_out_valid -> avalon_st_adapter:in_0_valid
+	wire  [31:0] udp_generator_data_out_data;                            // udp_generator:data_out_data -> avalon_st_adapter:in_0_data
+	wire         udp_generator_data_out_ready;                           // avalon_st_adapter:in_0_ready -> udp_generator:data_out_ready
+	wire         udp_generator_data_out_startofpacket;                   // udp_generator:data_out_startofpacket -> avalon_st_adapter:in_0_startofpacket
+	wire         udp_generator_data_out_endofpacket;                     // udp_generator:data_out_endofpacket -> avalon_st_adapter:in_0_endofpacket
+	wire   [1:0] udp_generator_data_out_empty;                           // udp_generator:data_out_empty -> avalon_st_adapter:in_0_empty
+	wire         avalon_st_adapter_out_0_valid;                          // avalon_st_adapter:out_0_valid -> tx_multiplexer:in1_valid
+	wire  [31:0] avalon_st_adapter_out_0_data;                           // avalon_st_adapter:out_0_data -> tx_multiplexer:in1_data
+	wire         avalon_st_adapter_out_0_ready;                          // tx_multiplexer:in1_ready -> avalon_st_adapter:out_0_ready
+	wire         avalon_st_adapter_out_0_startofpacket;                  // avalon_st_adapter:out_0_startofpacket -> tx_multiplexer:in1_startofpacket
+	wire         avalon_st_adapter_out_0_endofpacket;                    // avalon_st_adapter:out_0_endofpacket -> tx_multiplexer:in1_endofpacket
+	wire   [0:0] avalon_st_adapter_out_0_error;                          // avalon_st_adapter:out_0_error -> tx_multiplexer:in1_error
+	wire   [1:0] avalon_st_adapter_out_0_empty;                          // avalon_st_adapter:out_0_empty -> tx_multiplexer:in1_empty
+	wire         eth_tse_receive_valid;                                  // eth_tse:ff_rx_dval -> avalon_st_adapter_001:in_0_valid
+	wire  [31:0] eth_tse_receive_data;                                   // eth_tse:ff_rx_data -> avalon_st_adapter_001:in_0_data
+	wire         eth_tse_receive_ready;                                  // avalon_st_adapter_001:in_0_ready -> eth_tse:ff_rx_rdy
+	wire         eth_tse_receive_startofpacket;                          // eth_tse:ff_rx_sop -> avalon_st_adapter_001:in_0_startofpacket
+	wire         eth_tse_receive_endofpacket;                            // eth_tse:ff_rx_eop -> avalon_st_adapter_001:in_0_endofpacket
+	wire   [5:0] eth_tse_receive_error;                                  // eth_tse:rx_err -> avalon_st_adapter_001:in_0_error
+	wire   [1:0] eth_tse_receive_empty;                                  // eth_tse:ff_rx_mod -> avalon_st_adapter_001:in_0_empty
+	wire         avalon_st_adapter_001_out_0_valid;                      // avalon_st_adapter_001:out_0_valid -> msgdma_rx:st_sink_valid
+	wire  [31:0] avalon_st_adapter_001_out_0_data;                       // avalon_st_adapter_001:out_0_data -> msgdma_rx:st_sink_data
+	wire         avalon_st_adapter_001_out_0_ready;                      // msgdma_rx:st_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire         avalon_st_adapter_001_out_0_startofpacket;              // avalon_st_adapter_001:out_0_startofpacket -> msgdma_rx:st_sink_startofpacket
+	wire         avalon_st_adapter_001_out_0_endofpacket;                // avalon_st_adapter_001:out_0_endofpacket -> msgdma_rx:st_sink_endofpacket
+	wire   [5:0] avalon_st_adapter_001_out_0_error;                      // avalon_st_adapter_001:out_0_error -> msgdma_rx:st_sink_error
+	wire   [1:0] avalon_st_adapter_001_out_0_empty;                      // avalon_st_adapter_001:out_0_empty -> msgdma_rx:st_sink_empty
+	wire         rst_controller_reset_out_reset;                         // rst_controller:reset_out -> [altpll_shift:reset, enet_pll:reset]
+	wire         rst_controller_001_reset_out_reset;                     // rst_controller_001:reset_out -> [avalon_st_adapter:in_rst_0_reset, button_pio:reset_n, calibration_ram:reset, calibration_ram:reset2, channel_adapter_0:reset_n, cpu:reset_n, debug_uart:reset_n, frame_timer:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, mm_interconnect_0:sensor_interface_rst_reset_bridge_in_reset_reset, mm_interconnect_1:cpu_reset_reset_bridge_in_reset_reset, msgdma_rx:reset_n_reset_n, msgdma_tx:reset_n_reset_n, onchip_flash:reset_n, rst_translator:in_reset, sensor_interface:rst_reset, tx_multiplexer:reset_n, udp_generator:rst_reset]
+	wire         rst_controller_001_reset_out_reset_req;                 // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in]
+	wire         rst_controller_002_reset_out_reset;                     // rst_controller_002:reset_out -> ddr3_ram:global_reset_n
+	wire         cpu_debug_reset_request_reset;                          // cpu:debug_reset_request -> [rst_controller_002:reset_in0, rst_controller_003:reset_in0, rst_controller_004:reset_in1, rst_controller_005:reset_in1, rst_controller_006:reset_in0]
+	wire         rst_controller_003_reset_out_reset;                     // rst_controller_003:reset_out -> ddr3_ram:soft_reset_n
+	wire         rst_controller_004_reset_out_reset;                     // rst_controller_004:reset_out -> [avalon_st_adapter_001:in_rst_0_reset, descriptor_memory:reset, eth_tse:reset, mm_interconnect_1:eth_tse_reset_connection_reset_bridge_in_reset_reset, output_pio:reset_n, rst_translator_001:in_reset, sys_clk_timer:reset_n, sysid:reset_n]
+	wire         rst_controller_004_reset_out_reset_req;                 // rst_controller_004:reset_req -> [descriptor_memory:reset_req, rst_translator_001:reset_req_in]
+	wire         rst_controller_005_reset_out_reset;                     // rst_controller_005:reset_out -> [ext_flash:reset_n, irq_synchronizer:receiver_reset, mm_interconnect_1:ext_flash_reset_reset_bridge_in_reset_reset]
+	wire         rst_controller_006_reset_out_reset;                     // rst_controller_006:reset_out -> [mm_interconnect_1:ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_1:ddr3_ram_soft_reset_reset_bridge_in_reset_reset]
+
+	q_sys_altpll_shift altpll_shift (
+		.clk                (sys_clk_clk),                        //       inclk_interface.clk
+		.reset              (rst_controller_reset_out_reset),     // inclk_interface_reset.reset
+		.read               (),                                   //             pll_slave.read
+		.write              (),                                   //                      .write
+		.address            (),                                   //                      .address
+		.readdata           (),                                   //                      .readdata
+		.writedata          (),                                   //                      .writedata
+		.c0                 (altpll_shift_c0_clk),                //                    c0.clk
+		.areset             (),                                   //        areset_conduit.export
+		.locked             (altpll_shift_locked_conduit_export), //        locked_conduit.export
+		.scandone           (),                                   //           (terminated)
+		.scandataout        (),                                   //           (terminated)
+		.c3                 (),                                   //           (terminated)
+		.c4                 (),                                   //           (terminated)
+		.phasecounterselect (3'b000),                             //           (terminated)
+		.phaseupdown        (1'b0),                               //           (terminated)
+		.phasestep          (1'b0),                               //           (terminated)
+		.scanclk            (1'b0),                               //           (terminated)
+		.scanclkena         (1'b0),                               //           (terminated)
+		.scandata           (1'b0),                               //           (terminated)
+		.configupdate       (1'b0),                               //           (terminated)
+		.c1                 (),                                   //           (terminated)
+		.c2                 (),                                   //           (terminated)
+		.phasedone          ()                                    //           (terminated)
+	);
+
+	q_sys_button_pio button_pio (
+		.clk      (sys_clk_clk),                              //                 clk.clk
+		.reset_n  (~rst_controller_001_reset_out_reset),      //               reset.reset_n
+		.address  (mm_interconnect_1_button_pio_s1_address),  //                  s1.address
+		.readdata (mm_interconnect_1_button_pio_s1_readdata), //                    .readdata
+		.in_port  (button_pio_external_connection_export)     // external_connection.export
+	);
+
+	q_sys_calibration_ram calibration_ram (
+		.clk         (sys_clk_clk),                                     //   clk1.clk
+		.address     (mm_interconnect_1_calibration_ram_s1_address),    //     s1.address
+		.clken       (mm_interconnect_1_calibration_ram_s1_clken),      //       .clken
+		.chipselect  (mm_interconnect_1_calibration_ram_s1_chipselect), //       .chipselect
+		.write       (mm_interconnect_1_calibration_ram_s1_write),      //       .write
+		.readdata    (mm_interconnect_1_calibration_ram_s1_readdata),   //       .readdata
+		.writedata   (mm_interconnect_1_calibration_ram_s1_writedata),  //       .writedata
+		.byteenable  (mm_interconnect_1_calibration_ram_s1_byteenable), //       .byteenable
+		.reset       (rst_controller_001_reset_out_reset),              // reset1.reset
+		.address2    (mm_interconnect_0_calibration_ram_s2_address),    //     s2.address
+		.chipselect2 (mm_interconnect_0_calibration_ram_s2_chipselect), //       .chipselect
+		.clken2      (mm_interconnect_0_calibration_ram_s2_clken),      //       .clken
+		.write2      (mm_interconnect_0_calibration_ram_s2_write),      //       .write
+		.readdata2   (mm_interconnect_0_calibration_ram_s2_readdata),   //       .readdata
+		.writedata2  (mm_interconnect_0_calibration_ram_s2_writedata),  //       .writedata
+		.byteenable2 (mm_interconnect_0_calibration_ram_s2_byteenable), //       .byteenable
+		.clk2        (sys_clk_clk),                                     //   clk2.clk
+		.reset2      (rst_controller_001_reset_out_reset),              // reset2.reset
+		.reset_req   (1'b0),                                            // (terminated)
+		.freeze      (1'b0),                                            // (terminated)
+		.reset_req2  (1'b0)                                             // (terminated)
+	);
+
+	q_sys_channel_adapter_0 channel_adapter_0 (
+		.clk               (sys_clk_clk),                         //   clk.clk
+		.reset_n           (~rst_controller_001_reset_out_reset), // reset.reset_n
+		.in_data           (tx_multiplexer_out_data),             //    in.data
+		.in_valid          (tx_multiplexer_out_valid),            //      .valid
+		.in_ready          (tx_multiplexer_out_ready),            //      .ready
+		.in_startofpacket  (tx_multiplexer_out_startofpacket),    //      .startofpacket
+		.in_endofpacket    (tx_multiplexer_out_endofpacket),      //      .endofpacket
+		.in_empty          (tx_multiplexer_out_empty),            //      .empty
+		.in_error          (tx_multiplexer_out_error),            //      .error
+		.in_channel        (tx_multiplexer_out_channel),          //      .channel
+		.out_data          (channel_adapter_0_out_data),          //   out.data
+		.out_valid         (channel_adapter_0_out_valid),         //      .valid
+		.out_ready         (channel_adapter_0_out_ready),         //      .ready
+		.out_startofpacket (channel_adapter_0_out_startofpacket), //      .startofpacket
+		.out_endofpacket   (channel_adapter_0_out_endofpacket),   //      .endofpacket
+		.out_empty         (channel_adapter_0_out_empty),         //      .empty
+		.out_error         (channel_adapter_0_out_error)          //      .error
+	);
+
+	q_sys_cpu cpu (
+		.clk                                 (sys_clk_clk),                                       //                       clk.clk
+		.reset_n                             (~rst_controller_001_reset_out_reset),               //                     reset.reset_n
+		.reset_req                           (rst_controller_001_reset_out_reset_req),            //                          .reset_req
+		.d_address                           (cpu_data_master_address),                           //               data_master.address
+		.d_byteenable                        (cpu_data_master_byteenable),                        //                          .byteenable
+		.d_read                              (cpu_data_master_read),                              //                          .read
+		.d_readdata                          (cpu_data_master_readdata),                          //                          .readdata
+		.d_waitrequest                       (cpu_data_master_waitrequest),                       //                          .waitrequest
+		.d_write                             (cpu_data_master_write),                             //                          .write
+		.d_writedata                         (cpu_data_master_writedata),                         //                          .writedata
+		.d_readdatavalid                     (cpu_data_master_readdatavalid),                     //                          .readdatavalid
+		.debug_mem_slave_debugaccess_to_roms (cpu_data_master_debugaccess),                       //                          .debugaccess
+		.i_address                           (cpu_instruction_master_address),                    //        instruction_master.address
+		.i_read                              (cpu_instruction_master_read),                       //                          .read
+		.i_readdata                          (cpu_instruction_master_readdata),                   //                          .readdata
+		.i_waitrequest                       (cpu_instruction_master_waitrequest),                //                          .waitrequest
+		.i_readdatavalid                     (cpu_instruction_master_readdatavalid),              //                          .readdatavalid
+		.irq                                 (cpu_irq_irq),                                       //                       irq.irq
+		.debug_reset_request                 (cpu_debug_reset_request_reset),                     //       debug_reset_request.reset
+		.debug_mem_slave_address             (mm_interconnect_1_cpu_debug_mem_slave_address),     //           debug_mem_slave.address
+		.debug_mem_slave_byteenable          (mm_interconnect_1_cpu_debug_mem_slave_byteenable),  //                          .byteenable
+		.debug_mem_slave_debugaccess         (mm_interconnect_1_cpu_debug_mem_slave_debugaccess), //                          .debugaccess
+		.debug_mem_slave_read                (mm_interconnect_1_cpu_debug_mem_slave_read),        //                          .read
+		.debug_mem_slave_readdata            (mm_interconnect_1_cpu_debug_mem_slave_readdata),    //                          .readdata
+		.debug_mem_slave_waitrequest         (mm_interconnect_1_cpu_debug_mem_slave_waitrequest), //                          .waitrequest
+		.debug_mem_slave_write               (mm_interconnect_1_cpu_debug_mem_slave_write),       //                          .write
+		.debug_mem_slave_writedata           (mm_interconnect_1_cpu_debug_mem_slave_writedata),   //                          .writedata
+		.dummy_ci_port                       ()                                                   // custom_instruction_master.readra
+	);
+
+	q_sys_ddr3_ram ddr3_ram (
+		.pll_ref_clk        (ddr3_ram_pll_ref_clk_clk),                          //      pll_ref_clk.clk
+		.global_reset_n     (~rst_controller_002_reset_out_reset),               //     global_reset.reset_n
+		.soft_reset_n       (~rst_controller_003_reset_out_reset),               //       soft_reset.reset_n
+		.afi_clk            (ddr3_ram_afi_clk_clk),                              //          afi_clk.clk
+		.afi_half_clk       (),                                                  //     afi_half_clk.clk
+		.afi_reset_n        (),                                                  //        afi_reset.reset_n
+		.afi_reset_export_n (),                                                  // afi_reset_export.reset_n
+		.mem_a              (memory_mem_a),                                      //           memory.mem_a
+		.mem_ba             (memory_mem_ba),                                     //                 .mem_ba
+		.mem_ck             (memory_mem_ck),                                     //                 .mem_ck
+		.mem_ck_n           (memory_mem_ck_n),                                   //                 .mem_ck_n
+		.mem_cke            (memory_mem_cke),                                    //                 .mem_cke
+		.mem_cs_n           (memory_mem_cs_n),                                   //                 .mem_cs_n
+		.mem_dm             (memory_mem_dm),                                     //                 .mem_dm
+		.mem_ras_n          (memory_mem_ras_n),                                  //                 .mem_ras_n
+		.mem_cas_n          (memory_mem_cas_n),                                  //                 .mem_cas_n
+		.mem_we_n           (memory_mem_we_n),                                   //                 .mem_we_n
+		.mem_reset_n        (memory_mem_reset_n),                                //                 .mem_reset_n
+		.mem_dq             (memory_mem_dq),                                     //                 .mem_dq
+		.mem_dqs            (memory_mem_dqs),                                    //                 .mem_dqs
+		.mem_dqs_n          (memory_mem_dqs_n),                                  //                 .mem_dqs_n
+		.mem_odt            (memory_mem_odt),                                    //                 .mem_odt
+		.avl_ready          (mm_interconnect_1_ddr3_ram_avl_waitrequest),        //              avl.waitrequest_n
+		.avl_burstbegin     (mm_interconnect_1_ddr3_ram_avl_beginbursttransfer), //                 .beginbursttransfer
+		.avl_addr           (mm_interconnect_1_ddr3_ram_avl_address),            //                 .address
+		.avl_rdata_valid    (mm_interconnect_1_ddr3_ram_avl_readdatavalid),      //                 .readdatavalid
+		.avl_rdata          (mm_interconnect_1_ddr3_ram_avl_readdata),           //                 .readdata
+		.avl_wdata          (mm_interconnect_1_ddr3_ram_avl_writedata),          //                 .writedata
+		.avl_be             (mm_interconnect_1_ddr3_ram_avl_byteenable),         //                 .byteenable
+		.avl_read_req       (mm_interconnect_1_ddr3_ram_avl_read),               //                 .read
+		.avl_write_req      (mm_interconnect_1_ddr3_ram_avl_write),              //                 .write
+		.avl_size           (mm_interconnect_1_ddr3_ram_avl_burstcount),         //                 .burstcount
+		.local_init_done    (mem_if_ddr3_emif_0_status_local_init_done),         //           status.local_init_done
+		.local_cal_success  (mem_if_ddr3_emif_0_status_local_cal_success),       //                 .local_cal_success
+		.local_cal_fail     (mem_if_ddr3_emif_0_status_local_cal_fail),          //                 .local_cal_fail
+		.pll_mem_clk        (),                                                  //      pll_sharing.pll_mem_clk
+		.pll_write_clk      (),                                                  //                 .pll_write_clk
+		.pll_locked         (),                                                  //                 .pll_locked
+		.pll_capture0_clk   (),                                                  //                 .pll_capture0_clk
+		.pll_capture1_clk   ()                                                   //                 .pll_capture1_clk
+	);
+
+	q_sys_debug_uart debug_uart (
+		.clk           (sys_clk_clk),                                   //                 clk.clk
+		.reset_n       (~rst_controller_001_reset_out_reset),           //               reset.reset_n
+		.address       (mm_interconnect_1_debug_uart_s1_address),       //                  s1.address
+		.begintransfer (mm_interconnect_1_debug_uart_s1_begintransfer), //                    .begintransfer
+		.chipselect    (mm_interconnect_1_debug_uart_s1_chipselect),    //                    .chipselect
+		.read_n        (~mm_interconnect_1_debug_uart_s1_read),         //                    .read_n
+		.write_n       (~mm_interconnect_1_debug_uart_s1_write),        //                    .write_n
+		.writedata     (mm_interconnect_1_debug_uart_s1_writedata),     //                    .writedata
+		.readdata      (mm_interconnect_1_debug_uart_s1_readdata),      //                    .readdata
+		.rxd           (debug_uart_external_connection_rxd),            // external_connection.export
+		.txd           (debug_uart_external_connection_txd),            //                    .export
+		.irq           (irq_mapper_receiver4_irq)                       //                 irq.irq
+	);
+
+	q_sys_descriptor_memory descriptor_memory (
+		.clk        (sys_clk_clk),                                       //   clk1.clk
+		.address    (mm_interconnect_1_descriptor_memory_s1_address),    //     s1.address
+		.clken      (mm_interconnect_1_descriptor_memory_s1_clken),      //       .clken
+		.chipselect (mm_interconnect_1_descriptor_memory_s1_chipselect), //       .chipselect
+		.write      (mm_interconnect_1_descriptor_memory_s1_write),      //       .write
+		.readdata   (mm_interconnect_1_descriptor_memory_s1_readdata),   //       .readdata
+		.writedata  (mm_interconnect_1_descriptor_memory_s1_writedata),  //       .writedata
+		.byteenable (mm_interconnect_1_descriptor_memory_s1_byteenable), //       .byteenable
+		.reset      (rst_controller_004_reset_out_reset),                // reset1.reset
+		.reset_req  (rst_controller_004_reset_out_reset_req),            //       .reset_req
+		.freeze     (1'b0)                                               // (terminated)
+	);
+
+	q_sys_enet_pll enet_pll (
+		.clk                (sys_clk_clk),                    //       inclk_interface.clk
+		.reset              (rst_controller_reset_out_reset), // inclk_interface_reset.reset
+		.read               (),                               //             pll_slave.read
+		.write              (),                               //                      .write
+		.address            (),                               //                      .address
+		.readdata           (),                               //                      .readdata
+		.writedata          (),                               //                      .writedata
+		.c0                 (enet_pll_c0_clk),                //                    c0.clk
+		.c1                 (enet_pll_c1_clk),                //                    c1.clk
+		.c2                 (enet_pll_c2_clk),                //                    c2.clk
+		.c3                 (enet_pll_c3_clk),                //                    c3.clk
+		.c4                 (enet_pll_c4_clk),                //                    c4.clk
+		.locked             (enet_pll_locked_conduit_export), //        locked_conduit.export
+		.scandone           (),                               //           (terminated)
+		.scandataout        (),                               //           (terminated)
+		.phasecounterselect (3'b000),                         //           (terminated)
+		.phaseupdown        (1'b0),                           //           (terminated)
+		.phasestep          (1'b0),                           //           (terminated)
+		.scanclk            (1'b0),                           //           (terminated)
+		.scanclkena         (1'b0),                           //           (terminated)
+		.scandata           (1'b0),                           //           (terminated)
+		.configupdate       (1'b0),                           //           (terminated)
+		.areset             (1'b0),                           //           (terminated)
+		.phasedone          ()                                //           (terminated)
+	);
+
+	q_sys_eth_tse eth_tse (
+		.clk           (sys_clk_clk),                                        // control_port_clock_connection.clk
+		.reset         (rst_controller_004_reset_out_reset),                 //              reset_connection.reset
+		.reg_addr      (mm_interconnect_1_eth_tse_control_port_address),     //                  control_port.address
+		.reg_data_out  (mm_interconnect_1_eth_tse_control_port_readdata),    //                              .readdata
+		.reg_rd        (mm_interconnect_1_eth_tse_control_port_read),        //                              .read
+		.reg_data_in   (mm_interconnect_1_eth_tse_control_port_writedata),   //                              .writedata
+		.reg_wr        (mm_interconnect_1_eth_tse_control_port_write),       //                              .write
+		.reg_busy      (mm_interconnect_1_eth_tse_control_port_waitrequest), //                              .waitrequest
+		.tx_clk        (eth_tse_pcs_mac_tx_clock_connection_clk),            //   pcs_mac_tx_clock_connection.clk
+		.rx_clk        (eth_tse_pcs_mac_rx_clock_connection_clk),            //   pcs_mac_rx_clock_connection.clk
+		.set_10        (eth_tse_mac_status_connection_set_10),               //         mac_status_connection.set_10
+		.set_1000      (eth_tse_mac_status_connection_set_1000),             //                              .set_1000
+		.eth_mode      (eth_tse_mac_status_connection_eth_mode),             //                              .eth_mode
+		.ena_10        (eth_tse_mac_status_connection_ena_10),               //                              .ena_10
+		.rgmii_in      (eth_tse_mac_rgmii_connection_rgmii_in),              //          mac_rgmii_connection.rgmii_in
+		.rgmii_out     (eth_tse_mac_rgmii_connection_rgmii_out),             //                              .rgmii_out
+		.rx_control    (eth_tse_mac_rgmii_connection_rx_control),            //                              .rx_control
+		.tx_control    (eth_tse_mac_rgmii_connection_tx_control),            //                              .tx_control
+		.ff_rx_clk     (sys_clk_clk),                                        //      receive_clock_connection.clk
+		.ff_tx_clk     (sys_clk_clk),                                        //     transmit_clock_connection.clk
+		.ff_rx_data    (eth_tse_receive_data),                               //                       receive.data
+		.ff_rx_eop     (eth_tse_receive_endofpacket),                        //                              .endofpacket
+		.rx_err        (eth_tse_receive_error),                              //                              .error
+		.ff_rx_mod     (eth_tse_receive_empty),                              //                              .empty
+		.ff_rx_rdy     (eth_tse_receive_ready),                              //                              .ready
+		.ff_rx_sop     (eth_tse_receive_startofpacket),                      //                              .startofpacket
+		.ff_rx_dval    (eth_tse_receive_valid),                              //                              .valid
+		.ff_tx_data    (channel_adapter_0_out_data),                         //                      transmit.data
+		.ff_tx_eop     (channel_adapter_0_out_endofpacket),                  //                              .endofpacket
+		.ff_tx_err     (channel_adapter_0_out_error),                        //                              .error
+		.ff_tx_mod     (channel_adapter_0_out_empty),                        //                              .empty
+		.ff_tx_rdy     (channel_adapter_0_out_ready),                        //                              .ready
+		.ff_tx_sop     (channel_adapter_0_out_startofpacket),                //                              .startofpacket
+		.ff_tx_wren    (channel_adapter_0_out_valid),                        //                              .valid
+		.mdc           (eth_tse_mac_mdio_connection_mdc),                    //           mac_mdio_connection.mdc
+		.mdio_in       (eth_tse_mac_mdio_connection_mdio_in),                //                              .mdio_in
+		.mdio_out      (eth_tse_mac_mdio_connection_mdio_out),               //                              .mdio_out
+		.mdio_oen      (eth_tse_mac_mdio_connection_mdio_oen),               //                              .mdio_oen
+		.magic_wakeup  (),                                                   //           mac_misc_connection.magic_wakeup
+		.magic_sleep_n (),                                                   //                              .magic_sleep_n
+		.ff_tx_crc_fwd (),                                                   //                              .ff_tx_crc_fwd
+		.ff_tx_septy   (),                                                   //                              .ff_tx_septy
+		.tx_ff_uflow   (),                                                   //                              .tx_ff_uflow
+		.ff_tx_a_full  (),                                                   //                              .ff_tx_a_full
+		.ff_tx_a_empty (),                                                   //                              .ff_tx_a_empty
+		.rx_err_stat   (),                                                   //                              .rx_err_stat
+		.rx_frm_type   (),                                                   //                              .rx_frm_type
+		.ff_rx_dsav    (),                                                   //                              .ff_rx_dsav
+		.ff_rx_a_full  (),                                                   //                              .ff_rx_a_full
+		.ff_rx_a_empty ()                                                    //                              .ff_rx_a_empty
+	);
+
+	q_sys_ext_flash #(
+		.DEVICE_FAMILY     ("MAX 10"),
+		.CS_WIDTH          (1),
+		.ADDR_WIDTH        (24),
+		.ASI_WIDTH         (4),
+		.ASMI_ADDR_WIDTH   (32),
+		.ENABLE_4BYTE_ADDR (1),
+		.IO_MODE           ("QUAD"),
+		.CHIP_SELS         (1)
+	) ext_flash (
+		.clk                  (clock_bridge_0_in_clk_clk),                         //       clock_sink.clk
+		.reset_n              (~rst_controller_005_reset_out_reset),               //            reset.reset_n
+		.avl_csr_read         (mm_interconnect_1_ext_flash_avl_csr_read),          //          avl_csr.read
+		.avl_csr_waitrequest  (mm_interconnect_1_ext_flash_avl_csr_waitrequest),   //                 .waitrequest
+		.avl_csr_write        (mm_interconnect_1_ext_flash_avl_csr_write),         //                 .write
+		.avl_csr_addr         (mm_interconnect_1_ext_flash_avl_csr_address),       //                 .address
+		.avl_csr_wrdata       (mm_interconnect_1_ext_flash_avl_csr_writedata),     //                 .writedata
+		.avl_csr_rddata       (mm_interconnect_1_ext_flash_avl_csr_readdata),      //                 .readdata
+		.avl_csr_rddata_valid (mm_interconnect_1_ext_flash_avl_csr_readdatavalid), //                 .readdatavalid
+		.avl_mem_write        (mm_interconnect_1_ext_flash_avl_mem_write),         //          avl_mem.write
+		.avl_mem_burstcount   (mm_interconnect_1_ext_flash_avl_mem_burstcount),    //                 .burstcount
+		.avl_mem_waitrequest  (mm_interconnect_1_ext_flash_avl_mem_waitrequest),   //                 .waitrequest
+		.avl_mem_read         (mm_interconnect_1_ext_flash_avl_mem_read),          //                 .read
+		.avl_mem_addr         (mm_interconnect_1_ext_flash_avl_mem_address),       //                 .address
+		.avl_mem_wrdata       (mm_interconnect_1_ext_flash_avl_mem_writedata),     //                 .writedata
+		.avl_mem_rddata       (mm_interconnect_1_ext_flash_avl_mem_readdata),      //                 .readdata
+		.avl_mem_rddata_valid (mm_interconnect_1_ext_flash_avl_mem_readdatavalid), //                 .readdatavalid
+		.avl_mem_byteenable   (mm_interconnect_1_ext_flash_avl_mem_byteenable),    //                 .byteenable
+		.irq                  (irq_synchronizer_receiver_irq),                     // interrupt_sender.irq
+		.flash_dataout        (ext_flash_flash_dataout_conduit_dataout),           //    flash_dataout.conduit_dataout
+		.flash_dclk_out       (ext_flash_flash_dclk_out_conduit_dclk_out),         //   flash_dclk_out.conduit_dclk_out
+		.flash_ncs            (ext_flash_flash_ncs_conduit_ncs)                    //        flash_ncs.conduit_ncs
+	);
+
+	q_sys_frame_timer frame_timer (
+		.clk           (sys_clk_clk),                                 //           clk.clk
+		.reset_n       (~rst_controller_001_reset_out_reset),         //         reset.reset_n
+		.address       (mm_interconnect_1_frame_timer_s1_address),    //            s1.address
+		.writedata     (mm_interconnect_1_frame_timer_s1_writedata),  //              .writedata
+		.readdata      (mm_interconnect_1_frame_timer_s1_readdata),   //              .readdata
+		.chipselect    (mm_interconnect_1_frame_timer_s1_chipselect), //              .chipselect
+		.write_n       (~mm_interconnect_1_frame_timer_s1_write),     //              .write_n
+		.irq           (),                                            //           irq.irq
+		.timeout_pulse (frame_timer_export)                           // external_port.export
+	);
+
+	q_sys_msgdma_rx msgdma_rx (
+		.mm_write_address                           (msgdma_rx_mm_write_address),                           //                mm_write.address
+		.mm_write_write                             (msgdma_rx_mm_write_write),                             //                        .write
+		.mm_write_byteenable                        (msgdma_rx_mm_write_byteenable),                        //                        .byteenable
+		.mm_write_writedata                         (msgdma_rx_mm_write_writedata),                         //                        .writedata
+		.mm_write_waitrequest                       (msgdma_rx_mm_write_waitrequest),                       //                        .waitrequest
+		.descriptor_read_master_address             (msgdma_rx_descriptor_read_master_address),             //  descriptor_read_master.address
+		.descriptor_read_master_read                (msgdma_rx_descriptor_read_master_read),                //                        .read
+		.descriptor_read_master_readdata            (msgdma_rx_descriptor_read_master_readdata),            //                        .readdata
+		.descriptor_read_master_waitrequest         (msgdma_rx_descriptor_read_master_waitrequest),         //                        .waitrequest
+		.descriptor_read_master_readdatavalid       (msgdma_rx_descriptor_read_master_readdatavalid),       //                        .readdatavalid
+		.descriptor_write_master_address            (msgdma_rx_descriptor_write_master_address),            // descriptor_write_master.address
+		.descriptor_write_master_write              (msgdma_rx_descriptor_write_master_write),              //                        .write
+		.descriptor_write_master_byteenable         (msgdma_rx_descriptor_write_master_byteenable),         //                        .byteenable
+		.descriptor_write_master_writedata          (msgdma_rx_descriptor_write_master_writedata),          //                        .writedata
+		.descriptor_write_master_waitrequest        (msgdma_rx_descriptor_write_master_waitrequest),        //                        .waitrequest
+		.descriptor_write_master_response           (msgdma_rx_descriptor_write_master_response),           //                        .response
+		.descriptor_write_master_writeresponsevalid (msgdma_rx_descriptor_write_master_writeresponsevalid), //                        .writeresponsevalid
+		.clock_clk                                  (sys_clk_clk),                                          //                   clock.clk
+		.reset_n_reset_n                            (~rst_controller_001_reset_out_reset),                  //                 reset_n.reset_n
+		.csr_writedata                              (mm_interconnect_1_msgdma_rx_csr_writedata),            //                     csr.writedata
+		.csr_write                                  (mm_interconnect_1_msgdma_rx_csr_write),                //                        .write
+		.csr_byteenable                             (mm_interconnect_1_msgdma_rx_csr_byteenable),           //                        .byteenable
+		.csr_readdata                               (mm_interconnect_1_msgdma_rx_csr_readdata),             //                        .readdata
+		.csr_read                                   (mm_interconnect_1_msgdma_rx_csr_read),                 //                        .read
+		.csr_address                                (mm_interconnect_1_msgdma_rx_csr_address),              //                        .address
+		.prefetcher_csr_address                     (mm_interconnect_1_msgdma_rx_prefetcher_csr_address),   //          prefetcher_csr.address
+		.prefetcher_csr_read                        (mm_interconnect_1_msgdma_rx_prefetcher_csr_read),      //                        .read
+		.prefetcher_csr_write                       (mm_interconnect_1_msgdma_rx_prefetcher_csr_write),     //                        .write
+		.prefetcher_csr_writedata                   (mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata), //                        .writedata
+		.prefetcher_csr_readdata                    (mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata),  //                        .readdata
+		.csr_irq_irq                                (irq_mapper_receiver1_irq),                             //                 csr_irq.irq
+		.st_sink_data                               (avalon_st_adapter_001_out_0_data),                     //                 st_sink.data
+		.st_sink_valid                              (avalon_st_adapter_001_out_0_valid),                    //                        .valid
+		.st_sink_ready                              (avalon_st_adapter_001_out_0_ready),                    //                        .ready
+		.st_sink_startofpacket                      (avalon_st_adapter_001_out_0_startofpacket),            //                        .startofpacket
+		.st_sink_endofpacket                        (avalon_st_adapter_001_out_0_endofpacket),              //                        .endofpacket
+		.st_sink_empty                              (avalon_st_adapter_001_out_0_empty),                    //                        .empty
+		.st_sink_error                              (avalon_st_adapter_001_out_0_error)                     //                        .error
+	);
+
+	q_sys_msgdma_tx msgdma_tx (
+		.mm_read_address                            (msgdma_tx_mm_read_address),                            //                 mm_read.address
+		.mm_read_read                               (msgdma_tx_mm_read_read),                               //                        .read
+		.mm_read_byteenable                         (msgdma_tx_mm_read_byteenable),                         //                        .byteenable
+		.mm_read_readdata                           (msgdma_tx_mm_read_readdata),                           //                        .readdata
+		.mm_read_waitrequest                        (msgdma_tx_mm_read_waitrequest),                        //                        .waitrequest
+		.mm_read_readdatavalid                      (msgdma_tx_mm_read_readdatavalid),                      //                        .readdatavalid
+		.descriptor_read_master_address             (msgdma_tx_descriptor_read_master_address),             //  descriptor_read_master.address
+		.descriptor_read_master_read                (msgdma_tx_descriptor_read_master_read),                //                        .read
+		.descriptor_read_master_readdata            (msgdma_tx_descriptor_read_master_readdata),            //                        .readdata
+		.descriptor_read_master_waitrequest         (msgdma_tx_descriptor_read_master_waitrequest),         //                        .waitrequest
+		.descriptor_read_master_readdatavalid       (msgdma_tx_descriptor_read_master_readdatavalid),       //                        .readdatavalid
+		.descriptor_write_master_address            (msgdma_tx_descriptor_write_master_address),            // descriptor_write_master.address
+		.descriptor_write_master_write              (msgdma_tx_descriptor_write_master_write),              //                        .write
+		.descriptor_write_master_byteenable         (msgdma_tx_descriptor_write_master_byteenable),         //                        .byteenable
+		.descriptor_write_master_writedata          (msgdma_tx_descriptor_write_master_writedata),          //                        .writedata
+		.descriptor_write_master_waitrequest        (msgdma_tx_descriptor_write_master_waitrequest),        //                        .waitrequest
+		.descriptor_write_master_response           (msgdma_tx_descriptor_write_master_response),           //                        .response
+		.descriptor_write_master_writeresponsevalid (msgdma_tx_descriptor_write_master_writeresponsevalid), //                        .writeresponsevalid
+		.clock_clk                                  (sys_clk_clk),                                          //                   clock.clk
+		.reset_n_reset_n                            (~rst_controller_001_reset_out_reset),                  //                 reset_n.reset_n
+		.csr_writedata                              (mm_interconnect_1_msgdma_tx_csr_writedata),            //                     csr.writedata
+		.csr_write                                  (mm_interconnect_1_msgdma_tx_csr_write),                //                        .write
+		.csr_byteenable                             (mm_interconnect_1_msgdma_tx_csr_byteenable),           //                        .byteenable
+		.csr_readdata                               (mm_interconnect_1_msgdma_tx_csr_readdata),             //                        .readdata
+		.csr_read                                   (mm_interconnect_1_msgdma_tx_csr_read),                 //                        .read
+		.csr_address                                (mm_interconnect_1_msgdma_tx_csr_address),              //                        .address
+		.prefetcher_csr_address                     (mm_interconnect_1_msgdma_tx_prefetcher_csr_address),   //          prefetcher_csr.address
+		.prefetcher_csr_read                        (mm_interconnect_1_msgdma_tx_prefetcher_csr_read),      //                        .read
+		.prefetcher_csr_write                       (mm_interconnect_1_msgdma_tx_prefetcher_csr_write),     //                        .write
+		.prefetcher_csr_writedata                   (mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata), //                        .writedata
+		.prefetcher_csr_readdata                    (mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata),  //                        .readdata
+		.csr_irq_irq                                (irq_mapper_receiver0_irq),                             //                 csr_irq.irq
+		.st_source_data                             (msgdma_tx_st_source_data),                             //               st_source.data
+		.st_source_valid                            (msgdma_tx_st_source_valid),                            //                        .valid
+		.st_source_ready                            (msgdma_tx_st_source_ready),                            //                        .ready
+		.st_source_startofpacket                    (msgdma_tx_st_source_startofpacket),                    //                        .startofpacket
+		.st_source_endofpacket                      (msgdma_tx_st_source_endofpacket),                      //                        .endofpacket
+		.st_source_empty                            (msgdma_tx_st_source_empty),                            //                        .empty
+		.st_source_error                            (msgdma_tx_st_source_error)                             //                        .error
+	);
+
+	altera_onchip_flash #(
+		.INIT_FILENAME                       (""),
+		.INIT_FILENAME_SIM                   (""),
+		.DEVICE_FAMILY                       ("MAX 10"),
+		.PART_NAME                           ("10M50DAF484C6GES"),
+		.DEVICE_ID                           ("50"),
+		.SECTOR1_START_ADDR                  (0),
+		.SECTOR1_END_ADDR                    (8191),
+		.SECTOR2_START_ADDR                  (8192),
+		.SECTOR2_END_ADDR                    (16383),
+		.SECTOR3_START_ADDR                  (16384),
+		.SECTOR3_END_ADDR                    (114687),
+		.SECTOR4_START_ADDR                  (114688),
+		.SECTOR4_END_ADDR                    (188415),
+		.SECTOR5_START_ADDR                  (188416),
+		.SECTOR5_END_ADDR                    (360447),
+		.MIN_VALID_ADDR                      (0),
+		.MAX_VALID_ADDR                      (360447),
+		.MIN_UFM_VALID_ADDR                  (0),
+		.MAX_UFM_VALID_ADDR                  (114687),
+		.SECTOR1_MAP                         (1),
+		.SECTOR2_MAP                         (2),
+		.SECTOR3_MAP                         (3),
+		.SECTOR4_MAP                         (4),
+		.SECTOR5_MAP                         (5),
+		.ADDR_RANGE1_END_ADDR                (360447),
+		.ADDR_RANGE2_END_ADDR                (360447),
+		.ADDR_RANGE1_OFFSET                  (2048),
+		.ADDR_RANGE2_OFFSET                  (0),
+		.ADDR_RANGE3_OFFSET                  (0),
+		.AVMM_DATA_ADDR_WIDTH                (19),
+		.AVMM_DATA_DATA_WIDTH                (32),
+		.AVMM_DATA_BURSTCOUNT_WIDTH          (4),
+		.SECTOR_READ_PROTECTION_MODE         (0),
+		.FLASH_SEQ_READ_DATA_COUNT           (4),
+		.FLASH_ADDR_ALIGNMENT_BITS           (2),
+		.FLASH_READ_CYCLE_MAX_INDEX          (5),
+		.FLASH_RESET_CYCLE_MAX_INDEX         (12),
+		.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  (60),
+		.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (17500000),
+		.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (15250),
+		.PARALLEL_MODE                       (1),
+		.READ_AND_WRITE_MODE                 (1),
+		.WRAPPING_BURST_MODE                 (0),
+		.IS_DUAL_BOOT                        ("False"),
+		.IS_ERAM_SKIP                        ("True"),
+		.IS_COMPRESSED_IMAGE                 ("False")
+	) onchip_flash (
+		.clock                   (sys_clk_clk),                                       //    clk.clk
+		.reset_n                 (~rst_controller_001_reset_out_reset),               // nreset.reset_n
+		.avmm_data_addr          (mm_interconnect_1_onchip_flash_data_address),       //   data.address
+		.avmm_data_read          (mm_interconnect_1_onchip_flash_data_read),          //       .read
+		.avmm_data_writedata     (mm_interconnect_1_onchip_flash_data_writedata),     //       .writedata
+		.avmm_data_write         (mm_interconnect_1_onchip_flash_data_write),         //       .write
+		.avmm_data_readdata      (mm_interconnect_1_onchip_flash_data_readdata),      //       .readdata
+		.avmm_data_waitrequest   (mm_interconnect_1_onchip_flash_data_waitrequest),   //       .waitrequest
+		.avmm_data_readdatavalid (mm_interconnect_1_onchip_flash_data_readdatavalid), //       .readdatavalid
+		.avmm_data_burstcount    (mm_interconnect_1_onchip_flash_data_burstcount),    //       .burstcount
+		.avmm_csr_addr           (mm_interconnect_1_onchip_flash_csr_address),        //    csr.address
+		.avmm_csr_read           (mm_interconnect_1_onchip_flash_csr_read),           //       .read
+		.avmm_csr_writedata      (mm_interconnect_1_onchip_flash_csr_writedata),      //       .writedata
+		.avmm_csr_write          (mm_interconnect_1_onchip_flash_csr_write),          //       .write
+		.avmm_csr_readdata       (mm_interconnect_1_onchip_flash_csr_readdata)        //       .readdata
+	);
+
+	q_sys_output_pio output_pio (
+		.clk        (sys_clk_clk),                                //                 clk.clk
+		.reset_n    (~rst_controller_004_reset_out_reset),        //               reset.reset_n
+		.address    (mm_interconnect_1_output_pio_s1_address),    //                  s1.address
+		.write_n    (~mm_interconnect_1_output_pio_s1_write),     //                    .write_n
+		.writedata  (mm_interconnect_1_output_pio_s1_writedata),  //                    .writedata
+		.chipselect (mm_interconnect_1_output_pio_s1_chipselect), //                    .chipselect
+		.readdata   (mm_interconnect_1_output_pio_s1_readdata),   //                    .readdata
+		.out_port   (led_pio_external_connection_export)          // external_connection.export
+	);
+
+	sensor_algo sensor_interface (
+		.csr_address            (mm_interconnect_1_sensor_interface_csr_address),         //                       csr.address
+		.csr_read               (mm_interconnect_1_sensor_interface_csr_read),            //                          .read
+		.csr_readdata           (mm_interconnect_1_sensor_interface_csr_readdata),        //                          .readdata
+		.csr_write              (mm_interconnect_1_sensor_interface_csr_write),           //                          .write
+		.csr_writedata          (mm_interconnect_1_sensor_interface_csr_writedata),       //                          .writedata
+		.csr_byteenable         (mm_interconnect_1_sensor_interface_csr_byteenable),      //                          .byteenable
+		.data_out_endofpacket   (sensor_interface_data_out_endofpacket),                  //                  data_out.endofpacket
+		.data_out_data          (sensor_interface_data_out_data),                         //                          .data
+		.data_out_empty         (sensor_interface_data_out_empty),                        //                          .empty
+		.data_out_ready         (sensor_interface_data_out_ready),                        //                          .ready
+		.data_out_startofpacket (sensor_interface_data_out_startofpacket),                //                          .startofpacket
+		.data_out_valid         (sensor_interface_data_out_valid),                        //                          .valid
+		.clk_clk                (sys_clk_clk),                                            //                       clk.clk
+		.rst_reset              (rst_controller_001_reset_out_reset),                     //                       rst.reset
+		.in_adc_data            (sensor_in_adc_data),                                     //                    sensor.in_adc_data
+		.in_trg                 (sensor_in_trg),                                          //                          .in_trg
+		.out_adc_clk            (sensor_out_adc_clk),                                     //                          .out_adc_clk
+		.out_adc_cnv            (sensor_out_adc_cnv),                                     //                          .out_adc_cnv
+		.out_sensor_clk         (sensor_out_sensor_clk),                                  //                          .out_sensor_clk
+		.out_sensor_gain        (sensor_out_sensor_gain),                                 //                          .out_sensor_gain
+		.out_sensor_rst         (sensor_out_sensor_rst),                                  //                          .out_sensor_rst
+		.status_out             (sensor_status_status_out),                               //                status_out.status_out
+		.ext_input              (sensor_synchro_ext_input),                               //                   synchro.ext_input
+		.serial_rx              (sensor_synchro_serial_rx),                               //                          .serial_rx
+		.serial_tx              (sensor_synchro_serial_tx),                               //                          .serial_tx
+		.address                (sensor_interface_calibration_ram_interface_address),     // calibration_ram_interface.address
+		.clken                  (sensor_interface_calibration_ram_interface_read),        //                          .read
+		.cali_fac               (sensor_interface_calibration_ram_interface_readdata),    //                          .readdata
+		.waitrequest            (sensor_interface_calibration_ram_interface_waitrequest)  //                          .waitrequest
+	);
+
+	q_sys_sys_clk_timer sys_clk_timer (
+		.clk        (sys_clk_clk),                                   //   clk.clk
+		.reset_n    (~rst_controller_004_reset_out_reset),           // reset.reset_n
+		.address    (mm_interconnect_1_sys_clk_timer_s1_address),    //    s1.address
+		.writedata  (mm_interconnect_1_sys_clk_timer_s1_writedata),  //      .writedata
+		.readdata   (mm_interconnect_1_sys_clk_timer_s1_readdata),   //      .readdata
+		.chipselect (mm_interconnect_1_sys_clk_timer_s1_chipselect), //      .chipselect
+		.write_n    (~mm_interconnect_1_sys_clk_timer_s1_write),     //      .write_n
+		.irq        (irq_mapper_receiver3_irq)                       //   irq.irq
+	);
+
+	q_sys_sysid sysid (
+		.clock    (sys_clk_clk),                                    //           clk.clk
+		.reset_n  (~rst_controller_004_reset_out_reset),            //         reset.reset_n
+		.readdata (mm_interconnect_1_sysid_control_slave_readdata), // control_slave.readdata
+		.address  (mm_interconnect_1_sysid_control_slave_address)   //              .address
+	);
+
+	q_sys_tx_multiplexer tx_multiplexer (
+		.clk               (sys_clk_clk),                           //   clk.clk
+		.reset_n           (~rst_controller_001_reset_out_reset),   // reset.reset_n
+		.out_data          (tx_multiplexer_out_data),               //   out.data
+		.out_valid         (tx_multiplexer_out_valid),              //      .valid
+		.out_ready         (tx_multiplexer_out_ready),              //      .ready
+		.out_startofpacket (tx_multiplexer_out_startofpacket),      //      .startofpacket
+		.out_endofpacket   (tx_multiplexer_out_endofpacket),        //      .endofpacket
+		.out_empty         (tx_multiplexer_out_empty),              //      .empty
+		.out_error         (tx_multiplexer_out_error),              //      .error
+		.out_channel       (tx_multiplexer_out_channel),            //      .channel
+		.in0_data          (msgdma_tx_st_source_data),              //   in0.data
+		.in0_valid         (msgdma_tx_st_source_valid),             //      .valid
+		.in0_ready         (msgdma_tx_st_source_ready),             //      .ready
+		.in0_startofpacket (msgdma_tx_st_source_startofpacket),     //      .startofpacket
+		.in0_endofpacket   (msgdma_tx_st_source_endofpacket),       //      .endofpacket
+		.in0_empty         (msgdma_tx_st_source_empty),             //      .empty
+		.in0_error         (msgdma_tx_st_source_error),             //      .error
+		.in1_data          (avalon_st_adapter_out_0_data),          //   in1.data
+		.in1_valid         (avalon_st_adapter_out_0_valid),         //      .valid
+		.in1_ready         (avalon_st_adapter_out_0_ready),         //      .ready
+		.in1_startofpacket (avalon_st_adapter_out_0_startofpacket), //      .startofpacket
+		.in1_endofpacket   (avalon_st_adapter_out_0_endofpacket),   //      .endofpacket
+		.in1_empty         (avalon_st_adapter_out_0_empty),         //      .empty
+		.in1_error         (avalon_st_adapter_out_0_error)          //      .error
+	);
+
+	udp_generator udp_generator (
+		.clk_clk                (sys_clk_clk),                                    //      clk.clk
+		.rst_reset              (rst_controller_001_reset_out_reset),             //      rst.reset
+		.csr_address            (mm_interconnect_1_udp_generator_csr_address),    //      csr.address
+		.csr_write              (mm_interconnect_1_udp_generator_csr_write),      //         .write
+		.csr_writedata          (mm_interconnect_1_udp_generator_csr_writedata),  //         .writedata
+		.csr_byteenable         (mm_interconnect_1_udp_generator_csr_byteenable), //         .byteenable
+		.csr_read               (mm_interconnect_1_udp_generator_csr_read),       //         .read
+		.csr_readdata           (mm_interconnect_1_udp_generator_csr_readdata),   //         .readdata
+		.data_in_data           (sensor_interface_data_out_data),                 //  data_in.data
+		.data_in_ready          (sensor_interface_data_out_ready),                //         .ready
+		.data_in_valid          (sensor_interface_data_out_valid),                //         .valid
+		.data_in_empty          (sensor_interface_data_out_empty),                //         .empty
+		.data_in_endofpacket    (sensor_interface_data_out_endofpacket),          //         .endofpacket
+		.data_in_startofpacket  (sensor_interface_data_out_startofpacket),        //         .startofpacket
+		.data_out_data          (udp_generator_data_out_data),                    // data_out.data
+		.data_out_empty         (udp_generator_data_out_empty),                   //         .empty
+		.data_out_endofpacket   (udp_generator_data_out_endofpacket),             //         .endofpacket
+		.data_out_startofpacket (udp_generator_data_out_startofpacket),           //         .startofpacket
+		.data_out_ready         (udp_generator_data_out_ready),                   //         .ready
+		.data_out_valid         (udp_generator_data_out_valid)                    //         .valid
+	);
+
+	q_sys_mm_interconnect_0 mm_interconnect_0 (
+		.sys_clk_clk_clk                                        (sys_clk_clk),                                            //                                sys_clk_clk.clk
+		.sensor_interface_rst_reset_bridge_in_reset_reset       (rst_controller_001_reset_out_reset),                     // sensor_interface_rst_reset_bridge_in_reset.reset
+		.sensor_interface_calibration_ram_interface_address     (sensor_interface_calibration_ram_interface_address),     // sensor_interface_calibration_ram_interface.address
+		.sensor_interface_calibration_ram_interface_waitrequest (sensor_interface_calibration_ram_interface_waitrequest), //                                           .waitrequest
+		.sensor_interface_calibration_ram_interface_read        (sensor_interface_calibration_ram_interface_read),        //                                           .read
+		.sensor_interface_calibration_ram_interface_readdata    (sensor_interface_calibration_ram_interface_readdata),    //                                           .readdata
+		.calibration_ram_s2_address                             (mm_interconnect_0_calibration_ram_s2_address),           //                         calibration_ram_s2.address
+		.calibration_ram_s2_write                               (mm_interconnect_0_calibration_ram_s2_write),             //                                           .write
+		.calibration_ram_s2_readdata                            (mm_interconnect_0_calibration_ram_s2_readdata),          //                                           .readdata
+		.calibration_ram_s2_writedata                           (mm_interconnect_0_calibration_ram_s2_writedata),         //                                           .writedata
+		.calibration_ram_s2_byteenable                          (mm_interconnect_0_calibration_ram_s2_byteenable),        //                                           .byteenable
+		.calibration_ram_s2_chipselect                          (mm_interconnect_0_calibration_ram_s2_chipselect),        //                                           .chipselect
+		.calibration_ram_s2_clken                               (mm_interconnect_0_calibration_ram_s2_clken)              //                                           .clken
+	);
+
+	q_sys_mm_interconnect_1 mm_interconnect_1 (
+		.ddr3_ram_afi_clk_clk                                      (ddr3_ram_afi_clk_clk),                                 //                                    ddr3_ram_afi_clk.clk
+		.ext_flash_clock_bridge_out_clk_clk                        (clock_bridge_0_in_clk_clk),                            //                      ext_flash_clock_bridge_out_clk.clk
+		.sys_clk_clk_clk                                           (sys_clk_clk),                                          //                                         sys_clk_clk.clk
+		.cpu_reset_reset_bridge_in_reset_reset                     (rst_controller_001_reset_out_reset),                   //                     cpu_reset_reset_bridge_in_reset.reset
+		.ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset (rst_controller_006_reset_out_reset),                   // ddr3_ram_avl_translator_reset_reset_bridge_in_reset.reset
+		.ddr3_ram_soft_reset_reset_bridge_in_reset_reset           (rst_controller_006_reset_out_reset),                   //           ddr3_ram_soft_reset_reset_bridge_in_reset.reset
+		.eth_tse_reset_connection_reset_bridge_in_reset_reset      (rst_controller_004_reset_out_reset),                   //      eth_tse_reset_connection_reset_bridge_in_reset.reset
+		.ext_flash_reset_reset_bridge_in_reset_reset               (rst_controller_005_reset_out_reset),                   //               ext_flash_reset_reset_bridge_in_reset.reset
+		.cpu_data_master_address                                   (cpu_data_master_address),                              //                                     cpu_data_master.address
+		.cpu_data_master_waitrequest                               (cpu_data_master_waitrequest),                          //                                                    .waitrequest
+		.cpu_data_master_byteenable                                (cpu_data_master_byteenable),                           //                                                    .byteenable
+		.cpu_data_master_read                                      (cpu_data_master_read),                                 //                                                    .read
+		.cpu_data_master_readdata                                  (cpu_data_master_readdata),                             //                                                    .readdata
+		.cpu_data_master_readdatavalid                             (cpu_data_master_readdatavalid),                        //                                                    .readdatavalid
+		.cpu_data_master_write                                     (cpu_data_master_write),                                //                                                    .write
+		.cpu_data_master_writedata                                 (cpu_data_master_writedata),                            //                                                    .writedata
+		.cpu_data_master_debugaccess                               (cpu_data_master_debugaccess),                          //                                                    .debugaccess
+		.cpu_instruction_master_address                            (cpu_instruction_master_address),                       //                              cpu_instruction_master.address
+		.cpu_instruction_master_waitrequest                        (cpu_instruction_master_waitrequest),                   //                                                    .waitrequest
+		.cpu_instruction_master_read                               (cpu_instruction_master_read),                          //                                                    .read
+		.cpu_instruction_master_readdata                           (cpu_instruction_master_readdata),                      //                                                    .readdata
+		.cpu_instruction_master_readdatavalid                      (cpu_instruction_master_readdatavalid),                 //                                                    .readdatavalid
+		.msgdma_rx_descriptor_read_master_address                  (msgdma_rx_descriptor_read_master_address),             //                    msgdma_rx_descriptor_read_master.address
+		.msgdma_rx_descriptor_read_master_waitrequest              (msgdma_rx_descriptor_read_master_waitrequest),         //                                                    .waitrequest
+		.msgdma_rx_descriptor_read_master_read                     (msgdma_rx_descriptor_read_master_read),                //                                                    .read
+		.msgdma_rx_descriptor_read_master_readdata                 (msgdma_rx_descriptor_read_master_readdata),            //                                                    .readdata
+		.msgdma_rx_descriptor_read_master_readdatavalid            (msgdma_rx_descriptor_read_master_readdatavalid),       //                                                    .readdatavalid
+		.msgdma_rx_descriptor_write_master_address                 (msgdma_rx_descriptor_write_master_address),            //                   msgdma_rx_descriptor_write_master.address
+		.msgdma_rx_descriptor_write_master_waitrequest             (msgdma_rx_descriptor_write_master_waitrequest),        //                                                    .waitrequest
+		.msgdma_rx_descriptor_write_master_byteenable              (msgdma_rx_descriptor_write_master_byteenable),         //                                                    .byteenable
+		.msgdma_rx_descriptor_write_master_write                   (msgdma_rx_descriptor_write_master_write),              //                                                    .write
+		.msgdma_rx_descriptor_write_master_writedata               (msgdma_rx_descriptor_write_master_writedata),          //                                                    .writedata
+		.msgdma_rx_descriptor_write_master_response                (msgdma_rx_descriptor_write_master_response),           //                                                    .response
+		.msgdma_rx_descriptor_write_master_writeresponsevalid      (msgdma_rx_descriptor_write_master_writeresponsevalid), //                                                    .writeresponsevalid
+		.msgdma_rx_mm_write_address                                (msgdma_rx_mm_write_address),                           //                                  msgdma_rx_mm_write.address
+		.msgdma_rx_mm_write_waitrequest                            (msgdma_rx_mm_write_waitrequest),                       //                                                    .waitrequest
+		.msgdma_rx_mm_write_byteenable                             (msgdma_rx_mm_write_byteenable),                        //                                                    .byteenable
+		.msgdma_rx_mm_write_write                                  (msgdma_rx_mm_write_write),                             //                                                    .write
+		.msgdma_rx_mm_write_writedata                              (msgdma_rx_mm_write_writedata),                         //                                                    .writedata
+		.msgdma_tx_descriptor_read_master_address                  (msgdma_tx_descriptor_read_master_address),             //                    msgdma_tx_descriptor_read_master.address
+		.msgdma_tx_descriptor_read_master_waitrequest              (msgdma_tx_descriptor_read_master_waitrequest),         //                                                    .waitrequest
+		.msgdma_tx_descriptor_read_master_read                     (msgdma_tx_descriptor_read_master_read),                //                                                    .read
+		.msgdma_tx_descriptor_read_master_readdata                 (msgdma_tx_descriptor_read_master_readdata),            //                                                    .readdata
+		.msgdma_tx_descriptor_read_master_readdatavalid            (msgdma_tx_descriptor_read_master_readdatavalid),       //                                                    .readdatavalid
+		.msgdma_tx_descriptor_write_master_address                 (msgdma_tx_descriptor_write_master_address),            //                   msgdma_tx_descriptor_write_master.address
+		.msgdma_tx_descriptor_write_master_waitrequest             (msgdma_tx_descriptor_write_master_waitrequest),        //                                                    .waitrequest
+		.msgdma_tx_descriptor_write_master_byteenable              (msgdma_tx_descriptor_write_master_byteenable),         //                                                    .byteenable
+		.msgdma_tx_descriptor_write_master_write                   (msgdma_tx_descriptor_write_master_write),              //                                                    .write
+		.msgdma_tx_descriptor_write_master_writedata               (msgdma_tx_descriptor_write_master_writedata),          //                                                    .writedata
+		.msgdma_tx_descriptor_write_master_response                (msgdma_tx_descriptor_write_master_response),           //                                                    .response
+		.msgdma_tx_descriptor_write_master_writeresponsevalid      (msgdma_tx_descriptor_write_master_writeresponsevalid), //                                                    .writeresponsevalid
+		.msgdma_tx_mm_read_address                                 (msgdma_tx_mm_read_address),                            //                                   msgdma_tx_mm_read.address
+		.msgdma_tx_mm_read_waitrequest                             (msgdma_tx_mm_read_waitrequest),                        //                                                    .waitrequest
+		.msgdma_tx_mm_read_byteenable                              (msgdma_tx_mm_read_byteenable),                         //                                                    .byteenable
+		.msgdma_tx_mm_read_read                                    (msgdma_tx_mm_read_read),                               //                                                    .read
+		.msgdma_tx_mm_read_readdata                                (msgdma_tx_mm_read_readdata),                           //                                                    .readdata
+		.msgdma_tx_mm_read_readdatavalid                           (msgdma_tx_mm_read_readdatavalid),                      //                                                    .readdatavalid
+		.button_pio_s1_address                                     (mm_interconnect_1_button_pio_s1_address),              //                                       button_pio_s1.address
+		.button_pio_s1_readdata                                    (mm_interconnect_1_button_pio_s1_readdata),             //                                                    .readdata
+		.calibration_ram_s1_address                                (mm_interconnect_1_calibration_ram_s1_address),         //                                  calibration_ram_s1.address
+		.calibration_ram_s1_write                                  (mm_interconnect_1_calibration_ram_s1_write),           //                                                    .write
+		.calibration_ram_s1_readdata                               (mm_interconnect_1_calibration_ram_s1_readdata),        //                                                    .readdata
+		.calibration_ram_s1_writedata                              (mm_interconnect_1_calibration_ram_s1_writedata),       //                                                    .writedata
+		.calibration_ram_s1_byteenable                             (mm_interconnect_1_calibration_ram_s1_byteenable),      //                                                    .byteenable
+		.calibration_ram_s1_chipselect                             (mm_interconnect_1_calibration_ram_s1_chipselect),      //                                                    .chipselect
+		.calibration_ram_s1_clken                                  (mm_interconnect_1_calibration_ram_s1_clken),           //                                                    .clken
+		.cpu_debug_mem_slave_address                               (mm_interconnect_1_cpu_debug_mem_slave_address),        //                                 cpu_debug_mem_slave.address
+		.cpu_debug_mem_slave_write                                 (mm_interconnect_1_cpu_debug_mem_slave_write),          //                                                    .write
+		.cpu_debug_mem_slave_read                                  (mm_interconnect_1_cpu_debug_mem_slave_read),           //                                                    .read
+		.cpu_debug_mem_slave_readdata                              (mm_interconnect_1_cpu_debug_mem_slave_readdata),       //                                                    .readdata
+		.cpu_debug_mem_slave_writedata                             (mm_interconnect_1_cpu_debug_mem_slave_writedata),      //                                                    .writedata
+		.cpu_debug_mem_slave_byteenable                            (mm_interconnect_1_cpu_debug_mem_slave_byteenable),     //                                                    .byteenable
+		.cpu_debug_mem_slave_waitrequest                           (mm_interconnect_1_cpu_debug_mem_slave_waitrequest),    //                                                    .waitrequest
+		.cpu_debug_mem_slave_debugaccess                           (mm_interconnect_1_cpu_debug_mem_slave_debugaccess),    //                                                    .debugaccess
+		.ddr3_ram_avl_address                                      (mm_interconnect_1_ddr3_ram_avl_address),               //                                        ddr3_ram_avl.address
+		.ddr3_ram_avl_write                                        (mm_interconnect_1_ddr3_ram_avl_write),                 //                                                    .write
+		.ddr3_ram_avl_read                                         (mm_interconnect_1_ddr3_ram_avl_read),                  //                                                    .read
+		.ddr3_ram_avl_readdata                                     (mm_interconnect_1_ddr3_ram_avl_readdata),              //                                                    .readdata
+		.ddr3_ram_avl_writedata                                    (mm_interconnect_1_ddr3_ram_avl_writedata),             //                                                    .writedata
+		.ddr3_ram_avl_beginbursttransfer                           (mm_interconnect_1_ddr3_ram_avl_beginbursttransfer),    //                                                    .beginbursttransfer
+		.ddr3_ram_avl_burstcount                                   (mm_interconnect_1_ddr3_ram_avl_burstcount),            //                                                    .burstcount
+		.ddr3_ram_avl_byteenable                                   (mm_interconnect_1_ddr3_ram_avl_byteenable),            //                                                    .byteenable
+		.ddr3_ram_avl_readdatavalid                                (mm_interconnect_1_ddr3_ram_avl_readdatavalid),         //                                                    .readdatavalid
+		.ddr3_ram_avl_waitrequest                                  (~mm_interconnect_1_ddr3_ram_avl_waitrequest),          //                                                    .waitrequest
+		.debug_uart_s1_address                                     (mm_interconnect_1_debug_uart_s1_address),              //                                       debug_uart_s1.address
+		.debug_uart_s1_write                                       (mm_interconnect_1_debug_uart_s1_write),                //                                                    .write
+		.debug_uart_s1_read                                        (mm_interconnect_1_debug_uart_s1_read),                 //                                                    .read
+		.debug_uart_s1_readdata                                    (mm_interconnect_1_debug_uart_s1_readdata),             //                                                    .readdata
+		.debug_uart_s1_writedata                                   (mm_interconnect_1_debug_uart_s1_writedata),            //                                                    .writedata
+		.debug_uart_s1_begintransfer                               (mm_interconnect_1_debug_uart_s1_begintransfer),        //                                                    .begintransfer
+		.debug_uart_s1_chipselect                                  (mm_interconnect_1_debug_uart_s1_chipselect),           //                                                    .chipselect
+		.descriptor_memory_s1_address                              (mm_interconnect_1_descriptor_memory_s1_address),       //                                descriptor_memory_s1.address
+		.descriptor_memory_s1_write                                (mm_interconnect_1_descriptor_memory_s1_write),         //                                                    .write
+		.descriptor_memory_s1_readdata                             (mm_interconnect_1_descriptor_memory_s1_readdata),      //                                                    .readdata
+		.descriptor_memory_s1_writedata                            (mm_interconnect_1_descriptor_memory_s1_writedata),     //                                                    .writedata
+		.descriptor_memory_s1_byteenable                           (mm_interconnect_1_descriptor_memory_s1_byteenable),    //                                                    .byteenable
+		.descriptor_memory_s1_chipselect                           (mm_interconnect_1_descriptor_memory_s1_chipselect),    //                                                    .chipselect
+		.descriptor_memory_s1_clken                                (mm_interconnect_1_descriptor_memory_s1_clken),         //                                                    .clken
+		.eth_tse_control_port_address                              (mm_interconnect_1_eth_tse_control_port_address),       //                                eth_tse_control_port.address
+		.eth_tse_control_port_write                                (mm_interconnect_1_eth_tse_control_port_write),         //                                                    .write
+		.eth_tse_control_port_read                                 (mm_interconnect_1_eth_tse_control_port_read),          //                                                    .read
+		.eth_tse_control_port_readdata                             (mm_interconnect_1_eth_tse_control_port_readdata),      //                                                    .readdata
+		.eth_tse_control_port_writedata                            (mm_interconnect_1_eth_tse_control_port_writedata),     //                                                    .writedata
+		.eth_tse_control_port_waitrequest                          (mm_interconnect_1_eth_tse_control_port_waitrequest),   //                                                    .waitrequest
+		.ext_flash_avl_csr_address                                 (mm_interconnect_1_ext_flash_avl_csr_address),          //                                   ext_flash_avl_csr.address
+		.ext_flash_avl_csr_write                                   (mm_interconnect_1_ext_flash_avl_csr_write),            //                                                    .write
+		.ext_flash_avl_csr_read                                    (mm_interconnect_1_ext_flash_avl_csr_read),             //                                                    .read
+		.ext_flash_avl_csr_readdata                                (mm_interconnect_1_ext_flash_avl_csr_readdata),         //                                                    .readdata
+		.ext_flash_avl_csr_writedata                               (mm_interconnect_1_ext_flash_avl_csr_writedata),        //                                                    .writedata
+		.ext_flash_avl_csr_readdatavalid                           (mm_interconnect_1_ext_flash_avl_csr_readdatavalid),    //                                                    .readdatavalid
+		.ext_flash_avl_csr_waitrequest                             (mm_interconnect_1_ext_flash_avl_csr_waitrequest),      //                                                    .waitrequest
+		.ext_flash_avl_mem_address                                 (mm_interconnect_1_ext_flash_avl_mem_address),          //                                   ext_flash_avl_mem.address
+		.ext_flash_avl_mem_write                                   (mm_interconnect_1_ext_flash_avl_mem_write),            //                                                    .write
+		.ext_flash_avl_mem_read                                    (mm_interconnect_1_ext_flash_avl_mem_read),             //                                                    .read
+		.ext_flash_avl_mem_readdata                                (mm_interconnect_1_ext_flash_avl_mem_readdata),         //                                                    .readdata
+		.ext_flash_avl_mem_writedata                               (mm_interconnect_1_ext_flash_avl_mem_writedata),        //                                                    .writedata
+		.ext_flash_avl_mem_burstcount                              (mm_interconnect_1_ext_flash_avl_mem_burstcount),       //                                                    .burstcount
+		.ext_flash_avl_mem_byteenable                              (mm_interconnect_1_ext_flash_avl_mem_byteenable),       //                                                    .byteenable
+		.ext_flash_avl_mem_readdatavalid                           (mm_interconnect_1_ext_flash_avl_mem_readdatavalid),    //                                                    .readdatavalid
+		.ext_flash_avl_mem_waitrequest                             (mm_interconnect_1_ext_flash_avl_mem_waitrequest),      //                                                    .waitrequest
+		.frame_timer_s1_address                                    (mm_interconnect_1_frame_timer_s1_address),             //                                      frame_timer_s1.address
+		.frame_timer_s1_write                                      (mm_interconnect_1_frame_timer_s1_write),               //                                                    .write
+		.frame_timer_s1_readdata                                   (mm_interconnect_1_frame_timer_s1_readdata),            //                                                    .readdata
+		.frame_timer_s1_writedata                                  (mm_interconnect_1_frame_timer_s1_writedata),           //                                                    .writedata
+		.frame_timer_s1_chipselect                                 (mm_interconnect_1_frame_timer_s1_chipselect),          //                                                    .chipselect
+		.msgdma_rx_csr_address                                     (mm_interconnect_1_msgdma_rx_csr_address),              //                                       msgdma_rx_csr.address
+		.msgdma_rx_csr_write                                       (mm_interconnect_1_msgdma_rx_csr_write),                //                                                    .write
+		.msgdma_rx_csr_read                                        (mm_interconnect_1_msgdma_rx_csr_read),                 //                                                    .read
+		.msgdma_rx_csr_readdata                                    (mm_interconnect_1_msgdma_rx_csr_readdata),             //                                                    .readdata
+		.msgdma_rx_csr_writedata                                   (mm_interconnect_1_msgdma_rx_csr_writedata),            //                                                    .writedata
+		.msgdma_rx_csr_byteenable                                  (mm_interconnect_1_msgdma_rx_csr_byteenable),           //                                                    .byteenable
+		.msgdma_rx_prefetcher_csr_address                          (mm_interconnect_1_msgdma_rx_prefetcher_csr_address),   //                            msgdma_rx_prefetcher_csr.address
+		.msgdma_rx_prefetcher_csr_write                            (mm_interconnect_1_msgdma_rx_prefetcher_csr_write),     //                                                    .write
+		.msgdma_rx_prefetcher_csr_read                             (mm_interconnect_1_msgdma_rx_prefetcher_csr_read),      //                                                    .read
+		.msgdma_rx_prefetcher_csr_readdata                         (mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata),  //                                                    .readdata
+		.msgdma_rx_prefetcher_csr_writedata                        (mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata), //                                                    .writedata
+		.msgdma_tx_csr_address                                     (mm_interconnect_1_msgdma_tx_csr_address),              //                                       msgdma_tx_csr.address
+		.msgdma_tx_csr_write                                       (mm_interconnect_1_msgdma_tx_csr_write),                //                                                    .write
+		.msgdma_tx_csr_read                                        (mm_interconnect_1_msgdma_tx_csr_read),                 //                                                    .read
+		.msgdma_tx_csr_readdata                                    (mm_interconnect_1_msgdma_tx_csr_readdata),             //                                                    .readdata
+		.msgdma_tx_csr_writedata                                   (mm_interconnect_1_msgdma_tx_csr_writedata),            //                                                    .writedata
+		.msgdma_tx_csr_byteenable                                  (mm_interconnect_1_msgdma_tx_csr_byteenable),           //                                                    .byteenable
+		.msgdma_tx_prefetcher_csr_address                          (mm_interconnect_1_msgdma_tx_prefetcher_csr_address),   //                            msgdma_tx_prefetcher_csr.address
+		.msgdma_tx_prefetcher_csr_write                            (mm_interconnect_1_msgdma_tx_prefetcher_csr_write),     //                                                    .write
+		.msgdma_tx_prefetcher_csr_read                             (mm_interconnect_1_msgdma_tx_prefetcher_csr_read),      //                                                    .read
+		.msgdma_tx_prefetcher_csr_readdata                         (mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata),  //                                                    .readdata
+		.msgdma_tx_prefetcher_csr_writedata                        (mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata), //                                                    .writedata
+		.onchip_flash_csr_address                                  (mm_interconnect_1_onchip_flash_csr_address),           //                                    onchip_flash_csr.address
+		.onchip_flash_csr_write                                    (mm_interconnect_1_onchip_flash_csr_write),             //                                                    .write
+		.onchip_flash_csr_read                                     (mm_interconnect_1_onchip_flash_csr_read),              //                                                    .read
+		.onchip_flash_csr_readdata                                 (mm_interconnect_1_onchip_flash_csr_readdata),          //                                                    .readdata
+		.onchip_flash_csr_writedata                                (mm_interconnect_1_onchip_flash_csr_writedata),         //                                                    .writedata
+		.onchip_flash_data_address                                 (mm_interconnect_1_onchip_flash_data_address),          //                                   onchip_flash_data.address
+		.onchip_flash_data_write                                   (mm_interconnect_1_onchip_flash_data_write),            //                                                    .write
+		.onchip_flash_data_read                                    (mm_interconnect_1_onchip_flash_data_read),             //                                                    .read
+		.onchip_flash_data_readdata                                (mm_interconnect_1_onchip_flash_data_readdata),         //                                                    .readdata
+		.onchip_flash_data_writedata                               (mm_interconnect_1_onchip_flash_data_writedata),        //                                                    .writedata
+		.onchip_flash_data_burstcount                              (mm_interconnect_1_onchip_flash_data_burstcount),       //                                                    .burstcount
+		.onchip_flash_data_readdatavalid                           (mm_interconnect_1_onchip_flash_data_readdatavalid),    //                                                    .readdatavalid
+		.onchip_flash_data_waitrequest                             (mm_interconnect_1_onchip_flash_data_waitrequest),      //                                                    .waitrequest
+		.output_pio_s1_address                                     (mm_interconnect_1_output_pio_s1_address),              //                                       output_pio_s1.address
+		.output_pio_s1_write                                       (mm_interconnect_1_output_pio_s1_write),                //                                                    .write
+		.output_pio_s1_readdata                                    (mm_interconnect_1_output_pio_s1_readdata),             //                                                    .readdata
+		.output_pio_s1_writedata                                   (mm_interconnect_1_output_pio_s1_writedata),            //                                                    .writedata
+		.output_pio_s1_chipselect                                  (mm_interconnect_1_output_pio_s1_chipselect),           //                                                    .chipselect
+		.sensor_interface_csr_address                              (mm_interconnect_1_sensor_interface_csr_address),       //                                sensor_interface_csr.address
+		.sensor_interface_csr_write                                (mm_interconnect_1_sensor_interface_csr_write),         //                                                    .write
+		.sensor_interface_csr_read                                 (mm_interconnect_1_sensor_interface_csr_read),          //                                                    .read
+		.sensor_interface_csr_readdata                             (mm_interconnect_1_sensor_interface_csr_readdata),      //                                                    .readdata
+		.sensor_interface_csr_writedata                            (mm_interconnect_1_sensor_interface_csr_writedata),     //                                                    .writedata
+		.sensor_interface_csr_byteenable                           (mm_interconnect_1_sensor_interface_csr_byteenable),    //                                                    .byteenable
+		.sys_clk_timer_s1_address                                  (mm_interconnect_1_sys_clk_timer_s1_address),           //                                    sys_clk_timer_s1.address
+		.sys_clk_timer_s1_write                                    (mm_interconnect_1_sys_clk_timer_s1_write),             //                                                    .write
+		.sys_clk_timer_s1_readdata                                 (mm_interconnect_1_sys_clk_timer_s1_readdata),          //                                                    .readdata
+		.sys_clk_timer_s1_writedata                                (mm_interconnect_1_sys_clk_timer_s1_writedata),         //                                                    .writedata
+		.sys_clk_timer_s1_chipselect                               (mm_interconnect_1_sys_clk_timer_s1_chipselect),        //                                                    .chipselect
+		.sysid_control_slave_address                               (mm_interconnect_1_sysid_control_slave_address),        //                                 sysid_control_slave.address
+		.sysid_control_slave_readdata                              (mm_interconnect_1_sysid_control_slave_readdata),       //                                                    .readdata
+		.udp_generator_csr_address                                 (mm_interconnect_1_udp_generator_csr_address),          //                                   udp_generator_csr.address
+		.udp_generator_csr_write                                   (mm_interconnect_1_udp_generator_csr_write),            //                                                    .write
+		.udp_generator_csr_read                                    (mm_interconnect_1_udp_generator_csr_read),             //                                                    .read
+		.udp_generator_csr_readdata                                (mm_interconnect_1_udp_generator_csr_readdata),         //                                                    .readdata
+		.udp_generator_csr_writedata                               (mm_interconnect_1_udp_generator_csr_writedata),        //                                                    .writedata
+		.udp_generator_csr_byteenable                              (mm_interconnect_1_udp_generator_csr_byteenable)        //                                                    .byteenable
+	);
+
+	q_sys_irq_mapper irq_mapper (
+		.clk           (sys_clk_clk),                        //       clk.clk
+		.reset         (rst_controller_001_reset_out_reset), // clk_reset.reset
+		.receiver0_irq (irq_mapper_receiver0_irq),           // receiver0.irq
+		.receiver1_irq (irq_mapper_receiver1_irq),           // receiver1.irq
+		.receiver2_irq (irq_mapper_receiver2_irq),           // receiver2.irq
+		.receiver3_irq (irq_mapper_receiver3_irq),           // receiver3.irq
+		.receiver4_irq (irq_mapper_receiver4_irq),           // receiver4.irq
+		.sender_irq    (cpu_irq_irq)                         //    sender.irq
+	);
+
+	altera_irq_clock_crosser #(
+		.IRQ_WIDTH (1)
+	) irq_synchronizer (
+		.receiver_clk   (clock_bridge_0_in_clk_clk),          //       receiver_clk.clk
+		.sender_clk     (sys_clk_clk),                        //         sender_clk.clk
+		.receiver_reset (rst_controller_005_reset_out_reset), // receiver_clk_reset.reset
+		.sender_reset   (rst_controller_001_reset_out_reset), //   sender_clk_reset.reset
+		.receiver_irq   (irq_synchronizer_receiver_irq),      //           receiver.irq
+		.sender_irq     (irq_mapper_receiver2_irq)            //             sender.irq
+	);
+
+	q_sys_avalon_st_adapter #(
+		.inBitsPerSymbol (8),
+		.inUsePackets    (1),
+		.inDataWidth     (32),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (1),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (32),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (1),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk        (sys_clk_clk),                           // in_clk_0.clk
+		.in_rst_0_reset      (rst_controller_001_reset_out_reset),    // in_rst_0.reset
+		.in_0_data           (udp_generator_data_out_data),           //     in_0.data
+		.in_0_valid          (udp_generator_data_out_valid),          //         .valid
+		.in_0_ready          (udp_generator_data_out_ready),          //         .ready
+		.in_0_startofpacket  (udp_generator_data_out_startofpacket),  //         .startofpacket
+		.in_0_endofpacket    (udp_generator_data_out_endofpacket),    //         .endofpacket
+		.in_0_empty          (udp_generator_data_out_empty),          //         .empty
+		.out_0_data          (avalon_st_adapter_out_0_data),          //    out_0.data
+		.out_0_valid         (avalon_st_adapter_out_0_valid),         //         .valid
+		.out_0_ready         (avalon_st_adapter_out_0_ready),         //         .ready
+		.out_0_startofpacket (avalon_st_adapter_out_0_startofpacket), //         .startofpacket
+		.out_0_endofpacket   (avalon_st_adapter_out_0_endofpacket),   //         .endofpacket
+		.out_0_empty         (avalon_st_adapter_out_0_empty),         //         .empty
+		.out_0_error         (avalon_st_adapter_out_0_error)          //         .error
+	);
+
+	q_sys_avalon_st_adapter_001 #(
+		.inBitsPerSymbol (8),
+		.inUsePackets    (1),
+		.inDataWidth     (32),
+		.inChannelWidth  (0),
+		.inErrorWidth    (6),
+		.inUseEmptyPort  (1),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (2),
+		.outDataWidth    (32),
+		.outChannelWidth (0),
+		.outErrorWidth   (6),
+		.outUseEmptyPort (1),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk        (sys_clk_clk),                               // in_clk_0.clk
+		.in_rst_0_reset      (rst_controller_004_reset_out_reset),        // in_rst_0.reset
+		.in_0_data           (eth_tse_receive_data),                      //     in_0.data
+		.in_0_valid          (eth_tse_receive_valid),                     //         .valid
+		.in_0_ready          (eth_tse_receive_ready),                     //         .ready
+		.in_0_startofpacket  (eth_tse_receive_startofpacket),             //         .startofpacket
+		.in_0_endofpacket    (eth_tse_receive_endofpacket),               //         .endofpacket
+		.in_0_empty          (eth_tse_receive_empty),                     //         .empty
+		.in_0_error          (eth_tse_receive_error),                     //         .error
+		.out_0_data          (avalon_st_adapter_001_out_0_data),          //    out_0.data
+		.out_0_valid         (avalon_st_adapter_001_out_0_valid),         //         .valid
+		.out_0_ready         (avalon_st_adapter_001_out_0_ready),         //         .ready
+		.out_0_startofpacket (avalon_st_adapter_001_out_0_startofpacket), //         .startofpacket
+		.out_0_endofpacket   (avalon_st_adapter_001_out_0_endofpacket),   //         .endofpacket
+		.out_0_empty         (avalon_st_adapter_001_out_0_empty),         //         .empty
+		.out_0_error         (avalon_st_adapter_001_out_0_error)          //         .error
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (1),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller (
+		.reset_in0      (~mem_resetn_in_reset_reset_n),   // reset_in0.reset
+		.clk            (sys_clk_clk),                    //       clk.clk
+		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
+		.reset_req      (),                               // (terminated)
+		.reset_req_in0  (1'b0),                           // (terminated)
+		.reset_in1      (1'b0),                           // (terminated)
+		.reset_req_in1  (1'b0),                           // (terminated)
+		.reset_in2      (1'b0),                           // (terminated)
+		.reset_req_in2  (1'b0),                           // (terminated)
+		.reset_in3      (1'b0),                           // (terminated)
+		.reset_req_in3  (1'b0),                           // (terminated)
+		.reset_in4      (1'b0),                           // (terminated)
+		.reset_req_in4  (1'b0),                           // (terminated)
+		.reset_in5      (1'b0),                           // (terminated)
+		.reset_req_in5  (1'b0),                           // (terminated)
+		.reset_in6      (1'b0),                           // (terminated)
+		.reset_req_in6  (1'b0),                           // (terminated)
+		.reset_in7      (1'b0),                           // (terminated)
+		.reset_req_in7  (1'b0),                           // (terminated)
+		.reset_in8      (1'b0),                           // (terminated)
+		.reset_req_in8  (1'b0),                           // (terminated)
+		.reset_in9      (1'b0),                           // (terminated)
+		.reset_req_in9  (1'b0),                           // (terminated)
+		.reset_in10     (1'b0),                           // (terminated)
+		.reset_req_in10 (1'b0),                           // (terminated)
+		.reset_in11     (1'b0),                           // (terminated)
+		.reset_req_in11 (1'b0),                           // (terminated)
+		.reset_in12     (1'b0),                           // (terminated)
+		.reset_req_in12 (1'b0),                           // (terminated)
+		.reset_in13     (1'b0),                           // (terminated)
+		.reset_req_in13 (1'b0),                           // (terminated)
+		.reset_in14     (1'b0),                           // (terminated)
+		.reset_req_in14 (1'b0),                           // (terminated)
+		.reset_in15     (1'b0),                           // (terminated)
+		.reset_req_in15 (1'b0)                            // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (1),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (1),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_001 (
+		.reset_in0      (~reset_reset_n),                         // reset_in0.reset
+		.clk            (sys_clk_clk),                            //       clk.clk
+		.reset_out      (rst_controller_001_reset_out_reset),     // reset_out.reset
+		.reset_req      (rst_controller_001_reset_out_reset_req), //          .reset_req
+		.reset_req_in0  (1'b0),                                   // (terminated)
+		.reset_in1      (1'b0),                                   // (terminated)
+		.reset_req_in1  (1'b0),                                   // (terminated)
+		.reset_in2      (1'b0),                                   // (terminated)
+		.reset_req_in2  (1'b0),                                   // (terminated)
+		.reset_in3      (1'b0),                                   // (terminated)
+		.reset_req_in3  (1'b0),                                   // (terminated)
+		.reset_in4      (1'b0),                                   // (terminated)
+		.reset_req_in4  (1'b0),                                   // (terminated)
+		.reset_in5      (1'b0),                                   // (terminated)
+		.reset_req_in5  (1'b0),                                   // (terminated)
+		.reset_in6      (1'b0),                                   // (terminated)
+		.reset_req_in6  (1'b0),                                   // (terminated)
+		.reset_in7      (1'b0),                                   // (terminated)
+		.reset_req_in7  (1'b0),                                   // (terminated)
+		.reset_in8      (1'b0),                                   // (terminated)
+		.reset_req_in8  (1'b0),                                   // (terminated)
+		.reset_in9      (1'b0),                                   // (terminated)
+		.reset_req_in9  (1'b0),                                   // (terminated)
+		.reset_in10     (1'b0),                                   // (terminated)
+		.reset_req_in10 (1'b0),                                   // (terminated)
+		.reset_in11     (1'b0),                                   // (terminated)
+		.reset_req_in11 (1'b0),                                   // (terminated)
+		.reset_in12     (1'b0),                                   // (terminated)
+		.reset_req_in12 (1'b0),                                   // (terminated)
+		.reset_in13     (1'b0),                                   // (terminated)
+		.reset_req_in13 (1'b0),                                   // (terminated)
+		.reset_in14     (1'b0),                                   // (terminated)
+		.reset_req_in14 (1'b0),                                   // (terminated)
+		.reset_in15     (1'b0),                                   // (terminated)
+		.reset_req_in15 (1'b0)                                    // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (2),
+		.OUTPUT_RESET_SYNC_EDGES   ("none"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_002 (
+		.reset_in0      (cpu_debug_reset_request_reset),      // reset_in0.reset
+		.reset_in1      (~mem_resetn_in_reset_reset_n),       // reset_in1.reset
+		.clk            (),                                   //       clk.clk
+		.reset_out      (rst_controller_002_reset_out_reset), // reset_out.reset
+		.reset_req      (),                                   // (terminated)
+		.reset_req_in0  (1'b0),                               // (terminated)
+		.reset_req_in1  (1'b0),                               // (terminated)
+		.reset_in2      (1'b0),                               // (terminated)
+		.reset_req_in2  (1'b0),                               // (terminated)
+		.reset_in3      (1'b0),                               // (terminated)
+		.reset_req_in3  (1'b0),                               // (terminated)
+		.reset_in4      (1'b0),                               // (terminated)
+		.reset_req_in4  (1'b0),                               // (terminated)
+		.reset_in5      (1'b0),                               // (terminated)
+		.reset_req_in5  (1'b0),                               // (terminated)
+		.reset_in6      (1'b0),                               // (terminated)
+		.reset_req_in6  (1'b0),                               // (terminated)
+		.reset_in7      (1'b0),                               // (terminated)
+		.reset_req_in7  (1'b0),                               // (terminated)
+		.reset_in8      (1'b0),                               // (terminated)
+		.reset_req_in8  (1'b0),                               // (terminated)
+		.reset_in9      (1'b0),                               // (terminated)
+		.reset_req_in9  (1'b0),                               // (terminated)
+		.reset_in10     (1'b0),                               // (terminated)
+		.reset_req_in10 (1'b0),                               // (terminated)
+		.reset_in11     (1'b0),                               // (terminated)
+		.reset_req_in11 (1'b0),                               // (terminated)
+		.reset_in12     (1'b0),                               // (terminated)
+		.reset_req_in12 (1'b0),                               // (terminated)
+		.reset_in13     (1'b0),                               // (terminated)
+		.reset_req_in13 (1'b0),                               // (terminated)
+		.reset_in14     (1'b0),                               // (terminated)
+		.reset_req_in14 (1'b0),                               // (terminated)
+		.reset_in15     (1'b0),                               // (terminated)
+		.reset_req_in15 (1'b0)                                // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (2),
+		.OUTPUT_RESET_SYNC_EDGES   ("none"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_003 (
+		.reset_in0      (cpu_debug_reset_request_reset),      // reset_in0.reset
+		.reset_in1      (~mem_resetn_in_reset_reset_n),       // reset_in1.reset
+		.clk            (),                                   //       clk.clk
+		.reset_out      (rst_controller_003_reset_out_reset), // reset_out.reset
+		.reset_req      (),                                   // (terminated)
+		.reset_req_in0  (1'b0),                               // (terminated)
+		.reset_req_in1  (1'b0),                               // (terminated)
+		.reset_in2      (1'b0),                               // (terminated)
+		.reset_req_in2  (1'b0),                               // (terminated)
+		.reset_in3      (1'b0),                               // (terminated)
+		.reset_req_in3  (1'b0),                               // (terminated)
+		.reset_in4      (1'b0),                               // (terminated)
+		.reset_req_in4  (1'b0),                               // (terminated)
+		.reset_in5      (1'b0),                               // (terminated)
+		.reset_req_in5  (1'b0),                               // (terminated)
+		.reset_in6      (1'b0),                               // (terminated)
+		.reset_req_in6  (1'b0),                               // (terminated)
+		.reset_in7      (1'b0),                               // (terminated)
+		.reset_req_in7  (1'b0),                               // (terminated)
+		.reset_in8      (1'b0),                               // (terminated)
+		.reset_req_in8  (1'b0),                               // (terminated)
+		.reset_in9      (1'b0),                               // (terminated)
+		.reset_req_in9  (1'b0),                               // (terminated)
+		.reset_in10     (1'b0),                               // (terminated)
+		.reset_req_in10 (1'b0),                               // (terminated)
+		.reset_in11     (1'b0),                               // (terminated)
+		.reset_req_in11 (1'b0),                               // (terminated)
+		.reset_in12     (1'b0),                               // (terminated)
+		.reset_req_in12 (1'b0),                               // (terminated)
+		.reset_in13     (1'b0),                               // (terminated)
+		.reset_req_in13 (1'b0),                               // (terminated)
+		.reset_in14     (1'b0),                               // (terminated)
+		.reset_req_in14 (1'b0),                               // (terminated)
+		.reset_in15     (1'b0),                               // (terminated)
+		.reset_req_in15 (1'b0)                                // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (2),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (1),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_004 (
+		.reset_in0      (~reset_reset_n),                         // reset_in0.reset
+		.reset_in1      (cpu_debug_reset_request_reset),          // reset_in1.reset
+		.clk            (sys_clk_clk),                            //       clk.clk
+		.reset_out      (rst_controller_004_reset_out_reset),     // reset_out.reset
+		.reset_req      (rst_controller_004_reset_out_reset_req), //          .reset_req
+		.reset_req_in0  (1'b0),                                   // (terminated)
+		.reset_req_in1  (1'b0),                                   // (terminated)
+		.reset_in2      (1'b0),                                   // (terminated)
+		.reset_req_in2  (1'b0),                                   // (terminated)
+		.reset_in3      (1'b0),                                   // (terminated)
+		.reset_req_in3  (1'b0),                                   // (terminated)
+		.reset_in4      (1'b0),                                   // (terminated)
+		.reset_req_in4  (1'b0),                                   // (terminated)
+		.reset_in5      (1'b0),                                   // (terminated)
+		.reset_req_in5  (1'b0),                                   // (terminated)
+		.reset_in6      (1'b0),                                   // (terminated)
+		.reset_req_in6  (1'b0),                                   // (terminated)
+		.reset_in7      (1'b0),                                   // (terminated)
+		.reset_req_in7  (1'b0),                                   // (terminated)
+		.reset_in8      (1'b0),                                   // (terminated)
+		.reset_req_in8  (1'b0),                                   // (terminated)
+		.reset_in9      (1'b0),                                   // (terminated)
+		.reset_req_in9  (1'b0),                                   // (terminated)
+		.reset_in10     (1'b0),                                   // (terminated)
+		.reset_req_in10 (1'b0),                                   // (terminated)
+		.reset_in11     (1'b0),                                   // (terminated)
+		.reset_req_in11 (1'b0),                                   // (terminated)
+		.reset_in12     (1'b0),                                   // (terminated)
+		.reset_req_in12 (1'b0),                                   // (terminated)
+		.reset_in13     (1'b0),                                   // (terminated)
+		.reset_req_in13 (1'b0),                                   // (terminated)
+		.reset_in14     (1'b0),                                   // (terminated)
+		.reset_req_in14 (1'b0),                                   // (terminated)
+		.reset_in15     (1'b0),                                   // (terminated)
+		.reset_req_in15 (1'b0)                                    // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (2),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_005 (
+		.reset_in0      (~reset_reset_n),                     // reset_in0.reset
+		.reset_in1      (cpu_debug_reset_request_reset),      // reset_in1.reset
+		.clk            (clock_bridge_0_in_clk_clk),          //       clk.clk
+		.reset_out      (rst_controller_005_reset_out_reset), // reset_out.reset
+		.reset_req      (),                                   // (terminated)
+		.reset_req_in0  (1'b0),                               // (terminated)
+		.reset_req_in1  (1'b0),                               // (terminated)
+		.reset_in2      (1'b0),                               // (terminated)
+		.reset_req_in2  (1'b0),                               // (terminated)
+		.reset_in3      (1'b0),                               // (terminated)
+		.reset_req_in3  (1'b0),                               // (terminated)
+		.reset_in4      (1'b0),                               // (terminated)
+		.reset_req_in4  (1'b0),                               // (terminated)
+		.reset_in5      (1'b0),                               // (terminated)
+		.reset_req_in5  (1'b0),                               // (terminated)
+		.reset_in6      (1'b0),                               // (terminated)
+		.reset_req_in6  (1'b0),                               // (terminated)
+		.reset_in7      (1'b0),                               // (terminated)
+		.reset_req_in7  (1'b0),                               // (terminated)
+		.reset_in8      (1'b0),                               // (terminated)
+		.reset_req_in8  (1'b0),                               // (terminated)
+		.reset_in9      (1'b0),                               // (terminated)
+		.reset_req_in9  (1'b0),                               // (terminated)
+		.reset_in10     (1'b0),                               // (terminated)
+		.reset_req_in10 (1'b0),                               // (terminated)
+		.reset_in11     (1'b0),                               // (terminated)
+		.reset_req_in11 (1'b0),                               // (terminated)
+		.reset_in12     (1'b0),                               // (terminated)
+		.reset_req_in12 (1'b0),                               // (terminated)
+		.reset_in13     (1'b0),                               // (terminated)
+		.reset_req_in13 (1'b0),                               // (terminated)
+		.reset_in14     (1'b0),                               // (terminated)
+		.reset_req_in14 (1'b0),                               // (terminated)
+		.reset_in15     (1'b0),                               // (terminated)
+		.reset_req_in15 (1'b0)                                // (terminated)
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (2),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller_006 (
+		.reset_in0      (cpu_debug_reset_request_reset),      // reset_in0.reset
+		.reset_in1      (~mem_resetn_in_reset_reset_n),       // reset_in1.reset
+		.clk            (ddr3_ram_afi_clk_clk),               //       clk.clk
+		.reset_out      (rst_controller_006_reset_out_reset), // reset_out.reset
+		.reset_req      (),                                   // (terminated)
+		.reset_req_in0  (1'b0),                               // (terminated)
+		.reset_req_in1  (1'b0),                               // (terminated)
+		.reset_in2      (1'b0),                               // (terminated)
+		.reset_req_in2  (1'b0),                               // (terminated)
+		.reset_in3      (1'b0),                               // (terminated)
+		.reset_req_in3  (1'b0),                               // (terminated)
+		.reset_in4      (1'b0),                               // (terminated)
+		.reset_req_in4  (1'b0),                               // (terminated)
+		.reset_in5      (1'b0),                               // (terminated)
+		.reset_req_in5  (1'b0),                               // (terminated)
+		.reset_in6      (1'b0),                               // (terminated)
+		.reset_req_in6  (1'b0),                               // (terminated)
+		.reset_in7      (1'b0),                               // (terminated)
+		.reset_req_in7  (1'b0),                               // (terminated)
+		.reset_in8      (1'b0),                               // (terminated)
+		.reset_req_in8  (1'b0),                               // (terminated)
+		.reset_in9      (1'b0),                               // (terminated)
+		.reset_req_in9  (1'b0),                               // (terminated)
+		.reset_in10     (1'b0),                               // (terminated)
+		.reset_req_in10 (1'b0),                               // (terminated)
+		.reset_in11     (1'b0),                               // (terminated)
+		.reset_req_in11 (1'b0),                               // (terminated)
+		.reset_in12     (1'b0),                               // (terminated)
+		.reset_req_in12 (1'b0),                               // (terminated)
+		.reset_in13     (1'b0),                               // (terminated)
+		.reset_req_in13 (1'b0),                               // (terminated)
+		.reset_in14     (1'b0),                               // (terminated)
+		.reset_req_in14 (1'b0),                               // (terminated)
+		.reset_in15     (1'b0),                               // (terminated)
+		.reset_req_in15 (1'b0)                                // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/MM_to_ST_Adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/MM_to_ST_Adapter.v
new file mode 100644
index 0000000..c49897b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/MM_to_ST_Adapter.v
@@ -0,0 +1,365 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This logic recieves Avalon Memory Mapped read data and translates it into
+  the Avalon Streaming format.  The ST format requires all data to be packed
+  until the final transfer when packet support is enabled.  As a result when
+  you enable unaligned acceses the data from two sucessive reads must be
+  combined to form a single word of data.  If you disable packet support
+  and unaligned access support this block will synthesize into wires.
+  
+  This block does not provide any read throttling as it simply acts as a format
+  adapter between the read master port and the read master FIFO.  All throttling
+  should be provided by the read master to prevent overflow.  Since this logic
+  sits on the MM side of the FIFO the bytes are in 'little endian' format and
+  will get swapped around on the other side of the FIFO (symbol size can be adjusted
+  there too).
+  
+  Revision History:
+  
+  1.0 Initial version
+  
+  2.0 Removed 'bytes_to_next_boundary' and using the address and length signals
+      instead to determine how much out of alignment the master begins.
+
+  2.1 Changed the extra last access logic to be based on the descriptor address
+      and length as apposed to the counter values.  Created a new 'length_counter'
+      input to determine when the last read has arrived.
+*/
+
+
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module MM_to_ST_Adapter (
+  clk,
+  reset,
+  
+  length,
+  length_counter,
+  address,
+  reads_pending,
+  start,
+
+  readdata,
+  readdatavalid,
+  fifo_data,
+  fifo_write,
+  fifo_empty,
+  fifo_sop,
+  fifo_eop
+);
+
+
+
+  parameter DATA_WIDTH = 32;                   // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses)
+  parameter LENGTH_WIDTH = 32;
+  parameter ADDRESS_WIDTH = 32;
+  parameter BYTE_ADDRESS_WIDTH = 2;            // log2(DATA_WIDTH/8)
+  parameter READS_PENDING_WIDTH = 5;
+  parameter EMPTY_WIDTH = 2;                   // log2(DATA_WIDTH/8)
+  parameter PACKET_SUPPORT = 1;                // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded
+  // only set one of these at a time
+  parameter UNALIGNED_ACCESS_ENABLE = 1;       // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY')
+  parameter FULL_WORD_ACCESS_ONLY = 0;         // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary).
+
+
+  input clk;
+  input reset;
+  
+
+  input [LENGTH_WIDTH-1:0] length;
+  input [LENGTH_WIDTH-1:0] length_counter;
+  input [ADDRESS_WIDTH-1:0] address;
+  input [READS_PENDING_WIDTH-1:0] reads_pending;
+  input start;   // one cycle strobe at the start of a transfer used to capture bytes_to_transfer
+
+
+  input [DATA_WIDTH-1:0] readdata;
+  input readdatavalid;
+  output wire [DATA_WIDTH-1:0] fifo_data;
+  output wire fifo_write;
+  output wire [EMPTY_WIDTH-1:0] fifo_empty;
+  output wire fifo_sop;
+  output wire fifo_eop;
+
+
+  // internal registers and wires  
+  reg [DATA_WIDTH-1:0] readdata_d1;
+  reg readdatavalid_d1;
+  wire [DATA_WIDTH-1:0] data_in;            // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled
+  wire valid_in;                            // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled
+  reg valid_in_d1;
+  wire [DATA_WIDTH-1:0] barrelshifter_A;    // shifted current read data
+  wire [DATA_WIDTH-1:0] barrelshifter_B;
+  reg [DATA_WIDTH-1:0] barrelshifter_B_d1;  // shifted previously read data
+  wire [DATA_WIDTH-1:0] combined_word;  // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
+  wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)];  // will be used to create barrelshifter_A inputs
+  wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)];  // will be used to create barrelshifter_B inputs
+  wire extra_access_enable;
+  reg extra_access;
+  wire last_unaligned_fifo_write;
+  reg first_access_seen;
+  reg second_access_seen;
+  wire first_access_seen_rising_edge;
+  wire second_access_seen_rising_edge;
+  reg [BYTE_ADDRESS_WIDTH-1:0] byte_address;
+  reg [EMPTY_WIDTH-1:0] last_empty;  // only the last word written into the FIFO can have empty bytes
+  reg start_and_end_same_cycle;  // when the amount of data to transfer is only a full word or less
+
+
+  generate
+    if (UNALIGNED_ACCESS_ENABLE == 1)  // unaligned so using a pipelined input
+    begin
+      assign data_in = readdata_d1;
+      assign valid_in = readdatavalid_d1;
+    end
+    else
+    begin
+      assign data_in = readdata;       // no barrelshifters in this case so pipelining is not necessary
+      assign valid_in = readdatavalid;
+    end
+  endgenerate
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      readdata_d1 <= 0;
+    end
+    else
+    begin
+      if (readdatavalid == 1)
+      begin
+        readdata_d1 <= readdata;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      readdatavalid_d1 <= 0;
+      valid_in_d1 <= 0;
+    end
+    else
+    begin
+      readdatavalid_d1 <= readdatavalid;
+      valid_in_d1 <= valid_in;  // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset == 1)
+    begin
+      barrelshifter_B_d1 <= 0;
+    end
+    else
+    begin
+      if (valid_in == 1)
+      begin
+        barrelshifter_B_d1 <= barrelshifter_B;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      first_access_seen <= 0;
+    end
+    else
+    begin
+      if (start == 1)
+      begin
+        first_access_seen <= 0;
+      end
+      else if (valid_in == 1)
+      begin
+        first_access_seen <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      second_access_seen <= 0;
+    end
+    else
+    begin
+      if (start == 1)
+      begin
+        second_access_seen <= 0;
+      end
+      else if ((first_access_seen == 1) & (valid_in == 1))
+      begin
+        second_access_seen <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      byte_address <= 0;
+    end
+    else if (start == 1)
+    begin
+      byte_address <= address[BYTE_ADDRESS_WIDTH-1:0];
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      last_empty <= 0;
+    end
+    else if (start == 1)
+    begin
+      last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}};  // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      extra_access <= 0;
+    end
+    else if (start == 1)
+    begin
+      extra_access <= extra_access_enable;  // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only)
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      start_and_end_same_cycle <= 0;
+    end
+    else if (start == 1)
+    begin
+      start_and_end_same_cycle <= (length <= (DATA_WIDTH/8));
+    end
+  end
+
+
+  /* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word.
+     Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered.  This allows both barrelshifters
+     to be logically OR'ed together to form a single packed word.  Shifter A is used to shift the current read data towards the upper bytes of the
+     combined word (since those are the upper addresses of the combined word).  Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains
+     the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word).
+  */
+  generate
+    genvar input_offset;
+    for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
+    begin:  barrel_shifter_inputs
+      assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset)); 
+      assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset);
+    end
+  endgenerate
+
+  assign barrelshifter_A = barrelshifter_input_A[byte_address];   // upper portion of the packed word
+  assign barrelshifter_B = barrelshifter_input_B[byte_address];   // lower portion of the packed word (will be pipelined so it will be the previous word read by the master)
+  assign combined_word = (barrelshifter_A | barrelshifter_B_d1);  // barrelshifters shift in zeros so we can just OR the words together here to create a packed word
+
+
+
+  assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0);
+  assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0);
+  assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0];  // enable when empty >= byte address
+
+
+  /*  Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses
+      is enabled.  The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases
+      when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write.
+      In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write
+      to the FIFO will immediately follow the last read.
+  */
+  assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) &
+                                     (  ((extra_access == 0) & (valid_in == 1)) |                         // don't need a pipeline flush
+                                        ((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0))  );  // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined)
+
+
+  // This block should be optimized down depending on the packet support or access type settings.  In the case where packet support is off
+  // and only full accesses are used this block should become zero logic elements.
+  generate
+  if (PACKET_SUPPORT == 1)
+  begin
+    if (UNALIGNED_ACCESS_ENABLE == 1)
+    begin
+      assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1));
+      assign fifo_eop = last_unaligned_fifo_write;
+      assign fifo_empty = (fifo_eop == 1)? last_empty : 0;  // always full accesses until the last word
+    end
+    else
+    begin
+      assign fifo_sop = first_access_seen_rising_edge;
+      assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1);  // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined
+      if (FULL_WORD_ACCESS_ONLY == 1)
+      begin
+        assign fifo_empty = 0;  // full accesses so no empty symbols throughout the transfer
+      end
+      else
+      begin
+        assign fifo_empty = (fifo_eop == 1)? last_empty : 0;  // always full accesses until the last word
+      end
+    end
+  end
+  else
+  begin
+    assign fifo_eop = 0;
+    assign fifo_sop = 0;
+    assign fifo_empty = 0;
+  end
+
+
+  if (UNALIGNED_ACCESS_ENABLE == 1)
+  begin
+    assign fifo_data = combined_word;
+    assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1));  // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed
+  end
+  else
+  begin  // don't need to pipeline since the data will not go through the barrel shifters
+    assign fifo_data = data_in;   // don't need to barrelshift when aligned accesses are used
+    assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory
+  end
+  endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/ST_to_MM_Adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/ST_to_MM_Adapter.v
new file mode 100644
index 0000000..cdc9016
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/ST_to_MM_Adapter.v
@@ -0,0 +1,154 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+	This logic recieves registers the byte address of the master when 'start'
+	is asserted.  This block then barrelshifts the write data based on the byte
+	address to make sure that the input data (from the FIFO) is reformatted to
+	line up with memory properly.
+	
+	The only throttling mechanism in this block is the FIFO not empty signal as
+	well as waitreqeust from the fabric.
+	
+	Revision History:
+	
+	1.0 Initial version
+	
+	2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
+	    much out of alignment the master begins.
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module ST_to_MM_Adapter (
+  clk,
+  reset,
+
+  enable,
+  address,
+  start,
+  waitrequest,
+  stall,
+  write_data,
+  
+  fifo_data,
+  fifo_empty,
+  fifo_readack
+);
+
+  parameter DATA_WIDTH = 32;
+  parameter BYTEENABLE_WIDTH_LOG2 = 2;
+  parameter ADDRESS_WIDTH = 32;
+  parameter UNALIGNED_ACCESS_ENABLE = 0;  // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
+  localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1;  // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
+
+  input clk;
+  input reset;
+  
+  input enable;  // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
+  input [ADDRESS_WIDTH-1:0] address;
+  input start;   // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
+  input waitrequest;
+  input stall;
+  output wire [DATA_WIDTH-1:0] write_data;
+
+  input [DATA_WIDTH-1:0] fifo_data;
+  input fifo_empty;
+  output wire fifo_readack;
+  
+
+  wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;  
+  wire [DATA_WIDTH-1:0] barrelshifter_A;
+  wire [DATA_WIDTH-1:0] barrelshifter_B;
+  reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
+  wire [DATA_WIDTH-1:0] combined_word;  // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
+  wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one;  // simplifies barrelshifter select logic
+  reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
+  wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)];  // will be used to create barrelshifter_A inputs
+  wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)];  // will be used to create barrelshifter_B inputs
+
+
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      bytes_to_next_boundary_minus_one_d1 <= 0;
+    end
+    else if (start)
+    begin
+      bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      barrelshifter_B_d1 <= 0;
+    end
+    else
+    begin
+      if (start == 1)
+      begin
+        barrelshifter_B_d1 <= 0;
+      end
+      else if (fifo_readack == 1)
+      begin
+        barrelshifter_B_d1 <= barrelshifter_B;
+      end
+    end
+  end
+
+
+  assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0];  // bytes per word - unaligned byte offset = distance to next boundary
+  assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
+  assign combined_word = barrelshifter_A | barrelshifter_B_d1;
+
+generate
+genvar input_offset;
+for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
+begin:  barrel_shifter_inputs
+  assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
+  assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
+end
+endgenerate
+
+  assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
+  assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
+  
+generate
+if (UNALIGNED_ACCESS_ENABLE == 1)
+begin
+  assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
+  assign write_data = combined_word;
+end
+else
+begin
+  assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
+  assign write_data = fifo_data;
+end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v b/FPGA_firmware/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
new file mode 100644
index 0000000..3eff49e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
@@ -0,0 +1,253 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// Filename: afi_mux.v
+// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
+// During calibration, mux_sel = 1, sequencer AFI signals are selected
+// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+module afi_mux_ddr3_ddrx (
+	clk,
+	mux_sel,
+	afi_addr,
+	afi_ba,
+	afi_cs_n,
+	afi_cke,
+	afi_odt,
+	afi_ras_n,
+	afi_cas_n,
+	afi_we_n,
+	afi_dm,
+	afi_wlat,
+	afi_rlat,
+	afi_rst_n,
+	afi_dqs_burst,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_rdata_en,
+	afi_rdata_en_full,
+	afi_rdata,
+	afi_rdata_valid,
+	afi_cal_success,
+	afi_cal_fail,
+	seq_mux_addr,
+	seq_mux_ba,
+	seq_mux_cs_n,
+	seq_mux_cke,
+	seq_mux_odt,
+	seq_mux_ras_n,
+	seq_mux_cas_n,
+	seq_mux_we_n,
+	seq_mux_dm,
+	seq_mux_rst_n,
+	seq_mux_dqs_burst,
+	seq_mux_wdata,
+	seq_mux_wdata_valid,
+	seq_mux_rdata_en,
+	seq_mux_rdata_en_full,
+	seq_mux_rdata,
+	seq_mux_rdata_valid,
+	phy_mux_addr,
+	phy_mux_ba,
+	phy_mux_cs_n,
+	phy_mux_cke,
+	phy_mux_odt,
+	phy_mux_ras_n,
+	phy_mux_cas_n,
+	phy_mux_we_n,
+	phy_mux_dm,
+	phy_mux_wlat,
+	phy_mux_rlat,
+	phy_mux_rst_n,
+	phy_mux_dqs_burst,
+	phy_mux_wdata,
+	phy_mux_wdata_valid,
+	phy_mux_rdata_en,
+	phy_mux_rdata_en_full,
+	phy_mux_rdata,
+	phy_mux_rdata_valid,
+	phy_mux_cal_success,
+	phy_mux_cal_fail
+);
+
+
+parameter AFI_ADDR_WIDTH            = 0;
+parameter AFI_BANKADDR_WIDTH        = 0;
+parameter AFI_CS_WIDTH              = 0;
+parameter AFI_CLK_EN_WIDTH          = 0;
+parameter AFI_ODT_WIDTH             = 0;
+parameter AFI_WLAT_WIDTH            = 0;
+parameter AFI_RLAT_WIDTH            = 0;
+parameter AFI_RRANK_WIDTH           = 0;
+parameter AFI_WRANK_WIDTH           = 0;
+parameter AFI_DM_WIDTH              = 0;
+parameter AFI_CONTROL_WIDTH         = 0;
+parameter AFI_DQ_WIDTH              = 0;
+parameter AFI_WRITE_DQS_WIDTH       = 0;
+parameter AFI_RATE_RATIO            = 0;
+
+parameter MRS_MIRROR_PING_PONG_ATSO = 0;
+
+input clk;
+
+input	mux_sel;
+
+
+// AFI inputs from the controller
+input         [AFI_ADDR_WIDTH-1:0]  afi_addr;
+input     [AFI_BANKADDR_WIDTH-1:0]  afi_ba;
+input      [AFI_CONTROL_WIDTH-1:0]  afi_cas_n;
+input       [AFI_CLK_EN_WIDTH-1:0]  afi_cke;
+input           [AFI_CS_WIDTH-1:0]  afi_cs_n;
+input          [AFI_ODT_WIDTH-1:0]  afi_odt;
+input      [AFI_CONTROL_WIDTH-1:0]  afi_ras_n;
+input      [AFI_CONTROL_WIDTH-1:0]  afi_we_n;
+input           [AFI_DM_WIDTH-1:0]  afi_dm;
+output        [AFI_WLAT_WIDTH-1:0]  afi_wlat;
+output        [AFI_RLAT_WIDTH-1:0]  afi_rlat;
+input      [AFI_CONTROL_WIDTH-1:0]  afi_rst_n;
+input	 [AFI_WRITE_DQS_WIDTH-1:0]	afi_dqs_burst;
+input           [AFI_DQ_WIDTH-1:0]  afi_wdata;
+input    [AFI_WRITE_DQS_WIDTH-1:0]  afi_wdata_valid;
+input         [AFI_RATE_RATIO-1:0]  afi_rdata_en;
+input         [AFI_RATE_RATIO-1:0]  afi_rdata_en_full;
+output	        [AFI_DQ_WIDTH-1:0]  afi_rdata;
+output	      [AFI_RATE_RATIO-1:0]  afi_rdata_valid;
+
+output                              afi_cal_success;
+output                              afi_cal_fail;
+
+// AFI inputs from the sequencer
+input         [AFI_ADDR_WIDTH-1:0]  seq_mux_addr;
+input     [AFI_BANKADDR_WIDTH-1:0]  seq_mux_ba;
+input           [AFI_CS_WIDTH-1:0]  seq_mux_cs_n;
+input       [AFI_CLK_EN_WIDTH-1:0]  seq_mux_cke;
+input	       [AFI_ODT_WIDTH-1:0]  seq_mux_odt;
+input	   [AFI_CONTROL_WIDTH-1:0]  seq_mux_ras_n;
+input	   [AFI_CONTROL_WIDTH-1:0]  seq_mux_cas_n;
+input	   [AFI_CONTROL_WIDTH-1:0]  seq_mux_we_n;
+input           [AFI_DM_WIDTH-1:0]  seq_mux_dm;
+input	   [AFI_CONTROL_WIDTH-1:0]  seq_mux_rst_n;
+input	 [AFI_WRITE_DQS_WIDTH-1:0]	seq_mux_dqs_burst;
+input           [AFI_DQ_WIDTH-1:0]  seq_mux_wdata;
+input    [AFI_WRITE_DQS_WIDTH-1:0]	seq_mux_wdata_valid;
+input         [AFI_RATE_RATIO-1:0]  seq_mux_rdata_en;
+input         [AFI_RATE_RATIO-1:0]  seq_mux_rdata_en_full;
+output          [AFI_DQ_WIDTH-1:0]  seq_mux_rdata;
+output        [AFI_RATE_RATIO-1:0]  seq_mux_rdata_valid;
+
+// Mux output to the rest of the PHY logic
+output        [AFI_ADDR_WIDTH-1:0]  phy_mux_addr;
+output    [AFI_BANKADDR_WIDTH-1:0]  phy_mux_ba;
+output          [AFI_CS_WIDTH-1:0]  phy_mux_cs_n;
+output      [AFI_CLK_EN_WIDTH-1:0]  phy_mux_cke;
+output         [AFI_ODT_WIDTH-1:0]  phy_mux_odt;
+output     [AFI_CONTROL_WIDTH-1:0]  phy_mux_ras_n;
+output     [AFI_CONTROL_WIDTH-1:0]  phy_mux_cas_n;
+output     [AFI_CONTROL_WIDTH-1:0]  phy_mux_we_n;
+output          [AFI_DM_WIDTH-1:0]  phy_mux_dm;
+input         [AFI_WLAT_WIDTH-1:0]  phy_mux_wlat;
+input         [AFI_RLAT_WIDTH-1:0]  phy_mux_rlat;
+output     [AFI_CONTROL_WIDTH-1:0]  phy_mux_rst_n;
+output   [AFI_WRITE_DQS_WIDTH-1:0]  phy_mux_dqs_burst;
+output          [AFI_DQ_WIDTH-1:0]  phy_mux_wdata;
+output   [AFI_WRITE_DQS_WIDTH-1:0]  phy_mux_wdata_valid;
+output        [AFI_RATE_RATIO-1:0]  phy_mux_rdata_en;
+output        [AFI_RATE_RATIO-1:0]  phy_mux_rdata_en_full;
+input           [AFI_DQ_WIDTH-1:0]  phy_mux_rdata;
+input         [AFI_RATE_RATIO-1:0]  phy_mux_rdata_valid;
+
+input                               phy_mux_cal_success;
+input                               phy_mux_cal_fail;
+
+
+reg	     [AFI_ADDR_WIDTH-1:0]  afi_addr_r;
+reg  [AFI_BANKADDR_WIDTH-1:0]  afi_ba_r;
+reg   [AFI_CONTROL_WIDTH-1:0]  afi_cas_n_r;
+reg    [AFI_CLK_EN_WIDTH-1:0]  afi_cke_r;
+reg        [AFI_CS_WIDTH-1:0]  afi_cs_n_r;
+reg       [AFI_ODT_WIDTH-1:0]  afi_odt_r;
+reg   [AFI_CONTROL_WIDTH-1:0]  afi_ras_n_r;
+reg   [AFI_CONTROL_WIDTH-1:0]  afi_we_n_r;
+reg   [AFI_CONTROL_WIDTH-1:0]  afi_rst_n_r;
+
+reg	[AFI_ADDR_WIDTH-1:0] seq_mux_addr_r;
+reg	[AFI_BANKADDR_WIDTH-1:0] seq_mux_ba_r;
+reg	[AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n_r;
+reg [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke_r;
+reg	[AFI_CS_WIDTH-1:0] seq_mux_cs_n_r;
+reg [AFI_ODT_WIDTH-1:0] seq_mux_odt_r;
+reg	[AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n_r;
+reg	[AFI_CONTROL_WIDTH-1:0] seq_mux_we_n_r;
+reg	[AFI_CONTROL_WIDTH-1:0] seq_mux_rst_n_r;
+
+
+always @(posedge clk)
+begin
+	afi_addr_r  <= afi_addr;
+	afi_ba_r    <= afi_ba;
+	afi_cs_n_r  <= afi_cs_n;
+	afi_cke_r   <= afi_cke;
+	afi_odt_r   <= afi_odt;
+	afi_ras_n_r <= afi_ras_n;
+	afi_cas_n_r <= afi_cas_n;
+	afi_we_n_r  <= afi_we_n;
+	afi_rst_n_r <= afi_rst_n;
+
+	seq_mux_addr_r <= seq_mux_addr;
+	seq_mux_ba_r <= seq_mux_ba;
+	seq_mux_cs_n_r <= seq_mux_cs_n;
+	seq_mux_cke_r <= seq_mux_cke;
+	seq_mux_odt_r <= seq_mux_odt;
+	seq_mux_ras_n_r <= seq_mux_ras_n;
+	seq_mux_cas_n_r <= seq_mux_cas_n;
+	seq_mux_we_n_r <= seq_mux_we_n;
+	seq_mux_rst_n_r <= seq_mux_rst_n;
+end
+
+
+wire [AFI_DQ_WIDTH-1:0] afi_wdata_int;
+assign afi_rdata = phy_mux_rdata;
+assign afi_wdata_int = afi_wdata;
+
+assign afi_rdata_valid = mux_sel ? {AFI_RATE_RATIO{1'b0}} : phy_mux_rdata_valid;
+
+assign seq_mux_rdata       = phy_mux_rdata;
+assign seq_mux_rdata_valid = phy_mux_rdata_valid;
+
+assign phy_mux_addr        = mux_sel ? seq_mux_addr_r : afi_addr_r;
+assign phy_mux_ba    = mux_sel ? seq_mux_ba_r    : afi_ba_r; 
+assign phy_mux_cs_n  = mux_sel ? seq_mux_cs_n_r  : afi_cs_n_r;
+assign phy_mux_cke   = mux_sel ? seq_mux_cke_r   : afi_cke_r;
+assign phy_mux_odt   = mux_sel ? seq_mux_odt_r   : afi_odt_r;
+assign phy_mux_ras_n = mux_sel ? seq_mux_ras_n_r : afi_ras_n_r;
+assign phy_mux_cas_n = mux_sel ? seq_mux_cas_n_r : afi_cas_n_r;
+assign phy_mux_we_n  = mux_sel ? seq_mux_we_n_r  : afi_we_n_r;
+assign phy_mux_dm    = mux_sel ? seq_mux_dm      : afi_dm;
+assign afi_wlat = phy_mux_wlat;
+assign afi_rlat = phy_mux_rlat;
+assign phy_mux_rst_n = mux_sel ? seq_mux_rst_n_r : afi_rst_n_r;
+assign phy_mux_dqs_burst = mux_sel ? seq_mux_dqs_burst : afi_dqs_burst;
+assign phy_mux_wdata         = mux_sel ? seq_mux_wdata         : afi_wdata_int;
+assign phy_mux_wdata_valid   = mux_sel ? seq_mux_wdata_valid   : afi_wdata_valid;
+assign phy_mux_rdata_en      = mux_sel ? seq_mux_rdata_en      : afi_rdata_en;
+assign phy_mux_rdata_en_full = mux_sel ? seq_mux_rdata_en_full : afi_rdata_en_full;
+
+assign afi_cal_success = phy_mux_cal_success;
+assign afi_cal_fail    = phy_mux_cal_fail;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sdc b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sdc
new file mode 100644
index 0000000..5a140c9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sdc
@@ -0,0 +1,112 @@
+## Generated SDC file "sum_peak.out.sdc"
+
+## Copyright (C) 2019  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and any partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors.  Please
+## refer to the applicable agreement for further details, at
+## https://fpgasoftware.intel.com/eula.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"
+
+## DATE    "Mon Jul 31 13:54:17 2023"
+
+##
+## DEVICE  "10M50DAF484C6GES"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {clk_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}]  0.020  
+set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}]  0.020  
+set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}]  0.020  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sv b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sv
new file mode 100644
index 0000000..54474b7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sv
@@ -0,0 +1,311 @@
+/*
+This is for get data from sensor(avalon_streaming source)
+And at the same time, 
+frame counter counts the frameID
+bkg_sub do the bkg calibration and sub bkg depends on the frameID
+and cluster_locate start to locate the position of cluster when the bkg_sub_on is 1
+at the mean time 
+the data after bkg_sub is stored in ram4sig, as well as the first three words(I put it at address 500 to 502)
+
+
+
+*/
+
+
+`timescale 100 ps / 100 ps
+module algo_reconstruction (
+			//Clock/reset
+			input  wire        	clk_clk,                    //                     clk.clk
+			input  wire        	rst_reset,                  //                     connect to int_reset from sensor_interface, to reset frameID to 0;
+			//avalon ST sink
+			input  logic unsigned[31:0] data_in_data,           //  data_in.data
+			output wire        data_in_ready,          //         .ready
+			input  wire        data_in_valid,          //         .valid
+			input  wire [1:0]  data_in_empty,          //         .empty
+			input  wire        data_in_endofpacket,    //         .endofpacket
+			input  wire        data_in_startofpacket,  //         .startofpacket
+			//avalon ST source
+			output wire [31:0] data_out_data,          // data_out.data
+			output wire [1:0]  data_out_empty,         //         .empty
+			output wire        data_out_endofpacket,   //         .endofpacket
+			output wire        data_out_startofpacket, //         .startofpacket
+			input  wire        data_out_ready,         //         .ready  the UDP is ready
+			output wire        data_out_valid,          //         .valid
+
+			output wire[26:0]	 frameID, // for assign signal in tb simulation
+			output wire bkg_sub_on,
+			output wire rst_frame,
+				 
+			//data for sig after bkg subtraction
+			input wire			   sig_rdclk,						//the read port for sig_ram
+			input wire[8:0]		sig_rdaddress,             //0~319 for data. 500~502 for the 3 words head
+			output wire[31:0]		sig_out,
+			output reg 			sig_ram_last,
+
+			//the output of cluster_locate
+			output wire[8:0]		sig_ch_left,
+			output wire[8:0]		sig_ch_right,
+			output wire				has_cluster,
+			output wire				no_cluster
+		
+			
+	);
+
+
+		//set a frameID counter
+		//frameID + 1 at the rising edge of data_in_startofpacket
+		//wire[26:0] frameID;
+		frame_counter framectr(
+			.clk_clk(clk_clk),
+			.rst_reset(rst_reset),
+			.sig(data_in_startofpacket),
+			.frame_Num(frameID)
+		);
+		
+
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 5'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 5'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 5'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 5'd3;	//sending third word :				
+	localparam STATE_DATA_PRO	= 5'd4;	//blocking data do calculation
+	localparam STATE_DATA_NEXT  = 5'd7;  //sending data
+	localparam STATE_LOC	= 5'd5;	//calculatebb
+	
+	
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+	localparam WORDS_TO_SEND = 163;
+
+	//the number of clocks for STATE_DATA_PRO
+	reg [5:0] delay_ctr;
+	localparam DELAY_CLOCKS = 3; 
+	
+	// for sum
+	reg[31:0] sum_all;
+	
+	//the bkg-ram
+	wire[15:0] bkg_signal0;
+	wire[15:0] bkg_signal1;
+	wire[31:0] bkg_input_data;
+	
+	//signal after subtract background
+	//got the background signal at the third clock in STATE_DATA_PRO
+	//and subtract it to 16 bit by giving up the LSM, i.e. divide 2. 
+	reg [16:0] signal0_17bit;
+	reg [16:0] signal1_17bit;
+	wire[15:0] signal0;
+	wire[15:0] signal1;
+	
+	assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
+	assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
+	
+	bkg_ram bkg_but0(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_reset),
+		.frameID(frameID[26:0]),
+		.address(tx_ctr[8:0]), 
+		.data_in_data(bkg_input_data[31:16]),
+		.bkg_signal(bkg_signal0),
+		.bkg_sub_status(bkg_sub_on)
+	); 
+	
+	bkg_ram bkg_but1(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_reset),
+		.frameID(frameID[26:0]),
+		.address(tx_ctr[8:0]), 
+		.data_in_data(bkg_input_data[15:0]),
+		.bkg_signal(bkg_signal1)
+	); 
+	
+	assign bkg_input_data = (state==STATE_DATA_NEXT)?~data_in_data:15'b0;
+	
+	
+		//The state machine
+	always @(posedge clk_clk or posedge rst_reset)
+	begin 
+		if (rst_reset)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+						tx_ctr <= 0;
+					end
+				end
+				STATE_WORD0:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_WORD1;
+					tx_ctr <= tx_ctr+ 1'b1;
+					end
+				end
+				STATE_WORD1:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_WORD2;
+					tx_ctr <= tx_ctr +1'b1;
+					end
+				end
+				STATE_WORD2:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_DATA_PRO;
+					tx_ctr <= tx_ctr +1'b1;
+					delay_ctr <= DELAY_CLOCKS -1;
+					end
+				end
+				STATE_DATA_PRO:
+				begin
+					delay_ctr <= delay_ctr -1;
+					if (delay_ctr == 0)
+					begin
+						state <= STATE_DATA_NEXT;
+						delay_ctr <= DELAY_CLOCKS - 1;
+						signal0_17bit <= {1'b0,~data_in_data[31:16]}-{1'b0,bkg_signal0};
+					   signal1_17bit <= {1'b0,~data_in_data[15:0]}-{1'b0,bkg_signal1};
+					end
+				end
+				STATE_DATA_NEXT:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1'b1;
+						if (tx_ctr == WORDS_TO_SEND -1)	//last word, size matches
+							state <= STATE_LOC;
+						else
+							state <= STATE_DATA_PRO;	
+					end
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+		
+	assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready; 
+	assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1 : 0; 
+	//assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)? data_in_data: 0;
+	assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
+									(state == STATE_DATA_NEXT)? {~signal0,~signal1}: 0;
+	assign data_out_startofpacket = data_in_startofpacket;	
+	assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1 : 0;	
+	assign data_out_empty = 0;
+	
+	//the signal indicate the signal after bkg sub is ready or not
+	wire sub_bkg_signal_ready;
+	assign sub_bkg_signal_ready = (delay_ctr == 0)? 1 :0;
+	//the rst signal for every frame
+	//wire rst_frame;
+	assign rst_frame = data_in_startofpacket || rst_reset;
+	
+	//the cluster_locating part
+	//it is built by the fact that regardless data_out_ready signal, the STATE_DATA_PRO will go to STATE_DATA_NEXT
+	//so the signal after bkg sub will continue at least two clocks
+	reg[8:0] cl_address;
+	wire[15:0] cl_data_in_data;
+	wire cl_data_in_valid;
+//	reg[8:0] ch_left;
+//	reg[8:0] ch_right;
+//	wire[8:0] sig_ch_left;
+//	wire[8:0] sig_ch_right;
+//	wire has_cluster;
+//	wire no_cluster;
+	
+	cluster_locate cl_but(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_frame),
+		.address(cl_address), 
+		.data_in_data(cl_data_in_data),
+		.data_in_valid(cl_data_in_valid),
+		.sig_ch_left(sig_ch_left),
+		.sig_ch_right(sig_ch_right),
+		.has_cluster(has_cluster),
+		.no_cluster(no_cluster)
+	); 
+
+		
+	reg[2:0] state_clu;
+	localparam STATE_CLU_IDLE = 0;
+	localparam STATE_CLU_FIRST = 1;
+	localparam STATE_CLU_SECOND = 3;
+	
+	assign cl_data_in_data = (state_clu == STATE_CLU_FIRST)? signal0:
+										(state_clu == STATE_CLU_SECOND)? signal1: 0;
+	assign cl_data_in_valid = (bkg_sub_on & (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND))? 1'b1: 1'b0;
+	
+	always @ (posedge clk_clk or posedge rst_frame)
+	begin
+		if (rst_frame)
+		begin
+			state_clu <= STATE_CLU_IDLE;
+			cl_address <= 9'b0;
+		end
+		else case(state_clu)
+		STATE_CLU_IDLE:
+		begin
+			if (sub_bkg_signal_ready)
+				state_clu <= STATE_CLU_FIRST;
+		end
+		STATE_CLU_FIRST:
+		begin
+			state_clu <= STATE_CLU_SECOND;
+			cl_address <= cl_address + 1'b1;
+		end
+		STATE_CLU_SECOND:
+		begin
+			state_clu <= STATE_CLU_IDLE;
+			cl_address <= cl_address + 1'b1;
+		end
+		default:
+			state_clu <= STATE_CLU_IDLE;
+		endcase
+	end
+	
+	
+	//when bkg_sub is not on, store the original data
+	//store the signal after bkg_sub in ram
+	//the first there words are at address 500~502
+	wire sig_ram_wren;
+	wire[31:0] sig_ram_data;
+	wire[8:0] sig_wraddress;
+	
+	
+	ram4sig sig_ram (
+	.data(sig_ram_data),
+	.rdaddress(sig_rdaddress),
+	.rdclock(sig_rdclk),
+	.wraddress(sig_wraddress),
+	.wrclock(clk_clk),
+	.wren(sig_ram_wren),
+	.q(sig_out)
+	);
+	
+	assign sig_ram_wren = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND)? 1: 0;
+	assign sig_wraddress = (state == STATE_WORD0)? 9'd500:
+								  (state == STATE_WORD1)? 9'd501:
+								  (state == STATE_WORD2)? 9'd502: cl_address;
+	assign sig_ram_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data: {16'b0,cl_data_in_data};
+	assign sig_ram_last = (state == STATE_LOC)? 1'b1: 1'b0;
+	
+			
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.v b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.v
new file mode 100644
index 0000000..0802a6f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.v
@@ -0,0 +1,329 @@
+// sum_interface.v
+
+
+
+`timescale 1 ps / 1 ps
+
+module algo_reconstruction (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		  
+		//Avalon ST receiver
+		input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+	
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty       	//                        .empty
+		
+		
+    );
+
+	 
+	 
+	 
+	 
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset;
+	end
+
+	
+	 //Very important globals
+	reg[31:0] 	rx_buffer[162:0];		//Data to receive: 3 words header plus sensor data
+	
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[31:0] transmit_buffer[162:0]; //DATA to transmit, the last word is Sum_all.
+	
+	 //********************** Avalon receiver ************************
+	 /*
+		The receiver is used to receive data from sensor interface
+		And a simple calculation
+	*/
+
+	 reg [1:0] data_in_state;
+	 localparam DATA_IN_STATE_IDLE = 0; //waiting for high
+	// localparam DATA_IN_VALID = 5; //valid wait for start packet 
+	 localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
+	 localparam DATA_IN_STATE_FINISH = 3; // finish receiveing to run algorithm 
+	 localparam DATA_IN_STATE_LOCK = 2; //roll to IDLE
+	 
+	 localparam WORDS_TO_RECEIVE = 163; 
+	 localparam WORDS_TO_SEND = 163;	
+	 
+	 integer i;	//for generate loops
+	 
+	 //registers to drive input pins of ST interfaces
+	 
+	 reg reg_in_ready;
+		
+		//Helper stuff
+	reg[15:0]  rx_ctr; //counter of receive data worDS_TO_RECEIVE
+	reg[31:0] sum_all; //
+	reg[31:0] sum_high;
+	reg[31:0] sum_low;
+	
+	
+	
+	//the threshold bkg subtraction process
+	wire[15:0]	channel_ctr0; //channel_ctr<= 2*rx_ctr -6
+	wire[15:0]	channel_ctr1;
+	assign channel_ctr0 = (rx_ctr>2'b00)? (((rx_ctr-2'b01)<<1)): 16'h1FE; 
+	assign channel_ctr1 = channel_ctr0 + 1'b1;
+	wire[15:0] bkg0;
+	wire[15:0] bkg1;
+	
+//bkg	bkg_inst0(
+//	.address ( channel_ctr0[8:0]),
+//	.clock ( clk_clk),
+//	.q ( bkg0)
+//	);
+//
+//bkg	bkg_inst1(
+//	.address ( channel_ctr1[8:0]),
+//	.clock ( clk_clk),
+//	.q ( bkg1)
+//	);
+//
+
+rom_bkg	rom_bkg_inst (
+	.address_a ( channel_ctr0[8:0] ),
+	.address_b ( channel_ctr1[8:0] ),
+	.clock ( clk_clk),
+	.q_a ( bkg0),
+	.q_b ( bkg1)
+	);
+
+	
+	// The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if(int_rst)
+		begin
+			data_in_state <= DATA_IN_STATE_IDLE;
+			sum_all <= 0;
+			sum_high <= 0;
+			sum_low <= 0; 
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE:
+				begin
+					if (data_in_valid)
+					begin
+						data_in_state <= DATA_IN_STATE_RECEIVE;
+						rx_ctr <= 0;
+						sum_all <= 0;
+						sum_high <= 0;
+						sum_low <= 0; 
+					end
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin
+					if (data_in_valid & data_in_ready)
+					begin	
+							rx_ctr <= rx_ctr+1;
+							sum_high  <= sum_high + data_in_data[31:16];
+							sum_low <= sum_low+ data_in_data[15:0];	
+
+					end
+					
+					if (rx_ctr == (WORDS_TO_RECEIVE-1))
+					begin
+						data_in_state <= DATA_IN_STATE_FINISH;
+						sum_all <= sum_low +sum_high;
+					end				
+				end
+				DATA_IN_STATE_FINISH:
+				begin
+					data_in_state <= DATA_IN_STATE_LOCK;
+					rx_ctr <= 0;
+				end
+				DATA_IN_STATE_LOCK:
+				begin
+					if (~data_in_valid)
+						data_in_state <= DATA_IN_STATE_IDLE;
+				end
+				
+				default:
+					data_in_state <= DATA_IN_STATE_IDLE;
+			endcase
+	end
+	
+	//Combinational Part
+	
+	always @ (*)
+	begin
+		if (int_rst)
+		begin
+			reg_in_ready <= 0;
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE, DATA_IN_STATE_LOCK:
+				begin
+					reg_in_ready <= 0;
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin
+					if (data_in_startofpacket)
+						reg_in_ready <= 1;
+					if (data_in_ready)   
+						rx_buffer[rx_ctr] <= (rx_ctr>2'b10)?{data_in_data[31:16]-bkg0, data_in_data[15:0]-bkg1}:data_in_data[31:0];
+				end
+				DATA_IN_STATE_FINISH:
+				begin	
+					reg_in_ready <= 0;
+					for (i = 0; i < (WORDS_TO_SEND-1); i = i+1)
+					begin
+						transmit_buffer[i] <= rx_buffer[i];
+					end
+					transmit_buffer[WORDS_TO_SEND-1] <= sum_all;
+				end
+				default:
+				begin
+					reg_in_ready <= 0;
+				end
+			endcase
+	end
+	
+	assign data_in_ready = reg_in_ready;
+
+			
+		//Generate Avalon trigger signal
+	assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
+	
+
+	 
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+
+	
+	
+		//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+			data_out_state <= DATA_OUT_STATE_IDLE;
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+						tx_ctr <= tx_ctr + 1;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+						data_out_state <= DATA_OUT_STATE_LOCK;
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					tx_ctr <= 0;
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+					data_out_state <= DATA_OUT_STATE_IDLE;
+			endcase
+	end
+
+		//Driving bus signals
+	always @( *)
+	begin
+		if (int_rst)
+		begin
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
+				begin
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					reg_valid 		= 1;
+					reg_data[31:0] 		= transmit_buffer[tx_ctr];
+					if (tx_ctr == 0)
+						reg_startofpacket 	= 1;
+					else
+						reg_startofpacket 	= 0;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+					begin
+						reg_endofpacket 	= 1;
+					end
+					else
+						reg_endofpacket 	= 0;
+				end
+				
+				default:
+				begin
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+			endcase
+	end
+
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_bkg.v b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_bkg.v
new file mode 100644
index 0000000..1c32042
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_bkg.v
@@ -0,0 +1,349 @@
+// the interface between sensor_interface and UDP
+// with a sum_signal operation
+// with background subtraction
+// background info is in rom_bkg 
+
+
+
+`timescale 1 ps / 1 ps
+
+module algo_reconstruction (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		  
+		//Avalon ST receiver
+		(* keep *)input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+	
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty       	//                        .empty
+		
+		
+    );
+	 
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset;
+	end
+
+	
+	 //Very important globals
+	reg[31:0] 	rx_buffer[162:0];		//Data to receive: 3 words header plus sensor data
+	
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[31:0] transmit_buffer[162:0]; //DATA to transmit, the last word is Sum_all.
+	
+	 //********************** Avalon receiver ************************
+	 /*
+		The receiver is used to receive data from sensor interface
+		And a simple calculation
+	*/
+
+	 reg [1:0] data_in_state;
+	 localparam DATA_IN_STATE_IDLE = 0; //waiting for high
+	// localparam DATA_IN_VALID = 5; //valid wait for start packet 
+	 localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
+	 localparam DATA_IN_STATE_FINISH = 3; // finish and to copy data from rx_buffer to transmit_buffer;  
+	 localparam DATA_IN_STATE_LOCK_ALGO = 2; // leave for algorithm; currently
+	 
+	 localparam WORDS_TO_RECEIVE = 163; 
+	 localparam WORDS_TO_SEND = 163;	
+	 
+	 integer i;	//for generate loops
+	 
+	 //registers to drive input pins of ST interfaces
+	 
+	 reg reg_in_ready;
+		
+		//Helper stuff
+	reg[15:0]  rx_ctr; //counter of receive data worDS_TO_RECEIVE
+	
+	  // for sum
+	reg[31:0] sum_all; //
+	reg[31:0] sum_high;
+	reg[31:0] sum_low;
+	
+	
+	//the threshold bkg subtraction process
+	wire[31:0]	channel_ctr; //channel_ctr<= 2*rx_ctr
+	reg[31:0] reg_channel_ctr; 
+	assign channel_ctr = reg_channel_ctr;
+	//assign channel_ctr0 = rx_ctr<<1;
+	//assign channel_ctr1 = channel_ctr0 + 1'b1;
+	wire[31:0] bkg;
+	wire[31:0] wire_bkg;
+	
+	wire[31:0] wire_rx_buffer; // the first 3 channel is data_in_data
+	wire[31:0] wire_for_sum; //the first 3 channel is 0
+
+
+	rom_bkg	rom_bkg_inst (
+		.address_a ( channel_ctr[24:16]),
+		.address_b ( channel_ctr[8:0] ),
+		.clock ( clk_clk),
+		.q_a ( bkg[31:16]),
+		.q_b ( bkg[15:0])
+		);
+
+		
+	// The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if(int_rst)
+		begin
+			data_in_state <= DATA_IN_STATE_IDLE;
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE:
+				begin
+					if (data_in_valid & data_in_startofpacket)
+					begin
+						data_in_state <= DATA_IN_STATE_RECEIVE;
+					end
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin									
+					if (data_in_endofpacket)
+					begin
+						data_in_state <= DATA_IN_STATE_LOCK_ALGO;					
+					end				
+				end
+				DATA_IN_STATE_FINISH:
+				begin
+					data_in_state <= DATA_IN_STATE_IDLE;				
+				end
+				DATA_IN_STATE_LOCK_ALGO:
+				begin
+					if (~data_in_valid)
+						data_in_state <= DATA_IN_STATE_FINISH;
+				end			
+				default:
+					data_in_state <= DATA_IN_STATE_IDLE;
+			endcase
+	end
+	
+
+	//Sequential Part for registers
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if(int_rst)
+		begin
+			rx_ctr <= 0;
+			sum_all <= 0;
+			sum_high <= 0;
+			sum_low <= 0;
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE:
+				begin
+					rx_ctr <= 0;
+					sum_all <= 0;
+					sum_high <= 0;
+					sum_low <= 0;
+
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin									
+					rx_ctr <= rx_ctr + 1'b1;
+					reg_channel_ctr[31:16] <= rx_ctr << 1;
+					reg_channel_ctr[15:0] <= (rx_ctr << 1) + 1'b1;	
+					rx_buffer[rx_ctr] <= wire_rx_buffer;
+					sum_high <= sum_high + wire_for_sum[31:16];
+					sum_low <= sum_low + wire_for_sum[15:0];
+
+				end
+				DATA_IN_STATE_FINISH:
+				begin
+					for (i = 0; i < (WORDS_TO_SEND-1); i = i+1)
+					begin
+						transmit_buffer[i] <= rx_buffer[i];
+					end
+					transmit_buffer[WORDS_TO_SEND-1] <= sum_all;// I should add one more state for sum_all				
+				end
+				DATA_IN_STATE_LOCK_ALGO:
+				begin
+					sum_all <= sum_high + sum_low;
+				end			
+					
+			endcase
+	end
+	
+	assign wire_bkg = ((rx_ctr == 0) |(rx_ctr == 1)| (rx_ctr == 2))? 0: bkg; 
+	assign wire_rx_buffer = {data_in_data[31:16]-wire_bkg[31:16], data_in_data[15:0]-wire_bkg[15:0]};
+	assign wire_for_sum = ((rx_ctr == 0) |(rx_ctr == 1) | (rx_ctr == 2))?32'b0:wire_rx_buffer;
+	//Combinational Part
+	always @ (*)
+	begin
+		if (int_rst)
+		begin
+			reg_in_ready <= 0;
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE:
+				begin
+					reg_in_ready <= 0;
+
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin
+					reg_in_ready <= 1;
+				end
+				DATA_IN_STATE_FINISH, DATA_IN_STATE_LOCK_ALGO:
+				begin	
+					reg_in_ready <= 0;				
+				end
+				default:
+				begin
+					reg_in_ready <= 0;
+				end
+			endcase
+	end
+	
+	assign data_in_ready = reg_in_ready;
+
+			
+		//Generate Avalon trigger signal
+	assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
+	
+
+	 
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+
+	
+	
+		//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			data_out_state <= DATA_OUT_STATE_IDLE;
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+						tx_ctr <= tx_ctr + 1;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+						data_out_state <= DATA_OUT_STATE_LOCK;
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					tx_ctr <= 0;
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+				begin
+					data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+			endcase
+	end
+
+		//Driving bus signals
+	always @( *)
+	begin
+		if (int_rst)
+		begin
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
+				begin
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					reg_data[31:0] = transmit_buffer[tx_ctr];	
+					reg_valid 		= 1;
+					if (tx_ctr == 0)
+						reg_startofpacket 	= 1;
+					else
+						reg_startofpacket 	= 0;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+					begin
+						reg_endofpacket 	= 1;
+					end
+					else
+						reg_endofpacket 	= 0;
+				end
+				
+				default:
+				begin
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+			endcase
+	end
+
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_interface.v b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_interface.v
new file mode 100644
index 0000000..b11a2e1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_interface.v
@@ -0,0 +1,283 @@
+// the interface between sensor_interface and UDP packet 
+// avalon_streaming sink and source 
+// words to send/receive is 163
+
+
+
+`timescale 1 ps / 1 ps
+
+module algo_reconstruction (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		  
+		//Avalon ST receiver
+		input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+	
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty       	//                        .empty
+		
+		
+    );
+
+	 
+	 
+	 
+	 
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset;
+	end
+
+	
+	 //Very important globals
+	reg[31:0] 	rx_buffer[162:0];		//Data to receive: 3 words header plus sensor data
+	
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[31:0] transmit_buffer[162:0]; //DATA to transmit
+	
+	 //********************** Avalon receiver ************************
+	 reg [1:0] data_in_state;
+	 localparam DATA_IN_STATE_IDLE = 0; //waiting for high
+	 localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
+	 localparam DATA_IN_STATE_FINISH = 3; // finish receiveing to run algorithm 
+	 localparam DATA_IN_STATE_LOCK = 2; //roll to IDLE
+	 
+	 localparam WORDS_TO_RECEIVE = 163; 
+	 localparam WORDS_TO_SEND = 163;	
+	 
+	 integer i;	//for generate loops
+	 
+	 //registers to drive input pins of ST interfaces
+	 
+	 reg reg_in_ready;
+		
+		//Helper stuff
+	reg[15:0]  rx_ctr; //counter of receive data worDS_TO_RECEIVE
+
+	// The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if(int_rst)
+		begin
+			data_in_state <= DATA_IN_STATE_IDLE;
+
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE:
+				begin
+					if (data_in_valid)
+					begin
+						data_in_state <= DATA_IN_STATE_RECEIVE;
+						rx_ctr <= 0;
+					end
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin
+					if (data_in_valid & data_in_ready)
+					begin						
+							rx_ctr <= rx_ctr+1;					
+					end
+					
+					if (rx_ctr == (WORDS_TO_RECEIVE-1))
+					begin
+						data_in_state <= DATA_IN_STATE_FINISH;
+					end				
+				end
+				DATA_IN_STATE_FINISH:
+				begin
+					data_in_state <= DATA_IN_STATE_LOCK;
+					rx_ctr <= 0;
+				end
+				DATA_IN_STATE_LOCK:
+				begin
+					if (~data_in_valid)
+						data_in_state <= DATA_IN_STATE_IDLE;
+				end
+				
+				default:
+					data_in_state <= DATA_IN_STATE_IDLE;
+			endcase
+	end
+	
+	//Combinational Part
+	
+	always @ (*)
+	begin
+		if (int_rst)
+		begin
+			reg_in_ready <= 0;
+		end
+		else
+			case(data_in_state)
+				DATA_IN_STATE_IDLE, DATA_IN_STATE_LOCK:
+				begin
+					reg_in_ready <= 0;
+				end
+				DATA_IN_STATE_RECEIVE:
+				begin					
+					if (data_in_startofpacket)
+						reg_in_ready <= 1;
+					if (data_in_ready)   
+						rx_buffer[rx_ctr] <= data_in_data[31:0];
+				end				
+				DATA_IN_STATE_FINISH:
+				begin	
+					reg_in_ready <= 0;
+					for (i = 0; i < (WORDS_TO_SEND); i = i+1)
+					begin
+						transmit_buffer[i] <= rx_buffer[i];
+					end
+				end
+				default:
+				begin
+					reg_in_ready <= 0;
+				end
+			endcase
+	end
+	
+	assign data_in_ready = reg_in_ready;
+
+			
+		//Generate Avalon trigger signal
+	assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
+	
+
+	
+	 
+	 
+	 
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+
+	
+	
+		//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+			data_out_state <= DATA_OUT_STATE_IDLE;
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+						tx_ctr <= tx_ctr + 1;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+						data_out_state <= DATA_OUT_STATE_LOCK;
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					tx_ctr <= 0;
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+					data_out_state <= DATA_OUT_STATE_IDLE;
+			endcase
+	end
+
+		//Driving bus signals
+	always @( *)
+	begin
+		if (int_rst)
+		begin
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
+				begin
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					reg_valid 		= 1;
+					reg_data[31:0] 		= transmit_buffer[tx_ctr];
+					if (tx_ctr == 0)
+						reg_startofpacket 	= 1;
+					else
+						reg_startofpacket 	= 0;
+					if (tx_ctr == (WORDS_TO_SEND-1))
+					begin
+						reg_endofpacket 	= 1;
+					end
+					else
+						reg_endofpacket 	= 0;
+				end
+				
+				default:
+				begin
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+				end
+			endcase
+	end
+
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_state.sv b/FPGA_firmware/q_sys/synthesis/submodules/algo_state.sv
new file mode 100644
index 0000000..f048eee
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_state.sv
@@ -0,0 +1,202 @@
+// algo_state
+/*
+Takes an input stream and calculate some value
+
+Remarks:
+- The transfer is performed on the fly, without buffering. Input gets backpressed when needed
+*/
+
+
+`timescale 100 ps / 100 ps
+module algo_reconstruction (
+		//Clock/reset
+      input  wire        	clk_clk,                    //                     clk.clk
+      input  wire        	rst_reset,                  //                     rst.reset
+		
+		//avalon ST sink
+		input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+		//avalon ST source
+		output wire [31:0] data_out_data,          // data_out.data
+		output wire [1:0]  data_out_empty,         //         .empty
+		output wire        data_out_endofpacket,   //         .endofpacket
+		output wire        data_out_startofpacket, //         .startofpacket
+		input  wire        data_out_ready,         //         .ready
+		output wire        data_out_valid          //         .valid
+	);
+
+
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 0;	//waiting for SOP
+	localparam STATE_WORD0	= 1;	//sending first word : 			
+	localparam STATE_WORD1	= 2;	//sending second word: 				
+	localparam STATE_WORD2	= 3;	//sending third word :				
+	localparam STATE_DATA	= 4;	//sending data
+	localparam STATE_CALC	= 5;	//calculate
+	localparam STATE_RESULT	= 6;	//send result//LAST_WORDS
+
+	reg		reg_ready;	//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+	reg		reg_empty;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+	localparam WORDS_TO_SEND = 163;
+
+	// for sum
+	reg[31:0] sum_all;
+		//The state machine
+	always @(posedge clk_clk or posedge rst_reset)
+	begin 
+		if (rst_reset)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+						tx_ctr <= 0;
+					end
+				end
+				STATE_WORD0, STATE_WORD1,STATE_WORD2:
+				begin
+					if (data_out_ready & data_in_valid)
+					begin
+						state <= state + 1;
+						tx_ctr <= tx_ctr +1;
+					end
+				end
+				STATE_DATA:
+				begin
+					if (data_out_ready && data_in_valid)
+					begin
+						tx_ctr <= tx_ctr+1;
+						if (tx_ctr == WORDS_TO_SEND -2)	//last word, size matches
+							state <= STATE_CALC;
+					end
+				end
+				STATE_CALC:
+				begin
+					sum_all <= 32'h1199;
+					state <= STATE_RESULT;
+				end
+				STATE_RESULT:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1;
+						state <= STATE_IDLE;
+					end
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		//Driving bus signals
+	always_comb
+	begin
+		if (rst_reset)
+		begin
+			reg_ready = 0;
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+			reg_empty = 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_WORD0:
+				begin
+					reg_ready 		= data_out_ready;
+					reg_valid 		= 1;
+					reg_data = data_in_data;
+					reg_startofpacket 	= 1;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_WORD1,STATE_WORD2:
+				begin
+					reg_ready 		= 1;
+					reg_valid 		= 1;
+					reg_data 		= data_in_data;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_DATA:
+				begin
+					reg_ready 		= 1;
+					reg_valid 		= 1;
+					reg_data 		= data_in_data;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_CALC:
+				begin
+					reg_ready 		= 1;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_RESULT:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data			= sum_all;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 1;
+					reg_empty 		= 0;
+				end
+
+				default:
+				begin
+					reg_ready = 0;
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket = 0;
+					reg_endofpacket = 0;
+					reg_empty = 0;
+				end
+			endcase
+	end
+
+	
+	assign data_in_ready = reg_ready;
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+	assign data_out_empty = reg_empty;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v b/FPGA_firmware/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
new file mode 100644
index 0000000..2c9db87
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
@@ -0,0 +1,352 @@
+//module algo_top_cl_cali_rms
+//combine bkg_subtraction, cluster_locate, and calibration, and rms
+
+//tested with algo_top_cl_cali_rms_tb.v
+module algo_top_cl_cali_rms(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // 3 + 160 + 4 = 167 words * 32bit 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket , //         .startofpacket	
+	
+
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+
+	//for cluster => will be in register map
+	input wire [7:0] 		CL_THRESHOLD,
+	input wire [7:0] 		CL_SIZE,
+	input wire [7:0]		IN_ALGO_THRESHOLD,
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest
+	
+);
+	//avalon source for header 
+	wire [31:0] header_data;
+	wire			header_ready;
+	wire [1:0]	header_empty;
+	wire			header_endofpacket;
+	wire			header_startofpacket;
+	wire			header_valid;
+	
+	//avalon source for channel data
+	wire [31:0] channel_data;
+	wire			channel_ready;
+	wire [1:0]	channel_empty;
+	wire			channel_endofpacket;
+	wire			channel_startofpacket;
+	wire			channel_valid;
+	
+	//avalon source for result
+	wire [31:0] recon_data;
+	wire			recon_ready;
+	wire [1:0]	recon_empty;
+	wire			recon_endofpacket;
+	wire			recon_startofpacket;
+	wire			recon_valid;
+	
+	/******************** merge three data source together *****************************************/
+	reg [1:0] avalon_sender_state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_HEADER = 2'd1;
+	localparam STATE_CHANNEL = 2'd3;
+	localparam STATE_RECON = 2'd2;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			avalon_sender_state <= STATE_IDLE;
+		end
+		else case(avalon_sender_state)
+		STATE_IDLE:
+		begin
+			if (header_startofpacket)
+				avalon_sender_state <= STATE_HEADER;
+		end
+		STATE_HEADER:
+		begin
+			if (channel_startofpacket)
+				avalon_sender_state <= STATE_CHANNEL;
+		end
+		STATE_CHANNEL:
+		begin
+			if (recon_startofpacket)
+				avalon_sender_state <= STATE_RECON;
+		end
+		STATE_RECON:
+		begin
+			if (recon_endofpacket && to_udp_ready)
+				avalon_sender_state <= STATE_IDLE;
+		end
+		default:
+			avalon_sender_state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	assign to_udp_data = (avalon_sender_state == STATE_HEADER)? header_data: (avalon_sender_state == STATE_CHANNEL)? channel_data: (avalon_sender_state == STATE_RECON)? recon_data: 32'd0;
+	assign header_ready = (avalon_sender_state == STATE_HEADER)? to_udp_ready: 1'b0;
+	assign channel_ready = (avalon_sender_state == STATE_CHANNEL)? to_udp_ready: 1'b0;
+	assign recon_ready = (avalon_sender_state == STATE_RECON)? to_udp_ready: 1'b0;
+	
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (avalon_sender_state == STATE_HEADER)? header_startofpacket: 1'b0;
+	assign to_udp_endofpacket = (avalon_sender_state == STATE_RECON)? recon_endofpacket: 1'b0;
+	assign to_udp_valid = (avalon_sender_state == STATE_HEADER)? header_valid: (avalon_sender_state == STATE_CHANNEL)? channel_valid: (avalon_sender_state == STATE_RECON)? recon_valid: 1'b0;
+	
+		
+	
+	
+	
+	
+	
+	
+	
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[1:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	wire			bkg_sub_on;
+	
+	bkg_subtraction_pipe #(.BKG_FRAME(8192)) bkg_subtraction0( //4 for simulation, 8192 for real firmware setup
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0),
+		.bkg_sub_on			(bkg_sub_on),
+		
+		
+		//3 header
+		.to_udp_data (header_data),           
+		.to_udp_ready(header_ready),          
+		.to_udp_valid (header_valid),          
+		.to_udp_empty (header_empty),          
+		.to_udp_endofpacket (header_endofpacket),    
+		.to_udp_startofpacket (header_startofpacket)
+		
+		
+		
+	);
+	
+	
+	wire [15:0] wire_data1;
+	wire 			wire_ready1;
+	wire			wire_valid1;
+	wire	      wire_empty1;
+	wire			wire_endofpacket1;
+	wire			wire_startofpacket1;
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(wire_data1),
+		.data_out_empty	(wire_empty1),
+		.data_out_endofpacket		(wire_endofpacket1),
+		.data_out_startofpacket		(wire_startofpacket1),
+		.data_out_ready	(wire_ready1),
+		.data_out_valid	(wire_valid1)
+		
+	);
+	
+		//from st_splitter0 to cluster_locate
+		wire [15:0] wire_data2;
+		wire 			wire_ready2;
+		wire			wire_valid2;
+		wire	      wire_empty2;
+		wire			wire_endofpacket2;
+		wire			wire_startofpacket2;
+		
+		//from st_splitter0 to calibration
+		wire [15:0] wire_data3;
+		wire 			wire_ready3;
+		wire			wire_valid3;
+		wire	      wire_empty3;
+		wire			wire_endofpacket3;
+		wire			wire_startofpacket3;
+	
+	st_splitter16 st_splitter0 (
+		.st_splitter16_clk_clk            (clk),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (rst),        // st_splitter16_reset.reset
+		
+		
+		.st_splitter16_in_ready           (wire_ready1),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (wire_valid1),           //                    .valid
+		.st_splitter16_in_startofpacket   (wire_startofpacket1),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (wire_endofpacket1),     //                    .endofpacket
+		.st_splitter16_in_empty           (wire_empty1),           //                    .empty
+		.st_splitter16_in_data            (wire_data1),            //                    .data
+		
+		
+		.st_splitter16_out0_ready         (wire_ready2),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (wire_valid2),         //                    .valid
+		.st_splitter16_out0_startofpacket (wire_startofpacket2), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (wire_endofpacket2),   //                    .endofpacket
+		.st_splitter16_out0_empty         (wire_empty2),         //                    .empty
+		.st_splitter16_out0_data          (wire_data2),          //                    .data
+		
+		
+		.st_splitter16_out1_ready         (wire_ready3),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (wire_valid3),         //                    .valid
+		.st_splitter16_out1_startofpacket (wire_startofpacket3), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (wire_endofpacket3),   //                    .endofpacket
+		.st_splitter16_out1_empty         (wire_empty3),         //                    .empty
+		.st_splitter16_out1_data          (wire_data3)           //                    .data
+	);
+
+
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire has_cluster;
+	wire no_cluster;
+	
+	wire cl_last_channel;
+	cluster_locate cluster_locate0(
+		
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data2),
+		.data_in_ready		(wire_ready2),
+		.data_in_valid		(wire_valid2),
+		.data_in_empty		(wire_empty2),
+		.data_in_startofpacket		(wire_startofpacket2),
+		.data_in_endofpacket			(wire_endofpacket2),
+		
+		.THRESHOLD			({8'b0,CL_THRESHOLD}),
+		.SIZE					({1'b0,CL_SIZE}),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+	
+		.data_in_last		(cl_last_channel)
+	
+	); 
+	
+	
+	wire[8:0]		data_caled_address;
+	wire [15:0]		data_caled;
+	wire				data_caled_rd_enable;
+
+	//when bkg_sub_on is off, it equals to 8192.... the scaled 1 for calibration factor
+	wire [15:0] cali_fac_masked = bkg_sub_on? cali_fac:16'd8192;
+	calibration calibration0(
+	
+	.clk(clk),
+	.rst(rst),
+		
+	.data_in_data		(wire_data3),
+	.data_in_ready		(wire_ready3),
+	.data_in_valid		(wire_valid3),
+	.data_in_empty		(wire_empty3),
+	.data_in_startofpacket		(wire_startofpacket3),
+	.data_in_endofpacket			(wire_endofpacket3),
+	
+	.address		(address),
+	.clken		(clken),
+	.cali_fac	(cali_fac_masked),
+	.waitrequest(waitrequest),
+	
+	.data_caled_address(data_caled_address),
+	.data_caled(data_caled),
+	.data_caled_rd_enable(data_caled_rd_enable),
+
+	.to_udp_data (channel_data),           
+	.to_udp_ready(channel_ready),          
+	.to_udp_valid (channel_valid),          
+	.to_udp_empty (channel_empty),          
+	.to_udp_endofpacket (channel_endofpacket),    
+	.to_udp_startofpacket (channel_startofpacket)
+
+	);
+
+	
+	rms rms0(
+
+
+		.clk(clk),
+		.rst(rst),
+
+		.bkg_sub_on			(bkg_sub_on),
+		.sig_ram_last		(cl_last_channel),
+
+		.sig_rdaddress(data_caled_address),            
+		.sig(data_caled),
+		.sig_rd_eable(data_caled_rd_enable),
+
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+
+		.to_udp_data (recon_data),           
+		.to_udp_ready(recon_ready),          
+		.to_udp_valid (recon_valid),          
+		.to_udp_empty (recon_empty),          
+		.to_udp_endofpacket (recon_endofpacket),    
+		.to_udp_startofpacket (recon_startofpacket)
+
+
+	);
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
new file mode 100644
index 0000000..1cc0eaa
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
@@ -0,0 +1,563 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Title         : (DDR1/2/3,LPDDR1) address and command decoder
+//
+// File          : alt_mem_ddrx_addr_cmd.v
+//
+// Abstract      : Address and command decoder
+///////////////////////////////////////////////////////////////////////////////
+
+//altera message_off 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_addr_cmd
+    # (parameter
+        // Global parameters
+        CFG_PORT_WIDTH_TYPE           = 3,
+        CFG_PORT_WIDTH_OUTPUT_REGD    = 1,
+        CFG_MEM_IF_CHIP               = 1,
+        CFG_MEM_IF_CKE_WIDTH          = 1,    // same width as CS_WIDTH
+        CFG_MEM_IF_ADDR_WIDTH         = 16,   // max supported address bits, must be >= row bits (For ddr3 >=13 even if row=12)
+        CFG_MEM_IF_ROW_WIDTH          = 16,   // max supported row bits
+        CFG_MEM_IF_COL_WIDTH          = 12,   // max supported column bits
+        CFG_MEM_IF_BA_WIDTH           = 3,    // max supported bank bits
+        CFG_CTL_RATE                  = "FULL",
+        CFG_DWIDTH_RATIO              = 2
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        ctl_cal_success,
+        
+        //run-time configuration interface
+        cfg_type,
+        cfg_output_regd,
+        
+        cfg_enable_chipsel_for_sideband, // to indicate should we de-assert cs_n for sideband signal (self refresh and deep power down specific)
+        
+        // AFI interface (Signals from Arbiter block)
+        bg_do_write,
+        bg_do_read,
+        bg_do_burst_chop,
+        bg_do_auto_precharge,
+        bg_do_activate,
+        bg_do_precharge,
+        bg_do_precharge_all,
+        bg_do_refresh,
+        bg_do_self_refresh,
+        bg_do_power_down,
+        bg_do_zq_cal,
+        bg_do_lmr,
+        
+        bg_do_burst_terminate,     //Currently does not exist in arbiter
+        bg_do_deep_pdown,        //Currently does not exist in arbiter
+        
+        // address information
+        bg_to_chip,                    // active high input (one hot)
+        bg_to_bank,
+        bg_to_row,
+        bg_to_col,
+        
+        bg_to_lmr,            //Currently doesn not exist in arbiter
+        lmr_opcode,
+        
+        //output to PHY
+        afi_addr,
+        afi_ba,
+        afi_cke,
+        afi_cs_n,
+        afi_ras_n,
+        afi_cas_n,
+        afi_we_n,
+        afi_rst_n
+    );
+    
+    //=================================================================================================//
+    //        input/output declaration                                                                 //
+    //=================================================================================================//
+    
+    input ctl_clk;
+    input ctl_reset_n;
+    input ctl_cal_success;
+    
+    //run-time configuration input
+    input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
+    input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
+    
+    input cfg_enable_chipsel_for_sideband;
+    
+    // Arbiter command inputs
+    input bg_do_write;
+    input bg_do_read;
+    input bg_do_burst_chop;
+    input bg_do_auto_precharge;
+    input bg_do_activate;
+    input bg_do_precharge;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_precharge_all;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_refresh;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_self_refresh;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_power_down;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_zq_cal;
+    input bg_do_lmr;
+    
+    input bg_do_burst_terminate;
+    input [CFG_MEM_IF_CHIP-1:0]    bg_do_deep_pdown;
+    
+    input   [CFG_MEM_IF_CHIP-1:0]       bg_to_chip;
+    input   [CFG_MEM_IF_BA_WIDTH-1:0]   bg_to_bank;
+    input   [CFG_MEM_IF_ROW_WIDTH-1:0]  bg_to_row;
+    input   [CFG_MEM_IF_COL_WIDTH-1:0]  bg_to_col;
+    input   [CFG_MEM_IF_BA_WIDTH-1:0]   bg_to_lmr;
+    input   [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode;
+    
+    //output
+    output  [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]     afi_cke;
+    output  [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]          afi_cs_n;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                              afi_ras_n;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                              afi_cas_n;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                              afi_we_n;
+    output  [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]      afi_ba;
+    output  [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]    afi_addr;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                              afi_rst_n;
+    
+    //=================================================================================================//
+    //        reg/wire declaration                                                                     //
+    //=================================================================================================//
+    
+    wire bg_do_write;
+    wire bg_do_read;
+    wire bg_do_burst_chop;
+    wire bg_do_auto_precharge;
+    wire bg_do_activate;
+    wire bg_do_precharge;
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_precharge_all;
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_refresh;
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_self_refresh;
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_power_down;
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_zq_cal;
+    wire bg_do_lmr;
+    
+    wire [CFG_MEM_IF_CHIP-1:0]    bg_do_deep_pdown; 
+    wire bg_do_burst_terminate;
+    
+    reg [CFG_MEM_IF_CHIP-1:0]    do_self_refresh;
+    reg [CFG_MEM_IF_CHIP-1:0]    do_power_down;
+    reg [CFG_MEM_IF_CHIP-1:0]    do_deep_pdown;
+    
+    reg [CFG_MEM_IF_CHIP-1:0]    do_self_refresh_r;
+    reg [CFG_MEM_IF_CHIP-1:0]    do_power_down_r;
+    reg [CFG_MEM_IF_CHIP-1:0]    do_deep_pdown_r;
+    
+    wire  [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]       afi_cke;
+    wire  [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]            afi_cs_n;
+    wire  [(CFG_DWIDTH_RATIO/2) - 1:0]                                afi_ras_n;
+    wire  [(CFG_DWIDTH_RATIO/2) - 1:0]                                afi_cas_n;
+    wire  [(CFG_DWIDTH_RATIO/2) - 1:0]                                afi_we_n;
+    wire  [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]        afi_ba;
+    wire  [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]      afi_addr;
+    wire  [(CFG_DWIDTH_RATIO/2) - 1:0]                                afi_rst_n;
+    
+    
+    reg   [(CFG_MEM_IF_CKE_WIDTH) - 1:0]     int_cke;
+    reg   [(CFG_MEM_IF_CKE_WIDTH) - 1:0]     int_cke_r;
+    reg   [(CFG_MEM_IF_CHIP) - 1:0]          int_cs_n;
+    reg                                      int_ras_n;
+    reg                                      int_cas_n;
+    reg                                      int_we_n;
+    reg [(CFG_MEM_IF_BA_WIDTH) - 1:0]        int_ba;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]      int_addr;
+    
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]       combi_cke  ;
+    reg [(CFG_MEM_IF_CHIP) - 1:0]            combi_cs_n ;
+    reg                                         combi_ras_n;
+    reg                                      combi_cas_n;
+    reg                                         combi_we_n ;
+    reg [(CFG_MEM_IF_BA_WIDTH) - 1:0]        combi_ba   ;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]      combi_addr ;
+    
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]       combi_cke_r  ;
+    reg [(CFG_MEM_IF_CHIP) - 1:0]            combi_cs_n_r ;
+    reg                                         combi_ras_n_r;
+    reg                                      combi_cas_n_r;
+    reg                                         combi_we_n_r ;
+    reg [(CFG_MEM_IF_BA_WIDTH) - 1:0]        combi_ba_r   ;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]      combi_addr_r ;
+    
+    wire    [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_row;
+    wire    [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] temp_col;
+    wire    [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col;
+    wire                                    col12;
+    
+    wire     [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col_r;
+    
+    reg [CFG_MEM_IF_CHIP-1:0]   chip_in_self_refresh;
+    
+    //=================================================================================================//
+    
+    generate
+        if (CFG_MEM_IF_ADDR_WIDTH > CFG_MEM_IF_ROW_WIDTH)
+            begin
+                assign int_row      = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_ROW_WIDTH){1'b0}},bg_to_row};
+            end
+        else
+            begin
+                assign int_row      = bg_to_row;
+            end
+    endgenerate
+    
+    assign temp_col     = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_COL_WIDTH){1'b0}},bg_to_col};
+    assign afi_rst_n    = {(CFG_DWIDTH_RATIO/2){1'b1}};
+    assign col12        = (cfg_type == `MMR_TYPE_DDR3) ? ~bg_do_burst_chop : temp_col[11]; //DDR3
+    
+    generate
+        if (CFG_MEM_IF_ADDR_WIDTH < 13)
+            begin
+                assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-1:10],bg_do_auto_precharge,temp_col[9:0]};
+            end
+        else if (CFG_MEM_IF_ADDR_WIDTH == 13)
+            begin
+                assign int_col = {col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
+            end
+        else
+            begin
+                assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-3:11],col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
+            end
+    endgenerate
+    
+    generate
+        if (CFG_DWIDTH_RATIO == 2)
+            begin
+                assign afi_cke      = int_cke;
+                assign afi_cs_n     = int_cs_n;
+                assign afi_ras_n    = int_ras_n;
+                assign afi_cas_n    = int_cas_n;
+                assign afi_we_n     = int_we_n;
+                assign afi_ba       = int_ba;
+                assign afi_addr     = int_addr;
+            end
+        else
+            begin
+                assign afi_cke      = {int_cke,int_cke_r};
+                assign afi_cs_n     = {int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};    // to provide time for addr bus to settle at high freq, cs sent on 2nd phase
+                assign afi_ras_n    = {int_ras_n,int_ras_n};
+                assign afi_cas_n    = {int_cas_n,int_cas_n};
+                assign afi_we_n     = {int_we_n,int_we_n};
+                assign afi_ba       = {int_ba,int_ba};
+                assign afi_addr     = {int_addr,int_addr};
+            end
+    endgenerate
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)            // aligns cke with cs for slf rfsh & pwrdwn(lpddr1)which is defined only when cs_n goes low
+        begin
+            if (!ctl_reset_n)
+                int_cke_r   <=  {(CFG_MEM_IF_CKE_WIDTH){1'b0}};
+            else
+                int_cke_r   <=  int_cke;
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)            // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
+        begin
+            if (!ctl_reset_n)
+                chip_in_self_refresh   <=  {(CFG_MEM_IF_CHIP){1'b0}};
+            else
+                if ((bg_do_self_refresh) || (bg_do_deep_pdown && cfg_type == `MMR_TYPE_LPDDR1)) //LPDDDR1
+                    chip_in_self_refresh   <=  bg_to_chip;
+                else
+                    chip_in_self_refresh   <=  {(CFG_MEM_IF_CHIP){1'b0}};
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    combi_cke_r    <=  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                    combi_cs_n_r   <=  {(CFG_MEM_IF_CHIP){1'b1}};
+                    combi_ras_n_r  <=  1'b1;
+                    combi_cas_n_r  <=  1'b1;
+                    combi_we_n_r   <=  1'b1;
+                    combi_ba_r     <=  {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                    combi_addr_r   <=  {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                end
+            else
+                begin
+                    combi_cke_r    <=  combi_cke;
+                    combi_cs_n_r   <=  combi_cs_n;
+                    combi_ras_n_r  <=  combi_ras_n;
+                    combi_cas_n_r  <=  combi_cas_n;
+                    combi_we_n_r   <=  combi_we_n;
+                    combi_ba_r     <=  combi_ba;
+                    combi_addr_r   <=  combi_addr;
+                end
+        end
+    
+    always @(*)
+        begin
+            if (cfg_output_regd)
+                begin
+                    int_cke     =  combi_cke_r;
+                    int_cs_n    =  combi_cs_n_r;
+                    int_ras_n   =  combi_ras_n_r;
+                    int_cas_n   =  combi_cas_n_r;
+                    int_we_n    =  combi_we_n_r;
+                    int_ba      =  combi_ba_r;
+                    int_addr    =  combi_addr_r;
+                end
+            else
+                begin
+                    int_cke     =  combi_cke;
+                    int_cs_n    =  combi_cs_n;
+                    int_ras_n   =  combi_ras_n;
+                    int_cas_n   =  combi_cas_n;
+                    int_we_n    =  combi_we_n;
+                    int_ba      =  combi_ba;
+                    int_addr    =  combi_addr;
+                end
+        end
+    
+    //CKE generation block
+    always @(*)
+        begin
+            if (ctl_cal_success)
+               begin 
+                    combi_cke = ~(bg_do_self_refresh | bg_do_power_down | bg_do_deep_pdown);
+               end
+            else
+               begin
+                    combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+               end
+        end
+    
+    //Pulse generator for self refresh, power down and deep power down
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
+                    do_power_down_r   <= {(CFG_MEM_IF_CHIP){1'b0}};
+                    do_deep_pdown_r   <= {(CFG_MEM_IF_CHIP){1'b0}};
+                end
+            else
+                begin
+                   do_self_refresh_r <= ~bg_do_self_refresh;
+                   do_power_down_r   <= ~bg_do_power_down;
+                   do_deep_pdown_r   <= ~bg_do_deep_pdown;
+                end
+        end
+    
+    always @(*)
+         begin
+            do_self_refresh = bg_do_self_refresh & do_self_refresh_r;
+            do_power_down   = bg_do_power_down & do_power_down_r;
+            do_deep_pdown   = bg_do_deep_pdown & do_deep_pdown_r;
+         end
+    
+    always @(*)        //All Command inputs are mutually exclusive
+        begin
+            if (ctl_cal_success)
+                begin
+                    // combi_cke     =   {(CFG_MEM_IF_CKE_WIDTH){1'b1}};        //Should we put default condition into if(!bg_do_refresh && !bg_do_activate....)??
+                    combi_cs_n    =   {(CFG_MEM_IF_CHIP){1'b1}};
+                    combi_ras_n   =   1'b1;
+                    combi_cas_n   =   1'b1;
+                    combi_we_n    =   1'b1;
+                    combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                    
+                    if (|bg_do_refresh)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_do_refresh;
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b0;
+                            combi_we_n    =  1'b1;
+                            combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                            combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                        end
+                    
+                    if (|bg_do_precharge_all)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_do_precharge_all;
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b1;
+                            combi_we_n    =  1'b0;
+                            combi_ba      =  bg_to_bank;
+                            combi_addr[10]=  1'b1;
+                        end
+                    
+                    if (bg_do_activate)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_to_chip;
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b1;
+                            combi_we_n    =  1'b1;
+                            combi_ba      =  bg_to_bank;
+                            combi_addr    =  int_row;
+                        end
+                    
+                    if (bg_do_precharge)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_to_chip;
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b1;
+                            combi_we_n    =  1'b0;
+                            combi_ba      =  bg_to_bank;
+                            combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                        end
+                    
+                    if (bg_do_write)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_to_chip;
+                            combi_ras_n   =  1'b1;
+                            combi_cas_n   =  1'b0;
+                            combi_we_n    =  1'b0;
+                            combi_ba      =  bg_to_bank;
+                            combi_addr    =  int_col;
+                        end
+                    
+                    if (bg_do_read)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                            combi_cs_n    =  ~bg_to_chip;
+                            combi_ras_n   =  1'b1;
+                            combi_cas_n   =  1'b0;
+                            combi_we_n    =  1'b1;
+                            combi_ba      =  bg_to_bank;
+                            combi_addr    =  int_col;
+                        end
+                    
+                    if (|do_power_down)
+                        begin
+                            // combi_cke     =  ~bg_to_chip;
+                            combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                            combi_ras_n   =  1'b1;
+                            combi_cas_n   =  1'b1;
+                            combi_we_n    =  1'b1;
+                            combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                            combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                      end
+                    
+                    if (|do_deep_pdown)                                    //Put assertion for memory type ddr2 and ddr3 as an error
+                        begin
+                            // combi_cke     =  ~bg_to_chip;
+                            if (cfg_enable_chipsel_for_sideband)
+                                begin
+                                    combi_cs_n    =  ~do_deep_pdown;                // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
+                                end
+                            else
+                                begin
+                                    combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                end
+                            
+                            combi_ras_n   =  1'b1;
+                            combi_cas_n   =  1'b1;
+                            combi_we_n    =  1'b0;
+                            combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                            combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                      end
+                    
+                    if (|do_self_refresh)
+                        begin
+                            // combi_cke     =  ~bg_to_chip;
+                            if (cfg_enable_chipsel_for_sideband)
+                                begin
+                                    combi_cs_n    =  ~do_self_refresh;                // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
+                                end
+                            else
+                                begin
+                                    combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                end
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b0;
+                            combi_we_n    =  1'b1;
+                            combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                            combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                        end
+                    
+                    if (|bg_do_zq_cal) // Only short zqcal supported
+                        begin
+                            if (cfg_type == `MMR_TYPE_DDR3) //DDR3
+                                begin
+                                    // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                                    combi_cs_n    =  ~bg_do_zq_cal;
+                                    combi_ras_n   =  1'b1;
+                                    combi_cas_n   =  1'b1;
+                                    combi_we_n    =  1'b0;
+                                    combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                                end
+                            else // Should we flag error or issue as NOP
+                                begin
+                                    // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                                    combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                    combi_ras_n   =  1'b1;
+                                    combi_cas_n   =  1'b1;
+                                    combi_we_n    =  1'b1;
+                                    combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                                end
+                        end
+                    if (bg_do_lmr)
+                        begin
+                            // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};                // to support chng rfsh time based on temp
+                            combi_cs_n    =  ~bg_to_chip;
+                            combi_ras_n   =  1'b0;
+                            combi_cas_n   =  1'b0;
+                            combi_we_n    =  1'b0;
+                            combi_ba      =  bg_to_lmr;
+                            combi_addr    =  lmr_opcode;
+                        end
+                    if (bg_do_burst_terminate)
+                        begin
+                            if (cfg_type == `MMR_TYPE_LPDDR1) //lpddr1
+                                begin
+                                    // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                                    combi_cs_n    =  ~bg_to_chip;
+                                    combi_ras_n   =  1'b1;
+                                    combi_cas_n   =  1'b1;
+                                    combi_we_n    =  1'b0;
+                                    combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                                end
+                            else
+                                begin
+                                    // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                                    combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                    combi_ras_n   =  1'b1;
+                                    combi_cas_n   =  1'b1;
+                                    combi_we_n    =  1'b1;
+                                    combi_ba      =   {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                                end
+                        end
+                end
+            else
+                begin
+                    // combi_cke     =  {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+                    combi_cs_n    =  {(CFG_MEM_IF_CHIP){1'b1}};
+                    combi_ras_n   =  1'b1;
+                    combi_cas_n   =  1'b1;
+                    combi_we_n    =  1'b1;
+                    combi_ba      =  {(CFG_MEM_IF_BA_WIDTH){1'b0}};
+                    combi_addr    =  {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                end
+        end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
new file mode 100644
index 0000000..783f0c6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
@@ -0,0 +1,808 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_addr_cmd_wrap
+# ( parameter
+    CFG_MEM_IF_CHIP                 =   2,
+    CFG_MEM_IF_CKE_WIDTH            =   2,  // same width as CS_WIDTH
+    CFG_MEM_IF_ADDR_WIDTH           =   16, // max supported address bits, must be >= row bits
+    CFG_MEM_IF_ROW_WIDTH            =   16, // max supported row bits
+    CFG_MEM_IF_COL_WIDTH            =   12, // max supported column bits  
+    CFG_MEM_IF_BA_WIDTH             =   3,  // max supported bank bits
+    CFG_LPDDR2_ENABLED              =   1,
+    CFG_PORT_WIDTH_TYPE             =   3,
+    CFG_DWIDTH_RATIO                =   2,
+    CFG_AFI_INTF_PHASE_NUM          =   2,
+    CFG_LOCAL_ID_WIDTH              =   8,
+    CFG_DATA_ID_WIDTH               =   4,
+    CFG_INT_SIZE_WIDTH              =   4,
+    CFG_ODT_ENABLED                 =   1,
+    CFG_MEM_IF_ODT_WIDTH            =   2,
+    CFG_PORT_WIDTH_CAS_WR_LAT       =   5,
+    CFG_PORT_WIDTH_TCL              =   5,
+    CFG_PORT_WIDTH_ADD_LAT          =   5,
+    CFG_PORT_WIDTH_WRITE_ODT_CHIP   =   4,
+    CFG_PORT_WIDTH_READ_ODT_CHIP    =   4,
+    CFG_PORT_WIDTH_OUTPUT_REGD      =   2
+)
+(
+    
+    ctl_clk,
+    ctl_reset_n,
+    ctl_cal_success,
+    
+    cfg_type,
+    cfg_tcl,
+    cfg_cas_wr_lat,
+    cfg_add_lat,
+    cfg_write_odt_chip,
+    cfg_read_odt_chip,
+    cfg_burst_length,
+    
+    cfg_output_regd_for_afi_output,
+    
+    // burst generator command signals
+    bg_do_write,
+    bg_do_read,
+    bg_do_burst_chop,
+    bg_do_burst_terminate,
+    bg_do_auto_precharge,
+    bg_do_activate,
+    bg_do_precharge,
+    bg_do_precharge_all,
+    bg_do_refresh,
+    bg_do_self_refresh,
+    bg_do_power_down,
+    bg_do_deep_pdown,
+    bg_do_rmw_correct,
+    bg_do_rmw_partial,
+    
+    bg_do_lmr_read,
+    bg_do_refresh_1bank,
+    
+    bg_do_zq_cal,
+    bg_do_lmr,
+    
+    bg_localid,
+    bg_dataid,
+    bg_size,
+    
+    // burst generator address signals
+    bg_to_chip, // active high input (one hot)
+    bg_to_bank,
+    bg_to_row,
+    bg_to_col,
+    bg_to_lmr,
+    lmr_opcode,
+    
+    //output
+    afi_cke,
+    afi_cs_n,
+    afi_ras_n,
+    afi_cas_n,
+    afi_we_n,
+    afi_ba,
+    afi_addr,
+    afi_rst_n,
+    afi_odt
+);
+
+    // -----------------------------
+    // local parameter declaration
+    // -----------------------------
+    
+    localparam CFG_FR_DWIDTH_RATIO = 2;
+    
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+    
+    input                                                             ctl_clk                       ;
+    input                                                             ctl_reset_n                   ;
+    input                                                             ctl_cal_success               ;
+    
+    //run-time csr chain input
+    input   [CFG_PORT_WIDTH_TYPE                             - 1 : 0] cfg_type                      ;
+    input   [CFG_PORT_WIDTH_TCL                              - 1 : 0] cfg_tcl                       ;
+    input   [CFG_PORT_WIDTH_CAS_WR_LAT                       - 1 : 0] cfg_cas_wr_lat                ;
+    input   [CFG_PORT_WIDTH_ADD_LAT                          - 1 : 0] cfg_add_lat                   ;
+    input   [CFG_PORT_WIDTH_WRITE_ODT_CHIP                   - 1 : 0] cfg_write_odt_chip            ;
+    input   [CFG_PORT_WIDTH_READ_ODT_CHIP                    - 1 : 0] cfg_read_odt_chip             ;
+    input   [4:0]                                                     cfg_burst_length              ;
+    
+    //output regd signal from rdwr_tmg block
+    input   [CFG_PORT_WIDTH_OUTPUT_REGD                      - 1 : 0] cfg_output_regd_for_afi_output;
+    
+    //command inputs
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write                   ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read                    ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop              ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate         ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_auto_precharge          ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_correct             ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_partial             ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate                ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge               ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_precharge_all           ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_refresh                 ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_self_refresh            ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_power_down              ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_deep_pdown              ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_zq_cal                  ;
+    input   [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_lmr                     ;
+    
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip                    ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank                    ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row                     ;
+    input   [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col                     ;
+    
+    input                                                             bg_do_lmr_read                ;
+    input                                                             bg_do_refresh_1bank           ;
+    
+    input    [7:0]                                                    bg_to_lmr                     ;
+    
+    input   [CFG_LOCAL_ID_WIDTH                              - 1 : 0] bg_localid                    ;
+    input   [CFG_DATA_ID_WIDTH                               - 1 : 0] bg_dataid                     ;
+    input   [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_size                       ;
+    
+    input   [CFG_MEM_IF_ADDR_WIDTH-1:0]                              lmr_opcode                     ;
+    
+    output  [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]    afi_cke                        ;
+    output  [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]         afi_cs_n                       ;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_ras_n                      ;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_cas_n                      ;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_we_n                       ;
+    output  [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]     afi_ba                         ;
+    output  [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]   afi_addr                       ;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_rst_n                      ;
+    output  [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]    afi_odt                        ;
+    
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+    
+    reg     [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]    afi_cke                        ;
+    reg     [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]         afi_cs_n                       ;
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_ras_n                      ;
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_cas_n                      ;
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_we_n                       ;
+    reg     [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]     afi_ba                         ;
+    reg     [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]   afi_addr                       ;
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                             afi_rst_n                      ;
+    reg     [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]    afi_odt                        ;
+    
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+    
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                               afi_rmw_correct                                       ;
+    reg     [(CFG_DWIDTH_RATIO/2) - 1:0]                               afi_rmw_partial                                       ;
+    
+    wire    [CFG_MEM_IF_CKE_WIDTH - 1:0]                               int_afi_cke                 [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire    [CFG_MEM_IF_CHIP- 1:0]                                     int_afi_cs_n                [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_ras_n               [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_cas_n               [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_we_n                [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire    [CFG_MEM_IF_BA_WIDTH - 1:0]                                int_afi_ba                  [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire    [CFG_MEM_IF_ADDR_WIDTH-1:0]                                int_afi_addr                [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_rst_n               [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_rmw_correct         [(CFG_DWIDTH_RATIO/2)-1:0];
+    wire                                                               int_afi_rmw_partial         [(CFG_DWIDTH_RATIO/2)-1:0];
+    
+    reg     [CFG_MEM_IF_CKE_WIDTH - 1:0]                               int_afi_cke_r               [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg     [CFG_MEM_IF_CHIP- 1:0]                                     int_afi_cs_n_r              [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_ras_n_r             [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_cas_n_r             [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_we_n_r              [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg     [CFG_MEM_IF_BA_WIDTH - 1:0]                                int_afi_ba_r                [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg     [CFG_MEM_IF_ADDR_WIDTH-1:0]                                int_afi_addr_r              [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_rst_n_r             [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_rmw_correct_r       [(CFG_DWIDTH_RATIO/2)-1:0];
+    reg                                                                int_afi_rmw_partial_r       [(CFG_DWIDTH_RATIO/2)-1:0];
+    
+    reg     [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]   phase_afi_cke               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]        phase_afi_cs_n              [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_ras_n             [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_cas_n             [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_we_n              [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]    phase_afi_ba                [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]  phase_afi_addr              [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_rst_n             [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_rmw_correct       [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            phase_afi_rmw_partial       [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]   int_ddrx_afi_cke            [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]        int_ddrx_afi_cs_n           [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_ras_n          [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_cas_n          [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_we_n           [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]    int_ddrx_afi_ba             [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]  int_ddrx_afi_addr           [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_rst_n          [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_rmw_correct    [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_ddrx_afi_rmw_partial    [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]   int_lpddr2_afi_cke          [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]        int_lpddr2_afi_cs_n         [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]  int_lpddr2_afi_addr         [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_lpddr2_afi_rst_n        [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_lpddr2_afi_rmw_correct  [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            int_lpddr2_afi_rmw_partial  [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]   mux_afi_cke                 [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]        mux_afi_cs_n                [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_ras_n               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_cas_n               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_we_n                [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]    mux_afi_ba                  [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]  mux_afi_addr                [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_rst_n               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_rmw_correct         [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            mux_afi_rmw_partial         [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]   fr_afi_cke                  ;
+    wire    [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]        fr_afi_cs_n                 ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_ras_n                ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_cas_n                ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_we_n                 ;
+    wire    [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]    fr_afi_ba                   ;
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0]  fr_afi_addr                 ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_rst_n                ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_rmw_correct          ;
+    wire    [(CFG_FR_DWIDTH_RATIO/2) - 1:0]                            fr_afi_rmw_partial          ;
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]      lpddr2_cke;
+    wire    [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]           lpddr2_cs_n;
+    wire    [(CFG_DWIDTH_RATIO/2) - 1:0]                               lpddr2_ras_n;
+    wire    [(CFG_DWIDTH_RATIO/2) - 1:0]                               lpddr2_cas_n;
+    wire    [(CFG_DWIDTH_RATIO/2) - 1:0]                               lpddr2_we_n;
+    wire    [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]       lpddr2_ba;
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]     lpddr2_addr;
+    wire    [(CFG_DWIDTH_RATIO/2) - 1:0]                               lpddr2_rst_n;
+    
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_write                                          ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_read                                           ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_burst_chop                                     ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_burst_terminate                                ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_auto_precharge                                 ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_rmw_correct                                    ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_rmw_partial                                    ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_activate                                       ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_precharge                                      ;
+    
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_rmw_correct_r                                  ;
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_rmw_partial_r                                  ;
+    
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_precharge_all     [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_refresh           [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_self_refresh      [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_power_down        [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_deep_pdown        [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_CHIP                   - 1 : 0]                int_bg_do_zq_cal            [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                int_bg_do_lmr                                           ;
+    
+    reg     [CFG_MEM_IF_CHIP       -1:0]                               int_bg_to_chip              [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_BA_WIDTH   -1:0]                               int_bg_to_bank              [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_ROW_WIDTH  -1:0]                               int_bg_to_row               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg     [CFG_MEM_IF_COL_WIDTH  -1:0]                               int_bg_to_col               [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    reg     [CFG_LOCAL_ID_WIDTH                - 1 : 0]                int_bg_localid;
+    reg     [CFG_DATA_ID_WIDTH                 - 1 : 0]                int_bg_dataid;
+    reg     [CFG_INT_SIZE_WIDTH                - 1 : 0]                int_bg_size;
+    
+    reg                                                                int_bg_do_lmr_read;
+    reg                                                                int_bg_do_refresh_1bank;
+    
+    wire    [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0]      afi_odt_h_l                 [CFG_AFI_INTF_PHASE_NUM-1:0];
+    wire    [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0]      mux_afi_odt_h_l             [CFG_AFI_INTF_PHASE_NUM-1:0];
+    
+    reg     [CFG_AFI_INTF_PHASE_NUM            - 1 : 0]                cfg_enable_chipsel_for_sideband;
+    
+    reg     [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0]  bg_do_self_refresh_r;
+    reg     [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0]  bg_do_deep_pdown_r;
+    
+    wire    one  = 1'b1;
+    wire    zero = 1'b0;
+    
+    // -----------------------------
+    // module definition
+    // -----------------------------
+    
+    genvar afi_j, afi_n;
+    generate
+        // map int_afi_* multi-dimensional array signals to afi_* output port signals
+        for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
+        begin : gen_afi_signals
+            always @ (*) 
+            begin
+                if (cfg_output_regd_for_afi_output == 2)
+                begin
+                    afi_cke         [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)]  = int_afi_cke_r           [afi_n] ;
+                    afi_cs_n        [((afi_n+1) * CFG_MEM_IF_CHIP)      -1 : (afi_n * CFG_MEM_IF_CHIP)]       = int_afi_cs_n_r          [afi_n] ;
+                    afi_ras_n       [afi_n]                                                                   = int_afi_ras_n_r         [afi_n] ;
+                    afi_cas_n       [afi_n]                                                                   = int_afi_cas_n_r         [afi_n] ;
+                    afi_we_n        [afi_n]                                                                   = int_afi_we_n_r          [afi_n] ;
+                    afi_ba          [((afi_n+1) * CFG_MEM_IF_BA_WIDTH)  -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)]   = int_afi_ba_r            [afi_n] ;
+                    afi_addr        [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr_r          [afi_n] ;
+                    afi_rst_n       [afi_n]                                                                   = int_afi_rst_n_r         [afi_n] ;
+                    afi_rmw_correct [afi_n]                                                                   = int_afi_rmw_correct_r   [afi_n] ;
+                    afi_rmw_partial [afi_n]                                                                   = int_afi_rmw_partial_r   [afi_n] ;
+                end
+                else
+                begin
+                    afi_cke         [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)]  = int_afi_cke           [afi_n] ;
+                    afi_cs_n        [((afi_n+1) * CFG_MEM_IF_CHIP)      -1 : (afi_n * CFG_MEM_IF_CHIP)]       = int_afi_cs_n          [afi_n] ;
+                    afi_ras_n       [afi_n]                                                                   = int_afi_ras_n         [afi_n] ;
+                    afi_cas_n       [afi_n]                                                                   = int_afi_cas_n         [afi_n] ;
+                    afi_we_n        [afi_n]                                                                   = int_afi_we_n          [afi_n] ;
+                    afi_ba          [((afi_n+1) * CFG_MEM_IF_BA_WIDTH)  -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)]   = int_afi_ba            [afi_n] ;
+                    afi_addr        [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr          [afi_n] ;
+                    afi_rst_n       [afi_n]                                                                   = int_afi_rst_n         [afi_n] ;
+                    afi_rmw_correct [afi_n]                                                                   = int_afi_rmw_correct   [afi_n] ;
+                    afi_rmw_partial [afi_n]                                                                   = int_afi_rmw_partial   [afi_n] ;
+                end
+            end
+        end
+        
+        // generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
+        
+        if (CFG_DWIDTH_RATIO == 2)
+        begin
+            // full rate, with any phase
+            assign int_afi_cke         [0] = fr_afi_cke         ;
+            assign int_afi_cs_n        [0] = fr_afi_cs_n        ;
+            assign int_afi_ras_n       [0] = fr_afi_ras_n       ;
+            assign int_afi_cas_n       [0] = fr_afi_cas_n       ;
+            assign int_afi_we_n        [0] = fr_afi_we_n        ;
+            assign int_afi_ba          [0] = fr_afi_ba          ;
+            assign int_afi_addr        [0] = fr_afi_addr        ;
+            assign int_afi_rst_n       [0] = fr_afi_rst_n       ;
+            assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
+            assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
+        end
+        else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
+        begin
+            // map phase_afi_* signals to int_afi_* signals
+            // half rate   , with phase=2
+            // quarter rate, with phase=4
+            for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
+            begin : gen_afi_signals_0
+                assign int_afi_cke         [afi_j] = phase_afi_cke         [afi_j] ;
+                assign int_afi_cs_n        [afi_j] = phase_afi_cs_n        [afi_j] ;
+                assign int_afi_ras_n       [afi_j] = phase_afi_ras_n       [afi_j] ;
+                assign int_afi_cas_n       [afi_j] = phase_afi_cas_n       [afi_j] ;
+                assign int_afi_we_n        [afi_j] = phase_afi_we_n        [afi_j] ;
+                assign int_afi_ba          [afi_j] = phase_afi_ba          [afi_j] ;
+                assign int_afi_addr        [afi_j] = phase_afi_addr        [afi_j] ;
+                assign int_afi_rst_n       [afi_j] = phase_afi_rst_n       [afi_j] ;
+                assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
+                assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
+            end
+        end
+        else    // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
+        begin
+            // map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
+            
+            // for cs_n signals:
+            // half rate    , with phase=1, drives int_afi_* 1 only
+            // quarter rate , with phase=2, drives int_afi_* 1 & 3
+            
+            // for other signals:
+            // half rate    , with phase=1, drives int_afi_* 0 & 1 with the same value
+            // quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
+            // Why? to improve timing margin on PHY side
+            
+            for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1) 
+            begin : gen_afi_signals_1
+                // Assign even phase with '1' because we only issue on odd phase (2T timing)
+                assign int_afi_cs_n        [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
+                
+                // Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
+                assign int_afi_cke         [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1))   ? phase_afi_cke  [1]                              : phase_afi_cke  [0];
+                
+                assign int_afi_ras_n       [afi_j] = phase_afi_ras_n       [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_cas_n       [afi_j] = phase_afi_cas_n       [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_we_n        [afi_j] = phase_afi_we_n        [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_ba          [afi_j] = phase_afi_ba          [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_addr        [afi_j] = phase_afi_addr        [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_rst_n       [afi_j] = phase_afi_rst_n       [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
+                assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
+            end
+        end
+        
+        for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1) 
+        begin : gen_afi_signals_r
+            // Registered output
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_afi_cke_r         [afi_j] <= 0;
+                    int_afi_cs_n_r        [afi_j] <= 0;
+                    int_afi_ras_n_r       [afi_j] <= 0;
+                    int_afi_cas_n_r       [afi_j] <= 0;
+                    int_afi_we_n_r        [afi_j] <= 0;
+                    int_afi_ba_r          [afi_j] <= 0;
+                    int_afi_addr_r        [afi_j] <= 0;
+                    int_afi_rst_n_r       [afi_j] <= 0;
+                    int_afi_rmw_correct_r [afi_j] <= 0;
+                    int_afi_rmw_partial_r [afi_j] <= 0;
+                end
+                else
+                begin
+                    int_afi_cke_r         [afi_j] <= int_afi_cke         [afi_j];
+                    int_afi_cs_n_r        [afi_j] <= int_afi_cs_n        [afi_j];
+                    int_afi_ras_n_r       [afi_j] <= int_afi_ras_n       [afi_j];
+                    int_afi_cas_n_r       [afi_j] <= int_afi_cas_n       [afi_j];
+                    int_afi_we_n_r        [afi_j] <= int_afi_we_n        [afi_j];
+                    int_afi_ba_r          [afi_j] <= int_afi_ba          [afi_j];
+                    int_afi_addr_r        [afi_j] <= int_afi_addr        [afi_j];
+                    int_afi_rst_n_r       [afi_j] <= int_afi_rst_n       [afi_j];
+                    int_afi_rmw_correct_r [afi_j] <= int_afi_rmw_correct [afi_j];
+                    int_afi_rmw_partial_r [afi_j] <= int_afi_rmw_partial [afi_j];
+                end
+            end
+        end
+    endgenerate
+    
+    // phase_afi_* signal generation
+    // instantiates an alt_mem_ddrx_addr_cmd for every phase
+    // maps bg_* signals to the correct instantiation
+    genvar afi_k;
+    generate
+        for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1) 
+        begin : gen_bg_afi_signal_decode
+
+            always @ (*)
+            begin
+                int_bg_do_write             [afi_k] = bg_do_write           [afi_k];
+                int_bg_do_read              [afi_k] = bg_do_read            [afi_k];
+                int_bg_do_burst_chop        [afi_k] = bg_do_burst_chop      [afi_k];
+                int_bg_do_burst_terminate   [afi_k] = bg_do_burst_terminate [afi_k];
+                int_bg_do_auto_precharge    [afi_k] = bg_do_auto_precharge  [afi_k];
+                int_bg_do_rmw_correct       [afi_k] = bg_do_rmw_correct     [afi_k];
+                int_bg_do_rmw_partial       [afi_k] = bg_do_rmw_partial     [afi_k];
+                int_bg_do_activate          [afi_k] = bg_do_activate        [afi_k];
+                int_bg_do_precharge         [afi_k] = bg_do_precharge       [afi_k];
+                                                                                   
+                int_bg_to_chip              [afi_k] = bg_to_chip            [(((afi_k+1)*CFG_MEM_IF_CHIP     )-1):(afi_k*CFG_MEM_IF_CHIP     )];
+                int_bg_to_bank              [afi_k] = bg_to_bank            [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
+                int_bg_to_row               [afi_k] = bg_to_row             [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
+                int_bg_to_col               [afi_k] = bg_to_col             [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
+            end
+            
+            if (CFG_DWIDTH_RATIO == 2) // full rate
+            begin
+                always @ (*)
+                begin
+                    int_bg_do_precharge_all     [afi_k] = bg_do_precharge_all   [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_refresh           [afi_k] = bg_do_refresh         [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_self_refresh      [afi_k] = bg_do_self_refresh    [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_power_down        [afi_k] = bg_do_power_down      [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_deep_pdown        [afi_k] = bg_do_deep_pdown      [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_zq_cal            [afi_k] = bg_do_zq_cal          [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )];
+                    int_bg_do_lmr               [afi_k] = bg_do_lmr             [afi_k];
+                end
+                
+                always @ (*)
+                begin
+                    cfg_enable_chipsel_for_sideband [afi_k] = one;
+                end
+            end
+            else // half and quarter rate
+            begin
+                always @ (*)
+                begin
+                    int_bg_do_precharge_all     [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all   [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )] : {CFG_MEM_IF_CHIP{1'b0}};
+                    int_bg_do_refresh           [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh         [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )] : {CFG_MEM_IF_CHIP{1'b0}};
+                    int_bg_do_zq_cal            [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal          [(((afi_k+1)*CFG_MEM_IF_CHIP    )-1):(afi_k*CFG_MEM_IF_CHIP      )] : {CFG_MEM_IF_CHIP{1'b0}};
+                    int_bg_do_lmr               [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr             [afi_k                                                            ] : 1'b0;
+                    
+                    // We need to assign these command to all phase
+                    // because these command might take one or more controller clock cycles
+                    // and we want to prevent CKE from toggling due to prolong commands
+                    int_bg_do_power_down        [afi_k] = bg_do_power_down   [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
+                    
+                    int_bg_do_self_refresh      [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
+                                                                                                    bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
+                    int_bg_do_deep_pdown        [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown   [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
+                                                                                                    bg_do_deep_pdown   [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r   [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
+                end
+                
+                always @ (*)
+                begin
+                    // We need to disable one phase of chipsel logic for sideband in half/quarter rate
+                    // in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
+                    cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
+                end
+            end
+            
+            // addresss command block instantiated based on number of phases
+            alt_mem_ddrx_addr_cmd  # (
+                .CFG_PORT_WIDTH_TYPE                ( CFG_PORT_WIDTH_TYPE                     ),
+                .CFG_PORT_WIDTH_OUTPUT_REGD         ( CFG_PORT_WIDTH_OUTPUT_REGD              ),
+                .CFG_MEM_IF_CHIP                    ( CFG_MEM_IF_CHIP                         ),
+                .CFG_MEM_IF_CKE_WIDTH               ( CFG_MEM_IF_CKE_WIDTH                    ),
+                .CFG_MEM_IF_ADDR_WIDTH              ( CFG_MEM_IF_ADDR_WIDTH                   ),
+                .CFG_MEM_IF_ROW_WIDTH               ( CFG_MEM_IF_ROW_WIDTH                    ),
+                .CFG_MEM_IF_COL_WIDTH               ( CFG_MEM_IF_COL_WIDTH                    ),
+                .CFG_MEM_IF_BA_WIDTH                ( CFG_MEM_IF_BA_WIDTH                     ),
+                .CFG_DWIDTH_RATIO                   ( CFG_FR_DWIDTH_RATIO                     )
+            ) alt_mem_ddrx_addr_cmd_inst (
+                .ctl_clk                            ( ctl_clk                                 ),
+                .ctl_reset_n                        ( ctl_reset_n                             ),
+                .ctl_cal_success                    ( ctl_cal_success                         ),
+                .cfg_type                           ( cfg_type                                ),
+                .cfg_output_regd                    ( cfg_output_regd_for_afi_output          ),
+                .cfg_enable_chipsel_for_sideband    ( cfg_enable_chipsel_for_sideband [afi_k] ),
+                .bg_do_write                        ( int_bg_do_write                 [afi_k] ),
+                .bg_do_read                         ( int_bg_do_read                  [afi_k] ),
+                .bg_do_auto_precharge               ( int_bg_do_auto_precharge        [afi_k] ),
+                .bg_do_burst_chop                   ( int_bg_do_burst_chop            [afi_k] ),
+                .bg_do_activate                     ( int_bg_do_activate              [afi_k] ),
+                .bg_do_precharge                    ( int_bg_do_precharge             [afi_k] ),
+                .bg_do_refresh                      ( int_bg_do_refresh               [afi_k] ),
+                .bg_do_power_down                   ( int_bg_do_power_down            [afi_k] ),
+                .bg_do_self_refresh                 ( int_bg_do_self_refresh          [afi_k] ),
+                .bg_do_lmr                          ( int_bg_do_lmr                   [afi_k] ),
+                .bg_do_precharge_all                ( int_bg_do_precharge_all         [afi_k] ),
+                .bg_do_zq_cal                       ( int_bg_do_zq_cal                [afi_k] ),
+                .bg_do_deep_pdown                   ( int_bg_do_deep_pdown            [afi_k] ),
+                .bg_do_burst_terminate              ( int_bg_do_burst_terminate       [afi_k] ),
+                .bg_to_chip                         ( int_bg_to_chip                  [afi_k] ),
+                .bg_to_bank                         ( int_bg_to_bank                  [afi_k] ),
+                .bg_to_row                          ( int_bg_to_row                   [afi_k] ),
+                .bg_to_col                          ( int_bg_to_col                   [afi_k] ),
+                .bg_to_lmr                          ( bg_to_lmr                               ),
+                .lmr_opcode                         ( lmr_opcode                              ),
+                .afi_cke                            ( int_ddrx_afi_cke                [afi_k] ),
+                .afi_cs_n                           ( int_ddrx_afi_cs_n               [afi_k] ),
+                .afi_ras_n                          ( int_ddrx_afi_ras_n              [afi_k] ),
+                .afi_cas_n                          ( int_ddrx_afi_cas_n              [afi_k] ),
+                .afi_we_n                           ( int_ddrx_afi_we_n               [afi_k] ),
+                .afi_ba                             ( int_ddrx_afi_ba                 [afi_k] ),
+                .afi_addr                           ( int_ddrx_afi_addr               [afi_k] ),
+                .afi_rst_n                          ( int_ddrx_afi_rst_n              [afi_k] )
+            );
+
+            if (CFG_LPDDR2_ENABLED)
+            begin
+                alt_mem_ddrx_lpddr2_addr_cmd  # (
+                    .CFG_PORT_WIDTH_OUTPUT_REGD         (CFG_PORT_WIDTH_OUTPUT_REGD             ),
+                    .CFG_MEM_IF_CHIP                    (CFG_MEM_IF_CHIP                        ),
+                    .CFG_MEM_IF_CKE_WIDTH               (CFG_MEM_IF_CKE_WIDTH                   ),
+                    .CFG_MEM_IF_ADDR_WIDTH              (CFG_MEM_IF_ADDR_WIDTH                  ),
+                    .CFG_MEM_IF_ROW_WIDTH               (CFG_MEM_IF_ROW_WIDTH                   ),
+                    .CFG_MEM_IF_COL_WIDTH               (CFG_MEM_IF_COL_WIDTH                   ),
+                    .CFG_MEM_IF_BA_WIDTH                (CFG_MEM_IF_BA_WIDTH                    ),
+                    .CFG_DWIDTH_RATIO                   (CFG_FR_DWIDTH_RATIO                    )
+                ) alt_mem_ddrx_lpddr2_addr_cmd_inst (
+                    .ctl_clk                            (ctl_clk                                ),
+                    .ctl_reset_n                        (ctl_reset_n                            ),
+                    .ctl_cal_success                    (ctl_cal_success                        ),
+                    .cfg_output_regd                    (cfg_output_regd_for_afi_output         ),
+                    .cfg_enable_chipsel_for_sideband    (cfg_enable_chipsel_for_sideband [afi_k]),
+                    .do_write                           (int_bg_do_write                 [afi_k]),
+                    .do_read                            (int_bg_do_read                  [afi_k]),
+                    .do_auto_precharge                  (int_bg_do_auto_precharge        [afi_k]),
+                    .do_activate                        (int_bg_do_activate              [afi_k]),
+                    .do_precharge                       (int_bg_do_precharge             [afi_k]),
+                    .do_refresh                         (int_bg_do_refresh               [afi_k]),
+                    .do_power_down                      (int_bg_do_power_down            [afi_k]),
+                    .do_self_refresh                    (int_bg_do_self_refresh          [afi_k]),
+                    .do_lmr                             (int_bg_do_lmr                   [afi_k]),
+                    .do_precharge_all                   (int_bg_do_precharge_all         [afi_k]),
+                    .do_deep_pwrdwn                     (int_bg_do_deep_pdown            [afi_k]),
+                    .do_burst_terminate                 (int_bg_do_burst_terminate       [afi_k]),
+                    .do_lmr_read                        (int_bg_do_lmr_read                     ),
+                    .do_refresh_1bank                   (int_bg_do_refresh_1bank                ),
+                    .to_chip                            (int_bg_to_chip                  [afi_k]),
+                    .to_bank                            (int_bg_to_bank                  [afi_k]),
+                    .to_row                             (int_bg_to_row                   [afi_k]),
+                    .to_col                             (int_bg_to_col                   [afi_k]),
+                    .to_lmr                             (bg_to_lmr                              ),
+                    .lmr_opcode                         (lmr_opcode[7:0]                        ),
+                    .afi_cke                            (int_lpddr2_afi_cke              [afi_k]),
+                    .afi_cs_n                           (int_lpddr2_afi_cs_n             [afi_k]),
+                    .afi_addr                           (int_lpddr2_afi_addr             [afi_k]),
+                    .afi_rst_n                          (int_lpddr2_afi_rst_n            [afi_k])
+                );
+            end
+            else
+            begin
+                assign int_lpddr2_afi_cke   [afi_k] = {(CFG_MEM_IF_CKE_WIDTH    * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}}; 
+                assign int_lpddr2_afi_cs_n  [afi_k] = {(CFG_MEM_IF_CHIP         * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
+                assign int_lpddr2_afi_addr  [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH   * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
+                assign int_lpddr2_afi_rst_n [afi_k] = {                           (CFG_FR_DWIDTH_RATIO/2)  {1'b0}};
+            end
+            
+            always @ (*)
+            begin
+                // Mux to select ddrx or lpddr2 addrcmd decoder blocks
+                if (cfg_type == `MMR_TYPE_LPDDR2)
+                begin
+                    phase_afi_cke   [afi_k] = int_lpddr2_afi_cke  [afi_k] ;
+                    phase_afi_cs_n  [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
+                    phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
+                    phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
+                    phase_afi_we_n  [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
+                    phase_afi_ba    [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
+                    phase_afi_addr  [afi_k] = int_lpddr2_afi_addr [afi_k] ;
+                    phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
+                end
+                else
+                begin
+                    phase_afi_cke   [afi_k] = int_ddrx_afi_cke   [afi_k] ;
+                    phase_afi_cs_n  [afi_k] = int_ddrx_afi_cs_n  [afi_k] ;
+                    phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
+                    phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
+                    phase_afi_we_n  [afi_k] = int_ddrx_afi_we_n  [afi_k] ;
+                    phase_afi_ba    [afi_k] = int_ddrx_afi_ba    [afi_k] ;
+                    phase_afi_addr  [afi_k] = int_ddrx_afi_addr  [afi_k] ;
+                    phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n) 
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
+                    int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
+                end
+                else
+                begin
+                    int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct    [afi_k];
+                    int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial    [afi_k];
+                end
+            end
+            
+            always @ (*) 
+            begin
+                if (cfg_output_regd_for_afi_output)
+                begin
+                    phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
+                    phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
+                end
+                else
+                begin
+                    phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct    [afi_k];
+                    phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial    [afi_k];
+                end
+            end
+            
+            alt_mem_ddrx_odt_gen #
+            (
+                .CFG_DWIDTH_RATIO               (CFG_DWIDTH_RATIO               ),
+                .CFG_ODT_ENABLED                (CFG_ODT_ENABLED                ),
+                .CFG_MEM_IF_CHIP                (CFG_MEM_IF_CHIP                ),
+                .CFG_MEM_IF_ODT_WIDTH           (CFG_MEM_IF_ODT_WIDTH           ),
+                .CFG_PORT_WIDTH_CAS_WR_LAT      (CFG_PORT_WIDTH_CAS_WR_LAT      ),
+                .CFG_PORT_WIDTH_TCL             (CFG_PORT_WIDTH_TCL             ),
+                .CFG_PORT_WIDTH_ADD_LAT         (CFG_PORT_WIDTH_ADD_LAT         ),
+                .CFG_PORT_WIDTH_TYPE            (CFG_PORT_WIDTH_TYPE            ),
+                .CFG_PORT_WIDTH_WRITE_ODT_CHIP  (CFG_PORT_WIDTH_WRITE_ODT_CHIP  ),
+                .CFG_PORT_WIDTH_READ_ODT_CHIP   (CFG_PORT_WIDTH_READ_ODT_CHIP   ),
+                .CFG_PORT_WIDTH_OUTPUT_REGD     (CFG_PORT_WIDTH_OUTPUT_REGD     )
+            )
+            odt_gen_inst
+            (
+                .ctl_clk                        (ctl_clk                        ),
+                .ctl_reset_n                    (ctl_reset_n                    ),
+                .cfg_type                       (cfg_type                       ),
+                .cfg_tcl                        (cfg_tcl                        ),
+                .cfg_cas_wr_lat                 (cfg_cas_wr_lat                 ),
+                .cfg_add_lat                    (cfg_add_lat                    ),
+                .cfg_write_odt_chip             (cfg_write_odt_chip             ),
+                .cfg_read_odt_chip              (cfg_read_odt_chip              ),
+                .cfg_burst_length               (cfg_burst_length               ),
+                .cfg_output_regd                (cfg_output_regd_for_afi_output ),
+                .bg_do_read                     (int_bg_do_read          [afi_k]),
+                .bg_do_write                    (int_bg_do_write         [afi_k]),
+                .bg_do_burst_chop               (int_bg_do_burst_chop    [afi_k]),
+                .bg_to_chip                     (int_bg_to_chip          [afi_k]),
+                .afi_odt                        (afi_odt_h_l             [afi_k])
+            );
+        end
+        
+        always @ (*)
+        begin
+            int_bg_dataid           = bg_dataid;
+            int_bg_localid          = bg_localid;
+            int_bg_size             = bg_size;
+            int_bg_do_lmr_read      = bg_do_lmr_read;
+            int_bg_do_refresh_1bank = bg_do_refresh_1bank;
+        end
+    endgenerate
+    
+    // ODT output generation
+    always @ (*)
+    begin
+        afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
+    end
+    
+    // generate ODT output signal from odt_gen
+    assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
+    
+    genvar afi_m;
+    generate
+        for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
+        begin : mux_for_odt
+            assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
+        end
+    endgenerate
+    
+    // generate fr_* signals from phase_* signals
+    assign mux_afi_cke               [0]  =     phase_afi_cke               [0];
+    assign mux_afi_cs_n              [0]  =     phase_afi_cs_n              [0];
+    assign mux_afi_ras_n             [0]  =     phase_afi_ras_n             [0];
+    assign mux_afi_cas_n             [0]  =     phase_afi_cas_n             [0];
+    assign mux_afi_we_n              [0]  =     phase_afi_we_n              [0];
+    assign mux_afi_ba                [0]  =     phase_afi_ba                [0];
+    assign mux_afi_addr              [0]  =     phase_afi_addr              [0];
+    assign mux_afi_rst_n             [0]  =     phase_afi_rst_n             [0];
+    assign mux_afi_rmw_correct       [0]  =     phase_afi_rmw_correct       [0];
+    assign mux_afi_rmw_partial       [0]  =     phase_afi_rmw_partial       [0];
+    
+    genvar afi_l;
+    generate
+        for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
+        begin : gen_resolve_phase_for_fullrate
+            assign mux_afi_cke               [afi_l]  =  mux_afi_cke         [(afi_l-1)] & phase_afi_cke         [afi_l];
+            assign mux_afi_cs_n              [afi_l]  =  mux_afi_cs_n        [(afi_l-1)] & phase_afi_cs_n        [afi_l];
+            assign mux_afi_ras_n             [afi_l]  =  mux_afi_ras_n       [(afi_l-1)] & phase_afi_ras_n       [afi_l];
+            assign mux_afi_cas_n             [afi_l]  =  mux_afi_cas_n       [(afi_l-1)] & phase_afi_cas_n       [afi_l];
+            assign mux_afi_we_n              [afi_l]  =  mux_afi_we_n        [(afi_l-1)] & phase_afi_we_n        [afi_l];
+            assign mux_afi_ba                [afi_l]  =  mux_afi_ba          [(afi_l-1)] | phase_afi_ba          [afi_l];
+            assign mux_afi_addr              [afi_l]  =  mux_afi_addr        [(afi_l-1)] | phase_afi_addr        [afi_l];
+            assign mux_afi_rst_n             [afi_l]  =  mux_afi_rst_n       [(afi_l-1)] | phase_afi_rst_n       [afi_l];
+            assign mux_afi_rmw_correct       [afi_l]  =  mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
+            assign mux_afi_rmw_partial       [afi_l]  =  mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
+        end
+    endgenerate
+    
+    assign fr_afi_cke         = mux_afi_cke         [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_cs_n        = mux_afi_cs_n        [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_ras_n       = mux_afi_ras_n       [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_cas_n       = mux_afi_cas_n       [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_we_n        = mux_afi_we_n        [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_ba          = mux_afi_ba          [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_addr        = mux_afi_addr        [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_rst_n       = mux_afi_rst_n       [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
+    assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
+    
+    // Registered version of self refresh and power down
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            bg_do_self_refresh_r <= 0;
+            bg_do_deep_pdown_r   <= 0;
+        end
+        else
+        begin
+            bg_do_self_refresh_r <= bg_do_self_refresh;
+            bg_do_deep_pdown_r   <= bg_do_deep_pdown;
+        end
+    end
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
new file mode 100644
index 0000000..4e955f2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
@@ -0,0 +1,1242 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_arbiter #
+    ( parameter
+        CFG_DWIDTH_RATIO            =   4,
+        CFG_CTL_TBP_NUM             =   4,
+        CFG_CTL_ARBITER_TYPE        =   "ROWCOL",
+        CFG_REG_GRANT               =   0,
+        CFG_REG_REQ                 =   0,
+        CFG_MEM_IF_CHIP             =   1,
+        CFG_MEM_IF_CS_WIDTH         =   1,
+        CFG_MEM_IF_BA_WIDTH         =   3,
+        CFG_MEM_IF_ROW_WIDTH        =   13,
+        CFG_MEM_IF_COL_WIDTH        =   10,
+        CFG_LOCAL_ID_WIDTH          =   10,
+        CFG_DATA_ID_WIDTH           =   10,
+        CFG_INT_SIZE_WIDTH          =   4,
+        CFG_AFI_INTF_PHASE_NUM      =   2,
+        CFG_DISABLE_PRIORITY        =   1
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // Common
+        stall_row_arbiter,
+        stall_col_arbiter,
+        
+        // Sideband Interface
+        sb_do_precharge_all,
+        sb_do_refresh,
+        sb_do_self_refresh,
+        sb_do_power_down,
+        sb_do_deep_pdown,
+        sb_do_zq_cal,
+        
+        // TBP Interface
+        row_req,
+        col_req,
+        act_req,
+        pch_req,
+        rd_req,
+        wr_req,
+        row_grant,
+        col_grant,
+        act_grant,
+        pch_grant,
+        rd_grant,
+        wr_grant,
+        log2_row_grant,
+        log2_col_grant,
+        log2_act_grant,
+        log2_pch_grant,
+        log2_rd_grant,
+        log2_wr_grant,
+        or_row_grant,
+        or_col_grant,
+        tbp_activate,
+        tbp_precharge,
+        tbp_read,
+        tbp_write,
+        tbp_chipsel,
+        tbp_bank,
+        tbp_row,
+        tbp_col,
+        tbp_size,
+        tbp_localid,
+        tbp_dataid,
+        tbp_ap,
+        tbp_burst_chop,
+        tbp_rmw_correct,
+        tbp_rmw_partial,
+        tbp_age,
+        tbp_priority,
+        
+        // Rank Timer Interface
+        can_activate,
+        can_precharge,
+        can_write,
+        can_read,
+        
+        // Arbiter Output Interface
+        arb_do_write,
+        arb_do_read,
+        arb_do_burst_chop,
+        arb_do_burst_terminate,
+        arb_do_auto_precharge,
+        arb_do_rmw_correct,
+        arb_do_rmw_partial,
+        arb_do_activate,
+        arb_do_precharge,
+        arb_do_precharge_all,
+        arb_do_refresh,
+        arb_do_self_refresh,
+        arb_do_power_down,
+        arb_do_deep_pdown,
+        arb_do_zq_cal,
+        arb_do_lmr,
+        arb_to_chipsel,
+        arb_to_chip,
+        arb_to_bank,
+        arb_to_row,
+        arb_to_col,
+        arb_localid,
+        arb_dataid,
+        arb_size
+    );
+
+localparam AFI_INTF_LOW_PHASE  = 0;
+localparam AFI_INTF_HIGH_PHASE = 1;
+
+input  ctl_clk;
+input  ctl_reset_n;
+
+// Common
+input  stall_row_arbiter;
+input  stall_col_arbiter;
+
+// Sideband Interface
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_precharge_all;
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_refresh;
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_self_refresh;
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_power_down;
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_deep_pdown;
+input  [CFG_MEM_IF_CHIP                                 - 1 : 0] sb_do_zq_cal;
+
+// TBP Interface
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] row_req;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] col_req;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] act_req;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] pch_req;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] rd_req;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] wr_req;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] row_grant;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] col_grant;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] act_grant;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] pch_grant;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] rd_grant;
+output [CFG_CTL_TBP_NUM                                 - 1 : 0] wr_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_row_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_col_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_act_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_pch_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_rd_grant;
+output [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_wr_grant;
+output                                                           or_row_grant;
+output                                                           or_col_grant;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_activate;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_precharge;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_read;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_write;
+input  [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH)         - 1 : 0] tbp_chipsel;
+input  [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH)         - 1 : 0] tbp_bank;
+input  [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH)        - 1 : 0] tbp_row;
+input  [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH)        - 1 : 0] tbp_col;
+input  [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH)          - 1 : 0] tbp_size;
+input  [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH)          - 1 : 0] tbp_localid;
+input  [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH)           - 1 : 0] tbp_dataid;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_ap;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_burst_chop;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_rmw_correct;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_rmw_partial;
+input  [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM)             - 1 : 0] tbp_age;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_priority;
+
+// Rank Timer Interface
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] can_activate;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] can_precharge;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] can_write;
+input  [CFG_CTL_TBP_NUM                                 - 1 : 0] can_read;
+
+// Arbiter Output Interface
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_write;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_read;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_chop;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_terminate;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_auto_precharge;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_correct;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_partial;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_activate;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_precharge;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_precharge_all;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_refresh;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_self_refresh;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_power_down;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_deep_pdown;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_zq_cal;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_lmr;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] arb_to_chipsel;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_to_chip;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] arb_to_bank;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
+output [CFG_LOCAL_ID_WIDTH                              - 1 : 0] arb_localid;
+output [CFG_DATA_ID_WIDTH                               - 1 : 0] arb_dataid;
+output [CFG_INT_SIZE_WIDTH                              - 1 : 0] arb_size;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Registers & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // General
+    wire one  = 1'b1;
+    wire zero = 1'b0;
+    
+    // TBP Interface
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] row_grant;
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] col_grant;
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] act_grant;
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] pch_grant;
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] rd_grant;
+    reg  [CFG_CTL_TBP_NUM       - 1 : 0] wr_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
+    reg                                  or_row_grant;
+    reg                                  or_col_grant;
+    reg                                  or_act_grant;
+    reg                                  or_pch_grant;
+    reg                                  or_rd_grant;
+    reg                                  or_wr_grant;
+    
+    // Arbiter Output Interface
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_write;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_read;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_chop;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_terminate;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_auto_precharge;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_partial;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_activate;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_precharge;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_precharge_all;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_refresh;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_self_refresh;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_power_down;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_deep_pdown;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_zq_cal;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_lmr;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] arb_to_chipsel;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_to_chip;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] arb_to_bank;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
+    reg  [CFG_LOCAL_ID_WIDTH                              - 1 : 0] arb_localid;
+    reg  [CFG_DATA_ID_WIDTH                               - 1 : 0] arb_dataid;
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] arb_size;
+    
+    // Common
+    reg                                 granted_read        [CFG_CTL_TBP_NUM - 1 : 0];
+    reg                                 granted_write       [CFG_CTL_TBP_NUM - 1 : 0];
+
+	// WSHUM: See Case:70614
+	// Flatten these into 1-D arrays to avoid using a 2-D array element as an index
+	// into another array, which causes data mismatches in Modelsim SE 10.1b
+	// granted_chipsel_r[tbp] becomes 
+	// granted_chipsel_r[CFG_MEM_IF_CS_WIDTH*(tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH * tbp]
+    //reg  [CFG_MEM_IF_CS_WIDTH  - 1 : 0] granted_chipsel_r   [CFG_CTL_TBP_NUM - 1 : 0];
+    //reg  [CFG_MEM_IF_CS_WIDTH  - 1 : 0] granted_chipsel_c   [CFG_CTL_TBP_NUM - 1 : 0];
+    reg [CFG_MEM_IF_CS_WIDTH*CFG_CTL_TBP_NUM  - 1 : 0] granted_chipsel_r;
+    reg [CFG_MEM_IF_CS_WIDTH*CFG_CTL_TBP_NUM  - 1 : 0] granted_chipsel_c;
+
+    reg  [CFG_MEM_IF_CHIP      - 1 : 0] granted_to_chip_r                            ;
+    reg  [CFG_MEM_IF_CHIP      - 1 : 0] granted_to_chip_c                            ;
+    reg  [CFG_MEM_IF_BA_WIDTH  - 1 : 0] granted_bank_r      [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_MEM_IF_BA_WIDTH  - 1 : 0] granted_bank_c      [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r       [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c       [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col         [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_INT_SIZE_WIDTH   - 1 : 0] granted_size        [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_DATA_ID_WIDTH    - 1 : 0] granted_dataid      [CFG_CTL_TBP_NUM - 1 : 0];
+    reg  [CFG_LOCAL_ID_WIDTH   - 1 : 0] granted_localid     [CFG_CTL_TBP_NUM - 1 : 0];
+    reg                                 granted_ap          [CFG_CTL_TBP_NUM - 1 : 0];
+    reg                                 granted_burst_chop  [CFG_CTL_TBP_NUM - 1 : 0];
+    reg                                 granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
+    reg                                 granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
+    
+    // Arbiter
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
+    
+    reg                            internal_or_row_grant;
+    reg                            internal_or_col_grant;
+    
+    reg                            int_or_row_grant;
+    reg                            int_or_col_grant;
+    reg                            int_or_act_grant;
+    reg                            int_or_pch_grant;
+    reg                            int_or_rd_grant;
+    reg                            int_or_wr_grant;
+    
+    reg                            granted_or_row_grant;
+    reg                            granted_or_col_grant;
+    reg                            granted_or_act_grant;
+    reg                            granted_or_pch_grant;
+    reg                            granted_or_rd_grant;
+    reg                            granted_or_wr_grant;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
+    
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
+    reg  [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
+    
+    wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Registers & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Outputs
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Granted logic specific grant signals
+    //----------------------------------------------------------------------------------------------------
+    always @ (*)
+    begin
+        granted_or_row_grant   = or_row_grant;
+        granted_or_col_grant   = or_col_grant;
+        granted_or_act_grant   = or_act_grant;
+        granted_or_pch_grant   = or_pch_grant;
+        granted_or_rd_grant    = or_rd_grant;
+        granted_or_wr_grant    = or_wr_grant;
+        
+        granted_row_grant      = row_grant;
+        granted_col_grant      = col_grant;
+        granted_act_grant      = act_grant;
+        granted_pch_grant      = pch_grant;
+        granted_rd_grant       = rd_grant;
+        granted_wr_grant       = wr_grant;
+        
+        log2_granted_row_grant = log2_row_grant;
+        log2_granted_col_grant = log2_col_grant;
+        
+        log2_granted_act_grant = log2_act_grant;
+        log2_granted_pch_grant = log2_pch_grant;
+        log2_granted_rd_grant  = log2_rd_grant;
+        log2_granted_wr_grant  = log2_wr_grant;
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Sideband outputs
+    //----------------------------------------------------------------------------------------------------
+    // Precharge all
+    always @ (*)
+    begin
+        arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
+    end
+    
+    // Refresh
+    always @ (*)
+    begin
+        arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
+    end
+    
+    // Self refresh
+    always @ (*)
+    begin
+        arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
+    end
+    
+    // Power down
+    always @ (*)
+    begin
+        arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
+    end
+    
+    // Power down
+    always @ (*)
+    begin
+        arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
+    end
+    
+    // ZQ calibration
+    always @ (*)
+    begin
+        arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
+    end
+    
+    // LMR
+    always @ (*)
+    begin
+        arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Non arbiter type aware outputs
+    //----------------------------------------------------------------------------------------------------
+    // Burst chop
+    always @ (*)
+    begin
+        arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
+    end
+    
+    // Burst terminate
+    always @ (*)
+    begin
+        arb_do_burst_terminate = 0;
+    end
+    
+    // RMW Correct
+    always @ (*)
+    begin
+        arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
+    end
+    
+    // RMW Partial
+    always @ (*)
+    begin
+        arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
+    end
+    
+    // LMR
+    // SPYGLASS FIX: altera_mem_if_ddr3_emif_test.altera_mem_if_ddr3_emif_inst.c0.ng0.alt_mem_ddrx_controller_top_inst.controller_inst.arb_do_lmr[1:0]' has multiple simultaneous drivers
+    // always @ (*)
+    // begin
+    //    arb_do_lmr = 0;
+    // end
+    
+    // Local ID
+    always @ (*)
+    begin
+        arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
+    end
+    
+    // Data ID
+    always @ (*)
+    begin
+        arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
+    end
+    
+    // Size
+    always @ (*)
+    begin
+        arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
+    end
+    
+    // Column address
+    // column command will only require column address, therefore there will be no conflcting column addresses
+    always @ (*)
+    begin
+        arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Arbiter type aware outputs
+    //----------------------------------------------------------------------------------------------------
+    generate
+    begin
+        if (CFG_CTL_ARBITER_TYPE == "COLROW")
+        begin
+            // Write
+            always @ (*)
+            begin
+                arb_do_write = 0;
+                
+                arb_do_write [AFI_INTF_LOW_PHASE] = granted_wr_grant;
+            end
+            
+            // Read
+            always @ (*)
+            begin
+                arb_do_read = 0;
+                
+                arb_do_read [AFI_INTF_LOW_PHASE] = granted_rd_grant;
+            end
+            
+            // Auto precharge
+            always @ (*)
+            begin
+                arb_do_auto_precharge = 0;
+                
+                arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
+            end
+            
+            // Activate
+            always @ (*)
+            begin
+                arb_do_activate = 0;
+                
+                arb_do_activate [AFI_INTF_HIGH_PHASE] = granted_act_grant;
+            end
+            
+            // Precharge
+            always @ (*)
+            begin
+                arb_do_precharge = 0;
+                
+                arb_do_precharge [AFI_INTF_HIGH_PHASE] = granted_pch_grant;
+            end
+            
+            // Chip address
+            // chipsel to to_chip address conversion
+            always @ (*)
+            begin
+                granted_to_chip_r = 0;
+                
+                if (|granted_row_grant)
+                    granted_to_chip_r [granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
+            end
+            
+            always @ (*)
+            begin
+                granted_to_chip_c = 0;
+                
+                if (|granted_col_grant)
+                    granted_to_chip_c [granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
+            end
+            
+            always @ (*)
+            begin
+                arb_to_chipsel = {granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)], granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]};
+            end
+            
+            always @ (*)
+            begin
+                arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
+            end
+            
+            // Bank address
+            always @ (*)
+            begin
+                arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
+            end
+            
+            // Row address
+            always @ (*)
+            begin
+                arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
+            end
+        end
+        else
+        begin
+            // Write
+            always @ (*)
+            begin
+                arb_do_write = 0;
+                
+                arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
+            end
+            
+            // Read
+            always @ (*)
+            begin
+                arb_do_read = 0;
+                
+                arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
+            end
+            
+            // Auto precharge
+            always @ (*)
+            begin
+                arb_do_auto_precharge = 0;
+                
+                arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
+            end
+            
+            // Activate
+            always @ (*)
+            begin
+                arb_do_activate = 0;
+                
+                arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
+            end
+            
+            // Precharge
+            always @ (*)
+            begin
+                arb_do_precharge = 0;
+                
+                arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
+            end
+            
+            // Chip address
+            // chipsel to to_chip address conversion
+            always @ (*)
+            begin
+                granted_to_chip_r = 0;
+                
+                if (|granted_row_grant)
+                    granted_to_chip_r [granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
+            end
+            
+            always @ (*)
+            begin
+                granted_to_chip_c = 0;
+                
+                if (|granted_col_grant)
+                    granted_to_chip_c [granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
+            end
+            
+            always @ (*)
+            begin
+                arb_to_chipsel = {granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)], granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]};
+            end
+            
+            always @ (*)
+            begin
+                arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
+            end
+            
+            // Bank address
+            always @ (*)
+            begin
+                arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
+            end
+            
+            // Row address
+            always @ (*)
+            begin
+                arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
+            end
+        end
+    end
+    endgenerate
+    
+    //----------------------------------------------------------------------------------------------------
+    // Granted outputs
+    //----------------------------------------------------------------------------------------------------
+    // Chip address
+    always @ (*)
+    begin
+        granted_chipsel_r   [CFG_MEM_IF_CS_WIDTH-1 : 0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel     [CFG_MEM_IF_CS_WIDTH  - 1 : 0];
+        granted_chipsel_c   [CFG_MEM_IF_CS_WIDTH-1 : 0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel     [CFG_MEM_IF_CS_WIDTH  - 1 : 0];
+    end
+    
+    // Bank address
+    always @ (*)
+    begin
+        granted_bank_r      [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank        [CFG_MEM_IF_BA_WIDTH  - 1 : 0];
+        granted_bank_c      [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank        [CFG_MEM_IF_BA_WIDTH  - 1 : 0];
+    end
+    
+    // Row address
+    always @ (*)
+    begin
+        granted_row_r       [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row         [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
+        granted_row_c       [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row         [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
+    end
+    
+    // Column address
+    always @ (*)
+    begin
+        granted_col         [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col         [CFG_MEM_IF_COL_WIDTH - 1 : 0];
+    end
+    
+    // Size
+    always @ (*)
+    begin
+        granted_size        [0] = {CFG_INT_SIZE_WIDTH  {granted_col_grant [0]}} & tbp_size        [CFG_INT_SIZE_WIDTH   - 1 : 0];
+    end
+    
+    // Local ID
+    always @ (*)
+    begin
+        granted_localid     [0] = {CFG_LOCAL_ID_WIDTH  {granted_col_grant [0]}} & tbp_localid     [CFG_LOCAL_ID_WIDTH   - 1 : 0];
+    end
+    
+    // Data ID
+    always @ (*)
+    begin
+        granted_dataid      [0] = {CFG_DATA_ID_WIDTH   {granted_col_grant [0]}} & tbp_dataid      [CFG_DATA_ID_WIDTH    - 1 : 0];
+    end
+    
+    // Auto precharge
+    always @ (*)
+    begin
+        granted_ap          [0] =                       granted_col_grant [0]   & tbp_ap          [                           0];
+    end
+    
+    // Burst Chop
+    always @ (*)
+    begin
+        granted_burst_chop  [0] =                       granted_col_grant [0]   & tbp_burst_chop  [                           0];
+    end
+    
+    // RMW Correct
+    always @ (*)
+    begin
+        granted_rmw_correct [0] =                       granted_col_grant [0]   & tbp_rmw_correct [                           0];
+    end
+    
+    // RMW Partial
+    always @ (*)
+    begin
+        granted_rmw_partial [0] =                       granted_col_grant [0]   & tbp_rmw_partial [                           0];
+    end
+    
+    generate
+    begin
+        genvar j_tbp;
+        for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
+        begin : granted_information_per_tbp
+            wire [CFG_MEM_IF_CS_WIDTH  - 1 : 0] chipsel_addr = tbp_chipsel     [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH  - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
+            wire [CFG_MEM_IF_BA_WIDTH  - 1 : 0] bank_addr    = tbp_bank        [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH  - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
+            wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr     = tbp_row         [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
+            wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr     = tbp_col         [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
+            wire [CFG_INT_SIZE_WIDTH   - 1 : 0] size         = tbp_size        [(j_tbp + 1) * CFG_INT_SIZE_WIDTH   - 1 : j_tbp * CFG_INT_SIZE_WIDTH  ];
+            wire [CFG_LOCAL_ID_WIDTH   - 1 : 0] localid      = tbp_localid     [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH   - 1 : j_tbp * CFG_LOCAL_ID_WIDTH  ];
+            wire [CFG_DATA_ID_WIDTH    - 1 : 0] dataid       = tbp_dataid      [(j_tbp + 1) * CFG_DATA_ID_WIDTH    - 1 : j_tbp * CFG_DATA_ID_WIDTH   ];
+            wire                                ap           = tbp_ap          [(j_tbp + 1)                        - 1 : j_tbp                       ];
+            wire                                burst_chop   = tbp_burst_chop  [(j_tbp + 1)                        - 1 : j_tbp                       ];
+            wire                                rmw_correct  = tbp_rmw_correct [(j_tbp + 1)                        - 1 : j_tbp                       ];
+            wire                                rmw_partial  = tbp_rmw_partial [(j_tbp + 1)                        - 1 : j_tbp                       ];
+            
+            // Chip address
+            always @ (*)
+            begin
+                granted_chipsel_r   [CFG_MEM_IF_CS_WIDTH*(j_tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH*j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r   [CFG_MEM_IF_CS_WIDTH*(j_tbp) - 1 : CFG_MEM_IF_CS_WIDTH*(j_tbp-1)];
+                granted_chipsel_c   [CFG_MEM_IF_CS_WIDTH*(j_tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH*j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c   [CFG_MEM_IF_CS_WIDTH*(j_tbp) - 1 : CFG_MEM_IF_CS_WIDTH*(j_tbp-1)];
+            end
+            
+            // Bank address
+            always @ (*)
+            begin
+                granted_bank_r      [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr   ) | granted_bank_r      [j_tbp - 1];
+                granted_bank_c      [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr   ) | granted_bank_c      [j_tbp - 1];
+            end
+            
+            // Row address
+            always @ (*)
+            begin
+                granted_row_r       [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr    ) | granted_row_r       [j_tbp - 1];
+                granted_row_c       [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr    ) | granted_row_c       [j_tbp - 1];
+            end
+            
+            // Column address
+            always @ (*)
+            begin
+                granted_col         [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr    ) | granted_col         [j_tbp - 1];
+            end
+            
+            // Size
+            always @ (*)
+            begin
+                granted_size        [j_tbp] = ({CFG_INT_SIZE_WIDTH  {granted_col_grant [j_tbp]}} & size        ) | granted_size        [j_tbp - 1];
+            end
+            
+            // Local ID
+            always @ (*)
+            begin
+                granted_localid     [j_tbp] = ({CFG_LOCAL_ID_WIDTH  {granted_col_grant [j_tbp]}} & localid     ) | granted_localid     [j_tbp - 1];
+            end
+            
+            // Data ID
+            always @ (*)
+            begin
+                granted_dataid      [j_tbp] = ({CFG_DATA_ID_WIDTH   {granted_col_grant [j_tbp]}} & dataid      ) | granted_dataid      [j_tbp - 1];
+            end
+            
+            // Auto precharge
+            always @ (*)
+            begin
+                granted_ap          [j_tbp] = (                      granted_col_grant [j_tbp]   & ap          ) | granted_ap          [j_tbp - 1];
+            end
+            
+            // Auto precharge
+            always @ (*)
+            begin
+                granted_burst_chop  [j_tbp] = (                      granted_col_grant [j_tbp]   & burst_chop  ) | granted_burst_chop  [j_tbp - 1];
+            end
+            
+            // RMW Correct
+            always @ (*)
+            begin
+                granted_rmw_correct [j_tbp] = (                      granted_col_grant [j_tbp]   & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
+            end
+            
+            // RMW Partial
+            always @ (*)
+            begin
+                granted_rmw_partial [j_tbp] = (                      granted_col_grant [j_tbp]   & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
+            end
+        end
+    end
+    endgenerate
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Outputs
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Arbiter
+//  
+//  Arbitration Rules (Priority Command-Aging Arbiter):
+//  
+//  - If only one master is requesting, grant that master immediately ELSE
+//  - If two of more masters are requesting:
+//      - Grant the request with priority ELSE
+//      - Grant read request over write request ELSE
+//      - Grant oldest request
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Common logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate OR of both grant signal
+    assign all_grant = row_grant | col_grant;
+    
+    //----------------------------------------------------------------------------------------------------
+    // Priority Command-aging logic
+    //----------------------------------------------------------------------------------------------------
+    // ==========Command-Aging==========
+    // 
+    // The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
+    // eg:  Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
+    //      Age dependecies will have the following value:
+    //          TBP0 age - 0000
+    //          TBP1 age - 0001
+    //          TBP2 age - 0011
+    //          TBP3 age - 0111
+    //      Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
+    //      TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
+    //      TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
+    //      So the oldest_req signal will have "0010"
+    // 
+    // ==========Priority==========
+    // 
+    // The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
+    // if there are more than 1 priority command, it will pick the oldest priority command
+    // eg:  Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
+    //      Age dependecies and priority bit will have the following value:
+    //          TBP0 age - 0000 priority - 0
+    //          TBP1 age - 0001 priority - 1
+    //          TBP2 age - 0011 priority - 1
+    //          TBP3 age - 0111 priority - 0
+    //      Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
+    //      and the rest will be set to '0'
+    
+    // If there is/are priority command/s, we need to select between those priority command
+    // if there is no priority command, we set int_priority to all '1'
+    // this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
+    
+    always @ (*)
+    begin
+        int_act_priority = {CFG_CTL_TBP_NUM{one}};
+        
+        int_pch_priority = {CFG_CTL_TBP_NUM{one}};
+        
+        if (CFG_DISABLE_PRIORITY == 1)
+        begin
+            int_col_priority = {CFG_CTL_TBP_NUM{one}};
+        end
+        else
+        begin
+            if ((tbp_priority & col_req) == 0)
+            begin
+                int_col_priority = {CFG_CTL_TBP_NUM{one}};
+            end
+            else
+            begin
+                int_col_priority = tbp_priority;
+            end
+        end
+    end
+    
+    generate
+    begin
+        genvar k_tbp;
+        for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
+        begin : priority_request_per_tbp
+            wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
+            
+            reg                            pre_calculated_act_info;
+            reg                            pre_calculated_pch_info;
+            reg                            pre_calculated_rd_info;
+            reg                            pre_calculated_wr_info;
+            
+            reg  [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
+            reg  [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
+            reg  [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
+            reg  [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
+            
+            if (CFG_REG_REQ)
+            begin
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        pre_calculated_act_info <= 1'b0;
+                        pre_calculated_pch_info <= 1'b0;
+                        pre_calculated_rd_info  <= 1'b0;
+                        pre_calculated_wr_info  <= 1'b0;
+                    end
+                    else
+                    begin
+                        pre_calculated_act_info <= int_act_priority [k_tbp];
+                        pre_calculated_pch_info <= int_pch_priority [k_tbp];
+                        pre_calculated_rd_info  <= int_col_priority [k_tbp];
+                        pre_calculated_wr_info  <= int_col_priority [k_tbp];
+                    end
+                end
+                
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        pre_calculated_act_age_info <= 0;
+                        pre_calculated_pch_age_info <= 0;
+                        pre_calculated_rd_age_info  <= 0;
+                        pre_calculated_wr_age_info  <= 0;
+                    end
+                    else
+                    begin
+                        pre_calculated_act_age_info <= current_age & int_act_priority;
+                        pre_calculated_pch_age_info <= current_age & int_pch_priority;
+                        pre_calculated_rd_age_info  <= current_age & int_col_priority;
+                        pre_calculated_wr_age_info  <= current_age & int_col_priority;
+                    end
+                end
+            end
+            else
+            begin
+                always @ (*)
+                begin
+                    pre_calculated_act_info = int_act_priority [k_tbp];
+                    pre_calculated_pch_info = int_pch_priority [k_tbp];
+                    pre_calculated_rd_info  = int_col_priority [k_tbp];
+                    pre_calculated_wr_info  = int_col_priority [k_tbp];
+                end
+                
+                always @ (*)
+                begin
+                    pre_calculated_act_age_info = current_age & int_act_priority;
+                    pre_calculated_pch_age_info = current_age & int_pch_priority;
+                    pre_calculated_rd_age_info  = current_age & int_col_priority;
+                    pre_calculated_wr_age_info  = current_age & int_col_priority;
+                end
+            end
+            
+            always @ (*)
+            begin
+                oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate  [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
+                oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
+                oldest_rd_req_with_priority  [k_tbp] = pre_calculated_rd_info  & rd_req  [k_tbp] & can_read      [k_tbp] & ~|(pre_calculated_rd_age_info  & rd_req  & can_read     );
+                oldest_wr_req_with_priority  [k_tbp] = pre_calculated_wr_info  & wr_req  [k_tbp] & can_write     [k_tbp] & ~|(pre_calculated_wr_age_info  & wr_req  & can_write    );
+            end
+            
+            always @ (*)
+            begin
+                act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate  [k_tbp];
+                pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
+                rd_req_with_priority  [k_tbp] = pre_calculated_rd_info  & rd_req  [k_tbp] & can_read      [k_tbp];
+                wr_req_with_priority  [k_tbp] = pre_calculated_wr_info  & wr_req  [k_tbp] & can_write     [k_tbp];
+            end
+        end
+    end
+    endgenerate
+    
+    
+    
+    //----------------------------------------------------------------------------------------------------
+    // Arbiter logic
+    //----------------------------------------------------------------------------------------------------
+    generate
+    begin
+        if (CFG_DWIDTH_RATIO == 2)
+        begin
+            // Full rate arbiter
+            always @ (*)
+            begin
+                int_row_grant    = 0;
+                int_col_grant    = 0;
+                int_act_grant    = 0;
+                int_pch_grant    = 0;
+                int_rd_grant     = 0;
+                int_wr_grant     = 0;
+                
+                int_or_row_grant = 1'b0;
+                int_or_col_grant = 1'b0;
+                int_or_act_grant = 1'b0;
+                int_or_pch_grant = 1'b0;
+                int_or_rd_grant  = 1'b0;
+                int_or_wr_grant  = 1'b0;
+                
+                if (!stall_col_arbiter && !internal_or_col_grant && |rd_req_with_priority)
+                begin
+                    int_col_grant    = oldest_rd_req_with_priority;
+                    int_rd_grant     = oldest_rd_req_with_priority;
+                    int_or_col_grant = 1'b1;
+                    int_or_rd_grant  = 1'b1;
+                end
+                else if (!stall_col_arbiter && !internal_or_col_grant && |wr_req_with_priority)
+                begin
+                    int_col_grant    = oldest_wr_req_with_priority;
+                    int_wr_grant     = oldest_wr_req_with_priority;
+                    int_or_col_grant = 1'b1;
+                    int_or_wr_grant  = 1'b1;
+                end
+                else if (!stall_row_arbiter && !internal_or_row_grant && |pch_req_with_priority)
+                begin
+                    int_row_grant    = oldest_pch_req_with_priority;
+                    int_pch_grant    = oldest_pch_req_with_priority;
+                    int_or_row_grant = 1'b1;
+                    int_or_pch_grant = 1'b1;
+                end
+                else if (!stall_row_arbiter && !internal_or_row_grant && |act_req_with_priority)
+                begin
+                    int_row_grant    = oldest_act_req_with_priority;
+                    int_act_grant    = oldest_act_req_with_priority;
+                    int_or_row_grant = 1'b1;
+                    int_or_act_grant = 1'b1;
+                end
+            end
+        end
+        else
+        begin
+            // Half and quarter rate arbiter
+            
+            // Row arbiter
+            always @ (*)
+            begin
+                int_row_grant    = 0;
+                int_act_grant    = 0;
+                int_pch_grant    = 0;
+                
+                int_or_row_grant = 1'b0;
+                int_or_act_grant = 1'b0;
+                int_or_pch_grant = 1'b0;
+                
+                if (!stall_row_arbiter && !internal_or_row_grant && |pch_req_with_priority)
+                begin
+                    int_row_grant    = oldest_pch_req_with_priority;
+                    int_pch_grant    = oldest_pch_req_with_priority;
+                    int_or_row_grant = 1'b1;
+                    int_or_pch_grant = 1'b1;
+                end
+                else if (!stall_row_arbiter && !internal_or_row_grant && |act_req_with_priority)
+                begin
+                    int_row_grant    = oldest_act_req_with_priority;
+                    int_act_grant    = oldest_act_req_with_priority;
+                    int_or_row_grant = 1'b1;
+                    int_or_act_grant = 1'b1;
+                end
+            end
+            
+            // Column arbiter
+            always @ (*)
+            begin
+                int_col_grant    = 0;
+                int_rd_grant     = 0;
+                int_wr_grant     = 0;
+                
+                int_or_col_grant = 1'b0;
+                int_or_rd_grant  = 1'b0;
+                int_or_wr_grant  = 1'b0;
+                
+                if (!stall_col_arbiter && !internal_or_col_grant && |rd_req_with_priority)
+                begin
+                    int_col_grant    = oldest_rd_req_with_priority;
+                    int_rd_grant     = oldest_rd_req_with_priority;
+                    int_or_col_grant = 1'b1;
+                    int_or_rd_grant  = 1'b1;
+                end
+                else if (!stall_col_arbiter && !internal_or_col_grant && |wr_req_with_priority)
+                begin
+                    int_col_grant    = oldest_wr_req_with_priority;
+                    int_wr_grant     = oldest_wr_req_with_priority;
+                    int_or_col_grant = 1'b1;
+                    int_or_wr_grant  = 1'b1;
+                end
+            end
+        end
+    end
+    endgenerate
+    
+    generate
+    begin
+        if (CFG_REG_GRANT == 1)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    row_grant      <= 0;
+                    col_grant      <= 0;
+                    
+                    act_grant      <= 0;
+                    pch_grant      <= 0;
+                    rd_grant       <= 0;
+                    wr_grant       <= 0;
+                    
+                    or_row_grant   <= 0;
+                    or_col_grant   <= 0;
+                    
+                    or_act_grant   <= 0;
+                    or_pch_grant   <= 0;
+                    or_rd_grant    <= 0;
+                    or_wr_grant    <= 0;
+                end
+                else
+                begin
+                    row_grant      <= int_row_grant;
+                    col_grant      <= int_col_grant;
+                    
+                    act_grant      <= int_act_grant;
+                    pch_grant      <= int_pch_grant;
+                    rd_grant       <= int_rd_grant;
+                    wr_grant       <= int_wr_grant;
+                    
+                    or_row_grant   <= int_or_row_grant;
+                    or_col_grant   <= int_or_col_grant;
+                    
+                    or_act_grant   <= int_or_act_grant;
+                    or_pch_grant   <= int_or_pch_grant;
+                    or_rd_grant    <= int_or_rd_grant;
+                    or_wr_grant    <= int_or_wr_grant;
+                end
+            end
+            
+            always @ (*)
+            begin
+                log2_row_grant = log2(row_grant);
+                log2_col_grant = log2(col_grant);
+                
+                log2_act_grant = log2(act_grant);
+                log2_pch_grant = log2(pch_grant);
+                log2_rd_grant  = log2(rd_grant );
+                log2_wr_grant  = log2(wr_grant );
+            end
+            
+            always @ (*)
+            begin
+                internal_or_row_grant = or_row_grant;
+                internal_or_col_grant = or_col_grant;
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                row_grant      = int_row_grant;
+                col_grant      = int_col_grant;
+                
+                act_grant      = int_act_grant;
+                pch_grant      = int_pch_grant;
+                rd_grant       = int_rd_grant;
+                wr_grant       = int_wr_grant;
+                
+                log2_row_grant = log2(int_row_grant);
+                log2_col_grant = log2(int_col_grant);
+                
+                log2_act_grant = log2(int_act_grant);
+                log2_pch_grant = log2(int_pch_grant);
+                log2_rd_grant  = log2(int_rd_grant );
+                log2_wr_grant  = log2(int_wr_grant );
+                
+                or_row_grant   = int_or_row_grant;
+                or_col_grant   = int_or_col_grant;
+                
+                or_act_grant   = int_or_act_grant;
+                or_pch_grant   = int_or_pch_grant;
+                or_rd_grant    = int_or_rd_grant;
+                or_wr_grant    = int_or_wr_grant;
+            end
+            
+            always @ (*)
+            begin
+                internal_or_row_grant = zero; // Hardwire to '0' because it's not require when col grant reg mode is disabled
+                internal_or_col_grant = zero; // Hardwire to '0' because it's not require when col grant reg mode is disabled
+            end
+        end
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Arbiter
+//
+//--------------------------------------------------------------------------------------------------------
+
+function integer log2;
+    input [31 : 0] value;
+    integer        i;
+    begin
+        log2 = 0;
+        for(i = 0;2 ** i < value;i = i + 1)
+        begin
+            log2 = i + 1;
+        end
+    end
+endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
new file mode 100644
index 0000000..416e9f3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
@@ -0,0 +1,1662 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_axi_st_converter #
+    ( parameter
+        AXI_ID_WIDTH      = 4,
+        AXI_ADDR_WIDTH    = 32,
+        AXI_LEN_WIDTH     = 4,
+        AXI_SIZE_WIDTH    = 3,
+        AXI_BURST_WIDTH   = 2,
+        AXI_LOCK_WIDTH    = 2,
+        AXI_CACHE_WIDTH   = 4,
+        AXI_PROT_WIDTH    = 3,
+        AXI_DATA_WIDTH    = 32,
+        AXI_RESP_WIDTH    = 4,
+        
+        ST_ADDR_WIDTH     = 32,
+        ST_SIZE_WIDTH     = 5,
+        ST_ID_WIDTH       = 4,
+        ST_DATA_WIDTH     = 32,
+        
+        COMMAND_ARB_TYPE  = "ROUND_ROBIN",
+        
+        REGISTERED        = 1
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // AXI Interface
+        // Write address channel
+        awid,
+        awaddr,
+        awlen,
+        awsize,
+        awburst,
+        awlock,
+        awcache,
+        awprot,
+        awvalid,
+        awready,
+        
+        // Write data channel
+        wid,
+        wdata,
+        wstrb,
+        wlast,
+        wvalid,
+        wready,
+        
+        // Write response channel
+        bid,
+        bresp,
+        bvalid,
+        bready,
+        
+        // Read address channel
+        arid,
+        araddr,
+        arlen,
+        arsize,
+        arburst,
+        arlock,
+        arcache,
+        arprot,
+        arvalid,
+        arready,
+        
+        // Read data channel
+        rid,
+        rdata,
+        rresp,
+        rlast,
+        rvalid,
+        rready,
+        
+        // Avalon ST Interface
+        // Command channel
+        itf_cmd_ready,
+        itf_cmd_valid,
+        itf_cmd,
+        itf_cmd_address,
+        itf_cmd_burstlen,
+        itf_cmd_id,
+        itf_cmd_priority,
+        itf_cmd_autoprecharge,
+        itf_cmd_multicast,
+        
+        // Write data channel
+        itf_wr_data_ready,
+        itf_wr_data_valid,
+        itf_wr_data,
+        itf_wr_data_byte_en,
+        itf_wr_data_begin,
+        itf_wr_data_last,
+        itf_wr_data_id,
+        
+        // Read data channel
+        itf_rd_data_ready,
+        itf_rd_data_valid,
+        itf_rd_data,
+        itf_rd_data_error,
+        itf_rd_data_begin,
+        itf_rd_data_last,
+        itf_rd_data_id
+    );
+
+input                               ctl_clk;
+input                               ctl_reset_n;
+
+// AXI Interface
+// Write address channel
+input  [AXI_ID_WIDTH       - 1 : 0] awid;
+input  [AXI_ADDR_WIDTH     - 1 : 0] awaddr;
+input  [AXI_LEN_WIDTH      - 1 : 0] awlen;
+input  [AXI_SIZE_WIDTH     - 1 : 0] awsize;
+input  [AXI_BURST_WIDTH    - 1 : 0] awburst;
+input  [AXI_LOCK_WIDTH     - 1 : 0] awlock;
+input  [AXI_CACHE_WIDTH    - 1 : 0] awcache;
+input  [AXI_PROT_WIDTH     - 1 : 0] awprot;
+input                               awvalid;
+output                              awready;
+
+// Write data channel
+input  [AXI_ID_WIDTH       - 1 : 0] wid;
+input  [AXI_DATA_WIDTH     - 1 : 0] wdata;
+input  [AXI_DATA_WIDTH / 8 - 1 : 0] wstrb;
+input                               wlast;
+input                               wvalid;
+output                              wready;
+
+// Write response channel
+output [AXI_ID_WIDTH       - 1 : 0] bid;
+output [AXI_RESP_WIDTH     - 1 : 0] bresp;
+output                              bvalid;
+input                               bready;
+
+// Read address channel
+input  [AXI_ID_WIDTH       - 1 : 0] arid;
+input  [AXI_ADDR_WIDTH     - 1 : 0] araddr;
+input  [AXI_LEN_WIDTH      - 1 : 0] arlen;
+input  [AXI_SIZE_WIDTH     - 1 : 0] arsize;
+input  [AXI_BURST_WIDTH    - 1 : 0] arburst;
+input  [AXI_LOCK_WIDTH     - 1 : 0] arlock;
+input  [AXI_CACHE_WIDTH    - 1 : 0] arcache;
+input  [AXI_PROT_WIDTH     - 1 : 0] arprot;
+input                               arvalid;
+output                              arready;
+
+// Read data channel
+output [AXI_ID_WIDTH       - 1 : 0] rid;
+output [AXI_DATA_WIDTH     - 1 : 0] rdata;
+output [AXI_RESP_WIDTH     - 1 : 0] rresp;
+output                              rlast;
+output                              rvalid;
+input                               rready;
+
+// Avalon ST Interface
+// Command channel
+input                               itf_cmd_ready;
+output                              itf_cmd_valid;
+output                              itf_cmd;
+output [ST_ADDR_WIDTH      - 1 : 0] itf_cmd_address;
+output [ST_SIZE_WIDTH      - 1 : 0] itf_cmd_burstlen;
+output [ST_ID_WIDTH        - 1 : 0] itf_cmd_id;
+output                              itf_cmd_priority;
+output                              itf_cmd_autoprecharge;
+output                              itf_cmd_multicast;
+
+// Write data channel
+input                               itf_wr_data_ready;
+output                              itf_wr_data_valid;
+output [ST_DATA_WIDTH      - 1 : 0] itf_wr_data;
+output [ST_DATA_WIDTH / 8  - 1 : 0] itf_wr_data_byte_en;
+output                              itf_wr_data_begin;
+output                              itf_wr_data_last;
+output [ST_ID_WIDTH        - 1 : 0] itf_wr_data_id;
+
+// Read data channel
+output                              itf_rd_data_ready;
+input                               itf_rd_data_valid;
+input [ST_DATA_WIDTH       - 1 : 0] itf_rd_data;
+input                               itf_rd_data_error;
+input                               itf_rd_data_begin;
+input                               itf_rd_data_last;
+input [ST_ID_WIDTH         - 1 : 0] itf_rd_data_id;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Registers & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // AXI outputs
+    reg                              awready;
+    reg                              wready;
+    reg  [AXI_ID_WIDTH      - 1 : 0] bid;
+    reg  [AXI_RESP_WIDTH    - 1 : 0] bresp;
+    reg                              bvalid;
+    reg                              arready;
+    reg  [AXI_ID_WIDTH      - 1 : 0] rid;
+    reg  [AXI_DATA_WIDTH    - 1 : 0] rdata;
+    reg  [AXI_RESP_WIDTH    - 1 : 0] rresp;
+    reg                              rlast;
+    reg                              rvalid;
+    
+    // ST outputs
+    reg                              itf_cmd_valid;
+    reg                              itf_cmd;
+    reg  [ST_ADDR_WIDTH     - 1 : 0] itf_cmd_address;
+    reg  [ST_SIZE_WIDTH     - 1 : 0] itf_cmd_burstlen;
+    reg  [ST_ID_WIDTH       - 1 : 0] itf_cmd_id;
+    reg                              itf_cmd_priority;
+    reg                              itf_cmd_autoprecharge;
+    reg                              itf_cmd_multicast;
+    reg                              itf_wr_data_valid;
+    reg  [ST_DATA_WIDTH     - 1 : 0] itf_wr_data;
+    reg  [ST_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
+    reg                              itf_wr_data_begin;
+    reg                              itf_wr_data_last;
+    reg  [ST_ID_WIDTH       - 1 : 0] itf_wr_data_id;
+    reg                              itf_rd_data_ready;
+    
+    wire one  = 1'b1;
+    wire zero = 1'b0;
+    
+    // Command channel
+    localparam WORD_ADDR_OFFSET = log2(AXI_DATA_WIDTH / 8);
+    localparam NATIVE_AXI_SIZE  = log2(AXI_DATA_WIDTH) - 3;
+    
+    integer i;
+    
+    wire [AXI_ADDR_WIDTH      - 1 : 0] byte_rd_addr;
+    wire [AXI_ADDR_WIDTH      - 1 : 0] byte_wr_addr;
+    
+    wire                               rd_req;
+    wire                               wr_req;
+    wire [1                       : 0] cmd_req;
+    wire                               rd_grant;
+    wire                               wr_grant;
+    
+    wire [ST_ID_WIDTH         - 1 : 0] rd_id;
+    wire [ST_ID_WIDTH         - 1 : 0] wr_id;
+    
+    reg  [AXI_ID_WIDTH        - 1 : 0] int_awid;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_awaddr;
+    reg  [AXI_LEN_WIDTH       - 1 : 0] int_awlen;
+    reg  [AXI_SIZE_WIDTH      - 1 : 0] int_awsize;
+    reg  [AXI_BURST_WIDTH     - 1 : 0] int_awburst;
+    reg  [AXI_LOCK_WIDTH      - 1 : 0] int_awlock;
+    reg  [AXI_CACHE_WIDTH     - 1 : 0] int_awcache;
+    reg  [AXI_PROT_WIDTH      - 1 : 0] int_awprot;
+    reg                                int_awvalid;
+    
+    reg  [AXI_ID_WIDTH        - 1 : 0] int_arid;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_araddr;
+    reg  [AXI_LEN_WIDTH       - 1 : 0] int_arlen;
+    reg  [AXI_SIZE_WIDTH      - 1 : 0] int_arsize;
+    reg  [AXI_BURST_WIDTH     - 1 : 0] int_arburst;
+    reg  [AXI_LOCK_WIDTH      - 1 : 0] int_arlock;
+    reg  [AXI_CACHE_WIDTH     - 1 : 0] int_arcache;
+    reg  [AXI_PROT_WIDTH      - 1 : 0] int_arprot;
+    reg                                int_arvalid;
+    
+    reg                                int_cmd_valid;
+    reg                                int_cmd;
+    reg  [ST_ADDR_WIDTH       - 1 : 0] int_cmd_address;
+    reg  [ST_SIZE_WIDTH       - 1 : 0] int_cmd_burstlen;
+    reg  [ST_ID_WIDTH         - 1 : 0] int_cmd_id;
+    reg                                int_cmd_priority;
+    reg                                int_cmd_autoprecharge;
+    reg                                int_cmd_multicast;
+    
+    reg                                int_awready;
+    reg                                int_arready;
+    
+    reg  [2 ** AXI_SIZE_WIDTH - 1 : 0] rd_size;
+    reg  [2 ** AXI_SIZE_WIDTH - 1 : 0] wr_size;
+    reg  [2 ** AXI_SIZE_WIDTH - 1 : 0] current_size;
+    
+    reg  [2 ** AXI_SIZE_WIDTH - 1 : 0] int_size;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] byte_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] byte_addr_counter;
+    reg  [ST_ADDR_WIDTH       - 1 : 0] registered_word_addr;
+    reg  [ST_ADDR_WIDTH       - 1 : 0] word_rd_addr;
+    reg  [ST_ADDR_WIDTH       - 1 : 0] word_wr_addr;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_byte_rd_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_byte_wr_addr;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] aligned_byte_rd_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] aligned_byte_wr_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] boundary_byte_rd_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] boundary_byte_wr_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] boundary_byte_rd_addr_increment;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] boundary_byte_wr_addr_increment;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_aligned_byte_rd_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_aligned_byte_wr_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_boundary_byte_rd_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_boundary_byte_wr_addr_mask;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_boundary_byte_rd_addr_increment;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] int_boundary_byte_wr_addr_increment;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] aligned_byte_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] aligned_byte_rd_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] aligned_byte_wr_addr;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] lower_wrap_boundary_byte_rd_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] upper_wrap_boundary_byte_rd_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] lower_wrap_boundary_byte_wr_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] upper_wrap_boundary_byte_wr_addr;
+    
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] lower_wrap_boundary_byte_addr;
+    reg  [AXI_ADDR_WIDTH      - 1 : 0] upper_wrap_boundary_byte_addr;
+    
+    reg                                upper_boundary_reached;
+    
+    reg  [AXI_BURST_WIDTH     - 1 : 0] burst_type;
+    
+    reg                                doing_write;
+    reg  [1                       : 0] cmd_grant;
+    reg  [1                       : 0] prev_cmd_grant;
+    
+    reg                                split_axi_cmd;
+    reg                                doing_split;
+    reg  [ST_SIZE_WIDTH       - 1 : 0] split_counter;
+    reg  [ST_SIZE_WIDTH       - 1 : 0] rd_burstlen;
+    reg  [ST_SIZE_WIDTH       - 1 : 0] wr_burstlen;
+    
+    reg                                int_grant;
+    reg                                int_rd_grant;
+    reg                                int_wr_grant;
+    reg                                int_doing_split;
+    
+    reg  [ST_ID_WIDTH         - 1 : 0] registered_id;
+    
+    // Write data channel
+    reg                              int_wr_data_valid;
+    reg  [ST_DATA_WIDTH     - 1 : 0] int_wr_data;
+    reg  [ST_DATA_WIDTH / 8 - 1 : 0] int_wr_data_byte_en;
+    reg                              int_wr_data_begin;
+    reg                              int_wr_data_last;
+    reg  [ST_ID_WIDTH       - 1 : 0] int_wr_data_id;
+    
+    reg                              write_data_begin_n;
+    
+    // Write response channel
+    localparam WR_CMD_FIFO_DATA_WIDTH  = AXI_ID_WIDTH;
+    localparam WR_CMD_FIFO_ADDR_WIDTH  = 5; // expected to be able to hold 32 in-flight command information
+    localparam WR_CMD_FIFO_DEPTH       = 2 ** WR_CMD_FIFO_ADDR_WIDTH;
+    
+    localparam WR_DATA_FIFO_DATA_WIDTH = AXI_ID_WIDTH;
+    localparam WR_DATA_FIFO_ADDR_WIDTH = 5; // expected to be able to hold 32 in-flight command information
+    localparam WR_DATA_FIFO_DEPTH      = 2 ** WR_DATA_FIFO_ADDR_WIDTH;
+    
+    wire                                  wr_cmd_fifo_write;
+    wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_write_data;
+    wire                                  wr_cmd_fifo_read;
+    wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_cmd_fifo_read_data;
+    wire                                  wr_cmd_fifo_read_data_valid;
+    wire                                  wr_cmd_fifo_empty;
+    wire                                  wr_cmd_fifo_almost_full;
+    
+    wire                                  wr_data_fifo_write;
+    wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_write_data;
+    wire                                  wr_data_fifo_read;
+    wire [WR_CMD_FIFO_DATA_WIDTH - 1 : 0] wr_data_fifo_read_data;
+    wire                                  wr_data_fifo_read_data_valid;
+    wire                                  wr_data_fifo_empty;
+    wire                                  wr_data_fifo_almost_full;
+    
+    reg                                   wr_cmd_fifo_ready;
+    reg                                   wr_data_fifo_ready;
+    
+    reg                                   id_matched;
+    
+    reg  [AXI_ID_WIDTH           - 1 : 0] int_bid;
+    reg  [AXI_RESP_WIDTH         - 1 : 0] int_bresp;
+    reg                                   int_bvalid;
+    
+    // Read data channel
+    localparam RD_CMD_FIFO_DATA_WIDTH  = AXI_LEN_WIDTH + 1;
+    localparam RD_CMD_FIFO_ADDR_WIDTH  = 5; // expected to be able to hold 32 in-flight command information
+    localparam RD_CMD_FIFO_DEPTH       = 2 ** RD_CMD_FIFO_ADDR_WIDTH;
+    
+    wire                                  rd_cmd_fifo_write;
+    wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_write_data;
+    wire                                  rd_cmd_fifo_read;
+    wire [RD_CMD_FIFO_DATA_WIDTH - 1 : 0] rd_cmd_fifo_read_data;
+    wire                                  rd_cmd_fifo_read_data_valid;
+    wire                                  rd_cmd_fifo_empty;
+    wire                                  rd_cmd_fifo_almost_full;
+    
+    reg                                   rd_cmd_fifo_ready;
+    
+    reg  [AXI_ID_WIDTH           - 1 : 0] int_rid;
+    reg  [AXI_DATA_WIDTH         - 1 : 0] int_rdata;
+    reg  [AXI_RESP_WIDTH         - 1 : 0] int_rresp;
+    reg                                   int_rlast;
+    reg                                   int_rvalid;
+    
+    reg                                   int_rd_data_ready;
+    
+    reg [RD_CMD_FIFO_DATA_WIDTH  - 1 : 0] read_data_counter;
+    reg                                   read_data_last;
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Registers & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Command Channel
+//
+//--------------------------------------------------------------------------------------------------------
+    //--------------------------------------------------------------------------
+    // AXI inputs
+    //--------------------------------------------------------------------------
+    always @ (*)
+    begin
+        int_awid    = awid;
+        int_awaddr  = awaddr;
+        int_awlen   = awlen;
+        int_awsize  = awsize;
+        int_awburst = awburst;
+        int_awlock  = awlock;
+        int_awcache = awcache;
+        int_awprot  = awprot;
+        int_awvalid = awvalid;
+        
+        int_arid    = arid;
+        int_araddr  = araddr;
+        int_arlen   = arlen;
+        int_arsize  = arsize;
+        int_arburst = arburst;
+        int_arlock  = arlock;
+        int_arcache = arcache;
+        int_arprot  = arprot;
+        int_arvalid = arvalid;
+    end
+    
+    //--------------------------------------------------------------------------
+    // Size related logics
+    //--------------------------------------------------------------------------
+    always @ (*)
+    begin
+        rd_size = (2 ** int_arsize);
+        wr_size = (2 ** int_awsize);
+    end
+    
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_size    <= 0;
+                end
+                else
+                begin
+                    if (rd_grant)
+                    begin
+                        int_size <= rd_size;
+                    end
+                    else if (wr_grant)
+                    begin
+                        int_size <= wr_size;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                if (rd_grant)
+                begin
+                    int_size = rd_size;
+                end
+                else if (wr_grant)
+                begin
+                    int_size = wr_size;
+                end
+                else
+                begin
+                    int_size = 0;
+                end
+            end
+        end
+    end
+    endgenerate
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            current_size <= 0;
+        end
+        else
+        begin
+            if (rd_grant)
+            begin
+                current_size <= rd_size;
+            end
+            else if (wr_grant)
+            begin
+                current_size <= wr_size;
+            end
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // Address related logics
+    //--------------------------------------------------------------------------
+    assign byte_rd_addr = int_araddr;
+    assign byte_wr_addr = int_awaddr;
+    
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_byte_rd_addr <= 0;
+                    int_byte_wr_addr <= 0;
+                end
+                else
+                begin
+                    if (itf_cmd_ready)
+                    begin
+                        int_byte_rd_addr <= byte_rd_addr;
+                        int_byte_wr_addr <= byte_wr_addr;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                int_byte_rd_addr = byte_rd_addr;
+                int_byte_wr_addr = byte_wr_addr;
+            end
+        end
+    end
+    endgenerate
+    
+    // Obtain address mask for aligned address
+    always @ (*)
+    begin
+        aligned_byte_rd_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
+        aligned_byte_wr_addr_mask = {AXI_ADDR_WIDTH{1'b1}};
+        
+        for (i = 0;i < (2 ** AXI_SIZE_WIDTH);i = i + 1'b1)
+        begin
+            if (int_arsize > i)
+            begin
+                aligned_byte_rd_addr_mask [i] = 1'b0;
+            end
+            
+            if (int_awsize > i)
+            begin
+                aligned_byte_wr_addr_mask [i] = 1'b0;
+            end
+        end
+    end
+    
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_aligned_byte_rd_addr_mask <= 0;
+                    int_aligned_byte_wr_addr_mask <= 0;
+                end
+                else
+                begin
+                    if (itf_cmd_ready)
+                    begin
+                        int_aligned_byte_rd_addr_mask <= aligned_byte_rd_addr_mask;
+                        int_aligned_byte_wr_addr_mask <= aligned_byte_wr_addr_mask;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                int_aligned_byte_rd_addr_mask = aligned_byte_rd_addr_mask;
+                int_aligned_byte_wr_addr_mask = aligned_byte_wr_addr_mask;
+            end
+        end
+    end
+    endgenerate
+    
+    // Obtain aligned address
+    always @ (*)
+    begin
+        aligned_byte_rd_addr = (int_byte_rd_addr & int_aligned_byte_rd_addr_mask);
+        aligned_byte_wr_addr = (int_byte_wr_addr & int_aligned_byte_wr_addr_mask);
+    end
+    
+    always @ (*)
+    begin
+        if (int_rd_grant)
+        begin
+            aligned_byte_addr = aligned_byte_rd_addr;
+        end
+        else if (int_wr_grant)
+        begin
+            aligned_byte_addr = aligned_byte_wr_addr;
+        end
+        else
+        begin
+            aligned_byte_addr = 0;
+        end
+    end
+    
+    // Obtain boundary address mask for wrapping burst
+    always @ (*)
+    begin
+        boundary_byte_rd_addr_mask      = {AXI_ADDR_WIDTH{1'b1}};
+        boundary_byte_wr_addr_mask      = {AXI_ADDR_WIDTH{1'b1}};
+        
+        for (i = 0;i < ((2 ** AXI_SIZE_WIDTH) + 4);i = i + 1'b1) // extend by another 4 because max length for wrapping burst is 16
+        begin
+            if ((int_arsize + log2_minus_one(int_arlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
+            begin
+                boundary_byte_rd_addr_mask [i] = 1'b0;
+            end
+            
+            if ((int_awsize + log2_minus_one(int_awlen[3:0])) > i) // constraint burstlen to 4 bits because max length for wrapping burst is 16
+            begin
+                boundary_byte_wr_addr_mask [i] = 1'b0;
+            end
+        end
+    end
+    
+    // Obtain boundary increment value for wrapping burst
+    always @ (*)
+    begin
+        boundary_byte_rd_addr_increment = aligned_byte_rd_addr_mask & ~boundary_byte_rd_addr_mask;
+        boundary_byte_wr_addr_increment = aligned_byte_wr_addr_mask & ~boundary_byte_wr_addr_mask;
+    end
+    
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_boundary_byte_rd_addr_mask      <= 0;
+                    int_boundary_byte_wr_addr_mask      <= 0;
+                    int_boundary_byte_rd_addr_increment <= 0;
+                    int_boundary_byte_wr_addr_increment <= 0;
+                end
+                else
+                begin
+                    if (itf_cmd_ready)
+                    begin
+                        int_boundary_byte_rd_addr_mask      <= boundary_byte_rd_addr_mask;
+                        int_boundary_byte_wr_addr_mask      <= boundary_byte_wr_addr_mask;
+                        int_boundary_byte_rd_addr_increment <= boundary_byte_rd_addr_increment;
+                        int_boundary_byte_wr_addr_increment <= boundary_byte_wr_addr_increment;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                int_boundary_byte_rd_addr_mask      = boundary_byte_rd_addr_mask;
+                int_boundary_byte_wr_addr_mask      = boundary_byte_wr_addr_mask;
+                int_boundary_byte_rd_addr_increment = boundary_byte_rd_addr_increment;
+                int_boundary_byte_wr_addr_increment = boundary_byte_wr_addr_increment;
+            end
+        end
+    end
+    endgenerate
+    
+    // Obtain upper and lower boundary of wrapping burst
+    always @ (*)
+    begin
+        lower_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask);
+        lower_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask);
+        upper_wrap_boundary_byte_rd_addr = (int_byte_rd_addr & int_boundary_byte_rd_addr_mask) + int_boundary_byte_rd_addr_increment;
+        upper_wrap_boundary_byte_wr_addr = (int_byte_wr_addr & int_boundary_byte_wr_addr_mask) + int_boundary_byte_wr_addr_increment;
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            lower_wrap_boundary_byte_addr <= 0;
+            upper_wrap_boundary_byte_addr <= 0;
+        end
+        else
+        begin
+            if (int_wr_grant)
+            begin
+                lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_wr_addr;
+                upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_wr_addr;
+            end
+            else if (int_rd_grant)
+            begin
+                lower_wrap_boundary_byte_addr <= lower_wrap_boundary_byte_rd_addr;
+                upper_wrap_boundary_byte_addr <= upper_wrap_boundary_byte_rd_addr;
+            end
+        end
+    end
+    
+    // Byte address counter, to count up for a AXI command with len larger than 1
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            byte_addr_counter <= 0;
+        end
+        else
+        begin
+            if (int_grant)
+            begin
+                byte_addr_counter <= aligned_byte_addr + int_size;
+            end
+            else if (itf_cmd_ready)
+            begin
+                byte_addr_counter <= byte_addr + current_size;
+            end
+        end
+    end
+    
+    // Determine whether current burst reached upper wrap boundary
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            upper_boundary_reached <= 1'b0;
+        end
+        else
+        begin
+            if (int_rd_grant)
+            begin
+                if (aligned_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_rd_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
+                begin
+                    upper_boundary_reached <= 1'b1;
+                end
+                else
+                begin
+                    upper_boundary_reached <= 1'b0;
+                end
+            end
+            else if (int_wr_grant)
+            begin
+                if (aligned_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_wr_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
+                begin
+                    upper_boundary_reached <= 1'b1;
+                end
+                else
+                begin
+                    upper_boundary_reached <= 1'b0;
+                end
+            end
+            else if (itf_cmd_ready)
+            begin
+                if (byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0] == upper_wrap_boundary_byte_addr [(2 ** AXI_SIZE_WIDTH) + 3 : 0])
+                begin
+                    upper_boundary_reached <= 1'b1;
+                end
+                else
+                begin
+                    upper_boundary_reached <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    // Byte address for wrapping burst command
+    always @ (*)
+    begin
+        if (burst_type == 2'd2 && upper_boundary_reached)
+        begin
+            byte_addr = lower_wrap_boundary_byte_addr;
+        end
+        else
+        begin
+            byte_addr = byte_addr_counter;
+        end
+    end
+    
+    // Byte to word address conversion logic
+    always @ (*)
+    begin
+        word_rd_addr         = 0;
+        word_wr_addr         = 0;
+        registered_word_addr = 0;
+        
+        word_rd_addr         = int_byte_rd_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
+        word_wr_addr         = int_byte_wr_addr [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
+        registered_word_addr = byte_addr        [AXI_ADDR_WIDTH - 1 : WORD_ADDR_OFFSET];
+    end
+    
+    // Command address to Avalon ST interface
+    always @ (*)
+    begin
+        if (int_wr_grant)
+        begin
+            int_cmd_address = word_wr_addr;
+        end
+        else if (int_rd_grant)
+        begin
+            int_cmd_address = word_rd_addr;
+        end
+        else if (int_doing_split)
+        begin
+            int_cmd_address = registered_word_addr;
+        end
+        else
+        begin
+            int_cmd_address = 0;
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // Command related logics
+    //--------------------------------------------------------------------------
+    assign rd_req  = int_arvalid & int_arready;
+    assign wr_req  = int_awvalid & int_awready;
+    assign cmd_req = {rd_req, wr_req};
+    
+    assign {rd_grant, wr_grant} = cmd_grant;
+    
+    // Command arbitration logic
+    generate
+    begin
+        if (COMMAND_ARB_TYPE == "ROUND_ROBIN")
+        begin
+            always @ (*)
+            begin
+                if (&cmd_req) // both command requesting at the same time
+                begin
+                    cmd_grant = prev_cmd_grant;
+                end
+                else
+                begin
+                    cmd_grant = cmd_req;
+                end
+            end
+        end
+        else if (COMMAND_ARB_TYPE == "WRITE_PRIORITY")
+        begin
+            always @ (*)
+            begin
+                if (&cmd_req) // both command requesting at the same time
+                begin
+                    cmd_grant = 2'b01; // make sure we always grant write request
+                end
+                else
+                begin
+                    cmd_grant = cmd_req;
+                end
+            end
+        end
+        else if (COMMAND_ARB_TYPE == "READ_PRIORITY")
+        begin
+            always @ (*)
+            begin
+                if (&cmd_req) // both command requesting at the same time
+                begin
+                    cmd_grant = 2'b10; // make sure we always grant read request
+                end
+                else
+                begin
+                    cmd_grant = cmd_req;
+                end
+            end
+        end
+    end
+    endgenerate
+    
+    // Previous command grant
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            prev_cmd_grant <= 2'b01; // default round robin priority
+        end
+        else
+        begin
+            if (|cmd_grant)
+            begin
+                prev_cmd_grant <= ~cmd_grant;
+            end
+        end
+    end
+    
+    // Grant signal for registered output
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_grant       <= 1'b0;
+                    int_wr_grant    <= 1'b0;
+                    int_rd_grant    <= 1'b0;
+                    int_doing_split <= 1'b0;
+                end
+                else
+                begin
+                    if (itf_cmd_ready)
+                    begin
+                        int_grant       <= wr_grant | rd_grant;
+                        int_wr_grant    <= wr_grant;
+                        int_rd_grant    <= rd_grant;
+                        int_doing_split <= doing_split;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                int_grant       = wr_grant | rd_grant;
+                int_wr_grant    = wr_grant;
+                int_rd_grant    = rd_grant;
+                int_doing_split = doing_split;
+            end
+        end
+    end
+    endgenerate
+    
+    // Doing write logic, indicate what we did last
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            doing_write <= 1'b0;
+        end
+        else
+        begin
+            if (wr_grant)
+            begin
+                doing_write <= 1'b1;
+            end
+            else if (rd_grant)
+            begin
+                doing_write <= 1'b0;
+            end
+        end
+    end
+    
+    // Command & valid to Avalon ST interface
+    always @ (*)
+    begin
+        if (wr_grant)
+        begin
+            int_cmd       = 1'b1; // Set command to '1' when there is a write, else '0'
+            int_cmd_valid = 1'b1;
+        end
+        else if (rd_grant)
+        begin
+            int_cmd       = 1'b0; // Set command to '1' when there is a write, else '0'
+            int_cmd_valid = 1'b1;
+        end
+        else if (doing_split)
+        begin
+            int_cmd       = doing_write;
+            int_cmd_valid = 1'b1;
+        end
+        else
+        begin
+            int_cmd       = 1'b0;
+            int_cmd_valid = 1'b0;
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // Burst related logics
+    //--------------------------------------------------------------------------
+    // Splitting logic
+    // we will split AXI command into multiple smaller Avalon ST commands if size if not equal to data width
+    // or when burst type is set to WRAP
+    always @ (*)
+    begin
+        if (wr_grant)
+        begin
+            split_axi_cmd = ((int_awsize != NATIVE_AXI_SIZE || int_awburst == 2) && int_awlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
+        end
+        else if (rd_grant)
+        begin
+            split_axi_cmd = ((int_arsize != NATIVE_AXI_SIZE || int_arburst == 2) && int_arlen != 0) ? 1'b1 : 1'b0; // don't need to split when size is '1'
+        end
+        else
+        begin
+            split_axi_cmd = 1'b0;
+        end
+    end
+    
+    // Splitting logic
+    // to keep track of how many commands to split
+    // also to tell other logic that it's currently doing split now
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            split_counter <= 0;
+            doing_split   <= 1'b0;
+        end
+        else
+        begin
+            if (wr_grant)
+            begin
+                split_counter <= int_awlen;
+                
+                if (split_axi_cmd)
+                begin
+                    doing_split <= 1'b1;
+                end
+                else
+                begin
+                    doing_split <= 1'b0;
+                end
+            end
+            else if (rd_grant)
+            begin
+                split_counter <= int_arlen;
+                
+                if (split_axi_cmd)
+                begin
+                    doing_split <= 1'b1;
+                end
+                else
+                begin
+                    doing_split <= 1'b0;
+                end
+            end
+            else if (itf_cmd_ready)
+            begin
+                if (split_counter != {ST_SIZE_WIDTH{1'b0}})
+                begin
+                    split_counter <= split_counter - 1'b1;
+                end
+                
+                if (split_counter == 1'b1)
+                begin
+                    doing_split <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    // Convert AXI len to Avalon ST burst size
+    always @ (*)
+    begin
+        rd_burstlen = int_arlen + 1'b1;
+        wr_burstlen = int_awlen + 1'b1;
+    end
+    
+    // Burst size to Avalon ST interface
+    always @ (*)
+    begin
+        if (wr_grant)
+        begin
+            int_cmd_burstlen = (split_axi_cmd) ? 1'b1: wr_burstlen;
+        end
+        else if (rd_grant)
+        begin
+            int_cmd_burstlen = (split_axi_cmd) ? 1'b1: rd_burstlen;
+        end
+        else if (doing_split)
+        begin
+            int_cmd_burstlen = 1'b1; // Size will always equal to '1' during spliting process
+        end
+        else
+        begin
+            int_cmd_burstlen = 0;
+        end
+    end
+    
+    // Burst type
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            burst_type <= 0;
+        end
+        else
+        begin
+            if (wr_grant)
+            begin
+                burst_type <= int_awburst;
+            end
+            else if (rd_grant)
+            begin
+                burst_type <= int_arburst;
+            end
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // ID related logics
+    //--------------------------------------------------------------------------
+    assign rd_id = int_arid;
+    assign wr_id = int_awid;
+    
+    // Registered ID, keep track of previous ID
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            registered_id <= 0;
+        end
+        else
+        begin
+            if (wr_grant)
+            begin
+                registered_id <= wr_id;
+            end
+            else if (rd_grant)
+            begin
+                registered_id <= rd_id;
+            end
+        end
+    end
+    
+    // Transfer AXI ID to Avalon ST interface
+    always @ (*)
+    begin
+        if (wr_grant)
+        begin
+            int_cmd_id = wr_id;
+        end
+        else if (rd_grant)
+        begin
+            int_cmd_id = rd_id;
+        end
+        else if (doing_split)
+        begin
+            int_cmd_id = registered_id;
+        end
+        else
+        begin
+            int_cmd_id = 0;
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // Others
+    //--------------------------------------------------------------------------
+    // Setting inband signals to '0'
+    always @ (*)
+    begin
+        int_cmd_priority      = zero;
+        int_cmd_autoprecharge = zero;
+        int_cmd_multicast     = zero;
+    end
+    
+    //--------------------------------------------------------------------------
+    // Outputs
+    //--------------------------------------------------------------------------
+    // AXI command output assignment
+    always @ (*)
+    begin
+        // disable ready signal during split or when FIFO is full
+        int_awready = itf_cmd_ready & ~doing_split & wr_cmd_fifo_ready;
+        int_arready = itf_cmd_ready & ~doing_split & rd_cmd_fifo_ready;
+    end
+    
+    always @ (*)
+    begin
+        // disable ready signal when granting other channel
+        awready = int_awready & ~rd_grant;
+        arready = int_arready & ~wr_grant;
+    end
+    
+    // Avalon ST command output assignment
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    itf_cmd_valid         <= 0;
+                    itf_cmd               <= 0;
+                    itf_cmd_burstlen      <= 0;
+                    itf_cmd_id            <= 0;
+                    itf_cmd_priority      <= 0;
+                    itf_cmd_autoprecharge <= 0;
+                    itf_cmd_multicast     <= 0;
+                end
+                else
+                begin
+                    if (itf_cmd_ready)
+                    begin
+                        itf_cmd_valid         <= int_cmd_valid;
+                        itf_cmd               <= int_cmd;
+                        itf_cmd_burstlen      <= int_cmd_burstlen;
+                        itf_cmd_id            <= int_cmd_id;
+                        itf_cmd_priority      <= int_cmd_priority;
+                        itf_cmd_autoprecharge <= int_cmd_autoprecharge;
+                        itf_cmd_multicast     <= int_cmd_multicast;
+                    end
+                end
+            end
+            
+            always @ (*)
+            begin
+                itf_cmd_address       = int_cmd_address;
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                itf_cmd_valid         = int_cmd_valid;
+                itf_cmd               = int_cmd;
+                itf_cmd_address       = int_cmd_address;
+                itf_cmd_burstlen      = int_cmd_burstlen;
+                itf_cmd_id            = int_cmd_id;
+                itf_cmd_priority      = int_cmd_priority;
+                itf_cmd_autoprecharge = int_cmd_autoprecharge;
+                itf_cmd_multicast     = int_cmd_multicast;
+            end
+        end
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Command Channel
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Write Data Channel
+//
+//--------------------------------------------------------------------------------------------------------
+    //--------------------------------------------------------------------------
+    // Write data begin logic
+    //--------------------------------------------------------------------------
+    // Determine write data begin based on write data last information
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            write_data_begin_n <= 1'b0;
+        end
+        else
+        begin
+            if (wlast & wready)
+            begin
+                write_data_begin_n <= 1'b0;
+            end
+            else if (wvalid & wready) // received a write data packet
+            begin
+                write_data_begin_n <= 1'b1;
+            end
+        end
+    end
+    
+    // Write data begin logic
+    always @ (*)
+    begin
+        if (wvalid & wready)
+        begin
+            int_wr_data_begin = ~write_data_begin_n;
+        end
+        else
+        begin
+            int_wr_data_begin = 1'b0;
+        end
+    end
+    
+    //--------------------------------------------------------------------------
+    // Others
+    //--------------------------------------------------------------------------
+    always @ (*)
+    begin
+        int_wr_data_valid   = wvalid & wready;
+        int_wr_data         = wdata;
+        int_wr_data_byte_en = wstrb;
+        int_wr_data_last    = wlast & wready;
+        int_wr_data_id      = wid;
+    end
+    
+    //--------------------------------------------------------------------------
+    // Outputs
+    //--------------------------------------------------------------------------
+    // AXI write data channel output assignment
+    always @ (*)
+    begin
+        wready = itf_wr_data_ready & wr_data_fifo_ready;
+    end
+    
+    // Avalon ST data chanel output assignment
+    generate
+    begin
+        if (REGISTERED)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    itf_wr_data_valid   <= 0;
+                    itf_wr_data         <= 0;
+                    itf_wr_data_byte_en <= 0;
+                    itf_wr_data_begin   <= 0;
+                    itf_wr_data_last    <= 0;
+                    itf_wr_data_id      <= 0;
+                end
+                else
+                begin
+                    if (itf_wr_data_ready)
+                    begin
+                        itf_wr_data_valid   <= int_wr_data_valid;
+                        itf_wr_data         <= int_wr_data;
+                        itf_wr_data_byte_en <= int_wr_data_byte_en;
+                        itf_wr_data_begin   <= int_wr_data_begin;
+                        itf_wr_data_last    <= int_wr_data_last;
+                        itf_wr_data_id      <= int_wr_data_id;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                itf_wr_data_valid   = int_wr_data_valid;
+                itf_wr_data         = int_wr_data;
+                itf_wr_data_byte_en = int_wr_data_byte_en;
+                itf_wr_data_begin   = int_wr_data_begin;
+                itf_wr_data_last    = int_wr_data_last;
+                itf_wr_data_id      = int_wr_data_id;
+            end
+        end
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Write Data Channel
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Write Response Channel
+//
+//--------------------------------------------------------------------------------------------------------
+    assign wr_cmd_fifo_write             = wr_grant;              // write into FIFO after receiving write request
+    assign wr_cmd_fifo_write_data        = wr_id;
+    assign wr_cmd_fifo_read              = id_matched;            // pop from FIFO when ID from both FIFO is matching
+    assign wr_cmd_fifo_read_data_valid   = ~wr_cmd_fifo_empty;
+    
+    assign wr_data_fifo_write            = int_wr_data_last;      // write into FIFO after receiving last data
+    assign wr_data_fifo_write_data       = int_wr_data_id;
+    assign wr_data_fifo_read             = id_matched;            // pop from FIFO when ID from both FIFO is matching
+    assign wr_data_fifo_read_data_valid  = ~wr_data_fifo_empty;
+    
+    // FIFO instantiation to store write command information
+    scfifo # (
+        .add_ram_output_register    ("ON"                          ),
+        .intended_device_family     ("Stratix IV"                  ),
+        .lpm_numwords               (WR_CMD_FIFO_DEPTH             ),
+        .lpm_showahead              ("ON"                          ),
+        .lpm_type                   ("scfifo"                      ),
+        .lpm_width                  (WR_CMD_FIFO_DATA_WIDTH        ),
+        .lpm_widthu                 (WR_CMD_FIFO_ADDR_WIDTH        ),
+        .overflow_checking          ("OFF"                         ),
+        .underflow_checking         ("OFF"                         ),
+        .use_eab                    ("ON"                          ),
+        .almost_full_value          (WR_CMD_FIFO_DEPTH - 1         )
+    ) wr_cmd_fifo (
+        .aclr                       (~ctl_reset_n                  ),
+        .clock                      (ctl_clk                       ),
+        .data                       (wr_cmd_fifo_write_data        ),
+        .rdreq                      (wr_cmd_fifo_read              ),
+        .wrreq                      (wr_cmd_fifo_write             ),
+        .empty                      (wr_cmd_fifo_empty             ),
+        .full                       (                              ),
+        .q                          (wr_cmd_fifo_read_data         ),
+        .almost_empty               (                              ),
+        .almost_full                (wr_cmd_fifo_almost_full       ),
+        .sclr                       (zero                          ),
+        .usedw                      (                              )
+    );
+    
+    // FIFO instantiation to store write data information
+    scfifo # (
+        .add_ram_output_register    ("ON"                          ),
+        .intended_device_family     ("Stratix IV"                  ),
+        .lpm_numwords               (WR_DATA_FIFO_DEPTH            ),
+        .lpm_showahead              ("ON"                          ),
+        .lpm_type                   ("scfifo"                      ),
+        .lpm_width                  (WR_DATA_FIFO_DATA_WIDTH       ),
+        .lpm_widthu                 (WR_DATA_FIFO_ADDR_WIDTH       ),
+        .overflow_checking          ("OFF"                         ),
+        .underflow_checking         ("OFF"                         ),
+        .use_eab                    ("ON"                          ),
+        .almost_full_value          (WR_DATA_FIFO_DEPTH - 1        )
+    ) wr_data_fifo (
+        .aclr                       (~ctl_reset_n                  ),
+        .clock                      (ctl_clk                       ),
+        .data                       (wr_data_fifo_write_data       ),
+        .rdreq                      (wr_data_fifo_read             ),
+        .wrreq                      (wr_data_fifo_write            ),
+        .empty                      (wr_data_fifo_empty            ),
+        .full                       (                              ),
+        .q                          (wr_data_fifo_read_data        ),
+        .almost_empty               (                              ),
+        .almost_full                (wr_data_fifo_almost_full      ),
+        .sclr                       (zero                          ),
+        .usedw                      (                              )
+    );
+    
+    // FIFO full logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            wr_cmd_fifo_ready  <= 1'b0;
+            wr_data_fifo_ready <= 1'b0;
+        end
+        else
+        begin
+            // Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
+            wr_cmd_fifo_ready  <= ~wr_cmd_fifo_almost_full;
+            wr_data_fifo_ready <= ~wr_data_fifo_almost_full;
+        end
+    end
+    
+    // ID macthing logic
+    always @ (*)
+    begin
+        if (wr_cmd_fifo_read_data == wr_data_fifo_read_data && wr_cmd_fifo_read_data_valid && wr_data_fifo_read_data_valid)
+        begin
+            id_matched = 1'b1;
+        end
+        else
+        begin
+            id_matched = 1'b0;
+        end
+    end
+    
+    // Response logic
+    // logic will keep valid high till response channel is ready to accept the command
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_bid    <= 0;
+            int_bresp  <= 0;
+            int_bvalid <= 1'b0;
+        end
+        else
+        begin
+            if (id_matched)
+            begin
+                int_bid    <= wr_cmd_fifo_read_data;
+                int_bresp  <= 0;
+                int_bvalid <= 1'b1;
+            end
+            else if (bready)
+            begin
+                int_bid    <= 0;
+                int_bresp  <= 0;
+                int_bvalid <= 0;
+            end
+        end
+    end
+    
+    // AXI write response channel output assignment
+    always @ (*)
+    begin
+        bid    = int_bid;
+        bresp  = int_bresp;
+        bvalid = int_bvalid;
+    end
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Write Response Channel
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Read Data Channel
+//
+//--------------------------------------------------------------------------------------------------------
+    assign rd_cmd_fifo_write             = rd_grant;                // write into FIFO after receiving read request
+    assign rd_cmd_fifo_write_data        = rd_burstlen;
+    assign rd_cmd_fifo_read              = read_data_last;          // pop from FIFO after sending last read data
+    assign rd_cmd_fifo_read_data_valid   = ~rd_cmd_fifo_empty;
+    
+    // FIFO to store read command information
+    scfifo # (
+        .add_ram_output_register    ("ON"                          ),
+        .intended_device_family     ("Stratix IV"                  ),
+        .lpm_numwords               (RD_CMD_FIFO_DEPTH             ),
+        .lpm_showahead              ("ON"                          ),
+        .lpm_type                   ("scfifo"                      ),
+        .lpm_width                  (RD_CMD_FIFO_DATA_WIDTH        ),
+        .lpm_widthu                 (RD_CMD_FIFO_ADDR_WIDTH        ),
+        .overflow_checking          ("OFF"                         ),
+        .underflow_checking         ("OFF"                         ),
+        .use_eab                    ("ON"                          ),
+        .almost_full_value          (RD_CMD_FIFO_DEPTH - 1         )
+    ) rd_cmd_fifo (
+        .aclr                       (~ctl_reset_n                  ),
+        .clock                      (ctl_clk                       ),
+        .data                       (rd_cmd_fifo_write_data        ),
+        .rdreq                      (rd_cmd_fifo_read              ),
+        .wrreq                      (rd_cmd_fifo_write             ),
+        .empty                      (rd_cmd_fifo_empty             ),
+        .full                       (                              ),
+        .q                          (rd_cmd_fifo_read_data         ),
+        .almost_empty               (                              ),
+        .almost_full                (rd_cmd_fifo_almost_full       ),
+        .sclr                       (zero                          ),
+        .usedw                      (                              )
+    );
+    
+    // FIFO full logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rd_cmd_fifo_ready  <= 1'b0;
+        end
+        else
+        begin
+            // Set to '1' when either FIFO almost full, to prevent converter from accepting new commands/data
+            rd_cmd_fifo_ready  <= ~rd_cmd_fifo_almost_full;
+        end
+    end
+    
+    // Read data counter
+    // keep tracks of read data count, to be used in read data last logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            read_data_counter <= 1;
+        end
+        else
+        begin
+            if (int_rvalid && int_rd_data_ready && read_data_last) // reset counter value after reaching last burst
+            begin
+                read_data_counter <= 1;
+            end
+            else if (int_rvalid && int_rd_data_ready) // count up when there is a read data begin transfered
+            begin
+                read_data_counter <= read_data_counter + 1'b1;
+            end
+        end
+    end
+    
+    // Read data last logic
+    // indicate which read data is the last burst
+    always @ (*)
+    begin
+        if (int_rvalid && int_rd_data_ready && read_data_counter == rd_cmd_fifo_read_data) // set last to '1' when counter matches FIFO output
+        begin
+            read_data_last = 1'b1;
+        end
+        else
+        begin
+            read_data_last = 1'b0;
+        end
+    end
+    
+    // Others
+    always @ (*)
+    begin
+        int_rid           = itf_rd_data_id;
+        int_rdata         = itf_rd_data;
+        int_rresp         = {itf_rd_data_error, 1'b0}; // If there is an error, it will indicate SLVERR on AXI interface
+        int_rlast         = read_data_last;
+        int_rvalid        = itf_rd_data_valid;
+        
+        int_rd_data_ready = rready;
+    end
+    
+    // AXI read data channel output assignment
+    always @ (*)
+    begin
+        rid    = int_rid;
+        rdata  = int_rdata;
+        rresp  = int_rresp;
+        rlast  = int_rlast;
+        rvalid = int_rvalid;
+    end
+    
+    // Avalon ST read data channel output assignment
+    always @ (*)
+    begin
+        itf_rd_data_ready = int_rd_data_ready;
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Read Data Channel
+//
+//--------------------------------------------------------------------------------------------------------
+
+function integer log2;
+    input [31 : 0] value;
+    integer        i;
+    begin
+        log2 = 0;
+        for(i = 0;2 ** i < value;i = i + 1)
+        begin
+            log2 = i + 1;
+        end
+    end
+endfunction
+
+function integer log2_minus_one;
+    input [31 : 0] value;
+    integer        i;
+    begin
+        log2_minus_one = 1;
+        for(i = 0;2 ** i < value;i = i + 1)
+        begin
+            log2_minus_one = i + 1;
+        end
+    end
+endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
new file mode 100644
index 0000000..0e52266
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
@@ -0,0 +1,155 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* message_disable = "14320" *) module alt_mem_ddrx_buffer
+# (
+    // module parameter port list
+    parameter
+        ADDR_WIDTH      =   3,
+        DATA_WIDTH      =   8,
+        REGISTER_OUTPUT =   0
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // write interface
+    write_valid,
+    write_address,
+    write_data,
+
+    // read interface
+    read_valid,
+    read_address,
+    read_data
+);
+
+    // -----------------------------
+    // local parameter declaration
+    // -----------------------------
+
+    localparam  BUFFER_DEPTH            =  two_pow_N(ADDR_WIDTH);
+    localparam  BUFFER_REGISTER_OUTPUT  = (REGISTER_OUTPUT) ? "CLOCK0" : "UNREGISTERED";
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input                           ctl_clk;
+    input                           ctl_reset_n;
+    
+    // write interface
+    input                           write_valid;
+    input   [ADDR_WIDTH-1:0]        write_address;
+    input   [DATA_WIDTH-1:0]        write_data;
+
+    // read interface
+    input                           read_valid;
+    input   [ADDR_WIDTH-1:0]        read_address;
+    output  [DATA_WIDTH-1:0]        read_data;
+
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    wire                            ctl_clk;
+    wire                            ctl_reset_n;
+                                                   
+    // write interface                             
+    wire                            write_valid;
+    wire    [ADDR_WIDTH-1:0]        write_address;
+    wire    [DATA_WIDTH-1:0]        write_data;
+                                                   
+    // read interface                              
+    wire                            read_valid;
+    wire    [ADDR_WIDTH-1:0]        read_address;
+    wire    [DATA_WIDTH-1:0]        read_data;
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+	altsyncram	altsyncram_component 
+    (
+				.wren_a (write_valid),
+				.clock0 (ctl_clk),
+				.address_a (write_address),
+				.address_b (read_address),
+				.data_a (write_data),
+				.q_b (read_data),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({DATA_WIDTH{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0)
+    );
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.indata_aclr_a = "NONE",
+		altsyncram_component.intended_device_family = "Stratix",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = BUFFER_DEPTH,
+		altsyncram_component.numwords_b = BUFFER_DEPTH,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = BUFFER_REGISTER_OUTPUT,
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = ADDR_WIDTH,
+		altsyncram_component.widthad_b = ADDR_WIDTH,
+		altsyncram_component.width_a = DATA_WIDTH,
+		altsyncram_component.width_b = DATA_WIDTH,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.wrcontrol_aclr_a = "NONE";
+
+
+    // alt_ddrx_ram_2port 
+    // ram_inst
+    // (
+    //     .clock      (ctl_clk),
+    //     .wren       (write_valid),
+    //     .wraddress  (write_address),
+    //     .data       (write_data),
+    //     .rdaddress  (read_address),
+    //     .q          (read_data)
+    // );
+
+
+    function integer two_pow_N;
+        input integer value;
+    begin
+        two_pow_N = 2 << (value-1);
+    end
+    endfunction
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
new file mode 100644
index 0000000..539b7c9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
@@ -0,0 +1,263 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_buffer_manager
+# (
+    parameter
+        CFG_BUFFER_ADDR_WIDTH         =   6
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // write interface
+    writeif_ready,
+    writeif_valid,
+    writeif_address,
+    writeif_address_blocked,
+
+    // buffer write interface
+    buffwrite_valid,
+    buffwrite_address,
+
+    // read interface
+    readif_valid,
+    readif_address,
+
+    // buffer read interface
+    buffread_valid,
+    buffread_datavalid,
+    buffread_address
+
+);
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+
+    localparam CTL_BUFFER_DEPTH             =   two_pow_N(CFG_BUFFER_ADDR_WIDTH);
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input                                           ctl_clk;
+    input                                           ctl_reset_n;
+
+    // write interface
+    output                                          writeif_ready;
+    input                                           writeif_valid;
+    input  [CFG_BUFFER_ADDR_WIDTH-1:0]              writeif_address;
+    input                                           writeif_address_blocked;
+
+    // buffer write interface
+    output                                          buffwrite_valid;
+    output  [CFG_BUFFER_ADDR_WIDTH-1:0]             buffwrite_address;
+
+    // read data interface
+    input                                           readif_valid;
+    input   [CFG_BUFFER_ADDR_WIDTH-1:0]             readif_address;
+
+    // buffer read interface
+    output                                          buffread_valid;
+    output                                          buffread_datavalid;
+    output  [CFG_BUFFER_ADDR_WIDTH-1:0]             buffread_address;
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    wire                                            ctl_clk;
+    wire                                            ctl_reset_n;
+                                                                             
+    // write interface                                                       
+    reg                                             writeif_ready;
+    wire                                            writeif_valid;
+    wire     [CFG_BUFFER_ADDR_WIDTH-1:0]            writeif_address;
+                                                                             
+    wire                                            writeif_address_blocked;
+                                                                             
+    // buffer write interface                                                
+    wire                                            buffwrite_valid;
+    wire     [CFG_BUFFER_ADDR_WIDTH-1:0]            buffwrite_address;
+                                                                             
+    // read data interface                                                   
+    wire                                            readif_valid;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]             readif_address;
+                                                                             
+    // buffer read interface                                                 
+    wire                                            buffread_valid;
+    reg                                             buffread_datavalid;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]             buffread_address;
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    wire                                            writeif_accepted;
+    reg     [CTL_BUFFER_DEPTH-1:0]                  mux_writeif_ready;
+    reg     [CTL_BUFFER_DEPTH-1:0]                  buffer_valid_array;    
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]             buffer_valid_counter;
+                                                                                       
+    reg                                             err_buffer_valid_counter_overflow;
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    assign  writeif_accepted    = writeif_ready & writeif_valid;
+
+    assign  buffwrite_address   = writeif_address;
+    assign  buffwrite_valid     = writeif_accepted;
+
+    assign  buffread_address    = readif_address;
+    assign  buffread_valid      = readif_valid;
+
+    always @ (*) 
+    begin
+
+        if (writeif_address_blocked)
+        begin
+            // can't write ahead of lowest address currently tracked by dataid array
+            writeif_ready = 1'b0;
+        end
+        else 
+        begin
+            // buffer is full when every location has been written
+            writeif_ready = ~&buffer_valid_counter;
+        end
+
+    end
+
+
+    // generate buffread_datavalid. 
+    // data is valid one cycle after adddress is presented to the buffer
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            buffread_datavalid <= 0;
+        end
+        else
+        begin
+            buffread_datavalid <= buffread_valid;
+        end
+    end
+
+
+    // genvar i;
+    // generate
+    //     for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1) 
+    //     begin : gen_mux_buffer_valid_array_signals
+
+    //         wire    [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
+
+    //         always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    //         begin
+    //             if (~ctl_reset_n)
+    //             begin
+    //                 //reset state ...
+    //                 buffer_valid_array [i] <= 0;
+    //             end
+    //             else
+    //             begin
+    //                 //active state ...
+
+    //                 // write & read to same location won't happen on same time
+
+    //                 // write
+    //                 if ( (writeif_address == gen_buffer_address) & writeif_accepted)
+    //                 begin
+    //                     buffer_valid_array[i] <= 1;
+    //                 end
+
+    //                 // read
+    //                 if ( (readif_address== gen_buffer_address) & readif_valid)
+    //                 begin
+    //                     buffer_valid_array[i] <= 0;
+    //                 end
+
+    //             end
+    //         end
+
+    //         always @ (*) 
+    //         begin
+    //             // mano - fmax !    
+    //             if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
+    //             begin
+    //                 mux_writeif_ready[i]  = 0;
+    //             end
+    //             else
+    //             begin
+    //                 mux_writeif_ready[i]  = 1;
+    //             end
+    //         end
+
+    //     end
+    // endgenerate
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            buffer_valid_counter <= 0;
+            err_buffer_valid_counter_overflow <= 0;
+        end
+        else
+        begin
+
+            if (writeif_accepted & readif_valid)
+            begin
+                // write & read at same time
+                buffer_valid_counter <= buffer_valid_counter;
+            end
+            else if (writeif_accepted)
+            begin
+                // write only
+                {err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
+            end
+            else if (readif_valid)
+            begin
+                // read only
+                buffer_valid_counter <= buffer_valid_counter - 1;
+            end
+            else
+            begin
+                buffer_valid_counter <= buffer_valid_counter;
+            end
+
+
+        end
+    end
+
+
+
+    function integer two_pow_N;
+        input integer value;
+    begin
+        two_pow_N = 2 << (value-1);
+    end
+    endfunction
+
+
+
+endmodule
+
+//
+// assert
+//
+// - write & read to same location happen on same time
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
new file mode 100644
index 0000000..6dcf78e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
@@ -0,0 +1,1582 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_burst_gen #
+    ( parameter
+        CFG_DWIDTH_RATIO                        =   4,
+        CFG_CTL_ARBITER_TYPE                    =   "ROWCOL",
+        CFG_REG_GRANT                           =   0,
+        CFG_MEM_IF_CHIP                         =   1,
+        CFG_MEM_IF_CS_WIDTH                     =   1,
+        CFG_MEM_IF_BA_WIDTH                     =   3,
+        CFG_MEM_IF_ROW_WIDTH                    =   13,
+        CFG_MEM_IF_COL_WIDTH                    =   10,
+        CFG_LOCAL_ID_WIDTH                      =   10,
+        CFG_DATA_ID_WIDTH                       =   10,
+        CFG_INT_SIZE_WIDTH                      =   4,
+        CFG_AFI_INTF_PHASE_NUM                  =   2,
+        CFG_PORT_WIDTH_TYPE                     =   3,
+        CFG_PORT_WIDTH_BURST_LENGTH             =   5,
+        CFG_PORT_WIDTH_TCCD                     =   4,
+        CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT   =   1,
+        CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE   =   1,
+        CFG_ENABLE_BURST_GEN_OUTPUT_REG         =   0
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // MMR Interface
+        cfg_type,
+        cfg_burst_length,
+        cfg_tccd,
+        cfg_enable_burst_interrupt,
+        cfg_enable_burst_terminate,
+        
+        // Arbiter Interface
+        arb_do_write,
+        arb_do_read,
+        arb_do_burst_chop,
+        arb_do_burst_terminate,
+        arb_do_auto_precharge,
+        arb_do_rmw_correct,
+        arb_do_rmw_partial,
+        arb_do_activate,
+        arb_do_precharge,
+        arb_do_precharge_all,
+        arb_do_refresh,
+        arb_do_self_refresh,
+        arb_do_power_down,
+        arb_do_deep_pdown,
+        arb_do_zq_cal,
+        arb_do_lmr,
+        arb_to_chipsel,
+        arb_to_chip,
+        arb_to_bank,
+        arb_to_row,
+        arb_to_col,
+        arb_localid,
+        arb_dataid,
+        arb_size,
+        
+        // AFI Interface
+        bg_do_write_combi,
+        bg_do_read_combi,
+        bg_do_burst_chop_combi,
+        bg_do_burst_terminate_combi,
+        bg_do_activate_combi,
+        bg_do_precharge_combi,
+        bg_to_chip_combi,
+        bg_effective_size_combi,
+        bg_interrupt_ready_combi,
+
+        bg_do_write,
+        bg_do_read,
+        bg_do_burst_chop,
+        bg_do_burst_terminate,
+        bg_do_auto_precharge,
+        bg_do_rmw_correct,
+        bg_do_rmw_partial,
+        bg_do_activate,
+        bg_do_precharge,
+        bg_do_precharge_all,
+        bg_do_refresh,
+        bg_do_self_refresh,
+        bg_do_power_down,
+        bg_do_deep_pdown,
+        bg_do_zq_cal,
+        bg_do_lmr,
+        bg_to_chipsel,
+        bg_to_chip,
+        bg_to_bank,
+        bg_to_row,
+        bg_to_col,
+        bg_doing_write,
+        bg_doing_read,
+        bg_rdwr_data_valid,
+        bg_interrupt_ready,
+        bg_localid,
+        bg_dataid,
+        bg_size,
+        bg_effective_size
+    );
+
+localparam AFI_INTF_LOW_PHASE  = 0;
+localparam AFI_INTF_HIGH_PHASE = 1;
+
+input                                                            ctl_clk;
+input                                                            ctl_reset_n;
+
+// MMR Interface
+input  [CFG_PORT_WIDTH_TYPE                             - 1 : 0] cfg_type;
+input  [CFG_PORT_WIDTH_BURST_LENGTH                     - 1 : 0] cfg_burst_length;
+input  [CFG_PORT_WIDTH_TCCD                             - 1 : 0] cfg_tccd;
+input  [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT           - 1 : 0] cfg_enable_burst_interrupt;
+input  [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE           - 1 : 0] cfg_enable_burst_terminate;
+
+// Arbiter Interface
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_write;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_read;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_chop;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_terminate;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_auto_precharge;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_correct;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_partial;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_activate;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_precharge;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_precharge_all;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_refresh;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_self_refresh;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_power_down;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_deep_pdown;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_zq_cal;
+input  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_lmr;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] arb_to_chipsel;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_to_chip;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] arb_to_bank;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
+input  [CFG_LOCAL_ID_WIDTH                              - 1 : 0] arb_localid;
+input  [CFG_DATA_ID_WIDTH                               - 1 : 0] arb_dataid;
+input  [CFG_INT_SIZE_WIDTH                              - 1 : 0] arb_size;
+
+// AFI Interface
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write_combi;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read_combi;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop_combi;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate_combi;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate_combi;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge_combi;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip_combi;
+output [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size_combi;
+output                                                           bg_interrupt_ready_combi;
+
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_auto_precharge;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_correct;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_partial;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_precharge_all;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_refresh;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_self_refresh;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_power_down;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_deep_pdown;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_zq_cal;
+output [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_lmr;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
+output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
+output                                                           bg_doing_write;
+output                                                           bg_doing_read;
+output                                                           bg_rdwr_data_valid;
+output                                                           bg_interrupt_ready;
+output [CFG_LOCAL_ID_WIDTH                              - 1 : 0] bg_localid;
+output [CFG_DATA_ID_WIDTH                               - 1 : 0] bg_dataid;
+output [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_size;
+output [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // AFI Interface
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_auto_precharge;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_partial;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_precharge_all;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_refresh;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_self_refresh;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_power_down;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_deep_pdown;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_zq_cal;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_lmr;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
+    reg                                                            bg_doing_write;
+    reg                                                            bg_doing_read;
+    reg                                                            bg_rdwr_data_valid;
+    reg                                                            bg_interrupt_ready;
+    reg  [CFG_LOCAL_ID_WIDTH                              - 1 : 0] bg_localid;
+    reg  [CFG_DATA_ID_WIDTH                               - 1 : 0] bg_dataid;
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_size;
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size;
+    
+    // Burst generation logic
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] int_size;
+    reg  [CFG_DATA_ID_WIDTH                               - 1 : 0] int_dataid;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
+    reg  [2                                                   : 0] int_col_address;
+    reg  [2                                                   : 0] int_address_left;
+    reg                                                            int_do_row_req;
+    reg                                                            int_do_col_req;
+    reg                                                            int_do_sideband_req;
+    reg                                                            int_do_auto_precharge;
+    reg                                                            int_do_rd_req;
+    reg                                                            int_do_wr_req;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] int_do_burst_chop;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] int_do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] int_do_rmw_partial;
+    
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] size;
+    reg  [CFG_DATA_ID_WIDTH                               - 1 : 0] dataid;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
+    reg  [2                                                   : 0] col_address;
+    reg  [2                                                   : 0] address_left;
+    reg                                                            do_row_req;
+    reg                                                            do_col_req;
+    reg                                                            do_sideband_req;
+    reg                                                            do_auto_precharge;
+    reg                                                            do_rd_req;
+    reg                                                            do_wr_req;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] do_burst_chop;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] do_rmw_partial;
+    
+    reg                                                            doing_auto_precharge;
+    
+    reg  [3 : 0] max_local_burst_size;
+    reg  [3 : 0] max_local_burst_size_divide_2;
+    reg  [3 : 0] max_local_burst_size_minus_2;
+    reg  [3 : 0] max_local_burst_size_divide_2_and_minus_2;
+    
+    reg  [3 : 0] burst_left;
+    reg          current_valid;
+    reg          delayed_valid;
+    reg          combined_valid;
+    
+    reg  [3 : 0] max_burst_left;
+    reg          delayed_doing;
+    reg          last_is_write;
+    reg          last_is_read;
+    
+    // Burst interrupt logic
+    reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
+    reg                               int_allow_interrupt;
+    reg                               int_interrupt_enable_ready;
+    reg                               int_interrupt_disable_ready;
+    reg                               int_interrupt_gate;
+    
+    // Burst terminate logic
+    reg                              int_allow_terminate;
+    reg                              int_do_burst_terminate;
+    reg                              int_do_burst_terminate_r;
+    reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
+    reg                              int_do_req;
+    reg                              doing_burst_terminate;
+    reg                              terminate_doing;
+    
+    // RMW Info
+    reg  [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
+    reg  [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
+    reg  [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
+    
+    // Data ID
+    reg  [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
+    reg  [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
+    
+    // Chip address
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] rdwr_to_chipsel;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] rdwr_to_chip;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] modified_to_chipsel;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] modified_to_chip;
+    
+    // Column address
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
+    
+    // Common
+    wire zero = 1'b0;
+    
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write_combi;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read_combi;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop_combi;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate_combi;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate_combi;
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge_combi;
+    reg  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip_combi;
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size_combi;
+    reg                                                            bg_interrupt_ready_combi;
+    
+    reg  [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] do_burst_terminate;
+    reg                                                            doing_write;
+    reg                                                            doing_read;
+    reg                                                            rdwr_data_valid;
+    reg                                                            interrupt_ready;
+    reg  [CFG_INT_SIZE_WIDTH                              - 1 : 0] effective_size;
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Outputs
+//
+//--------------------------------------------------------------------------------------------------------
+
+    // Do signals
+    generate
+        if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (! ctl_reset_n)
+                begin
+                    bg_do_write           <= 0;
+                    bg_do_read            <= 0;
+                    bg_do_auto_precharge  <= 0;
+                    bg_do_rmw_correct     <= 0;
+                    bg_do_rmw_partial     <= 0;
+                    bg_do_activate        <= 0;
+                    bg_do_precharge       <= 0;
+                    bg_do_precharge_all   <= 0;
+                    bg_do_refresh         <= 0;
+                    bg_do_self_refresh    <= 0;
+                    bg_do_power_down      <= 0;
+                    bg_do_deep_pdown      <= 0;
+                    bg_do_zq_cal          <= 0;
+                    bg_do_lmr             <= 0;
+                    bg_to_chip            <= 0;
+                    bg_to_chipsel         <= 0;
+                    bg_to_bank            <= 0;
+                    bg_to_row             <= 0;
+                    bg_localid            <= 0;
+                    bg_size               <= 0;
+                    bg_to_col             <= 0;
+                    bg_dataid             <= 0;
+                    bg_do_burst_chop      <= 0;
+                    bg_do_burst_terminate <= 0;
+                    bg_doing_write        <= 0;
+                    bg_doing_read         <= 0;
+                    bg_rdwr_data_valid    <= 0;
+                    bg_interrupt_ready    <= 0;
+                    bg_effective_size     <= 0;
+                end
+                else
+                begin
+                    bg_do_write           <= arb_do_write;
+                    bg_do_read            <= arb_do_read;
+                    bg_do_auto_precharge  <= arb_do_auto_precharge;
+                    bg_do_rmw_correct     <= combined_do_rmw_correct;
+                    bg_do_rmw_partial     <= combined_do_rmw_partial;
+                    bg_do_activate        <= arb_do_activate;
+                    bg_do_precharge       <= arb_do_precharge;
+                    bg_do_precharge_all   <= arb_do_precharge_all;
+                    bg_do_refresh         <= arb_do_refresh;
+                    bg_do_self_refresh    <= arb_do_self_refresh;
+                    bg_do_power_down      <= arb_do_power_down;
+                    bg_do_deep_pdown      <= arb_do_deep_pdown;
+                    bg_do_zq_cal          <= arb_do_zq_cal;
+                    bg_do_lmr             <= arb_do_lmr;
+                    bg_to_chip            <= modified_to_chip;
+                    bg_to_chipsel         <= modified_to_chipsel;
+                    bg_to_bank            <= arb_to_bank;
+                    bg_to_row             <= arb_to_row;
+                    bg_localid            <= arb_localid;
+                    bg_size               <= arb_size;
+                    bg_to_col             <= modified_to_col;
+                    bg_dataid             <= combined_dataid;
+                    bg_do_burst_chop      <= do_burst_chop;
+                    bg_do_burst_terminate <= do_burst_terminate;
+                    bg_doing_write        <= doing_write;
+                    bg_doing_read         <= doing_read;
+                    bg_rdwr_data_valid    <= rdwr_data_valid;
+                    bg_interrupt_ready    <= interrupt_ready;
+                    bg_effective_size     <= effective_size;
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                bg_do_write           = arb_do_write;
+                bg_do_read            = arb_do_read;
+                bg_do_auto_precharge  = arb_do_auto_precharge;
+                bg_do_activate        = arb_do_activate;
+                bg_do_precharge       = arb_do_precharge;
+                bg_do_precharge_all   = arb_do_precharge_all;
+                bg_do_refresh         = arb_do_refresh;
+                bg_do_self_refresh    = arb_do_self_refresh;
+                bg_do_power_down      = arb_do_power_down;
+                bg_do_deep_pdown      = arb_do_deep_pdown;
+                bg_do_zq_cal          = arb_do_zq_cal;
+                bg_do_lmr             = arb_do_lmr;
+                bg_to_chip            = modified_to_chip;
+                bg_to_chipsel         = modified_to_chipsel;
+                bg_to_bank            = arb_to_bank;
+                bg_to_row             = arb_to_row;
+                bg_localid            = arb_localid;
+                bg_size               = arb_size;
+                bg_do_burst_chop      = do_burst_chop;
+                bg_do_burst_terminate = do_burst_terminate;
+                bg_doing_write        = doing_write;
+                bg_doing_read         = doing_read;
+                bg_rdwr_data_valid    = rdwr_data_valid;
+                bg_interrupt_ready    = interrupt_ready;
+                bg_effective_size     = effective_size;
+            end
+            
+            // To column
+            always @ (*)
+            begin
+                bg_to_col = modified_to_col;
+            end
+            
+            // RMW info
+            always @ (*)
+            begin
+                bg_do_rmw_correct = combined_do_rmw_correct;
+                bg_do_rmw_partial = combined_do_rmw_partial;
+            end
+            
+            // Data ID
+            always @ (*)
+            begin
+                bg_dataid = combined_dataid;
+            end
+        end
+    endgenerate
+    
+    // Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0 
+    // following signals (inputs to rank_timer) need to be combi
+    always @ (*)
+    begin
+        bg_do_write_combi           = arb_do_write;
+        bg_do_read_combi            = arb_do_read;
+        bg_do_burst_chop_combi      = do_burst_chop;
+        bg_do_burst_terminate_combi = do_burst_terminate;
+        bg_do_activate_combi        = arb_do_activate;
+        bg_do_precharge_combi       = arb_do_precharge;
+        bg_to_chip_combi            = modified_to_chip;
+        bg_effective_size_combi     = effective_size;
+        bg_interrupt_ready_combi    = interrupt_ready;
+    end
+    
+    generate
+        genvar i;
+        for (i = 0;i < CFG_AFI_INTF_PHASE_NUM;i = i + 1)
+        begin : afi_phase_loop
+            // Registered chip/chipsel address for read/write request
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    rdwr_to_chip    [(i + 1) * CFG_MEM_IF_CHIP     - 1 : i * CFG_MEM_IF_CHIP    ] <= 0;
+                    rdwr_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH] <= 0;
+                end
+                else
+                begin
+                    if (arb_do_read[i] || arb_do_write[i])
+                    begin
+                        rdwr_to_chip    [(i + 1) * CFG_MEM_IF_CHIP     - 1 : i * CFG_MEM_IF_CHIP    ] <= arb_to_chip    [(i + 1) * CFG_MEM_IF_CHIP     - 1 : i * CFG_MEM_IF_CHIP    ];
+                        rdwr_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH] <= arb_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH];
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    always @ (*)
+    begin
+        if (do_burst_terminate)
+        begin
+            if (CFG_DWIDTH_RATIO != 2)
+            begin
+                modified_to_chip = rdwr_to_chip | arb_to_chip;
+            end
+            else
+            begin
+                modified_to_chip = rdwr_to_chip;
+            end
+            
+            modified_to_chipsel = rdwr_to_chipsel;
+        end
+        else
+        begin
+            modified_to_chip    = arb_to_chip;
+            modified_to_chipsel = arb_to_chipsel;
+        end
+    end
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Outputs
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Burst Generation Logic
+//  
+//  Doing read/write signal will indicate the "FULL" burst duration of a request
+//  Data Valid signal will indicate "VALID" burst duration of a request
+//  
+//  Example: Without address shifting (maximum local burst size of 4)
+//  
+//  Clock                          ____/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
+//  
+//  Input Request                  ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
+//  Input Column Address [2 : 0]   ----X  0  X-----------------X  0  X-----------------X  0  X-----------------X  0  X-----------------------
+//  Input Size                     ----X  1  X-----------------X  2  X-----------------X  3  X-----------------X  4  X-----------------------
+//  
+//  Output Column Address [2 : 0]  ----X  0  X-----------------X  0  X-----------------X  0  X-----------------X  0  X-----------------------
+//  Output Doing Signal            ____/  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  \_____
+//  Output Valid Signal            ____/  1  \_________________/  1  X  2  \___________/  1  X  2  X  3  \_____/  1  X  2  X  3  X  4  \_____
+//  
+//  Example: With address shifting (maximum local burst size of 4)
+//  
+//  Clock                          ____/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
+//  
+//  Input Request                  ----X W R X-----------------X W R X-----------------X W R X-----------------------
+//  Input Column Address [2 : 0]   ----X  1  X-----------------X  2  X-----------------X  2  X-----------------------
+//  Input Size                     ----X  1  X-----------------X  1  X-----------------X  2  X-----------------------
+//  
+//  Output Column Address [2 : 0]  ----X  0  X-----------------X  0  X-----------------X  0  X-----------------------
+//  Output Doing Signal            ____/  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  \_____
+//  Output Valid Signal            __________/  1  \_______________________/  1  \_________________/  1  X  2  \_____
+//                                     <----->                 <----------->           <----------->
+//                                     Offset                     Offset                  Offset
+//
+//  Example: Burst chop for DDR3 only (maximum local burst size of 4)
+//  
+//  Clock                          ____/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
+//  
+//  Input Request                  ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
+//  Input Column Address [2 : 0]   ----X  0  X-----------------X  1  X-----------------X  2  X-----------------X  3  X-----------------------
+//  Input Size                     ----X  1  X-----------------X  1  X-----------------X  1  X-----------------X  1  X-----------------------
+//  
+//  Output Column Address [2 : 0]  ----X  0  X-----------------X  0  X-----------------X  2  X-----------------X  2  X-----------------------
+//  Output Burst Chop Signal       ____/  1  \_________________/  1  \_________________/  1  \_________________/  1  \_______________________
+//  Output Doing Signal            ____/  1  X  2  \___________/  1  X  2  \___________/  1  X  2  \___________/  1  X  2  \_________________
+//  Output Valid Signal            ____/  1  \_______________________/  1  \___________/  1  \_______________________/  1  \_________________
+//                                                             <----->                                         <----->
+//                                                             Offset                                          Offset
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Maximum local burst size
+    //----------------------------------------------------------------------------------------------------
+    // Calculate maximum local burst size
+    // based on burst length and controller rate
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            max_local_burst_size <= 0;
+        end
+        else
+        begin
+            max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            max_local_burst_size_divide_2             <= 0;
+            max_local_burst_size_minus_2              <= 0;
+            max_local_burst_size_divide_2_and_minus_2 <= 0;
+        end
+        else
+        begin
+            max_local_burst_size_divide_2             <= max_local_burst_size / 2;
+            max_local_burst_size_minus_2              <= max_local_burst_size - 2'd2;
+            max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Address shifting
+    //----------------------------------------------------------------------------------------------------
+    // Column address
+    // we only require address [2 - 0] because the maximum supported
+    // local burst count is 8 which is BL of 16 in full rate
+    // we only take low phase of arb_to_col address because high and low phase is identical
+    always @ (*)
+    begin
+        int_col_address = 0;
+        
+        if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop)     // DDR3 and burst chop, we don't want address shifting during burst chop
+        begin
+            if (max_local_burst_size [2])               // max local burst of 4
+                int_col_address [0    ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
+            else
+                // max local burst of 1, 2 - address shifting in burst chop is not possible
+                // max local burst of 8    - not supported in DDR3, there is no BL 16 support in DDR3
+                int_col_address = 0;
+        end
+        else if (max_local_burst_size [0])              // max local burst of 1
+            int_col_address         = 0;
+        else if (max_local_burst_size [1])              // max local burst of 2
+            int_col_address [0    ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
+        else if (max_local_burst_size [2])              // max local burst of 4
+            int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
+        else if (max_local_burst_size [3])              // max local burst of 8
+            int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
+    end
+    
+    always @ (*)
+    begin
+        col_address = int_col_address;
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Command Info
+    //----------------------------------------------------------------------------------------------------
+    // To col address
+    always @ (*)
+    begin
+        int_to_col = arb_to_col;
+    end
+    
+    // Row request
+    always @ (*)
+    begin
+        int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
+    end
+    
+    // Column request
+    always @ (*)
+    begin
+        int_do_col_req = (|arb_do_write) | (|arb_do_read);
+    end
+    
+    // Sideband request
+    always @ (*)
+    begin
+        int_do_sideband_req = (|arb_do_precharge_all) | (|arb_do_refresh) | (|arb_do_self_refresh) | (|arb_do_power_down) | (|arb_do_deep_pdown) | (|arb_do_zq_cal) | (|arb_do_lmr);
+    end
+    
+    // Read and write request
+    always @ (*)
+    begin
+        int_do_rd_req = |arb_do_read;
+        int_do_wr_req = |arb_do_write;
+    end
+    
+    // Auto precharge
+    always @ (*)
+    begin
+        int_do_auto_precharge = |arb_do_auto_precharge;
+    end
+    
+    // Burst chop
+    always @ (*)
+    begin
+        int_do_burst_chop = arb_do_burst_chop;
+    end
+    
+    // RMW info
+    always @ (*)
+    begin
+        int_do_rmw_correct = arb_do_rmw_correct;
+        int_do_rmw_partial = arb_do_rmw_partial;
+    end
+    
+    // Other Info: size, dataid
+    always @ (*)
+    begin
+        int_size   = arb_size;
+        int_dataid = arb_dataid;
+    end
+    
+    always @ (*)
+    begin
+        size                = int_size;
+        dataid              = int_dataid;
+        to_col              = int_to_col;
+        do_row_req          = int_do_row_req;
+        do_col_req          = int_do_col_req;
+        do_sideband_req     = int_do_sideband_req;
+        do_rd_req           = int_do_rd_req;
+        do_wr_req           = int_do_wr_req;
+        do_auto_precharge   = int_do_auto_precharge;
+        do_burst_chop       = int_do_burst_chop;
+        do_rmw_correct      = int_do_rmw_correct;
+        do_rmw_partial      = int_do_rmw_partial;
+    end
+    
+    // Keep track of auto-precharge signal
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            doing_auto_precharge <= 1'b0;
+        end
+        else
+        begin
+            if (do_col_req && do_auto_precharge)
+            begin
+                doing_auto_precharge <= 1'b1;
+            end
+            else if (do_col_req && !do_auto_precharge)
+            begin
+                doing_auto_precharge <= 1'b0;
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Address Count
+    //----------------------------------------------------------------------------------------------------
+    // Address counting logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            address_left <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                if (col_address > 1'b1)
+                    address_left <= col_address - 2'd2;
+                else
+                    address_left <= 0;
+            end
+            else if (address_left != 0)
+                address_left <= address_left - 1'b1;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Valid Signal
+    //----------------------------------------------------------------------------------------------------
+    // Burst counting logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            burst_left <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                if (col_address == 0) // no shifting required
+                begin
+                    if (size > 1'b1)
+                        burst_left <= size - 2'd2;
+                    else
+                        burst_left <= 0;
+                end
+                else if (col_address == 1'b1) // require shifting
+                begin
+                    burst_left <= size - 1'b1;
+                end
+                else // require shifting
+                begin
+                    burst_left <= size;
+                end
+            end
+            else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
+                burst_left <= burst_left - 1'b1;
+        end
+    end
+    
+    // Current valid signal
+    // when there is a column request and column address is "0"
+    // valid signal must be asserted along with column request
+    always @ (*)
+    begin
+        if (do_col_req && col_address == 0)
+            current_valid = 1'b1;
+        else
+            current_valid = 1'b0;
+    end
+    
+    // Delayed valid signal
+    // when there is a column request with size larger than "1"
+    // valid signal will be asserted according to the request size
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            delayed_valid <= 0;
+        end
+        else
+        begin
+            if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
+                delayed_valid <= 1'b1;
+            else if (address_left == 0 && burst_left > 0)
+                delayed_valid <= 1'b1;
+            else
+                delayed_valid <= 1'b0;
+        end
+    end
+    
+    // Combined valid signal
+    always @ (*)
+    begin
+        combined_valid = current_valid | delayed_valid;
+    end
+    
+    // Read write valid signal
+    always @ (*)
+    begin
+        rdwr_data_valid = combined_valid;
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Doing Signal
+    //----------------------------------------------------------------------------------------------------
+    // Maximum burst counting logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            max_burst_left <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                if (do_burst_chop[0]) // Arbiter will make sure to broadcast burst chop info to both bits (0 & 1)
+                begin
+                    if (max_local_burst_size_divide_2 <= 2)
+                        max_burst_left <= 0;
+                    else
+                        max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
+                end
+                else
+                begin
+                    if (max_local_burst_size <= 2)
+                        max_burst_left <= 0;
+                    else
+                        max_burst_left <= max_local_burst_size_minus_2;
+                end
+            end
+            else if (max_burst_left != 0)
+                max_burst_left <= max_burst_left - 1'b1;
+        end
+    end
+    
+    // Delayed doing signal
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            delayed_doing <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                if (max_local_burst_size <= 1'b1)   //do not generate delayed_doing if max burst count is 1
+                    delayed_doing <= 1'b0;
+                else if (do_burst_chop && max_local_burst_size <= 2'd2)
+                    delayed_doing <= 1'b0;
+                else
+                    delayed_doing <= 1'b1;
+            end
+            else if (max_burst_left > 0)
+                delayed_doing <= 1'b1;
+            else
+                delayed_doing <= 1'b0;
+        end
+    end
+    
+    // Keep track of last commands
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            last_is_write <= 1'b0;
+            last_is_read  <= 1'b0;
+        end
+        else
+        begin
+            if (do_wr_req)
+            begin
+                last_is_write <= 1'b1;
+                last_is_read  <= 1'b0;
+            end
+            else if (do_rd_req)
+            begin
+                last_is_write <= 1'b0;
+                last_is_read  <= 1'b1;
+            end
+        end
+    end
+    
+    // Doing write signal
+    always @ (*)
+    begin
+        if (do_rd_req)
+            doing_write = 1'b0;
+        else if (do_wr_req)
+            doing_write = ~terminate_doing;
+        else if (last_is_write)
+            doing_write = delayed_doing & ~terminate_doing;
+        else
+            doing_write = 1'b0;
+    end
+    
+    // Doing read signal
+    always @ (*)
+    begin
+        if (do_wr_req)
+            doing_read = 1'b0;
+        else if (do_rd_req)
+            doing_read = ~terminate_doing;
+        else if (last_is_read)
+            doing_read = delayed_doing & ~terminate_doing;
+        else
+            doing_read = 1'b0;
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Burst Generation Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] RMW Info
+//
+//--------------------------------------------------------------------------------------------------------
+    // Registered arb_do_rmw_* signal when there is a coumn request
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            delayed_do_rmw_correct <= 0;
+            delayed_do_rmw_partial <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                delayed_do_rmw_correct <= do_rmw_correct;
+                delayed_do_rmw_partial <= do_rmw_partial;
+            end
+        end
+    end
+    
+    // Prolong RMW information until doing signal is deasserted
+    always @ (*)
+    begin
+        if (do_col_req)
+        begin
+            combined_do_rmw_correct = do_rmw_correct;
+            combined_do_rmw_partial = do_rmw_partial;
+        end
+        else if (delayed_doing & ~terminate_doing)
+        begin
+            combined_do_rmw_correct = delayed_do_rmw_correct;
+            combined_do_rmw_partial = delayed_do_rmw_partial;
+        end
+        else
+        begin
+            combined_do_rmw_correct = 0;
+            combined_do_rmw_partial = 0;
+        end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] RMW Info
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Data ID
+//
+//--------------------------------------------------------------------------------------------------------
+    // Register data ID when there is a column request
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            delayed_dataid <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+                delayed_dataid <= dataid;
+        end
+    end
+    
+    // Prolong data ID information until doing signal is deasserted
+    always @ (*)
+    begin
+        if (do_col_req)
+            combined_dataid = dataid;
+        else if (delayed_doing)
+            combined_dataid = delayed_dataid;
+        else
+            combined_dataid = 0;
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Data ID
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Column Address
+//
+//--------------------------------------------------------------------------------------------------------
+    // Change column address bit [2 : 0]
+    // see waveform examples in burst generation logic portion
+    always @ (*)
+    begin
+         modified_to_col = to_col;
+         
+         // During burst chop in DDR3 only, retain original column address
+         // maximum local burst in DDR3 is 4 which is BL8 in full rate
+         if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
+         begin
+             if (max_local_burst_size [1])                   // max local burst of 2
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 0 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+             else if (max_local_burst_size [2])              // max local burst of 4
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 1 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+         end
+         else
+         begin
+             if (max_local_burst_size [0])                   // max local burst of 1
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 0 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+             else if (max_local_burst_size [1])              // max local burst of 2
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 1 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+             else if (max_local_burst_size [2])              // max local burst of 4
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 2 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+             else if (max_local_burst_size [3])              // max local burst of 8
+             begin
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4)                        + 3 : 0                   ] = 0;
+                 modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
+             end
+         end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Column Address
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Burst Interrupt
+//  
+//  DDR, DDR2, LPDDR and LPDDR2 specific
+//  
+//  This logic re-use most of the existing logic in burst generation section (valid signal)
+//  This signal will be used in rank timer block to gate can_read and can_write signals
+//  
+//  Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
+//  
+//  Clock                          ____/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
+//  
+//  Do Signal                      ____/  1  \_________________/  1  \_________________/  1  \_________________/  1  \_______________________
+//  Doing Signal                   ____/  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  X  1  X  2  X  3  X  4  \_____
+//  Valid Signal                   ____/  1  \_______________________/  1  \_______________________/  1  \_______________________/  1  \_____
+//  
+//  Interrupt Ready (tCCD = 1)     /              HIGH               \_____/      HIGH       \___________/    HIGH   \_________________/     
+//  Interrupt Ready (tCCD = 2)     /   HIGH  \_____/      HIGH       \_____/      HIGH       \_________________/     \_________________/     
+//
+//--------------------------------------------------------------------------------------------------------
+    // n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
+    // if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
+    // if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
+    // if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            n_prefetch <= 0;
+        end
+        else
+        begin
+            n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
+        end
+    end
+    
+    // For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
+    // for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_allow_interrupt <= 1'b1;
+        end
+        else
+        begin
+            if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
+                int_allow_interrupt <= 1'b1;
+            else
+            begin
+                if (n_prefetch <= 1) // allow interrupt at any clock cycle
+                begin
+                    if (do_col_req && (((col_address == 0 && size > 1) || col_address != 0) || do_auto_precharge) && (CFG_REG_GRANT && max_local_burst_size > 2)) // only disable interrupt for native size larger than 2 (larger than BL4 in FR), only in CFG grant mode since we only can issue WRRD-NOP-WRRD in this mode
+                        int_allow_interrupt <= 1'b0;
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0)
+                        int_allow_interrupt <= 1'b1;
+                    else if (max_burst_left <= 1'b1)
+                        int_allow_interrupt <= 1'b1;
+                end
+                else if (n_prefetch == 2)
+                begin
+                    if (do_col_req)
+                        int_allow_interrupt <= 1'b0;
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left [0] == 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] == 1'b0)))
+                        int_allow_interrupt <= 1'b1;
+                    else if (int_allow_interrupt && max_burst_left > 1'b1 && ((CFG_REG_GRANT && max_burst_left [0] != 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] != 1'b0))) // so that we don't allow interrupt at odd bursts
+                        int_allow_interrupt <= 1'b0;
+                    else if (max_burst_left <= 1'b1)
+                        int_allow_interrupt <= 1'b1;
+                end
+                else if (n_prefetch == 4)
+                begin
+                    if (do_col_req)
+                        int_allow_interrupt <= 1'b0;
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b00)))
+                        int_allow_interrupt <= 1'b1;
+                    else if (int_allow_interrupt && max_burst_left > 1'b1 && ((CFG_REG_GRANT && max_burst_left [1 : 0] != 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] != 2'b00))) // so that we don't allow interrupt at odd bursts
+                        int_allow_interrupt <= 1'b0;
+                    else if (max_burst_left <= 1'b1)
+                        int_allow_interrupt <= 1'b1;
+                end
+            end
+        end
+    end
+    
+    // Interrupt info when interrupt feature is enabled
+    always @ (*)
+    begin
+        int_interrupt_enable_ready = int_allow_interrupt;
+    end
+    
+    // Interrupt info when interrupt feature is disabled
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_interrupt_disable_ready <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+            begin
+                if (CFG_REG_GRANT)
+                begin
+                    if (max_local_burst_size <= 2'd2)   //do not generate int_interrupt_ready
+                        int_interrupt_disable_ready <= 1'b0;
+                    else if (do_burst_chop && max_local_burst_size <= 3'd4)
+                        int_interrupt_disable_ready <= 1'b0;
+                    else
+                        int_interrupt_disable_ready <= 1'b1;
+                end
+                else
+                begin
+                    if (max_local_burst_size <= 1'b1)   //do not generate int_interrupt_ready if max burst count is 1
+                        int_interrupt_disable_ready <= 1'b0;
+                    else if (do_burst_chop && max_local_burst_size <= 2'd2)
+                        int_interrupt_disable_ready <= 1'b0;
+                    else
+                        int_interrupt_disable_ready <= 1'b1;
+                end
+            end
+            else if (!CFG_REG_GRANT && max_burst_left > 0)
+                int_interrupt_disable_ready <= 1'b1;
+            else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
+                int_interrupt_disable_ready <= 1'b1;
+            else
+                int_interrupt_disable_ready <= 1'b0;
+        end
+    end
+    
+    // Assign to output ports
+    always @ (*)
+    begin
+        if (cfg_enable_burst_interrupt && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
+        begin
+            interrupt_ready =  int_interrupt_enable_ready;
+        end
+        else
+        begin
+            interrupt_ready = ~int_interrupt_disable_ready;
+        end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Burst Interrupt
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Burst Terminate
+//  
+//  LPDDR1 and LPDDR2 specific only
+//
+//--------------------------------------------------------------------------------------------------------
+    // For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
+    // for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_allow_terminate    <= 1'b0;
+            int_do_burst_terminate <= 1'b0;
+        end
+        else
+        begin
+            if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
+            begin
+                if (n_prefetch <= 1) // allow terminate at any clock cycle
+                begin
+                    if (do_col_req && col_address != 0)
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                    else if (do_col_req && !do_auto_precharge && col_address == 0 && size == 1'b1 && (CFG_REG_GRANT && max_local_burst_size > 2)) // only allow terminate for native size larger than 2 in non-registered mode
+                    begin
+                        int_allow_terminate    <= 1'b1;
+                        
+                        if (!int_allow_terminate)
+                            int_do_burst_terminate <= 1'b1;
+                        else
+                            int_do_burst_terminate <= 1'b0;
+                    end
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)))
+                    begin
+                        int_allow_terminate <= 1'b1;
+                        
+                        if (!int_allow_terminate)
+                            int_do_burst_terminate <= 1'b1;
+                        else
+                            int_do_burst_terminate <= 1'b0;
+                    end
+                    else
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                end
+                else if (n_prefetch == 2)
+                begin
+                    if (do_col_req)
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)) && ((CFG_REG_GRANT && max_burst_left [0] == 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] == 1'b0) || int_allow_terminate == 1'b1))
+                    begin
+                        int_allow_terminate <= 1'b1;
+                        
+                        if (!int_allow_terminate)
+                            int_do_burst_terminate <= 1'b1;
+                        else
+                            int_do_burst_terminate <= 1'b0;
+                    end
+                    else
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                end
+                else if (n_prefetch == 4)
+                begin
+                    if (do_col_req)
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                    else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)) && ((CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b00) || int_allow_terminate == 1'b1))
+                    begin
+                        int_allow_terminate <= 1'b1;
+                        
+                        if (!int_allow_terminate)
+                            int_do_burst_terminate <= 1'b1;
+                        else
+                            int_do_burst_terminate <= 1'b0;
+                    end
+                    else
+                    begin
+                        int_allow_terminate    <= 1'b0;
+                        int_do_burst_terminate <= 1'b0;
+                    end
+                end
+            end
+            else
+            begin
+                int_allow_terminate <= 1'b0;
+            end
+        end
+    end
+    
+    // Registered version of do burst terminate
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_do_burst_terminate_r <= 1'b0;
+        end
+        else
+        begin
+            int_do_burst_terminate_r <= int_do_burst_terminate;
+        end
+    end
+    
+    // Effective size, actual issued size migh be smaller that maximum local burst size
+    // we need to inform rank timer about this information for efficient DQ bus turnaround operation
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_effective_size <= 0;
+        end
+        else
+        begin
+            if (do_col_req)
+                int_effective_size <= 1'b1;
+            else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
+                int_effective_size <= int_effective_size + 1'b1;
+        end
+    end
+    
+    // Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
+    // when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
+    // to prevent unwanted DQS toggle on the memory interface
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            doing_burst_terminate <= 1'b0;
+        end
+        else
+        begin
+            if (do_col_req) // reset to "0" after another new column command is detected
+                doing_burst_terminate <= 1'b0;
+            else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
+                doing_burst_terminate <= 1'b1;
+            else
+                doing_burst_terminate <= 1'b0;
+        end
+    end
+    
+    always @ (*)
+    begin
+        if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
+        begin
+            terminate_doing = (|do_burst_terminate) | (doing_burst_terminate & !do_col_req);
+        end
+        else
+        begin
+            terminate_doing = zero;
+        end
+    end
+    
+    // Burst terminate output ports
+    // set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
+    // or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
+    // any command from arbiter is have higher priority compared to burst terminate command
+    always @ (*)
+    begin
+        if (CFG_DWIDTH_RATIO == 2)
+            int_do_req = do_col_req | do_row_req | do_sideband_req; // sideband request might interfere with burst terminate command as well
+        else
+            int_do_req = do_col_req | do_sideband_req;              // sideband request might interfere with burst terminate command as well
+    end
+    
+    generate
+    begin
+        if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
+        begin
+            always @ (*)
+            begin
+                do_burst_terminate = 0;
+                
+                if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
+                begin
+                    if (int_do_req)
+                    begin
+                        do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
+                    end
+                    else
+                    begin
+                        // Use delayed version of burst terminate in REG_GRANT mode so that it won't terminate before interrupt can occur
+                        do_burst_terminate [AFI_INTF_HIGH_PHASE] = (CFG_REG_GRANT) ? int_do_burst_terminate_r : int_do_burst_terminate;
+                    end
+                end
+                else
+                begin
+                    do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
+                end
+            end
+        end
+        else if (CFG_CTL_ARBITER_TYPE == "COLROW")
+        begin
+            always @ (*)
+            begin
+                do_burst_terminate = 0;
+                
+                if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
+                begin
+                    if (int_do_req)
+                    begin
+                        do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
+                    end
+                    else
+                    begin
+                        // Use delayed version of burst terminate in REG_GRANT mode so that it won't terminate before interrupt can occur
+                        do_burst_terminate [AFI_INTF_LOW_PHASE] =  (CFG_REG_GRANT) ? int_do_burst_terminate_r : int_do_burst_terminate;
+                    end
+                end
+                else
+                begin
+                    do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
+                end
+            end
+        end
+    end
+    endgenerate
+    
+    // Effective size output ports
+    always @ (*)
+    begin
+        if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
+        begin
+            effective_size = int_effective_size;
+        end
+        else
+        begin
+            effective_size = {CFG_INT_SIZE_WIDTH{zero}};
+        end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Burst Terminate
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Burst Chop
+//  
+//  DDR3 specific only
+//
+//--------------------------------------------------------------------------------------------------------
+    // yyong generate
+    // yyong begin
+    // yyong     if (CFG_DWIDTH_RATIO == 2)
+    // yyong     begin
+    // yyong         always @ (*)
+    // yyong         begin
+    // yyong             if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
+    // yyong             begin
+    // yyong                 if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
+    // yyong                     do_burst_chop = arb_do_write | arb_do_read;
+    // yyong                 else if (arb_size == 1)
+    // yyong                     do_burst_chop = arb_do_write | arb_do_read;
+    // yyong                 else
+    // yyong                     do_burst_chop = 0;
+    // yyong             end
+    // yyong             else // Other memory types
+    // yyong             begin
+    // yyong                 do_burst_chop = 0;
+    // yyong             end
+    // yyong         end
+    // yyong     end
+    // yyong     else if (CFG_DWIDTH_RATIO == 4)
+    // yyong     begin
+    // yyong         always @ (*)
+    // yyong         begin
+    // yyong             do_burst_chop = 0;
+    // yyong             
+    // yyong             if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
+    // yyong             begin
+    // yyong                 if (arb_size == 1)
+    // yyong                     do_burst_chop = arb_do_write | arb_do_read;
+    // yyong                 else
+    // yyong                     do_burst_chop = 0;
+    // yyong             end
+    // yyong             else // Other memory types
+    // yyong             begin
+    // yyong                 do_burst_chop = 0;
+    // yyong             end
+    // yyong         end
+    // yyong     end
+    // yyong     else if (CFG_DWIDTH_RATIO == 8)
+    // yyong     begin
+    // yyong         // Burst chop is not available in quarter rate
+    // yyong         always @ (*)
+    // yyong         begin
+    // yyong             do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
+    // yyong         end
+    // yyong     end
+    // yyong end
+    // yyong endgenerate
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Burst Chop
+//
+//--------------------------------------------------------------------------------------------------------
+
+
+
+
+
+
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
new file mode 100644
index 0000000..6b0f78c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
@@ -0,0 +1,140 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_burst_tracking
+# (
+    // module parameter port list
+    parameter
+        CFG_BURSTCOUNT_TRACKING_WIDTH   =   7,
+        CFG_BUFFER_ADDR_WIDTH           =   6,
+        CFG_INT_SIZE_WIDTH              =   4
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // data burst interface
+    burst_ready,
+    burst_valid,
+
+    // burstcount counter sent to data_id_manager
+    burst_pending_burstcount,
+    burst_next_pending_burstcount,
+
+    // burstcount consumed by data_id_manager
+    burst_consumed_valid,
+    burst_counsumed_burstcount
+);
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input                                           ctl_clk;
+    input                                           ctl_reset_n;
+    
+    // data burst interface
+    input                                           burst_ready;
+    input                                           burst_valid;
+
+    // burstcount counter sent to data_id_manager
+    output  [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_pending_burstcount;
+    output  [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_next_pending_burstcount;
+
+    // burstcount consumed by data_id_manager
+    input                                           burst_consumed_valid;
+    input   [CFG_INT_SIZE_WIDTH-1:0]                burst_counsumed_burstcount;
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    wire                                            ctl_clk;
+    wire                                            ctl_reset_n;
+
+    // data burst interface
+    wire                                            burst_ready;
+    wire                                            burst_valid;
+
+    // burstcount counter sent to data_id_manager
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_pending_burstcount;
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_next_pending_burstcount;
+    //wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]    burst_count_accepted;
+
+    // burstcount consumed by data_id_manager
+    wire                                            burst_consumed_valid;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                burst_counsumed_burstcount;
+
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    reg     [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_counter;
+    reg     [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]     burst_counter_next;
+    wire                                            burst_accepted;
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    assign burst_pending_burstcount      = burst_counter;
+    assign burst_next_pending_burstcount = burst_counter_next;
+    
+    assign burst_accepted = burst_ready & burst_valid;
+
+    always @ (*) 
+    begin
+        if (burst_accepted & burst_consumed_valid)
+        begin
+            burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
+        end
+        else if (burst_accepted)
+        begin
+            burst_counter_next = burst_counter + 1;
+        end
+        else if (burst_consumed_valid)
+        begin
+            burst_counter_next = burst_counter - burst_counsumed_burstcount;
+        end
+        else 
+        begin
+            burst_counter_next = burst_counter;
+        end
+    end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            burst_counter <= 0;
+        end
+        else
+        begin
+
+            burst_counter <= burst_counter_next;
+
+        end
+    end
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
new file mode 100644
index 0000000..aeb5f31
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
@@ -0,0 +1,2472 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_cmd_gen
+    # (parameter
+        // cmd_gen settings
+        CFG_LOCAL_ADDR_WIDTH            = 33,
+        CFG_LOCAL_SIZE_WIDTH            = 3,
+        CFG_LOCAL_ID_WIDTH              = 8,
+        CFG_INT_SIZE_WIDTH              = 4,
+        CFG_PORT_WIDTH_COL_ADDR_WIDTH   = 4,
+        CFG_PORT_WIDTH_ROW_ADDR_WIDTH   = 5,
+        CFG_PORT_WIDTH_BANK_ADDR_WIDTH  = 2,
+        CFG_PORT_WIDTH_CS_ADDR_WIDTH    = 2,
+        CFG_PORT_WIDTH_BURST_LENGTH     = 5,
+        CFG_PORT_WIDTH_ADDR_ORDER       = 2,
+        CFG_DWIDTH_RATIO                = 2, // 2-FR,4-HR,8-QR
+        CFG_CTL_QUEUE_DEPTH             = 8,
+        CFG_MEM_IF_CHIP                 = 1, // one hot
+        CFG_MEM_IF_CS_WIDTH             = 1, // binary coded
+        CFG_MEM_IF_BA_WIDTH             = 3,
+        CFG_MEM_IF_ROW_WIDTH            = 13,
+        CFG_MEM_IF_COL_WIDTH            = 10,
+        CFG_DATA_ID_WIDTH               = 10,
+        CFG_ENABLE_QUEUE                = 1,
+        CFG_ENABLE_BURST_MERGE          = 1,
+        CFG_CMD_GEN_OUTPUT_REG          = 0,
+        CFG_CTL_TBP_NUM                 = 4,
+        CFG_CTL_SHADOW_TBP_NUM          = 4,
+        MIN_COL                         = 8,
+        MIN_ROW                         = 12,
+        MIN_BANK                        = 2,
+        MIN_CS                          = 1
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // tbp interface
+        tbp_full,
+        tbp_load,
+        tbp_read,
+        tbp_write,
+        tbp_chipsel,
+        tbp_bank,
+        tbp_row,
+        tbp_col,
+        tbp_shadow_chipsel,
+        tbp_shadow_bank,
+        tbp_shadow_row,
+        cmd_gen_load,
+        cmd_gen_waiting_to_load,
+        cmd_gen_chipsel,
+        cmd_gen_bank,
+        cmd_gen_row,
+        cmd_gen_col,
+        cmd_gen_write,
+        cmd_gen_read,
+        cmd_gen_multicast,
+        cmd_gen_size,
+        cmd_gen_localid,
+        cmd_gen_dataid,
+        cmd_gen_priority,
+        cmd_gen_rmw_correct,
+        cmd_gen_rmw_partial,
+        cmd_gen_autopch,
+        cmd_gen_complete,
+        cmd_gen_same_chipsel_addr,
+        cmd_gen_same_bank_addr,
+        cmd_gen_same_row_addr,
+        cmd_gen_same_col_addr,
+        cmd_gen_same_read_cmd,
+        cmd_gen_same_write_cmd,
+        cmd_gen_same_shadow_chipsel_addr,
+        cmd_gen_same_shadow_bank_addr,
+        cmd_gen_same_shadow_row_addr,
+	cmd_gen_busy,
+        
+        // input interface
+        cmd_gen_full,
+        cmd_valid,
+        cmd_address,
+        cmd_write,
+        cmd_read,
+        cmd_id,
+        cmd_multicast,
+        cmd_size,
+        cmd_priority,
+        cmd_autoprecharge,
+        
+        // datapath interface
+        proc_busy,
+        proc_load,
+        proc_load_dataid,
+        proc_write,
+        proc_read,
+        proc_size,
+        proc_localid,
+        wdatap_free_id_valid, // from wdata path
+        wdatap_free_id_dataid, // from wdata path
+        rdatap_free_id_valid, // from rdata path
+        rdatap_free_id_dataid, // from rdata path
+        tbp_load_index,
+        data_complete,
+        data_rmw_complete,
+        
+        // nodm and ecc signal
+        errcmd_ready,
+        errcmd_valid,
+        errcmd_chipsel,
+        errcmd_bank,
+        errcmd_row,
+        errcmd_column,
+        errcmd_size,
+        errcmd_localid,
+        data_partial_be,
+        
+        // configuration ports
+        cfg_enable_cmd_split,
+        cfg_burst_length,
+        cfg_addr_order,
+        cfg_enable_ecc,
+        cfg_enable_no_dm,
+        cfg_col_addr_width,
+        cfg_row_addr_width,
+        cfg_bank_addr_width,
+        cfg_cs_addr_width
+    );
+    
+    localparam MAX_COL                        = CFG_MEM_IF_COL_WIDTH;
+    localparam MAX_ROW                        = CFG_MEM_IF_ROW_WIDTH;
+    localparam MAX_BANK                       = CFG_MEM_IF_BA_WIDTH;
+    localparam MAX_CS                         = CFG_MEM_IF_CS_WIDTH;
+    localparam BUFFER_WIDTH                   = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
+    localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
+    localparam INT_LOCAL_ADDR_WIDTH           = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
+    
+    localparam CFG_CMD_GEN_SPLIT_REGISTERED   = 1;
+    localparam CFG_LOCAL_BURST_MERGE_IDCMP    = 0;   //Enable/Disable Local ID compare for burst merge
+
+    //ECC State Machine
+    localparam IDLE         = 4'h0;
+    localparam CORRECT_RD   = 4'h1;
+    localparam PARWR_WR     = 4'h2;
+    localparam FULL_WR      = 4'h3;
+    localparam PARWR_RD     = 4'h4;
+    localparam FULL_RD      = 4'h6;
+    localparam CORRECT_WR   = 4'h8;
+
+    input   ctl_clk;
+    input   ctl_reset_n;
+    
+    input                                                       tbp_full;
+    input   [CFG_CTL_TBP_NUM-1:0]                               tbp_load;
+    input   [CFG_CTL_TBP_NUM-1:0]                               tbp_read;
+    input   [CFG_CTL_TBP_NUM-1:0]                               tbp_write;
+    input   [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]         tbp_chipsel;
+    input   [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]         tbp_bank;
+    input   [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0]        tbp_row;
+    input   [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0]        tbp_col;
+    input   [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]  tbp_shadow_chipsel;
+    input   [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]  tbp_shadow_bank;
+    input   [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
+    output                                                      cmd_gen_load;
+    output                                                      cmd_gen_waiting_to_load;
+    output  [CFG_MEM_IF_CS_WIDTH-1:0]                           cmd_gen_chipsel;
+    output  [CFG_MEM_IF_BA_WIDTH-1:0]                           cmd_gen_bank;
+    output  [CFG_MEM_IF_ROW_WIDTH-1:0]                          cmd_gen_row;
+    output  [CFG_MEM_IF_COL_WIDTH-1:0]                          cmd_gen_col;
+    output                                                      cmd_gen_write;
+    output                                                      cmd_gen_read;
+    output                                                      cmd_gen_multicast;
+    output  [CFG_INT_SIZE_WIDTH-1:0]                            cmd_gen_size;
+    output  [CFG_LOCAL_ID_WIDTH-1:0]                            cmd_gen_localid;
+    output  [CFG_DATA_ID_WIDTH-1:0]                             cmd_gen_dataid;
+    output                                                      cmd_gen_priority;
+    output                                                      cmd_gen_rmw_correct;
+    output                                                      cmd_gen_rmw_partial;
+    output                                                      cmd_gen_autopch;
+    output                                                      cmd_gen_complete;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_chipsel_addr;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_bank_addr;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_row_addr;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_col_addr;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_read_cmd;
+    output  [CFG_CTL_TBP_NUM-1:0]                               cmd_gen_same_write_cmd;
+    output  [CFG_CTL_SHADOW_TBP_NUM-1:0]                        cmd_gen_same_shadow_chipsel_addr;
+    output  [CFG_CTL_SHADOW_TBP_NUM-1:0]                        cmd_gen_same_shadow_bank_addr;
+    output  [CFG_CTL_SHADOW_TBP_NUM-1:0]                        cmd_gen_same_shadow_row_addr;
+    output							cmd_gen_busy;
+    
+    output                                       cmd_gen_full;
+    input                                        cmd_valid;
+    input   [CFG_LOCAL_ADDR_WIDTH-1:0]           cmd_address;
+    input                                        cmd_write;
+    input                                        cmd_read;
+    input   [CFG_LOCAL_ID_WIDTH-1:0]             cmd_id;
+    input                                        cmd_multicast;
+    input   [CFG_LOCAL_SIZE_WIDTH-1:0]           cmd_size;
+    input                                        cmd_priority;
+    input                                        cmd_autoprecharge;
+    
+    output                                       proc_busy;
+    output                                       proc_load;
+    output                                       proc_load_dataid;
+    output                                       proc_write;
+    output                                       proc_read;
+    output  [CFG_INT_SIZE_WIDTH-1:0]             proc_size;
+    output  [CFG_LOCAL_ID_WIDTH-1:0]             proc_localid;
+    input                                        wdatap_free_id_valid;
+    input   [CFG_DATA_ID_WIDTH-1:0]              wdatap_free_id_dataid;
+    input                                        rdatap_free_id_valid;
+    input   [CFG_DATA_ID_WIDTH-1:0]              rdatap_free_id_dataid;
+    output  [CFG_CTL_TBP_NUM-1:0]                tbp_load_index;
+    input   [CFG_CTL_TBP_NUM-1:0]                data_complete;
+    input                                        data_rmw_complete;
+    
+    output                                       errcmd_ready; // high means cmd_gen accepts command
+    input                                        errcmd_valid;
+    input   [CFG_MEM_IF_CS_WIDTH-1:0]            errcmd_chipsel;
+    input   [CFG_MEM_IF_BA_WIDTH-1:0]            errcmd_bank;
+    input   [CFG_MEM_IF_ROW_WIDTH-1:0]           errcmd_row;
+    input   [CFG_MEM_IF_COL_WIDTH-1:0]           errcmd_column;
+    input   [CFG_INT_SIZE_WIDTH-1:0]             errcmd_size;
+    input   [CFG_LOCAL_ID_WIDTH   - 1 : 0]       errcmd_localid;
+    input                                        data_partial_be;
+    
+    input                                        cfg_enable_cmd_split;
+    input   [CFG_PORT_WIDTH_BURST_LENGTH-1:0]    cfg_burst_length;  // this contains immediate BL value, max is 31
+    input   [CFG_PORT_WIDTH_ADDR_ORDER-1:0]      cfg_addr_order;    // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
+    input                                        cfg_enable_ecc;
+    input                                        cfg_enable_no_dm;
+    input   [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0]  cfg_col_addr_width;
+    input   [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0]  cfg_row_addr_width;
+    input   [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
+    input   [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0]   cfg_cs_addr_width;
+    
+    // === address mapping
+    
+    integer n;
+    integer j;
+    integer k;
+    integer m;
+    
+    wire                                   cfg_enable_rmw;
+    wire			           take_from_ecc_correct;
+    wire				   ecc_queue_load;
+    wire				   split_queue_load;
+    wire				   split_queue_load_for_avl;
+    wire				   split_queue_load_init;	
+    wire				   split_queue_load_ecc_load;
+    reg					   split_queue_load_open;
+    wire				   split_queue_load_open_final;
+    wire				   split_queue_fast_unload;
+    reg     [3:0]			   ecc_state_sm;
+    
+    wire    [INT_LOCAL_ADDR_WIDTH-1:0]     int_cmd_address;
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      int_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      int_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     int_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     int_col_addr;
+    
+    // === command splitting block
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      int_split_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      int_split_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     int_split_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     int_split_col_addr;
+    reg                                    int_split_read;
+    wire				   int_split_read_final;
+    reg                                    int_split_write;
+    wire				   int_split_write_final; 
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       int_split_size;
+    reg                                    int_split_autopch;
+    reg                                    int_split_multicast;
+    reg                                    int_split_priority;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       int_split_localid;
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      split_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      split_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     split_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     split_col_addr;
+    reg                                    split_read;
+    reg                                    split_write;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       split_size;
+    reg                                    split_autopch;
+    reg                                    split_multicast;
+    reg                                    split_priority;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       split_localid;
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      buf_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      buf_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     buf_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     buf_col_addr;
+    reg                                    buf_read_req;
+    reg                                    buf_write_req;
+    reg                                    buf_autopch_req;
+    reg                                    buf_multicast;
+    reg                                    buf_priority;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       buf_localid;
+    reg     [CFG_LOCAL_SIZE_WIDTH:0]       buf_size;
+    
+    reg                                    buf_chip_addr_reach_max;
+    reg                                    buf_bank_addr_reach_max;
+    reg                                    buf_row_addr_reach_max;
+    reg                                    buf_col_addr_reach_max;
+    
+    reg     [3 : 0]                        int_buf_row_addr_reach_max;
+    
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       decrmntd_size;
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      incrmntd_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      incrmntd_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     incrmntd_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     incrmntd_col_addr;
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      max_chip_from_csr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      max_bank_from_csr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     max_row_from_csr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     max_col_from_csr;
+    
+    wire                                   copy;
+    reg     [2:0]                          unaligned_burst;  // because planned max native size is 8, unaligned burst can be a max of 7
+    reg     [3:0]                          native_size;      // support native size up to 15, bl16 FR have native size of 8
+    reg     [4:0]                          native_size_x2;
+    wire                                   require_gen;
+    reg                                    deassert_ready;
+    reg                                    registered;
+    reg                                    generating;
+    
+    // === ecc mux
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      ecc_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      ecc_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     ecc_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     ecc_col_addr;
+    reg                                    ecc_read;
+    reg                                    ecc_write;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       ecc_size;
+    reg                                    ecc_autopch;
+    reg                                    ecc_multicast;
+    reg                                    ecc_priority;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       ecc_localid;
+    reg     [CFG_DATA_ID_WIDTH-1:0]        ecc_dataid;
+    reg                                    ecc_correct;
+    reg                                    ecc_partial;
+    
+    reg                                    ecc_rmw_read;
+    reg                                    ecc_rmw_write;
+    reg                                    errcmd_ready;
+    reg                                    correct;
+    reg                                    partial_opr;
+
+    wire                                   mux_busy;
+    wire                                   mux_busy_non_ecc; 
+    wire			           mux_busy_ecc;
+    
+    wire    [CFG_MEM_IF_CS_WIDTH-1:0]      muxed_cs_addr;
+    wire    [CFG_MEM_IF_BA_WIDTH-1:0]      muxed_bank_addr;
+    wire    [CFG_MEM_IF_ROW_WIDTH-1:0]     muxed_row_addr;
+    wire    [CFG_MEM_IF_COL_WIDTH-1:0]     muxed_col_addr;
+    wire                                   muxed_read;
+    wire                                   muxed_write;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]       muxed_size;
+    wire                                   muxed_autopch;
+    wire                                   muxed_multicast;
+    wire                                   muxed_priority;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]       muxed_localid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]        muxed_dataid;
+    wire                                   muxed_complete;
+    wire                                   muxed_correct;
+    wire                                   muxed_partial;
+    
+    wire                                   proc_busy;
+    wire                                   proc_load;
+    wire                                   proc_load_dataid;
+    wire                                   proc_write;
+    wire                                   proc_read;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]       proc_size;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]       proc_localid;
+    
+    reg                                    ecc_proc_busy;
+    reg					   ecc_proc_busy_parwr_read_queue_load;
+    reg                                    ecc_proc_load;
+    reg                                    ecc_proc_load_dataid;
+    reg                                    ecc_proc_write;
+    reg                                    ecc_proc_read;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       ecc_proc_size;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       ecc_proc_localid;
+    
+    reg                                    waiting_to_load;
+    
+    wire    [CFG_CTL_TBP_NUM-1:0]          tbp_load_index;
+    
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
+    
+    // === queue
+    
+    reg     [BUFFER_WIDTH-1:0]               pipe[CFG_CTL_QUEUE_DEPTH-1:0];
+    reg                                      pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
+    
+    wire                                     fetch;
+    wire    [BUFFER_WIDTH-1:0]               buffer_input;
+    wire                                     write_to_queue;
+    wire                                     queue_full;
+    
+    wire                                     cmd_gen_load;
+    wire                                     cmd_gen_waiting_to_load;
+    wire    [CFG_MEM_IF_CS_WIDTH-1:0]        cmd_gen_chipsel;
+    wire    [CFG_MEM_IF_BA_WIDTH-1:0]        cmd_gen_bank;
+    wire    [CFG_MEM_IF_ROW_WIDTH-1:0]       cmd_gen_row;
+    wire    [CFG_MEM_IF_COL_WIDTH-1:0]       cmd_gen_col;
+    wire                                     cmd_gen_write;
+    wire                                     cmd_gen_read;
+    wire                                     cmd_gen_multicast;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]         cmd_gen_size;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]         cmd_gen_localid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]          cmd_gen_dataid;
+    wire                                     cmd_gen_priority;
+    wire                                     cmd_gen_rmw_correct;
+    wire                                     cmd_gen_rmw_partial;
+    wire                                     cmd_gen_autopch;
+    wire                                     cmd_gen_complete;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_chipsel_addr;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_bank_addr;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_row_addr;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_col_addr;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_read_cmd;
+    wire    [CFG_CTL_TBP_NUM-1:0]            cmd_gen_same_write_cmd;
+    wire    [CFG_CTL_SHADOW_TBP_NUM-1:0]     cmd_gen_same_shadow_chipsel_addr;
+    wire    [CFG_CTL_SHADOW_TBP_NUM-1:0]     cmd_gen_same_shadow_bank_addr;
+    wire    [CFG_CTL_SHADOW_TBP_NUM-1:0]     cmd_gen_same_shadow_row_addr;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_chipsel_addr;
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_bank_addr;
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_row_addr;
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_col_addr;
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_read_cmd;
+    reg     [CFG_CTL_TBP_NUM-1:0]            same_write_cmd;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     same_shadow_chipsel_addr;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     same_shadow_bank_addr;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     same_shadow_row_addr;
+    
+    reg                                      read           [CFG_CTL_TBP_NUM-1:0];
+    reg                                      write          [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]        chipsel        [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]        bank           [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]       row            [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]       col            [CFG_CTL_TBP_NUM-1:0];
+    
+    wire    [CFG_MEM_IF_CS_WIDTH-1:0]        shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    wire    [CFG_MEM_IF_BA_WIDTH-1:0]        shadow_bank    [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    wire    [CFG_MEM_IF_ROW_WIDTH-1:0]       shadow_row     [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]      int_ecc_cs_addr;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]      int_ecc_bank_addr;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]     int_ecc_row_addr;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]     int_ecc_col_addr;
+    reg                                    int_ecc_read;
+    wire                                   int_ecc_read_final;
+    reg                                    int_ecc_write;
+    wire				   int_ecc_write_final;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]       int_ecc_size;
+    reg                                    int_ecc_autopch;
+    reg                                    int_ecc_multicast;
+    reg                                    int_ecc_priority;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]       int_ecc_localid;
+    reg     [CFG_DATA_ID_WIDTH-1:0]        int_ecc_dataid;
+    reg					   int_ecc_data_complete;
+    reg                                    int_ecc_partial_be;
+    wire				   int_ecc_data_complete_final;
+    wire                                   int_ecc_partial_be_final;
+
+    //Burst merge
+    wire                                        cmd_gen_full_postq;
+    wire                                        cmd_valid_postq;
+    wire                                        cmd_write_postq;
+    wire                                        cmd_read_postq;
+    wire     [CFG_LOCAL_ID_WIDTH-1:0]           cmd_id_postq;
+    wire                                        cmd_multicast_postq;
+    wire     [CFG_LOCAL_SIZE_WIDTH-1:0]         cmd_size_postq;
+    wire     [CFG_LOCAL_SIZE_WIDTH:0]           cmd_size_plus_unaligned_size;
+    wire                                        cmd_priority_postq;
+    wire                                        cmd_autoprecharge_postq;
+    wire     [CFG_MEM_IF_CS_WIDTH-1:0]          int_cs_addr_postq;
+    wire     [CFG_MEM_IF_BA_WIDTH-1:0]          int_bank_addr_postq;
+    wire     [CFG_MEM_IF_ROW_WIDTH-1:0]         int_row_addr_postq;
+    wire     [CFG_MEM_IF_COL_WIDTH-1:0]         int_col_addr_postq; 
+
+    wire    one;
+    
+    //======================================================================================
+    //
+    //  [START] General
+    //
+    //======================================================================================
+        assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
+        
+        assign one            = 1'b1;
+        
+    //======================================================================================
+    //
+    //  [END] General
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] TBP Info
+    //
+    //======================================================================================
+        generate
+            genvar p;
+            for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
+                begin : info_per_tbp
+                    always @ (*)
+                        begin
+                            read   [p] = tbp_read   [p];
+                            write  [p] = tbp_write  [p];
+                            chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
+                            bank   [p] = tbp_bank   [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
+                            row    [p] = tbp_row    [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
+                            col    [p] = tbp_col    [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
+                        end
+                end
+            
+            for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
+                begin : info_per_shadow_tbp
+                    assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
+                    assign shadow_bank   [p] = tbp_shadow_bank   [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
+                    assign shadow_row    [p] = tbp_shadow_row    [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
+                end
+        endgenerate
+    //======================================================================================
+    //
+    //  [END] TBP Info
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Address re-mapping
+    //
+    //======================================================================================
+        // Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
+        always @ (*)
+            begin
+                // Row width info
+                if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
+                    begin
+                        cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
+                    begin
+                        cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                    begin
+                        cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                
+                // Bank width info
+                if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
+                    begin
+                        cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                    begin
+                        cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                
+                // Chipsel width info
+                if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
+                    begin
+                        cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+                else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                    begin
+                        cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
+                    end
+            end
+        
+        assign  int_cmd_address =   cmd_address;
+        
+        // Supported addr order
+        // 0 - chip-row-bank-col
+        // 1 - chip-bank-row-col
+        // 2 - row-chip-bank-col
+        
+        // Derive column address from address
+        always @(*)
+            begin : Col_addr_loop
+                int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
+                
+                for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
+                    begin
+                        if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
+                            begin
+                                int_col_addr[n] = int_cmd_address[n];
+                            end
+                        else
+                            begin
+                                int_col_addr[n] = 1'b0;
+                            end
+                    end
+                
+                int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
+            end
+        
+        // Derive row address from address
+        reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
+        reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
+        
+        always @(*)
+            begin : Row_addr_loop
+                for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
+                    begin
+                        row_addr_loop_1 = j + cfg_addr_bitsel_row;
+                        int_row_addr[j] = int_cmd_address[row_addr_loop_1];
+                    end
+                
+                for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
+                    begin
+                        row_addr_loop_2 = j + cfg_addr_bitsel_row;
+                        
+                        if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
+                            begin
+                                int_row_addr[j] = int_cmd_address[row_addr_loop_2];
+                            end
+                        else
+                            begin
+                                int_row_addr[j] = 1'b0;
+                            end
+                    end
+            end
+        
+        // Derive bank address from address
+        reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
+        reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
+        
+        always @(*)
+            begin : Bank_addr_loop
+                for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
+                    begin
+                        bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
+                        int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
+                    end
+                
+                for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
+                    begin
+                        bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
+                        
+                        if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
+                            begin
+                                int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
+                            end
+                        else
+                            begin
+                                int_bank_addr[k] = 1'b0;
+                            end
+                    end
+            end
+        
+        // Derive chipsel address from address
+        always @(*)
+            begin
+                m = 0;
+                
+                if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
+                    begin
+                        for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
+                            begin
+                                int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
+                            end
+                        for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
+                            begin
+                                if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
+                                    begin
+                                        int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
+                                    end
+                                else
+                                    begin
+                                        int_cs_addr[m] = 1'b0;
+                                    end
+                            end
+                    end
+                else  // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
+                    begin
+                        int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
+                    end
+            end
+    //======================================================================================
+    //
+    //  [END] Address re-mapping
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Burst Merge
+    //
+    //======================================================================================
+
+generate
+	if (CFG_ENABLE_BURST_MERGE == 1)
+    		begin
+	    	reg                                        cmd_write_str[1:0];
+    		wire                                       cmd_read_str[1:0];
+    		reg     [CFG_LOCAL_ID_WIDTH-1:0]           cmd_id_str[1:0];
+    		reg                                        cmd_multicast_str[1:0];
+    		reg     [CFG_LOCAL_SIZE_WIDTH-1:0]         cmd_size_str[1:0];
+    		reg                                        cmd_priority_str[1:0];
+    		reg                                        cmd_autoprecharge_str[1:0];
+    		reg     [CFG_MEM_IF_CS_WIDTH-1:0]          int_cs_addr_str[1:0];
+    		reg     [CFG_MEM_IF_BA_WIDTH-1:0]          int_bank_addr_str[1:0];
+    		reg     [CFG_MEM_IF_ROW_WIDTH-1:0]         int_row_addr_str[1:0];
+    		reg     [CFG_MEM_IF_COL_WIDTH-1:0]         int_col_addr_str[1:0];
+
+    		reg     [1:0]			       bm_write_ptr;
+    		reg     [1:0]			       bm_read_ptr;
+
+    		wire		                   bm_cs_can_merge;
+    		wire				   bm_bank_can_merge;
+    		wire				   bm_row_can_merge;
+    		wire				   bm_read_can_merge;
+    		wire				   bm_write_can_merge;
+    		wire				   bm_localid_can_merge;
+
+    		wire				   bm_valid_can_merge;
+    		wire				   bm_seqcol_can_merge;
+    		wire    [CFG_MEM_IF_COL_WIDTH:0]   bm_nextcol_can_merge;
+    		wire    [CFG_MEM_IF_COL_WIDTH-1:0] bm_base_col_addr;
+    		wire    [CFG_LOCAL_SIZE_WIDTH-1:0] bm_base_size; 
+    		wire    [CFG_MEM_IF_COL_WIDTH-1:0] bm_nextbase_col_addr;
+    		wire    [CFG_LOCAL_SIZE_WIDTH:0]   bm_total_merge_size;
+    		wire                               bm_oversize;
+		wire				   bm_cross_row;
+
+    		wire				   bm_can_merge;
+
+    		assign cmd_gen_full = (bm_write_ptr[1] != bm_read_ptr[1]) && (bm_write_ptr[0] == bm_read_ptr[0]);
+    		assign cmd_valid_postq = (bm_write_ptr != bm_read_ptr); 
+	
+    		assign cmd_read_str[0] = !cmd_write_str[0];
+    		assign cmd_read_str[1] = !cmd_write_str[1];
+
+    		assign int_col_addr_postq 		= bm_read_ptr[0] ? int_col_addr_str[1] 		: int_col_addr_str[0];
+    		assign int_row_addr_postq 		= bm_read_ptr[0] ? int_row_addr_str[1] 		: int_row_addr_str[0];
+    		assign int_bank_addr_postq 		= bm_read_ptr[0] ? int_bank_addr_str[1] 	: int_bank_addr_str[0];
+    		assign int_cs_addr_postq 		= bm_read_ptr[0] ? int_cs_addr_str[1] 		: int_cs_addr_str[0];
+    		assign cmd_write_postq 		= bm_read_ptr[0] ? cmd_write_str[1] 		: cmd_write_str[0];
+    		assign cmd_read_postq 		= bm_read_ptr[0] ? cmd_read_str[1] 		: cmd_read_str[0];
+    		assign cmd_id_postq 		= bm_read_ptr[0] ? cmd_id_str[1] 		: cmd_id_str[0];
+    		assign cmd_multicast_postq 		= bm_read_ptr[0] ? cmd_multicast_str[1] 	: cmd_multicast_str[0];
+    		assign cmd_size_postq 		= bm_read_ptr[0] ? cmd_size_str[1] 		: cmd_size_str[0];
+    		assign cmd_priority_postq 		= bm_read_ptr[0] ? cmd_priority_str[1] 		: cmd_priority_str[0];
+    		assign cmd_autoprecharge_postq 	= bm_read_ptr[0] ? cmd_autoprecharge_str[1] 	: cmd_autoprecharge_str[0];
+
+    		assign bm_cs_can_merge 		= (int_cs_addr_str[1] == int_cs_addr_str[0]);
+    		assign bm_bank_can_merge 		= (int_bank_addr_str[1] == int_bank_addr_str[0]);
+    		assign bm_row_can_merge 		= (int_row_addr_str[1] == int_row_addr_str[0]);
+    		assign bm_read_can_merge 		= (cmd_read_str[1] == cmd_read_str[0]);
+    		assign bm_write_can_merge 		= (cmd_write_str[1] == cmd_write_str[0]);
+    		assign bm_localid_can_merge 	= (CFG_LOCAL_BURST_MERGE_IDCMP == 1) ? (cmd_id_str[1] == cmd_id_str[0]) : 1'b1;
+    		assign bm_valid_can_merge 		= cmd_gen_full;
+
+    		assign bm_nextcol_can_merge         = bm_base_col_addr + (bm_base_size * CFG_DWIDTH_RATIO);
+    		assign bm_base_col_addr		    = int_col_addr_postq;
+    		assign bm_base_size		    = cmd_size_postq; 
+    		assign bm_nextbase_col_addr         = bm_read_ptr[0] ? int_col_addr_str[0] 		: int_col_addr_str[1];  //reverse ordr
+    		assign bm_seqcol_can_merge          = (bm_nextcol_can_merge == bm_nextbase_col_addr);
+    		assign bm_total_merge_size          = cmd_size_str[1] + cmd_size_str[0];
+    		assign bm_oversize                  = (bm_total_merge_size[CFG_LOCAL_SIZE_WIDTH] == 1);
+		assign bm_cross_row		    = (bm_nextcol_can_merge[CFG_MEM_IF_COL_WIDTH] == 1);
+
+		assign bm_can_merge = (CFG_ENABLE_BURST_MERGE == 1) ? (bm_valid_can_merge && bm_read_can_merge && bm_write_can_merge && bm_localid_can_merge && bm_bank_can_merge && bm_row_can_merge && bm_cs_can_merge && bm_seqcol_can_merge && !bm_oversize && !bm_cross_row && cmd_gen_full_postq) : 0;
+
+		//2 deep queue
+        	always @(posedge ctl_clk, negedge ctl_reset_n)
+            		begin
+                	if (!ctl_reset_n)
+                    		begin
+	            		int_col_addr_str[0] <= 0;
+    				int_row_addr_str[0] <= 0;
+    				int_bank_addr_str[0] <= 0;
+    				int_cs_addr_str[0] <= 0;
+    				cmd_write_str[0] <= 0;
+    				cmd_id_str[0] <= 0;
+    				cmd_multicast_str[0] <= 0;
+    				cmd_size_str[0] <= 0;
+    				cmd_priority_str[0] <= 0;
+    				cmd_autoprecharge_str[0] <= 0;
+                    		end
+                	else
+                    		begin
+                        	if (cmd_valid && !cmd_gen_full && (bm_write_ptr[0] == 0))
+                            		begin
+					int_col_addr_str[0] <= int_col_addr;
+    					int_row_addr_str[0] <= int_row_addr;
+    					int_bank_addr_str[0] <= int_bank_addr;
+    					int_cs_addr_str[0] <= int_cs_addr;
+    					cmd_write_str[0] <= cmd_write;
+    					cmd_id_str[0] <= cmd_id;
+    					cmd_multicast_str[0] <= cmd_multicast;
+    					cmd_size_str[0] <= cmd_size;
+    					cmd_priority_str[0] <= cmd_priority;
+    					cmd_autoprecharge_str[0] <= cmd_autoprecharge;
+                            		end
+				else if (bm_can_merge)
+					begin
+					if ((bm_read_ptr[0] == 1))
+						begin
+						int_col_addr_str[0] 	 <= int_col_addr_str[1];
+						end
+                                	cmd_size_str[0] 	 <= cmd_size_str[0] + cmd_size_str[1];
+			 		cmd_priority_str[0] 	 <= cmd_priority_str[0] || cmd_priority_str[1];
+					cmd_autoprecharge_str[0] <= cmd_autoprecharge_str[0] || cmd_autoprecharge_str[1];
+					cmd_multicast_str[0]	 <= cmd_multicast_str[0] || cmd_multicast_str[1];
+					end
+                    		end
+            		end
+
+		//2 deep queue
+       		always @(posedge ctl_clk, negedge ctl_reset_n)
+            		begin
+                	if (!ctl_reset_n)
+                    		begin
+				int_col_addr_str[1] <= 0;
+    				int_row_addr_str[1] <= 0;
+    				int_bank_addr_str[1] <= 0;
+    				int_cs_addr_str[1] <= 0;
+    				cmd_write_str[1] <= 0;
+    				cmd_id_str[1] <= 0;
+    				cmd_multicast_str[1] <= 0;
+    				cmd_size_str[1] <= 0;
+    				cmd_priority_str[1] <= 0;
+    				cmd_autoprecharge_str[1] <= 0;
+                    		end
+                	else
+                    		begin
+				if (cmd_valid && !cmd_gen_full && (bm_write_ptr[0] == 1))
+                            		begin
+					int_col_addr_str[1] <= int_col_addr;
+    					int_row_addr_str[1] <= int_row_addr;
+    					int_bank_addr_str[1] <= int_bank_addr;
+    					int_cs_addr_str[1] <= int_cs_addr;
+    					cmd_write_str[1] <= cmd_write;
+    					cmd_id_str[1] <= cmd_id;
+    					cmd_multicast_str[1] <= cmd_multicast;
+    					cmd_size_str[1] <= cmd_size;
+    					cmd_priority_str[1] <= cmd_priority;
+    					cmd_autoprecharge_str[1] <= cmd_autoprecharge;
+                            		end
+                    		end
+            		end
+
+		//write pointer
+        	always @(posedge ctl_clk, negedge ctl_reset_n)
+            		begin
+                	if (!ctl_reset_n)
+                    		begin
+				bm_write_ptr        <= 0;
+                    		end
+                	else
+                    		begin
+                        	if (cmd_valid && !cmd_gen_full)
+                            		begin
+					bm_write_ptr      <= bm_write_ptr + 1;
+                            		end
+				else if (bm_can_merge)
+					begin
+					bm_write_ptr      <= 1;
+					end
+                   		end
+            		end
+
+    		//read pointer
+        	always @(posedge ctl_clk, negedge ctl_reset_n)
+            		begin
+                	if (!ctl_reset_n)
+                    		begin
+				bm_read_ptr        <= 0;
+                    		end
+                	else
+                    		begin
+				if (cmd_valid_postq && !cmd_gen_full_postq)
+			    		begin
+					bm_read_ptr      <= bm_read_ptr + 1;
+			    		end	    
+				else if (bm_can_merge)
+					begin
+					bm_read_ptr      <= 0;
+					end
+                    		end
+            		end
+		end
+	else
+		begin
+		assign cmd_gen_full		= cmd_gen_full_postq;
+                assign cmd_valid_postq		= cmd_valid;
+                assign cmd_write_postq 		= cmd_write;
+                assign cmd_read_postq 		= cmd_read;
+                assign cmd_id_postq 		= cmd_id;
+                assign cmd_multicast_postq 	= cmd_multicast;
+                assign cmd_size_postq 		= cmd_size;
+                assign cmd_priority_postq 	= cmd_priority;
+                assign cmd_autoprecharge_postq 	= cmd_autoprecharge;
+                assign int_cs_addr_postq 	= int_cs_addr;
+                assign int_bank_addr_postq 	= int_bank_addr;
+                assign int_row_addr_postq 	= int_row_addr;
+                assign int_col_addr_postq 	= int_col_addr;
+		end
+endgenerate
+
+    //======================================================================================
+    //
+    //  [END] Burst Merge
+    //
+    //======================================================================================
+
+    //======================================================================================
+    //
+    //  [START] Burst splitting
+    //
+    //======================================================================================
+	assign 	cmd_gen_busy = cmd_gen_load || cmd_valid;
+        assign  cmd_gen_full_postq = mux_busy | deassert_ready;
+        assign  copy               = ~cmd_gen_full_postq & cmd_valid_postq; // Copy current input command info into a register
+	assign  cmd_size_plus_unaligned_size = unaligned_burst + cmd_size_postq;
+        assign  require_gen        = (cmd_size_postq > native_size | cmd_size_plus_unaligned_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
+        
+        // CSR address calculation
+        always @ (*)
+            begin
+                max_chip_from_csr = (2**cfg_cs_addr_width)   - 1'b1;
+                max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
+                max_row_from_csr  = (2**cfg_row_addr_width)  - 1'b1;
+                max_col_from_csr  = (2**cfg_col_addr_width)  - 1'b1;
+            end
+        
+        // Calculate native size for selected burstlength and controller rate
+        always @ (*)
+            begin
+                native_size    = 1 * (cfg_burst_length / CFG_DWIDTH_RATIO); // 1 for bl2 FR, 2 for bl8 HR, ...
+                native_size_x2 = 2 * (cfg_burst_length / CFG_DWIDTH_RATIO); // 2X of original native size
+            end
+        
+        always @(*)
+            begin
+                if (native_size == 1)
+                    begin
+                        unaligned_burst = 0;
+                    end
+                else if (native_size == 2)
+                    begin
+                        unaligned_burst = {2'd0,int_col_addr_postq[log2(CFG_DWIDTH_RATIO)]};
+                    end
+                else if (native_size == 4)
+                    begin
+                        unaligned_burst = {1'd0,int_col_addr_postq[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
+                    end
+                else // native_size == 8
+                    begin
+                        unaligned_burst = int_col_addr_postq[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
+                    end
+            end
+        
+        // Deassert local_ready signal because need to split local command into multiple memory commands
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        deassert_ready <= 0;
+                    end
+                else
+                    begin
+                        if (copy && require_gen)
+                            begin
+                                deassert_ready <= 1;
+                            end
+                        else if ((buf_size > native_size_x2) && cfg_enable_cmd_split)
+                            begin
+                                deassert_ready <= 1;
+                            end
+                        else if (generating && ~mux_busy)
+                            begin
+                                deassert_ready <= 0;
+                            end
+                    end
+            end
+        
+        // Assert register signal so that we will pass split command into TBP
+        always @ (*)
+        begin
+            if (copy && require_gen)
+                begin
+                    registered = 1;
+                end
+            else
+                begin
+                    registered = 0;
+                end
+        end
+        
+        // Generating signal will notify that current command in under splitting process
+        // Signal stays high until the last memory burst aligned command is generated
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        generating <= 0;
+                    end
+                else
+                    begin
+                        if (registered)
+                            begin
+                                generating <= 1;
+                            end
+                        else if ((generating && buf_size > native_size_x2) && cfg_enable_cmd_split)
+                            begin
+                                generating <= 1;
+                            end
+                        else if (~mux_busy)
+                            begin
+                                generating <= 0;
+                            end
+                    end
+            end
+        
+        // Determine the correct size
+        always @(*)
+            begin
+                if (!generating)
+                    begin
+                        if ((cmd_size_plus_unaligned_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
+                            begin
+                                int_split_size = cmd_size_postq;
+                            end
+                        else
+                            begin
+                                int_split_size = native_size - unaligned_burst;
+                            end
+                    end
+                else
+                    begin
+                        int_split_size = decrmntd_size;
+                    end
+            end
+        
+        // MUX logic to determine where to take the command info from
+        always @(*)
+            begin
+                if (!generating) // not generating so take direct input from avalon if
+                    begin
+                        int_split_read      = cmd_read_postq  & cmd_valid_postq;
+                        int_split_write     = cmd_write_postq & cmd_valid_postq;
+                        int_split_autopch   = cmd_autoprecharge_postq;
+                        int_split_multicast = cmd_multicast_postq;
+                        int_split_priority  = cmd_priority_postq;
+                        int_split_localid   = cmd_id_postq;
+                        int_split_cs_addr   = int_cs_addr_postq;
+                        int_split_bank_addr = int_bank_addr_postq;
+                        int_split_row_addr  = int_row_addr_postq;
+                        int_split_col_addr  = int_col_addr_postq;
+                    end
+                else // generating cmd so process buffer content
+                    begin
+                        int_split_read      = buf_read_req;
+                        int_split_write     = buf_write_req;
+                        int_split_autopch   = buf_autopch_req;
+                        int_split_multicast = buf_multicast;
+                        int_split_priority  = buf_priority;
+                        int_split_localid   = buf_localid;
+                        int_split_cs_addr   = incrmntd_cs_addr;
+                        int_split_bank_addr = incrmntd_bank_addr;
+                        int_split_row_addr  = incrmntd_row_addr;
+                        
+                        if (cfg_burst_length == 2)
+                            begin
+                                int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1], 1'b0};
+                            end
+                        else if (cfg_burst_length == 4)
+                            begin
+                                int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2], 2'b00};
+                            end
+                        else if (cfg_burst_length == 8)
+                            begin
+                                int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3], 3'b000};
+                            end
+                        else // if (cfg_burst_length == 16)
+                            begin
+                                int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4], 4'b0000};
+                            end
+                    end
+            end
+            
+            // Split command information
+            generate
+                if (CFG_CMD_GEN_SPLIT_REGISTERED)
+                    begin
+                        always @ (posedge ctl_clk or negedge ctl_reset_n)
+                            begin
+                                if (!ctl_reset_n)
+                                    begin
+                                        split_cs_addr   <= 0;
+                                        split_bank_addr <= 0;
+                                        split_row_addr  <= 0;
+                                        split_col_addr  <= 0;
+                                        split_read      <= 0;
+                                        split_write     <= 0;
+                                        split_size      <= 0;
+                                        split_autopch   <= 0;
+                                        split_multicast <= 0;
+                                        split_priority  <= 0;
+                                        split_localid   <= 0;
+                                    end
+                                else
+                                    begin
+                                        if (!queue_full)
+                                            begin
+                                                split_cs_addr   <= int_split_cs_addr;
+                                                split_bank_addr <= int_split_bank_addr;
+                                                split_row_addr  <= int_split_row_addr;
+                                                split_col_addr  <= int_split_col_addr;
+                                                split_read      <= int_split_read;
+                                                split_write     <= int_split_write;
+                                                split_size      <= int_split_size;
+                                                split_autopch   <= int_split_autopch;
+                                                split_multicast <= int_split_multicast;
+                                                split_priority  <= int_split_priority;
+                                                split_localid   <= int_split_localid;
+                                            end
+                                    end
+                            end
+                    end
+                else
+                    begin
+                        always @ (*)
+                            begin
+                                split_cs_addr   = int_split_cs_addr;
+                                split_bank_addr = int_split_bank_addr;
+                                split_row_addr  = int_split_row_addr;
+                                split_col_addr  = int_split_col_addr;
+                                split_read      = int_split_read;
+                                split_write     = int_split_write;
+                                split_size      = int_split_size;
+                                split_autopch   = int_split_autopch;
+                                split_multicast = int_split_multicast;
+                                split_priority  = int_split_priority;
+                                split_localid   = int_split_localid;
+                            end
+                    end
+            endgenerate
+            
+    //======================================================================================
+    //
+    //  [END] Burst splitting
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Command buffer
+    //
+    //======================================================================================
+        // Keep track of command size during a split process
+        // will keep decreasing when a split command was sent to TBP
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        buf_size      <= 0;
+                        decrmntd_size <= 0;
+                    end
+                else
+                    begin
+                        if (copy)
+                            begin
+                                buf_size <= cmd_size_plus_unaligned_size;
+                                
+                                if ((cmd_size_plus_unaligned_size) > native_size_x2)
+                                    begin
+                                        decrmntd_size <= native_size;
+                                    end
+                                else
+                                    begin
+                                        decrmntd_size <= cmd_size_plus_unaligned_size - native_size;
+                                    end
+                            end
+                        else if (!registered && (buf_size > native_size) && ~mux_busy)
+                            begin
+                                buf_size <= buf_size - native_size;
+                                
+                                if ((buf_size - native_size) > native_size_x2)
+                                    begin
+                                        decrmntd_size <= native_size;
+                                    end
+                                else
+                                    begin
+                                        decrmntd_size <= buf_size - native_size_x2;
+                                    end
+                            end
+                    end
+            end
+        
+        // Address max logic, assert '1' if address reaches boundary
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+                buf_chip_addr_reach_max <= 1'b0;
+                buf_bank_addr_reach_max <= 1'b0;
+                buf_col_addr_reach_max  <= 1'b0;
+                
+                int_buf_row_addr_reach_max <= 0;
+            end
+            else
+            begin
+                if (copy)
+                begin
+                    buf_chip_addr_reach_max <= (int_cs_addr_postq   == max_chip_from_csr) ? 1'b1 : 1'b0;
+                    buf_bank_addr_reach_max <= (int_bank_addr_postq == max_bank_from_csr) ? 1'b1 : 1'b0;
+                    
+                    int_buf_row_addr_reach_max [3] <= (int_row_addr_postq [     CFG_MEM_IF_ROW_WIDTH      - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [     CFG_MEM_IF_ROW_WIDTH      - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [2] <= (int_row_addr_postq [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [1] <= (int_row_addr_postq [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [0] <= (int_row_addr_postq [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    
+                    if ((cfg_burst_length == 16 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
+                        ||
+                        (cfg_burst_length ==  8 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
+                        ||
+                        (cfg_burst_length ==  4 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
+                        ||
+                        (cfg_burst_length ==  2 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
+                        )
+                    begin
+                        buf_col_addr_reach_max <= 1'b1;
+                    end
+                    else
+                    begin
+                        buf_col_addr_reach_max <= 1'b0;
+                    end
+                end
+                else if (generating && ~mux_busy)
+                begin
+                    buf_chip_addr_reach_max <= (buf_cs_addr   == max_chip_from_csr) ? 1'b1 : 1'b0;
+                    buf_bank_addr_reach_max <= (buf_bank_addr == max_bank_from_csr) ? 1'b1 : 1'b0;
+                    
+                    int_buf_row_addr_reach_max [3] <= (buf_row_addr [     CFG_MEM_IF_ROW_WIDTH      - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [     CFG_MEM_IF_ROW_WIDTH      - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [2] <= (buf_row_addr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [1] <= (buf_row_addr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    int_buf_row_addr_reach_max [0] <= (buf_row_addr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]  == max_row_from_csr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
+                    
+                    if ((cfg_burst_length == 16 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
+                        ||
+                        (cfg_burst_length ==  8 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
+                        ||
+                        (cfg_burst_length ==  4 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
+                        ||
+                        (cfg_burst_length ==  2 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
+                        )
+                    begin
+                        buf_col_addr_reach_max <= 1'b1;
+                    end
+                    else
+                    begin
+                        buf_col_addr_reach_max <= 1'b0;
+                    end
+                end
+            end
+        end
+        
+        always @ (*)
+        begin
+            buf_row_addr_reach_max = &int_buf_row_addr_reach_max;
+        end
+        
+        // Buffered command info, to be used in split process
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        buf_read_req    <= 1'b0;
+                        buf_write_req   <= 1'b0;
+                        buf_autopch_req <= 1'b0;
+                        buf_multicast   <= 1'b0;
+                        buf_priority    <= 1'b0;
+                        buf_localid     <= 0;
+                    end
+                else
+                    begin
+                        if (copy)
+                            begin
+                                buf_read_req    <= cmd_read_postq;
+                                buf_write_req   <= cmd_write_postq;
+                                buf_autopch_req <= cmd_autoprecharge_postq;
+                                buf_multicast   <= cmd_multicast_postq;
+                                buf_priority    <= cmd_priority_postq;
+                                buf_localid     <= cmd_id_postq;
+                            end
+                    end
+            end
+        
+        // Keep track of command address during a split process
+        // will keep increasing when a split command was sent to TBP
+        // also takes into account address order
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        buf_cs_addr   <= 0;
+                        buf_bank_addr <= 0;
+                        buf_row_addr  <= 0;
+                        buf_col_addr  <= 0;
+                    end
+                else
+                    if (copy)
+                        begin
+                            buf_cs_addr   <= int_cs_addr_postq;
+                            buf_bank_addr <= int_bank_addr_postq;
+                            buf_row_addr  <= int_row_addr_postq;
+                            buf_col_addr  <= int_col_addr_postq;
+                        end
+                    else if (generating && ~mux_busy)
+                        begin
+                            buf_cs_addr   <= incrmntd_cs_addr;
+                            buf_bank_addr <= incrmntd_bank_addr;
+                            buf_row_addr  <= incrmntd_row_addr;
+                            buf_col_addr  <= incrmntd_col_addr;
+                        end
+            end
+        
+        always @ (*)
+            begin
+                if (buf_col_addr_reach_max)
+                    begin
+                        incrmntd_cs_addr   = buf_cs_addr;
+                        incrmntd_bank_addr = buf_bank_addr;
+                        incrmntd_row_addr  = buf_row_addr;
+                        incrmntd_col_addr  = buf_col_addr;
+                        
+                        if (cfg_burst_length == 16)
+                            begin
+                                incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] = 0;
+                            end
+                        else if (cfg_burst_length == 8)
+                            begin
+                                incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] = 0;
+                            end
+                        else if (cfg_burst_length == 4)
+                            begin
+                                incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] = 0;
+                            end
+                        else //  if (cfg_burst_length == 2)
+                            begin
+                                incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] = 0;
+                            end
+                        
+                        if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
+                            begin
+                                if (buf_bank_addr_reach_max)
+                                    begin
+                                        incrmntd_bank_addr = 0;
+                                        if (buf_chip_addr_reach_max)
+                                            begin
+                                                incrmntd_cs_addr = 0;
+                                                if (buf_row_addr_reach_max)
+                                                    begin
+                                                        incrmntd_row_addr = 0;
+                                                    end
+                                                else
+                                                    begin
+                                                        incrmntd_row_addr = buf_row_addr + 1'b1;
+                                                    end
+                                            end
+                                        else
+                                            begin
+                                                incrmntd_cs_addr = buf_cs_addr + 1'b1;
+                                            end
+                                    end
+                                else
+                                    begin
+                                        incrmntd_bank_addr = buf_bank_addr + 1'b1;
+                                    end
+                            end
+                        else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
+                            begin
+                                if (buf_row_addr_reach_max)
+                                    begin
+                                        incrmntd_row_addr = 0;
+                                        if (buf_bank_addr_reach_max)
+                                            begin
+                                                incrmntd_bank_addr = 0;
+                                                if (buf_chip_addr_reach_max)
+                                                    begin
+                                                        incrmntd_cs_addr = 0;
+                                                    end
+                                                else
+                                                    begin
+                                                        incrmntd_cs_addr = buf_cs_addr + 1'b1;
+                                                    end
+                                            end
+                                        else
+                                            begin
+                                                incrmntd_bank_addr = buf_bank_addr + 1'b1;
+                                            end
+                                    end
+                                else
+                                    begin
+                                        incrmntd_row_addr = buf_row_addr + 1'b1;
+                                    end
+                            end
+                        else // 0 is chiprowbankcol
+                            begin
+                                if (buf_bank_addr_reach_max)
+                                    begin
+                                        incrmntd_bank_addr = 0;
+                                        if (buf_row_addr_reach_max)
+                                            begin
+                                                incrmntd_row_addr = 0;
+                                                if (buf_chip_addr_reach_max)
+                                                    begin
+                                                        incrmntd_cs_addr = 0;
+                                                    end
+                                                else
+                                                    begin
+                                                        incrmntd_cs_addr = buf_cs_addr + 1'b1;
+                                                    end
+                                            end
+                                        else
+                                            begin
+                                                incrmntd_row_addr = buf_row_addr + 1'b1;
+                                            end
+                                    end
+                                else
+                                    begin
+                                        incrmntd_bank_addr = buf_bank_addr + 1'b1;
+                                    end
+                            end
+                    end
+                else
+                    begin
+                        incrmntd_cs_addr   = buf_cs_addr;
+                        incrmntd_bank_addr = buf_bank_addr;
+                        incrmntd_row_addr  = buf_row_addr;
+                        incrmntd_col_addr  = buf_col_addr + cfg_burst_length;
+                    end
+            end
+    //======================================================================================
+    //
+    //  [END] Command buffer
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Data ID related logic
+    //
+    //======================================================================================
+        // proc signals to datapath
+        assign proc_busy        = (cfg_enable_rmw) ? ecc_proc_busy        : tbp_full;
+        assign proc_load        = (cfg_enable_rmw) ? ecc_proc_load        : cmd_gen_load;
+        assign proc_load_dataid = (cfg_enable_rmw) ? ecc_proc_load_dataid : cmd_gen_load;
+        assign proc_write       = (cfg_enable_rmw) ? ecc_proc_write       : cmd_gen_write;
+        assign proc_read        = (cfg_enable_rmw) ? ecc_proc_read        : cmd_gen_read;
+        assign proc_size        = (cfg_enable_rmw) ? ecc_proc_size        : cmd_gen_size;
+        assign proc_localid     = (cfg_enable_rmw) ? ecc_proc_localid     : cmd_gen_localid;
+        assign tbp_load_index   = (cfg_enable_rmw) ? 1                    : tbp_load; // set to '1' in RMW mode, because we need data_complete[0] to toggle indicating wdata is complete
+        
+        always @ (*)
+            begin
+		ecc_proc_busy      = !ecc_proc_busy_parwr_read_queue_load && !split_queue_load_for_avl; 
+		ecc_proc_busy_parwr_read_queue_load = !queue_full && ((ecc_state_sm == 4'h4) || (ecc_state_sm == 4'h1)); 
+		ecc_proc_load        = (ecc_proc_write | ecc_proc_read);
+                ecc_proc_load_dataid = !ecc_rmw_read;                                               // De-assert when we're loading an RMW read
+            end
+        
+        // Seperate into 2 process because ecc_proc read/write needs to be assigned seperately, due to blocking assignments
+        always @ (*)
+            begin
+                ecc_proc_write       = int_split_write;  
+                ecc_proc_read        = int_split_read | ecc_rmw_read;                               // Assert when we're loading an RMW read
+                ecc_proc_size        = int_split_size;
+                ecc_proc_localid     = int_split_localid;
+            end
+        
+    //======================================================================================
+    //
+    //  [END] Data ID related logic
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] ECC related logic
+    //
+    //======================================================================================
+			
+	//State Machine
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+        	if (!ctl_reset_n)
+                begin
+                    ecc_state_sm  <= IDLE;
+                    ecc_read      <= 1'b0;
+                    ecc_write     <= 1'b0;
+                    ecc_rmw_read  <= 1'b0;
+                    ecc_rmw_write <= 1'b0;
+                    correct       <= 1'b0;
+                    errcmd_ready  <= 1'b0;
+                    partial_opr   <= 1'b0;
+                end
+                else
+                begin
+                    case (ecc_state_sm)
+		    	IDLE :
+                        begin
+                       		if (cfg_enable_ecc && errcmd_valid)     
+                        	begin
+                        		ecc_state_sm  <= CORRECT_RD;
+					ecc_read      <= 1'b1;
+					ecc_write     <= 1'b0;
+                			ecc_rmw_read  <= 1'b1;
+                			ecc_rmw_write <= 1'b0;
+					correct       <= 1'b1;
+					errcmd_ready  <= 1'b1;
+                			partial_opr   <= 1'b0;
+                        	end
+				else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
+				begin
+					ecc_state_sm  <= FULL_WR;	//4'h3
+					ecc_read      <= 1'b0;
+                			ecc_write     <= 1'b1;
+					ecc_rmw_read  <= 1'b0;
+					ecc_rmw_write <= 1'b0;
+					correct       <= 1'b0;
+					errcmd_ready  <= 1'b0;
+					partial_opr   <= 1'b0;
+				end
+				else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
+				begin
+					ecc_state_sm  <= PARWR_RD;
+               	 			ecc_read      <= 1'b1;
+                			ecc_write     <= 1'b0;
+                			ecc_rmw_read  <= 1'b1;
+                			ecc_rmw_write <= 1'b0;
+					correct       <= 1'b0;
+					errcmd_ready  <= 1'b0;
+                			partial_opr   <= 1'b1;
+				end
+				else if (cfg_enable_rmw && int_ecc_read_final)
+				begin
+					ecc_state_sm  <= FULL_RD;	//4'h6
+					ecc_read      <= 1'b1;
+					ecc_write     <= 1'b0;
+					ecc_rmw_read  <= 1'b0;
+					ecc_rmw_write <= 1'b0;
+					correct       <= 1'b0;
+					errcmd_ready  <= 1'b0;
+					partial_opr   <= 1'b0;
+				end
+				else 
+				begin
+					ecc_state_sm  <= IDLE;
+					ecc_read      <= 1'b0;
+					ecc_write     <= 1'b0;
+                			ecc_rmw_read  <= 1'b0;
+                			ecc_rmw_write <= 1'b0;
+					correct       <= 1'b0;
+					errcmd_ready  <= 1'b0;
+                			partial_opr   <= 1'b0;
+				end
+			end
+			CORRECT_RD :
+                        begin
+				errcmd_ready <= 1'b0;
+				if (!queue_full)
+				begin
+					ecc_state_sm  <= CORRECT_WR;
+					ecc_read      <= 1'b0;
+					ecc_write     <= 1'b1;
+                			ecc_rmw_read  <= 1'b0;
+               	 			ecc_rmw_write <= 1'b1;
+					correct       <= 1'b1;
+					errcmd_ready  <= 1'b0;
+                			partial_opr   <= 1'b0;
+				end
+			end
+			CORRECT_WR :
+                        begin
+				if (!queue_full)
+				begin
+					if (cfg_enable_ecc && errcmd_valid)     
+                        		begin
+                        			ecc_state_sm  <= CORRECT_RD;
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b1;
+						errcmd_ready  <= 1'b1;
+                				partial_opr   <= 1'b0;
+                        		end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
+					begin
+						ecc_state_sm  <= FULL_WR;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b1;
+						ecc_rmw_read  <= 1'b0;
+						ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+						partial_opr   <= 1'b0;
+					end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
+					begin
+						ecc_state_sm  <= PARWR_RD;
+               	 				ecc_read      <= 1'b1;
+                				ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b1;
+					end
+					else if (cfg_enable_rmw && int_ecc_read_final)
+					begin
+						ecc_state_sm  <= FULL_RD;	//4'h6
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else 
+					begin
+						ecc_state_sm  <= IDLE;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+				end
+			end
+			PARWR_RD :
+                        begin
+				if (!queue_full)	     
+                        	begin
+                        		ecc_state_sm  <= PARWR_WR;	//4'h2
+					ecc_read      <= 1'b0;
+					ecc_write     <= 1'b1;
+                			ecc_rmw_read  <= 1'b0;
+                			ecc_rmw_write <= 1'b1;
+					correct       <= 1'b0;
+					errcmd_ready  <= 1'b0;
+                			partial_opr   <= 1'b1;
+				end
+			end
+			PARWR_WR :	//4'h2
+                        begin
+				if (!queue_full)
+				begin
+					if (cfg_enable_ecc && errcmd_valid)     
+                        		begin
+                        			ecc_state_sm  <= CORRECT_RD;
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b1;
+						errcmd_ready  <= 1'b1;
+                				partial_opr   <= 1'b0;
+                        		end	
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final) 
+					begin
+						ecc_state_sm  <= FULL_WR;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b1;
+                				ecc_rmw_read  <= 1'b0;
+               	 				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
+					begin
+						ecc_state_sm  <= PARWR_RD;
+               	 				ecc_read      <= 1'b1;
+                				ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b1;
+					end
+					else if (cfg_enable_rmw && int_ecc_read_final)
+					begin
+						ecc_state_sm  <= FULL_RD;	//4'h6
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else 
+					begin
+						ecc_state_sm  <= IDLE;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+				end
+			end
+			FULL_WR :	//4'h3
+                        begin
+				if (!queue_full)
+				begin
+					if (cfg_enable_ecc && errcmd_valid)     
+                        		begin
+                        			ecc_state_sm  <= CORRECT_RD;
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b1;
+						errcmd_ready  <= 1'b1;
+                				partial_opr   <= 1'b0;
+                        		end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final) 
+                        		begin
+						ecc_state_sm  <= PARWR_RD;
+               	 				ecc_read      <= 1'b1;
+                				ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b1;
+                        		end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final) 
+                        		begin
+						ecc_state_sm  <= FULL_WR;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b1;
+                				ecc_rmw_read  <= 1'b0;
+               	 				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+
+                        		end
+					else if (cfg_enable_rmw && int_ecc_read_final)
+					begin
+						ecc_state_sm  <= FULL_RD;	//4'h6
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else 
+					begin
+						ecc_state_sm  <= IDLE;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+				end
+			end
+			FULL_RD :	//4'h6
+                        begin
+				if (!queue_full)
+				begin
+					if (cfg_enable_ecc && errcmd_valid)     
+                        		begin
+                        			ecc_state_sm  <= CORRECT_RD;
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b1;
+						errcmd_ready  <= 1'b1;
+                				partial_opr   <= 1'b0;
+                        		end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
+					begin
+						ecc_state_sm  <= FULL_WR;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b1;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
+					begin
+						ecc_state_sm  <= PARWR_RD;
+               	 				ecc_read      <= 1'b1;
+                				ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b1;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b1;
+                        		end
+					else if (cfg_enable_rmw && int_ecc_read_final)
+					begin
+						ecc_state_sm  <= FULL_RD;	//4'h6
+						ecc_read      <= 1'b1;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+					else 
+					begin
+						ecc_state_sm  <= IDLE;
+						ecc_read      <= 1'b0;
+						ecc_write     <= 1'b0;
+                				ecc_rmw_read  <= 1'b0;
+                				ecc_rmw_write <= 1'b0;
+						correct       <= 1'b0;
+						errcmd_ready  <= 1'b0;
+                				partial_opr   <= 1'b0;
+					end
+				end
+			end
+			default :
+                        begin
+                                ecc_state_sm  <= IDLE;
+				ecc_read      <= 1'b0;
+				ecc_write     <= 1'b0;
+                		ecc_rmw_read  <= 1'b0;
+                		ecc_rmw_write <= 1'b0;
+				correct       <= 1'b0;
+				errcmd_ready  <= 1'b0;
+                		partial_opr   <= 1'b0;
+                        end
+		   endcase
+		end
+        end		
+
+        // for ECC usage only
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+		split_queue_load_open <= 1'b0;
+            end
+            else
+            begin
+		if (split_queue_load_for_avl) 
+		begin
+			split_queue_load_open <= int_split_write;	//set flag to indicate waiting for data_complete
+		end
+		else if (data_complete[0])
+		begin
+			split_queue_load_open <= 1'b0;	//clear flag to indicate data_complete has arrived
+		end
+            end
+        end
+        
+        // Delay cmd_gen command by one cycle
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+                int_ecc_cs_addr   <= 0;
+                int_ecc_bank_addr <= 0;
+                int_ecc_row_addr  <= 0;
+                int_ecc_col_addr  <= 0;
+                int_ecc_read      <= 0;
+                int_ecc_write     <= 0;
+                int_ecc_size      <= 0;
+                int_ecc_autopch   <= 0;
+                int_ecc_multicast <= 0;
+                int_ecc_priority  <= 0;
+                int_ecc_localid   <= 0;
+                int_ecc_dataid    <= 0;
+            end
+            else if (split_queue_load) // hold off the next command when ECC logic is busy
+	    begin
+                int_ecc_cs_addr   <= int_split_cs_addr;
+                int_ecc_bank_addr <= int_split_bank_addr;
+                int_ecc_row_addr  <= int_split_row_addr;
+                int_ecc_col_addr  <= int_split_col_addr;
+               	int_ecc_read      <= int_split_read_final;	//When data_id not ready, suppress load	
+		int_ecc_write     <= int_split_write_final;	//When data_id not ready, suppress load
+                int_ecc_size      <= int_split_size;
+                int_ecc_autopch   <= int_split_autopch;
+                int_ecc_multicast <= int_split_multicast;
+                int_ecc_priority  <= int_split_priority;
+                int_ecc_localid   <= int_split_localid;
+                
+                if (int_split_write)
+                begin
+                    int_ecc_dataid <= wdatap_free_id_dataid;
+                end
+                else
+                begin
+                    int_ecc_dataid <= rdatap_free_id_dataid;
+                end
+            end
+        end
+
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+		int_ecc_data_complete <= 0;
+		int_ecc_partial_be    <= 0;
+            end
+            else 
+	    begin
+		if (data_complete[0])
+		begin
+			int_ecc_data_complete <= data_complete[0];
+			int_ecc_partial_be    <= data_partial_be;
+		end
+		else if (split_queue_load_for_avl)
+		begin
+			int_ecc_data_complete <= 0;
+			int_ecc_partial_be    <= 0;
+		end
+            end
+        end
+       
+
+
+        // Buffer for ECC command information
+        always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+                ecc_cs_addr   <= 0;
+                ecc_bank_addr <= 0;
+                ecc_row_addr  <= 0;
+                ecc_col_addr  <= 0;
+                ecc_size      <= 0;
+                ecc_autopch   <= 0;
+                ecc_multicast <= 0;
+                ecc_dataid    <= 0;
+                ecc_localid   <= 0;
+                ecc_priority  <= 0;
+            end
+            else
+            begin
+                if (ecc_queue_load) //when queue take, load in new command
+						             //except when doing correction
+                begin
+                    ecc_cs_addr   <= take_from_ecc_correct ? errcmd_chipsel : int_ecc_cs_addr;
+                    ecc_bank_addr <= take_from_ecc_correct ? errcmd_bank    : int_ecc_bank_addr;
+                    ecc_row_addr  <= take_from_ecc_correct ? errcmd_row     : int_ecc_row_addr;
+                    ecc_col_addr  <= take_from_ecc_correct ? errcmd_column  : int_ecc_col_addr;
+                    ecc_size      <= take_from_ecc_correct ? errcmd_size    : int_ecc_size;
+                    ecc_autopch   <= take_from_ecc_correct ? 1'b0 	    : int_ecc_autopch;
+                    ecc_multicast <= take_from_ecc_correct ? 1'b0 	    : int_ecc_multicast;
+                    ecc_localid   <= take_from_ecc_correct ? 0 		    : int_ecc_localid;
+                    ecc_priority  <= take_from_ecc_correct ? errcmd_localid : int_ecc_priority;
+                    ecc_dataid    <= take_from_ecc_correct ? 1'b0 	    : int_ecc_dataid;
+                end
+		else	//on hold
+		begin
+                    ecc_cs_addr   <= ecc_cs_addr;
+                    ecc_bank_addr <= ecc_bank_addr;
+                    ecc_row_addr  <= ecc_row_addr;
+                    ecc_col_addr  <= ecc_col_addr;
+                    ecc_size      <= ecc_size;
+                    ecc_autopch   <= ecc_autopch;
+                    ecc_multicast <= ecc_multicast;
+                    ecc_localid   <= ecc_localid;
+                    ecc_priority  <= ecc_priority;
+                    ecc_dataid    <= ecc_dataid;
+                end
+            end
+        end
+
+	assign ecc_queue_load	        = (((ecc_state_sm == 4'b0000) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid)) ||
+					   ((ecc_state_sm == 4'b0011) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) || 
+				   	   ((ecc_state_sm == 4'b0110) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) ||
+					   ((ecc_state_sm == 4'b1000) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) ||
+					   ((ecc_state_sm == 4'b0010) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full)); 
+	
+	assign split_queue_load          = (split_queue_load_init || split_queue_load_ecc_load); 
+	assign split_queue_load_init     = (!int_ecc_read && !int_ecc_write && (int_split_read_final || int_split_write_final) && (ecc_state_sm != 4'h4) && (ecc_state_sm != 4'h1)); 
+	assign split_queue_load_ecc_load = (ecc_queue_load && (!take_from_ecc_correct));
+	assign split_queue_load_for_avl  = split_queue_load && (int_split_read_final || int_split_write_final);
+	assign int_split_read_final      = (int_split_read && rdatap_free_id_valid);
+	assign int_split_write_final     = (int_split_write && wdatap_free_id_valid);
+
+	assign split_queue_fast_unload   = data_complete[0] && split_queue_load_ecc_load;
+
+        assign int_ecc_data_complete_final = split_queue_fast_unload ? data_complete[0] : int_ecc_data_complete;
+	assign int_ecc_partial_be_final    = split_queue_fast_unload ? data_partial_be  : int_ecc_partial_be;
+
+	assign split_queue_load_open_final = split_queue_load_open && !data_complete[0];
+	assign int_ecc_read_final          = int_ecc_read  && !split_queue_load_open_final;
+	assign int_ecc_write_final         = int_ecc_write && !split_queue_load_open_final;
+
+        assign take_from_ecc_correct    = cfg_enable_ecc && errcmd_valid &&
+					  ((ecc_state_sm == 4'h0) ||
+ 					   ((ecc_state_sm == 4'h8) && !queue_full) ||
+ 					   ((ecc_state_sm == 4'h2) && !queue_full) ||
+ 					   ((ecc_state_sm == 4'h3) && !queue_full) ||
+ 					   ((ecc_state_sm == 4'h6) && !queue_full));
+
+        // ECC partial and correct information
+        always @ (*)
+            begin
+                ecc_correct = correct;
+                ecc_partial = partial_opr;
+            end
+        
+        // Waiting to load signal, indicate to TBP that we're about to load TBP but cmd_gen_load signal is not high
+        // this signal is required so that TBP will flush old contents in no-DM or ECC mode, else it'll cause in-efficiency
+        // in no-DM or ECC mode, we need to wait for write data to arrive before asserting read (partial write) or write (full write) request to TBP
+        // therefore TBP won't flush existing content in TBP because it didn't know command generator is about to load new command
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        waiting_to_load <= 1'b0;
+                    end
+                else
+                    begin
+                        if (tbp_full) // need to load when TBP is full, case:93272, avl_ready will stuck low if we keep all tbp slots with open page, this will free up at least one slot
+                            begin
+                                waiting_to_load <= 1'b1;
+                            end
+                        else
+                            begin
+                                waiting_to_load <= 1'b0;
+                            end
+                    end
+            end
+    //======================================================================================
+    //
+    //  [END] ECC related logic
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Mux Logic
+    //
+    //======================================================================================
+        assign mux_busy         = cfg_enable_rmw ? mux_busy_ecc : mux_busy_non_ecc;
+        assign mux_busy_non_ecc = queue_full;	
+	assign mux_busy_ecc     = (!split_queue_load_for_avl); 
+
+        assign  muxed_cs_addr           = (cfg_enable_rmw) ?  ecc_cs_addr           :  split_cs_addr;
+        assign  muxed_bank_addr         = (cfg_enable_rmw) ?  ecc_bank_addr         :  split_bank_addr;
+        assign  muxed_row_addr          = (cfg_enable_rmw) ?  ecc_row_addr          :  split_row_addr;
+        assign  muxed_col_addr          = (cfg_enable_rmw) ?  ecc_col_addr          :  split_col_addr;
+        assign  muxed_read              = (cfg_enable_rmw) ?  ecc_read              :  split_read;
+        assign  muxed_write             = (cfg_enable_rmw) ?  ecc_write             :  split_write;
+        assign  muxed_size              = (cfg_enable_rmw) ?  ecc_size              :  split_size;
+        assign  muxed_autopch           = (cfg_enable_rmw) ?  ecc_autopch           :  split_autopch;
+        assign  muxed_multicast         = (cfg_enable_rmw) ?  ecc_multicast         :  split_multicast;
+        assign  muxed_localid           = (cfg_enable_rmw) ?  ecc_localid           :  split_localid;
+        assign  muxed_priority          = (cfg_enable_rmw) ?  ecc_priority          :  split_priority;
+        assign  muxed_dataid            = (cfg_enable_rmw) ?  ecc_dataid            : (muxed_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
+        assign  muxed_complete          = (cfg_enable_rmw) ? !ecc_rmw_write         :  split_read; // Data is always complete for read command, therefore set it to split_read
+        assign  muxed_correct           = (cfg_enable_rmw) ?  ecc_correct           :  1'b0;
+        assign  muxed_partial           = (cfg_enable_rmw) ?  ecc_partial           :  1'b0;
+    //======================================================================================
+    //
+    //  [END] Mux Logic
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Queue Logic
+    //
+    //======================================================================================
+        // mapping of buffer_input
+        assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
+        
+        // avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
+        assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
+        assign fetch = cmd_gen_load & ~tbp_full;
+        
+        //pipefull and pipe register chain
+        //feed 0 to pipefull entry that is empty
+        always @(posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                    begin
+                        for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
+                            begin
+                                pipefull[j] <= 1'b0;
+                                pipe    [j] <= 0;
+                            end
+                    end
+                else
+                    begin
+                        if (fetch) // fetch and write
+                            begin
+                                        for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
+                                            begin
+                                                if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
+                                                    begin
+                                                        pipefull[j] <= write_to_queue;
+                                                        pipe    [j] <= buffer_input;
+                                                    end
+                                                else
+                                                    begin
+                                                        pipefull[j] <= pipefull[j+1];
+                                                        pipe    [j] <= pipe    [j+1];
+                                                    end
+                                            end
+                                        
+                                        pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
+                                        pipe    [CFG_CTL_QUEUE_DEPTH-1] <= pipe    [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
+                            end
+                        else if (write_to_queue) // write only
+                            begin
+                                        for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
+                                            begin
+                                                if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
+                                                    begin
+                                                        pipefull[j] <= 1'b1;
+                                                        pipe    [j] <= buffer_input;
+                                                    end
+                                            end
+                                        
+                                        if(pipefull[0] == 1'b0)
+                                            begin
+                                                pipefull[0] <= 1'b1;
+                                                pipe    [0] <= buffer_input;
+                                            end
+                            end
+                    end
+            end
+    //======================================================================================
+    //
+    //  [END] Queue Logic
+    //
+    //======================================================================================
+    
+    //======================================================================================
+    //
+    //  [START] Output Logic
+    //
+    //======================================================================================
+        generate
+                begin
+                    wire                                     int_queue_full;
+                    
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_chipsel_addr;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_bank_addr;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_row_addr_0;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_row_addr_1;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_row_addr_2;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_row_addr_3;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_col_addr;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_read_cmd;
+                    reg     [CFG_CTL_TBP_NUM-1:0]            int_same_write_cmd;
+                    
+                    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     int_same_shadow_chipsel_addr;
+                    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     int_same_shadow_bank_addr;
+                    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]     int_same_shadow_row_addr;
+                    
+                    reg                                      int_register_valid;
+                    
+                    reg     [CFG_MEM_IF_CS_WIDTH-1:0]        int_cmd_gen_chipsel;
+                    reg     [CFG_MEM_IF_BA_WIDTH-1:0]        int_cmd_gen_bank;
+                    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]       int_cmd_gen_row;
+                    reg     [CFG_MEM_IF_COL_WIDTH-1:0]       int_cmd_gen_col;
+                    reg                                      int_cmd_gen_write;
+                    reg                                      int_cmd_gen_read;
+                    reg                                      int_cmd_gen_multicast;
+                    reg     [CFG_INT_SIZE_WIDTH-1:0]         int_cmd_gen_size;
+                    reg     [CFG_LOCAL_ID_WIDTH-1:0]         int_cmd_gen_localid;
+                    reg     [CFG_DATA_ID_WIDTH-1:0]          int_cmd_gen_dataid;
+                    reg                                      int_cmd_gen_priority;
+                    reg                                      int_cmd_gen_rmw_correct;
+                    reg                                      int_cmd_gen_rmw_partial;
+                    reg                                      int_cmd_gen_autopch;
+                    reg                                      int_cmd_gen_complete;
+                    
+                    // TBP address and command comparison logic
+                    always @ (*)
+                        begin
+                            for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    // Chipselect address
+                                    if (int_cmd_gen_chipsel == chipsel[j])
+                                        begin
+                                            int_same_chipsel_addr[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_chipsel_addr[j] = 1'b0;
+                                        end
+                                    
+                                    // Bank addr
+                                    if (int_cmd_gen_bank == bank[j])
+                                        begin
+                                            int_same_bank_addr[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_bank_addr[j] = 1'b0;
+                                        end
+                                    
+                                    // Row addr
+                                    if (int_cmd_gen_row[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
+                                        begin
+                                            int_same_row_addr_0[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_row_addr_0[j] = 1'b0;
+                                        end
+                                    
+                                    if (int_cmd_gen_row[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
+                                        begin
+                                            int_same_row_addr_1[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_row_addr_1[j] = 1'b0;
+                                        end
+                                    
+                                    if (int_cmd_gen_row[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
+                                        begin
+                                            int_same_row_addr_2[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_row_addr_2[j] = 1'b0;
+                                        end
+                                    
+                                    if (int_cmd_gen_row[CFG_MEM_IF_ROW_WIDTH             - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH             - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
+                                        begin
+                                            int_same_row_addr_3[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_row_addr_3[j] = 1'b0;
+                                        end
+                                    
+                                    // Col addr
+                                    if (int_cmd_gen_col == col[j])
+                                        begin
+                                            int_same_col_addr[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_col_addr[j] = 1'b0;
+                                        end
+                                    
+                                    // Read command
+                                    if (int_cmd_gen_read == read[j])
+                                        begin
+                                            int_same_read_cmd[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_read_cmd[j] = 1'b0;
+                                        end
+                                    
+                                    // Write command
+                                    if (int_cmd_gen_write == write[j])
+                                        begin
+                                            int_same_write_cmd[j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            int_same_write_cmd[j] = 1'b0;
+                                        end
+                                end
+                        end
+                    
+                    // Shadow TBP address and command comparison logic
+                    always @ (*)
+                        begin
+                            for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    if (int_queue_full)
+                                        begin
+                                            // Chipselect address
+                                            if (int_cmd_gen_chipsel == shadow_chipsel[j])
+                                                begin
+                                                    int_same_shadow_chipsel_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_chipsel_addr[j] = 1'b0;
+                                                end
+                                            
+                                            // Bank addr
+                                            if (int_cmd_gen_bank == shadow_bank[j])
+                                                begin
+                                                    int_same_shadow_bank_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_bank_addr[j] = 1'b0;
+                                                end
+                                            
+                                            // Row addr
+                                            if (int_cmd_gen_row == shadow_row[j])
+                                                begin
+                                                    int_same_shadow_row_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_row_addr[j] = 1'b0;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            // Chipselect address
+                                            if (muxed_cs_addr == shadow_chipsel[j])
+                                                begin
+                                                    int_same_shadow_chipsel_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_chipsel_addr[j] = 1'b0;
+                                                end
+                                            
+                                            // Bank addr
+                                            if (muxed_bank_addr == shadow_bank[j])
+                                                begin
+                                                    int_same_shadow_bank_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_bank_addr[j] = 1'b0;
+                                                end
+                                            
+                                            // Row addr
+                                            if (muxed_row_addr == shadow_row[j])
+                                                begin
+                                                    int_same_shadow_row_addr[j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_same_shadow_row_addr[j] = 1'b0;
+                                                end
+                                        end
+                                end
+                        end
+                    
+                    assign int_queue_full = tbp_full | ((cmd_gen_read & ~rdatap_free_id_valid) | (cmd_gen_write & ~wdatap_free_id_valid));
+                    
+                    always @ (*)
+                        begin
+                            int_register_valid       = one;
+                            int_cmd_gen_read         = muxed_read;
+                            int_cmd_gen_write        = muxed_write;
+                            int_cmd_gen_multicast    = muxed_multicast;
+                            int_cmd_gen_autopch      = muxed_autopch;
+                            int_cmd_gen_priority     = muxed_priority;
+                            int_cmd_gen_complete     = muxed_complete;
+                            int_cmd_gen_rmw_correct  = muxed_correct;
+                            int_cmd_gen_rmw_partial  = muxed_partial;
+                            int_cmd_gen_dataid       = muxed_dataid;
+                            int_cmd_gen_localid      = muxed_localid;
+                            int_cmd_gen_size         = muxed_size;
+                            int_cmd_gen_chipsel      = muxed_cs_addr;
+                            int_cmd_gen_row          = muxed_row_addr;
+                            int_cmd_gen_bank         = muxed_bank_addr;
+                            int_cmd_gen_col          = muxed_col_addr;
+                        end
+                    
+                    always @ (*)
+                        begin
+                            same_chipsel_addr        = int_same_chipsel_addr;
+                            same_bank_addr           = int_same_bank_addr;
+                            same_row_addr            = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
+                            same_col_addr            = int_same_col_addr;
+                            same_read_cmd            = int_same_read_cmd;
+                            same_write_cmd           = int_same_write_cmd;
+                            
+                            same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
+                            same_shadow_bank_addr    = int_same_shadow_bank_addr;
+                            same_shadow_row_addr     = int_same_shadow_row_addr;
+                        end
+                    
+                    assign queue_full                       = int_queue_full;
+                    assign cmd_gen_load                     = (cmd_gen_read & rdatap_free_id_valid) | (cmd_gen_write & wdatap_free_id_valid);
+                    assign cmd_gen_waiting_to_load          = waiting_to_load;
+                    assign cmd_gen_read                     = int_cmd_gen_read;
+                    assign cmd_gen_write                    = int_cmd_gen_write;
+                    assign cmd_gen_multicast                = int_cmd_gen_multicast;
+                    assign cmd_gen_autopch                  = int_cmd_gen_autopch;
+                    assign cmd_gen_priority                 = int_cmd_gen_priority;
+                    assign cmd_gen_complete                 = int_cmd_gen_complete;
+                    assign cmd_gen_rmw_correct              = int_cmd_gen_rmw_correct;
+                    assign cmd_gen_rmw_partial              = int_cmd_gen_rmw_partial;
+                    assign cmd_gen_dataid                   = int_cmd_gen_dataid;
+                    assign cmd_gen_localid                  = int_cmd_gen_localid;
+                    assign cmd_gen_size                     = int_cmd_gen_size;
+                    assign cmd_gen_chipsel                  = int_cmd_gen_chipsel;
+                    assign cmd_gen_row                      = int_cmd_gen_row;
+                    assign cmd_gen_bank                     = int_cmd_gen_bank;
+                    assign cmd_gen_col                      = int_cmd_gen_col;
+                    assign cmd_gen_same_chipsel_addr        = same_chipsel_addr;
+                    assign cmd_gen_same_bank_addr           = same_bank_addr;
+                    assign cmd_gen_same_row_addr            = same_row_addr;
+                    assign cmd_gen_same_col_addr            = same_col_addr;
+                    assign cmd_gen_same_read_cmd            = same_read_cmd;
+                    assign cmd_gen_same_write_cmd           = same_write_cmd;
+                    assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
+                    assign cmd_gen_same_shadow_bank_addr    = same_shadow_bank_addr;
+                    assign cmd_gen_same_shadow_row_addr     = same_shadow_row_addr;
+                end
+        endgenerate
+    //======================================================================================
+    //
+    //  [END] Output Logic
+    //
+    //======================================================================================
+    
+    //----------------------------------------------------------------------------------------------------------------
+
+    function integer log2;
+        input [31:0] value;
+        integer i;
+        begin
+            log2 = 0;
+            
+            for(i = 0; 2**i < value; i = i + 1)
+                log2 = i + 1;
+        end
+    endfunction
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v
new file mode 100644
index 0000000..f9819a5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v
@@ -0,0 +1,2513 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_controller #
+	( parameter
+        // Local interface parameters
+        CFG_LOCAL_SIZE_WIDTH                                =   3,
+        CFG_LOCAL_ADDR_WIDTH                                =   32,
+        CFG_LOCAL_DATA_WIDTH                                =   80,            // Maximum DQ width of 40
+        CFG_LOCAL_ID_WIDTH                                  =   8,
+        CFG_LOCAL_IF_TYPE                                   =   "AVALON",
+        
+        // Memory interface parameters
+        CFG_MEM_IF_CHIP                                     =   2,
+        CFG_MEM_IF_CS_WIDTH                                 =   1,
+        CFG_MEM_IF_BA_WIDTH                                 =   3,
+        CFG_MEM_IF_ROW_WIDTH                                =   15,
+        CFG_MEM_IF_COL_WIDTH                                =   12,
+        CFG_MEM_IF_ADDR_WIDTH                               =   15,
+        CFG_MEM_IF_CKE_WIDTH                                =   2,
+        CFG_MEM_IF_ODT_WIDTH                                =   2,
+        CFG_MEM_IF_CLK_PAIR_COUNT                           =   2,
+        CFG_MEM_IF_DQ_WIDTH                                 =   40,
+        CFG_MEM_IF_DQS_WIDTH                                =   5,
+        CFG_MEM_IF_DM_WIDTH                                 =   5,
+        
+        // Controller parameters
+        CFG_DWIDTH_RATIO                                    =   2,
+        CFG_ODT_ENABLED                                     =   1,            // NOTICE: required?
+        CFG_OUTPUT_REGD                                     =   0,            // NOTICE: un-used and will be removed
+        CFG_CTL_TBP_NUM                                     =   4,
+        CFG_LPDDR2_ENABLED                                  =   0,
+        CFG_DATA_REORDERING_TYPE                            =   "INTER_BANK",
+        CFG_ECC_MULTIPLES_16_24_40_72                       =   1,
+        
+        // Data path buffer & fifo parameters
+        CFG_WRBUFFER_ADDR_WIDTH                             =   6,
+        CFG_RDBUFFER_ADDR_WIDTH                             =   10,
+        CFG_MAX_PENDING_RD_CMD                              =   16,
+        CFG_MAX_PENDING_WR_CMD                              =   8,
+        
+        // MMR port width
+        // cfg: general
+        CFG_PORT_WIDTH_TYPE                                 =   3,
+        CFG_PORT_WIDTH_INTERFACE_WIDTH                      =   8,
+        CFG_PORT_WIDTH_BURST_LENGTH                         =   5,
+        CFG_PORT_WIDTH_DEVICE_WIDTH                         =   4,
+        CFG_PORT_WIDTH_OUTPUT_REGD                          =   2,
+        
+        // cfg: address mapping signals
+        CFG_PORT_WIDTH_ADDR_ORDER                           =   2,
+        CFG_PORT_WIDTH_COL_ADDR_WIDTH                       =   5,
+        CFG_PORT_WIDTH_ROW_ADDR_WIDTH                       =   5,
+        CFG_PORT_WIDTH_BANK_ADDR_WIDTH                      =   3,
+        CFG_PORT_WIDTH_CS_ADDR_WIDTH                        =   3,
+        
+        // cfg: timing parameters                                                                                             
+        CFG_PORT_WIDTH_CAS_WR_LAT                           =   4,          // max will be 8 in DDR3
+        CFG_PORT_WIDTH_ADD_LAT                              =   3,          // max will be 10 in DDR3
+        CFG_PORT_WIDTH_TCL                                  =   4,          // max will be 11 in DDR3
+        CFG_PORT_WIDTH_TRRD                                 =   4,          // 2 - 8        enough?
+        CFG_PORT_WIDTH_TFAW                                 =   6,          // 6 - 32       enough?
+        CFG_PORT_WIDTH_TRFC                                 =   8,          // 12-140       enough?
+        CFG_PORT_WIDTH_TREFI                                =   13,         // 780 - 6240   enough?
+        CFG_PORT_WIDTH_TRCD                                 =   4,          // 2 - 11       enough?
+        CFG_PORT_WIDTH_TRP                                  =   4,          // 2 - 11       enough?
+        CFG_PORT_WIDTH_TWR                                  =   4,          // 2 - 12       enough?
+        CFG_PORT_WIDTH_TWTR                                 =   4,          // 1 - 10       enough?
+        CFG_PORT_WIDTH_TRTP                                 =   4,          // 2 - 8        enough?
+        CFG_PORT_WIDTH_TRAS                                 =   5,          // 4 - 29       enough?
+        CFG_PORT_WIDTH_TRC                                  =   6,          // 8 - 40       enough?
+        CFG_PORT_WIDTH_TCCD                                 =   4,          // max will be 8 in DDR3
+        CFG_PORT_WIDTH_TMRD                                 =   3,          // 4 - ?        enough?
+        CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES                =   10,         // max will be 512 in DDR3
+        CFG_PORT_WIDTH_PDN_EXIT_CYCLES                      =   4,          // 3 - ?        enough?
+        CFG_PORT_WIDTH_AUTO_PD_CYCLES                       =   16,         // enough?
+        CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES             =   4,          // enough?
+        CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                 =   4,          // enough?
+        
+        // cfg: extra timing parameters
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH              =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID         =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH              =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID         =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID       =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK   =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT        =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL          =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD             =   4,
+        
+        // cfg: control signals
+        CFG_PORT_WIDTH_REORDER_DATA                         =   1,
+        CFG_PORT_WIDTH_STARVE_LIMIT                         =   6,
+        CFG_PORT_WIDTH_USER_RFSH                            =   1,
+        CFG_PORT_WIDTH_SELF_RFSH                            =   1,
+        CFG_PORT_WIDTH_REGDIMM_ENABLE                       =   1,
+        CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT               =   1,
+        CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE               =   1,
+        CFG_ENABLE_CMD_SPLIT                                = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
+        CFG_ENABLE_WDATA_PATH_LATENCY                       =   0,
+        
+        // cfg: ecc signals
+        CFG_PORT_WIDTH_ENABLE_ECC                           =   1,
+        CFG_PORT_WIDTH_ENABLE_AUTO_CORR                     =   1,
+        CFG_PORT_WIDTH_GEN_SBE                              =   1,
+        CFG_PORT_WIDTH_GEN_DBE                              =   1,
+        CFG_PORT_WIDTH_ENABLE_INTR                          =   1,
+        CFG_PORT_WIDTH_MASK_SBE_INTR                        =   1,
+        CFG_PORT_WIDTH_MASK_DBE_INTR                        =   1,
+        CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR               =   1,
+        CFG_PORT_WIDTH_CLR_INTR                             =   1,
+        CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES           =   1,
+        CFG_PORT_WIDTH_ENABLE_NO_DM                         =   1,
+		CFG_ECC_DECODER_REG									=	1,
+        
+        // cfg: odt
+        CFG_PORT_WIDTH_WRITE_ODT_CHIP                       =   4,
+        CFG_PORT_WIDTH_READ_ODT_CHIP                        =   4,
+        
+        // cfg: ecc signals
+        STS_PORT_WIDTH_SBE_ERROR                            =   1,
+        STS_PORT_WIDTH_DBE_ERROR                            =   1,
+        STS_PORT_WIDTH_CORR_DROP_ERROR                      =   1,
+        STS_PORT_WIDTH_SBE_COUNT                            =   8,
+        STS_PORT_WIDTH_DBE_COUNT                            =   8,
+        STS_PORT_WIDTH_CORR_DROP_COUNT                      =   8,
+        
+        // PHY parameters
+        CFG_WLAT_BUS_WIDTH                                  =   4,
+        CFG_RRANK_BUS_WIDTH                                 =   1,
+        CFG_WRANK_BUS_WIDTH                                 =   1,
+        CFG_USE_SHADOW_REGS                                 =   0,
+        
+        // controller read data return mode
+        CFG_RDATA_RETURN_MODE                               = "PASSTHROUGH",
+		CFG_ERRCMD_FIFO_REG									= 0,
+
+	CFG_ENABLE_BURST_MERGE 				    = 0
+    )
+    (
+        // Clock and reset
+        ctl_clk,
+        ctl_reset_n,
+        
+        // Command channel
+        itf_cmd_ready,
+        itf_cmd_valid,
+        itf_cmd,
+        itf_cmd_address,
+        itf_cmd_burstlen,
+        itf_cmd_id,
+        itf_cmd_priority,
+        itf_cmd_autopercharge,
+        itf_cmd_multicast,
+        
+        // Write data channel
+        itf_wr_data_ready,
+        itf_wr_data_valid,
+        itf_wr_data,
+        itf_wr_data_byte_en,
+        itf_wr_data_begin,
+        itf_wr_data_last,
+        itf_wr_data_id,
+        
+        // Read data channel
+        itf_rd_data_ready,
+        itf_rd_data_valid,
+        itf_rd_data,
+        itf_rd_data_error,
+        itf_rd_data_begin,
+        itf_rd_data_last,
+        itf_rd_data_id,
+        itf_rd_data_id_early,                   // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
+        itf_rd_data_id_early_valid,             // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
+        
+        // Sideband signals
+        local_refresh_req,
+        local_refresh_chip,
+        local_zqcal_req,
+        local_zqcal_chip,
+        local_deep_powerdn_chip,
+        local_deep_powerdn_req,
+        local_self_rfsh_req,
+        local_self_rfsh_chip,
+        local_refresh_ack,
+        local_deep_powerdn_ack,
+        local_power_down_ack,
+        local_self_rfsh_ack,
+        local_init_done,
+        
+        // Controller commands to the AFI interface
+        afi_rst_n,
+        afi_ba,
+        afi_addr,
+        afi_cke,
+        afi_cs_n,
+        afi_ras_n,
+        afi_cas_n,
+        afi_we_n,
+        afi_odt,
+        
+        // Controller read and write data to the AFI interface
+        afi_wlat,
+        afi_dqs_burst,
+        afi_dm,
+        afi_wdata,
+        afi_wdata_valid,
+        afi_rdata_en,
+        afi_rdata_en_full,
+        afi_rrank,
+        afi_wrank,
+        afi_rdata,
+        afi_rdata_valid,
+        
+        // Status and control signal to the AFI interface
+        ctl_cal_success,
+        ctl_cal_fail,
+        ctl_cal_req,
+        ctl_init_req,
+        ctl_mem_clk_disable,
+        ctl_cal_byte_lane_sel_n,
+        
+        // cfg: general
+        cfg_type,
+        cfg_interface_width,    // not sure where this signal is used
+        cfg_burst_length,
+        cfg_device_width,       // not sure where this signal is used
+        cfg_output_regd,
+        
+        // cfg: address mapping signals
+        cfg_addr_order,
+        cfg_col_addr_width,
+        cfg_row_addr_width,
+        cfg_bank_addr_width,
+        cfg_cs_addr_width,
+        
+        // cfg: timing parameters
+        cfg_cas_wr_lat,
+        cfg_add_lat,
+        cfg_tcl,
+        cfg_trrd,
+        cfg_tfaw,
+        cfg_trfc,
+        cfg_trefi,
+        cfg_trcd,
+        cfg_trp,
+        cfg_twr,
+        cfg_twtr,
+        cfg_trtp,
+        cfg_tras,
+        cfg_trc,
+        cfg_tccd,
+        cfg_auto_pd_cycles,
+        cfg_self_rfsh_exit_cycles,
+        cfg_pdn_exit_cycles,
+        cfg_power_saving_exit_cycles,
+        cfg_mem_clk_entry_cycles,
+        cfg_tmrd,
+        
+        // cfg: extra timing parameters
+        cfg_extra_ctl_clk_act_to_rdwr,
+        cfg_extra_ctl_clk_act_to_pch,
+        cfg_extra_ctl_clk_act_to_act,
+        cfg_extra_ctl_clk_rd_to_rd,
+        cfg_extra_ctl_clk_rd_to_rd_diff_chip,
+        cfg_extra_ctl_clk_rd_to_wr,
+        cfg_extra_ctl_clk_rd_to_wr_bc,
+        cfg_extra_ctl_clk_rd_to_wr_diff_chip,
+        cfg_extra_ctl_clk_rd_to_pch,
+        cfg_extra_ctl_clk_rd_ap_to_valid,
+        cfg_extra_ctl_clk_wr_to_wr,
+        cfg_extra_ctl_clk_wr_to_wr_diff_chip,
+        cfg_extra_ctl_clk_wr_to_rd,
+        cfg_extra_ctl_clk_wr_to_rd_bc,
+        cfg_extra_ctl_clk_wr_to_rd_diff_chip,
+        cfg_extra_ctl_clk_wr_to_pch,
+        cfg_extra_ctl_clk_wr_ap_to_valid,
+        cfg_extra_ctl_clk_pch_to_valid,
+        cfg_extra_ctl_clk_pch_all_to_valid,
+        cfg_extra_ctl_clk_act_to_act_diff_bank,
+        cfg_extra_ctl_clk_four_act_to_act,
+        cfg_extra_ctl_clk_arf_to_valid,
+        cfg_extra_ctl_clk_pdn_to_valid,
+        cfg_extra_ctl_clk_srf_to_valid,
+        cfg_extra_ctl_clk_srf_to_zq_cal,
+        cfg_extra_ctl_clk_arf_period,
+        cfg_extra_ctl_clk_pdn_period,
+        
+        // cfg: control signals
+        cfg_reorder_data,       // enable data reordering
+        cfg_starve_limit,       // starvation counter limit
+        cfg_user_rfsh,
+        cfg_regdimm_enable,
+        cfg_enable_burst_interrupt,
+        cfg_enable_burst_terminate,
+        
+        // cfg: ecc signals
+        cfg_enable_ecc,
+        cfg_enable_auto_corr,
+        cfg_enable_ecc_code_overwrites,
+        cfg_enable_no_dm,
+        cfg_gen_sbe,
+        cfg_gen_dbe,
+        cfg_enable_intr,
+        cfg_mask_sbe_intr,
+        cfg_mask_dbe_intr,
+        cfg_mask_corr_dropped_intr,
+        cfg_clr_intr,
+        
+        // cfg: odt
+        cfg_write_odt_chip,
+        cfg_read_odt_chip,
+        
+        // sts: ecc signals
+        ecc_interrupt,
+        sts_sbe_error,
+        sts_dbe_error,
+        sts_corr_dropped,
+        sts_sbe_count,
+        sts_dbe_count,
+        sts_corr_dropped_count,
+        sts_err_addr,
+        sts_corr_dropped_addr,
+
+        //calibration
+        cfg_cal_req,
+        sts_cal_fail,
+        sts_cal_success,
+	
+	    // DQS enable tracking
+	    cfg_enable_dqs_tracking,  //enable DQS enable tracking support in controller
+	    afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
+	    afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
+	    afi_ctl_long_idle, // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
+
+        // Refresh controller
+        tbp_empty,
+        cmd_gen_busy,
+        sideband_in_refresh
+	
+    );
+
+// General parameters
+localparam CFG_ECC_BE_ALLLOW_RMW			   = 0;
+localparam CFG_MEM_IF_DQ_PER_DQS                           = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
+localparam CFG_INT_SIZE_WIDTH                              = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
+localparam CFG_CTL_QUEUE_DEPTH                             = 8;
+localparam CFG_ENABLE_QUEUE                                = 0;
+//localparam CFG_ENABLE_BURST_MERGE                          = 0;
+localparam CFG_CMD_GEN_OUTPUT_REG                          = 1;                 // only in effect when CFG_ENABLE_QUEUE is set to '0'
+localparam CFG_CTL_ARBITER_TYPE                            = "ROWCOL";
+localparam CFG_AFI_INTF_PHASE_NUM                          = 2;
+localparam CFG_ECC_DATA_WIDTH                              = CFG_MEM_IF_DQ_WIDTH  * CFG_DWIDTH_RATIO;
+localparam CFG_ECC_DM_WIDTH                                = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
+localparam CFG_ECC_CODE_WIDTH                              = 8;
+localparam CFG_ECC_MULTIPLES                               = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
+localparam CFG_PARTIAL_BE_PER_WORD_ENABLE                  = 1;
+localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG                 = 1;
+localparam CFG_DISABLE_PRIORITY                            = 1;
+localparam CFG_REG_GRANT                                   = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
+localparam CFG_REG_REQ                                     = 0;
+localparam CFG_RANK_TIMER_OUTPUT_REG                       = 1;
+localparam CFG_ECC_DEC_REG                                 = 1;
+localparam CFG_ECC_RDATA_REG                               = 1;
+localparam CFG_ECC_ENC_REG                                 = 1;
+localparam CFG_WDATA_REG                                   = CFG_ENABLE_WDATA_PATH_LATENCY;
+localparam CFG_DISABLE_READ_REODERING                      = 0;
+localparam CFG_ENABLE_SHADOW_TBP                           = 0;
+localparam CFG_CTL_SHADOW_TBP_NUM                          = CFG_CTL_TBP_NUM;    // similar to TBP number
+
+// Datapath buffer & fifo size calculation
+localparam CFG_MAX_PENDING_ERR_CMD                         = 8;                 // temporary
+
+localparam CFG_MAX_PENDING_RD_CMD_WIDTH                    = log2(CFG_MAX_PENDING_RD_CMD);
+localparam CFG_WRDATA_ID_WIDTH                             = log2(CFG_MAX_PENDING_WR_CMD);
+localparam CFG_ERRCMD_FIFO_ADDR_WIDTH                      = log2(CFG_MAX_PENDING_ERR_CMD);
+localparam CFG_RDDATA_ID_WIDTH                             = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
+localparam CFG_DATA_ID_WIDTH                               = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
+// to avoid -1
+localparam integer CFG_DATA_ID_REMAINDER                   = (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH) ? 0 : 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
+localparam CFG_WRDATA_VEC_ID_WIDTH                         = CFG_MAX_PENDING_WR_CMD;
+
+// AFI 
+localparam CFG_ADDR_RATE_RATIO                             = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
+localparam CFG_AFI_IF_FR_ADDR_WIDTH                        = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
+localparam CFG_DRAM_WLAT_GROUP                             = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
+localparam CFG_LOCAL_WLAT_GROUP                            = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
+
+// Derived timing parameters width
+localparam T_PARAM_ACT_TO_RDWR_WIDTH                                  = (CFG_DWIDTH_RATIO == 8) ? 3  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4; //case:234203
+localparam T_PARAM_ACT_TO_PCH_WIDTH                                   = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_ACT_TO_ACT_WIDTH                                   = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_RD_TO_RD_WIDTH                                     = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_RD_TO_WR_WIDTH                                     = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_RD_TO_WR_BC_WIDTH                                  = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_RD_TO_PCH_WIDTH                                    = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_RD_AP_TO_VALID_WIDTH                               = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_WR_TO_WR_WIDTH                                     = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_WR_TO_RD_WIDTH                                     = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_WR_TO_RD_BC_WIDTH                                  = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_WR_TO_PCH_WIDTH                                    = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_WR_AP_TO_VALID_WIDTH                               = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;      
+localparam T_PARAM_PCH_TO_VALID_WIDTH                                 = (CFG_DWIDTH_RATIO == 8) ? 3  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4; //case:234203
+localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH                             = (CFG_DWIDTH_RATIO == 8) ? 3  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4; //case:234203
+
+localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH                           = (CFG_DWIDTH_RATIO == 8) ? 2  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4;
+localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH                           = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;
+localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH                           = (CFG_DWIDTH_RATIO == 8) ? 2  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4;
+localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH                           = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;
+localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH                         = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;
+localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH                              = (CFG_DWIDTH_RATIO == 8) ? 4  : (CFG_DWIDTH_RATIO == 4) ? 5  : 6;
+localparam T_PARAM_ARF_TO_VALID_WIDTH                                 = (CFG_DWIDTH_RATIO == 8) ? 7  : (CFG_DWIDTH_RATIO == 4) ? 8  : 9;
+localparam T_PARAM_PDN_TO_VALID_WIDTH                                 = (CFG_DWIDTH_RATIO == 8) ? 3  : (CFG_DWIDTH_RATIO == 4) ? 3  : 4; //case:234203
+localparam T_PARAM_SRF_TO_VALID_WIDTH                                 = (CFG_DWIDTH_RATIO == 8) ? 8  : (CFG_DWIDTH_RATIO == 4) ? 9  : 10;
+localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH                                = (CFG_DWIDTH_RATIO == 8) ? 7  : (CFG_DWIDTH_RATIO == 4) ? 8  : 9;
+localparam T_PARAM_ARF_PERIOD_WIDTH                                   = (CFG_DWIDTH_RATIO == 8) ? 12 : (CFG_DWIDTH_RATIO == 4) ? 12 : 13; //case:234203
+localparam T_PARAM_PDN_PERIOD_WIDTH                                   = 17; //case:234203
+localparam T_PARAM_POWER_SAVING_EXIT_WIDTH                            = (CFG_DWIDTH_RATIO == 8) ? 3  : (CFG_DWIDTH_RATIO == 4) ? 2  : 3; //case:234203
+localparam T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH                         = (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES > 6) ? CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES : 5; //case:234203
+
+localparam integer CFG_DATAID_ARRAY_DEPTH                             = 2**CFG_DATA_ID_WIDTH;
+localparam integer CFG_WRDATA_ID_WIDTH_SQRD                           = 2**CFG_WRDATA_ID_WIDTH;
+
+// Clock and reset
+input  ctl_clk;
+input  ctl_reset_n;
+
+// Command channel
+output                                 itf_cmd_ready;
+input                                  itf_cmd_valid;
+input                                  itf_cmd;
+input  [CFG_LOCAL_ADDR_WIDTH  - 1 : 0] itf_cmd_address;
+input  [CFG_LOCAL_SIZE_WIDTH  - 1 : 0] itf_cmd_burstlen;
+input  [CFG_LOCAL_ID_WIDTH - 1 : 0]    itf_cmd_id;
+input                                  itf_cmd_priority;
+input                                  itf_cmd_autopercharge;
+input                                  itf_cmd_multicast;
+
+// Write data channel
+output                                    itf_wr_data_ready;
+input                                     itf_wr_data_valid;
+input  [CFG_LOCAL_DATA_WIDTH     - 1 : 0] itf_wr_data;
+input  [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
+input                                     itf_wr_data_begin;
+input                                     itf_wr_data_last;
+input  [CFG_LOCAL_ID_WIDTH       - 1 : 0] itf_wr_data_id;
+
+// Read data channel
+input                                 itf_rd_data_ready;
+output                                itf_rd_data_valid;
+output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
+output                                itf_rd_data_error;
+output                                itf_rd_data_begin;
+output                                itf_rd_data_last;
+output [CFG_LOCAL_ID_WIDTH   - 1 : 0] itf_rd_data_id;
+output [CFG_LOCAL_ID_WIDTH   - 1 : 0] itf_rd_data_id_early;
+output                                itf_rd_data_id_early_valid;
+
+// Sideband signals
+input                            local_refresh_req;
+input  [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
+input                            local_zqcal_req;
+input  [CFG_MEM_IF_CHIP - 1 : 0] local_zqcal_chip;
+input                            local_deep_powerdn_req;
+input  [CFG_MEM_IF_CHIP-1:0]     local_deep_powerdn_chip;
+input                            local_self_rfsh_req;
+input  [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
+output                           local_refresh_ack;
+output                           local_deep_powerdn_ack;
+output                           local_power_down_ack;
+output                           local_self_rfsh_ack;
+output                           local_init_done;
+
+// Controller commands to the AFI interface
+output [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_rst_n;
+output [(CFG_MEM_IF_BA_WIDTH   * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
+output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
+output [(CFG_MEM_IF_CKE_WIDTH  * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
+output [(CFG_MEM_IF_CHIP       * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
+output [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_ras_n;
+output [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_cas_n;
+output [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_we_n;
+output [(CFG_MEM_IF_ODT_WIDTH  * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
+
+// Controller read and write data to the AFI interface
+input  [CFG_WLAT_BUS_WIDTH                            - 1 : 0] afi_wlat;
+output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
+output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO        - 1 : 0] afi_dm;
+output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO        - 1 : 0] afi_wdata;
+output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
+output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
+output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
+output [CFG_RRANK_BUS_WIDTH                           - 1 : 0] afi_rrank;
+output [CFG_WRANK_BUS_WIDTH                           - 1 : 0] afi_wrank;
+input  [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO        - 1 : 0] afi_rdata;
+input  [CFG_DWIDTH_RATIO / 2                          - 1 : 0] afi_rdata_valid;
+
+// Status and control signal to the AFI interface
+input                                                     ctl_cal_success;
+input                                                     ctl_cal_fail;
+output                                                    ctl_cal_req;
+output                                                    ctl_init_req;
+output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP   - 1 : 0] ctl_cal_byte_lane_sel_n ;
+output [CFG_MEM_IF_CLK_PAIR_COUNT                - 1 : 0] ctl_mem_clk_disable;
+
+// cfg: general
+input  [CFG_PORT_WIDTH_TYPE            - 1 : 0] cfg_type;
+input  [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
+input  [CFG_PORT_WIDTH_BURST_LENGTH    - 1 : 0] cfg_burst_length;
+input  [CFG_PORT_WIDTH_DEVICE_WIDTH    - 1 : 0] cfg_device_width;
+input  [CFG_PORT_WIDTH_OUTPUT_REGD     - 1 : 0] cfg_output_regd;
+
+// cfg: address mapping signals
+input  [CFG_PORT_WIDTH_ADDR_ORDER      - 1 : 0] cfg_addr_order;
+input  [CFG_PORT_WIDTH_COL_ADDR_WIDTH  - 1 : 0] cfg_col_addr_width;
+input  [CFG_PORT_WIDTH_ROW_ADDR_WIDTH  - 1 : 0] cfg_row_addr_width;
+input  [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
+input  [CFG_PORT_WIDTH_CS_ADDR_WIDTH   - 1 : 0] cfg_cs_addr_width;
+
+// cfg: timing parameters
+input  [CFG_PORT_WIDTH_CAS_WR_LAT               - 1 : 0] cfg_cas_wr_lat;
+input  [CFG_PORT_WIDTH_ADD_LAT                  - 1 : 0] cfg_add_lat;
+input  [CFG_PORT_WIDTH_TCL                      - 1 : 0] cfg_tcl;
+input  [CFG_PORT_WIDTH_TRRD                     - 1 : 0] cfg_trrd;
+input  [CFG_PORT_WIDTH_TFAW                     - 1 : 0] cfg_tfaw;
+input  [CFG_PORT_WIDTH_TRFC                     - 1 : 0] cfg_trfc;
+input  [CFG_PORT_WIDTH_TREFI                    - 1 : 0] cfg_trefi;
+input  [CFG_PORT_WIDTH_TRCD                     - 1 : 0] cfg_trcd;
+input  [CFG_PORT_WIDTH_TRP                      - 1 : 0] cfg_trp;
+input  [CFG_PORT_WIDTH_TWR                      - 1 : 0] cfg_twr;
+input  [CFG_PORT_WIDTH_TWTR                     - 1 : 0] cfg_twtr;
+input  [CFG_PORT_WIDTH_TRTP                     - 1 : 0] cfg_trtp;
+input  [CFG_PORT_WIDTH_TRAS                     - 1 : 0] cfg_tras;
+input  [CFG_PORT_WIDTH_TRC                      - 1 : 0] cfg_trc;
+input  [CFG_PORT_WIDTH_TCCD                     - 1 : 0] cfg_tccd;
+input  [CFG_PORT_WIDTH_AUTO_PD_CYCLES           - 1 : 0] cfg_auto_pd_cycles;
+input  [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES    - 1 : 0] cfg_self_rfsh_exit_cycles;
+input  [CFG_PORT_WIDTH_PDN_EXIT_CYCLES          - 1 : 0] cfg_pdn_exit_cycles;
+input  [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
+input  [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES     - 1 : 0] cfg_mem_clk_entry_cycles;
+input  [CFG_PORT_WIDTH_TMRD                     - 1 : 0] cfg_tmrd;
+
+// cfg: extra timing parameters
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR          - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH           - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT           - 1 : 0] cfg_extra_ctl_clk_act_to_act;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD             - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR             - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC          - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH            - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID       - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR             - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD             - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC          - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH            - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID       - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID     - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT      - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL        - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD           - 1 : 0] cfg_extra_ctl_clk_arf_period;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD           - 1 : 0] cfg_extra_ctl_clk_pdn_period;
+
+// cfg: control signals
+input  [CFG_PORT_WIDTH_REORDER_DATA                 - 1 : 0] cfg_reorder_data;
+input  [CFG_PORT_WIDTH_STARVE_LIMIT                 - 1 : 0] cfg_starve_limit;
+input  [CFG_PORT_WIDTH_USER_RFSH                    - 1 : 0] cfg_user_rfsh;
+input  [CFG_PORT_WIDTH_REGDIMM_ENABLE               - 1 : 0] cfg_regdimm_enable;
+input  [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT       - 1 : 0] cfg_enable_burst_interrupt;
+input  [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE       - 1 : 0] cfg_enable_burst_terminate;
+
+// cfg: ecc signals
+input  [CFG_PORT_WIDTH_ENABLE_ECC                   - 1 : 0] cfg_enable_ecc;
+input  [CFG_PORT_WIDTH_ENABLE_AUTO_CORR             - 1 : 0] cfg_enable_auto_corr;
+input  [CFG_PORT_WIDTH_ENABLE_NO_DM                 - 1 : 0] cfg_enable_no_dm;
+input  [CFG_PORT_WIDTH_GEN_SBE                      - 1 : 0] cfg_gen_sbe;
+input  [CFG_PORT_WIDTH_GEN_DBE                      - 1 : 0] cfg_gen_dbe;
+input  [CFG_PORT_WIDTH_ENABLE_INTR                  - 1 : 0] cfg_enable_intr;
+input  [CFG_PORT_WIDTH_MASK_SBE_INTR                - 1 : 0] cfg_mask_sbe_intr;
+input  [CFG_PORT_WIDTH_MASK_DBE_INTR                - 1 : 0] cfg_mask_dbe_intr;
+input  [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR       - 1 : 0] cfg_mask_corr_dropped_intr;
+input  [CFG_PORT_WIDTH_CLR_INTR                     - 1 : 0] cfg_clr_intr;
+input  [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES   - 1 : 0] cfg_enable_ecc_code_overwrites;
+
+// cfg: odt
+input  [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
+input  [CFG_PORT_WIDTH_READ_ODT_CHIP  - 1 : 0] cfg_read_odt_chip;
+
+// sts: ecc signals
+output                                                 ecc_interrupt;
+output [STS_PORT_WIDTH_SBE_ERROR              - 1 : 0] sts_sbe_error;
+output [STS_PORT_WIDTH_DBE_ERROR              - 1 : 0] sts_dbe_error;
+output [STS_PORT_WIDTH_SBE_COUNT              - 1 : 0] sts_sbe_count;
+output [STS_PORT_WIDTH_DBE_COUNT              - 1 : 0] sts_dbe_count;
+output [CFG_LOCAL_ADDR_WIDTH                  - 1 : 0] sts_err_addr;
+output [STS_PORT_WIDTH_CORR_DROP_ERROR        - 1 : 0] sts_corr_dropped;
+output [STS_PORT_WIDTH_CORR_DROP_COUNT        - 1 : 0] sts_corr_dropped_count;
+output [CFG_LOCAL_ADDR_WIDTH                  - 1 : 0] sts_corr_dropped_addr;
+
+// calibration signals
+input                                                   cfg_cal_req;
+output                                                  sts_cal_fail;
+output                                                  sts_cal_success;
+
+// DQS enable tracking
+input   cfg_enable_dqs_tracking;
+output  [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
+input   [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
+output  [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
+
+output  tbp_empty;
+output  cmd_gen_busy;
+output  sideband_in_refresh;
+
+//==============================================================================
+//
+//  Wires
+//
+//==============================================================================
+    // alt_mem_ddrx_input_if
+    wire                                    itf_cmd_ready;
+    wire                                    itf_wr_data_ready;
+    wire                                    itf_rd_data_valid;
+    wire [CFG_LOCAL_DATA_WIDTH     - 1 : 0] itf_rd_data;
+    wire                                    itf_rd_data_error;
+    wire                                    itf_rd_data_begin;
+    wire                                    itf_rd_data_last;
+    wire [CFG_LOCAL_ID_WIDTH       - 1 : 0] itf_rd_data_id;
+    wire [CFG_LOCAL_ID_WIDTH       - 1 : 0] itf_rd_data_id_early;
+    wire                                    itf_rd_data_id_early_valid;
+    wire                                    cmd_valid;
+    wire [CFG_LOCAL_ADDR_WIDTH     - 1 : 0] cmd_address;
+    wire                                    cmd_write;
+    wire                                    cmd_read;
+    wire                                    cmd_multicast;
+    wire [CFG_LOCAL_SIZE_WIDTH     - 1 : 0] cmd_size;
+    wire                                    cmd_priority;
+    wire                                    cmd_autoprecharge;
+    wire [CFG_LOCAL_ID_WIDTH       - 1 : 0] cmd_id;
+    wire [CFG_LOCAL_DATA_WIDTH     - 1 : 0] write_data;
+    wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
+    wire                                    write_data_valid;
+    wire [CFG_LOCAL_ID_WIDTH       - 1 : 0] write_data_id;
+    wire                                    local_refresh_ack;
+    wire                                    local_deep_powerdn_ack;
+    wire                                    local_power_down_ack;
+    wire                                    local_self_rfsh_ack;
+    wire                                    local_init_done;
+    wire                                    rfsh_req;
+    wire [CFG_MEM_IF_CHIP          - 1 : 0] rfsh_chip;
+    wire                                    zqcal_req;
+    wire                                    deep_powerdn_req;
+    wire [CFG_MEM_IF_CHIP          - 1 : 0] deep_powerdn_chip;
+    wire                                    self_rfsh_req;
+    wire [CFG_MEM_IF_CHIP          - 1 : 0] self_rfsh_chip;
+    
+    // alt_mem_ddrx_cmd_gen
+    wire                                  cmd_gen_load;
+    wire                                  cmd_gen_waiting_to_load;
+    wire [CFG_MEM_IF_CS_WIDTH    - 1 : 0] cmd_gen_chipsel;
+    wire [CFG_MEM_IF_BA_WIDTH    - 1 : 0] cmd_gen_bank;
+    wire [CFG_MEM_IF_ROW_WIDTH   - 1 : 0] cmd_gen_row;
+    wire [CFG_MEM_IF_COL_WIDTH   - 1 : 0] cmd_gen_col;
+    wire                                  cmd_gen_write;
+    wire                                  cmd_gen_read;
+    wire                                  cmd_gen_multicast;
+    wire [CFG_INT_SIZE_WIDTH     - 1 : 0] cmd_gen_size;
+    wire [CFG_LOCAL_ID_WIDTH     - 1 : 0] cmd_gen_localid;
+    wire [CFG_DATA_ID_WIDTH      - 1 : 0] cmd_gen_dataid;
+    wire                                  cmd_gen_priority;
+    wire                                  cmd_gen_rmw_correct;
+    wire                                  cmd_gen_rmw_partial;
+    wire                                  cmd_gen_autopch;
+    wire                                  cmd_gen_complete;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_chipsel_addr;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_bank_addr;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_row_addr;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_col_addr;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_read_cmd;
+    wire [CFG_CTL_TBP_NUM        - 1 : 0] cmd_gen_same_write_cmd;
+    wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
+    wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
+    wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
+    wire                                  cmd_gen_full;
+    
+    // alt_mem_ddrx_tbp
+    wire                                                           tbp_full;
+    wire                                                           tbp_empty;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] row_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] act_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] pch_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] col_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] rd_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] wr_req;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_read;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_write;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_precharge;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_activate;
+    wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH)         - 1 : 0] tbp_chipsel;
+    wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH)         - 1 : 0] tbp_bank;
+    wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH)        - 1 : 0] tbp_row;
+    wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH)        - 1 : 0] tbp_col;
+    wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] tbp_shadow_chipsel;
+    wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] tbp_shadow_bank;
+    wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
+    wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH)          - 1 : 0] tbp_size;
+    wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH)          - 1 : 0] tbp_localid;
+    wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH)           - 1 : 0] tbp_dataid;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_ap;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_burst_chop;
+    wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM)             - 1 : 0] tbp_age;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_priority;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_rmw_correct;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_rmw_partial;
+    wire [CFG_MEM_IF_CHIP                                 - 1 : 0] tbp_bank_closed;
+    wire [CFG_MEM_IF_CHIP                                 - 1 : 0] tbp_timer_ready;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_load_index;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] tbp_load;
+    wire                                                           data_rmw_fetch;
+    
+    // alt_mem_ddrx_arbiter
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] row_grant;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] col_grant;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] act_grant;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] pch_grant;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] rd_grant;
+    wire [CFG_CTL_TBP_NUM                                 - 1 : 0] wr_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_row_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_col_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_act_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_pch_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_rd_grant;
+    wire [log2(CFG_CTL_TBP_NUM)                           - 1 : 0] log2_wr_grant;
+    wire                                                           or_row_grant;
+    wire                                                           or_col_grant;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_write;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_read;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_chop;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_burst_terminate;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_auto_precharge;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_correct;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_rmw_partial;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_activate;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_precharge;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_precharge_all;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_refresh;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_self_refresh;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_power_down;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_deep_pdown;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_do_zq_cal;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] arb_do_lmr;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] arb_to_chipsel;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] arb_to_chip;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] arb_to_bank;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
+    wire [CFG_LOCAL_ID_WIDTH                              - 1 : 0] arb_localid;
+    wire [CFG_DATA_ID_WIDTH                               - 1 : 0] arb_dataid;
+    wire [CFG_INT_SIZE_WIDTH                              - 1 : 0] arb_size;
+    
+    // alt_mem_ddrx_burst_gen
+
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write_combi;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read_combi;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop_combi;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate_combi;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate_combi;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge_combi;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip_combi;
+    wire [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size_combi;
+    wire                                                           bg_interrupt_ready_combi;
+
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_write;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_read;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_chop;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_burst_terminate;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_auto_precharge;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_correct;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_rmw_partial;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_activate;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_precharge;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_precharge_all;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_refresh;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_self_refresh;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_power_down;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_deep_pdown;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_do_zq_cal;
+    wire [CFG_AFI_INTF_PHASE_NUM                          - 1 : 0] bg_do_lmr;
+    wire                                                           bg_do_lmr_read = 0;
+    wire                                                           bg_do_refresh_1bank = 0;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP)      - 1 : 0] bg_to_chip;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
+    wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
+    wire                                                           bg_doing_write;
+    wire                                                           bg_doing_read;
+    wire                                                           bg_rdwr_data_valid;
+    wire                                                           bg_interrupt_ready;
+    wire [CFG_LOCAL_ID_WIDTH                              - 1 : 0] bg_localid;
+    wire [CFG_DATA_ID_WIDTH                               - 1 : 0] bg_dataid;
+    wire [CFG_RDDATA_ID_WIDTH                             - 1 : 0] bg_rddataid;
+    wire [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_size;
+    wire [CFG_INT_SIZE_WIDTH                              - 1 : 0] bg_effective_size;
+    wire [                                                  7 : 0] bg_to_lmr = 0;
+    
+    // alt_mem_ddrx_addr_cmd_wrap
+    wire [(CFG_MEM_IF_CKE_WIDTH  * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
+    wire [(CFG_MEM_IF_CHIP       * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
+    wire [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_ras_n;
+    wire [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_cas_n;
+    wire [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_we_n;
+    wire [(CFG_MEM_IF_BA_WIDTH   * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
+    wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
+    wire [(CFG_DWIDTH_RATIO / 2)                           - 1 : 0] afi_rst_n;
+    wire [(CFG_MEM_IF_ODT_WIDTH  * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
+    wire [CFG_AFI_IF_FR_ADDR_WIDTH                         - 1 : 0] lmr_opcode = 0;
+    
+    // alt_mem_ddrx_rdwr_data_tmg
+    wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2)                   - 1 : 0] afi_rdata_en;
+    wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2)                   - 1 : 0] afi_rdata_en_full;
+    wire [CFG_PORT_WIDTH_OUTPUT_REGD                                      - 1 : 0] cfg_output_regd_for_afi_output;
+    wire [CFG_DRAM_WLAT_GROUP                                             - 1 : 0] ecc_wdata_fifo_read;
+    wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH                         - 1 : 0] ecc_wdata_fifo_dataid;
+    wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH                    - 1 : 0] ecc_wdata_fifo_dataid_vector;
+    wire [CFG_DRAM_WLAT_GROUP                                             - 1 : 0] ecc_wdata_fifo_rmw_correct;
+    wire [CFG_DRAM_WLAT_GROUP                                             - 1 : 0] ecc_wdata_fifo_rmw_partial;
+    wire                                                                           ecc_wdata_fifo_read_first;
+    wire [CFG_DATA_ID_WIDTH                                               - 1 : 0] ecc_wdata_fifo_dataid_first;
+    wire [CFG_DATAID_ARRAY_DEPTH                                          - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
+    wire                                                                           ecc_wdata_fifo_rmw_correct_first;
+    wire                                                                           ecc_wdata_fifo_rmw_partial_first;
+    wire [CFG_DRAM_WLAT_GROUP                                             - 1 : 0] ecc_wdata_fifo_first_vector;
+    wire                                                                           ecc_wdata_fifo_read_last;
+    wire [CFG_DATA_ID_WIDTH                                               - 1 : 0] ecc_wdata_fifo_dataid_last;
+    wire [CFG_DATAID_ARRAY_DEPTH                                          - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
+    wire                                                                           ecc_wdata_fifo_rmw_correct_last;
+    wire                                                                           ecc_wdata_fifo_rmw_partial_last;
+    wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH                       - 1 : 0] ecc_wdata_wrdataid;
+    wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD                  - 1 : 0] ecc_wdata_wrdataid_vector;
+    wire [CFG_WRDATA_ID_WIDTH                                             - 1 : 0] ecc_wdata_wrdataid_first;
+    wire [CFG_WRDATA_ID_WIDTH_SQRD                                        - 1 : 0] ecc_wdata_wrdataid_vector_first;
+    wire [CFG_WRDATA_ID_WIDTH                                             - 1 : 0] ecc_wdata_wrdataid_last;
+    wire [CFG_WRDATA_ID_WIDTH_SQRD                                        - 1 : 0] ecc_wdata_wrdataid_vector_last;
+    wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_rrank;
+    wire [CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2) * CFG_MEM_IF_DQS_WIDTH - 1 : 0] int_afi_wrank;
+    wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2)                   - 1 : 0] afi_dqs_burst;
+    wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2)                   - 1 : 0] afi_wdata_valid;
+    wire [CFG_MEM_IF_DQ_WIDTH  * CFG_DWIDTH_RATIO                         - 1 : 0] afi_wdata;
+    wire [CFG_MEM_IF_DM_WIDTH  * CFG_DWIDTH_RATIO                         - 1 : 0] afi_dm;
+    
+    // alt_mem_ddrx_wdata_path
+    wire proc_busy;
+    wire proc_load;
+    wire proc_load_dataid;
+    wire proc_write;
+    wire proc_read;
+    wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
+    wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
+    wire                                                          wdatap_free_id_valid;
+    wire [CFG_DATA_ID_WIDTH                              - 1 : 0] wdatap_free_id_dataid;
+    wire [CFG_WRDATA_ID_WIDTH                            - 1 : 0] wdatap_free_id_wrdataid;
+    wire                                                          wr_data_mem_full;
+    wire [CFG_CTL_TBP_NUM                                - 1 : 0] data_complete;
+    wire                                                          data_rmw_complete;
+    wire                                                          data_partial_be;
+    wire [CFG_LOCAL_DATA_WIDTH                           - 1 : 0] wdatap_data;
+    wire [CFG_LOCAL_DATA_WIDTH                           - 1 : 0] wdatap_rmw_partial_data;
+    wire [CFG_LOCAL_DATA_WIDTH                           - 1 : 0] wdatap_rmw_correct_data;
+    wire                                                          wdatap_rmw_partial;
+    wire                                                          wdatap_rmw_correct;
+    wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
+    wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH         - 1 : 0] wdatap_ecc_code;
+    wire [CFG_ECC_MULTIPLES                              - 1 : 0] wdatap_ecc_code_overwrite;
+    
+    // alt_mem_ddrx_rdata_path
+    wire                                rdatap_free_id_valid;
+    wire [CFG_DATA_ID_WIDTH    - 1 : 0] rdatap_free_id_dataid;
+    wire [CFG_RDDATA_ID_WIDTH  - 1 : 0] rdatap_free_id_rddataid;
+    wire                                read_data_valid;
+    wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
+    wire                                read_data_error;
+    wire [CFG_LOCAL_ID_WIDTH   - 1 : 0] read_data_localid;
+    wire                                errcmd_ready;
+    wire                                errcmd_valid;
+    wire [CFG_MEM_IF_CS_WIDTH  - 1 : 0] errcmd_chipsel;
+    wire [CFG_MEM_IF_BA_WIDTH  - 1 : 0] errcmd_bank;
+    wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
+    wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
+    wire [CFG_INT_SIZE_WIDTH   - 1 : 0] errcmd_size;
+    wire [CFG_LOCAL_ID_WIDTH   - 1 : 0] errcmd_localid;
+    wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
+    wire                                rdatap_rcvd_cmd;
+    wire                                rdatap_rcvd_corr_dropped;
+    wire                                rmwfifo_data_valid; 
+    wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
+    wire [CFG_ECC_MULTIPLES                      - 1 : 0] rmwfifo_ecc_dbe;
+    wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
+    
+    // alt_mem_ddrx_ecc_encoder_decoder_wrapper
+    wire [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] ecc_rdata;
+    wire                                                  ecc_rdata_valid;
+    wire [CFG_ECC_DM_WIDTH                       - 1 : 0] ecc_dm;
+    wire [CFG_ECC_DATA_WIDTH                     - 1 : 0] ecc_wdata;
+    wire [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_sbe;
+    wire [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_dbe;
+    wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
+    wire                                                  ecc_interrupt;
+    wire [STS_PORT_WIDTH_SBE_ERROR               - 1 : 0] sts_sbe_error;
+    wire [STS_PORT_WIDTH_DBE_ERROR               - 1 : 0] sts_dbe_error;
+    wire [STS_PORT_WIDTH_SBE_COUNT               - 1 : 0] sts_sbe_count;
+    wire [STS_PORT_WIDTH_DBE_COUNT               - 1 : 0] sts_dbe_count;
+    wire [CFG_LOCAL_ADDR_WIDTH                   - 1 : 0] sts_err_addr;
+    wire [STS_PORT_WIDTH_CORR_DROP_ERROR         - 1 : 0] sts_corr_dropped;
+    wire [STS_PORT_WIDTH_CORR_DROP_COUNT         - 1 : 0] sts_corr_dropped_count;
+    wire [CFG_LOCAL_ADDR_WIDTH                   - 1 : 0] sts_corr_dropped_addr;
+    
+    // alt_mem_ddrx_sideband
+    wire                                       rfsh_ack;
+    wire                                       self_rfsh_ack;
+    wire                                       deep_powerdn_ack;
+    wire                                       power_down_ack;
+    wire                                       stall_row_arbiter;
+    wire                                       stall_col_arbiter;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   stall_chip;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_precharge_all;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_refresh;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_self_refresh;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_power_down;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_deep_pdown;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   sb_do_zq_cal;
+    wire [CFG_CTL_TBP_NUM           - 1 : 0]   sb_tbp_precharge_all;
+    wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0]   ctl_sb_mem_clk_disable;
+    wire                                       ctl_sb_cal_req;
+    wire                                       ctl_sb_init_req;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   afi_ctl_refresh_done;
+    wire [CFG_MEM_IF_CHIP           - 1 : 0]   afi_ctl_long_idle;
+    
+    // alt_mem_ddrx_rank_timer
+    wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
+    wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
+    wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
+    wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
+    
+    // alt_mem_ddrx_timing_param
+    wire [T_PARAM_ACT_TO_RDWR_WIDTH          - 1 : 0] t_param_act_to_rdwr;
+    wire [T_PARAM_ACT_TO_PCH_WIDTH           - 1 : 0] t_param_act_to_pch;
+    wire [T_PARAM_ACT_TO_ACT_WIDTH           - 1 : 0] t_param_act_to_act;
+    wire [T_PARAM_RD_TO_RD_WIDTH             - 1 : 0] t_param_rd_to_rd;
+    wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH   - 1 : 0] t_param_rd_to_rd_diff_chip;
+    wire [T_PARAM_RD_TO_WR_WIDTH             - 1 : 0] t_param_rd_to_wr;
+    wire [T_PARAM_RD_TO_WR_BC_WIDTH          - 1 : 0] t_param_rd_to_wr_bc;
+    wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH   - 1 : 0] t_param_rd_to_wr_diff_chip;
+    wire [T_PARAM_RD_TO_PCH_WIDTH            - 1 : 0] t_param_rd_to_pch;
+    wire [T_PARAM_RD_AP_TO_VALID_WIDTH       - 1 : 0] t_param_rd_ap_to_valid;
+    wire [T_PARAM_WR_TO_WR_WIDTH             - 1 : 0] t_param_wr_to_wr;
+    wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH   - 1 : 0] t_param_wr_to_wr_diff_chip;
+    wire [T_PARAM_WR_TO_RD_WIDTH             - 1 : 0] t_param_wr_to_rd;
+    wire [T_PARAM_WR_TO_RD_BC_WIDTH          - 1 : 0] t_param_wr_to_rd_bc;
+    wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH   - 1 : 0] t_param_wr_to_rd_diff_chip;
+    wire [T_PARAM_WR_TO_PCH_WIDTH            - 1 : 0] t_param_wr_to_pch;
+    wire [T_PARAM_WR_AP_TO_VALID_WIDTH       - 1 : 0] t_param_wr_ap_to_valid;
+    wire [T_PARAM_PCH_TO_VALID_WIDTH         - 1 : 0] t_param_pch_to_valid;
+    wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH     - 1 : 0] t_param_pch_all_to_valid;
+    wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
+    wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH      - 1 : 0] t_param_four_act_to_act;
+    wire [T_PARAM_ARF_TO_VALID_WIDTH         - 1 : 0] t_param_arf_to_valid;
+    wire [T_PARAM_PDN_TO_VALID_WIDTH         - 1 : 0] t_param_pdn_to_valid;
+    wire [T_PARAM_SRF_TO_VALID_WIDTH         - 1 : 0] t_param_srf_to_valid;
+    wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH        - 1 : 0] t_param_srf_to_zq_cal;
+    wire [T_PARAM_ARF_PERIOD_WIDTH           - 1 : 0] t_param_arf_period;
+    wire [T_PARAM_PDN_PERIOD_WIDTH           - 1 : 0] t_param_pdn_period;
+    wire [T_PARAM_POWER_SAVING_EXIT_WIDTH    - 1 : 0] t_param_power_saving_exit;
+    wire [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
+    
+    // General
+    wire init_done                                                                           = ctl_cal_success;
+    wire sts_cal_success                                                                     = ctl_cal_success;
+    wire sts_cal_fail                                                                        = ctl_cal_fail;
+    wire ctl_cal_req                                                                         = cfg_cal_req | ctl_sb_cal_req;
+    wire ctl_init_req                                                                        = ctl_sb_init_req;
+    wire [CFG_MEM_IF_CLK_PAIR_COUNT            - 1 : 0] ctl_mem_clk_disable                  = ctl_sb_mem_clk_disable;
+    wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n              = 0;
+	wire [CFG_RRANK_BUS_WIDTH                  - 1 : 0] afi_rrank                = CFG_USE_SHADOW_REGS ? int_afi_rrank[CFG_RRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
+	wire [CFG_WRANK_BUS_WIDTH                  - 1 : 0] afi_wrank                = CFG_USE_SHADOW_REGS ? int_afi_wrank[CFG_WRANK_BUS_WIDTH - 1:0] : {CFG_RRANK_BUS_WIDTH{1'b0}};
+    
+    // Log 2 function
+    function integer log2;
+       input [31:0] value;
+       integer    i;
+       begin
+          log2 = 0;
+          for(i = 0; 2**i < value; i = i + 1)
+       log2 = i + 1;
+       end
+    endfunction
+	
+	// register init_done signal
+	reg  init_done_reg;
+	always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            init_done_reg            <= 0;
+        end
+        else
+        begin
+            init_done_reg            <= init_done;
+        end
+    end
+    
+//==============================================================================
+// alt_mem_ddrx_input_if
+//------------------------------------------------------------------------------
+//
+//  Input interface block
+//
+//  Info: Includes cmd channel, and both read and write channels
+//        * Optional half-rate bridge logic
+//
+//==============================================================================
+    
+    alt_mem_ddrx_input_if #
+    (
+        .CFG_LOCAL_DATA_WIDTH          (CFG_LOCAL_DATA_WIDTH      ),
+        .CFG_LOCAL_ID_WIDTH            (CFG_LOCAL_ID_WIDTH        ),
+        .CFG_LOCAL_ADDR_WIDTH          (CFG_LOCAL_ADDR_WIDTH      ),
+        .CFG_LOCAL_SIZE_WIDTH          (CFG_LOCAL_SIZE_WIDTH      ),
+        .CFG_MEM_IF_CHIP               (CFG_MEM_IF_CHIP           ),
+        .CFG_AFI_INTF_PHASE_NUM        (CFG_AFI_INTF_PHASE_NUM    ),
+        .CFG_CTL_ARBITER_TYPE          (CFG_CTL_ARBITER_TYPE      )
+    )
+    input_if_inst
+    (
+        .itf_cmd_ready             (itf_cmd_ready              ),
+        .itf_cmd_valid             (itf_cmd_valid              ),
+        .itf_cmd                   (itf_cmd                    ),
+        .itf_cmd_address           (itf_cmd_address            ),
+        .itf_cmd_burstlen          (itf_cmd_burstlen           ),
+        .itf_cmd_id                (itf_cmd_id                 ),
+        .itf_cmd_priority          (itf_cmd_priority           ),
+        .itf_cmd_autopercharge     (itf_cmd_autopercharge      ),
+        .itf_cmd_multicast         (itf_cmd_multicast          ),
+        .itf_wr_data_ready         (itf_wr_data_ready          ),
+        .itf_wr_data_valid         (itf_wr_data_valid          ),
+        .itf_wr_data               (itf_wr_data                ),
+        .itf_wr_data_byte_en       (itf_wr_data_byte_en        ),
+        .itf_wr_data_begin         (itf_wr_data_begin          ),
+        .itf_wr_data_last          (itf_wr_data_last           ),
+        .itf_wr_data_id            (itf_wr_data_id             ),
+        .itf_rd_data_ready         (itf_rd_data_ready          ),
+        .itf_rd_data_valid         (itf_rd_data_valid          ),
+        .itf_rd_data               (itf_rd_data                ),
+        .itf_rd_data_error         (itf_rd_data_error          ),
+        .itf_rd_data_begin         (itf_rd_data_begin          ),
+        .itf_rd_data_last          (itf_rd_data_last           ),
+        .itf_rd_data_id            (itf_rd_data_id             ),
+        .itf_rd_data_id_early      (itf_rd_data_id_early       ),
+        .itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
+        .cmd_gen_full              (cmd_gen_full               ),
+        .cmd_valid                 (cmd_valid                  ),
+        .cmd_address               (cmd_address                ),
+        .cmd_write                 (cmd_write                  ),
+        .cmd_read                  (cmd_read                   ),
+        .cmd_multicast             (cmd_multicast              ),
+        .cmd_size                  (cmd_size                   ),
+        .cmd_priority              (cmd_priority               ),
+        .cmd_autoprecharge         (cmd_autoprecharge          ),
+        .cmd_id                    (cmd_id                     ),
+        .write_data                (write_data                 ),
+        .wr_data_mem_full          (wr_data_mem_full           ),
+        .write_data_id             (write_data_id              ),
+        .byte_en                   (byte_en                    ),
+        .write_data_valid          (write_data_valid           ),
+        .read_data                 (read_data                  ),
+        .read_data_valid           (read_data_valid            ),
+        .read_data_error           (read_data_error            ),
+        .read_data_localid         (read_data_localid          ),
+        .read_data_begin           (                           ),         // NOTICE: not connected?
+        .read_data_last            (                           ),         // NOTICE: not connected?
+        .bg_do_read                (bg_do_read                 ),
+        .bg_localid                (bg_localid                 ),
+        .bg_do_rmw_correct         (bg_do_rmw_correct          ),
+        .bg_do_rmw_partial         (bg_do_rmw_partial          ),
+        .local_refresh_req         (local_refresh_req          ),
+        .local_refresh_chip        (local_refresh_chip         ),
+        .local_zqcal_req           (local_zqcal_req            ),
+//        .local_zqcal_chip          (local_zqcal_chip           ),
+        .local_deep_powerdn_req    (local_deep_powerdn_req     ),
+        .local_deep_powerdn_chip   (local_deep_powerdn_chip    ),
+        .local_self_rfsh_req       (local_self_rfsh_req        ),
+        .local_self_rfsh_chip      (local_self_rfsh_chip       ),
+        .local_refresh_ack         (local_refresh_ack          ),
+        .local_deep_powerdn_ack    (local_deep_powerdn_ack     ),
+        .local_power_down_ack      (local_power_down_ack       ),
+        .local_self_rfsh_ack       (local_self_rfsh_ack        ),
+        .local_init_done           (local_init_done            ),
+        .rfsh_req                  (rfsh_req                   ),
+        .rfsh_chip                 (rfsh_chip                  ),
+        .zqcal_req                 (zqcal_req                  ),
+        .deep_powerdn_req          (deep_powerdn_req           ),
+        .deep_powerdn_chip         (deep_powerdn_chip          ),
+        .self_rfsh_req             (self_rfsh_req              ),
+        .self_rfsh_chip            (self_rfsh_chip             ),
+        .rfsh_ack                  (rfsh_ack                   ),
+        .deep_powerdn_ack          (deep_powerdn_ack           ),
+        .power_down_ack            (power_down_ack             ),
+        .self_rfsh_ack             (self_rfsh_ack              ),
+        .init_done                 (init_done_reg              )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_cmd_gen
+//------------------------------------------------------------------------------
+//
+//  Command generator block
+//
+//  Info: * generates cmd from local and internal ECC block
+//        * splitting and merging of all commands
+//        * optional queue for latency reduction purpose when no merging is required
+//
+//==============================================================================
+    
+    alt_mem_ddrx_cmd_gen #
+    (
+        .CFG_LOCAL_ADDR_WIDTH               (CFG_LOCAL_ADDR_WIDTH               ),
+        .CFG_LOCAL_SIZE_WIDTH               (CFG_LOCAL_SIZE_WIDTH               ),
+        .CFG_LOCAL_ID_WIDTH                 (CFG_LOCAL_ID_WIDTH                 ),
+        .CFG_INT_SIZE_WIDTH                 (CFG_INT_SIZE_WIDTH                 ),
+        .CFG_PORT_WIDTH_COL_ADDR_WIDTH      (CFG_PORT_WIDTH_COL_ADDR_WIDTH      ),
+        .CFG_PORT_WIDTH_ROW_ADDR_WIDTH      (CFG_PORT_WIDTH_ROW_ADDR_WIDTH      ),
+        .CFG_PORT_WIDTH_BANK_ADDR_WIDTH     (CFG_PORT_WIDTH_BANK_ADDR_WIDTH     ),
+        .CFG_PORT_WIDTH_CS_ADDR_WIDTH       (CFG_PORT_WIDTH_CS_ADDR_WIDTH       ),
+        .CFG_PORT_WIDTH_BURST_LENGTH        (CFG_PORT_WIDTH_BURST_LENGTH        ),
+        .CFG_PORT_WIDTH_ADDR_ORDER          (CFG_PORT_WIDTH_ADDR_ORDER          ),
+        .CFG_DWIDTH_RATIO                   (CFG_DWIDTH_RATIO                   ),
+        .CFG_CTL_QUEUE_DEPTH                (CFG_CTL_QUEUE_DEPTH                ),
+        .CFG_MEM_IF_CHIP                    (CFG_MEM_IF_CHIP                    ),
+        .CFG_MEM_IF_CS_WIDTH                (CFG_MEM_IF_CS_WIDTH                ),
+        .CFG_MEM_IF_BA_WIDTH                (CFG_MEM_IF_BA_WIDTH                ),
+        .CFG_MEM_IF_ROW_WIDTH               (CFG_MEM_IF_ROW_WIDTH               ),
+        .CFG_MEM_IF_COL_WIDTH               (CFG_MEM_IF_COL_WIDTH               ),
+        .CFG_DATA_ID_WIDTH                  (CFG_DATA_ID_WIDTH                  ),
+        .CFG_ENABLE_QUEUE                   (CFG_ENABLE_QUEUE                   ),
+        .CFG_ENABLE_BURST_MERGE             (CFG_ENABLE_BURST_MERGE             ),
+        .CFG_CMD_GEN_OUTPUT_REG             (CFG_CMD_GEN_OUTPUT_REG             ),
+        .CFG_CTL_TBP_NUM                    (CFG_CTL_TBP_NUM                    ),
+        .CFG_CTL_SHADOW_TBP_NUM             (CFG_CTL_SHADOW_TBP_NUM             )
+    )
+    cmd_gen_inst
+    (
+        .ctl_clk                            (ctl_clk                            ),
+        .ctl_reset_n                        (ctl_reset_n                        ),
+        .tbp_full                           (tbp_full                           ),
+        .tbp_load                           (tbp_load                           ),
+        .tbp_read                           (tbp_read                           ),
+        .tbp_write                          (tbp_write                          ),
+        .tbp_chipsel                        (tbp_chipsel                        ),
+        .tbp_bank                           (tbp_bank                           ),
+        .tbp_row                            (tbp_row                            ),
+        .tbp_col                            (tbp_col                            ),
+        .tbp_shadow_chipsel                 (tbp_shadow_chipsel                 ),
+        .tbp_shadow_bank                    (tbp_shadow_bank                    ),
+        .tbp_shadow_row                     (tbp_shadow_row                     ),
+        .cmd_gen_load                       (cmd_gen_load                       ),
+        .cmd_gen_waiting_to_load            (cmd_gen_waiting_to_load            ),
+        .cmd_gen_chipsel                    (cmd_gen_chipsel                    ),
+        .cmd_gen_bank                       (cmd_gen_bank                       ),
+        .cmd_gen_row                        (cmd_gen_row                        ),
+        .cmd_gen_col                        (cmd_gen_col                        ),
+        .cmd_gen_write                      (cmd_gen_write                      ),
+        .cmd_gen_read                       (cmd_gen_read                       ),
+        .cmd_gen_multicast                  (cmd_gen_multicast                  ),
+        .cmd_gen_size                       (cmd_gen_size                       ),
+        .cmd_gen_localid                    (cmd_gen_localid                    ),
+        .cmd_gen_dataid                     (cmd_gen_dataid                     ),
+        .cmd_gen_priority                   (cmd_gen_priority                   ),
+        .cmd_gen_rmw_correct                (cmd_gen_rmw_correct                ),
+        .cmd_gen_rmw_partial                (cmd_gen_rmw_partial                ),
+        .cmd_gen_autopch                    (cmd_gen_autopch                    ),
+        .cmd_gen_complete                   (cmd_gen_complete                   ),
+        .cmd_gen_same_chipsel_addr          (cmd_gen_same_chipsel_addr          ),
+        .cmd_gen_same_bank_addr             (cmd_gen_same_bank_addr             ),
+        .cmd_gen_same_row_addr              (cmd_gen_same_row_addr              ),
+        .cmd_gen_same_col_addr              (cmd_gen_same_col_addr              ),
+        .cmd_gen_same_read_cmd              (cmd_gen_same_read_cmd              ),
+        .cmd_gen_same_write_cmd             (cmd_gen_same_write_cmd             ),
+        .cmd_gen_same_shadow_chipsel_addr   (cmd_gen_same_shadow_chipsel_addr   ),
+        .cmd_gen_same_shadow_bank_addr      (cmd_gen_same_shadow_bank_addr      ),
+        .cmd_gen_same_shadow_row_addr       (cmd_gen_same_shadow_row_addr       ),
+        .cmd_gen_busy                       (cmd_gen_busy                       ),
+        .cmd_gen_full                       (cmd_gen_full                       ),
+        .cmd_valid                          (cmd_valid                          ),
+        .cmd_address                        (cmd_address                        ),
+        .cmd_write                          (cmd_write                          ),
+        .cmd_read                           (cmd_read                           ),
+        .cmd_id                             (cmd_id                             ),
+        .cmd_multicast                      (cmd_multicast                      ),
+        .cmd_size                           (cmd_size                           ),
+        .cmd_priority                       (cmd_priority                       ),
+        .cmd_autoprecharge                  (cmd_autoprecharge                  ),
+        .proc_busy                          (proc_busy                          ),
+        .proc_load                          (proc_load                          ),
+        .proc_load_dataid                   (proc_load_dataid                   ),
+        .proc_write                         (proc_write                         ),
+        .proc_read                          (proc_read                          ),
+        .proc_size                          (proc_size                          ),
+        .proc_localid                       (proc_localid                       ),
+        .wdatap_free_id_valid               (wdatap_free_id_valid               ),
+        .wdatap_free_id_dataid              (wdatap_free_id_dataid              ),
+        .rdatap_free_id_valid               (rdatap_free_id_valid               ),
+        .rdatap_free_id_dataid              (rdatap_free_id_dataid              ),
+        .tbp_load_index                     (tbp_load_index                     ),
+        .data_complete                      (data_complete                      ),
+        .data_rmw_complete                  (data_rmw_complete                  ),
+        .errcmd_ready                       (errcmd_ready                       ),
+        .errcmd_valid                       (errcmd_valid                       ),
+        .errcmd_chipsel                     (errcmd_chipsel                     ),
+        .errcmd_bank                        (errcmd_bank                        ),
+        .errcmd_row                         (errcmd_row                         ),
+        .errcmd_column                      (errcmd_column                      ),
+        .errcmd_size                        (errcmd_size                        ),
+        .errcmd_localid                     (errcmd_localid                     ),
+        .data_partial_be                    (data_partial_be                    ),
+        .cfg_enable_cmd_split               (CFG_ENABLE_CMD_SPLIT               ),
+        .cfg_burst_length                   (cfg_burst_length                   ),
+        .cfg_addr_order                     (cfg_addr_order                     ),
+        .cfg_enable_ecc                     (cfg_enable_ecc                     ),
+        .cfg_enable_no_dm                   (cfg_enable_no_dm                   ),
+        .cfg_col_addr_width                 (cfg_col_addr_width                 ),
+        .cfg_row_addr_width                 (cfg_row_addr_width                 ),
+        .cfg_bank_addr_width                (cfg_bank_addr_width                ),
+        .cfg_cs_addr_width                  (cfg_cs_addr_width                  )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_tbp
+//------------------------------------------------------------------------------
+//
+//  Timing bank pool block
+//
+//  Info: * parallel queue in which a cmd is present
+//        * tracks timer and bank status information of the command it hold
+//        * monitor other TBPs content to update status bit in itself such
+//          as the autoprecharge bit
+//	      * pass timer value to another TBP if need arises
+//
+//==============================================================================
+    
+    alt_mem_ddrx_tbp #
+    (
+        .CFG_CTL_TBP_NUM                        (CFG_CTL_TBP_NUM                        ),
+        .CFG_CTL_SHADOW_TBP_NUM                 (CFG_CTL_SHADOW_TBP_NUM                 ),
+        .CFG_ENABLE_SHADOW_TBP                  (CFG_ENABLE_SHADOW_TBP                  ),
+        .CFG_DWIDTH_RATIO                       (CFG_DWIDTH_RATIO                       ),
+        .CFG_CTL_ARBITER_TYPE                   (CFG_CTL_ARBITER_TYPE                   ),
+        .CFG_MEM_IF_CHIP                        (CFG_MEM_IF_CHIP                        ),
+        .CFG_MEM_IF_CS_WIDTH                    (CFG_MEM_IF_CS_WIDTH                    ),
+        .CFG_MEM_IF_BA_WIDTH                    (CFG_MEM_IF_BA_WIDTH                    ),
+        .CFG_MEM_IF_ROW_WIDTH                   (CFG_MEM_IF_ROW_WIDTH                   ),
+        .CFG_MEM_IF_COL_WIDTH                   (CFG_MEM_IF_COL_WIDTH                   ),
+        .CFG_LOCAL_ID_WIDTH                     (CFG_LOCAL_ID_WIDTH                     ),
+        .CFG_INT_SIZE_WIDTH                     (CFG_INT_SIZE_WIDTH                     ),
+        .CFG_DATA_ID_WIDTH                      (CFG_DATA_ID_WIDTH                      ),
+        .CFG_PORT_WIDTH_STARVE_LIMIT            (CFG_PORT_WIDTH_STARVE_LIMIT            ),
+        .CFG_PORT_WIDTH_TYPE                    (CFG_PORT_WIDTH_TYPE                    ),
+        .CFG_PORT_WIDTH_REORDER_DATA            (CFG_PORT_WIDTH_REORDER_DATA            ),
+        .CFG_REG_REQ                            (CFG_REG_REQ                            ),
+        .CFG_REG_GRANT                          (CFG_REG_GRANT                          ),
+        .CFG_DATA_REORDERING_TYPE               (CFG_DATA_REORDERING_TYPE               ),
+        .CFG_DISABLE_READ_REODERING             (CFG_DISABLE_READ_REODERING             ),
+        .CFG_DISABLE_PRIORITY                   (CFG_DISABLE_PRIORITY                   ),
+        .T_PARAM_ACT_TO_RDWR_WIDTH              (T_PARAM_ACT_TO_RDWR_WIDTH              ),
+        .T_PARAM_ACT_TO_ACT_WIDTH               (T_PARAM_ACT_TO_ACT_WIDTH               ),
+        .T_PARAM_ACT_TO_PCH_WIDTH               (T_PARAM_ACT_TO_PCH_WIDTH               ),
+        .T_PARAM_RD_TO_PCH_WIDTH                (T_PARAM_RD_TO_PCH_WIDTH                ),
+        .T_PARAM_WR_TO_PCH_WIDTH                (T_PARAM_WR_TO_PCH_WIDTH                ),
+        .T_PARAM_PCH_TO_VALID_WIDTH             (T_PARAM_PCH_TO_VALID_WIDTH             ),
+        .T_PARAM_RD_AP_TO_VALID_WIDTH           (T_PARAM_RD_AP_TO_VALID_WIDTH           ),
+        .T_PARAM_WR_AP_TO_VALID_WIDTH           (T_PARAM_WR_AP_TO_VALID_WIDTH           )
+    )
+    tbp_inst
+    (
+        .ctl_clk                                (ctl_clk                                ),
+        .ctl_reset_n                            (ctl_reset_n                            ),
+        .tbp_full                               (tbp_full                               ),
+        .tbp_empty                              (tbp_empty                              ),
+        .cmd_gen_load                           (cmd_gen_load                           ),
+        .cmd_gen_waiting_to_load                (cmd_gen_waiting_to_load                ),
+        .cmd_gen_chipsel                        (cmd_gen_chipsel                        ),
+        .cmd_gen_bank                           (cmd_gen_bank                           ),
+        .cmd_gen_row                            (cmd_gen_row                            ),
+        .cmd_gen_col                            (cmd_gen_col                            ),
+        .cmd_gen_write                          (cmd_gen_write                          ),
+        .cmd_gen_read                           (cmd_gen_read                           ),
+        .cmd_gen_size                           (cmd_gen_size                           ),
+        .cmd_gen_localid                        (cmd_gen_localid                        ),
+        .cmd_gen_dataid                         (cmd_gen_dataid                         ),
+        .cmd_gen_priority                       (cmd_gen_priority                       ),
+        .cmd_gen_rmw_correct                    (cmd_gen_rmw_correct                    ),
+        .cmd_gen_rmw_partial                    (cmd_gen_rmw_partial                    ),
+        .cmd_gen_autopch                        (cmd_gen_autopch                        ),
+        .cmd_gen_complete                       (cmd_gen_complete                       ),
+        .cmd_gen_same_chipsel_addr              (cmd_gen_same_chipsel_addr              ),
+        .cmd_gen_same_bank_addr                 (cmd_gen_same_bank_addr                 ),
+        .cmd_gen_same_row_addr                  (cmd_gen_same_row_addr                  ),
+        .cmd_gen_same_col_addr                  (cmd_gen_same_col_addr                  ),
+        .cmd_gen_same_read_cmd                  (cmd_gen_same_read_cmd                  ),
+        .cmd_gen_same_write_cmd                 (cmd_gen_same_write_cmd                 ),
+        .cmd_gen_same_shadow_chipsel_addr       (cmd_gen_same_shadow_chipsel_addr       ),
+        .cmd_gen_same_shadow_bank_addr          (cmd_gen_same_shadow_bank_addr          ),
+        .cmd_gen_same_shadow_row_addr           (cmd_gen_same_shadow_row_addr           ),
+        .row_req                                (row_req                                ),
+        .act_req                                (act_req                                ),
+        .pch_req                                (pch_req                                ),
+        .col_req                                (col_req                                ),
+        .rd_req                                 (rd_req                                 ),
+        .wr_req                                 (wr_req                                 ),
+        .row_grant                              (row_grant                              ),
+        .col_grant                              (col_grant                              ),
+        .act_grant                              (act_grant                              ),
+        .pch_grant                              (pch_grant                              ),
+        .rd_grant                               (rd_grant                               ),
+        .wr_grant                               (wr_grant                               ),
+        .log2_row_grant                         (log2_row_grant                         ),
+        .log2_col_grant                         (log2_col_grant                         ),
+        .log2_act_grant                         (log2_act_grant                         ),
+        .log2_pch_grant                         (log2_pch_grant                         ),
+        .log2_rd_grant                          (log2_rd_grant                          ),
+        .log2_wr_grant                          (log2_wr_grant                          ),
+        .or_row_grant                           (or_row_grant                           ),
+        .or_col_grant                           (or_col_grant                           ),
+        .tbp_read                               (tbp_read                               ),
+        .tbp_write                              (tbp_write                              ),
+        .tbp_precharge                          (tbp_precharge                          ),
+        .tbp_activate                           (tbp_activate                           ),
+        .tbp_chipsel                            (tbp_chipsel                            ),
+        .tbp_bank                               (tbp_bank                               ),
+        .tbp_row                                (tbp_row                                ),
+        .tbp_col                                (tbp_col                                ),
+        .tbp_shadow_chipsel                     (tbp_shadow_chipsel                     ),
+        .tbp_shadow_bank                        (tbp_shadow_bank                        ),
+        .tbp_shadow_row                         (tbp_shadow_row                         ),
+        .tbp_size                               (tbp_size                               ),
+        .tbp_localid                            (tbp_localid                            ),
+        .tbp_dataid                             (tbp_dataid                             ),
+        .tbp_ap                                 (tbp_ap                                 ),
+        .tbp_burst_chop                         (tbp_burst_chop                         ),
+        .tbp_age                                (tbp_age                                ),
+        .tbp_priority                           (tbp_priority                           ),
+        .tbp_rmw_correct                        (tbp_rmw_correct                        ),
+        .tbp_rmw_partial                        (tbp_rmw_partial                        ),
+        .sb_tbp_precharge_all                   (sb_tbp_precharge_all                   ),
+        .sb_do_precharge_all                    (sb_do_precharge_all                    ),
+        .t_param_act_to_rdwr                    (t_param_act_to_rdwr                    ),
+        .t_param_act_to_act                     (t_param_act_to_act                     ),
+        .t_param_act_to_pch                     (t_param_act_to_pch                     ),
+        .t_param_rd_to_pch                      (t_param_rd_to_pch                      ),
+        .t_param_wr_to_pch                      (t_param_wr_to_pch                      ),
+        .t_param_pch_to_valid                   (t_param_pch_to_valid                   ),
+        .t_param_rd_ap_to_valid                 (t_param_rd_ap_to_valid                 ),
+        .t_param_wr_ap_to_valid                 (t_param_wr_ap_to_valid                 ),
+        .tbp_bank_closed                        (tbp_bank_closed                        ),
+        .tbp_timer_ready                        (tbp_timer_ready                        ),
+        .cfg_reorder_data                       (cfg_reorder_data                       ),
+        .tbp_load                               (tbp_load                               ),
+        .data_complete                          (data_complete                          ),
+        .data_rmw_complete                      (data_rmw_complete                      ),
+        .data_rmw_fetch                         (data_rmw_fetch                         ),
+        .cfg_starve_limit                       (cfg_starve_limit                       ),
+        .cfg_type                               (cfg_type                               ),
+        .cfg_enable_ecc                         (cfg_enable_ecc                         ),
+        .cfg_enable_no_dm                       (cfg_enable_no_dm                       )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_arbiter
+//------------------------------------------------------------------------------
+//
+//  Arbiter block
+//
+//  Info: Priority command-aging arbiter, it will grant command with priority
+//        first, during tie-break situation, oldest command will be granted.
+//        Read comment in arbiter code for more information
+//
+//==============================================================================
+    
+    alt_mem_ddrx_arbiter #
+    (
+        .CFG_DWIDTH_RATIO           (CFG_DWIDTH_RATIO           ),
+        .CFG_CTL_TBP_NUM            (CFG_CTL_TBP_NUM            ),
+        .CFG_CTL_ARBITER_TYPE       (CFG_CTL_ARBITER_TYPE       ),
+        .CFG_REG_GRANT              (CFG_REG_GRANT              ),
+        .CFG_REG_REQ                (CFG_REG_REQ                ),
+        .CFG_MEM_IF_CHIP            (CFG_MEM_IF_CHIP            ),
+        .CFG_MEM_IF_CS_WIDTH        (CFG_MEM_IF_CS_WIDTH        ),
+        .CFG_MEM_IF_BA_WIDTH        (CFG_MEM_IF_BA_WIDTH        ),
+        .CFG_MEM_IF_ROW_WIDTH       (CFG_MEM_IF_ROW_WIDTH       ),
+        .CFG_MEM_IF_COL_WIDTH       (CFG_MEM_IF_COL_WIDTH       ),
+        .CFG_LOCAL_ID_WIDTH         (CFG_LOCAL_ID_WIDTH         ),
+        .CFG_DATA_ID_WIDTH          (CFG_DATA_ID_WIDTH          ),
+        .CFG_INT_SIZE_WIDTH         (CFG_INT_SIZE_WIDTH         ),
+        .CFG_AFI_INTF_PHASE_NUM     (CFG_AFI_INTF_PHASE_NUM     ),
+        .CFG_DISABLE_PRIORITY       (CFG_DISABLE_PRIORITY       )
+    )
+    arbiter_inst
+    (
+        .ctl_clk                    (ctl_clk                    ),
+        .ctl_reset_n                (ctl_reset_n                ),
+        .stall_row_arbiter          (stall_row_arbiter          ),
+        .stall_col_arbiter          (stall_col_arbiter          ),
+        .sb_do_precharge_all        (sb_do_precharge_all        ),
+        .sb_do_refresh              (sb_do_refresh              ),
+        .sb_do_self_refresh         (sb_do_self_refresh         ),
+        .sb_do_power_down           (sb_do_power_down           ),
+        .sb_do_deep_pdown           (sb_do_deep_pdown           ),
+        .sb_do_zq_cal               (sb_do_zq_cal               ),
+        .row_req                    (row_req                    ),
+        .col_req                    (col_req                    ),
+        .act_req                    (act_req                    ),
+        .pch_req                    (pch_req                    ),
+        .rd_req                     (rd_req                     ),
+        .wr_req                     (wr_req                     ),
+        .row_grant                  (row_grant                  ),
+        .col_grant                  (col_grant                  ),
+        .act_grant                  (act_grant                  ),
+        .pch_grant                  (pch_grant                  ),
+        .rd_grant                   (rd_grant                   ),
+        .wr_grant                   (wr_grant                   ),
+        .log2_row_grant             (log2_row_grant             ),
+        .log2_col_grant             (log2_col_grant             ),
+        .log2_act_grant             (log2_act_grant             ),
+        .log2_pch_grant             (log2_pch_grant             ),
+        .log2_rd_grant              (log2_rd_grant              ),
+        .log2_wr_grant              (log2_wr_grant              ),
+        .or_row_grant               (or_row_grant               ),
+        .or_col_grant               (or_col_grant               ),
+        .tbp_activate               (tbp_activate               ),
+        .tbp_precharge              (tbp_precharge              ),
+        .tbp_read                   (tbp_read                   ),
+        .tbp_write                  (tbp_write                  ),
+        .tbp_chipsel                (tbp_chipsel                ),
+        .tbp_bank                   (tbp_bank                   ),
+        .tbp_row                    (tbp_row                    ),
+        .tbp_col                    (tbp_col                    ),
+        .tbp_size                   (tbp_size                   ),
+        .tbp_localid                (tbp_localid                ),
+        .tbp_dataid                 (tbp_dataid                 ),
+        .tbp_ap                     (tbp_ap                     ),
+        .tbp_burst_chop             (tbp_burst_chop             ),
+        .tbp_rmw_correct            (tbp_rmw_correct            ),
+        .tbp_rmw_partial            (tbp_rmw_partial            ),
+        .tbp_age                    (tbp_age                    ),
+        .tbp_priority               (tbp_priority               ),
+        .can_activate               (can_activate               ),
+        .can_precharge              (can_precharge              ),
+        .can_write                  (can_write                  ),
+        .can_read                   (can_read                   ),
+        .arb_do_write               (arb_do_write               ),
+        .arb_do_read                (arb_do_read                ),
+        .arb_do_burst_chop          (arb_do_burst_chop          ),
+        .arb_do_burst_terminate     (arb_do_burst_terminate     ),
+        .arb_do_auto_precharge      (arb_do_auto_precharge      ),
+        .arb_do_rmw_correct         (arb_do_rmw_correct         ),
+        .arb_do_rmw_partial         (arb_do_rmw_partial         ),
+        .arb_do_activate            (arb_do_activate            ),
+        .arb_do_precharge           (arb_do_precharge           ),
+        .arb_do_precharge_all       (arb_do_precharge_all       ),
+        .arb_do_refresh             (arb_do_refresh             ),
+        .arb_do_self_refresh        (arb_do_self_refresh        ),
+        .arb_do_power_down          (arb_do_power_down          ),
+        .arb_do_deep_pdown          (arb_do_deep_pdown          ),
+        .arb_do_zq_cal              (arb_do_zq_cal              ),
+        .arb_do_lmr                 (arb_do_lmr                 ),
+        .arb_to_chipsel             (arb_to_chipsel             ),
+        .arb_to_chip                (arb_to_chip                ),
+        .arb_to_bank                (arb_to_bank                ),
+        .arb_to_row                 (arb_to_row                 ),
+        .arb_to_col                 (arb_to_col                 ),
+        .arb_localid                (arb_localid                ),
+        .arb_dataid                 (arb_dataid                 ),
+        .arb_size                   (arb_size                   )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_burst_gen
+//------------------------------------------------------------------------------
+//
+//  Burst generation block
+//
+//  Info: Create DQ/DQS burst information for AFI block
+//
+//==============================================================================
+    
+    alt_mem_ddrx_burst_gen #
+    (
+        .CFG_DWIDTH_RATIO                       (CFG_DWIDTH_RATIO                       ),
+        .CFG_CTL_ARBITER_TYPE                   (CFG_CTL_ARBITER_TYPE                   ),
+        .CFG_REG_GRANT                          (CFG_REG_GRANT                          ),
+        .CFG_MEM_IF_CHIP                        (CFG_MEM_IF_CHIP                        ),
+        .CFG_MEM_IF_CS_WIDTH                    (CFG_MEM_IF_CS_WIDTH                    ),
+        .CFG_MEM_IF_BA_WIDTH                    (CFG_MEM_IF_BA_WIDTH                    ),
+        .CFG_MEM_IF_ROW_WIDTH                   (CFG_MEM_IF_ROW_WIDTH                   ),
+        .CFG_MEM_IF_COL_WIDTH                   (CFG_MEM_IF_COL_WIDTH                   ),
+        .CFG_LOCAL_ID_WIDTH                     (CFG_LOCAL_ID_WIDTH                     ),
+        .CFG_DATA_ID_WIDTH                      (CFG_DATA_ID_WIDTH                      ),
+        .CFG_INT_SIZE_WIDTH                     (CFG_INT_SIZE_WIDTH                     ),
+        .CFG_AFI_INTF_PHASE_NUM                 (CFG_AFI_INTF_PHASE_NUM                 ),
+        .CFG_PORT_WIDTH_TYPE                    (CFG_PORT_WIDTH_TYPE                    ),
+        .CFG_PORT_WIDTH_BURST_LENGTH            (CFG_PORT_WIDTH_BURST_LENGTH            ),
+        .CFG_PORT_WIDTH_TCCD                    (CFG_PORT_WIDTH_TCCD                    ),
+        .CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT  (CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT  ),
+        .CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE  (CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE  ),
+        .CFG_ENABLE_BURST_GEN_OUTPUT_REG        (CFG_ENABLE_BURST_GEN_OUTPUT_REG        )
+    )
+    burst_gen_inst
+    (
+        .ctl_clk                                (ctl_clk                                ),
+        .ctl_reset_n                            (ctl_reset_n                            ),
+        .cfg_type                               (cfg_type                               ),
+        .cfg_burst_length                       (cfg_burst_length                       ),
+        .cfg_tccd                               (cfg_tccd                               ),
+        .cfg_enable_burst_interrupt             (cfg_enable_burst_interrupt             ),
+        .cfg_enable_burst_terminate             (cfg_enable_burst_terminate             ),
+        .arb_do_write                           (arb_do_write                           ),
+        .arb_do_read                            (arb_do_read                            ),
+        .arb_do_burst_chop                      (arb_do_burst_chop                      ),
+        .arb_do_burst_terminate                 (arb_do_burst_terminate                 ),
+        .arb_do_auto_precharge                  (arb_do_auto_precharge                  ),
+        .arb_do_rmw_correct                     (arb_do_rmw_correct                     ),
+        .arb_do_rmw_partial                     (arb_do_rmw_partial                     ),
+        .arb_do_activate                        (arb_do_activate                        ),
+        .arb_do_precharge                       (arb_do_precharge                       ),
+        .arb_do_precharge_all                   (arb_do_precharge_all                   ),
+        .arb_do_refresh                         (arb_do_refresh                         ),
+        .arb_do_self_refresh                    (arb_do_self_refresh                    ),
+        .arb_do_power_down                      (arb_do_power_down                      ),
+        .arb_do_deep_pdown                      (arb_do_deep_pdown                      ),
+        .arb_do_zq_cal                          (arb_do_zq_cal                          ),
+        .arb_do_lmr                             (arb_do_lmr                             ),
+        .arb_to_chipsel                         (arb_to_chipsel                         ),
+        .arb_to_chip                            (arb_to_chip                            ),
+        .arb_to_bank                            (arb_to_bank                            ),
+        .arb_to_row                             (arb_to_row                             ),
+        .arb_to_col                             (arb_to_col                             ),
+        .arb_localid                            (arb_localid                            ),
+        .arb_dataid                             (arb_dataid                             ),
+        .arb_size                               (arb_size                               ),
+        .bg_do_write_combi                      (bg_do_write_combi                      ),
+        .bg_do_read_combi                       (bg_do_read_combi                       ),
+        .bg_do_burst_chop_combi                 (bg_do_burst_chop_combi                 ),
+        .bg_do_burst_terminate_combi            (bg_do_burst_terminate_combi            ),
+        .bg_do_activate_combi                   (bg_do_activate_combi                   ),
+        .bg_do_precharge_combi                  (bg_do_precharge_combi                  ),
+        .bg_to_chip_combi                       (bg_to_chip_combi                       ),
+        .bg_effective_size_combi                (bg_effective_size_combi                ),
+        .bg_interrupt_ready_combi               (bg_interrupt_ready_combi               ),
+        .bg_do_write                            (bg_do_write                            ),
+        .bg_do_read                             (bg_do_read                             ),
+        .bg_do_burst_chop                       (bg_do_burst_chop                       ),
+        .bg_do_burst_terminate                  (bg_do_burst_terminate                  ),
+        .bg_do_auto_precharge                   (bg_do_auto_precharge                   ),
+        .bg_do_rmw_correct                      (bg_do_rmw_correct                      ),
+        .bg_do_rmw_partial                      (bg_do_rmw_partial                      ),
+        .bg_do_activate                         (bg_do_activate                         ),
+        .bg_do_precharge                        (bg_do_precharge                        ),
+        .bg_do_precharge_all                    (bg_do_precharge_all                    ),
+        .bg_do_refresh                          (bg_do_refresh                          ),
+        .bg_do_self_refresh                     (bg_do_self_refresh                     ),
+        .bg_do_power_down                       (bg_do_power_down                       ),
+        .bg_do_deep_pdown                       (bg_do_deep_pdown                       ),
+        .bg_do_zq_cal                           (bg_do_zq_cal                           ),
+        .bg_do_lmr                              (bg_do_lmr                              ),
+        .bg_to_chipsel                          (bg_to_chipsel                          ),
+        .bg_to_chip                             (bg_to_chip                             ),
+        .bg_to_bank                             (bg_to_bank                             ),
+        .bg_to_row                              (bg_to_row                              ),
+        .bg_to_col                              (bg_to_col                              ),
+        .bg_doing_write                         (bg_doing_write                         ),
+        .bg_doing_read                          (bg_doing_read                          ),
+        .bg_rdwr_data_valid                     (bg_rdwr_data_valid                     ),
+        .bg_interrupt_ready                     (bg_interrupt_ready                     ),
+        .bg_localid                             (bg_localid                             ),
+        .bg_dataid                              (bg_dataid                              ),
+        .bg_size                                (bg_size                                ),
+        .bg_effective_size                      (bg_effective_size                      )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_addr_cmd_wrap
+//------------------------------------------------------------------------------
+//
+//  Address and command decoder block
+//
+//  Info: Trasalate controller internal command into AFI command
+//
+//==============================================================================
+    
+    // wire [CFG_MEM_IF_CHIP      - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP      - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP      - 1 : CFG_MEM_IF_CHIP     ];
+    // wire [CFG_MEM_IF_BA_WIDTH  - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH  - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH  - 1 : CFG_MEM_IF_BA_WIDTH ];
+    // wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row  = bg_to_row  [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row  [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
+    // wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col  = bg_to_col  [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col  [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
+    // 
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh       = bg_do_refresh       [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh       [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down    = bg_do_power_down    [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down    [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh  = bg_do_self_refresh  [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh  [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown    = bg_do_deep_pdown    [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown    [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    // wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal        = bg_do_zq_cal        [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal        [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+    
+    alt_mem_ddrx_addr_cmd_wrap #
+    (
+        .CFG_MEM_IF_CHIP                (CFG_MEM_IF_CHIP                ),
+        .CFG_MEM_IF_CKE_WIDTH           (CFG_MEM_IF_CKE_WIDTH           ),
+        .CFG_MEM_IF_ADDR_WIDTH          (CFG_AFI_IF_FR_ADDR_WIDTH       ),
+        .CFG_MEM_IF_ROW_WIDTH           (CFG_MEM_IF_ROW_WIDTH           ),
+        .CFG_MEM_IF_COL_WIDTH           (CFG_MEM_IF_COL_WIDTH           ),
+        .CFG_MEM_IF_BA_WIDTH            (CFG_MEM_IF_BA_WIDTH            ),
+        .CFG_LPDDR2_ENABLED             (CFG_LPDDR2_ENABLED             ),
+        .CFG_DWIDTH_RATIO               (CFG_DWIDTH_RATIO               ),
+        .CFG_ODT_ENABLED                (CFG_ODT_ENABLED                ),
+        .CFG_MEM_IF_ODT_WIDTH           (CFG_MEM_IF_ODT_WIDTH           ),
+        .CFG_AFI_INTF_PHASE_NUM         (CFG_AFI_INTF_PHASE_NUM         ),
+        .CFG_LOCAL_ID_WIDTH             (CFG_LOCAL_ID_WIDTH             ),
+        .CFG_DATA_ID_WIDTH              (CFG_DATA_ID_WIDTH              ),
+        .CFG_INT_SIZE_WIDTH             (CFG_INT_SIZE_WIDTH             ),
+        .CFG_PORT_WIDTH_TYPE            (CFG_PORT_WIDTH_TYPE            ),
+        .CFG_PORT_WIDTH_CAS_WR_LAT      (CFG_PORT_WIDTH_CAS_WR_LAT      ),
+        .CFG_PORT_WIDTH_TCL             (CFG_PORT_WIDTH_TCL             ),
+        .CFG_PORT_WIDTH_ADD_LAT         (CFG_PORT_WIDTH_ADD_LAT         ),
+        .CFG_PORT_WIDTH_WRITE_ODT_CHIP  (CFG_PORT_WIDTH_WRITE_ODT_CHIP  ),
+        .CFG_PORT_WIDTH_READ_ODT_CHIP   (CFG_PORT_WIDTH_READ_ODT_CHIP   ),
+        .CFG_PORT_WIDTH_OUTPUT_REGD     (CFG_PORT_WIDTH_OUTPUT_REGD     )
+    )
+    addr_cmd_wrap_inst
+    (
+        .ctl_clk                        (ctl_clk                        ),
+        .ctl_reset_n                    (ctl_reset_n                    ),
+        .ctl_cal_success                (ctl_cal_success                ),
+        .cfg_type                       (cfg_type                       ),
+        .cfg_tcl                        (cfg_tcl                        ),
+        .cfg_cas_wr_lat                 (cfg_cas_wr_lat                 ),
+        .cfg_add_lat                    (cfg_add_lat                    ),
+        .cfg_write_odt_chip             (cfg_write_odt_chip             ),
+        .cfg_read_odt_chip              (cfg_read_odt_chip              ),
+        .cfg_burst_length               (cfg_burst_length               ),
+        .cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
+        .bg_do_write                    (bg_do_write                    ),      
+        .bg_do_read                     (bg_do_read                     ),      
+        .bg_do_auto_precharge           (bg_do_auto_precharge           ),      
+        .bg_do_burst_chop               (bg_do_burst_chop               ),      
+        .bg_do_activate                 (bg_do_activate                 ),      
+        .bg_do_precharge                (bg_do_precharge                ),      
+        .bg_do_refresh                  (bg_do_refresh                  ),      
+        .bg_do_power_down               (bg_do_power_down               ),      
+        .bg_do_self_refresh             (bg_do_self_refresh             ),      
+        .bg_do_rmw_correct              (bg_do_rmw_correct              ),      
+        .bg_do_rmw_partial              (bg_do_rmw_partial              ),      
+        .bg_do_lmr                      (bg_do_lmr                      ),      
+        .bg_do_precharge_all            (bg_do_precharge_all            ),      
+        .bg_do_zq_cal                   (bg_do_zq_cal                   ),      
+        .bg_do_lmr_read                 (bg_do_lmr_read                 ),
+        .bg_do_refresh_1bank            (bg_do_refresh_1bank            ),
+        .bg_do_burst_terminate          (bg_do_burst_terminate          ),      
+        .bg_do_deep_pdown               (bg_do_deep_pdown               ),      
+        .bg_to_chip                     (bg_to_chip                     ),      
+        .bg_to_bank                     (bg_to_bank                     ),      
+        .bg_to_row                      (bg_to_row                      ),      
+        .bg_to_col                      (bg_to_col                      ),      
+        .bg_to_lmr                      (bg_to_lmr                      ),
+        .bg_dataid                      (bg_dataid                      ),
+        .bg_localid                     (bg_localid                     ),
+        .bg_size                        (bg_size                        ),
+        .lmr_opcode                     (lmr_opcode                     ),
+        .afi_cke                        (afi_cke                        ),
+        .afi_cs_n                       (afi_cs_n                       ),
+        .afi_ras_n                      (afi_ras_n                      ),
+        .afi_cas_n                      (afi_cas_n                      ),
+        .afi_we_n                       (afi_we_n                       ),
+        .afi_ba                         (afi_ba                         ),
+        .afi_addr                       (afi_addr                       ),
+        .afi_rst_n                      (afi_rst_n                      ),
+        .afi_odt                        (afi_odt                        )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_odt_gen
+//------------------------------------------------------------------------------
+//
+//  ODT generation block
+//
+//  Info: Generate ODT information based on user configuration
+//
+//==============================================================================
+    
+    // alt_mem_ddrx_odt_gen #
+    // (
+    //     .CFG_DWIDTH_RATIO               (CFG_DWIDTH_RATIO               ),
+    //     .CFG_ODT_ENABLED                (CFG_ODT_ENABLED                ),
+    //     .CFG_MEM_IF_CHIP                (CFG_MEM_IF_CHIP                ),
+    //     .CFG_MEM_IF_ODT_WIDTH           (CFG_MEM_IF_ODT_WIDTH           ),
+    //     .CFG_OUTPUT_REGD                (CFG_OUTPUT_REGD                ),
+    //     .CFG_PORT_WIDTH_CAS_WR_LAT      (CFG_PORT_WIDTH_CAS_WR_LAT      ),
+    //     .CFG_PORT_WIDTH_TCL             (CFG_PORT_WIDTH_TCL             ),
+    //     .CFG_PORT_WIDTH_ADD_LAT         (CFG_PORT_WIDTH_ADD_LAT         ),
+    //     .CFG_PORT_WIDTH_TYPE            (CFG_PORT_WIDTH_TYPE            )
+    // )
+    // odt_gen_inst
+    // (
+    //     .ctl_clk                        (ctl_clk                        ),
+    //     .ctl_reset_n                    (ctl_reset_n                    ),
+    //     .cfg_type                       (cfg_type                       ),
+    //     .cfg_tcl                        (cfg_tcl                        ),
+    //     .cfg_cas_wr_lat                 (cfg_cas_wr_lat                 ),
+    //     .cfg_add_lat                    (cfg_add_lat                    ),
+    //     .cfg_write_odt_chip             (cfg_write_odt_chip             ),
+    //     .cfg_read_odt_chip              (cfg_read_odt_chip              ),
+    //     .cfg_burst_length               (cfg_burst_length               ),
+    //     .bg_do_read                     (bg_do_read                     ),
+    //     .bg_do_write                    (bg_do_write                    ),
+    //     .bg_to_chip                     (bg_to_chip                     ),
+    //     .afi_odt                        (afi_odt                        )
+    // );
+    
+//==============================================================================
+// alt_mem_ddrx_rdwr_data_tmg
+//------------------------------------------------------------------------------
+//
+//  Read / write data timing block
+//
+//  Info: Adjust read and write data timing based on AFI information
+//
+//==============================================================================
+ 	
+    alt_mem_ddrx_rdwr_data_tmg #
+    (
+        .CFG_DWIDTH_RATIO                   (CFG_DWIDTH_RATIO                   ),
+        .CFG_MEM_IF_CHIP                    (CFG_MEM_IF_CHIP                    ),
+        .CFG_MEM_IF_DQ_WIDTH                (CFG_MEM_IF_DQ_WIDTH                ),
+        .CFG_MEM_IF_DQS_WIDTH               (CFG_MEM_IF_DQS_WIDTH               ),
+        .CFG_MEM_IF_DM_WIDTH                (CFG_MEM_IF_DM_WIDTH                ),
+        .CFG_WLAT_BUS_WIDTH                 (CFG_WLAT_BUS_WIDTH                 ),
+        .CFG_DRAM_WLAT_GROUP                (CFG_DRAM_WLAT_GROUP                ),
+        .CFG_DATA_ID_WIDTH                  (CFG_DATA_ID_WIDTH                  ),
+        .CFG_WDATA_REG                      (CFG_WDATA_REG                      ),
+        .CFG_ECC_ENC_REG                    (CFG_ECC_ENC_REG                    ),
+        .CFG_AFI_INTF_PHASE_NUM             (CFG_AFI_INTF_PHASE_NUM             ),
+        .CFG_PORT_WIDTH_ENABLE_ECC          (CFG_PORT_WIDTH_ENABLE_ECC          ),
+        .CFG_PORT_WIDTH_OUTPUT_REGD         (CFG_PORT_WIDTH_OUTPUT_REGD         ),
+        .CFG_CTL_ARBITER_TYPE               (CFG_CTL_ARBITER_TYPE               ),
+        .CFG_USE_SHADOW_REGS                (CFG_USE_SHADOW_REGS                )
+    )
+    rdwr_data_tmg_inst
+    (
+        .ctl_clk                            (ctl_clk                            ),
+        .ctl_reset_n                        (ctl_reset_n                        ),
+        .cfg_enable_ecc                     (cfg_enable_ecc                     ),
+        .cfg_output_regd                    (cfg_output_regd                    ),
+        .cfg_output_regd_for_afi_output     (cfg_output_regd_for_afi_output     ),
+        .bg_do_read                         (bg_do_read                         ),
+        .bg_do_write                        (bg_do_write                        ),
+        .bg_doing_read                      (bg_doing_read                      ),
+        .bg_doing_write                     (bg_doing_write                     ),
+        .bg_rdwr_data_valid                 (bg_rdwr_data_valid                 ),
+        .dataid                             (bg_dataid                          ),
+        .bg_do_rmw_correct                  (bg_do_rmw_correct                  ),
+        .bg_do_rmw_partial                  (bg_do_rmw_partial                  ),
+        .bg_to_chip                         (bg_to_chip                         ),
+        .ecc_wdata                          (ecc_wdata                          ),
+        .ecc_dm                             (ecc_dm                             ),
+        .afi_wlat                           (afi_wlat                           ),
+        .afi_doing_read                     (afi_rdata_en                       ),
+        .afi_doing_read_full                (afi_rdata_en_full                  ),
+        .ecc_wdata_fifo_read                (ecc_wdata_fifo_read                ),
+        .ecc_wdata_fifo_dataid              (ecc_wdata_fifo_dataid              ),
+        .ecc_wdata_fifo_dataid_vector       (ecc_wdata_fifo_dataid_vector       ),
+        .ecc_wdata_fifo_rmw_correct         (ecc_wdata_fifo_rmw_correct         ),
+        .ecc_wdata_fifo_rmw_partial         (ecc_wdata_fifo_rmw_partial         ),
+        .ecc_wdata_fifo_read_first          (ecc_wdata_fifo_read_first          ),
+        .ecc_wdata_fifo_dataid_first        (ecc_wdata_fifo_dataid_first        ),
+        .ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
+        .ecc_wdata_fifo_rmw_correct_first   (ecc_wdata_fifo_rmw_correct_first   ),
+        .ecc_wdata_fifo_rmw_partial_first   (ecc_wdata_fifo_rmw_partial_first   ),
+        .ecc_wdata_fifo_first_vector        (ecc_wdata_fifo_first_vector        ),
+        .ecc_wdata_fifo_read_last           (ecc_wdata_fifo_read_last           ),
+        .ecc_wdata_fifo_dataid_last         (ecc_wdata_fifo_dataid_last         ),
+        .ecc_wdata_fifo_dataid_vector_last  (ecc_wdata_fifo_dataid_vector_last  ),
+        .ecc_wdata_fifo_rmw_correct_last    (ecc_wdata_fifo_rmw_correct_last    ),
+        .ecc_wdata_fifo_rmw_partial_last    (ecc_wdata_fifo_rmw_partial_last    ),
+        .afi_rrank                          (int_afi_rrank                      ),
+        .afi_wrank                          (int_afi_wrank                      ),
+        .afi_dqs_burst                      (afi_dqs_burst                      ),
+        .afi_wdata_valid                    (afi_wdata_valid                    ),
+        .afi_wdata                          (afi_wdata                          ),
+        .afi_dm                             (afi_dm                             )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_wdata_path
+//------------------------------------------------------------------------------
+//
+//  Write data path block
+//
+//  Info: Handles write data processing
+//
+//==============================================================================
+   
+    // match datapath id width, with command path id width
+    generate
+    begin : gen_resolve_datap_id
+        genvar i;
+        for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
+        begin : write_dataid_per_dqs_group
+            if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
+            begin
+                assign ecc_wdata_wrdataid        [(i + 1) * CFG_WRDATA_ID_WIDTH     - 1 : i * CFG_WRDATA_ID_WIDTH    ] = ecc_wdata_fifo_dataid        [(i * CFG_DATA_ID_WIDTH     ) + CFG_WRDATA_ID_WIDTH     - 1 : i * CFG_DATA_ID_WIDTH     ];
+                assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
+            end
+            else    // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
+            begin
+                assign ecc_wdata_wrdataid        [(i + 1) * CFG_WRDATA_ID_WIDTH     - 1 : i * CFG_WRDATA_ID_WIDTH    ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid        [(i * CFG_DATA_ID_WIDTH     ) + CFG_WRDATA_ID_WIDTH     - 1 : i * CFG_DATA_ID_WIDTH     ]};
+                assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER                  {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
+            end
+        end
+        
+        if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
+        begin
+            assign wdatap_free_id_dataid           = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
+            assign ecc_wdata_wrdataid_first        = ecc_wdata_fifo_dataid_first [CFG_WRDATA_ID_WIDTH - 1 : 0];
+            assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first [CFG_WRDATA_ID_WIDTH_SQRD -1 : 0];
+            assign ecc_wdata_wrdataid_last         = ecc_wdata_fifo_dataid_last [CFG_WRDATA_ID_WIDTH - 1 : 0];
+            assign ecc_wdata_wrdataid_vector_last  = ecc_wdata_fifo_dataid_vector_last [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0];
+        end
+        else    // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
+        begin
+            assign wdatap_free_id_dataid           = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
+            assign ecc_wdata_wrdataid_first        = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
+            assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
+            assign ecc_wdata_wrdataid_last         = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
+            assign ecc_wdata_wrdataid_vector_last  = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
+        end
+        
+        if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
+        begin
+            assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
+            assign bg_rddataid           = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
+        end
+        else if(CFG_RDDATA_ID_WIDTH > CFG_DATA_ID_WIDTH)
+        begin
+            assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
+            assign bg_rddataid           = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
+        end
+        else // CFG_RDDATA_ID_WIDTH == CFG_DATA_ID_WIDTH
+        begin
+            assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
+            assign bg_rddataid           = bg_dataid;
+        end
+    end
+    endgenerate
+
+
+    alt_mem_ddrx_wdata_path #
+    (
+        .CFG_LOCAL_DATA_WIDTH                       (CFG_LOCAL_DATA_WIDTH           ),
+        .CFG_MEM_IF_DQ_WIDTH                        (CFG_MEM_IF_DQ_WIDTH            ),
+        .CFG_MEM_IF_DQS_WIDTH                       (CFG_MEM_IF_DQS_WIDTH           ),
+        .CFG_INT_SIZE_WIDTH                         (CFG_INT_SIZE_WIDTH             ),
+        .CFG_DATA_ID_WIDTH                          (CFG_WRDATA_ID_WIDTH            ),
+        .CFG_DRAM_WLAT_GROUP                        (CFG_DRAM_WLAT_GROUP            ),
+        .CFG_LOCAL_WLAT_GROUP                       (CFG_LOCAL_WLAT_GROUP           ),
+        .CFG_TBP_NUM                                (CFG_CTL_TBP_NUM                ),
+        .CFG_BUFFER_ADDR_WIDTH                      (CFG_WRBUFFER_ADDR_WIDTH        ),
+        .CFG_DWIDTH_RATIO                           (CFG_DWIDTH_RATIO               ),
+        .CFG_ECC_MULTIPLES                          (CFG_ECC_MULTIPLES              ),
+        .CFG_WDATA_REG                              (CFG_WDATA_REG                  ),
+        .CFG_PARTIAL_BE_PER_WORD_ENABLE             (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
+        .CFG_ECC_CODE_WIDTH                         (CFG_ECC_CODE_WIDTH             ),
+        .CFG_PORT_WIDTH_BURST_LENGTH                (CFG_PORT_WIDTH_BURST_LENGTH    ),
+        .CFG_PORT_WIDTH_ENABLE_ECC                  (CFG_PORT_WIDTH_ENABLE_ECC      ),
+        .CFG_PORT_WIDTH_ENABLE_AUTO_CORR            (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
+        .CFG_PORT_WIDTH_ENABLE_NO_DM                (CFG_PORT_WIDTH_ENABLE_NO_DM    ),
+        .CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES  (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
+        .CFG_PORT_WIDTH_INTERFACE_WIDTH             (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
+	.CFG_ECC_BE_ALLLOW_RMW			    (CFG_ECC_BE_ALLLOW_RMW)
+    )
+    wdata_path_inst
+    (
+        .ctl_clk                                    (ctl_clk                            ),
+        .ctl_reset_n                                (ctl_reset_n                        ),
+        .cfg_burst_length                           (cfg_burst_length                   ),
+        .cfg_enable_ecc                             (cfg_enable_ecc                     ),
+        .cfg_enable_auto_corr                       (cfg_enable_auto_corr               ),
+        .cfg_enable_no_dm                           (cfg_enable_no_dm                   ),
+        .cfg_enable_ecc_code_overwrites             (cfg_enable_ecc_code_overwrites     ),
+        .cfg_interface_width                        (cfg_interface_width                ),
+        .wdatap_free_id_valid                       (wdatap_free_id_valid               ),
+        .wdatap_free_id_dataid                      (wdatap_free_id_wrdataid            ),
+        .proc_busy                                  (proc_busy                          ),
+        .proc_load                                  (proc_load                          ),
+        .proc_load_dataid                           (proc_load_dataid                   ),
+        .proc_write                                 (proc_write                         ),
+        .tbp_load_index                             (tbp_load_index                     ),
+        .proc_size                                  (proc_size                          ),
+        .wr_data_mem_full                           (wr_data_mem_full                   ),
+        .write_data_en                              (write_data_valid                   ),
+        .write_data                                 (write_data                         ),
+        .byte_en                                    (byte_en                            ),
+        .data_complete                              (data_complete                      ),
+        .data_rmw_complete                          (data_rmw_complete                  ),
+        .data_rmw_fetch                             (data_rmw_fetch                     ),
+        .data_partial_be                            (data_partial_be                    ),
+        .doing_write                                (ecc_wdata_fifo_read                ),
+        .dataid                                     (ecc_wdata_wrdataid                 ),
+        .dataid_vector                              (ecc_wdata_wrdataid_vector          ),
+        .rdwr_data_valid                            (ecc_wdata_fifo_read                ),
+        .rmw_correct                                (ecc_wdata_fifo_rmw_correct         ),
+        .rmw_partial                                (ecc_wdata_fifo_rmw_partial         ),
+        .doing_write_first                          (ecc_wdata_fifo_read_first          ),
+        .dataid_first                               (ecc_wdata_wrdataid_first           ),
+        .dataid_vector_first                        (ecc_wdata_wrdataid_vector_first    ),
+        .rdwr_data_valid_first                      (ecc_wdata_fifo_read_first          ),
+        .rmw_correct_first                          (ecc_wdata_fifo_rmw_correct_first   ),
+        .rmw_partial_first                          (ecc_wdata_fifo_rmw_partial_first   ),
+        .doing_write_first_vector                   (ecc_wdata_fifo_first_vector        ),
+        .rdwr_data_valid_first_vector               (ecc_wdata_fifo_first_vector        ),
+        .doing_write_last                           (ecc_wdata_fifo_read_last           ),
+        .dataid_last                                (ecc_wdata_wrdataid_last            ),
+        .dataid_vector_last                         (ecc_wdata_wrdataid_vector_last     ),
+        .rdwr_data_valid_last                       (ecc_wdata_fifo_read_last           ),
+        .rmw_correct_last                           (ecc_wdata_fifo_rmw_correct_last    ),
+        .rmw_partial_last                           (ecc_wdata_fifo_rmw_partial_last    ),
+        .wdatap_data                                (wdatap_data                        ),
+        .wdatap_rmw_partial_data                    (wdatap_rmw_partial_data            ),
+        .wdatap_rmw_correct_data                    (wdatap_rmw_correct_data            ),
+        .wdatap_rmw_partial                         (wdatap_rmw_partial                 ),
+        .wdatap_rmw_correct                         (wdatap_rmw_correct                 ),
+        .wdatap_dm                                  (wdatap_dm                          ),
+        .wdatap_ecc_code                            (wdatap_ecc_code                    ),
+        .wdatap_ecc_code_overwrite                  (wdatap_ecc_code_overwrite          ),
+        .rmwfifo_data_valid                         (rmwfifo_data_valid                 ),
+        .rmwfifo_data                               (rmwfifo_data                       ),
+        .rmwfifo_ecc_dbe                            (rmwfifo_ecc_dbe                    ),
+        .rmwfifo_ecc_code                           (rmwfifo_ecc_code                   )
+    );
+    
+//==============================================================================
+// alt_mem_ddrx_rdata_path
+//------------------------------------------------------------------------------
+//
+//  Read data path block
+//
+//  Info: Handles read data processing
+//
+//==============================================================================
+
+    alt_mem_ddrx_rdata_path #
+    (
+        .CFG_LOCAL_DATA_WIDTH               (CFG_LOCAL_DATA_WIDTH               ),
+        .CFG_INT_SIZE_WIDTH                 (CFG_INT_SIZE_WIDTH                 ),
+        .CFG_DATA_ID_WIDTH                  (CFG_RDDATA_ID_WIDTH                ),
+        .CFG_LOCAL_ID_WIDTH                 (CFG_LOCAL_ID_WIDTH                 ),
+        .CFG_LOCAL_ADDR_WIDTH               (CFG_LOCAL_ADDR_WIDTH               ),
+        .CFG_BUFFER_ADDR_WIDTH              (CFG_RDBUFFER_ADDR_WIDTH            ),
+        .CFG_MEM_IF_CS_WIDTH                (CFG_MEM_IF_CS_WIDTH                ),
+        .CFG_MEM_IF_BA_WIDTH                (CFG_MEM_IF_BA_WIDTH                ),
+        .CFG_MEM_IF_ROW_WIDTH               (CFG_MEM_IF_ROW_WIDTH               ),
+        .CFG_MEM_IF_COL_WIDTH               (CFG_MEM_IF_COL_WIDTH               ),
+        .CFG_MAX_READ_CMD_NUM_WIDTH         (CFG_MAX_PENDING_RD_CMD_WIDTH       ),
+        .CFG_RDATA_RETURN_MODE              (CFG_RDATA_RETURN_MODE              ),
+        .CFG_AFI_INTF_PHASE_NUM             (CFG_AFI_INTF_PHASE_NUM             ),
+        .CFG_ERRCMD_FIFO_ADDR_WIDTH         (CFG_ERRCMD_FIFO_ADDR_WIDTH         ),
+        .CFG_DWIDTH_RATIO                   (CFG_DWIDTH_RATIO                   ),
+        .CFG_ECC_MULTIPLES                  (CFG_ECC_MULTIPLES                  ),
+        .CFG_ECC_CODE_WIDTH                 (CFG_ECC_CODE_WIDTH                 ),
+        .CFG_PORT_WIDTH_TYPE                (CFG_PORT_WIDTH_TYPE                ),
+        .CFG_PORT_WIDTH_ENABLE_ECC          (CFG_PORT_WIDTH_ENABLE_ECC          ),
+        .CFG_PORT_WIDTH_ENABLE_AUTO_CORR    (CFG_PORT_WIDTH_ENABLE_AUTO_CORR    ),
+        .CFG_PORT_WIDTH_ENABLE_NO_DM        (CFG_PORT_WIDTH_ENABLE_NO_DM        ),
+        .CFG_PORT_WIDTH_BURST_LENGTH        (CFG_PORT_WIDTH_BURST_LENGTH        ),
+        .CFG_PORT_WIDTH_ADDR_ORDER          (CFG_PORT_WIDTH_ADDR_ORDER          ),
+        .CFG_PORT_WIDTH_COL_ADDR_WIDTH      (CFG_PORT_WIDTH_COL_ADDR_WIDTH      ),
+        .CFG_PORT_WIDTH_ROW_ADDR_WIDTH      (CFG_PORT_WIDTH_ROW_ADDR_WIDTH      ),
+        .CFG_PORT_WIDTH_BANK_ADDR_WIDTH     (CFG_PORT_WIDTH_BANK_ADDR_WIDTH     ),
+        .CFG_PORT_WIDTH_CS_ADDR_WIDTH       (CFG_PORT_WIDTH_CS_ADDR_WIDTH       ),
+		.CFG_ERRCMD_FIFO_REG				(CFG_ERRCMD_FIFO_REG				)
+    )
+    rdata_path_inst
+    (
+        .ctl_clk                            (ctl_clk                            ),
+        .ctl_reset_n                        (ctl_reset_n                        ),
+        .cfg_type                           (cfg_type                           ),
+        .cfg_enable_ecc                     (cfg_enable_ecc                     ),
+        .cfg_enable_auto_corr               (cfg_enable_auto_corr               ),
+        .cfg_enable_no_dm                   (cfg_enable_no_dm                   ),
+        .cfg_burst_length                   (cfg_burst_length                   ),
+        .cfg_addr_order                     (cfg_addr_order                     ),
+        .cfg_col_addr_width                 (cfg_col_addr_width                 ),
+        .cfg_row_addr_width                 (cfg_row_addr_width                 ),
+        .cfg_bank_addr_width                (cfg_bank_addr_width                ),
+        .cfg_cs_addr_width                  (cfg_cs_addr_width                  ),
+        .rdatap_free_id_valid               (rdatap_free_id_valid               ),
+        .rdatap_free_id_dataid              (rdatap_free_id_rddataid            ),
+        .proc_busy                          (proc_busy                          ),
+        .proc_load                          (proc_load                          ),
+        .proc_load_dataid                   (proc_load_dataid                   ),
+        .proc_read                          (proc_read                          ),
+        .proc_size                          (proc_size                          ),
+        .proc_localid                       (proc_localid                       ),
+        .read_data_valid                    (read_data_valid                    ),
+        .read_data                          (read_data                          ),
+        .read_data_error                    (read_data_error                    ),
+        .read_data_localid                  (read_data_localid                  ),
+        .bg_do_read                         (bg_do_read                         ),
+        .bg_to_chipsel                      (bg_to_chipsel                      ),
+        .bg_to_bank                         (bg_to_bank                         ),
+        .bg_to_row                          (bg_to_row                          ),
+        .bg_to_column                       (bg_to_col                          ),
+        .bg_dataid                          (bg_rddataid                        ),
+        .bg_localid                         (bg_localid                         ),
+        .bg_size                            (bg_size                            ),
+        .bg_do_rmw_correct                  (bg_do_rmw_correct                  ),
+        .bg_do_rmw_partial                  (bg_do_rmw_partial                  ),
+        .ecc_rdata                          (ecc_rdata                          ),
+        .ecc_rdatav                         (ecc_rdata_valid                    ),
+        .ecc_sbe                            (ecc_sbe                            ),
+        .ecc_dbe                            (ecc_dbe                            ),
+        .ecc_code                           (ecc_code                           ),
+        .errcmd_ready                       (errcmd_ready                       ),
+        .errcmd_valid                       (errcmd_valid                       ),
+        .errcmd_chipsel                     (errcmd_chipsel                     ),
+        .errcmd_bank                        (errcmd_bank                        ),
+        .errcmd_row                         (errcmd_row                         ),
+        .errcmd_column                      (errcmd_column                      ),
+        .errcmd_size                        (errcmd_size                        ),
+        .errcmd_localid                     (errcmd_localid                     ),
+        .rdatap_rcvd_addr                   (rdatap_rcvd_addr                   ),
+        .rdatap_rcvd_cmd                    (rdatap_rcvd_cmd                    ),
+        .rdatap_rcvd_corr_dropped           (rdatap_rcvd_corr_dropped           ),
+        .rmwfifo_data_valid                 (rmwfifo_data_valid                 ),
+        .rmwfifo_data                       (rmwfifo_data                       ),
+        .rmwfifo_ecc_dbe                    (rmwfifo_ecc_dbe                    ),
+        .rmwfifo_ecc_code                   (rmwfifo_ecc_code                   )
+    );
+    
+//==============================================================================
+//  alt_mem_ddrx_ecc_encoder_decoder_wrapper
+//------------------------------------------------------------------------------
+//
+//  ECC encoder/decoder block
+//
+//  Info: Encode write data and decode read data, correct single bit error
+//        and detect double bit errors
+//
+//==============================================================================
+    
+    alt_mem_ddrx_ecc_encoder_decoder_wrapper #
+    (
+        .CFG_LOCAL_ADDR_WIDTH                   (CFG_LOCAL_ADDR_WIDTH               ),
+        .CFG_LOCAL_DATA_WIDTH                   (CFG_LOCAL_DATA_WIDTH               ),
+        .CFG_DWIDTH_RATIO                       (CFG_DWIDTH_RATIO                   ),
+        .CFG_ECC_MULTIPLES                      (CFG_ECC_MULTIPLES                  ),
+        .CFG_MEM_IF_DQ_WIDTH                    (CFG_MEM_IF_DQ_WIDTH                ),
+        .CFG_MEM_IF_DQS_WIDTH                   (CFG_MEM_IF_DQS_WIDTH               ),
+        .CFG_ECC_CODE_WIDTH                     (CFG_ECC_CODE_WIDTH                 ),
+        .CFG_ECC_ENC_REG                        (CFG_ECC_ENC_REG                    ),
+        .CFG_ECC_DEC_REG                        (CFG_ECC_DEC_REG                    ),
+		.CFG_ECC_DECODER_REG					(CFG_ECC_DECODER_REG				),
+        .CFG_ECC_RDATA_REG                      (CFG_ECC_RDATA_REG                  ),
+        .CFG_PORT_WIDTH_INTERFACE_WIDTH         (CFG_PORT_WIDTH_INTERFACE_WIDTH     ),
+        .CFG_PORT_WIDTH_ENABLE_ECC              (CFG_PORT_WIDTH_ENABLE_ECC          ),
+        .CFG_PORT_WIDTH_GEN_SBE                 (CFG_PORT_WIDTH_GEN_SBE             ),
+        .CFG_PORT_WIDTH_GEN_DBE                 (CFG_PORT_WIDTH_GEN_DBE             ),
+        .CFG_PORT_WIDTH_ENABLE_INTR             (CFG_PORT_WIDTH_ENABLE_INTR         ),
+        .CFG_PORT_WIDTH_MASK_SBE_INTR           (CFG_PORT_WIDTH_MASK_SBE_INTR       ),
+        .CFG_PORT_WIDTH_MASK_DBE_INTR           (CFG_PORT_WIDTH_MASK_DBE_INTR       ),
+        .CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR  (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
+        .CFG_PORT_WIDTH_CLR_INTR                (CFG_PORT_WIDTH_CLR_INTR            ),
+        .STS_PORT_WIDTH_SBE_ERROR               (STS_PORT_WIDTH_SBE_ERROR           ),
+        .STS_PORT_WIDTH_DBE_ERROR               (STS_PORT_WIDTH_DBE_ERROR           ),
+        .STS_PORT_WIDTH_SBE_COUNT               (STS_PORT_WIDTH_SBE_COUNT           ),
+        .STS_PORT_WIDTH_DBE_COUNT               (STS_PORT_WIDTH_DBE_COUNT           ),
+        .STS_PORT_WIDTH_CORR_DROP_ERROR         (STS_PORT_WIDTH_CORR_DROP_ERROR     ),
+        .STS_PORT_WIDTH_CORR_DROP_COUNT         (STS_PORT_WIDTH_CORR_DROP_COUNT     )
+    )
+    ecc_encoder_decoder_wrapper_inst
+    (
+        .ctl_clk                            (ctl_clk                            ),
+        .ctl_reset_n                        (ctl_reset_n                        ),
+        .cfg_interface_width                (cfg_interface_width                ),
+        .cfg_enable_ecc                     (cfg_enable_ecc                     ),
+        .cfg_gen_sbe                        (cfg_gen_sbe                        ),
+        .cfg_gen_dbe                        (cfg_gen_dbe                        ),
+        .cfg_enable_intr                    (cfg_enable_intr                    ),
+        .cfg_mask_sbe_intr                  (cfg_mask_sbe_intr                  ),
+        .cfg_mask_dbe_intr                  (cfg_mask_dbe_intr                  ),
+        .cfg_mask_corr_dropped_intr         (cfg_mask_corr_dropped_intr         ),
+        .cfg_clr_intr                       (cfg_clr_intr                       ),
+        .wdatap_dm                          (wdatap_dm                          ),
+        .wdatap_data                        (wdatap_data                        ),
+        .wdatap_rmw_partial_data            (wdatap_rmw_partial_data            ),
+        .wdatap_rmw_correct_data            (wdatap_rmw_correct_data            ),
+        .wdatap_rmw_partial                 (wdatap_rmw_partial                 ),
+        .wdatap_rmw_correct                 (wdatap_rmw_correct                 ),
+        .wdatap_ecc_code                    (wdatap_ecc_code                    ),
+        .wdatap_ecc_code_overwrite          (wdatap_ecc_code_overwrite          ),
+        .rdatap_rcvd_addr                   (rdatap_rcvd_addr                   ),
+        .rdatap_rcvd_cmd                    (rdatap_rcvd_cmd                    ),
+        .rdatap_rcvd_corr_dropped           (rdatap_rcvd_corr_dropped           ),
+        .afi_rdata                          (afi_rdata                          ),
+        .afi_rdata_valid                    (afi_rdata_valid                    ),
+        .ecc_rdata                          (ecc_rdata                          ),
+        .ecc_rdata_valid                    (ecc_rdata_valid                    ),
+        .ecc_dm                             (ecc_dm                             ),
+        .ecc_wdata                          (ecc_wdata                          ),
+        .ecc_sbe                            (ecc_sbe                            ),
+        .ecc_dbe                            (ecc_dbe                            ),
+        .ecc_code                           (ecc_code                           ),
+        .ecc_interrupt                      (ecc_interrupt                      ),
+        .sts_sbe_error                      (sts_sbe_error                      ),
+        .sts_dbe_error                      (sts_dbe_error                      ),
+        .sts_sbe_count                      (sts_sbe_count                      ),
+        .sts_dbe_count                      (sts_dbe_count                      ),
+        .sts_err_addr                       (sts_err_addr                       ),
+        .sts_corr_dropped                   (sts_corr_dropped                   ),
+        .sts_corr_dropped_count             (sts_corr_dropped_count             ),
+        .sts_corr_dropped_addr              (sts_corr_dropped_addr              )
+    );
+    
+//==============================================================================
+//  alt_mem_ddrx_sideband
+//------------------------------------------------------------------------------
+//
+//  Sideband block
+//
+//  Info: Monitor and issue sideband specific commands such as user/auto
+//        refresh, self refresh, power down, deep power down, 
+//        precharge all and zq calibration commands
+//
+//==============================================================================
+    
+    alt_mem_ddrx_sideband #
+    (
+        .CFG_PORT_WIDTH_TYPE                    (CFG_PORT_WIDTH_TYPE                    ),
+        .CFG_DWIDTH_RATIO                       (CFG_DWIDTH_RATIO                       ),
+        .CFG_REG_GRANT                          (CFG_REG_GRANT                          ),
+        .CFG_CTL_TBP_NUM                        (CFG_CTL_TBP_NUM                        ),
+        .CFG_MEM_IF_CS_WIDTH                    (CFG_MEM_IF_CS_WIDTH                    ),
+        .CFG_MEM_IF_CHIP                        (CFG_MEM_IF_CHIP                        ),
+        .CFG_MEM_IF_BA_WIDTH                    (CFG_MEM_IF_BA_WIDTH                    ),
+        .CFG_PORT_WIDTH_TCL                     (CFG_PORT_WIDTH_TCL                     ),
+        .CFG_PORT_WIDTH_CS_ADDR_WIDTH           (CFG_PORT_WIDTH_CS_ADDR_WIDTH           ),
+        .CFG_MEM_IF_CLK_PAIR_COUNT              (CFG_MEM_IF_CLK_PAIR_COUNT              ),
+        .CFG_RANK_TIMER_OUTPUT_REG              (CFG_RANK_TIMER_OUTPUT_REG              ),
+        .T_PARAM_ARF_TO_VALID_WIDTH             (T_PARAM_ARF_TO_VALID_WIDTH             ),
+        .T_PARAM_ARF_PERIOD_WIDTH               (T_PARAM_ARF_PERIOD_WIDTH               ),
+        .T_PARAM_PCH_ALL_TO_VALID_WIDTH         (T_PARAM_PCH_ALL_TO_VALID_WIDTH         ),
+        .T_PARAM_SRF_TO_VALID_WIDTH             (T_PARAM_SRF_TO_VALID_WIDTH             ),
+        .T_PARAM_SRF_TO_ZQ_CAL_WIDTH            (T_PARAM_SRF_TO_ZQ_CAL_WIDTH            ),
+        .T_PARAM_PDN_TO_VALID_WIDTH             (T_PARAM_PDN_TO_VALID_WIDTH             ),
+        .T_PARAM_PDN_PERIOD_WIDTH               (T_PARAM_PDN_PERIOD_WIDTH               ),
+        .T_PARAM_POWER_SAVING_EXIT_WIDTH        (T_PARAM_POWER_SAVING_EXIT_WIDTH        ),
+        .T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH     (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH     )
+    )
+    sideband_inst
+    (
+        .ctl_clk                                (ctl_clk                                ),
+        .ctl_reset_n                            (ctl_reset_n                            ),
+        .rfsh_req                               (rfsh_req                               ),
+        .rfsh_chip                              (rfsh_chip                              ),
+        .rfsh_ack                               (rfsh_ack                               ),
+        .zqcal_req                              (zqcal_req                              ),
+        .self_rfsh_req                          (self_rfsh_req                          ),
+        .self_rfsh_chip                         (self_rfsh_chip                         ),
+        .self_rfsh_ack                          (self_rfsh_ack                          ),
+        .deep_powerdn_req                       (deep_powerdn_req                       ),
+        .deep_powerdn_chip                      (deep_powerdn_chip                      ),
+        .deep_powerdn_ack                       (deep_powerdn_ack                       ),
+        .power_down_ack                         (power_down_ack                         ),
+        .stall_row_arbiter                      (stall_row_arbiter                      ),
+        .stall_col_arbiter                      (stall_col_arbiter                      ),
+        .stall_chip                             (stall_chip                             ),
+        .sb_do_precharge_all                    (sb_do_precharge_all                    ),
+        .sb_do_refresh                          (sb_do_refresh                          ),
+        .sb_do_self_refresh                     (sb_do_self_refresh                     ),
+        .sb_do_power_down                       (sb_do_power_down                       ),
+        .sb_do_deep_pdown                       (sb_do_deep_pdown                       ),
+        .sb_do_zq_cal                           (sb_do_zq_cal                           ),
+        .sb_tbp_precharge_all                   (sb_tbp_precharge_all                   ),
+        .ctl_mem_clk_disable                    (ctl_sb_mem_clk_disable                 ),
+        .ctl_cal_req                            (ctl_sb_cal_req                         ),
+        .ctl_init_req                           (ctl_sb_init_req                        ),
+        .ctl_cal_success                        (ctl_cal_success                        ),
+        .cmd_gen_chipsel                        (cmd_gen_chipsel                        ),
+        .tbp_chipsel                            (tbp_chipsel                            ),
+        .tbp_load                               (tbp_load                               ),
+        .t_param_arf_to_valid                   (t_param_arf_to_valid                   ),
+        .t_param_arf_period                     (t_param_arf_period                     ),
+        .t_param_pch_all_to_valid               (t_param_pch_all_to_valid               ),
+        .t_param_srf_to_valid                   (t_param_srf_to_valid                   ),
+        .t_param_srf_to_zq_cal                  (t_param_srf_to_zq_cal                  ),
+        .t_param_pdn_to_valid                   (t_param_pdn_to_valid                   ),
+        .t_param_pdn_period                     (t_param_pdn_period                     ),
+        .t_param_power_saving_exit              (t_param_power_saving_exit              ),
+        .t_param_mem_clk_entry_cycles           (t_param_mem_clk_entry_cycles           ),
+        .tbp_empty                              (tbp_empty                              ),
+        .tbp_bank_closed                        (tbp_bank_closed                        ),
+        .tbp_timer_ready                        (tbp_timer_ready                        ),
+        .row_grant                              (or_row_grant                           ),
+        .col_grant                              (or_col_grant                           ),
+        .afi_ctl_refresh_done                   (afi_ctl_refresh_done                   ),
+        .afi_seq_busy                           (afi_seq_busy                           ),
+        .afi_ctl_long_idle                      (afi_ctl_long_idle                      ),
+        .cfg_cs_addr_width                      (cfg_cs_addr_width                      ),
+        .cfg_enable_dqs_tracking                (cfg_enable_dqs_tracking                ),
+        .cfg_user_rfsh                          (cfg_user_rfsh                          ),
+        .cfg_type                               (cfg_type                               ),
+        .cfg_tcl                                (cfg_tcl                                ),
+        .cfg_regdimm_enable                     (cfg_regdimm_enable                     ),
+        .sideband_in_refresh                    (sideband_in_refresh                    )
+    );
+    
+//==============================================================================
+//  alt_mem_ddrx_rank_timer
+//------------------------------------------------------------------------------
+//
+//  Rank timer block
+//
+//  Info: Monitor rank specific timing parameter for activate, precharge,
+//        read and write commands
+//
+//============================================================================== 
+    
+    alt_mem_ddrx_rank_timer #
+    (
+        .CFG_DWIDTH_RATIO                       (CFG_DWIDTH_RATIO                       ),
+        .CFG_CTL_TBP_NUM                        (CFG_CTL_TBP_NUM                        ),
+        .CFG_CTL_ARBITER_TYPE                   (CFG_CTL_ARBITER_TYPE                   ),
+        .CFG_MEM_IF_CHIP                        (CFG_MEM_IF_CHIP                        ),
+        .CFG_MEM_IF_CS_WIDTH                    (CFG_MEM_IF_CS_WIDTH                    ),
+        .CFG_INT_SIZE_WIDTH                     (CFG_INT_SIZE_WIDTH                     ),
+        .CFG_AFI_INTF_PHASE_NUM                 (CFG_AFI_INTF_PHASE_NUM                 ),
+        .CFG_REG_GRANT                          (CFG_REG_GRANT                          ),
+        .CFG_RANK_TIMER_OUTPUT_REG              (CFG_RANK_TIMER_OUTPUT_REG              ),
+        .CFG_PORT_WIDTH_BURST_LENGTH            (CFG_PORT_WIDTH_BURST_LENGTH            ),
+        .T_PARAM_FOUR_ACT_TO_ACT_WIDTH          (T_PARAM_FOUR_ACT_TO_ACT_WIDTH          ),
+        .T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH     (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH     ),
+        .T_PARAM_WR_TO_WR_WIDTH                 (T_PARAM_WR_TO_WR_WIDTH                 ),
+        .T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH       (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH       ),
+        .T_PARAM_WR_TO_RD_WIDTH                 (T_PARAM_WR_TO_RD_WIDTH                 ),
+        .T_PARAM_WR_TO_RD_BC_WIDTH              (T_PARAM_WR_TO_RD_BC_WIDTH              ),
+        .T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH       (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH       ),
+        .T_PARAM_RD_TO_RD_WIDTH                 (T_PARAM_RD_TO_RD_WIDTH                 ),
+        .T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH       (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH       ),
+        .T_PARAM_RD_TO_WR_WIDTH                 (T_PARAM_RD_TO_WR_WIDTH                 ),
+        .T_PARAM_RD_TO_WR_BC_WIDTH              (T_PARAM_RD_TO_WR_BC_WIDTH              ),
+        .T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH       (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH       )
+    )
+    rank_timer_inst
+    (
+        .ctl_clk                                (ctl_clk                                ),
+        .ctl_reset_n                            (ctl_reset_n                            ),
+        .cfg_burst_length                       (cfg_burst_length                       ),
+        .t_param_four_act_to_act                (t_param_four_act_to_act                ),
+        .t_param_act_to_act_diff_bank           (t_param_act_to_act_diff_bank           ),
+        .t_param_wr_to_wr                       (t_param_wr_to_wr                       ),
+        .t_param_wr_to_wr_diff_chip             (t_param_wr_to_wr_diff_chip             ),
+        .t_param_wr_to_rd                       (t_param_wr_to_rd                       ),
+        .t_param_wr_to_rd_bc                    (t_param_wr_to_rd_bc                    ),
+        .t_param_wr_to_rd_diff_chip             (t_param_wr_to_rd_diff_chip             ),
+        .t_param_rd_to_rd                       (t_param_rd_to_rd                       ),
+        .t_param_rd_to_rd_diff_chip             (t_param_rd_to_rd_diff_chip             ),
+        .t_param_rd_to_wr                       (t_param_rd_to_wr                       ),
+        .t_param_rd_to_wr_bc                    (t_param_rd_to_wr_bc                    ),
+        .t_param_rd_to_wr_diff_chip             (t_param_rd_to_wr_diff_chip             ),
+        .bg_do_write                            (bg_do_write_combi                      ),
+        .bg_do_read                             (bg_do_read_combi                       ),
+        .bg_do_burst_chop                       (bg_do_burst_chop_combi                 ),
+        .bg_do_burst_terminate                  (bg_do_burst_terminate_combi            ),
+        .bg_do_activate                         (bg_do_activate_combi                   ),
+        .bg_do_precharge                        (bg_do_precharge_combi                  ),
+        .bg_to_chip                             (bg_to_chip_combi                       ),
+        .bg_effective_size                      (bg_effective_size_combi                ),
+        .bg_interrupt_ready                     (bg_interrupt_ready_combi               ),
+        .cmd_gen_chipsel                        (cmd_gen_chipsel                        ),
+        .tbp_chipsel                            (tbp_chipsel                            ),
+        .tbp_load                               (tbp_load                               ),
+        .stall_chip                             (stall_chip                             ),
+        .can_activate                           (can_activate                           ),
+        .can_precharge                          (can_precharge                          ),
+        .can_read                               (can_read                               ),
+        .can_write                              (can_write                              )
+    );
+    
+//==============================================================================
+//  alt_mem_ddrx_timing_param
+//------------------------------------------------------------------------------
+//
+//  Timing parameter block
+//
+//  Info: Pre-calculate required timing parameters for each memory commands
+//        based on memory type
+//
+//==============================================================================
+    
+    alt_mem_ddrx_timing_param #
+    (
+        .CFG_DWIDTH_RATIO                                       (CFG_DWIDTH_RATIO                                       ),
+        .CFG_CTL_ARBITER_TYPE                                   (CFG_CTL_ARBITER_TYPE                                   ),
+        .CFG_PORT_WIDTH_TYPE                                    (CFG_PORT_WIDTH_TYPE                                    ),
+        .CFG_PORT_WIDTH_BURST_LENGTH                            (CFG_PORT_WIDTH_BURST_LENGTH                            ),
+        .CFG_PORT_WIDTH_CAS_WR_LAT                              (CFG_PORT_WIDTH_CAS_WR_LAT                              ),
+        .CFG_PORT_WIDTH_ADD_LAT                                 (CFG_PORT_WIDTH_ADD_LAT                                 ),
+        .CFG_PORT_WIDTH_TCL                                     (CFG_PORT_WIDTH_TCL                                     ),
+        .CFG_PORT_WIDTH_TRRD                                    (CFG_PORT_WIDTH_TRRD                                    ),
+        .CFG_PORT_WIDTH_TFAW                                    (CFG_PORT_WIDTH_TFAW                                    ),
+        .CFG_PORT_WIDTH_TRFC                                    (CFG_PORT_WIDTH_TRFC                                    ),
+        .CFG_PORT_WIDTH_TREFI                                   (CFG_PORT_WIDTH_TREFI                                   ),
+        .CFG_PORT_WIDTH_TRCD                                    (CFG_PORT_WIDTH_TRCD                                    ),
+        .CFG_PORT_WIDTH_TRP                                     (CFG_PORT_WIDTH_TRP                                     ),
+        .CFG_PORT_WIDTH_TWR                                     (CFG_PORT_WIDTH_TWR                                     ),
+        .CFG_PORT_WIDTH_TWTR                                    (CFG_PORT_WIDTH_TWTR                                    ),
+        .CFG_PORT_WIDTH_TRTP                                    (CFG_PORT_WIDTH_TRTP                                    ),
+        .CFG_PORT_WIDTH_TRAS                                    (CFG_PORT_WIDTH_TRAS                                    ),
+        .CFG_PORT_WIDTH_TRC                                     (CFG_PORT_WIDTH_TRC                                     ),
+        .CFG_PORT_WIDTH_TCCD                                    (CFG_PORT_WIDTH_TCCD                                    ),
+        .CFG_PORT_WIDTH_TMRD                                    (CFG_PORT_WIDTH_TMRD                                    ),
+        .CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES                   (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES                   ),
+        .CFG_PORT_WIDTH_PDN_EXIT_CYCLES                         (CFG_PORT_WIDTH_PDN_EXIT_CYCLES                         ),
+        .CFG_PORT_WIDTH_AUTO_PD_CYCLES                          (CFG_PORT_WIDTH_AUTO_PD_CYCLES                          ),
+        .CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES                (CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES                ),
+        .CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                    (CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                    ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR               (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR               ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH                (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH                ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT                (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT                ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD                  (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD                  ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP        (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP        ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR                  (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR                  ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC               (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC               ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP        (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP        ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH                 (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH                 ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID            (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID            ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR                  (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR                  ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP        (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP        ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD                  (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD                  ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC               (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC               ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP        (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP        ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH                 (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH                 ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID            (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID            ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID              (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID              ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID          (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID          ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK      (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK      ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT           (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT           ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID              (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID              ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID              (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID              ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID              (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID              ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL             (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL             ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD                (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD                ),
+        .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD                (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD                ),
+        .T_PARAM_ACT_TO_RDWR_WIDTH                              (T_PARAM_ACT_TO_RDWR_WIDTH                              ),
+        .T_PARAM_ACT_TO_PCH_WIDTH                               (T_PARAM_ACT_TO_PCH_WIDTH                               ),
+        .T_PARAM_ACT_TO_ACT_WIDTH                               (T_PARAM_ACT_TO_ACT_WIDTH                               ),
+        .T_PARAM_RD_TO_RD_WIDTH                                 (T_PARAM_RD_TO_RD_WIDTH                                 ),
+        .T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH                       (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH                       ),
+        .T_PARAM_RD_TO_WR_WIDTH                                 (T_PARAM_RD_TO_WR_WIDTH                                 ),
+        .T_PARAM_RD_TO_WR_BC_WIDTH                              (T_PARAM_RD_TO_WR_BC_WIDTH                              ),
+        .T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH                       (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH                       ),
+        .T_PARAM_RD_TO_PCH_WIDTH                                (T_PARAM_RD_TO_PCH_WIDTH                                ),
+        .T_PARAM_RD_AP_TO_VALID_WIDTH                           (T_PARAM_RD_AP_TO_VALID_WIDTH                           ),
+        .T_PARAM_WR_TO_WR_WIDTH                                 (T_PARAM_WR_TO_WR_WIDTH                                 ),
+        .T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH                       (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH                       ),
+        .T_PARAM_WR_TO_RD_WIDTH                                 (T_PARAM_WR_TO_RD_WIDTH                                 ),
+        .T_PARAM_WR_TO_RD_BC_WIDTH                              (T_PARAM_WR_TO_RD_BC_WIDTH                              ),
+        .T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH                       (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH                       ),
+        .T_PARAM_WR_TO_PCH_WIDTH                                (T_PARAM_WR_TO_PCH_WIDTH                                ),
+        .T_PARAM_WR_AP_TO_VALID_WIDTH                           (T_PARAM_WR_AP_TO_VALID_WIDTH                           ),
+        .T_PARAM_PCH_TO_VALID_WIDTH                             (T_PARAM_PCH_TO_VALID_WIDTH                             ),
+        .T_PARAM_PCH_ALL_TO_VALID_WIDTH                         (T_PARAM_PCH_ALL_TO_VALID_WIDTH                         ),
+        .T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH                     (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH                     ),
+        .T_PARAM_FOUR_ACT_TO_ACT_WIDTH                          (T_PARAM_FOUR_ACT_TO_ACT_WIDTH                          ),
+        .T_PARAM_ARF_TO_VALID_WIDTH                             (T_PARAM_ARF_TO_VALID_WIDTH                             ),
+        .T_PARAM_PDN_TO_VALID_WIDTH                             (T_PARAM_PDN_TO_VALID_WIDTH                             ),
+        .T_PARAM_SRF_TO_VALID_WIDTH                             (T_PARAM_SRF_TO_VALID_WIDTH                             ),
+        .T_PARAM_SRF_TO_ZQ_CAL_WIDTH                            (T_PARAM_SRF_TO_ZQ_CAL_WIDTH                            ),
+        .T_PARAM_ARF_PERIOD_WIDTH                               (T_PARAM_ARF_PERIOD_WIDTH                               ),
+        .T_PARAM_PDN_PERIOD_WIDTH                               (T_PARAM_PDN_PERIOD_WIDTH                               ),
+        .T_PARAM_POWER_SAVING_EXIT_WIDTH                        (T_PARAM_POWER_SAVING_EXIT_WIDTH                        ),
+        .T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH                     (T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH                     )
+    )
+    timing_param_inst
+    (
+        .ctl_clk                                                (ctl_clk                                                ),
+        .ctl_reset_n                                            (ctl_reset_n                                            ),
+        .cfg_burst_length                                       (cfg_burst_length                                       ),
+        .cfg_type                                               (cfg_type                                               ),
+        .cfg_cas_wr_lat                                         (cfg_cas_wr_lat                                         ),
+        .cfg_add_lat                                            (cfg_add_lat                                            ),
+        .cfg_tcl                                                (cfg_tcl                                                ),
+        .cfg_trrd                                               (cfg_trrd                                               ),
+        .cfg_tfaw                                               (cfg_tfaw                                               ),
+        .cfg_trfc                                               (cfg_trfc                                               ),
+        .cfg_trefi                                              (cfg_trefi                                              ),
+        .cfg_trcd                                               (cfg_trcd                                               ),
+        .cfg_trp                                                (cfg_trp                                                ),
+        .cfg_twr                                                (cfg_twr                                                ),
+        .cfg_twtr                                               (cfg_twtr                                               ),
+        .cfg_trtp                                               (cfg_trtp                                               ),
+        .cfg_tras                                               (cfg_tras                                               ),
+        .cfg_trc                                                (cfg_trc                                                ),
+        .cfg_tccd                                               (cfg_tccd                                               ),
+        .cfg_tmrd                                               (cfg_tmrd                                               ),
+        .cfg_self_rfsh_exit_cycles                              (cfg_self_rfsh_exit_cycles                              ),
+        .cfg_pdn_exit_cycles                                    (cfg_pdn_exit_cycles                                    ),
+        .cfg_auto_pd_cycles                                     (cfg_auto_pd_cycles                                     ),
+        .cfg_power_saving_exit_cycles                           (cfg_power_saving_exit_cycles                           ),
+        .cfg_mem_clk_entry_cycles                               (cfg_mem_clk_entry_cycles                               ),
+        .cfg_extra_ctl_clk_act_to_rdwr                          (cfg_extra_ctl_clk_act_to_rdwr                          ),
+        .cfg_extra_ctl_clk_act_to_pch                           (cfg_extra_ctl_clk_act_to_pch                           ),
+        .cfg_extra_ctl_clk_act_to_act                           (cfg_extra_ctl_clk_act_to_act                           ),
+        .cfg_extra_ctl_clk_rd_to_rd                             (cfg_extra_ctl_clk_rd_to_rd                             ),
+        .cfg_extra_ctl_clk_rd_to_rd_diff_chip                   (cfg_extra_ctl_clk_rd_to_rd_diff_chip                   ),
+        .cfg_extra_ctl_clk_rd_to_wr                             (cfg_extra_ctl_clk_rd_to_wr                             ),
+        .cfg_extra_ctl_clk_rd_to_wr_bc                          (cfg_extra_ctl_clk_rd_to_wr_bc                          ),
+        .cfg_extra_ctl_clk_rd_to_wr_diff_chip                   (cfg_extra_ctl_clk_rd_to_wr_diff_chip                   ),
+        .cfg_extra_ctl_clk_rd_to_pch                            (cfg_extra_ctl_clk_rd_to_pch                            ),
+        .cfg_extra_ctl_clk_rd_ap_to_valid                       (cfg_extra_ctl_clk_rd_ap_to_valid                       ),
+        .cfg_extra_ctl_clk_wr_to_wr                             (cfg_extra_ctl_clk_wr_to_wr                             ),
+        .cfg_extra_ctl_clk_wr_to_wr_diff_chip                   (cfg_extra_ctl_clk_wr_to_wr_diff_chip                   ),
+        .cfg_extra_ctl_clk_wr_to_rd                             (cfg_extra_ctl_clk_wr_to_rd                             ),
+        .cfg_extra_ctl_clk_wr_to_rd_bc                          (cfg_extra_ctl_clk_wr_to_rd_bc                          ),
+        .cfg_extra_ctl_clk_wr_to_rd_diff_chip                   (cfg_extra_ctl_clk_wr_to_rd_diff_chip                   ),
+        .cfg_extra_ctl_clk_wr_to_pch                            (cfg_extra_ctl_clk_wr_to_pch                            ),
+        .cfg_extra_ctl_clk_wr_ap_to_valid                       (cfg_extra_ctl_clk_wr_ap_to_valid                       ),
+        .cfg_extra_ctl_clk_pch_to_valid                         (cfg_extra_ctl_clk_pch_to_valid                         ),
+        .cfg_extra_ctl_clk_pch_all_to_valid                     (cfg_extra_ctl_clk_pch_all_to_valid                     ),
+        .cfg_extra_ctl_clk_act_to_act_diff_bank                 (cfg_extra_ctl_clk_act_to_act_diff_bank                 ),
+        .cfg_extra_ctl_clk_four_act_to_act                      (cfg_extra_ctl_clk_four_act_to_act                      ),
+        .cfg_extra_ctl_clk_arf_to_valid                         (cfg_extra_ctl_clk_arf_to_valid                         ),
+        .cfg_extra_ctl_clk_pdn_to_valid                         (cfg_extra_ctl_clk_pdn_to_valid                         ),
+        .cfg_extra_ctl_clk_srf_to_valid                         (cfg_extra_ctl_clk_srf_to_valid                         ),
+        .cfg_extra_ctl_clk_srf_to_zq_cal                        (cfg_extra_ctl_clk_srf_to_zq_cal                        ),
+        .cfg_extra_ctl_clk_arf_period                           (cfg_extra_ctl_clk_arf_period                           ),
+        .cfg_extra_ctl_clk_pdn_period                           (cfg_extra_ctl_clk_pdn_period                           ),
+        .t_param_act_to_rdwr                                    (t_param_act_to_rdwr                                    ),
+        .t_param_act_to_pch                                     (t_param_act_to_pch                                     ),
+        .t_param_act_to_act                                     (t_param_act_to_act                                     ),
+        .t_param_rd_to_rd                                       (t_param_rd_to_rd                                       ),
+        .t_param_rd_to_rd_diff_chip                             (t_param_rd_to_rd_diff_chip                             ),
+        .t_param_rd_to_wr                                       (t_param_rd_to_wr                                       ),
+        .t_param_rd_to_wr_bc                                    (t_param_rd_to_wr_bc                                    ),
+        .t_param_rd_to_wr_diff_chip                             (t_param_rd_to_wr_diff_chip                             ),
+        .t_param_rd_to_pch                                      (t_param_rd_to_pch                                      ),
+        .t_param_rd_ap_to_valid                                 (t_param_rd_ap_to_valid                                 ),
+        .t_param_wr_to_wr                                       (t_param_wr_to_wr                                       ),
+        .t_param_wr_to_wr_diff_chip                             (t_param_wr_to_wr_diff_chip                             ),
+        .t_param_wr_to_rd                                       (t_param_wr_to_rd                                       ),
+        .t_param_wr_to_rd_bc                                    (t_param_wr_to_rd_bc                                    ),
+        .t_param_wr_to_rd_diff_chip                             (t_param_wr_to_rd_diff_chip                             ),
+        .t_param_wr_to_pch                                      (t_param_wr_to_pch                                      ),
+        .t_param_wr_ap_to_valid                                 (t_param_wr_ap_to_valid                                 ),
+        .t_param_pch_to_valid                                   (t_param_pch_to_valid                                   ),
+        .t_param_pch_all_to_valid                               (t_param_pch_all_to_valid                               ),
+        .t_param_act_to_act_diff_bank                           (t_param_act_to_act_diff_bank                           ),
+        .t_param_four_act_to_act                                (t_param_four_act_to_act                                ),
+        .t_param_arf_to_valid                                   (t_param_arf_to_valid                                   ),
+        .t_param_pdn_to_valid                                   (t_param_pdn_to_valid                                   ),
+        .t_param_srf_to_valid                                   (t_param_srf_to_valid                                   ),
+        .t_param_srf_to_zq_cal                                  (t_param_srf_to_zq_cal                                  ),
+        .t_param_arf_period                                     (t_param_arf_period                                     ),
+        .t_param_pdn_period                                     (t_param_pdn_period                                     ),
+        .t_param_power_saving_exit                              (t_param_power_saving_exit                              ),
+        .t_param_mem_clk_entry_cycles                           (t_param_mem_clk_entry_cycles                           )
+    );
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v
new file mode 100644
index 0000000..bd60d6c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v
@@ -0,0 +1,1208 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//////////////////////////////////////////////////////////////////////////////
+// This module is a ST wrapper for the soft IP NextGen controller and the MMR
+//////////////////////////////////////////////////////////////////////////////
+
+//altera message_off 10230
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_controller_st_top(
+    clk,
+    half_clk,
+    reset_n,
+    itf_cmd_ready,
+    itf_cmd_valid,
+    itf_cmd,
+    itf_cmd_address,
+    itf_cmd_burstlen,
+    itf_cmd_id,
+    itf_cmd_priority,
+    itf_cmd_autopercharge,
+    itf_cmd_multicast,
+    itf_wr_data_ready,
+    itf_wr_data_valid,
+    itf_wr_data,
+    itf_wr_data_byte_en,
+    itf_wr_data_begin,
+    itf_wr_data_last,
+    itf_wr_data_id,
+    itf_rd_data_ready,
+    itf_rd_data_valid,
+    itf_rd_data,
+    itf_rd_data_error,
+    itf_rd_data_begin,
+    itf_rd_data_last,
+    itf_rd_data_id,
+    afi_rst_n,
+    afi_cs_n,
+    afi_cke,
+    afi_odt,
+    afi_addr,
+    afi_ba,
+    afi_ras_n,
+    afi_cas_n,
+    afi_we_n,
+    afi_dqs_burst,
+    afi_wdata_valid,
+    afi_wdata,
+    afi_dm,
+    afi_wlat,
+    afi_rdata_en,
+    afi_rdata_en_full,
+    afi_rdata,
+    afi_rdata_valid,
+    afi_rrank,
+    afi_wrank,
+    afi_rlat,
+    afi_cal_success,
+    afi_cal_fail,
+    afi_cal_req,
+    afi_init_req,
+    afi_mem_clk_disable,
+    afi_cal_byte_lane_sel_n,
+    afi_ctl_refresh_done,
+    afi_seq_busy,
+    afi_ctl_long_idle,
+    local_init_done,
+    local_refresh_ack,
+    local_powerdn_ack,
+    local_self_rfsh_ack,
+	local_deep_powerdn_ack,
+    local_refresh_req,
+    local_refresh_chip,
+    local_powerdn_req,
+    local_self_rfsh_req,
+    local_self_rfsh_chip,
+	local_deep_powerdn_req,
+	local_deep_powerdn_chip,
+    local_zqcal_req,
+    local_zqcal_chip,
+    local_multicast,
+    local_priority,
+    ecc_interrupt,
+    csr_read_req,
+    csr_write_req,
+    csr_burst_count,
+    csr_beginbursttransfer,
+    csr_addr,
+    csr_wdata,
+    csr_rdata,
+    csr_be,
+    csr_rdata_valid,
+    csr_waitrequest,
+    tbp_empty,
+    cmd_gen_busy,
+    sideband_in_refresh
+);
+
+//////////////////////////////////////////////////////////////////////////////
+parameter LOCAL_SIZE_WIDTH                          = "";
+parameter LOCAL_ADDR_WIDTH                          = "";
+parameter LOCAL_DATA_WIDTH                          = "";
+parameter LOCAL_BE_WIDTH                            = "";
+parameter LOCAL_ID_WIDTH                            = "";
+parameter LOCAL_CS_WIDTH                            = "";
+parameter MEM_IF_ADDR_WIDTH                         = "";
+parameter MEM_IF_CLK_PAIR_COUNT                     = "";
+parameter LOCAL_IF_TYPE                             = "";
+parameter DWIDTH_RATIO                              = "";
+parameter CTL_ODT_ENABLED                           = "";
+parameter CTL_OUTPUT_REGD                           = "";
+parameter CTL_TBP_NUM                               = "";
+parameter WRBUFFER_ADDR_WIDTH                       = "";
+parameter RDBUFFER_ADDR_WIDTH                       = "";
+parameter MAX_PENDING_RD_CMD                        = 16;
+parameter MAX_PENDING_WR_CMD                        = 8;
+parameter MEM_IF_CS_WIDTH                           = "";
+parameter MEM_IF_CHIP                               = "";
+parameter MEM_IF_BANKADDR_WIDTH                     = "";
+parameter MEM_IF_ROW_WIDTH                          = "";
+parameter MEM_IF_COL_WIDTH                          = "";
+parameter MEM_IF_ODT_WIDTH                          = "";
+parameter MEM_IF_DQS_WIDTH                          = "";
+parameter MEM_IF_DWIDTH                             = "";
+parameter MEM_IF_DM_WIDTH                           = "";
+parameter MAX_MEM_IF_CS_WIDTH                       = "";
+parameter MAX_MEM_IF_CHIP                           = "";
+parameter MAX_MEM_IF_BANKADDR_WIDTH                 = "";
+parameter MAX_MEM_IF_ROWADDR_WIDTH                  = "";
+parameter MAX_MEM_IF_COLADDR_WIDTH                  = "";
+parameter MAX_MEM_IF_ODT_WIDTH                      = "";
+parameter MAX_MEM_IF_DQS_WIDTH                      = "";
+parameter MAX_MEM_IF_DQ_WIDTH                       = "";
+parameter MAX_MEM_IF_MASK_WIDTH                     = "";
+parameter MAX_LOCAL_DATA_WIDTH                      = "";
+parameter CFG_TYPE                                  = "";
+parameter CFG_INTERFACE_WIDTH                       = "";
+parameter CFG_BURST_LENGTH                          = "";
+parameter CFG_DEVICE_WIDTH                          = "";
+parameter CFG_REORDER_DATA                          = "";
+parameter CFG_DATA_REORDERING_TYPE                  = "";
+parameter CFG_STARVE_LIMIT                          = "";
+parameter CFG_ADDR_ORDER                            = "";
+parameter MEM_CAS_WR_LAT                            = "";
+parameter MEM_ADD_LAT                               = "";
+parameter MEM_TCL                                   = "";
+parameter MEM_TRRD                                  = "";
+parameter MEM_TFAW                                  = "";
+parameter MEM_TRFC                                  = "";
+parameter MEM_TREFI                                 = "";
+parameter MEM_TRCD                                  = "";
+parameter MEM_TRP                                   = "";
+parameter MEM_TWR                                   = "";
+parameter MEM_TWTR                                  = "";
+parameter MEM_TRTP                                  = "";
+parameter MEM_TRAS                                  = "";
+parameter MEM_TRC                                   = "";
+parameter CFG_TCCD                                  = "";
+parameter MEM_AUTO_PD_CYCLES                        = "";
+parameter CFG_SELF_RFSH_EXIT_CYCLES                 = "";
+parameter CFG_PDN_EXIT_CYCLES                       = "";
+parameter CFG_POWER_SAVING_EXIT_CYCLES              = "";
+parameter CFG_MEM_CLK_ENTRY_CYCLES                  = "";
+parameter MEM_TMRD_CK                               = "";
+parameter CTL_ECC_ENABLED                           = "";
+parameter CTL_ECC_RMW_ENABLED                       = "";
+parameter CTL_ECC_MULTIPLES_16_24_40_72             = "";
+parameter CFG_GEN_SBE                               = "";
+parameter CFG_GEN_DBE                               = "";
+parameter CFG_ENABLE_INTR                           = "";
+parameter CFG_MASK_SBE_INTR                         = "";
+parameter CFG_MASK_DBE_INTR                         = "";
+parameter CFG_MASK_CORRDROP_INTR                    = 0;
+parameter CFG_CLR_INTR                              = "";
+parameter CTL_USR_REFRESH                           = "";
+parameter CTL_REGDIMM_ENABLED                       = "";
+parameter CTL_ENABLE_BURST_INTERRUPT				= "";
+parameter CTL_ENABLE_BURST_TERMINATE				= "";
+parameter CFG_WRITE_ODT_CHIP                        = "";
+parameter CFG_READ_ODT_CHIP                         = "";
+parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP             = "";
+parameter CFG_PORT_WIDTH_READ_ODT_CHIP              = "";
+parameter MEM_IF_CKE_WIDTH                          = "";//check
+parameter CTL_CSR_ENABLED                           = "";
+parameter CFG_ENABLE_NO_DM                          = "";
+parameter CSR_ADDR_WIDTH                            = "";
+parameter CSR_DATA_WIDTH                            = "";
+parameter CSR_BE_WIDTH                              = "";
+parameter CFG_ENABLE_DQS_TRACKING                   = 0;
+parameter CFG_WLAT_BUS_WIDTH                        = 6;
+parameter CFG_RLAT_BUS_WIDTH                        = 6;
+parameter CFG_RRANK_BUS_WIDTH                       = 0;
+parameter CFG_WRANK_BUS_WIDTH                       = 0;
+parameter CFG_USE_SHADOW_REGS                       = 0;
+
+parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT            = "";
+parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT            = "";
+parameter CTL_RD_TO_PCH_EXTRA_CLK                   = 0;
+parameter CTL_RD_TO_RD_EXTRA_CLK                    = 0;
+parameter CTL_WR_TO_WR_EXTRA_CLK                    = 0;
+parameter CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK          = 0;
+parameter CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK          = 0;
+
+parameter CTL_ENABLE_WDATA_PATH_LATENCY             = 0;
+
+parameter CFG_ECC_DECODER_REG						= 0;
+parameter CFG_ERRCMD_FIFO_REG						= 0;
+
+parameter ENABLE_BURST_MERGE                        = 0;
+//////////////////////////////////////////////////////////////////////////////
+
+localparam CFG_LOCAL_SIZE_WIDTH                                 = LOCAL_SIZE_WIDTH;
+localparam CFG_LOCAL_ADDR_WIDTH                                 = LOCAL_ADDR_WIDTH;
+localparam CFG_LOCAL_DATA_WIDTH                                 = LOCAL_DATA_WIDTH;
+localparam CFG_LOCAL_BE_WIDTH                                   = LOCAL_BE_WIDTH;
+localparam CFG_LOCAL_ID_WIDTH                                   = LOCAL_ID_WIDTH;
+localparam CFG_LOCAL_IF_TYPE                                    = LOCAL_IF_TYPE;
+localparam CFG_MEM_IF_ADDR_WIDTH                                = MEM_IF_ADDR_WIDTH;
+localparam CFG_MEM_IF_CLK_PAIR_COUNT                            = MEM_IF_CLK_PAIR_COUNT;
+localparam CFG_DWIDTH_RATIO                                     = DWIDTH_RATIO;
+localparam CFG_ODT_ENABLED                                      = CTL_ODT_ENABLED;
+localparam CFG_CTL_TBP_NUM                                      = CTL_TBP_NUM;
+localparam CFG_WRBUFFER_ADDR_WIDTH                              = WRBUFFER_ADDR_WIDTH;
+localparam CFG_RDBUFFER_ADDR_WIDTH                              = RDBUFFER_ADDR_WIDTH;
+localparam CFG_MAX_PENDING_RD_CMD                               = MAX_PENDING_RD_CMD;
+localparam CFG_MAX_PENDING_WR_CMD                               = MAX_PENDING_WR_CMD;
+localparam CFG_MEM_IF_CS_WIDTH                                  = MEM_IF_CS_WIDTH;
+localparam CFG_MEM_IF_CHIP                                      = MEM_IF_CHIP;
+localparam CFG_MEM_IF_BA_WIDTH                                  = MEM_IF_BANKADDR_WIDTH;
+localparam CFG_MEM_IF_ROW_WIDTH                                 = MEM_IF_ROW_WIDTH;
+localparam CFG_MEM_IF_COL_WIDTH                                 = MEM_IF_COL_WIDTH;
+localparam CFG_MEM_IF_CKE_WIDTH                                 = MEM_IF_CKE_WIDTH;
+localparam CFG_MEM_IF_ODT_WIDTH                                 = MEM_IF_ODT_WIDTH;
+localparam CFG_MEM_IF_DQS_WIDTH                                 = MEM_IF_DQS_WIDTH;
+localparam CFG_MEM_IF_DQ_WIDTH                                  = MEM_IF_DWIDTH;
+localparam CFG_MEM_IF_DM_WIDTH                                  = MEM_IF_DM_WIDTH;
+localparam CFG_COL_ADDR_WIDTH                                   = MEM_IF_COL_WIDTH;
+localparam CFG_ROW_ADDR_WIDTH                                   = MEM_IF_ROW_WIDTH;
+localparam CFG_BANK_ADDR_WIDTH                                  = MEM_IF_BANKADDR_WIDTH;
+localparam CFG_CS_ADDR_WIDTH                                    = LOCAL_CS_WIDTH;
+localparam CFG_CAS_WR_LAT                                       = MEM_CAS_WR_LAT;
+localparam CFG_ADD_LAT                                          = MEM_ADD_LAT;
+localparam CFG_TCL                                              = MEM_TCL;
+localparam CFG_TRRD                                             = MEM_TRRD;
+localparam CFG_TFAW                                             = MEM_TFAW;
+localparam CFG_TRFC                                             = MEM_TRFC;
+localparam CFG_TREFI                                            = MEM_TREFI;
+localparam CFG_TRCD                                             = MEM_TRCD;
+localparam CFG_TRP                                              = MEM_TRP;
+localparam CFG_TWR                                              = MEM_TWR;
+localparam CFG_TWTR                                             = MEM_TWTR;
+localparam CFG_TRTP                                             = MEM_TRTP;
+localparam CFG_TRAS                                             = MEM_TRAS;
+localparam CFG_TRC                                              = MEM_TRC;
+localparam CFG_AUTO_PD_CYCLES                                   = MEM_AUTO_PD_CYCLES;
+localparam CFG_TMRD                                             = MEM_TMRD_CK;
+localparam CFG_ENABLE_ECC                                       = CTL_ECC_ENABLED;
+localparam CFG_ENABLE_AUTO_CORR                                 = CTL_ECC_RMW_ENABLED;
+localparam CFG_ECC_MULTIPLES_16_24_40_72                        = CTL_ECC_MULTIPLES_16_24_40_72;
+localparam CFG_ENABLE_ECC_CODE_OVERWRITES                       = 1'b1;
+localparam CFG_CAL_REQ                                          = 0;
+localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR                        = 0;
+localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH                         = 0;
+localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT                         = 0;
+localparam CFG_EXTRA_CTL_CLK_RD_TO_RD                           = 0 + CTL_RD_TO_RD_EXTRA_CLK;
+localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP                 = 0 + CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK;
+localparam CFG_EXTRA_CTL_CLK_RD_TO_WR                           = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC                        = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP                 = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH                          = 0 + CTL_RD_TO_PCH_EXTRA_CLK;
+localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID                     = 0;
+localparam CFG_EXTRA_CTL_CLK_WR_TO_WR                           = 0 + CTL_WR_TO_WR_EXTRA_CLK;
+localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP                 = 0 + CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK;
+localparam CFG_EXTRA_CTL_CLK_WR_TO_RD                           = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC                        = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP                 = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
+localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH                          = 0;
+localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID                     = 0;
+localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID                       = 0;
+localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID                   = 0;
+localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK               = 0;
+localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT                    = 0;
+localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID                       = 0;
+localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID                       = 0;
+localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID                       = 0;
+localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL                      = 0;
+localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD                         = 0;
+localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD                         = 0;
+localparam CFG_OUTPUT_REGD                                      = CTL_OUTPUT_REGD;
+localparam CFG_MASK_CORR_DROPPED_INTR                           = 0;
+localparam CFG_USER_RFSH                                        = CTL_USR_REFRESH;
+localparam CFG_REGDIMM_ENABLE                                   = CTL_REGDIMM_ENABLED;
+localparam CFG_ENABLE_BURST_INTERRUPT                           = CTL_ENABLE_BURST_INTERRUPT;
+localparam CFG_ENABLE_BURST_TERMINATE                           = CTL_ENABLE_BURST_TERMINATE;
+localparam CFG_ENABLE_WDATA_PATH_LATENCY                        = CTL_ENABLE_WDATA_PATH_LATENCY;
+localparam CFG_ENABLE_BURST_MERGE                               = ENABLE_BURST_MERGE; 
+
+localparam CFG_PORT_WIDTH_TYPE                                  = 3;
+localparam CFG_PORT_WIDTH_INTERFACE_WIDTH                       = 8;
+localparam CFG_PORT_WIDTH_BURST_LENGTH                          = 5;
+localparam CFG_PORT_WIDTH_DEVICE_WIDTH                          = 4;
+localparam CFG_PORT_WIDTH_REORDER_DATA                          = 1;
+localparam CFG_PORT_WIDTH_STARVE_LIMIT                          = 6;
+localparam CFG_PORT_WIDTH_OUTPUT_REGD                           = 2;
+localparam CFG_PORT_WIDTH_ADDR_ORDER                            = 2;
+localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH                        = 5;
+localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH                        = 5;
+localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH                       = 3;
+localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH                         = 3;
+localparam CFG_PORT_WIDTH_CAS_WR_LAT                            = 4;
+localparam CFG_PORT_WIDTH_ADD_LAT                               = 4;
+localparam CFG_PORT_WIDTH_TCL                                   = 4;
+localparam CFG_PORT_WIDTH_TRRD                                  = 4;
+localparam CFG_PORT_WIDTH_TFAW                                  = 6;
+localparam CFG_PORT_WIDTH_TRFC                                  = 9; //case:234203
+localparam CFG_PORT_WIDTH_TREFI                                 = 14; //case:234203
+localparam CFG_PORT_WIDTH_TRCD                                  = 4;
+localparam CFG_PORT_WIDTH_TRP                                   = 4;
+localparam CFG_PORT_WIDTH_TWR                                   = 5; //case:234203
+localparam CFG_PORT_WIDTH_TWTR                                  = 4;
+localparam CFG_PORT_WIDTH_TRTP                                  = 4;
+localparam CFG_PORT_WIDTH_TRAS                                  = 6; //case:234203
+localparam CFG_PORT_WIDTH_TRC                                   = 6;
+localparam CFG_PORT_WIDTH_TCCD                                  = 4;
+localparam CFG_PORT_WIDTH_TMRD                                  = 3;
+localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES                 = 10;
+localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES                       = 4;
+localparam CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES              = 4;
+localparam CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                  = ((CTL_REGDIMM_ENABLED == 1) ? 13 : 6);
+localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES                        = 16;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR             = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH              = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT              = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD                = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP      = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR                = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC             = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP      = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH               = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID          = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR                = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP      = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD                = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC             = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP      = 4;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH               = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID          = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID            = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID        = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK    = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT         = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID            = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID            = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID            = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL           = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD              = 1;
+localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD              = 1;
+localparam CFG_PORT_WIDTH_ENABLE_ECC                            = 1;
+localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR                      = 1;
+localparam CFG_PORT_WIDTH_GEN_SBE                               = 1;
+localparam CFG_PORT_WIDTH_GEN_DBE                               = 1;
+localparam CFG_PORT_WIDTH_ENABLE_INTR                           = 1;
+localparam CFG_PORT_WIDTH_MASK_SBE_INTR                         = 1;
+localparam CFG_PORT_WIDTH_MASK_DBE_INTR                         = 1;
+localparam CFG_PORT_WIDTH_CLR_INTR                              = 1;
+localparam CFG_PORT_WIDTH_USER_RFSH                             = 1;
+localparam CFG_PORT_WIDTH_SELF_RFSH                             = 1;
+localparam CFG_PORT_WIDTH_REGDIMM_ENABLE                        = 1;
+localparam CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT                = 1;
+localparam CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE                = 1;
+localparam CFG_RDATA_RETURN_MODE                                = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
+
+localparam CFG_LPDDR2_ENABLED                                   = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
+localparam CFG_ADDR_RATE_RATIO                                  = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
+localparam CFG_AFI_IF_FR_ADDR_WIDTH                             = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
+
+localparam STS_PORT_WIDTH_SBE_ERROR                             = 1;
+localparam STS_PORT_WIDTH_DBE_ERROR                             = 1;
+localparam STS_PORT_WIDTH_CORR_DROP_ERROR                       = 1;
+localparam STS_PORT_WIDTH_SBE_COUNT                             = 8;
+localparam STS_PORT_WIDTH_DBE_COUNT                             = 8;
+localparam STS_PORT_WIDTH_CORR_DROP_COUNT                       = 8;
+
+// We are supposed to use these parameters when the CSR is enabled
+// but the MAX_ parameters are not defined
+//localparam AFI_CS_WIDTH                                         = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
+//localparam AFI_CKE_WIDTH                                        = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
+//localparam AFI_ODT_WIDTH                                        = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
+//localparam AFI_ADDR_WIDTH                                       = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
+//localparam AFI_BA_WIDTH                                         = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
+//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH                        = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
+
+localparam AFI_CS_WIDTH                                         = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_CKE_WIDTH                                        = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_ODT_WIDTH                                        = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_ADDR_WIDTH                                       = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_BA_WIDTH                                         = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH                        = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
+
+localparam AFI_CMD_WIDTH                                        = (CFG_DWIDTH_RATIO / 2);
+localparam AFI_DQS_BURST_WIDTH                                  = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_WDATA_VALID_WIDTH                                = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_WDATA_WIDTH                                      = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
+localparam AFI_DM_WIDTH                                         = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
+localparam AFI_WLAT_WIDTH                                       = CFG_WLAT_BUS_WIDTH;
+localparam AFI_RDATA_EN_WIDTH                                   = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
+localparam AFI_RDATA_WIDTH                                      = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
+localparam AFI_RDATA_VALID_WIDTH                                = (CFG_DWIDTH_RATIO / 2);
+localparam AFI_RRANK_WIDTH                                      = CFG_RRANK_BUS_WIDTH;
+localparam AFI_WRANK_WIDTH                                      = CFG_WRANK_BUS_WIDTH;
+localparam AFI_RLAT_WIDTH                                       = CFG_RLAT_BUS_WIDTH;
+localparam AFI_OTF_BITNUM                                       = 12;
+localparam AFI_AUTO_PRECHARGE_BITNUM                            = 10;
+localparam AFI_MEM_CLK_DISABLE_WIDTH                            = CFG_MEM_IF_CLK_PAIR_COUNT;
+
+//////////////////////////////////////////////////////////////////////////////
+// BEGIN PORT SECTION
+
+// Clk and reset signals
+input                                                                  clk;
+input                                                                  half_clk;
+input                                                                  reset_n;
+
+// Command channel
+output                                                                 itf_cmd_ready;
+input                                                                  itf_cmd_valid;
+input                                                                  itf_cmd;
+input   [CFG_LOCAL_ADDR_WIDTH                              - 1 : 0]    itf_cmd_address;
+input   [CFG_LOCAL_SIZE_WIDTH                              - 1 : 0]    itf_cmd_burstlen;
+input   [CFG_LOCAL_ID_WIDTH                                - 1 : 0]    itf_cmd_id;
+input                                                                  itf_cmd_priority;
+input                                                                  itf_cmd_autopercharge;
+input                                                                  itf_cmd_multicast;
+// Write data channel
+output                                                                 itf_wr_data_ready;
+input                                                                  itf_wr_data_valid;
+input   [CFG_LOCAL_DATA_WIDTH                              - 1 : 0]    itf_wr_data;
+input   [CFG_LOCAL_BE_WIDTH                                - 1 : 0]    itf_wr_data_byte_en;
+input                                                                  itf_wr_data_begin;
+input                                                                  itf_wr_data_last;
+input   [CFG_LOCAL_ID_WIDTH                                - 1 : 0]    itf_wr_data_id;
+// Read data channel
+input                                                                  itf_rd_data_ready;
+output                                                                 itf_rd_data_valid;
+output  [CFG_LOCAL_DATA_WIDTH                              - 1 : 0]    itf_rd_data;
+output                                                                 itf_rd_data_error;
+output                                                                 itf_rd_data_begin;
+output                                                                 itf_rd_data_last;
+output  [CFG_LOCAL_ID_WIDTH                                - 1 : 0]    itf_rd_data_id;
+
+// AFI signals
+output  [AFI_CMD_WIDTH                                     - 1 : 0]    afi_rst_n;
+output  [AFI_CS_WIDTH                                      - 1 : 0]    afi_cs_n;
+output  [AFI_CKE_WIDTH                                     - 1 : 0]    afi_cke;
+output  [AFI_ODT_WIDTH                                     - 1 : 0]    afi_odt;
+output  [AFI_ADDR_WIDTH                                    - 1 : 0]    afi_addr;
+output  [AFI_BA_WIDTH                                      - 1 : 0]    afi_ba;
+output  [AFI_CMD_WIDTH                                     - 1 : 0]    afi_ras_n;
+output  [AFI_CMD_WIDTH                                     - 1 : 0]    afi_cas_n;
+output  [AFI_CMD_WIDTH                                     - 1 : 0]    afi_we_n;
+output  [AFI_DQS_BURST_WIDTH                               - 1 : 0]    afi_dqs_burst;
+output  [AFI_WDATA_VALID_WIDTH                             - 1 : 0]    afi_wdata_valid;
+output  [AFI_WDATA_WIDTH                                   - 1 : 0]    afi_wdata;
+output  [AFI_DM_WIDTH                                      - 1 : 0]    afi_dm;
+input   [AFI_WLAT_WIDTH                                    - 1 : 0]    afi_wlat;
+output  [AFI_RDATA_EN_WIDTH                                - 1 : 0]    afi_rdata_en;
+output  [AFI_RDATA_EN_WIDTH                                - 1 : 0]    afi_rdata_en_full;
+output  [AFI_RRANK_WIDTH                                   - 1 : 0]    afi_rrank;
+output  [AFI_WRANK_WIDTH                                   - 1 : 0]    afi_wrank;
+input   [AFI_RDATA_WIDTH                                   - 1 : 0]    afi_rdata;
+input   [AFI_RDATA_VALID_WIDTH                             - 1 : 0]    afi_rdata_valid;
+input   [AFI_RLAT_WIDTH                                    - 1 : 0]    afi_rlat;
+input                                                                  afi_cal_success;
+input                                                                  afi_cal_fail;
+output                                                                 afi_cal_req;
+output                                                                 afi_init_req;
+output  [AFI_MEM_CLK_DISABLE_WIDTH                         - 1 : 0]    afi_mem_clk_disable;
+output  [AFI_CAL_BYTE_LANE_SEL_N_WIDTH                     - 1 : 0]    afi_cal_byte_lane_sel_n;
+output  [CFG_MEM_IF_CHIP                                   - 1 : 0]    afi_ctl_refresh_done;
+input   [CFG_MEM_IF_CHIP                                   - 1 : 0]    afi_seq_busy;
+output  [CFG_MEM_IF_CHIP                                   - 1 : 0]    afi_ctl_long_idle;
+
+// Sideband signals
+output                                                                 local_init_done;
+output                                                                 local_refresh_ack;
+output                                                                 local_powerdn_ack;
+output                                                                 local_self_rfsh_ack;
+output  															   local_deep_powerdn_ack;
+input                                                                  local_refresh_req;
+input   [CFG_MEM_IF_CHIP                                   - 1 : 0]    local_refresh_chip;
+input                                                                  local_powerdn_req;
+input                                                                  local_self_rfsh_req;
+input   [CFG_MEM_IF_CHIP                                   - 1 : 0]    local_self_rfsh_chip;
+input																   local_deep_powerdn_req;
+input   [CFG_MEM_IF_CHIP                                   - 1 : 0]    local_deep_powerdn_chip;
+input																   local_zqcal_req;
+input   [CFG_MEM_IF_CHIP                                   - 1 : 0]    local_zqcal_chip;
+input                                                                  local_multicast;
+input                                                                  local_priority;
+
+// Csr & ecc signals
+output                                                                 ecc_interrupt;
+input                                                                  csr_read_req;
+input                                                                  csr_write_req;
+input   [1                                                 - 1 : 0]    csr_burst_count;
+input                                                                  csr_beginbursttransfer;
+input   [CSR_ADDR_WIDTH                                    - 1 : 0]    csr_addr;
+input   [CSR_DATA_WIDTH                                    - 1 : 0]    csr_wdata;
+output  [CSR_DATA_WIDTH                                    - 1 : 0]    csr_rdata;
+input   [CSR_BE_WIDTH                                      - 1 : 0]    csr_be;
+output                                                                 csr_rdata_valid;
+output                                                                 csr_waitrequest;
+
+// Refresh controller signals
+	output 															   tbp_empty;
+	output 															   cmd_gen_busy;
+	output 															   sideband_in_refresh;
+
+// END PORT SECTION
+//////////////////////////////////////////////////////////////////////////////
+
+wire    [CFG_PORT_WIDTH_TYPE                               - 1 : 0]    cfg_type;
+wire    [CFG_PORT_WIDTH_BURST_LENGTH                       - 1 : 0]    cfg_burst_length;
+wire    [CFG_PORT_WIDTH_ADDR_ORDER                         - 1 : 0]    cfg_addr_order;
+wire                                                                   cfg_enable_ecc;
+wire                                                                   cfg_enable_auto_corr;
+wire                                                                   cfg_gen_sbe;
+wire                                                                   cfg_gen_dbe;
+wire                                                                   cfg_reorder_data;
+wire                                                                   cfg_user_rfsh;
+wire                                                                   cfg_regdimm_enable;
+wire                                                                   cfg_enable_burst_interrupt;
+wire                                                                   cfg_enable_burst_terminate;
+wire                                                                   cfg_enable_dqs_tracking;
+wire    [CFG_PORT_WIDTH_OUTPUT_REGD                        - 1 : 0]    cfg_output_regd;
+wire                                                                   cfg_enable_no_dm;
+wire                                                                   cfg_enable_ecc_code_overwrites;
+wire    [CFG_PORT_WIDTH_CAS_WR_LAT                         - 1 : 0]    cfg_cas_wr_lat;
+wire    [CFG_PORT_WIDTH_ADD_LAT                            - 1 : 0]    cfg_add_lat;
+wire    [CFG_PORT_WIDTH_TCL                                - 1 : 0]    cfg_tcl;
+wire    [CFG_PORT_WIDTH_TRRD                               - 1 : 0]    cfg_trrd;
+wire    [CFG_PORT_WIDTH_TFAW                               - 1 : 0]    cfg_tfaw;
+wire    [CFG_PORT_WIDTH_TRFC                               - 1 : 0]    cfg_trfc;
+wire    [CFG_PORT_WIDTH_TREFI                              - 1 : 0]    cfg_trefi;
+wire    [CFG_PORT_WIDTH_TRCD                               - 1 : 0]    cfg_trcd;
+wire    [CFG_PORT_WIDTH_TRP                                - 1 : 0]    cfg_trp;
+wire    [CFG_PORT_WIDTH_TWR                                - 1 : 0]    cfg_twr;
+wire    [CFG_PORT_WIDTH_TWTR                               - 1 : 0]    cfg_twtr;
+wire    [CFG_PORT_WIDTH_TRTP                               - 1 : 0]    cfg_trtp;
+wire    [CFG_PORT_WIDTH_TRAS                               - 1 : 0]    cfg_tras;
+wire    [CFG_PORT_WIDTH_TRC                                - 1 : 0]    cfg_trc;
+wire    [CFG_PORT_WIDTH_AUTO_PD_CYCLES                     - 1 : 0]    cfg_auto_pd_cycles;
+wire    [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES              - 1 : 0]    cfg_self_rfsh_exit_cycles;
+wire    [CFG_PORT_WIDTH_PDN_EXIT_CYCLES                    - 1 : 0]    cfg_pdn_exit_cycles;
+wire    [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES           - 1 : 0]    cfg_power_saving_exit_cycles;
+wire    [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES               - 1 : 0]    cfg_mem_clk_entry_cycles;
+wire    [CFG_PORT_WIDTH_TMRD                               - 1 : 0]    cfg_tmrd;
+wire    [CFG_PORT_WIDTH_COL_ADDR_WIDTH                     - 1 : 0]    cfg_col_addr_width;
+wire    [CFG_PORT_WIDTH_ROW_ADDR_WIDTH                     - 1 : 0]    cfg_row_addr_width;
+wire    [CFG_PORT_WIDTH_BANK_ADDR_WIDTH                    - 1 : 0]    cfg_bank_addr_width;
+wire    [CFG_PORT_WIDTH_CS_ADDR_WIDTH                      - 1 : 0]    cfg_cs_addr_width;
+wire                                                                   cfg_enable_intr;
+wire                                                                   cfg_mask_sbe_intr;
+wire                                                                   cfg_mask_dbe_intr;
+wire                                                                   cfg_clr_intr;
+wire                                                                   cfg_cal_req;
+
+wire    [4                                                 - 1 : 0]    cfg_clock_off;
+wire                                                                   cfg_self_rfsh;
+wire                                                                   cfg_ganged_arf;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR          - 1 : 0]    cfg_extra_ctl_clk_act_to_rdwr;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH           - 1 : 0]    cfg_extra_ctl_clk_act_to_pch;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT           - 1 : 0]    cfg_extra_ctl_clk_act_to_act;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD             - 1 : 0]    cfg_extra_ctl_clk_rd_to_rd;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP   - 1 : 0]    cfg_extra_ctl_clk_rd_to_rd_diff_chip;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR             - 1 : 0]    cfg_extra_ctl_clk_rd_to_wr;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC          - 1 : 0]    cfg_extra_ctl_clk_rd_to_wr_bc;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP   - 1 : 0]    cfg_extra_ctl_clk_rd_to_wr_diff_chip;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH            - 1 : 0]    cfg_extra_ctl_clk_rd_to_pch;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID       - 1 : 0]    cfg_extra_ctl_clk_rd_ap_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR             - 1 : 0]    cfg_extra_ctl_clk_wr_to_wr;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP   - 1 : 0]    cfg_extra_ctl_clk_wr_to_wr_diff_chip;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD             - 1 : 0]    cfg_extra_ctl_clk_wr_to_rd;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC          - 1 : 0]    cfg_extra_ctl_clk_wr_to_rd_bc;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP   - 1 : 0]    cfg_extra_ctl_clk_wr_to_rd_diff_chip;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH            - 1 : 0]    cfg_extra_ctl_clk_wr_to_pch;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID       - 1 : 0]    cfg_extra_ctl_clk_wr_ap_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID         - 1 : 0]    cfg_extra_ctl_clk_pch_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID     - 1 : 0]    cfg_extra_ctl_clk_pch_all_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0]    cfg_extra_ctl_clk_act_to_act_diff_bank;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT      - 1 : 0]    cfg_extra_ctl_clk_four_act_to_act;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID         - 1 : 0]    cfg_extra_ctl_clk_arf_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID         - 1 : 0]    cfg_extra_ctl_clk_pdn_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID         - 1 : 0]    cfg_extra_ctl_clk_srf_to_valid;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL        - 1 : 0]    cfg_extra_ctl_clk_srf_to_zq_cal;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD           - 1 : 0]    cfg_extra_ctl_clk_arf_period;
+wire    [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD           - 1 : 0]    cfg_extra_ctl_clk_pdn_period;
+wire    [CFG_PORT_WIDTH_STARVE_LIMIT                       - 1 : 0]    cfg_starve_limit;
+wire    [CFG_PORT_WIDTH_WRITE_ODT_CHIP                     - 1 : 0]    cfg_write_odt_chip;
+wire    [CFG_PORT_WIDTH_READ_ODT_CHIP                      - 1 : 0]    cfg_read_odt_chip;
+wire    [CFG_PORT_WIDTH_INTERFACE_WIDTH                    - 1 : 0]    cfg_interface_width;
+wire    [CFG_PORT_WIDTH_DEVICE_WIDTH                       - 1 : 0]    cfg_device_width;
+wire    [CFG_PORT_WIDTH_TCCD                               - 1 : 0]    cfg_tccd;
+wire                                                                   cfg_mask_corr_dropped_intr;
+wire    [2                                                 - 1 : 0]    cfg_mem_bl;
+wire                                                                   cfg_user_ecc_en;
+
+//ECC related outputs from controller to csr
+wire    [STS_PORT_WIDTH_SBE_ERROR                          - 1 : 0]    sts_sbe_error;
+wire    [STS_PORT_WIDTH_DBE_ERROR                          - 1 : 0]    sts_dbe_error;
+wire    [STS_PORT_WIDTH_SBE_COUNT                          - 1 : 0]    sts_sbe_count;
+wire    [STS_PORT_WIDTH_DBE_COUNT                          - 1 : 0]    sts_dbe_count;
+wire    [CFG_LOCAL_ADDR_WIDTH                              - 1 : 0]    sts_err_addr;
+wire    [STS_PORT_WIDTH_CORR_DROP_ERROR                    - 1 : 0]    sts_corr_dropped;
+wire    [STS_PORT_WIDTH_CORR_DROP_COUNT                    - 1 : 0]    sts_corr_dropped_count;
+wire    [CFG_LOCAL_ADDR_WIDTH                              - 1 : 0]    sts_corr_dropped_addr;
+
+//
+// Reconfiguration Support
+//
+// cfg_* signals may be reconfigured to different values using the Configuration Status Registers
+//      - some cfg_* signals are not reconfigurable, and are always assigned to parameters
+//      - When CSR is not enabled
+//          - cfg_* signals are assigned to parameters
+//      - when CSR is enabled
+//          - cfg_* signals are assigned to csr_* signals
+//              - csr_* signal generation based on Configuration Registers
+//              - default value for csr_* signals are based on parameters
+
+// cfg_* signals that are not reconfigurable
+       assign   cfg_type                                = CFG_TYPE;
+       assign   cfg_interface_width                     = CFG_INTERFACE_WIDTH;
+       assign   cfg_device_width                        = CFG_DEVICE_WIDTH;
+       assign   cfg_enable_ecc_code_overwrites          = CFG_ENABLE_ECC_CODE_OVERWRITES;
+       assign   cfg_enable_no_dm                        = CFG_ENABLE_NO_DM;
+       assign   cfg_output_regd                         = CFG_OUTPUT_REGD;
+       assign   cfg_pdn_exit_cycles                     = CFG_PDN_EXIT_CYCLES;
+       assign   cfg_power_saving_exit_cycles            = CFG_POWER_SAVING_EXIT_CYCLES;
+       assign   cfg_mem_clk_entry_cycles                = CFG_MEM_CLK_ENTRY_CYCLES;
+       assign   cfg_self_rfsh_exit_cycles               = CFG_SELF_RFSH_EXIT_CYCLES;
+       assign   cfg_tccd                                = CFG_TCCD;
+       assign   cfg_tmrd                                = CFG_TMRD;
+       assign   cfg_user_rfsh                           = CFG_USER_RFSH;
+       assign   cfg_write_odt_chip                      = CFG_WRITE_ODT_CHIP;
+       assign   cfg_read_odt_chip                       = CFG_READ_ODT_CHIP;
+       assign   cfg_enable_dqs_tracking                 = CFG_ENABLE_DQS_TRACKING;
+       assign   cfg_enable_burst_interrupt              = CFG_ENABLE_BURST_INTERRUPT;
+       assign   cfg_enable_burst_terminate              = CFG_ENABLE_BURST_TERMINATE;
+       assign   cfg_extra_ctl_clk_act_to_rdwr           = CFG_EXTRA_CTL_CLK_ACT_TO_RDWR;
+       assign   cfg_extra_ctl_clk_act_to_pch            = CFG_EXTRA_CTL_CLK_ACT_TO_PCH;
+       assign   cfg_extra_ctl_clk_act_to_act            = CFG_EXTRA_CTL_CLK_ACT_TO_ACT;
+       assign   cfg_extra_ctl_clk_rd_to_rd              = CFG_EXTRA_CTL_CLK_RD_TO_RD;
+       assign   cfg_extra_ctl_clk_rd_to_rd_diff_chip    = CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP;
+       assign   cfg_extra_ctl_clk_rd_to_wr              = CFG_EXTRA_CTL_CLK_RD_TO_WR;
+       assign   cfg_extra_ctl_clk_rd_to_wr_bc           = CFG_EXTRA_CTL_CLK_RD_TO_WR_BC;
+       assign   cfg_extra_ctl_clk_rd_to_wr_diff_chip    = CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP;
+       assign   cfg_extra_ctl_clk_rd_to_pch             = CFG_EXTRA_CTL_CLK_RD_TO_PCH;
+       assign   cfg_extra_ctl_clk_rd_ap_to_valid        = CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID;
+       assign   cfg_extra_ctl_clk_wr_to_wr              = CFG_EXTRA_CTL_CLK_WR_TO_WR;
+       assign   cfg_extra_ctl_clk_wr_to_wr_diff_chip    = CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP;
+       assign   cfg_extra_ctl_clk_wr_to_rd              = CFG_EXTRA_CTL_CLK_WR_TO_RD;
+       assign   cfg_extra_ctl_clk_wr_to_rd_bc           = CFG_EXTRA_CTL_CLK_WR_TO_RD_BC;
+       assign   cfg_extra_ctl_clk_wr_to_rd_diff_chip    = CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP;
+       assign   cfg_extra_ctl_clk_wr_to_pch             = CFG_EXTRA_CTL_CLK_WR_TO_PCH;
+       assign   cfg_extra_ctl_clk_wr_ap_to_valid        = CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID;
+       assign   cfg_extra_ctl_clk_pch_to_valid          = CFG_EXTRA_CTL_CLK_PCH_TO_VALID;
+       assign   cfg_extra_ctl_clk_pch_all_to_valid      = CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID;
+       assign   cfg_extra_ctl_clk_act_to_act_diff_bank  = CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK;
+       assign   cfg_extra_ctl_clk_four_act_to_act       = CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT;
+       assign   cfg_extra_ctl_clk_arf_to_valid          = CFG_EXTRA_CTL_CLK_ARF_TO_VALID;
+       assign   cfg_extra_ctl_clk_pdn_to_valid          = CFG_EXTRA_CTL_CLK_PDN_TO_VALID;
+       assign   cfg_extra_ctl_clk_srf_to_valid          = CFG_EXTRA_CTL_CLK_SRF_TO_VALID;
+       assign   cfg_extra_ctl_clk_srf_to_zq_cal         = CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL;
+       assign   cfg_extra_ctl_clk_arf_period            = CFG_EXTRA_CTL_CLK_ARF_PERIOD;
+       assign   cfg_extra_ctl_clk_pdn_period            = CFG_EXTRA_CTL_CLK_PDN_PERIOD;
+
+// cfg_* signals that are reconfigurable
+generate
+    if (CTL_CSR_ENABLED == 1 || CTL_ECC_ENABLED == 1) begin
+
+        wire    [CFG_PORT_WIDTH_TYPE                               - 1 : 0]    csr_cfg_type;
+        wire    [CFG_PORT_WIDTH_BURST_LENGTH                       - 1 : 0]    csr_cfg_burst_length;
+        wire    [CFG_PORT_WIDTH_ADDR_ORDER                         - 1 : 0]    csr_cfg_addr_order;
+        wire                                                                   csr_cfg_enable_ecc;
+        wire                                                                   csr_cfg_enable_auto_corr;
+        wire                                                                   csr_cfg_gen_sbe;
+        wire                                                                   csr_cfg_gen_dbe;
+        wire                                                                   csr_cfg_reorder_data;
+        wire                                                                   csr_cfg_regdimm_enable;
+        wire    [CFG_PORT_WIDTH_CAS_WR_LAT                         - 1 : 0]    csr_cfg_cas_wr_lat;
+        wire    [CFG_PORT_WIDTH_ADD_LAT                            - 1 : 0]    csr_cfg_add_lat;
+        wire    [CFG_PORT_WIDTH_TCL                                - 1 : 0]    csr_cfg_tcl;
+        wire    [CFG_PORT_WIDTH_TRRD                               - 1 : 0]    csr_cfg_trrd;
+        wire    [CFG_PORT_WIDTH_TFAW                               - 1 : 0]    csr_cfg_tfaw;
+        wire    [CFG_PORT_WIDTH_TRFC                               - 1 : 0]    csr_cfg_trfc;
+        wire    [CFG_PORT_WIDTH_TREFI                              - 1 : 0]    csr_cfg_trefi;
+        wire    [CFG_PORT_WIDTH_TRCD                               - 1 : 0]    csr_cfg_trcd;
+        wire    [CFG_PORT_WIDTH_TRP                                - 1 : 0]    csr_cfg_trp;
+        wire    [CFG_PORT_WIDTH_TWR                                - 1 : 0]    csr_cfg_twr;
+        wire    [CFG_PORT_WIDTH_TWTR                               - 1 : 0]    csr_cfg_twtr;
+        wire    [CFG_PORT_WIDTH_TRTP                               - 1 : 0]    csr_cfg_trtp;
+        wire    [CFG_PORT_WIDTH_TRAS                               - 1 : 0]    csr_cfg_tras;
+        wire    [CFG_PORT_WIDTH_TRC                                - 1 : 0]    csr_cfg_trc;
+        wire    [CFG_PORT_WIDTH_AUTO_PD_CYCLES                     - 1 : 0]    csr_cfg_auto_pd_cycles;
+        wire    [CFG_PORT_WIDTH_COL_ADDR_WIDTH                     - 1 : 0]    csr_cfg_col_addr_width;
+        wire    [CFG_PORT_WIDTH_ROW_ADDR_WIDTH                     - 1 : 0]    csr_cfg_row_addr_width;
+        wire    [CFG_PORT_WIDTH_BANK_ADDR_WIDTH                    - 1 : 0]    csr_cfg_bank_addr_width;
+        wire    [CFG_PORT_WIDTH_CS_ADDR_WIDTH                      - 1 : 0]    csr_cfg_cs_addr_width;
+        wire                                                                   csr_cfg_enable_intr;
+        wire                                                                   csr_cfg_mask_sbe_intr;
+        wire                                                                   csr_cfg_mask_dbe_intr;
+        wire                                                                   csr_cfg_clr_intr;
+        wire                                                                   csr_cfg_cal_req;
+
+        wire    [CFG_MEM_IF_CLK_PAIR_COUNT                         - 1 : 0]    csr_cfg_clock_off;
+        wire                                                                   csr_cfg_self_rfsh;
+        wire                                                                   csr_cfg_ganged_arf;
+        wire    [CFG_PORT_WIDTH_STARVE_LIMIT                       - 1 : 0]    csr_cfg_starve_limit;
+	wire	[8						   - 1 : 0]    int_csr_cfg_starve_limit;
+        wire    [CFG_PORT_WIDTH_INTERFACE_WIDTH                    - 1 : 0]    csr_cfg_interface_width;
+        wire    [CFG_PORT_WIDTH_DEVICE_WIDTH                       - 1 : 0]    csr_cfg_device_width;
+        wire                                                                   csr_cfg_mask_corr_dropped_intr;
+        wire    [2                                                 - 1 : 0]    csr_cfg_mem_bl;
+        wire                                                                   csr_cfg_user_ecc_en;
+
+        assign cfg_burst_length                         = csr_cfg_burst_length;
+        assign cfg_reorder_data                         = csr_cfg_reorder_data;
+	assign csr_cfg_starve_limit			= int_csr_cfg_starve_limit;
+        assign cfg_starve_limit                         = csr_cfg_starve_limit;
+        assign cfg_addr_order                           = csr_cfg_addr_order;
+        assign cfg_col_addr_width                       = csr_cfg_col_addr_width;
+        assign cfg_row_addr_width                       = csr_cfg_row_addr_width;
+        assign cfg_bank_addr_width                      = csr_cfg_bank_addr_width;
+        assign cfg_cs_addr_width                        = csr_cfg_cs_addr_width;
+        assign cfg_cas_wr_lat                           = csr_cfg_cas_wr_lat;
+        assign cfg_add_lat                              = csr_cfg_add_lat;
+        assign cfg_tcl                                  = csr_cfg_tcl;
+        assign cfg_trrd                                 = csr_cfg_trrd;
+        assign cfg_tfaw                                 = csr_cfg_tfaw;
+        assign cfg_trfc                                 = csr_cfg_trfc;
+        assign cfg_trefi                                = csr_cfg_trefi;
+        assign cfg_trcd                                 = csr_cfg_trcd;
+        assign cfg_trp                                  = csr_cfg_trp;
+        assign cfg_twr                                  = csr_cfg_twr;
+        assign cfg_twtr                                 = csr_cfg_twtr;
+        assign cfg_trtp                                 = csr_cfg_trtp;
+        assign cfg_tras                                 = csr_cfg_tras;
+        assign cfg_trc                                  = csr_cfg_trc;
+        assign cfg_enable_ecc                           = csr_cfg_enable_ecc;
+        assign cfg_enable_auto_corr                     = csr_cfg_enable_auto_corr;
+        assign cfg_gen_sbe                              = csr_cfg_gen_sbe;
+        assign cfg_gen_dbe                              = csr_cfg_gen_dbe;
+        assign cfg_enable_intr                          = csr_cfg_enable_intr;
+        assign cfg_mask_sbe_intr                        = csr_cfg_mask_sbe_intr;
+        assign cfg_mask_dbe_intr                        = csr_cfg_mask_dbe_intr;
+        assign cfg_mask_corr_dropped_intr               = csr_cfg_mask_corr_dropped_intr;
+        assign cfg_clr_intr                             = csr_cfg_clr_intr;
+        assign cfg_regdimm_enable                       = csr_cfg_regdimm_enable;
+        assign cfg_cal_req                              = csr_cfg_cal_req;
+        assign cfg_auto_pd_cycles                       = csr_cfg_auto_pd_cycles;
+
+        alt_mem_ddrx_csr # (
+            .CFG_AVALON_ADDR_WIDTH                              ( CSR_ADDR_WIDTH                                     ),
+            .CFG_AVALON_DATA_WIDTH                              ( CSR_DATA_WIDTH                                     ),
+            .CFG_BURST_LENGTH                                   ( CFG_BURST_LENGTH                                   ),
+            .CFG_REORDER_DATA                                   ( CFG_REORDER_DATA                                   ),
+            .CFG_STARVE_LIMIT                                   ( CFG_STARVE_LIMIT                                   ),
+            .CFG_ADDR_ORDER                                     ( CFG_ADDR_ORDER                                     ),
+            .CFG_COL_ADDR_WIDTH                                 ( CFG_COL_ADDR_WIDTH                                 ),
+            .CFG_ROW_ADDR_WIDTH                                 ( CFG_ROW_ADDR_WIDTH                                 ),
+            .CFG_BANK_ADDR_WIDTH                                ( CFG_BANK_ADDR_WIDTH                                ),
+            .CFG_CS_ADDR_WIDTH                                  ( CFG_CS_ADDR_WIDTH                                  ),
+            .CFG_CAS_WR_LAT                                     ( CFG_CAS_WR_LAT                                     ),
+            .CFG_ADD_LAT                                        ( CFG_ADD_LAT                                        ),
+            .CFG_TCL                                            ( CFG_TCL                                            ),
+            .CFG_TRRD                                           ( CFG_TRRD                                           ),
+            .CFG_TFAW                                           ( CFG_TFAW                                           ),
+            .CFG_TRFC                                           ( CFG_TRFC                                           ),
+            .CFG_TREFI                                          ( CFG_TREFI                                          ),
+            .CFG_TRCD                                           ( CFG_TRCD                                           ),
+            .CFG_TRP                                            ( CFG_TRP                                            ),
+            .CFG_TWR                                            ( CFG_TWR                                            ),
+            .CFG_TWTR                                           ( CFG_TWTR                                           ),
+            .CFG_TRTP                                           ( CFG_TRTP                                           ),
+            .CFG_TRAS                                           ( CFG_TRAS                                           ),
+            .CFG_TRC                                            ( CFG_TRC                                            ),
+            .CFG_AUTO_PD_CYCLES                                 ( CFG_AUTO_PD_CYCLES                                 ),
+            .CFG_ENABLE_ECC                                     ( CFG_ENABLE_ECC                                     ),
+	    .CTL_ECC_CSR_ENABLED				( CFG_ENABLE_ECC				     ),
+            .CTL_CSR_ENABLED                                    ( CTL_CSR_ENABLED                                    ),
+            .CFG_ENABLE_AUTO_CORR                               ( CFG_ENABLE_AUTO_CORR                               ),
+            .CFG_REGDIMM_ENABLE                                 ( CFG_REGDIMM_ENABLE                                 ),
+            .MEM_IF_DQS_WIDTH                                   ( CFG_MEM_IF_DQS_WIDTH                               )
+
+        ) register_control_inst (
+            .avalon_mm_read                                     ( csr_read_req                                       ),
+            .avalon_mm_write                                    ( csr_write_req                                      ),
+            .avalon_mm_addr                                     ( csr_addr                                           ),
+            .avalon_mm_wdata                                    ( csr_wdata                                          ),
+            .avalon_mm_rdata                                    ( csr_rdata                                          ),
+            .avalon_mm_be                                       ( csr_be                                             ),
+            .avalon_mm_waitrequest                              ( csr_waitrequest                                    ),
+            .avalon_mm_rdata_valid                              ( csr_rdata_valid                                    ),
+
+            .cfg_burst_length                                   ( csr_cfg_burst_length                               ),
+            .cfg_addr_order                                     ( csr_cfg_addr_order                                 ),
+            .cfg_enable_ecc                                     ( csr_cfg_enable_ecc                                 ),
+            .cfg_enable_auto_corr                               ( csr_cfg_enable_auto_corr                           ),
+            .cfg_gen_sbe                                        ( csr_cfg_gen_sbe                                    ),
+            .cfg_gen_dbe                                        ( csr_cfg_gen_dbe                                    ),
+            .cfg_reorder_data                                   ( csr_cfg_reorder_data                               ),
+            .cfg_regdimm_enable                                 ( csr_cfg_regdimm_enable                             ),
+            .cfg_cas_wr_lat                                     ( csr_cfg_cas_wr_lat                                 ),
+            .cfg_add_lat                                        ( csr_cfg_add_lat                                    ),
+            .cfg_tcl                                            ( csr_cfg_tcl                                        ),
+            .cfg_trrd                                           ( csr_cfg_trrd                                       ),
+            .cfg_tfaw                                           ( csr_cfg_tfaw                                       ),
+            .cfg_trfc                                           ( csr_cfg_trfc                                       ),
+            .cfg_trefi                                          ( csr_cfg_trefi                                      ),
+            .cfg_trcd                                           ( csr_cfg_trcd                                       ),
+            .cfg_trp                                            ( csr_cfg_trp                                        ),
+            .cfg_twr                                            ( csr_cfg_twr                                        ),
+            .cfg_twtr                                           ( csr_cfg_twtr                                       ),
+            .cfg_trtp                                           ( csr_cfg_trtp                                       ),
+            .cfg_tras                                           ( csr_cfg_tras                                       ),
+            .cfg_trc                                            ( csr_cfg_trc                                        ),
+            .cfg_auto_pd_cycles                                 ( csr_cfg_auto_pd_cycles                             ),
+            .cfg_col_addr_width                                 ( csr_cfg_col_addr_width                             ),
+            .cfg_row_addr_width                                 ( csr_cfg_row_addr_width                             ),
+            .cfg_bank_addr_width                                ( csr_cfg_bank_addr_width                            ),
+            .cfg_cs_addr_width                                  ( csr_cfg_cs_addr_width                              ),
+            .cfg_enable_intr                                    ( csr_cfg_enable_intr                                ),
+            .cfg_mask_sbe_intr                                  ( csr_cfg_mask_sbe_intr                              ),
+            .cfg_mask_dbe_intr                                  ( csr_cfg_mask_dbe_intr                              ),
+            .cfg_clr_intr                                       ( csr_cfg_clr_intr                                   ),
+            .cfg_clock_off                                      ( csr_cfg_clock_off                                  ),
+            .cfg_starve_limit                                   ( int_csr_cfg_starve_limit                           ),
+            .cfg_mask_corr_dropped_intr                         ( csr_cfg_mask_corr_dropped_intr                     ),
+            .cfg_cal_req                                        ( csr_cfg_cal_req                                    ),
+            
+            .local_power_down_ack                               ( local_powerdn_ack                                  ),
+            .local_self_rfsh_ack                                ( local_self_rfsh_ack                                ),
+            
+            .sts_cal_success                                    ( afi_cal_success                                    ),
+            .sts_cal_fail                                       ( afi_cal_fail                                       ),
+            .sts_sbe_error                                      ( sts_sbe_error                                      ),
+            .sts_dbe_error                                      ( sts_dbe_error                                      ),
+            .sts_sbe_count                                      ( sts_sbe_count                                      ),
+            .sts_dbe_count                                      ( sts_dbe_count                                      ),
+            .sts_err_addr                                       ( {{(32-CFG_LOCAL_ADDR_WIDTH){1'b0}}  ,sts_err_addr} ),
+            .sts_corr_dropped                                   ( sts_corr_dropped                                   ),
+            .sts_corr_dropped_count                             ( sts_corr_dropped_count                             ),
+            .sts_corr_dropped_addr                              ( {{(32-CFG_LOCAL_ADDR_WIDTH){1'b0}} ,sts_corr_dropped_addr}),
+
+            .ctl_clk                                            ( clk                                                ),
+            .ctl_rst_n                                          ( reset_n                                            )
+        );
+    end
+    else begin
+
+        assign csr_rdata = 0;
+        assign csr_rdata_valid = 0;
+        assign csr_waitrequest = 0;
+
+        assign cfg_burst_length                         = CFG_BURST_LENGTH;
+        assign cfg_reorder_data                         = CFG_REORDER_DATA;
+        assign cfg_starve_limit                         = CFG_STARVE_LIMIT;
+        assign cfg_addr_order                           = CFG_ADDR_ORDER;
+        assign cfg_col_addr_width                       = CFG_COL_ADDR_WIDTH;
+        assign cfg_row_addr_width                       = CFG_ROW_ADDR_WIDTH;
+        assign cfg_bank_addr_width                      = CFG_BANK_ADDR_WIDTH;
+        assign cfg_cs_addr_width                        = CFG_CS_ADDR_WIDTH;
+        assign cfg_cas_wr_lat                           = CFG_CAS_WR_LAT;
+        assign cfg_add_lat                              = CFG_ADD_LAT;
+        assign cfg_tcl                                  = CFG_TCL;
+        assign cfg_trrd                                 = CFG_TRRD;
+        assign cfg_tfaw                                 = CFG_TFAW;
+        assign cfg_trfc                                 = CFG_TRFC;
+        assign cfg_trefi                                = CFG_TREFI;
+        assign cfg_trcd                                 = CFG_TRCD;
+        assign cfg_trp                                  = CFG_TRP;
+        assign cfg_twr                                  = CFG_TWR;
+        assign cfg_twtr                                 = CFG_TWTR;
+        assign cfg_trtp                                 = CFG_TRTP;
+        assign cfg_tras                                 = CFG_TRAS;
+        assign cfg_trc                                  = CFG_TRC;
+        assign cfg_auto_pd_cycles                       = CFG_AUTO_PD_CYCLES;
+        assign cfg_enable_ecc                           = CFG_ENABLE_ECC;
+        assign cfg_enable_auto_corr                     = CFG_ENABLE_AUTO_CORR;
+        assign cfg_gen_sbe                              = CFG_GEN_SBE;
+        assign cfg_gen_dbe                              = CFG_GEN_DBE;
+        assign cfg_enable_intr                          = CFG_ENABLE_INTR;
+        assign cfg_mask_sbe_intr                        = CFG_MASK_SBE_INTR;
+        assign cfg_mask_dbe_intr                        = CFG_MASK_DBE_INTR;
+        assign cfg_mask_corr_dropped_intr               = CFG_MASK_CORR_DROPPED_INTR;
+        assign cfg_clr_intr                             = CFG_CLR_INTR;
+        assign cfg_regdimm_enable                       = CFG_REGDIMM_ENABLE;
+        assign cfg_cal_req                              = CFG_CAL_REQ;
+
+    end
+endgenerate
+
+
+// Next Gen Controller
+alt_mem_ddrx_controller # (
+    .CFG_LOCAL_SIZE_WIDTH                               ( CFG_LOCAL_SIZE_WIDTH                               ),
+    .CFG_LOCAL_ADDR_WIDTH                               ( CFG_LOCAL_ADDR_WIDTH                               ),
+    .CFG_LOCAL_DATA_WIDTH                               ( CFG_LOCAL_DATA_WIDTH                               ),
+    .CFG_LOCAL_ID_WIDTH                                 ( CFG_LOCAL_ID_WIDTH                                 ),
+    .CFG_LOCAL_IF_TYPE                                  ( CFG_LOCAL_IF_TYPE                                  ),
+    .CFG_MEM_IF_ADDR_WIDTH                              ( CFG_MEM_IF_ADDR_WIDTH                              ),
+    .CFG_MEM_IF_CLK_PAIR_COUNT                          ( CFG_MEM_IF_CLK_PAIR_COUNT                          ),
+    .CFG_DWIDTH_RATIO                                   ( CFG_DWIDTH_RATIO                                   ),
+    .CFG_ODT_ENABLED                                    ( CFG_ODT_ENABLED                                    ),
+    .CFG_LPDDR2_ENABLED                                 ( CFG_LPDDR2_ENABLED                                 ),
+    .CFG_CTL_TBP_NUM                                    ( CFG_CTL_TBP_NUM                                    ),
+    .CFG_DATA_REORDERING_TYPE                           ( CFG_DATA_REORDERING_TYPE                           ),
+    .CFG_WRBUFFER_ADDR_WIDTH                            ( CFG_WRBUFFER_ADDR_WIDTH                            ),
+    .CFG_RDBUFFER_ADDR_WIDTH                            ( CFG_RDBUFFER_ADDR_WIDTH                            ),
+    .CFG_MAX_PENDING_RD_CMD                             ( CFG_MAX_PENDING_RD_CMD                             ),
+    .CFG_MAX_PENDING_WR_CMD                             ( CFG_MAX_PENDING_WR_CMD                             ),
+    .CFG_ECC_MULTIPLES_16_24_40_72                      ( CFG_ECC_MULTIPLES_16_24_40_72                      ),
+    .CFG_MEM_IF_CS_WIDTH                                ( CFG_MEM_IF_CS_WIDTH                                ),
+    .CFG_MEM_IF_CHIP                                    ( CFG_MEM_IF_CHIP                                    ),
+    .CFG_MEM_IF_BA_WIDTH                                ( CFG_MEM_IF_BA_WIDTH                                ),
+    .CFG_MEM_IF_ROW_WIDTH                               ( CFG_MEM_IF_ROW_WIDTH                               ),
+    .CFG_MEM_IF_COL_WIDTH                               ( CFG_MEM_IF_COL_WIDTH                               ),
+    .CFG_MEM_IF_CKE_WIDTH                               ( CFG_MEM_IF_CKE_WIDTH                               ),
+    .CFG_MEM_IF_ODT_WIDTH                               ( CFG_MEM_IF_ODT_WIDTH                               ),
+    .CFG_MEM_IF_DQS_WIDTH                               ( CFG_MEM_IF_DQS_WIDTH                               ),
+    .CFG_MEM_IF_DQ_WIDTH                                ( CFG_MEM_IF_DQ_WIDTH                                ),
+    .CFG_MEM_IF_DM_WIDTH                                ( CFG_MEM_IF_DM_WIDTH                                ),
+    .CFG_PORT_WIDTH_TYPE                                ( CFG_PORT_WIDTH_TYPE                                ),
+    .CFG_PORT_WIDTH_INTERFACE_WIDTH                     ( CFG_PORT_WIDTH_INTERFACE_WIDTH                     ),
+    .CFG_PORT_WIDTH_BURST_LENGTH                        ( CFG_PORT_WIDTH_BURST_LENGTH                        ),
+    .CFG_PORT_WIDTH_DEVICE_WIDTH                        ( CFG_PORT_WIDTH_DEVICE_WIDTH                        ),
+    .CFG_PORT_WIDTH_REORDER_DATA                        ( CFG_PORT_WIDTH_REORDER_DATA                        ),
+    .CFG_PORT_WIDTH_STARVE_LIMIT                        ( CFG_PORT_WIDTH_STARVE_LIMIT                        ),
+    .CFG_PORT_WIDTH_OUTPUT_REGD                         ( CFG_PORT_WIDTH_OUTPUT_REGD                         ),
+    .CFG_PORT_WIDTH_ADDR_ORDER                          ( CFG_PORT_WIDTH_ADDR_ORDER                          ),
+    .CFG_PORT_WIDTH_COL_ADDR_WIDTH                      ( CFG_PORT_WIDTH_COL_ADDR_WIDTH                      ),
+    .CFG_PORT_WIDTH_ROW_ADDR_WIDTH                      ( CFG_PORT_WIDTH_ROW_ADDR_WIDTH                      ),
+    .CFG_PORT_WIDTH_BANK_ADDR_WIDTH                     ( CFG_PORT_WIDTH_BANK_ADDR_WIDTH                     ),
+    .CFG_PORT_WIDTH_CS_ADDR_WIDTH                       ( CFG_PORT_WIDTH_CS_ADDR_WIDTH                       ),
+    .CFG_PORT_WIDTH_CAS_WR_LAT                          ( CFG_PORT_WIDTH_CAS_WR_LAT                          ),
+    .CFG_PORT_WIDTH_ADD_LAT                             ( CFG_PORT_WIDTH_ADD_LAT                             ),
+    .CFG_PORT_WIDTH_TCL                                 ( CFG_PORT_WIDTH_TCL                                 ),
+    .CFG_PORT_WIDTH_TRRD                                ( CFG_PORT_WIDTH_TRRD                                ),
+    .CFG_PORT_WIDTH_TFAW                                ( CFG_PORT_WIDTH_TFAW                                ),
+    .CFG_PORT_WIDTH_TRFC                                ( CFG_PORT_WIDTH_TRFC                                ),
+    .CFG_PORT_WIDTH_TREFI                               ( CFG_PORT_WIDTH_TREFI                               ),
+    .CFG_PORT_WIDTH_TRCD                                ( CFG_PORT_WIDTH_TRCD                                ),
+    .CFG_PORT_WIDTH_TRP                                 ( CFG_PORT_WIDTH_TRP                                 ),
+    .CFG_PORT_WIDTH_TWR                                 ( CFG_PORT_WIDTH_TWR                                 ),
+    .CFG_PORT_WIDTH_TWTR                                ( CFG_PORT_WIDTH_TWTR                                ),
+    .CFG_PORT_WIDTH_TRTP                                ( CFG_PORT_WIDTH_TRTP                                ),
+    .CFG_PORT_WIDTH_TRAS                                ( CFG_PORT_WIDTH_TRAS                                ),
+    .CFG_PORT_WIDTH_TRC                                 ( CFG_PORT_WIDTH_TRC                                 ),
+    .CFG_PORT_WIDTH_TCCD                                ( CFG_PORT_WIDTH_TCCD                                ),
+    .CFG_PORT_WIDTH_TMRD                                ( CFG_PORT_WIDTH_TMRD                                ),
+    .CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES               ( CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES               ),
+    .CFG_PORT_WIDTH_PDN_EXIT_CYCLES                     ( CFG_PORT_WIDTH_PDN_EXIT_CYCLES                     ),
+    .CFG_PORT_WIDTH_AUTO_PD_CYCLES                      ( CFG_PORT_WIDTH_AUTO_PD_CYCLES                      ),
+    .CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES            ( CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES            ),
+    .CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                ( CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR           ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR           ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH            ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH            ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT            ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT            ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD              ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD              ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP    ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP    ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR              ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR              ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC           ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC           ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP    ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP    ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH             ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH             ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID        ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID        ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR              ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR              ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP    ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP    ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD              ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD              ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC           ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC           ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP    ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP    ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH             ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH             ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID        ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID        ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID          ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID          ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID      ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID      ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK  ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK  ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT       ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT       ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID          ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID          ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID          ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID          ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID          ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID          ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL         ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL         ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD            ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD            ),
+    .CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD            ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD            ),
+    .CFG_PORT_WIDTH_ENABLE_ECC                          ( CFG_PORT_WIDTH_ENABLE_ECC                          ),
+    .CFG_PORT_WIDTH_ENABLE_AUTO_CORR                    ( CFG_PORT_WIDTH_ENABLE_AUTO_CORR                    ),
+    .CFG_PORT_WIDTH_GEN_SBE                             ( CFG_PORT_WIDTH_GEN_SBE                             ),
+    .CFG_PORT_WIDTH_GEN_DBE                             ( CFG_PORT_WIDTH_GEN_DBE                             ),
+    .CFG_PORT_WIDTH_ENABLE_INTR                         ( CFG_PORT_WIDTH_ENABLE_INTR                         ),
+    .CFG_PORT_WIDTH_MASK_SBE_INTR                       ( CFG_PORT_WIDTH_MASK_SBE_INTR                       ),
+    .CFG_PORT_WIDTH_MASK_DBE_INTR                       ( CFG_PORT_WIDTH_MASK_DBE_INTR                       ),
+    .CFG_PORT_WIDTH_CLR_INTR                            ( CFG_PORT_WIDTH_CLR_INTR                            ),
+    .CFG_PORT_WIDTH_USER_RFSH                           ( CFG_PORT_WIDTH_USER_RFSH                           ),
+    .CFG_PORT_WIDTH_SELF_RFSH                           ( CFG_PORT_WIDTH_SELF_RFSH                           ),
+    .CFG_PORT_WIDTH_REGDIMM_ENABLE                      ( CFG_PORT_WIDTH_REGDIMM_ENABLE                      ),
+    .CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT              ( CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT              ),
+    .CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE              ( CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE              ),
+    .CFG_ENABLE_WDATA_PATH_LATENCY                      ( CFG_ENABLE_WDATA_PATH_LATENCY                      ),
+    .CFG_PORT_WIDTH_WRITE_ODT_CHIP                      ( CFG_PORT_WIDTH_WRITE_ODT_CHIP                      ),
+    .CFG_PORT_WIDTH_READ_ODT_CHIP                       ( CFG_PORT_WIDTH_READ_ODT_CHIP                       ),
+    .CFG_WLAT_BUS_WIDTH                                 ( CFG_WLAT_BUS_WIDTH                                 ),
+    .CFG_RRANK_BUS_WIDTH                                ( CFG_RRANK_BUS_WIDTH                                ),
+    .CFG_WRANK_BUS_WIDTH                                ( CFG_WRANK_BUS_WIDTH                                ),
+    .CFG_USE_SHADOW_REGS                                ( CFG_USE_SHADOW_REGS                                ),
+    .CFG_RDATA_RETURN_MODE                              ( CFG_RDATA_RETURN_MODE                              ),
+	.CFG_ECC_DECODER_REG								( CFG_ECC_DECODER_REG								 ),
+	.CFG_ERRCMD_FIFO_REG								( CFG_ERRCMD_FIFO_REG								 ),					
+    .CFG_ENABLE_BURST_MERGE                             ( CFG_ENABLE_BURST_MERGE                             )
+
+) controller_inst (
+    .ctl_clk                                            ( clk                                                ),
+    .ctl_reset_n                                        ( reset_n                                            ),
+
+    .itf_cmd_ready                                      ( itf_cmd_ready                                      ),
+    .itf_cmd_valid                                      ( itf_cmd_valid                                      ),
+    .itf_cmd                                            ( itf_cmd                                            ),
+    .itf_cmd_address                                    ( itf_cmd_address                                    ),
+    .itf_cmd_burstlen                                   ( itf_cmd_burstlen                                   ),
+    .itf_cmd_id                                         ( itf_cmd_id                                         ),
+    .itf_cmd_priority                                   ( itf_cmd_priority                                   ),
+    .itf_cmd_autopercharge                              ( itf_cmd_autopercharge                              ),
+    .itf_cmd_multicast                                  ( itf_cmd_multicast                                  ),
+
+    .itf_wr_data_ready                                  ( itf_wr_data_ready                                  ),
+    .itf_wr_data_valid                                  ( itf_wr_data_valid                                  ),
+    .itf_wr_data                                        ( itf_wr_data                                        ),
+    .itf_wr_data_byte_en                                ( itf_wr_data_byte_en                                ),
+    .itf_wr_data_begin                                  ( itf_wr_data_begin                                  ),
+    .itf_wr_data_last                                   ( itf_wr_data_last                                   ),
+    .itf_wr_data_id                                     ( itf_wr_data_id                                     ),
+
+    .itf_rd_data_ready                                  ( itf_rd_data_ready                                  ),
+    .itf_rd_data_valid                                  ( itf_rd_data_valid                                  ),
+    .itf_rd_data                                        ( itf_rd_data                                        ),
+    .itf_rd_data_error                                  ( itf_rd_data_error                                  ),
+    .itf_rd_data_begin                                  ( itf_rd_data_begin                                  ),
+    .itf_rd_data_last                                   ( itf_rd_data_last                                   ),
+    .itf_rd_data_id                                     ( itf_rd_data_id                                     ),
+
+    .local_refresh_req                                  ( local_refresh_req                                  ),
+    .local_refresh_chip                                 ( local_refresh_chip                                 ),
+    .local_deep_powerdn_req                             ( local_deep_powerdn_req                             ),
+	.local_deep_powerdn_chip                            ( local_deep_powerdn_chip                            ),
+    .local_self_rfsh_req                                ( local_self_rfsh_req                                ),
+    .local_self_rfsh_chip                               ( local_self_rfsh_chip                               ),
+    .local_zqcal_req                                    ( local_zqcal_req                                    ),
+    .local_zqcal_chip                                   ( local_zqcal_chip                                   ),
+    .local_refresh_ack                                  ( local_refresh_ack                                  ),
+    .local_deep_powerdn_ack                             ( local_deep_powerdn_ack	                         ),
+    .local_power_down_ack                               ( local_powerdn_ack                                  ),
+    .local_self_rfsh_ack                                ( local_self_rfsh_ack                                ),
+    .local_init_done                                    ( local_init_done                                    ),
+
+    .afi_cke                                            ( afi_cke                                            ),
+    .afi_cs_n                                           ( afi_cs_n                                           ),
+    .afi_ras_n                                          ( afi_ras_n                                          ),
+    .afi_cas_n                                          ( afi_cas_n                                          ),
+    .afi_we_n                                           ( afi_we_n                                           ),
+    .afi_ba                                             ( afi_ba                                             ),
+    .afi_addr                                           ( afi_addr                                           ),
+    .afi_odt                                            ( afi_odt                                            ),
+    .afi_rst_n                                          ( afi_rst_n                                          ),
+
+    .afi_dqs_burst                                      ( afi_dqs_burst                                      ),
+    .afi_wdata_valid                                    ( afi_wdata_valid                                    ),
+    .afi_wdata                                          ( afi_wdata                                          ),
+    .afi_dm                                             ( afi_dm                                             ),
+    .afi_wlat                                           ( afi_wlat                                           ),
+    .afi_rdata_en                                       ( afi_rdata_en                                       ),
+    .afi_rdata_en_full                                  ( afi_rdata_en_full                                  ),
+    .afi_rrank                                          ( afi_rrank                                          ),
+    .afi_wrank                                          ( afi_wrank                                          ),
+    .afi_rdata                                          ( afi_rdata                                          ),
+    .afi_rdata_valid                                    ( afi_rdata_valid                                    ),
+    .ctl_cal_success                                    ( afi_cal_success                                    ),
+    .ctl_cal_fail                                       ( afi_cal_fail                                       ),
+    .ctl_cal_req                                        ( afi_cal_req                                        ),
+    .ctl_init_req                                       ( afi_init_req                                       ),
+    .ctl_mem_clk_disable                                ( afi_mem_clk_disable                                ),
+    .ctl_cal_byte_lane_sel_n                            ( afi_cal_byte_lane_sel_n                            ),
+
+    .cfg_type                                           ( cfg_type                                           ),
+    .cfg_interface_width                                ( cfg_interface_width                                ),
+    .cfg_burst_length                                   ( cfg_burst_length                                   ),
+    .cfg_device_width                                   ( cfg_device_width                                   ),
+    .cfg_reorder_data                                   ( cfg_reorder_data                                   ),
+    .cfg_starve_limit                                   ( cfg_starve_limit                                   ),
+    .cfg_output_regd                                    ( cfg_output_regd                                    ),
+
+    .cfg_addr_order                                     ( cfg_addr_order                                     ),
+    .cfg_col_addr_width                                 ( cfg_col_addr_width                                 ),
+    .cfg_row_addr_width                                 ( cfg_row_addr_width                                 ),
+    .cfg_bank_addr_width                                ( cfg_bank_addr_width                                ),
+    .cfg_cs_addr_width                                  ( cfg_cs_addr_width                                  ),
+    .cfg_cas_wr_lat                                     ( cfg_cas_wr_lat                                     ),
+    .cfg_add_lat                                        ( cfg_add_lat                                        ),
+    .cfg_tcl                                            ( cfg_tcl                                            ),
+    .cfg_trrd                                           ( cfg_trrd                                           ),
+    .cfg_tfaw                                           ( cfg_tfaw                                           ),
+    .cfg_trfc                                           ( cfg_trfc                                           ),
+    .cfg_trefi                                          ( cfg_trefi                                          ),
+    .cfg_trcd                                           ( cfg_trcd                                           ),
+    .cfg_trp                                            ( cfg_trp                                            ),
+    .cfg_twr                                            ( cfg_twr                                            ),
+    .cfg_twtr                                           ( cfg_twtr                                           ),
+    .cfg_trtp                                           ( cfg_trtp                                           ),
+    .cfg_tras                                           ( cfg_tras                                           ),
+    .cfg_trc                                            ( cfg_trc                                            ),
+    .cfg_tccd                                           ( cfg_tccd                                           ),
+    .cfg_auto_pd_cycles                                 ( cfg_auto_pd_cycles                                 ),
+    .cfg_self_rfsh_exit_cycles                          ( cfg_self_rfsh_exit_cycles                          ),
+    .cfg_pdn_exit_cycles                                ( cfg_pdn_exit_cycles                                ),
+    .cfg_power_saving_exit_cycles                       ( cfg_power_saving_exit_cycles                       ),
+    .cfg_mem_clk_entry_cycles                           ( cfg_mem_clk_entry_cycles                           ),
+    .cfg_tmrd                                           ( cfg_tmrd                                           ),
+    .cfg_enable_ecc                                     ( cfg_enable_ecc                                     ),
+    .cfg_enable_auto_corr                               ( cfg_enable_auto_corr                               ),
+    .cfg_enable_no_dm                                   ( cfg_enable_no_dm                                   ),
+    .cfg_enable_ecc_code_overwrites                     ( cfg_enable_ecc_code_overwrites                     ),
+    .cfg_cal_req                                        ( cfg_cal_req                                        ),
+    .cfg_gen_sbe                                        ( cfg_gen_sbe                                        ),
+    .cfg_gen_dbe                                        ( cfg_gen_dbe                                        ),
+    .cfg_enable_intr                                    ( cfg_enable_intr                                    ),
+    .cfg_mask_sbe_intr                                  ( cfg_mask_sbe_intr                                  ),
+    .cfg_mask_dbe_intr                                  ( cfg_mask_dbe_intr                                  ),
+    .cfg_mask_corr_dropped_intr                         ( cfg_mask_corr_dropped_intr                         ),
+
+    .cfg_clr_intr                                       ( cfg_clr_intr                                       ),
+    .cfg_user_rfsh                                      ( cfg_user_rfsh                                      ),
+    .cfg_regdimm_enable                                 ( cfg_regdimm_enable                                 ),
+    .cfg_enable_burst_interrupt                         ( cfg_enable_burst_interrupt                         ),
+    .cfg_enable_burst_terminate                         ( cfg_enable_burst_terminate                         ),
+    .cfg_write_odt_chip                                 ( cfg_write_odt_chip                                 ),
+    .cfg_read_odt_chip                                  ( cfg_read_odt_chip                                  ),
+    .cfg_extra_ctl_clk_act_to_rdwr                      ( cfg_extra_ctl_clk_act_to_rdwr                      ),
+    .cfg_extra_ctl_clk_act_to_pch                       ( cfg_extra_ctl_clk_act_to_pch                       ),
+    .cfg_extra_ctl_clk_act_to_act                       ( cfg_extra_ctl_clk_act_to_act                       ),
+    .cfg_extra_ctl_clk_rd_to_rd                         ( cfg_extra_ctl_clk_rd_to_rd                         ),
+    .cfg_extra_ctl_clk_rd_to_rd_diff_chip               ( cfg_extra_ctl_clk_rd_to_rd_diff_chip               ),
+    .cfg_extra_ctl_clk_rd_to_wr                         ( cfg_extra_ctl_clk_rd_to_wr                         ),
+    .cfg_extra_ctl_clk_rd_to_wr_bc                      ( cfg_extra_ctl_clk_rd_to_wr_bc                      ),
+    .cfg_extra_ctl_clk_rd_to_wr_diff_chip               ( cfg_extra_ctl_clk_rd_to_wr_diff_chip               ),
+    .cfg_extra_ctl_clk_rd_to_pch                        ( cfg_extra_ctl_clk_rd_to_pch                        ),
+    .cfg_extra_ctl_clk_rd_ap_to_valid                   ( cfg_extra_ctl_clk_rd_ap_to_valid                   ),
+    .cfg_extra_ctl_clk_wr_to_wr                         ( cfg_extra_ctl_clk_wr_to_wr                         ),
+    .cfg_extra_ctl_clk_wr_to_wr_diff_chip               ( cfg_extra_ctl_clk_wr_to_wr_diff_chip               ),
+    .cfg_extra_ctl_clk_wr_to_rd                         ( cfg_extra_ctl_clk_wr_to_rd                         ),
+    .cfg_extra_ctl_clk_wr_to_rd_bc                      ( cfg_extra_ctl_clk_wr_to_rd_bc                      ),
+    .cfg_extra_ctl_clk_wr_to_rd_diff_chip               ( cfg_extra_ctl_clk_wr_to_rd_diff_chip               ),
+    .cfg_extra_ctl_clk_wr_to_pch                        ( cfg_extra_ctl_clk_wr_to_pch                        ),
+    .cfg_extra_ctl_clk_wr_ap_to_valid                   ( cfg_extra_ctl_clk_wr_ap_to_valid                   ),
+    .cfg_extra_ctl_clk_pch_to_valid                     ( cfg_extra_ctl_clk_pch_to_valid                     ),
+    .cfg_extra_ctl_clk_pch_all_to_valid                 ( cfg_extra_ctl_clk_pch_all_to_valid                 ),
+    .cfg_extra_ctl_clk_act_to_act_diff_bank             ( cfg_extra_ctl_clk_act_to_act_diff_bank             ),
+    .cfg_extra_ctl_clk_four_act_to_act                  ( cfg_extra_ctl_clk_four_act_to_act                  ),
+    .cfg_extra_ctl_clk_arf_to_valid                     ( cfg_extra_ctl_clk_arf_to_valid                     ),
+    .cfg_extra_ctl_clk_pdn_to_valid                     ( cfg_extra_ctl_clk_pdn_to_valid                     ),
+    .cfg_extra_ctl_clk_srf_to_valid                     ( cfg_extra_ctl_clk_srf_to_valid                     ),
+    .cfg_extra_ctl_clk_srf_to_zq_cal                    ( cfg_extra_ctl_clk_srf_to_zq_cal                    ),
+    .cfg_extra_ctl_clk_arf_period                       ( cfg_extra_ctl_clk_arf_period                       ),
+    .cfg_extra_ctl_clk_pdn_period                       ( cfg_extra_ctl_clk_pdn_period                       ),
+    .cfg_enable_dqs_tracking                            ( cfg_enable_dqs_tracking                            ),
+    .ecc_interrupt                                      ( ecc_interrupt                                      ),
+    .sts_sbe_error                                      ( sts_sbe_error                                      ),
+    .sts_dbe_error                                      ( sts_dbe_error                                      ),
+    .sts_sbe_count                                      ( sts_sbe_count                                      ),
+    .sts_dbe_count                                      ( sts_dbe_count                                      ),
+    .sts_err_addr                                       ( sts_err_addr                                       ),
+    .sts_corr_dropped                                   ( sts_corr_dropped                                   ),
+    .sts_corr_dropped_count                             ( sts_corr_dropped_count                             ),
+    .sts_corr_dropped_addr                              ( sts_corr_dropped_addr                              ),
+
+    .afi_ctl_refresh_done                               ( afi_ctl_refresh_done                               ),
+    .afi_seq_busy                                       ( afi_seq_busy                                       ),
+    .afi_ctl_long_idle                                  ( afi_ctl_long_idle                                  ),
+    .itf_rd_data_id_early                               (                                                    ),
+    .itf_rd_data_id_early_valid                         (                                                    ),
+    .sts_cal_fail                                       (                                                    ),
+    .sts_cal_success                                    (                                                    ),
+
+    .tbp_empty                                          ( tbp_empty                                          ),
+    .cmd_gen_busy                                       ( cmd_gen_busy                                       ),
+    .sideband_in_refresh                                ( sideband_in_refresh                                )
+);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
new file mode 100644
index 0000000..77e1b39
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
@@ -0,0 +1,1433 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+//altera message_off 10230
+
+module alt_mem_ddrx_csr #
+    ( parameter
+        DWIDTH_RATIO                = 2,
+        CTL_CSR_ENABLED             = 1,
+        CTL_ECC_CSR_ENABLED         = 1,
+        CTL_CSR_READ_ONLY           = 0,
+        CTL_ECC_CSR_READ_ONLY       = 0,
+        CFG_AVALON_ADDR_WIDTH              = 8,
+        CFG_AVALON_DATA_WIDTH              = 32,
+        
+        MEM_IF_CLK_PAIR_COUNT       = 1,
+        MEM_IF_DQS_WIDTH            = 72,
+        
+        CFG_CS_ADDR_WIDTH            = 1,        // same as MEM_IF_CHIP
+        CFG_ROW_ADDR_WIDTH            = 13,      // max supported row bits
+        CFG_COL_ADDR_WIDTH            = 10,      // max supported column bits
+        CFG_BANK_ADDR_WIDTH             = 3,       // max supported bank bits
+        
+        CFG_ENABLE_ECC             = 1,
+        CFG_ENABLE_AUTO_CORR         = 1,
+        CFG_REGDIMM_ENABLE         = 0,
+        
+        // timing parameter width
+	//WARNING: When updating width, need to ensure the address mapping is still valid.
+        CAS_WR_LAT_BUS_WIDTH        = 4,       // max will be 8 in DDR3
+        ADD_LAT_BUS_WIDTH           = 4,       // max will be 6 in DDR2
+        TCL_BUS_WIDTH               = 4,       // max will be 11 in DDR3
+        BL_BUS_WIDTH                = 5,       // 
+        TRRD_BUS_WIDTH              = 4,       // 2 - 8
+        TFAW_BUS_WIDTH              = 6,       // 6 - 32
+	TRFC_BUS_WIDTH              = 9,       // 12 - 140?	//case:234203
+        TREFI_BUS_WIDTH             = 14,      // 780 - 6240	//case:234203
+        TRCD_BUS_WIDTH              = 4,       // 2 - 11
+        TRP_BUS_WIDTH               = 4,       // 2 - 11
+	TWR_BUS_WIDTH               = 5,       // 2 - 12	//case:234203
+        TWTR_BUS_WIDTH              = 4,       // 1 - 10
+        TRTP_BUS_WIDTH              = 4,       // 2 - 8
+	TRAS_BUS_WIDTH              = 6,       // 4 - 29	//case:234203
+        TRC_BUS_WIDTH               = 6,       // 8 - 40
+        AUTO_PD_BUS_WIDTH           = 16,      // same as CSR interface
+        STARVE_LIMIT_BUS_WIDTH      = 8,
+        
+        // timing parameter
+        CFG_CAS_WR_LAT              = 0,        // these timing parameter must be set properly for controller to work
+        CFG_ADD_LAT                 = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TCL                     = 0,        // these timing parameter must be set properly for controller to work
+        CFG_BURST_LENGTH                      = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRRD                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TFAW                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRFC                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TREFI                   = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRCD                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRP                     = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TWR                     = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TWTR                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRTP                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRAS                    = 0,        // these timing parameter must be set properly for controller to work
+        CFG_TRC                     = 0,        // these timing parameter must be set properly for controller to work
+        CFG_AUTO_PD_CYCLES          = 0,        // these timing parameter must be set properly for controller to work
+        
+        // parameters used by input interface
+        CFG_ADDR_ORDER                  = 1,        // normally we will use '1' for chip, bank, row, column arrangement
+        CFG_REORDER_DATA         = 0,
+        CFG_STARVE_LIMIT                = 0,
+        MEM_IF_CSR_COL_WIDTH        = 5,
+        MEM_IF_CSR_ROW_WIDTH        = 5,
+        MEM_IF_CSR_BANK_WIDTH       = 3,
+        MEM_IF_CSR_CS_WIDTH         = 3
+    )
+    (
+        ctl_clk,
+        ctl_rst_n,
+        
+        // csr interface (Avalon)
+        avalon_mm_addr,
+        avalon_mm_be,
+        avalon_mm_write,
+        avalon_mm_wdata,
+        avalon_mm_read,
+        avalon_mm_rdata,
+        avalon_mm_rdata_valid,
+        avalon_mm_waitrequest,
+        
+        // input from PHY
+        sts_cal_success,
+        sts_cal_fail,
+        
+        // input from state machine
+        local_power_down_ack,
+        local_self_rfsh_ack,
+        
+        // input from ecc
+        sts_sbe_error,
+        sts_dbe_error,
+        sts_corr_dropped,
+        sts_sbe_count,
+        sts_dbe_count,
+        sts_corr_dropped_count,
+        sts_err_addr,
+        sts_corr_dropped_addr,
+        
+        // output to PHY
+        cfg_cal_req,
+        cfg_clock_off,
+        ctl_cal_byte_lane_sel_n,
+        
+        // output to timer
+        cfg_cas_wr_lat,
+        cfg_add_lat,
+        cfg_tcl,
+        cfg_burst_length,
+        cfg_trrd,
+        cfg_tfaw,
+        cfg_trfc,
+        cfg_trefi,
+        cfg_trcd,
+        cfg_trp,
+        cfg_twr,
+        cfg_twtr,
+        cfg_trtp,
+        cfg_tras,
+        cfg_trc,
+        cfg_auto_pd_cycles,
+        
+        // output to input interface
+        cfg_addr_order,
+        cfg_col_addr_width,
+        cfg_row_addr_width,
+        cfg_bank_addr_width,
+        cfg_cs_addr_width,
+        
+        // output to ecc
+        cfg_enable_ecc,
+        cfg_enable_auto_corr,
+        cfg_gen_sbe,
+        cfg_gen_dbe,
+        cfg_enable_intr,
+        cfg_mask_sbe_intr,
+        cfg_mask_dbe_intr,
+        cfg_mask_corr_dropped_intr,
+        cfg_clr_intr,
+
+        // output to others
+        cfg_regdimm_enable,
+        cfg_reorder_data,
+        cfg_starve_limit
+    );
+
+localparam integer CFG_MEM_IF_CS_WIDTH  = (2**CFG_CS_ADDR_WIDTH);
+
+input ctl_clk;
+input ctl_rst_n;
+
+input avalon_mm_write;
+input avalon_mm_read;
+input [CFG_AVALON_ADDR_WIDTH - 1       : 0] avalon_mm_addr;
+input [CFG_AVALON_DATA_WIDTH - 1       : 0] avalon_mm_wdata;
+input [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] avalon_mm_be;
+
+output avalon_mm_waitrequest;
+output avalon_mm_rdata_valid;
+output [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
+
+// input from AFI
+input sts_cal_success;
+input sts_cal_fail;
+
+// input from state machine
+input local_power_down_ack;
+input local_self_rfsh_ack;
+
+// input from ecc
+input           sts_sbe_error;
+input           sts_dbe_error;
+input           sts_corr_dropped;
+input  [7  : 0] sts_sbe_count;
+input  [7  : 0] sts_dbe_count;
+input  [7  : 0] sts_corr_dropped_count;
+input  [31 : 0] sts_err_addr;
+input  [31 : 0] sts_corr_dropped_addr;
+
+// output to PHY
+output                                              cfg_cal_req;
+output [MEM_IF_CLK_PAIR_COUNT              - 1 : 0] cfg_clock_off;
+output [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
+
+// output to timer
+output [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
+output [ADD_LAT_BUS_WIDTH    - 1 : 0] cfg_add_lat;
+output [TCL_BUS_WIDTH        - 1 : 0] cfg_tcl;
+output [BL_BUS_WIDTH         - 1 : 0] cfg_burst_length;
+output [TRRD_BUS_WIDTH       - 1 : 0] cfg_trrd;
+output [TFAW_BUS_WIDTH       - 1 : 0] cfg_tfaw;
+output [TRFC_BUS_WIDTH       - 1 : 0] cfg_trfc;
+output [TREFI_BUS_WIDTH      - 1 : 0] cfg_trefi;
+output [TRCD_BUS_WIDTH       - 1 : 0] cfg_trcd;
+output [TRP_BUS_WIDTH        - 1 : 0] cfg_trp;
+output [TWR_BUS_WIDTH        - 1 : 0] cfg_twr;
+output [TWTR_BUS_WIDTH       - 1 : 0] cfg_twtr;
+output [TRTP_BUS_WIDTH       - 1 : 0] cfg_trtp;
+output [TRAS_BUS_WIDTH       - 1 : 0] cfg_tras;
+output [TRC_BUS_WIDTH        - 1 : 0] cfg_trc;
+output [AUTO_PD_BUS_WIDTH    - 1 : 0] cfg_auto_pd_cycles;
+
+// output to input interface
+output [1 : 0]                         cfg_addr_order;
+output                                 cfg_reorder_data;
+output [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
+output [MEM_IF_CSR_COL_WIDTH  - 1 : 0] cfg_col_addr_width;
+output [MEM_IF_CSR_ROW_WIDTH  - 1 : 0] cfg_row_addr_width;
+output [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
+output [MEM_IF_CSR_CS_WIDTH   - 1 : 0] cfg_cs_addr_width;
+
+//output to ecc
+output cfg_enable_ecc;
+output cfg_enable_auto_corr;
+output cfg_gen_sbe;
+output cfg_gen_dbe;
+output cfg_enable_intr;
+output cfg_mask_sbe_intr;
+output cfg_mask_dbe_intr;
+output cfg_mask_corr_dropped_intr;
+output cfg_clr_intr;
+
+output cfg_regdimm_enable;
+
+wire avalon_mm_waitrequest;
+wire avalon_mm_rdata_valid;
+wire [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
+
+reg int_write_req;
+reg int_read_req;
+reg int_rdata_valid;
+reg [8              - 1       : 0] int_addr; // hard-coded to only 8 bits
+reg [CFG_AVALON_DATA_WIDTH - 1       : 0] int_wdata;
+reg [CFG_AVALON_DATA_WIDTH - 1       : 0] int_rdata;
+reg [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] int_be;
+
+reg int_mask_avalon_mm_write;
+reg int_mask_avalon_mm_read;
+reg int_mask_ecc_avalon_mm_write;
+reg int_mask_ecc_avalon_mm_read;
+
+// output to PHY
+wire                                              cfg_cal_req;
+wire [MEM_IF_CLK_PAIR_COUNT              - 1 : 0] cfg_clock_off;
+wire [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
+
+// output to timer
+wire [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
+wire [ADD_LAT_BUS_WIDTH    - 1 : 0] cfg_add_lat;
+wire [TCL_BUS_WIDTH        - 1 : 0] cfg_tcl;
+wire [BL_BUS_WIDTH         - 1 : 0] cfg_burst_length;
+wire [TRRD_BUS_WIDTH       - 1 : 0] cfg_trrd;
+wire [TFAW_BUS_WIDTH       - 1 : 0] cfg_tfaw;
+wire [TRFC_BUS_WIDTH       - 1 : 0] cfg_trfc;
+wire [TREFI_BUS_WIDTH      - 1 : 0] cfg_trefi;
+wire [TRCD_BUS_WIDTH       - 1 : 0] cfg_trcd;
+wire [TRP_BUS_WIDTH        - 1 : 0] cfg_trp;
+wire [TWR_BUS_WIDTH        - 1 : 0] cfg_twr;
+wire [TWTR_BUS_WIDTH       - 1 : 0] cfg_twtr;
+wire [TRTP_BUS_WIDTH       - 1 : 0] cfg_trtp;
+wire [TRAS_BUS_WIDTH       - 1 : 0] cfg_tras;
+wire [TRC_BUS_WIDTH        - 1 : 0] cfg_trc;
+wire [AUTO_PD_BUS_WIDTH    - 1 : 0] cfg_auto_pd_cycles;
+
+// output to input interface
+wire [1 : 0]                         cfg_addr_order;
+wire                                 cfg_reorder_data;
+wire [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
+wire [MEM_IF_CSR_COL_WIDTH  - 1 : 0] cfg_col_addr_width;
+wire [MEM_IF_CSR_ROW_WIDTH  - 1 : 0] cfg_row_addr_width;
+wire [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
+wire [MEM_IF_CSR_CS_WIDTH   - 1 : 0] cfg_cs_addr_width;
+
+//output to ecc
+wire cfg_enable_ecc;
+wire cfg_enable_auto_corr;
+wire cfg_gen_sbe;
+wire cfg_gen_dbe;
+wire cfg_enable_intr;
+wire cfg_mask_sbe_intr;
+wire cfg_mask_dbe_intr;
+wire cfg_mask_corr_dropped_intr;
+wire cfg_clr_intr;
+
+// output to others
+wire cfg_regdimm_enable;
+
+// CSR read registers
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_100;
+
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_110;
+
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_120;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_121;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_122;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_123;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_124;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_125;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_126;
+
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_130;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_131;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_132;
+
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_133;
+reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_134;
+
+/*------------------------------------------------------------------------------
+
+   CSR Interface
+
+------------------------------------------------------------------------------*/
+// Assign waitrequest signal to '0'
+assign avalon_mm_waitrequest = 1'b0;
+
+generate
+    if (!CTL_CSR_ENABLED && !CTL_ECC_CSR_ENABLED)
+    begin
+        // when both csr and ecc csr is disabled
+        assign avalon_mm_rdata       = 0;
+        assign avalon_mm_rdata_valid = 0;
+    end
+    else
+    begin
+        // register all inputs
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                int_write_req <= 0;
+                int_read_req  <= 0;
+                int_addr      <= 0;
+                int_wdata     <= 0;
+                int_be        <= 0;
+            end
+            else
+            begin
+                int_addr  <= avalon_mm_addr [7 : 0]; // we only need the bottom 8 bits
+                int_wdata <= avalon_mm_wdata;
+                int_be    <= avalon_mm_be;
+                
+                if (avalon_mm_write)
+                    int_write_req <= 1'b1;
+                else
+                    int_write_req <= 1'b0;
+                
+                if (avalon_mm_read)
+                    int_read_req <= 1'b1;
+                else
+                    int_read_req <= 1'b0;
+            end
+        end
+        
+        // Write and read request mask
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                int_mask_avalon_mm_write     <= 1'b0;
+                int_mask_avalon_mm_read      <= 1'b0;
+                int_mask_ecc_avalon_mm_write <= 1'b0;
+                int_mask_ecc_avalon_mm_read  <= 1'b0;
+            end
+            else
+            begin
+                if (CTL_CSR_READ_ONLY)
+                begin
+                    int_mask_avalon_mm_write <= 1'b1;
+                    int_mask_avalon_mm_read  <= 1'b0;
+                end
+                else
+                begin
+                    int_mask_avalon_mm_write <= 1'b0;
+                    int_mask_avalon_mm_read  <= 1'b0;
+                end
+                
+                if (CTL_ECC_CSR_READ_ONLY)
+                begin
+                    int_mask_ecc_avalon_mm_write <= 1'b1;
+                    int_mask_ecc_avalon_mm_read  <= 1'b0;
+                end
+                else
+                begin
+                    int_mask_ecc_avalon_mm_write <= 1'b0;
+                    int_mask_ecc_avalon_mm_read  <= 1'b0;
+                end
+            end
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           Read Interface
+        
+        ------------------------------------------------------------------------------*/
+        assign avalon_mm_rdata       = int_rdata;
+        assign avalon_mm_rdata_valid = int_rdata_valid;
+        
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                int_rdata       <= 0;
+                int_rdata_valid <= 0;
+            end
+            else
+            begin
+                if (int_read_req)
+                begin
+                    if (int_addr == 8'h00)
+                        int_rdata <= read_csr_register_100;
+                    else if (int_addr == 8'h10)
+                        int_rdata <= read_csr_register_110;
+                    else if (int_addr == 8'h20)
+                        int_rdata <= read_csr_register_120;
+                    else if (int_addr == 8'h21)
+                        int_rdata <= read_csr_register_121;
+                    else if (int_addr == 8'h22)
+                        int_rdata <= read_csr_register_122;
+                    else if (int_addr == 8'h23)
+                        int_rdata <= read_csr_register_123;
+                    else if (int_addr == 8'h24)
+                        int_rdata <= read_csr_register_124;
+                    else if (int_addr == 8'h25)
+                        int_rdata <= read_csr_register_125;
+                    else if (int_addr == 8'h26)
+                        int_rdata <= read_csr_register_126;
+                    else if (int_addr == 8'h30)
+                        int_rdata <= read_csr_register_130;
+                    else if (int_addr == 8'h31)
+                        int_rdata <= read_csr_register_131;
+                    else if (int_addr == 8'h32)
+                        int_rdata <= read_csr_register_132;
+                    else if (int_addr == 8'h33)
+                        int_rdata <= read_csr_register_133;
+                    else if (int_addr == 8'h34)
+                        int_rdata <= read_csr_register_134;
+                end
+                
+                if (int_read_req)
+                    int_rdata_valid <= 1'b1;
+                else
+                    int_rdata_valid <= 1'b0;
+            end
+        end
+    end
+endgenerate
+
+/*------------------------------------------------------------------------------
+
+   CSR Registers
+
+------------------------------------------------------------------------------*/
+generate
+    genvar i;
+    if (!CTL_CSR_ENABLED) // when csr is disabled
+    begin
+        // assigning values to the top
+        assign cfg_cas_wr_lat          = CFG_CAS_WR_LAT;
+        assign cfg_add_lat             = CFG_ADD_LAT;
+        assign cfg_tcl                 = CFG_TCL;
+        assign cfg_burst_length        = CFG_BURST_LENGTH;
+        assign cfg_trrd                = CFG_TRRD;
+        assign cfg_tfaw                = CFG_TFAW;
+        assign cfg_trfc                = CFG_TRFC;
+        assign cfg_trefi               = CFG_TREFI;
+        assign cfg_trcd                = CFG_TRCD;
+        assign cfg_trp                 = CFG_TRP;
+        assign cfg_twr                 = CFG_TWR;
+        assign cfg_twtr                = CFG_TWTR;
+        assign cfg_trtp                = CFG_TRTP;
+        assign cfg_tras                = CFG_TRAS;
+        assign cfg_trc                 = CFG_TRC;
+        assign cfg_auto_pd_cycles      = CFG_AUTO_PD_CYCLES;
+        
+        assign cfg_addr_order              = CFG_ADDR_ORDER;
+        assign cfg_reorder_data     = CFG_REORDER_DATA;
+        assign cfg_starve_limit            = CFG_STARVE_LIMIT;
+        assign cfg_cs_addr_width       = CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0;
+        assign cfg_bank_addr_width     = CFG_BANK_ADDR_WIDTH;
+        assign cfg_row_addr_width      = CFG_ROW_ADDR_WIDTH;
+        assign cfg_col_addr_width      = CFG_COL_ADDR_WIDTH;
+        
+        assign cfg_cal_req             = 0;
+        assign cfg_clock_off     = 0;
+        assign ctl_cal_byte_lane_sel_n = 0;
+        
+        assign cfg_regdimm_enable          = 1'b1; // udimm or rdimm determined by parameter CFG_REGDIMM_ENABLE
+	always @ (*)
+	begin
+		// set all to zeros.
+		read_csr_register_100 = 0;
+		read_csr_register_110 = 0;
+		read_csr_register_120 = 0;
+		read_csr_register_121 = 0;
+		read_csr_register_122 = 0;
+		read_csr_register_123 = 0;
+		read_csr_register_124 = 0;
+		read_csr_register_125 = 0;
+		read_csr_register_126 = 0;
+		read_csr_register_134 = 0;
+	end
+    end
+    else
+    begin
+        /*------------------------------------------------------------------------------
+        
+           0x100 ALTMEPHY Status and Control Register
+        
+        ------------------------------------------------------------------------------*/
+        reg         csr_cal_success;
+        reg         csr_cal_fail;
+        reg         csr_cal_req;
+        reg [5 : 0] csr_clock_off;
+        
+        // assign value back to top
+        assign cfg_cal_req         = csr_cal_req;
+        assign cfg_clock_off = csr_clock_off [MEM_IF_CLK_PAIR_COUNT - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_cal_req     <= 0;
+                csr_clock_off   <= 0;
+            end
+            else
+            begin
+                // write request
+                if (int_write_req && int_addr == 8'h00)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_cal_req   <= int_wdata [2]     ;
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_clock_off <= int_wdata [13 : 8];
+                    end
+                end
+            end
+        end
+        
+        // read only registers
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_cal_success <= 0;
+                csr_cal_fail    <= 0;
+            end
+            else
+            begin
+                csr_cal_success <= sts_cal_success;
+                csr_cal_fail    <= sts_cal_fail;
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_100 = 0;
+            
+            // then we set individual bits
+            read_csr_register_100 [0]      = csr_cal_success;
+            read_csr_register_100 [1]      = csr_cal_fail;
+            read_csr_register_100 [2]      = csr_cal_req;
+            read_csr_register_100 [13 : 8] = csr_clock_off;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x110 Controller Status and Control Register
+        
+        ------------------------------------------------------------------------------*/
+        reg [15 : 0] csr_auto_pd_cycles;
+        reg          csr_auto_pd_ack;
+        reg          csr_self_rfsh;    // yyong: remember to handle this
+        reg          csr_self_rfsh_ack;
+        reg          csr_ganged_arf;   // yyong: remember to handle this
+        reg [1  : 0] csr_addr_order;
+        reg          csr_reg_dimm;     // yyong: remember to handle this
+        reg [1  : 0] csr_drate;
+        
+        // assign value back to top
+        assign cfg_auto_pd_cycles = csr_auto_pd_cycles;
+        assign cfg_addr_order         = csr_addr_order;
+        assign cfg_regdimm_enable     = csr_reg_dimm;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_auto_pd_cycles <= CFG_AUTO_PD_CYCLES;  // reset to default value
+                csr_self_rfsh      <= 0;
+                csr_ganged_arf     <= 0;
+                csr_addr_order     <= CFG_ADDR_ORDER;          // reset to default value
+                csr_reg_dimm       <= CFG_REGDIMM_ENABLE; // reset to default value
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h10)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_auto_pd_cycles [ 7 :  0] <= int_wdata [ 7 :  0];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_auto_pd_cycles [15 :  8] <= int_wdata [15 :  8];
+                    end
+                    
+                    if (int_be [2])
+                    begin
+                        csr_self_rfsh      <= int_wdata [17]     ;
+                        csr_ganged_arf     <= int_wdata [19]     ;
+                        csr_addr_order     <= int_wdata [21 : 20];
+                        csr_reg_dimm       <= int_wdata [22]     ;
+                    end
+                end
+            end
+        end
+        
+        // read only registers
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_auto_pd_ack   <= 0;
+                csr_self_rfsh_ack <= 0;
+                csr_drate         <= 0;
+            end
+            else
+            begin
+                csr_auto_pd_ack   <= local_power_down_ack;
+                csr_self_rfsh_ack <= local_self_rfsh_ack;
+                csr_drate         <= (DWIDTH_RATIO == 2) ? 2'b00 : 2'b01; // Fullrate - 00, Halfrate - 01
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_110 = 0;
+            
+            // then we set individual bits
+            read_csr_register_110 [15 : 0 ] = csr_auto_pd_cycles;
+            read_csr_register_110 [16]      = csr_auto_pd_ack;
+            read_csr_register_110 [17]      = csr_self_rfsh;
+            read_csr_register_110 [18]      = csr_self_rfsh_ack;
+            read_csr_register_110 [19]      = csr_ganged_arf;
+            read_csr_register_110 [21 : 20] = csr_addr_order;
+            read_csr_register_110 [22]      = csr_reg_dimm;
+            read_csr_register_110 [24 : 23] = csr_drate;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x120 Memory Address Sizes 0
+        
+        ------------------------------------------------------------------------------*/
+        reg [7 : 0] csr_col_width;
+        reg [7 : 0] csr_row_width;
+        reg [3 : 0] csr_bank_width;
+        reg [3 : 0] csr_chip_width;
+        
+        // assign value back to top
+        assign cfg_cs_addr_width    = csr_chip_width [MEM_IF_CSR_CS_WIDTH   - 1 : 0];
+        assign cfg_bank_addr_width  = csr_bank_width [MEM_IF_CSR_BANK_WIDTH - 1 : 0];
+        assign cfg_row_addr_width   = csr_row_width  [MEM_IF_CSR_ROW_WIDTH  - 1 : 0];
+        assign cfg_col_addr_width   = csr_col_width  [MEM_IF_CSR_COL_WIDTH  - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_col_width  <= CFG_COL_ADDR_WIDTH;                           // reset to default value
+                csr_row_width  <= CFG_ROW_ADDR_WIDTH;                           // reset to default value
+                csr_bank_width <= CFG_BANK_ADDR_WIDTH;                            // reset to default value
+                csr_chip_width <= CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0; // reset to default value
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h20)
+                begin
+                    if (int_be [0])
+                    begin
+                        if (int_wdata [7 : 0] <= CFG_COL_ADDR_WIDTH)
+                        begin
+                            csr_col_width  <= int_wdata [7  : 0 ];
+                        end
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        if (int_wdata [15 : 8] <= CFG_ROW_ADDR_WIDTH)
+                        begin
+                            csr_row_width  <= int_wdata [15 : 8 ];
+                        end
+                    end
+                    
+                    if (int_be [2])
+                    begin
+                        if (int_wdata [19 : 16] <= CFG_BANK_ADDR_WIDTH)
+                        begin
+                            csr_bank_width <= int_wdata [19 : 16];
+                        end
+                        
+                        if (int_wdata [23 : 20] <= (CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0))
+                        begin
+                            csr_chip_width <= int_wdata [23 : 20];
+                        end
+                    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_120 = 0;
+            
+            // then we set individual bits
+            read_csr_register_120 [7  : 0 ] = csr_col_width;
+            read_csr_register_120 [15 : 8 ] = csr_row_width;
+            read_csr_register_120 [19 : 16] = csr_bank_width;
+            read_csr_register_120 [23 : 20] = csr_chip_width;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x121 Memory Address Sizes 1
+        
+        ------------------------------------------------------------------------------*/
+        reg [31 : 0] csr_data_binary_representation;
+        reg [7 : 0] csr_chip_binary_representation;
+        
+        reg [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] cal_byte_lane;
+        
+        // assign value back to top
+        assign ctl_cal_byte_lane_sel_n = ~cal_byte_lane;
+        
+        // determine cal_byte_lane base on csr data
+        for (i = 0;i < CFG_MEM_IF_CS_WIDTH;i = i + 1)
+        begin : ctl_cal_byte_lane_per_chip
+            always @ (posedge ctl_clk or negedge ctl_rst_n)
+            begin
+                if (!ctl_rst_n)
+                    cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= {MEM_IF_DQS_WIDTH{1'b1}}; // setting to all ones
+                else
+                begin
+                    if (csr_chip_binary_representation[i])
+                        cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= csr_data_binary_representation [MEM_IF_DQS_WIDTH - 1 : 0];
+                    else
+                        cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= 0;
+                end
+            end
+        end
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_data_binary_representation <= {MEM_IF_DQS_WIDTH{1'b1}};
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h21)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_data_binary_representation [ 7 :  0] <= int_wdata [ 7 :  0];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_data_binary_representation [15 :  8] <= int_wdata [15 :  8];
+                    end
+                    
+                    if (int_be [2])
+                    begin
+                        csr_data_binary_representation [23 : 16] <= int_wdata [23 : 16];
+                    end
+                    
+                    if (int_be [3])
+                    begin
+                        csr_data_binary_representation [31 : 24] <= int_wdata [31 : 24];
+                    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_121 = 0;
+            
+            // then we set individual bits
+            read_csr_register_121 [31 : 0 ] = csr_data_binary_representation;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x122 Memory Address Sizes 2
+        
+        ------------------------------------------------------------------------------*/
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_chip_binary_representation <= {CFG_MEM_IF_CS_WIDTH{1'b1}};
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h22)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_chip_binary_representation [ 7 :  0] <= int_wdata [7  : 0 ];
+                    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_122 = 0;
+            
+            // then we set individual bits
+            read_csr_register_122 [7  : 0 ] = csr_chip_binary_representation;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x123 Memory Timing Parameters Registers 0
+        
+        ------------------------------------------------------------------------------*/
+        reg [3 : 0] csr_trcd;
+        reg [3 : 0] csr_trrd;
+        reg [3 : 0] csr_trp;
+        reg [3 : 0] csr_tmrd; // yyong: might remove this
+        reg [7 : 0] csr_tras;
+        reg [7 : 0] csr_trc;
+        
+        // assign value back to top
+        assign cfg_trcd = csr_trcd [TRCD_BUS_WIDTH - 1 : 0];
+        assign cfg_trrd = csr_trrd [TRRD_BUS_WIDTH - 1 : 0];
+        assign cfg_trp  = csr_trp  [TRP_BUS_WIDTH  - 1 : 0];
+        assign cfg_tras = csr_tras [TRAS_BUS_WIDTH - 1 : 0];
+        assign cfg_trc  = csr_trc  [TRC_BUS_WIDTH  - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_trcd <= CFG_TRCD; // reset to default value
+                csr_trrd <= CFG_TRRD; // reset to default value
+                csr_trp  <= CFG_TRP;  // reset to default value
+                csr_tmrd <= 0;        // yyong: might remove this
+                csr_tras <= CFG_TRAS; // reset to default value
+                csr_trc  <= CFG_TRC;  // reset to default value
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h23)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_trcd <= int_wdata [3  : 0 ];
+                        csr_trrd <= int_wdata [7  : 4 ];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_trp  <= int_wdata [11 : 8 ];
+                        csr_tmrd <= int_wdata [15 : 12];
+                    end
+                    
+                    if (int_be [2])
+                    begin
+                        csr_tras <= int_wdata [23 : 16];
+                    end
+                    
+                    if (int_be [3])
+                    begin
+                        csr_trc  <= int_wdata [31 : 24];
+                    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_123 = 0;
+            
+            // then we set individual bits
+            read_csr_register_123 [3  : 0 ] = csr_trcd;
+            read_csr_register_123 [7  : 4 ] = csr_trrd;
+            read_csr_register_123 [11 : 8 ] = csr_trp;
+            read_csr_register_123 [15 : 12] = csr_tmrd;
+            read_csr_register_123 [23 : 16] = csr_tras;
+            read_csr_register_123 [31 : 24] = csr_trc;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x124 Memory Timing Parameters Registers 1
+        
+        ------------------------------------------------------------------------------*/
+        reg [3 : 0] csr_twtr;
+        reg [3 : 0] csr_trtp;
+        reg [5 : 0] csr_tfaw;
+        
+        // assign value back to top
+        assign cfg_twtr = csr_twtr [TWTR_BUS_WIDTH - 1 : 0];
+        assign cfg_trtp = csr_trtp [TRTP_BUS_WIDTH - 1 : 0];
+        assign cfg_tfaw = csr_tfaw [TFAW_BUS_WIDTH - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_twtr <= CFG_TWTR;
+                csr_trtp <= CFG_TRTP;
+                csr_tfaw <= CFG_TFAW;
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h24)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_twtr <= int_wdata [3  : 0 ];
+                        csr_trtp <= int_wdata [7  : 4 ];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_tfaw <= int_wdata [13 : 8 ];
+                    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_124 = 0;
+            
+            // then we set individual bits
+            read_csr_register_124 [3  : 0 ] = csr_twtr;
+            read_csr_register_124 [7  : 4 ] = csr_trtp;
+            read_csr_register_124 [15 : 8 ] = csr_tfaw;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x125 Memory Timing Parameters Registers 2
+        
+        ------------------------------------------------------------------------------*/
+        reg [15 : 0] csr_trefi;
+	reg [8  : 0] csr_trfc;	//case:234203
+        
+        // assign value back to top
+        assign cfg_trefi = csr_trefi [TREFI_BUS_WIDTH - 1 : 0];
+        assign cfg_trfc  = csr_trfc  [TRFC_BUS_WIDTH  - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_trefi <= CFG_TREFI;
+                csr_trfc  <= CFG_TRFC;
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h25)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_trefi [ 7 :  0] <= int_wdata [ 7 :  0];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_trefi [15 :  8] <= int_wdata [15 :  8];
+                    end
+                    
+                    if (int_be [2])
+                    begin
+			csr_trfc [ 7 : 0] <= int_wdata [23 : 16];	//case:234203
+                    end
+
+		    if (int_be [3])					//case:234203
+                    begin						//case:234203
+                        csr_trfc [ 8    ] <= int_wdata [24];		//case:234203
+		    end
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_125 = 0;
+            
+            // then we set individual bits
+            read_csr_register_125 [15 : 0 ] = csr_trefi;
+	    read_csr_register_125 [24 : 16] = csr_trfc;	//case:234203
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x126 Memory Timing Parameters Registers 3
+        
+        ------------------------------------------------------------------------------*/
+        reg [3 : 0] csr_tcl;
+        reg [3 : 0] csr_al;
+        reg [3 : 0] csr_cwl;
+	reg [4 : 0] csr_twr;	//case:234203
+        reg [7 : 0] csr_bl;
+        
+        // assign value back to top
+        assign cfg_tcl          = csr_tcl [TCL_BUS_WIDTH        - 1 : 0];
+        assign cfg_add_lat      = csr_al  [ADD_LAT_BUS_WIDTH    - 1 : 0];
+        assign cfg_cas_wr_lat   = csr_cwl [CAS_WR_LAT_BUS_WIDTH - 1 : 0];
+        assign cfg_twr          = csr_twr [TWR_BUS_WIDTH        - 1 : 0];
+        assign cfg_burst_length = csr_bl  [BL_BUS_WIDTH         - 1 : 0];
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_tcl <= CFG_TCL;
+                csr_al  <= CFG_ADD_LAT;
+                csr_cwl <= CFG_CAS_WR_LAT;
+                csr_twr <= CFG_TWR;
+                csr_bl  <= CFG_BURST_LENGTH;
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h26)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_tcl <= int_wdata [3  : 0 ];
+                        csr_al  <= int_wdata [7  : 4 ];
+                    end
+                    
+                    if (int_be [1])
+                    begin
+                        csr_cwl           <= int_wdata [11 : 8 ];
+			csr_twr [ 3 : 0 ] <= int_wdata [15 : 12]; 	//case:234203
+                    end
+
+                    if (int_be [2])
+                    begin
+                        csr_bl  <= int_wdata [23 : 16];
+                    end
+
+		    if (int_be [3])				//case:234203
+                    begin					//case:234203
+                        csr_twr [ 4     ] <= int_wdata [24];	//case:234203
+                    end						//case:234203
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_126 = 0;
+            
+            // then we set individual bits
+            read_csr_register_126 [3  : 0 ] = csr_tcl;
+            read_csr_register_126 [7  : 4 ] = csr_al;
+            read_csr_register_126 [11 : 8 ] = csr_cwl;
+	    read_csr_register_126 [15 : 12] = csr_twr[3:0];	//case:234203
+            read_csr_register_126 [23 : 16] = csr_bl;
+	    read_csr_register_126 [24]      = csr_twr[4];	//case:234203
+        end
+
+        /*------------------------------------------------------------------------------
+        
+           0x134 Controller Status and Control Register - Advanced Features
+        
+        ------------------------------------------------------------------------------*/
+        reg          csr_reorder_data;
+        reg [7 : 0]  csr_starve_limit;
+        
+        // assign value back to top
+        assign cfg_reorder_data = csr_reorder_data;
+        assign cfg_starve_limit = csr_starve_limit;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_reorder_data    <= CFG_REORDER_DATA;
+                csr_starve_limit    <= CFG_STARVE_LIMIT;  // reset to default value
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h34)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_reorder_data <= int_wdata [ 0];
+                    end
+                    
+                    if (int_be [2])
+                    begin
+                        csr_starve_limit <= int_wdata [23 :  16];
+                    end
+                    
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_134 = 0;
+            
+            // then we set individual bits
+            read_csr_register_134 [ 0 ]       = csr_reorder_data;
+            read_csr_register_134 [ 23 : 16 ] = csr_starve_limit;
+        end    
+    end
+	
+    if (!CTL_ECC_CSR_ENABLED)
+    begin
+        assign cfg_enable_ecc              = 1'b0; // default value
+        assign cfg_enable_auto_corr    = 1'b0; // default value
+        assign cfg_gen_sbe             = 0;
+        assign cfg_gen_dbe             = 0;
+        assign cfg_enable_intr         = 1'b0; // default value
+        assign cfg_mask_sbe_intr       = 0;
+        assign cfg_mask_dbe_intr       = 0;
+        assign cfg_clr_intr               = 0;
+        assign cfg_mask_corr_dropped_intr=0;
+    end
+    else
+    begin
+        /*------------------------------------------------------------------------------
+        
+           0x130 ECC Control Register
+        
+        ------------------------------------------------------------------------------*/
+        reg csr_enable_ecc;
+        reg csr_enable_auto_corr;
+        reg csr_gen_sbe;
+        reg csr_gen_dbe;
+        reg csr_enable_intr;
+        reg csr_mask_sbe_intr;
+        reg csr_mask_dbe_intr;
+        reg csr_ecc_clear;
+        reg csr_mask_corr_dropped_intr;
+        
+        // assign value back to top
+        assign cfg_enable_ecc                   = csr_enable_ecc;
+        assign cfg_enable_auto_corr         = csr_enable_auto_corr;
+        assign cfg_gen_sbe                  = csr_gen_sbe;
+        assign cfg_gen_dbe                  = csr_gen_dbe;
+        assign cfg_enable_intr              = csr_enable_intr;
+        assign cfg_mask_sbe_intr            = csr_mask_sbe_intr;
+        assign cfg_mask_dbe_intr            = csr_mask_dbe_intr;
+        assign cfg_clr_intr                    = csr_ecc_clear;
+        assign cfg_mask_corr_dropped_intr   = csr_mask_corr_dropped_intr;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_enable_ecc              <= CFG_ENABLE_ECC;
+                csr_enable_auto_corr        <= CFG_ENABLE_AUTO_CORR;
+                csr_gen_sbe                 <= 0;
+                csr_gen_dbe                 <= 0;
+                csr_enable_intr             <= 1'b1;
+                csr_mask_sbe_intr           <= 0;
+                csr_mask_dbe_intr           <= 0;
+                csr_ecc_clear               <= 0;
+                csr_mask_corr_dropped_intr  <= 0;
+            end
+            else
+            begin
+                // write request
+                if (!int_mask_ecc_avalon_mm_write && int_write_req && int_addr == 8'h30)
+                begin
+                    if (int_be [0])
+                    begin
+                        csr_enable_ecc       <= int_wdata [0];
+                        csr_enable_auto_corr <= int_wdata [1];
+                        csr_gen_sbe          <= int_wdata [2];
+                        csr_gen_dbe          <= int_wdata [3];
+                        csr_enable_intr      <= int_wdata [4];
+                        csr_mask_sbe_intr    <= int_wdata [5];
+                        csr_mask_dbe_intr    <= int_wdata [6];
+                        csr_ecc_clear        <= int_wdata [7];
+                    end
+                    if (int_be [1])
+                    begin
+                        csr_mask_corr_dropped_intr    <= int_wdata [8];
+                    end
+                end
+                
+                // set csr_clear to zero after one clock cycle
+                if (csr_ecc_clear)
+                    csr_ecc_clear     <= 1'b0;
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_130 = 0;
+            
+            // then we set individual bits
+            read_csr_register_130 [0] = csr_enable_ecc;
+            read_csr_register_130 [1] = csr_enable_auto_corr;
+            read_csr_register_130 [2] = csr_gen_sbe;
+            read_csr_register_130 [3] = csr_gen_dbe;
+            read_csr_register_130 [4] = csr_enable_intr;
+            read_csr_register_130 [5] = csr_mask_sbe_intr;
+            read_csr_register_130 [6] = csr_mask_dbe_intr;
+            read_csr_register_130 [7] = csr_ecc_clear;
+            read_csr_register_130 [8] = csr_mask_corr_dropped_intr;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x131 ECC Status Register (Read Only)
+        
+        ------------------------------------------------------------------------------*/
+        reg         csr_sbe_error;
+        reg         csr_dbe_error;
+        reg         csr_corr_dropped;
+        reg [7 : 0] csr_sbe_count;
+        reg [7 : 0] csr_dbe_count;
+        reg [7 : 0] csr_corr_dropped_count;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_sbe_error <= 0;
+                csr_dbe_error <= 0;
+                csr_sbe_count <= 0;
+                csr_dbe_count <= 0;
+                csr_corr_dropped <= 0;
+                csr_corr_dropped_count <= 0;
+            end
+            else
+            begin
+                // all registers are read only registers
+                if (csr_ecc_clear)
+                begin
+                    csr_sbe_error <= 0;
+                    csr_dbe_error <= 0;
+                    csr_sbe_count <= 0;
+                    csr_dbe_count <= 0;
+                    csr_corr_dropped <= 0;
+                    csr_corr_dropped_count <= 0;
+                end
+                else
+                begin
+                    csr_sbe_error <= sts_sbe_error;
+                    csr_dbe_error <= sts_dbe_error;
+                    csr_sbe_count <= sts_sbe_count;
+                    csr_dbe_count <= sts_dbe_count;
+                    csr_corr_dropped <= sts_corr_dropped;
+                    csr_corr_dropped_count <= sts_corr_dropped_count;
+                end
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // first, set all to zeros
+            read_csr_register_131 = 0;
+            
+            // then we set individual bits
+            read_csr_register_131 [0      ] = csr_sbe_error;
+            read_csr_register_131 [1      ] = csr_dbe_error;
+            read_csr_register_131 [2      ] = csr_corr_dropped;
+            read_csr_register_131 [15 : 8 ] = csr_sbe_count;
+            read_csr_register_131 [23 : 16] = csr_dbe_count;
+            read_csr_register_131 [31 : 24] = csr_corr_dropped_count;
+        end
+        
+        /*------------------------------------------------------------------------------
+        
+           0x132 ECC Error Address Register (Read Only)
+        
+        ------------------------------------------------------------------------------*/
+        reg [31 : 0] csr_error_addr;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_error_addr <= 0;
+            end
+            else
+            begin
+                // all registers are read only registers
+                if (csr_ecc_clear)
+                    csr_error_addr <= 0;
+                else
+                    csr_error_addr <= sts_err_addr;
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // then we set individual bits
+            read_csr_register_132 = csr_error_addr;
+        end    
+
+        /*------------------------------------------------------------------------------
+        
+           0x133 ECC Correction Dropped Address Register (Read Only)
+        
+        ------------------------------------------------------------------------------*/
+        reg [31 : 0] csr_corr_dropped_addr;
+        
+        // register arrays to store CSR informations
+        always @ (posedge ctl_clk or negedge ctl_rst_n)
+        begin
+            if (!ctl_rst_n)
+            begin
+                csr_corr_dropped_addr <= 0;
+            end
+            else
+            begin
+                // all registers are read only registers
+                if (csr_ecc_clear)
+                    csr_corr_dropped_addr <= 0;
+                else
+                    csr_corr_dropped_addr <= sts_corr_dropped_addr;
+            end
+        end
+        
+        // assigning read datas back to 32 bit bus
+        always @ (*)
+        begin
+            // then we set individual bits
+            read_csr_register_133 = csr_corr_dropped_addr;
+        end		
+    end
+endgenerate
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v
new file mode 100644
index 0000000..c06525e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v
@@ -0,0 +1,1003 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_dataid_manager
+# (
+    parameter
+        CFG_DATA_ID_WIDTH                   = 8,
+        CFG_DRAM_WLAT_GROUP                 = 1,
+        CFG_LOCAL_WLAT_GROUP                = 1,
+        CFG_BUFFER_ADDR_WIDTH               = 6,
+        CFG_INT_SIZE_WIDTH                  = 1,
+        CFG_TBP_NUM                         = 4,
+        CFG_BURSTCOUNT_TRACKING_WIDTH       = 7,
+        CFG_PORT_WIDTH_BURST_LENGTH         = 5,
+        CFG_DWIDTH_RATIO                    = 2,
+	CFG_ECC_BE_ALLLOW_RMW		    = 0
+)
+(
+
+    // clock & reset
+    ctl_clk,
+    ctl_reset_n,
+
+    // configuration signals
+    cfg_burst_length,
+    cfg_enable_ecc,
+    cfg_enable_auto_corr,
+    cfg_enable_no_dm,
+
+    // update cmd interface
+    update_cmd_if_ready,
+    update_cmd_if_valid,
+    update_cmd_if_data_id,    
+    update_cmd_if_burstcount,    
+    update_cmd_if_tbp_id,    
+                                                                                       
+    // update data interface                                                           
+    update_data_if_valid,
+    update_data_if_data_id,
+    update_data_if_data_id_vector,
+    update_data_if_burstcount,    
+    update_data_if_next_burstcount,    
+  
+    // notify burstcount consumed interface
+    notify_data_if_valid,
+    notify_data_if_burstcount,    
+
+    // notify data ready interface (TBP)
+    notify_tbp_data_ready,
+    notify_tbp_data_partial_be,
+   
+    // buffer write address generate interface
+    write_data_if_ready,
+    write_data_if_valid,
+    write_data_if_accepted,
+    write_data_if_address,
+    write_data_if_partial_be,
+    write_data_if_allzeros_be,
+
+    // buffer read addresss generate interface
+    read_data_if_valid,
+    read_data_if_data_id,
+    read_data_if_data_id_vector,
+    read_data_if_valid_first,
+    read_data_if_data_id_first,
+    read_data_if_data_id_vector_first,
+    read_data_if_valid_first_vector,
+    read_data_if_valid_last,
+    read_data_if_data_id_last,
+    read_data_if_data_id_vector_last,
+    read_data_if_address,
+    read_data_if_datavalid,
+    read_data_if_done
+
+    
+);
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+
+    localparam integer CFG_DATAID_ARRAY_DEPTH      =   (2**CFG_DATA_ID_WIDTH);
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+    
+    // clock & reset 
+    input                                               ctl_clk;
+    input                                               ctl_reset_n;
+    
+    // configuration signals
+    input  [CFG_PORT_WIDTH_BURST_LENGTH    - 1 : 0]     cfg_burst_length;
+    input                                               cfg_enable_ecc;
+    input                                               cfg_enable_auto_corr;
+    input                                               cfg_enable_no_dm;
+    
+    // update cmd interface
+    output                                              update_cmd_if_ready;
+    input                                               update_cmd_if_valid;
+    input   [CFG_DATA_ID_WIDTH-1:0]                     update_cmd_if_data_id;    
+    input   [CFG_INT_SIZE_WIDTH-1:0]                    update_cmd_if_burstcount;    
+    input   [CFG_TBP_NUM-1:0]                           update_cmd_if_tbp_id;    
+                                                                                       
+    // update data interface                                                           
+    input                                               update_data_if_valid;
+    input   [CFG_DATA_ID_WIDTH-1:0]                     update_data_if_data_id;
+    input   [CFG_DATAID_ARRAY_DEPTH-1:0]                update_data_if_data_id_vector;
+    input   [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_data_if_burstcount;    
+    input   [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_data_if_next_burstcount;    
+    
+    // notify data interface
+    output                                              notify_data_if_valid;
+    output  [CFG_INT_SIZE_WIDTH-1:0]                    notify_data_if_burstcount;
+    
+    // notify tbp interface                                                                                           
+    output  [CFG_TBP_NUM-1:0]                           notify_tbp_data_ready;
+    output                                              notify_tbp_data_partial_be;
+    
+    // buffer write address generate interface
+    output                                              write_data_if_ready;
+    input                                               write_data_if_valid;
+    output                                              write_data_if_accepted;
+    output  [CFG_BUFFER_ADDR_WIDTH-1:0]                 write_data_if_address;
+    input                                               write_data_if_partial_be;
+    input						write_data_if_allzeros_be;
+
+    // read data interface
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                           read_data_if_valid;
+    input   [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]         read_data_if_data_id;
+    input   [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0]    read_data_if_data_id_vector;
+    input                                                       read_data_if_valid_first;
+    input   [CFG_DATA_ID_WIDTH-1:0]                             read_data_if_data_id_first;
+    input   [CFG_DATAID_ARRAY_DEPTH-1:0]                        read_data_if_data_id_vector_first;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                           read_data_if_valid_first_vector;
+    input                                                       read_data_if_valid_last;
+    input   [CFG_DATA_ID_WIDTH-1:0]                             read_data_if_data_id_last;
+    input   [CFG_DATAID_ARRAY_DEPTH-1:0]                        read_data_if_data_id_vector_last;
+    output  [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0]     read_data_if_address;
+    output  [CFG_DRAM_WLAT_GROUP-1:0]                           read_data_if_datavalid;
+    output                                                      read_data_if_done;
+   
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    // clock and reset
+    wire                                                ctl_clk;
+    wire                                                ctl_reset_n;
+
+    // configuration signals
+    wire    [CFG_PORT_WIDTH_BURST_LENGTH    - 1 : 0]    cfg_burst_length;
+    wire                                                cfg_enable_ecc;
+    wire                                                cfg_enable_auto_corr;
+    wire                                                cfg_enable_no_dm;
+    
+    // update cmd interface
+    wire                                                update_cmd_if_ready;	
+    wire                                                update_cmd_if_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                     update_cmd_if_data_id;    
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    update_cmd_if_burstcount;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                    update_cmd_if_burstcount_r;
+    wire    [CFG_TBP_NUM-1:0]                           update_cmd_if_tbp_id;    
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 update_cmd_if_address;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 update_cmd_if_address_r;
+                                                                                       
+    // update data interface                                                           
+    wire                                                update_data_if_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                     update_data_if_data_id;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                update_data_if_data_id_vector;
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_data_if_burstcount;    
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_data_if_next_burstcount;    
+  
+    // notify data interface
+    wire                                                notify_data_if_valid;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    notify_data_if_burstcount;    
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                mux_notify_data_if_valid;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                    mux_notify_data_if_burstcount   [CFG_DATAID_ARRAY_DEPTH-1:0];    
+
+    // dataid array
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                dataid_array_valid;
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                dataid_array_data_ready;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 dataid_array_address            [CFG_DATAID_ARRAY_DEPTH-1:0];
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                    dataid_array_burstcount         [CFG_DATAID_ARRAY_DEPTH-1:0]; // mano - this should be CFG_INT_SIZE_WIDTH?
+    reg     [CFG_TBP_NUM-1:0]                           dataid_array_tbp_id             [CFG_DATAID_ARRAY_DEPTH-1:0];
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                mux_dataid_array_done;
+                                                                                                                      
+    // notify tbp interface                                                                                           
+    wire    [CFG_TBP_NUM-1:0]                           notify_tbp_data_ready;
+    reg                                                 notify_tbp_data_partial_be;
+    reg     [CFG_TBP_NUM-1:0]                           mux_tbp_data_ready              [CFG_DATAID_ARRAY_DEPTH-1:0];
+    reg     [CFG_TBP_NUM-1:0]                           tbp_data_ready_r;
+    
+    // buffer write address generate interface
+    reg                                                 write_data_if_ready;
+    wire                                                write_data_if_valid;
+    wire                                                write_data_if_accepted;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 write_data_if_address;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 write_data_if_nextaddress;
+    wire                                                write_data_if_partial_be;
+    wire						write_data_if_allzeros_be;
+
+    // read data interface
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                           read_data_if_valid;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]         read_data_if_data_id;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0]    read_data_if_data_id_vector;
+    reg     [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0]     read_data_if_address;
+    reg     [CFG_DRAM_WLAT_GROUP-1:0]                           read_data_if_datavalid;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                            read_data_if_burstcount;   // used in assertion check
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                         mux_read_data_if_address        [CFG_DATAID_ARRAY_DEPTH-1:0];
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                            mux_read_data_if_burstcount     [CFG_DATAID_ARRAY_DEPTH-1:0];
+    wire                                                        read_data_if_done;
+    
+    reg                                                 write_data_if_address_blocked;
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    reg                                                 cfg_enable_partial_be_notification;
+    reg     [CFG_PORT_WIDTH_BURST_LENGTH    - 1 : 0]    cfg_max_cmd_burstcount;
+    reg     [CFG_PORT_WIDTH_BURST_LENGTH    - 1 : 0]    cfg_max_cmd_burstcount_2x;
+
+    wire                                                update_cmd_if_accepted;
+    reg                                                 update_cmd_if_accepted_r;
+    wire                                                update_cmd_if_address_blocked;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                 update_cmd_if_nextaddress;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 update_cmd_if_nextaddress_r;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 update_cmd_if_nextmaxaddress;
+    reg                                                 update_cmd_if_nextmaxaddress_wrapped;       // nextmaxaddress has wrapped around buffer max address
+    reg     [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_cmd_if_unnotified_burstcount;
+    reg     [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]         update_cmd_if_next_unnotified_burstcount;
+
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                mux_write_data_if_address_blocked;
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                mux_update_cmd_if_address_blocked;
+    reg                     				mux_update_cmd_if_address_blocked_q1;	
+    reg                     				mux_update_cmd_if_address_blocked_q2;	
+    reg                     				mux_update_cmd_if_address_blocked_q3;	
+    reg                     				mux_update_cmd_if_address_blocked_q4;	    
+
+    // error debug signals - used in assertions
+    reg                                                 err_dataid_array_overwritten;
+    reg                                                 err_dataid_array_invalidread;
+    
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 buffer_valid_counter;               // increments on data write, decrements on data read
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 buffer_cmd_unallocated_counter;       // increments by cmd burstcount on update cmd, decrements on data read
+    reg                                                 buffer_valid_counter_full;
+    reg                                                 err_buffer_valid_counter_overflow;
+    reg                                                 err_buffer_cmd_unallocated_counter_overflow;
+   
+    reg                                                 partial_be_detected;
+    reg                                                 partial_be_when_no_cmd_tracked;
+
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                update_data_if_burstcount_greatereq;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                update_data_if_burstcount_same;
+    wire                                                update_data_bc_gt_update_cmd_unnotified_bc;
+
+    wire                                 burstcount_list_read;
+    wire [CFG_INT_SIZE_WIDTH - 1 : 0]    burstcount_list_read_data;
+    wire                                 burstcount_list_read_data_valid;
+    wire                                 burstcount_list_write;
+    wire [CFG_INT_SIZE_WIDTH - 1 : 0]    burstcount_list_write_data;
+    
+    reg                                  update_data_if_burstcount_greatereq_burstcount_list;
+    reg                                  update_data_if_burstcount_same_burstcount_list;
+    
+    
+    integer k;
+
+
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    always @ (*)
+    begin
+        cfg_enable_partial_be_notification = cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
+    end
+    
+    always @ (*)
+    begin
+        cfg_max_cmd_burstcount    = cfg_burst_length / CFG_DWIDTH_RATIO;
+        cfg_max_cmd_burstcount_2x = 2 * cfg_max_cmd_burstcount;
+    end
+
+    assign burstcount_list_write      = update_cmd_if_accepted;
+    assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
+    assign burstcount_list_read       = notify_data_if_valid;
+    
+    // Burst count list to keep track of burst count value,
+    // to be used for comparison with burst count value from burst tracking logic
+    alt_mem_ddrx_list
+    # (
+        .CTL_LIST_WIDTH             (CFG_INT_SIZE_WIDTH),
+        .CTL_LIST_DEPTH             (CFG_DATAID_ARRAY_DEPTH),
+        .CTL_LIST_INIT_VALUE_TYPE   ("ZERO"),
+        .CTL_LIST_INIT_VALID        ("INVALID")
+    )
+    burstcount_list
+    (
+        .ctl_clk                    (ctl_clk),
+        .ctl_reset_n                (ctl_reset_n),
+        .list_get_entry_valid       (burstcount_list_read_data_valid),
+        .list_get_entry_ready       (burstcount_list_read),
+        .list_get_entry_id          (burstcount_list_read_data),
+        .list_get_entry_id_vector   (),
+        .list_put_entry_valid       (burstcount_list_write),
+        .list_put_entry_ready       (),
+        .list_put_entry_id          (burstcount_list_write_data)
+    );
+    
+    always @ (*)
+    begin
+        if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
+        begin
+            update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
+        end
+        else
+        begin
+            update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
+        end
+        
+        if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
+        begin
+            update_data_if_burstcount_same_burstcount_list = 1'b1;
+        end
+        else
+        begin
+            update_data_if_burstcount_same_burstcount_list = 1'b0;
+        end
+    end
+    
+    // dataid_array management
+    genvar i;
+    generate
+        for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1) 
+        begin : gen_dataid_array_management
+
+            assign update_data_if_burstcount_greatereq  [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
+            assign update_data_if_burstcount_same       [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n) 
+            begin
+                if (~ctl_reset_n)
+                begin
+                    dataid_array_address    [i] <= 0;
+                    dataid_array_burstcount [i] <= 0;
+                    dataid_array_tbp_id     [i] <= 0;
+                    dataid_array_data_ready [i] <= 1'b0;
+                    dataid_array_valid      [i] <= 1'b0;
+                    mux_dataid_array_done   [i] <= 1'b0;
+                    
+                    err_dataid_array_overwritten <= 0;
+                    err_dataid_array_invalidread <= 0;
+                end
+                else
+                begin
+                    // update cmd, update data & read data will not happen on same cycle
+
+                    // update cmd interface
+                    if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
+                    begin
+                        dataid_array_address    [i] <=  update_cmd_if_address;
+                        dataid_array_burstcount [i] <=  update_cmd_if_burstcount;
+                        dataid_array_tbp_id     [i] <=  update_cmd_if_tbp_id;
+                        dataid_array_valid      [i] <=  1'b1;
+                        mux_dataid_array_done   [i] <=  1'b0;
+                        
+                        if (dataid_array_valid[i])
+                        begin
+                            err_dataid_array_overwritten <= 1;
+                        end
+                    end
+
+                    // update data interface
+                    if (update_data_if_burstcount_greatereq[i])
+                    begin
+                        dataid_array_data_ready         [i] <= 1'b1;
+                    end
+
+                    // read data interface
+                    if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
+                    begin
+                        dataid_array_address    [i] <=  dataid_array_address    [i] + 1;
+                        dataid_array_burstcount [i] <=  dataid_array_burstcount [i] - 1;
+                        dataid_array_data_ready [i] <=  0;
+                        
+                        if (dataid_array_burstcount [i] == 1'b1)
+                        begin
+                            dataid_array_valid    [i] <=  1'b0;
+                            mux_dataid_array_done [i] <=  1'b1;
+                        end
+                        else
+                        begin
+                            mux_dataid_array_done [i] <=  1'b0;
+                        end
+                        
+                        if (~dataid_array_valid[i])
+                        begin
+                            err_dataid_array_invalidread <= 1;
+                        end
+                    end
+                    else
+                    begin
+                        mux_dataid_array_done [i] <=  1'b0;
+                    end
+
+                end
+            end
+
+            always @ (*)
+            begin
+                if (update_data_if_burstcount_greatereq[i])
+                begin
+                    mux_notify_data_if_valid [i] = 1'b1;
+                end
+                else
+                begin
+                    mux_notify_data_if_valid [i] = 1'b0;
+                end
+            end
+
+        end
+    endgenerate
+
+    // mux to generate signals from output of dataid_array
+
+    // 1. notify TBP that data is ready to be read
+    // 2. notify other blocks burstcount consumed by dataid_array entry
+    // 3. generate read data address
+
+    
+    assign notify_data_if_valid     = update_data_if_burstcount_greatereq_burstcount_list;
+    assign notify_data_if_burstcount= burstcount_list_read_data;
+
+    assign read_data_if_burstcount  = mux_read_data_if_burstcount   [CFG_DATAID_ARRAY_DEPTH-1];
+    assign read_data_if_done        = |mux_dataid_array_done;
+    
+    assign update_cmd_if_address_blocked= mux_update_cmd_if_address_blocked_q1 | mux_update_cmd_if_address_blocked_q2 | mux_update_cmd_if_address_blocked_q3 | mux_update_cmd_if_address_blocked_q4;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        	begin
+            	mux_update_cmd_if_address_blocked_q1 <= 0;
+		mux_update_cmd_if_address_blocked_q2 <= 0;
+            	mux_update_cmd_if_address_blocked_q3 <= 0;
+		mux_update_cmd_if_address_blocked_q4 <= 0;
+		end
+        else
+        	begin
+            	mux_update_cmd_if_address_blocked_q1 <= |mux_update_cmd_if_address_blocked[(CFG_DATAID_ARRAY_DEPTH-1):(CFG_DATAID_ARRAY_DEPTH/4*3)];
+		mux_update_cmd_if_address_blocked_q2 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4*3)-1):(CFG_DATAID_ARRAY_DEPTH/2)];
+		mux_update_cmd_if_address_blocked_q3 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/2)-1):(CFG_DATAID_ARRAY_DEPTH/4)];
+		mux_update_cmd_if_address_blocked_q4 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4)-1):0];
+		end
+    end     
+    
+    generate
+        if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
+        begin
+            always @ (*)
+            begin
+                read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
+            end
+        end
+        else
+        begin
+            wire                                 rdata_address_list_read;
+            wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
+            wire                                 rdata_address_list_read_data_valid;
+            wire                                 rdata_address_list_write;
+            wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
+            
+            assign rdata_address_list_read       = read_data_if_valid_last;
+            assign rdata_address_list_write      = read_data_if_valid_first;
+            assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
+            
+            // Read data address list, to keep track of read address to different write data buffer group
+            alt_mem_ddrx_list
+            # (
+                .CTL_LIST_WIDTH             (CFG_BUFFER_ADDR_WIDTH),
+                .CTL_LIST_DEPTH             (CFG_DRAM_WLAT_GROUP),
+                .CTL_LIST_INIT_VALUE_TYPE   ("ZERO"),
+                .CTL_LIST_INIT_VALID        ("INVALID")
+            )
+            rdata_address_list
+            (
+                .ctl_clk                    (ctl_clk),
+                .ctl_reset_n                (ctl_reset_n),
+                .list_get_entry_valid       (rdata_address_list_read_data_valid),
+                .list_get_entry_ready       (rdata_address_list_read),
+                .list_get_entry_id          (rdata_address_list_read_data),
+                .list_get_entry_id_vector   (),
+                .list_put_entry_valid       (rdata_address_list_write),
+                .list_put_entry_ready       (),
+                .list_put_entry_id          (rdata_address_list_write_data)
+            );
+            
+            for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
+            begin : rdata_if_address_per_dqs_group
+                always @ (*)
+                begin
+                    if (read_data_if_valid_first_vector [i])
+                    begin
+                        read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
+                    end
+                    else
+                    begin
+                        read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            write_data_if_address_blocked <= 0;
+        end
+        else
+        begin
+            write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
+        end
+    end
+
+    always @ (*) 
+    begin
+        mux_tbp_data_ready                          [0] = (mux_notify_data_if_valid          [0]) ? dataid_array_tbp_id     [0] : {CFG_TBP_NUM{1'b0}};
+        mux_notify_data_if_burstcount               [0] = (mux_notify_data_if_valid          [0]) ? dataid_array_burstcount [0] : 0;
+        mux_read_data_if_address                    [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address    [0] : 0;
+        mux_read_data_if_burstcount                 [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
+
+        mux_write_data_if_address_blocked           [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
+
+        if (update_cmd_if_nextmaxaddress_wrapped)
+        begin
+            mux_update_cmd_if_address_blocked   [0] =  (dataid_array_valid[0] & ~( (dataid_array_address[0] <  update_cmd_if_address) & (dataid_array_address[0] >  update_cmd_if_nextmaxaddress) ));
+        end
+        else
+        begin
+            mux_update_cmd_if_address_blocked   [0] =  (dataid_array_valid[0] &  ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
+        end
+    end
+
+    genvar j;
+    generate
+        for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
+        begin : gen_mux_dataid_array_output
+            always @ (*) 
+            begin
+                mux_tbp_data_ready                  [j] = mux_tbp_data_ready            [j-1] | ( (mux_notify_data_if_valid          [j]) ? dataid_array_tbp_id     [j] : {CFG_TBP_NUM{1'b0}} );
+                mux_notify_data_if_burstcount       [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid          [j]) ? dataid_array_burstcount [j] : 0 );
+                mux_read_data_if_address            [j] = mux_read_data_if_address      [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address    [j] : 0 );
+                mux_read_data_if_burstcount         [j] = mux_read_data_if_burstcount   [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
+
+                mux_write_data_if_address_blocked   [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
+
+                if (update_cmd_if_nextmaxaddress_wrapped)
+                begin
+                    mux_update_cmd_if_address_blocked   [j] =  (dataid_array_valid[j] & ~( (dataid_array_address[j] <  update_cmd_if_address) & (dataid_array_address[j] >  update_cmd_if_nextmaxaddress) ));
+                end
+                else
+                begin
+                    mux_update_cmd_if_address_blocked   [j] =  (dataid_array_valid[j] &  ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
+                end
+            end
+        end
+    endgenerate
+   
+    assign notify_tbp_data_ready    = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
+
+
+    // address generation for data location in buffer
+    
+    assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
+    assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            update_cmd_if_accepted_r    <= 0;
+            update_cmd_if_address_r     <= 0;
+            update_cmd_if_nextaddress_r <= 0;
+        end
+        else
+        begin
+            update_cmd_if_accepted_r    <= update_cmd_if_accepted;
+            update_cmd_if_address_r     <= update_cmd_if_address;
+            update_cmd_if_nextaddress_r <= update_cmd_if_nextaddress;
+        end
+    end
+    
+    always @ (*)
+    begin
+        if (update_cmd_if_accepted_r)
+        begin
+            update_cmd_if_address = update_cmd_if_nextaddress_r;
+        end
+        else
+        begin
+            update_cmd_if_address = update_cmd_if_address_r;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            write_data_if_address                <= 0;
+            write_data_if_nextaddress            <= 0;
+        end
+        else
+        begin
+            if (write_data_if_accepted)
+            begin
+                write_data_if_address     <= write_data_if_address + 1;
+                write_data_if_nextaddress <= write_data_if_address + 2;
+            end
+            else
+            begin
+                write_data_if_nextaddress <= write_data_if_address + 1;
+            end
+        end
+    end  
+    
+    always @ (*)
+    begin
+        update_cmd_if_nextmaxaddress = update_cmd_if_address + cfg_max_cmd_burstcount_2x;
+    end
+    
+    always @ (*)
+    begin
+        if (update_cmd_if_address > update_cmd_if_nextmaxaddress)
+        begin
+            update_cmd_if_nextmaxaddress_wrapped = 1'b1;
+        end
+        else
+        begin
+            update_cmd_if_nextmaxaddress_wrapped = 1'b0;
+        end
+    end
+
+    // un-notified burstcount counter
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            update_cmd_if_next_unnotified_burstcount <= 0;
+        end
+        else
+        begin
+            update_cmd_if_next_unnotified_burstcount <= update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            update_cmd_if_burstcount_r <= 0;
+        end
+        else
+        begin
+            update_cmd_if_burstcount_r <= update_cmd_if_burstcount;
+        end
+    end
+    
+    always @ (*)
+    begin
+        if (update_cmd_if_accepted_r)
+        begin
+            update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount + update_cmd_if_burstcount_r;
+        end
+        else
+        begin
+            update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount;
+        end
+    end
+
+
+
+
+    // currently buffer_cmd_unallocated_counter only used for debug purposes
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
+            err_buffer_cmd_unallocated_counter_overflow <= 0;
+        end
+        else
+        begin
+
+            if (update_cmd_if_accepted & read_data_if_valid_last)
+            begin
+                // write & read at same time
+                buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
+            end
+            else if (update_cmd_if_accepted)
+            begin
+                // write only
+                {err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
+            end
+            else if (read_data_if_valid_last)
+            begin
+                // read only
+                buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
+            end
+            else
+            begin
+                buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
+            end
+
+        end
+    end
+
+    assign update_cmd_if_ready     = ~update_cmd_if_address_blocked;
+    assign  write_data_if_accepted = write_data_if_ready & write_data_if_valid;
+
+    always @ (*) 
+    begin
+
+        if (write_data_if_address_blocked)
+        begin
+            // can't write ahead of lowest address currently tracked by dataid array
+            write_data_if_ready = 1'b0;
+        end
+        else 
+        begin
+            // buffer is full when every location has been written
+            // if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
+            write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
+        end
+
+    end
+
+
+    // generate buffread_datavalid. 
+    // data is valid one cycle after adddress is presented to the buffer
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            read_data_if_datavalid <= 0;
+        end
+        else
+        begin
+            read_data_if_datavalid <= read_data_if_valid;
+        end
+    end
+
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            buffer_valid_counter              <= 0;
+            buffer_valid_counter_full         <= 1'b0;
+            err_buffer_valid_counter_overflow <= 0;
+        end
+        else
+        begin
+
+            if (write_data_if_accepted & read_data_if_valid_last)
+            begin
+                // write & read at same time
+                buffer_valid_counter      <= buffer_valid_counter;
+                buffer_valid_counter_full <= buffer_valid_counter_full;
+            end
+            else if (write_data_if_accepted)
+            begin
+                // write only
+                {err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
+                
+                if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
+                begin
+                    buffer_valid_counter_full <= 1'b1;
+                end
+                else
+                begin
+                    buffer_valid_counter_full <= 1'b0;
+                end
+            end
+            else if (read_data_if_valid_last)
+            begin
+                // read only
+                buffer_valid_counter      <= buffer_valid_counter - 1;
+                buffer_valid_counter_full <= 1'b0;
+            end
+            else
+            begin
+                buffer_valid_counter      <= buffer_valid_counter;
+                buffer_valid_counter_full <= buffer_valid_counter_full;
+            end
+
+
+        end
+    end
+
+    // partial be generation logic
+
+    always @ (*) 
+    begin
+        if (partial_be_when_no_cmd_tracked)
+        begin
+            notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
+        end
+        else
+        begin
+            notify_tbp_data_partial_be = partial_be_detected;
+        end    
+    end
+
+    assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
+	
+	generate
+		if (CFG_ECC_BE_ALLLOW_RMW) begin
+			reg							detect_all_zeros_be;
+			reg							detect_all_ones_be;
+			reg							detect_partial_write_be;
+	
+			always @ (posedge ctl_clk or negedge ctl_reset_n) 
+			begin 
+				if (~ctl_reset_n)
+				begin
+					detect_all_zeros_be <= 1'b0;
+					detect_partial_write_be <= 1'b0;
+					detect_all_ones_be	<= 1'b0;
+				end
+				else begin
+					if (write_data_if_accepted & write_data_if_allzeros_be)
+					begin
+						detect_all_zeros_be <= 1'b1;
+					end
+					
+					else if (write_data_if_accepted & ~write_data_if_partial_be & ~write_data_if_allzeros_be)
+					begin
+						detect_all_ones_be <= 1'b1;
+					end
+					
+					else if (write_data_if_accepted & write_data_if_partial_be)
+					begin
+						detect_partial_write_be <= 1'b1;
+					end
+		
+					else if (|update_data_if_burstcount_same)
+					begin
+						detect_all_zeros_be <= 1'b0;
+						detect_partial_write_be <= 1'b0;
+						detect_all_ones_be <= 1'b0;
+					end
+				end
+			end
+		
+			always @ (*)
+			begin
+				if (|update_data_if_burstcount_same)
+				begin
+					if (detect_partial_write_be)
+					begin
+						partial_be_detected = 1'b1;
+					end
+					else if (detect_all_zeros_be & ~detect_all_ones_be)
+					begin
+						partial_be_detected = 1'b1;
+					end
+					else
+					begin
+						partial_be_detected = 1'b0;
+					end
+				end
+				else
+				begin
+					partial_be_detected = 1'b0;
+				end
+			end
+		
+			always @ (posedge ctl_clk or negedge ctl_reset_n) 
+			begin
+				if (~ctl_reset_n)
+				begin
+					partial_be_when_no_cmd_tracked <= 1'b0;
+				end
+				else
+				begin
+					if (cfg_enable_partial_be_notification)
+					begin
+						if (partial_be_when_no_cmd_tracked)
+						begin
+							if (update_data_if_valid & ~notify_data_if_valid)
+							begin
+								// there's finally a cmd being tracked, but there's insufficient data in buffer
+								// this cmd has partial be
+								partial_be_when_no_cmd_tracked <= 1'b0;
+							end
+							else if (update_data_if_valid & notify_data_if_valid)
+							begin
+								// there's finally a cmd being tracked, and there's sufficient data in buffer
+								if (|update_data_if_burstcount_same)
+								begin
+									// this command has partial be
+									partial_be_when_no_cmd_tracked <= 1'b0;
+								end
+								else
+								begin
+									// this command doesnt have partial be
+									// let partial_be_when_no_cmd_tracked continue asserted
+								end
+							end
+						end
+						else
+						begin
+							partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
+						end
+					end
+					else
+					begin
+						partial_be_when_no_cmd_tracked <= 1'b0;
+					end
+				end
+			end
+			
+		end
+		else begin
+			
+			always @ (posedge ctl_clk or negedge ctl_reset_n) 
+			begin
+				if (~ctl_reset_n)
+				begin
+					partial_be_when_no_cmd_tracked <= 1'b0;
+					partial_be_detected <= 1'b0;
+				end
+				else
+				begin
+					if (cfg_enable_partial_be_notification)
+					begin
+						if (partial_be_when_no_cmd_tracked)
+						begin
+							if (update_data_if_valid & ~notify_data_if_valid)
+							begin
+								// there's finally a cmd being tracked, but there's insufficient data in buffer
+								// this cmd has partial be
+								partial_be_when_no_cmd_tracked <= 1'b0;
+							end
+							else if (update_data_if_valid & notify_data_if_valid)
+							begin
+								// there's finally a cmd being tracked, and there's sufficient data in buffer
+								if (|update_data_if_burstcount_same)
+								begin
+									// this command has partial be
+									partial_be_when_no_cmd_tracked <= 1'b0;
+									partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
+								end
+								else
+								begin
+									// this command doesnt have partial be
+									// let partial_be_when_no_cmd_tracked continue asserted
+								end
+							end
+						end
+						else if (partial_be_detected & ~notify_data_if_valid)
+						begin
+							partial_be_detected <= partial_be_detected;
+						end
+						else
+						begin
+							partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
+							partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
+						end
+					end
+					else
+					begin
+						partial_be_when_no_cmd_tracked <= 1'b0;
+						partial_be_detected <= 1'b0;
+					end
+				end
+			end
+				
+		end
+	endgenerate
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
new file mode 100644
index 0000000..d55302f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
@@ -0,0 +1,458 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+//For tCL = 3 and tCWL = 2 rdwr_data_tmg block output must be registered in order to support ODT
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_ddr2_odt_gen
+    # ( parameter
+        CFG_DWIDTH_RATIO              =   2,
+        CFG_PORT_WIDTH_ADD_LAT        =   3,
+        CFG_PORT_WIDTH_OUTPUT_REGD    =   1,
+        CFG_PORT_WIDTH_TCL            =   4
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        cfg_tcl,
+        cfg_add_lat,
+        cfg_burst_length,
+        cfg_output_regd,
+        bg_do_write,
+        bg_do_read,
+        int_odt_l,
+        int_odt_h
+    );
+    
+    //=================================================================================================//
+    //        Local parameter definition                                                               //
+    //=================================================================================================//
+    
+    localparam  integer CFG_TCL_PIPE_LENGTH =   2**CFG_PORT_WIDTH_TCL; // okay to size this to 4 since max latency in DDR2 is 7+6=13
+    localparam          CFG_TAOND           =   2;
+    localparam          CFG_TAOFD           =   2.5;
+    
+    //=================================================================================================//
+    //        input/output declaration                                                                 //
+    //=================================================================================================//
+    
+    input                                    ctl_clk;
+    input                                    ctl_reset_n;
+    input   [CFG_PORT_WIDTH_TCL-1:0]         cfg_tcl;
+    input   [CFG_PORT_WIDTH_ADD_LAT-1:0]     cfg_add_lat;
+    input   [4:0]                            cfg_burst_length;
+    input   [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
+    
+    input                                    bg_do_write;
+    input                                    bg_do_read;
+    
+    output                                   int_odt_l;
+    output                                   int_odt_h;
+    
+    //=================================================================================================//
+    //        reg/wire declaration                                                                     //
+    //=================================================================================================//
+    
+    wire bg_do_write;
+    wire bg_do_read;
+    
+    reg  [1:0] regd_output;
+    
+    reg  [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
+    reg  [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
+    reg                           int_tcwl_even;
+    reg                           int_tcwl_odd;
+    
+    reg  [CFG_PORT_WIDTH_TCL-1:0] write_latency;
+    reg  [CFG_PORT_WIDTH_TCL-1:0] read_latency;
+    
+    wire int_odt_l;
+    wire int_odt_h;
+    
+    reg reg_odt_l;
+    reg reg_odt_h;
+    
+    reg combi_odt_l;
+    reg combi_odt_h;
+    
+    reg [1:0] offset_code;
+    
+    reg start_odt_write;
+    reg start_odt_read;
+    
+    reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
+    reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
+    
+    reg [3:0]   doing_write_count;
+    reg [3:0]   doing_read_count;
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    regd_output <= 0;
+                end
+            else
+                begin
+                    if (cfg_output_regd)
+                        regd_output <= (CFG_DWIDTH_RATIO / 2) * cfg_output_regd;
+                    else
+                        regd_output <= 2'd0;
+                end
+        end
+    
+    always @ (*)
+        begin
+            int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                int_tcwl    <=  0;
+            else
+                int_tcwl    <=  int_tcwl_unreg;
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    int_tcwl_even <= 1'b0;
+                    int_tcwl_odd  <= 1'b0;
+                end
+            else
+                begin
+                    if (int_tcwl % 2 == 0)
+                        begin
+                            int_tcwl_even <= 1'b1;
+                            int_tcwl_odd  <= 1'b0;
+                        end
+                    else
+                        begin
+                            int_tcwl_even <= 1'b0;
+                            int_tcwl_odd  <= 1'b1;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    write_latency <= 0;
+                    read_latency  <= 0;
+                end
+            else
+                begin
+                    write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
+                    read_latency  <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
+                end
+        end
+    
+    //=================================================================================================//
+    //        Delay ODT signal to match READ DQ/DQS                                                    //
+    //=================================================================================================//
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                do_read_pipe    <=  0;
+            else
+                if (bg_do_read)
+                    do_read_pipe    <=  {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
+                else
+                    do_read_pipe    <=  {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
+        end
+    
+    always @(*)
+        begin
+            if (int_tcwl < 3)
+                start_odt_read  =  bg_do_read;
+            else
+                start_odt_read  =  do_read_pipe[read_latency];
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin doing_read_count   <=  0; end
+            else
+                begin
+                    if (start_odt_read)
+                        begin
+                            if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
+                                doing_read_count   <=  1;
+                            else
+                                doing_read_count   <=  0;
+                        end
+                    else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
+                        begin
+                            doing_read_count   <=  0;
+                        end
+                    else if (doing_read_count > 0)
+                        begin
+                            doing_read_count   <=  doing_read_count + 1'b1;
+                        end
+                end
+        end
+    
+    //=================================================================================================//
+    //        Delay ODT signal to match WRITE DQ/DQS                                                   //
+    //=================================================================================================//
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                do_write_pipe    <=  0;
+            else
+                if (bg_do_write)
+                    do_write_pipe    <=  {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
+                else
+                    do_write_pipe    <=  {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
+        end
+    
+    always @(*)
+        begin
+            if (int_tcwl < 4)
+                start_odt_write =  bg_do_write;
+            else
+                start_odt_write =  do_write_pipe[write_latency];
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                doing_write_count   <=  0;
+            else
+                if (start_odt_write)
+                    begin
+                        if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
+                            doing_write_count   <=  1;
+                        else
+                            doing_write_count   <=  0;
+                    end
+                else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
+                    begin
+                        doing_write_count   <=  0;
+                    end
+                else if (doing_write_count > 0)
+                    begin
+                        doing_write_count   <=  doing_write_count + 1'b1;
+                    end
+        end
+    
+    //=================================================================================================//
+    //        ODT signal generation block                                                              //
+    //=================================================================================================//
+    
+    always @ (*)
+        begin
+            if (CFG_DWIDTH_RATIO == 2) // full rate
+                begin
+                    if (start_odt_write || start_odt_read)
+                        begin
+                            combi_odt_h = 1'b1;
+                            combi_odt_l = 1'b1;
+                        end
+                    else
+                        begin
+                            combi_odt_h = 1'b0;
+                            combi_odt_l = 1'b0;
+                        end
+                end
+            else // half and quarter rate
+                begin
+                    if (int_tcwl_even)
+                        begin
+                            if (start_odt_write)
+                                begin
+                                    combi_odt_h = 1'b1;
+                                    combi_odt_l = 1'b1;
+                                end
+                            else if (start_odt_read)
+                                begin
+                                    combi_odt_h = 1'b1;
+                                    combi_odt_l = 1'b0;
+                                end
+                            else
+                                begin
+                                    combi_odt_h = 1'b0;
+                                    combi_odt_l = 1'b0;
+                                end
+                        end
+                    else
+                        begin
+                            if (start_odt_write)
+                                begin
+                                    combi_odt_h = 1'b1;
+                                    combi_odt_l = 1'b0;
+                                end
+                            else if (start_odt_read)
+                                begin
+                                    combi_odt_h = 1'b1;
+                                    combi_odt_l = 1'b1;
+                                end
+                            else
+                                begin
+                                    combi_odt_h = 1'b0;
+                                    combi_odt_l = 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    reg_odt_h <= 1'b0;
+                    reg_odt_l <= 1'b0;
+                end
+            else
+                begin
+                    if (CFG_DWIDTH_RATIO == 2) // full rate
+                        begin
+                            if (start_odt_write || start_odt_read)
+                                begin
+                                    reg_odt_h <= 1'b1;
+                                    reg_odt_l <= 1'b1;
+                                end
+                            else if (doing_write_count > 0 || doing_read_count > 0)
+                                begin
+                                    reg_odt_h <= 1'b1;
+                                    reg_odt_l <= 1'b1;
+                                end
+                            else
+                                begin
+                                    reg_odt_h <= 1'b0;
+                                    reg_odt_l <= 1'b0;
+                                end
+                        end
+                    else // half and quarter rate
+                        begin
+                            if (start_odt_write)
+                                begin
+                                    if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
+                                        begin
+                                            reg_odt_h <= 1'b1;
+                                            reg_odt_l <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            if (int_tcwl_even)
+                                                begin
+                                                    reg_odt_h <= 1'b0;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    reg_odt_h <= 1'b1;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                        end
+                                end
+                            else if (start_odt_read)
+                                begin
+                                    if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
+                                        begin
+                                            reg_odt_h <= 1'b1;
+                                            reg_odt_l <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            if (int_tcwl_odd)
+                                                begin
+                                                    reg_odt_h <= 1'b0;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    reg_odt_h <= 1'b1;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                        end
+                                end
+                            else if (doing_write_count > 0)
+                                begin
+                                    if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
+                                        begin
+                                            reg_odt_h <= 1'b1;
+                                            reg_odt_l <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            if (int_tcwl_even)
+                                                begin
+                                                    reg_odt_h <= 1'b0;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    reg_odt_h <= 1'b1;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                        end
+                                end
+                            else if (doing_read_count > 0)
+                                begin
+                                    if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
+                                        begin
+                                            reg_odt_h <= 1'b1;
+                                            reg_odt_l <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            if (int_tcwl_odd)
+                                                begin
+                                                    reg_odt_h <= 1'b0;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    reg_odt_h <= 1'b1;
+                                                    reg_odt_l <= 1'b1;
+                                                end
+                                        end
+                                end
+                            else
+                                begin
+                                    reg_odt_h <= 1'b0;
+                                    reg_odt_l <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    generate
+        if (CFG_DWIDTH_RATIO == 2) // full rate
+            begin
+                assign  int_odt_h   = combi_odt_h | reg_odt_h;
+                assign  int_odt_l   = combi_odt_h | reg_odt_h;
+            end
+        else if (CFG_DWIDTH_RATIO == 4) // half rate
+            begin
+                assign  int_odt_h   = combi_odt_h | reg_odt_h;
+                assign  int_odt_l   = combi_odt_l | reg_odt_l;
+            end
+        else if (CFG_DWIDTH_RATIO == 8) // quarter rate
+            begin
+                
+            end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
new file mode 100644
index 0000000..56af284
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
@@ -0,0 +1,473 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10036 10230
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_ddr3_odt_gen
+    # (parameter
+        CFG_DWIDTH_RATIO             =   2,
+        CFG_PORT_WIDTH_OUTPUT_REGD   =   1,
+        CFG_PORT_WIDTH_TCL           =   4,
+        CFG_PORT_WIDTH_CAS_WR_LAT    =   4
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        cfg_tcl,
+        cfg_cas_wr_lat,
+        cfg_output_regd,
+        bg_do_write,
+        bg_do_read,
+        bg_do_burst_chop,
+        int_odt_l,
+        int_odt_h,
+        int_odt_i_1,
+        int_odt_i_2
+    );
+    
+    localparam  integer CFG_TCL_PIPE_LENGTH =   2**CFG_PORT_WIDTH_TCL;
+    //=================================================================================================//
+    //        DDR3 ODT timing parameters                                                               //
+    //=================================================================================================//
+    
+    localparam integer    CFG_ODTH8             = 6; //Indicates No. of cycles ODT signal should stay high
+    localparam integer    CFG_ODTH4             = 4; //Indicates No. of cycles ODT signal should stay high
+    localparam integer    CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO / 2;
+    // AL also applies to ODT signal so ODT logic is AL agnostic
+    // also regdimm because ODT is registered too
+    // ODTLon = CWL + AL - 2
+    // ODTLoff = CWL + AL - 2
+    
+    //=================================================================================================//
+    //        input/output declaration                                                                 //
+    //=================================================================================================//
+    
+    input   ctl_clk;
+    input   ctl_reset_n;
+    input   [CFG_PORT_WIDTH_TCL-1:0]         cfg_tcl;
+    input   [CFG_PORT_WIDTH_CAS_WR_LAT-1:0]  cfg_cas_wr_lat;
+    input   [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
+    input   bg_do_write;
+    input   bg_do_read;
+    input   bg_do_burst_chop;
+    output  int_odt_l;
+    output  int_odt_h;
+    output  int_odt_i_1;
+    output  int_odt_i_2;
+    
+    //=================================================================================================//
+    //        reg/wire declaration                                                                     //
+    //=================================================================================================//
+    
+    wire    bg_do_write;
+    reg     int_do_read;
+    reg     int_do_write_burst_chop;
+    reg     int_do_read_burst_chop;
+    reg     int_do_read_burst_chop_c;
+    reg     do_read_r;
+    
+    wire [3:0]  diff_unreg;                 // difference between CL and CWL
+    reg  [3:0]  diff;
+    wire [3:0]  diff_modulo_unreg;
+    reg  [3:0]  diff_modulo;
+    wire [3:0]  sel_do_read_pipe_unreg;
+    reg  [3:0]  sel_do_read_pipe;
+    reg         diff_modulo_not_zero;
+    reg         diff_modulo_one;
+    reg         diff_modulo_two;
+    reg         diff_modulo_three;
+    
+    reg     int_odt_l_int;
+    reg     int_odt_l_int_r1;
+    reg     int_odt_l_int_r2;
+    
+    reg     premux_odt_h;
+    reg     premux_odt_h_r;
+    reg     int_odt_h_int;
+    reg     int_odt_h_int_r1;
+    reg     int_odt_h_int_r2;
+    
+    reg     int_odt_i_1_int;
+    reg     int_odt_i_2_int;
+    reg     int_odt_i_1_int_r1;
+    reg     int_odt_i_2_int_r1;
+    reg     int_odt_i_1_int_r2;
+    reg     int_odt_i_2_int_r2;
+    
+    wire    int_odt_l;
+    wire    int_odt_h;
+    wire    int_odt_i_1;
+    wire    int_odt_i_2;
+    reg  [3:0]   doing_write_count;
+    reg  [3:0]   doing_read_count;
+    wire         doing_read_count_not_zero;
+    reg          doing_read_count_not_zero_r;
+    wire [3:0]   doing_write_count_limit;
+    wire [3:0]   doing_read_count_limit;
+   
+    reg [CFG_TCL_PIPE_LENGTH        -1:0]   do_read_pipe;
+    reg [CFG_TCL_PIPE_LENGTH        -1:0]   do_burst_chop_pipe;
+
+    //=================================================================================================//
+    //        Define ODT pulse width during READ operation                                             //
+    //=================================================================================================//
+    
+    //ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
+    
+    assign  diff_unreg              = cfg_tcl - cfg_cas_wr_lat;
+    assign  diff_modulo_unreg       = (diff % CFG_ODTPIPE_THRESHOLD); 
+    assign  sel_do_read_pipe_unreg  = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo_not_zero;
+    //assign  diff_modulo_not_zero    = (|diff_modulo);
+    //assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin 
+                    diff                <= 0; 
+                    diff_modulo         <= 0;
+                    sel_do_read_pipe    <= 0;
+                end
+            else
+                begin 
+                    diff                <= diff_unreg; 
+                    diff_modulo         <= diff_modulo_unreg;
+                    sel_do_read_pipe    <= (sel_do_read_pipe_unreg > 0) ? (sel_do_read_pipe_unreg - 1'b1) : 0;
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    diff_modulo_not_zero <= 1'b0;
+                    diff_modulo_one      <= 1'b0;
+                    diff_modulo_two      <= 1'b0;
+                    diff_modulo_three    <= 1'b0;
+                end
+            else
+                begin
+                    diff_modulo_not_zero <= |diff_modulo;
+                    diff_modulo_one      <= (diff_modulo == 1) ? 1'b1 : 1'b0;
+                    diff_modulo_two      <= (diff_modulo == 2) ? 1'b1 : 1'b0;
+                    diff_modulo_three    <= (diff_modulo == 3) ? 1'b1 : 1'b0;
+                end
+        end
+
+    always @ (*) 
+        begin
+            int_do_read              = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read       : do_read_pipe       [sel_do_read_pipe] ;
+            int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
+        end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+        begin
+            if (~ctl_reset_n)
+                begin
+                    int_do_read_burst_chop <= 1'b0;
+                end
+            else
+                begin
+                    if (int_do_read)
+                        begin
+                            int_do_read_burst_chop <= int_do_read_burst_chop_c;
+                        end
+                end
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    do_read_pipe <= 0;
+                end
+            else
+                begin
+                    do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_read};
+                end
+        end
+
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    do_burst_chop_pipe <= 0;
+                end
+            else
+                begin
+                    do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_burst_chop};
+                end
+        end
+    
+    assign doing_read_count_limit    = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
+    assign doing_read_count_not_zero = (|doing_read_count);
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    doing_read_count <= 0;
+                end
+            else
+                begin
+                    if (int_do_read)
+                        begin
+                            doing_read_count <= 1;
+                        end
+                    else if (doing_read_count >= doing_read_count_limit)
+                        begin
+                            doing_read_count <= 0;
+                        end
+                    else if (doing_read_count > 0)
+                        begin
+                            doing_read_count <= doing_read_count + 1'b1;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (~ctl_reset_n)
+                begin
+                    doing_read_count_not_zero_r <= 1'b0;
+                end
+            else
+                begin
+                    doing_read_count_not_zero_r <= doing_read_count_not_zero;
+                end
+        end
+
+    //=================================================================================================//
+    //        Define ODT pulse width during WRITE operation                                            //
+    //=================================================================================================//
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+        begin
+            if (~ctl_reset_n)
+                begin
+                    int_do_write_burst_chop <= 1'b0;
+                end
+            else
+                begin
+                    if (bg_do_write)
+                        begin
+                            int_do_write_burst_chop <= bg_do_burst_chop;
+                        end
+                end
+        end
+
+    assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    doing_write_count <= 0;
+                end
+            else
+                begin
+                    if (bg_do_write)
+                        begin
+                            doing_write_count <= 1;
+                        end
+                    else if (doing_write_count >= doing_write_count_limit)
+                        begin
+                            doing_write_count <= 0;
+                        end
+                    else if (doing_write_count > 0)
+                        begin
+                            doing_write_count <= doing_write_count + 1'b1;
+                        end
+            end
+        end
+    
+    //=================================================================================================//
+    //        ODT signal generation block                                                              //
+    //=================================================================================================//
+    
+    always @ (*)
+        begin
+            if (bg_do_write || int_do_read)
+                begin
+                    premux_odt_h = 1'b1;
+                end
+            else if (doing_write_count > 0 || doing_read_count > 0)
+                begin
+                    premux_odt_h = 1'b1;
+                end
+            else
+                begin
+                    premux_odt_h = 1'b0;
+                end
+        end
+  
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+        begin
+            if (~ctl_reset_n)
+                begin
+                    premux_odt_h_r  <= 1'b0;
+                end
+            else
+                begin
+                    if (int_do_read)
+                        begin
+                            premux_odt_h_r <= 1'b1;
+                        end
+                    else if ((doing_read_count > 1 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 4) || diff_modulo_two)) || (doing_read_count > 0 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 2) || diff_modulo_three)))
+                        begin
+                            premux_odt_h_r <= 1'b1;
+                        end
+                    else
+                        begin
+                            premux_odt_h_r <= 1'b0;
+                        end
+                end
+        end
+
+    always @ (*)
+        begin
+            if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r))
+                begin
+                    int_odt_h_int = premux_odt_h_r;
+                end
+            else // write, read with normal odt
+                begin 
+                    int_odt_h_int = premux_odt_h;
+                end
+        end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    int_odt_l_int <= 1'b0;
+                end
+            else
+                begin
+                    if (bg_do_write || (int_do_read && !diff_modulo_two && !diff_modulo_three))
+                        begin
+                            int_odt_l_int <= 1'b1;
+                        end
+                    else if (doing_write_count > 0 || doing_read_count > 0)
+                        begin
+                            int_odt_l_int <= 1'b1;
+                        end
+                    else
+                        begin
+                            int_odt_l_int <= 1'b0;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    int_odt_i_1_int <= 1'b0;
+                end
+            else
+                begin
+                    if (bg_do_write || int_do_read)
+                        begin
+                            int_odt_i_1_int <= 1'b1;
+                        end
+                    else if (doing_write_count > 1 || (doing_read_count > 1 && !diff_modulo_not_zero) || (doing_read_count > 0 && diff_modulo_not_zero))
+                        begin
+                            int_odt_i_1_int <= 1'b1;
+                        end
+                    else
+                        begin
+                            int_odt_i_1_int <= 1'b0;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    int_odt_i_2_int <= 1'b0;
+                end
+            else
+                begin
+                    if (bg_do_write || int_do_read)
+                        begin
+                            int_odt_i_2_int <= 1'b1;
+                        end
+                    else if (doing_write_count > 1 || (doing_read_count > 1 && (!diff_modulo_not_zero || diff_modulo_one)) || (doing_read_count > 0 && (diff_modulo_two || diff_modulo_three)))
+                        begin
+                            int_odt_i_2_int <= 1'b1;
+                        end
+                    else
+                        begin
+                            int_odt_i_2_int <= 1'b0;
+                        end
+                end
+        end
+    
+    //Generate registered output
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    int_odt_h_int_r1   <= 1'b0;
+                    int_odt_l_int_r1   <= 1'b0;
+                    int_odt_i_1_int_r1 <= 1'b0;
+                    int_odt_i_2_int_r1 <= 1'b0;
+                    
+                    int_odt_h_int_r2   <= 1'b0;
+                    int_odt_l_int_r2   <= 1'b0;
+                    int_odt_i_1_int_r2 <= 1'b0;
+                    int_odt_i_2_int_r2 <= 1'b0;
+                end
+            else
+                begin
+                    int_odt_h_int_r1   <= int_odt_h_int;
+                    int_odt_l_int_r1   <= int_odt_l_int;
+                    int_odt_i_1_int_r1 <= int_odt_i_1_int;
+                    int_odt_i_2_int_r1 <= int_odt_i_2_int;
+                    
+                    int_odt_h_int_r2   <= int_odt_h_int_r1;
+                    int_odt_l_int_r2   <= int_odt_l_int_r1;
+                    int_odt_i_1_int_r2 <= int_odt_i_1_int_r1;
+                    int_odt_i_2_int_r2 <= int_odt_i_2_int_r1;
+                end
+        end
+    
+    generate
+        if (CFG_DWIDTH_RATIO == 2) // full rate
+            begin
+                assign  int_odt_h   = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
+                assign  int_odt_l   = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
+                assign  int_odt_i_1 = 1'b0;
+                assign  int_odt_i_2 = 1'b0;
+            end
+        else if (CFG_DWIDTH_RATIO == 4) // half rate
+            begin
+                assign  int_odt_h   = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
+                assign  int_odt_l   = (cfg_output_regd == 2) ? int_odt_l_int_r2 : ((cfg_output_regd == 1) ? int_odt_l_int_r1 : int_odt_l_int);
+                assign  int_odt_i_1 = 1'b0;
+                assign  int_odt_i_2 = 1'b0;
+            end
+        else if (CFG_DWIDTH_RATIO == 8) // quarter rate
+            begin
+                assign  int_odt_h   = (cfg_output_regd == 2) ? int_odt_h_int_r2   : ((cfg_output_regd == 1) ? int_odt_h_int_r1   : int_odt_h_int  );
+                assign  int_odt_l   = (cfg_output_regd == 2) ? int_odt_l_int_r2   : ((cfg_output_regd == 1) ? int_odt_l_int_r1   : int_odt_l_int  );
+                assign  int_odt_i_1 = (cfg_output_regd == 2) ? int_odt_i_1_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_1_int_r1 : int_odt_i_1_int);
+                assign  int_odt_i_2 = (cfg_output_regd == 2) ? int_odt_i_2_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_2_int_r1 : int_odt_i_2_int);
+            end
+    endgenerate
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
new file mode 100644
index 0000000..8f847c9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
@@ -0,0 +1,41 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] MMR - Memory Mapped Register Definition
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Generic Signals
+    //----------------------------------------------------------------------------------------------------
+    // cfg_type
+    `define MMR_TYPE_DDR1    3'b000
+    `define MMR_TYPE_DDR2    3'b001
+    `define MMR_TYPE_DDR3    3'b010
+    `define MMR_TYPE_LPDDR1  3'b011
+    `define MMR_TYPE_LPDDR2  3'b100
+    
+    //----------------------------------------------------------------------------------------------------
+    // Address Mapping Signals
+    //----------------------------------------------------------------------------------------------------
+    // cfg_addr_order
+    `define MMR_ADDR_ORDER_CS_ROW_BA_COL    2'b00
+    `define MMR_ADDR_ORDER_CS_BA_ROW_COL    2'b01
+    `define MMR_ADDR_ORDER_ROW_CS_BA_COL    2'b10
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] MMR - Memory Mapped Register Definition
+//
+//--------------------------------------------------------------------------------------------------------
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
new file mode 100644
index 0000000..3ef7e6a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
@@ -0,0 +1,427 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//altera message_off 10230 10036
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_ecc_decoder #
+    ( parameter
+        CFG_DATA_WIDTH              =   40,
+        CFG_ECC_CODE_WIDTH          =   8,
+
+        CFG_ECC_DEC_REG             =   1,
+		CFG_ECC_DECODER_REG			=	0,
+        CFG_ECC_RDATA_REG           =   0,
+        
+        CFG_MMR_DRAM_DATA_WIDTH     =   7,
+        CFG_MMR_LOCAL_DATA_WIDTH    =   7,
+        
+        CFG_PORT_WIDTH_ENABLE_ECC   =   1
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        cfg_local_data_width,
+        cfg_dram_data_width,
+        cfg_enable_ecc,
+        
+        input_data,
+        input_data_valid,
+        output_data,
+        output_data_valid,
+        output_ecc_code,
+        
+        err_corrected,
+        err_detected,
+        err_fatal,
+        err_sbe
+    );
+
+localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
+
+input  ctl_clk;
+input  ctl_reset_n;
+
+input  [CFG_MMR_DRAM_DATA_WIDTH   - 1 : 0] cfg_local_data_width;
+input  [CFG_MMR_LOCAL_DATA_WIDTH  - 1 : 0] cfg_dram_data_width;
+input  [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
+
+input  [CFG_DATA_WIDTH     - 1 : 0] input_data;
+input                               input_data_valid;
+
+output [CFG_DATA_WIDTH     - 1 : 0] output_data;
+output                              output_data_valid;
+output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
+
+output                          err_corrected;
+output                          err_detected;
+output                          err_fatal;
+output                          err_sbe;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_decoder_input;
+    
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_decoder_input_data;
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_decoder_input_ecc_code;
+    reg  [CFG_DATA_WIDTH     - 1 : 0] or_int_decoder_input_ecc_code;
+    
+    reg  [CFG_DATA_WIDTH     - 1 : 0] output_data;
+    reg                               output_data_valid;
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
+    
+    reg                               err_corrected;
+    reg                               err_detected;
+    reg                               err_fatal;
+    reg                               err_sbe;
+
+    wire                              int_err_corrected;
+    wire                              int_err_detected;
+    wire                              int_err_fatal;
+    wire                              int_err_sbe;
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
+    
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code;
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r;
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r_r;
+    
+    wire [CFG_DATA_WIDTH     - 1 : 0] decoder_input;
+    wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
+    reg                               decoder_output_valid;
+
+    reg  [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
+    reg                               decoder_output_valid_r;
+	reg								  decoder_output_valid_r_r;
+    reg                               int_err_corrected_r;
+    reg                               int_err_detected_r;
+    reg                               int_err_fatal_r;
+    reg                               int_err_sbe_r;
+    
+    
+    wire zero = 1'b0;
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Common Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    // Input data splitting/masking logic:
+    // change
+    // <Empty data> - <ECC code> - <Data>
+    // into
+    // <ECC code> - <Empty data> - <Data>
+    generate
+        genvar i_data;
+        for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
+        begin : decoder_input_per_data_width
+            always @ (*)
+            begin
+                int_decoder_input_data [i_data] = input_data [i_data];
+            end
+        end
+    endgenerate
+    
+    generate
+        if (CFG_ECC_RDATA_REG)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_decoder_input <= 0;
+                end
+                else
+                begin
+                    int_decoder_input <= int_decoder_input_data;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    decoder_output_valid    <= 0;
+                    decoder_output_ecc_code <= 0;
+                end
+                else
+                begin
+                    decoder_output_valid    <= input_data_valid;
+                    decoder_output_ecc_code <= int_output_ecc_code;
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                int_decoder_input = int_decoder_input_data;
+            end
+            
+            always @ (*)
+            begin
+                decoder_output_valid    = input_data_valid;
+                decoder_output_ecc_code = int_output_ecc_code;
+            end
+        end
+    endgenerate
+    
+    // Decoder input assignment
+    assign decoder_input = int_decoder_input;
+    
+    
+
+    // Decoder output, registered
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            decoder_output_r            <= {CFG_ECC_DATA_WIDTH{1'b0}};
+            decoder_output_valid_r      <= 1'b0;
+			decoder_output_valid_r_r    <= 1'b0;
+            int_err_corrected_r         <= 1'b0;
+            int_err_detected_r          <= 1'b0;
+            int_err_fatal_r             <= 1'b0;
+            int_err_sbe_r               <= 1'b0;
+            decoder_output_ecc_code_r   <= {CFG_ECC_CODE_WIDTH{1'b0}};
+            decoder_output_ecc_code_r_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
+        end
+        else
+        begin
+            decoder_output_r            <= decoder_output;
+            decoder_output_valid_r      <= decoder_output_valid;
+			decoder_output_valid_r_r    <= decoder_output_valid_r;
+            int_err_corrected_r         <= int_err_corrected;
+            int_err_detected_r          <= int_err_detected;
+            int_err_fatal_r             <= int_err_fatal;
+            int_err_sbe_r               <= int_err_sbe;
+            decoder_output_ecc_code_r   <= decoder_output_ecc_code;
+            decoder_output_ecc_code_r_r <= decoder_output_ecc_code_r;
+        end
+    end
+    
+    // Decoder output ecc code
+    generate
+        if (CFG_DATA_WIDTH <= 8)
+        begin
+            // No support for ECC case
+            always @ (*)
+            begin
+                int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                if (cfg_enable_ecc)
+                    int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
+                else
+                    int_output_ecc_code = 0;
+            end
+        end
+    endgenerate
+
+    // Decoder wrapper output assignment
+    generate
+    begin : gen_decoder_output_reg_select
+        if (CFG_ECC_DEC_REG)
+        begin
+            always @ (*)
+            begin
+                if (cfg_enable_ecc)
+                begin
+                    output_data         = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r};     // Assign '0' to ECC code portions
+                    output_data_valid   = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r_r : decoder_output_valid_r;
+                    err_corrected       = int_err_corrected_r;
+                    err_detected        = int_err_detected_r;
+                    err_fatal           = int_err_fatal_r;
+                    err_sbe             = int_err_sbe_r;
+                    output_ecc_code     = (CFG_ECC_DECODER_REG == 1) ? decoder_output_ecc_code_r_r : decoder_output_ecc_code_r;
+                end
+                else
+                begin
+                    output_data         = input_data;
+                    output_data_valid   = input_data_valid;
+                    err_corrected       = 1'b0;
+                    err_detected        = 1'b0;
+                    err_fatal           = 1'b0;
+                    err_sbe             = 1'b0;
+                    output_ecc_code     = decoder_output_ecc_code;
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                if (cfg_enable_ecc)
+                begin
+                    output_data         = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output};     // Assign '0' to ECC code portions
+                    output_data_valid   = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r : decoder_output_valid;
+                    err_corrected       = int_err_corrected;
+                    err_detected        = int_err_detected;
+                    err_fatal           = int_err_fatal;
+                    err_sbe             = int_err_sbe;
+                    output_ecc_code     = decoder_output_ecc_code;
+                end
+                else
+                begin
+                    output_data         = input_data;
+                    output_data_valid   = input_data_valid;
+                    err_corrected       = 1'b0;
+                    err_detected        = 1'b0;
+                    err_fatal           = 1'b0;
+                    err_sbe             = 1'b0;
+                    output_ecc_code     = decoder_output_ecc_code;
+                end
+            end
+        end
+    end
+    endgenerate
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Common Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+    
+    generate
+    begin
+        if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
+        begin
+            wire [39 : 0] internal_decoder_input;
+            wire [31 : 0] internal_decoder_output;
+            
+            // Assign decoder output
+            assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
+            
+            // Assign decoder output
+            assign decoder_output    = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
+            
+            // 32/39 bit decoder instantiation
+            alt_mem_ddrx_ecc_decoder_32 
+				# (
+					.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+				)
+			decoder_inst
+                (
+					.clk		   (ctl_clk						   ),
+					.reset_n	   (ctl_reset_n					   ),
+            	    .data          (internal_decoder_input [38 : 0]),
+            	    .err_corrected (int_err_corrected              ),
+            	    .err_detected  (int_err_detected               ),
+            	    .err_fatal     (int_err_fatal                  ),
+                    .err_sbe       (int_err_sbe                    ),
+            	    .q             (internal_decoder_output        )
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 16)
+        begin
+            wire [39 : 0] internal_decoder_input;
+            wire [31 : 0] internal_decoder_output;
+            
+            // Assign decoder output
+            assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
+            
+            // Assign decoder output
+            assign decoder_output    = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
+            
+            // 32/39 bit decoder instantiation
+            alt_mem_ddrx_ecc_decoder_32
+				# (
+					.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+				)			
+			decoder_inst
+                (
+					.clk		   (ctl_clk						   ),
+					.reset_n	   (ctl_reset_n					   ),
+            	    .data          (internal_decoder_input [38 : 0]),
+            	    .err_corrected (int_err_corrected              ),
+            	    .err_detected  (int_err_detected               ),
+            	    .err_fatal     (int_err_fatal                  ),
+                    .err_sbe       (int_err_sbe                    ),
+            	    .q             (internal_decoder_output        )
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 32)
+        begin
+            // 32/39 bit decoder instantiation
+            alt_mem_ddrx_ecc_decoder_32
+				# (
+					.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+				)			
+			decoder_inst
+                (
+					.clk		   (ctl_clk				  ),
+					.reset_n	   (ctl_reset_n			  ),
+            	    .data          (decoder_input [38 : 0]),
+            	    .err_corrected (int_err_corrected     ),
+            	    .err_detected  (int_err_detected      ),
+            	    .err_fatal     (int_err_fatal         ),
+                    .err_sbe       (int_err_sbe           ),
+            	    .q             (decoder_output        )
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 64)
+        begin
+            // 32/39 bit decoder instantiation
+            alt_mem_ddrx_ecc_decoder_64
+				# (
+					.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+				)			
+			decoder_inst
+                (
+					.clk		   (ctl_clk			 ),
+					.reset_n	   (ctl_reset_n	     ),
+            	    .data          (decoder_input    ),
+            	    .err_corrected (int_err_corrected),
+            	    .err_detected  (int_err_detected ),
+            	    .err_fatal     (int_err_fatal    ),
+                    .err_sbe       (int_err_sbe      ),
+            	    .q             (decoder_output   )
+                );
+        end
+        else
+        begin
+        	assign int_err_corrected	= 1'b0;
+        	assign int_err_detected		= 1'b0;
+        	assign int_err_fatal 		= 1'b0;
+        	assign int_err_sbe 			= 1'b0;
+        	assign decoder_output		= {CFG_ECC_DATA_WIDTH{1'b0}};
+        end	        
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
new file mode 100644
index 0000000..9605e79
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
@@ -0,0 +1,496 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTECC%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altecc_decoder 
+
+// ============================================================
+// File Name: alt_mem_ddrx_ecc_decoder_32.v
+// Megafunction Name(s):
+// 			altecc_decoder
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data err_corrected err_detected err_fatal q
+//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:07:26:21:21:15:PN cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=64 LPM_WIDTH=6 data eq
+//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN  VERSION_END
+
+//synthesis_resources = lut 72 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_decoder_32_decode
+	( 
+	data,
+	eq) /* synthesis synthesis_clearbox=1 */;
+	input   [5:0]  data;
+	output   [63:0]  eq;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [5:0]  data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [5:0]  data_wire;
+	wire  [63:0]  eq_node;
+	wire  [63:0]  eq_wire;
+	wire  [3:0]  w_anode1000w;
+	wire  [3:0]  w_anode1010w;
+	wire  [3:0]  w_anode1020w;
+	wire  [3:0]  w_anode1030w;
+	wire  [3:0]  w_anode1041w;
+	wire  [3:0]  w_anode1053w;
+	wire  [3:0]  w_anode1064w;
+	wire  [3:0]  w_anode1074w;
+	wire  [3:0]  w_anode1084w;
+	wire  [3:0]  w_anode1094w;
+	wire  [3:0]  w_anode1104w;
+	wire  [3:0]  w_anode1114w;
+	wire  [3:0]  w_anode1124w;
+	wire  [3:0]  w_anode1135w;
+	wire  [3:0]  w_anode1147w;
+	wire  [3:0]  w_anode1158w;
+	wire  [3:0]  w_anode1168w;
+	wire  [3:0]  w_anode1178w;
+	wire  [3:0]  w_anode1188w;
+	wire  [3:0]  w_anode1198w;
+	wire  [3:0]  w_anode1208w;
+	wire  [3:0]  w_anode1218w;
+	wire  [3:0]  w_anode464w;
+	wire  [3:0]  w_anode482w;
+	wire  [3:0]  w_anode499w;
+	wire  [3:0]  w_anode509w;
+	wire  [3:0]  w_anode519w;
+	wire  [3:0]  w_anode529w;
+	wire  [3:0]  w_anode539w;
+	wire  [3:0]  w_anode549w;
+	wire  [3:0]  w_anode559w;
+	wire  [3:0]  w_anode571w;
+	wire  [3:0]  w_anode583w;
+	wire  [3:0]  w_anode594w;
+	wire  [3:0]  w_anode604w;
+	wire  [3:0]  w_anode614w;
+	wire  [3:0]  w_anode624w;
+	wire  [3:0]  w_anode634w;
+	wire  [3:0]  w_anode644w;
+	wire  [3:0]  w_anode654w;
+	wire  [3:0]  w_anode665w;
+	wire  [3:0]  w_anode677w;
+	wire  [3:0]  w_anode688w;
+	wire  [3:0]  w_anode698w;
+	wire  [3:0]  w_anode708w;
+	wire  [3:0]  w_anode718w;
+	wire  [3:0]  w_anode728w;
+	wire  [3:0]  w_anode738w;
+	wire  [3:0]  w_anode748w;
+	wire  [3:0]  w_anode759w;
+	wire  [3:0]  w_anode771w;
+	wire  [3:0]  w_anode782w;
+	wire  [3:0]  w_anode792w;
+	wire  [3:0]  w_anode802w;
+	wire  [3:0]  w_anode812w;
+	wire  [3:0]  w_anode822w;
+	wire  [3:0]  w_anode832w;
+	wire  [3:0]  w_anode842w;
+	wire  [3:0]  w_anode853w;
+	wire  [3:0]  w_anode865w;
+	wire  [3:0]  w_anode876w;
+	wire  [3:0]  w_anode886w;
+	wire  [3:0]  w_anode896w;
+	wire  [3:0]  w_anode906w;
+	wire  [3:0]  w_anode916w;
+	wire  [3:0]  w_anode926w;
+	wire  [3:0]  w_anode936w;
+	wire  [3:0]  w_anode947w;
+	wire  [3:0]  w_anode959w;
+	wire  [3:0]  w_anode970w;
+	wire  [3:0]  w_anode980w;
+	wire  [3:0]  w_anode990w;
+	wire  [2:0]  w_data462w;
+
+	assign
+		data_wire = data,
+		eq = eq_node,
+		eq_node = eq_wire[63:0],
+		eq_wire = {{w_anode1218w[3], w_anode1208w[3], w_anode1198w[3], w_anode1188w[3], w_anode1178w[3], w_anode1168w[3], w_anode1158w[3], w_anode1147w[3]}, {w_anode1124w[3], w_anode1114w[3], w_anode1104w[3], w_anode1094w[3], w_anode1084w[3], w_anode1074w[3], w_anode1064w[3], w_anode1053w[3]}, {w_anode1030w[3], w_anode1020w[3], w_anode1010w[3], w_anode1000w[3], w_anode990w[3], w_anode980w[3], w_anode970w[3], w_anode959w[3]}, {w_anode936w[3], w_anode926w[3], w_anode916w[3], w_anode906w[3], w_anode896w[3], w_anode886w[3], w_anode876w[3], w_anode865w[3]}, {w_anode842w[3], w_anode832w[3], w_anode822w[3], w_anode812w[3], w_anode802w[3], w_anode792w[3], w_anode782w[3], w_anode771w[3]}, {w_anode748w[3], w_anode738w[3], w_anode728w[3], w_anode718w[3], w_anode708w[3], w_anode698w[3], w_anode688w[3], w_anode677w[3]}, {w_anode654w[3], w_anode644w[3], w_anode634w[3], w_anode624w[3], w_anode614w[3], w_anode604w[3], w_anode594w[3], w_anode583w[3]}, {w_anode559w[3], w_anode549w[3], w_anode539w[3], w_anode529w[3], w_anode519w[3], w_anode509w[3], w_anode499w[3], w_anode482w[3]}},
+		w_anode1000w = {(w_anode1000w[2] & w_data462w[2]), (w_anode1000w[1] & (~ w_data462w[1])), (w_anode1000w[0] & (~ w_data462w[0])), w_anode947w[3]},
+		w_anode1010w = {(w_anode1010w[2] & w_data462w[2]), (w_anode1010w[1] & (~ w_data462w[1])), (w_anode1010w[0] & w_data462w[0]), w_anode947w[3]},
+		w_anode1020w = {(w_anode1020w[2] & w_data462w[2]), (w_anode1020w[1] & w_data462w[1]), (w_anode1020w[0] & (~ w_data462w[0])), w_anode947w[3]},
+		w_anode1030w = {(w_anode1030w[2] & w_data462w[2]), (w_anode1030w[1] & w_data462w[1]), (w_anode1030w[0] & w_data462w[0]), w_anode947w[3]},
+		w_anode1041w = {(w_anode1041w[2] & data_wire[5]), (w_anode1041w[1] & data_wire[4]), (w_anode1041w[0] & (~ data_wire[3])), 1'b1},
+		w_anode1053w = {(w_anode1053w[2] & (~ w_data462w[2])), (w_anode1053w[1] & (~ w_data462w[1])), (w_anode1053w[0] & (~ w_data462w[0])), w_anode1041w[3]},
+		w_anode1064w = {(w_anode1064w[2] & (~ w_data462w[2])), (w_anode1064w[1] & (~ w_data462w[1])), (w_anode1064w[0] & w_data462w[0]), w_anode1041w[3]},
+		w_anode1074w = {(w_anode1074w[2] & (~ w_data462w[2])), (w_anode1074w[1] & w_data462w[1]), (w_anode1074w[0] & (~ w_data462w[0])), w_anode1041w[3]},
+		w_anode1084w = {(w_anode1084w[2] & (~ w_data462w[2])), (w_anode1084w[1] & w_data462w[1]), (w_anode1084w[0] & w_data462w[0]), w_anode1041w[3]},
+		w_anode1094w = {(w_anode1094w[2] & w_data462w[2]), (w_anode1094w[1] & (~ w_data462w[1])), (w_anode1094w[0] & (~ w_data462w[0])), w_anode1041w[3]},
+		w_anode1104w = {(w_anode1104w[2] & w_data462w[2]), (w_anode1104w[1] & (~ w_data462w[1])), (w_anode1104w[0] & w_data462w[0]), w_anode1041w[3]},
+		w_anode1114w = {(w_anode1114w[2] & w_data462w[2]), (w_anode1114w[1] & w_data462w[1]), (w_anode1114w[0] & (~ w_data462w[0])), w_anode1041w[3]},
+		w_anode1124w = {(w_anode1124w[2] & w_data462w[2]), (w_anode1124w[1] & w_data462w[1]), (w_anode1124w[0] & w_data462w[0]), w_anode1041w[3]},
+		w_anode1135w = {(w_anode1135w[2] & data_wire[5]), (w_anode1135w[1] & data_wire[4]), (w_anode1135w[0] & data_wire[3]), 1'b1},
+		w_anode1147w = {(w_anode1147w[2] & (~ w_data462w[2])), (w_anode1147w[1] & (~ w_data462w[1])), (w_anode1147w[0] & (~ w_data462w[0])), w_anode1135w[3]},
+		w_anode1158w = {(w_anode1158w[2] & (~ w_data462w[2])), (w_anode1158w[1] & (~ w_data462w[1])), (w_anode1158w[0] & w_data462w[0]), w_anode1135w[3]},
+		w_anode1168w = {(w_anode1168w[2] & (~ w_data462w[2])), (w_anode1168w[1] & w_data462w[1]), (w_anode1168w[0] & (~ w_data462w[0])), w_anode1135w[3]},
+		w_anode1178w = {(w_anode1178w[2] & (~ w_data462w[2])), (w_anode1178w[1] & w_data462w[1]), (w_anode1178w[0] & w_data462w[0]), w_anode1135w[3]},
+		w_anode1188w = {(w_anode1188w[2] & w_data462w[2]), (w_anode1188w[1] & (~ w_data462w[1])), (w_anode1188w[0] & (~ w_data462w[0])), w_anode1135w[3]},
+		w_anode1198w = {(w_anode1198w[2] & w_data462w[2]), (w_anode1198w[1] & (~ w_data462w[1])), (w_anode1198w[0] & w_data462w[0]), w_anode1135w[3]},
+		w_anode1208w = {(w_anode1208w[2] & w_data462w[2]), (w_anode1208w[1] & w_data462w[1]), (w_anode1208w[0] & (~ w_data462w[0])), w_anode1135w[3]},
+		w_anode1218w = {(w_anode1218w[2] & w_data462w[2]), (w_anode1218w[1] & w_data462w[1]), (w_anode1218w[0] & w_data462w[0]), w_anode1135w[3]},
+		w_anode464w = {(w_anode464w[2] & (~ data_wire[5])), (w_anode464w[1] & (~ data_wire[4])), (w_anode464w[0] & (~ data_wire[3])), 1'b1},
+		w_anode482w = {(w_anode482w[2] & (~ w_data462w[2])), (w_anode482w[1] & (~ w_data462w[1])), (w_anode482w[0] & (~ w_data462w[0])), w_anode464w[3]},
+		w_anode499w = {(w_anode499w[2] & (~ w_data462w[2])), (w_anode499w[1] & (~ w_data462w[1])), (w_anode499w[0] & w_data462w[0]), w_anode464w[3]},
+		w_anode509w = {(w_anode509w[2] & (~ w_data462w[2])), (w_anode509w[1] & w_data462w[1]), (w_anode509w[0] & (~ w_data462w[0])), w_anode464w[3]},
+		w_anode519w = {(w_anode519w[2] & (~ w_data462w[2])), (w_anode519w[1] & w_data462w[1]), (w_anode519w[0] & w_data462w[0]), w_anode464w[3]},
+		w_anode529w = {(w_anode529w[2] & w_data462w[2]), (w_anode529w[1] & (~ w_data462w[1])), (w_anode529w[0] & (~ w_data462w[0])), w_anode464w[3]},
+		w_anode539w = {(w_anode539w[2] & w_data462w[2]), (w_anode539w[1] & (~ w_data462w[1])), (w_anode539w[0] & w_data462w[0]), w_anode464w[3]},
+		w_anode549w = {(w_anode549w[2] & w_data462w[2]), (w_anode549w[1] & w_data462w[1]), (w_anode549w[0] & (~ w_data462w[0])), w_anode464w[3]},
+		w_anode559w = {(w_anode559w[2] & w_data462w[2]), (w_anode559w[1] & w_data462w[1]), (w_anode559w[0] & w_data462w[0]), w_anode464w[3]},
+		w_anode571w = {(w_anode571w[2] & (~ data_wire[5])), (w_anode571w[1] & (~ data_wire[4])), (w_anode571w[0] & data_wire[3]), 1'b1},
+		w_anode583w = {(w_anode583w[2] & (~ w_data462w[2])), (w_anode583w[1] & (~ w_data462w[1])), (w_anode583w[0] & (~ w_data462w[0])), w_anode571w[3]},
+		w_anode594w = {(w_anode594w[2] & (~ w_data462w[2])), (w_anode594w[1] & (~ w_data462w[1])), (w_anode594w[0] & w_data462w[0]), w_anode571w[3]},
+		w_anode604w = {(w_anode604w[2] & (~ w_data462w[2])), (w_anode604w[1] & w_data462w[1]), (w_anode604w[0] & (~ w_data462w[0])), w_anode571w[3]},
+		w_anode614w = {(w_anode614w[2] & (~ w_data462w[2])), (w_anode614w[1] & w_data462w[1]), (w_anode614w[0] & w_data462w[0]), w_anode571w[3]},
+		w_anode624w = {(w_anode624w[2] & w_data462w[2]), (w_anode624w[1] & (~ w_data462w[1])), (w_anode624w[0] & (~ w_data462w[0])), w_anode571w[3]},
+		w_anode634w = {(w_anode634w[2] & w_data462w[2]), (w_anode634w[1] & (~ w_data462w[1])), (w_anode634w[0] & w_data462w[0]), w_anode571w[3]},
+		w_anode644w = {(w_anode644w[2] & w_data462w[2]), (w_anode644w[1] & w_data462w[1]), (w_anode644w[0] & (~ w_data462w[0])), w_anode571w[3]},
+		w_anode654w = {(w_anode654w[2] & w_data462w[2]), (w_anode654w[1] & w_data462w[1]), (w_anode654w[0] & w_data462w[0]), w_anode571w[3]},
+		w_anode665w = {(w_anode665w[2] & (~ data_wire[5])), (w_anode665w[1] & data_wire[4]), (w_anode665w[0] & (~ data_wire[3])), 1'b1},
+		w_anode677w = {(w_anode677w[2] & (~ w_data462w[2])), (w_anode677w[1] & (~ w_data462w[1])), (w_anode677w[0] & (~ w_data462w[0])), w_anode665w[3]},
+		w_anode688w = {(w_anode688w[2] & (~ w_data462w[2])), (w_anode688w[1] & (~ w_data462w[1])), (w_anode688w[0] & w_data462w[0]), w_anode665w[3]},
+		w_anode698w = {(w_anode698w[2] & (~ w_data462w[2])), (w_anode698w[1] & w_data462w[1]), (w_anode698w[0] & (~ w_data462w[0])), w_anode665w[3]},
+		w_anode708w = {(w_anode708w[2] & (~ w_data462w[2])), (w_anode708w[1] & w_data462w[1]), (w_anode708w[0] & w_data462w[0]), w_anode665w[3]},
+		w_anode718w = {(w_anode718w[2] & w_data462w[2]), (w_anode718w[1] & (~ w_data462w[1])), (w_anode718w[0] & (~ w_data462w[0])), w_anode665w[3]},
+		w_anode728w = {(w_anode728w[2] & w_data462w[2]), (w_anode728w[1] & (~ w_data462w[1])), (w_anode728w[0] & w_data462w[0]), w_anode665w[3]},
+		w_anode738w = {(w_anode738w[2] & w_data462w[2]), (w_anode738w[1] & w_data462w[1]), (w_anode738w[0] & (~ w_data462w[0])), w_anode665w[3]},
+		w_anode748w = {(w_anode748w[2] & w_data462w[2]), (w_anode748w[1] & w_data462w[1]), (w_anode748w[0] & w_data462w[0]), w_anode665w[3]},
+		w_anode759w = {(w_anode759w[2] & (~ data_wire[5])), (w_anode759w[1] & data_wire[4]), (w_anode759w[0] & data_wire[3]), 1'b1},
+		w_anode771w = {(w_anode771w[2] & (~ w_data462w[2])), (w_anode771w[1] & (~ w_data462w[1])), (w_anode771w[0] & (~ w_data462w[0])), w_anode759w[3]},
+		w_anode782w = {(w_anode782w[2] & (~ w_data462w[2])), (w_anode782w[1] & (~ w_data462w[1])), (w_anode782w[0] & w_data462w[0]), w_anode759w[3]},
+		w_anode792w = {(w_anode792w[2] & (~ w_data462w[2])), (w_anode792w[1] & w_data462w[1]), (w_anode792w[0] & (~ w_data462w[0])), w_anode759w[3]},
+		w_anode802w = {(w_anode802w[2] & (~ w_data462w[2])), (w_anode802w[1] & w_data462w[1]), (w_anode802w[0] & w_data462w[0]), w_anode759w[3]},
+		w_anode812w = {(w_anode812w[2] & w_data462w[2]), (w_anode812w[1] & (~ w_data462w[1])), (w_anode812w[0] & (~ w_data462w[0])), w_anode759w[3]},
+		w_anode822w = {(w_anode822w[2] & w_data462w[2]), (w_anode822w[1] & (~ w_data462w[1])), (w_anode822w[0] & w_data462w[0]), w_anode759w[3]},
+		w_anode832w = {(w_anode832w[2] & w_data462w[2]), (w_anode832w[1] & w_data462w[1]), (w_anode832w[0] & (~ w_data462w[0])), w_anode759w[3]},
+		w_anode842w = {(w_anode842w[2] & w_data462w[2]), (w_anode842w[1] & w_data462w[1]), (w_anode842w[0] & w_data462w[0]), w_anode759w[3]},
+		w_anode853w = {(w_anode853w[2] & data_wire[5]), (w_anode853w[1] & (~ data_wire[4])), (w_anode853w[0] & (~ data_wire[3])), 1'b1},
+		w_anode865w = {(w_anode865w[2] & (~ w_data462w[2])), (w_anode865w[1] & (~ w_data462w[1])), (w_anode865w[0] & (~ w_data462w[0])), w_anode853w[3]},
+		w_anode876w = {(w_anode876w[2] & (~ w_data462w[2])), (w_anode876w[1] & (~ w_data462w[1])), (w_anode876w[0] & w_data462w[0]), w_anode853w[3]},
+		w_anode886w = {(w_anode886w[2] & (~ w_data462w[2])), (w_anode886w[1] & w_data462w[1]), (w_anode886w[0] & (~ w_data462w[0])), w_anode853w[3]},
+		w_anode896w = {(w_anode896w[2] & (~ w_data462w[2])), (w_anode896w[1] & w_data462w[1]), (w_anode896w[0] & w_data462w[0]), w_anode853w[3]},
+		w_anode906w = {(w_anode906w[2] & w_data462w[2]), (w_anode906w[1] & (~ w_data462w[1])), (w_anode906w[0] & (~ w_data462w[0])), w_anode853w[3]},
+		w_anode916w = {(w_anode916w[2] & w_data462w[2]), (w_anode916w[1] & (~ w_data462w[1])), (w_anode916w[0] & w_data462w[0]), w_anode853w[3]},
+		w_anode926w = {(w_anode926w[2] & w_data462w[2]), (w_anode926w[1] & w_data462w[1]), (w_anode926w[0] & (~ w_data462w[0])), w_anode853w[3]},
+		w_anode936w = {(w_anode936w[2] & w_data462w[2]), (w_anode936w[1] & w_data462w[1]), (w_anode936w[0] & w_data462w[0]), w_anode853w[3]},
+		w_anode947w = {(w_anode947w[2] & data_wire[5]), (w_anode947w[1] & (~ data_wire[4])), (w_anode947w[0] & data_wire[3]), 1'b1},
+		w_anode959w = {(w_anode959w[2] & (~ w_data462w[2])), (w_anode959w[1] & (~ w_data462w[1])), (w_anode959w[0] & (~ w_data462w[0])), w_anode947w[3]},
+		w_anode970w = {(w_anode970w[2] & (~ w_data462w[2])), (w_anode970w[1] & (~ w_data462w[1])), (w_anode970w[0] & w_data462w[0]), w_anode947w[3]},
+		w_anode980w = {(w_anode980w[2] & (~ w_data462w[2])), (w_anode980w[1] & w_data462w[1]), (w_anode980w[0] & (~ w_data462w[0])), w_anode947w[3]},
+		w_anode990w = {(w_anode990w[2] & (~ w_data462w[2])), (w_anode990w[1] & w_data462w[1]), (w_anode990w[0] & w_data462w[0]), w_anode947w[3]},
+		w_data462w = data_wire[2:0];
+endmodule //alt_mem_ddrx_ecc_decoder_32_decode
+
+//synthesis_resources = lut 72 mux21 32 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_decoder_32_altecc_decoder
+	(
+	clk,
+	reset_n,
+	data,
+	err_corrected,
+	err_detected,
+	err_fatal,
+	err_sbe,
+	q) /* synthesis synthesis_clearbox=1 */;
+	
+	parameter CFG_ECC_DECODER_REG = 0;
+	
+	input			clk;
+	input			reset_n;
+	input   [38:0]  data;
+	output   err_corrected;
+	output   err_detected;
+	output   err_fatal;
+	output   err_sbe;
+	output   [31:0]  q;
+
+	wire  [63:0]   wire_error_bit_decoder_eq;
+	wire	wire_mux21_0_dataout;
+	wire	wire_mux21_1_dataout;
+	wire	wire_mux21_10_dataout;
+	wire	wire_mux21_11_dataout;
+	wire	wire_mux21_12_dataout;
+	wire	wire_mux21_13_dataout;
+	wire	wire_mux21_14_dataout;
+	wire	wire_mux21_15_dataout;
+	wire	wire_mux21_16_dataout;
+	wire	wire_mux21_17_dataout;
+	wire	wire_mux21_18_dataout;
+	wire	wire_mux21_19_dataout;
+	wire	wire_mux21_2_dataout;
+	wire	wire_mux21_20_dataout;
+	wire	wire_mux21_21_dataout;
+	wire	wire_mux21_22_dataout;
+	wire	wire_mux21_23_dataout;
+	wire	wire_mux21_24_dataout;
+	wire	wire_mux21_25_dataout;
+	wire	wire_mux21_26_dataout;
+	wire	wire_mux21_27_dataout;
+	wire	wire_mux21_28_dataout;
+	wire	wire_mux21_29_dataout;
+	wire	wire_mux21_3_dataout;
+	wire	wire_mux21_30_dataout;
+	wire	wire_mux21_31_dataout;
+	wire	wire_mux21_4_dataout;
+	wire	wire_mux21_5_dataout;
+	wire	wire_mux21_6_dataout;
+	wire	wire_mux21_7_dataout;
+	wire	wire_mux21_8_dataout;
+	wire	wire_mux21_9_dataout;
+	wire  data_bit;
+	wire  [31:0]  data_t;
+	wire  [38:0]  data_wire;
+	wire  [63:0]  decode_output;
+	wire  err_corrected_wire;
+	wire  err_detected_wire;
+	wire  err_fatal_wire;
+	wire  [18:0]  parity_01_wire;
+	wire  [9:0]  parity_02_wire;
+	wire  [4:0]  parity_03_wire;
+	wire  [1:0]  parity_04_wire;
+	wire  [0:0]  parity_05_wire;
+	wire  [5:0]  parity_06_wire;
+	wire  parity_bit;
+	wire  [37:0]  parity_final_wire;
+	wire  [5:0]  parity_t;
+	wire  [31:0]  q_wire;
+	wire  syn_bit;
+	wire  syn_e;
+	wire  [4:0]  syn_t;
+	wire  [6:0]  syndrome_wire;
+	reg   [6:0]  syndrome;
+	reg	  [38:0] data_reg;
+	
+	generate
+		if (CFG_ECC_DECODER_REG == 1)
+		begin
+			always @ (posedge clk or negedge reset_n)
+			begin
+				if (!reset_n)
+				begin
+					syndrome	<= {7{1'b0}};
+					data_reg	<= {39{1'b0}};
+				end else
+				begin
+					syndrome	<= syndrome_wire;
+					data_reg	<= data_wire;
+				end
+			end	
+		end else
+		begin
+			always @ (*)
+			begin
+				syndrome	= syndrome_wire;
+				data_reg	= data_wire;				
+			end
+		end
+	endgenerate
+	
+	alt_mem_ddrx_ecc_decoder_32_decode   error_bit_decoder
+	( 
+	.data(syndrome[5:0]),
+	.eq(wire_error_bit_decoder_eq));
+	assign		wire_mux21_0_dataout = (syndrome[6] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
+	assign		wire_mux21_1_dataout = (syndrome[6] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
+	assign		wire_mux21_10_dataout = (syndrome[6] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
+	assign		wire_mux21_11_dataout = (syndrome[6] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
+	assign		wire_mux21_12_dataout = (syndrome[6] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
+	assign		wire_mux21_13_dataout = (syndrome[6] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
+	assign		wire_mux21_14_dataout = (syndrome[6] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
+	assign		wire_mux21_15_dataout = (syndrome[6] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
+	assign		wire_mux21_16_dataout = (syndrome[6] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
+	assign		wire_mux21_17_dataout = (syndrome[6] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
+	assign		wire_mux21_18_dataout = (syndrome[6] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
+	assign		wire_mux21_19_dataout = (syndrome[6] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
+	assign		wire_mux21_2_dataout = (syndrome[6] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
+	assign		wire_mux21_20_dataout = (syndrome[6] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
+	assign		wire_mux21_21_dataout = (syndrome[6] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
+	assign		wire_mux21_22_dataout = (syndrome[6] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
+	assign		wire_mux21_23_dataout = (syndrome[6] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
+	assign		wire_mux21_24_dataout = (syndrome[6] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
+	assign		wire_mux21_25_dataout = (syndrome[6] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
+	assign		wire_mux21_26_dataout = (syndrome[6] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
+	assign		wire_mux21_27_dataout = (syndrome[6] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
+	assign		wire_mux21_28_dataout = (syndrome[6] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
+	assign		wire_mux21_29_dataout = (syndrome[6] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
+	assign		wire_mux21_3_dataout = (syndrome[6] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
+	assign		wire_mux21_30_dataout = (syndrome[6] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
+	assign		wire_mux21_31_dataout = (syndrome[6] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
+	assign		wire_mux21_4_dataout = (syndrome[6] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
+	assign		wire_mux21_5_dataout = (syndrome[6] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
+	assign		wire_mux21_6_dataout = (syndrome[6] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
+	assign		wire_mux21_7_dataout = (syndrome[6] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
+	assign		wire_mux21_8_dataout = (syndrome[6] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
+	assign		wire_mux21_9_dataout = (syndrome[6] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
+	assign
+		data_bit = data_t[31],
+		data_t = {(data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2] | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
+		data_wire = data,
+		decode_output = wire_error_bit_decoder_eq,
+		err_corrected = err_corrected_wire,
+		err_corrected_wire = ((syn_bit & syn_e) & data_bit),
+		err_detected = err_detected_wire,
+		err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
+		err_fatal = err_fatal_wire,
+		err_sbe = syn_e,
+		err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
+		parity_01_wire = {(data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[32]},
+		parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[33] ^ data_wire[0])},
+		parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[34] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
+		parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[35] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
+		parity_05_wire = {(((((((((((((((data_wire[36] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
+		parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[37] ^ data_wire[26])},
+		parity_bit = parity_t[5],
+		parity_final_wire = {(data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^ parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[38] ^ data_wire[0])},
+		parity_t = {(parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
+		q = q_wire,
+		q_wire = {wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
+		syn_bit = syn_t[4],
+		syn_e = syndrome[6],
+		syn_t = {(syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
+		syndrome_wire = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[18]};
+endmodule //alt_mem_ddrx_ecc_decoder_32_altecc_decoder
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module alt_mem_ddrx_ecc_decoder_32
+# (
+	parameter
+		CFG_ECC_DECODER_REG = 1
+) 
+(
+	clk,
+	reset_n,
+	data,
+	err_corrected,
+	err_detected,
+	err_fatal,
+    err_sbe,
+	q)/* synthesis synthesis_clearbox = 1 */;
+	
+	input			clk;
+	input			reset_n;
+	input	[38:0]  data;
+	output	  err_corrected;
+	output	  err_detected;
+	output	  err_fatal;
+	output	  err_sbe;
+	output	[31:0]  q;
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire  sub_wire4;
+	wire [31:0] sub_wire3;
+	wire  err_detected = sub_wire0;
+	wire  err_fatal = sub_wire1;
+	wire  err_corrected = sub_wire2;
+	wire  err_sbe = sub_wire4;
+	wire [31:0] q = sub_wire3[31:0];
+
+	alt_mem_ddrx_ecc_decoder_32_altecc_decoder	
+	# (
+		.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+	)
+	alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component (
+				.clk (clk),
+				.reset_n (reset_n),
+				.data (data),
+				.err_detected (sub_wire0),
+				.err_fatal (sub_wire1),
+				.err_corrected (sub_wire2),
+				.err_sbe (sub_wire4),
+				.q (sub_wire3));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
+// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
+// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
+// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL "data[38..0]"
+// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
+// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
+// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
+// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
+// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
+// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
new file mode 100644
index 0000000..cdf4946
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
@@ -0,0 +1,721 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTECC%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altecc_decoder 
+
+// ============================================================
+// File Name: alt_mem_ddrx_ecc_decoder_64.v
+// Megafunction Name(s):
+// 			altecc_decoder
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
+//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
+//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ  VERSION_END
+
+//synthesis_resources = lut 144 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_decoder_64_decode
+	( 
+	data,
+	eq) /* synthesis synthesis_clearbox=1 */;
+	input   [6:0]  data;
+	output   [127:0]  eq;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [6:0]  data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [5:0]  data_wire;
+	wire  enable_wire1;
+	wire  enable_wire2;
+	wire  [127:0]  eq_node;
+	wire  [63:0]  eq_wire1;
+	wire  [63:0]  eq_wire2;
+	wire  [3:0]  w_anode1006w;
+	wire  [3:0]  w_anode1018w;
+	wire  [3:0]  w_anode1029w;
+	wire  [3:0]  w_anode1040w;
+	wire  [3:0]  w_anode1050w;
+	wire  [3:0]  w_anode1060w;
+	wire  [3:0]  w_anode1070w;
+	wire  [3:0]  w_anode1080w;
+	wire  [3:0]  w_anode1090w;
+	wire  [3:0]  w_anode1100w;
+	wire  [3:0]  w_anode1111w;
+	wire  [3:0]  w_anode1122w;
+	wire  [3:0]  w_anode1133w;
+	wire  [3:0]  w_anode1143w;
+	wire  [3:0]  w_anode1153w;
+	wire  [3:0]  w_anode1163w;
+	wire  [3:0]  w_anode1173w;
+	wire  [3:0]  w_anode1183w;
+	wire  [3:0]  w_anode1193w;
+	wire  [3:0]  w_anode1204w;
+	wire  [3:0]  w_anode1215w;
+	wire  [3:0]  w_anode1226w;
+	wire  [3:0]  w_anode1236w;
+	wire  [3:0]  w_anode1246w;
+	wire  [3:0]  w_anode1256w;
+	wire  [3:0]  w_anode1266w;
+	wire  [3:0]  w_anode1276w;
+	wire  [3:0]  w_anode1286w;
+	wire  [3:0]  w_anode1297w;
+	wire  [3:0]  w_anode1308w;
+	wire  [3:0]  w_anode1319w;
+	wire  [3:0]  w_anode1329w;
+	wire  [3:0]  w_anode1339w;
+	wire  [3:0]  w_anode1349w;
+	wire  [3:0]  w_anode1359w;
+	wire  [3:0]  w_anode1369w;
+	wire  [3:0]  w_anode1379w;
+	wire  [3:0]  w_anode1390w;
+	wire  [3:0]  w_anode1401w;
+	wire  [3:0]  w_anode1412w;
+	wire  [3:0]  w_anode1422w;
+	wire  [3:0]  w_anode1432w;
+	wire  [3:0]  w_anode1442w;
+	wire  [3:0]  w_anode1452w;
+	wire  [3:0]  w_anode1462w;
+	wire  [3:0]  w_anode1472w;
+	wire  [3:0]  w_anode1483w;
+	wire  [3:0]  w_anode1494w;
+	wire  [3:0]  w_anode1505w;
+	wire  [3:0]  w_anode1515w;
+	wire  [3:0]  w_anode1525w;
+	wire  [3:0]  w_anode1535w;
+	wire  [3:0]  w_anode1545w;
+	wire  [3:0]  w_anode1555w;
+	wire  [3:0]  w_anode1565w;
+	wire  [3:0]  w_anode1576w;
+	wire  [3:0]  w_anode1587w;
+	wire  [3:0]  w_anode1598w;
+	wire  [3:0]  w_anode1608w;
+	wire  [3:0]  w_anode1618w;
+	wire  [3:0]  w_anode1628w;
+	wire  [3:0]  w_anode1638w;
+	wire  [3:0]  w_anode1648w;
+	wire  [3:0]  w_anode1658w;
+	wire  [3:0]  w_anode1670w;
+	wire  [3:0]  w_anode1681w;
+	wire  [3:0]  w_anode1698w;
+	wire  [3:0]  w_anode1708w;
+	wire  [3:0]  w_anode1718w;
+	wire  [3:0]  w_anode1728w;
+	wire  [3:0]  w_anode1738w;
+	wire  [3:0]  w_anode1748w;
+	wire  [3:0]  w_anode1758w;
+	wire  [3:0]  w_anode1770w;
+	wire  [3:0]  w_anode1781w;
+	wire  [3:0]  w_anode1792w;
+	wire  [3:0]  w_anode1802w;
+	wire  [3:0]  w_anode1812w;
+	wire  [3:0]  w_anode1822w;
+	wire  [3:0]  w_anode1832w;
+	wire  [3:0]  w_anode1842w;
+	wire  [3:0]  w_anode1852w;
+	wire  [3:0]  w_anode1863w;
+	wire  [3:0]  w_anode1874w;
+	wire  [3:0]  w_anode1885w;
+	wire  [3:0]  w_anode1895w;
+	wire  [3:0]  w_anode1905w;
+	wire  [3:0]  w_anode1915w;
+	wire  [3:0]  w_anode1925w;
+	wire  [3:0]  w_anode1935w;
+	wire  [3:0]  w_anode1945w;
+	wire  [3:0]  w_anode1956w;
+	wire  [3:0]  w_anode1967w;
+	wire  [3:0]  w_anode1978w;
+	wire  [3:0]  w_anode1988w;
+	wire  [3:0]  w_anode1998w;
+	wire  [3:0]  w_anode2008w;
+	wire  [3:0]  w_anode2018w;
+	wire  [3:0]  w_anode2028w;
+	wire  [3:0]  w_anode2038w;
+	wire  [3:0]  w_anode2049w;
+	wire  [3:0]  w_anode2060w;
+	wire  [3:0]  w_anode2071w;
+	wire  [3:0]  w_anode2081w;
+	wire  [3:0]  w_anode2091w;
+	wire  [3:0]  w_anode2101w;
+	wire  [3:0]  w_anode2111w;
+	wire  [3:0]  w_anode2121w;
+	wire  [3:0]  w_anode2131w;
+	wire  [3:0]  w_anode2142w;
+	wire  [3:0]  w_anode2153w;
+	wire  [3:0]  w_anode2164w;
+	wire  [3:0]  w_anode2174w;
+	wire  [3:0]  w_anode2184w;
+	wire  [3:0]  w_anode2194w;
+	wire  [3:0]  w_anode2204w;
+	wire  [3:0]  w_anode2214w;
+	wire  [3:0]  w_anode2224w;
+	wire  [3:0]  w_anode2235w;
+	wire  [3:0]  w_anode2246w;
+	wire  [3:0]  w_anode2257w;
+	wire  [3:0]  w_anode2267w;
+	wire  [3:0]  w_anode2277w;
+	wire  [3:0]  w_anode2287w;
+	wire  [3:0]  w_anode2297w;
+	wire  [3:0]  w_anode2307w;
+	wire  [3:0]  w_anode2317w;
+	wire  [3:0]  w_anode2328w;
+	wire  [3:0]  w_anode2339w;
+	wire  [3:0]  w_anode2350w;
+	wire  [3:0]  w_anode2360w;
+	wire  [3:0]  w_anode2370w;
+	wire  [3:0]  w_anode2380w;
+	wire  [3:0]  w_anode2390w;
+	wire  [3:0]  w_anode2400w;
+	wire  [3:0]  w_anode2410w;
+	wire  [3:0]  w_anode912w;
+	wire  [3:0]  w_anode929w;
+	wire  [3:0]  w_anode946w;
+	wire  [3:0]  w_anode956w;
+	wire  [3:0]  w_anode966w;
+	wire  [3:0]  w_anode976w;
+	wire  [3:0]  w_anode986w;
+	wire  [3:0]  w_anode996w;
+	wire  [2:0]  w_data1669w;
+	wire  [2:0]  w_data910w;
+
+	assign
+		data_wire = data[5:0],
+		enable_wire1 = (~ data[6]),
+		enable_wire2 = data[6],
+		eq = eq_node,
+		eq_node = {eq_wire2[63:0], eq_wire1},
+		eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
+		eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
+		w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
+		w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
+		w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
+		w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
+		w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
+		w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
+		w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
+		w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
+		w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
+		w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
+		w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
+		w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
+		w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
+		w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
+		w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
+		w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
+		w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
+		w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
+		w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
+		w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
+		w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
+		w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
+		w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
+		w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
+		w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
+		w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
+		w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
+		w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
+		w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
+		w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
+		w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
+		w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
+		w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
+		w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
+		w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
+		w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
+		w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
+		w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
+		w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
+		w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
+		w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
+		w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
+		w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
+		w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
+		w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
+		w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
+		w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
+		w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
+		w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
+		w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
+		w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
+		w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
+		w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
+		w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
+		w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
+		w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
+		w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
+		w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
+		w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
+		w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
+		w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
+		w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
+		w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
+		w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
+		w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
+		w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
+		w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
+		w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
+		w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
+		w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
+		w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
+		w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
+		w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
+		w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
+		w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
+		w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
+		w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
+		w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
+		w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
+		w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
+		w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
+		w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
+		w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
+		w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
+		w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
+		w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
+		w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
+		w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
+		w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
+		w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
+		w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
+		w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
+		w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
+		w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
+		w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
+		w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
+		w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
+		w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
+		w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
+		w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
+		w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
+		w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
+		w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
+		w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
+		w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
+		w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
+		w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
+		w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
+		w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
+		w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
+		w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
+		w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
+		w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
+		w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
+		w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
+		w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
+		w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
+		w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
+		w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
+		w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
+		w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
+		w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
+		w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
+		w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
+		w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
+		w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
+		w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
+		w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
+		w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
+		w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
+		w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
+		w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
+		w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
+		w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
+		w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
+		w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
+		w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
+		w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
+		w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
+		w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
+		w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
+		w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
+		w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
+		w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
+		w_data1669w = data_wire[2:0],
+		w_data910w = data_wire[2:0];
+endmodule //alt_mem_ddrx_ecc_decoder_64_decode
+
+//synthesis_resources = lut 144 mux21 64 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_decoder_64_altecc_decoder
+	( 
+	clk,
+	reset_n,
+	data,
+	err_corrected,
+	err_detected,
+	err_fatal,
+	err_sbe,
+	q) /* synthesis synthesis_clearbox=1 */;
+	input			clk;
+	input			reset_n;
+	input   [71:0]  data;
+	output   err_corrected;
+	output   err_detected;
+	output   err_fatal;
+	output   err_sbe;
+	output   [63:0]  q;
+
+	parameter CFG_ECC_DECODER_REG = 0;
+	
+	wire  [127:0]   wire_error_bit_decoder_eq;
+	wire	wire_mux21_0_dataout;
+	wire	wire_mux21_1_dataout;
+	wire	wire_mux21_10_dataout;
+	wire	wire_mux21_11_dataout;
+	wire	wire_mux21_12_dataout;
+	wire	wire_mux21_13_dataout;
+	wire	wire_mux21_14_dataout;
+	wire	wire_mux21_15_dataout;
+	wire	wire_mux21_16_dataout;
+	wire	wire_mux21_17_dataout;
+	wire	wire_mux21_18_dataout;
+	wire	wire_mux21_19_dataout;
+	wire	wire_mux21_2_dataout;
+	wire	wire_mux21_20_dataout;
+	wire	wire_mux21_21_dataout;
+	wire	wire_mux21_22_dataout;
+	wire	wire_mux21_23_dataout;
+	wire	wire_mux21_24_dataout;
+	wire	wire_mux21_25_dataout;
+	wire	wire_mux21_26_dataout;
+	wire	wire_mux21_27_dataout;
+	wire	wire_mux21_28_dataout;
+	wire	wire_mux21_29_dataout;
+	wire	wire_mux21_3_dataout;
+	wire	wire_mux21_30_dataout;
+	wire	wire_mux21_31_dataout;
+	wire	wire_mux21_32_dataout;
+	wire	wire_mux21_33_dataout;
+	wire	wire_mux21_34_dataout;
+	wire	wire_mux21_35_dataout;
+	wire	wire_mux21_36_dataout;
+	wire	wire_mux21_37_dataout;
+	wire	wire_mux21_38_dataout;
+	wire	wire_mux21_39_dataout;
+	wire	wire_mux21_4_dataout;
+	wire	wire_mux21_40_dataout;
+	wire	wire_mux21_41_dataout;
+	wire	wire_mux21_42_dataout;
+	wire	wire_mux21_43_dataout;
+	wire	wire_mux21_44_dataout;
+	wire	wire_mux21_45_dataout;
+	wire	wire_mux21_46_dataout;
+	wire	wire_mux21_47_dataout;
+	wire	wire_mux21_48_dataout;
+	wire	wire_mux21_49_dataout;
+	wire	wire_mux21_5_dataout;
+	wire	wire_mux21_50_dataout;
+	wire	wire_mux21_51_dataout;
+	wire	wire_mux21_52_dataout;
+	wire	wire_mux21_53_dataout;
+	wire	wire_mux21_54_dataout;
+	wire	wire_mux21_55_dataout;
+	wire	wire_mux21_56_dataout;
+	wire	wire_mux21_57_dataout;
+	wire	wire_mux21_58_dataout;
+	wire	wire_mux21_59_dataout;
+	wire	wire_mux21_6_dataout;
+	wire	wire_mux21_60_dataout;
+	wire	wire_mux21_61_dataout;
+	wire	wire_mux21_62_dataout;
+	wire	wire_mux21_63_dataout;
+	wire	wire_mux21_7_dataout;
+	wire	wire_mux21_8_dataout;
+	wire	wire_mux21_9_dataout;
+	wire  data_bit;
+	wire  [63:0]  data_t;
+	wire  [71:0]  data_wire;
+	wire  [127:0]  decode_output;
+	wire  err_corrected_wire;
+	wire  err_detected_wire;
+	wire  err_fatal_wire;
+	wire  [35:0]  parity_01_wire;
+	wire  [17:0]  parity_02_wire;
+	wire  [8:0]  parity_03_wire;
+	wire  [3:0]  parity_04_wire;
+	wire  [1:0]  parity_05_wire;
+	wire  [30:0]  parity_06_wire;
+	wire  [6:0]  parity_07_wire;
+	wire  parity_bit;
+	wire  [70:0]  parity_final_wire;
+	wire  [6:0]  parity_t;
+	wire  [63:0]  q_wire;
+	wire  syn_bit;
+	wire  syn_e;
+	wire  [5:0]  syn_t;
+	wire  [7:0]  syndrome_wire;
+	reg   [7:0]  syndrome;
+	reg	  [71:0] data_reg;
+	
+	generate
+		if (CFG_ECC_DECODER_REG == 1)
+		begin
+			always @ (posedge clk or negedge reset_n)
+			begin
+				if (!reset_n)
+				begin
+					syndrome	<= {8{1'b0}};
+					data_reg	<= {72{1'b0}};
+				end else
+				begin
+					syndrome	<= syndrome_wire;
+					data_reg	<= data_wire;
+				end
+			end	
+		end else
+		begin
+			always @ (*)
+			begin
+				syndrome	= syndrome_wire;
+				data_reg	= data_wire;				
+			end
+		end
+	endgenerate
+	alt_mem_ddrx_ecc_decoder_64_decode   error_bit_decoder
+	( 
+	.data(syndrome[6:0]),
+	.eq(wire_error_bit_decoder_eq));
+	assign		wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
+	assign		wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
+	assign		wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
+	assign		wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
+	assign		wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
+	assign		wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
+	assign		wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
+	assign		wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
+	assign		wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
+	assign		wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
+	assign		wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
+	assign		wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
+	assign		wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
+	assign		wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
+	assign		wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
+	assign		wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
+	assign		wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
+	assign		wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
+	assign		wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
+	assign		wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
+	assign		wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
+	assign		wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
+	assign		wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
+	assign		wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
+	assign		wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
+	assign		wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
+	assign		wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_reg[32]) : data_reg[32];
+	assign		wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_reg[33]) : data_reg[33];
+	assign		wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_reg[34]) : data_reg[34];
+	assign		wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_reg[35]) : data_reg[35];
+	assign		wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_reg[36]) : data_reg[36];
+	assign		wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_reg[37]) : data_reg[37];
+	assign		wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_reg[38]) : data_reg[38];
+	assign		wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_reg[39]) : data_reg[39];
+	assign		wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
+	assign		wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_reg[40]) : data_reg[40];
+	assign		wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_reg[41]) : data_reg[41];
+	assign		wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_reg[42]) : data_reg[42];
+	assign		wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_reg[43]) : data_reg[43];
+	assign		wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_reg[44]) : data_reg[44];
+	assign		wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_reg[45]) : data_reg[45];
+	assign		wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_reg[46]) : data_reg[46];
+	assign		wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_reg[47]) : data_reg[47];
+	assign		wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_reg[48]) : data_reg[48];
+	assign		wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_reg[49]) : data_reg[49];
+	assign		wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
+	assign		wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_reg[50]) : data_reg[50];
+	assign		wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_reg[51]) : data_reg[51];
+	assign		wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_reg[52]) : data_reg[52];
+	assign		wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_reg[53]) : data_reg[53];
+	assign		wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_reg[54]) : data_reg[54];
+	assign		wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_reg[55]) : data_reg[55];
+	assign		wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_reg[56]) : data_reg[56];
+	assign		wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_reg[57]) : data_reg[57];
+	assign		wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_reg[58]) : data_reg[58];
+	assign		wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_reg[59]) : data_reg[59];
+	assign		wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
+	assign		wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_reg[60]) : data_reg[60];
+	assign		wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_reg[61]) : data_reg[61];
+	assign		wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_reg[62]) : data_reg[62];
+	assign		wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_reg[63]) : data_reg[63];
+	assign		wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
+	assign		wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
+	assign		wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
+	assign
+		data_bit = data_t[63],
+		data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
+ | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
+		data_wire = data,
+		decode_output = wire_error_bit_decoder_eq,
+		err_corrected = err_corrected_wire,
+		err_corrected_wire = ((syn_bit & syn_e) & data_bit),
+		err_detected = err_detected_wire,
+		err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
+		err_fatal = err_fatal_wire,
+		err_sbe = syn_e,
+		err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
+		parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
+		parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
+		parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
+		parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
+		parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
+		parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
+		parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
+		parity_bit = parity_t[6],
+		parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
+ parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
+		parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
+		q = q_wire,
+		q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
+		syn_bit = syn_t[5],
+		syn_e = syndrome[7],
+		syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
+		syndrome_wire = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
+endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module alt_mem_ddrx_ecc_decoder_64 
+	#(
+		parameter
+			CFG_ECC_DECODER_REG = 1
+	)
+	(
+	clk,
+	reset_n,
+	data,
+	err_corrected,
+	err_detected,
+	err_fatal,
+	err_sbe,
+	q)/* synthesis synthesis_clearbox = 1 */;
+
+	input			clk;
+	input			reset_n;
+	input	[71:0]  data;
+	output	  err_corrected;
+	output	  err_detected;
+	output	  err_fatal;
+	output	  err_sbe;
+	output	[63:0]  q;
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire  sub_wire4;
+	wire [63:0] sub_wire3;
+	wire  err_detected = sub_wire0;
+	wire  err_fatal = sub_wire1;
+	wire  err_corrected = sub_wire2;
+	wire  err_sbe = sub_wire4;
+	wire [63:0] q = sub_wire3[63:0];
+
+	alt_mem_ddrx_ecc_decoder_64_altecc_decoder
+	# (
+		.CFG_ECC_DECODER_REG	(CFG_ECC_DECODER_REG)
+	)
+	alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
+				.clk (clk),
+				.reset_n (reset_n),
+				.data (data),
+				.err_detected (sub_wire0),
+				.err_fatal (sub_wire1),
+				.err_corrected (sub_wire2),
+				.err_sbe (sub_wire4),
+				.q (sub_wire3));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
+// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
+// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
+// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
+// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
+// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
+// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
+// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
+// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
+// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
+// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
+// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
new file mode 100644
index 0000000..04b3a65
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
@@ -0,0 +1,295 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//altera message_off 10036
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_ecc_encoder #
+    ( parameter
+        CFG_DATA_WIDTH              =   40,
+        CFG_ECC_CODE_WIDTH          =   8,
+        CFG_ECC_ENC_REG             =   0,
+        CFG_MMR_DRAM_DATA_WIDTH     =   7,
+        CFG_MMR_LOCAL_DATA_WIDTH    =   7,
+        
+        CFG_PORT_WIDTH_ENABLE_ECC   =   1
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        cfg_local_data_width,
+        cfg_dram_data_width,
+        cfg_enable_ecc,
+        
+        input_data,
+        input_ecc_code,
+        input_ecc_code_overwrite,
+        output_data
+    );
+
+localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
+
+input  ctl_clk;
+input  ctl_reset_n;
+
+input  [CFG_MMR_DRAM_DATA_WIDTH   - 1 : 0] cfg_local_data_width;
+input  [CFG_MMR_LOCAL_DATA_WIDTH  - 1 : 0] cfg_dram_data_width;
+input  [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
+
+input  [CFG_DATA_WIDTH     - 1 : 0] input_data;
+input  [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
+input                               input_ecc_code_overwrite;
+
+output [CFG_DATA_WIDTH - 1 : 0] output_data;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_encoder_input;
+    
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_input_data;
+    reg  [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
+    reg                               int_input_ecc_code_overwrite;
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_encoder_output;
+    
+    reg  [CFG_DATA_WIDTH     - 1 : 0] output_data;
+    reg  [CFG_DATA_WIDTH     - 1 : 0] int_encoder_output_modified;
+    
+    wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
+    wire [CFG_DATA_WIDTH     - 1 : 0] encoder_output;
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Common Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    // Input data
+    generate
+        genvar i_data;
+        for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
+        begin : encoder_input_per_data_width
+            always @ (*)
+            begin
+                int_encoder_input [i_data] = input_data [i_data];
+            end
+        end
+    endgenerate
+    
+    // Encoder input assignment
+    assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
+    
+    // Output data merging logic
+    // change
+    // <ECC code> - <Empty data> - <Data>
+    // into
+    // <Empty data> - <ECC code> - <Data>
+    always @ (*)
+    begin
+        int_encoder_output = encoder_output;
+    end
+    
+    generate
+        if (CFG_DATA_WIDTH <= 8)
+        begin
+            // No support for ECC case
+            always @ (*)
+            begin
+                // Write data only
+                int_encoder_output_modified = int_encoder_output;
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                // Write data
+                int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
+                
+                // Ecc code
+                if (int_input_ecc_code_overwrite)
+                begin
+                    int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
+                end
+                else
+                begin
+                    int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
+                end
+            end
+        end
+    endgenerate
+    
+    // Encoder output assignment
+    always @ (*)
+    begin
+        if (cfg_enable_ecc)
+            output_data = int_encoder_output_modified;
+        else
+            output_data = int_input_data;
+    end
+    
+    generate
+        if (CFG_ECC_ENC_REG)
+        begin
+            // Registered version
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_input_data               <= 0;
+                    int_input_ecc_code           <= 0;
+                    int_input_ecc_code_overwrite <= 0;
+                end
+                else
+                begin
+                    int_input_data               <= input_data;
+                    int_input_ecc_code           <= input_ecc_code;
+                    int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
+                end
+            end
+        end
+        else
+        begin
+            // Non-registered version
+            always @ (*)
+            begin
+                int_input_data               = input_data;
+                int_input_ecc_code           = input_ecc_code;
+                int_input_ecc_code_overwrite = input_ecc_code_overwrite;
+            end
+        end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Common Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+    
+    generate
+    begin
+        if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
+        begin
+            wire [39 : 0] internal_encoder_output;
+            
+            // Assign bit 39 to '0'
+            assign internal_encoder_output [39] = 1'b0;
+            
+            // Assign the lower data bits
+            assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0]              = internal_encoder_output [31 :  0];
+            
+            // Assign the upper ECC bits
+            assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
+            
+            // 32/39 bit encoder instantiation
+            alt_mem_ddrx_ecc_encoder_32 #
+                (
+                    .CFG_ECC_ENC_REG    (CFG_ECC_ENC_REG                 )
+                )
+            encoder_inst
+                (
+                    .clk                (ctl_clk                         ),
+                    .reset_n            (ctl_reset_n                     ),
+            	    .data               ({24'd0, encoder_input}          ),
+                    .q                  (internal_encoder_output [38 : 0])
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 16)
+        begin
+            wire [39 : 0] internal_encoder_output;
+            
+            // Assign bit 39 to '0'
+            assign internal_encoder_output [39] = 1'b0;
+            
+            // Assign the lower data bits
+            assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0]              = internal_encoder_output [31 :  0];
+            
+            // Assign the upper ECC bits
+            assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
+            
+            // 32/39 bit encoder instantiation
+            alt_mem_ddrx_ecc_encoder_32 #
+                (
+                    .CFG_ECC_ENC_REG    (CFG_ECC_ENC_REG                 )
+                )
+            encoder_inst
+                (
+                    .clk                (ctl_clk                         ),
+                    .reset_n            (ctl_reset_n                     ),
+            	    .data               ({16'd0, encoder_input}          ),
+                    .q                  (internal_encoder_output [38 : 0])
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 32)
+        begin
+            // Assign bit 39 to '0'
+            assign encoder_output [39] = 1'b0;
+            
+            // 32/39 bit encoder instantiation
+            alt_mem_ddrx_ecc_encoder_32 #
+                (
+                    .CFG_ECC_ENC_REG    (CFG_ECC_ENC_REG        )
+                )
+            encoder_inst
+                (
+                    .clk                (ctl_clk                ),
+                    .reset_n            (ctl_reset_n            ),
+            	    .data               (encoder_input          ),
+                    .q                  (encoder_output [38 : 0])
+                );
+        end
+        else if (CFG_ECC_DATA_WIDTH == 64)
+        begin
+            // 64/72 bit encoder instantiation
+            alt_mem_ddrx_ecc_encoder_64 #
+                (
+                    .CFG_ECC_ENC_REG    (CFG_ECC_ENC_REG)
+                )
+            encoder_inst
+                (
+                    .clk                (ctl_clk        ),
+                    .reset_n            (ctl_reset_n    ),
+            	    .data               (encoder_input  ),
+                    .q                  (encoder_output )
+                );
+        end
+        else
+        begin
+        	assign encoder_output = {CFG_DATA_WIDTH{1'b0}};
+        end        
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
new file mode 100644
index 0000000..aba974a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
@@ -0,0 +1,288 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTECC%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altecc_encoder 
+
+// ============================================================
+// File Name: alt_mem_ddrx_ecc_encoder_32.v
+// Megafunction Name(s):
+// 			altecc_encoder
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
+//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
+    ( parameter
+        CFG_ECC_ENC_REG = 0
+    )
+	( 
+        clk,
+        reset_n,
+	    data,
+	    q
+    ) /* synthesis synthesis_clearbox=1 */;
+    input           clk;
+    input           reset_n;
+	input   [31:0]  data;
+	output   [38:0]  q;
+
+	wire  [31:0]  data_wire;
+	wire  [17:0]  parity_01_wire;
+	wire  [9:0]  parity_02_wire;
+	wire  [4:0]  parity_03_wire;
+	wire  [1:0]  parity_04_wire;
+	wire  [0:0]  parity_05_wire;
+	wire  [5:0]  parity_06_wire;
+    wire  [37:0]  parity_final;
+	wire  [37:0]  parity_final_wire;
+    reg   [37:0]  parity_final_reg;
+	wire  [37:0]  q_wire;
+    reg   [37:0]  q_reg;
+
+	assign
+		data_wire = data,
+		parity_01_wire = {
+                            (data_wire[30] ^ parity_01_wire[16]),
+                            (data_wire[28] ^ parity_01_wire[15]),
+                            (data_wire[26] ^ parity_01_wire[14]),
+                            (data_wire[25] ^ parity_01_wire[13]),
+                            (data_wire[23] ^ parity_01_wire[12]),
+                            (data_wire[21] ^ parity_01_wire[11]),
+                            (data_wire[19] ^ parity_01_wire[10]),
+                            (data_wire[17] ^ parity_01_wire[9]),
+                            (data_wire[15] ^ parity_01_wire[8]),
+                            (data_wire[13] ^ parity_01_wire[7]),
+                            (data_wire[11] ^ parity_01_wire[6]),
+                            (data_wire[10] ^ parity_01_wire[5]),
+                            (data_wire[8] ^ parity_01_wire[4]),
+                            (data_wire[6] ^ parity_01_wire[3]),
+                            (data_wire[4] ^ parity_01_wire[2]),
+                            (data_wire[3] ^ parity_01_wire[1]),
+                            (data_wire[1] ^ parity_01_wire[0]),
+                            data_wire[0]
+                         },
+		parity_02_wire = {
+                            (data_wire[31] ^ parity_02_wire[8]),
+                            ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
+                            ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
+                            ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
+                            ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
+                            ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
+                            ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
+                            ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
+                            ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
+                            data_wire[0]
+                         },
+		parity_03_wire = {
+                            (((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
+                            ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
+                            ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
+                            ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
+                            ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
+                         },
+		parity_04_wire = {
+                            ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
+                            ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
+                         },
+		parity_05_wire = {
+                            ((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
+                         },
+		parity_06_wire = {
+                            (data_wire[31] ^ parity_06_wire[4]),
+                            (data_wire[30] ^ parity_06_wire[3]),
+                            (data_wire[29] ^ parity_06_wire[2]),
+                            (data_wire[28] ^ parity_06_wire[1]),
+                            (data_wire[27] ^ parity_06_wire[0]),
+                            data_wire[26]
+                         },
+		parity_final_wire = {
+                                (q_wire[37] ^ parity_final_wire[36]),
+                                (q_wire[36] ^ parity_final_wire[35]),
+                                (q_wire[35] ^ parity_final_wire[34]),
+                                (q_wire[34] ^ parity_final_wire[33]),
+                                (q_wire[33] ^ parity_final_wire[32]),
+                                (q_wire[32] ^ parity_final_wire[31]),
+                                (q_wire[31] ^ parity_final_wire[30]),
+                                (q_wire[30] ^ parity_final_wire[29]),
+                                (q_wire[29] ^ parity_final_wire[28]),
+                                (q_wire[28] ^ parity_final_wire[27]),
+                                (q_wire[27] ^ parity_final_wire[26]),
+                                (q_wire[26] ^ parity_final_wire[25]),
+                                (q_wire[25] ^ parity_final_wire[24]),
+                                (q_wire[24] ^ parity_final_wire[23]),
+                                (q_wire[23] ^ parity_final_wire[22]),
+                                (q_wire[22] ^ parity_final_wire[21]),
+                                (q_wire[21] ^ parity_final_wire[20]),
+                                (q_wire[20] ^ parity_final_wire[19]),
+                                (q_wire[19] ^ parity_final_wire[18]),
+                                (q_wire[18] ^ parity_final_wire[17]),
+                                (q_wire[17] ^ parity_final_wire[16]),
+                                (q_wire[16] ^ parity_final_wire[15]),
+                                (q_wire[15] ^ parity_final_wire[14]),
+                                (q_wire[14] ^ parity_final_wire[13]),
+                                (q_wire[13] ^ parity_final_wire[12]),
+                                (q_wire[12] ^ parity_final_wire[11]),
+                                (q_wire[11] ^ parity_final_wire[10]),
+                                (q_wire[10] ^ parity_final_wire[9]),
+                                (q_wire[9] ^ parity_final_wire[8]),
+                                (q_wire[8] ^ parity_final_wire[7]),
+                                (q_wire[7] ^ parity_final_wire[6]),
+                                (q_wire[6] ^ parity_final_wire[5]),
+                                (q_wire[5] ^ parity_final_wire[4]),
+                                (q_wire[4] ^ parity_final_wire[3]),
+                                (q_wire[3] ^ parity_final_wire[2]),
+                                (q_wire[2] ^ parity_final_wire[1]),
+                                (q_wire[1] ^ parity_final_wire[0]),
+                                 q_wire[0]
+                            },
+        parity_final = {
+                            (q_reg[37] ^ parity_final[36]),
+                            (q_reg[36] ^ parity_final[35]),
+                            (q_reg[35] ^ parity_final[34]),
+                            (q_reg[34] ^ parity_final[33]),
+                            (q_reg[33] ^ parity_final[32]),
+                            (q_reg[32] ^ parity_final[31]),
+                            parity_final_reg[31 : 0]
+                       },
+        q = {parity_final[37], q_reg},
+		q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
+        
+        generate
+            if (CFG_ECC_ENC_REG)
+            begin
+                always @ (posedge clk or negedge reset_n)
+                begin
+                    if (!reset_n)
+                    begin
+                        q_reg            <= 0;
+                        parity_final_reg <= 0;
+                    end
+                    else
+                    begin
+                        q_reg            <= q_wire;
+                        parity_final_reg <= parity_final_wire;
+                    end
+                end
+            end
+            else
+            begin
+                always @ (*)
+                begin
+                    q_reg            = q_wire;
+                    parity_final_reg = parity_final_wire;
+                end
+            end
+        endgenerate
+        
+endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module alt_mem_ddrx_ecc_encoder_32 #
+    ( parameter
+        CFG_ECC_ENC_REG = 0
+    )
+    (
+        clk,
+        reset_n,
+	    data,
+	    q
+    )/* synthesis synthesis_clearbox = 1 */;
+
+    input           clk;
+    input           reset_n;
+	input	[31:0]  data;
+	output	[38:0]  q;
+
+	wire [38:0] sub_wire0;
+	wire [38:0] q = sub_wire0[38:0];
+
+	alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
+        (
+            .CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
+        )
+    alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
+        (
+            .clk (clk),
+            .reset_n (reset_n),
+		    .data (data),
+		    .q (sub_wire0)
+        );
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
+// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
+// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
new file mode 100644
index 0000000..8031fd6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
@@ -0,0 +1,394 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTECC%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altecc_encoder 
+
+// ============================================================
+// File Name: alt_mem_ddrx_ecc_encoder_64.v
+// Megafunction Name(s):
+// 			altecc_encoder
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data q
+//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
+    ( parameter
+        CFG_ECC_ENC_REG = 0
+    )
+	(
+        clk,
+        reset_n,
+	    data,
+	    q
+    ) /* synthesis synthesis_clearbox=1 */;
+    input           clk;
+    input           reset_n;
+	input   [63:0]  data;
+	output   [71:0]  q;
+
+	wire  [63:0]  data_wire;
+	wire  [34:0]  parity_01_wire;
+	wire  [17:0]  parity_02_wire;
+	wire  [8:0]   parity_03_wire;
+	wire  [3:0]   parity_04_wire;
+	wire  [1:0]   parity_05_wire;
+	wire  [30:0]  parity_06_wire;
+	wire  [6:0]   parity_07_wire;
+    wire  [70:0]  parity_final;
+	wire  [70:0]  parity_final_wire;
+    reg   [70:0]  parity_final_reg;
+	wire  [70:0]  q_wire;
+    reg   [70:0]  q_reg;
+    
+	assign
+		data_wire = data,
+		parity_01_wire = {
+                            (data_wire[63] ^ parity_01_wire[33]),
+                            (data_wire[61] ^ parity_01_wire[32]),
+                            (data_wire[59] ^ parity_01_wire[31]),
+                            (data_wire[57] ^ parity_01_wire[30]),
+                            (data_wire[56] ^ parity_01_wire[29]),
+                            (data_wire[54] ^ parity_01_wire[28]),
+                            (data_wire[52] ^ parity_01_wire[27]),
+                            (data_wire[50] ^ parity_01_wire[26]),
+                            (data_wire[48] ^ parity_01_wire[25]),
+                            (data_wire[46] ^ parity_01_wire[24]),
+                            (data_wire[44] ^ parity_01_wire[23]),
+                            (data_wire[42] ^ parity_01_wire[22]),
+                            (data_wire[40] ^ parity_01_wire[21]),
+                            (data_wire[38] ^ parity_01_wire[20]),
+                            (data_wire[36] ^ parity_01_wire[19]),
+                            (data_wire[34] ^ parity_01_wire[18]),
+                            (data_wire[32] ^ parity_01_wire[17]),
+                            (data_wire[30] ^ parity_01_wire[16]),
+                            (data_wire[28] ^ parity_01_wire[15]),
+                            (data_wire[26] ^ parity_01_wire[14]),
+                            (data_wire[25] ^ parity_01_wire[13]),
+                            (data_wire[23] ^ parity_01_wire[12]),
+                            (data_wire[21] ^ parity_01_wire[11]),
+                            (data_wire[19] ^ parity_01_wire[10]),
+                            (data_wire[17] ^ parity_01_wire[9]),
+                            (data_wire[15] ^ parity_01_wire[8]),
+                            (data_wire[13] ^ parity_01_wire[7]),
+                            (data_wire[11] ^ parity_01_wire[6]),
+                            (data_wire[10] ^ parity_01_wire[5]),
+                            (data_wire[8] ^ parity_01_wire[4]),
+                            (data_wire[6] ^ parity_01_wire[3]),
+                            (data_wire[4] ^ parity_01_wire[2]),
+                            (data_wire[3] ^ parity_01_wire[1]),
+                            (data_wire[1] ^ parity_01_wire[0]),
+                            data_wire[0]
+                         },
+		parity_02_wire = {
+                            ((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]),
+                            ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]),
+                            ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]),
+                            ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]),
+                            ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]),
+                            ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]),
+                            ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]),
+                            ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]),
+                            ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]),
+                            ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
+                            ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
+                            ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
+                            ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
+                            ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
+                            ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
+                            ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
+                            ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
+                            data_wire[0]
+                         },
+		parity_03_wire = {
+                            ((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]),
+                            ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]),
+                            ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]),
+                            ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]),
+                            ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]),
+                            ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
+                            ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
+                            ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
+                            ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
+                         },
+		parity_04_wire = {
+                            ((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]),
+                            ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]),
+                            ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
+                            ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
+                         },
+		parity_05_wire = {
+                            ((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]),
+                            ((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
+                         },
+		parity_06_wire = {
+                            (data_wire[56] ^ parity_06_wire[29]),
+                            (data_wire[55] ^ parity_06_wire[28]),
+                            (data_wire[54] ^ parity_06_wire[27]),
+                            (data_wire[53] ^ parity_06_wire[26]),
+                            (data_wire[52] ^ parity_06_wire[25]),
+                            (data_wire[51] ^ parity_06_wire[24]),
+                            (data_wire[50] ^ parity_06_wire[23]),
+                            (data_wire[49] ^ parity_06_wire[22]),
+                            (data_wire[48] ^ parity_06_wire[21]),
+                            (data_wire[47] ^ parity_06_wire[20]),
+                            (data_wire[46] ^ parity_06_wire[19]),
+                            (data_wire[45] ^ parity_06_wire[18]),
+                            (data_wire[44] ^ parity_06_wire[17]),
+                            (data_wire[43] ^ parity_06_wire[16]),
+                            (data_wire[42] ^ parity_06_wire[15]),
+                            (data_wire[41] ^ parity_06_wire[14]),
+                            (data_wire[40] ^ parity_06_wire[13]),
+                            (data_wire[39] ^ parity_06_wire[12]),
+                            (data_wire[38] ^ parity_06_wire[11]),
+                            (data_wire[37] ^ parity_06_wire[10]),
+                            (data_wire[36] ^ parity_06_wire[9]),
+                            (data_wire[35] ^ parity_06_wire[8]),
+                            (data_wire[34] ^ parity_06_wire[7]),
+                            (data_wire[33] ^ parity_06_wire[6]),
+                            (data_wire[32] ^ parity_06_wire[5]),
+                            (data_wire[31] ^ parity_06_wire[4]),
+                            (data_wire[30] ^ parity_06_wire[3]),
+                            (data_wire[29] ^ parity_06_wire[2]),
+                            (data_wire[28] ^ parity_06_wire[1]),
+                            (data_wire[27] ^ parity_06_wire[0]),
+                            data_wire[26]
+                         },
+		parity_07_wire = {
+                            (data_wire[63] ^ parity_07_wire[5]),
+                            (data_wire[62] ^ parity_07_wire[4]),
+                            (data_wire[61] ^ parity_07_wire[3]),
+                            (data_wire[60] ^ parity_07_wire[2]),
+                            (data_wire[59] ^ parity_07_wire[1]),
+                            (data_wire[58] ^ parity_07_wire[0]),
+                            data_wire[57]
+                         },
+		parity_final_wire = {
+                                (q_wire[70] ^ parity_final_wire[69]),
+                                (q_wire[69] ^ parity_final_wire[68]),
+                                (q_wire[68] ^ parity_final_wire[67]),
+                                (q_wire[67] ^ parity_final_wire[66]),
+                                (q_wire[66] ^ parity_final_wire[65]),
+                                (q_wire[65] ^ parity_final_wire[64]),
+                                (q_wire[64] ^ parity_final_wire[63]),
+                                (q_wire[63] ^ parity_final_wire[62]),
+                                (q_wire[62] ^ parity_final_wire[61]),
+                                (q_wire[61] ^ parity_final_wire[60]),
+                                (q_wire[60] ^ parity_final_wire[59]),
+                                (q_wire[59] ^ parity_final_wire[58]),
+                                (q_wire[58] ^ parity_final_wire[57]),
+                                (q_wire[57] ^ parity_final_wire[56]),
+                                (q_wire[56] ^ parity_final_wire[55]),
+                                (q_wire[55] ^ parity_final_wire[54]),
+                                (q_wire[54] ^ parity_final_wire[53]),
+                                (q_wire[53] ^ parity_final_wire[52]),
+                                (q_wire[52] ^ parity_final_wire[51]),
+                                (q_wire[51] ^ parity_final_wire[50]),
+                                (q_wire[50] ^ parity_final_wire[49]),
+                                (q_wire[49] ^ parity_final_wire[48]),
+                                (q_wire[48] ^ parity_final_wire[47]),
+                                (q_wire[47] ^ parity_final_wire[46]),
+                                (q_wire[46] ^ parity_final_wire[45]),
+                                (q_wire[45] ^ parity_final_wire[44]),
+                                (q_wire[44] ^ parity_final_wire[43]),
+                                (q_wire[43] ^ parity_final_wire[42]),
+                                (q_wire[42] ^ parity_final_wire[41]),
+                                (q_wire[41] ^ parity_final_wire[40]),
+                                (q_wire[40] ^ parity_final_wire[39]),
+                                (q_wire[39] ^ parity_final_wire[38]),
+                                (q_wire[38] ^ parity_final_wire[37]),
+                                (q_wire[37] ^ parity_final_wire[36]),
+                                (q_wire[36] ^ parity_final_wire[35]),
+                                (q_wire[35] ^ parity_final_wire[34]),
+                                (q_wire[34] ^ parity_final_wire[33]),
+                                (q_wire[33] ^ parity_final_wire[32]),
+                                (q_wire[32] ^ parity_final_wire[31]),
+                                (q_wire[31] ^ parity_final_wire[30]),
+                                (q_wire[30] ^ parity_final_wire[29]),
+                                (q_wire[29] ^ parity_final_wire[28]),
+                                (q_wire[28] ^ parity_final_wire[27]),
+                                (q_wire[27] ^ parity_final_wire[26]),
+                                (q_wire[26] ^ parity_final_wire[25]),
+                                (q_wire[25] ^ parity_final_wire[24]),
+                                (q_wire[24] ^ parity_final_wire[23]),
+                                (q_wire[23] ^ parity_final_wire[22]),
+                                (q_wire[22] ^ parity_final_wire[21]),
+                                (q_wire[21] ^ parity_final_wire[20]),
+                                (q_wire[20] ^ parity_final_wire[19]),
+                                (q_wire[19] ^ parity_final_wire[18]),
+                                (q_wire[18] ^ parity_final_wire[17]),
+                                (q_wire[17] ^ parity_final_wire[16]),
+                                (q_wire[16] ^ parity_final_wire[15]),
+                                (q_wire[15] ^ parity_final_wire[14]),
+                                (q_wire[14] ^ parity_final_wire[13]),
+                                (q_wire[13] ^ parity_final_wire[12]),
+                                (q_wire[12] ^ parity_final_wire[11]),
+                                (q_wire[11] ^ parity_final_wire[10]),
+                                (q_wire[10] ^ parity_final_wire[9]),
+                                (q_wire[9]  ^ parity_final_wire[8]),
+                                (q_wire[8]  ^ parity_final_wire[7]),
+                                (q_wire[7]  ^ parity_final_wire[6]),
+                                (q_wire[6]  ^ parity_final_wire[5]),
+                                (q_wire[5]  ^ parity_final_wire[4]),
+                                (q_wire[4]  ^ parity_final_wire[3]),
+                                (q_wire[3]  ^ parity_final_wire[2]),
+                                (q_wire[2]  ^ parity_final_wire[1]),
+                                (q_wire[1]  ^ parity_final_wire[0]),
+                                 q_wire[0]
+                            },
+        parity_final = {
+                            (q_reg[70] ^ parity_final[69]),
+                            (q_reg[69] ^ parity_final[68]),
+                            (q_reg[68] ^ parity_final[67]),
+                            (q_reg[67] ^ parity_final[66]),
+                            (q_reg[66] ^ parity_final[65]),
+                            (q_reg[65] ^ parity_final[64]),
+                            parity_final_reg [64 : 0]
+                       },
+		q = {parity_final[70], q_reg},
+		q_wire = {parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[34], data_wire};
+        
+        generate
+            if (CFG_ECC_ENC_REG)
+            begin
+                always @ (posedge clk or negedge reset_n)
+                begin
+                    if (!reset_n)
+                    begin
+                        q_reg            <= 0;
+                        parity_final_reg <= 0;
+                    end
+                    else
+                    begin
+                        q_reg            <= q_wire;
+                        parity_final_reg <= parity_final_wire;
+                    end
+                end
+            end
+            else
+            begin
+                always @ (*)
+                begin
+                    q_reg            = q_wire;
+                    parity_final_reg = parity_final_wire;
+                end
+            end
+        endgenerate
+endmodule //alt_mem_ddrx_ecc_encoder_64_altecc_encoder
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module alt_mem_ddrx_ecc_encoder_64 #
+    ( parameter
+        CFG_ECC_ENC_REG = 0
+    )
+    (
+        clk,
+        reset_n,
+	    data,
+	    q
+    )/* synthesis synthesis_clearbox = 1 */;
+
+    input           clk;
+    input           reset_n;
+	input	[63:0]  data;
+	output	[71:0]  q;
+
+	wire [71:0] sub_wire0;
+	wire [71:0] q = sub_wire0[71:0];
+
+	alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
+        (
+            .CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
+        )
+    alt_mem_ddrx_ecc_encoder_64_altecc_encoder_component
+        (
+            .clk (clk),
+            .reset_n (reset_n),
+		    .data (data),
+		    .q (sub_wire0)
+        );
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
+// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
+// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
+// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
+// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
+// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
+// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_syn.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
new file mode 100644
index 0000000..ac5c5f9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
@@ -0,0 +1,1156 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
+    ( parameter
+        CFG_LOCAL_DATA_WIDTH                    =   80,
+        CFG_LOCAL_ADDR_WIDTH                    =   32,
+        CFG_DWIDTH_RATIO                        =   2,
+        
+        CFG_MEM_IF_DQ_WIDTH                     =   40,
+        CFG_MEM_IF_DQS_WIDTH                    =   5,
+        
+        CFG_ECC_CODE_WIDTH                      =   8,
+        CFG_ECC_MULTIPLES                       =   1,
+        
+        CFG_ECC_ENC_REG                         =   0,
+        CFG_ECC_DEC_REG                         =   0,
+		CFG_ECC_DECODER_REG						=	0,
+        CFG_ECC_RDATA_REG                       =   0,
+        
+        CFG_PORT_WIDTH_INTERFACE_WIDTH          =   8,
+        CFG_PORT_WIDTH_ENABLE_ECC               =   1,
+        CFG_PORT_WIDTH_GEN_SBE                  =   1,
+        CFG_PORT_WIDTH_GEN_DBE                  =   1,
+        CFG_PORT_WIDTH_ENABLE_INTR              =   1,
+        CFG_PORT_WIDTH_MASK_SBE_INTR            =   1,
+        CFG_PORT_WIDTH_MASK_DBE_INTR            =   1,
+        CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR   =   1,
+        CFG_PORT_WIDTH_CLR_INTR                 =   1,
+        
+        STS_PORT_WIDTH_SBE_ERROR                =   1,
+        STS_PORT_WIDTH_DBE_ERROR                =   1,
+        STS_PORT_WIDTH_SBE_COUNT                =   8,
+        STS_PORT_WIDTH_DBE_COUNT                =   8,
+        STS_PORT_WIDTH_CORR_DROP_ERROR          =   1,
+        STS_PORT_WIDTH_CORR_DROP_COUNT          =   8
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // MMR Interface
+        cfg_interface_width,
+        cfg_enable_ecc,
+        cfg_gen_sbe,
+        cfg_gen_dbe,
+        cfg_enable_intr,
+        cfg_mask_sbe_intr,
+        cfg_mask_dbe_intr,
+        cfg_mask_corr_dropped_intr,
+        cfg_clr_intr,
+        
+        // Wdata & Rdata Interface Inputs
+        wdatap_dm,
+        wdatap_data,
+        wdatap_rmw_partial_data,
+        wdatap_rmw_correct_data,
+        wdatap_rmw_partial,
+        wdatap_rmw_correct,
+        wdatap_ecc_code,
+        wdatap_ecc_code_overwrite,
+        rdatap_rcvd_addr,
+        rdatap_rcvd_cmd,
+        rdatap_rcvd_corr_dropped,
+        
+        // AFI Interface Inputs
+        afi_rdata,
+        afi_rdata_valid,
+        
+        // Wdata & Rdata Interface Outputs
+        ecc_rdata,
+        ecc_rdata_valid,
+        
+        // AFI Inteface Outputs
+        ecc_dm,
+        ecc_wdata,
+        
+        // ECC Error Information
+        ecc_sbe,
+        ecc_dbe,
+        ecc_code,
+        ecc_interrupt,
+        
+        // MMR ECC Information
+        sts_sbe_error,
+        sts_dbe_error,
+        sts_sbe_count,
+        sts_dbe_count,
+        sts_err_addr,
+        sts_corr_dropped,
+        sts_corr_dropped_count,
+        sts_corr_dropped_addr
+    );
+//--------------------------------------------------------------------------------------------------------
+//
+//  Important Note:
+//  
+//  This block is coded with the following consideration in mind
+//  - Parameter
+//      - maximum LOCAL_DATA_WIDTH will be (40 * DWIDTH_RATIO)
+//      - maximum ECC_DATA_WIDTH will be (40 * DWIDTH_RATIO)
+//  - MMR configuration
+//      - ECC option disabled:
+//          - maximum DQ width is 40
+//          - maximum LOCAL_DATA width is (40 * DWIDTH_RATIO)
+//          - WDATAP_DATA and ECC_DATA size will match (no ECC code)
+//      - ECC option enabled:
+//          - maximum DQ width is 40
+//          - maximum LOCAL_DATA width is (32 * DWIDTH_RATIO)
+//          - WDATAP_DATA width will be (8 * DWIDTH_RATIO) lesser than ECC_DATA (ECC code)
+//  
+//  Block level diagram
+//  -----------------------------------                                                                               
+//      Write Data Path (Per DRATE)                                                                                   
+//  -----------------------------------                                                                               
+//                     __________                    ___________                    ___________                       
+//                    |          |                  |           |                  |           |                      
+//  Local Write Data  |   Data   |                  |           |                  |           |                      
+//  ---- 40 bits ---->|   Mask   |---- 32 bits ---->|  Encoder  |---- 40 bits ---->|  ECC MUX  |---- 40 bits ---->    
+//                |   |          |                  |           |                  |           |                      
+//                |   |__________|                  |___________|                  |___________|                      
+//                |                                                                      ^                            
+//                |---------------------------------- 40 bits ---------------------------|                            
+//                                                                                                                    
+//                                                                                                                    
+//  -----------------------------------                                                                               
+//      Read Data Path (Per DRATE)                                                                                    
+//  -----------------------------------                                                                               
+//                     __________                    ___________                    ___________                       
+//                    |          |                  |           |                  |           |                      
+//    AFI Read Data   |   Data   |                  |           |                  |           |                      
+//  ---- 40 bits ---->|   Mask   |---- 40 bits ---->|  Decoder  |---- 32 bits ---->|  ECC MUX  |---- 40 bits ---->    
+//                |   |          |                  |           |                  |           |                      
+//                |   |__________|                  |___________|                  |___________|                      
+//                |                                                                      ^                            
+//                |---------------------------------- 40 bits ---------------------------|                            
+//                                                                                                                    
+//--------------------------------------------------------------------------------------------------------
+
+localparam CFG_MEM_IF_DQ_PER_DQS         = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
+
+localparam CFG_ECC_DATA_WIDTH            = CFG_MEM_IF_DQ_WIDTH  * CFG_DWIDTH_RATIO;
+
+localparam CFG_LOCAL_DM_WIDTH            = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
+localparam CFG_ECC_DM_WIDTH              = CFG_ECC_DATA_WIDTH   / CFG_MEM_IF_DQ_PER_DQS;
+
+localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
+localparam CFG_LOCAL_DM_PER_WORD_WIDTH   = CFG_LOCAL_DM_WIDTH   / CFG_ECC_MULTIPLES;
+localparam CFG_ECC_DATA_PER_WORD_WIDTH   = CFG_ECC_DATA_WIDTH   / CFG_ECC_MULTIPLES;
+localparam CFG_ECC_DM_PER_WORD_WIDTH     = CFG_ECC_DM_WIDTH     / CFG_ECC_MULTIPLES;
+
+localparam CFG_MMR_DRAM_DATA_WIDTH       = CFG_PORT_WIDTH_INTERFACE_WIDTH;
+localparam CFG_MMR_LOCAL_DATA_WIDTH      = CFG_PORT_WIDTH_INTERFACE_WIDTH;
+
+localparam CFG_MMR_DRAM_DM_WIDTH         = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;  // Minus 3 because byte enable will be divided by 4/8
+localparam CFG_MMR_LOCAL_DM_WIDTH        = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2;  // Minus 3 because byte enable will be divided by 4/8
+
+// The following 2 parameters should match!
+localparam CFG_ENCODER_DATA_WIDTH       = CFG_ECC_DATA_PER_WORD_WIDTH;          // supports only 24, 40 and 72
+localparam CFG_DECODER_DATA_WIDTH       = CFG_ECC_DATA_PER_WORD_WIDTH;          // supports only 24, 40 and 72
+
+input  ctl_clk;
+input  ctl_reset_n;
+
+// MMR Interface
+input  [CFG_PORT_WIDTH_INTERFACE_WIDTH          - 1 : 0] cfg_interface_width;
+input  [CFG_PORT_WIDTH_ENABLE_ECC               - 1 : 0] cfg_enable_ecc;
+input  [CFG_PORT_WIDTH_GEN_SBE                  - 1 : 0] cfg_gen_sbe;
+input  [CFG_PORT_WIDTH_GEN_DBE                  - 1 : 0] cfg_gen_dbe;
+input  [CFG_PORT_WIDTH_ENABLE_INTR              - 1 : 0] cfg_enable_intr;
+input  [CFG_PORT_WIDTH_MASK_SBE_INTR            - 1 : 0] cfg_mask_sbe_intr;
+input  [CFG_PORT_WIDTH_MASK_DBE_INTR            - 1 : 0] cfg_mask_dbe_intr;
+input  [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR   - 1 : 0] cfg_mask_corr_dropped_intr;
+input  [CFG_PORT_WIDTH_CLR_INTR                 - 1 : 0] cfg_clr_intr;
+
+// Wdata & Rdata Interface Inputs
+input  [CFG_LOCAL_DM_WIDTH                     - 1 : 0] wdatap_dm;
+input  [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] wdatap_data;
+input  [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] wdatap_rmw_partial_data;
+input  [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] wdatap_rmw_correct_data;
+input                                                   wdatap_rmw_partial;
+input                                                   wdatap_rmw_correct;
+input  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
+input  [CFG_ECC_MULTIPLES                      - 1 : 0] wdatap_ecc_code_overwrite;
+input  [CFG_LOCAL_ADDR_WIDTH                   - 1 : 0] rdatap_rcvd_addr;
+input                                                   rdatap_rcvd_cmd;
+input                                                   rdatap_rcvd_corr_dropped;
+
+// AFI Interface Inputs
+input  [CFG_ECC_DATA_WIDTH   - 1 : 0] afi_rdata;
+input  [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
+
+// Wdata & Rdata Interface Outputs
+output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
+output                                ecc_rdata_valid;
+
+// AFI Inteface Outputs
+output [CFG_ECC_DM_WIDTH     - 1 : 0] ecc_dm;
+output [CFG_ECC_DATA_WIDTH   - 1 : 0] ecc_wdata;
+
+// ECC Error Information
+output [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_sbe;
+output [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_dbe;
+output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
+output                                                  ecc_interrupt;
+
+// MMR ECC Information
+output [STS_PORT_WIDTH_SBE_ERROR        - 1 : 0] sts_sbe_error;
+output [STS_PORT_WIDTH_DBE_ERROR        - 1 : 0] sts_dbe_error;
+output [STS_PORT_WIDTH_SBE_COUNT        - 1 : 0] sts_sbe_count;
+output [STS_PORT_WIDTH_DBE_COUNT        - 1 : 0] sts_dbe_count;
+output [CFG_LOCAL_ADDR_WIDTH            - 1 : 0] sts_err_addr;
+output [STS_PORT_WIDTH_CORR_DROP_ERROR  - 1 : 0] sts_corr_dropped;
+output [STS_PORT_WIDTH_CORR_DROP_COUNT  - 1 : 0] sts_corr_dropped_count;
+output [CFG_LOCAL_ADDR_WIDTH            - 1 : 0] sts_corr_dropped_addr;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // Output registers
+    reg  [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] ecc_rdata;
+    reg                                                   ecc_rdata_valid;
+    reg  [CFG_ECC_DM_WIDTH                       - 1 : 0] ecc_dm;
+    reg  [CFG_ECC_DATA_WIDTH                     - 1 : 0] ecc_wdata;
+    reg  [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_sbe;
+    reg  [CFG_ECC_MULTIPLES                      - 1 : 0] ecc_dbe;
+    reg  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
+    reg                                                   ecc_interrupt;
+    reg  [STS_PORT_WIDTH_SBE_ERROR               - 1 : 0] sts_sbe_error;
+    reg  [STS_PORT_WIDTH_DBE_ERROR               - 1 : 0] sts_dbe_error;
+    reg  [STS_PORT_WIDTH_SBE_COUNT               - 1 : 0] sts_sbe_count;
+    reg  [STS_PORT_WIDTH_DBE_COUNT               - 1 : 0] sts_dbe_count;
+    reg  [CFG_LOCAL_ADDR_WIDTH                   - 1 : 0] sts_err_addr;
+    reg  [STS_PORT_WIDTH_CORR_DROP_ERROR         - 1 : 0] sts_corr_dropped;
+    reg  [STS_PORT_WIDTH_CORR_DROP_COUNT         - 1 : 0] sts_corr_dropped_count;
+    reg  [CFG_LOCAL_ADDR_WIDTH                   - 1 : 0] sts_corr_dropped_addr;
+    
+    // Common
+    reg  [CFG_MMR_DRAM_DATA_WIDTH  - 1 : 0] cfg_dram_data_width;
+    reg  [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
+    
+    reg  [CFG_MMR_DRAM_DM_WIDTH    - 1 : 0] cfg_dram_dm_width;
+    reg  [CFG_MMR_LOCAL_DM_WIDTH   - 1 : 0] cfg_local_dm_width;
+    
+    // Input Logic
+    reg  [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
+    reg  [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
+    reg  [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
+    
+    reg                                 int_encoder_input_rmw_partial;
+    reg                                 int_encoder_input_rmw_correct;
+    reg                                 wdatap_rmw_partial_r;
+    reg                                 wdatap_rmw_correct_r;
+    
+    reg  [CFG_ECC_DATA_WIDTH   - 1 : 0] int_decoder_input_data;
+    reg                                 int_decoder_input_data_valid;
+    
+    // Output Logic
+    reg  [CFG_ECC_MULTIPLES    - 1 : 0] int_sbe;
+    reg  [CFG_ECC_MULTIPLES    - 1 : 0] int_dbe;
+    
+    reg  [CFG_ECC_DM_WIDTH     - 1 : 0] int_encoder_output_dm;
+    reg  [CFG_ECC_DM_WIDTH     - 1 : 0] int_encoder_output_dm_r;
+    wire [CFG_ECC_MULTIPLES    - 1 : 0] int_decoder_output_data_valid;
+    
+    reg  [CFG_ECC_DATA_WIDTH                     - 1 : 0] int_encoder_output_data;
+    reg  [CFG_ECC_DATA_WIDTH                     - 1 : 0] int_encoder_output_data_r;
+    wire [CFG_LOCAL_DATA_WIDTH                   - 1 : 0] int_decoder_output_data;
+    wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
+    
+    // ECC specific logic
+    reg  [1                            : 0] inject_data_error;
+    
+    reg                                     int_sbe_detected;
+    reg                                     int_dbe_detected;
+    wire                                    int_be_detected;
+    reg                                     int_sbe_store;
+    reg                                     int_dbe_store;
+    reg                                     int_sbe_valid;
+    reg                                     int_dbe_valid;
+    reg                                     int_sbe_valid_r;
+    reg                                     int_dbe_valid_r;
+    
+    reg                                     int_ecc_interrupt;
+    wire                                    int_interruptable_error_detected;
+    
+    reg  [STS_PORT_WIDTH_SBE_ERROR          - 1 : 0] int_sbe_error;
+    reg  [STS_PORT_WIDTH_DBE_ERROR          - 1 : 0] int_dbe_error;
+    reg  [STS_PORT_WIDTH_SBE_COUNT          - 1 : 0] int_sbe_count;
+    reg  [STS_PORT_WIDTH_DBE_COUNT          - 1 : 0] int_dbe_count;
+    reg  [CFG_LOCAL_ADDR_WIDTH              - 1 : 0] int_err_addr ;
+    reg  [STS_PORT_WIDTH_CORR_DROP_ERROR    - 1 : 0] int_corr_dropped;
+    reg  [STS_PORT_WIDTH_CORR_DROP_COUNT    - 1 : 0] int_corr_dropped_count;
+    reg  [CFG_LOCAL_ADDR_WIDTH              - 1 : 0] int_corr_dropped_addr ;
+    reg                                              int_corr_dropped_detected;
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Common
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // DRAM and local data width
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_dram_data_width <= 0;
+        end
+        else
+        begin
+            cfg_dram_data_width <= cfg_interface_width;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_local_data_width <= 0;
+        end
+        else
+        begin
+            // Important note, if we set memory interface width (DQ width) to 8 and enable_ecc to 1,
+            // this will result in local data width of 0, this case is not supported
+            // this must be checked with assertion so that this case will not happen in regression
+            if (cfg_enable_ecc)
+            begin
+                cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
+            end
+            else
+            begin
+                cfg_local_data_width <= cfg_interface_width;
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // DRAM and local be width
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_dram_dm_width <= 0;
+        end
+        else
+        begin
+            cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_local_dm_width <= 0;
+        end
+        else
+        begin
+            cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
+        end
+    end
+    
+    // Registered version
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            wdatap_rmw_partial_r <= 1'b0;
+            wdatap_rmw_correct_r <= 1'b0;
+        end
+        else
+        begin
+            wdatap_rmw_partial_r <= wdatap_rmw_partial;
+            wdatap_rmw_correct_r <= wdatap_rmw_correct;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_encoder_output_data_r <= 0;
+            int_encoder_output_dm_r   <= 0;
+        end
+        else
+        begin
+            int_encoder_output_data_r <= int_encoder_output_data;
+            int_encoder_output_dm_r   <= int_encoder_output_dm;
+        end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [ENC] Common
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Input Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Write data & byte enable from wdata_path
+    //----------------------------------------------------------------------------------------------------
+    always @ (*)
+    begin
+        int_encoder_input_data             = wdatap_data;
+        int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
+        int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
+        
+        if (CFG_ECC_ENC_REG)
+        begin
+            int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
+            int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
+        end
+        else
+        begin
+            int_encoder_input_rmw_partial = wdatap_rmw_partial;
+            int_encoder_input_rmw_correct = wdatap_rmw_correct;
+        end
+    end
+    
+    generate
+        genvar i_drate;
+        for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
+        begin : encoder_input_dm_mux_per_dm_drate
+            
+          wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
+          wire 																	 int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
+          reg [CFG_LOCAL_DM_PER_WORD_WIDTH + CFG_ECC_DM_PER_WORD_WIDTH - 1 : 0] int_encoder_input_dm_tmp;
+
+            always @ (*)
+            begin
+              if (cfg_enable_ecc)
+                begin
+                  if (int_encoder_input_dm_all_zeros)
+                    begin
+                      int_encoder_input_dm_tmp = { {CFG_ECC_DM_PER_WORD_WIDTH{1'b0}}, int_encoder_input_dm };
+                    end
+                  else
+                    begin
+                      int_encoder_input_dm_tmp = { {CFG_ECC_DM_PER_WORD_WIDTH{1'b1}}, int_encoder_input_dm };
+                    end
+                end
+              else
+                begin
+                  int_encoder_input_dm_tmp = { {CFG_ECC_DM_PER_WORD_WIDTH{1'b0}}, int_encoder_input_dm };
+                end
+              int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = int_encoder_input_dm_tmp[CFG_ECC_DM_PER_WORD_WIDTH-1:0];
+            end // always @ begin
+        end
+    endgenerate
+    
+    //----------------------------------------------------------------------------------------------------
+    // Read data & read data valid from AFI
+    //----------------------------------------------------------------------------------------------------
+    always @ (*)
+    begin
+        int_decoder_input_data = afi_rdata;
+    end
+    
+    always @ (*)
+    begin
+        int_decoder_input_data_valid = afi_rdata_valid [0];
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Input Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Output Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Write data & byte enable to AFI interface
+    //----------------------------------------------------------------------------------------------------
+    always @ (*)
+    begin
+        ecc_wdata = int_encoder_output_data;
+    end
+    
+    always @ (*)
+    begin
+        if (CFG_ECC_ENC_REG)
+        begin
+            ecc_dm = int_encoder_output_dm_r;
+        end
+        else
+        begin
+            ecc_dm = int_encoder_output_dm;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Read data to rdata_path
+    //----------------------------------------------------------------------------------------------------
+    always @ (*)
+    begin
+        ecc_rdata = int_decoder_output_data;
+    end
+    
+    always @ (*)
+    begin
+        ecc_rdata_valid = |int_decoder_output_data_valid;
+    end
+
+    //----------------------------------------------------------------------------------------------------
+    // ECC specific logic
+    //----------------------------------------------------------------------------------------------------
+
+    // Single bit error
+    always @ (*)
+    begin
+        if (cfg_enable_ecc)
+            ecc_sbe = int_sbe;
+        else
+            ecc_sbe = 0;
+    end
+    
+    // Double bit error
+    always @ (*)
+    begin
+        if (cfg_enable_ecc)
+            ecc_dbe = int_dbe;
+        else
+            ecc_dbe = 0;
+    end
+    
+    // ECC code
+    always @ (*)
+    begin
+        if (cfg_enable_ecc)
+            ecc_code = int_ecc_code;
+        else
+            ecc_code = 0;
+    end
+    
+    // Interrupt signal
+    always @ (*)
+    begin
+        ecc_interrupt = int_ecc_interrupt;
+    end
+
+    
+    //----------------------------------------------------------------------------------------------------
+    // MMR ECC specific logic
+    //----------------------------------------------------------------------------------------------------
+    // Single bit error
+    always @ (*)
+    begin
+        sts_sbe_error = int_sbe_error;
+    end
+    
+    // Double bit error
+    always @ (*)
+    begin
+        sts_dbe_error = int_dbe_error;
+    end
+    
+    // Single bit error count
+    always @ (*)
+    begin
+        sts_sbe_count = int_sbe_count;
+    end
+    
+    // Double bit error count
+    always @ (*)
+    begin
+        sts_dbe_count = int_dbe_count;
+    end
+    
+    // Error address
+    always @ (*)
+    begin
+        sts_err_addr = int_err_addr;
+    end
+    
+    // Correctable Error dropped
+    always @ (*)
+    begin
+        sts_corr_dropped = int_corr_dropped;
+    end
+    
+    // Single bit error count
+    always @ (*)
+    begin
+        sts_corr_dropped_count = int_corr_dropped_count;
+    end
+    
+    // Correctable Error dropped address
+    always @ (*)
+    begin
+        sts_corr_dropped_addr = int_corr_dropped_addr;
+    end
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Output Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Encoder / Decoder Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Encoder
+    //----------------------------------------------------------------------------------------------------
+    generate
+        genvar m_drate;
+        for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
+        begin : encoder_inst_per_drate
+          wire [CFG_ENCODER_DATA_WIDTH + CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0] input_data_tmp               = {{CFG_ENCODER_DATA_WIDTH{1'b0}}, int_encoder_input_data             [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0]  input_data               = input_data_tmp[CFG_ENCODER_DATA_WIDTH - 1 : 0];
+
+          wire [CFG_ENCODER_DATA_WIDTH + CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0]  input_rmw_partial_data_tmp   = {{CFG_ENCODER_DATA_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0]  input_rmw_partial_data   = input_rmw_partial_data_tmp[ CFG_ENCODER_DATA_WIDTH - 1 : 0 ];
+
+          wire [CFG_ENCODER_DATA_WIDTH + CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0] 	input_rmw_correct_data_tmp   = {{CFG_ENCODER_DATA_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0]  input_rmw_correct_data   = input_rmw_correct_data_tmp[ CFG_ENCODER_DATA_WIDTH - 1 : 0 ];
+
+          wire [CFG_ECC_CODE_WIDTH     - 1 : 0] 	input_ecc_code           = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
+          wire 																		input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] 	output_data;
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] 	output_rmw_partial_data;
+          wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] 	output_rmw_correct_data;
+            
+            always @ (*)
+            begin
+                if (int_encoder_input_rmw_partial)
+                begin
+                    int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
+                end
+                else if (int_encoder_input_rmw_correct)
+                begin
+                    int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
+                end
+                else
+                begin
+                    int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data             [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data             [1 : 0] ^ inject_data_error [1 : 0])};
+                end
+            end
+            
+            alt_mem_ddrx_ecc_encoder #
+            (
+                .CFG_DATA_WIDTH             (CFG_ENCODER_DATA_WIDTH     ),
+                .CFG_ECC_CODE_WIDTH         (CFG_ECC_CODE_WIDTH         ),
+                .CFG_ECC_ENC_REG            (CFG_ECC_ENC_REG            ),
+                .CFG_MMR_DRAM_DATA_WIDTH    (CFG_MMR_DRAM_DATA_WIDTH    ),
+                .CFG_MMR_LOCAL_DATA_WIDTH   (CFG_MMR_LOCAL_DATA_WIDTH   ),
+                .CFG_PORT_WIDTH_ENABLE_ECC  (CFG_PORT_WIDTH_ENABLE_ECC  )
+            )
+            encoder_inst
+            (
+                .ctl_clk                    (ctl_clk                    ),
+                .ctl_reset_n                (ctl_reset_n                ),
+                .cfg_local_data_width       (cfg_local_data_width       ),
+                .cfg_dram_data_width        (cfg_dram_data_width        ),
+                .cfg_enable_ecc             (cfg_enable_ecc             ),
+                .input_data                 (input_data                 ),
+                .input_ecc_code             (input_ecc_code             ),
+                .input_ecc_code_overwrite   (1'b0                       ),  // ECC code overwrite feature is only needed during RMW correct phase
+                .output_data                (output_data                )
+            );
+            
+            alt_mem_ddrx_ecc_encoder #
+            (
+                .CFG_DATA_WIDTH             (CFG_ENCODER_DATA_WIDTH     ),
+                .CFG_ECC_CODE_WIDTH         (CFG_ECC_CODE_WIDTH         ),
+                .CFG_ECC_ENC_REG            (CFG_ECC_ENC_REG            ),
+                .CFG_MMR_DRAM_DATA_WIDTH    (CFG_MMR_DRAM_DATA_WIDTH    ),
+                .CFG_MMR_LOCAL_DATA_WIDTH   (CFG_MMR_LOCAL_DATA_WIDTH   ),
+                .CFG_PORT_WIDTH_ENABLE_ECC  (CFG_PORT_WIDTH_ENABLE_ECC  )
+            )
+            rmw_partial_encoder_inst
+            (
+                .ctl_clk                    (ctl_clk                    ),
+                .ctl_reset_n                (ctl_reset_n                ),
+                .cfg_local_data_width       (cfg_local_data_width       ),
+                .cfg_dram_data_width        (cfg_dram_data_width        ),
+                .cfg_enable_ecc             (cfg_enable_ecc             ),
+                .input_data                 (input_rmw_partial_data     ),
+                .input_ecc_code             (input_ecc_code             ),
+                .input_ecc_code_overwrite   (1'b0                       ),  // ECC code overwrite feature is only needed during RMW correct phase
+                .output_data                (output_rmw_partial_data    )
+            );
+            
+            alt_mem_ddrx_ecc_encoder #
+            (
+                .CFG_DATA_WIDTH             (CFG_ENCODER_DATA_WIDTH     ),
+                .CFG_ECC_CODE_WIDTH         (CFG_ECC_CODE_WIDTH         ),
+                .CFG_ECC_ENC_REG            (CFG_ECC_ENC_REG            ),
+                .CFG_MMR_DRAM_DATA_WIDTH    (CFG_MMR_DRAM_DATA_WIDTH    ),
+                .CFG_MMR_LOCAL_DATA_WIDTH   (CFG_MMR_LOCAL_DATA_WIDTH   ),
+                .CFG_PORT_WIDTH_ENABLE_ECC  (CFG_PORT_WIDTH_ENABLE_ECC  )
+            )
+            rmw_correct_encoder_inst
+            (
+                .ctl_clk                    (ctl_clk                    ),
+                .ctl_reset_n                (ctl_reset_n                ),
+                .cfg_local_data_width       (cfg_local_data_width       ),
+                .cfg_dram_data_width        (cfg_dram_data_width        ),
+                .cfg_enable_ecc             (cfg_enable_ecc             ),
+                .input_data                 (input_rmw_correct_data     ),
+                .input_ecc_code             (input_ecc_code             ),
+                .input_ecc_code_overwrite   (input_ecc_code_overwrite   ),
+                .output_data                (output_rmw_correct_data    )
+            );
+        end
+    endgenerate
+    
+    //----------------------------------------------------------------------------------------------------
+    // Decoder
+    //----------------------------------------------------------------------------------------------------
+    generate
+        genvar n_drate;
+        for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
+        begin : decoder_inst_per_drate
+            wire err_corrected;
+            wire err_detected;
+            wire err_fatal;
+            wire err_sbe;
+            
+            wire [CFG_DECODER_DATA_WIDTH + CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 0] input_data_tmp  = {{CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
+            wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data  = input_data_tmp[ CFG_DECODER_DATA_WIDTH - 1 : 0 ];
+            wire                                  input_data_valid = int_decoder_input_data_valid;
+            wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
+            wire                                  output_data_valid;
+            wire [CFG_ECC_CODE_WIDTH     - 1 : 0] output_ecc_code;
+            
+            assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
+            assign int_ecc_code            [(n_drate + 1) * CFG_ECC_CODE_WIDTH            - 1 : n_drate * CFG_ECC_CODE_WIDTH           ] = output_ecc_code;
+            assign int_decoder_output_data_valid [n_drate] = output_data_valid;
+            
+            alt_mem_ddrx_ecc_decoder #
+            (
+                .CFG_DATA_WIDTH                (CFG_DECODER_DATA_WIDTH        ),
+                .CFG_ECC_CODE_WIDTH            (CFG_ECC_CODE_WIDTH            ),
+                .CFG_ECC_DEC_REG               (CFG_ECC_DEC_REG               ),
+				.CFG_ECC_DECODER_REG           (CFG_ECC_DECODER_REG           ),
+                .CFG_ECC_RDATA_REG             (CFG_ECC_RDATA_REG             ),
+                .CFG_MMR_DRAM_DATA_WIDTH       (CFG_MMR_DRAM_DATA_WIDTH       ),
+                .CFG_MMR_LOCAL_DATA_WIDTH      (CFG_MMR_LOCAL_DATA_WIDTH      ),
+                .CFG_PORT_WIDTH_ENABLE_ECC     (CFG_PORT_WIDTH_ENABLE_ECC     )
+            )
+            decoder_inst
+            (
+                .ctl_clk                       (ctl_clk                       ),
+                .ctl_reset_n                   (ctl_reset_n                   ),
+                .cfg_local_data_width          (cfg_local_data_width          ),
+                .cfg_dram_data_width           (cfg_dram_data_width           ),
+                .cfg_enable_ecc                (cfg_enable_ecc                ),
+                .input_data                    (input_data                    ),
+                .input_data_valid              (input_data_valid              ),
+                .output_data                   (output_data                   ),
+                .output_data_valid             (output_data_valid             ),
+                .output_ecc_code               (output_ecc_code               ),
+                .err_corrected                 (err_corrected                 ),
+                .err_detected                  (err_detected                  ),
+                .err_fatal                     (err_fatal                     ),
+                .err_sbe                       (err_sbe                       )
+            );
+            
+            // Error detection
+			/*
+            always @ (*)
+            begin
+                if (err_detected || err_sbe)
+                begin
+                    if (err_corrected || err_sbe)
+                    begin
+                        int_sbe [n_drate] = 1'b1;
+                        int_dbe [n_drate] = 1'b0;
+                    end
+                    else if (err_fatal)
+                    begin
+                        int_sbe [n_drate] = 1'b0;
+                        int_dbe [n_drate] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_sbe [n_drate] = 1'b0;
+                        int_dbe [n_drate] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    int_sbe [n_drate] = 1'b0;
+                    int_dbe [n_drate] = 1'b0;
+                end
+            end
+			*/
+			always @ (*)
+			begin
+				int_sbe [n_drate] = err_corrected | err_sbe;
+				int_dbe [n_drate] = err_fatal;				
+			end
+        end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Encoder / Decoder Instantiation
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] ECC Specific Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    //----------------------------------------------------------------------------------------------------
+    // Common Logic
+    //----------------------------------------------------------------------------------------------------
+
+    // Below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
+    // - int_sbe_detected
+    // - int_dbe_detected
+    // - int_be_detected
+    // - int_corr_dropped_detected
+    // - rdatap_rcvd_addr
+    //
+    //  see SPR:362993
+
+    always @ (*)
+    begin
+        int_sbe_valid               = |int_sbe & ecc_rdata_valid;
+        int_dbe_valid               = |int_dbe & ecc_rdata_valid;
+        int_sbe_detected            = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
+        int_dbe_detected            = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
+        int_corr_dropped_detected   = rdatap_rcvd_corr_dropped;
+    end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (~ctl_reset_n)
+        begin
+            int_sbe_valid_r     <= 0;
+            int_dbe_valid_r     <= 0;
+
+            int_sbe_store       <= 0;
+            int_dbe_store       <= 0;
+        end
+        else
+        begin
+
+            int_sbe_valid_r     <= int_sbe_valid;
+            int_dbe_valid_r     <= int_dbe_valid;
+
+            int_sbe_store       <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
+            int_dbe_store       <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Error Innjection Logic
+    //----------------------------------------------------------------------------------------------------
+    // Data error injection, this will cause output data to be injected with single/double bit error
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            inject_data_error <= 0;
+        end
+        else
+        begin
+            // Put DBE 1st so that when user sets both gen_sbe and gen_dbe, DBE will have higher priority
+            if (cfg_gen_dbe)
+                inject_data_error <= 2'b11;
+            else if (cfg_gen_sbe)
+                inject_data_error <= 2'b01;
+            else
+                inject_data_error <= 2'b00;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Single bit error
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_sbe_error <= 1'b0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (int_sbe_detected)
+                    int_sbe_error <= 1'b1;
+                else if (cfg_clr_intr)
+                    int_sbe_error <= 1'b0;
+            end
+            else
+            begin
+                int_sbe_error <= 1'b0;
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Single bit error count
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_sbe_count <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (cfg_clr_intr)
+                    if (int_sbe_detected)
+                        int_sbe_count <= 1;
+                    else
+                        int_sbe_count <= 0;
+                else if (int_sbe_detected)
+                    int_sbe_count <= int_sbe_count + 1'b1;
+            end
+            else
+            begin
+                int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Double bit error
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_dbe_error <= 1'b0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (int_dbe_detected)
+                    int_dbe_error <= 1'b1;
+                else if (cfg_clr_intr)
+                    int_dbe_error <= 1'b0;
+            end
+            else
+            begin
+                int_dbe_error <= 1'b0;
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Double bit error count
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_dbe_count <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (cfg_clr_intr)
+                    if (int_dbe_detected)
+                        int_dbe_count <= 1;
+                    else
+                        int_dbe_count <= 0;
+                else if (int_dbe_detected)
+                    int_dbe_count <= int_dbe_count + 1'b1;
+            end
+            else
+            begin
+                int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Error address
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_err_addr <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (int_be_detected)
+                    int_err_addr <= rdatap_rcvd_addr;
+                else if (cfg_clr_intr)
+                    int_err_addr <= 0;
+            end
+            else
+            begin
+                int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
+            end
+        end
+    end
+
+    //----------------------------------------------------------------------------------------------------
+    // Dropped Correctable Error
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_corr_dropped <= 1'b0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (int_corr_dropped_detected)
+                    int_corr_dropped <= 1'b1;
+                else if (cfg_clr_intr)
+                    int_corr_dropped <= 1'b0;
+            end
+            else
+            begin
+                int_corr_dropped <= 1'b0;
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Dropped Correctable Error count
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_corr_dropped_count <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (cfg_clr_intr)
+                    if (int_corr_dropped_detected)
+                        int_corr_dropped_count <= 1;
+                    else
+                        int_corr_dropped_count <= 0;
+                else if (int_corr_dropped_detected)
+                    int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
+            end
+            else
+            begin
+                int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
+            end
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Dropped Correctable Error address
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_corr_dropped_addr <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                if (int_corr_dropped_detected)
+                    int_corr_dropped_addr <= rdatap_rcvd_addr;
+                else if (cfg_clr_intr)
+                    int_corr_dropped_addr <= 0;
+            end
+            else
+            begin
+                int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
+            end
+        end
+    end
+
+
+    //----------------------------------------------------------------------------------------------------
+    // Interrupt logic
+    //----------------------------------------------------------------------------------------------------
+
+    assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
+    assign int_be_detected = int_sbe_detected | int_dbe_detected;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_ecc_interrupt <= 1'b0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc && cfg_enable_intr)
+            begin
+                if (int_interruptable_error_detected)
+                    int_ecc_interrupt <= 1'b1;
+                else if (cfg_clr_intr)
+                    int_ecc_interrupt <= 1'b0;
+            end
+            else
+            begin
+                int_ecc_interrupt <= 1'b0;
+            end
+        end
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] ECC Specific Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v
new file mode 100644
index 0000000..25e018c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v
@@ -0,0 +1,239 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* message_disable = "14320" *) module alt_mem_ddrx_fifo
+# (
+    parameter
+        CTL_FIFO_DATA_WIDTH              =    8,
+        CTL_FIFO_ADDR_WIDTH              =    3
+)
+(
+    // general
+    ctl_clk,
+    ctl_reset_n,
+
+    // pop free fifo entry
+    get_valid,
+    get_ready,
+    get_data,   
+
+    // push free fifo entry
+    put_valid,
+    put_ready,
+    put_data   
+
+);
+
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+
+    localparam CTL_FIFO_DEPTH              = (2 ** CTL_FIFO_ADDR_WIDTH);
+    localparam CTL_FIFO_TYPE               = "SCFIFO";                      // SCFIFO, CUSTOM
+
+
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input                               ctl_clk;
+    input                               ctl_reset_n;
+
+    // pop free fifo entry
+    input                               get_ready;
+    output                              get_valid;
+    output [CTL_FIFO_DATA_WIDTH-1:0]    get_data;   
+
+    // push free fifo entry
+    output                              put_ready;
+    input                               put_valid;
+    input  [CTL_FIFO_DATA_WIDTH-1:0]    put_data;
+
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    wire                                get_valid;
+    wire                                get_ready;
+    wire [CTL_FIFO_DATA_WIDTH-1:0]      get_data;   
+
+    wire                                put_valid;
+    wire                                put_ready;
+    wire [CTL_FIFO_DATA_WIDTH-1:0]      put_data;
+
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    reg [CTL_FIFO_DATA_WIDTH-1:0]       fifo          [CTL_FIFO_DEPTH-1:0];
+    reg [CTL_FIFO_DEPTH-1:0]            fifo_v;
+
+    wire                                fifo_get;
+    wire                                fifo_put;
+    wire                                fifo_empty;
+    wire                                fifo_full;
+
+    wire zero;
+
+
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    assign fifo_get = get_valid & get_ready;
+    assign fifo_put = put_valid & put_ready;
+    assign zero = 1'b0;
+
+
+    generate
+    begin : gen_fifo_instance
+        if (CTL_FIFO_TYPE == "SCFIFO")
+        begin
+
+            assign get_valid = ~fifo_empty;
+            assign put_ready = ~fifo_full;
+
+            scfifo	#(
+                .add_ram_output_register    ( "ON"                  ),
+                .intended_device_family     ( "Stratix IV"          ),
+                .lpm_numwords               ( CTL_FIFO_DEPTH        ),
+                .lpm_showahead              ( "ON"                  ),
+                .lpm_type                   ( "scfifo"              ),
+                .lpm_width                  ( CTL_FIFO_DATA_WIDTH   ),
+                .lpm_widthu                 ( CTL_FIFO_ADDR_WIDTH   ),
+                .overflow_checking          ( "OFF"                 ),
+                .underflow_checking         ( "OFF"                 ),
+                .use_eab                    ( "ON"                  )
+            ) scfifo_component (
+                .aclr                       (~ctl_reset_n),
+                .clock                      (ctl_clk),
+                .data                       (put_data),
+                .rdreq                      (fifo_get),
+                .wrreq                      (fifo_put),
+                .empty                      (fifo_empty),
+                .full                       (fifo_full),
+                .q                          (get_data),
+                .almost_empty               (),
+                .almost_full                (),
+                .sclr                       (zero),
+                .usedw                      ()
+            );
+
+
+        end
+        else // CTL_FIFO_TYPE == "CUSTOM"
+        begin
+
+            assign get_valid = fifo_v[0];
+            assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
+            assign get_data  = fifo[0];
+
+
+                // put & get management
+                integer i; 
+                always @ (posedge ctl_clk or negedge ctl_reset_n) 
+                begin
+                    if (~ctl_reset_n)
+                    begin
+                        for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
+                        begin
+                            // initialize every entry
+                            fifo           [i]     <= 0;
+                            fifo_v         [i]     <= 1'b0;
+
+                        end
+                    end
+                    else
+                    begin
+                        // get request code must be above put request code
+                        if (fifo_get)
+                        begin
+                            // on a get request, fifo entry is shifted to move next entry to head
+                            for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
+                            begin
+                                fifo_v     [i-1]   <=  fifo_v [i];
+                                fifo       [i-1]   <=  fifo   [i];
+                            end
+
+                                fifo_v     [CTL_FIFO_DEPTH-1]   <=  0;
+                        end
+
+                        if (fifo_put)
+                        begin
+                            // on a put request, next empty fifo entry is written
+                            
+                            if (~fifo_get)
+                            begin
+                                // put request only
+                                for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
+                                begin
+                                    if ( fifo_v[i-1] & ~fifo_v[i])
+                                    begin
+                                        fifo_v     [i]   <=  1'b1;
+                                        fifo       [i]   <=  put_data;
+                                    end
+                                end
+                                if (~fifo_v[0])
+                                begin
+                                    fifo_v     [0]   <=  1'b1;
+                                    fifo       [0]   <=  put_data;
+                                end
+                            end
+                            else
+                            begin
+                                // put & get request on same cycle
+                                for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
+                                begin
+                                    if ( fifo_v[i-1] & ~fifo_v[i])
+                                    begin
+                                        fifo_v     [i-1]   <=  1'b1;
+                                        fifo       [i-1]   <=  put_data;
+                                    end
+                                end
+                                if (~fifo_v[0])
+                                begin
+                                    $display("error - fifo underflow");
+                                end
+                            end
+
+                        end
+
+                    end
+                end
+        end
+    end
+    endgenerate
+
+
+
+
+
+
+
+
+
+endmodule
+
+//
+// ASSERT
+//
+// fifo underflow
+//
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v
new file mode 100644
index 0000000..5d010cd
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v
@@ -0,0 +1,315 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_input_if 
+    #(parameter 
+    CFG_LOCAL_DATA_WIDTH    = 64,
+    CFG_LOCAL_ID_WIDTH      = 8,
+    CFG_LOCAL_ADDR_WIDTH    = 33,
+    CFG_LOCAL_SIZE_WIDTH    = 3,
+    CFG_MEM_IF_CHIP         = 1,
+    CFG_AFI_INTF_PHASE_NUM  = 2,
+    CFG_CTL_ARBITER_TYPE    = "ROWCOL"
+    )
+    (
+        // cmd channel
+        itf_cmd_ready,
+        itf_cmd_valid,
+        itf_cmd,
+        itf_cmd_address,
+        itf_cmd_burstlen,
+        itf_cmd_id,
+        itf_cmd_priority,
+        itf_cmd_autopercharge,
+        itf_cmd_multicast,
+    
+        // write data channel
+        itf_wr_data_ready,
+        itf_wr_data_valid,
+        itf_wr_data,
+        itf_wr_data_byte_en,
+        itf_wr_data_begin,
+        itf_wr_data_last,
+        itf_wr_data_id,
+        
+        // read data channel
+        itf_rd_data_ready,
+        itf_rd_data_valid,
+        itf_rd_data,
+        itf_rd_data_error,
+        itf_rd_data_begin,
+        itf_rd_data_last,
+        itf_rd_data_id,
+        itf_rd_data_id_early,
+        itf_rd_data_id_early_valid,
+
+        // command generator
+        cmd_gen_full,
+        cmd_valid,
+        cmd_address,
+        cmd_write,
+        cmd_read,
+        cmd_multicast,
+        cmd_size,
+        cmd_priority,
+        cmd_autoprecharge,
+        cmd_id,
+        
+        // write data path
+        wr_data_mem_full,
+        write_data_id,
+        write_data,
+        byte_en,
+        write_data_valid,
+        
+        // read data path
+        read_data,
+        read_data_valid,
+        read_data_error,
+        read_data_localid,
+        read_data_begin,
+        read_data_last, 
+        
+        //side band
+        local_refresh_req,
+        local_refresh_chip,
+        local_zqcal_req,
+        local_deep_powerdn_req,
+        local_deep_powerdn_chip,
+        local_self_rfsh_req,
+        local_self_rfsh_chip,
+        local_refresh_ack,
+        local_deep_powerdn_ack,
+        local_power_down_ack,
+        local_self_rfsh_ack,
+        local_init_done,
+        
+        bg_do_read,
+        bg_do_rmw_correct,
+        bg_do_rmw_partial,
+        bg_localid,
+        rfsh_req,
+        rfsh_chip,
+        zqcal_req,
+        deep_powerdn_req,
+        deep_powerdn_chip,
+        self_rfsh_req,
+        self_rfsh_chip,
+        rfsh_ack,
+        deep_powerdn_ack,
+        power_down_ack,
+        self_rfsh_ack,
+        init_done
+    
+    );
+
+    localparam AFI_INTF_LOW_PHASE  = 0;
+    localparam AFI_INTF_HIGH_PHASE = 1;
+
+    // command channel
+    output  itf_cmd_ready;
+    input   [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
+    input   itf_cmd_valid;
+    input   itf_cmd;
+    input   [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
+    input   [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
+    input   itf_cmd_priority;
+    input   itf_cmd_autopercharge;
+    input   itf_cmd_multicast;
+    
+    // write data channel
+    output  itf_wr_data_ready;
+    input   itf_wr_data_valid;
+    input   [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
+    input   [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
+    input   itf_wr_data_begin;
+    input   itf_wr_data_last;
+    input   [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
+        
+    // read data channel
+    input   itf_rd_data_ready;
+    output  itf_rd_data_valid;
+    output  [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
+    output  itf_rd_data_error;
+    output  itf_rd_data_begin;
+    output  itf_rd_data_last;
+    output  [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
+    output  [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
+    output                           itf_rd_data_id_early_valid;
+    
+    // command generator
+    input   cmd_gen_full;
+    output  cmd_valid;
+    output  [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
+    output  cmd_write;
+    output  cmd_read;
+    output  cmd_multicast;
+    output  [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
+    output  cmd_priority;
+    output  cmd_autoprecharge;
+    output  [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
+
+    // write data path
+    output  [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
+    output  [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
+    output  write_data_valid;
+    input   wr_data_mem_full;
+    output  [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
+
+    // read data path
+    input   [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
+    input   read_data_valid;
+    input   read_data_error;
+    input   [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
+    input   read_data_begin;
+    input   read_data_last;
+        
+    //side band
+    input   local_refresh_req;
+    input   [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
+    input   local_zqcal_req;
+    input   local_deep_powerdn_req;
+    input   [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
+    input   local_self_rfsh_req;
+    input   [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
+    output  local_refresh_ack;
+    output  local_deep_powerdn_ack;
+    output  local_power_down_ack;
+    output  local_self_rfsh_ack;
+    output  local_init_done;
+    
+    //side band
+    input   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
+    input   [CFG_LOCAL_ID_WIDTH     - 1 : 0] bg_localid;
+    input   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
+    input   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
+    output  rfsh_req;
+    output  [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
+    output  zqcal_req;
+    output  deep_powerdn_req;
+    output  [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
+    output  self_rfsh_req;
+    output  [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
+    input   rfsh_ack;
+    input   deep_powerdn_ack;
+    input   power_down_ack;
+    input   self_rfsh_ack;
+    input   init_done;
+        
+    // command generator
+    wire    cmd_priority;
+    wire    [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
+    wire    cmd_read;
+    wire    cmd_write;
+    wire    cmd_multicast;
+    wire    cmd_gen_full;
+    wire    cmd_valid;
+    wire    itf_cmd_ready;
+    wire    cmd_autoprecharge;
+    wire    [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
+    
+    //side band
+    wire   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
+    wire   [CFG_LOCAL_ID_WIDTH     - 1 : 0] bg_localid;
+    wire   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
+    wire   [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
+    wire rfsh_req;
+    wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
+    wire 					   zqcal_req;
+    wire deep_powerdn_req;
+    wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
+    wire    self_rfsh_req;
+    //wire  rfsh_ack;
+    //wire  deep_powerdn_ack;
+    wire    power_down_ack;
+    //wire  self_rfsh_ack;
+    // wire init_done;
+    
+    //write data path
+    wire    itf_wr_data_ready;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
+    wire    write_data_valid;
+    wire    [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0] write_data_id; 
+    
+    //read data path
+    wire    itf_rd_data_valid;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
+    wire    itf_rd_data_error;
+    wire    itf_rd_data_begin;
+    wire    itf_rd_data_last;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
+    wire    itf_rd_data_id_early_valid;
+    
+    // commmand generator
+    assign cmd_priority                 = itf_cmd_priority;
+    assign cmd_address                  = itf_cmd_address;
+    assign cmd_multicast                = itf_cmd_multicast;
+    assign cmd_size                     = itf_cmd_burstlen;
+    assign cmd_autoprecharge            = itf_cmd_autopercharge;
+    assign cmd_id                       = itf_cmd_id;
+    
+    // side band    
+    assign rfsh_req                     = local_refresh_req;
+    assign rfsh_chip                    = local_refresh_chip;
+    assign zqcal_req                    = local_zqcal_req;
+    assign deep_powerdn_req             = local_deep_powerdn_req;
+    assign deep_powerdn_chip            = local_deep_powerdn_chip;
+    assign self_rfsh_req                = local_self_rfsh_req;
+    assign self_rfsh_chip               = local_self_rfsh_chip;
+    assign local_refresh_ack            = rfsh_ack;
+    assign local_deep_powerdn_ack       = deep_powerdn_ack;
+    assign local_power_down_ack         = power_down_ack;
+    assign local_self_rfsh_ack          = self_rfsh_ack;
+    assign local_init_done              = init_done;
+    
+    //write data path
+    assign write_data                   = itf_wr_data;
+    assign byte_en                      = itf_wr_data_byte_en;
+    assign write_data_valid             = itf_wr_data_valid;
+    assign write_data_id                = itf_wr_data_id;
+    
+    // read data path
+    assign itf_rd_data_id               = read_data_localid;
+    assign itf_rd_data_error            = read_data_error;
+    assign itf_rd_data_valid            = read_data_valid;
+    assign itf_rd_data_begin            = read_data_begin;
+    assign itf_rd_data_last             = read_data_last;
+    assign itf_rd_data                  = read_data;
+    assign itf_rd_data_id_early         = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
+	
+	//==============================================================================
+	// Logic below is to tie low itf_cmd_ready, itf_cmd_valid and itf_wr_data_ready when local_init_done is low
+	assign itf_cmd_ready      = ~cmd_gen_full & local_init_done;
+	assign itf_wr_data_ready  = ~wr_data_mem_full & local_init_done;
+	assign cmd_read           = ~itf_cmd & itf_cmd_valid & local_init_done;
+    assign cmd_write          = itf_cmd & itf_cmd_valid & local_init_done;
+	assign cmd_valid          = itf_cmd_valid & local_init_done;
+
+    generate
+    begin : gen_rd_data_id_early_valid
+        if (CFG_CTL_ARBITER_TYPE == "COLROW")
+        begin
+            assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
+        end
+        else
+        begin
+            assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
+        end
+    end
+    endgenerate
+
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_list.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_list.v
new file mode 100644
index 0000000..03559e6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_list.v
@@ -0,0 +1,242 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_list
+# (
+    // module parameter port list
+    parameter
+        CTL_LIST_WIDTH              =    3,        // number of dram commands that can be tracked at a time
+        CTL_LIST_DEPTH              =    8,
+        CTL_LIST_INIT_VALUE_TYPE    =    "INCR",   // INCR, ZERO
+        CTL_LIST_INIT_VALID         =    "VALID"   // VALID, INVALID
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // pop free list
+    list_get_entry_valid,
+    list_get_entry_ready,
+    list_get_entry_id,   
+    list_get_entry_id_vector,
+
+    // push free list
+    list_put_entry_valid,
+    list_put_entry_ready,
+    list_put_entry_id   
+
+);
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input                               ctl_clk;
+    input                               ctl_reset_n;
+
+    // pop free list
+    input                               list_get_entry_ready;
+    output                              list_get_entry_valid;
+    output [CTL_LIST_WIDTH-1:0]         list_get_entry_id;
+    output [CTL_LIST_DEPTH-1:0]         list_get_entry_id_vector;
+
+    // push free list
+    output                              list_put_entry_ready;
+    input                               list_put_entry_valid;
+    input [CTL_LIST_WIDTH-1:0]          list_put_entry_id;
+
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    reg                                 list_get_entry_valid;
+    wire                                list_get_entry_ready;
+    reg  [CTL_LIST_WIDTH-1:0]           list_get_entry_id;   
+    reg  [CTL_LIST_DEPTH-1:0]           list_get_entry_id_vector;
+
+    wire                                list_put_entry_valid;
+    reg                                 list_put_entry_ready;
+    wire [CTL_LIST_WIDTH-1:0]           list_put_entry_id;
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    reg [CTL_LIST_WIDTH-1:0]            list          [CTL_LIST_DEPTH-1:0];
+    reg                                 list_v        [CTL_LIST_DEPTH-1:0];
+    reg [CTL_LIST_DEPTH-1:0]            list_vector;
+
+    wire                                list_get = list_get_entry_valid & list_get_entry_ready;
+    wire                                list_put = list_put_entry_valid & list_put_entry_ready;
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    // generate interface signals
+    always @ (*) 
+    begin
+        // connect interface signals to list head & tail
+        list_get_entry_valid     = list_v[0];
+        list_get_entry_id        = list[0];
+        list_get_entry_id_vector = list_vector;
+        list_put_entry_ready     = ~list_v[CTL_LIST_DEPTH-1];
+    end
+
+    // list put & get management
+    integer i; 
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
+            begin
+                // initialize every entry
+                if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
+                begin
+                    list           [i]     <= i;
+                end
+                else
+                begin
+                    list           [i]     <= {CTL_LIST_WIDTH{1'b0}};
+                end
+
+                if (CTL_LIST_INIT_VALID == "VALID")
+                begin
+                    list_v         [i]     <= 1'b1;
+                end
+                else
+                begin
+                    list_v         [i]     <= 1'b0;
+                end
+
+            end
+            
+            list_vector <= {CTL_LIST_DEPTH{1'b0}};
+        end
+        else
+        begin
+            // get request code must be above put request code
+            if (list_get)
+            begin
+                // on a get request, list is shifted to move next entry to head
+                for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
+                begin
+                    list_v     [i-1]   <=  list_v [i];
+                    list       [i-1]   <=  list   [i];
+                end
+
+                    list_v     [CTL_LIST_DEPTH-1]   <=  0;
+                
+                for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
+                begin
+                    if (i == list [1])
+                    begin
+                        list_vector [i] <= 1'b1;
+                    end
+                    else
+                    begin
+                        list_vector [i] <= 1'b0;
+                    end
+                end
+            end
+
+            if (list_put)
+            begin
+                // on a put request, next empty list entry is written
+                
+                if (~list_get)
+                begin
+                    // put request only
+                    for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
+                    begin
+                        if ( list_v[i-1] & ~list_v[i])
+                        begin
+                            list_v     [i]   <=  1'b1;
+                            list       [i]   <=  list_put_entry_id;
+                        end
+                    end
+                    if (~list_v[0])
+                    begin
+                        list_v     [0]   <=  1'b1;
+                        list       [0]   <=  list_put_entry_id;
+                        
+                        for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
+                        begin
+                            if (i == list_put_entry_id)
+                            begin
+                                list_vector [i] <= 1'b1;
+                            end
+                            else
+                            begin
+                                list_vector [i] <= 1'b0;
+                            end
+                        end
+                    end
+                end
+                else
+                begin
+                    // put & get request on same cycle
+                    for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
+                    begin
+                        if (list_v[i-1] & ~list_v[i])
+                        begin
+                            list_v     [i-1]   <=  1'b1;
+                            list       [i-1]   <=  list_put_entry_id;
+                        end
+                    end
+                    // if (~list_v[0])
+                    // begin
+                    //     $display("error - list underflow");
+                    // end
+                    
+                    for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
+                    begin
+                        if (list_v[0] & ~list_v[1])
+                        begin
+                            if (i == list_put_entry_id)
+                            begin
+                                list_vector [i] <= 1'b1;
+                            end
+                            else
+                            begin
+                                list_vector [i] <= 1'b0;
+                            end
+                        end
+                        else
+                        begin
+                            if (i == list [1])
+                            begin
+                                list_vector [i] <= 1'b1;
+                            end
+                            else
+                            begin
+                                list_vector [i] <= 1'b0;
+                            end
+                        end
+                    end
+                end
+
+            end
+
+        end
+    end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
new file mode 100644
index 0000000..f7e99b1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
@@ -0,0 +1,400 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Title         : LPDDR2 controller address and command decoder
+//
+// File          : alt_mem_ddrx_lpddr2_addr_cmd.v
+//
+// Abstract      : LPDDR2 Address and command decoder
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_lpddr2_addr_cmd
+    # (parameter
+    
+        // Global parameters
+        CFG_PORT_WIDTH_OUTPUT_REGD    = 1,
+        CFG_MEM_IF_CHIP               = 1,
+        CFG_MEM_IF_CKE_WIDTH          = 1,    // same width as CS_WIDTH
+        CFG_MEM_IF_ADDR_WIDTH         = 20,
+        CFG_MEM_IF_ROW_WIDTH          = 15,   // max supported row bits
+        CFG_MEM_IF_COL_WIDTH          = 12,   // max supported column bits  
+        CFG_MEM_IF_BA_WIDTH           = 3,    // max supported bank bits
+        CFG_DWIDTH_RATIO              = 2
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        ctl_cal_success,
+
+        //run-time configuration interface
+        cfg_output_regd,
+        cfg_enable_chipsel_for_sideband,
+
+        // AFI interface (Signals from Arbiter block)
+        do_write,
+        do_read,
+        do_auto_precharge,
+        do_activate,
+        do_precharge,
+        do_precharge_all,
+        do_refresh,
+        do_self_refresh,
+        do_power_down,
+        do_lmr,
+        
+        do_lmr_read,         //Currently does not exist in arbiter
+        do_refresh_1bank,     //Currently does not exist in arbiter
+        do_burst_terminate,     //Currently does not exist in arbiter
+        do_deep_pwrdwn,     //Currently does not exist in arbiter
+        
+        // address information
+        to_chip,                 // active high input (one hot)
+        to_bank,
+        to_row,
+        to_col,
+        to_lmr,
+        lmr_opcode,
+        
+        //output
+        afi_cke,
+        afi_cs_n,
+        afi_addr,
+        afi_rst_n
+    );
+    
+    input ctl_clk;
+    input ctl_reset_n;
+    input ctl_cal_success;
+
+    //run-time  configuration input
+    input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
+    input                                   cfg_enable_chipsel_for_sideband;
+
+    //  Arbiter command inputs
+    input do_write;
+    input do_read;
+    input do_auto_precharge;
+    input do_activate;
+    input do_precharge;
+
+    input [CFG_MEM_IF_CHIP-1:0]    do_precharge_all;
+    input [CFG_MEM_IF_CHIP-1:0]    do_refresh;
+    input [CFG_MEM_IF_CHIP-1:0]    do_self_refresh;
+    input [CFG_MEM_IF_CHIP-1:0]    do_power_down;
+    input [CFG_MEM_IF_CHIP-1:0]    do_deep_pwrdwn;
+
+
+    input do_lmr;
+
+    
+    input do_lmr_read;
+    input do_refresh_1bank;
+    input do_burst_terminate;
+    
+    input   [CFG_MEM_IF_CHIP-1:0]       to_chip;
+    input   [CFG_MEM_IF_BA_WIDTH-1:0]   to_bank;
+    input   [CFG_MEM_IF_ROW_WIDTH-1:0]  to_row;
+    input   [CFG_MEM_IF_COL_WIDTH-1:0]  to_col;
+    input   [7:0]                       to_lmr;
+    input   [7:0]                       lmr_opcode;
+    
+    //output
+    output  [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]   afi_cke;
+    output  [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]        afi_cs_n;
+    output  [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]  afi_addr;
+    output  [(CFG_DWIDTH_RATIO/2) - 1:0]                            afi_rst_n;
+    
+    wire do_write;
+    wire do_read;
+    wire do_auto_precharge;
+    wire do_activate;
+    wire do_precharge;
+
+    wire  [CFG_MEM_IF_CHIP-1:0]    do_precharge_all;
+    wire  [CFG_MEM_IF_CHIP-1:0]    do_refresh;
+    wire  [CFG_MEM_IF_CHIP-1:0]    do_self_refresh;
+    wire  [CFG_MEM_IF_CHIP-1:0]    do_power_down;
+    wire  [CFG_MEM_IF_CHIP-1:0]    do_deep_pwrdwn;
+
+    wire do_lmr;
+
+    wire do_lmr_read;
+    wire do_refresh_1bank;
+    wire do_burst_terminate;
+    
+    reg   [2:0]    temp_bank_addr;
+    reg   [14:0]   temp_row_addr;
+    reg   [11:0]   temp_col_addr;
+
+    
+    wire    [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]   afi_cke;
+    wire    [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0]        afi_cs_n;
+    wire    [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0]  afi_addr;
+    wire    [(CFG_DWIDTH_RATIO/2) - 1:0]                            afi_rst_n;
+    
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]      int_cke;
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]      int_cke_r;
+    reg [(CFG_MEM_IF_CHIP) - 1:0]           int_cs_n;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]     int_addr;
+    
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]      combi_cke;
+    reg [(CFG_MEM_IF_CHIP) - 1:0]           combi_cs_n;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]     combi_addr;
+    reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0]      combi_cke_r;
+    reg [(CFG_MEM_IF_CHIP) - 1:0]           combi_cs_n_r;
+    reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0]     combi_addr_r;
+    
+    reg   [CFG_MEM_IF_CHIP - 1:0]           do_power_down_r;
+    reg   [CFG_MEM_IF_CHIP - 1:0]           do_self_refresh_r;
+    reg   [CFG_MEM_IF_CHIP - 1:0]           do_deep_pwrdwn_r;
+    reg   [CFG_MEM_IF_CHIP - 1:0]           int_do_power_down;
+    reg   [CFG_MEM_IF_CHIP - 1:0]           int_do_self_refresh;
+    reg   [CFG_MEM_IF_CHIP - 1:0]           int_do_deep_pwrdwn;
+    
+    assign afi_rst_n    = {(CFG_DWIDTH_RATIO/2){1'b1}};
+    
+    
+    generate
+        if (CFG_DWIDTH_RATIO == 2) begin
+            assign afi_cke      = int_cke;
+            assign afi_cs_n     = int_cs_n;
+            assign afi_addr     = int_addr;
+        end
+        else begin
+            assign afi_cke      = {int_cke,int_cke};
+            assign afi_cs_n     = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
+            assign afi_addr     = {int_addr,int_addr};
+        end        
+    endgenerate
+    
+// need half rate code to adjust for half rate cke or cs
+   
+    always @(posedge ctl_clk, negedge ctl_reset_n)            // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
+        begin
+            if (!ctl_reset_n)
+                begin
+                    do_power_down_r   <= {(CFG_MEM_IF_CHIP){1'b0}};
+                    do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
+                    do_deep_pwrdwn_r  <= {(CFG_MEM_IF_CHIP){1'b0}};
+                end
+            else
+                begin
+                    do_power_down_r   <= ~do_power_down;
+                    do_self_refresh_r <= ~do_self_refresh;
+                    do_deep_pwrdwn_r  <= ~do_deep_pwrdwn;
+                end
+        end
+    
+    always @(*)
+        begin
+            int_do_power_down   = do_power_down   & do_power_down_r;
+            int_do_self_refresh = do_self_refresh & do_self_refresh_r;
+            int_do_deep_pwrdwn  = do_deep_pwrdwn  & do_deep_pwrdwn_r;
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            combi_cke_r   <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
+            combi_cs_n_r  <= {CFG_MEM_IF_CHIP{1'b1}}  ;
+            combi_addr_r  <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
+        end
+        else
+        begin
+            combi_cke_r   <= combi_cke  ;
+            combi_cs_n_r  <= combi_cs_n ;
+            combi_addr_r  <= combi_addr ;
+        end
+    end
+
+    always @(*)
+        begin
+            if (cfg_output_regd)
+                begin
+                    int_cke     =  combi_cke_r;
+                    int_cs_n    =  combi_cs_n_r;
+                    int_addr    =  combi_addr_r;
+                end
+            else
+                begin
+                    int_cke     =  combi_cke;
+                    int_cs_n    =  combi_cs_n;
+                    int_addr    =  combi_addr;
+                end
+        end
+    
+    
+    always @ (*) 
+    begin
+        temp_row_addr    = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
+        temp_col_addr    = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
+        temp_bank_addr   = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
+        temp_row_addr    = to_row ;
+        temp_col_addr    = to_col ;
+        temp_bank_addr   = to_bank;
+    end
+    
+    //CKE generation block
+    always @(*)
+        begin
+            if (ctl_cal_success)
+               begin 
+                    combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
+               end
+            else
+               begin
+                    combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
+               end
+        end
+    
+    
+    always @(*)
+        begin
+            if (ctl_cal_success)
+                begin
+                    combi_cs_n    =   {(CFG_MEM_IF_CHIP){1'b1}};
+                    combi_addr    =   {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                    
+                    if (|do_refresh)
+                        begin
+                            combi_cs_n                                          =  ~do_refresh;
+                            combi_addr[3:0]                                     =   4'b1100;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+
+                    if (do_refresh_1bank)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =   4'b0100;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+
+                    if (|do_precharge_all)
+                        begin
+                            combi_cs_n                                          = ~do_precharge_all;
+                            combi_addr[3:0]                                     =  4'b1011;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       = {temp_bank_addr,2'b00,(|do_precharge_all)};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+                   
+                    if (do_activate)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  {temp_row_addr[9:8],2'b10};
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {temp_bank_addr,temp_row_addr[12:10]};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {temp_row_addr[14:13],temp_row_addr[7:0]};
+                        end
+                    
+                    if (do_precharge)
+                        begin
+                            combi_cs_n                                          = ~to_chip;
+                            combi_addr[3:0]                                     = 4'b1011;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       = {temp_bank_addr,3'b000};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          = {temp_row_addr[14:13],temp_row_addr[7:0]};
+                        end
+                    
+                    if (do_write)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  4'b0001;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {temp_bank_addr,temp_col_addr[2:1],1'b0};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {temp_col_addr[11:3],do_auto_precharge};
+                        end
+                   
+                    if (do_read)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  4'b0101;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {temp_bank_addr,temp_col_addr[2:1],1'b0};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {temp_col_addr[11:3],do_auto_precharge};
+                        end
+                    
+                    if (|int_do_power_down)
+                        begin
+                            combi_cs_n                                          =  {(CFG_MEM_IF_CHIP){1'b1}};
+                            combi_addr[3:0]                                     =  4'b0000;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+                    
+                    if (|int_do_deep_pwrdwn)
+                        begin
+                            if (cfg_enable_chipsel_for_sideband)
+                                begin
+                                    combi_cs_n                                  = ~int_do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in deep power down;
+                                end
+                            else
+                                begin
+                                    combi_cs_n                                  =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                end
+                            
+                            combi_addr[3:0]                                     =  4'b0011;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+
+                    if (|int_do_self_refresh)
+                        begin
+                            if (cfg_enable_chipsel_for_sideband)
+                                begin
+                                    combi_cs_n                                  = ~int_do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in deep power down;
+                                end
+                            else
+                                begin
+                                    combi_cs_n                                  =  {(CFG_MEM_IF_CHIP){1'b1}};
+                                end
+                            
+                            combi_addr[3:0]                                     =  4'b0100;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+                   
+                    if (do_lmr)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  4'b0000;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  to_lmr[5:0];
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {to_lmr[7:6],lmr_opcode};
+                        end
+
+                    if (do_lmr_read)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  4'b1000;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  to_lmr[5:0];
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {to_lmr[7:6],{8{1'b0}}};
+                        end
+                   
+                    if (do_burst_terminate)
+                        begin
+                            combi_cs_n                                          =  ~to_chip;
+                            combi_addr[3:0]                                     =  4'b0011;
+                            combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4]       =  {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
+                            combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10]          =  {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
+                        end
+            
+                           
+                end
+            else
+                begin
+                    combi_cs_n                                                  =  {(CFG_MEM_IF_CHIP){1'b1}};
+                    combi_addr                                                  =  {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
+                end
+        end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v
new file mode 100644
index 0000000..40214cb
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v
@@ -0,0 +1,289 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Title         : alt_mem_ddrx_mm_st_converter
+//
+// File          : alt_mem_ddrx_mm_st_converter.v
+//
+// Abstract      : take in Avalon MM interface and convert it to single cmd and 
+//                 multiple data Avalon ST
+//
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_mm_st_converter # (
+    parameter
+        AVL_SIZE_WIDTH     = 3,
+        AVL_ADDR_WIDTH     = 25,
+        AVL_DATA_WIDTH     = 32,
+        LOCAL_ID_WIDTH     = 8,
+        CFG_DWIDTH_RATIO   = 4,
+        CFG_MM_ST_CONV_REG = 0
+    )
+    (
+        
+        ctl_clk, // controller clock
+        ctl_reset_n, // controller reset_n, synchronous to ctl_clk
+        
+        ctl_half_clk, // controller clock, half-rate 
+        ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk 
+        
+        // Avalon data slave interface
+        avl_ready, // Avalon wait_n
+        avl_read_req, // Avalon read 
+        avl_write_req, // Avalon write
+        avl_size, // Avalon burstcount
+        avl_burstbegin, // Avalon burstbegin
+        avl_addr, // Avalon address 
+        avl_rdata_valid, // Avalon readdata_valid
+        avl_rdata, // Avalon readdata
+        avl_wdata, // Avalon writedata
+        avl_be, // Avalon byteenble
+        
+        local_rdata_error, // Avalon readdata_error
+        local_multicast, // In-band multicast
+        local_autopch_req, // In-band auto-precharge request signal 
+        local_priority, // In-band priority signal
+        
+        // cmd channel
+        itf_cmd_ready,
+        itf_cmd_valid,
+        itf_cmd,
+        itf_cmd_address,
+        itf_cmd_burstlen,
+        itf_cmd_id,
+        itf_cmd_priority,
+        itf_cmd_autopercharge,
+        itf_cmd_multicast,
+    
+        // write data channel
+        itf_wr_data_ready,
+        itf_wr_data_valid,
+        itf_wr_data,
+        itf_wr_data_byte_en,
+        itf_wr_data_begin,
+        itf_wr_data_last,
+        itf_wr_data_id,
+        
+        // read data channel
+        itf_rd_data_ready,
+        itf_rd_data_valid,
+        itf_rd_data,
+        itf_rd_data_error,
+        itf_rd_data_begin,
+        itf_rd_data_last,
+        itf_rd_data_id
+);
+    localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
+    
+    input ctl_clk;
+    input ctl_reset_n;
+    
+    input ctl_half_clk;
+    input ctl_half_clk_reset_n;
+    
+    output                      avl_ready;
+    input                       avl_read_req;
+    input                       avl_write_req;
+    input  [AVL_SIZE_WIDTH-1:0] avl_size;
+    input                       avl_burstbegin;
+    input  [AVL_ADDR_WIDTH-1:0] avl_addr;
+    output                      avl_rdata_valid;
+    output [3:0]                local_rdata_error;
+    output [AVL_DATA_WIDTH-1:0] avl_rdata;
+    input  [AVL_DATA_WIDTH-1:0] avl_wdata;
+    input  [AVL_BE_WIDTH-1:0]   avl_be;
+    
+    input local_multicast;
+    input local_autopch_req;
+    input local_priority;
+    
+    input                       itf_cmd_ready;
+    output                      itf_cmd_valid;
+    output                      itf_cmd;
+    output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
+    output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
+    output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
+    output                      itf_cmd_priority;
+    output                      itf_cmd_autopercharge;
+    output                      itf_cmd_multicast;
+    
+    input                       itf_wr_data_ready;
+    output                      itf_wr_data_valid;
+    output [AVL_DATA_WIDTH-1:0] itf_wr_data;
+    output [AVL_BE_WIDTH-1:0]   itf_wr_data_byte_en;
+    output                      itf_wr_data_begin;
+    output                      itf_wr_data_last;
+    output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
+    
+    output                     itf_rd_data_ready;
+    input                      itf_rd_data_valid;
+    input [AVL_DATA_WIDTH-1:0] itf_rd_data;
+    input                      itf_rd_data_error;
+    input                      itf_rd_data_begin;
+    input                      itf_rd_data_last;
+    input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
+    
+    reg   [AVL_SIZE_WIDTH-1:0] burst_count;
+    
+    wire                       int_ready;
+    wire                       itf_cmd; // high is write
+    wire                       itf_wr_if_ready;
+    wire  [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
+    wire                       itf_wr_data_begin;
+    wire                       itf_wr_data_last;
+    wire  [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
+    reg                        data_pass;
+    reg   [AVL_SIZE_WIDTH-1:0] burst_counter;
+    
+    reg                          avl_read_req_reg;
+    reg                          avl_write_req_reg;
+    reg   [AVL_SIZE_WIDTH-1:0]   avl_size_reg;
+    reg   [AVL_ADDR_WIDTH-1:0]   avl_addr_reg;
+    reg   [AVL_DATA_WIDTH-1:0]   avl_wdata_reg;
+    reg   [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
+    
+    reg                          itf_rd_data_valid_reg;
+    reg   [AVL_DATA_WIDTH-1:0]   itf_rd_data_reg;
+    reg   [3:0]                  itf_rd_data_error_reg;
+    
+    reg                          local_multicast_reg;
+    reg                          local_autopch_req_reg;
+    reg                          local_priority_reg;
+    
+    generate
+        if (CFG_MM_ST_CONV_REG == 1)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    avl_read_req_reg            <= 1'b0;
+                    avl_write_req_reg           <= 1'b0;
+                    avl_size_reg                <= {AVL_SIZE_WIDTH{1'b0}};
+                    avl_addr_reg                <= {AVL_ADDR_WIDTH{1'b0}};
+                    avl_wdata_reg               <= {AVL_DATA_WIDTH{1'b0}};
+                    avl_be_reg                  <= {AVL_BE_WIDTH{1'b0}};
+                    itf_rd_data_valid_reg       <= 1'b0;
+                    itf_rd_data_reg             <= {AVL_DATA_WIDTH{1'b0}};
+                    itf_rd_data_error_reg       <= 4'b0;
+                    local_multicast_reg         <= 1'b0;
+                    local_autopch_req_reg       <= 1'b0;
+                    local_priority_reg          <= 1'b0;
+                end else
+                begin
+                    if (int_ready)
+                    begin
+                        avl_read_req_reg        <= avl_read_req;
+                        avl_write_req_reg       <= avl_write_req;
+                        avl_size_reg            <= avl_size;
+                        avl_addr_reg            <= avl_addr;
+                        avl_wdata_reg           <= avl_wdata;
+                        avl_be_reg              <= avl_be;
+                        local_multicast_reg     <= local_multicast;
+                        local_autopch_req_reg   <= local_autopch_req;
+                        local_priority_reg      <= local_priority;
+                    end
+                        itf_rd_data_valid_reg   <= itf_rd_data_valid;
+                        itf_rd_data_reg         <= itf_rd_data;
+                        itf_rd_data_error_reg   <= itf_rd_data_error;
+                end
+            end
+        end else 
+        begin
+            always @ (*)
+            begin
+                avl_read_req_reg            = avl_read_req;
+                avl_write_req_reg           = avl_write_req;
+                avl_size_reg                = avl_size;
+                avl_addr_reg                = avl_addr;
+                avl_wdata_reg               = avl_wdata;
+                avl_be_reg                  = avl_be;
+                itf_rd_data_valid_reg       = itf_rd_data_valid;
+                itf_rd_data_reg             = itf_rd_data;
+                itf_rd_data_error_reg       = {4{itf_rd_data_error}};
+                local_multicast_reg         = local_multicast;
+                local_autopch_req_reg       = local_autopch_req;
+                local_priority_reg          = local_priority;
+            end
+        end
+    endgenerate
+    
+    // when cmd_ready = 1'b1, avl_ready = 1'b1;
+    // when avl_write_req = 1'b1,
+    // take this write req and then then drive avl_ready until receive # of beats = avl_size? 
+    // we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
+    // when cmd_ready = 1'b1, avl_ready = 1'b1;
+    // when local_ready_req = 1'b1,
+    // take this read_req
+    // we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
+
+    assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
+
+    assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
+    
+    assign avl_ready = int_ready;
+    assign itf_rd_data_ready = 1'b1;
+    assign itf_cmd_address = avl_addr_reg ;
+    assign itf_cmd_burstlen = avl_size_reg ;
+    assign itf_cmd_autopercharge = local_autopch_req_reg ;
+    assign itf_cmd_priority = local_priority_reg ;
+    assign itf_cmd_multicast = local_multicast_reg ;
+    assign itf_cmd = avl_write_req_reg;
+
+    assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
+    assign itf_wr_data_begin = 1'b0;
+    assign itf_wr_data_last = 1'b0;
+    assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
+    
+    // write data channel
+    assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
+    assign itf_wr_data = avl_wdata_reg ;
+    assign itf_wr_data_byte_en = avl_be_reg ;
+             
+    // read data channel
+    assign avl_rdata_valid = itf_rd_data_valid_reg;
+    assign avl_rdata =  itf_rd_data_reg;
+    assign local_rdata_error = itf_rd_data_error_reg;
+    
+    assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                burst_counter  <=  {AVL_SIZE_WIDTH{1'b0}};
+            else
+                begin
+                    if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
+                        burst_counter   <=  avl_size_reg - 1'b1;
+                    else if (avl_write_req_reg && itf_wr_data_ready)
+                        burst_counter   <=  burst_counter - 1'b1;
+                end
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                data_pass  <=  1'b0;
+            else
+                begin
+                    if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
+                        data_pass  <=  1'b1;
+                    else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
+                        data_pass  <=  1'b0;
+                end
+        end
+        
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v
new file mode 100644
index 0000000..d548eab
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v
@@ -0,0 +1,297 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_odt_gen
+    #( parameter
+        CFG_DWIDTH_RATIO                = 2,
+        CFG_ODT_ENABLED                 = 1,
+        CFG_MEM_IF_CHIP                 = 2, //one_hot
+        CFG_MEM_IF_ODT_WIDTH            = 2,
+        CFG_PORT_WIDTH_OUTPUT_REGD      = 1,
+        CFG_PORT_WIDTH_CAS_WR_LAT       = 4,
+        CFG_PORT_WIDTH_TCL              = 4,
+        CFG_PORT_WIDTH_ADD_LAT          = 3,
+        CFG_PORT_WIDTH_TYPE             = 3,
+        CFG_PORT_WIDTH_WRITE_ODT_CHIP   = 4,
+        CFG_PORT_WIDTH_READ_ODT_CHIP    = 4
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        //Configuration Interface
+        cfg_type,
+        cfg_tcl,
+        cfg_cas_wr_lat,
+        cfg_add_lat,
+        cfg_write_odt_chip,
+        cfg_read_odt_chip,
+        cfg_burst_length,
+        cfg_output_regd,
+        
+        //Arbiter Interface
+        bg_do_read,
+        bg_do_write,
+        bg_do_burst_chop,
+        bg_to_chip, //one_hot
+        
+        //AFI Interface
+        afi_odt
+    );
+    
+    //=================================================================================================//
+    //        input/output declaration                                                                 //
+    //=================================================================================================//
+    
+    input                                                     ctl_clk;
+    input                                                     ctl_reset_n;
+    
+    //Input from Configuration Interface
+    
+    input   [CFG_PORT_WIDTH_TYPE                -1:0]         cfg_type;
+    input   [CFG_PORT_WIDTH_TCL                 -1:0]         cfg_tcl;
+    input   [CFG_PORT_WIDTH_CAS_WR_LAT          -1:0]         cfg_cas_wr_lat;
+    input   [CFG_PORT_WIDTH_ADD_LAT             -1:0]         cfg_add_lat;
+    input   [CFG_PORT_WIDTH_WRITE_ODT_CHIP      -1:0]         cfg_write_odt_chip;
+    input   [CFG_PORT_WIDTH_READ_ODT_CHIP       -1:0]         cfg_read_odt_chip;
+    input   [4:0]                                             cfg_burst_length;
+    input   [CFG_PORT_WIDTH_OUTPUT_REGD         -1:0]         cfg_output_regd;
+     
+    //Inputs from Arbiter Interface
+    
+    input                                                     bg_do_read;
+    input                                                     bg_do_write;
+    input                                                     bg_do_burst_chop;
+    input   [CFG_MEM_IF_CHIP                         -1:0]    bg_to_chip;
+    
+    //Output to AFI Interface
+    
+    output  [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2))-1:0] afi_odt;
+    
+    //=================================================================================================//
+    //        reg/wire declaration                                                                     //
+    //=================================================================================================//
+    
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  write_odt_chip  [CFG_MEM_IF_CHIP-1:0];
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  read_odt_chip   [CFG_MEM_IF_CHIP-1:0];
+    
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr2_odt_l;
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr2_odt_h;
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr3_odt_l;
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr3_odt_h;
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr3_odt_i_1;
+    wire    [CFG_MEM_IF_ODT_WIDTH-1:0]                  ddr3_odt_i_2;
+    
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_odt_l;
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_odt_h;
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_odt_i_1;
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_odt_i_2;
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_write_odt_chip;
+    reg     [CFG_MEM_IF_ODT_WIDTH-1:0]                  int_read_odt_chip;
+    
+    integer i;
+    
+    //=================================================================================================//
+    //        cfg_write_odt_chip & cfg_read_odt_chip definition                                        //
+    //=================================================================================================//
+    
+    /*
+    DDR3
+    four chip selects odt scheme, for two ranks per dimm configuration
+    .---------------------------------------++---------------------------------------.
+    |               write to                ||                odt to                 |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |  chip 0 |  chip 1 |  chip 2 |  chip 3 ||  chip 0 |  chip 1 |  chip 2 |  chip 3 |
+    |=--------+---------+---------+---------++---------+---------+---------+--------=|
+    |    1    |         |         |         ||    1    |         |    1    |         |    //cfg_write_odt_chip[0] = 4'b0101; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |    1    |         |         ||         |    1    |         |    1    |    //cfg_write_odt_chip[1] = 4'b1010; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |    1    |         ||    1    |         |    1    |         |    //cfg_write_odt_chip[2] = 4'b0101; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |         |    1    ||         |    1    |         |    1    |    //cfg_write_odt_chip[3] = 4'b1010; //chip[3] -> chip[0]
+    '---------+---------+---------+---------++---------+---------+---------+---------'
+    .---------------------------------------++---------------------------------------.
+    |                read to                ||                odt to                 |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |  chip 0 |  chip 1 |  chip 2 |  chip 3 ||  chip 0 |  chip 1 |  chip 2 |  chip 3 |
+    |=--------+---------+---------+---------++---------+---------+---------+--------=|
+    |    1    |         |         |         ||         |         |    1    |         |    //cfg_read_odt_chip[0] = 4'b0100; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |    1    |         |         ||         |         |         |    1    |    //cfg_read_odt_chip[1] = 4'b1000; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |    1    |         ||    1    |         |         |         |    //cfg_read_odt_chip[2] = 4'b0001; //chip[3] -> chip[0]
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |         |    1    ||         |    1    |         |         |    //cfg_read_odt_chip[3] = 4'b0010; //chip[3] -> chip[0]
+    '---------+---------+---------+---------++---------+---------+---------+---------'
+    */
+    
+    /*
+    DDR2
+    four or more chip selects odt scheme, assumes two ranks per dimm
+    .---------------------------------------++---------------------------------------.
+    |             write/read to             ||                odt to                 |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    | chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 || chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 |
+    |=--------+---------+---------+---------++---------+---------+---------+--------=|
+    |    1    |         |         |         ||         |         |    1    |         |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |    1    |         |         ||         |         |         |    1    |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |    1    |         ||    1    |         |         |         |
+    +---------+---------+---------+---------++---------+---------+---------+---------+
+    |         |         |         |    1    ||         |    1    |         |         |
+    '---------+---------+---------+---------++---------+---------+---------+---------'
+    */
+    
+    //Unpack read/write_odt_chip array into per chip array
+    
+    generate
+    genvar a;
+    begin : unpack_odt_config
+        for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
+        begin : unpack_odt_config_per_chip
+            assign write_odt_chip[a] = cfg_write_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
+            assign read_odt_chip[a]  = cfg_read_odt_chip  [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
+        end
+    end
+    endgenerate
+    
+    always @(*)
+    begin
+        int_write_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+        int_read_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+        for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+        begin
+            if (bg_to_chip[i])
+            begin
+                int_write_odt_chip = write_odt_chip[i];
+                int_read_odt_chip = read_odt_chip[i];
+            end
+        end
+    end
+    
+    //=================================================================================================//
+    //        Instantiate DDR2 ODT generation Block                                                    //
+    //=================================================================================================//
+    
+    generate
+        genvar b;
+        for (b=0; b<CFG_MEM_IF_ODT_WIDTH; b=b+1)
+        begin : ddr2_odt_gen
+            alt_mem_ddrx_ddr2_odt_gen
+            # (
+                .CFG_DWIDTH_RATIO           (CFG_DWIDTH_RATIO),
+                .CFG_PORT_WIDTH_ADD_LAT     (CFG_PORT_WIDTH_ADD_LAT),
+                .CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
+                .CFG_PORT_WIDTH_TCL         (CFG_PORT_WIDTH_TCL)
+            )
+            alt_mem_ddrx_ddr2_odt_gen_inst
+            (
+                .ctl_clk                    (ctl_clk),
+                .ctl_reset_n                (ctl_reset_n),
+                .cfg_tcl                    (cfg_tcl),
+                .cfg_add_lat                (cfg_add_lat),
+                .cfg_burst_length           (cfg_burst_length),
+                .cfg_output_regd            (cfg_output_regd),
+                .bg_do_write                (bg_do_write & int_write_odt_chip[b]),
+                .bg_do_read                 (bg_do_read & int_read_odt_chip[b]),
+                .int_odt_l                  (ddr2_odt_l[b]),
+                .int_odt_h                  (ddr2_odt_h[b])
+            );
+        end
+    endgenerate
+    
+    //=================================================================================================//
+    //        Instantiate DDR3 ODT generation Block                                                    //
+    //=================================================================================================//
+    
+    generate
+        genvar c; 
+        for (c=0; c<CFG_MEM_IF_ODT_WIDTH; c=c+1)
+        begin : ddr3_odt_gen
+            alt_mem_ddrx_ddr3_odt_gen
+            # (
+                .CFG_DWIDTH_RATIO           (CFG_DWIDTH_RATIO),
+                .CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
+                .CFG_PORT_WIDTH_TCL         (CFG_PORT_WIDTH_TCL),
+                .CFG_PORT_WIDTH_CAS_WR_LAT  (CFG_PORT_WIDTH_CAS_WR_LAT)
+            )
+            alt_mem_ddrx_ddr3_odt_gen_inst
+            (
+                .ctl_clk                    (ctl_clk),
+                .ctl_reset_n                (ctl_reset_n),
+                .cfg_tcl                    (cfg_tcl),
+                .cfg_cas_wr_lat             (cfg_cas_wr_lat),
+                .cfg_output_regd            (cfg_output_regd),
+                .bg_do_write                (bg_do_write & int_write_odt_chip[c]),
+                .bg_do_read                 (bg_do_read & int_read_odt_chip[c]),
+                .bg_do_burst_chop           (bg_do_burst_chop),
+                .int_odt_l                  (ddr3_odt_l[c]),
+                .int_odt_h                  (ddr3_odt_h[c]),
+                .int_odt_i_1                (ddr3_odt_i_1[c]),
+                .int_odt_i_2                (ddr3_odt_i_2[c])
+            );
+        end
+    endgenerate
+    
+    //=================================================================================================//
+    //        ODT Output generation based on memory type and ODT feature turned ON or not              //
+    //=================================================================================================//
+    
+    always @(*)
+    begin
+        if (cfg_type == `MMR_TYPE_DDR2)
+        begin
+            int_odt_l   = ddr2_odt_l;
+            int_odt_h   = ddr2_odt_h;
+            int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+            int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+        end
+        else if (cfg_type == `MMR_TYPE_DDR3)
+        begin
+            int_odt_l   = ddr3_odt_l;
+            int_odt_h   = ddr3_odt_h;
+            int_odt_i_1 = ddr3_odt_i_1;
+            int_odt_i_2 = ddr3_odt_i_2;
+        end
+        else
+        begin
+            int_odt_l   = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+            int_odt_h   = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+            int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+            int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
+        end
+    end
+    
+    generate
+        if (CFG_ODT_ENABLED == 1)
+        begin
+            if (CFG_DWIDTH_RATIO == 2) // quarter rate
+                assign afi_odt = int_odt_l;
+            else if (CFG_DWIDTH_RATIO == 4) // half rate
+                assign afi_odt = {int_odt_h,int_odt_l};
+            else if (CFG_DWIDTH_RATIO == 8) // quarter rate
+                assign afi_odt = {int_odt_h,int_odt_i_2, int_odt_i_1, int_odt_l};
+        end
+        else
+            assign afi_odt = {(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)){1'b0}};
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v
new file mode 100644
index 0000000..8668b5c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v
@@ -0,0 +1,2995 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036 10762
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+module alt_mem_ddrx_rank_timer #
+    ( parameter
+        CFG_DWIDTH_RATIO                        =   2,
+        CFG_CTL_TBP_NUM                         =   4,
+        CFG_CTL_ARBITER_TYPE                    =   "ROWCOL",
+        CFG_MEM_IF_CHIP                         =   1,
+        CFG_MEM_IF_CS_WIDTH                     =   1,
+        CFG_INT_SIZE_WIDTH                      =   4,
+        CFG_AFI_INTF_PHASE_NUM                  =   2,
+        CFG_REG_GRANT                           =   0,
+        CFG_RANK_TIMER_OUTPUT_REG               =   0,
+        CFG_PORT_WIDTH_BURST_LENGTH             =   5,
+        T_PARAM_FOUR_ACT_TO_ACT_WIDTH           =   0,
+        T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH      =   0,
+        T_PARAM_WR_TO_WR_WIDTH                  =   0,
+        T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH        =   0,
+        T_PARAM_WR_TO_RD_WIDTH                  =   0,
+        T_PARAM_WR_TO_RD_BC_WIDTH               =   0,
+        T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH        =   0,
+        T_PARAM_RD_TO_RD_WIDTH                  =   0,
+        T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH        =   0,
+        T_PARAM_RD_TO_WR_WIDTH                  =   0,
+        T_PARAM_RD_TO_WR_BC_WIDTH               =   0,
+        T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH        =   0
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // MMR Configurations
+        cfg_burst_length,
+        
+        // Timing parameters
+        t_param_four_act_to_act,
+        t_param_act_to_act_diff_bank,
+        t_param_wr_to_wr,
+        t_param_wr_to_wr_diff_chip,
+        t_param_wr_to_rd,
+        t_param_wr_to_rd_bc,
+        t_param_wr_to_rd_diff_chip,
+        t_param_rd_to_rd,
+        t_param_rd_to_rd_diff_chip,
+        t_param_rd_to_wr,
+        t_param_rd_to_wr_bc,
+        t_param_rd_to_wr_diff_chip,
+        
+        // Arbiter Interface
+        bg_do_write,
+        bg_do_read,
+        bg_do_burst_chop,
+        bg_do_burst_terminate,
+        bg_do_activate,
+        bg_do_precharge,
+        bg_to_chip,
+        bg_effective_size,
+        bg_interrupt_ready,
+        
+        // Command Generator Interface
+        cmd_gen_chipsel,
+        
+        // TBP Interface
+        tbp_chipsel,
+        tbp_load,
+        
+        // Sideband Interface
+        stall_chip,
+        
+        can_activate,
+        can_precharge,
+        can_read,
+        can_write
+    );
+
+input                                                       ctl_clk;
+input                                                       ctl_reset_n;
+
+input  [CFG_PORT_WIDTH_BURST_LENGTH                - 1 : 0] cfg_burst_length;
+
+input  [T_PARAM_FOUR_ACT_TO_ACT_WIDTH              - 1 : 0] t_param_four_act_to_act;
+input  [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH         - 1 : 0] t_param_act_to_act_diff_bank;
+input  [T_PARAM_WR_TO_WR_WIDTH                     - 1 : 0] t_param_wr_to_wr;
+input  [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH           - 1 : 0] t_param_wr_to_wr_diff_chip;
+input  [T_PARAM_WR_TO_RD_WIDTH                     - 1 : 0] t_param_wr_to_rd;
+input  [T_PARAM_WR_TO_RD_BC_WIDTH                  - 1 : 0] t_param_wr_to_rd_bc;
+input  [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH           - 1 : 0] t_param_wr_to_rd_diff_chip;
+input  [T_PARAM_RD_TO_RD_WIDTH                     - 1 : 0] t_param_rd_to_rd;
+input  [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH           - 1 : 0] t_param_rd_to_rd_diff_chip;
+input  [T_PARAM_RD_TO_WR_WIDTH                     - 1 : 0] t_param_rd_to_wr;
+input  [T_PARAM_RD_TO_WR_BC_WIDTH                  - 1 : 0] t_param_rd_to_wr_bc;
+input  [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH           - 1 : 0] t_param_rd_to_wr_diff_chip;
+
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_write;
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_read;
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_burst_chop;
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_burst_terminate;
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_activate;
+input  [CFG_AFI_INTF_PHASE_NUM                     - 1 : 0] bg_do_precharge;
+input  [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
+input  [CFG_INT_SIZE_WIDTH                         - 1 : 0] bg_effective_size;
+input                                                       bg_interrupt_ready;
+
+input  [CFG_MEM_IF_CS_WIDTH                        - 1 : 0] cmd_gen_chipsel;
+
+input  [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH)    - 1 : 0] tbp_chipsel;
+input  [CFG_CTL_TBP_NUM                            - 1 : 0] tbp_load;
+
+input  [CFG_MEM_IF_CHIP                            - 1 : 0] stall_chip;
+
+output [CFG_CTL_TBP_NUM                            - 1 : 0] can_activate;
+output [CFG_CTL_TBP_NUM                            - 1 : 0] can_precharge;
+output [CFG_CTL_TBP_NUM                            - 1 : 0] can_read;
+output [CFG_CTL_TBP_NUM                            - 1 : 0] can_write;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // General
+    localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
+    localparam RANK_TIMER_TFAW_OFFSET    = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
+    
+    localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
+    
+    wire one  = 1'b1;
+    wire zero = 1'b0;
+    
+    // Timing Parameter Comparison Logic
+    reg less_than_1_act_to_act_diff_bank;
+    reg less_than_2_act_to_act_diff_bank;
+    reg less_than_3_act_to_act_diff_bank;
+    reg less_than_4_act_to_act_diff_bank;
+    reg less_than_4_four_act_to_act;
+    
+    reg less_than_1_rd_to_rd;
+    reg less_than_1_rd_to_wr;
+    reg less_than_1_wr_to_wr;
+    reg less_than_1_wr_to_rd;
+    reg less_than_1_rd_to_wr_bc;
+    reg less_than_1_wr_to_rd_bc;
+    reg less_than_1_rd_to_rd_diff_chip;
+    reg less_than_1_rd_to_wr_diff_chip;
+    reg less_than_1_wr_to_wr_diff_chip;
+    reg less_than_1_wr_to_rd_diff_chip;
+    
+    reg less_than_2_rd_to_rd;
+    reg less_than_2_rd_to_wr;
+    reg less_than_2_wr_to_wr;
+    reg less_than_2_wr_to_rd;
+    reg less_than_2_rd_to_wr_bc;
+    reg less_than_2_wr_to_rd_bc;
+    reg less_than_2_rd_to_rd_diff_chip;
+    reg less_than_2_rd_to_wr_diff_chip;
+    reg less_than_2_wr_to_wr_diff_chip;
+    reg less_than_2_wr_to_rd_diff_chip;
+    
+    reg less_than_3_rd_to_rd;
+    reg less_than_3_rd_to_wr;
+    reg less_than_3_wr_to_wr;
+    reg less_than_3_wr_to_rd;
+    reg less_than_3_rd_to_wr_bc;
+    reg less_than_3_wr_to_rd_bc;
+    reg less_than_3_rd_to_rd_diff_chip;
+    reg less_than_3_rd_to_wr_diff_chip;
+    reg less_than_3_wr_to_wr_diff_chip;
+    reg less_than_3_wr_to_rd_diff_chip;
+    
+    reg less_than_4_rd_to_rd;
+    reg less_than_4_rd_to_wr;
+    reg less_than_4_wr_to_wr;
+    reg less_than_4_wr_to_rd;
+    reg less_than_4_rd_to_wr_bc;
+    reg less_than_4_wr_to_rd_bc;
+    reg less_than_4_rd_to_rd_diff_chip;
+    reg less_than_4_rd_to_wr_diff_chip;
+    reg less_than_4_wr_to_wr_diff_chip;
+    reg less_than_4_wr_to_rd_diff_chip;
+    
+    reg more_than_2_rd_to_rd;
+    reg more_than_2_rd_to_wr;
+    reg more_than_2_wr_to_wr;
+    reg more_than_2_wr_to_rd;
+    reg more_than_2_rd_to_wr_bc;
+    reg more_than_2_wr_to_rd_bc;
+    reg more_than_2_rd_to_rd_diff_chip;
+    reg more_than_2_rd_to_wr_diff_chip;
+    reg more_than_2_wr_to_wr_diff_chip;
+    reg more_than_2_wr_to_rd_diff_chip;
+    
+    reg more_than_3_rd_to_rd;
+    reg more_than_3_rd_to_wr;
+    reg more_than_3_wr_to_wr;
+    reg more_than_3_wr_to_rd;
+    reg more_than_3_rd_to_wr_bc;
+    reg more_than_3_wr_to_rd_bc;
+    reg more_than_3_rd_to_rd_diff_chip;
+    reg more_than_3_rd_to_wr_diff_chip;
+    reg more_than_3_wr_to_wr_diff_chip;
+    reg more_than_3_wr_to_rd_diff_chip;
+    
+    reg less_than_xn1_act_to_act_diff_bank;
+    reg less_than_xn1_rd_to_rd;
+    reg less_than_xn1_rd_to_wr;
+    reg less_than_xn1_wr_to_wr;
+    reg less_than_xn1_wr_to_rd;
+    reg less_than_xn1_rd_to_wr_bc;
+    reg less_than_xn1_wr_to_rd_bc;
+    reg less_than_xn1_rd_to_rd_diff_chip;
+    reg less_than_xn1_rd_to_wr_diff_chip;
+    reg less_than_xn1_wr_to_wr_diff_chip;
+    reg less_than_xn1_wr_to_rd_diff_chip;
+    
+    reg less_than_x0_act_to_act_diff_bank;
+    reg less_than_x0_rd_to_rd;
+    reg less_than_x0_rd_to_wr;
+    reg less_than_x0_wr_to_wr;
+    reg less_than_x0_wr_to_rd;
+    reg less_than_x0_rd_to_wr_bc;
+    reg less_than_x0_wr_to_rd_bc;
+    reg less_than_x0_rd_to_rd_diff_chip;
+    reg less_than_x0_rd_to_wr_diff_chip;
+    reg less_than_x0_wr_to_wr_diff_chip;
+    reg less_than_x0_wr_to_rd_diff_chip;
+    
+    reg less_than_x1_act_to_act_diff_bank;
+    reg less_than_x1_rd_to_rd;
+    reg less_than_x1_rd_to_wr;
+    reg less_than_x1_wr_to_wr;
+    reg less_than_x1_wr_to_rd;
+    reg less_than_x1_rd_to_wr_bc;
+    reg less_than_x1_wr_to_rd_bc;
+    reg less_than_x1_rd_to_rd_diff_chip;
+    reg less_than_x1_rd_to_wr_diff_chip;
+    reg less_than_x1_wr_to_wr_diff_chip;
+    reg less_than_x1_wr_to_rd_diff_chip;
+    
+    reg more_than_x0_rd_to_rd;
+    reg more_than_x0_rd_to_wr;
+    reg more_than_x0_wr_to_wr;
+    reg more_than_x0_wr_to_rd;
+    reg more_than_x0_rd_to_wr_bc;
+    reg more_than_x0_wr_to_rd_bc;
+    reg more_than_x0_rd_to_rd_diff_chip;
+    reg more_than_x0_rd_to_wr_diff_chip;
+    reg more_than_x0_wr_to_wr_diff_chip;
+    reg more_than_x0_wr_to_rd_diff_chip;
+    
+    // Input
+    reg                               int_do_activate;
+    reg                               int_do_precharge;
+    reg                               int_do_burst_chop;
+    reg                               int_do_burst_terminate;
+    reg                               int_do_write;
+    reg                               int_do_read;
+    reg  [CFG_MEM_IF_CHIP    - 1 : 0] int_to_chip_r;
+    reg  [CFG_MEM_IF_CHIP    - 1 : 0] int_to_chip_c;
+    reg  [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
+    reg                               int_interrupt_ready;
+    
+    // Activate Monitor
+    localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
+    localparam ACTIVATE_COMMAND_WIDTH = 3;
+    localparam NUM_OF_TFAW_SHIFT_REG  = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
+    
+    reg  [CFG_MEM_IF_CHIP        - 1 : 0] act_tfaw_ready;
+    reg  [CFG_MEM_IF_CHIP        - 1 : 0] act_tfaw_ready_combi;
+    reg  [CFG_MEM_IF_CHIP        - 1 : 0] act_trrd_ready;
+    reg  [CFG_MEM_IF_CHIP        - 1 : 0] act_trrd_ready_combi;
+    reg  [CFG_MEM_IF_CHIP        - 1 : 0] act_ready;
+    wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
+    
+    // Read/Write Monitor
+    localparam IDLE               = 2'b00;
+    localparam WR                 = 2'b01;
+    localparam RD                 = 2'b10;
+    localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
+    
+    reg  [CFG_INT_SIZE_WIDTH               - 1 : 0] max_local_burst_size;
+    
+    reg  [T_PARAM_RD_TO_WR_WIDTH           - 1 : 0] effective_rd_to_wr_combi;
+    reg  [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
+    reg  [T_PARAM_WR_TO_RD_WIDTH           - 1 : 0] effective_wr_to_rd_combi;
+    reg  [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
+    
+    reg  [T_PARAM_RD_TO_WR_WIDTH           - 1 : 0] effective_rd_to_wr;
+    reg  [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
+    reg  [T_PARAM_WR_TO_RD_WIDTH           - 1 : 0] effective_wr_to_rd;
+    reg  [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
+    
+    reg  [CFG_MEM_IF_CHIP                  - 1 : 0] read_ready;
+    reg  [CFG_MEM_IF_CHIP                  - 1 : 0] write_ready;
+    
+    // Precharge Monitor
+    reg  [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
+    
+    // Output
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
+    
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] can_read;
+    reg  [CFG_CTL_TBP_NUM - 1 : 0] can_write;
+    
+    reg  [T_PARAM_FOUR_ACT_TO_ACT_WIDTH   - 1 : 0] sel_act_tfaw_shift_out_point;
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Input
+//
+//--------------------------------------------------------------------------------------------------------
+    // Do activate
+    always @ (*)
+    begin
+        int_do_activate = |bg_do_activate;
+    end
+    
+    // Do precharge
+    always @ (*)
+    begin
+        int_do_precharge = |bg_do_precharge;
+    end
+    
+    //Do burst chop
+    always @ (*)
+    begin
+        int_do_burst_chop = |bg_do_burst_chop;
+    end
+    
+    //Do burst terminate
+    always @ (*)
+    begin
+        int_do_burst_terminate = |bg_do_burst_terminate;
+    end
+    
+    // Do write
+    always @ (*)
+    begin
+        int_do_write = |bg_do_write;
+    end
+    
+    // Do read
+    always @ (*)
+    begin
+        int_do_read = |bg_do_read;
+    end
+    
+    // To chip
+    always @ (*)
+    begin
+        // _r for row command and _c for column command
+        if (CFG_CTL_ARBITER_TYPE == "COLROW")
+        begin
+            int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP     - 1 : 0              ];
+            int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+        end
+        else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
+        begin
+            int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP     - 1 : 0              ];
+            int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
+        end
+    end
+    
+    // Effective size
+    always @ (*)
+    begin
+        int_effective_size = bg_effective_size;
+    end
+    
+    // Interrupt ready
+    always @ (*)
+    begin
+        int_interrupt_ready = bg_interrupt_ready;
+    end
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Input
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Output
+//
+//--------------------------------------------------------------------------------------------------------
+    generate
+        genvar x_cs;
+        for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
+        begin : can_logic_per_chip
+            reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
+            
+            always @ (*)
+            begin
+                if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
+                begin
+                    chip_addr = cmd_gen_chipsel;
+                end
+                else
+                begin
+                    chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
+                end
+            end
+            
+            if (CFG_RANK_TIMER_OUTPUT_REG)
+            begin
+                always @ (*)
+                begin
+                    can_activate  [x_cs] = int_can_activate  [x_cs]                      ;
+                    can_precharge [x_cs] = int_can_precharge [x_cs]                      ;
+                    can_read      [x_cs] = int_can_read      [x_cs] & int_interrupt_ready;
+                    can_write     [x_cs] = int_can_write     [x_cs] & int_interrupt_ready;
+                end
+                
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        int_can_activate [x_cs] <= 1'b0;
+                    end
+                    else
+                    begin
+                        if (stall_chip [chip_addr])
+                        begin
+                            int_can_activate [x_cs] <= 1'b0;
+                        end
+                        else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
+                        begin
+                            int_can_activate [x_cs] <= 1'b0;
+                        end
+                        else
+                        begin
+                            int_can_activate [x_cs] <= act_ready [chip_addr];
+                        end
+                    end
+                end
+                
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        int_can_precharge [x_cs] <= 1'b0;
+                    end
+                    else
+                    begin
+                        if (stall_chip [chip_addr])
+                        begin
+                            int_can_precharge [x_cs] <= 1'b0;
+                        end
+                        else
+                        begin
+                            int_can_precharge [x_cs] <= pch_ready [chip_addr];
+                        end
+                    end
+                end
+                
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        int_can_read [x_cs] <= 1'b0;
+                    end
+                    else
+                    begin
+                        if (stall_chip [chip_addr])
+                        begin
+                            int_can_read [x_cs] <= 1'b0;
+                        end
+                        else if (int_do_write)
+                        begin
+                            if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
+                            begin
+                                if (int_do_burst_chop && more_than_x0_wr_to_rd_bc)
+                                begin
+                                    int_can_read [x_cs] <= 1'b0;
+                                end
+                                else if (!int_do_burst_chop && more_than_x0_wr_to_rd)
+                                begin
+                                    int_can_read [x_cs] <= 1'b0;
+                                end
+                                else
+                                begin
+                                    int_can_read [x_cs] <= 1'b1;
+                                end
+                            end
+                            else // to other chip addr as compared to current TBP
+                            begin
+                                int_can_read [x_cs] <= 1'b0;
+                            end
+                        end
+                        else if (int_do_read)
+                        begin
+                            if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
+                            begin
+                                if (more_than_x0_rd_to_rd)
+                                begin
+                                    int_can_read [x_cs] <= 1'b0;
+                                end
+                                else
+                                begin
+                                    int_can_read [x_cs] <= 1'b1;
+                                end
+                            end
+                            else // to other chip addr as compared to current TBP
+                            begin
+                                int_can_read [x_cs] <= 1'b0;
+                            end
+                        end
+                        else
+                        begin
+                            int_can_read [x_cs] <= read_ready [chip_addr];
+                        end
+                    end
+                end
+                
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        int_can_write [x_cs] <= 1'b0;
+                    end
+                    else
+                    begin
+                        if (stall_chip [chip_addr])
+                        begin
+                            int_can_write [x_cs] <= 1'b0;
+                        end
+                        else if (int_do_read)
+                        begin
+                            if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
+                            begin
+                                if (int_do_burst_chop && more_than_x0_rd_to_wr_bc)
+                                begin
+                                    int_can_write [x_cs] <= 1'b0;
+                                end
+                                else if (!int_do_burst_chop && more_than_x0_rd_to_wr)
+                                begin
+                                    int_can_write [x_cs] <= 1'b0;
+                                end
+                                else
+                                begin
+                                    int_can_write [x_cs] <= 1'b1;
+                                end
+                            end
+                            else // to other chip addr as compared to current TBP
+                            begin
+                                int_can_write [x_cs] <= 1'b0;
+                            end
+                        end
+                        else if (int_do_write)
+                        begin
+                            if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
+                            begin
+                                if (more_than_x0_wr_to_wr)
+                                begin
+                                    int_can_write [x_cs] <= 1'b0;
+                                end
+                                else
+                                begin
+                                    int_can_write [x_cs] <= 1'b1;
+                                end
+                            end
+                            else // to other chip addr as compared to current TBP
+                            begin
+                                int_can_write [x_cs] <= 1'b0;
+                            end
+                        end
+                        else
+                        begin
+                            int_can_write [x_cs] <= write_ready [chip_addr];
+                        end
+                    end
+                end
+            end
+            else
+            begin
+                // Can activate
+                always @ (*)
+                begin
+                    can_activate [x_cs] = act_ready [chip_addr];
+                end
+                
+                // Can precharge
+                always @ (*)
+                begin
+                    can_precharge [x_cs] = pch_ready [chip_addr];
+                end
+                
+                // Can read
+                always @ (*)
+                begin
+                    can_read [x_cs] = read_ready [chip_addr];
+                end
+                
+                // Can write
+                always @ (*)
+                begin
+                    can_write [x_cs] = write_ready [chip_addr];
+                end
+            end
+        end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Output
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Timing Parameter Comparison Logic
+//
+//--------------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_act_to_act_diff_bank <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_act_to_act_diff_bank <= 1)
+                less_than_1_act_to_act_diff_bank <= 1'b1;
+            else
+                less_than_1_act_to_act_diff_bank <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_act_to_act_diff_bank <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_act_to_act_diff_bank <= 2)
+                less_than_2_act_to_act_diff_bank <= 1'b1;
+            else
+                less_than_2_act_to_act_diff_bank <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_act_to_act_diff_bank <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_act_to_act_diff_bank <= 3)
+                less_than_3_act_to_act_diff_bank <= 1'b1;
+            else
+                less_than_3_act_to_act_diff_bank <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_act_to_act_diff_bank <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_act_to_act_diff_bank <= 4)
+                less_than_4_act_to_act_diff_bank <= 1'b1;
+            else
+                less_than_4_act_to_act_diff_bank <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_four_act_to_act <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_four_act_to_act <= 4)
+                less_than_4_four_act_to_act <= 1'b1;
+            else
+                less_than_4_four_act_to_act <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd <= 1)
+                less_than_1_rd_to_rd <= 1'b1;
+            else
+                less_than_1_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr <= 1)
+                less_than_1_rd_to_wr <= 1'b1;
+            else
+                less_than_1_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr <= 1)
+                less_than_1_wr_to_wr <= 1'b1;
+            else
+                less_than_1_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd <= 1)
+                less_than_1_wr_to_rd <= 1'b1;
+            else
+                less_than_1_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc <= 1)
+                less_than_1_rd_to_wr_bc <= 1'b1;
+            else
+                less_than_1_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc <= 1)
+                less_than_1_wr_to_rd_bc <= 1'b1;
+            else
+                less_than_1_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip <= 1)
+                less_than_1_rd_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_1_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip <= 1)
+                less_than_1_rd_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_1_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip <= 1)
+                less_than_1_wr_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_1_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_1_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip <= 1)
+                less_than_1_wr_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_1_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd <= 2)
+                less_than_2_rd_to_rd <= 1'b1;
+            else
+                less_than_2_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr <= 2)
+                less_than_2_rd_to_wr <= 1'b1;
+            else
+                less_than_2_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr <= 2)
+                less_than_2_wr_to_wr <= 1'b1;
+            else
+                less_than_2_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd <= 2)
+                less_than_2_wr_to_rd <= 1'b1;
+            else
+                less_than_2_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc <= 2)
+                less_than_2_rd_to_wr_bc <= 1'b1;
+            else
+                less_than_2_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc <= 2)
+                less_than_2_wr_to_rd_bc <= 1'b1;
+            else
+                less_than_2_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip <= 2)
+                less_than_2_rd_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_2_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip <= 2)
+                less_than_2_rd_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_2_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip <= 2)
+                less_than_2_wr_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_2_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_2_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip <= 2)
+                less_than_2_wr_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_2_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd <= 3)
+                less_than_3_rd_to_rd <= 1'b1;
+            else
+                less_than_3_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr <= 3)
+                less_than_3_rd_to_wr <= 1'b1;
+            else
+                less_than_3_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr <= 3)
+                less_than_3_wr_to_wr <= 1'b1;
+            else
+                less_than_3_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd <= 3)
+                less_than_3_wr_to_rd <= 1'b1;
+            else
+                less_than_3_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc <= 3)
+                less_than_3_rd_to_wr_bc <= 1'b1;
+            else
+                less_than_3_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc <= 3)
+                less_than_3_wr_to_rd_bc <= 1'b1;
+            else
+                less_than_3_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip <= 3)
+                less_than_3_rd_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_3_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip <= 3)
+                less_than_3_rd_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_3_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip <= 3)
+                less_than_3_wr_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_3_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_3_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip <= 3)
+                less_than_3_wr_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_3_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd <= 4)
+                less_than_4_rd_to_rd <= 1'b1;
+            else
+                less_than_4_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr <= 4)
+                less_than_4_rd_to_wr <= 1'b1;
+            else
+                less_than_4_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr <= 4)
+                less_than_4_wr_to_wr <= 1'b1;
+            else
+                less_than_4_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd <= 4)
+                less_than_4_wr_to_rd <= 1'b1;
+            else
+                less_than_4_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc <= 4)
+                less_than_4_rd_to_wr_bc <= 1'b1;
+            else
+                less_than_4_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc <= 4)
+                less_than_4_wr_to_rd_bc <= 1'b1;
+            else
+                less_than_4_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip <= 4)
+                less_than_4_rd_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_4_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip <= 4)
+                less_than_4_rd_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_4_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip <= 4)
+                less_than_4_wr_to_wr_diff_chip <= 1'b1;
+            else
+                less_than_4_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            less_than_4_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip <= 4)
+                less_than_4_wr_to_rd_diff_chip <= 1'b1;
+            else
+                less_than_4_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd >= 2)
+                more_than_2_rd_to_rd <= 1'b1;
+            else
+                more_than_2_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr >= 2)
+                more_than_2_rd_to_wr <= 1'b1;
+            else
+                more_than_2_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr >= 2)
+                more_than_2_wr_to_wr <= 1'b1;
+            else
+                more_than_2_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd >= 2)
+                more_than_2_wr_to_rd <= 1'b1;
+            else
+                more_than_2_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc >= 2)
+                more_than_2_rd_to_wr_bc <= 1'b1;
+            else
+                more_than_2_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc >= 2)
+                more_than_2_wr_to_rd_bc <= 1'b1;
+            else
+                more_than_2_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip >= 2)
+                more_than_2_rd_to_rd_diff_chip <= 1'b1;
+            else
+                more_than_2_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip >= 2)
+                more_than_2_rd_to_wr_diff_chip <= 1'b1;
+            else
+                more_than_2_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip >= 2)
+                more_than_2_wr_to_wr_diff_chip <= 1'b1;
+            else
+                more_than_2_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_2_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip >= 2)
+                more_than_2_wr_to_rd_diff_chip <= 1'b1;
+            else
+                more_than_2_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_rd_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd >= 3)
+                more_than_3_rd_to_rd <= 1'b1;
+            else
+                more_than_3_rd_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_rd_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr >= 3)
+                more_than_3_rd_to_wr <= 1'b1;
+            else
+                more_than_3_rd_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_wr_to_wr <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr >= 3)
+                more_than_3_wr_to_wr <= 1'b1;
+            else
+                more_than_3_wr_to_wr <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_wr_to_rd <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd >= 3)
+                more_than_3_wr_to_rd <= 1'b1;
+            else
+                more_than_3_wr_to_rd <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_rd_to_wr_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_bc >= 3)
+                more_than_3_rd_to_wr_bc <= 1'b1;
+            else
+                more_than_3_rd_to_wr_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_wr_to_rd_bc <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_bc >= 3)
+                more_than_3_wr_to_rd_bc <= 1'b1;
+            else
+                more_than_3_wr_to_rd_bc <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_rd_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_rd_diff_chip >= 3)
+                more_than_3_rd_to_rd_diff_chip <= 1'b1;
+            else
+                more_than_3_rd_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_rd_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_rd_to_wr_diff_chip >= 3)
+                more_than_3_rd_to_wr_diff_chip <= 1'b1;
+            else
+                more_than_3_rd_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_wr_to_wr_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_wr_diff_chip >= 3)
+                more_than_3_wr_to_wr_diff_chip <= 1'b1;
+            else
+                more_than_3_wr_to_wr_diff_chip <= 1'b0;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            more_than_3_wr_to_rd_diff_chip <= 1'b0;
+        end
+        else
+        begin
+            if (t_param_wr_to_rd_diff_chip >= 3)
+                more_than_3_wr_to_rd_diff_chip <= 1'b1;
+            else
+                more_than_3_wr_to_rd_diff_chip <= 1'b0;
+        end
+    end
+    
+    generate
+    begin
+        if (CFG_REG_GRANT)
+        begin
+            always @ (*)
+            begin
+                if (CFG_RANK_TIMER_OUTPUT_REG)
+                begin
+                    less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
+                    less_than_xn1_rd_to_rd             = less_than_2_rd_to_rd;
+                    less_than_xn1_rd_to_wr             = less_than_2_rd_to_wr;
+                    less_than_xn1_wr_to_wr             = less_than_2_wr_to_wr;
+                    less_than_xn1_wr_to_rd             = less_than_2_wr_to_rd;
+                    less_than_xn1_rd_to_wr_bc          = less_than_2_rd_to_wr_bc;
+                    less_than_xn1_wr_to_rd_bc          = less_than_2_wr_to_rd_bc;
+                    less_than_xn1_rd_to_rd_diff_chip   = less_than_2_rd_to_rd_diff_chip;
+                    less_than_xn1_rd_to_wr_diff_chip   = less_than_2_rd_to_wr_diff_chip;
+                    less_than_xn1_wr_to_wr_diff_chip   = less_than_2_wr_to_wr_diff_chip;
+                    less_than_xn1_wr_to_rd_diff_chip   = less_than_2_wr_to_rd_diff_chip;
+                    
+                    less_than_x0_act_to_act_diff_bank  = less_than_3_act_to_act_diff_bank;
+                    less_than_x0_rd_to_rd              = less_than_3_rd_to_rd;
+                    less_than_x0_rd_to_wr              = less_than_3_rd_to_wr;
+                    less_than_x0_wr_to_wr              = less_than_3_wr_to_wr;
+                    less_than_x0_wr_to_rd              = less_than_3_wr_to_rd;
+                    less_than_x0_rd_to_wr_bc           = less_than_3_rd_to_wr_bc;
+                    less_than_x0_wr_to_rd_bc           = less_than_3_wr_to_rd_bc;
+                    less_than_x0_rd_to_rd_diff_chip    = less_than_3_rd_to_rd_diff_chip;
+                    less_than_x0_rd_to_wr_diff_chip    = less_than_3_rd_to_wr_diff_chip;
+                    less_than_x0_wr_to_wr_diff_chip    = less_than_3_wr_to_wr_diff_chip;
+                    less_than_x0_wr_to_rd_diff_chip    = less_than_3_wr_to_rd_diff_chip;
+                    
+                    less_than_x1_act_to_act_diff_bank  = less_than_4_act_to_act_diff_bank;
+                    less_than_x1_rd_to_rd              = less_than_4_rd_to_rd;
+                    less_than_x1_rd_to_wr              = less_than_4_rd_to_wr;
+                    less_than_x1_wr_to_wr              = less_than_4_wr_to_wr;
+                    less_than_x1_wr_to_rd              = less_than_4_wr_to_rd;
+                    less_than_x1_rd_to_wr_bc           = less_than_4_rd_to_wr_bc;
+                    less_than_x1_wr_to_rd_bc           = less_than_4_wr_to_rd_bc;
+                    less_than_x1_rd_to_rd_diff_chip    = less_than_4_rd_to_rd_diff_chip;
+                    less_than_x1_rd_to_wr_diff_chip    = less_than_4_rd_to_wr_diff_chip;
+                    less_than_x1_wr_to_wr_diff_chip    = less_than_4_wr_to_wr_diff_chip;
+                    less_than_x1_wr_to_rd_diff_chip    = less_than_4_wr_to_rd_diff_chip;
+                end
+                else
+                begin
+                    // Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
+                    less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
+                    less_than_xn1_rd_to_rd             = less_than_2_rd_to_rd;
+                    less_than_xn1_rd_to_wr             = less_than_2_rd_to_wr;
+                    less_than_xn1_wr_to_wr             = less_than_2_wr_to_wr;
+                    less_than_xn1_wr_to_rd             = less_than_2_wr_to_rd;
+                    less_than_xn1_rd_to_wr_bc          = less_than_2_rd_to_wr_bc;
+                    less_than_xn1_wr_to_rd_bc          = less_than_2_wr_to_rd_bc;
+                    less_than_xn1_rd_to_rd_diff_chip   = less_than_2_rd_to_rd_diff_chip;
+                    less_than_xn1_rd_to_wr_diff_chip   = less_than_2_rd_to_wr_diff_chip;
+                    less_than_xn1_wr_to_wr_diff_chip   = less_than_2_wr_to_wr_diff_chip;
+                    less_than_xn1_wr_to_rd_diff_chip   = less_than_2_wr_to_rd_diff_chip;
+                    
+                    less_than_x0_act_to_act_diff_bank  = less_than_2_act_to_act_diff_bank;
+                    less_than_x0_rd_to_rd              = less_than_2_rd_to_rd;
+                    less_than_x0_rd_to_wr              = less_than_2_rd_to_wr;
+                    less_than_x0_wr_to_wr              = less_than_2_wr_to_wr;
+                    less_than_x0_wr_to_rd              = less_than_2_wr_to_rd;
+                    less_than_x0_rd_to_wr_bc           = less_than_2_rd_to_wr_bc;
+                    less_than_x0_wr_to_rd_bc           = less_than_2_wr_to_rd_bc;
+                    less_than_x0_rd_to_rd_diff_chip    = less_than_2_rd_to_rd_diff_chip;
+                    less_than_x0_rd_to_wr_diff_chip    = less_than_2_rd_to_wr_diff_chip;
+                    less_than_x0_wr_to_wr_diff_chip    = less_than_2_wr_to_wr_diff_chip;
+                    less_than_x0_wr_to_rd_diff_chip    = less_than_2_wr_to_rd_diff_chip;
+                    
+                    less_than_x1_act_to_act_diff_bank  = less_than_3_act_to_act_diff_bank;
+                    less_than_x1_rd_to_rd              = less_than_3_rd_to_rd;
+                    less_than_x1_rd_to_wr              = less_than_3_rd_to_wr;
+                    less_than_x1_wr_to_wr              = less_than_3_wr_to_wr;
+                    less_than_x1_wr_to_rd              = less_than_3_wr_to_rd;
+                    less_than_x1_rd_to_wr_bc           = less_than_3_rd_to_wr_bc;
+                    less_than_x1_wr_to_rd_bc           = less_than_3_wr_to_rd_bc;
+                    less_than_x1_rd_to_rd_diff_chip    = less_than_3_rd_to_rd_diff_chip;
+                    less_than_x1_rd_to_wr_diff_chip    = less_than_3_rd_to_wr_diff_chip;
+                    less_than_x1_wr_to_wr_diff_chip    = less_than_3_wr_to_wr_diff_chip;
+                    less_than_x1_wr_to_rd_diff_chip    = less_than_3_wr_to_rd_diff_chip;
+                end
+            end
+            
+            always @ (*)
+            begin
+                more_than_x0_rd_to_rd           = more_than_3_rd_to_rd;
+                more_than_x0_rd_to_wr           = more_than_3_rd_to_wr;
+                more_than_x0_wr_to_wr           = more_than_3_wr_to_wr;
+                more_than_x0_wr_to_rd           = more_than_3_wr_to_rd;
+                more_than_x0_rd_to_wr_bc        = more_than_3_rd_to_wr_bc;
+                more_than_x0_wr_to_rd_bc        = more_than_3_wr_to_rd_bc;
+                more_than_x0_rd_to_rd_diff_chip = more_than_3_rd_to_rd_diff_chip;
+                more_than_x0_rd_to_wr_diff_chip = more_than_3_rd_to_wr_diff_chip;
+                more_than_x0_wr_to_wr_diff_chip = more_than_3_wr_to_wr_diff_chip;
+                more_than_x0_wr_to_rd_diff_chip = more_than_3_wr_to_rd_diff_chip;
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                if (CFG_RANK_TIMER_OUTPUT_REG)
+                begin
+                    less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
+                    less_than_xn1_rd_to_rd             = less_than_1_rd_to_rd;
+                    less_than_xn1_rd_to_wr             = less_than_1_rd_to_wr;
+                    less_than_xn1_wr_to_wr             = less_than_1_wr_to_wr;
+                    less_than_xn1_wr_to_rd             = less_than_1_wr_to_rd;
+                    less_than_xn1_rd_to_wr_bc          = less_than_1_rd_to_wr_bc;
+                    less_than_xn1_wr_to_rd_bc          = less_than_1_wr_to_rd_bc;
+                    less_than_xn1_rd_to_rd_diff_chip   = less_than_1_rd_to_rd_diff_chip;
+                    less_than_xn1_rd_to_wr_diff_chip   = less_than_1_rd_to_wr_diff_chip;
+                    less_than_xn1_wr_to_wr_diff_chip   = less_than_1_wr_to_wr_diff_chip;
+                    less_than_xn1_wr_to_rd_diff_chip   = less_than_1_wr_to_rd_diff_chip;
+                    
+                    less_than_x0_act_to_act_diff_bank  = less_than_2_act_to_act_diff_bank;
+                    less_than_x0_rd_to_rd              = less_than_2_rd_to_rd;
+                    less_than_x0_rd_to_wr              = less_than_2_rd_to_wr;
+                    less_than_x0_wr_to_wr              = less_than_2_wr_to_wr;
+                    less_than_x0_wr_to_rd              = less_than_2_wr_to_rd;
+                    less_than_x0_rd_to_wr_bc           = less_than_2_rd_to_wr_bc;
+                    less_than_x0_wr_to_rd_bc           = less_than_2_wr_to_rd_bc;
+                    less_than_x0_rd_to_rd_diff_chip    = less_than_2_rd_to_rd_diff_chip;
+                    less_than_x0_rd_to_wr_diff_chip    = less_than_2_rd_to_wr_diff_chip;
+                    less_than_x0_wr_to_wr_diff_chip    = less_than_2_wr_to_wr_diff_chip;
+                    less_than_x0_wr_to_rd_diff_chip    = less_than_2_wr_to_rd_diff_chip;
+                    
+                    less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
+                    less_than_x1_rd_to_rd             = less_than_3_rd_to_rd;
+                    less_than_x1_rd_to_wr             = less_than_3_rd_to_wr;
+                    less_than_x1_wr_to_wr             = less_than_3_wr_to_wr;
+                    less_than_x1_wr_to_rd             = less_than_3_wr_to_rd;
+                    less_than_x1_rd_to_wr_bc          = less_than_3_rd_to_wr_bc;
+                    less_than_x1_wr_to_rd_bc          = less_than_3_wr_to_rd_bc;
+                    less_than_x1_rd_to_rd_diff_chip   = less_than_3_rd_to_rd_diff_chip;
+                    less_than_x1_rd_to_wr_diff_chip   = less_than_3_rd_to_wr_diff_chip;
+                    less_than_x1_wr_to_wr_diff_chip   = less_than_3_wr_to_wr_diff_chip;
+                    less_than_x1_wr_to_rd_diff_chip   = less_than_3_wr_to_rd_diff_chip;
+                end
+                else
+                begin
+                    // Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
+                    less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
+                    less_than_xn1_rd_to_rd             = less_than_1_rd_to_rd;
+                    less_than_xn1_rd_to_wr             = less_than_1_rd_to_wr;
+                    less_than_xn1_wr_to_wr             = less_than_1_wr_to_wr;
+                    less_than_xn1_wr_to_rd             = less_than_1_wr_to_rd;
+                    less_than_xn1_rd_to_wr_bc          = less_than_1_rd_to_wr_bc;
+                    less_than_xn1_wr_to_rd_bc          = less_than_1_wr_to_rd_bc;
+                    less_than_xn1_rd_to_rd_diff_chip   = less_than_1_rd_to_rd_diff_chip;
+                    less_than_xn1_rd_to_wr_diff_chip   = less_than_1_rd_to_wr_diff_chip;
+                    less_than_xn1_wr_to_wr_diff_chip   = less_than_1_wr_to_wr_diff_chip;
+                    less_than_xn1_wr_to_rd_diff_chip   = less_than_1_wr_to_rd_diff_chip;
+                    
+                    less_than_x0_act_to_act_diff_bank  = less_than_1_act_to_act_diff_bank;
+                    less_than_x0_rd_to_rd              = less_than_1_rd_to_rd;
+                    less_than_x0_rd_to_wr              = less_than_1_rd_to_wr;
+                    less_than_x0_wr_to_wr              = less_than_1_wr_to_wr;
+                    less_than_x0_wr_to_rd              = less_than_1_wr_to_rd;
+                    less_than_x0_rd_to_wr_bc           = less_than_1_rd_to_wr_bc;
+                    less_than_x0_wr_to_rd_bc           = less_than_1_wr_to_rd_bc;
+                    less_than_x0_rd_to_rd_diff_chip    = less_than_1_rd_to_rd_diff_chip;
+                    less_than_x0_rd_to_wr_diff_chip    = less_than_1_rd_to_wr_diff_chip;
+                    less_than_x0_wr_to_wr_diff_chip    = less_than_1_wr_to_wr_diff_chip;
+                    less_than_x0_wr_to_rd_diff_chip    = less_than_1_wr_to_rd_diff_chip;
+                    
+                    less_than_x1_act_to_act_diff_bank  = less_than_2_act_to_act_diff_bank;
+                    less_than_x1_rd_to_rd              = less_than_2_rd_to_rd;
+                    less_than_x1_rd_to_wr              = less_than_2_rd_to_wr;
+                    less_than_x1_wr_to_wr              = less_than_2_wr_to_wr;
+                    less_than_x1_wr_to_rd              = less_than_2_wr_to_rd;
+                    less_than_x1_rd_to_wr_bc           = less_than_2_rd_to_wr_bc;
+                    less_than_x1_wr_to_rd_bc           = less_than_2_wr_to_rd_bc;
+                    less_than_x1_rd_to_rd_diff_chip    = less_than_2_rd_to_rd_diff_chip;
+                    less_than_x1_rd_to_wr_diff_chip    = less_than_2_rd_to_wr_diff_chip;
+                    less_than_x1_wr_to_wr_diff_chip    = less_than_2_wr_to_wr_diff_chip;
+                    less_than_x1_wr_to_rd_diff_chip    = less_than_2_wr_to_rd_diff_chip;
+                end
+            end
+            
+            always @ (*)
+            begin
+                more_than_x0_rd_to_rd           = more_than_2_rd_to_rd;
+                more_than_x0_rd_to_wr           = more_than_2_rd_to_wr;
+                more_than_x0_wr_to_wr           = more_than_2_wr_to_wr;
+                more_than_x0_wr_to_rd           = more_than_2_wr_to_rd;
+                more_than_x0_rd_to_wr_bc        = more_than_2_rd_to_wr_bc;
+                more_than_x0_wr_to_rd_bc        = more_than_2_wr_to_rd_bc;
+                more_than_x0_rd_to_rd_diff_chip = more_than_2_rd_to_rd_diff_chip;
+                more_than_x0_rd_to_wr_diff_chip = more_than_2_rd_to_wr_diff_chip;
+                more_than_x0_wr_to_wr_diff_chip = more_than_2_wr_to_wr_diff_chip;
+                more_than_x0_wr_to_rd_diff_chip = more_than_2_wr_to_rd_diff_chip;
+            end
+        end
+    end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Timing Parameter Comparison Logic
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Activate Monitor
+//  
+//  Monitors the following rank timing parameters:
+//  
+//  - tFAW, four activate window, only four activate is allowed in a specific timing window
+//  - tRRD, activate to activate different bank
+//
+//--------------------------------------------------------------------------------------------------------
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            sel_act_tfaw_shift_out_point <= 0;
+        end
+        else
+        begin
+            if (ENABLE_BETTER_TRRD_EFFICIENCY)
+            begin
+                sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
+            end
+            else
+            begin
+                sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
+            end
+        end
+    end
+    
+    generate
+        genvar t_cs;
+        genvar t_tfaw;
+        for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
+        begin : act_monitor_per_chip
+            //----------------------------------------------------------------------------------------------------
+            // tFAW Monitor
+            //----------------------------------------------------------------------------------------------------
+            reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
+            reg [NUM_OF_TFAW_SHIFT_REG  - 1 : 0] act_tfaw_shift_reg;
+            
+            assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
+            
+            // Shift register to keep track of tFAW
+            // Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
+            // Shift in '1' when there is an activate else shift in '0'
+            // Shift out every clock cycles
+            
+            always @ (*)
+            begin
+            	act_tfaw_shift_reg [2] <= 1'b0;
+            	act_tfaw_shift_reg [1] <= 1'b0;
+            	act_tfaw_shift_reg [0] <= 1'b0;
+            end
+            
+            // Shift register [3]
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    act_tfaw_shift_reg [3] <= 1'b0;
+                end
+                else
+                begin
+                    // Shift in '1' if there is an activate
+                    // else shift in '0'
+                    if (int_do_activate && int_to_chip_r [t_cs])
+                        act_tfaw_shift_reg [3] <= 1'b1;
+                    else
+                        act_tfaw_shift_reg [3] <= 1'b0;
+                end
+            end
+            
+            // Shift register [n : 3]
+            for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
+            begin : tfaw_shift_register
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        act_tfaw_shift_reg [t_tfaw] <= 1'b0;
+                    end
+                    else
+                    begin
+                        act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
+                    end
+                end
+            end
+            
+            // Activate command counter
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    act_tfaw_cmd_cnt <= 0;
+                end
+                else
+                begin
+                    if (int_do_activate && int_to_chip_r [t_cs])
+                    begin
+                        if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
+                            act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
+                        else
+                            act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
+                    end
+                    else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
+                        act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
+                end
+            end
+            
+            // tFAW ready signal
+            always @ (*)
+            begin
+                // If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
+                if (less_than_4_four_act_to_act)
+                begin
+                    act_tfaw_ready_combi [t_cs] = 1'b1;
+                end
+                else
+                begin
+                    if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
+                        act_tfaw_ready_combi [t_cs] = 1'b0;
+                    else if (act_tfaw_cmd_cnt < 3'd4)
+                        act_tfaw_ready_combi [t_cs] = 1'b1;
+                    else
+                        act_tfaw_ready_combi [t_cs] = 1'b0;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    act_tfaw_ready [t_cs] <= 1'b0;
+                end
+                else
+                begin
+                    act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
+                end
+            end
+            
+            //----------------------------------------------------------------------------------------------------
+            // tRRD Monitor
+            //----------------------------------------------------------------------------------------------------
+            reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
+            
+            // tRRD counter
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    act_trrd_cnt <= 0;
+                end
+                else
+                begin
+                    if (int_do_activate && int_to_chip_r [t_cs])
+                    begin
+                        if (ENABLE_BETTER_TRRD_EFFICIENCY)
+                        begin
+                            act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
+                        end
+                        else
+                        begin
+                            act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
+                        end
+                    end
+                    else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
+                    begin
+                        act_trrd_cnt <= act_trrd_cnt + 1'b1;
+                    end
+                end
+            end
+            
+            // tRRD monitor
+            always @ (*)
+            begin
+                if (int_do_activate && int_to_chip_r [t_cs])
+                begin
+                    if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
+                        act_trrd_ready_combi [t_cs] = 1'b1;
+                    else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
+                        act_trrd_ready_combi [t_cs] = 1'b1;
+                    else
+                        act_trrd_ready_combi [t_cs] = 1'b0;
+                end
+                else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
+                    act_trrd_ready_combi [t_cs] = 1'b1;
+                else
+                    act_trrd_ready_combi [t_cs] = 1'b0;
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    act_trrd_ready [t_cs] <= 1'b0;
+                end
+                else
+                begin
+                    act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
+                end
+            end
+            
+            //----------------------------------------------------------------------------------------------------
+            // Overall activate ready
+            //----------------------------------------------------------------------------------------------------
+            always @ (*)
+            begin
+                if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
+                begin
+                    act_ready [t_cs] = 1'b0;
+                end
+                else
+                begin
+                    if (ENABLE_BETTER_TRRD_EFFICIENCY)
+                    begin
+                        act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
+                    end
+                    else
+                    begin
+                        act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Activate Monitor
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Read/Write Monitor
+//  
+//  Monitors the following rank timing parameters:
+//  
+//  - Write to read timing parameter (tWTR)
+//  - Read to write timing parameter
+//  
+//  Missing Features:
+//  
+//  - Burst interrupt
+//  - Burst terminate
+//
+//--------------------------------------------------------------------------------------------------------
+    
+    //----------------------------------------------------------------------------------------------------
+    // Effective Timing Parameters
+    // Only when burst interrupt option is enabled
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            max_local_burst_size <= 0;
+        end
+        else
+        begin
+            max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
+        end
+    end
+    
+    always @ (*)
+    begin
+        if (int_do_burst_chop)
+        begin
+            effective_rd_to_wr_combi           = t_param_rd_to_wr_bc;
+            effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip;
+            effective_wr_to_rd_combi           = t_param_wr_to_rd_bc;
+            effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip;
+        end
+        else if (int_do_burst_terminate)
+        begin
+            if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
+                effective_rd_to_wr_combi           = t_param_rd_to_wr           - (max_local_burst_size - int_effective_size);
+            else
+                effective_rd_to_wr_combi           = 1'b1;
+            
+            if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
+                effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
+            else
+                effective_rd_to_wr_diff_chip_combi = 1'b1;
+            
+            if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
+                effective_wr_to_rd_combi           = t_param_wr_to_rd           - (max_local_burst_size - int_effective_size);
+            else
+                effective_wr_to_rd_combi           = 1'b1;
+            
+            if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
+                effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
+            else
+                effective_wr_to_rd_diff_chip_combi = 1'b1;
+        end
+        else
+        begin
+            effective_rd_to_wr_combi           = effective_rd_to_wr;
+            effective_rd_to_wr_diff_chip_combi = effective_rd_to_wr_diff_chip;
+            effective_wr_to_rd_combi           = effective_wr_to_rd;
+            effective_wr_to_rd_diff_chip_combi = effective_wr_to_rd_diff_chip;
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            effective_rd_to_wr           <= 0;
+            effective_rd_to_wr_diff_chip <= 0;
+            effective_wr_to_rd           <= 0;
+            effective_wr_to_rd_diff_chip <= 0;
+        end
+        else
+        begin
+            effective_rd_to_wr           <= effective_rd_to_wr_combi;
+            effective_rd_to_wr_diff_chip <= effective_rd_to_wr_diff_chip_combi;
+            effective_wr_to_rd           <= effective_wr_to_rd_combi;
+            effective_wr_to_rd_diff_chip <= effective_wr_to_rd_diff_chip_combi;
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Read / Write State Machine
+    //----------------------------------------------------------------------------------------------------
+    generate
+        genvar s_cs;
+        for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
+        begin : rdwr_monitor_per_chip
+            reg [1                      : 0] rdwr_state;
+            reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
+            reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
+            reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
+            reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
+            reg                              int_do_read_this_chip;
+            reg                              int_do_write_this_chip;
+            reg                              int_do_read_diff_chip;
+            reg                              int_do_write_diff_chip;
+            
+            reg                              doing_burst_chop;
+            reg                              doing_burst_terminate;
+            
+            reg                              int_read_ready;
+            reg                              int_write_ready;
+            
+            // Do read/write to this/different chip
+            always @ (*)
+            begin
+                if (int_do_read)
+                begin
+                    if (int_to_chip_c [s_cs])
+                    begin
+                        int_do_read_this_chip = 1'b1;
+                        int_do_read_diff_chip = 1'b0;
+                    end
+                    else
+                    begin
+                        int_do_read_this_chip = 1'b0;
+                        int_do_read_diff_chip = 1'b1;
+                    end
+                end
+                else
+                begin
+                    int_do_read_this_chip = 1'b0;
+                    int_do_read_diff_chip = 1'b0;
+                end
+            end
+            
+            always @ (*)
+            begin
+                if (int_do_write)
+                begin
+                    if (int_to_chip_c [s_cs])
+                    begin
+                        int_do_write_this_chip = 1'b1;
+                        int_do_write_diff_chip = 1'b0;
+                    end
+                    else
+                    begin
+                        int_do_write_this_chip = 1'b0;
+                        int_do_write_diff_chip = 1'b1;
+                    end
+                end
+                else
+                begin
+                    int_do_write_this_chip = 1'b0;
+                    int_do_write_diff_chip = 1'b0;
+                end
+            end
+            
+            // Read write counter to this chip address
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    read_cnt_this_chip  <= 0;
+                    write_cnt_this_chip <= 0;
+                end
+                else
+                begin
+                    if (int_do_read_this_chip)
+                        read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
+                    else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
+                        read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
+                    
+                    if (int_do_write_this_chip)
+                        write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
+                    else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
+                        write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
+                end
+            end
+            
+            // Read write counter to different chip address
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    read_cnt_diff_chip  <= 0;
+                    write_cnt_diff_chip <= 0;
+                end
+                else
+                begin
+                    if (int_do_read_diff_chip)
+                        read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
+                    else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
+                        read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
+                    
+                    if (int_do_write_diff_chip)
+                        write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
+                    else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
+                        write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
+                end
+            end
+            
+            // Doing burst chop signal
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    doing_burst_chop <= 1'b0;
+                end
+                else
+                begin
+                    if (int_do_read || int_do_write)
+                    begin
+                        if (int_do_burst_chop)
+                            doing_burst_chop <= 1'b1;
+                        else
+                            doing_burst_chop <= 1'b0;
+                    end
+                end
+            end
+            
+            // Doing burst terminate signal
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    doing_burst_terminate <= 1'b0;
+                end
+                else
+                begin
+                    if (int_do_read || int_do_write)
+                        doing_burst_terminate <= 1'b0;
+                    else if (int_do_burst_terminate && int_to_chip_c [s_cs]) // to current chip only
+                        doing_burst_terminate <= 1'b1;
+                end
+            end
+            
+            // Register comparison logic for better fMAX
+            reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
+            reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
+            reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
+            reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
+            reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
+            reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
+            reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
+            reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
+            
+            reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
+            reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
+            reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
+            reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           <= 1'b0;
+                    compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
+                    compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           <= 1'b0;
+                    compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
+                    compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           <= 1'b0;
+                    compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
+                    compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           <= 1'b0;
+                    compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
+                end
+                else
+                begin
+                    // Read to this chip comparison
+                    if (int_do_read_this_chip)
+                    begin
+                        if (less_than_x1_rd_to_rd)
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           <= 1'b0;
+                        end
+                        
+                        if (less_than_x1_rd_to_wr)
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           <= 1'b0;
+                        end
+                        
+                        if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           <= 1'b0;
+                        end
+                    end
+                    
+                    // Read to different chip comparison
+                    if (int_do_read_diff_chip)
+                    begin
+                        if (less_than_x1_rd_to_rd_diff_chip)
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
+                        end
+                        
+                        if (less_than_x1_rd_to_wr_diff_chip)
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
+                        end
+                        
+                        if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
+                        end
+                    end
+                    
+                    // Write to this chip comparison
+                    if (int_do_write_this_chip)
+                    begin
+                        if (less_than_x1_wr_to_wr)
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           <= 1'b0;
+                        end
+                        
+                        if (less_than_x1_wr_to_rd)
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           <= 1'b0;
+                        end
+                        
+                        if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           <= 1'b0;
+                        end
+                    end
+                    
+                    // Write to different chip comparison
+                    if (int_do_write_diff_chip)
+                    begin
+                        if (less_than_x1_wr_to_wr_diff_chip)
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
+                        end
+                        
+                        if (less_than_x1_wr_to_rd_diff_chip)
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
+                        end
+                        
+                        if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           <= 1'b0;
+                    compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
+                    compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           <= 1'b0;
+                    compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
+                end
+                else
+                begin
+                    // Read to this chip comparison
+                    if (int_do_read_this_chip)
+                    begin
+                        if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
+                        // We're not comparing against effective_timing_param because it is not loaded yet!
+                        // It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (read_cnt_this_chip >= (effective_rd_to_wr_combi - 1'b1))
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           <= 1'b0;
+                        end
+                    end
+                    
+                    // Read to different chip comparison
+                    if (int_do_read_diff_chip)
+                    begin
+                        if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
+                        // We're not comparing against effective_timing_param because it is not loaded yet!
+                        // It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip_combi - 1'b1))
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
+                        end
+                    end
+                    
+                    // Write to this chip comparison
+                    if (int_do_write_this_chip)
+                    begin
+                        if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
+                        // We're not comparing against effective_timing_param because it is not loaded yet!
+                        // It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (write_cnt_this_chip >= (effective_wr_to_rd_combi - 1'b1))
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           <= 1'b0;
+                        end
+                    end
+                    
+                    // Write to different chip comparison
+                    if (int_do_write_diff_chip)
+                    begin
+                        if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
+                        // We're not comparing against effective_timing_param because it is not loaded yet!
+                        // It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip_combi - 1'b1))
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
+                        end
+                        else
+                        begin
+                            compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            // Read write monitor state machine
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    rdwr_state      <= IDLE;
+                    int_read_ready  <= 1'b0;
+                    int_write_ready <= 1'b0;
+                end
+                else
+                begin
+                    case (rdwr_state)
+                        IDLE :
+                            begin
+                                if (int_do_write_this_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_wr_to_rd_bc)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_wr_to_rd)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    
+                                    if (less_than_x0_wr_to_wr)
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_write_diff_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (less_than_x0_wr_to_rd_diff_chip)
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_wr_to_wr_diff_chip)
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_read_this_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd)
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_rd_to_wr_bc)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_rd_to_wr)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                end
+                                else if (int_do_read_diff_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd_diff_chip)
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_rd_to_wr_diff_chip)
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else
+                                begin
+                                    rdwr_state      <= IDLE;
+                                    int_read_ready  <= 1'b1;
+                                    int_write_ready <= 1'b1;
+                                end
+                            end
+                        WR :
+                            begin
+                                if (int_do_write_this_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_wr_to_rd_bc)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_wr_to_rd)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    
+                                    if (less_than_x0_wr_to_wr)
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_write_diff_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_read_this_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd)
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_rd_to_wr_bc)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_rd_to_wr)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                end
+                                else if (int_do_read_diff_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else
+                                begin
+                                    if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
+                                    begin
+                                        if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd           && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           &&
+                                            compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip   )
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                        
+                                        if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           &&
+                                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip   )
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           &&
+                                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip   )
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                        
+                                        if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           &&
+                                            compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip   )
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                end
+                            end
+                        RD :
+                            begin
+                                if (int_do_write_this_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_wr_to_rd_bc)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_wr_to_rd)
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                    end
+                                    
+                                    if (less_than_x0_wr_to_wr)
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_write_diff_chip)
+                                begin
+                                    rdwr_state <= WR;
+                                    
+                                    if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else if (int_do_read_this_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd)
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (int_do_burst_chop) // burst chop
+                                    begin
+                                        if (less_than_x0_rd_to_wr_bc)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (less_than_x0_rd_to_wr)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                end
+                                else if (int_do_read_diff_chip)
+                                begin
+                                    rdwr_state <= RD;
+                                    
+                                    if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
+                                        int_read_ready  <= 1'b1;
+                                    else
+                                        int_read_ready  <= 1'b0;
+                                    
+                                    if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
+                                        int_write_ready <= 1'b1;
+                                    else
+                                        int_write_ready <= 1'b0;
+                                end
+                                else
+                                begin
+                                    if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
+                                    begin
+                                        if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd          &&
+                                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip  )
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                        
+                                        if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr           && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           &&
+                                            compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip   )
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                    else
+                                    begin
+                                        if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd           && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd           &&
+                                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip   )
+                                            int_read_ready  <= 1'b1;
+                                        else
+                                            int_read_ready  <= 1'b0;
+                                        
+                                        if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr           && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr           &&
+                                            compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
+                                            int_write_ready <= 1'b1;
+                                        else
+                                            int_write_ready <= 1'b0;
+                                    end
+                                end
+                            end
+                        default :
+                            rdwr_state <= IDLE;
+                    endcase
+                end
+            end
+            
+            // Assign read/write ready signal to top
+            always @ (*)
+            begin
+                if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
+                begin
+                    read_ready  [s_cs] = 1'b0;
+                    write_ready [s_cs] = 1'b0;
+                end
+                else
+                begin
+                    if (CFG_RANK_TIMER_OUTPUT_REG)
+                    begin
+                        read_ready  [s_cs] = int_read_ready;
+                        write_ready [s_cs] = int_write_ready;
+                    end
+                    else
+                    begin
+                        read_ready  [s_cs] = int_read_ready  & int_interrupt_ready;
+                        write_ready [s_cs] = int_write_ready & int_interrupt_ready;
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Read/Write Monitor
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Precharge Monitor
+//
+//--------------------------------------------------------------------------------------------------------
+    generate
+        genvar u_cs;
+        for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
+        begin : pch_monitor_per_chip
+            always @ (*)
+            begin
+                if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
+                    pch_ready [u_cs] = 1'b0;
+                else
+                    pch_ready [u_cs] = one;
+            end
+        end
+    endgenerate
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Precharge Monitor
+//
+//--------------------------------------------------------------------------------------------------------
+
+
+
+
+
+
+
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v
new file mode 100644
index 0000000..33154bb
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v
@@ -0,0 +1,1202 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_rdata_path
+# (
+    // module parameter port list
+    parameter
+        CFG_LOCAL_DATA_WIDTH            = 8,
+        CFG_INT_SIZE_WIDTH              = 2,
+        CFG_DATA_ID_WIDTH               = 3,                // number of buckets
+        CFG_LOCAL_ID_WIDTH              = 3,
+        CFG_LOCAL_ADDR_WIDTH            = 32,
+        CFG_BUFFER_ADDR_WIDTH           = 5,
+        CFG_MEM_IF_CS_WIDTH             = 2,
+        CFG_MEM_IF_BA_WIDTH             = 3,
+        CFG_MEM_IF_ROW_WIDTH            = 13,
+        CFG_MEM_IF_COL_WIDTH            = 10,
+        CFG_MAX_READ_CMD_NUM_WIDTH      = 4,                // expected in-flight read commands at a time
+        CFG_RDATA_RETURN_MODE           = "PASSTHROUGH",    // INORDER, PASSTHROUGH
+        CFG_AFI_INTF_PHASE_NUM          = 2,
+        CFG_ERRCMD_FIFO_ADDR_WIDTH      = 3,
+        CFG_DWIDTH_RATIO                = 2,
+        CFG_ECC_MULTIPLES               = 1,
+        CFG_ECC_CODE_WIDTH              = 8,
+        CFG_PORT_WIDTH_TYPE             = 3,
+        CFG_PORT_WIDTH_ENABLE_ECC       = 1,
+        CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
+        CFG_PORT_WIDTH_ENABLE_NO_DM     = 1,
+        CFG_PORT_WIDTH_BURST_LENGTH     = 5,
+        CFG_PORT_WIDTH_ADDR_ORDER       = 2, 
+        CFG_PORT_WIDTH_COL_ADDR_WIDTH   = 9, 
+        CFG_PORT_WIDTH_ROW_ADDR_WIDTH   = 12, 
+        CFG_PORT_WIDTH_BANK_ADDR_WIDTH  = 3, 
+        CFG_PORT_WIDTH_CS_ADDR_WIDTH    = 2,
+		CFG_ERRCMD_FIFO_REG 			= 1								// set 1 to improve timing for errcmd_fifo
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // configuration
+    cfg_type,
+    cfg_enable_ecc,
+    cfg_enable_auto_corr,
+    cfg_enable_no_dm,
+    cfg_burst_length,
+    cfg_addr_order,
+    cfg_col_addr_width,
+    cfg_row_addr_width,
+    cfg_bank_addr_width,
+    cfg_cs_addr_width,
+
+    // command generator & TBP command load interface / cmd update interface
+    rdatap_free_id_valid,
+    rdatap_free_id_dataid,
+    proc_busy,
+    proc_load,
+    proc_load_dataid,
+    proc_read,
+    proc_size,
+    proc_localid,
+
+    // input interface data channel / buffer read interface
+    read_data_valid,                // data sent to either dataid_manager, or input interface
+    read_data,
+    read_data_error,
+    read_data_localid,
+    
+    // Arbiter issued reads interface
+    bg_do_read,
+    bg_to_chipsel,
+    bg_to_bank,
+    bg_to_row,
+    bg_to_column,
+    bg_dataid,
+    bg_localid,
+    bg_size,
+    bg_do_rmw_correct,
+    bg_do_rmw_partial,
+
+    // read data from memory interface
+    ecc_rdata,
+    ecc_rdatav,
+    ecc_sbe,
+    ecc_dbe,
+    ecc_code,
+
+    // ECC Error commands interface, to command generator
+    errcmd_ready,
+    errcmd_valid,
+    errcmd_chipsel,
+    errcmd_bank,
+    errcmd_row,
+    errcmd_column,
+    errcmd_size,
+    errcmd_localid,
+
+    // ECC Error address interface, to ECC block
+    rdatap_rcvd_addr,
+    rdatap_rcvd_cmd,
+    rdatap_rcvd_corr_dropped,
+
+    // RMW fifo interface, to wdatap
+    rmwfifo_data_valid,
+    rmwfifo_data,
+    rmwfifo_ecc_dbe,
+    rmwfifo_ecc_code
+
+);
+
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+    localparam CFG_ECC_RDATA_COUNTER_REG   = 0;                // set to 1 to improve timing
+	localparam CFG_RMW_BIT_WIDTH = 1;
+    localparam CFG_RMW_PARTIAL_BIT_WIDTH = 1;
+    localparam CFG_PENDING_RD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_DATA_ID_WIDTH + CFG_RMW_BIT_WIDTH + CFG_RMW_PARTIAL_BIT_WIDTH;
+    localparam CFG_ERRCMD_FIFO_WIDTH     = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_INT_SIZE_WIDTH + CFG_LOCAL_ID_WIDTH;
+    localparam CFG_INORDER_INFO_FIFO_WIDTH = CFG_INT_SIZE_WIDTH+CFG_LOCAL_ID_WIDTH;
+    localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
+    localparam CFG_RDATA_ERROR_WIDTH = 1;
+    localparam CFG_IN_ORDER_BUFFER_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RDATA_ERROR_WIDTH;
+    localparam CFG_MAX_READ_CMD_NUM = 2**CFG_MAX_READ_CMD_NUM_WIDTH;
+
+    localparam MIN_COL              =   8;
+    localparam MIN_ROW              =   12;
+    localparam MIN_BANK             =   2;
+    localparam MIN_CS               =   1;
+    localparam MAX_COL              = CFG_MEM_IF_COL_WIDTH;
+    localparam MAX_ROW              = CFG_MEM_IF_ROW_WIDTH;
+    localparam MAX_BANK             = CFG_MEM_IF_BA_WIDTH;
+    localparam MAX_CS               = CFG_MEM_IF_CS_WIDTH;
+
+    localparam CFG_IGNORE_NUM_BITS_COL          = log2 (CFG_DWIDTH_RATIO);
+    localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH   = log2 (CFG_LOCAL_ADDR_WIDTH);
+
+    integer j,k,m,n;
+
+
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    input   ctl_clk;
+    input   ctl_reset_n;
+    
+    // configuration
+    input   [CFG_PORT_WIDTH_TYPE- 1:0]              cfg_type;
+    input   [CFG_PORT_WIDTH_ENABLE_ECC-1:0]         cfg_enable_ecc;
+    input   [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0]   cfg_enable_auto_corr;
+    input   [CFG_PORT_WIDTH_ENABLE_NO_DM-1:0]       cfg_enable_no_dm;
+    input   [CFG_PORT_WIDTH_BURST_LENGTH-1:0]       cfg_burst_length;
+
+    input  [CFG_PORT_WIDTH_ADDR_ORDER      - 1 : 0] cfg_addr_order;
+    input  [CFG_PORT_WIDTH_COL_ADDR_WIDTH  - 1 : 0] cfg_col_addr_width;
+    input  [CFG_PORT_WIDTH_ROW_ADDR_WIDTH  - 1 : 0] cfg_row_addr_width;
+    input  [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
+    input  [CFG_PORT_WIDTH_CS_ADDR_WIDTH   - 1 : 0] cfg_cs_addr_width;
+        
+    // command generator & TBP command load interface / cmd update interface
+    output                              rdatap_free_id_valid;
+    output  [CFG_DATA_ID_WIDTH-1:0]     rdatap_free_id_dataid;
+    input                               proc_busy;
+    input                               proc_load;
+    input                               proc_load_dataid;
+    input                               proc_read;
+    input   [CFG_INT_SIZE_WIDTH-1:0]    proc_size;
+    input   [CFG_LOCAL_ID_WIDTH-1:0]    proc_localid;
+
+    // input interface data channel
+    output                              read_data_valid;                
+    output  [CFG_LOCAL_DATA_WIDTH-1:0]  read_data;
+    output                              read_data_error;
+    output  [CFG_LOCAL_ID_WIDTH-1:0]    read_data_localid;
+
+    // Arbiter issued reads interface
+    input   [CFG_AFI_INTF_PHASE_NUM-1:0]                            bg_do_read;
+    input   [CFG_AFI_INTF_PHASE_NUM-1:0]                            bg_do_rmw_correct;
+    input   [CFG_AFI_INTF_PHASE_NUM-1:0]                            bg_do_rmw_partial;
+    input   [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH  ) -1:0]   bg_to_chipsel;
+    input   [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH  ) -1:0]   bg_to_bank;
+    input   [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0]   bg_to_row;
+    input   [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0]   bg_to_column;
+    input   [(                       CFG_DATA_ID_WIDTH    ) -1:0]   bg_dataid;
+    input   [(                       CFG_LOCAL_ID_WIDTH   ) -1:0]   bg_localid;
+    input   [(                       CFG_INT_SIZE_WIDTH   ) -1:0]   bg_size;
+
+    // read data from memory interface
+    input   [CFG_LOCAL_DATA_WIDTH-1:0]                       ecc_rdata;
+    input                                                    ecc_rdatav;
+    input   [CFG_ECC_MULTIPLES - 1 : 0]                      ecc_sbe;
+    input   [CFG_ECC_MULTIPLES - 1 : 0]                      ecc_dbe;
+    input   [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
+
+    // ECC Error commands interface, to command generator
+    input                                 errcmd_ready;
+    output                                errcmd_valid;
+    output    [CFG_MEM_IF_CS_WIDTH-1:0]   errcmd_chipsel;
+    output    [CFG_MEM_IF_BA_WIDTH-1:0]   errcmd_bank;
+    output    [CFG_MEM_IF_ROW_WIDTH-1:0]  errcmd_row;
+    output    [CFG_MEM_IF_COL_WIDTH-1:0]  errcmd_column;
+    output    [CFG_INT_SIZE_WIDTH-1:0]    errcmd_size;
+    output    [CFG_LOCAL_ID_WIDTH-1:0]    errcmd_localid;
+
+    // ECC Error address interface, to ECC block
+    output  [CFG_LOCAL_ADDR_WIDTH-1:0]                      rdatap_rcvd_addr;
+    output                                                  rdatap_rcvd_cmd;
+    output                                                  rdatap_rcvd_corr_dropped;
+
+    // RMW fifo interface, to wdatap
+    output                                                   rmwfifo_data_valid; 
+    output  [CFG_LOCAL_DATA_WIDTH-1:0]                       rmwfifo_data;
+    output  [CFG_ECC_MULTIPLES - 1 : 0]                      rmwfifo_ecc_dbe;
+    output  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    wire    ctl_clk;
+    wire    ctl_reset_n;
+
+    // configuration
+    wire    [CFG_PORT_WIDTH_TYPE- 1:0]                  cfg_type;
+    wire    [CFG_PORT_WIDTH_ENABLE_ECC-1:0]             cfg_enable_ecc;
+    wire    [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0]       cfg_enable_auto_corr;
+    wire    [CFG_PORT_WIDTH_BURST_LENGTH-1:0]           cfg_burst_length;
+
+    wire  [CFG_PORT_WIDTH_ADDR_ORDER      - 1 : 0] cfg_addr_order;
+    wire  [CFG_PORT_WIDTH_COL_ADDR_WIDTH  - 1 : 0] cfg_col_addr_width;
+    wire  [CFG_PORT_WIDTH_ROW_ADDR_WIDTH  - 1 : 0] cfg_row_addr_width;
+    wire  [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
+    wire  [CFG_PORT_WIDTH_CS_ADDR_WIDTH   - 1 : 0] cfg_cs_addr_width;
+        
+    // command generator & TBP command load interface / cmd update interface
+    reg                                 rdatap_free_id_valid;
+    reg     [CFG_DATA_ID_WIDTH-1:0]     rdatap_free_id_dataid;
+    wire                               proc_busy;
+    wire                               proc_load;
+    wire                               proc_load_dataid;
+    wire                               proc_read;
+    wire   [CFG_INT_SIZE_WIDTH-1:0]    proc_size;
+    wire   [CFG_LOCAL_ID_WIDTH-1:0]    proc_localid;
+
+    // input interface data channel
+    reg                              read_data_valid;                
+    reg  [CFG_LOCAL_DATA_WIDTH-1:0]  read_data;
+    reg                              read_data_error;
+    reg  [CFG_LOCAL_ID_WIDTH-1:0]    read_data_localid;
+
+    // Arbiter issued reads interface
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                             bg_do_read;
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                             bg_do_rmw_correct;
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                             bg_do_rmw_partial;
+    wire  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH  ) -1:0]    bg_to_chipsel;
+    wire  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH  ) -1:0]    bg_to_bank;
+    wire  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0]    bg_to_row;
+    wire  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0]    bg_to_column;
+    wire  [(                       CFG_DATA_ID_WIDTH    ) -1:0]    bg_dataid;
+    wire  [(                       CFG_LOCAL_ID_WIDTH   ) -1:0]    bg_localid;
+    wire  [(                       CFG_INT_SIZE_WIDTH   ) -1:0]    bg_size;
+
+    reg   [CFG_AFI_INTF_PHASE_NUM-1:0]                             int_bg_do_read;
+    reg   [CFG_AFI_INTF_PHASE_NUM-1:0]                             int_bg_do_rmw_correct;
+    reg   [CFG_AFI_INTF_PHASE_NUM-1:0]                             int_bg_do_rmw_partial;
+    reg   [CFG_MEM_IF_CS_WIDTH   -1:0]                             int_bg_to_chipsel[CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg   [CFG_MEM_IF_BA_WIDTH   -1:0]                             int_bg_to_bank   [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg   [CFG_MEM_IF_ROW_WIDTH  -1:0]                             int_bg_to_row    [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg   [CFG_MEM_IF_COL_WIDTH  -1:0]                             int_bg_to_column [CFG_AFI_INTF_PHASE_NUM-1:0];
+    reg   [CFG_DATA_ID_WIDTH     -1:0]                             int_bg_dataid;
+    reg   [CFG_LOCAL_ID_WIDTH    -1:0]                             int_bg_localid;
+    reg   [CFG_INT_SIZE_WIDTH    -1:0]                             int_bg_size;
+
+    // read data from memory interface
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                       ecc_rdata;
+    wire                                                     ecc_rdatav;
+    wire    [CFG_ECC_MULTIPLES- 1 : 0]                       ecc_sbe;
+    wire    [CFG_ECC_MULTIPLES- 1 : 0]                       ecc_dbe;
+    wire    [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
+
+    // ECC Error commands interface, to command generator
+    wire                                errcmd_ready;
+    wire                                errcmd_valid;
+    wire    [CFG_MEM_IF_CS_WIDTH-1:0]   errcmd_chipsel;
+    wire    [CFG_MEM_IF_BA_WIDTH-1:0]   errcmd_bank;
+    wire    [CFG_MEM_IF_ROW_WIDTH-1:0]  errcmd_row;
+    wire    [CFG_MEM_IF_COL_WIDTH-1:0]  errcmd_column;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]    errcmd_size;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]    errcmd_localid;
+
+    // RMW fifo interface, to wdatap
+    wire                                                     rmwfifo_data_valid; 
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                       rmwfifo_data;
+    wire    [CFG_ECC_MULTIPLES- 1 : 0]                       rmwfifo_ecc_dbe;
+    wire    [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
+
+    reg                                                     rdatap_rcvd_cmd;
+    reg                                                     rdatap_rcvd_corr_dropped;
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    wire[CFG_INT_SIZE_WIDTH-1:0]                cfg_max_cmd_burstcount;
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_chipsel;
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_bank;
+    reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_row;
+
+    wire                                cmdload_valid;
+    reg  [CFG_MAX_READ_CMD_NUM_WIDTH-1:0]   cmd_counter;
+    reg                                 cmd_counter_full;
+    wire                                cmd_counter_load;
+
+    wire                                free_id_get_ready;
+    wire                                free_id_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]     free_id_dataid;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]free_id_dataid_vector;
+    wire                                allocated_put_ready;
+    wire                                allocated_put_valid;
+    wire                                int_free_id_valid;
+
+    wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_input;
+    wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_output;
+    wire                                 pfifo_output_valid;
+    wire                                 pfifo_input_ready;
+
+    wire                                 rdata_burst_complete;
+    reg                                  rdata_burst_complete_r;
+
+    reg                                  rout_data_valid;                // rout_data sent to dataid_manager
+    reg                                  rout_cmd_valid;                 // rout_cmd sent to dataid_manager
+    reg                                  rout_data_rmwfifo_valid;        // rout_data sent to rmwfifo
+    reg                                  rout_cmd_rmwfifo_valid;         // rout_cmd  sent to rmwfifo
+    wire                                 rout_rmw_rmwpartial;
+    reg                                  rout_data_error;
+    reg                                  rout_sbecmd_valid;
+    reg                                  rout_errnotify_valid;
+    wire [CFG_LOCAL_DATA_WIDTH-1:0]      rout_data;
+    wire [CFG_DATA_ID_WIDTH-1:0]         rout_data_dataid;
+    wire [CFG_LOCAL_ID_WIDTH-1:0]        rout_data_localid;
+    wire [CFG_INT_SIZE_WIDTH-1:0]        rout_data_burstcount;
+    wire [CFG_ECC_MULTIPLES- 1 : 0]      rout_ecc_dbe;
+    wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rout_ecc_code;
+
+
+    reg                                 pfifo_input_do_read;
+    reg                                 pfifo_input_rmw;
+    reg                                 pfifo_input_rmw_partial;
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]   pfifo_input_chipsel;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]   pfifo_input_bank;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]  pfifo_input_row;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]  pfifo_input_column;
+    reg     [CFG_DATA_ID_WIDTH-1:0]     pfifo_input_dataid;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]    pfifo_input_localid;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]    pfifo_input_size;
+
+    reg                                 mux_pfifo_input_rmw             [CFG_AFI_INTF_PHASE_NUM -1 : 0]; 
+    reg                                 mux_pfifo_input_rmw_partial     [CFG_AFI_INTF_PHASE_NUM -1 : 0];
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]   mux_pfifo_input_chipsel         [CFG_AFI_INTF_PHASE_NUM -1 : 0];
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]   mux_pfifo_input_bank            [CFG_AFI_INTF_PHASE_NUM -1 : 0];
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]  mux_pfifo_input_row             [CFG_AFI_INTF_PHASE_NUM -1 : 0];
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]  mux_pfifo_input_column          [CFG_AFI_INTF_PHASE_NUM -1 : 0];
+
+    wire                                pfifo_rmw;
+    wire                                pfifo_rmw_partial;
+    wire    [CFG_MEM_IF_CS_WIDTH-1:0]   pfifo_chipsel;
+    wire    [CFG_MEM_IF_BA_WIDTH-1:0]   pfifo_bank;
+    wire    [CFG_MEM_IF_ROW_WIDTH-1:0]  pfifo_row;
+    wire    [CFG_MEM_IF_COL_WIDTH-1:0]  pfifo_column;
+    wire    [CFG_MEM_IF_COL_WIDTH-1:0]  pfifo_column_burst_aligned;
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]   pfifo_chipsel_r;
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]   pfifo_bank_r;
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]  pfifo_row_r;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]  pfifo_column_r;
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]  pfifo_column_burst_aligned_r;
+    wire    [CFG_DATA_ID_WIDTH-1:0]     pfifo_dataid;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]    pfifo_localid;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]    pfifo_size;
+    reg     [CFG_LOCAL_ADDR_WIDTH-1:0]  pfifo_addr;
+
+    wire    [CFG_INT_SIZE_WIDTH-1:0]    ecc_rdata_current_count;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]    ecc_rdata_counter;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]    ecc_rdatavalid_count;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]    ecc_rdata_burst_complete_count;
+    reg                                 ecc_sbe_cmd_detected;
+    reg                                 ecc_dbe_cmd_detected;
+
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                dataid_array_valid;
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                dataid_array_data_ready;
+    reg     [CFG_BUFFER_ADDR_WIDTH-1:0]                 dataid_array_burstcount         [CFG_DATAID_ARRAY_DEPTH-1:0];
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]                    dataid_array_localid            [CFG_DATAID_ARRAY_DEPTH-1:0];
+
+    wire                                                inordr_id_data_complete;
+    reg                                                 inordr_id_data_complete_r;
+    wire                                                inordr_id_valid;
+    wire                                                inordr_id_list_valid;
+    wire                                                inordr_read_data_valid;
+    reg                                                 inordr_read_data_valid_r;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                  inordr_read_data;
+    wire                                                inordr_read_data_error;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                     inordr_id_dataid;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                inordr_id_dataid_vector;
+    wire    [CFG_LOCAL_ID_WIDTH-1:0]                    inordr_id_localid;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]                    inordr_id_localid_r;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                    inordr_data_counter;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]                    inordr_data_counter_plus_1;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    inordr_next_data_counter;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    inordr_id_expected_burstcount;
+    reg     [CFG_DATAID_ARRAY_DEPTH-1:0]                mux_inordr_data_ready;
+
+    wire                                                inordr_info_input_ready;
+    wire                                                inordr_info_output_valid;
+    wire    [CFG_INORDER_INFO_FIFO_WIDTH-1:0]           inordr_info_input;
+    wire    [CFG_INORDER_INFO_FIFO_WIDTH-1:0]           inordr_info_output;
+
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                 buffwrite_address;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    buffwrite_offset;
+    wire    [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0]        buffwrite_data;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                 buffread_address;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    buffread_offset;
+    wire    [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0]        buffread_data;
+
+    wire                                                int_ecc_sbe;
+    wire                                                int_ecc_dbe;
+
+    wire                                                errcmd_fifo_in_cmddropped;
+    reg                                                 errcmd_fifo_in_cmddropped_r;
+    wire                                                errcmd_fifo_in_ready;
+    wire                                                errcmd_fifo_in_valid_wire;
+    wire    [CFG_ERRCMD_FIFO_WIDTH-1:0]                 errcmd_fifo_in_wire;
+    wire    [CFG_ERRCMD_FIFO_WIDTH-1:0]                 errcmd_fifo_out;
+    reg	                                                errcmd_fifo_in_valid;
+    reg     [CFG_ERRCMD_FIFO_WIDTH-1:0]                 errcmd_fifo_in;
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    //
+    // READ DATA MAIN OUTPUT MUX
+    //
+
+    generate
+    begin : gen_rdata_output_mux
+        if (CFG_RDATA_RETURN_MODE == "PASSTHROUGH")
+        begin
+            always @ (*) 
+            begin
+                read_data_valid         = rout_data_valid;
+                read_data               = rout_data;
+                read_data_error         = rout_data_error;
+                read_data_localid       = rout_data_localid;
+
+                rdatap_free_id_valid    = ~cmd_counter_full;
+                rdatap_free_id_dataid   = 0;
+            end
+        end
+        else
+        begin
+            always @ (*) 
+            begin
+                read_data_valid         = inordr_read_data_valid_r;
+                read_data               = inordr_read_data;
+                read_data_error         = inordr_read_data_error;
+                read_data_localid       = inordr_id_localid_r;
+
+                rdatap_free_id_valid    = ~cmd_counter_full & free_id_valid;
+                rdatap_free_id_dataid   = free_id_dataid;
+            end
+        end
+    end
+    endgenerate
+
+
+    // 
+    // RDATA_ROUTER
+    //
+
+    // mux to select correct burst gen output phase for read command
+    // assumes bg_do_read only asserted for 1 of the CFG_AFI_INTF_PHASE_NUM
+    
+    genvar rdp_k;
+    generate
+        for (rdp_k = 0; rdp_k < CFG_AFI_INTF_PHASE_NUM; rdp_k = rdp_k + 1) 
+        begin : gen_bg_afi_signal_decode
+
+            always @ (*) 
+            begin
+
+                int_bg_do_read              [rdp_k] = bg_do_read        [rdp_k];     
+                int_bg_do_rmw_correct       [rdp_k] = bg_do_rmw_correct [rdp_k]; 
+                int_bg_do_rmw_partial       [rdp_k] = bg_do_rmw_partial [rdp_k]; 
+
+                int_bg_to_chipsel           [rdp_k] = bg_to_chipsel [(((rdp_k+1)*CFG_MEM_IF_CS_WIDTH )-1):(rdp_k*CFG_MEM_IF_CS_WIDTH )]; 
+                int_bg_to_bank              [rdp_k] = bg_to_bank    [(((rdp_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(rdp_k*CFG_MEM_IF_BA_WIDTH )]; 
+                int_bg_to_row               [rdp_k] = bg_to_row     [(((rdp_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(rdp_k*CFG_MEM_IF_ROW_WIDTH)]; 
+                int_bg_to_column            [rdp_k] = bg_to_column  [(((rdp_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(rdp_k*CFG_MEM_IF_COL_WIDTH)]; 
+
+            end
+
+        end
+    endgenerate
+
+    always @ (*) 
+    begin
+           int_bg_dataid                       = bg_dataid;
+           int_bg_localid                      = bg_localid; 
+           int_bg_size                         = bg_size;    
+    end
+
+
+    always @ (*) 
+    begin
+       mux_pfifo_input_rmw             [0]     = (int_bg_do_read [0]) ?  int_bg_do_rmw_correct  [0] : 0;
+       mux_pfifo_input_rmw_partial     [0]     = (int_bg_do_read [0]) ?  int_bg_do_rmw_partial  [0] : 0;
+       mux_pfifo_input_chipsel         [0]     = (int_bg_do_read [0]) ?  int_bg_to_chipsel      [0] : 0;
+       mux_pfifo_input_bank            [0]     = (int_bg_do_read [0]) ?  int_bg_to_bank         [0] : 0;
+       mux_pfifo_input_row             [0]     = (int_bg_do_read [0]) ?  int_bg_to_row          [0] : 0;
+       mux_pfifo_input_column          [0]     = (int_bg_do_read [0]) ?  int_bg_to_column       [0] : 0;
+    end
+    
+    genvar rdp_j;
+    generate
+        for (rdp_j = 1; rdp_j < CFG_AFI_INTF_PHASE_NUM; rdp_j = rdp_j + 1) 
+        begin : gen_bg_afi_phase_mux
+            always @ (*) 
+            begin
+                mux_pfifo_input_rmw             [rdp_j]     = mux_pfifo_input_rmw             [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct  [rdp_j] : 0);
+                mux_pfifo_input_rmw_partial     [rdp_j]     = mux_pfifo_input_rmw_partial     [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial  [rdp_j] : 0);
+                mux_pfifo_input_chipsel         [rdp_j]     = mux_pfifo_input_chipsel         [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel      [rdp_j] : 0);
+                mux_pfifo_input_bank            [rdp_j]     = mux_pfifo_input_bank            [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank         [rdp_j] : 0);
+                mux_pfifo_input_row             [rdp_j]     = mux_pfifo_input_row             [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row          [rdp_j] : 0);
+                mux_pfifo_input_column          [rdp_j]     = mux_pfifo_input_column          [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column       [rdp_j] : 0);
+            end
+        end
+    endgenerate    
+
+     always @ (*) 
+     begin
+        pfifo_input_do_read         = |int_bg_do_read;
+
+        pfifo_input_rmw             = mux_pfifo_input_rmw             [CFG_AFI_INTF_PHASE_NUM-1]; 
+        pfifo_input_rmw_partial     = mux_pfifo_input_rmw_partial     [CFG_AFI_INTF_PHASE_NUM-1];
+        pfifo_input_chipsel         = mux_pfifo_input_chipsel         [CFG_AFI_INTF_PHASE_NUM-1];
+        pfifo_input_bank            = mux_pfifo_input_bank            [CFG_AFI_INTF_PHASE_NUM-1];
+        pfifo_input_row             = mux_pfifo_input_row             [CFG_AFI_INTF_PHASE_NUM-1];
+        pfifo_input_column          = mux_pfifo_input_column          [CFG_AFI_INTF_PHASE_NUM-1];
+        pfifo_input_dataid          = int_bg_dataid                                             ;
+        pfifo_input_localid         = int_bg_localid                                            ;
+        pfifo_input_size            = int_bg_size                                               ;
+     end
+
+
+
+    // format for pfifo_input & pfifo_output must be same
+    assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
+    assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
+
+    // read data for this command has been fully received from memory
+    assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
+
+    alt_mem_ddrx_fifo
+    #(
+        .CTL_FIFO_DATA_WIDTH (CFG_PENDING_RD_FIFO_WIDTH),
+        .CTL_FIFO_ADDR_WIDTH (CFG_MAX_READ_CMD_NUM_WIDTH)
+    )
+    pending_rd_fifo
+    (
+     .ctl_clk            (ctl_clk),
+     .ctl_reset_n        (ctl_reset_n),
+
+     .get_ready          (rdata_burst_complete),
+     .get_valid          (pfifo_output_valid),
+     .get_data           (pfifo_output),   
+
+     .put_ready          (pfifo_input_ready),                      // no back-pressure allowed
+     .put_valid          (pfifo_input_do_read),    
+     .put_data           (pfifo_input)
+    );
+
+
+    assign cmd_counter_load     = ~proc_busy & proc_load & proc_read;
+    assign cmdload_valid        = cmd_counter_load & proc_load_dataid;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            cmd_counter      <= 0;
+            cmd_counter_full <= 1'b0;
+        end
+        else
+        begin
+
+            if (cmd_counter_load & rdata_burst_complete)
+            begin
+                cmd_counter      <= cmd_counter;
+                cmd_counter_full <= cmd_counter_full;
+            end
+            else if (cmd_counter_load)
+            begin
+                cmd_counter <= cmd_counter + 1;
+                
+                if (cmd_counter == {{(CFG_MAX_READ_CMD_NUM_WIDTH - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
+                begin
+                    cmd_counter_full <= 1'b1;
+                end
+                else
+                begin
+                    cmd_counter_full <= 1'b0;
+                end
+            end
+            else if (rdata_burst_complete)
+            begin
+                cmd_counter      <= cmd_counter - 1;
+                cmd_counter_full <= 1'b0;
+            end
+        end
+    end
+
+    assign rout_data            = ecc_rdata;
+    assign rout_data_dataid     = pfifo_dataid;
+    assign rout_data_localid    = pfifo_localid;
+    assign rout_data_burstcount = ecc_rdata_current_count;
+    assign rout_rmw_rmwpartial  = (pfifo_rmw | pfifo_rmw_partial);
+    assign rout_ecc_dbe         = ecc_dbe;
+    assign rout_ecc_code        = ecc_code;
+
+    always @ (*) 
+    begin
+        //rout_data_valid         = 0;
+        //rout_cmd_valid          = 0;
+        rout_data_rmwfifo_valid = 0;
+        rout_cmd_rmwfifo_valid  = 0;
+        rout_sbecmd_valid       = 0;
+        rout_data_error         = 0;
+        rout_errnotify_valid    = 0;
+
+        
+        if (~cfg_enable_ecc & ~cfg_enable_no_dm)
+        begin
+            rout_data_valid = ecc_rdatav;
+            rout_cmd_valid = rout_data_valid & rdata_burst_complete;
+        end
+        else
+        begin
+
+            rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
+            rout_data_valid         = ecc_rdatav & ~rout_rmw_rmwpartial;
+            rout_cmd_valid          = rout_data_valid & rdata_burst_complete;
+
+            rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
+
+
+            rout_data_error = int_ecc_dbe;
+
+            rout_errnotify_valid =  ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
+
+            if (cfg_enable_auto_corr)
+            begin
+                rout_sbecmd_valid =  rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
+            end
+
+        end
+        
+    end
+
+    
+    // rmwfifo interface
+    assign rmwfifo_data_valid           = rout_data_rmwfifo_valid;
+    assign rmwfifo_data                 = rout_data;
+    assign rmwfifo_ecc_dbe              = rout_ecc_dbe;
+    assign rmwfifo_ecc_code             = rout_ecc_code;
+
+
+    // ecc_sbe_cmd_detected 
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            ecc_sbe_cmd_detected <= 0;            
+            ecc_dbe_cmd_detected <= 0;            
+        end
+        else
+        begin
+            if (rdata_burst_complete)
+            begin
+                ecc_sbe_cmd_detected <= 0;
+                ecc_dbe_cmd_detected <= 0;
+            end
+            else if (int_ecc_sbe)
+            begin
+                ecc_sbe_cmd_detected <= 1;
+            end
+            else if (int_ecc_dbe)
+            begin
+                ecc_dbe_cmd_detected <= 1;
+            end
+        end
+    end
+
+    assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
+    assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
+
+    //
+    // ECC_RDATA counter
+    //
+
+    assign ecc_rdata_current_count = (CFG_ECC_RDATA_COUNTER_REG) ? ecc_rdata_counter : ecc_rdatavalid_count;
+    assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
+    assign ecc_rdata_burst_complete_count = pfifo_size;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            ecc_rdata_counter <= 0;
+        end
+        else
+        begin
+
+            if (rdata_burst_complete)
+            begin
+                ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
+            end
+            else
+            begin
+                ecc_rdata_counter <= ecc_rdatavalid_count;
+            end
+
+        end
+    end
+
+    assign errcmd_fifo_in_valid_wire = rout_sbecmd_valid;
+    assign errcmd_fifo_in_wire = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
+    assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
+    assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid_wire;
+    assign cfg_max_cmd_burstcount = (cfg_burst_length / CFG_DWIDTH_RATIO);
+
+    // DDR3, pfifo_column_burst_aligned is burst length 8 aligned
+    // DDR2, pfifo_column is already burst aligned
+    assign pfifo_column_burst_aligned = (cfg_type == `MMR_TYPE_DDR3) ?  {pfifo_column[(CFG_MEM_IF_COL_WIDTH-1):3],{3{1'b0}} } : pfifo_column;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            pfifo_chipsel_r              <= 0;
+            pfifo_bank_r                 <= 0;
+            pfifo_row_r                  <= 0;
+            pfifo_column_r               <= 0;
+            pfifo_column_burst_aligned_r <= 0;
+        end
+        else
+        begin
+            pfifo_chipsel_r              <= pfifo_chipsel             ;
+            pfifo_bank_r                 <= pfifo_bank                ;
+            pfifo_row_r                  <= pfifo_row                 ;
+            pfifo_column_r               <= pfifo_column              ;
+            pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
+        end
+    end
+   
+	generate
+		if (CFG_ERRCMD_FIFO_REG == 1)
+		begin
+			always @ (posedge ctl_clk	or negedge ctl_reset_n)
+				begin
+				if (!ctl_reset_n)
+				begin
+					errcmd_fifo_in_valid	<= 1'b0;
+					errcmd_fifo_in			<= {CFG_ERRCMD_FIFO_WIDTH{1'b0}};
+				end else
+				begin
+					errcmd_fifo_in_valid	<= errcmd_fifo_in_valid_wire;
+					errcmd_fifo_in			<= errcmd_fifo_in_wire;
+				end
+			 end	
+		end else // (CFG_ERRCMD_FIFO_REG == 0)
+		begin
+			always @ (*)
+			begin
+				errcmd_fifo_in_valid		= errcmd_fifo_in_valid_wire;
+				errcmd_fifo_in				= errcmd_fifo_in_wire;
+			end
+		end
+	endgenerate   
+	
+    alt_mem_ddrx_fifo
+    # (
+        .CTL_FIFO_DATA_WIDTH             (CFG_ERRCMD_FIFO_WIDTH),
+        .CTL_FIFO_ADDR_WIDTH             (CFG_ERRCMD_FIFO_ADDR_WIDTH)
+    )
+    errcmd_fifo_inst
+    (
+        .ctl_clk		(ctl_clk),
+        .ctl_reset_n	(ctl_reset_n),
+
+        .get_ready		(errcmd_ready && cfg_enable_auto_corr),
+        .get_valid		(errcmd_valid),
+        .get_data		(errcmd_fifo_out),   
+
+        .put_ready		(errcmd_fifo_in_ready),
+        .put_valid		(errcmd_fifo_in_valid),
+        .put_data       (errcmd_fifo_in)
+
+    );
+
+
+    // 
+    // error address information for MMR's
+    //
+    //  - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
+    //  - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register 
+    //    rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see SPR:362993
+    //
+
+    assign rdatap_rcvd_addr                      = pfifo_addr;
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            rdata_burst_complete_r                  <= 0;
+            errcmd_fifo_in_cmddropped_r             <= 0;
+
+            rdatap_rcvd_cmd                         <= 0;
+            rdatap_rcvd_corr_dropped                <= 0;
+        end
+        else
+        begin
+
+            rdata_burst_complete_r                  <= rdata_burst_complete;
+            errcmd_fifo_in_cmddropped_r             <= errcmd_fifo_in_cmddropped;
+
+            rdatap_rcvd_cmd                         <= rdata_burst_complete;
+            rdatap_rcvd_corr_dropped                <= errcmd_fifo_in_cmddropped;
+        end
+    end
+
+
+    // generate local address from chip, bank, row, column addresses
+    always @(*) 
+    begin : addr_loop
+
+        pfifo_addr = 0;
+
+        // column
+        pfifo_addr[MIN_COL - CFG_IGNORE_NUM_BITS_COL - 1 : 0] = pfifo_column_burst_aligned_r[MIN_COL - 1 : CFG_IGNORE_NUM_BITS_COL];    
+        for (n=MIN_COL; n<MAX_COL; n=n+1'b1) begin
+            if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in CSR using cfg_col_addr_width
+                 pfifo_addr[n - CFG_IGNORE_NUM_BITS_COL] = pfifo_column_burst_aligned_r[n]; 
+            end
+        end
+
+        // row
+        for (j=0; j<MIN_ROW; j=j+1'b1) begin    //The purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
+            pfifo_addr[j + cfg_addr_bitsel_row] =  pfifo_row_r[j];
+        end
+        for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin               
+            if(j < cfg_row_addr_width) begin    // bit of row_addr can be configured in CSR using cfg_row_addr_width
+                pfifo_addr[j + cfg_addr_bitsel_row] =  pfifo_row_r[j];
+            end
+        end
+
+        // bank
+        for (k=0; k<MIN_BANK; k=k+1'b1) begin    //The purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
+            pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
+        end
+        for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin               
+            if(k < cfg_bank_addr_width) begin   // bit of bank_addr can be configured in CSR using cfg_bank_addr_width
+                pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
+            end
+         end
+
+        // cs
+        m = 0;
+        if (cfg_cs_addr_width > 1'b0) begin    //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
+            for (m=0; m<MIN_CS; m=m+1'b1) begin  //The purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
+                pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m]; 
+            end
+            for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin                
+                if(m < cfg_cs_addr_width) begin     // bit of cs_addr can be configured in CSR using cfg_cs_addr_width
+                    pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m]; 
+                end    
+            end
+        end
+
+    end
+
+
+
+    // pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            cfg_addr_bitsel_chipsel <=  0;
+            cfg_addr_bitsel_bank    <=  0;
+            cfg_addr_bitsel_row     <=  0;
+        end
+        else
+        begin
+            //row
+            if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
+                cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
+            else if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
+                cfg_addr_bitsel_row <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
+            else  // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
+
+            // bank
+            if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
+                cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
+            else  // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                cfg_addr_bitsel_bank <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
+
+            //chipsel
+            if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
+                cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL; 
+            else  // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
+                cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL; 
+
+        end
+    end
+
+
+    //
+    // Everything below is for
+    // CFG_RDATA_RETURN_MODE == INORDER support
+    //
+
+    generate
+    begin : gen_rdata_return_inorder
+    if (CFG_RDATA_RETURN_MODE == "INORDER")
+    begin
+
+
+        //
+        // DATAID MANAGEMENT
+        //
+
+        genvar i;
+        for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1) 
+        begin : gen_dataid_array
+
+            assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
+
+            // dataid_array
+            always @ (posedge ctl_clk or negedge ctl_reset_n) 
+            begin
+                if (~ctl_reset_n)
+                begin
+                    dataid_array_data_ready[i]  <= 1'b0;
+                    dataid_array_burstcount[i]  <= 0;
+                    dataid_array_localid   [i]  <= 0;
+                end
+                else
+                begin
+                
+                    // update command
+                    if (cmdload_valid & free_id_dataid_vector[i])
+                    begin
+                       dataid_array_burstcount[i]     <= proc_size;
+                    end
+
+
+                    // writing data to buffer
+                    if (rout_data_valid & (rout_data_dataid == i))
+                    begin
+                       dataid_array_data_ready[i]  <= 1'b1;
+                       dataid_array_localid[i]     <= rout_data_localid;
+                    end
+
+                    // completed reading data from buffer
+                    if (inordr_id_data_complete & inordr_id_dataid_vector[i])
+                    begin
+                       dataid_array_data_ready[i]  <= 1'b0;
+                       dataid_array_burstcount[i]  <= 0;            
+                    end
+                end
+            end
+            
+            // dataid_array output decode mux
+            always @ (*) 
+            begin
+                if (inordr_id_valid & inordr_id_dataid_vector[i])
+                begin
+                    mux_inordr_data_ready[i] = dataid_array_data_ready[i];
+                end
+                else
+                begin
+                    mux_inordr_data_ready[i] = 1'b0;
+                end
+            end
+
+        end
+
+        assign inordr_read_data_valid = |mux_inordr_data_ready;
+
+
+
+        // 
+        // FREE & ALLOCATED DATAID LIST 
+        //
+
+        assign free_id_get_ready    = cmdload_valid;
+        assign allocated_put_valid  = free_id_get_ready & free_id_valid;
+
+        // list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, SPR:358527
+        assign free_id_valid        = int_free_id_valid & inordr_info_input_ready;
+        assign inordr_id_valid      = inordr_id_list_valid & inordr_info_output_valid;
+
+        alt_mem_ddrx_list
+        #(
+            .CTL_LIST_WIDTH                     (CFG_DATA_ID_WIDTH),
+            .CTL_LIST_DEPTH                     (CFG_DATAID_ARRAY_DEPTH),
+            .CTL_LIST_INIT_VALUE_TYPE           ("INCR"),
+            .CTL_LIST_INIT_VALID                ("VALID")
+        )
+        list_freeid_inst
+        (
+         .ctl_clk                               (ctl_clk),
+         .ctl_reset_n                           (ctl_reset_n),
+                                                                            
+         .list_get_entry_ready                  (free_id_get_ready),
+         .list_get_entry_valid                  (int_free_id_valid),
+         .list_get_entry_id                     (free_id_dataid),   
+         .list_get_entry_id_vector              (free_id_dataid_vector),   
+        
+         // ready can be ignored, list entry availability is guaranteed
+         .list_put_entry_ready                  (),                             
+         .list_put_entry_valid                  (inordr_id_data_complete),         
+         .list_put_entry_id                     (inordr_id_dataid)
+        );
+
+        alt_mem_ddrx_list
+        #(
+            .CTL_LIST_WIDTH                     (CFG_DATA_ID_WIDTH),
+            .CTL_LIST_DEPTH                     (CFG_DATAID_ARRAY_DEPTH),
+            .CTL_LIST_INIT_VALUE_TYPE           ("ZERO"),
+            .CTL_LIST_INIT_VALID                ("INVALID")
+        )
+        list_allocated_id_inst
+        (
+         .ctl_clk                               (ctl_clk),
+         .ctl_reset_n                           (ctl_reset_n),
+                                                                                   
+         .list_get_entry_ready                  (inordr_id_data_complete),
+         .list_get_entry_valid                  (inordr_id_list_valid),
+         .list_get_entry_id                     (inordr_id_dataid),   
+         .list_get_entry_id_vector              (inordr_id_dataid_vector),   
+
+         // allocated_put_ready can be ignored, list entry availability is guaranteed
+         .list_put_entry_ready                  (allocated_put_ready),
+         .list_put_entry_valid                  (allocated_put_valid),    
+         .list_put_entry_id                     (free_id_dataid)
+        );
+
+        // format for inordr_info_input & inordr_info_output must be same
+        assign inordr_info_input = {proc_localid,proc_size};
+        assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
+
+        alt_mem_ddrx_fifo
+        # (
+            .CTL_FIFO_DATA_WIDTH             (CFG_INORDER_INFO_FIFO_WIDTH),
+            .CTL_FIFO_ADDR_WIDTH             (CFG_DATA_ID_WIDTH)
+        )
+        inordr_info_fifo_inst
+        (
+            .ctl_clk		(ctl_clk),
+            .ctl_reset_n	(ctl_reset_n),
+
+            .get_ready		(inordr_id_data_complete),
+            .get_valid		(inordr_info_output_valid),
+            .get_data		(inordr_info_output),   
+
+            .put_ready		(inordr_info_input_ready),
+            .put_valid		(allocated_put_valid),
+            .put_data       (inordr_info_input)
+
+        );
+
+        //
+        // IN-ORDER READ MANAGER
+        //
+
+        always @ (posedge ctl_clk or negedge ctl_reset_n) 
+        begin
+            if (~ctl_reset_n)
+            begin
+                inordr_data_counter        <= 0;
+                inordr_data_counter_plus_1 <= 0;
+                inordr_read_data_valid_r   <= 0;
+                inordr_id_data_complete_r  <= 0;
+                inordr_id_localid_r        <= 0;
+            end
+            else
+            begin
+                if (inordr_id_data_complete)
+                begin
+                    inordr_data_counter        <= 0;
+                    inordr_data_counter_plus_1 <= 1;
+                end
+                else
+                begin
+                    inordr_data_counter        <= inordr_next_data_counter;
+                    inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
+                end
+
+                inordr_id_localid_r     <= inordr_id_localid;
+
+                // original signal used to read from buffer
+                // _r version used to pop the fifos
+                inordr_read_data_valid_r    <=  inordr_read_data_valid;
+                inordr_id_data_complete_r   <= inordr_id_data_complete;
+            end
+        end
+
+        assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
+        assign inordr_id_data_complete  = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
+        
+        //
+        // BUFFER
+        //
+        assign buffwrite_offset = ecc_rdata_counter;
+        assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
+        assign buffwrite_data   = {rout_data_error,rout_data};
+
+        assign buffread_offset = inordr_data_counter;
+        assign buffread_address = {inordr_id_dataid,buffread_offset};
+        assign {inordr_read_data_error,inordr_read_data} = buffread_data;
+
+        alt_mem_ddrx_buffer                                                 
+        # (                                                                 
+            .ADDR_WIDTH                         (CFG_BUFFER_ADDR_WIDTH),
+            .DATA_WIDTH                         (CFG_IN_ORDER_BUFFER_DATA_WIDTH) 
+        )                                                                   
+        in_order_buffer_inst                                               
+        (                                                                   
+            // port list                                                    
+            .ctl_clk                            (ctl_clk),
+            .ctl_reset_n                        (ctl_reset_n),
+                                                                            
+            // write interface                                              
+            .write_valid                        (rout_data_valid),
+            .write_address                      (buffwrite_address),
+            .write_data                         (buffwrite_data),
+                                                                            
+            // read interface                                               
+            .read_valid                         (inordr_read_data_valid),
+            .read_address                       (buffread_address),
+            .read_data                          (buffread_data)
+        );
+
+    end
+    end
+    endgenerate
+
+
+    function integer log2; 
+       input [31:0] value; 
+       integer    i; 
+       begin 
+          log2 = 0; 
+          for(i = 0; 2**i < value; i = i + 1) 
+       log2 = i + 1; 
+       end 
+    endfunction    
+
+endmodule
+
+//
+// assert
+//
+// - rdatap_free_id_valid XOR rdatap_allocated_put_ready must always be 1
+// - CFG_BUFFER_ADDR_WIDTH must be >= CFG_INT_SIZE_WIDTH. must have enough location to store 1 dram command worth of data
+// - put_ready goes low
+// - ecc_rdatav is high, but pfifo_output_valid is low
+// - buffer size must be dataid x max size per command
+// - is rdata_burst_complete allowed to be high every cycle?
+// - CFG_BUFFER_ADDR_WIDTH > CFG_DATA_ID_WIDTH
+// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
+// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
+// - cmd_counter_full & cmdload_valid
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v
new file mode 100644
index 0000000..400eb5a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v
@@ -0,0 +1,4108 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10036
+
+///////////////////////////////////////////////////////////////////////////////
+// Title         : DDR controller AFi interfacing block
+//
+// File          : afi_block.v
+//
+// Abstract      : AFi block
+///////////////////////////////////////////////////////////////////////////////
+
+//Things to check
+//1. Does afi_wlat need to be registered?
+//2. Does ecc_wdata_fifo_read generation changes with ECC
+//3. Why in ddrx controller int_dqs_burst and int_wdata_valid signals are registered when CFG_OUTPUT_REGD is 1. Why complex logic instead of simple registering??
+//4. We need rdwr_data_valid signal from arbiter to determine how many datas are valid within one dram burst
+//5. Do we need to end rdwr_data_valid with doing_write to generate ecc_wdata_fifo_read? Yes
+//6. Look at all comments and SPRs for old ddrx afi block
+//7. Currently additive_latency, ECC, HR features are not supported
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_rdwr_data_tmg
+    # (parameter
+        CFG_DWIDTH_RATIO              =    2,
+        CFG_MEM_IF_CHIP               =    1,
+        CFG_MEM_IF_DQ_WIDTH           =    8,
+        CFG_MEM_IF_DQS_WIDTH          =    1,
+        CFG_MEM_IF_DM_WIDTH           =    1,
+        CFG_WLAT_BUS_WIDTH            =    6,
+        CFG_DRAM_WLAT_GROUP           =    1,
+        CFG_DATA_ID_WIDTH             =    10,
+        CFG_WDATA_REG                 =    0,
+        CFG_ECC_ENC_REG               =    0,
+        CFG_AFI_INTF_PHASE_NUM        =    2,
+        CFG_PORT_WIDTH_ENABLE_ECC     =    1,
+        CFG_PORT_WIDTH_OUTPUT_REGD    =    1,
+        CFG_CTL_ARBITER_TYPE          =    "ROWCOL",
+        CFG_USE_SHADOW_REGS           =    0
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // configuration
+        cfg_enable_ecc,
+        cfg_output_regd,
+        cfg_output_regd_for_afi_output,
+        
+        //Arbiter command input
+        bg_do_read,
+        bg_do_write,
+        bg_doing_read,
+        bg_doing_write,
+        bg_rdwr_data_valid,        //Required for user burst length lesser than dram burst length
+        dataid,
+        bg_do_rmw_correct,
+        bg_do_rmw_partial,
+        bg_to_chip,
+        
+        //Inputs from ECC/WFIFO blocks
+        ecc_wdata,
+        ecc_dm,
+        
+        //Input from AFI Block
+        afi_wlat,
+        
+        //Output from AFI Block
+        afi_doing_read,            //Use to generate rdata_valid signals in PHY
+        afi_doing_read_full,      //AFI 2.0 signal, used by UniPHY for dqs enable control
+        
+        ecc_wdata_fifo_read,
+        ecc_wdata_fifo_dataid,
+        ecc_wdata_fifo_dataid_vector,
+        ecc_wdata_fifo_rmw_correct,
+        ecc_wdata_fifo_rmw_partial,
+        
+        ecc_wdata_fifo_read_first,
+        ecc_wdata_fifo_dataid_first,
+        ecc_wdata_fifo_dataid_vector_first,
+        ecc_wdata_fifo_rmw_correct_first,
+        ecc_wdata_fifo_rmw_partial_first,
+        ecc_wdata_fifo_first_vector,
+        
+        ecc_wdata_fifo_read_last,
+        ecc_wdata_fifo_dataid_last,
+        ecc_wdata_fifo_dataid_vector_last,
+        ecc_wdata_fifo_rmw_correct_last,
+        ecc_wdata_fifo_rmw_partial_last,
+        
+        afi_rrank,
+        afi_wrank,
+        
+        afi_dqs_burst,
+        afi_wdata_valid,
+        afi_wdata,
+        afi_dm
+    );
+    
+    localparam integer  CFG_WLAT_PIPE_LENGTH     = 2**(CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP);
+    localparam integer  CFG_DATAID_ARRAY_DEPTH   = 2**CFG_DATA_ID_WIDTH;
+    integer i;
+    
+    //=================================================================================================//
+    //        input/output declaration                                                                 //
+    //=================================================================================================//
+    
+    input  ctl_clk;
+    input  ctl_reset_n;
+    
+    // configuration
+    input  [CFG_PORT_WIDTH_ENABLE_ECC-1:0]  cfg_enable_ecc;
+    input  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
+    output [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
+    
+    //Arbiter command input
+    input  [CFG_AFI_INTF_PHASE_NUM-1:0]                   bg_do_read;
+    input  [CFG_AFI_INTF_PHASE_NUM-1:0]                   bg_do_write;
+    input                                                 bg_doing_read;
+    input                                                 bg_doing_write;
+    input                                                 bg_rdwr_data_valid;
+    input  [CFG_DATA_ID_WIDTH-1:0]                        dataid;
+    input  [CFG_AFI_INTF_PHASE_NUM-1:0]                   bg_do_rmw_correct;
+    input  [CFG_AFI_INTF_PHASE_NUM-1:0]                   bg_do_rmw_partial;
+    input  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CHIP)-1:0] bg_to_chip;
+    
+    //Inputs from ECC/WFIFO blocks
+    input  [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0]                                              ecc_wdata;
+    input  [(CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO)/(CFG_MEM_IF_DQ_WIDTH/CFG_MEM_IF_DQS_WIDTH)-1:0] ecc_dm;
+    
+    //Input from AFI Block
+    input  [CFG_WLAT_BUS_WIDTH-1:0]                       afi_wlat;
+    
+    //output to AFI block
+    output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   afi_doing_read;
+    output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   afi_doing_read_full;
+    
+    output [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_read;
+    output [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]       ecc_wdata_fifo_dataid;
+    output [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0]  ecc_wdata_fifo_dataid_vector;
+    output [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_rmw_correct;
+    output [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_rmw_partial;
+    
+    output                                                   ecc_wdata_fifo_read_first;
+    output [CFG_DATA_ID_WIDTH-1:0]                           ecc_wdata_fifo_dataid_first;
+    output [CFG_DATAID_ARRAY_DEPTH-1:0]                      ecc_wdata_fifo_dataid_vector_first;
+    output                                                   ecc_wdata_fifo_rmw_correct_first;
+    output                                                   ecc_wdata_fifo_rmw_partial_first;
+    output [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_first_vector;
+    
+    output                                                   ecc_wdata_fifo_read_last;
+    output [CFG_DATA_ID_WIDTH-1:0]                           ecc_wdata_fifo_dataid_last;
+    output [CFG_DATAID_ARRAY_DEPTH-1:0]                      ecc_wdata_fifo_dataid_vector_last;
+    output                                                   ecc_wdata_fifo_rmw_correct_last;
+    output                                                   ecc_wdata_fifo_rmw_partial_last;
+    
+    output [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_rrank;
+    output [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_wrank;
+    
+    output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 afi_dqs_burst;
+    output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 afi_wdata_valid;
+    output [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0]                      afi_wdata;
+    output [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0]                      afi_dm;
+    
+    //=================================================================================================//
+    //        reg/wire declaration                                                                     //
+    //=================================================================================================//
+    
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                      bg_do_read;
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                      bg_do_write;
+    wire                                                    bg_doing_read;
+    wire                                                    bg_doing_write;
+    wire                                                    bg_rdwr_data_valid;
+    wire  [CFG_DATA_ID_WIDTH-1:0]                           dataid;
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                      bg_do_rmw_correct;
+    wire  [CFG_AFI_INTF_PHASE_NUM-1:0]                      bg_do_rmw_partial;
+    wire  [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CHIP)-1:0]    bg_to_chip;
+    
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   afi_doing_read;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   afi_doing_read_full;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   int_afi_doing_read;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   int_afi_doing_read_full;
+    reg   [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   int_afi_doing_read_r;
+    reg   [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]   int_afi_doing_read_full_r;
+    
+    wire  [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_read;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_read_r1;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_read_r2;
+    wire  [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]       ecc_wdata_fifo_dataid;
+    wire  [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0]  ecc_wdata_fifo_dataid_vector;
+    wire  [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_rmw_correct;
+    wire  [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_rmw_partial;
+    
+    wire                                                    ecc_wdata_fifo_read_first;
+    wire  [CFG_DATA_ID_WIDTH-1:0]                           ecc_wdata_fifo_dataid_first;
+    wire  [CFG_DATAID_ARRAY_DEPTH-1:0]                      ecc_wdata_fifo_dataid_vector_first;
+    wire                                                    ecc_wdata_fifo_rmw_correct_first;
+    wire                                                    ecc_wdata_fifo_rmw_partial_first;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                         ecc_wdata_fifo_first_vector;
+    
+    wire                                                    ecc_wdata_fifo_read_last;
+    wire  [CFG_DATA_ID_WIDTH-1:0]                           ecc_wdata_fifo_dataid_last;
+    wire  [CFG_DATAID_ARRAY_DEPTH-1:0]                      ecc_wdata_fifo_dataid_vector_last;
+    wire                                                    ecc_wdata_fifo_rmw_correct_last;
+    wire                                                    ecc_wdata_fifo_rmw_partial_last;
+    
+    wire  [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_rrank;
+    wire  [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_wrank;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 afi_dqs_burst;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 afi_wdata_valid;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 int_afi_dqs_burst;
+    wire  [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 int_afi_wdata_valid;
+    reg   [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 int_afi_dqs_burst_r;
+    reg   [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0]                 int_afi_wdata_valid_r;
+    wire  [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0]                      afi_wdata;
+    wire  [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0]                      afi_dm;
+    
+    //Internal signals
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_combi       [CFG_DRAM_WLAT_GROUP-1:0];
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_combi       [CFG_DRAM_WLAT_GROUP-1:0];
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_mux         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_mux         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
+    reg  [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path;
+    
+    reg                                   doing_read_combi;
+    reg                                   doing_read_full_combi;
+    reg                                   doing_read_r;
+    reg                                   doing_read_full_r;
+    reg   [CFG_WLAT_PIPE_LENGTH-1:0]      doing_write_pipe;
+    reg   [CFG_WLAT_PIPE_LENGTH-1:0]      rdwr_data_valid_pipe;
+    reg   [CFG_WLAT_PIPE_LENGTH-1:0]      do_write_pipe;
+    reg   [CFG_WLAT_PIPE_LENGTH-1:0]      rmw_correct_pipe;
+    reg   [CFG_WLAT_PIPE_LENGTH-1:0]      rmw_partial_pipe;
+    reg   [CFG_DATA_ID_WIDTH-1:0]         dataid_pipe         [CFG_WLAT_PIPE_LENGTH-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    dataid_vector_pipe  [CFG_WLAT_PIPE_LENGTH-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    dataid_vector;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_dqs_burst;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_dqs_burst_r;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_wdata_valid;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_wdata_valid_r;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_real_wdata_valid;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_read;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_read_r;
+    reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid          [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid_r        [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector   [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector_r [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_rmw_correct;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_rmw_correct_r;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_rmw_partial;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]       int_ecc_wdata_fifo_rmw_partial_r;
+    
+    reg   [CFG_MEM_IF_CHIP-1:0]           wr_chip_pipe                       [CFG_WLAT_PIPE_LENGTH-1:0];
+    
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_to_chip;
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_rank                           [CFG_MEM_IF_DQS_WIDTH-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]           rd_chip;
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_rd_rank_full_rate;
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_rd_rank_full_rate_r;
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_wr_rank_full_rate              [CFG_MEM_IF_DQS_WIDTH-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_wr_rank_full_rate_r            [CFG_MEM_IF_DQS_WIDTH-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_wr_rank_half_rate              [CFG_MEM_IF_DQS_WIDTH-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]           int_wr_rank_half_rate_r            [CFG_MEM_IF_DQS_WIDTH-1:0];
+    
+    wire  [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_rd_rank;
+    wire  [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_wr_rank;
+    reg   [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_rd_rank_r;
+    reg   [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_wr_rank_r;
+    
+    wire                                  int_do_rmw_correct;
+    wire                                  int_do_rmw_partial;
+    
+    // DQS burst logic for half rate design
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                     int_dqs_burst_half_rate;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                     int_dqs_burst_half_rate_r;
+    
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                     first_afi_wlat;
+    reg   [CFG_DRAM_WLAT_GROUP-1:0]                     last_afi_wlat;
+    
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  smallest_afi_wlat                                 [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  largest_afi_wlat                                  [CFG_DRAM_WLAT_GROUP-1:0];
+    
+    reg                                                 smallest_afi_wlat_eq_0;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  smallest_afi_wlat_minus_1;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  smallest_afi_wlat_minus_2;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  smallest_afi_wlat_minus_3;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  smallest_afi_wlat_minus_4;
+    reg                                                 smallest_doing_write_pipe_eq_afi_wlat_minus_0;
+    reg                                                 smallest_doing_write_pipe_eq_afi_wlat_minus_1;
+    reg                                                 smallest_doing_write_pipe_eq_afi_wlat_minus_2;
+    reg                                                 smallest_doing_write_pipe_eq_afi_wlat_minus_3;
+    reg                                                 smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
+    reg                                                 smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
+    reg                                                 smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       smallest_dataid_pipe_eq_afi_wlat_minus_1;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       smallest_dataid_pipe_eq_afi_wlat_minus_2;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       smallest_dataid_pipe_eq_afi_wlat_minus_3;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  smallest_dataid_vector_pipe_eq_afi_wlat_minus_1;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  smallest_dataid_vector_pipe_eq_afi_wlat_minus_2;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  smallest_dataid_vector_pipe_eq_afi_wlat_minus_3;
+    reg                                                 smallest_rmw_correct_pipe_eq_afi_wlat_minus_1;
+    reg                                                 smallest_rmw_correct_pipe_eq_afi_wlat_minus_2;
+    reg                                                 smallest_rmw_correct_pipe_eq_afi_wlat_minus_3;
+    reg                                                 smallest_rmw_partial_pipe_eq_afi_wlat_minus_1;
+    reg                                                 smallest_rmw_partial_pipe_eq_afi_wlat_minus_2;
+    reg                                                 smallest_rmw_partial_pipe_eq_afi_wlat_minus_3;
+    reg                                                 smallest_doing_write_pipe_eq_afi_wlat_minus_x;
+    reg                                                 smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       smallest_dataid_pipe_eq_afi_wlat_minus_x;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
+    reg                                                 smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
+    reg                                                 smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
+    
+    reg                                                 largest_afi_wlat_eq_0;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  largest_afi_wlat_minus_1;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  largest_afi_wlat_minus_2;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  largest_afi_wlat_minus_3;
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  largest_afi_wlat_minus_4;
+    reg                                                 largest_doing_write_pipe_eq_afi_wlat_minus_0;
+    reg                                                 largest_doing_write_pipe_eq_afi_wlat_minus_1;
+    reg                                                 largest_doing_write_pipe_eq_afi_wlat_minus_2;
+    reg                                                 largest_doing_write_pipe_eq_afi_wlat_minus_3;
+    reg                                                 largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
+    reg                                                 largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
+    reg                                                 largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       largest_dataid_pipe_eq_afi_wlat_minus_1;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       largest_dataid_pipe_eq_afi_wlat_minus_2;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       largest_dataid_pipe_eq_afi_wlat_minus_3;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  largest_dataid_vector_pipe_eq_afi_wlat_minus_1;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  largest_dataid_vector_pipe_eq_afi_wlat_minus_2;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  largest_dataid_vector_pipe_eq_afi_wlat_minus_3;
+    reg                                                 largest_rmw_correct_pipe_eq_afi_wlat_minus_1;
+    reg                                                 largest_rmw_correct_pipe_eq_afi_wlat_minus_2;
+    reg                                                 largest_rmw_correct_pipe_eq_afi_wlat_minus_3;
+    reg                                                 largest_rmw_partial_pipe_eq_afi_wlat_minus_1;
+    reg                                                 largest_rmw_partial_pipe_eq_afi_wlat_minus_2;
+    reg                                                 largest_rmw_partial_pipe_eq_afi_wlat_minus_3;
+    reg                                                 largest_doing_write_pipe_eq_afi_wlat_minus_x;
+    reg                                                 largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       largest_dataid_pipe_eq_afi_wlat_minus_x;
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
+    reg                                                 largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
+    reg                                                 largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
+    
+    reg                                                 afi_wlat_eq_0                            [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  afi_wlat_minus_1                         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  afi_wlat_minus_2                         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  afi_wlat_minus_3                         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0]  afi_wlat_minus_4                         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 doing_write_pipe_eq_afi_wlat_minus_0     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 doing_write_pipe_eq_afi_wlat_minus_1     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 doing_write_pipe_eq_afi_wlat_minus_2     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 doing_write_pipe_eq_afi_wlat_minus_3     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       dataid_pipe_eq_afi_wlat_minus_1          [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       dataid_pipe_eq_afi_wlat_minus_2          [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       dataid_pipe_eq_afi_wlat_minus_3          [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  dataid_vector_pipe_eq_afi_wlat_minus_1   [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  dataid_vector_pipe_eq_afi_wlat_minus_2   [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  dataid_vector_pipe_eq_afi_wlat_minus_3   [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_correct_pipe_eq_afi_wlat_minus_1     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_correct_pipe_eq_afi_wlat_minus_2     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_correct_pipe_eq_afi_wlat_minus_3     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_partial_pipe_eq_afi_wlat_minus_1     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_partial_pipe_eq_afi_wlat_minus_2     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_partial_pipe_eq_afi_wlat_minus_3     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 doing_write_pipe_eq_afi_wlat_minus_x     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rdwr_data_valid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATA_ID_WIDTH-1:0]                       dataid_pipe_eq_afi_wlat_minus_x          [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_DATAID_ARRAY_DEPTH-1:0]                  dataid_vector_pipe_eq_afi_wlat_minus_x   [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_correct_pipe_eq_afi_wlat_minus_x     [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 rmw_partial_pipe_eq_afi_wlat_minus_x     [CFG_DRAM_WLAT_GROUP-1:0];
+    
+    reg                                                 do_write_pipe_eq_afi_wlat_minus_0        [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 do_write_pipe_eq_afi_wlat_minus_1        [CFG_DRAM_WLAT_GROUP-1:0];
+    reg                                                 do_write_pipe_eq_afi_wlat_minus_2        [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]                         wr_chip_pipe_eq_afi_wlat_minus_0         [CFG_DRAM_WLAT_GROUP-1:0];
+    reg   [CFG_MEM_IF_CHIP-1:0]                         wr_chip_pipe_eq_afi_wlat_minus_1         [CFG_DRAM_WLAT_GROUP-1:0];
+    
+    wire  one  = 1'b1;
+    wire  zero = 1'b0;
+    
+    //=================================================================================================//
+    //            Internal cfg_output_regd                                                             //
+    //=================================================================================================//
+    generate
+        genvar N;
+        for (N = 0;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
+        begin : output_regd_logic_per_dqs_group
+            always @ (*)
+            begin
+                
+                if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
+                begin
+                    // When both wdata_reg and ecc_reg is enabled
+                    // we need to fetch data from wdata path earlier and delay the command path
+                    if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
+                    begin
+                        // Extra latency one afi command output, to match wdata output latency
+                        cfg_output_regd_for_afi_output_combi [N] = 2'd2;
+                        cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
+                    end
+                    else if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] == 2)
+                    begin
+                        cfg_output_regd_for_afi_output_combi [N] = 2'd1;
+                        cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
+                    end
+                    else
+                    begin
+                        cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
+                        cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
+                    end
+                end
+                else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
+                begin
+                    if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
+                    begin
+                        // We enable output_regd for signals going to PHY
+                        // because we need to fetch data 2 clock cycles earlier
+                        cfg_output_regd_for_afi_output_combi [N] = 2'd1;
+                        
+                        // We disable output_regd for signals going to wdata_path
+                        // because we need to fecth data 2 clock cycles earlier
+                        cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
+                    end
+                    else
+                    begin
+                        cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
+                        cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
+                    end
+                end
+                else
+                begin
+                    cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
+                    cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
+                end
+            end
+        end
+        
+        for (N = 1;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
+        begin : output_regd_mux_logic
+            always @ (*)
+            begin
+                cfg_output_regd_for_afi_output_mux       [N] = cfg_output_regd_for_afi_output_combi       [N] | cfg_output_regd_for_afi_output_mux       [N-1];
+                cfg_output_regd_for_wdata_path_mux       [N] = cfg_output_regd_for_wdata_path_combi       [N] | cfg_output_regd_for_wdata_path_mux       [N-1];
+            end
+        end
+    endgenerate
+    
+    always @ (*)
+    begin
+        cfg_output_regd_for_afi_output_mux       [0] = cfg_output_regd_for_afi_output_combi       [0];
+        cfg_output_regd_for_wdata_path_mux       [0] = cfg_output_regd_for_wdata_path_combi       [0];
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_output_regd_for_afi_output       <= 2'd0;
+            cfg_output_regd_for_wdata_path       <= 2'd0;
+        end
+        else
+        begin
+            cfg_output_regd_for_afi_output       <= cfg_output_regd_for_afi_output_mux       [CFG_DRAM_WLAT_GROUP-1];
+            cfg_output_regd_for_wdata_path       <= cfg_output_regd_for_wdata_path_mux       [CFG_DRAM_WLAT_GROUP-1];
+        end
+    end
+    
+    //=================================================================================================//
+    //            Read timing logic                                                                    //
+    //=================================================================================================//
+    
+    //*************************************************************************************************//
+    //            afi_doing_read generation logic                                                      //
+    //*************************************************************************************************//
+    always @(*)
+    begin
+        if (bg_doing_read && bg_rdwr_data_valid)
+        begin
+            doing_read_combi = 1'b1;
+        end
+        else
+        begin
+            doing_read_combi = 1'b0;
+        end
+        
+        doing_read_full_combi = bg_doing_read;
+    end
+    
+    // registered output
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            doing_read_r      <= 1'b0;
+            doing_read_full_r <= 1'b0;
+        end
+        else
+        begin
+            doing_read_r      <= doing_read_combi;
+            doing_read_full_r <= doing_read_full_combi;
+        end
+    end
+    
+    generate
+        genvar I;
+        for (I = 0; I < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); I = I + 1)
+            begin : B
+                assign int_afi_doing_read      [I] = (cfg_output_regd_for_afi_output) ? doing_read_r      : doing_read_combi;
+                assign int_afi_doing_read_full [I] = (cfg_output_regd_for_afi_output) ? doing_read_full_r : doing_read_full_combi;
+            end
+    endgenerate
+    
+    // Registered output
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_afi_doing_read_r      <= 0;
+            int_afi_doing_read_full_r <= 0;
+        end
+        else
+        begin
+            int_afi_doing_read_r      <= int_afi_doing_read;
+            int_afi_doing_read_full_r <= int_afi_doing_read_full;
+        end
+    end
+    
+    assign afi_doing_read      = (cfg_output_regd_for_afi_output == 2) ? int_afi_doing_read_r      : int_afi_doing_read;
+    assign afi_doing_read_full = (cfg_output_regd_for_afi_output == 2) ? int_afi_doing_read_full_r : int_afi_doing_read_full;
+    
+    //=================================================================================================//
+    //            Write timing logic                                                                   //
+    //=================================================================================================//
+    // Content of pipe shows how long dqs should toggle, used to generate dqs_burst
+    // content of pipe is also used to generate wdata_valid signal
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            doing_write_pipe <= 0;
+        end
+        else
+        begin
+            doing_write_pipe <= {doing_write_pipe[CFG_WLAT_PIPE_LENGTH-2:0],bg_doing_write};
+        end
+    end
+    
+    // content of pipe shows how much data should be read out of the write data FIFO
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rdwr_data_valid_pipe <= 0;
+        end
+        else
+        begin
+            rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[CFG_WLAT_PIPE_LENGTH- 2:0],bg_rdwr_data_valid};
+        end
+    end
+    
+    // do_write pipe information
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            do_write_pipe <= 0;
+        end
+        else
+        begin
+            do_write_pipe <= {do_write_pipe[CFG_WLAT_PIPE_LENGTH-2:0],|bg_do_write};
+        end
+    end
+    
+    // to_chip pipe for write command
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                 wr_chip_pipe [i] <= 0;
+            end
+        end
+        else
+        begin
+            wr_chip_pipe [0] <= int_to_chip;
+            
+            for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                 wr_chip_pipe [i] <= wr_chip_pipe [i-1];
+            end
+        end
+    end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                 dataid_pipe [i] <= 0;
+            end
+        end
+        else
+        begin
+            dataid_pipe [0] <= dataid;
+            
+            for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                dataid_pipe [i] <= dataid_pipe [i-1];
+            end
+        end
+    end
+    
+    //pre-calculated dataid comparison logic
+    always @ (*)
+    begin
+        for (i=0; i<(CFG_DATAID_ARRAY_DEPTH); i=i+1)
+        begin
+            if (dataid == i)
+            begin
+                dataid_vector [i] = 1'b1;
+            end
+            else
+            begin
+                dataid_vector [i] = 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            dataid_vector_pipe [0] <= 0;
+            
+            for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                dataid_vector_pipe [i] <= 0;
+            end
+        end
+        else
+        begin
+            dataid_vector_pipe [0] <= dataid_vector;
+            
+            for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
+            begin
+                dataid_vector_pipe [i] <= dataid_vector_pipe[i-1];
+            end
+        end
+    end
+    
+    assign int_do_rmw_correct = |bg_do_rmw_correct;
+    assign int_do_rmw_partial = |bg_do_rmw_partial;
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rmw_correct_pipe <= 0;
+        end
+        else
+        begin
+            rmw_correct_pipe <= {rmw_correct_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_correct};
+        end
+    end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rmw_partial_pipe <= 0;
+        end
+        else
+        begin
+            rmw_partial_pipe <= {rmw_partial_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_partial};
+        end
+    end
+    
+    // Pre-calculated logic for each DQS group
+    generate
+        genvar P;
+        for (P = 0;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
+        begin : pre_calculate_logic_per_dqs_group
+            // afi_wlat for current DQS group
+            wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    afi_wlat_eq_0    [P] <= 1'b0;
+                    afi_wlat_minus_1 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    afi_wlat_minus_2 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    afi_wlat_minus_3 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    afi_wlat_minus_4 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        afi_wlat_eq_0 [P] <= 1'b1;
+                    end
+                    else
+                    begin
+                        afi_wlat_eq_0 [P] <= 1'b0;
+                    end
+            
+                    afi_wlat_minus_1 [P] <= current_afi_wlat - 1'd1;
+                    afi_wlat_minus_2 [P] <= current_afi_wlat - 2'd2;
+                    afi_wlat_minus_3 [P] <= current_afi_wlat - 2'd3;
+                    afi_wlat_minus_4 [P] <= current_afi_wlat - 3'd4;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                    doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                    doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                    doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        if (doing_write_pipe[0])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 2)
+                    begin
+                        if (doing_write_pipe[1])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 3)
+                    begin
+                        if (doing_write_pipe[2])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[1])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (doing_write_pipe[afi_wlat_minus_1 [P]])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[afi_wlat_minus_2 [P]])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[afi_wlat_minus_3 [P]])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[afi_wlat_minus_4 [P]])
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 2)
+                    begin
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 3)
+                    begin
+                        if (rdwr_data_valid_pipe[1])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rdwr_data_valid_pipe[afi_wlat_minus_2 [P]])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[afi_wlat_minus_3 [P]])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[afi_wlat_minus_4 [P]])
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                    do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                    do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        if (do_write_pipe[0])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (|bg_do_write)
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (|bg_do_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 2)
+                    begin
+                        if (do_write_pipe[1])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (do_write_pipe[0])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (|bg_do_write)
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (do_write_pipe[afi_wlat_minus_1 [P]])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
+                        end
+                        
+                        if (do_write_pipe[afi_wlat_minus_2 [P]])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (do_write_pipe[afi_wlat_minus_3 [P]])
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= 0;
+                    wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= 0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= int_to_chip;
+                        wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= 0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= wr_chip_pipe [0];
+                        wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= int_to_chip;
+                    end
+                    else
+                    begin
+                        wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= wr_chip_pipe [afi_wlat_minus_1 [P]];
+                        wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= wr_chip_pipe [afi_wlat_minus_2 [P]];
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    dataid_pipe_eq_afi_wlat_minus_1        [P] <= 0;
+                    dataid_pipe_eq_afi_wlat_minus_2        [P] <= 0;
+                    dataid_pipe_eq_afi_wlat_minus_3        [P] <= 0;
+                    dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
+                    dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
+                    dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= 0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        dataid_pipe_eq_afi_wlat_minus_1        [P] <= 0;
+                        dataid_pipe_eq_afi_wlat_minus_2        [P] <= 0;
+                        dataid_pipe_eq_afi_wlat_minus_3        [P] <= 0;
+                        dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
+                        dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
+                        dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= 0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        dataid_pipe_eq_afi_wlat_minus_1        [P] <= dataid;
+                        dataid_pipe_eq_afi_wlat_minus_2        [P] <= dataid;
+                        dataid_pipe_eq_afi_wlat_minus_3        [P] <= dataid;
+                        dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector;
+                        dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
+                        dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
+                    end
+                    else if (current_afi_wlat == 2)
+                    begin
+                        dataid_pipe_eq_afi_wlat_minus_1        [P] <= dataid_pipe       [0];
+                        dataid_pipe_eq_afi_wlat_minus_2        [P] <= dataid;
+                        dataid_pipe_eq_afi_wlat_minus_3        [P] <= dataid;
+                        dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[0];
+                        dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
+                        dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
+                    end
+                    else if (current_afi_wlat == 3)
+                    begin
+                        dataid_pipe_eq_afi_wlat_minus_1        [P] <= dataid_pipe       [1];
+                        dataid_pipe_eq_afi_wlat_minus_2        [P] <= dataid_pipe       [0];
+                        dataid_pipe_eq_afi_wlat_minus_3        [P] <= dataid;
+                        dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[1];
+                        dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[0];
+                        dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
+                    end
+                    else
+                    begin
+                        dataid_pipe_eq_afi_wlat_minus_1        [P] <= dataid_pipe       [afi_wlat_minus_2 [P]];
+                        dataid_pipe_eq_afi_wlat_minus_2        [P] <= dataid_pipe       [afi_wlat_minus_3 [P]];
+                        dataid_pipe_eq_afi_wlat_minus_3        [P] <= dataid_pipe       [afi_wlat_minus_4 [P]];
+                        dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[afi_wlat_minus_2 [P]];
+                        dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[afi_wlat_minus_3 [P]];
+                        dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector_pipe[afi_wlat_minus_4 [P]];
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                    rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                    rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                    rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                    rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                    rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == 0)
+                    begin
+                        rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                    end
+                    else if (current_afi_wlat == 1)
+                    begin
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 2)
+                    begin
+                        if (rmw_correct_pipe[0])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else if (current_afi_wlat == 3)
+                    begin
+                        if (rmw_correct_pipe[1])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[1])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[0])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rmw_correct_pipe[afi_wlat_minus_2 [P]])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[afi_wlat_minus_2 [P]])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[afi_wlat_minus_3 [P]])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[afi_wlat_minus_3 [P]])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[afi_wlat_minus_4 [P]])
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[afi_wlat_minus_4 [P]])
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
+                        end
+                        else
+                        begin
+                            rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (*)
+            begin
+                if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
+                begin
+                    doing_write_pipe_eq_afi_wlat_minus_x     [P] = doing_write_pipe_eq_afi_wlat_minus_3     [P];
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P];
+                    dataid_pipe_eq_afi_wlat_minus_x          [P] = dataid_pipe_eq_afi_wlat_minus_3          [P];
+                    dataid_vector_pipe_eq_afi_wlat_minus_x   [P] = dataid_vector_pipe_eq_afi_wlat_minus_3   [P];
+                    rmw_correct_pipe_eq_afi_wlat_minus_x     [P] = rmw_correct_pipe_eq_afi_wlat_minus_3     [P];
+                    rmw_partial_pipe_eq_afi_wlat_minus_x     [P] = rmw_partial_pipe_eq_afi_wlat_minus_3     [P];
+                end
+                else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
+                begin
+                    doing_write_pipe_eq_afi_wlat_minus_x     [P] = doing_write_pipe_eq_afi_wlat_minus_2     [P];
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P];
+                    dataid_pipe_eq_afi_wlat_minus_x          [P] = dataid_pipe_eq_afi_wlat_minus_2          [P];
+                    dataid_vector_pipe_eq_afi_wlat_minus_x   [P] = dataid_vector_pipe_eq_afi_wlat_minus_2   [P];
+                    rmw_correct_pipe_eq_afi_wlat_minus_x     [P] = rmw_correct_pipe_eq_afi_wlat_minus_2     [P];
+                    rmw_partial_pipe_eq_afi_wlat_minus_x     [P] = rmw_partial_pipe_eq_afi_wlat_minus_2     [P];
+                end
+                else
+                begin
+                    doing_write_pipe_eq_afi_wlat_minus_x     [P] = doing_write_pipe_eq_afi_wlat_minus_1     [P];
+                    rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P];
+                    dataid_pipe_eq_afi_wlat_minus_x          [P] = dataid_pipe_eq_afi_wlat_minus_1          [P];
+                    dataid_vector_pipe_eq_afi_wlat_minus_x   [P] = dataid_vector_pipe_eq_afi_wlat_minus_1   [P];
+                    rmw_correct_pipe_eq_afi_wlat_minus_x     [P] = rmw_correct_pipe_eq_afi_wlat_minus_1     [P];
+                    rmw_partial_pipe_eq_afi_wlat_minus_x     [P] = rmw_partial_pipe_eq_afi_wlat_minus_1     [P];
+                end
+            end
+            
+            // First vector
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    ecc_wdata_fifo_first_vector [P] <= 1'b0;
+                end
+                else
+                begin
+                    if (current_afi_wlat == smallest_afi_wlat [CFG_DRAM_WLAT_GROUP - 1])
+                    begin
+                        ecc_wdata_fifo_first_vector [P] <= 1'b1;
+                    end
+                    else
+                    begin
+                        ecc_wdata_fifo_first_vector [P] <= 1'b0;
+                    end
+                end
+            end
+        end
+        
+        for (P = 1;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
+        begin : afi_wlat_info_logic
+            // afi_wlat for current DQS group
+            wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
+            
+            // Smallest/largest afi_wlat logic
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_afi_wlat [P] <= 0;
+                    largest_afi_wlat  [P] <= 0;
+                end
+                else
+                begin
+                    if (current_afi_wlat < smallest_afi_wlat [P-1])
+                    begin
+                        smallest_afi_wlat [P] <= current_afi_wlat;
+                    end
+                    else
+                    begin
+                        smallest_afi_wlat [P] <= smallest_afi_wlat [P-1];
+                    end
+                    
+                    if (current_afi_wlat > largest_afi_wlat [P-1])
+                    begin
+                        largest_afi_wlat [P] <= current_afi_wlat;
+                    end
+                    else
+                    begin
+                        largest_afi_wlat [P] <= largest_afi_wlat [P-1];
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    // Smallest/largest afi_wlat logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            smallest_afi_wlat [0] <= 0;
+            largest_afi_wlat  [0] <= 0;
+        end
+        else
+        begin
+            smallest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
+            largest_afi_wlat  [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
+        end
+    end
+    
+    generate
+        if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
+        begin
+            always @ (*)
+            begin
+                smallest_afi_wlat_eq_0                            = afi_wlat_eq_0                            [0];
+                smallest_afi_wlat_minus_1                         = afi_wlat_minus_1                         [0];
+                smallest_afi_wlat_minus_2                         = afi_wlat_minus_2                         [0];
+                smallest_afi_wlat_minus_3                         = afi_wlat_minus_3                         [0];
+                smallest_afi_wlat_minus_4                         = afi_wlat_minus_4                         [0];
+                smallest_doing_write_pipe_eq_afi_wlat_minus_0     = doing_write_pipe_eq_afi_wlat_minus_0     [0];
+                smallest_doing_write_pipe_eq_afi_wlat_minus_1     = doing_write_pipe_eq_afi_wlat_minus_1     [0];
+                smallest_doing_write_pipe_eq_afi_wlat_minus_2     = doing_write_pipe_eq_afi_wlat_minus_2     [0];
+                smallest_doing_write_pipe_eq_afi_wlat_minus_3     = doing_write_pipe_eq_afi_wlat_minus_3     [0];
+                smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
+                smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
+                smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [0];
+                smallest_dataid_pipe_eq_afi_wlat_minus_1          = dataid_pipe_eq_afi_wlat_minus_1          [0];
+                smallest_dataid_pipe_eq_afi_wlat_minus_2          = dataid_pipe_eq_afi_wlat_minus_2          [0];
+                smallest_dataid_pipe_eq_afi_wlat_minus_3          = dataid_pipe_eq_afi_wlat_minus_3          [0];
+                smallest_dataid_vector_pipe_eq_afi_wlat_minus_1   = dataid_vector_pipe_eq_afi_wlat_minus_1   [0];
+                smallest_dataid_vector_pipe_eq_afi_wlat_minus_2   = dataid_vector_pipe_eq_afi_wlat_minus_2   [0];
+                smallest_dataid_vector_pipe_eq_afi_wlat_minus_3   = dataid_vector_pipe_eq_afi_wlat_minus_3   [0];
+                smallest_rmw_correct_pipe_eq_afi_wlat_minus_1     = rmw_correct_pipe_eq_afi_wlat_minus_1     [0];
+                smallest_rmw_correct_pipe_eq_afi_wlat_minus_2     = rmw_correct_pipe_eq_afi_wlat_minus_2     [0];
+                smallest_rmw_correct_pipe_eq_afi_wlat_minus_3     = rmw_correct_pipe_eq_afi_wlat_minus_3     [0];
+                smallest_rmw_partial_pipe_eq_afi_wlat_minus_1     = rmw_partial_pipe_eq_afi_wlat_minus_1     [0];
+                smallest_rmw_partial_pipe_eq_afi_wlat_minus_2     = rmw_partial_pipe_eq_afi_wlat_minus_2     [0];
+                smallest_rmw_partial_pipe_eq_afi_wlat_minus_3     = rmw_partial_pipe_eq_afi_wlat_minus_3     [0];
+                smallest_doing_write_pipe_eq_afi_wlat_minus_x     = doing_write_pipe_eq_afi_wlat_minus_x     [0];
+                smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
+                smallest_dataid_pipe_eq_afi_wlat_minus_x          = dataid_pipe_eq_afi_wlat_minus_x          [0];
+                smallest_dataid_vector_pipe_eq_afi_wlat_minus_x   = dataid_vector_pipe_eq_afi_wlat_minus_x   [0];
+                smallest_rmw_correct_pipe_eq_afi_wlat_minus_x     = rmw_correct_pipe_eq_afi_wlat_minus_x     [0];
+                smallest_rmw_partial_pipe_eq_afi_wlat_minus_x     = rmw_partial_pipe_eq_afi_wlat_minus_x     [0];
+                
+                largest_afi_wlat_eq_0                             = afi_wlat_eq_0                            [0];
+                largest_afi_wlat_minus_1                          = afi_wlat_minus_1                         [0];
+                largest_afi_wlat_minus_2                          = afi_wlat_minus_2                         [0];
+                largest_afi_wlat_minus_3                          = afi_wlat_minus_3                         [0];
+                largest_afi_wlat_minus_4                          = afi_wlat_minus_4                         [0];
+                largest_doing_write_pipe_eq_afi_wlat_minus_0      = doing_write_pipe_eq_afi_wlat_minus_0     [0];
+                largest_doing_write_pipe_eq_afi_wlat_minus_1      = doing_write_pipe_eq_afi_wlat_minus_1     [0];
+                largest_doing_write_pipe_eq_afi_wlat_minus_2      = doing_write_pipe_eq_afi_wlat_minus_2     [0];
+                largest_doing_write_pipe_eq_afi_wlat_minus_3      = doing_write_pipe_eq_afi_wlat_minus_3     [0];
+                largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1  = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
+                largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2  = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
+                largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3  = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [0];
+                largest_dataid_pipe_eq_afi_wlat_minus_1           = dataid_pipe_eq_afi_wlat_minus_1          [0];
+                largest_dataid_pipe_eq_afi_wlat_minus_2           = dataid_pipe_eq_afi_wlat_minus_2          [0];
+                largest_dataid_pipe_eq_afi_wlat_minus_3           = dataid_pipe_eq_afi_wlat_minus_3          [0];
+                largest_dataid_vector_pipe_eq_afi_wlat_minus_1    = dataid_vector_pipe_eq_afi_wlat_minus_1   [0];
+                largest_dataid_vector_pipe_eq_afi_wlat_minus_2    = dataid_vector_pipe_eq_afi_wlat_minus_2   [0];
+                largest_dataid_vector_pipe_eq_afi_wlat_minus_3    = dataid_vector_pipe_eq_afi_wlat_minus_3   [0];
+                largest_rmw_correct_pipe_eq_afi_wlat_minus_1      = rmw_correct_pipe_eq_afi_wlat_minus_1     [0];
+                largest_rmw_correct_pipe_eq_afi_wlat_minus_2      = rmw_correct_pipe_eq_afi_wlat_minus_2     [0];
+                largest_rmw_correct_pipe_eq_afi_wlat_minus_3      = rmw_correct_pipe_eq_afi_wlat_minus_3     [0];
+                largest_rmw_partial_pipe_eq_afi_wlat_minus_1      = rmw_partial_pipe_eq_afi_wlat_minus_1     [0];
+                largest_rmw_partial_pipe_eq_afi_wlat_minus_2      = rmw_partial_pipe_eq_afi_wlat_minus_2     [0];
+                largest_rmw_partial_pipe_eq_afi_wlat_minus_3      = rmw_partial_pipe_eq_afi_wlat_minus_3     [0];
+                largest_doing_write_pipe_eq_afi_wlat_minus_x      = doing_write_pipe_eq_afi_wlat_minus_x     [0];
+                largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x  = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
+                largest_dataid_pipe_eq_afi_wlat_minus_x           = dataid_pipe_eq_afi_wlat_minus_x          [0];
+                largest_dataid_vector_pipe_eq_afi_wlat_minus_x    = dataid_vector_pipe_eq_afi_wlat_minus_x   [0];
+                largest_rmw_correct_pipe_eq_afi_wlat_minus_x      = rmw_correct_pipe_eq_afi_wlat_minus_x     [0];
+                largest_rmw_partial_pipe_eq_afi_wlat_minus_x      = rmw_partial_pipe_eq_afi_wlat_minus_x     [0];
+            end
+        end
+        else
+        begin
+            // Pre-calculated logic for smallest/largest afi_wlat (for afi addr/cmd logic)
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_afi_wlat_eq_0     <= 1'b0;
+                    smallest_afi_wlat_minus_1  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    smallest_afi_wlat_minus_2  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    smallest_afi_wlat_minus_3  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    smallest_afi_wlat_minus_4  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                end
+                else
+                begin
+                    if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        smallest_afi_wlat_eq_0  <= 1'b1;
+                    end
+                    else
+                    begin
+                        smallest_afi_wlat_eq_0  <= 1'b0;
+                    end
+                    
+                    smallest_afi_wlat_minus_1  <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
+                    smallest_afi_wlat_minus_2  <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
+                    smallest_afi_wlat_minus_3  <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
+                    smallest_afi_wlat_minus_4  <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 4;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                end
+                else
+                begin
+                    if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (doing_write_pipe[0])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (doing_write_pipe[1])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (doing_write_pipe[2])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[1])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (doing_write_pipe[smallest_afi_wlat_minus_1])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[smallest_afi_wlat_minus_2])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[smallest_afi_wlat_minus_3])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[smallest_afi_wlat_minus_4])
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                end
+                else
+                begin
+                    if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (rdwr_data_valid_pipe[1])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_2])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_3])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_4])
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_dataid_pipe_eq_afi_wlat_minus_1        <= 0;
+                    smallest_dataid_pipe_eq_afi_wlat_minus_2        <= 0;
+                    smallest_dataid_pipe_eq_afi_wlat_minus_3        <= 0;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
+                end
+                else
+                begin
+                    if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        smallest_dataid_pipe_eq_afi_wlat_minus_1        <= 0;
+                        smallest_dataid_pipe_eq_afi_wlat_minus_2        <= 0;
+                        smallest_dataid_pipe_eq_afi_wlat_minus_3        <= 0;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        smallest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid;
+                        smallest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid;
+                        smallest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        smallest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [0];
+                        smallest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid;
+                        smallest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        smallest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [1];
+                        smallest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid_pipe       [0];
+                        smallest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[1];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[0];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else
+                    begin
+                        smallest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [smallest_afi_wlat_minus_2];
+                        smallest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid_pipe       [smallest_afi_wlat_minus_3];
+                        smallest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid_pipe       [smallest_afi_wlat_minus_4];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[smallest_afi_wlat_minus_2];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[smallest_afi_wlat_minus_3];
+                        smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector_pipe[smallest_afi_wlat_minus_4];
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                end
+                else
+                begin
+                    if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (rmw_correct_pipe[0])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (rmw_correct_pipe[1])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[1])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[0])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rmw_correct_pipe[smallest_afi_wlat_minus_2])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[smallest_afi_wlat_minus_2])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[smallest_afi_wlat_minus_3])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[smallest_afi_wlat_minus_3])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[smallest_afi_wlat_minus_4])
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[smallest_afi_wlat_minus_4])
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (*)
+            begin
+                if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
+                begin
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_x     = smallest_doing_write_pipe_eq_afi_wlat_minus_3    ;
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
+                    smallest_dataid_pipe_eq_afi_wlat_minus_x          = smallest_dataid_pipe_eq_afi_wlat_minus_3         ;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_x   = smallest_dataid_vector_pipe_eq_afi_wlat_minus_3  ;
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_x     = smallest_rmw_correct_pipe_eq_afi_wlat_minus_3    ;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_x     = smallest_rmw_partial_pipe_eq_afi_wlat_minus_3    ;
+                end
+                else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
+                begin
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_x     = smallest_doing_write_pipe_eq_afi_wlat_minus_2    ;
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
+                    smallest_dataid_pipe_eq_afi_wlat_minus_x          = smallest_dataid_pipe_eq_afi_wlat_minus_2         ;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_x   = smallest_dataid_vector_pipe_eq_afi_wlat_minus_2  ;
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_x     = smallest_rmw_correct_pipe_eq_afi_wlat_minus_2    ;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_x     = smallest_rmw_partial_pipe_eq_afi_wlat_minus_2    ;
+                end
+                else
+                begin
+                    smallest_doing_write_pipe_eq_afi_wlat_minus_x     = smallest_doing_write_pipe_eq_afi_wlat_minus_1    ;
+                    smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
+                    smallest_dataid_pipe_eq_afi_wlat_minus_x          = smallest_dataid_pipe_eq_afi_wlat_minus_1         ;
+                    smallest_dataid_vector_pipe_eq_afi_wlat_minus_x   = smallest_dataid_vector_pipe_eq_afi_wlat_minus_1  ;
+                    smallest_rmw_correct_pipe_eq_afi_wlat_minus_x     = smallest_rmw_correct_pipe_eq_afi_wlat_minus_1    ;
+                    smallest_rmw_partial_pipe_eq_afi_wlat_minus_x     = smallest_rmw_partial_pipe_eq_afi_wlat_minus_1    ;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    largest_afi_wlat_eq_0     <= 1'b0;
+                    largest_afi_wlat_minus_1  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    largest_afi_wlat_minus_2  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    largest_afi_wlat_minus_3  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                    largest_afi_wlat_minus_4  <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
+                end
+                else
+                begin
+                    if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        largest_afi_wlat_eq_0  <= 1'b1;
+                    end
+                    else
+                    begin
+                        largest_afi_wlat_eq_0  <= 1'b0;
+                    end
+                    
+                    largest_afi_wlat_minus_1  <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
+                    largest_afi_wlat_minus_2  <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
+                    largest_afi_wlat_minus_3  <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
+                    largest_afi_wlat_minus_4  <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 4;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                    largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                    largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                    largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                end
+                else
+                begin
+                    if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (doing_write_pipe[0])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (doing_write_pipe[1])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (doing_write_pipe[2])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[1])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[0])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (bg_doing_write)
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (doing_write_pipe[largest_afi_wlat_minus_1])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_0  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[largest_afi_wlat_minus_2])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_1  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[largest_afi_wlat_minus_3])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_2  <= 1'b0;
+                        end
+                        
+                        if (doing_write_pipe[largest_afi_wlat_minus_4])
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_doing_write_pipe_eq_afi_wlat_minus_3  <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                end
+                else
+                begin
+                    if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (rdwr_data_valid_pipe[1])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[0])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (bg_rdwr_data_valid)
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rdwr_data_valid_pipe[largest_afi_wlat_minus_2])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[largest_afi_wlat_minus_3])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rdwr_data_valid_pipe[largest_afi_wlat_minus_4])
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    largest_dataid_pipe_eq_afi_wlat_minus_1        <= 0;
+                    largest_dataid_pipe_eq_afi_wlat_minus_2        <= 0;
+                    largest_dataid_pipe_eq_afi_wlat_minus_3        <= 0;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
+                end
+                else
+                begin
+                    if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        largest_dataid_pipe_eq_afi_wlat_minus_1        <= 0;
+                        largest_dataid_pipe_eq_afi_wlat_minus_2        <= 0;
+                        largest_dataid_pipe_eq_afi_wlat_minus_3        <= 0;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        largest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid;
+                        largest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid;
+                        largest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        largest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [0];
+                        largest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid;
+                        largest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        largest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [1];
+                        largest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid_pipe       [0];
+                        largest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid;
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[1];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[0];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
+                    end
+                    else
+                    begin
+                        largest_dataid_pipe_eq_afi_wlat_minus_1        <= dataid_pipe       [largest_afi_wlat_minus_2];
+                        largest_dataid_pipe_eq_afi_wlat_minus_2        <= dataid_pipe       [largest_afi_wlat_minus_3];
+                        largest_dataid_pipe_eq_afi_wlat_minus_3        <= dataid_pipe       [largest_afi_wlat_minus_4];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[largest_afi_wlat_minus_2];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[largest_afi_wlat_minus_3];
+                        largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector_pipe[largest_afi_wlat_minus_4];
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                end
+                else
+                begin
+                    if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
+                    begin
+                        largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
+                    begin
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
+                    begin
+                        if (rmw_correct_pipe[0])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
+                    begin
+                        if (rmw_correct_pipe[1])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[1])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[0])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[0])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_correct)
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (int_do_rmw_partial)
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                    else
+                    begin
+                        if (rmw_correct_pipe[largest_afi_wlat_minus_2])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[largest_afi_wlat_minus_2])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[largest_afi_wlat_minus_3])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[largest_afi_wlat_minus_3])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
+                        end
+                        
+                        if (rmw_correct_pipe[largest_afi_wlat_minus_4])
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                        
+                        if (rmw_partial_pipe[largest_afi_wlat_minus_4])
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
+                        end
+                        else
+                        begin
+                            largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
+                        end
+                    end
+                end
+            end
+            
+            always @ (*)
+            begin
+                if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
+                begin
+                    largest_doing_write_pipe_eq_afi_wlat_minus_x     = largest_doing_write_pipe_eq_afi_wlat_minus_3    ;
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
+                    largest_dataid_pipe_eq_afi_wlat_minus_x          = largest_dataid_pipe_eq_afi_wlat_minus_3         ;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_x   = largest_dataid_vector_pipe_eq_afi_wlat_minus_3  ;
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_x     = largest_rmw_correct_pipe_eq_afi_wlat_minus_3    ;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_x     = largest_rmw_partial_pipe_eq_afi_wlat_minus_3    ;
+                end
+                else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
+                begin
+                    largest_doing_write_pipe_eq_afi_wlat_minus_x     = largest_doing_write_pipe_eq_afi_wlat_minus_2    ;
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
+                    largest_dataid_pipe_eq_afi_wlat_minus_x          = largest_dataid_pipe_eq_afi_wlat_minus_2         ;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_x   = largest_dataid_vector_pipe_eq_afi_wlat_minus_2  ;
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_x     = largest_rmw_correct_pipe_eq_afi_wlat_minus_2    ;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_x     = largest_rmw_partial_pipe_eq_afi_wlat_minus_2    ;
+                end
+                else
+                begin
+                    largest_doing_write_pipe_eq_afi_wlat_minus_x     = largest_doing_write_pipe_eq_afi_wlat_minus_1    ;
+                    largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
+                    largest_dataid_pipe_eq_afi_wlat_minus_x          = largest_dataid_pipe_eq_afi_wlat_minus_1         ;
+                    largest_dataid_vector_pipe_eq_afi_wlat_minus_x   = largest_dataid_vector_pipe_eq_afi_wlat_minus_1  ;
+                    largest_rmw_correct_pipe_eq_afi_wlat_minus_x     = largest_rmw_correct_pipe_eq_afi_wlat_minus_1    ;
+                    largest_rmw_partial_pipe_eq_afi_wlat_minus_x     = largest_rmw_partial_pipe_eq_afi_wlat_minus_1    ;
+                end
+            end
+        end
+    endgenerate
+    
+    //*************************************************************************************************//
+    //            afi_rank generation logic                                                            //
+    //*************************************************************************************************//
+    // to_chip information, based on arbiter type, we need column chip information only
+    always @ (*)
+    begin
+        if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
+        begin
+            // Take the top chip information
+            int_to_chip = bg_to_chip [CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP - 1 : (CFG_AFI_INTF_PHASE_NUM - 1) * CFG_MEM_IF_CHIP];
+        end
+        else if (CFG_CTL_ARBITER_TYPE == "COLROW")
+        begin
+            // Take the bottom chip information
+            int_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0];
+        end
+    end
+    
+    // Chip information for read command
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rd_chip <= 0;
+        end
+        else
+        begin
+            if (|bg_do_read)
+            begin
+                rd_chip <= int_to_chip;
+            end
+        end
+    end
+    
+    // afi_rank information for read command
+    always @ (*)
+    begin
+        if (|bg_do_read)
+        begin
+            int_rd_rank_full_rate = int_to_chip;
+        end
+        else if (bg_doing_read)
+        begin
+            int_rd_rank_full_rate = rd_chip;
+        end
+        else
+        begin
+            // afi_rrank needs to be sticky (case:45607)
+            int_rd_rank_full_rate = rd_chip;
+        end
+    end
+    
+    // Registered read rank information
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_rd_rank_full_rate_r <= 0;
+        end
+        else
+        begin
+            int_rd_rank_full_rate_r <= int_rd_rank_full_rate;
+        end
+    end
+    
+    // afi_rank information for write command
+    generate
+        genvar R;
+        for (R = 0;R < CFG_DRAM_WLAT_GROUP;R = R + 1)
+        begin : wr_rank_info_loop
+            // Full rate rank information
+            always @ (*)
+            begin
+                if (afi_wlat_eq_0 [R])
+                begin
+                    if (do_write_pipe [0])
+                    begin
+                        int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
+                    end
+                    else if (|bg_do_write)
+                    begin
+                        int_wr_rank_full_rate [R] = int_to_chip;
+                    end
+                    else if (doing_write_pipe [0])
+                    begin
+                        int_wr_rank_full_rate [R] = int_wr_rank_full_rate_r [R];
+                    end
+                    else
+                    begin
+                        int_wr_rank_full_rate [R] = 0;
+                    end
+                end
+                else
+                begin
+                    if (do_write_pipe_eq_afi_wlat_minus_0 [R])
+                    begin
+                        int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
+                    end
+                    else if (do_write_pipe_eq_afi_wlat_minus_1 [R])
+                    begin
+                        int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_1 [R];
+                    end
+                    else if (doing_write_pipe_eq_afi_wlat_minus_0 [R])
+                    begin
+                        int_wr_rank_full_rate [R] = int_wr_rank_full_rate_r [R];
+                    end
+                    else
+                    begin
+                        int_wr_rank_full_rate [R] = 0;
+                    end
+                end
+            end
+            
+            // Half rate rank information
+            always @ (*)
+            begin
+                if (afi_wlat_eq_0 [R])
+                begin
+                    if (do_write_pipe [0])
+                    begin
+                        int_wr_rank_half_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
+                    end
+                    else if (doing_write_pipe [0])
+                    begin
+                        int_wr_rank_half_rate [R] = int_wr_rank_half_rate_r [R];
+                    end
+                    else
+                    begin
+                        int_wr_rank_half_rate [R] = 0;
+                    end
+                end
+                else
+                begin
+                    if (do_write_pipe_eq_afi_wlat_minus_0 [R])
+                    begin
+                        int_wr_rank_half_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
+                    end
+                    else if (doing_write_pipe_eq_afi_wlat_minus_0 [R])
+                    begin
+                        int_wr_rank_half_rate [R] = int_wr_rank_half_rate_r [R];
+                    end
+                    else
+                    begin
+                        int_wr_rank_half_rate [R] = 0;
+                    end
+                end
+            end
+            
+            // Registered write rank information
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_wr_rank_full_rate_r [R] <= 0;
+                    int_wr_rank_half_rate_r [R] <= 0;
+                end
+                else
+                begin
+                    int_wr_rank_full_rate_r [R] <= int_wr_rank_full_rate [R];
+                    int_wr_rank_half_rate_r [R] <= int_wr_rank_half_rate [R];
+                end
+            end
+        end
+            
+        for (R = 0;R < CFG_MEM_IF_DQS_WIDTH;R = R + 1)
+        begin : rank_info_per_dqs_group
+            wire [CFG_MEM_IF_CHIP-1:0] derived_rd_rank_full_rate;
+            wire [CFG_MEM_IF_CHIP-1:0] derived_rd_rank_full_rate_r;
+            wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_full_rate;
+            wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_full_rate_r;
+            wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_half_rate;
+            wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_half_rate_r;
+            
+            if (CFG_DRAM_WLAT_GROUP == 1)
+            begin
+                assign derived_rd_rank_full_rate   = int_rd_rank_full_rate;
+                assign derived_rd_rank_full_rate_r = int_rd_rank_full_rate_r;
+                assign derived_wr_rank_full_rate   = int_wr_rank_full_rate   [0];
+                assign derived_wr_rank_full_rate_r = int_wr_rank_full_rate_r [0];
+                assign derived_wr_rank_half_rate   = int_wr_rank_half_rate   [0];
+                assign derived_wr_rank_half_rate_r = int_wr_rank_half_rate_r [0];
+            end
+            else
+            begin
+                assign derived_rd_rank_full_rate   = int_rd_rank_full_rate;
+                assign derived_rd_rank_full_rate_r = int_rd_rank_full_rate_r;
+                assign derived_wr_rank_full_rate   = int_wr_rank_full_rate   [R];
+                assign derived_wr_rank_full_rate_r = int_wr_rank_full_rate_r [R];
+                assign derived_wr_rank_half_rate   = int_wr_rank_half_rate   [R];
+                assign derived_wr_rank_half_rate_r = int_wr_rank_half_rate_r [R];
+            end
+            
+            // afi_rank information
+            if (CFG_DWIDTH_RATIO == 2) // full rate
+            begin
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r : derived_wr_rank_full_rate;
+            end
+            else if (CFG_DWIDTH_RATIO == 4) // half rate
+            begin
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r: derived_wr_rank_full_rate;
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r: derived_wr_rank_half_rate;
+            end
+            else if (CFG_DWIDTH_RATIO == 8) // quarter rate
+            begin
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
+                
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r : derived_wr_rank_full_rate;
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
+                assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
+            end
+        end
+        
+        // Registered output
+        always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+            begin
+                int_rd_rank_r <= 0;
+                int_wr_rank_r <= 0;
+            end
+            else
+            begin
+                int_rd_rank_r <= int_rd_rank;
+                int_wr_rank_r <= int_wr_rank;
+            end
+        end
+        
+        if (CFG_USE_SHADOW_REGS)
+        begin
+            assign afi_rrank = (cfg_output_regd_for_afi_output == 2) ? int_rd_rank_r : int_rd_rank;
+            assign afi_wrank = (cfg_output_regd_for_afi_output == 2) ? int_wr_rank_r : int_wr_rank;
+        end
+        else
+        begin
+            assign afi_rrank = 0;
+            assign afi_wrank = 0;
+        end
+    endgenerate
+    
+    //*************************************************************************************************//
+    //            afi_dqs_burst generation logic                                                       //
+    //*************************************************************************************************//
+    generate
+        genvar S;
+        for (S = 0;S < CFG_DRAM_WLAT_GROUP;S = S + 1) // generate wlat logic for each DQS group
+        begin : dqs_burst_logic_per_dqs_group_1
+            // high earlier than wdata_valid but ends the same
+            // for writes only, where dqs should toggle, use doing_write_pipe
+            always @(*)
+            begin
+                if (afi_wlat_eq_0 [S])
+                begin
+                    if (bg_doing_write || doing_write_pipe[0])
+                    begin
+                        int_dqs_burst [S] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_dqs_burst [S] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (doing_write_pipe_eq_afi_wlat_minus_1 [S] || doing_write_pipe_eq_afi_wlat_minus_0 [S])
+                    begin
+                        int_dqs_burst [S] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_dqs_burst [S] = 1'b0;
+                    end
+                end
+            end
+            
+            // registered output
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_dqs_burst_r [S] <= 1'b0;
+                end
+                else
+                begin
+                    int_dqs_burst_r [S] <= int_dqs_burst [S];
+                end
+            end
+            
+            always @ (*)
+            begin
+                if (afi_wlat_eq_0 [S])
+                begin
+                    if (doing_write_pipe[0])
+                    begin
+                        int_dqs_burst_half_rate [S] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_dqs_burst_half_rate [S] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (doing_write_pipe_eq_afi_wlat_minus_0 [S])
+                    begin
+                        int_dqs_burst_half_rate [S] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_dqs_burst_half_rate [S] = 1'b0;
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_dqs_burst_half_rate_r [S] <= 1'b0;
+                end
+                else
+                begin
+                    int_dqs_burst_half_rate_r [S] <= int_dqs_burst_half_rate [S];
+                end
+            end
+        end
+        
+        for (S = 0; S < CFG_MEM_IF_DQS_WIDTH; S = S + 1)
+        begin : dqs_burst_logic_per_dqs_group_2
+            wire derived_dqs_burst;
+            wire derived_dqs_burst_r;
+            wire derived_dqs_burst_half_rate;
+            wire derived_dqs_burst_half_rate_r;
+            
+            if (CFG_DRAM_WLAT_GROUP == 1)
+            begin
+                assign derived_dqs_burst             = int_dqs_burst             [0];
+                assign derived_dqs_burst_r           = int_dqs_burst_r           [0];
+                assign derived_dqs_burst_half_rate   = int_dqs_burst_half_rate   [0];
+                assign derived_dqs_burst_half_rate_r = int_dqs_burst_half_rate_r [0];
+            end
+            else
+            begin
+                assign derived_dqs_burst             = int_dqs_burst             [S];
+                assign derived_dqs_burst_r           = int_dqs_burst_r           [S];
+                assign derived_dqs_burst_half_rate   = int_dqs_burst_half_rate   [S];
+                assign derived_dqs_burst_half_rate_r = int_dqs_burst_half_rate_r [S];
+            end
+            
+            if (CFG_DWIDTH_RATIO == 2) // fullrate
+            begin
+                assign int_afi_dqs_burst [S] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r : derived_dqs_burst;
+            end
+            else if (CFG_DWIDTH_RATIO == 4) // halfrate
+            begin
+                assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r           : derived_dqs_burst          ;
+                assign int_afi_dqs_burst[S                       ] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
+            end
+            else if (CFG_DWIDTH_RATIO == 8) // quarterrate
+            begin
+                assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r           : derived_dqs_burst          ;
+                assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
+                assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
+                assign int_afi_dqs_burst[S                           ] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
+            end
+        end
+    endgenerate
+    
+    // Registered output
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_afi_dqs_burst_r <= 0;
+        end
+        else
+        begin
+            int_afi_dqs_burst_r <= int_afi_dqs_burst;
+        end
+    end
+    
+    assign afi_dqs_burst = (cfg_output_regd_for_afi_output == 2) ? int_afi_dqs_burst_r : int_afi_dqs_burst;
+    
+    //*************************************************************************************************//
+    //            afi_wdata_valid generation logic                                                     //
+    //*************************************************************************************************//
+    generate
+        genvar T;
+        for (T = 0;T < CFG_DRAM_WLAT_GROUP;T = T + 1) // generate wlat logic for each DQS group
+        begin : wdata_valid_logic_per_dqs_group_1
+            always @(*)
+            begin
+                if (afi_wlat_eq_0 [T])
+                begin
+                    if (doing_write_pipe[0])
+                    begin
+                        int_wdata_valid [T] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_wdata_valid [T] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (doing_write_pipe_eq_afi_wlat_minus_0 [T])
+                    begin
+                        int_wdata_valid [T] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_wdata_valid [T] = 1'b0;
+                    end
+                end
+            end
+            
+            // registered output
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_wdata_valid_r [T] <= 1'b0;
+                end
+                else
+                begin
+                    int_wdata_valid_r [T] <= int_wdata_valid [T];
+                end
+            end
+        end
+        
+        for (T = 0;T < CFG_MEM_IF_DQS_WIDTH;T = T + 1)
+        begin : wdata_valid_logic_per_dqs_group_2
+            wire derived_wdata_valid;
+            wire derived_wdata_valid_r;
+            
+            if (CFG_DRAM_WLAT_GROUP == 1)
+            begin
+                assign derived_wdata_valid   = int_wdata_valid   [0];
+                assign derived_wdata_valid_r = int_wdata_valid_r [0];
+            end
+            else
+            begin
+                assign derived_wdata_valid   = int_wdata_valid   [T];
+                assign derived_wdata_valid_r = int_wdata_valid_r [T];
+            end
+            
+            if (CFG_DWIDTH_RATIO == 2) // fullrate
+            begin
+                assign int_afi_wdata_valid [T] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+            end
+            else if (CFG_DWIDTH_RATIO == 4) // halfrate
+            begin
+                assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+                assign int_afi_wdata_valid [T                       ] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+            end
+            else if (CFG_DWIDTH_RATIO == 8) // quarterrate
+            begin
+                assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+                assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+                assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+                assign int_afi_wdata_valid [T                           ] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
+            end
+        end
+    endgenerate
+    
+    // Registered output
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            int_afi_wdata_valid_r <= 0;
+        end
+        else
+        begin
+            int_afi_wdata_valid_r <= int_afi_wdata_valid;
+        end
+    end
+    
+    assign afi_wdata_valid = (cfg_output_regd_for_afi_output == 2) ? int_afi_wdata_valid_r : int_afi_wdata_valid;
+    
+    //*************************************************************************************************//
+    //            afi_wdata generation logic                                                           //
+    //*************************************************************************************************//
+    generate
+        genvar M;
+        for (M = 0;M < CFG_DRAM_WLAT_GROUP;M = M + 1) // generate wlat logic for each DQS group
+        begin : wlat_logic_per_dqs_group
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_read                                                                  //
+            //*************************************************************************************************//
+            // Indicate when to read from write data buffer
+            // based on burst_gen signals
+            always @(*)
+            begin
+                if (afi_wlat_eq_0 [M])
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_read [M] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read [M] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
+                    begin
+                        int_ecc_wdata_fifo_read [M] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read [M] = 1'b0;
+                    end
+                end
+            end
+            
+            // Registered output
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_read_r [M] <= 1'b0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_read_r [M] <= int_ecc_wdata_fifo_read [M];
+                end
+            end
+            
+            // Determine write data buffer read signal based on output_regd info
+            // output_regd info is derived based on afi_wlat value
+            assign ecc_wdata_fifo_read [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_r [M] : int_ecc_wdata_fifo_read [M];
+            
+            // Registered output
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    ecc_wdata_fifo_read_r1 [M] <= 1'b0;
+                    ecc_wdata_fifo_read_r2 [M] <= 1'b0;
+                end
+                else
+                begin
+                    ecc_wdata_fifo_read_r1 [M] <= ecc_wdata_fifo_read    [M];
+                    ecc_wdata_fifo_read_r2 [M] <= ecc_wdata_fifo_read_r1 [M];
+                end
+            end
+            
+            // data valid one clock cycle after read
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_real_wdata_valid [M] <=  1'b0;
+                end
+                else
+                begin
+                    if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
+                    begin
+                        int_real_wdata_valid [M] <= ecc_wdata_fifo_read_r2 [M];
+                    end
+                    else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
+                    begin
+                        int_real_wdata_valid [M] <= ecc_wdata_fifo_read_r1 [M];
+                    end
+                    else
+                    begin
+                        int_real_wdata_valid [M] <= ecc_wdata_fifo_read    [M];
+                    end
+                end
+            end
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_dataid/dataid_vector                                                  //
+            //*************************************************************************************************//
+            // Dataid generation to write buffer, to indicate which wdata should be passed to AFI
+            always @(*)
+            begin
+                if (afi_wlat_eq_0 [M])
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_dataid        [M] = dataid;
+                        int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid        [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+                else
+                begin
+                    if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
+                    begin
+                        int_ecc_wdata_fifo_dataid        [M] = dataid_pipe_eq_afi_wlat_minus_x        [M];
+                        int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector_pipe_eq_afi_wlat_minus_x [M];
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid        [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+            end
+            
+            // Registered output
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_dataid_r        [M] <= 0;
+                    int_ecc_wdata_fifo_dataid_vector_r [M] <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_dataid_r        [M] <= int_ecc_wdata_fifo_dataid        [M];
+                    int_ecc_wdata_fifo_dataid_vector_r [M] <= int_ecc_wdata_fifo_dataid_vector [M];
+                end
+            end
+            
+            assign ecc_wdata_fifo_dataid        [(M + 1) * CFG_DATA_ID_WIDTH      - 1 : M * CFG_DATA_ID_WIDTH     ] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_r        [M] : int_ecc_wdata_fifo_dataid        [M];
+            assign ecc_wdata_fifo_dataid_vector [(M + 1) * CFG_DATAID_ARRAY_DEPTH - 1 : M * CFG_DATAID_ARRAY_DEPTH] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_r [M] : int_ecc_wdata_fifo_dataid_vector [M];
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_rmw_correct/partial                                                   //
+            //*************************************************************************************************//
+            // Read modify write info logic
+            always @(*)
+            begin
+                if (afi_wlat_eq_0 [M])
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct [M] = int_do_rmw_correct;
+                        int_ecc_wdata_fifo_rmw_partial [M] = int_do_rmw_partial;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct [M] = rmw_correct_pipe_eq_afi_wlat_minus_x [M];
+                        int_ecc_wdata_fifo_rmw_partial [M] = rmw_partial_pipe_eq_afi_wlat_minus_x [M];
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_r [M] <= 0;
+                    int_ecc_wdata_fifo_rmw_partial_r [M] <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_r [M] <= int_ecc_wdata_fifo_rmw_correct [M];
+                    int_ecc_wdata_fifo_rmw_partial_r [M] <= int_ecc_wdata_fifo_rmw_partial [M];
+                end
+            end
+            
+            assign ecc_wdata_fifo_rmw_correct [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_r [M] : int_ecc_wdata_fifo_rmw_correct [M];
+            assign ecc_wdata_fifo_rmw_partial [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_r [M] : int_ecc_wdata_fifo_rmw_partial [M];
+        end
+    endgenerate
+    
+    generate
+        if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
+        begin
+            assign ecc_wdata_fifo_read_first          = ecc_wdata_fifo_read;
+            assign ecc_wdata_fifo_dataid_first        = ecc_wdata_fifo_dataid;
+            assign ecc_wdata_fifo_dataid_vector_first = ecc_wdata_fifo_dataid_vector;
+            assign ecc_wdata_fifo_rmw_correct_first   = ecc_wdata_fifo_rmw_correct;
+            assign ecc_wdata_fifo_rmw_partial_first   = ecc_wdata_fifo_rmw_partial;
+            
+            assign ecc_wdata_fifo_read_last           = ecc_wdata_fifo_read;
+            assign ecc_wdata_fifo_dataid_last         = ecc_wdata_fifo_dataid;
+            assign ecc_wdata_fifo_dataid_vector_last  = ecc_wdata_fifo_dataid_vector;
+            assign ecc_wdata_fifo_rmw_correct_last    = ecc_wdata_fifo_rmw_correct;
+            assign ecc_wdata_fifo_rmw_partial_last    = ecc_wdata_fifo_rmw_partial;
+        end
+        else
+        begin
+            reg                                   ecc_wdata_fifo_read_first_r;
+            reg                                   int_ecc_wdata_fifo_read_first;
+            reg                                   int_ecc_wdata_fifo_read_first_r;
+            reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid_first;
+            reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid_first_r;
+            reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector_first;
+            reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector_first_r;
+            reg                                   int_ecc_wdata_fifo_rmw_correct_first;
+            reg                                   int_ecc_wdata_fifo_rmw_correct_first_r;
+            reg                                   int_ecc_wdata_fifo_rmw_partial_first;
+            reg                                   int_ecc_wdata_fifo_rmw_partial_first_r;
+            
+            reg                                   ecc_wdata_fifo_read_last_r;
+            reg                                   int_ecc_wdata_fifo_read_last;
+            reg                                   int_ecc_wdata_fifo_read_last_r;
+            reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid_last;
+            reg   [CFG_DATA_ID_WIDTH-1:0]         int_ecc_wdata_fifo_dataid_last_r;
+            reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector_last;
+            reg   [CFG_DATAID_ARRAY_DEPTH-1:0]    int_ecc_wdata_fifo_dataid_vector_last_r;
+            reg                                   int_ecc_wdata_fifo_rmw_correct_last;
+            reg                                   int_ecc_wdata_fifo_rmw_correct_last_r;
+            reg                                   int_ecc_wdata_fifo_rmw_partial_last;
+            reg                                   int_ecc_wdata_fifo_rmw_partial_last_r;
+            
+            // Determine first ecc_wdata_fifo_* info
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_read                                                                  //
+            //*************************************************************************************************//
+            // Indicate when to read from write data buffer
+            // based on burst_gen signals
+            always @(*)
+            begin
+                if (smallest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_read_first = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read_first = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_read_first = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read_first = 1'b0;
+                    end
+                end
+            end
+            
+            // Registered output
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_read_first_r <= 1'b0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_read_first_r <= int_ecc_wdata_fifo_read_first;
+                end
+            end
+            
+            // Determine write data buffer read signal based on output_regd info
+            // output_regd info is derived based on afi_wlat value
+            assign ecc_wdata_fifo_read_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_first_r : int_ecc_wdata_fifo_read_first;
+            
+            // Registered output
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    ecc_wdata_fifo_read_first_r <= 1'b0;
+                end
+                else
+                begin
+                    ecc_wdata_fifo_read_first_r <= ecc_wdata_fifo_read_first;
+                end
+            end
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_dataid/dataid_vector                                                  //
+            //*************************************************************************************************//
+            // Dataid generation to write buffer, to indicate which wdata should be passed to AFI
+            always @(*)
+            begin
+                if (smallest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_dataid_first        = dataid;
+                        int_ecc_wdata_fifo_dataid_vector_first = dataid_vector;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid_first        = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+                else
+                begin
+                    if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_dataid_first        = smallest_dataid_pipe_eq_afi_wlat_minus_x       ;
+                        int_ecc_wdata_fifo_dataid_vector_first = smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid_first        = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+            end
+            
+            // Registered output
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_dataid_first_r        <= 0;
+                    int_ecc_wdata_fifo_dataid_vector_first_r <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_dataid_first_r        <= int_ecc_wdata_fifo_dataid_first       ;
+                    int_ecc_wdata_fifo_dataid_vector_first_r <= int_ecc_wdata_fifo_dataid_vector_first;
+                end
+            end
+            
+            assign ecc_wdata_fifo_dataid_first        = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_first_r        : int_ecc_wdata_fifo_dataid_first       ;
+            assign ecc_wdata_fifo_dataid_vector_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_first_r : int_ecc_wdata_fifo_dataid_vector_first;
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_rmw_correct/partial                                                   //
+            //*************************************************************************************************//
+            // Read modify write info logic
+            always @(*)
+            begin
+                if (smallest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_first = int_do_rmw_correct;
+                        int_ecc_wdata_fifo_rmw_partial_first = int_do_rmw_partial;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_first = smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
+                        int_ecc_wdata_fifo_rmw_partial_first = smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_first_r <= 0;
+                    int_ecc_wdata_fifo_rmw_partial_first_r <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_first_r <= int_ecc_wdata_fifo_rmw_correct_first;
+                    int_ecc_wdata_fifo_rmw_partial_first_r <= int_ecc_wdata_fifo_rmw_partial_first;
+                end
+            end
+            
+            assign ecc_wdata_fifo_rmw_correct_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_first_r : int_ecc_wdata_fifo_rmw_correct_first;
+            assign ecc_wdata_fifo_rmw_partial_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_first_r : int_ecc_wdata_fifo_rmw_partial_first;
+            
+            // Determine last ecc_wdata_fifo_* info
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_read                                                                  //
+            //*************************************************************************************************//
+            // Indicate when to read from write data buffer
+            // based on burst_gen signals
+            always @(*)
+            begin
+                if (largest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_read_last = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read_last = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_read_last = 1'b1;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_read_last = 1'b0;
+                    end
+                end
+            end
+            
+            // Registered output
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_read_last_r <= 1'b0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_read_last_r <= int_ecc_wdata_fifo_read_last;
+                end
+            end
+            
+            // Determine write data buffer read signal based on output_regd info
+            // output_regd info is derived based on afi_wlat value
+            assign ecc_wdata_fifo_read_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_last_r : int_ecc_wdata_fifo_read_last;
+            
+            // Registered output
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    ecc_wdata_fifo_read_last_r <= 1'b0;
+                end
+                else
+                begin
+                    ecc_wdata_fifo_read_last_r <= ecc_wdata_fifo_read_last;
+                end
+            end
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_dataid/dataid_vector                                                  //
+            //*************************************************************************************************//
+            // Dataid generation to write buffer, to indicate which wdata should be passed to AFI
+            always @(*)
+            begin
+                if (largest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_dataid_last        = dataid;
+                        int_ecc_wdata_fifo_dataid_vector_last = dataid_vector;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid_last        = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+                else
+                begin
+                    if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_dataid_last        = largest_dataid_pipe_eq_afi_wlat_minus_x       ;
+                        int_ecc_wdata_fifo_dataid_vector_last = largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_dataid_last        = {(CFG_DATA_ID_WIDTH){1'b0}};
+                        int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
+                    end
+                end
+            end
+            
+            // Registered output
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_dataid_last_r        <= 0;
+                    int_ecc_wdata_fifo_dataid_vector_last_r <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_dataid_last_r        <= int_ecc_wdata_fifo_dataid_last       ;
+                    int_ecc_wdata_fifo_dataid_vector_last_r <= int_ecc_wdata_fifo_dataid_vector_last;
+                end
+            end
+            
+            assign ecc_wdata_fifo_dataid_last        = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_last_r        : int_ecc_wdata_fifo_dataid_last       ;
+            assign ecc_wdata_fifo_dataid_vector_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_last_r : int_ecc_wdata_fifo_dataid_vector_last;
+            
+            //*************************************************************************************************//
+            //            ecc_wdata_fifo_rmw_correct/partial                                                   //
+            //*************************************************************************************************//
+            // Read modify write info logic
+            always @(*)
+            begin
+                if (largest_afi_wlat_eq_0)
+                begin
+                    if (bg_rdwr_data_valid && bg_doing_write)
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_last = int_do_rmw_correct;
+                        int_ecc_wdata_fifo_rmw_partial_last = int_do_rmw_partial;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
+                    end
+                end
+                else
+                begin
+                    if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_last = largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
+                        int_ecc_wdata_fifo_rmw_partial_last = largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
+                    end
+                    else
+                    begin
+                        int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
+                        int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
+                    end
+                end
+            end
+            
+            always @ (posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (~ctl_reset_n)
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_last_r <= 0;
+                    int_ecc_wdata_fifo_rmw_partial_last_r <= 0;
+                end
+                else
+                begin
+                    int_ecc_wdata_fifo_rmw_correct_last_r <= int_ecc_wdata_fifo_rmw_correct_last;
+                    int_ecc_wdata_fifo_rmw_partial_last_r <= int_ecc_wdata_fifo_rmw_partial_last;
+                end
+            end
+            
+            assign ecc_wdata_fifo_rmw_correct_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_last_r : int_ecc_wdata_fifo_rmw_correct_last;
+            assign ecc_wdata_fifo_rmw_partial_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_last_r : int_ecc_wdata_fifo_rmw_partial_last;
+        end
+    endgenerate
+    
+    // No data manipulation on wdata
+    assign afi_wdata = ecc_wdata;
+    
+    //*************************************************************************************************//
+    //            afi_dm generation logic                                                              //
+    //*************************************************************************************************//
+    //Why do we need ecc_dm and rdwr_data_valid to determine DM
+    // ecc_dm will not get updated till we read another data from wrfifo, so we need to drive DMs based on rdwr_data_valid
+    //Output registered information already backed in ecc_wdata_fifo_read
+    
+    generate
+        genvar J;
+        genvar K;
+        if (CFG_DRAM_WLAT_GROUP == 1)
+        begin
+            for (J = 0; J < CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO; J = J + 1)
+            begin : dm_loop
+                assign afi_dm [J] = ~ecc_dm [J] | ~int_real_wdata_valid;
+            end
+        end
+        else
+        begin
+            for (J = 0; J < CFG_DWIDTH_RATIO; J = J + 1)
+            begin : dwidth_ratio_loop
+                for (K = 0; K < CFG_DRAM_WLAT_GROUP; K = K + 1)
+                begin : dm_loop
+                    assign afi_dm [(J * CFG_DRAM_WLAT_GROUP) + K] = ~ecc_dm [(J * CFG_DRAM_WLAT_GROUP) + K] | ~int_real_wdata_valid [K];
+                end
+            end
+        end
+    endgenerate
+    
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v
new file mode 100644
index 0000000..a7b7820
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v
@@ -0,0 +1,1745 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230 10762 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_sideband
+    # (parameter
+    
+        // parameters
+        CFG_PORT_WIDTH_TYPE                     =   3,
+        CFG_DWIDTH_RATIO                        =   2, //2-FR,4-HR,8-QR
+        CFG_REG_GRANT                           =   1,
+        CFG_CTL_TBP_NUM                         =   4,
+        CFG_MEM_IF_CS_WIDTH                     =   1,
+        CFG_MEM_IF_CHIP                         =   1, // one hot
+        CFG_MEM_IF_BA_WIDTH                     =   3,
+        CFG_PORT_WIDTH_TCL                      =   4,
+        CFG_PORT_WIDTH_CS_ADDR_WIDTH            =   2,
+        CFG_MEM_IF_CLK_PAIR_COUNT               =   2,
+        CFG_RANK_TIMER_OUTPUT_REG               =   0,
+        T_PARAM_ARF_TO_VALID_WIDTH              =   10,
+        T_PARAM_ARF_PERIOD_WIDTH                =   13,
+        T_PARAM_PCH_ALL_TO_VALID_WIDTH          =   10,
+        T_PARAM_SRF_TO_VALID_WIDTH              =   10,
+        T_PARAM_SRF_TO_ZQ_CAL_WIDTH             =   10,
+        T_PARAM_PDN_TO_VALID_WIDTH              =   6,
+        T_PARAM_PDN_PERIOD_WIDTH                = 16,
+        T_PARAM_POWER_SAVING_EXIT_WIDTH         = 6,
+        T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH      = 4,
+        BANK_TIMER_COUNTER_OFFSET               = 2  //used to be 4
+    )
+    (
+    
+        ctl_clk,
+        ctl_reset_n,
+        
+        // local interface
+        rfsh_req,
+        rfsh_chip,
+        rfsh_ack,
+        self_rfsh_req,
+        self_rfsh_chip,
+        self_rfsh_ack,
+        deep_powerdn_req,
+        deep_powerdn_chip,
+        deep_powerdn_ack,
+        power_down_ack,
+        
+        // sideband output
+        stall_row_arbiter,
+        stall_col_arbiter,
+        stall_chip,
+        sb_do_precharge_all,
+        sb_do_refresh,
+        sb_do_self_refresh,
+        sb_do_power_down,
+        sb_do_deep_pdown,
+        sb_do_zq_cal,
+        sb_tbp_precharge_all,
+        
+        // PHY interface
+        ctl_mem_clk_disable,
+        ctl_cal_req,
+        ctl_init_req,
+        ctl_cal_success,
+        
+        // tbp & cmd gen
+        cmd_gen_chipsel,
+        tbp_chipsel,
+        tbp_load,
+        
+        // timing
+        t_param_arf_to_valid,
+        t_param_arf_period,
+        t_param_pch_all_to_valid,
+        t_param_srf_to_valid,
+        t_param_srf_to_zq_cal,
+        t_param_pdn_to_valid,
+        t_param_pdn_period,
+        t_param_power_saving_exit,
+        t_param_mem_clk_entry_cycles,
+        
+        // block status
+        tbp_empty,
+        tbp_bank_closed,
+        tbp_timer_ready,
+        row_grant,
+        col_grant,
+        
+        // dqs tracking
+        afi_ctl_refresh_done,
+        afi_seq_busy,
+        afi_ctl_long_idle,
+        
+        // config ports
+        cfg_cs_addr_width,
+        cfg_enable_dqs_tracking,
+        cfg_user_rfsh,
+        cfg_type,
+        cfg_tcl,
+        cfg_regdimm_enable,
+
+        // ZQ Calibration
+        zqcal_req,
+        
+        // to refresh controller
+        sideband_in_refresh
+    );
+    
+    // states for "sideband_state" state machine
+    localparam IDLE_S1      = 3'b000;
+    localparam ARF          = 3'b001;
+    localparam PDN          = 3'b010;
+    localparam SRF          = 3'b100;
+	
+    // states for "disable_clk_state" state machine
+    localparam IDLE_S2      = 2'b00;
+    localparam DISABLECLK1  = 2'b01;
+    localparam DISABLECLK2  = 2'b10;
+	
+    // states for "state" state machine
+    localparam IDLE_S3      = 9'b000000000;
+    localparam INIT         = 9'b000000001;
+    localparam PCHALL       = 9'b000000010;
+    localparam REFRESH      = 9'b000000100;
+    localparam PDOWN        = 9'b000001000;
+    localparam SELFRFSH     = 9'b000010000;
+    localparam DEEPPDN      = 9'b000100000;
+    localparam INITREQ      = 9'b001000000;
+    localparam ZQCAL        = 9'b010000000;
+    localparam DQSTRK       = 9'b100000000;
+    
+    localparam POWER_SAVING_COUNTER_WIDTH      = T_PARAM_SRF_TO_VALID_WIDTH;
+    localparam POWER_SAVING_EXIT_COUNTER_WIDTH = T_PARAM_POWER_SAVING_EXIT_WIDTH;
+    localparam DISABLE_CLK_COUNTER_WIDTH       = T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH;
+    localparam ARF_COUNTER_WIDTH               = T_PARAM_ARF_PERIOD_WIDTH;
+    localparam PDN_COUNTER_WIDTH               = T_PARAM_PDN_PERIOD_WIDTH;
+    
+    localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2 ** CFG_MEM_IF_BA_WIDTH;
+    localparam integer CFG_PORT_WIDTH_TCL_SQRD  = 2 ** CFG_PORT_WIDTH_TCL;
+    localparam SAMPLE_EVERY_N_RFSH = 0; //Valid values are 0-7
+    
+    input                                               ctl_clk;
+    input                                               ctl_reset_n;
+    
+    input                                               rfsh_req;
+    input   [CFG_MEM_IF_CHIP-1:0]                       rfsh_chip;
+    output                                              rfsh_ack;
+    input                                               self_rfsh_req;
+    input   [CFG_MEM_IF_CHIP-1:0]                       self_rfsh_chip;
+    output                                              self_rfsh_ack;
+    input                                               deep_powerdn_req;
+    input   [CFG_MEM_IF_CHIP-1:0]                       deep_powerdn_chip;
+    output                                              deep_powerdn_ack;
+    output                                              power_down_ack;
+    
+    output                                              stall_row_arbiter;
+    output                                              stall_col_arbiter;
+    output  [CFG_MEM_IF_CHIP-1:0]                       stall_chip;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_precharge_all;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_refresh;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_self_refresh;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_power_down;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_deep_pdown;
+    output  [CFG_MEM_IF_CHIP-1:0]                       sb_do_zq_cal;
+    output  [CFG_CTL_TBP_NUM-1:0]                       sb_tbp_precharge_all;
+    
+    output  [CFG_MEM_IF_CLK_PAIR_COUNT-1:0]             ctl_mem_clk_disable;
+    output                                              ctl_cal_req;
+    output                                              ctl_init_req;
+    input                                               ctl_cal_success;
+    
+    input   [CFG_MEM_IF_CS_WIDTH-1:0]                   cmd_gen_chipsel;
+    input   [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
+    input   [CFG_CTL_TBP_NUM-1:0]                       tbp_load;
+    
+    input   [T_PARAM_ARF_TO_VALID_WIDTH-1:0]            t_param_arf_to_valid;
+    input   [T_PARAM_ARF_PERIOD_WIDTH-1:0]              t_param_arf_period;
+    input   [T_PARAM_PCH_ALL_TO_VALID_WIDTH-1:0]        t_param_pch_all_to_valid;
+    input   [T_PARAM_SRF_TO_VALID_WIDTH-1:0]            t_param_srf_to_valid;
+    input   [T_PARAM_SRF_TO_ZQ_CAL_WIDTH-1:0]           t_param_srf_to_zq_cal;
+    input   [T_PARAM_PDN_TO_VALID_WIDTH-1:0]            t_param_pdn_to_valid;
+    input   [T_PARAM_PDN_PERIOD_WIDTH-1:0]              t_param_pdn_period;
+    input   [T_PARAM_POWER_SAVING_EXIT_WIDTH-1:0]       t_param_power_saving_exit;
+    input   [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH-1:0]    t_param_mem_clk_entry_cycles;
+    
+    input                                               tbp_empty;
+    input   [CFG_MEM_IF_CHIP-1:0]                       tbp_bank_closed;
+    input   [CFG_MEM_IF_CHIP-1:0]                       tbp_timer_ready;
+    input                                               row_grant;
+    input                                               col_grant;
+    
+    output  [CFG_MEM_IF_CHIP-1:0]                       afi_ctl_refresh_done;
+    input   [CFG_MEM_IF_CHIP-1:0]                       afi_seq_busy;
+    output  [CFG_MEM_IF_CHIP-1:0]                       afi_ctl_long_idle;
+    
+    input   [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0]          cfg_cs_addr_width;
+    input                                               cfg_enable_dqs_tracking;
+    input                                               cfg_user_rfsh;
+    input   [CFG_PORT_WIDTH_TYPE-1:0]                   cfg_type;
+    input   [CFG_PORT_WIDTH_TCL-1:0]                    cfg_tcl;
+    input                                               cfg_regdimm_enable;
+    
+    input                                               zqcal_req;
+
+    output  [CFG_MEM_IF_CHIP-1:0]                       sideband_in_refresh;
+
+    // end of port declaration
+    
+    wire                                    self_rfsh_ack;
+    wire                                    deep_powerdn_ack;
+    wire                                    power_down_ack;
+    
+    wire    [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
+    
+    wire                                    ctl_cal_req;
+    wire                                    ctl_init_req;
+    
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_precharge_all;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_refresh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_self_refresh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_power_down;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_deep_pdown;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sb_do_zq_cal;
+    reg     [CFG_CTL_TBP_NUM-1:0]           sb_tbp_precharge_all;
+    
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_refresh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_power_down;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_deep_pdown;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_self_rfsh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_self_rfsh_r;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_precharge_all;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_zqcal;
+    reg     [CFG_MEM_IF_CHIP-1:0]           stall_chip;
+    reg     [CFG_MEM_IF_CHIP-1:0]           int_stall_chip;
+    reg     [CFG_MEM_IF_CHIP-1:0]           int_stall_chip_combi;
+    reg     [CFG_MEM_IF_CHIP-1:0]           stall_arbiter;
+    reg     [CFG_MEM_IF_CHIP-1:0]           afi_ctl_refresh_done;
+    wire    [CFG_MEM_IF_CHIP-1:0]           afi_ctl_long_idle;
+    reg     [CFG_MEM_IF_CHIP-1:0]           dqstrk_exit;
+    reg     [CFG_MEM_IF_CHIP-1:0]           doing_zqcal;
+    reg     [CFG_MEM_IF_CHIP-1:0]           init_req;
+    reg     [CFG_MEM_IF_CHIP-1:0]           disable_clk;
+    reg     [CFG_MEM_IF_CHIP-1:0]           int_init_req;
+    reg     [CFG_MEM_IF_CHIP-1:0]           int_disable_clk;
+    
+    reg                                     refresh_req;
+    
+    reg     [CFG_MEM_IF_CHIP-1:0]           refresh_chip_req;
+    reg     [CFG_MEM_IF_CHIP-1:0]           self_refresh_chip_req;
+    reg                                     self_rfsh_req_r;
+    reg     [CFG_MEM_IF_CHIP-1:0]           deep_pdown_chip_req;
+    reg     [CFG_MEM_IF_CHIP-1:0]           power_down_chip_req;
+    wire    [CFG_MEM_IF_CHIP-1:0]           power_down_chip_req_combi;
+    
+    wire    [CFG_MEM_IF_CHIP-1:0]           all_banks_closed;
+    wire    [CFG_MEM_IF_CHIP-1:0]           tcom_not_running;
+    reg     [CFG_PORT_WIDTH_TCL_SQRD-1:0]   tcom_not_running_pipe [CFG_MEM_IF_CHIP-1:0];
+    reg     [CFG_MEM_IF_CHIP-1:0]           can_refresh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           can_self_rfsh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           can_deep_pdown;
+    reg     [CFG_MEM_IF_CHIP-1:0]           can_power_down;
+    reg     [CFG_MEM_IF_CHIP-1:0]           can_exit_power_saving_mode;
+    reg     [CFG_MEM_IF_CHIP-1:0]           cs_refresh_req;
+    wire    grant;
+    wire    [CFG_MEM_IF_CHIP-1:0]           cs_zq_cal_req;
+    wire    [CFG_MEM_IF_CHIP-1:0]           power_saving_enter_ready;
+    wire    [CFG_MEM_IF_CHIP-1:0]           power_saving_exit_ready;
+    reg     [PDN_COUNTER_WIDTH  - 1 : 0]    power_down_cnt;
+    reg                                     no_command_r1;
+    reg     [CFG_MEM_IF_CHIP-1:0]           afi_seq_busy_r; // synchronizer
+    reg     [CFG_MEM_IF_CHIP-1:0]           afi_seq_busy_r2; // synchronizer
+    
+    //new! to avoid contention
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_refresh_req;
+    reg                                     refresh_req_ack;
+    reg                                     dummy_do_refresh;
+    reg                                     dummy_do_refresh_r;
+    reg                                     do_refresh_r;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_self_rfsh_req;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_self_rfsh_req_r1;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_self_rfsh_req_r2;
+    reg                                     self_rfsh_req_ack;
+    reg                                     dummy_do_self_rfsh;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_zqcal_req;
+    reg                                     zqcal_req_ack;
+    reg                                     dummy_do_zqcal;
+    reg     [CFG_MEM_IF_CHIP-1:0]           do_pch_all_req;
+    reg                                     pch_all_req_ack;
+    reg                                     dummy_do_pch_all;
+    reg                                     do_refresh_to_all_chip;
+    reg                                     do_refresh_to_all_chip_r;
+    reg                                     do_self_refresh_to_all_chip;
+    reg                                     do_self_refresh_to_all_chip_r;
+    reg                                     do_zqcal_to_all_chip;
+    reg                                     do_zqcal_to_all_chip_r;
+    reg     [CFG_MEM_IF_CHIP-1:0]           sideband_in_refresh;
+    reg     [2:0]                           trk_rfsh_cntr [CFG_MEM_IF_CHIP-1:0];
+    
+    integer i;
+    
+    assign ctl_mem_clk_disable = {CFG_MEM_IF_CLK_PAIR_COUNT{&int_disable_clk}};
+    assign ctl_cal_req         = &int_init_req;
+    assign ctl_init_req        = 1'b0;
+    assign afi_ctl_long_idle   = {CFG_MEM_IF_CHIP{1'b0}};
+    
+    //generate *_chip_ok signals by checking can_*[chip], only when for_chip[chip] is 1   
+    generate
+        genvar chip;
+        for (chip = 0; chip < CFG_MEM_IF_CHIP; chip = chip + 1)
+        begin : gen_chip_ok
+            // check can_* only for chips that we'd like to precharge_all to, ^~ is XNOR
+            assign tcom_not_running[chip] = tbp_timer_ready[chip];
+            assign all_banks_closed[chip] = tbp_bank_closed[chip];
+            
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    tcom_not_running_pipe[chip] <= 0;
+                end
+                else
+                begin
+                    if (!tcom_not_running[chip])
+                    begin
+                        tcom_not_running_pipe[chip] <= 0;
+                    end
+                    else
+                    begin
+                        tcom_not_running_pipe[chip] <= {tcom_not_running_pipe[chip][CFG_PORT_WIDTH_TCL_SQRD -2 :0],tcom_not_running[chip]};
+                    end
+                end
+            end
+            
+            // Generate per chip init_req and disable_clk
+            // to be used in MMR case where they actually use smaller CS than the actual design
+            // example: 2 CS design, but user only use 1 CS in MMR mode
+            always @ (*)
+            begin
+                if (chip < (2 ** cfg_cs_addr_width))
+                begin
+                    int_init_req   [chip] = init_req   [chip];
+                    int_disable_clk[chip] = disable_clk[chip];
+                end
+                else
+                begin
+                    int_init_req   [chip] = 1'b1;
+                    int_disable_clk[chip] = 1'b1;
+                end
+            end
+        end
+    endgenerate
+    
+    assign  rfsh_ack         = (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) ? |do_refresh : ((|do_refresh | do_refresh_r) & refresh_req_ack);
+    assign  self_rfsh_ack    = |do_self_rfsh;
+    assign  deep_powerdn_ack = |do_deep_pdown;
+    assign  power_down_ack   = |do_power_down;
+    
+    // Register sideband signals when CFG_REG_GRANT is '1'
+    // to prevent sideband request going out on the same cycle as tbp request
+    generate
+    begin
+        genvar j;
+        if (CFG_REG_GRANT == 1)
+        begin
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    sb_do_precharge_all <= 0;
+                    sb_do_refresh       <= 0;
+                    sb_do_self_refresh  <= 0;
+                    sb_do_power_down    <= 0;
+                    sb_do_deep_pdown    <= 0;
+                    sb_do_zq_cal        <= 0;
+                end
+                else
+                begin
+                    sb_do_precharge_all <= do_precharge_all;
+                    sb_do_refresh       <= do_refresh;
+                    sb_do_self_refresh  <= do_self_rfsh;
+                    sb_do_power_down    <= do_power_down;
+                    sb_do_deep_pdown    <= do_deep_pdown;
+                    sb_do_zq_cal        <= do_zqcal;
+                end
+            end
+            
+            for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
+            begin : tbp_loop_1
+                always @ (posedge ctl_clk or negedge ctl_reset_n)
+                begin
+                    if (!ctl_reset_n)
+                    begin
+                        sb_tbp_precharge_all [j] <= 1'b0;
+                    end
+                    else
+                    begin
+                        if (tbp_load[j])
+                        begin
+                            sb_tbp_precharge_all [j] <= do_precharge_all [cmd_gen_chipsel];
+                        end
+                        else
+                        begin
+                            sb_tbp_precharge_all [j] <= do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
+                        end
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                sb_do_precharge_all = do_precharge_all;
+                sb_do_refresh       = do_refresh;
+                sb_do_self_refresh  = do_self_rfsh;
+                sb_do_power_down    = do_power_down;
+                sb_do_deep_pdown    = do_deep_pdown;
+                sb_do_zq_cal        = do_zqcal;
+            end
+            
+            for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
+            begin : tbp_loop_2
+                always @ (*)
+                begin
+                    sb_tbp_precharge_all [j] = do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
+                end
+            end
+        end
+    end
+    endgenerate
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            refresh_req_ack    <= 0;
+            zqcal_req_ack      <= 0;
+            pch_all_req_ack    <= 0;
+            self_rfsh_req_ack  <= 0;
+            dummy_do_refresh_r <= 0;
+            do_refresh_r       <= 0;
+        end
+        else
+        begin
+            refresh_req_ack    <= dummy_do_refresh;
+            zqcal_req_ack      <= dummy_do_zqcal;
+            pch_all_req_ack    <= dummy_do_pch_all;
+            self_rfsh_req_ack  <= dummy_do_self_rfsh;
+            dummy_do_refresh_r <= dummy_do_refresh;
+            
+            if (dummy_do_refresh && !dummy_do_refresh_r)
+            begin
+                do_refresh_r <= |do_refresh;
+            end
+            else
+            begin
+                do_refresh_r <= 0;
+            end
+        end
+    end
+    
+    always @(*)
+    begin
+        i = 0;
+        dummy_do_refresh = 0;
+        dummy_do_pch_all = 0;
+        dummy_do_zqcal   = 0;
+        
+        if (|do_pch_all_req)
+        begin
+            do_refresh = 0;
+            do_zqcal   = 0;
+            
+            if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
+            begin
+                do_precharge_all = do_pch_all_req;
+            end
+            else
+            begin
+                for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
+                begin
+                    if (i%2 == 0 && !pch_all_req_ack) // case:139868 fixing case where pch_all goes to all cs on the same cycle, which is illegal in RDIMM mode
+                    begin
+                        do_precharge_all [i] = do_pch_all_req[i];
+                        dummy_do_pch_all     = |do_pch_all_req;
+                    end
+                    else if (i%2 == 1 && pch_all_req_ack)
+                    begin
+                        do_precharge_all [i] = do_pch_all_req[i];
+                    end
+                    else
+                    begin
+                        do_precharge_all [i] = 0;
+                    end
+                end
+            end
+        end
+        else if (|do_refresh_req)
+        begin
+            if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) // if not (regdimm and DDR3), normal refresh
+            begin
+                do_refresh = do_refresh_req;
+            end
+            else
+            begin
+                for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
+                begin
+                    if (i%2 == 0)
+                    begin
+                        do_refresh [i]   = do_refresh_req [i];
+
+                        if (&refresh_chip_req) // refresh to all chips in REGDIMM
+                        begin
+                            dummy_do_refresh = &do_refresh_req;
+                        end
+                        else
+                        begin
+                            dummy_do_refresh = |do_refresh_req;
+                        end
+                    end
+                    else if (i%2 == 1 && refresh_req_ack)
+                    begin
+                        do_refresh [i] = do_refresh_req [i];
+                    end
+                    else
+                    begin
+                        do_refresh [i] = 0;
+                    end
+                end
+            end
+            
+            do_precharge_all = 0;
+            do_zqcal         = 0;
+        end
+        else if (|do_zqcal_req)
+        begin
+            do_refresh       = 0;
+            do_precharge_all = 0;
+            
+            if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
+            begin
+                do_zqcal = do_zqcal_req;
+            end
+            else
+            begin
+                for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
+                begin
+                    if (i%2 == 0)
+                    begin
+                        do_zqcal [i]   = do_zqcal_req[i];
+                        dummy_do_zqcal = |do_zqcal_req;
+                    end
+                    else if (i%2 == 1 && zqcal_req_ack)
+                    begin
+                        do_zqcal [i] = do_zqcal_req[i];
+                    end
+                    else
+                    begin
+                        do_zqcal [i] = 0;
+                    end
+                end
+            end
+        end
+        else
+        begin
+            do_refresh       = 0;
+            dummy_do_refresh = 0;
+            do_precharge_all = 0;
+            dummy_do_pch_all = 0;
+            do_zqcal         = 0;
+            dummy_do_zqcal   = 0;
+        end
+    end
+    
+    always @(*)
+    begin
+        i                  = 0;
+        dummy_do_self_rfsh = 1'b0;
+        
+        if (|do_refresh_req || |do_precharge_all || |do_zqcal_req)
+        begin
+            if (|do_self_rfsh_r)
+            begin
+                do_self_rfsh       = do_self_rfsh_req;
+                dummy_do_self_rfsh = 1'b1;
+            end
+            else
+            begin
+                do_self_rfsh = 0;
+            end
+        end
+        else
+        begin
+            if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
+            begin
+                do_self_rfsh = do_self_rfsh_req;
+            end
+            else
+            begin
+                for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
+                begin
+                    if (i%2 == 0)
+                    begin
+                        do_self_rfsh [i]   = do_self_rfsh_req[i];
+                        dummy_do_self_rfsh = |do_self_rfsh_req;
+                    end
+                    else if (i%2 == 1 && self_rfsh_req_ack)
+                    begin
+                        do_self_rfsh [i] = do_self_rfsh_req[i];
+                    end
+                    else
+                    begin
+                        do_self_rfsh [i] = 0;
+                    end
+                end
+            end
+        end
+    end
+    
+    always @ (*)
+    begin
+        do_refresh_to_all_chip      = &do_refresh_req;
+        do_self_refresh_to_all_chip = &do_self_rfsh_req;
+        do_zqcal_to_all_chip        = &do_zqcal_req;
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            do_self_rfsh_req_r1           <= 0;
+            do_self_rfsh_req_r2           <= 0;
+            
+            do_refresh_to_all_chip_r      <= 1'b0;
+            do_self_refresh_to_all_chip_r <= 1'b0;
+            do_zqcal_to_all_chip_r        <= 1'b0;
+        end
+        else
+        begin
+            do_self_rfsh_req_r1           <= do_self_rfsh_req;
+            do_self_rfsh_req_r2           <= do_self_rfsh_req_r1;
+            
+            do_refresh_to_all_chip_r      <= do_refresh_to_all_chip;
+            do_self_refresh_to_all_chip_r <= do_self_refresh_to_all_chip;
+            do_zqcal_to_all_chip_r        <= do_zqcal_to_all_chip;
+        end
+    end
+    
+    assign stall_row_arbiter = |stall_arbiter;
+    assign stall_col_arbiter = |stall_arbiter;
+    
+    assign grant             = (CFG_REG_GRANT == 1) ? (row_grant | col_grant) : 1'b0;
+    
+    //register self_rfsh_req and deep_powerdn_req
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            self_refresh_chip_req <= 0;
+            deep_pdown_chip_req   <= 0;
+            self_rfsh_req_r       <= 0;
+            do_self_rfsh_r        <= 0;
+        end
+        else
+        begin
+            if (self_rfsh_req)
+            begin
+                self_refresh_chip_req <= self_rfsh_chip;
+            end
+            else
+            begin
+                self_refresh_chip_req <= 0;
+            end
+            
+            self_rfsh_req_r <= self_rfsh_req & |self_rfsh_chip;
+            do_self_rfsh_r  <= do_self_rfsh;
+            
+            if (deep_powerdn_req)
+            begin
+                deep_pdown_chip_req <= deep_powerdn_chip;
+            end
+            else
+            begin
+                deep_pdown_chip_req <= 0;
+            end
+        end
+    end
+    
+    //combi user refresh
+    always @(*)
+    begin
+        if (cfg_user_rfsh)
+        begin
+            if (rfsh_req)
+            begin
+                refresh_req      = 1'b1;
+                refresh_chip_req = rfsh_chip;
+            end
+            else
+            begin
+                refresh_req      = 1'b0;
+                refresh_chip_req = 0;
+            end
+        end
+        else
+        begin
+            refresh_req      = |cs_refresh_req;
+            refresh_chip_req =  cs_refresh_req;
+        end
+    end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            afi_seq_busy_r  <= 0;
+            afi_seq_busy_r2 <= 0;
+        end
+        else
+        begin
+            afi_seq_busy_r  <= afi_seq_busy;
+            afi_seq_busy_r2 <= afi_seq_busy_r;
+        end
+    end
+    
+    // cans
+    generate
+        genvar w_cs;
+        for (w_cs = 0;w_cs < CFG_MEM_IF_CHIP;w_cs = w_cs + 1)
+        begin : can_signal_per_chip
+            // Can refresh signal for each rank
+            always @ (*)
+            begin
+                can_refresh    [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs]                                         & ~grant;
+            end
+            
+            // Can self refresh signal for each rank
+            always @ (*)
+            begin
+                can_self_rfsh  [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
+            end
+            
+            always @ (*)
+            begin
+                can_deep_pdown [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
+            end
+            
+            // Can power down signal for each rank
+            always @ (*)
+            begin
+                can_power_down [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
+            end
+            
+            // Can exit power saving mode signal for each rank
+            always @ (*)
+            begin
+                can_exit_power_saving_mode [w_cs] = power_saving_exit_ready [w_cs];
+            end
+        end
+    endgenerate
+    
+/*------------------------------------------------------------------------------
+
+    [START] Power Saving Rank Monitor
+
+------------------------------------------------------------------------------*/
+    /*------------------------------------------------------------------------------
+        Power Saving State Machine
+    ------------------------------------------------------------------------------*/
+    generate
+        genvar u_cs;
+        for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
+        begin : power_saving_logic_per_chip
+            reg  [POWER_SAVING_COUNTER_WIDTH      - 1 : 0] power_saving_cnt;
+            reg  [POWER_SAVING_EXIT_COUNTER_WIDTH - 1 : 0] power_saving_exit_cnt;
+            reg  [8                                   : 0] state;
+            reg  [2                                   : 0] sideband_state;
+            reg  [1                                   : 0] disable_clk_state;
+            reg                                            disable_clk_state_busy;
+            reg                                            disable_clk_state_busy_r;
+            reg                                            int_enter_power_saving_ready;
+            reg                                            int_exit_power_saving_ready;
+            reg                                            registered_reset;
+            reg                                            int_zq_cal_req;
+            reg                                            int_do_power_down;
+            reg                                            int_do_power_down_r1;
+            reg                                            int_do_deep_power_down;
+            reg                                            int_do_deep_power_down_r1;
+            reg                                            int_do_self_refresh;
+            reg                                            int_do_self_refresh_r1;
+            reg [DISABLE_CLK_COUNTER_WIDTH        - 1 : 0] disable_clk_cnt;
+            reg                                            disable_clk_entry;
+            reg                                            disable_clk_exit;
+            reg                                            int_disable_clk;
+            reg                                            int_disable_clk_r1;
+            reg                                            in_refresh;
+            
+            // assignment
+            assign power_saving_enter_ready [u_cs] = int_enter_power_saving_ready;
+            assign power_saving_exit_ready  [u_cs] = int_exit_power_saving_ready  & ~((int_do_power_down & ~int_do_power_down_r1) | (int_do_self_refresh & ~int_do_self_refresh_r1) | (int_do_deep_power_down & ~int_do_deep_power_down_r1));
+            
+            assign cs_zq_cal_req            [u_cs] = int_zq_cal_req;
+            
+            // Counter for power saving state machine
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    power_saving_cnt <= 0;
+                end
+                else
+                begin
+                    if (do_precharge_all[u_cs] || do_refresh[u_cs] || do_self_rfsh[u_cs] || do_power_down[u_cs])
+                    begin
+                        power_saving_cnt <= BANK_TIMER_COUNTER_OFFSET;
+                    end
+                    else if (power_saving_cnt != {POWER_SAVING_COUNTER_WIDTH{1'b1}})
+                    begin
+                        power_saving_cnt <= power_saving_cnt + 1'b1;
+                    end
+                end
+            end
+            
+            // Counter for power saving exit cycles
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    power_saving_exit_cnt <= 0;
+                end
+                else
+                begin
+                    if ((int_do_power_down & !int_do_power_down_r1) || (int_do_self_refresh & !int_do_self_refresh_r1) || (int_do_deep_power_down & !int_do_deep_power_down_r1))
+                    begin
+                        power_saving_exit_cnt <= BANK_TIMER_COUNTER_OFFSET;
+                    end
+                    else if (power_saving_exit_cnt != {POWER_SAVING_EXIT_COUNTER_WIDTH{1'b1}})
+                    begin
+                        power_saving_exit_cnt <= power_saving_exit_cnt + 1'b1;
+                    end
+                end
+            end
+            
+            // Disable clock counter
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    disable_clk_cnt <= 0;
+                end
+                else
+                begin
+                    if ((int_do_self_refresh & !int_do_self_refresh_r1) || (int_do_deep_power_down & !int_do_deep_power_down_r1) || (!int_disable_clk & int_disable_clk_r1))
+                    begin
+                        disable_clk_cnt <= BANK_TIMER_COUNTER_OFFSET;
+                    end
+                    else if (disable_clk_cnt != {DISABLE_CLK_COUNTER_WIDTH{1'b1}})
+                    begin
+                        disable_clk_cnt <= disable_clk_cnt + 1'b1;
+                    end
+                end
+            end
+            
+            // Do power down, deep power down and self refresh register
+            always @ (*)
+            begin
+                int_do_power_down = do_power_down[u_cs];
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_do_power_down_r1 <= 1'b0;
+                end
+                else
+                begin
+                    int_do_power_down_r1 <= int_do_power_down;
+                end
+            end
+            
+            always @ (*)
+            begin
+                int_do_deep_power_down = do_deep_pdown[u_cs];
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_do_deep_power_down_r1 <= 1'b0;
+                end
+                else
+                begin
+                    int_do_deep_power_down_r1 <= int_do_deep_power_down;
+                end
+            end
+            
+            always @ (*)
+            begin
+                int_do_self_refresh = do_self_rfsh[u_cs];
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_do_self_refresh_r1 <= 1'b0;
+                end
+                else
+                begin
+                    int_do_self_refresh_r1 <= int_do_self_refresh;
+                end
+            end
+            
+            // Disable clock registers
+            always @ (*)
+            begin
+                int_disable_clk = disable_clk[u_cs];
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_disable_clk_r1 <= 1'b0;
+                end
+                else
+                begin
+                    int_disable_clk_r1 <= int_disable_clk;
+                end
+            end
+            
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    disable_clk_state_busy_r <= 1'b0;
+                end
+                else
+                begin
+                    disable_clk_state_busy_r <= disable_clk_state_busy;
+                end
+            end
+            
+            // Power saving mode exit ready information
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    int_exit_power_saving_ready <= 1'b0;
+                end
+                else
+                begin
+                    if      ((int_do_power_down)      && (!int_do_power_down_r1))       // positive edge detector but late by one clock cycle
+                    begin
+                        int_exit_power_saving_ready <= 1'b0;
+                    end
+                    else if ((int_do_self_refresh)    && (!int_do_self_refresh_r1))     // positive edge detector
+                    begin
+                        int_exit_power_saving_ready <= 1'b0;
+                    end
+                    else if ((int_do_deep_power_down) && (!int_do_deep_power_down_r1))  // positive edge detector
+                    begin
+                        int_exit_power_saving_ready <= 1'b0;
+                    end
+                    else if (power_saving_exit_cnt >= t_param_power_saving_exit)
+                    begin
+                        int_exit_power_saving_ready <= 1'b1;
+                    end
+                    else
+                    begin
+                        int_exit_power_saving_ready <= 1'b0;
+                    end
+                end
+            end
+            
+            // Disable clock entry and exit logic
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    disable_clk_entry <= 1'b0;
+                    disable_clk_exit  <= 1'b0;
+                end
+                else
+                begin
+                    if      ((int_do_self_refresh)    && (!int_do_self_refresh_r1))     // positive edge detector
+                    begin
+                        disable_clk_entry <= 1'b0;
+                        disable_clk_exit  <= 1'b0;
+                    end
+                    else if ((int_do_deep_power_down) && (!int_do_deep_power_down_r1))  // positive edge detector
+                    begin
+                        disable_clk_entry <= 1'b0;
+                        disable_clk_exit  <= 1'b0;
+                    end
+                    else if ((!int_disable_clk)       && (int_disable_clk_r1))          // negative edge detector
+                    begin
+                        disable_clk_entry <= 1'b0;
+                        disable_clk_exit  <= 1'b0;
+                    end
+                    else if (disable_clk_cnt >= t_param_mem_clk_entry_cycles)
+                    begin
+                        disable_clk_entry <= 1'b1;
+                        disable_clk_exit  <= 1'b1;
+                    end
+                    else
+                    begin
+                        disable_clk_entry <= 1'b0;
+                        disable_clk_exit  <= 1'b0;
+                    end
+                end
+            end
+            
+            // stall_chip output signal
+            always @ (*)
+            begin
+                if (CFG_RANK_TIMER_OUTPUT_REG)
+                begin
+                    stall_chip[u_cs] = int_stall_chip[u_cs] | int_stall_chip_combi[u_cs];
+                end
+                else
+                begin
+                    stall_chip[u_cs] = int_stall_chip[u_cs];
+                end
+            end
+            
+            // int_stall_chip_combi signal, we need to issue stall chip one clock cycle earlier to rank timer
+            // because rank timer is using a register output
+            always @ (*)
+            begin
+                if (state == IDLE_S3)
+                begin
+                    if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
+                    begin
+                        int_stall_chip_combi[u_cs] = 1'b1;
+                    end
+                    else if (self_refresh_chip_req[u_cs])
+                    begin
+                        int_stall_chip_combi[u_cs] = 1'b1;
+                    end
+                    else if (deep_pdown_chip_req[u_cs])
+                    begin
+                        int_stall_chip_combi[u_cs] = 1'b1;
+                    end
+                    else if (power_down_chip_req_combi[u_cs])
+                    begin
+                        int_stall_chip_combi[u_cs] = 1'b1;
+                    end
+                    else
+                    begin
+                        int_stall_chip_combi[u_cs] = 1'b0;
+                    end
+                end
+                else
+                begin
+                    int_stall_chip_combi[u_cs] = 1'b0;
+                end
+            end
+            
+            // command issuing state machine
+            always @(posedge ctl_clk, negedge ctl_reset_n)
+            begin : FSM
+                if (!ctl_reset_n)
+                begin
+                    state                      <= INIT;
+                    int_stall_chip[u_cs]       <= 1'b0;
+                    stall_arbiter[u_cs]        <= 1'b0;
+                    do_power_down[u_cs]        <= 1'b0;
+                    do_deep_pdown[u_cs]        <= 1'b0;
+                    do_self_rfsh_req[u_cs]     <= 1'b0;
+                    do_zqcal_req[u_cs]         <= 1'b0;
+                    doing_zqcal[u_cs]          <= 1'b0;
+                    do_pch_all_req[u_cs]       <= 1'b0;
+                    do_refresh_req[u_cs]       <= 1'b0;
+                    afi_ctl_refresh_done[u_cs] <= 1'b0;
+                    dqstrk_exit[u_cs]          <= 1'b0;
+                    init_req[u_cs]             <= 1'b0;
+                    trk_rfsh_cntr[u_cs]        <= 0;
+                end
+                else
+                begin
+                    case(state)
+                        INIT :
+                            begin
+                                if (ctl_cal_success == 1'b1)
+                                begin
+                                    state                <= IDLE_S3;
+                                    int_stall_chip[u_cs] <= 1'b0;
+                                end
+                                else
+                                begin
+                                    state                <= INIT;
+                                    int_stall_chip[u_cs] <= 1'b1;
+                                end
+                            end
+                        IDLE_S3 :
+                            begin
+                                do_pch_all_req[u_cs] <= 1'b0;
+                                
+                                if (do_zqcal_req[u_cs])
+                                begin
+                                    if (do_zqcal[u_cs])
+                                    begin
+                                        do_zqcal_req[u_cs]  <= 1'b0;
+                                        doing_zqcal[u_cs]   <= 1'b0;
+                                        stall_arbiter[u_cs] <= 1'b0;
+                                    end
+                                end
+                                else if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
+                                begin
+                                    int_stall_chip[u_cs] <= 1'b1;
+                                    
+                                    if (all_banks_closed[u_cs])
+                                    begin
+                                        state <= REFRESH;
+                                    end
+                                    else
+                                    begin
+                                        state <= PCHALL;
+                                    end
+                                end
+                                else if (self_refresh_chip_req[u_cs])
+                                begin
+                                    int_stall_chip[u_cs] <= 1'b1;
+                                    
+                                    if (all_banks_closed[u_cs])
+                                    begin
+                                        state <= SELFRFSH;
+                                    end
+                                    else
+                                    begin
+                                        state <= PCHALL;
+                                    end
+                                end
+                                else if (deep_pdown_chip_req[u_cs])
+                                begin
+                                    int_stall_chip[u_cs] <= 1'b1;
+                                    
+                                    if (all_banks_closed[u_cs])
+                                    begin
+                                        state <= DEEPPDN;
+                                    end
+                                    else
+                                    begin
+                                        state <= PCHALL;
+                                    end
+                                end
+                                else if (power_down_chip_req_combi[u_cs])
+                                begin
+                                    int_stall_chip[u_cs] <= 1'b1;
+                                    
+                                    if (all_banks_closed[u_cs])
+                                    begin
+                                        state <= PDOWN;
+                                    end
+                                    else
+                                    begin
+                                        state <= PCHALL;
+                                    end
+                                end
+                                else if (int_stall_chip[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
+                                begin
+                                    int_stall_chip[u_cs] <= 1'b0;
+                                end
+                            end
+                        PCHALL :
+                            begin
+                                if (refresh_chip_req[u_cs] | self_refresh_chip_req[u_cs] | power_down_chip_req_combi[u_cs] | deep_pdown_chip_req[u_cs])
+                                begin
+                                    if (do_precharge_all[u_cs] || all_banks_closed[u_cs])
+                                    begin
+                                        do_pch_all_req[u_cs] <= 1'b0;
+                                        stall_arbiter[u_cs]  <= 1'b0;
+                                        
+                                        if (refresh_chip_req[u_cs])
+                                        begin
+                                            state <= REFRESH;
+                                        end
+                                        else if (self_refresh_chip_req[u_cs])
+                                        begin
+                                            state <= SELFRFSH;
+                                        end
+                                        else if (deep_pdown_chip_req[u_cs])
+                                        begin
+                                            state <= DEEPPDN;
+                                        end
+                                        else
+                                        begin
+                                            state <= PDOWN;
+                                        end
+                                    end
+                                    else if (refresh_chip_req[u_cs])
+                                    begin
+                                        if ((~all_banks_closed & refresh_chip_req     ) == (~all_banks_closed & tcom_not_running & refresh_chip_req     ) && !grant)
+                                        begin
+                                            do_pch_all_req[u_cs] <= 1'b1;
+                                            stall_arbiter[u_cs]  <= 1'b1;
+                                        end
+                                    end
+                                    else if (self_refresh_chip_req[u_cs])
+                                    begin
+                                        if ((~all_banks_closed & self_refresh_chip_req) == (~all_banks_closed & tcom_not_running & self_refresh_chip_req) && !grant)
+                                        begin
+                                            do_pch_all_req[u_cs] <= 1'b1;
+                                            stall_arbiter[u_cs]  <= 1'b1;
+                                        end
+                                    end
+                                    else if (&tcom_not_running && !grant) // for power down and deep power down request, since these request must go to all chips
+                                    begin
+                                        do_pch_all_req[u_cs] <= 1'b1;
+                                        stall_arbiter[u_cs]  <= 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    state                <= IDLE_S3;
+                                    do_pch_all_req[u_cs] <= 1'b0;
+                                    stall_arbiter[u_cs]  <= 1'b0;
+                                end
+                            end
+                        REFRESH :
+                            begin
+                                if (do_refresh[u_cs])
+                                begin
+                                    do_refresh_req[u_cs] <= 1'b0;
+                                    stall_arbiter[u_cs]  <= 1'b0;
+                                    if (cfg_enable_dqs_tracking && (do_refresh_to_all_chip | do_refresh_to_all_chip_r))
+                                        trk_rfsh_cntr[u_cs]  <= trk_rfsh_cntr[u_cs] + 1'b1;
+                                    
+                                    if (cfg_enable_dqs_tracking && (do_refresh_to_all_chip | do_refresh_to_all_chip_r) && trk_rfsh_cntr[u_cs] == SAMPLE_EVERY_N_RFSH)
+                                    begin
+                                        state <= DQSTRK;
+                                        trk_rfsh_cntr[u_cs] <= 0;
+                                    end
+                                    else if (power_down_chip_req_combi[u_cs])
+                                    begin
+                                        state <= PDOWN;
+                                    end
+                                    else if (zqcal_req)
+                                    begin
+                                        state <= ZQCAL;
+                                        doing_zqcal[u_cs] <= 1'b1;
+                                    end
+                                    else
+                                    begin
+                                        state <= IDLE_S3;
+                                    end
+                                end
+                                else if (refresh_chip_req[u_cs])
+                                begin
+                                    if (!all_banks_closed[u_cs])
+                                    begin
+                                        state <= PCHALL;
+                                    end
+                                    else if (refresh_chip_req == (can_refresh & refresh_chip_req))
+                                    begin
+                                        do_refresh_req[u_cs] <= 1'b1;
+                                        stall_arbiter[u_cs]  <= 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (zqcal_req)
+                                    begin
+                                        state <= ZQCAL;
+                                        doing_zqcal[u_cs] <= 1'b1;
+                                    end
+                                    else
+                                    begin
+                                    state <= IDLE_S3;
+                                    end
+                                    stall_arbiter[u_cs] <= 1'b0;
+                                end
+                            end
+                        SELFRFSH :
+                            begin
+                                if (!all_banks_closed[u_cs])
+                                begin
+                                    state <= PCHALL;
+                                end
+                                else if (!self_refresh_chip_req[u_cs] && can_exit_power_saving_mode[u_cs] && !disable_clk_state_busy)
+                                begin
+                                    do_self_rfsh_req[u_cs] <= 1'b0;
+                                    stall_arbiter[u_cs]    <= 1'b0;
+                                    
+                                    if (cfg_type == `MMR_TYPE_DDR3) // DDR3
+                                    begin
+                                        state             <= ZQCAL;
+                                        doing_zqcal[u_cs] <= 1'b1;
+                                    end
+                                    else
+                                    begin
+                                        state <= IDLE_S3;
+                                    end
+                                end
+                                else if (do_self_rfsh_req_r2[u_cs])
+                                begin
+                                    stall_arbiter[u_cs] <= 1'b0; // only assert for three clock cycle for self refresh entry (thress instead of one to solve conflicting command issues in half/quarter rate and regdimm design)
+                                end
+                                else if (self_refresh_chip_req == (can_self_rfsh & self_refresh_chip_req) && !(|do_precharge_all))
+                                begin
+                                    do_self_rfsh_req[u_cs] <= 1'b1;
+                                    stall_arbiter[u_cs]    <= 1'b1;
+                                end
+                            end
+                        PDOWN :
+                            begin
+                                if (refresh_chip_req[u_cs] && !do_refresh[u_cs] && can_exit_power_saving_mode[u_cs])
+                                begin
+                                    state               <= REFRESH;
+                                    do_power_down[u_cs] <= 1'b0;
+                                    stall_arbiter[u_cs] <= 1'b0;
+                                end
+                                else if (!power_down_chip_req_combi[u_cs] && can_exit_power_saving_mode[u_cs])
+                                begin
+                                    do_power_down[u_cs] <= 1'b0;
+                                    stall_arbiter[u_cs] <= 1'b0;
+                                    state               <= IDLE_S3;
+                                end
+                                else if (&can_power_down && !refresh_req)
+                                begin
+                                    do_power_down[u_cs] <= 1'b1;
+                                    stall_arbiter[u_cs] <= 1'b1;
+                                end
+                                else
+                                begin
+                                    state <= PDOWN;
+                                end
+                            end
+                        DEEPPDN :
+                            begin
+                                if (!all_banks_closed[u_cs])
+                                begin
+                                    state <= PCHALL;
+                                end
+                                else if (!deep_pdown_chip_req[u_cs] && can_exit_power_saving_mode[u_cs] && !disable_clk_state_busy)
+                                begin
+                                    do_deep_pdown[u_cs] <= 1'b0;
+                                    state               <= INITREQ;
+                                end
+                                else if (&can_deep_pdown && !(|do_precharge_all))
+                                begin
+                                    do_deep_pdown[u_cs] <= 1'b1;
+                                    stall_arbiter[u_cs] <= 1'b1;
+                                end
+                            end
+                        ZQCAL :
+                            begin
+                                if (cs_zq_cal_req[u_cs])
+                                begin
+                                    do_zqcal_req[u_cs]  <= 1'b1;
+                                    stall_arbiter[u_cs] <= 1'b1;
+                                    
+                                    state <= IDLE_S3;
+                                end
+                            end
+                        DQSTRK :
+                            begin
+                                if      (!dqstrk_exit[u_cs] && !afi_ctl_refresh_done[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
+                                begin
+                                    afi_ctl_refresh_done[u_cs] <= 1'b1;
+                                end
+                                else if (!dqstrk_exit[u_cs] &&  afi_ctl_refresh_done[u_cs] && afi_seq_busy_r2[u_cs]) // stall until seq_busy is deasserted
+                                begin
+                                    dqstrk_exit[u_cs] <= 1'b1;
+                                end
+                                else if (dqstrk_exit[u_cs] && !afi_seq_busy_r2[u_cs])
+                                begin
+                                    afi_ctl_refresh_done[u_cs] <= 1'b0;
+                                    dqstrk_exit[u_cs]          <= 1'b0;
+                                    state                      <= IDLE_S3;
+                                end
+                            end
+                        INITREQ :
+                            begin
+                                if (!init_req[u_cs])
+                                begin
+                                    init_req[u_cs] <= 1'b1;
+                                end
+                                else if (!ctl_cal_success) // wait for cal_success to go low
+                                begin
+                                    init_req[u_cs] <= 1'b0;
+                                    state          <= INIT;
+                                end
+                            end
+                        default :
+                            begin
+                                state <= IDLE_S3;
+                            end
+                    endcase
+                end
+            end
+            
+            // Disable memory clock state
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    disable_clk_state      <= IDLE_S2;
+                    disable_clk_state_busy <= 1'b0;
+                    disable_clk[u_cs]      <= 1'b0;
+                end
+                else
+                begin
+                    case (disable_clk_state)
+                        IDLE_S2 :
+                            begin
+                                if (do_self_rfsh[u_cs] && !disable_clk_state_busy_r) // to prevent it from re-entering disable clock state
+                                begin
+                                    disable_clk_state      <= DISABLECLK1;
+                                    disable_clk_state_busy <= 1'b1;
+                                end
+                                else if (do_deep_pdown[u_cs] && !disable_clk_state_busy_r) // to prevent it from re-entering disable clock state
+                                begin
+                                    disable_clk_state      <= DISABLECLK1;
+                                    disable_clk_state_busy <= 1'b1;
+                                end
+                                else
+                                begin
+                                    disable_clk_state      <= IDLE_S2;
+                                    disable_clk_state_busy <= 1'b0;
+                                    disable_clk[u_cs]      <= 1'b0;
+                                end
+                            end
+                        DISABLECLK1 :
+                            begin
+                                if ((!deep_pdown_chip_req[u_cs] && !self_refresh_chip_req[u_cs]) && can_exit_power_saving_mode[u_cs]) // exit both power saving state
+                                begin
+                                    disable_clk_state <= DISABLECLK2;
+                                    disable_clk[u_cs] <= 1'b0;
+                                end
+                                else if (disable_clk_entry) // can disable memory clock now
+                                begin
+                                    disable_clk[u_cs] <= 1'b1;
+                                end
+                            end
+                        DISABLECLK2 :
+                            begin
+                                if (!(!int_disable_clk && int_disable_clk_r1) && disable_clk_exit) // delay by N clock cycles before exting deep power down or self refresh
+                                begin
+                                    disable_clk_state      <= IDLE_S2;
+                                    disable_clk_state_busy <= 1'b0;
+                                end
+                            end
+                        default :
+                            begin
+                                disable_clk_state <= IDLE_S2;
+                            end
+                    endcase
+                end
+            end
+            
+            // sideband state machine
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    sideband_state               <= IDLE_S1;
+                    int_enter_power_saving_ready <= 1'b0;
+                    int_zq_cal_req               <= 1'b0;
+                    sideband_in_refresh[u_cs]    <= 1'b0;
+                end
+                else
+                begin
+                    case (sideband_state)
+                        IDLE_S1 :
+                            begin
+                                int_zq_cal_req <= 1'b0;
+                                
+                                if (power_saving_cnt >= t_param_pch_all_to_valid)
+                                begin
+                                    int_enter_power_saving_ready <= 1'b1;
+                                end
+                                else
+                                begin
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                                
+                                if (do_precharge_all[u_cs])
+                                begin
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                                
+                                if (do_refresh[u_cs])
+                                begin
+                                    sideband_state               <= ARF;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                    
+                                end
+                                
+                                if (do_self_rfsh[u_cs])
+                                begin
+                                    sideband_state               <= SRF;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                                
+                                if (do_power_down[u_cs])
+                                begin
+                                    sideband_state               <= PDN;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                               
+                                if (do_refresh[u_cs])
+                                begin
+                                    sideband_in_refresh[u_cs]    <= 1'b1;
+                                end
+                                else
+                                begin
+                                    sideband_in_refresh[u_cs]    <= 1'b0;
+                                end
+                                          
+                            end
+                        ARF :
+                            begin
+                                if (power_saving_cnt >= t_param_arf_to_valid)
+                                begin
+                                    sideband_state               <= IDLE_S1;
+                                    int_enter_power_saving_ready <= 1'b1;
+                                    sideband_in_refresh[u_cs]    <= 1'b0;
+                                    int_zq_cal_req               <= 1'b1;
+                                end
+                                else
+                                begin
+                                    sideband_state               <= ARF;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                    sideband_in_refresh[u_cs]    <= 1'b1;
+                                    int_zq_cal_req               <= 1'b0;
+                                end
+                            end
+                        SRF :
+                            begin
+                                sideband_in_refresh[u_cs]          <= 1'b0;
+										  
+                                // ZQ request to state machine
+                                if (power_saving_cnt == t_param_srf_to_zq_cal) // only one cycle
+                                begin
+                                    int_zq_cal_req <= 1'b1;
+                                end
+                                else
+                                begin
+                                    int_zq_cal_req <= 1'b0;
+                                end
+                                
+                                if (!do_self_rfsh[u_cs] && power_saving_cnt >= t_param_srf_to_valid)
+                                begin
+                                    sideband_state               <= IDLE_S1;
+                                    int_enter_power_saving_ready <= 1'b1;
+                                end
+                                else
+                                begin
+                                    sideband_state               <= SRF;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                            end
+                        PDN :
+                            begin
+                                int_zq_cal_req <= 1'b0;
+                                sideband_in_refresh[u_cs]          <= 1'b0;
+                                
+                                if (!do_power_down[u_cs] && power_saving_cnt >= t_param_pdn_to_valid)
+                                begin
+                                    sideband_state               <= IDLE_S1;
+                                    int_enter_power_saving_ready <= 1'b1;
+                                end
+                                else
+                                begin
+                                    sideband_state               <= PDN;
+                                    int_enter_power_saving_ready <= 1'b0;
+                                end
+                            end
+                        default :
+                            begin
+                                sideband_state <= IDLE_S1;
+                                sideband_in_refresh[u_cs]          <= 1'b0;
+                            end
+                    endcase
+                end
+            end
+        end
+    endgenerate
+    
+    /*------------------------------------------------------------------------------
+        Refresh Request
+    ------------------------------------------------------------------------------*/
+    generate
+        genvar s_cs;
+        for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
+        begin : auto_refresh_logic_per_chip
+            reg [ARF_COUNTER_WIDTH - 1 : 0] refresh_cnt;
+            
+            // refresh counter
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    refresh_cnt <= 0;
+                end
+                else
+                begin
+                    if (self_rfsh_req && !self_rfsh_req_r && |self_rfsh_chip && !do_refresh[s_cs])
+                    begin
+                        refresh_cnt <= {ARF_COUNTER_WIDTH{1'b1}};
+                    end
+                    else if (do_refresh[s_cs])
+                    begin
+                        refresh_cnt <= 3;
+                    end
+                    else if (refresh_cnt != {ARF_COUNTER_WIDTH{1'b1}})
+                    begin
+                        refresh_cnt <= refresh_cnt + 1'b1;
+                    end
+                end
+            end
+            
+            // refresh request logic
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    cs_refresh_req [s_cs] <= 1'b0;
+                end
+                else
+                begin
+                    if (self_rfsh_req && !self_rfsh_req_r && |self_rfsh_chip && !do_refresh[s_cs])
+                    begin
+                        cs_refresh_req [s_cs] <= 1'b1;
+                    end
+                    else if (do_refresh[s_cs] || do_self_rfsh[s_cs])
+                    begin
+                        cs_refresh_req [s_cs] <= 1'b0;
+                    end
+                    else if (refresh_cnt >= t_param_arf_period)
+                    begin
+                        cs_refresh_req [s_cs] <= 1'b1;
+                    end
+                    else
+                    begin
+                        cs_refresh_req [s_cs] <= 1'b0;
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    /*------------------------------------------------------------------------------
+        Power Down Request
+    ------------------------------------------------------------------------------*/
+    // register no command signal
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            no_command_r1 <= 1'b0;
+        end
+        else
+        begin
+            no_command_r1 <= tbp_empty;
+        end
+    end
+    
+    // power down counter
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            power_down_cnt <= 0;
+        end
+        else
+        begin
+            if ((!tbp_empty && no_command_r1) || self_rfsh_req) // negative edge detector
+            begin
+                power_down_cnt <= 3;
+            end
+            else if (tbp_empty && power_down_cnt != {PDN_COUNTER_WIDTH{1'b1}} && ctl_cal_success)
+            begin
+                power_down_cnt <= power_down_cnt + 1'b1;
+            end
+        end
+    end
+    
+    // power down request logic
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            power_down_chip_req <= 0;
+        end
+        else
+        begin
+            if (t_param_pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
+            begin
+                power_down_chip_req <= 0;
+            end
+            else
+            begin
+                if (!tbp_empty || self_rfsh_req) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
+                begin
+                    power_down_chip_req <= 0;
+                end
+                else if (power_down_chip_req == 0)
+                begin
+                    if (power_down_cnt >= t_param_pdn_period && !(|doing_zqcal))
+                    begin
+                        power_down_chip_req <= {CFG_MEM_IF_CHIP{1'b1}};
+                    end
+                    else
+                    begin
+                        power_down_chip_req <= 0;
+                    end
+                end
+                else if (!(power_down_cnt >= t_param_pdn_period))
+                begin
+                    power_down_chip_req <= 0;
+                end
+            end
+        end
+    end
+    
+    assign power_down_chip_req_combi = power_down_chip_req & {CFG_MEM_IF_CHIP{tbp_empty}} & {CFG_MEM_IF_CHIP{~refresh_req}};
+
+/*------------------------------------------------------------------------------
+
+    [END] Power Saving Rank Monitor
+
+------------------------------------------------------------------------------*/
+    
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v
new file mode 100644
index 0000000..5ea7cb7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v
@@ -0,0 +1,3539 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// altera message_off 10230 10036
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_tbp
+    #( parameter
+        CFG_CTL_TBP_NUM                 =   4,
+        CFG_CTL_SHADOW_TBP_NUM          =   4,
+        CFG_ENABLE_SHADOW_TBP           =   0,
+        CFG_DWIDTH_RATIO                =   2,
+        CFG_CTL_ARBITER_TYPE            =   "ROWCOL",
+        CFG_MEM_IF_CHIP                 =   1, // one hot
+        CFG_MEM_IF_CS_WIDTH             =   1, // binary encoded
+        CFG_MEM_IF_BA_WIDTH             =   3,
+        CFG_MEM_IF_ROW_WIDTH            =   13,
+        CFG_MEM_IF_COL_WIDTH            =   10,
+        CFG_LOCAL_ID_WIDTH              =   8,
+        CFG_INT_SIZE_WIDTH              =   4,
+        CFG_DATA_ID_WIDTH               =   10,
+        CFG_REG_REQ                     =   0,
+        CFG_REG_GRANT                   =   0,
+        CFG_DATA_REORDERING_TYPE        =   "INTER_BANK",
+        CFG_DISABLE_READ_REODERING      =   0,
+        CFG_DISABLE_PRIORITY            =   0,
+        CFG_PORT_WIDTH_REORDER_DATA     =   1,
+        CFG_PORT_WIDTH_STARVE_LIMIT     =   6,
+        CFG_PORT_WIDTH_TYPE             =   3,
+        T_PARAM_ACT_TO_RDWR_WIDTH       =   4,
+        T_PARAM_ACT_TO_ACT_WIDTH        =   4,
+        T_PARAM_ACT_TO_PCH_WIDTH        =   4,
+        T_PARAM_RD_TO_PCH_WIDTH         =   4,
+        T_PARAM_WR_TO_PCH_WIDTH         =   4,
+        T_PARAM_PCH_TO_VALID_WIDTH      =   4,
+        T_PARAM_RD_AP_TO_VALID_WIDTH    =   4,
+        T_PARAM_WR_AP_TO_VALID_WIDTH    =   4
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // Cmd gen interface
+        tbp_full,
+        tbp_empty,
+        cmd_gen_load,
+        cmd_gen_waiting_to_load,
+        cmd_gen_chipsel,
+        cmd_gen_bank,
+        cmd_gen_row,
+        cmd_gen_col,
+        cmd_gen_write,
+        cmd_gen_read,
+        cmd_gen_size,
+        cmd_gen_localid,
+        cmd_gen_dataid,
+        cmd_gen_priority,
+        cmd_gen_rmw_correct,
+        cmd_gen_rmw_partial,
+        cmd_gen_autopch,
+        cmd_gen_complete,
+        cmd_gen_same_chipsel_addr,
+        cmd_gen_same_bank_addr,
+        cmd_gen_same_row_addr,
+        cmd_gen_same_col_addr,
+        cmd_gen_same_read_cmd,
+        cmd_gen_same_write_cmd,
+        cmd_gen_same_shadow_chipsel_addr,
+        cmd_gen_same_shadow_bank_addr,
+        cmd_gen_same_shadow_row_addr,
+        
+        // Arbiter interface
+        row_req,
+        act_req,
+        pch_req,
+        row_grant,
+        act_grant,
+        pch_grant,
+        col_req,
+        rd_req,
+        wr_req,
+        col_grant,
+        rd_grant,
+        wr_grant,
+        log2_row_grant,
+        log2_col_grant,
+        log2_act_grant,
+        log2_pch_grant,
+        log2_rd_grant,
+        log2_wr_grant,
+        or_row_grant,
+        or_col_grant,
+        tbp_read,
+        tbp_write,
+        tbp_precharge,
+        tbp_activate,
+        tbp_chipsel,
+        tbp_bank,
+        tbp_row,
+        tbp_col,
+        tbp_shadow_chipsel,
+        tbp_shadow_bank,
+        tbp_shadow_row,
+        tbp_size,
+        tbp_localid,
+        tbp_dataid,
+        tbp_ap,
+        tbp_burst_chop,
+        tbp_age,
+        tbp_priority,
+        tbp_rmw_correct,
+        tbp_rmw_partial,
+        sb_tbp_precharge_all,
+        sb_do_precharge_all,
+        
+        // Timer value
+        t_param_act_to_rdwr,
+        t_param_act_to_act,
+        t_param_act_to_pch,
+        t_param_rd_to_pch,
+        t_param_wr_to_pch,
+        t_param_pch_to_valid,
+        t_param_rd_ap_to_valid,
+        t_param_wr_ap_to_valid,
+        
+        // Misc interface
+        tbp_bank_closed,
+        tbp_timer_ready,
+        tbp_load,
+        data_complete,
+        data_rmw_complete,
+        data_rmw_fetch,
+        
+        // Config interface
+        cfg_reorder_data,
+        cfg_starve_limit,
+        cfg_type,
+        cfg_enable_ecc,
+        cfg_enable_no_dm
+    );
+    
+    localparam integer CFG_MEM_IF_BA_WIDTH_SQRD     = 2**CFG_MEM_IF_BA_WIDTH;
+    localparam         TBP_COUNTER_OFFSET           = (CFG_REG_GRANT) ? 2 : 1;
+    localparam          RDWR_AP_TO_VALID_WIDTH      = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
+    localparam          COL_TIMER_WIDTH             = T_PARAM_ACT_TO_RDWR_WIDTH;
+    localparam          ROW_TIMER_WIDTH             = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
+    localparam          TRC_TIMER_WIDTH             = T_PARAM_ACT_TO_ACT_WIDTH;
+    localparam          COMBINED_TIMER_WIDTH        = (ROW_TIMER_WIDTH > TRC_TIMER_WIDTH) ? ROW_TIMER_WIDTH : TRC_TIMER_WIDTH;
+    
+    // Start of port declaration
+    input   ctl_clk;
+    input   ctl_reset_n;
+    
+    output                               tbp_full;
+    output                               tbp_empty;
+    input                                cmd_gen_load;
+    input                                cmd_gen_waiting_to_load;
+    input   [CFG_MEM_IF_CS_WIDTH-1:0]    cmd_gen_chipsel;
+    input   [CFG_MEM_IF_BA_WIDTH-1:0]    cmd_gen_bank;
+    input   [CFG_MEM_IF_ROW_WIDTH-1:0]   cmd_gen_row;
+    input   [CFG_MEM_IF_COL_WIDTH-1:0]   cmd_gen_col;
+    input                                cmd_gen_write;
+    input                                cmd_gen_read;
+    input   [CFG_INT_SIZE_WIDTH-1:0]     cmd_gen_size;
+    input   [CFG_LOCAL_ID_WIDTH-1:0]     cmd_gen_localid;
+    input   [CFG_DATA_ID_WIDTH-1:0]      cmd_gen_dataid;
+    input                                cmd_gen_priority;
+    input                                cmd_gen_rmw_correct;
+    input                                cmd_gen_rmw_partial;
+    input                                cmd_gen_autopch;
+    input                                cmd_gen_complete;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_chipsel_addr;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_bank_addr;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_row_addr;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_col_addr;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_read_cmd;
+    input   [CFG_CTL_TBP_NUM-1:0]        cmd_gen_same_write_cmd;
+    input   [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
+    input   [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
+    input   [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
+    
+    output  [CFG_CTL_TBP_NUM-1:0]                               row_req;
+    output  [CFG_CTL_TBP_NUM-1:0]                               act_req;
+    output  [CFG_CTL_TBP_NUM-1:0]                               pch_req;
+    input   [CFG_CTL_TBP_NUM-1:0]                               row_grant;
+    input   [CFG_CTL_TBP_NUM-1:0]                               act_grant;
+    input   [CFG_CTL_TBP_NUM-1:0]                               pch_grant;
+    output  [CFG_CTL_TBP_NUM-1:0]                               col_req;
+    output  [CFG_CTL_TBP_NUM-1:0]                               rd_req;
+    output  [CFG_CTL_TBP_NUM-1:0]                               wr_req;
+    input   [CFG_CTL_TBP_NUM-1:0]                               col_grant;
+    input   [CFG_CTL_TBP_NUM-1:0]                               rd_grant;
+    input   [CFG_CTL_TBP_NUM-1:0]                               wr_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_row_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_col_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_act_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_pch_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_rd_grant;
+    input   [log2(CFG_CTL_TBP_NUM)-1:0]                         log2_wr_grant;
+    input                                                       or_row_grant;
+    input                                                       or_col_grant;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_read;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_write;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_precharge;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_activate;
+    output  [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]         tbp_chipsel;
+    output  [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]         tbp_bank;
+    output  [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0]        tbp_row;
+    output  [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0]        tbp_col;
+    output  [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]  tbp_shadow_chipsel;
+    output  [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]  tbp_shadow_bank;
+    output  [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
+    output  [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0]          tbp_size;
+    output  [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0]          tbp_localid;
+    output  [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0]           tbp_dataid;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_ap;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_burst_chop;
+    output  [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0]             tbp_age;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_priority;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_rmw_correct;
+    output  [CFG_CTL_TBP_NUM-1:0]                               tbp_rmw_partial;
+    input   [CFG_CTL_TBP_NUM-1:0]                               sb_tbp_precharge_all;
+    input   [CFG_MEM_IF_CHIP-1:0]                               sb_do_precharge_all;
+    
+    input   [T_PARAM_ACT_TO_RDWR_WIDTH-1:0]    t_param_act_to_rdwr;
+    input   [T_PARAM_ACT_TO_ACT_WIDTH-1:0]     t_param_act_to_act;
+    input   [T_PARAM_ACT_TO_PCH_WIDTH-1:0]     t_param_act_to_pch;
+    input   [T_PARAM_RD_TO_PCH_WIDTH-1:0]      t_param_rd_to_pch;
+    input   [T_PARAM_WR_TO_PCH_WIDTH-1:0]      t_param_wr_to_pch;
+    input   [T_PARAM_PCH_TO_VALID_WIDTH-1:0]   t_param_pch_to_valid;
+    input   [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
+    input   [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
+    
+    output  [CFG_MEM_IF_CHIP-1:0]              tbp_bank_closed;
+    output  [CFG_MEM_IF_CHIP-1:0]              tbp_timer_ready;
+    output  [CFG_CTL_TBP_NUM-1:0]              tbp_load;
+    input   [CFG_CTL_TBP_NUM-1:0]              data_complete;
+    input                                      data_rmw_complete;
+    output                                     data_rmw_fetch;
+    
+    input   [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
+    input   [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
+    input   [CFG_PORT_WIDTH_TYPE-1:0]         cfg_type;
+    input                                     cfg_enable_ecc;
+    input                                     cfg_enable_no_dm;
+    // End of port declaration
+    
+    // Logic operators
+    wire                          tbp_full;
+    wire                          tbp_empty;
+    wire    [CFG_CTL_TBP_NUM-1:0] tbp_load;
+    wire    [CFG_CTL_TBP_NUM-1:0] load_tbp;
+    wire    [CFG_CTL_TBP_NUM-1:0] load_tbp_index;	
+    wire    [CFG_CTL_TBP_NUM-1:0] flush_tbp;
+    reg     [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
+    reg     [CFG_CTL_TBP_NUM-1:0] row_req;
+    reg     [CFG_CTL_TBP_NUM-1:0] act_req;
+    reg     [CFG_CTL_TBP_NUM-1:0] pch_req;
+    reg     [CFG_CTL_TBP_NUM-1:0] col_req;
+    reg     [CFG_CTL_TBP_NUM-1:0] rd_req;
+    reg     [CFG_CTL_TBP_NUM-1:0] wr_req;
+    
+    wire                          cfg_enable_rmw;
+    
+    wire                          int_tbp_full;	
+    wire                          int_tbp_empty;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0]             valid;
+    reg     [CFG_CTL_TBP_NUM-1:0]             valid_combi;	
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]         chipsel      [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]         bank         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]        row          [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_COL_WIDTH-1:0]        col          [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             write;
+    reg     [CFG_CTL_TBP_NUM-1:0]             read;
+    wire    [CFG_CTL_TBP_NUM-1:0]             precharge;
+    wire    [CFG_CTL_TBP_NUM-1:0]             activate;
+    reg     [CFG_INT_SIZE_WIDTH-1:0]          size    [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             autopch;
+    reg     [CFG_LOCAL_ID_WIDTH-1:0]          localid      [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_DATA_ID_WIDTH-1:0]           dataid       [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             priority_a;
+    reg     [CFG_CTL_TBP_NUM-1:0]             activated;
+    reg     [CFG_CTL_TBP_NUM-1:0]             activated_p;
+    reg     [CFG_CTL_TBP_NUM-1:0]             activated_combi;
+    reg     [CFG_CTL_TBP_NUM-1:0]             precharged;
+    reg     [CFG_CTL_TBP_NUM-1:0]             precharged_combi;
+    reg     [CFG_CTL_TBP_NUM-1:0]             not_done_tbp_row_pass_flush;
+    reg     [CFG_CTL_TBP_NUM-1:0]             not_done_tbp_row_pass_flush_r;
+    reg     [CFG_CTL_TBP_NUM-1:0]             done_tbp_row_pass_flush;
+    reg     [CFG_CTL_TBP_NUM-1:0]             done_tbp_row_pass_flush_r;
+    reg     [CFG_CTL_TBP_NUM-1:0]             open_row_pass;
+    reg     [CFG_CTL_TBP_NUM-1:0]             open_row_pass_r;
+    reg     [CFG_CTL_TBP_NUM-1:0]             open_row_passed;
+    wire    [CFG_CTL_TBP_NUM-1:0]             open_row_pass_flush;
+    reg     [CFG_CTL_TBP_NUM-1:0]             open_row_pass_flush_r;
+    reg     [CFG_CTL_TBP_NUM-1:0]             log2_open_row_pass_flush   [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             done;
+    reg     [CFG_CTL_TBP_NUM-1:0]             done_combi;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete_rd;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete_wr;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete_combi;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete_combi_rd;
+    reg     [CFG_CTL_TBP_NUM-1:0]             complete_combi_wr;
+    reg     [CFG_CTL_TBP_NUM-1:0]             wst_p;
+    reg     [CFG_CTL_TBP_NUM-1:0]             ssb;
+    reg     [CFG_CTL_TBP_NUM-1:0]             ssbr;
+    reg     [CFG_CTL_TBP_NUM-1:0]             ap;
+    reg     [CFG_CTL_TBP_NUM-1:0]             real_ap;
+    reg     [CFG_CTL_TBP_NUM-1:0]             rmw_correct;
+    reg     [CFG_CTL_TBP_NUM-1:0]             rmw_partial;
+    reg     [CFG_CTL_TBP_NUM-1:0]             rmw;
+    reg     [CFG_CTL_TBP_NUM-1:0]             require_flush;
+    reg     [CFG_CTL_TBP_NUM-1:0]             require_flush_calc;
+    reg     [CFG_CTL_TBP_NUM-1:0]             require_pch_combi [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]             require_pch;
+    reg     [CFG_CTL_TBP_NUM-1:0]             burst_chop;
+    reg     [CFG_CTL_TBP_NUM-1:0]             age         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation  [CFG_CTL_TBP_NUM-1:0];
+    
+    // bit vectors
+    reg     [CFG_CTL_TBP_NUM-1:0] apvo_combi;   // vector for smart autopch open page
+    reg     [CFG_CTL_TBP_NUM-1:0] apvo;         // vector for smart autopch open page
+    reg     [CFG_CTL_TBP_NUM-1:0] apvc_combi;   // vector for smart autopch close page
+    reg     [CFG_CTL_TBP_NUM-1:0] apvc;         // vector for smart autopch close page
+    reg     [CFG_CTL_TBP_NUM-1:0] rpv_combi         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] rpv               [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] cpv_combi         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] cpv               [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] wrt_combi         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] wrt               [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] sbv_combi         [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] sbv               [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] sbvt_combi        [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0] sbvt              [CFG_CTL_TBP_NUM-1:0];
+    
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi  [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv        [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt       [CFG_CTL_TBP_NUM-1:0];
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] or_wrt;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] nor_rpv;
+    reg     [CFG_CTL_TBP_NUM-1:0] nor_cpv;
+    reg     [CFG_CTL_TBP_NUM-1:0] nor_sbv;
+    reg     [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
+    
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_read;
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_write;
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_ap;
+    wire    [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]         tbp_chipsel;
+    wire    [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]         tbp_bank;
+    wire    [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0]        tbp_row;
+    wire    [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0]        tbp_col;
+    wire    [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0]  tbp_shadow_chipsel;
+    wire    [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0]  tbp_shadow_bank;
+    wire    [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
+    wire    [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0]          tbp_size;
+    wire    [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0]          tbp_localid;
+    wire    [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0]           tbp_dataid;
+    wire    [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0]             tbp_age;
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_priority;
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_rmw_correct;
+    wire    [CFG_CTL_TBP_NUM-1:0]                               tbp_rmw_partial;
+    
+    wire    [CFG_MEM_IF_CHIP-1:0]                               tbp_bank_closed;
+    wire    [CFG_MEM_IF_CHIP-1:0]                               tbp_timer_ready;
+    reg     [CFG_MEM_IF_CHIP-1:0]                               bank_closed;
+    reg     [CFG_MEM_IF_CHIP-1:0]                               timer_ready;
+    reg     [CFG_CTL_TBP_NUM-1:0]                               int_bank_closed        [CFG_MEM_IF_CHIP-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]                               int_timer_ready        [CFG_MEM_IF_CHIP-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0]                        int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
+    
+    reg     [CFG_CTL_TBP_NUM-1:0]        same_command_read;
+    reg     [CFG_CTL_TBP_NUM-1:0]        same_chip_bank_row;
+    reg     [CFG_CTL_TBP_NUM-1:0]        same_chip_bank_diff_row;
+    reg     [CFG_CTL_TBP_NUM-1:0]        same_chip_bank;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
+    reg     [CFG_CTL_TBP_NUM-1:0]        pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]        pre_calculated_same_chip_bank_row      [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]        pre_calculated_same_chip_bank          [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank   [CFG_CTL_TBP_NUM-1:0];
+    
+    reg     [COL_TIMER_WIDTH-1:0]        col_timer           [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]        col_timer_ready;
+    reg     [CFG_CTL_TBP_NUM-1:0]        col_timer_pre_ready;
+    
+    reg     [COMBINED_TIMER_WIDTH-1:0]   combined_timer      [CFG_CTL_TBP_NUM-1:0];
+    reg     [ROW_TIMER_WIDTH-1:0]        row_timer_combi     [CFG_CTL_TBP_NUM-1:0];
+    reg     [ROW_TIMER_WIDTH-1:0]        row_timer           [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]        row_timer_ready;
+    reg     [CFG_CTL_TBP_NUM-1:0]        row_timer_pre_ready;
+    
+    reg     [TRC_TIMER_WIDTH-1:0]        trc_timer           [CFG_CTL_TBP_NUM-1:0];
+    reg     [CFG_CTL_TBP_NUM-1:0]        trc_timer_ready;
+    reg     [CFG_CTL_TBP_NUM-1:0]        trc_timer_pre_ready;
+    reg     [CFG_CTL_TBP_NUM-1:0]        trc_timer_pre_ready_combi;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] pch_ready;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
+    reg     [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
+    
+    reg                           compare_t_param_act_to_rdwr_less_than_offset;
+    reg                           compare_t_param_act_to_act_less_than_offset;
+    reg                           compare_t_param_act_to_pch_less_than_offset;
+    reg                           compare_t_param_rd_to_pch_less_than_offset;
+    reg                           compare_t_param_wr_to_pch_less_than_offset;
+    reg                           compare_t_param_pch_to_valid_less_than_offset;
+    reg                           compare_t_param_rd_ap_to_valid_less_than_offset;
+    reg                           compare_t_param_wr_ap_to_valid_less_than_offset;
+    
+    reg                           compare_offset_t_param_act_to_rdwr_less_than_0;
+    reg                           compare_offset_t_param_act_to_rdwr_less_than_1;
+    
+    reg     [T_PARAM_ACT_TO_RDWR_WIDTH-1:0]    offset_t_param_act_to_rdwr;
+    reg     [T_PARAM_ACT_TO_ACT_WIDTH-1:0]     offset_t_param_act_to_act;
+    reg     [T_PARAM_ACT_TO_PCH_WIDTH-1:0]     offset_t_param_act_to_pch;
+    reg     [T_PARAM_RD_TO_PCH_WIDTH-1:0]      offset_t_param_rd_to_pch;
+    reg     [T_PARAM_WR_TO_PCH_WIDTH-1:0]      offset_t_param_wr_to_pch;
+    reg     [T_PARAM_PCH_TO_VALID_WIDTH-1:0]   offset_t_param_pch_to_valid;
+    reg     [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
+    reg     [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] can_act;
+    reg     [CFG_CTL_TBP_NUM-1:0] can_pch;
+    reg     [CFG_CTL_TBP_NUM-1:0] can_rd;
+    reg     [CFG_CTL_TBP_NUM-1:0] can_wr;
+    
+    reg     [CFG_CTL_TBP_NUM-1:0] finish_tbp;
+    
+    wire    [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
+    reg     [CFG_MEM_IF_CS_WIDTH-1:0]    shadow_chipsel             [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_BA_WIDTH-1:0]    shadow_bank                [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    reg     [CFG_MEM_IF_ROW_WIDTH-1:0]   shadow_row                 [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    reg     [ROW_TIMER_WIDTH-1:0]        shadow_row_timer           [CFG_CTL_SHADOW_TBP_NUM-1:0];
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
+    reg     [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
+    
+    wire    one  = 1'b1;
+    wire    zero = 1'b0;
+    
+    integer i;
+    integer j;
+    genvar  k;
+    
+    //----------------------------------------------------------------------------------------------------
+    // Output port assignments
+    //----------------------------------------------------------------------------------------------------
+    assign tbp_read        = read;
+    assign tbp_write       = write;
+    assign tbp_ap          = real_ap;
+    assign tbp_burst_chop  = burst_chop;
+    assign tbp_precharge   = precharge;
+    assign tbp_activate    = activate;
+    assign tbp_priority    = priority_a;
+    assign tbp_rmw_correct = rmw_correct;
+    assign tbp_rmw_partial = rmw_partial;
+    
+    generate
+        begin
+            for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
+                begin : tbp_name
+                    assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH]    = chipsel[k];
+                    assign tbp_bank   [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH]    = bank   [k];
+                    assign tbp_row    [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row    [k];
+                    assign tbp_col    [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col    [k];
+                    assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH]       = localid[k];
+                    assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH]          = dataid [k];
+                    assign tbp_age    [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM]                = age    [k];
+                    assign tbp_size   [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH]       = size   [k];
+                end
+            
+            for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
+                begin : tbp_shadow_name
+                    if (CFG_ENABLE_SHADOW_TBP)
+                        begin
+                            assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH]    = shadow_chipsel[k];
+                            assign tbp_shadow_bank   [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH]    = shadow_bank   [k];
+                            assign tbp_shadow_row    [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row    [k];
+                        end
+                    else
+                        begin
+                            assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH]    = 0;
+                            assign tbp_shadow_bank   [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH]    = 0;
+                            assign tbp_shadow_row    [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
+                        end
+                end
+        end
+    endgenerate
+    
+    assign  tbp_full          = int_tbp_full;
+    assign  tbp_empty         = int_tbp_empty;
+    assign  int_tbp_empty     = &(valid ^~ done); // empty if valid and done are the same
+    assign  load_tbp          = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
+    assign  flush_tbp         = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
+    assign  tbp_load          = load_tbp;
+    assign  tbp_bank_closed   = bank_closed;
+    assign  tbp_timer_ready   = timer_ready;
+    assign  precharge         = activated;
+    assign  activate          = ~activated;
+    
+    //----------------------------------------------------------------------------------------------------
+    // TBP General Functions
+    //----------------------------------------------------------------------------------------------------
+    assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    valid_combi <= 0;
+                end
+            else
+                begin
+                    valid_combi <= (valid | load_tbp) & ~flush_tbp;
+                end
+        end
+
+    assign load_tbp_index = ~valid_combi & (valid_combi + 1);
+    assign int_tbp_full   = &valid_combi;
+
+    //----------------------------------------------------------------------------------------------------
+    // Finish TBP
+    //----------------------------------------------------------------------------------------------------
+    // Logic to determine when can we flush a done TBP
+    // in non-shadow TBP case, we can only flush once the timer finished counting
+    // in shadow TBP case, we can flush once it is pushed into shadow TBP
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                begin
+                    if (CFG_ENABLE_SHADOW_TBP)
+                        begin
+                            finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i]);
+                        end
+                    else
+                        begin
+                            finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i];
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Shadow TBP Logic
+    //----------------------------------------------------------------------------------------------------
+    // Determine when can we flush TBP
+    assign flush_shadow_tbp   = shadow_valid & shadow_row_timer_pre_ready;
+    
+    // Determine when it's ready to push into shadow TBP
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                begin
+                    if (CFG_ENABLE_SHADOW_TBP)
+                        begin
+                            if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
+                                begin
+                                    ready_to_push_tbp_combi[i] = 1'b0;
+                                end
+                            else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
+                                begin
+                                    ready_to_push_tbp_combi[i] = 1'b0;
+                                end
+                            else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
+                                begin
+                                    ready_to_push_tbp_combi[i] = 1'b1;
+                                end
+                            else
+                                begin
+                                    ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
+                                end
+                        end
+                    else
+                        begin
+                            ready_to_push_tbp_combi[i] = zero;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            ready_to_push_tbp[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
+                        end
+                end
+        end
+    
+    // Determine when to push into shadow TBP
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                begin
+                    if (CFG_ENABLE_SHADOW_TBP)
+                        begin
+                            if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
+                                begin
+                                    push_tbp_combi[i] = 1'b0;
+                                end
+                            else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
+                                begin
+                                    push_tbp_combi[i] = 1'b1;
+                                end
+                            else
+                                begin
+                                    push_tbp_combi[i] = push_tbp[i];
+                                end
+                        end
+                    else
+                        begin
+                            push_tbp_combi[i] = zero;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            push_tbp[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            push_tbp[i] <= push_tbp_combi[i];
+                        end
+                end
+        end
+    
+    // Shadow TBP information
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            shadow_chipsel[i] <= 0;
+                            shadow_bank   [i] <= 0;
+                            shadow_row    [i] <= 0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            if (CFG_ENABLE_SHADOW_TBP)
+                                begin
+                                    if (push_tbp_combi[i])
+                                        begin
+                                            shadow_chipsel[i] <= chipsel[i];
+                                            shadow_bank   [i] <= bank   [i];
+                                            shadow_row    [i] <= row    [i];
+                                        end
+                                end
+                            else
+                                begin
+                                    shadow_chipsel[i] <= 0;
+                                    shadow_bank   [i] <= 0;
+                                    shadow_row    [i] <= 0;
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            shadow_valid[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            if (CFG_ENABLE_SHADOW_TBP)
+                                begin
+                                    if (flush_shadow_tbp[i])
+                                        begin
+                                            shadow_valid[i] <= 1'b0;
+                                        end
+                                    else if (push_tbp[i])
+                                        begin
+                                            shadow_valid[i] <= 1'b1;
+                                        end
+                                end
+                            else
+                                begin
+                                    shadow_valid[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            shadow_row_timer          [i] <= 0;
+                            shadow_row_timer_pre_ready[i] <= 1'b0;
+                            shadow_row_timer_ready    [i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
+                        begin
+                            if (CFG_ENABLE_SHADOW_TBP)
+                                begin
+                                    if (push_tbp[i])
+                                        begin
+                                            if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
+                                                begin
+                                                    // Decide to take the larger timer value between row/trc timer
+                                                    if (row_timer[i] > trc_timer[i])
+                                                        begin
+                                                            shadow_row_timer[i] <= row_timer[i] - 1'b1;
+                                                        end
+                                                    else
+                                                        begin
+                                                            shadow_row_timer[i] <= trc_timer[i] - 1'b1;
+                                                        end
+                                                    
+                                                    shadow_row_timer_pre_ready[i] <= 1'b0;
+                                                    shadow_row_timer_ready    [i] <= 1'b0;
+                                                end
+                                            else
+                                                begin
+                                                    shadow_row_timer          [i] <= 0;
+                                                    shadow_row_timer_pre_ready[i] <= 1'b1;
+                                                    shadow_row_timer_ready    [i] <= 1'b1;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            if (shadow_row_timer[i] != 0)
+                                                begin
+                                                    shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
+                                                end
+                                            
+                                            if (shadow_row_timer[i] <= 1)
+                                                begin
+                                                    shadow_row_timer_ready[i] <= 1'b1;
+                                                end
+                                            
+                                            if (shadow_row_timer[i] <= 2)
+                                                begin
+                                                    shadow_row_timer_pre_ready[i] <= 1'b1;
+                                                end
+                                        end
+                                end
+                            else
+                                begin
+                                    shadow_row_timer          [i] <= 0;
+                                    shadow_row_timer_pre_ready[i] <= 1'b0;
+                                    shadow_row_timer_ready    [i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Request logic
+    //----------------------------------------------------------------------------------------------------
+    // Can_* logic for request logic, indicate whether TBP can request now
+    // Can activate
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            can_act[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (activated_combi[i]) // activated, so there is no need to enable activate again
+                                begin
+                                    can_act[i] <= 1'b0;
+                                end
+                            else if (col_grant[i]) //done, there is no need to enable activate again
+                                begin
+                                    can_act[i] <= 1'b0;
+                                end
+                            else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
+                                begin
+                                    can_act[i] <= 1'b1;
+                                end
+                            else if
+                                (
+                                    !done[i] && valid[i] &&
+                                    (
+                                        ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && (precharge_tbp[i] || pch_grant[i])) ||
+                                        ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i]                )) ||
+                                        (!cfg_reorder_data && precharge_tbp[i])
+                                    )
+                                )
+                                // precharge or precharge all command, re-enable since it is not done
+                                // (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
+                                begin
+                                    can_act[i] <= 1'b1;
+                                end
+                        end
+                end
+        end
+    
+    // Can precharge
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            can_pch[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
+                        end
+                end
+        end
+    
+    // Can read
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            can_rd[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (col_grant[i] || done[i]) // done, there is no need to enable read again
+                                begin
+                                    can_rd[i] <= 1'b0;
+                                end
+                            else if
+                                (
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && (precharge_tbp[i] || pch_grant[i])) ||
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i]                )) ||
+                                    (!cfg_reorder_data && precharge_tbp[i])
+                                )
+                                // precharge or precharge all command, can't read since bank is not active
+                                // (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
+                                begin
+                                    can_rd[i] <= 1'b0;
+                                end
+                            else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
+                                begin
+                                    can_rd[i] <= 1'b1;
+                                end
+                        end
+                end
+        end
+    
+    // Can write
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            can_wr[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (col_grant[i] || done[i]) // done, there is no need to enable read again
+                                begin
+                                    can_wr[i] <= 1'b0;
+                                end
+                            else if
+                                (
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && (precharge_tbp[i] || pch_grant[i])) ||
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i]                )) ||
+                                    (!cfg_reorder_data && precharge_tbp[i])
+                                )
+                                // precharge or precharge all command, can't write since bank is not active
+                                // (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
+                                begin
+                                    can_wr[i] <= 1'b0;
+                                end
+                            else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
+                                begin
+                                    can_wr[i] <= 1'b1;
+                                end
+                        end
+                end
+        end
+    
+    // Row request
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    row_req[i] = act_req[i] | pch_req[i];
+                end
+        end
+    
+    // Column request
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    col_req[i] = rd_req[i] | wr_req[i];
+                end
+        end
+    
+    // Individual activate, precharge, read and write request logic
+    always @ (*)
+        begin
+            for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                begin
+                    act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
+                    pch_req[i] = require_pch[i] & pch_ready[i]  & can_pch[i];
+                    
+                    rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
+                    wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Valid logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicates that current TBP is valid after load an invalid after flush
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            valid[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (load_tbp[i])
+                                begin
+                                    valid[i] <= 1'b1;
+                                end
+                            else if (flush_tbp[i])
+                                begin
+                                    valid[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // TBP information
+    //----------------------------------------------------------------------------------------------------
+    // Keeps information from cmd_gen after load
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        chipsel    [i] <= 0;
+                        bank       [i] <= 0;
+                        row        [i] <= 0;
+                        col        [i] <= 0;
+                        write      [i] <= 0;
+                        read       [i] <= 0;
+                        size       [i] <= 0;
+                        autopch    [i] <= 0;
+                        localid    [i] <= 0;
+                        dataid     [i] <= 0;
+                        rmw_correct[i] <= 0;
+                        rmw_partial[i] <= 0;
+                        rmw        [i] <= 0;
+                    end
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        if (load_tbp[i])
+                            begin
+                                chipsel    [i] <= cmd_gen_chipsel;
+                                bank       [i] <= cmd_gen_bank;
+                                row        [i] <= cmd_gen_row;
+                                col        [i] <= cmd_gen_col;
+                                write      [i] <= cmd_gen_write;
+                                read       [i] <= cmd_gen_read;
+                                size       [i] <= cmd_gen_size;
+                                autopch    [i] <= cmd_gen_autopch;
+                                localid    [i] <= cmd_gen_localid;
+                                dataid     [i] <= cmd_gen_dataid;
+                                rmw_correct[i] <= cmd_gen_rmw_correct;
+                                rmw_partial[i] <= cmd_gen_rmw_partial;
+                                rmw        [i] <= cmd_gen_rmw_partial | cmd_gen_rmw_correct;
+                            end
+                    end
+        end
+    
+    // Priority information
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        priority_a[i] <=  1'b0;
+                    end
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        if (CFG_DISABLE_PRIORITY == 1)
+                            begin
+                                priority_a[i] <= zero;
+                            end
+                        else
+                            begin
+                                if (load_tbp[i])
+                                    begin
+                                        if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
+                                            begin
+                                                priority_a[i] <= cmd_gen_priority;
+                                            end
+                                        else
+                                            begin
+                                                priority_a[i] <= 1'b0;
+                                            end
+                                    end
+                                else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
+                                    begin
+                                        priority_a[i] <=  1'b1;
+                                    end
+                            end
+                    end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Row dependency vector
+    //----------------------------------------------------------------------------------------------------
+    // RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (load_tbp[i])
+                                begin
+                                    if
+                                        (
+                                            !flush_tbp[j] && !push_tbp[j] &&
+                                            (
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
+                                                (!cfg_reorder_data && valid[j] && same_chip_bank[j])
+                                            )
+                                        )
+                                        // (INTER_ROW)   Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
+                                        // (INTER_ROW)   Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
+                                        //               This is to prevent activate going to the later RMW commands
+                                        // (INTER_BANK)  Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
+                                        // (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
+                                        begin
+                                            rpv_combi[i][j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            rpv_combi[i][j] = 1'b0;
+                                        end
+                                end
+                            else if (flush_tbp[j] || push_tbp[j])
+                                // (INTER_ROW)  Set RPV to '0' after flush
+                                // (INTER_BANK) Set RPV to '0' after flush
+                                begin
+                                    rpv_combi[i][j] = 1'b0;
+                                end
+                            else
+                                begin
+                                    rpv_combi[i][j] = rpv[i][j];
+                                end
+                        end
+                end
+        end
+    
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                        begin
+                            if (CFG_ENABLE_SHADOW_TBP)
+                                begin
+                                    if (load_tbp[i])
+                                        begin
+                                            if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
+                                                // Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
+                                                begin
+                                                    shadow_rpv_combi[i][j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    shadow_rpv_combi[i][j] = 1'b0;
+                                                end
+                                        end
+                                    else if (push_tbp[j] && rpv[i][j])
+                                        // If there is a push_tbp and RPV is set to '1'
+                                        // We need to shift RPV to Shadow RPV
+                                        begin
+                                            shadow_rpv_combi[i][j] = 1'b1;
+                                        end
+                                    else if (flush_shadow_tbp[j])
+                                        // (INTER_ROW)  Set RPV to '0' after flush
+                                        // (INTER_BANK) Set RPV to '0' after flush
+                                        begin
+                                            shadow_rpv_combi[i][j] = 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            shadow_rpv_combi[i][j] = shadow_rpv[i][j];
+                                        end
+                                end
+                            else
+                                begin
+                                    shadow_rpv_combi[i][j] = zero;
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_rpv[i] <= 1'b0;
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    rpv[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
+                                        begin
+                                            rpv[i][j] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            rpv[i][j] <= rpv_combi[i][j];
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    shadow_rpv[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Column dependency vector
+    //----------------------------------------------------------------------------------------------------
+    // CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (load_tbp[i])
+                                begin
+                                    if
+                                        (
+                                            !flush_tbp[j] && !col_grant[j] &&
+                                            (
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank    [j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
+                                                (!cfg_reorder_data && valid[j] && !done[j])
+                                            )
+                                        )
+                                        // (INTER_ROW)   Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
+                                        // (INTER_ROW)   Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
+                                        // (INTER_ROW)   Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
+                                        // (INTER_BANK)  Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
+                                        // (INTER_BANK)  Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
+                                        // (INTER_BANK)  Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
+                                        // (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
+                                        begin
+                                            cpv_combi[i][j] = 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            cpv_combi[i][j] = 1'b0;
+                                        end
+                                end
+                            else if (col_grant[j])
+                                // (INTER_ROW)  Set CPV to '0' after col_grant
+                                // (INTER_BANK) Set CPV to '0' after col_grant
+                                begin
+                                    cpv_combi[i][j] = 1'b0;
+                                end
+                            else
+                                begin
+                                    cpv_combi[i][j] = cpv[i][j];
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_cpv[i] <= 1'b0;
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    cpv[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_cpv[i] <= ~|cpv_combi[i];
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (i == j)  // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
+                                        begin
+                                            cpv[i][j] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            cpv[i][j] <= cpv_combi[i][j];
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Activate related logic
+    //----------------------------------------------------------------------------------------------------
+    // Open-row-pass flush logic
+    // after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
+    // after a done command and WST (open row pass to another TBP with same page from a done command with page open)
+    
+    // Logic to determine which not-done TBP should be flushed to perform open-row-pass
+    always @ (*)
+        begin
+            not_done_tbp_row_pass_flush = col_grant & wst_p;
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            not_done_tbp_row_pass_flush_r[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
+                        end
+                end
+        end
+    
+    // Logic to determine which done TBP should be flushed to perform open-row-pass
+    always @ (*)
+        begin
+            done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            done_tbp_row_pass_flush_r[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (done_tbp_row_pass_flush_r[i])
+                                begin
+                                    done_tbp_row_pass_flush_r[i] <= 1'b0;
+                                end
+                            else
+                                begin
+                                    done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
+                                end
+                        end
+                end
+        end
+    
+    // Using done_tbp_row_pass_flush_r to improve timing
+    // it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
+    // [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
+    assign  open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
+    
+    // Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
+                end
+        end
+    
+    // Open-row-passed logic, keep signal high once there is a open-row-pass to current TBP
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            open_row_passed[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (open_row_pass[i])
+                                begin
+                                    open_row_passed[i] <= 1'b1;
+                                end
+                            else if (flush_tbp[i])
+                                begin
+                                    open_row_passed[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    // Registered version
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            open_row_pass_r      [i] <= 1'b0;
+                            open_row_pass_flush_r[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            open_row_pass_r      [i] <= open_row_pass      [i];
+                            open_row_pass_flush_r[i] <= open_row_pass_flush[i];
+                        end
+                end
+        end
+    
+    // Activated logic
+    // indicate that current TBP is activated by activate command or open-row-pass
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (act_grant[i] || open_row_pass[i])
+                        begin
+                            activated_combi[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            activated_combi[i] = 1'b0;
+                        end
+                end
+        end
+    
+    // activated need not to be validated with valid
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            activated  [i] <= 1'b0;
+                            activated_p[i] <= 1'b0;
+                        end
+                end
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        activated_p[i] <= activated_combi[i]; // activated pulse
+                        
+                        if (flush_tbp[i] || pch_grant[i])
+                            begin
+                                activated[i] <= 1'b0;
+                            end
+                        else if (precharge_tbp[i])
+                            begin
+                                activated[i] <= 1'b0;
+                            end
+                        else if (activated_combi[i])
+                            begin
+                                activated[i] <= 1'b1;
+                            end
+                    end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Precharge related logic
+    //----------------------------------------------------------------------------------------------------
+    // Precharge all logic
+    // indicate which TBP is precharged cause of sideband precharge all command
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    precharge_tbp[i] = sb_tbp_precharge_all[i];
+                end
+        end
+    
+    // Precharge logic
+    // indicate which TBP is precharged
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (load_tbp[i])
+                        begin
+                            precharged_combi[i] = 1'b0;
+                        end
+                    else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
+                        // Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
+                        // due to TBP interlock case
+                        begin
+                            precharged_combi[i] = 1'b0;
+                        end
+                    else if (col_grant[i] && real_ap[i])
+                        begin
+                            precharged_combi[i] = 1'b1;
+                        end
+                    else if (pch_grant[i])
+                        begin
+                            precharged_combi[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            precharged_combi[i] = precharged[i];
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            precharged[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            precharged[i] <= precharged_combi[i];
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Auto-precharge related logic
+    //----------------------------------------------------------------------------------------------------
+    // Auto precharge related logic, to determine which TBP should be closed or kept open
+    // OPP - autoprecharge when there is another command to same chip-bank different row
+    // CPP - do not autoprecharge when there is another command to the same chip-bank-row
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (flush_tbp[i])
+                        begin
+                            apvo_combi[i] = 1'b0;
+                            apvc_combi[i] = 1'b0;
+                        end
+                    else if
+                        (
+                            (load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
+                            (
+                                (|load_tbp && !load_tbp[i]) && // load other TBP
+                                (
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
+                                    (!cfg_reorder_data && !ssb[i])
+                                )
+                            )
+                        )
+                        // (INTER_ROW)   update multiple times whenever there is a load so that it'll get the latest AP info
+                        // (INTER_BANK)  only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
+                        // (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
+                        begin
+                            if
+                                (
+                                    (load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
+                                    ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
+                                )
+                                // (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
+                                // set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
+                                begin
+                                    apvo_combi[i] = 1'b1;
+                                end
+                            else
+                                begin
+                                    apvo_combi[i] = apvo[i];
+                                end
+                            
+                            if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
+                                // set to '1' if there is a new command with same-chip-bank-row with current TBP
+                                begin
+                                    apvc_combi[i] = 1'b1;
+                                end
+                            else
+                                begin
+                                    apvc_combi[i] = apvc[i];
+                                end
+                        end
+                    else
+                        begin
+                            apvo_combi[i] = apvo[i];
+                            apvc_combi[i] = apvc[i];
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            apvo[i] <= 1'b0;
+                            apvc[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            apvo[i] <= apvo_combi[i];
+                            apvc[i] <= apvc_combi[i];
+                        end
+                end
+        end
+    
+    // Auto precharge
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
+                        begin
+                            ap[i] = 1'b0;
+                        end
+                    else if (apvo[i])
+                        begin
+                            ap[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            ap[i] = autopch[i] | require_flush[i];
+                        end
+                end
+        end
+    
+    // Real auto-precharge
+    // purpose is to make pipelining easier in the future (if needed)
+    always @ (*)
+    begin
+        real_ap = ap;
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Done logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate that current TBP has finished issuing column command
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (load_tbp[i])
+                        begin
+                            done_combi[i] = 1'b0;
+                        end
+                    else if (flush_tbp[i])
+                        begin
+                            done_combi[i] = 1'b0;
+                        end
+                    else if (col_grant[i])
+                        begin
+                            done_combi[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            done_combi[i] = done[i];
+                        end
+                end
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            done[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            done[i] <= done_combi[i];
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Complete logic
+    //----------------------------------------------------------------------------------------------------
+    reg  [CFG_CTL_TBP_NUM-1:0] partial_vector_combi [CFG_CTL_TBP_NUM-1:0];
+    reg  [CFG_CTL_TBP_NUM-1:0] partial_vector       [CFG_CTL_TBP_NUM-1:0];
+    reg  [CFG_CTL_TBP_NUM-1:0] load_rmw_data;
+    reg  [CFG_CTL_TBP_NUM-1:0] all_complete_vector;
+    reg                        all_complete;
+    
+    wire                       data_rmw_fetch = data_rmw_complete && !all_complete;
+    
+    // Partial information, to indicate which partial command should receive the current data_rmw_complete
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (i == j)
+                                begin
+                                    partial_vector_combi[i][j] = zero;
+                                end
+                            else
+                                begin
+                                    if (load_tbp[i] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct) && cmd_gen_write) // only required for partial write commands
+                                        begin
+                                            if (!done[j] && valid[j] && rmw[j] && write[j] && !load_rmw_data[j] && !complete_wr[j]) // compare with current valid and not done RMW commands
+                                                begin
+                                                    partial_vector_combi[i][j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    partial_vector_combi[i][j] = 1'b0;
+                                                end
+                                        end
+                                    else if (load_rmw_data[j])
+                                        begin
+                                            partial_vector_combi[i][j] = 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            partial_vector_combi[i][j] = partial_vector[i][j];
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    partial_vector[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    partial_vector[i][j] <= partial_vector_combi[i][j];
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            load_rmw_data[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (~|partial_vector_combi[i] && data_rmw_complete)
+                                begin
+                                    load_rmw_data[i] <= 1'b1;
+                                end
+                            else
+                                begin
+                                    load_rmw_data[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    // Indicate that the data for current TBP is complete and ready to be issued
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (load_tbp[i])
+                        begin
+                            if (cmd_gen_read)
+                                begin
+                                    complete_combi_rd[i] =  cmd_gen_complete;
+                                    complete_combi_wr[i] =  1'b0;
+                                end
+                            else
+                                begin
+                                    complete_combi_rd[i] =  1'b0;
+                                    complete_combi_wr[i] =  cmd_gen_complete;
+                                end
+                        end
+                    else if (write[i] && !complete[i])
+                        begin
+                            complete_combi_rd[i] =  complete_rd[i];
+                            
+                            if (cfg_enable_rmw)
+                                begin
+                                    complete_combi_wr[i] =  load_rmw_data[i];
+                                end
+                            else
+                                begin
+                                    complete_combi_wr[i] =  data_complete[i];
+                                end
+                        end
+                    else
+                        begin
+                            complete_combi_rd[i] = complete_rd[i];
+                            complete_combi_wr[i] = complete_wr[i];
+                        end
+                end
+        end
+    
+    always @ (*)
+        begin
+            complete_combi = complete_combi_rd | complete_combi_wr;
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    complete    <=  0;
+                    complete_rd <=  0;
+                    complete_wr <=  0;
+                end
+            else
+                begin
+                    complete    <=  complete_combi;
+                    complete_rd <=  complete_combi_rd;
+                    complete_wr <=  complete_combi_wr;
+                end
+        end
+    
+    // To indicate that all TBP has completed, expect non-valid TBP
+    always @ (*)
+        begin
+            all_complete = &all_complete_vector;
+            
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (!valid[i])
+                        begin
+                            all_complete_vector[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            all_complete_vector[i] = complete[i];
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Same bank vector logic
+    //----------------------------------------------------------------------------------------------------
+    // This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
+    // SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
+    // prevents activate to and activated bank
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
+                                begin
+                                    // There is no need to SBV in INTER_BANK case
+                                    sbv_combi[i][j] = zero;
+                                end
+                            else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
+                                begin
+                                    if
+                                        (
+                                            (load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
+                                            (activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
+                                        )
+                                        // Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
+                                        // Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
+                                        begin
+                                            sbv_combi[i][j] = 1'b1;
+                                        end
+                                    else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
+                                        // Set SBV to '0' if there is a flush to other TBP
+                                        // Set SBV to '0' if there is a precharge to other TBP
+                                        // Set SBV to '0' if there is a precharge all command from sideband
+                                        begin
+                                            sbv_combi[i][j] = 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            sbv_combi[i][j] = sbv[i][j];
+                                        end
+                                end
+                            else
+                                begin
+                                    sbv_combi[i][j] = sbv[i][j];
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_sbv[i] <= 1'b0;
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    sbv[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_sbv[i] <= ~|sbv_combi[i];
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
+                                        begin
+                                            sbv[i][j] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            sbv[i][j] <= sbv_combi[i][j];
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Same bank timer vector logic
+    //----------------------------------------------------------------------------------------------------
+    // SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
+                                begin
+                                    sbvt_combi[i][j] = zero;
+                                end
+                            else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
+                                begin
+                                    if (flush_tbp[i])
+                                        begin
+                                            sbvt_combi[i][j] = 1'b0;
+                                        end
+                                    else if (push_tbp[j])
+                                        begin
+                                            sbvt_combi[i][j] = 1'b0;
+                                        end
+                                    else if
+                                        (
+                                            (pch_grant[j] || (col_grant[j] && real_ap[j])) &&
+                                            (
+                                                (load_tbp[i] && same_chip_bank[j]) ||
+                                                (valid[i] && pre_calculated_same_chip_bank[i][j])
+                                            )
+                                        )
+                                        // Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
+                                        begin
+                                            sbvt_combi[i][j] = 1'b1;
+                                        end
+                                    else if
+                                        (
+                                             precharged[j] && valid[j] &&
+                                            (
+                                                (load_tbp[i] && same_chip_bank[j]) ||
+                                                (valid[i] && pre_calculated_same_chip_bank[i][j])
+                                            )
+                                        )
+                                        // Set to '1' when same-chip-bank address TBP is still in precharge state
+                                        begin
+                                            sbvt_combi[i][j] = ~row_timer_pre_ready[j];
+                                        end
+                                    else
+                                        begin
+                                            sbvt_combi[i][j] = zero;
+                                        end
+                                end
+                            else
+                                begin
+                                    sbvt_combi[i][j] = sbvt[i][j];
+                                end
+                        end
+                end
+        end
+    
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                        begin
+                            if (CFG_ENABLE_SHADOW_TBP)
+                                begin
+                                    if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
+                                        begin
+                                            shadow_sbvt_combi[i][j] = zero;
+                                        end
+                                    else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
+                                        begin
+                                            if (flush_shadow_tbp[j])
+                                                begin
+                                                    shadow_sbvt_combi[i][j] = 1'b0;
+                                                end
+                                            else if (push_tbp[j] && sbvt[i][j])
+                                                begin
+                                                    shadow_sbvt_combi[i][j] = 1'b1;
+                                                end
+                                            else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
+                                                // Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
+                                                begin
+                                                    shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
+                                                end
+                                            else
+                                                begin
+                                                    shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            shadow_sbvt_combi[i][j] = zero;
+                                        end
+                                end
+                            else
+                                begin
+                                    shadow_sbvt_combi[i][j] = zero;
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+			    nor_sbvt[i] <= 1'b0;
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    sbvt[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
+                            
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
+                                        begin
+                                            sbvt[i][j] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            sbvt[i][j] <= sbvt_combi[i][j];
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    shadow_sbvt[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Seen same bank logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate that it sees a new TBP which is same-chip-bank with current TBP
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            ssb[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (flush_tbp[i])
+                                        begin
+                                            ssb[i] <= 1'b0;
+                                        end
+                                    else if (load_tbp[j] && valid[i] && same_chip_bank[i])
+                                        begin
+                                            ssb[i] <= 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Seen same bank row logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            ssbr[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (flush_tbp[i])
+                                        begin
+                                            ssbr[i] <= 1'b0;
+                                        end
+                                    else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
+                                        begin
+                                            ssbr[i] <= 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Will send transfer logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate that it will pass current TBP information (timing/page) over to other TBP
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            wst_p[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (load_tbp[i]) // Reset back to '0'
+                                        begin
+                                            wst_p[i] <= 1'b0;
+                                        end
+                                    else if
+                                        (
+                                            ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && precharged_combi[i] && done_combi[i]) ||
+                                            ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i]                 ) ||
+                                            (!cfg_reorder_data && precharged_combi[i])
+                                        )
+                                        // Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
+                                        // (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
+                                        //               to make sure we're able to open-row-pass a not-done precharged command
+                                        begin
+                                            wst_p[i] <= 1'b0;
+                                        end
+                                    else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
+                                        begin
+                                            wst_p[i] <= 1'b0;
+                                        end
+                                    else if
+                                        (
+                                            load_tbp[j] && same_chip_bank_row[i] &&
+                                            (
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
+                                                ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i]                 )) ||
+                                                (!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
+                                            )
+                                        )
+                                        // Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
+                                        // make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
+                                        // (INTER_ROW)   included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
+                                        //               to make sure we're able to open-row-pass a not-done precharged command
+                                        // (INTER_BANK)  make sure SSB is not set (only set WST once)
+                                        // (NON_REORDER) make sure SSB is not set (only set WST once)
+                                        begin
+                                            wst_p[i] <= 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Will receive transfer logic
+    //----------------------------------------------------------------------------------------------------
+    // Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
+    always @ (*)
+    begin
+        for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+            begin
+                for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                    begin
+                        if
+                            (
+                                load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
+                                (
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW"  && !ssbr[j]) ||
+                                    ( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
+                                    (!cfg_reorder_data && !ssb[j])
+                                )
+                            )
+                            // Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
+                            // provided other TBP is valid and not precharged
+                            // (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
+                            begin
+                                wrt_combi[i][j] = 1'b1;
+                            end
+                        else if (flush_tbp[j])
+                            begin
+                                wrt_combi[i][j] = 1'b0;
+                            end
+                        else
+                            begin
+                                wrt_combi[i][j] = wrt[i][j];
+                            end
+                    end
+            end
+    end
+ 
+    always @ (*)
+    begin
+        for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+            begin
+               or_wrt [i] =  |wrt[i];	
+            end
+    end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                        begin
+                            wrt    [i] <= 0;
+                        end
+                end
+            else
+                begin
+                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                        begin
+                            for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
+                                begin
+                                    if (i == j)
+                                        wrt[i][j] <= 1'b0;
+                                    else
+                                        wrt[i][j] <= wrt_combi[i][j];
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Require flush logic
+    //----------------------------------------------------------------------------------------------------
+    // On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
+    // if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            require_flush[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (CFG_CTL_TBP_NUM == 1)
+                                begin
+                                    require_flush[i] <= cmd_gen_load | cmd_gen_waiting_to_load;
+                                end
+                            else
+                                begin
+                                    if (|flush_tbp) // tbp will not be full on the next clock cycle
+                                        begin
+                                            require_flush[i] <= 1'b0;
+                                        end
+                                    else if (int_tbp_full && (cmd_gen_load | cmd_gen_waiting_to_load))
+                                        begin
+                                            if (same_chip_bank_row[i])
+                                                require_flush[i] <= 1'b0;
+                                            else
+                                                require_flush[i] <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            require_flush[i] <= 1'b0;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Require precharge logic
+    //----------------------------------------------------------------------------------------------------
+    // Precharge request logic, to clear up lockup state in TBP
+    always @(*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                        begin
+                            if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
+                                begin
+                                    require_pch_combi[i][j] = zero;
+                                end
+                            else
+                                begin
+                                    if (i == j)
+                                        begin
+                                            require_pch_combi[i][j] = 1'b0;
+                                        end
+                                    else if (activated[i] && !done[i])
+                                        begin
+                                            if (cpv[i][j] && sbv[j][i])
+                                                begin
+                                                    require_pch_combi[i][j] = 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    require_pch_combi[i][j] = 1'b0;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            require_pch_combi[i][j] = 1'b0;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            require_pch[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (flush_tbp[i])
+                                begin
+                                    require_pch[i] <= 1'b0;
+                                end
+                            else
+                                begin
+                                    // included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
+                                    require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
+                                end
+                        end
+                end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Address/command comparison logic
+    //----------------------------------------------------------------------------------------------------
+    // Command comparator
+    always @ (*)
+        begin
+            if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
+                begin
+                    same_command_read = cmd_gen_same_read_cmd;
+                end
+            else
+                begin
+                    same_command_read = {CFG_CTL_TBP_NUM{zero}};
+                end
+        end
+    
+    always @ (*)
+        begin
+            same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
+        end
+    
+    // Address comparator
+    always @(*)
+        begin
+            same_chip_bank          = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
+            same_chip_bank_row      = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr &  cmd_gen_same_row_addr;
+            same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
+        end
+    
+    always @ (*)
+        begin
+            same_shadow_chip_bank          = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
+            same_shadow_chip_bank_row      = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr &  cmd_gen_same_shadow_row_addr;
+            same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
+        end
+    
+    // Registered version, to improve fMAX
+    generate
+        begin
+            genvar i_tbp;
+            genvar j_tbp;
+            for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
+                begin : i_compare_loop
+                    for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
+                        begin : j_compare_loop
+                            always @ (posedge ctl_clk or negedge ctl_reset_n)
+                                begin
+                                    if (!ctl_reset_n)
+                                        begin
+                                            pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
+                                            pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b0;
+                                            pre_calculated_same_chip_bank          [i_tbp][j_tbp] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            if (load_tbp [i_tbp])
+                                                begin
+                                                    pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
+                                                    pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= same_chip_bank_row      [j_tbp];
+                                                    pre_calculated_same_chip_bank          [i_tbp][j_tbp] <= same_chip_bank          [j_tbp];
+                                                end
+                                            else if (load_tbp [j_tbp])
+                                                begin
+                                                    if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
+                                                        pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
+                                                    else
+                                                        pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
+                                                    
+                                                    if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
+                                                        pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b1;
+                                                    else
+                                                        pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b0;
+                                                    
+                                                    if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
+                                                        pre_calculated_same_chip_bank          [i_tbp][j_tbp] <= 1'b1;
+                                                    else
+                                                        pre_calculated_same_chip_bank          [i_tbp][j_tbp] <= 1'b0;
+                                                end
+                                            else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
+                                                begin
+                                                    if (row [i_tbp] != row [j_tbp])
+                                                        begin
+                                                            pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
+                                                            pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b0;
+                                                        end
+                                                    else
+                                                        begin
+                                                            pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
+                                                            pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b1;
+                                                        end
+                                                    
+                                                    pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
+                                                    pre_calculated_same_chip_bank_row      [i_tbp][j_tbp] <= 1'b0;
+                                                    pre_calculated_same_chip_bank          [i_tbp][j_tbp] <= 1'b0;
+                                                end
+                                        end
+                                end
+                        end
+                end
+                
+                for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
+                begin : i_compare_loop_shadow
+                    for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
+                        begin : j_compare_loop_shadow
+                            always @ (posedge ctl_clk or negedge ctl_reset_n)
+                                begin
+                                    if (!ctl_reset_n)
+                                        begin
+                                            pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
+                                        end
+                                    else
+                                        begin
+                                            if (load_tbp [i_tbp])
+                                                begin
+                                                    if (push_tbp [j_tbp])
+                                                        pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank        [j_tbp];
+                                                    else
+                                                        pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
+                                                end
+                                            else if (push_tbp [j_tbp])
+                                                begin
+                                                    if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
+                                                        pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
+                                                    else
+                                                        pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
+                                                end
+                                            else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
+                                                begin
+                                                    pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
+                                                end
+                                        end
+                                end
+                        end
+                end
+        end
+    endgenerate
+    
+    //----------------------------------------------------------------------------------------------------
+    // Bank specific timer related logic
+    //----------------------------------------------------------------------------------------------------
+    // Offset timing paramter to achieve accurate timing gap between commands
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    compare_t_param_act_to_rdwr_less_than_offset    <= 0;
+                    compare_t_param_act_to_act_less_than_offset     <= 0;
+                    compare_t_param_act_to_pch_less_than_offset     <= 0;
+                    compare_t_param_rd_to_pch_less_than_offset      <= 0;
+                    compare_t_param_wr_to_pch_less_than_offset      <= 0;
+                    compare_t_param_pch_to_valid_less_than_offset   <= 0;
+                    compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
+                    compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
+                    
+                    compare_offset_t_param_act_to_rdwr_less_than_0  <= 0;
+                    compare_offset_t_param_act_to_rdwr_less_than_1  <= 0;
+                end
+            else
+                begin
+                    if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_act_to_act > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_act_to_act_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_act_to_act_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_act_to_pch_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_act_to_pch_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
+                        begin
+                            compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
+                        end
+                    else
+                        begin
+                            compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
+                        end
+                    
+                    if (offset_t_param_act_to_rdwr <= 0)
+                        begin
+                            compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
+                        end
+                    else
+                        begin
+                            compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
+                        end
+                    
+                    if (offset_t_param_act_to_rdwr <= 1)
+                        begin
+                            compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
+                        end
+                    else
+                        begin
+                            compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    offset_t_param_act_to_rdwr    <= 0;
+                    offset_t_param_act_to_act     <= 0;
+                    offset_t_param_act_to_pch     <= 0;
+                    offset_t_param_rd_to_pch      <= 0;
+                    offset_t_param_wr_to_pch      <= 0;
+                    offset_t_param_pch_to_valid   <= 0;
+                    offset_t_param_rd_ap_to_valid <= 0;
+                    offset_t_param_wr_ap_to_valid <= 0;
+                end
+            else
+                begin
+                    if (!compare_t_param_act_to_rdwr_less_than_offset)
+                        begin
+                            offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_act_to_rdwr <= 0;
+                        end
+                    
+                    if (!compare_t_param_act_to_act_less_than_offset)
+                        begin
+                            offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_act_to_act <= 0;
+                        end
+                    
+                    if (!compare_t_param_act_to_pch_less_than_offset)
+                        begin
+                            offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_act_to_pch <= 0;
+                        end
+                    
+                    if (!compare_t_param_rd_to_pch_less_than_offset)
+                        begin
+                            offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_rd_to_pch <= 0;
+                        end
+                    
+                    if (!compare_t_param_wr_to_pch_less_than_offset)
+                        begin
+                            offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_wr_to_pch <= 0;
+                        end
+                    
+                    if (!compare_t_param_pch_to_valid_less_than_offset)
+                        begin
+                            offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_pch_to_valid <= 0;
+                        end
+                    
+                    if (!compare_t_param_rd_ap_to_valid_less_than_offset)
+                        begin
+                            offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_rd_ap_to_valid <= 0;
+                        end
+                    
+                    if (!compare_t_param_wr_ap_to_valid_less_than_offset)
+                        begin
+                            offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
+                        end
+                    else
+                        begin
+                            offset_t_param_wr_ap_to_valid <= 0;
+                        end
+                end
+        end
+    
+    // Pre-calculated logic to improve timing, for row_timer and trc_timer
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            compare_t_param_rd_to_pch_greater_than_row_timer     [i] <= 1'b0;
+                            compare_t_param_wr_to_pch_greater_than_row_timer     [i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
+                                begin
+                                    compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
+                                end
+                            else
+                                begin
+                                    compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
+                                end
+                            
+                            if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
+                                begin
+                                    compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
+                                end
+                            else
+                                begin
+                                    compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    // Column timer logic
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        col_timer          [i] <= 0;
+                        col_timer_ready    [i] <= 1'b0;
+                        col_timer_pre_ready[i] <= 1'b0;
+                    end
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        if (row_grant[i])
+                            begin
+                                if (compare_t_param_act_to_rdwr_less_than_offset)
+                                    begin
+                                        col_timer          [i] <= 0;
+                                        col_timer_ready    [i] <= 1'b1;
+                                        col_timer_pre_ready[i] <= 1'b1;
+                                    end
+                                else
+                                    begin
+                                        col_timer          [i] <= offset_t_param_act_to_rdwr;
+                                        
+                                        if (compare_offset_t_param_act_to_rdwr_less_than_0)
+                                            begin
+                                                col_timer_ready    [i] <= 1'b1;
+                                            end
+                                        else
+                                            begin
+                                                col_timer_ready    [i] <= 1'b0;
+                                            end
+                                        
+                                        if (compare_offset_t_param_act_to_rdwr_less_than_1)
+                                            begin
+                                                col_timer_pre_ready[i] <= 1'b1;
+                                            end
+                                        else
+                                            begin
+                                                col_timer_pre_ready[i] <= 1'b0;
+                                            end
+                                    end
+                            end
+                        else
+                            begin
+                                if (col_timer[i] != 0)
+                                    begin
+                                        col_timer[i] <= col_timer[i] - 1'b1;
+                                    end
+                                
+                                if (col_timer[i] <= 1)
+                                    begin
+                                        col_timer_ready[i] <= 1'b1;
+                                    end
+                                else
+                                    begin
+                                        col_timer_ready[i] <= 1'b0;
+                                    end
+                                
+                                if (col_timer[i] <= 2)
+                                    begin
+                                        col_timer_pre_ready[i] <= 1'b1;
+                                    end
+                                else
+                                    begin
+                                        col_timer_pre_ready[i] <= 1'b0;
+                                    end
+                            end
+                    end
+        end
+    
+    // log2 result of open-row-pass-flush, to be used during timer information pass
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
+                end
+        end
+    
+    // Registered version
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            log2_open_row_pass_flush_r[i] <= 0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
+                        end
+                end
+        end
+    
+    // Combined timer logic
+    // compare between row_timer and trc_timer and take the largest value
+    // to be used in open_row_pass only
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            combined_timer[i] <= 0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (CFG_REG_GRANT == 0 && open_row_pass_r[i]) // for QR controller only
+                                begin
+                                    if (col_grant[i])
+                                        begin
+                                            if (row_timer_combi[i] > combined_timer[log2_open_row_pass_flush_r[i]])
+                                                begin
+                                                    combined_timer[i] <= row_timer_combi[i];
+                                                end
+                                            else
+                                                begin
+                                                    combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
+                                        end
+                                end
+                            else
+                                begin
+                                    if (row_timer_combi[i] > trc_timer[i])
+                                        begin
+                                            combined_timer[i] <= row_timer_combi[i];
+                                        end
+                                    else
+                                        begin
+                                            combined_timer[i] <= (trc_timer[i] > 1'b1) ? (trc_timer[i] - 1'b1) : 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    // Row timer logic
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                begin
+                    if (trc_timer[i] <= 1)
+                        begin
+                            trc_timer_pre_ready_combi[i] = 1'b1;
+                        end
+                    else
+                        begin
+                            trc_timer_pre_ready_combi[i] = 1'b0;
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            trc_timer          [i] <= 0;
+                            trc_timer_ready    [i] <= 1'b0;
+                            trc_timer_pre_ready[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            // Reset row_timer after push
+                            if (push_tbp[i])
+                                begin
+                                    trc_timer          [i] <= 0;
+                                    trc_timer_ready    [i] <= 1'b1;
+                                    trc_timer_pre_ready[i] <= 1'b1;
+                                end
+                            // We need to update the timer as soon as possible when CFG_REG_GRANT == 0
+                            // because after open-row-pass, row grant can happen on the next clock cycle
+                            else if (CFG_REG_GRANT == 0 && open_row_pass[i])
+                                begin
+                                    trc_timer_ready    [i] <= 1'b0;
+                                    trc_timer_pre_ready[i] <= 1'b0;
+                                end
+                            else if
+                                (open_row_pass_r[i])
+                                begin
+                                    trc_timer          [i] <= combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
+                                    trc_timer_ready    [i] <= 1'b0;
+                                    trc_timer_pre_ready[i] <= 1'b0;
+                                end
+                            else if (act_grant[i])
+                                begin
+                                    trc_timer          [i] <= offset_t_param_act_to_act;
+                                    trc_timer_ready    [i] <= 1'b0;
+                                    trc_timer_pre_ready[i] <= 1'b0;
+                                end
+                            else
+                                begin
+                                    if (trc_timer[i] != 0)
+                                        begin
+                                            trc_timer[i] <= trc_timer[i] - 1'b1;
+                                        end
+                                    
+                                    if (trc_timer[i] <= 1)
+                                        begin
+                                            trc_timer_ready[i] <= 1'b1;
+                                        end
+                                    
+                                    if (trc_timer[i] <= 2)
+                                        begin
+                                            trc_timer_pre_ready[i] <= 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (*)
+        begin
+            for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+            begin
+                if (rd_grant[i])
+                    begin
+                        if (real_ap[i])
+                            begin
+                                row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
+                            end
+                        else
+                            begin
+                                if
+                                    (
+                                        (CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
+                                        (CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
+                                    )
+                                    begin
+                                        row_timer_combi[i] = offset_t_param_rd_to_pch;
+                                    end
+                                else
+                                    begin
+                                        row_timer_combi[i] = row_timer[i] - 1'b1;
+                                    end
+                            end
+                    end
+                else if (wr_grant[i])
+                    begin
+                        if (real_ap[i])
+                            begin
+                                row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
+                            end
+                        else
+                            begin
+                                if
+                                    (
+                                        (CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
+                                        (CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
+                                    )
+                                    begin
+                                        row_timer_combi[i] = offset_t_param_wr_to_pch;
+                                    end
+                                else
+                                    begin
+                                        row_timer_combi[i] = row_timer[i] - 1'b1;
+                                    end
+                            end
+                    end
+                else
+                    begin
+                        if (row_timer[i] != 0)
+                            begin
+                                row_timer_combi[i] = row_timer[i] - 1'b1;
+                            end
+                        else
+                            begin
+                                row_timer_combi[i] = 0;
+                            end
+                    end
+            end
+        end
+    
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            row_timer          [i] <= 0;
+                            row_timer_ready    [i] <= 1'b0;
+                            row_timer_pre_ready[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            // Reset row_timer after push
+                            if (push_tbp[i])
+                                begin
+                                    row_timer          [i] <= 0;
+                                    row_timer_ready    [i] <= 1'b1;
+                                    row_timer_pre_ready[i] <= 1'b1;
+                                end
+                            else if (act_grant[i])
+                                begin
+                                    if (compare_t_param_act_to_pch_less_than_offset)
+                                        begin
+                                            row_timer          [i] <= 0;
+                                            row_timer_ready    [i] <= 1'b1;
+                                            row_timer_pre_ready[i] <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            // Load tRAS after precharge command
+                                            row_timer          [i] <= offset_t_param_act_to_pch;
+                                            row_timer_ready    [i] <= 1'b0;
+                                            row_timer_pre_ready[i] <= 1'b0;
+                                        end
+                                end
+                            else if (pch_grant[i])
+                                begin
+                                    if (compare_t_param_pch_to_valid_less_than_offset)
+                                        begin
+                                            row_timer          [i] <= 0;
+                                            row_timer_ready    [i] <= 1'b1;
+                                            row_timer_pre_ready[i] <= 1'b1;
+                                        end
+                                    else
+                                        begin
+                                            // Load tRP after precharge command
+                                            row_timer          [i] <= offset_t_param_pch_to_valid;
+                                            row_timer_ready    [i] <= 1'b0;
+                                            row_timer_pre_ready[i] <= 1'b0;
+                                        end
+                                end
+                            else if (col_grant[i])
+                                begin
+                                     row_timer          [i] <= row_timer_combi[i];
+                                     row_timer_ready    [i] <= 1'b0;
+                                     row_timer_pre_ready[i] <= 1'b0;
+                                end
+                            else
+                                begin
+                                    if (row_timer[i] != 0)
+                                        begin
+                                            row_timer[i] <= row_timer[i] - 1'b1;
+                                        end
+                                    
+                                    if (row_timer[i] <= 1)
+                                        begin
+                                            row_timer_ready[i] <= 1'b1;
+                                        end
+                                    
+                                    if (row_timer[i] <= 2)
+                                        begin
+                                            row_timer_pre_ready[i] <= 1'b1;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    // Logic to let precharge request logic that it is ready to request now
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            pch_ready[i] <= 1'b0;
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                        begin
+                            if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
+                                // disable pch_ready after open-row-pass and grant
+                                // since precharge is not needed immediately after TBP is loaded
+                                begin
+                                    pch_ready[i] <= 1'b0;
+                                end
+                            else if (row_timer_pre_ready[i] && ((trc_timer_pre_ready[i] && open_row_passed[i]) || !open_row_passed[i]) && !precharged[i])
+                                // disable pch_ready if current TBP is precharged
+                                // only compare with trc_timer if TBP is an open_row_pass command
+                                begin
+                                    pch_ready[i] <= 1'b1;
+                                end
+                            else
+                                begin
+                                    pch_ready[i] <= 1'b0;
+                                end
+                        end
+                end
+        end
+    
+    // Logic to let sideband know which chip contains active banks
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    int_bank_closed[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (chipsel[j] == i && valid[j])
+                                        begin
+                                            if (sb_tbp_precharge_all[j])
+                                                begin
+                                                    int_bank_closed[i][j] <= 1'b1;
+                                                end
+                                            else if (precharged_combi[j])
+                                                begin
+                                                    int_bank_closed[i][j] <= 1'b1;
+                                                end
+                                            else if (activated_combi[j])
+                                                begin
+                                                    int_bank_closed[i][j] <= 1'b0;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            int_bank_closed[i][j] <= 1'b1; // else default to '0'
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    // Logic to let sideband know which chip contains running timer
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    int_timer_ready[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                                begin
+                                    if (chipsel[j] == i)
+                                        begin
+                                            if (col_grant[j] || row_grant[j])
+                                                begin
+                                                    int_timer_ready[i][j] <= 1'b0;
+                                                end
+                                            else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
+                                                begin
+                                                    int_timer_ready[i][j] <= 1'b1;
+                                                end
+                                            else
+                                                begin
+                                                    int_timer_ready[i][j] <= 1'b0;
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            int_timer_ready[i][j] <= 1'b1; // else default to '1'
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    int_shadow_timer_ready[i][j] <= 1'b0;
+                                end
+                        end
+                end
+            else
+                begin
+                    for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+                        begin
+                            for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
+                                begin
+                                    if (CFG_ENABLE_SHADOW_TBP)
+                                        begin
+                                            if (shadow_chipsel[j] == i)
+                                                begin
+                                                    if (push_tbp[j])
+                                                        begin
+                                                            int_shadow_timer_ready[i][j] <= 1'b0;
+                                                        end
+                                                    else if (shadow_row_timer_pre_ready[j])
+                                                        begin
+                                                            int_shadow_timer_ready[i][j] <= 1'b1;
+                                                        end
+                                                    else
+                                                        begin
+                                                            int_shadow_timer_ready[i][j] <= 1'b0;
+                                                        end
+                                                end
+                                            else
+                                                begin
+                                                    int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
+                                                end
+                                        end
+                                    else
+                                        begin
+                                            int_shadow_timer_ready[i][j] <= one;
+                                        end
+                                end
+                        end
+                end
+        end
+    
+    always @ (*)
+    begin
+        for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
+            begin
+                bank_closed[i] = &int_bank_closed[i];
+                timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
+            end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Age logic
+    //----------------------------------------------------------------------------------------------------
+    // To tell the current age of each TBP entry
+    // so that arbiter will be able to grant the oldest entry (if there is a tie-break)
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    age[i]  <=  0;
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
+                            begin
+                                if (i == j)
+                                    begin
+                                        age[i][j]  <=  1'b0;
+                                    end
+                                else
+                                    begin
+                                        if (load_tbp[i])
+                                            if (!flush_tbp[j] && (valid[j]))
+                                                age[i][j]  <=  1'b1;
+                                            else
+                                                age[i][j]  <=  1'b0;
+                                        else if (flush_tbp[j])
+                                            age[i][j]  <=  1'b0;
+                                    end
+                            end
+                    end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Starvation logic
+    //----------------------------------------------------------------------------------------------------
+    // Logic will increments when there is a col_grant to other TBP
+    // will cause priority to be asserted when the count reaches starvation threshold
+    always @(posedge ctl_clk, negedge ctl_reset_n)
+        begin
+            if (!ctl_reset_n)
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    starvation[i]   <=  0;
+            else
+                for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
+                    begin
+                        if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
+                            starvation[i]   <=  0;
+                        else if (|col_grant && starvation[i] < cfg_starve_limit)
+                            starvation[i]   <=  starvation[i]+1'b1;
+                    end
+        end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Burst chop logic
+    //----------------------------------------------------------------------------------------------------
+    // Logic to determine whether we will issue burst chop in DDR3 mode only
+    generate
+        begin
+            if (CFG_DWIDTH_RATIO == 2)
+                begin
+                    always @ (posedge ctl_clk or negedge ctl_reset_n)
+                        begin
+                            if (!ctl_reset_n)
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            burst_chop [i] <= 1'b0;
+                                        end
+                                end
+                            else
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            if (cfg_type == `MMR_TYPE_DDR3)
+                                                begin
+                                                    if (load_tbp [i])
+                                                        begin
+                                                            if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
+                                                                burst_chop [i] <= 1'b1;
+                                                            else if (cmd_gen_size == 1'b1)
+                                                                burst_chop [i] <= 1'b1;
+                                                            else
+                                                                burst_chop [i] <= 1'b0;
+                                                        end
+                                                end
+                                            else
+                                                begin
+                                                    burst_chop [i] <= 1'b0;
+                                                end
+                                        end
+                                end
+                        end
+                end
+            else if (CFG_DWIDTH_RATIO == 4)
+                begin
+                    always @ (posedge ctl_clk or negedge ctl_reset_n)
+                        begin
+                            if (!ctl_reset_n)
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            burst_chop [i] <= 1'b0;
+                                        end
+                                end
+                            else
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            if (cfg_type == `MMR_TYPE_DDR3)
+                                                begin
+                                                    if (load_tbp [i])
+                                                        begin
+                                                            if (cmd_gen_size == 1'b1)
+                                                                burst_chop [i] <= 1'b1;
+                                                            else
+                                                                burst_chop [i] <= 1'b0;
+                                                        end
+                                                end
+                                            else
+                                                begin
+                                                    burst_chop [i] <= 1'b0;
+                                                end
+                                        end
+                                end
+                        end
+                end
+            else if (CFG_DWIDTH_RATIO == 8)
+                begin
+                    // Burst chop is not available in quarter rate
+                    always @ (posedge ctl_clk or negedge ctl_reset_n)
+                        begin
+                            if (!ctl_reset_n)
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            burst_chop [i] <= 1'b0;
+                                        end
+                                end
+                            else
+                                begin
+                                    for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
+                                        begin
+                                            burst_chop [i] <= 1'b0;
+                                        end
+                                end
+                        end
+                end
+        end
+    endgenerate
+    
+    //----------------------------------------------------------------------------------------------------------------
+    
+    function integer log2;
+        input [31:0] value;
+        integer      i;
+        begin
+            log2 = 0;
+            
+            for(i = 0; 2**i < value; i = i + 1)
+                begin
+                    log2 = i + 1;
+                end
+        end
+    endfunction
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v
new file mode 100644
index 0000000..92f6495
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v
@@ -0,0 +1,732 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+//altera message_off 10230
+
+`include "alt_mem_ddrx_define.iv"
+
+`timescale 1 ps / 1 ps
+module alt_mem_ddrx_timing_param #
+    ( parameter
+        CFG_DWIDTH_RATIO                                    =   2,
+        CFG_CTL_ARBITER_TYPE                                =   "ROWCOL",
+        
+        // cfg: general
+        CFG_PORT_WIDTH_TYPE                                 =   3,
+        CFG_PORT_WIDTH_BURST_LENGTH                         =   5,
+        
+        // cfg: timing parameters
+        CFG_PORT_WIDTH_CAS_WR_LAT                           =   4,          // max will be 8 in DDR3
+        CFG_PORT_WIDTH_ADD_LAT                              =   3,          // max will be 10 in DDR3
+        CFG_PORT_WIDTH_TCL                                  =   4,          // max will be 11 in DDR3
+        CFG_PORT_WIDTH_TRRD                                 =   4,          // 2 - 8        enough?
+        CFG_PORT_WIDTH_TFAW                                 =   6,          // 6 - 32       enough?
+        CFG_PORT_WIDTH_TRFC                                 =   8,          // 12-140       enough?
+        CFG_PORT_WIDTH_TREFI                                =   13,         // 780 - 6240   enough?
+        CFG_PORT_WIDTH_TRCD                                 =   4,          // 2 - 11       enough?
+        CFG_PORT_WIDTH_TRP                                  =   4,          // 2 - 11       enough?
+        CFG_PORT_WIDTH_TWR                                  =   4,          // 2 - 12       enough?
+        CFG_PORT_WIDTH_TWTR                                 =   4,          // 1 - 10       enough?
+        CFG_PORT_WIDTH_TRTP                                 =   4,          // 2 - 8        enough?
+        CFG_PORT_WIDTH_TRAS                                 =   5,          // 4 - 29       enough?
+        CFG_PORT_WIDTH_TRC                                  =   6,          // 8 - 40       enough?
+        CFG_PORT_WIDTH_TCCD                                 =   3,          // max will be 4 in 4n prefetch architecture?
+        CFG_PORT_WIDTH_TMRD                                 =   3,          // 4 - ?        enough?
+        CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES                =   10,         // max will be 512 in DDR3
+        CFG_PORT_WIDTH_PDN_EXIT_CYCLES                      =   4,          // 3 - ?        enough?
+        CFG_PORT_WIDTH_AUTO_PD_CYCLES                       =   16,         // enough?
+        CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES             =   4,          // enough?
+        CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES                 =   4,          // enough?
+        
+        // cfg: extra timing parameters
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH              =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID         =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD               =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC            =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP     =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH              =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID         =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID       =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK   =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT        =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID           =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL          =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD             =   4,
+        CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD             =   4,
+        
+        // Output - derived timing parameters width
+        T_PARAM_ACT_TO_RDWR_WIDTH                           =   6,          // temporary
+        T_PARAM_ACT_TO_PCH_WIDTH                            =   6,          // temporary
+        T_PARAM_ACT_TO_ACT_WIDTH                            =   6,          // temporary
+        T_PARAM_RD_TO_RD_WIDTH                              =   6,          // temporary
+        T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH                    =   6,          // temporary
+        T_PARAM_RD_TO_WR_WIDTH                              =   6,          // temporary
+        T_PARAM_RD_TO_WR_BC_WIDTH                           =   6,          // temporary
+        T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH                    =   6,          // temporary
+        T_PARAM_RD_TO_PCH_WIDTH                             =   6,          // temporary
+        T_PARAM_RD_AP_TO_VALID_WIDTH                        =   6,          // temporary
+        T_PARAM_WR_TO_WR_WIDTH                              =   6,          // temporary
+        T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH                    =   6,          // temporary
+        T_PARAM_WR_TO_RD_WIDTH                              =   6,          // temporary
+        T_PARAM_WR_TO_RD_BC_WIDTH                           =   6,          // temporary
+        T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH                    =   6,          // temporary
+        T_PARAM_WR_TO_PCH_WIDTH                             =   6,          // temporary
+        T_PARAM_WR_AP_TO_VALID_WIDTH                        =   6,          // temporary
+        T_PARAM_PCH_TO_VALID_WIDTH                          =   6,          // temporary
+        T_PARAM_PCH_ALL_TO_VALID_WIDTH                      =   6,          // temporary
+        T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH                  =   6,          // temporary
+        T_PARAM_FOUR_ACT_TO_ACT_WIDTH                       =   6,          // temporary
+        T_PARAM_ARF_TO_VALID_WIDTH                          =   8,          // temporary
+        T_PARAM_PDN_TO_VALID_WIDTH                          =   6,          // temporary
+        T_PARAM_SRF_TO_VALID_WIDTH                          =   10,         // temporary
+        T_PARAM_SRF_TO_ZQ_CAL_WIDTH                         =   10,         // temporary
+        T_PARAM_ARF_PERIOD_WIDTH                            =   13,         // temporary
+        T_PARAM_PDN_PERIOD_WIDTH                            =   16,         // temporary
+        T_PARAM_POWER_SAVING_EXIT_WIDTH                     =   6,          // temporary
+        T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH                  =   4           // temporary
+    )
+    (
+        ctl_clk,
+        ctl_reset_n,
+        
+        // Input - configuration
+        cfg_burst_length,
+        cfg_type,
+        
+        // Input - memory timing parameter
+        cfg_cas_wr_lat,
+        cfg_add_lat,
+        cfg_tcl,
+        cfg_trrd,
+        cfg_tfaw,
+        cfg_trfc,
+        cfg_trefi,
+        cfg_trcd,
+        cfg_trp,
+        cfg_twr,
+        cfg_twtr,
+        cfg_trtp,
+        cfg_tras,
+        cfg_trc,
+        cfg_tccd,
+        cfg_tmrd,
+        cfg_self_rfsh_exit_cycles,
+        cfg_pdn_exit_cycles,
+        cfg_auto_pd_cycles,
+        cfg_power_saving_exit_cycles,
+        cfg_mem_clk_entry_cycles,
+        
+        // Input - extra derived timing parameter
+        cfg_extra_ctl_clk_act_to_rdwr,
+        cfg_extra_ctl_clk_act_to_pch,
+        cfg_extra_ctl_clk_act_to_act,
+        cfg_extra_ctl_clk_rd_to_rd,
+        cfg_extra_ctl_clk_rd_to_rd_diff_chip,
+        cfg_extra_ctl_clk_rd_to_wr,
+        cfg_extra_ctl_clk_rd_to_wr_bc,
+        cfg_extra_ctl_clk_rd_to_wr_diff_chip,
+        cfg_extra_ctl_clk_rd_to_pch,
+        cfg_extra_ctl_clk_rd_ap_to_valid,
+        cfg_extra_ctl_clk_wr_to_wr,
+        cfg_extra_ctl_clk_wr_to_wr_diff_chip,
+        cfg_extra_ctl_clk_wr_to_rd,
+        cfg_extra_ctl_clk_wr_to_rd_bc,
+        cfg_extra_ctl_clk_wr_to_rd_diff_chip,
+        cfg_extra_ctl_clk_wr_to_pch,
+        cfg_extra_ctl_clk_wr_ap_to_valid,
+        cfg_extra_ctl_clk_pch_to_valid,
+        cfg_extra_ctl_clk_pch_all_to_valid,
+        cfg_extra_ctl_clk_act_to_act_diff_bank,
+        cfg_extra_ctl_clk_four_act_to_act,
+        cfg_extra_ctl_clk_arf_to_valid,
+        cfg_extra_ctl_clk_pdn_to_valid,
+        cfg_extra_ctl_clk_srf_to_valid,
+        cfg_extra_ctl_clk_srf_to_zq_cal,
+        cfg_extra_ctl_clk_arf_period,
+        cfg_extra_ctl_clk_pdn_period,
+        
+        // Output - derived timing parameters
+        t_param_act_to_rdwr,
+        t_param_act_to_pch,
+        t_param_act_to_act,
+        t_param_rd_to_rd,
+        t_param_rd_to_rd_diff_chip,
+        t_param_rd_to_wr,
+        t_param_rd_to_wr_bc,
+        t_param_rd_to_wr_diff_chip,
+        t_param_rd_to_pch,
+        t_param_rd_ap_to_valid,
+        t_param_wr_to_wr,
+        t_param_wr_to_wr_diff_chip,
+        t_param_wr_to_rd,
+        t_param_wr_to_rd_bc,
+        t_param_wr_to_rd_diff_chip,
+        t_param_wr_to_pch,
+        t_param_wr_ap_to_valid,
+        t_param_pch_to_valid,
+        t_param_pch_all_to_valid,
+        t_param_act_to_act_diff_bank,
+        t_param_four_act_to_act,
+        t_param_arf_to_valid,
+        t_param_pdn_to_valid,
+        t_param_srf_to_valid,
+        t_param_srf_to_zq_cal,
+        t_param_arf_period,
+        t_param_pdn_period,
+        t_param_power_saving_exit,
+        t_param_mem_clk_entry_cycles
+    );
+
+input  ctl_clk;
+input  ctl_reset_n;
+
+// Input - configuration
+input  [CFG_PORT_WIDTH_BURST_LENGTH                       - 1 : 0] cfg_burst_length;
+input  [CFG_PORT_WIDTH_TYPE                               - 1 : 0] cfg_type;
+
+// Input - memory timing parameter
+input  [CFG_PORT_WIDTH_CAS_WR_LAT                         - 1 : 0] cfg_cas_wr_lat;
+input  [CFG_PORT_WIDTH_ADD_LAT                            - 1 : 0] cfg_add_lat;
+input  [CFG_PORT_WIDTH_TCL                                - 1 : 0] cfg_tcl;
+input  [CFG_PORT_WIDTH_TRRD                               - 1 : 0] cfg_trrd;
+input  [CFG_PORT_WIDTH_TFAW                               - 1 : 0] cfg_tfaw;
+input  [CFG_PORT_WIDTH_TRFC                               - 1 : 0] cfg_trfc;
+input  [CFG_PORT_WIDTH_TREFI                              - 1 : 0] cfg_trefi;
+input  [CFG_PORT_WIDTH_TRCD                               - 1 : 0] cfg_trcd;
+input  [CFG_PORT_WIDTH_TRP                                - 1 : 0] cfg_trp;
+input  [CFG_PORT_WIDTH_TWR                                - 1 : 0] cfg_twr;
+input  [CFG_PORT_WIDTH_TWTR                               - 1 : 0] cfg_twtr;
+input  [CFG_PORT_WIDTH_TRTP                               - 1 : 0] cfg_trtp;
+input  [CFG_PORT_WIDTH_TRAS                               - 1 : 0] cfg_tras;
+input  [CFG_PORT_WIDTH_TRC                                - 1 : 0] cfg_trc;
+input  [CFG_PORT_WIDTH_TCCD                               - 1 : 0] cfg_tccd;
+input  [CFG_PORT_WIDTH_TMRD                               - 1 : 0] cfg_tmrd;
+input  [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES              - 1 : 0] cfg_self_rfsh_exit_cycles;
+input  [CFG_PORT_WIDTH_PDN_EXIT_CYCLES                    - 1 : 0] cfg_pdn_exit_cycles;
+input  [CFG_PORT_WIDTH_AUTO_PD_CYCLES                     - 1 : 0] cfg_auto_pd_cycles;
+input  [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES           - 1 : 0] cfg_power_saving_exit_cycles;
+input  [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES               - 1 : 0] cfg_mem_clk_entry_cycles;
+
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR          - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH           - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT           - 1 : 0] cfg_extra_ctl_clk_act_to_act;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD             - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR             - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC          - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH            - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID       - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR             - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD             - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC          - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP   - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH            - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID       - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID     - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT      - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID         - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL        - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD           - 1 : 0] cfg_extra_ctl_clk_arf_period;
+input  [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD           - 1 : 0] cfg_extra_ctl_clk_pdn_period;
+
+// Output - derived timing parameters
+output [T_PARAM_ACT_TO_RDWR_WIDTH                         - 1 : 0] t_param_act_to_rdwr;
+output [T_PARAM_ACT_TO_PCH_WIDTH                          - 1 : 0] t_param_act_to_pch;
+output [T_PARAM_ACT_TO_ACT_WIDTH                          - 1 : 0] t_param_act_to_act;
+output [T_PARAM_RD_TO_RD_WIDTH                            - 1 : 0] t_param_rd_to_rd;
+output [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH                  - 1 : 0] t_param_rd_to_rd_diff_chip;
+output [T_PARAM_RD_TO_WR_WIDTH                            - 1 : 0] t_param_rd_to_wr;
+output [T_PARAM_RD_TO_WR_BC_WIDTH                         - 1 : 0] t_param_rd_to_wr_bc;
+output [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH                  - 1 : 0] t_param_rd_to_wr_diff_chip;
+output [T_PARAM_RD_TO_PCH_WIDTH                           - 1 : 0] t_param_rd_to_pch;
+output [T_PARAM_RD_AP_TO_VALID_WIDTH                      - 1 : 0] t_param_rd_ap_to_valid;
+output [T_PARAM_WR_TO_WR_WIDTH                            - 1 : 0] t_param_wr_to_wr;
+output [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH                  - 1 : 0] t_param_wr_to_wr_diff_chip;
+output [T_PARAM_WR_TO_RD_WIDTH                            - 1 : 0] t_param_wr_to_rd;
+output [T_PARAM_WR_TO_RD_BC_WIDTH                         - 1 : 0] t_param_wr_to_rd_bc;
+output [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH                  - 1 : 0] t_param_wr_to_rd_diff_chip;
+output [T_PARAM_WR_TO_PCH_WIDTH                           - 1 : 0] t_param_wr_to_pch;
+output [T_PARAM_WR_AP_TO_VALID_WIDTH                      - 1 : 0] t_param_wr_ap_to_valid;
+output [T_PARAM_PCH_TO_VALID_WIDTH                        - 1 : 0] t_param_pch_to_valid;
+output [T_PARAM_PCH_ALL_TO_VALID_WIDTH                    - 1 : 0] t_param_pch_all_to_valid;
+output [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH                - 1 : 0] t_param_act_to_act_diff_bank;
+output [T_PARAM_FOUR_ACT_TO_ACT_WIDTH                     - 1 : 0] t_param_four_act_to_act;
+output [T_PARAM_ARF_TO_VALID_WIDTH                        - 1 : 0] t_param_arf_to_valid;
+output [T_PARAM_PDN_TO_VALID_WIDTH                        - 1 : 0] t_param_pdn_to_valid;
+output [T_PARAM_SRF_TO_VALID_WIDTH                        - 1 : 0] t_param_srf_to_valid;
+output [T_PARAM_SRF_TO_ZQ_CAL_WIDTH                       - 1 : 0] t_param_srf_to_zq_cal;
+output [T_PARAM_ARF_PERIOD_WIDTH                          - 1 : 0] t_param_arf_period;
+output [T_PARAM_PDN_PERIOD_WIDTH                          - 1 : 0] t_param_pdn_period;
+output [T_PARAM_POWER_SAVING_EXIT_WIDTH                   - 1 : 0] t_param_power_saving_exit;
+output [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH                - 1 : 0] t_param_mem_clk_entry_cycles;
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+    // Output
+    reg  [T_PARAM_ACT_TO_RDWR_WIDTH                   - 1 : 0] t_param_act_to_rdwr;
+    reg  [T_PARAM_ACT_TO_PCH_WIDTH                    - 1 : 0] t_param_act_to_pch;
+    reg  [T_PARAM_ACT_TO_ACT_WIDTH                    - 1 : 0] t_param_act_to_act;
+    reg  [T_PARAM_RD_TO_RD_WIDTH                      - 1 : 0] t_param_rd_to_rd;
+    reg  [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH            - 1 : 0] t_param_rd_to_rd_diff_chip;
+    reg  [T_PARAM_RD_TO_WR_WIDTH                      - 1 : 0] t_param_rd_to_wr;
+    reg  [T_PARAM_RD_TO_WR_BC_WIDTH                   - 1 : 0] t_param_rd_to_wr_bc;
+    reg  [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH            - 1 : 0] t_param_rd_to_wr_diff_chip;
+    reg  [T_PARAM_RD_TO_PCH_WIDTH                     - 1 : 0] t_param_rd_to_pch;
+    reg  [T_PARAM_RD_AP_TO_VALID_WIDTH                - 1 : 0] t_param_rd_ap_to_valid;
+    reg  [T_PARAM_WR_TO_WR_WIDTH                      - 1 : 0] t_param_wr_to_wr;
+    reg  [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH            - 1 : 0] t_param_wr_to_wr_diff_chip;
+    reg  [T_PARAM_WR_TO_RD_WIDTH                      - 1 : 0] t_param_wr_to_rd;
+    reg  [T_PARAM_WR_TO_RD_BC_WIDTH                   - 1 : 0] t_param_wr_to_rd_bc;
+    reg  [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH            - 1 : 0] t_param_wr_to_rd_diff_chip;
+    reg  [T_PARAM_WR_TO_PCH_WIDTH                     - 1 : 0] t_param_wr_to_pch;
+    reg  [T_PARAM_WR_AP_TO_VALID_WIDTH                - 1 : 0] t_param_wr_ap_to_valid;
+    reg  [T_PARAM_PCH_TO_VALID_WIDTH                  - 1 : 0] t_param_pch_to_valid;
+    reg  [T_PARAM_PCH_ALL_TO_VALID_WIDTH              - 1 : 0] t_param_pch_all_to_valid;
+    reg  [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH          - 1 : 0] t_param_act_to_act_diff_bank;
+    reg  [T_PARAM_FOUR_ACT_TO_ACT_WIDTH               - 1 : 0] t_param_four_act_to_act;
+    reg  [T_PARAM_ARF_TO_VALID_WIDTH                  - 1 : 0] t_param_arf_to_valid;
+    reg  [T_PARAM_PDN_TO_VALID_WIDTH                  - 1 : 0] t_param_pdn_to_valid;
+    reg  [T_PARAM_SRF_TO_VALID_WIDTH                  - 1 : 0] t_param_srf_to_valid;
+    reg  [T_PARAM_SRF_TO_ZQ_CAL_WIDTH                 - 1 : 0] t_param_srf_to_zq_cal;
+    reg  [T_PARAM_SRF_TO_ZQ_CAL_WIDTH                 - 1 : 0] t_param_srf_to_zq_cal_temp1;
+    reg  [T_PARAM_ARF_PERIOD_WIDTH                    - 1 : 0] t_param_arf_period;
+    reg  [T_PARAM_PDN_PERIOD_WIDTH                    - 1 : 0] t_param_pdn_period;
+    reg  [T_PARAM_POWER_SAVING_EXIT_WIDTH             - 1 : 0] t_param_power_saving_exit;
+    reg  [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH          - 1 : 0] t_param_mem_clk_entry_cycles;
+    
+    reg  [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH            - 1 : 0] temp_wr_to_rd_diff_chip;
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Register & Wires
+//
+//--------------------------------------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------------------------------------
+//
+//  [START] Timing Parameter Calculation
+//  
+//  Important Note:
+//  
+//  - Added "cfg_extra_ctl_clk_*" ports into our timing parameter calculation in order for us to
+//  tweak the timing parameter gaps in the future without changing the code
+//  
+//  - This will be very useful in HIP implementation
+//  
+//  - "cfg_extra_ctl_clk_*" must be set in term of controller clock cycles
+//
+//--------------------------------------------------------------------------------------------------------
+    // DIV is a divider for our timing parameters, DIV will be '1' in fullrate, '2' in halfrate
+    // and '4' in quarter rate
+    localparam DIV = CFG_DWIDTH_RATIO / 2;
+    
+    // Use the following table to determine the optimum timing parameter
+    // ==========================================================================================================
+    // ||   Controller Rate   ||   Arbiter Type   ||   Command Transition   ||   Remainder DIV   ||   Offset   ||
+    // ==========================================================================================================
+    // ||        FR           ||    Don't care    ||       Don't care       ||       Yes         ||     No     ||
+    // ----------------------------------------------------------------------------------------------------------
+    // ||                     ||                  ||       Row -> Col       ||       Yes         ||     No     ||
+    // --                     --      ROWCOL      ---------------------------------------------------------------
+    // ||                     ||                  ||       Col -> Row       ||       No          ||     Yes    ||
+    // --        HR           -----------------------------------------------------------------------------------
+    // ||                     ||                  ||       Row -> Col       ||       No          ||     Yes    ||
+    // --                     --      COLROW      ---------------------------------------------------------------
+    // ||                     ||                  ||       Col -> Row       ||       Yes         ||     No     ||
+    // ----------------------------------------------------------------------------------------------------------
+    // ||                     ||                  ||       Row -> Col       ||       Yes*        ||     No     ||
+    // --                     --      ROWCOL      ---------------------------------------------------------------
+    // ||                     ||                  ||       Col -> Row       ||       Yes*        ||     Yes    ||
+    // --        QR           -----------------------------------------------------------------------------------
+    // ||                     ||                  ||       Row -> Col       ||       Yes*        ||     Yes    ||
+    // --                     --      COLROW      ---------------------------------------------------------------
+    // ||                     ||                  ||       Col -> Row       ||       Yes*        ||     No     ||
+    // ----------------------------------------------------------------------------------------------------------
+    // Footnote:
+    // * for calculation with remainder of '3' only
+    
+    //---------------------------------------------------
+    // Remainder calculation
+    //---------------------------------------------------
+    // We need to remove the extra clock cycle in half and quarter rate
+    // for two subsequent different commands but remain for two subsequent same commands
+    // example of two subsequent different commands: ROW-TO-COL, COL-TO-ROW
+    // example of two subsequent same commands: ROW-TO-ROW, COL-TO-COL
+    
+    // Self to self command require DIV
+    localparam DIV_ROW_TO_ROW = DIV;
+    localparam DIV_COL_TO_COL = DIV;
+    localparam DIV_SB_TO_SB   = DIV;
+    
+    localparam DIV_ROW_TO_COL =     (
+                                        (CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
+                                            (
+                                                DIV // Need DIV in full & quarter rate
+                                            ) :
+                                            (
+                                                (CFG_DWIDTH_RATIO == 4) ?
+                                                    (
+                                                        (CFG_CTL_ARBITER_TYPE == "ROWCOL") ? DIV : 1 // Only need DIV in ROWCOL arbiter mode
+                                                    ) :
+                                                    (
+                                                        DIV // DIV is assigned by default
+                                                    )
+                                            )
+                                    );
+    localparam DIV_COL_TO_ROW =     (
+                                        (CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
+                                            (
+                                                DIV // Need DIV in full & quarter rate
+                                            ) :
+                                            (
+                                                (CFG_DWIDTH_RATIO == 4) ?
+                                                    (
+                                                        (CFG_CTL_ARBITER_TYPE == "COLROW") ? DIV : 1 // Only need DIV in COLROW arbiter mode
+                                                    ) :
+                                                    (
+                                                        DIV // DIV is assigned by default
+                                                    )
+                                            )
+                                    );
+    localparam DIV_SB_TO_ROW  =     DIV_COL_TO_ROW; // Similar to COL_TO_ROW parameter
+    
+    //---------------------------------------------------
+    // Remainder offset calculation
+    //---------------------------------------------------
+    // In QR, odd number calculation will only need to add extra offset when calculation's remainder is > 2
+    
+    // Self to self command's remainder offset will be 0
+    localparam DIV_ROW_TO_ROW_OFFSET = 0;
+    localparam DIV_COL_TO_COL_OFFSET = 0;
+    localparam DIV_SB_TO_SB_OFFSET   = 0;
+    
+    localparam DIV_ROW_TO_COL_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
+    localparam DIV_COL_TO_ROW_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
+    localparam DIV_SB_TO_ROW_OFFSET  = DIV_COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
+    
+    //---------------------------------------------------
+    // Offset calculation
+    //---------------------------------------------------
+    // We need to offset timing parameter due to HR 1T and QR 2T support
+    // this is because we can issue a row and column command in one controller clock cycle
+    
+    // Self to self command doesn't require offset
+    localparam ROW_TO_ROW_OFFSET = 0;
+    localparam COL_TO_COL_OFFSET = 0;
+    localparam SB_TO_SB_OFFSET   = 0;
+    
+    localparam ROW_TO_COL_OFFSET =  (
+                                        (CFG_DWIDTH_RATIO == 2) ?
+                                            (
+                                                0 // Offset is not required in full rate
+                                            ) :
+                                            (
+                                                (CFG_CTL_ARBITER_TYPE == "ROWCOL") ? 0 : 1 // Need offset in ROWCOL arbiter mode
+                                            )
+                                    );
+    localparam COL_TO_ROW_OFFSET =  (
+                                        (CFG_DWIDTH_RATIO == 2) ?
+                                            (
+                                                0 // Offset is not required in full rate
+                                            ) :
+                                            (
+                                                (CFG_CTL_ARBITER_TYPE == "COLROW") ? 0 : 1 // Need offset in COLROW arbiter mode
+                                            )
+                                    );
+    localparam SB_TO_ROW_OFFSET  =  COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
+    
+    //----------------------------------------------------------------------------------------------------
+    // Common timing parameters, not memory type specific
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            t_param_act_to_rdwr          <= 0;
+            t_param_act_to_pch           <= 0;
+            t_param_act_to_act           <= 0;
+            t_param_pch_to_valid         <= 0;
+            t_param_act_to_act_diff_bank <= 0;
+            t_param_four_act_to_act      <= 0;
+            t_param_arf_to_valid         <= 0;
+            t_param_pdn_to_valid         <= 0;
+            t_param_srf_to_valid         <= 0;
+            t_param_arf_period           <= 0;
+            t_param_pdn_period           <= 0;
+            t_param_power_saving_exit    <= 0;
+            t_param_mem_clk_entry_cycles <= 0;
+        end
+        else
+        begin
+            // Set act_to_rdwr to '0' when additive latency is enabled
+            if (cfg_add_lat >= (cfg_trcd - 1))
+                t_param_act_to_rdwr      <= 0                                                                                                                        + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr         ;
+            else
+                t_param_act_to_rdwr      <= ((cfg_trcd - cfg_add_lat)     / DIV) + (((cfg_trcd - cfg_add_lat)     % DIV_ROW_TO_COL) > DIV_ROW_TO_COL_OFFSET ? 1 : 0) + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr         ;          // ACT to RD/WR                         - tRCD
+            
+            t_param_act_to_pch           <= (cfg_tras                     / DIV) + ((cfg_tras                     % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_pch          ;          // ACT to PCH                           - tRAS
+            t_param_act_to_act           <= (cfg_trc                      / DIV) + ((cfg_trc                      % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act          ;          // ACT to ACT (same bank)               - tRC
+            
+            t_param_pch_to_valid         <= (cfg_trp                      / DIV) + ((cfg_trp                      % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_to_valid        ;          // PCH to ACT                           - tRP
+            
+            t_param_act_to_act_diff_bank <= (cfg_trrd                     / DIV) + ((cfg_trrd                     % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act_diff_bank;          // ACT to ACT (diff banks)              - tRRD
+            t_param_four_act_to_act      <= (cfg_tfaw                     / DIV) + ((cfg_tfaw                     % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_four_act_to_act     ;          // Valid window for 4 ACT               - tFAW
+            
+            t_param_arf_to_valid         <= (cfg_trfc                     / DIV) + ((cfg_trfc                     % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) +  SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_arf_to_valid        ;          // ARF to VALID                         - tRFC
+            t_param_pdn_to_valid         <= (cfg_pdn_exit_cycles          / DIV) + ((cfg_pdn_exit_cycles          % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) +  SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pdn_to_valid        ;          // PDN to VALID                         - normally 3 clock cycles
+            t_param_srf_to_valid         <= (cfg_self_rfsh_exit_cycles    / DIV) + ((cfg_self_rfsh_exit_cycles    % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) +  SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_srf_to_valid        ;          // SRF to VALID                         - normally 200 clock cycles
+            
+            t_param_arf_period           <= (cfg_trefi                    / DIV) + ((cfg_trefi                    % DIV_SB_TO_SB  ) > DIV_SB_TO_SB_OFFSET   ? 1 : 0) +   SB_TO_SB_OFFSET + cfg_extra_ctl_clk_arf_period          ;          // ARF period                           - tREFI
+            t_param_pdn_period           <= cfg_auto_pd_cycles                                                                                                       +   SB_TO_SB_OFFSET + cfg_extra_ctl_clk_pdn_period          ;          // PDN count after TBP is empty         - specified by user
+            
+            t_param_power_saving_exit    <= (cfg_power_saving_exit_cycles / DIV) + ((cfg_power_saving_exit_cycles % DIV_SB_TO_SB  ) > DIV_SB_TO_SB_OFFSET   ? 1 : 0) +   SB_TO_SB_OFFSET                                         ;          // SRF and PDN exit cycles
+            t_param_mem_clk_entry_cycles <= (cfg_mem_clk_entry_cycles     / DIV) + ((cfg_mem_clk_entry_cycles     % DIV_SB_TO_SB  ) > DIV_SB_TO_SB_OFFSET   ? 1 : 0) +   SB_TO_SB_OFFSET                                         ;          // SRF and PDN mem clock entry and exit cycles
+        end
+    end
+    
+    //----------------------------------------------------------------------------------------------------
+    // Memory type specific timing parameters
+    //----------------------------------------------------------------------------------------------------
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            t_param_rd_to_rd            <= 0;
+            t_param_rd_to_rd_diff_chip  <= 0;
+            t_param_rd_to_wr            <= 0;
+            t_param_rd_to_wr_bc         <= 0;
+            t_param_rd_to_wr_diff_chip  <= 0;
+            t_param_rd_to_pch           <= 0;
+            t_param_rd_ap_to_valid      <= 0;
+            t_param_wr_to_wr            <= 0;
+            t_param_wr_to_wr_diff_chip  <= 0;
+            t_param_wr_to_rd            <= 0;
+            t_param_wr_to_rd_bc         <= 0;
+            t_param_wr_to_rd_diff_chip  <= 0;
+            t_param_wr_to_pch           <= 0;
+            t_param_wr_ap_to_valid      <= 0;
+            t_param_pch_all_to_valid    <= 0;
+            t_param_srf_to_zq_cal_temp1 <= 0;
+            t_param_srf_to_zq_cal       <= 0;
+            
+            temp_wr_to_rd_diff_chip     <= 0;
+        end
+        else
+        begin
+            if (cfg_type == `MMR_TYPE_DDR1)
+            begin
+                // DDR
+                // ******************************
+                // Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
+                // to remain consistent with the controller
+                // ******************************
+                t_param_rd_to_rd            <= (cfg_tccd / DIV)                                         + ((cfg_tccd % DIV_COL_TO_COL)                                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd          ;      // RD to RD             - tCCD
+                t_param_rd_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip;      // RD to RD diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_rd_to_wr            <= (((cfg_burst_length / 2) + cfg_tcl) / DIV)               + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL)               > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr          ;      // RD to WR             - RL + (BL/2)
+                t_param_rd_to_wr_bc         <= 0                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc       ;      // RDBC to WR           - 0, DDR3 specific only
+                t_param_rd_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                     + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip;      // RD to WR diff rank   - Same as RD to WR
+                t_param_rd_to_pch           <= ((cfg_burst_length / 2) / DIV)                           + (((cfg_burst_length / 2) % DIV_COL_TO_ROW)                           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch         ;      // RD to PCH            - (BL/2)
+                t_param_rd_ap_to_valid      <= (((cfg_burst_length / 2) + cfg_trp) / DIV)               + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW)               > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid    ;      // RDAP to VALID        - RD to PCH + PCH to VALID
+                
+                t_param_wr_to_wr            <= (cfg_tccd / DIV)                                         + ((cfg_tccd % DIV_COL_TO_COL)                                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr          ;      // WR to WR             - tCCD
+                t_param_wr_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip;      // WR to WR diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_wr_to_rd            <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV)          + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL)          > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd          ;      // WR to RD             - WL + (BL/2) + tWTR, WL always 1
+                t_param_wr_to_rd_bc         <= 0                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc       ;      // WRBC to RD           - 0, DDR3 specific only
+                t_param_wr_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 3) / DIV)                     + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip;      // WR to RD diff rank   - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
+                t_param_wr_to_pch           <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV)           + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW)           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch         ;      // WR to PCH            - WL + (BL/2) + tWR
+                t_param_wr_ap_to_valid      <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid    ;      // WRAP to VALID        - WR to PCH + PCH to VALID
+                
+                t_param_pch_all_to_valid    <= ((cfg_trp + 1) / DIV)                                    + (((cfg_trp + 1) % DIV_SB_TO_ROW )                                    > DIV_SB_TO_ROW_OFFSET  ? 1 : 0) + SB_TO_ROW_OFFSET  + cfg_extra_ctl_clk_pch_all_to_valid  ;      // PCHALL to VALID      - tRPA = tRP + 1
+                
+                t_param_srf_to_zq_cal       <= 0                                                                                                                                                                + SB_TO_SB_OFFSET   + cfg_extra_ctl_clk_srf_to_zq_cal     ;      // SRF to ZQ CAL        - 0, DDR3 specific only
+            end
+            else if (cfg_type == `MMR_TYPE_DDR2)
+            begin
+                // DDR2
+                // ******************************
+                // Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
+                // to remain consistent with the controller
+                // ******************************
+                t_param_rd_to_rd            <= (cfg_tccd / DIV)                                                                 + ((cfg_tccd % DIV_COL_TO_COL)                                                                 > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd          ;      // RD to RD             - tCCD
+                t_param_rd_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip;      // RD to RD diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_rd_to_wr            <= (((cfg_burst_length / 2) + 2) / DIV)                                             + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                                             > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr          ;      // RD to WR             - RL - WL + (BL/2) + 1, (RL - WL) will always be '1'
+                t_param_rd_to_wr_bc         <= 0                                                                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc       ;      // RDBC to WR           - 0, DDR3 specific only
+                t_param_rd_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                             + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                                             > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip;      // RD to WR diff rank   - Same as RD to WR
+                t_param_rd_to_pch           <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) / DIV)            + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) % DIV_COL_TO_ROW)            > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch         ;      // RD to PCH            - AL + (BL/2) - 2 + max(tRTP or 2)
+                t_param_rd_ap_to_valid      <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) / DIV)  + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW)  > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid    ;      // RDAP to VALID        - RD to PCH + PCH to VALID
+                
+                t_param_wr_to_wr            <= (cfg_tccd / DIV)                                                                 + ((cfg_tccd % DIV_COL_TO_COL)                                                                 > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr          ;      // WR to WR             - tCCD
+                t_param_wr_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip;      // WR to WR diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_wr_to_rd            <= ((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) / DIV)                        + (((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL)                        > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd          ;      // WR to RD             - WL + (BL/2) + tWTR
+                t_param_wr_to_rd_bc         <= 0                                                                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc       ;      // WRBC to RD           - 0, DDR3 specific only
+                t_param_wr_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 1) / DIV)                                             + ((((cfg_burst_length / 2) + 1) % DIV_COL_TO_COL)                                             > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip;      // WR to RD diff rank   - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
+                t_param_wr_to_pch           <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) / DIV)           + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW)           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch         ;      // WR to PCH            - WL + (BL/2) + tWR
+                t_param_wr_ap_to_valid      <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid    ;      // WRAP to VALID        - WR to PCH + PCH to VALID
+                
+                t_param_pch_all_to_valid    <= ((cfg_trp + 1) / DIV)                                                            + (((cfg_trp + 1) % DIV_SB_TO_ROW )                                                            > DIV_SB_TO_ROW_OFFSET  ? 1 : 0) + SB_TO_ROW_OFFSET  + cfg_extra_ctl_clk_pch_all_to_valid  ;      // PCHALL to VALID      - tRPA = tRP + 1
+                
+                t_param_srf_to_zq_cal       <= 0                                                                                                                                                                                                                + SB_TO_SB_OFFSET   + cfg_extra_ctl_clk_srf_to_zq_cal     ;      // SRF to ZQ CAL        - 0, DDR3 specific only
+            end
+            else if (cfg_type == `MMR_TYPE_DDR3)
+            begin
+                // ******************************
+                // Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
+                // to remain consistent with the controller
+                // ******************************
+                
+                // Temp value to make sure value is always larger than tCL (guaranteed), else it might create problem in HIP
+                // BL will alyways be set to 8 and max difference between tCL and tCWL is 3
+                temp_wr_to_rd_diff_chip     <= (cfg_cas_wr_lat + (cfg_burst_length / 2) + 2);
+                
+                t_param_rd_to_rd            <= ((cfg_burst_length / 2) / DIV)                                                                                                                                                                                         + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd          ;       // RD to RD             - BL/2, not tCCD because there is no burst interrupt support in DDR3
+                t_param_rd_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                                   + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip;       // RD to RD diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_rd_to_wr            <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV)                     + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr          ;       // RD to WR             - RL - WL + (BL/2) + 2
+                t_param_rd_to_wr_bc         <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) / DIV)                     + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc       ;       // RDBC to WR           - RL - WL + (BL/4) + 2
+                t_param_rd_to_wr_diff_chip  <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV)                     + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip;       // RD to WR diff rank   - Same as RD to WR
+                t_param_rd_to_pch           <= ((cfg_add_lat + max(cfg_trtp, 4)) / DIV)                                            + (((cfg_add_lat + max(cfg_trtp, 4)) % DIV_COL_TO_ROW)                                            > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch         ;       // RD to PCH            - AL + max(tRTP or 4)
+                t_param_rd_ap_to_valid      <= ((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) / DIV)                                  + (((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) % DIV_COL_TO_ROW)                                  > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid    ;       // RDAP to VALID        - RD to PCH + PCH to VALID
+                
+                t_param_wr_to_wr            <= ((cfg_burst_length / 2) / DIV)                                                                                                                                                                                         + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr          ;       // WR to WR             - BL/2, not tCCD because there is no burst interrupt support in DDR3
+                t_param_wr_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                                   + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip;       // WR to WR diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_wr_to_rd            <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV)                + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL)                > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd          ;       // WR to RD             - WL + (BL/2) + max(tWTR or 4)
+                t_param_wr_to_rd_bc         <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV)                + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL)                > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc       ;       // WRBC to RD           - Same as WR to RD
+                t_param_wr_to_rd_diff_chip  <= ((temp_wr_to_rd_diff_chip - cfg_tcl) / DIV)                                         + (((temp_wr_to_rd_diff_chip - cfg_tcl) % DIV_COL_TO_COL)                                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip;       // WR to RD diff rank   - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
+                t_param_wr_to_pch           <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) / DIV)           + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW)           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch         ;       // WR to PCH            - WL + (BL/2) + tWR
+                t_param_wr_ap_to_valid      <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid    ;       // WRAP to VALID        - WR to PCH + PCH to VALID
+                
+                t_param_pch_all_to_valid    <= (cfg_trp / DIV)                                                                     + ((cfg_trp % DIV_SB_TO_ROW )                                                                     > DIV_SB_TO_ROW_OFFSET  ? 1 : 0) + SB_TO_ROW_OFFSET  + cfg_extra_ctl_clk_pch_all_to_valid  ;       // PCHALL to VALID      - tRP
+                
+                t_param_srf_to_zq_cal_temp1       <= ((cfg_self_rfsh_exit_cycles / 2) / DIV)                                                                                                                                                                                + SB_TO_SB_OFFSET   + cfg_extra_ctl_clk_srf_to_zq_cal     ;       // SRF to ZQ CAL        - SRF exit time divided by 2
+		t_param_srf_to_zq_cal       <= (t_param_arf_to_valid < t_param_srf_to_zq_cal_temp1) ? t_param_srf_to_zq_cal_temp1 : (t_param_arf_to_valid + 10); //Set proper delay for 933MHz
+            end
+            else if (cfg_type == `MMR_TYPE_LPDDR1)
+            begin
+                // LPDDR
+                // ******************************
+                // Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
+                // to remain consistent with the controller
+                // ******************************
+                t_param_rd_to_rd            <= (cfg_tccd / DIV)                                         + ((cfg_tccd % DIV_COL_TO_COL)                                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd          ;      // RD to RD             - tCCD
+                t_param_rd_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip;      // RD to RD diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_rd_to_wr            <= (((cfg_burst_length / 2) + cfg_tcl) / DIV)               + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL)               > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr          ;      // RD to WR             - RL + (BL/2)
+                t_param_rd_to_wr_bc         <= 0                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc       ;      // RDBC to WR           - 0, DDR3 specific only
+                t_param_rd_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                     + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip;      // RD to WR diff rank   - Same as RD to WR
+                t_param_rd_to_pch           <= ((cfg_burst_length / 2) / DIV)                           + (((cfg_burst_length / 2) % DIV_COL_TO_ROW)                           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch         ;      // RD to PCH            - (BL/2)
+                t_param_rd_ap_to_valid      <= (((cfg_burst_length / 2) + cfg_trp) / DIV)               + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW)               > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid    ;      // RDAP to VALID        - RD to PCH + PCH to VALID
+                
+                t_param_wr_to_wr            <= (cfg_tccd / DIV)                                         + ((cfg_tccd % DIV_COL_TO_COL)                                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr          ;      // WR to WR             - tCCD
+                t_param_wr_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                             + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip;      // WR to WR diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_wr_to_rd            <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV)          + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL)          > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd          ;      // WR to RD             - WL + (BL/2) + tWTR, WL always 1
+                t_param_wr_to_rd_bc         <= 0                                                                                                                                                                + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc       ;      // WRBC to RD           - 0, DDR3 specific only
+                t_param_wr_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 3) / DIV)                     + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL)                     > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip;      // WR to RD diff rank   - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
+                t_param_wr_to_pch           <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV)           + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW)           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch         ;      // WR to PCH            - WL + (BL/2) + tWR
+                t_param_wr_ap_to_valid      <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid    ;      // WRAP to VALID        - WR to PCH + PCH to VALID
+                
+                t_param_pch_all_to_valid    <= ((cfg_trp + 1) / DIV)                                    + (((cfg_trp + 1) % DIV_SB_TO_ROW )                                    > DIV_SB_TO_ROW_OFFSET  ? 1 : 0) + SB_TO_ROW_OFFSET  + cfg_extra_ctl_clk_pch_all_to_valid  ;      // PCHALL to VALID      - tRPA = tRP + 1
+                
+                t_param_srf_to_zq_cal       <= 0                                                                                                                                                                + SB_TO_SB_OFFSET   + cfg_extra_ctl_clk_srf_to_zq_cal     ;      // SRF to ZQ CAL        - 0, DDR3 specific only
+            end
+            else if (cfg_type == `MMR_TYPE_LPDDR2)
+            begin
+                // LPDDR2
+                // ******************************
+                // Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
+                // to remain consistent with the controller
+                // ******************************
+                
+                // Temp value to precalculate difference between tCL and tCWL + 2 (dead cycle)
+                if ((cfg_tcl - cfg_cas_wr_lat) > 2)
+                begin
+                    temp_wr_to_rd_diff_chip <= 0;
+                end
+                else
+                begin
+                    temp_wr_to_rd_diff_chip <= (cfg_cas_wr_lat + 2) - cfg_tcl;
+                end
+                
+                t_param_rd_to_rd            <= (cfg_tccd / DIV)                                                                        + ((cfg_tccd % DIV_COL_TO_COL)                                                                        > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd          ;      // RD to RD             - tCCD
+                t_param_rd_to_rd_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                                           + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip;      // RD to RD diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_rd_to_wr            <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV)                         + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL)                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr          ;      // RD to WR             - RL - WL + (BL/2) + 2
+                t_param_rd_to_wr_bc         <= 0                                                                                                                                                                                                                              + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc       ;      // RDBC to WR           - 0, DDR3 specific only
+                t_param_rd_to_wr_diff_chip  <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV)                         + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL)                         > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip;      // RD to WR diff rank   - Same as RD to WR
+                t_param_rd_to_pch           <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) / DIV)            + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) % DIV_COL_TO_ROW)            > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch         ;      // RD to PCH            - AL + (BL/2) - 2 + max(tRTP or 2)
+                t_param_rd_ap_to_valid      <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) / DIV)  + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW)  > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid    ;      // RDAP to VALID        - RD to PCH + PCH to VALID
+                
+                t_param_wr_to_wr            <= (cfg_tccd / DIV)                                                                        + ((cfg_tccd % DIV_COL_TO_COL)                                                                        > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr          ;      // WR to WR             - tCCD
+                t_param_wr_to_wr_diff_chip  <= (((cfg_burst_length / 2) + 2) / DIV)                                                                                                                                                                                           + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip;      // WR to WR diff rank   - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
+                t_param_wr_to_rd            <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) / DIV)                + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) % DIV_COL_TO_COL)                > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd          ;      // WR to RD             - WL + (BL/2) + max(tWTR or 4)
+                t_param_wr_to_rd_bc         <= 0                                                                                                                                                                                                                              + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc       ;      // WRBC to RD           - 0, DDR3 specific only
+                t_param_wr_to_rd_diff_chip  <= ((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) / DIV)                              + (((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) % DIV_COL_TO_COL)                              > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip;      // WR to RD diff rank   - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
+                t_param_wr_to_pch           <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) / DIV)           + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) % DIV_COL_TO_ROW)           > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch         ;      // WR to PCH            - WL + (BL/2) + tWR
+                t_param_wr_ap_to_valid      <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid    ;      // WRAP to VALID        - WR to PCH + PCH to VALID
+                
+                t_param_pch_all_to_valid    <= ((cfg_trp + 1) / DIV)                                                                   + (((cfg_trp + 1) % DIV_SB_TO_ROW )                                                                   > DIV_SB_TO_ROW_OFFSET  ? 1 : 0) + SB_TO_ROW_OFFSET  + cfg_extra_ctl_clk_pch_all_to_valid  ;      // PCHALL to VALID      - tRPA = tRP + 1
+                
+                t_param_srf_to_zq_cal       <= 0                                                                                                                                                                                                                              + SB_TO_SB_OFFSET   + cfg_extra_ctl_clk_srf_to_zq_cal     ;      // SRF to ZQ CAL        - 0, DDR3 specific only
+            end
+        end
+    end
+    
+    // Function to determine max of 2 inputs
+    localparam MAX_FUNCTION_PORT_WIDTH = (CFG_PORT_WIDTH_TRTP > CFG_PORT_WIDTH_TWTR) ? CFG_PORT_WIDTH_TRTP : CFG_PORT_WIDTH_TWTR;
+    
+    function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
+        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
+        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
+        begin
+            if (value1 > value2)
+                max = value1;
+            else
+                max = value2;
+        end
+    endfunction
+//--------------------------------------------------------------------------------------------------------
+//
+//  [END] Timing Parameter Calculation
+//
+//--------------------------------------------------------------------------------------------------------
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v
new file mode 100644
index 0000000..04a167e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v
@@ -0,0 +1,1128 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//altera message_off 10230 10036
+
+`timescale 1 ps / 1 ps
+
+module alt_mem_ddrx_wdata_path
+# (
+    // module parameter port list
+    parameter
+        CFG_LOCAL_DATA_WIDTH                      = 16,
+        CFG_MEM_IF_DQ_WIDTH                       = 8,
+        CFG_MEM_IF_DQS_WIDTH                      = 1,
+        CFG_INT_SIZE_WIDTH                        = 5,
+        CFG_DATA_ID_WIDTH                         = 4,
+        CFG_DRAM_WLAT_GROUP                       = 1,
+        CFG_LOCAL_WLAT_GROUP                      = 1,
+        CFG_TBP_NUM                               = 8,
+        CFG_BUFFER_ADDR_WIDTH                     = 10,
+        CFG_DWIDTH_RATIO                          = 2,
+        CFG_ECC_MULTIPLES                         = 1,
+        CFG_WDATA_REG                             = 0,
+        CFG_PARTIAL_BE_PER_WORD_ENABLE            = 1,
+        CFG_ECC_CODE_WIDTH                        = 8,
+        CFG_PORT_WIDTH_BURST_LENGTH               = 5,
+        CFG_PORT_WIDTH_ENABLE_ECC                 = 1,
+        CFG_PORT_WIDTH_ENABLE_AUTO_CORR           = 1,
+        CFG_PORT_WIDTH_ENABLE_NO_DM               = 1,
+        CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
+        CFG_PORT_WIDTH_INTERFACE_WIDTH            = 8,
+	CFG_ECC_BE_ALLLOW_RMW			  = 0
+)
+(
+    // port list
+    ctl_clk,
+    ctl_reset_n,
+
+    // configuration signals
+    cfg_burst_length,
+    cfg_enable_ecc,
+    cfg_enable_auto_corr,
+    cfg_enable_no_dm,
+    cfg_enable_ecc_code_overwrites,
+    cfg_interface_width,
+
+    // command generator & TBP command load interface / cmd update interface
+    wdatap_free_id_valid,
+    wdatap_free_id_dataid,
+    proc_busy,
+    proc_load,
+    proc_load_dataid,
+    proc_write,
+    tbp_load_index,
+    proc_size,
+
+    // input interface data channel / buffer write interface
+    wr_data_mem_full,
+    write_data_en,
+    write_data,
+    byte_en,
+    
+    // notify TBP interface
+    data_complete,
+    data_rmw_complete,
+    data_rmw_fetch,
+    data_partial_be,
+    
+    // AFI interface / buffer read interface
+    doing_write,
+    dataid,
+    dataid_vector,
+    rdwr_data_valid,
+    rmw_correct,
+    rmw_partial,
+    
+    doing_write_first,
+    dataid_first,
+    dataid_vector_first,
+    rdwr_data_valid_first,
+    rmw_correct_first,
+    rmw_partial_first,
+    doing_write_first_vector,
+    rdwr_data_valid_first_vector,
+    
+    doing_write_last,
+    dataid_last,
+    dataid_vector_last,
+    rdwr_data_valid_last,
+    rmw_correct_last,
+    rmw_partial_last,
+    
+    wdatap_data,
+    wdatap_rmw_partial_data,
+    wdatap_rmw_correct_data,
+    wdatap_rmw_partial,
+    wdatap_rmw_correct,
+    wdatap_dm,
+    wdatap_ecc_code,
+    wdatap_ecc_code_overwrite,
+
+    // RMW fifo interface, from rdatap
+    rmwfifo_data_valid,
+    rmwfifo_data,
+    rmwfifo_ecc_dbe,
+    rmwfifo_ecc_code
+
+);
+
+    // -----------------------------
+    // local parameter declarations
+    // -----------------------------
+
+    localparam CFG_MEM_IF_DQ_PER_DQS                = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
+    
+    localparam CFG_BURSTCOUNT_TRACKING_WIDTH        = CFG_BUFFER_ADDR_WIDTH+1;
+    
+    localparam CFG_RMWFIFO_ECC_DBE_WIDTH            = CFG_ECC_MULTIPLES;
+    localparam CFG_RMWFIFO_ECC_CODE_WIDTH           = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
+    localparam CFG_RMWDATA_FIFO_DATA_WIDTH          = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
+    localparam CFG_RMWDATA_FIFO_ADDR_WIDTH          = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
+
+    localparam CFG_LOCAL_BE_WIDTH                   = CFG_LOCAL_DATA_WIDTH / 8;
+    localparam CFG_LOCAL_DM_WIDTH                   = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
+    localparam CFG_MMR_DRAM_DATA_WIDTH              = CFG_PORT_WIDTH_INTERFACE_WIDTH;
+    localparam CFG_MMR_DRAM_DM_WIDTH                = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
+
+    localparam integer CFG_DATAID_ARRAY_DEPTH       = (2**CFG_DATA_ID_WIDTH);
+    
+    localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP      = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
+    localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP        = CFG_LOCAL_DM_WIDTH   / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
+    
+    
+    // -----------------------------
+    // port declaration
+    // -----------------------------
+
+    // clock and reset
+    input                                           ctl_clk;
+    input                                           ctl_reset_n;
+
+    // configuration signals
+    input   [CFG_PORT_WIDTH_BURST_LENGTH     - 1 : 0]           cfg_burst_length;
+    input   [CFG_PORT_WIDTH_ENABLE_ECC       - 1 : 0]           cfg_enable_ecc;
+    input   [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0]           cfg_enable_auto_corr;
+    input   [CFG_PORT_WIDTH_ENABLE_NO_DM     - 1 : 0]           cfg_enable_no_dm;
+    input   [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
+    input   [CFG_PORT_WIDTH_INTERFACE_WIDTH  - 1 : 0]           cfg_interface_width;
+    
+    //  command generator free dataid interface
+    output                                          wdatap_free_id_valid;
+    output  [CFG_DATA_ID_WIDTH-1:0]                 wdatap_free_id_dataid;
+
+    // command generator & TBP command load interface / cmd update interface
+    input                                           proc_busy;       
+    input                                           proc_load;
+    input                                           proc_load_dataid;
+    input                                           proc_write;
+    input   [CFG_TBP_NUM-1:0]                       tbp_load_index;
+    input   [CFG_INT_SIZE_WIDTH-1:0]                proc_size;   
+
+    // input interface data channel / buffer write interface
+    output                                          wr_data_mem_full;  
+    input                                           write_data_en;
+    input   [CFG_LOCAL_DATA_WIDTH-1:0]              write_data;
+    input   [CFG_LOCAL_BE_WIDTH-1:0]                byte_en;
+    
+    // notify TBP interface
+    output  [CFG_TBP_NUM-1:0]                       data_complete;
+    output                                          data_rmw_complete;      // broadcast to TBP's
+    input                                           data_rmw_fetch;
+    output                                          data_partial_be;
+    
+    // AFI interface / buffer read interface
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        doing_write;
+    input   [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]      dataid;
+    input   [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        rdwr_data_valid;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        rmw_correct;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        rmw_partial;
+    
+    input                                                    doing_write_first;
+    input   [CFG_DATA_ID_WIDTH-1:0]                          dataid_first;
+    input   [CFG_DATAID_ARRAY_DEPTH-1:0]                     dataid_vector_first;
+    input                                                    rdwr_data_valid_first;
+    input                                                    rmw_correct_first;
+    input                                                    rmw_partial_first;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        doing_write_first_vector;
+    input   [CFG_DRAM_WLAT_GROUP-1:0]                        rdwr_data_valid_first_vector;
+    
+    input                                                    doing_write_last;
+    input   [CFG_DATA_ID_WIDTH-1:0]                          dataid_last;
+    input   [CFG_DATAID_ARRAY_DEPTH-1:0]                     dataid_vector_last;
+    input                                                    rdwr_data_valid_last;
+    input                                                    rmw_correct_last;
+    input                                                    rmw_partial_last;
+    
+    output  [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_data;
+    output  [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_rmw_partial_data;
+    output  [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_rmw_correct_data;
+    output                                                   wdatap_rmw_partial;
+    output                                                   wdatap_rmw_correct;
+    output  [CFG_LOCAL_DM_WIDTH-1:0]                         wdatap_dm;
+    output  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
+    output  [CFG_ECC_MULTIPLES                      - 1 : 0] wdatap_ecc_code_overwrite;
+
+    // RMW fifo interface
+    input                                                   rmwfifo_data_valid; 
+    input  [CFG_LOCAL_DATA_WIDTH-1:0]                       rmwfifo_data;
+    input  [CFG_ECC_MULTIPLES- 1 : 0]                       rmwfifo_ecc_dbe;
+    input  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
+
+    // -----------------------------
+    // port type declaration
+    // -----------------------------
+
+    // clock and reset
+    wire                                            ctl_clk;
+    wire                                            ctl_reset_n;
+
+    // configuration signals
+    wire    [CFG_PORT_WIDTH_BURST_LENGTH     - 1 : 0]           cfg_burst_length;
+    wire    [CFG_PORT_WIDTH_ENABLE_ECC       - 1 : 0]           cfg_enable_ecc;
+    wire    [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0]           cfg_enable_auto_corr;
+    wire    [CFG_PORT_WIDTH_ENABLE_NO_DM     - 1 : 0]           cfg_enable_no_dm;
+    wire    [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;             // overwrite (and don't re-calculate) ecc code on DBE
+    wire    [CFG_PORT_WIDTH_INTERFACE_WIDTH  - 1 : 0]           cfg_interface_width;
+    
+    //  command generator free dataid interface
+    wire                                            wdatap_free_id_valid;
+    wire                                            wdatap_int_free_id_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                 wdatap_free_id_dataid;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]            wdatap_free_id_dataid_vector;
+
+    // command generator & TBP command load interface / cmd update interface
+    wire                                            proc_busy;       
+    wire                                            proc_load;
+    wire                                            proc_load_dataid;
+    wire                                            proc_write;
+    wire    [CFG_TBP_NUM-1:0]                       tbp_load_index;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                proc_size;   
+
+    // input interface data channel / buffer write interface
+    wire                                            wr_data_mem_full;  
+    wire                                            write_data_en;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]              write_data;
+    wire    [CFG_LOCAL_BE_WIDTH-1:0]                byte_en;
+    
+    // notify TBP interface
+    wire    [CFG_TBP_NUM-1:0]                       data_complete;
+    wire                                            data_rmw_complete;
+    wire                                            data_partial_be;
+    
+    // AFI interface / buffer read interface
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                        doing_write;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]      dataid;
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                        rdwr_data_valid;
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                        rmw_correct;
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                        rmw_partial;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_data;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_rmw_partial_data;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                       wdatap_rmw_correct_data;
+    wire                                                     wdatap_rmw_partial;
+    wire                                                     wdatap_rmw_correct;
+    wire    [CFG_LOCAL_DM_WIDTH-1:0]                         wdatap_dm;
+    reg     [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
+    reg     [CFG_ECC_MULTIPLES                      - 1 : 0] wdatap_ecc_code_overwrite;
+
+    // RMW fifo interface
+    wire                                                   rmwfifo_data_valid; 
+    wire  [CFG_LOCAL_DATA_WIDTH-1:0]                       rmwfifo_data;
+    wire  [CFG_ECC_MULTIPLES- 1 : 0]                       rmwfifo_ecc_dbe;
+    wire  [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
+
+
+    // -----------------------------
+    // signal declaration
+    // -----------------------------
+
+    // configuration
+    reg  [CFG_MMR_DRAM_DATA_WIDTH  - 1 : 0]             cfg_dram_data_width;
+    reg  [CFG_MMR_DRAM_DM_WIDTH    - 1 : 0]             cfg_dram_dm_width;
+
+    // command generator & TBP command load interface / cmd update interface
+    wire                                                wdatap_cmdload_ready;
+    wire                                                wdatap_cmdload_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                     wdatap_cmdload_dataid;
+    wire    [CFG_TBP_NUM-1:0]                           wdatap_cmdload_tbp_index;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                    wdatap_cmdload_burstcount;
+
+    // input interface data channel / buffer write interface
+    wire                                                wdatap_datawrite_ready;
+    wire                                                wdatap_datawrite_valid;
+    wire                                                wdatap_datawrite_accepted;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                  wdatap_datawrite_data;
+    wire    [CFG_LOCAL_BE_WIDTH-1:0]                    wdatap_datawrite_be;
+    reg     [CFG_LOCAL_DM_WIDTH-1:0]                    wdatap_datawrite_dm;
+    reg     [CFG_LOCAL_DM_WIDTH-1:0]                    int_datawrite_dm;
+    wire                                                wdatap_datawrite_partial_be;
+    wire						wdatap_datawrite_allzeros_be;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                 wdatap_datawrite_address;
+    reg     [CFG_ECC_MULTIPLES-1:0]                     int_datawrite_partial_be;
+
+    // notify TBP interface
+    wire    [CFG_TBP_NUM-1:0]                           wdatap_tbp_data_ready;
+    wire                                                wdatap_tbp_data_partial_be;
+
+    // AFI interface data channel / buffer read interface
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                           wdatap_dataread_valid;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]         wdatap_dataread_dataid;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0]    wdatap_dataread_dataid_vector;
+    reg     [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0]         wdatap_dataread_dataid_r;
+    wire                                                        wdatap_dataread_valid_first;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                             wdatap_dataread_dataid_first;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                        wdatap_dataread_dataid_vector_first;
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                           wdatap_dataread_valid_first_vector;
+    wire                                                        wdatap_dataread_valid_last;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                             wdatap_dataread_dataid_last;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                        wdatap_dataread_dataid_vector_last;
+    wire    [CFG_DRAM_WLAT_GROUP-1:0]                           wdatap_dataread_datavalid;
+    reg     [CFG_LOCAL_DATA_WIDTH-1:0]                          wdatap_dataread_data;
+    reg     [CFG_LOCAL_DATA_WIDTH-1:0]                          wdatap_dataread_rmw_partial_data;
+    reg     [CFG_LOCAL_DATA_WIDTH-1:0]                          wdatap_dataread_rmw_correct_data;
+    reg                                                         wdatap_dataread_rmw_partial;
+    reg                                                         wdatap_dataread_rmw_correct;
+    reg     [CFG_LOCAL_DM_WIDTH-1:0]                            wdatap_dataread_dm;
+    wire    [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0]     wdatap_dataread_address;
+    wire                                                        wdatap_dataread_done;
+    wire                                                        wdatap_dataread_ready;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]                          wdatap_dataread_buffer_data;
+    wire    [CFG_LOCAL_DM_WIDTH-1:0]                            wdatap_dataread_buffer_dm;
+
+    wire                                                        wdatap_free_id_get_ready;
+    wire                                                        wdatap_allocated_put_ready;
+    wire                                                        wdatap_allocated_put_valid;
+
+    wire                                                        wdatap_update_data_dataid_valid;
+    wire    [CFG_DATA_ID_WIDTH-1:0]                             wdatap_update_data_dataid;
+    wire    [CFG_DATAID_ARRAY_DEPTH-1:0]                        wdatap_update_data_dataid_vector;
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]                 wdatap_update_data_burstcount;
+    wire    [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0]                 wdatap_update_data_next_burstcount;
+    wire                                                        wdatap_notify_data_valid;
+    wire    [CFG_INT_SIZE_WIDTH-1:0]                            wdatap_notify_data_burstcount_consumed;
+
+    // buffer read/write signals
+    wire                                                        wdatap_buffwrite_valid;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                         wdatap_buffwrite_address;
+    wire                                                        wdatap_buffread_valid;
+    wire    [CFG_BUFFER_ADDR_WIDTH-1:0]                         wdatap_buffread_address;
+
+    wire    [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0]       rmwfifo_input;
+    wire    [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0]       rmwfifo_output;
+    wire                                            rmwfifo_output_read;
+    wire                                            rmwfifo_output_valid;
+    reg                                             rmwfifo_output_valid_r;
+    wire                                            rmwfifo_output_valid_pulse;
+    reg                                             rmwfifo_output_valid_handshake;
+    wire    [CFG_LOCAL_DATA_WIDTH-1:0]              rmwfifo_output_data;
+    reg     [CFG_LOCAL_DATA_WIDTH-1:0]              rmwfifo_output_data_r;
+    wire    [CFG_ECC_MULTIPLES- 1 : 0]              rmwfifo_output_ecc_dbe;
+    wire    [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
+
+    reg     [CFG_LOCAL_DATA_WIDTH-1:0]              rmw_merged_data;
+    reg                                             rmw_correct_r1;
+    reg                                             rmw_partial_r1;
+    reg                                             rmw_correct_r2;
+    reg                                             rmw_partial_r2;
+    wire                                            rmwfifo_ready; 
+
+    // debug signals, for assertions
+    wire                                                        err_rmwfifo_overflow;
+
+    // -----------------------------
+    // module definition
+    // -----------------------------
+
+    // renaming port names to more meaningfull internal names
+    
+    assign wdatap_cmdload_valid         = ~proc_busy & proc_load & proc_write & proc_load_dataid;
+    assign wdatap_cmdload_tbp_index     = tbp_load_index;
+    assign wdatap_cmdload_burstcount    = proc_size;
+    assign wdatap_cmdload_dataid        = wdatap_free_id_dataid;
+
+    assign wr_data_mem_full             = ~wdatap_datawrite_ready;
+    assign wdatap_datawrite_valid       = write_data_en;
+    assign wdatap_datawrite_data        = write_data;
+    assign wdatap_datawrite_be          = byte_en; // we need to replicate
+
+    assign data_complete                = wdatap_tbp_data_ready;
+    assign data_rmw_complete            = rmwfifo_output_valid_pulse | rmwfifo_output_valid_handshake;       // broadcast to all TBP's
+    assign data_partial_be              = wdatap_tbp_data_partial_be;
+    
+    assign wdatap_dataread_valid               = doing_write & rdwr_data_valid & ~rmw_correct;
+    assign wdatap_dataread_dataid              = dataid;
+    assign wdatap_dataread_dataid_vector       = dataid_vector;
+    assign wdatap_dataread_valid_first         = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
+    assign wdatap_dataread_dataid_first        = dataid_first;
+    assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
+    assign wdatap_dataread_valid_first_vector  = rdwr_data_valid_first_vector;
+    assign wdatap_dataread_valid_last          = doing_write_last  & rdwr_data_valid_last  & ~rmw_correct_last ;
+    assign wdatap_dataread_dataid_last         = dataid_last;
+    assign wdatap_dataread_dataid_vector_last  = dataid_vector_last;
+    assign wdatap_data                         = wdatap_dataread_data;
+    assign wdatap_rmw_partial_data             = wdatap_dataread_rmw_partial_data;
+    assign wdatap_rmw_correct_data             = wdatap_dataread_rmw_correct_data;
+    assign wdatap_rmw_partial                  = wdatap_dataread_rmw_partial;
+    assign wdatap_rmw_correct                  = wdatap_dataread_rmw_correct;
+    assign wdatap_dm                           = wdatap_dataread_dm;
+
+    // internal signals
+
+    // flow control between free list & allocated list
+    assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
+    assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
+    assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
+
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_dram_data_width <= 0;
+        end
+        else
+        begin
+            if (cfg_enable_ecc)
+            begin
+                cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;            // SPR:362973
+            end
+            else
+            begin
+                cfg_dram_data_width <= cfg_interface_width;
+            end
+        end
+    end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            cfg_dram_dm_width <= 0;
+        end
+        else
+        begin
+            cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
+        end
+    end
+
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            //reset state ...
+            wdatap_dataread_dataid_r <= 0;
+        end
+        else
+        begin
+            //active state ...
+            wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
+        end
+    end
+    
+    alt_mem_ddrx_list
+    #(
+        .CTL_LIST_WIDTH                             (CFG_DATA_ID_WIDTH),
+        .CTL_LIST_DEPTH                             (CFG_DATAID_ARRAY_DEPTH),
+        .CTL_LIST_INIT_VALUE_TYPE                   ("INCR"),
+        .CTL_LIST_INIT_VALID                        ("VALID")
+    )
+    wdatap_list_freeid_inst
+    (
+     .ctl_clk                                       (ctl_clk),
+     .ctl_reset_n                                   (ctl_reset_n),
+                                                                        
+     .list_get_entry_ready                          (wdatap_free_id_get_ready),
+     .list_get_entry_valid                          (wdatap_int_free_id_valid),
+     .list_get_entry_id                             (wdatap_free_id_dataid),   
+     .list_get_entry_id_vector                      (wdatap_free_id_dataid_vector),   
+    
+     // wdatap_dataread_ready can be ignored, list entry availability is guaranteed
+     .list_put_entry_ready                          (wdatap_dataread_ready),                             
+     .list_put_entry_valid                          (wdatap_dataread_done),         
+     .list_put_entry_id                             (wdatap_dataread_dataid_r)
+    );
+
+    alt_mem_ddrx_list
+    #(
+        .CTL_LIST_WIDTH                             (CFG_DATA_ID_WIDTH),
+        .CTL_LIST_DEPTH                             (CFG_DATAID_ARRAY_DEPTH),
+        .CTL_LIST_INIT_VALUE_TYPE                   ("ZERO"),
+        .CTL_LIST_INIT_VALID                        ("INVALID")
+    )
+    wdatap_list_allocated_id_inst
+    (
+     .ctl_clk                                       (ctl_clk),
+     .ctl_reset_n                                   (ctl_reset_n),
+                                                                               
+     .list_get_entry_ready                          (wdatap_notify_data_valid),
+     .list_get_entry_valid                          (wdatap_update_data_dataid_valid),
+     .list_get_entry_id                             (wdatap_update_data_dataid),   
+     .list_get_entry_id_vector                      (wdatap_update_data_dataid_vector),   
+
+     // wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
+     .list_put_entry_ready                          (wdatap_allocated_put_ready),
+     .list_put_entry_valid                          (wdatap_allocated_put_valid),    
+     .list_put_entry_id                             (wdatap_free_id_dataid)
+    );
+    
+    alt_mem_ddrx_burst_tracking
+    # (
+        .CFG_BURSTCOUNT_TRACKING_WIDTH              (CFG_BURSTCOUNT_TRACKING_WIDTH),
+        .CFG_BUFFER_ADDR_WIDTH                      (CFG_BUFFER_ADDR_WIDTH),
+        .CFG_INT_SIZE_WIDTH                         (CFG_INT_SIZE_WIDTH)
+    )
+    wdatap_burst_tracking_inst
+    (
+        // port list
+        .ctl_clk                                    (ctl_clk),
+        .ctl_reset_n                                (ctl_reset_n),
+                                                                      
+        // data burst interface                                       
+        .burst_ready                                (wdatap_datawrite_ready),
+        .burst_valid                                (wdatap_datawrite_valid),
+
+        // burstcount counter sent to data_id_manager
+        .burst_pending_burstcount                   (wdatap_update_data_burstcount),
+        .burst_next_pending_burstcount              (wdatap_update_data_next_burstcount),
+
+        // burstcount consumed by data_id_manager
+        .burst_consumed_valid                       (wdatap_notify_data_valid),
+        .burst_counsumed_burstcount                 (wdatap_notify_data_burstcount_consumed)
+    );
+
+    alt_mem_ddrx_dataid_manager
+    # (
+        .CFG_DATA_ID_WIDTH                          (CFG_DATA_ID_WIDTH),
+        .CFG_LOCAL_WLAT_GROUP                       (CFG_LOCAL_WLAT_GROUP),
+        .CFG_DRAM_WLAT_GROUP                        (CFG_DRAM_WLAT_GROUP),
+        .CFG_BUFFER_ADDR_WIDTH                      (CFG_BUFFER_ADDR_WIDTH),
+        .CFG_INT_SIZE_WIDTH                         (CFG_INT_SIZE_WIDTH),
+        .CFG_TBP_NUM                                (CFG_TBP_NUM),
+        .CFG_BURSTCOUNT_TRACKING_WIDTH              (CFG_BURSTCOUNT_TRACKING_WIDTH),
+        .CFG_PORT_WIDTH_BURST_LENGTH                (CFG_PORT_WIDTH_BURST_LENGTH),
+        .CFG_DWIDTH_RATIO                           (CFG_DWIDTH_RATIO),
+	.CFG_ECC_BE_ALLLOW_RMW			    (CFG_ECC_BE_ALLLOW_RMW)
+    )
+    wdatap_dataid_manager_inst
+    (
+
+        // clock & reset
+        .ctl_clk                                    (ctl_clk),
+        .ctl_reset_n                                (ctl_reset_n),
+
+        // configuration signals
+        .cfg_burst_length                           (cfg_burst_length),
+        .cfg_enable_ecc                             (cfg_enable_ecc),
+        .cfg_enable_auto_corr                       (cfg_enable_auto_corr),
+        .cfg_enable_no_dm                           (cfg_enable_no_dm),
+
+        // update cmd interface                                                                                                        
+        .update_cmd_if_ready                        (wdatap_cmdload_ready),
+        .update_cmd_if_valid                        (wdatap_cmdload_valid),
+        .update_cmd_if_data_id                      (wdatap_cmdload_dataid),    
+        .update_cmd_if_burstcount                   (wdatap_cmdload_burstcount),
+        .update_cmd_if_tbp_id                       (wdatap_cmdload_tbp_index),    
+                                                                                                
+        // update data interface                                                               
+        .update_data_if_valid                       (wdatap_update_data_dataid_valid),
+        .update_data_if_data_id                     (wdatap_update_data_dataid),
+        .update_data_if_data_id_vector              (wdatap_update_data_dataid_vector),
+        .update_data_if_burstcount                  (wdatap_update_data_burstcount),    
+        .update_data_if_next_burstcount             (wdatap_update_data_next_burstcount),    
+                                                                                                                                       
+        // notify data interface                                                                                                       
+        .notify_data_if_valid                       (wdatap_notify_data_valid),
+        .notify_data_if_burstcount                  (wdatap_notify_data_burstcount_consumed),    
+                                                                                                                                       
+        // notify tbp interface                                                                                               
+        .notify_tbp_data_ready                      (wdatap_tbp_data_ready),
+        .notify_tbp_data_partial_be                 (wdatap_tbp_data_partial_be),
+         
+        // buffer write address generate interface
+        .write_data_if_ready                        (wdatap_datawrite_ready),
+        .write_data_if_valid                        (wdatap_datawrite_valid),
+        .write_data_if_accepted                     (wdatap_datawrite_accepted),
+        .write_data_if_address                      (wdatap_datawrite_address),
+        .write_data_if_partial_be                   (wdatap_datawrite_partial_be),
+	.write_data_if_allzeros_be	    	    (wdatap_datawrite_allzeros_be),
+
+        // read data interface
+        .read_data_if_valid                         (wdatap_dataread_valid),
+        .read_data_if_data_id                       (wdatap_dataread_dataid),
+        .read_data_if_data_id_vector                (wdatap_dataread_dataid_vector),
+        .read_data_if_valid_first                   (wdatap_dataread_valid_first),
+        .read_data_if_data_id_first                 (wdatap_dataread_dataid_first),
+        .read_data_if_data_id_vector_first          (wdatap_dataread_dataid_vector_first),
+        .read_data_if_valid_first_vector            (wdatap_dataread_valid_first_vector),
+        .read_data_if_valid_last                    (wdatap_dataread_valid_last),
+        .read_data_if_data_id_last                  (wdatap_dataread_dataid_last),
+        .read_data_if_data_id_vector_last           (wdatap_dataread_dataid_vector_last),
+        .read_data_if_address                       (wdatap_dataread_address),
+        .read_data_if_datavalid                     (wdatap_dataread_datavalid),
+        .read_data_if_done                          (wdatap_dataread_done)          // use with wdatap_dataread_dataid_r
+    );
+
+    genvar wdatap_m;
+    genvar wdatap_n;
+    generate
+        for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
+        begin : wdata_buffer_per_dwidth_ratio
+            for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
+            begin : wdata_buffer_per_dqs_group
+                alt_mem_ddrx_buffer
+                # (
+                    .ADDR_WIDTH                                 (CFG_BUFFER_ADDR_WIDTH),
+                    .DATA_WIDTH                                 (CFG_WR_DATA_WIDTH_PER_DQS_GROUP),
+                    .REGISTER_OUTPUT                            (CFG_WDATA_REG)
+                )
+                wdatap_buffer_data_inst
+                (
+                    // port list
+                    .ctl_clk                                    (ctl_clk),
+                    .ctl_reset_n                                (ctl_reset_n),
+                    
+                    // write interface
+                    .write_valid                                (wdatap_datawrite_accepted),
+                    .write_address                              (wdatap_datawrite_address),
+                    .write_data                                 (wdatap_datawrite_data       [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
+                    
+                    // read interface
+                    .read_valid                                 (wdatap_dataread_valid       [wdatap_n]),
+                    .read_address                               (wdatap_dataread_address     [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
+                    .read_data                                  (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
+                );
+                
+                alt_mem_ddrx_buffer
+                # (
+                    .ADDR_WIDTH                                 (CFG_BUFFER_ADDR_WIDTH),
+                    .DATA_WIDTH                                 (CFG_WR_DM_WIDTH_PER_DQS_GROUP),
+                    .REGISTER_OUTPUT                            (CFG_WDATA_REG)
+                )
+                wdatap_buffer_be_inst
+                (
+                    // port list
+                    .ctl_clk                                    (ctl_clk),
+                    .ctl_reset_n                                (ctl_reset_n),
+                    
+                    // write interface
+                    .write_valid                                (wdatap_datawrite_accepted),
+                    .write_address                              (wdatap_datawrite_address),
+                    .write_data                                 (int_datawrite_dm          [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
+                    
+                    // read interface
+                    .read_valid                                 (wdatap_dataread_valid     [wdatap_n]),
+                    .read_address                               (wdatap_dataread_address   [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
+                    .read_data                                  (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
+                );
+            end
+        end
+    endgenerate
+
+    //
+    // byteenables analysis & generation
+    //
+    //  -   generate partial byteenable signal, per DQ word or per local word
+    //  -   set unused interface width byteenables to either 0 or 1
+    //
+
+    genvar wdatap_j, wdatap_k;
+    generate
+		if (CFG_ECC_BE_ALLLOW_RMW) begin
+			
+			reg     [CFG_ECC_MULTIPLES-1:0]                      be_all_ones;
+			reg     [CFG_ECC_MULTIPLES-1:0]                      be_all_zeros;
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio    [CFG_ECC_MULTIPLES-1:0];
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1          [CFG_ECC_MULTIPLES-1:0];
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0          [CFG_ECC_MULTIPLES-1:0];
+			
+			assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
+			assign wdatap_datawrite_allzeros_be = (!cfg_enable_no_dm & &be_all_zeros) ? 1'b1 : 1'b0;
+			
+			for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
+			begin : local_dm
+				always @ (*)
+				begin
+					if (CFG_MEM_IF_DQ_PER_DQS == 4)
+					begin
+						wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
+					end
+					else
+					begin
+						wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
+					end
+				end
+			end
+			
+			for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1) 
+			begin : gen_partial_be
+	
+				always @ (*) 
+				begin
+				be_all_ones[wdatap_j]    = &int_datawrite_dm_unused1[wdatap_j];
+				be_all_zeros[wdatap_j]   = ~(|int_datawrite_dm_unused0[wdatap_j]);
+					wdatap_datawrite_dm_widthratio [wdatap_j] =  wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
+				end
+				
+				for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
+				begin : gen_dm_unused_bits
+					always @ (*) 
+					begin
+						if (wdatap_k < cfg_dram_dm_width)
+						begin
+							int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] =  wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
+							int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] =  wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
+						end
+						else
+						begin
+							int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] =  {1'b1};
+							int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] =  {1'b0};
+						end
+					end
+				end
+				
+				always @ (*) 
+				begin
+					// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
+					if (cfg_enable_no_dm)
+					begin
+						int_datawrite_partial_be[wdatap_j] =  ~be_all_ones[wdatap_j];
+					end
+					else
+					begin
+						int_datawrite_partial_be[wdatap_j] =  ~(be_all_ones[wdatap_j] | be_all_zeros[wdatap_j]);
+					end
+					
+					if (cfg_enable_ecc)
+					begin
+						if (be_all_zeros[wdatap_j])
+						begin
+							// no ECC code will be written
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
+						end
+						else
+						begin
+							// higher unused be bit will be used for ECC word
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
+						end
+					end
+					else
+					begin
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
+					end
+				end
+			end
+		end
+		else begin
+			
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio    [CFG_ECC_MULTIPLES-1:0];
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1          [CFG_ECC_MULTIPLES-1:0];
+			reg     [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0          [CFG_ECC_MULTIPLES-1:0];
+			
+			assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
+			assign wdatap_datawrite_allzeros_be = 0;
+			
+			for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
+			begin : local_dm
+				always @ (*)
+				begin
+					if (CFG_MEM_IF_DQ_PER_DQS == 4)
+					begin
+						wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
+					end
+					else
+					begin
+						wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
+					end
+				end
+			end
+			
+			for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1) 
+			begin : gen_partial_be
+				wire be_all_ones    = &int_datawrite_dm_unused1[wdatap_j];
+				wire be_all_zeros   = ~(|int_datawrite_dm_unused0[wdatap_j]);
+				
+				always @ (*) 
+				begin
+						wdatap_datawrite_dm_widthratio [wdatap_j] =  wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
+				end
+				
+				for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
+				begin : gen_dm_unused_bits
+					always @ (*) 
+					begin
+						if (wdatap_k < cfg_dram_dm_width)
+						begin
+							int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] =  wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
+							int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] =  wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
+						end
+						else
+						begin
+							int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] =  {1'b1};
+							int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] =  {1'b0};
+						end
+					end
+				end
+				
+				always @ (*) 
+				begin
+					// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
+					if (cfg_enable_no_dm)
+					begin
+						int_datawrite_partial_be[wdatap_j] =  ~be_all_ones;
+					end
+					else
+					begin
+						int_datawrite_partial_be[wdatap_j] =  ~( be_all_ones | be_all_zeros );
+					end
+					
+					if (cfg_enable_ecc)
+					begin
+						if (be_all_zeros)
+						begin
+							// no ECC code will be written
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
+						end
+						else
+						begin
+							// higher unused be bit will be used for ECC word
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
+						end
+					end
+					else
+					begin
+							int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
+					end
+				end
+			end
+		end
+        
+    endgenerate
+
+
+    //
+    // rmw data fifo
+    //
+
+    // assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
+    assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
+    
+    // New data_rmw_complete logic, TBP/cmd_gen will have to assert data_rmw_fetch before data_rmw_complete de-asserts
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rmwfifo_output_valid_handshake <= 1'b0;
+        end
+        else
+        begin
+            if (data_rmw_fetch)
+            begin
+                rmwfifo_output_valid_handshake <= 1'b0;
+            end
+            else if (rmwfifo_output_valid_pulse)
+            begin
+                rmwfifo_output_valid_handshake <= 1'b1;
+            end
+        end
+    end
+    
+    always @ (posedge ctl_clk or negedge ctl_reset_n) 
+    begin
+        if (~ctl_reset_n)
+        begin
+            rmwfifo_output_valid_r  <= 1'b0;
+            rmw_correct_r1          <= 1'b0;
+            rmw_partial_r1          <= 1'b0;
+            rmw_correct_r2          <= 1'b0;
+            rmw_partial_r2          <= 1'b0;
+        end
+        else
+        begin
+            rmwfifo_output_valid_r  <= rmwfifo_output_valid;
+            rmw_correct_r1          <= rmw_correct;
+            rmw_partial_r1          <= rmw_partial;
+            rmw_correct_r2          <= rmw_correct_r1;
+            rmw_partial_r2          <= rmw_partial_r1;
+        end
+    end
+    
+    // RMW FIFO output register
+    always @ (posedge ctl_clk or negedge ctl_reset_n)
+    begin
+        if (!ctl_reset_n)
+        begin
+            rmwfifo_output_data_r <= 0;
+        end
+        else
+        begin
+            rmwfifo_output_data_r <= rmwfifo_output_data;
+        end
+    end
+
+    assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
+    assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
+    assign rmwfifo_output_read = rmw_correct_r1 | (&wdatap_dataread_datavalid & rmw_partial_r1); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
+    assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
+
+    alt_mem_ddrx_fifo
+    #(
+        .CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
+        .CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
+    )
+    rmw_data_fifo_inst
+    (
+        .ctl_clk            (ctl_clk),
+        .ctl_reset_n        (ctl_reset_n),
+
+        .get_ready          (rmwfifo_output_read),
+        .get_valid          (rmwfifo_output_valid),
+        .get_data           (rmwfifo_output),
+
+        .put_ready          (rmwfifo_ready),
+        .put_valid          (rmwfifo_data_valid),
+        .put_data           (rmwfifo_input)
+    );
+
+
+    //
+    // rmw data merge block
+    //
+
+    genvar wdatap_i;
+    generate
+        for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1) 
+        begin : gen_rmw_data_merge
+
+            always @ (*) 
+            begin
+                if (wdatap_dataread_buffer_dm[wdatap_i])
+                begin
+                    // data from wdatap buffer
+                    rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
+                end
+                else
+                begin
+                    // data from rmwfifo
+                    if (CFG_WDATA_REG)
+                    begin
+                        rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data_r [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
+                    end
+                    else
+                    begin
+                        rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data   [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
+                    end
+                end
+            end
+
+        end
+    endgenerate
+
+    //
+    // wdata output mux
+    //
+    // drives wdatap_data & wdatap_be from either of
+    // if cfg_enabled etc ?
+    // - wdatap buffer                      (~rmw_correct & ~rmw_partial)
+    // - rmwfifo                            (rmw_correct)
+    // - merged wdatap buffer & rmwfifo     (rmw_partial)
+    //
+
+    generate
+        if (CFG_WDATA_REG)
+        begin
+            always @ (*)
+            begin
+                if (cfg_enable_ecc | cfg_enable_no_dm)
+                begin
+                    wdatap_dataread_data             = wdatap_dataread_buffer_data;
+                    wdatap_dataread_rmw_partial_data = rmw_merged_data;
+                    wdatap_dataread_rmw_correct_data = rmwfifo_output_data_r;
+                    wdatap_dataread_rmw_partial      = rmw_partial_r2;
+                    wdatap_dataread_rmw_correct      = rmw_correct_r2;
+                    
+                    if (rmw_correct_r2 | rmw_partial_r2)
+                    begin
+                        wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
+                    end
+                    else
+                    begin
+                        wdatap_dataread_dm = wdatap_dataread_buffer_dm;
+                    end
+                end
+                else
+                begin
+                    wdatap_dataread_dm               = wdatap_dataread_buffer_dm;
+                    wdatap_dataread_data             = wdatap_dataread_buffer_data;
+                    wdatap_dataread_rmw_partial_data = 0;
+                    wdatap_dataread_rmw_correct_data = 0;
+                    wdatap_dataread_rmw_partial      = 1'b0;
+                    wdatap_dataread_rmw_correct      = 1'b0;
+                end
+            end
+            
+            // ecc code overwrite
+            // - is asserted when we don't want controller to re-calculate the ecc code
+            // - only allowed when we're not doing any writes in this clock
+            // - only allowed when rmwfifo output is valid
+            always @ (posedge ctl_clk or negedge ctl_reset_n)
+            begin
+                if (!ctl_reset_n)
+                begin
+                    wdatap_ecc_code           <= 0;
+                    wdatap_ecc_code_overwrite <= 0;
+                end
+                else
+                begin
+                    wdatap_ecc_code <= rmwfifo_output_ecc_code;
+                    
+                    if (cfg_enable_ecc_code_overwrites)
+                    begin
+                        if (rmw_correct_r1)
+                        begin
+                            wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
+                        end
+                        else if (rmw_partial_r1)
+                        begin
+                            if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
+                            begin
+                                wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
+                            end
+                            else
+                            begin
+                                wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
+                            end
+                        end
+                        else
+                        begin
+                            wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
+                        end
+                    end
+                    else
+                    begin
+                        wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
+                    end
+                end
+            end
+        end
+        else
+        begin
+            always @ (*)
+            begin
+                if (cfg_enable_ecc | cfg_enable_no_dm)
+                begin
+                    wdatap_dataread_data             = wdatap_dataread_buffer_data;
+                    wdatap_dataread_rmw_partial_data = rmw_merged_data;
+                    wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
+                    wdatap_dataread_rmw_partial      = rmw_partial_r1;
+                    wdatap_dataread_rmw_correct      = rmw_correct_r1;
+                    
+                    if (rmw_correct_r1 | rmw_partial_r1)
+                    begin
+                        wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
+                    end
+                    else
+                    begin
+                        wdatap_dataread_dm = wdatap_dataread_buffer_dm;
+                    end
+                end
+                else
+                begin
+                    wdatap_dataread_dm               = wdatap_dataread_buffer_dm;
+                    wdatap_dataread_data             = wdatap_dataread_buffer_data;
+                    wdatap_dataread_rmw_partial_data = 0;
+                    wdatap_dataread_rmw_correct_data = 0;
+                    wdatap_dataread_rmw_partial      = 1'b0;
+                    wdatap_dataread_rmw_correct      = 1'b0;
+                end
+            end
+            
+            // ecc code overwrite
+            // - is asserted when we don't want controller to re-calculate the ecc code
+            // - only allowed when we're not doing any writes in this clock
+            // - only allowed when rmwfifo output is valid
+            always @ (*)
+            begin
+                wdatap_ecc_code         = rmwfifo_output_ecc_code;
+                
+                if (cfg_enable_ecc_code_overwrites)
+                begin
+                    if (rmw_correct_r1)
+                    begin
+                        wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
+                    end
+                    else if (rmw_partial_r1)
+                    begin
+                        if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
+                        begin
+                            wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
+                        end
+                        else
+                        begin
+                            wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
+                        end
+                    end
+                    else
+                    begin
+                        wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
+                    end
+                end
+                else
+                begin
+                    wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
+                end
+            end
+        end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
new file mode 100644
index 0000000..3559af0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv
@@ -0,0 +1,535 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_nextgen_ddr3_controller_core; -name IP_TOOL_VERSION 19.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *)
+module alt_mem_if_nextgen_ddr3_controller_core (
+    afi_clk,
+    afi_reset_n,
+    afi_half_clk,
+
+    itf_cmd_ready,
+    itf_cmd_valid,
+    itf_cmd,
+    itf_cmd_address,
+    itf_cmd_burstlen,
+    itf_cmd_id,
+    itf_cmd_priority,
+    itf_cmd_autopercharge,
+    itf_cmd_multicast,
+    itf_wr_data_ready,
+    itf_wr_data_valid,
+    itf_wr_data,
+    itf_wr_data_byte_en,
+    itf_wr_data_begin,
+    itf_wr_data_last,
+    itf_wr_data_id,
+    itf_rd_data_ready,
+    itf_rd_data_valid,
+    itf_rd_data,
+    itf_rd_data_error,
+    itf_rd_data_begin,
+    itf_rd_data_last,
+    itf_rd_data_id,
+    afi_rst_n, 
+    afi_cs_n,
+    afi_cke,
+    afi_odt,
+    afi_addr,
+    afi_ba,
+    afi_ras_n,
+    afi_cas_n,
+    afi_we_n,
+    afi_dqs_burst,
+    afi_wdata_valid,
+    afi_wdata,
+    afi_dm,
+    afi_wlat,
+    afi_rdata_en,
+    afi_rdata_en_full,
+    afi_rrank,
+    afi_wrank,
+    afi_rdata,
+    afi_rdata_valid,
+    afi_rlat,
+    afi_cal_success,
+    afi_cal_fail,
+    afi_cal_req,
+    afi_init_req,
+	afi_mem_clk_disable,
+    afi_ctl_refresh_done,
+    afi_seq_busy,
+    afi_ctl_long_idle,
+    local_refresh_ack,
+    local_powerdn_ack,
+    local_self_rfsh_ack,
+    local_deep_powerdn_ack,
+    local_refresh_req,
+    local_refresh_chip,
+    local_self_rfsh_req,
+    local_self_rfsh_chip,
+    local_deep_powerdn_req,
+    local_deep_powerdn_chip,
+    local_zqcal_req,
+    local_zqcal_chip,
+    local_multicast,
+    local_priority,
+    local_init_done,
+    local_cal_success,
+    local_cal_fail,
+    ecc_interrupt,
+    csr_read_req,
+    csr_write_req,
+    csr_addr,
+    csr_wdata,
+    csr_rdata,
+    csr_be,
+    csr_rdata_valid,
+    csr_waitrequest,
+    tbp_empty,
+    cmd_gen_busy,
+    sideband_in_refresh
+);
+
+
+    parameter   AVL_SIZE_WIDTH                      = 0;
+    parameter   AVL_ADDR_WIDTH                      = 0;
+    parameter   AVL_DATA_WIDTH                      = 0;
+    parameter   LOCAL_ID_WIDTH                      = 0;
+    parameter   AVL_BE_WIDTH                        = 0;
+    parameter   LOCAL_CS_WIDTH                      = 0;
+    parameter   MEM_IF_ADDR_WIDTH                   = 0;
+    parameter   MEM_IF_CLK_PAIR_COUNT               = 0;
+    parameter   LOCAL_IF_TYPE                       = "AVALON";
+    parameter   DWIDTH_RATIO                        = 0;
+    parameter   CTL_ODT_ENABLED                     = 0;
+    parameter   CTL_OUTPUT_REGD                     = 0;
+    parameter   CTL_TBP_NUM                         = 0;
+    parameter   WRBUFFER_ADDR_WIDTH                 = 0;
+    parameter   RDBUFFER_ADDR_WIDTH                 = 0;
+    parameter   MAX_PENDING_RD_CMD                  = 0;
+    parameter   MAX_PENDING_WR_CMD                  = 0;
+    parameter   MEM_IF_CS_WIDTH                     = 0;
+    parameter   MEM_IF_CHIP_BITS                    = 0;
+    parameter   MEM_IF_BANKADDR_WIDTH               = 0;
+    parameter   MEM_IF_ROW_ADDR_WIDTH               = 0;
+    parameter   MEM_IF_COL_ADDR_WIDTH               = 0;
+    parameter   MEM_IF_ODT_WIDTH                    = 0;
+    parameter   MEM_IF_CLK_EN_WIDTH                 = 0;
+    parameter   MEM_IF_DQS_WIDTH                    = 0;
+    parameter   MEM_IF_DQ_WIDTH                     = 0;
+    parameter   MEM_IF_DM_WIDTH                     = 0;
+
+    parameter   MAX_MEM_IF_CS_WIDTH                 = 30;
+    parameter   MAX_MEM_IF_CHIP                     = 4;
+    parameter   MAX_MEM_IF_BANKADDR_WIDTH           = 3;
+    parameter   MAX_MEM_IF_ROWADDR_WIDTH            = 16;
+    parameter   MAX_MEM_IF_COLADDR_WIDTH            = 12;
+    parameter   MAX_MEM_IF_ODT_WIDTH                = 1;
+    parameter   MAX_MEM_IF_DQS_WIDTH                = 5;
+    parameter   MAX_MEM_IF_DQ_WIDTH                 = 40;
+    parameter   MAX_MEM_IF_MASK_WIDTH               = 5;
+    parameter   MAX_LOCAL_DATA_WIDTH                = 80;
+
+    parameter   CFG_TYPE                            = 0;
+    parameter   CFG_INTERFACE_WIDTH                 = 0;
+    parameter   CFG_BURST_LENGTH                    = 0;
+    parameter   CFG_REORDER_DATA                    = 0;
+    parameter   CFG_DATA_REORDERING_TYPE            = "INTER_ROW";
+    parameter   CFG_STARVE_LIMIT                    = 0;
+    parameter   CFG_ADDR_ORDER                      = 0;
+
+    parameter   MEM_WTCL_INT                        = 0;
+    parameter   MEM_ADD_LAT                         = 0;
+    parameter   MEM_TCL                             = 0;
+    parameter   MEM_TRRD                            = 0;
+    parameter   MEM_TFAW                            = 0;
+    parameter   MEM_TRFC                            = 0;
+    parameter   MEM_TREFI                           = 0;
+    parameter   MEM_TRCD                            = 0;
+    parameter   MEM_TRP                             = 0;
+    parameter   MEM_TWR                             = 0;
+    parameter   MEM_TWTR                            = 0;
+    parameter   MEM_TRTP                            = 0;
+    parameter   MEM_TRAS                            = 0;
+    parameter   MEM_TRC                             = 0;
+    parameter   CFG_TCCD                            = 2;
+    parameter   MEM_AUTO_PD_CYCLES                  = 0;
+    parameter   MEM_IF_RD_TO_WR_TURNAROUND_OCT      = 0;
+    parameter   MEM_IF_WR_TO_RD_TURNAROUND_OCT      = 0;
+    parameter   CTL_RD_TO_PCH_EXTRA_CLK             = 0;
+    parameter   CTL_RD_TO_RD_EXTRA_CLK              = 0;
+    parameter   CTL_WR_TO_WR_EXTRA_CLK              = 0;
+    parameter   CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK    = 0;
+    parameter   CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK    = 0;
+
+    parameter   AFI_ADDR_WIDTH                      = 0;
+    parameter   AFI_BANKADDR_WIDTH                  = 0;
+    parameter   AFI_CONTROL_WIDTH                   = 0;
+    parameter   AFI_CS_WIDTH                        = 0;
+    parameter   AFI_CLK_EN_WIDTH                    = 0;
+    parameter   AFI_ODT_WIDTH                       = 0;
+    parameter   AFI_DM_WIDTH                        = 0;
+    parameter   AFI_DQ_WIDTH                        = 0;
+    parameter   AFI_WRITE_DQS_WIDTH                 = 0;
+    parameter   AFI_RATE_RATIO                      = 0;
+    parameter   AFI_WLAT_WIDTH                      = 0;
+    parameter   AFI_RLAT_WIDTH                      = 0;
+    parameter   AFI_RRANK_WIDTH                     = 0;
+    parameter   AFI_WRANK_WIDTH                     = 0;
+
+    parameter   USE_SHADOW_REGS                     = 0;
+    parameter   CFG_SELF_RFSH_EXIT_CYCLES           = 0;
+    parameter   CFG_PDN_EXIT_CYCLES                 = 0;
+    parameter   CFG_POWER_SAVING_EXIT_CYCLES        = 0;
+    parameter   CFG_MEM_CLK_ENTRY_CYCLES            = 0;
+    parameter   MEM_TMRD_CK                         = 0;
+    parameter   CTL_ECC_ENABLED                     = 0;
+    parameter   CTL_ECC_AUTO_CORRECTION_ENABLED     = 0;
+    parameter   CTL_ECC_MULTIPLES_16_24_40_72       = 1;
+    parameter   CTL_ENABLE_BURST_INTERRUPT_INT      = 0;
+    parameter   CTL_ENABLE_BURST_TERMINATE_INT      = 0;
+    parameter   CTL_ENABLE_WDATA_PATH_LATENCY       = 0;
+    parameter   CFG_GEN_SBE                         = 0;
+    parameter   CFG_GEN_DBE                         = 0;
+    parameter   CFG_ENABLE_INTR                     = 0;
+    parameter   CFG_MASK_SBE_INTR                   = 0;
+    parameter   CFG_MASK_DBE_INTR                   = 0;
+    parameter   CFG_MASK_CORRDROP_INTR              = 0;
+    parameter   CFG_CLR_INTR                        = 0;
+    parameter   CTL_USR_REFRESH                     = 0;
+    parameter   CTL_REGDIMM_ENABLED                 = 0;
+    parameter   CFG_WRITE_ODT_CHIP                  = 0;
+    parameter   CFG_READ_ODT_CHIP                   = 0;
+    parameter   CFG_PORT_WIDTH_WRITE_ODT_CHIP       = 0;
+    parameter   CFG_PORT_WIDTH_READ_ODT_CHIP        = 0;
+    parameter   MEM_IF_CKE_WIDTH                    = 0;
+    parameter   CFG_ENABLE_NO_DM                    = 0;
+    parameter   CSR_BE_WIDTH                        = 4;
+
+    parameter CTL_CSR_ENABLED                       = 0;
+    parameter CSR_ADDR_WIDTH                        = 8;
+    parameter CSR_DATA_WIDTH                        = 32;
+  
+    parameter CFG_ERRCMD_FIFO_REG                   = 0;
+    parameter CFG_ECC_DECODER_REG                   = 0; 
+    parameter CTL_CS_WIDTH                          = 0;
+    parameter USE_DQS_TRACKING                      = 0;
+    parameter ENABLE_BURST_MERGE                    = 0;
+
+    parameter CONTINUE_AFTER_CAL_FAIL               = 0;
+    parameter MAX10_CFG                         = 0;
+
+localparam AFI_RDATA_EN_WIDTH                        = (MEM_IF_DQS_WIDTH * (DWIDTH_RATIO / 2));
+
+
+input                                                   afi_clk;
+input                                                   afi_reset_n;
+input                                                   afi_half_clk;
+
+output                                                  itf_cmd_ready;
+input                                                   itf_cmd_valid;
+input                                                   itf_cmd;
+input   [AVL_ADDR_WIDTH                     - 1 : 0]    itf_cmd_address;
+input   [AVL_SIZE_WIDTH                     - 1 : 0]    itf_cmd_burstlen;
+input   [LOCAL_ID_WIDTH                     - 1 : 0]    itf_cmd_id;
+input                                                   itf_cmd_priority;
+input                                                   itf_cmd_autopercharge;
+input                                                   itf_cmd_multicast;
+output                                                  itf_wr_data_ready;
+input                                                   itf_wr_data_valid;
+input   [AVL_DATA_WIDTH                     - 1 : 0]    itf_wr_data;
+input   [AVL_BE_WIDTH                       - 1 : 0]    itf_wr_data_byte_en;
+input                                                   itf_wr_data_begin;
+input                                                   itf_wr_data_last;
+input   [LOCAL_ID_WIDTH                     - 1 : 0]    itf_wr_data_id;
+input                                                   itf_rd_data_ready;
+output                                                  itf_rd_data_valid;
+output  [AVL_DATA_WIDTH                     - 1 : 0]    itf_rd_data;
+output                                                  itf_rd_data_error;
+output                                                  itf_rd_data_begin;
+output                                                  itf_rd_data_last;
+output  [LOCAL_ID_WIDTH                     - 1 : 0]    itf_rd_data_id;
+
+output  [AFI_CONTROL_WIDTH                  - 1 : 0]    afi_rst_n; 
+output  [AFI_CS_WIDTH                       - 1 : 0]    afi_cs_n;
+output  [AFI_CLK_EN_WIDTH                   - 1 : 0]    afi_cke;
+output  [AFI_ODT_WIDTH                      - 1 : 0]    afi_odt;
+output  [AFI_ADDR_WIDTH                     - 1 : 0]    afi_addr;
+output  [AFI_BANKADDR_WIDTH                 - 1 : 0]    afi_ba;
+output  [AFI_CONTROL_WIDTH                  - 1 : 0]    afi_ras_n;
+output  [AFI_CONTROL_WIDTH                  - 1 : 0]    afi_cas_n;
+output  [AFI_CONTROL_WIDTH                  - 1 : 0]    afi_we_n;
+output  [AFI_WRITE_DQS_WIDTH                - 1 : 0]    afi_dqs_burst;
+output  [AFI_WRITE_DQS_WIDTH                - 1 : 0]    afi_wdata_valid;
+output  [AFI_DQ_WIDTH                       - 1 : 0]    afi_wdata;
+output  [AFI_DM_WIDTH                       - 1 : 0]    afi_dm;
+input   [AFI_WLAT_WIDTH                     - 1 : 0]    afi_wlat;
+output  [AFI_RATE_RATIO                     - 1 : 0]    afi_rdata_en;
+wire	[AFI_RDATA_EN_WIDTH		    - 1 : 0]	int_afi_rdata_en;
+output  [AFI_RATE_RATIO                     - 1 : 0]    afi_rdata_en_full;
+wire	[AFI_RDATA_EN_WIDTH 		    - 1 : 0]	int_afi_rdata_en_full;
+output  [AFI_RRANK_WIDTH                    - 1 : 0]    afi_rrank;
+output  [AFI_WRANK_WIDTH                    - 1 : 0]    afi_wrank;
+input   [AFI_DQ_WIDTH                       - 1 : 0]    afi_rdata;
+input   [AFI_RATE_RATIO                     - 1 : 0]    afi_rdata_valid;
+input   [AFI_RLAT_WIDTH                     - 1 : 0]    afi_rlat;
+input                                                   afi_cal_success;
+input                                                   afi_cal_fail;
+output                                                  afi_cal_req;
+output                                                  afi_init_req;
+output  [MEM_IF_CLK_PAIR_COUNT              - 1 : 0]    afi_mem_clk_disable;
+
+wire    [(MEM_IF_DQS_WIDTH*CTL_CS_WIDTH)  - 1 : 0]    afi_cal_byte_lane_sel_n;
+output  [MEM_IF_CS_WIDTH                  - 1 : 0]    afi_ctl_refresh_done;
+input   [MEM_IF_CS_WIDTH                  - 1 : 0]    afi_seq_busy;
+output  [MEM_IF_CS_WIDTH                  - 1 : 0]    afi_ctl_long_idle;
+
+output                                                  local_refresh_ack;
+output                                                  local_powerdn_ack;
+output                                                  local_self_rfsh_ack;
+output                                                  local_deep_powerdn_ack;
+input                                                   local_refresh_req;
+input   [CTL_CS_WIDTH                       - 1 : 0]    local_refresh_chip;
+input                                                   local_self_rfsh_req;
+input   [CTL_CS_WIDTH                       - 1 : 0]    local_self_rfsh_chip;
+input                                                   local_deep_powerdn_req;
+input   [CTL_CS_WIDTH                       - 1 : 0]    local_deep_powerdn_chip;
+input                                                   local_zqcal_req;
+input   [CTL_CS_WIDTH                       - 1 : 0]    local_zqcal_chip;
+input                                                   local_multicast;
+input                                                   local_priority;
+
+output                                                  local_init_done;
+output                                                  local_cal_success;
+output                                                  local_cal_fail;
+
+output                                                  ecc_interrupt;
+input                                                   csr_read_req;
+input                                                   csr_write_req;
+input   [CSR_ADDR_WIDTH                     - 1 : 0]    csr_addr;
+input   [CSR_DATA_WIDTH                     - 1 : 0]    csr_wdata;
+output  [CSR_DATA_WIDTH                     - 1 : 0]    csr_rdata;
+input   [CSR_BE_WIDTH                       - 1 : 0]    csr_be;
+output                                                  csr_rdata_valid;
+output                                                  csr_waitrequest;
+
+	output	tbp_empty;
+	output	cmd_gen_busy;
+	output sideband_in_refresh;
+
+alt_mem_ddrx_controller_st_top # (
+    .LOCAL_SIZE_WIDTH                   ( AVL_SIZE_WIDTH                     ),
+    .LOCAL_ADDR_WIDTH                   ( AVL_ADDR_WIDTH                     ),
+    .LOCAL_DATA_WIDTH                   ( AVL_DATA_WIDTH                     ),
+    .LOCAL_BE_WIDTH                     ( AVL_BE_WIDTH                       ),
+    .LOCAL_ID_WIDTH                     ( LOCAL_ID_WIDTH                     ),
+    .LOCAL_CS_WIDTH                     ( LOCAL_CS_WIDTH                     ),
+    .MEM_IF_ADDR_WIDTH                  ( MEM_IF_ADDR_WIDTH                  ),
+    .MEM_IF_CLK_PAIR_COUNT              ( MEM_IF_CLK_PAIR_COUNT              ),
+    .LOCAL_IF_TYPE                      ( LOCAL_IF_TYPE                      ),
+    .DWIDTH_RATIO                       ( DWIDTH_RATIO                       ),
+    .CTL_ODT_ENABLED                    ( CTL_ODT_ENABLED                    ),
+    .CTL_OUTPUT_REGD                    ( CTL_OUTPUT_REGD                    ),
+    .CTL_TBP_NUM                        ( CTL_TBP_NUM                        ),
+    .WRBUFFER_ADDR_WIDTH                ( WRBUFFER_ADDR_WIDTH                ),
+    .RDBUFFER_ADDR_WIDTH                ( RDBUFFER_ADDR_WIDTH                ),
+    .MAX_PENDING_RD_CMD                 ( MAX10_CFG ? 16 : MAX_PENDING_RD_CMD                 ),
+    .MAX_PENDING_WR_CMD                 ( MAX10_CFG ? 8  : MAX_PENDING_WR_CMD                 ),
+    .MEM_IF_CS_WIDTH                    ( MEM_IF_CHIP_BITS                   ),
+    .MEM_IF_CHIP                        ( CTL_CS_WIDTH                       ),
+    .MEM_IF_BANKADDR_WIDTH              ( MEM_IF_BANKADDR_WIDTH              ),
+    .MEM_IF_ROW_WIDTH                   ( MEM_IF_ROW_ADDR_WIDTH              ),
+    .MEM_IF_COL_WIDTH                   ( MEM_IF_COL_ADDR_WIDTH              ),
+    .MEM_IF_ODT_WIDTH                   ( MEM_IF_ODT_WIDTH                   ),
+    .MEM_IF_DQS_WIDTH                   ( MEM_IF_DQS_WIDTH                   ),
+    .MEM_IF_DWIDTH                      ( MEM_IF_DQ_WIDTH                    ),
+    .MEM_IF_DM_WIDTH                    ( MEM_IF_DM_WIDTH                    ),
+    .MAX_MEM_IF_CS_WIDTH                ( MAX_MEM_IF_CS_WIDTH                ),
+    .MAX_MEM_IF_CHIP                    ( MAX_MEM_IF_CHIP                    ),
+    .MAX_MEM_IF_BANKADDR_WIDTH          ( MAX_MEM_IF_BANKADDR_WIDTH          ),
+    .MAX_MEM_IF_ROWADDR_WIDTH           ( MAX_MEM_IF_ROWADDR_WIDTH           ),
+    .MAX_MEM_IF_COLADDR_WIDTH           ( MAX_MEM_IF_COLADDR_WIDTH           ),
+    .MAX_MEM_IF_ODT_WIDTH               ( MAX_MEM_IF_ODT_WIDTH               ),
+    .MAX_MEM_IF_DQS_WIDTH               ( MAX_MEM_IF_DQS_WIDTH               ),
+    .MAX_MEM_IF_DQ_WIDTH                ( MAX_MEM_IF_DQ_WIDTH                ),
+    .MAX_MEM_IF_MASK_WIDTH              ( MAX_MEM_IF_MASK_WIDTH              ),
+    .MAX_LOCAL_DATA_WIDTH               ( MAX_LOCAL_DATA_WIDTH               ),
+    .CFG_TYPE                           ( CFG_TYPE                           ),
+    .CFG_INTERFACE_WIDTH                ( CFG_INTERFACE_WIDTH                ),
+    .CFG_BURST_LENGTH                   ( CFG_BURST_LENGTH                   ),
+    .CFG_DEVICE_WIDTH                   ( MEM_IF_DQS_WIDTH                   ),
+    .CFG_REORDER_DATA                   ( CFG_REORDER_DATA                   ),
+    .CFG_DATA_REORDERING_TYPE           ( CFG_DATA_REORDERING_TYPE           ),
+    .CFG_STARVE_LIMIT                   ( CFG_STARVE_LIMIT                   ),
+    .CFG_ADDR_ORDER                     ( CFG_ADDR_ORDER                     ),
+    .MEM_CAS_WR_LAT                     ( MEM_WTCL_INT                       ),
+    .MEM_ADD_LAT                        ( MEM_ADD_LAT                        ),
+    .MEM_TCL                            ( MEM_TCL                            ),
+    .MEM_TRRD                           ( MEM_TRRD                           ),
+    .MEM_TFAW                           ( MEM_TFAW                           ),
+    .MEM_TRFC                           ( MEM_TRFC                           ),
+    .MEM_TREFI                          ( MEM_TREFI                          ),
+    .MEM_TRCD                           ( MEM_TRCD                           ),
+    .MEM_TRP                            ( MEM_TRP                            ),
+    .MEM_TWR                            ( MEM_TWR                            ),
+    .MEM_TWTR                           ( MEM_TWTR                           ),
+    .MEM_TRTP                           ( MEM_TRTP                           ),
+    .MEM_TRAS                           ( MEM_TRAS                           ),
+    .MEM_TRC                            ( MEM_TRC                            ),
+    .CFG_TCCD                           ( CFG_TCCD                           ),
+    .MEM_AUTO_PD_CYCLES                 ( MEM_AUTO_PD_CYCLES                 ),
+    .MEM_IF_RD_TO_WR_TURNAROUND_OCT     ( MEM_IF_RD_TO_WR_TURNAROUND_OCT     ),
+    .MEM_IF_WR_TO_RD_TURNAROUND_OCT     ( MEM_IF_WR_TO_RD_TURNAROUND_OCT     ),
+    .CTL_RD_TO_PCH_EXTRA_CLK            ( CTL_RD_TO_PCH_EXTRA_CLK            ),
+    .CTL_RD_TO_RD_EXTRA_CLK             ( CTL_RD_TO_RD_EXTRA_CLK             ),
+    .CTL_WR_TO_WR_EXTRA_CLK             ( CTL_WR_TO_WR_EXTRA_CLK             ),
+    .CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK   ( CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK   ),
+    .CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK   ( CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK   ),
+    .CFG_SELF_RFSH_EXIT_CYCLES          ( CFG_SELF_RFSH_EXIT_CYCLES          ),
+    .CFG_PDN_EXIT_CYCLES                ( CFG_PDN_EXIT_CYCLES                ),
+    .CFG_POWER_SAVING_EXIT_CYCLES       ( CFG_POWER_SAVING_EXIT_CYCLES       ),
+    .CFG_MEM_CLK_ENTRY_CYCLES           ( CFG_MEM_CLK_ENTRY_CYCLES           ),
+    .MEM_TMRD_CK                        ( MEM_TMRD_CK                        ),
+    .CTL_ECC_ENABLED                    ( CTL_ECC_ENABLED                    ),
+    .CTL_ECC_RMW_ENABLED                ( CTL_ECC_AUTO_CORRECTION_ENABLED    ),
+    .CTL_ECC_MULTIPLES_16_24_40_72      ( CTL_ECC_MULTIPLES_16_24_40_72      ),
+    .CTL_ENABLE_BURST_INTERRUPT         ( CTL_ENABLE_BURST_INTERRUPT_INT     ),
+    .CTL_ENABLE_BURST_TERMINATE         ( CTL_ENABLE_BURST_TERMINATE_INT     ),
+    .CTL_ENABLE_WDATA_PATH_LATENCY      ( CTL_ENABLE_WDATA_PATH_LATENCY      ),
+    .ENABLE_BURST_MERGE                 ( ENABLE_BURST_MERGE      ),    
+    .CFG_GEN_SBE                        ( CFG_GEN_SBE                        ),
+    .CFG_GEN_DBE                        ( CFG_GEN_DBE                        ),
+    .CFG_ENABLE_INTR                    ( CFG_ENABLE_INTR                    ),
+    .CFG_MASK_SBE_INTR                  ( CFG_MASK_SBE_INTR                  ),
+    .CFG_MASK_DBE_INTR                  ( CFG_MASK_DBE_INTR                  ),
+    .CFG_MASK_CORRDROP_INTR             ( CFG_MASK_CORRDROP_INTR             ),
+    .CFG_CLR_INTR                       ( CFG_CLR_INTR                       ),
+    .CTL_USR_REFRESH                    ( CTL_USR_REFRESH                    ),
+    .CTL_REGDIMM_ENABLED                ( CTL_REGDIMM_ENABLED                ),
+    .CFG_WRITE_ODT_CHIP                 ( CFG_WRITE_ODT_CHIP                 ),
+    .CFG_READ_ODT_CHIP                  ( CFG_READ_ODT_CHIP                  ),
+    .CFG_PORT_WIDTH_WRITE_ODT_CHIP      ( CFG_PORT_WIDTH_WRITE_ODT_CHIP      ),
+    .CFG_PORT_WIDTH_READ_ODT_CHIP       ( CFG_PORT_WIDTH_READ_ODT_CHIP       ),
+    .MEM_IF_CKE_WIDTH                   ( MEM_IF_CLK_EN_WIDTH                ),
+    .CFG_ENABLE_NO_DM                   ( CFG_ENABLE_NO_DM                   ),
+    .CTL_CSR_ENABLED                    ( MAX10_CFG ? 0 : CTL_CSR_ENABLED),
+    .CSR_ADDR_WIDTH                     ( CSR_ADDR_WIDTH                     ),
+    .CSR_DATA_WIDTH                     ( CSR_DATA_WIDTH                     ),
+    .CSR_BE_WIDTH                       ( CSR_BE_WIDTH                       ),
+    .CFG_ENABLE_DQS_TRACKING            ( USE_DQS_TRACKING                   ),
+    .CFG_WLAT_BUS_WIDTH                 ( AFI_WLAT_WIDTH                     ),
+    .CFG_RLAT_BUS_WIDTH                 ( AFI_RLAT_WIDTH                     ),
+    .CFG_RRANK_BUS_WIDTH                ( AFI_RRANK_WIDTH                    ),
+    .CFG_WRANK_BUS_WIDTH                ( AFI_WRANK_WIDTH                    ),
+    .CFG_USE_SHADOW_REGS                ( USE_SHADOW_REGS                    ),
+    .CFG_ECC_DECODER_REG		( CFG_ECC_DECODER_REG		     ),
+    .CFG_ERRCMD_FIFO_REG		( CFG_ERRCMD_FIFO_REG		     )
+
+) alt_mem_ddrx_controller_top_inst (
+    .clk                                ( afi_clk                            ),
+    .half_clk                           ( afi_half_clk                       ),
+    .reset_n                            ( afi_reset_n                        ),
+    .itf_cmd_ready                      ( itf_cmd_ready                      ),
+    .itf_cmd_valid                      ( itf_cmd_valid                      ),
+    .itf_cmd                            ( itf_cmd                            ),
+    .itf_cmd_address                    ( itf_cmd_address                    ),
+    .itf_cmd_burstlen                   ( itf_cmd_burstlen                   ),
+    .itf_cmd_id                         ( itf_cmd_id                         ),
+    .itf_cmd_priority                   ( itf_cmd_priority                   ),
+    .itf_cmd_autopercharge              ( itf_cmd_autopercharge              ), 
+    .itf_cmd_multicast                  ( itf_cmd_multicast                  ),
+    .itf_wr_data_ready                  ( itf_wr_data_ready                  ),
+    .itf_wr_data_valid                  ( itf_wr_data_valid                  ),
+    .itf_wr_data                        ( itf_wr_data                        ),
+    .itf_wr_data_byte_en                ( itf_wr_data_byte_en                ),
+    .itf_wr_data_begin                  ( itf_wr_data_begin                  ),
+    .itf_wr_data_last                   ( itf_wr_data_last                   ),
+    .itf_wr_data_id                     ( itf_wr_data_id                     ),
+    .itf_rd_data_ready                  ( itf_rd_data_ready                  ),
+    .itf_rd_data_valid                  ( itf_rd_data_valid                  ),
+    .itf_rd_data                        ( itf_rd_data                        ),
+    .itf_rd_data_error                  ( itf_rd_data_error                  ),
+    .itf_rd_data_begin                  ( itf_rd_data_begin                  ),
+    .itf_rd_data_last                   ( itf_rd_data_last                   ),
+    .itf_rd_data_id                     ( itf_rd_data_id                     ),
+    .afi_rst_n                          ( afi_rst_n                          ), 
+    .afi_cs_n                           ( afi_cs_n                           ),
+    .afi_cke                            ( afi_cke                            ),
+    .afi_odt                            ( afi_odt                            ),
+    .afi_addr                           ( afi_addr                           ),
+    .afi_ba                             ( afi_ba                             ),
+    .afi_ras_n                          ( afi_ras_n                          ),
+    .afi_cas_n                          ( afi_cas_n                          ),
+    .afi_we_n                           ( afi_we_n                           ),
+    .afi_dqs_burst                      ( afi_dqs_burst                      ),
+    .afi_wdata_valid                    ( afi_wdata_valid                    ),
+    .afi_wdata                          ( afi_wdata                          ),
+    .afi_dm                             ( afi_dm                             ),
+    .afi_wlat                           ( afi_wlat                           ),
+    .afi_rdata_en                       ( int_afi_rdata_en                   ),
+    .afi_rdata_en_full                  ( int_afi_rdata_en_full              ),
+    .afi_rrank                          ( afi_rrank                          ),
+    .afi_wrank                          ( afi_wrank                          ),
+    .afi_rdata                          ( afi_rdata                          ),
+    .afi_rdata_valid                    ( afi_rdata_valid                    ),
+    .afi_rlat                           ( afi_rlat                           ),
+    .afi_cal_success                    ( CONTINUE_AFTER_CAL_FAIL ? (afi_cal_success | afi_cal_fail) : afi_cal_success ),
+    .afi_cal_fail                       ( CONTINUE_AFTER_CAL_FAIL ? 1'b0 : afi_cal_fail ),
+    .afi_cal_req                        ( afi_cal_req                        ),
+    .afi_init_req                       ( afi_init_req                       ),
+    .afi_mem_clk_disable                ( afi_mem_clk_disable                ),
+    .afi_cal_byte_lane_sel_n            ( afi_cal_byte_lane_sel_n            ),
+    .afi_ctl_refresh_done               ( afi_ctl_refresh_done               ),
+    .afi_seq_busy                       ( afi_seq_busy                       ),
+    .afi_ctl_long_idle                  ( afi_ctl_long_idle                  ),
+    .local_init_done                    ( local_init_done                    ),
+    .local_refresh_ack                  ( local_refresh_ack                  ),
+    .local_powerdn_ack                  ( local_powerdn_ack                  ),
+    .local_self_rfsh_ack                ( local_self_rfsh_ack                ),
+    .local_deep_powerdn_ack             ( local_deep_powerdn_ack             ),
+    .local_refresh_req                  ( local_refresh_req                  ),
+    .local_refresh_chip                 ( local_refresh_chip                 ),
+    .local_powerdn_req                  (                                    ),
+    .local_self_rfsh_req                ( local_self_rfsh_req                ),
+    .local_self_rfsh_chip               ( local_self_rfsh_chip               ),
+    .local_deep_powerdn_req             ( local_deep_powerdn_req             ),
+    .local_deep_powerdn_chip            ( local_deep_powerdn_chip            ),
+    .local_zqcal_req                    ( local_zqcal_req                    ),
+    .local_zqcal_chip                   ( local_zqcal_chip                   ),
+    .local_multicast                    ( local_multicast                    ),
+    .local_priority                     ( local_priority                     ),
+    .ecc_interrupt                      ( ecc_interrupt                      ),
+    .csr_read_req                       ( csr_read_req                       ),
+    .csr_write_req                      ( csr_write_req                      ),
+    .csr_burst_count                    ( 1'b1                               ),
+    .csr_beginbursttransfer             (                                    ),
+    .csr_addr                           ( csr_addr                           ),
+    .csr_wdata                          ( csr_wdata                          ),
+    .csr_rdata                          ( csr_rdata                          ),
+    .csr_be                             ( csr_be                             ),
+    .csr_rdata_valid                    ( csr_rdata_valid                    ),
+    .csr_waitrequest                    ( csr_waitrequest                    ),
+    .tbp_empty                          ( tbp_empty                          ),
+    .cmd_gen_busy                       ( cmd_gen_busy                       ),
+    .sideband_in_refresh                ( sideband_in_refresh                )
+);
+
+assign afi_rdata_en = int_afi_rdata_en[AFI_RATE_RATIO-1:0];
+assign afi_rdata_en_full = int_afi_rdata_en_full[AFI_RATE_RATIO-1:0];
+assign local_cal_success = afi_cal_success;
+assign local_cal_fail = afi_cal_fail;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
new file mode 100644
index 0000000..cf8576a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v
@@ -0,0 +1,915 @@
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+    // --------------------------------------------------
+    // Parameters
+    // --------------------------------------------------
+    parameter SYMBOLS_PER_BEAT  = 1,
+    parameter BITS_PER_SYMBOL   = 8,
+    parameter FIFO_DEPTH        = 16,
+    parameter CHANNEL_WIDTH     = 0,
+    parameter ERROR_WIDTH       = 0,
+    parameter USE_PACKETS       = 0,
+    parameter USE_FILL_LEVEL    = 0,
+    parameter USE_STORE_FORWARD = 0,
+    parameter USE_ALMOST_FULL_IF = 0,
+    parameter USE_ALMOST_EMPTY_IF = 0,
+
+    // --------------------------------------------------
+    // Empty latency is defined as the number of cycles
+    // required for a write to deassert the empty flag.
+    // For example, a latency of 1 means that the empty
+    // flag is deasserted on the cycle after a write.
+    //
+    // Another way to think of it is the latency for a
+    // write to propagate to the output. 
+    // 
+    // An empty latency of 0 implies lookahead, which is
+    // only implemented for the register-based FIFO.
+    // --------------------------------------------------
+    parameter EMPTY_LATENCY     = 3,
+    parameter USE_MEMORY_BLOCKS = 1,
+
+    // --------------------------------------------------
+    // Internal Parameters
+    // --------------------------------------------------
+    parameter DATA_WIDTH  = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+    parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+    // --------------------------------------------------
+    // Ports
+    // --------------------------------------------------
+    input                       clk,
+    input                       reset,
+
+    input [DATA_WIDTH-1: 0]     in_data,
+    input                       in_valid,
+    input                       in_startofpacket,
+    input                       in_endofpacket,
+    input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]     in_empty,
+    input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]     in_error,
+    input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0]  in_channel,
+    output                      in_ready,
+
+    output [DATA_WIDTH-1 : 0]   out_data,
+    output reg                  out_valid,
+    output                      out_startofpacket,
+    output                      out_endofpacket,
+    output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]    out_empty,
+    output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]    out_error,
+    output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+    input                       out_ready,
+
+    input [(USE_STORE_FORWARD ? 2 : 1) : 0]   csr_address,
+    input                       csr_write,
+    input                       csr_read,
+    input [31 : 0]              csr_writedata,
+    output reg [31 : 0]         csr_readdata,
+
+    output  wire                almost_full_data,
+    output  wire                almost_empty_data
+);
+
+    // --------------------------------------------------
+    // Local Parameters
+    // --------------------------------------------------
+    localparam ADDR_WIDTH   = log2ceil(FIFO_DEPTH);
+    localparam DEPTH        = FIFO_DEPTH;
+    localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+    localparam PAYLOAD_WIDTH     = (USE_PACKETS == 1) ? 
+                   2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+                   DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+    // --------------------------------------------------
+    // Internal Signals
+    // --------------------------------------------------
+    genvar i;
+
+    reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+    reg [ADDR_WIDTH-1 : 0]  wr_ptr;
+    reg [ADDR_WIDTH-1 : 0]  rd_ptr;
+    reg [DEPTH-1      : 0]  mem_used;
+
+    wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+    wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+    wire read;
+    wire write;
+
+    reg empty;
+    reg next_empty;
+    reg full;
+    reg next_full;
+
+    wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+    wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+    wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+    reg  internal_out_valid;
+    wire internal_out_ready;
+
+    reg  [ADDR_WIDTH : 0] fifo_fill_level;
+    reg  [ADDR_WIDTH : 0] fill_level;
+
+    reg  [ADDR_WIDTH-1 : 0]   sop_ptr = 0;
+    wire [ADDR_WIDTH-1 : 0]   curr_sop_ptr;
+    reg  [23:0]   almost_full_threshold;
+    reg  [23:0]   almost_empty_threshold;
+    reg  [23:0]   cut_through_threshold;
+    reg  [15:0]   pkt_cnt;
+    reg           drop_on_error_en;
+    reg           error_in_pkt;
+    reg           pkt_has_started;
+    reg           sop_has_left_fifo;
+    reg           fifo_too_small_r;
+    reg           pkt_cnt_eq_zero;
+    reg           pkt_cnt_eq_one;
+
+    wire          wait_for_threshold;
+    reg           pkt_mode;
+    wire          wait_for_pkt;
+    wire          ok_to_forward;
+    wire          in_pkt_eop_arrive;
+    wire          out_pkt_leave;
+    wire          in_pkt_start;
+    wire          in_pkt_error;
+    wire          drop_on_error;
+    wire          fifo_too_small;
+    wire          out_pkt_sop_leave;
+    wire [31:0]   max_fifo_size;
+    reg           fifo_fill_level_lt_cut_through_threshold;
+
+    // --------------------------------------------------
+    // Define Payload
+    //
+    // Icky part where we decide which signals form the
+    // payload to the FIFO with generate blocks.
+    // --------------------------------------------------
+    generate
+        if (EMPTY_WIDTH > 0) begin : gen_blk1
+            assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+            assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+        end 
+        else begin : gen_blk1_else
+            assign out_empty = in_error;
+            assign in_packet_signals = {in_startofpacket, in_endofpacket};
+            assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+        end
+    endgenerate
+
+    generate
+        if (USE_PACKETS) begin : gen_blk2
+            if (ERROR_WIDTH > 0) begin : gen_blk3
+                if (CHANNEL_WIDTH > 0) begin : gen_blk4
+                    assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+                    assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk4_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data, in_error};
+                    assign {out_packet_signals, out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk3_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk5
+                    assign in_payload = {in_packet_signals, in_data, in_channel};
+                    assign {out_packet_signals, out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk5_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data};
+                    assign {out_packet_signals, out_data} = out_payload;
+                end
+            end
+        end
+        else begin : gen_blk2_else
+            assign out_packet_signals = 0;
+            if (ERROR_WIDTH > 0) begin : gen_blk6
+                if (CHANNEL_WIDTH > 0) begin : gen_blk7
+                    assign in_payload = {in_data, in_error, in_channel};
+                    assign {out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk7_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_data, in_error};
+                    assign {out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk6_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk8
+                    assign in_payload = {in_data, in_channel};
+                    assign {out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk8_else
+                    assign out_channel = in_channel;
+                    assign in_payload = in_data;
+                    assign out_data = out_payload;
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Memory-based FIFO storage
+    //
+    // To allow a ready latency of 0, the read index is 
+    // obtained from the next read pointer and memory 
+    // outputs are unregistered.
+    //
+    // If the empty latency is 1, we infer bypass logic
+    // around the memory so writes propagate to the
+    // outputs on the next cycle.
+    //
+    // Do not change the way this is coded: Quartus needs
+    // a perfect match to the template, and any attempt to 
+    // refactor the two always blocks into one will break
+    // memory inference.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin  : gen_blk9
+
+        if (EMPTY_LATENCY == 1) begin : gen_blk10
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] = in_payload;
+
+                internal_out_payload = mem[mem_rd_ptr];
+            end
+
+        end else begin : gen_blk10_else
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] <= in_payload;
+
+                internal_out_payload <= mem[mem_rd_ptr];
+            end
+
+        end
+
+        assign mem_rd_ptr = next_rd_ptr;
+    
+    end else begin : gen_blk9_else
+
+    // --------------------------------------------------
+    // Register-based FIFO storage
+    //
+    // Uses a shift register as the storage element. Each
+    // shift register slot has a bit which indicates if
+    // the slot is occupied (credit to Sam H for the idea).
+    // The occupancy bits are contiguous and start from the
+    // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+    // FIFO.
+    // 
+    // Each slot is enabled during a read or when it
+    // is unoccupied. New data is always written to every
+    // going-to-be-empty slot (we keep track of which ones
+    // are actually useful with the occupancy bits). On a
+    // read we shift occupied slots.
+    // 
+    // The exception is the last slot, which always gets 
+    // new data when it is unoccupied.
+    // --------------------------------------------------
+        for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem[i] <= 0;
+                end 
+                else if (read || !mem_used[i]) begin
+                    if (!mem_used[i+1])
+                        mem[i] <= in_payload;
+                    else
+                        mem[i] <= mem[i+1];
+                end
+            end
+        end
+
+        always @(posedge clk, posedge reset) begin
+            if (reset) begin
+                mem[DEPTH-1] <= 0;
+            end 
+            else begin
+                if (DEPTH == 1) begin
+                    if (write)
+                        mem[DEPTH-1] <= in_payload;
+                end
+                else if (!mem_used[DEPTH-1])
+                    mem[DEPTH-1] <= in_payload;    
+            end
+        end
+
+    end
+    endgenerate
+
+    assign read  = internal_out_ready && internal_out_valid  && ok_to_forward;
+    assign write = in_ready && in_valid;
+
+    // --------------------------------------------------
+    // Pointer Management
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
+
+        assign incremented_wr_ptr = wr_ptr + 1'b1;
+        assign incremented_rd_ptr = rd_ptr + 1'b1;
+        assign next_wr_ptr =  drop_on_error ? curr_sop_ptr : write ?  incremented_wr_ptr : wr_ptr;
+        assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                wr_ptr <= 0;
+                rd_ptr <= 0;
+            end
+            else begin
+                wr_ptr <= next_wr_ptr;
+                rd_ptr <= next_rd_ptr;
+            end
+        end
+
+    end else begin : gen_blk11_else
+
+    // --------------------------------------------------
+    // Shift Register Occupancy Bits
+    //
+    // Consider a 4-deep FIFO with 2 entries: 0011
+    // On a read and write, do not modify the bits.
+    // On a write, left-shift the bits to get 0111.
+    // On a read, right-shift the bits to get 0001.
+    //
+    // Also, on a write we set bit0 (the head), while
+    // clearing the tail on a read.
+    // --------------------------------------------------
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                mem_used[0] <= 0;
+            end 
+            else begin
+                if (write ^ read) begin
+                    if (write)
+                        mem_used[0] <= 1;
+                    else if (read) begin
+                        if (DEPTH > 1)
+                            mem_used[0] <= mem_used[1];
+                        else
+                            mem_used[0] <= 0;
+                    end    
+                end
+            end
+        end
+
+        if (DEPTH > 1) begin : gen_blk12
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem_used[DEPTH-1] <= 0;
+                end
+                else begin 
+                    if (write ^ read) begin            
+                        mem_used[DEPTH-1] <= 0;
+                        if (write)
+                            mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+                    end
+                end
+            end
+          end
+     
+        for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+            always @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    mem_used[i] <= 0;
+                end 
+                else begin
+                    if (write ^ read) begin
+                        if (write)
+                            mem_used[i] <= mem_used[i-1];
+                        else if (read)
+                            mem_used[i] <= mem_used[i+1];     
+                    end
+                end
+            end
+        end
+     
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Memory FIFO Status Management
+    //
+    // Generates the full and empty signals from the
+    // pointers. The FIFO is full when the next write 
+    // pointer will be equal to the read pointer after
+    // a write. Reading from a FIFO clears full.
+    //
+    // The FIFO is empty when the next read pointer will
+    // be equal to the write pointer after a read. Writing
+    // to a FIFO clears empty.
+    //
+    // A simultaneous read and write must not change any of 
+    // the empty or full flags unless there is a drop on error event.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
+
+        always @* begin
+            next_full = full;
+            next_empty = empty;
+     
+            if (read && !write) begin
+                next_full = 1'b0;
+     
+                if (incremented_rd_ptr == wr_ptr)
+                    next_empty = 1'b1;
+            end
+            
+            if (write && !read) begin
+                if (!drop_on_error)
+                  next_empty = 1'b0;
+                else if (curr_sop_ptr == rd_ptr)   // drop on error and only 1 pkt in fifo
+                  next_empty = 1'b1;
+     
+                if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+                    next_full = 1'b1;
+            end
+
+            if (write && read && drop_on_error) begin
+                if (curr_sop_ptr == next_rd_ptr)
+                  next_empty = 1'b1;
+            end
+        end
+     
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                empty <= 1;
+                full  <= 0;
+            end
+            else begin 
+                empty <= next_empty;
+                full  <= next_full;
+            end
+        end
+
+    end else begin : gen_blk13_else
+    // --------------------------------------------------
+    // Register FIFO Status Management
+    //
+    // Full when the tail occupancy bit is 1. Empty when
+    // the head occupancy bit is 0.
+    // --------------------------------------------------
+        always @* begin
+            full  = mem_used[DEPTH-1];
+            empty = !mem_used[0];
+
+            // ------------------------------------------
+            // For a single slot FIFO, reading clears the
+            // full status immediately.
+            // ------------------------------------------
+            if (DEPTH == 1)
+                full = mem_used[0] && !read;
+
+            internal_out_payload = mem[0];
+
+            // ------------------------------------------
+            // Writes clear empty immediately for lookahead modes.
+            // Note that we use in_valid instead of write to avoid
+            // combinational loops (in lookahead mode, qualifying
+            // with in_ready is meaningless).
+            //
+            // In a 1-deep FIFO, a possible combinational loop runs
+            // from write -> out_valid -> out_ready -> write
+            // ------------------------------------------
+            if (EMPTY_LATENCY == 0) begin
+                empty = !mem_used[0] && !in_valid;
+
+                if (!mem_used[0] && in_valid)
+                    internal_out_payload = in_payload;
+            end
+        end
+
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-ST Signals
+    //
+    // The in_ready signal is straightforward. 
+    //
+    // To match memory latency when empty latency > 1, 
+    // out_valid assertions must be delayed by one clock
+    // cycle.
+    //
+    // Note: out_valid deassertions must not be delayed or 
+    // the FIFO will underflow.
+    // --------------------------------------------------
+    assign in_ready = !full;
+    assign internal_out_ready = out_ready || !out_valid;
+
+    generate if (EMPTY_LATENCY > 1) begin : gen_blk14
+        always @(posedge clk or posedge reset) begin
+            if (reset)
+                internal_out_valid <= 0;
+            else begin
+                internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+                if (read) begin
+                    if (incremented_rd_ptr == wr_ptr)
+                        internal_out_valid <= 1'b0;
+                end
+            end
+        end
+    end else begin : gen_blk14_else
+        always @* begin
+            internal_out_valid = !empty & ok_to_forward;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Single Output Pipeline Stage
+    //
+    // This output pipeline stage is enabled if the FIFO's 
+    // empty latency is set to 3 (default). It is disabled
+    // for all other allowed latencies.
+    //
+    // Reason: The memory outputs are unregistered, so we have to
+    // register the output or fmax will drop if combinatorial
+    // logic is present on the output datapath.
+    // 
+    // Q: The Avalon-ST spec says that I have to register my outputs
+    //    But isn't the memory counted as a register?
+    // A: The path from the address lookup to the memory output is
+    //    slow. Registering the memory outputs is a good idea. 
+    //
+    // The registers get packed into the memory by the fitter
+    // which means minimal resources are consumed (the result
+    // is a altsyncram with registered outputs, available on 
+    // all modern Altera devices). 
+    //
+    // This output stage acts as an extra slot in the FIFO, 
+    // and complicates the fill level.
+    // --------------------------------------------------
+    generate if (EMPTY_LATENCY == 3) begin : gen_blk15
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                out_valid   <= 0;
+                out_payload <= 0;
+            end
+            else begin
+                if (internal_out_ready) begin
+                    out_valid   <= internal_out_valid & ok_to_forward;
+                    out_payload <= internal_out_payload;
+                end
+            end
+        end
+    end
+    else begin : gen_blk15_else
+        always @* begin
+            out_valid   = internal_out_valid;
+            out_payload = internal_out_payload;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Fill Level
+    //
+    // The fill level is calculated from the next write
+    // and read pointers to avoid unnecessary latency
+    // and logic.
+    //
+    // However, if the store-and-forward mode of the FIFO
+    // is enabled, the fill level is an up-down counter
+    // for fmax optimization reasons.
+    //
+    // If the output pipeline is enabled, the fill level 
+    // must account for it, or we'll always be off by one.
+    // This may, or may not be important depending on the
+    // application.
+    //
+    // For now, we'll always calculate the exact fill level
+    // at the cost of an extra adder when the output stage
+    // is enabled.
+    // --------------------------------------------------
+    generate if (USE_FILL_LEVEL) begin : gen_blk16
+        wire [31:0] depth32;
+        assign depth32 = DEPTH;
+
+        if (USE_STORE_FORWARD) begin
+
+            reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
+            
+            // --------------------------------------------------
+            // We only drop on endofpacket. As long as we don't add to the fill
+            // level on the dropped endofpacket cycle, we can simply subtract
+            // (packet length - 1) from the fill level for dropped packets.
+            // --------------------------------------------------
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    curr_packet_len_less_one <= 0;
+                end else begin
+                    if (write) begin
+                        curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
+                        if (in_endofpacket)
+                            curr_packet_len_less_one <= 0;
+                    end
+                end
+            end
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    fifo_fill_level <= 0;
+                end else if (drop_on_error) begin
+                    fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
+                    if (read)
+                        fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
+                end else if (write && !read) begin
+                    fifo_fill_level <= fifo_fill_level + 1'b1;
+                end else if (read && !write) begin
+                    fifo_fill_level <= fifo_fill_level - 1'b1;
+                end
+            end
+
+        end else begin
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) 
+                    fifo_fill_level <= 0;
+                else if (next_full & !drop_on_error)
+                    fifo_fill_level <= depth32[ADDR_WIDTH:0];
+                else begin
+                    fifo_fill_level[ADDR_WIDTH]     <= 1'b0;
+                    fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+                end
+            end
+
+        end
+
+        always @* begin
+            fill_level = fifo_fill_level;
+
+            if (EMPTY_LATENCY == 3)
+                fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+        end
+    end
+    else begin : gen_blk16_else
+        always @* begin
+            fill_level = 0;
+        end  
+    end
+    endgenerate
+
+    generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
+      assign almost_full_data = (fill_level >= almost_full_threshold);
+    end
+    else
+      assign almost_full_data = 0;
+    endgenerate
+
+    generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
+      assign almost_empty_data = (fill_level <= almost_empty_threshold);
+    end
+    else
+      assign almost_empty_data = 0;
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-MM Status & Control Connection Point
+    //
+    // Register map:
+    //
+    // | Addr   | RW |     31 - 0      |
+    // |  0     | R  |   Fill level    |
+    //
+    // The registering of this connection point means
+    // that there is a cycle of latency between 
+    // reads/writes and the updating of the fill level.
+    // --------------------------------------------------
+    generate if (USE_STORE_FORWARD) begin : gen_blk19
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              cut_through_threshold  <= 0;
+              drop_on_error_en       <= 0;
+              csr_readdata           <= 0;
+              pkt_mode               <= 1'b1;
+          end
+          else begin
+              if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 5)
+                    csr_readdata <= {31'b0, drop_on_error_en};
+                else if (csr_address == 4)
+                    csr_readdata <= {8'b0, cut_through_threshold};
+                else if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b101)
+                   drop_on_error_en       <= csr_writedata[0];
+               else if(csr_address == 3'b100) begin
+                   cut_through_threshold  <= csr_writedata[23:0];
+                   pkt_mode <= (csr_writedata[23:0] == 0);
+               end
+               else if(csr_address == 3'b011)
+                    almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end     
+          end
+      end
+    end
+    else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              csr_readdata           <= 0;
+          end
+          else begin
+             if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b011)
+                   almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end       
+          end
+      end
+    end
+    else begin : gen_blk19_else2
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              csr_readdata <= 0;
+          end
+          else if (csr_read) begin
+              csr_readdata <= 0;
+
+              if (csr_address == 0) 
+                  csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+          end
+      end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Store and forward logic
+    // --------------------------------------------------
+    // if the fifo gets full before the entire packet or the
+    // cut-threshold condition is met then start sending out
+    // data in order to avoid dead-lock situation
+
+    generate if (USE_STORE_FORWARD) begin : gen_blk20
+      assign wait_for_threshold   = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+      assign wait_for_pkt         = pkt_cnt_eq_zero  | (pkt_cnt_eq_one  & out_pkt_leave);
+      assign ok_to_forward        = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : 
+                                     ~wait_for_threshold) | fifo_too_small_r;
+      assign in_pkt_eop_arrive    = in_valid & in_ready & in_endofpacket;
+      assign in_pkt_start         = in_valid & in_ready & in_startofpacket;
+      assign in_pkt_error         = in_valid & in_ready & |in_error;
+      assign out_pkt_sop_leave    = out_valid & out_ready & out_startofpacket;
+      assign out_pkt_leave        = out_valid & out_ready & out_endofpacket;
+      assign fifo_too_small       = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+      // count packets coming and going into the fifo
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          pkt_cnt           <= 0;
+          pkt_has_started   <= 0;
+          sop_has_left_fifo <= 0;
+          fifo_too_small_r  <= 0;
+          pkt_cnt_eq_zero   <= 1'b1;
+          pkt_cnt_eq_one    <= 1'b0;
+          fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+        end
+        else begin
+          fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+          fifo_too_small_r <= fifo_too_small;
+
+          if( in_pkt_eop_arrive )
+            sop_has_left_fifo <= 1'b0;
+          else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+            sop_has_left_fifo <= 1'b1;
+
+          if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+            pkt_cnt <= pkt_cnt + 1'b1;
+            pkt_cnt_eq_zero <= 0;
+            if (pkt_cnt == 0)
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+          else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+            pkt_cnt <= pkt_cnt - 1'b1;
+            if (pkt_cnt == 1) 
+              pkt_cnt_eq_zero <= 1'b1;
+            else
+              pkt_cnt_eq_zero <= 1'b0;
+            if (pkt_cnt == 2) 
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+
+          if (in_pkt_start)
+            pkt_has_started <= 1'b1;
+          else if (in_pkt_eop_arrive)
+            pkt_has_started <= 1'b0;
+        end
+      end
+
+      // drop on error logic
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          sop_ptr <= 0;
+          error_in_pkt <= 0;
+        end
+        else begin
+          // save the location of the SOP
+          if ( in_pkt_start ) 
+            sop_ptr <= wr_ptr;
+
+          // remember if error in pkt
+          // log error only if packet has already started
+          if (in_pkt_eop_arrive)
+            error_in_pkt <= 1'b0;
+          else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+            error_in_pkt <= 1'b1;
+        end
+      end
+
+      assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & 
+                            ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+      assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
+
+    end
+    else begin : gen_blk20_else
+      assign ok_to_forward = 1'b1;
+      assign drop_on_error = 1'b0;
+      if (ADDR_WIDTH <= 1)
+        assign curr_sop_ptr = 1'b0;
+      else
+        assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v
new file mode 100644
index 0000000..7a47241
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v
@@ -0,0 +1,141 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_clock_crosser(
+                                 in_clk,
+                                 in_reset,
+                                 in_ready,
+                                 in_valid,
+                                 in_data,
+                                 out_clk,
+                                 out_reset,
+                                 out_ready,
+                                 out_valid,
+                                 out_data
+                                );
+
+  parameter  SYMBOLS_PER_BEAT    = 1;
+  parameter  BITS_PER_SYMBOL     = 8;
+  parameter  FORWARD_SYNC_DEPTH  = 2;
+  parameter  BACKWARD_SYNC_DEPTH = 2;
+  parameter  USE_OUTPUT_PIPELINE = 1;
+  
+  localparam  DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+  input                   in_clk;
+  input                   in_reset;
+  output                  in_ready;
+  input                   in_valid;
+  input  [DATA_WIDTH-1:0] in_data;
+
+  input                   out_clk;
+  input                   out_reset;
+  input                   out_ready;
+  output                  out_valid;
+  output [DATA_WIDTH-1:0] out_data;
+
+  // Data is guaranteed valid by control signal clock crossing.  Cut data
+  // buffer false path.
+  (* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
+  reg    [DATA_WIDTH-1:0] out_data_buffer;
+
+  reg                     in_data_toggle;
+  wire                    in_data_toggle_returned;
+  wire                    out_data_toggle;
+  reg                     out_data_toggle_flopped;
+
+  wire                    take_in_data;
+  wire                    out_data_taken;
+
+  wire                    out_valid_internal;
+  wire                    out_ready_internal;
+
+  assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
+  assign take_in_data = in_valid & in_ready;
+  assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
+  assign out_data_taken = out_ready_internal & out_valid_internal;
+
+  always @(posedge in_clk or posedge in_reset) begin
+    if (in_reset) begin
+      in_data_buffer <= {DATA_WIDTH{1'b0}};
+      in_data_toggle <= 1'b0;
+    end else begin
+      if (take_in_data) begin
+        in_data_toggle <= ~in_data_toggle;
+        in_data_buffer <= in_data;
+      end
+    end //in_reset
+  end //in_clk always block
+
+  always @(posedge out_clk or posedge out_reset) begin
+    if (out_reset) begin
+      out_data_toggle_flopped <= 1'b0;
+      out_data_buffer <= {DATA_WIDTH{1'b0}};
+    end else begin
+      out_data_buffer <= in_data_buffer;
+      if (out_data_taken) begin
+        out_data_toggle_flopped <= out_data_toggle;
+      end
+    end //end if
+  end //out_clk always block
+
+  altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
+				     .clk(out_clk),
+				     .reset_n(~out_reset),
+				     .din(in_data_toggle),
+				     .dout(out_data_toggle)
+				     );
+  
+  altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
+				     .clk(in_clk),
+				     .reset_n(~in_reset),
+				     .din(out_data_toggle_flopped),
+				     .dout(in_data_toggle_returned)
+				     );
+
+  generate if (USE_OUTPUT_PIPELINE == 1) begin
+
+      altera_avalon_st_pipeline_base 
+      #(
+         .BITS_PER_SYMBOL(BITS_PER_SYMBOL),
+         .SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
+      ) output_stage (
+         .clk(out_clk),
+         .reset(out_reset),
+         .in_ready(out_ready_internal),
+         .in_valid(out_valid_internal),
+         .in_data(out_data_buffer),
+         .out_ready(out_ready),
+         .out_valid(out_valid),
+         .out_data(out_data)
+      );
+
+  end else begin
+
+      assign out_valid = out_valid_internal;
+      assign out_ready_internal = out_ready;
+      assign out_data = out_data_buffer;
+
+  end
+
+  endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc
new file mode 100644
index 0000000..d2d6a7c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc
@@ -0,0 +1,71 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# $File: //acds/main/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.sdc $
+# $Revision: #1 $
+# $Date: 2014/04/09 $
+# $Author: kespence $
+#------------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
+# Altera timing constraints for Avalon clock domain crossing (CDC) paths.
+# The purpose of these constraints is to remove the false paths and replace with timing bounded 
+# requirements for compilation.
+#
+# ***Important note *** 
+#
+# The clocks involved in this transfer must be kept synchronous and no false path
+# should be set on these paths for these constraints to apply correctly.
+# -----------------------------------------------------------------------------
+
+set crosser_entity "altera_avalon_st_clock_crosser:"
+set_max_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] 100
+set_min_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -100
+
+set sync_entity "altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:"
+set_max_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] 100
+set_min_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -100
+
+if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
+    set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+    set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+} else {
+    set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max 2
+    set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max 2
+}
+
+# -----------------------------------------------------------------------------
+# This procedure constrains the skew between the token and data bits, and should
+# be called from the top level SDC, once per instance of the clock crosser.
+#
+# The hierarchy path to the handshake clock crosser instance is required as an 
+# argument.
+#
+# In practice, the token and data bits tend to be placed close together, making
+# excessive skew less of an issue.
+# -----------------------------------------------------------------------------
+proc constrain_alt_handshake_clock_crosser_skew { path } {
+
+    set in_regs  [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_buffer* ] 
+    set out_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|out_data_buffer* ] 
+
+    set in_regs [ add_to_collection $in_regs  [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_toggle ] ]
+    set out_regs [ add_to_collection $out_regs [ get_registers $path|*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:in_to_out_synchronizer|din_s1 ] ]
+
+    if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
+        set_max_skew -from $in_regs -to $out_regs -get_skew_value_from_clock_period dst_clock_period -skew_value_multiplier 0.8
+    } else {
+        set_max_skew -from $in_regs -to $out_regs 1.5 
+    }
+}
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
new file mode 100644
index 0000000..d1a2958
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v
@@ -0,0 +1,218 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+// Clock crosser module with handshaking mechanism
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_handshake_clock_crosser
+#(
+    parameter DATA_WIDTH       = 8,
+              BITS_PER_SYMBOL  = 8,
+              USE_PACKETS      = 0,
+
+              // ------------------------------
+              // Optional signal widths
+              // ------------------------------
+              USE_CHANNEL      = 0,
+              CHANNEL_WIDTH    = 1,
+              USE_ERROR        = 0,
+              ERROR_WIDTH      = 1,
+
+              VALID_SYNC_DEPTH = 2,
+              READY_SYNC_DEPTH = 2,
+
+              USE_OUTPUT_PIPELINE = 1,
+
+              // ------------------------------
+              // Derived parameters
+              // ------------------------------
+              SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
+              EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+    input in_clk,
+    input in_reset,
+    input out_clk,
+    input out_reset,
+
+    output in_ready,
+    input  in_valid,
+    input [DATA_WIDTH - 1 : 0]      in_data,
+    input [CHANNEL_WIDTH - 1 : 0]   in_channel,
+    input [ERROR_WIDTH - 1 : 0]     in_error,
+    input in_startofpacket,
+    input in_endofpacket,
+    input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+    input  out_ready,
+    output out_valid,
+    output [DATA_WIDTH - 1 : 0]     out_data,
+    output [CHANNEL_WIDTH - 1 : 0]  out_channel,
+    output [ERROR_WIDTH - 1 : 0]    out_error,
+    output out_startofpacket,
+    output out_endofpacket,
+    output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+
+    // ------------------------------
+    // Payload-specific widths
+    // ------------------------------
+    localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
+    localparam PCHANNEL_W   = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
+    localparam PERROR_W     = (USE_ERROR) ? ERROR_WIDTH : 0;
+
+    localparam PAYLOAD_WIDTH = DATA_WIDTH + 
+        PACKET_WIDTH +
+        PCHANNEL_W +
+        EMPTY_WIDTH +
+        PERROR_W;
+
+   
+    wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+    wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+   
+    // ------------------------------
+    // Assign in_data and other optional sink interface 
+    // signals to in_payload.
+    // ------------------------------
+    assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+    generate
+        // optional packet inputs
+        if (PACKET_WIDTH) begin
+            assign in_payload[
+                DATA_WIDTH + PACKET_WIDTH - 1 : 
+                DATA_WIDTH
+            ] = {in_startofpacket, in_endofpacket};
+        end
+        // optional channel input
+        if (USE_CHANNEL) begin
+            assign in_payload[
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 : 
+              DATA_WIDTH + PACKET_WIDTH
+            ] = in_channel;
+        end
+        // optional empty input
+        if (EMPTY_WIDTH) begin
+            assign in_payload[
+                DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 : 
+                DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+            ] = in_empty;
+        end
+        // optional error input
+        if (USE_ERROR) begin
+            assign in_payload[
+                DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 : 
+                DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+            ] = in_error;
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Pipe the input payload to our inner module which handles the
+    // actual clock crossing
+    // --------------------------------------------------
+    altera_avalon_st_clock_crosser
+    #(
+        .SYMBOLS_PER_BEAT    (1),
+        .BITS_PER_SYMBOL     (PAYLOAD_WIDTH),
+        .FORWARD_SYNC_DEPTH  (VALID_SYNC_DEPTH),
+        .BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
+        .USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
+    ) clock_xer (
+        .in_clk    (in_clk      ),
+        .in_reset  (in_reset    ),
+        .in_ready  (in_ready    ),
+        .in_valid  (in_valid    ),
+        .in_data   (in_payload  ),
+        .out_clk   (out_clk     ),
+        .out_reset (out_reset   ),
+        .out_ready (out_ready   ),
+        .out_valid (out_valid   ),
+        .out_data  (out_payload )
+    );
+
+    // --------------------------------------------------
+    // Split out_payload into the output signals.
+    // --------------------------------------------------
+    assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+
+    generate
+        // optional packet outputs
+        if (USE_PACKETS) begin
+            assign {out_startofpacket, out_endofpacket} = 
+                out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+        end else begin
+            // avoid a "has no driver" warning.
+            assign {out_startofpacket, out_endofpacket} = 2'b0;
+        end
+   
+        // optional channel output
+        if (USE_CHANNEL) begin
+            assign out_channel = out_payload[
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 : 
+              DATA_WIDTH + PACKET_WIDTH
+            ];
+        end else begin
+            // avoid a "has no driver" warning.
+            assign out_channel = 1'b0;
+        end
+
+        // optional empty output
+        if (EMPTY_WIDTH) begin
+            assign out_empty = out_payload[
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 : 
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+            ];
+        end else begin
+            // avoid a "has no driver" warning.
+            assign out_empty = 1'b0;
+        end
+
+        // optional error output
+        if (USE_ERROR) begin
+            assign out_error = out_payload[
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 : 
+              DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+            ];
+        end else begin
+            // avoid a "has no driver" warning.
+            assign out_error = 1'b0;
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value.
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        integer i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000..062b061
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,139 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+                                       clk,
+                                       reset,
+                                       in_ready,
+                                       in_valid,
+                                       in_data,
+                                       out_ready,
+                                       out_valid,
+                                       out_data
+                                       );
+
+   parameter  SYMBOLS_PER_BEAT  = 1;
+   parameter  BITS_PER_SYMBOL   = 8;
+   parameter  PIPELINE_READY    = 1;
+   localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+   
+   input clk;
+   input reset;
+   
+   output in_ready;
+   input  in_valid;
+   input [DATA_WIDTH-1:0] in_data;
+   
+   input                  out_ready;
+   output                 out_valid;
+   output [DATA_WIDTH-1:0] out_data;
+   
+   reg                     full0;
+   reg                     full1;
+   reg [DATA_WIDTH-1:0]    data0;
+   reg [DATA_WIDTH-1:0]    data1;
+
+   assign out_valid = full1;
+   assign out_data  = data1;    
+   
+   generate if (PIPELINE_READY == 1) 
+     begin : REGISTERED_READY_PLINE
+        
+        assign in_ready  = !full0;
+
+        always @(posedge clk, posedge reset) begin
+           if (reset) begin
+              data0 <= {DATA_WIDTH{1'b0}};
+              data1 <= {DATA_WIDTH{1'b0}};
+           end else begin
+              // ----------------------------
+              // always load the second slot if we can
+              // ----------------------------
+              if (~full0)
+                data0 <= in_data;
+              // ----------------------------
+              // first slot is loaded either from the second,
+              // or with new data
+              // ----------------------------
+              if (~full1 || (out_ready && out_valid)) begin
+                 if (full0)
+                   data1 <= data0;
+                 else
+                   data1 <= in_data;
+              end
+           end
+        end
+        
+        always @(posedge clk or posedge reset) begin
+           if (reset) begin
+              full0    <= 1'b0;
+              full1    <= 1'b0;
+           end else begin
+              // no data in pipeline
+              if (~full0 & ~full1) begin
+                 if (in_valid) begin
+                    full1 <= 1'b1;
+                 end
+              end // ~f1 & ~f0
+
+              // one datum in pipeline 
+              if (full1 & ~full0) begin
+                 if (in_valid & ~out_ready) begin
+                    full0 <= 1'b1;
+                 end
+                 // back to empty
+                 if (~in_valid & out_ready) begin
+                    full1 <= 1'b0;
+                 end
+              end // f1 & ~f0
+              
+              // two data in pipeline 
+              if (full1 & full0) begin
+                 // go back to one datum state
+                 if (out_ready) begin
+                    full0 <= 1'b0;
+                 end
+              end // end go back to one datum stage
+           end
+        end
+
+     end 
+   else 
+     begin : UNREGISTERED_READY_PLINE
+	
+	// in_ready will be a pass through of the out_ready signal as it is not registered
+	assign in_ready = (~full1) | out_ready;
+	
+	always @(posedge clk or posedge reset) begin
+	   if (reset) begin
+	      data1 <= 'b0;
+	      full1 <= 1'b0;
+	   end
+	   else begin
+	      if (in_ready) begin
+		 data1 <= in_data;
+		 full1 <= in_valid;
+	      end
+	   end
+	end		
+     end
+   endgenerate
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
new file mode 100644
index 0000000..cc31c27
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
@@ -0,0 +1,166 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_stage #(
+    parameter 
+      SYMBOLS_PER_BEAT = 1,
+      BITS_PER_SYMBOL = 8,
+      USE_PACKETS = 0,
+      USE_EMPTY = 0,
+      PIPELINE_READY = 1,
+
+      // Optional ST signal widths.  Value "0" means no such port.
+      CHANNEL_WIDTH = 0,
+      ERROR_WIDTH = 0,
+
+      // Derived parameters
+      DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+      PACKET_WIDTH = 0,
+      EMPTY_WIDTH = 0
+  )
+  (
+    input clk,
+    input reset,
+
+    output in_ready,
+    input in_valid,
+    input [DATA_WIDTH - 1 : 0] in_data,
+    input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
+    input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
+    input in_startofpacket,
+    input in_endofpacket,
+    input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+    input out_ready,
+    output out_valid,
+    output [DATA_WIDTH - 1 : 0] out_data,
+    output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
+    output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
+    output out_startofpacket,
+    output out_endofpacket,
+    output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+  localparam 
+    PAYLOAD_WIDTH = 
+      DATA_WIDTH +
+      PACKET_WIDTH +
+      CHANNEL_WIDTH +
+      EMPTY_WIDTH +
+      ERROR_WIDTH;
+
+  wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+  wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+  // Assign in_data and other optional in_* interface signals to in_payload.
+  assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+  generate
+    // optional packet inputs
+    if (PACKET_WIDTH) begin
+      assign in_payload[
+        DATA_WIDTH + PACKET_WIDTH - 1 : 
+        DATA_WIDTH
+      ] = {in_startofpacket, in_endofpacket};
+    end
+    // optional channel input
+    if (CHANNEL_WIDTH) begin
+      assign in_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH
+      ] = in_channel;
+    end
+    // optional empty input
+    if (EMPTY_WIDTH) begin
+      assign in_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+      ] = in_empty;
+    end
+    // optional error input
+    if (ERROR_WIDTH) begin
+      assign in_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+      ] = in_error;
+    end
+  endgenerate
+
+  altera_avalon_st_pipeline_base #(
+    .SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
+    .BITS_PER_SYMBOL (1),
+    .PIPELINE_READY (PIPELINE_READY)
+  ) core (
+    .clk (clk),
+    .reset (reset),
+    .in_ready (in_ready),
+    .in_valid (in_valid),
+    .in_data (in_payload),
+    .out_ready (out_ready),
+    .out_valid (out_valid),
+    .out_data (out_payload)
+  );
+
+  // Assign out_data and other optional out_* interface signals from out_payload.
+  assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+  generate
+    // optional packet outputs
+    if (PACKET_WIDTH) begin
+      assign {out_startofpacket, out_endofpacket} = 
+        out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+    end else begin
+      // Avoid a "has no driver" warning.
+      assign {out_startofpacket, out_endofpacket} = 2'b0;
+    end
+
+    // optional channel output
+    if (CHANNEL_WIDTH) begin
+      assign out_channel = out_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH
+      ];
+    end else begin
+      // Avoid a "has no driver" warning.
+      assign out_channel = 1'b0;
+    end
+    // optional empty output
+    if (EMPTY_WIDTH) begin
+      assign out_empty = out_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
+      ];
+    end else begin
+      // Avoid a "has no driver" warning.
+      assign out_empty = 1'b0;
+    end
+    // optional error output
+    if (ERROR_WIDTH) begin
+      assign out_error = out_payload[
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 : 
+        DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
+      ];
+    end else begin
+      // Avoid a "has no driver" warning.
+      assign out_error = 1'b0;
+    end
+  endgenerate
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
new file mode 100644
index 0000000..c244a3f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
@@ -0,0 +1,422 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/main/ip/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter.sv $
+// $Revision: #3 $
+// $Date: 2012/01/18 $
+// $Author: pscheidt $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_splitter #(
+   parameter 
+      NUMBER_OF_OUTPUTS  = 2, 
+      QUALIFY_VALID_OUT  = 1, 
+      DATA_WIDTH         = 8,
+      BITS_PER_SYMBOL    = 8,
+      USE_PACKETS        = 0,   
+      CHANNEL_WIDTH      = 1,	   
+      ERROR_WIDTH        = 1,
+      EMPTY_WIDTH        = 1
+  )
+(
+   output wire                    in0_ready,
+   input  wire                    in0_valid,
+   input  wire  [DATA_WIDTH-1 :0] in0_data,
+   input  wire  [CHANNEL_WIDTH-1 :0] in0_channel,
+   input  wire  [ERROR_WIDTH-1   :0] in0_error,
+   input  wire                    in0_startofpacket,
+   input  wire                    in0_endofpacket,
+   input  wire  [EMPTY_WIDTH-1   :0] in0_empty,
+   
+   input  wire                    out0_ready,
+   output wire                    out0_valid,
+   output wire  [DATA_WIDTH-1 :0] out0_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out0_channel,
+   output wire  [ERROR_WIDTH-1   :0] out0_error,
+   output wire                    out0_startofpacket,
+   output wire                    out0_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out0_empty,
+   
+   input  wire                    out1_ready,
+   output wire                    out1_valid,
+   output wire  [DATA_WIDTH-1 :0] out1_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out1_channel,
+   output wire  [ERROR_WIDTH-1   :0] out1_error,
+   output wire                    out1_startofpacket,
+   output wire                    out1_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out1_empty,
+   
+   input  wire                    out2_ready,
+   output wire                    out2_valid,
+   output wire  [DATA_WIDTH-1 :0] out2_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out2_channel,
+   output wire  [ERROR_WIDTH-1   :0] out2_error,
+   output wire                    out2_startofpacket,
+   output wire                    out2_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out2_empty,
+   
+   input  wire                    out3_ready,
+   output wire                    out3_valid,
+   output wire  [DATA_WIDTH-1 :0] out3_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out3_channel,
+   output wire  [ERROR_WIDTH-1   :0] out3_error,
+   output wire                    out3_startofpacket,
+   output wire                    out3_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out3_empty,
+   
+   input  wire                    out4_ready,
+   output wire                    out4_valid,
+   output wire  [DATA_WIDTH-1 :0] out4_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out4_channel,
+   output wire  [ERROR_WIDTH-1   :0] out4_error,
+   output wire                    out4_startofpacket,
+   output wire                    out4_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out4_empty,
+   
+   input  wire                    out5_ready,
+   output wire                    out5_valid,
+   output wire  [DATA_WIDTH-1 :0] out5_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out5_channel,
+   output wire  [ERROR_WIDTH-1   :0] out5_error,
+   output wire                    out5_startofpacket,
+   output wire                    out5_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out5_empty,
+   
+   input  wire                    out6_ready,
+   output wire                    out6_valid,
+   output wire  [DATA_WIDTH-1 :0] out6_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out6_channel,
+   output wire  [ERROR_WIDTH-1   :0] out6_error,
+   output wire                    out6_startofpacket,
+   output wire                    out6_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out6_empty,
+   
+   input  wire                    out7_ready,
+   output wire                    out7_valid,
+   output wire  [DATA_WIDTH-1 :0] out7_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out7_channel,
+   output wire  [ERROR_WIDTH-1   :0] out7_error,
+   output wire                    out7_startofpacket,
+   output wire                    out7_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out7_empty,
+   
+   input  wire                    out8_ready,
+   output wire                    out8_valid,
+   output wire  [DATA_WIDTH-1 :0] out8_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out8_channel,
+   output wire  [ERROR_WIDTH-1   :0] out8_error,
+   output wire                    out8_startofpacket,
+   output wire                    out8_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out8_empty,
+   
+   input  wire                    out9_ready,
+   output wire                    out9_valid,
+   output wire  [DATA_WIDTH-1 :0] out9_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out9_channel,
+   output wire  [ERROR_WIDTH-1   :0] out9_error,
+   output wire                    out9_startofpacket,
+   output wire                    out9_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out9_empty,
+   
+   input  wire                    out10_ready,
+   output wire                    out10_valid,
+   output wire  [DATA_WIDTH-1 :0] out10_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out10_channel,
+   output wire  [ERROR_WIDTH-1   :0] out10_error,
+   output wire                    out10_startofpacket,
+   output wire                    out10_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out10_empty,
+   
+   input  wire                    out11_ready,
+   output wire                    out11_valid,
+   output wire  [DATA_WIDTH-1 :0] out11_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out11_channel,
+   output wire  [ERROR_WIDTH-1   :0] out11_error,
+   output wire                    out11_startofpacket,
+   output wire                    out11_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out11_empty,
+   
+   input  wire                    out12_ready,
+   output wire                    out12_valid,
+   output wire  [DATA_WIDTH-1 :0] out12_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out12_channel,
+   output wire  [ERROR_WIDTH-1   :0] out12_error,
+   output wire                    out12_startofpacket,
+   output wire                    out12_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out12_empty,
+   
+   input  wire                    out13_ready,
+   output wire                    out13_valid,
+   output wire  [DATA_WIDTH-1 :0] out13_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out13_channel,
+   output wire  [ERROR_WIDTH-1   :0] out13_error,
+   output wire                    out13_startofpacket,
+   output wire                    out13_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out13_empty,
+   
+   input  wire                    out14_ready,
+   output wire                    out14_valid,
+   output wire  [DATA_WIDTH-1 :0] out14_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out14_channel,
+   output wire  [ERROR_WIDTH-1   :0] out14_error,
+   output wire                    out14_startofpacket,
+   output wire                    out14_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out14_empty,
+   
+   input  wire                    out15_ready,
+   output wire                    out15_valid,
+   output wire  [DATA_WIDTH-1 :0] out15_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out15_channel,
+   output wire  [ERROR_WIDTH-1   :0] out15_error,
+   output wire                    out15_startofpacket,
+   output wire                    out15_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out15_empty,
+   
+   input  wire                    clk,
+   input  wire                    reset
+);
+
+
+// ********************************************************************
+// Module Wiring
+
+wire   [15:0]            OutReady;
+wire   [15:0]            OutValid;
+wire   [DATA_WIDTH-1 :0] OutData    [15:0];
+wire   [CHANNEL_WIDTH-1 :0] OutChannel [15:0];
+wire   [ERROR_WIDTH-1   :0] OutError   [15:0];
+wire   [15:0]            OutSOP;
+wire   [15:0]            OutEOP;
+wire   [EMPTY_WIDTH-1   :0] OutEmpty   [15:0];
+
+genvar                   i, j;
+
+
+// ********************************************************************
+// Module Logic
+
+assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]);
+
+
+generate
+   for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT
+      assign OutData[i]    = in0_data;
+      assign OutChannel[i] = in0_channel;
+      assign OutError[i]   = in0_error;
+      assign OutSOP[i]     = in0_startofpacket;
+      assign OutEOP[i]     = in0_endofpacket;
+      assign OutEmpty[i]   = in0_empty;
+   end
+endgenerate
+
+
+generate
+   for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT
+      assign OutData[j]    = {DATA_WIDTH{1'b0}};
+      assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}};
+      assign OutError[j]   = {ERROR_WIDTH{1'b0}};
+      assign OutSOP[j]     = 1'b0;
+      assign OutEOP[j]     = 1'b0;
+      assign OutEmpty[j]   = {EMPTY_WIDTH{1'b0}};
+   end
+endgenerate
+
+
+generate
+   if (QUALIFY_VALID_OUT) begin
+      assign OutValid[0]  = &{in0_valid, OutReady[15:1]};
+      assign OutValid[1]  = &{in0_valid, OutReady[15:2],  OutReady[0]};
+      assign OutValid[2]  = &{in0_valid, OutReady[15:3],  OutReady[1:0]};
+      assign OutValid[3]  = &{in0_valid, OutReady[15:4],  OutReady[2:0]};
+      assign OutValid[4]  = &{in0_valid, OutReady[15:5],  OutReady[3:0]};
+      assign OutValid[5]  = &{in0_valid, OutReady[15:6],  OutReady[4:0]};
+      assign OutValid[6]  = &{in0_valid, OutReady[15:7],  OutReady[5:0]};
+      assign OutValid[7]  = &{in0_valid, OutReady[15:8],  OutReady[6:0]};
+      assign OutValid[8]  = &{in0_valid, OutReady[15:9],  OutReady[7:0]};
+      assign OutValid[9]  = &{in0_valid, OutReady[15:10], OutReady[8:0]};
+      assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]};
+      assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]};
+      assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]};
+      assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]};
+      assign OutValid[14] = &{in0_valid, OutReady[15],    OutReady[13:0]};
+      assign OutValid[15] = &{in0_valid,                  OutReady[14:0]};
+   end
+   else begin
+      assign OutValid[0]  = in0_valid;
+      assign OutValid[1]  = in0_valid;
+      assign OutValid[2]  = in0_valid;
+      assign OutValid[3]  = in0_valid;
+      assign OutValid[4]  = in0_valid;
+      assign OutValid[5]  = in0_valid;
+      assign OutValid[6]  = in0_valid;
+      assign OutValid[7]  = in0_valid;
+      assign OutValid[8]  = in0_valid;
+      assign OutValid[9]  = in0_valid;
+      assign OutValid[10] = in0_valid;
+      assign OutValid[11] = in0_valid;
+      assign OutValid[12] = in0_valid;
+      assign OutValid[13] = in0_valid;
+      assign OutValid[14] = in0_valid;
+      assign OutValid[15] = in0_valid;
+   end
+endgenerate
+
+
+assign OutReady[0]        = out0_ready;
+assign out0_valid         = OutValid[0];
+assign out0_data          = OutData[0];
+assign out0_channel       = OutChannel[0];
+assign out0_error         = OutError[0];
+assign out0_startofpacket = OutSOP[0];
+assign out0_endofpacket   = OutEOP[0];
+assign out0_empty         = OutEmpty[0];
+
+assign OutReady[1]        = out1_ready;
+assign out1_valid         = OutValid[1];
+assign out1_data          = OutData[1];
+assign out1_channel       = OutChannel[1];
+assign out1_error         = OutError[1];
+assign out1_startofpacket = OutSOP[1];
+assign out1_endofpacket   = OutEOP[1];
+assign out1_empty         = OutEmpty[1];
+
+assign OutReady[2]        = out2_ready;
+assign out2_valid         = OutValid[2];
+assign out2_data          = OutData[2];
+assign out2_channel       = OutChannel[2];
+assign out2_error         = OutError[2];
+assign out2_startofpacket = OutSOP[2];
+assign out2_endofpacket   = OutEOP[2];
+assign out2_empty         = OutEmpty[2];
+
+assign OutReady[3]        = out3_ready;
+assign out3_valid         = OutValid[3];
+assign out3_data          = OutData[3];
+assign out3_channel       = OutChannel[3];
+assign out3_error         = OutError[3];
+assign out3_startofpacket = OutSOP[3];
+assign out3_endofpacket   = OutEOP[3];
+assign out3_empty         = OutEmpty[3];
+
+assign OutReady[4]        = out4_ready;
+assign out4_valid         = OutValid[4];
+assign out4_data          = OutData[4];
+assign out4_channel       = OutChannel[4];
+assign out4_error         = OutError[4];
+assign out4_startofpacket = OutSOP[4];
+assign out4_endofpacket   = OutEOP[4];
+assign out4_empty         = OutEmpty[4];
+
+assign OutReady[5]        = out5_ready;
+assign out5_valid         = OutValid[5];
+assign out5_data          = OutData[5];
+assign out5_channel       = OutChannel[5];
+assign out5_error         = OutError[5];
+assign out5_startofpacket = OutSOP[5];
+assign out5_endofpacket   = OutEOP[5];
+assign out5_empty         = OutEmpty[5];
+
+assign OutReady[6]        = out6_ready;
+assign out6_valid         = OutValid[6];
+assign out6_data          = OutData[6];
+assign out6_channel       = OutChannel[6];
+assign out6_error         = OutError[6];
+assign out6_startofpacket = OutSOP[6];
+assign out6_endofpacket   = OutEOP[6];
+assign out6_empty         = OutEmpty[6];
+
+assign OutReady[7]        = out7_ready;
+assign out7_valid         = OutValid[7];
+assign out7_data          = OutData[7];
+assign out7_channel       = OutChannel[7];
+assign out7_error         = OutError[7];
+assign out7_startofpacket = OutSOP[7];
+assign out7_endofpacket   = OutEOP[7];
+assign out7_empty         = OutEmpty[7];
+
+assign OutReady[8]        = out8_ready;
+assign out8_valid         = OutValid[8];
+assign out8_data          = OutData[8];
+assign out8_channel       = OutChannel[8];
+assign out8_error         = OutError[8];
+assign out8_startofpacket = OutSOP[8];
+assign out8_endofpacket   = OutEOP[8];
+assign out8_empty         = OutEmpty[8];
+
+assign OutReady[9]        = out9_ready;
+assign out9_valid         = OutValid[9];
+assign out9_data          = OutData[9];
+assign out9_channel       = OutChannel[9];
+assign out9_error         = OutError[9];
+assign out9_startofpacket = OutSOP[9];
+assign out9_endofpacket   = OutEOP[9];
+assign out9_empty         = OutEmpty[9];
+
+assign OutReady[10]        = out10_ready;
+assign out10_valid         = OutValid[10];
+assign out10_data          = OutData[10];
+assign out10_channel       = OutChannel[10];
+assign out10_error         = OutError[10];
+assign out10_startofpacket = OutSOP[10];
+assign out10_endofpacket   = OutEOP[10];
+assign out10_empty         = OutEmpty[10];
+
+assign OutReady[11]        = out11_ready;
+assign out11_valid         = OutValid[11];
+assign out11_data          = OutData[11];
+assign out11_channel       = OutChannel[11];
+assign out11_error         = OutError[11];
+assign out11_startofpacket = OutSOP[11];
+assign out11_endofpacket   = OutEOP[11];
+assign out11_empty         = OutEmpty[11];
+
+assign OutReady[12]        = out12_ready;
+assign out12_valid         = OutValid[12];
+assign out12_data          = OutData[12];
+assign out12_channel       = OutChannel[12];
+assign out12_error         = OutError[12];
+assign out12_startofpacket = OutSOP[12];
+assign out12_endofpacket   = OutEOP[12];
+assign out12_empty         = OutEmpty[12];
+
+assign OutReady[13]        = out13_ready;
+assign out13_valid         = OutValid[13];
+assign out13_data          = OutData[13];
+assign out13_channel       = OutChannel[13];
+assign out13_error         = OutError[13];
+assign out13_startofpacket = OutSOP[13];
+assign out13_endofpacket   = OutEOP[13];
+assign out13_empty         = OutEmpty[13];
+
+assign OutReady[14]        = out14_ready;
+assign out14_valid         = OutValid[14];
+assign out14_data          = OutData[14];
+assign out14_channel       = OutChannel[14];
+assign out14_error         = OutError[14];
+assign out14_startofpacket = OutSOP[14];
+assign out14_endofpacket   = OutEOP[14];
+assign out14_empty         = OutEmpty[14];
+
+assign OutReady[15]        = out15_ready;
+assign out15_valid         = OutValid[15];
+assign out15_data          = OutData[15];
+assign out15_channel       = OutChannel[15];
+assign out15_error         = OutError[15];
+assign out15_startofpacket = OutSOP[15];
+assign out15_endofpacket   = OutEOP[15];
+assign out15_empty         = OutEmpty[15];
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_default_burst_converter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_default_burst_converter.sv
new file mode 100644
index 0000000..d1dafa0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_default_burst_converter.sv
@@ -0,0 +1,189 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_default_burst_converter.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------------
+// Default Burst Converter
+// Notes:
+//  1) If burst type FIXED and slave is AXI,
+//     passthrough the transaction.
+//  2) Else, converts burst into non-bursting
+//     transactions (length of 1).
+// --------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_default_burst_converter
+#(
+    parameter PKT_BURST_TYPE_W  = 2,
+    parameter PKT_BURSTWRAP_W   = 5,
+    parameter PKT_ADDR_W        = 12,
+    parameter PKT_BURST_SIZE_W  = 3,
+    parameter IS_AXI_SLAVE      = 0,
+    parameter LEN_W             = 2
+)
+(
+    input                                    clk,
+    input                                    reset,
+    input                                    enable,
+
+    input      [PKT_BURST_TYPE_W - 1 : 0]    in_bursttype,
+    input      [PKT_BURSTWRAP_W  - 1 : 0]    in_burstwrap_reg,
+    input      [PKT_BURSTWRAP_W  - 1 : 0]    in_burstwrap_value,
+    input      [PKT_ADDR_W       - 1 : 0]    in_addr,
+    input      [PKT_ADDR_W       - 1 : 0]    in_addr_reg,
+    input      [LEN_W            - 1 : 0]    in_len,
+    input      [PKT_BURST_SIZE_W - 1 : 0]    in_size_value,
+
+    input                                    in_is_write,
+
+    output reg [PKT_ADDR_W       - 1 : 0]    out_addr,
+    output reg [LEN_W            - 1 : 0]    out_len,
+
+    output reg                               new_burst
+);
+
+    // ---------------------------------------------------
+    // AXI Burst Type Encoding
+    // ---------------------------------------------------
+    typedef enum bit  [1:0]
+    {
+     FIXED       = 2'b00,
+     INCR        = 2'b01,
+     WRAP        = 2'b10,
+     RESERVED    = 2'b11
+    } AxiBurstType;
+
+    // -------------------------------------------
+    // Internal Signals
+    // -------------------------------------------
+    wire [LEN_W - 1 : 0]    unit_len = {{LEN_W - 1 {1'b0}}, 1'b1};
+    reg  [LEN_W - 1 : 0]    next_len;
+    reg  [LEN_W - 1 : 0]    remaining_len;
+    reg  [PKT_ADDR_W       - 1 : 0]    next_incr_addr;
+    reg  [PKT_ADDR_W       - 1 : 0]    incr_wrapped_addr;
+    reg  [PKT_ADDR_W       - 1 : 0]    extended_burstwrap_value;
+    reg  [PKT_ADDR_W       - 1 : 0]    addr_incr_variable_size_value;
+
+    // -------------------------------------------
+    // Byte Count Converter
+    // -------------------------------------------
+    // Avalon Slave: Read/Write, the out_len is always 1 (unit_len).
+    // AXI Slave: Read/Write, the out_len is always the in_len (pass through) of a given cycle.
+    //            If bursttype RESERVED, out_len is always 1 (unit_len).
+    generate if (IS_AXI_SLAVE == 1)
+        begin : axi_slave_out_len
+            always_ff @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    out_len <= {LEN_W{1'b0}};
+                end
+                else if (enable) begin
+                    out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
+                end
+            end
+        end
+    else // IS_AXI_SLAVE == 0
+        begin : non_axi_slave_out_len
+            always_comb begin
+                out_len = unit_len;
+            end
+        end
+    endgenerate
+
+
+    always_comb begin : proc_extend_burstwrap
+        extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value};
+        addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value;
+    end
+
+    // -------------------------------------------
+    // Address Converter
+    // -------------------------------------------
+    // Write: out_addr = in_addr at every cycle (pass through).
+    // Read: out_addr = in_addr at every new_burst. Subsequent addresses calculated by converter.
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            next_incr_addr <= {PKT_ADDR_W{1'b0}};
+            out_addr <= {PKT_ADDR_W{1'b0}};
+        end
+        else if (enable) begin
+            next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
+            if (new_burst) begin
+                next_incr_addr <= in_addr + addr_incr_variable_size_value;
+            end
+            out_addr <= incr_wrapped_addr;
+        end
+    end
+
+    always_comb begin
+        incr_wrapped_addr = in_addr;
+        if (!new_burst) begin
+            // This formula calculates addresses of WRAP bursts and works perfectly fine for other burst types too.
+            incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value);
+        end
+    end
+
+    // -------------------------------------------
+    // Control Signals
+    // -------------------------------------------
+
+    // Determine the min_len.
+    //     1) FIXED read to AXI slave: One-time passthrough, therefore the min_len == in_len.
+    //     2) FIXED write to AXI slave: min_len == 1.
+    //     3) FIXED read/write to Avalon slave: min_len == 1.
+    //     4) RESERVED read/write to AXI/Avalon slave: min_len == 1.
+    wire [LEN_W  - 1 : 0] min_len;
+    generate if (IS_AXI_SLAVE == 1)
+        begin : axi_slave_min_len
+            assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len;
+        end
+    else // IS_AXI_SLAVE == 0
+        begin : non_axi_slave_min_len
+            assign min_len = unit_len;
+        end
+    endgenerate
+
+    // last_beat calculation.
+    wire last_beat = (remaining_len == min_len);
+
+    // next_len calculation.
+    always_comb begin
+        remaining_len = in_len;
+        if (!new_burst) remaining_len = next_len;
+    end
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            next_len <= 1'b0;
+        end
+        else if (enable) begin
+            next_len <= remaining_len - unit_len;
+        end
+    end
+
+    // new_burst calculation.
+    always_ff @(posedge clk, posedge reset) begin
+       if (reset) begin
+            new_burst <= 1'b1;
+        end
+        else if (enable) begin
+            new_burst <= last_beat;
+        end
+    end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_dual_boot.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_dual_boot.v
new file mode 100644
index 0000000..cf13580
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_dual_boot.v
@@ -0,0 +1,61 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+module altera_dual_boot
+(
+	clk,
+	nreset,
+	avmm_rcv_address,
+	avmm_rcv_writedata,
+	avmm_rcv_write,
+	avmm_rcv_read,
+	avmm_rcv_readdata
+);
+	parameter LPM_TYPE = "ALTERA_DUAL_BOOT";
+	parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA";
+	parameter A_WIDTH = 3;
+	parameter WD_WIDTH = 4;
+	parameter RD_WIDTH = 17;
+	parameter MAX_DATA_WIDTH = 32;
+	parameter CONFIG_CYCLE = 28;	
+	parameter RESET_TIMER_CYCLE = 40;
+	
+	input clk;
+	input nreset;
+	input [A_WIDTH-1:0] avmm_rcv_address;
+	input [MAX_DATA_WIDTH-1:0] avmm_rcv_writedata;
+	input avmm_rcv_write;
+	input avmm_rcv_read;
+	output [MAX_DATA_WIDTH-1:0] avmm_rcv_readdata;
+	
+	alt_dual_boot_avmm alt_dual_boot_avmm_comp
+	(
+		.clk(clk),
+		.nreset(nreset),
+		.avmm_rcv_address(avmm_rcv_address),
+		.avmm_rcv_writedata(avmm_rcv_writedata),
+		.avmm_rcv_write(avmm_rcv_write),
+		.avmm_rcv_read(avmm_rcv_read),
+		.avmm_rcv_readdata(avmm_rcv_readdata)
+	);
+	defparam
+		alt_dual_boot_avmm_comp.LPM_TYPE = LPM_TYPE,
+		alt_dual_boot_avmm_comp.INTENDED_DEVICE_FAMILY = INTENDED_DEVICE_FAMILY,
+		alt_dual_boot_avmm_comp.A_WIDTH = A_WIDTH,
+		alt_dual_boot_avmm_comp.MAX_DATA_WIDTH = MAX_DATA_WIDTH,
+		alt_dual_boot_avmm_comp.WD_WIDTH = WD_WIDTH,
+		alt_dual_boot_avmm_comp.RD_WIDTH = RD_WIDTH,
+		alt_dual_boot_avmm_comp.CONFIG_CYCLE = CONFIG_CYCLE,
+		alt_dual_boot_avmm_comp.RESET_TIMER_CYCLE = RESET_TIMER_CYCLE;
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller.sv
new file mode 100644
index 0000000..cd211a0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller.sv
@@ -0,0 +1,611 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2015 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1ps / 1ps
+
+module altera_epcq_controller #(
+	parameter CS_WIDTH		= 1,
+	parameter ENABLE_4BYTE_ADDR = 1,
+	parameter ADDR_WIDTH	= 22,
+	parameter ASI_WIDTH		= 1,
+	parameter DEVICE_FAMILY = "CYCLONE V",
+	parameter ASMI_ADDR_WIDTH = 22,
+	parameter CHIP_SELS = 1
+)(
+	input 	wire		  								clk,
+	input 	wire		  								reset_n,
+	                                        			
+	// ports to access csr                        			
+	input 	wire										avl_csr_write,
+	input 	wire		  								avl_csr_read,
+	input 	wire 	[2:0] 								avl_csr_addr,
+	input 	wire 	[31:0] 								avl_csr_wrdata,
+	output 	reg 	[31:0] 								avl_csr_rddata,
+	output 	reg 		 								avl_csr_rddata_valid,
+	output 	reg 			 							avl_csr_waitrequest,
+	                                        			
+	// ports to access memory        			
+	input	wire		  								avl_mem_write,
+	input	wire										avl_mem_read,
+	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
+	input	wire	[31:0]								avl_mem_wrdata,
+	input	wire 	[3:0]								avl_mem_byteenable,
+	input	wire	[6:0]								avl_mem_burstcount,
+	output	wire	[31:0]								avl_mem_rddata,
+	output	reg											avl_mem_rddata_valid,
+	output 	reg 			 							avl_mem_waitrequest,
+	
+	// interrupt signal
+	output	reg 										irq,
+	
+	// Disable dedicated active serial interface
+	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
+	output  reg											epcq_dclk,
+	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
+	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
+	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
+	
+	// ASMI PARALLEL interface
+	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
+	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
+	input   wire 										ddasi_dclk,
+	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
+	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
+	
+	input   wire										asmi_busy,
+	input   wire										asmi_data_valid,
+	input   wire	[7:0]  								asmi_dataout,
+	output  reg											asmi_clkin,
+	output  reg											asmi_reset,
+	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
+	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
+	output  reg		[7:0]  								asmi_datain,
+	output  reg											asmi_fast_read,
+	output  wire										asmi_rden,
+	output  reg											asmi_shift_bytes,
+	output  reg 										asmi_en4b_addr,
+	output  wire										asmi_wren,
+	output  reg											asmi_write,
+	
+	input   wire										asmi_illegal_erase,
+	input   wire										asmi_illegal_write,
+	input   wire	[7:0]  								asmi_rdid_out,
+	input   wire	[7:0]  								asmi_status_out,
+	input   wire	[7:0]  								asmi_epcs_id,
+	output  reg											asmi_read_rdid,
+	output  reg											asmi_read_status,
+	output	reg											asmi_read_sid,
+	output  reg 										asmi_bulk_erase,
+	output  reg											asmi_sector_erase,
+	output  reg											asmi_sector_protect
+);
+	localparam LOCAL_ADDR_WIDTH = ADDR_WIDTH+2;
+	localparam CSR_DATA_WIDTH   = 32;
+	localparam LAST_ADDR_BIT    = (ASMI_ADDR_WIDTH == 24) ? 15 :
+									(ASMI_ADDR_WIDTH == 32) ? 23 : 15;
+	
+	reg  [8:0] wr_burstcount_cnt, rd_burstcount_cnt;
+	reg	 [8:0] rd_mem_burstcount, wr_mem_burstcount;
+	
+	wire last_wr_byte;
+	wire access_csr_status, access_csr_sid, access_csr_rdid, access_csr_mem_op, access_isr, access_imr, access_sce;
+	wire read_status_combi, read_sid_combi, read_rdid_combi, read_isr_combi, read_imr_combi, write_isr_combi, write_imr_combi, write_sce_combi;
+	wire bulk_erase_combi, sector_erase_combi, sector_protect_combi;
+	wire wren_combi, illegal_write_combi, illegal_erase_combi;
+	wire m_illegal_write_combi, m_illegal_erase_combi;
+	wire read_mem_combi, write_mem_combi;
+	wire data_valid_combi, pending_wr_data;
+	wire detect_addroffset;
+	wire [8:0] wfifo_data_in_0, wfifo_data_in_1, wfifo_data_in_2, wfifo_data_in_3;
+	wire [ADDR_WIDTH-1:0] temp_mem_addr;
+	
+	reg reset_n_reg;
+	reg wr_mem_waitrequest, local_waitrequest;
+	reg illegal_write_reg, illegal_erase_reg, m_illegal_write_reg, m_illegal_erase_reg;
+	reg read_status_valid, read_sid_valid, read_rdid_valid, read_isr_valid, read_imr_valid;
+	reg read_status_en, read_sid_en, read_rdid_en;
+	reg wren_internal;
+	reg [LOCAL_ADDR_WIDTH-1:0] wr_mem_addr;
+	reg [7:0] rd_data_reg [4];
+	reg [3:0][8:0] wr_data_reg;
+	reg [1:0] rd_cnt;
+	reg [1:0] wr_cnt;
+	reg [3:0] wr_data_reg_full;
+	reg detect_addroffset_reg, asmi_busy_reg;
+	reg [2:0] temp_sce;
+	
+	// Direct connection
+	assign asmi_clkin 		= clk;
+	assign asmi_reset 		= ~reset_n;
+	assign ddasi_dataout 	= epcq_dataout;
+	assign epcq_dclk 		= ddasi_dclk;
+	assign epcq_scein		= ddasi_scein;
+	assign epcq_sdoin		= ddasi_sdoin;
+	assign epcq_dataoe		= ddasi_dataoe;
+	
+	// chip select
+	generate if (DEVICE_FAMILY == "Arria 10") begin
+		always @(posedge clk or negedge reset_n) begin
+			if (~reset_n) begin
+				asmi_sce			<= {CS_WIDTH{1'b0}};
+			end 
+// to pack the address space this is needed
+			else if (write_mem_combi || read_mem_combi) begin
+				if (CHIP_SELS == 1 ) 					
+					asmi_sce			<= 3'b001;
+				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 0) 
+					asmi_sce			<= 3'b001;
+				else if (CHIP_SELS == 2 && avl_mem_addr[ADDR_WIDTH-1] == 1) 
+					asmi_sce			<= 3'b010;
+				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1] == 1)	
+					asmi_sce			<= 3'b100;
+				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 0) 	
+					asmi_sce			<= 3'b001;
+				else if (CHIP_SELS == 3 && avl_mem_addr[ADDR_WIDTH-1:ADDR_WIDTH-2] == 1) 	
+					asmi_sce			<= 3'b010;
+				else
+					asmi_sce			<= {CS_WIDTH{1'b0}};
+			end
+			else if (write_sce_combi) begin
+				asmi_sce			<= avl_csr_wrdata[2:0];
+			end
+			else if (asmi_en4b_addr) begin
+				asmi_sce			<= temp_sce;
+			end
+		end
+// decoder ring  if the CHIP_SEL is only 1 then avalon address is the temp address
+//		if the chipsele is 2 then need to remove top address bit
+//		if the chipelect is 3 then remove the top 2 address bits.  
+		assign temp_mem_addr	= CHIP_SELS == 1 ? avl_mem_addr:( CHIP_SELS == 2 ? {1'b0,avl_mem_addr[ADDR_WIDTH-2:0]}:{2'b00,avl_mem_addr[ADDR_WIDTH-3:0]});
+	end
+	else begin
+		always @(posedge clk) begin
+			asmi_sce				<= {CS_WIDTH{1'b0}};
+		end
+		assign temp_mem_addr	= avl_mem_addr;
+	end
+	endgenerate
+	
+	// wait_request generation logic
+	assign avl_mem_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
+	assign avl_csr_waitrequest = (asmi_busy || asmi_busy_reg) ? 1'b1 : (local_waitrequest || wr_mem_waitrequest);
+	
+	// access CSR decoding logic
+	assign access_csr_status	= (avl_csr_addr == 3'b000);
+	assign access_csr_sid		= (avl_csr_addr == 3'b001);
+	assign access_csr_rdid		= (avl_csr_addr == 3'b010);
+	assign access_csr_mem_op	= (avl_csr_addr == 3'b011);
+	assign access_isr			= (avl_csr_addr == 3'b100);
+	assign access_imr			= (avl_csr_addr == 3'b101);
+	assign access_sce			= (avl_csr_addr == 3'b110);
+	
+	// read/write memory combi logic
+	assign read_mem_combi		= (avl_mem_read && ~avl_mem_waitrequest);
+	assign write_mem_combi		= (avl_mem_write && ~avl_mem_waitrequest);
+
+	// read csr logic
+	assign read_status_combi	= (avl_csr_read && access_csr_status && ~avl_csr_waitrequest);
+	assign read_sid_combi		= (avl_csr_read && access_csr_sid && ~avl_csr_waitrequest);
+	assign read_rdid_combi		= (avl_csr_read && access_csr_rdid && ~avl_csr_waitrequest);
+	assign read_isr_combi		= (avl_csr_read && access_isr && ~avl_csr_waitrequest);
+	assign read_imr_combi		= (avl_csr_read && access_imr && ~avl_csr_waitrequest);
+	assign write_isr_combi		= (avl_csr_write && access_isr && ~avl_csr_waitrequest);
+	assign write_imr_combi		= (avl_csr_write && access_imr && ~avl_csr_waitrequest);
+	assign write_sce_combi		= (avl_csr_write && access_sce && ~avl_csr_waitrequest);
+	
+	// write csr logic
+	assign bulk_erase_combi		= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b01);
+	assign sector_erase_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b10);
+	assign sector_protect_combi	= (avl_csr_write && access_csr_mem_op && ~avl_csr_waitrequest && avl_csr_wrdata[1:0] == 2'b11);
+	assign illegal_write_combi	= (asmi_illegal_write) ? 1'b1 :
+									(write_isr_combi && avl_csr_wrdata[1]) ? 1'b0 : 
+										illegal_write_reg;
+	assign illegal_erase_combi	= (asmi_illegal_erase) ? 1'b1 :
+									(write_isr_combi && avl_csr_wrdata[0]) ? 1'b0 : 
+										illegal_erase_reg;
+	assign m_illegal_write_combi= (write_imr_combi) ? avl_csr_wrdata[1] : m_illegal_write_reg;
+	assign m_illegal_erase_combi= (write_imr_combi) ? avl_csr_wrdata[0] : m_illegal_erase_reg;
+	assign wren_combi			= (sector_protect_combi || sector_erase_combi || bulk_erase_combi);
+										
+	assign asmi_rden			= (rd_burstcount_cnt > 9'd0);		// deasserted at the last 2 byte - refer to ASMI_PARALLEL UG
+
+	// interrupt signal
+	assign irq = (illegal_write_reg && m_illegal_write_reg) || (illegal_erase_reg && m_illegal_erase_reg);
+	
+	assign last_wr_byte = (wr_burstcount_cnt == wr_mem_burstcount - 9'd1) ? 1'b1 : 1'b0;
+	
+	assign asmi_wren = wren_internal || asmi_en4b_addr || asmi_shift_bytes || asmi_write;
+	
+	assign data_valid_combi = (rd_burstcount_cnt[1:0] == 2'b00) ? asmi_data_valid : 1'b0;
+	
+	assign wfifo_data_in_0 = {avl_mem_byteenable[0], avl_mem_wrdata[7:0]   };
+	assign wfifo_data_in_1 = {avl_mem_byteenable[1], avl_mem_wrdata[15:8]  };
+	assign wfifo_data_in_2 = {avl_mem_byteenable[2], avl_mem_wrdata[23:16] };
+	assign wfifo_data_in_3 = {avl_mem_byteenable[3], avl_mem_wrdata[31:24] };
+	
+	assign avl_mem_rddata  = {rd_data_reg[3], rd_data_reg[2], rd_data_reg[1], rd_data_reg[0]};
+	assign pending_wr_data = (|wr_data_reg_full) ? 1'b1 : 1'b0;
+	assign detect_addroffset = (pending_wr_data && wr_data_reg[wr_cnt][8]) ? 1'b1 : 
+								(wr_burstcount_cnt == {9{1'b0}}) ? 1'b0 : detect_addroffset_reg;
+
+	//-------------------------------- array to store write data -------------------------------------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			wr_data_reg			<= '{{9{1'b0}}, {9{1'b0}}, {9{1'b0}}, {9{1'b0}}};
+			wr_data_reg_full	<= {4{1'b0}};
+		end 
+		else if (write_mem_combi) begin
+			wr_data_reg			<= {wfifo_data_in_3, wfifo_data_in_2, wfifo_data_in_1, wfifo_data_in_0};
+			wr_data_reg_full	<= {4{1'b1}};
+		end
+		else if (wr_data_reg_full > 4'b0000) begin
+			wr_data_reg_full	<= wr_data_reg_full << 1;
+		end
+	end
+	
+	//-------------------------------- array to store read data -------------------------------------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			rd_data_reg			<= '{{8{1'b0}}, {8{1'b0}}, {8{1'b0}}, {8{1'b0}}};
+			rd_cnt				<= {2{1'b0}};
+		end 
+		else if (asmi_data_valid) begin
+			rd_data_reg[rd_cnt]	<= asmi_dataout;
+			rd_cnt				<= rd_cnt + 2'b01;
+		end
+	end
+	
+	//------------------------------- Enable 4-byte addressing out of reset ----------------------
+	generate 
+	if (ENABLE_4BYTE_ADDR) begin
+		typedef enum logic[1:0] {EN4B_CHIP1, EN4B_CHIP2, EN4B_CHIP3, IDLE} state_t;
+		state_t state;
+	
+		always @(posedge clk or negedge reset_n_reg) begin	// use reset_n_reg because user is allow to send cmd to ASMI_PARALLEL 2 clock cycles after reset
+			if (~reset_n_reg) begin	
+				state					<= EN4B_CHIP1;
+				asmi_en4b_addr			<= 1'b1;
+				temp_sce				<= 3'b001;
+			end
+			else begin
+				case (state)
+					EN4B_CHIP1 : begin
+									asmi_en4b_addr			<= 1'b1;
+									if (~asmi_busy) begin
+										if (CHIP_SELS > 1) begin
+											state					<= EN4B_CHIP2;
+											temp_sce				<= 3'b010;
+										end
+										else begin
+											state					<= IDLE;
+											temp_sce				<= 3'b000;
+										end
+									end
+								 end
+					EN4B_CHIP2 : begin
+									asmi_en4b_addr			<= 1'b1;
+									if (~asmi_busy) begin
+										if (CHIP_SELS > 2) begin
+											state					<= EN4B_CHIP3;
+											temp_sce				<= 3'b100;
+										end
+										else begin
+											state					<= IDLE;
+											temp_sce				<= 3'b000;
+										end
+									end
+								 end
+					EN4B_CHIP3 : begin
+									asmi_en4b_addr			<= 1'b1;
+									if (~asmi_busy) begin
+										state					<= IDLE;
+										temp_sce				<= 3'b000;
+									end
+								 end
+					IDLE	   : begin
+									asmi_en4b_addr			<= 1'b0;
+									state					<= IDLE;
+									temp_sce				<= 3'b000;
+								 end
+					default : 	 begin
+									asmi_en4b_addr			<= 1'b0;
+									state					<= IDLE;
+									temp_sce				<= 3'b000;
+								 end
+				endcase
+			end
+		end
+	end
+	else begin
+		always @(posedge clk) begin
+			asmi_en4b_addr				<= 1'b0;
+			temp_sce					<= 3'b000;
+		end
+	end
+	endgenerate
+	
+	//--------------------------------------- Waitrequest logic ----------------------------------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			wr_mem_waitrequest			<= 1'b0;
+			local_waitrequest			<= 1'b0;
+		end
+		else begin
+			if (read_mem_combi || read_status_combi || read_sid_combi || read_rdid_combi || bulk_erase_combi || sector_erase_combi || sector_protect_combi || asmi_en4b_addr) begin		// no back pressure during imr & isr access
+				local_waitrequest		<= 1'b1;
+			end
+			else if (asmi_busy_reg && ~asmi_busy) begin
+				local_waitrequest		<= 1'b0;
+			end
+			
+			if (write_mem_combi) begin
+				wr_mem_waitrequest	<= 1'b1;
+			end
+			else if ((~pending_wr_data && ~asmi_write) || asmi_busy_reg && ~asmi_busy) begin
+				wr_mem_waitrequest	<= 1'b0;
+			end
+		end
+	end
+	
+	// -------------------------------------- MEM ACCESS -----------------------------------------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			rd_mem_burstcount			<= {9{1'b0}};
+			wr_mem_burstcount			<= {9{1'b0}};
+			wr_mem_addr					<= {LOCAL_ADDR_WIDTH{1'b0}};
+		end
+		else begin
+			if (read_mem_combi) begin
+				rd_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
+			end
+			if (write_mem_combi && (wr_burstcount_cnt == {9{1'b0}})) begin
+				wr_mem_addr				<= {temp_mem_addr, 2'b00};
+				wr_mem_burstcount		<= {avl_mem_burstcount, 2'b00}; 
+			end
+		end
+	end
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			wr_burstcount_cnt				<= {9{1'b0}};
+		end
+		else begin
+			if (pending_wr_data) begin
+				wr_burstcount_cnt			<= wr_burstcount_cnt + 9'd1;
+			end
+			else if (wr_burstcount_cnt == wr_mem_burstcount) begin
+				wr_burstcount_cnt			<= {9{1'b0}};
+			end
+		end
+	end
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			rd_burstcount_cnt				<= {9{1'b0}};
+		end
+		else begin
+			if (read_mem_combi) begin
+				rd_burstcount_cnt			<= 9'd1;
+			end
+			else if (rd_burstcount_cnt == rd_mem_burstcount) begin		// each rd 4 burst
+				rd_burstcount_cnt			<= {9{1'b0}};
+			end
+			else if (asmi_data_valid && rd_burstcount_cnt > 0) begin
+				rd_burstcount_cnt			<= rd_burstcount_cnt + 9'd1;
+			end
+		end
+	end
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			asmi_addr					<= {ASMI_ADDR_WIDTH{1'b0}};
+		end
+		else begin
+			if (sector_erase_combi) begin // set lower 16 bits to zero so that erase at starting address of each sector
+				asmi_addr				<= {avl_csr_wrdata[LAST_ADDR_BIT : 8], {16{1'b0}}};	
+			end
+			if (read_mem_combi) begin
+				asmi_addr				<= {temp_mem_addr, 2'b00};
+			end
+			
+			if (detect_addroffset && ~detect_addroffset_reg) begin
+				asmi_addr			<= wr_mem_addr + {{LOCAL_ADDR_WIDTH-9{1'b0}}, wr_burstcount_cnt};
+			end
+
+		end
+	end
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			asmi_datain					<= {8{1'b0}};
+			wr_cnt						<= {2{1'b0}};
+			asmi_shift_bytes			<= 1'b0;
+		end
+		else begin
+			if (sector_protect_combi) begin
+				asmi_datain				<= {{1{1'b0}}, avl_csr_wrdata[11], avl_csr_wrdata[12], avl_csr_wrdata[10:8], {2{1'b0}}};	// BP3, TB, BP2, BP1, BP0
+			end
+			if (pending_wr_data) begin
+				asmi_datain				<= wr_data_reg[wr_cnt][7:0];
+				wr_cnt					<= wr_cnt + 2'd1;
+			end
+			if (pending_wr_data && wr_data_reg[wr_cnt][8]) begin
+				asmi_shift_bytes		<= 1'b1;
+			end
+			else begin
+				asmi_shift_bytes		<= 1'b0;
+			end
+		end
+	end
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			asmi_read_status			<= 1'b0;
+			asmi_read_sid				<= 1'b0;
+			asmi_read_rdid				<= 1'b0;
+			asmi_bulk_erase				<= 1'b0;
+			asmi_sector_erase			<= 1'b0;
+			asmi_sector_protect			<= 1'b0;
+			wren_internal				<= 1'b0;
+			asmi_write					<= 1'b0;
+			asmi_fast_read				<= 1'b0;
+			asmi_busy_reg				<= 1'b0;
+			avl_mem_rddata_valid		<= 1'b0;
+			detect_addroffset_reg		<= 1'b0;
+			reset_n_reg					<= 1'b0;
+		end
+		else begin
+			asmi_read_status			<= read_status_combi;
+			asmi_read_sid				<= read_sid_combi;
+			asmi_read_rdid				<= read_rdid_combi;
+			asmi_bulk_erase				<= bulk_erase_combi;
+			asmi_sector_erase			<= sector_erase_combi;				
+			asmi_sector_protect			<= sector_protect_combi;
+			wren_internal				<= wren_combi;
+			asmi_write					<= last_wr_byte;
+			asmi_fast_read				<= read_mem_combi;
+			asmi_busy_reg				<= asmi_busy;
+			avl_mem_rddata_valid		<= data_valid_combi;
+			detect_addroffset_reg		<= detect_addroffset;
+			reset_n_reg					<= 1'b1;
+		end
+	end
+	
+	// --------------------------------------------- CSR ACCESS -------------------------------------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			illegal_write_reg			<= 1'b0;
+			illegal_erase_reg			<= 1'b0;
+			m_illegal_write_reg			<= 1'b0;
+			m_illegal_erase_reg			<= 1'b0;
+		end
+		else begin
+			illegal_write_reg			<= illegal_write_combi;
+			illegal_erase_reg			<= illegal_erase_combi;
+			m_illegal_write_reg			<= m_illegal_write_combi;
+			m_illegal_erase_reg			<= m_illegal_erase_combi;
+		end
+	end
+	
+	// csr read only registers enable logic
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			read_status_en				<= 1'b0;
+			read_sid_en 				<= 1'b0;
+			read_rdid_en				<= 1'b0;
+		end
+		else if (asmi_read_status) begin
+			read_status_en				<= 1'b1;
+		end
+		else if (asmi_read_sid) begin
+			read_sid_en					<= 1'b1;
+		end
+		else if (asmi_read_rdid) begin
+			read_rdid_en				<= 1'b1;
+		end
+		else if (asmi_busy == 0) begin
+			read_status_en				<= 1'b0;
+			read_sid_en 				<= 1'b0;
+			read_rdid_en				<= 1'b0;
+		end
+	end
+	
+	// generation logic for avl csr read data valid
+	assign avl_csr_rddata_valid	= read_status_valid || read_sid_valid || read_rdid_valid || read_isr_valid || read_imr_valid;
+	
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			read_status_valid			<= 1'b0;
+			read_sid_valid				<= 1'b0;
+			read_rdid_valid				<= 1'b0;
+			read_isr_valid				<= 1'b0;
+			read_imr_valid				<= 1'b0;
+		end
+		else begin
+			if (read_status_en && asmi_busy == 0) begin
+				read_status_valid			<= 1'b1;
+			end
+			else begin
+				read_status_valid			<= 1'b0;
+			end
+			
+			if (read_sid_en && asmi_busy == 0) begin
+				read_sid_valid				<= 1'b1;
+			end
+			else begin
+				read_sid_valid				<= 1'b0;
+			end
+			
+			if (read_rdid_en && asmi_busy == 0) begin
+				read_rdid_valid				<= 1'b1;
+			end
+			else begin
+				read_rdid_valid				<= 1'b0;
+			end
+			
+			if (read_isr_combi) begin
+				read_isr_valid				<= 1'b1;
+			end
+			else begin
+				read_isr_valid				<= 1'b0;
+			end
+			
+			if (read_imr_combi) begin
+				read_imr_valid				<= 1'b1;
+			end
+			else begin
+				read_imr_valid				<= 1'b0;
+			end
+		end
+	end
+	
+	// generation logic for avl csr read data
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			avl_csr_rddata				<= {CSR_DATA_WIDTH{1'b0}};
+		end
+		else begin
+			if (read_status_en && asmi_busy == 0) begin
+				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_status_out};
+			end
+			if (read_sid_en && asmi_busy == 0) begin
+				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_epcs_id};
+			end
+			if (read_rdid_en && asmi_busy == 0) begin
+				avl_csr_rddata				<= {{CSR_DATA_WIDTH-8{1'b0}}, asmi_rdid_out};
+			end
+			if (read_isr_combi) begin
+				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, illegal_write_reg, illegal_erase_reg};
+			end
+			if (read_imr_combi) begin
+				avl_csr_rddata				<= {{CSR_DATA_WIDTH-2{1'b0}}, m_illegal_write_reg, m_illegal_erase_reg};
+			end
+		end
+	end
+	
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv
new file mode 100644
index 0000000..2793347
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv
@@ -0,0 +1,230 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+`timescale 1ps / 1ps
+
+module altera_epcq_controller_arb #(
+	parameter CS_WIDTH		= 1,
+	parameter ENABLE_4BYTE_ADDR = 1,
+	parameter ADDR_WIDTH	= 22,
+	parameter ASI_WIDTH		= 1,
+	parameter DEVICE_FAMILY = "CYCLONE V",
+	parameter ASMI_ADDR_WIDTH = 22,
+	parameter CHIP_SELS = 1
+)(
+	input 	wire		  								clk,
+	input 	wire		  								reset_n,
+	                                        			
+	// ports to access csr                        			
+	input 	wire										avl_csr_write,
+	input 	wire		  								avl_csr_read,
+	input 	wire 	[2:0] 								avl_csr_addr,
+	input 	wire 	[31:0] 								avl_csr_wrdata,
+	output 	reg 	[31:0] 								avl_csr_rddata,
+	output 	reg 		 								avl_csr_rddata_valid,
+	output 	reg 			 							avl_csr_waitrequest,
+	                                        			
+	// ports to access memory        			
+	input	wire		  								avl_mem_write,
+	input	wire										avl_mem_read,
+	input	wire  	[ADDR_WIDTH-1:0]					avl_mem_addr,			
+	input	wire	[31:0]								avl_mem_wrdata,
+	input	wire 	[3:0]								avl_mem_byteenable,
+	input	wire	[6:0]								avl_mem_burstcount,
+	output	wire	[31:0]								avl_mem_rddata,
+	output	reg											avl_mem_rddata_valid,
+	output 	reg 			 							avl_mem_waitrequest,
+	
+	// interrupt signal
+	output	reg 										irq,
+	
+	// Disable dedicated active serial interface
+	input  	wire	[ASI_WIDTH-1:0]						epcq_dataout,
+	output  reg											epcq_dclk,
+	output  reg		[CS_WIDTH-1:0] 						epcq_scein,
+	output  reg		[ASI_WIDTH-1:0]						epcq_sdoin,
+	output  reg		[ASI_WIDTH-1:0]						epcq_dataoe,
+	
+	// ASMI PARALLEL interface
+	input   wire	[ASI_WIDTH-1:0]						ddasi_dataoe,
+	output  reg 	[ASI_WIDTH-1:0]						ddasi_dataout,
+	input   wire 										ddasi_dclk,
+	input   wire 	[CS_WIDTH-1:0] 						ddasi_scein,
+	input   reg		[ASI_WIDTH-1:0]  					ddasi_sdoin,
+	
+	input   wire										asmi_busy,
+	input   wire										asmi_data_valid,
+	input   wire	[7:0]  								asmi_dataout,
+	output  reg											asmi_clkin,
+	output  reg											asmi_reset,
+	output  reg		[CS_WIDTH-1:0] 						asmi_sce,
+	output	reg	    [ASMI_ADDR_WIDTH-1:0]  				asmi_addr,
+	output  reg		[7:0]  								asmi_datain,
+	output  reg											asmi_fast_read,
+	output  wire										asmi_rden,
+	output  reg											asmi_shift_bytes,
+	output  reg 										asmi_en4b_addr,
+	output  wire										asmi_wren,
+	output  reg											asmi_write,
+	
+	input   wire										asmi_illegal_erase,
+	input   wire										asmi_illegal_write,
+	input   wire	[7:0]  								asmi_rdid_out,
+	input   wire	[7:0]  								asmi_status_out,
+	input   wire	[7:0]  								asmi_epcs_id,
+	output  reg											asmi_read_rdid,
+	output  reg											asmi_read_status,
+	output	reg											asmi_read_sid,
+	output  reg 										asmi_bulk_erase,
+	output  reg											asmi_sector_erase,
+	output  reg											asmi_sector_protect
+);
+
+	reg temp_mem_write, temp_mem_read, mem_write, mem_read, back_pressured_ctrl;
+	reg [ADDR_WIDTH-1:0] temp_mem_addr, mem_addr;		
+	reg [31:0] temp_mem_wrdata, mem_wrdata;
+	reg [3:0] temp_mem_byteenable, mem_byteenable;
+	reg [6:0] temp_mem_burstcount, mem_burstcount;
+	
+	wire back_pressured, temp_csr_waitrequest, temp_mem_waitrequest;
+
+	//-------------------- Arbitration logic between avalon csr and mem interface -----------
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			back_pressured_ctrl		<= 1'b0;
+		end 
+		else if (back_pressured) begin
+			back_pressured_ctrl		<= 1'b1;
+		end
+		else if (~temp_csr_waitrequest) begin
+			back_pressured_ctrl		<= 1'b0;
+		end
+	end
+
+	always @(posedge clk or negedge reset_n) begin
+		if (~reset_n) begin
+			mem_write 			<= 1'b0;
+			mem_read 			<= 1'b0;
+			mem_addr			<= {ADDR_WIDTH{1'b0}};
+			mem_wrdata			<= {32{1'b0}};
+			mem_byteenable		<= {4{1'b0}};
+			mem_burstcount		<= {7{1'b0}};
+		end 
+		else if ((avl_csr_write || avl_csr_read) && ~avl_csr_waitrequest && (avl_mem_write || avl_mem_read) && ~avl_mem_waitrequest) begin
+			// to back pressure master
+			mem_write 			<= avl_mem_write;
+			mem_read 			<= avl_mem_read;
+			mem_addr			<= avl_mem_addr;
+			mem_wrdata			<= avl_mem_wrdata;
+			mem_byteenable		<= avl_mem_byteenable;
+			mem_burstcount		<= avl_mem_burstcount;
+		end
+	end
+	
+	assign back_pressured	   = ((avl_csr_write || avl_csr_read) && ~temp_csr_waitrequest && (avl_mem_write || avl_mem_read)) ? 1'b1 : 1'b0; // to back pressure controller
+	assign avl_csr_waitrequest = (~avl_csr_write && ~avl_csr_read && back_pressured_ctrl) ? 1'b1 : temp_csr_waitrequest;
+	assign avl_mem_waitrequest = (back_pressured_ctrl) ? 1'b1 : temp_mem_waitrequest;
+	assign temp_mem_write	   = (back_pressured) ? 1'b0 :
+									(back_pressured_ctrl) ? mem_write : avl_mem_write;
+	assign temp_mem_read	   = (back_pressured) ? 1'b0 :
+									(back_pressured_ctrl) ? mem_read : avl_mem_read;
+	assign temp_mem_addr	   = (back_pressured) ? {ADDR_WIDTH{1'b0}} :
+									(back_pressured_ctrl) ? mem_addr : avl_mem_addr;
+	assign temp_mem_wrdata	   = (back_pressured) ? {32{1'b0}} :
+									(back_pressured_ctrl) ? mem_wrdata : avl_mem_wrdata;
+	assign temp_mem_byteenable = (back_pressured) ? {4{1'b0}} :
+									(back_pressured_ctrl) ? mem_byteenable : avl_mem_byteenable;
+	assign temp_mem_burstcount = (back_pressured) ? {7{1'b0}} :
+									(back_pressured_ctrl) ? mem_burstcount : avl_mem_burstcount;
+	
+	
+	//---------------------------------------------------------------------------------------//
+	
+	altera_epcq_controller #(
+		.CS_WIDTH		   (CS_WIDTH),
+		.DEVICE_FAMILY     (DEVICE_FAMILY),
+		.ADDR_WIDTH        (ADDR_WIDTH),
+		.ASMI_ADDR_WIDTH   (ASMI_ADDR_WIDTH),
+		.ASI_WIDTH         (ASI_WIDTH),
+		.CHIP_SELS	 (CHIP_SELS),
+		.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR)
+	) controller (
+		.clk                  (clk),                  
+		.reset_n              (reset_n),              
+		.avl_csr_read         (avl_csr_read),         
+		.avl_csr_waitrequest  (temp_csr_waitrequest),  
+		.avl_csr_write        (avl_csr_write),        
+		.avl_csr_addr         (avl_csr_addr),         
+		.avl_csr_wrdata       (avl_csr_wrdata),       
+		.avl_csr_rddata       (avl_csr_rddata),       
+		.avl_csr_rddata_valid (avl_csr_rddata_valid), 
+		.avl_mem_write        (temp_mem_write),        
+		.avl_mem_burstcount   (temp_mem_burstcount),   
+		.avl_mem_waitrequest  (temp_mem_waitrequest),  
+		.avl_mem_read         (temp_mem_read),         
+		.avl_mem_addr         (temp_mem_addr),         
+		.avl_mem_wrdata       (temp_mem_wrdata),
+		.avl_mem_byteenable   (temp_mem_byteenable),
+		.avl_mem_rddata       (avl_mem_rddata),       
+		.avl_mem_rddata_valid (avl_mem_rddata_valid), 
+		.asmi_status_out      (asmi_status_out),      
+		.asmi_epcs_id         (asmi_epcs_id),         
+		.asmi_illegal_erase   (asmi_illegal_erase),   
+		.asmi_illegal_write   (asmi_illegal_write),   
+		.ddasi_dataoe         (ddasi_dataoe),         
+		.ddasi_dclk           (ddasi_dclk),           
+		.ddasi_scein          (ddasi_scein),          
+		.ddasi_sdoin          (ddasi_sdoin),          
+		.asmi_busy            (asmi_busy),            
+		.asmi_data_valid      (asmi_data_valid),      
+		.asmi_dataout         (asmi_dataout),         
+		.epcq_dataout         (epcq_dataout),         
+		.ddasi_dataout        (ddasi_dataout),        
+		.asmi_read_rdid       (asmi_read_rdid),       
+		.asmi_read_status     (asmi_read_status),     
+		.asmi_read_sid        (asmi_read_sid),        
+		.asmi_bulk_erase      (asmi_bulk_erase),      
+		.asmi_sector_erase    (asmi_sector_erase),    
+		.asmi_sector_protect  (asmi_sector_protect),  
+		.epcq_dclk            (epcq_dclk),            
+		.epcq_scein           (epcq_scein),           
+		.epcq_sdoin           (epcq_sdoin),           
+		.epcq_dataoe          (epcq_dataoe),          
+		.asmi_clkin           (asmi_clkin),           
+		.asmi_reset           (asmi_reset),           
+		.asmi_sce			  (asmi_sce),
+		.asmi_addr            (asmi_addr),            
+		.asmi_datain          (asmi_datain),          
+		.asmi_fast_read       (asmi_fast_read),       
+		.asmi_rden            (asmi_rden),            
+		.asmi_shift_bytes     (asmi_shift_bytes),     
+		.asmi_wren            (asmi_wren),            
+		.asmi_write           (asmi_write),           
+		.asmi_rdid_out        (asmi_rdid_out),        
+		.asmi_en4b_addr       (asmi_en4b_addr),       
+		.irq                  (irq)                   
+	);                                                
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc
new file mode 100644
index 0000000..90b8629
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc
@@ -0,0 +1,303 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# CORE_PARAMETERS
+set IS_SMALLMAC 0
+set ENABLE_SUP_ADDR 0
+set ENABLE_MAC_FLOW_CTRL 0
+set ENABLE_MAGIC_DETECT 1
+set ENABLE_HD_LOGIC 1
+set ENABLE_ENA 32
+set ENABLE_GMII_LOOPBACK 1
+set STAT_CNT_ENA 1
+
+set old_mode [set_project_mode -get_mode_value always_show_entity_name] 
+set_project_mode -always_show_entity_name on
+
+# Function to constraint non-std_synchronizer path
+proc altera_eth_tse_constraint_net_delay {from_reg to_reg max_net_delay} {
+   
+   set_net_delay -from [get_pins -compatibility_mode ${from_reg}|q] -to [get_registers ${to_reg}] -max $max_net_delay
+   
+   if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+      set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 100ns
+      set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+   } else {
+      # Relax the fitter effort
+      set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 8ns
+      set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+   }
+   
+}
+
+# Function to constraint std_synchronizer
+proc altera_eth_tse_constraint_std_sync {} {
+   
+   altera_eth_tse_constraint_net_delay  *  *altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1  6ns
+   
+}
+
+# Function to constraint pointers
+proc altera_eth_tse_constraint_ptr {from_path from_reg to_path to_reg max_skew max_net_delay} {
+   
+   set_net_delay -from [get_pins -compatibility_mode *${from_path}|${from_reg}[*]|q] -to [get_registers *${to_path}|${to_reg}*] -max $max_net_delay
+   
+   if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+      # Check for instances
+      set inst [get_registers -nowarn *${from_path}|${from_reg}\[0\]]
+      
+      # Check number of instances
+      set inst_num [llength [query_collection -report -all $inst]]
+      if {$inst_num > 0} {
+         # Uncomment line below for debug purpose
+         #puts "${inst_num} ${from_path}|${from_reg} instance(s) found"
+      } else {
+         # Uncomment line below for debug purpose
+         #puts "No ${from_path}|${from_reg} instance found"
+      }
+      
+      # Constraint one instance at a time to avoid set_max_skew apply to all instances
+      foreach_in_collection each_inst_tmp $inst {
+      set each_inst [get_node_info -name $each_inst_tmp] 
+         # Get the path to instance
+         regexp "(.*${from_path})(.*|)(${from_reg})" $each_inst reg_path inst_path inst_name reg_name
+         
+         set_max_skew -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] $max_skew
+         
+         set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 100ns
+         set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+      }
+      
+   } else {
+      # Relax the fitter effort
+      set_max_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 8ns
+      set_min_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+   }
+   
+}
+
+# Function to constraint clock crosser
+proc altera_eth_tse_constraint_clock_crosser {} {
+    set module_name altera_tse_clock_crosser
+    
+    set from_reg1 in_data_toggle
+    set to_reg1 altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+    
+    set from_reg2 in_data_buffer
+    set to_reg2 out_data_buffer
+    
+    set from_reg3 out_data_toggle_flopped
+    set to_reg3 altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+    
+    set max_skew 7.5ns
+    
+    set max_delay1 6ns
+    set max_delay2 4ns
+    set max_delay3 6ns
+
+    # Check for clock crosser instances
+    set inst [get_registers -nowarn *${module_name}:*|${from_reg1}]
+    
+    # Check number of instances
+    set inst_num [llength [query_collection -report -all $inst]]
+    
+    # Apply constraint if clock crosser exist
+    if {$inst_num > 0} {
+    
+        # Constraint one instance at a time to avoid set_max_skew apply to all instances
+        foreach_in_collection each_inst_tmp $inst {
+        set each_inst [get_node_info -name $each_inst_tmp] 
+        
+            # Get the path to instance
+            regexp "(.*${module_name})(:.*|)(${from_reg1})" $each_inst reg_path inst_path inst_name reg_name
+            # Check if data buffer of the clock crosser instance exists or get synthesized away
+            set reg2_collection [get_registers -nowarn ${inst_path}${inst_name}${to_reg2}[*]]
+            set reg2_num [llength [query_collection -report -all $reg2_collection]]
+             
+            # Apply constraints common in both STA and FIT
+            set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg1}|q]    -to [get_registers *${module_name}:*|${to_reg1}] -max $max_delay1
+            set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg3}|q]    -to [get_registers *${module_name}:*|${to_reg3}] -max $max_delay3
+            if {$reg2_num > 0} {
+                set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg2}[*]|q] -to [get_registers *${module_name}:*|${to_reg2}[*]] -max $max_delay2
+            }
+            
+            # Apply constraints specific to STA
+            if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+                if {$reg2_num > 0} {
+                    set_max_skew -from [get_registers "${inst_path}${inst_name}${from_reg1} ${inst_path}${inst_name}${from_reg2}[*]"] -to [get_registers "${inst_path}${inst_name}${to_reg1} ${inst_path}${inst_name}${to_reg2}[*]"] $max_skew
+                    
+                    set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] 100ns
+                    set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] -100ns
+                }
+                
+                set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] 100ns
+                set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] -100ns
+                
+                set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] 100ns
+                set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] -100ns
+            
+            # Apply constraints specific to FIT
+            } else {
+                # Relax the fitter effort
+                set_max_delay -from [get_registers *${module_name}:*|${from_reg1}]    -to [get_registers *${module_name}:*|${to_reg1}] 8ns
+                set_min_delay -from [get_registers *${module_name}:*|${from_reg1}]    -to [get_registers *${module_name}:*|${to_reg1}] -100ns
+                if {$reg2_num > 0} {
+                    set_max_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] 8ns
+                    set_min_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] -100ns
+                }
+                set_max_delay -from [get_registers *${module_name}:*|${from_reg3}]    -to [get_registers *${module_name}:*|${to_reg3}] 8ns
+                set_min_delay -from [get_registers *${module_name}:*|${from_reg3}]    -to [get_registers *${module_name}:*|${to_reg3}] -100ns
+            }
+        }
+    }
+}
+
+# Constraint Standard Synchronizer
+altera_eth_tse_constraint_std_sync
+
+if {[expr $IS_SMALLMAC == 1]} {
+   # Small MAC
+   set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|command_config[9]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   
+   set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+} else {
+   # MAC with FIFO
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[9]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+   set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|frm_length[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+   
+   if {[expr ($ENABLE_SUP_ADDR == 1)]} {
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[16]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[17]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[18]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+   
+   }
+   
+   if {[expr ($ENABLE_MAC_FLOW_CTRL == 1)]} {
+      set_false_path -from [get_registers *|altera_tse_mac_rx:*|pause_quant_val*] -to [get_registers *|altera_tse_mac_tx:*|pause_latch*]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|pause_quant_reg*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|pause_quant_reg*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|holdoff_quant*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+   }
+
+   # Magic packet detection 
+   if {[expr ($ENABLE_MAGIC_DETECT == 1)]} {
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+      set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+
+      if {[expr ($ENABLE_SUP_ADDR == 1)]} {
+         set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+         set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+         set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+         set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+      }
+   }
+
+   altera_eth_tse_constraint_clock_crosser
+
+}
+
+# FIFO at Avalon-ST user interface
+# The max skew and max net delay are set for maximum of 125 MHz for user clock domain
+# Transfer to user clock must be adjusted to smaller values if the user clock is running at clock faster than 125 MHz
+
+# From MAC TX Clock to TX User Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD  g_out  altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+# From TX User Clock to MAC TX Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT  g_out  altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+
+# From RX User Clock to MAC RX Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD  g_out  altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+# From MAC RX Clock to RX User Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT  g_out  altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+
+# From TX User Clock to MAC TX Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT  g_out  altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+
+# From MAC RX Clock to RX User Clock
+altera_eth_tse_constraint_ptr  altera_tse_a_fifo_34:RX_STATUS  wr_g_ptr_reg altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+
+# GMII loopback
+if {[expr ($ENABLE_GMII_LOOPBACK == 1)]} {
+   altera_eth_tse_constraint_ptr  altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD  g_out  altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+   altera_eth_tse_constraint_ptr  altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT  g_out  altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*  din_s1  7.5ns  6ns
+}
+
+# Half duplex logic
+if {[expr ($ENABLE_HD_LOGIC == 1)]} {
+   if {[expr ($ENABLE_ENA == 8)]} {
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|eop[1]]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|sop[1]]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers  *|altera_tse_mac_tx:U_TX|rd_1[*]]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+   } else {
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+   }
+}
+
+#**************************************************************
+# Set False Path for altera_tse_reset_synchronizer
+#**************************************************************
+set tse_aclr_counter 0
+set tse_clrn_counter 0
+set tse_aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+set tse_clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+foreach_in_collection tse_aclr_pin $tse_aclr_collection {
+    set tse_aclr_counter [expr $tse_aclr_counter + 1]
+}
+foreach_in_collection tse_clrn_pin $tse_clrn_collection {
+    set tse_clrn_counter [expr $tse_clrn_counter + 1]
+}
+if {$tse_aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+}
+
+if {$tse_clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+}
+
+set_project_mode -always_show_entity_name $old_mode
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_mac.v
new file mode 100644
index 0000000000000000000000000000000000000000..8044f2b865cd4fcdedf8a0dbbac70693ab939e0b
GIT binary patch
literal 76504
zcmV(lK=i+h6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT;?lv8~_
z%IE3uh$i}ns5PwyN*Fpy?%dApbwDXhCqJEU>jFBnpknT8*cpheUBU#TD!1HI;ay6k
z0FWr|)b7ayKH-}cKve+?ENnth&TJpEb;4d*ur@be=?;ETo6$qBP^xyq_WEFmA*d;+
zz?6G_S7zzc7giKtl+kV+E5cF3R#UnurktP`77bFq4R9#FcXFBmeIi7>&OW{uPv+Qn
zHEHXe-Zmp>d5G*Oxnq6VwI!PRN`K08n+F#^T<Izb2pkM?hOqV=s{*Q;^+aMXN;j|s
z1KyAH`7@Pb8Hzh?kN_0@yDQ#6De$hM%o72EW+sS`-uIc8x~oeF>b7>@6RqSF!6+<3
zKgxH;KoII^-*YC>PReRsPmF*4VZNZeV)MTmTnUeG_wm)ZmH)Ea2Dm{<EnH%rT<Iop
zG*LVlhW@+_`h66@;{4Ec!pR#*(pXV0enEA>T`+)5M%rYoW;{?FfWQH0#JrQ-ejsby
zX~oxQORVl|cyi)u7+%3tZw3U7@qcImUTp=d&}INpRP`12x%dBH_KRCvtyx4H7|<xF
z)V#5^JpT`jr<J5&G4HV*$QpzrSw}(d$r{NgvU=RTYG~T;zy|3ZfrLHsMBWkGn$hM@
z&JM<sP!op#U@e*Q*NHj7#PyPvMflpLZbE2KwF)D$$hV$MkgZKc0^yi;EpzTT=uz&x
zex%gH4ux%-jgGpG`owGZ7WSOrDpe2%sGMU7d{?ZOSBr_TDwAEjG9DN34;u~Z`7xS&
z2f!i@hsrEMzbY?mjnIKBe)~D?CfjtXfCD4UT@4QQNSDhZeN(upMm+#Tarl+sAbDRa
zKLmfs?M_?2f9(mEv<KlM1s5!z<}B2N6-s*oph`cwTgN+ZS(iY!TBKwsi>>BU%Q{Jm
z$Da0a)>R+an`^a+GqizymrgJ8o!)pfR+0;Du5XTlnS}pg>A)=IB%nn*Pk-N2?of?7
zH3ROrC))$>r<H|G44({QgrRxX{R$aQvA-D$uR{O<;G&89B5Dg*LMH?e3DSL<d*yGm
z(6IirI{eypMB$55uPQA_KTK|K;Db^iGV|=fA4JA5;r5;^#zogiNOcB_`3_Zb(!A<9
z787l&H_Zh`FxH|u?Dv=bVBv2dOBmQhx~z1Qy#!X}1bSJ65P#mz)Tis_Oxx)_sP@z3
zf@oi(gXJJ5_<)P|696bUTuB`v_q_wI&N#o8#fct6Ne>_44GuGt-`U|i_?N&InE&4T
zCQs2jiJKlmAVh+DK*NB+$)~wRGpK0}ZSzqxGJ9TRGv75$i}Z&9NehY{h)h2-A1mCG
zE|YkK`}OPegS8duN{^6PMnZZIzyIIcf2CmK`1eA;l=-b*7d+{AIcb`O#VUC7UWaDv
zNO$-f7ao->Tk`bAdHF$uX)MQvnxn@Bw#ZSOBaX}<3xlQ%9U_vJ9*;#nd%WHbS~vdr
zy#gg3Gg$QoPa-000{U7hKmx9I9W29ZVomWJZi#=tKMl)xhIFegKq?y<R?^lvX+C67
zHx8Umu;+()R(8+Gs)I+A8LW!kC>V>lR;_>hIHWU_-D~ziF9?@C*>ht>7s;kGJ*^`y
z>OjX3Dbs#$|A|^d#O?p2I1xTwce0{7@k(4I>ARhFUgKGXde(CpC`0x+<P3g#&?v7G
zB=srJ-iB{dI)i@;_13pY-c?GpB7q9j!l1qGV_(Infj;5np0bk=W8ohI>}@#|)3d3F
z+Hw#A+dQ-UL~AGZ+OqiJ3WC*)6dK=IWOQ+J23ai$Hgaofk3`yNn#jxX!{mumZ!tn`
zu%)`W?UvO2d-AQ@k)pALI;u4NGM=go|0?x)0Qzd)SX=X!h!cTkdxV2v2I12ZYl=gf
z)acF9r_eG46TP+8_=w?$v!lxad3eas^hk3JAvE#o$LZkF#AA_^RJQy7J2k;YFs#e>
zQ4VV#bQUcV%Ex7JklO0{rL$Gmh(kZJHaYIr`lV(qaMmay;7p`YkmI*jw)-$wrF4?q
z(^%vy!r9L%qW#CTerc%cAS62yD#V%J$N0<IvMa=u?dxvLFinK!F$Li!dh%MR9|<g+
zNv2m@{Slu7<G;$DJ>zchAF#C?x;~*2i-<li{1ry3__tm&<p*crZoLseO5fy5!$hi*
z6)d9p!|R{A059dJmgdTX!wPCj?m&MzSLy1Hbp}Li-|#ZPqZVFU(1~2`ZJGhVL~@37
zxHZT|k~=N%4>bBDQH8)k<Phm-4&+qn9M7ak)ISJwaN~(vWLhb*O9l{xe5^JdyqUa)
ziYGiNZ8OELT6SEdt_<Us-GS<J4@j09yoQxd@9rx=0aJIbJ1UnRxNGu24$mmascnZ#
zFoi9)`wg3iZqJ3ZnW?br0a`@KZyPZj-hyEedF-xs!S1vn$kox!b{6IlW8ROEQX%EI
z12YC&nKu4yUm~=%-<&C3u~m;+Nxn2f;5(;@Z17(~*U+|}2=T!ghAL!8r?kdaDNrYJ
z^6uzK&bWMIYxv~U@nT9o;@qk7`EtM9h=NM>{kX3qTA`CxAp$;QqEYB)gBd0V$3?GK
z>H`Is=RArVgK(VS8w#JUkm5Q++XY>fg+d_;7qycWrkbD%4#QPxWy+q4a2Cv7=hG4Q
zj2w5b<QQnMZoR(mht}x0CECesL_VaPf488>+}`XlY#%Cns0@Qm=*&4c#L;;DlAdGw
zBoU09ydkE}eVOpjnq-sl%EL*3nWWjj4oSDlW2USn%<-wT#&ZB5n=<m`w;u)%9UTQ=
z9DkfbfY3<2LuuD&sU_7aaIBO?ecBAN5u7=Tu@+a%S6E-v&>#lzGR9AIqm5bhQU+Wv
zhUz;yXc}=yQ&jiGf`3AdBOq8J(CBn%Wwsp(gdu}9+?mF^Jy#M#%`EV1!jaR{(1h;t
zB(R2XPZ!P1fo*8DFC}lHFUqF4$Cw4Nue-l$#etl~2x9uVXc<C0M8=Nozph8w>bE>S
z9$BmfY|AR^_s^g^?V+l3HmGNB2!ou>)q~0cT!4~?5k%eO1Fk!@g)q5#BprYV=u6=Q
z;z*ai0lT~C_GQg9WRuSG#mS)Y=NMTwbDNNMJCBR9pbT`54k%`t@#`hD9gF~C7(;vh
zR1nl;MzRCwP5_52*TxpC5r#)Hlf0gK&uoXHnVePdd~JX`&f@x<b^(GHE}75>2i&Qt
z9tcc?W4chn2QBzlczUmAznLnNC#zJibK}8%d-}6lyzMv~oegJQyH(q~uhra$hUJB9
zkJaE-V|?qxFi)~@+&x&DKXFu;0%@*JNH^w+sheg4Q5TUWvN$q;@lRF(DYQGmYHXv$
zgWJfB>XTwD-&}%KiU)IDTkARO-#5I`VmleSB~HCb+<#m&C*?p7TzQ1{EzrtPaUaw?
z3P{%Qy-EK@00q4eAC4V4j5Mo!FhAQ7qxm^dJu2KLC@c8KX?Un9eJ>e=SUbUq=1)~q
zUhJ6BcQ0*$&WH)CN0ItKxy#m=NkPAfzCmvR^uUi>EsXS5RWoPtLxA<|WMQg*;y_0#
z8244Bj_H5CxqORtQy?#!5r(^7U_oAlrvVRL6>HnnxJAL;z7PR|0~}a(p@P=nbiTtq
z+$_j6<8!;O3fJ!InqVW*EgmHx@en*K`tF?|RD}N(Pw#IA{b!CLrsX^5$BxUVW6u*L
zWRh@y{;tlG+WWj7RcFeNqi)Nsou0}yL!cVVMQzhES&R{2-4B&+k$&*RD`eRZqV_xT
zY&3mXhPRx-em!un6V-C<z7(uP<^`EA49Wt5f`|IGOr7>@{lr@-rEZOhyL-jUpMF~-
z0Zn+8GZX~Q6e|x#L6FJDCHLE;CwU6$VKWfAiv`!2+vibRk#LPZaboas`ABctHGJ1<
z79m^E&0B~HX2bqJ*sA)^$+^#Emq`4~O>vaqi*F9`sGNKwqjZgz)gq({9rGDKa4$`w
zvr%@z9qAolRJcQcnHzA%BqaM4$a5M%bsaD*_!VwBl9}v2PHjXP?yn;<W31YrapdmE
zvpMzxyw>DaXjcGZgIE{(Dy?&RHu2{!KZk_4oP+g_+#LoI<@nY=Mr#$Z^XH3{BKj!M
z6)QV{TwrE0vacC~MnlTdarF(-WDZoRVo2BOJPprJ;vyYeR_I44f|Elg3S%!=7BozV
zUV)H1CWu>W^Hst9sVCi($~NhG>z>U>;JRQlHSmc-bIw%Rq9<!0EO+(v3%=+SWBiD9
zP}F?c9+Uod|Ne;(9pYR@Vy-CRKBJQm?{b9YA>|NH>oRwwJFXt44Y*3s)H$4%D<#aX
z*12l<o;#fbt{rRgd7S29UOQq*tRxS07o^1tdHzU1kkU7wPotRHJiC@W@f>tI*+^(@
zQPy&XtJ?$Nc32LNe79)JI6e#HYxyE8>bIXj6U1+bg(=*Ue+Z72%-LL~RZMzvP)`Dk
z5zRD?5L^Z7fcP<ic?0popCWHpGi;*5@706&q7$vNpKU~2ILh1|^GCK~3+Z5XH3P?d
z;{ID3$^H|Si<G7P*i524ZcJQ~=EVQra+5p@n0?hz+)WX!m(CT8n>MTJIE}_XV;tA!
z2NbF%lYB$5-3kVBz5eVnzmDXT7o~02^Nv4QxPvy&IzCPok;e?~YldGH+xjw`13HUp
zNE*JSrqMTp0YrbClO(bN_{%)jpt4CBDOZj|Hcy`SsYuhJkpVAK<W+&`GEYgI(ERlq
z15ryMuw0aOy&?J%+$FiDJQPuXWx0S`b#D%WL&hmdJ96wPdobN3cmx%JHma`?%XNT$
zC?Y81I9d9B(GVwB_tk`7Af>H9s4{*byDA1{$C$$vEw(G(*4b-A(q8E5fUSvp6qj&c
zR#po5d6j~P^aDQ_!w@f|_3MHbqASo}eBrm%1I>S2dr@FBo^Eo{H2xy%fkyZY*#||c
z`66NR7fL6tZi_T?M(q!E6-Ykg==VDTdq981fWDogj~rT?Kq2bi(}OAJ>BB8g*kjYy
z%n@K=rB;%4*R5&(zB;&pWaEcTZiFy}t)tL-{=~_nD~;Ivef8#U@w;SQ*iQJ=TJ?Xn
zx@~**s=pIv3!^sJ_#UE2auoa7oB0zs(j{$4S{la7A9uIx6BBU;04veSgdfc#lyUTM
z@<jUt0Go7r+}{Ey;;x<3PtSuuk{<f~OefFRBM>8u1nXlzQ_CqeQh<5Cj@Y7lW!P?K
z!lSmBN>^H;P(XsF(XIX+nUF`XH-;wdf#cBjBTxRtwG(QkY^fBP<e|bHt~z#GD2sll
z$!gppt%*O;rB+fgs6lL0^AL6=;4OqG#-3#-UE<g`+&-qJ_9ZNqp`HI-iA6SdZa}mj
z%L&N%;|msFzne#}0)^0o18Aeo{`Mj68j>T*T?wDF342ypC)sbgx)O>av`{vK;&GsS
zeQzGa`VWfwAK}B}0uUl9>B`wTjPf3=#y~4O(M))DiRQ~bi|hmaW|ixEyzKpqEl^$x
z0Ncd(;G&>1Q72I#J%4Qe=Z4ga9ZAjN^*DW4z_kB6*_mTUs56{hGJg8Y*f~X#+3(^4
z`PtfBnLhtDM{f$+y0dqrR_@tY@||wk_vu%yU=kB3C+S-s&Tv1yW6tRANizi|V*4vV
zqo;~?Sndg_<!jL)g;=#=mToH+v=$q18m)F|gDX<c&mO<x_~XAkq7Uiz7wylLtV@Mq
z)MG%e6L$iZ!ijWdJqQcEkXem|A}MYK+>IlqjjP>z5>DOn36la-{&sM#2vmZ%uv>*H
z-VCjDe@FutI|~Md@o(Uao6q#AQwgWgduZKHqhDTlb8xKOLiGuzlbwgY7VP+%+zi8c
zscW=IqHv-(tPyO3Nh*x`2Iv4{!9Aka(J*d)bd4H>u3ino<dE4`D(eA@tD;TU_d872
z6Z~I$H6xSL9!xPut$qv#osE4c0K0jal&ZSAx7x(<ta^$qKiyk@1)g&`7`Ga2rLEQP
z6x+>F%I6Nb>8subb5<#vn>f-1)P8s4<>YMxo|<NlJPJbAANV$)*rvSk4kl8d6<I5B
zxADqk`^$8C6E2L5nYx5Tn+-C+UaBhFD`B6AS>6$<TI0%m(ZpDrF(|cKIf;yX+?eF!
zz%x)292^chdlfp}@{_<XnV_q<T3P%6)a44Rko9y!w^+RWY1S{SD)eJ|swu-#CPm|G
z2#{_N9LasT+1#=Tq`>RXUo=&>##`gtD06Tpb1R3RsZ8|fwE)g5K(*QeJ-q);6N8<Y
zN(FQ$&Y{hc+A3xX@+c4|`@@5k0VjT#=zE)K@q^8&gb=R1ZalYJ1d5dB3y}nop#m}#
zPO@Ps%}KrEG-`Qv9p#Uia-Ox&w0FYpfBFwmg%fa|pBlG-nxvKJl|y%QV^NFmmArl%
zKF2+9e<vSr(H3cy3r9lBE_l%=FKL;$O+CUWKVU1g*Xpl<G)Fn7cmv$gA}F8|<iUYs
zE+ED?gW}h5LNlmb5`ze+&vrtX-HsTyH=LH5L;jf~o1d0kPL7a3tI+P@VC5j49SUem
z>&MU?A6ZNG=~AA+Ni80}>sUS;K>Qz$gx`}RzBG{7*@nTdyV7U&%Kl+R4ByI{7+F~d
zkP&+f3x}gF|LjQNBl=il_68(4_c;HXx*k$a4hGXncQ41m5^X*l-x|Om0*n=cVc_~D
zbJ#0_x2Pp$#c1WH*aY2bAVJ+heitayV`u^+g&bt`Goklmkld^XI4wbkH&(It4c84x
z-X=FS6Uu`w&hJ@gbyA$4S``P^&Sq%6$vrPhLQ2>4!6EUClD7LY$@lh}=2ri_6T@4%
z$T2avV~Spfb~3VnCtF2}*stRf<bd}jIiN%N(s^h~u+}IPzxIi?vyA#WBWTq~gMH9M
z(HI+aF=(vL3UK(>?=fm9v>n%@_F~$ouc;BLXbxGEF>-#KP4KWjB*+H*u41yY$2)?v
z_^nAhoY{N8W1xNV^qH*Ms|L|wdr-r%r#cU3=|9PcBikRbmrkXkQ_*MUQT|&<oKed>
zAuIQXg7UGHd_>bY+?ok^X+i$Q*>on)lJ^02wd)~BITcN40i+nKu<F?R-oJEVhwp5U
zVH-&SSDd~wd@nEwh6}U6QhoGT(g{ATMJL4mc?>aOl_9(VzD*d6)LP?ljY{3uo4{Rv
zxx)Vy>}j%8odiXwHfxkL&_LWP^?lJ(I|n{mM`tz9TS=UBh)r7XRkR-%uI*J|I{Tx~
zAf^JqGLSP2*Ddm^WDb^8;}J|*{3Q<p&I;t7`mUo%pQ-JHjgw_?zPumo^V3+|etz>j
z1S-@1xs~j~snhwAg8E}sDH1fgE|iVD2Dvg648@Y^)u%NW6AYn~X!Sg^gnAbZhSs@^
z-2j-NL7K($HGriDy`j>I$H)ma=Zv1b<lqu6#$bcM`g^$F3FU7X=h#M?V=DDALs7on
zXpMg@oq_dtQud_gztP(US@i_{xvBB@+$$6m;TW4mS`I|IE^IR5zuej=`u@xU;i0eD
zTSp|ui|0RKw7{0+CV0~odW-C@ePascMqzHHq3pC!Y<i;DRNJK^K<xD^jLY(V8u1Oj
zr~HiR9^H6n_iOwN9guT<ynG=IGe69qse>b;wm0qZ5)#w)$69w$VqOH^1@-MLSqHM`
zFc`bg{#rzY^CASgwcDRXO)aWS57vz_EC~(l^0sGYTA&66da$}j+tT;vh*M#c&@Z&S
zwp4_w_LW*IM+3Q6h*+Ah!O*v11F?1F7>JG|)1mi+oNJzl`y${bqE9Bs<z9DC-*`d>
zyzr-N2zERNs+6%K!JgR{f2n+5UsDU{**pa;f7Q>b`fzwvEdkNd;IAF~q#nVeBhV<W
zmbs0BPg5Zr%&lXyM^G@V{ut&dn+!RlqY>ml4=0lw<qw3S79#z)USkIaZWhfyyw!rr
zLli628WrIWtH<^zZLc%`_FLkozd~@Any^BUfJ03oKx?X|6`aDoAHtvokn`)gE|HgN
z3W=QZNu<AH!pl$J>(Kx?7<Q9as>jzyb*?NLgw7%j=ovPzL{Go;wzTe=^jsoM|2o1Q
z$Kb~tST&hMXU1hk1b(=Mw@&$9+9v{_inpu{riVt4?ldkaGr~nE%Z*=jJ6~{TUsD%r
zeQkULNjbF9K0hBcmFoBX{3=k&3whvTr_N*11`irRfDYpfr^qECyi(8Xe%-2rM@GzI
zwud^~TN@Lf20S4D<a}D8G&-#~^^3lOw-M^)EN&3Nj7kqK?1Z@7z4`!NxZ}k4&@HN=
zn8o28QPR4Vz$!C`Nv5#4+@i_XIrDZ*Z0U>DFRXdHpG^3&sdZtIXCn~^p_PdsSP20b
z&<Fry5Z2+y-sgYziONb&Wi%v!FMM|#%G)7vxpAXEo2Yx6@6I<nP(w_;0&;L2d{m0^
zc*QlJR~A&IYg2g`zT}v-V#9o!NxOe3lo~-!74519;ETVbh2-l^N$Nt%(SZ8~4D(;!
z4hOfB>JSSkQ>eYse>BJ@N2Cz68T$H7&_j?3S9xd8Qr$ZOgPP-s+f;27ENw0~9#BHU
z0iBNhsej!`<GEX{C)NU>x52#LdMDV$)N)0q3hR3*Za`rTAl}?cwy>xZA8&ePvr=Z*
z4E;ly(==B+A>edeKv+sNsp}?j4%1?X7VUuYZ5J>)Ng_!388-i}R$c|9otibfTim`e
zC^fgcK{SnAliZN*=isP5<~vL4GGAvP?_dUqgT!LCVRYf{OX2SMC&Q+>%LCv;lF(oI
zKLiQsoLM>QdJ-?5c;p=`EK#ykLQ@RTuxNZ-F;>y$qoMRuB?OL#&{!P8-iOn@=ac&e
zCtph|#GA`}6}|Ve=^aGP3-h}c0O3RY%Y;FE;kz9%_6Hj(!u*B!syx>$5i#=&UL+Lx
z$i&H)8*TT!SD<IZ6HJz@Vr_M@l>$&+&z^}cfQnJiH1t4}Lk6YA`EDQf0jCkTbPExN
z?iOL-EA>zx+X{{ppIq>x8O=g%6-C?7hIg&2gvV><bl%FBrebb9K(B|Kqj$`<<1dCi
z4I#u0q|oMpZD0DK4G<>fh7xu_tiSK$jS`>S?9jU~yyEN&Jb*-6XCAMy?tVfwupIK*
zjWfcq8va|bS62MMMR`evpP1BkL8Lcypr#4x=XXek6)F10Q28(h#B)n$zlJ6A<ScH}
zlaGA*7(jPpQ9&ivi;Wt5#vH|tHv_y{8hERcG3ix$eKN=ojs_bCIONk6%pIZ!f*CYC
z)OaxG(ZHa~wceV2`!IH`;RV^v`91WgDDeDP%$cSE$Px=K_I#D(TXf`d>+`+NO_Ps4
zHQgrgClJ_zqzu?x4Y5k)O;Ite`aA!8$cLqGeBa8mB_hGlu8Aq`dVJ<vBc=3>NW~P<
z969Fkw6BlVq34qN^<E$(q0Dm*G3;!e13@Iq`w8bF{hV@@yPT@LML#DgoAdp;ECpjk
zp4dXmR;u8X)LxSf#|>P!I>6%OJLIFfk%!10Yf}H7OMjfk8CW>z%uJF$l6K=JhD}KG
z!PgI{3b@YC@3TbwPmt&zuh7;}Qf)0;rJS_PJOkYK)n^H&7Gx5PM9*#7Dhbn$b?JjG
zJ?Sx<ESk*|^H{mSXSMFFxNQ*^XUtGlt!(HzZ+*=Tv+ZU~TQ1Jc0xKHwoq5{~{d<$^
zhQB43*KhM}?qPQschy=X|Dgw-G&{Md$rr{f6WcJ#l74R76(XqjdM%eOxeZK2hhQ(u
z5)pAGvS*vp!E&95e+-roT1Iq4m(lA&d3iZ|`Dn64VZS0v^x9!Z80d+mMVf{|!Vp$q
zqNR%YU*Y|$W@A40{%i}V49pNi$n{K=>19bLfg9<3X@%u+K<bT|Ct=i8-Nmwhbhmrc
z(C;r_%e(j;eD}^Mu1V-)excoDND<22;zyC{iMY+`!+1PXzcomJO;vl*K%9W6*|^R$
zR)agsLsr@U;>^UF8bQ9V`2Vx$;nycEl~y@Q?8voZ^sT(696}6PPZJiga-98#Cfs?`
zoVQ*W=ZsvEcP<O3hLK-=HfcVHIl>EoX4{=^;OjXCi$pfW%G?>GOE(u8PRE1@uct<)
zzo4YkgEs`M{<tj{<ssUNAdWpi<%&g0^?4yYc%_(~L(Sv+BdoZ&CF&h}m4ZGvb+{nQ
zEZ|`Oq+5R!`1R`{sm46OyKIHS_EJwYdG7BmjP@(}^PTa;nNRx<EbHtG>&O*(-WTdE
z4pwwU^zV$L?BBzWnSOO*YC}mEne;Za7lw~=Hig+E!TM107F|P2H3#!<bTnX_s{^6m
zySPF5@`}_rX(}0E6<LbWuA*Uxs@>RMG&m*g6sr{IsYwr61ssp{B`F_OHTA3OULet0
z|GY0X5Oq~s;?UnofBXF!Ta0*GuM)XCr)l^?k9R(2;fe=?L4I%`Wwow406l0WEs-@D
zc+oj@>|Tx`#8JKwv3oxo_Hd{GWn#nWbvVti5tN}OypOcbwi15b9Fo?jq3x93FiO(7
z(0{pSYpbl&Ct6CVmPR$8EBQ$ni1o>`h_vk=xu7WCi}JAUfNKZINSpa-fP4uz<&FGP
zo24-agzgk{LD{iD-ft38o(5%f&7}Zm&E<t4P1;*Czn`Jwuv=DP8>v9RsctDGTkHAk
zF`X3Wxn2=rj%1~43TR2F1c@?RFlVeTWzvlbLu8)d)4<o9@6FX`GuC(OvG*_`8vJDG
zHzvGoEBee5BIGU&<ovW&BRQGQ@4$>JsY6v_Ep0doX_1l`vd=P0cLjekxYg8)`#e|M
zumS7Sm)STCp`lmOWy(WE(dAQL4Ed96mBDqpl$2_RK^%y@b>5&$WQ$eP4_<6&S7zRc
zST|I;`gG?VtqB4VPH9^>5@~;aqLgSOwOLl*GA8!Kcc*<I+^r)G7;5*t664gajj`9{
z5o_SH$}zjOelZ24C(ob7&i9vnyW0dwAVAnA?Ej7eJBV%>RJ}yXcwzs1Pr{zd#^f4%
z0SLA%-FSn2-}L+I%$IttDu(|AQ;vCP+=AVdJM(eBsJHYN3##Y3y)|Pk!%HxhWQ>im
zM9spVL$Ufgod<3bTdt77$=SHztzxQoY7IjeD!5SqFL&CNFC|h%x`Q@a{QCy4(V?Oc
zB(mb6wjK0$U`5V17!X3`F0e1)6hqTQm=OQBPBW17qTYWXjpB^u2lW~xRHXIChL$8u
zeKa%a+}!suA!R>UG@m=)sX`}&|BA6&)EQAK^sb3>PgI(#FKW00+!St6NX*oi&*&+F
z#p<lHo4adPuMOuElG`O+#f$1{7ljCsCRZMLh9C~YIp<Iho^pqa#DD9sG7>V2945N2
zW_>U1yRge~zbse@Q$QN-)yZbNdp}M>xdvdfJC*aLO+ZY?0229O%tx#fp9Kf}$QB4{
zl8_%4JIB-jHLynU1x?A7bb`Ts-PmLH;=}mhdiLL^q~-3%h)+#;UnkPXHe5PL8WR{@
zKA{{z$A<<ukZHFhRw^Mmqs9f`YoZj)VN&*~Z|I#B^-1(ok6IBcc@+e%^jfeqBt2~p
zCW>PXU%dXYyfSk&0#x4w-S;hfn)~If47LCAZF+Bg%_^fxYg&C|)_xtKv_H%h*#(T;
z4-%DRT)4hvD<#>BtgcDFh!6KyhU__seU<_S!rjuXBDoax*#vr1&4lS)bVoDsNGJy{
zavULMBG~6tIMsIL%T?|6ZGFIFe<<m!96He{bzoJg^?V30FyVOON$zh9U}6VmeHNxm
zB#@*A=Rvs$N`N)D-{x#wP9bbX5`_{Uf5QrA<CSP-kC`-oH~yXU){81RPRQLG^Z=}2
zXQ<~pmJuRB1Uqo{RhgQ@s#DF?9FMXkMX*0ELBm650XR~@z1hyxJQ|KC<xz-S02pC<
z@;oOrt1%n3f;jzA)iuvau>xxpehZAjhh*Pm%hhzM&zlK=n&xdoMLi3<A)dytEV-5@
zdCP_X)2V48N>DEBw|P`c6*s09z_)*fUbCTcP)hs47FoD|lsCqcG}2%y<*0@H$8)M*
zwq(|Mn5UzeGTL6b(MfPJ{zDZ`{33MGWKG{}uF5{rF_0a89+K&nIOaa87qh(~La!cd
zc^YYlVRz@eN+zv=9uqkRm*y{K<%9|9CT9<HwY}%`bWWrZ@qk~zY**u0nhVTT)<!RW
z)(@$n8?Sq46^!)Tb)_t2b{xvo!(-i&!(O53{~MjAxy5u1zPZy*S%Ag!x62YZY+(OJ
ziNJqbBDsO0QTqy<^VYi&50X`4`XFDav6&gunXttHJUIX3FPk#{xBWSt_|Rv_w4CEQ
zU`U=Efu}x~E+}@2#4|Ymr|A9Vd~MqaxSuXA9#tfb^FjVsi=#1tJcI<$>ZA2>smJRm
z^;}~3QnQGK0eLQlQWnv%-ak3T6Wvil3=qko93QpJ_zikAgV+|H0NkTdF?1W#hpSvZ
zSSqo92+Sq7)d-;IJXIyx`i3ngvKH1+{AKFBgfRjSWelz{sO{vqbXW$^V&{1IHoq}n
zKtJ|M<%0#P7{+$Y3nitnbunjluHN86egOl_+}v#G(bMCbRI-@n=0bhwm9;5MObd&R
z;O?EPV&&ENFPtALQxwfU6L~CtUpy26CDTKz{&p8aH37CO5tXZcSrb6TPKz1h*;Svk
znJl@o2Yigog$8XWUY&gG{9^|lFXerIMQ)lnFX!LqNoFQ3C-G&EO82o=fK;^~QpT|a
zC&8ax3)4zl_?4N{#?0+qx{RhkME($Wv&gx#9Yu5Lw&^@t8H-q@baePXJ9XNzDL)@f
zztv51-cnGHij6kp1nhz~$Q+DVCY9I_s3LkKE_+H=*^bIAh`^qn3ei~Y7=Jesi}{T~
z+!%?OXzfJn%W%A#XG=%uIMD+(hub_almnO;UQj=)JQV-JJH6=Qe$m#x@LK<m(b9=U
z^iMTK*IPTC%LXbvkc1*EtB+!L6abJ>Me@Q<g-`OHe6lD?=9sc+hjT)uO}N>FNS*um
z(Q)6u2<10PWFPoek7gx`f0^px|ENg-dEe9aihJB0*#u857n5jdUn-k%S`-+U&xLXj
znJO(;sg=rVc2vR&G5N*0am+nFVp5VF83jF6cPBmkjeDgFF@kssX&tvu<(ayF>&L9`
zdRp=7;fgBswrTJPEUGK3(_vKabU4xB>*2`&g(PuZ&x^vIU6)ms@v%SAsF*?pR*^`5
z>>vd-wi0LEC7u4Z4j8bf`e2Z3*m%}!Q$L40gana<INV<;4)!s;-I_~$o9cz1fmn}j
z9wxW{#j}c)jVOA>vD^H!thIbLS?=r+9avZfin+kA%d4r?r4lRnIryj<hD7<}>R(0I
zrSj8*w+*&Uc(6Twmi@L{h>I9cDT{}W`2)(bZ;&RsN>1ir9yn@|S6hF%kZx$JOv@wB
z>H62E{8}#m<1O>--LxgN;6alo*q^UwLAQgt4s}B1C3ZrxO$WB_ln~AMhlfHiei`|3
zs5G(l+w?x4_Q6!lQgsKtDdS;8eGDwA_fPHrdFWV=(j0Y3h9?mqRL6xvLh|~xIs?gW
zdLMUs&+x4&@+)sr1}0GWe5C0?Hrj}|Nto=WHunV=im;m@%xH|$@y7Oq7Tw(nzFcx?
zBc=#Id*k#QcE-n#T0d{E|0ywS=_<^hf#N7$36?gq*sf$<GdJWm(-7XANY~|r0Vy~O
zSk&0Fid(SuGtDY0a|1%d?22)^J8_|v%r4Gz{5z<zKY^3s7b4Q;@{?c+rIF#;%#zJ5
zc?NA{u6bAhRXr`Vv9LtWYGbAb*N5@xk<aR)h?g*TuRcLx5_mdNJxhC^Yb!QalnY$#
ztugCcZY)6Bfoe#Vv7b~iw7wvTgWhuqkw@;J%4J-B!|t@Tadc!k0wO@>qgkUf=<N1b
zvBw~olVjj{;9i;N543UlsZwO%XVtwt<u@_X6`Ug7J9^lsA4xvhr7)V5MS}cscYtvg
z4T5e07$UEt{UBJROSBaN?7BXz65HDk7D5*6l1R|DsPqlXqq$R2`H}T>?;Q2lnW5>+
zL}s<EGMMmg0{&6+4GbbhZb^3SHcMErw%Y2cnVUWDw6Uc%6B}2J<-@fy2PEpzU3kNM
z>?GRs=Pj%`wqh=;`r(M0t=ctNv8cbx&Kt=d86>=#x^(H(2{1@0PE%KU2TThACWeOv
zdRh|E-;9ABSQ<k*xt~`Wugh$&`pO$n(ssFQ<d@o32y~?S+sR4lUA0w5(Wfdt#(`=^
zlK2uv7nE^R8w0%iP|5qLrWh5#>Ew)LCviV|<-}AJJ6IKHJyE%@D;coY@<9+id$1=R
za~Fhr{9v;#zte5?Mzyw`Vn1jB%kfotV*iBV1{eXR6W%qvfnk3XAMf#=-ep8o*f3dg
zYrb_4{7=q7n4HnP18HRz(-o{ahRR$(1HpD@rr@!v+&6uabpq!6VO9pnNOJF7$oG$p
zD}r-h%db>zh&`ao5F$N*F*ZbdH>Sm%xQc$8m3ni<WGgSltz>D&wg(-iQ$SSGH$Gd8
znDIR5qvt5LK5wa$zK`d$A?3!*Ukspp3qEnO>zoytc|#*a%YLlhuJSZRG1|>eyc^GJ
z1O&J#PaT4CIAT{ame3Ej@LAu=DNj&|Mo$;ZeSy<r1p)=%B`~Y4EDG0zS)5$FY31<h
z3+_|Bg`xxQw~vih7aC}oX{1nb1-UrlTMO(W#}d8-cxZKC$wY;=sPm?7-kbxigN{?P
zWXQf9x6){7yorA*V)P_mXCHy;(!zoko}{>T<)}@?bSK0IrN-Fc)A??@4vdK$aU|o;
zt<F&n94wrwi?YzGv$4?$L0{Jxcrn=&5E1DNJYVtp;ZXTZQc$P>`e>PpN6;QEg3GHg
z%6b9pf0s_B-dvQ}V#Vm!!B@!W#aGMl*NdvdBZnP+@xsaV?*$8by}wL56y6S#teA*@
zc%XX777Fox2QGlv-lM}*XWQ1yEd4<15!S^pWPQ1i5Sb9D7k>4{xW*c2D)*c`EguvH
zMKAx*xJ{ui&f5QrxR{-d?d}bT)~o7=t4gx@*;{+0szlr1o}ECl4JFqI1I{=Cg}5*w
zSij94MT!fCR&AyC?+Iz{UVjlRR0D(~@m={gJLuG48)jKTgzV3jffk%U{$tB-d=xdj
zi2<y=$Z#(^n$_e1;RE@=M_V07Oz4-nTz$dx^l$pK{h*JiOR=|a`r!mY1?WmXem8@f
zscT4I_JNbM`di1RL|kplN0wt&ITY!*JHl2rx@j?|o=aadrFMGIVD3uK>DUoF%KqV-
zA>fz1S-nfZD#>bFt=TmjrHGg`qhAT_gX<jzjIb|aI>`&I+*n0_t)KIuYwbREGE!M~
zzye}Ip0vAPU`GnNoCn_{53D%XKBPmGqvr*v@onAJqtbsGZJZNz&gy;UEvo7`PFdij
zD<fBuhJL`UX|J})R))$x{E^NxbHxO8!@_2a;iT|f4spO&dz=%I;6Y|mK`<2Sj(F-Z
zK79NnBdsyM{5|g*S^+T`RC}*jwz4XrIUP*gCLui2#Yca{2_Y7A`P3^SzdG`MPUBsa
z+HfPtPYcMQb7ob}u&tOOr`=dolmizjP|g<UQ9*#c7L@>dg`0W~x^EwPhzLcK!rBol
z+(y`e#ozoO(BUR4t8wNP9e4bk(z3_{VSEi`;p!ExXXZ)+>KVt33&xSXQ}z*7ta5Zc
zJFyZq9LM89kE(6f2R<vSEXPI259x-mw=zndPhDX(MLKomzC;ZLBuzIlzEfic)7?J@
zo`Y1H$+KnDL`dY-_g3Da7D>~}IZ2IsOc+Jm;!dy}66oa^vg<OwiWczOs|RhA%~Vge
zPmh}q-J;4!NuKH~TdB^6njWr2noy+ZXVflws;+TAIO~(<k2m0e-}l=mS_}qkjja}p
zDU*`;67$Hb^oW8syoksSvlkeDhK?WpZdi#S(B!td=uSu}a>f~xC16okbr0TzQ57I^
z<P_zPnz&4Yb-(BY4Dz(Fo2EY5)JWT`SL-|3&P3@5pZSw7nxQu2fP~TLDpq5;^~qOk
z25T~xG?vj1n@O!{#tP512aG09OiMNGMaE9}4{s5a_2t^1Qr9AAJ`55)Io8p`zaeT~
zmkYpsX$0xkqnOar2<sDjgXiq{v8}0Uokn1pPgOQsE+Be}Sy-jS1f^hx+NcoYqcWX`
zYftAMj{XLi8awqB1c<Lt!Ot-5q=emHo2%I^7M9gZ@nlgAVOv-Z;|cZGoe5P`{{T%2
z!5BzeDa?^)Wt%bo{cnMyaySl|3~8_$9VFnV{L*br9uvA}Q`HZLd#T60Gg1%t;9Jn5
z@9Rw7kIme_`)shoE***46tti)b->M_2r*yKf;qF0lEGK;Ti8lLi3Q!>IwXt_AmXmn
z!M2}!r?1YSqlGS*(k~^hAruVV<^oeJ&DW9f(@r&Ju&H21z|{s+Rc-ZIWUkcFM3jJP
z(`V6Pdm8k)9=4hWJH(rbk^I>z>?x<W)%T%^s2}nlA=7e<{q6pQ|2wt+pSM>`#Z3>T
zeckiQ%VcDFh-0%if6Od<cORnq)^wf>fWX0G`ZjIO={XjBtCZ>)rDdz~1`%=s?f`dh
z`_(Fd%9ee@e2aOwi(VTLLlUk@ct-Ms76MPLzjCaN;tt>;j|Tc?DxJ5>QhSIeg-wrC
zmx5ORLoUYHHp|h)ZoRH>HhhK?NaahGJds6tAIkQux8}kWy0oxbajKRfP|DLHnNIV=
z>+R|IwwQRyTyb#}btzJijPJ7fb51Sr6{ngQI(iGTX@hxFY(Fi-UA5i|syrv(tlBzp
zoIg&5jpM;*m7}0~i5#(%@hU1?)6M`B8EV{|I=xnSLnjnH^F-FY1DzkdvL}@lha1Nx
zWSbb(|A2?gnu8bT@P8)gcM2urfFE(NL0BU^d}3Q1V`Vh$rF_mbTg>+2{+4{^%#<8C
zDVY_8vhvEU!+Lf*D=vwGhfasDfSG)R?L=JC8S!-F-BG*f#AbkK^&w)~eCQ<w<{}g~
zX|=&8@W$nd#WH%Q-g5^=E2g`^0kh9bi^3O%+^&sLGvUoAR`+vA%T|ST-I&EG5@$v0
z4+4@m%0M=1%gN7T#LT$DEr3Vffdn^<^Flu5!1?@K8Ix<MT=wR`lz6A<(A<(KW;;<M
zp7`kRUOuhO&zFnSMAGC>UIV>9@jne@sz8efQbS4x5M+l)db??+5J0z4&uB(ewb?Mc
zyWQ3tjB7v(c5jz*dAkG;H>J6H+WF)t$tb6Ndfe@^TbSx-Ke*-ESb3>D20b**8tSEY
zIc`93l9vAGV}u$LVLk)K5c9j|#z!aRBt76>??|ptIT4?mi5&ja1`d$sjgePbKl04k
zTGi|>x1Yo~&E}6-Lo&2P^{9C8#B+>tnmvVJ4vI%xUAGUturxsXzCwLl7UN|chNOGT
zF-FRT!+-pvwQgA3kcfFMIa%wI;+Zj{lBNSPI$oipUu2x<yAAx2<{de@q(n(id80Bn
zguLdQiV%YW;7jnH8i7U>DlMnJKmvK`8($e!=4uO-ZQDJZw@OWH<1rgyQfL|4nf8@Z
zL&2knMNH6fLn3p#rk2s}I$snOtXxwe@+xns_;pT)*TIOPlY@qkx?5YqvuBqkGJf>r
ze&c4PGcK-}?xJGcQYzPaBjxv&62o-yT+h29LilHrQyzZmiA@QX`Bx9Tc|2hJZ6nwB
zRW4mB1mQeLn8v;Vt!OzGl;w(T=}J<qzu4(&3<+nGnpZZg##hKd-Uo)K(SYE3<8z)@
z=Mc(u*5YcuyG4AEtY_W9@eVVYZ?K)})rfEM9}eaB*5n<QY$%kwO|;pLrOoqwZS?DI
z-xb&iFP5BtB_^0~*T3p9nQs9vxa?QB=hE=xCRjOaw`ZX)TD(ywk8K6hjk(126lHI?
zmw^UG5jWQcs$n3=kI#Q?h|&uS7QbEh9p0fvYbW&WM+8G4^H^S7E`N!8=jy4C%Bnr1
z?0?LDM2*{I>TNXv)PZ7{<Ynu*rc88*;(ZGtt}CFmQ^D*27CHVUUVS};lBG4egAY_+
z^NP=yBF(ODtO-iZ=U2~d6Eji+#D}VMpKc!9w+43L_*^D-)S%JF_wqn*gSTfo&p0|*
zruw$+6ljl8sn0S%0i7Z^l;$@L>|bd1taA}%+!+#p-V6!r<#FQvB9XXuJ@_Hi808^r
zu^cx9MZPA_evKEEBjR>1r)`IG6-~Ndm$j9vrbjo6Up^t|=5rYGv&&;*1m^wM$#Czr
z{@t7(2hps~5UU&Bh}YQ?q^Vf9z$Eh>WEXG9^;Dy0?XY^$$aB}uh9uZv{2mD3Pr0Gs
z&R2agvsc$sFA7m3I1~}tH4!9^2JF~yrn=RJ()Bo|mjBaw)v<44(1I1KrxFapVO1sG
z=4L{(-p*w*cG>AB(Vr5cJ@H$USh}4wzi4p0(rCmHVL7>UOEq#qq(BlRTnhy$2#hIW
zu^o!60^Dl#`dn03W39P_w1<T)mEfO2wv-q5@hON(u6MQ;Iv>1pjb!pw>t>d+8Ts6#
zs3qzn%jpDHuP3F5rP!P0WAIsOrE8Ktb!D}bl&Ge(l3)Im9#^<&;|>ydU*S4RW-{Cs
zp|(DYj@qCi1aq#UJhiU{YW7zWeIGD7Q9Wb^u*@9BTY?7S8q~<+5~FxdSuUdh%?J^h
z-;1wtr(gR)(7yR|bI|Pt=JjOACxc**3y+tu?^h;~2XuE6=p7Y98O)Zn#N8!zb1_`N
zP>(GH{EHQJXMUqxSvDPgNkSz2s!^pMAp3dBFU?h{OMN?9g0Y@_WBFs#9b4>!+h5vY
zoICCOJH+)R{EZ383JDHP!gL`!*XSG!!`g!JD_G)cIYKE40KG+?tKNk1W1QG6+}`xB
zTe+me(E_#pufl?hpqWYd#;5&+Z~QAh_F8yJP~W5J&Mo+8XV?!~1+H6MYid<Jj~#g*
z33_ZpK)7x7V)IicSsIrirZ`spc-@-{<LBr<Pr_j{xozm-h9e})72-^l5Y4u8&Mkl5
zoj^yZR-g5m)c5|I9geNb;6WM9geo31LzM{Dbe}%(9ocf6DphQ-mH;bVCLg<SGWwT3
zHKwZYmv?jt%y9S!f~YXWe-azCcE3A0vPanDE8UYf^iA*7G(`l*1XDZ%i(rDj7BKmi
zI6W0=hb;LCSL}ZJQQlL5cky=;{K!CEj;SU!PCI50pz{o|*4{Y+1dEcuazq}NR-O?7
znCcv!ZUY04q-=>JkXI1}D=RR@wd5KmWA7S0tNx4e6EW>aCIUHX3N`i173qxrxCrbd
zZp`#Q`cE<BtOL`e0V1wn!ceR`NDb~Q&bqX5_A~8RX?ve@8mM<=d_l98QL(E1B4kF;
zl$vTkAH=MT4r$mZG~u?n!7$($5SXx)I771TP-;=k1xO>|G%psePu;wERqL^NcY*M?
z?p%6v>m+$A*UGJp@+~OAmjPAMayOr1;I#!nCL}bBhktPy1*7IbyIL;J>54F4lXM6r
zh@6p{FKe;Y32<!qS=!qDWwV9Jk2pKj2FWK!f@ya!yl$C_&KV#2Ht(N}x}kTu8B0fK
ztMP2_78u*Q;i1$QwtK|71FdfS7<BqW4@VZ+e_i6{MhK^7t2QERJlG2~kG5CcZokn3
z2b{FY+wWtRIb@F{sb0KXNLXy!yg{RF0daP?#U(Xvfr9Gy4CD+=P<*qn=#9$G4pW=4
z0e1~Yy>aq8VXV)ka|Jt;$JKx_jk>k5VO~572GxJ$_gXpps;3X=4qkOL1U19?Yq0aT
ze|^q4UgC*w{(9i<q179(#$dneU7XV}eK#kAdd{vQq&3OiOAi;oBdspYRCaj)cE=(t
zFaYaOy>#iLVdQF%^|=VR3e18Z$^k9#aXhRf31)q)q-BN%P@d>Xv^cuYq{vWT)Liz}
zzewsH*q@$EzT?~kJLTbZw!x>6-Gpfo2>i=S^}ZmEExY#E?iEy6LGaskPn--CdXexR
zh+i@eA7BPpn!?lb+Ng8MTyWpt(C2PBG~K8%VD^mxV@A#-cy>GgFX|qa8C~q#rCdHE
z6g~sKrwsWw@d@6#ravKDtTJ0(JtU&xF@Wt;UbmoRp-0*Te6pL~G%B#o7Go>iEa0`C
z-ZW9h>*UE`P&~Ev;%Q?0UIyh^oan{k<p@8~M01Rk%k%swCm)iomqwj{?^Xz=gx@xE
zymB8<M2=vfP!|Uh7fh&hH?p;l!TyI=5DMO$a@ljH8vd)+R>t-QRe(k8TZ7F+hNTg|
z0D$aRIGSELQmM3Knw&wzro`vW4n+VjK+wNeY{vOT%!7^C&;!_5r<u4(#U8ci%yIbJ
zazRdzy3gu{-%2W<*I$pRko7d;oHM3c$R6NmD8V`nokDVUn6_HNG;maP)E?Hy3KcZN
zTta}ShkfC}6iZFxEN^E}k)dii**WANANM(rZQ$u#r8WMlNK=r6GKo8TqUC=7Yg0ST
z^y&S)qGBPZ-CO}{Lh(DI{}qn}KRg7f6cz<tComKgfTl%Nmpzj2y~}u+8t{{6A`c6r
zOfX1p2z$ax)SaCP6>uljc+E?i&v1v|8vFn$x@k6_8dn-^()$0KL+nG-y-wP0P%8Qr
z?2zc)B@mt(MTDP><jX?dJgmbiCqbOa^-^@+W9s@CX>0MrsDi<z8&05OTlg{Fl-d0o
zDyIPe0tVHU`|ti&>NzmG@y>DtH!*Sq^Fcq=b<z~iM2tQbVD(E(=S-b+u^B?%zH!HZ
zhgMM^xb}Nu_8$znPSad15toeX*-3M&Nf)YsEQpRHyYBl%VwauMFF!bzNST}yNydpJ
zUJMfTto~9<nwf#<2d#*SQm_ue=o}an<E1XV0<7S{v!b|su7AuvT{``FKvxBToI1CB
zpx=o^;>i2xH%utER$l3@S&cKqbZ!5;DgjjJ*6S17ThEw5|8gK`AV7x;{rVi_*8myk
zbq%(8KzV0e2f2gB?`Mn|;PxPD6g|3vT(#)5a&;d&R>c(Ag-)R02_1N;Qem8rlJ*q^
zC(tP8rDP)#_dc%C#({C@(O?fQ%}oc!#)7lvxr-vn8WhO}3olZ^7}~oJG={DSQjk(q
z|H!qi`#BwYgI)X~7s`0ray*q^RU0WqG9m6MOaCc<CAd!2>I%Qcjgh<*vw^F4$;o!F
zjD`H0T9}^5n?qn>hbgkpVj$whoF@GJwOk5<yf)EMKEwdj+o1AEpK#$q+tospT_`zJ
zP0{N*iz_dPmPLY_$9`zyv;ZMpnG`xVCgEe}wbk<KmBOC3>On1FgCPFYbBphN<4)#*
zZ5A5lNhrB;qZEbYuI~k~faSF_lNy=&OceaFQ^zer{LgFEQG+3PQyTAOm)~$=;RYuH
zmb!R+LcBn~Qu8~+dH*3Vv6)pe5t+Q#*hz@sJYp)9%I=ZzssdnofyCv!pt_A~CNA;{
zRM$D`^*_#iz=+ocLmN0X&ZQ?mdj-OgMEzv$^rUtIt_4sd_gsOfxwtW;s<iOxgwpFT
z0RvM+UhEWp?4@WZV}rIN{I{L3)p8BgGW;{Mtw>@rflhO7LnJjQ?yk92G^KO8dLTx}
zM~O?n)FR;@1%e1l9%vU`5_Q%A6G8%)LfZm%Ofbhmo0VTUBp*}Bs4RN-O>?~)JdLYn
zOms>Lmhb*QMfno?R=Qv-+u&)EipGk`7C4N8&`xBvtDzR!6KtT=WCrcZFQJdY0<mYL
za}8hG5Q!{=;~z9kBOu>^tQT;q%$^KM7WH^^f&|x1e}ZgK<WHvP$1KAUUd3ynZ8{P!
zkS(2~4Z&7vuK?n`8!+yA7uzfzL{r~XRQwIAif{B*v1%-*QdYv#4&^PnQDTx)vISYu
zF{ve7z&+Nyb5CH<gMKy2KigVH2qs_(J{pW>te14~z+D>q1hU6#`{`f*YqSyV8v^Fs
zKk>pIFigUv1EH5^uIY+SMTHkmPa58^07FJ>YO;~!Ec)<c=LleOdfS0f@Fwrp!<E~w
z%y>5}&ikvW<(iksvDc5%MTv4picurJc5n1=Q=|@R!(HD822(c=EF4|y`lz7lFaq8#
zO~#i(r}C_1nYs};aJhCTei#qum5JH*00Wt5B0$PNJjPYP-lCk#*8hh8A92xeu>S(4
zyX<Z=uC^<!K9Jq03|TG3b<JES*Eq(X#Pxx-AiL>nzDi_aL3GM2g6mL4k+q_C+4k4=
zdO{&_4@~<B2?`t53OMB>EtteGOBsEE0nsGWolhB!p6B*t=M}txOdcAMS#}S1UI|M1
zcTM{TDw8*o`$2QoFTn;K<f{S!5#rdq?rehG?}>=KGVn<z<(y~`jkS|`J%8AA-Exq0
z)1n}KYsuf*8KPMi+1J6YMYee!^|smGuWpL00I(dXxr7I&&9Bpw+&nDT-MH^pEFv0P
zA1A3q#E}sTi{WDuVt=;l_b2`;X1CN>+0D(HIY$72l7ICX@VULKt|+EwmGXhk+fPS*
zCiA&r``x5)J5b#^r|zZ$;q&S22sP6bm}@`fCjq|xTLm)+%o!F(u>O^>>mO=7xH9(u
z??TxN(Z)`7DW6(bDP;AKu(Ioouy;}jdJTN1P>-RX0AOVF@yUh7c^u(yK-DBm1@9)B
z<Yfg>w+PcQ>VBPxoygRdl-^oyiAS$dRRM)h!^~b*;Sm4kkTG`C3^MQW$1i=5K9B0K
zGzDJs!20GgC{EG>YmrUs)NFe1bcNZi#p*Bu9)no8WlHy>aQr_P%NdY$cu}$5nTyVU
zrTW`_<d?w8kSr>Bp}CAM0-<xha|WJ=G7Rg`9JL_Pvr42ED%bCC=turIKexn9|B@La
znl*1J>}vXsNYYwPrgTPzAW{H2DM1qbQTPyu1)?%);ioDMn3CPcCzE(1b!|3Si$LJb
z{WP6Y1=tc7u?f}^9?0rZAdb$3$0hB3(R#>HLURHGtH<5JOTNRmK$~J45NFFP!P)CF
zxvQw{bPCOi=$(3<-uCae%V^A3&M*qPMsK_DJ^t_9qw{8>+G-J~u>=_|r=rGz#sI#Z
zN+}CH8e-b%I!$s*t<0>m76_Jk0313!AUiazQd1s(*i9@ZFKlZ+Ofg64utvVEyq~@o
zB5g^JDV6~RFe%5$o$gjy?`4^QLMg`uet|lm&7UeE-Q`@gmv+<C=>{|oqG<5LxbUSh
zEyf_1_W;F%-}{rqQtN>N6e%TT4=#FWJre#yp5}M0ueh%M0P`dh^-YJdZ(~;Ko@N#&
zFO2+5qWCd;5<;auZ-ukn3C23^H3V1BtbNDvq}ASi&AYC8zdWLjcn-k{h*=L~;-hNd
zH)0p#(O0ehP<wRsSlb3(!y%+cnzmI_?cbDcbZSL4bPb(bxh*Af@{Ku9C0LDx=zGPm
zxdpEXYKlHZe;3eBK6RP+qM#7AWNX&?O<lqc4lkDUwjgQ|aFqgv0>H)NW0opEYyJm=
zJ2gAglV<)9vKHux7*0#`@5Bp#JjoArrmpFshTj(d9u8G(7D=?Gt^9~(74-<~v_E1F
zPAPWBz|dg&ew@yUzg%eU&{(iO-MH!&<rjc`WG?Hd#A5l>f#K942VniE+$al!;aVGh
z0;ub0GeK{AnI+aN<;$xkbbmN3Zky{`Kv$0=*TMsO&ex)SzHR0S(!@mUT?*qMm2qBI
zfS|`|D}#3-JF{20I>G2i7|s{75MT(`Zwu|Bu0RbJS5ywHysoO>&C4z~x*@LyRh;mu
z<0?zWxUw@=6Wco24l}8~J^17}F(B|q7c<^;QHBOZR|x4I3nafvC62GwHhY@0oL4CH
z>p+Pl!KT(%IjdKsFKQM;4VcLBN~;bjF`sbwg@Y!iG+_C~|4qovjk8h?+<gF_7e8uk
z2sNGDv~7X69}e&MWNvRy<0TE`Ge(WcLn)Kq0khEcFPa!ZX;NdYn^EcLHD?Oce}kUW
zB0Kc|$ZK;O%mx>&TJYGwvYaaM_VG`-tc7u#c-E9?WkzK?7=aWpdn&E45%-{S1z$DH
zM_;d5+2mIo09qz&@1$2U+hJG%O?WGpbkL41CYUGUhagK*vFEJ5Se#-Ch6dp=Wxe1i
zY<^<+B5jvrWd~d>LqY2s5>S6=g(RyT*85wKkYDMe-R769S_tT~gaw!s$H@52boR<`
z+mXa1DTOm@n%7JIW6b0G=+DYoCrBi|qrRC^T5u3V6ar;OW6lIth?U)Oi*VJtLajJH
zTxbfka&eXNenk^*bNF=X%NK$Ctg_xE4Zo%KwRgn>zUv?--vEGPGJh1a9A{{^eZcmK
zS!)Gq@oS9k6+EE+a%^*qEXJbn80GY|B4;-N6tH)BwmLXk9c|?W^JPP3p8}~EH-C6$
z8Lv57txu^JgY5i17M#3+5St@XjsLDg&p^Z$HxlAtC^T^aX1j37N_fCmdHqOud#j=?
ztx{_jrXu72zaD{-rX{8G&us+hvWZ9iskyoGkY!jqLzBbu0Wd%7?o<RLp9R3jXvF_y
zDypnMD65({AM_faxIYrIRy}?K`%~ifw#9GowPD8H(*7@P5?MMiB&YM&3>iC5KHFuw
zs7{dq-;d|?3z4H4K7210%Q-mmr>We%???yYy2aXE$0b<-=GCUrCv=miWK)8#Ogo`;
zB>)=DE)1`**E-(`{(1||H}`D9JN}Jcx`X3^2W_>L2X7Sx+IZ;KB<h+QnzC4v0ZM!{
z%_JGDf*W^cSNO0XYJ^vJGuVrNrXqa(*?CAr8aeE9>&_HBQi#B-@mcvUL0d&<E8jh!
zD!$t7;SjoXpEEzO#*epN;aKN$$8$J^!Z5JD?s#}2@<~KkFZOLnm@w#-ZSnFuSPtWE
zB)MfYjeM`V9Hu%_-Z=M!9@f9~aGOCfQKK8Ab1pnM`($gzM_mj3hjIq76nw|jNmEe*
z=qvDI4)b@zsn42>zkr5*&Ew$bKZSy@N)H7UW$?;bVn#He8OScz9rMP<QB&0o=_7-5
z#ok@MZ~Qnegneqr==92ry8(=I0*dHOqZAQD#}8_FXx${d7b~}wk|sJh2a15d`e>k?
zsl%$@U7Bj%I#sb4-bW;k|E7QvM5HyKuyK`wGk!69y8ePI_XW2$sDVmCY>KQzz`EWC
z{6p35MA?>{qYim{nVrtG&`D$Sn%KktSJC3$XKx1|z$~5531ccqyTbq24Jtreymu6p
z>gt4}?u}gQU2gx%b(A~`XnY>LQ2#9o#)jmIF{!V%;@bsuZ77F^99`gJrw6=Bk#*ry
zKP{KmNSj4BO248vk}-`I!a#GbJIIL;&qMqQI)~PMQe;~w4mFJXZ&8bsqxQd&0P?Bt
z2dT)_Wa;2f5!J~`BZmS^_-&E5f*7x3nx+lM9cV;v3GN$Ja#W%9Igqoa6hf{hTi7>L
z_QRTe7;228WG-b8aITj)0MKr^P&Fjfk%g-29Y(n=&rWs5)X6$}i^A2XBi%&$7;GRQ
z0HmYdW)JrdyHKvOHl;4MVGjPD8)!fCr+q)(;qEuWkI=<N#|s;l^m15(SFTbjTtAGx
zv!yIC2FG@d_$}M)(|)sZJ1BW1YJqwgy9k8tS@oD>q@_%6snIsVe_r1DpnM83#*KuO
z<&o}K)&M}BzxD>gm{#-tM-LMPbB<F)Qr>-@Xp0L7_F7I0Y(|Y1f_6&II|jZy);8m7
zC@jjO4F)q1N4hAo6VMvL!}`{u5DojWb)5ul_L(2NTx?AMz6_!f53^SdH!{Ql=*T`!
zom2pXWn?fFKxm^CJB3l@xfes@@K%RWrh<mZOfw<-K34S^ki_340|y7tmT=M0jy$pV
z^ox%FIlS5p<8vR7kP&ao^XVwE!GdzO_+9f0kAV_4)m57y-(0sU?713ny&1_7wCV{_
zQDEND+0?y(bdAJcUX+naaRIDM6BuT$Y}d#qQbdyPZEXnufv1Lb7^*<lPL&!c?(t4k
zUfp9EHpL{|!M=OhrJ2G#@sHy`^g9YN&V~aNGdnH{W(qZeW7-~Gr|*=fMqug_V}D_p
zsJ#gHboxuADeB)<@934|%n2ppcG7utR1UX;iAallm_xfMdm$lTS>`2rX%khvS@;6d
z;usU`TzF$k=}bL8D5+_9ViGH(GAK*I#qOkt3_)m%b|WfX>*dPTqM2>I;;k^nyN*r?
zoArx`+3w@DG!#fnKf*B_9OENv3{;fHYt76M0y@TVOc3ve&{1xS8P9i@&Xx}|?q80D
z$Os5gjEkdc@Jf_qW%i3*G0=0;Kk83?%}A|y_~z7!*~uhmvDe$IMWL+g>fWJ5ilZTT
zbY<^IQevGgJEZ`tqFl0M^e&1jrDIaxh`EIoE@HSZlh=}#+}Z9;riI8lH#-~Yj1SLq
zTZ`+f9bdl=z6LBIuLpR>`ewq6c1$9aQI?64;5d`X-5xps856&y6yf`u@+)L6a_O^{
z-Vv>@hsGnV%Iu+X_wU9UaP{Cofp9B<9AJB-m;Ca^=!5ku6l{`vxFRuZ9QRlg>Hp0E
zuqNlAP;d**fA+dL1S^dsCZDkDR}B)51dMxueQ-sIdytWEb_4gI&;9GY0_@MEZG>@`
zomg4z0@qyc#g;=5)y242o`=%8b;;z$TIp?+bdAPywXgbK1pl|YeJ4(Cd)ukjD(0Gy
z*DZ|Cf1Uh_xheTS5e$38{jbu_q71DQniFxCN^a5!mTbUf(fE@@m^8~s3lLGaM7PE|
zw;uLcCt1hinXF#321MN*O%bdSby1gxVmI?54@}YLRW?6W<v}2P*c&`9O3lBAJJWC>
z3v8`APJ5pk{$<np3c_2dT+L#{9WlYwvy6Yok5>3G%K^W-rPZ~kZHk!OlP{9Z)I0^k
zX8x*Sj`_AfU-{Y&6m28ZyIyNTGs|@iu7%o!{P@da6J#8I3i+k$ysQ%5(|*#pFhen&
zQy=C}!o;IWcM=h{4;pD1ZW!?gq+-S>9xV-N$nZZw(xF7P$g^>o>_C$5UA}UfuIzHK
z=d(2v2O@5TlV38XU>pI|$<bXWULrX0R>u28ouU$6HXq@V0g;cXy3z&z>Kdm0j1OT3
z0rB;l1XHwMl0g+qV&y)p2(?7Lx^(BayoqKdRO;2?NwMN)ob>`78;DkI)%3z|G_y`y
zGcC^Gq&QBaw7Ir(>X~`Is9uEXBoDwUQnx0$J}N`F!NbLocuwb!*Cm&!r>$CcG8D<;
zb|B_gx)d&{omxdF&JM;r32`I0lG|y%MKTZJ8VbfDtcb&@6BPPgqmU4jEFuUX@c3`E
zhBC}8?XHs*8$q!2kr~RuIy$H*nc8k^WV`p*VRZyRQ8KT3F$*z6G|aoW1_#;|I~<Dp
z*B}s1|LUXUl!_wDU!Rcp@?ToLW(gw9Byn|<=RHb!vk(G!=7q{uMk|@>qXFM3xf&I1
z<eif#5C$p_1w&1l3-`-$48^AENAj5xr}HX_echDI#8)S$o-DI-z_)jcUZ8)EUK~+g
z_a#*fWCcKnAanS_l=`<fQX>a*sC>GiI!69U(69u+Ez}b+zYsdl&82NsNczcT+~OrW
zq;K2}_2M4d#}IS8r;oMDn{69=?nzD=PrUT@EesUnvF_$T7F=#h>!7U>(DqG3_G2d(
zteL<H$%mkSC{^60#~B_pWWfI%$T?2(JUcF!wm-PtA9>%Adnh+}G2FYutpFU}DbsBT
zGSA!#UcrYxzYPD)wT<AM?+HR7o1r(Zc4N@umo5m4fl@cuQEY<0O6vPM7`U?`vvc5b
zgrSa!jj=#5ab_`I-e}TsN*{H|>_MX?;ybCx5BCInJO?&qJ%~hZ9cF^caQ4`gjt$km
zH|X@EY6Z2HjTvfN#WoaUI`oVLJHalKt&Ee=H5K5LQk^z+LYj)kcmC3Dxong>>gqh1
zwS0Gg2)aGr8HRu;o~?sG$<5*t*&v0bcpnA%dZTI>8ex=i+MHNa=?(^AJ&HXg`)6Yv
z`zuCd6wiM&A7es{#vofV=ADK48m9B<2X4tl;Ju=V*a&{K{6$!EVliBmG{#YFA$E}_
z&20{f&t6BO_Fsmo;Kidm32je@`(b@-nbQ8+yw`UEb`r`t(13XEl{A5ayMKVDqoO1#
zU7G{X;{s(t%uTad3zV1M3ei>nTYS6-7vlW@wXx<YHjwryrO*9+$E9nQO0?r!cz={%
zjSoo&nCf}0sy_%(9xO8K8$|N~c~+<CZVd}1i20e_fsObHQ_jh`L$38;Ju&;OP~4{j
zvjIRO?FeKX01wJ31*&_EPG-nmP!PfQbse{fwx}=JQ%~b?m#>3M`TfS%xCB5p2d(yp
z+uaG|_em9*%8-ym+y>}WmVn~i{k0rw(uElYe8~d>`T-L*&N}0!KDCX?A1?H_q^2O-
z!+bvs525D+!ARFmaRt7QN5V`U_IOnGf`w9s)4ftw7^Fl2xJ(A^1i4tthu<O!oWU2d
z)qV~$_N_xZ4$f4abF6@68hl{!J^pNvgYaFKkF?voX+BVpM^COYkG(bKZ@hEVv*=RJ
z*Hvd#q)So618!O68y67Kp=B0~s5{Pl3lvk<UWVP6822w(d`33L{<4vkA3Reo2@Nw_
z?%i<MADVkzO4xg`m^Y?=V^FJWj*!+&1uqM=p3|lZ(Wq$ZK2TGUiVXJbA2wgRZcnE=
zDk6wBW+U!DzV}5>vU~WUhmNoL<&uFBhrRd@dK`xu25xHx1%CPK8d3`$sD%+VgZd;b
zW|)!vbeBU(cP;rK5}>qtPuZWsOYpC)e1VQ-mnsOOsfc8pZm*6Sp4wAXHky$yl5MCq
z6&l>n(sS0=*D50{?XcyOon)vixGlQgH=SVWPGf0ZCu9_2g11zar)B|Ef;&+8Yj4{s
zF2}p0f5rP?OA8}XuIkoItCr>XjI;MA0TbPt=9f8}z$6dTxWVE6%$_uSi@*-7>?diY
zSzlouW)-EufEP!g8cUfI*lV1c2Ty@&_C&{Zp6D2ISUFSL=?xMW*WWCAVl+UD|IW1x
z|Ab6rIW9ld+2q30t4p&?+A6K&oOTwE^CxPVciawi&40A70SIvN0PUJS_-SMes!kOD
zU_q9ONfo;hKdA<b8IYRn0;$HFznhgf3E=CV#<96ZP>o5eqZ9b_h<x{llNU}oRX3w{
zxU3kRLMD)>u|rLE?1{6Kuf2CCa&7nQGyYg7tpMkEI2_D2d@%dIH8L@M8bY}{p!!b}
zSAmBQkk7N)%IlM76eSFG7jGOYNRuG<m8A|~Z+kA`SjWSU_L+4>;s-L8lEz1HcLMuu
zxYjU!RMW-sgtBcgM5n$f2DLcTf~XuKA*|n>ezFDR#+G>1CETS4BsX!?I!&)W`E6f<
zrN}`+;RQQXX5Lz3Prfb>E-FWzB9{#pCIcb|0~S*+ThyL+L2Ynd4_1?1@u<c)?KS~n
zc+D(kNH0n{e_|od4bnpi?j3JR6F$9LC2lxD`~Wc5m6XZV1oV7Q0I<(FU?%Z*1FR!r
z|5VIVBn0Y};%6=#rg;lgJ?Ny(N5`Rq&U5`ne$pOQf9_T}b*9dNlk`#_)}7m`ew&^R
zmPS9l=9RgF$fwUs*X$MzvVmlsTiNb%<WzE2CA!_5nJU4~z8H-bd~U=t8^gc;tL~aW
zy6EW0F&V_ggS1TASls8_vef2=z8IwPM7yId6^cGcWP(d9xFGK#<i`L5?~ktIud=d;
z-9~`h(NH%$_#QHy$~TSAfT~E)eayGkO;d$9iae^+vx=8uwj3D!#hd?(VG^{XNGikU
z+zE0lFbijf@me>s`-x~oE+0=>NlM$2=bnM<#WI%RVL)RbkR#MMysat`a&3dH@gjnB
zmqx6M3qs<HmTll+Q(x>ntDLhi+bv-o#RUp+vIvx6HVQ4ui24ZJ>4J$TwFWv+?eOz>
zLyhq<#4<=Kw@fae&g5yO2TLiyo7Pocl6}fHOxQ?hprhRF&ZU*qa4)y$_$DeUI@PCR
zAznnj=iRJ$ZA!7+V|4}&cdp^`(6gO@HKU^=Eo|=12!HoONrzQ!He5ZJw_F(Up$Z(e
zrK|f$h-Hr}p*ff>x-yIRBnCnV2gG+t!3VYbaQOrIE)1_C#TYnU*`;@-cx+`+g(m^#
zY_@F)4t5ti>tP2S4sUdH<olvkyL^6$Qut;~RZSTwo0c_cI~X#qc!==4XN82Yl$avQ
z7!2=_JC}3iB|Fy3EVKcT*-oTp_A1T`qYd-K%OPh+I=IjM^Rs9TiWX?T;iW(Tx%gzk
z6HVXk{aOviUwn!H<~$mKPY31gD1cjd@KC6=h5mpXb8C!JdqUHLt=qpw9!DIbEF*CU
z`ejm39*-Yq3t5hkLWN!K)+A%snkKrZ56xSepeBC)KakWtplf3!C%ti+c9gRr-${Uj
ze(<lj-t~N4qNNZB&$5`;`;;TxBe_ri$+mLg{brO}-DENF^20}@-kf@T^G%P|3Sy4<
zcBw$laT}QSillo2uYnz@kSeWns0dR*0SRJ*eByHJ2sP>oG`dfI<Q8XnliwmVi4?T3
zq_S)K_D5+e8Y2b7Mjew&*j_)%8F@B8Bp?YD?9E%O`bYZ(m8hJ<)<IHQFNGRKzrjti
zET2{uQD&ma2b?iLOgkX7!X`vaKc@TpAw%nrTvs$Ol~&|w&m&3%+_tVIHWAD_m704K
z7E}M!YVlT(e_Yd}MQp=h>IjNcS}<s+(4mK4STK5h!*tD-Xw|3O<jx)1OV}jtSXMu4
zlgK3y@gMi<{L06sZcr0ktX&VX8p~q#L}>!YP}LFJL(&fV5+!av!8}xu^-!8*inZ!W
z<|99uM<IR;BxvV0lqme~W0K==AIfJ$miB5g+Xs%74{l#u+e=FMpU2PgLGTZVcwIy3
zT;-nMH*sA%T*}qhv1FkPG2AG9#hif1*vw9B<84v4U!}bZ#DprW1%EosNk^D8_qecp
zB-{!oW%?Zdq7dKTkVjec{)!Pr2EkpTawKB&cAX~IFt?)x3DMCKmqpN&XOskw)Db1u
zASzNnT|IbddU1v%SqF*MyxJ|zYVEnJ@Y}#9gu%elMsM6470ue|w10_ZqgI}t$6Bm=
z3dCDw%Ife4)Ux}gdN6Tcz}&@Cw_lq!{9Gq`rvZ~;oxo)libX5>lr8APzYk>7c@x6T
zs{^(UUjm<LYRS?<+nGgo*OcxRy3gYgF>Hk_fMQu+%(L(yIO}ytrgn)53}!yRhtoIb
zjx;nW6=!2_(eQ8i61AsmN>8nk2D2LT8d$hPakUsd412P(wCY^2*hMH}ExWb+ryRbD
z@_cqk9>p_vYB+SF?Pi`J(jFYza3}O2A{`i@?hv3roe1UA+D6#eBYTZD(CR8De8uZK
z(m*z~Y$E6NtcZR#DuxCW$ls5Rv@{Z%fJ8v-1szGyk5KR0x4U<&V_-lbinf(p&?)vB
zh2q0CBT3iwK;2bxx<(3r$1L!bG_iOm5Le9F+C-;eC#aYKQMGR8>3$z^WyT9CTNFoL
z9NgP6nc8`HMW*P$?d>JfW&iZ_Q4a0;d6EQz)OhcS+*{O6yyenkr15jVHs`STHCXFX
z#SmUne?Y&0<Mt%A58+Q33;IcvH#uRva$Yvx{AqR+$zva*%18Wv&YL5{)CV2vN!@_K
zNZOQNVxXuhnyz}kbpMkLG^%+bO5{>T{ei`j_sUYG0<8!c#cA|A$7>Cj<YM2B>dwA&
zw&gS%SX*QA!G2mWqcd!hax4;+JUpNA)7z#Z3!PpPe5`D=4pWAnY4csGlPFDkP7w!{
zz3=@_a9cC`FHeEH@C2cFS9sw7b?LYmFU^8j<xmvi5Ehm5YUEi)HLJUu_Wh|dmV8JK
zE!z7*PTzoj1k%`?P+NNGRMIPfcdIT){DihfhK=CkX`WFpqd+z)rQLyv?a8^3S(fP*
zVW&1VkCsVFO^3oV&M}Y{Y9y8M4D}Z@O5usA%jZY&e;LU%t&=<A9HvXz0m3hx*ef0z
z*^&KXjjLeZGko8*Dpbs3c+Hli_H4(peK{9o2rdyCPkuyyZC$#boAh{woQqu<x)|gH
zP?k$`pQGKDb0^NIz&}+|?pC@AT<lKyKNZ;GSJ-1vW+jYm$b-0=%bfkyYRMOFFsM!}
zG$k|#IDKda((@VOOba%Y-&s>J0TpUe)H#_tXJM|j@zojvj4I}7lpeD+;3+G62Iqz7
z--$vQX{F!SyptdMM><FR`ntY%f?O_VeWb2BxZg?rerRAB+iu#RTN_xG)mX!~@xA`)
z5>Y7bsaK{IcqN>W&gQ)Rg+XNeTfIPXXnP2-Zysh3`#TKH0NK(spMHmEvyw3~(U5EZ
zwL;J7c`-cM@O>}zfj3L17mZ<2<`cL#R*&Ke|LgNZgq7}@W_@`(5PQ7<2pz~LwkN1-
z=!k=5+=@skehQSgfEdCdR$-q!xc-Af@dH;U#%Bq=^QDeMOqEWj*bj!0+0bC84~9q%
zwS2LMz1N1SMF=C$ngnw4VSh})ATrKsr!DyH?aGAHom3MFqthz*75EO`x|X1zLR!80
zD(SCv#+LU7aCGCYKGASSR`Z=uJt10iKQ3e4hO8@fa0ApC+sU6xtCn?$Ty&E+wb91p
zoEe#eu%^+38oe69ZwFa}r<RId3Bt$=B=VcG)`{mBk1IAt-=SF8EjwLfCNxq4n!LLz
zqf*fbpTz+u6f2zDG4zS+@3cKAXwgV70JzBu@#p;_0b(p(X;;)7(YIr#?A}lrSi;s!
z{qe<%<$Prg+U;0MPmYE_xpZ9vH7O;c=@c$so5{WQHn=z-wv+TSe<r)EsV{1`Os{>B
zAFFMleX|r|FfAZk>HyLoysK-d0kzaBLOvyF_9TO#$eLzUhD0_E0PdL5wtS1)O~Y0a
z5)s}+&vp)?K{nh9Ga<p(ZHt>`|DL5_o7V}!T44I38Q6Dad1KA}0~Tg<VXxJmOafCU
z3%8*GBe}D=*S;m28_z@Uw=B^$F8p@D*rU+ViX6a<+Gk@vYLI3|I0J#H$6Kt>a)hjW
zXIFwvHi_k5QVMT|>T%YW6dQ3Adq#JND0it=yKl+oP(-8oT4GbmJTVm^fnbW6mb+Q9
z^e6)!P*actfIi1CUBYUF<n57*pOwLYRV?dAH@dnv=XQH&;<xg&Hfsm9s!z0249+=!
zJSe=9Rq&lof==LR$Ox~QzUHn&zh@jNBeo;=FQidFM#yE8T!brZ^YT}t!?mUSk0@im
zYF_%fW{iY6c?U0Bnvr{a0EJ0&({S?rmgB_dY<)nNH3^^R&|K8SB3Yp~a0wfOJ#lo%
zuE7Ljzo%n7>l|*Qksk_eV%4RaDAj7j?%0O6^Q0V|`|F=%r6`zXs&j6&Q8H#b@=ANm
z3Za`bg5B_1l5Sr()ODl=%7Wg%H4umHoWmtVoyBeP!_-C&#$DbpnPk^3XS@ja;Qm3B
z7~DPpHqm|1cBE3%q)4UJQ(?QQe9z$=BO*=X-EczuogUsG4%_bZ=PM;j(_(c@Ydr+m
z=kO*Cq5z@BUE?~l#BFR%wO*-9m-;Du>70d%AVd#ycG9}*1<7&WPYcj(YD0UiqTek)
zJNLU_(sl4KZe@kOFn^wul-#BGH$KcadL_nv^;d6x!UAsD1~;8PesVx`_Z_srG7-Vv
zFn8RQ4xr3b@D(-g4u7-(t>~@n(ri!(;gF|*U>fW|OEk&L^C`noQH4|2NI`CslM@(R
z^9>oThrzSn%?Gw*Bwm(LB^G_6h}Q$4rw<=gj|FfDNO5^`1DG$~7^(wEOo3}I2M}e0
z!tK+11k@H1hw0>xvhWLMtbeJ!u=fjO8eoglpTMKl#Ki>7RD*F-q;GQm;k^IiKd478
zCLV2jfn>AmE39(Bs0EV@dJ>WI6De@VW&6gh)aTO>t{-%y^Bjg3ap?;fR&Bx@IcSNC
zz|8zZ7b2NxIPiR=u4w@(0&YU3Ic>n9Z=SN>k6cfE;Z3)N9d3i#b^qX-jks|^CgT{x
z$IEYJa!zhb&9kua{+kZ7jm@9%EUVDgqN+Y#qE<HBs4W3+N;QgB#Y~bbaH)HOQ%`kl
zP#<>vMcfXUI~Y6_MFYxeF`2TudYA?;dEZ#*$P1`zCiPjqB)OO1Ks9mHNq=s@3fPn>
zXn5aisSE%@z20k|WJv`H(3=#2%0OK%t`OV=iPG<@Te6&>jh_IZw_-`yX4|f(w&>Om
z@ZjhYe9ahL)OLB*vb>s>A=+v%QrBsVZVOZuNgokP=dWx#ZU8hjiKhj%>76kPZ}yh3
z$K<ywiY&T{@XabGY+7BNQ@@W4uRDj+-ddZV_3dj)`$yQ*g|sRamI-Mt(4|63`8EWi
zenGP!21l8%q2`p5Twh0Ahl7qnHXZ|i1V_vbgPCPQxl{-Pfi}@g^D6fMGY~7gi^8G$
z4}jE^$Ra|Ed?Jw?^cc<7I8?mnG^JLIOArU31m2{ly`x&$qr{HVRN8qk5z>h~Hu(rJ
z0){DH&v5Z+U4%dhN3CVz(Ib#pl&f~Pd$gfK;TTZj;sG%(zbQAnFXP-uEEW6vqs}1+
zi(JTdJXAP;;X{s;GhD;E)g$;;`kM_Gdv_RLLOIHq9lmzv7Xy|J2<Nd24fZ;Y!aL40
zB24cW#P}ko2Fe|MsQ?FPBgc`jyJxgpEU%sf&SUKmTSBhya}w`FWj`IA%8ZId52BC#
z=m7Vo72Efao3^+qUEPuj_;!{T1)zSxRLpyMrOD$_`ToKUGFs!`!jC-IIe<5u`-BHA
zAyhUIgdy?j4ZYQ;MTUIIvj`KE=sJ9=5S56Hii&FIbEFxXn2&lwvS;?>Ze?J)wJ%fE
z=yvDv@;$dd<C}<CCZk<z%M&U~=pM@nI!M4fRt4-G6S1;3?838`vqgc0n10)|!nOr#
zFG)yo1Zejwhot2cM0w)9_GEzxRw4-}#+r`?n0*D@faEh{S?lju(K-_rq#NRjqSYZR
z+{U&SbzKq7iuWj!TG)Ucz{$SIcSsOxcc&=_zyyHIm0Dm%In?(>VC{3D^ry1bLtlfG
zhS|adD4zR*(|&QKj%GqPSNFFr)!Qvf4*iujIa3txSvNvoYC){$k2hw7+HX<Tnt^&j
z(v+!UP>qIDL-QuOvyk#egf}YN6s1Wx2|#bjO|U4EZ_%b$tJ~|*rDZYe@@T^nZq(Um
z{jY9RfS8|1x;nI2hH!W7s97_}9~{+}E^o3Fzhh9SjH#{p%V)KWB|Y|fza@~B*bh$N
zf0&;-3U+!p)g2~D_h}na=}V@5H;PlQP*|$2)i9$^a?=impmJ&@M{<ia7CyRq;v3vD
z&`z<zNi8N=Y1PrsI;N`ht0U8n`R`!kvyrY^oC-Y{&G~&sUt$?@@Cb1-ZPmE}!Ievy
zS;jm*_wIHSsMceRh;E<J1u2>9^Mz~c!~0n0cI~UI`O)~$G-ECL0ZIb637sP2f%J*f
z7mxF#3UwsR>{-F4(PRV;hdzgOfb_7;WTz!Rx4u}SyIamG+}UXck7{r^=GzL)m$91w
z(hS;H+#KX2%qlQ-34MVvG4v^o&s&)L@I!Bl)Qh(*^D}z`O+=|6tO_d73tzylgv$s&
zU<q7Zv_5QdYC#udpvOZt@|)QfSC0?lX8h^K(S}Fqox7;O%%`xT9^QMqFe-YUnu9?J
z0pvYoeVfC2XO{=|CR@3CFGvABTV&mWv-@Ck;;Oyi-BjGt+88mPBnvGK06~<vdWKc8
zetnp8B=<QaMBWG_nr-*3L7T=S?S7|1?pWWyoxW64-1Im)<q*FQBR#=GZuan1{cYxw
zgRD3fG;z*?X-3w<$QJek<z}i-P`blj10^Vn<2M%y!facFLG^clXWT(KN^_7<fd*I7
ziulOA^O^XUk8vzdYsx&jUGWLN_SwiC9nhGZ-;fF(8Ui(H%GQK*yIv7Kd)|uc3%7<D
zR@ReWl>oA2nZG-uCk|$O)c}keM|p8I5`c_I)Q5IHL~bf2C3#r0U2B+^^43Eq+*$qm
z<H$Ymq1VFo^s(r@pvf?H&MDhX9!B~Z-nK(Jg;4KT%)%u?&2$Rh`}0d^<x>HorL@)h
z;L0XmKi2*DgB&8m;6OJo(>mO3k>9jNTnAddp)<sQUbh+sELp3r2SaT6XMTbR+~Ots
zfu~S!P6iH;W~A%GKD5KuYJNk>M?x0?IAi|GdnR*UAxyINXVIraAJag0YTF5|1iMxy
zRpe4M3~^frUvxcQ6QgAvT5Qgdhu&!QOK%8f&Yf(e_)9cAmFCgOqr4t_Wl%hWVfl$a
z%Lx5ct}HgZRX$)y_k#e?c|5$>B|?(!mHR=axRF#r^R_N(uWj7!DxZ?&xXsu)%c$sH
zQO|@J|B||68k&$(t0r<37FA#Pv>%%NPlN?qZb^iI_|aWe!96Q!iB82*vbyjxV(y3V
z<}!9Wr@2iXJP0iTdhf6Y-`o|y-J1GInB?HwhEgf$UcV|Z(AnJH>dx#1inYKR&nT<Q
z6c(hF+bib0u%+teJX|DS>B;c@v75ltEAn^bdROFvp?3axe;yD8F_ZNor%e+Vd#VF5
zF2%<F?}89}xeecJprOCTt*-ceL{LG|PPaOyUdTt}zck_Cky4b5uZ=YfVD|{d8YotG
z8Gj|h3aQvWc3dVHsW#w_+&~_SD+Ia_i7Z>ll7gvQ=U9BG-`TP3%&19LrSFn(6yi~=
z{v8a#gBzuF6VBU#SiJOpdIh4+_zraee1ptkE;f_&Ta6a<wQw39AFzFatsy1ENXB*~
z{{cPo@drWAR=IGKX!-GrjSQW17E!>J!em0Ln``4oLEx1hrLBc=G>|W|REhGbb)ou>
zc>$?Q^E0>SRBEIXB{7PlSni2#dn?x}<&_D33ty318C6i9YW-@~q*}?0pd@t!9Uw3a
z*=94tE*QDkR5}<3b(HJ8ZO=1;!)iUdek>FxB3_~Fms>!Fh2sWfTncPau_7n1R>evj
zL<b(z+yVbhd^|+>N6NBdZsDbNW3JmJ*rGiTpKm62a<0|SVj&5`_@=gQcB0dH3Ij5|
zz}llQr*jp+{sreJdve20!BLJl6_~uS9NUKIjl;*ZljMF(kucmcbD(#;)Bs*@7r&;Y
zuZ_kPErBE2^li&`4l9GvW$3Dz2lcuFFlrh^P+mVD_N^4kc(NSz{71H6fCn9YLIwm1
zV2l)+m*sr5g|ecL8gnI+-2EW~>IXjf&234g)CGw<xxZ1!nTA1Vp#|ECW4#Edxf!VJ
zZ$oadqYfnc6bMAp%6ZwxPgy|~+vW;T7u+FFXhA{S;t=VKypOynjWje?<)WP*1Won$
z$+ar{RUxs#Lju2ERp|m5bOL1}<>C!$^9OFnelf(lh0H+n*-v@c%p423|BUb7ErLYJ
zlX(}r?bOflK|nf~QRZu#@nP=yT8x7ne7p#vtY@j|J&o|Hv46ak_aEX?8mgrE7K{c^
z9>Wr5s~G2jYpEiB59N`ahRTS+fq>8~%{|zYJ*c6ao?yH|<ts~dommr|w>z=9teqVZ
z7MqDPfDThuCeZZ{FDS(Nivql2<^~=}Fk0c5fXZOzNkPn8UgHG&Q-weN37#tK7Ts%J
z){fUVWPd2W-l&sEs>>B%!*hkkFdQsK5oTVegkXUpiF){WS=m>Yqb-g(lU0OK4tNJH
zxCKYh_XVZ)KS=`B0yYTNVa=a5cYajGg#AD0Z;z(w>Ir3NNIF4+6U*$%JV;ArI3j}<
zTu;i`Soj#e?0DMSWM8oJ?b6KwdAJ`V`kEXf^@=bza3mp9AtCSn%^)WP<f2-`WUS7B
zDG+D)7}Fbu$+K~d((c7PB~(EaF{NtT+_)J?-NFc!80V3a5#=f9h3{?(vQ1c;y<pfO
zvp-uB2E3*5bD)gXaMYbBUo>rE=v+vo1RtEKF9?e$oI1I*Dx4OyvBazeu=I76Hw0e|
z9>bSxXfxakXzl{w%WLLQYmVv+Ky|<bs&RA7k^6S?*MdR`{4TntdMi81>mO%z+MksE
z@z7SLq3L*tu>}?wD7Eu=ej>vbqSJ{VtjKtI&bmOIIbk#-ve!OgKBeou)Rdx@993PA
zQgg=?Kbz5U`6vIDw#P)-SaPM)n>>FCr6Ay_04}E{-~R^Cn$gK8y?&Xz!kdl$2z5qo
z2%d=xs!=(70acP#{w9dM6T7}Wu-TVSJ|YmjS3*k-kkLhHTN~y6-LuqLeQc9sam-=j
zwz4<MEHXDrYJY||1>ax?R`hsykmJf+0L~`JP@@=JD}9<WNWPq^Ktp?4yrR)x3$D$X
z@XyMs503%FKT5ZvA~gNS)BaD;_UlrL8k~I*X9<Q4?L!NMZ9*@{)vA^6cu2H-9+&Ab
zW%f^f1$5-oF`J(Y-0C1$hIvMW6m>584U{2<h}5)+e6QA~NqT$QR*ji|Nh=ucP@s0(
zWEoJylTpM0{l~S9C9H?6IiPhc;ih7b)v2OheseQbXjJprv%I=gxW8$MnRV$5Vm#a=
zpm}w6dJOfy<(_TxF$fP=w>NSLv=LsZ{$sCbS5`l$LRJ{-=l1@sZ0;kWkb}NJl7671
z?hY!&%2_A-&Vkh#NlFiHqLMy2n>h1QOioMteeP;*!3&sp)NO`+iI9X3$$wUlGYU$V
zi;+~lu0KGr&{Mr5W_e_iR+VAGfs(R+{uU*U5Jp4wEJvXa;?Jt9DCqyx_2w4G=Z%tX
zu=vWZP5)Pgw;k<>&zddfzZ(ZL3RgM)8Xp2m=jMs9(SJNjJvwwIM$NH%&&*#uS957c
z93l4aOW833%=;GSXthiX_h^&~PjMOt?iaSwDDS_3`Bi13PWp+n^AN`~&}t}D$cmGQ
z&RX{X8SC!dQZNpjN32SKfQD$7#EjJ^9WZ+Qoh-l7A@J%P_Orc)y8owNevTth`0;!2
zwwzGFvbGEmA>di8p>^3DO2!j;IHAaol+4MsgsQF039%FCfA0`Qv{NL|eIUdXHmu*U
zCs2Ub1w7!3eGB?mFaCFO8%C&uZ8NeoTF+Syo}nHt;c@u1tQ4i!_A%KKD!ea=V19mE
zcyAf*5MyX--bfCvr3HJKv8Xl$Y})}~5u|mq#uE1^k>&ZDC5M?HPDQ`J307wpaE^D$
zu}FPcrLUowO<Xf}NOU-i?@HF1sk30l6XWydiZKWCghS+mZ9q=3<f4$%ck;gg+ZNEN
z$#NI>a~7bB=AK{&JluSw-pNd(*Gxu+dvHKajd+)6#?qF@fBn18S9cPu!A|5XHQtO1
zOX@~*nq$PoZ&Ldx)O9<N*u!PjsC?U*asb}7V&+MC7PBjY5>pI8s?TR#baFI6Vk$P?
zP6Nk>U;?o{niQ&HB}o$-Ax~fG%<1DmHZpvJ`2KNY+>6IAB4yLoZNpqu5?A8b`~c2_
zYRzxhLXz-w#N|6q*iAVh!EwAj$F%ltm6=<^PiUX_inTk6UnKF(wiIE2dv9CfgDcC)
zTHBR2ytNum49*c7YCmyKaXQly*q{YtP6VO17k<N|s6PZ3Zan+o(&y{j%EY}x+)aXk
zU~~!_EUy6fwq^A<EE%lW`Y`yyZ$SC@(}a&lDsvw`x?e|dy-_g7?G&0J^YUPPa5&=v
zo+vKLSe!|`O>7COr*FXv;B+1!tsckms&f)gmLqwEo)4b>l|6O7v<&1R>mDw^G|%7<
zWyztbtjtZTtrL#Cgq8AJk~hHiiA}|lCWf>&%je}#Zc)I#C9&<HwO8oQ)j+ckZoTv6
z^n-73DcM2BJ(5`CrhXqBhmybjIw`O7YYS&@OB2EJbeYIy40s3IJ^d`HYD6&?19Nre
zQm|4*-t)L3fgO`6JH=VGLEQvG-IE7DS4YxrQGJTB(F4q8+Qf426^E$}elCqBYQZSo
z>-8D24fWZF2yBJS5V4O0hjY+2n7VCzFE*sAGFa*|7-2r06!PadTIjDO3imsq1Ud<Y
z&=sSyApfM}6fkS{;DDT`2{$xh|5NVw$YL;TGc)zPI*2V<vzEv&){}|<oK7eTUJIPG
zw1*x!|H(el>7}n|lJ3Mpwr*{a?d<DHoNya2Vw8|SwH%qxxXhCu@Vu749Jf3*Z<jb#
zwrJl#POcIWBog6YUp6KsTd{e#izyc2aoEXRMq98@94qTMCTCZi%dM&^?NSDxQFrjO
zU_~%4IL0E=aux?4@x0ERCKb5JAE+yF0lk;SKve#h>d5xzJcWunXX4lWT<@p*+wun5
zzhH@JRb9_6!YlXD=;Z)bISif8GE>~jh51G9xlyswuQKcTj?%deU~?m4Dybiw9X>Xt
zd?`0mx$P@vEZXqlKER+mM-|t|lePZss6Dh<L9KX%h&5*<Hf@8QyX3&fpK&n7LeI3l
z4&{fC$$|!ScSBAx#D#BHR;#h%>3J7s<D_~Zm2vmm|7*Q}ulJda&qeog-3q|)$Ky>e
zKQr5ftBX3hWJ*`iH(`3dR#CjQrY+~Cz>ijl)|z(?BC?E$QJ8II`8=P4y!~#<fA4bG
zN*fWoUxguxJJ=WZL7>EQV?pInw#tsl@l7z*L^8!L)ST@P5ZaVVOf1MZ$jLFz=GG4r
z5t<tj9*vj;ZSH4AF5jLNI=vq{i=>?6LEZ*93T$OL9=$cHIv7n?nGj;x^xDOTq!C}9
zejHAjX8~c(S;BF_kVfLUT6~H&8><MkSYRkgQX_9j*hS&G8ydUuP;Cn7AP_3yp;nlk
zl70O?{eZI=2emg8<OT7j7NRe~V$v;sA`r#_SR@o<6;MF`%88USQ@1*fb=w#m3(s3u
z>=K;BAzfl}Y|69^$t3)izm0DllcG(Zgn4b4dFj*IUF(cM$S$l<P+G1}<vwnT^dsj<
z_2%s6`D{B3e=;8MxCE<*owq;pw~-6EuONAaM^seAhI7ydDD7R%1o!%L9)RY3U(>3<
zg4!uTH=i);9uZn24}gqW<`n4mAu#kARYm4`%2)R8cBesaE6X0NcQnh#zm-l=YMU4R
zuN4Wr!YIizy3iMcO_k}ibVKs1EoE=8%<yhi29y}KrZJ;hrskX@xBU5;6s(F|F!|}p
z0FQq;JL3`n>gpX=Uc#3uRj8e&V-aSc$EyKNB!&`Q$d(dmcGB+<jTG3fd77M%cRuVt
zNDh#nkc(VR`qDVTm96P9>-1o^7P*DC5qzj(AM9~S*Dwq*$U9EVrTZ_fov}hLwQ#j5
zXFV^6B@~@=G8AK=LUq*G`rWkLe?;4>IIFFlZiT%OVg>H24{Xw;@6kNMpvgn}y}t!l
z8Q}<*e>W~yIa9^%+t4gdu24w8e5B^Xai9Y6K@fkAEL_-EQItTTN#*2=Z@6jMho!G=
z^(I~KDhOde>1LKa-6Zp^tq)C}LEFr-bg_+|52pQ8aUJws+Uld+WcPeAVm^{!qYbtL
zBNr47oi7W}ZYB`;*D4Sde33T;=y{3;?ru;{F%q|9uvr7(PE#2-PICP9`nE|D?D;(Z
z`TPc-XHejbZDwn>3~-BS+WF9{T1$(_{X`DL^(xo#Id`yfTz!A*j`gw>*CbkSfKC)}
ztTvmoJq5cadAnF?39|RL2&r@o#UO%)MRscfC=8ygmx<wf)*R?jQZkNWWo&^aBK(eE
zsr~8Lg?_RQ6pB9KiH=eKQ)h63A{i-4N_%$3-)S_r*?J_m_|`3X$~?7%4JL^>gEZ*!
zUv1N8I_U=^3{gx-C+BkBpR_%ujlARLAJu*ciY(Q*@DEPkfY5nmC)Jb4_Db{7yZ$;Q
z%1u^1=Z`|Agmw}W>arQ~6^Pgq5bu_PeJSqJDm<DY^@#_8nSe^o)b5Gum$n7hP)-n&
z(=@_t2NlkhW=Mwwe{>w<i^0JnS{K)?OO<ZE8(})TVUjR{U&}(~6E|&{T&T>>JQsU=
zuAmuPj;JBkLCVl1xeI8C4SWrCRb^y0uwHo5e9O}lI2OXU`dCF&icb*aVP(bf+#Eg~
z9@$RAkrRMr68~*gRd2sHi>Vw*E){q{g=uXb=1Xp&(8CkMKlZb_V{R&3r365+C*Bg{
zQ|SkLiDN{$@E_KDh2c!5XVgN++}tJ~nT$LrXt-`NxS~PY)^u=5G4VrGYv0|)YA7^I
z1^Rl;>A0woW$xq0Gqr4@kmuQ3GFAApp|SrE+#->TTMl^q29RGVY~HQk1Cnw353r#s
z#X!GVM3_A2($Uu6{ahKSfDu}OUh1o_W7+^%K&QX1LQI(O)|ZtzXzN=dHL7Qes3qXf
zV7%I3V#wN<q)teyfxhilQYmH0D>WmW!6sHn2hO}pg!4U8(zw|&BRv`{N%giyt#_z|
z7o|<G=I#5M-J*?{OpD#h@;;7rLpgaxFNI~t|9$B1?pppusR7~CjIR?E9%Y3b4HC(F
zq-#TSSW^<0BC;Ph(N~^^C@7E2c)|YOana33ulzV?C&vNe<dn#s8<zf713p=*{m0|G
zcw_0>q1GXbiY%1-$D~p$-XbtG+l45ZRtOIhSg?Pj%`jbZz|xEct+lfWucrupuoT?d
zm#A83hL<2Cui{`HK!_w6eZm;Pvi9XKhfY@dQ`#A@;%5-m%5-2M&qC1Gr6i?94FnL>
zQ=dd`9m6TV1PCJLpPmrAns);$EFyTImRLR}^?5c#g{H3GRVGT`*+|<oxeN%T52kz4
zs|d6X51LiOgUiN|IJQX096m1Z!EKJ~|B5vCP(rUD=yK}@MOo<#s<YsJ@-1#{3xT<x
zmb+ixFEYlQX~++dLcgd!eqq9G`$JN#K*qsln>lk>LsQ9yC{L#D59D!5mspDft|e3n
zlX)MUlz(m3FET6y_d{0}h!r`BK!&Rbs)`d(k2k%K^;O#u$lm37k-#Kyo*z<V+j7)!
zmEfS=!H~vP7?Sxbfg)E9#u+A??&cJeEJpC8pGvwwW+cF~4AJqJaGhlYQSDixO+AkE
z)NYKVbLjg^+tYSEEqrAliAk69h}gC$V%-Mp$<}E0mHL!f+n7LfKj#0^&}JQZkb><1
z0y!(O#<tJ2pa5&&=&<e_VI>s*&Ux0q6ul*5G-7Pp$1m$*DlYRI_%*a-Ki2bRB9*aX
zScVFAkQeOIvNmUxBCpr(t%K0nc-RCmBc&)9ssw+D>sV*j#7wZJzQO#ICWe%7<(rWT
z6r>TO5&HK8K*gbKS&Q%pT9}2i27>irj7$CAyp$7ok`##^lnwB>Kbr(%E%b;}m6JD~
zr_t90|Gc;s-KEFr8)!UTE&B9mRE$OUlQq&<`xND7J%|IMdOEIcwgE)SVE{mp+jBj7
zcjcbC?#>mI>9<a<1aecNt;1R572vbt!BjFTAHsPKT}(_Wy<_D*8qOf83hIC7&aY!1
z<1i9X4yJdh7H-bTM6AU*)yJ0JJMr~R!)JJ473q%%re(vgEAYf7aFu?NGM7EMFLiA2
z7>8zzRitcv0THhM<M0YS?S+T4;n2$o(7rBUR!1V#*)%NG8qVDD>Hi42&y}xS{~%<z
zO#)6xE`jR4f}+t2OQ>GNlUBib-9fe-XwcA*0<J*b=smyOcB4kX9>@&b3l7in!o72j
z8D2!$F)gQC))$eapl*$makg-YOVw1RvY_@9pFFKGfa&wtM2iZ_@{VyVo*twa2U!}i
z>A@=A3tmn%i6UQN%{FWDLVSmNSqr7zeaY~H7%+<=5&9oB<0HA1z}CElGgqNsI74Z-
zT4KVgb8v}LBV)G<(7<^IWwC!-70RnK*}sx@>0wlzNJTGug8z>%7p65pTj0CAxxlS$
z4r3Ienv#-;eibccmuT>RF;-3K`}-0qn3sw#IIKG|rZ#-{Xfri8GdxxD*6_6Q#JUD<
z;ao8O7X2CaJ2KmxVHH-uiS?<1EwbRc#?~3ht{9^80XTDZPt%$jFvJ)|p+3Z+U1)4q
zKqqPBm_9uP@hEAHzz1NJy-GoxE#9^Us=87%17B9-BN4fSA5``|Dxp3yXsf<bI+)B>
zOVhC6inWiH&o4vnr{0rpSKVZ}8aQT9d!b4LJMgX?9SkITV@EQ*V6c*V@-bscNLdEk
zTeD68tsacL&Z?fwmaR3}6e;fpon2V%<1|kaw6}<89(XO!?UZ2L?TfI3b1K~xkR=W|
z08*GCcY&^v4(Pd|2A9TNJ|jP~-uHwt8IcSak_v<%g4(toG94&+_Q0+BKY`#zs_|hP
z3zSE732>^d7vuvIK1e5bu4Fh58v$8~b@XQ@5}U5bFa4FJb*C7(&FU4PI9lNbkKBle
zyd%>1)B*UT@){KHR`QS+@}ydks1Fai>|Y<)nbvE#stYUP0F7@4!L%zH-i<D?O=dSC
z^Kk9yseJgmyw0r%m6noCE-m-bXK4y!nt-DFp}+_zVntN(-@#YNPO<etijSzmUnIn%
zBDqKkW%d=ydf=V%!DAa#U6|{UqQ|C&wiB2@9BKG9XjA_7;V>>?y>(*j*!i=xjdc+U
z-Xs-Jd|8w=b1Q$)_-ZM9Pm+Dfk&p@u(fRV|WNKl;<VfQ7Wp#?jN=_KvF{^?dd>|>8
z^^|QuAhAtinAKxzUZ(bCPB8;wq5Sm%^e^?a0Yy^EhHd3@t9Kg?0{dspE#u&G3vOQd
zM(m_Q%R)5zV_3(pyW$2M!_rolR$zE7bFVNdFVwhAD}z?V{GT3IgXbDnQro<^cm`HE
zu>o_+*JX+<MUD30_azxhSwTmy>3lSJ+D2$2ak;y<E&6l?5xXb+lag4w6uc~$+mOu{
zWFfDr&43TTkd=zN^YxIf*q6fy#wB$dz~e2HA<W0?$N~|+k^AYh9y%CY6nz_rMyz*p
zyO&9|Q=q^o(Un`yd&r2Z=CI6z*W|qD!6S!$-|#8F^HDI}<u+9C!L4YzCngz*p}RY_
z9G@(P7Q^WzY~UI{VB!2gO4PggcQct~@ytqzq{tZaEATXH--8|Fj3y@5Kp*e<_l6la
zCTWb{_~h6cUr`<)*L-O9(wdp_UCKH~PJpo_)VH|cl}p7s!SuT!tyU>;$2QwONC(x<
z>MQWA6Tkkh6VR`o$gV-GnuNla%PH><`(Hhd;Y2fv<`t1nk_;lt#X+C4`*l&1UigAB
z2diVZGSz9h9MJgMxNQ80k&jrv$85s(^^U#WSFOp?mIPs*1%GyMk!@n^X;JOQ_o>Zj
zC`tqpKXcol<AH~M*8e!$#X%BCD2*y#xFt!BUaBunW5Z|0npRcCv#$~*KCjNibRUq*
zQTswW&vwU%c9TQ{eVAl`M>EcQXC-gOP(3w9e)ohpNzDCs=-zL`QdN@O6l<h7aT(}}
z{=EIiY$|s|0@kf=>pO3RpMOV0tT?d*1UD%4UZy>YM5BB#kktb-E@U|oN-E8XEj^}<
z(}&#qmjiAxZw^d#`{>=j{GW#W^<~|Ct(gMAlBtjM5O*vMHc;9bXd7~YkMlv7iV)Q@
z-}7W+_FCO=)1r-(8QmgO1r*hu=!B`nq>n7BN&Zi0I-Il=Q^NCW>XXp`D!bMYmzAK2
z!S?g$A^lLJ1Wso?1Y;Ie)TNEG@*vhytVIyHJLRKBzC4_NqqT;dDl-!X?_jhp@`YAo
z=BIORV}8zx%ar~3&yy9Ym3l2yBKlc-rhpw=Q`{g{RK;N8cxku33?s7>Q$!m#(d|HX
z@Pt>L*T79Cp2~8n`#*<+<u~k;vBNq)J=#Z=hsQkB<**V%GqkN@YVoE_wCq6Bo{E-R
zmzr#*^J1%MyLg(b8$=vY5Iu>0S;*OhL=@Ex%okUih}?q@F>zyvzhfZG<o%)cP2rSj
zOq+u_S-{Et*)EWF0H0nIgyi7${v@hE$A!FBsZt?B*1^i3C(VtYdq~rm2y49E7J!!&
z&ZjKEBucGdb4Mcx+{hofgBD#4?}UWD`T*~NIP8hhaacjaowi%`terHOy0p0I*=+HR
z`cio_A=BI5ZTCWQ+=g^G{=M}*^r9Ga!N&;Z$m8c2ag5QQowl0)2Ce93jHre))=j48
zacjH2Q^3~+_qcNU;Z!#7MAY(d98GIiSwhaD+rU=_G;#a!UzcRIy$&cmx)OHeHs27z
z8O~p0^c4K`n;j-vgHw3XV+R8NKiJy_q01+28tSsTJDb&C`&+-YZHc(gxG1;0fL~9Y
zH6w1ytZZ*-EF9{Mw?E^_fr5*1WzL94vrwXPy)$%gVPXzyx`EcUNcZ1<{6IY^aQSg*
zIO1)MVsPSiNbg*jiZD&aMF3ioB-fcK*6oE$@F&KjZ4J%w47_=MCP1<N@1vEbLg)9!
zRwz}0T3kow*b*&lC9n<_AeW4j@#Zm}be0GW4=0vPu>*BV5=#y3Q2_MB_upTJAh$sz
zuipYNTF}asE%Al^*De`FWNAphsDgGtG#SB>5YYLHzB%fr1Il4bq2&v?^i8A?j~?Fu
z<r*xaU9>r3?H%~Urlz8{9KP~IdUjiLVRPXk+wmtA%~^N^4(A%qpbYRO*1`o3(1Yg>
zP3f|UG_;E8G$o%;TYo&pH8;1>Drq@$0RyjO@{tK5$4b?u&ej%nGDA+>(>A>bdjYBs
ztt3G>1(s1CfiJAhj*~CsV-S`k0iLuXrM$96Bwt6|^YB8~*DHYVZ!R1HctT&{VpBOT
zPC(!{5g89-Hf}HO#|!;k*u|Y=J!tr(DO3YjcBiE+XodTDNr*|~W7~zC^rX4>4Q-&2
zXL{W6460shaQehwibe9`QV!mS%B)xj&dH7VqGbz8MI=>P(hb~6aDM;xZ+ITDcGc8N
zanD;b(c3XazVw_0$$KqF*~iG`7-XrdF%B!fteMBMmk-X*2y;S~G5OXfeedr<D46HB
z69dUFz{8i+v;oi6w9-%&TCzdzLl})tI#PF!TiILqk!q*m+O|5Di$K=>c`)Et$WOv@
zAjID{<qIMwNQ;`wmD#*7k(?6@6n(825}{w<h5liHk>WjR7WM04;}YWasoLAo9BqF<
zfB};oPjOIJQ)xewFC=&IBtzL*3vJG_&+%whRnDf%xDM7K)DDiB<BX9;SGn&$t`QM3
z&$w&VoK>$f)qb`?QAdLU9&mI<T1~GKr&d!Ogs&!j+`3Wa48KN$M*kIM^eMHP@?@`y
z#Wtp1C(e;Iot~svZ5<41K&D=Tm*0DeGiH2|gQ9Le6qJGIaol<$E0yM$p8pY2UC5QK
zyM91V??j2SVUjYt0H>iwqWdqqnF_PuSDz+E)9PC>pPQ3@hh2k1&ZQ=S&`Mf8=1s99
zrtyQe;`k9;umvE1)s_U<7;dQu8!D|Ze@13ZI8zFkXHC-ET06qP7ns51El36=!iMO?
zq?kPCoT*EeSmWV|zmMu8G?i&0VgXs74EFT%Xt^Dr5ba$=@31NyLkSF2ZpiI@#TD$(
zuoE{h$Gce2+xK$LL#;=^FP@RWQAxOfTFSn_=Kur6?5clOKIYr}E3MUT(D=#h^wE9p
zB{&=9ELLahAR)l>n$r@FhV6A@lr8^47t0?({!%A8q0DjN!R(@HoLY_+w8+Sc1S<M*
zSw$UEGg~uGNd1mXy}C7OI0MiR+#eInram*Zvj7s=wu=rjzE}OzhtpOU?t;5P=NQ<%
zcrDWkC~<2B%|{OgX^iU~q044ou-QM46NB}!@jF%st`*l(Va)Gvbjw7SL6Lwb<bdD{
zVk&D7gO*wE{tFE3h?ulJ-eoJLAlm9;Z7W_GuJ!$fKh{w9J>0?0nrq0w2U?K%ui+om
zgu{in!bS5x@f01Uxh|m}H&+;Y=9q9D*66M9H%Ev|Wg&fzGJd5-=ed1$Sr6+06sRlV
z2+50G9&<fclxWab?Xi8f7Q>d4SWW<v5JEFZx^4}3zqrkR35wNvl03>WJY1%)``1(H
zE$lBI)S_n}yCaUMj=5KhALVtdq7O^Fk?EXxdP>dH_)3;j>F_XL_x;sBE~Ddd2DKIU
zqIo`Z@y!wMCh5B1>C+=#XqyG1mGGme^K#9^86jYmy0>6kkr~Poov;V!X>$=Cl_sBK
ziZ~6)nX^k(OgAAl>v!UHl8Gp*KeLC^I^2EL`7Ty~8UQm)xKhG8cvpzt_R|54r}7hC
zqx;)W-Y^O&PQ#0cHekc6q`tF=v~ryh@R2=;opsUDW3E#o_#;)f?GLp{rGT|mKOi@(
z6cLgz>?%rg@h;fNmm6h5LkJ3TI#osKg@L8U*HmE+0u)ipX1@8o?_9JF8^nPcI=)B9
zi!8cBeBmG<Y}3I&Y?_a@b1pSv1|!IJOEOLMyPw$s+MBRuQho?fy<IaXx_O&+%RADE
zu4CtsiP#Tr!KtV>?!!raJ;pnUWjhVbcX}cnBWHiV9&EXM-@J(wb;9uFCIxZKI|*mq
zy}~RurRp<M>w-PZ<5kUri0?ACB8|7}iLI3gAN5HNUh82V`r<ra<~lR=RW`BJkZJZT
z48c3Dp5m|L(>t>a?7c!n8q$2HEY9!PnVt!$3=Skg{#L3j79aO`vvBL}nfaHnKjB82
ztQ%x5kqN&rSIEcDKb0kXlnb5uXwYH&Q)?7d6#DzOt^bSCXO|ASjPV7nw}12@7uO<l
z+YgNA?GI{DK3z?8g*J+9yA#6efdulOt%ZGNTn>b>ZU96qy(1OQFuRwe7X0m4+@MXR
z|B;j^$En`1z@oIKrq|%ZHpx&18@`Gd%?O&WMoJNilzWSl_?Mv40)c58|56V{YTSlr
zMRcSXknU){RdRxz0Y`Ys&vAtNDs_LWyp7|hM83@kx-??OK`XUb_n#aOh26)da0$lz
z7#gKVG3n;gRc!KXGdBqLAiQldI9-aH%0Sn!=>Zume7J+kYGLLHK=eF@q<kl3JeYlm
z3X!NQ*{_JTahi}Eo*L9Gu#APy?}(1!w&YmkFtme2ZZuI%4;DX_QT?R|NQGwaiB4U>
zf9h!Sbgf*{g#&*Ftna=>|BbdNBRB0=&a+o6fn_-(@M94)udwpcr9pG5bOmK_dH)!#
zy3S|TcH{vGs)F!NA`Zv(Q^A)(Dcoxz8>dKpvLO;2fWP+ovRnB@=28|*i%{g9Ojp7a
zpaoxlf1WwJplnEy@Fhl7qf{92N}!xXZAI};X2tv{)1Hd$w8S<=q4^ZHCa8ojfCsSu
zs74Tt^fB=+ckl0wlSdo))hZK2j;<@zS0*2Fe6&g$NXMAt>KN4CM^hrAN%?GZ$ayX9
zaT-|n2a@HD*~*H(Y5r~<aDN1WP!<SROt5%G3bp%6$Q(cuid+wn0`vz}32|s7GU$TF
zbwA4bQLFZHa*+QjM*6P;c9#8q<Dk@nir7S1FCEOgZn5FOzANcN6=we@@EXsPO{eCs
z!%9B|5=1e)rgTk~R+!Cz5-D6!!OMdaJ|TG*pxE@QWSwquoL1a&Xg`O1Aai$w_zk>b
zI#MX^@R)m|lkh#}1pqsj$kV9JPRJ-v3)UozgX}|EN1?_+XV`IA?&roB0McpCMvtGz
zJ<4dDZ*9)Y#=2~1KU}pGv?sV$eE%syc6pv~`298W#zee(EZJ~h>scw^1v4pvyw?Rh
zLzG}mjpME>2vqBQDa!DIJ|lg%5*SkU04O0TVgfR}^DSE>wy0Xou^A}xU0m1?(lzc9
zWB>dXR{|AvqQ74S4H>X>elQyfqq4S-Vmuv4Dz@QeE<#%n*#~-5i@x0pHmvn=AFFX9
z^b2nwCSYi2Gw8q@BTCP?5?Yyq5xw&C4%$W$#TawoLMIxSc%!?*ozE|n25?V8G*<z2
z75ZqG?xU-PZ+)iu3x@qs+hbIC1xl`nBI}e`UerU=$y{)&^EpUydDnRB(bJjxd_9rG
z>K(&0*%&xotKC$kwpKN(!=Y4gHnP2ucN14>kAeC@`J&NDcZ^^N;V8aVJbF}WYvI7X
zGo+^$6<RfmT#*AMOz>((qpAHwCjs|^U-d)ZdKY;GN@*)*RG@e7ZWd_+*Y>P_bxjGV
zInx^1V*qz_(a+}q)VyDWVV9rww8<I&ewa=LzFj2w3b=kvgZ<-r;iRR>?vt&$<plp8
z7`VufKuRa}+odQH7slWi0cX%F>u%cV-IE%`99lk7flMpi5>fW){_?~>wDIU8)ZF_4
zTSiZz4m~=n&kpblI+YnSzL0AsiT@O;+nOWvTgyHUiOIQbHr(BRT~(Ps0XTsvqtzFe
ztVZspd!N^lh(y8+2tpL(sT^s7+F$*O#2B}?)kf9``v@6(>0>lQ*RF@+5Aa$Z0WSu%
zjW{6l@Y-C&`uUSgD3~uO3?#6B>gWd;=@+YbkzeOiHgwPCp*;LE$Z^7}C1w{xfm|2i
z+62eB`6N-4yS7Dp%i%S}v8KEcvI=O*si>3dk|a+IN2L(K<0+iy>-<&Hq>n{e!lCbr
zFcsou;vfPhr2tm1AKO+HhYi}#K$Pn)o7>xv#mjK0=hOcRj=4_z(U8Ioj4JusTU1rc
zmDd~rvl8`M8w^^y$$)phdm0u0S%Nwl%7X3DH}#cM1T=;0hX`%w7X_U{58p@w^d(ur
zOcW4y1I{KZP#r54iI07T41s#8N^)8hS9}55r|=e5iuJN^H}Z)a<eY<MFw$ZZjq7`V
zEE}jR<eQJIHv@P^IkFA_mc&<AR6Vu8c}l<r_eJk5?R;Mgw;L$L!5}vBppC~zLv>cf
zuFF&foc4_64VnTTddhz=i(F9Gpji8@tVH0*^M_0`_DXlBpwq2=XgG@7SU_Ip@Je7h
zxNj=^ifoZLF0OuC?SeN}U0o~m$<ud2oM|E5B=5JY#}spM`h^Qn;eB+E`OFt7lC4Y4
zSGfdDZTbZX03A)Qp!X$n!ic_~e!Ia92+${loR9%8fAH0Z3fH7;Ow6Zs6_rSJT#BHw
z=k;jHq+HuRM}t2od>Nd5(%S~Z7rvnxnA#9c<?z%-vq;|zsPrPhOrLmski6n;d&5dM
z@98?UJrz|%fkBWL^&c8a?(o_B-3$XF;DJ8RHfNw&(Ds%v&V@KTsr7D<#EL$wO%!gV
zt+X_<GIsq%(Qw8x^tRty4z>J?FC0m#V-bW54u>`(rR+5T{_3!Kz|Ix*`)9t943>Qd
zz$rYoAks@P3oX`d8+2Tvp8=nW>n<T#xm~6aV0YrKkXiWMT{2%pSpgA<6I%3{my4%?
zhURe^waby5l~$cYD53ojuw}chqdJv^;?CoxcC0DntRI>EixGY|&nD7)M}^h;V0ucQ
zsgJLm#pth8k66Mu%%?8hx{ts=JiBo8nyj3uU@;4ps|#q9qajY@L;N%d6H!$V5|3}3
z-`^AtIhekgw$8fMbrA*g1zVE)SU05kGnbu=xXh0$^*GF88ltJm&Pn&zY~oMNrB&e!
zrn}2w>s*xzles!P8Gb1Ci|tFK*1Lg#mhZS6ghS0n4w5nbAh)9;ZLxb7HRcZ>0?aDM
zDqEyeLb1KaG`kth;Y-inPi(m;Z#7_XcsTo|nz$0?9wxECEH126*|T>W<UdRaSY*qq
zp&@@wF$a)TJ&2_*(6@Z_93{n3tp#IffSIWLR<HQ^qv%mTmVhrG16IXny^dci>y`n!
zBqHjBHNp1l^1!dFJV+_#zgc{0no{~?;KJ=~uLDr&aOpBG6|D0Uc!ib-tpB5XmI{Jq
zRU;(h<M}%N&e3Oun21D%tEoZ9SYKE+jSN2J^>idy4=XnX3rdZJxDmM_)74SNWWPPz
zg%4M?cd0mq;nF|lIK;B^znd@r67b_l#yyglx!GVp7i?}@{aL9Y)6q_t!4v_%S4&A4
z50v#R^j1g!$B&GzGiX$aFL1?K@_ME^?r4m39ydi`|E7+F>r<($60`*eUM2v4w%5X;
z(EX&Z#FX^*29E}sle0*2PK&{ypWOvm5U<_M>P0${W$#JL9Mbxxh=8SVI@mA{LH~lY
z*cz?rVLL=@WSfD8@Vs}BA5Fn>P&ZE^ZS>0LX_@K{roIR1kc-H?yNGbJHD=h#X$Zr~
zN4jGw<*mK-T*1i@t7C|_vnv(HPpEyV3rAs)^Y#|3j9eIh<I|m@`M%#@qg{03VpW=8
zXB1f!jJy2qf)8NI?{=0QZ(c~rt6vQ7Ji$Rard|gvn|P2`f9A0u=<TwAT5nTeH(LJf
z^F%x5`PM=i*yTGE7(|jY9py+_L;?K0&^X$jl52C{E?VEXb++SQ0PltGJS}h10dsn-
zTZT$Uuj39A(t)<qHsH~0Q>s1Niz)Nr`H!|~`DIb<_e;pICNShF#|P0!*=x%(6bDhz
zq#Q!yX<N;-NI%2EeFN6a_TH<xrS1{RuZ1Ddb{B*e+WDAHkr21cX}e-M&>yep_at9;
zZZ?Pq$7T-+Vz4T}YM8>2bbmWlSAt+QsB%GqW^i1DrLQ7?l*~|pf72x|(MfkzPq-{#
zSvjrCRD)CBb~40%pnO{s<d%rQ7Y1pfTOx7vabx39Qo6|A92J-p40tBVrjPOQE<iop
z?O4^Xi}1$Ec_k*Gs(WK*y(r70eO=Gm-4?62T^bM+Mi|G)#EEMzay1ANhlX9i)K2Ma
z?Ef4Fvi0WRY|MORKa*NNwR`^0m|6dVjoBACah>&vkXB>+Ik<y<d?>Ugo=C_*KJe1^
z8irs6K+BHiSBH0b768QrkoEVvm{orolQojPMs+CmT?}54g9g^Eq<Y2R3(mChX?9=W
z1kwBHQXi<}<=$n=hkzIh(^qDYjWZVr{xDSYG#lnadB?%@>xf8JA03hZA`DjEKy=gt
zgz!Nih|?={o~5Khr7|>8_UTfo`65o6mhd?FUaxRJ#10^U*(loRWjk8rs?BUr6V~RS
zzn}`aeYT2g`>0hNZi3ltE1c4<;&PPZ$KbS2ZGGh)04&J6=ZUn34z0;OcO|QQy&mK|
zKgAo~qpwo0Ed6S1_sNYwrRSs;GJ~QxK}=>)w{GD+^ZU)Be*j?;Er<t7;5b=1GwSZ<
z7UGq2g|$qPBcI`nnSRPj&{J%AWj;tOapRt5*#3pa6N#zpA*SF7+v@XtUMPc&b(08d
zhf&uC3%`*pQ;;I2-}5x#cgI|tUf%`!eP(#WA2QS7VzSQd6Nf_EXWr2siGIssw;<nk
zBjh`}Bkj@xGya#lA^3sZtEEA1$yZecpoLzPI*5hwHwnJ@m*J;oyzJ=`_&}Tij?~kp
z@eEY|P=W)}Q{M4@YYH0xPDyWJSQnD9{7Gm{dkGH%@gfgl)`~YMG6NITdK4zp1~-m-
zZ4DgXiVBQxiCuw8k-7Tok_)gn+ssc5310c;W2=VRoW>q(GtUTnGU`2-RFZLCK@4Ea
zNe&!D%sB@@dx-bPxm1iND%YjguMsG43v-+kByljfWTqorlP!k}5=)6yY_(7LlMQin
z#THQIJh{|-ILCk4!A(n$(U%3k4dg3UD|JxA+|!y-#_Q!TjwOzT(mAC(jI+v=>a9Ks
zGIhrQ<V@n#67dU^zO510o?Hv@y|H?7Kj)aEcT(^T6+p(`ge-34ok+vz?mz^KmRL~2
z-HG9ifhRP)<cc9Zqs$@&yH4As4mBZc84K=WDi*MgitZ5%DMQIEvzy*W=|2noUFAIB
zofXq9KnvDngLy7(A!<Cj%jd<<4Re#1TmvZkI;5U`M&rsy&@OtAuUpB7EcXer_24Dx
zOi0;a!4vqP2tLF?VV$;X5~jcFoTYxp5L`pbNf)rDUMbmOph3ol8yfCFVO^q)8ug4E
z_=p2#`qNWWyI`?e;(TD{qw6`7ocLZ|1REy+FgIqr&)GI7SuDIcrORX}j!Tf+q!|*0
z!pQ%!P0VeRxS$*?fF7=HDNQ;9QoV!^;`61bImj@$aqfpYAFr3F0@L9o@oW8w!}O8Q
zftkk}-vhncQAi&I(!Zvu7yPR8?+s`JRXMY`+RU?jc$%*-Ky~UslYcYa4Z*r((}L#x
z8#_B$v~eA6uM?-GGf%&>EsB|=t4T3>QVA#o^ZDOFK-@BDsH#Z8^IYzmXu}7T-d)T-
zG5AV>c3BJsKq@13$3{M`9;odM<6PTvip(EPL`qr-g<p`G5@C`K&gN0z`fBY6R05%-
zR&<E1g1xq?hiZb6&J+r{?+6tJzr3*ZAZl9jUxe<IoTFdXRmqta0j_nmbIXcKl#*04
z{d}_NRZrx2horh#MaS7S&!K2qsM7Dp^MFFtPA7}1jK(2?_VukwhV@W;%kHzo>wqI`
zIMP$cDVKz>&Z`O#S=(~L7+N!;uOuA^B8bF(C)1{9&MdZSmn<>|eNk6!sZdQpyA1?W
zr=78@jai(=MKX=HTg$Y`Y8N064+~YqWbYad^ww78<hli^__#Ioq68{sa7;mV`PWx3
zVII8bTyp9&cfM=rs0yJZ;mg1Y7m|_VSaZ~hknxF(|D48G%N$s&?GtD--X@m4TpB>_
zu*G&GgSVPhaX~@n_VIF2hvfO|K#mGmh@Qza`-Rc7ijWyb$Y4h|NzN{$U1^q}aM`G7
zQWJc<+K&1H3(wLT`&JJm%agRcP`$yHr`Ew*dUuB9$m<*SsKX@Q3}WorZZX|XKX9Op
z#gqM|Lv<^);BlF4f|wRLGlMok<!qUFHT&QZI%xmYemO1GN`2?2#jZVBbCk;l9Se`2
zGngDPA^*RWp-)5m%L1EqS3>45rD`nX#<q;V2r7H<r>0HJH&{u+pEljK>aLaerq~2{
zGe7{NtAE%3M1k<L?qsaWOkXBZ;EWxxg@+Kg_0%VdBO2p=OXhF4k*Y~eQkfl0+pX4a
z9xwwP0eMv5G&uM^>FLQ<Gb^4k3}gQbL%=a1uCwo(QxArr#fgxy(p=t?(a=)zlTw__
z+{9rji4PQFJbP#dykdmuuJJO1Yp1Xt!$*EVsL6wYGiB7f@#*Y5ouq!?Gnr_sZ5!k3
zSO^zNVX*P~d;19i7dQvORTMzQXA|hV`H$mN^orhCOJ%#-Y$abbSE?YoN@52U^I=`A
z-canE5%WgZ(-`0)Md_HBJGe*hvrBO#w}^sxAhFnGW#qPJw@lCCIh|;sUBl4SaNPi^
zsVN5>1DDl785Z6XyXoUl;Uasp(qHdX!GtvtMkZPTdN(8Mx(0dPWE~|HB`dUFXJ1gP
z++`{C?dAq!$nP97rT(VS<UiXky6oa+y}i^1l_GY)oO6%ypK<_gfx?<OS>{`K+NhKg
zZ_R^Q0LSSM2LT@0mYwem>BKc`o>BYb{)Y;oMWYVBufxo_9M6RR2XKgrA}p%}jD{<I
zaE>b}i&Xmxn~rX!m>6k7F~GPj_D&>K8d2)AeGWj3=)Jq7SxM<>)33h<$?QLVsSCe1
zOb8#7%r_rbX#0{*qg*X!ktQ`~@C%0+zNyOtm58W}g2!*as@9I{K6mai19;0v+pE_&
zr1%VWDK_K%a0lWK0V!<N=HYc<z1~^^!1YmYp;NmW|M?m>GW81Wj?vU|56){camPX&
z(lKPFwH{9JvR<?gId&vi+X@YMR$b<FNP)HSh5;_8qV0n;Ks612+cd8`m!(LPvFkJ(
z&B|1d<J3>zikHbU@z8D1%N*ejPZq$FM0;7N(8LPnmtB4<PS$<AaRal?oOO?a*Vw-3
zxP7(ryx`(fuq`SLfYa#rJaY+=$eX_uxz<loDW+5Jaq%{lb7sifpPL6@j1Rp)U|M_d
zT|qDkJm!9zuwBwRrs{Yx4YI7o0?`I{k>!aaZTtEH=(QLsKpw9f?qZy{v{x1L4+o~1
zalxcS*7Ek;?MGYQr)Ob&^jJs0o;{Fb?I~lo9>yxyG^1RERDOt~S|x6hox3dD>XIqA
z3>S1nbfRQuFapw^4Q2}F>jG9`b~s<$zY6-)l0XBG(s3c<rFh9Wb&mGs5AO{`NBHj3
zgIEh0&~p+W$`c(Q0yX0?0Ra>Ci}Q_XAg@;{hcf55Wom;hT_smF4}XOtg+@;aOjze$
zrNqzmEZ&~%lrwVjlSYp2jECGHvmLmM(j7d?U8av~OG!KXoJz!I`vxFl5nOW8)P1T@
z&NG}oVP3i+(}`rh)^65QoG2)!ut9xeND%L!+)KWO=dr^P-bZ2yAq*>Piy-@8?)oE@
zL>qo-rP_!N%M~F&%+ydC<y*r5m|_iSp_nd?k#_C*j@$vQISr}v2xi^C(MPLMu8a4|
z?nRYvgiAUZr%5>E0a>$Ume&VT=DqHbp+`%lVNA?Rm*W(~3L9Lo02M_U7}9$OzIBbO
ziu_}%qt8WbOj6Ij&mkdh2cMFBc8?jRQA-<PGWS8}xx{X8p($9gn2^CSr`pQ*c)I?q
z%-UbUR}{VWx~#8aMYWwV0AK6eMpb)Sx7iBRp$LFmR4{2%;}IQVD700rg(xSrm9nX5
z=_S=hbF5PESm=?u%6K6*@GS8a)-KbsN%;LjfWLi<kRlS)9+w))xVbke@0Z_`iyuhd
zyg_>-U3{at-vSt*(7hI8KJI`)4?)n-$Sb<S76+$3EF=TAAyy>kt>0}9^G0G-LfIfc
ze^>PCclPF4la}=Xsv7-C*k_F>SHi|1P*;O)`QeAy42w?gKIOf=;yj~>G|8w=3-J#y
zS7Rh6amq_SP&;2gwJk&DNAb0P&nr`rx%bjq(+GKeDB8sMlxqNy8`<nd1dTI1g`ToB
zzt}{EIZ;Mte&0EiU?0a}4lew+yZe&6-UT?2rvWh|6!wR4lQ;lf4>gv`|DmWp6il_m
zOul|A^&L$+qLwA|>C0x*Nl7Cj`s2ixM`WFp{#_*>vR<@0$ub6<r9~97m6#Sw#Xcn-
z`Zv0#O{RZ~>!gr_bf=fd^~L+vweUlz?Gu=GL^r`GOFfz6*EZs=tz#Uni<MEI5dsEw
zusN)zG>mcup9QRx+*leLb-cV@>;(+1^X&YOIJ4vh(9dSBuAxo7Ae1rjFv2!?xXC^V
z=j@;{1)g3~&7nD{T^@>tk^UgbgFRp1s4%EiVETD8$e?PN_ON9ZUOt&i!J4JGNy~p*
zJ4fI&CB>Q~w5gvQj`^=fi>5a=Tn_v2*%qel7--GqErH(dVbUhg*@NfFYzp$R-VaF_
z_oGuV`<<ex{*zX*gw5I!DEvI8rp4yX?nk$%mtC-^1?kDUPF(C*XkU<nIj&jDA-S7J
zA1bU@f~v(UX5Z@y_L%%5F!7LAx>*wC$qP@({*&bQxbwUHNMD+zfBWBfMMUkyMnLZ;
z?2_ee^C{?D)f}w5Svh{V`6}5O)=MB+p8&`dg4E3)^E({+*-IZO5kT?I9I>EwFJ?SD
z#4WTwd^nH8T8?%W-{dx$tnseI;fG$#|M#qg&(ubOWWEwy2Q0ezks2sy-DmZTEYH$-
zgW=Uxy~zwPBs{tTsGM6LtWz$FD;7ijQjZQ_^}bskmL$Ilj*vsefiH0m_~9o)C9?%e
zs6-U)7!SAZImCJRGp)TWX`6r{R#L;Uox%e`;O7uaIaRM7Hq-jJIp7$pKY+dnwb}_F
ztP7#9<o_wy!+Q(nr3Ktxr9X#Z9I}`7;8WE<)p)TUJ?6&Hj)_f=n}8lD#-(%@K#Cry
zlzM=Q&oX}OYB#b($)^M|K#QKOVM`!L5KTnJsBS3ZrehLEXe<Uk>9@qHa5#5(F^at4
zRHRTHKP|QFF4^48$~QnVaRxJZJ*NcT+orsAUyA0Jt%62(Wsx);cfb89diet499Y}u
zkF|=cfj1jy7<YK0yqGS=dK?oYHTe%Y-K_WD-5sg70a;+kCG?)Pc$Qje0auDT7VGTm
z)VV)PPH?j*cFBuYX1HUq7q~-HZfzROsAhlqDyc~-BZq|z_RNmmB!aib=rz+6Mf?>p
z4}E4KdYX)L3BEypGU^W0&x8-XBo!Y}79yWNiB@4du=OxAk^kW{uDt7k6MuG7DKv}v
z(-p{0_8}ugE>r%VU}3e9<jYq}w%T*)9<-{F_=`5<Ds!sAJF#dWOTmBRF!OJdgCJ(C
zCN=Vl(pqF`<({hK`Y}aj2(8Pm)WW*_mV{!N`WM>x<m1Ci*o7p%(IGQ%<}<&O8>}yp
zarz86S*zeO=ZM9+im?>v8b1S9;B2-{1o}3yL1*!AJ~L;wWoWr_gKpix$d0_CuFCY_
zM^=ce4^Z<zWsN}WtIYwmBUfGUB0~UuNrnMTdqdah-+cu6#w-D^YNF~$Od^Bi4op6R
z#z?aRWs%OJ0?HL|ph)uUaP<)D=pjVhnQf~FI_hTC@lOF&&h${|yJ9MetX1TYe5C8d
zrMt)DSo_3Zy0z2MaQnLHhwZ&ma_Qz*y%&EmY)bH1aXGC+<W%9mvd5sN$?kD!$zGNc
zjGAzXv<D#QpSz3Vs_$>f%MZV7i?b>?j60f?qg4KD5E7r%ab@+1nob8tupqyXXx_?i
z&)|<Sncr~nmjsTKG8Mw@a47X-A=B|P(;6#46#-Zgl3vx|TkwheB77lKpxSfliKsFU
zBk`}0hf+L>ppnR4<qUFY8yn-c-Z-guC3_}1FJrAVryF=bvd=^p7$ZzBzzMJC#v#8P
zre3xMdHB7nA~2<F8BP_M@iX_E&Kf<u4Ea1%!_emlH+eOh1up)2CpmPE&q(1(@ipNq
z@7l)@a$_z0=T+Xa7FeL@VX1!MzHC2`I^O<LW>Khw$jLZo8NcIKj5IaY_@K$amAcu=
zv0b{QJU<}t?^q)Tpi9mpj%{02Dg*ILharY?Ye#qyRvPXS<nz4$GP%B{3tiPOT5z-r
z*}BO3-qT`<2B76e2QRwEr_ll29&4~|VdIm9J20GHH}G}QMIs!~mM*zzQ*SB2jV<H|
zM87ajC9}}8;>Ve71WNWGY7VN4rYh(=Aa%HFMusspYjWNe)Gv9BXPtvb$rF~uuJ^dj
za<sH>fH%%cI{dn#m;S@41vYJ{2P}+IW`QRbb%TLIdywlCdO1kPv<8ucb}L(&B$w&!
zKpc>idF%8TM>?7t1iGZ3eZ|DXU3HrBNKnp>Pjth>pEY#bZ|+N>ZUsH&8KhHB@fMsn
z%8WPstmQSn>*>1IaPEsB_N__>C&@ZZ2s4q0W@|=w+LH*fs^iVFZaxf&Y9bp2CW315
zx)~Hw<fvA#t@imVDw5nfq|^G0+J@|jzs!DHqs;ew{-=R%abH20!PZ?9q1CfPpJuFf
z-b@ERwPWNh$MJ~KT3!!;%d{n%cjIKpStE_8?DU@cOGBq19qn2T8w?^&%6u7MQaM>c
zDWj8{jdBVnx1xTW!V6&$K~px)lZ{Z%#cX_@j?l#l^{k4}*?V<&(8|8xv|&f%QNlD2
zum)p52qFfWVD5DOy%tN16^SPr61jvXT2Qg35f^IUe-{G3yNquSq4TS=1W8Z_88Jwv
zQMM5tQ|q9vL3eD6r|OxprfjQ{8iyMZaXpXDjPERxDywR%0bpv%wO<)Y&J({x`Z?kl
zk@fEc%7SLTWjBsWO;LoC=5gz#&%;>yVHD8hrx-X>5(@wiQBO=uT?WLz7RjzNmHkv4
z42NVIT@@ovv@XR!ZLk2hCv1sb>5#4%V*}`ghXsesS@WU7J8K?nbZ$ywyLI1l=6xdI
zJ+$P$ii8q;Q~IX&N~N8(-D+AQlIB(48*SCnY~8|cU@1uZAQaf2UXRt-K?DE;_9R|(
z|G554I-!k|W)H9CgiSeDsuCBOR4=v0Jjt~bL4PiZ<lPA`nnN5KlxD=?#Qxi+z;8j+
zNg?w?&ZrU#$DkAsrWiLodU1Dd1MUj1CZIYRtcw2($?$|6Dh!SqaSvkNm!TH&H6^vf
zsy)+dl<zFFm`AI#3q<k*h@dx)>Kty!pA^a2%O^2emy1d|O91)3Q>x&!Zz%~`8T}Ht
z(Y6dJ7r;9Bhd97&j*yRLyjc`x_RVne>xGhL#htC+C8v@b3OO-+*qR))6$R+Dg(tcW
zIZG^Ju>=_|yr2Vo-AF}kX=8k96H}!5UjKZ)uI=H2LpotNkveTd%jQes!_F{3v<MQ6
zlgy4W`Bf^juv1>B?{b~`(e@XhNTXzs>Q-h8Z0Ayu(P}&Hm;S=qeIo8tgw`Ug6w&Ar
zgG@Mc2NOR72Vj4hpc0*pF+g|?l|0oerFoQA%473!m^es=;_8XrRT1tP0^22gWd3~1
zAvZ^=DUy6^pgf{l%mu#Vt)8MaCeZaV*9w)a<yFCmXP(Lhwxru_*GiI)bBsGh%_K|w
zPFFT$KZXAG|Me#?d?~Ia%oH=%q=4BoZ^|$0=Jq368;zk6H_L53FHhPZLMls_1ZJ`N
z!?L&g(T)@;lE+NOk~NVUD#JPN`<h-b<H-+QKQQ!?z!oTaC%`aR*isU$b~l1l!<1;p
zWp;4j%d(KEl}$ulLf6)7USV1lK$`fY0+SXFvy?T<3gW5hKNcU2bL!N!bJ%7^P~s;a
zFu-{McCh8T_d{h3(!LQVy6>KYy|*vQoHw~p3@TH=Xy}7v44PrW)bP1ky|Zo)(vPJ0
z^niG|s3@N?dyI~6ulw2vq$(KQCZZr{G(1kAH~5NttDOOT93W}2YC{~W|DKCh`QKXH
z!g0$<V7y&s>ZM8z%OXC@i3Y?j6-Q(2=a+3~7tZ@?i(IWZybnx1AmTf7BT>BD)m^Q`
zEJ6cA?UJ90J|Sxtum?;gtMAb?Wb6^-hr`0OgfA|EeMjML^S<@AP0iP5A3G$L3p(XZ
zrQbO&(L=D*WCT0q0w9DB+w8VwOuU<ql;>JmDB3v-qEGcrNy^K;NG7HPz_&95)0naV
zQr8)QuSIR=ij&0!MB;ha<119?y1f0Rz}1|#i|DPjtXxhms$YAlvxT_E5G*e*n*}rI
z@`zI&a$xuw5-EseM`E>MNSHP2*V>uX^Rs{xh(1*_t08xN+q4l2^g`nIG>ZhLr=;ZT
z_G8JO-Tn*b)gVY5$7jBxc*ZR!8Vh{4?>YYm7Vv^M1=%e~N4jv*$)R_nHpk5B92VXe
z3g#O=9SD!On_2gFHbbGI6QNXjBEp61P#*l+kqBQGBCuhE$;tAl3J`v6R(BUH9-Y8!
zc?1<J-&lv!FB;^FUkq$_98po9>8RBGghr48pv!WKT)c&_*-m8P5Y6U>`4O&Cie<3+
zxGS$RiH%`5l#cz~cc<D2H^Nz#9}v<FM%0!%U>_>@1lNMiLtMS;FL?s@Mv>!K&a6U|
zHkwSgA8A`H)XW=hdZaB}k{!AL6ugK6|204oX=Ta+J{_+4^f^z~Ho@drrVm)XP~w~~
z%T|a^W9^`X<zgijFgjOcDBquhWpt7S|IFvl#Txu)bsxQ_YFu?D-4lXV(;%LhrsoD2
z3oH5&vWsg<w5!k$)$n%dh?efZojvX__6G;j(Y$POT8K9tM8-gWgO5Ybo77jJF}DjR
z=g~-vwYUy^U^#Edl>R`oyN`2n#kT5hxY*%UW@k&QCUx1w_6A5}0~aTAyO;yp?KE8l
z>}4;ouh|u^wJF*8E96f@<q{`DnB641KWqOfSSQ9@L1f@Pk6aZbVeSHiI}Z$VP?s5K
z3^m`5q^dnZwWyMubNSDl(v=Ht2y%}#b;|h?V65P<r2RCF_`)6*0`Zbh4oW%Al_PU&
z#p%Lcbq4~Cf@mQK#w=wtvU2jbcSV#zKbh`_GW~l(?gr@P*zGYek*X7Xyt5CP9Ck3)
zXo<Xxer5W17`faIkL<m&z)#}tj{zLkAb|Xg9j#s|XarE-f`5&X`R6ew(+!<<5{6KZ
ziP-O)SOFiQ#wnsZ)=aauI2ruxN`VO|_Ify`x#@fiGpoM<uK2Of*`@FL!aa_C=@1ht
zT}!$-fHz%$XXI9@qu9Piq!989*s&{Zw<h>whv)cU=X~=Sust^EcF-Qj<8B;;D+MMB
z;iz`P)Vo$VmFMNh$3bq$@F>(Aw|q_jpD7M_gA<|2>zGr}hTMvYqY8crl?GXB_ifTh
zG1qS!>j90p*k!gVnUO#$asaxv9UdBLpX#LF7XS+As{JCogLDU~Tk+$arf%DC;z%7@
z!B*1V=ubRX$_RnmW(lvsFV&d(3!pH|R8=?o)&}cBZYB7NBt{W)GNj#fjR1FC&|u2t
zYWCA;kuL#H>e>0$Tz-t5b5#2Eh}0Qa7m2O84zaaw{&k&AS@Pu!*aQ63KOe6KZy<23
zu?&*cM+B7IaUg#q>AIk~&(dDGMpY6j{!V`H&O#F5&p~69b#e64;@0^O-=aU6(O6ff
zjh-eh6ib6IAY?gq#9x#;r|*ly>UkQ|bJ+k<1LH0_xzZ_b&a`%PqfTfE2zNljO0hge
zE;zF=(Mk85_xT=xOda+K?3+Eq`MaGh2{#>?i|uHurXMax7RpFT1YB8dz0SoYiZr{`
zuPC6q;lDL&SnmP6*QooXUp3&dSuGMonwF(~0wUO(gK<vMH=S_Ag8;yFJ$@oj2W8#6
zuK3MI-&dgTWr-<OCL!*;T^u9K;gvc+Nw5@mV$+fj<3oiW<TJxs?vMUJPy?PHIz@UT
zVFZ_zKD^XPF-87L5-r1_k!YW$%Ht~fqJx<U5>f;gScbgrxfzh3Z>cN`fvzeRB!cry
z?-+U6tG8~Z1b$L5WbJ$rrbd4ShYQW%jG<-M!>}W;HO2}443si&wx56CWK5dETH*mJ
ze-VN*!?1AR?Dy;2%F!Q-z|1MxF|}m<?RnjRM6ihcOQ@=;=$M7^q(@I%%}UumV0jHG
zdk;%zXwkfT-Q4F1e**xxc#rFyGIJJCh5}g^8=f?p{;Ay8`|DbCM1PbHf@v3^afN{2
zuwNyl^2-%Sw3Q-g%L}mXxfURKB#G)!k`x?K)ut$8nYB+b)rpFZ6_zR97`acY2C|f}
z%d0yqQ#`_Qj-Sf&S&;chg^6~z!(FDoZ%mZQvi;C`55)Y31G?g#G>jns-E3BZX(K&h
zrf2g5L`yvGpM|e1ZaYXKZxBi;w%`0c6`?@}fx>f9@z?DV@>=>>G#eQ&T|b}4lB-O9
z5buwcT-n$DJL#9^xw{K-ic(xr%<pv=U6lyO=y}ey@f=-dP_XJAaD?Oq#xyQ~2=UV2
z1J`2Zphq?)+|Zeh<mEh0y}|HvL#jApF`pe!u*llp&OMhwvfKBb@vG{o;!cPD3TQ5*
zdtRB|>-g}uW{=%4_$|(t<|TWMv|)J+jtRCuB1OT@i&!?_jvC(y6S?mgc@3Vs;NqaS
zS+GTQ*k4wYl2b()R`gj^dTr)`-QTITA*tySS`8#O^pJ5=X4A;`+9E9ugKrS=JBNnI
z>d5#>raApKY)rlq8?7DL05y^Zp+3O?!wTSgKFIb&1bB-?Oz>TSpV@X?{apLk(mUIN
z9$d>Ka+{$Egi12Wj{#N;P!QY&fQhhfU`v$PdFOt--x?bOAn-O(xHdOt@Or*fQL!nh
z43coLGqef56H>$OKq1YWsq0PqDe=$BTo7gKkZvXA7PFnkR*8Pw$Lm-z@U;%#7e)=s
zBeW7th2C=D#2k3mm>uIi<hzP$*#7CIoPQ@{w2P9N>SEmhUjzmUSdIb5nUP|=I|Ept
zd8=S>?HJ~;DYvGhS;>DR<1#q76*!Fz#FwjxK{?6lD_1<wf~80N*;5HYF*GW5_Tr|p
z^f(0l<urLTeWd%4oYLb*#hrYe6=3?;viO5~2R*a{#O5Z{RHxg!I0404W|KxtN!Vol
zc6t|JOrd0A3~_z`T?8o8097p9BwUeUtPqAtIF%!VsC94J3l9Ic?=_`XZs^Wt*iNnH
zFjb+)<y;)cGxTC@&RY>O3@#yzrEl;Z0y~v!Dd3^`5{<!!Gv!jT28qD`uVK|4L4#O5
z+q~nnCsiuc3fc#5COy#Awb_2)zSABo@j(W^;OE}dl$}sLXzgjz46z#sMc4Cem}?ax
zdAzfNQ=}6SQkS%-6lj4E$khZXQW!&vwliZ8z4O#D$`yk??rZ-t3IG(iBfetI>w}57
z@Ud#i*ba?PZ3ybFYoqAQtTJV?DJ-w$-d;dw$xy|?8mgX8CGk!=#P1~_<7+@P@o}~E
zhn2^Rv^(7b=2@S!H{dPEpHNC}kVzij61pqZP@Xo#)h+mHC`H1spwW_NYXiTsyxTv$
z28xZGi$sWjM!ErbXigB(j&shpfCcPq*MWUD<pYe7M7ZdPRx`M__$^BrHli@RoBq#{
zRYDtjF2Z;$;ET&k^O97#*6Ph=jpn`g`5qYR<-`riBYQ13n^C`7z4dv%I+#Q{p*5{E
z{G~3o&M^_{)CGHXtCM>PrwRc8IY7q0J>4fpoL8qOp7L@7(@O&{(*k$n*e=Ni7zrj<
z&@0)>2*+hTl<aP~GaALL#d3Q_!!z<DR-2=Ucp^8|JL&>z6YY(^05T1H5ReEura=PR
z=hj)&vq3;vOBl;~EyW3!!n9O_t(Y-|M0<A88EDr4u7B`fCM99pE{A8898?$n(2iVY
zbQ4U>i+|hjrdtsAD99jU2{QGcqre9<v=qz|LbC9H$ALMb{@LVeia3O04lVgqS6!Sc
z5MA0UzY4|8mf3W=!3gt(^kUpLurtZv@X2ofA&Q>C4bl>T{k%KBg5aqD6|C{aB^l6i
zowZnTVPmOT(=wq{V{#Dyx+$RYH7s|jt>K)?Ft)#H?D2x}$>*A%hK)+rmW~tXOvG6p
zu_>~Xem4>$R4c@(PL^aLXT;ujYGA6;4GbtC8(fFaNwFDyL!J#kU<81n!aQac(hn4s
zQ%ZIw7al3cfg7l^*xDSLljW`lkM&gnWZ>IPy{qpq<X>@`t~-ENbTYXu4-7KG3?evi
zAv724hdqefIgIvLlQ%Tmj?K5c_o0Pl(bf6t{Y+DQA2E&!??JWLXnv1=LoAVW5TJ9j
z`W*Tu-chY(UK1e33(x)~!aD3Kyb#M5j8qyfi%QUU#6ohdOBJ*lYWad9VE~>awI+``
zoe0iZBMEJDFbmHE7y%pOrqAGotD`h9IhgZ|jgw@PiJtdxmh|o81i<|NIT<#qs6qwl
z4gW8$@lznX+o4_Z;dUqLn^!XcNlFyAB`mg;@p&lOtM9!jw5}$cUP33;Gm}y@iY0qy
z3A#1q@(g`Me45ol6X_<jTC(>`w-*fJLj!a9vHG)&Tg36jG|yY=MB*=d2B2g52Uew^
z^98o2v%Ehc8b<N{K44hVx^{&jL-1LzG2rwvwCIdw_f=bWBJ%%I&Uf@)K~tJQA-{!+
zCb%a0#zp54WBCuh&i1I?ZGwe%`KBNDvaoMj8)aE@3F2YI-3SPsRr(r)Jlky018;=d
zyO(u}$U%nGq7MHdnRw;yQxqc8amk6WnTO0$6|%A+Iw>#W<F`5taJf~pKdYd485vh1
z(?!MHi-gr2<_R;6m6aFLLeOD@Ux#IP`sU&L1<bSW5$4KXac2)m8@bk6=b9@$_jEIC
z6(wiWZ{18LcJQO%7;M6MXjO{}hF>OJ8v8bmw(%j3!=Dc&n8tp*9-{Xi9Bq6XZ@6Xh
z_4MG|aLkS;msTuRE~>I^#-^+oNyxXXhMWc$2*1fKnm^M_k(<r2jgA!^NCE6Zex=}x
z|4>bqfpp#(e0qeZ#F7p~>ls7F+o^~z*0Z?115yvT*Y3Q--%cbSX-WG1R+7R-?*Ji_
zdcr|-fd!YP>SPSTx|VS5iF~m%MF30=KJFDOk4iVgr=x>4mn?OQ;iM#dHj5Ke{$U>p
zVxHK3PfcH#FXUSsXa6LX4A@ez(mqwD%`f1*_grF`Z9jW7X?n%$0~EwMq!W|z<1t!k
z%vllU8`NF6OZw3S5FE&hZ6LBJ?!g=Zf8WE9@Rhj$OjT6R01zasZ*s@4D*VQ=44E@&
z#Y91;z0ba8#RosamM>P}WATSTmk3cH)h5ZNnx46UR2A!PQLVgNLHzBIaf}ifPH+Hj
zfuw)Xs2K?l|G(%_?^`X3URsw(bDf@LhT)EgC}D*gde_4`>?+kX$iI@m437-(1p8e_
z(Rjmbn0^vy?8<-_NaAykA(%iXoqd~97^Cets1MizII}!w^#h_QUsFqZKF&f-y;Xup
zw6XeWrb$aTI@P*kP*h!*!~<I?HP-C4f^r)cb_^Q8@}dz*A|0IAA+X!<pdRqH@;qOG
z8M&4>JdowhAE%#>Qv1DHS_))5gt>UQwq^ob$ILYwx9oeH01OCs)2wgJilp|m*ZIN6
z{6kh1e6ALrnW@Vhk`Utq%$P|yXVSci*2*@-$zj^mEQT9S>_Gf?8pOyIJ!i-_;joC?
zM!*teZ{wdFCnNf)c@^LU^0H#HfQ)h&V&x7-?YYet9f|$L){5Fi^nt^<Mc6@!ls|9t
zoaUgyJcL{fMynBcWBELjX^m?pWq;*5pskTBNaAm5)qgX^G8O`NqKH5rJW9L?)SWyb
zd^GZ_5P;1wds-5Sf1-;OsGeg16>&Z*6f$>cM;5y`NqR}zyianqJaV}{lGmwZ81v$h
zIRMN};LUH9!PbF}I<|V`*pi>PS)OuRR=pTnWcG&r?Tc7Yd-Q(1+u%4bbZyd<lV{2M
z!Rorf15E3x(=xX>zO>pWx8E-}bpgawEa%u_;3>>JY>CmNfGpViHTK#Y#mz8~BEYTU
z-@r$C>lGG0sDiL!yIA;Fx8&_!qzE~mnBoz}e!YjTQ~a%=ghi|MWtPS6;nGU|uXg2t
z5n#ih5~DWa++CRNL7cgn_bHX52?b}Idw^V7iX8OopQHHTb?Qw{$!(@h!`6Ict$zys
z`^Hq0-V48|9j`-{9u5XqKJ}YbmkoLOoC}n1qXOv!N9#T5F(8iNM%90Btk5J=5La6`
zctjZ$CJEfDx_@7^974>aShg_%*T_UyMYOl2MD-^9^z}wV@9&?8b_ifgemYx0nfeEw
zp$PTw$RH$FwU@Ic=NsWg0af)%|8Pn<IYQ{Vpo|oZhYjK1^?>okWM^VRYQ3)Djw`n*
zDw&(t_m_z_B%G<RJ~`GHNz9WUXvq(=5|BwirnSI7ZES|pS^yXI{R<5v0fm3IVsUYL
z4}as~lo%6xk7%$Kves!5Yl$IMS^~Fro5))1?&a}uZD6_wD4({Qz{Q<3lu$i{lXtyy
zW$L&J_63se%caK<CS;Xnv+P&o4Nn4P4yB_b5JjRisOp$Ogi(wzHteg(sNUY=_^Aa4
zX;6)p9j&(4%Jic!=zaGwUA!O8MA$t9>)m;v4q)uuMI1qWS78>M&d?}oj2yf6>|Z3T
z%YW`iNK}DgiHE4=$Xu^Y<VvdUyM`~G^oHZ?;AD+8uSL0_K{F~nnG3kz^7qf5Fx@fH
zV_<Wjj_4NSD~!#HyP(8M_{9stx7^UL+W3(O)Zl&oS_`jm^jv*0E9eLB=B1|`X@0Ws
zkB%@{Y-M_e=^{M)-KaLl%B0euo+7oU|1*v{>(LQ&@L5P3#d^o9vFZKvCs2$g>_E`{
z=n{Bn&edi+uts*QS+IzOqO|9;0#(+N!BiBgh#VBiJ70IOBA7I!1}Y<tXFJ4GfZgR7
zB<$5|+({{0Ky~3yj?Fiuf1{#Fy!Yw^_Iey+^u7RfH+Pr2EP0bxKjRRwkPWR!n{czv
zG}`@%^^+g-V>#*SG;JI<Ww6rBhaj~neGZCf$2+g|yE5CQ55re#8a))i$-+PDW@&ET
zKn6{WPKjAs@*);??MeIL!BTf-EKSwe^4JR(A={gUmS93sSdNR^rwjw1XmsP764A}6
zT5CpaHU$wK7>RJvd+le0gC6qMiyTqmei7h9ChfcK4J?pK@r-pDRamzHRSWPxh>6`q
zG|n9_Xa|0j)lB-L;_OY>Kt=HF5227KCjDSiM-ZR14p`EYd)$GGTI|k7ck@;A>ut-m
zE`}r?#eb*;bfJhNfy;>yf?bEZiGf7kvb!9}y+AQPsxpOMsu;A5t5i-gHnuS0h5aa!
zu5I()qF$;y-B)1BFSs*&gf3<UKubU|9Xh01#;{9Tn2HT1p|6=x6>qvHq*aHAu6xV7
zn?OD!j_aa5<@k_GB<b|VFX*+C1j@^?XN8hELl!a;H>a?yfRWKVL3ZtbB>Wp<OZtZL
z#x!w`51#m`Np+h$wp2w+{RxaEW?$}FA}Z0GtUuu-H6~_Cs9OweL12blsnTcqbE_8H
zt>0E^PN)Yobk*(R9Eqlkf??($b4zfz#dO$=+oP{sXVxE{5)mu|ns}+%8E=<1M%-&F
zvJ!ql84#%j=RossQ1HB@Apb=#8}P2Tz9p{;BUw~$?$tP_@GrkEX&srv7lot2oJ?2;
z7BSpC5MY>1d>6>S8_KBp5MAv{jZ((nZai&z`p(87qzZm1#MT{UCRcU+;dZ})oPrB{
z^+afKc>d39Nzuzg)X!V7D0gswkzzNY0%=$+^<<MnCzPi~MU?Q^vJo$mzNRN*1nEPI
z;|NR-1Kc5#wkI#<SPbx#HRLO+XxhA%lp<%IXxyuK|Ht1<OAn1T?DkhLgd_xE87?Uf
zx9e2X@KwIz`Y?mcb3<9*n~AYy38Lx_E0A@b)6{#gt-+yJ_RuCMnUseAVcF+L;dSn6
zU9hf%Z^hp`3pCnDX-J7W2`B%1{=7w34zSX-5qZ0-JV^oP<q4{yI!LB|0!wy*R2+ED
z?r<TF^QS!;E~Wsbn0HqSn)fi%9YZ>aagmjY%cdO}qzLCWkZu|O42BQB1!hSO>xfx6
zlv~TD0@#WiNa#PhU@l0(f7b$u_xQ2QXjntP@FG9|mH6<h&>3e<#*@yNu}K$}Qtlz~
zNL$>^H_**-jS4Xt8yBr##7K*|-WR?p=DnDL+Vcv*ybSN0RnBYq*>gi^g%38c+ZVNc
zSI3h;0`t<30VerDrpC6j;uh9I_F%~{3v>xf3fx5<N3P7kOUFOwb-G&kNsn;XEWf5N
zFONI68K`0sc7;!S%==IVO&z`h$PGKM>lypGDybNW-Z7XJ=4FAZ_tX~sA_)({ceFLx
z^2vYtN6Lc!0{@zxIiwqd`Q@wn7=|!y6HbIYmV43c-89@_ad9!<b8zk>)9!~F=#qPB
zKca6u1~2gj^sk>j@S6uj(_P_y@8K*LnlY!tKE#u$eIx_<r$W|h^vIJGjXClNg<F#Q
zdxs;<&k0{5qrE)Vfy7Iv7oo4e;quxtSpj#pqL&e^FR@|Zx8vR5;<#sdb*oORAqTDQ
zIIT39pJxjdWnv}o7v^pVIE|#QgL+d4Zk^BZa6cF{MLALn*Vdp;{F7abqQ*(+O*;2o
z;LkQm3eo{gP}VL>SX?#N+jtg+LG>K&j0mH8ewamJRE#~-5XjG_tU?_9wGfu<C9Zrf
z!>6YPZ9ecaLsioe8JwM(aX_>1Ek>gg>LZ>QZ8Y>rSucl>#JoK5e)Qpt9S38_Bv$0r
zE7S4}UppN_Z(a>xfe^hKy1StJFAv94kg@6ErPs!Ulcmv!Ss<Pfpj`M^#LPQ8I5sb^
z2}Ji0PBa$IPzh9)j4_r4D&cDLYXNL{v(a*F?7a+RN)3Q=&m61mB?a|E$M5HbIWIla
z8C~K^27Zt_%JUo2e#8G~ooUFhBQP!XmW0xLEEweomPT^SW2hXi7ePCP&X?Gty9Htu
zj3bnjrW?1s*4fdoQ(@pcF3R4R^MVC7f=eignmMok{2>3}gZk`rk&j&USfOruHk9O$
zfWbahi4Pq0g;08bkznCyi%&%(uap<t?XH!Y86yC93HxYNz6mH+b|3Vs_1CdGfI1cn
zzM7--&eci?$E+8Yf~mjCS6~;yh59rRJmG2y^@uFn6Ws1nR~gtsW=l2K1*Mln!I9oV
zeI?NhD{WblCM`u4TA<R-E^AY@t$AbFh+(b#+Xx<TAy#RHAySX{cyBl4@e*ORKTY5J
z#If`Z`0!Fbb4`dc_A4#DmX#}RL1UYync<^mKZ7OqcMr_v8z|13^y$ia%NU1yNZvu(
zHYU0f`IBf!5W$bMtESwjO_krp8T4d}JDaJ4^A7QqjQTVJ3>vEAZS`lXjiYb@(uqtr
zW{lFA7{M~xVK)u5h~yLA)mdqwC4yz$dvPy_F=XR1ycQTUhUqHN`!Qd<k<0Im<bUZ&
zK&80__@+fa(!l6#Z5pdQ0GlEVlw6;Ho8K9p)^!IHqyH};&#j;RE0TLVE2FW4iCCv+
ze-ri(42?yD?YOZ8^eN)1Ug&0IWhk}Q7m?G&&$WTg;{%MbGA}2yG-a7mceBE(Sgz5m
zm$T~s1mwycP2hcHb4oN62-Am2*+D~_gO;*q_-}pVU+_!@ul1A(?2F7H%O5NpNK-#H
zw-fGpl|MeaURA&G5bUztZJ>$tLW7_j6_8V8HN3-lj*e=+oAogeqU0&n$vwoBY@JYD
zSupSA60jF8MbxQbc!Zy+VCf_%Ur0<ej=tZhh^yjFm6H~ZrZJl9^zm!_S4+Tz6~FCz
z=rr_(2w<gVvP!c?dF1>Mfie&r(HhM$<Q{f^$M+YHs|LX!yv;%4w}@exhOD$^mMYWM
zB?w^JR0L7lyL?NHqG<Rw?84|?4My+n$z+JJLWR_tV$!_l+k6`O#Ix5fTLflVz^!4V
zCm8&b>-HC6I2r;eD!$5ICL80;MMa}}wvjr>h5MR**Xtkio!wUzOEjJH4FLq=CA7*V
zFIv(Ccu^Wd-uQ1l>0|;|r-_dNe54(tD5aJmrtkL$;c-mCS0lq(<5QcYK6k!MJgnT{
z*VV7Q_3lB)h{GSlwd#X84kvWjLk6C!d7AVMPgW-4-p*<b>l(xfUku~)4p5rlht+m6
z6qb2O;SN4-RZmy&00e&KpSLEm>w#0ec@4!B9y(?At9j9KAAs1`&(@s`AaQ0w=dM{z
znFUl=zcuA(EuL_RfD;j9eS9DdRCU#<i&xGu-{>cwMN7W+w3<?EhZ_mRKL9wiIvYp|
ztu}Ni;C@Jj-A*Nq;w<k%o=G#{xx@b-8?g{RZ&dxP&kbV0QPwU&jmrJZ^6h4woHh*7
zu?}?we~w?k0)BQM&-Wh-CmNepMjQ>_k)~S|6Jk1n*cvG+JO+1--JqXBr43L3UYh>E
zf&rlFye<y}?0&Z|N?XLfns%@>{l2U)^W%*BCLy=K$iO`2>fASa7c<LXA-xXALUw2i
zY;gE4kLyUA(>t|mjs`Y)wM#!74p!s487u$khp;a{X@vA%FeK=i`J8VdDkznq)2uT!
zKg;|?e49gDIF(aSuWBJO>kDzee*$c-E5<v9MHEB+pD+Ie33~I#f{@AZ4UYSy_6%8d
zDFMfXT)og*eism^Aei)(y{@-Md7d5RGDK{CS^v?EtxBUe`nl|6d>oHclxDc$1Iyi)
zDJ7=;C-M`Lor6;l-$m|AXZwNK5frvtxX<1IetPt*9X$*!-Ni_OC!CU#o)DyENIClB
z)xnBCTi8~9`Hbbgw5w%((-FWV&aOO;y!=5<gr_pXP=yl0tHWay{o34hW{y1|$sw;l
zV8P2*-chPdTJQVN5(_vU!o@t+jNz=EZwXlndsc*dRvIFIaXU87M3_pXRO&4;>aCY!
z9k1VV1TZSQ9jQ(2*p*G;Y13$me0yS=<-t_VfOakAta1A44_i;FD|)0mklKC=W(%|p
zF$i6Tj4<^GsA^e&Awk%O!zIn63Kesz`B`NXgNw=kXiAj$-O)lB_J?OZ->^ahZ&ixC
z_R690^66-!E06`~RKeq#5}x6-gzSuPK|e7YHZbP+P9tTe!ExHB$HYSv#>xCl3&f<X
z4RKh!ao(_Q3$Qb<LR0Vu4&*<A{a=<7iZRVQ`ZF>dOKPh87m~Nj*7M~Fi`TIVN7;Sz
z5H9guO1)qI%>0cHm&7Ma`dN=2*hB2rWv>CH(~5>=MJ#soJKrck5J84>F18j7U_%w^
zF;3xLd>vqL!fJCs!q5(G)#fb|>hSb;>Z|ek+Yc}E(vjNApxAnq)4*1-_tZNJ>yyON
zbG|UVjv_Y9R{aIf+6izldKs_Lj?XdJ3fZN*&xKhLbu*M^5(A~r@o+bQoUdXn;&tM>
zz;paU77ndlQ-3vG!Q6!g^<AaISedYDy?TW;JyPNr-to0NKZ8Y+3A7F80@!_pVq-vG
zohQG8{IfdzG+`XhekQKjIxsUA85Un#tfi3>=NeGuIfPheT|3SM?)JspEft)fmreCM
zpI}v|JCx{*HVF==i_nayBoupq5p4e;e{1aO!Y4M#OIEAsI+1z8x&*biY5Hjob2ps=
zfkP3)O00HHqxXj^6kM|kl$tAuzb*I{S$!R6zVyryD}c}?w$%&@%{8yJoTL0x$tw)e
zF&e%-K9&-{e$v5h{<PmE^OkZAz!TSmLag=k{$<?g6;2-Z-Jl|lez0pw3n>N?;#U5{
zBKZl1@ESL`Faas`=X%B04i@k{DPftQVR7QDWjJ?YJx4ktdVSl)r%=0c8rEGcbzfU#
zMtN)9n~O99F##^~ty5dk`en3l*QQJ6L~3i2xJ)F_A+aZm(?T0pmDTMU-hP)o@^8Id
z6x0|t5Siy;@N2G_(S>7mdkLB(tq~>3X6JR#u?}4IWycV;NW-w(Xtm&Oq|SNjN=qsK
zlj(a1Wv48lbG|L2c=l^j@cqAjO}yth;w~?t^j2Pt5oj8vs7Kd`gx9IPB9A>E;W_6x
z?ZG^Bye&XzN{2Y-QRR6Ut-aZZOnL%ZI~>Z@PXUgkYQfZyAr`BwO%{s|8Mhq88yV?6
z350^3VS@f;nk3i9#-aw#V6>Opsf=O^-4EwdFQArNy;@m5rq~_mP_bBe;-CA?fdS!t
zx8rMo=CGL{7aN9WjR$ZA1t~}cwkMUx@|AuwJypA{gL{d)^(`+XaH8~5aHoLfow#j0
zU*cN-`lw{H$g;OqHsl+Tbjo?lc5{!ThycC{jNont;=|Yg2!8rMV;QmN_VvG8R6)w7
zrqZjY=V3$Fd*eMsYV}FVbdo3!_;~r%JSCL##gDmKL_usfb@c9AVYJlV15v?i++_3%
zUec<Nt8KWTS5tPNuwes~(a*o*?QOkqDpDB8rHdCqkrA1#24$0%hNF)v;U3`V0K=au
zfAraT`@tZCIJ7#~E@A8ukLREaEdE7saUW8KbyJau{^hfQ;=VH<jQUHhJ<Lsy<P=Qr
zj4c5lQ^vw0Ng8r@jaM5utu}&}-h<m4#;g_c-EAbM7nQWB^3%R1o{y~B4K%2;U!M$d
z%b&j|zWonIDhJ-^%vI#CsAE)}eW#{p&Bn#*V+sDzN1Iq~0xiMG+nyOHJc9;poh+TA
zX}>`RwSz;kqDd#!s7zGhi}yO!WxCpHl#SF|wD!VCz>5H(eLAaJl`4}3p7VrD6nuRQ
z9{p9IrvQO$rJ)e2FX#`sG-iJ3ny3<K8?D;@w{$AHwCYBd!_+a-Pk$2k%)D~w-#nEt
z9fY+umbG(q^=`hGK)0M9q`L+Q7tpPyXadFe7fz^R*!cJYL)bcrnM<Vut%9jJe#0cs
zY1u**oQ|!)GR+~u;#kSvs$`g{5{0->yjpwo)`!K&duG%09d3-ClVWaQ4kN!x`psME
z9r>9F8H6dJ;9cewUZ>c3u)$c${o~}%@!y1ONGgX*3?J+EH*hEK5iZZ>fTXUuS=Z!?
z5z2i@2u?!Vst_%wKDAWKFfwzM0Z~rZ<PSp;zU5wE;^u~5`XLoTpaZ=^cY3uV!Omj~
z@1D#On(R_d_7lb))^_WymG-#voy<I)-7~uWXUkgfQ$zt0R(LWb<d41<7jU5k+`rqo
z1jo(b+tW6Fgx=kzu5FZ|JdH29;Cz)4009^MV<sZfaZ9Z1&qq?4rVap)6>Z3f=B=FV
zfdX+w^|i#Tlk;K3ZQ8Wy4b6M5A7_@@5@FCWAe4_D<und0Z;VPl!euLIh}^Ma{(-4L
ztq^!t#}*aU$sMe@U}@U8@qvR>f0D^|`@6pTvoLHbSs_Ly{Gc41MxSnj-S|MOdW_?M
z&c3@M@Emr7qyCjl%W@-U+f1<$JdG@kitj$>w~wxR{LSY_tP`}c!>i>>mNqh-A??CY
zOLr1Lf)Z31uiP!|;RTHoFb!~Eq%I6%6YHU`7>;+P?We@yO0~wtm0f(>lQ`q+D@a*?
z?$vrA$qpO~oro=)#mZVQ+L{<&$q_8j0EP6^%t(RQr3lh1QD{Di@ONN4T<WwL>Nx`_
ziHU}dxFovBsAg!YTj@Jg1b3O`eBgUJyh}+FHZQx|w>=1IV7(^i&sqt7kM!M;uUkof
zh})#;So#&3s%<zJ?0sND?n9v)_wZGgY{6%w9<o#9L~Sz4%)GnO1!DJw7eI*swg&Q2
zLCn2kUKQfJIk|yN3x9cw6C4BaYmm1<Rt_O}g-#EPK9e+IW*mu9Hl{gJupW?dV!9re
zNnh@z_t^q;fW$}Bm$WY{s$ftxSIOL$il{L^!saU!xSw4$$n?yJ0K`)QGv-}4G$BgE
z`31CNoP0Fl1&K+sz~14K@8dKR1kax$B$^~JZ0~C{G5!tuuoh2H0xyGxiz=^%VON~x
zSB?2=CCOqae3T)kyDZb8pGVh=!53t^cq&f90UvT%qD%u49+pjE%;<T`k0Yx1ePmn;
z3vU5mi2`u3p5}15HQmCS_9xF7=#nO~b%SeHY1ZI8c&}yA-(D#zEQ8K$(7C^=Ln{k-
z8=R#5wQr<oAtqf&8A`r`ga9pj<Ni}!mH+#2#<WMv`Qs7u(`0F7VaZpXoCl%O^uX!n
zq`kjI)0CCm=ZMc?Rlp&fC=j^0y06Qa#FYW*JoIX^_46Fvng>mVylUdG^8^x<&mY(F
zW|dx8zT07Ar$?2U5<aUKo7{>IZVpck!GDqxU0npid|>G=i*>VkkcRRee^`F?S_x<Q
z9y!j|+(i&bdDb=o2MKbkjfyAq5WtLqm+)2e42KsS?A0Wc%GiL0sN7kHWi(9?jplD-
zlMOdY6!rKV5R!|97DlAh#QsQOSZZHX)j(2}n?L4&KsR+Poei{8iy!!JZ!N7b4*tGd
z$3F-V4&tIccR+L88YoAqRMhC$a_>k=vY-~Wk1W-#H$IMVp<2qGgu_jsW8v$$J*3Rl
zRy9W!Jwx{?i;>l>OCbs2iCnsgZ}OhE&6~#+40AUbRvnJ^Wp);qundbg>;2dI!u?fm
zA#D8-MOEw~mi1u)8r7-U)axTzX#s3)L{S>2IS$RAFt`)Un{ZMg?APqbHQbWDfLA@0
zN_nDY$cN>gW$wW(r<?c#vnw&Ix~W)sp2}N-Pp{_pE1xcL(y%f#giM^h%B-YQL32X8
zysBX4s>2OoSrpU7EBt>4AYq5-+{g?Gavo71Tvm%qX5B+Xfy&6%@p;A)5U(1tVm(vX
zIuO^IMX~N+eNjVs*|!|x@+)aE>8VfI%PM4*F)YWt!kAby7(s&X&-q+aQ=(xu&udv~
zY*ykYw@r(_pKc*3K_RpR*hX1AZ;SO>-y&NijxGe=#ycB%|73GM+yVXhDXZf5mttoA
z-!2z6^FskT|E&GNa}gU&emGpH^Nym^29=(dS~`+U-1NgUujnx6bVRf}(L36Ttsue)
zWl_9q0SC-+<ziXSUB`vZftz(jyeaWH2TL}&VpOgSA~hE^>Ift(TRfOaqegEr*M&}t
zFT0x43C{O8I1lck)VBzkH8mGz!VEKwVXzlYe0)u}WC}x4yinXt7l%XN+8crVd{shY
z^26Q<?pR3%`?4Zg<DrmKSl2rH;CAEhTYl*QEi>bFAu(QbcE<B<96Mx}+qU^Vb>?$>
zI1V(zSM2#F-hpMyjS$$P8TP@JF8moeOK@=Ztl2fd&|8Q#gr&09R{KZ&oUD9=HhnyY
zskt3?H=zpDG>9>Uih49aA8-bchIK26E(Dp#hCFkV+r!>}3~l_GqI?%o<+opG*2QaL
zkWIiJeLdheN+Q%mS+^-JY!{XWp^U(o`{=f!{|ljC2(uixb3BVRCSOyrE!A`a0!T*K
z03t42W`L7LCS=;I0%k&)2WvX>&G{YfF>!S;;u4qtmJcSIU-E~~m5b}kys9TyPg>de
z$Ej87a)RqQ^iZgU_P+A6Vsc#J=RM+hh;{%hJ%sE^4x>x#C^#)pN?bWTG-zG0CTFZt
zQfs6b@K$hhul-fSIurkkM4r-yr};1<2T#ooQSEe*D=;Dd;iLR8Xs(>Wl0kLhpKAUo
z;1I3nOpI(NU<gt(>_{K3JTHyymxW6Tzzz=}Kbo7=yV-h-VAe1C*`_Q_)LSsyJ~v`_
z96RQ>=vr9aECuB$#Nh`j+|TdKTabl;;9#I+<U3$1wCTTh*4P?8P9U;Z`dhjqcF;QP
zrssmQ?81$c3I2mceH7|^#F2CP{nHY)u@lgB+`CDWnkGJeriomF^G?7O=`)GMi(Bh)
zhrdl0&gRNYt<`)I=gRpopG8rns4dd9>?pqaR3n7@5X87N-Z2hB(8L??LxU2Pkz3Jb
zk0o1L#QRGc_<lI~jR9=*oa|j?vp0(j|ET~Nl#=_@fT}q}-hMWi+7I_T$*pcjI>s6@
z;pK*(vu~#zYVIoe=Yxbk*4Pi+Rv+~HL=glSQ<Uv%vO6(6nAnu8pqYRhMPP#So+a-`
zadKrsvAY8K;{~(vqCKs-1nOhRafV<>+3>zKUTiB!mA3l*r(zKWg!!QThzi-vaWa)W
z^JXvk3O{@Whj<l|GVgR)(I0TKcMeR%nu?)?x2bgL#^T1ZYGFEf<wcXQhCTQMwT|rK
zTf~PoG4Rsp=|vN1zV&2L5(sW;hF(!qWTb^%)oU1?=@neTF)H~%$^Uiq#^Zw=kkL5o
z5BP{n=Pm(8#iI+X&l&=HB))*du_5&gs|XWCT!*{zw;cRj19{R>StNhnlUE6c8h080
z(sJ!*972`7uvuDjk^|*L1XW$a^zz7gvMTU5>Vk<t+RVJo=jrr<TXCoG?P&{6?xtC-
z9Lr|brQqaPsZOL>)=9BhX<8`}zx*WAT(ERlOk!Avi%yKBrKLg&f(9XPI_g2@AReNy
z&y#j`XrKxDhkUu6t^Ovu2C4dV1T6;Yg&w-o9)M;h*M=!a2=kBU{tOtUqsaw1QvGY)
zi%IF((lYeqjW~kT!GtMh4?C7t8{*9VVTdo2Nhw9m)q%u$m?SjzBW})OiW62dE_N99
zE?0N%%x$ie_d7wp2rYR9w?y=PGNH9x$tx&q<^y5Au6(fn9Nh*j@V!wj9czTe@vjYG
z+*{+pJ+i|gUrjvpT5a1?y2m(h8XU2CD>zG7aFXk^<fGYIRe}i2>RBE`=35Iz?$8#s
zP5C@uigUJL7f1+Fh&7Rz{o}Uy4XTZobeBx3qCU)Dq|#_}<AzV#Hb{~f4|pS?8xX~?
zVLxKV$4w60dVnfBIfcJrm*!;ZJ<j4~%-7&41LTC`h>Djv-u2~1AFbwyXGA1aJ>wlZ
zWiZ^!?`F_)pTv?ZWDFBqH0##Ik(G*7+qnwIYUsJQMe-h~z@Z%&fyf=2^?SQ|B%A2A
zKKQ|4>q!s)_6byAjDd|k6!-d6HD#ISM&^v+^pbh-V-d&pZ@??oE-p^Yd)7D3o0dE2
z{GkSjHk9g6|JqP`RL$`y)@YbrhK1jDnPmrqP4aGAniu0CqB9)`-v(jTc*?&D;KZsQ
zBK>r#bOTu|M#-j}_D`Y1l}%G77^0GcPXMmA<(LJ9oe3&s33){WsaC{C%Rbr>Jy#S-
z;yjV(3cagV_c0s~DH<qw{Hw{#=>p)&@lgl}4G<|K^csm!0|`OIR=Y{;AIvJh`j5~!
z#Gu_Sme{HxziWCZS>nH6iUlgSDM(7pm?Cmi)=vBQ%D)BHz-Oz}Wo0<2Kahb7kKq`Q
zLcF1ycROgl<8Yy{rBN^ml7K_X+OyjUqQt}vLL8_!RrVgFEQCR_gq}oS{XRg(b@oE8
z0R+&?p*wY-2nze|gw722(uIVFEh;Z@QN=edZ090^veSJ&_l<MHF-+xiYCvVKm04?W
zN&l<eW4U{-6B2tJg%P>eIFn`lqnKM9!sv?jWHKeXFC0}|z-{&hpX9-|U(;C}Kwy6?
zeOCvb7rIQ}!%t7<;S_&!811#G)$^O)Ln^@cy4O6bc*7{mpW-Vgv{($k?iHP_Y#wYF
z4VW~B{d~(0)3o-n1~$yi?qx}h3fpQLx0#|pa$s6u5&QGo&#$0OwZA4<SF^W*^$cFg
zvm4`x?a^7Y5MQoWRO?p7z>Q8f!V?MJJTiAbVg(E^(1=TkK>lu8)U2`D-v>E~2o{_H
z3)L(Lqn1s2cD|V>>PR{|SzAewo}TqE+1iZ+(l=*_?G0y;K%7l%v;x=LZTcDI|Jm4G
zljPP+y5j)$)(xT&R`mMerO_AvYA;*U1(Jb{4?b!qs_^8|vGOqIaa0HF57@VzD_BI&
z0>b#ZsS}uyf7om8nm#T6spbxjkH9S78)fm(N?Q6=jnoThh$WS0@%=_{aBOtKJeeT4
zGE>cIM<1rrGz3z<L!D!l3y1@``M-2XVx}2{?DG<{Mu0y(_AOi;u<{CQuYK?~MkJ=0
z{~|i@X@H4hsETAzDKY+1&LJ>(VGobfU_diPSunH(Y&<_j+k+e)E8YCo{<gP4==w`H
z)?B)`oy4-x`DKI7B%>a5Ubr({1*FA%3EZDo%M!*V5&zq`4C``JAuyN=`pa1J=mS>G
z8d;m8Cyl5u^GCS^q+rYSN{AnGxWO!JOe{~dhrMuqG2ED4!!vT`;IZbKjor@K2Ao%J
z$y-H#xymTVF86zu@r@ATC<jy*O5r_@U&Jr5QmRyE#2FWCnIIcw8h+bZs8K%?3tHg7
zul0~kZ}MAW{WfnrM(Xt6!zu6lPHtvAWonVY^AjUfv|Wdsh1XXwc($l?jDu(ZPGkAZ
zv2nPPvYk@a?SscOpG0g+AixK|<*;&rE?DguBX>}v;qphRON>xEA?k2oYhy^BzNab$
zZxmj&=9kwk<*WntTjrS4XuMDh1XpBP6boaVt{Z)4_Ze!tgil}*E|4w`8jClVl0?ph
z5vGLsJLaQ4XRC^fiYGX}wm`dfW*j&%RLOA{)D$5F>pVN2UICbGcPWBi8(ZU(odRv*
z`ij%a$4$SW+kJbrQ+z1>qSmXnfR<@b?akHx;N%_3gS7>&I)e+i%l`%<O8uiFMr6DY
zhlyl7HPgW2bZvxbT@FAg_1y?Sp6WcS(Q4x?46WFwI?mfQaz>q;VS*BKFmfwFRhVL5
zbaXuYwV|~3#p(j(nX+OOQyygOFix3STV~Wh7}1Ci`=MC<s=M&>rJX1J%~goNWxPIr
z6Fy!QHv1z2xWNI}%)xDV`;2<KCp9g9Ciz4)Ja>*ck9&ntgQ8D<PV~rdb>dck_o;|<
zmx6hAE^U!nTu%wAD>53)==ugXb$?e1#t#Fc3$1yx;7n7fP!RAt)fPzx2PR&z?~lv;
zscQU8OYy7J9JPuL8Ll!B-Y$wJyu_u7VY_96Fx*ZbKB}?gu(-QqN<=ibe)Z-~3;44z
z3kIC}wq@3U%O7=;k$vPn<eGO%2|MDnSP6MOJ;EV%C_od&)gov9pfD`PbQlogWMSxt
z3lZpaNA>ckl_&rG70bNJkv7w^$cF<rlEwSX6be4w4O}t<_OEQHG=oy8PqWrqzFz1P
zU36^|#(*)gV)=~Sz}G5d><<=>O<rgh+my(^O+Di=vt%l);zj!#F4GO_DOc&lYFf)R
zALBy%=7#Y<pN^V+fpH!9L6O=@8b-}7GZs{B0cqO1QfBueFXqrGrg}xUH~@}>C=n0o
zN$G;*NWP8QzR4w<wc;oKJBfFTut(lZPngc{I_vtIhwbd^2D$I!pEpiYAUc{vBD67?
z(|ku79)W|3C4Cg$zCr!fqp?bPnfl8s_i$4mB~WQbueU>m9BX@a7-W8_SY%Dn$G^~~
zL9Qnmj6nHxK}C?L=@r)AJwu?#nn8Qbu!`Z{W^tKH)q4OQGdtws_>#W9LX(+f4gAV2
z20WfO9o!v>*e7z+0BKlxZhT3gBW-|^zj)8sVJ0FsNkgB2!{HSc+&tXDK*CYWA3Vru
zk0;7+?V~tAFn!MGWCA(Q*cy;Ja@2aRL|p3V@5#UgFbsB(EN5xmtcHWjixy}xb}7oL
zBTCxMD@5!V{R9jqk%bS1UAZ0CsOJRP`J^WW;0206q+i*VF?fi$ayM-TW+7rhTwBRv
zNL;a*`<xEKTb75!tZH0r*THUT$qy@)IN3u;+_Zdu@XynjZs@Oi(Wli>GDg+_PONYj
zeer`XuUomx#PH6-_-csbKz(0H!Ln{c7y9~Yc2u9{9l9eOK-ftSX9EwaCJK>-#jxsh
z;5=LV%K=_s4gShsUip*@HQ{hfcFNx#&D9FE2<fQ!bLP9Nl(w+m%Eyq<{Oca9#lTWh
zj^X$GR~rVW*HUGxd(2CE={2k3rFfOGv~jU|JiHHbK3Kc{=0N`kXy<RfdAvVf?ZPmt
z_bu1SnJTx~7GwzFO|6C#tIL_MKiZJJf{S)qMmV|@OfNf}sC7nb#wflQ!96&&Hk`1s
zzr*j6l1$y~64YB(BLHIv8%Ycbz<basjZX;MUIL)QjW0=tMp6X-wEsLn=2TR#Y$5gH
zjnpU&(s$^`gs<v==&}u{bqd(<RumYKY4O5cfQibRR@fsX6N|re;=}WTv(=cU&E0bl
zj8ea(K3PtB`OUfs@MabMQ}Wi_yiD)o>N_USi}cmr;gk?PFda9B5Jt#$_0wTFJ#n>z
z{xO<%xfC@jj!t9}UD=!lMJ>)S2HiG#cCXpLf+DvrZIMeNvVeuj<c>J&ET08$u(ads
z%5^?5WfH^>c)jIF>CI@r^tTX^*QDtzuD~Adi1FpB_sb?2v#_%QeRU|fU#SJU#K@IQ
zq;dT27|EREI}NmV275}z4sNHN_2rZx8|d``Avy%ghg8K344#{g2NfR#@}e+9kpf6_
zt)#J`RF@jvk-*QsNp;k&cFw&b8Hsm^#;=j6>LvGI9{mv8{7dgl$QBmYo&?nqkrbfo
z2N|}>q>k$y<TF7;>H5-9mkkjq9B9UYH@*dI)9&JP?qd1-GdZL8<}nGI|Dg3@mhixQ
zkqH87<=pF+vX8YLFwc_F#B8NSqGOr7aBq09&m3w<8u4{d)B48=C*}UJL83huIy$l}
z3Q4;+YcGKNt|buIgshA3jaFlbd8-xc3BILix@Z1dY#w0ZKnt+Z57N!58klwR!pn7>
z`5Ef+{+^WzDo~A4YE#gr{2)pT7@4D$X~O(6N7vS^OV{9lB@>vk=Sr2S;E0V{%Da<W
zBGj~aGCJU2-Pe#0`rVbUn#7Ni@Sa!iVAJ`TXdd3x)n6C+&_dNmJf?e1-~6w{60~0d
z!=r9-6Xxv@<<)<epa1Yx<=rlUpP_fxBfM$U>P<#h)%ybC>}EdU*rz{|DwKu<f9^U0
zEvsL&dJRZ3F<5j~U``xqc0g85xO))Abqde-DiB~^TblS33%);e|8&G_IW+K5{l@EK
z&cKVU(M!sYK6E#cr%8w?xi3tv-m+v;Dl8b>TMMj0H9;_uZx7p+j<eZf8b>%~Ic9~m
zGHhJi#T!QtB_Yh>>i|aKt0LhMz=VTXl!(n>>oXs7U*1CC-sO5g?PMwvq&29XGc^hX
z9-&?pnxtSi)<-X0snU}lJP|MW&S%C8OX}DSj`c>UQr(jnQ@wsr$}+!Qn)tRO!!g%Z
zs5CG|r-~Jzb074v**VD=f}a>;&$~C7^kfUoh(<nVuK4D=T<3i$8w3d9kX+~=Az~(K
zoPOLb#I!hiH_|HT+<fq;k1qfLrvv{-aI+}D>#-PbzOXJWrBzjUb$nAdd8vfe!dEz-
z*@zw%nGKXhqhl0Js<)8fMJAz`*mwnE;{$SZrPnymV!a6~3lKbVwl(W_^DN}l7$*MJ
zbt?CXB^Rs-ekiA{Du8{CHxrfB`2l`8aT+*Zw#UL_+*Tnu4&hu91I~cD9z~p9XDl9w
zsjdZ~$5U)#Lo|^()tNXDc%SSx1+@PI^4#QsVw>b*NT3%TmYn%RqvT0D=QgXP6Cpyd
zPX|)<QqAzTJ~aCyUISaX>-FD5J*0mN%r87~(vmcTo;CV0?k=9q(?w}EPQz@$SCnDn
zoGx!5Jwz0zt*1V5ZQ`SrHtBw3`=DKggTtdlDVx2>UuE+`q*th|b@|@{JrMkuydM5f
zKykg$@IBc{BoVH@3kG=5T1#R-mz2Q+9<84ZYFAYH<7Dt<gXpV)5*76{yTSNw**WR{
zKbL3U7O?7j+g7%o>~cZ(wJ|!c@8XN_U3)gq8n!&jxZsY(O!u4pW*m6e)at6o{WKxG
zKZVg2Vo3@^<s$)1yWNQ1lERPoLhm>TW{^qUzsxcuPwf{%ZO>XrCg+3gRGtw!y;dI4
z#o=B^SxyS^L72K8>op(%S17s|R(s_c;-N}~+6yj$*X|M(5fjzP&n^*xgl0TT*q(Re
z&*{^!iwxcKGDyP34{kjDN^)wP*(-qNBO_hGr3`?0e$8mY19V#W2k?X&t#-0ex#lt=
zPHiS^ToM|`XbvhfzAz}@Cu4-QMc=0CPiicJ@z~OJE!NdY2a{rlx}!QqX1`l9d|(Ou
z1woSHXQ{bTCPC1^>RAMc?>JtWQEKvun@XbAXK@E(qW@hL-8<-oS8}3x<U59A6U4dB
z*3t1*-bhuSF(Y@Lh@P2U=cWUfBoUTP*S3@A&QT1RKG>pk2!ax+HFvFS35wZ4m`hrQ
zDAI0xA`I){7zK+SD?VicFHm5S(r}`1#Jf)JFZcNjGlHF^Gtyni2wxISnsuUAL7b?P
z<!KA<B4mcfnV~xboiusv`V-WT&1g=o@9U>Nq{QU<kwV$TDwU&Yv<|Z^Su{1p!r*S;
zu&%t%VlN)L%WyI(D0&JH$}U_D2nn3sYgwu6hJ>c(c?G8MHFhAMsQ&gAq=HF2R5FTy
zWm}cfeDD!AH=>7#gzR*fV!PKC+}`pJV;&f=o;`iP3$0Gx)kU`ssvYe=7zXh))D<k`
zo13@t2h|QzkEfDJ3ALZ6LGkcsimc3KeNG4`?9d{$2)bzIcnL-r?t<AenK|FwxtQQb
zOEg@JK<%V)6`R;*1NVGU3xSB==<d}LM#f?I+4I9?NTb!VArf+|yMWbF;^HPBI1$I1
z(!U6oZ6}xca|oS5`?jW>+u!ONSdtYWU`=H>7E0|O_HR<+3*~I7ECnAXeSJKNiD6Hn
zrR-Wa`bQE(eVZ{^*0FDd!m}p1@#hduU|pLhhb<Vo@aIdq%Lfo*;t)-IjFr=?5c4?F
zm~~WG<g`!v5daV=P1U%r!U8BU<)EREb>~e<V*pu?Y48Da6Z6~`V(%D!1Y>p7K(Gzz
zO_?`H4vBGgVx_|VPJAd9IAA+Uc&EelLWtJ2mvvSSPNh8zD5L6Z!pjeU!tOny?f#fp
zZBfx-?qPy(+ex|oH~%?V1E7|ya3G}$#Q;xn;mN_uS1AH_MLzcmvr?d$EB%*z4F+PX
zgNBM{{+wbc*#Xx^n~N%OAobCF2YKt_9$b+BttF|*Ocyi9?0ZE%@xeIrI~Op2=|lH$
z-#Ay$X!H#I?Bd`#Gjj(OY*H}a@tet45izOwO^YOIb*4YrmZF=zxhse&9$R7aR<yK*
zlxN|LW%nB^<&uivpqI7#Tl6?p-@^cvfWQ)6`TiF|*u=CmEGvmXwK|#srcg7xQmW;2
zM9=d9HZX^M>(Hco5`l~l3Bq{PZ5L2g6x9H#9+b@o%*C7Mqms7i`G;=tDfsj*O*42z
zzx=m{Kri#U{>c%WGPq=XAXCnDKC|~(Q*R@ZdcW4_NvVttQA*t6@U7^wS`gCR^wI-}
zt0}pFM7`axq6i4MRjDm&18g+!ZlgqKyB$rf;8Pp*Z+TLJ+(pVE&$d;81TIa{e&R&7
zs(R8c?zQJ9I>rO$LDf><ODg`Ds%?TQQ7fwzX7aXVV$d9gINz|0haWACF%IKk&>&`2
zcZ|mFroh3sIQ7~9<r*t6D~=e(3)x;Oub`m5m&8%~t;pDd{8@jO28B7PI;dOd2wDly
z26b1|68*ThA{0fH#|jZ1q6#)&GE%!~8jyEgnh}J6rp$y;ZwcA$pYEbM{7YI|V?h5^
zSc!HP`jGuVAAm3X?0gZ{2E1LR+UN29$xqd*R|NKa^{rJh5AZ<~5(FD5d^O+?@O!yL
za%roT{@0@ihlX5_m%cAP*J3013J^s1ehHe=9h^{fIX<i1DyMiw9yH6Kf(pG@t?9}!
zTG5x)QW<C`-^Wl?{Yl|ZYdMk($5j(S{Tc*p7}=ovHU1Pu--dwqB)J3*)yYm_TSsK|
zaqk0MJ0X3>(C%eg<jUKmaQ5-#e2$C-KmGbzVh&F{=4I$g@AbLK%hAbFBO{*rf>3wx
zlonml>^(Cn{gds%CtE=3VzJp$3c9f~h4FBkv~+joBVcWS2H6(~g!GZhm&AowyTMRS
zAAfBiflC|Wf{s6>-g8~Lx@G&v#D;GQ?^PT$2kyX>)}yBZBcAsCs{_>VZ?f*4^mOgm
zSx6T44C{#J5)d|RCH=MFb=^zU|6~t&zt`fObDmK>kD2L=a~E`NgO$Vu$WF1(g>SU?
z1*nnemwuK_Yy$h*tV|IU!Qp1sZkP4j39kLT>>5`Cw!3RMos<|lKr<k|NXi8}e6+Eg
z=l0nyM30sSen-nPvj68OCVljsydLHf@$3%Ng$K<c!5skzP4w0X_u|o!Ou4t~BL-9?
zcY_!9fcb1O-0R>)A$|<W*oVfIqpl5tZrAIaeY(36l24{WPGGs#jq$iSI<9AEmXan)
zE}3?)d8SRa2)3q1_gUJ(lliFW$_yI(8!ESxn&E2<-8u7an{`Y8q_Y{@++fx&GPw8X
zfmmq>(Ai8kH<q(G7n8l}I`@#lB{=Tf#l%MC-?~HtsrZ-$-<|w4;NU{&Z|!TArLYBo
zuyQfwnG-J=USV7mGL%>TXB5<pQ|lGL131|F$+;J>i0B@UClfI(na~GsWmrbW)mWOq
z7O5u<)6D|^Mj{Um556|t7I3!QNzR%_-kn(Gf7O<w8S4LkotS(MYfUs}CWe#ee^-dj
zLTD6ek1t9eErq?3)$s%@%igctsnMLDKM+rA12F;EXRF}ZB%2p>dg3xBB9oZY;3@Hh
z1djfKPHc^o;>3uQe<a@sssl0o`yhcB72O1*J*Z-YN2#p(lL_e*I7wI_uqAac2FYFA
zv9$I0zpOz?U$PB>n9}=-RTV@<kojF>GEOO}ABh?JQ~Jc5-AjHQ6NC}Cm$6^qP_ez9
z%HHbAk2d!FC3i&vl{1Fa@F`<dxbx;6d1iEr2%^=UY9Lw(YHSNTE|OWVilVU7I~Dci
zv1nWzSe0&SO%v>??f$hIE`x>L^Z;np;gV&(d^oI`CsN_LJ4i*Cy`2EFOlQU^tM=aG
zitjb3spj`N*Yx#Xc#!cE&=o<*dU_5wt_qcJpF05de8$#E67Pt=?5bV*@rYE$iMOoH
z(!p$(YF3!-A*Bl6h%{Ur?n@to#ZgR)ekkCtjtW=aVL*!F5xkbk!uTlzaF|;o$RM{n
z|J{a3Aco`mRTtz`oZ)ue9~{m2vM9Dkp65Gj5yw%>)?YK6Zh1EL^c~iBaP<LU0NhEh
zL>l@I>2${t=7(J`hYkFQnwhfpckjEMv$uG269hJHf{;UmwqbCwAS_gU_Yu{YDFhmO
zJ>i|Cc!CO_CaZ(xpLvn1<6CmCLp`9H^<Bf#kEl_GXy3fWN<wh!6Y}Pz$$f;0ck_qw
zCDEY%%=+r&Cz9;v>dY;i3|@=X;{+mL>u0LcFp~XHpMFY?d~L?&41&E=8vTZjgs78}
zk!zK%*4cjX_;c~9e9@ESXCgXEzp7E^7{Td&t>0P#4FvHItvd>e8;K7e&drH2!Lo>{
zChPEt8}Cqh?)A|N1*xM*)2Vv2g-!^;zJ6g%aeIunb^Qq2#{H(lZfH_H_}k^jBPEA0
z1K3f_JKu*Cq3izrPz8fJKmOndSOGhdti@GAcgqpNzyXW?pdA3_|Enoen#FM5Bvg{6
z*(RtmbyYcWAQ~(Yh}RmdnPTM9T#5hPfUU|Z!sG_F+ycmB6uTa(Lbo7Z!D?eJj);lX
z-*nM#UInt4f_5-`eG_#aHlxl9FsBN<kWS}?Q1$HCrvVKr^3~L^)hI0@;idXlSlw`6
z9b&&Uz~Qv$+^&t9-X;zF-P$E#EJy0Z;PN}u51;=0#lDmwrSdXWR&<FFb3WHVj8TJW
zoV$rnN3`spKZ-41^QoAiFAKM2ucInXkp{Rhx~pXVWJi?}j*_`N-CI5oGM8Q)Yc0YL
z7QlwO@$$pi{Q*q>wBR@^)TN2U!vqgJFWbtk2t7QRTs^_V#0@}CL}c&;Nm*6mgN_1L
z_%nX7C=tk3Ge9Z;J^2We`GFE#=|3rEuyF#$Ae$&U@<<V|OmxX<p%7-Iwhei0+2K@X
zhR#h}6kqjEe$To;dn+~F>eFMavR7KKefo;EcZ3VgqhZARv$8Omb&*TS7#0<4^@DL9
z?B0Wqd)1%a^rP}uDzkVe<!(gNc?{oUt)lF@R?-|K#2H$NF^B?nAX7g%>aD1x)1i0u
zI1qoCtvDmQ%wft8GmYlFLK}7SE1s<nF3-W0sdU!AB;(E{9K&*S(XXg6R)-cwnQeH(
zjhZAT(2sMSe_s^b<1nC_BgTtFC#Ro7(m8aAE(q;!!;)8KEo(-KoB1v}x@7J}S4HOA
z(=iOI|9_!j3x}2(q2!BT0`yVHxt5!Qf<$z*!g2Kp|1a?Sg&<QdyD@JU5@9t`Z#*h#
zeX-T+)|c~{Y`6E=cAt^gmscBi-WFVAob>gkrZDY+eB^O!)1igAc02Mnde#PH0Z?-Z
zum-4cmf19N(f#JCjut8D-GaV#t9aEM#eo{-Un_X6K6g)G^s;<gJ<&ApFFQ+9=~N%E
z=J<`5Xlg3L)?rkfLap8GjME8fz{CgYR*gc*U{N>=;Zpu9OZj$CFOixYdLe8_2ySQF
zw)N^ILQK-*LdHDj<p48whtgWUmRB08QY&YLots1p3JLgD<#oV5=ldhBhb_f0o(@Gc
zt@W5#FX@u&!B`D#OYRm45nl@^ts?RA7<pzatcv97LLjGu`V6&v%q^s@Lyt0yWpu&?
z7ZhGBU!oQy4Wl)v*qZpGg~*ZJUCUUEt@Ie;sCL74(2hWJCdJvXm}yS(ct-7u21v6N
z)Gk6BFD3aiE`uc*)UV7u(&(xF20JWIOzF^^G5+MI@lp<f>t>(E+GzfExJG+Gl*vTU
zLhML|*X<H`&{HO5Gj#?=f#e~0OLd>~t=QR|<j%&B+nZTO9oFvaaLR1?ig(?J=n1&$
z=ffp$)Brgl^O&Zr=DSl5I`oN!(Qwy{iH6sJ^c3K@Rbg~Zr+se%XXoF~X1c%3ZE<;d
zX61Frd#<exoGDQ~D*?STmMir_fiNHtV9_27JMh@#&2RDVWt4IPchV`0TaMTi-j<RW
z7QIMJdAb?tYE6HagAt_gz!o5re+G&G{D*YvGir&pTC$yGzA0VWZR_PRPSJH)n^}Li
z%)^3c{N^^QcE+f)-D>h84Qe&-@jxXf_lQBR;j0+E93^8kr6A}65~@^k&$M@~J7zjz
zn_WlWaP*I_%uZBB*(Ab7H<}p?<&GSbS&UZ>xhZz`p28AVuCSN8imQ5q{lq^l{gVCh
zGfd<O?7bk@sax?Ryv{C!RKi4WAl;rS{nMG!Zn`)dDFaw4MM&UD(UA9m$<u_qqx-QK
z&Nk_@f??U4;tzP{r5!OH)1BEo?Vmg$<Ryu^hh3B$)oRo@qoJaVF||}<R{oMGf!YO&
zOlY7?Szsf?s;wbCT7IskbPgR0l;(QMJOf5PKX1z5pfO9KtmQxTK2HCh+an%nhq@+>
zweZKv%ocX#+}JIpWMua2J&!a?Z0mzsBknOfSN|NsQM2gs{d<oy&l-F|#Z3VjpxIH~
z$xKh|(xSWeafQ`XP5Kt%dFQU_PW_mudYV!SZ~-<=%Oewu5&Vi?j%eJp4psw-?dWj(
zoz#u@xtAKs%+^@lu@W8k8#1e*RZ$8ukrHU(jWt$2W!$jnm-Ch=VaL9gN-Ong*H7l1
zZ+iF6)eZ&N*IQomoketm+QjR69tw|M&I?|WO2$Jwn)t*o&rNF-Qbkp3cQ~)!HW};N
zT^`j>iA$TXj&F5n2^Od+3x&6_uGF^&@ury$xxRoW*mRELk&i|JkMQ%<33%(0q?$e8
zb`R&x__cWIa3p_Y?rZOFD@DLHn@uR?T5Q!LlIsC?26;cQZ%!~EdrKxqIxD3WG<Oeo
z3%~sb^ajxSo3n|6-(I{qkf_@|IDvh6uLK$^*Wj4szvkZEk{%0NnXdG*Bp3n-yV!9}
z$obJqo?tBc705yQ(6UF20^%fj_eAFzIM{+IH=JPrL)(P^23kpv59KUsNF_s~dASxg
zPF={e3o_;pgm1A*F~%ABv+k(>q8@^fxcQ1GHt(5K5SyZ{EAKZ8I)!g_Cm-VOp~g(I
zxFzPW;KW};Rd)0k_+lslnpRHQG~>y!pZ1r|d!P=PlEK)bU%^pt+n1Pj3SDz3rcgaj
zFVW0X7MdLTcV;idZ^ZF(Rwe$4^6UG?;Mv3_?XcI&a;0|V2}Bsew_H=^^~8p4u^3;3
zYMm%exxbI79I)n^tmS)JabS5<pn#o$gbw|Ib+1QJ%pV^p%Bvn$!J8ks=&2KXVaOd3
zggap5(wX_N!FpI^%~Z<CN#7=pbnq>6l~JA9+1$b$owyRIsMBm-&tq1wa2u6)RoR>8
z9S?9Y14()i0BVe)V<}V6ING}D)k^HTpt2WboR+?5VMBqT;5m9s!kPNPN}g>vC>mDv
z;$=X_VgvV+S0*}tFOYdFwO=28ZZnib8UWCBFZ%&~Ff49Q{qmLH+uNQG_wGiN#kq;j
zE*3Xuw8};Kq&k-<%~i?Z>O)(!?3MT6A@An49*(~UdsJ%<@!#2w(&m#BHn>H~_&8`+
z5?~ZMGE_JIj=sgbSx>*499cdmjMIRL@3~iJ)wpX?4g%^7G>yc=3tl_4u%Eh>#kqji
z(?AMCESBdb9JeW*ce}ZS_r%<_)=Hwnx9@7>E|nWbDFU#y-X<c0eC>x2#bS{>G!6#g
zQ^*-lJGir1UDFtc3#dGY1SrCn(BNcEITHc3k3v>p-AmSSrk$MfgRX0$qat$qSUJ1j
z*3PI__<ft;tCUBh1ZrwgZoz0#M)7;EX7x@^(IixD=a~Rb`@#HMUb)IhNRx(yY-%xK
z82$DLHlUSEwn#Obn-{D0|C`X|B!(Y{km?o6n|o9e*i^MHTBWy<U=N%nrx{G^y(ym5
zC3w|KEB(nh+0KTCe0hGv*<DX+V5AQVwer&SN8n^cL9lPrzE0*fadvgx4j{2?X!u(v
zb^ByQ_ertnJBcVPpQKXI4Z^ofiL8+P58G%=rO0%2MLHR0IlZ4w_%$rVF$MOI5(4$M
z|C7_duS8B!pOd<SD6n$r!dj0V*U+u&NH*z6;H&kb0A%pNu`+8qde^o65$xuId=Fsn
zh1C9hgss~&`;w@xHYTi1FCtV3LFe<vykZ7PEL$aGpQmQ4yfjhR+X}a|>8#bJ(?Eww
zRvi_DB^TV`wc^k^s@fl->)5_GJhyx$UY2vq(Jl<|+)K%o^1A~r>gQR<6|V&VajE*g
z+}b4SP4e3yoUL-SqdT1l=92FT5;1<DdRyyKoo&7>Um=4WB}F4nIcAHv$oUS94)q8R
zc^qj!{W)>6j7~fF{-&$BFQUPla<isjsfL_d5!O{TntK`vznbf|GlG38V-^gvwtlt*
zUjKkNezxYpV#@?uGNDNlFX7>s>P8*Q#zdB&INUQtp!Cl^LsF+#IV@U?JwZF*^RQ9i
zZ4!7r>=Uz;pgq0HKuL7kC9IBFIhtaoZH88kNPWHW0ycG!W0gvDrH;)W&Oxo$As2%E
zBI<Y&ROG!zWAsB7JPav4U*77!L!FA1IBfM|_wB#5)T^M|_45*Jw4qUgEEr;+Y=AJ2
z`h6(OMkCAA#I%CCu5#_r5&YS;C~xmBwZrIM{<XGSoQ@`#cW-BNaC(`HA|ewCXc$L5
z_@yK-v9Wf6irfgS?2J=O+T&XrWC*-?C6B6M4`|xyw+4?oZ@Mac(_62a5u$1-HT<J4
z{R*<%!Z#=)g}2XTimi=tO9GRbSQ;wUPFoL^TCAd-0w)sXyTZ&#$g~>;vOE7mHnXD=
znSp0p2423mCa#=dFa<Dw33aGckjOKjU}J=dhERTlm1!b~1UKBDbi$L==7N9sVk1|!
zu5B`4o^mz9#u96!j3w(FbzG8QPKUj_Hfk)`TOUi@8$7oi#%``$JF-(Is6=<nMdf2$
zKRsq&UrcM8<;L5-z_Aois1-S|-qE$$oD7R8ChLrwOQi_sOuO4&=Sp2Leh7}E_<hGO
zewgJ6(L^;O*v4g^*F6*}kvNN+X$r9eYU%j<;yd1|B7+fg*lYD)XjyDvPDA0uhaX_j
zdccc%d(NYxg8w1FO_s;CwQK=$d(0BzG09#2Xw%~aTWKaVFI5%H+-3DB3^?kSaL4=m
z0rP3q+)Ec*02!Wb`fbj&FRF5*N{yE}*)fLXu})rL`fLDIxgSRZs<O9<ysYm_jS>kP
zKBUvQ(;=Vzu~x@KWfUFVRjPJ^oQ=DVwG4EzQ?=--5e*O9H)fuef4iGh+_7ak$IoW6
ze^9))IEtKsGN|_Pa~Qa!H*hKZY$mSi4F2?tlGTN<Cw{^i$I#tJitJa{s@T>sg{>rm
z4E~md7z>r8r$*7j3~U3$b}*5%g0Bw?Ynxa@_Q26`!GD}&zX6j<^@{!u#=(&@WCSUi
z^(Lm-bos<qeE|ePpei~4TJ17E0A?U!|2qO6ic^3RL+ACh-5MsCy6a;>u7*fy)1>qz
z2TR=lV^|a8u&(SmfLQ%W3N-xs(a#z+D!0jBy-e&;X#RJCEY0xvgE+Cf4W&tIP|z0#
z2bvS~AK?|DiN@kEti3ZoH*`A?84L9;e_ETRp<7{Ned}s>QN4Q6(L1s6sHb~mn7Lzk
zAjv}Aab!9xfWF%(mv>6Hv*6?GJJtlWJ5U7RtC>Omxg>IneD>nhFeSL*c6HReqyVr~
zo4yB`SmVZ}(J4t~s+R;%JqOSCC9{0!JC$skqiY|h-InXc$P*3zK^Fd;lDw&bk9uzA
z1!@|w5I0$#CYX|)(NP@7RK;5qkzUjRlvn0+VEH6la?=<8rVqR>|GNu$tCvq!&0Ve2
zxYx=)AF1oTUr_-?5q373E%d*BAE@h9{d_`pSKM09rwaSt6oQQFclJm4;hZ+g7!U4P
zjtply!j3aV=f|$mO44X>cM!d|qUk+njpCWn5KF9HQHyx==`mDpEaC?%S-@TYpHzX2
z{`GZLodl^&ebGB4aJ#xq`IKM(=ZZqFQ80euIG<QAWtN2&7`>)39!nLb0)n><@O&rG
zXMN9jEj;PQU%~0t+5O+pe&an6tlM<cj6?(c{usM&GX7vy_D9qaQ4`wTkYsji(tkjy
zVDakmBS5L$mN@hINn0lx0~@o{;1(_vaacmR$YHcyu%F~XN>A3sI2&?4a4zO{JzOCV
zVJ7Bum|x9k&z%e&ecp9&M{32SF_uu>50SSi&tiwihL(`Vw`!BI6e@PRLJ4E-MYe6H
zoc_T65nH$f8HO+$&hW`S?kpsKT$3<~yS6z$te@kN=w0gObXEbjhvhM-xIj>qCpKWq
zVJZW*{r<egYQrF~Fw6LryQ^ZIz|*lg%<=}NM!?<vjxBoZ5XT@Q2T0XY-+8vfFsEiP
z#@?=TfA=m27EsH~$9(4OUyLEhy-sYL_B<Lti2QQ0Sc-Ew=5&>AWnYB>oJw~yN%({G
zd$+Bi<^f%DKhOQEYW7d)aV5zJjqzdp3W)1ObA*qd<9ee>?6FlPonXAMp5~eIbw+oV
zQ4!`-P-ss7i-$$(D6MBBu<<MScyHQ3#Fuw%uax(2D9U7NHFOtPm@tW7?K$q)b!Rsk
ztZIV}1r}>UZ|pe|gtz5eBSkeN0Xv@t;M5uRETle3CElk};ik)oqvFKjPP1sRm6MIw
zv@A#`9gIWE;qv@wHau&VHzo!LzV-f9BywR};S<Q4hN(A|Atx$H{Hh@Ml2zJ5Acrh`
zM}?Gl$Z-d!-x`zGn#p%An`w8Q%t)K$R0B78bG#}oW&jXfqlNcZ`2psW@E}W_YlR*z
zt&2C6mbZ{0Ml^TP&IcZ$ND=!pOkDOB)rGzN><mcI7RP8G8uuWT8oT>B58TOPPdtiQ
z9$$>OpGdM<{enSZEy-L^^Gt$$gu9ZjIErYLe5|uJLrqk=i|t+Hds#pma*ws!{m3cv
z-K;$5U}HB^!mg5L*TnW8dfx=)p(Q<IfzeR5jHGK=&E#ePrx4Uxu%CP|CMS9k{TkoJ
z_<vIkv!W715c*^P5m{~k&-*4Rk?6<%dLGg^FJgE*^w6ozNpvfABvjBid3yt)g9S0T
z06@AdPA~}1dfMpBIqade#07u^Z_1hiVsi7{8lbhb{HyK^(&IuY%$iOMjB_>b{sQgA
z{OoEvya7Lay%i7=3*`|sh{{Ob0YJ7_?S^}2L}TZqxwcm9biOSlA2&oLs#rgNCCsIY
zW|;)?;pnFF+t@V<;%NJfLoHB~s;>#ive|E?y5{uh&Rsk6=mow>CHlBJtRB6HDhd83
z!NhX5+E<71yZNHpV=^13=pP|Q1lXNX9WfTK{le(85$R*dw@}jBKb-W2WALgZSov{a
zw~{D6d^(;4C}bLA>Hl{Q2TYQ;FYNV2KSC5b1yRsrR}xgmO>}RDQ=K=qo}QA5D(goL
zsilnKQH`oSthx0&j<<)3{bZKrK_4oy!(vl|c*;@<Gf$Ar8_|iz+RYE3cG}|?awT@b
zX>10-;`4B&q2SDfB1V;(V+L<uW(oBqs2U-DW=@76e7jfw68^4Pz;SnHjz4LL!_p}C
zIp?SStP<s4%z9td4Tpipt^%*2Jl}NxX}K4c$k5VBL2<K6T|xNdC}}8c=;FIP)}3KX
zGyPL+1da<>{(IjTd(F;vf~xkMO>$CsZ0-cFO0w_NH0d%*=}^Udl#vpy=<vHEeU0no
zpDDxc|64l6ue(~V<i?}>TZT&A{t39qxU2k*;I;}rT8Tg=Vn#Fc?R@N()@gy|PqGVk
z9PFjDv`CNiy!7Kfk%sCRFR>Gtp)*uXIe%dqMuzDwJ<!C+0Nm4@*EwU03^|KgfyMT+
z)tvubrH(|8p`o{#L*xX(fj3xinu--aOkgi?H)dufihT&%`v$fFsc=6=&vWqCVtgVU
z&pf&0f-qm46Jus<4^n=+vCJ0^#&d}oep3v6*(cE152ku{32s}l9O6PyM}?~T*fXtc
zE7-neTIl1<EQRW_#AeNSbd%KT%3@krBv)^LJzbMQ%EUET7a>)!$-#;b8DRyTaHC9Q
z`@AC+FjnA|{IYL0F}G#5_D^R()Oaaf$LSHk(Wii7sroL?V*12`O`9NPkH9o?w!Q=(
ziRqPe`Yn^zrRohKu>mOETT(DpEAuCeuxiQCAHXVyzRI%L<+6hWRCZS}IF%n{6<uXm
zwUgf}5=s_Eg}br=KcJ;MgU-kDUeWMiPD!%Wzbpi84MtXhC!u?Gi2q{2NCqWYxDobK
zv%aIj*$kn`qo#JWYWD!IFCFzP5aH1sHB%f|1Pa9Qd(#a%o+Rx0VlCe?P%9^B3<i3e
zsa{V}K@xgZ4mD$rTis!#l{Rsw%(eZYjM#!&{$;SltB30Z6J)h@*AtM+`t<kZftD|^
z%dq+*-!@bAiHddSrbxR9vkok@k}EJ3@;)Fsx<Bg`R6@7QpT9FBk2hn60tA9EI+Mj~
zEGzM)*rqM=E>8J(M%pC%o_Jk7j8LbX=Az*)-1Pxr9QyKhW^C@U+q%5W-DPSqto0$6
zHi<Bo=yS;mK=;Jn*(2%URJ6!N{s>4!SRV2#ML5~FGas+1-pOof+iO82zwa|)fm=i6
z6>%7A8Dox7Hwl!{>rM^JLt8hXj5oXh;}t=Ui1ABJl(a!aiA!;&Q>zxcdK*`^tL5KO
zyTKpXn~ludK7ox(>4D-Mnj$qzTvOx3;@Uh;%EiwzXPZGL5+k1%j$$UQq~-1dMO7wb
zXgx_foVq8|fykKj<Pr1~NUkR)r{a;!7&SF+-JsI~|KoHZUKE+>Dr)Z(=Y^(1pNr7h
zj6WQHp<ew3TOUu6L9sNt24VZ!P9dZfgRB|0H1S5Bh41xRI`F^X{w(Vf6@K7KNfgpx
z(Z^cGB?IeBQ{EBjQLzT=h@1oeK1#A^>f=t<mqtMRji8v5ZqnUuM%6l*0d^FQvUxax
zbP?q7@<lDdpDqgYOEGyiVEHg{k|7w+>V8N=i9L=8iIN1{p!w=HFDv6h88{9`l1uPE
zp4vVrfq$&<w~WT_WNLBC$|wQ60r~PonoNcr7BvO3D1Y1N6SUZqCaVeBam}zXbX22;
zcKiL%cSgQ0K`^;*9b}g$&nC%4RMf+pSY}EesNthPIW7EyD+O_fM#F_-z~JxBHoaX8
zLP_oof<72MMmT^K<FhvaS5IFvcG-(-DM=z!B#*2FWehBVt{fsap5YQLA6TaBD4*Nd
zti^;GkXF{p40hJ!6WfxpiXbSYw9}+&{37C#!11yWRPN-!tR16TOzjuG4P{xXfkMEl
z7?mlxz0XIiVnH)c1E+m|rek%fhq%(k!x$4Bs%{_@i{U#PCR$Yng`x2NuhyoJnnpD-
zJ%#ivf%li@NMGJZxV)Sw*24l)E1L`)fh9*?FW+jGm6iR%l)}3xp?O@p1Qij<rln~B
z8i4P*!5w8h1V`H0H#*ed*Mu{rKr?1Ler?n#?<6#l@t+<YxQM|v--5!joqsW-ZZ-tJ
zA5Rz6hUyxSjz;8DHy*e>#vR7JqXJ4!a2ooCLs#ht{??WHtfEh$dmdN=K%odPjkdy7
zwI;DJ0P)@p@{s_^&;qkde`|DMECpnNqVv)2;VnmI>zUWm^De^*CB^8yAR$a_-qoAy
zwOKaGBBdwXNVSD7$%*p6OJJ@Pb4;xlVg2<~+x3i>R^~vO4gA>V!C)Pd6X<ah3Ce(-
zzOjpH6Prt08<JIBzdKw0*hRzNWV)@A)4-@-8{`i};E3b3Cj8MS*M#VJNW)VhL9VKy
zlERHcgtlW41*-?Jtt49gB{at3g>qjsXd5r5TMkbAWMAj2J}e;(3WFPBi8(h^<Cv>!
zSjEsQxLSi{M_!mw9{hhQ6;+Qm++Xq=i*Il~H(8_~B92PGYRlbs@}8)vI1tZide_#C
zH#LirWrjJ2(<xate{ku`FVq{cG`NJZC!#@N(-C`)!z8W|1ma9a=lwQecvy*=8>`>C
zOw%SrcNqc7jsc_5OoZanE|5<mUr<2GRhWR^!ggV?5#PijC@jPR(syb>Q*b~5E|$e>
zC8A9$V<c=50i)i#8o_Z0JwKyP_eJQ=qUIawUs3bGpc>12^;R?27!>|Ev+Zk@gyF>#
z-gFz*o`R&0SqCiRTY9i%=h{9X7R~s%5u@Vmw0ik~oK~|yUXyI9{@9a`nMtx#j1sSM
z3;ru)<&Ln&i3N61p(zAaA709?`B|A1mpY}!Ra{dChp;0;$KYQq*R&MCOR#KJyMGF$
z>t`fYSZ~?vr5|o{zdL({-Z53=b7yU9zW7Gvu4Vqueq$Z>A3Z7mt0MFLH(18<HiWQx
zJqzcYZ`p#F4@oFM#Rv8aInd3o*&nNq06F%4LC#tNaF>UU3sok!L%*tXF9%^THm9ms
zEO+I=lk<C~3_Nh8UIGyH%2meb%RK$uM+MIWPJ7n{wuo${y@S92mXxL^<B5z^H!IoO
zvUuShS-v%X85k5};i?3Ev=_a|5*1!rOjG&zjCQqZlS#Gf=C-rwr;M5j5&xOcxpYTm
z4=ZsTkvd)l4w|X*ikoV&9r7jaBV=Uk9{Do~3Oojr;4ec^$Pd;P%o?vh0-@TuvXAtw
zSmXi{j7h1Z(4?YCut%Glt857tU-M4Ayjy50_Zv8=q=;%(q&(;%GX2c)+{#2nM%cIJ
zfIb3w7zHB?p|7Wa)xzBRavqL}9Aj@i^Mk@l>I`oqN2KTbzT+kdV_6h*y~uR;SX(os
z*tI!i)vZUVtIS=JVhn=4zcQEl@Zs*P2Wfk)6Eq?rWN5Tau)y~EWfxt0tsH$)|Cc_O
zj&0H)%p|O6v2J~I#6ZuXNpWo%MT5ESZ!GUNS4c;kyh^ydm&oh)8t%5ra9LpOB*hA}
z_qmNG4YU!ic2m()q!thMh~~cI=_oN(;r~g8{AFQ09)Gxf$8Z9xoXu@mJ{dL<_9xBN
z!j_%&it&hTWs1OU@uMl2{KACac#D>8?_-dhKFytvaPV~nxF|3sjAI4SBD)vx1BEWW
zm3*nS?>0Gs`PrGw?kY`$cH^}h#558aQ|DZ^Xx8K40I_p74`#s`Zk^>Mu%cRv4Su@0
zzE7s}`1Fo5uG~^)n?Sgx)aW!!PU);zHG??J00NHX6!=7hPUh$g(-brMxfF#Sc1Y<Q
z<k)lPHKsu%AZ1lB&)*FSRwp8+g%bo@3XO&39w~2FIaLQge1HyFZqKLyCUCABn5L0Q
z1SG->^#dCQ-4Y8qLNheqv`i-sh&B<3Y(7m>({<mMG=mQ8p|5|82=1qBvIT|Njo#U3
zU{s*D<1o<Cd+%&tNYy{9MXg_LHV=lXA(3_Bb#mE`Xb_dAZle-1nxl5P=5-+HctqE0
zK>hapRV#H?-)n<6SIzHJMg&JfU_pdZn@3A@>f5~2KWc-lfyxeRL{9%$uTcTwhNhjI
zK4|Wv?grE@L^YMIAt5yIzcGMwkFX-0*`^LtR)=xiFOFWtFktkD(&McjgjiYcM?I;K
z48Z{UivMVViUPF>aABWI6Woah5eitMY<s#hfX^J@xFy&>9q4e806sZH9m+4&Lb)7-
zG9CyH1RTaYGZJ?<egO7UWubBIO@M0zM*>ex{$qcMo9L5$;?mvvEr$o|TP>E2ju=C^
zI^*pV&$UoFZVD$$#l7>wbAWuEs6J1x?l_W-YODaut<$tHF5~T4a?JfDtmLFn7fsy^
zuM>kgjDEG9u_@r|T7%PiUotxb()Y8-{Du2{DqM^?$2lvn&RrB=$l&sTHyA{cDz7to
zF-Zb}DOY2pYW=!+Xucb9AAhHOu}Of=GqoCDl1sRBvJw;czA{BEjnZo<Ekp%2PeRLr
zPv-2h3i?7*ZDC(~ra~qSgZz*glZ5acVO8hOr-yaeE6WVlYX)bN0g?1V3V5+KF_k!+
z+lW8my1L&!FRnb(ZEjpk_=QaQyR!gc$V}k_BFBBH;yHjW2I_ym?tD}h>cK7fNH%9g
zPQDV(!cHwy_|&3QClDa=`(&(x?p#18Y{RB(lF;`G?dXs2h}4X0^59#VutmPVR?<M!
ztt?ZUkyH#&!t@8P-q@WM2IspoGt=7S`H}+{+z*Sg)yr%!PK`t;Hii<tL>x3ypTw9T
z!$*9tjA4t_3XPy1s@a=lLs)DE2z4b!w{u;pYZFsH-V-L<-Fo?s?|kYTjH=e<i4m1A
zImUV`B)32&>#Xyg_HL^SMKzFnYT+&<U^=DAcai46eroVO{a4=Zqrxw3snIy+yOBjR
z?T;zmtiX1eib2MPZIzSzla-u5Eg-BwZ>yxTGR>PgL~~C6Cbw;9eUZs0ami0i7Q5lM
zvN(f8SsM>4Ce|!Tr_5IoW3macZ^#NzFA%w;J?<qX@!<m`_E{ENs%i^XLK%JWW|S2L
zz@bj)lcx{JmI*>5BLZoXpj=SXRF~@&Yx01~TXjK|)2@DVTWS!RyPHJMfQo9+^~(;b
zT;>$EkD!9=Is|^FC(%`o(_jq@)8L<sYwtw?tB!G-_m2fw<ZM~ygb~TJc!y%~uV&qZ
z0MT#GD1ALMb&k+ugkMExU)9bR?9o<S4KYjL_jX%rF0*aNrQTMuXH7nvP_I0GE!WYU
z)nitPy5)MJj}KITX0ZPBJYCH5@X1vn&N}fhk*9a8X%qblcf%zvfNjvG@H#B#r<<>m
z6O#Jm87F({Sw0}Kw+NF{G+9M&H!7p$RIkksyE%n%f5<5f<lOtUP4gRfHu?8D7)MwN
z%;H3{$2?mcbeZ+V7^~|1oSrkqNbX2`^^vXNDQdACZ5Vr;L#>Uns@mVTHK;J3;v07X
z`+})SXPF#0lHWBPZXbqpq^64?k?oD~&5|Y6>;3oTUkX-cxg<8;|F;QG_u`zOgh}wx
zP<;kSa~aRno7w_Js8gcA_{LnF_E2_1bQRXmw*2Gx?B<{4`e@1S>%58yJ7?@?`Sk0m
zx7MmcW^>pwMfBMiy`mk0Uhx6(s2Ua+(c3zqQfq3rJwz7y>FU7MfM}V+Kg!i>lFrRE
zQ_mFo6_$2l;SrM!s?CA54OqB1DlAsAN~ey3SqY)w^F|aitRh{ZI%2Be@!ltVIM}~2
zxKMyiQf?V&l@0d2kjpB&hT$kP3OD65jGIj8z74rb1k#58&HsoYj9$>LO&<{YHNIEG
zIdMHx+Z62z{br}h6kbhiO&{mw)A8!7kfen+`vrro8%lDVvJqX%moz10eC|uc5)Yxf
zWq`T6#*Og7ZoVA5`Eio{hP`9~@4Cs_knDQ03yW9paXFFGdnp0G%DZGguj|5b310sa
z34NWAX4>8W6||6H%JtRe$&3fsalXd6=cV_a`VDr<-Ch<&Zp05PW+mwG5pVY|_HXwQ
zbU~{$0qNG_TrDq!^jklO*sz#|-6g8=UyRNt`b_>$q2KP4jo2EEb!@&S_mf<zT60x>
z?k;g4Zvo(a8t{3*vr}%`Zp(=g0w(7R(h-k+sT2i(7&}87PDEB{U^7prxK*UQ0@v!0
zZM`gJ7OlwBx8LcctG^JD=#8<{ycLYRl6+{zaGgsQQg8!sdC%qVHg)n<M#&q}6JQLm
z5j?#Ccn-?AiizVU{nR%mKq%EGOv^<s`2h`Yyh0Vynfbc1jo%doSsdU2kEH)FswhU{
z4zy-F%(7wi5JcNs5e)0<&y84j;5lTugdQqVR_(gw{g%!cC@&+0q%%M}ekx{hg;DRH
ztFHTF%=XK<71(nXwj<<kPn1mDOIA9H(7l~jFrT&-7#3Nn^bd>6Bd%Vz>eravaugW(
zF&DiSNXcZHV?BUHM+#B~HzqQ)wy#g_j>b2Ubjn%Xv9s5LT7oXV;;R0)B+CqgV^@iN
z(YBv~g~jz7|6(kHHp9q!^>XngU_iJ1VG2e(cs3p~tU-7`R#g+El#B7C^PSL-tfu+3
zOY{VeN(-`os&Fz+5)?VQTE5S~8aGaK(|tU`GB&KqTg%#I)BH2n99e~L5vKx5up*ri
zCYtkif0K(vtA03QT^9uw3nW`fwQ`>UO#IlkEPRY{gw0}B*Jkp>L)QpIyaAum{<{@;
z`|+2<pnQ}P%;^H<OuW+A7rmDTaecf#Yvr6FSDxzW6-zTe1XZ`TBTZql>Bh7_SZhXU
zW2(Kla$QI)U&52(JnD<f&j32*fK5Nf0;Z6SVHDBlUzB}lZ@BQ>t){E}K7l-z>w=HU
zg0g0pS6rh7Z?M`3!2IQR=K_k1#w$r%Y2VnA9FXd~9`d<o4$|^U#B=4U!O8l3tvH%!
zxPzV_2s3zb>6G1MYp+5S^!><pZTCAlfcLwo|2S_(pFx6P#HY@u;wc=svwalcVn_sK
zma4b5N_j^1d+xNnhxXRFKagLM4`f>QLzSi6;#nKZbFqlt^|36RpHa4qqW#S!;b^Bj
zAY}6b=q1ExhORv%9xJ2Ex?z%4HiXZgJc(kZ9=LGEkRG*<09t;Y%@W)}BPnRZ%{cb1
zPE=@=^MDSym-+s&=bZ)BK`?xJ;v=INkDQaE`WQz^Qyomjlx<}#oy^rAYCTL3&)*&U
z*iPosoe=M#^BZw3xvNMIS2I^7&ttz17EuU1khtU5EW<mxSDy~$_th`&aq5b+bv%;%
zn*1dDnNw@7j()26et2v?M1)6KKt-;rzC6ifLK#Lr3$Y|hM#1vsqy61AZlK6XtzB{0
z5Y)vqAn5)UR};>UXnzK|<4U7dpSloygA!-nQUBVuVWRN*wh05Q%&vBNG!Z&$%5P7s
z2`p)CQVHltt64F_@}g)`X0+u8Axush_r&r=m;7R!nf-pHXn9O`+`GoJT>!g+hDU%l
zRN|FW>KYq|G?HX;Dq)e$EJY%Khk3$j;NXNv2;W5~DY{J_^t-9!uRm`0|Cm_~M3ZrW
zeVqv?qI()UOT%n_{7oSQ5B8pkHlIiMWJ0&S#$8Hbs%+~lRdBez-uh)1T<G7@YhZzp
qD`^+JBK0~v7d;$^6goZ>ZywZ^fQ9{>E~w9{UV~%Hc@%mF5j1TdwfxEe

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v
new file mode 100644
index 0000000..ca58d25
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v
@@ -0,0 +1,40 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_ptp_std_synchronizer #(
+    parameter width = 1,
+    parameter depth = 3
+) (
+    input   clk,
+    input   reset_n,
+    input   [width-1:0] din,
+    output  [width-1:0] dout
+);
+
+genvar i;
+generate
+for (i = 0; i < width; i = i + 1) begin: nocut_sync    
+    altera_std_synchronizer_nocut #(
+        .depth(depth)
+    ) std_sync_nocut (
+        .clk        (clk),
+        .reset_n    (reset_n),
+        .din        (din[i]),
+        .dout       (dout[i])
+    );
+end    
+endgenerate
+    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v
new file mode 100644
index 0000000..e00b300
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer.v
@@ -0,0 +1,65 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// START_FILE_HEADER ----------------------------------------------------------
+//
+// Filename    : altera_eth_tse_std_synchronizer.v
+//
+// Description : Contains the simulation model for the altera_eth_tse_std_synchronizer
+//
+// Owner       : Paul Scheidt
+//
+// Copyright (C) Altera Corporation 2008, All Rights Reserved
+//
+// END_FILE_HEADER ------------------------------------------------------------
+
+// START_MODULE_NAME-----------------------------------------------------------
+//
+// Module Name : altera_eth_tse_std_synchronizer
+//
+// Description : Single bit clock domain crossing synchronizer. 
+//               Composed of two or more flip flops connected in series.
+//               Random metastable condition is simulated when the 
+//               __ALTERA_STD__METASTABLE_SIM macro is defined.
+//               Use +define+__ALTERA_STD__METASTABLE_SIM argument 
+//               on the Verilog simulator compiler command line to 
+//               enable this mode. In addition, dfine the macro
+//               __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output 
+//               with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+// END_MODULE_NAME-------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_std_synchronizer  #(
+    parameter depth = 3
+) (
+    input   clk,
+    input   reset_n,
+    input   din,
+    output  dout
+);
+    
+    altera_std_synchronizer_nocut #(
+        .depth(depth)
+    ) std_sync_no_cut (
+        .clk        (clk),
+        .reset_n    (reset_n),
+        .din        (din),
+        .dout       (dout)
+    );
+    
+endmodule
+      
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v
new file mode 100644
index 0000000..7afe47e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v
@@ -0,0 +1,60 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//
+// Module Name : altera_eth_tse_std_synchronizer_bundle
+//
+// Description : Bundle of bit synchronizers. 
+//               WARNING: only use this to synchronize a bundle of 
+//               *independent* single bit signals or a Gray encoded 
+//               bus of signals. Also remember that pulses entering 
+//               the synchronizer will be swallowed upon a metastable
+//               condition if the pulse width is shorter than twice
+//               the synchronizing clock period.
+//
+
+`timescale 1 ps / 1 ps
+module altera_eth_tse_std_synchronizer_bundle  (
+                                        clk,
+                                        reset_n,
+                                        din,
+                                        dout
+                                        );
+    // GLOBAL PARAMETER DECLARATION
+    parameter width = 1;
+    parameter depth = 3;   
+   
+    // INPUT PORT DECLARATION
+    input clk;
+    input reset_n;
+    input [width-1:0] din;
+
+    // OUTPUT PORT DECLARATION
+    output [width-1:0] dout;
+   
+    generate
+        genvar i;
+        for (i=0; i<width; i=i+1)
+        begin : sync
+            altera_eth_tse_std_synchronizer #(.depth(depth))
+                                    u  (
+                                        .clk(clk), 
+                                        .reset_n(reset_n), 
+                                        .din(din[i]), 
+                                        .dout(dout[i])
+                                        );
+        end
+    endgenerate
+   
+endmodule // altera_eth_tse_std_synchronizer_bundle
+// END OF MODULE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_gpio_lite.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_gpio_lite.sv
new file mode 100644
index 0000000..e3fde01
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_gpio_lite.sv
@@ -0,0 +1,1200 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_incr_burst_converter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_incr_burst_converter.sv
new file mode 100644
index 0000000..38c19dd
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_incr_burst_converter.sv
@@ -0,0 +1,310 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ----------------------------------------------------------
+// This component is used for INCR Avalon slave
+// (slave which only supports INCR) or AXI slave.
+// It converts burst length of input packet
+// to match slave burst.
+// ----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_incr_burst_converter
+#(
+  parameter
+    // ----------------------------------------
+    // Burst length Parameters
+    // (real burst length value, not bytecount)
+    // ----------------------------------------
+    MAX_IN_LEN          = 16,
+    MAX_OUT_LEN         = 4,
+    NUM_SYMBOLS         = 4,
+    ADDR_WIDTH          = 12,
+    BNDRY_WIDTH         = 12,
+    BURSTSIZE_WIDTH     = 3,
+    IN_NARROW_SIZE      = 0,
+    PURELY_INCR_AVL_SYS = 0,
+    // ------------------
+    // Derived Parameters
+    // ------------------
+    LEN_WIDTH       = log2ceil(MAX_IN_LEN) + 1,
+    OUT_LEN_WIDTH   = log2ceil(MAX_OUT_LEN) + 1,
+    LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
+)
+(
+    input                               clk,
+    input                               reset,
+    input                               enable,
+
+    input                               is_write,
+    input [LEN_WIDTH       - 1 : 0]     in_len,
+    input                               in_sop,
+
+    input [ADDR_WIDTH      - 1 : 0]     in_addr,
+    input [ADDR_WIDTH      - 1 : 0]     in_addr_reg,
+    input [BNDRY_WIDTH     - 1 : 0]     in_burstwrap_reg,
+    input [BURSTSIZE_WIDTH - 1 : 0]     in_size_t,
+    input [BURSTSIZE_WIDTH - 1 : 0]     in_size_reg,
+
+    // converted output length
+    // out_len         : compressed burst, read
+    // uncompressed_len: uncompressed, write
+    output reg [LEN_WIDTH  - 1 : 0]     out_len,
+    output reg [LEN_WIDTH  - 1 : 0]     uncompr_out_len,
+    // Compressed address output
+    output reg [ADDR_WIDTH - 1 : 0]     out_addr,
+    output reg                          new_burst_export
+);
+
+    // ----------------------------------------
+    // Signals for wrapping support
+    // ----------------------------------------
+    reg [LEN_WIDTH - 1 : 0]        remaining_len;
+    reg [LEN_WIDTH - 1 : 0]        next_out_len;
+    reg [LEN_WIDTH - 1 : 0]        next_rem_len;
+    reg [LEN_WIDTH - 1 : 0]        uncompr_remaining_len;
+    reg [LEN_WIDTH - 1 : 0]        next_uncompr_remaining_len;
+    reg [LEN_WIDTH - 1 : 0]        next_uncompr_rem_len;
+    reg                            new_burst;
+    reg                            uncompr_sub_burst;
+
+    // Avoid QIS warning
+    wire [OUT_LEN_WIDTH - 1 : 0]   max_out_length;
+    assign max_out_length  = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
+
+    always_comb begin
+        new_burst_export = new_burst;
+    end
+
+    // -------------------------------------------
+    // length remaining calculation
+    // -------------------------------------------
+
+    always_comb begin : proc_uncompressed_remaining_len
+        if ((in_len <= max_out_length) && is_write) begin
+            uncompr_remaining_len = in_len;
+        end else begin
+            uncompr_remaining_len = max_out_length;
+        end
+
+        if (uncompr_sub_burst)
+            uncompr_remaining_len = next_uncompr_rem_len;
+    end
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            next_uncompr_rem_len  <= 0;
+        end
+        else if (enable) begin
+            next_uncompr_rem_len  <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
+        end
+    end
+
+    always_comb begin : proc_compressed_remaining_len
+       remaining_len  = in_len;
+        if (!new_burst)
+            remaining_len = next_rem_len;
+    end
+
+    always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len
+        if(reset) begin
+            next_uncompr_remaining_len <= '0;
+        end
+        else if (enable) begin
+            if (in_sop) begin
+                next_uncompr_remaining_len <= in_len - max_out_length;
+            end
+            else if (!uncompr_sub_burst)
+                next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
+        end
+    end
+
+    always_comb begin
+        next_out_len = max_out_length;
+        if (remaining_len < max_out_length) begin
+            next_out_len = remaining_len;
+        end
+    end // always_comb
+
+    // --------------------------------------------------
+    // Length remaining calculation : compressed
+    // --------------------------------------------------
+    // length remaining for compressed transaction
+    // for wrap, need special handling for first out length
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset)
+            next_rem_len  <= 0;
+        else if (enable) begin
+            if (new_burst)
+                next_rem_len <= in_len - max_out_length;
+            else
+                next_rem_len <= next_rem_len - max_out_length;
+        end
+    end
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            uncompr_sub_burst <= 0;
+        end
+        else if (enable && is_write) begin
+            uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
+        end
+    end
+
+
+    // --------------------------------------------------
+    // Control signals
+    // --------------------------------------------------
+    wire end_compressed_sub_burst;
+    assign end_compressed_sub_burst  = (remaining_len == next_out_len);
+
+    // new_burst:
+    //  the converter takes in_len for new calculation
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset)
+            new_burst   <= 1;
+        else if (enable)
+            new_burst   <= end_compressed_sub_burst;
+    end
+
+    // --------------------------------------------------
+    // Output length
+    // --------------------------------------------------
+    // register out_len for compressed trans
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            out_len <= 0;
+        end
+        else if (enable) begin
+            out_len <= next_out_len;
+        end
+    end
+
+    // register uncompr_out_len for uncompressed trans
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            uncompr_out_len <= '0;
+        end
+        else if (enable) begin
+            uncompr_out_len <= uncompr_remaining_len;
+        end
+    end
+
+    // --------------------------------------------------
+    // Address Calculation
+    // --------------------------------------------------
+    reg [ADDR_WIDTH - 1 : 0]        addr_incr_sel;
+    reg [ADDR_WIDTH - 1 : 0]        addr_incr_sel_reg;
+    reg [ADDR_WIDTH - 1 : 0]        addr_incr_full_size;
+
+    localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
+
+    generate
+        if (IN_NARROW_SIZE) begin : narrow_addr_incr
+            reg [ADDR_WIDTH - 1 : 0]    addr_incr_variable_size;
+            reg [ADDR_WIDTH - 1 : 0]    addr_incr_variable_size_reg;
+
+            assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
+            assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
+
+            assign addr_incr_sel  = addr_incr_variable_size;
+            assign addr_incr_sel_reg  = addr_incr_variable_size_reg;
+        end
+        else begin : full_addr_incr
+            assign addr_incr_full_size  = ADDR_INCR[ADDR_WIDTH - 1 : 0];
+            assign addr_incr_sel  = addr_incr_full_size;
+            assign addr_incr_sel_reg = addr_incr_full_size;
+        end
+    endgenerate
+
+
+    reg [ADDR_WIDTH - 1 : 0]    next_out_addr;
+    reg [ADDR_WIDTH - 1 : 0]    incremented_addr;
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            out_addr <= '0;
+        end else begin
+            if (enable) begin
+                out_addr <=  (next_out_addr);
+            end
+        end
+    end
+
+    generate
+        if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
+            always_ff @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    incremented_addr <= '0;
+                end
+                else if (enable) begin
+                    incremented_addr <= (next_out_addr + addr_incr_sel_reg);
+                    if (new_burst) begin
+                        incremented_addr <= (next_out_addr + addr_incr_sel);
+                    end
+                end
+            end // always_ff @
+
+            always_comb begin
+                next_out_addr = in_addr;
+                if (!new_burst) begin
+                    next_out_addr = incremented_addr;
+                end
+            end
+        end
+        else begin : incremented_addr_pure_av
+            always_ff @(posedge clk, posedge reset) begin
+            if (reset) begin
+               incremented_addr <= '0;
+                end
+                else if (enable) begin
+                    incremented_addr <= (next_out_addr + addr_incr_sel_reg);
+                end
+            end // always_ff @
+
+            always_comb begin
+                next_out_addr  = in_addr;
+                if (!new_burst) begin
+                    next_out_addr  = (incremented_addr);
+                end
+            end
+
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv
new file mode 100644
index 0000000..ecd18a9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv
@@ -0,0 +1,49 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_irq_clock_crosser/altera_irq_clock_crosser.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+module altera_irq_clock_crosser
+  #(
+    parameter IRQ_WIDTH          = 31,
+    parameter SYNCHRONIZER_DEPTH = 3
+  )
+  (
+
+   input                  receiver_clk,
+   input                  receiver_reset,
+   input                  sender_clk,
+   input                  sender_reset,
+   input  [IRQ_WIDTH-1:0] receiver_irq,
+   output [IRQ_WIDTH-1:0] sender_irq
+);
+
+   altera_std_synchronizer_bundle 
+     #(
+       .depth( SYNCHRONIZER_DEPTH ),
+       .width( IRQ_WIDTH ) 
+     ) sync (
+       .clk( sender_clk ),
+       .reset_n( ~sender_reset ),
+       .din( receiver_irq ),
+       .dout( sender_irq )
+     );
+   
+   
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv
new file mode 100644
index 0000000..d9663bb
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_mem_if_sequencer_rst.sv
@@ -0,0 +1,117 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module altera_mem_if_sequencer_rst
+(
+   clk,
+   rst,
+   clken_out,
+   reset_out
+);
+   timeunit 1ns;
+   timeprecision 1ps;
+
+   parameter DEPTH = 2;
+   parameter CLKEN_LAGS_RESET = 0;
+
+   localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1;
+
+   input                               clk;
+   input                               rst;
+   output                              clken_out;
+   output                              reset_out;
+
+   (*preserve*) reg  [2: 0]            altera_reset_synchronizer_int_chain;
+
+   wire                                w_sync_rst_input;
+   reg   [(DEPTH-1): 0]                r_sync_rst_chain;
+
+   reg                                 r_sync_rst_dly;
+   reg                                 r_sync_rst;
+   reg                                 r_early_rst;
+
+    assign w_sync_rst_input = altera_reset_synchronizer_int_chain[2];
+
+
+
+   assign clken_out                    =~r_early_rst;
+   assign reset_out                    = r_sync_rst;
+
+
+
+initial
+begin
+   altera_reset_synchronizer_int_chain <= '1;
+end
+
+always @(posedge clk)
+begin
+   altera_reset_synchronizer_int_chain[2:0]
+      <= {altera_reset_synchronizer_int_chain[1:0], ~rst};
+end
+
+
+initial
+begin
+   r_sync_rst_chain <= {DEPTH{1'b1}};
+end
+
+always @(posedge clk)
+begin
+   if (w_sync_rst_input == 1'b1)
+   begin
+      r_sync_rst_chain <= {DEPTH{1'b1}};
+   end
+   else
+   begin
+      r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]};
+   end
+end
+
+initial
+begin
+   r_sync_rst_dly <= 1'b1;
+   r_sync_rst     <= 1'b1;
+   r_early_rst    <= 1'b1;
+end
+always @(posedge clk)
+begin
+   r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1];
+
+   case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst})
+      3'b000:   r_sync_rst <= 1'b0; 
+      3'b001:   r_sync_rst <= 1'b0;
+      3'b010:   r_sync_rst <= 1'b0;
+      3'b011:   r_sync_rst <= 1'b1;
+      3'b100:   r_sync_rst <= 1'b1; 
+      3'b101:   r_sync_rst <= 1'b1;
+      3'b110:   r_sync_rst <= 1'b1;
+      3'b111:   r_sync_rst <= 1'b1; 
+      default:  r_sync_rst <= 1'b1;
+   endcase
+
+   case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]})
+      2'b00:   r_early_rst <= 1'b0; 
+      2'b01:   r_early_rst <= 1'b1; 
+      2'b10:   r_early_rst <= 1'b0; 
+      2'b11:   r_early_rst <= 1'b1; 
+      default: r_early_rst <= 1'b1;
+   endcase
+end
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv
new file mode 100644
index 0000000..51d642a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv
@@ -0,0 +1,263 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
+// $Revision: #3 $
+// $Date: 2012/07/11 $    
+// $Author: tgngo $
+
+//-----------------------------------------
+// Address alignment: 
+// This component will aglin input address with input size
+// Support address increment with butst type and burstwrap value
+//-----------------------------------------
+`timescale 1 ns / 1 ns
+
+module  altera_merlin_address_alignment
+#( 
+   parameter 
+            ADDR_W            = 12,
+            BURSTWRAP_W       = 12,
+            TYPE_W            = 2,
+            SIZE_W            = 3,
+            INCREMENT_ADDRESS = 1,
+            NUMSYMBOLS        = 8,
+            SELECT_BITS       = log2(NUMSYMBOLS),
+            IN_DATA_W         = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
+            OUT_DATA_W        = ADDR_W + SELECT_BITS 
+)
+(
+    input                       clk,
+    input                       reset,
+ 
+    input [IN_DATA_W-1:0]       in_data, // in_data = {wrap_boundary, address, type, size}
+    input                       in_valid,
+    //output                      in_ready,
+    input                       in_sop,
+    input                       in_eop,
+
+    output reg [OUT_DATA_W-1:0] out_data,
+    input                       out_ready
+    //output                      out_valid
+        
+);
+typedef enum bit [1:0] 
+{
+    FIXED       = 2'b00,
+    INCR        = 2'b01,
+    WRAP        = 2'b10,
+    RESERVED    = 2'b11
+} AxiBurstType;
+    //----------------------------------------------------
+    // AXSIZE decoding
+    //
+    // Turns the axsize value into the actual number of bytes
+    // being transferred.
+    // ---------------------------------------------------
+
+function reg[9:0] bytes_in_transfer;
+    input [SIZE_W-1:0] axsize;
+    case (axsize)
+        4'b0000: bytes_in_transfer = 10'b0000000001;
+        4'b0001: bytes_in_transfer = 10'b0000000010;
+        4'b0010: bytes_in_transfer = 10'b0000000100;
+        4'b0011: bytes_in_transfer = 10'b0000001000;
+        4'b0100: bytes_in_transfer = 10'b0000010000;
+        4'b0101: bytes_in_transfer = 10'b0000100000;
+        4'b0110: bytes_in_transfer = 10'b0001000000;
+        4'b0111: bytes_in_transfer = 10'b0010000000;
+        4'b1000: bytes_in_transfer = 10'b0100000000;
+        4'b1001: bytes_in_transfer = 10'b1000000000;
+        default: bytes_in_transfer = 10'b0000000001;
+    endcase
+endfunction
+
+    //--------------------------------------
+    //  Burst type decode
+    //--------------------------------------
+AxiBurstType write_burst_type;
+
+function AxiBurstType burst_type_decode 
+(
+    input [1:0] axburst
+);
+    AxiBurstType burst_type;
+    begin
+        case (axburst)
+            2'b00    : burst_type = FIXED;
+            2'b01    : burst_type = INCR;
+            2'b10    : burst_type = WRAP;
+            2'b11    : burst_type = RESERVED;
+            default  : burst_type = INCR;
+        endcase
+        return burst_type;
+    end
+endfunction
+
+    //----------------------------------------------------
+    // Ubiquitous, familiar log2 function
+    //----------------------------------------------------
+function integer log2;
+    input integer value;
+
+    value = value - 1;        
+    for(log2 = 0; value > 0; log2 = log2 + 1)
+        value = value >> 1;
+    
+endfunction
+    //------------------------------------------------------------------------
+    // This component will read address and size and check
+    // if this is aligned or not. If not then it will align this address to the size
+    // of the transfer:
+    // Check alignment:
+    //     - With data width, can define maximun how many lower bits of address to indicate this 
+    //       address align to the size
+    //     - Ex: 32 bits data => size can be: 1, 2, 4 bytes
+    //           For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
+    //                        addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
+    //                        addr=00|01| (1)             => start addr at 1, is not aligned to size 4 byte
+    //           For 2 bytes: use last one bit to indicate algined or not
+    //                        addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
+    //                        addr=000|1| (1), 001|1| (3) => not align to 2 bytes
+    // As size runtime change, creat mask and change accordingly to size, can detect address alignment
+    // and to align to size, apply this mask with zero to the address.
+    //-------------------------------------------------------------------------     
+
+    // THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
+    // in which the first part contains the mask to check if this address aligned or not
+    //              second part contains the mast to mask address to align to size
+    
+    function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
+        input [ADDR_W-1:0] address;
+        input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
+        
+        integer            i;
+        reg [SELECT_BITS-1:0]  mask_address;
+        reg [SELECT_BITS-1:0]  check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
+        mask_address   = '1;
+        check_unaligned  = '0;
+        for(i = 0; i < SELECT_BITS ; i = i + 1) begin
+            if (i < size) begin
+                check_unaligned[i]  = address[i];
+                mask_address[i]       = 1'b0;
+            end 
+        end
+        mask_select_and_align_address   = {check_unaligned,mask_address};
+    endfunction
+
+    
+
+    reg [ADDR_W-1 : 0]     in_address;
+    reg [ADDR_W-1 : 0]     first_address_aligned;
+    reg [SIZE_W-1 : 0]     in_size;
+    reg [(SELECT_BITS*2)-1 : 0] output_masks;
+    // Extract information from  input data
+    assign in_address             = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
+    assign in_size                = in_data[SIZE_W-1 : 0];
+    
+    // Generate the masks
+    always_comb
+        begin
+            output_masks  = mask_select_and_align_address(in_address, in_size);
+        end
+    
+    // Align address if needed
+
+    generate
+        // SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
+        if (SELECT_BITS == 0)
+            assign first_address_aligned = in_address;
+        else begin
+            // SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
+            wire [SELECT_BITS-1 : 0]    aligned_address_bits;
+            if (SELECT_BITS == 1)
+                assign aligned_address_bits   = in_address[0] & output_masks[0];
+            else
+                assign aligned_address_bits   = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
+            assign first_address_aligned  = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
+        end
+    endgenerate
+    
+    
+    
+    // Increment address base on size, first address keep the same
+    generate
+        if (INCREMENT_ADDRESS)
+            begin
+                reg [ADDR_W-1 : 0] increment_address;
+                reg [ADDR_W-1 : 0] out_aligned_address_burst;
+                reg [ADDR_W-1 : 0] address_burst;
+                reg [ADDR_W-1 : 0] base_address;
+                reg [9 : 0]        number_bytes_transfer;
+                reg [ADDR_W-1 : 0] burstwrap_mask;
+                reg [ADDR_W-1 : 0] burst_address_high;
+                reg [ADDR_W-1 : 0] burst_address_low;
+                reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
+                reg [TYPE_W-1 : 0]     in_type;
+                //------------------------------------------------
+                // Use the extended burstwrap value to split the high (constant) and
+                // low (changing) part of the address
+                //-----------------------------------------------
+                assign in_type                = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
+                assign in_burstwrap_boundary  = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
+                assign burstwrap_mask         = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
+                assign burst_address_high     = out_aligned_address_burst & ~burstwrap_mask;
+                assign burst_address_low      = out_aligned_address_burst;
+                assign number_bytes_transfer  = bytes_in_transfer(in_size);
+                assign write_burst_type       = burst_type_decode(in_type);
+
+                always @*
+                    begin
+                        if (in_sop)
+                            begin
+                                out_aligned_address_burst  = in_address;
+                                base_address               = first_address_aligned;
+                            end
+                        else
+                            begin
+                                out_aligned_address_burst  = address_burst;
+                                base_address               = out_aligned_address_burst;
+                            end
+                        case (write_burst_type)
+                            INCR:
+                                increment_address  = base_address + number_bytes_transfer;
+                            WRAP:
+                                increment_address  = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
+                            FIXED:
+                                increment_address  = out_aligned_address_burst;
+                            default:
+                                increment_address  = base_address + number_bytes_transfer;
+                        endcase // case (write_burst_type)
+                    end // always @ *
+                always_ff @(posedge clk, negedge reset)
+                    begin
+                        if (!reset)
+                            begin
+                                address_burst <= '0;
+                            end
+                        else
+                            begin
+                                if (in_valid & out_ready)
+                                    address_burst <= increment_address;
+                            end
+                    end
+                // send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
+                assign   out_data  = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
+            end // if (INCREMENT_ADDRESS)
+        else
+            begin
+                assign   out_data  = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
+            end // else: !if(INCREMENT_ADDRESS)
+        
+    endgenerate
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
new file mode 100644
index 0000000..5a8b297
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv
@@ -0,0 +1,272 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
+// $Revision: #3 $
+// $Date: 2010/07/07 $
+// $Author: jyeap $
+
+/* -----------------------------------------------------------------------
+Round-robin/fixed arbitration implementation.
+
+Q: how do you find the least-significant set-bit in an n-bit binary number, X?
+
+A: M = X & (~X + 1)
+
+Example: X = 101000100
+ 101000100 & 
+ 010111011 + 1 =
+
+ 101000100 &
+ 010111100 =
+ -----------
+ 000000100
+
+The method can be generalized to find the first set-bit
+at a bit index no lower than bit-index N, simply by adding
+2**N rather than 1.
+
+
+Q: how does this relate to round-robin arbitration?
+A:
+Let X be the concatenation of all request signals.
+Let the number to be added to X (hereafter called the
+top_priority) initialize to 1, and be assigned from the
+concatenation of the previous saved-grant, left-rotated
+by one position, each time arbitration occurs.  The
+concatenation of grants is then M.
+
+Problem: consider this case:
+
+top_priority            = 010000
+request                 = 001001
+~request + top_priority = 000110
+next_grant              = 000000 <- no one is granted!
+
+There was no "set bit at a bit index no lower than bit-index 4", so 
+the result was 0.
+
+We need to propagate the carry out from (~request + top_priority) to the LSB, so
+that the sum becomes 000111, and next_grant is 000001.  This operation could be
+called a "circular add". 
+
+A bit of experimentation on the circular add reveals a significant amount of 
+delay in exiting and re-entering the carry chain - this will vary with device
+family.  Quartus also reports a combinational loop warning.  Finally, 
+Modelsim 6.3g has trouble with the expression, evaluating it to 'X'.  But 
+Modelsim _doesn't_ report a combinational loop!)
+
+An alternate solution: concatenate the request vector with itself, and OR
+corresponding bits from the top and bottom halves to determine next_grant.
+
+Example:
+
+top_priority                        =        010000
+{request, request}                  = 001001 001001
+{~request, ~request} + top_priority = 110111 000110
+result of & operation               = 000001 000000
+next_grant                          =        000001
+
+Notice that if request = 0, the sum operation will overflow, but we can ignore
+this; the next_grant result is 0 (no one granted), as you might expect.
+In the implementation, the last-granted value must be maintained as
+a non-zero value - best probably simply not to update it when no requests
+occur.
+
+----------------------------------------------------------------------- */ 
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_arbitrator
+#(
+    parameter NUM_REQUESTERS = 8,
+    // --------------------------------------
+    // Implemented schemes
+    // "round-robin"
+    // "fixed-priority"
+    // "no-arb"
+    // --------------------------------------
+    parameter SCHEME         = "round-robin",
+    parameter PIPELINE       = 0
+)
+(
+    input clk,
+    input reset,
+   
+    // --------------------------------------
+    // Requests
+    // --------------------------------------
+    input [NUM_REQUESTERS-1:0]  request,
+   
+    // --------------------------------------
+    // Grants
+    // --------------------------------------
+    output [NUM_REQUESTERS-1:0] grant,
+
+    // --------------------------------------
+    // Control Signals
+    // --------------------------------------
+    input                       increment_top_priority,
+    input                       save_top_priority
+);
+
+    // --------------------------------------
+    // Signals
+    // --------------------------------------
+    wire [NUM_REQUESTERS-1:0]   top_priority;
+    reg  [NUM_REQUESTERS-1:0]   top_priority_reg;
+    reg  [NUM_REQUESTERS-1:0]   last_grant;
+    wire [2*NUM_REQUESTERS-1:0] result;
+
+    // --------------------------------------
+    // Scheme Selection
+    // --------------------------------------
+    generate
+        if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
+            assign top_priority = top_priority_reg;
+        end
+        else begin
+            // Fixed arbitration (or single-requester corner case)
+            assign top_priority = 1'b1;
+        end
+    endgenerate
+
+    // --------------------------------------
+    // Decision Logic
+    // --------------------------------------
+    altera_merlin_arb_adder
+    #(
+        .WIDTH (2 * NUM_REQUESTERS)
+    ) 
+    adder
+    (
+        .a ({ ~request, ~request }),
+        .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
+        .sum (result)
+    );
+
+  
+    generate if (SCHEME == "no-arb") begin
+
+        // --------------------------------------
+        // No arbitration: just wire request directly to grant
+        // --------------------------------------
+        assign grant = request;
+
+    end else begin
+        // Do the math in double-vector domain
+        wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
+        assign grant_double_vector = {request, request} & result;
+
+        // --------------------------------------
+        // Extract grant from the top and bottom halves
+        // of the double vector.
+        // --------------------------------------
+        assign grant =
+            grant_double_vector[NUM_REQUESTERS - 1 : 0] |
+            grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
+
+    end
+    endgenerate
+
+    // --------------------------------------
+    // Left-rotate the last grant vector to create top_priority.
+    // --------------------------------------
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            top_priority_reg <= 1'b1;
+        end
+        else begin
+            if (PIPELINE) begin
+                if (increment_top_priority) begin
+                    top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
+                        grant[NUM_REQUESTERS-1]} : top_priority_reg;
+                end
+            end else begin
+                if (increment_top_priority) begin
+                    if (|request)
+                        top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
+                            grant[NUM_REQUESTERS-1] };
+                    else
+                        top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
+                end
+                else if (save_top_priority) begin
+                    top_priority_reg <= grant; 
+                end
+            end
+        end
+    end
+
+endmodule
+
+// ----------------------------------------------
+// Adder for the standard arbitrator
+// ----------------------------------------------
+module altera_merlin_arb_adder
+#(
+    parameter WIDTH = 8
+)
+(
+    input [WIDTH-1:0] a,
+    input [WIDTH-1:0] b,
+
+    output [WIDTH-1:0] sum
+);
+
+    wire [WIDTH:0] sum_lint;
+    // ----------------------------------------------
+    // Benchmarks indicate that for small widths, the full
+    // adder has higher fmax because synthesis can merge
+    // it with the mux, allowing partial decisions to be 
+    // made early.
+    //
+    // The magic number is 4 requesters, which means an
+    // 8 bit adder.
+    // ----------------------------------------------
+    genvar i;
+    generate if (WIDTH <= 8) begin : full_adder
+
+        wire cout[WIDTH-1:0];
+
+        assign sum[0]  = (a[0] ^ b[0]);
+        assign cout[0] = (a[0] & b[0]);
+
+        for (i = 1; i < WIDTH; i = i+1) begin : arb
+
+            assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
+            assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
+
+        end
+
+    end else begin : carry_chain
+
+        assign sum_lint = a + b;
+        assign sum = sum_lint[WIDTH-1:0];
+
+    end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv
new file mode 100644
index 0000000..4ad5243
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv
@@ -0,0 +1,261 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ns / 1 ns
+
+// -----------------------------------------------------
+// Top level for the burst adapter. This selects the
+// implementation for the adapter, based on the
+// parameterization.
+// -----------------------------------------------------
+module altera_merlin_burst_adapter
+#(
+    parameter 
+    // Indicates the implementation to instantiate:
+    //    "13.1" means the slow, inexpensive generic burst converter.
+    //    "new" means the fast, expensive per-burst converter.
+    ADAPTER_VERSION             = "13.1",
+
+    // Indicates if this adapter needs to support read bursts
+    // (almost always true).
+    COMPRESSED_READ_SUPPORT     = 1,
+
+    // Standard Merlin packet parameters that indicate
+    // field position within the packet
+    PKT_BEGIN_BURST             = 81,
+    PKT_ADDR_H                  = 79,
+    PKT_ADDR_L                  = 48,
+    PKT_BYTE_CNT_H              = 5,
+    PKT_BYTE_CNT_L              = 0,
+    PKT_BURSTWRAP_H             = 11,
+    PKT_BURSTWRAP_L             = 6,
+    PKT_TRANS_COMPRESSED_READ   = 14,
+    PKT_TRANS_WRITE             = 13,
+    PKT_TRANS_READ              = 12,
+    PKT_BYTEEN_H                = 83,
+    PKT_BYTEEN_L                = 80,
+    PKT_BURST_TYPE_H            = 88,
+    PKT_BURST_TYPE_L            = 87,
+    PKT_BURST_SIZE_H            = 86,
+    PKT_BURST_SIZE_L            = 84,
+    ST_DATA_W                   = 89,
+    ST_CHANNEL_W                = 8,
+
+    // Component-specific parameters. Explained
+    // in the implementation levels
+    IN_NARROW_SIZE              = 0,
+    NO_WRAP_SUPPORT             = 0,
+    INCOMPLETE_WRAP_SUPPORT     = 1,
+    BURSTWRAP_CONST_MASK        = 0,
+    BURSTWRAP_CONST_VALUE       = -1,
+
+    OUT_NARROW_SIZE             = 0,
+    OUT_FIXED                   = 0,
+    OUT_COMPLETE_WRAP           = 0,
+    BYTEENABLE_SYNTHESIS        = 0,
+    PIPE_INPUTS                 = 0,
+
+    OUT_BYTE_CNT_H              = 5,
+    OUT_BURSTWRAP_H             = 11
+)
+(
+    input                            clk,
+    input                            reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                            sink0_valid,
+    input [ST_DATA_W-1 : 0]          sink0_data,
+    input [ST_CHANNEL_W-1 : 0]       sink0_channel,
+    input                            sink0_startofpacket,
+    input                            sink0_endofpacket,
+    output reg                       sink0_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output wire                      source0_valid,
+    output wire [ST_DATA_W-1 : 0]    source0_data,
+    output wire [ST_CHANNEL_W-1 : 0] source0_channel,
+    output wire                      source0_startofpacket,
+    output wire                      source0_endofpacket,
+    input                            source0_ready
+);
+
+    localparam PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+
+    generate if (COMPRESSED_READ_SUPPORT == 0) begin : altera_merlin_burst_adapter_uncompressed_only
+
+        // -------------------------------------------------------------------
+        // The reduced version of the adapter is only meant to be used on
+        // non-bursting wide to narrow links.
+        // -------------------------------------------------------------------
+        altera_merlin_burst_adapter_uncompressed_only #(
+            .PKT_BYTE_CNT_H            (PKT_BYTE_CNT_H),
+            .PKT_BYTE_CNT_L            (PKT_BYTE_CNT_L),
+            .PKT_BYTEEN_H              (PKT_BYTEEN_H),
+            .PKT_BYTEEN_L              (PKT_BYTEEN_L),
+            .ST_DATA_W                 (ST_DATA_W),
+            .ST_CHANNEL_W              (ST_CHANNEL_W)
+        ) burst_adapter (
+            .clk                   (clk),
+            .reset                 (reset),
+            .sink0_valid           (sink0_valid),
+            .sink0_data            (sink0_data),
+            .sink0_channel         (sink0_channel),
+            .sink0_startofpacket   (sink0_startofpacket),
+            .sink0_endofpacket     (sink0_endofpacket),
+            .sink0_ready           (sink0_ready),
+            .source0_valid         (source0_valid),
+            .source0_data          (source0_data),
+            .source0_channel       (source0_channel),
+            .source0_startofpacket (source0_startofpacket),
+            .source0_endofpacket   (source0_endofpacket),
+            .source0_ready         (source0_ready)
+        );
+
+    end
+    else if (ADAPTER_VERSION == "13.1") begin : altera_merlin_burst_adapter_13_1
+
+        // -----------------------------------------------------
+        // This is the generic converter implementation, which attempts
+        // to convert all burst types with a generalized conversion
+        // function. This results in low area, but low fmax.
+        // -----------------------------------------------------
+        altera_merlin_burst_adapter_13_1 #(
+            .PKT_BEGIN_BURST           (PKT_BEGIN_BURST),
+            .PKT_ADDR_H                (PKT_ADDR_H ),
+            .PKT_ADDR_L                (PKT_ADDR_L),
+            .PKT_BYTE_CNT_H            (PKT_BYTE_CNT_H),
+            .PKT_BYTE_CNT_L            (PKT_BYTE_CNT_L ),
+            .PKT_BURSTWRAP_H           (PKT_BURSTWRAP_H),
+            .PKT_BURSTWRAP_L           (PKT_BURSTWRAP_L),
+            .PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
+            .PKT_TRANS_WRITE           (PKT_TRANS_WRITE),
+            .PKT_TRANS_READ            (PKT_TRANS_READ),
+            .PKT_BYTEEN_H              (PKT_BYTEEN_H),
+            .PKT_BYTEEN_L              (PKT_BYTEEN_L),
+            .PKT_BURST_TYPE_H          (PKT_BURST_TYPE_H),
+            .PKT_BURST_TYPE_L          (PKT_BURST_TYPE_L),
+            .PKT_BURST_SIZE_H          (PKT_BURST_SIZE_H),
+            .PKT_BURST_SIZE_L          (PKT_BURST_SIZE_L),
+            .IN_NARROW_SIZE            (IN_NARROW_SIZE),
+            .BYTEENABLE_SYNTHESIS      (BYTEENABLE_SYNTHESIS),
+            .OUT_NARROW_SIZE           (OUT_NARROW_SIZE),
+            .OUT_FIXED                 (OUT_FIXED),
+            .OUT_COMPLETE_WRAP         (OUT_COMPLETE_WRAP),
+            .ST_DATA_W                 (ST_DATA_W),
+            .ST_CHANNEL_W              (ST_CHANNEL_W),
+            .BURSTWRAP_CONST_MASK      (BURSTWRAP_CONST_MASK),
+            .BURSTWRAP_CONST_VALUE     (BURSTWRAP_CONST_VALUE),
+            .PIPE_INPUTS               (PIPE_INPUTS),
+            .NO_WRAP_SUPPORT           (NO_WRAP_SUPPORT),
+            .OUT_BYTE_CNT_H            (OUT_BYTE_CNT_H),
+            .OUT_BURSTWRAP_H           (OUT_BURSTWRAP_H)
+        ) burst_adapter (
+            .clk                   (clk),
+            .reset                 (reset),
+            .sink0_valid           (sink0_valid),
+            .sink0_data            (sink0_data),
+            .sink0_channel         (sink0_channel),
+            .sink0_startofpacket   (sink0_startofpacket),
+            .sink0_endofpacket     (sink0_endofpacket),
+            .sink0_ready           (sink0_ready),
+            .source0_valid         (source0_valid),
+            .source0_data          (source0_data),
+            .source0_channel       (source0_channel),
+            .source0_startofpacket (source0_startofpacket),
+            .source0_endofpacket   (source0_endofpacket),
+            .source0_ready         (source0_ready)
+        );
+
+    end
+    else begin : altera_merlin_burst_adapter_new
+
+        // -----------------------------------------------------
+        // This is the per-burst-type converter implementation. This attempts
+        // to convert bursts with specialized functions for each burst
+        // type. This typically results in higher area, but higher fmax.
+        // -----------------------------------------------------
+        altera_merlin_burst_adapter_new #(
+            .PKT_BEGIN_BURST           (PKT_BEGIN_BURST),
+            .PKT_ADDR_H                (PKT_ADDR_H ),
+            .PKT_ADDR_L                (PKT_ADDR_L),
+            .PKT_BYTE_CNT_H            (PKT_BYTE_CNT_H),
+            .PKT_BYTE_CNT_L            (PKT_BYTE_CNT_L ),
+            .PKT_BURSTWRAP_H           (PKT_BURSTWRAP_H),
+            .PKT_BURSTWRAP_L           (PKT_BURSTWRAP_L),
+            .PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ),
+            .PKT_TRANS_WRITE           (PKT_TRANS_WRITE),
+            .PKT_TRANS_READ            (PKT_TRANS_READ),
+            .PKT_BYTEEN_H              (PKT_BYTEEN_H),
+            .PKT_BYTEEN_L              (PKT_BYTEEN_L),
+            .PKT_BURST_TYPE_H          (PKT_BURST_TYPE_H),
+            .PKT_BURST_TYPE_L          (PKT_BURST_TYPE_L),
+            .PKT_BURST_SIZE_H          (PKT_BURST_SIZE_H),
+            .PKT_BURST_SIZE_L          (PKT_BURST_SIZE_L),
+            .IN_NARROW_SIZE            (IN_NARROW_SIZE),
+            .BYTEENABLE_SYNTHESIS      (BYTEENABLE_SYNTHESIS),
+            .OUT_NARROW_SIZE           (OUT_NARROW_SIZE),
+            .OUT_FIXED                 (OUT_FIXED),
+            .OUT_COMPLETE_WRAP         (OUT_COMPLETE_WRAP),
+            .ST_DATA_W                 (ST_DATA_W),
+            .ST_CHANNEL_W              (ST_CHANNEL_W),
+            .BURSTWRAP_CONST_MASK      (BURSTWRAP_CONST_MASK),
+            .BURSTWRAP_CONST_VALUE     (BURSTWRAP_CONST_VALUE),
+            .PIPE_INPUTS               (PIPE_INPUTS),
+            .NO_WRAP_SUPPORT           (NO_WRAP_SUPPORT),
+            .INCOMPLETE_WRAP_SUPPORT   (INCOMPLETE_WRAP_SUPPORT),
+            .OUT_BYTE_CNT_H            (OUT_BYTE_CNT_H),
+            .OUT_BURSTWRAP_H           (OUT_BURSTWRAP_H)
+        ) burst_adapter (
+            .clk                   (clk),
+            .reset                 (reset),
+            .sink0_valid           (sink0_valid),
+            .sink0_data            (sink0_data),
+            .sink0_channel         (sink0_channel),
+            .sink0_startofpacket   (sink0_startofpacket),
+            .sink0_endofpacket     (sink0_endofpacket),
+            .sink0_ready           (sink0_ready),
+            .source0_valid         (source0_valid),
+            .source0_data          (source0_data),
+            .source0_channel       (source0_channel),
+            .source0_startofpacket (source0_startofpacket),
+            .source0_endofpacket   (source0_endofpacket),
+            .source0_ready         (source0_ready)
+        );
+
+    end 
+    endgenerate
+
+    // synthesis translate_off
+     
+    // -----------------------------------------------------
+    // Simulation-only check for incoming burstwrap values inconsistent with 
+    // BURSTWRAP_CONST_MASK, which would indicate a paramerization error. 
+    //
+    // Should be turned into an assertion, really.
+    // -----------------------------------------------------
+    always @(posedge clk or posedge reset) begin
+        if (~reset && sink0_valid &&
+          BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] &
+          (BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L])
+        ) begin
+            $display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]);
+        end
+    end
+
+    // synthesis translate_on
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
new file mode 100644
index 0000000..1f7ce2b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
@@ -0,0 +1,1174 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $
+// $Revision: #68 $
+// $Date: 2014/01/23 $
+// $Author: wkleong $
+
+// -------------------------------------------------------
+// Merlin Burst Adapter
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// <burstwrap value> + 1
+// By definition, burstwrap values are of the form 2^n - 1; adding 1 is a non-ripple operation.
+module altera_merlin_burst_adapter_burstwrap_increment #(parameter WIDTH = 8)
+  (
+    input [WIDTH - 1:0] mask,
+    output [WIDTH - 1:0] inc
+  );
+    assign inc[0] = ~mask[0];
+
+    genvar i;
+    generate
+        for (i = 1; i < WIDTH; i = i+1) begin : burstwrap_increment_loop
+          assign inc[i] = mask[i - 1] & ~mask[i];
+        end
+    endgenerate
+endmodule
+
+module altera_merlin_burst_adapter_adder #(parameter WIDTH = 8) (
+    input cin,
+    input  [WIDTH-1 : 0] a,
+    input  [WIDTH-1 : 0] b,
+    output [WIDTH-1 : 0] sum
+  );
+
+  genvar i;
+
+  wire [WIDTH-1:0] carry;
+  assign sum[0] = a[0] ^ b[0] ^ cin;
+  assign carry[0] = a[0] & b[0] | a[0] & cin | b[0] & cin;
+
+  generate
+      for (i = 1; i < WIDTH; i = i+1) begin : full_adder_loop
+          assign sum[i] = a[i] ^ b[i] ^ carry[i-1];
+          assign carry[i] = a[i] & b[i] | a[i] & carry[i-1] | b[i] & carry[i-1];
+      end
+  endgenerate
+endmodule
+
+// a - b = a + ~b + 1
+module altera_merlin_burst_adapter_subtractor #(parameter WIDTH = 8) (
+    input  [WIDTH-1 : 0] a,
+    input  [WIDTH-1 : 0] b,
+    output [WIDTH-1 : 0] diff
+  );
+
+  altera_merlin_burst_adapter_adder #(.WIDTH (WIDTH)) subtract (
+    .cin (1'b1),
+    .a (a),
+    .b (~b),
+    .sum (diff)
+  );
+endmodule
+
+// Pipeline position:
+//   0: register module inputs
+//   1: register module output
+// I would have expected that with register retiming/duplication turned on, the
+// pipeline position parameter would have no effect.  Not so,
+// PIPELINE_POSITION=1 is significantly better than PIPELINE_POSITION=0.
+
+module altera_merlin_burst_adapter_min #(parameter PKT_BYTE_CNT_W=8, PKT_BURSTWRAP_W=8, PIPELINE_POSITION = 1)
+  (
+    input clk,
+    input reset,
+    input [PKT_BYTE_CNT_W - 1 : 0] a,
+    input [PKT_BYTE_CNT_W - 1 : 0] b,
+    input [PKT_BURSTWRAP_W - 1 : 0] c,
+    input c_enable,
+    input [PKT_BYTE_CNT_W - 1 : 0] d,
+    output reg [PKT_BYTE_CNT_W - 1 : 0] result
+  );
+
+    wire [PKT_BYTE_CNT_W : 0] ab_diff;
+    wire [PKT_BYTE_CNT_W : 0] ac_diff;
+    wire [PKT_BYTE_CNT_W : 0] bc_diff;
+    wire a_lt_b;
+    wire a_lt_c;
+    wire b_lt_c;
+
+    reg [PKT_BYTE_CNT_W - 1 : 0] a_reg;
+    reg [PKT_BYTE_CNT_W - 1 : 0] b_reg;
+    reg [PKT_BURSTWRAP_W - 1 : 0] c_reg;
+    reg c_enable_reg;
+    reg [PKT_BYTE_CNT_W - 1 : 0] d_reg;
+
+    generate
+      if (PIPELINE_POSITION == 0) begin
+        always_ff @(posedge clk or posedge reset) begin
+          if (reset) begin
+            a_reg <= '0;
+            b_reg <= '0;
+            c_reg <= '0;
+            c_enable_reg <= '0;
+            d_reg <= '0;
+          end
+          else begin
+            a_reg <= a;
+            b_reg <= b;
+            c_reg <= c;
+            c_enable_reg <= c_enable;
+            d_reg <= d;
+          end
+        end
+      end
+      else begin
+        always @* begin
+            a_reg = a;
+            b_reg = b;
+            c_reg = c;
+            c_enable_reg = c_enable;
+            d_reg = d;
+        end
+      end
+    endgenerate
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ab_sub (
+      .a ({1'b0, a_reg}),
+      .b ({1'b0, b_reg}),
+      .diff (ab_diff)
+    );
+    assign a_lt_b = ab_diff[PKT_BYTE_CNT_W];
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ac_sub (
+      .a ({1'b0, a_reg}),
+      .b ({{(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}),
+      .diff (ac_diff)
+    );
+    assign a_lt_c = ac_diff[PKT_BYTE_CNT_W];
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) bc_sub (
+      .a ({1'b0, b_reg}),
+      .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}),
+      .diff (bc_diff)
+    );
+    assign b_lt_c = bc_diff[PKT_BYTE_CNT_W];
+
+    // If d is greater than any of the values, it'll be greater than the min,
+    // certainly.  If d is greater than the min, use d.  Of course, ignore c if
+    // !c_enable.
+
+    // Note: d is "number-of-symbols", of width PKT_BYTE_CNT_W. So, a constant,
+    // and a power of 2 (until we support non-power-of-2 symbols/interface
+    // here).
+    // wire use_d = (d > a) || (d > b) || ( (d > c) && c_enable);
+    // I think there's something clever I can do with masks, but my head hurts,
+    // so try something simpler.
+    // wire use_d =
+    //   (&(~a[PKT_BYTE_CNT_W - 1:LOG2_NUMSYMBOLS])) ||
+    //   (&(~b[PKT_BYTE_CNT_W-1:LOG2_NUMSYMBOLS])) ||
+    //   ((&(~c[PKT_BURSTWRAP_W-1:LOG2_NUMSYMBOLS])) && c_enable
+    // );
+    wire [PKT_BYTE_CNT_W : 0] da_diff;
+    wire [PKT_BYTE_CNT_W : 0] db_diff;
+    wire [PKT_BYTE_CNT_W : 0] dc_diff;
+    wire d_gt_a;
+    wire d_gt_b;
+    wire d_gt_c;
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) da_sub (
+      .a ({1'b0, d_reg}),
+      .b ({1'b0, a_reg}),
+      .diff (da_diff)
+    );
+    assign d_gt_a = ~da_diff[PKT_BYTE_CNT_W];
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) db_sub (
+      .a ({1'b0, d_reg}),
+      .b ({1'b0, b_reg}),
+      .diff (db_diff)
+    );
+    assign d_gt_b = ~db_diff[PKT_BYTE_CNT_W];
+
+    altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) dc_sub (
+      .a ({1'b0, d_reg}),
+      .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}),
+      .diff (dc_diff)
+    );
+    assign d_gt_c = ~(d_reg < c_reg); // kevtan mod ~dc_diff[PKT_BYTE_CNT_W];
+
+    wire use_d = d_gt_a || d_gt_b || (d_gt_c && c_enable_reg);
+
+    wire [4:0] cmp = {a_lt_b, a_lt_c, b_lt_c, c_enable_reg, use_d};
+
+    reg [PKT_BYTE_CNT_W - 1 : 0] p1_result;
+    always @(a_reg or b_reg or c_reg or d_reg or cmp) begin
+      casex (cmp)
+        5'b00010: p1_result = c_reg;
+        5'b00110: p1_result = b_reg;
+        5'b01110: p1_result = b_reg;
+        5'b10010: p1_result = c_reg;
+        5'b11010: p1_result = a_reg;
+        5'b11110: p1_result = a_reg;
+
+        5'b00000: p1_result = b_reg;
+        5'b00100: p1_result = b_reg;
+        5'b01100: p1_result = b_reg;
+        5'b10000: p1_result = a_reg;
+        5'b11000: p1_result = a_reg;
+        5'b11100: p1_result = a_reg;
+
+        5'b????1: p1_result = d_reg;
+
+        default: p1_result = 'X; // don't-care
+      endcase
+    end
+
+    generate
+      if (PIPELINE_POSITION == 1) begin
+        always_ff @(posedge clk or posedge reset) begin
+          if (reset) begin
+            result <= '0;
+          end
+          else begin
+            result <= p1_result;
+          end
+        end
+      end
+      else begin
+        always @* begin
+          result = p1_result;
+        end
+      end
+    endgenerate
+endmodule
+
+
+module altera_merlin_burst_adapter_13_1
+#(
+  parameter // Merlin packet parameters
+    PKT_BEGIN_BURST             = 81,
+    PKT_ADDR_H                  = 79,
+    PKT_ADDR_L                  = 48,
+    PKT_BYTE_CNT_H              = 5,
+    PKT_BYTE_CNT_L              = 0,
+    PKT_BURSTWRAP_H             = 11,
+    PKT_BURSTWRAP_L             = 6,
+    PKT_TRANS_COMPRESSED_READ   = 14,
+    PKT_TRANS_WRITE             = 13,
+    PKT_TRANS_READ              = 12,
+    PKT_BYTEEN_H                = 83,
+    PKT_BYTEEN_L                = 80,
+    PKT_BURST_TYPE_H            = 88,
+    PKT_BURST_TYPE_L            = 87,
+    PKT_BURST_SIZE_H            = 86,
+    PKT_BURST_SIZE_L            = 84,
+    IN_NARROW_SIZE              = 0,
+    OUT_NARROW_SIZE             = 0,
+    OUT_FIXED                   = 0,
+    OUT_COMPLETE_WRAP           = 0,
+    ST_DATA_W                   = 89,
+    ST_CHANNEL_W                = 8,
+
+    // Component-specific parameters
+    BYTEENABLE_SYNTHESIS        = 0,
+    BURSTWRAP_CONST_MASK        = 0,
+    PIPE_INPUTS			        = 0,
+    NO_WRAP_SUPPORT		        = 0,
+    BURSTWRAP_CONST_VALUE       = -1,
+    OUT_BYTE_CNT_H              = 5,
+    OUT_BURSTWRAP_H             = 11
+)
+(
+
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink0_valid,
+    input  [ST_DATA_W-1 : 0]    sink0_data,
+    input  [ST_CHANNEL_W-1 : 0] sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output reg                  sink0_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg                      source0_valid,
+    output reg [ST_DATA_W-1    : 0] source0_data,
+    output reg [ST_CHANNEL_W-1 : 0] source0_channel,
+    output reg                      source0_startofpacket,
+    output reg                      source0_endofpacket,
+    input                           source0_ready
+);
+  localparam
+    PKT_BYTE_CNT_W          = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+    PKT_ADDR_W              = PKT_ADDR_H - PKT_ADDR_L + 1,
+    PKT_BYTEEN_W            = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+    OUT_BYTE_CNT_W          = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+    OUT_BURSTWRAP_W         = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+    PKT_BURSTWRAP_W         = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+    OUT_MAX_BYTE_CNT        = 1 << (OUT_BYTE_CNT_W - 1),
+    OUT_MAX_BURSTWRAP       = (1 << OUT_BURSTWRAP_W) - 1,
+    NUM_SYMBOLS             = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+    PKT_BURST_SIZE_W        = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1,
+    PKT_BURST_TYPE_W        = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1,
+    LOG2_NUM_SYMBOLS        = (NUM_SYMBOLS == 1) ? 1 :log2ceil(NUM_SYMBOLS);
+
+  // "min" operation on burstwrap values is a bitwise AND.
+  // Todo: one input is always set to constant OUT_MAX_BURSTWRAP; this is a
+  // number of the form 2^n.  Does this fact yield an optimization?
+  function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min(
+    input [PKT_BURSTWRAP_W - 1 : 0] a, b
+  );
+    altera_merlin_burst_adapter_burstwrap_min = a & b;
+  endfunction
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function unsigned[63:0] log2ceil;
+        input reg[63:0] val;
+        reg [63:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+  //----------------------------------------------------
+  // AXSIZE encoding: run-time  size of the transaction.
+  // ---------------------------------------------------
+  function reg[511:0] set_byteenable_based_on_size;
+      input [PKT_BURST_SIZE_W-1:0] axsize;
+           begin
+              case (axsize)
+                  4'b0000: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
+                  4'b0001: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003;
+                  4'b0010: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F;
+                  4'b0011: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF;
+                  4'b0100: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFF;
+                  4'b0101: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF;
+                  4'b0110: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF;
+                  4'b0111: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                  4'b1000: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                  4'b1001: set_byteenable_based_on_size = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                  default: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
+              endcase
+          end
+  endfunction
+
+  // ---------------------------------------------------
+  // STATE MACHINE DEFINITIONS
+  // ---------------------------------------------------
+  typedef enum bit [2:0] { // int unsigned {
+    ST_IDLE 	    = 3'b000,
+    ST_COMP_TRANS   = 3'b001,	// This state is used for compressed transactions
+				                // - Address and byte count needs to be calculated for every round internally
+    ST_UNCOMP_TRANS = 3'b010, 	// This state is used for uncompressed transaction where address is passthrough
+				                // and bytecount is decremented based on max
+    ST_UNCOMP_WR_SUBBURST = 3'b100
+  } t_state;
+  t_state state, next_state;
+
+  // ---------------------------------------------------
+  // AXI Burst Type Encoding
+  // ---------------------------------------------------
+  typedef enum bit  [1:0]
+    {
+        FIXED       = 2'b00,
+        INCR        = 2'b01,
+        WRAP        = 2'b10,
+        RESERVED    = 2'b11
+    } AxiBurstType;
+
+  // ------------------------------
+  // Note on signal naming convention used
+  // in_*		--> These signals are either coming directly from sink or a combi off the sink signals
+  //			--> Timing - zero cycle
+  // d0_in_* 	--> Signals that are to be used in this block. It is off a mux between in_* signals
+  //		    and the 'saved' version of the signals
+  //		    --> Timing - zero cycle (IF PIPE_INPUTS == 0)
+  // d1_in_*    --> Signals that are output of initial flop stage.
+  //            --> Timing - always delayed by 1 clock. (vs the input)
+
+  // ------------------------------
+  // CONSTANTS
+  // ------------------------------
+  wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig 	    = NUM_SYMBOLS		[PKT_BYTE_CNT_W - 1 : 0];
+  wire [PKT_BYTE_CNT_W - 1 : 0] out_max_byte_cnt_sig 	= OUT_MAX_BYTE_CNT	[PKT_BYTE_CNT_W - 1 : 0];
+
+  // quartus integration failure
+  wire [63:0]                       log2_numsymbols     = log2ceil(NUM_SYMBOLS);
+  wire [PKT_BURST_SIZE_W - 1 : 0]   encoded_numsymbols  = log2_numsymbols[PKT_BURST_SIZE_W-1:0];
+
+  // ---------------------------------------------------
+  // INPUT STAGE SIGNALS CONDITIONING
+  // ---------------------------------------------------
+
+  // Internal wires
+  reg [ST_DATA_W - 1 : 0 ]		d1_in_data;
+  reg [ST_CHANNEL_W - 1 : 0 ]		d1_in_channel;
+  reg [PKT_BURST_SIZE_W - 1 : 0]	d1_in_size;
+  reg [PKT_BURST_TYPE_W - 1 : 0]	d1_in_bursttype;
+  reg [PKT_BYTEEN_W - 1 : 0]		d1_in_byteen;
+  reg [PKT_BURST_SIZE_W - 1 : 0] 	d0_in_size;
+  reg [PKT_BURSTWRAP_W - 1 : 0] 	d0_in_burstwrap;
+  reg [PKT_BURST_TYPE_W - 1 : 0] 	d0_in_bursttype;
+  reg [PKT_ADDR_W - 1 : 0]	 	d0_in_addr;
+  reg [PKT_BYTE_CNT_W - 1 : 0]		d0_in_bytecount;
+  reg	d0_in_narrow;
+  reg	d0_in_passthru;
+  reg	d0_in_valid;
+  reg 	d0_in_sop;
+  reg  	d0_in_compressed_read;
+  reg  	d0_in_write;
+  reg	d0_in_uncompressed_read;
+  reg 	d1_in_eop;
+  reg	d1_in_uncompressed_read;
+  reg  	d1_in_narrow;
+  reg   d1_in_passthru;
+  reg   in_ready_hold;
+
+  reg [PKT_BYTE_CNT_W - 1 : 0] the_min_byte_cnt_or_num_sym;
+
+  wire [PKT_BURSTWRAP_W - 1 : 0] wrap_mask;
+  wire [PKT_BURSTWRAP_W - 1 : 0] incremented_wrap_mask;
+  reg disable_wrap_dist_calc;
+
+  // Input stage registers
+  reg [ST_DATA_W - 1 : 0]        in_data_reg;
+  reg [ST_CHANNEL_W-1 : 0]       in_channel_reg;
+  reg [PKT_BYTEEN_W - 1 : 0]	 in_byteen_reg;
+  reg [PKT_BURST_SIZE_W - 1 : 0] in_size_reg;
+  reg [PKT_BURSTWRAP_W - 1 : 0]  in_burstwrap_reg;
+  reg [PKT_BURST_TYPE_W - 1 : 0] in_bursttype_reg;
+  reg [PKT_ADDR_W - 1 : 0]	     in_addr_reg;
+  reg [PKT_BYTE_CNT_W - 1 : 0]	 in_bytecount_reg;
+  reg in_compressed_read_reg;
+  reg in_uncompressed_read_reg;
+  reg in_narrow_reg;		// Holds the flag until next burst command.
+  reg in_passthru_reg;		// Holds flag until next start of packet command
+  reg in_eop_reg;
+  reg in_bytecount_reg_zero;
+  reg in_write_reg;
+  reg in_valid_reg;
+  reg in_sop_reg;
+
+
+  // Length coversion
+  reg [PKT_ADDR_W - 1 : 0]     	 int_nxt_addr_reg;
+  reg [PKT_ADDR_W - 1 : 0]       int_nxt_addr_reg_dly;
+  reg [PKT_BYTE_CNT_W - 1 : 0] 	 int_bytes_remaining_reg;
+  reg [PKT_BYTE_CNT_W - 1 : 0]   out_uncomp_byte_cnt_reg;
+  reg [PKT_BURSTWRAP_W - 1 :0]	 int_dist_reg;
+  reg                            new_burst_reg;
+  reg [PKT_BYTE_CNT_W -1:0] 	int_byte_cnt_narrow_reg;
+
+  reg [PKT_ADDR_W - 1 : 0 ]     nxt_addr;
+  reg [PKT_ADDR_W - 1 : 0 ]     nxt_addr2;
+  reg [PKT_BYTE_CNT_W - 1 : 0]	nxt_byte_cnt;
+  reg [PKT_BYTE_CNT_W - 1 : 0] 	nxt_uncomp_subburst_byte_cnt;
+  reg [PKT_BYTE_CNT_W - 1 : 0]  nxt_byte_remaining;
+  reg [PKT_BURSTWRAP_W - 1 : 0] nxt_dist;
+  reg [PKT_ADDR_W - 1 : 0] 	extended_burstwrap;
+
+  reg  [PKT_BYTE_CNT_W -1 :0] d0_int_bytes_remaining;
+  reg  [PKT_ADDR_W - 1 : 0 ]  d0_int_nxt_addr;
+  reg  [PKT_BURSTWRAP_W - 1 : 0 ] d0_int_dist;
+
+  // Output registers
+  reg [PKT_ADDR_W - 1 : 0] 	out_addr_reg;
+  reg 				out_valid_reg;
+  reg 				out_sop_reg;
+  reg 				out_eop_reg;
+  reg [PKT_BURSTWRAP_W - 1 : 0] out_burstwrap_reg;
+  reg [PKT_BYTE_CNT_W - 1 : 0] 	out_byte_cnt_reg;
+  reg 				nxt_in_ready;
+
+//  wire [PKT_ADDR_W - 1 : 0]      nxt_out_addr;
+  wire                           nxt_out_valid;
+  wire                           nxt_out_sop;
+  wire                           nxt_out_eop;
+  wire [PKT_BURSTWRAP_W - 1 : 0] nxt_out_burstwrap;
+//  wire [PKT_BYTE_CNT_W - 1 : 0]  nxt_bytecount;
+
+  // ----------------
+  // ALIAS INPUT MAPPINGS
+  // -----------------
+  // cmd              PKT_TRANS_COMPRESSED_READ  PKT_TRANS_READ PKT_TRANS_WRITE
+  // read                                     0               1               0
+  // compressed read                          1               1               0
+  // write                                    0               0               1
+  // N.b. The fabric sets both PKT_TRANS_COMPRESSED_READ and PKT_TRANS_READ ???
+  wire in_compressed_read	=	sink0_data [PKT_TRANS_COMPRESSED_READ];
+  wire in_write 		    =	sink0_data [PKT_TRANS_WRITE];
+  wire in_read			    =	sink0_data [PKT_TRANS_READ];
+  wire in_uncompressed_read	=	in_read & ~sink0_data [PKT_TRANS_COMPRESSED_READ];
+
+  wire [ST_DATA_W - 1 : 0] in_data = sink0_data;
+  wire in_valid	= sink0_valid & in_ready_hold;  // Fbz143820 hold ready and internal valid to zero during reset
+  wire in_sop	= sink0_startofpacket;
+  wire in_eop	= sink0_endofpacket;
+  wire [ST_CHANNEL_W - 1 : 0] in_channel = sink0_channel;
+
+  wire [PKT_ADDR_W - 1 : 0 ]	  in_addr      = sink0_data[PKT_ADDR_H : PKT_ADDR_L];
+  wire [PKT_BYTEEN_W - 1 : 0]	  in_byteen    = sink0_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+  wire [PKT_BYTE_CNT_W - 1 : 0]	  in_bytecount = sink0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L];
+  wire [PKT_BURST_SIZE_W - 1 : 0] in_size      = IN_NARROW_SIZE ? sink0_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] : encoded_numsymbols;
+
+  // Signals decoded based on inputs
+  wire [PKT_BYTE_CNT_W - 1 : 0] in_burstcount 	= in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0];
+  wire in_narrow 	= in_size < log2_numsymbols[PKT_BYTE_CNT_W -1 :0];
+  wire in_passthru	= in_burstcount <= 16;
+
+  wire [PKT_BURST_TYPE_W - 1 : 0] in_bursttype = sink0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L];
+  wire [PKT_BURSTWRAP_W - 1 : 0]  in_burstwrap;
+
+  genvar i;
+  generate
+    for (i = 0; i < PKT_BURSTWRAP_W; i = i + 1) begin : assign_burstwrap_bit
+      if (BURSTWRAP_CONST_MASK[i]) begin
+        assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i];
+      end
+      else begin
+        assign in_burstwrap[i] = sink0_data[PKT_BURSTWRAP_L + i];
+      end
+    end
+  endgenerate
+
+  // ----------------------------------
+  // Input Load control signals
+  // ----------------------------------
+
+generate if (PIPE_INPUTS == 0)
+ begin : NON_PIPELINED_INPUTS
+
+  // Used to capture sink signals as each incoming cycle is accepted.
+  wire	load_next_cmd	= d0_in_valid & sink0_ready;
+
+  // Used to capture sink signals as each incoming transaction (currently only used by passthru generation)
+  wire	load_next_pkt	= d0_in_valid & sink0_ready & d0_in_sop;
+
+  always_ff @(posedge clk or posedge reset) begin
+	if (reset) begin
+			in_channel_reg 		<= '0;
+			in_data_reg 		<= '0;
+			in_burstwrap_reg	<= '0;
+			in_bursttype_reg	<= '0;
+			in_byteen_reg		<= '0;
+			in_narrow_reg		<= '0;
+			in_size_reg		    <= '0;
+			in_passthru_reg		<= '0;
+			in_eop_reg		    <= '0;
+			in_bytecount_reg_zero	    <= '0;
+			in_uncompressed_read_reg    <= '0;
+	end
+	else begin
+		if (load_next_cmd) begin
+			in_channel_reg 		<= in_channel;
+			in_data_reg 		<= in_data;
+			in_burstwrap_reg	<= in_burstwrap;
+			in_bursttype_reg	<= in_bursttype;
+			in_byteen_reg		<= in_byteen;
+			in_narrow_reg		<= in_narrow;
+			in_size_reg		    <= in_size;
+			in_bytecount_reg_zero	  <= ~|in_bytecount;
+			in_uncompressed_read_reg  <= in_uncompressed_read;
+            in_eop_reg                <= in_eop;
+		end
+
+		// Passthru is evaluated every transaction
+                if (load_next_pkt) begin
+                        in_passthru_reg         <= in_passthru;
+                end
+	end
+  end
+
+  assign d0_in_size 		= new_burst_reg ? in_size	: in_size_reg;
+  assign d0_in_addr 		= in_addr;
+  assign d0_in_bytecount	= in_bytecount;
+  assign d0_in_burstwrap	= new_burst_reg ? in_burstwrap 	: in_burstwrap_reg;
+  assign d0_in_bursttype	= new_burst_reg ? in_bursttype 	: in_bursttype_reg;
+  assign d0_in_narrow 		= new_burst_reg ? in_narrow	: in_narrow_reg;
+  assign d0_in_passthru		= load_next_pkt ? in_passthru	: in_passthru_reg;
+  assign d0_in_write             = in_write;
+  assign d0_in_compressed_read   = in_compressed_read;
+  assign d0_in_uncompressed_read = in_uncompressed_read;
+  assign d0_in_valid             = in_valid;
+  assign d0_in_sop               = in_sop;
+  assign d1_in_eop               = in_eop_reg;
+  assign d1_in_data              = in_data_reg;
+  assign d1_in_channel           = in_channel_reg;
+  assign d1_in_size              = in_size_reg;
+  assign d1_in_bursttype         = in_bursttype_reg;
+  assign d1_in_byteen            = in_byteen_reg;
+  assign d1_in_uncompressed_read = in_uncompressed_read_reg;
+  assign d1_in_narrow            = in_narrow_reg;
+  assign d1_in_passthru          = in_passthru_reg;
+
+ end : NON_PIPELINED_INPUTS
+
+else
+ begin : PIPELINED_INPUTS
+
+  reg [PKT_BURST_SIZE_W - 1 : 0]        d0_int_size;
+  reg [PKT_BURSTWRAP_W - 1 : 0]         d0_int_burstwrap;
+  reg [PKT_BURST_TYPE_W - 1 : 0]        d0_int_bursttype;
+  reg d0_int_narrow;
+  reg d0_int_passthru;
+
+  always_ff @(posedge clk or posedge reset) begin
+        if (reset) begin
+            in_channel_reg          <= '0;
+            in_data_reg             <= '0;
+            in_burstwrap_reg        <= '0;
+            in_bursttype_reg        <= '0;
+            in_byteen_reg           <= '0;
+            in_narrow_reg           <= '0;
+            in_size_reg             <= '0;
+            in_addr_reg             <= '0;
+            in_passthru_reg         <= '0;
+            in_eop_reg              <= '0;
+            in_bytecount_reg        <= '0;
+            in_bytecount_reg_zero   <= '0;
+            in_uncompressed_read_reg  <= '0;
+			in_write_reg		<= '0;
+			in_compressed_read_reg	<= '0;
+			in_uncompressed_read_reg <= '0;
+			in_sop_reg		<= '0;
+			in_valid_reg		<= '0;
+            d1_in_eop               <= '0;
+            d1_in_data              <= '0;
+            d1_in_channel           <= '0;
+            d1_in_size              <= '0;
+            d1_in_bursttype         <= '0;
+            d1_in_byteen            <= '0;
+            d1_in_uncompressed_read <= '0;
+            d1_in_narrow            <= '0;
+            d1_in_passthru          <= '0;
+			d0_int_size           <= '0;
+			d0_int_burstwrap      <= '0;
+			d0_int_bursttype     <= '0;
+			d0_int_narrow       <= '0;
+			d0_int_passthru   	<= '0;
+        end
+        else begin
+                if (sink0_ready & in_valid) begin
+                        in_channel_reg           <= in_channel;
+                        in_data_reg              <= in_data;
+                        in_burstwrap_reg         <= in_burstwrap;
+                        in_bursttype_reg         <= in_bursttype;
+                        in_byteen_reg            <= in_byteen;
+                        in_narrow_reg            <= in_narrow;
+                        in_size_reg              <= in_size;
+                        in_addr_reg              <= in_addr;
+                        in_bytecount_reg         <= in_bytecount;
+                        in_bytecount_reg_zero    <= ~|in_bytecount;
+                        in_uncompressed_read_reg  <= in_uncompressed_read;
+                        in_eop_reg               <= in_eop;
+                        in_write_reg             <= in_write;
+                        in_compressed_read_reg   <= in_compressed_read;
+                        in_uncompressed_read_reg <= in_uncompressed_read;
+                        in_sop_reg               <= in_sop;
+                end
+                // Passthru is evaluated every transaction
+                if (sink0_ready & in_sop & in_valid) begin
+                        in_passthru_reg         <= in_passthru;
+                end
+
+		if (sink0_ready) in_valid_reg             <= in_valid;
+
+		if ( 	( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+			( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+                        d1_in_eop               <= in_eop_reg;
+                        d1_in_data              <= in_data_reg;
+                        d1_in_channel           <= in_channel_reg;
+                        d1_in_size              <= in_size_reg;
+                        d1_in_bursttype         <= in_bursttype_reg;
+                        d1_in_byteen            <= in_byteen_reg;
+                        d1_in_uncompressed_read <= in_uncompressed_read_reg;
+                        d1_in_narrow            <= in_narrow_reg;
+                        d1_in_passthru          <= in_passthru_reg;
+		end
+
+                if (    ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                        ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+		  d0_int_size        <= in_size_reg;
+		  d0_int_burstwrap   <= in_burstwrap_reg;
+		  d0_int_bursttype   <= in_bursttype_reg;
+		  d0_int_narrow      <= in_narrow_reg;
+		  d0_int_passthru    <= in_passthru_reg;
+		end
+
+
+	end
+  end
+
+  assign d0_in_size             = new_burst_reg ? in_size_reg : d0_int_size;
+  assign d0_in_addr             = in_addr_reg;
+  assign d0_in_bytecount        = in_bytecount_reg;
+  assign d0_in_burstwrap        = new_burst_reg ? in_burstwrap_reg : d0_int_burstwrap;
+  assign d0_in_bursttype        = new_burst_reg ? in_bursttype_reg : d0_int_bursttype;
+  assign d0_in_narrow           = new_burst_reg ? in_narrow_reg : d0_int_narrow;
+  assign d0_in_passthru         = new_burst_reg ? in_passthru_reg : d0_int_passthru;
+  assign d0_in_write             = in_write_reg;
+  assign d0_in_compressed_read   = in_compressed_read_reg;
+  assign d0_in_uncompressed_read = in_uncompressed_read_reg;
+  assign d0_in_valid             = in_valid_reg;
+  assign d0_in_sop               = in_sop_reg;
+
+ end : PIPELINED_INPUTS
+endgenerate
+
+  // -------------------------------
+  // Length Calculation Input Staging.
+  // -------------------------------
+
+  reg [PKT_ADDR_W -1 : 0] 	int_nxt_addr_with_offset;
+
+  reg [PKT_BURSTWRAP_W - 1 : 0] no_wrap_dist;
+
+  // These 2 values are part of break up of calculation from pre-flop to post-flop for timing optimization
+  assign int_nxt_addr_with_offset  = int_nxt_addr_reg | extended_burstwrap & (int_nxt_addr_reg_dly + int_byte_cnt_narrow_reg);
+
+  // Unaligned address support
+  //reg [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0 ] d0_in_addr_aligned_full;
+  reg [PKT_ADDR_W + log2ceil(NUM_SYMBOLS) - 1 : 0 ] d0_in_addr_aligned_full;
+  altera_merlin_address_alignment
+    # (
+        .ADDR_W             (PKT_ADDR_W),
+        .BURSTWRAP_W        (1), // Not used in burst adapter calculation usage of this module
+        .TYPE_W             (0), // Not used in burst adapter calculation usage of this module
+        .SIZE_W             (PKT_BURST_SIZE_W),
+        .INCREMENT_ADDRESS  (0),
+        .NUMSYMBOLS        (NUM_SYMBOLS)
+        ) align_address_to_size
+        (
+            .clk(1'b0), .reset(1'b0), .in_valid(1'b0), .in_sop(1'b0), .in_eop(1'b0), .out_ready(),  // Dummy. Not used in INCREMENT_ADDRESS=0 settings
+                                                                                                    // This block is purely combi
+            .in_data    ( { d0_in_addr , d0_in_size } ),
+            .out_data   ( d0_in_addr_aligned_full )
+        );
+
+  // On start of every new burst, take in new input values for calculations
+  assign d0_int_bytes_remaining = new_burst_reg ? d0_in_bytecount: int_bytes_remaining_reg - out_byte_cnt_reg;
+  assign d0_int_nxt_addr        = new_burst_reg ? d0_in_addr_aligned_full[PKT_ADDR_W-1:0] : int_nxt_addr_with_offset;
+  assign d0_int_dist            = NO_WRAP_SUPPORT ? no_wrap_dist : incremented_wrap_mask - ( d0_int_nxt_addr[PKT_BURSTWRAP_W-1:0] & wrap_mask);
+  always_comb begin
+
+    if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave.
+      no_wrap_dist = ~nxt_out_burstwrap[PKT_BURSTWRAP_W] ? num_symbols_sig : '1;
+    end
+    else if (OUT_BURSTWRAP_W == 1) begin
+     no_wrap_dist =  ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1] ? num_symbols_sig : '1;
+    end
+    else if (LOG2_NUM_SYMBOLS <= OUT_BURSTWRAP_W) begin
+
+     no_wrap_dist = (|nxt_out_burstwrap[PKT_BURSTWRAP_W - 1: 0] &  ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1]) ?
+                    num_symbols_sig : '1;
+    end
+    else begin
+     no_wrap_dist = num_symbols_sig;
+    end
+
+  end
+
+  // -------------------------------
+  // Output Load Control Signals
+  // -------------------------------
+
+  // Used by output flops to load in next state when:
+  // 1. source has taken command (or ready to accept)
+  // 2. if no command is pending (IDLE)
+  wire	load_next_out_cmd	= source0_ready | ~source0_valid;
+  //wire  load_next_out_pkt	= (source0_ready & source0_endofpacket) | ~source0_valid;
+
+  // ---------------------------------------------------
+  // INTERMEDIATE CONTROL FLAGS / HOLDING REGISTERS
+  // ---------------------------------------------------
+
+  always_comb begin
+
+    // Default case : Always try to use the slaves max byte count. If a narrow transfer occurs, follow the masters num_symbols_sig
+    the_min_byte_cnt_or_num_sym = d0_in_narrow ? num_symbols_sig : out_max_byte_cnt_sig;
+
+
+    if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave.
+      disable_wrap_dist_calc = ~d0_in_burstwrap[OUT_BURSTWRAP_W];
+    end
+    else begin
+      if (OUT_NARROW_SIZE || OUT_FIXED || OUT_COMPLETE_WRAP) begin  //AXI Slave
+	// When burst type is "RESERVED" it means that a fix burst wide-to-narrow has occured
+	// kevtan : added highest bit of wrap mask
+        disable_wrap_dist_calc 		= (d0_in_passthru && d0_in_bursttype != RESERVED) | nxt_out_burstwrap[PKT_BURSTWRAP_W - 1];
+        the_min_byte_cnt_or_num_sym	= (d0_in_narrow   && ~d0_in_passthru && d0_in_bursttype==WRAP) ? num_symbols_sig : out_max_byte_cnt_sig;
+                                              // kevtan : Fbz140322 : in case of narrow transfer, chop to smallest if it's not passthru
+                                              //                      Calculation is messed up if narrow
+                                              //                    : added term to only chop to smallest in case of wrapping transactions
+      end
+      else if (OUT_BURSTWRAP_W == PKT_BURSTWRAP_W) begin // Sequential slave
+        disable_wrap_dist_calc = d0_in_burstwrap[PKT_BURSTWRAP_W - 1];
+      end
+      else begin
+	// Dont really have a full story here to tell "Default?"
+	// This assumes that OUT_BURSTWRAP_W < PKT_BURSTWRAP_W. Then looks at the slave's wrap boundary.
+	// If d0_in_burstwrap[OUT_BURSTWRAP_W] is set, this is sequential?
+	// If d0_in_burstwrap[OUT_BURSTWRAP_W - 1] is set, then it needs to be sequential to the slave?
+        disable_wrap_dist_calc =  ~d0_in_burstwrap[OUT_BURSTWRAP_W] & d0_in_burstwrap[OUT_BURSTWRAP_W - 1];
+      end
+    end
+  end
+
+
+  // ----------------------------------------------------
+  // FSM : Finite State Machine
+  // For handling the control signals for burst adapter.
+  // Note: Arcs in the SM will only take effect is there's no backpressurring from the source
+  // ---------------------------------------------------
+
+  always_comb begin : state_transition
+    // default
+    next_state = ST_IDLE;
+
+    case (state)
+	ST_IDLE : begin
+		next_state = ST_IDLE;
+
+		if (d0_in_valid) begin
+			if (d0_in_write | d0_in_uncompressed_read) 	next_state = ST_UNCOMP_TRANS;
+			if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
+		end
+	end
+
+	ST_UNCOMP_TRANS : begin
+		next_state = ST_UNCOMP_TRANS;
+
+		if (source0_endofpacket) begin
+			if (~d0_in_valid) next_state = ST_IDLE;
+			else begin
+                if (d0_in_write | d0_in_uncompressed_read)	next_state = ST_UNCOMP_TRANS;
+                if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
+            end
+		end
+        else begin
+            if (|nxt_uncomp_subburst_byte_cnt)   next_state = ST_UNCOMP_WR_SUBBURST;
+        end
+	end
+
+	ST_UNCOMP_WR_SUBBURST : begin
+        next_state = ST_UNCOMP_WR_SUBBURST;
+
+        if (source0_endofpacket) begin
+            if (~d0_in_valid) next_state = ST_IDLE;
+            else begin
+                if (d0_in_write | d0_in_uncompressed_read)  next_state = ST_UNCOMP_TRANS;
+                if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
+            end
+        end
+        else begin
+            if (~|nxt_uncomp_subburst_byte_cnt)	next_state = ST_UNCOMP_TRANS;
+        end
+    end
+
+	ST_COMP_TRANS : begin
+        next_state = ST_COMP_TRANS;
+
+        if (source0_endofpacket) begin
+            if (~d0_in_valid) begin
+                next_state = ST_IDLE;
+            end
+            else begin
+                if (d0_in_write | d0_in_uncompressed_read)	next_state = ST_UNCOMP_TRANS;
+                if (d0_in_compressed_read) 			next_state = ST_COMP_TRANS;
+            end
+        end
+    end
+
+  endcase
+  end
+
+  // ----------------------------------------------------
+  // FSM : Controlled output control signals
+  // ----------------------------------------------------
+
+  // in_ready is asserted when:
+  // 1. IDLE
+  // 2. COMPRESSED TRANSACTION 	 : When not being back pressured by source and sending out last cmd.
+  // 3. UNCOMPRESSED TRANSACTION : When not being back pressured by source
+
+  assign nxt_in_ready = (state == ST_COMP_TRANS) ? source0_endofpacket & source0_ready | ~source0_valid :
+			            (state == ST_UNCOMP_TRANS | state == ST_UNCOMP_WR_SUBBURST) ? source0_ready | ~source0_valid :
+			            in_ready_hold; // Fbz143820 hold ready and internal valid to zero during reset
+
+  // out_valid is asserted:
+  // 1. Following sink_valid unless in ST_COMP_TRANS, where it's always one, unless it's endofpacket.
+  assign nxt_out_valid = ((state == ST_COMP_TRANS) & ~source0_endofpacket ) ? 1'b1 : d0_in_valid;
+
+  // out_startofpacket
+  // 1. Following sink_startofpacket unless in ST_COMP_TRANS, where it's always one for first cycle before accepted.
+  assign nxt_out_sop = ( (state == ST_COMP_TRANS) & source0_ready & !new_burst_reg) ? 1'b0 : d0_in_sop;
+
+  // out_endofpacket ??
+  // Follows sink_endofpacket unless in ST_COMP_TRANS, where it is a compare of whether this is the last cycle
+  assign nxt_out_eop = (state == ST_COMP_TRANS) ? ( source0_ready? new_burst_reg : in_bytecount_reg_zero ) : d1_in_eop;
+
+
+
+  always_ff @(posedge clk or posedge reset) begin
+	if (reset) 	begin
+		state		    <= ST_IDLE;
+		out_valid_reg 	<= '0;
+		out_sop_reg 	<= '0;
+        in_ready_hold   <= '0;
+	end
+	else begin
+	if (~source0_valid | source0_ready) begin
+		state 		    <= next_state;
+		out_valid_reg	<= nxt_out_valid;
+		out_sop_reg 	<= nxt_out_sop;
+    end
+        in_ready_hold <= 1'b1;
+	end
+  end
+
+  assign sink0_ready = nxt_in_ready; // COMBI OUT??
+
+  // ---------------------------------------------------
+  // Converter
+  // ---------------------------------------------------
+
+  // ---------------------------------------------------
+  // Wrap boundary distance calculation
+  // ---------------------------------------------------
+
+  // Wrap mask takes in nxt_out_burstwrap to handle cases where there's a wrapping Avalon slave with boundary < PKT_BURSTWRAP_W
+  assign wrap_mask = disable_wrap_dist_calc ? '1 : nxt_out_burstwrap;
+
+  // Must be valid in the cycle prior to each begin-subburst, for calculating begin_subburst_byte_cnt.
+  altera_merlin_burst_adapter_burstwrap_increment #(.WIDTH (PKT_BURSTWRAP_W)) the_burstwrap_increment
+  (
+    .mask (wrap_mask),
+    .inc (incremented_wrap_mask)
+  );
+
+  // ---------------------------------------------------
+  // Length Converter
+  // ---------------------------------------------------
+
+  always_comb
+   begin : EXT_BURSTWRAP
+        extended_burstwrap  = { {(PKT_ADDR_W - PKT_BURSTWRAP_W) {d0_in_burstwrap[PKT_BURSTWRAP_W -1]}}, d0_in_burstwrap };
+   end
+
+  altera_merlin_burst_adapter_min #(
+    .PKT_BYTE_CNT_W (PKT_BYTE_CNT_W),
+    .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W),
+    .PIPELINE_POSITION (2) // NO PIPELINE (ALL COMBI)
+    )
+   the_min (
+    .clk (clk),
+    .reset (reset),
+    .a (d0_int_bytes_remaining),
+    .b (the_min_byte_cnt_or_num_sym),
+    .c (d0_int_dist),
+    .c_enable (~wrap_mask[PKT_BURSTWRAP_W - 1]),
+    .d (num_symbols_sig),
+    .result (nxt_byte_cnt)
+  );
+
+// synthesis translate_off
+
+// TEMP ASSERTION FOR OWN CHECKING
+//always @(posedge clk or posedge reset) begin
+//        if (~reset && in_bursttype==WRAP && sink0_valid && sink0_ready && NO_WRAP_SUPPORT==1) begin
+//        	$display ("SELF_CHK: WRAP transaction seen in no wrap support settings");
+//	end
+//end
+
+// synthesis translate_on
+
+  // ---------------------------------------
+  // Next Address Calculation
+  // ---------------------------------------
+  always_comb
+   begin : NXT_ADDR_CALC
+
+ 	 nxt_addr  = d0_int_nxt_addr & ~extended_burstwrap;
+	 // this part of calculation is moved to post flop (nxt_addr2 = (extended_burstwrap & (d0_int_nxt_addr + nxt_byte_cnt_narrow));
+
+   end
+
+  // ---------------------------------------
+  // Length Converter Registers
+  // ---------------------------------------
+  always_ff @(posedge clk or posedge reset) begin
+	if (reset) begin
+		out_byte_cnt_reg	    <= '0;
+		int_byte_cnt_narrow_reg <= '0;
+		int_bytes_remaining_reg	<= '0;
+		int_nxt_addr_reg	    <= '0;
+        int_nxt_addr_reg_dly    <= '0;
+		new_burst_reg		    <= '0;
+		out_addr_reg		    <= '0;
+	end
+	else begin
+	   if (load_next_out_cmd) begin
+        out_byte_cnt_reg        <= nxt_byte_cnt;
+        int_byte_cnt_narrow_reg <= (nxt_byte_cnt >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0]) << d0_in_size;
+        int_bytes_remaining_reg	<= d0_int_bytes_remaining;
+        int_nxt_addr_reg        <= nxt_addr;
+        int_nxt_addr_reg_dly    <= d0_int_nxt_addr;
+        // New burst is when next byte count is equal to bytes remaining. (Used only in COMPRESSED transaction)
+        new_burst_reg           <= (nxt_byte_cnt == d0_int_bytes_remaining) | next_state != ST_COMP_TRANS;
+        // Initial address and non-COMPRESSED transaction address does not use offset.
+        out_addr_reg		    <= new_burst_reg ? d0_in_addr : int_nxt_addr_with_offset;
+	   end
+	end
+  end
+
+ // ----------------------------------------------------
+ // Uncompressed transaction calculations
+ // Address 	: No changes, just pass through (handled in the flop in for out_addr_reg) // Make it to the output?
+ // Byte count 	: For reads, this will be just the num_symbols_sig
+ // 		    : For writes, it will need to decrement for subsequent reads unless it's 0,
+ //               in which the next calculated byte count is used.
+ // ----------------------------------------------------
+
+  always_comb
+	begin : UNCOMPRESSED_SUBBURST_BYTE_CNT_CALC
+
+	// During start of uncompressed transaction, load the nxt_uncomp_subburst_byte_cnt with the "current output byte count - num_symbols_sig"
+	// After that, on subsequent cycles, load in the 'saved' byte count value - num_symbols_sig
+	// This signal is used also for transition of the state machine to ensure we will reload the byte count with the results from
+	// length converter if we decremented to zero.
+	// In essence, the wrap boundary is still observed and maintained. [Hence the use of the current output byte count when in ST_UNCOMP_TRANS.
+
+	nxt_uncomp_subburst_byte_cnt  =
+		(state == ST_UNCOMP_TRANS) ?
+			( (source0_valid & source0_ready) ? out_byte_cnt_reg - num_symbols_sig : out_uncomp_byte_cnt_reg ) :
+			out_uncomp_byte_cnt_reg - ( (source0_valid & source0_ready)? num_symbols_sig : '0)  ;
+
+   end
+
+  always_ff @(posedge clk or posedge reset) begin
+    if (reset) begin
+		out_uncomp_byte_cnt_reg	<= '0;
+    end
+    else begin
+	if (load_next_out_cmd) begin
+		out_uncomp_byte_cnt_reg <= nxt_uncomp_subburst_byte_cnt;
+	end
+    end
+  end
+
+  // ---------------------------------------------------
+  // Burst Type Generation
+  // AXI/Avalon masters - Avalon slave	- This is pass through from packet to slave
+  // AXI/Avalon masters - AXI slave		- It will always be converted to INCR type
+  // ---------------------------------------------------
+  reg [PKT_BURST_TYPE_W - 1 : 0 ] out_bursttype;
+
+  // bursttype will switch to INCR if repeated wraps detected (NOTE: ??)
+  assign out_bursttype = ((d1_in_bursttype == RESERVED)| (~d1_in_passthru & OUT_NARROW_SIZE)) ? INCR : d1_in_bursttype;
+
+  // ---------------------------------------------------
+  // Burst Wrap Generation
+  // Burst wrap is taken to be just the MIN between OUT_MAX_BURSTWRAP and the input burstwrap
+  // This is to handle cases where the slave's wrapping boundary is different from the master's
+  // Essentially, the master transaction characteristics are honored, but the burst wrap is modified.
+  // (Arguably, this can be handled by the slave)
+  // NOTE: Internally, this is used to generate the wrap_mask, so to calculate the correct wrapping distance.
+  // ---------------------------------------------------
+
+  assign nxt_out_burstwrap = altera_merlin_burst_adapter_burstwrap_min(OUT_MAX_BURSTWRAP, d0_in_burstwrap);
+
+  always_ff @(posedge clk or posedge reset) begin
+        if (reset) 	out_burstwrap_reg <= '0;
+        else
+                if (    ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                        ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+		out_burstwrap_reg <= nxt_out_burstwrap;
+		end
+  end
+
+  // ---------------------------------------------------
+  // Byte enable generation
+  // Follow unless : in compressed transaction.
+  // ---------------------------------------------------
+  reg  [LOG2_NUM_SYMBOLS - 1 : 0 ] out_addr_masked;
+  wire [511:0 ] d1_initial_byteen = set_byteenable_based_on_size(d1_in_size);   // To fix quartus integration error.
+                                                                                // Unused bits are expected to be synthesized away
+  reg  [PKT_BYTEEN_W - 1 : 0 ] out_byteen;
+
+  // Unaligned address changes.
+  // NOTE : Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address.
+  //                     Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle)
+    always_ff @(posedge clk or posedge reset) begin
+        if (reset)                  out_addr_masked <= '0;
+        else
+            if (load_next_out_cmd)  out_addr_masked <= new_burst_reg ? d0_in_addr_aligned_full[LOG2_NUM_SYMBOLS-1:0] : int_nxt_addr_with_offset[LOG2_NUM_SYMBOLS-1:0];
+    end
+
+  always_comb begin
+	if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS) )
+		out_byteen 	= d1_initial_byteen [NUM_SYMBOLS-1:0] << out_addr_masked;
+	else
+		out_byteen	= d1_in_byteen;
+  end
+
+
+  // ---------------------------------------------------
+  // Mapping of output signals. This will help to see what is comb out or flop out
+  // ---------------------------------------------------
+
+  always_comb begin : source0_out_assignments
+
+	source0_valid		    = out_valid_reg;
+	source0_startofpacket	= out_sop_reg;
+	source0_endofpacket	    = nxt_out_eop; 	// COMBI
+
+	// Generic assign to all data
+	source0_data 	= d1_in_data;
+    source0_channel = d1_in_channel;
+
+    	// Override fields the component is aware of.
+    	source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] 		= d1_in_uncompressed_read ? num_symbols_sig :
+                                                              (state == ST_UNCOMP_WR_SUBBURST) ? out_uncomp_byte_cnt_reg :
+                                                              out_byte_cnt_reg; // COMBI
+    	source0_data[PKT_ADDR_H : PKT_ADDR_L]               = out_addr_reg;
+    	source0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]     = out_burstwrap_reg;
+    	source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]   = out_bursttype;	// COMBI
+    	source0_data[PKT_BYTEEN_H: PKT_BYTEEN_L]            = out_byteen;		// COMBI
+  end
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv
new file mode 100644
index 0000000..1abaa13
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv
@@ -0,0 +1,1890 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_merlin_burst_adapter_new.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+// -------------------------------------------------------------------
+// Merlin Burst Adapter: converts incoming burst packets to fit slave burst
+// capabilities. 
+// -------------------------------------------------------------------
+module altera_merlin_burst_adapter_new
+#(
+    parameter 
+    // Standard merlin packet parameters that indicate
+    // field position within the packet
+    PKT_BEGIN_BURST             = 81,
+    PKT_ADDR_H                  = 79,
+    PKT_ADDR_L                  = 48,
+    PKT_BYTE_CNT_H              = 5,
+    PKT_BYTE_CNT_L              = 0,
+    PKT_BURSTWRAP_H             = 11,
+    PKT_BURSTWRAP_L             = 6,
+    PKT_TRANS_COMPRESSED_READ   = 14,
+    PKT_TRANS_WRITE             = 13,
+    PKT_TRANS_READ              = 12,
+    PKT_BYTEEN_H                = 83,
+    PKT_BYTEEN_L                = 80,
+    PKT_BURST_TYPE_H            = 88,
+    PKT_BURST_TYPE_L            = 87,
+    PKT_BURST_SIZE_H            = 86,
+    PKT_BURST_SIZE_L            = 84,
+    ST_DATA_W                   = 89,
+    ST_CHANNEL_W                = 8,
+
+    // The values here are used to infer the slave's maximum
+    // burst count and constant wrapping boundary (if it exists)
+    OUT_BYTE_CNT_H              = 5,
+    OUT_BURSTWRAP_H             = 11,
+
+    // Indicates if incoming packets can have sizes less
+    // than the data width
+    IN_NARROW_SIZE              = 0,
+
+    // Indicates if the endpoint slave can accept packets
+    // with sizes less than the data width
+    OUT_NARROW_SIZE             = 0,
+
+    // Indicates if the endpoint slave can accept fixed bursts
+    OUT_FIXED                   = 0,
+
+    // Indicates if the endpoint slave can accept wrap bursts
+    OUT_COMPLETE_WRAP           = 0,
+
+    // Enables byteenable synthesis, used to convert size to
+    // byteenables
+    BYTEENABLE_SYNTHESIS        = 0,
+
+    // A mask that indicates which bits of the burstwrap field are
+    // constant. Used for optimization purposes.
+    BURSTWRAP_CONST_MASK        = 0,
+
+    // Indicates the value of burstwrap bits that are constant when
+    // used with BURSTWRAP_CONST_MASK
+    BURSTWRAP_CONST_VALUE       = -1,
+
+    // Controls wrapping support. For optimization purposes.
+    NO_WRAP_SUPPORT             = 0,
+    INCOMPLETE_WRAP_SUPPORT     = 1,
+
+    // Pipelining options
+    PIPE_INPUTS                 = 0,
+    PIPE_INTERNAL               = 0
+)
+(
+    input                           clk,
+    input                           reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                           sink0_valid,
+    input [ST_DATA_W    - 1 : 0]    sink0_data,
+    input [ST_CHANNEL_W - 1 : 0]    sink0_channel,
+    input                           sink0_startofpacket,
+    input                           sink0_endofpacket,
+    output reg                      sink0_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg                        source0_valid,
+    output reg [ST_DATA_W    - 1 : 0] source0_data,
+    output reg [ST_CHANNEL_W - 1 : 0] source0_channel,
+    output reg                        source0_startofpacket,
+    output reg                        source0_endofpacket,
+    input                             source0_ready
+);
+
+    // Widths of various fields in the packet
+    localparam
+    PKT_BYTE_CNT_W        = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+    PKT_ADDR_W            = PKT_ADDR_H - PKT_ADDR_L + 1,
+    PKT_BYTEEN_W          = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+    OUT_BYTE_CNT_W        = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+    OUT_BURSTWRAP_W       = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+    PKT_BURSTWRAP_W       = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+    PKT_BURST_SIZE_W      = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1,
+    PKT_BURST_TYPE_W      = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1;
+
+    localparam
+    NUM_SYMBOLS           = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+    LOG2_NUM_SYMBOLS      = log2ceil(NUM_SYMBOLS),
+    ADDR_MASK_SEL         = (NUM_SYMBOLS == 1) ? 1 : log2ceil(NUM_SYMBOLS);
+    
+    // We try to keep everything in terms of words (transfers) instead of
+    // bytes in this implementation. Cognitive ease!
+    localparam
+    IN_LEN_W              = PKT_BYTE_CNT_W - LOG2_NUM_SYMBOLS,
+    MAX_IN_LEN            = 1 << (IN_LEN_W - 1),
+    OUT_LEN_W             = OUT_BYTE_CNT_W - LOG2_NUM_SYMBOLS,
+    MAX_OUT_LEN           = 1 << (OUT_LEN_W - 1),
+
+    BNDRY_WIDTH           = PKT_BURSTWRAP_W,
+    OUT_BOUNDARY          = MAX_OUT_LEN * NUM_SYMBOLS,
+    BYTE_TO_WORD_SHIFT    = log2ceil(NUM_SYMBOLS),
+    BYTE_TO_WORD_SHIFT_W  = log2ceil(BYTE_TO_WORD_SHIFT) + 1;
+
+    // Determines the protocol from the features that are enabled or disabled.
+    // Should be moved to the code that parameterizes this adapter.
+    localparam
+    AXI_SLAVE             = OUT_FIXED & OUT_NARROW_SIZE & OUT_COMPLETE_WRAP,
+    IS_WRAP_AVALON_SLAVE  = !AXI_SLAVE & (PKT_BURSTWRAP_H != OUT_BURSTWRAP_H),
+    IS_INCR_SLAVE         = !AXI_SLAVE & !IS_WRAP_AVALON_SLAVE,
+    NON_BURSTING_SLAVE    = (MAX_OUT_LEN == 1),
+    // This parameter indicates that the system is purely INCR avalon master/slave
+    INCR_AVALON_SYS       = IS_INCR_SLAVE && (PKT_BURSTWRAP_W == 1) && (OUT_BURSTWRAP_W == 1) && (IN_NARROW_SIZE == 0);
+
+    // ---------------------------------------------------
+    // State definitions
+    // ---------------------------------------------------
+    typedef enum bit [1:0] {
+
+        // The idle state.
+        ST_IDLE         = 2'b00,
+
+        // Adapter enters this state when the converters accept a compressed 
+        // transaction (read). Address and burst length is calculated 
+        // for every output transfer.
+        ST_COMP_TRANS   = 2'b01,
+
+        // Adapter enters this state when the converters accept uncompressed 
+        // transactions (writes, generally). Address is passed through and 
+        // burst length is decremented according to the conventions of the
+        // packet format.
+        ST_UNCOMP_TRANS = 2'b10
+    } t_state;
+
+    t_state state, next_state;
+
+    // ---------------------------------------------------
+    // Merlin packet burst type encoding
+    // ---------------------------------------------------
+    typedef enum bit[1:0]
+    {
+        FIXED       = 2'b00,
+        INCR        = 2'b01,
+        WRAP        = 2'b10,
+        REP_WRAP    = 2'b11
+    } BurstType;
+
+    // ---------------------------------------------------
+    // Here we go!
+    //
+    // An optional input pipeline stage. We typically do not use this
+    // because the interconnect allows users to add pipelines just
+    // before the burst adapter inputs.
+    //
+    // Signal prefix entering this stage: sink0_*
+    // Signal prefix exiting this stage: sink0_pipe_*
+    // ---------------------------------------------------
+    wire                         sink0_pipe_valid;
+    wire [ST_DATA_W    - 1 : 0]  sink0_pipe_data;
+    wire [ST_CHANNEL_W - 1 : 0]  sink0_pipe_channel;
+    wire                         sink0_pipe_sop;
+    wire                         sink0_pipe_eop;
+    wire                         sink0_pipe_ready;
+
+    generate
+    if (PIPE_INPUTS == 1) begin : input_pipeline
+        altera_avalon_st_pipeline_stage #(
+            .SYMBOLS_PER_BEAT (1),
+            .BITS_PER_SYMBOL  (ST_DATA_W),
+            .USE_PACKETS      (1),
+            .USE_EMPTY        (0),
+            .EMPTY_WIDTH      (0),
+            .CHANNEL_WIDTH    (ST_CHANNEL_W),
+            .PACKET_WIDTH     (2),
+            .ERROR_WIDTH      (0),
+            .PIPELINE_READY   (1)
+        ) input_pipe (
+            .clk               (clk),
+            .reset             (reset),
+
+            .in_ready          (sink0_ready),
+            .in_valid          (sink0_valid),
+            .in_startofpacket  (sink0_startofpacket),
+            .in_endofpacket    (sink0_endofpacket),
+            .in_data           (sink0_data),
+            .in_channel        (sink0_channel),
+
+            .out_ready         (sink0_pipe_ready),
+            .out_valid         (sink0_pipe_valid),
+            .out_startofpacket (sink0_pipe_sop),
+            .out_endofpacket   (sink0_pipe_eop),
+            .out_data          (sink0_pipe_data),
+            .out_channel       (sink0_pipe_channel),
+
+            .in_empty          (1'b0),
+            .in_error          (1'b0),
+            .out_empty         (),
+            .out_error         ()
+        );
+    end
+    else begin : no_input_pipeline
+
+        assign sink0_pipe_valid   = sink0_valid;
+        assign sink0_pipe_data    = sink0_data;
+        assign sink0_pipe_channel = sink0_channel;
+        assign sink0_pipe_sop     = sink0_startofpacket;
+        assign sink0_pipe_eop     = sink0_endofpacket;
+        assign sink0_ready        = sink0_pipe_ready;
+
+    end 
+    endgenerate
+
+    // --------------------------------------------------
+    // Signal extraction stage. We extract signals from
+    // the packet payload and compute some values.
+    //
+    // Signal prefix entering this stage: sink0_pipe_*
+    // Signal prefix exiting this stage: in_*
+    // --------------------------------------------------
+    wire [PKT_BURST_TYPE_W - 1 : 0]  in_bursttype         = sink0_pipe_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L];
+    wire [PKT_BYTE_CNT_W   - 1 : 0]  in_bytecount         = sink0_pipe_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L];
+    wire [PKT_ADDR_W       - 1 : 0]  in_addr              = sink0_pipe_data[PKT_ADDR_H : PKT_ADDR_L];
+    wire [63 : 0]                    log2_numsymbols      = log2ceil(NUM_SYMBOLS);
+    wire [PKT_BYTE_CNT_W   - 1 : 0]  in_burstcount        = in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0];
+    wire [IN_LEN_W         - 1 : 0]  in_len               = in_burstcount[IN_LEN_W - 1 : 0];
+    wire [PKT_BURST_SIZE_W - 1 : 0]  in_size              = sink0_pipe_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L];
+    wire                             in_write             = sink0_pipe_data[PKT_TRANS_WRITE];
+    wire                             in_compressed_read   = sink0_pipe_data[PKT_TRANS_COMPRESSED_READ];
+    wire                             in_read              = sink0_pipe_data[PKT_TRANS_READ];
+    wire                             in_uncompressed_read = in_read & ~sink0_pipe_data[PKT_TRANS_COMPRESSED_READ];
+    wire                             in_sop               = sink0_pipe_sop;
+    wire                             in_eop               = sink0_pipe_eop;
+    wire [PKT_BYTEEN_W     - 1 : 0]  in_byteen            = sink0_pipe_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+    wire                             in_passthru          = in_burstcount <= 16;
+
+    wire                             in_valid;
+    reg                              in_ready_hold;
+    wire                             in_narrow;
+    wire [PKT_BURSTWRAP_W  - 1 : 0]  in_burstwrap;
+    wire [PKT_ADDR_W       - 1 : 0]  in_aligned_addr;
+    wire [PKT_BURSTWRAP_W  - 1 : 0]  in_boundary;
+
+    // Used to keep ready low during reset
+    always_ff @(posedge clk or posedge reset) begin
+        if (reset) begin
+            in_ready_hold <= '0;
+        end else begin
+            in_ready_hold <= '1;
+        end
+    end
+
+    assign in_valid = sink0_pipe_valid & in_ready_hold;
+    assign in_narrow = in_size < log2_numsymbols[PKT_BYTE_CNT_W - 1 : 0];
+
+    // Optimization: extract burstwrap, and drive the constant bits to
+    // their constant values to help the synthesis tool.
+    genvar i;
+    generate
+        for (i = 0; i < PKT_BURSTWRAP_W; i = i+1) begin: assign_burstwrap_bit
+            if (BURSTWRAP_CONST_MASK[i]) begin
+                assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i];
+            end
+            else begin
+                assign in_burstwrap[i] = sink0_pipe_data[PKT_BURSTWRAP_L + i];
+            end
+        end
+    endgenerate
+
+    // Addresses in the packet can be unaligned. Here we align the address
+    // for ease of internal calculations. The initial output address may
+    // still be unaligned to preserve the original transaction intention.
+    
+    wire [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0] out_mask_and_aligned_addr;
+    altera_merlin_address_alignment
+    #(
+        .ADDR_W             (PKT_ADDR_W),
+        .BURSTWRAP_W        (1), // unused because we just want to align address
+        .TYPE_W             (0), // unused because we just want to align address
+        .SIZE_W             (PKT_BURST_SIZE_W),
+        .INCREMENT_ADDRESS  (0),
+        .NUMSYMBOLS         (NUM_SYMBOLS)
+    ) align_address_to_size
+    (
+        // Not used when INCREMENT_ADDRESS = 0
+        .clk       (1'b0), 
+        .reset     (1'b0), 
+        .in_valid  (1'b0), 
+        .in_sop    (1'b0), 
+        .in_eop    (1'b0), 
+        .out_ready (),
+
+        .in_data   ({ in_addr, in_size }),
+        .out_data  (out_mask_and_aligned_addr)
+    );
+
+    assign in_aligned_addr = out_mask_and_aligned_addr[PKT_ADDR_W - 1 : 0];
+
+    // Incrementing the burstwrap provides the wrapping boundary for
+    // wrapping transactions.
+    altera_merlin_burst_adapter_burstwrap_increment 
+    #(
+        .WIDTH (PKT_BURSTWRAP_W)
+    ) the_burstwrap_increment
+    (
+        .mask (in_burstwrap),
+        .inc  (in_boundary)
+    );
+
+    localparam OUT_BNDRY_ADDR_SEL_W = log2ceil(OUT_BOUNDARY);
+    localparam OUT_BOUNDARY_WIDTH   = OUT_BNDRY_ADDR_SEL_W + 1;
+
+    // address to use for distance calculations when the transaction
+    // boundary is less than the slave's wrapping boundary.
+    wire [PKT_ADDR_W           - 1 : 0]     in_bndry_addr_sel;
+
+    // the length (in words) to the transaction boundary (if it exists)
+    wire [IN_LEN_W             - 1 : 0]     len_to_in_bndry;
+
+    // the length (in words) to the slave's boundary (if it exists)
+    wire [OUT_BOUNDARY_WIDTH   - 1 : 0]     len_to_out_bndry;
+
+    reg  [IN_LEN_W             - 1 : 0]     first_len;
+    wire [BYTE_TO_WORD_SHIFT_W - 1 : 0]     byte_to_word_shift;
+    assign byte_to_word_shift = BYTE_TO_WORD_SHIFT[BYTE_TO_WORD_SHIFT_W - 1 : 0];
+
+    // This part calculates the length that is required to align the burst to
+    // the transaction's wrapping boundary (if it exists), or to the slave's
+    // wrapping boundary (if it exists). We pre-compute this ahead of the
+    // converters to minimize the logic loops in determining the output
+    // burst lengths. Note that incoming addresses for wrapping transactions
+    // are always aligned to size by definition.
+
+    assign in_bndry_addr_sel = in_addr & in_burstwrap;
+    assign len_to_in_bndry = (in_boundary - in_bndry_addr_sel) >> byte_to_word_shift;
+    
+    generate
+
+        if (OUT_BNDRY_ADDR_SEL_W > 0) begin : len_to_out_bndry_calc
+            wire [OUT_BNDRY_ADDR_SEL_W - 1 : 0] out_bndry_addr_sel;
+
+            // We have to use the aligned address, because this part may
+            // handle incoming incrementing bursts which can be unaligned.
+            assign out_bndry_addr_sel = in_aligned_addr[OUT_BNDRY_ADDR_SEL_W - 1 : 0];
+            assign len_to_out_bndry   = (OUT_BOUNDARY - out_bndry_addr_sel) >> byte_to_word_shift;
+        end 
+        
+        // A nonsensical corner-case of a wrapping slave with 
+        // MAX_OUT_LEN = 1, NUM_SYMBOLS = 1
+        else begin : len_to_out_bndry_calc_corner
+            assign len_to_out_bndry = OUT_BOUNDARY >> byte_to_word_shift;
+        end
+
+    endgenerate
+
+    // --------------------------------------------------
+    // Optional internal pipeline stage. 
+    //
+    // Note that we still buffer the transfer if the pipeline stage is 
+    // unused, because the adapter must accept read transactions before 
+    // converting them. Failure to do this will lead to masters receiving 
+    // responses before their commands have been accepted in unpipelined 
+    // systems. The buffering registers are named in_*_reg.
+    //
+    // Notes on signal naming convention used:
+    //
+    // in_*       --> These signals are coming directly from the previous stage.
+    //            --> Timing - zero cycle delta
+    // d0_in_*    --> Signals that are outputs of this stage.
+    //            --> Timing - zero cycle delta (IF PIPE_INTERNAL == 0) else 1 clock
+    // d1_in_*    --> Signals that are outputs of this stage.
+    //            --> Timing - always delayed by 1 clock. (vs the input)
+    // --------------------------------------------------
+    reg                             in_sop_reg;
+    reg                             in_eop_reg;
+    reg                             in_valid_reg;
+    reg                             in_compressed_read_reg;
+    reg                             in_uncompressed_read_reg;
+    reg                             in_write_reg;
+    reg                             in_passthru_reg;
+    reg [PKT_BURST_SIZE_W - 1 : 0]  in_size_reg;
+    reg [ST_DATA_W        - 1 : 0]  in_data_reg;
+    reg [ST_CHANNEL_W     - 1 : 0]  in_channel_reg;
+    reg [PKT_BURST_TYPE_W - 1 : 0]  in_bursttype_reg;
+    reg [PKT_BURSTWRAP_W  - 1 : 0]  in_burstwrap_reg;
+    reg [PKT_BYTEEN_W     - 1 : 0]  in_byteen_reg;
+    reg [PKT_ADDR_W       - 1 : 0]  in_addr_reg;
+    reg [PKT_ADDR_W       - 1 : 0]  in_aligned_addr_reg;
+    reg [IN_LEN_W         - 1 : 0]  in_len_reg;
+    reg                             in_narrow_reg;
+
+    reg [PKT_ADDR_W       - 1 : 0]  d0_in_addr;
+    reg [PKT_ADDR_W       - 1 : 0]  d0_in_aligned_addr;
+    reg                             d0_in_sop;
+    reg                             d0_in_compressed_read;
+    reg                             d0_in_uncompressed_read;
+    reg                             d0_in_write;
+    reg [PKT_BURST_TYPE_W - 1 : 0]  d0_in_bursttype;
+    reg [PKT_BURSTWRAP_W  - 1 : 0]  d0_in_burstwrap;
+    reg [PKT_BURSTWRAP_W  - 1 : 0]  d0_in_burstwrap_value;
+    reg [PKT_BURST_SIZE_W - 1 : 0]  d0_in_size;
+    reg [PKT_BURST_SIZE_W - 1 : 0]  d0_in_size_value;
+    reg [IN_LEN_W         - 1 : 0]  d0_in_len;
+    reg                             d0_in_valid;
+        
+    reg                             d1_in_narrow;
+    reg [PKT_ADDR_W       - 1 : 0]  d1_in_aligned_addr;
+    reg                             d1_in_eop;
+    reg                             d1_in_compressed_read;
+    reg                             d1_in_uncompressed_read;
+    reg [ST_DATA_W        - 1 : 0]  d1_in_data;
+    reg [ST_CHANNEL_W     - 1 : 0]  d1_in_channel;
+    reg                             d1_in_write;
+    reg [PKT_BURST_TYPE_W - 1 : 0]  d1_in_bursttype;
+    reg [PKT_BURSTWRAP_W  - 1 : 0]  d1_in_burstwrap;
+    reg                             d1_in_passthru;
+    reg [PKT_BURST_SIZE_W - 1 : 0]  d1_in_size;
+    reg [PKT_BYTEEN_W     - 1 : 0]  d1_in_byteen;
+
+    reg                             nb;
+
+    generate
+        if (PIPE_INTERNAL == 0) begin : no_internal_pipeline
+
+            always_ff @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    in_eop_reg               <= '0;
+                    in_compressed_read_reg   <= '0;
+                    in_uncompressed_read_reg <= '0;
+                    in_data_reg              <= '0;
+                    in_channel_reg           <= '0;
+                    in_write_reg             <= '0;
+                    in_bursttype_reg         <= '0;
+                    in_burstwrap_reg         <= '0;
+                    in_passthru_reg          <= '0;
+                    in_size_reg              <= '0;
+                    in_byteen_reg            <= '0;
+                    in_aligned_addr_reg      <= '0;
+                    in_narrow_reg            <= '0;
+                end else begin
+                    if (sink0_pipe_valid & sink0_pipe_ready) begin
+                        in_eop_reg               <= in_eop;
+                        in_data_reg              <= sink0_pipe_data;
+                        in_channel_reg           <= sink0_pipe_channel;
+                        in_compressed_read_reg   <= in_compressed_read;
+                        in_uncompressed_read_reg <= in_uncompressed_read;
+                        in_write_reg             <= in_write;
+                        in_bursttype_reg         <= in_bursttype;
+                        in_burstwrap_reg         <= in_burstwrap;
+                        in_size_reg              <= in_size;
+                        in_byteen_reg            <= in_byteen;
+                        in_aligned_addr_reg      <= in_aligned_addr;
+                        in_narrow_reg            <= in_narrow;
+                    end
+                    // length changes during packets, so sample
+                    // length-dependent signals at the start
+                    if (sink0_pipe_valid & sink0_pipe_ready & in_sop) begin
+                        in_passthru_reg <= in_passthru;
+                    end
+                end // else: !if(reset)
+            end // always_ff @
+
+            always_comb begin
+                d0_in_sop                = in_sop;
+                d0_in_compressed_read    = in_compressed_read;
+                d0_in_uncompressed_read  = in_uncompressed_read;
+                d0_in_write              = in_write;
+                d0_in_burstwrap          = in_burstwrap;
+                d0_in_size               = in_size;
+                d0_in_addr               = in_addr;
+                d0_in_aligned_addr       = in_aligned_addr;
+                d0_in_len                = in_len;
+                d0_in_valid              = in_valid;
+
+                d1_in_eop                = in_eop_reg;
+                d1_in_compressed_read    = in_compressed_read_reg;
+                d1_in_uncompressed_read  = in_uncompressed_read_reg;
+                d1_in_write              = in_write_reg;
+                d1_in_burstwrap          = in_burstwrap_reg;
+                d1_in_size               = in_size_reg;
+                d1_in_aligned_addr       = in_aligned_addr_reg;
+                d1_in_data               = in_data_reg;
+                d1_in_channel            = in_channel_reg;
+                d1_in_bursttype          = in_bursttype_reg;
+                d1_in_passthru           = in_passthru_reg;
+                d1_in_byteen             = in_byteen_reg;
+                d1_in_narrow             = in_narrow_reg;
+
+                // Assign after the related d1_in_* signals have been assigned.
+                d0_in_size_value         = nb ? d0_in_size : d1_in_size;
+                d0_in_burstwrap_value    = nb ? d0_in_burstwrap : d1_in_burstwrap;
+            end
+
+        end // block: no_internal_pipeline
+        else begin : internal_pipeline
+
+            reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size_dl;
+            reg [PKT_BURSTWRAP_W - 1 : 0]  d0_in_burstwrap_dl;
+
+            always_ff @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    in_eop_reg               <= '0;
+                    in_sop_reg               <= '0;
+                    in_compressed_read_reg   <= '0;
+                    in_uncompressed_read_reg <= '0;
+                    in_data_reg              <= '0;
+                    in_channel_reg           <= '0;
+                    in_write_reg             <= '0;
+                    in_bursttype_reg         <= '0;
+                    in_burstwrap_reg         <= '0;
+                    in_passthru_reg          <= '0;
+                    in_size_reg              <= '0;
+                    in_byteen_reg            <= '0;
+                    in_addr_reg              <= '0;
+                    in_aligned_addr_reg      <= '0;
+                    in_len_reg               <= '0;
+                    in_narrow_reg            <= '0;
+                    in_valid_reg             <= '0;
+                    
+                    d1_in_eop                <= '0;
+                    d1_in_compressed_read    <= '0;
+                    d1_in_data               <= '0;
+                    d1_in_channel            <= '0;
+                    d1_in_write              <= '0;
+                    d1_in_bursttype          <= '0;
+                    d1_in_burstwrap          <= '0;
+                    d1_in_passthru           <= '0;
+                    d1_in_size               <= '0;
+                    d0_in_size_dl            <= '0;
+                    d0_in_burstwrap_dl       <= '0;
+                    d1_in_byteen             <= '0;
+                end else begin
+                    if (sink0_pipe_valid & sink0_pipe_ready) begin
+                        in_eop_reg               <= in_eop;
+                        in_sop_reg               <= in_sop;
+                        in_data_reg              <= sink0_pipe_data;
+                        in_channel_reg           <= sink0_pipe_channel;
+                        in_compressed_read_reg   <= in_compressed_read;
+                        in_uncompressed_read_reg <= in_uncompressed_read;
+                        in_write_reg             <= in_write;
+                        in_bursttype_reg         <= in_bursttype;
+                        in_burstwrap_reg         <= in_burstwrap;
+                        in_size_reg              <= in_size;
+                        in_byteen_reg            <= in_byteen;
+                        in_addr_reg              <= in_addr;
+                        in_aligned_addr_reg      <= in_aligned_addr;
+                        in_len_reg               <= in_len;
+                        in_narrow_reg            <= in_narrow;
+                    end
+                    // length changes during packets, so sample
+                    // length-dependent signals at the start
+                    if (in_valid & sink0_pipe_ready & in_sop)
+                        in_passthru_reg <= in_passthru;
+                    if (sink0_pipe_ready)
+                        in_valid_reg <= in_valid;
+                    if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                        ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) )) begin
+                        d1_in_eop               <= in_eop_reg;
+                        d1_in_compressed_read   <= in_compressed_read_reg;
+                        d1_in_data              <= in_data_reg;
+                        d1_in_channel           <= in_channel_reg;
+                        d1_in_write             <= in_write_reg;
+                        d1_in_bursttype         <= in_bursttype_reg;
+                        d1_in_burstwrap         <= in_burstwrap_reg;
+                        d0_in_burstwrap_dl      <= in_burstwrap_reg;
+                        d1_in_passthru          <= in_passthru_reg;
+                        d1_in_size              <= in_size_reg;
+                        d0_in_size_dl           <= in_size_reg;
+                        d1_in_byteen            <= in_byteen_reg;
+                        d1_in_aligned_addr      <= in_aligned_addr_reg;
+                        d1_in_narrow            <= in_narrow_reg;
+                        d1_in_uncompressed_read <= in_uncompressed_read_reg;
+                    end // if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |...
+                end // else: !if(reset)
+            end // always_ff @
+
+            always_comb begin
+                d0_in_valid             = in_valid_reg;
+                d0_in_sop               = in_sop_reg;
+                d0_in_compressed_read   = in_compressed_read_reg;
+                d0_in_uncompressed_read = in_uncompressed_read_reg;
+                d0_in_write             = in_write_reg;
+                d0_in_burstwrap         = in_burstwrap_reg;
+                d0_in_size              = in_size_reg;
+                d0_in_size_value        = nb ? in_size_reg : d0_in_size_dl;
+                d0_in_burstwrap_value   = nb ? in_burstwrap_reg : d0_in_burstwrap_dl;
+                d0_in_addr              = in_addr_reg;
+                d0_in_aligned_addr      = in_aligned_addr_reg;
+                d0_in_len               = in_len_reg;
+            end // always_comb
+        end // block: internal_pipeline
+
+    endgenerate
+
+    // --------------------------------------------------
+    // Control logic stage: state machine
+    // --------------------------------------------------
+    always_ff @(posedge clk or posedge reset) begin
+        if (reset)  begin
+            state <= ST_IDLE;
+        end else begin
+            if (~source0_valid | source0_ready) begin
+                state <= next_state;
+            end
+        end
+    end
+
+    always_comb begin : state_transition
+        next_state = ST_IDLE;   // default
+        case (state)
+            ST_IDLE : begin
+                next_state = ST_IDLE;
+
+                if (d0_in_valid) begin
+                    if (d0_in_write | d0_in_uncompressed_read)  next_state = ST_UNCOMP_TRANS;
+                    if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
+                end
+            end
+
+            ST_UNCOMP_TRANS : begin
+                next_state = ST_UNCOMP_TRANS;
+
+                if (source0_endofpacket) begin
+                    if (!d0_in_valid) next_state = ST_IDLE;
+                    else begin
+                        if (d0_in_write | d0_in_uncompressed_read)  next_state = ST_UNCOMP_TRANS;
+                        if (d0_in_compressed_read)                  next_state = ST_COMP_TRANS;
+                    end
+                end
+            end
+            ST_COMP_TRANS : begin
+                next_state = ST_COMP_TRANS;
+
+                if (source0_endofpacket) begin
+                    if (!d0_in_valid) begin
+                        next_state = ST_IDLE;
+                    end
+                    else begin
+                        if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS;
+                        if (d0_in_compressed_read)                 next_state = ST_COMP_TRANS;
+                    end
+                end
+            end
+        endcase
+    end
+
+    // --------------------------------------------------
+    // Control logic stage: signals for the converters. These signals
+    // enable the correct converter for a burst type, and act as a 
+    // select line when muxing the converter outputs.
+    //
+    // Each type of slave receives its own control logic stage, optimized
+    // for that particular type.
+    // --------------------------------------------------
+    wire [PKT_BYTE_CNT_W  - 1 : 0]  out_byte_cnt;
+    wire [IN_LEN_W        - 1 : 0]  incr_out_len;
+    wire [IN_LEN_W        - 1 : 0]  wrap_out_len;
+    wire [IN_LEN_W        - 1 : 0]  incr_uncompr_out_len;
+    wire [IN_LEN_W        - 1 : 0]  wrap_uncompr_out_len;
+    wire [PKT_ADDR_W      - 1 : 0]  incr_out_addr;
+    wire [PKT_ADDR_W      - 1 : 0]  wrap_out_addr;
+    wire [PKT_ADDR_W      - 1 : 0]  fixed_out_addr;
+    reg  [PKT_ADDR_W      - 1 : 0]  uncompr_out_addr;
+    wire [IN_LEN_W        - 1 : 0]  fixed_out_len;
+    wire [PKT_ADDR_W      - 1 : 0]  out_addr;
+
+    wire                    in_full_size_write_wrap;
+    wire                    in_full_size_read_wrap;
+    wire                    in_default_converter;
+    wire                    in_full_size_incr;
+    reg                     in_default_converter_reg;
+    reg                     in_full_size_incr_reg;
+    reg                     in_full_size_write_wrap_reg;
+    reg                     in_full_size_read_wrap_reg;
+
+    wire                    new_burst;
+    wire                    fixed_new_burst;
+    wire                    wrap_new_burst;
+    wire                    incr_new_burst;
+
+    wire                    next_out_sop;
+    wire                    next_out_eop;
+    wire                    is_passthru;
+    wire                    enable_incr_converter;
+    wire                    enable_fixed_converter;
+    wire                    enable_write_wrap_converter;
+    wire                    enable_read_wrap_converter;
+    wire                    enable_incr_write_converter;
+    wire                    enable_incr_read_converter;
+    reg [IN_LEN_W - 1 : 0]  d0_first_len;
+
+
+    // -----------------------------------------------------------------------
+    // Enable the converters when:
+    // - (sink0_pipe_valid  && (source0_ready | ~source0_valid):
+    //         : when the BA is in idle (!source_valid) and there is a packet coming at input
+    //           or the outpacket has been accepted and there is a packet coming
+    // - (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready))
+    //         : For compressed read, need something consider at end_of_packet, only when seeing
+    //           end_of_packet then turn off converter.
+    // Each converter will be turned on with its own enable based on different type of incoming burst
+    // -----------------------------------------------------------------------
+    generate
+        if (NON_BURSTING_SLAVE) begin : non_bursting_converter_control
+            wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
+            assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
+
+            if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
+                always_comb begin
+                    d0_in_bursttype            = nb ? in_bursttype : in_bursttype_reg;
+                end
+            end
+            else begin : PIPELINE_INPUT
+                    reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
+                always_ff @(posedge clk or posedge reset) begin
+                    if (reset) begin
+                        d0_in_bursttype_dl         <= '0;
+                    end else begin
+                        if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                            ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+                            d0_in_bursttype_dl        <= in_bursttype_reg;
+                        end
+                    end // else: !if(reset)
+                end // always_ff @
+                always_comb begin
+                    d0_in_bursttype            = nb ? in_bursttype_reg : d0_in_bursttype_dl;
+                end
+            end
+
+            //nb: new burst signal
+            assign nb                        =  fixed_new_burst;
+
+            // -----------------------------------------------------------------------
+            // I. Conveter enable signals: Turn on/off each conveter accordingly
+            // -----------------------------------------------------------------------
+            assign enable_fixed_converter = (d0_in_valid  && (source0_ready | !source0_valid) || (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready)));
+           
+            // -----------------------------------------------------------------------
+            // II. Packet signals
+            // -----------------------------------------------------------------------
+            assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(fixed_new_burst)) ? 1'b0 : d0_in_sop;
+            assign next_out_eop = (state == ST_COMP_TRANS) ?  fixed_new_burst  : d1_in_eop;
+            
+            // -----------------------------------------------------------------------
+            // III. Output select
+            // -----------------------------------------------------------------------
+            assign out_byte_cnt  = fixed_out_byte_cnt;
+            assign out_addr      = fixed_out_addr;
+        end
+        else if (INCR_AVALON_SYS) begin : incr_avalon_converter_control
+            wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
+            assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
+
+            //nb: new burst signal
+            assign nb                        =  incr_new_burst;
+            
+            // -----------------------------------------------------------------------
+            // I. Conveter enable signals: Turn on/off each conveter accordingly
+            // -----------------------------------------------------------------------
+            assign enable_incr_converter = (d0_in_valid  && (source0_ready | !source0_valid) || (source0_endofpacket ?  1'b0 :(state == ST_COMP_TRANS) && (!source0_valid | source0_ready)));
+            
+            // -----------------------------------------------------------------------
+            // II. Packet signals
+            // -----------------------------------------------------------------------
+            assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(incr_new_burst)) ? 1'b0 : d0_in_sop;
+            assign next_out_eop = (state == ST_COMP_TRANS) ?  incr_new_burst  : d1_in_eop;
+            
+            // -----------------------------------------------------------------------
+            // III. Output select
+            // -----------------------------------------------------------------------
+            assign out_byte_cnt  = incr_out_byte_cnt;
+            assign out_addr  =  incr_out_addr;
+        end
+        else begin : other_converter_control
+            if (IS_WRAP_AVALON_SLAVE) begin
+                wire                    in_narrow_or_fixed;
+                wire                    in_read_but_not_fixed_or_narrow;
+                wire                    in_write_but_not_fixed_or_narrow;
+                reg                     in_read_but_not_fixed_or_narrow_reg;
+                reg                     in_write_but_not_fixed_or_narrow_reg;
+                reg                     in_narrow_or_fixed_reg;
+                reg                     d0_in_read_but_not_fixed_or_narrow;
+                reg                     d0_in_write_but_not_fixed_or_narrow;
+                reg                     d0_in_default_converter;
+                reg                     d1_in_narrow_or_fixed;
+                reg                     d1_in_read_but_not_fixed_or_narrow;
+                reg                     d1_in_write_but_not_fixed_or_narrow;
+                reg                     d1_in_default_converter;
+                reg [IN_LEN_W - 1 : 0]  first_len_reg;
+
+                wire [PKT_BYTE_CNT_W - 1 : 0]  fixed_out_byte_cnt;
+                wire [PKT_BYTE_CNT_W - 1 : 0]  incr_out_byte_cnt;
+                wire                    in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
+
+                // nb: new burst
+                assign nb                               = (d1_in_narrow_or_fixed ? fixed_new_burst : new_burst);
+                assign in_read_but_not_fixed_or_narrow  = in_compressed_read & !in_narrow_or_fixed;
+                assign in_write_but_not_fixed_or_narrow = in_write & !in_narrow_or_fixed;
+                assign in_narrow_or_fixed               = in_narrow || in_fixed;
+                assign in_default_converter             = in_fixed || in_narrow || in_uncompressed_read;
+                assign incr_out_byte_cnt                = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
+                assign fixed_out_byte_cnt               = fixed_out_len << log2_numsymbols;
+
+                //----------------------------------------------------------------
+                // I. Pipeline input stage
+                //----------------------------------------------------------------
+                if (PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_narrow_or_fixed_reg               <= '0;
+                            in_read_but_not_fixed_or_narrow_reg  <= '0;
+                            in_write_but_not_fixed_or_narrow_reg <= '0;
+                            in_default_converter_reg             <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & sink0_pipe_valid) begin
+                                in_narrow_or_fixed_reg               <= in_narrow_or_fixed;
+                                in_read_but_not_fixed_or_narrow_reg  <= in_read_but_not_fixed_or_narrow;
+                                in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow;
+                                in_default_converter_reg             <= in_default_converter;
+                            end // if (sink0_pipe_ready & sink0_pipe_valid)
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_first_len                         = first_len;
+                        d0_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow;
+                        d0_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow;
+                        d0_in_default_converter              = in_default_converter;
+                        d1_in_narrow_or_fixed                = in_narrow_or_fixed_reg;
+                        d1_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow_reg;
+                        d1_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow_reg;
+                        d1_in_default_converter              = in_default_converter_reg;
+                    end // always_comb
+                end // block: NO_PIPELINE_INPUT
+                else begin : PIPELINE_INPUT
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_narrow_or_fixed_reg               <= '0;
+                            in_read_but_not_fixed_or_narrow_reg  <= '0;
+                            in_write_but_not_fixed_or_narrow_reg <= '0;
+                            in_default_converter_reg             <= '0;
+                            d1_in_narrow_or_fixed                <= '0;
+                            d1_in_read_but_not_fixed_or_narrow   <= '0;
+                            d1_in_write_but_not_fixed_or_narrow  <= '0;
+                            d1_in_default_converter              <= '0;
+                            first_len_reg                        <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & sink0_pipe_valid) begin
+                                in_narrow_or_fixed_reg               <= in_narrow_or_fixed;
+                                in_read_but_not_fixed_or_narrow_reg  <= in_read_but_not_fixed_or_narrow;
+                                in_write_but_not_fixed_or_narrow_reg <= in_write_but_not_fixed_or_narrow;
+                                in_default_converter_reg             <= in_default_converter;
+                            end // if (sink0_pipe_ready & sink0_pipe_valid)
+                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+                                first_len_reg                       <= first_len;
+                                d1_in_narrow_or_fixed               <= in_narrow_or_fixed_reg;
+                                d1_in_read_but_not_fixed_or_narrow  <= in_read_but_not_fixed_or_narrow_reg;
+                                d1_in_write_but_not_fixed_or_narrow <= in_write_but_not_fixed_or_narrow_reg;
+                                d1_in_default_converter             <= in_default_converter_reg;
+                            end
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_in_default_converter              = in_default_converter_reg;
+                        d0_first_len                         = first_len_reg;
+                        d0_in_read_but_not_fixed_or_narrow   = in_read_but_not_fixed_or_narrow_reg;
+                        d0_in_write_but_not_fixed_or_narrow  = in_write_but_not_fixed_or_narrow_reg;
+                    end
+                end // block: PIPELINE_INPUT
+
+                // -------------------------------------------------------------------------
+                // II. First length calculation
+                // -------------------------------------------------------------------------
+                wire same_boundary;
+                // ----------------------------------------------------------
+                // Slave is a wrapping slave, if in_burst wrap has same boundary
+                // pass the burst untouched.
+                // ----------------------------------------------------------
+                if (OUT_BNDRY_ADDR_SEL_W <= PKT_BURSTWRAP_W - 1) begin
+                    assign same_boundary = (in_boundary[OUT_BNDRY_ADDR_SEL_W] == 1);
+                end else begin
+                    assign same_boundary = 0;
+                end
+
+                // --------------------------------------------------------------------------
+                // 1. If in_burst wrapping boundary is lager or INCR burst then always
+                // send first sub_burst length is aligned to slave boudary,
+                // 2. Else aligned to master boundary
+                // Notes:
+                // For INCR, it is tricky that the length can be any value but as the slave is
+                // wrapping, still needs to convert the burst at slave boundary
+                // (in_len <= len_to_out_bndry): can tell the in INCR burst can totally
+                // fit in slave boundary -> pass thru
+                // This works same way for INCOMPLETE wrap as well, so cannot make seperate
+                // optimization when dont support INCOMPLETE wrap
+                // --------------------------------------------------------------------------
+                wire in_len_smaller_not_cross_out_bndry;
+                wire in_len_smaller_not_cross_in_bndry;
+
+                assign in_len_smaller_not_cross_out_bndry  = (in_len <= len_to_out_bndry);
+                assign in_len_smaller_not_cross_in_bndry   = (in_len <= len_to_in_bndry);
+                always_comb begin
+                    if ((in_boundary > OUT_BOUNDARY) || (in_burstwrap[BNDRY_WIDTH - 1] == 1)) begin
+                        first_len  = len_to_out_bndry;
+                        if (in_len_smaller_not_cross_out_bndry || same_boundary)
+                            first_len = in_len;
+                    end
+                    else begin
+                        first_len  = len_to_in_bndry;
+                        if (in_len_smaller_not_cross_in_bndry || same_boundary)
+                            first_len = in_len;
+                    end
+                end // always_comb
+
+                // -----------------------------------------------------------------------
+                // III. Conveter enable signals: Turn on/off each conveter accordingly
+                // -----------------------------------------------------------------------
+                // WRAPPING AVALON: two conveters:
+                //  1. wrap_burst_conveter    -> handle full_size INCR, WRAP
+                //  2. default_burst_conveter -> handle narrow_size burst
+                //  opt, seperate enable for write and reach
+                // -----------------------------------------------------------------------
+                // fixed_new_burst && new_burst : note this for incr_write as it is write_enable, cannot turn on incase a read happen before
+                assign enable_incr_write_converter = (d0_in_valid && d0_in_write_but_not_fixed_or_narrow && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_but_not_fixed_or_narrow && !nb));
+                assign enable_incr_read_converter  = (d0_in_valid && d0_in_read_but_not_fixed_or_narrow && fixed_new_burst && (source0_ready || !source0_valid) || (( state == ST_COMP_TRANS) && source0_ready && d1_in_read_but_not_fixed_or_narrow && !nb));
+                assign enable_fixed_converter      = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
+
+                // -----------------------------------------------------------------------
+                // IV. Packet signals
+                // -----------------------------------------------------------------------
+                assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : new_burst)) ? 1'b0 : d0_in_sop;
+                assign next_out_eop  = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : new_burst)  : d1_in_eop;
+                
+                // -----------------------------------------------------------------------
+                // V. Output select
+                // -----------------------------------------------------------------------
+                assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt;
+                assign out_addr      = d1_in_default_converter ? fixed_out_addr : incr_out_addr;
+            end // if (IS_WRAP_AVALON_SLAVE)
+
+            if (AXI_SLAVE) begin
+                reg [IN_LEN_W - 1 : 0]   first_len_reg;
+                reg                      d0_in_incr;
+                reg                      d1_in_incr;
+                reg                      in_incr_reg;
+                wire                     in_read_wrap_conveter;
+                wire                     in_write_wrap_conveter;
+                reg                      in_read_wrap_conveter_reg;
+                reg                      in_write_wrap_conveter_reg;
+
+                reg                      d0_in_read_wrap_conveter;
+                reg                      d0_in_write_wrap_conveter;
+                reg                      d0_in_default_converter;
+                reg                      d1_in_read_wrap_conveter;
+                reg                      d1_in_write_wrap_conveter;
+                reg                      d1_in_default_converter;
+
+                wire                     in_incr                          = (in_bursttype == 2'b01) && !in_uncompressed_read;
+                wire                     in_wrap                          = (in_bursttype == 2'b10);
+                wire                     in_fixed                         = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
+                wire                     in_narrow_read_wrap_smaller_16   = in_narrow && in_wrap && is_passthru && in_compressed_read;
+                wire                     in_narrow_write_wrap_smaller_16  = in_narrow && in_wrap && is_passthru && in_write;
+                wire                     in_narrow_wrap_larger_16         = in_narrow && in_wrap && !is_passthru;
+                
+                wire [PKT_BYTE_CNT_W  - 1 : 0]  wrap_out_byte_cnt;
+                wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
+                wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
+
+                assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
+                assign wrap_out_byte_cnt  = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols;
+                assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
+
+                assign in_full_size_read_wrap  = in_compressed_read & in_wrap & !in_narrow;
+                assign in_full_size_write_wrap = in_write & in_wrap & !in_narrow;
+                assign in_read_wrap_conveter   = in_full_size_read_wrap  || in_narrow_read_wrap_smaller_16;
+                assign in_write_wrap_conveter  = in_full_size_write_wrap || in_narrow_write_wrap_smaller_16;
+                assign in_default_converter    = in_narrow_wrap_larger_16 || in_fixed || in_uncompressed_read;
+
+                //nb: new burst signal
+                assign nb                       = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst));
+                // is_passthru : still read from real input, as we want to shift 1 clock here, all control signal and first len
+                assign is_passthru = in_sop ? (in_passthru) : in_passthru_reg;
+                
+                //----------------------------------------------------------------
+                // I. Pipeline input stage
+                //----------------------------------------------------------------
+                if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_write_wrap_conveter_reg <= '0;
+                            in_read_wrap_conveter_reg  <= '0;
+                            in_default_converter_reg   <= '0;
+                            in_incr_reg                <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & sink0_pipe_valid) begin
+                                in_write_wrap_conveter_reg <= in_write_wrap_conveter;
+                                in_read_wrap_conveter_reg  <= in_read_wrap_conveter;
+                                in_default_converter_reg   <= in_default_converter;
+                                in_incr_reg                <= in_incr;
+                            end
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_in_incr                 = in_incr;
+                        d0_in_default_converter    = in_default_converter;
+                        d0_in_read_wrap_conveter   = in_read_wrap_conveter;
+                        d0_in_write_wrap_conveter  = in_write_wrap_conveter;
+                        d0_first_len               = first_len;
+                        d1_in_default_converter    = in_default_converter_reg;
+                        d1_in_read_wrap_conveter   = in_read_wrap_conveter_reg;
+                        d1_in_write_wrap_conveter  = in_write_wrap_conveter_reg;
+                        d1_in_incr                 = in_incr_reg;
+                        d0_in_bursttype            = nb ? in_bursttype : in_bursttype_reg;
+                    end
+                end
+                else begin : PIPELINE_INPUT
+                        reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_write_wrap_conveter_reg <= '0;
+                            in_read_wrap_conveter_reg  <= '0;
+                            in_default_converter_reg   <= '0;
+                            d1_in_default_converter    <= '0;
+                            d1_in_read_wrap_conveter   <= '0;
+                            d1_in_write_wrap_conveter  <= '0;
+                            first_len_reg              <= '0;
+                            in_incr_reg                <= '0;
+                            d0_in_bursttype_dl         <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & in_valid) begin
+                                in_write_wrap_conveter_reg <= in_write_wrap_conveter;
+                                in_read_wrap_conveter_reg  <= in_read_wrap_conveter;
+                                in_default_converter_reg   <= in_default_converter;
+                                first_len_reg              <= first_len;
+                                in_incr_reg                <= in_incr;
+                            end
+                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+                                d1_in_default_converter   <= in_default_converter_reg;
+                                d1_in_read_wrap_conveter  <= in_read_wrap_conveter_reg;
+                                d1_in_write_wrap_conveter <= in_write_wrap_conveter_reg;
+                                d1_in_incr                <= in_incr_reg;
+                                d0_in_bursttype_dl        <= in_bursttype_reg;
+                            end
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_in_incr                 = in_incr_reg;
+                        d0_in_default_converter    = in_default_converter_reg;
+                        d0_in_read_wrap_conveter   = in_read_wrap_conveter_reg;
+                        d0_in_write_wrap_conveter  = in_write_wrap_conveter_reg;
+                        d0_first_len               = first_len_reg;
+                        d0_in_bursttype            = nb ? in_bursttype_reg : d0_in_bursttype_dl;
+                    end
+                end
+
+                // -------------------------------------------------------------------------
+                // II. First length calculation
+                // -------------------------------------------------------------------------
+                // For AXI slave, avalon master must set alwaysBurstMaxBurst so
+                // INCOMPLETE wrap burst will not happen
+                // 1. If any wrapping burst that smaller than 16 -> pass thru
+                // 2. Else first sub_burst length is aligned to slave boundary
+                // -------------------------------------------------------------------------
+                //wire passthru = (in_len < len_to_out_bndry) || is_passthru; // why compare here? Keep this until we figure out why.
+                always_comb begin
+                    if (in_boundary > OUT_BOUNDARY) begin
+                        first_len = is_passthru ? in_len : len_to_out_bndry;
+                    end else begin
+                        first_len = is_passthru ? in_len : len_to_in_bndry;
+                    end
+                end // always_comb
+
+                // -----------------------------------------------------------------------
+                // III. Conveter enable signals: Turn on/off each conveter accordingly
+                // -----------------------------------------------------------------------
+                // AXI slave: three conveters:
+                //  1. wrap_burst_conveter    -> handle WRAP
+                //     1.1 : full size wrap   --> convert to fit in slave boundary
+                //     1.2 : narrow size wrap
+                //                            ---> <= 16 : pass thru
+                //                            ---> > 16 : convert to non-bursting
+                //  2. incr_burst_convter     -> handle full/narrow size INCR
+                //  3. default_burst_conveter -> handle FIXED
+                // -----------------------------------------------------------------------
+                // Note: narrow wrap with length larger 16 can happen with Avalon narrow wraping
+                // master to AXI slave. To support this, it will hurt fmax
+                // also the WA adapter currently not pack data in this case, to be better support
+                // need to start from WA first
+                // -----------------------------------------------------------------------
+                assign new_burst                   = incr_new_burst && wrap_new_burst;
+                assign enable_incr_converter       = (d0_in_valid && d0_in_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_incr && !nb));
+                assign enable_write_wrap_converter = (d0_in_valid && d0_in_write_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_write_wrap_conveter && !nb));
+                assign enable_read_wrap_converter  = (d0_in_valid && d0_in_read_wrap_conveter && fixed_new_burst && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_read_wrap_conveter && !nb));
+                assign enable_fixed_converter      = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
+                
+                // -----------------------------------------------------------------------
+                // IV. Packet signals
+                // -----------------------------------------------------------------------
+                assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop;
+                assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))  : d1_in_eop;
+
+                // -----------------------------------------------------------------------
+                // V. Output select
+                // -----------------------------------------------------------------------
+                assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt);
+                assign out_addr      = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr);
+            end // if (AXI_SLAVE)
+
+            if (IS_INCR_SLAVE) begin
+                reg [IN_LEN_W - 1 : 0]   first_len_reg;
+                reg                      d0_in_default_converter;
+                reg                      d0_in_full_size_incr;
+                reg                      d0_in_full_size_write_wrap;
+                reg                      d0_in_full_size_read_wrap;
+                reg                      d1_in_default_converter;
+                reg                      d1_in_full_size_incr;
+                reg                      d1_in_full_size_write_wrap;
+                reg                      d1_in_full_size_read_wrap;
+                reg                      d1_in_incr;
+                reg                      in_incr_reg;
+                wire                     in_incr  = (in_bursttype == 2'b01);
+                wire                     in_wrap  = (in_bursttype == 2'b10);
+
+                wire [PKT_BYTE_CNT_W  - 1 : 0]  incr_out_byte_cnt;
+                wire [PKT_BYTE_CNT_W  - 1 : 0]  fixed_out_byte_cnt;
+
+                assign incr_out_byte_cnt  = (d1_in_compressed_read ? incr_out_len : incr_uncompr_out_len) << log2_numsymbols;
+                assign fixed_out_byte_cnt = fixed_out_len << log2_numsymbols;
+
+                if (NO_WRAP_SUPPORT) begin
+                    assign in_default_converter      = !in_full_size_incr;
+                    assign nb   = d1_in_default_converter ? fixed_new_burst : incr_new_burst;
+                end
+                else begin
+                    wire    in_narrow_incr;
+                    wire    in_fixed = (in_bursttype == 2'b00) || (in_bursttype == 2'b11);
+
+                    assign in_narrow_incr       = in_incr & in_narrow;
+                    assign in_default_converter = in_fixed || in_narrow || in_narrow_incr || in_uncompressed_read;
+                    assign nb                   = (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst));
+                end
+
+                assign in_full_size_incr         = in_incr & !in_narrow & !in_uncompressed_read;
+                assign in_full_size_write_wrap   = in_write & in_wrap & !in_narrow;
+                assign in_full_size_read_wrap    = in_compressed_read & in_wrap & !in_narrow;
+                
+                //----------------------------------------------------------------
+                // I. Pipeline input stage
+                //----------------------------------------------------------------
+                if(PIPE_INTERNAL == 0) begin : NO_PIPELINE_INPUT
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_full_size_write_wrap_reg <= '0;
+                            in_full_size_read_wrap_reg  <= '0;
+                            in_full_size_incr_reg       <= '0;
+                            in_default_converter_reg    <= '0;
+                            in_incr_reg                 <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & sink0_pipe_valid) begin
+                                in_incr_reg                 <= in_incr;
+                                in_full_size_incr_reg       <= in_full_size_incr;
+                                in_full_size_write_wrap_reg <= in_full_size_write_wrap;
+                                in_full_size_read_wrap_reg  <= in_full_size_read_wrap;
+                                in_default_converter_reg    <= in_default_converter;
+                            end
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_in_default_converter     = in_default_converter;
+                        d0_in_full_size_incr        = in_full_size_incr;
+                        d0_in_full_size_write_wrap  = in_full_size_write_wrap;
+                        d0_in_full_size_read_wrap   = in_full_size_read_wrap;
+                        d0_first_len                = first_len;
+                        d1_in_incr                  = in_incr_reg;
+                        d1_in_default_converter     = in_default_converter_reg;
+                        d1_in_full_size_incr        = in_full_size_incr_reg;
+                        d1_in_full_size_write_wrap  = in_full_size_write_wrap_reg;
+                        d1_in_full_size_read_wrap   = in_full_size_read_wrap_reg;
+                        d0_in_bursttype             = nb ? in_bursttype : in_bursttype_reg;
+                    end
+                end
+                else begin : PIPELINE_INPUT
+                    reg [PKT_BURST_TYPE_W - 1 :0]  d0_in_bursttype_dl;
+                    always_ff @(posedge clk or posedge reset) begin
+                        if (reset) begin
+                            in_full_size_write_wrap_reg <= '0;
+                            in_full_size_read_wrap_reg  <= '0;
+                            in_full_size_incr_reg       <= '0;
+                            in_default_converter_reg    <= '0;
+                            d1_in_default_converter     <= '0;
+                            d1_in_full_size_incr        <= '0;
+                            d1_in_full_size_write_wrap  <= '0;
+                            d1_in_full_size_read_wrap   <= '0;
+                            d1_in_incr                  <= '0;
+                            first_len_reg               <= '0;
+                            in_incr_reg                 <= '0;
+                            d0_in_bursttype_dl          <= '0;
+                        end else begin
+                            if (sink0_pipe_ready & in_valid) begin
+                                in_full_size_incr_reg       <= in_full_size_incr;
+                                in_full_size_write_wrap_reg <= in_full_size_write_wrap;
+                                in_full_size_read_wrap_reg  <= in_full_size_read_wrap;
+                                in_default_converter_reg    <= in_default_converter;
+                                in_incr_reg                 <= in_incr;
+                                first_len_reg               <= first_len;
+                            end
+                            if (((state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) |
+                                ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin
+                                d1_in_default_converter    <= in_default_converter_reg;
+                                d1_in_full_size_incr       <= in_full_size_incr_reg;
+                                d1_in_full_size_write_wrap <= in_full_size_write_wrap_reg;
+                                d1_in_full_size_read_wrap  <= in_full_size_read_wrap_reg;
+                                d1_in_incr                 <= in_incr_reg;
+                                d0_in_bursttype_dl         <= in_bursttype_reg;
+                            end
+                        end // else: !if(reset)
+                    end // always_ff @
+                    always_comb begin
+                        d0_in_default_converter     = in_default_converter_reg;
+                        d0_in_full_size_incr        = in_full_size_incr_reg;
+                        d0_in_full_size_write_wrap  = in_full_size_write_wrap_reg;
+                        d0_in_full_size_read_wrap   = in_full_size_read_wrap_reg;
+                        d0_first_len                = first_len_reg;
+                        d0_in_bursttype             = nb ? in_bursttype_reg : d0_in_bursttype_dl;
+                    end
+                end
+                
+                // --------------------------------------------------------------------------------------
+                // II. First length calculation
+                // --------------------------------------------------------------------------------------
+                // Note: the slave is INCR slave, in pratical is has no boundary so if in burst is wrap
+                // the sub burst can send out "slave max length" first fs the in burst not yet wraps back
+                // To simplify and optimize: the first sub_burst length stills send out aligned length first
+                // --------------------------------------------------------------------------------------
+                // If no INCOMPLETE wrap burst
+                // 1. in_boundary is larger out_boundary; first sub_burst length is: aligned to out boundary
+                // 2. in_boundary is smaller out_boundary; first sub_burst length is: aligned to in boundary
+                // --------------------------------------------------------------------------------------
+                if (!NO_WRAP_SUPPORT) begin : HAVE_WRAP_BURSTING_SUPPORT
+                    if (!INCOMPLETE_WRAP_SUPPORT) begin : no_incomplete_wrap_support
+                        assign first_len = (in_boundary > OUT_BOUNDARY) ? len_to_out_bndry : len_to_in_bndry;
+                    end
+                    else begin : incomplete_wrap_support
+                        // -------------------------------------------------------------------------
+                        // If INCOMPLETE wrap support
+                        // 1. The idea is still same, based on boundary and select either aligned to in/out boundary
+                        // 2. But need to check if in_len is smaller to "aligned" in/out boundary for incomplete case
+                        // -> the burst is pass thru is in_len is smaller
+                        // -------------------------------------------------------------------------
+                        wire in_len_smaller_aligned_out_bdry = (in_len <= len_to_out_bndry);
+                        wire in_len_smaller_aligned_in_bdry  = (in_len <= len_to_in_bndry);
+                        always_comb begin
+                            if (in_boundary > OUT_BOUNDARY) begin
+                                first_len = (in_len_smaller_aligned_out_bdry) ? in_len : len_to_out_bndry;
+                            end
+                            else begin
+                                first_len = (in_len_smaller_aligned_in_bdry) ? in_len : len_to_in_bndry;
+                            end
+                        end
+                    end // block: incomplete_wrap_support
+                end
+
+                // -----------------------------------------------------------------------
+                // III. Conveter enable signals: Turn on/off each conveter accordingly
+                // -----------------------------------------------------------------------
+                // INCR slave: three conveters:
+                //  1. wrap_burst_conveter    -> handle WRAP
+                //  2. incr_burst_convter     -> handle INCR
+                //  2. default_burst_conveter -> handle narrow burst
+                // -----------------------------------------------------------------------
+                // -----------------------------------------------------------------------
+                // Purposely support AXI to Avalon: with no wrapping suppport
+                // all wrapping transaction witll be converted to non-bursting sub-burst
+                // 21-January-2014
+                // -----------------------------------------------------------------------
+                if (NO_WRAP_SUPPORT) begin
+                    assign enable_incr_converter        = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb));
+                    assign enable_fixed_converter       = (d0_in_valid && d0_in_default_converter && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
+                    
+                    // -----------------------------------------------------------------------
+                    // IV. Packet signals
+                    // -----------------------------------------------------------------------
+                    assign next_out_sop  = (state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : incr_new_burst) ? 1'b0 : d0_in_sop;
+                    assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : incr_new_burst)  : d1_in_eop;
+                    
+                    // -----------------------------------------------------------------------
+                    // V. Output select
+                    // -----------------------------------------------------------------------
+                    assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : incr_out_byte_cnt;
+                    assign out_addr  = d1_in_default_converter ? fixed_out_addr : incr_out_addr;
+                end
+                else begin
+                    assign new_burst                    = incr_new_burst && wrap_new_burst;
+                    assign enable_incr_converter        = (d0_in_valid && d0_in_full_size_incr && fixed_new_burst && wrap_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_incr && !nb));
+                    assign enable_fixed_converter       = (d0_in_valid && d0_in_default_converter && new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_default_converter && !nb));
+                    assign enable_write_wrap_converter  = (d0_in_valid && d0_in_full_size_write_wrap && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_write_wrap && !nb));
+                    assign enable_read_wrap_converter   = (d0_in_valid && d0_in_full_size_read_wrap  && fixed_new_burst && incr_new_burst && (source0_ready || !source0_valid) || ((state == ST_COMP_TRANS) && source0_ready && d1_in_full_size_read_wrap && !nb));
+
+                    // -----------------------------------------------------------------------
+                    // IV. Packet signals
+                    // -----------------------------------------------------------------------
+                    assign next_out_sop  = ((state == ST_COMP_TRANS) & source0_ready & !(d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))) ? 1'b0 : d0_in_sop;
+                    assign next_out_eop = (state == ST_COMP_TRANS) ?  (d1_in_default_converter ? fixed_new_burst : (d1_in_incr ? incr_new_burst : wrap_new_burst))  : d1_in_eop;
+                    
+                    // -----------------------------------------------------------------------
+                    // V. Output select
+                    // -----------------------------------------------------------------------
+                    wire [PKT_BYTE_CNT_W  - 1 : 0]  wrap_out_byte_cnt;
+                    assign wrap_out_byte_cnt    = (d1_in_compressed_read ? wrap_out_len : wrap_uncompr_out_len) << log2_numsymbols;
+                    
+                    assign out_byte_cnt  = d1_in_default_converter ? fixed_out_byte_cnt : (d1_in_incr ? incr_out_byte_cnt : wrap_out_byte_cnt);
+                    assign out_addr  = d1_in_default_converter ? fixed_out_addr : (d1_in_incr ? incr_out_addr : wrap_out_addr);
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Control signals
+    // --------------------------------------------------
+    reg   source0_valid_reg;
+    wire  next_source0_valid;
+    reg   source0_startofpacket_reg;
+
+    wire  is_write;
+    assign is_write  = nb ? (d0_in_write) : d1_in_write;
+
+    //-------------------------------------------------------------------------
+    // Handshaking and packet signals
+    // -----------------------------------------------------------------------
+    // source0_valid: takes from in sink_valid unless read then wait until end_of_packet
+    assign next_source0_valid  = ((state == ST_COMP_TRANS) & !source0_endofpacket) ? 1'b1 : d0_in_valid;
+
+    // sink0_ready needs always to be asserted first, hold one after reset
+    assign sink0_pipe_ready  = (state == ST_UNCOMP_TRANS) ? source0_ready || !source0_valid : (state == ST_COMP_TRANS) ? nb && source0_ready || !source0_valid : in_ready_hold;
+
+    always_ff @(posedge clk or posedge reset) begin
+        if (reset)  begin
+            source0_valid_reg         <= '0;
+            source0_startofpacket_reg <= '1;
+        end else begin
+            if (~source0_valid | source0_ready) begin
+                source0_valid_reg         <= next_source0_valid;
+                source0_startofpacket_reg <= next_out_sop;
+            end
+        end // else: !if(reset)
+    end // always_ff @
+
+    // Assign output signals
+    always_comb begin
+        source0_endofpacket    = next_out_eop;
+        source0_startofpacket  = source0_startofpacket_reg;
+        source0_valid          = source0_valid_reg;
+    end
+
+    // --------------------------------------------------
+    // Converters instantiation and signal mappings.
+    // --------------------------------------------------
+    generate
+        if (NON_BURSTING_SLAVE) begin : non_bursting_slave_converters_sel
+            altera_default_burst_converter
+            #(
+             .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
+             .PKT_ADDR_W          (PKT_ADDR_W),
+             .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
+             .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
+             .LEN_W               (IN_LEN_W),
+             .IS_AXI_SLAVE        (AXI_SLAVE)
+            )
+            the_default_burst_converter
+            (
+             .clk                       (clk),
+             .reset                     (reset),
+             .enable                    (enable_fixed_converter), // turn on if a fixed
+             .in_addr                   (d0_in_aligned_addr),
+             .in_addr_reg               (d1_in_aligned_addr),
+             .in_bursttype              (d0_in_bursttype),
+             .in_burstwrap_reg          (d1_in_burstwrap),
+             .in_burstwrap_value        (d0_in_burstwrap_value),
+             .in_len                    (d0_in_len),
+             .in_size_value             (d0_in_size_value),
+             .in_is_write               (is_write),
+             .out_len                   (fixed_out_len),
+             .out_addr                  (fixed_out_addr),
+             .new_burst                 (fixed_new_burst)
+            );
+        end
+        else if (INCR_AVALON_SYS) begin : system_purely_avalon_converter_sel
+            //-----------------------------------------------------------------
+            // When system is purely INCR, only need one converter.
+            //-----------------------------------------------------------------
+            altera_incr_burst_converter
+            #(
+             .MAX_IN_LEN          (MAX_IN_LEN),
+             .MAX_OUT_LEN         (MAX_OUT_LEN),
+             .ADDR_WIDTH          (PKT_ADDR_W),
+             .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
+             .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
+             .IN_NARROW_SIZE      (IN_NARROW_SIZE),
+             .NUM_SYMBOLS         (NUM_SYMBOLS),
+             .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
+            )
+            the_converter_for_avalon_incr_slave
+            (
+             .clk                     (clk),
+             .reset                   (reset),
+             .enable                  (enable_incr_converter),
+             .in_len                  (d0_in_len),
+             .in_sop                  (d0_in_sop),
+             .in_burstwrap_reg        (d1_in_burstwrap),
+             .in_size_t               (d0_in_size),
+             .in_size_reg             (d1_in_size),
+             .in_addr                 (d0_in_aligned_addr),
+             .in_addr_reg             (d1_in_aligned_addr),
+             .is_write                (is_write),
+             .out_len                 (incr_out_len),
+             .uncompr_out_len         (incr_uncompr_out_len),
+             .out_addr                (incr_out_addr),
+             .new_burst_export        (incr_new_burst)
+            );
+        end
+        else begin : converters_selection
+            if (IS_WRAP_AVALON_SLAVE) begin : wrapping_avalon_slave_converter_sel
+                altera_wrap_burst_converter
+                #(
+                 .MAX_IN_LEN            (MAX_IN_LEN),
+                 .MAX_OUT_LEN           (MAX_OUT_LEN),
+                 .ADDR_WIDTH            (PKT_ADDR_W),
+                 .BNDRY_WIDTH           (PKT_BURSTWRAP_W),
+                 .AXI_SLAVE             (AXI_SLAVE),
+                 .NUM_SYMBOLS           (NUM_SYMBOLS),
+                 .OPTIMIZE_WRITE_BURST  (0)
+                )
+                the_converter_for_avalon_wrap_slave
+                (
+                 .clk                               (clk),
+                 .reset                             (reset),
+                 .enable_read                       (enable_incr_read_converter),
+                 .enable_write                      (enable_incr_write_converter),
+                 .in_len                            (d0_in_len),
+                 .first_len                         (d0_first_len),
+                 .in_sop                            (d0_in_sop),
+                 .in_burstwrap                      (d0_in_burstwrap),
+                 .in_burstwrap_reg                  (d1_in_burstwrap),
+                 .in_boundary                       (in_boundary),
+                 .in_addr                           (d0_in_aligned_addr),
+                 .in_addr_reg                       (d1_in_aligned_addr),
+                 .out_len                           (incr_out_len),
+                 .uncompr_out_len                   (incr_uncompr_out_len),
+                 .out_addr                          (incr_out_addr),
+                 .new_burst_export                  (new_burst)
+                );
+
+                altera_default_burst_converter
+                #(
+                 .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
+                 .PKT_ADDR_W          (PKT_ADDR_W),
+                 .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
+                 .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
+                 .LEN_W               (IN_LEN_W),
+                 .IS_AXI_SLAVE        (AXI_SLAVE)
+                )
+                the_default_burst_converter
+                (
+                 .clk                       (clk),
+                 .reset                     (reset),
+                 .enable                    (enable_fixed_converter), // turn on if a fixed
+                 .in_addr                   (d0_in_aligned_addr),
+                 .in_addr_reg               (d1_in_aligned_addr),
+                 .in_bursttype              (d0_in_bursttype),
+                 .in_burstwrap_reg          (d1_in_burstwrap),
+                 .in_burstwrap_value        (d0_in_burstwrap_value),
+                 .in_len                    (d0_in_len),
+                 .in_size_value             (d0_in_size_value),
+                 .in_is_write               (is_write),
+                 .out_len                   (fixed_out_len),
+                 .out_addr                  (fixed_out_addr),
+                 .new_burst                 (fixed_new_burst)
+                );
+            end
+            if (AXI_SLAVE) begin : axi_slave_converter_sel
+                altera_wrap_burst_converter
+                #(
+                 .MAX_IN_LEN              (MAX_IN_LEN),
+                 .MAX_OUT_LEN             (MAX_OUT_LEN),
+                 .ADDR_WIDTH              (PKT_ADDR_W),
+                 .BNDRY_WIDTH             (PKT_BURSTWRAP_W),
+                 .NUM_SYMBOLS             (NUM_SYMBOLS),
+                 .AXI_SLAVE               (AXI_SLAVE),
+                 .OPTIMIZE_WRITE_BURST    (0)
+                )
+                the_converter_for_avalon_wrap_slave
+                (
+                 .clk                               (clk),
+                 .reset                             (reset),
+                 .enable_read                       (enable_read_wrap_converter),
+                 .enable_write                      (enable_write_wrap_converter),
+                 .in_len                            (d0_in_len),
+                 .first_len                         (d0_first_len),
+                 .in_sop                            (d0_in_sop),
+                 .in_burstwrap                      (d0_in_burstwrap),
+                 .in_burstwrap_reg                  (d1_in_burstwrap),
+                 .in_boundary                       (in_boundary),
+                 .in_addr                           (d0_in_aligned_addr),
+                 .in_addr_reg                       (d1_in_aligned_addr),
+                 .out_len                           (wrap_out_len),
+                 .uncompr_out_len                   (wrap_uncompr_out_len),
+                 .out_addr                          (wrap_out_addr),
+                 .new_burst_export                  (wrap_new_burst)
+                );
+
+                altera_incr_burst_converter
+                #(
+                 .MAX_IN_LEN          (MAX_IN_LEN),
+                 .MAX_OUT_LEN         (MAX_OUT_LEN),
+                 .ADDR_WIDTH          (PKT_ADDR_W),
+                 .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
+                 .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
+                 .IN_NARROW_SIZE      (IN_NARROW_SIZE),
+                 .NUM_SYMBOLS         (NUM_SYMBOLS),
+                 .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
+                )
+                the_converter_for_avalon_incr_slave
+                (
+                 .clk                (clk),
+                 .reset              (reset),
+                 .enable             (enable_incr_converter),
+                 .in_len             (d0_in_len),
+                 .in_sop             (d0_in_sop),
+                 .in_burstwrap_reg   (d1_in_burstwrap),
+                 .in_size_t          (d0_in_size),
+                 .in_size_reg        (d1_in_size),
+                 .in_addr            (d0_in_aligned_addr),
+                 .in_addr_reg        (d1_in_aligned_addr),
+                 .is_write           (is_write),
+                 .out_len            (incr_out_len),
+                 .uncompr_out_len    (incr_uncompr_out_len),
+                 .out_addr           (incr_out_addr),
+                 .new_burst_export   (incr_new_burst)
+                );
+
+                // --------------------------------------------------
+                // The fixed burst converter module
+                // --------------------------------------------------
+                altera_default_burst_converter
+                #(
+                 .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
+                 .PKT_ADDR_W          (PKT_ADDR_W),
+                 .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
+                 .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
+                 .LEN_W               (IN_LEN_W),
+                 .IS_AXI_SLAVE        (AXI_SLAVE)
+                )
+                the_default_burst_converter
+                (
+                 .clk                       (clk),
+                 .reset                     (reset),
+                 .enable                    (enable_fixed_converter), // turn on if a fixed
+                 .in_addr                   (d0_in_aligned_addr),
+                 .in_addr_reg               (d1_in_aligned_addr),
+                 .in_bursttype              (d0_in_bursttype),
+                 .in_burstwrap_reg          (d1_in_burstwrap),
+                 .in_burstwrap_value        (d0_in_burstwrap_value),
+                 .in_len                    (d0_in_len),
+                 .in_size_value             (d0_in_size_value),
+                 .in_is_write               (is_write),
+                 .out_len                   (fixed_out_len),
+                 .out_addr                  (fixed_out_addr),
+                 .new_burst                 (fixed_new_burst)
+                );
+            end
+            if (IS_INCR_SLAVE) begin : incr_slave_converter_sel
+                if (NO_WRAP_SUPPORT) begin : no_wrap_incr_slave_converter_sel
+                    altera_incr_burst_converter
+                    #(
+                     .MAX_IN_LEN          (MAX_IN_LEN),
+                     .MAX_OUT_LEN         (MAX_OUT_LEN),
+                     .ADDR_WIDTH          (PKT_ADDR_W),
+                     .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
+                     .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
+                     .IN_NARROW_SIZE      (0), // not support narrow as this is INCR avalon slave
+                     .NUM_SYMBOLS         (NUM_SYMBOLS),
+                     .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
+                    )
+                    the_converter_for_avalon_incr_slave
+                    (
+                     .clk                (clk),
+                     .reset              (reset),
+                     .enable             (enable_incr_converter),
+                     .in_len             (d0_in_len),
+                     .in_sop             (d0_in_sop),
+                     .in_burstwrap_reg   (d1_in_burstwrap),
+                     .in_size_t          (d0_in_size),
+                     .in_size_reg        (d1_in_size),
+                     .in_addr            (d0_in_aligned_addr),
+                     .in_addr_reg        (d1_in_aligned_addr),
+                     .is_write           (is_write),
+                     .out_len            (incr_out_len),
+                     .uncompr_out_len    (incr_uncompr_out_len),
+                     .out_addr           (incr_out_addr),
+                     .new_burst_export   (incr_new_burst)
+                    );
+  
+                    // --------------------------------------------------
+                    // The default converter
+                    // --------------------------------------------------
+                    altera_default_burst_converter
+                    #(
+                     .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
+                     .PKT_ADDR_W          (PKT_ADDR_W),
+                     .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
+                     .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
+                     .LEN_W               (IN_LEN_W),
+                     .IS_AXI_SLAVE        (AXI_SLAVE)
+                    )
+                    the_default_burst_converter
+                    (
+                     .clk                       (clk),
+                     .reset                     (reset),
+                     .enable                    (enable_fixed_converter), // turn on if a fixed
+                     .in_addr                   (d0_in_aligned_addr),
+                     .in_addr_reg               (d1_in_aligned_addr),
+                     .in_bursttype              (d0_in_bursttype),
+                     .in_burstwrap_reg          (d1_in_burstwrap),
+                     .in_burstwrap_value        (d0_in_burstwrap_value),
+                     .in_len                    (d0_in_len),
+                     .in_size_value             (d0_in_size_value),
+                     .in_is_write               (is_write),
+                     .out_len                   (fixed_out_len),
+                     .out_addr                  (fixed_out_addr),
+                     .new_burst                 (fixed_new_burst)
+                    );
+                end
+                else begin : wrap_incr_slave_conveter_sel
+                    altera_wrap_burst_converter
+                    #(
+                     .MAX_IN_LEN              (MAX_IN_LEN),
+                     .MAX_OUT_LEN             (MAX_OUT_LEN),
+                     .ADDR_WIDTH              (PKT_ADDR_W),
+                     .BNDRY_WIDTH             (PKT_BURSTWRAP_W),
+                     .NUM_SYMBOLS             (NUM_SYMBOLS),
+                     .AXI_SLAVE               (AXI_SLAVE),
+                     .OPTIMIZE_WRITE_BURST    (0)
+                    )
+                    the_converter_for_avalon_wrap_slave
+                    (
+                     .clk                               (clk),
+                     .reset                             (reset),
+                     .enable_read                       (enable_read_wrap_converter),
+                     .enable_write                      (enable_write_wrap_converter),
+                     .in_len                            (d0_in_len),
+                     .first_len                         (d0_first_len),
+                     .in_sop                            (d0_in_sop),
+                     .in_burstwrap                      (d0_in_burstwrap),
+                     .in_burstwrap_reg                  (d1_in_burstwrap),
+                     .in_boundary                       (in_boundary),
+                     .in_addr                           (d0_in_aligned_addr),
+                     .in_addr_reg                       (d1_in_aligned_addr),
+                     .out_len                           (wrap_out_len),
+                     .uncompr_out_len                   (wrap_uncompr_out_len),
+                     .out_addr                          (wrap_out_addr),
+                     .new_burst_export                  (wrap_new_burst)
+                    );
+
+                    altera_incr_burst_converter
+                    #(
+                     .MAX_IN_LEN          (MAX_IN_LEN),
+                     .MAX_OUT_LEN         (MAX_OUT_LEN),
+                     .ADDR_WIDTH          (PKT_ADDR_W),
+                     .BNDRY_WIDTH         (PKT_BURSTWRAP_W),
+                     .BURSTSIZE_WIDTH     (PKT_BURST_SIZE_W),
+                     .IN_NARROW_SIZE      (IN_NARROW_SIZE),
+                     .NUM_SYMBOLS         (NUM_SYMBOLS),
+                     .PURELY_INCR_AVL_SYS (INCR_AVALON_SYS)
+                    )
+                    the_converter_for_avalon_incr_slave
+                    (
+                     .clk                     (clk),
+                     .reset                   (reset),
+                     .enable                  (enable_incr_converter),
+                     .in_len                  (d0_in_len),
+                     .in_sop                  (d0_in_sop),
+                     .in_burstwrap_reg        (d1_in_burstwrap),
+                     .in_size_t               (d0_in_size),
+                     .in_size_reg             (d1_in_size),
+                     .in_addr                 (d0_in_aligned_addr),
+                     .in_addr_reg             (d1_in_aligned_addr),
+                     .is_write                (is_write),
+                     .out_len                 (incr_out_len),
+                     .uncompr_out_len         (incr_uncompr_out_len),
+                     .out_addr                (incr_out_addr),
+                     .new_burst_export        (incr_new_burst)
+                    );
+                    
+                    // --------------------------------------------------
+                    // The fixed burst converter module
+                    // --------------------------------------------------
+                    altera_default_burst_converter
+                    #(
+                     .PKT_BURST_TYPE_W    (PKT_BURST_TYPE_W),
+                     .PKT_ADDR_W          (PKT_ADDR_W),
+                     .PKT_BURSTWRAP_W     (PKT_BURSTWRAP_W),
+                     .PKT_BURST_SIZE_W    (PKT_BURST_SIZE_W),
+                     .LEN_W               (IN_LEN_W),
+                     .IS_AXI_SLAVE        (AXI_SLAVE)
+                    )
+                    the_default_burst_converter
+                    (
+                     .clk                       (clk),
+                     .reset                     (reset),
+                     .enable                    (enable_fixed_converter), // turn on if a fixed
+                     .in_addr                   (d0_in_aligned_addr),
+                     .in_addr_reg               (d1_in_aligned_addr),
+                     .in_bursttype              (d0_in_bursttype),
+                     .in_burstwrap_reg          (d1_in_burstwrap),
+                     .in_burstwrap_value        (d0_in_burstwrap_value),
+                     .in_len                    (d0_in_len),
+                     .in_size_value             (d0_in_size_value),
+                     .in_is_write               (is_write),
+                     .out_len                   (fixed_out_len),
+                     .out_addr                  (fixed_out_addr),
+                     .new_burst                 (fixed_new_burst)
+                    );
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function unsigned[63:0] log2ceil;
+        input reg [63:0] val;
+        reg [63:0]       i;
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+    // ---------------------------------------------------
+    // Mapping of output signals.
+    // ---------------------------------------------------
+    wire load_next_output_pck  = source0_ready | !source0_valid;
+    always_ff @(posedge clk or posedge reset) begin
+        if (reset) begin
+            uncompr_out_addr <= '0;
+        end
+        else if (load_next_output_pck) begin
+            uncompr_out_addr <= d0_in_addr;
+        end
+
+    end
+
+    // ---------------------------------------------------
+    // Out burstype
+    // ---------------------------------------------------
+    // If AXI slave, out_bursttype = INCR if either of the following 2 conditions is met:
+    //  1) in_passthru (i.e. the input burst count < 16).
+    //  2) input packet has bursttype == REP_WRAP (Repeated Wrap).
+    // Else, out_bursttype = in_bursttype.
+    // For all other slaves, change the bursttype to INCR.
+    wire [PKT_BURST_TYPE_W - 1 : 0] out_bursttype;
+    generate
+        if (AXI_SLAVE) begin : AXI_SLAVE_out_bursttype
+            assign out_bursttype = (!d1_in_passthru || d1_in_bursttype == REP_WRAP) ? INCR : d1_in_bursttype;
+        end
+        else begin : others_slave_out_bursttype
+           assign out_bursttype =  INCR;
+        end
+    endgenerate
+
+    // At source0_startofpacket, out_addr_read is the in_addr.
+    wire [PKT_ADDR_W - 1 : 0] out_addr_read;
+    assign out_addr_read = source0_startofpacket_reg ? uncompr_out_addr : out_addr;
+
+    // Choose between uncompressed or compressed trans address.
+    wire [PKT_ADDR_W - 1 : 0] out_addr_assigned_to_packet;
+    assign out_addr_assigned_to_packet = (d1_in_write || d1_in_uncompressed_read) ?  uncompr_out_addr : out_addr_read;
+
+    // ---------------------------------------------------
+    // Byteenable Generation.
+    // Passthrough unless compressed transaction.
+    // ---------------------------------------------------
+    reg  [PKT_BYTEEN_W - 1 : 0 ]     out_byteen;
+    reg  [ADDR_MASK_SEL - 1 : 0 ]    out_addr_masked;
+    wire [511:0] initial_byteen = set_byteenable_based_on_size(d1_in_size); // To fix quartus integration error. Unused bits are expected to be synthesized away
+
+    // Unaligned address changes.
+    // Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address.
+    //              Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle)
+    always_comb begin
+        // Addresses from the converters (out_addr) are always aligned.
+        out_addr_masked = out_addr[ADDR_MASK_SEL-1:0];
+    end
+
+    always_comb begin
+    if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS))
+        out_byteen     = initial_byteen[NUM_SYMBOLS-1:0] << out_addr_masked;
+    else
+        out_byteen  = d1_in_byteen;
+    end
+    // -- End of Byteenable Generation --
+
+    always_comb begin : source0_out_assignments
+        source0_data                                       = d1_in_data;
+        source0_channel                                    = d1_in_channel;
+        // Override fields the component is aware of.
+        source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]  = out_bursttype;
+        source0_data[PKT_BYTE_CNT_H   : PKT_BYTE_CNT_L  ]  = out_byte_cnt;
+        source0_data[PKT_ADDR_H       : PKT_ADDR_L      ]  = out_addr_assigned_to_packet;
+        source0_data[PKT_BYTEEN_H     : PKT_BYTEEN_L    ]  = out_byteen;
+    end
+
+    //----------------------------------------------------
+    // "min" operation on burstwrap values is a bitwise AND.
+    //----------------------------------------------------
+    function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min;
+        input [PKT_BURSTWRAP_W - 1 : 0] a, b;
+        begin
+            altera_merlin_burst_adapter_burstwrap_min  = a & b;
+        end
+    endfunction
+
+    //----------------------------------------------------
+    // AXSIZE encoding: run-time  size of the transaction.
+    // ---------------------------------------------------
+    function reg[511:0] set_byteenable_based_on_size;
+        input [3:0] axsize;
+        begin
+            case (axsize)
+                4'b0000: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
+                4'b0001: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003;
+                4'b0010: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F;
+                4'b0011: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF;
+                4'b0100: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFF;
+                4'b0101: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF;
+                4'b0110: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF;
+                4'b0111: set_byteenable_based_on_size = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                4'b1000: set_byteenable_based_on_size = 512'h0000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                4'b1001: set_byteenable_based_on_size = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+                default: set_byteenable_based_on_size = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001;
+            endcase
+        end
+    endfunction
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
new file mode 100644
index 0000000..663f48a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
@@ -0,0 +1,94 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#68 $
+// $Revision: #68 $
+// $Date: 2014/01/23 $
+// $Author: wkleong $
+
+`timescale 1 ns / 1 ns
+
+// -------------------------------------------------------
+// Adapter for uncompressed transactions only. This adapter will
+// typically be used to adapt burst length for non-bursting 
+// wide to narrow Avalon links.
+// -------------------------------------------------------
+module altera_merlin_burst_adapter_uncompressed_only
+#(
+    parameter 
+    PKT_BYTE_CNT_H  = 5,
+    PKT_BYTE_CNT_L  = 0,
+    PKT_BYTEEN_H    = 83,
+    PKT_BYTEEN_L    = 80,
+    ST_DATA_W       = 84,
+    ST_CHANNEL_W    = 8
+)
+(
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                           sink0_valid,
+    input  [ST_DATA_W-1 : 0]        sink0_data,
+    input  [ST_CHANNEL_W-1 : 0]     sink0_channel,
+    input                           sink0_startofpacket,
+    input                           sink0_endofpacket,
+    output reg                      sink0_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg                      source0_valid,
+    output reg [ST_DATA_W-1    : 0] source0_data,
+    output reg [ST_CHANNEL_W-1 : 0] source0_channel,
+    output reg                      source0_startofpacket,
+    output reg                      source0_endofpacket,
+    input                           source0_ready
+);
+    localparam
+        PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+        NUM_SYMBOLS    = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+
+    wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0];
+
+    always_comb begin : source0_data_assignments
+        source0_valid         = sink0_valid;
+        source0_channel       = sink0_channel;
+        source0_startofpacket = sink0_startofpacket;
+        source0_endofpacket   = sink0_endofpacket;
+
+        source0_data          = sink0_data;
+        source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig;
+
+        sink0_ready = source0_ready;
+    end
+
+endmodule
+
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
new file mode 100644
index 0000000..2f836a3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
@@ -0,0 +1,296 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Burst Uncompressor
+//
+// Compressed read bursts -> uncompressed
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_burst_uncompressor
+#(
+    parameter ADDR_W      = 16,
+    parameter BURSTWRAP_W = 3,
+    parameter BYTE_CNT_W  = 4,
+    parameter PKT_SYMBOLS = 4,
+    parameter BURST_SIZE_W = 3
+)
+(
+    input clk,
+    input reset,
+   
+    // sink ST signals
+    input sink_startofpacket,
+    input sink_endofpacket,
+    input sink_valid,
+    output sink_ready,
+   
+    // sink ST "data"
+    input [ADDR_W - 1: 0] sink_addr,
+    input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
+    input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
+    input sink_is_compressed,
+    input [BURST_SIZE_W-1 : 0] sink_burstsize,
+   
+    // source ST signals
+    output source_startofpacket,
+    output source_endofpacket,
+    output source_valid,
+    input source_ready,
+   
+    // source ST "data"
+    output [ADDR_W - 1: 0] source_addr,
+    output [BURSTWRAP_W - 1 : 0] source_burstwrap,
+    output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
+   
+    // Note: in the slave agent, the output should always be uncompressed.  In
+    // other applications, it may be required to leave-compressed or not. How to
+    // control?  Seems like a simple mux - pass-through if no uncompression is
+    // required.
+    output source_is_compressed,
+    output [BURST_SIZE_W-1 : 0] source_burstsize
+);
+
+//----------------------------------------------------
+// AXSIZE decoding
+//
+// Turns the axsize value into the actual number of bytes
+// being transferred.
+// ---------------------------------------------------
+function reg[63:0] bytes_in_transfer;
+    input [BURST_SIZE_W-1:0] axsize;
+    case (axsize)
+        4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+        4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+        4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+        4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+        4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+        4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+        4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+        4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+        4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+        4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+        default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+    endcase
+
+endfunction  
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+  
+   // def: Burst Compression.  In a merlin network, a compressed burst is one 
+   // which is transmitted in a single beat.  Example: read burst.  In 
+   // constrast, an uncompressed burst (example: write burst) is transmitted in
+   // one beat per writedata item.
+   //
+   // For compressed bursts which require response packets, burst
+   // uncompression is required.  Concrete example: a read burst of size 8
+   // occupies one response-fifo position.  When that fifo position reaches the
+   // front of the FIFO, the slave starts providing the required 8 readdatavalid
+   // pulses.  The 8 return response beats must be provided in a single packet,
+   // with incrementing address and decrementing byte_cnt fields.  Upon receipt
+   // of the final readdata item of the burst, the response FIFO item is
+   // retired.
+   // Burst uncompression logic provides:
+   //   a) 2-state FSM (idle, busy)
+   //     reset to idle state
+   //     transition to busy state for 2nd and subsequent rdv pulses
+   //     - a single-cycle burst (aka non-burst read) causes no transition to
+   //     busy state.
+   //   b) response startofpacket/endofpacket logic.  The response FIFO item 
+   //   will have sop asserted, and may have eop asserted. (In the case of
+   //   multiple read bursts transmit in the command fabric in a single packet,
+   //   the eop assertion will come in a later FIFO item.)  To support packet
+   //   conservation, and emit a well-formed packet on the response fabric,
+   //     i) response fabric startofpacket is asserted only for the first resp.
+   //     beat;
+   //     ii) response fabric endofpacket is asserted only for the last resp.
+   //     beat.
+   //   c) response address field.  The response address field contains an
+   //   incrementing sequence, such that each readdata item is associated with
+   //   its slave-map location.  N.b. a) computing the address correctly requires
+   //   knowledge of burstwrap behavior b) there may be no clients of the address
+   //   field, which makes this field a good target for optimization.  See
+   //   burst_uncompress_address_counter below.
+   //   d) response byte_cnt field.  The response byte_cnt field contains a
+   //   decrementing sequence, such that each beat of the response contains the
+   //   count of bytes to follow.  In the case of sub-bursts in a single packet,
+   //   the byte_cnt field may decrement down to num_symbols, then back up to
+   //   some value, multiple times in the packet.
+  
+   reg burst_uncompress_busy;
+   reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
+   wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
+   wire first_packet_beat;
+   wire last_packet_beat;
+
+   assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
+   assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
+
+   // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
+   // the output.
+   assign source_byte_cnt =
+     first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
+   assign source_valid = sink_valid;
+  
+   // Last packet beat is set throughout receipt of an uncompressed read burst
+   // from the response FIFO - this forces all the burst uncompression machinery
+   // idle.
+   assign last_packet_beat = ~sink_is_compressed |
+     (
+     burst_uncompress_busy ?
+       (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
+         sink_valid & (sink_byte_cnt == num_symbols)
+     );
+  
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_busy <= '0;
+       burst_uncompress_byte_counter <= '0;
+     end
+     else begin
+       if (source_valid & source_ready & sink_valid) begin
+         // No matter what the current state, last_packet_beat leads to
+         // idle.
+         if (last_packet_beat) begin
+           burst_uncompress_busy <= '0;
+           burst_uncompress_byte_counter <= '0;
+         end
+         else begin
+           if (burst_uncompress_busy) begin
+             burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? 
+               (burst_uncompress_byte_counter_lint - num_symbols) :
+               (sink_byte_cnt - num_symbols);
+           end
+           else begin // not busy, at least one more beat to go
+             burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
+             // To do: should busy go true for numsymbols-size compressed
+             // bursts?
+             burst_uncompress_busy <= 1'b1;
+           end
+         end
+       end
+     end
+   end
+  
+   reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
+   reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
+
+   wire [63:0] decoded_burstsize_wire;
+   wire [ADDR_W-1:0] decoded_burstsize;
+
+
+   localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
+   wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
+   // The input burstwrap value can be used as a mask against address values,
+   // but with one caveat: the address width may be (probably is) wider than 
+   // the burstwrap width.  The spec says: extend the msb of the burstwrap 
+   // value out over the entire address width (but only if the address width
+   // actually is wider than the burstwrap width; otherwise it's a 0-width or
+   // negative range and concatenation multiplier). 
+   generate
+      if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
+         // Sign-extend, just wires:
+            assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
+                {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
+            assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
+      end
+      else begin
+            assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
+      end
+   endgenerate
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_base <= '0;
+     end
+     else if (first_packet_beat & source_ready) begin
+       burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
+     end
+   end
+
+   assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);  //expand it to 64 bits
+   assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];      //then take the width that is needed
+
+   wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
+   (
+     (first_packet_beat ?
+       sink_addr :
+       burst_uncompress_address_offset) + decoded_burstsize
+    ) &
+    addr_width_burstwrap[ADDR_W-1:0];
+    wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_offset <= '0;
+     end
+     else begin
+       if (source_ready & source_valid) begin
+         burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
+         // if (first_packet_beat) begin
+         //   burst_uncompress_address_offset <=
+         //     (sink_addr + num_symbols) & addr_width_burstwrap;
+         // end
+         // else begin
+         //   burst_uncompress_address_offset <=
+         //     (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
+         // end
+       end
+     end
+   end
+  
+   // On the first packet beat, send the input address out unchanged, 
+   // while values are computed/registered for 2nd and subsequent beats.
+   assign source_addr = first_packet_beat ? sink_addr :
+       burst_uncompress_address_base | burst_uncompress_address_offset;
+   assign source_burstwrap = sink_burstwrap;
+   assign source_burstsize = sink_burstsize;
+  
+   //-------------------------------------------------------------------
+   // A single (compressed) read burst will have sop/eop in the same beat.
+   // A sequence of read sub-bursts emitted by a burst adapter in response to a
+   // single read burst will have sop on the first sub-burst, eop on the last.
+   // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve 
+   // packet conservation.
+   assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
+   assign source_endofpacket   = sink_endofpacket & last_packet_beat;
+   assign sink_ready = source_valid & source_ready & last_packet_beat;
+  
+   // This is correct for the slave agent usage, but won't always be true in the
+   // width adapter.  To do: add an "please uncompress" input, and use it to
+   // pass-through or modify, and set source_is_compressed accordingly.
+   assign source_is_compressed = 1'b0;
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_agent.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
new file mode 100644
index 0000000..0e311d7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_agent.sv
@@ -0,0 +1,303 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Agent
+//
+// Converts Avalon-MM transactions into
+// Merlin network packets.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_agent
+#(
+   // -------------------
+   // Packet Format Parameters
+   // -------------------
+   parameter 
+   PKT_QOS_H                  = 109,
+   PKT_QOS_L                  = 106,
+   PKT_DATA_SIDEBAND_H        = 105,
+   PKT_DATA_SIDEBAND_L        = 98,
+   PKT_ADDR_SIDEBAND_H        = 97, 
+   PKT_ADDR_SIDEBAND_L        = 93,
+   PKT_CACHE_H                = 92,
+   PKT_CACHE_L                = 89,
+   PKT_THREAD_ID_H            = 88,
+   PKT_THREAD_ID_L            = 87,
+   PKT_BEGIN_BURST            = 81,
+   PKT_PROTECTION_H           = 80,
+   PKT_PROTECTION_L           = 80,
+   PKT_BURSTWRAP_H            = 79,
+   PKT_BURSTWRAP_L            = 77,
+   PKT_BYTE_CNT_H             = 76,
+   PKT_BYTE_CNT_L             = 74,
+   PKT_ADDR_H                 = 73,
+   PKT_ADDR_L                 = 42,
+   PKT_BURST_SIZE_H           = 86,
+   PKT_BURST_SIZE_L           = 84,
+   PKT_BURST_TYPE_H           = 94,
+   PKT_BURST_TYPE_L           = 93,
+   PKT_TRANS_EXCLUSIVE        = 83,
+   PKT_TRANS_LOCK             = 82,
+   PKT_TRANS_COMPRESSED_READ  = 41,
+   PKT_TRANS_POSTED           = 40,
+   PKT_TRANS_WRITE            = 39,
+   PKT_TRANS_READ             = 38,
+   PKT_DATA_H                 = 37,
+   PKT_DATA_L                 = 6,
+   PKT_BYTEEN_H               = 5,
+   PKT_BYTEEN_L               = 2,
+   PKT_SRC_ID_H               = 1,
+   PKT_SRC_ID_L               = 1,
+   PKT_DEST_ID_H              = 0,
+   PKT_DEST_ID_L              = 0,
+   PKT_RESPONSE_STATUS_L      = 110,
+   PKT_RESPONSE_STATUS_H      = 111,
+   PKT_ORI_BURST_SIZE_L       = 112,
+   PKT_ORI_BURST_SIZE_H       = 114,
+   ST_DATA_W                  = 115,
+   ST_CHANNEL_W               = 1,
+
+   // -------------------
+   // Agent Parameters
+   // -------------------
+   AV_BURSTCOUNT_W       = 3,
+   ID                    = 1,
+   SUPPRESS_0_BYTEEN_RSP = 1,
+   BURSTWRAP_VALUE       = 4,
+   CACHE_VALUE           = 0,
+   SECURE_ACCESS_BIT     = 1,
+   USE_READRESPONSE      = 0,
+   USE_WRITERESPONSE     = 0,
+
+   // -------------------
+   // Derived Parameters
+   // -------------------
+   PKT_BURSTWRAP_W   = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+   PKT_BYTE_CNT_W    = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+   PKT_PROTECTION_W  = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
+   PKT_ADDR_W        = PKT_ADDR_H - PKT_ADDR_L + 1,
+   PKT_DATA_W        = PKT_DATA_H - PKT_DATA_L + 1,
+   PKT_BYTEEN_W      = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   PKT_SRC_ID_W      = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
+   PKT_DEST_ID_W     = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
+   PKT_BURST_SIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
+) (
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input                         clk,
+   input                         reset,
+
+   // -------------------
+   // Avalon-MM Anti-Master
+   // -------------------
+   input [PKT_ADDR_W-1 : 0]      av_address,
+   input                         av_write,
+   input                         av_read,
+   input [PKT_DATA_W-1 : 0]      av_writedata,
+   output reg [PKT_DATA_W-1 : 0] av_readdata,
+   output reg                    av_waitrequest,
+   output reg                    av_readdatavalid,
+   input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
+   input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
+   input                         av_debugaccess,
+   input                         av_lock,
+   output reg [1 : 0]            av_response,
+   output reg                    av_writeresponsevalid,
+
+   // -------------------
+   // Command Source
+   // -------------------
+   output reg                    cp_valid,
+   output reg [ST_DATA_W-1 : 0]  cp_data,
+   output wire                   cp_startofpacket,
+   output wire                   cp_endofpacket,
+   input                         cp_ready,
+
+   // -------------------
+   // Response Sink
+   // -------------------
+   input                         rp_valid,
+   input [ST_DATA_W-1 : 0]       rp_data,
+   input [ST_CHANNEL_W-1 : 0]    rp_channel,
+   input                         rp_startofpacket,
+   input                         rp_endofpacket,
+   output reg                    rp_ready
+);
+    // ------------------------------------------------------------
+    // Utility Functions
+    // ------------------------------------------------------------
+   function integer clogb2;
+      input [31 : 0] value;
+      begin
+         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+            value = value >> 1;
+         clogb2 = clogb2 - 1;
+      end
+   endfunction // clogb2
+
+   localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
+   localparam NUMSYMBOLS   = PKT_BYTEEN_W; 
+   localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
+   localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
+   localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
+
+   typedef enum bit  [1 : 0]
+   {
+      FIXED       = 2'b00,
+      INCR        = 2'b01,
+      WRAP        = 2'b10,
+      OTHER_WRAP  = 2'b11
+   } MerlinBurstType;
+
+   // --------------------------------------
+   // Potential optimization: compare in words to save bits?
+   // --------------------------------------
+   wire is_burst;
+   assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
+
+   wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
+   wire [31 : 0] id_int              = ID; 
+   wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
+   wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
+
+   // --------------------------------------
+   // Address alignment
+   //
+   // The packet format requires that addresses be aligned to
+   // the transaction size.
+   // --------------------------------------
+   wire [PKT_ADDR_W-1 : 0] av_address_aligned;
+   generate 
+      if (NUMSYMBOLS > 1) begin
+         assign av_address_aligned = 
+         {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
+      end
+      else begin
+         assign av_address_aligned = av_address;
+      end 
+   endgenerate
+
+   // --------------------------------------
+   // Command & Response Construction
+   // --------------------------------------
+   always_comb begin
+      cp_data                                              = '0;
+
+      cp_data[PKT_PROTECTION_L]                            = av_debugaccess;    
+      cp_data[PKT_PROTECTION_L+1]                          = SECURE_ACCESS_BIT[0];  // secure cache bit
+      cp_data[PKT_PROTECTION_L+2]                          = 1'b0;                  // instruction/data cache bit
+      cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]           = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
+      cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]             = av_burstcount;
+      cp_data[PKT_ADDR_H : PKT_ADDR_L]                     = av_address_aligned;
+      cp_data[PKT_TRANS_EXCLUSIVE]                         = 1'b0;
+      cp_data[PKT_TRANS_LOCK]                              = av_lock;
+      cp_data[PKT_TRANS_COMPRESSED_READ]                   = av_read & is_burst;
+      cp_data[PKT_TRANS_READ]                              = av_read;
+      cp_data[PKT_TRANS_WRITE]                             = av_write;
+      cp_data[PKT_TRANS_POSTED]                            = av_write & !USE_WRITERESPONSE;
+      cp_data[PKT_DATA_H : PKT_DATA_L]                     = av_writedata;
+      cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L]                 = av_byteenable;
+      cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]         = burstsize_sig;
+      cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
+      cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]         = bursttype_value;
+      cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L]                 = id_int[PKT_SRC_ID_W-1 : 0];
+      cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L]           = '0;
+      cp_data[PKT_CACHE_H : PKT_CACHE_L]                   = CACHE_VALUE[3 : 0];
+      cp_data[PKT_QOS_H : PKT_QOS_L]                       = '0;        
+      cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L]   = '0;
+      cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L]   = '0;
+
+      av_readdata                                          = rp_data[PKT_DATA_H : PKT_DATA_L];
+      if (USE_WRITERESPONSE || USE_READRESPONSE)
+         av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
+      else
+         av_response = '0;
+      end
+
+   // --------------------------------------
+   // Command Control
+   // --------------------------------------
+   reg hold_waitrequest;
+
+   always @ (posedge clk, posedge reset) begin
+      if (reset)
+         hold_waitrequest <= 1'b1;
+      else
+         hold_waitrequest <= 1'b0;
+   end  
+   
+   always_comb begin
+      cp_valid = 0;
+
+      if ((av_write || av_read) && ~hold_waitrequest)
+         cp_valid = 1;
+   end
+
+   generate if (BURSTING) begin
+      reg sop_enable;
+
+      always @(posedge clk, posedge reset) begin
+         if (reset) begin
+            sop_enable <= 1'b1;
+         end
+         else begin
+            if (cp_valid && cp_ready) begin
+               sop_enable <= 1'b0;
+               if (cp_endofpacket)
+                  sop_enable <= 1'b1;
+            end
+         end
+      end
+
+      assign cp_startofpacket = sop_enable;
+      assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
+
+   end 
+   else begin
+
+      assign cp_startofpacket = 1'b1;
+      assign cp_endofpacket   = 1'b1;
+
+   end
+   endgenerate
+
+   // --------------------------------------
+   // Backpressure & Readdatavalid
+   // --------------------------------------
+   always_comb begin
+      rp_ready              = 1;
+      av_readdatavalid      = 0;
+      av_writeresponsevalid = 0;
+      av_waitrequest = hold_waitrequest | !cp_ready;
+
+      if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
+         av_writeresponsevalid = rp_valid;
+      else
+         av_readdatavalid      = rp_valid;
+
+      if (SUPPRESS_0_BYTEEN_RSP) begin
+         if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
+            av_readdatavalid = 0;
+      end
+   end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_translator.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
new file mode 100644
index 0000000..2b0d90b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
@@ -0,0 +1,556 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts an Avalon-MM master interface into an 
+// Avalon-MM "universal" master interface.
+//
+// The universal interface is defined as the superset of ports
+// and parameters that can represent any legal Avalon 
+// interface.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_translator #(
+   parameter
+      // widths
+      AV_ADDRESS_W                = 32,
+      AV_DATA_W                   = 32,
+      AV_BURSTCOUNT_W             = 4,
+      AV_BYTEENABLE_W             = 4,
+
+      UAV_ADDRESS_W               = 38,
+      UAV_BURSTCOUNT_W            = 10,
+  
+      // optional ports
+      USE_BURSTCOUNT              = 1,
+      USE_BEGINBURSTTRANSFER      = 0,
+      USE_BEGINTRANSFER           = 0,
+      USE_CHIPSELECT              = 0,
+      USE_READ                    = 1,
+      USE_READDATAVALID           = 1,
+      USE_WRITE                   = 1,
+      USE_WAITREQUEST             = 1,
+      USE_WRITERESPONSE           = 0,
+      USE_READRESPONSE            = 0,
+   
+      AV_REGISTERINCOMINGSIGNALS  = 0,
+      AV_SYMBOLS_PER_WORD         = 4,
+      AV_ADDRESS_SYMBOLS          = 0,
+      // must be enabled for a bursting master
+      AV_CONSTANT_BURST_BEHAVIOR  = 1,
+      UAV_CONSTANT_BURST_BEHAVIOR = 0,
+      AV_BURSTCOUNT_SYMBOLS       = 0,
+      AV_LINEWRAPBURSTS           = 0
+)(
+   input wire                           clk,
+   input wire                           reset,
+
+   // Universal Avalon Master
+   output reg                           uav_write,
+   output reg                           uav_read,
+   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
+   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+   output wire [AV_DATA_W -1 : 0]       uav_writedata,
+   output wire                          uav_lock,
+   output wire                          uav_debugaccess,
+   output wire                          uav_clken,
+
+   input wire [AV_DATA_W -1 : 0]        uav_readdata,
+   input wire                           uav_readdatavalid,
+   input wire                           uav_waitrequest,
+   input wire [1 : 0]                   uav_response,
+   input wire                           uav_writeresponsevalid,
+
+   // Avalon-MM Anti-master (slave)
+   input reg                            av_write,
+   input reg                            av_read,
+   input wire [AV_ADDRESS_W -1 : 0]     av_address,
+   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
+   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
+   input wire [AV_DATA_W -1 : 0]        av_writedata,
+   input wire                           av_begintransfer,
+   input wire                           av_beginbursttransfer,
+   input wire                           av_lock,
+   input wire                           av_chipselect,
+   input wire                           av_debugaccess,
+   input wire                           av_clken,
+
+   output wire [AV_DATA_W -1 : 0]       av_readdata,
+   output wire                          av_readdatavalid,
+   output reg                           av_waitrequest,
+   output reg [1 : 0]                   av_response,
+   output reg                           av_writeresponsevalid
+);
+
+   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
+   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
+   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
+   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
+   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
+
+   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
+   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
+
+   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
+   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
+
+   function integer flog2;
+      input [31:0]  depth;
+      integer       i;
+      begin
+         i = depth;
+         if ( i <= 0 ) flog2 = 0;
+         else begin
+            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
+               i = i >> 1;
+         end
+      end
+   endfunction // flog2
+
+    // ------------------------------------------------------------
+    // Calculates the ceil(log2()) of the input val.
+    //
+    // Limited to a positive 32-bit input value.
+    // ------------------------------------------------------------
+    function integer clog2;
+        input[31:0] val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            clog2 = 0;
+
+            while (i < val) begin
+                clog2 = clog2 + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+   function integer pow2;
+      input [31:0] toShift;
+      begin
+         pow2 = 1;
+         pow2 = pow2 << toShift;
+      end
+   endfunction // pow2
+
+   // -------------------------------------------------
+   // Assign some constants to appropriately-sized signals to
+   // avoid synthesis warnings. This also helps some simulators
+   // with their inferred sensitivity lists.
+   //
+   // The symbols per word calculation here rounds non-power of two
+   // symbols to the next highest power of two, which is what we want
+   // when calculating the decrementing byte count.
+   // -------------------------------------------------
+   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
+   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
+
+   reg                            internal_beginbursttransfer;
+   reg                            internal_begintransfer;
+   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
+   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
+
+   reg uav_read_pre;
+   reg uav_write_pre;
+   reg read_accepted;
+
+   // -------------------------------------------------
+   // Pass through signals that we don't touch
+   // -------------------------------------------------
+   assign uav_writedata    = av_writedata;
+   assign uav_byteenable   = av_byteenable;
+   assign uav_lock         = av_lock;
+   assign uav_debugaccess  = av_debugaccess;
+   assign uav_clken        = av_clken;
+
+   assign av_readdata      = uav_readdata;
+   assign av_readdatavalid = uav_readdatavalid;
+
+   // -------------------------------------------------
+   // Response signals
+   // -------------------------------------------------
+   always_comb begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
+         av_response = '0;
+      else
+         av_response = uav_response;
+
+      if (USE_WRITERESPONSE) begin
+         av_writeresponsevalid = uav_writeresponsevalid;
+      end else begin
+         av_writeresponsevalid = '0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert byte and word addresses into byte addresses
+   // -------------------------------------------------
+   always_comb begin
+      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
+
+      if (AV_ADDRESS_SYMBOLS)
+         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      else begin
+         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert burstcount into symbol units
+   // -------------------------------------------------
+   always_comb begin
+      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
+
+      if (USE_BURSTCOUNT) begin
+         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
+         if (AV_BURSTCOUNT_SYMBOLS)
+            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         else begin
+            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // This is where we perform the per-transfer address and burstcount 
+   // calculations that are required by downstream modules.
+   // -------------------------------------------------
+   reg [UAV_ADDRESS_W -1 : 0] address_register;
+   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
+   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
+
+   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
+
+   always_comb begin
+      uav_address = uav_address_pre;
+      uav_burstcount = uav_burstcount_pre;
+
+      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+         uav_address = address_register;
+         uav_burstcount = burstcount_register;
+      end
+   end
+
+   reg first_burst_stalled;
+   reg burst_stalled;
+
+   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
+   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
+
+   generate
+      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
+         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+         end
+         else begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+         end
+      end
+      else begin
+         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         address_register <= '0;
+         burstcount_register_lint <= '0;
+      end else begin
+         address_register <= address_register;
+         burstcount_register_lint <= burstcount_register_lint;
+
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               address_register <= uav_address_pre;
+               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
+            end else begin
+               address_register <= combi_burst_addr_reg;
+               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               address_register <= combi_addr_reg;
+               burstcount_register_lint <= burstcount_register - symbols_per_word;
+            end
+         end
+      end
+   end
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         first_burst_stalled <= 1'b0;
+         burst_stalled <= 1'b0;
+      end else begin
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               first_burst_stalled <= 1'b1;
+            end else begin
+               first_burst_stalled <= 1'b0;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               burst_stalled <= 1'b0;
+            end else begin
+               burst_stalled <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // Waitrequest translation
+   // -------------------------------------------------
+   always @(posedge clk, posedge reset) begin
+      if (reset)
+         read_accepted <= 1'b0;
+      else begin
+         read_accepted <= read_accepted;
+         if (read_accepted == 0)
+            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
+            read_accepted <= 1'b0;
+      end
+
+   end
+
+   reg write_accepted = 0;
+   generate if (AV_REGISTERINCOMINGSIGNALS) begin
+      always @(posedge clk, posedge reset) begin
+         if (reset)
+            write_accepted <= 1'b0;
+         else begin
+            write_accepted <=
+            ~av_waitrequest ? 1'b0 :
+            uav_write & ~uav_waitrequest? 1'b1 :
+            write_accepted;
+         end
+      end
+   end endgenerate
+
+   always_comb begin
+      av_waitrequest = uav_waitrequest;
+
+      if (USE_READDATAVALID == 0) begin
+         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+      end
+
+      if (AV_REGISTERINCOMINGSIGNALS) begin
+         av_waitrequest =
+            uav_read_pre ? ~uav_readdatavalid :
+            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+            1'b1;
+      end
+
+      if (USE_WAITREQUEST == 0) begin
+         av_waitrequest = 0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Determine the output read and write signals from 
+   // the read/write/chipselect input signals.
+   // -------------------------------------------------
+   always_comb begin
+      uav_write      =  1'b0;
+      uav_write_pre  =  1'b0;
+      uav_read       =  1'b0;
+      uav_read_pre   =  1'b0;
+
+      if (!USE_CHIPSELECT) begin
+         if (USE_READ) begin
+            uav_read_pre = av_read;
+         end
+     
+         if (USE_WRITE) begin
+            uav_write_pre = av_write;
+         end
+      end else begin
+         if (!USE_WRITE && USE_READ) begin
+            uav_write_pre = av_chipselect & ~av_read;
+            uav_read_pre = av_read;
+         end else if (!USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_chipselect & ~av_write;
+         end else if (USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_read;
+         end
+      end
+
+      if (USE_READDATAVALID == 0)
+         uav_read = uav_read_pre & ~read_accepted;
+      else
+         uav_read = uav_read_pre;
+
+      if (AV_REGISTERINCOMINGSIGNALS == 0)
+         uav_write = uav_write_pre;
+      else
+         uav_write = uav_write_pre & ~write_accepted;
+   end
+
+   // -------------------------------------------------
+   // Begintransfer assignment
+   // -------------------------------------------------
+   reg end_begintransfer;
+
+   always_comb begin
+      if (USE_BEGINTRANSFER) begin
+         internal_begintransfer = av_begintransfer;
+      end else begin
+         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if (internal_begintransfer == 1 && uav_waitrequest)
+            end_begintransfer <= 1'b1;
+         else if (uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Beginbursttransfer assignment
+   // -------------------------------------------------
+   reg   end_beginbursttransfer;
+   wire  last_burst_transfer_pre;
+   wire  last_burst_transfer_reg;
+   wire  last_burst_transfer;
+
+   // compare values before the mux to shorten critical path; benchmark before changing
+   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+   always_comb begin
+      if (USE_BEGINBURSTTRANSFER) begin
+         internal_beginbursttransfer = av_beginbursttransfer;
+      end else begin
+         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_beginbursttransfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= end_beginbursttransfer;
+         if (last_burst_transfer && internal_begintransfer || uav_read) begin
+            end_beginbursttransfer <= 1'b0;
+         end
+         else if (uav_write && internal_begintransfer) begin
+            end_beginbursttransfer <= 1'b1;
+         end
+      end
+   end
+
+   // synthesis translate_off
+
+   // ------------------------------------------------
+   // check_1   : for waitrequest signal violation
+   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
+   // Exception : begintransfer / beginbursttransfer
+   //           : previously not in any transaction (idle)
+   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
+   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
+   // ------------------------------------------------
+
+   reg av_waitrequest_r;
+   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
+   reg [AV_ADDRESS_W-1:0]    av_address_r;
+   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
+   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
+   reg [AV_DATA_W-1:0]       av_writedata_r;
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         av_waitrequest_r           <= '0;
+         av_write_r                 <= '0;
+         av_read_r                  <= '0;
+         av_lock_r                  <= '0;
+         av_chipselect_r            <= '0;
+         av_debugaccess_r           <= '0;
+         av_address_r               <= '0;
+         av_byteenable_r            <= '0;
+         av_burstcount_r            <= '0;
+         av_writedata_r             <= '0;
+      end else begin
+         av_waitrequest_r           <= av_waitrequest;
+         av_write_r                 <= av_write;
+         av_read_r                  <= av_read;
+         av_lock_r                  <= av_lock;
+         av_chipselect_r            <= av_chipselect;
+         av_debugaccess_r           <= av_debugaccess;
+         av_address_r               <= av_address;
+         av_byteenable_r            <= av_byteenable;
+         av_burstcount_r            <= av_burstcount;
+         av_writedata_r             <= av_writedata;
+   
+         if (
+            av_waitrequest_r && // When waitrequest is asserted
+            (
+               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
+               (av_read                   != av_read_r)  ||
+               (av_lock                   != av_lock_r)  ||
+               (av_debugaccess            != av_debugaccess_r) ||
+               (av_address                != av_address_r) ||
+               (av_byteenable             != av_byteenable_r) ||
+               (av_burstcount             != av_burstcount_r)
+            )  &&
+            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
+            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
+         ) begin
+            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
+            $display("av_address                %x --> %x", av_address_r               , av_address               );
+            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
+            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
+            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
+            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
+            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
+            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
+            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
+            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
+         end
+      end
+   
+   // end check_1
+   
+   end
+
+  // synthesis translate_on
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv
new file mode 100644
index 0000000..3189332
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv
@@ -0,0 +1,297 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_reorder_memory.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------------------------------
+// Merlin Order Memory: this stores responses from slave
+// and do reorder. The memory structure is normal memory
+// with many segments for different responses that master
+// can handle.
+// The number of segment is the number of MAX_OUTSTANDING_RESPONSE
+// ------------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+module altera_merlin_reorder_memory 
+#(
+   parameter  DATA_W         = 32,
+              ADDR_H_W       = 4, // width to represent how many segments
+              ADDR_L_W       = 4,
+              VALID_W        = 4,
+              NUM_SEGMENT    = 4,
+              DEPTH          = 16
+
+)
+    
+(
+    // -------------------
+    // Clock
+    // -------------------
+    input                       clk,
+    input                       reset,
+    // -------------------
+    // Signals
+    // -------------------
+    input [DATA_W - 1 : 0]      in_data,
+    input                       in_valid,
+    output                      in_ready,
+ 
+    output reg [DATA_W - 1 : 0] out_data,
+    output reg                  out_valid,
+    input                       out_ready,
+    // --------------------------------------------
+    // wr_segment: select write portion of memory
+    // rd_segment: select read portion of memory
+    // --------------------------------------------
+    input [ADDR_H_W - 1 : 0]    wr_segment,
+    input [ADDR_H_W - 1 : 0]    rd_segment
+ 
+);
+
+    // -------------------------------------
+    // Local parameter
+    // -------------------------------------
+    localparam SEGMENT_W  = ADDR_H_W;
+    
+    wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr;
+    reg [ADDR_H_W + ADDR_L_W - 1 : 0]  mem_rd_addr;
+    wire [ADDR_L_W - 1 : 0]            mem_wr_ptr;
+    wire [ADDR_L_W - 1 : 0]            mem_rd_ptr;
+    reg [ADDR_L_W - 1 : 0]             mem_next_rd_ptr;
+    reg [DATA_W - 1 : 0]               out_payload;
+    
+    wire [NUM_SEGMENT - 1 : 0]         pointer_ctrl_in_ready;
+    wire [NUM_SEGMENT - 1 : 0]         pointer_ctrl_in_valid;
+    wire [NUM_SEGMENT - 1 : 0]         pointer_ctrl_out_valid;
+    wire [NUM_SEGMENT - 1 : 0]         pointer_ctrl_out_ready;
+    wire [ADDR_L_W - 1 : 0]            pointer_ctrl_wr_ptr [NUM_SEGMENT];
+    wire [ADDR_L_W - 1 : 0]            pointer_ctrl_rd_ptr [NUM_SEGMENT];
+    wire [ADDR_L_W - 1 : 0]            pointer_ctrl_next_rd_ptr [NUM_SEGMENT];
+    
+    // ---------------------------------
+    // Memory storage
+    // ---------------------------------
+    (* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0]               mem [DEPTH - 1 : 0];
+	always @(posedge clk) begin
+		if (in_valid && in_ready)
+			mem[mem_wr_addr] = in_data;
+        out_payload = mem[mem_rd_addr];
+	end
+    //assign mem_rd_addr  = {rd_segment, mem_next_rd_ptr};
+    
+    always_comb
+       begin
+           out_data  = out_payload;
+           out_valid = pointer_ctrl_out_valid[rd_segment];
+       end
+    // ---------------------------------
+    // Memory addresses
+    // ---------------------------------
+    assign mem_wr_ptr       = pointer_ctrl_wr_ptr[wr_segment];
+    //assign mem_rd_ptr       = pointer_ctrl_rd_ptr[rd_segment];
+    //assign mem_next_rd_ptr  = pointer_ctrl_next_rd_ptr[rd_segment];
+
+    assign mem_wr_addr  = {wr_segment, mem_wr_ptr};
+
+    // ---------------------------------------------------------------------------
+    // Bcos want, empty latency, mean assert read the data will appear on out_data. 
+    // And need to jump around different segment of the memory. 
+    // So when seeing endofpacket for this current segment, the read address
+    // will jump to next segment at first read address, so that the data will be ready
+    // it is okay to jump to next segment as this is the sequence of all transaction
+    // and they just increment. (standing at segment 0, then for sure next segment 1)
+    // ----------------------------------------------------------------------------
+    wire endofpacket;
+    assign endofpacket  = out_payload[0];
+    wire [ADDR_H_W - 1: 0] next_rd_segment;
+    assign next_rd_segment  = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1;
+
+    always_comb
+        begin
+            if (out_valid && out_ready && endofpacket)
+                begin
+                    mem_next_rd_ptr  = pointer_ctrl_rd_ptr[next_rd_segment];
+                    //mem_rd_addr      = {rd_segment + 1'b1, mem_next_rd_ptr};
+					mem_rd_addr      = {next_rd_segment, mem_next_rd_ptr};
+					
+                end
+            else
+                begin
+                    mem_next_rd_ptr  = pointer_ctrl_next_rd_ptr[rd_segment];
+                    mem_rd_addr      = {rd_segment, mem_next_rd_ptr};
+                end
+        end
+    
+    
+    // ---------------------------------
+    // Output signals
+    // ---------------------------------
+    assign in_ready  = pointer_ctrl_in_ready[wr_segment];
+    
+    // ---------------------------------
+    // Control signals for each segment
+    // ---------------------------------
+    genvar j;
+    generate
+        for (j = 0; j < NUM_SEGMENT; j = j + 1)
+            begin : pointer_signal
+                assign pointer_ctrl_in_valid[j]  = (wr_segment == j) && in_valid;
+                assign pointer_ctrl_out_ready[j]  = (rd_segment == j) && out_ready;
+                
+            end
+    endgenerate
+    
+    // ---------------------------------
+    // Seperate write and read pointer
+    // for each segment in memory
+    // ---------------------------------
+    genvar i;
+    generate
+        for (i = 0; i < NUM_SEGMENT; i = i + 1)
+            begin : each_segment_pointer_controller
+	            memory_pointer_controller 
+                 #(
+                   .ADDR_W   (ADDR_L_W)
+                   ) reorder_memory_pointer_controller
+                 (
+                  .clk              (clk),
+                  .reset            (reset),                  
+                  .in_ready         (pointer_ctrl_in_ready[i]),
+                  .in_valid         (pointer_ctrl_in_valid[i]),
+                  .out_ready        (pointer_ctrl_out_ready[i]),
+                  .out_valid    	(pointer_ctrl_out_valid[i]),                  
+		          .wr_pointer    	(pointer_ctrl_wr_ptr[i]),
+                  .rd_pointer       (pointer_ctrl_rd_ptr[i]),
+                  .next_rd_pointer  (pointer_ctrl_next_rd_ptr[i])
+                  );
+            end // block: each_segment_pointer_controller
+    endgenerate
+endmodule
+
+
+module memory_pointer_controller 
+#(
+    parameter ADDR_W   = 4
+)
+(
+    // -------------------
+    // Clock
+    // -------------------
+    input                   clk,
+    input                   reset,
+    // -------------------
+    // Signals
+    // -------------------
+    output reg              in_ready,
+	input                   in_valid,
+    input                   out_ready,
+    output reg              out_valid,
+	// -------------------------------
+    // Output write and read pointer
+    // -------------------------------
+	output [ADDR_W - 1 : 0] wr_pointer,
+	output [ADDR_W - 1 : 0] rd_pointer,
+    output [ADDR_W - 1 : 0] next_rd_pointer
+);
+
+	reg [ADDR_W - 1 : 0]      	incremented_wr_ptr;
+	reg [ADDR_W - 1 : 0]      	incremented_rd_ptr;
+	reg [ADDR_W - 1 : 0]      	wr_ptr;
+	reg [ADDR_W - 1 : 0]      	rd_ptr;
+	reg [ADDR_W - 1 : 0]		next_wr_ptr;
+	reg [ADDR_W - 1 : 0]		next_rd_ptr;
+	reg full, empty, next_full, next_empty;
+	reg read, write, internal_out_ready, internal_out_valid;
+	
+	assign incremented_wr_ptr = wr_ptr + 1'b1;
+	assign incremented_rd_ptr = rd_ptr + 1'b1;
+	assign next_wr_ptr =  write ?  incremented_wr_ptr : wr_ptr;
+	assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr;
+	assign wr_pointer  = wr_ptr;
+    assign rd_pointer  = rd_ptr;
+    assign next_rd_pointer  = next_rd_ptr;
+    
+	// -------------------------------
+    // Define write and read signals
+    // --------------------------------
+    // internal read, if it has any valid data
+    // and output are ready to accepts data then a read will be performed.
+    // -------------------------------
+	//assign read  = internal_out_ready && internal_out_valid;
+    assign read  = internal_out_ready && !empty;
+	assign write = in_ready && in_valid;
+
+	always_ff @(posedge clk or posedge reset) 
+        begin
+		    if (reset) 
+                begin
+			        wr_ptr <= 0;
+			        rd_ptr <= 0;
+		        end 
+            else 
+                begin
+			        wr_ptr <= next_wr_ptr;
+			        rd_ptr <= next_rd_ptr;
+		        end
+	    end
+    // ---------------------------------------------------------------------------
+	// Generate full/empty signal for memory
+    // if read and next read pointer same as write, set empty, write will clear empty
+    // if write and next write pointer same as read, set full, read will clear full
+    // -----------------------------------------------------------------------------
+	always_comb 
+        begin
+            next_full = full;
+            next_empty = empty;
+		    if (read && !write) 
+                begin
+			        next_full = 1'b0;
+			        if (incremented_rd_ptr == wr_ptr)
+				        next_empty = 1'b1;
+                end
+		    if (write && !read) 
+                begin
+                    next_empty = 1'b0;
+                    if (incremented_wr_ptr == rd_ptr)
+                        next_full = 1'b1;
+		        end
+	    end // always_comb
+    
+    always_ff @(posedge clk or posedge reset) 
+        begin
+            if (reset) 
+                begin
+                    empty <= 1;
+                    full  <= 0;
+                end
+            else 
+                begin 
+                    empty <= next_empty;
+                    full  <= next_full;
+                end
+        end
+
+	// --------------------
+    // Control signals
+    // --------------------
+    always_comb
+        begin
+            in_ready            = !full;
+            out_valid           = !empty;
+            internal_out_ready  = out_ready;
+		end // always_comb
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
new file mode 100644
index 0000000..3a4d90b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv
@@ -0,0 +1,622 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_agent
+#(
+   // Packet parameters
+   parameter PKT_BEGIN_BURST           = 81,
+   parameter PKT_DATA_H                = 31,
+   parameter PKT_DATA_L                = 0,
+   parameter PKT_SYMBOL_W              = 8,
+   parameter PKT_BYTEEN_H              = 71,
+   parameter PKT_BYTEEN_L              = 68,
+   parameter PKT_ADDR_H                = 63,
+   parameter PKT_ADDR_L                = 32,
+   parameter PKT_TRANS_LOCK            = 87,
+   parameter PKT_TRANS_COMPRESSED_READ = 67,
+   parameter PKT_TRANS_POSTED          = 66, 
+   parameter PKT_TRANS_WRITE           = 65,
+   parameter PKT_TRANS_READ            = 64,
+   parameter PKT_SRC_ID_H              = 74,
+   parameter PKT_SRC_ID_L              = 72,
+   parameter PKT_DEST_ID_H             = 77,
+   parameter PKT_DEST_ID_L             = 75,
+   parameter PKT_BURSTWRAP_H           = 85,
+   parameter PKT_BURSTWRAP_L           = 82,
+   parameter PKT_BYTE_CNT_H            = 81,
+   parameter PKT_BYTE_CNT_L            = 78,
+   parameter PKT_PROTECTION_H          = 86,
+   parameter PKT_PROTECTION_L          = 86,
+   parameter PKT_RESPONSE_STATUS_H     = 89,
+   parameter PKT_RESPONSE_STATUS_L     = 88,
+   parameter PKT_BURST_SIZE_H          = 92,
+   parameter PKT_BURST_SIZE_L          = 90,
+   parameter PKT_ORI_BURST_SIZE_L      = 93,
+   parameter PKT_ORI_BURST_SIZE_H      = 95,
+   parameter ST_DATA_W                 = 96,
+   parameter ST_CHANNEL_W              = 32,
+
+   // Slave parameters
+   parameter ADDR_W           = PKT_ADDR_H - PKT_ADDR_L + 1,
+   parameter AVS_DATA_W       = PKT_DATA_H - PKT_DATA_L + 1,
+   parameter AVS_BURSTCOUNT_W = 4,
+   parameter PKT_SYMBOLS      = AVS_DATA_W / PKT_SYMBOL_W,
+
+   // Slave agent parameters
+   parameter PREVENT_FIFO_OVERFLOW = 0,
+   parameter SUPPRESS_0_BYTEEN_CMD = 1,
+   parameter USE_READRESPONSE      = 0,
+   parameter USE_WRITERESPONSE     = 0,
+
+   // Derived slave parameters
+   parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   parameter BURST_SIZE_W = 3,
+
+   // Derived FIFO width
+   parameter FIFO_DATA_W = ST_DATA_W + 1,
+   
+   // ECC parameter
+   parameter ECC_ENABLE = 0
+) (
+   input                         clk,
+   input                         reset,
+
+   // Universal-Avalon anti-slave
+   output [ADDR_W-1:0]           m0_address,
+   output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
+   output [AVS_BE_W-1:0]         m0_byteenable,
+   output                        m0_read,
+   input [AVS_DATA_W-1:0]        m0_readdata,
+   input                         m0_waitrequest,
+   output                        m0_write,
+   output [AVS_DATA_W-1:0]       m0_writedata,
+   input                         m0_readdatavalid,
+   output                        m0_debugaccess,
+   output                        m0_lock,
+   input [1:0]                   m0_response,
+   input                         m0_writeresponsevalid,
+
+   // Avalon-ST FIFO interfaces.
+   // Note: there's no need to include the "data" field here, at least for
+   // reads, since readdata is filled in from slave info.  To keep life
+   // simple, have a data field, but fill it with 0s.
+   // Av-st response fifo source interface
+   output reg [FIFO_DATA_W-1:0]  rf_source_data,
+   output                        rf_source_valid,
+   output                        rf_source_startofpacket,
+   output                        rf_source_endofpacket,
+   input                         rf_source_ready,
+
+   // Av-st response fifo sink interface
+   input [FIFO_DATA_W-1:0]       rf_sink_data,
+   input                         rf_sink_valid,
+   input                         rf_sink_startofpacket,
+   input                         rf_sink_endofpacket,
+   output                        rf_sink_ready,
+
+   // Av-st readdata fifo src interface, data and response
+   // extra 2 bits for storing RESPONSE STATUS
+   output [AVS_DATA_W+1:0]       rdata_fifo_src_data,
+   output                        rdata_fifo_src_valid,
+   input                         rdata_fifo_src_ready,
+
+   // Av-st readdata fifo sink interface
+   input [AVS_DATA_W+1:0]        rdata_fifo_sink_data,
+   input                         rdata_fifo_sink_valid,
+   output                        rdata_fifo_sink_ready,
+   input                         rdata_fifo_sink_error,
+
+   // Av-st sink command packet interface
+   output                        cp_ready,
+   input                         cp_valid,
+   input [ST_DATA_W-1:0]         cp_data,
+   input [ST_CHANNEL_W-1:0]      cp_channel,
+   input                         cp_startofpacket,
+   input                         cp_endofpacket,
+
+   // Av-st source response packet interface
+   input                         rp_ready,
+   output reg                    rp_valid,
+   output reg [ST_DATA_W-1:0]    rp_data,
+   output                        rp_startofpacket,
+   output                        rp_endofpacket
+);
+
+   // --------------------------------------------------
+   // Ceil(log2()) function log2ceil of 4 = 2
+   // --------------------------------------------------
+   function integer log2ceil;
+      input reg[63:0] val;
+      reg [63:0] i;
+   
+      begin
+         i = 1;
+         log2ceil = 0;
+
+         while (i < val) begin
+            log2ceil = log2ceil + 1;
+            i = i << 1;
+         end
+      end
+   endfunction     
+
+   // ------------------------------------------------
+   // Local Parameters
+   // ------------------------------------------------
+   localparam DATA_W       = PKT_DATA_H - PKT_DATA_L + 1;
+   localparam BE_W         = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+   localparam MID_W        = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
+   localparam SID_W        = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+   localparam BYTE_CNT_W   = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+   localparam BURSTWRAP_W  = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+   localparam BURSTSIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
+   localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
+   localparam MAX_BURST    = 1 << (AVS_BURSTCOUNT_W - 1);
+   localparam BURSTING     = (MAX_BURST > PKT_SYMBOLS);
+
+   // ------------------------------------------------
+   // Signals
+   // ------------------------------------------------
+   wire [DATA_W-1:0]      cmd_data;
+   wire [BE_W-1:0]        cmd_byteen;
+   wire [ADDR_W-1:0]      cmd_addr;
+   wire [MID_W-1:0]       cmd_mid;
+   wire [SID_W-1:0]       cmd_sid;
+   wire                   cmd_read;
+   wire                   cmd_write;
+   wire                   cmd_compressed;
+   wire                   cmd_posted;
+   wire [BYTE_CNT_W-1:0]  cmd_byte_cnt;
+   wire [BURSTWRAP_W-1:0] cmd_burstwrap;
+   wire [BURSTSIZE_W-1:0] cmd_burstsize;
+   wire                   cmd_debugaccess;
+
+   wire                   suppress_cmd;
+   wire                   byteen_asserted;
+   wire                   suppress_read;
+   wire                   suppress_write;
+   wire                   needs_response_synthesis;
+   wire                   generate_response;
+
+   // Assign command fields
+   assign cmd_data         = cp_data[PKT_DATA_H  :PKT_DATA_L  ];
+   assign cmd_byteen       = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
+   assign cmd_addr         = cp_data[PKT_ADDR_H  :PKT_ADDR_L  ];
+   assign cmd_compressed   = cp_data[PKT_TRANS_COMPRESSED_READ];
+   assign cmd_posted       = cp_data[PKT_TRANS_POSTED];
+   assign cmd_write        = cp_data[PKT_TRANS_WRITE];
+   assign cmd_read         = cp_data[PKT_TRANS_READ];
+   assign cmd_mid          = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
+   assign cmd_sid          = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+   assign cmd_byte_cnt     = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   assign cmd_burstwrap    = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   assign cmd_burstsize    = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   assign cmd_debugaccess  = cp_data[PKT_PROTECTION_L];
+
+   // Local "ready_for_command" signal: deasserted when the agent is unable to accept
+   // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
+   // ~rp_ready), ...
+   // Say, this could depend on the type of command, for example, even if the
+   // rdv FIFO is full, a write request can be accepted.  For later.
+   wire ready_for_command;
+
+   wire local_lock  = cp_valid & cp_data[PKT_TRANS_LOCK];
+   wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
+   wire local_read  = cp_valid & cp_data[PKT_TRANS_READ];
+   wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
+   wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+   generate
+      if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
+         // ---------------------------------------------------
+         // Backpressure if the slave says to, or if FIFO overflow may occur.
+         // 
+         // All commands are backpressured once the FIFO is full
+         // even if they don't need storage. This breaks a long
+         // combinatorial path from the master read/write through
+         // this logic and back to the master via the backpressure
+         // path.
+         //
+         // To avoid a loss of throughput the FIFO will be parameterized 
+         // one slot deeper. The extra slot should never be used in normal
+         // operation, but should a slave misbehave and accept one more
+         // read than it should then backpressure will kick in.
+         //
+         // An example: assume a slave with MPRT = 2. It can accept a
+         // command sequence RRWW without backpressuring. If the FIFO is
+         // only 2 deep, we'd backpressure the writes leading to loss of
+         // throughput. If the FIFO is 3 deep, we'll only backpressure when
+         // RRR... which is an illegal condition anyway.
+         // ---------------------------------------------------
+
+         assign ready_for_command = rf_source_ready;
+         assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
+
+      end else begin : no_prevent_fifo_overflow_block
+
+         // Do not suppress the command or the slave will
+         // not be able to waitrequest
+         assign ready_for_command = 1'b1;
+         // Backpressure only if the slave says to.
+         assign cp_ready = ~m0_waitrequest | suppress_cmd;
+
+      end
+   endgenerate
+
+   generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = ~byteen_asserted;
+      assign suppress_cmd     = ~byteen_asserted;
+   end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = ~byteen_asserted && cmd_read;
+   end else begin : no_suppress_0_byteen_cmd
+      assign suppress_read    = 1'b0;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = 1'b0;
+   end
+   endgenerate
+
+   // -------------------------------------------------------------------
+   // Extract avalon signals from command packet.
+   // -------------------------------------------------------------------
+   // Mask off the lower bits of address.
+   // The burst adapter before this component will break narrow sized packets
+   // into sub-bursts of length 1. However, the packet addresses are preserved,
+   // which means this component may see size-aligned addresses.
+   //
+   // Masking ensures that the addresses seen by an Avalon slave are aligned to 
+   // the full data width instead of the size.
+   //
+   // Example:
+   // output from burst adapter (datawidth=4, size=2 bytes):
+   // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
+   // expected output from slave agent:
+   // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
+   generate 
+      if (BITS_TO_MASK > 0) begin : mask_address
+
+         assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
+
+      end else begin : no_mask_address
+
+         assign m0_address = cmd_addr;
+
+      end
+   endgenerate
+
+   assign m0_byteenable = cmd_byteen;
+   assign m0_writedata  = cmd_data;
+
+   // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
+   // this sort of burst exists only in merlin fabric ST packets. What to do
+   // if we see such a burst? All beats in that burst need to be transmitted
+   // to the slave so we have enough space-time for byteenable expression.
+   //
+   // There can be multiple bursts in a packet, but only one beat per burst
+   // in <most> cases. The exception is when we've decided not to insert a
+   // burst adapter for efficiency reasons, in which case this agent is also
+   // responsible for driving burstcount to 1 on each beat of an uncompressed
+   // read burst.
+
+   assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
+
+   generate 
+       // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal.  Assign m0_burstcount
+       // from a sub-range, or 0-pad, as appropriate.
+       if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
+          wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
+          assign m0_burstcount = (local_read & ~local_compressed_read) ?
+             {zero_pad, num_symbols} :
+             {zero_pad, cmd_byte_cnt};
+       end
+       else begin : m0_burstcount_no_pad
+          assign m0_burstcount = (local_read & ~local_compressed_read) ? 
+          num_symbols[AVS_BURSTCOUNT_W-1:0] : 
+          cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
+       end
+   endgenerate
+
+   assign m0_write = ready_for_command & local_write & !suppress_write;
+   assign m0_lock  = ready_for_command & local_lock & (m0_read | m0_write);
+   assign m0_debugaccess  = cmd_debugaccess;
+
+   // -------------------------------------------------------------------
+   // Indirection layer for response packet values.  Some may always wire
+   // directly from the slave translator; others will no doubt emerge from
+   // various FIFOs.
+   // What to put in resp_data when a write occured? Answer: it does not
+   // matter, because only response status is needed for non-posted writes,
+   // and the packet already has a field for that.
+   //
+   // We use the rdata_fifo to store write responses as well. This allows us
+   // to handle backpressure on the response path, and allows write response
+   // merging.
+   assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
+   assign rdata_fifo_src_data  = {m0_response, m0_readdata};
+
+   // ------------------------------------------------------------------
+   // Generate a token when read commands are suppressed. The token
+   // is stored in the response FIFO, and will be used to synthesize 
+   // a read response. The same token is used for non-posted write
+   // response synthesis.
+   //
+   // Note: this token is not generated for suppressed uncompressed read cycles;
+   // the burst uncompression logic at the read side of the response FIFO
+   // generates the correct number of responses.
+   //
+   // When the slave can return the response, let it do its job. Don't 
+   // synthesize a response in that case, unless we've suppressed the
+   // the last transfer in a write sub-burst.
+   // ------------------------------------------------------------------
+   wire write_end_of_subburst;
+   assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || 
+                                        (!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
+                                        (USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
+
+   // Avalon-ST interfaces to external response FIFO.
+   //
+   // For efficiency, when synthesizing a write response we only store a non-posted write 
+   // transaction at its endofpacket, even if it was split into multiple sub-bursts.
+   //
+   // When not synthesizing write responses, we store each sub-burst in the FIFO.
+   // Each sub-burst to the slave will return a response, which corresponds to one 
+   // entry in the FIFO. We merge all the sub-burst responses on the final
+   // sub-burst and send it on the response channel.
+
+   wire internal_cp_endofburst;
+   wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
+   wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
+
+   assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
+   assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
+   assign write_end_of_subburst = local_write & internal_cp_endofburst;
+
+   assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
+                             & ready_for_command & cp_ready;
+   assign rf_source_startofpacket = cp_startofpacket;
+   assign rf_source_endofpacket   = cp_endofpacket;
+   always @* begin
+      // default: assign every command packet field to the response FIFO...
+      rf_source_data                                  = {1'b0, cp_data};
+
+      // ... and override select fields as needed.
+      rf_source_data[FIFO_DATA_W-1]                      = needs_response_synthesis;
+      rf_source_data[PKT_DATA_H   :PKT_DATA_L]           = {DATA_W {1'b0}};
+      rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L]         = cmd_byteen;
+      rf_source_data[PKT_ADDR_H   :PKT_ADDR_L]           = cmd_addr;
+      rf_source_data[PKT_TRANS_COMPRESSED_READ]          = cmd_compressed;
+      rf_source_data[PKT_TRANS_POSTED]                   = cmd_posted;
+      rf_source_data[PKT_TRANS_WRITE]                    = cmd_write;
+      rf_source_data[PKT_TRANS_READ]                     = cmd_read;
+      rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L]         = cmd_mid;
+      rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L]        = cmd_sid;
+      rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]      = cmd_byte_cnt;
+      rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]    = cmd_burstwrap;
+      rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]  = cmd_burstsize;
+      rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L]  = '0;
+      rf_source_data[PKT_PROTECTION_L]                   = cmd_debugaccess;
+   end
+
+   wire uncompressor_source_valid;
+   wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
+   wire last_write_response;
+
+   // last_write_response indicates the last response of the broken-up write burst (sub-bursts).
+   // At this time, the final merged response is sent, and rp_valid is only asserted
+   // once for the whole burst.
+   generate
+      if (USE_WRITERESPONSE) begin
+         assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
+         always @* begin
+            if (rf_sink_data[PKT_TRANS_WRITE] == 1) 
+               rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
+            else
+               rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end else begin
+         assign last_write_response = 1'b0;
+         always @* begin
+            rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end
+   endgenerate
+
+   // ------------------------------------------------------------------
+   // Response merging
+   // ------------------------------------------------------------------
+   reg [1:0] current_response;
+   reg [1:0] response_merged;
+   generate
+     if (USE_WRITERESPONSE) begin : response_merging_all
+        reg first_write_response;
+        reg reset_merged_output;
+        reg [1:0] previous_response_in;
+        reg [1:0]  previous_response;
+
+        always_ff @(posedge clk, posedge reset) begin
+           if (reset) begin
+              first_write_response  <= 1'b1;
+           end 
+           else begin // Merging work for write response, for read: previous_response_in = current_response
+              if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
+                 first_write_response <= 1'b0;
+                 if (rf_sink_endofpacket)
+                    first_write_response <= 1'b1;
+              end
+           end
+        end
+
+        always_comb begin
+           current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
+           reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
+           previous_response_in = reset_merged_output ? current_response : previous_response;
+           response_merged = current_response >= previous_response ? current_response: previous_response_in;
+        end
+
+        always_ff @(posedge clk or posedge reset) begin
+           if (reset) begin 
+              previous_response <= 2'b00;
+           end
+           else begin
+              if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
+                 previous_response <= response_merged;
+              end
+           end
+        end
+     end else begin : response_merging_read_only
+        always @* begin
+           current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | 
+                                                         {2{rdata_fifo_sink_error}};
+           response_merged = current_response;
+        end
+     end
+   endgenerate
+
+   assign generate_response = rf_sink_data[FIFO_DATA_W-1];
+
+   wire [BYTE_CNT_W-1:0]  rf_sink_byte_cnt   = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   wire                   rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+   wire [BURSTWRAP_W-1:0] rf_sink_burstwrap  = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   wire [BURSTSIZE_W-1:0] rf_sink_burstsize  = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   wire [ADDR_W-1:0]      rf_sink_addr       = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
+   // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
+   wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;    
+
+   wire [BYTE_CNT_W-1:0]   burst_byte_cnt;
+   wire [BURSTWRAP_W-1:0]  rp_burstwrap;
+   wire [ADDR_W-1:0]       rp_address;
+   wire                    rp_is_compressed;
+   wire                    ready_for_response;
+
+   // ------------------------------------------------------------------
+   // We're typically ready for a response if the network is ready. There
+   // is one exception:
+   //
+   // If the slave issues write responses, we only issue a merged response on 
+   // the final sub-burst. As a result, we only care about response channel 
+   // availability on the final burst when we send out the merged response.
+   // ------------------------------------------------------------------
+   assign ready_for_response = (USE_WRITERESPONSE) ? 
+                            rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: 
+                            rp_ready;
+
+   // ------------------------------------------------------------------
+   // Backpressure the readdata fifo if we're supposed to synthesize a response.
+   // This may be a read response (for suppressed reads) or a write response
+   // (for non-posted writes).
+   // ------------------------------------------------------------------
+   assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
+
+   always @* begin
+      // By default, return all fields...
+      rp_data                                               = rf_sink_data[ST_DATA_W - 1 : 0];
+
+      // ... and override specific fields.
+      rp_data[PKT_DATA_H   :PKT_DATA_L]                     = rdata_fifo_sink_data[AVS_DATA_W-1:0];
+      // Assignments directly from the response fifo.
+      rp_data[PKT_TRANS_POSTED]                             = rf_sink_data[PKT_TRANS_POSTED];
+      rp_data[PKT_TRANS_WRITE]                              = rf_sink_data[PKT_TRANS_WRITE];
+      rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]                   = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+      rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]                  = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+      rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L]                   = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+      rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L]            = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
+
+      // Burst uncompressor assignments
+      rp_data[PKT_ADDR_H   :PKT_ADDR_L]                     = rp_address;
+      rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]              = rp_burstwrap;
+      rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]                = burst_byte_cnt;
+      rp_data[PKT_TRANS_READ]                               = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+      rp_data[PKT_TRANS_COMPRESSED_READ]                    = rp_is_compressed;
+
+      rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L]  = response_merged;
+      rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]            = uncompressor_burstsize;
+      // bounce the original size back to the master untouched
+      rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]    = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
+   end
+
+   // ------------------------------------------------------------------
+   // Note: the burst uncompressor may be asked to generate responses for
+   // write packets; these are treated the same as single-cycle uncompressed 
+   // reads.
+   // ------------------------------------------------------------------
+   altera_merlin_burst_uncompressor #(
+      .ADDR_W               (ADDR_W),
+      .BURSTWRAP_W          (BURSTWRAP_W),
+      .BYTE_CNT_W           (BYTE_CNT_W),
+      .PKT_SYMBOLS          (PKT_SYMBOLS),
+      .BURST_SIZE_W         (BURSTSIZE_W)
+   ) uncompressor (
+      .clk                  (clk),
+      .reset                (reset),
+      .sink_startofpacket   (rf_sink_startofpacket_wire),
+      .sink_endofpacket     (rf_sink_endofpacket),
+      .sink_valid           (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
+      .sink_ready           (rf_sink_ready),
+      .sink_addr            (rf_sink_addr),
+      .sink_burstwrap       (rf_sink_burstwrap),
+      .sink_byte_cnt        (rf_sink_byte_cnt),
+      .sink_is_compressed   (rf_sink_compressed),
+      .sink_burstsize       (rf_sink_burstsize),
+
+      .source_startofpacket (rp_startofpacket),
+      .source_endofpacket   (rp_endofpacket),
+      .source_valid         (uncompressor_source_valid),
+      .source_ready         (ready_for_response),
+      .source_addr          (rp_address),
+      .source_burstwrap     (rp_burstwrap),
+      .source_byte_cnt      (burst_byte_cnt),
+      .source_is_compressed (rp_is_compressed),
+      .source_burstsize     (uncompressor_burstsize)
+   );
+
+   //--------------------------------------
+   // Assertion: In case slave support response. The slave needs return response in order
+   // Ex: non-posted write followed by a read: write response must complete before read data 
+   //--------------------------------------
+   // synthesis translate_off      
+   ERROR_write_response_and_read_response_cannot_happen_same_time:
+   assert property ( @(posedge clk)
+      disable iff (reset) !(m0_writeresponsevalid  && m0_readdatavalid)
+   );    
+
+   // synthesis translate_on
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
new file mode 100644
index 0000000..2e65068
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
@@ -0,0 +1,482 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon  MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator #(
+   parameter
+   //Widths
+   AV_ADDRESS_W           = 32,
+   AV_DATA_W              = 32,
+   AV_BURSTCOUNT_W        = 4,
+   AV_BYTEENABLE_W        = 4,
+   UAV_BYTEENABLE_W       = 4,
+
+   //Read Latency
+   AV_READLATENCY          = 1,
+
+   //Timing
+   AV_READ_WAIT_CYCLES     = 0,
+   AV_WRITE_WAIT_CYCLES    = 0,
+   AV_SETUP_WAIT_CYCLES    = 0,
+   AV_DATA_HOLD_CYCLES     = 0,
+
+   //Optional Port Declarations
+   USE_READDATAVALID       = 1,
+   USE_WAITREQUEST         = 1,
+   USE_READRESPONSE        = 0,
+   USE_WRITERESPONSE       = 0,
+
+   //Variable Addressing
+   AV_SYMBOLS_PER_WORD     = 4,
+   AV_ADDRESS_SYMBOLS      = 0,
+   AV_BURSTCOUNT_SYMBOLS   = 0,
+   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
+   UAV_ADDRESS_W           = 38,
+   UAV_BURSTCOUNT_W        = 10,
+   UAV_DATA_W              = 32,
+
+   AV_CONSTANT_BURST_BEHAVIOR       = 0,
+   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
+   CHIPSELECT_THROUGH_READLATENCY   = 0,
+
+   // Tightly-Coupled Options
+   USE_UAV_CLKEN           = 0,
+   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+) (
+
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input wire                             clk,
+   input wire                             reset,
+
+   // -------------------
+   // Universal Avalon Slave
+   // -------------------
+
+   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
+   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
+   input wire                             uav_write,
+   input wire                             uav_read,
+   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
+   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
+   input wire                             uav_lock,
+   input wire                             uav_debugaccess,
+   input wire                             uav_clken,
+
+   output logic                           uav_readdatavalid,
+   output logic                           uav_waitrequest,
+   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
+   output logic [1:0]                     uav_response,
+   // input wire                             uav_writeresponserequest,
+   output logic                           uav_writeresponsevalid,
+
+   // -------------------
+   // Customizable Avalon Master
+   // -------------------
+   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
+   output logic [AV_DATA_W - 1 : 0]       av_writedata,
+   output logic                           av_write,
+   output logic                           av_read,
+   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+   output logic                           av_begintransfer,
+   output wire                            av_chipselect,
+   output logic                           av_beginbursttransfer,
+   output logic                           av_lock,
+   output wire                            av_clken,
+   output wire                            av_debugaccess,
+   output wire                            av_outputenable,
+
+   input logic [AV_DATA_W - 1 : 0]        av_readdata,
+   input logic                            av_readdatavalid,
+   input logic                            av_waitrequest,
+
+   input logic [1:0]                      av_response,
+   // output logic                           av_writeresponserequest,
+   input wire                             av_writeresponsevalid
+
+);
+
+   function integer clog2_plusone;
+      input [31:0] Depth;
+      integer i;
+      begin
+         i = Depth;
+         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
+            i = i >> 1;
+      end
+   endfunction
+
+   function integer max;
+      //returns the larger of two passed arguments
+      input [31:0] one;
+      input [31:0] two;
+      if(one > two)
+         max=one;
+      else
+         max=two;
+   endfunction // int
+
+   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
+   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+                                          AV_ADDRESS_W :
+                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+                                          AV_BURSTCOUNT_W :
+                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+   // Calculate the symbols per word as the power of 2 extended symbols per word
+   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
+
+   // +--------------------------------
+   // |Backwards Compatibility Signals
+   // +--------------------------------
+   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+   assign av_debugaccess = uav_debugaccess;
+
+   // +-------------------
+   // |Passthru Signals
+   // +-------------------
+
+   reg [1 : 0] av_response_delayed;
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         av_response_delayed <= 2'b0;
+      end else begin
+         av_response_delayed <= av_response;
+      end
+   end
+
+   always_comb
+   begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
+         uav_response = '0;
+      end else begin
+         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
+            uav_response = av_response;
+         end else begin
+            uav_response = av_response_delayed;
+         end
+      end
+   end
+   // assign av_writeresponserequest = uav_writeresponserequest;
+   assign uav_writeresponsevalid = av_writeresponsevalid;
+
+   //-------------------------
+   //Writedata and Byteenable
+   //-------------------------
+
+   always@* begin
+      av_byteenable = '0;
+      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   always@* begin
+      av_writedata = '0;
+      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+   end
+
+   // +-------------------
+   // |Calculated Signals
+   // +-------------------
+
+   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+         if(byteenable[i] == 1) begin
+            return i;
+         end
+      end
+
+      return '0;
+
+   endfunction
+
+   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
+   always@(posedge clk, posedge reset) begin
+      if(reset) begin
+         burstcount_reg <= '0;
+         address_reg    <= '0;
+      end else begin
+         burstcount_reg <= burstcount_reg;
+         address_reg    <= address_reg;
+         if(av_beginbursttransfer) begin
+            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+         end
+      end
+   end
+
+   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+   always@* begin
+      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+         temp_wire = decode_byteenable(uav_byteenable);
+         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+      end else begin
+         real_uav_address = uav_address;
+      end
+
+      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_address = address_reg;
+   end
+
+   always@* begin
+      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_burstcount = burstcount_reg;
+   end
+
+   always@* begin
+      av_lock = uav_lock;
+   end
+
+   // -------------------
+   // Writebyteenable Assignment
+   // -------------------
+   always@* begin
+      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   // -------------------
+   // Waitrequest Assignment
+   // -------------------
+
+   reg av_waitrequest_generated;
+   reg av_waitrequest_generated_read;
+   reg av_waitrequest_generated_write;
+   reg waitrequest_reset_override;
+   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         wait_latency_counter <= '0;
+         waitrequest_reset_override <= 1'h1;
+      end else begin
+         waitrequest_reset_override <= 1'h0;
+         wait_latency_counter <= '0;
+         if( ~uav_waitrequest | waitrequest_reset_override )
+            wait_latency_counter <= '0;
+         else if( uav_read | uav_write )
+            wait_latency_counter <= wait_latency_counter + 1'h1;
+      end
+   end
+
+
+   always @* begin
+
+      av_read  = uav_read;
+      av_write = uav_write;
+      av_waitrequest_generated         = 1'h1;
+      av_waitrequest_generated_read    = 1'h1;
+      av_waitrequest_generated_write   = 1'h1;
+
+      if(LOG2_OF_LATENCY_SUM == 1)
+         av_waitrequest_generated = 0;
+
+      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+         if(uav_write)
+            av_waitrequest_generated = av_waitrequest_generated_write;
+         else
+            av_waitrequest_generated = av_waitrequest_generated_read;
+
+      end
+
+      if(USE_WAITREQUEST) begin
+         uav_waitrequest = av_waitrequest;
+      end else begin
+         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+      end
+
+   end
+
+   // --------------
+   // Readdata Assignment
+   // --------------
+
+   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+   always@(posedge clk, posedge reset) begin
+      if(reset)
+         av_readdata_pre <= 'b0;
+      else
+         av_readdata_pre <= av_readdata;
+   end
+
+   always@* begin
+      uav_readdata = {UAV_DATA_W{1'b0}};
+      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata;
+      end else begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
+      end
+   end
+   
+   // -------------------
+   // Readdatavalid Assigment
+   // -------------------
+   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+   reg top_read_latency_shift_reg;
+
+   always@* begin
+      uav_readdatavalid=top_read_latency_shift_reg;
+      if(USE_READDATAVALID) begin
+         uav_readdatavalid = av_readdatavalid;
+      end
+   end
+
+   always@* begin
+      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+         top_read_latency_shift_reg=read_latency_shift_reg;
+      end
+      if (AV_READLATENCY > 1) begin
+         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+      end
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if (reset) begin
+         read_latency_shift_reg <= '0;
+      end else if (av_clken) begin
+         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+         end
+      end
+   end
+
+   // ------------
+   // Chipselect and OutputEnable
+   // ------------
+   reg av_chipselect_pre;
+   wire cs_extension;
+   reg av_outputenable_pre;
+   
+   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset)
+         av_outputenable_pre <= 1'b0;
+      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
+         av_outputenable_pre <= 0;
+      else
+         av_outputenable_pre <= cs_extension | uav_read;
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         av_chipselect_pre  <= 1'b0;
+      end else begin
+         av_chipselect_pre  <= 1'b0;
+         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+            if(uav_read) begin
+               av_chipselect_pre <= 1'b1;
+            end else if(cs_extension == 1) begin
+               av_chipselect_pre <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------
+   // Begintransfer Assigment
+   // -------------------
+   reg end_begintransfer;
+
+   always@* begin
+      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+            end_begintransfer <= 1'b1;
+         else if(uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------
+   // Beginbursttransfer Assigment
+   // -------------------
+   reg end_beginbursttransfer;
+   reg in_transfer;
+
+   always@* begin
+      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_beginbursttransfer <= 1'b0;
+         in_transfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+         if(uav_write && uav_burstcount == symbols_per_word)
+            in_transfer <=1'b0;
+         else if(uav_write)
+            in_transfer <=1'b1;
+      end
+   end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv
new file mode 100644
index 0000000..b30d4d7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv
@@ -0,0 +1,787 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------------
+// Merlin Traffic Limiter
+//
+// Ensures that non-posted transaction responses are returned 
+// in order of request. Out-of-order responses can happen 
+// when a master does a non-posted transaction on a slave 
+// while responses are pending from a different slave.
+//
+// Examples:
+//   1) read to any latent slave, followed by a read to a 
+//      variable-latent slave
+//   2) read to any fixed-latency slave, followed by a read 
+//      to another fixed-latency slave whose fixed latency is smaller.
+//   3) non-posted write to any latent slave, followed by a non-posted
+//      write or read to any variable-latent slave.
+//
+// This component has two implementation modes that ensure
+// response order, controlled by the REORDER parameter.
+// 
+//   0) Backpressure to prevent a master from switching slaves 
+//   until all outstanding responses have returned. We also 
+//   have to suppress the non-posted transaction, obviously.
+//
+//   1) Reorder the responses as they return using a memory
+//   block.
+// -----------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// altera message_off 10036
+module altera_merlin_traffic_limiter
+#(
+   parameter
+      PKT_TRANS_POSTED           = 1,
+      PKT_DEST_ID_H              = 0,
+      PKT_DEST_ID_L              = 0,
+      PKT_SRC_ID_H               = 0,
+      PKT_SRC_ID_L               = 0,
+      PKT_BYTE_CNT_H             = 0,
+      PKT_BYTE_CNT_L             = 0,
+      PKT_BYTEEN_H               = 0,
+      PKT_BYTEEN_L               = 0,
+      PKT_TRANS_WRITE            = 0,
+      PKT_TRANS_READ             = 0,
+      ST_DATA_W                  = 72,
+      ST_CHANNEL_W               = 32,
+
+      MAX_OUTSTANDING_RESPONSES  = 1,
+      PIPELINED                  = 0,
+      ENFORCE_ORDER              = 1,
+
+      // -------------------------------------
+      // internal: allows optimization between this
+      // component and the demux
+      // -------------------------------------
+      VALID_WIDTH                = 1,
+
+      // -------------------------------------
+      // Prevents all RAW and WAR hazards by waiting for 
+      // responses to return before issuing a command 
+      // with different direction.
+      //
+      // This is intended for Avalon masters which are 
+      // connected to AXI slaves, because of the differing
+      // ordering models for the protocols.
+      //
+      // If PREVENT_HAZARDS is 1, then the current implementation
+      // needs to know whether incoming writes will be posted or
+      // not at compile-time. Only one of SUPPORTS_POSTED_WRITES
+      // and SUPPORTS_NONPOSTED_WRITES can be 1.
+      //
+      // When PREVENT_HAZARDS is 0 there is no such restriction.
+      //
+      // It is possible to be less restrictive for memories.
+      // -------------------------------------
+      PREVENT_HAZARDS            = 0,
+
+      // -------------------------------------
+      // Used only when hazard prevention is on, but may be used
+      // for optimization work in the future.
+      // -------------------------------------
+      SUPPORTS_POSTED_WRITES     = 1,
+      SUPPORTS_NONPOSTED_WRITES  = 0,
+
+      // -------------------------------------------------
+      // Enables the reorder buffer which allows a master to 
+      // switch slaves while responses are pending.
+      // Reponses will be reordered following command issue order.
+      // -------------------------------------------------
+      REORDER                    = 0
+)
+(
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input clk,
+   input reset,
+
+   // -------------------
+   // Command
+   // -------------------
+   input                            cmd_sink_valid,
+   input [ST_DATA_W-1 : 0]          cmd_sink_data,
+   input [ST_CHANNEL_W-1 : 0]       cmd_sink_channel,
+   input                            cmd_sink_startofpacket,
+   input                            cmd_sink_endofpacket,
+   output                           cmd_sink_ready,
+
+   output reg [VALID_WIDTH-1  : 0]  cmd_src_valid,
+   output reg [ST_DATA_W-1    : 0]  cmd_src_data,
+   output reg [ST_CHANNEL_W-1 : 0]  cmd_src_channel,
+   output reg                       cmd_src_startofpacket,
+   output reg                       cmd_src_endofpacket,
+   input                            cmd_src_ready,
+
+   // -------------------
+   // Response
+   // -------------------
+   input                            rsp_sink_valid,
+   input [ST_DATA_W-1 : 0]          rsp_sink_data,
+   input [ST_CHANNEL_W-1 : 0]       rsp_sink_channel,
+   input                            rsp_sink_startofpacket,
+   input                            rsp_sink_endofpacket,
+   output reg                       rsp_sink_ready,
+
+   output reg                       rsp_src_valid,
+   output reg [ST_DATA_W-1 : 0]     rsp_src_data,
+   output reg [ST_CHANNEL_W-1 : 0]  rsp_src_channel,
+   output reg                       rsp_src_startofpacket,
+   output reg                       rsp_src_endofpacket,
+   input                            rsp_src_ready
+);
+
+   // -------------------------------------
+   // Local Parameters
+   // -------------------------------------
+   localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+   localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1);
+   localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 4;
+   localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+   localparam MAX_DEST_ID = 1 << (DEST_ID_W);
+   localparam PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+   
+   // -------------------------------------------------------
+   // Memory Parameters
+   // ------------------------------------------------------
+   localparam MAX_BYTE_CNT = 1 << (PKT_BYTE_CNT_W);
+   localparam MAX_BURST_LENGTH = log2ceil(MAX_BYTE_CNT/NUMSYMBOLS);
+
+   // Memory stores packet width, including sop and eop
+   localparam MEM_W = ST_DATA_W + ST_CHANNEL_W + 1 + 1;
+   localparam MEM_DEPTH = MAX_OUTSTANDING_RESPONSES * (MAX_BYTE_CNT/NUMSYMBOLS);
+   
+   // -----------------------------------------------------
+   // Input Stage
+   //
+   // Figure out if the destination id has changed
+   // -----------------------------------------------------
+   wire                    stage1_dest_changed;
+   wire                    stage1_trans_changed;
+   wire [PAYLOAD_W-1 : 0]  stage1_payload;
+   wire                    in_nonposted_cmd;
+   reg [ST_CHANNEL_W-1:0]  last_channel;
+   wire [DEST_ID_W-1 : 0]  dest_id;
+   reg [DEST_ID_W-1 : 0]   last_dest_id;
+   reg                     was_write;
+   wire                    is_write;
+   wire                    suppress;
+   wire                    save_dest_id;
+
+   wire                    suppress_change_dest_id;
+   wire                    suppress_max_outstanding;
+   wire                    suppress_change_trans_but_not_dest;
+   wire                    suppress_change_trans_for_one_slave;
+   
+   generate if (PREVENT_HAZARDS == 1) begin : convert_posted_to_nonposted_block
+      assign in_nonposted_cmd = 1'b1;
+   end else begin : non_posted_cmd_assignment_block
+      assign in_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0);
+   end
+   endgenerate
+
+   // ------------------------------------
+   // Optimization: for the unpipelined case, we can save the destid if
+   // this is an unsuppressed nonposted command. This eliminates
+   // dependence on the backpressure signal.
+   //
+   // Not a problem for the pipelined case.
+   // ------------------------------------
+   generate
+      if (PIPELINED) begin : pipelined_save_dest_id
+         assign save_dest_id = cmd_sink_valid & cmd_sink_ready & in_nonposted_cmd;
+      end else begin : unpipelined_save_dest_id
+         assign save_dest_id = cmd_sink_valid & ~(suppress_change_dest_id | suppress_max_outstanding) & in_nonposted_cmd;
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         last_dest_id   <= 0;
+         last_channel   <= 0;
+         was_write      <= 0;
+      end
+      else if (save_dest_id) begin
+         last_dest_id   <= dest_id;
+         last_channel   <= cmd_sink_channel;
+         was_write      <= is_write;
+      end
+   end
+
+   assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+   assign is_write = cmd_sink_data[PKT_TRANS_WRITE];
+   assign stage1_dest_changed = (last_dest_id != dest_id);
+   assign stage1_trans_changed = (was_write != is_write);
+
+   assign stage1_payload = {
+      cmd_sink_data, 
+      cmd_sink_channel,
+      cmd_sink_startofpacket,
+      cmd_sink_endofpacket,
+      stage1_dest_changed,
+      stage1_trans_changed };
+      
+   // -----------------------------------------------------
+   // (Optional) pipeline between input and output
+   // -----------------------------------------------------
+   wire                    stage2_valid;
+   reg                     stage2_ready;
+   wire [PAYLOAD_W-1 : 0]  stage2_payload;
+   
+   generate
+      if (PIPELINED == 1) begin : pipelined_limiter
+         altera_avalon_st_pipeline_base
+         #(
+            .BITS_PER_SYMBOL(PAYLOAD_W)
+         ) stage1_pipe (
+            .clk        (clk),
+            .reset      (reset),
+            .in_ready   (cmd_sink_ready),
+            .in_valid   (cmd_sink_valid),
+            .in_data    (stage1_payload),
+            .out_valid  (stage2_valid),
+            .out_ready  (stage2_ready),
+            .out_data   (stage2_payload)
+         );
+      end else begin : unpipelined_limiter
+         assign stage2_valid   = cmd_sink_valid;
+         assign stage2_payload = stage1_payload;
+         assign cmd_sink_ready = stage2_ready;
+      end
+   endgenerate
+
+   // -----------------------------------------------------
+   // Output Stage
+   // -----------------------------------------------------
+   wire [ST_DATA_W-1 : 0]  stage2_data;
+   wire [ST_CHANNEL_W-1:0] stage2_channel;
+   wire                    stage2_startofpacket;
+   wire                    stage2_endofpacket;
+   wire                    stage2_dest_changed;               
+   wire                    stage2_trans_changed;               
+   reg                     has_pending_responses;
+   reg [COUNTER_W-1 : 0]   pending_response_count;
+   reg [COUNTER_W-1 : 0]   next_pending_response_count;
+   wire                    nonposted_cmd;
+   wire                    nonposted_cmd_accepted;
+   wire                    response_accepted;
+   wire                    response_sink_accepted;
+   wire                    response_src_accepted;
+   wire                    count_is_1;
+   wire                    count_is_0;
+   reg                     internal_valid;
+   wire [VALID_WIDTH-1:0]  wide_valid;
+
+   assign { stage2_data, 
+      stage2_channel,
+      stage2_startofpacket,
+      stage2_endofpacket,
+      stage2_dest_changed,
+      stage2_trans_changed } = stage2_payload;
+
+   generate if (PREVENT_HAZARDS == 1) begin : stage2_nonposted_block
+      assign nonposted_cmd = 1'b1;
+   end else begin
+      assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0);
+   end
+   endgenerate
+
+   assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket);
+
+   // -----------------------------------------------------------------------------
+   // Use the sink's control signals here, because write responses may be dropped
+   // when hazard prevention is on.
+   //
+   // When case REORDER, move all side to rsp_source as all packets from rsp_sink will 
+   // go in the reorder memory.
+   // One special case when PREVENT_HAZARD is on, need to use reorder_memory_valid
+   // as the rsp_source will drop
+   // -----------------------------------------------------------------------------
+   
+   assign response_sink_accepted = rsp_sink_valid && rsp_sink_ready && rsp_sink_endofpacket;
+   // Avoid Qis warning when incase, no REORDER, the signal reorder_mem_valid is not in used.
+   wire   reorder_mem_out_valid;
+   wire   reorder_mem_valid;
+   generate 
+      if (REORDER) begin
+         assign reorder_mem_out_valid = reorder_mem_valid;
+      end else begin
+         assign reorder_mem_out_valid = '0;
+      end
+   endgenerate
+
+   assign response_src_accepted = reorder_mem_out_valid & rsp_src_ready & rsp_src_endofpacket;
+   assign response_accepted = (REORDER == 1) ? response_src_accepted : response_sink_accepted;
+   
+   always @* begin
+      next_pending_response_count = pending_response_count;
+
+      if (nonposted_cmd_accepted)
+         next_pending_response_count = pending_response_count + 1'b1;
+      if (response_accepted)
+         next_pending_response_count = pending_response_count - 1'b1;
+      if (nonposted_cmd_accepted && response_accepted)
+         next_pending_response_count = pending_response_count;
+   end
+
+   assign count_is_1 = (pending_response_count == 1);
+   assign count_is_0 = (pending_response_count == 0);
+   // ------------------------------------------------------------------
+   // count_max_reached : count if maximum command reach to backpressure
+   // ------------------------------------------------------------------
+   reg count_max_reached;
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         pending_response_count <= 0;
+         has_pending_responses <= 0;
+         count_max_reached     <= 0;
+      end
+      else begin
+         pending_response_count <= next_pending_response_count;
+         // synthesis translate_off
+         if (count_is_0 && response_accepted) 
+            $display("%t: %m: Error: unexpected response: pending_response_count underflow", $time());
+         // synthesis translate_on
+         has_pending_responses <= has_pending_responses 
+            && ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted)
+            || (count_is_0 && nonposted_cmd_accepted && ~response_accepted);
+            count_max_reached <= (next_pending_response_count == MAX_OUTSTANDING_RESPONSES);
+         
+      end
+   end
+
+   wire suppress_prevent_harzard_for_particular_destid;
+   wire this_destid_trans_changed;
+   genvar j;
+   generate
+      if (REORDER) begin: fifo_dest_id_write_read_control_reorder_on
+         wire [COUNTER_W - 1 : 0]    current_trans_seq_of_this_destid;
+         wire [MAX_DEST_ID - 1 : 0]  current_trans_seq_of_this_destid_valid;
+         wire [MAX_DEST_ID - 1 : 0]  responses_arrived;
+         reg [COUNTER_W - 1:0]       trans_sequence;
+         wire [MAX_DEST_ID - 1 : 0]  trans_sequence_we;
+         
+         wire [COUNTER_W : 0]        trans_sequence_plus_trans_type;
+         wire                        current_trans_type_of_this_destid;
+         wire [COUNTER_W : 0]        current_trans_seq_of_this_destid_plus_trans_type [MAX_DEST_ID];
+         // ------------------------------------------------------------
+         // Control write trans_sequence to fifos
+         //
+         // 1. when command accepted, read destid from command packet, 
+         //     write this id to the fifo (each fifo for each desitid)  
+         // 2. when response acepted, read the destid from response packet,
+         //     will know which sequence of this response, write it to
+         //     correct segment in memory.
+         //     what if two commands go to same slave, the two sequences
+         //     go time same fifo, this even helps us to maintain order
+         //     when two commands same thread to one slave.
+         // -----------------------------------------------------------
+         wire [DEST_ID_W - 1 : 0]   rsp_sink_dest_id; 
+         wire [DEST_ID_W - 1 : 0]   cmd_dest_id;
+         assign rsp_sink_dest_id = rsp_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+         
+         // write in fifo the trans_sequence and type of transaction
+         assign trans_sequence_plus_trans_type = {stage2_data[PKT_TRANS_WRITE], trans_sequence};
+
+         // read the cmd_dest_id from output of pipeline stage so that either
+         // or not, it wont affect how we write to fifo
+         assign cmd_dest_id = stage2_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+         // -------------------------------------
+         // Get the transaction_seq for that dest_id
+         // -------------------------------------
+         wire [COUNTER_W - 1: 0]    trans_sequence_rsp;
+         wire [COUNTER_W : 0]       trans_sequence_rsp_plus_trans_type;
+         wire [COUNTER_W - 1: 0]    trans_sequence_rsp_this_destid_waiting;
+         wire [COUNTER_W : 0]       sequence_and_trans_type_this_destid_waiting;
+         wire                         trans_sequence_rsp_this_destid_waiting_valid;
+         assign trans_sequence_rsp_plus_trans_type = current_trans_seq_of_this_destid_plus_trans_type[rsp_sink_dest_id];
+         assign trans_sequence_rsp                 = trans_sequence_rsp_plus_trans_type[COUNTER_W - 1: 0];
+
+         // do I need to check if this fifo is valid, it should be always valid, unless a command not yet sent
+         // and response comes back which means something weird happens.
+         // It is worth to do an assertion but now to avoid QIS warning, just do as normal ST handshaking
+         // check valid and ready
+         
+         for (j = 0; j < MAX_DEST_ID; j = j+1) 
+            begin : write_and_read_trans_sequence
+               assign trans_sequence_we[j] = (cmd_dest_id == j) && nonposted_cmd_accepted;
+               assign responses_arrived[j] = (rsp_sink_dest_id == j) && response_sink_accepted;
+            end
+   
+         // --------------------------------------------------------------------
+         // This is array of fifos, which will be created base on how many slaves
+         // that this master can see (max dest_id_width)
+         // Each fifo, will store the trans_sequence, which go to that slave
+         // On the response path, based in the response from which slave
+         // the fifo of that slave will be read, to check the sequences.
+         // and this sequence is the write address to the memory
+         // -----------------------------------------------------------------------------------
+         // There are 3 sequences run around the limiter, they have a relationship
+         // And this is how the key point of reorder work:
+         // 
+         // trans_sequence      : command sequence, each command go thru the limiter
+         //                   will have a sequence to show their order. A simple 
+         //                   counter from 0 go up and repeat.      
+         // trans_sequence_rsp   : response sequence, each response that go back to limiter,
+         //                   will be read from trans_fifos to know their sequence.
+         // expect_trans_sequence : Expected sequences for response that the master is waiting
+         //                   The limiter will hold this sequence and wait until exactly response
+         //                   for this sequence come back (trans_sequence_rsp)
+         //                   aka: if trans_sequence_rsp back is same as expect_trans_sequence
+         //                   then it is correct order, else response store in memory and
+         //                   send out to master later, when expect_trans_sequence match.
+         // ------------------------------------------------------------------------------------
+         for (j = 0;j < MAX_DEST_ID; j = j+1) begin : trans_sequence_per_fifo
+            altera_avalon_sc_fifo 
+                #(
+                  .SYMBOLS_PER_BEAT   (1),
+                  .BITS_PER_SYMBOL    (COUNTER_W + 1), // one bit extra to store type of transaction
+                  .FIFO_DEPTH         (MAX_OUTSTANDING_RESPONSES),
+                  .CHANNEL_WIDTH      (0),
+                  .ERROR_WIDTH        (0),
+                  .USE_PACKETS        (0),
+                  .USE_FILL_LEVEL     (0),
+                  .EMPTY_LATENCY      (1),
+                  .USE_MEMORY_BLOCKS  (0),
+                  .USE_STORE_FORWARD  (0),
+                  .USE_ALMOST_FULL_IF (0),
+                  .USE_ALMOST_EMPTY_IF (0)
+                  ) dest_id_fifo 
+                (
+                 .clk            (clk),
+                 .reset          (reset),
+                 .in_data         (trans_sequence_plus_trans_type),
+                 .in_valid        (trans_sequence_we[j]),
+                 .in_ready        (),     
+                 .out_data        (current_trans_seq_of_this_destid_plus_trans_type[j]),
+                 .out_valid       (current_trans_seq_of_this_destid_valid[j]),
+                 .out_ready       (responses_arrived[j]),
+                 .csr_address      (2'b00),                        // (terminated)
+                 .csr_read        (1'b0),                         // (terminated)
+                 .csr_write       (1'b0),                         // (terminated)
+                 .csr_readdata     (),                            // (terminated)
+                 .csr_writedata    (32'b00000000000000000000000000000000), // (terminated)
+                 .almost_full_data (),                            // (terminated)
+                 .almost_empty_data (),                            // (terminated)
+                 .in_startofpacket (1'b0),                         // (terminated)
+                 .in_endofpacket   (1'b0),                         // (terminated)
+                 .out_startofpacket (),                            // (terminated)
+                 .out_endofpacket   (),                            // (terminated)
+                 .in_empty        (1'b0),                         // (terminated)
+                 .out_empty       (),                            // (terminated)
+                 .in_error        (1'b0),                         // (terminated)
+                 .out_error       (),                            // (terminated)
+                 .in_channel      (1'b0),                         // (terminated)
+                 .out_channel      ()                             // (terminated)
+                 );
+         end // block: trans_sequence_per_fifo
+      
+         // -------------------------------------------------------
+         // Calculate the transaction sequence, just simple increase
+         // when each commands pass by
+         // --------------------------------------------------------
+         always @(posedge clk or posedge reset) 
+            begin
+               if (reset) begin
+                  trans_sequence   <= '0;
+               end else begin
+                  if (nonposted_cmd_accepted) 
+                     trans_sequence <= ( (trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : trans_sequence + 1'b1;
+               end
+            end
+   
+         // -------------------------------------
+         // Control Memory for reorder responses 
+         // -------------------------------------
+         wire [COUNTER_W - 1 : 0] next_rd_trans_sequence;
+         reg [COUNTER_W - 1 : 0] rd_trans_sequence;
+         reg [COUNTER_W - 1 : 0] next_expected_trans_sequence;
+         reg [COUNTER_W - 1 : 0] expect_trans_sequence;
+         wire [ST_DATA_W - 1 : 0]        reorder_mem_data;
+         wire [ST_CHANNEL_W - 1 : 0]      reorder_mem_channel;
+         wire                       reorder_mem_startofpacket;
+         wire                       reorder_mem_endofpacket;
+         wire                        reorder_mem_ready;
+         // -------------------------------------------
+         // Data to write and read from reorder memory
+         // Store everything includes channel, sop, eop
+         // -------------------------------------------
+         reg [MEM_W - 1 : 0]       mem_in_rsp_sink_data;
+         reg [MEM_W - 1 : 0]       reorder_mem_out_data;
+         always_comb
+            begin
+               mem_in_rsp_sink_data = {rsp_sink_data, rsp_sink_channel, rsp_sink_startofpacket, rsp_sink_endofpacket};
+            end
+   
+         assign next_rd_trans_sequence = ((rd_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : rd_trans_sequence + 1'b1;
+         assign next_expected_trans_sequence = ((expect_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : expect_trans_sequence + 1'b1;
+   
+         always_ff @(posedge clk, posedge reset)
+            begin
+               if (reset) begin
+                  rd_trans_sequence    <= '0;
+                  expect_trans_sequence <= '0;
+               end else begin
+                  if (rsp_src_ready && reorder_mem_valid) begin
+                     if (reorder_mem_endofpacket == 1) begin //endofpacket
+                        expect_trans_sequence <= next_expected_trans_sequence;
+                        rd_trans_sequence    <= next_rd_trans_sequence;
+                     end
+                  end
+               end
+            end // always_ff @
+   
+         // For PREVENT_HAZARD, 
+         // Case: Master Write to S0, read S1, and Read S0 back but if Write for S0
+         // not yet return then we need to backpressure this, else read S0 might take over write 
+         // This is more checking after the fifo destid, as read S1 is inserted in midle
+         // when see new packet, try to look at the fifo for that slave id, check if it
+         // type of transaction
+         assign sequence_and_trans_type_this_destid_waiting = current_trans_seq_of_this_destid_plus_trans_type[cmd_dest_id];
+         assign current_trans_type_of_this_destid = sequence_and_trans_type_this_destid_waiting[COUNTER_W];
+         assign trans_sequence_rsp_this_destid_waiting_valid = current_trans_seq_of_this_destid_valid[cmd_dest_id];
+         // it might waiting other sequence, check if different type of transaction as only for PREVENT HAZARD
+         // if comming comamnd to one slave and this slave is still waiting for response from previous command
+         // which has diiferent type of transaction, we back-pressure this command to avoid HAZARD
+         assign suppress_prevent_harzard_for_particular_destid = (current_trans_type_of_this_destid != is_write) & trans_sequence_rsp_this_destid_waiting_valid;
+         
+         // -------------------------------------
+         // Memory for reorder buffer
+         // -------------------------------------
+         altera_merlin_reorder_memory 
+            #(
+              .DATA_W     (MEM_W),
+              .ADDR_H_W   (COUNTER_W),
+              .ADDR_L_W   (MAX_BURST_LENGTH),
+              .NUM_SEGMENT (MAX_OUTSTANDING_RESPONSES),
+              .DEPTH      (MEM_DEPTH)
+              ) reorder_memory 
+               (
+                .clk          (clk),
+                .reset        (reset),              
+                .in_data      (mem_in_rsp_sink_data),
+                .in_valid     (rsp_sink_valid),
+                .in_ready     (reorder_mem_ready),
+                .out_data     (reorder_mem_out_data),
+                .out_valid    (reorder_mem_valid),              
+                .out_ready    (rsp_src_ready),              
+                .wr_segment   (trans_sequence_rsp),
+                .rd_segment   (expect_trans_sequence)             
+                );
+         // -------------------------------------
+         // Output from reorder buffer
+         // -------------------------------------
+         assign reorder_mem_data = reorder_mem_out_data[MEM_W -1 : ST_CHANNEL_W + 2];
+         assign reorder_mem_channel = reorder_mem_out_data[ST_CHANNEL_W + 2 - 1 : 2];
+         assign reorder_mem_startofpacket = reorder_mem_out_data[1];
+         assign reorder_mem_endofpacket = reorder_mem_out_data[0];
+
+         // -------------------------------------
+         // Because use generate statment
+         // so move all rsp_src_xxx controls here
+         // -------------------------------------
+         always_comb begin
+            cmd_src_data            = stage2_data;
+            rsp_src_valid           = reorder_mem_valid;
+            rsp_src_data            = reorder_mem_data;
+            rsp_src_channel         = reorder_mem_channel;
+            rsp_src_startofpacket   = reorder_mem_startofpacket;
+            rsp_src_endofpacket     = reorder_mem_endofpacket;
+            // -------------------------------------
+            // Forces commands to be non-posted if hazard prevention
+            // is on, also drops write responses
+            // -------------------------------------
+            rsp_sink_ready       = reorder_mem_ready; // now it takes ready signal from the memory not direct from master
+            if (PREVENT_HAZARDS == 1) begin
+               cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
+               
+               if (rsp_src_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
+                  rsp_src_valid = 1'b0;
+                  rsp_sink_ready = 1'b1;
+               end
+            end
+         end // always_comb
+
+      end // block: fifo_dest_id_write_read_control_reorder_on
+   endgenerate
+   
+   // -------------------------------------
+   // Pass-through command and response
+   // -------------------------------------
+
+   always_comb 
+      begin
+         cmd_src_channel         = stage2_channel;
+         cmd_src_startofpacket   = stage2_startofpacket;
+         cmd_src_endofpacket     = stage2_endofpacket;
+      end // always_comb
+   
+   // -------------------------------------
+   // When there is no REORDER requirement
+   // Just pass through signals
+   // -------------------------------------
+   generate
+      if (!REORDER) begin : use_selector_or_pass_thru_rsp
+         always_comb begin
+            cmd_src_data            = stage2_data;
+            // pass thru almost signals
+            rsp_src_valid           = rsp_sink_valid;
+            rsp_src_data            = rsp_sink_data;
+            rsp_src_channel         = rsp_sink_channel;
+            rsp_src_startofpacket   = rsp_sink_startofpacket;
+            rsp_src_endofpacket     = rsp_sink_endofpacket;
+            // -------------------------------------
+            // Forces commands to be non-posted if hazard prevention
+            // is on, also drops write responses
+            // -------------------------------------
+            rsp_sink_ready = rsp_src_ready; // take care this, should check memory empty
+            if (PREVENT_HAZARDS == 1) begin
+               cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
+
+               if (rsp_sink_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
+                  rsp_src_valid = 1'b0;
+                  rsp_sink_ready = 1'b1;
+               end
+            end
+         end // always_comb
+      end // if (!REORDER)
+   endgenerate
+
+   // --------------------------------------------------------
+   // Backpressure & Suppression
+   // --------------------------------------------------------
+   // ENFORCE_ORDER: unused option, always is 1, remove it
+   // Now the limiter will suppress when max_outstanding reach
+   // --------------------------------------------------------
+   generate
+      if (ENFORCE_ORDER) begin : enforce_order_block
+         assign suppress_change_dest_id = (REORDER == 1) ? 1'b0 : nonposted_cmd && has_pending_responses && 
+                                   (stage2_dest_changed || (PREVENT_HAZARDS == 1 && stage2_trans_changed));
+      end else begin : no_order_block
+         assign suppress_change_dest_id = 1'b0;
+      end
+   endgenerate
+
+   // ------------------------------------------------------------
+   // Even we allow change slave while still have pending responses
+   // But one special case, when PREVENT_HAZARD=1, we still allow
+   // switch slave while type of transaction change (RAW, WAR) but
+   // only to different slaves.
+   // if to same slave, we still need back pressure that to make
+   // sure no racing
+   // ------------------------------------------------------------
+
+   generate
+      if (REORDER) begin : prevent_hazard_block
+         assign suppress_change_trans_but_not_dest = nonposted_cmd && has_pending_responses && 
+                                          !stage2_dest_changed && (PREVENT_HAZARDS == 1 && stage2_trans_changed);
+      end else begin : no_hazard_block
+         assign suppress_change_trans_but_not_dest = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
+      end
+   endgenerate
+   
+   generate
+      if (REORDER) begin : prevent_hazard_block_for_particular_slave
+         assign suppress_change_trans_for_one_slave = nonposted_cmd && has_pending_responses && (PREVENT_HAZARDS == 1 && suppress_prevent_harzard_for_particular_destid);
+      end else begin : no_hazard_block_for_particular_slave
+         assign suppress_change_trans_for_one_slave = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
+      end
+   endgenerate
+   
+   // ------------------------------------------
+   // Backpressure when max outstanding transactions are reached
+   // ------------------------------------------
+   generate
+      if (REORDER) begin : max_outstanding_block
+         assign suppress_max_outstanding = count_max_reached;
+      end else begin
+         assign suppress_max_outstanding = 1'b0;
+      end
+   endgenerate
+
+   assign suppress = suppress_change_trans_for_one_slave | suppress_change_dest_id | suppress_max_outstanding;
+   assign wide_valid = { VALID_WIDTH {stage2_valid} } & stage2_channel;
+
+   always @* begin
+      stage2_ready = cmd_src_ready;
+      internal_valid = stage2_valid;
+      // --------------------------------------------------------
+      // change suppress condidtion, in case REODER it will alllow changing slave
+      // even still have pending transactions.
+      // -------------------------------------------------------
+      if (suppress) begin
+         stage2_ready = 0;
+         internal_valid = 0;
+      end
+
+      if (VALID_WIDTH == 1) begin
+         cmd_src_valid = {VALID_WIDTH{1'b0}};
+         cmd_src_valid[0] = internal_valid;
+      end else begin
+         // -------------------------------------
+         // Use the one-hot channel to determine if the destination
+         // has changed. This results in a wide valid bus
+         // -------------------------------------
+         cmd_src_valid = wide_valid;
+         if (nonposted_cmd & has_pending_responses) begin
+            if (!REORDER) begin
+               cmd_src_valid = wide_valid & last_channel;
+               // -------------------------------------
+               // Mask the valid signals if the transaction type has changed
+               // if hazard prevention is enabled
+               // -------------------------------------
+               if (PREVENT_HAZARDS == 1)
+                  cmd_src_valid = wide_valid & last_channel & { VALID_WIDTH {!stage2_trans_changed} };
+            end else begin // else: !if(!REORDER) if REORDER happen
+               if (PREVENT_HAZARDS == 1)
+                  cmd_src_valid = wide_valid & { VALID_WIDTH {!suppress_change_trans_for_one_slave} };
+               if (suppress_max_outstanding) begin
+                  cmd_src_valid = {VALID_WIDTH {1'b0}};
+               end
+
+            end 
+         end
+      end
+   end
+   
+   // --------------------------------------------------
+   // Calculates the log2ceil of the input value.
+   //
+   // This function occurs a lot... please refactor.
+   // --------------------------------------------------
+   function integer log2ceil;
+      input integer val;
+      integer i;
+
+      begin
+         i = 1;
+         log2ceil = 0;
+
+         while (i < val) begin
+            log2ceil = log2ceil + 1;
+            i = i << 1;
+         end
+      end
+   endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv
new file mode 100644
index 0000000..ed914b0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv
@@ -0,0 +1,1206 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------------
+// Merlin Width Adapter
+// -----------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_width_adapter
+#(
+    parameter IN_PKT_ADDR_L                 = 0,
+    parameter IN_PKT_ADDR_H                 = 31,
+    parameter IN_PKT_DATA_L                 = 32,
+    parameter IN_PKT_DATA_H                 = 63,
+    parameter IN_PKT_BYTEEN_L               = 64,
+    parameter IN_PKT_BYTEEN_H               = 67,
+    parameter IN_PKT_TRANS_COMPRESSED_READ  = 72,
+    parameter IN_PKT_BYTE_CNT_L             = 73,
+    parameter IN_PKT_BYTE_CNT_H             = 77,
+    parameter IN_PKT_BURSTWRAP_L            = 78,
+    parameter IN_PKT_BURSTWRAP_H            = 82,
+    parameter IN_PKT_BURST_SIZE_L           = 83,
+    parameter IN_PKT_BURST_SIZE_H           = 85,
+    parameter IN_PKT_RESPONSE_STATUS_L      = 86,
+    parameter IN_PKT_RESPONSE_STATUS_H      = 87,
+    parameter IN_PKT_TRANS_EXCLUSIVE        = 88,
+    parameter IN_PKT_BURST_TYPE_L           = 89,
+    parameter IN_PKT_BURST_TYPE_H           = 90,
+    parameter IN_PKT_ORI_BURST_SIZE_L       = 91,
+    parameter IN_PKT_ORI_BURST_SIZE_H       = 93,
+    parameter IN_PKT_TRANS_WRITE            = 94,
+    parameter IN_ST_DATA_W                  = 110,
+
+    parameter OUT_PKT_ADDR_L                = 0,
+    parameter OUT_PKT_ADDR_H                = 31,
+    parameter OUT_PKT_DATA_L                = 32,
+    parameter OUT_PKT_DATA_H                = 47,
+    parameter OUT_PKT_BYTEEN_L              = 48,
+    parameter OUT_PKT_BYTEEN_H              = 49,
+    parameter OUT_PKT_TRANS_COMPRESSED_READ = 54,
+    parameter OUT_PKT_BYTE_CNT_L            = 55,
+    parameter OUT_PKT_BYTE_CNT_H            = 59,
+    parameter OUT_PKT_BURST_SIZE_L          = 60,
+    parameter OUT_PKT_BURST_SIZE_H          = 62,
+    parameter OUT_PKT_RESPONSE_STATUS_L     = 63,
+    parameter OUT_PKT_RESPONSE_STATUS_H     = 64,
+    parameter OUT_PKT_TRANS_EXCLUSIVE       = 65,
+    parameter OUT_PKT_BURST_TYPE_L          = 66,
+    parameter OUT_PKT_BURST_TYPE_H          = 67,
+    parameter OUT_PKT_ORI_BURST_SIZE_L      = 68,
+    parameter OUT_PKT_ORI_BURST_SIZE_H      = 70,
+    parameter OUT_ST_DATA_W                 = 92,
+
+    parameter ST_CHANNEL_W                  = 32,
+    parameter OPTIMIZE_FOR_RSP              = 0,
+
+    parameter PACKING                       = 1,    // 1: Enables packing in Avalon systems
+    parameter CONSTANT_BURST_SIZE           = 1,    // 1: Optimizes for Avalon-only systems as those always have full size transactions
+    parameter RESPONSE_PATH                 = 0,    // 0: This adapter is on command path, 1: This adapter is on response path
+
+    // Address alignment can be turned off (an optimisation) if all connected
+    // masters only issue aligned addresses.
+    parameter ENABLE_ADDRESS_ALIGNMENT      = 1
+)
+( 
+    input                            clk,
+    input                            reset,
+    output reg                       in_ready,
+    input                            in_valid,
+    input      [ST_CHANNEL_W-1:0]    in_channel,
+    input      [IN_ST_DATA_W-1:0]    in_data,
+    input                            in_startofpacket,
+    input                            in_endofpacket,
+    input                            out_ready,
+    output reg                       out_valid,
+    output reg [ST_CHANNEL_W-1:0]    out_channel,
+    output reg [OUT_ST_DATA_W-1:0]   out_data,
+    output reg                       out_startofpacket,
+    output reg                       out_endofpacket,
+
+    input      [2:0]                 in_command_size_data
+);
+
+    // ------------------------------------------------------------
+    // Local Parameters
+    // ------------------------------------------------------------
+    localparam IN_NUMSYMBOLS        = IN_PKT_BYTEEN_H - IN_PKT_BYTEEN_L + 1;
+    localparam IN_DATA_W            = IN_PKT_DATA_H   - IN_PKT_DATA_L   + 1;
+    localparam IN_BYTEEN_W          = IN_NUMSYMBOLS;
+
+    localparam OUT_NUMSYMBOLS       = OUT_PKT_BYTEEN_H - OUT_PKT_BYTEEN_L + 1;
+    localparam OUT_DATA_W           = OUT_PKT_DATA_H   - OUT_PKT_DATA_L   + 1;
+    localparam OUT_BYTEEN_W         = OUT_NUMSYMBOLS;
+
+    localparam BURST_TYPE_W         = IN_PKT_BURST_TYPE_H - IN_PKT_BURST_TYPE_L + 1;
+    localparam BURST_SIZE_W         = IN_PKT_BURST_SIZE_H - IN_PKT_BURST_SIZE_L + 1;    
+    localparam RESPONSE_STATUS_W    = IN_PKT_RESPONSE_STATUS_H - IN_PKT_RESPONSE_STATUS_L + 1;
+    localparam SYMBOL_W             = IN_DATA_W / IN_NUMSYMBOLS;
+    localparam ADDRESS_W            = IN_PKT_ADDR_H     - IN_PKT_ADDR_L     + 1;
+    localparam BYTE_CNT_W           = IN_PKT_BYTE_CNT_H - IN_PKT_BYTE_CNT_L + 1;
+    localparam OUT_BYTE_CNT_W       = OUT_PKT_BYTE_CNT_H - OUT_PKT_BYTE_CNT_L + 1;
+    localparam BWRAP_W              = IN_PKT_BURSTWRAP_H - IN_PKT_BURSTWRAP_L + 1;
+    localparam SIZE_W               = 2 ** BURST_SIZE_W;
+
+    localparam RATIO                = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? 
+                                         IN_NUMSYMBOLS / OUT_NUMSYMBOLS : 
+                                         OUT_NUMSYMBOLS / IN_NUMSYMBOLS );
+    localparam WIDE_NUMSYMBOLS      = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? 
+                                         IN_NUMSYMBOLS : OUT_NUMSYMBOLS );
+    localparam WIDE_DATA            = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? 
+                                         IN_DATA_W - (OUT_NUMSYMBOLS*SYMBOL_W) : 
+                                         OUT_DATA_W - (IN_NUMSYMBOLS*SYMBOL_W));
+    localparam OUT_SEGMENT_W        = OUT_NUMSYMBOLS * SYMBOL_W;
+
+    localparam NW_BITFORSELECT_R    = clogb2(IN_NUMSYMBOLS);
+    localparam NW_BITFORSELECT_L    = clogb2(OUT_NUMSYMBOLS) - 1;
+    localparam ALIGNED_BITS_L       = clogb2(OUT_NUMSYMBOLS) - 1;
+    localparam WN_ADDR_LSBS         = clogb2(RATIO);
+    localparam WN_ADDR_SELECT       = clogb2(IN_NUMSYMBOLS);
+    localparam LOG_OUT_NUMSYMBOLS   = clogb2(OUT_NUMSYMBOLS);
+    
+    // ------------------------------------------------------------
+    // Utility Functions
+    // ------------------------------------------------------------
+
+    function integer clogb2;
+        input [63:0] value;
+        begin
+            clogb2 = 0;
+            while (value>0) begin
+                value = value >> 1;
+                clogb2 = clogb2 + 1;
+            end
+            clogb2 = clogb2 - 1;
+        end
+    endfunction // clogb2    
+
+    function integer min;
+        input [31:0] a;
+        input [31:0] b;
+        begin
+            return (a < b) ? a : b;
+        end
+    endfunction
+
+    function integer max;
+        input [31:0] a;
+        input [31:0] b;
+        begin
+            return (a > b) ? a : b;
+        end
+    endfunction
+
+    function reg [clogb2(RATIO)-1:0] mask_to_select_correct_segments_for_size;
+        input [clogb2(RATIO)-1:0] select_output_segment;
+        input [9:0]     size_ratio;
+        input int       msb_select_bit;
+
+        integer         i;
+        mask_to_select_correct_segments_for_size    = '1;
+        for (i=0; i < msb_select_bit; i = i +1'b1 ) begin
+            if (clogb2(size_ratio) > i)
+                mask_to_select_correct_segments_for_size[i]   = select_output_segment[i];
+        end
+    endfunction 
+  
+    function reg [ADDRESS_W-1:0] choose_packed_address_base_on_size;
+        input [9:0]     size_ratio;
+        input int       msb_select_bit;
+        
+        integer         i;
+        choose_packed_address_base_on_size = '1;
+        for (i=0; i < msb_select_bit; i = i +1'b1 ) begin
+            if (clogb2(size_ratio) > i)
+                choose_packed_address_base_on_size[i + NW_BITFORSELECT_R]    = 1'b0;
+        end
+    endfunction
+
+    // ------------------------------------------------------------
+    // Computes how many bytes are in this transfer, based on the size
+    // encoding.
+    // ------------------------------------------------------------
+    function reg[9:0] bytes_in_transfer;
+        input [BURST_SIZE_W-1:0] axsize;
+    
+        case (axsize)
+            4'b0000: bytes_in_transfer = 10'b0000000001;
+            4'b0001: bytes_in_transfer = 10'b0000000010;
+            4'b0010: bytes_in_transfer = 10'b0000000100;
+            4'b0011: bytes_in_transfer = 10'b0000001000;
+            4'b0100: bytes_in_transfer = 10'b0000010000;
+            4'b0101: bytes_in_transfer = 10'b0000100000;
+            4'b0110: bytes_in_transfer = 10'b0001000000;
+            4'b0111: bytes_in_transfer = 10'b0010000000;
+            4'b1000: bytes_in_transfer = 10'b0100000000;
+            4'b1001: bytes_in_transfer = 10'b1000000000;            
+            default: bytes_in_transfer = 10'b0000000001;
+        endcase
+
+    endfunction
+
+    // ------------------------------------------------------------
+    // Pseudo-field Parameters
+    //
+    // The width adapter widens the data and byteenable fields in the 
+    // output packet, thus changing the output packet format. By using 
+    // pseudo-fields, we can avoid remapping each individual field to 
+    // the output, which is a non-scalable solution. 
+    //
+    // How? Assume the packet format is { FIRST, byteen, MID, data, LAST },
+    // where byteen and data positions are interchangeable. FIRST, MID and
+    // LAST are pseudo-fields that represent the collection of fields in
+    // those positions.
+    // 
+    // Not all the pseudo-fields may exist for a given packet format. A
+    // non-existent field has reversed indices, so we have to be careful 
+    // when using them.
+    // ------------------------------------------------------------
+
+    localparam IN_FIRST_L = 0,
+               IN_FIRST_H = min(IN_PKT_BYTEEN_L, IN_PKT_DATA_L) - 1,
+               IN_MID_L   = min(IN_PKT_DATA_H, IN_PKT_BYTEEN_H) + 1,
+               IN_MID_H   = max(IN_PKT_DATA_L, IN_PKT_BYTEEN_L) - 1,
+               IN_LAST_L  = max(IN_PKT_BYTEEN_H, IN_PKT_DATA_H) + 1,
+               IN_LAST_H  = IN_ST_DATA_W - 1,
+ 
+               FIRST_EXISTS = (IN_FIRST_H >= IN_FIRST_L),
+               MID_EXISTS   = (IN_MID_H   >= IN_MID_L),
+               LAST_EXISTS  = (IN_LAST_H  >= IN_LAST_L),
+
+               FIRST_W      = IN_FIRST_H - IN_FIRST_L + 1,
+               MID_W        = IN_MID_H   - IN_MID_L   + 1,
+               LAST_W       = IN_LAST_H  - IN_LAST_L  + 1,
+
+               // -------------------------------------------------
+               // We cannot split the output map into generate blocks as we
+               // do for the inputs because address and size are mapped over
+               // the pseudo-fields. We ensure that the indices are always
+               // legal, even if the field is unused later on.
+
+               OUT_FIRST_L = 0,
+               OUT_FIRST_H = FIRST_EXISTS ? 
+                                min(OUT_PKT_BYTEEN_L, OUT_PKT_DATA_L) - 1 :
+                                OUT_FIRST_L,
+               OUT_MID_L   = min(OUT_PKT_DATA_H, OUT_PKT_BYTEEN_H) + 1,
+               OUT_MID_H   = MID_EXISTS ? 
+                                max(OUT_PKT_DATA_L, OUT_PKT_BYTEEN_L) - 1 : 
+                                OUT_MID_L,
+               OUT_LAST_L  = max(OUT_PKT_BYTEEN_H, OUT_PKT_DATA_H) + 1,
+               OUT_LAST_H  = LAST_EXISTS ? 
+                                OUT_ST_DATA_W - 1 :
+                                OUT_LAST_L;
+  
+    // ------------------------------------------------------------
+    // Signals
+    // ------------------------------------------------------------
+    reg [BURST_SIZE_W-1:0]      in_size_field; 
+    reg [IN_DATA_W-1:0]         in_data_field; 
+    reg [IN_BYTEEN_W-1:0]       in_byteen_field;
+    reg [ADDRESS_W-1:0]         in_address_field;
+    reg [ADDRESS_W-1:0]         address_from_packet;
+    reg [BYTE_CNT_W-1:0]        in_byte_cnt_field;
+    reg [BWRAP_W-1:0]           in_burstwrap_field;
+    reg [RESPONSE_STATUS_W-1:0] in_response_status_field;
+    reg                         in_cmpr_read;
+    reg                         in_lock_field;
+    reg                         in_write;
+    reg [BURST_TYPE_W-1:0]      in_burst_type_field;
+    reg [BYTE_CNT_W-1:0]        quantized_byte_cnt_field;
+                                
+    reg [BURST_SIZE_W-1:0]      out_size_field;
+    reg [OUT_DATA_W-1:0]        out_data_field;
+    reg [OUT_BYTEEN_W-1:0]      out_byteen_field;
+    reg [ADDRESS_W-1:0]         out_address_field;
+    reg                         out_cmpr_read;
+    reg [BYTE_CNT_W-1:0]        out_byte_cnt_field;
+    reg                         out_lock_field;
+    reg [BURST_TYPE_W-1:0]      out_burst_type_field;
+    reg [RESPONSE_STATUS_W-1:0] out_response_status_field;
+    
+    reg [FIRST_W-1:0]           in_first_field;
+    reg [FIRST_W-1:0]           out_first_field;
+    reg [MID_W-1:0]             in_mid_field;
+    reg [MID_W-1:0]             out_mid_field;
+    reg [LAST_W-1:0]            in_last_field;
+    reg [LAST_W-1:0]            out_last_field;
+                                
+    reg [WIDE_DATA-1:0]         data_reg;
+    reg [WIDE_NUMSYMBOLS-1:0]   byteen_reg;
+    reg [ADDRESS_W-1:0]         address_reg;
+    reg [BYTE_CNT_W-1:0]        byte_cnt_reg;
+    reg                         use_reg;
+    reg                         startofpacket_reg;
+    reg                         endofpacket_reg;
+    reg [OUT_SEGMENT_W-1:0]     mask;
+    reg [RESPONSE_STATUS_W-1:0] response_status_reg;
+    
+    
+    reg [ADDRESS_W-1:0]         int_output_sel;
+    reg [clogb2(RATIO)-1:0]     output_sel;
+    reg [OUT_SEGMENT_W-1:0]     data_array   [0:RATIO-1];
+    reg [OUT_NUMSYMBOLS-1:0]    byteen_array [0:RATIO-1];
+
+    // In narrow-to-wide adaptation, each input datum/byteenable bit maps to
+    // one of OUT_NUMSYMBOLS/IN_NUMSYMBOLS subfields in the wider output
+    // packet. (Call these subfields "segments".)  A subfield of the input
+    // address, in_bitforselect, selects the segment. Examples:
+    // 8-16 adaptation:  in_bitforselect = in_address_field[0]
+    // 8-32 adaptation:  in_bitforselect = in_address_field[1:0]
+    // 8-64 adaptation:  in_bitforselect = in_address_field[2:0]
+    // 16-32 adaptation: in_bitforselect = in_address_field[1]
+    // 32-64 adaptation: in_bitforselect = in_address_field[2]
+
+    // The width of in_bitforselect is 
+    //  log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) =
+    //  log2(RATIO)
+    
+    // The msb of in_bitforselect is driven by
+    //   in_adress_field[log2(OUT_NUMSYMBOLS) - 1]
+    // The lsb of in_adress_field is driven by
+    //   in_adress_field[log2(IN_NUMSYMBOLS)]
+
+
+    reg [clogb2(RATIO)-1:0] in_bitforselect;
+    integer i, j;
+   
+    // ----------------------------------------
+    // Input Field Mapping
+    // ----------------------------------------
+    reg [ADDRESS_W-1:0] address_for_adaptation;
+    always @* begin
+        in_size_field            = in_data[IN_PKT_BURST_SIZE_H :IN_PKT_BURST_SIZE_L ];
+        in_data_field            = in_data[IN_PKT_DATA_H       :IN_PKT_DATA_L       ];
+        in_byteen_field          = in_data[IN_PKT_BYTEEN_H     :IN_PKT_BYTEEN_L     ];
+        address_from_packet      = in_data[IN_PKT_ADDR_H       :IN_PKT_ADDR_L       ];
+        in_byte_cnt_field        = in_data[IN_PKT_BYTE_CNT_H   :IN_PKT_BYTE_CNT_L   ];
+        in_cmpr_read             = in_data[IN_PKT_TRANS_COMPRESSED_READ];
+        in_write                 = in_data[IN_PKT_TRANS_WRITE];
+        in_lock_field            = in_data[IN_PKT_TRANS_EXCLUSIVE];
+        in_burst_type_field      = in_data[IN_PKT_BURST_TYPE_H :IN_PKT_BURST_TYPE_L ];
+        in_response_status_field = in_data[IN_PKT_RESPONSE_STATUS_H :IN_PKT_RESPONSE_STATUS_L];
+    end
+
+    // ----------------------------------------
+    // Process unaligned address for first address of the burst
+    // ----------------------------------------
+    generate
+    if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS && ENABLE_ADDRESS_ALIGNMENT) begin
+        reg [ADDRESS_W + (BWRAP_W-1) + BURST_SIZE_W + BURST_TYPE_W - 1 :0] address_for_alignment;
+        reg [ADDRESS_W + clogb2(IN_NUMSYMBOLS)-1:0] address_after_aligned;
+
+        assign address_for_alignment = {address_from_packet, in_size_field};
+        assign address_for_adaptation = address_after_aligned[ADDRESS_W-1:0];
+        
+        altera_merlin_address_alignment
+        #(
+           .ADDR_W            (ADDRESS_W),
+           .BURSTWRAP_W       (BWRAP_W),
+           .INCREMENT_ADDRESS (0),
+           .NUMSYMBOLS        (IN_NUMSYMBOLS),
+           .SIZE_W            (BURST_SIZE_W)
+        ) check_and_align_address_to_size
+        (
+           .clk       (clk),
+           .reset     (reset),
+           .in_data   (address_for_alignment),
+           .out_data  (address_after_aligned),
+           .in_valid  (),
+           .in_sop    (),
+           .in_eop    (),
+           .out_ready ()
+        );
+    end else begin
+        assign address_for_adaptation = address_from_packet;
+    end
+    endgenerate
+
+    generate begin
+        if (FIRST_EXISTS) begin
+            always @* begin
+                in_first_field = in_data[IN_FIRST_H:IN_FIRST_L];
+            end
+        end else begin
+            always @* begin
+                in_first_field = '0;
+            end
+        end
+        if (MID_EXISTS) begin
+            always @* begin
+                in_mid_field = in_data[IN_MID_H:IN_MID_L];
+            end
+        end else begin
+            always @* begin
+                in_mid_field = '0;
+            end
+        end
+        if (LAST_EXISTS) begin
+            always @* begin
+                in_last_field = in_data[IN_LAST_H:IN_LAST_L];
+            end
+        end
+    end
+    endgenerate
+
+   generate
+      
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      // Wide-to-Narrow
+      //
+      // For every input cycle, we drive out a bunch'o'output 
+      // cycles.  Nothing fancier.  Yes, it could be more
+      // optimal, but we'll leave that for another day.
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS)  begin
+
+         wire [31:0] cmd_burst_size = CONSTANT_BURST_SIZE ? IN_NUMSYMBOLS : bytes_in_transfer(in_size_field);
+         
+         // Below mess is just to avoid Quartus warnings about mis-sized assignments.
+         wire [31:0] int_out_numsymbols = OUT_NUMSYMBOLS;
+         wire [clogb2(OUT_NUMSYMBOLS):0] sized_out_numsymbols = int_out_numsymbols[clogb2(OUT_NUMSYMBOLS):0];
+
+         wire [31:0] int_out_size = (cmd_burst_size < OUT_NUMSYMBOLS) ? cmd_burst_size : OUT_NUMSYMBOLS;
+         wire [SIZE_W-1:0] sized_out_size = int_out_size[SIZE_W-1:0];
+
+         wire [31:0] int_ratio_minus_1 = (cmd_burst_size / OUT_NUMSYMBOLS) - 1;
+         wire [clogb2(RATIO)-1:0] sized_ratio_minus_1 = int_ratio_minus_1[clogb2(RATIO)-1:0];
+
+         wire [31:0] int_log2_out_numsymbols = clogb2(OUT_NUMSYMBOLS);
+         wire [BURST_SIZE_W-1:0] log2_out_numsymbols = int_log2_out_numsymbols[BURST_SIZE_W-1:0];
+
+         wire [31:0] int_byte_cnt_factor = (in_size_field < log2_out_numsymbols) ? log2_out_numsymbols : in_size_field;
+         wire [BURST_SIZE_W-1:0] sized_byte_cnt_factor = int_byte_cnt_factor[BURST_SIZE_W-1:0];
+
+         reg single_response_expected;
+         reg only_one_segment_asserted;
+         reg [RATIO-1:0] segments_with_be_asserted;
+         reg [clogb2(RATIO)-1:0] count;
+
+         assign single_response_expected = (RESPONSE_PATH && ((only_one_segment_asserted && in_startofpacket && in_endofpacket) || in_write));      
+
+         always @(posedge clk, posedge reset) begin
+            if (reset) begin
+               address_reg  <= '0;
+               byte_cnt_reg <= '0;
+               count        <= '0;
+               use_reg      <= '0;
+               endofpacket_reg <= '0;
+               data_reg     <= '0;
+               byteen_reg   <= '0;
+            end else begin
+               // If we're not working on a wide datum, 
+               // then wait until one arrives.
+               if (~use_reg) begin
+
+                  if (CONSTANT_BURST_SIZE) begin // when the system contains ONLY Avalon masters and slaves
+                      address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT];
+                      address_reg[WN_ADDR_SELECT - 1 : 0]        <= sized_out_numsymbols;
+                      data_reg     <= in_data_field[IN_DATA_W-1:OUT_NUMSYMBOLS*SYMBOL_W];
+                      byteen_reg   <= in_byteen_field >> OUT_NUMSYMBOLS;
+                      byte_cnt_reg <= in_byte_cnt_field - sized_out_numsymbols;
+                  end else begin
+                      address_reg <= in_address_field + sized_out_size;
+                      byte_cnt_reg <= (in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor) - sized_out_numsymbols;
+                  end
+                  
+                  endofpacket_reg <= in_endofpacket;
+
+                  if (in_valid && out_ready && !in_cmpr_read && (cmd_burst_size > OUT_NUMSYMBOLS) && !single_response_expected) begin
+                     // Data has arrived!
+                     count   <= sized_ratio_minus_1;
+                     use_reg <= 1'b1;
+                  end
+
+               end else begin // if (count == 0)
+                  // We have a wide datum in progress.  Just wait until 
+                  // the previous datum is taken, and then set 
+                  // up the next transfer.
+                  if (out_ready) begin
+                      if (CONSTANT_BURST_SIZE) begin
+                          address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT];
+                          address_reg[WN_ADDR_SELECT - 1 : 0]        <= address_reg[WN_ADDR_SELECT - 1 : 0] + sized_out_numsymbols;
+                          data_reg     <= data_reg    >> (OUT_NUMSYMBOLS * SYMBOL_W);
+                          byteen_reg   <= byteen_reg  >> (OUT_NUMSYMBOLS);
+                      end else begin
+                          address_reg <= address_reg + sized_out_size;
+                      end
+                     byte_cnt_reg <= byte_cnt_reg - sized_out_numsymbols;
+                     count <= count - 1'b1;
+                     if (count == 1'b1)
+                       // We're at the end of this word.
+                       use_reg <= '0;
+
+                  end // if (out_ready)
+               end // else: !if(count == 0)
+            end // if (posedge clk)
+         end // always @ (clk, reset)
+
+
+         always @* begin
+            // Calculate in_ready.
+            // If count is 0, then we don't have data underway, and we 
+            // definitely won't be ready for it the first time 'round.
+            // If count is '1', then we're finishing a set, and we're 
+            //   ready if the output is.
+            // If count > 1, then we're mid set, and certainly 
+            //   not ready.
+            in_ready = 0;
+            if ( (cmd_burst_size <= OUT_NUMSYMBOLS) || count == 1 || in_cmpr_read )
+               in_ready = out_ready;
+
+            out_valid                 = in_valid;
+            out_channel               = in_channel;
+            out_startofpacket         = in_startofpacket;
+            out_endofpacket           = 0;
+                                      
+            out_size_field            = (cmd_burst_size < OUT_NUMSYMBOLS) ? in_size_field : log2_out_numsymbols;
+            if (CONSTANT_BURST_SIZE) begin // For Avalon only
+                out_byteen_field   = in_byteen_field[OUT_NUMSYMBOLS-1:0];
+                out_data_field     = in_data_field[OUT_NUMSYMBOLS * SYMBOL_W-1:0];
+                out_byte_cnt_field = in_byte_cnt_field;
+            end else begin
+                out_byte_cnt_field = in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor;
+            end
+             
+            out_first_field           = in_first_field;
+            out_mid_field             = in_mid_field;
+            out_last_field            = in_last_field;
+            out_cmpr_read             = in_cmpr_read;
+            out_lock_field            = in_lock_field;
+            out_burst_type_field      = in_burst_type_field;
+            out_response_status_field = in_response_status_field;
+
+            // Case when command size <= OUT_NUMSYMBOLS: pass the cycle
+            // through, unmodified
+            if (cmd_burst_size <= OUT_NUMSYMBOLS) begin
+                out_endofpacket = in_endofpacket;
+                in_address_field = address_from_packet;
+            end // (cmd_burst_size <= OUT_NUMSYMBOLS)
+            else begin 
+                // Case when we need to bus size data (size > OUT_NUMSYMBOLS). 
+                out_lock_field     = 0;
+                // Change fixed burst type opcodes to the repeated wrap
+                // opcode.
+                if (in_burst_type_field == 2'b00) begin
+                    out_burst_type_field = 2'b11;
+                end
+                // On the first address of the burst, align and send this 
+                // address to the network
+                in_address_field = address_for_adaptation;
+            end // (cmd_burst_size > OUT_NUMSYMBOLS)
+
+            out_address_field         = in_address_field;
+            int_output_sel            = in_address_field >> log2_out_numsymbols ;
+            if (in_cmpr_read)
+                out_endofpacket = 1;
+            
+            if (use_reg) begin
+
+               out_startofpacket = 0;
+               // If it's the last cycle, or if there's no more data, 
+               // we can allow an endofpacket.
+               if (count == 1) 
+                  out_endofpacket = endofpacket_reg;
+               
+               out_byte_cnt_field = byte_cnt_reg;
+               out_address_field  = address_reg;
+               if (CONSTANT_BURST_SIZE) begin // Avalon system
+                   out_data_field     = data_reg[(OUT_NUMSYMBOLS * SYMBOL_W)-1:0];
+                   out_byteen_field   = byteen_reg[OUT_NUMSYMBOLS-1:0];
+                   byteen_array       = '{RATIO {0} };
+                   data_array         = '{RATIO {0} };
+               end
+               int_output_sel     = address_reg >> log2_out_numsymbols;
+            end
+ 
+            output_sel                = int_output_sel[WN_ADDR_LSBS-1:0];
+            if (!CONSTANT_BURST_SIZE) begin
+                out_byteen_field          = byteen_array[output_sel];
+                out_data_field            = data_array[output_sel];
+            end
+            
+            // Check each output-sized segment to see whether it 
+            // is enabled (byteenables)
+            segments_with_be_asserted = 0;
+            for (i = 0; i < RATIO; i=i+1) begin
+                segments_with_be_asserted[i] = |in_byteen_field[i*OUT_BYTEEN_W +: OUT_BYTEEN_W];
+            end
+
+            // Determine whether only one segment is asserted. This code detects a power of two,
+            // i.e. only 1 bit is asserted.
+            only_one_segment_asserted = (segments_with_be_asserted && !(segments_with_be_asserted & (segments_with_be_asserted - 1))); 
+
+            //-----------------------------------------
+            // Optimization for non-bursting wide-narrow response.
+            //
+            // Only one segment of the wide word will have asserted
+            // byteenables. Just pass that segment through and drop
+            // the rest. This should synthesize to an and-or mux.
+            //-----------------------------------------
+            if (OPTIMIZE_FOR_RSP | single_response_expected) begin
+                out_startofpacket  = in_startofpacket;
+                out_endofpacket    = in_endofpacket;
+                in_ready           = out_ready;
+                //-----------------------------------------
+                // Not correct, but nothing in the response path looks
+                // at these today (10.1). Must be corrected when we allow
+                // multiple width adapters on a path.
+                //-----------------------------------------
+                out_address_field  = in_address_field;
+                out_byte_cnt_field = in_byte_cnt_field;
+
+                out_data_field   = '0;
+                out_byteen_field = '0;
+                for (i = 0; i < RATIO; i=i+1) begin
+                    mask = '0;
+                    for (j = 0; j < OUT_NUMSYMBOLS; j=j+1) begin
+                        mask |= {SYMBOL_W{in_byteen_field[i*OUT_NUMSYMBOLS+j]}} << (j*SYMBOL_W);
+                    end
+    
+                    out_data_field |= mask & in_data_field[i*OUT_SEGMENT_W +: OUT_SEGMENT_W];
+                    out_byteen_field |= in_byteen_field[i*OUT_NUMSYMBOLS +: OUT_NUMSYMBOLS];
+                end
+            end
+            else begin  // to prevent latches
+                j = 0;
+                mask = '0;
+            end
+
+         end // always @ *
+         
+         //-------------------------------------------------------
+         // Configuration Error Checking
+         //-------------------------------------------------------
+         // synthesis translate_off
+         initial begin
+            if (RATIO * OUT_NUMSYMBOLS != IN_NUMSYMBOLS) begin
+               $display("%m : The ratio of input symbols to output symbols must be an integer.");
+               $stop();
+            end
+         end
+         // synthesis translate_on
+         if (!CONSTANT_BURST_SIZE) begin
+             integer ibyte;
+             always @* begin
+                 for(ibyte=0; ibyte<RATIO; ibyte=ibyte+1) begin: mux_mapping
+                     data_array[ibyte] = in_data_field[(ibyte*OUT_NUMSYMBOLS*SYMBOL_W)+:OUT_NUMSYMBOLS*SYMBOL_W];
+                     byteen_array[ibyte] = in_byteen_field[(ibyte*OUT_NUMSYMBOLS)+:OUT_NUMSYMBOLS];
+                 end
+             end
+         end
+      end // if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS)
+        
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      // Narrow-to-Wide
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS)  begin
+         wire                    p0_valid;
+         reg                     p0_startofpacket;
+         reg                     p0_endofpacket;
+         reg [IN_DATA_W-1:0]     p0_data_field; 
+         reg [IN_BYTEEN_W-1:0]   p0_byteen_field;
+         reg [ADDRESS_W-1:0]     p0_address_field;
+         reg [BWRAP_W-1:0]       p0_bwrap_field;
+         reg [BYTE_CNT_W-1:0]    p0_byte_cnt_field;
+         reg [clogb2(RATIO)-1:0] p0_bitforselect;
+         reg                     p0_cmpr_read;
+         reg [FIRST_W-1:0]       p0_first_field;
+         reg [MID_W-1:0]         p0_mid_field;
+         reg [LAST_W-1:0]        p0_last_field;
+         reg                     p0_use_reg;
+         reg [ST_CHANNEL_W-1:0]  p0_channel;
+         reg [BURST_SIZE_W-1:0]  p0_burst_size;
+		 reg [BURST_SIZE_W-1:0]  p0_ori_burst_size;
+         reg                     p0_out_lock_field;
+         reg [BURST_TYPE_W-1:0]  p0_burst_type_field;
+         
+         reg [RESPONSE_STATUS_W-1:0] p0_response_status_field;
+         reg                     p0_reg_startofpacket;
+         reg                     p0_reg_endofpacket;
+         reg [IN_DATA_W-1:0]     p0_reg_data_field; 
+         reg [IN_BYTEEN_W-1:0]   p0_reg_byteen_field;
+         reg [ADDRESS_W-1:0]     p0_reg_address_field;
+         reg [BWRAP_W-1:0]       p0_reg_bwrap_field;
+         reg [BYTE_CNT_W-1:0]    p0_reg_byte_cnt_field;
+         reg [clogb2(RATIO)-1:0] p0_reg_bitforselect;
+         reg                     p0_reg_cmpr_read;
+         reg [FIRST_W-1:0]       p0_reg_first_field;
+         reg [MID_W-1:0]         p0_reg_mid_field;
+         reg [LAST_W-1:0]        p0_reg_last_field;
+         reg [ST_CHANNEL_W-1:0]  p0_reg_channel;
+         reg [BURST_SIZE_W-1:0]  p0_reg_burst_size;
+		 reg [BURST_SIZE_W-1:0]  p0_reg_ori_burst_size;
+         reg [BURST_TYPE_W-1:0]  p0_reg_burst_type_field;
+         reg [RESPONSE_STATUS_W-1:0] p0_reg_response_status_field;
+         reg                     p0_reg_out_lock_field;
+         wire                    p1_valid;
+         reg                     p1_ready;
+         reg                     p1_startofpacket;
+         reg                     p1_endofpacket;
+         reg [IN_DATA_W-1:0]     p1_data_field; 
+         reg [IN_BYTEEN_W-1:0]   p1_byteen_field;
+         reg [ADDRESS_W-1:0]     p1_address_field;
+         reg [ADDRESS_W-1:0]     out_address_field_mask;
+         reg [BYTE_CNT_W-1:0]    p1_byte_cnt_field;
+         
+         reg [BURST_SIZE_W-1:0]  p1_burst_size;
+         reg [BYTE_CNT_W-1:0]    p1_byte_cnt_unpack_field;
+         wire                    response_data_packing;
+         reg [clogb2(RATIO)-1:0] p1_shift_correct_ouput_segments;
+         reg [clogb2(RATIO)-1:0] p1_push_data_to_output;
+         
+         reg                     p1_cmpr_read;
+         reg [RESPONSE_STATUS_W-1:0] p1_response_status_field;
+         reg                     unc_sink_valid;
+         wire                    unc_sink_ready;
+         wire                    unc_src_startofpacket;
+         wire                    unc_src_endofpacket;
+         wire                    unc_src_valid;
+         wire [ADDRESS_W-1:0]    unc_src_addr;
+         wire [BYTE_CNT_W-1:0]   unc_src_byte_cnt;
+
+         wire                    aligned_addr;
+         wire                    aligned_byte_cnt;
+         wire                    unaligned_read;
+
+         reg [BYTE_CNT_W-1:0]    count;
+         reg                     count_eq_zero;
+
+         wire [31:0] int_in_numsymbols = IN_NUMSYMBOLS;
+         wire [BYTE_CNT_W-1:0] byte_cnt_sized_in_num_symbols = 
+            int_in_numsymbols[BYTE_CNT_W-1:0];
+         reg [9:0]  cmd_burst_size;
+         wire [31:0] out_numsymbols_wire = LOG_OUT_NUMSYMBOLS;
+         wire [31:0]        int_encoded_burstsize = NW_BITFORSELECT_R; //NW_BITFORSELECT_R is the log2 of IN_NUMSYMBOLS
+         wire [BURST_SIZE_W-1:0] encoded_burstsize = int_encoded_burstsize[BURST_SIZE_W-1:0];      
+            
+        // Care about burstwrap on command path only
+        if (RESPONSE_PATH == 0) begin
+            assign in_burstwrap_field = in_data[IN_PKT_BURSTWRAP_H:IN_PKT_BURSTWRAP_L];
+        end
+        else begin
+            assign in_burstwrap_field = {BWRAP_W{1'b1}};
+        end   
+
+		// To use "read response merging" the Width adapter need to know the size of the command
+		// to check if downside happen. For AXI system, the fifo will store this number (non-packing: we use "combined width adapter")
+		// but in case system without AXI, the system use stand alone width adapter and it cannot read this value
+		// Make a condition incase we see stand alone WA, set this in_command_burst_size to input size
+        //wire [2:0] in_command_burst_size = out_numsymbols_wire[2:0];
+		//if (!((PACKING == 1) & (CONSTANT_BURST_SIZE == 1))) // stand alone WA
+		//	begin
+		//		assign in_command_burst_size = in_command_size_data;
+		//	end
+		reg [BURST_SIZE_W-1:0]      	in_ori_size_field;
+		always @* begin
+			in_ori_size_field        = in_data[IN_PKT_ORI_BURST_SIZE_H :IN_PKT_ORI_BURST_SIZE_L ];
+		end
+		
+        reg [9:0]   size_ratio;
+         // --------------------------------------------
+         // Stage 0: buffer the input cycle if read burst 
+         // uncompression is going to happen.
+         //
+         // This avoids the possibility of a master receiving a premature
+         // response while its read burst is still being waitrequested.
+         // --------------------------------------------
+         always @(posedge clk, posedge reset) begin
+            if (reset) begin
+               p0_use_reg            <= 1'b0;
+               p0_reg_startofpacket  <= 1'b0;
+               p0_reg_endofpacket    <= 1'b0;
+               p0_reg_data_field     <= '0;
+               p0_reg_bwrap_field    <= '0;
+               p0_reg_byteen_field   <= '0;
+               p0_reg_address_field  <= '0;
+               p0_reg_byte_cnt_field <= '0;
+               p0_reg_cmpr_read      <= 1'b0;
+               p0_reg_first_field    <= '0;
+               p0_reg_mid_field      <= '0;
+               p0_reg_last_field     <= '0;
+               p0_reg_channel        <= '0;
+               p0_reg_burst_size     <= '0;
+			   p0_reg_ori_burst_size     <= '0;
+               p0_reg_out_lock_field <= '0;
+               p0_reg_burst_type_field      <= '0;
+               p0_reg_response_status_field <= '0;
+            end else begin
+               if (unaligned_read & in_valid)
+                  p0_use_reg <= 1'b1;
+               if (unc_src_endofpacket & p1_ready)
+                  p0_use_reg <= 1'b0;
+
+               if (unaligned_read) begin
+                  p0_reg_startofpacket  <= p0_startofpacket;
+                  p0_reg_endofpacket    <= p0_endofpacket;   
+                  p0_reg_data_field     <= p0_data_field;    
+                  p0_reg_bwrap_field    <= p0_bwrap_field;
+                  p0_reg_byteen_field   <= p0_byteen_field;  
+                  p0_reg_address_field  <= p0_address_field; 
+                  p0_reg_byte_cnt_field <= p0_byte_cnt_field;
+                  p0_reg_cmpr_read      <= p0_cmpr_read;     
+                  p0_reg_first_field    <= p0_first_field;   
+                  p0_reg_mid_field      <= p0_mid_field;     
+                  p0_reg_last_field     <= p0_last_field;    
+                  p0_reg_channel        <= p0_channel;
+                  p0_reg_burst_size     <= p0_burst_size;
+				  p0_reg_ori_burst_size <= p0_ori_burst_size;
+                  p0_reg_out_lock_field <= p0_out_lock_field;
+                  p0_reg_burst_type_field       <= p0_burst_type_field;
+                  p0_reg_response_status_field  <= p0_response_status_field;
+               end
+            end
+         end
+
+         always @* begin
+            in_ready = p1_ready;
+   
+            // accept on the first cycle 
+            if (unaligned_read & in_valid & ~p0_use_reg)
+                in_ready = 1;
+
+            if (p0_use_reg)
+                in_ready = 0;
+         end
+
+         always @* begin
+            p0_startofpacket  = in_startofpacket;
+            p0_endofpacket    = in_endofpacket;
+            p0_data_field     = in_data_field;  
+            p0_bwrap_field    = in_burstwrap_field;
+            p0_byteen_field   = in_byteen_field;
+            //p0_address_field  = in_address_field;  
+            p0_address_field  = address_for_adaptation;  // read address from oacket
+            
+            p0_byte_cnt_field = in_byte_cnt_field;
+            p0_cmpr_read      = in_cmpr_read;     
+            p0_first_field    = in_first_field;   
+            p0_mid_field      = in_mid_field;     
+            p0_last_field     = in_last_field;
+            p0_channel        = in_channel;
+            p0_burst_size     = in_size_field;
+			p0_ori_burst_size = in_ori_size_field;
+            p0_out_lock_field = in_lock_field;
+            p0_burst_type_field         = in_burst_type_field;
+            p0_response_status_field    = in_response_status_field;
+            if (p0_use_reg) begin
+               p0_startofpacket  = p0_reg_startofpacket;
+               p0_endofpacket    = p0_reg_endofpacket;
+               p0_data_field     = p0_reg_data_field;  
+               p0_bwrap_field    = p0_reg_bwrap_field;
+               p0_byteen_field   = p0_reg_byteen_field;
+               p0_address_field  = p0_reg_address_field;  
+               p0_byte_cnt_field = p0_reg_byte_cnt_field;
+               p0_cmpr_read      = p0_reg_cmpr_read;     
+               p0_first_field    = p0_reg_first_field;   
+               p0_mid_field      = p0_reg_mid_field;     
+               p0_last_field     = p0_reg_last_field;
+               p0_channel        = p0_reg_channel;
+               p0_burst_size     = p0_reg_burst_size;
+			   p0_ori_burst_size = p0_reg_ori_burst_size;
+               p0_out_lock_field = p0_reg_out_lock_field;
+               p0_burst_type_field      = p0_reg_burst_type_field;
+               p0_response_status_field = p0_reg_response_status_field;
+            end
+         end
+
+         assign p0_valid = in_valid | p0_use_reg;
+
+         // --------------------------------------------
+         // Stage 1: uncompress the input packet if necessary
+         // --------------------------------------------
+         assign p1_valid = (unaligned_read) ? unc_src_valid : p0_valid;
+         assign aligned_addr     = (p0_address_field[ALIGNED_BITS_L:0] == 0);
+         assign aligned_byte_cnt = (p0_byte_cnt_field[ALIGNED_BITS_L:0] == 0);
+         if ((RESPONSE_PATH == 0) && (PACKING == 1)) begin // if this is avalon then checking on aligned,
+            assign unaligned_read   = p0_cmpr_read & (~aligned_addr || ~aligned_byte_cnt);
+         end else begin
+            assign unaligned_read   = '0;
+         end
+         
+         always @* begin
+            p1_data_field     = p0_data_field;
+            p1_byteen_field   = p0_byteen_field;
+            p1_startofpacket  = p0_startofpacket;
+            p1_endofpacket    = p0_endofpacket;
+            p1_address_field  = p0_address_field;
+            p1_byte_cnt_field = p0_byte_cnt_field;
+            p1_cmpr_read      = p0_cmpr_read;
+            p1_response_status_field    = p0_response_status_field;
+            p1_burst_size     = p0_burst_size;
+            unc_sink_valid    = 0;
+
+            if (unaligned_read) begin
+               unc_sink_valid    = p0_valid;
+
+               p1_startofpacket  = unc_src_startofpacket;
+               p1_endofpacket    = unc_src_endofpacket;
+               p1_address_field  = unc_src_addr;
+               p1_byte_cnt_field = unc_src_byte_cnt;
+               p1_cmpr_read      = 0;
+            end
+         end
+
+         altera_merlin_burst_uncompressor
+         #(
+            .ADDR_W      (ADDRESS_W),
+            .BURSTWRAP_W (BWRAP_W),
+            .BYTE_CNT_W  (BYTE_CNT_W),
+            .PKT_SYMBOLS (IN_NUMSYMBOLS),
+            .BURST_SIZE_W(BURST_SIZE_W)
+         ) uncompressor (
+            .clk                  (clk),
+            .reset                (reset),
+
+            .sink_startofpacket   (p0_startofpacket),
+            .sink_endofpacket     (p0_endofpacket),
+            .sink_valid           (unc_sink_valid),
+            .sink_ready           (unc_sink_ready),
+            .sink_addr            (p0_address_field),
+            .sink_burstwrap       (p0_bwrap_field),
+            .sink_byte_cnt        (p0_byte_cnt_field),
+            .sink_is_compressed   (1'b1),   // should always be compressed
+            .sink_burstsize       (encoded_burstsize),
+
+            .source_startofpacket (unc_src_startofpacket),
+            .source_endofpacket   (unc_src_endofpacket),
+            .source_valid         (unc_src_valid),
+            .source_ready         (p1_ready),
+            .source_addr          (unc_src_addr),
+            .source_burstwrap     (),
+            .source_byte_cnt      (unc_src_byte_cnt),
+            .source_is_compressed (),
+            .source_burstsize     ()
+         );
+
+         // --------------------------------------------
+         // Stage 2: perform narrow to wide adaptation on the beats
+         // --------------------------------------------
+         
+         always @(posedge clk, posedge reset) begin
+            if (reset) begin
+               data_reg          <= '0;
+               byteen_reg        <= '0;
+               startofpacket_reg <= '0;
+               count             <= '0;
+               count_eq_zero     <= '1;
+               response_status_reg <= '0;
+            end else begin
+               
+               if (p1_valid && (out_ready || ~out_valid)) begin
+                  // Lay input data & input byte enables into 
+                  // the temp registers
+                  data_reg      <= data_reg   | (p1_data_field   << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W));
+                  byteen_reg    <= byteen_reg | (p1_byteen_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS));
+                  response_status_reg   <= out_response_status_field;
+                  // Capture the stuff that's to be held constant
+                  if (count_eq_zero) begin
+                     startofpacket_reg <= p1_startofpacket;
+                     if (~p1_endofpacket) begin
+                        count <= p1_byte_cnt_field - byte_cnt_sized_in_num_symbols;
+                        count_eq_zero <=
+                          ~|(p1_byte_cnt_field - byte_cnt_sized_in_num_symbols);
+                     end 
+                  end else begin
+                     count <= count - byte_cnt_sized_in_num_symbols;
+                     count_eq_zero <= ~|(count - byte_cnt_sized_in_num_symbols);
+                  end
+
+                  //if (p1_endofpacket || (p1_shift_correct_ouput_segments == '1)) begin
+                  if (p1_endofpacket || (p1_push_data_to_output == '1)) begin
+                     data_reg     <= '0;
+                     byteen_reg   <= '0;
+                     response_status_reg <= '0;
+                  end
+                  
+                  if (out_valid && out_ready) begin
+                     startofpacket_reg <= '0;
+                  end
+                  
+               end // if (p1_valid && (out_ready || ~out_valid))
+            end // if (posedge clk)
+         end // always @ (clk, reset)
+
+         always @* begin
+            // Handle narrow-size transaction from the master: 
+            // The width of in_bitforselect is 
+            //  log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) =
+            //  log2(RATIO)
+            // The msb of in_bitforselect is driven by: in_adress_field[log2(OUT_NUMSYMBOLS) - 1]
+            // The lsb of in_adress_field is driven by: in_adress_field[log2(IN_NUMSYMBOLS)]
+
+            // The function: mask_to_select_segments_for_size: is used to build a mask that changed at run-time
+            // when narrow-size transaction, It recaculates the width of in_bitforselect base on size ratio
+
+            // EX: Full-size transaction (2 bytes)N-W: in_bitforselect  = in_address[1:0]
+            //     Narrow-size transaction(1 byte)N-W: in_bitforselect  = {1, in_address[0]}
+            
+            p1_shift_correct_ouput_segments = p1_address_field[NW_BITFORSELECT_L:NW_BITFORSELECT_R];
+            
+            // size ratio betwen command size and response size
+            //cmd_burst_size = bytes_in_transfer(in_command_burst_size);
+			cmd_burst_size = bytes_in_transfer(p0_ori_burst_size);
+			
+            size_ratio = cmd_burst_size >> in_size_field; 
+            
+            if (RESPONSE_PATH == 0) begin 
+            // if the WA is on command path, Avalon interconnect default
+            // bitselectfor data packing and push out data are same, compile time 
+                p1_push_data_to_output = p1_shift_correct_ouput_segments;
+            end else begin 
+            // the WA is on reponse path and default: PACKING = 1
+            // on response path, need based on size, run-time, to determinite output segment
+                p1_push_data_to_output = mask_to_select_correct_segments_for_size(p1_shift_correct_ouput_segments, size_ratio, clogb2(RATIO));
+                out_address_field_mask = choose_packed_address_base_on_size(size_ratio, clogb2(RATIO));
+            end
+
+            // We push data to the output whenever the input is 
+            // an endofpacket, or the input drives the most-significant
+            // segment of the wider output word.
+            out_valid = 0;
+            if (PACKING == 1) begin
+                if (p1_endofpacket || (p1_push_data_to_output == '1)) begin
+                    out_valid = p1_valid;
+                end
+            end else begin
+                out_valid = p1_valid;
+            end
+
+            out_startofpacket = p1_startofpacket || startofpacket_reg;
+            out_endofpacket   = p1_endofpacket;
+
+            // Compressed read with byte_cnt > input interface width: 
+            // this is a read burst spanning more than the originating
+            // interface of data, so all byteenables must be asserted.
+            if (p1_cmpr_read && (p1_byte_cnt_field > IN_NUMSYMBOLS)) begin
+                out_byteen_field = '1;
+            end else begin
+                if (PACKING == 1) begin  // byteenable only affect on command path
+                    out_byteen_field = byteen_reg |
+                        (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS));
+                end else begin // non-packing: shift input byteenable to correct position
+                    out_byteen_field = (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS));
+                end
+            end
+            
+            // caculate bytecnt "unpack" according to OUTNUMSYMBOLS
+            p1_byte_cnt_unpack_field = p1_byte_cnt_field << clogb2(RATIO);
+            out_address_field = p1_address_field;
+
+            if (RESPONSE_PATH == 0) begin
+                if (PACKING == 1) begin // if the WA is on command path, Avalon interconnect default
+                    out_data_field      = data_reg   | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W));
+                    out_byte_cnt_field  = quantized_byte_cnt_field;
+                    out_address_field[NW_BITFORSELECT_L:0] = 0;
+                    out_size_field      = out_numsymbols_wire[BURST_SIZE_W-1:0]; // for Avalon the size is converted to slave side
+                 end else begin
+                    out_data_field      = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W));
+                    out_byte_cnt_field  = p1_byte_cnt_unpack_field;
+                    out_size_field      = p1_burst_size;
+                 end
+            end else begin // the WA is on reponse path and default: PACKING = 1
+                //if (in_size_field < in_command_burst_size) begin // downsize happen on command path, the response need packing
+				if (in_size_field < in_ori_size_field) begin // downsize happen on command path, the response need packing
+                    out_data_field    = data_reg  
+                        | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W));
+                    out_address_field = p1_address_field & out_address_field_mask;
+                    out_size_field      = p1_burst_size;
+                    out_byte_cnt_field  = p1_byte_cnt_field;
+                end else begin // narrow transaction on command path, reponse packet will not packed
+                    out_data_field      = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W));
+                    out_byte_cnt_field  = p1_byte_cnt_field;
+                    out_size_field      = p1_burst_size;
+                end
+            end
+			
+			//if (in_size_field < in_command_burst_size) begin // downsize happen on command path, the response need packing
+			if (in_size_field < in_ori_size_field) begin // downsize happen on command path, the response need packing
+                // Response merging: rules: DECERR(11) > SLVERR (10) > OKAY (00)
+                // EXOKAY will not happen on merging
+                out_response_status_field = '0;
+                if (response_status_reg >= p1_response_status_field) begin
+                    out_response_status_field = response_status_reg;
+                end else begin
+                    out_response_status_field = p1_response_status_field;
+                end
+            end else begin // narrow transaction on command path, reponse packet will not packed
+                out_response_status_field   = p1_response_status_field;
+            end
+				
+            out_cmpr_read      = p1_cmpr_read;
+
+            // nothing touches these fields, so assign them
+            // directly from the input fields
+            out_first_field      = p0_first_field;
+            out_mid_field        = p0_mid_field;
+            out_last_field       = p0_last_field;
+            out_lock_field       = p0_out_lock_field;
+            out_channel          = p0_channel;
+            out_burst_type_field = p0_burst_type_field;
+         end // always @ *
+
+        //-------------------------------------------------------
+        // output byte_cnt, rounded up to alignment with the output-side 
+        // address map footprint implied by the input-side access.
+        //
+        // See "option 3" in Appendix C of
+        // merlin_interconnect_architecture_fd_91.doc.
+        //-------------------------------------------------------
+        reg [NW_BITFORSELECT_L:0] low_addr_bits;
+
+        always @* begin
+           low_addr_bits = p1_address_field[NW_BITFORSELECT_L:0];
+           
+           quantized_byte_cnt_field = low_addr_bits + 
+               p1_byte_cnt_field + 
+               {clogb2(OUT_NUMSYMBOLS){1'b1}};
+           quantized_byte_cnt_field[NW_BITFORSELECT_L:0] = '0;
+        end
+
+         //-------------------------------------------------------
+         // Backpressure
+         //-------------------------------------------------------
+         always @ * begin
+            p1_ready = out_ready || ~out_valid;
+         end
+   
+      end // if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS)
+
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      // Same Width.  Seems kind of silly, but let's be complete.
+      //-------------------------------------------------------
+      //-------------------------------------------------------
+      if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS)  begin
+   
+         always @* begin
+            in_ready                    = out_ready;
+            out_valid                   = in_valid;
+            out_channel                 = in_channel;
+            out_startofpacket           = in_startofpacket;
+            out_endofpacket             = in_endofpacket;
+            out_size_field              = in_size_field;
+            out_data_field              = in_data_field;
+            out_byteen_field            = in_byteen_field;
+            out_address_field           = in_address_field;
+            out_byte_cnt_field          = in_byte_cnt_field;
+            out_response_status_field   = in_response_status_field;
+            out_lock_field              = in_lock_field;
+            out_burst_type_field        = in_burst_type_field;            
+            out_cmpr_read               = in_cmpr_read;
+            out_first_field             = in_first_field;
+            out_mid_field               = in_mid_field;
+            out_last_field              = in_last_field;
+         end // always @ *
+   
+      end // if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS)
+
+   endgenerate
+
+   // ---------------------------------------
+   // Output Field Mapping
+   //
+   // Conditionally assign the pseudo-fields. Assign address and size 
+   // last, because they partly override the pseudo-fields.
+   // ---------------------------------------
+   always @* begin
+      if (FIRST_EXISTS)
+          out_data[OUT_FIRST_H:OUT_FIRST_L] = out_first_field;
+      if (MID_EXISTS)
+          out_data[OUT_MID_H:OUT_MID_L]     = out_mid_field;
+      if (LAST_EXISTS)
+          out_data[OUT_LAST_H:OUT_LAST_L]   = out_last_field;
+
+      out_data[OUT_PKT_BURST_SIZE_H      : OUT_PKT_BURST_SIZE_L     ] = out_size_field;
+      out_data[OUT_PKT_DATA_H            : OUT_PKT_DATA_L           ] = out_data_field;
+      out_data[OUT_PKT_BYTEEN_H          : OUT_PKT_BYTEEN_L         ] = out_byteen_field;
+      out_data[OUT_PKT_ADDR_H            : OUT_PKT_ADDR_L           ] = out_address_field;
+      out_data[OUT_PKT_BYTE_CNT_H        : OUT_PKT_BYTE_CNT_L       ] = out_byte_cnt_field;
+      out_data[OUT_PKT_TRANS_COMPRESSED_READ                        ] = out_cmpr_read;
+      out_data[OUT_PKT_TRANS_EXCLUSIVE                              ] = out_lock_field;
+      out_data[OUT_PKT_BURST_TYPE_H      : OUT_PKT_BURST_TYPE_L     ] = out_burst_type_field;
+      out_data[OUT_PKT_RESPONSE_STATUS_H : OUT_PKT_RESPONSE_STATUS_L] = out_response_status_field;
+   end // always @ *
+
+endmodule // width_adapter
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v
new file mode 100644
index 0000000..5dfbfce
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v
@@ -0,0 +1,249 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher #(
+    parameter ENHANCED_FEATURES = 0,
+    parameter ENABLE_READ_BURST = 0,
+    parameter MAX_READ_BURST_COUNT = 4,
+    parameter MAX_READ_BURST_COUNT_WIDTH = 3,
+    parameter DATA_WIDTH = 32,
+    parameter DATA_BYTEENABLE_WIDTH = 4,
+    parameter DESCRIPTOR_WIDTH = 128,
+    parameter ADDRESS_WIDTH = 32,
+    parameter RESPONSE_FIFO_DEPTH   = 256,
+    parameter RESPONSE_FIFO_DEPTH_LOG2 = 7
+
+) (
+    input                                           clk,
+    input                                           reset,
+    input [DATA_WIDTH-1:0]                          mm_read_readdata,
+    input                                           mm_read_waitrequest,
+    input                                           mm_read_readdatavalid,
+    input                                           st_src_descr_ready,
+    input                                           mm_write_waitrequest,
+    input                                           mm_write_writeresponsevalid,
+    input [1:0]                                     mm_write_response,  // don't care the response status
+    input                                           st_snk_valid,
+    input [255:0]                                   st_snk_data,
+    input [2:0]                                     mm_csr_address,
+    input                                           mm_csr_write,
+    input                                           mm_csr_read,
+    input [31:0]                                    mm_csr_writedata,
+    
+    output [ADDRESS_WIDTH-1:0]                      mm_read_address,
+    output                                          mm_read_read,
+    output [MAX_READ_BURST_COUNT_WIDTH-1:0]         mm_read_burstcount,
+    output                                          st_src_descr_valid,
+    output [DESCRIPTOR_WIDTH-1:0]                   st_src_descr_data,
+    output [ADDRESS_WIDTH-1:0]                      mm_write_address,
+    output                                          mm_write_write,
+    output [DATA_WIDTH-1:0]                         mm_write_writedata,
+    output [DATA_BYTEENABLE_WIDTH-1:0]              mm_write_byteenable,
+    output                                          st_snk_ready,
+    output                                          csr_irq,
+    output [31:0]                                   mm_csr_readdata
+
+
+
+
+);
+
+
+
+
+localparam RESPONSE_FIFO_WIDTH  = (ENHANCED_FEATURES == 1) ? 96 : 64;
+
+
+wire                            run;
+wire                            reset_prefetcher;
+wire [31:0]                     nxt_desc_ptr_low;
+wire [31:0]                     nxt_desc_ptr_high;
+wire                            desc_poll_en;
+wire [15:0]                     desc_poll_freq;
+wire                            put_resp_fifo;
+wire [RESPONSE_FIFO_WIDTH-1:0]  resp_fifo_wdata;
+wire                            clear_run;
+wire                            update_nxt_desc_ptr;
+wire [63:0]                     updated_ptr_desc;
+wire [RESPONSE_FIFO_WIDTH-1:0]  resp_fifo_rdata;
+wire                            get_resp_fifo;
+wire                            park_mode;
+wire                            write_back_done;
+wire                            transfer_complete_irq_mask;
+wire [7:0]                      error_irq_mask;
+wire                            early_termination_irq_mask;
+wire [7:0]                      error;
+wire                            early_termination;
+wire                            clear_irq;
+wire                            global_interrupt_enable_mask;
+wire                            reset_complete_from_read;
+wire                            reset_complete_from_write_back;
+wire                            reset_complete;
+wire                            resp_fifo_full;
+
+
+
+altera_msgdma_prefetcher_read #(
+    .ENHANCED_FEATURES              (ENHANCED_FEATURES),
+    .ENABLE_READ_BURST              (ENABLE_READ_BURST),
+    .MAX_READ_BURST_COUNT           (MAX_READ_BURST_COUNT),
+    .MAX_READ_BURST_COUNT_WIDTH     (MAX_READ_BURST_COUNT_WIDTH),
+    .DATA_WIDTH                     (DATA_WIDTH),
+    .ADDRESS_WIDTH                  (ADDRESS_WIDTH),
+    .DESCRIPTOR_WIDTH               (DESCRIPTOR_WIDTH),
+    .RESPONSE_FIFO_WIDTH            (RESPONSE_FIFO_WIDTH)
+) u_prefetcher_read (
+    // inputs
+    .clk                                (clk),
+    .reset                              (reset),
+    .mm_read_readdata                   (mm_read_readdata),
+    .mm_read_waitrequest                (mm_read_waitrequest),
+    .mm_read_readdatavalid              (mm_read_readdatavalid),
+    .st_src_descr_ready                 (st_src_descr_ready),
+    .run                                (run),
+    .reset_prefetcher                   (reset_prefetcher),
+    .nxt_desc_ptr_low                   (nxt_desc_ptr_low),
+    .nxt_desc_ptr_high                  (nxt_desc_ptr_high),
+    .desc_poll_en                       (desc_poll_en),
+    .desc_poll_freq                     (desc_poll_freq),
+    .resp_fifo_full                     (resp_fifo_full),
+    // outputs
+    .mm_read_address                    (mm_read_address),
+    .mm_read_read                       (mm_read_read),
+    .mm_read_burstcount                 (mm_read_burstcount),
+    .st_src_descr_valid                 (st_src_descr_valid),
+    .st_src_descr_data                  (st_src_descr_data),
+    .put_resp_fifo                      (put_resp_fifo),
+    .resp_fifo_wdata                    (resp_fifo_wdata),
+    .clear_run                          (clear_run),
+    .update_nxt_desc_ptr                (update_nxt_desc_ptr),
+    .updated_ptr_desc                   (updated_ptr_desc),
+    .reset_complete                     (reset_complete_from_read)
+
+);
+
+
+
+altera_msgdma_prefetcher_write_back #(
+    .ENHANCED_FEATURES          (ENHANCED_FEATURES),
+    .DATA_WIDTH                 (DATA_WIDTH),
+    .DATA_BYTEENABLE_WIDTH      (DATA_BYTEENABLE_WIDTH),
+    .ADDRESS_WIDTH              (ADDRESS_WIDTH),
+    .RESPONSE_FIFO_WIDTH        (RESPONSE_FIFO_WIDTH)
+) u_prefetcher_write_back (
+    // inputs
+    .clk                            (clk),
+    .reset                          (reset),
+    .mm_write_waitrequest           (mm_write_waitrequest),
+    .mm_write_response              (mm_write_response),
+    .mm_write_writeresponsevalid    (mm_write_writeresponsevalid),
+    .st_snk_valid                   (st_snk_valid),
+    .st_snk_data                    (st_snk_data),
+    .resp_fifo_rdata                (resp_fifo_rdata),
+    .park_mode                      (park_mode),
+    .run                            (run),
+    .reset_prefetcher               (reset_prefetcher),
+    // outputs
+    .mm_write_address               (mm_write_address),
+    .mm_write_write                 (mm_write_write),
+    .mm_write_writedata             (mm_write_writedata),
+    .mm_write_byteenable            (mm_write_byteenable),
+    .st_snk_ready                   (st_snk_ready),
+    .get_resp_fifo                  (get_resp_fifo),
+    .write_back_done                (write_back_done),
+    .transfer_complete_irq_mask     (transfer_complete_irq_mask),
+    .error_irq_mask                 (error_irq_mask),
+    .early_termination_irq_mask     (early_termination_irq_mask),
+    .error                          (error),
+    .early_termination              (early_termination),
+    .reset_complete                 (reset_complete_from_write_back)
+
+);
+
+
+
+altera_msgdma_prefetcher_fifo #(
+    .RESPONSE_FIFO_WIDTH        (RESPONSE_FIFO_WIDTH),
+    .RESPONSE_FIFO_DEPTH        (RESPONSE_FIFO_DEPTH),
+    .RESPONSE_FIFO_DEPTH_LOG2   (RESPONSE_FIFO_DEPTH_LOG2),
+    .LATENCY                    (2)
+) u_prefetcher_fifo (
+    // inputs
+    .clk        (clk),
+    .areset     (reset),
+    .sreset     (reset_complete),
+    .wr_data    (resp_fifo_wdata),
+    .wrreq      (put_resp_fifo),
+    .rdreq      (get_resp_fifo),
+    // outputs
+    .full       (resp_fifo_full),
+    .rd_data    (resp_fifo_rdata)
+
+);
+
+
+
+altera_msgdma_prefetcher_csr u_prefetcher_csr (
+    // inputs
+    .clk                            (clk),
+    .reset                          (reset),
+    .mm_csr_address                 (mm_csr_address),
+    .mm_csr_write                   (mm_csr_write),
+    .mm_csr_read                    (mm_csr_read),
+    .mm_csr_writedata               (mm_csr_writedata),
+    .clear_run                      (clear_run),
+    .reset_complete                 (reset_complete),
+    .irq                            (csr_irq),
+    .update_nxt_desc_ptr            (update_nxt_desc_ptr),
+    .updated_ptr_desc               (updated_ptr_desc),
+    // outputs
+    .mm_csr_readdata                (mm_csr_readdata),
+    .run                            (run),
+    .reset_prefetcher               (reset_prefetcher),
+    .clear_irq                      (clear_irq),
+    .nxt_desc_ptr_low               (nxt_desc_ptr_low),
+    .nxt_desc_ptr_high              (nxt_desc_ptr_high),
+    .desc_poll_en                   (desc_poll_en),
+    .desc_poll_freq                 (desc_poll_freq),
+    .global_interrupt_enable_mask   (global_interrupt_enable_mask),
+    .park_mode                      (park_mode)
+
+);
+
+
+
+altera_msgdma_prefetcher_interrupt u_prefetcher_interrupt (
+    // inputs
+    .clk                                (clk),
+    .reset                              (reset),
+    .write_back_done                    (write_back_done), 
+    .transfer_complete_irq_mask         (transfer_complete_irq_mask),
+    .error_irq_mask                     (error_irq_mask),
+    .early_termination_irq_mask         (early_termination_irq_mask),
+    .error                              (error),
+    .early_termination                  (early_termination),
+    .clear_irq                          (clear_irq),
+    .global_interrupt_enable_mask       (global_interrupt_enable_mask),
+    // outputs
+    .irq                                (csr_irq)
+
+);
+
+
+assign reset_complete = reset_complete_from_read & reset_complete_from_write_back;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v
new file mode 100644
index 0000000..55fc75a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v
@@ -0,0 +1,226 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher_csr (
+    input               clk,
+    input               reset,
+
+    input [2:0]         mm_csr_address,
+    input               mm_csr_write,
+    input               mm_csr_read,
+    input [31:0]        mm_csr_writedata,
+
+    output reg [31:0]   mm_csr_readdata,
+
+    input               clear_run,
+    input               reset_complete,
+    input               irq,
+    input               update_nxt_desc_ptr,
+    input [63:0]        updated_ptr_desc,
+
+    output reg          run,
+    output reg          reset_prefetcher,
+    output              clear_irq,
+    output reg [31:0]   nxt_desc_ptr_low,
+    output reg [31:0]   nxt_desc_ptr_high,
+    output reg          desc_poll_en,
+    output reg [15:0]   desc_poll_freq,
+    output reg          global_interrupt_enable_mask,
+    output reg          park_mode
+
+);
+
+
+wire        control_access;
+wire        nxt_desc_ptr_low_access;
+wire        nxt_desc_ptr_high_access;
+wire        desc_poll_freq_access;
+wire        status_access;
+wire        reset_prefetcher_nxt;
+wire        run_nxt;
+
+wire [31:0] mm_csr_readdata_nxt;
+wire [31:0] control_int;
+wire [31:0] nxt_desc_ptr_low_int;
+wire [31:0] nxt_desc_ptr_high_int;
+wire [31:0] desc_poll_freq_int;
+wire [31:0] status_int;
+
+wire        control_read;
+wire        nxt_desc_ptr_low_read;
+wire        nxt_desc_ptr_high_read;
+wire        desc_poll_freq_read;
+wire        status_read;
+
+
+//--------------------------------------------------------------------------------------------//
+// address decode
+//--------------------------------------------------------------------------------------------//
+assign control_access               = (mm_csr_address == 3'h0);
+assign nxt_desc_ptr_low_access      = (mm_csr_address == 3'h1);
+assign nxt_desc_ptr_high_access     = (mm_csr_address == 3'h2);
+assign desc_poll_freq_access        = (mm_csr_address == 3'h3);
+assign status_access                = (mm_csr_address == 3'h4);
+
+//--------------------------------------------------------------------------------------------//
+// read decode
+//--------------------------------------------------------------------------------------------//
+assign control_read             = control_access & mm_csr_read;
+assign nxt_desc_ptr_low_read    = nxt_desc_ptr_low_access & mm_csr_read; 
+assign nxt_desc_ptr_high_read   = nxt_desc_ptr_high_access & mm_csr_read; 
+assign desc_poll_freq_read      = desc_poll_freq_access & mm_csr_read;
+assign status_read              = status_access & mm_csr_read;
+
+
+
+
+//--------------------------------------------------------------------------------------------//
+// park mode bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        park_mode   <= 1'b0;
+    else if (mm_csr_write & control_access)
+        park_mode   <= mm_csr_writedata[4];
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// global interrupt enable mask bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        global_interrupt_enable_mask    <= 1'b0;
+    else if (mm_csr_write & control_access)
+        global_interrupt_enable_mask   <= mm_csr_writedata[3];
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// reset prefetcher bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        reset_prefetcher    <= 1'b0;
+    else
+        reset_prefetcher    <= reset_prefetcher_nxt;
+end
+
+assign reset_prefetcher_nxt = reset_prefetcher ? ~reset_complete : (mm_csr_write & control_access & mm_csr_writedata[2]); 
+
+
+
+//--------------------------------------------------------------------------------------------//
+// descriptor poll en bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        desc_poll_en    <= 1'b0;
+    else if (mm_csr_write & control_access)
+        desc_poll_en   <= mm_csr_writedata[1];
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// run bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        run     <= 1'b0;
+    else
+        run     <= run_nxt;
+end
+
+assign run_nxt = run ? ~clear_run : (mm_csr_write & control_access & mm_csr_writedata[0]); 
+
+
+
+//--------------------------------------------------------------------------------------------//
+// next descriptor pointer low
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        nxt_desc_ptr_low    <= 32'h0;
+    else if (mm_csr_write & nxt_desc_ptr_low_access)
+        nxt_desc_ptr_low    <= mm_csr_writedata;
+    else if (update_nxt_desc_ptr)
+        nxt_desc_ptr_low    <= updated_ptr_desc[31:0];
+end
+
+
+//--------------------------------------------------------------------------------------------//
+// next descriptor pointer high
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        nxt_desc_ptr_high    <= 32'h0;
+    else if (mm_csr_write & nxt_desc_ptr_high_access)
+        nxt_desc_ptr_high    <= mm_csr_writedata;
+    else if (update_nxt_desc_ptr)
+        nxt_desc_ptr_high    <= updated_ptr_desc[63:32];
+end
+
+
+
+
+//--------------------------------------------------------------------------------------------//
+// descriptor poll freq
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        desc_poll_freq  <= 16'h0;
+    else if (mm_csr_write & desc_poll_freq_access)
+        desc_poll_freq  <= mm_csr_writedata[15:0];
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// irq status clear event 
+//--------------------------------------------------------------------------------------------//
+assign clear_irq = mm_csr_write & status_access & mm_csr_writedata[0];
+
+//--------------------------------------------------------------------------------------------//
+// readdata register
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        mm_csr_readdata <= 32'h0;
+    else
+        mm_csr_readdata <= mm_csr_readdata_nxt;
+end
+
+
+
+assign control_int              = {27'h0, park_mode, global_interrupt_enable_mask, reset_prefetcher, desc_poll_en, run};
+assign nxt_desc_ptr_low_int     = nxt_desc_ptr_low; 
+assign nxt_desc_ptr_high_int    = nxt_desc_ptr_high; 
+assign desc_poll_freq_int       = {16'h0, desc_poll_freq};
+assign status_int               = {31'h0, irq};
+
+assign mm_csr_readdata_nxt      =   (control_int            & {32{control_read}}            )   |
+                                    (nxt_desc_ptr_low_int   & {32{nxt_desc_ptr_low_read}}   )   |
+                                    (nxt_desc_ptr_high_int  & {32{nxt_desc_ptr_high_read}}  )   |
+                                    (desc_poll_freq_int     & {32{desc_poll_freq_read}}     )   |
+                                    (status_int             & {32{status_read}}             );
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v
new file mode 100644
index 0000000..1baf01a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v
@@ -0,0 +1,142 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher_fifo #(
+    parameter RESPONSE_FIFO_WIDTH   = 64,
+    parameter RESPONSE_FIFO_DEPTH   = 256,
+    parameter RESPONSE_FIFO_DEPTH_LOG2 = 7,
+    parameter LATENCY = 2
+) (
+    input                               clk,
+    input                               areset,
+    input                               sreset,
+    input [RESPONSE_FIFO_WIDTH-1:0]     wr_data,
+    input                               wrreq,
+    input                               rdreq,
+    
+    output                              full,
+    output [RESPONSE_FIFO_WIDTH-1:0]    rd_data
+);
+
+
+reg [RESPONSE_FIFO_DEPTH_LOG2-1:0]  write_address;
+reg [RESPONSE_FIFO_DEPTH_LOG2-1:0]  read_address;
+reg [RESPONSE_FIFO_DEPTH_LOG2:0] internal_used;
+
+wire internal_full;
+//wire internal_empty;
+wire [(RESPONSE_FIFO_WIDTH/8)-1:0]  write_byteenables;
+
+
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      write_address <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        write_address <= 0;
+      end
+      else if (wrreq == 1)
+      begin
+        write_address <= write_address + 1'b1;
+      end
+    end
+  end
+
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      read_address <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        read_address <= 0;
+      end
+      else if (rdreq == 1)
+      begin
+        read_address <= read_address + 1'b1;
+      end
+    end
+  end
+
+  assign write_byteenables = {(RESPONSE_FIFO_WIDTH/8){1'b1}};
+
+  // TODO:  Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
+  altsyncram the_dp_ram (
+    .clock0 (clk),
+    .wren_a (wrreq),
+    .byteena_a (write_byteenables),
+    .data_a (wr_data),
+    .address_a (write_address),
+    .q_b (rd_data),
+    .address_b (read_address)
+  );
+  defparam the_dp_ram.operation_mode = "DUAL_PORT";  // simple dual port (one read, one write port)
+  defparam the_dp_ram.lpm_type = "altsyncram";
+  defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
+  defparam the_dp_ram.power_up_uninitialized = "TRUE";
+  defparam the_dp_ram.byte_size = 8;
+  defparam the_dp_ram.width_a = RESPONSE_FIFO_WIDTH;
+  defparam the_dp_ram.width_b = RESPONSE_FIFO_WIDTH;
+  defparam the_dp_ram.widthad_a = RESPONSE_FIFO_DEPTH_LOG2;
+  defparam the_dp_ram.widthad_b = RESPONSE_FIFO_DEPTH_LOG2;
+  defparam the_dp_ram.width_byteena_a = (RESPONSE_FIFO_WIDTH/8);
+  defparam the_dp_ram.numwords_a = RESPONSE_FIFO_DEPTH;
+  defparam the_dp_ram.numwords_b = RESPONSE_FIFO_DEPTH;
+  defparam the_dp_ram.address_reg_b = "CLOCK0";
+  defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
+
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      internal_used <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        internal_used <= 0;
+      end
+      else
+      begin
+        case ({wrreq, rdreq})
+          2'b01: internal_used <= internal_used - 1'b1;
+          2'b10: internal_used <= internal_used + 1'b1;
+          default: internal_used <= internal_used;
+        endcase
+      end
+    end
+  end
+
+
+  //assign internal_empty = (read_address == write_address) & (internal_used == 0);
+  assign internal_full = (write_address == read_address) & (internal_used != 0);
+
+  //assign used = internal_used;    // this signal reflects the number of words in the FIFO
+  //assign empty = internal_empty;  // combinational so it'll glitch a little bit
+  assign full = internal_full;    // dito
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v
new file mode 100644
index 0000000..2cda00b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v
@@ -0,0 +1,55 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher_interrupt (
+    input           clk,
+    input           reset,
+    input           write_back_done,
+    input           transfer_complete_irq_mask,
+    input [7:0]     error_irq_mask,
+    input           early_termination_irq_mask,
+    input [7:0]     error,
+    input           early_termination,
+    input           clear_irq,
+    input           global_interrupt_enable_mask,
+
+    output reg      irq
+
+);
+
+wire set_irq;
+
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        irq <= 0;
+    else begin
+        case ({clear_irq, set_irq})
+            2'b00: irq <= irq;
+            2'b01: irq <= 1'b1;
+            2'b10: irq <= 1'b0;
+            2'b11: irq <= 1'b1;
+        endcase
+    end
+end
+
+assign set_irq  = (global_interrupt_enable_mask == 1) & (write_back_done == 1) &       // transfer ended and interrupts are enabled
+                   ((transfer_complete_irq_mask == 1) |                        // transfer ended and the transfer complete IRQ is enabled
+                    ((error & error_irq_mask) != 0) |                          // transfer ended with an error and this IRQ is enabled
+                    ((early_termination & early_termination_irq_mask) == 1));  // transfer ended early due to early termination and this IRQ is enabled
+
+                    
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v
new file mode 100644
index 0000000..b012691
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v
@@ -0,0 +1,515 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher_read #(
+    parameter ENHANCED_FEATURES = 0,
+    parameter ENABLE_READ_BURST = 0,
+    parameter MAX_READ_BURST_COUNT = 4,
+    parameter MAX_READ_BURST_COUNT_WIDTH = 3,
+    parameter DATA_WIDTH = 32,
+    parameter ADDRESS_WIDTH = 32,
+    parameter DESCRIPTOR_WIDTH = 128,
+    parameter RESPONSE_FIFO_WIDTH = 64
+
+) (
+    input                                           clk,
+    input                                           reset,
+
+    input [DATA_WIDTH-1:0]                          mm_read_readdata,
+    input                                           mm_read_waitrequest,
+    input                                           mm_read_readdatavalid,
+    output reg [ADDRESS_WIDTH-1:0]                  mm_read_address,
+    output reg                                      mm_read_read,
+    output [MAX_READ_BURST_COUNT_WIDTH-1:0]         mm_read_burstcount,
+
+    input                                           st_src_descr_ready,
+    output reg                                      st_src_descr_valid,
+    output [DESCRIPTOR_WIDTH-1:0]                   st_src_descr_data,
+
+    input                                           resp_fifo_full,
+    output                                          put_resp_fifo,
+    output [RESPONSE_FIFO_WIDTH-1:0]                resp_fifo_wdata,
+
+    input                                           run,
+    input                                           reset_prefetcher,
+    input [31:0]                                    nxt_desc_ptr_low,
+    input [31:0]                                    nxt_desc_ptr_high,
+    input                                           desc_poll_en,
+    input [15:0]                                    desc_poll_freq,
+    output                                          clear_run,
+    output reg                                      update_nxt_desc_ptr,
+    output [63:0]                                   updated_ptr_desc,
+    output reg                                      reset_complete
+
+);
+
+
+
+// y = log2(x)
+function integer log2;
+    input integer x;
+    begin
+        x = x-1;
+        for(log2=0; x>0; log2=log2+1)
+            x = x>>1;
+    end
+endfunction
+
+
+localparam PREFETCHER_DESCRIPTOR_WIDTH  = DESCRIPTOR_WIDTH * 2;
+localparam NUM_RD_REQ                   = (ENABLE_READ_BURST == 1) ? (PREFETCHER_DESCRIPTOR_WIDTH / (DATA_WIDTH * MAX_READ_BURST_COUNT)) : (PREFETCHER_DESCRIPTOR_WIDTH / DATA_WIDTH);
+localparam NUM_TOTAL_BURST_BEAT         = PREFETCHER_DESCRIPTOR_WIDTH / DATA_WIDTH;
+localparam RD_REQ_CNT_WIDTH             = (NUM_RD_REQ == 1) ? 1 : log2(NUM_RD_REQ);
+localparam BURST_BEAT_CNT_WIDTH         = (NUM_TOTAL_BURST_BEAT == 1) ? 1 : log2(NUM_TOTAL_BURST_BEAT);
+localparam RD_ADDR_INCR                 = (ENABLE_READ_BURST == 1) ? ((DATA_WIDTH * MAX_READ_BURST_COUNT) / 8) : (DATA_WIDTH / 8);
+localparam DESCRIPTOR_DEPTH             = PREFETCHER_DESCRIPTOR_WIDTH / DATA_WIDTH;
+
+
+
+reg [3:0]                       ctrl_state;
+reg [3:0]                       ctrl_state_nxt;
+reg                             mm_read_read_nxt;
+reg [RD_REQ_CNT_WIDTH-1:0]      rd_req_cnt;
+reg [RD_REQ_CNT_WIDTH-1:0]      rd_req_cnt_nxt;
+reg [BURST_BEAT_CNT_WIDTH-1:0]  rd_burst_cnt;
+reg [BURST_BEAT_CNT_WIDTH-1:0]  rd_burst_cnt_nxt;
+reg [ADDRESS_WIDTH-1:0]         ptr_desc;
+reg [DATA_WIDTH-1:0]            descriptor_internal [0:DESCRIPTOR_DEPTH-1];
+reg [15:0]                      poll_cnt;
+reg [15:0]                      poll_cnt_nxt;
+reg                             load_from_ptr_reg;
+
+
+wire                                rd_wait_done;
+wire                                rd_pend_done;
+wire                                poll_wait_done;
+wire                                owned_by_hardware;
+wire                                set_mm_read_read;
+wire                                clr_mm_read_read;
+wire [63:0]                         ptr_reg;
+wire                                load_ptr_reg;
+wire [ADDRESS_WIDTH-1:0]            ptr_desc_nxt;
+wire [ADDRESS_WIDTH-1:0]            nxt_desc_ptr_to_fifo_unmask;
+wire [RESPONSE_FIFO_WIDTH-33:0]     nxt_desc_ptr_to_fifo;
+wire                                poll_load_state;
+wire                                wr_req_state;
+wire                                rd_req_state;
+wire                                clr_run_state;
+wire                                idle_state;
+wire                                wr_done_state;
+wire                                reset_complete_nxt;
+
+localparam [3:0]    IDLE        = 4'b0000; 
+localparam [3:0]    RD_REQ      = 4'b0001; 
+localparam [3:0]    RD_WAIT     = 4'b0010; 
+localparam [3:0]    RD_PEND     = 4'b0011; 
+localparam [3:0]    RD_DONE     = 4'b0100; 
+localparam [3:0]    WR_REQ      = 4'b0101; 
+localparam [3:0]    WR_WAIT     = 4'b0110; 
+localparam [3:0]    WR_DONE     = 4'b0111; 
+localparam [3:0]    POLL_LOAD   = 4'b1000; 
+localparam [3:0]    POLL_WAIT   = 4'b1001; 
+localparam [3:0]    CLR_RUN     = 4'b1010; 
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Main FSM
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        ctrl_state  <= IDLE;
+    else
+        ctrl_state  <= ctrl_state_nxt;
+end
+
+
+
+always @* begin
+    case (ctrl_state)
+        IDLE: begin
+            if (run & ~reset_prefetcher)
+                ctrl_state_nxt  = RD_REQ;
+            else
+                ctrl_state_nxt  = IDLE;
+        end
+
+        RD_REQ: begin
+            ctrl_state_nxt  = RD_WAIT;
+        end
+        
+        RD_WAIT: begin
+            if (rd_wait_done)
+                ctrl_state_nxt  = RD_PEND;
+            else
+                ctrl_state_nxt  = RD_WAIT;
+        end
+
+        RD_PEND: begin
+            if (rd_pend_done)
+                ctrl_state_nxt  = RD_DONE;
+            else
+                ctrl_state_nxt  = RD_PEND;
+        end
+
+        RD_DONE: begin
+            if (reset_prefetcher | (~owned_by_hardware & ~desc_poll_en)) // The completion of read request will be the point where reset_prefetcher takes effects
+                ctrl_state_nxt  = CLR_RUN;
+            else if (desc_poll_en & ~owned_by_hardware)
+                ctrl_state_nxt  = POLL_LOAD;
+            else if (owned_by_hardware & ~resp_fifo_full)
+                ctrl_state_nxt  = WR_REQ;
+            else
+                ctrl_state_nxt  = RD_DONE;
+        end
+
+        WR_REQ: begin
+            ctrl_state_nxt  = WR_WAIT;
+        end
+
+        WR_WAIT: begin
+            if (st_src_descr_ready)
+                ctrl_state_nxt  = WR_DONE;
+            else
+                ctrl_state_nxt  = WR_WAIT;
+        end
+        
+        WR_DONE: begin
+            ctrl_state_nxt  = RD_REQ;
+        end
+
+        POLL_LOAD: begin
+            ctrl_state_nxt  = POLL_WAIT;
+        end
+
+        POLL_WAIT: begin
+            if (poll_wait_done)
+                ctrl_state_nxt  = RD_REQ;
+            else
+                ctrl_state_nxt  = POLL_WAIT;
+        end
+
+        CLR_RUN: begin
+            ctrl_state_nxt  = IDLE;
+        end
+
+        default: begin
+            ctrl_state_nxt  = IDLE;
+        end
+
+    endcase
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// RD REQ Counter
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        rd_req_cnt  <= 0;
+    else
+        rd_req_cnt  <= rd_req_cnt_nxt;
+end
+
+always @* begin
+    if (set_mm_read_read)
+        rd_req_cnt_nxt = (NUM_RD_REQ - 1);
+    else if ((rd_req_cnt > 0) & mm_read_read & ~mm_read_waitrequest)
+        rd_req_cnt_nxt = rd_req_cnt - 1;
+    else
+        rd_req_cnt_nxt = rd_req_cnt;
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// RD BURST BEAT Counter
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        rd_burst_cnt    <= 0;
+    else
+        rd_burst_cnt    <= rd_burst_cnt_nxt;
+end
+
+always @* begin
+    if (set_mm_read_read)
+        rd_burst_cnt_nxt = (NUM_TOTAL_BURST_BEAT - 1);
+    else if ((rd_burst_cnt > 0) & mm_read_readdatavalid)
+        rd_burst_cnt_nxt = rd_burst_cnt - 1;
+    else
+        rd_burst_cnt_nxt = rd_burst_cnt;
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Descriptor Poll Counter
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        poll_cnt    <= 0;
+    else
+        poll_cnt    <= poll_cnt_nxt;
+end
+
+always @* begin
+    if (poll_load_state)
+        poll_cnt_nxt = desc_poll_freq;
+    else if (poll_cnt > 0)
+        poll_cnt_nxt = poll_cnt - 1;
+    else
+        poll_cnt_nxt = poll_cnt;
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Avalon MM Read descriptor registers
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        mm_read_read    <= 1'b0;
+    else
+        mm_read_read    <= mm_read_read_nxt;
+end
+
+always @* begin
+    case ({set_mm_read_read, clr_mm_read_read})
+        2'b00: mm_read_read_nxt     = mm_read_read;
+        2'b01: mm_read_read_nxt     = 1'b0;
+        2'b10: mm_read_read_nxt     = 1'b1;
+        2'b11: mm_read_read_nxt     = mm_read_read;
+        default: mm_read_read_nxt   = 1'b0;
+    endcase
+end
+
+
+
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        mm_read_address <= 0;
+    else if (set_mm_read_read)
+        mm_read_address <= (load_from_ptr_reg ? ptr_reg[ADDRESS_WIDTH-1:0] : ptr_desc[ADDRESS_WIDTH-1:0]);
+    else if (mm_read_read & ~mm_read_waitrequest)
+        mm_read_address <= mm_read_address + RD_ADDR_INCR;
+    else
+        mm_read_address <= mm_read_address;
+end
+
+assign mm_read_burstcount = MAX_READ_BURST_COUNT;   // If read burst mode is disabled, this signal is not exported out at mSGDMA top level 
+
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Descriptor internal register
+//--------------------------------------------------------------------------------------------//
+genvar i;
+generate
+    for (i=0; i<DESCRIPTOR_DEPTH; i=i+1) begin : descriptor_array_loop
+        always @(posedge clk or posedge reset) begin
+            if (reset)
+                descriptor_internal[DESCRIPTOR_DEPTH-1-i] <= {DATA_WIDTH{1'b0}};
+            else if (mm_read_readdatavalid & (rd_burst_cnt == i))
+                descriptor_internal[DESCRIPTOR_DEPTH-1-i] <= mm_read_readdata;
+        end
+    end
+endgenerate
+
+
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        ptr_desc    <= 0;
+    else if (wr_done_state)
+        ptr_desc    <= ptr_desc_nxt;
+    else
+        ptr_desc    <= ptr_desc;
+end
+
+
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        update_nxt_desc_ptr     <= 1'b0;
+    else if (wr_done_state & desc_poll_en)
+        update_nxt_desc_ptr     <= 1'b1;
+    else
+        update_nxt_desc_ptr     <= 1'b0;
+end
+
+generate
+if (ADDRESS_WIDTH == 64) begin
+    assign updated_ptr_desc = ptr_desc;
+end
+else begin
+    assign updated_ptr_desc = {{(64 - ADDRESS_WIDTH){1'b0}}, ptr_desc};
+end
+endgenerate
+
+
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        load_from_ptr_reg   <= 1'b0;
+    else if (load_ptr_reg)
+        load_from_ptr_reg   <= 1'b1;
+    else if (wr_done_state)
+        load_from_ptr_reg   <= 1'b0;
+end
+
+assign nxt_desc_ptr_to_fifo_unmask = load_from_ptr_reg ? ptr_reg[ADDRESS_WIDTH-1:0] : ptr_desc; 
+
+generate
+if (ENHANCED_FEATURES) begin
+    if (ADDRESS_WIDTH == 64) begin
+        assign nxt_desc_ptr_to_fifo = nxt_desc_ptr_to_fifo_unmask;
+    end
+    else begin
+        assign nxt_desc_ptr_to_fifo = {{(64 - ADDRESS_WIDTH){1'b0}}, nxt_desc_ptr_to_fifo_unmask};
+    end
+end
+else begin
+    if (ADDRESS_WIDTH == 32) begin
+        assign nxt_desc_ptr_to_fifo = nxt_desc_ptr_to_fifo_unmask;
+    end
+    else begin
+        assign nxt_desc_ptr_to_fifo = {{(32 - ADDRESS_WIDTH){1'b0}}, nxt_desc_ptr_to_fifo_unmask};
+    end
+end
+endgenerate
+
+
+//--------------------------------------------------------------------------------------------//
+// Avalon ST Write Dispatcher registers
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        st_src_descr_valid  <= 1'b0;
+    else if (wr_req_state)
+        st_src_descr_valid  <= 1'b1;
+    else if (st_src_descr_valid & st_src_descr_ready)
+        st_src_descr_valid  <= 1'b0;
+    else
+        st_src_descr_valid  <= st_src_descr_valid;
+end
+
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Reset Prefetcher Complete bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        reset_complete  <= 1'b0;
+    else
+        reset_complete  <= reset_complete_nxt;
+end
+
+assign reset_complete_nxt = reset_complete ? reset_prefetcher : (reset_prefetcher & (idle_state | clr_run_state));
+
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Combinatorial assignment
+//--------------------------------------------------------------------------------------------//
+assign rd_req_state         = (ctrl_state == RD_REQ);
+assign poll_load_state      = (ctrl_state == POLL_LOAD);
+assign wr_req_state         = (ctrl_state == WR_REQ);
+assign clr_run_state        = (ctrl_state == CLR_RUN);
+assign idle_state           = (ctrl_state == IDLE);
+assign wr_done_state        = (ctrl_state == WR_DONE); 
+
+assign set_mm_read_read     = rd_req_state;
+assign clr_mm_read_read     = (ctrl_state == RD_WAIT) & (ctrl_state_nxt != RD_WAIT);
+assign load_ptr_reg         = (ctrl_state == IDLE) & (ctrl_state_nxt == RD_REQ);
+
+assign ptr_reg              = {nxt_desc_ptr_high, nxt_desc_ptr_low};
+
+assign rd_wait_done         = (rd_req_cnt == 0) & mm_read_read & ~mm_read_waitrequest;      
+assign rd_pend_done         = (rd_burst_cnt == 0) & mm_read_readdatavalid;
+assign poll_wait_done       = (poll_cnt == 0);
+assign clear_run            = clr_run_state | (idle_state & run & reset_prefetcher);
+assign put_resp_fifo        = wr_done_state;
+
+generate
+if (ENHANCED_FEATURES) begin
+
+    if (DATA_WIDTH == 32) begin
+        assign ptr_desc_nxt         = {descriptor_internal[11][31:0], descriptor_internal[3][31:0]};
+        assign owned_by_hardware    = descriptor_internal[15][30];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[15][29:0], descriptor_internal[10][31:0], descriptor_internal[9][31:0], descriptor_internal[8][31:0], descriptor_internal[7][31:0], descriptor_internal[2][31:0], descriptor_internal[1][31:0], descriptor_internal[0][31:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[15][31:0], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 64) begin
+        assign ptr_desc_nxt         = {descriptor_internal[5][63:32], descriptor_internal[1][63:32]};
+        assign owned_by_hardware    = descriptor_internal[7][62];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[7][61:32], descriptor_internal[5][31:0], descriptor_internal[4][63:0], descriptor_internal[3][63:32], descriptor_internal[1][31:0], descriptor_internal[0][63:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[7][63:32], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 128) begin
+        assign ptr_desc_nxt         = {descriptor_internal[2][127:96], descriptor_internal[0][127:96]};
+        assign owned_by_hardware    = descriptor_internal[3][126];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[3][125:96], descriptor_internal[2][95:0], descriptor_internal[1][127:96], descriptor_internal[0][95:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[3][127:96], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 256) begin
+        assign ptr_desc_nxt         = {descriptor_internal[1][127:96], descriptor_internal[0][127:96]};
+        assign owned_by_hardware    = descriptor_internal[1][254];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[1][253:224], descriptor_internal[1][95:0], descriptor_internal[0][255:224], descriptor_internal[0][95:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[1][255:224], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 512) begin
+        assign ptr_desc_nxt         = {descriptor_internal[0][383:352], descriptor_internal[0][127:96]};
+        assign owned_by_hardware    = descriptor_internal[0][510];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[0][509:480], descriptor_internal[0][351:224], descriptor_internal[0][95:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[0][511:480], nxt_desc_ptr_to_fifo};
+    end
+end
+else begin
+    
+    if (DATA_WIDTH == 32) begin
+        assign ptr_desc_nxt         = descriptor_internal[3][31:0];
+        assign owned_by_hardware    = descriptor_internal[7][30];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[7][29:0], descriptor_internal[2][31:0], descriptor_internal[1][31:0], descriptor_internal[0][31:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[7][31:0], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 64) begin
+        assign ptr_desc_nxt         = descriptor_internal[1][63:32];
+        assign owned_by_hardware    = descriptor_internal[3][62];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[3][61:32], descriptor_internal[1][31:0], descriptor_internal[0][63:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[3][63:32], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 128) begin
+        assign ptr_desc_nxt         = descriptor_internal[0][127:96];
+        assign owned_by_hardware    = descriptor_internal[1][126];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[1][125:96], descriptor_internal[0][95:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[1][127:96], nxt_desc_ptr_to_fifo};
+    end
+    else if (DATA_WIDTH == 256) begin
+        assign ptr_desc_nxt         = descriptor_internal[0][127:96];
+        assign owned_by_hardware    = descriptor_internal[0][254];
+        assign st_src_descr_data    = {2'b10, descriptor_internal[0][253:224], descriptor_internal[0][95:0]};
+        assign resp_fifo_wdata      = {descriptor_internal[0][255:224], nxt_desc_ptr_to_fifo};
+    end
+end
+endgenerate
+
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v
new file mode 100644
index 0000000..a65d7e9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v
@@ -0,0 +1,416 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+module altera_msgdma_prefetcher_write_back #(
+    parameter ENHANCED_FEATURES = 0,
+    parameter DATA_WIDTH = 32,
+    parameter DATA_BYTEENABLE_WIDTH = 32,
+    parameter ADDRESS_WIDTH = 32,
+    parameter RESPONSE_FIFO_WIDTH = 64
+) (
+    input                                   clk,
+    input                                   reset,
+
+    input                                   mm_write_waitrequest,
+    input                                   mm_write_writeresponsevalid,
+    input [1:0]                             mm_write_response,  // don't care the response status
+    output reg [ADDRESS_WIDTH-1:0]          mm_write_address,
+    output reg                              mm_write_write,
+    output reg [DATA_WIDTH-1:0]             mm_write_writedata,
+    output reg [DATA_BYTEENABLE_WIDTH-1:0]  mm_write_byteenable,
+
+    input                                   st_snk_valid,
+    input [255:0]                           st_snk_data,
+    output reg                              st_snk_ready,
+
+    input [RESPONSE_FIFO_WIDTH-1:0]         resp_fifo_rdata,
+    output                                  get_resp_fifo,
+
+    output                                  write_back_done,
+    output                                  transfer_complete_irq_mask,
+    output [7:0]                            error_irq_mask,
+    output                                  early_termination_irq_mask,
+    output [7:0]                            error,
+    output                                  early_termination,
+
+    input                                   reset_prefetcher,
+    input                                   park_mode,
+    input                                   run,
+    output reg                              reset_complete
+
+);
+
+localparam [2:0]    IDLE        = 3'b000; 
+localparam [2:0]    START       = 3'b001; 
+localparam [2:0]    WR_REQ      = 3'b010; 
+localparam [2:0]    WR_WAIT     = 3'b011; 
+localparam [2:0]    WR_PEND     = 3'b100; 
+localparam [2:0]    WR_DONE     = 3'b101; 
+localparam [2:0]    ST_READY    = 3'b110; 
+
+reg [2:0]                           desc_wrback_state;
+reg [2:0]                           desc_wrback_state_nxt;
+reg [1:0]                           wr_req_cnt;
+reg [1:0]                           wr_req_cnt_nxt;
+reg [1:0]                           wr_resp_cnt;
+reg [1:0]                           wr_resp_cnt_nxt;
+reg                                 owned_by_hardware_wrback;
+
+wire                                mm_write_write_nxt;
+wire                                idle_state;
+wire                                wr_req_state;
+wire                                wr_done_state;
+wire                                st_ready_state;
+wire                                start_state;
+wire                                wr_req_done;
+wire                                wr_resp_done;
+wire [ADDRESS_WIDTH-1:0]            nxt_desc_pointer_base;
+wire [ADDRESS_WIDTH-1:0]            mm_write_address_int [0:2];
+wire [DATA_BYTEENABLE_WIDTH-1:0]    mm_write_byteenable_int [0:2];
+wire [DATA_WIDTH-1:0]               mm_write_writedata_int [0:2];
+wire                                reset_complete_nxt;
+
+
+//--------------------------------------------------------------------------------------------//
+// Main FSM
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        desc_wrback_state  <= IDLE;
+    else
+        desc_wrback_state  <= desc_wrback_state_nxt;
+end
+
+always @* begin
+    case (desc_wrback_state)
+        IDLE: begin
+            if (run & ~reset_prefetcher)
+                desc_wrback_state_nxt   = START;
+            else
+                desc_wrback_state_nxt   = IDLE;
+        end
+
+        START: begin
+            if (reset_prefetcher) // to handle case where reset prefetcher occurs during descriptor poll events and no more response from dispatcher
+                desc_wrback_state_nxt   = IDLE;
+            else if (st_snk_valid)
+                desc_wrback_state_nxt   = WR_REQ;
+            else
+                desc_wrback_state_nxt   = START;
+        end
+
+        WR_REQ: begin
+            desc_wrback_state_nxt       = WR_WAIT;
+        end
+        
+        WR_WAIT: begin
+            if (wr_req_done)
+                desc_wrback_state_nxt   = WR_PEND;
+            else
+                desc_wrback_state_nxt   = WR_WAIT;
+        end
+        
+        WR_PEND: begin
+            if (wr_resp_done)
+                desc_wrback_state_nxt   = WR_DONE;
+            else
+                desc_wrback_state_nxt   = WR_PEND;
+        end
+        
+        WR_DONE: begin
+            desc_wrback_state_nxt       = ST_READY;
+        end
+        
+        ST_READY: begin
+            if (reset_prefetcher)
+                desc_wrback_state_nxt       = IDLE;
+            else
+                desc_wrback_state_nxt       = START;
+        end
+
+        default: begin
+            desc_wrback_state_nxt  = IDLE;
+        end
+
+    endcase
+end 
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Avalon MM Write Back registers
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        mm_write_write   <= 1'b0;
+    else
+        mm_write_write   <= mm_write_write_nxt;
+end
+
+assign mm_write_write_nxt = mm_write_write ? ~wr_req_done : wr_req_state;
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        mm_write_address        <= 0;
+        mm_write_byteenable     <= 0;
+        mm_write_writedata      <= 0;
+    end
+    else begin
+        mm_write_address        <= mm_write_address_int[wr_req_cnt_nxt];
+        mm_write_byteenable     <= mm_write_byteenable_int[wr_req_cnt_nxt];
+        mm_write_writedata      <= mm_write_writedata_int[wr_req_cnt_nxt];
+    end
+end
+
+
+
+//--------------------------------------------------------------------------------------------//
+// Write req counter
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        wr_req_cnt   <= 0;
+    else
+        wr_req_cnt   <= wr_req_cnt_nxt;
+end
+
+always @* begin
+    if (wr_req_state)
+        wr_req_cnt_nxt = 2'h2;
+    else if ((wr_req_cnt > 0) & mm_write_write & ~mm_write_waitrequest)
+        wr_req_cnt_nxt = wr_req_cnt - 1;
+    else
+        wr_req_cnt_nxt = wr_req_cnt;
+end
+
+
+//--------------------------------------------------------------------------------------------//
+// Write resp counter
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        wr_resp_cnt   <= 0;
+    else
+        wr_resp_cnt   <= wr_resp_cnt_nxt;
+end
+
+always @* begin
+    if (wr_req_state)
+        wr_resp_cnt_nxt = 2'h2;
+    else if ((wr_resp_cnt > 0) & mm_write_writeresponsevalid)
+        wr_resp_cnt_nxt = wr_resp_cnt - 1;
+    else
+        wr_resp_cnt_nxt = wr_resp_cnt;
+end
+
+
+//--------------------------------------------------------------------------------------------//
+// Snapshot park_mode csr value each time before write back transaction begins case:321667
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        owned_by_hardware_wrback    <= 0;
+    else if (wr_req_state)
+        owned_by_hardware_wrback    <= park_mode;
+end
+
+
+//--------------------------------------------------------------------------------------------//
+// Avalon ST registers
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        st_snk_ready    <= 1'b0;
+    else if (wr_done_state)
+        st_snk_ready    <= 1'b1;
+    else
+        st_snk_ready    <= 1'b0;
+end
+
+
+//--------------------------------------------------------------------------------------------//
+// Reset Prefetcher Complete bit
+//--------------------------------------------------------------------------------------------//
+always @(posedge clk or posedge reset) begin
+    if (reset)
+        reset_complete  <= 1'b0;
+    else
+        reset_complete  <= reset_complete_nxt;
+end
+
+assign reset_complete_nxt = reset_complete ? reset_prefetcher : (reset_prefetcher & (idle_state | st_ready_state | start_state));
+
+
+//--------------------------------------------------------------------------------------------//
+// Combinatorial assignment
+//--------------------------------------------------------------------------------------------//
+assign idle_state                   = (desc_wrback_state == IDLE);
+assign wr_req_state                 = (desc_wrback_state == WR_REQ);
+assign wr_done_state                = (desc_wrback_state == WR_DONE);
+assign st_ready_state               = (desc_wrback_state == ST_READY);
+assign start_state                  = (desc_wrback_state == START);
+assign wr_req_done                  = ~mm_write_waitrequest & (wr_req_cnt == 0);
+assign wr_resp_done                 = mm_write_writeresponsevalid & (wr_resp_cnt == 0);
+assign get_resp_fifo                = wr_done_state; // Ensure the next resp data is available during worst case scenario (back to back write back).Resp fifo has read latency of 2. 
+assign write_back_done              = st_snk_ready;
+assign error                        = st_snk_data[39:32];
+assign early_termination            = st_snk_data[40];
+assign transfer_complete_irq_mask   = st_snk_data[41];
+assign error_irq_mask               = st_snk_data[49:42];
+assign early_termination_irq_mask   = st_snk_data[50];
+
+generate
+if (ENHANCED_FEATURES) begin
+
+    assign nxt_desc_pointer_base    = resp_fifo_rdata[63:0];
+
+    if (DATA_WIDTH == 32) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 20; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 60; 
+        
+        assign mm_write_byteenable_int[2]   = 4'hf;
+        assign mm_write_byteenable_int[1]   = 4'h3;
+        assign mm_write_byteenable_int[0]   = 4'hf;
+        
+        assign mm_write_writedata_int[2]   = {st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {23'h0, st_snk_data[40:32]};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[95], owned_by_hardware_wrback, resp_fifo_rdata[93:64]};
+
+    end
+    else if (DATA_WIDTH == 64) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 56; 
+        
+        assign mm_write_byteenable_int[2]   = 8'h0f;
+        assign mm_write_byteenable_int[1]   = 8'h30;
+        assign mm_write_byteenable_int[0]   = 8'hf0;
+        
+        assign mm_write_writedata_int[2]   = {32'h0, st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {23'h0, st_snk_data[40:32], 32'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[95], owned_by_hardware_wrback, resp_fifo_rdata[93:64], 32'h0};
+
+    end
+    else if (DATA_WIDTH == 128) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 48; 
+        
+        assign mm_write_byteenable_int[2]   = 16'h000f;
+        assign mm_write_byteenable_int[1]   = 16'h0030;
+        assign mm_write_byteenable_int[0]   = 16'hf000;
+        
+        assign mm_write_writedata_int[2]   = {96'h0, st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {87'h0, st_snk_data[40:32], 32'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[95], owned_by_hardware_wrback, resp_fifo_rdata[93:64], 96'h0};
+
+    end
+    else if (DATA_WIDTH == 256) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 32; 
+        
+        assign mm_write_byteenable_int[2]   = 32'h000f0000;
+        assign mm_write_byteenable_int[1]   = 32'h00300000;
+        assign mm_write_byteenable_int[0]   = 32'hf0000000;
+        
+        assign mm_write_writedata_int[2]   = {96'h0, st_snk_data[31:0], 128'h0};
+        assign mm_write_writedata_int[1]   = {87'h0, st_snk_data[40:32], 160'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[95], owned_by_hardware_wrback, resp_fifo_rdata[93:64], 224'h0};
+
+    end
+    else if (DATA_WIDTH == 512) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 0; 
+        
+        assign mm_write_byteenable_int[2]   = 64'h00000000000f0000;
+        assign mm_write_byteenable_int[1]   = 64'h0000000000300000;
+        assign mm_write_byteenable_int[0]   = 64'hf000000000000000;
+        
+        assign mm_write_writedata_int[2]   = {352'h0, st_snk_data[31:0], 128'h0};
+        assign mm_write_writedata_int[1]   = {343'h0, st_snk_data[40:32], 160'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[95], owned_by_hardware_wrback, resp_fifo_rdata[93:64], 480'h0};
+
+    end
+
+end
+else begin
+
+    assign nxt_desc_pointer_base    = resp_fifo_rdata[31:0];
+
+    if (DATA_WIDTH == 32) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 20; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 28; 
+        
+        assign mm_write_byteenable_int[2]   = 4'hf;
+        assign mm_write_byteenable_int[1]   = 4'h3;
+        assign mm_write_byteenable_int[0]   = 4'hf;
+        
+        assign mm_write_writedata_int[2]   = {st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {23'h0, st_snk_data[40:32]};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[63], owned_by_hardware_wrback, resp_fifo_rdata[61:32]};
+    
+    end
+    else if (DATA_WIDTH == 64) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 24; 
+        
+        assign mm_write_byteenable_int[2]   = 8'h0f;
+        assign mm_write_byteenable_int[1]   = 8'h30;
+        assign mm_write_byteenable_int[0]   = 8'hf0;
+        
+        assign mm_write_writedata_int[2]   = {32'h0, st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {23'h0, st_snk_data[40:32], 32'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[63], owned_by_hardware_wrback, resp_fifo_rdata[61:32], 32'h0};
+
+    end
+    else if (DATA_WIDTH == 128) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 16; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 16; 
+        
+        assign mm_write_byteenable_int[2]   = 16'h000f;
+        assign mm_write_byteenable_int[1]   = 16'h0030;
+        assign mm_write_byteenable_int[0]   = 16'hf000;
+        
+        assign mm_write_writedata_int[2]   = {96'h0, st_snk_data[31:0]};
+        assign mm_write_writedata_int[1]   = {87'h0, st_snk_data[40:32], 32'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[63], owned_by_hardware_wrback, resp_fifo_rdata[61:32], 96'h0};
+
+    end
+    else if (DATA_WIDTH == 256) begin
+        assign mm_write_address_int[2]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[1]      = nxt_desc_pointer_base + 0; 
+        assign mm_write_address_int[0]      = nxt_desc_pointer_base + 0; 
+        
+        assign mm_write_byteenable_int[2]   = 32'h000f0000;
+        assign mm_write_byteenable_int[1]   = 32'h00300000;
+        assign mm_write_byteenable_int[0]   = 32'hf0000000;
+        
+        assign mm_write_writedata_int[2]   = {96'h0, st_snk_data[31:0], 128'h0};
+        assign mm_write_writedata_int[1]   = {87'h0, st_snk_data[40:32], 160'h0};
+        assign mm_write_writedata_int[0]   = {resp_fifo_rdata[63], owned_by_hardware_wrback, resp_fifo_rdata[61:32], 224'h0};
+
+    end
+end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp b/FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..838e6b2659bfe63574177fc9ed0280657ac08512
GIT binary patch
literal 880
zcmV-$1CRWR6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2%+8HaKXuL2<48z-bgZ28|
z_x6Kg9*usYOy$a~4l}(b6x=(zzYt{(SNjx=<n4H^Yq`~si#J@O20vZ^-crll5rgnL
z^m}~TXf8Re?Xff=)j|<|uN@JO+{-Tr2qE&t@^4>lZc9XJTR{#>tk@^`pS=X?(xA`3
zu;IpaqllD#s+A9?{{z*vWz<kW4MEUMvLhzXa9gQMzfD()w{C)h*A*ERmxt^rx1guO
zDpftf=OzAye{QUzWC*|`=Sns9%Jam3ycCEFmG8?>FpPp<*XkDMJ??IVk6H_BPiemB
z{t3nofx<XjNvNUdhFq4APIRo+TO7b6*HVpjUK@WUCUHhpG4t@HI*L1rJWi!AD5%6>
z3hE4w=?W#H!Ro|bS=&Y1r*WI7W1e#o;e4y*uthjIdfd#42z3<>c2@tq`$|D{>uMKh
zjH%Psk`-7EN4LE1>l-qfPYuUu*g4iq*_6e$a5^&3G;wM$$J;2}A`k3hIW@dytP}0z
zUUDIvbY_(?%x4>oJVJlg?<xHnrOYw;J*S7<xhB%RZox<~AjSwc(0I0ZNMbhFodznh
zR#O5@_;%QKos>{l;rpg%KTqBK2VQ+`5f{>tA(L#$*|w0PWJ|$dGOZ$xWB_6+fMW5I
zUL6x)o@lcm8mVlJX85t4`+!X|71Bo`=`=J%!NmJE!D&sl7KPD56LHOTCwX1Ikm05x
zQ=H^!^Qb<?F;@<Trb}nvaeCC;7s6c3CjU{h>I<FT!ieTU<?lN6W4gO=X}KG$iB;YQ
zkV4!DR(%p$Xx4ZG6p<$s2PRMDN3XTV#Nl5Ku(XDY?)d4oBqQXzx=&5xr3{B-m6sg4
zCr&k2iRqPL<z4iS*2G43gnNYv_SoZp(WD(5w!AiE6m!*B!!J_)i9Q4W=e{Ba;A)b#
zwh4Bg5uG0}%06`hg7f&ybCuaA;&tqj3^EXJBe-t1*K2UxErF?N9Bf~XJL&+b?`{rv
z#d|sf>6FmUkqD6Uqk&S?g_3!%0S3To9B9JGobW^`y73m+V_;Zra}+UYOaKiK!zFg1
G?1VW+BCyN=

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv
new file mode 100644
index 0000000000000000000000000000000000000000..6c661ec720aa3c5369f0b7de9343e04783bee50f
GIT binary patch
literal 12424
zcmV;3Fn7<36Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2%+8HaKXuL2<48z-bgZ28|
z_x6Kg9*usYOy$a~4l}(b6x=(zzYt{(SNjx=<n4H^Yq`~si#J@O20vZ^-crll5rgnL
z^m}~TXf8Re?Xff=)j|<|uN@JO+{-Tr2qE&t@^4>lZc9YH<N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}^qo4jU9P5V}q_V_XHeL4ZSm<=6Q
zN_|TVR?xs_l=qFsp-3&E-$@IiXPFU2<ad-WDGKRd{d+}eDV`t4a5m3>kg3hTxSANk
zwaM}p&q?&lYTfmPDwR5u7vW~+DX{Pyc~I{XWbal%ZGs9^$fpOB&QtBNf@5ZKS-D~-
z^a3u=&d=;x_)-77TT=NHwftz{$fl-bv+@v87xM?p=2rXqAUUrNlq3!sxVMZ91NJ9D
zs`3@ZsitX#CxhR$teG*tvChIRR3&~?hbci2VDcI=qpsc<nubE6L`|L^In5`tpk`aG
zP=I=BUGy~g>-tjQZ5vJ&pt&g<I2Es+9!(F!hlUy`DcP)$Jp#hw$@%Pc^#TDX(f}QJ
zK3qWt-2w_+aKY4p9}t^0W}dC;w!Zn*Y=1SypDIvVFEI&UZf?_6EXk8Wzuwc+n|r?x
zIx#%-xEJIRC$iptdFAG~;P8xdLAMNw-u+if;(xSpHSpIhvd8ij)P)D0Spu^9mQr+K
z_{Wm=O)mNV5$qXz^yBiv9}%z6%`HGWKLn!$Pr`c1W_~y{QW7;vm5tTq{I_Jot$+8j
zt$*wXMEKB=P}4w@=DzIGsbeSNi%Qjx?okH+NDZ~!@UazrhLTt9U>U}>Sd!uaD&t@#
zQG<#b*WoBT$FvhdTHDYY_<C=_$o<zS<?!p}Jtg||Jw;@WB>UdDJ8K+u9Ee+dv@$iB
z1nF-LmlHxy0&+n=INKci!Q1I#_@x#S?J<d9OW~kY|16#XP?+>%wk}|3I-LxBqQW8q
z4WZM82fbpIKZX_`<RD}6EGTHn?wy&;U$dDEBc>A&BqWls#6=uLuiJl=I!l(RlGAN3
zX`sE8YW(EMRcJLdEMXz-=cfeX1P8iar0RD*Dc6FG&#mDVwO+h0Gfe3?I^yXU!6Y`V
z6@;24@+xy|h@kF*&GCLG;)!tM8z#<D6|qqP&O2nNRMK#Uqg*%FZM#!^cB^p)Y?Xiv
zCnf8QQ|O@ocEZ9*;7+w_&Oz?qBoRAcHuuVEEn#ErOjot&Pdv_iqx_f9f@oDlC%2E=
z7c@g0pH_7ov0GRJ4<yp!NFq``SgV9Jsx&?NvKOcI?!%c+QM1bidOV9}@>*(fyDt^I
z>n=QUc)%@32UsXTV16WWCDg9&MRUM8qVZ@hX2nwv@)-UMx;G79U%=E0S&xvRat7y1
z{7fT%cAUq_<Nqse!~i|x3L)4>;y$Zec$JlwzkwHcL^1B;M9C+7uyOnW%=GnSl3>VJ
zYHRfD8Cdu+RZ|?f<D}87C}|2vLcn$qg?nYqg%gyUdIT;dvXJ6W@%93w#6>;>e=>)P
zwxGAV&S8y2#J+ZxLa+>_uZbcAp1;xM9;Q2Vll1%g1N}1`iNX>{4@S_`n>Yzw7AlVD
zc#Iv=>3{@SdZ3$l8(NfIDuDB<A}9bEv4Xt|dc$R7ZrT4SK25#1S~7}XE5zJDD3zCn
zHd)8&P56KcfeV-R7F>xL+!e%$%|r~xvZqheXpm;FS^EJ0ejf7ZTF3eyG2EQ3(+(i&
zIqhFl!S;~lrFs3{S)rIk-t*k^JjV!@!Dl-y)kP9_i|1Bl<d}UdBGAGq&=x2WHeA)?
z#lvbRoY5v-OQNt8yaAc9msfZ$>6UsOzO~Mun6&=vY4TNUXqw3I7fPudFe^6ox1Xu*
zq1|oz92=*>wZP9@1UJjvm?%!apK#XPP{`H${>)imh;Q!I{wrWa64f}#%O7!r%?~5M
z=JGXYPc`%@eU-F@K%;DB+u{owoL-t;|7*or1bqoa^GG5GDv=hH48i;JeF7=!-U8>r
z2T3#J)(#6rGp9=@=-6jGYGazQ2gkQ(a@9*5B<bU@KIU=Q-0TK_oR7|)00>0~{acWC
z+s{k!9=dH}9n9xH^R4dHcD?eZD#pL^$vCW-u*d)-t++H57=$ibZ0c+=YcvIbzu#rt
z?m$SiHO2+*ZNs`o<d@zfwCw<oYgyHA`MKX@w~hKoVYlcmtRKWof6vE!z(YryL+2_2
zbZ{TXSe_|2&*qAN@TyB8WyP+Q{QD9}G-`;}323SY6HWOK4KDV4LTd&ExV;=pf<ujQ
z0{mLP-=s^5@AFvS94}Aq2V0f@9nwIQ-ceU80)HKJsHD~57JZ=FE-r(oz_!6O78_vV
z`b5vy2AmdOfi?3GDxGP7((qN(l#81t+~)A}066cI+Xo&I;z#O_-7TKMywZAOt)CYG
zNXwMWg-G`rAwCf;-H-d-spj(sMx+|72M&&XUH_8DLA;Gta<bR%^9_fg@y-bdz`ujl
zQ7_%uFT~W<Zt#RFTuLT^ET|jkH<RxKs^jxcjNWRw##-C}Wl}jOx9+<fWJ}O<5HG9*
zm)#yDo79$x*&(2dTJQ8Bdbti5n?IC+$A!a2#aE{dXtn#w8Mr&NIRV$Vv(m&-u|7~G
z!WAkcw2%q=$?Cm$K<p&qqD%9nS0fxGu#CM&=y4uUsNJ8^xd4JOxbU@nkKmiOm6a-&
zM;`>N!`R+N%w-_y&s{wvXC{cdB`kO>*FJi%?MHi9xkf=LLMCXib)SHke_pr@S;{r+
z*u{23f%mQ40G0g=S(rLYCFkMHE%7LUYf|;IW*Ma-{k8;h3pKwNfF_ox3Xr`oT)J!n
zUPQXdxzIW25c%ZGUAM_;j!c=l<aiKoRi0N~b$LWw!7~P137vj~WQQrSI_Xa%`?*H6
z{_9V97@f**2sDg;d>Dxk%f)6@x^z7>&kGyLN~eFfv9)iyo61*oHsrJ*yIr`p`ByQJ
zck!0|ta$za)(+b{nk}!_tIDf`F7(aOP+G={Pn<@T&)^D<f?jTYbhB7>7IkER6^Lb_
zLZj^hk{*}iz{2H}L|{S`m-6!F&Z%Wus~x{&&D2}j@P`b*`U>W)dORozE%A%4u+1U7
zSZR`H_Z*szjBKO-AcwBs&<TLjChlM}o8dw@uno-^(NOci*iat9vrPt%Dq2%s@^)Vp
ze4T*&Yf4daoNLPPTIjI-Ghc%5x+4i2uW4-|0zdn{3w=wP3~AT^Cx9LkQEf3ZevEo7
zk6M2-okF8%6RC!?Q;#>+6(pct|7({-R=c}7WB^B;+0N1$r$C@F9p~W#y7R4ihX6Oe
zcpw>BOv_lF1N3anSjAVha9_fR_^wcJX={sy|5pa7Z%705bV9EY$J4Ut<+T=Va{_-M
zEw#8VmDqEyH#8Nx&WEZFTFI3tXL<<jE)!<u&&Pp5mF?$_Q2F%G;5tlpH}slBLAyDF
zSmE6<3&kCkO<C0c)O?;cC+hO7upKz(zR*GhC?F5((;|_qj0xrofdDzLX0JaAR3Cuz
zLyNM`vt6A+)>RSGIK?yGX_?g*;4y|#B-q8mL?#80G$gR2odWc?93j<c%f4H-?k<C$
z5uOCmR8Idsgz-C%y2^<4A`d*qvM-ivzPLd^4E+;w^*3p64|A#8T)uo9M)9jYg*&d$
z6&s;2J*SEVjp#A*=W0qju`c)maHRB(9f}sGe(u7G!C&+mxc{%5QgUSqcV6)AC(`*(
zEk|!w=c<in76Dk2tPTj5nSI};I47x%9<Yn#&aIqUW=HB68L`aC_EAB#)(_l1;$Mp)
zD(^P04yNTabI+#opGsSp3Pf1n7GKOm4;FLi<E=c5m{$JNC?sO1gE<)IE6vrPIp&l;
zXwCTjLD?=B^v=&)Svk51{gJorE+SDP;F$}&7y&^oR7kyP;>mHA82d6R4fSiI|N0l}
z-oRz|^!8>nK-~M-C@CKxs2BYZ$uP&tYZA?P=KtJ)0MnG+7&jmhR+SJi(mPb1Z2};R
z$kRMS%x|d}GOQ`r6lH2M`V)Yg%-5X3Z7HexyQukw{|DF>2RCJa|AoREImT_#mNFHK
znB@n|7187}ZM!Z>{W-SNz@MbvQ@(Y*F!Ftu*G!J{U-$`O^h2Qpuzi@Je6(Tn#@h_g
zK-QNtzuz;w*i0~BFWj8|AN6*wwzZ`B0UUI4CvA$xmFygb#MSoKs6TEe3m@=n)EM2I
z<eNuoK}_|8$rU)BAnmsTfdTR6Zn+($HQK}zVxEP76b;qq>N<v6Xo4QG%E+aU$K1J+
z2L{y(1F~ThCd3#<cgpOcTu|edTn4F-LIRZtVM#-|Frabz&JfYL?Leul+vA%n<a}cH
zIs7fY&&^VqIt1Z^=>n-#`cftWOh_49rqW^<?uX;>8|l-p+S))sTCX5r1^vdzbvVSy
zUc+VoyMigP=eCJjS~J<(FXQuvP<=k!c<MRdFtL07oVkl^gA(0~co=KP#0#DmuCtf6
zhHR6=W9rPbRksHAw@zGeK$d>{F2kX{2dJK%PfvD)A3PLhjCI7*wONhw2ZlzGD{xlH
zohD56bk&3GT^7|3uB47py8Z0#wj$2%#=YBOGiF6rVYtCnZ&X*%1sNsZ93$F6QKmjP
z$7Rc6K-DMvY$>vZ&o_U|^A2pnOzrM{UqbI(3S>v=X^;NoOr&SW7cBX!(yl7Z?)&`p
zTO9YGQ5SrSuZ)qf?ALYtbIcu5+F(UF7(!6Tm}%wLKQ7j@DzKXGVfx_p=s=PJepKn}
zzSFf{D?WuHQzLcozc#iU2P@&wGSD9AS+^1E{f-{V^;>jEDEg|{S$z??CHCK(Gzs{*
zNFqh$KdKS70q0{jGoXg~W|(uZ{T>0r)V)3b$A&ILY0q`+C;ZceYVlp_)DWoM;@R1I
zp4)gfNGh2CAkZ2J#`$}!hl4_RTD9RqDZSalv7}q_xIs1H1smu%3=L~v_SCn4wx)fd
zy<p>`#oh0ppwr^Wo-S3+K33fW+vKlJf`~hCb4ybfQN{_Mh{$AzY)=RlD0-a`@aHtE
zqM6Q`KYB}eJv!8v?2{F749!A)1{ZS<RqyDRb{F3Ii9MzbqjuNa{5G=Apg+|UvlUP)
zEMi%5v^eRl^_R)*7MEvCiEdM>*{Fu%DX3MaY-}~ip5hO2y#utlQpVCOM7>0Ip5IoY
zA}!S`25;R^B(dP*t@O9PG!#$2?n%I5PgG%^Y2M9QV<$BN>5GEpDV8dzy?>I)P$Z9J
zd8aK~oh&Kasp`V4TLI@r=Tff2vm@VkCIKdFfOL7xg-wj`hs7$Q@M<L_f?Pq1(QapO
z)CNDe52~dB{8lUGVgY{JZ$gEW%BOR7tWgqr|4<3{Q*2WsIY#AAB1?#C>70$0!L41g
z%W?DRfx2m8UBm8gt_WbAe%lukeO@mQBVSW+U1Orp1>&ZSxsvWTR{h4Yqxzr)33kW#
zeWdt_*I_8akue?j<g|n1tUh35Yn5pyC)GK#o7|wuHVWQV<8STY8=6FiTm4|QqU<&E
zT@=IkR(hh8d+&j_JsV1-rQi@ULnW*CHm1GByW*5|y+R|3lXuZ6GwJCV;(?@;rW(sS
z54P|erW7EKK*a6UPGj~_I&cD?jwRh!c!h#bi3Z=zNjS_@d?B5ycV`n2yWEWQO`mhJ
zx}=h*1F07z3#=@-@_|ws9S(19ydw|S$64{ik|n#do%E|0{J-kKNRIM7I0b2M7*91&
z4+`Lo%LUkpridCQleghprz(d)rHrPf;i5nKqAYL1I=N;NCj8`(i#K+C2^c_#yOEvV
z4SC*e{w^Mr#m{<PbWwg!cO(@(f%_uq=8>stBm*pcH_J@1s6L=$vThK~V}u|4h~hSr
zpw{!0I8gd=q$S8$BGc9;ISFu)eIrr6;jU2)_mAaG4~&(DD1FciWct1c=-L-SscGAW
z?d|-9))2hRwe%uP0H`RX$fdOoKD$#$^ZxEh-CYupLt+us>{&=xI)_j)|DWnfJ0;|&
zY#?JkdA*}nz|P2M87R^+`lCTrSR>VJltb(0gCKdb_=zB(dCe&>fjJ0G*9OjT3!ycH
z;9*jj7k*n}?=Wb3;lp9I_;RGhI63df;zf8rI~JQ>qtUzL`U8Cqv53Bm1Oo6X7;1Ye
zpHKN9Yfoe`=yb+fUI!4e`uxcD5G@v(4p*^$&rz#eiQ8=T5drop6juwOXpDqQ?}y)g
zTTs*5eUt3#D+XCe%@b24u#>OkP<avMt2iY>5AdrF!)z+$+VlQ8d*yYrSfbbsdF8Zv
z2Q;us#cUjf8yCkAqQVpt6Zu?!r#FMe^?}n)-pW=0YQ1+!XYq4qSY;~8!TT;n{9iAm
z6GXSi1X%~AlkW&X*Hv)_QjxU4IJHPMh6DR?*de5D&%5|o2CqSl$6Xv}(sV|pjnTzh
ze3#NcP<SWOou`@zw|tdTL|#0tm~+%t5)#=ExPE=S(Tb}P{f*9X%tH~A%h@+;3&r?V
z?h%0nZV|@vw3CWq5XK=oP=d+z<GysRojZisEz}Pwt18uWu)yn@v>hIG0P4&jQU1il
z)9uTPfu8T`1GO+!%cvPWrkf`zjF;ao#FC#ZLRNvn%0!Zp2pd~w;<<eX*FxC{YI<qB
zZ59ioef2ffTuz}JB`pL8<dU!rMVRuS9tQ>30AyYbizE>t9kyC^Mg@_+56SdT9bQw5
zOrk*x7h_y<n2MYl7EWg`uV!V+(9+djNj^wbR~1%VeSSndzAk#Nfix7^6C3_4_pSYa
zh1GJy6r6fAsG&)j*OeQeOzVPLO@vr?H6;5hykuD`1WI=_du4x5jfSFUl(L~~mx58d
z!IQR89eGP@M?cYB698DGrF+h6pIXR+r0kr9{1inHBt3uf86^U^j)~634L`oreY4^%
zg|K=*B-@&IC4J+|GY7b(!#?#PV#}tpI_92#j#?wN1++=4tJujHKMYvHTRU7sUi8Ty
zB+urqphQF8lQ8^L_Urm6oJPHz6D)@k@TFg^ZcQuzqjms{<M;e&>VSKj4`D4ZBCV?D
zBqH9zABV;=Kt+f9zYNA?V;I37wwB>?ODtrdU%z3Jq$QqC+Y8HS{vjT}UGP)*pV=7z
z<>|iPk)R#52fNq(CnPN{THuIT{)^%BXahu+VX+CrDfMMKZ+9s8;rdIV4K+SO>kvg(
zB3|zK&!PQkeFdVJ;w=R<lD1?U)Opn10LNCx(=3{L%Q_eOTisiYTo|;0ic4ZW%x@v{
z(VD!;n^J3>^VF|Y3<UictW<_b(KKSHkzF0T9e~W$xlbwG{b-!asx)`iO<A-|cn3Id
z{3daV((OF{8--c)$6kOOOmXNt!7Tvjjrpy_CB5ZVT%^Jit2VR;MC#=~pJX8D&gC+`
z3c3bf`e&cKN{@ye&G-(%nZC=t)dt%hNaDIh6pbGs3NPR@cq{BuhI=oG3oaQdzek<K
zD;Kfk-#1B`i!zatRc6in@}TM_D~r{i-$f_Dd^wLz#ifQYTL6*Mu*iV6C^cJEt#Z8f
zeI+3U+qRgU0yN%@QgZ=7*WcUCTirrDq$_rdA#m&t)s+><|BE>oPOZs)+N7{F<yao%
zX|nm&hw-jRAdm}9u2?73=WeR1Py5aw<X>LUiIw2>_q*(V)msI=Wpi`OO7=Z?!aS?T
z+iC=ZN`p%<V${<)Wded^r_aH}XuwUqg~pxKd8c_B3V;om;jjN0ONW@6|9K;XbzTIj
z65aSwz`<I*PFN_!jPIsYoh_!307bEv^dBw&n#7)IGfe`BS$9Fupr5vc;sEj0dN=>N
zk#!v3#UYKx>(Nbys3evLuN-f`l8n+qFlJ9dnl=~=0<rs!(zR;FY*?JHi{|cA$|!{o
zfEAEXNeGcja4KI`=40f}7R#oPxx&ZCDqO$cS}(E0GkI}*df#VDYnr~<HA9o56SEPH
z{Xy@*YG`e!#uliUu@GPLv=&6+`~q;qS${Axl9$~KhCjRWn}Z?U7DK`l9B|Ov6YfEb
zYFH6n#eLS=fL$jFz}65`*CLF{$T8R*42g%ReVh`GC3^mjKtg==$+*pTOE<n?>J#~@
z<$$16W{Qxk``<Kj*Ilf70-%dOU1{0=mr?Gu9R6IYoA|cf^43K*0A(A<H3UxnTcLWM
zZmGh|OKc)+X89`|23f<mJscY-<1Se4oATX!+9$2PbMm0SDTS^;h7uN2Q;hPPM(KS5
zo0GuhrOfuIs7gm^%<0%4)F!6!K?eYyAl}e_=C?H~Er-x!6rE&O&*%T_?(6-Fe<O{X
ziu_7raFTW^l*oXKT5i=&gF_t@qiLMvGxpr5qK|cQq*NM~zX?>|*B<m3g3&~k_v*I;
zUJ9!2=x6v*LF|$Y+*hs}M)-T1FuP|Xs@K|4Ja^*rTSK`g&6!t#j+bv>XXp;G8r*YX
zi9{+lwne^_X-i1d_wMMx=`!m9tDG}aIL2RrA?Wjq9fmsVo?4y%=P7Hb@Cldq!cp`C
zKQq=d{-}vbQga3dlkKJoc?=mzGO01yuQ7vqA7`Z5OQ3k#YeA)z8sG%qIThqUsT{zD
z(O~3;B^471rb7blR|3Yk?i~W^mVO^25&|1#cG$odvoQxsT;S}zR31Vov(v!~vag2P
z7{vsZB)vrODX<u$ig;Cjk)b<ihF0>FX@95C{Nlg2YvglLG|SxbyvafJKWK6Ea`zH@
zd{T8C<v_`hS&7!;+^*Hshn?M-PD3+9XJcsuLygO27V&}MNtI=tx(|?8jNBo|WSd+|
zohFaZr10!raj-q--XliFASnQB%r75ppJRku(kn6PEf=PIy0Cz~+Ov)~wY-Ou=KB5f
z9Z=cZYoORJRR$VB<ducI<nlZh3SK12Ogy9^zAlwcoXK!={AG|w;bD2GS6PJ*ZdmI;
zm&JS)pkjgpq*-$@%_osUjs+1hu(t>&I+|6r(kVF;fcfl(h{#*7KI;T?8~2kEj|HW|
z6MlF%0{_mBO?vg)1QA-p4-XAsf7Es4wN*cDB9U+hRpC1nzF}%HJe9wH|7Ao5?~^c%
z>(FscUMj(Bw(-SP=^%Nzbln6)$B80ktU!?ehvLQYq~ep2nY^<$QLCjQ^(ippAOavN
zJ1;ojAv(jNlCh(CQhh#OwN><6HtGxvM#cIPGi%R4#^8nHudBi)V`;&fui0Agb8yGf
z3*qn7TfpAt3J)I!8D$%|@VYO9M%kOFqufw(lA+O^iRUR#ghEtC;Rs`)n>JIwqrU>4
zkQBk4DhJUF-Dd}sK3iuVdA((>{?6CcZrLG=4I9UUD;u%JoZS+9zg$89j3KmWug8;6
zuuEzZ!>y%7JyvhB1=e$NLWKD#<7b>7(S}(~kz~l#Dt#T5Me!rV7B0&x`n?|F6u{eb
ztBG}}^*8oNqRJz9IJ6I0Y{j~-^Ts@yPwpE7P%Mz1wYUm>>#n0o5B9^RjA@&B;u`CD
z>Y=TpcY*=cN&q0IVY3hNyd2)$pTq~xy|OcO>0}s4tCB&SoVGug(vx2+)uoGAcLdXc
z=0J!gQQYC0!Do}nR`mIjxmd0SflT#TO5k<XTEJSmjWMf-&n-bvWHkOU|BtRwl{wkJ
z|IF|zBv~o38s_#|(=?koaACI?4WE^Y;H&hKtD2mesp2+8q0JMF!GjW|d1RbQ$xKjT
z+2+qyXz(YiH90W(DD#}I3{La83%su}JDoFTW-T%AhLf~2&V0(Y*l}z<2s)+X0?0A@
z(sqh#S270`v%sb#9JW7pGL%=I>8%1<DCN8^PGnlnF;TVKs&4|tJ)PU4mRC_`+Z_Tg
z0FJ1rkaEYE<G<Sm5|(^+K+RCu{;bCVX>s+x+6F8@UUkEf1({nWI228Ym=M2NY=mk8
zDnTR8NJPrXF!a3<*2L?CNI4is@HXLqpZJ@bfW4|6_bPC(@<Fb{?1Vr{!?4B(nu_ci
zsCE|JztJ)?`nY8q4e8Y+s1_&HaMTs0sU=a)3+Gtf$pjYu&R~db9KI^{c?(^t2k2mn
zi=w)_t`zJ!Z+7+v7_xuvb5w3MWGjI0p<rzUdI-sL(5ocz#F|w7Ox+U6SOPeT3MhfQ
z8t!rnGesR_K#-ttCzB>cpe`Uy#I~z8Q>d~J>D9qP_Zepo6UNqxK@n_^(x>{*LbiBQ
z2iw7qRInGQd;swbl1xNP+7A09eGJU+*1b?w1W3~~Xdlp~HFOecyYlBd`qknBtr3_m
z^loQ<9S1iSL7+aa>DQ|UgA(Xmw@@_Af1RU#1uK;P$_gpLpYyCaHHZAs5II%NNBi+2
z!ewll_)H$yLPk_+UwTA}#2C)MV=4~8Jz{Jtd`tt(ae--u54hY_gfU&AYb5JAaF?kE
zICLB|s$d-aBVrnxI%l{CMzCmI;U^oj18>XZ{NpUyo8!bJ;)}00P@A=kiD!sSl69ti
zEdbm3Kj@xTv>__~w+xjTF!A*_(%^<$WE^Y`wlKG4kcdZ)LBj#SegZfyg-wy~On*dz
zjj~Z73<;DQ9sv|8kkiGqEm|);j@FdEtzTjn^fHzxgopak7`WH(eSO~1<yEjbHQ0ZB
zB{VWWrakl((;DF8_LePkThzE|x9;0egJ8%B*XnJD#ZvNH|LxeDQ1yKq$;A&C0(4l+
zo!_+Dk#>&hPP}R~ehSV?(N4rq@tWMN9~=4>IqO1AAL3_czV@KhAb!8se@PEgCtd;Y
zVXQY1P=3*1oJbmJ6`n+Fr!P(HB-KR6L{&Cw$m>nh=Q^y~G009ik%1szq!U5?smf*-
z@->^;Z+eeM_>r<+D|(KFAhCI|DvM27s6meXl&|zwa_u~EPH*fvgmTal2^z$BRR&Ed
zK3)~T4pxCHgvGIL@%H;Gd8q|>+{CG4MTV8n<sAFmL{M!y{dglw9WV{zI_F`GC6^Mw
z0h?2bNX~BPQ@iReA5+hndan69fK7C#n|4ds@dk8zdXo1kt;CW9+{VDrPKa*iJI+3K
zd$E@*?!7c1ie1m!;rrE%OWB-7b42s}!siPXEa#Cx2GhF&QIu@60G^<4PssRddn^Qv
zk%)$eN-qQlnu$_>47cjaPr}cKzrj@zaF>RY^sFB{KC3+`e%=~Ab5VpYV1&~4dkj#<
z1hGq18MCA7R1T)7&U-jA_81R>Hd65806lyw<k`rmtL$dJI-eCv0V2&h%9J?Q(qzc?
z#0Se4BLs-V4U&Lh;`P%IZ(6j_(7IB*+~WC}AE(^hA)_8E(&?qpLxOUdig1wQQaC<q
z_v4fLBU%#;&3rgUKWy@w<?TiDF#x>5r+9EHh>KIt_@6FHq`au4&fYqyqP7-M-iQ9K
zWG6q(h%Rfbxl{&Xo?WS^z6HGg%HRT_J?dxY+(t8-&)7E2HjRD&mHe579{syyYeq7k
zZzM)VFE;q!KvnW*!j(6y!w6xX_sLhuExSQsle&nAN$DGY5_iwo(9sGnkas%HN!pmT
zZ9cPKMb}b%#nHyuR>*+LcI%~*QsMMsN@tTSb*F2`3AW?W)Iy0Z!X1sC4vX}dtp=)6
z8&{BL^xw9*DyI7a01`I^I0S9v{j7|>(E!;3JfrA|3LS&cp<a5$_FNDh8hu9*oeY@~
zxX_l-!U>J^InR(v^c)z@_?0l1$_$@~U%Rr4qDwR-h|1JAyUzP~ptq*Fe6Rc{2H3}=
zeEAd-m`+aQhF4p0K(|!I%s}knCVp}c;t7$vnhlF(2u>7YQ3SEq;C|J24KVqzI8sH&
zuacE$kVpnh%M*U<XoOq~jv3w4>`)~~y1yyqrv?1nWmv|(_5Idr142pBeX)S3<2u*8
z{8#s)XO2s_nmX75#G!h-(21}b2fwxGrU=@ol5)5Q5H$^Z$ngqj>u%`!Z9)p`*u4yF
z86Rc}G%Tq1@r1DXk>OeLrPDMJ!X{N&o=>x)p3hR#d@20$2TP@F-Ei&DdCYNlHV*?&
zef#Lob$`4J5?3rWbpry`S=-0W<04DvO&pBK<`uD#K_3`x@z&DI5~$tb0A&IG2S6$1
zt>4z$0BZ2!x>!MLh-ZUpWN<=F<`Pa<S#GSVxUDm#3yvZ-N^T|So3JQFu1Uj&hKa|l
ze0p?b!hlf@{Svxt=L3vHTt^5n?;@OfH7Vn`n}0aq{zlB)BY@Onm^c~D!${y$>0j;<
zN1O@Q|NACo4Cz{A!ow&tCgx+>%LsBe=xfa=kDoAJ#?&G7mbAcuj#yNlfn5o69NX0Y
zeSR2yKESTjqZ|RFp^0Sdd=37LBv@Gr$B_9bV5xvEtPBHY=K<7lQIdkH3mlUUdl4^I
z&WGLzhn-Jrn$k>~gYU1zZLW$diuyOmb|nNJUw2zdxc~O&&|~f_eHGg<y4AsYZ(5S%
zRF7E1c9BVV3I*+I$W{)~wW6!Q5jA47UU~P(7Z1cKcX|1`gqhQ!eifU&t+a}^OUT%F
z(1mW$wc@)Li`ps)Y=B*3^0ZiEgo^w_lo|7)CpCxrCJ2e+)C@r~_9|l`J&ap1tS`db
zu<gIBXFd!FwLUj-XybFYw@jPOl7l+}UG%ltB>EzUAhM%+oN;o6UX*BBW%y%cCpD+W
zfE>UCgW5?4wR${VQ=tiEa97Rq9%OC{^I%1Q?MptjjrGl1Az=vEc|c`(?^?gRhN04#
zxq->&fIVO8bp0fc)x>5Oo~od{R_#j;gkC6rKx+EvI#Z6%JiGP=AYXfXK4D`p{fR0{
zQ&{*F(Y<G$%_hMp0vcEo*>U~84J2z=>G3WgX7z@Px1Fa~y$IN&=FbLqtK@YPLxv#3
zN+M)eOffGja^SM`2^|64mqFEC{Kr$fo2<bxar&`fs<d0bSd7MGCxir5)^*_Y!-m(@
zc4+%a^^0h$3BQ$?XGGiC#8dH7|KFpi$D{n1+ZG^6wG&(xGgTT4bYe{z$~XOUzcO^P
z#p6kH-owW#EXF&L!TC|yN{L2#<@`)<Yc%rQ_|<vI`Mnrui^9HbTvJpt4DEmzcOGo%
z<wliTaVhf?R<<sw86@)OosG`S^pfEiK-0e{qZMEUm}5TBK>4{}H?}#fYfe_y3xu;a
zYZLdStTKB^@A-JutLw5DWp4G3bq;|yvz^>jW|3o4CN$1HLdtv0y;9))*LA%hZ@ZWq
zj=6*k1Tj#S{{8!Jdf{v$M54;cjF&W=cyi})!>G?UBFJeAy?U=t+`?O2m{6yxgiUo&
zhjW@6w{(Q=x3riLt<RGo_EB77@Igw09Rwkc_+m5R?n?(4QMCU+A5FDBia0c+7RDk<
z_LFWG6Y7*BX_OACC$>RU1X*p-rrBgJ1;C?;OWF^-i&sZCj6SZ-*HhO7LKXyiPor@d
z4b2rB`?SE&!oriY8>nXE2SYzt3$*kP@=M?s#{waWU-?k?PJGHJ6{b^-OE|q&Evs~w
zQvBM1+TFR^Y$wMFjx5-MUHCsO7<PNtSd;msF#Zc5uH+0LBW@{X5U}SC8o7)Lhbm#Y
z1Qs;672+58aE74v1nj3CUcmQPdiY%dMLjU}e9gg2C@$jQH*axul(7{bv2ro^6B-ul
zc(L}dp07nrq^`PE6uVq|Tkfp1RjJbXItx%Z2TqMfq;B&4Tm@p}#lC17yCmc*xN=XI
zyaOA{zqH>x`6+-Kx&6fjZWzL*P>B=|4t`SVPkCN$hOgQ)WP}<*O8PPA86aEBZxNzB
ze$x8*Ro8B-V`WdWkLi%ql~qg9ssfBr_rg8oA?E0%B)HKp=3EUZm8zmF&d<!aa(4;i
zRreK5vynr?+cHN#&l}t1Ko#KPz%i$)GiEZXIevCjj0G_$e2&pU4>l@#Ao<qcC~|nB
zxm%Wrkxv~R3(SW&*veX>P43F&uM?FC*)PNz=nRtlVl&;21;K($Sj8s37>3V?B{@O#
zvWp6Do{L*+4T@CkQ+X3FCC<Ibw3f2AJH~ZUQz~wf)UjUsQxJ=hH)3s3IIUdo+IxZx
zj!Aa-4=vL0@qN%iDeZZ2_W0b2(Q<{k26<x4X+9LIX8;Uah^bs41!feDFvYO4+Di^W
zj*>Q!=&QmsDZn)}7G2cQn%LEL*0<>?ylVFeE3<r6>;MW~Hag8{u6ooj?qfHw$=M+F
zFZ0}Yy8NDoGQPczq89n)M9uHkt{2S9y$L5>AZEcy1)0=A`do39TcBK}+(SwO#k>96
zpG!MBnUJ*~J)7hu)#o-esvI3tF&GoxMq{KX%&&LJ9vP5==!U?QqZrrE;z;KYGrw@Y
zNh%yI>Uy!~;h;!l2$H{sg`decC=Ha(^B)*|WA&_zkIn*GlSJfIgEcjL^@cTCN#VHg
z<h@I^fUHZdpO{z`REIhX?h}*sgyy02mkNJ<1<BWu52d0Rb!XyyT*>Tao!voJc!JoM
ze8bc`=iZAWV{mf}0VZz_f`*E4Y-_hG#$U4#?);4ZH=FDt<`*Ja?*t{AFTasX_~0{O
zgUs-ovOxrlh~lz7P%ptk;fVdOu4ffN_qO>>V6Te{-dD=Acoy%uM5fnkE&>%JAx_rq
z8dl65>;xMYGzw|(AlFE{_z1VXDaR9qNMSdiyA4ho45-~0>Au{;*YfE3r){r8QSQ0V
zKX$odRyz3yu4l1r<iPN2oD&#NrCej4?4`0LkZf_Xmf3Nd17H@kkMn0kAd$1cCl<Ef
zN5F^0d^nqI7H|CW4fF6h_BdlZ2P1anTc}Ik<iSs@UQR;BgnHmB8F3IRnv@K0zo!r+
z46(Iz4DcKvU1t?Axao<y*?WMadzps<P#yna6G3Cn<jxG<sgvZzOW7)sWM4y~Oh4OR
zKVF!VekA5YF4qwY(3MJ7fgVMYK+Gx4vA-O7tqRHOFxH<Blr+0l%Ej6Bf^<V6yZYx~
zI};*w98i>40DTsqKpX{nv;i8LqLdY49Lv5qa7S7xR-gF99Iy-OEOGL{x)Wtvbq&U1
z*%j(QlUd|$?sE0l8Ku1F@L#w9WcLv-6gV6~7d=)I5vgaV^zU(1Y#OVO!59l)-p|c0
zSjJn@fCOu|q~85*iwz@l22)NXb>MCW!_CrQA+N~LE`dKobZy3<5n~Q#!|R@7L6JE9
zRP}=>Wf`o&*o7oo{Nj7VXsR<BXdXgn2MNBsc;hPsm};61ujR;P<t{);^l;u_Eul{=
zQ04}UnO#---i40Fg1peaalbxyZ@@0^uLS9`gx452`mHxqWR~vJMowyPkE*aFZ%ofF
z_sPQ#&{vmSi|BU8QgMlg&bidmsWhdDM|)`Mic{*HvK@ko3L;kABWJlbHe-e&)ZjBu
zt<N+TcSz6w(`O#z5T!sQ?QumGyl&>Fbj%5uPbvpE0)5z6L(Q((qq%X}(TK0fhnl;I
zQ%9RC&Y1eWb--~<M{V?osY0Qb-b@rH@`9g>nHgb=%M`L02wXB0ia%2_tx;m#Up<aL
G@~GaHkUbj!

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.sdc b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.sdc
new file mode 100644
index 0000000..44b5b3b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.sdc
@@ -0,0 +1,92 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -to [get_registers {*|flash_busy_reg}]
+set_false_path -to [get_registers {*|flash_busy_clear_reg}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.v
new file mode 100644
index 0000000..5a00d87
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash.v
@@ -0,0 +1,331 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//   ALTERA_ONCHIP_FLASH
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module  altera_onchip_flash ( 
+	// To/From System
+	clock,
+	reset_n,
+	
+	// To/From Avalon_MM data slave interface
+	avmm_data_read,
+	avmm_data_write,
+	avmm_data_addr,
+	avmm_data_writedata,
+	avmm_data_burstcount,
+	avmm_data_waitrequest,
+	avmm_data_readdatavalid,
+	avmm_data_readdata,
+	
+	// To/From Avalon_MM csr slave interface
+	avmm_csr_read,
+	avmm_csr_write,
+	avmm_csr_addr,
+	avmm_csr_writedata,
+	avmm_csr_readdata
+);
+	parameter DEVICE_FAMILY = "MAX 10";
+	parameter PART_NAME = "Unknown";
+	parameter IS_DUAL_BOOT = "False";
+	parameter IS_ERAM_SKIP = "False";
+	parameter IS_COMPRESSED_IMAGE = "False";
+	parameter INIT_FILENAME = "";
+
+	// simulation only start
+	parameter DEVICE_ID = "08";
+	parameter INIT_FILENAME_SIM = "";
+	// simulation only end
+
+	parameter PARALLEL_MODE = 0;
+	parameter READ_AND_WRITE_MODE = 0;
+	parameter WRAPPING_BURST_MODE = 0;
+	
+	parameter AVMM_CSR_DATA_WIDTH = 32;
+	parameter AVMM_DATA_DATA_WIDTH = 32;
+	parameter AVMM_DATA_ADDR_WIDTH = 20;
+	parameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
+	parameter FLASH_DATA_WIDTH = 32;
+	parameter FLASH_ADDR_WIDTH = 23;
+	parameter FLASH_SEQ_READ_DATA_COUNT = 2;	//number of 32-bit data per sequential read. only need in parallel mode.
+	parameter FLASH_READ_CYCLE_MAX_INDEX = 3;	//period to for each sequential read. only need in parallel mode.
+	parameter FLASH_ADDR_ALIGNMENT_BITS = 1; 	//number of last addr bits for alignment. only need in parallel mode.
+	parameter FLASH_RESET_CYCLE_MAX_INDEX = 28;	//period that required by flash before back to idle for erase and program operation
+	parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
+	parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
+	parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
+	parameter MIN_VALID_ADDR = 1;
+	parameter MAX_VALID_ADDR = 1;
+	parameter MIN_UFM_VALID_ADDR = 1;
+	parameter MAX_UFM_VALID_ADDR = 1;
+	parameter SECTOR1_START_ADDR = 1;
+	parameter SECTOR1_END_ADDR = 1;
+	parameter SECTOR2_START_ADDR = 1;
+	parameter SECTOR2_END_ADDR = 1;
+	parameter SECTOR3_START_ADDR = 1;
+	parameter SECTOR3_END_ADDR = 1;
+	parameter SECTOR4_START_ADDR = 1;
+	parameter SECTOR4_END_ADDR = 1;
+	parameter SECTOR5_START_ADDR = 1;
+	parameter SECTOR5_END_ADDR = 1;
+	parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+	parameter SECTOR1_MAP = 1;
+	parameter SECTOR2_MAP = 1;
+	parameter SECTOR3_MAP = 1;
+	parameter SECTOR4_MAP = 1;
+	parameter SECTOR5_MAP = 1;
+	parameter ADDR_RANGE1_END_ADDR = 1;
+	parameter ADDR_RANGE2_END_ADDR = 1;
+	parameter ADDR_RANGE1_OFFSET = 1;
+	parameter ADDR_RANGE2_OFFSET = 1;
+	parameter ADDR_RANGE3_OFFSET = 1;
+	// To/From System
+	input clock;
+	input reset_n;
+
+	// To/From Avalon_MM data slave interface
+	input avmm_data_read;
+	input avmm_data_write;
+	input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
+	input [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
+	input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
+	output avmm_data_waitrequest;
+	output avmm_data_readdatavalid;
+	output [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
+
+	// To/From Avalon_MM csr slave interface
+	input avmm_csr_read;
+	input avmm_csr_write;
+	input avmm_csr_addr;
+	input [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
+	output [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
+
+	wire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
+	wire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
+	wire [31:0] csr_control_wire;
+	wire [9:0] csr_status_wire;
+	wire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
+	wire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
+	wire flash_busy;
+	wire flash_se_pass;
+	wire flash_sp_pass;
+	wire flash_osc;
+	wire flash_xe_ye;
+	wire flash_se;
+	wire flash_arclk;
+	wire flash_arshft;
+	wire flash_drclk;
+	wire flash_drshft;
+	wire flash_drdin;
+	wire flash_nprogram;
+	wire flash_nerase;
+	wire flash_par_en;
+	wire flash_xe_ye_wire;
+	wire flash_se_wire;
+	
+	assign avmm_data_readdata = avmm_data_readdata_wire;
+
+	generate
+		if (READ_AND_WRITE_MODE == 0) begin
+			assign avmm_csr_readdata = 32'hffffffff;
+			assign csr_control_wire = 32'h3fffffff;
+		end
+		else begin
+			assign avmm_csr_readdata = avmm_csr_readdata_wire;
+		end
+	endgenerate
+
+	generate
+		if (DEVICE_ID == "02" || DEVICE_ID == "01") begin
+			assign flash_par_en = 1'b1;
+			assign flash_xe_ye = 1'b1;
+			assign flash_se = 1'b1;
+		end
+		else begin
+			assign flash_par_en = PARALLEL_MODE[0];
+			assign flash_xe_ye = flash_xe_ye_wire;
+			assign flash_se = flash_se_wire;
+		end
+	endgenerate
+	
+	generate
+		if (READ_AND_WRITE_MODE) begin
+			// -------------------------------------------------------------------
+			// Instantiate a Avalon_MM csr slave controller
+			// -------------------------------------------------------------------	
+			altera_onchip_flash_avmm_csr_controller avmm_csr_controller ( 
+				// To/From System
+				.clock(clock),
+				.reset_n(reset_n),
+
+				// To/From Avalon_MM csr slave interface
+				.avmm_read(avmm_csr_read),
+				.avmm_write(avmm_csr_write),
+				.avmm_addr(avmm_csr_addr),
+				.avmm_writedata(avmm_csr_writedata),
+				.avmm_readdata(avmm_csr_readdata_wire),
+		
+				// To/From Avalon_MM data slave interface
+				.csr_control(csr_control_wire),
+				.csr_status(csr_status_wire)
+			);
+		end
+	endgenerate
+
+	// -------------------------------------------------------------------
+	// Instantiate a Avalon_MM data slave controller
+	// -------------------------------------------------------------------	
+	altera_onchip_flash_avmm_data_controller # (
+
+		.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
+		.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
+		.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
+		.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
+		.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
+		.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
+		.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
+		.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
+		.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
+		.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
+		.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
+		.MIN_VALID_ADDR (MIN_VALID_ADDR),
+		.MAX_VALID_ADDR (MAX_VALID_ADDR),
+		.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
+		.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
+		.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
+		.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
+		.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
+		.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
+		.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
+		.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
+		.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
+		.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
+		.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
+		.SECTOR1_MAP (SECTOR1_MAP),
+		.SECTOR2_MAP (SECTOR2_MAP),
+		.SECTOR3_MAP (SECTOR3_MAP),
+		.SECTOR4_MAP (SECTOR4_MAP),
+		.SECTOR5_MAP (SECTOR5_MAP),
+		.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
+		.ADDR_RANGE2_END_ADDR (ADDR_RANGE2_END_ADDR),
+		.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
+		.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
+		.ADDR_RANGE3_OFFSET (ADDR_RANGE3_OFFSET)
+
+	) avmm_data_controller ( 
+		// To/From System
+		.clock(clock),
+		.reset_n(reset_n),
+		
+		// To/From Flash IP interface
+		.flash_busy(flash_busy),
+		.flash_se_pass(flash_se_pass),
+		.flash_sp_pass(flash_sp_pass),
+		.flash_osc(flash_osc),
+		.flash_drdout(flash_drdout_wire),
+		.flash_xe_ye(flash_xe_ye_wire),
+		.flash_se(flash_se_wire),
+		.flash_arclk(flash_arclk),
+		.flash_arshft(flash_arshft),
+		.flash_drclk(flash_drclk),
+		.flash_drshft(flash_drshft),
+		.flash_drdin(flash_drdin),
+		.flash_nprogram(flash_nprogram),
+		.flash_nerase(flash_nerase),
+		.flash_ardin(flash_ardin_wire),
+
+		// To/From Avalon_MM data slave interface
+		.avmm_read(avmm_data_read),
+		.avmm_write(avmm_data_write),
+		.avmm_addr(avmm_data_addr),
+		.avmm_writedata(avmm_data_writedata),
+		.avmm_burstcount(avmm_data_burstcount),
+		.avmm_waitrequest(avmm_data_waitrequest),
+		.avmm_readdatavalid(avmm_data_readdatavalid),
+		.avmm_readdata(avmm_data_readdata_wire),
+
+		// To/From Avalon_MM csr slave interface
+		.csr_control(csr_control_wire),
+		.csr_status(csr_status_wire)
+	);
+	
+	// -------------------------------------------------------------------
+	// Instantiate wysiwyg for onchip flash block
+	// -------------------------------------------------------------------
+	altera_onchip_flash_block # (
+	
+		.DEVICE_FAMILY (DEVICE_FAMILY),
+		.PART_NAME (PART_NAME),
+		.IS_DUAL_BOOT (IS_DUAL_BOOT),
+		.IS_ERAM_SKIP (IS_ERAM_SKIP),
+		.IS_COMPRESSED_IMAGE (IS_COMPRESSED_IMAGE),
+		.INIT_FILENAME (INIT_FILENAME),
+		.MIN_VALID_ADDR (MIN_VALID_ADDR),
+		.MAX_VALID_ADDR (MAX_VALID_ADDR),
+		.MIN_UFM_VALID_ADDR (MIN_UFM_VALID_ADDR),
+		.MAX_UFM_VALID_ADDR (MAX_UFM_VALID_ADDR),
+		.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
+        .ADDR_RANGE2_END_ADDR (ADDR_RANGE2_END_ADDR),
+		.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
+		.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
+		.ADDR_RANGE3_OFFSET (ADDR_RANGE3_OFFSET),
+		// simulation only start
+		.DEVICE_ID (DEVICE_ID),
+		.INIT_FILENAME_SIM (INIT_FILENAME_SIM)
+		// simulation only end
+		
+	) altera_onchip_flash_block (
+		.xe_ye(flash_xe_ye),
+		.se(flash_se),
+		.arclk(flash_arclk),
+		.arshft(flash_arshft),
+		.ardin(flash_ardin_wire),
+		.drclk(flash_drclk),
+		.drshft(flash_drshft),
+		.drdin(flash_drdin),
+		.nprogram(flash_nprogram),
+		.nerase(flash_nerase),
+		.nosc_ena(1'b0),
+		.par_en(flash_par_en),
+		.drdout(flash_drdout_wire),
+		.busy(flash_busy),
+		.se_pass(flash_se_pass),
+		.sp_pass(flash_sp_pass),
+		.osc(flash_osc)
+	);
+	
+	
+endmodule //altera_onchip_flash
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
new file mode 100644
index 0000000..3813fac
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
@@ -0,0 +1,182 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_avmm_csr_controller (
+	// To/From System
+	clock,
+	reset_n,
+
+	// To/From Avalon_MM csr slave interface
+	avmm_read,
+	avmm_write,
+	avmm_addr,
+	avmm_writedata,
+	avmm_readdata,
+	
+	// To/From Avalon_MM data slave interface
+	csr_status,
+	csr_control
+);
+
+	parameter AVMM_CSR_DATA_WIDTH = 32;
+
+	localparam [1:0]	ERASE_ST_IDLE = 0,
+						ERASE_ST_PENDING = 1,
+						ERASE_ST_BUSY = 2;
+
+	localparam [1:0]	STATUS_IDLE = 0,
+						STATUS_BUSY_ERASE = 1,
+						STATUS_BUSY_WRITE = 2,
+						STATUS_BUSY_READ = 3;
+
+	// To/From System
+	input clock;
+	input reset_n;
+
+	// To/From Avalon_MM csr slave interface
+	input avmm_read;
+	input avmm_write;
+	input avmm_addr;
+	input [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
+	output [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
+	
+	// To/From Avalon_MM data slave interface
+	input [9:0] csr_status;
+	output [31:0] csr_control;
+	
+	reg [22:0] csr_sector_page_erase_addr_reg;
+	reg [4:0] csr_wp_mode;
+	reg [1:0] csr_erase_state;
+	reg csr_control_access;
+	reg reset_n_reg1;
+	reg reset_n_reg2;
+
+	wire reset_n_w;
+	wire is_idle;
+	wire is_erase_busy;
+	wire valid_csr_erase_addr;
+	wire valid_csr_write;
+	wire [31:0] csr_control_signal;
+	wire [22:0] csr_erase_addr;
+
+	assign is_idle = (csr_status[1:0] == STATUS_IDLE);
+	assign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
+	assign csr_erase_addr = avmm_writedata[22:0];
+	assign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
+	assign valid_csr_write = (avmm_write & avmm_addr);		
+	assign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
+	assign csr_control = csr_control_signal;
+	assign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
+
+	// avoid async reset removal issue 
+	assign reset_n_w = reset_n_reg2;
+	
+	// Initiate register value for simulation. The initiate value can't be xx
+	initial begin
+		csr_sector_page_erase_addr_reg <= {(23){1'b1}};
+		csr_wp_mode = {(5){1'b1}};
+		csr_erase_state = ERASE_ST_IDLE;
+		csr_control_access = 1'b0;
+		reset_n_reg1 = 1'b0;
+		reset_n_reg2 = 1'b0;
+	end
+
+	// -------------------------------------------------------------------
+	// Avoid async reset removal issue 
+	// -------------------------------------------------------------------
+	always @ (negedge reset_n or posedge clock) begin
+		if (~reset_n) begin
+			{reset_n_reg2, reset_n_reg1} <= 2'b0;
+		end
+		else begin
+			{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
+		end
+	end
+	
+	// -------------------------------------------------------------------
+	// Avalon_MM read/write
+	// -------------------------------------------------------------------		
+	always @ (posedge clock) begin
+		
+		// synchronous reset
+		if (~reset_n_w) begin
+
+			// reset all register
+			csr_sector_page_erase_addr_reg <= {(23){1'b1}};
+			csr_wp_mode <= {(5){1'b1}};
+			csr_erase_state <= ERASE_ST_IDLE;
+			csr_control_access <= 1'b0;
+
+		end
+		else begin
+
+			// store read address
+			if (avmm_read) begin
+				csr_control_access <= avmm_addr;
+			end
+		
+			// write control register
+			if (valid_csr_write) begin
+				csr_wp_mode <= avmm_writedata[27:23];
+				if (is_idle) begin 
+					csr_sector_page_erase_addr_reg <= avmm_writedata[22:0]; 
+				end
+			end
+		
+			// erase control fsm
+			case (csr_erase_state)
+				ERASE_ST_IDLE:
+					if (is_idle && valid_csr_write && valid_csr_erase_addr) begin 
+						csr_erase_state <= ERASE_ST_PENDING;
+					end
+				ERASE_ST_PENDING:
+					if (is_erase_busy) begin 
+						csr_erase_state <= ERASE_ST_BUSY; 
+					end
+				ERASE_ST_BUSY:
+					if (is_idle) begin
+						csr_erase_state <= ERASE_ST_IDLE; 
+					end
+				default: begin
+					csr_erase_state <= ERASE_ST_IDLE;
+				end
+			endcase
+		end
+		
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
new file mode 100644
index 0000000..0fef6ec
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
@@ -0,0 +1,1263 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_avmm_data_controller (
+    // To/From System
+    clock,
+    reset_n,
+    
+    // To/From Flash IP interface
+    flash_busy,
+    flash_se_pass,
+    flash_sp_pass,
+    flash_osc,
+    flash_drdout,
+    flash_xe_ye,
+    flash_se,
+    flash_arclk,
+    flash_arshft,
+    flash_drclk,
+    flash_drshft,
+    flash_drdin,
+    flash_nprogram,
+    flash_nerase,
+    flash_ardin,
+        
+    // To/From Avalon_MM data slave interface
+    avmm_read,
+    avmm_write,
+    avmm_addr,
+    avmm_writedata,
+    avmm_burstcount,
+    avmm_waitrequest,
+    avmm_readdatavalid,
+    avmm_readdata,
+        
+    // To/From Avalon_MM csr slave interface
+    csr_control,
+    csr_status
+);
+
+    parameter READ_AND_WRITE_MODE = 0;
+    parameter WRAPPING_BURST_MODE = 0;
+    parameter DATA_WIDTH = 32;
+    parameter AVMM_DATA_ADDR_WIDTH = 20;
+    parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
+    parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
+    parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
+    parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
+    parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
+    parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
+    parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
+    parameter MIN_VALID_ADDR = 1;
+    parameter MAX_VALID_ADDR = 1;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+    parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+    parameter SECTOR1_MAP = 1;
+    parameter SECTOR2_MAP = 1;
+    parameter SECTOR3_MAP = 1;
+    parameter SECTOR4_MAP = 1;
+    parameter SECTOR5_MAP = 1;
+    parameter ADDR_RANGE1_END_ADDR = 1;
+    parameter ADDR_RANGE2_END_ADDR = 1;
+    parameter ADDR_RANGE1_OFFSET = 1;
+    parameter ADDR_RANGE2_OFFSET = 1;
+    parameter ADDR_RANGE3_OFFSET = 1;
+
+    localparam [1:0]    ERASE_ST_IDLE = 0,
+                        ERASE_ST_PENDING = 1,
+                        ERASE_ST_BUSY = 2;
+
+    localparam [1:0]    STATUS_IDLE = 0,
+                        STATUS_BUSY_ERASE = 1,
+                        STATUS_BUSY_WRITE = 2,
+                        STATUS_BUSY_READ = 3;
+
+    localparam [2:0]    WRITE_STATE_IDLE = 0,
+                        WRITE_STATE_ADDR = 1,
+                        WRITE_STATE_WRITE = 2,
+                        WRITE_STATE_WAIT_BUSY = 3,
+                        WRITE_STATE_WAIT_DONE = 4,
+                        WRITE_STATE_RESET = 5,
+                        WRITE_STATE_ERROR = 6;
+
+    localparam [2:0]    ERASE_STATE_IDLE = 0,
+                        ERASE_STATE_ADDR = 1,
+                        ERASE_STATE_WAIT_BUSY = 2,
+                        ERASE_STATE_WAIT_DONE = 3,
+                        ERASE_STATE_RESET = 4,
+                        ERASE_STATE_ERROR = 5;
+
+    localparam [2:0]    READ_STATE_IDLE = 0,
+                        READ_STATE_ADDR = 1,
+                        READ_STATE_READ = 2,
+                        READ_STATE_SETUP = 2,
+                        READ_STATE_DUMMY = 3,
+                        READ_STATE_READY = 4,
+                        READ_STATE_FINAL = 5,
+                        READ_STATE_CLEAR = 6,
+                        READ_STATE_PULSE_SE = 7;
+
+    localparam [0:0]    READ_SETUP = 0,
+                        READ_RECV_DATA = 1;
+
+    localparam [1:0]    READ_VALID_IDLE = 0,
+                        READ_VALID_READING = 1,
+                        READ_VALID_PRE_READING = 2;
+
+    // To/From System
+    input clock;
+    input reset_n;
+    
+    // To/From Flash IP interface
+    input flash_busy;
+    input flash_se_pass;
+    input flash_sp_pass;
+    input flash_osc;
+    input [DATA_WIDTH-1:0] flash_drdout;
+    output flash_xe_ye;
+    output flash_se;
+    output flash_arclk;
+    output flash_arshft;
+    output flash_drclk;
+    output flash_drshft;
+    output flash_drdin;
+    output flash_nprogram;
+    output flash_nerase;
+    output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
+        
+    // To/From Avalon_MM data slave interface
+    input avmm_read;
+    input avmm_write;
+    input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
+    input [DATA_WIDTH-1:0] avmm_writedata;
+    input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
+    output avmm_waitrequest;
+    output avmm_readdatavalid;
+    output reg [DATA_WIDTH-1:0] avmm_readdata;
+        
+    // To/From Avalon_MM csr slave interface
+    input [31:0] csr_control;
+    output [9:0] csr_status;
+
+    reg reset_n_reg1;
+    reg reset_n_reg2;
+    reg [1:0] csr_status_busy;
+    reg csr_status_e_pass;
+    reg csr_status_w_pass;
+    reg csr_status_r_pass;
+    reg [2:0] erase_state;
+    reg [2:0] write_state;
+    reg [2:0] read_state;
+    reg avmm_read_state;
+    reg [1:0] avmm_read_valid_state;
+    reg avmm_readdatavalid_reg;
+    reg avmm_readdata_ready;
+    reg [2:0] flash_sector_addr;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
+    reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
+    reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
+    reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
+    reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
+    reg write_drclk_en;
+    reg read_drclk_en;
+    reg enable_arclk_sync_reg;
+    reg enable_arclk_neg_reg;
+    reg enable_arclk_neg_pos_reg;
+    reg enable_drclk_neg_reg;
+    reg enable_drclk_neg_pos_reg;
+    reg enable_drclk_neg_pos_write_reg;
+    reg flash_drdin_neg_reg;
+    reg [15:0] write_count;
+    reg [25:0] erase_count;
+    reg [2:0] read_count;
+    reg [2:0] read_ctrl_count;
+    reg [2:0] data_count;
+    reg write_timeout;
+    reg write_wait;
+    reg write_wait_neg;
+    reg erase_timeout;
+    reg read_wait;
+    reg read_wait_neg;
+    reg flash_drshft_reg;
+    reg flash_drshft_neg_reg;
+    reg flash_se_neg_reg;
+    reg flash_se_pass_reg;
+    reg flash_sp_pass_reg;
+    reg flash_busy_reg;
+    reg flash_busy_clear_reg;
+    reg erase_busy_scan;
+    reg write_busy_scan;
+    reg is_sector1_writable_reg;
+    reg is_sector2_writable_reg;
+    reg is_sector3_writable_reg;
+    reg is_sector4_writable_reg;
+    reg is_sector5_writable_reg;
+
+    wire reset_n_w;
+    wire is_addr_within_valid_range;
+    wire is_addr_writable;
+    wire is_sector_writable;
+    wire is_erase_addr_writable;
+    wire [2:0] cur_e_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
+    wire [2:0] flash_sector_wire;
+    wire is_valid_write_burst_count;
+    wire is_erase_busy;
+    wire is_write_busy;
+    wire is_read_busy;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
+    wire [19:0] csr_page_erase_addr;
+    wire [2:0] csr_sector_erase_addr;
+    wire valid_csr_sector_erase_addr;
+    wire [1:0] csr_erase_state;
+    wire [4:0] csr_write_protection_mode;
+    wire valid_csr_erase;
+    wire valid_command;
+    wire flash_drdin_w;
+    wire flash_arclk_arshft_en_w;
+    wire flash_se_w;
+    wire is_busy;
+    wire write_wait_w;
+    wire read_wait_w;
+    wire flash_busy_sync;
+    wire flash_busy_clear_sync;
+
+    generate // generate combi based on read and write mode
+        if (READ_AND_WRITE_MODE == 1) begin
+            assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
+            assign is_write_busy = (write_state != WRITE_STATE_IDLE);
+            assign is_read_busy = (read_state != READ_STATE_IDLE);
+            assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
+            assign flash_drdin = flash_drdin_neg_reg;
+            assign write_wait_w = (write_wait || write_wait_neg);
+            assign is_erase_addr_writable =
+                (valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
+            assign csr_write_protection_mode = csr_control[27:23];
+            assign is_valid_write_burst_count = (avmm_burstcount == 1);
+            always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_addr_wire_neg_reg <= 0;
+                end
+                else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
+                    flash_addr_wire_neg_reg <=  { flash_sector_addr, 1'b0, {(19){1'b1}}};
+                end
+                else begin
+                    flash_addr_wire_neg_reg <= flash_page_addr;
+                end
+            end
+            
+        end
+        else begin
+            assign is_erase_busy = 1'b0;
+            assign is_write_busy = 1'b0;
+            assign is_read_busy = (read_state != READ_STATE_IDLE);
+            assign is_busy = is_read_busy;
+            assign flash_drdin = 1'b1;
+            assign write_wait_w = 1'b0;
+             always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_addr_wire_neg_reg <= 0;
+                end
+                else begin
+                    flash_addr_wire_neg_reg <= flash_page_addr;
+                end
+            end
+        end
+    endgenerate    
+    
+    assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
+    assign csr_page_erase_addr = csr_control[19:0];
+    assign csr_sector_erase_addr = csr_control[22:20];
+    assign csr_erase_state = csr_control[31:30];
+    assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
+    assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
+    assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
+
+    assign cur_read_addr = avmm_addr;
+    assign read_wait_w = (read_wait || read_wait_neg);
+    
+    generate // generate combi based on read burst mode
+        if (WRAPPING_BURST_MODE == 0) begin
+            // incrementing read
+            assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
+            assign cur_e_addr = csr_sector_erase_addr;
+            assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
+            assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
+            assign flash_se_w = (read_state == READ_STATE_SETUP);
+            assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
+            assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
+        end
+        else begin
+            // wrapping read
+            assign cur_e_addr = csr_sector_erase_addr;
+            assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
+            assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
+            assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
+            assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
+        end
+    endgenerate
+    
+    assign flash_arshft = 1'b1;
+    assign flash_drshft = flash_drshft_neg_reg;
+    assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
+    assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
+    assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
+    assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
+    assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
+    assign flash_se = flash_se_neg_reg;
+    assign flash_ardin = flash_addr_wire_neg_reg;
+
+    assign avmm_readdatavalid = avmm_readdatavalid_reg;    
+    always @(posedge clock) begin
+        if (~reset_n_w | ~csr_status_r_pass) begin
+            avmm_readdata <= 32'hffffffff;
+         end
+         else begin
+            avmm_readdata <= flash_drdout;
+         end
+    end
+
+    // avoid async reset removal issue 
+    assign reset_n_w = reset_n_reg2;
+
+    // initial register
+    initial begin
+        csr_status_busy = STATUS_IDLE;
+        csr_status_e_pass = 0;
+        csr_status_w_pass = 0;
+        csr_status_r_pass = 0;
+        avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
+        avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
+        erase_state = ERASE_STATE_IDLE;
+        write_state = WRITE_STATE_IDLE;
+        read_state = READ_STATE_IDLE;
+        avmm_read_state = READ_SETUP;
+        avmm_read_valid_state = READ_VALID_IDLE;
+        avmm_readdatavalid_reg = 0;
+        avmm_readdata_ready = 0;
+        flash_sector_addr = 0;
+        flash_page_addr = 0;
+        flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
+        flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
+        write_drclk_en = 0;
+        read_drclk_en = 0;
+        flash_drshft_reg = 1;
+        flash_drshft_neg_reg = 1;
+        flash_busy_reg = 0;
+        flash_busy_clear_reg = 0;
+        flash_se_neg_reg = 0;
+        flash_se_pass_reg = 0;
+        flash_sp_pass_reg = 0;
+        erase_busy_scan = 0;
+        write_busy_scan = 0;
+        flash_seq_read_ardin = 0;
+        enable_arclk_neg_reg = 0;
+        enable_arclk_neg_pos_reg = 0;
+        enable_drclk_neg_reg = 0;
+        enable_drclk_neg_pos_reg = 0;
+        enable_drclk_neg_pos_write_reg = 0;
+        flash_drdin_neg_reg = 0;
+        write_count = 0;
+        erase_count = 0;
+        read_ctrl_count = 0;        
+        data_count = 0;
+        write_timeout = 0;
+        erase_timeout = 0;
+        write_wait = 0;
+        write_wait_neg = 0;
+        reset_n_reg1 = 0;
+        reset_n_reg2 = 0;
+        read_wait = 0;
+        read_wait_neg = 0;
+        read_count = 0;
+        is_sector1_writable_reg = 0;
+        is_sector2_writable_reg = 0;
+        is_sector3_writable_reg = 0;
+        is_sector4_writable_reg = 0;
+        is_sector5_writable_reg = 0;
+    end
+    
+    // -------------------------------------------------------------------
+    // Avoid async reset removal issue 
+    // -------------------------------------------------------------------
+    always @ (negedge reset_n or posedge clock) begin
+        if (~reset_n) begin
+            {reset_n_reg2, reset_n_reg1} <= 2'b0;
+        end
+        else begin
+            {reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Sync combinational output before feeding into flash
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_sync_reg <= 0;
+        end
+        else begin
+            enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
+        end
+    end
+    
+    // -------------------------------------------------------------------
+    // Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
+    // -------------------------------------------------------------------
+    always @ (negedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_neg_reg <= 0;
+            enable_drclk_neg_reg <= 0;
+            flash_drshft_neg_reg <= 1;
+            flash_se_neg_reg <= 0;
+            write_wait_neg <= 0;
+            read_wait_neg <= 0;
+        end
+        else begin
+            enable_arclk_neg_reg <= enable_arclk_sync_reg;
+            enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
+            flash_drshft_neg_reg <= flash_drshft_reg;
+            flash_se_neg_reg <= flash_se_w;
+            write_wait_neg <= write_wait;
+            read_wait_neg <= read_wait;
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Get rid of glitch for pos clock
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_neg_pos_reg <= 0;
+        end
+        else begin
+            enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Pine line page address path
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            flash_page_addr <= 0;
+        end
+        else begin
+            flash_page_addr <= flash_page_addr_wire;
+        end
+    end
+
+    generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
+        if (READ_AND_WRITE_MODE == 1) begin
+            // -------------------------------------------------------------------
+            // Pine line sector address path
+            // -------------------------------------------------------------------
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    flash_sector_addr <= 0;
+                end
+                else begin
+                    flash_sector_addr <= flash_sector_wire;
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Minitor flash pass signal and update CSR busy status
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    flash_se_pass_reg <= 0;
+                    flash_sp_pass_reg <= 0;
+                    csr_status_busy <= STATUS_IDLE;
+                end
+                else begin
+                    flash_se_pass_reg <= flash_se_pass;
+                    flash_sp_pass_reg <= flash_sp_pass;
+                    
+                    if (is_erase_busy) begin
+                        csr_status_busy <= STATUS_BUSY_ERASE;
+                    end
+                    else if (is_write_busy) begin
+                        csr_status_busy <= STATUS_BUSY_WRITE;
+                    end
+                    else if (is_read_busy) begin
+                        csr_status_busy <= STATUS_BUSY_READ;
+                    end
+                    else begin
+                        csr_status_busy <= STATUS_IDLE;
+                    end
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Monitor and store flash busy signal, it may faster then the clock
+            // -------------------------------------------------------------------
+            wire busy_scan;
+            assign busy_scan = (erase_busy_scan || write_busy_scan);
+            always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
+                if (~reset_n || ~busy_scan) begin
+                    flash_busy_reg <= 0;
+                    flash_busy_clear_reg <= 0;
+                end
+                else if (flash_busy_reg) begin
+                    flash_busy_reg <= flash_busy_reg;
+                    flash_busy_clear_reg <= ~flash_busy;
+                end
+                else begin
+                    flash_busy_reg <= flash_busy;
+                    flash_busy_clear_reg <= 0;
+                end
+            end
+
+            altera_std_synchronizer #(
+                .depth (2)
+            ) stdsync_busy ( 
+                .clk(clock), // clock
+                .din(flash_busy_reg), // busy signal
+                .dout(flash_busy_sync), // busy signal which reg to clock
+                .reset_n(reset_n) // active low reset
+            );
+
+            altera_std_synchronizer #(
+                .depth (2)
+            ) stdsync_busy_clear ( 
+                .clk(clock), // clock
+                .din(flash_busy_clear_reg), // busy signal
+                .dout(flash_busy_clear_sync), // busy signal which reg to clock
+                .reset_n(reset_n) // active low reset
+            );
+            
+            // -------------------------------------------------------------------
+            // Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
+            // -------------------------------------------------------------------
+            always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_drdin_neg_reg <= 1;
+                end
+                else begin
+                    flash_drdin_neg_reg <= flash_drdin_w;
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    write_state <= WRITE_STATE_IDLE;
+                    write_wait <= 0;
+                end
+                else begin
+                    case (write_state)
+                        WRITE_STATE_IDLE: begin
+                            // reset all register
+                            write_count <= 0;
+                            write_timeout <= 1'b0;
+                            write_busy_scan <= 1'b0;
+                            enable_drclk_neg_pos_write_reg <= 0;
+                            
+                            // check command
+                            if (avmm_write) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
+                                    write_state <= WRITE_STATE_ADDR;
+                                    write_wait <= 1;
+                                end
+                            end
+                        end
+                        
+                        WRITE_STATE_ADDR: begin
+                            if (is_addr_writable && is_valid_write_burst_count) begin
+                                write_count <= DATA_WIDTH[5:0];
+                                write_state <= WRITE_STATE_WRITE;
+                            end
+                            else begin
+                                write_wait <= 0;
+                                write_count <= 2;
+                                write_state <= WRITE_STATE_ERROR;
+                            end
+                        end
+
+                        WRITE_STATE_WRITE: begin
+                            if (write_count != 0) begin
+                                write_drclk_en <= 1;
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                enable_drclk_neg_pos_write_reg <= 1;
+                                write_drclk_en <= 0;
+                                write_busy_scan <= 1'b1;
+                                write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_WAIT_BUSY;
+                            end
+                        end                
+
+                        WRITE_STATE_WAIT_BUSY: begin
+                            if (flash_busy_sync) begin
+                                write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_WAIT_DONE;
+                            end
+                            else begin
+                                if (write_count != 0)
+                                    write_count <= write_count - 16'd1;
+                                else begin
+                                    write_timeout <= 1'b1;
+                                    write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                    write_state <= WRITE_STATE_RESET;
+                                end
+                            end
+                        end
+                        
+                        WRITE_STATE_WAIT_DONE: begin
+                            if (flash_busy_clear_sync) begin
+                                write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_RESET;
+                            end
+                            else begin
+                                if (write_count != 0) begin
+                                    write_count <= write_count - 16'd1;
+                                end
+                                else begin
+                                    write_timeout <= 1'b1;
+                                    write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                    write_state <= WRITE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        WRITE_STATE_RESET: begin
+                            write_busy_scan <= 1'b0;
+                            if (write_timeout) begin
+                                csr_status_w_pass <= 1'b0;
+                            end
+                            else begin
+                                csr_status_w_pass <= flash_sp_pass_reg;
+                            end
+                            if (write_count == 1) begin
+                                write_wait <= 0;
+                            end
+                            if (write_count != 0) begin
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                write_state <= WRITE_STATE_IDLE;
+                            end
+                        end
+                        
+                        WRITE_STATE_ERROR: begin
+                            csr_status_w_pass <= 1'b0;
+                            if (write_count == 1) begin
+                                write_wait <= 0;
+                            end
+                            if (write_count != 0) begin
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                write_state <= WRITE_STATE_IDLE;
+                            end
+                        end
+                        
+                        default: begin
+                            write_state <= WRITE_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end    
+
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    erase_state <= ERASE_STATE_IDLE;
+                end
+                else begin
+                    case (erase_state)
+
+                        ERASE_STATE_IDLE: begin
+                            // reset all register
+                            erase_count <= 0;
+                            erase_timeout <= 1'b0;
+                            erase_busy_scan <= 1'b0;
+                            
+                            // check command
+                            if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
+                                erase_state <= ERASE_STATE_ADDR;
+                            end
+                        end
+
+                        ERASE_STATE_ADDR: begin
+                            if (is_erase_addr_writable) begin
+                                erase_busy_scan <= 1'b1;
+                                erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_WAIT_BUSY;
+                            end
+                            else begin
+                                erase_count <= 2;
+                                erase_state <= ERASE_STATE_ERROR;
+                            end
+                        end
+                        
+                        ERASE_STATE_WAIT_BUSY: begin
+                            if (flash_busy_sync) begin
+                                erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_WAIT_DONE;
+                            end
+                            else begin
+                                if (erase_count != 0)
+                                    erase_count <= erase_count - 26'd1;
+                                else begin
+                                    erase_timeout <= 1'b1;
+                                    erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                    erase_state <= ERASE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        ERASE_STATE_WAIT_DONE: begin
+                            if (flash_busy_clear_sync) begin
+                                erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_RESET;
+                            end
+                            else begin
+                                if (erase_count != 0) begin
+                                    erase_count <= erase_count - 26'd1;
+                                end
+                                else begin
+                                    erase_timeout <= 1'b1;
+                                    erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                    erase_state <= ERASE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        ERASE_STATE_RESET: begin
+                            erase_busy_scan <= 1'b0;
+                            if (erase_timeout) begin
+                                csr_status_e_pass <= 1'b0;
+                            end
+                            else begin
+                                csr_status_e_pass <= flash_se_pass_reg;
+                            end
+                            if (erase_count != 0) begin
+                                erase_count <= erase_count - 26'd1;
+                            end
+                            else begin
+                                erase_state <= ERASE_STATE_IDLE;
+                            end
+                        end
+
+                        ERASE_STATE_ERROR: begin
+                            csr_status_e_pass <= 1'b0;
+                            if (erase_count != 0) begin
+                                erase_count <= erase_count - 26'd1;
+                            end
+                            else begin
+                                erase_state <= ERASE_STATE_IDLE;
+                            end
+                        end
+                        
+                        default: begin
+                            erase_state <= ERASE_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end
+        end
+    endgenerate
+    
+    generate // generate always block for read operation based on read burst mode.
+        if (WRAPPING_BURST_MODE == 0) begin
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    read_state <= READ_STATE_IDLE;
+                    read_wait <= 0;
+                end
+                else begin
+                    case (read_state)
+
+                        READ_STATE_IDLE: begin
+                            // reset all register
+                            avmm_read_state <= READ_SETUP;
+                            avmm_readdata_ready <= 0;
+                            flash_ardin_align_reg <= 0;
+                            read_ctrl_count <= 0;
+                            avmm_burstcount_input_reg <= 0;
+                            enable_drclk_neg_pos_reg <= 0;
+                            read_drclk_en <= 0;
+                            flash_drshft_reg <= 1;
+                            
+                            // check command
+                            if (avmm_read) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
+                                    read_wait <= 1;
+                                    read_state <= READ_STATE_ADDR;
+                                    flash_seq_read_ardin <= avmm_addr;
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                end
+                            end
+                        end
+
+                        READ_STATE_ADDR: begin
+                            if (is_addr_within_valid_range) begin
+                                csr_status_r_pass <= 1;
+                            end
+                            else begin
+                                csr_status_r_pass <= 0;
+                            end
+                        
+                            read_wait <= 0;
+                            read_state <= READ_STATE_PULSE_SE;
+                        end
+                        READ_STATE_PULSE_SE: begin
+                             read_wait <= 1;
+              		     read_state <= READ_STATE_SETUP;
+                        end
+
+                        // incrementing read
+                        READ_STATE_SETUP: begin
+                            if (next_flash_read_ardin > MAX_VALID_ADDR) begin
+                                flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
+                            end
+                            else begin
+                                flash_seq_read_ardin <= next_flash_read_ardin;
+                            end
+                            flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
+                            if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
+                                read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
+                                read_state <= READ_STATE_DUMMY;
+                            end
+                            else begin
+                                read_state <= READ_STATE_READY;
+                            end
+                        end
+
+                        READ_STATE_DUMMY: begin
+                            if (read_ctrl_count > 1) begin
+                                read_ctrl_count <= read_ctrl_count - 3'd1;
+                            end
+                            else begin
+                                read_state <= READ_STATE_READY;
+                            end
+                        end
+
+                        READ_STATE_READY: begin
+                            if (avmm_read_state == READ_SETUP) begin
+                                avmm_readdata_ready <= 1;
+                            end
+                            read_drclk_en <= 1;
+                            flash_drshft_reg <= 0;
+                            read_state <= READ_STATE_FINAL;
+                        end
+                        
+                        READ_STATE_FINAL: begin
+                            flash_drshft_reg <= 1;
+                            avmm_readdata_ready <= 0;
+                            avmm_read_state <= READ_RECV_DATA;
+
+                            if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
+                                read_state <= READ_STATE_CLEAR;
+                                read_drclk_en <= 0;
+                                enable_drclk_neg_pos_reg <= 1;
+                            end
+                            else begin
+                                read_state <= READ_STATE_PULSE_SE;
+                            end
+                        end
+
+                        // Dummy state to clear arclk glitch
+                        READ_STATE_CLEAR: begin
+                            read_wait <= 0;
+                            read_state <= READ_STATE_IDLE;
+                        end
+
+                        default: begin
+                            read_state <= READ_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end    
+        end
+        else begin
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    read_state <= READ_STATE_IDLE;
+                    read_wait <= 0;
+                end
+                else begin
+                    case (read_state)
+
+                        READ_STATE_IDLE: begin
+                            // reset all register
+                            avmm_readdata_ready <= 0;
+                            flash_ardin_align_reg <= 0;
+                            read_ctrl_count <= 0;
+                            enable_drclk_neg_pos_reg <= 0;
+                            flash_drshft_reg <= 1;
+                            read_drclk_en <= 0;
+                            avmm_burstcount_input_reg <= 0;
+                            
+                            // check command
+                            if (avmm_read) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
+                                    read_wait <= 1;
+                                    read_state <= READ_STATE_ADDR;
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                    
+                                end
+                            end
+                        end
+
+                        READ_STATE_ADDR: begin
+                              read_wait <= 0;
+                            if (is_addr_within_valid_range) begin
+                                csr_status_r_pass <= 1;
+                            end
+                            else begin
+                                csr_status_r_pass <= 0;
+                            end
+                        
+                            read_state <= READ_STATE_PULSE_SE;
+                            read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
+                        end
+                        READ_STATE_PULSE_SE: begin
+                             read_wait <= 1;
+              		     read_state <= READ_STATE_READ;
+                        end
+                        
+                        // wrapping read
+                        READ_STATE_READ: begin
+                            
+                            // read control signal
+                            if (read_ctrl_count > 0) begin
+                                read_ctrl_count <= read_ctrl_count - 3'd1;
+                            end
+                            if (read_ctrl_count == 2) begin
+                                avmm_readdata_ready <= 1;
+                                read_drclk_en <= 1;
+                                flash_drshft_reg <= 0;
+                            end
+                            else begin
+                                flash_drshft_reg <= 1;
+                            end
+                            if (avmm_read && ~read_wait) begin
+                                read_wait <= 1;
+                            end
+                            if (avmm_readdata_ready || read_ctrl_count == 0) begin
+                                avmm_readdata_ready <= 0;
+                                if (avmm_read) begin
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                    read_state <= READ_STATE_ADDR;
+                                end
+                            end
+                            
+                            // read data signal
+                            if (read_count > 0) begin
+                                read_count <= read_count - 3'd1;
+                            end
+                            else begin
+                                if (avmm_readdata_ready) begin
+                                    read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
+                                end
+                            end
+                            
+                            // back to idle if both control and read cycle are finished
+                            if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
+                                read_state <= READ_STATE_IDLE;
+                                read_drclk_en <= 0;
+                                read_wait <= 0;
+                                enable_drclk_neg_pos_reg <= 1;
+                            end
+                            
+                        end
+
+                        default: begin
+                            read_state <= READ_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end
+        end
+    endgenerate
+
+    generate // generate readdatavalid control signal always block based on read burst mode.
+        if (WRAPPING_BURST_MODE == 0) begin
+            // -------------------------------------------------------------------
+            // Control readdatavalid signal - incrementing read
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    avmm_read_valid_state <= READ_VALID_IDLE;
+                    avmm_burstcount_reg <= 0;
+                    avmm_readdatavalid_reg <= 0;
+                    flash_ardin_align_backup_reg <= 0;
+                    data_count <= 0;
+                end
+                else begin
+                    case (avmm_read_valid_state)
+                        READ_VALID_IDLE: begin
+                            if (avmm_readdata_ready) begin
+                                data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
+                                avmm_read_valid_state <= READ_VALID_PRE_READING;
+                                avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                flash_ardin_align_backup_reg <= flash_ardin_align_reg;
+                            end
+                        end
+                        READ_VALID_PRE_READING: begin
+                            avmm_readdatavalid_reg <= 1;
+                            avmm_read_valid_state <= READ_VALID_READING;
+                        end
+                        READ_VALID_READING: begin
+
+                            if (avmm_burstcount_reg == 0) begin
+                                avmm_read_valid_state <= READ_VALID_IDLE;
+                                avmm_readdatavalid_reg <= 0;
+                            end
+                            else begin
+                                if (data_count > 0) begin
+                                    if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
+                                        avmm_readdatavalid_reg <= 1;
+                                        avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                    end
+                                    else begin
+                                        avmm_readdatavalid_reg <= 0;
+                                    end
+                                    data_count <= data_count - 3'd1;
+                                end
+                                else begin
+                                    flash_ardin_align_backup_reg <= 0;
+                                    data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
+                                    avmm_read_valid_state <= READ_VALID_PRE_READING;
+                                    avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                end
+                            end
+                        end
+                        
+                        default: begin
+                            avmm_read_valid_state <= READ_VALID_IDLE;
+                            avmm_burstcount_reg <= 0;
+                            avmm_readdatavalid_reg <= 0;
+                            flash_ardin_align_backup_reg <= 0;
+                            data_count <= 0;
+                        end
+                    endcase
+                end
+            end
+        end
+        else begin
+            // -------------------------------------------------------------------
+            // Control readdatavalid signal - wrapping read with fixed burst count
+            //     Burst count
+            //         1~2 - ZB8
+            //         1~4 - all other devices
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    avmm_read_valid_state <= READ_VALID_IDLE;
+                    avmm_readdatavalid_reg <= 0;
+                end
+                else begin
+                    case (avmm_read_valid_state)
+                        READ_VALID_IDLE: begin
+                            data_count <= 0;
+                            if (avmm_readdata_ready) begin
+                                data_count <= avmm_burstcount_input_reg - 3'd1;
+                                avmm_read_valid_state <= READ_VALID_PRE_READING;
+                            end
+                        end
+                        READ_VALID_PRE_READING: begin
+                            avmm_readdatavalid_reg <= 1;
+                            avmm_read_valid_state <= READ_VALID_READING;
+                        end
+                        
+                        READ_VALID_READING: begin
+                            if (data_count > 0) begin
+                                data_count <= data_count - 3'd1;
+                            end
+                            else begin
+                                if (avmm_readdata_ready) begin
+                                    data_count <= avmm_burstcount_input_reg - 3'd1;
+                                end
+                                else begin
+                                    avmm_read_valid_state <= READ_VALID_IDLE;
+                                    avmm_readdatavalid_reg <= 0;
+                                end
+                            end
+                        end
+                        
+                        default: begin
+                            avmm_read_valid_state <= READ_VALID_IDLE;
+                        end
+                    endcase
+                end
+            end
+        end
+    endgenerate
+
+    generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
+        if (READ_AND_WRITE_MODE == 1) begin
+            // -------------------------------------------------------------------
+            // Instantiate a shift register to send the data to UFM serially (load parallel)
+            // -------------------------------------------------------------------
+            lpm_shiftreg # (
+                .lpm_type ("LPM_SHIFTREG"),
+                .lpm_width (DATA_WIDTH),
+                .lpm_direction ("LEFT")
+            ) ufm_data_shiftreg (
+                .data(avmm_writedata),
+                .clock(clock),
+                .enable(write_state == WRITE_STATE_WRITE),
+                .load(write_count == DATA_WIDTH),
+                .shiftout(flash_drdin_w),
+                .aclr(write_state == WRITE_STATE_IDLE)
+            );
+        end
+    endgenerate
+
+    altera_onchip_flash_address_range_check    # (
+        .MIN_VALID_ADDR(MIN_VALID_ADDR),
+        .MAX_VALID_ADDR(MAX_VALID_ADDR)
+    ) address_range_checker (
+        .address(cur_read_addr),
+        .is_addr_within_valid_range(is_addr_within_valid_range)
+    );
+
+    altera_onchip_flash_convert_address # (
+        .ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
+        .ADDR_RANGE2_END_ADDR(ADDR_RANGE2_END_ADDR),
+        .ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
+        .ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET),
+        .ADDR_RANGE3_OFFSET(ADDR_RANGE3_OFFSET)
+    ) address_convertor (
+        .address(cur_a_addr),
+        .flash_addr(flash_page_addr_wire)
+    );
+
+    generate // sector address convertsion is unnecessary in read only mode
+        if (READ_AND_WRITE_MODE == 1) begin
+        
+            // pipe line addr legality check logic
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    is_sector1_writable_reg <= 1'b0;
+                    is_sector2_writable_reg <= 1'b0;
+                    is_sector3_writable_reg <= 1'b0;
+                    is_sector4_writable_reg <= 1'b0;
+                    is_sector5_writable_reg <= 1'b0;
+                end
+                else begin
+                    is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
+                    is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
+                    is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
+                    is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
+                    is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
+                end
+            end
+
+            altera_onchip_flash_a_address_write_protection_check # (
+                .SECTOR1_START_ADDR(SECTOR1_START_ADDR),
+                .SECTOR1_END_ADDR(SECTOR1_END_ADDR),
+                .SECTOR2_START_ADDR(SECTOR2_START_ADDR),
+                .SECTOR2_END_ADDR(SECTOR2_END_ADDR),
+                .SECTOR3_START_ADDR(SECTOR3_START_ADDR),
+                .SECTOR3_END_ADDR(SECTOR3_END_ADDR),
+                .SECTOR4_START_ADDR(SECTOR4_START_ADDR),
+                .SECTOR4_END_ADDR(SECTOR4_END_ADDR),
+                .SECTOR5_START_ADDR(SECTOR5_START_ADDR),
+                .SECTOR5_END_ADDR(SECTOR5_END_ADDR)
+            ) access_address_write_protection_checker (
+                .address(cur_a_addr),
+                .is_sector1_writable(is_sector1_writable_reg),
+                .is_sector2_writable(is_sector2_writable_reg),
+                .is_sector3_writable(is_sector3_writable_reg),
+                .is_sector4_writable(is_sector4_writable_reg),
+                .is_sector5_writable(is_sector5_writable_reg),
+                .is_addr_writable(is_addr_writable)
+            );
+        
+            altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
+                .address(cur_e_addr[2:0]),
+                .is_sector1_writable(is_sector1_writable_reg),
+                .is_sector2_writable(is_sector2_writable_reg),
+                .is_sector3_writable(is_sector3_writable_reg),
+                .is_sector4_writable(is_sector4_writable_reg),
+                .is_sector5_writable(is_sector5_writable_reg),
+                .is_addr_writable(is_sector_writable)
+            );
+            
+            altera_onchip_flash_convert_sector # (
+                .SECTOR1_MAP(SECTOR1_MAP),
+                .SECTOR2_MAP(SECTOR2_MAP),
+                .SECTOR3_MAP(SECTOR3_MAP),
+                .SECTOR4_MAP(SECTOR4_MAP),
+                .SECTOR5_MAP(SECTOR5_MAP)
+            ) sector_convertor (
+                .sector(cur_e_addr[2:0]),
+                .flash_sector(flash_sector_wire)
+            );
+        end
+    endgenerate
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_util.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_util.v
new file mode 100644
index 0000000..3a81c50
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_onchip_flash_util.v
@@ -0,0 +1,270 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_UTIL
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_address_range_check (
+    address,
+    is_addr_within_valid_range
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter MIN_VALID_ADDR = 1;
+    parameter MAX_VALID_ADDR = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    output is_addr_within_valid_range;
+    
+    assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
+
+endmodule
+
+
+module altera_onchip_flash_address_write_protection_check (
+    use_sector_addr,
+    address,
+    write_protection_mode,
+    is_addr_writable
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+    parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+
+    input use_sector_addr;
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    input [4:0] write_protection_mode;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;    
+    wire is_sector1_writable;
+    wire is_sector2_writable;
+    wire is_sector3_writable;
+    wire is_sector4_writable;
+    wire is_sector5_writable;
+    
+    assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
+    assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
+    assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
+    assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
+    assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
+    assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
+    assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
+    assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
+    assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
+    assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_s_address_write_protection_check (
+    address,
+    is_sector1_writable,
+    is_sector2_writable,
+    is_sector3_writable,
+    is_sector4_writable,
+    is_sector5_writable,
+    is_addr_writable
+);
+
+    input [2:0] address;
+    input is_sector1_writable;
+    input is_sector2_writable;
+    input is_sector3_writable;
+    input is_sector4_writable;
+    input is_sector5_writable;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;
+
+    assign is_sector1_addr = (address == 1);
+    assign is_sector2_addr = (address == 2);
+    assign is_sector3_addr = (address == 3);
+    assign is_sector4_addr = (address == 4);
+    assign is_sector5_addr = (address == 5);
+
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_a_address_write_protection_check (
+    address,
+    is_sector1_writable,
+    is_sector2_writable,
+    is_sector3_writable,
+    is_sector4_writable,
+    is_sector5_writable,
+    is_addr_writable
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    input is_sector1_writable;
+    input is_sector2_writable;
+    input is_sector3_writable;
+    input is_sector4_writable;
+    input is_sector5_writable;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;
+
+    assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
+    assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
+    assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
+    assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
+    assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
+
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_convert_address (
+    address,
+    flash_addr
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter ADDR_RANGE1_END_ADDR = 1;
+    parameter ADDR_RANGE2_END_ADDR = 1;
+    parameter ADDR_RANGE1_OFFSET = 1;
+    parameter ADDR_RANGE2_OFFSET = 1;
+    parameter ADDR_RANGE3_OFFSET = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    output [FLASH_ADDR_WIDTH-1:0] flash_addr;
+
+    assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) : 
+                        (address <= ADDR_RANGE2_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
+                        (address + ADDR_RANGE3_OFFSET[FLASH_ADDR_WIDTH-1:0]);
+    
+endmodule
+
+
+module altera_onchip_flash_convert_sector (
+    sector,
+    flash_sector
+);
+
+    parameter SECTOR1_MAP = 1;
+    parameter SECTOR2_MAP = 1;
+    parameter SECTOR3_MAP = 1;
+    parameter SECTOR4_MAP = 1;
+    parameter SECTOR5_MAP = 1;
+
+    input [2:0] sector;
+    output [2:0] flash_sector;
+
+    assign flash_sector = 
+        (sector == 1) ? SECTOR1_MAP[2:0] :
+        (sector == 2) ? SECTOR2_MAP[2:0] :
+        (sector == 3) ? SECTOR3_MAP[2:0] :
+        (sector == 4) ? SECTOR4_MAP[2:0] :
+        (sector == 5) ? SECTOR5_MAP[2:0] :
+        3'd0; // Set to 0 for invalid sector ID
+
+endmodule
+
+
+module altera_onchip_flash_counter (
+    clock,
+    reset,
+    count
+);
+    input clock;
+    input reset;
+    output [4:0] count;
+    
+    reg [4:0] count_reg;
+    
+    assign count = count_reg;
+
+    initial begin
+        count_reg = 0;
+    end
+    
+    always @ (posedge reset or posedge clock) begin
+        if (reset) begin
+            count_reg <= 0;
+        end
+        else begin
+            count_reg <= count_reg + 5'd1;
+        end
+    end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.sdc b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.sdc
new file mode 100644
index 0000000..3a7710f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.sdc
@@ -0,0 +1,30 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set aclr_counter 0
+set clrn_counter 0
+set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+set aclr_counter [get_collection_size $aclr_collection]
+set clrn_counter [get_collection_size $clrn_collection]
+
+if {$aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+}
+
+if {$clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+}
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.v
new file mode 100644
index 0000000..bee20fd
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_controller.v
@@ -0,0 +1,319 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// ACDS13.1 - Added reset request as part of reset sequencing
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+    parameter NUM_RESET_INPUTS              = 6,
+    parameter USE_RESET_REQUEST_IN0 = 0,
+    parameter USE_RESET_REQUEST_IN1 = 0,
+    parameter USE_RESET_REQUEST_IN2 = 0,
+    parameter USE_RESET_REQUEST_IN3 = 0,
+    parameter USE_RESET_REQUEST_IN4 = 0,
+    parameter USE_RESET_REQUEST_IN5 = 0,
+    parameter USE_RESET_REQUEST_IN6 = 0,
+    parameter USE_RESET_REQUEST_IN7 = 0,
+    parameter USE_RESET_REQUEST_IN8 = 0,
+    parameter USE_RESET_REQUEST_IN9 = 0,
+    parameter USE_RESET_REQUEST_IN10 = 0,
+    parameter USE_RESET_REQUEST_IN11 = 0,
+    parameter USE_RESET_REQUEST_IN12 = 0,
+    parameter USE_RESET_REQUEST_IN13 = 0,
+    parameter USE_RESET_REQUEST_IN14 = 0,
+    parameter USE_RESET_REQUEST_IN15 = 0,
+    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
+    parameter SYNC_DEPTH                    = 2,
+    parameter RESET_REQUEST_PRESENT         = 0,
+    parameter RESET_REQ_WAIT_TIME           = 3,
+    parameter MIN_RST_ASSERTION_TIME        = 11,
+    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
+    parameter ADAPT_RESET_REQUEST          = 0
+)
+(
+    // --------------------------------------
+    // We support up to 16 reset inputs, for now
+    // --------------------------------------
+    input reset_in0,
+    input reset_in1,
+    input reset_in2,
+    input reset_in3,
+    input reset_in4,
+    input reset_in5,
+    input reset_in6,
+    input reset_in7,
+    input reset_in8,
+    input reset_in9,
+    input reset_in10,
+    input reset_in11,
+    input reset_in12,
+    input reset_in13,
+    input reset_in14,
+    input reset_in15,
+    input reset_req_in0,
+    input reset_req_in1,
+    input reset_req_in2,
+    input reset_req_in3,
+    input reset_req_in4,
+    input reset_req_in5,
+    input reset_req_in6,
+    input reset_req_in7,
+    input reset_req_in8,
+    input reset_req_in9,
+    input reset_req_in10,
+    input reset_req_in11,
+    input reset_req_in12,
+    input reset_req_in13,
+    input reset_req_in14,
+    input reset_req_in15,
+
+
+    input  clk,
+    output reg reset_out,
+    output reg reset_req
+);
+
+   // Always use async reset synchronizer if reset_req is used
+   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+   // --------------------------------------
+   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
+   // --------------------------------------
+   localparam MIN_METASTABLE = 3;
+   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
+
+   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
+
+   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
+                                            MIN_RST_ASSERTION_TIME + 1 :
+                                        (
+                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
+                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
+                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
+                                        );
+
+   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
+   // --------------------------------------
+
+   wire merged_reset;
+   wire merged_reset_req_in;
+   wire reset_out_pre;
+   wire reset_req_pre;
+
+   // Registers and Interconnect
+   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
+   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
+   reg                                          r_sync_rst;
+   reg                                          r_early_rst;
+
+    // --------------------------------------
+    // "Or" all the input resets together
+    // --------------------------------------
+    assign merged_reset = (  
+                              reset_in0 | 
+                              reset_in1 | 
+                              reset_in2 | 
+                              reset_in3 | 
+                              reset_in4 | 
+                              reset_in5 | 
+                              reset_in6 | 
+                              reset_in7 | 
+                              reset_in8 | 
+                              reset_in9 | 
+                              reset_in10 | 
+                              reset_in11 | 
+                              reset_in12 | 
+                              reset_in13 | 
+                              reset_in14 | 
+                              reset_in15
+                          );
+
+    assign merged_reset_req_in = (
+                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
+                            );
+
+
+    // --------------------------------------
+    // And if required, synchronize it to the required clock domain,
+    // with the correct synchronization type
+    // --------------------------------------
+    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
+
+        assign reset_out_pre = merged_reset;
+        assign reset_req_pre = merged_reset_req_in;
+
+    end else begin
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
+        )
+        alt_rst_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset),
+            .reset_out  (reset_out_pre)
+        );
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_req_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset_req_in),
+            .reset_out  (reset_req_pre)
+        );
+
+    end
+    endgenerate
+
+    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
+                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
+        always @* begin
+            reset_out = reset_out_pre;
+            reset_req = reset_req_pre;
+        end
+    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
+
+        wire reset_out_pre2;
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH+1),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_sync_uq2
+        (
+            .clk        (clk),
+            .reset_in   (reset_out_pre),
+            .reset_out  (reset_out_pre2)
+        );
+
+        always @* begin
+            reset_out = reset_out_pre2;
+            reset_req = reset_req_pre;
+        end
+
+    end
+    else begin
+
+    // 3-FF Metastability Synchronizer
+    initial
+    begin
+        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
+            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
+    end
+
+    // Synchronous reset pipe
+    initial
+    begin
+        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
+        begin
+            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+    else
+    begin
+        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
+    end
+    end
+
+    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
+    // matches the early input.
+
+    always @(posedge clk)
+    begin
+        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
+            3'b000:   r_sync_rst <= 1'b0; // Not reset
+            3'b001:   r_sync_rst <= 1'b0;
+            3'b010:   r_sync_rst <= 1'b0;
+            3'b011:   r_sync_rst <= 1'b1;
+            3'b100:   r_sync_rst <= 1'b1; 
+            3'b101:   r_sync_rst <= 1'b1;
+            3'b110:   r_sync_rst <= 1'b1;
+            3'b111:   r_sync_rst <= 1'b1; // In Reset
+            default:  r_sync_rst <= 1'b1;
+        endcase
+
+        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
+            2'b00:   r_early_rst <= 1'b0; // Not reset
+            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
+            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
+            2'b11:   r_early_rst <= 1'b1; // Held in reset
+            default: r_early_rst <= 1'b1;
+        endcase
+    end
+
+    always @* begin
+        reset_out = r_sync_rst;
+        reset_req = r_early_rst;
+    end
+
+    end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_synchronizer.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_synchronizer.v
new file mode 100644
index 0000000..01613ec
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_reset_synchronizer.v
@@ -0,0 +1,87 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+    reg altera_reset_synchronizer_int_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+                altera_reset_synchronizer_int_chain_out <= 1'b1;
+            end
+            else begin
+                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+            end
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v
new file mode 100644
index 0000000..1521f77
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v
@@ -0,0 +1,195 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
+// $Revision: #8 $
+// $Date: 2009/02/18 $
+// $Author: pscheidt $
+//-----------------------------------------------------------------------------
+//
+// File: altera_std_synchronizer_nocut.v
+//
+// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
+//           as altera_std_synchronizer.v, except that the embedded false
+//           path constraint is removed in this module. If you use this
+//           module, you will have to apply the appropriate timing
+//           constraints.
+//
+//           We expect to make this a standard Quartus atom eventually.
+//
+//           Composed of two or more flip flops connected in series.
+//           Random metastable condition is simulated when the 
+//           __ALTERA_STD__METASTABLE_SIM macro is defined.
+//           Use +define+__ALTERA_STD__METASTABLE_SIM argument 
+//           on the Verilog simulator compiler command line to 
+//           enable this mode. In addition, define the macro
+//           __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output 
+//           with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+//-----------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_std_synchronizer_nocut (
+                                clk, 
+                                reset_n, 
+                                din, 
+                                dout
+                                );
+
+   parameter depth = 3; // This value must be >= 2 !
+   parameter rst_value = 0;     
+     
+   input   clk;
+   input   reset_n;    
+   input   din;
+   output  dout;
+   
+   // QuartusII synthesis directives:
+   //     1. Preserve all registers ie. do not touch them.
+   //     2. Do not merge other flip-flops with synchronizer flip-flops.
+   // QuartusII TimeQuest directives:
+   //     1. Identify all flip-flops in this module as members of the synchronizer 
+   //        to enable automatic metastability MTBF analysis.
+
+   (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON  "} *) reg din_s1;
+
+   (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;    
+   
+   //synthesis translate_off
+   initial begin
+      if (depth <2) begin
+         $display("%m: Error: synchronizer length: %0d less than 2.", depth);
+      end
+   end
+
+   // the first synchronizer register is either a simple D flop for synthesis
+   // and non-metastable simulation or a D flop with a method to inject random
+   // metastable events resulting in random delay of [0,1] cycles
+   
+`ifdef __ALTERA_STD__METASTABLE_SIM
+
+   reg[31:0]  RANDOM_SEED = 123456;      
+   wire  next_din_s1;
+   wire  dout;
+   reg   din_last;
+   reg          random;
+   event metastable_event; // hook for debug monitoring
+
+   initial begin
+      $display("%m: Info: Metastable event injection simulation mode enabled");
+   end
+   
+   always @(posedge clk) begin
+      if (reset_n == 0)
+        random <= $random(RANDOM_SEED);
+      else
+        random <= $random;
+   end
+
+   assign next_din_s1 = (din_last ^ din) ? random : din;   
+
+   always @(posedge clk or negedge reset_n) begin
+       if (reset_n == 0) 
+         din_last <= (rst_value == 0)? 1'b0 : 1'b1;
+       else
+         din_last <= din;
+   end
+
+   always @(posedge clk or negedge reset_n) begin
+       if (reset_n == 0) 
+         din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
+       else
+         din_s1 <= next_din_s1;
+   end
+   
+`else 
+
+   //synthesis translate_on   
+   generate if (rst_value == 0)
+       always @(posedge clk or negedge reset_n) begin
+           if (reset_n == 0) 
+             din_s1 <= 1'b0;
+           else
+             din_s1 <= din;
+       end
+   endgenerate
+   
+   generate if (rst_value == 1)
+       always @(posedge clk or negedge reset_n) begin
+           if (reset_n == 0) 
+             din_s1 <= 1'b1;
+           else
+             din_s1 <= din;
+       end
+   endgenerate
+   //synthesis translate_off      
+
+`endif
+
+`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
+   always @(*) begin
+      if (reset_n && (din_last != din) && (random != din)) begin
+         $display("%m: Verbose Info: metastable event @ time %t", $time);
+         ->metastable_event;
+      end
+   end      
+`endif
+
+   //synthesis translate_on
+
+   // the remaining synchronizer registers form a simple shift register
+   // of length depth-1
+   generate if (rst_value == 0)
+      if (depth < 3) begin
+         always @(posedge clk or negedge reset_n) begin
+            if (reset_n == 0) 
+              dreg <= {depth-1{1'b0}};            
+            else
+              dreg <= din_s1;
+         end         
+      end else begin
+         always @(posedge clk or negedge reset_n) begin
+            if (reset_n == 0) 
+              dreg <= {depth-1{1'b0}};
+            else
+              dreg <= {dreg[depth-3:0], din_s1};
+         end
+      end
+   endgenerate
+   
+   generate if (rst_value == 1)
+      if (depth < 3) begin
+         always @(posedge clk or negedge reset_n) begin
+            if (reset_n == 0) 
+              dreg <= {depth-1{1'b1}};            
+            else
+              dreg <= din_s1;
+         end         
+      end else begin
+         always @(posedge clk or negedge reset_n) begin
+            if (reset_n == 0) 
+              dreg <= {depth-1{1'b1}};
+            else
+              dreg <= {dreg[depth-3:0], din_s1};
+         end
+      end
+   endgenerate
+
+   assign dout = dreg[depth-2];
+   
+endmodule 
+
+
+                        
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_13.v
new file mode 100644
index 0000000000000000000000000000000000000000..cc235b16b7e63d7a1dbee737f3075a0ce57a6655
GIT binary patch
literal 8480
zcmV+*A>ZDM6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkF4ML9#_z8~Ux!GK-K5W|r7H6P`
zQz&Qz(``bh)7B4VnAiaHFiCOX2|!&Z{bbtiYW9c&jCB}~)W)E*{D|_CykO@rD|16F
zQ&N=raJ4;p@^f#vmLlHn$X__6IDo$M=vMW&*;JS!VCwsH{Bdt1Qf-ioQ34;TjL0Jd
ztA6k3dAEfWbq7Yf18>*{_a+Ll^MKEGn>OoVvt=UWI19BUy%}1rWC^!}#^i;zIfjje
zl`S)zw)UMUIcF^Ps3mp8;v~qzkzRnR<TdAU=rN4+>@b{MR<dKMPTP1xaT29;srH)@
zi2lXdibLEu!Gd57W<bF!kKW3+KjgTz_i|p}^&3@)URX3!hagRjSIK}l=X2;pIPKu9
zZ0)8!`0h<SFij2#xlm6AZsxl`NQJjG1wYF6Fn)SbZAuQ#MgyoF7B4pNNj^E9QV3|{
zNbv!uDxIjZG>~l>)R)$S=U9BZPP-^dW1n01-&K=AGfJ`T42=vYp#}NeU((*;)X|B@
zX(v(+JF9SwQvI^e1E3zrGmL6DFF@92J!;W-tUOQJ&4Q69)Vw}T(~o>PYix(d+#L^L
z!8uiS$b~JfNoh$4d>to4DmLZ86&;S>5q!+=y~==z=1BZZF1haDZh@Q3az(l~$s|r7
zO>}K962L4%MVp<^7QhR??^GQlj1yi?4cZ=fC{Z84{Nv{f!WbSW;vRq?)h3y^h44_M
z&H5hOl(B9cdv5X|3Gl%>mv38~7^S@6^pr@35FK0B7H$vwX4)DMhCm?R=W6s>gLQ@~
zz&{DH>aHA;Nhi5Fe{ChyD5dH!4P||331uO~%xxVO01sFHw;6(hVuLN4A@-{2s6L}g
z6^csM3|&C^){R)<v+0M|(Sgi0h|)AMA)P+_Ii?<tm<)auPwZBY9`sGj^WBY0kFy8x
zVSS%PW>?BD0)ywcQ#Xon8$*G5q{rioO)*oGDG?ZB369oiU2*CmsB#6alS%VzXM)AZ
z>+G4=beLf4UD8~~+NoF%dhr3M2v>fFi;J#|#_>a|#eacpejyNwulP@97c!?*_^KlS
zVjbTBf2UR)LXgFJc}@D1F!u`?1G#o>djC0K%8N1~1<3SVqx`s({5By33byi6z`J!6
z64~;XZ^}7kgD=xr4??X}Nbe344Num}S-3TK4@QDN7pXnjYaC3tZmqLk+o2OjN!YAV
zgGM#x4ASW2AJyG(Nse``uf;e7QTQ0)LowXvB%P0y8%LA|Ch~ZbKru5vg%v-T4QY0+
zf?*9~2FbP5NlKgpG_SGY#-xRmaT74$%46obMEF?L?r6^dY_!JW+32s0%c#fXnTix^
zM|^eIl9Bfnm@F<e(m6t}s2Rdq{=&R_Q<c?pM`B{h=G9<keHk4&eP9meY@wBXJ>6s<
zqG`WxZx4^U!|zGhZ$Sj6%(5T<$bK)SLfg(q+<I@}vF@+C&1Z{IU7rMj#y9w98mZyk
zL>-N7KZxw`-^7CS$RAJuI_&(vfeSO5Z+BQ2GYp?Lzz$HTsLq~ux0&{8R+8KFi}l+O
zr7$T>G)6S=mE(4j2izi+E}ueWXt?2`X5_&$$>O|ypD!#yI+3h-l4rF*jG)SX%%*U0
z@c)>8Q-)ehL+c7GU^4n4z`zSl$4C7S0LeRYCJ~^WZ`b1~2%_l+C;~Z12hvy$4nnk&
z;Ede~R*iwx%|vdus3~LYnnR3fI?CS+oy`BHx0D)?E3hx>)5634Aky<hSll`8$Y>Vy
zKb<0f_U`CgzfZmZ84n>{O3v>d65X$L-nkQ!)6rWUIL%f23Rg`Idaj2jTluJDx@=T;
z_%U~HowE+kYTgMmTmf2Cjt7AGc#_nYG@1-`TIOhZ03VpfJP`98u444G*LRNt__u;V
zagh*Kh2<v>aw5Ks4_1i-3z-F;7&5+4O&hK`tiwU3ZSv&mU%5!B&awHKV<AXE;YmR4
zaBY%>PRSfPOL!%=R}JH`?ghgTtAC}BONam`pTwAikFEn(Ztq(hp@8VV@sv?>@~8D<
zn&?5rJGf=udNK4;BppF!TY4#|(@d<d*n`|276>@YZC}EWTeP@-w+z_H5%a^no!ir>
z*TJq6A<dcbGCWp>x!&=WqABBu9#LTbqqH~BwX09V;mW=%uQ_V9+_}<cHm%xY0%DIA
z<VL3vZ~=Wfn=!~nXcKZGy6p{jp_lePz`v30b;5_JZn5qJ*ib^eow5cufh(fLoBwM1
zSe+df?c9MCW&ckQ3!F$tJuZKDQMehj$8jNvikr||n2lLKo)Tl-RnDbt@M7C^VEF|_
z7^c4x{-3@#bMTS62Lulm>Y9`vP0BpA`7PyqH=U`304J6~8|u&^$T6g?YBY*mrP|#5
z@CMQn;mT;nuHRN>10BR<$%;w{%rF3q2%m|fW1c%0XoD*a6D%g`smL{z;*-Kbm=e0{
zy&NUDsx6*YF?Y5Pr+`pRE+#W&Uzn_gyQ4LEhPY+uHdIg$TqPyu*x9W>X3(jXS#*n|
zm#_J21U3Mom;tD~<>h3;^p@uTb0KZPo8MzT;1e6%yW%yEV{rw>2iqR=tjDjCXIkBY
zOk0MtDtX`j3t%F32aNz$mwwLhQw2=DbjUv|qZZQt4bnXEhvGCj{{r02@+p^=+qDv2
z@9_&6wz+1yX@-BY#cz}2nhDR-onR9n)@=|@&3?Zp^$J?`t;#LW$^l0#Rb?6@7zO}L
z+wpe-tnN<1V-!kW{AxwmohY-d8`@wQsf0~xya~Pg>_I3%3+o76Gq@e{794n-t=$et
zoNqg7*X4a6Sqv0Bm?7{2sHEDdEn7Ung`|BITC~L5+-t=Vt3hnFh!3MEI|NcTx?xZ-
zdhbfWz2sXwEF;fZLA?SczQ7McjD;|UYX<FR2a`gX=Zt{DuInI^9+<R~q68~+zcxiY
zPMJ89*|^6#v6)GrzlFRA^m1M~ZKS<bD`qR!?|4XuF=_Q8)0fGo7jgphhh;2@!F)>P
z63cNX!1-=MFTnrX?FLv|-mo)NE1&J4j!FZ8&s_MH&oj-#;|FdO@T#;w^k;7>e`4!H
z&}}j1)++!*YS0qebWG+q?_a5#%zWtc@D={PqA7<-l7CCq2}C`lltd_7`Nlt@mCzQ3
zt1qQn>O6Q7?-i5?HVy;^+N^+NZ(dswvAk?<?Vf0UE?h~fLS2GX{ok7~<&BN_bFgH4
zNo)@8II2vBh8mX$l}@jA`@Ba=&~LvGQxB%sf{UZ5;f0;6<4L=yrO~@2!+lbW<>95e
zpo3pbkKr9K4<-X4_TQchz|$AF#e46W(5^~Fsa%|uvM@;(k#=_|+Q)w)Mj^(_a(ohg
zQ{%Jpgi~;-0}dyzc~kQ;8f;6=#T)}T%UQnciIdg&+npN$5WLwtp2T2YEhhVJSpdXH
z8~r92hcH;?(|lL;V(;@_JO5&+#Zk79zv-?;4L3c%$bp+YQtxqPjt*g#nOW)RE~~xG
z%e!Lbm)sf2q?6PzHp0oHl97ZSyf+-UqOwV`ap<?SEOyZ}RC26Ysts>R+&-x|bVt47
zU%lEl_U{7EPKe(-TQlBKCS-PGCzTc0LzazW+uTt9Ff;}=^qpul_DTxkcy=%4Xa*4A
zSSRTkv^^kK3zqZ+-jZ9S2P)o)2|Xh_0qbdq3}4SVi!WLT_e3qc2YEIg8u^C@cR6eU
z^V6IfDmY!L8couS$yeOgeTg_*36Q2F(<Z{e8senexgwmwVP`cGg1};4-m9g`^Nby#
zD3iTp$*9GF6UJMbmL)mDAhWbgPH#r;_m;nZQ1i+;jR<(R*U_Rz{#U&+TELYf2<^zc
z%;z@Af6LUr@R7TtkyQZ?Jp1Dk#vPX4LihD&hQ}`hi5pIseh5rv#nYKF&?tx@05)-c
z`$7L(x{#ww<ltWtAMatj0TXdDm=-8$F&wAl`gW$ocdCgTR`}&$TtG<99sM40m1+?u
z-czIymkVsTA_Y8{!t3bL)#8ZJ@2?3v_I#869k07od_XeFnl>2BsHp{@m}W3Z))eXS
zD0rfa7>bnE*f<R7#3tMos$Mrs2S3b@4k)SKA`#(l_POw}7{sP~e-TRs<-T>I^IBkK
z?hONGySPs@&|~o6AIHz5Z!TJ2sfZEM#U_YW-7)Z9ITeJpvD(K$9eik`>m|6OMyPmT
z=2z~&j=@5(imp+C4Ci?dL)$a=f;}f7m|zuaZ41(`FUW#Kc>1BV7PgGGPeB@Di!)<6
ztW`>|W40Xv(|($<Xaf6)3|-{^&`)IC+t^gDK;uVgs&XHYj0VC$;yU<Gyi}waZjK${
zJ^Cr$u1lpF5HRGKutOW=5&z+O1H6!5yW-%l7AtY)qYx_3?s84jw%Cn3)g_Jhw<-~m
zQg(L)98=*GT4N?>u=>wPbRFoV*pA<CWX^vBVkIC0^UeIt$7SAclaC_1%CU;38Nj>E
zG=Ucnd=UL(cVH)Ur8D*x3gKRDhB};_=`_Ug%eN=-^69`2`d2+bt#C|_z~p&Gx7&8z
zKr6~Iz*xZDi_HzYwi_*H!HS)WAp1rdn&w^cn|b+Ubt<u(QWevAk8lPA#w(u{C{gL?
zeQFw)*QxPLIJFJ2OzW6kulz}s_HXpE+Yrdb+_ivx!1y&C%JYb*GCM1HF8<3p>{6rz
z8G|z&B`RL6YD-m@Lq!&V0RA`B2!_~p;+O?HKq)AY$Yl>9&imThea7u-3%j{+qXR0q
z;V1cL?{s#j=ZIuUyNR+atx8-td)Ui62$CND3w37Kn|l10%h7nSmtGxEGpk55S)zve
zA%WkRTj>mxDp$iQcQabuBiQu<%m0C5J&Edo;Ae;LAgH$~Gx{R8k53AV+$F%CZ0WJs
zfnU?z7cLs1J9VFKwmj^jg>^zGz>l5?Nx(p<O2EvC^_358Aw9z=EX?)DW^NkZ^LWo(
zA<naa1}^XgEccy&9uRlLg9kx9X2HiB9T$`@lYP(r%|up@W&mLHAr5{D`S8EEic#Zl
zY#EeTkbs`UY7B$KA1#|pA<JYw|C8Ln4uQRwW|&^8vVEwmqB=>lh-Q^+lAZ9zKN*sw
zc3~@LIKd`K?40WWd5osQbQY=Fs@;$!MnUJDE=;s5lzyu|aI5F#3EXbjeN{pOQ11_W
z-0m*oI~yd4iqwh!aPVmR2f~DBC3vw9#aHvOwR>2NS3si$uehh#X!?TT{WF!W1#z9(
zh_P0zDsf-o*DeNvUK>PGEZ(@LJuxQ8uOyv^X$5OU{*wDwG^NhW-hx5Hu3MoyADF8R
zgs!Z8$2R+(uFXEes76B;Y%rMt#MjVr72urL;9K@M27%wa%wB!s{$u&?Z*NXExj<Go
za~E*kOyb*9o@d{MCPl2Z)bhuxR5rXPR^MMG5>YZQ9Pnl2I^EP)M_v{hpSw^d;m9g<
z+~67=ol9IBs^K0MI+>W4c`iTq-9ctzj5tp<mgJN`|Gj7i8<)XOCEJTK>Tnwvq4=p`
z>HZOX;y5{*U0uBq?JYKBLvzeWx}J%|fDw_=+c1d2k+3JA(O=ek=o#(tq0k(o?FF*9
zq1lA51Z9I1jX+QNR>I6`>AxNJQtKq-)Y05Qm5$7ym<^K@4dsNI-9O0vu|3MnJ=t0W
zJ-zJZde*_Xk^H-PqCidy5Im~_kWtvSAt@DoYxuw9jcFN20b?e~k67PYBjcN5H7%Ma
zQswn79yEdzlXo)do%nwH`P4(1$-$9Ldk8tMmoX&ad{-z>?`ZoeqkOXw7b{E;B7s%7
z9a^{Nbeb!p=*D+lo-wqlAGgDIQ@QiGm%J#^Q<pf*#q1}^W`!zOvi3J>X0W=a(|AUm
zMk*>Q+b%5l<ZYbR$)U9w32mCW6T`%10bD}m%v4V3EQKct_j1===4y|5FLG_$2Vm2W
zsI%*P0Jo?-8wI5y<c$2EDrHTfybJ@d4{YEil^8;8f(Vk|yzPl$o706Kj-loQbVyCg
zY*QGEy2z~uL1BVSc5=mx)&<oD+8N~imd#SElQcrn<u@euc6idx;F5IrQ}G8h-P6V+
z3Mp3k_l7Tu@>m&pvkb7BFQ$}_vAb;3QIx_8X!)p+<}n0Tp^<;i6UvxSN0Hq6)2DWr
zDYOWA?ZF45#?c#B*&ktE!zvtSgBLtU$Th$G_V3;f6+eRA8K^`yY@U>_j_YI{7vTr%
zx3+YO!lLx-3LA)7A1x0I3SQQ?lU_r<Esc4E52VR~m%2F&6Mj13^8ax)Yn%pqku^eG
zjZ6lFzZlZMKL*FRIl5s2#e{CJoH=}7<XEP*0akT$nPe+5>Xp77?oj4;x24!a%2UN+
zdIho=+BT&u(=5js=FtT}GeWc0lHq#pMOb#>oHcU-O8R1^Ah0dLu(=tO`uuG~SGoq^
z!t@*Pg)!=lzHiRi4T&6OD86%sCuY0CbZs*O$rXl{>{3s;{-qFD@DtG*CPsMbkZO>r
zI;tq8!v*+5Tu*S<uyXZUZ>6%|bd>+ScKtZ43#YjDOOdz(2mWoF;CJ`0_PYXI{>q?+
z=kSt+8O2s&eP}XoXj!x<7_d9^oaP2Bm3SW49zQu(vU7=jBo9T=*I32YmiyX5X(Pw{
z-2ir=j>UJFn=tzYJ6JTpui=QVe{H*j{MG*7RK2@AG>mv<4OyE5zYTdxFeG;ZtA$YR
z^%%tAARd0f%LKL?pwv8&^4Sd?TjQ<)==LNLf8>=OB~5sxa>rdA?+4!^{OC`nWfuG<
zI;>?VF&%IMLj5;AS)Y3i0+O_7p0$@K_ZHQ+F<SNJ3$Tot*#G<Ufww}-o=Ryyq8h}%
z={moBx*(?wQnJ>)#5v%hWgU578@70ExRl#<@Mo&6mPy5pJeuBMHaMiN*TnhF{kaS3
z(VMdmhr_YLR5&g!hz9ID()v4WI}y`gIrlpJxi2fF{Nu;)u0g132gxIFl3?V(cMT?i
zAwQMj!N-FLe{n_7_K__&jY!s0#*0w@k0g^d=e?l4#xHbN0w34$xi3J{)Nqx){y`A7
zG$nv+>&F_9_81mVr#}$>;+hI$sHOuPgmuW0HuUj9V_iPEbm3M|ssu4Kfrr^lJlK5Y
zz&ItQ8N#x4-J^q9#$(XOzH-?%#}pSz<I$FKPyU{~ef5n9Z;?P#gk6;WcdzpTuHl(5
zRN8~<a^nY>-|`I)QJ*}eo-Qa5vu_+t-lu*dRyw^ap<<s+L&A2}N7wWj(rm|YFKcp7
zt4ol*!cC6oiu+K?vkKzET4)Lc4ssAEGNXBOIK8czupl0@R6_JvY_{ccT=3h+@X+l<
z3&1$VTtaODHBm>?GQGVp8P+1o^DBCShp1)-k<4yiYsge_J?$H_mPQkZ9Y%i^#O$w8
zaGw1-%vRs?)pI9{*Jrby2>c5z*)Lp~;BhbY4x1*h#Q3tq%4uXhiS>)|jvDCf$SQ)x
zK#Xd6kS|d@sbPmm$P`in{;PUVZV*y%ZlpBqF4KJ4RJHH}h)WbI&JocfHoFR%_8lQj
z+rWd@Nm?URq&-5W>00zN4WZ)5nHXtRG@wsAwn&k8^d%#%Go?HvyTzO^nAR*d!K}ON
z;e^lPsFh4-IPmbj`hJ{rATf=%AQRNU<ZR46zB2E$tTz!bqbRrpcB>O5aYcV?+nu$a
z4QAlMH=xdqFR)2uO*|$HJ|L^s5sA>eJ!(9d5dcHb0}Z})1kg^CSEZ|#C;a{4rO9$7
zSOAZN#n12UL&&+?_w05c*u-SXuA=takPV0uKm@L1_a04BQ-mq3OhAiW6esxKD>mNI
zh!vgN0f2)A2vsiu|Em`qoZ#iRF-1`9?^Y;e=zjn!oR0_po2VXP_h7JYM<aU-zCx7s
zr-0wN%3c%7NC9Fw6pUDlg8hlQBT)57<&LN#ks>bnw~z6ze+G^YPfX~k8jqh6J!rq<
zAnvV#O!WdhYnFB0Usn_dB-QQ1awZG_>DWzuqIZyG284=N*J(4bVJ;fOqNFPz4qbv(
z2|Xv7x0A3WQ=vLDV02D0#18CTjy00YZMi2+wb|KITQ+!)OUX9Ou+E*SWuSNzOZPA)
zHfiEa!I=f@FxEoL{Mt?n_f=_MwPP}}Bt)?<{Eq~_QUuN-Ax=B~DBr`EF6C=O1F3MY
zhA2{&rHr!o1@9OP_$OPh96dtyE(cytv~O&7OI(+beIQjv8I4()C`H~b2B-O+_1vko
zSJv8@LWFae@+giLGmC{PN%pe}(%29evfzFe-GJOPoUK=4ZrtwXDvMJ1+g^&fk6orq
zNCWle1BKhMx7DEGL-k!%{UVe0kc^Bh3%IRYa9znVai-O^;wVv-lvMeH(8+W{NUgd=
zIl>P`Srx@+bC#4<Dt{KtfN^HGN@iIiJtWQt?;dqHH;N$sZ<$Fg)pt3r5RNe$5ORhC
zsCn#}eQ)^MiV~@;&aQ|B;27_*Gu|elNL96My+)rFzH1Vm^4}JQtVWG=BWZOp>GDk|
z+18T-bro$lxI5<b#yDUz##iPY2BVYCaqI_q$|g87dh|4_th-4J-t5i<XL`$lf*C~a
zIz06cEw#0fVwdzGZv=U4><Cop>6m#9=K~=d?((rl|0Q-JxqLvMw9ZB-9G$>t=bk{6
z+$)CTU`H*%DR&I|`k4kK%;x%$?5wtP?M}@**CRd^fT;?UROy$DJ9x4dq}+g(G))|u
zkbV!*y9eOkgQdGaF{)u%oJ7gW>$Cghy~6$Vk={O&WEn3?Kz3`vGXR+0>a-=dWdUGc
z%c$o%QDf3Fuz-MR4VuWI5?v$A{sXR*&R(&yjgu$S{=cW(YAL&atB&ISF6(*z)NI3r
zW8OYT_c}oeAO6$KcH-il-sd)+DB}~`hbrIXTyK$NE>P2@P9EL9oWRsq$bjTBPpNB#
zrTKd`1gIHp=i5ksCP9!8Yksr!;1$33PDzA2;$%57Y-?)X#Ve%xGKq@~*l*{FFhc{=
z9_r=(lj>A7`YL=MrP1jQ!J#eWn`a_<COWY;0*|-63M-reZ+NEh5O|Zg>rFese&~xT
z3(+QL0D4UBOTCO|<iv0h`{y(fK3I`HGJz@PG6Z@RIkwk=Yy+<0;j`Rt6qYq{9FuPd
zhkNalp&TOlxKz(|*g7*=Y0zl5B^WUSNyyRU2KhF-E{+j*^(IP6s&3%BvgyG+49036
zZvlC>k;LcW@qflN{4Od^8F)vMTmLOegLhWOBLq(5(q+D@sMjT_g~&$XlBUSO%%^7E
zEa;AWax2ZSnWWZSFYLP3S7*_gaBlNWer+8?M!n=@F`1tg*bJF#8MdAhKs9wPJ^-1+
zP`WA60oCfGvFVC7kAB_5xj@O-Q0ihbMY&2Hju39CUMrRBrL9&tLbL)!b+}5xku{%k
zwF5T@F-H$1`X@jN<0Pw_((m_)D~cMpnD2!a9xT$P>DOFNiR;2{M41)Xp5wBSg+6aj
zrbS@8DCH!#B@Jps4%dbA<0k?tD!bM6z<B|1-j)NfW}G70S7P#_waGl?)UZsz064t3
zC(aUfw5I;^(S=onM-IForhw%4`3j>swcR(AE_>L5Edgygr;ygneZ9Ct+u}e=h?a~D
z<tK5Qz+%jid?u^65R&iCFF_X1A7@<YpS%=aeE6qkQ*T5A0oAO~Zekv<<E${%JbUea
z7~Hf48y?H@JjUa!K+1b;oYN1N?e<8$-T`u?8<uyYlza*Ii3ZtFPKvwFrK1P5x;NDv
O!M~z1s|e5=h@aO%4{{Lz

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_24.v
new file mode 100644
index 0000000000000000000000000000000000000000..62f0cf735e9752b9e73503d1f4218e96a6b0006c
GIT binary patch
literal 9152
zcmV;xBR|}W6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkF4ML9#_z8|siPtbSMq~m^=8JxO
zNP>cABM-mwKFy%XUe~5B5hNDYcw&yX$Z@Q<A@1fBEbIX~VVQTnxU{d&(5*Bp(;~D6
zUg7Eu=&RJSKSmd&QkV>CkBZV1^@?*;-f|VuN<w;i^{41*zBLHFDs&!o1<BbjkPO$X
zQ3nBO<x9D)s_x>9ggb%TT?uJ)z(jH?Ns6=d^?E4hBgh&!_<^r!;sK|K@H_3Q$cfL1
ztKp{P6z63`78AHa5raALX&dQ$T;uFL@9VKKq6FUw%%_|1^>+};M#>V|qk&GKkm!mc
zQFqT;(}=Z*7!k;+7cyar1LIqKiWj}UVn{r!e*jsfNu4(Ky-oCbSKoG|u_8ZtS3Vl6
zT-O}57mlE$tH_&RIt@*#-yZvUE3Tzq)212|(gNVXt7q*Y++uGNj)UV5%_4eqlE2*E
z7|E@bViD{oU%K2%Hl^WvT7!U<plN$`#~1WGtgZJ{MOL!AQ%EA_8)zgcFTDt-k<vI7
z)%FW5fF+r$oF|Z-2q5ewW46cJ5MQOiuBm3HkVw$Z5z6{#OhXd^btyJ^J5WPvHU;^C
zjqExL*U|~sexqj8FN!&B#<hCY?}J#XwNx57i(XXNA1;}h-(}Fg;zVNG!#6pQ4`Iar
zvDJThj&wpMq#Cx_s7uiIfMQQ7IIF6Nl7A@CqaI7ZiL6-%zG5Z-GdiT0RFG3i$kwvu
zcH?B~_<J`Q;u(4%XAF40DYPeAU{rbiN@mzfJ#;}C#HC3-chG$Le0o;z9S<Z&v3{YE
z#=}f$e{URe90o8uPfv$%D_4L4e|ey>YmiAj|2|w6?XQ@^+Hn(O<#WMwBL`i^mh#Ea
z<kS=myZ?H-NiM}|>-YAO-`dFAM{gHRC8Ml+*&k@RCgZP;QKVm$-kem!W9=6i`&`#&
z;U>FYU!a9S8XJ}zIo2Mm52ZXVEd%qv6wYS=m4Ne{Bxks^zAynKUa``x)D};wdc{bl
zEm$^yVHqL_dtq+_Zjat;>&pzKdA>!0+3ghS7&L5+=P>`Pig{U*EOO61S+|lVT`A`C
z*%oUFAxlA-%;%VGT5nrzg*xIG==em`{|&=#e?+~+`b_d_(RqIVwuvSRqu-vK$6gZR
z^H#w8f`bL>J)p&t(5YIBocef^@ElxNC__9x`bwkaKvWIZfP2%3!9Y-q%Pana?&C5N
zXe&4}nF3@!$>)$f!q39d&{<F5q;&ssGe7Y+9sdfFeh1|#mZ#ny>A#~VTJibb0R4F5
zUKK~;fh{I-MW3z6kI?XaGHO?pb&E$%^-At^azlZ26jZG$gAc`V6gv{CH*X1Lcq)rR
z(H&_s=Xs@_J!k6rYw(I+fa7l4D_%|ger@Pw5m2|V9fOJ1)BDpZ%`ZV(B!|sv@wr5c
z?gmzXq%QITqXI$-JY9@I5j0(EbJ^tC66M=D1N@l){2!Cd9LugOuyvpf33IoRTm~}u
zNwCH0n(f7H_lw1wFzO^gOAQs?Q5Lh^ek&v%M4mY29}Co380z|9krJdqIu%HDtlK-M
z3ZiJ^K6Kc{lglta^BrC7{?T35y=SM60KHcoOEUyd1UUSxBK+ADbyqArIMZ!1#z)`|
zmBT-VSxMR`Vjb*@tIt<e>7(Gb!uOyrdC=LyonTnj+m;N}Am}nAo3Pav6qvLRk#~Ju
z1N`6WNh#qQ!n<Dm4z}8-kS^Y!`57|N@((uQM3Fi-5{WKQ7(@DI<f0tI;>Ey6gyQy@
zH`DkPIu<=2o`s2a4>o%eI;#{B_OzL|{T9*=!FpR-E~KYaN??&kauO`Qewr}sPjc<S
zXK{!1=<pgDtDI%T#(gJow#z+U;ZTCoE|5w)ua*xYMGsPmA75X$bRNxF!;&O<0Kuo4
zG#&tS2h;H54yh)f<I|S$5shbQSrJ0JPKbP#X{PVvdQx%k9WkEw5Sq{%oL@<QHUkn$
znFy$GRDeXs3xA<`j9B#hhlfZpwL0%@^s>iFByuS@o_i|q;Doig3CmhlWb#teddH6x
zD^h*91#x|l%fy5wqeqAVWFS+>kehpvEK%!8#D(HMwt^#Swx;uv6L6+Q_C*WrT>=^=
z&&FDg+>^J>%`pnms@i%<kRJpkz>Tbd`%*`J`ss)vhdq*@O#C@^$Esu3nIvJG$h&U4
zI_G35eZs&@inlpyxmzstz+=JnHwVrWOBK7SX`%>$@It!MW-Jify^`>?Gij01OBgV?
zm<&1k2b35N>q-~2Wp{3KGEyhj*5ltWFiRbphWTPysw2$}o%^L@AbkT%Z^&xzl-eE2
z-{~XriL{BoBvTYH(LvVbQl!AS&^<P5OO-0R#}=Fj7eT?9m<j~xs{qpPQ)aJ@N9Tw~
zMQf3?vWH9zr=-DPQO&N^aug7$_f536S(iYORY>FSIlVKEf|@d&$bp&M475wpqpOg(
zJgz7yUjSYrPjBs+wz+;L8QUqDQ#klKT*?C}$SgnHkxsfynWllHuPi7G!iM0OhS`-J
z$0D7*i%Hb<OyCdyo^{Ibjk7>QAWtECylqW1QDb`~jZ6)FE!cKg9Vu58jSbq^cm|Cf
z2DNe{QdsxR9+d!$Rk+@=#w-o!2n%(>Y2$(BpX_|4j`VdUyMyz_lX0GNCQOkuv;+7>
z=}Aw{Erx2Au;loZp?SL&jE#`;9sWF=>l)_!9L}IT9yu*?P5{>NF%2~Tb`V_R38y8}
zTL79wDKzw9>W97yVCo2vyYXMEN;y_M1>abYCIWTLHay4)x<y)8Bi>lh`<3cM^T1Bq
z`h@d-oz<#?G&iY7=S7u*2mWfFS{}eZR3Q{z*%cB$8=lj~DrqM;r_4mK53pDP^&sUD
zHboOYn!X?s+w=n1U-|L9h+j!_$IuLw_N_$gNuP)ZY|0}tq|yMU#Yv|2W@7YLSR|aU
z_vE=T_e-Dqec@WwEkQp>O{C=9&2@AF;_P|<y#W>n@=tJCA}IEEo)!}#ocMw34DhDx
zXLYb&8DRE*QySH6)BD1>On!G*8QKb3X~F0}-NJ&_$F3pIg7QI=VYht4Le06s(G;dY
z(v2@H-(F%q!Z$v@YVrHQz>H_1#YH5qZ#DRbu7U?ps}Il(XVRwbPeQPu$$2qlhSH}9
zew$@LkyYN*D!I&(AU1gJud6=0@zZSYf&OV}#o5nUwfd!6j!8Tm2#Nks%cIae2W?Gi
zGX+EEcRN75Fy`$#<$VuG(u`@6r_^>*QJV;zEBXfhiby$lc!TcRf4QdIJa98=(g^$6
zt9W7#gU~8~z^IQZijp-~eI+;3Z~Io<B}15A!3b?qL%S74q>atgZD^$i2v@t!c-KXA
zMbfR%q3QLo2%MO*-*A|y?34KFxkriB+Yq8nY&+@<9+OT)SdCASbae}+_<;?riY6&R
zZs%PRDwHMrLxP5uClIHmgO+`LHA?L*+N9)zI?yH;^S21!7MC^t>ffn+WIQUeAnplF
zB^UnS`9^QsH7BqXH>vc{i83lTemS>WUo-79h6O%|X6QLvRJiK<i24e$c*SSsIq6le
zek;37g<1UOEIOZ{<0+}c0_2N&$13)LhDtOXdONHNJ}FS@S>p9LS`Eu@u!&FXldy<s
z`0VHA&{YG5?Mso|1mZ+cRbJJ82kk=c-$0Xvt3OSomNQ2&_*+$?2cK~tn#g<J`9_P)
zgIpd5>RX|Zyki{(`Et)RX9Bav^3;K!y`rGWkQlAq<4ft<f?Q8yo~`VyI-!e(6VgqM
zt{SZTD<nt!o2!*p(u(72-$Ioah)={L?Ok9s`MhHge}oD)A`L3&GyWHR(Ct~VZ2+T+
z)jvqz%^Zkx3kmBv^mYJ?VU&P^PV#q4HE(iaY1~nTw0$(0M#*Lt=k2CyZE_4-l6upV
zRoL6Q$c6l`Wqb%d>O<UDeiKG-=Qvd*@js)bA@RK72t^t;LJfn_0mF!6V~8xHK&)Gg
z&!Vcx6<43lXL@&Fc@@Yd0Y~IZNbf_^G0iZhi{*dO_Na%7-S$aOgpE-e_b*DkA>cyY
z%a%g@yyEcw?e{yP+<TmDxzwcZg5i{llA>WIxfz~YW^_OrcLqPpq25l+HPGCx-?=Y8
zq}8`Mg|?s3CGqH;|4;Kk)nAxakW8>*(yPZ*K{Coy<zjb=`av6_1i#Wpr0D42lfOaq
zf+I;4U)iH|4k^Zbc<cYdgNJ_-88_)2Od?V<YSXO+B0=%LFNl#@T9euM$Rbhd>PVh9
zpJw{GpCsN{!BwAM)5G!Is+l`~EXj3}=Ru!-S7P50Tp4&q+eN2rODPc%g^!ms+dB^y
zEEt2t=x(;i?nXyQoZQ!8OJtkPTS)Z&%9KY8xY48RtxRrW!<^i4PGP|5SymPdZZNjz
zfBS}t%mbPGfeV9II#qIQP6(maen7`16>s*?d~VL<d=n7MI#6i`D8-MeNEb#r>I{_A
zKR6RBJh0k)n?5!eaLWane<f*gThL>TxIjQj%*9`8vQH?daWb@7sEi3>P{rF%pRWU<
zE*O9U>q*MmeC~0ZtuXtgb_nI5FcVMXu@-PWVY|)yhe@U`ZcPZKBo?A}Q_hhU<>ZSR
zZioB7VQt(Zh%;;?9jRNBNG@`%ZckEu_XB9&L#zmgJw#6cm3DlLl9`t<gJ^t^zydwJ
zEguhf?<p*ko8?p5fb#L_5DQy9mt*FIojVphBR$d>tk+e$=IcDno@(?G0%syq?vHpQ
zrm(+DDA8iEnL3XF2>$*m!lAO##ygFg;o_h(JwzB*OH?82#3x%)Fo^_Y3h@dx>OaBx
zjllw-m+&kzN6yTkcl=5F!h=;5H#S64Z7q@6mddeLYm>|WtUljhV6Sh%dy=d+@vi|R
z#dA+lx?Sn&C<G|$g8MIhi3g;pe%{0t*!?iza+Gr7EmNb<^%gtBxJIAkj5YQ28OD_G
zsmJ&KJ`p_Sl2tVxG!!;wmBhC~BkVqpo$ZuGsQjiLk$c3==*F%={(x|1h7DNY5h*yS
zZ8giz>h&oxq7VD`SjPa>G8e%O1PFQPp&cyUU;bh@2{?5AzE7NNWq|`qsI*i$4(x(q
zl$0H9j_|n*Ho0|Cr5U}6Zm9#Oty%t@9?Ew5&2c6gx62aD2Prj;ibPETq>FN1ffBOm
zaF?Ka2L==fJx&f%6#Aq0NDSFcUB3GJyo>1cN_Z`8bL`b*MAW|eY!P-}CqZ}myG=j1
zr$nkKN<iP+E#5~(dG2ki2cc4Hnn#^4r$axzcj{C`Jze-wpxqBi_)8>M#m-&B-b^WG
z46c8)L@jSxYoPlo8-+v^Z<lt3qeimlk-N-heO+))iJk{luxp#jbc7z{OLR<^-^(14
z-bBe@x)aS7+i~<~N`#X{On&q(f#3y-Qf(73b<~gI8G5QJ{+4~6CGfp#FQbMyGNton
zk>WCy^RB3O`)S4-#A%$6(SqeBC*Et`9E&DKj0o$Es-?c)$$KceoF7O0G6*TI8f&yM
z1gS`<Tz0IcRgtDkE!mJmZ9?||>ZfZ&rkqgW2=|1P_JkIjGbCCmAJ7|E&dk>i`ZDWX
z=KTm&(Mpv9&Jy=SFa<IuI|Z!@z>>X2XhD~p1ho@JH$%rFdd>MjC2@4Kh#{-XetM-G
zA&I8dUDXz9$vW54rlR$oQ!E_n0o#ufPfHo{AkS6412|Xsd!3)ypGlE$3pBRl%vUiK
zn|ng99F>K?HT~SU4fKqifNcfn>0y(?V;jRvw~VXP+kXT1k?U4ACXcw|4H{SJY>n2U
zC4q0aWE6P_3Lct%n_XUggWrQvJt?5~Q&MK8yE*2NH#S3xT7Qu*<nErPRE|x8v<h71
z50&Boh}idc5(8i7q-J>rqub;rFM*ee5>PS>oUR!l9!sGu&jSeweuu*6%tBj>@5Yhx
zcS*NqgK<(wUOE#_<ztEJxfkp@%k6!b_*vJ#5%kbndpRGQh4CxnL9!6#XiUs+Qg0}8
zo@gt;Mh*<+ntUFVd}+&V;=yvMU#PY|rr3f!c=KVHHv#gSp6C!<!(kt_SMh_n66;6-
zR<@Kuec*&mIpHOiHfuOtd?dcn+`d*j%Vou+{kpfvNJ=-?@l)nM`7bvzagXQM@OnWh
zv*^{fCf*3CGRudS%0o+_a)kZS1G5jK-7$-mW0r6vl!S+?ppucqmT^F~CYqw&jvR#X
zKJoB-qncKU%rV$)ApQ_&$EKr|DYrfEf&r!8&!=)}KE~4Vd)5Ya5CtFUk?M_9iDw{P
z!ec`6VGwCvkNjt~)F}W=TI@KXUJ@A(C&dkekU@IH__r;<rr<XsaTRDv<xjMJTaL8u
z1@?x<dfY~7A;NaadsV~Wz3=8JKL1t4!O{?ZY`=?{yI)x?0w>{C`Kj$vOs(&YUfRHd
z)_&c5D&OxIIOBgY&_A1=Y+xZUrghrUm`5#g6Toz?JpY<*%6>+dZ9My!-S0y61Mz#k
z`A4!rTdOQrjIZI%RHYN4GZDR2i&zf$UE~}E@FSQ@A2%h2k|WPMH`3+Naz~yuxpt<!
zrZk}PIbTQE&mD4PeXurJet?^8IW<?J+-~^tS-*9WTkth|%Cv+?o`HmytYHomKH`3o
ztWT)Khw-|Z@3x2bXZG{YYYg(HEf+R!^R(pJqtqQGB1pfY{_SejRo25J02ivsfG^Ws
zw8BZc8K6b2P4q{;Gqr+XcF<*W6L|Od!@xbpJJ>P{L;@<mOwHh7c1nA&YB*S#KC1_O
zGc=Y}&fnuk3b}5V?cXoOLei;Gz~W^Od6H$W0q>Jzi9-=unHsnLNFp;mzHKxm24a&?
zJWyV@6c>*BBv6*jCH#m>awsP*OZH>XLubpbGFAKjvR0NN?C-x>AIfLT((ZxP3Rz_s
z?yawA;It^`T}<lb+gBUn)pbS*=i{+ewen}GyUOz?_9E~H_};wS(VdGI2KHA`V#Lc)
zkwBT4w?EC&kI+s!1UYu~1*-;Rmtwdz&K~qP#VKM3>EWzaRgtgi`iWri7JDMwkD2x&
z4l|lz@4Q$cTraUc4t&9B#_H&i&u33sNH9}<^QUzI@KTYX&#pV`+b?ned1=j%xj?^b
zA?>2eD}{#@w-OJc>^Ajk^7<<8oLx92h+?W}{xhMgec1-G1Cg0X`&rLy4dYS)4kHD)
zT)FWasNaHrMV4pMqT%?0%0rrsGyl>lA{R`MMZT|frAWyKjW5u`IyN6&0q6+P1*$0(
ztNkMb#L^rcE$IN_k^%&9kzLUss?k@OB)Hz+?=>0DV9*bBST!jaTEW_iYP=}g_A&E}
zID)(uGl%;?m$R0b>KV31stm+$@#1A6vtD`M7PRW*SE&#|fDcfvXLCw24M$COhQDW2
zo7JJ6fx|T+X1B($z+pW<F(ce`%vwB%o|~;E2F{{(bdWqdMpF~6e0G;H2%!&v`6?hA
z{c3|wb4|)bC$~=_>uwUde)Fv=h(1PuGj-(Y6mgY)ED3`0UZ~o-)--QdqH1Moj-Hi%
zdVa!$KEeXL&43scjNluGhz*ctzNz)&X(-nwHDGj*k(IolZM^+rsmd>;J@WG9iQ18W
zCoc)^DWy)WmIJlYM5pWTrPG;n&}~z7pU%vj$p2hJyGWw=!Q;TCtgXw<YCRE||16Y@
zO#EUy{P{&jU9_|vBVo`*u1deqd$NkZxzdDcG(kG$fWN^<r2}>)6Lr+bulbDu@gE=j
zMwB=o=OF%T{yeq}j<T@uXdg*7CHB%uooKn*v#15mI6Z}m@bt6PPBc1LOT>ef;6gI|
z_oFsx`;?6vm!{8PBe~MeFyoO$rBQn>`EUrpGOZhcQ)<$PC#lBPy|X&i7!IY&4goJf
zDB~+I(E&!T@8zIR&38eh!s)=`S4yr*pE16A_0g!QxF2xA`-@D)=NhmIT~Fq5V@i44
zJ8<BMeFG9{)0A+l`Shz1nP|U*9<uaAwXv14WO}p=<Y0cwj-B#<ortAV5ZPRM9)7;|
zsQk4(C%=-G3%6SfIn1%PA$Vo1%{n#ThSV`DexHLy;8IDN)rm5K7oF8GPZd~|Wj^Nq
zx)7V)4J7-jMzmTHmy=_R8g;v`%&-0P2pJy~N5p7vQa%Ae3sylaE7x}*<_~b$xy=ch
ziE5>B5}Oaiq3@{Nt}+xJfAehP9~obn9O*!~iNYMBlJY$o>g>MFN?z7Yeei5004;K2
zT7Pni8z-fa4F+Rt!tp-li)#v3fPw!>PLUs!fPplW{cQ}yIwyZQl|DKHe|!+~&{V!W
zw=?HDC#W(@@pv5c6K5CauuUF}1?-MfD@NcZTxt%|yA*9TRIuPLD|X<v*o`>WzGz_W
zhJ$+d(40_&nZmRR`Omo-st_=qWaXJVN2#BXXJMJ6qYXdPJBgeZS0t~cvoZra(zQjL
zl~LG${@wr9R9d6(FllutGA=Ow1w84e_94f`!kctsK8fm(*-`ZKD%9#FwrLk&_{ZaW
ziSzI>j-TfRIXC?M`&!VIUZ4L5?(NcNVLO&EWy*{Ja5%h&#KBg{M8p*J$!X5sZ&G!K
zvdU4AF(r+Llo)`s8kN~8A<K(W;SF}-_3diVLkB;f=JC}FbI>($B3F2VpOj9wvo5vR
zxb+yHR#t#UxqpuMq*TsyxF>uZ7uY~zH7^F99mMDW7I%baT<w9RTHuzFwL6%cqvyoC
ze`Sf4JY<wfQ?5ghQ`2NT_FBd}cj@{(9Hra$>E=8_^aB2C@qxz@xF8S&+92-_iE00&
z2G|6G{YLL6_}vVYCx`&&0Cnn}?(f5KZwI+EO+aK+ObRWP{akuS3RI{^?tY{A$i5z(
zh`N<iP9aTJ7pH5B)lf*gh^TMPu9j%+?aiQHLqw$fVLDy&F~?&=93(yPky%|DF*Jm8
zv^R$(ykG3}Eh~oSH%6Ei9P(7l^>gHt_~~1YkKR?4ppE=$^GD$MJTlz)?Cfuh0(~>~
z7m)@c=Bp<vVY-F)+1u+MO>*My7Tu?kDRJjcI7fBKiNL12)A*(7pnNp}#*~=uc!y(Y
zTe%4lB0?|vY0vTFEMol1T$+$&4wR9W55ZuJEVU6R<&0h5d=v_#Ox3>YPkf0-qTrR2
zOnzvTYo-`Elz2+Z7T$oH`YRc_*GJ?0{oZL&S0Fj=VGC>N*uHex6aag`VeFx`@wPwZ
ze7q-^!6+*%vmUed>u^VL#AR{k67<>c^-m2yV%MTL1TBu|0>M%x!^ny}wH>c4DaHAn
z^L-!WmELVkS`;Up8#iB3w*q&ex%+F)KcPD#D@LfSfaK(GF(hJ_cx>*d$I_|4gk;5?
z?WbL4#5%qwCM9lS@r<amU>y5^?;wmAv48nbA@rVh7q#FyeRP?>{~As%`E=sMAdj%l
z_s2Py^U=c`%k10{xn2aLCgDMAJ!qX2>U!i0#Iz3Ur0baDd3dzh?r~P%(fYkhE4*Y)
zXr}{AkBej*hjx9b%s7}0vrzQdhcfh68rup88uc__m@$35<%Z@AKg0P;U&+!Kaj^XF
zpfx}htcd9H^XIEXc@~oIj#lo&0i8datVYx>lzBgv&cLe4XuYDd8%?2^J|22Mg~G{w
z|0_j)P4Pr2Q9AqM8h-Xs<{C{8zp>7ZbcSE#ib?M?@mtnU*2ER<liYs4+;<nDcn0lt
z-%i&$YlfR&(OAvBK<O_~!iaAE(pdu{;O?qQ52286At?wef&*NwMZxP#gEw{OqajRi
zYdjjf(&m?J6}&j36h^iUX2Zhwwj;XNepF0ACP7MHe>uo>VNnjma>R~=rcaml;WPsk
zLSym}{VjrpT$jjgN{%dDga>JGuI18^b<k?*yCU)9N&_#CmYMIl8c7`r6Kh`j`=cyZ
z>~<&|{HP}C9P1tZfrDpiw-~@p$1QZl)dKld7hNOtJAoy*hmTUwdYaevx8iNMg+jQe
zYVomcALKmkq0i6s?@-3Un);=%wSW9kn~q0Y%cgTEqaW6D-eUved=mbW@ZH*-#!Vy+
zn}z*DTW$+Y!Ii|%!Bjyiz_DOu0^}5K9Z8ogL7BPp%Iqi57Ot3W;&CE7S$8bjm29t%
z7#}=viwlDR$Hq7sM!Cc5Hw}9ZVJba-s0|I$)o?M)&mRovM2hJ9V3yr0%|;7Oi1Dja
zfq!G<75%-ieFwTn>u|>Ci)dQva>A(~!a<6+ItsSd_G!j`Gp<;L6Ya(nA>oUJ#Y?@7
zyy9#<cikf0Z)pM``LSIpfX|ht{}YLs!@Di9EZd*6tWvoRE^DkVNb*^X3<eB0ZRKRp
zG&+I`5B$NH{5#K<!7e3*s~UVFmEXOu#-1ybYZXyKwT^=iYz9(zqTcUduIyOyNg6C$
zr}B1XsSEfk;Pt60u%I;Px+uDYPJEc*2c|Evx!G=S^_hf2L_AfY2elsbj3J{Zdw*R}
zYkMSdp1i}BH!DrFx5E)5j;7m3f>suy_=s#VB|s#AA2T4frTA?gcoG@j$x(q;fNSqQ
zUk&J8G6v|IdK3KSsLo))NcC8~NPRdU=N(^<4{Zz1*z_jhQe;Dg>z?v*|Cht%FjMbt
z@SycOc&|;O0!G_hPL8d5;H3`QTu2F^<PdsJPw>P)O}dL6mi$Rgw;&YV?KbZ6>}>#-
Ku0Beg<LMO%)ZVuM

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v
new file mode 100644
index 0000000000000000000000000000000000000000..16979f20c56573452b352f14b3837708b1b66880
GIT binary patch
literal 7312
zcmV;B9B<=`6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxB+B8c>)b9R;6b(GK#
zAh?v8NoeT+$D-qT#jc|!R&;T%V>7o4>B6h};`DI#h8;RTkf+|3xQ#N^J~~{)3OLIm
z;~MdZ*G<*z$Kr&76s|3Rs=a;M@5N)`^21wEM1;(a5r_M^!FX%rmpXcpmD0RsE9i;r
zZCGU?|8nn;yBu(lpW_z(Y%A&|mCL_1&?3(&-2-nA5CwV$>P2+zjQ=_=V;$|&S+gW%
z`1U#e;n|mt3@Ns<ghWeXvGS}7U~-kLgf0<Iw0J#Mk}L?(YbjL=Ua@FveO~l$Jf`92
zpk=4d4dAvmRt5GC-zo!ggHmf3Pc^pE2`_SUxyUD^AivIfDQqJ@AMv&8U6Y!$A+~F*
z1g1>t)yz10`XDKy3halI`-`j6{18?*Gz`l+*2Ngm7i_0o+YhzAM@<A)Cwy6+ns$Af
z9JbWvXaK0}=7xMMi)>aj-t(P78p}rCOih#h2Pj<M-dI&7)R(Zy89@Fj;0T+;yrX5D
z&tjr@6y#0H`Z+}2Vb-S37+hZ{Bbi*Nm2Rr5s)zIb%`*(GQI|(E5$gl7nrJl$F4vb?
zhw~dQm?C5-X;p-kFIZD=&x&4@AFaW4P>+puAbkX7q>yK+!A9lb*_E7cMQ&Lv&DN6F
z5cLP%BDP6ho4MWDqh<ImjZzcnQCoWIA@x!TwFaJ!aoLrVAodv@!Yn#?XALLtjPA%{
zfXL=e9=L-AgOwg#$n)!{1!e|`ILKK4V$p06^Y`U7GZ|016wWeE1NzVi|3>7=_K|g1
zng9w8gq~Lj&QqUN2T~3|FJ{Ot!w*RI)O}#nB`;?|cnnGse<$~Jzs2rZc>0<!g$-yj
zjuh{JoQ+9uSiqKD-~=<P9g4SI9H+W^;?fKDQjvuR2kGMa^C_C$Cr<x7v5EJQj?{Ms
zR39{YSi)1*x#}g?)vVrGaW6;$dI(`{i*u~9gG~}d0RrY7vI3+(9dRJA!Vt`+{65kx
zSY4nF-vpi6By#S4uEry(Ac-1`69iS)!wlk>;*+12yH5Cv$pok<F0<}oBHfEtvWyMl
z^QX#&F*b;y=wmXyK4!LK>|!bimx30tK@F&{(CUW-tjKEsQt3Rxp3v^HckYRYR2Mi0
zz#4wemXwnqF`umucs{j<ZyeRnXnCWU$0(F5Aed!fwF12PE3^uJ#Ba{!azO=J`Te;s
z-8x~c-f4+8teF{d0!zk}V~)npHUJ)DWvl!qWmMqtOd}33XUcY92aT`JDCK05GxFXJ
z4Rk2$b7~ViZ@LmWD+UxLLIMG?zp2FrJbM;}(xm$LVK(*@QU#T+{|?x4OUbO6lFIZ(
zyoey-{Ezuk(FpCt0|0N3|FxLTC=?WX;Wm3yN<9WKsMpPALp3C}fw03_XwwsMt)Wb;
zuKe+h()K<P_C+M&(V`Fd_Un|qj0lzUI3+sSIapYW0M;f{p^H?s<?BT5l!-3F$jGoH
zK<Puu1et@I_D<0-ND>5!L#F%_TQ7qfn{NB5jlQ-0lb?9How&D~uJUhTz+%{Y^^D{V
zPuoxljGA*l8B?QZz!QytfeE%tUOt4Qi@Rd-0Glv8-VOWhL^UXt4Mi%$7ANHAv3sF^
zX70;hsmoab8s^%Y)~AAVR5@IB`CvSIFM~KZt6drAj^9(XnxOa>>sVJs)LtGiCU@W5
z^+%*7tRd5UGa_jWH<3&=2gt?kO4yC;+{3C^{5esZqXe2aRA%v_Nk-9=i$H%7!DT}S
zwVo7?8P!jg)x>ac<{@;=$YI63zd{r9dx9C&xP#i;8lvW2t4I%|Avi<fbo)%cG5x&~
z2)oytSVq$Js16FD8KouN=`^daUX9NCfXf9TB@$GfDWiPjf}E=In>zKkg%P6Um9MCB
z<l!iluyfWKtmx6&HcdM~_YDvr&#6lUS-Ue8uy0yeJ`~MMq-+{U@Im7E)<9e7C4hyc
z|EF*lJPMv9Uw_pjv2L(6^4`@Y&G*Bh_0dOs&U?{JH2B#`{WJJ5DUSz6@R98}ivk-=
zi0g}#M4W&527VBBO@(~6@Mm?oi*$4~j@cEk&T(kCd;)j3#=emT!YLLwn48*2<L}Xu
zFR!7<<fF)3u8C3NWq+T^oV|ZN3`^vdsCmBcsg=h+ATjt3h8Ri?&RDPKqnrHJjVatl
z5D5uEbifWZcG!;jFP(i_Jg&6qPhq^A-3ri*^m&#GBSFshJiZ*##?5zFs;f}y$-9R3
zbOck;jLL^nHtfS&)P59<Iyip@NT&95W5Qc@f=OITAfhM!kB?uW_0D)8jl;g@4G)_;
zGIPR}(WPycN}b59k*`m;R|4(K*(9}?_th7h)*J5-{4488(^~M99)Q&z4SzDYqmdG%
z`q~@J@Mw<7#qzDo)Zh}{rMl<(jvV*<gT1VAe~R6k&RHPTXB052R1wdI+9?=ECkTvT
zwm&kT@Ymm?Ldsw-g)bY>0MsbHyq<eS#9bjY<^u4fh#hVKc@5}s-lL__O-v4+=9m?5
z9uq|MmDrDFl{&L6hr0HTj&m0ckz@%sc&hvm6!wm8k$REa=uF;0BG|01EQ5N<-zToo
z2o4n;uPsCR=T+Xd%z8hg9lutrcHFZ=dj}MWC+^^lRR9^T+$PlyyTk!|RGPgnMi>vI
z`6HTZ$>ffQSDhf)>>0#X{I_Jf?%G_;OQN|(bV{IxiU&Cp=h{nc*h0CHNcH?hL&pAS
zT5<MY@D@BL&1d<IMntoo68lfUIyt5{T)J58i#Qu$+3HP2NYHME<$<#Tp@A^JS0lG;
zG|rM)=US?qQO7AlE$k!MBp!*mW!MSmUmmk%f=F5|)ta3$=%1Gw{`}jSs46jZ-vfT=
z1M2Z@Di(~<t&&#S#!*i&_lyq@(vekHeu~yrvKor+11mhkAT$EuJLLT?ma>|VyX($S
zH&t6fvCy`Cl=nPh{d}yf7j;!faC1jrL~%PAPTh}RfeE{Gy_!ruT~_65BGZ+6S39Pa
zT)K8kcgWZadhs;pIzOcSqn~Ga^QkEM_Lhri5X&5mj%w2}=#UQt!P#6{PUKfD2pR$n
z<&#|EFOU^p@V9@*)3zb6DfYrTOLwQ*Z&98S4j{&dcE&0KZGLoCWN0%ej^+lcXfHL1
zSj|INcz;Fe{?qkamkAQ-8!)<q4F%0&s_;|OX{Ai6+Om+B;$Cac^R%QNDy<zN$P}1Y
zMfGMD&WVGI_R2Oy95~Q1!zmFirXl*)BgEp2@}fsh1I_y>I%~?OB<L?|ast!^Dr}5A
z`TF)P48=8T{VrykIG3Wrt#3U-iZjjc{7_y+9m+#6e)RYiH_r{gG&d~jpi_5BBxqnW
zRdbhDT>r|s#}PHFMRmwy^c2<;V3XZH!K|`203DTsx0DnC%FL<`=$pNU7MS5hEq9dT
zXvFF?DpNDFGx@{&-{8YJpZ8w*0Y+W^8^`pmVR82qxWKbV2gUL;6N^1`iDdh<C&Nnj
zIE;{@ICv1%eNHkWIxjN+6-{o?V~CQe=~SaNC9+2~cqV4go0XruB6vssd6^m^{u8FG
zU4gc{LkJ=t{J`GEw^IYNzu7YzZrXhBe*lnk;pUeRwhVQw)xN<P8^Ia-XNBQ?*^<0B
z;zuxEMQ2U7G}}%-NAZ1~FgsyxZ1)vi%^%Dz6jmTTUSM&%Z7ofn=(=GEh3Y<c)fMQK
zF#rYQxhyo7Ma?4~R$H!|+hibFz2V8!;AbxHSZ{aj;Vvdcz=1^hIcE_`vUskIPMnT&
zFY&gGW%3v;pH2CP(UJ^(W?#Ok^qt@Sa4Z>W44kv_8C;0Ou5Tu-$f)`SIOHL&XK-#5
zAr4oEpv@^}EF0usr-^fGr4q&A7t1{xjF%~h5+V(dfUwRPy?^SnL8H1o`tn>K<tU3e
zXrH@RvRz1DtAE5Q(9V+Psf5I5JbM~|HA$`IwCHX7N3}p@jS*Fa^YO}Q+horAG-unt
zwd9fYzpjs}?S!(T1hxUB@HUyLhMz~fXiv|0i1)~<l4S&aJe1wW`?!ci^0UDgNc+z}
zYL;g3D3hBl`4E%zo2^W3S&{4~-5qb0#-)wengSXOJz=5zhZbn)<<{zVQjLe$!pUrA
z<3+~3v-|4E;~V(6#?0z}tnoEq<U5s`&s9C2YuICgcB%QKa17jt&XvX!o~B`SDx*E@
zsI?p)$!B^}IBNz$um5A?ksSiAr^m6{1U7{G)@9Mbdn?awZ|MgM>5aF4vt^{+$%?=L
z*ha3|WQSTn@KX6#QA7Wck*jDe<uMx;3ZfP-@$uk=_w0iupwC9C306sVn&|?%0tI)$
zD#;+VK%kr_2(Geaeeax1<IH?AD#HJHAOcvX%jNQu)aI}kYs!`ga707t(3pMGZ3Ny*
zB^VMxaBBao1+q=SFe5hyqR-5(QwhM4D`=<6F8<k;&ZZ^!uJ$8CAPU8y`f*@SaQm=b
zbv;GFf&cmJGZD4~VxrEAYQpwAm83#HpqbJMtC&2Mso!MCt_-@(vB>UC@d)fXt7nke
zySZ_c2srb))2liWGTlY!b@{Y6uXY1rip5KN^N~ur`2&gbA8J0nxNrLkj}WS8`Jgas
zTCqvKrGtK{xwCz-un7r0TV02)GA2{l>~)UAiJZ-x!Ao9s`@N$L@B5|?!enpVF=`nV
zr>^XnF#4y^IU*(66mc>Y%c-$2H$y;tkL2CP*uC5P_G%hVc~RntB^Yw9k@vgSaWdxM
z*b*qw0e#2C{uFK`>2O5n^sf^@FJxwD?6_8osvTSXG}1v*aP(DhNGSCE3Uj@@#c_C@
znW?0Ug9i)~`f8ZOHS+*(w=>V{;aORmZYgfLY||9EhdH`RG$ot?*%hsgrB%1^9x{r=
zppOgfg@&Pi)atQ_DVW_O`iT3zrw^1e&tXLe=X2#qlO_2ewICDZo-2+~oozs*ahcdf
z9;`(?A>`+2OFIRaarcCuw@>B*e_80J2nMEIIW_p>>kS^Wh2aP+?Cvgz$usJKm8J^S
z7ET~2OD;hQ<4IgEt9&M1+>GQY5uInsnj&nS=Yt-da=Vo!eo#;324s>y*6~JRAseK@
z^aWQ^<&fR0E3*{6X56h(dxv*rs$arI$~}qm!+7G6u%W|6!V8&H3-oc)tt)SXzk&tV
zGPP>QZ74%YACiW;mY5<_Z@T>NZ;0y{BEpRH;T+b$X&+?Wp{647VRaGg4P@;7-Ny5%
zcBjVS3tjWAg?1LfK=jrG$A5PNplr<zu)ol#uT`m>9QAIVp~v{5ijq&N6U@sF=7yqc
za8(ULZ97}hPh`ca6y{B3y@;kwF9$6x6GG@3Y(Rtv6Svn3ycMw=gWk9=(4WMO^J2<g
zI##vc03toa7x|k_>kfO&CcyKbCjqT)U%^g|5g~2$GX+ZC0h1|)%!{*?nG>@U5o62K
z-J-&fT$tGU_=gM}e*OGx-fs?lcrMtrG5#Rf(d4HAthEL3zi|SE-e<(1Co>l|1210R
zK!vEc;Wk1lcp`d2n)H0)#}lp6Usm6fSyph^JLMxdU#Jv)F{a>ED++jn;k%}q3s;I^
zs(t^TaLS6x@~9lRWcWlaFyVAGx!)PV2V!A-sk0U}?$nM(^Y|L<fsR48Wrk&d5$A#B
z+6fgaST~I&#zKW|^%mTlLZ<Z2`~D*{^_f~VV%c=6+ISKzP{O8HsX)AoGh|B18D8?;
zx3n84n5Oi2!+*{E?IYr9;^nM*l;UtfwH7XdZ*Vl!(hU>VRc_94tFU3BJdg_urpB$a
zJT+>R>jd)=l?jpY_Kw8%jP@1!^`4VJsjC0$D;jOrB#xN#U|(mF!qDY4PL(~ztSlGF
z2E=2|ZZV1vS|{yz#IGxaE$J)2<umD(W;N%s_HE<SjgPK^eoLs_Go}bqZQ{}9cNLAK
zqaP8d7!k*HNSMapj*8hI!>*_}qf0AE&hn-Ja6xxFjQb12Vek-k)EHCJjkgx`S?MSL
zBuCQhB6Ugmt&gidDhs!07PpQ5xO?5obyz?D%d4SilkB-?#Xr>E&}zgzB=h`))tp9A
z-A4#&Y>>EQ#gJ;2|9kk8$;#n`h6EZaTM=eI0e~&e_z#y*0gz@c_{9Pa(}*Dtjlwh}
zCFLX=K?H5#B3&pbF$-+%L#Iq1_vt6EF!p8MBt-ram?^*H%&e&G_PhO$S_Y>?s<vN%
z;m>Y}Zx5geYyaKEAq<TU5h+?3Nvn~4vxSI<-sQXuCkGZ(dC|0x4%$)1DGB{@`Pqu+
zl@gO7cO&f-CUI)k5Ap4K?coLflQ~dA1LeYR9u-+Sxqcl>Dch4y91o?U2oKwvv0*;W
zI#*85C=%<Nv|Cy*uv{f5Oo4(iS}`u)R$06$eHX`~ps|K?JJP4G^6hAGP^vTjKbH6d
za@%>HAksat7x+YD_vP_!4}f3ApMh-rrNgh5R9d+r+sx16c?0?3)RtmBQZx1TyUyfF
z7acUmQizUXC<nKPJO_>MrQ+=ZGqE=dWCSwx7dfg)@1!*Z6rmHR(G(rNG=MZ<g3hLz
zNA~!57VozuyV2W1Y;})<xAIW0f2YE?Ggrn%dj&6ACSRGsEAjPMvqD$N+Jy2#O!O!X
z_<$;fTT0LH6c9OSgDC;j$NJhjyI+$+#uq@pyx~Rd&HIS9RSBgnQ7M9r-I{9)(YHhH
zMmB*}OK+UbNoAc^&A}d8QuBvEP%8TSG!FBb8MNJOOTqRA6za?B1%C45@c@D$>SoSz
zJ@t=G{Df`*j1;d8MD6KX%_vSVg%L7Nb?cdvi8)9}X?;p#`%`nE<;4A%bk75;8k^EH
zbezYFvv>@5gx36Y7jvB6L1i3`f3=1v#u~TgYY{G=R;?)+;C+l`#bE@DM0KGI{#3lE
zFO;XkR_DRiviBNoDY&^=kl3qs1sFw*2C*EevcHof<(V>coooefme!LIX2|k208rHn
z^nd#2V(HVr?8R`&*h}#FcOEfbSb3B4r0jZ#YzHa6jm-ije={`hyw&dPN~c%jThNjk
zf^0wG;zZ=hRQvI|w^&&av$HcPk1x^jXo{-jD|+AUa-H{3kWnW%q1;9<`pO)XR0*WG
zlM4UnclvV;Y#AR^0WkYmy}ie>Ll-L^WF7oSJnt_IbcMR7+%seF@7t`69T%0$u7!&c
zYUSK(wD&{nG1EjhTHmXAZ%*|<8gM2U5DNM(7xZ`R4yazy>%@Du*Z2(aww#YWFu<I2
z@W|;b-_LRqmkEg4-qiKT5gULT5MhD&PQ;D%e$KRFQZBU;m+;tDQ4brw-#Oku0M0$w
z{RImAl?!op%L3^PlT@jW$^@Snxx9g!?gO%rwJ};y%YrIHSYAeaMz5(<j1Zga1oB%=
z-<yLUG9@e1Y3*_Z?sE^L%cl$D)6_MWLsF>`gb3)r>W&wu>VmE_uSRiV>m_5Yxv!Zk
zQfwbU$M4h$_|Y2$4(fbjedJ{^4kL=leSoL-JO`;(U7@1zQMUh;^|&?Bn6e>~K#S%C
z(VmC!Wao2Oth$EnQ%cOA+xJJ;a1$9Ep4*>^=tN_OLy<Kv43|2!`v?~Gmx^i-Fh5Y{
zE071>ZM*+}c!`}zJ4nASEi1ck4l&PbM~wMH9@;11JlLK5AQa`pG-2K8(a~sUnhXlc
zhj%kPM)}gd1|?;o!1c{-sR{b{Ud!1X$8^k`$gilue`!}k+kCWduS&u~{GNEh-?2)L
zal9oYT7hwiy`ex;?<xvb`hu@v+T1saWqFJfI(}yrq0e)(te3?0{zCb+!YCtQI>8$U
zkw+qtP&qatJLf;MjAmSHow6FieIu_p<5%Cx-Wt8f-E0=VkH>9{<h<=A!^B5I<Q&i<
z1E1bpefqX)@QCPHD?lL}=wduW!<itS@baVkL-j7myo6CKEG;+X)B`E)^<A!;ClAor
zX&bpK7r+xoK1U&X{8nq6v`csrS8sd^tkVlGKi5@_L`plg-e#X4=IqbS2o@x0rNAkJ
zj_uyg4Hd$Gl4sNgD1qee*)u^iyK{(%c|y||(D=8XY-yL02q6Sm;C|q0sZ=t7(k<uf
zrtZ}8KqR!^gw#s-6#_sz<DdBf0;0e2jknt(^%Y~$5F9P9Iu<L7U)dU35_~AK=U~%#
qc*+;0!MhN!fT=^m*PW&@J+)~@q}fb<<d<mt?2ACDd3o5`6vhbc_Fd@!

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v
new file mode 100644
index 0000000000000000000000000000000000000000..8db5040878b83d1cd7f80081255cfb2c80b96ac9
GIT binary patch
literal 14328
zcmV<UHwVaz6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkF4ML9#_z8}R;ki~ExCeV~dOQeQ
z+;BS~9%?B1gr^t~^c2qt`siuRu!l7R3`oS0G2JN&zM~xnFC3rBW?PDw%cU3_Ox&XP
z9oMB3mtF?``rXIk3Ofqq5@$WdauM<CDAvkO0f<N}AX7m<+gu;~{)AC7M6u*p6MhbA
zCJ;~)UHP}I<y$X3{$uJ>82!=|`WI~1()h{9O*ggP$2Eos{OdL<r~N{9*|7avfv&9H
z2QK0mW(pHQ8g$XLIUTeCXUIvmV7S9AU}`hA+tpj1+Yy$8>5von?NA#Bp-n;(h5^e{
zaCClM^?(Zkw$fCBNWZChaU4PlMJCn_fu!Lp6n-VR4&ysst}7|o|7Td*9YrcAt=h*b
za*5M5vV|r<>FeYCsfPaa+9?l`V=fX7F*6LYi~!YiXAd5x;d^MZ#^rzYCbt(w>y;9?
zr2BG~md7xwiAOxxf+Bma&0d%v?ARpV#b;t97$#eCV%v1lR`y9$8WDYc#IDc?L4TZb
zM>~bQ94G>})Ill{9Ht+?Hgx7N<)2kZTWOsn`Q<6Ox*`=-JsaIW|Ag>QDfVi8|5%d7
z>}?S$SM`Ip&c&y$LZ|Qrf&>L6hD%ulJwioIyx^|t!(~u~xZ{QD9w?V5doh6n*ZZ#7
z=ssruL=VWy+8Fg2D0>^piFByvXIgWhNR2&c;pBT*(g)8o#ISMLl0U_<1Ks8g)1kmI
zKCT(eCsi-<>xJdc?tB^bKw|46^u-4kFaT-xM&5I3srNS;{2tiM^VN}U8+BVB=*}xD
z2$N7jl*3_;wIva5XUKXX?J{!i%%}a?-R3)wW?~PX;I=XCEr#i)k;eX99?(A4GqI7O
z^gIaU#&^&@|4l9^ddatBx`G2l$f$p07<0uZ<lLkytH0orU3d)g9nh7V>9`R}kK$Z)
za`qq{)J!w~0;jXK<QVi+^=v@vCSU}n4ZtY6ZKk0UOJ<kas_1neaiZNTAK@ip51NpH
z=Q9L!84up)=Wlm@`0EgJB-kV75K8?Gw6>-@U^&Nfox;dLq877vt4I{oxZtJlw{~{Q
z3YQBod?NeYwEAH!g(qX@<9`tLpYbj+)?dv6<pIUzX~3{@p>k}y?{Jd&aapOOXRnY4
z)mSnoQfCKaypmqaq0@T*6jo1nak4n0LKWKZ<M_IL4JZTYAfr0>b+$K#pI)#LGPjAN
zY`^r9haLnDI*KN^f60h!s#@|fL=|eHfmjU}oa*t&`FsZiu&BGWjEWHdW#aLk(VJUi
zMf+K_)UbjAz2`6Z7wNHWXkY#&i+R}mK97h@A!f4TijYePieP06e3SX41Y`;TqH?D>
zS3i|WblMW)a5b!?AQ~L^_{u96WNDp-R_W-~L!^lli<R{Ovr-!O$ZPK(w3Ccr{4;VA
zQi*`sMF#pX1kHr7n2Jd~{V1Z-4=RPs@(vJRXi@|?wkdRx8of2mBUUs`BX>?CzMm@n
zW94rf*ehkK&4B}^@+TY9X+oyxo3)$v0JM9#U@%B9vWS3X3atsm*~ybgX*;YFvcDMi
zB&r@56@@f$C}UbJNr)T)2FqhV(b`~|Ao!$UyHhrAi66s>%L&zWN15&Sl&)LE!jswH
zg5rV+qO2FCqHDF*S?`mQ%%TgdXqiZJJ$5f*fT!X%E?<Bm-gH|ZfNn@wx|D>VYxFUh
zoJ@^ivcBr$3*Q?|1MNA)&A`R{(!M4DCDST?Dod*W0EN8&(z*_KW}En~51~4~%z`JX
z`u-OTpP-u?Hu+-iHvQzLd@62`L@=_z6RwrvVa`)bGQxswD%_pV!jV)-C^h||w$SgW
z_1v$}8fQ#d6|<TEVp7XISi1@R8IiiH(9zeB>64Qs2dKD3(Z6)#psm|~I9_f}UVowG
z{sOowEkkKR3Q93Fmat&<+7(9*FYuhHa3FJ_BlJ#MtH7RmLEhYf8SH7hlYxDOX|1tJ
zm5P(jU-mVtc)-7Hup%e*Y25%nFDA{=@>Ow%Z+$g^QF?R>-dEN(jbC4$VhgxP8NxQ>
z+z7g{S2RRQfysfoU{d5P`W8(a;^VZQ=@2eXPLTKb5`($SH}g-(vKStqs2A+gHML^H
z!C_B5f&ZrVQ6O#Iv64{x&}?SkQqr6vSEk9{54rIydd*-0h1VahXsCVAUcacqm>Qx<
zBux0>C>=CR^?axpVJ`Wb(Wj?3-OnwGh#v*ZH>d#KR1p2Qo<9wo{WBE{G8e3E>cr+`
zCCd8i?NHxJw_N$XL~$^;1B@U6AE?Ae#1Sy|ddut1Uha+iCQy9@2R%mj9nN}qa6bAx
zXTa$e+gF6+4|OK;oyKwxLiZhacd%gIr}cZJOIHLDNrC4H4%t8p3^6qWQulw;p@wcZ
zx+Wp_Myscl`EB#d3GO}?F7(~10~w#=7rwgP-+Oifm2%+>=Y#8{(GkfCa=5S;{|d!X
zp{=TsXYV91pSWqz8hC`AQ_lGb<hQE4yo&>}6g!gGw7L_7F0SerIsUB+6f@;IWMclj
z%-e5I_}_aYO2^5y*I|+z9gHZ_z;K8Kt4*I}xptlGCPeeCOZ#JYa}yX9#>U}(0*tq6
zcUI2rKd4wntq}j|gRh3|bpo3ML(~I<W6$u}3l2R>ye$+LImu&|-w}aY;r+qscmK?o
zyyu-!GMEhHR3*EtDczo*8O~Es4vXy$yaiTGe&_NR04+D`bivYroj^0I3ga(|MUXI?
zAm@SFws(`{{#euxHX|K)T#Hyf^Zfw)k{w=SWPOett(Q{$Twl`sI{oI{_^6S%SuYTd
z9OE5kfZF`o!lI3dn9~bU_I+B0l%f|BC|kHqCQruh)-$H-XE1=#Z#rVM{TBJG9gn95
zr`+VRf#2e?iBI|WLZ^<H7#A_;5BORsM6-kHW4c&uF6UE4?Nf@!BDd2f&(JtXB5WVZ
z>EN7CH^#)H>lDYCG*~}#Sject(W&xR#VTrZ-Jf`9Dqbs_UcMjg_0s}Rs(&vH&ckiy
zRlK&>Ts+lim}Gp1r{H-mSNAI_y}AD-4ql3I2^09Q04Khl{fAz3yAZ8;iG^tF)t07e
za@Mx6(td-W!JNY2CI9>T8(9yMG<EXzp&xdNx;6N*qaK~+=!HA{Rm-*IJCu{&mr{hQ
zhW;`uMTF~M(i*jCMwan;i9hdGPC->&QmA&vo|~QNx7d#)Qvr;8&6xtN<{fe-(`TO8
zvUuiAZ!JY361EDeh9kN?o)bAOvt)C(Nn41uTb~}J$N%@+x^*Qit3qV6To||7fMRuw
zM52jQL^o(?0k}HA?yN5JO%Jhe4A+VJx#$;A_p_9%b(lr3zxUzf5GR98k(W`Yh)}&e
zwUX0ky(B!C{_(q}_{DH?&TnYr<_D!(FfWsw7^W0`ri@ksUc-hWy}J@@YzI@v$wkH|
zzYMROYiL0&tE;b=YgtmK0f80@#V>{X5#7Ko8*UZx=HIog|5Yutr*FzA9-UF~(?-j1
zV^%#qiIf#kzY=E5pYxdmTHJ6@;@cjo9+o4dGD0kpVo4byBlq-t*Xu0$OWlEAom^Io
zQRsBBg*FGZzs;D%*SF<8;IZl}KdI|ybS#@^vayyxf<u#ZJDH?`6;rth>w*P1UYlD#
z4vA828y6mf@pRl%y03A2U9q~CpG`Nu786mMkC`&Gi51|OUi=OJl&}@!`vV=i-f2sz
zIadnJ=f%Y|YIGa+ROuO_l#&alx5z`e&zc=U6GGRRyMNef8fF5;7+pft1%$rCmN1m@
zFmkHuF6BW^Laf_0JRCMzvj|FMU4%ZjTQm>e#2gW^PNJ&+TeW|z$OUV7afh=sqz05P
z?jsS?27%%SB0rg!X!#A+sON=*KfmH!R)Hsb8T>+2=NPmWD&L1hkVq`vCpABXTLK#U
zdO;#%Si(TPm63ZM)f*m-Az{n%iFF%gk4^0c-!7WMkcgHp)-*5c*mEkf&lQnGUf016
z{~Y&KGDjJ4gY$%NZ9$-aZ4rE_m+4>yQpqF^=)--QkXulB6>q<mleo^9FsV8GgIeP5
z5vaGjReXTFD0%AP0`5w0a5vDVE#~V0h+~=%f25*Yzw-qL>!ZDCMLaLOOTiwRcpG^g
z=g9D$j~r>ZOyo0ISW>R9PnR8_e`Zg6HHDnkDa;q8Z3H-<Vint~M0y1u@?J3Sk^Cmo
z6GFR?f5<cTTvbKcm47oV#-^Ejj<I_wtmsf9?gq1NuT45$^)#!&+>^%dc{oTduANmr
z_TR%j@?%Qr3J%3OcG)cXmti;%iV-G~+~~a}sRmd+&QKQ0@^cx|{=%#$n!Y=9ew=p)
z{xvJBTBJqD0;&d?3;rxL$Oe*)6K^fit)9<=9S2a^7rLid8Wd0}nZQFFa}sJF1w!+@
zG0uooJ&hxfk`1POOtCNG|5(j0z{iHcK!kpHmg)JpZmADnSC<agA(CM3HYhLsz(P~6
zRxq~Ff<e!fUQV9cjK>+RM4UXrj6QU_SFnRhFw|Y7{$aj7q%?~UO^xosnk}opa4vP>
zqW)u4Ex?QaFhbX`_Pb!GcAi_|O;fEfm3=u78Z`T9_W%U8=6E1IUo6Y#X7ujy5QK(x
zViJEccP<_V=So(jkGqC62Pcl>fNBm9OI34|bX$F=lnn)fp0*|e-lB663oi?8hLaXG
zE~WLcvy|84Kj+<(Q<FtEZ75&JlJuk=ceo{{8yWm1(yFx1<$?N&F(YERKrEnGucbb{
zuuMu{_CqTodmT*`K5kZE%8V60lnMS0ZiaUwsFd7XRT8YLGDJq@Fz59yzM!j!RWWi{
z!Z6FtPv6_a0|2OPR$3}c$*UuPR2!)1@M|IUA@Olcropw3{2I$IVCWZZS@d6Hy5tz&
zL#%V>f_^b7dpw^C;?JA0afuo-W_Zu$J24XCImI?P#g>~N`fT=H#g3k|V?MC0q}<KU
zJIkOoc9bE2FOWYXZ4XO=jJrIR3dRU>^yIRXtw-MmUrr>7ch<%y+dJ6odP`2yc9R2S
zlPr&c6*@F-#dTIeNw_b>(luIUseDYNXlxF|b~K}?=VlT9Lg3`DQ~r<qA~gp;rcipS
zIscKv#cZ#8Yj#t8AYW!V2-tpGH<PnF7~EXS%I9?-)FP|XzPgxSV^Pffy5RI%`X<zB
zY6ZLmFYon;XKK;p7%24{yzK&z<lsdWCrg1k);v6&9Plu~bkkVI=fR9nmRGy$Ld1eZ
zdoSiSWn>md^v&X;J<xrT>c@)Nuyi{2TXQc2iu;e8p>5@6qZ6U1Gi=HY0XYj|_4TO)
z#l_BS^jpM5-t^Q}RjI%B)kFfN@Z{BzWtA}zG4)*Lh_;Y^KDe8sUc`E)L)+9u4iOVa
zZy*oc0|yZR7ca$Cxsy}ONcj85n1?RWOY$Km#ZA#ULf!r^OH2a3O#k2Wzu5BWroa8$
zry>Ni`f&dPD0@`dxfpHbXGp0adopgKC@5Id7w)%98>2lqjd<g>OvASb#<mQVn#Mr|
z`pg-ILoJhd+we<A+c_mNYZTJ}h^3>6d$~o{lY-$N(UmqRw<Ktfxy<Wpi0}e2!uc{$
z4guk`W*2W~t?9jvDa0~tUmi9+ZCd_)mdnZ>59AED4vsWj2$J=*%8Te&HA+ank+D&)
zz^6lQpUCC~9<zn>8T66s({Tc{XLTIlq;MlqlS-k~Q1o)ouUa4+5N~IW>x{m9u#i*<
z+btL0_xnuSMi|sp5gEf!oSvK4dX0yPHP_3sx_4)nOeN`f{G!=J7|dCOY`>H`&mdU8
z99Yo^!m{3@4PIq{3%t}>A0DIuoFR6%pTQY%J4D9nfTQKOi6I%jj}sE6YCwOJtAT0E
z`{`eck;4p<&Z>ECy#!ggPimiW)oM)JNOc18W@bcSO~es2nwJ5?AtS4ISRfJf50G~?
zX!8P0wr{EWUT*;^9^y+s9z4YM_QI$~#QCiCsBD-AmQ-1F^7C!kRw*1>BSLz-RT8rv
z=%aov$@Sr*mssXQ=FT$VA$CAFde|Y8MHq#9nSEH`JtLIG#h#2CE1`z8wEV`MY4_dk
zu;1k7J6I8FLxrE1IN^B-GUl#@_yxzxH4PryLfN0H88NJYN)FAj%x*Y+$2^2_P_pBn
zA=Z;b_OKZ7wPRh8*8w<5B~t=?2F!qFwgxAJ?2(YvMe&QF@Xi?zhvX>kR+Jq)tn#MY
ze!j8gURgRX;c8i%JLEqmSL~soHtzc|xR8`dbB?LPPP589><+ikjKrDPRH5E6m5;FQ
z7n*BSRvlIdd?~<sE6W$YFJDO?5f4T27jU;m(@-Vm20(WtGZp_aE$Adz6&u1I&B8Bg
z@3ZB{K;PPKjWjBk@2w;)#c!%$oWw60dhkzkbKh_vz(1#5>39meZV0-Mz$j6Xy^8LZ
z7hI^7xk=hb`ITn^C5YCL<Yo(xit6P52>QsgI~}Otc>1Tg#SSS8O;vx9rj*mCQ(a>3
zzu!CFY<VLTX`N11=O7Ms5$}#w^;&~RlW|y7N7M3bd_(b-S4&dCik7i}(oPuLPQ)wu
ztI#LAGI_z>7IVqkuO+q)CnuRgK60#`ENWkaw=R<$)LA)eJQOOT;@mMIQ3`CuH$fSs
z{eAYmxdrP@CwkF^hmG^TFLDmMXR8=a+akUPGhqIIbzpl_>Oj2aZ#ssDVK}h&X9@|Q
z0s6bPJfAoeD|8|TBoTNcv2)g6<tF@!*>sQH>JS=pL&-$6#~z8Bn~)sUXDZIl;~@*J
zYv(irNXl)*-vVcv8kg8LQ@b5=>IM_bQ*dSf{Jw-3#y%n8Hv>b?1{OI+M?V3<*VZAs
z7D3Ak6-l?_qk*p`%XN6l`h$<z%Gc=GG++Sr=bjgGGNgc~`N^20OHdjkn|7Di<rbU4
zdDi=2e##c#1`gv>S|a^pDSHt^n<za`7_FJ>qm7}u9CT{fy5YPF$Y3~f)_#F*s5GqC
ziXfp|y{Ab9pKCqQkMBgs8~e0IN#g!S7gA#pB`YFdyK2j+xC43b)Xy?C57T+>RZ)Op
zR|qCQl4d0R4bi7@QbN=tAh&Q!_imt($7qD0w4W|KRM?ZEww|y3_D^Y(S_tWsPy><d
z*4Dm*u_p>tPBwArTK>%b>KG}GexRieDP*aAN0}F5oQ3I$sFK>Aqa5a#ZY~f78-dW5
z689JQvpKvLw451%d0`)t>&|*kYBf7okm|qz<2-<6^AJ`gvdRIJ+r3E!|2&a;1m>x^
z)i2}&`b?>D9RM3&epWJc5Imt4?`6|`*`Fru^n|?k;jy#{rzgTZY%Kw;xQzp8EgoUk
zOp+B%3~jicP8vSWue->opS8M`RfrYj{lPjbB*lZ)x9ush6j`OOX<|i*7_E4Sm%fV?
z4d1qf9jI+pRrsO}N9zMa*Cxd4nQjC^mVM;b26++#s=U+bHGO}n!0m&P085A@A2GKi
z_@^9}UVKK1+wK^OjO88crdsn2IjaC#Ds+d5rgEHk*l#;3irXO2TA{#s2M#&7o3QN8
zC4x>8h(#Ml-a|nL7s!2Mn(!a5G@CPfv7#T;dmvhBzKAxV=JbO5XLT=kA4)MpWuaW{
z4j+n$MQNe&%VFq^*sOuBbI|qz4zw>ff%gaCX(&qLHXPjY0cL?ed|!XG-GuZ<q@Elu
zB9AD*Ztv=k{X5ya2k}{ihC52>YraF9f<$SU8#F2YYwQ!CrNozq?gHmT_KwoGx{a80
z3>9dt#^aU_I$>MgCIU^6^NTPgM4a=<92sO#ugb$m<D8|ep{!(gH->Xh=rNpehZ~I)
zFE%^6iNZA^G`#0J;&oSm#niHyH%3uH)0{o*JUaXclmni21x@eq9NHJK7MC`wVpI?&
z+|hSEt8Gt1PF!fx5VQkvDDpDzrCCYu=xVC~{72MZ^u=@XvA(%#+lOI1RpAQ}&0&jX
zFV9qM1Iv1W8@u%3$)x6S<1+YO>Pm*)16Gd*)}AwS@WOD>k&Q{BG9B|P|C8`%0DXUe
zlRQS1!$o)=(l%#5A${5%W=koyol-|u=FnXQFnb?yEf)au!SPH!4#vuvYc&<dFtjQ{
z@osfpHr*r3u2HF}4CV~TE;tA<^`6ydx*!jguswG<+#jv#orV#(1=z6N&yp5ilU?U5
z^h#Ew&z(wK$nLJ<ZGU@kBWmFTzx+J_@*6CEzZg+@R$ex?HX^WMSZj*9(0K?i)ziGr
z2facdCV1*=4jta+#{STn+l~t||3v6$+^bP4NJ`v}e8LB%t9_o;kB<kMHi!dXNVPTp
zJNj9jDPY$h=V)>#TvfLs-G|;^CY}yi_9rW+2mcd~GQh`z+-`{u$9mzgyL8tk_>Lz-
zi`j;@25JYKgUWl?w}L86Is;zZVH2u}Vyik1$=Lel(rl?rsR^u>ZT|;X7iUk^lII=_
zvyR#w9G8Ojm+o|_#2_Gc<4$T*OuuJVnyz6OO}WtEPLrI~GhuF&rNMHe?HxT)&z}f&
z6-?^cv}H&NE5x0`ysEjdV(DzP9R8&rEqOeW<n}ohWB1P^EH8t06UP!uO->n_DSqqx
zX9vOSQYsMBRQe`_!Tj}0niTrd$lzUGI*|}@A0F_b*zIGVzJ)_))W#dgvV@hjwB{IM
zQ6!BT#i}H>sRZNz-AuD|u-cRp9!^sBNYs=Cw+c$5`3<(wU)+3To3?$~?~>f*4(v@;
z5<}5dTX1qy$32Jj&i>5V8tV_c&KBwmdANIorH3$S)la{<7tWx7wc6mN$I@OYSB|1G
zFRxswNPc$rA<1UKuatA8r?gllO)!5rrXo{_$2~-H%maylU!c$QqMOuzbsU3K#nWwK
z(9n;k-oj>MYRo!QkR^kohxApT|Cqj?Wv%Qhy7-({>s@T(UfB^6170x4dNdbYQm7-h
zstoY7snq;o?9U0?BU+-hg*LhWsLIM1Pi!I7HZ^%ZJ9^7&MJRcQmG{nJWP0z2J!szL
zGwCIDE?GmwQ2ZJs8934HVKL%6A}kEiBww+mfx`}|Y7^W1hL07qtv`HL57Fk|4gGs_
zZn!)IzJ+s);~b1tXvEZ#ZmRbl%!BzhO@IY2eRBSTo?#Z~bhSlE5DvCvQ>QO2k53)1
zjdmD%Pptqo0s6o!2HM7I6%9n8;$68B4!%AqDsv_sRpwzyHQ_f)S#^`G_uF64m5jOU
zLa&|L*R7$UFK5?2%9Lln{Qd$Q<?AH)=7<T>PU;Sl=>0?WdCx~#N2&J}znv7n5We7B
z+Z6yro7xwzD)r*Ez>)1JlM386W6!R{2`ti8_j28KjnS|5@(@3L)_q>s*}MOud~L%3
zMgF~JKnQ=a!;uS~QZCP|70hqhBpTdfP<#h`n>YtPdwB=rLk696$C20Jo$S!(i<;cd
zM^6av4_X@Cx0ebkePwri0^mD(Uy@RNgY0-$lgl$Q{@fVrp-&U-u<9?h>ZVnJf0>2*
zxf&CC9C2w?D<m}Bj;STb7OFk>K{N9Mp!V8{vICzXVW#_>St>6>>ee>R4kgF|sg~Ve
zjB1T&Zp3P0n>PHOKIZl6{6C&jM+PsTS^vlaRRg?1=nl1uJ^W>t_F|A6uS4D{)-i8B
zh*@S~Y6ThO7o<jEiZOI#oKGtk!(9&I^qB?wqw+)Lzw*1tW7w|q(`8a(383h_Z~QM-
zVO^3U`Xdm2ptWG`8#wV{RTly^F*SaF(YP%P7mU@qDbwOIT|hQMoU9EHI%||ei%-l;
zwGruHUO8=@Y>=6C@d(OOTSFaIw>J*jMXr(mSmDvQ>_3*a@o+efftj7&VaOeTpajZL
z9^)avM=I9t=#o|q<t*duH?Oe)V0C^DG|RT|${O%cLb7A%&d^nkanG-H#Xg~*fe#Dr
zmzMJvdHmBCgM%Ytq7X<nw1zX$fs$c=0SsGJJ7pAyubJ`*kS}=IaJX$s|G)r;<i$w;
z1%wD1^Q<d;zMR4<;Bf94-w$SuVWFUd$K@`!i*s%hFjtfgbKkcD#=7|KxmrrMW8^AP
z*uRPeAnK64l2Pi<PhH`esHWnCa)2aVt;YDlxJCKsZ`vlTgRi;Y>CVl5Iz}j~X-Uj4
zgBl8=xm6@SO|5YeE8AW>uwA3;X#N0yaTUBZIOLC%imt$fd3{7qE9XYhmxh3m$X}C?
z&~_}2eOd1O5EMlu0fJDBU(qY1y9Z4i8N@UpZ@>ZPTnYx|6J}|FrZztWW7xXMwjFJL
zcMBa)W0~RN%#Em`&!l}nL=SSXl;u~H#FPKgA&;U$bW&~QR7$hAHT(mOe6H?#*~*14
z`l`0RJ7w<*dKNV33RC2#o(Y3_CJb&Jjo#~pO(0YzG6uyD$p|cUr7V`VqD#33ljtKt
zd#Q)OG-H|38)Jn2+NkIda28hQExb2z-9%h?>&WV8sigDbxuQcVcXcpt0HY^$ZczvD
zBBX?~rKSrYzNnnT_XODkvxPep1$J2<#RT^<ZDmqg@5%OfWJ%=NqrOaL$3vabGn}BF
zz>N%z*~0@PXF4|OZ<CMR`r{R3yZ7b%wI_;B8eK2-uJnJHf!yV}Cd#`HR>z>#!FWzL
z+n=I@4He2MNtl#?qvqC1<(u>BZ8KK?!N+c*Au7A%u+qOLZpvgYPboIu5%9;=lFq!-
zip3*{rZ@?8qjPJd+;Zh7(AT*kn&G((FqYF8OyD~Tz%*f^->l(0x(LCHz^Zk8B0;<k
zDyFrOR^yme0qXl*n%5nW9BF2Yq}xr_Ew-V)9NId0B+^t`M&BqFG@4cuu>Nw_kfWw-
z3+pmCaN((opL2()z8BQ}P0W;~eDVY&@w82%IQt9@_-6@$PTy~{4HI+R?xq}m`6}7~
z#2vxE?Yx4gWQ^B{$`DT%?{^2lIE=U0@<}OCq(jC^ITs8qxoZE-y6MeKdR9^8)XmH>
z@QWc6=m~^Bytc=>>0m{@1Dn0`EFbsci0X~{ybD^~dntzHSl{AU?9p1B(Ldn_#RzEp
z`zf-w2AW_I$o_d%x;DlGVB|i}^GhzyJiSC3T@NcDw?c6*^BSb`+AY~Q?AyJ=04%EY
z)P!3j0L_+?>b41R4{X5tIH-}#Lr+2Xe%ht&Zgl#rEBQXsmtQ^1wX4N9Ok=pC)g05k
zz;#sBUw&jU$rY+~2O!;KKnZ4Z7$XNTV4~E_=0EKJ0)TLO!7KL~0YJ6K<9X%j0pZJ4
zT5|GSSn2ukHgly8R;_z)mET=7YaDr13~<ZYeY}f53y=toZ`>uUPr^`M&(x0M_4#1k
zj8Qw4@ndaq%}DSs*vWa#lb!C4{eu>;qgPpB6VwiO7VSOob_`7T;$2@|H?|G~dk)u+
zYnb0J!e>Lk)O6?5&u<53=s^JSg7SO>`1-ZQ$t(mO-g6B^Z5y5hjZZS~BjF32yR>}?
zV>@{Orop?)%#&I!<KI(=YeR$@A73=n*Vn=5M6jIs4g2wWy{6w+o6j(Wl2XP4F0OGb
z%-E=U-JNdEy&!mA%qa`tPtD*nk1UMxwooD!-xsYT^yFj*B-T0)qTY30cXVN*3+Ewd
zHP3=-bZ&>;p*CRQ&mz-*tnXtxSP3r~GdbBe05!;4q*jdjCAyi_pG*9<^xIS_dLNR*
z)lYF}&<`9ar~so)gq6mYx6P@~2_Gt(U2x4iBeHy5nBv!+O}9_EY+;R;XnqL=MXa#{
z6ntF*DsUCyTVLntV7pGu3W+2A5{;KRA!HIKCc({S{byOK9o|0sd2QK}>ZoSLZT|z&
z%<Mh8)mJ;7opX3+>zuJ0mFmABCSpTfBY90pROro+{^1djOP*-cQL@mFFwOvYdu&!}
z5ex==6y+$3@}`}p`~XMebcK(-($T-#%3H*4mn0>@decSQ|4hFY>PP7~;NC^>p~2|y
z!)wCg_2G(6G?}~urT*EP!~2F6`IQFqE;I<uD&%6EtrJ6?lIdx!8OMWyUl<NB={|A;
z<6)~_Ea8TN$GcCij>DdZ#RLs;Mz4ilo=0E{rmM%jSu^&}p&G|dazz{walCR_q9D^m
z%kO}2QT(ID<XvMZ)>NNOmuA$G&&n!|yuxdTYV!h?M;zXCcCK8wh5SYX@k>5@GvNHH
z;{Pd)h*ixicecD{0J)N|dyUAyp*gIgLva8C<i@es<MIAGo$xmbOqTBwZ3oOoXY<;X
zhn+(h3V1@^QPU4V@YLo-VF!ev1KMHc!OeZ&uvbP|Ufj-NIzw*#!)c#aNT&L+IxLfE
zq^q1t<%nLj3*>Hy5D!<QWiX$4cQFo|-l#ZUIiCiDjT$%d6StGlb!^V)i2{~3Ugoq-
zs;F}#@1;K@94`KlLHo<X<eP}hDs|7)7>a0v=W;Sb6h#qyv4ei7L8IgR?{FPyZt6zR
z4(P?FARdvJW)x04hsk)wzE(}Yp6pe95Q`9s%D$y!Et#-B6x;$8hsVC0Lnng@QNtNU
z?|Czerk9Ud0np$7J|Mb4>bipix92v|??(<EtU69Q)-WxYx7r@aQqG|RSnbo#8CvWC
zaNW|^vd$>qTrI4&wtIV%Y{xxeCDo@tOqwbc!SH!$i}%v5SjF*Z{;YFB$LqolQ^>`%
z%;Mq=aUI&F(V?~AG+aaQIc||CM+Z`V#>}DsVou7{PNZj=qhOLWwQ0gA*f<ivgKotX
z{RsSf1c`9Cm{PK<E~Ne8IQHg~`GayHOP{5y0DO464myL`Cx`n6_4aAKyjO*C1WChA
zbm$h2yYv&ZCTaQJe{AKQ;+cNP{1Agl>uzh<Z`Xv@fhn#^$sLd|FDpG4-y@_*1o$<!
zdn0y5tfIRDz7c2<NBf}GMn(FZ0|C`zaL8ZSM<ZI)GhSKN`M8MYXXa?1@mAee`?%rb
z%_5a{g1%>tk60iI58uKW{qKa-f}I0@VtdlACfBU>xzW+AiBrB0w?D&DrHf2hl>u2a
zn75f$a!8%;AYoc|CYSo9d{ChBKJGU~ZbE7yxPlbwcD9y<ypl|fp9?-)^gyJPis+2J
z^d;=xDQUtWw$wh>>!ZsO+VlC7;d9e$b^zu+E@LOk&lFE<#Ll7GxLcYP1AW=;Kc4|p
zu|6nzogpiQjun>>;&K>Gg5%}9h;qM$1;&Z$2Bl@P90>lX8OSoJeSHh6`FuC(<Hi+~
zxCT_oMS3vW1m;ZGdtIY#7bF&{+I!G&*fKkZ<cKmDq_{tI&gRl?ulJLN?PDI?{tjDf
z+B5Ty#JRx86c7VgBsk?S<+bC}udQCjps0=9+{K7}=0QzZAi!~r>);)JFsM(IYKfj(
z+^e2N-bqYdpz66v11~=)0hM@Gy!j)xv&2GTp$6UTcax8bBM6Wg*8xWP;p%v-QtD*w
z4$-uwdcL``kGQTF{e&*92e6Iyv)L3;B=V?Z@y3fV7JIZ$z7TZIIhK&G!oqMyq&DD$
z4Al03Lj@(Y#LIdwNTIndtVagFC4?iy5@X>c3A43-zYU3R&q8-YIV&0LAs`h$mLB$j
zaFjIUkU90uU}k5M_5h7NIh&+SSta4_6Te&6vt>MroF9Fsft^xS*NaXkWF>QLeLd!H
z4ZvVvuqoq{ZOZouww89>KwJ*#6?DP!vK4kKG7jvT{>IffBTW)$i2p7IetwdCJ~aI9
z+mcJ9GO%;yCyCPiq74RLMt6TEUMBgu(-$9GXoQ{rc>-;b1So6{tNy_ZWQ1;x5CFU0
ze*~);w0}9&KI8yD-VSJolkRW}OwjgQ3gK6G114#?;4<Cj_xExpP2}Ybg}~%GLKPqF
zVMQb$GFX9-Qik}e&<JF#tf4`X&Z1_{(l!woIT){iYluM0Orvq?C?J{lh58B^Ehba0
z*FHs}o@NUU`3|Li{C!<Y$*>nD`lwmXCTKWgTc?8EJDD1B=+S&#6@iUM&^Bj8-x;<I
zO(CBg5SgCcnDK~7&F%O!zRtzbs5LPwA2T>R?U9o&Sw4UshHuO=hA1rv_*KYEC~4(}
z@DjOxDl<->Ggxn>5rhf!*dAIX65*WtsKzd(mtj!JatGRXLp(CS`-lsD+jHz(bDjiz
zy@WD^9Y@|afBB%c@*$0Xs;`&c34vWsPldm9xD#7tViKx2t3n=}XK`3wP$}z^muVg^
z>$wkEfKW%ijPIg(*b&KI0Es8H9qLs{1hT}v7Y|v?tLKDm8YO5VEfz;22J8V?fuW-D
ztO|<~Y?V;n2!aw`)Y-fJ<~s75`+6SM_gN^=TGxXBupP`v6?D#f`oWw_NFg@2pe!hJ
z$56Xk@ijmy!@(ZZvptmrl+6HLsnfu9wDi4t@!)LjN|QzR|B>wkUfCc`Z()j4+F}^W
z1N6EyK0K|Z&`7VU>kWrny^$utOKnDTfg5_Q>1<hjJ5kV$3=c-Zr@eUx)_)~C^^0U3
zsm1G+BfiE#J2p1`Ds#`bsW<Rmn4-?yB`k9ka9kX??9?rc-MGfhM?!qiE<d0lH`t~9
zbYjx7#yp;*nthRz&1r~>Pw-NM7zG=!Unco%xI^MDp|3*3y0AZRRY`l-wXDhxs%H>t
zM16HHdhZOWCQLhMNs}WoxW=yJfLuaX?;b10xNG3e46C=fto8bE7{P%ebr(+g045uU
zmw*rih}K?+NiMyq13xqAojtb)+|qwp*zNhwX^?CqA68mUc^zPss8Ed%lk;_#JU2G;
z)aZbAlzyIcE=~X_KnzpIHusq7q>NL_fZSD+zMDk_1{=9TATr5W>OnFB7bldKjsZFG
z1q+kWxXNm}<OdBHWwo=#KeE)1p*u+t3@)DJ+FM^RrA2)~ZGd4@BZ66ShKvr7tXW^X
zx~sgKW=uaU6|S2#A42X}eD2f0uqiIjEOX~S^5|z<x3Nud1U1I)=8u2r-;8s65=rwD
ztKVyG4MN=S93BWh@Ehb9o}8?^DY%0~?ys*lAj9jNfOFDcB<|c7(5t)?4PxiT$i@vy
zog0)F&1p#`A&f~xaGGzk7ox376yd6SZ8-W*0C0=k7z8X=;9$|nyNd~ody0~VMVCo=
zB|Dt_3A;3d`EVjq+*+KfvK%V-oVhSJGjqAyo3bk@Rs6O|05>0t7gg#2Nq6*onaAC9
zPHACzfv$?J$8VL@(yKRGjE5T4s63zKDtU~9>$t|7dqDiM4Prz$*bBWXKD7j;kNhU{
zK`%%w2F($tgn2GRr)<)YnrEwr^-?1w0cp3VJ0tq*+_;pIWeJnZFrD{ProFDivHCa%
zF_J3J<0?GfErJ01hy!ksdB+HsYjj0BzwwXHvdK7L-tQu>L+Oor*n@b{=2$B0x0l_R
zEt*kqR~c;nfga7G@2sHO+(eh#U4sTKbPirVrEvE|yKV4D-pKcS)M24rb%9H7*80(c
zn?l~NRAmOAMlB3TfZmWuPbZ&#icR-vU|)*jzEKEu(>{c$Tag5rL+yA?_y*t+rS$Z)
z$WhbkBD-_qz@AB^K92u`I@E@amhoWt4S_b&PdH?9nEO{#t<3loAX&nFlb&B=2C<U@
zNs{M9s6>4Jh8v1InbY*!yXjf55C5XX!hDa^B_5#-yn3kh+7Mr~xd<E+{%k7K)Tizl
zS(FAQ4$Ygc>ds!BN9DRP#ofB{mE!tDn5<p>uZhEH^DJOb5whr!n`VR-Q`S5o!ggPI
zNQ~zDdqIK;IDM&L&6e!|ktd(MS6Os;w2TqyvCg8a@6Lq;XfN=)2u6|Po1=14u66-B
zPaJ~6q;2i_l068RU)Mhu{TZ8=X+v|l1)lbKYH=sPJM>pVzxVXYYq{z<b{|TQk)d-_
z8N?gsO0RJ~sgqjlr14ct^FFZ8-oI<23Igdi9Nt)2&NI?@b-F{g`{AE9qFX@iebyme
zCMIv-)S$2OO$9(4T{(E^W&gR8Lw(eXZTt_C-p)x+|HkZOnCcS)Vk4ASRC{s5PEBe<
z-Gk+r#QZ?5<J)MKT5TbiG<PKihB-J;3!>#j75?X@r7Ngybp>QeL!;mNEUI`#3-*z@
zu<}45komU%S|XZ$mx&q?TtfI>`R)m?0Y0%{pb;B}gKI+Z>v6cS=NO_3sdEgtRKw~G
z%FrFjEGh##y2~4)ux?wVdhFbJ!)ZEclC^>iKG>C?qQGXQ0!}8AKZhgge4gzijcCFc
zq>(MWhKVZ>K*kdA7P;dMclnOO)h)I=tkIKOYDeI_PW&ZU%jE@4dOZwzOq=BVMeFtC
zw;5*9uWWeZY+qvO*s+hYrLU4|wV?y*VjP#1y(uT@GkjpC?Tfy$BZUm$JE|YB_SDqk
z%x6r=z_!Z(`0-iPXBnBIb0;z3*Z4InbEwdeyssXLrrWn(3&?+L&DHD(b=kgMn*?V%
z@jNYIC5QOEBGndG4@>bsCG`XVBp6S)x4AVRCBXgYJh(y90>cQ8>j;5AIb|O)jO#J|
z?dYus@w;@ebQXlQ9b{(2Fj(lkbFzSS@*x7f#17&P=bwdGT>`aTNeP+d5j@LW*t)QZ
z@GH;r3&;y%hV{)#!Pym%w0Kn`t$f{5p}UcG=!>eDd=w+T!muAvGIMLjX8l8<bp%GX
zsj6-NnS4lm#XS6adbF78F7gCQC+U6cayVfkvn&Z-Hw*%Dp-z~D>Y=IYP%UyfgLJ8^
zqh{&0>@Oo}Q1d>N>ov5Egl_!?C_79_ph+Swb+9XPRLcu6)rribW^r8q(hVk-C9T<g
zF$PtO!>2`_F^cL<&)mOQ96ys@4~v%vrf9(?06;_V>BnZ67yk)(eAVi-Fz|*JYPUlV
zEuK9~(0iu=wMbf~laB}#&U`Q1?(u;<QQeT1#r!P2B6FCFf%h{9aO0^4K(xWaY2>g#
zs%=xDr(<Jh*58?(7~^CTrDIDXM{$x_TbFXv-fIBHiS|PwdaIVn$_pZTQqh&rrd?fm
z1C>+&cm;<1#;uX0M}Xr`wv>!~>Hd8Nt7=W8%m0jh>mq_VlHdLm7L#_{w9KsV#;0I<
zW)1tChhM^HuEw-nd>Y~>P4{v3?R=K+9@`MbGoe99Ffa0;s;Vz@EmJ?n*Sf>kdcR-6
z(HDWRe4|jrrmt*yHk6BC_qyy-VgWFH4?vM3Qi8yL)t}1V0ANy-jhX5k$4ITZ7`@9i
zZO|JB35#23bwMbXS)K|3e>)TUI0#3fda6Y-0?VBlu0~bJjr~7@DZC^*#?{2IT*N)V
z&qNh+e10XlH{MtAL&GQ@!nc_08~M=z@clN+q$Y{W0(j!aK?@zmd(_r00|xb8XNacD
zskf)PN~6H}hNd-GUM(doF63kT`Amt*M=*(YV0xgbJay$Ih{y_-9sR7fe2bS7IFk5|
z@Rfd+FVIwfNEeE!@y2GswogrKx=Ha9Q5)DC38Cae5?2AxEmC@vSsWLJcm_l5n~J-K
z#8Sf@&vn?rJb)0^!M<2L@AHH+>yr5W%ln-rPG}Kh5Dr6Ch)U@OF|ztNxU$FmT^u$!
zp}OHWoy;5Fg9Lmj#Jo}eIvT~>-Y-JtE~w)UJ0TO-uSec2F|B`-0E+3jFz}1KULg0{
mu7sBx+e11~5LdjC(tBcgVqNM12k7w9H{lW>m>kxn=Hd-p6z2B;

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v
new file mode 100644
index 0000000000000000000000000000000000000000..7a5ac7ec582ac585d8341917f7d608842fc63daa
GIT binary patch
literal 12328
zcmV+@FxStE6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkF4ML9#_z8}R;ki~ExCeVK4Tg(?
zuT4;j$KBRN=G*G$2_DO^^OPinepB_dAC4`5J0y5h6`x?^%18VFRM2e3aRpd{Z#{Q3
zkou5h5+XbKEtSfy^oqeGVWgMdf%MU|dGrUmN5ce;A8P|W0Q}<i9jN@C8L(LOpUq`7
zu3$f?ilRJX0wd=ACmgnzU6qS5mwHCyVlFX~EDHamVL$?<(t)`|=cK8rut#J#`7xNH
zzU8X?H;J=K%O>zXVRv-&g9L318{%)JuH0WQ>(4v?vKorxnw3hHgiNAmXPw{YS1V_V
zoFJS#(|a{fUq}Tp^-S@#T4L!!K1pD_=w`AV)nZz;V&Zf>!98|j!iAJ+Y8Ts_+KOjF
z6$%*H!4B@<2}3GBcL=DPWF2mYKqB9G$yhg@f*88r!ab?Xs8C$0&)wIqLv>N_?%ErH
z&$}r$wR5*4^Z%AYPVn;bU-gRrVDcAx!rp?>5NG;kP81kgd-0tf_%VF#T^;bZCjEhP
zXjF2`A)8A6F`(&~41b0!TA;f{y*~oU?cE&iK8neYd~tX8DZkrKAW?xl0zHCP0X_(6
zUt;t($z9lxXFwCO&E*gm8-1j-UD_t5U6WfRw9S9Jak8aCBMNA$-$_5nen+7aNg0)a
z;bXhRTM9&ugopZx&Xw<}PpIzbz@$62dlvR**o^C2C=w7i?!{V2-_D0IZH{J;78P3P
zG@mI4dThlY|9_fmXPbhUaT>84E$Di=T*1N=Dy&1queHS~C781T4-~5F?DOvv=D>Oe
zKcyv!s0y}_ud|FODQVl2SnFWO+iVIR9tFq!nq^F}SUlAvOA|DD5An<kApq0dKKE+Z
z{y(_R{&k;_ubo|B9WiNtT4%dq9g1VU6_dBtmD1ih{LJC+WFA5B6eKXpS73(9V0OLA
z4e{ncC$vr#H63~^%Q^Dv4(OjG<iia?@C5$xWR8w7E+4c`3N3UHsLo&*wG)<Qo#}9^
zjyU@E{t6w#J+3DSQy(<#y;@Jw3qD6U_LT=3ziWNZg1;1c-N*!J!v@u-O&wjF!56&i
zWP!G8Qql_UeQ-|oNuZVvR!ZV>iF8hvN8`hTZT5CcM%CIyNkQZNdQByoM`kd$i9t4o
zNJPL<%rrxk*V{&h%j`(X-C-$bc&4RXKVe!U{q(Jg=tS-{7_Cw#vNO<D!v_C%9Ce6N
zHv<>!{ze~m`or*>Bgz6a>VOf8q$;l_#t}Apvi8XYGmXYXT=W${LB^k8i((}nnjTAr
z-hob-JN&PjMJq<pr@lcpuDLW=Vyih(|0=ZhSJSKIhH`wLpEU|(qZ~?`)p~UYAtEvk
z5P#cuy}Zh?&q3WXGe^*fIE{IhdBaVkbTMS{NN?PB^D@T{w^GzP!@Q<Lxc@3iH9=J}
zT)$8n2Vf9iP&*gD{x<NQYtp<M>GIG-gq^Ki^&F&sN;AWPd7^TYsfY2Ek8Y<9mHTY=
zPsmr;*Q1cN@PU8;+U(aoQI%OD)*X%F(LHAILl{Z&CpD*`GaUPPm#pdb6YYObGU4e;
zR3Dt;ad)XbuJk*hR)NF-IM<f69G!~z_526@N3(V)&W9GZM@4hxd$$G|L_}b1les(K
z_V(bN<x`ytrMG~GECiP_g_^wu*^7PJwbulg4{ZNBlq<gIH4NW9s`{1fJ|t62Ie@z!
z&qez7w;FAdtB|1H(6S|BuLbTnbVxGpQ?dYYREBk2))^N$LB7tHiQH6fs$<lFnA0o$
zD)FYj9w(@2EEKY?opqUJQyV{`uNV${Kg@$>NQIO2B6Eablr`>FJa%O=$e;%o3x%Ew
zTy>?5eXRPS`OejNJnk4$wVE@aPKUfd83D<^xp35ez8tGdxF6Ei+;7-_;I$<tMKN(D
zyVS=X`@VRQVY>+Q*m5BBP^VCl7WZ^oe2LGpkxOcEHiEvR+}4QQIF3w`mAckwgfJZQ
zIpot07tVcXfmXC;lFytt$^};&rpS$0ZzgV}IJ8cCQpeB5YG)gC$ZWI&qHr9Bj1{>N
zA3orf-O(ei{7X_F%-$jYh5o4K9UZ4FIdCra(}yp^AG7S+3+i*7l74e{wJ`G?yN0Wo
zlUdYBmcbOl%=#-Y^X0NIz$8FHKC2A~k%W&96$`I5KA`>7sG!i_!H@xH?BT_LNN^yh
zV!n1nw4S@md831L<74HAr7oacQfQx;g_-|17Kt1p#tB!_mpr1CE`YE1Wz$uU^m`mu
zcZ2LHmvKSM7%cBxP}!--`5LO35WJ8N*j&NgnGDYt2Rk{NKKyB6a7|73sJwP-bE~h(
zZ476q&A`x-UJ?t~N;0I@%#VcFHI0FZao9HSpjdUpsObhhB^Eqb6Y-Q=MIU~HT-MkB
z@FR2!C}9VABjlOEU$=UrB<-<r3Tj`{)j6m8Z?x%K`9PQCeWwg$Jwe%ICCV#Cpt-W5
zwQNs=znLgeiM4e5qiqDxD@^@ZW3~19Gf>`Mj4>z?*RKsOS7#a_5A`^-Gn6TEWY)S$
z&lKMxt^8GVJkUv_0T|2K5xI==UV=JgQ}1AxZxcu>vo(5ek}ThD$^a0(M)=<@Ap|xy
zmR3h#3&pNk*7u>N+V~owL_QrJ<P1VqH}xD{yokYx2Myw_OmQiKmZ@)sM0*7p9#TSN
z*$<__16`OJ#*mhNDRc?g_V(+@R46LM%jad>95}khxRDsv+I?u5C2iAIcoehk97>_J
zu@QO>!dQ^lgDfsqd^@3xaY@AG1SenXY)!~P@gZ80NLIjm2z;B*Tia8S&ib)isx-l;
z;N5X(v@(0g7eZsy2jO&7<|=7lRvKKh61|4;4gyb;r&->R88JY-2ek!n6`Kv_m8u3e
zQo^|z*3y%Y2N2*)*m|lLlj>9@gRlKfy1>a`po4B}g%giGHiQB5zAzqGYPvzPg;ml)
zqrSw_<mv^?eFlZ;&2hA0rLSWXSjZHCK2F41E#qlEEj}VbGa_0zQK{h3^Q|n?y@joW
zGen5hLom`ggDj0TA;D$I)C{jPlqJpDxH#chnWzipl(sEOy$E5z`<^Ncr*uc3gmwv+
zhFkH&=4PgO2`2cg2BcymQ{ZB~Db^B<zcKBs<zBpy1K0X6+@a%+14{CC#YnB~JF;nE
zy#Hm9`*ZG<cN6ZJAt}1pKqg!$`IE`qj0fghU@qlkPeukvnE3o=x#=ZH^pl=;Y68zE
zNb@laY5CM$4O7{k9rc@uh46E6&Nm~I@g)bWj#IO_f3ksHFK;rJmes}j)aC?<u>SMl
ze$w@WELE}<bE#GVlKk;c2PNrd?o((4vy^-z#qIs*(9GD}M5f!BMX!S!38ZO6y(buJ
z&he_uo9YYq-v4&_m#+}ly_3LKtP>Gtw4+nk2-r~h50I(e2~IrGLev|&NPJI0<o>q!
z%UPnPvJ_ABw3%c;SZ?YkSWEdjx4h~<>Lo>BNA@?{d*E=z37pf&q2~N(G6C$+T#&<D
znnwodq}riL&Yq8mWbMxkc}V+*0BfAU@GiZiHkaK0oDy<r)$+j(m^H3H0~3Mm)kqZ%
z3Jj;Cr}t*g_7}32;kJ3K3SbIsm_I5}WD$Lj!X9!zr`B4x-Dj3$$1_ayt7K7pFXn;~
zxPlTAV+2lrFCZEfraeim4a`J)<KO<mgU?}GLug+8!$nXwA+X5lPMQvx6n1wMsr{4r
z+@}#D&?A$n<6-vNc=zJ$0d^rD{tSjHu6BcN{&08=E@hI>V0rd=R)DdD{%pp~1v|Ma
zy26Ae{-p1>2ZnynR19uSOW^-_EIh@+LmW3PP4brMdfQ0v!VA0j`b3es<7qt80Uzkh
zL2%D$37=m?s72LNTiU-Ca+8P~E4b@+(~<Q}ta>B;n>Y|rRfej-XT{DgYM@myy)+N+
ztx6WdWiKyExQ+#~z1KU+-rBr2`k*|IUoJ@0sfIqfq}9%N9>Bv<5IBmj&(<eXxqX^4
zj^Murz4(tEaB4BG#th3ZbZ&3?a;^%A>sk8Dwq#$mkQ34lxkf4&pmLHEUM-gzm(EM9
zk%^36Wt4=JQF?5}*pTrjmBGJS8C!RF+%^8#V>u(0=b`YITpurrl!3POBn*$b-&r*p
zSg9yY7kWvXLqF*%iQyFI)J13D0kB)UjvA62bls`RG$Y(eVmB~Z28Gyv%(sU;tvhA+
zW#^oFQ$Ig(Xwbe*m!G@g5h<G&M~g$UQV}R`)j>?stvT44LCANUe|?i#)+rT$Ot5xi
zjsXhJNT(McAt7eY#(d_dH1f%*n2!(jFMZv}a0=;Kv&i%!^8RCz3Pddr%-2`vyS%=^
zcS0+C3pa-2%*aQ7Z@~Pu>NN{B4RVdv=dUQs&F(T;WY4mLMRNLGqF@G&$B*j09d9fL
zb6V-5hTg99hV-?hfk1lSC1@y}6MPWsC*?6Jn;!vbC-1dl-46-<_zk>F>=~tAou+?Z
zTAl`y?>8}Vu}OV)_FxeGfG=V316k<N6>F#s7QQP$s(`f37-9wp)rG0VeYi!#SY=3J
zU$E>J2EVpOWZGH^zg)-8t@j*rNTO(593fmE4TlbZZD(n(;SA%Zrpr|Le3F@~6A}2e
zW93Gr0+i%Fk;;L!`va-wp7T4e5@Y1P%+i8srQLv-@?8!=kcjkRC$ak>Ws7#WI)8@V
zVEB$*Rzy@JCYS0K(&TH!<W;Z(Au#oETc*rUKB?8^L>_hQ=Z_Su;~?Q`L)kB%0Fh3h
zmrDmx{xgUr+b1<uIj*#fAj^0KuN@9l0LZ5)F0;_t@6CW9r9Jv}+&ZSqmZvzTMA5jB
zCWakBUQN2&q6=BE4QS|Mq)0;*YsBiP{43m{FHQxy$qaiBOT>38dtMj9ro^~z66yD5
zi~+zu4YQepi+u0}Pr;rNE|=fVhP3Zwu>Ylpd+F5mpcC3z7I@v<K?LG9z6$1|D9hDP
zzE}<m(ZBhejI7t@NP}IVphKrqOP2I$<k@n|hDXZB2zBG0i+wINZ9>%{aRh9Y*_Oi+
zIaP=+14=n}NC#&p>2bh@)Q`?wTg8*^r1q!zlBk9?`R{_Cj#?O|*`|HZ?A8!i_4XdX
zn$A@fmc{C@Dr=~hcD+-{thn2g4#i&lF@HbF+|U6^*cj}X%CH*JCY!Wbn5ORQbY$ve
zAN#AK&pO*B$68)Yfmz@|NNG%fMRoh!pW<Ash;mz%;fzrG-_fv%fv(mRMj4SFYmJOE
z_9fXiO-sVWa*CO&O_dwjA!7CU<KAQ1?*_iXkM4JIs(4KU=?n_hlaN0y14<YhWX~BE
zbi|s{5{kK~uf!~w7xm{ukxKH7Q%yXmT|U0MC(Z$v>#+^Piw)SVU;$R~p@s)ax_YLX
zO-fZak+%TvbWS3VEjSbN14dTvB`7I`#SP0m72hop$FFe+sCj*QzRDw4LSY=dxjOQE
zX);6FSzWwUH%}<TX}FzLgjgi+RR`%v>#qOZP}t-^L%e&<#V%I9tvkIs2u#fzen&d7
ziHvx5cl+ROtn&}IiEvJ7fjN{YX}F6_V{V#I_W(@zV1dro$$v%5p$s^7_((AGZpt8g
zh1J${%>urkxW8`tH$=~n<S>*u!=Qwz%0X(ET6YeDC=POO75Q-@nFXJG<Pa*y&AW*&
zk!~Q?^Yzf=cqCe?mfVb8c``}gjSR(BLJgCqC(Y*K<ee_;QuK9V96*i426w395YZxD
z#4=9^@u);ka1DJXZr7(r0yuy+WTCJ^8@nhoR#ZGX5f%GgLV1lVfOSQI_T`b2^q|BE
zMG4Ci`t+r0aB@Z#Nilt=Jj#An-q%j$_(0QdH2pO*`7SPB-qG&ch!B16H>UG_TTR-L
zt2TU4QV#qwmFpP5r0Sb=K^MEjh?52kCrm0}^0F5=-AYoOtU-51aXB5&sS!d*fHqGk
z=S+WMxd9qpqZ2F;6@x~y{E(y?M+(TXk(0M%$!lRr$F9&gVP$G}Hbp2m4u`z!aGS3D
z=<hMK9|1NDm9{l(aA8m%475U1K(q8>hCR%YplbOhSr%`pyaTza$yOygc<maYuJGlC
z{Xv&sm;lqe7d(<GY2rkknvRyzqM||TK~3j09ylX8E*>BaqklxF3~EYIwx6408DX5I
z5d16!YdBS=UvQ$G`Af4QhiH1IU_1$%U|})u=xh|hB!->l3PFr)iAV=g8W^WR1r@z!
zmojFA9gANLMdS#thLH|bojHMSkyH&l)t{>yBZ{H*>MrluJ&zB=Tf(<$V<RHa2Dd8i
z7dRJrRLAha(>>ubB@vLh7>k9L>NHTJ#7Lf#k6rnKUEl4?4xb1y{VK{jE?C{mb<3)l
zrsxmGDF3XR_sbWYHE!O>>uZW6!S0JYowS7jg^kt16lW+ysMq#`(eQ~y;_okXpEE}M
z&#z$wumH}X+q;FcGi*kkGrNJHi7?x#2|bWv+ZFaAzXw_*B=rMKW#~3Pnh!bi#64Wl
zl=3w!eLuZ#u-ZJY)`7`j-omp?is*R`_+~M%>h;b8_C7Q6z(Q8C9ZFGIl@$*I5UpeT
zUYw}pnlxIoNuu>!tuY4>PGvkjg!)%pkKg=_tCJDc{d$pZ_qTh1gBAFf*H#2hgmg~8
zuKEPj(W%tCH=At4di^IG5g08x4qaoQae=h5K3dZc=HCF694_zA?>3kGG`;NmnsJDH
zf-toBqg}s6LZ~?%!R;ll?Jbn95{ZF^%LtMDe;<F05>$*5A?#!t{ged2kZcd+{?BQ>
z6*S8%TauZLN*F^~rB6!Es6Goce5un!2&s{Kq)Xv{D9R+gCOAhFBf4h_5}P7d<_t*D
zsS7&Mfu4YE*BSQ{re|_#b<W+P>FC|jA6wNg6pYx$uprn;tDXj`L1aNkM$)#E_H;5Y
zSWZEusHME4R8$SPUO%ATKze_abxFQ%IiB<BZKd8;U>e4sjx!A^nq+ZQd-@P0&}qfY
z*K}j*AlfeEH%EN!2{ABevFCE7<#EAxd?372IIorIaSd2zcTRvHG0|7rRG8raikIgq
zi)cg~|1kko)EPzJz?(1RrHAzMaq>pzi0OZmO8imOOPrK8l94yNX_{WlEMD_`cg?0^
zdLLSSm@u@qRKWia%?D!Jc*L4*wpmC5^hk^L6?fn`G(PIac`-fjM7r|^(+Z_n>$FOt
z_XC9&fZ$m>P@~`>jp~8oVCBzgq1-^PAD&#-42;QSNhw>LKwNTK2#eVfSxFs>{VZfT
z-l&t;A+C{KD^WWLYzsdOsyUArOPCjqf}J+Qjbjo^gt75rfR0VUe#yCBUh<l&Uv6%#
zFTSTG&B>H)>@~$r=PVB0TZu+UMaOB4*DV(JQK`KdXT3}>f0}Eu2^uC|KX!_2Twqov
zi;YIREhAZk3`3<z%+I`{=%;eSiC4?W4<aTSK3f1Cx*W`2gmoR;YERGu{A6jg+g<xD
z7jU&twJ5(p&aST=j!+^dgS$M{y>I9T*r*5>qt^$UYoilrYC??fnT>AB&!Y`F_a|W+
z7&VMcw9Biq=NE~m^n;fd%UJ$^x&Kb9^|V1}|B8NW2ypSI<QM}J;1X4ck<^I6ux!FK
z>(=$kgS&>a-*#Mx*ZFYQITn05S_BH%mRRit;`5a$M1vyoK%1z383+?f!yM<(voZjh
zlU~H$E#XQ9HP?rOk@N0F^V@ZWmcop9LHltyRlZ(BNvLeR+3qH{5@EJ!S7F#Nnx0X%
zaLme4FV*KCW2GK(qcC3!KV#z*5h5)s3D@iTt-JQl+n_g_w)A8jX&H=D+%Ucnh%xax
zR<_cAhRAz$>_WdxuLua>*7k^*_$4UM-CzAVC}F_`ZYXzaXjsCI%^pa_Q}(!++5n?&
zB7!)Acq>vVsIVQO&V1gt{M@uWxdLOhzU~SON>>^bN6TFep$x}gq7|x1y+(qhdwP;P
zF!H&_-0R3VmoBkVDb4JKQi;1GkzNp(0FWQRsr^1`)$KgHv}KDb*=h0mx4elLbK4LO
z`I4OyZy)q0pRL!Hcvv5)ue-z{-x(n>9E9w#-j7Su{+5DjUmdM(Z>c!?VXx%V3BAkw
z>1@5(yeoQC)v*qflS;lWNO*~TpMdMFs}PfDn4Ek>{pG;)-&2Mso`9N{1u<C#UGemt
z`#utemJIfdzb3DKN>&^5UF*h(^N(w!0LuN#Yb7{T0nJOS9A8d{1u+y6KtGj(NR+C^
zlPgnbH!>W-O49M7Ui-v`;=8V|{V3H0{vMg_S6gc+!lAdsPRHkWUb^|HrwvX9lyBXN
zOw7Gaaz66nN#^4@Vvfw#E!!_BtXJK{=&sx&G13eo!?xVZ{m!M(YDU~V>Q!grI6D<h
zgspR1B6A%_ia~?ml5*N}bUYzXU<XG<wvuXkkYWL4W4kPo5hb_6A@sP<(H2DPos@p3
zLqp9qH`LrXRY<sx*9x)K9rwQqH6rXUr?N(d%jU-CT*B__0ES+GJ3is}_WoLyz7$nV
zAO{^LJ~K+lV>Jwg*3Y=~Zi6&6e*SeG$;ABqTXajTQHN-!`)eK^-@gE0^PX?RK^Y#-
z8X+2qy5L@!S!^NyLIWEr)}0+T;SEe8=N{cV*>c~c_RnMsAKt|}%qNTze_Xas4kLbI
z&`ov*Te5Ur!M7q7ECDa(Sfo2GCCrHoXBS=?@~>LmcNl*Lv%kMdv4YZ*uz`+<iQTc~
zi9pZ86YnGsdfEj6BBXfOL{_x3-~%jt5c71Ho}U5dQNC~i`LL;MO3L=e%qRd1m)=EC
z6y?HdJ3o46X&gO}O&&DJXaHvO17oR?)I1r7nA>^bmhMZXD8qY#YQUTy()COV@+)ih
zkBvga6X#`sWUDG4SVR%q#rDska8jIBzZ`I9nS9;D(8|M>r*Dx3BhrmS%ZV=iPb0l?
zpbmUA<56_bOer-CfOt_cY-i{@f$<-okouw(Hf8hQSMRz_&=L%C`DQhW^gWKMVte_P
zp@Q=$rx3-a%cyVuRksusXfKe|qNW=|a2M?jro@9bXgf!VVD;Cs%~+==xv-Y0@~VkG
z_OJ&nnb`u5R)^GiM62LvR;pcse~r@(GQ|df+1!+-r%KzRkedc1ya<wXrBz1xAe-cG
z=qJd0l@Mga_?|npxaw82+~8XZ*DQ5iVw;sUk_N$#hFY{st$@U`cWTWlV{lBDB_S*I
z3xs4qHj$38buk$>Fa8~xCOkVz#cA~-(|R9DhdWpC9P;A57W%P1{*q#8{Y!PGhbcAE
za73qZfaj*WO_~A>q1VI)Nm-nNf6I00-n01tf;zOY$V4@eX}DE&&8)LG_j~J`wJkp;
z1r7zujS$}$V;QTFn<iY>&p5bd;G}KYenzJ~?9YAHVYKQoiSbA~!OLODL(@}&mPkWr
zzG}4sKJp6hmw8r1)z<V9ou^MM3O2f;PWD0gyFS?m?Ts#Spu({H@heZgE(WdUUCCr=
z_X<6f2=*lmD#AenEGGTkL}WP8rZ5yDF`6d5%sAUumhE94Kga#{h|<BCV(c3j__|aI
z)DYK5{WG)1_L^D750dGrC56#3Gq9f-&=Zh}`Cz#)U|25j4;?N_(K%i0A{&dS^lhz^
z2d#2-n~f$ccJOJ+Yo8f{-Z>|$VDk9z>8}XrFoVCR8O{0=k&byL2YsdTn6plvS->@N
zkr&8)FZs51uMRRz)VWoyVFXk6^(qcWXwlxK0CJcYd45h4m#DD)8OS^A-H1E<Sipo3
z$VU1BQk9vv)g3jqt_#W<Aj7$_u;tORy9Of*gdU(4_~&t|2rfTsT2f`e&O0pZ!o&e;
z@L~&WRFv9Z<{(94Wcg5&Hmx;)VEY@a<i{Vps$#%K``T11QHrtEE65Sw_ISanz{Jg9
z2KQNWaU&!<w{-v$@Jii8PC87Qx|9l*CG3mlyu8h4=$@;_wuMt_M(Q<-b13ms2c)fd
zU;_ZKu=XwknYX%PPEfR7HMR|W1jf*{^m@uakmlyRDa~uogZ<~0K3%P2#i04Rs^eMD
z21P^wSn>fly#(BazKqM$Ms<xus!E4hrwRN9WN@M!VJ$RHlZ@@``Ts!Y@NxAL5#zRb
zH8WUMI^Jjwl>H4j```5*Rn8zg0p~kts6ke=TqKKactGNQS+hV27mO>GDydPaY9tV<
zBB)R>EC(T%k<7ro46{#Csg^#bEtg>kV_s1*hI&D{N<ic0nPd4GhKlpsjh~WR;R-@`
zeUAOMqTSeV?#)?>oigHKS1s>SGHaRIlmo+~6f)$&f#~$bs@(v(eIhmcJe;E6EeoUA
z_3+u(va?T#1BNWEEiNxCw?{ws%NX;-)3<<}&?<4T#i<!3=j{AZ=G@Pj$>>T1$QC{h
zl2vX*JqB5>@|Nf^#GMcC>kTMIt@*UPtDJjGzW~yz<&n-t=gKaFPwuw?-Ml`ATcPS%
zmVRM*2ld6}-yOZfOTEKWKKzO-K3JKt;YSQ=etH}W?f4e(rAmSE|AnOxcw8*|5VTpn
zZ5@g8q%Uh-C<iW9Fw@D3SUnQVy4-9wuyOqN-473@iX1-5df;+1g9lX-kU`bIJ>0c`
z9uDoQNts?suc3|DYz=vF&8B*E<hYD(qmuo_M`vLX8}>bGD2zI@(nRR)b%iA}e$03K
z#~qEQPs7KyR}8vJSIRRH<+?)Oz69i_v!q}NpOs6zKWrH`9lhFvBD*~;O)x1PwLUd=
zakIMFkp?r%09Jxq1gRMi{`a@*3Q)F~*4*5g1lNw4f;Yt*|9vWR#ZDmA%IwLn7#uaR
z(j(M(bUarW)>+=}Py?r+V|ZUBPy+GPB-KwvT`}UyRwpDqs>FB94W^pkxpqZC1!M@n
zkk<!NqJ7*aJ7C7CMV`fMGz=B8f@#Zoyt0Dhl?>}w4j4dHqtsNwFl*j*E=53I$i)c(
z`x#V%$)o9P(mVDM&Y(LM_+1LnZ|uvxs{A^^zBd`bXt5+cXBa&pPx(g7gXzDH%kWh*
zGQ%I}bvA<(QT(aH%FLe3r69Q}=n%KLGTsyQyZGPc>|os6z8%oYE~oI?@2!?`pzs?~
zU9wM`Sz+FQbW0B7&2+(Ms-`-Ut79T1VZR+5*eS|evg<uU2ZIni<rucRn<gq66}S=D
zX^`r7(cQa$AXu-9p^Xh_4A*<e^HN2^MMC<Yk6@)&wqjOfOK$Bc<vwLHV3DO?mp&du
za*_cmXCJRR&aii>`*bjIXuiw<&e4@13)-WP^kiEgSKWpor4Ix~B~#P=-((Q#@H98f
zywHZsHd6@r@=sF5S#Qpba4}2vUmS@!-F^?jC8*0hq_##K!S4r_!_B7%-K~R^chhke
zp<-i8Q3iuwf+VUvwX-W77rwQA;_iIwVP3l;`a#wJ%*0O1bktJXR*-sS?dH7_O^wpl
zqTt7TRd+?zBtDL+O#a?GZG&k1HdMAHA$^H;(-AvmmR3#-k$*NtG+cujvq2t=IU!$y
z@m<R*1Y4r;tr+k^Y&1Q`l@A7J_K)#!g~YYc&Sj-CuTVO5-ym+>G}~1X^O0JnrjE6i
z@SQdu%`V)7124Xe1*>QUB=Zi5a9AjWd|Xa!#+)yq{;w+LCzo*VkiYG~%oUn`nBE@I
z?j|o-1jPZ58fz^Hr}7-iH$Y45Q$|;DmdVuF819+{M1z5x=0r5rSSWto0}qI4Y|DTc
z&TG9a>+PF=10l92>lI{|%Jv2|g2WP*7Luu2w!gs5c4bZ!+<&+UN`2~^#9#V@9ed~L
zh|!<OkjRi!^eZIBJe-&JD%HKu$=4={(5wrKes;Nd>MiaqPm?hv9m8n=LfmDp@<d{u
z`$O4f=!Fk}mH{(W_r0Ei`nxSn2k$5jJ#)X(lkabr*5EF%biUqF=Gc*1+#{1FUXD1u
z)}-0OO0XxfEiou<Fri^cS_6<N6sp?86cjuJC_D6HP^`ccn{)$xXqQaEuqYmR<xQHZ
z<qn&1q7sA?-xI8ceXgoopvVV6Gta{rxL9E4ylClhW%Gx60+DeYvbHg(V*AH(A_w!c
zJ$3<-XM?{jGsS{cY|r_G>Mq;zODFfk^GRH(^CvxzLs#^rhnXka!W7a$QC@>+u>KkJ
zBcv@LNY7MX=x#Ys%>PktML;xg#G(FTjtL?odBLcqVxXl>WU&3H5@;uL{j+`JIkc(W
zMqL1GbV{^QfhG;A@l}>s=!ptAHGTTeC7sJj=W}RGJ*}x?DD=SB(;9+$0NAH48)58W
zmB~)T@|7ofu<zt+meGHBA=VW^lRY5c>VntIV4%t<>7p4%(%_+=rNq?QQzvKAj>a)l
z(W9u@UAkwF6HV4<><=@e#s3lGnubfpvNp=~M9XitUx4Sq>L%fd<gWQ!J=H1oxG!k#
zgnH?_o*XG~h&ESlGR&upJ4G`Y;Kt;ARS%gXN}AyL>k5cM$3jwh`NU+&MMmXD9}udT
zJcJi=fY;SH8Y+Y2zYw;h9B=sF=PH3K1!kYw4gU4XVgP{Ul)&KfSfv_RcBrJT+kui7
znF`&W9&a^5!P7c>P;qh33}J5ZC4F7D+<|?)s=^4|oIf*h9HSVhlmEpftgacHv~x`%
z-`y8&^i^yj`g>V*F<3r9rTEzaD@&wL4>aN^wwb_0nN6(@ai2WJI(i=MOHK`~ov0)6
z=Io64m|J-)=vE=eHS|-4#oe3jj1zT~EAX5)l^iMBy@HcQ1$nv?d;3}*ezd+hbYPm9
zL%30JJGs=zPu5(>;~DZi(dsXX8+*mYgRvxlr{=Q!6Ua9jjtJmbFIsazZhHgJ#6TJC
z&wGW?pHhjPxTm|%Krbr{$3L$(vv91Ex<=9|vJk#XKI~T3N?dtg_h^RTD#$RkIr{78
z@ylk*1yi<QTop7g-2JhPI-8vSE+sT62mfSBlWv1$%M?i>DUye;5e0_MGQVoE7yH)H
z=^m3q1N3MNxBqcGeeRmLQ6GMvBx>_lMNS~HC;uH1ysWM!5O!erPfE(p3ms#sMzsoF
zOiO@Td@A-=*Vv0mM}G{QeMOjkTUTs9ym@Ue-=A#h0CUKJYLZE$Sg#P_J`>#CV4?(0
zqGsh$#L95_&~4J0hvs=&FpSfWouauGr=RvlhgTO*ag**S`RfIQg^l`{uzHTlq<4RE
zJSZtte|&BcwTDTyNollQFzK?!G1kSf2rwxJY0_H~(CXY;Yx@Ma94H87Wn%3xx*nQq
z)AutU2iZQiCSL`2(P^}UlpC~v@j=I`%r|_p=PCc0a1FcS^Vk*tz{uOLJJJSVOelbk
zVS?Dq2YEPQ4K-0c#ixe0Z4nQ0okr|?Y>#}T?!pa*r6&#33&A$QW)F}U2kz*wf9Qu#
z$VWP6iH>iFcv6L8Y{Y2?0pn?o=sEH)u%IO4Uh}$TA^9+&!b#ohPr$jM8@ceiY<WlL
z)H(7`KB1)F&Ao}7Wzu{Exx1j;8d=s9wjA95x*C1}4sgkEs4@X@20N;*SILgBFF4qp
z2#Klr?dPKph~Y!^ab}@cBz3NJ1{n(IP7d+dG3o4QisW_ho}6a(1VNuD)qxy~k0R4x
zB7%3&QTw0HJUR}9oZp~0s7Va^oxW2`oaeGC4JScP%NOu2kzx>;8OD$jb*l~zZm$%K
zVvhic67SL&F)KyBnfj?~LsT>b)=bEmXb`aG{mf!V+yu4q(pxv2#!{)b1j%WuJ(LbH
zrCL}1l6%otpL9nCSx9a_bL?Y^C`?=i5h_!(2UPq9ZVqS2Q5oEaHojECZwV@;uI4Vh
z{F~>&vQSHtM+ntoUsI92Tb0pw#CK8=WNQ)R0yQ`@SL7~#mN7H%NKEpikr0O-s*S}4
zKoYw{deaHFB>O3u*uN>)*MvzeNcqpXGBIXM-Fxs)rW}|52sCP|62ibhm%1am5-Dm1
zPx#*4XCVAVPTm(9*96F_RE$GP>YHI)>j%g@7VtNKAp(s2LSIpG3_d_>yHV55$nG=$
z_w4&-W~QtRJpm8U4yO+^8eivvji*%B2#GG(OoYZ3UGLgH8E|~|`cn-Vyr_rz4`E04
zF|gRnHmZcYAFe;FH@mV}bAE08&_yx|xsLLdgVx8LnZ4)BRV2l+=>%`g4~De}QUE&y
z-3ExIN!i>Q3W`?in~~0h#va?r44jMM3x*1v<i7}E^V00^rBwHef!R;49{1{Vr=*=6
z45V_Jt^2{Ae8cW1Rz2iDlzT~}lTSr=MiexCr7U4osil;nI<yaTLRF@hdRGQJH_BeJ
zea;k{*i}}?y|e?7BV@8r(WC9jX0jEUzHt}S<Ky4fY!&nXpwz;VaO2E_eq^t`-9=^?
z3NBXs`7Zy#LGnuyD1jVIa2{bL_X3R(ikcit_wxo#@i{~~<*pNr7WnCdHP0vC!D7$b
z@V?F4!QeJtFJ?k=DG>2Ti*&;hcr4ZQ3+8EI4mHf=_l1?6gIQga2Y|A|_h&g8j!c@M
zaB0>k2Zl5wofQJ_4XXW0#(9lPHx}ZSth&f-$nr@Uup@8+wW)E$>Gb-8R6c-$D%MJ@
zmv3&Jiz!a<)&;60N=MN-e-D3_L+*Q9j2K^bxEhURJB$4TayCj{Jyne4Ku$|q*<SpP
zoWjNO5S%_X$Z?0<NI&44)S*hcXl7K137r09Tk)duT-`RupNvKLi9W_d(1+s=L^HxV
zr|^FK#8^E1U(^?7t1OG#ZTV}PF?IeCXkV*+ji<)U)Pav#t;?(CsFax4&^kLo9dmDY
z-QS;inVA!miDE;#J-zMiH8|M=$eyN<LSUWRz+Un*73P<0s0Uzul9Cr;nN+}`#@hpO
zWDgy;$9K?_v03u+9^FERdv4R@6-v0k?FMmyRdJf3x8Mw$-;6a=Z#pE=6{|T?=2zK5
OO{VQn!J%o^NtQ~s;r4U@

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v
new file mode 100644
index 0000000000000000000000000000000000000000..085851a2a4726b08ef867aae25934e500543bb88
GIT binary patch
literal 15344
zcmV<MI}gN*6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkF4ML9#_z8}D%$mayB|w?)q;IRD
zaLl3wM8y#KNM;==(S%;yS(xT#(-fuFwogYl*B54dpA5pdtQnpHoeH&Vf!xWa+@+k=
zXf`0AyhR9=-c_brIj(|@ZJ6+vwyaqlXvUINvDH7UZxmsmFv|&jyd;N1C4`;8U}3JB
z7k%J1X3iO+K`ck;=~gt(A_0YU!r5wf-%dN+2@ek%?20@?{hR}af(6Q0WPdB}a7gsv
z1Ow?QLZhT<9#emgE@DOgSB;r{aj@nVL*;6|Br+}*?j+zYDW#5Y4X171Nt}8pc<sDy
zs}f`#3hE3w(r3|$2kpGj@)99yE?-B|;{R7z8G>x>R@Tm=K@_=JRt{RJuAO|TW+-|Z
zan=yN5Iy(;riH_$oLUSDIiEelMUwKn33t07iXb3l1z24F1;<-;M6I!1r@rOK(IMj4
z=<_mXh|h}-;MR|+8@4$VlMx!>XyX$Kn%<!olVpJDb5tZ<Pq6p%d-a`pZxD+mVPP}s
z(JQ%)$ql67x9=(h<*(?_MI!DL-{%d^t#ja|6Cd~kD#X-Um3KfKU@>?Vd(cpX4d~hd
z9`N6s^80wmASMsdr&Q}sbMwSQmFL{(^NeQ!YdU*hZ<EI_+T8ep3~QrCjJ}hXCQ`RM
zcqDsRJ|QJ77PT(Upd~oaGw3HSuoF_(^;N{T6Sr?gV^cx1_d^{j_c%_JwVSL@NKoly
zGIX|uAcX*~bm&w(kLrXxwu8XEU&cUh-79CQHM~r!)}LtiKSKsx_y$M&30^C<qZ*5z
zat4;Sin&mlr^DVCR=McR;Hr$&2W$E1Bx9zG31`H`>sJFP)8IWE9~k#m{J@&5nK^~N
z`Zu(<q79isz-6+t-hd_+&C=QRU;P_cFcV*aoO%y};F*wV{$NicFu18;Yikos_Kh>-
z=-&(i+Npw(da_K8@G}GbaabyD0URsvpiuO%M_~5OyCO9@dEij;6Rnz=c!|jyar9Fl
zWRxsqJ1mR0CT;8YG~WGK-!vL7LYY<4zdP{;J23Y}ltj-}zSL)Uj^E>o1WWQjYGp}!
z>*`Vd(epUR6`mXXsqk4cd=Mr@$XH0?l9kC{IJoPrmtOMjHS*VFJ`b4d_b!7)mg_vZ
z^QgS~TUd8!gBIUW%Q}Hq9}+XeD)zL$0J5zAhqrY~MqVRVU_O<eJ9vqv4@$|<YmMLM
z&2D_9Bx#_rxpX+DdOCERp=q|H9ZW*sR0?|g?nqA}BhMQ?Dg}!-D)ac}!{U&XCZKc@
z0_L;G>|hvJ^X#w6*82N}epR{Alqok^ECj#lN%BOEP++_2wGdGLK{20Hb$avnjcjZ_
zMdKoT4%3pJ9XG5EFRE*IETZ9!w7S=Y+efn9&s6Z>KMD!qH#a1}K|qADM*kG4Bt`Rs
z&q~epzTi(dygGi2)OZ-QX+Y1`19u&}##L8UQKq44hZBjgU7(nf1IyPN5S-no0oavq
z+2wH5V~gG^xn?^g-q>8QF8|HYgH}xn;E}dkDlClc(f(}<&5~3wPkXGxTGmnLJj2i5
z2ik-!16RHyuZz&mp7iQaqt60YTI&P#{9b$gv5Um0vjeg=?{B)<w_S><ncXOYnc@_&
zS&tF|&%zPRCkvKBM?dV`qK;?K7D7@W)0Nf0a*rPv(g}(c*fk7ZTk7w63UhYRR+(oo
zAUWycPmyg6w>_6YJYwm^wg-YwjoZx4E$$-i`}8OTjH*I`@kxJs$&%;A=Xn}~Tu7kC
znxC}x_~&(i%DB0Io-)ME8l@0}?47;jIrbSL?LND)X7?T>mc%ezyEer*KO)mH_B;7E
zwMCSY!aYQ1LjKb8)F&)k{xM=u%<hYkkg5b<J%r!5POBaN=&#o02**$48=-QB1Y;y@
zwiVQsh+2urtX<>YKT@FNhMt0H_2Q_~nvV!ulX@8gcayn5ZZ4PVcHIYOtD$h|#?p~Y
z*)dT>hV~7SvK^i>qNqvfz=f*sdbog?T1DCWlwCX&6on%uujH#F$eHf~bIn@$zjh9R
zxSao8G+GFXDBGh2@@kvS%{h4Zh6CO^Q0)KYX^E!l|62GSWN`rF_U3XMsS=S!)4tO)
z^hv$d>*?ubla|C?ImfoG`Tix1owPwr49<8tIMaU>hmE}1s91qzX`vS4S>q3K5@+YT
zRks67RJ_dGtpQ2skFukoSAyBvlWaW@Wd07qf@rsZY&bc-ugUWmgv7|hizV`b8iZL^
z+t~d{d14MFqnRJ`bQp;5veHoZYC?m{d(vW*<itM9(`?6jt7WjG6tCD8e^lYo6})*7
zjLbNsC2T&nrQ)@Z8mZ2Fr^|hc$Lz^kN!zNrpQ(ZC`LhkZfo4^-x2>pkE5mZ&rkhN=
zo<2hLw4Y8=!r>fhR5ft~5%vPqf$K6lirV(kS7NhFVA+9La7EZvDd*B|A<BUU&iej=
zPzA!WHu%$lh{HCi9Yb(p3p1FI3o4-!zB68uUs-{nXY$?Au(CNsvz`Wj()^MRxFi1C
z2knORLkyr3pc2&{h*e3JcTB6DK_f#KKk_WD<Iy(aC@w@?p&^}cTBg)EY1Oo4BhI%@
zX|g{~gGw{-GQzQA2B>l8;CD+gJWuFDTrb`ZJ*yvCF>FWWj%D;5<rW%|IJVL@B}C5q
zgzTjSB|~CPN@QIW)xFay`Sw6<c9jx0EZ;4D&&z&uFmwo}e2C3R`F84}BG6kI-hv6)
zVvA1bYOJKpOKXbKvN^5KtfN087;k0*MEi7^hg7UWhZ)Sb3j%GkhXOETwn-YX#TNIK
zdI3Uz3GT)NqN?~AZCU~=CO8*g){TZ1-2x{0KtPq)Zs5$d3Q?wP7LV><wOS<&QWpk^
zrJQake;gm)@b%aswIN6Zm0L2s=&$#Pe@$Gc7c%H0e-e^U%b`*1D@B_J3(BHXpo`fP
zN#eYX<`M4r^2J$I5>+1giZ|CMp4mS-(B`N47GG*72LpMR2Sis|4VpcB4K@F8hLZvS
zcC=jcu;&Gk6;iq2Ias~Zce|X%Lk^be3y=yvQ^g8=R{c_C&VlJJ(SlOJ11ortL6jo4
z%|iChT-^Lh1CuuB<$gq=3UG{(sn1~opCM&q0hh$4fFX1@?*q)GDC>Gtesqn?Tv9(q
z2ee`Eq?ioml?LFhO~%L1NZWPs1K9>Z16&85S72Bn5p;@X9xRA7YR5oc(%lK)7(nb=
zzQ4{4WuDNV5?`;82>!7d;q7OO>BDIAaj`-1Zoz)O-=aW<?XW3NrY9H>b00fUyT#Pq
z(3C<ce&1Wo0r-&N4rpC~V~wY{@-G$J*Xi7V`S>YJ>H<)Z^6l9+syAuNzRuolyVf?V
z8n&L}#~oeU2nqoO=ce)?q7SPKdY)|ssvNjhCd=+=7Hy&FE^MMv9=!>zZ&=GEvUSAx
z7pG+}?DK`g`e^1<ap6xv>L~o-shFDrmWr8I5%2xjw8gI!D4h{j*S|8y%Q7^!HIQ;~
zwg|AhP8I%oyMm9D!1?J8n^rYvK>R&L_<?zIE2H{Z1y0Y7h7@3FB3Ht-IiK-JA9so$
ztA+3ii}e;+cXq-(1xE+Qlz+#%wh8@N=6T2@Y!rYF|HktO;^WW_CeeCW8RYnl$TtVX
zuYsoJ0@Cainh*1$=p0nxqN}Re;K%4%<S=LDU5>Dn%4Jv_UI-Ses9qjxTB-!r5fy$J
zymbnlStj4-n&qxi0W;h;gD$cE4?4RQTjI%(HDq!R_}bgQ)aT~sQyK#3GVRXuAZFLv
zIEXo1i|O`A9=3(bv*maHrtL$Q9Ll$*ZQVDpDn%g*r}hE4PpJ_;Gc&B*|Cb1*6D2k0
zh^O6^m%e=?>jLA(#O^lCebl2BT7=5>l)3t1zCmo`L=}n-7Cc9D)Y{hsKV^wtP&ONv
z@~U2EI7|GdN`2eEq2JNc3wM?UFh0#Ip=SI7QR3`q*ngzvU`4QZO#J;*BCMlf!?DI;
zRlpfgZ!oEKwewj|^U(%5FaXv4$AADQbIKjqfK4Qb!+vyOhIfuHz19ncEDN|boO5rD
z><R!g^#sO#Ih8$ERd%2^{C4k&taAuSJs-5fBcqDJnkg(mO0Ba~B9rr-P^292i<YUb
zUYV6ztU$tE#V|ctdu#sx-<Je4gO;EpnZ<IA)1!D8rw_YLa~;i+Nzyj|b<j4T1(w@`
zgdUc!Mfef4E`5a4#A!yPfCb(Sz`d3Qi4~x==Qo)6mvuGY>Q3otHSGyJBCA^D62~|g
zQUL)Q&Vkh#LGm=sXWx!A6_fOU`4u|3(xf)auvhF$=zf3Mc7z?hk|5XlJWhO;f8Hpo
zrT6|!j3|sQoC;-(Rr87l%{?b%`q&_|oYKIY|0_Zrzo80*h)EG>vesR~VHln5S3Phf
zukWj$D&clHb-FgSN>iA^&cl`b9vf%t1m;R^>DBoF(<gqS8FHy1b987AogMjGJ-<=}
z%)Z}%GLPlGhhTJEG6cD#L@VWw^C`k4pW;IcUcO{HAOrhQg?%pKY!kQl+D$Aib7^S{
zDovv><|qJcw1tiaEv}Umb;DZw=6p4Zhg0PPk%F!Q^PqJK0{Ur>m?PfB*p!PsE#E~n
zmX+jaQ=z?Zgv;1bulj`LQf8^a3Ma#;xohpRkr_*YFLTJ|t||gnVk+ay<o!7FA&#y@
zEmzkts;!Na?b-zK?LfgZs->w`2?`Fz9}FUdVvbGIL1XswS#cWSz(PpTS34ntz7?5$
z-r|rQiGd+Qd?_ZOyx%m)U|Pf}{C-NjnKv=(q0g!vuQfaxI+-L2T)E1qO0gS7t7W{2
ziMDK=v@2~<<Re|_pf?nGCQ}s>g^xrxg#>^?4w^!z9`5aORBPWF`ei1NFhM*O3HagV
zy|@*_zFiGmu)Z3$C|Hp|0Wx`(K4!ru?F|q|sPN>iV>~8Kkw*w6hN48BCKs9@kHW)4
zD(Cj)&NgKVx_Z|Z_$h~Qm4BvXjbCPY2$(8N+d!kh!wDU`M#)n`5by6HD?KwZWzvvK
zz_&33L?vHn**rrDfLi^(GiOHXATVJpumk@Nzyt>_|KK07NN-EyGq1-@myRw3(JDU5
zVO-y!@80kh?9y=<qK<EvN$zCj3l`=gz)bGw`qvtK*H5-jq>xSnLzTIh`^!qQf9K6@
zWZ;baIylKan90L2zzW`$=VAXY(KZDs81YM*TB=iNMd2p{)qWv>kcv!74Tn+fooQ8{
zZ%sSv%@<JbQBKx9Tc-+X9nG=IlLPuGsWS?x5;dteVNwL);@N7T2Sr2FF%|ImhEZSx
za%XNf^8SayqvYv~!p^)%ItekGzJpJ+fTPp#mr7s`GuUpVZhm7%SsbyfA%U!-K86_V
z_eov})Ff60xQ9o$=(Wc9k5!f+3dsF{$&!pFas8>yACt8RT&E_V8o|YHct}SQ4tN{y
z>tnd5Q$vzo7VjH<zcWS*mwtC}mEr!#U?{7^4VWnY(9O7$RaD&2O7X=*3LX^>CnH@e
z1Do$4u8xtV<QuRu{lp215^)t~XAyg1uiCR(nW-m<7mnW_g9USH#>YTxv`Aa{vlewG
z(%a{!bw3Ne3;;OE&oug${c`V@OWyoeqE^v=!5Qenb^=cIMram?+@Osh<Sc$PQtyvR
zH<A>2o^UC#d#ToeE9>?X62tK@O%(wTfzqtk;^jJYGT(Tx8<T800ihP?WWQm6O0S=9
z)1f~z>zCP?-3w06bRy<%Kk8hsQ#zBQ@}x`?3Qi(XTuse%#wacC*~LNz_GJm5_KFlO
z<P+E}<3ip_Z#U!HZ7ivYE`%K#0{_O1?X!U$FyX|qPu=^2Xf%3{I)K={GtE=Mf9MYg
z-EdX9h@tYOx9*LvJ==oL2;C^~fNDCJO5^bAEv-`E5^f1&1?JT84a%ZCNj0y2X-?WT
z0}8TXL2^FnURw{-gCF6ejsfy#2lGv<q{X+VKhlU^gzBNUz4$q$J{QTJF#7QimxXR1
zO3cNyPQy7}epexODZ(_I2|V-1o3Pl5EZ={N&jMmCnU*hYI4@o>!Um;iYz=7jm-UxY
z2LVLe3kmq86B%RvQ9<6Az5@GrgnHkE1HMSy85S#?Y%Zf#Zl!pGM0jpQ)}s5{eO`tO
zz-mCk9K>>=;uJL0>rBIzocXOV@xf}G_wvbvUCfkv2|;zDZ_k)C2o`p3P$O1qJ1W&6
z3(H#Q;qusb=XWXCZIKb_<+jq5AO>9V)Ir4v{P5{Ek-$WOU>COx?HcESFQ0b3f34a#
zqJ#g_B`sI4d0YC{k70?{%Q=M9^t_KtERFWhqNQdr(*@N0ltiPuB_wpOAh|6SUYCyO
zV@*tdi=liD@6J*Hj6Bc!22pM{uS3#@(K6};Gi@E7A+C?74>IMwS}7JD?<$iA5O|jZ
zWk|;jo~ALnlT6li$oFjF^jxSWQ@P6xJh75%^G>;2m`d;l(34OB#zFY3y2uWk@FgL-
zZkNl|_Qdf;^&`>@^VerdJyg}Eky!s_k}zD7?P1;ULw7(JnkoBy$1~hG@l!s@>rPz<
z_@SIbL6vYe$pSr5m7ou#lNw9$5HUV_<pGy*Ryw$YN?a^0k;;QAVk(Z;hXJdLDCqK*
zw>d@IZ{eSS_OrPqz%or(L&Amlk7EZMlQ-wiFbH70uC&2c+?`4^urP*>HGnx=5t``X
znfckc$wmF7x3Pv(?O?oi-MWmKOVpkaD!O4}JlrX_ap265pCPF}mUSm7p5{2wQT8wR
z>*Dj~*h28e6QEKw3Qqb8t_Go24~G~}x4fh?&jWqv=3h&5`mP@HOwPi`B1~3FdU)!p
zfSERW(Gn(jXyZ(7daFSi;;Zt3KMEtN8VyQe?XQ+)GO9^UB9iYD;=F!t>}SBFEx>IB
z!0XjI!woSCZw>f8uw_386wgCZ<Q{ASG6n2RKv!J)_zR?q{XiNaVJIZnGxsyz_7-R&
zdT`le77iJ4p+kRco4S*(^SQPBI2v#lD}wQa1y|GxO~oc1p{P%L8IAasyrF-gZ&k!L
zSV9S>P<tERzearskpkf+E-0kDhYC7vV7rxX1m1y#=lr-~hcn73>m^JL;!9;ZvLMkf
zgR`~`27TvVX}wFLsa!O1N36#e;guc)Ypmef*N)1<5n{iN#3pL{I5|{R`k7BBoz|(-
z`p0-8gX)Xp@BqRn5iZaa5wi<iQto<M$#piW#q>N|Rm;MKbph)7)<LGod}ayj4E9@}
zJl9e3&40pqaUNc0Z?z<t=b8hm5E03AG~X1)K6w*Mzt>#$)`v5Sjgdt=cD!?4dB}J+
zl^y)o88IQ!G|dMHCaBez)}!GUY}DSFIlfS}`&G9Z9`#L1QbX@bes~gjrB}eb6iv1C
zJlfH7zKDCQj$$g$OfBEE|L7YO=^)>Zid5+cEU@y{j_VCGNLVVEZi|OIuHLr7bhfWa
zc~dlUBddE1;xzsJI2{{e<d3wO9T*o*5_N@iHP{Q1tv;tX&qF1Q;iE<wlcmi{1c}d#
zSDI70#ps#XoefqS=At2uMp=oRuGlptV7tflBxjjvkJtQ5l>KZkIS_*~0J<=Dm7)VV
zKgmjr;g@eL`FOZvX!mz{<>NI7O?n|Cy&W&R{bZ5U(H;^av!Ki#Jt`i#EorswYSU4O
zp)$-*l_9t5nt4QR$sU?p-jHH*k`PG0L7QDo*)#H3+@v*(c`y$rXmM=}q3B)jTKZ1S
z5i}SLbx8*rxViQ-cQb-J&vRW2tAiK)ZdqA&+%;aF{X`6bccEC;U53?l#rkp2f$(JE
zj-HeHE#QB~cuw=)5BEIVjI_sW%AKxJUY-3@lHtLjFF}CtAx(;HExps{gmJOi(2}0t
zqo)Jt!RkKw4z+<_;}<#MGZ*T4Ps-Ue-0I*9+Oua^0pd?B@Z3;AG@fsW_-##5sSdI{
zHG9Gvvj`(asJA2E{y`m38qNFL$U-Avb20Is%?-H+1O|d2fv`GL^D#S)<wprR`7-<q
zwQlJ>PupX?n$+kIfr~V8zsP6!tIAB;*E~i*DG9_yO-hDTG0#auQ;02J0#pby%ZDAo
z2Y0(kDd14x@|rbQkg#h?Qf+t3u5sg<p2(eR-7RiI7b%C7<1WIlG0~Te)LV$fWau5?
zmBH~&X3`y=!1=US`U)uL=mUwo9o+F{yMN6*w%M#zjSAjElW#|F#!#^eOk-iLrY}M|
zfR2HC*F7DFj3(9v%y5tYU!)C4|51};-5evklk?%z(I0+!cp#)Vo^1oPLM5M$4l?x0
zR#5}XIWwR+4!!L9vezbWL;o0zi1BT(x2J+exqbSr$*^;$dJ_5%p;@c%$1L4{C8mRk
zJ=dR&CJ&hOj}>yA6}tY}hUV7dm*c>cmcam`f5tAqsgdD^c~5nc?UjmomA{R(NF!CS
z`pRVqO`>CrkYBuqtHey$s|-jJq(exWI`v+3s6$0pnt2jZQQf+OD8XY24FrYg&`f1f
zS)hLs+-bPC^LCgnYumYPW5t~Py#3gYz~AD9fg^C9BAR{c14;*VZj`+jC(FzKrZjUf
zgiM*y6z#Y|{C6L}SNsMg+zlv(V7~%RZ(nPSs)coHMJh7DI3>uq!RO2#R{N6AA0-S+
z1OMUxL;UrZ+<2M2Kz}7|!ijN;es9)UX^q(HN(wCXhr^#htWx|LI5e5rh;yS<OjgSW
z2z1AU`Xk2?8Pof6t*JV}J;3ay_@E}o`983w0o;4F_;}3OgNs;nuNH`!Nxzqnq6g$X
zM|QLT$jqt0qs~#qR!h5B*jq&CaN%ph&xI;Vx`l1TSlBl>Kul9z6FE74q&<5Wyi74s
zBRLeVA^?@<j??2Ti9nKk3*}}N-@V*5ETQ+@jJ$g>r*e-!Z;u_=YyUw}oHT(x)0hBm
zGaYeuv~9j}NIT)YoA+rU+7R|H2evc3!#R^tp-em+W>4_<MW2Ne?XTU6bb{{^ii{nD
zv{`u!oIbr$ZSqFY*B23g3d-E4pdAYr+Ma6GrC)nr#zg2%UL@!QvM^Vi%=gYve^Sj{
zo_h!ic2jqP4Sg_-JJ@miq;d%*eEI_Mefld1bFK$Uq1zM|o>0f;mSr%gsRc2h-X@Pa
zZ#wd9w~&PLmZ#p@c4KKlsWpP$#llRtXs)T!r?LX+dJN%6V1h}AWX<m2zR193d}L~(
zLU1OyCIA6;i6^;}&(2q0vmuK=jNXCmP88&0+%l`D!~uvgF#=I=jp&aQECc(v#>b50
zhj)a_<<%)})YQsnSEj;+b<vXk?lKJ>v(hhUC7$x&nQ`YUuEj{ON>JBD555`NSKLVD
zoO_*e%?&Y}u1@)}7U{UO(eIhOnnVIj%|vBuw=O(+vg~e9bNV-;3Hx|M%ZngH*pL;y
z?I++H@t9m~9KfYx_AcV;OA#a2p=tu1V92zC|Ht+VpV0FJfwQK!|JI7U{4ici9?u(f
zY)j$4+d;ez);wyIIYMHIYsrPpnSbY`NNQP>Jvj$8XNkU^zl20zN3>vSfdh5?Kj<z^
zF1IvgR!1cNyEc3f2_ExLn8^C@tN@Eztby^hToRj0{-75m308Vq|FX_#2?G42l6K;G
zKe@j`%4>|$C!a9n9m{CEW(ykRY4W3{0d|2<jZkH=@+XkH+4{tCJ0f-5%ouA-r)F}A
z--Q|Lcf#kVi%(l9`hmvuDm!<kPzgCtOsDUC$r2;003G)dQ5osBFyr_{P1$H+Gm-v(
zr0$1gV^1A5w_Ue1ASx&089VF5UkN`d;9lw^Z5-K%e`{)tY2rh_&dBm*>%u>-&c=E>
zM-kXCW+G36Nsy@x9Afcf`+#+sY6kMP(Y+yd+#h}Npu9;!nBS(xaFeY=`)>kV`OrtM
zGDqNlVp{Xzo8cHa2b0Cqwq1Qxa9D%2dMVFn1l7v(n0;WrQ2GEH4T!?V97fHdpl_c}
zw*Ez^xC38rslpxn|FBYAT*Cc%fsoq=cgfjh;_jWYKb?WRLW)ur*=PLQb%fEmN$eUm
z!Qs1W#1R`>U6_x*{E%UZGv7S$uNG<pC-v>6JRPxJW*tC;D5qmsv|W3yp)?wL>~;*k
zaGcK{F-}D_0K}XziK#<Rb~DqN+>WH~z5l@nVQs!{Pi#nxF{9M;>fpK^WHdhiH6~@G
z@b`wrzEx1@v!Lqwe5=aq>|ic}Uah5udjyrV;9U)dm3l(AsH6S#Y}{cK`MC=#I6!Y<
zP4O8NmCbE1mLXmfxFsy9J{%toBH-r}8w1OcwzZ5s77xcQVUZOO^;yhal$O{~q*8al
z7c&v62F0)K0{jIni#KN4(M19kbkb-Oz`bzT>=h=oSILF%uPuW!LUPyE%oJvocS~gT
zNK-CviDtlQB9Bup`_p5kx&+8U9l?>=sd(gHTdF)s3O#j45vN@)KPKquN5?Q297&3r
zc{AQ6Bl5N^XY+wgGMzgy9d6ZzNh^Upnv~pR-ojEan%H;jb}0bA__yH-Xh*1i7>)xp
z7LSmC{f~-F^>Feu&#nTQ18eQa2Xw#k)PM$~r>G^gWwPXa!A0M&JH7BNwHptE<LYgC
zx`<85DQKfO0jVgD_^R>*oGm;`cDs&U=;y7^3O}x)fGnz3z9pFwg<IhZM6kIe2dc&I
z-XIg@Fm|o1RJ_`npmle+PQsh!bx^Twp>%7lvkUp5{%pFfwli85Hv-pS=lJ6Z=Msyx
zrB4*dI*Fung%rmML#{Oe6t?FyGp`WSQ5Ire4X)qxI8LWh&%|d6%Ws!qH{YeMLpz0q
zr^x)M=qW}tcAY-pP<pLqANX#Qp*a6y4}GdR#Cgar)1V&)^cOL}m4U0@Qik@b;Gz%A
z&|k0z?W0C01MM)`EUy%$?KFW}^XoHj{>0DDgedt}-}0Pc_F>ec$u35eK^NRktYGz-
zpBK4_jYd_jabPpz!6(M7V447Qzht<42EW82&keow?nWMUIkuLQqJHK4R*P`3<Pt(o
z`R^r~c!(-wu|)~PtffL(epDa6jH=fVs0&t1lhTSY20-N8PtZmDcF3k<UkC4>-T_x1
zwmoj3$$mI^*7a8Dp_yjScl%tjGeu=0LpFcb`^uy_+>F#m2(hk8gA5(d!+$7B9=0#a
zWJxV8CN=c4VHUTDFFRj<m@Do1-~a!R#kDA@UG&BuUXV-$?>Xr(@!?HvU)7OuqWIsM
zOHYc@hAWDQZl4P_dV7vyTfy<d#86Lzt$KX}HLtcH4nbn)sguQXy>}WV)+Vv+`i1NB
z-=-)CI)1KWY72s@)U9kTv!3ohi2-0(Jve0|6+ijPDcgWQ3-^cs@Q**{qkYzqTl!Tm
z|8fMahPd=6xOjeKg-8GTSn;J`+abCYr*<UGM1RIoYrwf2*ktdo3i^^3%I`Wf$QFVs
zP=`A$cLv_#xLw72ce1VHj^ht4jHjMfT_q*c<0fUQEa?t-GHzp%i*@jJ8R#0lQbxgJ
zNPzGWL$D03^BNXCI8Zi^)(||oIftxthai(cVWd?3k<m)<9%l3ncw_(?0q&%$IF!t2
zme6zmRVWN+7w9QLsr!eWWWA*1?d_M;Lm>cU&DRF1N0VNiSGMdK2bT0@TV2zBaGP0}
zY_ipcj`N#m$(V+$gee=5AZAfesNqureVxJf<-x0jmccaBQoyukaVCUvA<v*@oMLou
z8a9p%1rX@Prw>_Ny9o7|&K+GnI5W=qhTM{8yNLq7L6?#(L*XKa8GputSZP&C?2vUT
zLpDfryLWvi)jin9w}N_i*Q`rr>ryumNLVxBe7-LI)$&@zU35v%5>6DbNL5Nj5Qih@
z(AQw^l~KH2O%?l(CS0+Oqu%>^c6T%OvC!;1Mg#LmKeaM!s4#om&5z1IF9X~QOM#Sp
zb{QK+k|(PdpxVo$g4W?Q!{)+zwJQyuo+gj{o>d4{8+N-YW1rrUm}5N>O2<7$F`B@4
znc#zT;^{F^xS*ApEVhRCb%UsYm@%XrV*Hoa<mnTAH+gsUa|ov4M^QKdme^4#v!-Rq
zi{D_|ZDI670_T<*bY)=u(H3a5uZ=onA^<3>7xm|2YD7m7H7Ec^6>H@My>pd|FOm4r
zftj$cCXVA`VM=(Pq+?gI$>r?^<ucD+rO~U;Ef=_W3U?2DJeQD%Z2cJ0jM-8Ue<`&s
zHP!mQ#1PocLrf?fFARkB`et;Euv;#wM{rG_s}Vn0NitTS)Z1Ys)&^He#&DLsBnc|~
zWjN5sjekSX#I1TR<ZI!^3p<>DG2NvBv{jPA7~T0FBZmCoO&~V9zw2=_VIVc}<8i#v
zK6tT9#PvQHS*4yyY98LMLdFX43Q!9!la6Nt_=?*FIf;^ckU81fWWe$@dFKVun|leQ
zYN75QrmBPCqmzFG%<9Dz{j?e+$Hc(X40iK3xUb#YEnZPx64Xx?1faVF`T}CdFq86o
z0{4c1w|-k<Pac)Fd;p8=W)F~@b;M^%q@=hYTXx^?aNt%4J{HEZ4O3Fao%QZ@A}V^c
zP<E(vyCTA#WIjH)0=w(p^wuBhgS7)Cft-B)V9ZWApDfM1-^phn^c!SMyaLZ5%hm+X
z^j<<zWIhxqFm&&xAe_<8pu+Im4|KDS$E$aC5j2NdqJ6I;>LceI$2Yk|N~3$RU1e1l
z{`sAge8a7Aoz-CI!TKo#Yusfg=1G=1m-=p&S09%rQkBH|wvvH*PSdRaWbfHDk#M=V
z&QH@hs$kp^x71Q4!C!5N=+2dirl@sjtHs!i=AfGF`HRIJkORV1{V{!SomMf=-S9^d
zevtlGw3jE+=cp6A%y#muK0#!n?H;(+rLrxfyusQ_Cn6bNJq5_4gv8WSqxQq<>;xf3
zRW6}vsF}y8bVIADj$nCrJO7XoKc!2}9!gFkt%fhOa`sgVOqm&UeaVp)0|A3V(h(}T
z=CprT8t?#8LVt^_>0ArbpmFnniwdXkU{|m_9>Sp4CC654^N4Srlse?}G3a)PnY%FI
zOMPv0+$wgP$tu8t_PQLO)UP0diULeA=33)L0aE?(vr&?ioe_BAP&V|sf0F$KQZewu
z!*OnIBC9<Tg)iNPTDi8~F{}EDD~{w(xyvFFLw@IlK`bC9>s9DXN0Yy`Hb1<vff2D_
zoL7k_(PpLWP*;{w^<<vP+iMj6d=e3kY-^8$ianbr8=2kM#sr~5#6=&LDbnDj_(a?u
z=rO2xaSRPUPd@L@y&FCx<x_4KXDUDe@V@cH9Is*|Zm!!aYmro2Fh=cU@KKn=EKuD3
zWk27)_lqy*xa_jOzAEk#i7t+wU2hI`bc@~HD-<cP+05@dKz~f`<k_VT7J?GUf#G&i
z)B~jO&%2JkQNk)`euuutVYNB4_+|@(IA=0ex4r_2ynJf2lNB$a%p?!!-n&roRjX^m
zFB*!&YVjYrzhd1{O3=Z%H?CU`qGnCmy&O1*#H~^bUvaL}x<qqtTc4oSURevb)kKPs
zbio9gXIaqrHiM9N*Dr%XI}*k91nBOLj3TJi96cq$`2QZ$LFzr95MXIwm;rX31yyBx
zIEYe==kLbyt0UF=><h%oH^kdP4u8f@8)KpHXI)C`UUc!+B)X%`x-!M&h~Y9wp;fXl
z;;S#o_x`{&{g$nXXp$Yzbm7d+!`k450HQId;iKW->5~VmMq;|z<Vx6A5i!jVhS@?m
z_OMZSdtLV{usXBWBYvQ#wckJ?Iaq%uDp){v^0$jXB$dx-B#b{3i!DT6H-Xq<Id0P4
z#6Tr!dIq;ISh>)C;_cZf+lY%2Cer0tJ-BvJ(TBTtE=mLyF_vr?II&0s;yeKBYxetJ
zC_Fy}#NIREQ)$v}gs0FndozQ*61DmE+W@7?iy*?%QJ(yy&Z0dsl6$fnbA*T|d&1LA
zEL!)Rgg$`Br^c)vJAkwGU;V9;lfR?^7E;D}U=h&zw>~m3fHBBe^dpH$vXaSVL`1fg
zf!yE@j{EZ5OBCLojP^A(rG#9pjLga5pHv+;7K%9?ZvJ+-2FsJ}4)-U@ncRLd+qG_T
zboCgseGb#VX3hAS^NT9ti%Dowe)$O;-v7@3h6j-re20vO+D*<}!DH4+L%N_j5U}r8
z=aBblGTbQqE>ic5Fic)%=s8wABBmjAlWG0;6d6+}U`;R~<)W6!zU~!diI`tJ<rEG5
zALuSdfXMM9-Rv&m1b2CQETo})EIYRPEpnO<LKWpq{6B(A37oLmKOMdwq@Agq$VZnL
ztEWLTHy{9;h{0X{dUTcujv%`SD(GKbc~Rzvd$FL3$m{1&7YXm1<4>m{97LW>N487b
zUMb*?!4|JhpNgd5Rp@{YD*50AX@<&cD=cMC_<OLhAV9S*2ck|A{?weETaz^}fOIKx
z*ugxr6t>S=Q*i$qE?RSXLhw`T4OU|bFtHtqnV7IuxS%2Gt7KeRV`z!AXeW1*IWEZ0
z+6o&G<lRoPdXg8Po~t#%c0#K*Rtlp*wZU6B1iF4XuN;$RB;;y;7e?Y>PW3Ty7Il{U
z0MR+f?co!}1i`n(sq}~;0j&~io-AfC)P#L#p|X<vGm%$d|NACNHOtGkgub(d(sqa*
zauWz-sV3uRc>)?M5{7kx;SFz10Qn9wy`|2vChcgA!f6eYx$o7NFrSIx$sm(s01n(i
zd>K!Wa};(Or-2a4V!B~p9*S2j9uQKUl(@2hEORe-bj;FeolXN9A@EXQwnPPu^r}q?
zL@T>@j3$j`?&FJ|yR+&qrxl)muE6fJ(b*WAp^p+NcpKu}NT>C15Kb$lIRqhuspvK4
znw&WB{=ikRiqMVeXaW$gu(DRRe9iLVJO?K75ouoz!=bfyk8D4(;pFHPt?uf16l(D7
zx#KYsFl+p_<t>I((tG>^=KfI@S0>{h&#|Z1)C4NcoW!q|YLH8`@w_MKHZX@)jPnZ}
zi{8}Q`JVRwwt|*H3-R+l0QgUIlQm4^q^GbH0ofM)&zMX>+)XS;?zb@Tx)-shtTI12
zc13fMJ*pD-?k}HrbOrwXmatH-&8p9Diw}L7!+TsuLqC0~QjYF40L>-`)$4Q01sKqb
zw7i?&{e?2D(Rrf!VJk0cUZ)eLtJS`A)>Wws2-vPMz!N{1L0bDTw7DDo<R-n=usU#k
zb2H|h`$#Lijwe8f|K$CDC~WHm!~<5PO*(LkLl~;Y15aED92~nd71>I6-ihFtBm96Z
zvz6BD7HXT^Rm#+Bx&MIm4rrZg^%9ZgjOK21WM2=CN}s}m0FV9v5sJ{kjAe;s>UUH!
z4$2-$S|4HT7M^NU{7##s(28?<Rg6VL&=9`(l~wtza!l5Fa&ea!+A!-hGe)9f%&{~^
zyWk>@ZKhz#$dY;oW6qiTC+v5?H#L(hDGyZFQ#H+th&$$%c61jEhMj+*1#epV2dH&d
z+Spep+958pkrGBgx4oF1_ncvSO@dX>_&|X(!eG`~Yd+!zgSy`#ysft}5O|ov!B>F%
z%R^GY?|#hl;$5ka32{yb_St30q9ux?YTSjx;J>#?;179u2PE_yv4MyY?>;rZCUgYR
zMhFAnC{tyVmzY0eW0p_!n}Mt%pW2R_Jk_f5O>(4ht$+O8<I3~R%>zCjd|uK&{!++y
z1U+fQ4bqXS9(h5F#ubl;`5zflaQbDV0k1M{Pr=(+qU7x|NnF|T9cApIbf!aiht;sY
z-^Ko!I3ksXUw0DGh9v&{_~Q<Hqfz7o5Da;!2M%Ir#n~-U^v$bIZKAn)mZcW;aZ!Ja
zmnF=!r&}4X97>OW%*L{iGo+x9a+sJvl{|RmaYd03Lm}dp1a_|3`6$Xj;iRs6W|rs&
zA}uQgv5E*E`ElpYtc<pdj@Z&jsg*LW*x-lhQ;BmBgG!4hr7tj8;!T#;y{~WV-SQ9O
zmRp38kz-T$UwZ9>9Uy|kQnrhw*<^*A&IpsnqL2e6u?t|dn29QJ3=@Xo7%h!3SWRZ7
zUs&u1Wpe7sg3O(zmJR_vKvq2qv2pDP-=8gFUkc=_3=jN>-1E-&VhL`x_}#b-uJtVE
z^jIPyKABwEk?|B(Da?qqM<b-Xq_%(GG-UIqk?yhteqPm&2@4*L&uffNrA@gGT#PMN
zHNb#4Df(`DM)Xc-VxMyq*Z&@FbF^vuF&~)d8p_5jqIzDrjVCfzP^@EE*@mx^hG5vD
zW`*cthOU<Axb#RmNu3668%mkx(`xA$$ja7p^`p~il6@U2-&AmZKm2~w_#MLKJ6Zgm
zzsU;o3Aoa*_5E;A(x-l5r0d2Ht=MsB-wG5w$$f!umIn4OF<x;aT<qy0B*)nE=ww7h
zbcYM-<e?HS!;*CeW_=nH{2jy74kc>EdcTn;8DNvwL?`^OOtvYy8rrBGtak@#p<T&+
z1xk>P_}YPfg$WiDUxb{SdC+;;L{VPtikQbklzouOOo6N=C<|6fcU`cJN%z9Rez2gl
zp9J)?W(Qo%y{ZjQUqjuWtiD|c3PAjWFYmC2FKS0dL1U1qRa}SI4K|}HVpKy>*F*fF
zoN6g=(><7GJ|Wq33}k8JggI)?mKeMF$FP$$?V$h|h31WuCRcwOyDR+7AImS3pRxr>
zysY@ZLew%=O>p>xm>~7QGv9X93`no?S;cP}4NF%7xh@x$c6dEC%NR98sfAv~)UQD)
z`@u(#P|ay2n4x6Hrt6d~YDHzBUUmm}vz2pVWTCHQcTw<cT9)j4=_tQG+JIs61$qO3
zuS*JoS<}$m2Y;*l#SwzI!h{ers^*5%-8n|OXv7jO*^dP8lf&2=Gcn>;%sPnd$P19y
z-_Ajb6>Q>RG$jbXD73q@-`NQ+#`WZ$+ufzVlR`mlX#l61>3G}#B68vFqN09fW2bW=
z0F8;_pSpr`OiVKQ<g}jSy~h`Iyj^qnAunIhqz4zIFDO$R7c6a9828~b@%G0FfT#va
zMIKpX`(>24y>E%8JX1x}oVh^;iJpa2bn%r9K3Z{+R;ykI5q;kG(9SZS#GH}?_dmY<
zSPwYeo_DkM!(_FO^J!C5e>E!b(*2xpgYdsZtKzcAKZkt5pXgR2-<>OA-NGJ^AK6zV
z^<=O7F56k%>XJ^L#H6Wx!H3Tp;i15ZB%$tViKHarD!W$HN%t%)VqT3o$LQ**0(dQQ
zmVu8b-edfFoGWa?#C~R;OOZ}KYkE>0(*Z0?3o$SAyEDU2DteBggcDOmj+0%pX0avq
z)8#1OTfs!y%gvyBA{;rU)EQzJTyl10jtOfaNZCumP{o#Z!c&~kSKms`xZ>ym{hIX|
zJhN@U%QMg6%q?ZlAnRRu6BrXS{JMJlZ=-MUr-EF}@GjCSpX>?<NR7DwcbHpo6mP|i
zX6B`KG_#Yr<_Jz|sA{;ue?BOp#mGLi^`z5}QC!vIVpg+{AL1#cGBk_A`fF<j6g=cL
zl%#0xuCa{$aSJQe*GEr3{==W`?63bx9BZxb$au9|gdLI23hxc)NnOQ!3HFEV>T42S
zLKqBE(YQ{e6dlm-Ii-R7!u&38s~B572lf+o;H_Up<?rWKQ79foHu~&_=Gza6={z-J
znL3YHRnD1qpn_@Xc5QgYRSbj909ilMSChajMc6;P`T}{%^^n4P`bAd+IAX)XrgtXl
zNmyfryMQcVW;R3|S+o!TV@BW)P41-g^Dj3(S_lbNLuT5mMK?YKzz`Jr^A{=Jz_K7U
zkCS1M%X)61)rK8;gSFWLO!oIwEcCt0VQO|khnV5~lknyIl@l8iTR;e%)c0ih0Q6hR
zF+r|+e3o1Dc)X}Jn3Djrh^e~uC@BTZ8wR8L*S7-^&yaGEoLWmjcQ0dK3zHYY6vaMq
zQvv~~*~@gyQK~^E&_owwjw>I$j&y}(9YV`Jc;k-ad(@?EHZ_|{c=OQgX+VX}5Ci*J
zL59`Fr@qTc<Q50T6lhQ$pZh*F4WNq>eeK$kbIcd}HYyy}89VCK>I4{<Y<Gpb`}dTp
zSf>~7xCb~qA0Iq2h1MFE^;KG8zf&RUv4|NHz#X=G;V*@wmw+D4c=*K|4iZfO1X;oz
zQ{006xMnL-fW-;2ePYL=P)41G11*X`mf?})G)UW=`8yCiq)*II@tuOG4Zg-)n^DHT
z&yNg<zPLf{U6<C2izq_|u*=siueeuj7&K;=rm3fb2M<J$@4>AX(X_u+{{oRPP;O^k
znrlD)gE1W?UGH6^qijw5kDEXpD~Juvq&=6O7{!g3R!Q^TJe^&3l`7kT&FwtgN6417
zm%R5^m_&dql(^{AaoUsdh9(bZRQhR?W$?O`!}<RV7j0$sy|PFL7uBJUw)l=9Dyp_c
zB7Ofcj!!Ev;j@3mq@{(GBL!-RG4_q2L>jZmrILBu$pyy<MGQg(sy>@`T{9Qp?2tHi
zAL;wAIzl?e<1AL1bHdE}%&sW|{tfOrlFot51w*cb%C*6m%dF=;=y3WJb756gmYY6K
z3RYdlLoZx%GQk*v-XEfLhZMm?*HW$7`Bd{7$e4<28@TgnV6LY_;Gz~$KLDNW1un(3
z9*|NSSmn@#)My<sSmuaEoc-3ZcKIfG7fjn}YHo_Q{EK96@skh1zc0Db5HEwIWq%>1
zeZ@&-5@NJJwucHT;QoJQT77W&cWKI$du=x-AKD48GhQgCD?kZ;xY-#z{DM*dg&>4(
z0(*b}Nz4GnI$q5HT2g;OczoA24Nx5`i;h>QRif!ymg$)PmQFO<=EyfWj;}qbuDZO4
zudAtUKF-jkAm+ND6=^HA3v>bDSe2n&4j+pi#PTLw0$xV2cQ)5GSRu|gC6~|smJ>|g
zsWA<);9bChCOZQw<=w=7)QQUWr6(Vs6R~q~d(u=r>y)46{{1nXD*@a9Smg+ZvS-q7
ONxISqcyHU7gWVe^_3@bi

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altshifttaps.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altshifttaps.v
new file mode 100644
index 0000000000000000000000000000000000000000..9fcfe0bdebdf01fc5cfde2b9ac6a74b3ecba821d
GIT binary patch
literal 2480
zcmV;h2~YNm6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQl!=9_&Ue+TTuWR3$!
z{&RTjp0$dWf3*0x>o{90ab2tj8v4ySFJdV0<*kw)vgFWi8DZ0#dYef9_HY!Yjv;2y
z;s6Cl5iNGN1<<=cr72B{d}M2qp>Zve6WskD^@*zt&g9^KF(%4B+lSA@>dq9b-$?w4
zhc#cM<{Lrpjon^2`vjT9I+Y?NCMFl{0(hS!T;kO5vJYnWKNY+aPU?tt^<U&ixNO#<
z&EjI}1)VM)gr&t0D)n#=F~N781>b0!-D;U>x4O@iKZk4OJ9l;>b0U}uP~D|y&r@Th
zbPkk%4tcrcWq&tAPpbHr8~MplNWly_0@PI?P75dP8;zxpr#PvXNts{nNH(`=sx}~o
zKOx}?o2Vq53E)*s=Y$=4;M%Dl{i&gWggA7X!WLRy;9v+*a3zkUVReY*9~PyalLx=1
zt2Z%;ctX2>s?@5l-g?$z8VGi#?6ge_C+F|uU@ue|Sjh7YR8{TpqAc=2t{)1V>uyPQ
zo{;fN>5->NbGL7Jz)Q$NOU&Ku_Ox4tZTRl<Ziuu5mH1!?BE|f%r&p@6N3!+Sj~A_W
zaDMemeP1{g>125`vzWV1Jz5hri+QpUwMKjEk2B4*sbJ<KLmRDO^*we|fmzT-WPnKF
zzB;+YW@+y#TJqVEUZsKb!u1C+p|#OI=)<eeZk7NwLx^?TEy$&~U>Ud%TUPR57gnEi
z4#Dhr$rY=zEI4zL1o2teWQHrsXO3`_92N~of?}KUv{-<(#H83J5K~dB?utFdK(|dU
zs4AMate9JCo2#{6#3uS3;Wko%n`x}Q0Ql2<8rp8UQ;PwwG15_FKt%>2CE{myJ($5l
zjx}2N3=B!A?ggt>aSWgCym4<*dV*Si0OTCzuArOtK@xUXA(RzB+x@Mtva&<v-O2#^
zi-n(*KTk;l3dAuo@;tOMr*iaEk0mjCnA9G2g`!x$*J50rU>t-*xH1^C6(T4^oSwJJ
zbE6wX4-k;|L?NHxd31rc&Kc@d5;^N06lp_4ntT4@Czp6SYZB1m8UELJez!p6LH!MI
zV<51^C$@E-SOneaF=@U{FQRGPK6$|CPsoe4*ucAbn3WlwD#U6*^sPuZ*;x$Th<3|{
zvFatZ_HYF`9z6gN(ELASV&pQIyd}pMg6rUr{Sr3-o*j=78^GbfH+uSY3kC(g=~ftz
zkvZW7JXGt8+6iU?8f&u(0A$Q9VK|hi*-d5ZSzy4+R<5zsTwARZa-{KJ3gg51C&~rH
z)I+xl^)E%dSAqM8!L?Y|FEN!?2epKZ$oa*b1yFYilySc<XUasMC{&?kQH%-u#)l^E
zpBvnWk16w-6j!`J6godbQ^ElLdB({tI`jrI!;Q6W{s<r{Me=!``U!ni1a;hDyqPK{
zcJI1=3VmmTXjq`E5#Y{PhdG)kP^saKck}NJkOtigBw3N%v9Kjt4nnAXY`T?dz0ToK
z=QX{0LkgRap~PSULz^s5Pt_2>m}np&(3fBf`SRV+RoaPBm-lq9zi{1rgdb$W2MiE?
z&V=J{8rY64E~Mvuka__FmE#><O7Sk<y|FH%v>1%-^VZh&l<B)gblWd;)sHo2@>?uN
zfuf!?Bk7oeYhQcxy4c;YULH<bjd$k;&H*z-l+1;7bOG-%^|J9x;_cF}azan-OzrPD
z&mBH@g&Zd4i%=l06Q_lWSiB#^TglW($vVN1oy^+|Til=4koaY^lblvS(Yy-PjGWIV
zEf+nx!p*320gmjiJ>FW0)J?(^pqvDhTRta5UiD1vyi4J2)tP|zZwew9`7W4KJ0h&;
zT{-36R-#<Sv6gSI-e|)`0t~EJY;a^pv{5Z#L|ERsgb8j0%WE~)^GgFF;}R69LIx#)
zvmoy4)5S=(nwBOPT6)ft#oWivVp`6{aLBCFnsCa{=yA8Ber0uJ@&aJdfWeMNN0^Ig
u)=q5QI%OLP2#Q@&oBIR2GX#e1cez15>MDwZLug*IH}AwmgbN3+e*#2$Qpyzo

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..7ed34207f9c73c20624aa361b67a3f72b5a5567c
GIT binary patch
literal 3728
zcmV;B4sY>`6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj!OiS|(+-e^`nJ%Rkd7xC;%yc)I
zevS?3Pv*u|S~yna1kSD`lJe;>;-#~#jxLxjV55{O=lzTg;vZ0I838W}=!&a~;U;WQ
zQ|!?8Fm14Dcqi!{7F=iS96d>jo<eEFjF)0lKc-Id!Vxq0-HYfD2+NOr4R(LzyT50m
zND2jahw(2#&tvv&18QgUQ?s0tC2+j+w+chOx9ZhRIP(<lVF=O^t=Ja)fA-PA`|0^k
zG@ee8qfKM-b^lxLzOCwg6@#?;I)DfbJTsJS{5>AMYw9Z<D_-EiGs$(W<~3>0j2Lsy
zO&#yrF3V1@`?hG99{X=T-l=QhZOrgZL)yqdeSaZ871Z7A00S0Kx<`mwGxA_6kb90o
zfe0BxP+lZq3L2sjn4WOD7(zF#nTw{;fl0!6+Kz+*hxbV3CF)aTKXfO6E+^A#{zIEN
zg*uara2V!W0zk=5dhxZ;T7f++w)bY(>eMhEPBcIF6y*+6R>Tybs&+=vF8nz|*y=F>
zt+O|1%FWKLORCa~h@^_b3=yi>_`=1sKL`b2eY5<I6B9PV<2*vFL2!<d1HC_q(ARbu
z5u7IQv+bM~AX{FV1ls3q?9vJ~y^ec#iUC#tD4;;yiSnD!hQ*Vb|6U+{o4`@$@G2&X
zvAWVFwc2uJc3*>y`5<}BhB?yV7{oJ{KtjwmNS(UBRb=Bo$;E^i1$VDQ0Cis!5Jn15
zTEn3Yk%%{_7#st8*A;ok*Zjch(}8SXrSk`_9&Vf#bWB3|xwKvV<6sr;aWmd?%_FSQ
z`Y$B}EYiw@u!=DtT`2Sa@DE(B^@<-%-#tIjqV6PHlPtzw)9b~%q9#`Pd%L)>vMpz~
zdBAXmK?HPgo*q%eu?EzE)erEEi{G;Ep?HDV5&o>C+_2wp%dEzRH70)NsbSist*co^
zGbc_A-+_7FSWHL(mwwt4<b*<WWwF$NF_usrq$@qt>|jn}J^#0ePfC1y+lG#TMY&UT
zBgh;uz*y1W%w$?S!}yDrHo{Y+<(bW(`jVmrOUt}l+wV*BB07o9F|Cs`N-_)5LAMVl
z^oJ4So~424GZJRPtJYIJLFUt~4n8ETNh4pUhS7K)gX828lM#8c%6E&O<_{vBCJ>l4
zrx%8hGf&V0Q=6UgmxK0~Rt`l;p-sDnn&<sIF6o&4gc6~aTIL~YxTT%uy>oFlQ-aui
z!7O8z8WXp}cjCy_3!;153hMTd9Ba&eHdc}HzIUfl&oEq#pt8)i`2tsg#g^@aqtD7T
zMHw!6Xy=L8{)xXj9*__wY8J}lfh~er<W7?Bli};I(M|As*+_I4I#>P7Gb`aIvTOzg
z6xe+!rI9*w1zGOJt^sr-SJ}Zhi%od%;}8jO7Vb3&+%eYO2LTAwzL$#e;Z^OUXEEgd
z47em!lR~}tucL#zXH3fzMHE$1YfiGF4||X*q+y`_W?DDs#n$Lct>Awxup;P5qgd)m
z`0?7AR!iQiLDACc69|~zyO)U0AC3mtmbb)G_$gnrDztrujK<(B>_h=d>|q&B?E!)(
zP-6NyR&mMr`w&PE$y`4AwYxi465UIm|H@+0I!B2;uOy(kVZkPNb^*s7PN)`Uodb<S
zkCyLBcZC+=Cb)fkC076&Vw+PgArZ{N9$}T9q@#Xm=_NWNxdg<G$n#%s{2fBBP&66g
zaW&XsIqMB$a+MS8RH=8mO8dzT`R%WvaOs2e*ljBR-`_`>E5D?oyvbIdV{f=3h((;5
z8x5@cjoGPUSaP1(Bvt_PP6{^odj;{@a$i@*e=C@wz5E{Rg@mlwAq=}jR?j6iyYVNr
z20jD*mC2BeQgLC!X6w>#c5)%7ENj?kwh5hT`Zo<sJ=5gd2m*ZNX{k1OGcv+WqI@j=
zmtX-RA5btydLv6ICGS~!v<81HFYb;G3tNoIHMo>D2t*jUkD=*jt4w+?j`m4cac->R
zwArkiU>QR#adZ*fRHSiZZ>F>nsn^JUa-RDquioFE!B#G%^Z2ocJMfsEq<Nasz~^wj
z%W`^1#lG)qMyMQdMk~!&-~RO!gm8t;@C0FFiZNt(c6F(*IzFP`{PM+RGhjeu4YqW*
zi%w(AQzysqRixNU)lJ3b@vz@j@<Z@;a#b>8I$Mmzy#)D)EMd(ar8#Z_zh4A~4c0r=
zVpMyMMVO=5vUhx&Opi1LnKdu&8V`F~jz!cM3L;OZl3>z$Pw3l62tDF{+ZZk7v%WsS
z_JT0J7`twOAy!bX&LT!tI`|V)U=M6>&du?3I+B50wy73}fi6IbPD+~ts`8dWPDU4(
zK5+ImAY!Wk2BDGBiXv#%f*;uUJljj7r6#TEp*Q_>a^r4HZ~nKmmEoHFJTow>w!IVF
zi2u7CkwKzREujAAxX`7DDGqUw=`A1{M&#wN;>afbD$Yv<)3_qj2llB#Y5;gh)gqf5
zkBnuG>7u^Yj{zNaa$MKI$4p#a&vUys<k3Pml*{P=75V|!owi=U8M4YpE`6eV{R$cE
z8NPv%`H+!{KWymxYZ6l?clL5QZ9_o0T`v4gE%}7X3X5|h9QVMxgwJEM@~0EO82AjA
zWdW@M28m>YL-STU0TH*qAUJP#KU+qN)cCws19FC9L7@impu4(nPNKaK`Gp;5g?yB+
z0mSgt*Uuf+YVDW6<!o#-->`U>5h6I!H?zO2j4QHahYF4>5(YC!kzu^}Fh)#;)X)^b
zg*W}zI1L<VrUehkUlU<zwL<LT`X>&y7)yjg=kb^6!Bq?fj%la#rHnMdfBcw9uWdHx
zg}$29@Do^u^6Yp*GxvltwpfcBo3u93^C(GzhN0C0^LX<W=D(0-Wux&H?1gk(P&_W8
z*n>0D%h5D}vaHIIx!jEyul26Xz;4rXwd78<JeKa#&2wPYmYGMS(q!=J^a&*dh>p*n
z%OinDx&QW<SLzkd?ft>cG(^lEnZIi+XM$W>_!af$g?9d7$^V$9JeaJd<LLmpk%Tg7
zqXiWY8qfEQo_`dEaDnrUOp~Nf+QX=~pukyzXy<4di4K@+U2Ak6x*};?@-QZtjFpBa
zpCd1vW9%nTvXqY1i~3pZ5HsD9P$%6I<+v3?=sZvjl~NqEH=c$h6#NJ*rOahxfG095
z?VTIVNa;|7Q-FbO*=n{pqS@CuGzB8Wh-W0?UYS|#PBKOzE(q@h1HP2c_mULsC0T?b
zJrjNy*JjEI^x4|nj0pnSJZ}zo##B7D%_)l3owTU=R?*c8iXEf-?TZ+VqP>{<u|CJt
ziroC&5>cGyU4DpLR|NUbPY7IHqcTHn?23bI&A9xr)htqJs>J9**4=c;nswqq&;VCW
u+yv9_gw+z2DsJ^Smm}cowecoOD)A$ZQA-Ao#B5dG!2Qc?x1jU6`8;f5081VK

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_bin_cnt.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_bin_cnt.v
new file mode 100644
index 0000000000000000000000000000000000000000..782a21faf3afa75ba896a151e5e093e5fbd7af28
GIT binary patch
literal 3256
zcmV;p3`g^e6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlMwv^FqTlnH9wnh1Qs$Cm@$uwa0
z+}w$SN6*~FiZ8QZ;~!St<?jpnhkL&jRP;`HR!kYUxyb8}#zV@yZ7li2fshh^p6dM+
zWDqi#mbn;R=~9P;Hp_4O)5A~S0KR&Y-&}m&Jo&oA*UIk3^n)gC;XYaCEnh8}7-_Pf
zT2*U7DNz&p6X2t>isO@_mDOH8hp*B7r#JiH+7DOM=~CxjC0qM<RVnnE?WOC15grjQ
z(w^0YjYvctfC738kG)z-kLtHyLq7qIA`(|q5mV}~S5hI3c?`3vcOn>0i8$_~axfmm
z9Xpvf&}MrZVB!}bLmYzry}D^ks609~u<HpPG`2F;Q=Y{asArhUP1zOz4tn5<S>lY1
z4F`~|@R$#MXEH|v5r!zZsSzy4PSLArve)(U{-}d_&~=e_!$g4TOb3UC2~cv>J5EWA
z)|B%Ic72F??hqj+`8_9U&02J(CSr<$`Aw>F9*y~`T!Y%Ej+nvU)fL{&ipVo6r%+E)
z@lU+Sag#iL<XVtuMRcdhu$I;upfRbs7E}afOBktXf7-W{n!eEP;aC%2;t+b>TLXNi
zXXl$<R_P0cML!>&>~<Nl@^n*}+E1_Z`c=4irhx4SNk5Lh^lRUD5ho7XMUrx+OKf5X
zu)}tm5rBn`;RUa|K>CZFdN+FY6o8mAOP*0bmqV2rUh-+?TeP;i`2Ej*zi|MqCUKNn
z8J*i{ArE<Hq@X7F@_&gJ_%=sjB*DCB_p9J6iZnA{ssB%7fgx40iHnQf&!Rb%QiE3a
zBR8hZA_1xa5T*gAJ|GFX+z#cG#37ghjBj@Cs8J^JXy~lRt)A`cXax5LO@GMF1Tk$o
zFPO{3{ax*7Gd7@@(9JR}LK8`H*7qF@j}?i$1t<(5(Ac#)WFD;wf&Hb0`Dy*>#i86c
z($Z^7c>ArupGq&sOZA5}h!&rlj1w^&(l`(91ng^pm7v(bUg`b2kjHJj(L~So%Z2re
zLjyY?b@z%aAzp4J*cY4@fL|%gCy!8CJ?zXjOk&wkvqUZPdtHf)vy?3$w9HPCOKrlC
z*|Y+T{qnss;`oB!_GgItN9Iw#;KHoG5y(B{wXmXLDc?C-@v{QaVWWJ$YYC}mBw>n<
zir2LLQzr-5Un{RF$U1?`Gc3?^LmAyN!claVmAV-8$JCW0vBuD&Xzs`XhlyE_9meni
zY<R>r=7Z*JR_B`Q5JE&BCR+;bN>OT~leO(H9^dt}$8vLpKbM2pv_F2vZB(dt<{|J!
zVV(2`M;15v%6{b|MYa+GLb(AfZsvZ<Yy2k&m`iy~7ChBzeVSVq3k19%GYwH|;ATOk
z4^v9t9Rz;QPyE#Ai~emadL~JC&AZ(^RIe_)N|#fxcrio^S|~PIYREOF<L%VWV<{q~
zWjdMvb8kcK8m(5Mhu{PZp`q$*UfB21m{ZUS!iuyffPp?Y><2wUpRIb+O_^repv~j&
z?t+JI7_gvcHcubswGaI#8i(-oMIXhi&^VJ%;VUxI;wuQj-7;XHzn>lb@R0EP&Lcr9
z2c%~Jb;?0QAneYi7C>?oShxxvWEbM+H_m2jj|igoS2fk>U6`A>IuLzdfuf!<YYRl^
z9Qs)i*|ddh5ChUpT#3^Q)q4C%Tt=sa{JSU4bGO2LRBNqu5w{if=*8EfUDEmc&GxJ<
zsoFy~$>C5~<-izwZ5^6Azct=p>djR7$S+>!Djh3*H{%}@aIpP$64(tB&^53rJo;>L
z5riIogD*H!z;EPGik>$bmO>>ZDdq92D^(+%wXy8~CX?hv%CG4}c>BMrig6)KEMXq7
zF7EBgD^-d~?e(+Z$rWQi3)PW@-M-8#F2f!(R{M!63#p@R&c9Kb<A51pnyrS*f@FMk
z2A~}+mOy86jypa#i^7^;ar^ttBK<s79BD`aJ}1o`=f6G1sAkbHZ<b#`X7(GK83$z@
z90iBiengfNwNpx0Ka7Y=O8xzZ@o2D<vb=nUJk{Vl@NjtWJ=JJQ880AKk}f;7d%$#1
z%Nw}?h<;mmqSIbP>car9P2el{#jFcE*(M!5!tL_Ul`-67JtT_EWNX7?sD!)MeEl5d
zUF%_|>+*F>r`baPY(GABs6DB?I{2MRXl}7A-&sb7y@rAta*}c&UpBVpao4iHXOCsd
zZ9M2W$ju?qe4J@eVz{`J!lpGlTUypK`)UH6eSL>=3-+3Q728@RSxEJ&%?X{zhM89A
z1f)jY*BN!K{!{`E1b1q*Uq&^Lw%&MoFc8A9!*6s(Xm;K?AehF2ZPW3uCV-dX5`zSE
z0QSfs0U2LR@N03D-98WKaKqUkmxnm~*k%uGsM0THNc`oun7({j;LaEJh?BG13~>L8
zP&Igxa>??(H4=p!z=p~p+G<3ysgK0@j;X4KolYQBNO605w>CUQ`dU`Gxi@pGRdgqI
z0M-3|c}lneUtN<hA364FO~!?N5`~>%=+42751`rQ1GA1iiQTan#=>+UtjbUt;EBOE
z+7qiV@!bT$!cNgSvX~&~pT0dk?lRLsuBIdT>QN%gyykqnS5HAd%<PWHk?c1I*7tS#
zRgW=Vy5VwK!OtN8F?yCLc8J0jdkLb+@A^&`*hOadVc`fdZ}LPXHEd;}uyy<nA11w?
zEVleu?^WER52IkDmYgQa;GqgD%UKJ?k@n8~=yfOH6lbOB%IM#dedwYJpOlpyK!oNb
qz!Q*_H~*7T^;ugETZ%&b9996LQ%ffq8c^EW5(;WbTgTm}C(VEkUs@Ib

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clk_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clk_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..cfcbd937d71faeecf579b4655306c24763748a08
GIT binary patch
literal 4656
zcmV-063^|66Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxCDnVuKr+50vFb0!?u
zYB_u@7#Lk0D$M;^STLnD#+|Yyv@8)r&2=$w<nnS;Da}iWhNjy}+QVPJTtH`)YYFug
zhN!G+Me3lCbq9%iDuvhU1U&4+O-w5u%~A|m?Sk*TN@0fgfPq_m>1Qs-IJ{(<Ownc)
z-1hgCd);ruJsP{MxP{L}w%LuZscgD+AQGE<XyqeR)+zKRIE5pc%c;r<ii8J1He52}
zKguZnu#Dn#=W!*C$A#TvLAtVGOjog`9vzvW13^w!bq(-<AX2<Ug5ZD1O(VlZUUpb0
zZ7x)HE7Hu%DK3$x3=Y^OE{!XHYxX2lzWG#%dTk228gbA@@-#jCHUeaTA{?AJZw8bD
za6y8&q3iR`Tra(I!tzf<Z@8VC64Q@H)DHXJTT>b%c3;+rE^;Ig(>vRMrj(7yq89FD
zxD|(v;p8kpLugLQq74#Ehm`rT!ke}Lym?;l1Z>TU&ykl{TPv&*?fFajVP_RhKglov
z0w5sI9S8Tx8{156j+<oO^=^$LZXz@6LN2!V@|@6AxdIJS0}KxiD7}F=D~gbD4R2==
zut*CSU0as#s0xZcz?q1MzugXdDDe9}$k#W^wtMDR_=hd*;4OE6^2>U<Ve(OBCn3pe
z0V6SeWY6Y<Y3;R^rLh>R;@z{WLEYBvm+r~Y_+pxD=L}OD2j*}5F)7+xevsmzh(}k+
zzI)HZm<p_dM(#f8KdhROB{9hPQ7Ka6gefL@2Cyh0(v%0ArM@kr5TeNOFB$0Qk9G4f
zK6%jx;DgqU9Mm)u1CV9GhSry(MN`{>0-6SHT+2jFbbI?q9*JOV%dPHfC9Iu`mdqB=
zJPUYkx5SZtHs0}|8M+alim4_0?IA`X+MMs1`Y9JoOc11hW~o;m1Jj@-zfu%{6x8%f
zYW7K({%j1Y+Ke0Q><c+iY+=ww+)8iS6%!w$HzeZvMkLTj5~9XlLf5-le+|igZ0ww_
z#OMQp{dF}w3a%Pif61a0(|iP62EtjQ(P^E=FX|0bd*FttT{tjI3b5JYHN56~PY)pc
z;x~^MQh7<}n(Rq{z9+g%g&X%4plY^DpMhTMtm5mo_0+mFp6}F$z=_!O(-OO-eZ|OH
zi<elyNbTVZ%X1TwjbLx#T6s+k*$uN&G{#o2B@WPDE!-Q98*fc{N;60*z|?BH{wwUO
zmE|{3T+Rxj##>iM_~KkMlw`6di2M3y-E47UOfKM{q%tdyEl9<9k~OoMQnf<gPSb6t
zdk&)IatT*it^<;$&wJfbAyF?YyYN1tA}3g0WQB~2(9%Lka+s>N2;)H&&pBKZq8PUi
z=8F&n3z(<GG3{W%bII8lO%EQ9!qc}Y0s%MdXji70ZW<aZIJo~Q;2hF_N*Tv}hCH%&
z;qR0geFG3n2ls2U2u@p{+X!o3_%*2OD9y9dewz-zoYr9lK!&2<Tfblwz9kt#<a49e
z%h`2UO6rEjht`BNg(R3GuRRpAD>>?<TXy4)`?1N4sgBfFe?^}{XFPqTztJe6_VQ@J
z4&B~Rjp(^z0%Z<egn@8_<bS&2=xn-+k!gxC?Pe~dlNZ7wn##vV^)hg-%9(6Uxf+zZ
zVdCz0fTQz%W;n!^t-<z;cSQukVcfaTtKkL3THj>K>f#|Az!`G#FYuU^wGL`c6x_WW
zy^=-dphOk$l-F3*PZ1pbPiOg*T#uO6z{~Q5#db-KEWnMg<;a~(>Jfc4L!)lk5TwR4
z|JqaUqt-Q){;2I?8aDOB#Cn&D1Va#un5~J$@3Px&{d>eNJFDjf!S*__;A|;H&9|fl
zX(>Q)T_@ZR?ttoKL}cPJCe!LS>-zA|_51uI3Ac68bm~V=!7rt%0ZzjQ??PAlkF{O4
zJ!g$HgLnO%TpxDrA(29SH(RohRVmSnN~|&qZdZ2r(wfeCD<I0);oYyu8u|-xri*6W
z2Mi>$YgCfkqnLTxgi>?+_dHm?Bqi}#I}avhcYKhB`$2eON#5Wynx|*vmJ~mkl?_=N
zY8A5<gDwThxZ6y$(7D!}=;ONYt#n^g>e-Z}fvI?ciH%)faMfEf9R%ro*@E#GzVVfV
zM*Q9Et!yRl4RDD$tiId+n_X~SGo`m?P76(hcoOr7n=ceQh}EPUmd`*_60MQJFAOKe
zX+tSXe&BvM_?6r9D<gY)&B1SZXr%UhQQf?X^JRBJb%<!OJrhd|Z?Ux@!<36BEP3rF
zUPmqNDLr9DaFt+sm)X|%Hfqi4ES1`ZDfe0RKCea11#5tzCm9mnaC;&`8cGsSKDPbr
z-0l=V+liyF5NL&OD$eg8l*Je-{~{lkc-qa^F@FtjBMRiB<@hx^)P>7>FEM$akYc3^
zp<|_1-ccWEBN2;-kUE-9a`<-3Y(!9Qzcg2ZkhTC9D=mxv0gfKip|OlkoSd3TX6p6B
zqz;x)aM(2B=r~xskM|&`A!h91tTqjjkG6jM#zed(VW+q$S;e?pc$l69(LuViky&Gk
zRtj=7(@HkdKVn5MI&$Xb=0sfM0CaBjkb;o2ok7Jtw9G}Gl^Snr3bA<FZL-`mBIIPa
zeYpl3m7N%=33pF2_)CnMZPp?<Y-;NzQQGGE#Y~?Y<SU{%{bbkoxq_x`?>6I9!$0Vp
z2>(@$wo;d{eit5O2;I|WITYTYaooBoCbcrrso~hakH~kX2UxZ5tH#S|6<y{iyAm|G
zFz8@b9VuE_3Af)v8oeBWM+LYn83{hm1EdUnRExF~>R}-M5s>H*$nE;{&X}%AO8)7|
z0Jpp}^0gQHzQ_6$EMx;}#@*3Sd#n`t1{au*CtWJ~Ne$ibGD%t);slS4?^dhOdRja<
z2rG^pW`SQS>qq038>!5Rhkb8b!(dEWSVv>V`A2l7LY>c7KDNcBUZOX8eMnbc`NZyw
z%6veh9fV?bMR5qv_2jqz_!aa_W&(ClzYKu?#l=QXd&sW?-QdjDvd)GnLM4oh7K2nQ
z8o({KwVK2g=qCWn#z-cRs~ZBZDe*l7<{Uq5*WTTLEu!-6O-GylyDrz2qvayn`rC4#
zXfKkRWmc=o!Z6CU=PK*}U>SpxRk&pk??j+|`1<cq!W_M|_;A*Lm^sI{)idaqlCx99
zK(IUN`&w*sjlb8YV9zQAan$7uR(hjkwgY0;=Y+M8_H9`NDg`^fuTY^ZS*3z=C(l-{
zO_KVp7Zihb&$)`II{ePIoui{q9J2zQ_T$e6h^q<hp&5?zp~$fgn&%0u_6E@3{9lx&
zn@JY$`Sk3C;R>lqSSSV%wK?=}G!Fe}{CU1y@!eSfTAOv0;iTK>2cU8ATEJXc;{R9!
z`9_nk*w<*rtxQS9Sjnrc3#&MRh9N_}Cvb?I%A+EEWTPeet@M6Ub3Ij1$T*jn95<rR
zH2x=`g?04z!VCP+B?!K-tZ~^A!s|~=X>tthm5|9+Wf$4u44b6Nn?4g7#%@FQe2sC8
zU8IXND_x(pKqRSbXBFe6X7s=;uG_gYlYzoP6X+fx!foFMFPzl^2(R&2+T$BKHLJ6G
zE4+Ww=@!8-bpqhs(bBrmB(-=M4n%*T%%d4H<*L*;h}X5Y!FM}u!w~Px?X$6&H<CHk
zyM3{Rv>GLM>r{wy=+x_$#hBs%Nnz$;mqINGR$_Tiqa021eXjym`GhsRkPPExSG3Jh
zk6iHx>LQwo{v56X7akxf5}>nHKSm*F7@@cnvl4i5rf0ij{9(?Ut?Lk8Wt`{FRWg&M
z2qNbA|48l)0Ng1+D_>l5daUClK*KmlAw!6=lt-9G(0^4t;I-tH?D{V2frV$ug>7i8
z3)>S#$IjE!?=u#7TD(8en7#!b9DJ%R(4L$&ghlD(D)iw;F!^Q~B^I!L&eRr7CNmED
ziNzAzeZko>g}rHhcxfo_eVa>2!zDxvbl*Q0?x97_I96fDV9(1Y4UQeDE`@;G^M!GC
zxvwG7hbRIMRtxOp*FOsWUzuf5QkmR%2%_RiA(9rn7zB5|4cVW?mjrliRnID7EFPMb
zty3a>#9dQcQ*3x>aDy9@B^?~ynSvTJPJ`8IM`6b?mYDx{{3lHSqtab{$&3$PKXU3L
zSS&*|kuftCjL;q_4a!NKb=o*VSNzN1`F70%f9o8lDjS;P3z_brx_*kFf%MulBP}<*
z5E@-Nh>$Ogq_on2tBmI8KD&f7ap!&oJW^Eu&~ms0u{|i<D({t*hPwe(dq{!Mz^>D@
zH$7$Kb2-W8evL1*__HT?iXK9%<$;;^YDGoI&TDz_%xCab7V}k9T>~swYt}`rZLyC7
zP>{JU)cUGgajgW~{ZJywD0zeJg-rX!sk!iBeZNDwmB(cPgyeWuaYcp~H_NW-i7(JS
zuLR7HV&86+I(!7HSb0^*(*S%x1L-fu?Ug^-U0`yQ>@Q!AcDh|lLFG(o97<v{j^+Ep
zpcXlF*ZevV=(y?Z5ufqD>eJ0Jn+zInQP}&IHXjW=F8-5V5BW2o+{otMaI43;(_~+(
zg=PiSm)EG-*21Qb0C*M5@!lo}DV?J(_#7T=ToD}{+}VK3T|&WhLw)=Jg0SlRNk1}J
mt%mIZtUb7k&ZlgMUDL?P5<<-#-9Z^Uq|r(f`8wb%ZNsY2&=xlU

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clock_crosser.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_clock_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..ffb01a468473fb61a4aa62364f5813ab6fa8913c
GIT binary patch
literal 4472
zcmV-;5r^)J6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQl~sCSDs)oOAjfTN(;
z0G9i2xE$`1$|?PQGbNBksBQo@IY*7k_{_i3*iVEHolnR;i(lLT1z=Ct$Tx2zHcDj4
zTMr2J)5`2=a;Xtrw50aNT!ZoD_Ruxb{P?*`+Y0{ytL+C^T_!yn9fNh+i23>1i;D!4
zi=zI?{ncu)P7H$IaU#%f249UIdFN<Od8Bqn{bz?)?7=(1Q&4-PM_e{@Fop=BDp&m1
zw2(l5(IyDqJ-XP%u9;h%t(=CPmqdhjm~uom{N9{(yO9auVWAXZswRguU*6!KLRN8n
z`mA#6zT>U-F0}T67PeANh!C1pso`_b0glcA_Lyhy4mk1~-DSylI+&N=`Xl$yN}xNX
zY&U<l8Y!!~oxZpN;^1a9o`~eJ-yuNK5Z+jqH`@@$=-~JS(Oj6rYSP?b>d85sQ6=p#
z+eSFojK>nO_pTVQS90`F8Hs2V3jBeM(E4zR^MZ+Et(R<$$oFfJ2@GpSA1!_54Ke&e
z`j`2_GPgKDwZaf(byT%Q@wZ(5bN!;{!b06&Bt8sLdl?rp2;ul>FW;cp_)Rtu?3JoV
z%d|pD$xVk@Vs<gnj1V!LsFlApZ^i;+4$$81#~4Q2O&<`#37Jr97UEk;mZLZ`xV(vH
z*pL(s+@@@1YVeF+-%9#@7m1s{L_Yi3yk~gSjw|1;Q^7u5GKIa-3LL9(_V)H|d{zIj
znVg8;-lUL2OY7^uEa+eh1R?vIb59cT06B~s%eLNHMPaiAk0sRLmdy{n37s)A){$*0
z;FWYSk;&zb*uvcJHD1a7w%6DaEHL_QKZ024qwyB+8(paNad#%cV2cJzQvj{50gbrF
zrk&6qoYlr-iXxx?L!rvvd|G*Dx`j6CNyI%dS`1471)#tPdl(dl)zDeHjSzn}+jMM3
zQ!OX!wwOWd`~e6*Iosb7Otdike#!-33}u0}CBdWu7t68fG*y5ER!t0W?dI%CZS*9y
zEo=vAZN$Om0$>p#hTeP2uH~M>-r7yLJ_RrwkZ~A{`hn^f3@!8zaYzIUY{t3Wo8wmS
zL%u9UHsK^6<;b57N!H{+l+kvJqt)ua76zN7jIJDOQHNOHY)e)8dp40NGSR8E^=omu
z%T1?_kyz?nQo8h?jS)&TrlPBB#&DXP4aO#jj9mIT;+7yoaU^o!d%vA}$-LnS$uk0A
z_1TqaPewv9a>ceuW4GN!-jPpS(j*3Ru&cfrQ;>JU*^ZsZdfNxxOouHu<Q&AVeWp{s
zN!QYA{!c9g*CDb!6moAAc2cr#1Crok{K4nKnV_6gk5h)E=H|=<q1grN+*x6CkRvc1
z5#CAmZl(3pwI0W|_WR7v*a(d8NP(98s$N@TAWP0U{a05y%>L&R5$Nr5OB>4-Azx^?
zDAX>{z2ly3&8QltbUeR!Nj`=eGBXF^!!dH<4<f)r*lX4TshHb=JA|REc!%d?Nadec
z<QZUMO93|ME;xe3%Ok!+5y2|=#VdILTejeDuKPfpxDojKY+CXlGhF7UW%@Sz)^;#6
zslame+T&T_gl(R|4Jt-)2m@}C<|`ea9>xJA-l5YdUyWpTw;~z<I03{yy$k&>PtQ8q
z4Asev6kr5;PT<PLG;_oM6_m)|YEGHB9Zp#pJ4a+~XO2+ZsGDKUY9u~pR+JX@);bnD
zd3Z-HPH4Qcd}<_VPsqmZ6ZL<L2H-kZg~{`eJOQ)L!Nv4p4;#CB+Vm_$MGF>}`Qn6G
zPgn^E@fXN2Q^_u*B`gcgSqs&?%t$1vMb0QS=ak7r`W6LnK@P=qLkdGV4xxWIT&nTK
z!jk9PMU*^k`_R557m*wHwEr<|e%~rKm)xSF?p%VN+}nmzmDoQ-gPyWlxEvHf>7pIX
zk??H3L}+}T{mzvQf@|dngcCa2_!HBQNs*n?V+#6CM91BdynZ(8%S-SY;5Q-&^a&*f
z9eLVNh+d1sDK_;MsD(#@#X~Q%zABOnuFgd1w)4p2@Z_zCfos$vx~8VZMBFm;3{aM+
z7?^TPP;%g6X*tkmssJueME7yymOA6B5{g!DRnT+iFC1u@a4Suk!eFeZ*%;gX+rTgi
zv^w*tqL;vW6k59N93x-MoNkwV1xzGB3WBB4c=9g8vsFGVSjp^A0`+ZxEFDV?d-Eh2
z%~i(B$kQ4hCzQV+HE?SKh-0GKbi!;HJv)ep;rm9nWcWfq?ut|dmt3~^D>+k`Xmfcg
z?4kVd@k^pYMaqOZHzQV0H(y3}$kL@~Scn=xf_=;8(YN(~JdVYi<b-|EJ?eTHD6JJT
z@wcGQ`T{*Cl16$0n*<1<D#l0njo_{mXQQ9jZ!;t`M7#?y2D+_JQ0rx^OS@CjjUB=m
z5@QMl+BY3m!5!SOK<(;-0H&s@<R~x^(Ov~Fa_siz4$TR<u~Uzmu`#X;Hq`4K%Mfke
zO340kMSj{{XTbrh9T~oVwk>Xe<=&0%I`c2|2ny#Lss7#vVV8mXE?`Ycqaa}RFfGYh
zPlf4NTpVM6X?u%)_AQ65G7Xzp>S}`Ak!}ly8MGdD$h?{}=n%GrPT;4uYC6BjHLMN9
zdqOlAekn}c8L$m4M(o614~w=9{2*c0R>@)_fqrn&t>N*II5}AmOr1#<U2^TxG9Ul;
zZccKATx({y!&k**`(iA)9jeWg?%>nM9|D*?<5}$e4<Njioq!~fi>zP8x{e?o9)eQR
zQM0393la{(Q_Qy3I4H$#4Y)9x#?$#dqYOOC_@2CsHAbW-UpmG_&<qJkkn<iH+?F}`
zF$so+kj&u;90!M~LZL@4kcIKnU6~~3&MeK8Q&CF*?w<!qjQP9(y>b*pBo_4|e@yp^
zWE!@RxI>e=IRl`7bb;h%uR#szqC4ug6-f2ehdQ>H^m#u<CdyXW8+n#%xeW68>af6I
z&BLui>0Er~eOI7YW9@n*Y@1j0PpO}ntK=L@T<K5aE)&p9Cn;7Cim#HG5?hM+{=d5I
z{`BA`YatKqhwt)!!G6f@B*d#A?6>~DR#P1h)Sfug<>eAKPTO@AA#^9bhJ)#GG`^N)
zUczhChGd}JAUgM*vr-NB5&(PVjAPW?=Wd>!Sn%5hZ2-X-amB6+3B^w9A#!6!WfWTU
z5Fl4UfOp^(_FoyakElt*KfSKD1|c?Dq0s7ue$<i=)@ju^Dk0qPw>C<AIe>JRs}mz&
zr!>ZO5CQ!m)10iAmwp+Fm{?Aq&<tr0!jkUN?el?Bwc>{NEnP}}Dm^($7c4Y^vZX+U
z4v4c_c9AEWiIQ85GAwVZ3?V17nY8>+n7$oYz1m%J2V#LEI=!h6+7QD>3_5lJ&3jO$
z0(_9QS(q6K!mca^Xd%m5%0>C5|AC4Ok=a#aKU;-VWdxN6R%%dzJll~*0w+%KjamsW
zUi-{Q(z^$zqoDLdB32TecJ~V`2>n-a%Iq)qdl2@Zgt3LP6bEsMi6ccwt0Vsgf&l&j
z2Y^`UAo%rY|EoN{0$LhuRklHylqM9;6`$``o}ynHZI@<8y0nmD;EZ=9EzZ}fRy063
z^Ifr#2F$D&o&g13#-PF5oWWW7;>64%xZP(U{iu=C>Kgv>{9LOxY__H3Waf77MH*iS
z-G0BZ)TEe9WJF$jL<S>`Z6Ct1U<!K?2)CcPIDi_oHE|uluZ}q<)6J48F22uiZ%}Hy
zHSakTXox*cp^@GRm!_pmyeKZIR}_Zs;(55gP_-sXJ3MY|n7=Y<r37OJ>(JAyU89AA
zkahAN4|UvjMB3a7$@?^pL*T+&E(&|zR>ylJfglD>Q2hW$b5(80!e}Fl&hfjO7;!gy
zmM^4gfnNkBu@=vK!Hj&I^Fu6oq}u?$%1rK43@>&lxyAw}7C*!zezS|<4PF)>1P$r3
z#tFBiKK_?b{E3A}IV6C}F!Y|R6i&PQkYw7+An^|a?<gQ|VNu<K)@B5aThN&SIFTj`
zPKvynB?eGEppb5EKYDchYxm0u+}5VBoP9Imkmse3X6cyE)^jRl&|W=?n)lz71+H|m
z@;}R|0`r?^MD3~3wl56<Jym4i^3m#H&TBBml(dENR$w^~hP|Y4E9@ZxJ_aV6J@f<1
z)rwe8@mpVK`mkPBX1bj*(Xd)?W<nk>(qbDGBDTuFmc)!O9`fh{*Wn=UIB=MCyHa4<
z^;C-M&Jc}t`UsaI^;Z1>$5-)o<O4x&eti{X3b`qkMpL8T9$9woJgR7V$nX#UOg;fw
zz?a}^eV--%HtMGV3N??ghdUfXddA6o8>z?qrkm*NkY33kqzV@rfqywl<}l-b=n|}`
z!@uqE+mkBTE&o0o#91AK%lB_?I?mJ=jEhkTamQF>uVU%3d2?xYw}WmGIhuUoRDE>>
zVe$Nc7X*y9K4MeaF2jK6z@vO3&!A9rKJ1a8RA?l#v86eRq0k;Dqc%7LK)r@=^#Xu8
zu-j4QXPM^y?Ir%N!<cXsK-Gi_EamvVti!{&?gxkREv3u~8FW=%kOltibK7nHEljKV
z<{ntF!WfSA5ZZ!C@wy-{1|6DhCobIAc0C)$)pZmtAIodm$}(+MqN#IGN)wunq(m#4
zR;WnhgBtW*^oD&SKG7Myzs@J;0%3ceg(^St!$(Sa_Kz7?Y!R2Q0gLtO)8nmt`A}<i
K@VrPZPzti5Kc`;+

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328checker.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328checker.v
new file mode 100644
index 0000000000000000000000000000000000000000..9e6885c1466897f0cbd7d287c55221953870fa40
GIT binary patch
literal 4616
zcmV+j68G(k6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btk*7^mpx{o*9@&kNHJ#QCjNG=-{F
z86@O47{c@jV_!@9ad&Ken;Dctg!hNSQ#nmw`bXB}4GKg;#bi1MehQTmDOmKhvypYL
zN4m!eXqd0Z#KTxUeGw<3cUbIlPC~9C3(xmc7*b}V&{EaG2O%Ovz<H|r3VAF~KDR~c
z<=P{2Zx7o)O77dd%I(MIwr7OI%VMs(#06J{o%U2ewg^M(XbF?iFjVKK@WVv0ELyT~
zm;?OVDv}QZD9{;vWbQY3oYo<BDJT1HxU#t;Yndn~nbFH?IWq2-ryfUhGl7=qzXM8q
z8ua#uE2qaG$vWtcRgk%S%l;yQ0{#Q2;sm4C=jeXrj9s<KtTFJmi)8bXBeky3L&vM?
zgAyI2G#kF(bUe}H;__(<NLw=<a$x>8YaxQvc8Api80yVl+J<Dtyxzse>^+!q*4yK-
z{7_k+3bvX_UBei9<ZNY+=Dlgq^}&2XxRCKdenR7ETLU*f1F9RZ;&t7tuwt}{a8Yu#
zb<LK->_2ns=6BEU`v+f;^&LT$$uHHLh4gCoEE)jX=t!c!bxY)G^p%*gvn6VaKu@#c
zHtY)iF~A!5Akm7`dSssej9v?U&Y^4uS{w)1kI910ezdqAtbXtc7{S@g^!|ncgwEDB
zjlvm|>VFqdU25p(67G_k=DwT(TPs9e(H(NG2l?LNQV&SkE!i?I?rk-yLHqr}uXFR7
z@uRlvQ7YV=ogiCWH#?=LjA3$L{g=|z@EnnI#bk*VB@ZjKcZ(TXAwgpqN({JE_VsmZ
zqms=dX9XpJVALq3M*CMi3e0rV6NeDx66a<ZTjkXcb&N{wI<KDTiDUUEJ1OLGg<_zS
z`b$9HML98bjKw{A<W1U<dl0Du(lYyJ)txnK3knYkxtg6i$_@;H1ztX(rNzAi+m-7F
zmQSa#3z6512BsyRKXbp__=1EjO-nxMAD9kSZ(B^4@^I$s>J@UP&LDda!FxPCa$X<&
zOLFkG(P^524Q!v*UBY%>F_$SxpLT5uhS<ktvDp66^>cs`VB9i$;}j94<yau~Eak^2
zhcp(E>^ce*yzY$59KL6&T(~Zzsp04k*Hsy(?ywxhjGQmX=v1*8>ts%Po^b6yK0U>G
ze>&9pw~%Zrz#+j0IwtQn@9IUf8^yqcZx~hH{Z6*<E3aQqj{?8?UQ#3%)<8YVtgvKO
z84mK8;D-JR_hP7utOT{8xYF*H(;g2<&Vmt5v7TO?I$+;d)Kf1l#@*82pkKgfg(O+h
z0H1V#*hr0yMb2jU3bp?xIp@X!*l0ba*n++<|40@q&$dou%=ZSVx&qZVMA{77rE?*a
zmIieNcq>%P1tB{@^w~jPQOajA<sr1KMVBS?3157<eV4xp;7gbiQ=u%j6tpVS2)UA^
z#aglZK%}Ch+Gh<|NNdQ#Q)Z8c63R=5Vbi8~X_rqV(w*8=cAEj9s4#O1dUevR7>7Gz
zkoljxvlO23E~3gyn%M<`jco_(W5cpAIT^QCTy(3#ps1cDuiMiZx|CB)emvgV$>!iF
z!2xxRfn57T7yv(FwOV7LuUATw)G`3Mhk&S#hd>xSn>sEyI8iNkE#>YHs~fI_+~P-n
zViO9~)VOlgB6$zF^GRa~vg`x|D{8qx9iRGJAHHx=F9i{YAqew<oqL+MCaDq{>Zn>%
z!wMbN91i2I+f@YP!YvdDse~W^=7!#m{^r;HCSOMQFdt+CXQJ!rwpwKKyp3%CF(V;a
z&65DXZ!b(<4E3U<Y%R_g5Tv`K@`1%_hkOVR*X#TkV)0g`MP)ijgA@}O7u%M2&@7zB
zdX58-f?n6`r|o#X=>%ozpoCGJ1CxD5i`{_<Lxq6ZHUbweOmGoe-CobPf!{)M-qqa-
zb$~20=_n)Ez3EyU|I2&}LaWHwkM8VWS1_SGmHoF=vyCoes%HwN1hRimVPwqN?a{ul
zB4yoi=bWfptj$AZNv-WxZOm#{8>F1<pe9<<yy^yXVVY0nMEg;k$_jabYxP0gRaTWp
zre(EJo5Fqv=1*(TJnPs5pkFQK+VpXKG|VBa9a_yU3{P4wrHMTzUKhRi`$5aEk{Nf!
zmk9R&PfDrCkTU>eBuz^V3SOlRtpQ#hRTS{3CB(a_HOe%nJT^%X+#ER|<FK9crHv%q
zP3JRjsmi)JGIu1!BEXZtY;fOon*@ixkpKj;axMKLR7paxaHL!co`SSqcn>@6Bzor_
za*WzZiukLvrDP+VdAlM^8tSnytIlNg`(^H`w#yL}{)4^h#wuF{T-*X=u0t1b2U+tY
zpl@5eS;Rmj6dZPQqEteZaBj7(SiSIdFC{FA?=E5z@vX&riR=8pZK5@Zzzufw?lWTa
zH8>;A!^+j0gH{xl3>4>79l5)LVO}6r=ka}$R$u%HC0JxA#@9lt9PYh<>ZKr0U|YiP
zp~R`m0nq(gYow6PIRgb=`WoF4uLCuvWw|#)6SZ5ObrCM%!BiXfJE(gyxV$iv94puU
zGWWXEF^2mMPkO1WaS`SDEGE=|$fi02yAB2;L!`$5Tao$ZOgPsXNjVzgU2-|?lg@?P
zxW~7rn4Q~0X-f6Y4CkvU7d|erFHYS(rtrbt^MTNBu$7q3Bken+l(n01+#x>HhPk(s
z<TkaS7ejDi9AiidL=KdxA<HOOSUhT-T3${WyO#O)pBbr;#D>y<1D4wY{`Ctg_q<>u
zaZduZ^-x?E^5hT18R=QLF;Ex>CJ!5%a=Onw^l(171}nAxGOs@-pDT<{mo+?l`m##!
zEveUse05nUN6V=>7!7h|GV~o5&<TuvtZu|N8m~*YgLM#wExIoo205F%5a9FB%M>1?
zEBQKC7!0-KdJm$5e|S<(;jrw?_G+J1i12V%KsJk&|Ao)n2DK)x3uxRyWkuePWHQzJ
z^Va6bf@Vw)!PaEU{OHGjCri^fMUOSj*!R7)Icx%05N=LITZmN=vBEpkt`ITh^A!T;
znM<G(LY?X-sbm`wA{cJ-OD>>|icUF#JpBG;F}xtEl#`U=OJm7(=u}sdO^*fZ2}KNV
zaIr4u?5@jGvQD4GW0mJ?7kLRn7H~$|2zqThdQKXd_6>7VB7iWE&U0#-*!oX7p4dU{
zq%mWOf`*`6W?%P(sI@pA_S1{FsY-0(FZ@9aZlK;F<yt5`-(D~G5M=V2keii!2atn@
z%jw~sx>|Cb=0<CGX;vEt+D;jZi2#MXWqyO^+vY1z@-=kk<v*cfuPRG%^h(gkX9K(0
zom;EdDPCdOv*5u2z`K~8&u{0Nj3!#eTf|0BeJfdOS4uh7&xm{xDBx~vfMv>?%o99l
zUW~ww<1-1y8ow!Vav$XZUs_K?sYgGlI@Rq~^KKLAvITm~+?;!h|1Y{cM9DKHMU}zv
zjud@jo#Iy<`j_z+Oj+0mNl5NyH&~=`FQhC%E?;q^hj7op2JRO|QLC1Bk)c8thZleZ
zH)QkQLJF$WE{_(E^9=AT>0p*f{*E)~pn}8s2UUX!KDe=6x~=2K=Y(zDEmO@+ti=<W
zkpNubpZeCCmET#r<+Qt+0Sudejp$)r5}g2XpU1P{<R24~F<RWsQ0a7VFx<{FQ}vfu
zLz@Kqat^}#iRk<kUgH1^$YZb@(`InO9W%45N#N|<dGDk6{7$XE1Y&yh8u~et54RUF
z%B|5UlOm5D($0S((xm6}xf@KV)`{_oBwOKpczdGEHHSTx!cB$kGS=?(*bFaC6*V*#
zNyA||eGw1sQiuiXaMRLv-b(5<V<K-f@;9{PuZTUt843hyNN3<-&iSfhd!DT6K9r-}
zbucOO(6{cuBV9Lm#tiV$dDLGb_eq&=plvf6LC=XIYO1PI7{m(aj>Bq~SwrCLpuEc4
zh>qVXFX-8_gc<d5zwof+sH-OAHFvQCSewUB1WB#QfykB`u`0lSV$lUY1!uK5n`V1C
z{+w32AtuG|18Z+?f}(=Ae+`MO&j_CkT=`+`+SlSWCvSzy{knh4Y-5RR&qRU3$AMpq
zgQN$Oo09IBtY{{p+vKklB8IPzoXuI6_G?W3ot#YG90Ra`6LHdQ9k-j*ADkVZ1M?`x
z6^aBiLWv>d7tpF=OWs^`^>HSeEr|gGa|;_ATNDl~bH8jGkuP~V0gQIHWuu!k0B~iQ
zj6q<zT4nDch!!%xUTI=97!<$uX3rmR0k@3!MhHKQZKNQc7&SdLtWoi5-fY2q+~ap`
zcj`VD=Y>F3mDcv>e0*r!BdVBD$r5YGHmFWW-|4Ag_b_090$aOx3ja|eSc9;D@$^wx
z@qDHRaTkNE%`ZtT#A>2UWgzn+Y!q5LMpps-dvR$+Xe8(fBR6b>Q`u=U9TRHwQ}uhg
zjer)R2evOl3g2k_w3tl~xTWV$f@M)4#p#X0mI0hJf*S@oF)`3jaxiJ!-Pl)wka)W;
z|IXp5xGr_C^t8`dXWc4?O1jt<XX>Yff6eC8>V#@Uc|`uvAcO-{Pe>yO5ZWcX8eF^i
yTrCZ(IUntoz86WCO)O<Wa%^cm+>D!}s=>rD02}vNg)-`L;yyC{aavlx<ayi!!0V*|

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328generator.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc328generator.v
new file mode 100644
index 0000000000000000000000000000000000000000..8d198589ebda15440934a9de555545c6206d2be1
GIT binary patch
literal 3512
zcmV;p4M*~e6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btk*7^mpx{o*7%WWlSXzj7UN*P{5I
z`!2i|Y=AhN)%(o;BwbM9u)szN+CM3AE5NyjPUIT35J{s@KBm2d(*me?Tz#F`A-|H%
zba>ve?J`|yp%=qb93Fz*Xz$>2JPNA`d5`g%ro90QPFhTjxKQ(>-GT3ei;uT|j;yun
z!9O<36+tIbb}cb%to-HU2G#y;zmp4QV%^a_I2IrwNF4>3Z6M(WGii#rcv`|e$W5WJ
z^cD0w76pZye;zijk+DMiG!d~;x^_&l`b=A`uqv8-Ce)XYx@b-|02eMok(ygI8#|dm
z*-s3;Vk8RI(hzo=yb;ESE&UtcI*>Tx!w|mT#9&gVk!<9~WlSflpM-jAqjTr7><=&8
zAoFi;&3`+$X+G^bj5D?Fz+s*aX4+__6DSq`+|HD%p1gA0b<HnXQiLTB2c0}`hKge6
z{Y}uWukdn@);ri*wO(l7=|6g8NJMHA1>$hw&MZ*2Oi;~U+YBZTP^=kuWp<}<0(iiM
zGU93h{o-oBma0p4(CnQ_Yjd2!op>Bg>L2VpbCii&`GE~m@zVZ`JcKoJAXkU8*Hr<w
z6L%p?mYpOOyw$o}yrny7!_cCO$|c#kYIDbjL^W6lc)fkdoGGhSZ8fb7s<}Oq{Vtum
z`huZdTC#ElZ~{bo-r9X~-xS)>XYNogu8}Ur{9%N=op#<lhcLf{{MA2}j<?{=y81cl
zqCAs?nF5Ti@Sv3AVjzbfqzq^ZOR)%9Z;R{>Jb)EVcR>p=0%gFEAcglkhzYVj<_=z<
zQDNXP0EXoNr|V)rXM6hi3rUjJfo1YcvL1Rn7R+qlrF>RZXRt(O8K!;}W?@;p<%_l0
zGa^+W8;T`?FOLT6A{bI$XY&L-X2+D@;EHBh?jXV=nfcBxKNX7=8RIQm@eDERXfd>`
zU(rjD5t)ABh5`Hdv>8m(q9QYnMg%0XK7o|B&G;E%n~*p?3>d*H&z6=op<ACb*7n#r
zpl2x^?AC=jCAt2~h-wi4ggdMdGlopZmYAEzz$BpquBY95g|OJUuOG8eAd_bPOLyg^
z;Ar;%LrLM~N-Ecsw?hd*9@3sLU*61{*pitnsVfBg=vhx73OT}<wEe{}R0(pYN_@wc
zNqc#Kc@o<R9rCIbcJG#I4lS}ZKS0a2f685$ub^CsybSK^*tS#hOhxa@zNOdl)ZbD$
zeeUI7-l90AqC{;+OPxaQ1c02sIZ$7(;sAK0GuwgU!E(r_ThbVfV0C|h0#8{gX4xnt
zx#u&@@1wJqq3h)?mD0JlV4+5c2Jm(Ns5WWsQqJy29L2^lq~fJdSzfjNbh1LL`oLjD
zIefp~DD7<Z-GVilEQ%O?NqI?bWJ=K7I9LdbrLMZTvpCNlsQxuthUz2dR<%l%St=W9
z1qXcRxH4U3=BoG^2W^SG?JcEN2dMB}tma2*2H6-mImTda{5E7|dc9C$y6m-TEM2e0
zOvroQf)CmTg;X8re&F^#m3#&z{KODYBD>+-!LTtEub85N3d+S3oqzFpv8dt;-xCN<
zGeabR*OdrMZAV`gWO7vIFnQ$Su_?a}H@GAnuU-}w*T>Vr!gpbCw)1Cam8;>8+%a?I
zS4LV`)F~eXr;-jHz_Hb~VcJGKSA3bWf@0B<mNLY-{xKR!lEKIk?dlb7+lzXn#V77f
zm~CFXGx_I(vb~{Z01kq;F+v1;gA48<$4+f0xP}MTlWR{lli9f0cU`LC+HYJ`+h1cV
z<?cblY$S}1b#$Pl;OV=f(w*`>7QKlteMS!UYcjrZl}O5SfS#dpVQpFo5YRN7TCG)4
z*@z~-9H7o1MrkqdSE00`x~s!QT1~~f^N`TMro6Q>|3hz-e|&9k<BkaB^mF(<3rm|0
zNRTy~VGWd_8*1dd2Wpe{i6wNvy(Kz({Z55s)~q38oCxJwV9OQJ5t=U2B!+5(jo$@Q
z=u(>k*D<m&prI}J7;D{`+!giqqru&`pbfF{P30VAGL)*0vQVp~Svm$w+_g_3IeiAD
z@kLsiiv;It!h7>D?`X10*Ov#|X#qDvr_rN0ORFv@+0gdSBOI`l?l9n{2=5i+XH)aB
z4!cwapB=OyisIDV6Zn_?kxz1m!x_;oD^qGd_>1*YM2OpmmM2A2Q^wirY@?2kUW0;@
za@PORzw6j-I)|GIL_NO;9D|S0lvN1o!-s)dHYXjw{ZuQ)!}gAS!sqyZs)UP059%nJ
zs`JqW{*~@dW*6Bzgu?@>+hXopE%#m>mkQb0AR)L8L+6X{F@J3Gap68vu5Kq+g&PVK
z-&V@UB)K{cDvp%$+mf1?8U7Q6UpqX<hUkxvM>Vmz#8+4(j7LN~Gu**r-v@C>2!rlL
z2JYgQ{-Ha)1&_=B(nWG+SrDZg6V=63;%C^2oCb6y%r+^3Nl#nLDFcE!Z`J&jr}UM1
zUqnzt{&2-4S)1hAdAdQy%mztp($O*^##aONbca4J{3Nd=biF{w4x4=6p1omZ|LL*j
zE&+DpP9W`h!%c|{tesO?JY7w}aZ&>{=!=jVj&WzWhGo)Wht~-WIisvt*(jtB@t1^3
zHR!1l^Qahy1<x2+y6cwPEst}~Y^VB2y=}BE>m|~eI0h+Xnp55K?$*Z=E*bD2xUIuy
zxk3a&J;_?iLTL8^f>(Z{{H~=|OQUS=>h{$RQkeiUV9=1AKyhAMPgw_C2R@V4y~)QX
z$9s=QEhFAV?JBPct|w7wn0aMaF+GeBY>#JwbWc8eZ;fkZB(!?Vvr~nye*ba2_WTJy
zT;m9eE=h;>uO>o-tJa2T$o7xfwLA4n?Nb!Z{4+3UL~n=~XhUx%uqArVy^w83X6~BN
z{{bM{(8WQZp<Oo4Tj(}dyVVB|c?S~5=zM}zB_nj;lAwKTat<Q3hKnPoPl~&l)AZJ`
z+GfTzRm7c%!35~6E5U)etP-nrTZRT_;@7(V6(x;q8{DTMQ$PzI(4nGs<k(l5jk<!3
zbOzz?FG(I#DU)3kZ4Vddh9(44=_du}VELN4OFq^yZ`}ra5dIP{fvw#=$ej1r!2YV1
mwGSi@N6D63Ev$^1i;lGAphR%>ufjj7Xuc7s>})IQt~^F%Hqj3N

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v
new file mode 100644
index 0000000000000000000000000000000000000000..1b7d3e8a6765a5ee3cb456fb8bbc729164dd1ea7
GIT binary patch
literal 2656
zcmV-m3ZM0h6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btk*7^mpx{o*8SA*GoowwJWdGoL@`
zl209Ea9yd37;#}Hcn)Ql+Udd0k~!UmuU4p#)9-cq6%hI8%AeiQag(L>RHo8o2IiE2
zZ)|jAc-d#`t?g(u<2o}hS;TAu04n8>Obm$m9-omSSL%A0Mo?^7V*639`#zrXF%>aC
zFpfp9yMX#Z^qkPs4`;>|OJ^^&v6P9T|D2E%33<~27w>8B)}3ORb{qHz;t5Gfh~rGE
z<`mi+qzn9aq&GnCcA+D8e-$8cHp}2sa&Pllw8v96t4{BQtNflTpl-Y9myTcj$$3s%
z(Zje((P=!Lhmzt}g^Ss}r6!Ir-_8eZRgqNb6Qpv+#_u3Q#;g$9qT?r&G3``*iG|{i
z33O(Ipuoo$Z!m@<@DBuTSnOCbVHyaYuHmORb#*HN(MC41E0f4I`=9xzKbnC3fUR|p
z@M(_Ib#xrX8!3Yx?Yb1^;7lR)Udznhp|s$7Lbc(^p6Eg93WHmGIBQ0pf7_T1)E(*Y
zzEQkp<;;o)=zq~gJhY1-cXoiv09C~!|NKguagU)`^hql?|8)HQE&irem#F_75NsR0
zI&Ov3VYi^7AWw1WYlmP%@@(Ss<bh}*z{sRd(K{G}Qe$ahMr$1?w3TT3(YUOZ2XKxN
zA>KLHF9)~AAHVjitQPGFYt)3UGwSQRHTfNWL@b_j<drX#>*+fH7^sFN<MUA90znKh
zU5_dHtrNxHw@u_Ji^l283)oM3<B8$2*VAdzij0$itH_|Rn5@Yj;C2BHE+gp(xl_-c
zBE3NDoaZDjhd|p{&Kg&Lk6TUFF?|6Gymy+$Wwf!<C9+n7b{JOc>BU?-&hW_LhYTE|
z<UcUzqh@M5op~aD#f5_KM&aUE|E*t?nY&L??w&|C0@RY{>Eg$wg>SeZo@n)M_x)^8
zcq>`E9Pf_l7g%85)W!O4n=mD|wfApcXBWAD@BcWx!AqBOdnn?oIBNE+4f5Ub^i(a#
z69cJ18B<qpszD`5FiHX%BMykc4$`W56sirTAy(*O{MlXK@3&pv(#77-FS&pwF!Vi_
z0J>y2Xq7sB2#f`Nhj&Sr|9<oH^tc4KdWT6#pH$<{LyW7kHJ9d7pY<G0mI2e(SLJsI
zVvpNj-FJW7Xt0qxdp<c|J4QXuaYingUN9nye!eKNj$WIVp<`aSyxBNxqjo?J#bNh4
zLZ{MFhd8m#3*4Vz`Cx2vIDc*5p=Mor-Q>@3#0YvLU@(EfjYnV2%a@SIxK_L^2pnGx
zcIbJ>$uEK&A|)kJzCsJ`N`Kz^y>A4~ugNhR;+M#}m=pmz&e98=6M7az_t^JZIi1UF
zA<I~|M2IIsOtUYs<uvjng^upM*eEW85g+1<eL0l>4(&j)?Y>kXYK|g#!d5~m7*}6d
z!Egf)of4F*0^(ELQ20;irWZpbAmi=NVLbLtu7*m^8Ayd84b&Hb*osN>e#i!pqA9SQ
z8{Ki25`gW|UR2VP)3Rhm)q#`g$cJ2?b<a5K)#32{GH0<+V#cN9cM&Y;`nbj=m;qF1
zgTtrs&N^NsJ<>CCa(n?D!(G9)X%^Ws1cXbFNspxB8%u2wMX`}V367r~dX>8y6z(9F
z_{hxNB1J(J5Te8Uw|H62)00@D)O5eqxhTB2-gVk!lbLNkyq&5W?oMvxq4-D(_wtUD
zzOkxlOlEnoP5RI3CKn{mV4u0Lgy++XMDhPh&9m2R^35%2EUdvO%(n|g%!)C2LQQ9l
z)WH(cNAN3ISL|@*=4D|LHo@eBP_(x44$W?d9GPMC*=cJzMK)Qtf?-8*d2+W~UV?%`
z@9ylnf3-rOIs5ERu!H~_#y){s&{<Z3rW~{*k+}E|Zi1>$y6!QI%%W|aRCTpUn%nEk
zWBeD65Gt;)Aq;=&p}&~y)jj|WVT`JQg>WcPz}hQd(x<(8i~7Q#b2Yx!xh;a5Ra483
O1Fjh3Wz6TGTG7ZuYCqEe

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32galois8.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_crc32galois8.v
new file mode 100644
index 0000000000000000000000000000000000000000..18871cff37c441128909db6dac28667b0e32afd5
GIT binary patch
literal 7784
zcmV-u9+%;Z6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btk*7^mpx{o*77Wor5R|CId^W_&{j
z`zWQdZ5ZVRUIXdWDNhN#QmMU$`i2)|3kf*1o8^K(QlIu=5?(l*vYh7}iB?T|K0cWE
zQhYtee{C}P*D(+*&y0?}YzF%JlR}^f+a$aD!rW6{hYV|$3tS*&6?IaFFaU#n*yn=Z
ziqhiiGC~EhkP;uo!QO`mR0*zM&?^{QWoI`S>KcOS?Iu~I*nc<pWJ1rXdZ4d+q<8<s
z#XMEK*`uKj(DB<}>QHDtLYjs=-^?Tnv{K;8`T5h$zi~w=&V+@+XPNc8v7&$&!$*uV
zIRW@X*JrS2C9z<`jMzdwcX-EeBT!Ti=J$~+t&eQ3m_y4|qryV&5!qYK4_L96Bf@CY
zzwl2FBrC^lpI>w^--1AMV-oHUunePf;-VGV2yxWyfl_yZWnRA`;Q`y2qDlhfL>m-{
zIu0K)=%=hVkz>iBlB`h^64+^iR+0CoJ)yWLxxd+s@l2H0Cuq?$Kbif2r3s)Vy554;
zR(b;Cytq~Hm34l|Yv_yNF`weDytCLP-E13Hw=RCbM)^Y1+<b&QM|wtV9CA!<LrRlK
zuyp-gM6*L)YHPbRn$9?YK2pkFR%eatr8mo<j>SK<tsizESpj3<t8qXL*?-0N*~j2C
zRiZ+f?g#d7BXaS&F4X=ymYlOCrGs1>N^6%S07WbxzO9UGwT)86IcP&GG5@ot$#$q-
z^Um&JeG&oC&w6^|9!*=5T@m_xk!lR5K4gd0+I5OmkO7d|F%u29P@L;UwnT=tCKL~d
zK5MOFKGFJJ%)Ag)RkLp4Nw9txzjfu;98UNptVUP?Ww4D*35#cm^uU3Ha9lDft@hGr
z8=~2PGWpZKh~r@+GXd6S4Pu?56xZWT8FnH|(=Vn-GrL$o*YRgrtI<oxEVftSUMw?u
zqF2g*SXbR~T(^ekzrl#_eX;46gs44yyuVR8-kQ#hpyTF({HT*1)O(p*rKL^{bcAkz
zwhY8RhqkH;=_Wy1<a^jojofJ@uE$YO1U1JYWw(dz!eh8b282N+Sq_>pYAv|L`4&?E
z!}a~_V~!$Y?&a}?n_=uT5fAek?^%+E+AR6+W-}Q?D=Ao|6bJ(Yq9||=i{AZ$rkIBs
zS<K$eMU)%`i^*t?WS6%iB_JODF0T0t$itWyAx5If4SB;;!ermpuPG_PwvP{VsGNb#
zOIxI*9MBin5kgO4@*n*qZB6&jbQ1iEG->OL*PNGcQlcZWiouDp9n2P`!yJ_#e(AHK
z?o4NFcMt{HE<F~0zZHou#j$|l`BPaBb;>(VjJYO_gj=@l;Qh_VjUUJLSYBzNhp%tK
zW_|=M^zMdm!6q)lJ{m{SFbL@`Uhn^|Ov^7Lyr6Tr6;u&JG){iNT3)|@z%4r8ho~hL
zQ#HI@T&wu0=__rlUko1JOrcl6Mqc;|l1J>!eB1Z~4!JQQQI5GEij(?T*Y@;o8*Qe3
zJ--0vt^<lAmR_Ihf#$RH_LK_yV9(X0Jk8Dh0)uERLDAMD@CV)5T2f@|ly~tF7>e^v
zoJ51kHUO_r@akR;@+a+FP$Z)Jo_kwlelLcM(IzRrjW7Y9k|o7&HeN%&@nZWhASKEG
zn_*Ie@p_mYQj1{V_cFC+O1T`I66}$_F1RCS0^?u?_cQ<J#NeL7@pEYY7k@@Q1r_8R
zm(*e>`|Qb)iD_6(C9jLbu+?iLNwg!S9k;{fyw~X?kJgE{;LjP^R<@M$R@Q0)n_6`(
z*aw<J%FR1sz~ffQZ?P54m6J~+c=GoH7*$l+bD6AGCigyH%3Au73XHB(x1)a}StcHW
zUPv|nh=-p>bP5gDNI~3~J8oe0ifm1NK34RbY<+Uq+GR3Ikq05+BRN4V-#}LOL?F-{
zKjUruVQ*g#I1KtxaB|i#cKs&&w8I;gg2Ly$I_nL6x@?fKE!^1fg-kWhsOE>mOfBNV
zuX6Yt5tJ~3Htf(6{4hF(Kx#;T&L<3XS503RfLN0kQLz-NgM>8vn8McJ%a7|xAV%k<
zBD#}Wj8j?ESa!qafUO^mSJ=NJSe1R{)%KpQG_078hTZ6~KekJCV!0kL&<a(NTPIhe
za=~p4d)27Bto^kl2yq8-b8F_JoPMd74J#M!zFTsYX5kQ6=q?k5!QQ&jL>#6YHwTzv
zBBBt!=B1Jh9jTyL5(NH*Q};kJ#Uja7I@(pu8%!{{Xs5_z+ySZg*;MMFCMuoX4UWna
z5uy10wu~xjWr^G$k?d_-S_v(S!`>e-6!cG}u}Jlx3a66|ROJ_R(2V(@<)c>$a)0Ra
zI#6Bf#8F}<cG5beU(df9b8JtppLc}${Ot6^enM7%zr6p!B~Ul?I6GCbcUk5BOd3Cw
zREiFuc8K9FLc<I)NPaA?5jp?)h6nl}?I%ZaKE!)dg{nC|vN-c~6U6M`pP50WIQYLu
zl{qO>mBanME8WdR+|CsYaj{WagTthz{wg5J19##8F$odPpYI1dAzfcyvA<$-nJ;k*
zAQ%xdVP2yo19d4n4PkLV`1p{AeK7U`$RH1wmSE$v75qEx54sUTaG@9;smHlG;iqLl
z*^i5ntx%5&&hhBlYex?WXHT-}sC9;c+XwjaG>YqY%6P(szWHUh7ZZAai@wkHljGO&
zl8!nIrzM+e%k&<q8-=yk3Gg{1hWZ?pazg;|Zj+U&4<!5-T;u4Yr?9xa50Xrh6U!;i
zKd>w3(6HO-=aO-AAN}&ly?B9|oxJCC#L);w?UgziVc^NoR;!a&?W5;|JNvuuQX$9A
z1h__G@cFoSpRkgr8JTJITNsC(H#{?s9T;94_UW*{bR7CW$hP{s&uis>ec4L}1@7#H
z+H3yN^(iU>CX!n=?(kQT>z+y;zH67GA(m30ktVA$Y7d9t9xIPlPIZkjI2<~?FJvg_
z&HbpsU)!+F5KB<ok)g$=21J0tvtK?k6Kx$yI_;y8V#qehDA8gPD}zOW^EB2!xpRED
zNoW>t4bd`JdG|NCH07c1v=_<D0h8iZy>w4+Fi`+xM;Ja$q?<Z6dq|UwB-E9WDfY-4
zswcL*(@vI`SGd9Q{4nj+=O{rko$7hwh=nLh!ermEyMUm)g<)c-_AgK%)*i2*TJ}_>
zsms@9pJz0AEe^;8hFE!ybc_5s>Tyr<#74&o9y`0rGGOTv5De$xo%@SNU%?I*r|01R
z!b&R5YZnf0Gggs=_tL>5NNXwpy_sWGyKl!lWwy3Mj9CR{w1;W+selezg-SKN6iIAx
z55E44NgvIzO&%ZV(^B6t^S5(*MfG8YzR1xIyuB(p5=$DoPyEq<sr&URT?>JsZsqXd
zYJL~oQ22-Rp~vt{76{T)<Gh;t1vS&1y;khV&Gf;M4I>-Jm^H8^<vZA`wcq}+)53uN
z04{UMd1%f|2^VUavcf)XU~HT_O(Gdy#e5hps&C!r0(xn|_J=3!AR)aG+HQ-$6|()p
zv^`2(j52q(H=%E{>5dSPy~SmMD;pj57+N{~J2=}ym4Vs^Zm;csNT|#7)v8<yR_Z`u
zqTpg+#Kkvy9Xdw#q3Tra?(FnJCUMxjRQymd1MBpAru7G<A=JzUAaeiPm1gaWdxY%{
zuArLxES*eh$yH<wsc8EId;fKbujA_k4H=nucx|wO)_P2{BfyiXb34>*)@X7&iehed
zB0NKt{!PbH)!dkOll9Y+I7;P#&g6=#dcrL5d;P9lx!TCiZsX`m`khc0#Nk$34=tK<
zcmgn(*tm)*{>j2+pz@;)`#^e1z2zGK=MzHr-gu951#SFbB8L6qc-)=K7y6(6mmjtl
z{gQQP>14td_eD>RYl)qylW^Sg8v7YR2-gO#(0@_kmVPLl_*ufZxxsp*m8g=60(?Md
zu$i{~8(WKw76|CoZXx{z)a~N!P(1DK&AeHp$8MMl>sVIxppo-WZ~<KcVH*M!4X4)N
zh}A~=g?Mg%976$={%;Gb>(d!Srbj@<fVhEhl)fAB?bhudu;ty~2y`#@1uX$bt^Ajw
zKa@GrpxK6w=m3cRb3MlKyKKQDsk%f=B<2p};*KqdAMUM158R>)#3My_B?ui6VGqa!
z_#vR0U=MrxfLlbly(F%K^m@7Gxb`ZvSk|F?-t-^M?&R1YBqfWq>p>2e-M*?aL^P%k
zoXYv4Dbzo?plCA*s+1{~P+T}#GJZ#6+4u8n8nL3HNFO2Akvtc>!(y6B9`*Ib3nk{k
zXErZ$H1bSOfDh}@m3*4~3<a+<rDR6AJJj|FSs@=Q)lw5>`I^F+lwE^->>)aY2w9}S
zMp8%3SCYq~v&WsJ;%B=&z!>E9I0%%@{Cec|kGT>%EHg5$@Y-E($flm((93Oxm~|*F
z#=Lm|z0_J$twG`gxqOr5Cj8{IJ;?T>4t2&q1GK;&`eBxgrRrmpWV=opVK$t>-)eUU
z_6@5HL$)sqY&(%!)A*PrC4!SBD;|O+x<@yBWXhZWwToRC*%As7P(nf_lBs9lvUI@g
zjbj<eYif<Mb(%d{NO15+7Dtp)3hauw2MAyAAxt?@$&NMoA-^38S_5NV0tPP?I^g)5
zuk*u!PanQCb=ghGg&B>>8-)}<gE(nlm_s_N)z9SY-LIDEbkzm0z>d~a5(VXOJ^Q4@
zp!~P5*Uha*I_Id6J!;0x@YW!uoK4mDpCxY5ctW*<@x+w0WY0qyIKpcdy*EHa5v)R;
zK*fT(avUAlzi_M@F*aLh>r|%+8FbPVci-1b8P5cs)+X{|XGHP2#o=N|Ur!{^W}ctH
zMAhduu?MNgm%+m(dK>(Q&sw!a8C*4gS`BxKQEr9PK4#*|{(8-PdAy0!k4bs9xVb-9
z{^@CyHu^~cj+C(wrx-ocQ(XnFLx^bh?!wCqu@groT@6X09QX*8dokZzn+phZ`0KcT
z0b;VHXUG6r!DDhxq27wqP4W}}SnfXhHoijZGbjT+x`I4`ptuoyD`>@2fX8p%3Svq9
zU3nWJD%zVV=_`+xj?qgscMu&s-!2f!DTvybMmsYWRC-_ALw)j}v25YA+XIhT6}Wo^
z`N}B7p>!u{o4!_n!hpujJ!7&0a=<KFdnIg&zq^(NuKLs%&WVYgOhR|*uZn{{ql!uZ
z#WHs&JGLM=d({)?nogTj@#<stD33XWCFOh>EHv%2ekR-0K1_<CjHmwkJ7r~;Rf@~&
zVxT5Z4M<NhO8k9bbSRGLOd`V;E9d!-P0mAx9Vxx?<<fxeMr|gV-cZ%QgU7h67Ismw
za(&sCBoXkf#FE7RC)hg{4l4XmlT^(>>Z%nN&}ks>f1^U%!}_eoGww%b5u5+san4fE
zpDkC9Qp!N2sa|U;sM8!aZO`<EPc8c~h3O9dJo?**0bjl-zcUKyOyWeXrZ5+DQlNVp
zxiqoz*2T81bd_VBF{yEcb3q+ChEiZqmP6^i_&(}pf%~y!Zwi5wq%(5l+BPQfcknei
zN2ss+`>Ay0`S=~wQY?GI*uQI*L9#v63WmMg2?_!4fD+W1NDlR~ayV74(1u?MD&oQ1
z#s3L2rbUcJgesvsg=*J;lV()IS_M7E!4B@c`n1PyPJg3%QiO#LGIt}K=`a-ng28fT
zji8-Z=Q+bVt^Y@&(>-ta-z`)hkOdIG%-M35^XS2!!*TBO$v$5W(diNR_Y3%uQ<Vg4
z-k;~5QXIy*LV;72R!cOhvI6PnUtOQ=D$3nSh@E=ez%B{<DFuP}a+YpwvP?gj(c)7U
zs_TwFgj?Ebob~cs7Q+X{!qK8z4yTv#4n7=#Q}86DmQy!IYC=PI86Oh62-w9ZOM@P7
zqziPmm=A>?;=(&skQ0Lq6a3xP0-Un+Li+;|A9tq{q6-S#F-q)V7vW0w0}QK-p9<Tj
z%5As!{^>+2Z<G^j8gZ~Sa2@{1qFnS0OMF!%U~3FR2bL-E($-Zm+An<_`!ZmXO<;#d
zgb=+K4G{B&%qrUY?U#2a;`|wrt-{cwIDT!h61pusMqc;ObZKWS<a5oI#rJ@&Zd*0n
z3ew%>=0CI)fbYrl4CQLyuNDuCt*B2;qv_@hl=+y(m!D9TL@y+hgmc+c!V<v%C!jzK
zC3My2MD8*M5lCjZOykl){O)faQN{K8d@NN0MsX3JYJwp?*I@t+b*B6i3lqNrtTZA^
zDC|)IWHO$>^R||ZtT-<UH)NZE%i};bE-s&zwC&%)nCI{^7|a6*aGz7*krg7m4hpcY
zK%JscJpNZ71>Sevf@^_Er;$EgMcxzyJ7tFYqHl=HtLS&D|E<bTy<osdrI9VkfS|!4
z9}67SqxNBK`I|hE*FB-_ErRvn!|Ch$VFTaeRjD{));1ni7M`tzf8sgXy}Z#msbLw?
zsis^=HpM?1r!`j}@uXAorGs6Dm*=2Y`@?90V`|x@dPv5!+hJ@bXxl{tY5H&x+aCr&
zEjfr_z*-~g;(d!v1_!QLU4KD03#+WhqDM!fpV^4iIiYfKC}$7|u^2O1uEGQdGAk|(
zCsHReT&qftwz4xQ#UBAEL;`<jas@l$)PX=tN~JQq&#^TT0cfH@AjNLd2{ZECob;#|
zVyfMc8Ux(CQH|LdEYPirt{?8_|A=q|yyo_HFr%r(-BpziI{3;=00!@4>eK*S{Ibw=
zIF0)HkdBd)QJ%OMhoz!Hm@7?$6g1rkqFU}afOFQa4e>re57+fCTU`YjFOs<Qev(X@
zNuKb>ZT<m%lrwMOjb@iEr_u%YRPBf84h%$;x}p^0Pf}_nS9xIUzG^-A<B|On>tV~U
zOP+GfQ-tHW3pfMiAf3)&ReR5=qLAjC&}60tHaU4wWa8^CnggnTDavnut{Ld$ArnMl
zMY~R2t^wQvWn4@<uzEtm7kL;?#wXK;F5;i<jt!d{|3EIfH`%hRjz2Ay&8U2okeM>w
zMXuM;o^60@+3`L1^`XkhOw}{mt8vQ>KW}3VH&toGNOhq9$cl7RGD{M(KLY5cEbP%m
zGV<~lDFZgeLt)eNdyq4#u9(9-o5@lLyC+Te=WkRStAUzH7Ip#%Jn>9<vfd+4C)fR8
zFa^GKHiJN*9<MpbE^WI35wHmn8Dj4abG%M|o3~-)D83zFPo5Bh0*|y{L*&aOf$<9_
zYR-b~{xabeT%>9|&Ki+S!1vhwOz2q=ipR8$35E>B*7O|QlVmFpM<SOU;;ovP=^kNo
z52N_1DhEeXTfe98iSyNp-7TJhf<VuOZ>-tM1=Puz@BkXG6HfXE$T4t6mSH6vQ(Ka5
znL{X@y(!_`(ihk=O=>VU4<ji}%=*6vmpuN*E;i2vuqYY-fkr&K5~~WsBPaK6h^#ZM
zZv?$8t*)wfigiyTowd(jKFrwuY{`hhMhOYgs#j(kOS9u_NuOy!1LBcUA3@`^MTs}d
z5jr7I4j%{%5(|a;^As^+x1Eo*XfCvdJ}j!1P$PYk;vvFwp|fL5>(sYIhQT<<>aH_e
zWRZ+|>{9E50o*Qt9$VM%-a#6LBYheF8ky8%k@b8Z&8$^Xeo<IHC<&OKJ9gSmgL%Iq
zJZFt<S2|(mO4U3Cp%J%3zq6t>d!wdGDK=ZOw}F}2*&ami`+$oWd_4>ODwS_Iogz&^
z89+Nj1h)uTqD+MW5%_uTqyxXaiK3Gec(4sQZtRN*jfTh0>o~KnAHIzyR!y>AZ_T?4
z3%4U}2O>LvNp+}&C$z3~^Fp^zruH6&W`n&U2`lX^52zV+8FDP7`>=ng;-xs>Zivy!
zSyu@G5|!%V=EHr0?QN-n%E=H?!CH|M1?)P(2qMoSr;Eh$ZmiEz!uvt-gC>Ru2#%S<
z8#dK`g=`5@<HQ$xW%TQ)OLZprAis{}nxU=mg2}icHn0Vs&XgexA*D_lfQS$$ZZ(_E
zhtxiE_IfrWt%w07E6NlvirdY|C}<~aNo(JHP8N>Wua5QHhwXygBtM^Y8*mwQW~4U}
z(q*bdixEUOwE}=pLpmH$IfulXMClcW4X%<ZI}mU4XXV+%y1v8La}Mx#-~+Pi$vNEy
zCh#Ahu!qNdQ~t5<Fh_uJ;5Kv+tUtJyXmOuUq?6Y%+>Y;h^t$(+SXm=|bbyF+>KyUF
z&)_C;&3X68aPY5tZ}UxGaqcqdy@0kt7|=uem+A=u=`GL6Df1fKw}2ilb@Cz=`%2x3
zIETxY$NvnDSg4sk_OxiY;8|tY>IC2KLDQI4L>Xu52B=Nv7MXl~FnZ~wO(OI{uZKY|
zN+mFp1^WI)(oXHbM*g+^{=&gTY<-}#Any8|#mTo;YdI~J2k~a5BM>IP<xEV7zw_Qd
z%O>8u4F@V$>^&Q~f-PM=xYp2w?PCSmOiQ1HB*e8y>0^N(yrF7IYdOz!m*5*9uTlUL
zHU_Kjz4(VirxB6_@i&8h+*X(}+eScRSR6!=R6-6gOhSu1kp+47EUwbyGi1E<J&yy8
z@iFYJph3aM3pP#HS|JfW@;2L&OYOns%0Fx`ZjU}0F|iBis>Ejhv(7#qH=c0wkmE2z
zM;im473^&hjVgXt!9NFBfCrciClOD6i2hT8%wEhR%1lK49g!jSuW2B1!spk5tlRT1
zCUv7#b$MJ}NvJJ4I8CNs|A)&fm?EGM^Moa(6;tIB2@5EW!bLL^ZlA(0kmn$~LEhan
z5=mrAEI~&&rp(2*l>WLKm+a+$J|l}+FpyGzi3^bhrN1>>kj6a^kSJrJ0(i`M?&ZOD
ue-6i-0b|yMT)`(0El;fDauKk8z{51@_i9vv`+1d~2$=kiNOakwSI}|=f*FGV

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..2e862541458ec087d234093b5d86730888549d46
GIT binary patch
literal 10576
zcmV-WDX-Rx6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&len}sbZ^{w)$2Yd%+*+2STGrhaxHv`oliOM!X`Thyau{+>`%lP56
zf9~A+h1Y`rtms&KO!r)|B`FG%*~ic7)`+37CiFF~BZ_Ea8cg?Pb5(WsCRgk09cY7O
z-Xo64Se3>esT6Gn1JeGDA_JWCvH5G9%vh8WK)Jh$SI%T_zR`7#de&P7fY<3Us4Sx^
z#fUJ-XuvUBcWzLZ8-W5E9<z-n*z29T3>{cWtMT5a=~}l;mWK+KpX4y?p4G^0W%lD1
zCs;V)QSDOCKZCkK!7DR=GaIS<wSMM;5@(r@_i;@OodwH2!R}+a)$Frw3vZz>T)pZ_
zi<o*%$MQGo59H67|I~q9*;a+9L8~#f2Yv$l*7u>z+ZJ6vV<JD-s-Rljj=I5LYWCNM
z{xy;k!vW)wC-|vpqJt!!e?WOttNoHO%MW&Ul_4Z+xa1?4%43;i{;_{JDDd9lKCH2d
zHn_S;wJH)9V`<Znx<COvQrljYXq?0FrEG**xPg}mryidJkr3|%*j~?1Ll1+3=NQ{y
zr}?TIpf!(DcQi>P_1xJYHskFG1juns(K~N;W(=be)pVFWJ_UXnxhkx}xe=4+8vLO$
zyDpdjI|uP~3PtN+e-ILkUqNi<^y2o6stys6NY#@OJC8zrMEDw2fi<tK?#IN4Kn7OE
z+IU9LW%?DgqD!mMy#0&@u5Ud=bRDcKKjOuz7gNtX*8V=8h0TRq@c!+D?$!rav>~e3
z*7R<~r~%(mco?ErW#*`u>;)xBsX2;_Qf`6htrLckphSQESKLPI=nehlDGN95&KLx+
zGb+P`sqdix*IYPDhb-uz-HZE&FAqFPp6%6U_vyH|sev@h<q*tAD9d|k1KJ1IJQ;KE
zg?Wdd9(4atI5g~|0f+gT4C#~ju4x2`djFGaHgDD>b;ksIDkO4Ywdm$QD<!U6^jis#
z#(&;y4D!zKQ#qhDE}L7<&8l}Mg!^y>c1$1EMu^|=1C{FU|8w$&6)os`hfn}!BICKH
z<g?AuPs5+}s3G1`Q<WcJ6B%4>6Py@}n!Kes8=(`E=WxdYJ7hY<>8c&24BD6pnn!6{
zdYs)8MVdK)(A>XKPz{yAjAbRE@+M@as~`<qyf9q(P)^c@r8vIVi~aXZrNk;-U1|^U
z>%B-B6I#s`Hg)03Hyl>!8O~H(1i?yhFAW1#CuUc)(P)xBRMzS0(l<60HfS*r3wqAB
z&iM134ZvHJ4+ZH}wh5cO{-Ofb`NRm-lZv?p&tnneUZ(m{3G1SV<7fIJQTntpDAd+$
z94`Hza@SP2bMd>Ri0@Du5|Gg=3?`z3sjI~+HMRm>ujMV#pVPHK!#AIM+&UKCekM&7
zmS-}sxIla1H(ORpA+2I>Ip7Dnl+>v{{bx;&P?7BL0%nE|cj@i3O{z2_CS6DL*{N2b
zFw-k?WuK7lIM(LC8n43S&?8zmzSWpBu243lmZe6w3XXZ{A`6!E$~=NM-ng@@69bLB
z{_8$807UJY!o>o^7Kcbv?W{_QUX2B%nXKs%-V|F$$L@68ix(vMBP0!YU;@Y#f7kDY
zcgcu@zr&lUZ^aAeF6vk10l*LKp~!Wxwo+CTHkPJ^glNWRBrqnxRl9j1sG>GA7xs@*
zMy<nvsdhPng#a(@T&?sq1MW$X^PTGLiH*5OVZ-aQWo|KH6B*e$4!2Uey$ffputQV`
z<O6wJcsVyaw3DPDM%;@smf)0~IV;v%As2nT#}CNvr4GSbKG?)=kL+B5x-(r{NyjON
zh9}jlqxM8Y-BW}<5jy34ZopX3y6l3F>l^@7BYJ~|%3_d2dRp7{5atmI3Vf>}mc`pM
zDNOep-13JAd`WOan2YO)eyuod(ty+`9{-6{**dM)d>*eb%&L@Ea?4EkiQhNuYDV$r
zi7cR^swYP-J-80PojHEizGD!}LnvWC7XJ1gS9d1xsSkF6?{22k6g92{D(ZirqX93x
z#0M<koVI<6gf$~IM=d-FJU>fS$*fj89D@k5_tKxJnCyuiDPg84vBiJ+;@%FDIoupV
zw6_ynqa)wH9=UZ{&#WM$zcZV-m^*gF@{9t6X;V#FFBrp<OaIrY(#|M6iZ;M01)1U^
zmSesYLHT?wrKUiER88mmf3r5P)PJ8r8p1q&4FM_Sb@Sdm9~V#^h+DTLL}fOxj?3!~
z%#Ac$yk`+MrEPnvY?Zx!NPzu8GJ;6a=|mcx!Zo4JQuxk>O6H_H2H_(1tg`moCam@I
z;ws+CQyrN8Knt_96OQZnsRrO!i$zFaHCOBDb;IO|i(WXi&^p4dyVKg`^r4|alCh-g
zo@2B0-Lx|)$o0%0p{0LRAvJO}&`!@K5sw(eAGWq-Z8<~kru>evwnsU0y~O-nrMWo;
z#CQhZ6Ch-k#BL$!c?4c6kn=h{eef|ZCwca`L3vZr0C@7I(TrpxWAP=(CluU^R_Ir_
z)EKnVVs73wv20mfOvnVVK^e|~3jT^XEFa71u<_f#t$IiThYrOo)Ns}5?^G5V0s~7m
zPx!bavLI<3AU5PvxJBXH<Ta0pV*!YY6%KQWs%OR2IBJzd$dkCTx<Z4uK8eyjFhagg
zPWAh$gVBE36}=)qCw`U@wI|3M2PNriPr}R065HB~E=#A`b*#-C`wR`=rK`RhI7Qgd
zs8KE=HQ`JriWuIt$-I2GBir7}!pUMhmu1$7K+NAqzKK-9B*4Ajxa%>J$SK8$J5uP*
z<kKABD%K-)kr3@0ivP{zt3K;ZmLgLiToL168m5|-tXKMn9K96KA~>)m1>9M1Yb0h4
zrStI&>3sTQ&}g&f94V05yETzEBAT#!130qD?wsf%_8vP>G96$A<Xt;1Y4wb*yzl8C
zoL04^*Y^UX2+~UDOWn&Sq$=mT-lCg^DQ%1ICFxzp;r_<fV%QAqH^EzNFh=W3KDLsc
zpo|yZZt6S_qAj%v-Nx4l6cagSNSR0RS<EwB`he8WhZEb|GmzyWdjy5XhOinBP*NQ5
zdkMI#_pWu%$2Y@ZULgJD)QX>Z-%|XQdS4cvj%3gh9x?dgQ+CS)KQAoXU?fiTtJCsu
zH4|;5j0qz~Ha$3URrr5N_kwQCOx_i~HH$`Y_!aIDNC0|e19Bx8(eOAhmNc|rrV~k0
zuaC$2FYz+|ep#%PZew>7g_ZJggd2S}tsdJ0ZVi+icf>Z7(e>R%^97c9k#&JtOTPTP
zz*!uUsq2-AfCJ{X((WGBW5WFo)AvdRgP)IMeA_Tja1!nDFt^NmA9Aa_UEHPQJr4cA
z^7kpL@WymGyADUrr=7MMfGdOwQE6Cy%SE}nI8lve59qDuMAmKGmx2$g=Bt6~H9(kW
znF&mIW{S1f)pbKJX2aT`R3y#PYA?Lb6;0gGBKm!S9fJ*d%C6rsLtz-LM$uQLP!OrT
ztrS^wE`}Vy9H*-w#QG2%HWLbo%$+fyeKBXHCmu<lV3V4WMC)f-k={W*(7W6we=LRC
zWfb5qajpaw0qZ2RgZs$fU&h7+s0g6ku$kA_447!a;PE<JX#axdK;OgyOEB=fYYEQn
zc8=prEyg5r6{c1DO%>wD&7m5WGuPX-X~6<EfC<Vmg}WXo?lbXtq?9Evl#KhKdYm&U
zOH*xe>WT_RExW)qHbz!+e}EhBtV27&CB&^*P6ES=HA4a^`;>WIPlNq=o$|ZYXXd<;
z?nEgx8qOxT;N$DacyRB?y~__DMW>{18Um`HI5DBnYdD=Dh5+Du&_xN5>Cc8n8W~|v
zZV~m2tV%FO7Ty1W#<Y=<d|2Z>`KzIi$wshbdZ^iodjVoDZ`(Q@aLc2I@;!up3t-u~
zd?y~t+)kD+nXq}2d0_I2GXd7+F!fv3p8KtI7By>-==FQdS0eLQ?S#X;;cTE5*TUt<
zr2W>6)!>jeYCfark_?1~MG#)o{<+=MXMZ;!#EPIO#7096v6kl;<OHLdf;QmB|9VM0
zpvao`)($hCfh`4)G{?9D{7f6~ccKx8tB#{@MyT=rnAA?ocICEOK2WX>oV~V)PMJY=
z>%@RC`u6RkYDgzWkKp_jyD^Z}-=Jr_G|G^9o-7@MRPG(2V%=(7Kq<Q!`zRq$2Es7X
zB%v$Ggj46ns`K=hvc0#!ljbhERHQsnPH6Sus|Wn2Z_x5;c2Vh&{VM>~;bfeH%-#SX
zkyz1a3-W48)>w>M8QcZ9Qrj%<+}QZKM=XBrlimQJYU&KMtLFu;+-_Uo7JN0@*;1dX
zFOE;H#LYh8FQr$-ylncg6`PY=l5cT=6xkibf;>%NhK~kV70w&y1g~O)dorAx9^XIE
zX+LmNTJM7A>-!>X9}zau6-m6nLPy)3tS>Zf?9Gj<aD}V8ITbY}Lauzf<MU|gJbuXW
zmRX-r(8B(xl<N#rfImkZKY*sQP4s%w8If-N+sJT&;5dyNm1x2DeysW!B0>q%+nX=-
z?w+`mXsAzv&-VzpiC*%4+X$nDO*yfO@7{5YpF3LMnLr`ZE9qfNa(R(Brz3fu7DxS|
zGk9iexTp}wVffQvUh-Oec0wwcW-If?a@b`uy4$~JEP4?WyGTc$r;!fve}l1SD}`11
zDT}JsdB<rxvWt3fpqNr%Vd*8mF<M<5B~fRsv;i;RIL!&@CXfUa3N>okSKMBi5sNIJ
zwD731!fasgO1uc7OS~SRIdv7CdCQFuzlFjKcIZk86?NCSlkcT9uxvdeorOPTqKw;3
zGNLJlw{d?ae_HZ0byhd%N;dwRExl<hNb-3deo7}4o&r-D3QF$64*H1AU_Ck`GQk~O
z<l7n(^Hi=Uy+zDGRUS>0`ug+|M|bp(OL-h5(nUYyLq0q3;D0=JxZ?QUmPBDcb)H33
zt)_P3YtH@qtcy$;Lpz_DJ6xs_Jza7pom6g|$v03Us6Ks{BpWSJ@c&ZG60TMLYy}nS
z8Fc17%s!l6Rq!z4fc;Rtq)ZUp0j5j9q{6@NEOF_x3=yOhMXWJ9Yc(#YeE&=da4}P=
z;WnObVzDW-tNCC0?g!eq30u7_#xwAsFtNRTzRSuH8IMI}uV$#0IY55>HtL~9M--J^
zK))->cX#kcb$9V*XEu)zq4((LJ!4@HG)pGNE>mxo{1Vp^Y17&%o6S@<d`uC)f0<TB
z3=$Aj>o8rfQt?R+ciVQyo(MD8!*iTf<$t&<&!n2=rJKy@Idx7nxQ>jWDQz9EH(JO&
z^g^Nqz>;M0)r_zFF}AktdoyS4qbi1gM4NEovy_!dO6z{OH`Mwp`Mp23a~63?jfgq)
zfYmcJa24DhP*kfJ2H@1L-k_d4*@Ahg^TLmyRi9F#+O&=Nza<OgM*Rn_R}w=SA84mC
z=9VcAWXQCr<ZCua>MU#gc5o9qev7u^IIgqLU#+$!*Ayl7Kb&NEwg&d4V%!{H<Py)z
zGcuzYy!Hy2%T$FZ$Z~vi-eBOD6*B9L*rOKxUqg3Vjkt^fRz*Iod(WSfceta@Qb$a)
zoNDe98-f#fq(Gy{)bySpp>a~TG8E%yJbYv_<zhnL|NeC_tSyHb3>KPb-E51L3w8H1
zfjLHinoA;>puUdz5mzbXoKF@z^{E06j<MfF;yNbWPm?f+WeO8Wa>E<rVge;^T5Z2)
z?s3L%R!J4!HNV*?dp_KB{*$-v9@eyD%tn>5be9;cE?EbBwi@_zn(J-2(-UBH|BsQq
z4Of_MsdYULFg3Y?+n(kt8;4HzZ*IyYr@c{d=Fg&N>CMCkcYRD=-|v<j;bSSgthi5=
zoh<t()&X@8c(9DeWbG&e#t1)&J=@>$gAZ!<at%2|Dd2|bpNnW<^OsT&hPu7Al~XTZ
z-t=+yz1?BUbl|9t7X;m#?YZSgu~L?J?+&DiCeZoVe=3z&n`9~O3bZwgRAl-;`}Fj_
zGc-&%JEMA5aF+w6M~5&w$FFEe@V{Itqym47?Z_Fc-A&r!zZ%iMIYNIX?_UOGbj1AM
zJm^iT`BU^>mlP^x3so9pOIf@|p!Y%ii2tgzn%IAyVSH)b-8X3r2$0{iCz6)<3PFDr
zRo1`Z2avZ@m?sU~(kT%*87$mJQ*r)(Xk{)(JMk;6SB849+AcMGW!kVoa<(B*4xj*z
zZDPtK`(aBRcRm_xBYPw{D-C{@HG|g-Mf^6hX+QfODSJZ`@<p9)vYldmGz)S5lI?1`
z;q-)&;((JBVQ!N%)1}jT1Ik3@8HYt9Yla%D4*)OD&NKsT3LQALft|BC`$WE^Ph9k2
zSQx%Sps=uAPL1tYC2GPtyJf7_Q?aTZ`t-8NdX2~_Grch77Nr&X-!hig*!AiMbzUpF
zU7i#vJ`kkDDOoP5qM83bN5oNqe|$RkH^>ezRBB8`U-7Yh{B<r>d(=Y>r7co-&lrn*
z*bT;R)7P?2a*|OL*8o~(HlsGVW}R|D_KwLGd$$}C>#CA&XQcU0i!BJq_acg~IMRR;
zpcVp6JwNs4R5^SE$4ilM(4i`%PK`*|5WNzHLu1y#JmFv3?4<5TVl|-+(C$VdeV+y9
z)zIAkX1*P14=iI%Gd#pSG%J=Ps+*fINh~%DfY>Pyia`t!bGY#m+d*|52*@n%WXE_}
zgHlDU7QK5SiCbcjLU_fgzUCySLDNp+>3Avii+ij`=BkGtXX<3=H(RbTWkzb#EG`#R
zbh-F<t$YC=y$o`I5KoiFox!^SNMK52q@#N95DTGYYfCK}CNZ<g2VF;R<D*HacQpq^
zjd&xxqeb*q?dDh+?<WB(<TGutl?;MtOJS7kRJ$%T|7s)KLvU&||K1D1doJb`K0bV-
zFfQgI69jggoR0R6eDV3XIlMag+^yR!peel&?tcHmvR-FkKN`Z8?^vFPMD8evMqg7z
z5!g4-MEg97k5Rlu#GUjyp|`<>2FS#PDt1%JjNBK}I=v{{1rP@$|1VplLj6Nv&khCa
zqDuq+;UC?X(x5L=L`%w60*;14xbLp&TH6_R-K;6IYnfR%-eSaVfpKP-rB!oP!G~Lw
zg#-qsq`gdNn`k$I=@Cp@gC_iz7K?19f_1kRFdsvgWOsx83po<K<pU(odfp^Ue~UiS
z^BrpA2pe9V)le_iPiWF_QlMfpleN%P#`>~->f_Snk67yJGtz!*aJ37Pxx{Pmb2gu;
z7X(B{rAq@oPyZ0d-_*EW&pzkY-t|8S!*^ch%>Tdt^lxcxgHRD%!fgpsg=2Uvw`dFR
zOyk~QB>`J^RVwAl3%JL_8yxr;)Tyd6Hxi{ejQ>Oc&Hg=7jeeI#id(pZp@({4A%fCp
zeX~i_K&GIpB%?RTxLEa~i}0LhM=7M;irFI^hOclVwHQCYfWxz_5-CU5{Oezpki-5v
zQJ5<^@_mXhc@sNGmdG}vM@CjaF_haNQr1iH_q>4zoJAJ4%JXw46i3n^0KW=6aJkLX
zsF96BQS3Dic?=O{X3@$M)sTRQR2@fR<Xgl5M_YwiL01|GZ#01|$@){}+&-$R_X#+S
zP!4Ve>Q=D+K*Tm%XZIsT{^l2xdKZbC5LPZav<CwG<;n5^^dkkdKrm}xH_&x0&gTd}
z#N!{v+2>tJK}L0P9s)h{78l)w3wmT^1oR`_kO@j5lF)#TSB1igeK#(nfy!61(!{%M
z?%qzgb|BW+`I{2r&IBg7&b5<~3u|e}h!Gr+TX#$7O`h&p<jV=~%xf4~*{Q+vier`}
z{Tn7ZRM)cK&*=(|Pk549)#uT<hSouQ5})F$;!>DX$1kHe(JV^z5nwxcJt5}b*D=)O
zg5u4Yvr%>o5co3y^d95}ez3#LC-lU)^Ps)K*>w+p12#T8KXM>w1)o_3bMx0n3wgXb
za@$(*Ai9sr3CsYMkAX`%1ghg;go&X%KW)_$UPOS}PJ`LYYIS7-4t^W`W=jm)8qMs&
zeIxy>MV0BwEZu8HEH3<j9P}7F^ya8P3C%m{vU)-ouDeFri){)hU^qB`vW@T>sLZe7
zUsmX!BCP+z6%s<UWEwiLmo0_U!kCmn-{n^ngpMd6xp=Lr2HXPP)*^Wa!DGz#$IOF<
zq~UIW6P3(3n2dLg6J>!S36zN!6-V|nmIPUP4&=|9T+Q7`XAHFVDy^O$Y`Tjm0h-=A
zO^zkO-%jcK|9+9HC6>fkrwrhPfWwdBXRPXLdBhPZD1wbd-!nu>1sSD~=%)5bWW_?i
z3W}P`hlvIyL>M8woG!BWsH-a52V#(Z<x%x=zH>H(D%p@yL*mbOENPmZt#3+pYaJT-
zq((4WuWUNOK<P?I4g|tPX3S>o*w|32&;^vB`brLiu>INxBV3of!S;btbEi~v*HxEF
z?2i^a-Qzueik*adc}gP#hWG@sTISWVv^ahJWo79;)Mi~4rY;ZWn0rn_J-NVtf&(*N
z03e^TayQ@EK6GLNefYYvZ1*SRB5p+%e-nRIRK>9twtO|xnmg5BP-eA1FdC&CC{c0`
z;!oM|Neo-RY1UiP5sW|hL=K<xr8`XNM)vc>xakk)+$6BkFj-~+A5=zgz?$567mi}#
znK`2CUa?ye{GlxCcX&1xI*<5ym%kmIT`ox5<?LsxL%Mf88ZyB*u<7T)QdX--)+od)
zs@oGsh$0=C@`=fH1rCe{i&dkN_)B)*+b<P91wQv@rRILNVe4X<SOtE8gV<6P%;Flt
znw>-He!ww)CZRA9Z^M$@Jj=AEVYJ`tbz}+(LXX!}{5P-zA3YA5yH&E%e`aG8TT>NQ
zCT=uo@iS>IkMpGhDyqN!eHKB}k(>&Vy4v8zJzivAm#%_AC84t0WJCUKob_pyr&26l
zk9XD%$!ub4^S%o^(N~A;tjgz_+(%oq97AY$TC;kF9={bCgJ-f#{zSzNIalG6BX}Eq
z-+gotY+deT=jlM(2(Z;(vwO=%QDB}h0*E8h>YqJWR1Et-uiI+9PuTowwinH#eRhk#
z1#qz(?@P~g5}!pEOnC1lQ|ZTMS+0ytUQLddIghHu7Kr7;Dg0^Q>{0xG-KjW??j0r+
zk9Ed%(X}t$Q`Gs69z!)J{eLjR3!p>Iqy+rvyOkRzg43`-wZTuT2CE@097_~Vvh+pF
z!}L$QIU5ap2#-r=ThLvHE~eAfE{&CXd9M}52?^XOgc$h%4t1^gR(80Adah$VU#JKP
zD()-sjIW*{nO2OlB+-QPskM2g*=%n5_>X;16mg0dRI42^Eh8<NK3qMX9Yr~{0lkvQ
zJ<Jt=qs`zi={d(NEW^emzx~Jnvcx&aKY#)URwY4{)Cf2`8L`7WrLdFApCDerVYC}e
z#QZd8ueXNZB|P?<98j&T{W`lPfgNwY>h<*75>-H@-WItiGj8vMEeYZa?@L11pam8c
zeEOg-gZJK{r;&tgqxX7pE}>gWue#Bd|4P&$vT`ROo_Kr*?793c3@v!0xkz)hDr%CB
z8Ut!8@L$|vks-SM_<Yx=uyg8&+)po8zuwDBWo-w}K5R<;=eReRiOKz_vMYg%X_?-%
zlw@yf6%~XBSv%DYvv3uA%?C`Mf6^GgtMUu#j=6nJLFY2I1=C_#<~qPwr`qYutd`t8
zMtO=`sZp>Qo|rZgeM<>(e~4GXJ`}xX%vJlkmKrCb$h;braQp2~9u^=}%3Z!p?`%W2
zk0Ye6{ero;1Nnmafj1!lix1INoqS;|(^f=S)#zU4Rd3)+W+k(2OKj>Y0Wudbh3%y*
zzb(jlDbmJQH>^uenpW%g(DXbl7PlNu$xE7ECA1zwCp1kTf3*;_^j%&|q@{K?ApcbJ
zsB)UO6_ww?m8Jk#y~@h>7Hqucm?M5>h^!1X9@`?Q%#7@YJhh5^NAG&Baoz%7U#2x6
zSJ)7}7n$)zf-{bM8Q&~#6nFqPWoT`ocV>>i9>1|9l~g&o6IT2eCWDlDfd}lAPNsAF
z>Qo~gN-X=I4;>HItC5Ta>YZX^D-y`zA8gS#C>i$I>8XoEx;dxjeq^~^`V-BE{h{%e
z)<zD19od3OJvWE942JZ4$~;&3bA~=srZ4t8)w3vjLoz8m@8Hpou5y!+ci#)MBtg|I
z6zTRZh_>IZrg|V#zW)bfH*~+0->}lUcg70DEvKrU=BhPn%TC};eTWliD*~LINm<F`
z)@lWPP`b!6aR34J<c7VB>^D9Dui9P>e!!IK_&D4Mc5WMqO~i7ZcBD+M*HCJm)D{TU
zw1YA7&)iT*z~lVMgY_QN=me#tH)<pNv*gT<{YV<qDr5X=qKCJ@C)vb6%|ik`mP1Qu
zLar4s3>qVEhegvDL+M@IKMu~sGxc|pMgI6pW6lT3bni18+FKTxqfDV&SY&`kqpR#1
z8FED){DB8EsL9763G=NJc;x7Bye+c^H2R2k=A|RBn;*g{I*F@M=@9YCK}Y!f0>X8W
z4TLC(w33yM4+XPJ??FhrVC)>yrUdSui<<U9Wo1R8t{;BZ$y%1*<k<vp?R<9Ik*xy%
zvs7uvlGjI6V94SLJcR_dhMYG>SsFXt@8Z7v*6wN;yiFp_>-ru1qp0cxZdwu6dsnG?
zuqL-_$DehHwjlG&+yS+{O9V`(M=+cKf+D;|1b0xMhC^wH*0KJN#Y-t5AvkayVzyQ0
zc{_Pxv5vmbn}sNx$5d1LloPBeaB>^DfDKg@YFD*i^mSOyMy#eou{!KW*~$Q&R*ul)
zX{t4ZN3jb6J@lMr-Ni~RUwz`t*BT=Fic=Nq&{=Wu?>M9_Al-+8FQkl8uQA^rVjVh>
z=~G@>P-0TvbomX&P(a(LGj`seHW=O3ln?2AQaEWSPX=;CI1uzswZf6K=^8DW_*pd(
z?!H@nLt_n;)Y?0$vl4L5B*hH%w&8GDG~ZP4O=whWp1w(Bs<0fA6XxSt=F2E3U|)2Y
z`qOk@w=#NXlzV3zf2qT|zG@43Ul`B!8fV|VbZ24$CdS>dod&rAh7s=YO>Ti)0!r|z
zaR|Ij-<!?Uh~E=68*{W(no9(xoSX^uoM<hlRK}olE(SBI;{cY~Pr9)+HRBfS+~__k
zGeOwc0gqdm1eXS!-ge}v*3VTW&_tCK5-!)x8sd{?a+2R!)`iX_=y8I8%zYjAY3vW^
z2}!BS&hnxE)2lGtAOEo&IU(m2I<Am5pT*u7apUjvj@tF^cPk%6YvS+%UNZ!(wg)z$
zPsZzP1C<7kI*1m&LinwPvH;fI>HXWmTiLxqcf3+)M!>q#5a{X};8La!gEy<a2W$$a
zb&Akg>Fzyn0*@iOA#DR-Frk%<i-_3D2PpOio=f&i9=<S=XN-?=wn@Z0Z00x5(P;##
z^3p&e%8l-$go0%9EsaIK{u{{&fkl2O^<z3q<^D+nRpTKeuTb_{U6>}8k$7%>{uYgA
zEHD>VTk0F{{xJ@<fmjW{8!V1>-96L0BR&k^t2Ob{57|L6Rql+r^~Y<ZSED@!(XswG
zEn)uO@L&PB;i-vT4*4*8&vKwbVunSVG077w($9&Q;Za58KBo#i=3maRuDd*Z-{9X^
z)Zf&yAkIdxr{x24kkb7Owjbko<OV6ZDyA;W=kKgCP175VBYY7Y8sk-$%7S~%jgBUn
z7N=f$hDV`l7gJqeQ)u8m<D2pOfw7LMHYes64u5Rp=2!?X3jc4}2_`)kAV2_t11Z|g
zmZ*Apv{nhB^Z1;ptx6)YH=oh%X3Yn*OXZdhWxA;rX0w8vQ=B_j*8iv*$LUtGgqedR
zcd|V@z#h7FE}<%qF6qQlfeW)Ow9x3CP$72!?=S5_M<MrjF~>QT<suFvdF&0sHt4cD
z+cnL9hV1KZGRZRK`?}$*w$M1}7GuqM_jhWw#xPSiL0$x>3X*^$Z7#5zW}+8H>m{7t
zSrLd>?+|5M*`fS&;$>CiDO53W^0)pzacT++&YBu0+CH<?cT$%Wjn2RYPApp!kN_5H
z-kk%geDTIyc+fl-(X~S5Z_<_<{xktSk+I<ARlH8qgBL^9X}i^HyuTrU4iv#CO;J8@
zC4A~bBE1Tk)aemt+~G1BW)7&&s{#7+B4W8IQtQ+bLm}ds4>?b+s{noF8Y~eP6j3JV
zq3n2zxk{c91icLlbd8_)20z_E5%P+AofznLH@z{hQ$;5n<A62x<52@^kzp$kkvjM>
zQXh~pBS?}W%ye6MyV$!#;6c209U9#`f8d%&T&^a>dn+L9k@U(OjSG(+CV^B2vSM0U
z;}oAg#-|}XTWLlt0hyfmSj$VRoGAPa5@D27DoM!B6A!J4?^#G^fTAI-B>r1nLX&Q%
zY-Ai21G!AMIDx_$@5Vf!p@!6ytRqW^4Vf|XbwJn)6H<HJ54uSR0K^6LLN7<Wgd1Gj
zj5`&_G6<&C3*lYj0@0r5@M&1le+>&muR0-Y#0#+e*m@zXnz9oxvQV-7aw%F|Sd;!2
zCKea{RC%-h;F~RKI-Fd_#`wO=sUHlL74S|jwjbiRta?Em^^RxkOZ)rnZn5_Zdn%+J
z!zO`1T*38xBdUpxFU39R=xY^xy;)f%?wFgA@_}r>lamvNzM2eL2Rr_>t(vSwS5wDs
zigdFL1Dl=E>{leQ5QlnJ4oK5{k?dsqi^%caZzY)f5PokU11rSZi%HN@75q0}P_C1z
z77v$Uo7wwi{w$VFWi(kpGQy73M*60#BEJy&t|%D&8z%M+uMUjARsw`vV}Zy)21+<g
e&Q~I9TawpoQ1cQCS`@Zbn*zB_t@<JHQ76a|SZ-4Q

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_8x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..c4f052d801fcb0858ba1e4ae4357c854626beaa0
GIT binary patch
literal 10560
zcmV-GDZkc>6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&len}sbZ^{w)$2Yd%+*+2STGrhaxHv`oliOM!X`Thyau{+>`%lP56
zf9~A+h1Y`rtms&KO!r)|B`FG%*~ic7)`+37CiFF~BZ_Ea8cg?Pb5(WsCRgk09cY7O
z-Xo64Se3>esT6Gn1JeGDA_JWCvH5G9%vh8WK)Jh$SI%T_zR`7#de&P7fY<3Us4Sx^
z#fUJ-XuvUBcWzLZ8-W5E9<z-n*z29>fnQ+t20xb%L`yWmc77#Ixf3ftsnc`#p2eI7
zx<B4i39W2mm+}^~6BuZHyM)1wM$N))P3^8W>c=U1YOY2_mROAhKPI#!sFTl=B(52`
zd5kem(N7L2#$YKFtm{-QasNOHH1jUmTauegO^`GKXkR$4&gPGAlu2qMy^~n96EdV2
zkiRsr?F1-*KX|*iYpCxPWUSi;oK)0a=SDViL}x1$VA#~(V4?>gkH+DRv84N26!bdR
z>|+E*zq%!`l<@LtDuJ}LE(HW>qd8TB9@@MCqrvDrmB$F>Tnne?8x)959}9a2u8j-0
zCJ<A`QIY(AS&0O)(`iPE%s#qyFJ>W}X>sDTsX9hKH9;M3avb44-%;}V$a)?3)8pjd
z*p~n>`2hi}_{#3xWLH%`YFEjbF4LR3tz9TclGWy+cw-=VphMz?a~_<mKoo4AG7>=K
zy}PHKoK(Meb_?vt4z*qeJs@X<2!A=28c5r5ng^LU-LA)J<8(qmW=$nF&_x#UF>m|r
zE+>v@rNLohl;W4W!JXhXIj`qh6Jx&$KY7o-d(TbfSOYQF`ggx062i<shH0uITmNL3
zEg5fOYsaL2)V!byO%s{tNWN=<RGWrm88ZW!?ovLSzm!^uLiB=CljnBFdJ_pfR3Ifb
zf8XsG+Mb?PkOeg<(tS6nsBYn$->EKQ9sT_BW-y~Hp~3|W#ub(ImWw;(L{ef%y#Lzm
z2MobeCy^>jH4M9SnZSBwL8(hq8XqwbtO)l?(-7R5r01|BxD0G%jIH*Nb|nV}ksEE|
zV<eNxKU6mQ$Hy-=mWj79F6vA->6lsa!3Tdr4dGs967q7|7K%gS;v*0Y{Df%Q3&2cM
zdb)&`6fI|2#?RS?tS6^F!-f3WiW%$<H0k&vJuYIj;d~W^Cle$aBK4!-Dz3QZN6cP6
zy+AS9s|Tbdltc|>0E?KM4#UGM*miu*6R%EQ+Ns31w&jRiL*zkgOe$SI+GoJ1YYSf~
z6ekrjUuH@_qdVZmR)t%Z_-n+dfvAM6*}5?4QfdRRW{rk7ghwAIHvSMiVetl1d&&lI
zcKKZ`?jd}IsM*>lT^t8CDMzTT&qgo*cpY*3CYpeCY#BxXP^3Dxxs*%z#Hi%w&%F~_
zI}r>yH}#2Ue*RBpus#-)YbBBvqKuu{(~LqWQ0i1hZFzoq6*t7{=x7GWc0ct6uB@)W
z0b9*w<@vAs_IJ-#R5FgW14HBI+i=vV*q8+w@D21Ys*Nv7uMdZ(Ge66?jn9`jC2R_o
z&hI;WOoFrlx7a&_wsA^jT|e{WGhrL8j8M@@jgw>kagP!wx9{E`Bzk%<LW~-r(bj8S
zg;{y(hsy!N6qa%%Dv}PW)R9^@lRQk~;Ohx5q%My97;RAqLx-rr0>&bYDg@(IA%y>K
zKOw>AvjH4)NHxE4q_m<Av-d3|KWA^38|jL=?<H>W;*K&3vD9JbMwo2VXYqx{YdjY$
zaL}9|dq4nfvxTqd9tW)I@I|nZ|6|c}QUr%p0N)#IVz!3CN4-mTRjlHa<6XQ;pHLyO
zLiY4-H4;-7`>N0CbHf=apZ+5sW+CqZ`b(ikhlQMtJ_T#p#sGks%j6mU5!;$~Ka;t6
z|H{0Vdvc=}?id1w{Pta$Jz98OgOXJ`3|=bqsss)1YDC5SynC?#^Rv0m>$VSAuumTX
zls<j5#+(<l!#GZy=72teN}=Np^?I~>p|kVp<z|*buAC|2y~h5k*l<{Lr6k9eZ5iy{
zE+Qr>`3-uwMFsoKHJf6&<G-d`n(3QqH$dvbDn?xh8~t0ofkf`fTCp6*&nB94QB=|{
zV3e0ET?Wf*M=LO~<D(XV$h#i;ss<)Cqh6QhkLVulc$p8VP^OL)a$ZUW^kLi?F*bdH
zi0`S=H&d2m{i#C!w6TnBF!BxBDdyt>O!s{5H-p7)bh`#&n|)#95c=Rb|IkN|a^8$L
zv^pLjRtr~>ib`)6ca=QBLZsOji7^MJM`nb>2nv4}-QYA<x1h&V97(2;PKXCRYuUf`
z5~H6;K>akIJtsh+FqviG>*GPfK{<-Yqukj!(9T!#8cdZbV)lEp=Idd(28+u1hbdmg
zbp$-mD8HtEdt%4%>_UnTrIOB_0zPnDzYp#jSvq4BSP0$8-bIU~9KWt~uf7u`#y9ZF
zWQrU_8(NCx-44bG)7If1w)$EE=iIxv0cvPy04X~PFswEC9BuU1Ef$VQE`F!-OOP%n
zuL3zURO-iFD=Q`d_#IIv&*ZE`#8(Y1k|5REB~v~e0{<&9IrY;cNuWpbQe7JJ5Unb4
zHV+p+<gZ!Am*$SfY9*~f_j`6Pyi1?e`g$4f5uO;r!zkDhB)%fje?>y)vvP!G%tb`m
z1UHN(i@tmeNj~5-Tlg7cHZ`sqE%*b7BaMLwV%tNnH09u>6hsaAdTY;k<qDHkJ3nlm
zg2$Baa8T}CHOKFnY%m9+F<u_4<nW|5dH@$p8bL_>;dm4L*`=zk7ownLP(I$#eN<lp
zU27jg!^T8)XEMt{A7@l@dRS>U0A<)AwhJbv`%6E_G{~E$jENa6Isl6k=hxz;K19>O
z)sRpbC6_RTc2q9j(3}2>RSN69qugdQQ5u0is<`c5toR7=$+z4?%{xJhzbKra39$dz
zihz1&`w1B9nI#f;k9!<kJ#q#qeFJ&F+9dI3tkw)@^9~!sVi~vfmCv_l81T35%EG{{
zfFiWO0|i#Dp)JC^PAmQF8Ed$={>aI08%KxP9_dJqMnT>XRnIR(kh38b?t)(eFa$L-
zj9SP$z5n$wiWbK`r*BB^CA3x*?o&&LWE5Af4PHrvyJsE}h~pZ-oQR&YaO#V7P)nq@
zm5BWzNjqCR)r+Q!I-*OUUytUzCb>t51VlhhP}9s4fmSJkEz!&h;H!ryJot43?3;B-
z(Ory)i%o92(&dS~2szNOi*jUeTv5nWQaEB80Jms0EAL@%9Nr6Syb&CVPZOdRJ!qBb
zdA(kv+?we7;KT?K9_&qsN=(XV7UY~%>M!JDcAMj;a2U-#xFdJdE%+-icBSnAU<1QM
zm5iy<=kv`MsyDCec&IEa?Q=Ca$yc)4l(?-?d{XDeRd==g5`)vD(Z__I8a^TS+qd!f
zfyQB0GvFt8_bWQ5t9<SbA%V!;$0(_rzzdi9iK`aELKB$HjrnBNHvX`<addfv`n}S`
z%??1bGpy&0_OFT{piH^}lsdue!umtrHey6Yo2vdDXk9b}*&h&?cyB6v)1_)OnpMzP
z66DJ3`WzjyRGthM=~v2U$My8-$^8(UGu>mJwRfv)sMnZbsO9rtc;G<)pu>UF>cSzl
zZ+8(@)k&$9<aslDku=0EeMMuj_?(=Hoqu?9_P(kG^GD(4Jfouk4pa0R-HWSI$gwfs
z#{i4dw4p>rfhh|UlV{E;u{uZ-f=j|l>-JMONXe}FBv)n%u@PumJ_>z_BL8(eMl;5l
zb+Mp(VN{jx!s9cBdloU4r>A+hAXeQ58(~$O{%Hj5H?w7e8da0DoC#X)TY^iF&KlvS
z(u>mK_NtHF!P=F}DSTv^yilw6<AX+&m_#d2)@Da3z|)GJ<bo)7pHV&C;C@<AT2t32
z*=wx4p+6pb&y}H#@76)q->fx~dFpMH0*Oa<=2YNOh@4X|1yuE&G;LMP%1<%29(0Yg
zuC3u;&xkVqZ%_CF;H3G$Q^sCo6ATD`1^R}N9ZG39bO3QK80a#Z-GWb1?JlHRxOcRN
zIGdfuk3Ql_(zn<eLW95$+{--+6^RNdEVFN@ACJw7q*D<MUsOcypDaVQ)zvscoK4Qx
z36cuMTwH$afU*YwdhsP!SqNeN@Bi98_G*%8Kn}C3uO*$6Q#KMO$2DKoKMfNP1wdaE
z&wPqYvrBIlWVBXyqI7m7LL`BZx}qAb<5#oqO>wNO5((tR+Vh+17-|o}u)hP;upS>S
zFNZGR>vGDU|0-nFy=!V>1)r$Yw1qU9CgYmEvf`6S5Ot`N_aU>3)YwpHh4}1jle3-t
zQ%BD*8@tH|AfXyoLNyk2=cnpuVO;*%ZJO%3kTBi2!qH8OJ+T7`UTRs;qNxJ%fOx7P
znF@Rt?!TKMj)%#7*-sZP+2%1Idf~~Ypz#t2zQ3Vle}SwRc!SW+lxFOw<q}WI8j|_2
z_}6B^TWyh`XR9@T%4JPT>33!lUNh^_QLQHXXpXB+mmGsz@LF|O^Nq@2-`q5~Tx<z|
zFW`j6QVUzJMDP}~Cn)QSZ02^+??zVlyb~2V@a*7|H~n)6Lu?CR_493yiShIu9=F4Q
zH_zA9M~i2voTy`hCZBeLhL>zAs0pABK0D%MtkJSKftK`hw5-^B(Z9ty+OP446kJL(
ziX|ZIHEH%vt8;#wwKBxw$^Ty+MN*F5emF52aBaJ`ysWO&thR^mTfzrm-9x@Q@f(g7
zy~e^CIFxHg{1Ld;))C?nlfiY_+H_|wnH1~=7ND3-E=!Mrv^O{%_ymKIxGIV-_>B<-
zzB{9$^gKMlhTg1U8d9BQ$=CuWSGQE;!Z@E2gc(AZ>2L*lIa2+mV)eTi^oGzBK@QXi
zY+d&_J5xGpyJsEVtqC+h2z9l)gXa%{Q@I+<`@{?P@$X})O7NoHV3b(d*M^=z@bv=@
z31;+WE}{aNf7j3y2F$&<H{S-c$gt?>CF{OoVC=@|T*9P-U<-NH9P2)kP^3-o3O!6u
zoIzbp$@KmhKqG(jaBkb4Hhse8EQqsPvL{=S!6+1Sb$T>;ESrU6CuQoyI`d~oAE;nh
z07eIJ9W?GC(9*ML2|A6MRZQ8_XqmU1W*Htg*vhO#%ii=ZbOB-T2c7!JzEwsj$laQ7
zfNZt?e}xfH1l8-MRaOyXDcryG`g1OEaAX#Bcf+CJ@}!-F78WVqt3!5~I(#y9DCvv-
z)cbLDUBOza<;|+Ez;`BrCzQXO@X5>{MQhJ3sUZ7NMk~yEYce*xx=8OyNQQo-5Y&TE
z6d=-7STT0U;&m-CXQG<)C536WjNV@TTAi0KFnLncr;jpS6HfAe+*W&Ho|uYmA*<$e
z0%8$DXQeJRvfiKzwLh|3bKE?t#u=(0B9Kal^rh46As#gw(!~wAEVu%NC0CB@F#HYt
z&Abn-^28ctNx*@KIGb{iD;AD$YXV#77Zj3{2oe4e1Ykf%&yx{io!JBX4+KkWX)siT
zD?p?mc6cD!@MSrBO^+l39RAA1R<uVu&(%vU6Svn>o-yPi<di9e52RfBZt~B0tVJ4j
zNDunU!_a9f9tl(RUl=Ap<~Tb;f&*X$7W*#XIm8+<z<#MR+jZ^B<c-J{bWY6RtD-Jg
zgI+q_Ea1Ch^GrKsB_imricmd`1z>ZW2&L28!HfH+!KtHE&?e<Ft}%Y|UkDs&%IS%E
zzWX^HjJ|8bMFWl&M)0&x0$IaW!FW{Km}!I01Ug%ZC49wfMORq*oinNsfFSGh9MJEy
zbh8hUa2uWuxhfHg`e}YP0}~|dvY;5fN7n*&iHQn~q)(w0(-LERoM409Szmi1#~(p$
z;Qw6H=(Q;{jZS=m{`5yCwFHGctm9Mab;s25LFGH8Z#zdU<0jcrOu9#s5Eo?^F(DzP
zV#h;?;4@+aYz(I@GSxUoKU|@`^_Zojoqe?eD@NCRWeL@a9tq{Ve?_`-aR;)~_Dp!5
zRD{TPh6a-*4(BR@S*oQ)$fDAeQ^LOzqHnXz;=1RygrI%?-M;8yh#ggE<2srU@OD(Y
zN%v_gcD(?Dp(+{S$05dlcb;J>)~tBQqbEr1n-{3IyN9#P9@0JQRdSnW7jAq~cE_Xr
z8GvY^Zt*3MKkA6>;63{yGIe=$AK`NmLSS>BtZ#GUizj3hAzg%CNKiIR*dG;#oD%x;
zdOz<HW>sNVDijkYoT!#kMjVIZib3}ipWhcH+AepZ9UpaP9{|Ze5QEVm^GO|iH)nB3
zvD2?Y{&A<HbrgBr#AjSsPG<GiEU2rk?goAgi&ay#h+BQwWiP|0?1j1U#_Y-*JhZRV
z{Tff)gzoqj5)H4sE2inZH$-{HeRTGHlOg;tVHKk97ce+rQIHQrvP&)OA>SeBlHEt~
zj@-b8j6q~kZ`z!l;$NL-OUu%$7`J>>?%g2*P$(-=Y?-EfBcr4#&9ipGebL8_$-MgA
zXz^RPp@I`0wl{>~MF`ruN@_wQf8M&|=kC&YvLgJ|b+yVxBn8heP$07QQK>&U+0i-i
z*+@sFUWF5ogP!EQFqgNH3@hx*AV{~c8j4;qJd2EKqven8^l$!CTC5c3BkIM`M4B!m
zLKQ2KUJ~k`%-ZW65Ln@anBSaIz*b>t&w{G_$hWk((Yr*%N$g>N0rO1ngtZDs8*C;c
zFs<1CvLWW9Pm?~1cv%N_U&Tfat5CLQ#pk<M?^RI_C<_VoJdc+8q!=%DZO+*Ajzkz^
z3JHk>nYnj|pexcCH%W3zI9<B$qv*xzZIBhHc!nOCERyaM(6`x2p=Ep`6J2rlvo<)r
zol<TmvsWC8>3no^*x(z>(<f)wh;LyIKucxY(YnZ7sFC8drlCy8?VM_o&PlvJCrq60
zxT&?VP8uSBR;48tx2Jwotw&gx!Q-L0;z}&bnd-FR64;Cne?i5Wa9quZM`FpxRgb46
zdINe=WHCv7{=@C6m^nmf0Olik@HBRik%U7(XK=NNe}AOw03;(_nQzySWoqFNfN1Ah
z?ZvJAbyCiVbTrQPd*4jZG#hmx9gPw)rjOUW8bcYUUho5v!IM}^mos}i?VCh&BHI{w
z2s=5;xfL@k5d9;Xo-t)v*I0(?GWWtkq3TT+Q+v2gwDkJH3Mk(am&Zx!=%NgTLvY_(
zA_Pk`eO6-^?pF~t=%9#YoAyGb&&emBGR0%zo%=SWOHnfKG$P~k>G(!48rg)m89ZvP
z4abcHJFj?q&_@LtnLATfJbKvD-{mVPEmLf5^p{<efhtA4WbmBl>PEYI2#6PX@FyWs
z%QzbZAF%z5Y^T3I2G&1mag%0E5*Y*ekaYknbZH+20f%*DfS|jleWz;j2F^RDZ&_9G
zDMR^RQwPqRc$nlr9?{~)3LS9G2FqjZ&MFeP2pom}-a$LQCg%bKCkoMs7vi~+dFZan
zi{QcjbdMKtlbRkv@?(T>N~`_%KCxE3jb<&9D-qailA8@4)_qRA>KJi>qE_sUa=^94
z=Xx|SvBU?%k3-xSuHcj9KV%5$2R{7Mred>_Q;yz;JwMyTtP0)OS>R)-ViP!rRDh9R
zVqU;o_)ZGt6bKRa|J{7>y{!4C8{E<gLRsl&)2{q2LFOcUyy^1HB;G`LXDW>{R@&#q
zgXFkkuJqb(qS1^kgQwWN)~K=DN=U=nL6<tT9K5d5!jKC6>W3&$;%_jPxMXB%gj?ES
zD^pCr<WaXS<#OnO@nEuivgCDVYE$5N1xa>0J<>}B-W8!azz>$c;^g#8<H=!;-u+vi
z&&9#!&@Qtj6F?}Ywzxz_)S<sz8z4!^;qj#nD~BA=4K$`w>prAH(YmwF;89bd6~tNk
zMd?IwR0}@*ng(6rljm9x47c>6X78RxQ7#fzEXj)bf4#`Wf!6)tlf{|$uuT5s)#RBY
zna2ADnpTds-ORL4^doq&Q!S&E<)KaK`TrQGN<6)s%x8;gYD=?Ai)0h*Wv`>%Vzm|8
z)KOlx7t&$xB`-sX)J^M2B-o=y?BzkGPs2w}N+6r-axt?xg4P#kL<5UN&UZvA>00+9
zDBoZQNdWCR1o{UCy3D6jr^%4w+D3U|he|Uh(f2`&%RL?F$k2~EXm?XPYdJb$s`*E1
z>oqEIJWkZ=e9p0u1mNOg-vRmPoJ1-rg@|!&&X{%Uo0zDJWm3KUhp^Ua$Nh$)z&D(x
z($O%l(!x3st%%+xSb2Y&_{w_L<gZpm0IBZO>hl#k;D;nH2&?T<<;uVFT1|&}WXmj$
zl2x)R49WEYz6zqL)QkFGe{U>hkdCP}9vwk|KXobLa#Nxq7l97lM0iNwI;_^gc}{iw
zCl_0PeHyb4G++?h=`?(8j$i_L_pb)D5B4;(h?&TRn)PQpcE4W;FMItJ2{gC$?nz8N
z$`d+%i4OhL2CIKjGmew|7LpnrvhvE=T_*Yu&TTn7o(!Xz7vmavR7`Ltv8PuWX3Hid
zPm2?4{`@f!)J^nSQgbOm$G0+!5%h%KVYW)wS{^v~<FvS=LG>4O$9(fQMvv?uweopS
zy_GG(98&@$fnt_dg}DH-G*(gvEjmj+d%WiD+6OQi%fvO|0@CRxoh5r-RNLnv#%>2d
zumV8@2;<Zk%8k#l@w9htGi<IWC0X}G3`Xq1+*8ARIy;|~kUV!S3+BfkOW(JptOEyg
zt6{5j?uVqcVxpxld56K_5I=LCuLRM9__6~QX-$*THh^6|fQ2E%S1S3DkxBt(?t{}n
z9tS=tOWPBSgT;gT4{&_@PHK2?9K+ErvDa(Tp9pAPSg^`m0bYjUzV(>1S2HMGDa0xr
zWU68ybBU<-@hmv;J8wDCC!vHFE!=B2#RpVeKE5fv**io3uFms8A8?cdN&VEnlvx_m
zCuFp45t3h4!R2-Z>qe1J?S9)ZPEe+(&7o2yQX|dL3Y|qSB=>9ekRXNXX{=|3>b1Hk
z{~eoCkcKu)(TYkLan&F7Un%yJGb(O$$O$L(c4U<HdCGQtdxv4=%JVictv9+2H+Z{^
zW1gpXS{%O71dn?tO7cXR1SD(d{j4<-X2z88W3RHRQUOzNE~2+L+Bz!%fhAkvNA*Jm
z^sgJNd%7AM&4Vh?lvw-Fn?{-NMsz6$J><R`j5yP>aVG4^wT%KLIK$qYak}2x7X=T0
z=X87kvZ@A!IdPaBvXlhQI-PGV<p$O<Ch_0P6f*0RH)x6fGHF?Ia=S}&_ZS%w6NPSi
zv7>(oL_KX&*~jpQe?8HSZw1S8%EqKc`s3Gn_86_Udt$WXWX%;&3Z*Wl$-MKyRy#Fq
zeFesK_0d$~(!#2G2}$7@Y^Gg2x!WrT3^zx=2s)Mjz@cf0P8K_tu{+S3A$3B_Gn$Fu
zi4aLkX<u}BrSw&+CSCyv&XQw5hZL-RQ2rtmVfGG2BNyc{5C%2U(F>KNkFfj5am=F`
z3PI;A0QqX!jz68ci-W(0!x~hPKv$R-#kb^FI6h9Tv%FF#_r(sN?g*HZ-L1v)I^H=)
z)ver@50g<SFo!;Dd8|T_eoMXa+7W;E&1xon>Y49jgZl?fny+7YSDAtO%M)HgmnMqX
z5?HJ0zS5&@S?|>ZtW40cJnvxQyhxxwnSgXJ`*_GgaqL90Y_PajPZX4(9iUs;&@s{-
zUQaO9gBwMv{mVT7qz0aKM)ZJZ_pw5UFhwcg6qU&oS}c?hir^uD-MY8{T07;p$U)WW
zPp>kkGh8OXmKmF7BOksEgEdmm2tOpPYLN33Zs*}kQ?Vl<85cmzUBrBV>9gr^_!BSk
zj)<^YHcr}fRX?aj)N(K^88ktNX5*qK3xg%?|J=hA$5@J**qY8AHTe}dG4UyKX<Tf7
zzp@^ljC`irksH!J0Q_;)0;W>3c$rK7h|8G^vy^Md9dQPK*u(k@gS_{wg!RGPNV<em
zU|$MDml|n09q3wxZ3?fqoD6YKQ*S5LEuwSgB}$8{%5XAqzynGzBCq1`UDi1APIK4M
zh3;fHNxt(f2#xl}ecqJmHR7CB>3})F;Nu!Sn!q7hfdS&XAMUDUoIZ5PJ*CH)1;n}D
zp=9k|-_y74MpAFee-=|O^p=V|?xav>o2G<$&9ExUE@oe<sb)Ju%KaC<v5<Vy2j=p=
zsBfK>9p48=k!vdn9ct40ymP3@Xh47B+Rqiqp##ix8~fn`kD#BZ)LE08*AsdS3Vlcq
z9$Wc1w6%;W09}z~o2AE%T25ml;`j&|fqRE&5X_4tf+9fZ;G1&vPI)1o2^D=ha&H@V
zbty&b434Gf3-Wyf++T5XN8j=1={0?84@o`#r9Ic#K{8OQkJsaOR46r~;S^t!QZ=V5
z#hhD_Paqv#MacyQ5|RKC`&{^|*BL>)SPTo1yT+;yS%iol8&SuOE|g<YHw7+G`pe%I
zy;G)gf1V{4^UE24Or1b4PYB`{fR|-d7fp#NEy0T1_wakQzgEkFG$$f1)J0f???qR4
zx-r7s>}K4eoi&tz7K=X@hv`!dB1VB&E_rFY)5bWgs4G<L8dVj+>QEz+!2S1kJCU~>
zR3DgjzrZ#(1}A)a2mEd;dLI<MF+P&kB#c5gzPqBN&@8~C*|r%Hy<^?s48eJZm^`Am
zhOgxRA&~tHy>!UBvfSZ%H?zy=O|+wad%i$jT4YV)m==P`fLup8LGF62abV6v@%hLm
zPq|m)ZG;@0b0=_|`mLWu00!yHNS95Oww#iD8X_76y$T=75GF$hP)34Y2rlS=fGG73
zF~C1%$RWLN)5cs>!Vjy?Qe-@ba79(J<>&jw-rfB_9nvXsHs<)`<G0>*flEI<)VWb<
zv~s+adqLl2-(&IK+(!J@KUZJORegdy!KRXGo`sIspm*k7ocaEN3;o^8TP08#0d74q
zMg*+qUx89Z4N-Zfud9$Ly@`9v*tM=n)zPNC<hZATg=E*o-(^o{B`!vI5M}65gnS>F
zx_(PZy~!+Za5yH_t()FV41tqF%0n}S*id|U!IR%KAHzj>V1vj`1Eug%udYmISeR5&
z<D-uDz?|9m>KtR<cr6+)y?D96l#UxdP?5v<S2|-)0C<1YY|xr2_{+4!ko%W*p^0C<
z<4LA!*qh7Q?V*d9i)WpkE~@ETe--`~V>c3J!3`rA2mIoZV}T}n=;hBb9^BpB^v~|0
z`Pzrbus`kt^1hDtOaT4T%X0Vu^Dx>#i|6=dj>R>>X8LPi>GJMB*Tbs#MPM>virTo`
zZDj>!2_6O$+Bnq3el6@l**h8Gc0YHaZLS@nT$9Z&kklU|M7Z7sFiaJZF`SMSt#m6K
zi40H1R1fH^Ug6TgjkdtUP=xf@^(J7j+Xl(bU~DiKn}nzct$8QNv*OXo%!6+pU;%_o
z2Mi_F)a3+^#P$&1f3lR7*r$iSO(F$-_m^1|8r7`5jp_%kT<!lov14#7_)50<?f^<z
zLzy~0egrp0>22wdtPIso9+zSkbol$|J2+fCP3C;7`Ql~eFEo!#bd@iTpH(M5&<w6e
zaDw;?+llps*`?Jb+$0U#QSap^>dqVrgrauicmA{MJ9Nw$cn29raHaFkM~0uX79WUg
z)FRvi_59k65^cjizw-nYP}kBaH{2z<3&Ze-cJ}VOw)4v&VODO3eAa!;TtobxY$?Xf
z8ojegmk=>C0(2Nj{T945zc%yO%#aWSmLEGes7FC#kowJkA@b_!3jG4?*p;`2|4X4H
zJV8raD{g|?o9Jh&=t04F;;j%Adg&6GajmjtG6tS};tX5zT?~7vW1n4A*}`H?OX6q<
zgfYCg6k8;1_c~>X&!1>EdWEuUmX@EM(Tc@^^F&zTaAWoXk`vftk(4m1fE%aa#Mz`z
z;LAYF@2g_L2JmrM-X<$0zispXuPi_iug^Eej&F0v4MiR0#LwE8Wz&g087FOf><AZ1
z9_K|eI}mQFf|77a39G;v9zxz)rlz$^jUxBgARt0&DwLL~V(mS?TjGGIW+q2<1P}0C
z2Ee`7Ib>H~UTw)G8Fyf#plei`j#2bY%7?=!5POb0lBEjR33kc+h=<>l;-R;*KRb}O
zf`q%OZma~Z)NFOlQ0Al5aZy#9Bw~fY_#8{8<g$HC^@|e)#Z)9Vk1!w5(@;tjV#8-|
z%_9uR1U-KyDbYf88eOt>2?jCrJQIqpGw&eUb6F_A9B171Aq|+p?KVKVXw4~iaPD$o
zIW4xM{U!TP)Mf2zQ>KD6;*h#B2G$UbVW>NGWrliX3gQ*P+7_LgZ$8SMATMriSZ??w
zf~Z@>IDR53Z}@TwSS9&3fSiFeLpg4Y*X?8nK0-C*9gshjirP|w5H;Dh?b|Mhz_~*p
z)`z%5x^Z%uLp31>>0xKCx)2!i=K{jibUhFuVubW*$7h_0nnd%57ri6Oj?|a3rukd!
z+98tT8ueQwF$r2wcX9$V$m~Y7Cj;pA^W?ljTsl+?ESUyUVXrck$TBIOy^3Q<0PAEk
z$nT&gU~<~FkO{l@+b#)9u0>!+1*0)UNPn;+tjDKdSno`aTa!-(BaP*?jmm?ik&HKS
zBJrfT=#9qj6gQ6|T-Jo%G2e6qg{}Wo?Dl+^+F7xb(T=+bZx9xnJsFB3ApKYB`zy?!
zm!=5ZeECQ$8`)R<9#=mz&4?QIXD5*r0RB1?Q^pPdmIjEouH|=nfBkNhOds`TMcgq(
zIJC}&c{3v3ZQo+AZH!P#D|B7LT2}Hqu$|U-dMn7`XEylM)et4FY>YoPB2IV3i;fK5
O=fpik8|V@WL|e7gbX~;&

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_dpram_ecc_16x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..d5120a728d1c53fef21a33f44824a2f2dcfef38a
GIT binary patch
literal 10936
zcmV;pDo53e6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&len}sbZ^{w)$2Yd%+*+2STGrhaxHv`oliOM!X`Thyau{+>`%lP56
zf9~A+h1Y`rtms&KO!r)|B`FG%*~ic7)`+37CiFF~BZ_Ea8cg?Pb5(WsCRgk09cY7O
z-Xo64Se3>esT6Gn1JeGDA_JWCvH5G9%vh8WK)Jh$SI%T_zR`7#de&P7fY<3Us4Sx^
z#fUJ-XuvUBcWzLZ8-W5E9<z-n*z27=X*Lpd=3*^IEo(N2`X|$J;f3JKbf_H>?4O6+
z!kf;;Gcs?l48*Incq<4){eX30^%E`c;JY_Ay<QGYSnN3WM1=7~pJJhA#;Bv%JcsK*
zE-&ciFrYkj-{lc|tRQ{7$|$W4_3J#bI#^lx|MK#oeq4<Y4)WuH;#z*Ud1)mQ!Liuc
zQN+oPc0wX3EvZ0bSMef+ucP6+*wwoU_1t%387fzM`~u1l%qKnWSIlH$is}{&L?k;w
zj~klioT}hNsA1=yTw6hu#y4Q=N+Yx1A>P@HSImiuwB@KMMY9G&sqKBBlox-(Kg42%
zNZMAH567f{?(;<>t@EK_Mw$@KBc3O4qSALKQp@S$?2TtLqD;qLIPB-^J8zz3;AXdO
zOT6OCiBjoaDU&sI8~h*l?V}~QVsb}Claf<mDDWVst(68N%!dn{|FHp~^*$lUeYA4P
zagLC5xEVBf)FK7+kcYN|jBEfUsm|6rkeTi%2g=o<A$i-8RCdN?$u-RxBYVyRfMU!~
zQtF8NR3Ql*qyBM$kQgHy!3*Ia{_vE%XBx|-S|$4QmO(d^oJdnMy!ni3!tL^kSc5ol
z^lbK|+VRSs;UAKn;f!H~HQKYu1byfEzaH^6t!`-A&pFr9?o*hmoPLb^F7MdF(UnV`
zk{$|Ubf1!m#$Ydr8H(5{G4>&kDE~m4@{Q4&GP7Y+T6|-AYF15|N4W`v|IjEM=DE+u
zL`zq_>V@OSBj{&qt`QStG*`6D#fKYx9*P8#$%^-1O$XLB$bM_5y~nL=B!)`acBjfv
zn?bDC&{}>`36&5o_UIzK#acnks+g%W1sd9b!3?jB4_W4i1{kOIK>qE-LCqD|VrlR>
zsr<3zcR-JtZ0ZX!yWG?hx2g=_@1WeWA@5C11^%u)@8G+cZohW*CH^%`<yBZ}vyWx-
zzjxE4yBPEYf$if)x}Cem=8uGONUg@KcXIyllz6`L4_iM+>&l+#L9)cQ76q`Z*%N>{
zS+5twi(cWC<`|0sns8v~wROJ{aUKf)dnD;Qfk7H~1kqZr|F5SnXLRSVmw^!Se5uwN
zy(r+%S!vKEoSFC)W=i3l@P6GTqlv<f2y~3auGGJhDa1cy(~iwKGZ>vtRAq5t?}nLj
zo}3H&F{CHUlezMGF<NGJSid<e;m(Y#!c!#DApq!&zkfKovg&WA4x;W)zUj}};akhX
z_^sBnDB)0xX-P@}hF<=J#PE=ghuUPgzLT3vzoY%v%1MQi7WMJhZevRv=F@5KoXPE9
z9y&w>dS`d6#c-brI8Rr*V$VA69hWwIxhp=8e@9i!%q?yXuzq#m!g8yzT>QCipj_!p
zqDoPxHinDUqnOOx@}_EY>@lxnlVutZ-JO>Z1<oLJ%UTJMB!IARiQ9b~@q{%SxAf+f
zvB4EnC~^$TEp)MseM!k`XeK)jf>qz5_Zh?URu=i5%~?=0RXM%0N@crZeWUjkRNQap
ze43w@S(shjw9z3lp;>Adv2&;(X#@;<D2?$yj5xCL74Xc4M#ki`t!QEwIUlB@&g~dl
zCk~!&_2fP<)HoY(_z^ZJtQLsF&7{;4|8-VX0rt4#;nNtIa(h+~2q*1R@ocJnf=Xuk
ztFpVsx@xkAxd@it7+^F9;|B})!$xT}Pif%!nV>eKr&V3pz|-z~U#kzAZh=m9;;9MB
z4#VxWN_|^CJr_oVT}6qdve$CNyyjoi5fA~%w5GDc<*uSFohefpzxcSam9mOt2W#pL
zv!yPSmYG@<|6KihKl%DCMN9u_!C?VY-_XM5FD`n$zJhNURWifNFn%&mM2cW3>X?=U
zqxre#kbqR#?2=$0OMY=c6QNx~^HJ_vF@n6W>aDg+6Ro#l$E!`KUdKg^XMrMyc%HD6
zYySJLyr2-n7DZMrL8Gv9P~jr{vXVL;om<t7RT$!YA`LoW(<YYv0>1opyuJb18O_xH
zyXy%P$0gNBQFx3?;2pAb0>JYUwivd>5Ogzw9^ttMP9dQcQBc_?Gnnobm;>C)K4p&s
z0jM0eB(_l4m#baK+N4GgJcN!Z>@l=|i&-{5kXEU%<9fu0@G$Q_r0F!wZlvK!_s1$@
zHT5G9hGBwxDc<)!a=xq#T}84DXw9fJI^y}BX8ixcyHQ#ae``Z&VgQ0pd4vb}RUj!o
z%V@f@Q#lh6y7AmFr_pxyMehlv7(J6y*JnjMMI%JIj1z`e8?9KetB2z6_($QNO<uc3
zc!_KN+I>Yc!{_)4!?#&~+S)+4iob9!%2=tsT64>+nEte<y>g*+-67eOx+k}?%qZii
zSe)n}9WthF@8)XvZygkfwpAG!`XTM@Osg@a6(bhav=CvK?1e`y3|3*bC=9#tNf!#|
zG0(1WSU%B8$rA&h8NQPQDacE@@AY}8Xs#Xbc^NU=5Y$~y4u2SBMXC3>3-LTrq?-!j
zBHxO}{nDg4S%K9+?S+Z9z`PidrX~PQ*z9&oJYlb9F%^kp0Zl2f-0F44!Qw%s#v#ST
zw9!+IO&|e^vKWl0xN~95N29g#vmS7mvXirA{6h!@Y_N7ti4zgD8Kauw+pYC)YyFs*
zqLFp^mPP{usV{n5Hz3RMWq3PRpFRRxJXp?R^dqy33EP9JF9EdNMuqNncx!sh1o;1Q
z)3;wQxdjs~WoU84G$OWJ4^^TLujlFBfD-nUsk3x2qnu~QllEtVS!nr23;1*4bnqvi
z)4)e{80LU1QH1f|%<-kQY=HnAM;pP{+N=*>Dl?4>=R(Uru&<(XA+twyEL@&rN#y8#
zNvH=Qak9{{APaZ~kLl6U^C5(J!JUN#;V)vy^TjV+nM0)@P%B5(CcY3RwO>zRd@#Dv
z9R9ri+;K@P8nYD9LX>9RDv-c^s5mC&H4~RT$^2qX;k9sTxFiEMBNAX>;QI#h{u*YK
znb+S^Xz$Eezn<_a`TDWcM5s=3cC$`??fX#lMl##Jq)^&z;|RWG?1zcR5^%#YFew56
zg6p8RqI}GK`2=XxAOEwasHj+Oap0d*E!fSNCNBXFm*h+hJD5(5Phb;cyWM<y`!yd2
z1~|b{{atyrMv4iLByGP!LiPnwm|6XuvQEg(Bvt<~@S48pn@myg)v0S2WYVU5%LWWY
zPuXc0i0`M-6||n-d~e&~<kH22dRhA^;+1HdX13=lk(0I10lQVLRlTEn!>%a<?}5zk
z=fo+g^#-sJZDNmCXWJ-`q2(79hw_Wh9To3#^w@8EN7elXT6JY`tYt9;_1{oCZ8{nc
zVF-v)9;M$lFiC~C9xm)Bq1E(OGcu$xj9~R>*Ux*HxHKbXmXf4QL5^P3e2tr6pD*M2
zzn!hY@_VgMUMv8pkr401`6wV6Ntoh!X~~o_8Jga}>AAR)Xq!PnzRTrRNS<TGt3QrM
zjaxJ|@(%5elgGg$Ri*rD_z@EMfqw2IC9hxguXgPF%(uS0h~$d!H+I!3dUV><Du%8M
zVeO%@lv)=r9|UJrB7Oxp?qwF4?i&GrE%hnw+tZ1L6s>dyA@_C9v)3`Z+9uZZICS!}
z2IWJshjk^bup}61cL4W<3NV?HB<Ljo8X;OB7Yq2P5cf6NET3p}|D2eC-V-qqFPv5G
zKC;6@xI2Pf25QeiuOpa~q*s{re|E?x-wgPswOJF*+=NmO2cONU-Z4}9Fyb4QG0*J1
z_iQ2;5gE?wxZEEU%@Dl#bCGRRx69qT>=Qb6eG%@F=P<-U*7C=VTf!0%b=qABnT@%t
zd&TgHPggOKSa9u6EJ%G7`TKaDO%>zcqm-&&oxo2<VQMkrLn#7e_BzrHNdAtGyA<rx
zd$5H+4{+*vHIbdfA#5+#h<6k648qe8klp7N%kKh*1Ju|}j7j=<g3LFnHsjtjT@0kd
zkPRfO5noeI1|WSs%Nw2v8B@%Bkoj=+OSQNNw2K0Bxv3_j8-gS^nIORVkjeT>0I3<&
zAT_`%5xq)OqY#b77(c88x)b?AD^lG}n=LYWvEnyBzQL7oq`2nK9UJ|czxRtI#GdJ<
zlZ^`ME_yT9siaZGj~isCuw?3_!kk@yLp<?bAJ$WBYBy4nR2}cXaOAHt$PNwmsnLgi
z<wH?MQg^v^_>~}uifaL2eb)wb$`$up=kK9^&dmxzZv@-wdEVxoh>Ds0(FO-j_E?ui
zwne~e-Z!lMVWEEGc~<~|QL`S&+l>-{=uta#@8{vFK@W=wzgIe(g=$6Azw%~2hrZ)5
zdu<3Y1|IaC_7OUu{`JfWD0=R%Ax=IuKJX==TTiG?zrT=ENUA^E)%GYE9Pq!AMQ_x@
zIruWjPwP50pN=p+=BAhK$wCGyl@_g7DlmH0>OBGQg7?&XVzo-aNXQ32LJ>{{{Vy$9
zZ@Y4(C#Hcm%$cv&+6#;18-%={VXmCXF29vPk`&Hzd3hibUI_Tx0W<{{C;*E#%~uoL
z!e^kCY8DgON#$0jsRrRh;x*T%@@u1pvjD8;)Dz|Fj8R(AVWVHm3wnqL0t=fNWT0r=
z|C3_ADI|3tt;zL&V%s_l#_2NhWb&B=e>PIXhcs{2IzmEVTDVwSpV`Gxa16~<ju$A2
zLJo`U!3N!t##c;&n`M%W*vdKU+-!P>POrO?g){e{n5!3NwGIoRj)j0S%FFK6&PHd)
z5VtJ?d~{%jSP?H_e3_8j-91f%wXZ_@2i8{(%*&Eb8&}r47&dSEi;c+*kwPKnO%0u^
zJP2}Zf>d)1?d1;0cQgMPs{7;gur=T=F+f7cW9hy6A6JU$G*iZhQmxRN&FMtVk}m|F
zm7=^H<Y>T-3T{SmXk<yI%2g#;L6no%Y}wU+QQi6GRst{rnArUGYo+JD0au0?!Y9k7
z+FwCi&8%HH^Pk8O9W6xlel$Vx;4yg+K0o-jfZso?r(nRaW=VY6(xxOGw(t6#X!q5h
zRA9%3(bvjfr0Pw;EvCH*?7cd&(`PL-F64a|*?KP{t|#Bt4%^}}nh2@ul76NUD!5N=
zo(*%I*1|^)bOX%|7Q%h#^PaFxb(paoGyJ(Gg@yOybg3k9Q8e`$`=_}(>`yNN)&L98
zS3Z3$g8@Z@T2w@b1c;VRfptA6L5d?rrd}PcCDfokQaR3vmBRkP|A`GU)&53W&5sQE
z@VGs=?cr1b9q<fnF3$SUkCWC|8IBWLD%Sb*8H|h>+d*2174Lk?y?-<uE$bwXQZd|C
zzIP{@;K$R8ovHkdSjkK#NJ@={1z#%fwIxXK5mWKKM@e0!0nl-Z0rFn+S}cz~cft)y
z>Dzm<#!8nA7#<>#Hm~Z9mE+95i_1IZ)kf5KIZL^KW{mgqeO~*`d(!{s6ExxkYgA|m
z5nvmTEh>?%h=M&yg?RPFoPkjO)fb}>THdg5(RyAs!5p-njecPz>s}zx+KRO59Mic}
zS8U6iFZG$nLL7RG@}-vHu|uq_sK6lo7T$J%i6t>&{nWsw^);E&R2CG`#lj*;+mz`l
zU$%519X)wGzh7xpF1`pHYcGo&*w~C`f;fit+hm=^Sq3R~0T9=V=4Ofo-BWT*I$n~=
z1jAYcb}W?PaE}S_!~WzO75jG*C^lvL05`2%@f@RJW1U(#tg><(kIC`-)><fp#p7zS
zvPIGy0xN)-N>pyedND`I8DzLuW)5cyp^qo?Te$idR8C6kDm=@%;M~`_M?9UsA8<>=
z-8p%Mbz$t+!<G&n-C%nRjFm+<+K!1p(CPjwICrxm*{-IKi-)PTE;!-V{pSK~Fh<X7
z>*<1gtzY$$q(eEdMhns;L{E-U0|6`5Q9%+Qd_mU8Xj+<oEy@_OmK8!P@V430V?J)j
zEKpjnIEX~Y`~2PH-?h&l*Uv)*B*@p>b}7}ae~o_2m`;VtYvzgVM_jxsL|#)btEkZe
z`*&!w0nr+>n~sTJOk5jO!Q>w&(Q2>OI|)#EQ}&0v<tcVQG+zYu3qS$L1j3ds&{v<A
z-M``N`@pplpOnjxbDjE2wR(wOiKhq5o7uSDC4sWk@*IO%_rimar9ZexI8xbJVz!LX
z(+H*g6UX1^@HYzRx<GlMiS{gN95_-{nO|Q~UFIdQH}u5x`%9Rz16^}B7@4wIr2=`V
znDA_fLui;*5z`Jp`Sb1agDzAlD(3Wf!}zvV-{92D6-wCbs{wDS=nv|(e4o1hq3!4$
zehaQi(*Ww0e#l&!7f@*%$c2ma(6@pk==KEx0(LwG$)mE1EG<(xzJ<H5nccW~bL4wC
zpww4_xfZYxM_EsGiosC^h2NEGAz<$%+-S@IavXZo`^Nfmk4rlfL9WXqn=x)>d1@xd
zdh+4ZrMyGo(XKOF+}`FA*_aYXdy_UWnYw^KVVZ=4e=dhwep;;9D55T`Z#Sr+!mNnP
zt9P5lW!2paZgh0UOA{{Of4{w)7}Ez|E!hOsM}iMp93LM<Uapmd3vUMwDP9lTq|D|X
z?7uq3(s?E{)N_BgP1k?w`9AJ{P2LO&**HnxS#euic!M>;Ri97IY;-!k)GTq5<=SfD
zRPkLQ;b|C0dZ$YbUycU@3h6J}Dbj|X_#uoZEX_k?OoVaW&Rel-Ct>MXp!9R{_1a$O
ztv0FXJQ~C)ZyXaV;TdDOr{hF%RnG%NgCtWOMpYFN?p$LNApG*L<+@QN_ancvG~U@G
z=7mm;GIrX-&C5bNqbc9#raNtDiWd<L^cggpMQ-DUq)&9JCO>MQB!Vyj;f#vlG>o)!
ze^Tne{=#vrttC3<*Q=}mz|`s_69BWRa;a(ZpM-?VzB@c)oG*FGM)*qxBki!$ixJ%6
zlL=J2*>M36>oymK#q;sfX~x&)PXQDhct!eqb<aAL<hXDIX($5njos!WExyDyUq^Tl
zvgJ2Wou;g5*LFc#GnR{=hk(VzV~L#SVDN<BvoU+2BJklq;lQEIt&pzm%s%i&|M`K;
zj5^rpyl3dsoRb8RSzhmvG+DupaJ`KO6aYa*M4H-)S5(D)0>u(Tltq1@tzuIp2NlmA
z5e?e(T2XE-gnmf%2_ZE-w-IwyX$=mZ{ERi-7xXYATRPiMU^*gwyk_$AVH1!i7ucjD
z%8Z2-36vlg9t@qf6d5VYSAk8WD7g+&S?ea?$N^Q?3;hXiB7j2iL4O=KID-hex<aHP
zPg;rg`~CRcgSMS7;{1(Q3Jl0WRFB!4Sd5UuPd(&}1ub}HSa!5>`*Y&C-d2HNLr&b~
z`c&@1G=MZhKBfs!Z=gw10-U>#!&{0LN9|sa(p<RH=9bKu!6@qdJ_RI_C4p5UU!}il
zYEQ<7n<q?Te5doW6&i!QCxTH^2U}PbsSDqE9BoWU{#n4=l>(`pq~W|Ptmwn1v{~*n
zl?I7OUh8=0#|W4_!zMbmDnCe#(N}?JuU1Zl%I}sZgUEjKtB<Y0*u?PKWfUjylM1AR
zOA$LeWjQsE%Y9K;*?GIh+=wz*@<0l^_ioL16vTzP-AT^y2-O_})a)<-%pLW=l*#Bn
zxz!sqJE>|H#o2f=Jw8gh;!4+nbxl8R_7k3>c%{K7?1e?P!)R}Jq?6z$9}-N9+A``}
z;@42y4?1I6zdF}5;Q<mQyc0a!l?z44;DO}MHcdGwqrKL|l-Y%p*3$LRzGuYZZ%1Nx
z?I6|n?)?S+BjA4eRl>!avpN<mJEwujou2FvP<YaS5-6B$eYt^EQwC^{kWTSjuqXZM
z#tf0=N<?kj?)vCKpe1;6|DNd!V7wHuFIiI03<u+X0?P@|Drg%iVRKcYgX+u<SG3>}
z)|U?L%vgcR!msFQo!++%hFu3D4y+NRkGV09rkpp~-Z(rPOaV7b)SF)R!(G3RC$r88
zh3^irRt^4iac~B|Onxu56zpD-2>|j`z;+f?V~du_&n(4_zKDVTxW0^jUQClKH-@o<
zlLqa(qT54){e=m7I)=~!r$(%I;0^9i5uPP+$Z{!fgLpTohAIK9*L-$+NEz%;mt2C1
z%5DoQg)>xtnJY*930J@nY|LAXzy|}@5}^f9e|ywWJAb;f*3Hhw$NQ?xqSrp(Jj2|x
zPvsw3DnJ36h-N=C>(w^ysuxi5BMxdds4o?RSX5<Zv8Sg^LoO(QNt+YmHBd}H^<Bu9
zPzi8qKCv%vOLcae9hoz(D94czrPS0bVuIF(z3~rr=XCaL0~QVPvL-qXyoTP%4B^B`
z<CtCia4ozRa=l_GOT}l0Wo>|BAbHn7EJg(+!ot+1O%0g((l-PdCO-*&4lSy{VF?&5
zEVt~d4tt?2v|DFwu0)*3S=cVO-+RVr1!z1vC3Dac^1G-?g=_;+Ie22>h&(UUW6^nc
z3En|Q$U4Uf(`3|#+<+8;`XxG4I456(VfbMjE4_n_Bp)}`oqv0~t9w4HN?vq(%oDT7
zalAkS)`#<_$#K6x_nKJEYYT*P1~kml?Ge^Sq1mH;6h}Vt;<O1?b{K4%qsY1J^x6BL
z*&PN5sXv}h;<_2o&k&1bffuEI&+7q*H6fJK4n;tuAC!6Bhj+DmI#0cyVoBCNyjnNu
z)ZKTZaYw%?N6qehmqf?|mx+6<ke7?+cQ#v;s_BRYH%|v`kz^|_=_s)jKrGTfw~4Ay
zl+xp$b->1UYT;}<vKM5>-+24*qOKqP^F-t+4I~@qAVAr-xiN&BvCK);54puzdzKfe
zILNrb<VeSVe+3b&tG3i5#rOO6!Rh~-$K=zfDsk3=tp#JVI0B_4afVCJ+JNzvI!Gbv
zuT}BUBi*@4p$2PN&Hhe~#G#zyf`4#ux4d}T)IL0Pp6xo6MUlC|0!6x`1-Xf5#smVR
zyXcP=m%m|^Lx}YAV=2?)Cie>t*e|11mM&b^HfvTawP4i1(6j`MbKf}+;g}**&+YfA
zK`~IliKf@3*_HE&J3@dgRZDy=3?Jtnz}C#iLx?ikr3>D2S5cHS4ec(5Z#JJbb2R*&
zQe%4P0?_yhb8bK*Z$T#>6N<{><}d6XlebDN1Jf$34k9j(0|+fYRlh!0EZDKYazZAr
zM8RBY9a{fi4UD}t_d8Z{kT|Fp00O07V`~##<9*g&X6<@y&-~AjD8B%HxbRsNLJm|P
zy%UG7*d*EN`(yD~b&xJr_Vxp@lxJPD-gwwwbC4#Slvi%J{o%lJHU^s?TAIUk$;mI~
zO#KjdB_)E3);(}5+|-pAPjRXGEZe0e&(pu>;B<;uFZ=|7@sY}zJ+_sIab`EEJ=pXw
ziox6D=LU-0(I}i-9_a~%H>*s+D<SZ1SY{1WaMp-V+Fsn@J9teD2k7UEW1or`uLXGS
zJNpFOt8M$G`S#+!O^mz=Y{6#!?hv6txQrNneXU(R8jk94EEEG%tteFBfG6s-7iX&z
z)nH4wLBk2=igMfnD10cXs-}+Km1`(-VbQWSLd6hJbjwFWId*%P21Ix&CuCP87lfYU
z(`?M_ZWh>@A1|6nz%Qq4#CmER)&4m3Ax~;uP`^}O_ClcCWGUHPGQ=%a2$)4!r<r{A
z)?%T3kOQYSL;e*zQT0Zt@2G6r3EOa#t?f(^%zw}EGR{(0QxW0|X9vxuKW&=Jbz9@)
zN-qb4@Lm}8(ykJOzg8YQuDkGf;1FT?k(|pi;H87hbF;NYDeET)ABVUN95s3SM|eqE
z*WG?SS^%KV<6uw(I-9`WoRx$%TPG&g4sheLea)!Wltvz`whO}*$_WLQHKa}6@Rex*
z_D_Tl2lvv^B6VIqgX7hKudGtq*t?R<D?kA2Ll8Z0R__Vz&_|KPde6{UMn>KS^~?)N
zQ;cf(Xl#`3Ca=j|BBZOHzS&Y4;0kx*{Q$$;m>~zlIp_@D<3+|5{|RzkEKa1@`{4OH
zXX7c_emm~B1s6Z_9n&+2k#v~nw61$9!YpZELG#ChKF-FbrLfz`=g+!5Nb&ixXX&gT
z#a9rXpRT>(rx&ATwZ%kg8R3A|lQO!nTO>#u7Ed2?*)BR(J=)ELhQ@(I5$`nNdP0N5
zyUG^$elx?pf3A4JuRB06`0PRBnwZZN`REH!%~}6y70UZy<U0LHc8HQX)i|RX{WPQj
z>8U0IXsKfM+WyWRV|2c){PjV(#o~<Nms=h?{t!^V8l{1Ik3AGTK=>*+N@;XdXS!%O
z0-#Ma!uMnkXoP($2A4VAJksdXYu)6#n<jv8GP)qj)~A$U#ut_f%B8btIGbsc{&xo>
zsy5>@`a!wtvox%qI+zG~wG<1UBM38Avwl+#YNbW((hZsdPwBnL!c821t>J`41G>dS
z_rdhaGFEKdOG|*;pEUyPX#6@d7SXWm@kR|DBSD3{Blk)FyRu?ytyCnbeHj^<aVpMk
zr7wV0srgm~IW}?0Yzu^jqC(W{Q94e!rK%ciRldom+~jnw$*6*#i>&@kxx4>YK!T`(
zUPJh`sNwu-)Y?{64R?6r`W5|JDtbEW67EjxPgW+g3kq*S1f(uVhbCRxYoo^(63TB_
zq|q*i*67a4TC8|QwZBmUmEu!JN^vl_DNATGjC*(B*2XRm<7Dr@$dik%P23`;y7WLC
zUFu^ge+cAd?1qABD0zbA5Q=pHE1Is%WP>1$i7UdM61<rKGXgfMuxRbsbOqPTqg#BR
zf*@ps7N8C;1`!VlJJ2B|yiHz%LZZ=l>uDp||7{Yd*e<`3Uf~`gPxoD<DDrieo#E*T
z;2gr<V9uw{1I@r)=MLZ=sP}^PiMy<1VrdJK)PfYmCRvkj?m%b?02<|gMEuNwC|s(Z
zDm%R5q)~unHabNxdjc1WBpSs_RIo=tti))ZIWH2x5)}*CA@g17-*W+i$!D>8Z{Sy_
z3RJzQU>&FQAN;^wWm@jy{c|Ns*n4hCAeVhU>Xu{#`N=<>hzyL+fsY%ff{NblA+Y4_
z2f0J&0~)N6(~|%=I>XyH*UB4gTTq+Zv;OapjzN6M#vaDec+PSr$Jc6HTOp14v<(bF
zcegFrv4nvPpCfgn2i7@<G&K*#jb~WW##LziW%q1>|I<2Hsj9+N%Wt{x?R~ybLheme
zv+3V>+f`6Pz`0S&cGEx;ATB1~X0(*?z5~|Ktw;$>(=*KbZWa+fjIkY)=5STrxrI<c
z+&t|exrQ7Rk^p)bit_**t#MfFMhBJC%G+r&jdnXIaH>9jR2KN$h@%B~>Vkvh1T;)j
zxe^ef;-G;J3;E^qVW>=YnY-Jqxhk{*J*J@`HvO(*gRb|?xM4Y5KIu=#64fega=$s|
z9ufPv25)3$XcFs>OdfZ$&~@Tnr?-y*^7W*Xj?CD#g!*W@*yOPqnin{c=c0^kcu!Rq
ztA7$Eli2P0LIoeRp&(uD@0|RyyEfj&dFd67|Ig#l7hn2o@%rMccp^jXpmYDg@me;(
zZz&T`c)~llCy4@vH2Urgl59EDd6r=TOeASH)9D*;gY~VL!4855pU6Nklk22~($5hM
zj~P73U|h2SHyn5)I|HK<I-c9f<0kD&Iilx`06ns_{$jnIi)Px*n>8tJhnHuGjNcwT
zr7p0ch3Gv1St`P`V=AR>9A|c{3J#zL86IdBvf$Ik)CHw2h|M7fYV=kKwSOgUWOB4i
zX<SmUG<>VL1B)WOF-S88HT$hGeR{1WO7AJ~R+)*Th|5+cTd;>vo#-mE40Gk2BO{KR
z?xS>EAL;P}3{4;rowznrjvWsYf94(^DVhw?VzT`b7rcw6Sc5LWVIrNgpQ}B^`LyTu
zFI-D9<q7)=G7azC=E{K2(q^Ak0*DUJ;`I~Go{jolFZHi%`T#4#bANZJHo87$4Z73<
zw3tV^y_J~0z?%fP2=UR+KPPPK-Epf@BJk0fy;g%S7pYjyCV~L_fG`vuvM%2Gn3?KV
zXHDtbs1ZFXwHZsHtj;_zzn#L1aES$3RCrb23-ny;o2QN}&M(P)5Tjq=&{QozpiEun
zm*Uyuah9^?5p;-NgROAjs~Dix*{YI9hCzP~adr{|ICEX^ZE-%!O(ef9n7oAK*UHq$
z8bupQZ3M>!qqKno)Z3VnBQ5UR&DRBbJvns%5ks7xJ}p`x$N{UjKFdB8sguFz@R}Mn
z&CqtIB-IG0vPO#GZhGs1m03PO?kLU~9)?2JtqHw^<??$}A#Rw3xYNv7dZ+W!P}oMr
zD+r8t7ruBCY`EmKugR?>h*_y_A~QZ^({kbzh%F#q%~(*SSsY$M2^ibeQDik0*e+kK
z<t<94<YFLPF7mC1#DMIlBpB=JxD2b=e<034mc6F4w-k8Z0bLtzDh8L|7+xd@O1G88
zc_GDZS^+%jZ3%?A&`|r;*faX9cf*6{7(k|bc01LW?5RH10U;<cQCcR<qTu}h2k_4)
z#}Q@a)IUYwJ1S^U&ciRI8?RREu){csko8t^PV949<iuvglk?fg*utM-6n0ujOYtSc
zrXBE8cWT9P;46#Hb1HzU7N>(``lqQ~&>goPXONL_9|tHos>s3GCL4Jm?>BX=^H!E~
zteYBlv$H=2TyTGxOj~gtbC=xjIe*ZYf|<+14AwB%<zpqfLlICyC?3u8<;$@X;rSW<
zEj`_9=pEorE*N353l$kKL0}9w9%XymIhF-dKMQ`ivPl^4gahmUOjhe0LGhQARHO#k
z#-(OnrGMp1Jt%$G5;i7llmgKiR15tGz|FoFO}y?N+0R|Ti!?bx2=48IN0-WT&{B2b
zKYp{U5^A^SthWfEWmGlR9O%Ooowh16>{mB_gdvqKU4<KU+qk1-{AxB*y?-LiR|(*#
zI{w;)@MvT=kMAT^$IB0sNrlPAlyYXA_=rYTGrAksV_&8E6YHibYuNDkC7C(OHwBcg
z^ChxQYs`DMt*}hJO=(+DN2M&56i<Y_FFut`zCXE<S3_fyth5MAsnd@;W-dAEKUROB
zB-$p*hVh~GgsdinU4eiA*w~aspRN}GjEhozPqB+GTVNcXa&mg*_Y-r6v)KkHvf7**
a?(7Lr?*~20<9nzQ>#B{thIqo2m+iFx6k+E8

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v
new file mode 100644
index 0000000000000000000000000000000000000000..c4c9b594d11dcc651284fa902584b289be3490dd
GIT binary patch
literal 10824
zcmV-OD!0{(6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzNLRlWvKgc+*ufXZH5-_Scw>wvpE
z&#jGbke0{LcT>5nHRVvzBRdG15pCZFGrAG})J(fw_4R#9==f}=fT0&RIRe3L#$wD`
zI0!j8m$tUu&4w?19?Anu(Y%D2s{*1|l5>Os=_8#2kUL=z4sn8|Z$Cn)x*OO)+-i8`
zltYus8sPvHKYUK&5E!x3LPOh!O;2xpU{{tZ?>moBI(|t`{v8e>tQ=~Mh693+5}wCm
zYP4Yjaksg=%eMi_1{hp3OdgwBZZ``T8=7AetZx)e<e5u$6*XUH7nbXP0mg-`&Tnm8
zO%4C1m%JY-Me_*3u6u9e$fKNR?zlzhKS#$Jx8me;i5}`4SaM)7@_|Qt+mo;u@=Cj4
zT2}_VO_{A@m$4^?RC@*eRB&ecfMEsIL>H1i8W#<TuH!Fu6m}#z9fZ#D2ev(bi6DOM
zkH)28@=jGET*3vHjoyF5|Ck0zk~2DUppR9v7-{P>thU(3jwoB}5!t+wCh<pQySA<w
zUGvgyVdbV>VP(8kaV9%Y%~crSI~@Q7zS4S|Wjan2upFMpkCvuW(@=0+Atts~e*J<j
z^7Efr;i{`nt!~?f4=uGlTX3+nX}x^8s9EU&ZG`Ps$a(rOimk;f5UlRcM?|Yz<Iay)
za$}gxyfmDkq=_9(W7j8iL((zP@nqlYGKw^VYB%o})iLJ8N{#AI!)fFSNPn_cWT}X#
zd;E3lm&FqiCREEo-?T(U2`$M08lUwcdLWQ#Q<+s5&i+Q+ei4|IG{vF#hgLZF+*<9s
z0OTt?fkMZT5`hOrYD_k1HX#7`H=`v53PKacd<ttk%C-X>=Ua^g&>Ftr7Lr{T2#WKY
z1)Pn47)J@!iyN{g(t#fe5VhMKgL@aweT@Q4fihKn`<^=v8szTazNQ%E0{i&}C#P97
z2IS9}f~6_#SsQ`<E3a#N)~WP5w7Pi0ZYj##TwvZ|&a<>M7C~b9UrhsZeF}QnA+Kx{
zn#Si}1x+Q1Tp86pBLqu*7fh=c{@?veWB@)9?ddT3O&3x@`41M^wE>g~{Rc(%osbX}
zXX$H%_t~+TT9p~qVk5T`fS=|@R8A#nu8%XvWmb9<mY+6Vqnsw4U4Zoj2ZY7pw|hHS
zIy}s9%ZLM0-%6(+5_o~QWOumIUomgIoUy9@n@7uA>?`LS-fA3VPpFCb)&0sTp+s^U
zY?X(Y=4%C_J`<TtVa)ptf#&YlDLP;KRMmWDe5ugcvx3A7(FpB!Cf$cQ4g7AZ?ZN&}
zk1q7Tm?5wZUPX~sEj$4^bk058^_*8RI`Hm>gZ>EE*dd2RY_VrAPPFZ|YAe+!v;IkB
z@_+)NnQ-`B8FuYE-|Yvqf{TIuRJULVRo<PW>TSJtgSh6G_Thu;42?O|D5QLjh@I7%
zBqu^6`lQa=Ma2gs_`(JjX&&K@dxP@1_1LROf~tD&TNklj8(sb<8IuEN<?uJ;@=Ukk
zPYI!Tr{>B;G-QyX;}=-&E;yLVvOR$-=}DtC+e$G01Gs4WBRO?b^x^S51yJuyBhq_*
zp~xA%LzLtWX%QmxT{wO*RKWi0?VF?3^3W7NK)p**gcSJLUwzYTtvtf3mI%KAWINI>
z!{=10B(LjWkM$Kk2>-K!htgVuCc{CSDR8+lJ<SmczXNZW$)I8$ztKt+k<D8*B=a5d
zJbU-Kak$qnm@I`8!7c?qwy>-^JqyMrtXiVD@B<CjK~8v>$*+uArEy<AWR=hl4UW&G
z_+-ykGQ_^bz_fl9z6J~u5YM9`$P#isB)8A!*n{h1*d`2eAzpM?IBTegR-=-42({Ba
zV)$RPc#0WTaIFXOzF#ngnMhX-JU}rlvDJ!^hV+9_1p;CMUPTt!)d}bQvr*zCORFPZ
zo!7fz!fscO@^n=(`^GE<{;1)Ou!{fzt8*VXx{b~eMni<I<&8fs*Crr$_0|AP^sx;H
z=(+w^dBTuCCH!;jp0h61s6h#DpE666liw{eZJle4I_;<lP8zmmv+i>cz`WK@Z4RDq
ze0`_TmzW@R%SqL(1kDZKN{=7*vf{!eiEcmlkMVY}KLI2={FrY>xcRPoK-hv=09c$u
zF>~=Ws*LLXU*u4<FU{NSb9%^382W!5?UH<-VM1tw8_@04+3z%%mv4X&>6oqmpA-J9
z0bGT%a}pt*h}?=&`cNX0&CjKh&xc*6*mvF#wF-I0R46|N03>2zFIQxA6pwWI*Ul>A
z+x|sq9)e*~EN5{1-&pVU?2<Q^)*ZfugwA9QO=y>BvjRgXwM*jG;Ej!%$g1ZdHS!s#
zeK|(z(S#Jlh4+8gk6hKeey*har}D><8SqeDvQjv^Vc;Amuqn-G<yk*&N^5GzVR@Vw
zlTOFYy4zO#*)gcU(Ys57ll%{zJ^#q!8w=gX^1ZttK2C$EzO^+iy^_87`J!PCy~W6W
z2w!r|3uR*-5QI@<7_+E){-w~FK|L4%gQ{vm3lbDjD!7yR;4|6jq~8^xS7VGMB3}q3
z&fIpeSd<8G)`#V{&{x@L2UJQ&@eXZ~)&$78C0r>ESUxQk_ubffgNZKt+Tzo>fTgdM
zLYNZ{x`e8htF_j*uNdbi5o%M1xs*?$baT$TwJ-M|ctZ-*8*9}6tg^Jbj~Zr`pDgML
z$1W`Vn%1h!s5}|g1T?&Lzi5s7iHitd2$2}qgc2i*55}ut|1xv;hfuA-MC%uq)|EVu
zB@-_duoK)m?GNVA^`7!p7j>zodiIhpJJa$AhID)f`*6IDVPMDh)lwQNM)*T)nyISb
z&oEP_XhQeEE-|Y!V6HfW&el!-apGJAA`R@PxIz(b<r{UPFHQpc(j0;56LQ|c@<5Dc
z>xW$J1m5w&M7LV=Ik;N6RWT}xvvCK+5N%{@{x#An-r_EB+HmH^IYoZivxG?4inW3-
zS;@bk=Un72e*sl$ebJ^|6j9H1n*8+Wo?f7Mb5cNoV1SsWh>?ls_AF+<k&sQ=Wogmy
z_Dqcmx8!i8)d}HQXwg8yIL;w4_)D4J+VF_l337o@)>7|k8at``mxP&N@VLyrt#j|#
zmt|)_t`{k==sO7^Yo;0`RBqoNq%dMCWND(<Hc1$c&(AnjnI11pQf1zZ*IiWxtMHb2
zepn4G4L`eFPiF;6MewDc6XvM%dG&v+uuJ|6Pxb?725oRbfk{x#(ckovxE3(L3nl<@
z&5KU|gg6z1xnZ!fSGJa&Xok5%*1*ozpEZS5gGu!*IIr9*Iau`(%?LW+StDgLnNHsV
z0ezkgd>MG%05$CP=t3S`_Ky+iLHN`#<Y^d+(tamw)Qpf}3G#IqtyH`0aDKN@LYa3X
zDWKw*-bmX<<sWL%TrA`bdIUD*qe|=DuStlc|FngfA*um8gxP>XSPL8RITL}}?A8OZ
z(9%z26{OrVuWO)o6Y#n5`qfl0h_~>RF3HU#oLpsls)4x_=xr1}xcFTGv)Wd_`Bd7@
z9;CDI)P##;c}JFe90p(w6)Ypt&+E$U_Cw&n!9B}9x0Fk_oUai;cDlTaa7`YeI2Kuk
zRwMXQBD}<ntJ$fk5R*#;qwDc#cgYrMp#bwHPvDS%SV@J@8rBm&=pNqs;)YJ`L^y;~
zkmFfFq`@JJ@^^E*;o;O=IR`jEjGI|Q^@g^}1bI+>l-G8FPvnK+ZWc)P)?`sE=@mrL
zK|#4Y1fX)355e^(0%64ahr7&E@BytmOmp!@Nru=`-~4F6BO?-sf+0t!IK2uWRsD|i
zgfCl=dQOWf6hUUjssK+p#_<IXx-VwFTBxY>O&+ts)@w^wq;H-*qFZhSIR~-2kixcz
z=m~G&oO$3h+#<3excJk~V9g2pEjj(L2Wo#HEAEX4PrZ6r{1l)D2ElLvUNE_dXx;=x
z0cAR%<ZX8I+w}VG7X})Rhqs9Jp|Q0OpumicW<`&;d5Mv2XK|=OU0N9k4N2%7o1FAJ
zvS><Nm0dJ^XC?XKDh}IY2si}d^X&<u?0OMoRf`sN_X-<A@H6|cNwbm1ejP@NtjQ^a
zETpFQp5#mp4#q#CWzGSn-rRM;#R;HqM@~rO&e>_@1YN1>Vf}rGx5h0aXs#{iR7kH>
zUk#qEu)_})v5?}O&-?=cMY=&Eg)$qw`c#razdCRMwpu)>#2A_e_{OI}#&JPL>nUVZ
zI)?*3zaw1M?S#M%FackKF)TlfCu>P`kQ0s4*IT}PjB@N08~iyyuIyaOQzhR$+(`3R
zPh(lAx<PG@#e{(TX;xwdMp;y<4x#d&x<j+0aJycWWuyWd+FpuDlW2?D!G=MJjwPO<
zm-V08cBJR10&v1>$Zn;FOYISh-bB*%T~ynRlt@%uZ6`4LU<}CLINuQ**tY6nU3XsB
ziQXbm-?`|1*&WusFlf<|q0rFnik}Sf7!OxuABZ(I$g9Dki&pQ4;yZu*d~3t_8RZ<7
z#^jL6E2Yp9;ATP^;t^$iXwST~)X`P7JxuwY5&`Tk3`7=G+Tm;ol=|h+D77n6CThgm
zP@gR8s@KDvLi~Nib3V8NLZax^fed7t3~qYa)da`<{{pZ`M|4mYPo$u#q`e#!v5!dY
zeuW3#IL8!R|KK+bSql-9?^QrJ$mdP=vCwbG5wmQz;CR;YZdjXS)nvHcjBTMN$r6?t
zIstv~E-w@c?TNgjC5I%w_5xq9MOh4Y9vDBPC2Npzz}6LrZcQYQ`z5)JDcA1SC@oJQ
z>$dPu{_+9IZdrh=SItg>T!GqO;&Z+Fr+mY^mw)U*aQo_AaiCIfuBe1pd7*^+%gRn?
zDlp}a3VUYfuFn={b2DpaTi^(X1SV?Gt<a_KDhvlTW<Fj1ykOZJHDIiqL4uH>#B@j{
zY>P%EG-K7jZ13dNA;zo@(BcG<!M>IBXhwcK%Y@ud_N43M@Q^Z15X`6M*COWjlP>6h
zyRQQFk%&u=2k|gs>k7`<=XZ#m2s4jgl6YS7rX}uXDJq`4LNK-EnYn8@h^sZMyIp#!
z|384MK0+J|l5@PYS)JMc*}RmGpO3|#;wo2zYcOYix`=Sht9=!*B&(3aO_e}0n?lcN
z=?stggrDDk7mZ<yuoOHiP6NPQ24~UytYMT`A62GogvgFzOfh$@EoF&V%9;mV+|J%$
zSD$zna?$A)`YCc#zS6T!Tm9&6#^s3xZ&*vw54`274}#HOuKQ%acMn^aH;o~7CPQ0;
z(40_nF~BiLza#m(@Cj%1ICCmGD1*)2Qrl{z;KPP~-^x$c=K&C8DNm+jqHGqtf7tyS
z*TNXzbz+In*19It5RPJoH=#WbYBC8S_4;KS3KHBDpq!3aV-i=CD>iv0L8PqBPbCtX
zoKQ;%^B<<@k__$=+u^(^Qw~TmA77F+6y&oVYVE13aX?BNSj6rI2!Yj6zAusm2XDlJ
zq@E#lg(weCZZCsEC<t8^G;>g^_LbUruGHAJD=K*cMs!?35-4muBWdts>Y$6Dad7ww
zNwj)*%ih&HOT&uX5_m1fFuy=0GgmeLvHsN0VdRft?I`1HuY@7CJh1|h(^M6U%gZAf
zWwA*@@5IdyqV;ku*dHKns`Hqac?NE+d+tezQ{SD^yq9372_S0&B1m}-S<hENNy)TN
z*Pr_WLW%!yy;xwmuDl_TR+s{`K)t=j$VmD_RDKP0;~ax^t|Kixhr$W*(ZBW$zmBB$
zASJpLlH*RfhjJtmQF!%g9?%Et+WqhsouS$I5zt#6=#cuM<v<0S+HwY123{N>%%$~x
zFQ5{K(IY=_S}Wl{v47&eEqdxwc1DT9O-vnMqBPqP?S^rzzLwba_cFm*wO<9);v-}f
ziWfa=U=}!4DAmbydr&Byb1=%(NxSql=@~m*U!Qu^E0`rT68~zI5C(%|6Z;UGWN3+b
zrotfu^RJ?#fZ%^$?OpNkJ2dm(mHa){vVb~FmlE0gBdAHBgnM47OwhxqJeZ_)k;A}0
zY3p99xWoee|L8rixII0z`!C8WOP`3^4n(b22Ef1^QLb-UtzaIyoE(!-XtCCf5-Tg+
z&c%P*DL2~1CV8gQIdFqXH&R4<U0R25>kXG+krhx~!T0zNA_fIUqMj1=gUFISF<2TD
zVG7<%K!C9$C=&0?Yk2U!=u=PIFf$?1%5;C<9~(6!yrf8{FT)>Gr4Nq8XBui#?E+l?
zv1G((36>*Yni{2|eQH!%r^wcC!3=iUO|-pFjvGoS?$a_qIk#-*mx+=PaeWla^=pS{
z9hNXUgmH1y(7BBe0!<m0-G+gR(l$H!na~L*inUzE@E$Jl;9h=~`G94b94Gs%3Wa9l
zUPY!}aAQxxr<0Oz!>xN0Sz0AZr@B^7hh9S_V;PRY;p8In2~j(44Av%zK#{v$(*Bu+
z!sM^B@LTh>yKtF>l!_xY6d7raGs+~NYAlJcPlQk6!gk!6fEq8B^+<-Y7;a|$EOYRI
zRl*@iS$%zzy9$Eg6?}c`JS4q$3CNx=SH7I)K`kF4JL|VUk9N%&qN$7OPJDg$4l1U3
zmfxrx=iQ2VFo6R2w;hq8vBky|pxLp2GZJP5R$hWle`e!$BrvIi{BK3Z^z|{7P(l1|
zp1+MlU!6-FT)%7-)>>b5qVcLjH$j86^pa@OI6Y&O1`%i&wDP0Np`cL;HHK7<-}L~2
zuOSwsHjN<T*9DgI)n9N?)+~xMj>=CQ9;HYl`N8Nlli_%znsL0NHxf2Q%`~t$4w52}
z|KV~Vy$x)>ei%rQ(D)=K->+1UOeHkLDj5prJUYr-nd1YDtc-%rRbC<yDCBWbvIbkF
z2Q6rIHA`^n?l$7+_+H5U1pv>o5SCI~-*2}U1GHydYWM*b7;t)Hj)iLK;4UrGN8a{<
zzbkdN^9}8+8i!c3Uy^SQ7zhiou~O;q$mbGwy50W+F*l%b#ycM+zKnt`Q2SR9ScBnE
zI&Mqvc-ao2l!6UGKfdI$#bJD+PpzVx?l5sn4nleJkgfs&!)VvE^oUWzDazFh>7MnF
zdH8X;@7k$l_}Fn2KID9mEqKx&9U}3=mt{>_-v0+%c|i_mRf&4ulv~7URD~vk>C|s<
zK9pbg8o75Da4<0>?rE;WsOZgKhm4}Y>%$*$O}GN8T3=-!ii|s`Z4{^^w=2@!rp6uh
z9=Z|oZwyN`gl-AD$r2FEI5Nz)s!Wm@**tB7Cj8?R|4}nD+Sf#Ao7z?aA%NT8u~RHj
z0Bt^o=3#ZrfHy{;S-g>;mjJ4#XHx2%x$pp@Mb-iVsY{7>rXG<Jnx=vriDIZ)ClLXE
zN3s`LGnzn-`x28EHx=Z64o^v#9GgshPwS_cD}5!1gSap|`NR67hns<)C2~wthfJ5c
zBH}XgCoOXb5<VZ=GrFQkXK<L+B<MOkDVgG)U=WJ(m%W&c^sy0qTmhg(4r3Bjyv_Ud
zc@X=`$4uYF`wE6FNEol%4A0VOJZ2)8XY6iFZT6BzzMK==ovjIWGBW-Ka-4p<^Xp|0
z(oLP$=ze0zke$_ctJ}*O*ORpedN;VzAyRiC0xmf)Q*ppp_J1D(gdtJVwB;q4ZWE7=
z?6b*Mapi-hh)jA(s4}RbUf(5G#M8y(<=3nfjBU{=T_^reaIO=zi`u{gP8La?Yqcnc
z9?I_%128}X;$`#M>@AfD{0n+jVf2l5c1W#WoXxKu@F@0ePadJi2@P%GV3n3}$5Z?-
zTC13oefHLtB}5Qf39Sx<w7bhI(#9|9<$U&>slB~Xkqb92vUX(bBx2r@rjHil(|Ch&
zFm+lT(4*8~RSMDOc~@>`ku+iDEP~CFF3GITgN(f2vqo5{!uBW{j(%x<y=f@>3FzEQ
zy;=+C)vJF)8!_YmaI(^di?M<QcZ#C}9a%ERmUeKL7v{3c^+U@t$7zv0s;8Yk7DqlR
zgI{JHk|DHd_jZ`}rlfs41@{@ECkFj1blnof8*mwwDwwD2D(@v28dyNIst56qq8rSc
zzE1lEDl{qie?`5}#O@y`sqBwAu$sAt8@*~3;ovQT#ztUb;qCs_I$sps6@_d8VuDkT
zAynd&bY&J`Nx!Cz)kDC5(EN2MX=7JHW(}yNRva2VN;`ND9$9BG<)_v&H`Ib?yJ(c`
z8+%cfFMex!%;MIB_}sa1DHQH}(+W#k-w_ocrDqpoa2JcS;c}Hr?;T*>3{H<IhRM9M
z2()3#7!wV^tQxGWZ`-0ODmlMwMM#>D$3^D>eNqz6O%zeFz^pv5Ewhji-H;FE;g_Vk
zij`a-=vRua<!wh6%wVX~+S0Z$YOW8~gd;vLEN32C&5#UGBCb(hai5g)i1_;hZM#S*
zEul*fzGJQ;HBz|L|L~bVy}jygC{iJKhFRa3dkX{)8r%H`Dt5m|RmxeARyicROu8t@
z{bPXVGFaGJEOWAXj>@0G9Kf3FP^Be1fp|hzms|8>OAdHXg;VVPFb-v(PP|5V76Z0&
z0kajNP_r7{gUOtkcL_X7gzx;!f(RiqHo+evvkzKe{(fa_wTj_Wspz@6xm1HKmMwBL
z(fyrKG3kqn_vYoeQ{~5q>87kw`SUp$LmW;c;D|Xfc+FJQL-Lw3qJ}T|_&SmIb^Xbr
z{@#iJB|kadd6r}~GYGp4STZ!0Q4&fj8VrudR6GrFKYSB8I3>ibSxuX{5pSiP8hAPP
zbfCn-%r7Qcm{JGO06DCz0B67-joqZ;*x0Y2>Zvz?DU-`K1(oYmt|RfY7b#`C5Q2~2
zQ>w#Fp<sw7f$kfi*FJ)8NMR#mt7Lkr9NHwzj*O1<8_}njymZhIR29NAk0>OR0zv*C
z%YrIc(8-0WXe|ErD8={%*wmaFh{3{w{vH5I+c{h&h^XLJzBy~6e{s>`KL>ZMuG9w$
zTT0t<1IdeusVe;N|0ib&L8J6J>)?jX-Z9vLrvcHpVdn|^=F)z^X=fygC<+$;4uk@8
z$`$s>lG17P;_OHDJ?7T+o*2C?btj4lqb~%Vt8c}TLWj#A$E$CH>+9NUnisLy*O&hI
zbk5auHkgba4H)6=9O_g!c<JMyR1Ulc!5~W>czWgvUAve6fCH|@kDp{-8pS16E6HM*
z`9XYsn7>Vb)nOACqT5I8I^XzmV(sz@aZV!+QPr}$sIj`e2hbynY?VSaxYy4kp43VY
zJIYv-oV5NK?>~|IK9^C53=oKrSYqF|NCX7;Y-M{ogLf|MY`}B2j>g1L)~6zT#$P^6
z5prxj=shJpU_VfeoQ9>np3}2C^2~d*s$y?;7Vl+{fS%!gM)huNjcO2bRvpi|&k^%`
zL+{O}_(_N$I-&jTRV>O45rBll=e%~fllkCKN|jF=^)sK{7u$P;vu#d~x<u_c=t%cs
zsJ@}czAEJ_)p<_Cd^nj2@H|*rsERANj^g(~)Q$=Qt5XU&(-J?YHk-(TG7ISS1T`tl
zPmMsLi2FL+`FSS;r_V0Wm0{q)oaYA|H&IQp7hHh$X0AiDOos^;aUCw{E_R?zy`>$K
z;J#vzR_UQZ=H-Cj-d#8@07j20F#t@JfLRmmaU$xW5c!ZG0fnH;og{m7gN8n8#KHAI
z_q2muwVCqRA=bo-YP5Bjq!Gx^%t!;gO6_qR`K_Fl`?-G1RSroOp@YSQLtZcYJqe;f
z7=lztI%LSdfp=%LJhRuuv*{j2*Z_$ZtTO+cY$z|gKv6KoS+KWuXQam{(PapTTF`Im
zw2B{PLw|su)cM0C<4#W7t5lpaugzJldz<5uUaV7I1S0dv&P+Fcona0)-}t1cV=n=-
zYBTinwO&SZv0%g0ARce&{Hm2*jMtR}EirPgO#TuSjO&%)hmsb|Kcma)9nT`}hN;&9
zobNnt=7<I<E`*lng5{}_f(zEn%U#|;`Dw_iRP51N)wB}#)$H(|xDIWvS1qZqTp&pr
za>R(D+ILRGY)6luj#)8)-puW&j9HFEy)ck<Jo1r@5V<v50iUUM=OP;>y~&#XOfCB#
z#sJ(lNyu6x6>2&rnt|9n9JUv7FYs(J>1f$rF<=}nsj7#Ud5^=6q`pnd6l%qh!>@KG
zn>ct$G7^c{XjTr)$w}qO_l|3*FcxE~;in`K&E-f+R`THU?AD;m$w*wXYU^!2O5c+s
zP{Uq~y!=a9HMARcT8Rb<tNL5fs2h_nExcEjfisuw51-O1hOX`Q+qedkzCKkfZ_+30
z9g4<rJ<tCEIylfAcqh4gwdy;P^Ri$`a5+U^+`2x}s8>`NTYOx&s=CR5KkzpOzc38$
z(z-VwJGe#}Ymr?hf`)fjT<FeWC{h1n2_9fMfT04c=toiZ+vTU*Hqs2=Cc5ndChD}>
zK5k*%(pOIIlfbk9SXgLxxD=%+YUW8giFHGo%nBgB&Sj>^i1qs))xAnWZWGyH`e)XN
zc?X9Zy<i_RUEIJ&*z)Wu>Kqb2KXWu(CMd540te`fhvQ^sbU5Tt9nA28j-9iPY5fN=
zkDX$UlmSVk&X+e_F@cgN6E=D>p2YKX$wQMc?kVu*v8lWxB&tcwjj+pU*25f;<v>}@
z#w8L{v7`BQ?vdzR#qr2lPSK><NzT+^sF9-Q$&9S3z;AcjE8-BFuY9_2OrB+pN;|Eo
zSr45HY#jm>#GD(_l$pjf^y)`#Lip2h2RbbWDQEd)5zE558JHNcfq;3ex>*n}hob+U
zqD%tbIPl>x{@c81<K7k>;j8-NLjRS1_fvsQ!6z1`8jDBxSum1Z|13Mqkh)pP9aTj$
zF-z9Va8J5+!zvZ&Dmi6Qti8^=bDk?@8B;`J?+tT%$bx7%wxd{)^z|{fPEz}~In=bb
z+z3f_e*MztzX4eUdKM7_g|ogc8WP>@J=6LfmS9T{&I*Ia0>v%>&XvfBYxjV@y{g5o
zm&g;ntZpB*jv4K5yFovRE{V2jAc@>SzQVX)@PoaOzRxel((692+~hhNK`X{O!o=<!
zl&6F}%$IS(_OpKh9>(w;#tC9u58C!4G=Y4rzk2>Wu|?+sf<a?aBMcOj$PTzB^C_#K
zIl1ewbGuWUqBs8I02j|Rd`M}<{$F8shiNYUN_H$7%=6IjiUZVCFYfAr2xO2hv9lrG
z&cw9uk@0CR6XA+S)asAHNNNk;#Nm@BZHXiY1#XpS8d)%&#JwfUIO<wxEF%$Z529gI
zfYsWzb;9&c!Q&$C?^1O7)@j|js-ip-lmNl<?X?fIVy`&S(*6~(-{IdzS>XE;C}pX&
zV2&9VR>c&kD)56Dze;u<ti>nTGfocMq_vG?Ts`()u#swvsclA5q&5(*iLE{sJ8^!n
z&la*I=(Z+n|Jlr{+N1D)e^9gQJW&=GuO!m~o?n4wgN`psF6YS*o<UN$?gAl~8>ceq
z9t_ZqF>&SCig{(ihKBi6%+T(K6k1pv*pHfF*Q~ui6%OCoy!vfO3{{6H#$9BxJ}t=(
z=_v4YVlpPg2|EXrExtp3JN)WK5IKCz(k(S;m_6tscgQ>t2#VAWV`D-^_-<ILmo-R{
z{JtY_XPO+<V?5AvvWe=qpw)pvlIY2Y+-FQw@p5B%Y8xJ*FtE~br~%syVgUrBvt}Fp
z+2QLqsx!bo8-H-3xdF1+6wr}(WzaNsNJbTWYJ`w(JpLHs=U{};ARX*tfR<B=cF`;o
zdUkeHg9OV$AUa)fWgsuW^5@@f;>x*?YtTNlsxHD!z(@ZoqnHouE@#Uru=yXrminZ)
zTxHeUBSCmXu%RV5*2~!;!6@@qa%HAy%Yk#XKY{evf#`(JwB28*aXUF!!%F$)v|u)5
z4m)Cyu8Z<yF(AM>+8BkF@a`DHt><Hl9!KN(j#z4pdLI%&$~2PT5pB(R-8up@4xA?s
z$tgnBa)@AN*G*uH%p5bd=JLV~)@a!-jKfimZyaAa<CA-Ke+0b>;q4vQsAda7p$}nN
zdl$t|Sgy>G2M+J~zN!@mUDw=76-_)yd^~x7w<NEPda|!QrMIZ{r=f?YC80hOUWg3~
zdeHj^&Na)RjTnt|#yc=b9LXK%5a?~dI;7zHgYUtTuIhc8#pUg_#Iw+nm3AMb+`1iE
z-Wlj@bqSvDuWbI?3Cl%r8Y4?DY#mpehT(KRk*2*I5rUOP(v+VDOz7$`du_DKsfK5d
zfI=Y5*Y`j#IPHV!04#NtnUT#Zyre-)veDvo)y|*KDJD6nJ$D@}elXtRP%=v>y>$C#
zoXmqaO8Js;x3C2Hoa?*_b+G@{0GrfiV@=o__FAe9X0H<l4sxjPGkg2>i-`P*mei*O
z!l9LgaBg!s8iwvj;xxrS3#|y;?sC%y|35fJJCq&8J_Q4jeF(L2%YT>FyOMgHbM`&q
z5qC10rbVC8$<ilCXr)@J+VCw2&c)-_j(1q&V4fi&Q&b^>VYxEN%~^OL-paJ?1f3;f
z1Lq)s?Lo^g-dN$f&wJ8#cx4N*{hV0Sh@}3#SCyVH0J~a~n;FB#Y2=}ATN6%lR%M*~
z!wSl@h~f%BupA|6({V}++b|1zLSML5mtZ?1Ga&?5^ZP-JEiQmXs)u6i4&Rol;Na{*
z$&&Ij&rAHg=KkP9lw_{HY*D=45DVMsVkFU-$?!bBVE%|Fr+Flx?MK4w*4yP;sH!QJ
zOQQ*vD_l0<==>#UZ0)ftNio>eGEGaFp=D{71<6NzNbhB5Q-sLmkKw3H2@ko10z~Zs
z9^ajyrH%$EB3K`B*Kl9G)ch0^;u=X<%6>)M@UwGL?u*XRnsgMb<C>kl`0&N7g_KAA
z9^ni`N2;Pxgi)-or|oO5f3mbB3yJp4G6iYG?cZM%lmjaFb3rCx)!}-?A|18_kTxZ+
ShT}yI<KaPrec4DL`tWiHh5H)-

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v
new file mode 100644
index 0000000000000000000000000000000000000000..43ec3282bc936b8d990a5a9166722376f76e342c
GIT binary patch
literal 12240
zcmV;>FE7xG6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzMM%+<)KjuCu6a3t`J%3`<S1fjtk
zt=9}wNQ@AFsJp&odfO2Plk`}jDH%0>k#wqVP!y_t@Bm_ka=HE*2}CZNWcU{~x}Ucc
zn}fzMJQ~sLXRed(w~Z34>6B+&2bWBaRvcfSJGyo&(!J}{x5@HasC}gT7wt9JgohB{
zM%{T0u0Lup`1MoQ`(&;>?UE{#=SvB<4*ZMC+6E$Sg-&mahDu8}G&h9f{FOr@2u%f9
zANBAOY-|8)dV~)Mqp*HWZN+*|(eq5Z-75InXeUmWio1-LKcAp<_V1ZAWevVP|MR9d
zR;v5;*!UFxL{pL?$stj(Pw?E4zDFgiSVOj=n$?9%A&!c1^XX*6H&_Pf+B?mO5{*$J
zwrF&9ny%D`qS(~rz5D{?zm-;tOA)CL7!K&H)gNtc@ZAm*kie?Wl|YV8rhKYnotD~3
z55Sc?(yLM1b4*j!RcClWycsF=PGi?=9+j$p)<tu#w}%blS=7e9me!x7LR<4T122WL
zIe|vxlGO>P=?YGUST5mK4A7xAjE#e3^N7;2R?Vkg_HAkSd42aM?$?#p#zF}oA7$Dg
z0FvyJHdpYNM27-*nfBC%)%`*0Mc>u$z|aDwJS4}+cFXYOv>M^83T$`R&WU7#=oQh8
zx`3v*U{lf7ivc!;WlhPM_u1VvYYHKCa{s_ePPv~!O~OOH1~l0+Z7vWjUu{?@y^D1}
zLRq2JZDCl^i-i0vC|UZ3Zu8bxLj0r?3!d0vH8+pXcVDHld~*ZV`*Tdc`$n3C)GEE;
zGNIpd0Af1B<|lDe`CK*(Ge0<E$ZW_d;le=fnFwYEoWzlzC4ab(pDj1!{?4mI0DVpe
ze~eTK5wq+5o;<BY4^`VQ>dOn;+`;mCy^dYig3F|GcJ7+Wqe4-6efwx~z))rQ`Wuu?
z_l3K#x8J&+I{_dYc9vdJ!`9=!eP1)1U4l!03b-`m9ly6vl@3kSx+^(5@fYy^tw1|-
zNPHBrtJ9AiD0&;!Ud4<z%FpJoJQ@EG0rgjh2T4oPOPXRXNMPRx?1uOj#L6r80!M|_
zZIYZYhv~`taZ#mC<T3+(zft$$VeKS?J(0j4`OB;&bcp%=!76#vT6#&3JpDc?+t!=W
z2_Kl)zI!sgok>%X$5r|wn;;kj2T`t1)!IKb95>Hj%g2R9Bv-x!%>mPJHivq!1-S86
zNOdS(MUE@fP-B*oYVR2@Ro5x%>0iwHo1hNu@fw$Zr223y;+H$Bc@J%KH;oO^?WfWS
z|G3$>XT#I;LVzKwOc-Py^Fs$Tla=)D0_WQwfJOl|>6VM==r~Nbivl+x<{^SB^l{G;
z(_B)p;>3_qrAq72NbCP%((7TIwr@=sHm>BeIAI(QsWB+%;8S7CNlT)r0~>w!7%jJ4
zC-W6~k|GEWm~$8=yeOTPR9F8dmcKUjb(S9ULjLvjF-aY=6oVT<@qm^)iuJ)ZWz6xY
zQGrLz&GwSI!5@OkE`qvwsSuW4%?L3?ClI7(x2E^Hpz0G<yH<VlDzMvzMyE-lRUG)$
zNzVc14l<KA-gv=(Ws$S>IvopImh0cy=yjpS6^AZ{L|?#@g|18V87m~Z84aorTL35B
zG@u?1Z@lcTSRp+}&o2i&@YDDsy?<LW#p?yZgrrac)z|X3Eh@s~IN@=aZ9eXn2Ctzy
z#3N-&Rje>kJyobbx2BNO;f={ta5k*kC@3cYLVCZRhmQ~Wuu-qk6n!CXWHC<EAtj7t
zZ>Rg$W6r3^c6^1^ZWi1NZc+qO2Obp=SG+i2B!3+}=+G*Tk$O(q<`6K}qW+w+UMnSV
z<H0$whr@=XV*#d7dSz_Y@CnM#=K^gv>)FIMGn4pr*b4^9*^hI66>^mMuw;vJRsjgb
z3eGj9921Bv)I#M6%iw9WuAl)W{~A-?wQPo_YtvwXKz1;8KJXZSnn=5h5;8{%cN<8=
z&58tPbfzEQ({N}WDisbKp#;JOPr{&GvkGa<!I=RMwd=16KDG)D9|89IuRgraWoT|f
zXWvN!ri18D;w=uPub^H0!nmRh`@b90YxMmvF6HK?b}ngt^{3@fWF&}y`{L`PfjWT0
ztvI8tKu8NPg(yO;q&=chybWaZ1^aM*YLi>rjUH~=1w^S#)0y+OUSy`W04XK?KZ|WH
zj@@A&X|__5=psh5k^_OXdEQjFtb$?Eg;HOE5>tf@xTL7<v!zDG>qHmPOdr)HQOA_I
zOJ0nac}~BJ&+2JRA@m<<l41Qum!2jXfVdv@sO@=0E}u5E$>GZB!n*55F9Mqear>EH
z-zs98^Y)$U7@e3q0mpxP%IX>}$3v!u%xKU3oypXFJj%tXErz&JbgTNg!C{`gyk4$M
z#reQ(?tFUwk9rMONvHy|$L!%x62B}<tgU$Zt>(<RWb*w=3LALk*_kPtjN(H|J5AkS
zjlt#a?n^e2E5dBa6?O~yt5!^KsU|p#tpa3|_ApG%I;Q)&2PnWVTQVzrd%Ud`-QAol
z$r|9(%+`b}7>fCwgq1BUcz>rtjP-;jM*oV%8cZYg+`f_TMJQcvz(33jH5cO@ti&A}
zN3ZaD?!BDc^20ILd3JTC=qzi3TtAfvKnTDHUPYdqsc7bbv|<zYIq90TPpnqMgyjJm
zE^KX=T-+Bb8194I{-Ll^#oY!wg26Qil)gNVDbjreh!YQWr%UHMk`g#ULgVYu)XT3`
z>g#~B82p`0^>mpL)R`NE8Rcsch;S*ncv01Qg<w=quw_x2$0#wi=wb-6VM<pJQ0e4O
zg@Y_2@sCY+wa;|XwHc42Z$&d`F}ob-FZ+y>xR1Em$A_kyKD`9L6~XVMe^U<gEE&0&
z!ha??3n4+7Fjfx8X-C`2F%%PSDI>iQ7(}Z_!<DW$T~<{|gUE%BHQqrc8il?qt6VVN
zhR&W)5?A#j*-bYW`4oBo2<H{LrJ2LpZzZba!7qM*S&)a%af2QmjXPea#dgWsP^#<T
zPrRf0+1JiQcier36Do!ZyXw-i?db1Wbj}LY!*gT%2|2yU>eWd!UK6C74dz-tC?yWO
zlML=2by0y$dt&tU!?<&ELFV+_Wz4DIo@NM(6G6Rrei|4R%V25$$TjT=yB5ytvLidp
z<<n_|B`eY!cfE!(f_n$hf45c9VxFfMveizk$q>+QH@~9T4AEIFB^=%x`#v9Qo*vw|
z+=^nq6=%mJq$<`x+mL)rKm9DMs5O73=gpsS2zhH7m|WegrWT11y4UCxRznOCkEMzU
zm*gyPKl=bvjVSzhy&Ta)(0?|C4kn~KVmmBdkc8G(m1^DtBtOy;#&f9gOvr$jo@Hq7
zFwQ<Xvn*Uk{$RGax8e-eknS&evCwMK85+RLfz!<3>mc3zdnWP>u!Odl$VCgSE0}&?
zeMLlJbO}zGGTwM8-7_qr7*U-$b8PN+O4UXr_RpwHtiDXQ<A+>iqa9Z#@&&xB@r?eA
zHgkPnpmP=BVx^oL>MhQJ_+^o{nwj9dJK(LG=Vckh)esbb;{gHrXCMZ3$K73hdzw$4
z)(UFxmJL{hFDXHLVHry@A^>R|sgl|fG&(%t)$XO1K#iytr>QSE<d4XTy0F1{;}zF4
zh^qiv<K^>&Hs_cY>t|pLluZn`Xy|LetdDVL(Pwr4K!8%whQ7{%dwf@kL)%X)-_v+#
zyp|KnySe-zTJ%!pkXOHy6bLkqw3@G=?+yLANFkD$yG?T*5;rfDgnGk8*pzj%UB9%s
z8-P>MyIx=-2|S}Qt(XI=fsleI6m<{^3UnEj=Y1qY<_PHLoOg$)cUI5!FG@z}H3y5H
zpp-zdqmN(<?E!ZToGR5^P7rN>e*q7nL)-Vniu3ltV=ugBeM4lDs(7v0Rmu5Lm!}t$
z<rGGpt#N98B=Y)bqs%oqQv?nCokm;hk79KptKaP1B~4H`lCQwg#A9+LUopHj_rwhr
zfL>C_@7Hmqu9ekAdCte+-AdOhDI=%I6S5O#KZ~QJcG1+BOg;LfF)RD2%PX@^$SVMu
zsoZ$V1y}?nq#VwrG;xjvZeHOhW1)3T9w3zBLY*N5@4B<$$gICo=pnshXO2*|JPV+D
zY{5ruI;i=QxKu#|FFT%fP2|nFj|k=PD#Comzy6`>{4%2dr1081jp_*oRcCB8NV&E6
zkd4x+a>Bs3mnV?sQ=GGhAl4DpFW!1cpXu*)HM)=*fXQh=#qr>KTPcsEExtU>O^Vwp
zI%IU#6d()|<;JBcy~Yj)oKoEta{c>pPh;LFB8Bp`lV@1?6PLxs4D(isQK>OZtq1%~
z2Wh9wxE?RjafM#8^(eQ7WG?pBqq^UVqtZXQG-5a}&e<uXP|gw)!wNMAkBPP%jr8&N
zag@q(v#{QHt)&jX-m+W{*L-TM=s>y7M8+u?q@@;3J`;<oXntv}a+qWBg=Ubm#qz@8
zQ^K+F-F4KMIt0KUzhHiRDA`V|gYU9zL_{?jNT8iYFQm$ACRtvmpzB&}6163uG#Q8K
zafwi0<wH-oH}w!%7ve=<9pL;H`YX9_?<XidW@qP{r5+=?3v>}_@1s^P!?;HmcqKct
z%k120&g+Pbx@C(Qu2(phM%wdokusB9;)Ym-fSN$V!`~eX^aO*@mAG~(=UZ(C8k_9i
z2O&M%k*(;WN0yg6y!~lM?7|=ncQp2(x=RFG7HK6z`39LB%;DIEB_3n6#?MgL2Mp}1
zGaB%YaYUzV3_Z;TDqy|rmr`<FVCCcKoQbFL?#nnYcpQ=4m)D<LLnY5tdhECeZNE0*
zIpYbPUo~v7(#bbP+5doRGYxAnlLa7C4fo*ql%y^=Fw$B^3laOcd}d1XUEdWPC5P~x
zGhko{DWaQ{1a9x;JVLT(dTbp42KnAd*4Hkz2w0ALOaIJMaiXq09KqfwRAtoE5%~{r
zB)F@8p^n1kss8l-ZK^LRA=ig+lQ^EVOrHrMVz}bBc9o_C|6jbv#SVkx+N^aX%8Ftv
zK2(YXJ>ZJU;7yp7tiEvu-nX+-J~$)Mnm~u2j>1YN7q1i}_z6KZvN7|J6%q~H$oh@v
zlfZ!IVv-~Mpj6HE4MFoshTSzy^_G?#%uYEp5;T|Dcc;sv41O^Bi8!4V*j#5JF%Ohp
zlf<{f_r&LuOjL7GqS}R&5*P&~w>_XBuylER8<fe2gdpJ4?f-ee;~%LicDRGcIwIGB
zB46{32yH-&6#g=FCSPYAwmv|IL6+!C5?*t$r5Aw*D>Ub)m)#V?8I=a*+Rev?R22$o
z;I^M3<$o%V{2hFh4H4dd|LNGqNZ54YN#*oh@URt1@^qTY(Nlb;ImsL^H_4zOc}{ZL
z-5%<QQRK~Sx|)UKZ#i7&;0r&{T%qYNGoub4M5947f@S^yCg}cq5*AilP-IY)dl@L2
z=(?Rws8{^1`yrpAe`fa>k`haut2Sxm)aP=_Rs-gWILB>us`{HIDSkP^*EI?u{cNVO
zJT-?i>;*qjna_Rr%OmFUS1lV5oJCt&lyi%Q(EoDvV_e8T<gV2acjbll1#ludF;Czg
zBcQD%oz7M#*Yu8`Bcv2b9l<x0J(o-91l&A_-ZA%1w(rnjKN3yV_kYA1XcHt!7v39|
zPXUjMD+OqGfPoR0FL|Kzy%FrlT0GX_bCQ=i=&nFkD`c6xsH+>aQ9Jv<%+B=7ARxx?
ziel$)J8cBUN+7_7))2iJ4Z)Hc5;J@~+$y2n$V)lJ?h3l3h<A_ex&vC4f!71rdXt3$
zV37i9HfjpXx$i#gW`eY-!EXDkUj9a)1fc@i;V}vfysw9w;-~aV`wmKTde(#bc?kf_
z_wWlhk}LS^xV#PjXnh+=V_R!(g~F_L+6YCd4V}xp=g7~TA#E|`bcEX3GGFjm5m12J
ztch&_$sP0VELmczh}P<->I<KVA~vs8-kmMnFJh}5h+({Q#ubmR<t&>2NsQqJ)d;xy
zg+_bf1K-8bg$OZlFvxy<8jIH`UB|%d|19?;4r93T_(g1!@@?BhZL6m{8Hulsc9|q1
zzxm#4IoB810PPp6%+V)DX&C-5(7?uA%IBZz)c!vaw!5o=QfoS65M24|IpShWEI#i8
zs!DzqM(yxG^(8-h6ylxU;=45g7G536_QlD6bdrbMLnQpOkaD7A)frN0mEG@8bAC;>
z@INa1gCc^_SJA4Ah>{sW<Q2B)15?ycz@AN`1iR(%F6zbLY$-bVwaAdz>qQ|@TvV;s
z$DPaV9|WR}aAOekY8$f0lQu{^2H8)(4OR*ZwKlMN@hv3>Cnmv|<AnfDQ3`%hEBj;Y
zcy5R%^#C;8Uaa!_O5C2=s!e;$w0IM(7K|l%RFQyoSOJHRXi77O9!e^b(q1cD;!p)Z
z0@wYf#lcoz5hq`xt<iZb;=Et7J>=EEcH|oe=(+91A*2AONxK!7+X=a52(7wh;r!{r
z%o}&1K1wR!Zhi5esyZpxwL;k-)drfb0YNub6&##+l~d4iTaK(c7k}mTQ23<Tpr9iP
zdCGKP-soX6BUs_kaY8Jv8i3Iy=ek7K*IpzBwP_0CbcIgHbK&*EN*eaI$2C@g4IRq*
zZQ7~;WGdZk-MCPZAn7q4zi^yt*G?nC#OW7}kSA8T<_znbP%N1HT1&Fzapx0MfRL1J
zT{|C<VNP*mw;o^^7F;di2gEd)_gh+BN+HHswe5c@?L)-%z#QMgp%3LC`N`32Y^ymd
zZ+Kq9>0q@!ej1Z@43)}c6Jhmk%Y@LajDdeOsKG26k(A-|bDb6Eo!zqtDSwZA9|QLj
zd{BXJed1vd-{g$Vv;-*2ahu0U{c3si(G=`2Yt1JSlyj<bLLPp)ic~^X8nI&=U}j-X
zlg~wA1@BwykE<Wo(Ayx8iy15O?<gzeuxlApd&Ab!vhachG$5q+hsP-i7_&?zFA^$t
zh#XPOBzC(GX%+}T>>`TzOppWVJVnz#9C{e0Ij22lQ5H3o!3F7!x9nVhXz7Svpb%^*
zafN>q^XzYSM1UmUFJiSZM%GzCeLTrRcgP2Nh!NcTN2e}HQQpy>DcLka_E%HP18l$V
zG00n@*S#9%)BG&;orO8XH9FUrWb$S^LScI3)BDF}D?D@?x0su}opC}SVo+(sV|zR>
zU2*hm!UdnEy_y6n?WYf5gFV`(l5TcPd3w78Vuc1OeObN~J5FI5h@K7U>ppu#nSC(l
z!&aMvdNT{v@#*zZHq9i~1qz^5aQ<M4SV&mP!~Bc*fUqhdzAEv)0sNVvwhrLo(kaF+
zBg2vU^_UxkNKQwNG-G&$3#SoGV-TPQ+zZ?ImB^wUtrViM>gly8tqHgM3-Ab|^Cwu6
z*^y-q>IF3qlZ-*&653`<aoR6vaGLJ>rBxW&2Lg_qUai0d9)&A%d(=|CaWcEf9A`XZ
zM&oY|xu8Rc=&dN!IMF_4Kw)#XW!RoTih4p+M8f*~?j^FOW>ktl-`ow<psJ6nw7;3J
zmzk4WS!=KMHNh+&D!w3u-I@LVPk*hG-BrSrJ|<U52oX4$>(ZE&bF1L+&azm18k?Yh
zh5b2bxt_@{=Td4bh$lf9-MzehGk_4O!v^(CgvWDOl<`AEosPo6d>GJI2jjU&?y!Dj
z5CHCExpx31*iB}k(<`OM2`?uC51JdywE=yzG)snc46aB{NgL<nMDqH<BVc8o&~d^q
zG?zJzF<-j%Le3Ba?51>t=+NJ0KAUPn)v}iveqbA5v#as^B3WM_c8rLe()?E@jYPu*
z3H4AP71oSjRKj)s@<mi+02A8^o?Om5j5NgapB}lY=@5fPO49^lfYLl@`mra8iqj?6
zr+2$&9G`|e95f-NMEP?UQx&1TRg5V-!?Uz#`ry}ZpVZZI@Mcy!LO~?Sb`+Qz&f|HA
zy~s%27P$SzOZxFj*R)xJ8D)XxyUZCs3B~vKmow9s5YBNWvLfZnG8^>N55F{O@mG#u
z$2V_=w#z;H?S*NDREIHppzRUw&=$~LKiG)Ketl0p+|WIZSIB_re`2UuOaQ+AU6KXG
zV7VDYj4Fk??cp%%4MntoD~4RPD&A(0K2Zl-eC|}(R7`Iy!C{ZFTGqW&Ji(#5jllHP
zzDi7JU|f8QY__3R9;lC9cZVFU0fd)<=EfpYy1E{m>jEkSN0;qRA_QTkoKnsFAS#?a
za~{p5a)D+E-i0GAmos}PnWqxsD@W#5z8*3ar{Vq}8&>tO*`5l>a|JtWn-_YxFCrGR
z<u-^xdc0MVJ*YjCtd3RQ@VuMNkZ~}VO)*n5M=Uj!Cy439w#Wt>3b2KvsUy<8|8)=$
zs3tPA8s(U!h6ks7oMG{VK}(?f;n}m{n}x&@-pKrVv?T!F`CfyCOIN6ZD+x|epCGHA
z5?hCl^~;DMh!h+MMHlF19Q!kN_<x?H&9FknZ)trss;vP(0#}ii*K{e?UT8|1%eqoh
z{i7J&1Xstuef!(wX=RrFXJAQ^$B)bN?F~)Y@&nIc3$@GTovXi-qufeQOZJev#{leA
zy4k9yFAnov$5RML2?xn`n_IcaUSN3Xjq#bC&jd`hNu(}+1WOE!h+Z@pa}^Ra-o)Lb
zd*e14s;k5W)99u>irHgpc52f>slRw$+Cf8<43#i<*A<V(faR4=ZB*5p<8!!#=Yzri
z$@+?Y?VFPM^54Ch!41gy!1!5Z4k^AcrU>1vc4h&OL9%2(<V8*CnitVl(D!IEBlQzv
zyO3xL?XSfH?W|aC_LDtJdU#5sOC`b(u_KaV8Xw$Bl{P6`jm9PSfyC{7M9ntQd%OH*
zrE4FC4?}(u6s{YoZI85S5^^~0dl6=kUKlyoMx$Y~=7Ke&3!{UKF}PJgQw<U=R!vg#
zQWvIn<+GL6(N#W|!GVV~y*{ViZz*tffDUw_H(klVf(t6CNs5)LZQZRRK@dgB0Y*Tq
zrrNCwk~Ygv4-UsM5^QsOaBn8kUwj^queelXYQhgrCbpmitJ)!~yvagf=}A$N^<=m*
zu!SmkoF>m|gO=P$IrE9%H9>I=eapqId;1%(z=Gop14soo%#4>GIoMA746R&|;RhuH
z-T~__dxR7<0=27?*H#uae&~LyF^Goe&&t?7y81|l1*Pw1&Ocui@K5buqD+Jf<pwE!
zX^+8#7g=v6krpAsx8>crkZ<#ba!fE~0iIBv8UM^Ii+xhF5R-?Q^W&&hi$CrSZq`O7
zk^4gzGL;v@S<8+qnE+B@o5s5(JvC3u<f~&N>_hZoRNf-)xi;j<|IzArZ&X52dmRzg
zfDrd|2dCM8t9Fv7T?gR*MU#o*&^R3{(-v;B&5z<;Z9)l^X%ivA-Qd^O8#>T$+*ig`
z**FtW7AH<4_|ZV|5h0f!)ltiq!`FSMHqo`|o@pn_+h>MhSg@c0+?Q{MW+Tfc-BQjS
zNxcfP+V%-RCeSp8*tcOjy9a_+US$!HB{R=T0)+cCSY^Wq9>&v()z(}>gCY^Y5dJ%!
zxL?M@q-=W$K?TOVnQE<DuC&@+yH|Ai?lyGf`e4=Uknzu4){mMRc&#oprMg+$N-(di
z@PZOR3`q!b2jhl}p*0qj!Lf>844R)u^P=2fH#4HCtYyiJHXlN<H0!>Yui##0mQ-IS
zv8zPHS0i?`0>4t6!;lYZ*AbtB(Dqo}kSA<}t#B6`au>cd(hpLnmJkis<5eDkV12li
z>+BdQZkw}p__Nuh$`KIbSoMdV;KI$}oavU9hvrT3`DQ`m&BXpvOz$>`ANd0c&9r_S
zUrt($`#l*>LF=u~ShU&4bFsg@9}fZTT5U^{X3tGvG&%{8>$sIMln4LW9uzJqZP0A}
z*tyb5u@MKIB)4CmCofGEiJob_J(6}67U7fBf^iOXhL961=m5%Ozj1Tb%bZ22**)_F
zx(uB$vMxXcdiWSEy?EKxTFn(2Sj9}(BuzzXmwdOYXZ1;Z{F&040(KcYLqlM~X$C_T
z&pI`22C1>ejJkdwm=TH46L#`_H(sd<B0UK-*H+r{$!%sDtvV~+REv$N*-;^4)H-D#
z5$zkLrR**u>eqe$j!K5a?vu6sHPmT-7&k!`W|^meyJ3wa4c=kU1>$-Z&Jms08SMZs
z85TF?Y~xsFzG)^Aoy0=DNGzmI2V;G6Gj5^8tiJRkVl{wfvF(0`b7M$&wr-Nza^%p;
z;gF@3NNC{&CCqEfzv{rD=aI)7pC()s3XP^XpX{0~h)jQIO`Fgm-%?HN=Zd4Dw1RCr
zXHGW#D1CdWF6mMhSv;ZId>+6~Zl19uiAm}QyD%D-J-A4LmKdc>^H2TzF&%^24pizc
zB#yz2-W(K1sVc&+aYqiXL`F;gn{WDSkW%+1QgQRzy*V)Nh4=EVvd_<~jW9e$N&f)S
zcHH&}`0wI;5Ss*dnvI2u`FHcoP}q$0U1<m93grepfDUEN`kqi3Xl<fkmX8)ALXLpN
zcfu>5p=wlhad-B|?!=W*>|L5^J*ybbU%ogp%gwlkQ`9@2QOEb@5*S}IxwBYpq8dwZ
zFq~#Uzt@eWMA_Ve+?<VKCnG3e#FHzp52o*FS*2Y4Ou%M>daWLV%b3-Jwp&oC%=Hxk
zJXe<r){RB@$wYl97PI9q6&^f)Su%q2J19Cg;s?k(&m}>m5j`D0-1tB=HXA$Nfc?@r
zxowrOvtvEI1@AeqM|N_&=@Qf3>6jSpj6`6kN26foUP=;&QgmINSyMN&pc4U@ihz%&
z^_@j<?bFGh{bo*aDsOY8lUO`*%?^d)>V*8lM7o^{W`&qJ?iLkCwf(3|F=iB|0$jq2
z4N_S2p6`m@POl~=mA)7cbvPTmeyu6AnXQhw_goRu`&QU(GFBoj>l*ewwJP{r>dSVj
z!{h&YL{lXrsZ75XlYt+A8;2&0ODakj)^=%2nMfUuiwIwfM%9cyTEA3*jv8|!3HBo;
zpESHSh~qS=5j(G)@8R}e;3NZDdE*ugpG<6bL$-~DwJHIWc=qNBPI~bhx*XTE0bhwV
z357D<+k9C!RgJ-?67co{5Uayvnzro>?E_bX)3ogP2J!MO>p|8`EE<UKZ`)>{&8!eH
zv=Ds~#&wCiU3&2e`=a;btr#T+@~e#BrD4A{F;81hd{{nb7tqloosD9&kQs&O_NBlM
z5Ll-uOk<S6EG}|QjOAjelko6)PhDYeAj#4&BTTy*iu$>!d-n#FCTw|T|A6&b%to<4
zjJ!!ZhsX8XqdC5WDcj#-{(;hekc_t*%oam;KTPKIRE63mL;97wDf1e7tIvq2PRAK6
z-a&-A8~wXg9n#pBs=l@q^9qK>DmU%p_;G888rzDAI*rlj+0YNVL$KL)0_i1C1>h6T
z)~6x8szA>$B|Lw>IL*EaaPE9d(*$PE5NLh#vSqJhFW6IDO-Q<21*8^mhsxk0nLQaj
zOqC}nW%bn)H_C&xPlncALb2Ke0Zis%kQg>VWTJVlm1zPF3|U_&d2@^6c-2NEW8Oi?
z9y3}AH?PnB`3<59HRscd(3ZeK?#(Uv>o5`dwXDY=#G3HoUYFnhZ&hG8;ER$?esGiU
zTk4YS+5VKDJJfvi0cHj(9<MDC$5bS^O&u|e#wq3}#BW-z^(QaImNMn`lf=&njUz7Y
z2YXCBC-#aF)8n@go6}xUX9!&0>c+B#FeGLmt^D!><alC<GTkv}SL$O8P%UT^@ZHVz
znm}xJ!rD2~pzL-XJTyO5awf8L4lNtlMyiuv3~r+?9UCc?a$!5AG&GN@Yy96f=>OhX
zM88K#YV<)yEwEWv{U(7Sq0WvKCVmKywf?7mox1&vqBkiK_2VBjT0(2gv{gDWG<6yg
zS3X0KA*K-J+J>v-b<Rabr!0glec{R6dLbtxk=J0x-OFTXaD$K{452xsFqM>takZ0A
zg|rvQqQ)bBw+JL0CfROimTvs6kSSYC%*=Ik!Xrtw)7BLH#zuPqLq>*Ow!gf7$^ufD
z>*Wn3$U!ZV9L=~)qepyt?=%U<_>D4h<&MUl6z*@}u-+cbq%p}W5A^U^<sP4an3YZF
z-bO2@Lo3JkqU6YKsLtb)zM?Ufv2uaBs{kH3f6WXCt=`gG#p|F?Wx|M<<p7Zo94XJ=
z;r@vtoD@mw(s1z6#`*NEgsfqijqXx3OcMeIEsg~{)ra|E5kPA5{&%6YEY2}gN;j5g
z-iahstdt1Mk32t$DHL4+7^cM9RgBrAb0MDd@ww0|OpL1`^2A=xGwfZdBEP8Md>@cb
z@mkN491p!4SJyx5a(UfZf!Ch9jx9)c@<h2$z07u;JGB$2hu+cpfGb)RZu85nv+DCp
z)*M=)%r-?FnqH6&nFu@?RIC7=qk!{}C$S}DhTH#sP!nwAaGCy&O>2NmBDZEvsquUh
z|1RbhU4j7>drns_LXJl?3oxJoVkMujVm2uTC&xa4%e&5wduEtmJ?#N4#$&y0bOf#}
zLeJ+kisk4<$0<=ak={jHf`mnbZ`A-w>Ow(u?WyNSX!Pv3ygCY67jbBiib=GrpTk%j
zuN;e7p$*IOoSrj>sAKAKFmEj1v2D*pD+a;^ZY<B*U(|<35VRou>pyzk^LF^wVji}r
z&1l)Rc<!KDMI4$`R471GYP=3Vz6;8i##KfyYt=&md*{h%Pr@&rgRpcJQ$SLQLv~z4
zTw%%F%ytc@g&e|Gq{jh;OaFJ{<ZKs)QAALY;bcv0H@>S-F<XxC@V!2Y$oDNQd2_!C
zsRE5H03-LZ*`RHtlJ#^OSx@5%L?%S&DMnAx!y~2*RfgvIk?|j}K%^8D#`c2=Aa7J-
zsH$EjQ0ilQu2MbndqyOH^J%R>T7?Xx{u`57aJ<N0&^2>j!#O2rdhOb(b$bSZqaAbz
zRRF6??w&KQ!Pxx?3VFBMQnUy!#+r|;)jCo4KiDei@b`dr;F%EnKO=IORJ%C7Xr=PS
zU`ZI=?sa0@p?9idqiw0VJ|SfSWMXcMI<NP8UbKKWf9O}}wrqTD>@u#El0wSE07iyR
zBedCBYpdKf{D9=(j_^s?rVVsZdMVerp`5r%-*$9-9Uys4QE}@H#|ieuh%qt$8DS_D
zhpCdN$!#|Kbd@y0S{R+(?XcK`vdwa<CJH>3Tu7K!=GP04*2P0(N985V(<wC4%Re00
zTG<V6O{dh#aN@84NDRA3QV$ODgJ@)&l>2@-Gj*}N@>yQeDP+jT(PoTS>Yh4lb-$2=
zav{Th!HTj2-83Z^*KaS*;##Jxu)2YM-Lf~81ns<fK4w6H4*|EJQ?^#6e*AkcpR~6i
zV4LVNV~GwH77v;#_hDyREG<(vi2|F3B!*Q!Q+Z99VQ4Ij5Q@?EqIx5_i{Pz5l8ys#
z_4<W00W(GSK<>FQo;q&b3Uvm;R>v2~A+d8`z<{lt7EkX*kxY~8q+{~HrJ5ET761*_
z$H5n8b-1B33btqDf>o?3+MXw(7HZr~Y4X8yw5;M7S?%vo){E(5d+r+XsUPhG1~uO^
zPn^}T#TGAvnGDkknW6rnMqP^Qds7dAy|Vgm^}>6}Jp4rMEi`_G`KoHsEVS!I5D8q_
zk06cAI!W!Z%(M3VE1NM}Wvd6LQ^{GB>Fc^8G4aG~8o2zXAdhYdiuSVkW9{Y9m^}F+
z8Y1^c#Y9p#ZvB@uW9ZAB&<y6T4TRizX>m4*9uQpS%hOT}4)~V%A|`Uo8Nz$F13jS|
z%jS1ncorBtkYb{-r_ZI<c^;sK((hOhNLPBc1Nfn{ZUFE&s23~)p1Nm)L*bU2I&;4U
ztmp)TqtKPNvi8dE5>VL;F%Iq#Z@fx$hRP@a?%1F~;AXu#PwAlF(z~%TA*+KHIE$Tx
z(eI!t!xVEZgx9K%G*(M56FYQsU5>a@l!Gi91Pp384W5!%&vLn#4FtdmymzC2Z2+uD
zt(Kf=-;<}o?_+G2Yv@pzIE4t?UYn8OuXXdW;xCX4DA7RZvJTed!L=86&}dfJsNgDD
z#-Hr9<g=>1a0iUAsD{%@;uR#<S}kyAm%p`McGKltP<*&>2=6>@*ofI8a`R}=%X7x@
z_}(S5Ntt=Oh}(RGoU3^*m>LbbIbbQ$k#i_w-t|`h9igHWu;uZEUuhio)R>vR$bjc=
z^f;>%0L=c;F0>g*mXD(`f7p0rJp=o&mFEh^k>61SKvri(kHcp@1OkCJ2_YbW91c+)
zP0;iLjIAw@8fDF!!oSC^No<EXF;{g-e-pq!k8Fu_Mj%Uc>b*c-iheQzP7E#CJ!T{@
zUC3e77{0AXKxGMtrH(Badg=#!Sagr{le!ozIA4e9w1byq)%BWsA)+oxXCU{0fL{XN
zN6ULDH5j|?Ya%LrU*k<N8Jlcz=UdoW9^*K*)<pVexngWKqVe>5KCTI@SDUG)dL{kh
zy&9$ut5mq>GfwNtp)*zlKdf<WY}s25=%Sw3O{v%6ThZ;XWZ+Q$`~DD!c!11tH|`1x
zXwrvT?#>KO0lx>zsp9%?Zt)@CwP4i1S&*0KcRVj5^Z@k*S|r|Z_G{;>ft6km*MU{9
zeqw8)D#a99fsmXPyNQO<qD#P4W-mH%FwjCTb#e3!I~4`mSFEaHe1V;drbIYLNtG|8
zKjVnhkr@lf!bD_bB%F80uekuzF!J1UJV@(RI45pqv=AD)ULyFZ*AkX_z<(}X%_%Xy
eA!v69s2YVhUIxF5MQoL0ka9gpVP*u45LUJlmAse$

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v
new file mode 100644
index 0000000000000000000000000000000000000000..92c9df5e9725959c792fb20caf6051b74ca50a59
GIT binary patch
literal 8264
zcmV-OAh+L(6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzM;oepBYO2is$!5#NmXDH?Y&0mSy
z@qX*r!Ejy<H7WUkS%OmTRC-u4i`uOY{?NY-c{2{Tok6sdEkC^yxQnmR2bT)YIK|{(
zv6*FoS!6<1V|8z(yNusyzo2wSJuc1bwh*Jo84Uw0{ljpI+@o-kF(stS8{n#q|Fzup
z4lVm7Mz(*9T<D!c<48(b%~frRq5VeRQEdXjj;b<hD{2;X?oUop4S~)Kh>UyTl6<9E
zxEr(ZxT1ZBp}&-*=pMy$ALE9{5*S^R*Lw~^r(=hcIeK7uBD0I#-aK2dQiRKwD<w8M
zfA?N&B||qzFN;Hg$+9pUtrQakfcZ(;9lcxrjK@|N`q+hx$1{@VZC3f)PR?PRR8gA#
zT(y0ox?Dx-EHlF!d(v*0?4ek^2!N(6yZqUY_KZB@(Gz3v!_?wY6CN}c4sq`DV@LjG
z@pn)u5q`A@>6@fN2aGHHRb`kg@UBl;{(#!S+o5~tyI-8dXo5~<s#mxYWv^d(K;5<j
z!alsjSQnCw8Fm5@T+z`@sz#psBKmc<!e|F2U?2sPp7x=l!6(SpPEz6sZ6DBz{c;AL
z1e9|_1=1wRd%Fice{D`q+{{r8_-9RHggkf*+qf!#Q+$<?aanW)eknoYpz!*_cZaq~
znBFweDw`!VB2}#N`j<mHN<duOg3k6Cfhejh6R+Wgr#T3#-2hyQoAlwCW^9|5{1vl_
zG%X)^jQf&{EJ<+EIAc2?D^vF_-BIEkI7UehP;fB*q7L3T=xB!+$UcRE5@~BNC+M<P
z>J>Z6EjcIQws3g&so7B)^Esw3iV>x*2J6a0-#~=YnTBCU=y*|u?OCiz$hs4mw(uEX
zRW?Uz9G^3@zE2^k=+SI@I;x#6+CUe|13V9UQqkwP&5)r?<2l1)MEQC0^6~bqoq?;G
z?w+w%16Z9X2dKTfxl`PWmcW*^qaMo<g0>F}?omv6K6Ma9HAI`jGPGuw*-sldoud7q
z9Nertz-_s2>LaL$m98sYJMzkW5<mwhX!PlP3pTK85UHLeMr?S_fqc8BL^KQ45$_QC
zvtnOiR^>j%B8NOxAkW8gM6M2>Xev_Nj#};SN&a`S;b)ijN?_@+grDsQML;1HFiOs(
z65S$)_&YqHMiRU)fhewx`3XGT${X`&*psMtt+Vq=s(t4!K56Mt;d#rdA2Ro537^-e
z^x-^>94YUjr-9^I-x0%naXwYd0cuJib)*9YoRq2iuEAIE2nY_Mk4Y4H9QZoop?l@o
zviN+&R--e1EKC?9z0fS2Q)_}rs)QG|9<>{a<f!%AqX~tbg)>xPC|2GrKS6m8-+JYD
zVIa>0$73*p^%C#MxLKY}iGfIf5x)TYu~efSdKapwe8&FSw=NB~iA!A!LjK5l8>?yJ
zdF+kHzSCyTUcDOmcfxnM5)R(u(01T=jt59>DdMhQbeP`RMdw#_fcswISzx?tx01>s
z*xvQAyk3gqFhnAj?jd3ouuJZ3GugLpN9pv{e~)9nP)QM(im(F1UuC0hued*WyEdFU
z5dPl7Cm@{fd*6SSwFyf-imD(}{X%;_lD>fHkU^$^xfT=-ZiRCT9@s&@4A>xZ)<a{}
z@aog<wztF(nJb8Z*eEHX>vPl}0mB409+<V73E;1jLaJ#3seXb;TJagCL~pQyf)wzt
z1^CVWr9;g+&kU7O&I!mnekfJ`=l312th(r0xs+$;Ozq>)kP-hTcKh>tXftpthg@d?
z=crNz9MDIgdUe{G6oc+b{1?=B?ch|YASS6t$Nb`zY&N{CYczn&E(`rnjJuU$8U?t^
zJU`ToePcbBM@B6`;n~z&ySx0jFD8+jx#t1gn>YA7etKWP(Uyapj!)ra++4JV`=6eW
zGQ*(Ddh=o*{%18KddVPnVaud(-@jKm!&qD6G3Hos$T>7Z%u!0t1X>CPt3U-pD50<+
z)4w6d;wTAJ0;4&#>WJ{_UqX8fw5xY@+zO<3!WMP-?-<2^RyOUxEi<IJxxmwaLb(<7
zoHXw8Rh4)A#B3iWB;JlROM=jDJv_!$Y<h;81e(ahd=!-z{$oU)3ZS-wdKW_!o-zAR
z=TcL~NHlj^J}ZC~lepG2e6j&sH~%>`0`=NI?Fb;yIT*)F2`CcB&6w(G<N8dEqpD#&
z*~K3eqiiAmVdl-oK<0NU3-NuBe*lt{)eg4L_er4SHAZjB+yIf8;U(NPc+PhR>j+`U
z#yc<6a~*d#y8P=Cq`iBHOfOJQ0?lhXypa&rz5+~CdO(?dQY%KuT;@jEd#{%h$moG*
zoGdmu{zpCVol|z6n`~qT#Nb{Gv$3&bN>)X%e+Kzfi6;rE{hoBDqA$4(Ozl_>2TWy%
z2fCi}R_|$Gh~&9-xMT+C9PA)XD;bZV;Uhog>Z=Y}R;_xKwP<xY1aKju_e)y*PW_e%
zRH>JEbX&wN;kpJMdjIAu^%I9yQy738o{?=?Uh_*4(PFIO&8g1rzN^9e$~yA&Br|{n
zIbc=~f&UvM75&eMP<L_3wV)u-tWd_MBcacC=Biq<y?fPQN{+s{5)@45Iu1))-J+<%
z0v{*N7$32@aMs(mh6AK}fUv}un2I+=JITdlR>fAORQ9^@Ai}@_iDodVp)V`B-u5O-
ze{v%qzhpUSu%K>Ka*T%`VaZa-Up%f|ec|*WPo>hd$J4`GIZ<7bI&K!OS$DFwzbV41
z813z0H?ElAw)7hP`e+nDij8>`vJYwzCRs~dqBCAeX2nx~$K=aG*7cE2{eR?1st!IN
z@0qeb25iAJ)LaoaCMC?~M>ZRYB<>{pPemC9iLJd+_#C=f5bY{I@;e9?s%CL(HB$p3
zg6qUtnlCY=1uxkxw;gL3apwZ^$j7077V4sch6>|oBN}h~<C12hpl+jkBjwA7dZgc+
z(sZ`@vYZt0>3jO3Q5;IE>8^?xJjJ&GO%)san{!+M5fmR^`mA;u8AZNs-eij7IkQho
zil4%@g|hHwC-Z!~F3;)lJ5gObN{>coA<g{43*jB0Ub)S<nwO=DVoaGsIh=6X5lQXc
zpc53IuDK;CYszyx&H{KHTn4po6R)v-=b00yArsfoOk7o-oiC*&|9l^tx*q{uT0mF~
zlY7`z^OJ%7<u>$d^l{rf0llM1&CGfE=AacaK$d2iALfj`V1#DbX|TB5ATY7tm+-7;
z)r&L_6)4YJP90=AZ08Zn{-oGWallTsRe%6evHpO-E^DY)7RLr26J__lyX)I=V%8}B
z^eGp2-uyq^3)Nm0LxK=<Q!|O-b7P(6?y#MOcC59n9=FDcz4j3+!46$;t4S2I9j}?D
ze0k)ysOp2=swud?4dj=K570Ym!%eD3O;UQh*<o}+y9Il#Bc_!`^YHzpEIEJV(|#23
z`{$gs0xwfE?sY9>$7G#A7P?n##A*kr)IG((a$mTEQX*1hMn@*(f7~4tSG=N=S~tmX
zVuNbd2DRnVc6MNwHWVdQQx<}wK35{c6TsVW0OvvJZsl$PRQ9`w!{IsLC4Y%nrFi>L
zaWLbi$$XNvv%tPZ7N&x0n&ef&5qi;*^{OuW;3oJ-JWu@M{1-Vf6>fq2Hp2q>qnAR?
z`x>%$lO*14aG4bhcYcE!@h|w~#D1VkgIT(8w>naN)fzjST;8XJM=<)|30raZ$!360
zq?}1iAkUZ=<n(0+1KR`?xX<Pkdy)<I!`s<zU(TA;YfMTtRYNskZa?Ns!nMKV?|p_-
zlN^5Zy<a)K7%OAFmCP&pZ~b!W3Bn?`t%#bP-Cj?a6bjm@RXlO6ZL=K5Y|_}j8EqY;
zF05-)GpUcEJ>a)I6A=R-BQ$)`U|uC9Gk`Ys!-K85nv<l0?ET^eQnDl3Ep1r9MZ||e
zwK_E)0-244)+kkpNq*viFDMV{MZRU;Z}wfJ@?RxQsXy%*d3E^xonY*#vjt9(Cq3Zf
zSUbv-rjy`Vfjlm>QRjcE<&81#6m#NT(pt`BkP>{@ZsFARmlie9N$kZm^%pBn#~JMN
z7NXY^sR1Lkt3Jw?ti}uTusH!N^Ntr|kTZEw5#DDGyp=CIz1WKqH~mqp15jrwkH4UN
zI>?6l*yKl=_0`62ZO@*Lpck6CN_EUeWi>eOS&*=q;@Em2n~<|29o_Yb>sG<zW)G_4
zw`j#}nf@O@KS<(Ukdy9Im+o;7v;&15d5&t74T<bsqhFqEYL!!|^DkH$F0E6^1${>!
z+SNhwr>G6kJZ!tJ{7m!7fes|V@2{h>knstF_J^`0>NOp70=LCb_c8S{DdK8)Pe>ox
zaPJ!4NncKq6``ebY1?AqbalV|4qkJwbXfTJ=lZPD^#tioUY^B|ZQ>nR9!fMME4Gbk
zTpxur+Du}_W<m50HB`4-kr{=)C|;-A!EG%e7nl>f7dUFrgTVtGa)g+cs+eMXiKK&U
zROj3UlL2!wXmM~1tw<Q<?!BUmwjd8B3#O;A;X)l8cE1v%t8Zzv+Z#7)6ea-~;4<9`
zD&%#-|KN(XbyN07It<d0G7FfsnHplV90Eu=)Vx7R$#e1S5uhUehNGO(G)tqqQZ-5!
zo{Lm?;77H85G>}22=p4Vlq5vh>Q)q*-NOl!dv5fvM5&xxA~%ZNnkdR-JH19X|6+yR
ztX!O!aP#NJ&m;6_y;ymb4@l*gZmIw7vT9LOmcL*gMTF5!ekPb4;KGFTS-fLUa7X5<
z1RU*Z-nC^l;NRLRyMBdo`YnrvsaRsiP%f}vXIC8UNIQ;)&GdnH{UbEdn32R%7IK2d
z+y!tf8Hm5?gW>72hM5oY5&lv7nHn@1?u9Q7lg8CCBj{2ty0BV>l*5?%y_?De9|4Bc
z=uh_cD&S4CrOO(?t$zO~Ypn$7F(Phu(jO=EsZH*~0}oi(g7wGc3jCq3o=zk=&uGd)
zw&b0IX@%vFvvmGf0?F08hPV+v32D%cE1<E00ZmjGA!n5k>$^hudn((BfaK)L?AwNs
zt7)KA=QBH-s~wn+d_rN8v7v3bu~9zTwoy@NOGxsJ{NLbBqaY%`BGq<EL1dDQSST4Q
zHP(rJ$@;)dsxSFGTq6ZvKr`o=qDDh~tWZCydt}|F*mjOy-5cw@KQ<aqcWgQSeO1Xh
zLsxqkqCjD^dT1raPI-i80|mQ|&KGMN+tOkC><(7H(BK)sb9Z1E`xBIMg?~4jGt|yD
zss|c(zf+KNN)A2|!f(6?$YwKIR6P8(;PO^{4LP6ZP3^N1f@N^r&17k!R9N~~appJ%
zD-D~}ct<!4lxTTg`I+_e)4Y$0>3cG?PwbG^yo=F`+T}Wo47J5il@Dr=s{chW?XO%$
zke__69PB+3?Xd2f3t<FR@xYKA#D!(+=mfI-d<Zw!I<87qwwm&!6+mF3vsd=#1Shbj
z$PA$idJ>u~)e8Q&#pX!}FED^!U0m8LX;w28YTIlt`5O1MccMr=YKc(Ph{J2=LJTi@
zoqHu;aHe2A-FFMU#e+&?O;5DzK_C>{U*;OC2%vnI@##ESz{*=$@xr0o7vWZ?9dT;^
zZSWh>pP$Ea1kpuV5_Vs6=0UMT!dv1K)(5Qk>5TBF$i0i1HQY8QhG(%1WeLIKo5+GC
zZMDZ$^pn=a#0UoUS=H8KL8$*Zf#piZ72ERzk;=IVGq`n94x#u^PfZoj%wfrD{Jhso
z8j83goVTQo!11(FUbgjMzroUUS{l?;{4Cbr!oNWFvF65i?VHL80tF&7qE>ep`<;6j
zY(nXtxC(2^_Pa_1rSQ1j>Ri-Mn=8`}-P&pNqXp1&{wD#7gPi+`g}NFZ|8G~5b0Z2#
zY)#fUaBPirG$8LW<#7aU?=OQNP5ky57%=93)dO)=x0@TBPU;8$5{=|N-+_+mS^da9
z76hi<g~}NxG+N1qgee%JN&RojJvV6`WqZBT@t#E$gJv9-bq*W^R825ly_7^Z`}lV2
z%H<vVx$12c$V&eIt`_rAHSE^k1ye;%uW@8Ks`O2;Bb-?C4*F2jUHSwqcB}a*{z8KN
z>o43+mu(UuA`y_@e4sCn_XD5rE^L^o3%o6);joUm<=ZZPCdhejZ?$+Oa`DH3=fFPS
z&9+=_QyQ2Pxk4-P*B_)p1c$~=bTPZ7=89G&ejJRpgalYQ(_EZMRK5s4hD9^hm^1y>
zOA?Upn(uS8!Pv0ggYlvwkVB!6p~dlN4t@svFVE;i%Rr&hio)9^d<9I4U)+8NUxH3Z
zvh(C%erH)1G4_{R?8cc`V(8i>M{Ax>ZH<l>1~Q>`iFCd3&~Sw&#W+yc^Hs>+eWxo1
zWi`}Dzkd?mrXKaOSQ!zBvsiB(14Vr@r$76!o&kLt?c2^+oy6H-39ST54)>&muo6*6
zamzBT4d(mgN@0_h{S=F(Xaua(xv+y2x<`s!N`Kz7p|mb9@)obg<ptrPX2uxk>#Qwa
z;vlUbHX7!TpCz)6kVPEshs-%^)*M~?N$g(j=^FI*;0f%5$acR<!X8@8ZasT<bic!2
z(<O5rQASuDCd*!E3WskS^nt@TOd`?tik9unm&4LcGtQG2gVtg${=Tr~XNa-i&>L-F
zyx#WBNhj0Wfuy;^83FA%$}o@PIvd@~?$%cuoXp>pMX~j)gkhQ$^Dj_x8iO@}8Q)h%
za$5Pr(>^WBf5Hg^T_I19vY(ZW@otouK99-o;7k!ZVSUV8)=nIQP6*mBtw3K8+3rgA
zC$GXn)@zzcDk+;XP1_y}9(tM{<RpOoPL~`dRdd*$B>73564czB!bn}SByzf%vYMLW
zl=v1aR8osOTv)w!AdQ2z5T5q1Xf$DSSsFLOK=n=r{hIaVgGi%N&+`RTiLyl#Yp1!F
zyP1o$PTF<#c-a`)(}e-lB^&W;VBRMG=IkQon3L4xdl>c!ob%_Xj<LlMk-&UfHaZvR
zY1Nvscs$|i7o(-Qqut8Ybj}6mgw)AaKmgsNmIBBS^?#kg;67v__0>OyEez&xE#_YH
zktcMz+$*QYYqA#ZW%+^6pFaTZ8L|)*y066L3gk%+)o!Pbj4oE|h<C_;!dT`?qQRXi
zK4xNvNx>(gP2s<oZ9g;SNGu<6CCD{Hs4Ox7`B>CabYG|d7=%oAqj{VI2D3{nWW+Mj
zuJ7_a)s8K@;1%2m6GoPAHpG<+f;7?s^1!{RRt72xASgS`>kGY79#qTWGLJe2#791p
zsLd2c>oh5I&N|s308L2pGtR-J!*BLGZ;|AMkrc=CgPDknQuku_PBd5Q$=oX4IMlm@
zi+N4q2b8PgEZhBBX(Ta;^J>f_)5GRP4&#SHD|@1qU61An3<$mV$!QrYZ`+1?ei#=y
ze&K~z@jM$HMd9<OvVwbIzYZ<erHW6bTj6Mgl%@l`$Oo>W0`UYJ#43^@|5npMAe#QN
zAKVSvcrB}PWX|&pBYr6pM(5=&jc3xYW?T@uqyK%^4|r&m3<mUzk%ROLi2IEzqV!_B
zYYxY@^LXFqvuVBtW4);GVLslAX0HFRTZz!LHmE`5S@=JS1<;=Am>cTe{X_<xQU<B=
z{?BYpor1|cVgk6f+#b`dRX)qVHlvdWIXsN7@+CBXjzl1BWKLUreArL0I<nD8?bl)s
zvUEtq52Tv}N+OWoNZc78!<tgsP;@rHY3ratQajbR;nZA!Nbu6sX!GH0v4q^ED=*BS
zM<ql|6q*CKGBTrL6O94CrQImlde6<L9DhS}aQ1fX%3xcvW(%b0PpSEe%fGV%v{0)n
z(-l<RVLbPcJuvoD6f>G6!G=d2cg?ch3dlfnkW?#^)HF^cl-B&jNnsbe+o^omH;c{5
zY3;TpLlzYvbKN@+c68)^)b6is42Nu$fkk$1|EDDLbC}IP;r2y$%E4=C5)YL)XhYT*
z0Tuh93@C`8htw`sXC6@Y22p#%J2bnxA)IjvKX1h02giGWHZuJFsd=}URI(x80xui5
z9N?!_j&Y~80t?LN5jE-bS|S8E!V*M=yj2ye<N4Q$U_e%PscdaVh%TPuD9<0pBUhgr
z?zR8<Gt1<_5yt?{xkgFHTdR5^EU;l1E~wvJsgShE=?Rfw9ji*8eEsHs=MnnIxs=Pl
zrlZDi!8|=d55Z&#E9`v={NOHho;GxE7#KZcU>*b&DmNTgEA9(YX+y&E9{RJ*d2Rz*
z(5l~+3m?P0gVQAT`wF*m!scPas$*)L8crCgxa%iLvCFsR?NG;366OpS7-Eu5JyKBh
z88OB()9nE%m$YBr3w0<#_Y~HPNi<~RxP);L>*dEOl#u-Jo+4sC_K`So1Ar3Zk;kY*
z)5^cydYG7IW)y?H0TB1-)`FGRaMT%vG34T-zl0eQlK$PaHP$@*dE{)dW<8)jsg+a<
z0W-g#?Dh2fk4l!yZ|zR-;kW4Z7DsDD=J=WJ=MmyR)ILC}=<D9R{2Z?z>`y0hcS2%(
zj!+6l{)BDWnfy?`UVW|2t@Y?F+@&yKp^XL<5t4U1>V$WFa-%DI$Ja~|DNq@{E$pdf
zsaoLnxpbp8;;y{eDU7|GPce8zDZ(gkYA6tcCb0HC^S{M=X7tmdEYGFb)&VS^v@ot8
zXgQvqxAw|-(93rH&sa)yj{@i}Yp6N`XI9zYVatIUY?m$8YGyd>Fb|>4ptDWq_+KIR
zQ#G>&n0=QMVN4}`D8R|^5LnLt)$Cu_aCs7Av#$Gh(Dlq%Jl=LLG^B*~7QV5`j{`Hc
zwn~GHyu%(@qL97h5cRwksU0BbT!AJpaeQYImnF&erQ#wFAjeB1Ra)Vi48ne0<kGs&
zWeHQ87U}HCCE4LtqqUngu>J>ug?pX;tdE(+?0E=*Q**%}$Gl47m50j4n`4g*I@%oF
z3G+q>SxG|cX5o>`;4<?tYKj*nG_90bjK!|rmEE8P^rLirGxv^HD45*~qZ5)Y9jQKJ
zr(B+!ofm)n9y!NC_*6v^roxIM6+c*k9O+HrriX1w)7GRwH=TAEpM8!xhoEUQ<+b*A
z5Of9=!?Z7c^*;S7Ldgt1wDq!HK;gRcpXq_}x;<-xY;+&y8u2CJ>5tb&bG6kjh&J<f
zu`o0sU1r!%pdR&%|M1Yo3=`p5*eB4>8(<u(HOZ^0gbqMAS4Uvo?(l`Bxc7Us=P$2B
zldI?@zQtwKk2>~D2LrkvOgJ(Tdku0Ik2a-d=ca=cbFEX0Oklrb{9Q70pLiOU5@^Pk
zohxq9EOm_5=XF&62>X&6xlk)A0KhCnz>$jd(B7t{pI*qB>Ny2Vq!U6KT3U5m%@CeB
z=Z#4NbnUr@ck%gvFYR#`STn#Ncq%;y{XH6OEPWtg@0Orz8ZnmJK4yYQx&qE_e7CeS
z@91NYq}DNMsFTJ3&5>Q5k9851=U5JnRA+~^pXiuEXs0!`p%Y7;MBwW-wp@L?MP}iN
Gv$6B^V=#jN

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v
new file mode 100644
index 0000000000000000000000000000000000000000..f4f068f7440050c88e1b98f283e6023957e47aa7
GIT binary patch
literal 15040
zcmV;xIzPpW6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzM>aO1caUi_yTy#>wr(Q~X^rHxR5
zDMq@J5lP;Pv`+?0FY?ruFBjFB%I5XtJ&?d+!0&R`%USLKp^wkLZJuBBRm>yM3yt(a
zpbiNAgu=~{jOSG?P;1q`Pq{=hSELJZ*x2<z=K6pBLNtuG@gim%kbMk}cHH$OVi|!m
z9t48w`y8>HIIOj)(~tU+9oIzEN}DVvK6B#+xf2mY`-9Vlw<$)u$ah+kEMSGiha5pd
zn%Y|cE>>SqY8V$YL|r{?@@X0Fww+|((dApQuNRi%v!u(R^MgTSV;L`eesxIb9qh`A
zx;cOH6Ki1#TAn`~#Xg6CG#B8%K{72)jb;>e!3_i<(^IdA#nP9qL->k4Ot0Df&zS+?
zIqLniV^9W1<*V%IJz5&Xm{j0YUY24zwkOsP*)gj;O+YMFHxn_qF%F16Q!}(M!llS3
z%A{L4Z^Ls-_GqM#B=dtLg`fS(d~2UV;G7<2!oEqaQB&s3ANYK*`MX_$ndz*kb}xd@
zlG1g%OZA@zjL0D?m2$pH-GTMJO=Sz*U^V06sYf~rg9gYwI6B*s0RrW0B>Epbi<6Bh
za`X6pitf7pF7E8N2$qGkIAVh8<~TvaPC{r0n7d&)dX2ZC;z)S{29DPDiM(5K$s=e)
zos=1tP83{T=nf|x6?1r&TbXI|n6*dF1Oge=SbxY|W$xs=XKO0BdP0b)OfbP*af*hR
z7+TnUK=tYVD(;s7`x|By{A#5;Z9Havc|nAeLx>%&?s-7ZV-W{0iaH-99B<X&6w#XK
zB?UxwI7J*xs)1ra3TH~>YQ!o1iR;8S$c-@1*C6#v*P6SByCnWv(PLnH>JF=&wJ&=o
zMw;wsR>q%vA{SI#{ty5Sc5Ym|U_iR&ejM*rLOn7z&v>95Ocx(=Cn6lXvBv-n4#O5I
zOx-ILsU4CaRUa3ME?i+r79&U`H=%PpdlUNY+7k)SS0YQp;_ij%HMe>{LfswtJJ7v&
z`>Zqi9GPq$giO&ov7;Xss(?SzwXx7vpzv88Yq>?Ytp-$XPwFGk^QNvsKZocdwi2Gh
zYi0FcH&q3X?Hz+R0-=qzFH-XP<dtt9W(nMk&#c%{n4H>qgO7Px8BC7-uCgN*jMESm
zENTIGd8u}ZpzY+2UEJp*KfpkQ2@vT62uf2Esp0;ZeZQ_Qp5L!#T{eg?w)iZ#mWP60
z!nud-Jr6avHvqi}rNyr)K8NqoA`5^FUZt>q4w*m!B6BZ|468;1+DS9si`XLXAqO|+
zZz?u*y^1`pOpv}hrtz9x`XGt~Fnhd8zRCeZaXwHpJ}ONk&QcE0!dqZqY$T2Sy$5y|
zgv>53gR-7bo+xq1G)f3+ofQg4m_uy48h(Q`Up!%ebfW%Is#^3ej$E;D;BLg1YhJbA
zyx+!!++)qm?s01i2kv%NlkGt0$igEvmIlJs21f`Hv`lOj1D2h{bmLUv=0{6gk{JQx
zR2d9BOUDU-J52PmNYIvSu=b|9LXA8<{NZj+6mH#bvW1M``TC&%buC*YRLQhc#9)m|
z_U*5!YfJVnJ<!sA*K_HlCXY~t<4fo%w(xqZbD2-i*8hhT74f*<=9`Z)9Qo7`_sy$3
zLoG1i^RawF53~{B(AbKCssJ}J5-s_KxX^NsTNUM%3I;mjQ2`rfsgS`daOl9o@CK`{
z3{s^i>L{3xr?1i+JCV*=j#W_U7xUT9DjZ@v^E3AMft^!}sTK=y9|Qj-o-yE5|2@Kh
zT&V*ofIMBV+9-tFn8;pQz@MEYH8$XvLEcPPNk+fJO?Ijz<y<yv3*<coLy!n222~z+
zPr(ZC&mAT9$Z3aAtpp+^G}vMLraLwHt9DI}luR}fIkX%vSc<I}cnD<-ot|?=+597L
zVS}O9KxCqnp%i70|2eDyJ8=iEKPM;+{i5=1;Fg%ghcnw+n$eAoBcsleA3g;{#Ulqe
zTW0}#Tz#@5ohdPNob@ol8zIsZ&KzD0q~1v9LQBHga{o^_15V7ri0pAVr~^L)Nz~ZF
z#%Hy^n$bi;<z<-aIU4~K3{GuAKW+&*W}4UZ!u-M>v=q1v1He&1p7(I?+PQ&ZjrFbl
z5=gOMt-qiI7Ri?`r8u(Ljfth;spL6A5N_c|Yd=$R1SU6wUU0-CInZ=_@vYx;-eag&
zol+_g%yRAvqLjIjPi93);3dnbl5y1pik@_pq)hyhVN#gU(94m<+XgxToze4Wp+A;Z
z#;r2^z|<(Hx|9WhbD&@Mb{Q;?1{m54M*CErs7J(){uk4gfmYPV?|F!S1zA}J+ckp*
zAp`MeI5{8~y7fG{BL|P-Q>K6T6HW!uHdr!m23jD<VeLa%7@==*B@6+)A}5zsBzXh6
z_m@9`!*(uJL}eHS@85}$ArjGK{GB$<*b7Xi-z>D8J9;m%HeA|gPlSpjyMAnrl|2Y~
zSnFTBS>zvk0Hts+3ne-%ZrfvL^;)R6VZ+L=X4THa3{NpA@U}XBEGcH0paI;i-E>iE
z7G|RfQ0V25WuQKI2~T$JoVeu=ecxEUFHae>ffLTu&}C&S)C_>fGzw;;15;=Ri)2d~
zLeX1z#Z6T4lTdLmi*0TaQ7esk=svOk*Hid)Z2+?KBS2#uvCSC^mN5c%<?z!*qEv>O
zd!>$ZjT4BjmFTrcR4~zW8!x`-vjI8p?Y2X|e^P#U%pQ>HS8%jTd6pxOjFS?sS23Ru
zn2{%<V)xk;t8pS$+OLbL;{lfeHFqNtg*oSL0%@^oet?pBPTwN@8@^~SC;_rDWwjb0
zg#u;rvC_Z+Q(>YHOMcLEch1O3y3bE4lREHcpJrYqGsz%1UYyzqsFe|_^{VrdQ-CyD
z55$Z-kl2O866@;3GBp)qAm&~&U9~cpkUsY)G>-6#u7_Ne@K2w*tq+FiG%ento!=~U
zW<8OX3%G}jAzz!46nLCEJiqm)SPJTcqvv~#qahC40qOq|Zd+yY?p}i%T_85S1*rc6
zJe6%F6jujg?Ox6A7A0;MbmHlhg%wDe6xYBvK(wp~j@wKDSHcE)H`Vnj9ha3>2<G9?
zqcbw)Q~_-fVIQFypmD=O4Ub1em{#}Eu8FYH8<vsF1B|H2art@M_a(~aKuSC>{Ii9(
zL-424lgap&c^NAhk>=`P+ic2cCv%L^?Wo3`@vZ(7^0|A(mhoAx_wTAZoLXD|HGGg(
z69#R3O-zB%Rj3&|5T4%du3<YH;!58t!Fks~U2c-j?@T4Xdw_mz{>=GY)U|e?+5*kk
z4FOBYSw#4Wv68)P3q}E3)WA1L{z^v?gBGggM?qczywx8;qMKK8@DHKp!08EqZOOgQ
zxfen+tE9MY6wJGUDBbru0WQ5GTlPhaGAN<GKmL^aa<M_vKj5Ya*#u!^*No*?6N3hu
zFei{F{aH%*&gJZ(l@U?rDr0&1j5k*N=~kvMSv+U0e~FT7JUy=+6~&J!ycT1`PqTi#
z2jrQ~7{!tj72yXPGkc8uOi`l~eA`h`m#WL8hreaFVA1bSdHT#vone*ECg+n?iV7Z_
z#14ugU>aQhXkysR4-q$no#TI8CU{tZCic!yOmEv?l<ql^x2jox)#LZ`#=khbe{t4y
zBK7DL9%)z8$}H{p*aa=TYGnLTr-W@=ie4gp%>*R`95vS-w15%SpA7TyD;sJUJ?-bx
zX{cGfT$<Q68P`OtPwyKvwI2>ClFBZ&qkH1AOtKX%3aY>%+l$y{kIgfd&F~3Epp;XG
zqx_Utys1}m4ZCz}3wv8p#oXBfkx5`<BIxn*VdAO-oe*F=H$}4I*9#}#-fVsWI*}|{
zWns(@CXfVbu{5*G1?UyyRQJmUaNLS|&M!*aoVvULZ>n9O>{H8GqK*o+NX(0u=!^kz
zV|168uI#yVORK6BJ4boI*uDC0BrZvJ@bC@J=7f-a+3EMjfM0JX{KYt?SU;2poq!wt
zSKvT<a{gm*MHKRvs`Z0uKx=w+F368d_6LF;*7t%lBa26RQE~~~a4xls>l+s6mKu&J
z#Y>PtG64TyN+A=jjAjwTvc-g;SvZ4d$`D%MO>hgmunTgo0JN*8$*g6-#uQD{eEgcZ
zN5>t(Wk3g5giCSa_OUTF-QDbEki64QV99l9%bb6CZFjT44t4aq^TPsFMkiKeHRGLW
zU8G_CsjF~jR-2ex?ngpqby~n*+8{G$wOE&i(J#m{#|GWYUm_O7L^>!~!S>#}uHC29
z{t~#Ge%OL=+ZxlOuz={m**+~v=FfcEt{X%U=>V#vLvo3TxKGbm79-+~JITn9_DK8&
zV|REsxQN6eB*}Nk<jbdlfBOP?VNGsxO&p$EPsfAzdi-z{$Aw$J9%YU7I@GcfQ#%IQ
z$)-L+kh9+kGRrucs3k;?Dj~E;0%Q;uqz1S{j?tPwIQ52*;{w*p-~vz3edf8uTw1BK
z2WQyw9c7v`?v9B0N209JZLe9$P{x0If9+!L%o`J*X7$it|5{I}Fm`yxbBrh=mT6ss
zJvQD(3=Iv^(K}Xgm#v8j&Ajba3Oi5RqhGOwxbrO3$nS^o-Bqgy|DR8nx0e5IFIlaM
zfF6q0Rp-u(o!RWfb$v~hRx9;|&I%0!T|n)?c|3;6tq$z!gpNj4A^pXnofr*@MOnOw
zgbhg9k|yJ6#hDjX<qvA<1zL!TAq@jhGY;s6s6-G$%Djp-#b1h4HG3zSl0Io%qa<aA
z<AD9XM!S+R+BdKH$*5cGr1kZjcTf44)iJAgF_#RD_DJd&?EP@nh-qiizjhE6$1W%n
zc-B^i66)nf!M?t|KPO~%D9ZoQHiz%bOROb$R8!b0GdseDxgnloLPsHzfrYAu-{i;$
zVy`45cFD?Q3z}u%iOpEZ%2N9VNh%5?g55iOU-zch5Mu?^WjFtmE5e3fFzT4ZE~(1r
zwQo>l@ElNB$%;hVlto4oa3JlJ9=q`CPi}~@3X;9>&<Dd0^(1_D&nqlxwsoOnygp;$
zih90%L`D`w3s*?D^atUFzNNv(|I8lzuLns<tI>y~mKjjcA>8xi?7!<<PHLs|uUJ@L
zi`H8V$IM`+o0yDs`CV85?wK&yy>9EbH8h3vmD+F6_jLM*S|IImHX8nL^AQVuNR!p8
zJVqd^;)D_QcJFP=Bsni$ApG@>YBGaM^bqptr$EA9Q{s2p^dmG7T6_XD6ngDIpRrbL
z<X_5y5oEI407>p_vPmB&e%NSR;v!M-ryVLr4E5ONwWP`su)?sdgg3<0Xxtd@Q_QD@
z_CNDDyM<JS7-!6}G&^`vpmR!9M@+|`D$2dae<&5j06h|`Y6*KNkgfLz_$t04L<Wu(
z;Ou|zrhOXObvW>nILCrYHfWwazNM<rJoq+FDJCz(&~9ZwG=oSx8|u}kRe_DI3~v2q
z4qu>h?xlo;7Ysy0<%I!-yBea07pexxaExW+A_}B*yn@uKR#}Qp*RxP2&>9cJi^i?{
z6X~u*Yjqs)OfZ{=x4`o3AzbJbb>cTMjy7#fVlbmsG}qAov?N%Fp-Cq%_{qp__53;~
zC<MCWhwfK#h^JuA)y?iUThgA-Nn+8f0OV!xQKcIEnG+IF=geE`$6$F4X1m6%0%17~
z?Isq_Pzz6Q=zxY3Hr9?gQCV*o36zMc#F(jY)%bm15^+rga@+t2MEX=^-G*cStJgeF
z_k(*|1uNVtLXO~!N_#bdo3-H1pmuAb*d*cwKwf?6bZ*Q&ZN_a+8`{lpD`MF6Xy3my
zq!(jgO*GhPkQ3x(z2%7B>QLGwy`4*_pUoc}dti&c$K+gRoS#JNVH2{>-*-2KOXvC%
zXM(8?X>IYX*)~GL`4o5BUdAp5d2_w8`i+7Wv-x|)3s(_qgSDVPVS2gJbMwQ{Vn(IU
zzsq*q-z7iub4G0;RbBodCmk=Aqy=%|=fS?W*>hrHKvVeHEM2oWVR6mX+HNb%2$>R_
zlt~uY{UVTK2Nd*~(y$u%)FrY?P155CsL@;cnD^abojx?H;5X911AceE^F+^u^5q^P
zSm%MTtV<<h6IqxzZBWiJs8hbp1Ng=SRV*u_pmS);{33?itse&;N;;tmk@25-V61zc
zw*$pk0bLUqpnF@i0qaS`62y+eoyFXb^<^$HezrcfE2#WB%W--F<jtk^QB#a9^Uqd;
z9Gb-(K4YZLMuw@UI>+otBH_c&;eRe(b80}1R}fQ(|F428YsZtM??wy-`S=4z^TeFv
zn$M{hzThAO9~s~XM*>flS`Crb*!6v9IZ(<xPJTrVp69IuNs_$jMnc8fnfMOw-1e6L
zD#17TdMzu`bOj5w$dN9ylpi)&DHC2q$AH_{<{zMzWi}YSZh2p1+=`bZ2^VQDdd06W
z_N<>4|CuweEa0#!mpHReFgvHE>h@rlc0{JHBhNb244g=+pPeH|eP;~FWuj!|933Ty
zvG>dT>t6AW`MO5X1>#i@LB@Xs=g;kR)M%83m$sXaF&oriE`Y%sc2@+x0)rZc9SLZ9
zK`)OIeZ<C_sjT2itWu~oaXDo-a-c#E6gzr|V2idVkwRuCTI#?#LFu{I+_lq`2JN5Z
zsRv|JadGM`c~(jb;D?^Q`pE_V(Uxae3zy;R03shyw*1ghYu2Cf-A;c4gielf$o{Jc
zmVSqS!-53?*>qbA#532d+yM1G+>uH9w?ryhdrH9?Vd*W0wZfOz3%iUq(i*8-N-m-_
zy_48$cVAM=5fAN_yj_P7k`J}b2hyvm8d}xEj7I2t$Q=HJVkHmuPoZ)F9kPhtx1jHT
zWYvCgzJUG*op$qKh>z*N>`qSSb%$zuhRxrjjqJ-)yA{%8=mC-SGARET_e*^i|L~jO
z8dvT^f^)$OU;I(FBP%bUMDK26M4PvLSq05SFZWv-Y+7sS^iENvc&>ABReON%HiA4h
zI-qdMWf90NxEorV&zzkM^5anBy*vms`xmaiu#J{kOv|sxfx<aF$(RZq;DP{_5!fD~
zxn;83iZEJnp=t9<vW~!5(bY9`g-x+YRpBZ%FC;k$m&c|G>+Km2U)6CMZL*r$ZBo;A
z_#Zpi%aq(&m^JtzIrW!AixLqN8_KTG3b#>r2c8U6vfAeaKg@RU(ze3$`x+}!NX}XP
ziH-;0((wGo#T;4<qw1W1D*g6CJMYMN2*b9;)x=T#7ah)7di$4IEQ{An>p+a!-=}=d
z3@BU{Z5UP}Z8MxYy2dqnM^Ji>p3vZ9aS^T$`i`sclncB2lU?O`5>Ue@Yv+qO4&8fN
zKOTGNj5pZcH8oz4Y`FDkBn&Cg!H9BiJM%raFwYw&>tOyf+~?AQC?%6fz-E0p+{82e
z>eZaYpvj~~=l!O~g75AV=fH)LB^c+@dW&j<;#*6k<OS{GJjv9&OzCWe{kg6WwW|{k
zErAWN9aQw3q$~e}>f4iFAHB0z5-JlNn?s$}E+|gS(VNNcN@X<6!0nqYUbpY6Tx=@E
z^kr-SpFXEOZ*3XNtfTN)<Ihicc`GtEt5H>Rp_UcNx8)9^d`Rv}g%YhaRO51hU8M8e
zCxqGn)hn21!P3~n$fj#@gpXDbs7?L|(1;72A&1lXyE{{FbrvfMm}iFs!DV;sG)`F4
zSEq^E@o;j;e%aeY+I9kqnF*!G9_Q(uX>sM8j29NjJDyLz+*_|bkBY%X<&5a$d-}F~
z9Ar$pQgUZ7irYXS<<`k|du>r$64ARh67WQ&P)>ik8Jr9d^z>7%up8oBA&!cZS`6TE
zf37OarN>C;;kHopr!Q*44B+?Wte^PGzSW-1mKR+2w*796F$NN;I(2g$wo)u^IrcG{
zC0W%Xho$8xr5YveDbPCx?UpIjze3$O7L$JVl4>n7J}-(_6m{Q9qP$;1xBxbrrfrgk
z&a<k)RV(xYuVWNUhJidX9;*dPwzNaoM<#3U?dn>nUhbH?jP174Irr--37`%bwFKAV
zUHdRBx!d@MGO-sUsNlES0LW1Z&o2QGl2i|l#ru2~sX`9GV;ygQafB;yY={j<=Ko@6
zw^uP$!x*kEN%MbX7?srgs;$j(4Je2UoQ&%lXDiQ(e0JZ$74K*<TTwr@SD69N5dVME
zGWua)C-bci8HHupKrADdk9r97oSO&5ZQQ1%7z7M_VSy@>63o9EPMqIin;k^Ewqf3d
z*OB2q5O0gOFtacrJ7&d(O=4iM>hfs|F?RH%Er~6y@^Skj<9ww73+_`V*0xAwV0-Rv
z8Vn$tYtGF4P2~hFEynetNS<Z4`UZE3RQ2Qg5^3rMDv{BzF33wELCiyi5D%%)`#d5R
zS#8_;W@Qjt!m9r%LoAl%c%CHiGSqLDl$=m}L@4Qz4?Ev-h@a->;*A$<$FCFqt|>;9
zedifF;t%t0sHLS5WJTb&|6%$OK-<_DBJW64(8kb0cTf5Fq|VTCUXG`a#|kf1nE=*>
zf^xgs2Rl&AnA{vMph6n(ZJw%aOR_#2OuJc<Ea5C~xlWhw`J&6`iQh9KBT*RiQ2Kh$
zvpU%93tmn|yW-2=so8xCCM-MdTsst#za)?az$F~H?1)%|BejvzfzNMXtE`goYv2u`
zP1R2?QYgj;qprJ&qhyC#pj+zrsHDa?B<ePsY1T$OdG!s!8e(UHdy6EwgNXe@e(SnZ
zOmo)aem6K(_p)rPOh-^-9o{~U+Ux=r?KJsrV9XN#qN%%@0fkd!eTJ5uZ^+CTVv7Vb
z%J2mF9w4P369LDZKrpxTslU+feTFfX9aljs7KIRk0D8oBRS=H;UM{)CF6VTVf0K6x
zPJf;>b7Phln6?9&3ix&;KU#LJ{MJp6=uJ=8JOY=kE_~@TmsUYqgiK4Htj2JZROJ|x
zyj$o)!h~R!iQyR-@?AEa%IpnUUqq7yYpToQOWE?0w5`#KWEvI`{9MMaJfR?JQ=Ow$
z_eph?uBzv??_+`vXu3oh?YnokhPpB+Eeo!@{ScL@Jx)9oGaCNkk#;+sm_DO+2lf9^
zI5A>G9Y}HAg83!e*y?SeG})Faf@^!sl3G&@&qK4DWc<7Z3Rj|w8B=eXib}v|b>-nn
zvxBb{KNpNn-t~|eq^?YMRKVP*sSO`MS~QAVCp&zeMHv|$F4|I4hWWK<?YYLZ6WyFU
zY)xd*s)2zGe-(17SbycBSJ~y;cExgdMRMM+0S4x^^6S)dcE7PZ0O8+*n-gq`+ta?q
z79=|<U<;0aWOX!7oa*gY^RaE@yzR-!z#|Xt_#-MNr-z)c0GgBvU;!xjON6kGk2M-R
zbGN)|Lu|@CU_QmxM;Kc(y{u7EnVzAZWFUmIKBZ$rl+5=sKcfa~RjMRu)?~najocmO
zd%dLwbbOKBy6rtUMv0+l1cn(uf|>RN_n@bh|Dh#~dLbSHJQ^=ehu%8eQQt3$-E{53
zaU<SQ(m@U0fV*{d0N)yPAv`$0oW9BDts?hHp{WPrn{16ISbe>7#Osw`qnF-qQ4ciB
z*aGp5HLp+(Bf}5~%EK>t_Rxtm?l-!&c|OXH%#%?S;^T@VS-6A$%nA})nj&cjl0y!C
zymJcd`fszT*-)QzaEQo-F9wl>#X~^#M8&c;XKB|@CCcOrzWmdLz{b$RMVrDt5+e}G
z=S(X>;7Jet&$xk{UPUYU+T@lyGJcJ>fYy)SLk#?vvthijd(q)P6w4&SiLAUlRmd8Y
zVGLH|E0Z~Q`5Y8fDu&P4EnmU#uCKKK;IkwaiUnvD!!)a|+|pP0cyLVj_-w1P+fVaa
z5tRQxE)*0uVuY9`|BQNprz=^`qY?)LMr70htuQH?N_FT1iA-+n{vIg#;m=8wne@Qo
zoq}`EdwrqKFQ?mJW*E7<t-M=0zG5d@CoWD-I(K{I)Tf<)PY^y800IRHbfwR_Fd-%M
zIW?krGA>Ks@shj)^|E!p7)&QFn%u`X`(YGJjqJ`^tL*Lc<G0I*FT5HD#{mCxYor7v
zd*L;RZB=L`h|(3kumwSiGqPW{iazBPu?XYNk;ec|7bqtfGXDyDK%VfPrPlr&j!=AM
zt?USA5^N=@kPypL-gs3EBs<~;Dk6_ua61J~3Hj0YqQ24~(5bU5=v8Ak-PXz>IJRE`
z$d|1dXNIL#6mG5iP(;Gk2qHx+O$1=HqU1)`d<f#?;3|?G%$Ou3A;5_Zrq(qQ*~1>V
zYpSDj!US9NH6_#=(6Q3uOM=Rpv-f-I?_>yh?;@=V1FMk+F_eZ9o09lcer!QMVFV=;
zLoTy+tS#~Vl$lmhsl32Sv2PxV%+BgPfPMbBfX;4{Q3vl`w{^>Y0YgqaJQ+)I8Wl6>
z^;-00D^g#7@;DOV)?!LbHEtRXGF8Wn({D7c;l-#MP-;(}PNjRXNrLd$|7ofFkne$j
z#y2f;9oP}FuyQHH)NkWrE>}6fGSBQQ9JB!$ERsfh%zafS%BC#Bg$Ur-_Mm~lbl%Q)
z_Y`nW#0O5MGyC+$RIB6^;W^PZ1p9MV7OoMqm>P`4n>1IOF#>V==N6-O7gsrlmNDz$
z$NwWo1;uHjvp>yG&^71Q<}JXI|KYVde`s0TMxu(Ncc1fr#5GEeL<jp31M=4HI=G**
z(?DI28s7pG&qkS^(A5yFYc2T9!d9<imJk~CIiW*9b3SqEPJMP^x0URyW($cBfVX9H
z=!^rLf)Cx^9E1YTcx095!4e0tyem}{#y_Q@3LXoHyydw}^_$^Oi7l1~_`;vyRjI|j
z<byx5*PCac1&m+mce87M`Z&nyT<BX6efs1!#CyH205hvggfH!+d34jUd*8XecCyFb
z<1C*IX!lDbM?C+2Vc>FKh+rXbAZ`P!?0U7<rVsK<3JP*Xg}7J;TeOnZC0s@vV}P$d
z#8rN64pVm@TXm#;YHwF6+0Yy$vbq{R`5nH6r94JhU}`>~_go%8Cu?;?nWpZ@%)Xbl
z+<R3i#%7#l_2dH7(JR<V5~ijRp+q{w3GOkXD*_Iz(=`=&_I3Z`h{15@2ybcI8N)o+
z1|S6%_%T}*Lpoy(D5dw?-@v&tBd~eOWF+z#)O)*>_7o#anv_OW#HZRxJ0D^J2#wA`
zxE*}LYJeH&b8qjvr5R|BF^?sf5CP3vEv=3-pwL_g1>}!f4JmR)YzLsV!i9VVYp(7Z
zIR48SE!YJUjMHD?1BjR<f*i+HWJhm`T|1tP+L@m(sYrZL7ZLO9*KwhC|LoQ&_Etp@
z1ATW>Dc69$%O*{S2{)DzFvfSR60R-#x1c+O=bpfdL|SAes$%baWO`$Ad?2Z9BjU6g
z7?aG9Ly(F!drp@^v>J;E$xV6Uti7e{jrdVIz9~9ScY&(vN^m&L-;YB6rDdt--Xn}B
zM@Den$M04nv1=gh<L==p1-O0&6753#Ss|t<Z`VVJJ$DFgCE3&WOkXMPGr2Ip5a<RQ
zOXAh)p!k0hG0@B26o4RFX$+sNP>qZ!_9b0yglw@(H195b-$fj!xejqR@0Mo+phP_F
z6LS?rG9bnXo)MMMV!l;N49F4p)GNfj!en*??ZS%_B^XYD6oJoWYd9{)1_cZ-!Xt?<
z<l*0atPkt<ht3F*AYT>uKgaD32~lE!G_;luqfcyTSx5H>2Ty@rE4Nmxh>vy&YuH4D
zu+zrqVfo5xJEYo^Q2UA@de(?t$0iAnkbAy$?tgpsGYR@vyaES1JZxr}^TW}<s>MkH
zz>!0qtJ*;87g`NXRp37u33+_X{a~W{wk?_?7AJ&1BK7I4zk|!G(5oc4+e<)b1G4bJ
zJTTbn>ne;d#npD|Z;g3_avyM>1GoTECLcCmZ$V;g=LEwxr*m6*R(`rB#>5jDoT>OR
z_c$Nf0;=qK{)?y24+UGUZpZyqYfH|%$fdUDjI5glOdKxYJQqc7{fpORS)c9}e^zmz
z6h0?BMu0Y=E*IGu$`dByIm8n+M<cf1^gkN*_od6nDzIwzE9?t#^(sL(_9l+MGu<i9
zLa1vYW3uTxpWSo9;a6Fn2@7BT4U{J|%!?*ImzwS5KVzTzx6Xj*K_+s(o{SL{ERzBl
zAK<dS086%R@pgWSap0G6MXW>E%cgGuER-!d!%%LZ;7o|aX?-|mGZY0v!`D)FKuqzi
zX%9(FTm&PU9|7lbbYEDckv1Nj6XZG7-q%ddM!b*#X}ewPdzavXvVGJWNV10x=}CFR
z#&CLtu3nc8pn0ab{2z*$_-c$Z-kx#f6xUP$Jb9n+EQ*J(A^@&qH$6Ntg<o*c*<?&U
z?)o2s!Iu41@%l^hAq$_p$sSdUhiI6t7BTVGy7na^_@gkqQ3>B<?%mzXm{quAFF+4k
zC14sF!Hp*7^g;|Lqa`h89z$9@$)PE+RWEPDzd3ZcZ(&%wdMi8;HE2dbqF$V#`gTeP
zWM~OJ^If4AaNfXuMM(9bDg}WXl?Da>T^SUTHAHxR6pzG1KuQ~1BwUcoEJ59fVVkG9
zcmElxmr{>lArGBzer|Eet6l#MY4%7j$Y=1=pEYSg9p$tT2O_t%-ezIwib($%LdSjq
ziCgyu;kz5p!n>hDD%lgA)+Bl6%Aq}1Xg0Xo?YU=ZqgcsM`YOQx;mY#*5MLW~FmZ@L
zJ4wm_4Hp$QbaZFvy;ZMpvL_;Hw8IRX@C8ZLTzryAxUMQ;J&~dp#1StdSk!^5+BSGR
z6~moRuNoH71O@|<5mn0HVkb5ftxh=XgS+xH2pIi}%xBjIZbxqTx58QBLG3)hfkVbT
zsC^xKOJmJ))bpPfzOebA6UcPV^Bd$INTc*lSbhu+`E|WoOf@g`06p`lAZnUjN&8z%
zc|?$xB4WdhvCloZ%8_M-y9ic#?5`<Mn0+d}euMT<MP|<7%}-@lz%n^d!{73_OmRnT
zWLaJ+jyT3>R8HKE-`ClV6+eJqbQuHhc+<>o$s$t{Dp%@w=r*#UVPB#;Rf<I@5y$>u
zkI4?>Q~I27H`8ItqMsi}vnSTpl}trHskUycz4*>Yhf))1os>#+#tC<~o46&)(605+
zp{x+&VJ(boqioKSI{J4z9+q>%1t#>DFBaXfg}1K$7q0V=yiTfNZ}E&hW&FbN41ZyX
zA@I~y@sOBNy%=TsE0hnt#7z)=_lo#lIshhD31DgksK&VB!fsbcUHlqpyhsBzQ#OkW
zGTvnn6SDqb-7N^et=o#K7fkw<0bvUUE1kG6XGKmzPlWet1*YQhtJGn;HfwN-e&bw8
zRG%yS2w_NCZ$hm@nL#q?6fZF|g#CPHdd{q+QDhcJ!EQryup@x^o?MF_^Zd9weiNmx
zR(Gv^++YoK+==ub#1)qDFjZ9KsCII*<kc*lY|)Rir(u(1N?xcfWS)oQO%zAER+l~s
zMq3&N_qu~z3`|SA_t#a;2a?xldRvT!`H0rz(Kfr7+f8C5Sy3#E3mXCs0Z|ULi)KmL
z1aq_>T_B(^>zr@fJ~R<L)F24xlBnk?%fT9?n+#BSQ%edOkCZA<&_@=|dP6KkpEbyx
z&_2aCUmwb)aD;y<@*AdWycVTlx|!^3DX&N%UBNsE`;Zcr$rkZdTauaM)RG;~)%C{K
z9ru)hkH&8z^tRvcE|t%Pq}8HCl7uNkAN;{*VqgaOBC^SiD)D{BjLk>imY_YJbo$~b
zK$;owcx!UzdmsF20WI9BWojxR9Zx}UR^ucWDg4@e1dOreo2|Elml=JG)y_q<6qcX#
zBZUgOte2h)s`xAp3)mt*B6$Dzd3g8Nl{1Bocc*z>6y|o%tq_93ILWlXU?weJbJ)sa
zRizs-d_no;7V;PEYQM-ec!Tj^N`f*(#6y#cUgtPOwVK->ShTWG6(f4~<7~@|^eC@y
zEh|@A%hXcA<%yyVwGslf7bL89>x*`??*D5XbP|ybI-&8cly6yrP}sON+4z^z)F$1e
zsk8&J^6^?Y57xZTp~x!sV1sZZdwLO*SHSts>}04&$K@WzxjjNICw4vG&%PiAfHY(_
z?EgDuP{7~B-i>M^+z{tKF``aw<RjJiU7as_8lD1H7do4S|87zLWZOtkmQlQHUnx~c
z@x#vN2(286e7o1jM`|gEKa>wIWtdACM*olo=>^^7|1amUSzuh`+!RN;)NcS{`|-U<
zOOw%is~kX4TQ+B?d*svGnz(jHCCs~{Ph>lXRqn|24SggPM&MQv;i}021lxJP>*&}*
z77_9^&;pkGi6F4;-A~bS-RKz*T#l31`I8KdCl_~FZ;iP)rLSlVId1BgYt(e?o26@h
z_?Kc{5$5I3SQr3l_69*sRCZgQgo`c9jN9brgn0|##g}>DPSz6}VNy}1J&mrZy7MZQ
zkyJrlCz^B4gZjZ@Qv+xmMp*4EeosS-68)6LIDV5W^9Ilx!i<0!mjC-uQ2s6r63WwZ
z+VjJLug9jqo+fW_jvOE?s-4?NB=t~)2}5+TP(MK`sZJ8{8aU&hPkp(Miuaii4*m*M
z8bX9nLl^L6gO!R%fI$ERzR4wllrDCL&U%Jb<8Wn@sgM^ebH@Wk)<(|n83!WgBrFDe
zeplgVkJI0yAMelj`p(=($05ZKe&_+@6wBSpm9bRf|0<nA)CY{0a_t1AB54R+W@dJa
zaa;}Rf4G)MA<gocg3~QLs;{S$*Rs_6&P@e>omjsG_n1}$sZdZv4n+c$QmCi+%~~$r
zw_xBH!f!k3m$uaZL<S4rL>>~_b8_O%h*n;Vjb7s*R(Nifrl51xY=<Ud4>6q8-D9rD
zEw~WRCn(R52HF6vz5G9DCv!P?u%jZ!e&!5)VM8E8B1>N>k0KWvE&|+tla@E~x9sk&
zN6hOV^ugjWg-PS*X+TpytN@nba;12+lK$;`C08uQ=8BssQ<ux4;jQ&>%3OIApaO-G
zWKByi6uQxpih6~6RkTTi*&-eoq@;Eyp!Hs1)zv$F!s09KHN7~LG`;=K=X&hHcqZ@S
zPfUP--$zxdL-0+_qP&-wD0!&Z-6aMfvtnQ($e(K6512bfjR9m^_qi|=b<?&Xi%bXK
zDB)_g{S`xm+6QXaj$BA6`}soY+{TQE!NaKWS8pz!yij(3aT`EpcVkJT#81n`s`w27
zt<0}JG3K(12kZ0Q)!aS&Zx$MB2o%pHX!&uvMmQZcg>E*0V@7tph9yBoPK;<%uc_6k
z;XF+Mhwj1Yrh%RqtK4kG(_pNJqn2UEAupRtVqqR-?YzwVLwzG>zqtxet%&8;8{JHp
zqLweZRb%(-KPtS1?ckiv4B)yLyDf!1+CnrXTGF33tqZMyH+bjp4}_fYE;r>^J}arQ
ztakjG-QRpbQ;hIlP%l?!Su?3#?`P=Pv9x@DG7moP-g9<J1D*!)40bS;<-ARxGCbsC
zJW(1j>1!gG?dj_PknR45P@HN4i&CiLkBvG*lkvp~-g5-(PhB9;!Tx^|<84Im2hXK4
z7-X!}lu{6V@iK<$uPzmsQvg0n=xUV;6j2tAkH;_b%bTD?`o(;jy<5&d1#BztAqBkA
z?;O9pkHFAjXr&WFHF8IlUO_eTRF4f{DJ~Pgd`d_kiAVg5HLi<s?iUHkEk1p}gRn)9
z`o%kB%Xg5$fkyQ%*G?FrWm6@#K@tv<nS)w(D7Y;3_C0u}oacQ7XaLwyi8X2(%&<Hu
z{t~UsUhlOB`Q?&XT|=RQ)nVAZNWILpzOe<**@*-pB3Zv6si-1_s1$zR*E)VI7=<Rj
zBDoY^^Z(6OI8`ydV%7OQE_LvoeKkh&q_K5?8p0HEU6=t=V_O7$U6FKG5D#^cZ{`OL
z{aw{|gMdUA9nKAJ<I_GjHzTQm?@6q%b4n_`fhN+mJgW#=l3Y<UeQl=o)%VQ*PzS-G
zps(OOe_aIV1EL6P$o`r+>s5BIh6`}>yBH@Pj}UJQnjv?PEe^8#wbD*CIQCeUbs7Aw
z-ql><3w*Fretb;NQOMXmduf_h2_|%Xnl>K*0qB;R@w^*`_hL#+=ej3y5N*4J-pgh|
z1Tr?bsjg5cTuPb13mrM<)s$NipWu}cu)UTS5x|(e!;CE_XX517I-A(jfEZhBWe25#
z3i4*V3J6OW+PLTUawgT}Y{0@opok(vvAHO4BihRR_vSmJsCoUBCWz~F*g?^pE}o4I
zxN?vbb;CV>Y$g3R3x7~pJh$GvpX-Fyw>M=pkFL%KEh5>JKT&Z6{WsvdQnRMsr|Eus
z?8AruFsx`(_-B61ydwG?{J&a@f!rH|PO12eCjD{Hr;8nh@23)VC}pUr4D$C928lrh
zAx@mPZ<O?LQ7}bBLu8mLlJ3k9_x)V~yH;pPvcKK9SxR>>WAv_~BZqf~_at}z`(jPN
z5<Gmra_S-NJ72Op$C$z*WikpjewRBisO1`qx5XING9|O9Cb@w$BGlEgWT+uPog&x{
z`I$~Ai0b{5Q9UEr8^UF8wFd;8sIqG1K03SWZSQKRX40H8@%ox3Sfhj+GxY(}eF1I9
z3gv85bwX#ldt(J?t;x`PBxAo@_!jVxRvN)2touprgSkjky%M$=JtHb93>i#~OivPT
zF5gzgIoXqFplZpnz8EFfL+4v3F~)}vkdMnu^IC~415_%~H^>(nlM5?RQpTyH06&-3
zbB||I&q{S*Wx#D1h5j<X0*@_VSWyYdMy(WR0M%9R^}oghUj6QV&C?fQ0c~QY{+&=U
zxGToP!mS|g1cW&wO~EX`9XMS*!<m!q(uJCFqj00qx2mv+iTS^9<CX;5Z_Q5sSf!6^
z5WwryDt%P_*d;*c7l>f0=ei+?%O49fT2(kBW)PU0m_|@^Fg|Swy4dTOWavb#oT76z
zmMYc%T`0UhtTg_1e%C0lqUDqNMV9)c9H6T>r0VAylr$I%;Z@?ew}<>BSZFYGekqL&
z^H!r1PA}d)ja{57!|6(uEf>t@3(?Q-R?=ccYH%m};~F)C<hGV@A8S&AGoJ@e2nsHf
z?M<SB)x)k8j4Bn`LYSP0?jDEYotuQ0S2FbSOBh+mt9Xoz8va_X(A_-*=D{i<Klx?8
zYwAMEFNM{VKYxcwX)a#b@R>Oavjvc&JRLKiXH_QU?bA|}?Uf3HL3s>>LSlw|ik8BZ
zXFY}c0HF01QXE^Qd-R~^ZEduD3dM`xa@O33=m)00h1t|>m?h~2&fPIlP_N^`E5g8`
zI?;C^U3`>kEJ;&8EbozO!tNjTGFa`;tsk12S;1pkc5U^5@shEQ5eMC$RPhZD=W0%a
zh;#jfKe{i;E85W0(YgxT&uP@&(e<sk+)r$L`Wp1-1f<@EP+WX|HKssJ$%~A;iG07C
zpkz=ZG&M9h!R#g@o@kYBmii{Y`UA`mG+6VC>B?^$SVmIQ57Lvq4UEbTHPDf4b57O0
z4{C>Du&gKyI5YH{4amdl*p}!7r5$e%pXs$aUTOsudPis<RSp5(uValO4>bL*#A3ul
zegK1y3eYG?3GH@?&rlCJFl+VSIY8sh`w7_3JdU#bA#Fmd<wYskgJ3*td`1yuQ#dja
z?P~x&`Mu55i%DPL-Zl&sL|dJL?&l6OK0eau2;Y^TT)l+K)?rg&lbjp~_tOJ$<vGWG
z*-omr<Y65Un2C%dUHq8XhuWVrZV{QV_=`EG1t)~SZG!*pXZd$SUZ(t-K2v=nYx7+e
z$nr6Xc$Pa`4=fsz#nXkFlT8Pa*sP`nIUi)s2l5)V?&wao-@P4iDk&SfpB)3Eb`Afj
zWF`6aT;y<um{@Q=z-P%g<73*68SO~wH}_FO^qmXjP}|PGM5Qa0KB8l)L>F$J6^<96
zlk1FrIMD@U3D6X`%Aoz5i`#A7fx^-(b$FpbX4htrx4Tq>@Bru@(A^g81-w~H2@0`S
zwOe16{&sk~7u0t%e#>=&Oore|+5}pXUN-0S4=Wyjv(>m*Ox^v>V*=QeaHPMI^|=Q*
zI99@7#XU3p`wi>Q`by4jYe1Il>iQIg74=nSnZ{dh5j#N?JHC1q_#+_f>&jjGU5`OH
zoANg{Kb~%@+R^<sY{Yez#p8sW3Rfz|&DmrB*$_Ww*ZW6Os#{pBlLFRg4!3+f9<H<P
z(ocpT!-GOeD%Pzgn|bI(vMw1us3efpy_X1X`pOqXkG{Z|BNLI=Al1RI+IM*vyPPhA
z3!O5!2b^qh5pIqq3$PgK)@8XDgYdX9-%fwzp5ll<!e<MHWgsgIG6MhlV5MQ_5wspc
ziBLT<FI84Srs^ooXc8~JacE?N9Rwk;Xh1WP@yjInyvFadfhsgA_~5#T`=)jpu)&71
zF+G?HrUPSxK0A96Ci+~R#fb4w1HcKEz<lg1Efc%$#fJ?8z5K)0XFcA9v49I(2;Ub!
zzjd@*k?0O%AOeWMCIw5}?duHGN<i0_c+y^&&m%1{aCpL^mxePGZ+%<nf~&|qQkDfp
WU?&@#CuN9P?w%6}d0R(P@4zW-;qdDK

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v
new file mode 100644
index 0000000000000000000000000000000000000000..86f8f352c83553a68714e86e8a173efd7abf46bf
GIT binary patch
literal 17488
zcmV(nK=Qwf6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzLX)5bMD+M;Q1p$Wgu;3J92O*f-|
zg8p$zZLx6?tEja5P&NdmG^xT(>2D)OSVNI@v|?%r9+U{6bT%DSX*jwTbcU`wmu>B}
zhbwNLv~lb))@%05dB(x96-~v=I<Ae0_DS*T6s~#E99<KIeQOr0m`T;VpEAn2$gErM
z29l}H`<Z^*JWV%u_eP_|Wl2OjNrF3-kd|7JsSBKaLb!+<;*XC+do0}!1y#&BBK}rg
z+x|$xXmdQdZE_MLjI4)&m_w9^9x!=SR(I3qmoU0qO2HhccX5o|{FC5lP&P@kI(U}S
zUaQRk#*I=lkDr)zPrbz8UhpuSh`;=cLV+L)Q9Pa@{B>cIbVTLW*H|q*0mXG@gO-^!
z<7XQw7TFFF6O-Te2Bk~IOCeiaX`BULe=b8BUDiW-jFk+V$zO)4k}d2|!){v#o-OI0
zE+rrtxN;%T1~B4QG2=7f36?ad2bybt*WS4Bho{tZHF^W`RTPPv+p|3;5}c7UEVfuu
zmPx=|4kMH)tygfKlev&o={PB<nT%MFxgWMF`V}wW2lgJa#Jb_P$Z`{?H@RDa@vy~Y
zD#qn;3oLHseJK3tv0s=OCea<l0Z7{9EW2Ejm8Cfp1y_wvi#e?!N5ZldcUR>~@=x|P
zUKMP)@!T4EgITtbAovpqiH^;~u{n(t{6Q@%PTh8gNeK%<_Uq*1b;U|*$T|Dc&M8lO
ziqXcvVur^~FFC&md4lkTrKqtC%$A}{CZ@R<GICxU6M1MSmPIHA19t3+OL%L~?fzsg
z4R4I0>CIudzlsu(W1KgaflD2a;@AaaD_pYot%gvy6E4z9efs^egLwU;qIGmY2{u{H
zYVRReDOCAFgS|tiX;KN-ZP>}=Pt#F`U90pGx^(bhc0?w;k=zyC3|BVa0kjHu(*hQ=
zd%C?UZF`^wPmNnW{oYByB-b%gaGb;8(#GCsbAW8XVmZ`nB3Lo6AR%WlCnvFG_<bj+
zYz2(N_shjUfLudQ=Vdoth^0EIE(%J9yRbfEM=l(j$HXPx$59MmV_6an^_?#bH%u9%
zqk!2F_s^wc)4Z{Et+ySJ%vBq6ekPMmx4S0WL&B^15s30bE$5fqk0QlBq5-VU;aX6s
z=fs3(RQoVaB-4;&J&RV`ltNXG)GaJ~YoQ7^0drJ!b<?qa)k`=Nknj*uIwx1AYgW6q
zg)q=sij#~CeJpo=pV<rAI1;BZ*y8W4Kl+%iLQ;5wPYgWo%JM7pdw!f&gc;biPK`?0
zIE^&x$Cjx?M4|kF5fAouX)h)bu6>~TBkf~T&%Xa({F!E87%XF)=`Q3>Gkf-fE1UJX
zCq@q8GP`cBJi&+^Z;CH}%x7>Ft<Ogga^mP@wZEzwVOE|qdEADLJ;{8!8}~uU_{x>w
z>Z#-*^UM%iD>%8@uM>z=xIE;QwTky6bp+*Gg+Ty{E^?%+Ue5ljkH8Fjrm;npKoS~S
zb7IF_70h=u`UGEA%rTJ;yJVdSwmRBRLqjlp|Mz!YE&^tE?f7>*#&VLh<_pj(N6MK{
zd29~?S7?I{T)yE(-OM&Oz}3e%Y*-(kYPgVg^z-f(cH;!`MCS6zJ8-9IFQyF;5|OqI
z?%e#v;g54y?jqn<|F3E}ZAORteGGs!0`6_iEYZ~c6;&rh=zwZxPg{mNQvI~q?=7_`
z^tQuKW62JKowjJ2zat4%FG5n<#<l+u<Jz=LX|eOJI<C+}Wo6FSKs-UE8f3y$!enQU
zJ`lyCc=P85{)l@}x_^fz@D2pY_dW)cCS^|fpy1C)?NLYuSo_JteWAV&{u+7Rj(WV_
zuMb_R$UiWQ8B`ls;|P-J3iuFOjCq42gEESWn)7Uh2imfQ3yvL)<}#C`if`%Edu!rF
zJRQG#5$QFG029Tkhx7p-R&!!V0V;k?jI&9rXPV04^Y4MNi9Vw3fWk3MHV|jeCkfUe
z3eMKkRvox)0|c1NNv8qI-)$Mf^<*v+(pvv@&`C8zltad0vkG(Gp7%NF%b18?@h7ps
z%mQ6(RrCg#nQ&SDvl(!7`aGgs9(`s%ZK8WZq=KChghmJJ-$89q4V+Cwbz0+r05@Z%
zE1R!c3Tm935M=;U#yT<GrxyWZX17OEFUMo-50PVR?z<Msr#Kse?aCb;FNFsW4vYI;
z;+c6)Swdt|IE9oc0xPs+#tfrbE(U-6iL5-!C@VN{-Lvf_@Cbub0&iV@i!Q;c&cb$x
z_$m?*fgYXIo3GN9`a@BW=TK?tEK|RF%SscF;IN{_O87H|oG>TTitPvhV=hN{i|b}_
z#BoLaoM{DRwqi|^1{~p^;wg}=K%?8&!@|ndY)4}L-kNnz%qw#T_0l{OnzHX9RPl{@
zmM7*^4Z3NsaE1$!38aB{&P@hb)_mfQ=B@JM_^gJuQ52F|z`BzvVu0rE&SOXNd@E=(
zyP%6+`|SFbjSPg&2h>L8D!%!7F6X`NnTSSKU0bT#zvUD<OEU0z|9r{CoMc$75{Yww
z>w8qDz6#3S0Eyq%Mf`QLoiot2JL<yPym!N;vtgkt%Iv$#pb*pxVikqG5bY>h7L&rJ
z6wG1AFhHa)Esc5~s+Lk(&3}mRm)-<CK??Hg8Wm$Xkj2QdFHFezr@?NM<|kralxtKk
z&c%d6&3XrG5Ke_OL*?6Lk(=`b;GwWg0C2vg-2>V$;?q>*_9^Jy<)*aJIt4;PMjf|_
zt%`7yl>SMW6%!|SB#FI={kOs99h);(ZY>JKLEarYPo=v9p4{6I>dYSEmeq@#Ft8-)
zq9XAJGCCjA3v&oom|;Ri41Btw!+b_M|DM7=h{nk*3dQT)<dl7QSA(G_BVq}vU=g^1
z1ii@q)^`b#J-c;u{XKwVMyfeVhL67*Umj&pmM~v^CDzorKr5nqlDtArO<S}iT%$E2
zeyB63M;uOVpjG8_)y_@~`tYI**=wO4s@MBSaRKG!Fp?duZ@Ym!A^M;EcwLW}N!hOn
zCoS}u<OIl9bm}nN*fbAXt>dq<clOBtL1t&0uA-Ol$I=UUHY%~gPx9w%C+E>dL+;W&
zTARc!X{{IIAEdXZlXLmV_Vwq-|Hc`kKWPK4&>X-tAs5|H=lNdk)!V7s@0skbTa>~S
zf3+irN3)vJ83f9!$R{+-U8ZCf-Ky*eh6??e%tA0q=qXG4B-$5KdEMkb0I1UOQki-V
zcZBs#7VB;<uuX2_l*CY}=w{ecG?3P_{zXYk<L$><PE4fbUv#VfF=nXZ-OkN6B#8x!
zxph!@ePw>0df)KFybc+tT)BA@PMYE724t_`Mq)X$qhwRJFcyR4R8CBe$r}YvqGiWP
zsv@Xb6$NamhfK#Z=j#T!WkK^#4I%OY*8J+Nnj_VEy$)dEXP>|k{)kh$nE=}dw6@@I
z+ENv{N&_(s;)E)+P#pkElIey_3S-+KoU4aESH1MRV-OT8OPD=An}MKuKu!^AoIlHv
zUx*ySpcAkT-cuJ20CJnVLa5HuY8jD|x@{o+QTs2I#BQ?=DBzp!ca>tXJW1Rk%g}RA
zVSurS5OJkq!@-C8B`VBSP2oeC`L~QfZGeY_wB|jj&+W67NTV`&V@~PboP|bfi<xjU
zzzMa>c!hwS4onoqrKcWdFWiA7k?q*6;q8)WLSA5ZhOU1_f-S~Q*cNDR<BADdc<0qw
zxnDft?gJgYZ#%LX8FYl2Bp7XFZ2HT_3Nx41q7YL-jy@LduATIA0=jltB!UEWVJ?ON
zi6?jZd8RjTj8eC=ktq^7bJJttxdwLqqL1Ot_O!0DZ02^K(IOdcLx4Fw4|cAD$PVnu
zD2Q}-d|#PH3xdcNL$B8p^!o_K<$OsYLteh{Tv-#mk_3M8l=Z$)EXR<NE+X+1Fw6lx
zl7q4W@cDV!3#Iu*1vui^aT!v3eSOa67YK-r`Y;ae7)|oNMx4n-?$!~<%Yrw%i+GiM
z7iAr$?3)J1l9yCI<dP<OVox}-aE>OK4dnGLNps;aL>@?APeaa#Q%srj#;Pnbr;bz@
zYlYp0vx+yUO(;*E@kd~zl{c?phm}gMxk>8#9Nv>Ee=<~e8d61rM1ZC)PrHXE@Ey%N
zo+=nIYQJpF2U(IRmp=ZDrOpm0*27#2i7CW3Ha7y9$<)eOJrNx>@xE7au|3b=G1%yb
z0Knt0iE40IK1MAMq_~RRV5X)s`OSz=M|FxOP!*zFuC%_CnphIdxdWo&@~#Uor9j8x
zZI3~S`kEBhMtI>wiq+o+_l^c&32DhJGqea|SMlE{O*(BWeKQYU9KPwipz6zt>&MS0
zT<SFY(5sm{LSg0q|2mm~(JEm~))>?>9qsTwV2Bb_mKt)<CR0Ab`R~Us-X8VC_TC%I
zAJPj+13;s`)$d%5mJe$INmV%>RAOlGMM<dj!U2{Dtr3lcn;q;XI!K@<=5c{B9vX8-
z!l3oYIbW#b20*P*HoJ5qHv!O*4u~Yl|F&4liy!DF!ml`9mxfmCKgzZa(EZPr^^a8r
z8N&#SMCJpE=|b}x=omO<Kf{WDA8+ws7X&j&pch77xg4p&Bv-?ZrXDkvX2$WHQ}Vgp
z<nrpHRVnpp#eqxX9&g{h9#Q7f&@Q>sFf+?Ios45q9;%<1!z?0f*$<U{OeXgrhsKl7
zJ?r7dI{WJsfTVA>L}boO2HBe2fNGDIhx*eg2N#tzRCJE<5bN-@4-0?F1o*h(V?J$|
zmA;hhX@WAN<2dOweZc%oKOyU05Fa7-&n`4KxV-mh`-MXs3%E@d%n8#9uoRB&wI#V?
z11180Ml6Z{PMiO3I3{=K=eDv4bY=?3;9&y>Q7IeQMv&!o$c04`z$(OSPT(aS$U!TV
z1kFn?C+gR&L)4(LwKNHmFZzVA5msf71uN2(+TgzUAt<H?D|?u<-GRYHR|Ed~PU{jL
zE@n%lfz>n&YFOx)ie_3os-5MMs2J{pJOdAjOvdp$J6~WT&j8{-T`xE*9N@67kq_tf
zZEZ0e09A>s?de*$V3&T7cCnZCmsTmgFl;6$H+^$SkKr#63QD-2&<~^ta``~NMMcON
zAT0s^NMtJIYh%?3xP`AH*D4nG72OZR(N?J}|J;Y%eD|9~caXcSd|AAP-+$wOg>^)Q
z#3*4Cg%BfS)HR!nK17exk(Ui>lQ!Wf`g97ZA$t9b4op6&_pN2kaic1`J3a4|%OEb7
z<J^oQ3=40i=0-Zp+&7zvmj#CEBc47gN_SPmyB5h2o6BHQ!}}iaxcUpXgTh|h6ZF@{
z&+;#x!SL2o*xvUDr7@S`r0>g-fFPx|*RC!{t^(EC8}QR>%|@_80j~c#tkW5gdGJem
zO6Z(Curr-*snLsz7pxSbkZtmIAbZ>**>oMoM=^JU`2iF|RhDGhJj80BydScQpIRCE
zXVplExc-5D^m?{wNBPd)c(L`b(wdgg&|2XDQQlDuBB@hD_E|KmN(;sbF=phgfj9E+
z{dWgU|N0Xv0P=#9jOD`;nr)e*8a@*hH~bVG6o`OJ;5XGGF3z{is*@Uuwu~^SOtldH
z_|ngh+?>}`qT+Qy1IP2~>9tX7an(H{m^Dgk!T+e{)4GWF2D%+EO4$qFxe{(8+><Gs
zVAKgVsx!a`V9y!J+1?6YfM&-)d--A>MlJ$K=B}$^peDX*?&ZJ^43_HLd}$3m{4g50
zdAi8+F5J`5c&E5q$*>{GZbV>hvAxs6Z)g3$Q}*4|T05$`=!Y$8k<z9e<wAM?u9xi0
zu;acWMuf}W{Fos>4XcprZ>*_7W0H-4EI`A1YJ*sv0g7>l>C8t++boOdr=H`^5{A;=
zK?tIw^-`XBx9Yn52d;<MwF+1QyvWpb0RA-naEp0kM0k{$_@Z`fi~YkA1t{CieB<ua
zARl8fpTo)U(qZ(XgkI1jJE_bWvdd@!C3%4{q=>xn3+xM1_nsB7roHb65og30OQHxs
zIz$PYjhj!cd;HzjIeC5{Ib7US$!EF;I^5eBIXR<_G3bJN!*tKh7F7q8LmvkwYb`1|
z!pK2o#?t!eX)oz+i(EhoJ=L7SFE--jXkOL`RE2tgG_OIL95B>hX>kX=iqQk=bV{Jj
zn+WHb`U0oHt&5`b=;m+8WF<trqTm;@&n+2cuOttCQ=V^lNJguKjhj{^*5+EyIO@TN
za(chPObDm?v?w7RG{3~oi&96oml`jPTV$p>ZbT@5A)VYVpK<tL-)st79U!bg%ew%t
zIi&S(FC@Th)J4f08Vd!5x?2-ktyQTt2nj(jc^5VyaDNzZ9t~ggVY{m@Nj8Q7gz+FV
zpk(+uB~}^ZYEaFg;<LT>&xtAA@CiS*7#4Cp?^rN=E86b5MwNvRDcsxb5Fz{oRFbnn
z+&R2I2b5skNQKsgmRyWa6@<pC=V7yslUTeGy1(4tA`bRNwwuUzpaE>)wXHD!V@Tcl
zWOefQ500>rv8=B9GXCl4<4O1|j)SLtVE~E~SHaleM2_bf@x(O8s^>KXx{h|raog{>
z`?W(^XHqX!QiD!N0EeM9Z|ZU#ZPkTd{^AXfy}qx8f%*s3j(CAvqPw>3@4Q24@S+Oo
zrK4B=EO-fl3pIciEt$Kpx{<Uw%5dDwD#_!0v`+~PvD}8XBke-qB~sXLXmsd*cIb-Z
zq}K&e*6&R^aj+=DV*o)gq~|uuh4h4iK}08jsUU3OtpGDDs>bR=AXr0lsf<Q79e@hj
z%^6&gd8y5jDPH)3?Z~eo2=O8`Yo7?7=DtXH4Kd=+;YFrR5C6pyH+Y)ZrBu>9W7EM`
zJ9Ykqj;czW5c9ZXv6L_l9mtp0vqVUSWv5?d<5?ePwTjE7(fp^y(bBSdDCkm#q|HeO
z@~j0j(v;gZHUs#cK9NLIx!Fl-193@pBJ8i*;e+o-iQMrf{*b>RsZ)Mb9ptDwLm~_4
zCR0izyYhKxaGTX*xb}Wv33EfHFS0YE{Mwh~PyKqYbX`3c5ZYhMr(^XAoi{^i5E#vA
zt0$;;C|WTsEuT018Oej8ERQLaR;ke<oli#$Q_a7Wb+`FuZWR7b*EBO{fNYYi{y;EB
zOzv}$Te*uxWxgoH=fC<vgx2?gBn^%th6v1mEh9<-gUmT@;RO%*7KG{uiUTlI%8n*4
znusPl?SeHPCV!hW=H27lP(^~(=K-k*SQEI%W${MWbqCtC7K0s*b3EMkddpM=7i~AF
zHi(>3A9pb%Mm0-=bi=Xv$B5^xmO$_3yHBOmGEDsowm#_iKMnCrHz~pHhSPS4S6O=b
zj=DtBsH$M~Bla(ZPEP*NFn1f?m*SZS?Lwo?4htq?pKH|xElpZS-RhRQ)#EjIn#(}K
zig=VJFgWibSMZ>g#hwyfouRdH+@L&@2efk9^=@gxt<1f857mYx41rIeZ_6`C!G<~%
zvnx7<a6-90`BA@*%Z%`te$po~y7Bvon*<376ndeoyvM>pVBO)IQk#kX_>W{Bc<yv!
zi75txbL;PYWk%fZAxDM<+<8{{CR%=)`)0V3JFZzTz?^(YSS1aG^Q!NVc_m?LMMp<*
z2Zl^3eUDF&GqSi$)JTpeA=L`gdX*`=-0<&JTLot_QpWaus`os)0PIszyQs!!@o8jL
z4Zc8?9O{d?AXBbGp`UuQ%Wjj+;5!g)FcYWq%d2W9S%oM=x!9MZkq-!OF^f_si3hCE
zg+!{F5l<-NuGTfpbOo$lv2UOf%ft%SpbpRPZ%y&xdfT*Tp)&I@jdXGQtmKSfkZ}o*
z-v(Q!>sOrIxlSN!RvPKV6HOFRg#R~vRxsj>QS6U>+Gk84yySs4!Jfw_(<#Z_@Sb!H
z?YlR7!NZ9FOd_@p{UiE9Q=ZbRN#YpU4qsPjWZ3oY@iG{xH1@iIo@8=t>~N+*ML<d~
z1q@m3TLdG(_ePSxB;;SqrF%)-Ue}kH{45<ZFgAJ)3dZy|#o`j4(e;X+$q8DE-WW{5
zdtfdW3uM$8)C+vOOrKzHVDq#28z-@Dos7U(-pdD4Y&m#|nx6?{c;JuL$FDN-EehiF
zz=dKHzcOow<5X+-(C*bQ@BnJ7p)w7QfGLQ;Y8O3BHT(7J17Z1~f&ml?`{++>U18$&
zL?j+6L)#LoBNZt+ccL;axO}7^oFJ0hgVHs6kB8%rPKfJ98()C6BI^K6&sN;&SHQv?
z2`jVK(Z}!Wn#c1ms@F363yIjktpsl~t?*`XPj0L_wl0jrosO@}Ku?ZEX!oeXX_|c&
zB4Xxn6vM2%mu}yx#Qi1-t?{|xJ(LI!^9$n1H~+FoMiQJDoKUtN)h&!ws;Iq8DE2d<
zyyI=AH8JFe@@RFP`u9z%qhJkkG+mBBu@4FY2=8llhp~-@J2G`i5&{`WuuXZ}Zgpa@
zL%e3GF=+}~XMVo<xcMK`R5s6%n<g0``0{K8mX0En6i3X__h%`qT-165*GTUH3xm8X
zJSTfhf_(2;h#`bYU*2xUH&Apa*yrHdD>=%e*Uu@)_s@$Yr6b&ebOobibRCK_F{OkF
zt-Pg+H%2-0E-cf}>c?vV?o+j3bLZ>}H$864!|~{%Hxj7D#K;K7iejY5@@(C!U15A+
zHG+OU&_wktP4K9K_;a3Vz2Fzewn<I$jEzX3J#B*%OWFa@9{VB~j=P0Nelp$>9Qa%!
zvPL)A@{kGi;T}cxVK&*`!STezw%bt<&=@+r3FK_Y(W8tauN0fC<3?iVUTH_}ov^`v
z7twvl(9awgraODD67gw8x(<N12hu3^r~Nyc)_7K9tk4*2A3_JOZ3eYNrl8<w^s^V1
zKUg+PR6H0Etw@Pjz|xClBCv_)Um*lMVpPKcTg--v(~UE60L%6+>3?PzAam?PwbWkR
ztE)Fw2Es75AgK$w^A3US3%VDAi*JMbPV+H7JM~pw81;Ml!gtYxr5jjIVZT)6%?8ZK
zg}<ZRV_bj{oNiSxMVN1eLoIA@p6;b*c7h<iJr9gKRwXFx;Of2>#`5@}4`j$KF>Fn3
z)6$!Hu29=xkkp>*hHv(!D@|nb%s{W8DX`_UFM&ON$A~9^PecV--K_eI$F9dBiONO+
z41MW$*druqN<9*c`X1aTJ?vS|hGnD83_8p2N&_!Y{+Ae6mn81c32wocc^kk837;Go
zS~)T=9Jo{>Pbw;JCF1>w7C2tTUtl#IcfhhXI7}1gUA5Etq`P6Ylo!#XyGXXJxK>)w
zdN3ZRo)TV7fAl$RbVW2OFvDVe99;&tLBm*@xOR8<=KtKSEi%}F2}7SyIa6BE@MCO6
z?I0Mc<|3K}b!;^)>zmhuW0QV{ChSD-I*ifP;H;ZPkp4oXXkwF<(y^*En~9+p=|EiA
z!6sge+0<JVMEgVgNTMY~lD)EETE&#iIhhj5pbo++O6zuc^4!XzTJ+FrV}19?FbiM<
zYm0<TT=q6|Vlelg-D({xuG&Dlx%X|dfOp_4wttl09EAP685q*wL9rO`?h@n49gYGm
z3Jh(dZ)0jIIN<N2$8J_-!V|kYBT@x>YRz&%<29pGrNM~0wq5oj1%J@;QaH<&f{H3^
zDnv{VWS{d6CX;8zfx=?9f9J#BpP@hlAGbIe3++H2K~4I&{oi2s5^^bv3PO1=ITpsC
z<&<SbE-qkjLu<0SeDxLVNI#E=LxKwfACBF7GMb@%?*A|v-*{xhkP_Z!i(!8?ryK;h
zov^hQ?2uREVu6$~1-DyQcy^0i2H5$1nD$*50&jHIssVchZnJ7syp{WbViY<3(d~(%
zQUrGBWD^}(@e*beCl4hSe;HlBM+O*(Ql15zu)%>A5NTI@eEbw8J?5Y7D6KlGZ0RHp
z6YSn#Iqo-XI-C2b35%aV>)=_$qBSgyOg9!7QX^n4&H>YsDO4Dm<JqI8^<5_`R4(C0
z$TKduQ#ZMKN`TJ78kmJ#+PKUqPgmLLk>5bdIAWqS0WpJo_R(;?h15v#W)92mtSdC5
z{eg+5fkihNgI{|Orxh*3@iF+aoLzjcJ)z0~p2b0ihGO)_ejH|^uHUBI-nTcC!4U{q
z+y8X!4yC1rsph{E8AwVT$V9##=kNJNl%|hq$(BneH@@i*Z#&pp9Nq`j6^;90^Nt6~
z1*AIt>HOfJtsT?pVIn5i6CktxRW%qp6fjyU1>m3}p0K`UQ!JXnvzo&l2PPP`Py{a#
z;?J=AkX^vEji!I%XLm3&yTZCEqp}6kY3jLcqy>}#k?GjtD`_W{*Jn)dIo|buU#j_6
z=danBywyYsUD`oaaj({W3Ei`uTFSURvj5-P-*l{mR-gdjfjA^<#&<2?5tS`|BsV(T
z+>=j(gaAx^)nN;vyrHvNMboTg{V=D#CiIWzU+1b_V{totYm{WV@cLF2CR&in;aZX(
z_w&MAr?`27!22)c^<^|ke#S*8k}(m_E~Ci|M_cFBv(D+t@f&7&bk(-qf{@x%>i!27
za<j!yM7uezPV|^z;6-H5^e~M(?-paH^}#b%?O*n0$&U3WEmeZy1^>#&k(=t`D5skQ
zK^xP6?D=OU04NUCEDPMZoCZ7ZTO&>w8x!Nm`P!usDNp-eh5*~W^B#I*zMV~mGO@z!
z)xH)v$|F$wzAYzuzWoAW-IPd#g6h(^CCyuji48el^VMh>o_$-!d`+z705yA9YE7oO
zpdjxl_jn$E4_yeA82}gL=QI3VQG!3k@*=htw(gVW9DAKRNLPGu*EsIBazaHdg7wUi
zmFeFgO&ax8drom9@#UQ*&I*v)_4xcBvLpd6WBOWZ^Rd~DmXu{rgA`*80*9ZlvlQd^
zOrV(dXc36+w6{OYvkWqJo(?LHzyLAZ^)Rdfv<L_z$Fbp!@R%*9gxAm<XSq|L+^{I@
zwpgBn-g^fgW;RXznuf9s|CwQ|#F8Gola(yt4sR3rSfiXm5nF#j?b(C_Az_9JA}McG
z;yXD7p)=Kcac%ElsVM&gRj?UM5wH0=Bhd&-yApeTLtQB!;^N(tqRD>C%KPo(G^*Fx
zqz!G^LL);$?rn|M!MS(Mfd<iHUS`?boK%<Pkg?kBr-{EX9=<n_q>Mgc_NFajin8J}
z7c3#2#ffoebqUeKS)M?k-&QJ)_uZB0M&ac{w1A)U;u__|@i2yi#C+4H6N;?pnh_>T
z5!p_t)s)hwX4T6kWKKjSWLcf`cG+8Ybj+fB76I2`KK#p_e;R{9#v6xrSKAP}BDRL%
zb&fsd8P%)f(Y*i@ChOK@U71vggx-@kYjDfj;aSmXUz~PF;0MufTRNy)^8q4BhtI*5
zZ@N$Ef>znb%3fous_q5ng5J)&Y4lG+!@)7paan|6cL#J)b=!$e7$(jl+70?3A$v7@
z>_$)=GN$>0PvufW4<`~9o#Jx+L`O6#qVw!;1*bW#wXt=rQCbPKk?F0aCX;4&v=+10
zo<a@dX3@wdcEn862$zxRbFo%%IBm*$r{=(3baf^DO>C+C?b*W;1zHqEEZnv6fpznf
zX6(5mJKn;oaImtbA~~hfG>C18EdppsBNao15R8>#72)>mRa&J*n*YZK+<#$P)+&en
z#!a>YAcTp>kCb43a=EE*m+2!K0(L$#r0^19X;4qA^bXe65=1}BrTceB{vM*%7$o6~
zG7%)IDFW8+5jJ>kaJ>bz_9-xO4e_=WsWhqfcMx!rSsI8VrjxjGU=ii!RgUDa5+J|Y
zoB4odicZBv{}lREtf1F+<r6yMWren4<^=y^6SzA?$(;B#mIc-?zjMNUezw4x?k)#P
zD+Vv>JNa4x3h~1gP!a!<K8@on!&>wFtn(B`4u8dfo4^KxbOP7r+<#=_70uRO^~o2N
zr=N5(XcG>{NO2YwdWwM!JjQWm&eO%{=~bFE)@yK~rL%?$=O>%-coQj&dE;7qT`x)3
z{Glc)9Cfqa`*NUvUtos&5YkIH#`Q7YNMYUZ5gzBP!0h<2VhxRMLch6k@2j7w2_{6~
z-+ielEaw7voRo;Kvm9Cc&0E(C7oali!gno4DRc1X!+y)Ps%VOmi}wxhC?^2v6eSd=
z43wXLuG9lP#hBPl5K<jWH~rzq$QZbX$iOlI$gbfYJS1j;i%9r7i1sE>x<!<$krk8^
z8D@s_f#zhIFCy-O0_NtbsGO!dV(rv{N^`r-G*pmExTF|K(lfyDx{fG8R9c<58j@-{
z{jpW!kwXD@=CHJ5U76Biy<T%{G2>;Mh!Z$KI+QgMcGEi@WvSJ&@hsF`Y5~M7fNSIs
zUVG$?%APs~_aBD>^z8r=1Es#aD@Na0!uqjF(cZR-+SNW5GhLXx6F+!}6Dtvr?MZYK
zL|l3zTJ6>358P)+`f2u11EB6)hbLa?XBS^J0L@`rV3L#JHC|Id>u^aalvYMKg)bD@
z5jp0454&rt^H@^7pbXqYNbR6Rb@C}(Ol8<W*AI&v)m<zL61LCeh(FVFj$Y%d!^Afi
zNJe4tWgjY=Rea9bZEftdpjc5tYMN{SMd$ewwsTb`MTThQ9CKpE`NmN8VHDiOvXHPr
zwI*%Ed9CIAinto9>V!-TRTIP{ZPt~0hB#>NhQ0jYs_tYxAQKV=w@toPY{xTZRaUCB
z#35=V{$0v;zqaRBO|+27S0t58i7erq3pzsWups?OOrT5^2hgsbWJ*daDai(E48fTh
zl>l?((==XeF<d?ZUBu|)lkj^;xgs+R(cg4)isJVcH4t)QD~aMqv^+(%^ahbfwX#q!
zvuC`}2;XtH(e?@>&@d)5Q0)0py-2yq5YLka`x>%(gQF2@=Q7eDb|N7)bGC=#J|xsh
ziDnTZs9{<;NNvnVTdGP8mXBb5<@7cqX|KHlHwh-z^K9lCIi)Bz6cMHebkC)f!+~VJ
z16J%9e34G_2V0pbG%$Ca{({f}AjeWjR-g{KuQ8{4-mjnD;?LVyFzxDZs=L?1L*+N<
z^EApgF;*57ekBU1xx0WvM%jSa*gbRot)>Sh9#}FnbWEm8h(^6IM(w*SA#?v|crK2~
zv7V=~)A!P2CTblE0WSN>T+4T_%rXK7b=F3_of9U1qR96Qb+D@5t_acquu_;bgU$O{
znriO`*0zl<qHFWFmS-&oOVAL>Cx)HNOW_z5CQ8O(?KmH?`>gZ^XS1+v-RZpNr#RN&
zrxNTf?*Au`?Tg4YkFeYM+EM>POHLuao&Ks=G>Y-#af<9j{1QoRlz~BbdvaQqLPdO|
z0w1}>4>y@zQGQ3Xfn;b^W7ISD(CDymgQC3^c$i`huf+jPL|*H>x}82G-TA?B#fW@A
z6mD6ZFhBs@SV!;_B|^pd)VjZD=veJP4jdk(nUA=-a3I}&+(f~cdx=j_wtn+-k#NR@
zJXg5TP@BxNyW06udoEbt6sAiHhoo;^>Y`i^Rs_VB#kJzKoQGVU8yK9;wtsu!zQHJ<
zR5=^{FL&1D55MYv8{2-0mj*LO=DwHedIo&<q@w*zT9$2{j3ySaV&xI-8dt8}Y=qA&
zYAbCJ%C@NDMY9$bM3z~qWclwFD`ls>(Ur{OFOF1)T}q5sgcB&nmI?=|7Ly2bCdzJ?
zpyC~DlUmtnCkv}4J69$-81<;u9bw9mx3+!PepguTP1HP+++6GHo2mHf5e;(a21D2t
zJi7=OKqCVu)Z;=BYYH23OOD>M$2m#iZZ~tH{!;T^Z;|3JPKUlWkRlh{3<`JXL(BAL
zQ1QF0D?Z1aY@y%Y;8)t7NF1|m$#m;ak;f~VqnamBGcqP5_+5*&*OK;<tYnr4zv#bf
z!1^C;R+L`0%y-`GL4dFE^^W9#;b8uUfiH;R69M#g?vUzwl9X2|V9REVVC?^T*k%7W
zrV(Gp`21Nyfxq&X5lxv%8vvnRDfBfvZ_+nRCHWc@$c!fR25r~0#Miyci+N<T;-nq4
zhrzH>71`N-BT~wzQ0a12%=rE>8-0c8Q5DN4#Ry3TskthTl0OZk7}YkZ6yBf{)io3e
ztmk}%ghAFsi~`&kru_HT1A!PB^B;W0y<7FZwKkvRzHT=kr(S#CFF5d6?)mX}TQ<d^
zmXSrzPR||-`#V7sK2onFuCoKuEx_aP!5hyiNW{~M(2*Cs;S+gcQ>XoXC(OY2=iT%j
z|KmhChTQ>$lCiZqT3H<Iggi<)-W%X$jkA)1_r(iu7V#K|cw*XY0EwH$!GIn$@hW9w
z11D{~6MaNR_hDavw<H=xvorh72<$NPXxqzfyrE&dpuNyA?{P}HR-=xVa>|Quw;ug$
zk4f7D$U|wUqfBj~D9z_U_|h!E<^enVm@Hk}&+N?*N_>2{)?7IxDWRY=(2@@AEm4kB
zuzkt`aui>3<m${%AZa8S!M9z8hVs6)llB~%5qJe(nxmnjx3)~}dBgk8DnZ8>bc7(%
zPX3oCnYe+#g6ucVMZkYYeD`BExCwK4p$f*+r#mlq-ew?3%YI<3_ft1gt9aV&KRs}I
zeV4I;rL--gPr#NVg(Z=*{6QkFx!*KyIp1?Ks+6Ec$NN1N?>?vhG<4}(-Fx9^(cAf{
zL|{lLAs}1Q6N^U}iTZn-|6STR?=@=%vn7rOel?;RQB;=hf$v*ok_rd<78a}}gzisa
z_5~GgT(a?JOc=nz8EHd=k+4loEqRA3@RVK}va(i0()##9miq!4h?V6J^S*fW<!7}E
z_~+~;BJ2abVgx&hDVg4uxp+NTxBw2Qg3KS3N~+U0Yau$%nKZ<6q~R#;V@*7MlENW5
zIe1RuMhT&1f2DJvh$-%BcJEHZz)eY*_Y=mHHMdX3&64n?fE0~3xKs^D+YZC4VPmk4
zaWA~sNRC}-T^5v!sq6AaZ?s0N-<B5(U-=3M(A!VoR%1ORNt-ie(E>c9QixJfeYY&-
z3_<(Y29+%Yt$OD`y<SdyvEf)oOhh}*>-NAS_W&+icUOM&XgS&no>(~e^?}LhVrJz6
zQYug2W<@XX8zJ?~6ZvT>dt(UA=_IBhxE=iOO7E}9y+Rk|tTkwV>dgMlDP|xsOXxZy
zI?AlHbJvj4Y1Z64J<IcXS7lB}l6nM4l-a&9YP{C!=`ITUB282VMEhwIHPQ|gxK#L&
zZNrfLsT3mn^pdHIS$M~b=EO<K(vc+^5uxh9^+zz~Pc*tnhmCn%K)w{)xNLUOiSM`>
zBv|<|?Ej`6S%wR*Dr^duJwuJ#`oEHChI59vqFs9zLLhBL@sEdc{W39_%5XZ}3Jc|G
zjp_c-PA?&hzvHhAId&XZ51VU8j^y*Wi#}H)hn}<9Z;|tQcXm5SB1_r@g`@4pL9;+e
zIHoW|JD+PQjY0oEKZifUR=C1Z*H#2OxBvJ{`9zzEQJs!4>?d0eqS;FkDbUevgo+ah
ziT7qwnTtZ}8EJw&s!~n8ze$f<S2@)hd`m?du1xIEQ%8tMTJ|Y)F)VRI^(l>h6c+z<
zO8)GGh@&Bg6-anexts|uTMihi{c}*~I(>Je)>ek>X-lPNgk<qF<w5~ypoAIp6=X}s
zoy3KF*zNn7dGma1nYbnvO;J{ZK9jgBb4!RfF=ivH1gskqfkdn;-g;c2X&@XY&n<CC
z77IUOu_8U~_BM!*2|9$Wq-1I^YaEEO(>Dd9)Q<6$&k5A7rBCHpB!D^he#P(cz#Ru`
zm|vLrfU<yT8f_L~{yi^*`o)bpCVS`JY#+ti_Qf!N82$gUcWm1RXJ$m7k|-@I+$~4F
z4=~ia(N17uzkBI}&fXFUOOSk-2N^o*5S*$(<1u0^486o(i-I_dr{!4GZwhA!@SMG8
zxk^v!Hi;~;5vFl5>fQN5r9}={-wU4;N6_dEm9Pwk_uM`Xg`S}Ui4Qi=*&I_Rj$web
zz4T9yojlbrwh{-DHIF)xQXZbi9P#@4+7QX-5IgWFB}3eSa4GFnS9A>)0#HF6gHG{1
z0!tG&YwXv%pMmwwYoDAy!ml-4S)mY(<j=e?)c+W~$<K2}N?<hF^dQanX@87`IgRSD
zB}Cm$8LST=)5DDIpl|`+N>w4ck)IWDMa2IW!&)^0=_>rT;>AxneWI8BV1@H_Q@-S?
zT2@NoR-!EQ<>d@3=AkkIYeGQ5UUzT;R58(@>*CZZT;wa=9$i=*`PjE+Hx?>n<N4>p
z66z=3H8yIL$yl^8xKNo%H5LMmnXQz>N6J6pnK+5ojj(4Yz%T+_>pqc*2-2zZ_RDVJ
zre*w_c#ZOkmapH=7iK~p;@<l(YL<!HZMV8Z0jB#Tl37Gjk<^pd>gTY2tWYPaEHZ~m
z$gfs-F9?Wka;VNXH6<<xDsT87doo?h&6z{*7l*kFlI7xmhG`?gi8!Y%8I1v=*=-=)
zX+bw?qVy+84=G*JrOyclS8Ixh-4#O=mBVn;epT~;`ps1Wt8K^c>XK>7pie}rwByF;
z=UmeIi`G^%i764hbZ|wZ;}-Ysdw=Mz^PNB<fk%Nh1DyI?ID9i6IVh&Cu>19@C(p69
znf*IdNIAPzdFgdQRx+iQ^kbH+1dT_di@MVN(qCoBin%O7!6Aw_Zy|DJDGXVmpFjiU
zHjvZwn|FIUNblUgPIdMoEY{m{$hqrtGeiU0%|@)uB=>~zFU^WmWZNR*U`*}D)NAHO
zv(P1}2?&VgqCGk>KHo+#au{B<Tc8h^O37DhL;-&)k96B_RLz2koQ#1!d`nSKW3cCh
zZQWPoXwynS|EmCC1zQ^0faWwNAy1XZ;>B72Ijhd%&8xbY3h`P9sOn~A8o(VTBFAz6
z{e-V;>|Zyjh)M*IY#AZ+irf6FQs1emV_HIOtKBtr_K^g67qw7y90g6Qog#!qOgL#w
z?(6n%s|5fqL4sGoRB)XSn!_ytvpFjB5CVw~j*3Y82^JbxFiN^~DGuuK6~B%1*WT<u
zY9*ev+n@Zd$iUKWWM5@YuGz#N7v=ARf#2Da0K+qepU6xyBE`Hjw13AnWf2_O5v#jr
z-a`KYwg2sCs}A4Yus<THlQXnukpSo3MD>z%Ux)%}3PPAZ<#H$p(ic|KgE+1o*Dmkv
z7C#8aox=eLV0IERr_lS%zus^KD<%$Vx43^SlKaYbjxJ!-=;-Dcp68BS3Nt43r;2b(
z|J0IWR;fSpM+sR3-9(#9Ry6lGhCiE5yi(+JY|QzKT<e!LO`fM2w6>h6GlNY=)g7B-
zuC5~)^@Md0a~(d~EcHXFf0!1Law~|*JB&}0KKlW+6Y1iw5J0dWkrsbHt#*Dh9cRmX
z2x`oAiWNr_Ul3F|Jl7ITsww5XdJiH`HZ2<UkvyI{H&&G_=D!%BnH}Aa@7@LN?t8f2
zL!a)$4Py`G<pB{bkQ@u#cdM7*WNSuM#;7jN=afx!pygrOKSG@2`Xs9aJ9=6I5~RFQ
z6_jdzQ$80xhqn^uWho0N)g3sJK~_}u|70U|tu#n41Gc+<Z&tP>hQ(YvB#s2+q4IgU
z`2i}7`(&+RsW*P>w`x;42zA>dCFD_id=FY|6~nm9S0pRt*b4z)aRy%%LAbppuYRQP
zKA(l$WPmziCjWma04BOOo2s`ArMtx4crgb%Ay67EX>XAuLC(RPym9<+dzcS7S*zR*
zjrnV!OqV+et`e%WMWy!Ijj_bX>i^}_FJvXVlXX%dxWxPid%zuFbpk;DEHrw8&kTd?
zWt=iqdaR3n+ITtXWPTAO8GnF^eez0P3>%gcNaDG%BsOMUqC_RjMXFOs2hk_wCkfzB
zjqt-#o#rxOIP?L#<x}|V^IDNb#=kJyt*)8VP9rA0mAzISzjDo}yx<jYNYg`eaE_Jn
z`RZKbl+SOix_(<|j%LSvD{=NtI{fFKz+_7o8o#7C8Dh0Qs_5Ja^-)BmBE5oaO^;gc
z5M6dM%%s`jS8B#LudYoEsqwm2_P^p%9%D6UlL940H8nt@#D9X;%VO=2A6a??jWkPU
z9GqwrDgKwn1dYruIx?OnIRD5hEb7#muddVg7aO|M0ypQL?l2es4Q{R@Fa||_O0dr?
z(f*a8U3+Us*$ceaF?=p^P$5AfeHmJikvTwu6n?AbuF>%o!FU+6N(oTIy@Dd*V=7Z7
z%u_B}O_=pHZ@8J>vT$ptGR~knUI_nt+1#~!4p#X8rvJ@KCL7hPTsx^gHh;|J<rg<b
zaUfy>o|Zwrh_wg=xc1))U;=856zU8@#%7H1G>QSla&sd0+fc$x#alvNW!bECX$7X-
z(2lrTkqMVq3e;Kb<sN9$QwkcBKr;+0eb_@jf_$&|CLWzfGg5{iGZH!t0TFb|xKhU^
zdPDEnQ?Uo}{;bSEWGwAt!n$5jctaB;tRmBLCAPXsH?g6Ztmq%zSfEQvm2-3R=tUm_
zzLjlFh6@FGsH3yS_IR&6MTwr;<1!;@^Vd|_cC-s8Q!Sh0czig6?_BqvGic3M#$DD}
zT@UzbCz1U&OjsUlv}7j8I+a3wro<taHcTh7CM1XS%y}}6iBkVDj&ykI_C5o+t}h~)
zHU~iElxBiU%B1-P>z-xPRd`q1a1MCz$~ed*=YNeBN$X8Eq)qMF@^rf*fv$rkPeEs}
z4T~5ScTmJyp<lFx%mxWg@K_|jE5k-pfBuSneM;&>sxNDu>g#9K2e{IzBs+3SxB~B+
z=&vT%P4kH$0kJUMemxo!qQ8IdNnz`}Q!eA$2=Huab4ooO^eH^yAafQYY)!oS_|kT*
ztxtV&t!_elzEX$`59stlOUJJPF<^U?S#*<#5IBU9Y!kEc-QG7(ATJVH)+io-MDfFo
zJ8ll4k=vsN-~HQDUH9{i{z9;^@S~3A82(pV?>wn=@3_rilSHUBd;YOpBl#C}l2KSW
zLB!i};tO$zBUl0smc@JDtCGXHsLLWTpr*8)K@CSD)muK!5{p&psMk_%%72_*hTQR~
z?|b7dVsrQHh}1M>b@WF#cwR=bJeM)Sg-TMsZJ9R$7gcwklvnDY#kuu#(mj<SW_Fm`
z0p>B}-1{5{aZt7kt*2;0v|&`}R|wd~U60c#$!FQMRsH=JdA!l;WtcgM)`W>N*L(tI
z!c7|?x^cC?w|m=t-kd49-d7y4`6xoXeB}6rY*R(CN?3wMd-Bexu6(ItpP=`EI!cy~
z`0mHs&b+FvRZ&^EcY7@vj~Xk8Q+EoLx-b37r#3VjKdW7?qqSHryQ=mcN*PMR`@IUl
zP3P1_voOmq^yTy>o$g3mGd>NAr5f|sdyvIP{{+$<8)8j_+}{v5(TN33S-=T;Unhd>
z`-7P;$e`*&kZ&{4B50K~4Au+KaH<|6yK}{b$z|MkdSD~hfu1`Di|B4Sfa>LPZhH`2
zR*g86nW1Ws2<p0t;R*N`{z)>C-W7(beb_61SHv4HAx;{V$nZno`R=Nu$}8MM_)fV~
z=(agkjx14nqdJ(<HCkQ6PKPh7e8dL1x;IAtpn>j}ao$hHZd^o6sm)Edu#5iApDNSh
zb}rVsf`uIJ0RuxRf40v~N0c<hH@x5e0<2M4A4LSucT_kI9-J#b&)Y)BaHGgTdhqGC
zf^Ra=qhAB_$HaNjr?B!V;0Q7O>d2)Gkrha{`=P!M^kZ>_=G}jm8lGbc41a2H>HL5&
zrkf&|SOOdQ6oPzO>c7ew!R&|C!8OqD&M@ZCdF583Wq*8U0p_}sK&Yw)`g1WsgwKO6
z$dW)8=F$Q@H=QmfiiFW~n9TqLuFx%ZpB6nf%^`zXe8c8><$NjP3Btu@Wj|V1sh5-!
zuE+gu$!mnd2&9Mi5NSP$@|DSxgc02O?nkQf0W%ydLs)j6qqA>uybD0*y@T^2AN3QD
zDh-xQNhdkBGtU)q=jFz&``0}P0+>p1bH5ef&=q-!2+K>P90+bTG{WR<^Vg5P`0u)h
z(i31NNNC-;pQ~-#aPsG9pgi}2W1noG3mPd1c<M9>j*r=oo8~3d^OJuzlGOYUJ=!^L
z`?V&M$pf~2Me^7D91`FGb7m_!e9PCp3v%c9FY4rj;!T_>_8EPwN;(3+ZIT#`q;m5p
z6gSPqY8Qa)6|GsI|8;BXI1PsOH7USWnw2lr#Ue`T&oRSdvaY{f5;{6Y!7hCr^bgP#
zh*;(2f<3_W0m^BV)nb#)^vgb<LeT0a#fsgZg@veSKGov(-WJXEG%V)<G4&WK^&zlQ
zhPoUB26PTQpdC12g~l!XTBRYIk?s#Rb2Vz_H5^@y>~^gg`FC}m3&HvZ!Z_=GyU4-B
zdky9y{HnGg07fH%is*OEms6v47)nTe0Ye15`y){xDA7|b{?tHuy2h&#>_Fh$*ZFZ&
z+@@U*m*|Dx)|>5DkcqPHuV`=cfIEG(2z-m`H{fjTz6yEN1vp;okU)rb8XmfD;bU%<
zN^8MN{QPE$n%huo;*_^GdqK|GQj(PgrshBzitZm>-QB*tK(0Ya_X>?k-(|^SK*F5F
zq98lvX^YOo_0DJsy={WXbD+;sr>bp8s3;?y3g&@2ryx16u{dQ8x2M$`izs>I=kU&7
zvNnb!D!L^rw_rPI)%p-vAGM;`!cHGo8S#fj<T;L)2H)4DoJ7#QeQhG*EfPRcG~#hV
zv=p>9z2D|Jp((>&Wr2|07ox(!_=39K<8EXy1jV?rqD_6jgN7}8LUvR{d9Qd9<k8;R
z);+3$NyRn77#m#mX*bR4xd|OyN4R}sNP9Kki*^=iZf1ZnT7^?dSL-*Q$ZM|+xx%Lj
z_2w$aZ!rK}tJHH(B;`V4eVRa0JiM$tc6wl*nLJDuY;n3iK>epVDdsBcu8tAE=#p{|
zlp15&DRNV`YYZ0!pOVp%od^~W#VVrO#Ywo<R6j^<`r`^!dz03f;1Owq?H@g0!W!9A
zwUVS;DO02tf-2+{K^ymRp5dZQQP@JL!YiA#1lTO6W_U2u7hTt+I2ZhTBeGgGNW))*
zd259tHZ@`hL0F!2!nL{7fFnFLAY1h*-1x{0Jg~28M3TCQCE=(VY<X0p9zy1)Eq;gj
zAdHGcF3wE#rT(LCWGf30a~zU0KRMxw{0GhYmfa`oPW#Jr=r2r%vPOpH=Geb0=Uh$I
zX2}+iRhVB*an4bIRKq1#BbbJ{Rz3}l*>|aGM+&FrLXUViJK_0F19SpSEB{s6t(K+C
z?<ERB?=HQj(Xc|0kLS@42$`$BaIM<jz&M$5JQg`7muIINoBos?5l)5b&?(zig2?5>
z42x4~zc+o08$&!ElE$Njl}+sb5R>$;f07l{&Ji_T8)dV0hray!9(2vjYytXR%$8re
zK!)m<u=J^u>@*jXM_I0oNmlFmB}frhDkx^R&{8-#qsTIB(YlzDay>Z2U<H+oP#oK>
zg&EoV+&Y35r8r3RaRhqEpzlfQk;Kl|w`_^TsF!B=#=Z(fWC12eHWnZIPDMvNVE6PG
z7~B!#i(>GAC1_IXUiHhu4brDu|E@2P2enK4TkCy9^7STgZADc%bbx|ZGDr8N3pYW&
zV%dvNT~qM5?lgo2_ZRu{ELSFVZIRjmF)!IHf<w}p@U1z_s6v*oaidPSQPs^;unP@9
zn0BT!a!55q)dtY|XZ5ip<ECKvMx0>6;qc%*NLbJdXsbpfrqSmX*ZKv-{U8}DZ`O2)
z=TRki)NoUGRHrdzXR63k+G+96Eq&o60Bb4<G0dK;^azs&om0L4uX;j>J3{c?E1AGU
f^@%=dR;%JrHC~`qL;+eA>7j4$Ze%;0xP((<d!prz

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v
new file mode 100644
index 0000000000000000000000000000000000000000..0d41b4720de9bfa500c804329664d5f63aa9c6c9
GIT binary patch
literal 19472
zcmV(rK<>Yb6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzLYrav9xH4o)g7L>YvU1;Ddeb#+&
zbE&~d=AIRR;8!X2h=%%WBnxvo=D2aonNQyJya{A%PQkzhusmZI+jiYG{$OXg$cxg|
z2g$#+stDS(1ti({K4uQQzq?cxX0rY76bnw_4Ko-MX{w?cpAx@l45?7mq4qw?bq137
z>7i1xn$t(HZwl$C<_j>I12#&}?XU4yt!ZMv;;JiAZ2)_qY-raHUzbR@=n<Tf23jAj
z&#;zrP?~Jxq8!i?@-Z(fx*Q>jVw3B3N^Xe|K}kIhkI4OhH)y5lJ6HXEgxfMpzELh*
zlk3nQMl4-{iaw4BG-1%F3Ma?wvz9d>U@_pkprr2M1JX~1wIN~LM@n-{6m2hfJreI1
zX4;hdc$)Jvubx=0XzdR%(dv2+6%oEim7>Mm^9lRbd2$?jF9vG7O@RyPw%ov0u*Zwg
zLOqcV@S#kIrYWfQ-L<aZ-0`n3xf1e1VaA+)d-5<iKFdMF3b%r9hIOJ99`-coBsD#b
zf1~)DS5Yi4ZP~7XSm2C@ka~5!sC+w7{wAuraKskFji6|%&);XO;QIu_5{<*@2oAdM
zFO$fQ_r)+!{*ail%u<`ctrtorA^@VRS@Mn{e2;0Wh-ZMPO+XkntkPzQ*fn=M<y(_3
z^}%<u2rbQ2TF~j%!L?2ZN;PnvFJsmAKB<QHCbNWHHXMyEHpdH)mQ}4QpNZYYGRq4?
z#+19-l>~6@IVX;jZD8nWwQRD?Ao*`4Sc0b7g~baboJw>RrM8&D&4lRbL2j6{Aa%-P
zq)gDV6pi?>UKLQ3GZss=&7ahxpvYl3AhLwN+sJ|Sp4Vs1&bv=FrB&;P4P|E^x|Q5J
zikHU10QuHTvk<Xtx}5}3{Ia#-LZy+_l7k)}KtM9?#N%tiUgjQjIH77O?hBcFXh2dL
znEP#|s(RV03lJ%`63oLEUG973%h|<|+`8-l;X7~cB|-Qnl*xTQ+Sr+wbB^#fmhKrG
z0Y$-M!~q@!<~9&vYl{~%1$eaQ^L=;B56XvpE#8e~{~9bgCr5J;cFk3zGlVV_%vo{R
z6e&0Ga8hH4Cr+N)I8xvM2)p7TyDc}3Pcoeio!~@D49~|>lL-U1+!<6u2bd$dS{~eH
z@EUG+M`SS7=Vs~V#Xwi8np`9Fzel-(pn2xy+W;5SaQhhFHqN2_buTaG`)>qyCMn;&
zLqxs9?~oL(uCfco%-^*j9~PIRfsl1BlTO@6RUK}?8^DR<5IjP&6-zrI6O-h!PHt}c
z9sOL|hgrW#4qCOTJneDo57uC0cD*zPpmqO%u{ESaoVNQj)$fe3Qet-5!mbQX*uH}P
zJ@@c65p0g(CCp6`BHA2&4?vpA3luFdFLkRrP0QD^_Aw`#_&SGiC(<BK9!F2vq6?g4
zwF?;Zfk&DTUTe*G(8@OGnwG+a{^ku1p+Xp2M;=^lYTNe<qUh<>s2a#|A_W6(&38mR
zPnEI6!b99|fDUlR(x!vZy2(+jX^?Xvh_E+7T*-u8HK+wFpjls?!fKAXeaHyIQawAJ
zu<(j=6Br&Nn}R`O!qQ9-q+WVJ+~a^NMJuQbBy<t?*lW!&bRRY#mwBp@!@4I^h}8>N
zg5>ic)x@U~z=e9Jp`rJb*5S1Cfog=ojC;HR4JE>xJL>kQRD2$a)x;N;h=Q^U{FzKo
zPXFB=Or&-I>00~<pfLQ_XWGQEW?&+f4<&U4<d+LOU|W!iv_CmDky{TE@`1Wons`-S
zq*&(qosCy@{-~*+cJ*fd;8dtCi}u*_j1Qcu25Q2a{j0n;$-`=nXq^B7=}TxHHo(e;
z*#(~#i8j}>@AtW&_D7#@AK$f@`5ps@3nDRhf@#Nzg@zuo5;EI-VVC6JKEbo7#<4TA
zu+Ohx84cKw${eDZaNnHb{#9GxD&pHRrM!fl0)TYv6EBwy*yWmS520v(A*$iNCw(TD
zr-W^fVF-AZk}T|AOe<=n#rSy1jkC&FvYfM9gx^8JBE(KzY$S_{FzR%-77M(S1mNbv
zsvL(cuHYb?k_O)t_<}Ps8yW6<oQF23W2$;S%;C}@;gq9A=-PlyPSCPu5mW}Iit3~K
z)+4c7!AjtXJFbMDX1X6<;9rfoysk`3wZt*FSC_QxQJxtpU~}npzr32yj@27JHUgom
zoXfTM{2|eIfA>|bCWN5e?io(Zm#)xR!kAZLFTKN^mpGWm`7Rd)ZU`}czez$R84b47
zl|1hrrg3Oe_D~w%Nk!jZ`Onf0B@0d>tnc3=d--lKt-U}dHI`RT79+ki3Gfe)b^2-8
zif4-arwzkLklMVV;S}PV%ssZIwEaf18GqYHKCH8zRA7gZc~LL~QtI)<ckhN?V$8Rd
z>i2~ZWFO^oM%Khk3!-=AyhU9U(~(}GU6t4w4p)qb79VbXFeQ@d^5T;zA_?IC8<hTl
zT+7|<HLi`&NGa@H#9Z4}n7NO5?npKS0&NDPwej(ZY3IicF{xKczj7k05HoIVV7?|j
z$_Q=!>$mQE<P87v*#~hlO)JJllt6ZPwGQoWNg82#(0J=a!;ps&G~W(j_?}AM4Sm)3
z0M8m<a$|_#+W&k9Gxgy(r;T<&q<jMHODa<`$Y`ktd0W2ZcNs`|-)_`W-Tn?}#Q95_
zg6JK(3u5W*Lkf*L)TsUCms%EdbF1`L1(xU?&E|kVBaZiyBlKd!$3*Yu-d|$O-#k`_
z&SSs*)9)@c{f?v>4W^RgZle(H>&!V>G}xn1r@7xbob=01zUKO&^nr*8Y-UQ4==MqO
zb;v@4G1{|>w^fN7tF5~v8_Z43lgGH!NGl~dBh{kFtwls~>eP_~3-LyWVWv;$%m3^Q
zc{B4h(G`AkXb*R%dF<S>HC*eFRo&Vph(}4j13I-Olf&ur?!o3q3ulv|Brk-5>f&Ow
z-3Ycs2-pb6@ZZSN!NzEv;cVgac`R4x!%juX9&kgKH%Q*m?e?!UT?&XUW07Dx3`77}
zlA3m4wHpt{LxDqS<)nU3OJEbeVfAWQah`{kt}z9@hdi7{p->PVDyFS!gMID^XPqKQ
z20Asa7yTs*DgtT??&y#75*f6wYC&?HBksD0Ym5$m=i(-$M+9=~Qua1}vb0;&!V6)w
zaZUfr(M`cd!R2X(^!7t@{7ct_N()zsdxfTrcccIyfy2S}nuV~7#fa%vg2jnzjw?7h
zT4znRQXz)cK}%CQ0(IHm*>r>ldsdhk_(vVuPx0z{{OgN?R#!UeEvr_EhD^UT`xmu$
z-J-m~n5z{s!xft5w(<2p8_Wn&oLdXPWccn#iRZge6K;sU0Zfvt{iX2ff#?;x4z&N5
z&JNf~qk@zf??hroRAve%(jhfb82}-_(}mob7jbWlqDRudAyL<kJ<lS~D=+8OeDMi|
z;jK_Yb%f>ApL9}X%!Q_vY%$z9ElS2~Wfv0)S@Rfihs*1>fFk{8sJ@PB{`UH-*!6Jh
z>G}oWAQh9fq315kD8UN-t7=2X*n4x!@%lZEgDMG;d)WH2I{l<9=!k1395?N8ZIlNh
z!)c#Tfp$fKgqtoy-g#JA7X3@Je4sS;{Ubh58Bi>qVOriNW(W9=vv<<}_t1i({OR~-
z075onFo5~JH##0Q&T}6yhshYnLT+}gW1OWTHFKU!A82twN3HRqSemLa**o^#&};Fd
zaG60vII9p$ZgeFyG$Nw5^6S;$NejR3FW=kquwF7cAol&JfCodB_d}513M1;T?6}R0
zYShh#gv(YM#SKfI{e+ob3`{w`NcH~?DX%#w%M4yxKhzAecCQ`NJS$OBv$hgHK)*nR
zS-RfmJZKn!Vrr0}<v)bxPPwa?9^x72Q2t+5{shYTUaD77q<9>;vU8EL`Cim~>PNW)
z*N@6H!%#e7g8|P50u0~&L}03`b?Es3ACX8|D6YK5NF*oBZN#xyXtBFMA)kW@yi*|j
zkhWqHFz#Z;i(E!IgmIq~4`pN=K(cY7sS~USU$N1sX)vXG?~IbKxh1D7xP{6V%DRvi
zz3js>8}$TYS#-+=kMc1nT2Vv#Q*e0k6Bvr(vk9$CPo2!-34Q)p8|~cPHy*poj_st#
zQUB{;2h{bA{)qTeRDJ-<Hs(AEBccBJzs;_KMBVmJG$szzKIz5$V@{e*0E5M2BEB;-
z{y(#SqSU#uV>HfXoww1*>J<MQDLjCM6|S#SB2z9P1t&5mKsAj{_fQbf-DVNfgnz&#
z-K4P#^3^l}y~ZE)=9{M$nOS4ws|W0%*U&rdh=`M5ql>Rz5$*xd)%X9M2>^I_WAc64
zxMQHUEW4h<a(3&7*f=f!fu(m>*!wJd5pxW`Ng^8MxG8WzNX0Z$PrYQ~^AI%xR?T4g
zJ&Uld@4ARHEUz`|JrLRWXtD3-90Q<RAw=*K2Q7zZei;XbPO9v)1ln5#Ty5nfr3(Yn
zsQNhRDWxDf-tV|Vi;3zrfFrg@XIvzD`BX7hrd82)uKN12283u`zm(27CYHwF8-1|A
z$I|WH4T(LUnE)j6c3svU)(Grt1c!z%fl+d*>yB%pjn_uZ{{OSv+XpOt!IQnC3e5c}
zlCZ%ps%k_;AeAn*F<p#ABe*aN@3jku!jbv_Od)_Vf%4k8Xnt~sPqU5_Q0Pn_nxufG
z+zVtUP)txNVYub;VEYl|&o!f^rHXXGI@O0E4GIU{56O>#Hc3JJlE}*taJmLaWHPu+
zFtsX3rRnwK!P`da^GyqPe^n%{E=<VnrhT7!2dmqD{8UWQ#uVCRfit^A8K5BRWw{7L
zv6hz`rYDPyW8C2jP*nfHWTsI8_;xjNr=CHgCUh>n)u!oS5cyuckMhHq#WU#wvqK-l
zJYik&A0#w$XZl$h_zLY`<glt+b^CI7>!H1_+eh{WEiBQ#ii0Z%ZfIAnjUh3cl?Ypz
z5q3dR6C)IHKqduQ%Y{9cEN(GS_8eH&0A?1-VUkgmoe8FqnJ}qDS%1JV{SXR?WKe-5
zHzv9b&*gwX>Z`u-y#FpBAeIdrw8Fr0S@zivQ3I4<Q9%A`hV;!^-%(r^>|u5)QJf-N
zBmn0{wWd*O?b<T7VRP11ATSD*{oHISPYnc2A1fRdy`2-i+qf-UTW{SY&nPl-d1$ji
zYm*7~^IC$(FuZJU5AQbeTbat!n<4wBeFROA^9}+ST7BdnKb70LC@$aS{tMU8Rk0OW
zLq%4Oadjw+MwY;tsfQJ@OjSE{ey2%bK2F>2n>*ph`O)df09P8Y^e~ihx|SwYhwmOt
zQl^#)<mCCmWMK;ulKiFQ{`LHuDNrAaQK8jQ&ih)$XzU69eW!NzrB1MkH=zXidkhRW
ztM7ICZ9F4IfSkA$xQ?o$9$zJl5A##1H8ro1wx9tR#W?GJu+6;u(5c&K?&bkhM5_)z
zc&Q=8czHfT$i7bYko__foCto7$+8E|CA_?bV{ChHnLh-z-_S1iB1fH^ZJssvNQCk2
z52+a{;KU4Xg%{PNNpZw!)|nehk-pJh=^s~BX0wwT-n^{?MBoi`qDUGH5Q@Vp-AN_y
z@;RYAr4i~G7VBTZ%1w{h9Fux+eFcCzz+0ZwO%(3~2{#uqsMiltZ9L{4d+^t7;-%!9
z6)Amnm@&%*tU%Ad5HEK;oYIBDkojYA5m-Y1>jnV{W*6)13f<nT7^oXkn;03fqXa;p
zhh508IA3As_ekq{f8Z48h}S{ksAjwKnmxfrCajWlX;f2sRtv0d`~*x<(d#t0q1ib#
zFF1K@S+#u!H_GrxV#QDmm_t4^4&G^y-$(WLs4_%D&cV*p^DT@UhAPQk$HtLOP!U`(
zH!AuZmwkuz&gBPSc<+#8HNO56jF|*gZIT*l-XeX+^u%Gqcb4tKFV6`)<oOhuz*n?G
z3ugw9wsBdSZr{ZlX*I~@y-I2?f}=pOJ;Kqtf`Tuuv~Mr*E9Bnscy);O8a7Q&rim$U
z0=q-=A9FRqizsVeHhZV0IR07$_=&gW0=Y6IiosZ_{nW9a`biX~s+T4R?T=LKKeMo-
zfbTGWz=@@;CmN)5CnRpo;6x??(fwkT3XQ(V;2j6?L+OR5veIx^HUL_+!vJ0Re23Ha
z0gF5?MGW##SEF6uoLUkG<svz`nvwp8iVA52a=@JcG{B&elDh73FeDy=SVqmr@o`^j
zQxc8z2Wmn)Kc|fV3Z7EbSIl+GshujZKMP9_2FmVzXNjN$Z7_cNLcvb$h2%IT?n62#
z9^-o6XX2i3It-rDeXn&x_#wY9a!{LWJtCT1xuS@u-dCsTnI|111!1E?FRhaY17!9u
zbf5hzF;ImvNnBmof~lqg9QNVsBt<ait+V7F@3<h*S&d<&F&57%-RKIm0LA6tzi%r7
z7PNYLGlNfZDFlSphh;ucU;v{l?%;b95Lzx0XzA&M97NrJSg+0{&~_%zcR`~J4x0|?
z>sOaQ0Lk#is?dy%C;JLnlVRwu;o2yFM?0Rl3nBGeG6}yp6a|k8`#uK<nO?J_B5pDD
zi&T*AI0ABV9q2htc;njZznad~G{>+d3-RBipTljs<qC?3pD?V4pOu`ZRYCJYP)k(S
z=GsGC4e-EyKEF$So(y520vR+7zCSHpg3JrXFf@3=T@db9hYr+)xF4J(jz=c-HY-BY
zXSYqxYB{L*=(V8tq24ohWtg{#Ks9$X4X9d~DF3yRD=LXu!5x?@^9F)}W4##$D{{B*
z&8CN8VXTG;fxWP*8d&uMiu-z%((nH6HMdxBZsFL2I1zb4vF=B2gm}PxwY9%Q)_#C5
z8gNDH+}I?!!G$ND2gJUv!U`*vgjN+y-mu%0R{zKg5lLutOBoJqA74D=>NQW1kE2W{
zX!?%O(vyiVlrgaDPuuTt7n@CuVsF3oF7-8&;6a?vD2iFbN#m+h7+5@s4*G&BW%KS0
z<=Os$Yyww{psI@5mZUXmQejwS$z(Dg_yil-{t0hlRTV{f7ak)+HIgw*3s$QaneE?7
zAJ>?bF!AF_#yj-S^EQE))4P1^i6TNnboMK~*Sc1_$0&nf_+%oxs)b<^OiY=>5eAi^
z{Oy;JR+N@}MQUgUJK$OH1YCKq&G>g;C8~*5815Swz|iMO;|wo6zRfK5PAWw8CGM(w
zN!7?d?|=ePkEpVhg^lKchq)Uc2GkJ8q!Rm)#XhcK9IocXAYZ3mnp_pz?Qj64T0Fu`
zO?1)uOH`03`U=@ttliB4b|F-6!#%5D$rJ-duxAC-=JJElVIx`42lmH>DZXD{MLld)
z6(5rUh4u@0?fwg}d&MI29+5ds6)LV=DxF>)>yc^_bbrnSkWv&LiD664i!d;2JJ+s0
zoweF01hlK;f-y?>@&XbLs&8}t!upfmZ$VdGJ^m(lAe((O(V@V>#dq^Z{D|+&i3I0T
zoIfq_Dho%=-`KUJ5B;R>DAQYfWg?~|N}@?7C$G>}W!cBg*2F!d&f7ZbeSR?g(K{JF
zi;Lp^CNC1@Ylb7by0<>i`EJ~ZMC}k!h>8E+oceyF^Ny?iD5sb$N*WdaY@u3oy@nhK
zA0*<nK&;iqq=4MDZ~Ge?;TK%1k1suAr-<YpJgQ&W4kj6EAh_aI2iZSd%uJzX1c}a+
zBms^_Hfh)V;c`p<jQ@L2bzG6bnER`bcYK7%{_#!2l)m+(CPxtfegosXu#Y(ueuCS<
zWn^37^9hnkavo`Iyp-KG(c5TJwY5GW&dr<!h9zjq66oamTvy>_su%mQ2;UvUGo-Mh
zcj%Kwk~zYXCqM5+-TU~We22rIiApc1&$Dof)>MVh1uyi>v@3p`Mv54DGXq)IODZzT
zfu;V#=ta7AKjuR)tYiH#;~D^@(z`LD{4K_u6BfPQCzd9@(#iuR`OPi*%L|W{rB)^`
zsqtGi6a(N{k1<TNWFngdNeRkTol!E><lB^15`<Lx{lgp)t5*-hzY&s@ff$@}7FX<e
z3YN2VB3Gc3k>F5$62tctDvHJ_w|V`MBK)M1n)7-OvO=NX(Fp!R{9!y-S;)ZuEU84X
zxnPv1n2OnLYO`ppdwA{I$zpgoC)uz#l4ODZV{zI5VM!^Q|Na^ukCe~c)458<Q{;+L
zu&x}RrN-oJpbUlk&$Sl6t{CJNO&!uGAb(bV+3+whYqXt5qf959l08W>Fi$qY8vXV#
zQE(nU%rZCiDcs4*lOZPr5xbH==b41mc0!Z#TX@;L@lQPEsRc1r+%;d9ZXBkY5WTtD
z2Q%&+lE(F`I3?!nzSJe3%37F5jB#-Cws&m=Ti$!yOw$dh9%Jzo?T9`kQPQ%mNViVk
z1*lJ1TZ}d@=p9h@XSXhdS-a_6skRtJ`cFd|YNvo+W#5Wl9CumV*_=;RLd|Yrn|XHl
z9Y-1S#zbf1cKMg3F?^2F)+Dqdhh%?0nDYc)1jsHo&fmb{8EiYRlmf8yUC}d_PiOnV
ztKJb^#qJtSU{>ktvW?iufJ7&Yp$z7HyNynOppPFCC0(c|e@X2Ul)bcc^BNmiE#lLa
zDgdOkHT7Tb%yNyzCwmtz2ndH1=`EP!&m}}`G%du0E{}A2&NmBb#B!%vJzL+KUj1^G
zQ#^zw?nyprccbaA8`Rn|&uJ;5@YMBUt(paIGkV*hNykwW*JSgR;34N1`o?}>;|e45
z*Mkmd8Je@3g*rPPU7P98wQS%r-7&rdRHC2s?=-dlyDW5F`3F(8ITIY2F0JJ<^chjV
z{^D+ZFMCLCIyqC^@`3;p$scp8McIv`U%yJ`sDyoCNmjz|cx)8`FdopEVFoh!*T?Gy
zq+22MuZ&;`vfju6rxmo#ykPooH-f=rK#(N2x({P*w9tchpRxapq1_=*n1iAQmLP+l
z=i7_lId!l}Tol_6QcxtZ2s$6!y;m(|a#Es}N?wOQav$xRS{`1;pu4-f%W@@=znE;`
zZbXri<l-yz>gip>=u0iRfLnz+wZ$-HAP{FNnpSofaM%KJ?nB@%?aA&5b+^3;NHfCa
z2^dc*9AxWATV>j%3_oudTLo7Rtrr*JUpAf}AG;$~%IW-CX=#>YE$Fgl?aeHybqG;J
zni%lq+NNh}NGpxGxfaS=3a~QZC7;50maGj$A0zLQ$W=Oe$Srl)?inK<VFa0~PG`})
zevq!A^~`zWAYod?$4pWvYwa}{5@!UUX!IDu4)_znEwo2jd>!mAH~=(56=Sfz*w%f!
zd*l<&YwLqs5lLmRwX^4CFVzU<V%hAuj7bYKuH7a=<E!VFt~f}KUJxrmIQY{}1V@K^
z$ve=68OQ<VeQ_KBy1g>Rf343>p&A`>J9>CaLQ|{U#oE3u0%EOWY<L4F$quV;8+5p|
zLx+O9w67D$v=Z(Bu6*!&43WO<M7SqzXMp^04S5n6R%_{R@I#87uZ#TdYY3(E0-$(b
zm_ClMBiaDqRH#)HJyh&nZ>D`1z*pX4Zc}hyl|zn8lC#WDd2C%zv%)!2jfdkH6&OcP
z<?!DCMwA3`fZ1nrUl^O2vLKfeTMWAA4ur9kB%(|H$|gw^>}k1^WXAHMz}R5{<@<FD
zP%-xN)mnA>-FCn^5tO2tB2~jh7@X?4(%W!82Uyh7zTEcay10J4I|v^Vt)NlfH@xAT
z%)WVMQTFT5YwWNxefr5X-dh7*vP&F1{ydOzqB@*A6mGxIeH#_0Rj~7|1!?z`nlSmF
zv08ENWK72?xic5SR9U|Vv7_i|ol8Vnvwl#MHGP+z!cj1SA-4h*J(k|)78?*ocFwcU
zAM4+`Da4H_>f7y}08@7Fcgxw~Q`PpRlKn)VAmI~RJ3j(CRVsE<xA0yOuXgmBAQTV>
z%qepJ^1*_&kt(j6UxAsO?T}~iH@@lsK-_0{M8CtehtW!p8Cp#|LdP^LUwZ8GKyR?S
z5^7iR!L@wlwG$CM=ojJsn0vZWed`!E(ejFBtu1wn|Mr7i^8>n_F$T=|t0p^lG0w=H
zl+2=|vFuxD%(#f%)~AQHhv=M3aMdfoit&K;L?i^c6+@IV-_6#^H23PfF47UUo2Vxq
z89n_(eQY&G9U|dLhtW64e)nRTlUe2zw1fb~Ej=hcXW6e)jpHpvtr@j7AievmR4-2B
zMx1u;FDGb6Mqu$0{jqJ8KUXSx03oUT!=1+p?v`A`7_=p_27hccOl>UA>!yA6XC4NG
zy0^C=Dz*LuPpDVCqdVa!7|{mvu4Mouvx7<qiM``WXm9+C@%N(NJc|>AMX!oLU_cnF
z6*xJrC<bW#S5EurHc=sVn}I%AiHyqy#rqHyPY-So>Tj#ugJcJ!CK}q}*-{rgwddT;
zL3%$wa??*0zG|?G`w7Y&=Y+c^?JbHr-|Bp9?5pLXu1P8qhX}f6fyLYDg~fvyuP*|C
z`q{Jy-p3;2uk4e8aI$r9^9GXf4~ur?s9ijLOa%T?5m^D+xep~-cTnQl0p$artN{gk
z8|@El<BBH^F&=?K2!uX^rR`Z&6_U(PZ#!vg$hk6-%79dz(h%KN1`GMtryqacgGoXw
zVV6~*sZ^)snlT`e!Sz+PI6!4!pi)g8`#p@w<DWf!j<x}(Ih?-*IvzQJgKsyU4KA$G
z(%nhglIR+YQB!eEIayYsO~Uy)9W2Y3IW8dMlxX5f^QhG{uOdsS*_11qE;YW_R7^Mw
z{(h0c|MAu<R#ia~qAJL_-h_xoQ4h$7)<AvAV70>bUc84`>>jMUnX=JncR`*2FIyz^
zbrl!IcJQwOqDzWjlmYSDdEMSS1&*7>t44cX8DlBS!~6%HvHgtKep5ito)aWJsr-09
zM)Jb~R!Q4Lsuz=H1(39Pm~&5^n!bSejLi@E<3eE?gYrjGj1RK4X*LP1IRF7V?<M6e
zu@%ehcSvOttHWW%6l$vvA*}lq(7YcDN;sR14e=m1M7lJ5Xe3W%8f<!h;REqSw2V(N
z8Km%sZhL(_*?+;BM90-&fy>ek<F}{e3+<<waSoXrzEII9y*S*c595%Nv;Rq&HUrIJ
zrZNeoIz_==cmsS9ejxqoS&RBPEf6PYOYgsdy9buRsK&-7-!LAGtaKP$!kVwU4774$
z7a!qlvOriCj29ByzTUmZM?o78q_K%%$yjfNn~^9<j7AG+>diu*Tj~?5ElUBYd)F!t
zv@{W}5Db#5|8-NxoY`L{2+7a>#qZ{Ub-SO3S@2LhH`jnC!LUEl;@k4t*I@6aaT|eW
zz>R^p|8*{IFc}iHp|{ZTsL`XFH1q+}&D_8^_C!9$Dy0W0woE6Twq*Ki+jOhSqshRe
zQ=7!DLo?1=QOOv!t&&11Iil^t=-;7vWK0ujAB)@yFbJpM2EQ{V>o0*~7gN>n4@Tct
zvuw5h^@1ci2`AC^fMZuJUvW+1xiJxZsE*Oqqsb3H0gK>+L7Vamv`mF)uW~jlz@(J`
zB{}uU0mYN^FqF@D?Av&GXb}*cCxqcY<{nkXaUb{8{03adhHX*^7N|IjFsdGS0Z_yR
zW=<RoR77@D$m70N)r%t7Y=BjQ2Md{QukSVqkfK|euz-=_C?+KVwmr?h6nSimv6o4I
z;4Wzv{q?cjGISN(h07?xp|_5g;1)qc<GewfwuR{-St@ktbS@z7KdcOu_r(V-2)vsD
zbD9Pl(cEn^6mZ|MP#aDBt~dFD*ODobc4*E^bxX>~=5iK0&RQ%cb3KY8Ii{PRrrDXi
zi;{1~=159d&68W}Pi>ki2dKSIn)=m%6T?b#tAuqFqz{ZgmM@gwH_h;<4!mbi%VR&$
z4JyPJO%`J6PZI$Gje}7^^iAw)4BmRMA#M{+b$T%s7zagA;!in|+ZI_M-b!$nn+#*<
zCzbZY4A#}FHY-;qN5*Ko*3pGkn#vnpuL0d!X!rYl6^kF0uB?LvkW5;Mh>KL7aPZ-O
z@|;|Ee}U@&mq?57+MC*A+`bx2?3yA+>hEpHa-^)1h}#vS<spt6mcktcV~U_W=dAp+
z=6JvF39EFt=SNtXk#jNx+>#rI0^vEev_1{W#K&>g4XqZYAOaN&3FC52eDmRG^}M%?
zV6uuFLM-u3vZc7ZuJJ({<zsp=nT1&uf-<5fjbuZ1)>OKN785;mqF;JjT!KT~Qhfso
zJcpIn(@}`vYmx3fNDN4gobRIZySC=)ZncP*lwzIydt{vK&Y{7vIYeP?w7T)URQP8F
zb+YmUc=Vz2#kR}hPiyAboDwpIO4$#Uwvwf34Zto{f)wIP+CIs9M7-^Dx2%yL8u4{l
z)oxS6iu4IQpc8YN&?(i!MF8FexvKNt&@x3Fb&hXX#Hb~(s})Dyg<T~D@LWrIW($9*
zp_O?WDtW#!ms7c5a>W#Rd};|Cld-3|7P6cE9?9$|BXzzeBHS)eQV3=iLW&NsyqCA1
z#`1oZ*<#miQ4#jXoH5H6l6my~gE>QHi{^$0&;5+4cA(KuCbS1WwwjUpf~w~sCTW4H
zi55<GDN-U+P#LP~C}M3~A|?cbw2_#`eCN5K%exsmcIK{6t0{NO<pr^(u{3+<9k>do
zJJFwv^hT(LSma4n52mg3{}MpiME_wlTi#I&Jl)dk6WpzA+;L`ZmKVp=7%zzBM~9k|
zAX3vF!CbwA?7=9)#2(>NG%QivMz9moxXHww@^1>{d|I-_@{E<^QA!leR&~0h?Q^>@
z&gx$~@~?(lDYl;?4<GO_Kocz47aP<y7*+f_7&E*0L(T9svZ)7vt~Z%CtW=bMo{r}o
za)v+=dsechnNSeFFvPP_Mkg;h4R%H3Y?9{U$wEyI{v7+#6&Wlt1%_685CVRN{uTC2
zGf}9sj8GqAN~%X7p^1XQQXpFEsVC^tlb}7!=A;r%ON{7wN!ZFvGLKG3XR>^<nr584
zGI8V7QcUShh;jlG!{djP1<p?Rk-==7IlPXyzZTYRnevk%HQip$JBys%NxQ=WgTxXj
zS9Wso5k&}zyftUHty2}VoffBoly1|JN5Qs!w^6hYy*+4z{rg8ZJH>&YfrXFThNA^t
zjy}9571C6TZ-c#ODk8Kxp8zct>LTD~PjxKjnb%;u4!iT@F=i=S*Ca4l)Q1I{DQuy9
z+9TZWfiuCoKNt0F+Y4vxq5q_ah`;@81x1rw6QI+fD(EVPNozcQ9Fw~rMOX+k&Bs-2
zFj@D=8;9X0eI;Rgw2;Vq3zEI*I;o!jc<{dL)z@nY{oBxcr=pDvGc)7pLYT<70pjjS
zI%XmgQa2MIZ30bQdgpwbpoBqPyR63CA0iW!p$HoLq$tAjGcJK+1P=zlr#hDR{x<Xz
zd3gv&tu5+^F{ZMYu`_l2OXL>Gsyfm;^<wp9JzPG8tFxTMq4h*RRyb1@pZNW*APUon
ztDZEz2SK3l9apZWBmTF%|0S=~T8dy*SV_FGQ)l-3v0m<1rreCT{@g@Pu+`L{!_Ki!
zDA~q!$740L{*LATsHe3tM&PZjnS+23S~T#D;_xbFj-Hq?+<A3LSt@GuB}uBLR+a`s
zy3K%XwhQvThi<Qr2oSX)@K7utYx>NuE3{^TZ6y&?)Zsmr^t<4`TYqyyM@96wRWe~Z
zx+oA;edVRiTvYNpzI`<T>J2MNc-Hupn<!;ceRaHRAyiLs!t~z53M&J$P}q$>n%#3q
zN@E_5sPLbUkBtamGqF?b9O$8odY0oac*l8kfXaBowXE)sI{Zbxmgw0G-g8}zRz@^}
zO(Zy!2|2G?+fbd63N|V??!A@_(>s&;6_jyKd*(cF(fd<o5L;o~W$jFwfs?0$_a<Ih
zLF7Awz^im5>FFJ8bGAVQy`SXb`$!z&VA->~*9)st$I^xNP*b4?TRwQ)p<*J+?~NA`
z*NV^Sh20pVCs-v^Qva$4CSCVAu{vIa8`?-bjOld?HpEz-cN<}DVnhS^$L-c7lq8*=
z@J#K#P!jo3jE{EI7#+~^tSlrGxPBw<GSiXV$V#fco}YcxJG0FizPYW0jAl}7wXv2I
zen2Q75;-yS&_1G42{DJxtvgPY7sqLpPrF&x6OQ~OW8unhvlulSAATa!ponq!ll{<L
zWPUp*vVDOX<OnxYT;9spd=%IK&1+c0(oFvm#=9Z#o(}N6%0RsONm)07DA)}38K)rP
ze&ivG3x~_qK*ccx`<c5e$n#L60G*x5iai{x0XdoEh<BIv1r(ryQ}oX1S4F@hXQ-5<
zX=?K^7;~`h>czL^K{s~`QaAtyS;zJVc+E2xFfN#0D1EOvwP}^14GvlvS|@nB$L3UC
z0PPL!|M(g~3=69T;@#&1=|_#y5)YYGTJniC5rp~@QSIK%Qh=qf+dy^*UTG78RY6}I
zb}OUa)1SySSAaJ?5y<YA&pIX4l0Pu*JJO|mijf5x%1=d%iVL<Tc((`>M-K{SlRK=v
zSIj~UL#nsP{D#>YM~q~g>M*AnyoyL2U`1$%iw!#Rhcy#@`X!8R6|4Ia8D{Ra)7So`
zV5U_`aJNp(KrnyZgQe^8>dmXhZSyIwquDmA@PuvxXHa+8o`TG&Mcsn2KR7qA#i>Md
zV0#fYVcU~G8B1{G1ll1YVx)`de$!Uc#?YN-5Qv*#N`iFhj16oi!|WG$uM1+NuiOUw
zW65y1OOTytOYqcA*=B{bd&j(R@Ya8`GKUG*F0BlyrHw^U@?gFL*qy5RAvK<@5)cHP
z=OsQ)tBxwhYJ>=>M=B5tB@=oVYY$`+OJQT%VDxMe?R<pxQpiL)beW~OV~xkVn!XD$
z2(k7T7jZ_A@><FA_hVIOTb*If&*1&Rd99{nFGSLpS_KBn{s7gzzWNhX$|+C6-5caB
z7v8PnGyy3t)?MN@r0MA0#_16GW>?3Tq=3a?jG=MALii088_A@lXh}R&1)y?WVW`U%
z;tW{B{oQrC8g>d8PWUZOh$E<_s%2~PnZ((`2z|*TVS%|~dZXjjk{<O)>Mt%uBa+N1
zz27`<Umn(GnmyewJCuw4xxURe*5OBHG4px>BH<6PcY0cD=Pl4~rR&x9Yj9=8TQZid
zRHbdV5)$$saj0)tXC$lQI=>$;3anutyX2;)aKD2^k#(|X?f-EJH~meCvE9A&fsK`@
zX*zTA?~c2e>?5Z;=b!=|11H^c2TPxtm}+<PcdMLRL>P{1Ik!vLBd2p+UEu<wg^{`n
zK8L`XbE<T!kfssuY6v_<!fslqGN=sg3+@Y+#L0GOKu6+p&*Z~%K=;?rQijBNGSSQ<
zKZi&rRFj2(ECj<~OU5Coe8VTo2#{O;c1u-!E9yNg`Iy!VS8(}OfM3%2zNRA2CR_0A
zt0|<FIIx0h$#;?K9gcfa+Ar!bTYK(Rop3_Qh7+#L30}_WB51~x%o7K}Re=qVC9V2c
znP@UnZvpyWBXpC?s}Ud-7UOc3W~pFyeSvPfV3x#XPk^^XlWMVmHPtW=l({}EGZtcH
zfQWZ&GsO2UQV#TnTHu<lACr-x)*po06&c86uz<mAM5ja)^-2|$E8qMpxH$=gNluJX
z+gSMA4t>RLkZ!-rJi$MXuXxdB8r>Ms;rC^20x+G}(WiGrdAo@m&mvRCNZl-?JPDuh
zXs8<$Zf$7Yxa!a?uripqQqL%V8$j|ZGYEFB7a`GG7Fit8%$uMt;K&-=MoNtYyHU#G
z%a>7!l#&EInhYYA7x<zPvlUdQEDPmRmB?7&wjMj@LMSqGQ8E6Idf7jC8_zQM8QGIR
zCze^+aMmM9PQ&-w^WZmD6~fU@0k7tmC7J{AZ|GNK#2CEHUB6XXQC~xJYkO3FM!LSi
zBMU$Wm#}1z3MhjlwF32e`mVO#PgIdm-zg&z&Ib)gYFa2ddgH(4ttjE|xU`DA@MHBf
zEcb>4b1sL_Xps;X8TsRw0dqB72=3o7c&`ZRce2r~(90Je0Na`E>xOj?;)d^dMlC}E
zeN~xyQ{xB4%7OoC+ryVlQwhhzR-k+uiC5{2_*&@a?qw`6Xt7#yXhH?R8F%eVKqt1?
z0lH+U`|j$F%#fq9)nUpD6)9oHIaBO>?ud<OE=tZ-cH(-X9nhJ^g7$EXUfdn&EJY@t
zGn;cIw!rs}=I@CE47(yk;bll{?!=tQ7+htVw-OS!{_$W<RETRKE6UVH(Yvmw`EVbz
z5f>;-2Q_UmE7#bb)<ET5ndT8(8jMrL-Bd@O<pC)*OA)+rY!kWt6z0;4O@wKL5MM#d
zBg8?#{Id@{;3ocB`qcHi#buy3)u)`7qrh4XfA8Mk{Yc?Cip+j3nNjMlvb6eQPwl<!
zkYHx)NL7|?sy_AIOR)E`S1@M#A(TQ+4x?olUe5xj<YjM>v#YSCkf0GhNuEcOb~aIw
zVEr03um(?IPO}&slEDgId-e*6^QlHzgyv$LaEFkYNgD+7u~v}@VG%x^y{2OoAm_?6
zj(K-Lfhxnh#}zfKR5f@oBr>``w4w*3%&+ZKM}i3aAfpMzD<q^i;0R@TO7;U-b@P9<
zo?%P4<{n35{8qkOcH|sWLWB-L^eRlUObEPpCJi^!XN`&IxT~=UIcRX}@JQFmWcLUo
z$ZP>Efk8mK1zf(_9v1cY3?pW{{kJv7#R9ROJJ#}DZaPQm*jAT*QVUX9eOjo|jrvGF
z0Pv_&`k;ez;NZtuD-1ZqZ_hXA{lcU`cy>maWCC1Cr1c86RI+m#UcD)wma2?90?+CQ
zodD0ljvp>bFzX8X%k+Tawv#(`o=vSIwK(A$5;Ph6$tWUg|1q7vq_wC)O6{dU-hC<W
zrNjNtLSBo?5UDYI7VZUS_HGa<p2(7dI18$Q_H0=aMU`v{Ok*b?nH7I}FG7kLt4AUb
zEY##wouDD>V+ZJY&y5*)teCBqED`S{>UY<O4;Oyfi?5}TMttl3Y;Ob^RLBHX5a-z4
zmKRp(r8Q%_D&3|?GX&dh|1@e!AU)!5oa&{?RvKz^5X!X_RV#Ju8t#FFpJ|fMnsLk0
z6lyLTfejWjr2&j6qXJ%o#lDEPCQ;;EWoS_MiZ~7n{~)jBkn_eMQ+#40eCUzFK81j}
zUVyxYWscv%j|h7mBY!<`_t~vgq<Kw0b2o(tanAro?G_<e#XGY9;s1{s>sPV{hf5*U
zWv#uW3*PBwD`uJLB&;y1q;EKD<HO4LODo2lm5V^ooe5~YsZIjcmLKc+6a#hafpE;P
z4B4SV9EcjVg%66+O|BI16(=^2%u3?<p7$*n31Bav;B6~pu8Q*RSRsLEM!;f6%`cYH
zPrG4qsAfDH8(}m=j^#CTk}q5w?AoQ9%}|kUUZIq2Y_ryXNsmDO$e!)n1Z*xn5-S)Y
zqmwFt%hk8tDk{zqd@;I<(wyvC{t6>b4u-Eva3Gv>lGSrTy^&{6RVP<GL+6dq<x$gL
znHs=b{5$N#kF}So7H#RZ(@!wMYg`<sNm5q<i?2*^Nz-VLb$Ee3*LOsF8^*7&%JZ1z
zyARh@k=s0drt!+e>R|{xzl^!mOV30E-U%eM8o;hbxSFOhnsr3cB0l9=Irgj|Ub;w>
z*m4~AXP$XR!)hu$kx6%f4B7?pR3+s$AS%OZ9>ttA@5vDS)<JNxURS11g%N~F%U&@Z
z+pB+Z4vk48K=>SsgZ?Y0Cxy%Evd{ym+LFcFi&rAkjY^XQ_)yJs9VXuiUS6NuaNQRH
z(b`4;ceAMHGgEql;iv?qykkgY=&TO@80~z9NV9>^qz__1a|J#2%yPuQW@(4F#jxsw
z)BG_C#s=s;Cfj%lzdK5kF4>7^J@D-HE8~56;3j@l_ayeg#k0ksc4lvkB^VcrDdN6%
z<O&N?!dWv`&j&Vl&)+4A%YMq9X$Q)1Mj6D|-Zs=$P_+lF$kXu0u8`9$m2h56wg6wM
z>}8NWgiO;c4;x!YECuTQF0lJhF3Q(2t21gdhcO&itEaTTYe24*?%8Rj<<9#m*9zL0
zXZX)wTfF0f9l7gnsPceIZ@YqWZeUJ-)ejJ%4mhZ!hFl5r58gx2a|W=dC81ExSoZ6L
zMvTUzbXm)f^V?fBk9Z82Loy4Zi{q;2`-HZn)~~=?TbH|}5R<t$b<V-IP=)!2os5Lz
zy*oTv>9wwwSW<4(SVAll1V-k*cLrel-LcIZUUu_|UzLt(qj+JOCzD#eeha(VQG~iO
zMNKLnIAdi)Ml&byxVtQA7@3#XZwPKw;<Gn;z01c1C!3h7%_)hdB8=DmLWkq%4x~B@
zFUP=fVb7^{sqiI{K?5%4E7g6eJ*!tbRQ-h|Sl>7>kA51!3M_c1at}y5OHRK@nB>cF
zeN84F>NeWDQnLQ$T>NoJ;TcnnwQPl>qy}?$C4A=;iu+EdmTydhsiYri{mTS+$71#$
z;hWh>Z{1r9n((K7DqG8U?lMX&-fn?@WXZi#Oq2WNMTgLJfJ9kQ{8$3l>ve10kwD8@
zmQ%EuFfS^Zin;SSV^#a<zJ{M|@tV&V8mbWCD7`R;4^F2%CXNEt+a5{PVs#JRV&fbn
zR<~cl40$8(gD>&dpio!Y<)h>PukTWC+YUUQmOKgX%@0X=6Q-8v<Sd8@vlz(XInMxh
zzMh|q!54wR8$$4h{97LNFm%MJkUV%dhqO%HK!Hs;SB}|#&?dKt(gct4P2GP<-6cvl
z?fxKK=Z#ZX2@D|IZ!d2u8^twv*8a^A8%oD<gw+plor4Q;8bC6ay!%v;R0I!vP`))K
znqZ$~XgiIf(GkOS^^iBu<n*E?iT;2;Qsj+R_+NJ7sLK+ek{{=nRNG5hj1Z%}0tkQP
z2m+RMWU(wA&?AMhwqsi10dDro;d_8^d)4Kx?l^$Nso1@dtGzXg8)%2s&tIw@@8cAH
zak3YHIVph{VR34}Y%kQXzq&7etY>wNRLvi7x{H~u1V~_Zb&;&;(IC1y`&Rn@?UAI%
z)vENSfHXVKm2g~IMlC<46!{N;gdISS0bAX(E7X%CA6Yc`_}0{gAn0T$WOLgr_lYjY
zq32a0`#)yW^0Euc15id)+pi6coL+M_Og>((01>q2AQb@^#md6Zkq?k=A(ZcQ3VtS$
z`RtCum-`Nf$Bqoa7xDhLDS5;cltf(UKcPWz5czNJ@2e9mKu}UA;IpaLCP6uiV}SEz
z<B@tu@4)*~q`FtX1ecq~%DY33L>DDYvxd*sA%}l%*>&4qBISaScC;$h8CJAcsa%xx
zj#uL_!v={MIIj8-UJ6G7zu}-Msy3;U3J{;P`#ZHTb>_~$!;NY?Myv+Nx@{lN$cOT%
z=6<I>Ts9mjR10?7F-_YwOALBh*=_n)Pb!znb_OXb`5BND;3AGQ?!1XPC18ROk|i#-
zJQ<-;a(H@UG5Z;g>meYSxltufg=OB@SI%~h!ED(d9<v=k4;or2pGPEj=Y(A5ClxJ_
zF>ZN;3@3cRup&Z7B?WtQj2>CIDJRkt39ZqRGvlyBBHw8Af+fjjjL?I;2Q^TU1kT{y
z^m;u348wU;_iqt^;?MsJ(tj`Syb<d^c{OZ2{4cpHGa#?DT`aAX;iPO6@L`k||NbtE
z9<R#W6zZ{`wu(>r*#=E~0aqlKwZihfB@QNyN_0fIYNh?Zx|itnbJ?YjklM370yGY1
zW?#d8{zG#F%1N<0s-cPL5~-sjvX8slZ|a#5KBoyQWopqUCQE-D{u{3HEgfFEM$&wF
zPEM`l{Nrxil~YH>4uEn{i!pZ+>stx&v0Brn^dGJP8GXl_bgx&6N%5ZfMUQ+i;_Ir2
zH1TIf{trpYQH4>w?zSEEK!ZpUdG<h|(e3zsi(Z!ZPs5lcO1a5-y0WU_bS?^Y$>vC*
zs++?bFB%tK^idJk3)S@F&u0VJX&ng}p5P(*`5=;6r+v|g;n6EhfNuG=YU$Hr0Y4xd
zQ$vQj+SX_F$*|meShkX5cZhxA-&Ou4sDF@K&d!z6XmRJgFAJl8dg<u44J3kqRW11E
zNCabUDNS7Gq&iU{e+oizrbg8-%x*y7t5DAipV=Rs>gE^2)I7e?fZmnXu$o5N>W*~3
z0kx1304C880sw%c2HO9aqZ7)cu?_|-B%HK>J~B9gHXyS*8sd?+PC85~OC$TWlx;}n
zF{Lx+eyOQ1X;*Z?mwPs-rvwL^s0{(T^!9WdGxqMuJ1sC(T2tca{b~ly&mALbX@-#G
zJI@O59FdrXAnoz7x#2TjnRI1}GvdrTmQZI_>|r9wUb3r&U)Y$dZ(#G(Z7`K*N1?{j
ziEP3Wb?vPdRaLuC{V{Kv-XP@9*j`jZFy^op0sjjC^m5N%8A<e<qB^6SAezs8B350r
zg9LxP;MiQQ>aZwUGula9X(Z=yybK$OFO4R^rNfR%tqoU(j!chLY$?f%GapZUcq3ic
z2e20LGD>tkI6cY3qKswWKp>8K$*YvT_keUW0DZmIq%c<j`JP5ty%&m9^BDzFsgP!$
z0@+rzcQ~s$mRl@)w`C7_?MF&jT^DsF68;6(54qL5O7cFdiwXrAenEHQ3>3A1TlR&S
zB9`_8Ll!O|g+(k7&6Mw?mb}<SUsGu%*l3B_NN)w~O<ku*`r%-paZRwf%JFRWJ{VR!
z^l3DQSr?MC=cQt~%;F5pp<e;vK5wW;9G~t;)@j<!75?WrF*G&m2!=>0MV$2t>}kTp
z{un41wy*wX2_A<a<Mm3F-UVl_ZC1M}&dH@c9WV`_iW%gEm*_dRH@se=pT#|#xsGDc
zTUq%x!Aqkq(_fb(7w9^QQ^M^lVfs%j&XtHH)EkzjQEL;YRGuY4p3^-Q5r%1x@p>*j
zWyHu^%FvZe|2W{&b2MW-+FNyG4?&`{_W?`!&SFl=Zx{d<3Vuo+HRI_~?Yzl%76Yc0
z=x9}KNr=wb)ym(q#RKS+CV89Jjfg|s6sre0{A9(UsQQXy^nPZH%D&N?SK@Xc=S6K4
z?^!i-UgdJnEQbxi_dD30>4w}@hm@4OVveI)>l7@&kU_A8i0J?}mSZ(zdN>%bbz+%a
zJmqdu;TS)zZ8Ew1Z}4MWFI;pe;2jbG?JXl#ff@hQNmuvV6kYD{mAuJdEt^!bvjoft
zAAUTsT&jn5blMlo*ZG)-_K0fywh63@Oe0G@T-;mb8|Z-0MwBKB@op#Amh5D>rObFd
zY9(FxT8gtiJc@>biaZS&;@6qm;e%BDV~c2SMoi*$6erSl29?YXbZsBfN|xj;cHok6
zksrek44Beh_D`aB1WJrQsxiS-jD|K+EyRq2#)#?1R<s&7bl(rPnAi8Ds;WB_=LYDv
z22{lI6*TU^HbO|8<jNTLQ#bpxM`K)IFBXLQ_fyWC<oZ1<5EpXwYCxf-FvjN-TQXis
z&Dmelw08SpCYs^wCgKowRG56UK=S27+7YBM^&X{PY~n3&?!{YgRQr!@*`ihNU$}{?
z$72rSbX}Bz29n+>8%p`x5dbUlNaKK=<rL?lMnV<RCv=`|F4wMM?L6w5?8el0O5^?r
z2$2dTek;E+z109Z#FI9_TOpA(?jj}w@#6E#Lu$eg2<$~i@Sv@@5u!XMcvWzt1v^mI
z&YO@&a*2bICOvhK`Yju^1}6hs$uMc6r7?5XC*c+lv%Hj+pzr%j-<*xD5>-e94*@>X
zN3d408I@;hyl1O4?R%QNP8z@!H}ie=Qsb3aQshg}qhjZzHjXM9lv#NIZqk@|<W$l5
zGtm>?oOL4Sl>0d9q<?WEArI#d8GGoqA62x`k1ttPG+ga*{uX91+RY~p!o&`hi(yeP
z=C?JVH<FMV;L?kKhE-O9)Ot8I<Qo!<Cuo7(qlG*~RLE;^vLWw+SqCiF_Zer_?k=&!
zg8}T`#GfnltaTPpAbb{;A_%+n%mZzZ^>j*<O&L;v60PPEXCWPx(1M1}-a$XZ?YCp7
z<!^-Y`86G;WyydWase_3*&00q{@t@uyLNN{a`9gks;e}8GBu=wAGX6V>eI9j{u<uU
zaoo#6+d$TEm?Rh=6jQ`tpSoMVPIYY~<DKWyMx8HeK2xI$6kYYB1)Z-nZB1Nk@&#K4
zEip>;`)V@uh~D`On0YSsQvHP-*B1aeM_E8TXp3T#u)t1BNI^7F(&=@*{(nX@B`$8>
z-yHimih^&&&xh#hJvCc&2y@m}Q%`4jLw)d6^fx0%icGalDvMXOp#iGd0_=t15yvUw
zW95B5@_|b75mABpofR2UWVjSIt9FWQ-rB(MKh`p1`41$9T$G25YNU%i8O`_V5EI8v
zCHJ~A`g=XqX)M;O%WXIXu?NYj#N-MHM`d8EHD6MFo&M{M98=fWt;61QGn`MHPW}kq
zyxmAYtuG=A89b#=h0|-HDZ0T3#V7r>JGGU<9hp@p0{t9W9{#w&rtoN1sTcOAzognA
zcHzpqgw}q^+IpPUe8i)IRRn9TpXo<CxD(DpvM_wwj}2_Pz?V}zNmB_haVy*e5s+_Q
z_$`${jWgdQk6*KUvWz=46EO--h|eLI9Sd?<kBV9)K(XF*Jq&n)YTNW#Sw^EkiZ#>}
z97juH8nXBPXm}%F8$oD$<cC=^!3l4L3AxqkY*8$81~QxX+*le<@8Gx;2~Sl_)f^wp
z?26>Zm}095Zv_C1o@HBeLA-#%E6OY}Hs-gYO>cj()tqiS2`zYOwU<mIR%c}sc;y{7
zz}Ut|(We*szU@3t&s`s?%4c`1b!Y)K3muWsWe23tyhSV)mp*RD$tP^qR}B8NYQJUK
zom#+KblQQ7s94%_@67sRn*Me!LD?N=yNXwHg0o4ejeoQ;d*a^Oo>r=8(P#;#kU$V`
zlr#m`Y5^gBI;*voj<5sSWd5GN{242+^lyM9X#lxQlXb9e8b{0N<L&8HPc&kX+eV=5
z)&bhg<sb|jwlBbg10L}KhbvO1G>qGIddjB?I3}?N;dD~eM+5i<PcXPM!*F~VXM}1(
zqX-}CnC|{11j*7_P)I3y)1gu{QL~vpZ9PQGBUHN+wTG)LKvP9DlSTjwu$9lQ>7_J-
z;A8~i=A`O##Es0oLZ_oZAvi3p2d?AZ=`(HmD*2!FGjr+1#|TvuDgGVvu+@ISO#K27
z26HkuwNFK+VXayDZ+uu>op4u)<MCte)y_K$U(LNKa-Cy`Y>Y?A7fx&0e*__juB0&S
z^G-5;uud(ihp`tET}E!x&5m(cbIybfElXji@hZ1*l$<~!A^MVW&F`TO!r7l9G}ny`
zvP-G=5bAA~J*kbmEySfDD!87Z2PlE$@GXk9>1}CKh%0QlSYdx&o-oXtsX3)rO9+-D
zlW~^?+LPMdA*_g7j4$|AylKyrApiyk%-@sPN{`8|NQ;u2QV?*26lH{(zwpnC9OSTj
z=Ub@&u`aEpPRq2z($H7gsPcqt>Efzb)y}DUhM8QBJCMi*C<zLzP-bLSkzZ9a_|M2o
zzjEQg){p@BAnGfsr-T@HusHo&PDr@N2fw}d!$L>VO?-A>^RqXBcaTt`qFeqw(+np0
zocyxB=`&wE4B`5LS>rB;!n(^iJeG0OOQnBmak`LCl~1lxPDb%IDQa22|M!g8!=9k#
zq4da`H(>geZ}>!BSxgg9YL*AnEvETuN@i0}<x|gBHRL5jRJhTL1HaXaGlm`>0XzMH
zu3Uf9Oo#~}PqYt_Z=5G;+a1`%_Tn2{qo$n&mOMzGx82K^4cO!%P$CXZV5j3lqnwnG
zXn;bj;67u^Pd{Zo6#W^K()o@gWj`TR(?f5Sl%G_U|2t6YUsRhDaFlIMnZ=j)qQ9xZ
zWJSRtJjm+SIV`ow$soL(39S`dO99I^Vjv^R)WzJ02<x_jqfEJ>C}zRH;{7yaeH<BQ
z2w2PNPs!_%D2aNzJDF-4^oSg(p0hvS$l-dLf8q=!VFMe4BwdUUUgM-a)=#GYPaca5
zN-hu!oaJll^4xDiA7Kof#Y1M!+vtg7BV@eelx1Xp*O=v2`_){W7IQYNtW_|msS)-R
zuWn`Bg5X_T!U!yMtfDyu<6`9fpMsdNX6_#_t?n23nG?Hf_@D{1zAVWf+6<6_zLUmh
zik(o7PMo~>rJ4_zKdi?kdWQ)cvV}9KbYn(i>w~v&@V|-RYU&HdNQSk0@JJtjP=pP#
z%o_qw_^DdI;FBNb!f&mE0RWQ&OcsYQ<GxxE4@I$bzpuJMif>xv;~Ym7=RoQ~MAWw2
zqI?GQO}lmHrM7Ra&GQX`2`gf+K#N;CDT^{4#x1JYNY)&_@+NCja1d8f)QUu>ZW*F&
z=XS(Hr)gPOzo{pUAG)&vCLA@Wn*+W%q;Le8Qq#umgZiQ;Bu<3zJrA`mJgfj-{2pvb
n%BvAxjAM20zYYM8^?X@qQ}j`shwE+_CQ_GvuS4=1k(XxSHJqkf

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce43f494dc0e0502ad32a4a3ac257074b52b6c37
GIT binary patch
literal 20848
zcmV((K;XZN6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){;kTi5EY=et|E%!Qz&mcYRjc$M6AjiFU~YP_%N
zQ~QmINVHqa0J=!W@h0Yo2Q0mZY=(76pyK%GbQBIc<O9W1H%^3tk7<C&<EyQ(hhykx
zkLTxQ(c*&ORQ9Vpk``nyds%cH&|5G+G^>|dtnzNR<4Ugjv_$AJ1$0M9B3SgDt_qmb
z@`o$Ns$M-=lxOQw<VI6&^Zn^m<)La-0#}_AKs{$_mw^LwEo5N5Jg~ipumlScREGa7
zU&z)OwK?UARy+&b?iJ7V-U1*v7%G3hIkYJC7_t{5WBPVXAHA_F6seP&7eP<`#%!Js
z*$L#|PYGL%d(m*s;1-4CsJk_ReK+O~1))5zK2>XGOsyIceyF8KW-x2#b)0_OoX(J9
zXl&LY#A1*nKKrZSc%f-M4poq2X9JekY!S6J2gkdgX*Pw>i^}=|X7a%a=-C4RZAfY`
zWSwT5I_!1U1B@gwM)CrLl2vr*7(ht~_;Z22rx+u{VVt4w+-5RmkU3QHsd)#gC6aa0
zGx%~qi+T<g$whK6(LAI{y#YwTi7haSc(L%p*GjlGj3Y?uF)I<fx(!XIrf!lt;Io%S
z`p$2*-6<Z8yGjN6p#y=V%o0yaI!j3?z-z1pf1-{$#a<)hKZ_C`6R+wG?NAr{bJ!*K
zEs9Owi1vg5Fl_p~N+cuF{Iz;NVKWU<x!(7@1>YAYgZEh(OPsv5nvk(<X3p7a3GXZj
zC#EQ-)_Og?yo20xrUPo;KeDm-m$c$FUiJ6pq;BAcakv&{V4C@=(bWnAB{Mt{Qb&{6
zm<$g$5Ttl#d-KoM{AGPZaO(3TC}>ZS>iI|Ib1$?N80UyA{A}{TRv`V0`yPF-4gn*?
zMTK>ol1R2@4MB*jJ_yNVJ_WkckE5+r_H;P~b*azcf!3*6V{mtz{io;uctd0|wVDaZ
z(gG|$C;Mv>6yGZh1NjTo`z^Q^PLepAG=)mC0}=g$FTiPf_}#OY?j9ME++>UP33o_|
z4LkU3C}zbEwnFI@--^;R=K!QIhi%kc#0H8%SFfqa2;?p<G==7p%9LNW!&Qpn_d3lL
zAQV-sRVu9__j02I%V#=e0F&!s=r{)i-oG_!BRy_EFX_bTaI>uuy3Sh4$;Owy(LvbU
z_lR;2H~<8{hd;_mRV5Y?B=x+Ty=sawEtJIPhD)g;2Bb=d6Cr1io6NO!``fNK{6|+J
z^T9%5T_=0q|2ou7V_8BFxKHgm0AdyhoPLibK3kAs?P_p#0&8EF@T7@_R|VXTtPQ(v
zc$zF@A0d{x#|DQMB`b)q;j^=%jdKkTU;*eOZHoW8T0E9shK~a4Li<2EKShnSdwu8H
zf9xODSEh)+$H6ViZfg}EVA*Qom80JneKP_(Hm2o`oL)8}K}&$46J>H;2wN(_?;fo<
z!Qu4kr@af<6XVYo6v#e}NS+!WVcQ!6Mlt2~2O|Qx{7+NunbW&@&d565CxQKjv7!w@
z0**O9Q??{@3c-q<6n5~BqcjGA&C40Sj6$_+a&scz2rR!MPj{Z1?_{II-X81@)UsV1
z@}=l^Y^M9iBsiGcv3}{XKl0czod|Yg%B^UFMq(i+Y!FP&u2Cv90jJAo+V#}a?^Juo
zdpWgx^m*u9N}$rt0_X4(!Lvv>a1s1LB{XOv(odRyl%ek;+uC9pa|=qpdc*c8yEIQ$
z&|kj=1o9Cz2{uzt!Pc18^|Et4I&J&e0-!82;ToI`*8d?1B$4=FgRT|yFZs=z_1=Ac
zrBV&N5wp~FK@LwEa;#ERvHxn8T!nKG&e!-g(rao{lRBJ7k+|ig@S8$E*qG1yi2*Nk
z!N(P6({0}OgrC-y>*=!kaw&Q_hVqm~I~J(|OmQ?%5B>F)+dm?2;T(7=Z)8LLptFdL
z!gh$l_+z|2z~xKNczNh;JO4ZwbaVBjW-$k5RnHjIq~z|({!1sb+2}4(Z<TqGE}Sv^
z)QJ4(gV^O5-f1(U&~>+Br%_)qHsftU4d&<Qc`JmWgowz3xuR|TzVlvK%1<Zz6>%NN
zwxiLLBTOQsfH;v2=6?MD_lC<`_ux%wCtAHsb#K#HXz)(xFQyz$(SeCPdDRVgNZ+)m
zAUf5im(m#%y$<g@<FU@(Wk(3R;K<zJzU$B}lYo<($-3ojTr8N1HV$&90P8Id8}?Ht
zp0Pq7esSl@MW1~>;)egiQ?rWBuz=V;0GKGJUd<PjG=SLHAW~?+VwU3wf_R|CZG3$i
z3_$Jo`uJK5<_V{0%DHKsS@moSyawm&(0>W=bqJVg(egKK$9Y#;vOLmHABS@s3xl6r
zelWP4;M>Pfw78Y><&CCh#Z+rp?yYO0f~)F-cMML(@M}b^lCouaXNJ{?QwoCU1aNC@
z>QL@dnMytotJz{Jtn2MwcTykr@@}UEn5MlU7e1S_0=W1d0}fRXN-htzUboC^?5_v)
zujqR}aF(pn@dTbB?xzDi%ABIt_<OoyDJ9Fp*o#Gng&^Gx2bG-b5*{5fJaM8j79v~r
zNCR0Q<?yk_;Q>K{Q80jbP%B5VCP*MT6ugRtS2jx)a*$I+|4|Tna6(|htXakq5=YI}
z)!2>o_DLEW6-m6~E4+sOxq*gzYva$O$Cv{?yZ$)T$;l%pV10xw-Eoi!vgiZcr0w<C
z$vQS}eJE!A0@l|CN#W#hl_AOk6NH1RK;kOGgV-v9<B2ur(8|zG+y0Z-wAx|y{~BTb
zHp%ukPom5cihhkD)nrReX;(Dlsl3BpdoiTNYRxc-npj6!T|=h6fDgvc_yyEF%`ToT
z_KL&{z*#03;#xH8SJcDvW1tK$3nT9`XcACaoVJ5`VIpCA$-8HKe&<*hLcL7|N7z|h
zB)VavaiNOQod93kdHh7%VuT%A)f&*^4n%mJ&F6Knm;GeV9;>t8!v$ubtn@e~9$vfo
zfHaO1=NZ#EcZ1NcT2xeM>X%(kqY+GeJ~8N~e@rO7PqhhyPCB%_ch*ewk{>ut$D8SY
zLUkc$xlN$`2<mUFgx!ir8Po%f55+%K+tt+M*0p}TzvR;jR;UKdv5_M{=}@|OE=a+_
zk_ToUH_B5^$LmVXlfK=PPx^yXVn7chNHAhn#?}%F^cSzps1A9r_C39!xREeB!|Lk|
zR(bjxlfeiUF7PhS3mqQHC=CGLBnn`>Tn{9kO^Gy6>IDtsazX;o_d%)haZ3m3+$xd_
za~M>g7yu9`LS@m7`kX7GGYA@C!2m+0M1oV5t$Fr?)a92fSV^a$Og^h2MViBkt{plx
zn+dE6S8DfEP-)%*anab2F-PvCe<^#9j~z~y%^~7(Ol_$3A=2~v!+>VSPXYJg6&<y6
z&X(3rA4`InK*gXr^XN=PkILTO7mrB~B0!{V^8G6gqi8j|lc5yKOKIZtAh-XyyV}rk
zkj2or=NY2f@hdgbb(|jE^zFcwyVNlTS_bO!Nm*^-?bK_L-s6q5*|Dpy2|g?yuj)a%
zN)xBF^#b@r)smjvA;vG%wSIt4KV^MEhkFMj{)aB=%iOJbhE=dZ<&}sp$2vE{lEWXB
zOaL?`CL}ETNv6YYf-Yy3iWf6EYJK5Io)qEEsZMz1pqp4kUSN9Sl$Zs>6H{Nwu-zGg
zvEVCZAYj%GdCykH7K(|C>FW_z#j#hI-^ctuSUJ7FHR>6L&Zd>GwytZA;Ra<$Ez-Cf
z-5tm9+9PM5Yw7qYy6K=&_}SZCJ)(S3%`pA@vgzw-c-K$Y((IJl<t})dBYCHMOz$~m
z9k353t*KulL%I6`$4hsFouW;Rx=NTQnDcQHJoU6igy`mpNE{9|W-B{M4bQv`H-dp4
zb>iI$PQgMIO=J<k<Zn$JDG(uM;;cjzTS#IB<5IO9S1A$s&B-da*b;+=W5Jn);e>d?
zjf4rLs@R<nW#}~hL}u{<>BCColMK)nCH}WNvG$xB#IeM@zc0vSoFaP>^-EcI@rrnX
zcn4r?KO{y5!T|_F{<W68j_uA*(s|>B0@kxy7{R72>NU7T1;6@5Win$$91dYcBaf{5
z2{k?0BS?m0M_fDY9ge`dLs(p2TuG4oW%qKUjlmyRKdZfB-WAxAF(F@CPZW-!Vv)Y6
z9Ntn0a}t<ZwvCaGJ5k!UNbaWP|D|xVJ{LJbJD=eD<79BsZY2o&mm@822jkhbEevMG
zQO+7~n<?oomlW9g#O;Xi5)M%RA4UIu8jsE7LsV)AwNiVsc7{a~uHAvmKGDh!Lw3s>
z4%T~IffU*^NeX%t-%&45{mo8L0$a+o2F|<KeMupWF>Fn|;uL%LvkXB;_OB2^g!pJq
z_Qp<Kb~=~}JX@RG1;>!e{qb^-)wl>g!(C(QvL!a^XAY?VM;A~Y8E}mHj<-42_2H@p
z;!Wf=W!<DSOId4++##>8KUL{yE_nUtr@HsoOsU2qmVM=s$9#x(XF+&57E{D3Dr;wG
z3p#EgMyqYe!lE5>Y%!qcv6k~2&f8|;(@SsWs1dBeZ5K3Z#A#VT95Zhj!M9+0fnplW
zawP1DpnLkQ|2bOr-n1Yc!g0?`+HWJ9t<J%f9_0`3fjMqphD@mB#bN4Jm(8{ZjFIdq
zGsDm1!D3IhchJ-Fe|{6Cx|J&vyaS`!x0PfOb+h+q*JX23$xpTKNg)X>ijwR>6kTcw
z@3T|G*N#K4@5D_Z*%4{tiM)vc-31ibf^HbTVWFD}6E@V9i`Pl-Bdom5DCYYzp%Va4
zXY7dtchkK3*^?Qz)mxxFcU;6jIlFy-(Z^#f+DC|pZa!4%ig`iGQ!CAy;RhS)1q8Cy
zw>2>wRwVZdwWY8H$a|+x$;5G|ptWZtPoUz?9ayjlWRG@_qACDsdT=oKeDf@697Q4@
zPPA-6Cy80Jl}yfFI<d$a^5uIFbq>tn79N$zsjVWJuW3~aG5sW;ODILG3@RVZZLnM&
zNdSVAjeH!Gmh_oS#;(*pmaP=}2QxCWUo|5rx$`k!bi8pguk$~n;j%&_&tfyMtgom!
z1|+%_P_t-A{r_Ejy6@1$c_BHUn6RrTTZoH;vAsmGD%`6F&$vPJ7$rrUuq@*AX{TJ4
ze0)&(v^nNIk@Wp++lJg6bNt~)giWtQB!8oj1<`FPyOcg6&X7k4M9-EbD5Nt}BX8{f
zPt|}fzva+Ij8_J<y;yQ;ZUW3;kpTBI+N|_SFP@6H(}$KlcMQ9aklwSYJl`GIy1-s(
z{ksJrJUf3+GEYiU4sy4XR4hz9{5un;*iUTAsL(Ozwg$5oo|euN7CKjUg5SH~Oc&Iz
zeT45pT|J@;lIG)$`~n*L$60zHxG67_)E9fc`4!cs;0}+)N^J#nbV<KurhjV#X8o*G
z3|UUXrF7>AyjPp8jSc7gDKPdl9(7>s<)x=cqi{3NUXcwkK5zP>08>}TVa2EN%8r#<
zvpfj)Rvn-vnSm2pgNd+9@M=))z`t|n!;4+>-pbHzoJd94>W<HtC}^{$tzZ4~AXgx;
z{9m0807g9zY#(T>YV*d(Y4^kT_N9X|=dx!+6TRdTt}wdzT8&E$OuWKYy&e)^(YHW-
zXD2cbzXoM}95DT`0WE98J1$m>Hic%-u2F2IpTRvui^^$_Sz4T*wvER@_i^ajh|b)Q
zs|43}6CybWoYyJA3rWicBrCP0pJ%+1gXKI+rp|^*HbqV^c$}wK3vu<R6F~jB^9y|a
zZU_IWkD@Ngi8yt*4;aCr6VSp&kd{bkQ*99^B=S~Sz|3acy?f3hup;NB#@D9gAn5Qb
zDms0_TO_F&oLBwh*=2w7_3kw#(blpiFM<g^8g#J^h@YiWQk?O9j5j-to~&JGeX_m0
zZ+&yvsgZvj$EKkpx*m2pz*rVTrkEC<*Ko}e<AlhGKB?pc|Fs2eJ+feg(a}wTSz-{-
zhRr{f0wpc8l|2kqIsih8zyO)A#^ewx*XkNp>m_CdV=;2dzDC&*T^JTtXScM}F=;NW
zNT*X&kf9EHCY%P4NCUm)?q#(hwVU7~0$D~^whOvf==Kba0_Kn~L1Qb?XC=}F2+k7l
z-(YHov}Vl27$)7!YJnak4DIN|cH2@`%Ba9A1i&W`=wLQe<JDPuiMtt#WKCYdwir@f
z!wm0=l0wU37!=jZ4_OJ7zt5CuT5JLRB5zCoOIp-Y*n>Ju`<r@KlBwCkJ{u+8j}y7Z
z@k%~4VtD}0FN|J4kyuUxoSHdTxc1w~ji9{&O9Y(<=}d{NnvU55i7At~eGMb=OWPD|
z;MwLmX>PBbxs9tkJ#XB=>qt8)?ogqX)vnOPwzVYS?|GeY?;nNuk5LJ<Q(?f?Dee9j
z?Ue$!%yWl?fXYb!Q@E}y8KWdij^IW{B6-RXpq-4qFX~}6@bG79T(0?nkAP#H9!~OK
zZsreIB^#b_g{dcxTJH3|yKD|AD|kvCYZfis_yY<K79t*!z-GTnm$|5h?u>V70I&}1
zGq^@a5=Fw^_yD7zZ4p;OM{$@f-Jz$YM<pMD1>BE>gL9+B<hTp`5fy7qpdHa8y6$Hu
zj*n4bhoD5b{<HRPVllugD=#N?4@(YEX3BDQbW`d>HfRQxM`gHzYrI8ob3cJ&%ToXJ
zrr~t+*WygI)6P$p5Y@`LVvz^dSi7vx{GX-2-tN=-TIA!jdD?*!iRMDq#9LA~C5H|R
zV9tCr%OMZiIuEJgB@`K@ssgoqlvJt`MN=1ta%yn*Z22wD8CV!Xf}rsn$(yHR`pHKa
zR88{f)}8tI`+IfC%Wvf9Xal0h8)lK4`sEMalp^OxhE;HvMc1S+S;x0*bq)L8uEu1)
z?3oFfjaCn+<l-U+{-$$h6*|!)3n_{6*?gT|xf!e*ah?v!$%QM7|4oK&wH4VXCsW_g
z&=is1={}+JFA*2b1l!gjPxu9!UitO*d`B`G1wD*qQ-$;Bu1t{`!&^XcNP61^IEJ2_
zEGLx7h<q)_adilzd(+;cS+7rIybhGAS%4#N8uVW=Y$)P*ok7{m{F1(8Jlul!*y$iM
ztu&P|*hSAs&wA6y>R3gO6-~;`XN5xG^plb=M8F6Q;v1&+3j8~V+?-1d7eF<q`gh9-
zwkDMj>cvj^2#|%+Ls?XnC_-*yM)W@veE)YXRIh62Uc3o)eqyc_z&X@|kDPBD&`VL}
z0xeX;v&^ntEsE>Yap_5^z(5x^Su*xap<Xb?OKmAuz+9nA*W(@_k`%j9eZi-J+(oEF
zR}d$<*SzIn(}1xTLjpLcWZwVX!p>v2pX5ZJ(0q*UWe?!uU54e;B!uZ|1mdh_(}w3C
z;O))W+OecKY`2IRAbz8kwFQm%I%Id7ncP23GUBmHJFpm@lW*D)6sf1cq93n1raU~E
z`f_2ZpCnhEna<TiTLL+EYuKwH+zUIjPZj1un%LJKQU02bmH?sE2mC~b@T<UcY(43#
zR~}VvJH6d@rF)lgyDBUR_<_(rz=_`4f3BB2f&4>gHX%5$EQ`ddb^kOPoCL8#qC?Lx
zH!}6!A}*9;;@n2^RZZd#w#f;=njd*P8wNrKx~CT&3mQse(e$i|4ObBhOBd|h?2iT^
zcPiHp>d85Q^s3pt{^|K`E#!SLrML>Cd8_8GzQ~X@0k(+Z-bGvIo*7$~MIEAtTfm<Z
zdCv-{v0o$j<+)N4TQztd`OpbSh#b%qbw*;>Lkff?Ch#aDv>3fq7~Q~}8e5{Kyv0i0
zqCpQ8&&b(?4_1l`IB8Ywa(pMDJbUu|!bZ$Kjq5U`Tx^^jkqQ8RwmUWs`(P_k@6xva
z`7VaU>&@{Uhpc@dUt09|3ne6<%5lv+NPXJUmM!Z6HJPc3z3oB(En(%~%rBpYCxhpD
zu+W}jds7K~kGM^PdUz2jer4gPPj?o~*=;g1{}nBR`lyo0S}nRn3Q}Z|>iCg-!zrwP
zA7f`21fxw``j4W4N}A(VbpamHAxy@nVbAJISV9(XXIKvd8NFCv<V5q}KD9&dk@Wmh
z$R)#j!*=UitxJ2CDEWz0HQ#`r%SjDB9&~6wPD-|KJpU_l|Hoqq>CXZlDaCH_!-jOM
zzlJg67d><^BMs^g>MWonc+`fDX?Ce%76-9cTmtSWPn0=s1%~^sa8QleZ9`ZCjGGJ*
z{O6f9$*>Zqvk#K4U_@jP$}1#KcWb)a0mXWZg=HaDg9)urj3_VqF4D{0I{<v2lwK_E
zm?eu2v=8pt=8`V)=}-s45Ssz0kDCzVFQXhqhQd}pZ|H>=-dy7A6Bkbq`{ggI0^w@!
z7#&XGAVHGoP4&@5EM4um0z1x5cpMrCZAZ$lFgf_O6~w*UG4uiJM2i5ZM^S6<(l`gk
z*L9ZQ69_=+Jw-PN6%_DXe*m$~wI?>cwza_&fvB!&+iL}H$iaWWDf(&+o>xr)du3qG
z2SCe~3KJf#7cx6=5wm{VRq*5in|iyRroR6{U~EQ@rr#bqOSPAzO@>t^*UdF|%TZvR
z6q|`v)X{AxV`#rm$zb4{pliRkVbi!Z$70ZFA@juHgQ38ws+of?tQGQf%>@XVAz4k%
zk?!ONRK0s_ixTED5V<jJ>mXqlu8Y#a4-tYGb(<WDsrQp3GmX>##o9DT6Dv5fNI8Ur
zPF^ZZy<*Li3ua})uYU1jkC<;MHIzR#FtYh$s1A?PK>>s2uSio^Cd4O)%2l%5G)~Ih
z-06M&BD|v}Y67PYgk`kL(4}4#v7(jFb%VNCDT;f1N9glZoQ_Eq&Y!YP_Gqf0rm<4R
zVR%|1o_1H#?RwFfL&B<T4$7Q~uNXBm&OgHAAu#$X6BJ3uD({XnSo+k4=R`_0bbr5=
z1t6e>Bfe<Z1ggf>684U5I2zKp2VuV;-T@usJhX+>Imnb|D9Yb<iarR{*Zq>gyB5Eb
z?5b~$cO8krPCJ)$e3GGum>;^}cSGohxO#FNef{oYDQTcFpRVK3BSp4<=ez~Itbe~z
zW(NerTrEp)$X{hb5BwKgeI0j^wx^h8+fWJAQ-=~rjgJ$Gr1(tyUJ=J@!DGvVbJ{kp
zoP~Ei76AW7iMZ(+YHF)MD1ow5D8{)qIp_=miKtNS*(6zH4$Afqf*<wqkyJ#;Tsy22
zM4nT({hhU{8=N;Y+Iq2I<KaOLx%sLERO(0q2Mf{jeQm3#@7ExyM+<HD#AKFi4jpL=
z$_KITVh@)rp^!+f-V0ZV$dF<|8(G3=(gNDN>tolWz?#HO<0R)G-Y|MKPAQN|^otqA
ziJE>_-P`=l;S+ZueR7^jDHT`-R7oQSA8kcM#k~{?;PO$3jDJ5kvPD~;Cc^}(4$>wC
z#TF{Yn)V_@=Tvq)rIYgc9h2+9&;|MLh99U9FEVuRvohOsb#iR#jhSC;dxY|1S$k@S
z5<P#@cp^AS)s^BR=Ie-)3OQ4m5Z%8QVA1si;V{Fr9{~%L1l_=lAm*tEguD#Fn-hSL
zyhzcsXK*ljGTt;bvPdDhK{|+DW7?X~4%Q-3=zkVwC(W?rbHomtGTJ`$T>oU_u79ES
ztdgO*0&F=)p4-v(lG{@+{dW++QDE86v#Jz5G+7Sl(T=SV%ofM77jf_(U@I+43I7}<
z3L15zc`NDLeqR*|<_3Dj$yLmf(_-psVtEp0E9&*`qN6X)`WXh5lQ7Bgtc~MlQ5ro#
z69xvu14gR_kcYDOIZrajif&jxQ)?y!X%LMR)%7K7gND;*O@`?!9^Mf<t^p1qUfI_)
zd}^VG35o%EhV(|f8C^>9QxUvcFA_5d$LaD!Ch_k0++L7cx@50E!;7H2i+6_NG_U;h
zH*bvNO1#xdy<}s8C6*h%c_=4{jrsxGmYgJ70W1(B>e&pZD{-1Rmr^1<`tv;Z4xfO?
z!Wpvok9~GpK@(>GueHbBojF~5B3KRcXp)v99%5bq{(7|Mkt$>#cT+tPrCI+UW(k$Y
zRYe#?XK}G7>nU}~KWB?U6rP!C`cl5#u)x3{Iuh%Oq^d>Yvet|gpr^Ag6SoU^7v)yR
z_<*h@BxG?;RU?C}igB9rL2s4;0ovpGi_D4MbC$iemJ|MLY2*`N@x$h~U~^y_VPATI
zrCd{xL$k$Az(E9qi74>O@VQVR$E7jOBkUufN4E8_M%nuQrU@&G$a0Yw%=yVff|tcy
z=V-RL1Giv&fskG<q=AZ+u51)eW=%^Z7Zn`J*8nwq*{D6EK>iCZBkj~lhHvb8uzHU3
z3X0*0B(}Wcml~vZvf6jhbd4^!>s~%1{;MW{PY;-R2K&f4hVm0pY(NT6&^h*+_t$YI
z?iu!)98tPtn4q41NxpVuBmKm2#b^ZS((>7}ut=wd{(;kFOdXbMus5gQLVR)TIL=)B
z&-S>GipQ7FMHgL}Mdfg03Ar9M)46$(9Y<t@yIAb<2whAap_<BOY^++(^geaE(0d(=
zMwhhTacSZ^uoJ#D0xip=^T`d-0k-s9R>I38nL`)neX68{A=Bz}h@XKTgFF(g)>r?Z
zpjmx&n|5ZbLo>b3!N$85$Gj>40aHisbhTs*h8Mc~k+IJ#aru6^`7o+h$>$(wnHPO%
zUY87ceuhT=I2Y~_ado6@5gbCv8;QwB29meJ;MNnzP%b79K4MAue;(MiRi0c@e9lKa
z>nw8dSKN0eYwkI?_6z}SXA?Tfz@d0G8BR`;7k>}yH6a{tcWEz)f5A<+@gfy9RhNKF
z`m26UU%IaVzp5Q=hsgXPyGkMPo64!K(&J>z^fhryKddDHw^sA4xA3Z8E$MwgCfNvl
z9MBtAsAl9{_CCJLMuzQ?4v^=g%oOT6LbiWI!SNZ1Dv1dIlD>8uIv5jYT-Sx+Ti!;w
zLz!M(n}$a;TlYHnxY1cyqOQXRt((w^c`Hh&`Z}%_FyQ;2NmQ!8bvp3_qG-R7=W;Ek
zUM;AA*<Q6fd*JG8{o8;Q4IB4!Tz@a0*<%tOOrc?=e0bHnTC3dp=EKzt$A4|Y7l}w5
zse9kh6wfd&TAilG#Kp4fki}{hYU0B}uh5!FdTl7tR9KbKR%w|k|5k5_=q0bmVVCS_
ziHY;Bcn<M%6l*gtdIHVrufCs(jPZwZ@vZZak3I<R@L<;4d<DM9$?>pU{dPGOp=kx~
zhdLIL75{F3uTOj~-=INYfJRYo@9$UBQuBUV7rab?zyoU8uKk5@qzfQ>kb=+1v1_Lu
zp+gXz{j|HJVW!i5_v&U2-YHZiqb8M5vF^B%X6JvX9^Cut{P|^#{zg3~zpa;%3ynA%
zu!n~Or{knE*|%2-joG9032uH<<ihvlIe$~<Ga7>?90YxoW?`g)51&cSGZ8bi9T6R`
zf#+bK0T;=}V6$q8r7wtB6+eS7F6v9rWDX{5EqCo<`ax?@@nRdt0n|6Ne%wW(xX-HJ
zOC7RZJjhuGjJa*MRck#r{SB?xEaM4@)f%5brHYMQFOC<<*JIgJ+~N{t$g}T8Vf5b<
z&99-)O~oZ-<$7Ha3afO6&1c1VRc?*&r|Z}C2>tzX3Fotjr(>VTd~9-<gMR(cxa!qf
zt6>Pp)N4(6IW&N^)6n6eE?(z@k^kt}rKvP~9;^Uh0}A;A=>8v_`ES8Zv#~pC8w`+Q
zU<k{-=Be$DYLu{$*@7iwyhR<JRA2ql{#^@Z?KuJ#1o`P(C1IDi!-39veeot!n(#D9
zF3<Orf8HX2Sk&Ls3GU=^$TdH1w(}TQSu7H?N(<rb`DI|vcr<ok^7QmE=cnt|g=QF$
z^xO9dibH2Xj^5axR0)TR6BbAUT2|Ses#Fh(P}RZ$B`e;yiWTv~hM4HAD7Pmet*r<C
zn6F<<;UJzkO>xsrSc@WEa6d)4MU)_k3<^@sHGMB(Aml&LS9W3tGg@Nh(K-v;Cb(@H
z=-h@838Y!AS*6h8z<rN}l1jqtZ2_G-L&$W}yD*>zvE65{wQo`S!wTEPqL$)Khq~1W
zJE%(nWS#rn*o2^}w|Z^NO&e4jll={MGKmW|;Y>UaYvj>y3q35%1T=jFr5*zw!=Q_8
z1KHZpI4b^+f&QOEOS*wVsaP(sSRNu1oc>G6+-c5)+GS70*Y_GTu<pRooBIofep&H9
zkV{mbako_YJ2ErR&zt{DIwde#qIT|cm=w6JQFK;7w6w@$eQ}<Nu|-syLq<N-lX4fy
z43C#dx`ne8FL?8Lp1_!<M`M->;V~{=J^GOZLIoby`JI7ZhSW|ohL^ZB91m|+9Boyh
z*fH~R^Z8zh3*6@&f5Mao{w1yYt*O@xZ$x7v8WC!yVkio<mqG_4l6fLHdU0fo#Z6Te
z{JNb6J6yqo(+}@X1G%JlkZ@S-fxDEdvMVVP&=>s-nMYW!^Dus9yV%tHo(gF!wlnz!
zQmnHz3`-(@kK*W&u3za5119maKrPe*r*mZKtu|3E*9mdm;3G|@8wAnf6^*;0%GmF$
z!uPq=NPmV7=nVgwbL1!)tlNQdGT?#&+0c%x2Iu6WWW8FC^gRXj_+Xe%$M=kNnUcY{
z3sMg4uta(qGK#lq<tXfpoHuRZW6xwwm2Nn1dh5{126}K%V6G2!ii;uB_t_#=HWGMl
zQb4aXK$t};V7l!U7iPjkC$f`Z!6whi>QgQ&UI{YiQ#|VOY5jq%jvw;v?_d)R8&t<5
zXTReZ6L3rDXBO@r#U|0E5F2p^dIvlT1vz0gj%Z(r8nsDevounA+dyTYX-Ce(1>R7P
zelxXVycl#NqzZ235PNFPNHahLq~UeV1OQ1#Zt~->#0`720tX2F-~m%m;0M9<iv~ec
zwkd3Z$pvPC?!bM2kX<%zvc}d~K3`D6J#-gq_5r7s0}5xwwt;9e5V{IdtEWRDZ^EM3
zBwg#LfSb*WT)M2vfAMdX2`u$1*YJ$BN6{!kCYmSS(ABqRk9J*cn>#O^n&5@vpcQ#x
z{BIe+<WU)UOIRo`+cEtz%%wd>RKi+AL{f{)|4LALgoim!JyuwILmcXn$$vA*i^Y!0
zxtPgI9R~+h+h|;e*VG4yAiV69%Ix5h>lJ&J;U)cb{ZCxz8*NYvup;v!?&#wR1!3|V
zTro<E_le*%d;34}w0!ygwzd;?iAK}K0X`QSzf;B=2kEM3-IoB~EIs`Zld{ap)>dQ*
zBKY15i%GsbC+A3;L`*Owr&+dAx86y9jV<DA6W9wq%p@rKplf<>YOKzO^}|{^4`F}&
z4qVwC9CVEysyqSXA@S-`1Q@U>2MB+3{OCyOdh_0m>&>G(pcr71@Wp*oigq!qz9+GK
z;1};u+^GH9Jf-<gz3nc^2(+%M9a@UoWO+UJo6h+WV_Ej`8DV)9kMOa*LRY!0Qjz7E
z*62014{io+4$+W*8`D;WQ|%k-2io=TE8Rq+)Z|?U#KuvTWryCRjQs(R<t`I9ZC|G+
zlDO;aA1F2AN^e#!HJq>5D@kkG@P*w?<N20kF(X#($}X1teK|@$4+j1yp<*H9^q5Yg
zzVX14lq-1JwY;G`sQ5!oTPkxNY0nQ1LjZbOZ|&Z`1F)qg;xX)>1Eo%rIA(ztie$er
z2b4yq@3()p@efp7pil1^dTCWas~{WN$#1Rn`)4u4Bw`-{H6MP3bqHrkvy`hu4iL&g
zYw%R0;U;ImTnKIS?>ki+S7lR?nGd-kl@D+k=diT>WigOtQTs3$nLSOr+!FO550uh?
z%Q1pNNjE<?>H$llif|OEDYSNfoJFQ?JT5!xsY60va+oP4rB1huxn%(v#jae3Y4`RG
zlr}VVqhntYOr@RF`Tc~j2PIC0JVMM34M^V_#ej}q5A-OK5aV|Sq&<|c!gXQ^g1SOs
zM%3ckDZL@_1KkTk_HtW8aw3o%HwYgq0rJnXWS~!V|0oGlq$-EiNu{6t{1aAxk_ss9
zJt9HrlwYv7I8rgIu^AfcwX(Z2K!qx@nuhDJhpNw!%_lNx5%-AGs0L&&X_+Vmy>0=a
zp-fJRs-WZO^d(u*0HU!<jMmCIA8?_nysHyw?-Ig4Jj?@>Sbn!u_dIaizb@uix0k-O
zw=$&2n9P|2bcU8WvUAp~Oj#Uo>v8J!)!VsAUO?})LTA#?xW0V(HNd;h`%a_&iVYcL
zguEm48(pYw!x}dGc)I0xWv+?l1wfRLz4eo(=B#n1NuuuplFHU4vcEZICjTYuhdpZY
z({G4+*l^q_Jw?T22q)5gbt&6&Ylv%Oj_tDTk34D^&{@5B$F2i!L|5sdRTj<-dR2+|
z)L#kZ<eUp1nDrXZWBai+`DLxwNqa7ES9{$4x-~1#<xoMHXk_Ce5sl1ZT!d1+*v-6=
zh{FR09w&q5^bvM-?dso+Zc7<A<Ixq^75nvF2<G{JDjWED<UI@U`7AI`zh?cAE$<vn
zF0N9HLR9b2OLJ^P4;s;}fj>xX{f}!ZRjEvMV|D24m@$Sl=enBh*mjl*;(H1I`eg_!
z`O<140yuI?g*nGuAHR{{RJx0%sZK(>dqUcWw5gnqe_)tT(=U)-KI<N2>5FqX9X6M)
zQH%B++&uh;3#=>p>)OW#z@fS!N{8@Kwh&OTh2WYlYP)~rtb&c5D*Uo!iS?Z6dlUyT
zw0aEA$>cIP=q<0au;|NlkmzXqi9nx*5*#GkKAzsSqogR*>JF4<r^LbE)nB*qSa@G{
zM*&VNiU>CG2U8d+E-Gp>{fY@WFkkt<LpD=SnO)01vw{yIr9jG@xs&J(>xO^RO<?T5
z`@`S_P`t^O<4rBNb20HLW0Y~Jo#yTLQELHoIPApPY~vN2XQMZo*&3ZvC@1vit->-Z
zEMomwKl}j$rk6!8hmB)Wy2JRA4o7a%2TJ7PZ3Ku8jY8CCi4BAGPV=s52D$e-tEdY5
z(6Xlvs$6ziv|?@@-bwwWM$})Yx$1s|q2xc%Tw^QoMKg3T$SFdMYOD_ZdgjwkNNQAB
z41i(!_t4sM-BIZt7d5h5lPir27Hw#gpDf2NUzV-b+cCfMwjwCUzNA+CZ3`*4%&XUw
z5s6}0Ve<5fZ$q$C@@FT8B$z_r9NQOO5Ib5Xv{1i{sImmqm1OG=%)sxg18^%DT1S2n
z7Er^A5qt8131DGCcFdVzimK7W1%2MoEx<puozyI&`{K57e*3d`;LIE$)#XGGs)Uqp
zR%DEoZ~KiJYnL-c%X;&9<)S{3tr^gcg=kGw{O4V6IK!FRPBpE0v58iQ%1@jJa>SE6
zO}DOm`dzCg!VglV1o1iAs33^Fn)R`|aL3wndfsU~cr}0^N-}WS%#g^%*>lO&oVzFs
zPmm}oP$}vs)0ivPbcvz4+)uG!9Ye4W%PrStn`-kzroTJV^~ACq4LsJV_Zjc3;-UIN
zsF+n#cA_5EE!z~xdp8V)T%T}SEC|zv#D&0$IxQ^TVgoc804&G38kXrf#?AhTkfMJM
zHj=7S>25!h(IbM^E5In9Oyth3shIWd_GJl@@Kr*#Pk*WukE_my{cf1lIY<gJ<?<Wm
z{0N*RD|3PnnaeZ@fWt%0ec)pdoRB*z6^wq2HZQ(4pGXT50S*64rQ!GsK5s@=gi>|>
z*(Ar2%;D<aJpZh$Clix;vtS?5=nltU1@MnoZZ7Enx6xKAspGiFGN_dA<|!2*T)q9K
zU!^v}To{Ez__eyt<EVzGizNmGSIaB9f=ePS3Ei-NHGh!Z1I5rj#dwF+)w#r00+sC*
zXJ`Tp2)SgqB8FI{r6W*6IZU4x=mvJo8_f2NY<I4!lR2DQgt`yxe{dIrjJlAu=-IZ|
z<GfswWDAo0s8=tVOfw?wpbUM+pG%U;`8z&Qa1@E~r&N}GPt@#s07N-3Dl|nl+jRn?
zw~%>+jkVB1kuUqoI{>?|OZe&uEzDz3eDo`>z4*IoKTY6S<rNDbfaxo7K)(Ewi+!Qf
zI#kCA{3F|ARRaU$=)sgehQ#0uOSt=pef)v6cM1;uNk4Q+P#`!&d}n$Dd;66awg<;l
z+IQmNaGS!(kH);+q-!4-T<pY?FW6v*yO;zt>ES>Bp<vHV(I=J4Uo(*y3rR|orRYAX
zz5axnR%+L_;*t)A2Kvu9<&LTWet=e*uHjs=;rA^mTnO3$Z56FrQYy1J(tB*lIJRAy
zsj9qRam1`ZENF|XYYmz+zo4AG)hD#-4`ylwvID~DkXW_2k1r(r)2{e*++*WwE|Jo`
ztU<ZkEbIXooEb2yK~87x6Uf$@=#M9vY|2c4G832|n{UdyAc;_6LNXZmc=CA3OgI}t
zA5^WrKEGl(C|X6hEI46E_;CscCd)W(Bxi$q{`v5{>+2J?>;N)J$7>w^yJ<v6fAMW$
zMW5F`jYy4vG*&!VGZ|24yD29cvvwqYxf4)o;8crlL2v&8itE8($!mZ$Xvn*l5&(dz
zvK_fc^00?8>wn94=nkB#q4+*-DIM46J-*_6PKbZ@Izaa?a~1SR*$8WFid&GP9?&DX
zL(*GC(d~kgJ{|E9iRY@pTSH%E*4rvpFaECCu~Lm3H??aA*y+Fv8qq*(Cvy+3y+>gS
zI@{5+wj@E%`;Sz>a6leHcB{=<N~Ry<2ms9AbrtA{TZC53SveMju<1GfN!#HpJ2Y=Y
z7CChgGySpxjJ@>O(P9ikP(rzN$Y)<HkD**@0$JHpPusU|-;HBU0zl%$Eh8zGe4x&4
z1kyh9?s0U6)Rk=_(L$qAuhx%a8IOvyFeN4Mc<^hOJo^M=c;=Go#-JL42{bO0&{E$R
zgr()1i<BuJ92(7NW*t?>3X!xc1j0js7WpPYI$@>dxbOZ7=YK(yBI3QlhLd30$+$gw
zELqwkSxQhn>stBS+5&&e$8{98hZOoS=fZ4J!=K$Ym}2uEf)gYM7}Rcpn^X;j^4RQ`
zM=O_J3jf}^c@EPf*hnkS*k8}wL-Fgln~pX&KSse0+y_8@CtE7vubnJA%$(~km|@MO
zbsu}?1E9p_)O72Io~12<UJM`O8|(>p!RvNUq~F@s+D8}kcnPOBXq@CbKwKe3T)hP^
zKAWDjyj<1DkWY$d%~y=U(d8&x!9_aYl*E0V2x{JTvlh{ia3VyqW^Q|}xl!}(S?QW%
zjLHN)<t=?|3;x;n=YlFHsS}T@A_x|KdQ{i|vLbBx(Z7#TPe%#wAmWsY=={N&D&k-q
z9Jp`c+~@&H9=;K%qgt@Bx#iU7s0|m#EOr<}ppsn-uyg|PP2csPm@bso&n<qw7!ax9
zsP0F!U}fRmWMG@8`;{5lFooYbjqRBLy92T0J^0T<LNbM{;4?Gp<)~XEH4RZ@ccq}C
z9+9QY%CGZijzI!Ubz5@7gXA{-(NZbksj)>)`IypdGEe}QK)JS-z{Kr<5_3ys0F%x=
z+|`KWlA|x;q!i`Lahh&<opm1>u@CN9bUpO8$V&GLXVs%$zThkeMJ+3wxUAx2G;U!V
z^Gs`*n6fZ=mta>2TVusdvhiFO{z1X7m*B#4hZHs3Pe$4$p|wsV3EXHLE%)BC<0LOg
zmZT7I*U?Q;{0^m`9$+#oy(&2#yq(#!*iig9RbJj=U;IcT;JbId$qsrPk<#3E<b5zQ
zc&cFIP%Q_h9W%meB?)jsxlUA$(cgGEVfkQJx(is2JVR(v`^798;b%3e|Hbe-Z{06W
z?40wra{hKRT-urB1!X|CiE<LEML>T7Yz~Ju1(LxMNvV)9dYQW9l^qe~OzS@-j=ulY
zqd#V`>-xE8O_eIV$vN<%!OTeP#>!g*0Hzc!->bH*3d?o^;bsv1W#2qz##@#ZHUt1%
zJN&%9;cUf*5<m^xo`5$+o;T7Qw^tQF@FTk1TmL|Wll^iCIR)AGnlBh)5oi+oOCOh<
zW=;v0pXreB6M31`OqnZGON8DEN@oJB>AIB!O0jMjotCF|9G0J63{LYn_s77_1E?4W
z!k2z~<U^zCN^#SIhKFFuGyG?9J_G+m0O-FzC7kYl7xS*_1LE$}uVl6?MfK(TWUG2y
z++8uDYcXiqh%0GyK=CqS4qitlJ%2#d4JjJ~347{H4ETf=5@@7U%s^z@qd!(5J3m~G
zpoCIPyI>>Uvk`0vr8_vHkTzxiF56l0G{Vput?x~;)1pPxegY2<2cZ!a`t26w2b5XA
z)E9SfhW_bDs$yxoYR%pqfY|v$0E;$Aq5UkWujlp&LCJ8kcamoK4r_*wiPqvul6Y=_
zOwaA_fsf;&p`Al_oZm=X3$dUZo46Vf9NkwkQ(HD-m3|`(!!`NhN|E@BJ<dCGR*s;8
z_UvEx3FvFDPA96UAC}%vnq+LSqGI=`3qRK-Kwx;Y0JQctz*!%L!ap0(-{76B`3~UJ
z!Jf_nSo3hT((q>1r8rBm3*a7mcRTpbzokH>ROc<uL-v$*e!?(lt&xSe^WN>iX`iD0
zv9YPH8~RFaPozhTuUq55J^5SW9U-CcQeS`Be@drhGDXRbcKi#`484rj`V{9&uF3cm
zFaB}@aL{sde-{s!M^9`!<E7xi$Q}S%{%}lK4+B1H_X>DoR_U%!bpq*9UZH}rya%Sj
z#g2=(^?+;4($5;l>*FY!6izMWrg*}osH2KbiG+C_%(*Qr&9wUTqgiIz>?e<?f!2ur
ze!Dn{(A70rRf8ZdhJ1iCL2YqR5lXS+P0MpZH`Sq^`5kf-O)Aw7Wn>e!cJyvnYR}I8
z<q6$m$+wTngN-r~*Bf4eCN85O+ovIM({xxSllkZlibmYI+TCmrZ7XPFk@jNIdOeKb
z>7T&ngQ_BXq_c!lWt~;QG-Hg@X5R^o>MX*%Lw}(~=k)dw?|K*Xx^SGfR}Alf2Me;E
zdf&vJ?u8_lqk~wr_-}c4J<vJ&HU-8wgDwz=RP|n@m*wtMd(-j>zKdE-7V=hsLH5Dr
z-fqClnl={ZbruG@h#sJ!i4@U`3I2FDafn6QIRta#<rWbbFrh^bM)t&VEg1c(s8$rg
zMI;hfP=Q|WTp|#(Z$(u+or-Fx!w(50b_kgYs7cPc873)N^_-#7E{nUdfggd=w%&eB
zFVNaY9bhs&8E%&`+|qJJc02}KJ2Ze@7%4wG<-GTIpW}qG9w>&J#Vyz5=OZ@9;V2Qk
zEi?%}k-Hv{7@&C1;*9<a&dU1Q;2TumEPw-H4=KY}nsL`xDT`%N8&5!56pF;*rEY$;
zi}t|5xShOBd<1wI2gWWq@3OcAl!5(sq03P`6z%98euCiG3<*YgkzlT-Iztz>CEWa6
zsS}q0h@<nroiX7s*RDnx>b48;Tti6GsRb_}A($4<m)^5e-D$NEXrW=D*AG%0K0HP2
zmF#BvIBw=JRUHe=Wb0!f&qnMh%XF-6YpR(m?ug4;Sn*SIO>aKgn_nYBj<5}qkXfm^
zQ2N@kan98Ib`NKMF`~Q*r$!n<Y%pSr8wV-N8pf?q8vePHAEF(aB(!+^rB6+spmNH@
z6`LupQ7c?+5JSB6h-`APPmp$@uw9^E*C8htTm?zVW8NI&)pKD0NN##_ns0Gdl(}yZ
z!MFr~sObr=*}*h^@NKZ15;VNJgur}+-tZ)Fa~Y*AX=hE?pO>rE6nB+%w+p31%~$Ci
z5nQGxLEb=1O8+e1nFp(3!cWj#94(i`F|`bf-h1(Vt_-BzxWQ>nz;3kJNNXV5mm37z
zC9UIn?8Dc#N*9uMva;Gb^sTAXIIdpkiJfB2{u<es_YjHq?s6`}pyZm&-3kYk_8Q_A
zO}Rv-ofMBNpLjp#f6XymR+ve__)$czYUmK!=^OsD1t}oX*rDWWD_+otYiui04035R
zt?1D=x=mhcfV$Ic#YA1}btDT&4Wgb+8g9S0B5c#9o=P^5e_-=T2IGYW+GngS#~qmS
zF3Zx&!0j0Vd@_AC!{dJ+CjWf|%eJDbCpbGNNrP11_2=kyh$r)<`CMH|dV($cS4X`6
z7@95!=VD9z<v3Kk5`Q-yDRFEk3Ds*BOI8>OZ4ivJ&D`c)hZRiRQv;I0eriunvFsqV
zZB*{&#KF=pZ)+uyX@=>$3OL6xBajXubANi)!xPNkL=BVKND_lC|H@=dSFmXXgtk3@
z9!5d?f|PvLM-qdQhYF;w)#Z@Ahu6iWd*K7&4>N<|YS%w4_D)j{JYq~y_f&*GUXq^7
z|7x<TmU0|Vot%oN>R&*^@NKcxM~V*KKLe_uhQcI+ORh|`rHze-QNw?XCfu`0w=3W4
z-M~_Ym)c~?zgTS>;Y?`}`8%8&*7xP1EYUUoILFZAw#&HJfG$->R>hCh$akW42M+nB
z`bONPzP-$eL;mS*5KOMu$^T{z>k!)vBezJ?e$c%3teq&C>bwEO+B9ML(MNmy{uF2P
zz;W*SYeay<E5Xn$QUhbeGG44$X0vV!g=U!};3BwHfcXeH#{iIs8_lJ1xE`D4fKxmw
zp|7&%bz;D~`@xqpgZ~iupE=8aSYkH%P)Sdkf6)*bht*URawYFHp@jia5w7lo4$dY`
z521@+_(#?`O@_?-jv;2Z*3EI8RBiVjeo;G!bE4_=KgE;3rk68^(f0Q!3-^zNo}wzI
z`n^1VF;zOX<r}&rPK$EdDtJ^*g0=0&_7av+oUq3B`L8Rs^4ZwA)oO&oxqlTffAE&0
zqdCZ2-q}7H+56BH?FWI)2RLaS{>=6y%<v!f26jJxNDnP$#1M5zzI?uBxAsn-v2-_!
z13Exve?MRZNeR$lNDGF+y>Ajx?$kV5vM+sTA!`7&$H?vh^V4t?rK}W>dT0e0G^d`O
zf+JZxBxGfVR()=Wsoznhj3oJ*JGEoD>=3nKWbnv!4go4_B4@QtCBtRtYV=<B_#tc{
zSix247E8VMzT_Ur>eC)h5`I5ze#%&M{W_kfQZ&)Jzw3*VkFO%~Q#Vuht$euAy&&jS
ztbmzUj=G2+Gk}2CLDF)$UEox53i7>55$07{E)Lka^!h=t(2k^)==)E3smkbu`O$r_
zQs)srp%j94IMFAEtUH_ei9JVB+K1kjciX?pIhw%VAEwiX_mW14KE}Y;38P+~C$M9l
z%7@)-Iw_xAqYPZ&yFX<_#=p9c9jWKg{dz{9pINj6W>?<VN@u{84S$FO=em8N&+lPL
zQD6LKw_p5j^?$SCz%*ep5p<YrkW3&JR(%siJW(O%<kby)Aa{1+K?IEs^tAmNnCiH@
zuqqgGPrq^xS@;iAPwyYsH~6QC8`IlDnfsCg16mLI0uZqu@yhZvrO>9uzpuK4W_9RX
zog%qE)!E0nWk6<6@rV=BSV*aNk0aa(V=`Q<uSxl&dywAoZF$DI&^M@habyN%?px}J
zWpd6P06p$`^g1Wu58p*&h4a48@!XMQDC7`xN~NNiipjx=efEa#TdAP#l5Ynkc%s%1
z0)+zU1xidEzvj|_XGLks9HAxt0BVKA)=$p?4;6Cerb+5N07O8w#ARgg*dRdvhS+S1
z=^sC4o!MdY6K5k>&Zia>u<LJqO1+Cgt)eysXO0cI0tqgh*3GFZY5h=dnT;pD%09J_
z>wQ`DiMS@{u~9P&RMw547!N@+{x8DBe?Mgp0EYCk5;rTwhL53p_d29{VJ<wAvp*k(
zeH5smT&DJvekp&B2$i;?_$`)|dYFLW8_<^C_o_x2-(^yqExFJ<sExgTV+i`^0b|Gx
zVx^ZivD$?%ffk-u&FWEgSCg^12L9kt-n!$|LpRJ1v^5QXCR96>*LTNf8TqZn$OCN<
zoLl)I5=Q4r`zvIYpv3o|xTHQ*%XtPt;;0_fU2|wA3l|F%Ko43GUfQ4flumZ$Q7W<e
zWK)!D@P|sDISiYdKW*OX)n|c8)#Vd*w(9LBkeo6hH!3mVXB9C49e#VlrMY;Ks>Eh7
z)2FW_w|SnA{a?{D4wf^hm;t#D8zBTr{Y$7ze!`d8V)?~Rk$hJm$14ArM64<ah|1`C
zL}*rP&H>?S8e_Y{^<UvU_Q44CK(_@?#()x6xUP`y6vYaKXQBfmJq~%o90m{q`Qx-@
zTLzGj<I_XgAvK{#x1@hNLKzI!_I+#(%5_GZ&2rdRVPhOOJs>Lkb49CQ(jXk39JE2q
zCLo@|iK98Ot^@>tX*P0l$pA^Yr1VwEu|^qK1K2Ip*~Kh{fhj&^Q6F<r*xak@WRmo)
zALULLKfQbcr2g8qQ9rP+iQia4RIOMuu1UUd6^VTXUXxfIIo53{MTSur%+bTVYGsrm
z5HH%x=u<aj<f4`c>uoi7#-|m`SD8^(FGgJG`>cESW3z%O74yF2KG>{Lg%stO#tA)A
zFlVb+sM`gNZJC}<kt?g#?`I%u<kMofW$z3+X@oqfQH~+LDaf9Xc3Z<h&t^3w(@NUG
zt@TUg*@wf{m^5}?YyXTcff=1RbeF|qAz5A#aNJ9g!I^i=+8q&-|7`mCrkt;?e=mTk
z>=x`cJ$Up$lJf~2D}tzlA}C$(>hQ?SEC<|+xvM-0#VhL0Zo>$za7cb(%D$6U##b$*
zn&Jks<yfTx4qm3jOgDRK^BiFW`_{8tU$cE*;gDI;>>dj3ekMBY++%*AOE6*o)iN;<
zZn`6OV|(>YiZb0C2=0&uAg+1@`{W)Ph4i3qp(n4Kr@Kb^@o+UsKZyI0K(n(ceF%oQ
zY74oWaA=P56*!0!-f!e@($M{{WAKKfy29f*%@j031ie^JPqx9-dpRI>hpcN%0qT_-
z1{j&^8oL+nSVNCEgzl`=`#(MMevEDb_YUw6hd=TI3tJZq#AE8=*>4w-8%*_)gt6S7
z;BQ~^k_E&CuGlO)fhJiv-;wU>^``qubG2j_RwL;4`iY)yqnOZKCRSH(9;c>Q@Gixt
z7T!}&0xivp9Ym=`kpq%{3c%v)616Y+bQ#3T?C2KxWP!H8A#8n)A!+&-VjS6F8jqD;
z9$clL^i0FD;i+dj@S}yswOUo_Q$|hAJ?e}9AIv!$Eff6S#Lkh~zn```I>jx4m<pwG
zb{Mr9<-gAzWXzL1wY6nz%esI~NHDo@g(z$Iv=L6z`u&H}D}C2)s_vr-Ab*|<lKf}r
z^aFat8e5&d^Zu54H6w2-{qAfeV0wdCq_Kuh12Yc4A<Qh{XulxTfv|>1hx4@XoVCJ(
zEo@7QA>f#w!`Ir{+8)}~E-XtlxXj?41l~X`o}l~-$0&>>!OsX`+&Je(84O;pAEv1l
zY~ae==HK%UwTmiCGQ;ghGufXn_RWPp`_|}j#+q$b%0_G|gYKJhbBd@*&h_lStVK|p
zMp?z>qAa0*V*HXcOwh#D?I<l*fc@WkGiPwiMUEbPK&!VCniieSrjiSIeFRc1c1}(&
zQBU>YJi5fGP_>({7-U^6y$sP8IG2MAnQ`r11Q&pNMp}}$Q)){bju>d6U>E=PTGb!~
z=^4`{9o09r+|m-%$;rx$Z)8L^Pmpo(TVqb-&qZLmzp{&6J##s2ACE3tgR_M5Z#I+n
z^zPs8`hn9ic)jeh5H7jK#1I%xjV746q!8Z=hk?0M-zGXlp*alXIH)3-Ge4%K1VVLk
zCN{EyKmnX1X2e3q=_*b;6t9oatQTYxuC6m@ay7xYuzP#JRtLBRPPkYHPAhlQ-JM*V
z8K=9!0VHOVv$;a&44`dj44<emw$g39*ZenwZQd6T_RErdDnO8pOY!8tC<hL7AM2xe
zsRpW+EZ`b2%sJuGyj@9vAZW<Wst>)fAQMYBM2i_Hj8GufLNU!#bQ6Za)yq3w)Tpdn
z5R~7`di0@IK!NzSJO+Y-8_<~{hz$my+oIe>r4TRw;wdD9F+rtEoq!7R14clpT8q0e
zQ2GI05U9%A+{Y9b)BRzD<wyv7PkjXUu)ZeR<X-%7_gs}7qQ9zlTK+07EqD!j@&5_g
z#c^+1vy|BEf=>}nl*H7S%%R^}UF!<X@!@p|v**;N&3^C*in$<x_{5BQ)vbff3%<_B
z_w>~Ll3Mo>tvI$7yE0@*qH*XbSxrbJQl-kfS~w?06al7c(Os9Bs~qGl!n${Fp4JON
zEAM30OvlKU7k}5@>iy{=OV(t?%YUi7MUX11$TNtTiX8*H4e-w4i6w^pm`e7>+g7RO
z^H{%hQ^JbADTka}u4XKesqU<g47G()Qsvo7qLzZO?e~$`PJjD4<<c40k(mDig|DB&
z?yU~jA58G4HkQe;D8q#9=h=MX!1Axq+d2eBpEPBuEz9H8Pj-mitRV$P-Sx9b@z*Hp
z%3#%Fd4+3K%osFQ1GDI2x6k>N2}YidiL*?<o>&t`qWBT#PlAm!w+}b(+OhbiBNDSp
zu4Y9KiW+N)%BY1iVXnid`XFeZe%}S}pUvx&&|Y7o3h4|hMQgd&Lc&}FeZVA=&#QYK
z$vu@F2l%0Z57ViSV8DHt!KW371l4oQ-`akZpH35Mgi`f=CGal`QhY4EA;ALb07Fgx
zwf6&WzKmJcilGHqfTbkD@nW&f<eH=Onk4c@B8?3M;;@q_@W$Mjb2DP6xvf-v&$tF}
zv)i=)*_wR=Qi&TFvvMlHIv5mOds&agMY_C>!1G2lbFa4(?g)vv*aN{{AKfq2I*Sff
znoW<B!3!TI9X|ME^PBaA-|&JqVeS(#FIgX2<(WU59J0^%iHBZcg6U>&r1wo+Mn`(+
z)%2d;f6xE^>1@phnvieSZ2XFD(zd3@CD*Y!G(=$WvIZoRdTYSFx6gRLcm^M|D>n{@
zq>?roA|%ly9b{pNQcx?i*l5dKugq(>q8%C5-0(ty8c9H0e4$>03i9B?%_Y($7@|Z@
zPx)?v>Y#GHKG3IZNcyISZ=?)f{nQV3QnM0YnSZz?>ps0)mIVT?yq6E_uPb?~m&6&E
zn$xWwTQ#_JZdxw@`eY(pDoy~=4s=<A`H#OXut$<`V^ddww-ptJNK6zRs!_+tFu=IX
zq>+L5abX@e9vS^aAAdT(ww9$NZfn{96AWcDlT1O{NByy&pO#?3<gta5oe?+D9SV6-
z77f<d=90X51C<MXMidiT8G?Pv-W`|9lw!EW6?y&L+%I;{p>()ztUF?%X9u}8yKn{Z
zh}CLhu6ZS@;P<y6JwF)i|DyBL#@pYW41%ov1e^`l;h=nHwL5FuikWcN;h!y@h2J9n
zC?*1Y_&IAmp(dVB;wZ|!=xAd@I`$tx3H3BW=RSZ}Si<Tdl=Y$&ICh)c-eJdmiTUwi
z{~y{U79**LbXtlCR&!cNPkaX1YKZKh-lA=)8=GI|Y;)}sN49G=uoSrxNbPG~&ytOX
zssJmaF08x6_IANJ{FgDW4*~tdswiM^nsOMVGc6M)tv4~bK~N)2Aot*nudI;4>yTxe
zq<g}8>+mbV+4*W0P4gk%L{0HyoVDN*8`NHisH+*N^%1)(BA-Fm2XdLyXJX!o<ZwiG
za2HiO^HBQI#U03SH0{N*M`aKB8=kb@(Gmxpqu07!Vgj(UNMF^5zpP@FlwQgh5a3;9
zX7r8r#|%(9Ye9(ZnYzWUJ$y5mRL2h)0*O=0jkqR00xT|Fruq7^=2NEqags|Op1N!0
z;kG;JyVQ%NaQL_4I~B)SNBT~+?}RI_?!2LCx{Mj)KYrxhKb{$FPtl90aE6V{^2n&6
zo{*1yNWpdo{D~wY6jdC6HV}Ay*xG{KE_>X`4-3Z4ZZ%Bqz}f|SF}|VhbE;4n_>{pw
zwDo=qqT&Yz#N({7U*jLIO=%~gNfqh86~ADO#t(I`^kei{Yd^lwkscJ;i_U^Act@~2
z(BF#gCU_Jo-Ez}%mY|n{JvK{;Hd`ZH#N{>xmB~Yb*mnjlhQUA1NH~9wSbm#b>$}Gq
z$s)=hp_U=n@y=aF{KhG`)NfZ7+wvu093C7>X#hZ~y0I$Nk%zCx-}C+(QGHg6gMToj
z%|C@j=yLJrD=wM!P<;uMzG)qJL{g{#jeQUa!;dKu?pfs1gwkka&H%|(_ld&HycK;7
z_I8MZnKv~E1cmenq$_SGo)3g+-f_7H3pZi7;%B*UeOYiptWguvEiu@5L`|SA!z>85
zp}=0k_WgF-vxg*Yegz-y{UlgpN;LA=wT@A}#yw?31dV+hb_O@C;U-v80CJyEPfm>=
zfB3&+XPOlcc)yBMCs-A?f}vk=@(Vw~1wK{^Ck7kVnRR~oRBJzE%vjC(*5mN9BycI6
zW%)e)d?YFCo0mVQ$=;Qmo6>pmn9O(6KiAgo!D1M(sX@f&QR2fKx~y^IDT{ao^{uQ%
z&#i(8<HNZcVzdW`{);}!78Uj2?oa{nHYHjE=nLZ!o#;1%p;mpx%{*>bZ$>$?VE^R>
zT*Vas>P&!;p@hacL@<@O0SxDtCD?)T4U>U)`aS6XU>)wxoyJazlc5L>jk2RSdu8>z
L*!RF%jCDfA!peuP

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v
new file mode 100644
index 0000000000000000000000000000000000000000..5b80beb47571b0c60813b6902e83a3dee8c35e66
GIT binary patch
literal 6136
zcmV<U7YFEz6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T44eK*_*Y&>y59K0RcQ|x9pu>vmz
zSw<y+D?o(ZnlH>IB8;y|Dph;qO+1WF$mfpEwJ2a~gRz9}b=h8tBi1xX?HT!^D+{fv
zp<&%qjp_D=G@#-uI<0u<5gTMl;fIN?`N-{uUje52?UwSDx6+<z=$U@4`Km~$XPGKR
zrYP&*WF!8ZqgosjhRCCcWf+mDcbCNd-6r8YwysY$Wa9#FcLMmnxVmUdQ7(Z7OFl(&
zkdg*G*VadQiq_L3?Is49x4rD3^<p>~b~u64qRN!Fb{tcUt;YozwjE8`Hu@hP(P>k>
zBDy5`!y&^C@MFODj_h8<;!epGfR#V6fL`@*Gc6lS^Z!)@U0`Fbk8o~pJIkQ#=Vj!f
zYkwXlL&6Irw}wMSGa>2~hzL}3`Ok+l_}oN#v2M<v*C2L!^+LC-(8`$}utyO!vhA|i
zdZR-lAm~O|R!tbv4DH%f8C2vo_mCBPP|NIu0y)l8(bcR$(e{ow4~LIbI%6#nL7IZN
z(s|PsyZs^^un3Prw1HrwG`bG}j~oz_nY(uF&|5=<{0}Cm8(r-#JeOTcHwn0t3#KJF
zIax~$zq&;nk;(0K%g2R|7OCU87)!lkU8>DEDKd=xT61mcGyJEha=NI6_xDY;zz=kI
zW$4Wi9;I%WLMx43CE3Qo-)<7spDckSe?zX~pmB{2C+IfXtex`j=p+4LCCF@)3c)Wc
zs`6`Q_Sxlq@@WQK)m{$?+i|tJ-|hk~>36!Z*V34MBV)EJ-yLk#Zx-Gn-iTWs>2FSg
z?Lcx^;SpzTG|>=6WNA8B7G7Q9iP0UIU4^E${m|t$HrxF|r?9%f5vY_$0=Yaid5(re
z^|54{KQoo_!s?^_fpBY&nc_C!$V#1Dd`c<;4*7&}O5Au_5a@U7o*Io*jmU<0K4A0K
zM?$WCWpGjkHCU&EQVwB9+^bpWR{_qigTHxT!C1GXNurIWk^|Z(80?)?t=pY_yzXhq
z(kIN4m*GWtaOUvj;VL$h4>bQ0dOjd2%m^a2;>SlD$>OxqKY0v2n!3rcB{N-qF80oZ
zfet}oDJfrSLiC71=GC?(aC=>0YkAHFPHwJ-_oG*3J&|?fHf9f9HsGJ7Ij;mg>+;lC
zWlG;WcDmFyV7m`dCh*HB^Jh5QZG+~MiX<m4Cr$02J?q6DmuxB$*gfs-C>VwbsXCZr
zDSUN~{D6(^d-nWD=+gP@!|{rS4pu*zEWsvA=5;%PL%udmg9hz>`l;KMiKH@Of;uug
z`7flh9Mo-A%_KJKqRaM#Q(UVr<mY8cMeW4h2g!3D-jhCHA-O<($cK$2X6k6^t+Q~d
zX5qp~FpMoav;sqF19B_;^c<3NE?G)cr<fMJoNG#EX=~%~=bvs)rTL2~hvrH4O`6GI
zLN{mPwEF$r*!r6v&wnBDxmGYxe>Qkim??9t*s$&`);O8=r4?Z0jZb-4D3nlg1TVss
zhNuprJhtT9uyIzngH8wkodVsZ3^I=W94G?*{mrZxmB4l{a5L<EGYa=T?=60x_Hpzp
z;fRNfo?xS921S!b3Z^L_$CD!aC)Yok_t5cws+~O6QD$Xd%$|NR4xSL5%d2ou5S*Ho
z%N9IK9_fopS$X6x57~+$#yIoI_ADue^?ptQFbY*TC;4F9A37agnJdkggP|aQ$yYfV
zSN=;l#WEsm!q~pmN>3#togExvc)BMvDD;XiXh`0!L-mn3$!bMBkM#u?lHBBIkAgtd
z1{JUL`49Sq#=6t*dwUH^tTBUUA~j_Epi%>}0wO4COy0^aCeXJeIZTxua@WbYMwl~^
z;-HFrJmOM?=lm`j{QfB`jswKW@b+|--@A+n*N+I9hdEamQOij2x@$)Q_)l&|`@A(^
zAMo<A{qs6U*?tn!f=r`tDjfEFZuuj-nyzBu*&v}k7#moS%MQo6tjTsTppzg72PHDz
ziW>Y2PHrR>8{BVY(<Kj?TSOOBo~LpmmdsRWNe{{ZczisFj$N55E)4t7jnac`n}f}I
zCaEzSJc7Y!uM*Gg-nJ#D3SZ+{N90;ekc(j!ii{zm8Fa<0-J*&qrX(GoFiNfnqM@n_
z@F*poKd4$l<h&v>iRNw(HQae(AP3@S$ChH?03~(w6tm#>{{1P<Mt7b*s2wB=xzv1^
z{vFFWfFnenN3x0Uew?u+kF|a*N=x3mIhMub5T~!RsIEn3P)3M@*n3?^0o(3Y?E8*l
z!COM3HYhWd;T?jjQ?$83Gt+5h(Dn-^kM9h?`o+nMj{q_>6ntCb%sJWiJn|8;4<_o%
zI1&50HP3FX==KZu3q}rQh+}GC_3#1@x^1Uf5RUBv8z;Q3NpA=M8bB~eLnFxpB_ReQ
zqZ4ZE4+Lhew}s>hrSwAYrw9oJjuvHCo`<y;BG_~4U|4ABwpL<=0gG6eW^Jh6*&TmD
zJ(gF`ypD*u0qCYC$UEaBwNB!|73X?zcZ0MwOI`O3$s?ZA=6<EO`!Fi`sZ~u5JUrE0
za*>RDa3S{l@rTM~l#2+~9iKc*HszX2uX^`7%;3}0ZzZ~@md#Zjesvuk3u_j8n;y+2
zyqrErRClPIf~v3l+F7+m7@@_M@?Ep@#CHF69{Tr~7k-g?U;SM$YQ_v8t@_q|brpRZ
z2Tw09AjJ3hkO*rvE5$OV!L|h~AioK56D?dFize`gq6Vjik`vSeW19JvJBX+(<jCJ8
zbQ@&V{^#86iyUq{$)2a09)jUih`vu>aME0cEo_$@B|m0bgy|)&#}HSeOQOV-)Yj%b
z$@oMILX`9+Z9=q=+swx^l^vp(9V<U5NN)RoC~cLI72Hx}xSYbcf~w^fPo9hbiUW>c
z8$n5iJj}4U?Q&Fa#*uolr9O7WdJ$zk%J9XoZ4~ikos(+ds15Tlc35?a8Gdaq;KNQf
zg==@_&MG5rtY3VH0dOB}n8J|@ktEult({Z$o=>uw6UlXnK4^RVSie7rEV8Ou9{nGu
zB+QBG?w;unxc{D9ply)lE{4_yUQUU>xdy%|>NDYOS;BzP2EPT~?=-78ZTk&ZPyuaH
zAz)p6v>!|AG>K>cqDX;ZLHP)quVRecrrwK5jo*n&uSYYlRoZPRFKVDsu#f+0)%cF1
z=^Hqb{dWPH$3h21AM-q#FAwjnLrm<`k4%*!g~q~PmKFimENk%552jnr;NCmAXGHr=
z8QJ=`tj+nK%qquJ*Fx=-wL`Bqk1q3@3ahYf8Rm_8wWdlJi^HgiiPDW50~V{P1DRE%
zAlzW9xt+*pK-O6Zw#*tf?7>-!2xc}E>OT=o=!tkwVSO-PuuoyGb$_-6wzxMY(0IN`
zbBuO{ZD93JsX2BR1d{*$G!6F?&A4=qi=5HhYS)7VurWe+;rnsxu!l89irQWF`h5_x
z$p~Yn2{9ZE+|#wa{VRam_>cRicPrRX{Gx@GMrTuMPCV0uWb<vXw;LNP9#P^FO7_Wz
zLJtq3^<f)K;THLAgEhlVGlUO4&ib}pb~GFQ1(LHQmVPAJ*Uqb&rboV6*5nJwYGP_P
zHmx*W^#kv<1TTIMt5_n9`D%`J>k6-8+co@aGe=e%c@?~@J%i&-uAID?6pqbU51r+g
z#w3Cum`fOP@i*kJjmQB>9BG%2*)G^i?D5e2b1kJY9TdQxJpshUArOTYf!R+Cm+^mu
zZkq&ccXg}e6yKVX0})R8DM~WvDCaTqUoNE%*|4_z%|S)0EC-W;heW&e7u~jyJ`vrd
z7?P?1)pu5kqxCdSi}&KBdiljM?h$P>`_cc#|2qhPLlq0i|JkfwY&d3T7)Y)Tf8cI<
zLidZ9W>YQmBaZ^j)V{}HKK1?vm~-PwPo}sqt2cZXX%G!1P`jt+%GZu}N_a(7=Jny_
z{%9yC-n$FN<;#<Y)~<gCs8DwDVZj>58xDCZ2(sP&C?Ye!L15(*CWf&nGtl=@(R<YX
zCmCA&Rv$OXF4(O5tJ?6gtK`Xg7n`(MRt9$kX2S9lxK`o`TelN_ojfn}6BY`TGn|pa
zXaWFQ7@FBBIc85N;=dK=)G3_4nVFfz8O*5H42w;RB!DC>5MQu==GPWs31+yfulHOA
zz&SfL_jxW~F)D7+fxj|1O(DuExBa&Qgh}Eu-$Z;cTRJhQ2`$Vz%Va&h^$0>I0{eOW
zZD~2xdXLvc+X>u{!Z4C!`>bg1bU@yE^U+wyFpy*WhxpLKKS5&TBKB=O!;^ra4#GEe
zJ&GRMnZqB&@<6Nyat~aY(gD~OgMi8H_bS@DniHE$RaeH3D^uUF6GhDPmJN;|EzuIF
zQInB5m<i<xdX(Wb*D>yqNJTwSFpIW*o9^XlbH8WNhPpSuoueM!*#m;=;4$<={8@xO
z8_0J(dt<`z43_=5?}l_&f(QPR6@6aU<`;mA_mk^V7~Hs8uN$Bb@%(s`k{hWBl0@he
z7V9##^JP|mx@|&0q1vjXgd2$@vr(V>F*SHZE2RU{b#V))k6BPDeuX%J7C<9Ke^L`=
zE(@d(Epr-+nCQ}wE<ZdU)J3?SdVuDK<RQKSsL`LKCk|Z@M^ho1YUTFDwJYh_bC&;P
zfE5=lhWO4+{R^;9dlp#lj@Oy9b8%NN-R58eInY&U^~O3KP`ZYGz=OTtYs_l#4QQd4
z;YZ%vwI((y7fQr1Kh%CAO~TwepOpzcblsCS%I<&?D>nf-6ze?<;vFbwfmG^p|N6c}
zK*6AC6Fvz@U~syJ12SjXz`>=a0ij(DSN-jN4q|?V`&9pV&}2ENWzp#bWxJ#*an4Ye
z=CO<K0z50%LBP6}fj{%mS+3XtVM@YyiAq!-o(kE!oonhh%>+M>I4x|~p4*P@7@S`n
z!ZV5K%AkubYI^G%g}qR>e*_8e-I^-w7(D9`ibk|fIFNu3cEdUT?Lz3uC{8KYY#cAs
zZS<hy7=f-sr!!-?ysuh0YX~pCoQNy3Ztgkypu3v!OfYxURW$-=Ng*4>BCj5Lb?@ll
z!2s~!@0k&hG?g@z0OY4a-~Z|-$*WlP)iLA9a2~#{A`b{jLvP=_LLZTsdS#%k#T!H}
z#4488C<C`lV-*mRzjkn1`z@yq5JV*T`^}%%%ME;!tF!3k_d8Sn1U7+r4!1iKOLq=J
zq96Pm@YB{~vuq5!gwyi{VFmVGo6L`LUq{rE$XIx?(vYgt%@`t{iVt+p>^;co&HON;
z%70)qtYpUxzR`7r7pOUa-&=U3E3lq&c#wj>j#CMFICQ5Ap~jU(QFNsBd3jt}$5Mtu
z*Jng3w96gK+9fp*YS)YSp)vU*t5&yC)5V6D{R8aH_L1`K+_jB!!|6XtJou(jtn{I3
zU4vxDmWP)-EV>7o_OdCoYzS2;9F1yAmn~%SOaTB@$|PmYY2}+*v<KcTy*o+d@0mH$
zzILq#9Zr`omLy$ew&DlYs|0z|)4S#?A|Ofx5tw78Vc!{y)+n?G4r9EzPcMXe<LC_q
zXh8iTAS*m}hg6K;$B9Fri?P`~bv`ngofz|f9@d2qlCrpZ_JGv`0sbQJ3wiZ7A!ZP#
z%<ruGvG%#Tmu9xv>ceNTM!Enz1W#_od$WRqfL;fW+YjZ~yck6(fqR>5{q>wtZ#5(2
z8WXT?*=oGBh7mc^X`(j7mtGLyNYYfjQT3MjdQ7G>8a)CiR`0r&-@3v)`2uiYG6Tx5
zn3sp`DqK355phR7vz&kIgG(ovp=8KCl2h7GK&Y)2FAU{k1W}e><C4~R%D4G$578~}
zxkR(+|C$)FoVhM-w+bEB!M_VvsHC>enzuvM?GZBxe(+h4OCMZa6yd$)Pvpqv+nSsz
zL^35ZNav|`VB3!06%XGOS!?Q-lRL4%+U)NU(XhfsurhMH3<Jbt-AHdyUentq4*N>r
zyU}yDOhMR>qlz_zeY7_!RPh~^Ref-uYed1H64uN|Y#;^E(qAh3x#3wdv^*PY6><9;
zX&67485sR%z9St8@9*;09uJYCKbS%Tfj-7mHsk%L*K3ro8cAQ%*pH;JC0)15$cN~z
zorYPk_gL|jT|sR*ozoQ~E*Z)=2UkVDT)>Z)Dmbhcv?0*XRVjupVTsf$YlYGE7l2Zf
zQ?#DnNPMPXi_Dg}3Kl2rLq==Q#q^j}sx#^*a&$PtIyBdyR4_a`%3`lui;s%<kszpT
zDj@@y2F*$8wY_P+mt(-2NJKw`f=@%!2=Hfgkl%8%`jAqNBYJ9(xS(c#Fp^WdaJrOU
zdT#Ze<7#h5lK}_2`u_fq+{1tA-H{=nBExSDZ&3`vh^Wkz8X88M3^B48HBzQc_`(%L
z?;#LPSg1~Aey=@>k_7yojUcR(o%}|R#lrr2k(A;&=361M<S`LzTBK4rV5GNj*CLXh
z4zw{4YWHG?25ESO2??f3)m(-BGADcV^K@z<sQDENjSor!YI@D-JWQR|{`Gzd-zhrW
z>wx`_xxa!xpt-AaEcvgDy6?=#jMtgZKNKA+AydoYh4hgs#Mvp#p#@Z1Bd)o^mO||v
z`6BzeF;yhhOvt1dH%f}%p(=Q8W1l~*d2sPCJbwp6W83gff}UB@6Z(&RTQEXM*W_pg
K_9@w4ASg%2E7!^Z

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..029948d6775129bf0d3bd814653b978d285651f0
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2Cx4|338UjqPzI2H#jQ^)B!+!c&zVh`xYs
z@VWhH-`t#KZy~6XDQ~@RrWL?h+boHx0<RQ<ei)pr-L+w~*kD>BtXhPqI9+w&-=pZc
znO;T)g_TGhPE=~yT9ft?_pxsv9zu+Fj}aqIh?9vk?IF%H9-$3yt^|w&Ygnt;9WVF2
z9FDKV*m20CHu!1SfQ~our@W~M5CdvdL8~p8wfE!-5_ttL)Rd3p=~q6H7ErzR-)W$C
zmvpZp=I$_z^P6`38|biCU@^jrVHWaM7*BauxObuh^O5S&gx=-m^VX|q$gZ(AZe5?d
zZ2~cSB)w}tG^ARBwN>*o7vIZYfKizk&=fmJyE?4_3etvj)$}_4_nfQT;wa5|^)+pb
zlG74EB&3XfOLJ8(k!wP}8oqcq;}Mci_5#XOPXU45d(FO}-N~3Ma>YB8hA5l!_G;Dw
SP006n;J=J*(-rsq(a;<f_M@=?

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v
new file mode 100644
index 0000000000000000000000000000000000000000..00a7aed10099a311b6f8c5b7973da51a75057517
GIT binary patch
literal 6672
zcmV+r8t>(c6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T5oeI{r#O?3s>D1HV*A*@|Zs;WuP
zXX#j6O%M<NMheOjcy`?{pX|1Msec#k2uS1g7)xBNOl!p4oW!>tErsFQkq>mb9RWmX
zu`Z4go_JL)Ze^LL^J!E3>S7FAL&Y13nq|iH0Sv15=cFI_G1P3M^*aU|5xCUEQL{y9
zH<*j0Lxx&3xu1^o-ogozP48x(e;?P?;KExR?Ndzpq_EgGH3rLyw^>>?WUwv=P!)7;
z+Wy0A=!Y@_EviXw1k%MeY3$-tjaKT?#b6p21n%d)S~l9n8((gXWJdC2TEV@!EkC8a
z0=?AF1;5L;OOD`;Dc~f?PD1Pj|EOw&d(pK0>3I-KZjykHA?On<w}N~!yOAVDR;RHe
z&tk^CeI75475?Jf7iJ)P7k!#qavJW|$)d5>rmV#jcU>zfS0jEaO;b@gi<8ec`T^)_
z{HzOtc7B2#Edbm2wvq~s2a7}aX>~Vf6fh`U+>^noZE-f0qs|(bCG)dz1l)ss1WGGi
zOVLDJH0&Jlf4|bs-VPd@iQ7$OFKi(=2`NWCO-n6Xhb*3i^#?;A_3L}n+iFxVKXK@W
zeQMdmvk-G7E7aBnrm@&FM_RkFsPeGJ$RE7N{0Iv5vrk55QzM0yWxa%89-Z!q-bcd~
zhGyLqQfS(B0B%w3dvebO?hNlE(Hx5$cU^cidTut)jOlfTo+u;^HsZ~L716ur0|hZO
zcu`(r^|gaUz$F(4nS-WkAHxyU0X=h9F0)o@27<$r$V@zIY2&RgMr7LcFk{`wQC<Iz
zdJv<=2DAH&wj@`pYYZn2oW~x;CrNs-o}pWj?{evp{@RzURncRyu~+HRKngQ+Wk5~~
z2#t7P2Ivrz8^qKZb(ek_y{dfi52e9CQ`cG^OQx3+`K`Yw(dN~rTU5=e0U3=sM~xxY
ziN7Q_WTt)2J8xwKK*hHosqv89Vv{waW3|G)8~Ixup@cv?iCX17!yWM~2Lsjvyk&5Y
z%b%XGCs*ksJp22k5)rBlzQ?U&KT6Q^UcCF7Q{_SSOs}0;8FLVTG`C&sfE#&vlJ4HY
zSnL&vGo!j-onAU0@#Dw>F{<tMd9K*{5*yL?C06<VDgt6e;W{_LGX<)v5phH(t4N-w
zeeT0Pyx4z(oh4T?6T01#U6)HG9bMkL_y|0XINkMFd(IPQpr&WT2>71IBeq)U#9?yb
zeki#Okd#ctg*~FQ+iH&WF_EzXY>jw=Is?_45nGmx-YzDriEw!uKO$%;hmM*^yC>w&
zo}|#m$yP6NnBY8|<<kn7GPwVmRnpGu4E~6H{<?>wbUr$SDLUoSl`kfBHn(uLeVdvB
zMXr>BAuq;T0C8~>*v$eVw%dg$J!AIX9bc-bhwRq@Df=_6vGx<|>95A{$f4yT!^a&S
zoMnl4Ch8GN+|AE;#zGGPr}#7QXAND-lE*v^=8s|6qEN_?%H;V<gvPfW@;;fr5vIhG
zZS4x9r&+F`F@2+8XN0tMOJ+8!8E(G_2*2snj+C80rjuy}tiW8&BtvNoCn(Rk?0j~0
zP%um4JN3HO-&B%FWh33aokbo>t{XZu9;%sxrHHX@*W(cuQQei3p@38D@`xQ%e%Z;P
z&YzusLHNYqwScHwAhi|5c=unaIAe1D5$>kH=%uG5>7he!gtd*rYto}g7s@_^zsJR1
z$7f@H(b7X+er-fK*n8IOBH+{_Z%m9k9k?BJEtrA)ShbOGoVP5T$y;<ILG{Q&i0g*)
zks&qzooCCJ+AdyXHy=y6mbwB0S;r%vVH@5fs2(aUdIsr+>2PS&%>*5lSmft4Dbnnl
zGi~Z{y^WLrT{x<-@#Do8;kPCwr=2rE?*p!<u-2fovl_E;IpWxa!=TV~R3oohbCREk
zvW<VHjt}GUd!P(RbH`G!$YyAb9VkQ*FdBk}Shi|VCGRmo-~>ZMaRA;}Kxmh352#31
z<Xzk%D)25}wp<<mklQstdCj7O=+BM%8~c3bAb&7EvjVqLLTr5GD>k;4jgO+S+CBaw
zgIl`(^i9_PjtOzEElHcTz2K%|M(^ARYIswSJxP+aYL%-(J}+yy4+X_`m2KWd;m|3&
zT}11wGw?K9pyQHfA!2@m!#jR)hbNI4ALusX@lhMpO{=h%<Mtyz3OLNvHE0Medh0@z
zs7k6#I5s&OMyX!FuTRRcC`__e-gq1;{IU}o1|4Vlb60@{4(hdr_e^*<%I0@xG_xF&
z;O0)UBWWJ<o|#9z5`zZ3ZFr%;jJr|pk2^FUd0Ob801!6a$mk=+!rb(^N4nXJSHsm3
zB$3(h@`|{cUANJv<`ZCk)UaU4wZU|7&qupF>iUhxE8^@$Sd~^>kI*D=-24K)lFw@-
zQu0W+%XS+5urCmp?S=4_lpKBNsXX{E3*MdPvBd;BDgG-UyFS~O08zT~=#-jHirp*x
z+hVo*cLlCF&_uZ6ye77W>FPwFsc&e0(|NCZ2UPIr!$t3IMTc1jvFDQlki{7Sj<~00
zBb+eeRguZJ2IBT?ic$!uM(Bx`EgeI7rLlLj76eDtWPHG1`F_IKzi44v%Vqfzoo?~u
z&u!h+{fql$z=`3oHj?m#)MV>cg$&ivGR5PztHhS_f5ddwv%U?ApojhuIn)s$fSp73
zpM@>B#3!%}IWbUY&qaLf0-e{!*TFPSIAe@-kNN{&PinuT^C@cG{M5uSaI!wuHaWlE
zvkE1S7=N@V1dmCt<u*V)-1$MV?jx94w;(OpHRfDXO{z|QhS`QDB_ukw2*G{OQ^s`&
z26x6`=CuHTa4GseJCY!h44R;iumuRUS=Z6Ms-D6zs5-AR6k2-r4vYDC5qL^7YZoVb
zqo)OBh5q8#v@Mb?bAx=H+4C&3x5uTUy>hka?8xR9;*5rmBj6@)aA#wH_lwFb5Q<i!
z{3T&b@_Q~GC^d{|L|5A!dkG%5odvyPN_|HP!bnNi9A|3V5d7g#iu!R8X>Lo4ZS@7h
z@xL@}>6=q>kX&sV9P@o`;d4Ot5EQ*DYRz&5IGu5&Wvjs><jC4>3XDMx<s7B^peHba
ze9UoV=&9fiAM#k3herj<aQPyyP;d5ydo+?a$<6(g)2X0k@<BHydY3>q4e0by;y^6l
z7JRm`(^d3h48vjxFc$W{^tm?r*vrXuVwNv(B%G@{f;sb%+%6K1a0MlJ9Rv>t>|(@F
z&cO~BzKeA?+h9<YvJ`Wa`AipJMe0zX(BBT@i4j2UlgTW0T<{iB9ZLwx$Wd1$?6c;-
zg7(KDVxh#&ry}yObD`7s^0Jc8HQ>e_W=7tZzBu$=7sxaL=uQM?=L;l?mW<re{NgiD
z#dsA!xji<f&Rk2O1Se_N+e`g@ujx9N$d4f*c3hECf=7@v3y=%y8CKdd4kTVFJcxjn
zudB!VBN}A%WFASfuih_l<9_EgvO?L<KPuCPq5i)!WzQ$|-b8!(Pjb~;%M4l*pJa)N
zJp{aWOtryTqPq`~m2R7qzU6`mvg;vgEG4d_8yABm1;J$Tg&8*%oiFKq`)66zMNoa1
zRvTmbb{)En0X?zpvxR&;#Xaigo^oY+;G8QAE>kq~Ar1RGoEyT9>T|Tb*l>zAE6SJ%
zW7aX?`jadysi%4O(7rsYv4FT&C4v{QDvX-w7HhL;h$iUwO#u<&b<UBkb%`MCj~$WZ
zTN`Uii$qg-&#SH~c<F50^+8?bi|kkHt~2dNjK9W7fY^7xp(w?DhU)eLNhrHc28UX_
z?<HE6x*9KgL~iX=6lqAhKfS4~7hH8#Z4#XylN(0n@>Pvg8)xH@-V^?NfOE{N{b+=;
zR5$=I`FxsEYBD4*9J{4-fDk8^K57a#|9#Fk&5@U()jC=qf-ZI!dm|(re63w4$|-E1
zFHYM6oA}g$QVl*sS;*YS!P@7`8*8+w^p&>%RIEiDN(U_em7sFfi0dB+45o?2kS@KD
zG0`@ZZyFC`mT9<Eahlo&8p_FPOR)W(v&ajc-0x|;GOM}QuA8~zz9f!iyg^jSM`ZTC
zPR0E-mt~NR1*s9q#8A~^VYzal|FfOUwhJwfVwGX{SVUN2q8&~_Pc_sAom2J5gTC=@
zTmPuo-{kR>bacQpdjd`{zEo25)FL^aA;q8WbbUPbs`S2Oc(8EyHSZ99^BwtoC!XJ^
zJR2y8$nsvCb8GScgQy}$w;7MzCUsefbtXtVXqv@^dpPerqj<!gF(;}s)RS-ZpMPNW
zoBfhOoO)(6MJJfp1D39jlSl24@QwUTop#l&St6OLZe9aKuOUmI52(vHFc#RKTL3$Y
zTo%cVa@kUN6Q2GW;&RG&#>G_eb)oTE-1J@1qVB6AS#MJIe4~T+Kt)<ft|&QL`FAW{
z`{UuG{{#vUkKM&c%g7@G5GpEhtZ3C$fOjA4YO62|UVJU0wi2@ZRJB#A^V~V)N21^Q
z&pmPCekPHi&J?Pm!xfM`Qefls;Bkcc+x>{)*K1ylzEWRP2;UvoQIUmzhn*To{Tp{!
zwah(wph`_jGNnbedn0To8SGlcSWh;`z0gEJVS47w&tWTRzR&IgNp(n6Z{ygvrS34j
zp}xwv__mA@CST3T(yWw%XWN1v!G@whd@qf24oeVvEi5=1PWGf?o(+^pSvMl$0eie3
z#|sBu{IU5CVc!#9LBrnnlEI(SR-;`(om3RdxQp@N$G~S9_q2V}uP3lAw0&F^cK5C?
z>1sZmzBAGtQFCo-?`eg9&WK%0Fw&-J-FQf&&I}SG=*mn+2$V21<T7=W^JFfiP>z-H
zx^oYcRHepr-?bZF1Dg+n>%fqv*YcM#DfECSn9A>G*|A+00<FIf-qVJKgZ{TbP)aLU
zdHIQi<87eDXzNxT3p?Km8b*z?75cQ&pA@mkf~Tq^Z%xPB;^z4J@Yg4!K|y=G%eL}K
zq^+Aym#VlOm|rvN4MfL{X^Gpic4nbOc(ZsUM8pC)<a3p&0E6X|`*fz<2c04zb@MYV
zT037K$Y_1TtNCS8uCl9*__shWIbWfD>sU(<kOa(m6mmOecd~N-V_1;-JyNX(GB98m
zj$i9rEr`2-4(zhnNp?2~D;a*LG=f$PM7n%(#Y<SjkOHJTv1Cq+vGDBo<3o|$x=`(x
zhP3KbhHrw+QZ9=rPc(Z+b2&j9GsN&awROAd87Dwy)`hr+B4RC^;>mBG0D}qY%u>iB
zjEjj#dkZ9VJ2$9JM2h~TRu}wf1)3afic<46=e#W#wR5`^Ulrazp8xV$*(ucfO7b|?
znVwUlSW&Y|fWWF0O#e}0RFDojqa#%Q$r0erxsS4Mqc7`zx-W{-6ubvM1)8xeMpDil
zdNaWrsdkDmmM?*ee&}%Vi{RLT?p_giiZY`YdWCiscoP%Zjgxo_#Q4rpyF8GT6#tg-
zT8$1B#Xj+I(5iKB7p_(yHj3=^fJmz8)+B@qEr5VMn%ADMub&u+e*OsBbvpTd5-^b|
zgM@!o8J?`pO2NgrD4s+fF}+BFIA)%Ogz9nR>Xar{#;JAWp!2cwmZj3&BwZDTHs2Hd
zwdlISWre0}Vd~w03_7a+iKfZU+1xl?v<8K8hn@Blt?CuuXD4jG#_SZ@_CfM6VvW8Q
zd~EIpi`KJu@lT=(T+~){e0p({(8ILM{f~0YzZHGfIyUj2&MX73zbG%-P+SadHc1v2
zn@nJyJ~uC7sOqO+CRJxBX#qdvyi&}JNJY-ax$OZN>8tTr4NP90_o>S;lWvb~0;ZC)
zU17bP_;wt<zF&W3$}wCw6DytUxk}9S!2%+UOuU##Icn6j=CeRUs&`(`6*y;E>6W-;
zym|I46D}pPmp*e7U{Q!t@reAxUt+uG$mW#T%*CNJ+0G+M17i>Mm%hA?%Ju=QB==kX
zJ$o(u2)r2D56l6Tb%ux4TN4`~>#St}8SFJpq-eP`4uy{27ALeN0aJ$O;VzR|2hgfP
z#iSt=rdTB`MQ>aVO$Yu<?>e!dH$Ee}5`BxW6|kEs3)N$TRtHvyVLc*RP&$3sI(%gi
zEl#h3SXN55D}$C^W$1ZZ$wQGwpKOiwLR}>}T_1*CfZ$&;h+}9xyW<T5NnKY;k35<H
zr_bffj6*;Qd!y_c&Hl{Jk9>=;dTN-%6pqmEuxCGN{C9XgEAI!>r@(ylhjrR>Gy|}$
zx%U(PVu*i1jg;@BKwOt0-6B||TF}IS7ah488}#);$GkTztPjhH;hNQO!m3?pFAp>l
z0Xn$N!JZ@NTI_IC1lD(U>t&e)+9VC4VW{@aVTIRmsr(AuWgI@Pw<nph?37Hm#m}5H
z-W{||^+mNpV1i<oOqmX!1Fsr9iApk?^Ts0vi3RMwIsv}y^AsV6c*T6HiMyrXz6$f7
zULr-`v7=5XK{7@LY-(<}QQgh6`T<P-QS~s#x<2yQoQV+xh-fR%C+>3$adH2>D;e)?
zgOCG^NOt@{H?kAbn~NmcLBoe*OG11z!XpfuJn+imVK~ScFh{;ef~BiS%NU4S=4rcT
zVhk`iTHx%IR_-$v$NFj8Hc74l4~g(K-9Z`FMQSm}H<gS>%ycG1g_!lB7l5G(5bXVq
zH!+lV>I)JrDuy)P+|gTSu<T<1`H{b8d7Q;ZQoH$g(dJ9-(p%z-|9fv!UwYzjJ2&i^
z@uJjWE;H#fq@)5Y$%YwTFJ~;TeE5-`r6e8WOM$9CqKqSJ?AJ3Ap#;w)u0H`Lb%ntZ
zgX#Ny&HLbz=)wkdrFo~77*7|6L;#>spBN`B)`X@vq9#o`mI`rk(Xx3ecO6?iEC(B4
zUuK*cWEq=<^ZTGtkRf)BURBV+65sY!{Q(gAiw^6nrZ#`da_<BO*%6LA%bbPMepk(i
zU5m?QM#yf(QKrVaO`1@-lm7!patQ9Ry6zO9l5IT@|Gz#!;Nyno*m)`2YTQ{4W<z9S
z`T4BG7iPRpraSaYCZ}t#wx2>grLUHq(ru`JJKo`6bj=kaW~(~heQVlsOgwSVKVCJj
zYL@AwmvTT2zqa0;R$ygRU`88ZgSJSaQy}fgE01pVP@dr!Qa<R5jO<9N#N*OhSSO{A
z)jqt;pY3D?e!oOg6NXAiofw=qRq$4oeXaCJw3AbH6nIvKkDaW|$aYnv?xeg+Z%&sw
zt8KQarwZ2AS2fM=jC~=Z6)1`d#b+}xlBJ^3&w3`<h0SbNo61b<nSlwMCur1IKOBXf
zjwn6UV{kBrM*)_<>q*}tYmbw34^l3jznql~HO^dV9&2@U^G$xf$fzdGY&~K?I3(;}
akmK}HL%u>Lw16LD_>~}LVhe;xb(W3KB>Eo!

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..2e25f1f4e88dfb0fdd3d773cb0e6d63dcb0876d5
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2Cw@jxml}+;U}*?x5KkM1T)uUK^Z$a0)tq
zpb`a~8|GF`Y0zzQX}SfPu3*U0>Ws9%f)HPl*~bs2Fgb`3^@3UsfUc-kjIDV4xE*nF
zgU2@*<-ESf0wja%Ha=#bzx(T1c-D-Kg;kY{n?44r*?nfDN1oz%XcTb~#j>#dCJYbj
zapxW)%Q$CskLo#|8rI1gcU-u<TF9aqbjV6(uN(=sgZ1iYqy+pqEPb!UKq&-9oQ;%d
zJ=dB7D^+zS*3Eb#Cfg1T=~*=3^2}vjl!ajjSH|?WJofpeLU#i(Mu@zKd*mm!GCxDR
z!7OAPM;Y$$n}#RfLe*ufQSMm30HN%i%Kj8)yyJBOghQ>Oj&$TocuY#K@mlCP1Ym2&
zX_|kFt%{`fNNK!i<MEZbaAb<%0yK8PtCk+*B=*YcSl*+so3Zgd+`pD`yjReW`Qj~X
StVg0a6P>lOS~o^O1!~^BQlG{E

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v
new file mode 100644
index 0000000000000000000000000000000000000000..c59dd86531eead4cdd6b383d3de5888662033e31
GIT binary patch
literal 5216
zcmV-m6rbyh6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T3D>NsFDRHN2VgKNTxE2wSCM8ag*
zkV*{TFOG8Xd}SUAY}Q;5F|aJ?<$&jf4>GXxAU)f%Xg3N;O^=x}5wrQGZ}!;{Iaetd
z9AB~_4UYp%LI2_IkVjiL>MWQkoapJIS!hgQ$!q+fcv3hs!5T`gY3I?^_|Mz?71Aki
zs970rEC3nTfByxtRI&UbiJ_sK;^=zO&orL5_m<ow$n)V-P|sk5DVvV^;K;LVB4KBv
zAgnQ(gS7LAlqIl=c#VT(;B+-qr#Dkrtwq@(Obr-Ad<v*aQ?j0tX_1&2{5nw#p`gpE
zV=7PzWv~j+t1B)Dm%mZfBmojZ$hXv}Pk3yXtUYP`)UfERU|5GhMvl6pNuL9`uI1{u
zsF!VaL+0u7XWZ~ECb0E8bo-BRb<!Z=<V1;s<)0V{K%QzL+sWd%d_1Q2z1_PGWJAVE
zgIoeIE9QjrosMC`_`*7v)YHP5<u;&id~K?KEp^jFv($W8KPmgpCMG<sKHNrmP6sg@
zL(>HY(@$Yx26YMHP-1Ui>PjTwm})P$E^6rtZyY78f!4GvhK;@PaUgM0zh+L~i+P%^
zJ+ugtbHP<^-RaWz0Im{-#n@u*x!uws3EpR>S)XlA0N@3a9p#zyEDsXQ$A38_gy6-s
ze>x;fi+ro)s)%SWw216ceDalYGO_s)&uTVE)_1#RHx`w0_E%xcf<%ww5Goxky~zi<
z14*EwW}C->|B1~CT2t+uVKyH<^3QRBK7}JBKOns~+1FE5#FJ;-D7h(T-&y|?YCd1%
zzubOWO{*@hXv|{GX7%VtAsS?;c8>>e4k!Y%LFgOqtMA%ID$-==G85#G|G-yvS+zAZ
zY#%jbhfpezKYHVVY62+Up#o4ft_hH3awy({iWUO$;&k>um)P0;Ycts!6?vk8T!EgL
zFy=eo<XIVVnf=#Qf_>94j;W&(Z@j?s)>N`<-HD0F?+mme&`wOt7xx-xXGg_6NHn}w
z37tO|ql;3-720_(j_M@d*;wS>+vp%`%6YkF6}~Fy(&Y8i7Z{5SXM8O{NTZOM6z371
zD6c#&ld^?{WyTQ84obwe0<o|HZSVJlly;6T1h&@BJ{6lv-Qt+Il}fYKr=-iX@~BB^
zN;5<`F{$s`o+SbQ<lPZHs<_sJ&@nT*y#MzkwUA6pN<3R)duLQbI;K^);tcX^&xu;M
zI<^(uM1k-xcJdXNTT?T+IEVisU;nnAWBB=%rc#ya%ONz-IXm$Y%9@utb6KPKwh%G$
z&&G)_Fg2(}VC6J@16QI9RB4{9?2<^8!N&cix(Rj3Xc_qM)Xp||k-9cSyZ5i`#G-1l
zNi%hW{jeA{qvkINcDfd<e7@;M?PoIJVY8vL{l%r_31S+rxiV0oY&*AFKHU#I?E6fZ
z2>ybm@+h}Cd(@IE6w%vhluZOR0TJW*Ow-CRPH4oDXhyMC;?D4oiB5au{h;4Ford{o
z@G-@slv(n=FEan;D5PypFBoMs<$#1K+pm*H?3wFBoIq9Gv#N06GhSgo$S&d%&SKVM
z>G3Nm%pw>If-n;Lx6V#`S~c`{NCHvj@%bm5Q08hN4UL1NZ8`#|33x&JsxqRG`>*Sq
z2K(2BW-j!Yf)#9PtJ8(6LjNDjpdgT-lz~YN38P0_JWS`WEfx=WUlyCo>%V@M^&3J3
zB+0{Me8DvXLU-38NF$CV7VgDS*$6sc;4;la{2GOoIW#YJ0cE&D^=NSMT&X{C7)Ww~
z9~0ctdPuLTO+Js4jW@@QsJm);H6e*hcIZFp8$iSI0u-TT@`Cte@uCqNr6Ed2_0F9e
zewa>lwyxqMuya%!gCiWyTl3fgH6mJ>HwP1ZB$eQjOxs%<I<w5COCHy)7zeNMQwr_|
zW%;3xhAD8m%}(ao6Lr-tN{t4+f<}ib%g**ONK3hMN3?}6C2O;BgM`Vl!qf-gge(5N
zENVY764Iyt2K8-%O`sC)(Y??hs${*+IcB@v9Z#@WZm+piCq36$=#S8>sAtZULiHYO
z=_2DhYv6dGlk=TIc88nlg^|@ZI_-zm5-~7ytSBnMz)I52Yi@yLO^;-YjT2R+zY2>@
zVkBgnzb4M^j&yFzZdKm9If{`N$R=F;)YQDHB?^s4V-u~KOplpT^!RBWf|QblKX0VI
zP@%I1Ti>l`JVh`y{+rmrU;n2-Vy?;+AJfrB)=iR=e=RA8FUK@!9v-RlPNYS48tiv%
zv!LYXCp5~)kS==lBZJf@3?{RfC11{dYNKty4+m-1@hIO5fn_e9go?oX%d!=%m~#TN
zP>Wc>YsNnKV8Ppj)oaNxl>jSM0RPw8y`67KbN#(JK1k|Wte>5Lt;M-$4DCKhW`>w=
zbH(B&i{IuEz8@NtZ$dW+y5+OJR<xG;+XC6S3Z9P=ZWFhf-cia??Tf3`oBgL8JcoOq
zFio?pqt6tgliaYv>Db(zftU|t_0DJaDyNXW^6yO9<C_0uej|Jqj4J1uBxxo_V84}d
zLi+>tt)<AOpf@!ZGo27Ws6?Uqk2?xJ27#F&XnLUzqC=Gu*2FAE^1h_T5hQC<-QK{y
zG|lP7a=)PCJ-Pxby$ozj-DJKAa%|PdkpF#6ym?9<@hMC>{%k1?TmI#_NBSXc@Np;r
zUkQ)Tun`;V{=P6DaBE&Ym$)gvo#*s;<9fOlta&?|+hhRpN8*9M7?7G2?Z<N&a-a)&
z^OGMt`4om66zTAo8(JUDyh`^;v?(?XTlA`{5aHcAvAetRWW~jO(yVj-(4&%aY7Axd
z;m-mv(#7_fpEj!>BymNW7^DM_Dp(R0H0nh4-$dG9pHyU^{>M!RiFsuw%R^Kx{YI6p
z#l4q@Sh9eD+;>5%UZ*TVpB@To_VHqBA*1q8?W>Js=F!Ig2wIk&Cc_OxoZ5Gqz)&dZ
zWOT%y-WRsR4};0|25~VhNT34ozsFYhu&dFc)<=GamTi!{$JD#&q6k90R1vOQDSc84
z%^&)RO0<vSB}%T58f8E?YW8~=i|{-<0I;@FiX2b}Bu)3^A#RSnD-J?PEc;yy?JwN&
zuc3W}s$uc08)`>DDhN>K07t8J<km@5b>GT$?kxZE{1nINb3t8xz1hUN?_<;Czmzd#
z7dB#YVaR6I8!0^)LEw#*LS74$5!Yyh{W`uJO_zwjU3F(AHLy2+;)MR${^C`PzYJFm
zyhDaSL^gP54SaY-i5_oZGBxTnNcf>cm^podgUNEgTg<BgA3-l)cc95vD!sE8s%!bX
zUkx6Usbm~U5<GA@u^thng^PCL19}F9%H6ykJt(zH4BWawzm?$7M>cV9gL>ld6!@>s
z&4a#0zL{`&N~<xCBg0>XmJP@e!AXln70gE3(6-kYq|&{n0^<*48Y=SY+7((WXD#@h
z&2_n)Q~pqX-#7C47$HYH8nkPCa~GcrBl7)zBejo#yVm|sUn#EN`>?+nD$1g;4BrA=
z%1#&IO?qfsZ_DK2-KCBi+s@1-3KYk)J&(^^mY}C19GRk4Ma{_nB%V1DvNe)Ml^<Go
zHSGoj&<Vrm8ONa*Q^6l~vQ&Q{bqD7YvFxdi*pDVM($(wdYl1lXC}pV}DE(atlI`25
zyl(<f31pLKbAR{}zzkw6KYlmD6P(!J5twB6YIrFm4GQV!TCU}gCT;Y^&eK3+|I;7;
zIjN#mS(J_10GRRP2Vzq++Hs_G256e90`-c57MeJ4l~Ch|tTgf4NDvq<1Q>t7=K*e3
z%oLCVYdg)tE2W)p3Di=ZW=jpdR2{^mw;La*DPuC;5N+C@0KW+$hzo!%xzVoZd!&`C
zOnKwHqjmF}lv@RgGD`y_q%{rO?~1m4OHrweBSxBC&s2c^$RGS<GF&MgOu4xnPYVFS
zMRd@T6{$_lsI)D;1)oH^t7U&g8JRkSW$ahL5Y^l{-;?dIS4||v2p8LwN(AuA7rGeU
zK5#U{A7(<;ftU$n@Gn8euQjU{+Rv*O(dDVeCTVtXqSIP#t`1N#?o@|oSgFz0?)LKI
zz1Z@K@G9dmp$uT%P3C)UNdgU(qWeE#YfAQQ0mhhj6bgDt5S$W!@frSF9*nu+>|xhs
zY`Jl99_$+3@A&Gh*@A2%s1(=IPQ$6TtAssNo5goUBM<zP^?+V%FI@>8ZMp@=Hoiwv
zD?vrFr0){Lnb+fiV^fw<LBt*UUD|VkCYW^~R13pBb>cv~cptB%JMA`~GS^{yaQ><z
z2+)-LSMq4e$zsA34^ss!@uE%&$;{{QZcy#|s3zQ1m_|2ZlyilE+5Thj7tvX^b6ZDU
z(<b8f;qdjpBFOg{lvD&f#UephzYfHlc<bbR$y$W54R|7oLA%`J!e__{H>bt*diXg%
zBjK8D<ks|YCsX4LfH!n14vy^@{vHxlRPesi+FQL6Z%U{{z`#?!<0v%llJG?1A_p7{
z00m<lZU{>>Su!{>cl*hw6MJTVt4w!b?bb6MX|gb0+<_G-kT>`&1C%mo;IJ_hWzK^m
zLu`ulK#LcG^Bwe?^s3eFpeI76Y%Pj+9zU_%IjcczxoteATq(n6AVe51mlO%!kOBCZ
zhfXa;uoQpU%HT)=65P>&IF!QL(w$A&HBg}Pc6-ff7CYd@^8=X6u!q%1Wd?h#gyfp1
zS@f!LZoM)0{BI$4Bc2t-tK2y?JT30A-Imo16z+TL0FKrB)s$<&+!Tb)ZdIlScWG(-
z%PGtdYNNU-GregE5aTFHx_wMjp2StceuPe-jEb4s%gnSs+0w||-5lAT4Izrh!G=OV
z<wy6H+C&GH4-h#uJ$U6CjNj=>QOT3a9ql;v&lZEfc*b7TSx}Xv;464l+6iw0!2-^$
zm7lFn@zb5*aCbQALL~j@5tPBynxE7Y`gQ^f--A|EfB@_J5+aeNrUOrynS}?dW}l*y
zU1>bQ#1f-ov8EQUEsp5Z8WTgE_)}pCuMj5=eV-`5Vji;~i4&@-$IF+RwzYaAH|Q?a
zip<m24{2Y$-D^|5vLQf&{%+Z{YJ0;(S(6IgRDaOTT=>^o(-r~(oc5Xr4Z$I^(yVGz
z^YEeAzGS3hhZ7#lQb$KhR;eIQJ0(2IG;i}q@-nU!b#0(|Q8a%VnLva;Tw(-!3Etlr
zX|?AYf|e=vAE*==`-1mdh0aSz{Mntn9+qywSi=0zC!&fH0>!Js8Y6fY$3F2Q_Qzs^
zs2>KhF?KQ1My?Jhgl(0r{1uty-K%)4kW2O5XYxEjFQPNDQ(ZjABwphv@wX>LI~$A0
zdlUPSKg*e1?ZVcWPe+#qyvoXP(HwmVgPU%Izw(d<Rots&ij=X0es=Z@cLoxsLrv&6
aP}`zF&*t5h#*vb?4y2z?lgLG{^0Kd(*ClBH

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v
new file mode 100644
index 0000000000000000000000000000000000000000..734e17b117a5213dccc167e46b5803e4f16a658a
GIT binary patch
literal 7672
zcmV<U9S7oz6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T5bEzkGV0-6O)bbX#zbSzNth5xsH
z=LE8U0IC46x8w8~!2{%mZO4A8OW-b@HY1g!vOL=VErMfBpq9!S!^NxpD<5jtoXBj3
z&O%2X$RAMti@R255I8SCl76Bc9Ki#kzPK+96+xZ7M51D3me@mYSjAUU6u*pzB9zQc
zu@xL^{Y<*7@3)2KvUKL9P+p2ZL=C=Kcp!twS0jw-TwB9(Z?diWS_Mbqok|pVK<R2Z
z6v1bL<iSdn%ID2f6ME>S9mfFQqGXYXQ6<W^IkRS%b4++adA&oAwk~0lIi<YrtSM1I
z6{|hB;rV~|4Pp#x@uoj=!pp#-`fbzuU7e%J;k)P6=kEn#Mh^{L6aBcjCHKFl{y`g#
zDM0&m@0U@F#7}efObe=_Zp^lSDavD!Fo-Jml{eg|{nSDZvSIsh^!tqbE#d0MCXc~S
z-0^^$W!=~yYFvf9^wJgTA|)`&?dfO^!~Cc?(^*|PgjF+Jh66(ph)-r1-cd@6o*VB_
zUT`nBldP(pt+yXZp!0s+?D%Q;;u4@tuNj!_P#VTfp|4ta8vg7_W#ko0_cVe7=shMK
z<yrnf!n#3?aLE5Z7_HIF9O$QA|A0Y`k37O(uE=(8uVyjs=KJCHte&lopmQCg_|;6^
z;|0PMFWA9OqN)~#_f7D8a5PD}04gA@xc*Mcs(hn4?B_dIU@67pwCo*gSos*py3IEz
zNA6&8bbn0FhjUR%cd`lL_xmEsU>qxrHkv#wTJQ}}U_=JwF{}e2{Vv^kRUypK6uc3x
zf&f5Ot1SS#O60GScS8=KAB=#u^h`fZMozzCpvE(dFMVui_ERc|<#M3(f7i{-#p0&^
zCfwW~wqQSjJQ8e*3P-f!-?(sW(J9>z9uvplHsw8WflNk4;`=vPOlO)8;`e<vy#1kb
z*EHlV=4eqOEm_^!6)!CvsD6_OM~3CUTrOQS(}>$iI@9K#^=rt_dHI*vQvBS@H88~P
zsUP%%tjiDv&Nfm9d4L~KTy`j?P&bKd$9BkI>!_eSrfj><acgtT<<0d~j)yPuKhh5q
zo;!%hjsdintjILyX{#jzmKDp)1YuLMVWoUzeCC?-|EZ114K2l<cba>CrnaQT#b8J%
zV!ie^ds$5hOU3U~&snR^!14MjFO)a{#0~b$z9<RSuof|#reNhXv^#j37|IZ;OXT93
zmKq#jhx!hAjQ<=^PBIbv_E9O5a29exLtRarz2(LH4;Kmo1g3}~!RZ)8uT-~ZPTu|H
z=YxQ(G{_9X4~w0D#@^jSMx^NW^T<2uMR4Lv`9<aP`{FnDhLSO)JG9>~c3}=qu0*y}
z;GG{hvjoCXJtJ<gtLYe>BVfYv7gp_ydQD-N2)7HT`5Y~OuM6sH2jp2;q#9&+pgwsH
zFzTUBgH(dp%0|3JU|S}VEdVMW80tnf2l}4S`{hBq#(<cgU0%fqx0k|l8r2F*(c);S
zwr+ex?=>{4zdrV%;C-01=}TCF<_HYW#yS0(h4MoXa#?*h_DZ5OBj-WGD^)AyULh`O
z)r?uUOIAOdlw%ru4?m8jJ~`u6ZNIBA%ylw-ynJ52s1fS&V>6{`C8oJvhJ}lZv>&GS
zAHz<vtC%rVSMlc#Mk9CxrsD2>ff9N?F<LWm*tu_h%{}3WMn1rZ){gVDBUw0U7ks5L
z(eIB{+?9S)D8~7lk(e|eLYOgF3h)p`VCG)CRKExRqxO_;FOOebZ*T58LUUXla|j{o
zhi4=QTLDNsEnDQe6C+NM2ZxXa!K45ib3B3J1LHey+{l}xyyo&>GF}pXxU-Fmz#pDX
zdpWu-Z}!j3nPZLUBOV*`DPq|a(h>W&dPxN;%zzE5JtK}t4d-GEF{eS{U(1Dy1@rK1
zwCJ}7FzX8~Fp2vUf&2Ik@Z9tJ7qE(fc&8j4_8{@{(mE#tL5?YjsDSAqif>(qomSEL
zZxJZ7g@~|Z!qwZSHHi5a)o@O}gTDjWy_}F%!zMb*>4`KJ(kTPnMO=OLk>v{*U-XO6
z-r~pC28<DP+Lpbr!0m_U4;2N;w_Sj*d>oqP50DWEM(e>MN+QM5lfN8J2{lGOa&RXa
zsB-;=rz16iE3aRb?D~`tZ);eWe1`A<(C5rC*o2v-?3!rIY?bnzN(0fcxH!z>EgkNk
z5HF`Cwka{FGNr}xpNOB-z3&fyHsoNJS&SBqvc*!$X#LSIVSZIp_IMSfaE$g;1GC~b
z06u(XDY;Vr2eix=CD@$t5bXIIgdNz3CdHKxF*cukK!m>4W}^t7BbgRlb_zW}W-rC+
z&-<>kFuYc|yNM!J6-Y2@ziA&!Y!rQs<ux@$cA@&>2?%Efz|-+Eu8@6#e4>Jt9%LyS
zd9Y)wz2?ArKSr9+l}KQ*{-7j8^VC<z_!y@EPmE!<OdV?;F(9_e?87>}y`bOYJI2Dj
znn;k1+f%y$Dnnx6hQ_B?QlRH*L17KZ43}@+-P%k*M+mUI!Q?!)L8y6^5c%;=PL-y#
z0+VrA5RYs0G~{&MwAkm1c@vGudju^fp1{t;(Uc>e6>WX`63^IO>v>Rsx{#k!TFU!N
z8LBh4bT>o%@55NQ2saRCah}S4LxBL_;V})YB(Mbzl!nNTbn_sSy>pRrs{FpRJ_(CX
z*96*$B~iBY;BOS3{x4Y{pCXN9L{SA>a(4j~W^*$#{U#U$we4gJLfdQXsg4Udz->{J
zMm2?0V=U`BT(uAKEK@9C4PqX0YL2mexR%j31-GqeONCY<6(fSa)r;vUAgO#uumXHO
z@l~eMK)W)|<m5Eb_rUr;=h{SPK{CZm2+cFLt==~#7SWd7y;rA98i{0N<?o6TK|wQ*
z2_Qk%wt8x4vx_4%tKH3GNiy^Dsize2;pxIB0`KD7gv;yDH<Wir4aS#tPP6~-<#;Bw
zVuqgZBwu+v&FAw<6A8XLtdm?E^m02d#~aW%(smzOG<$9~N0iMoOZ`875h-uxauG2#
zJF6UR+av&YUaUa>9{KCGGLV59paZ}u|DP<6hVzYQ#=A!R>55tc<o6}F=dZ2woMt^z
zohn=JNs73I2)atj!rm39VDVcBK+o)LXeSOVOPyyc6b-Avo&fH4WxBS!MY`nS9Y?ub
zJ9O8>x28?Xogye4Nh@e)`C-b?F)7EP(ipV70Y(zSlX$`;=By0p6cz;RE4!$%gba?M
zg8jY`V3f*;^QH@C(3vloCfeA_`g$ABy@Jy-`}cwjHR!dI-*I3rN|`|+Hf>Y*clQvv
z&_CU4GTR>;1mM5AGU38<AW}RJqg@FiyTq9;<V-?=%2MYIEKE&0cDWi1Z9Y4Mw@V)T
z=BbYU6_r0`<A3FmTN1mC@h7^Y7Mg&WtZ{<8k^YSv<DH+z=<pEv@%A;FmTgHgJ`T2!
zy<jek5Iv4t#GJXvgbltV8B|XAA3iqs&!YCLT+7t48WRbB1rt;xpcrr)&s7d5`eZLC
zWIxIwqb;Q-D2_r`o9ojpUP?QJe?H^@X7Zfj9XCMRsW%LS8|v~S)n$42ykP$oD;s^N
zA|`X4yc<nlzc=t;>*yJ4qkEOzP-1>JC?<kNsiu@QVV2+(C^LP!+J3NSe!pp~F;6bZ
zMDqIh8G!^~+nxR|v~iFsiE{_a!-J8M+y(4G+-*++Q!HTPtP|0nJm)~}X%4zfW4gyI
znjeX|sM7TwACki<f@*7fMXIHg<FD?+7oy+4#}HLF<cLi_5P1&>%1)pT8jm(6a(jpn
zN67HXt^Z{GRn#gl$su>a0d1)TaG<C*W~;WKxsD3XxV=DfnWiN$yVpb3uJnq{dFD5%
z#@sbi(AIWYPmzodtyrO2nA3nOQDe3j;41sfJ~jKDB&C!Axr|29xxw#=rt(RBtqRnK
zvJ+n09`E8BtR-P}R55@;3O@m)br!>5JVn~k2<QxP?XcOgB6c|h4lW^`zJ|B_28~QP
zZfHy++7_?8z~Cu0oYOrd+`%0ZlhER!Hz3IU)XTH%re<uLBF4Yl1Ka;e9j8M<qX|Xw
z)-Rf9RdRH=Co!SJIbBCA)!Z9z^WCz&BuPtNp#RAPFhN%;gzr(ec%)H5Kw@D|CH2E3
zHOoe}JwMTk=rGNuIJ~{`j0$vEGfm;1DdCwwZ+yibZ{CaDvSkH9nyfgcKm>~4gUv$V
zjud^HxWr$k3!kl>WbA46xKPrCHeaOWhVnkI2dd*lOIH@4Zscp*$lI~ZywS&NdlXzt
zHp1E3wf%O#eouanO5AI0*_(r3nP)bg-Epea?f`xv_c79YQSl|)N<2H1{byq6-<w>Y
z(!2D840;Pp1X~UN>WU;4L(PUQvEnjb5LYjU_K>}+%LH*1f%+Vep(|#$W7K8yBcMqO
zl#rXaW|VKIM^7RJ`!eVS2&!kc<Uchw&IFbLx>~Igg+LMWfS+a9nn%8AKvtz#5b~<s
zB1gD->)psJj#g&_O6iN2yBd-7s*M0BRe`jwMHDJQIHaq>Is!Sjd|jBCZLDUNW!B=c
z_RYps84Al-a#9cF(Y_Jhg=zWPB9|`$(-R5BA2BDSeM4G1L^WLJ?cVttxAP3LY6{?1
z+)TbYq@a(BzBG?NvB3^%6DtuiC+xVeK=SSbsf{nO#{5Ihr<B0hk66C&5b_llO-DD9
zOsB8x=Mkn6aViZ#Pg&P`{JQ#@M?UVcKlSPz*y(yt&6?3G&S(q;#S^2XECiXXO4{vL
z+n{MGEPeDX1g)9V9?9+8lcQib<vTwri1}=Txb=g#Qy6=0)RKM_O;90&J;k;roX;PZ
zA{G`D`g7Tpa($E&cGndT)JH&0-KQy&hw-4f(XKP#Y9!5p(&>OyG&GSX46_MV0xYbm
z&*_oRM@@|dCxEuyU*_~eOa?<ZWI`T9Z1A!lzjl^f>h^xy5qj!=1>yO}hoUH2Yo3bN
z$2sLVAkB`03qOk8a`Xq}Qqmva9HmC}?`MnhHE7YE9vZ$8-xo2+Bj0@x<4@m;1hN+@
zKuvUrOD7It+oL<5sFB5iruN(l48$tYfs%cK-MtP=L;-`m{YG4|0Ye235dPx^FDOT^
zj#aMfr5mxOQ&vmt0m!xe(_lpZo%ca=Lyp!126mD5)vE(mRg*0|<HwZqtYkyz{FB@$
zS&kl1#neB$-&!$TkouG5p6uk~@v%zm)1)z9aAjj@Y_|T!pR42C%5>QxB&T4VtRA0O
z7Nm4Alka-minn8^)BWBWEbc%q6@|lqiWg08?wP5;T1`dV2U3iYNUF{2l;=>qJ&G<9
zLJjC>5D$EeFEUza-nl>EYn-XHSvWDFEu92n<VA9qxONbqCRc@*?eb%w9)#{yl@1`U
z;7n`()B(e&3V#osI@0s~yCuO8Oq=7nuv&s)^{-*bmJKwEw{tw*s4QWiRgU~d4OYav
z5gY6ulH|JuiW@56px1}Tjf28HIG-%9_Aob$OEyO@g-W|s=?nq*Iy(Jue%e76!8YoE
zczICCiP>-Ks<6U<ZlHX^1lE~}kUo*Hzm%}pggqtio0*y?ZD=ShG>-#VTQ_i$@px1#
zTIb^|*<=u8)TIzPW{H!sjLpA|-GMSLpoQN7(hq8BbOraT*BlQ=VJ#Oa20OW>1(mXz
z*}q^hK}D&E960NV<&38gMBORWi@<`$RVCy`RRCQj%#FVKp^wV9%t&)qNiy|Zsuz{5
zW$X9ZSYV=9Q@VX*^67*X%lf#%P$tnS=Mv=F!#QX94gN;6L4dZU<p2RTnXpuru*i9u
z><}0~>w?UeSua-|z&22qGew@a*N=n3wKLE5?Ej(~#wYf+zTExKVJU3c{*%v~K1jVX
z-sw0&YsB8b{;4}f1~C0n_Kg(PZW9IH^R&8|Rl*C}kL^jT4s7>Re}ahI$2>QTsHcae
zIk=K|v|yNs=ZxB{u|^eP=4K2QN+^P&2Qr-=G!<+5FN(P4DR+*1AVcLIA>u#}1mz?W
zV50~TH7=E1p5#WPaK!(=^EF|$sQO$6e%dcx+uM}wNC<ZUChjQSK>E)2UvqxZLrh2q
zMWoQvL1x2rnd+l7eF=QGLOi1p;B-M`8;euW#BmCtA@Wo_GLuu7V_~_e->Tt^w~){l
zgJ6(hxO-j(wo#&%HTZp;M~k1OF-kUi2l#Y^x8!#e>qVTD`JQf^->sdc)huF*$Q>T0
z6$xxtxce>dX%ddb2PlVwYlySHW<WS$o=J|rW;b`qk%QfUb8(RpEF3FpXQQxh)dMen
z=CCVBrnGy9m*M6)3qj}QiL?`cp(sJ(O|K8_gy*31#(y@Uz~L*9Vz}8cQF@9q%8T`6
z`1>;q=CN>2y-EY<*p<sUh3k>r^Am16B@?}&JVdsw!T~?0StF%v0)(dhKEM6|Xf4M1
zy^mYX5<~zJfFC{}To#Y|O)V&Hp7vmo2E?8tl_p=w7=552MTbdd9%pr0;Ph3Bc=Eiw
z&ioB%d;En9kE@R2$$+$T6c@%l3-ud;)Vw-(_C=vs+SN6!ez|=C`YoERlGVQ2{d-cJ
z5Ror<v}=h<*4$s*;4ncO17UoEl<&Y>o<DuJC7z)a-8^t-s${oFh$VU6Gu0L8fh#GU
zs1N8`t?17^Q&B=9o)*-Luq9b<JM)>^>7hS}(QhZ$Ky}w_3%rfA{Wqio4AyO4;)78u
z?TiAmjFehDb%>bqgiCPW!R<HQS?eIgu|b#y6ETjzAXDavEtSJciO;w!CzxWDyGXQ7
zC%8E+ASWx0A<;>*c60biO38o@raX7&=>97>m@ieYoWnHcQ4`$v7N$ZDsvod$H`Wv)
z{Cv%VT#-qo|Hs&s`9B-iI=IeI=|2Hmv-ebKHkl7~fi|IWd5&H%GH*ChEKP=4O|g(@
zYsQ_RxRuY&@Sr{XkHpoyWsp(Zbe<CkA1vi72KnB49>N=n419r{{x$n*Vh_N~YeI(j
zTE_!t-;Ssqx0H^TKaX4Ej9lKB<mOQMVKSv?J^h`%$QQBt0{i);;WMnLg|73h3^&4x
z!3D4kxijwUUl2Q^y2k&5FQtn=&?Wz{U)|d?prGjuhnAtx#?GK9yH9)L*J~2eQ0Vvl
z><a@ydlysx!CA$3d^ZG)R5rkmZW;GSea6)5qcTP+`i+#!vMYphddseAw$e~KufU=u
z6k(H4wK1%ZR9*YqrrjRh#e0<%$6Z7GbyhVI+3MPEhboO6QiN>uUnD;mM|0)=T^#MC
zQ1DRQ2cxkgrQHAFi5W4qbx6dJg{?EIJ-gX$r#mqZ@b9cMMXNKsS)FPn(%=_>J!`Zw
z*jZ;^4S!Fbkel@zt+*5F_~+oV$VNQ_Nb>*DgFaI2&h%)H9IRtLO{8E8D|7iN@8QH9
z%e&~O?0y#_J*<M31gUd;U|HO<^8J2s&=HS02u$di5d8XNYuTn%2)I8T`D0#Cg))}h
z5B7QRcG+91qp&Q^TeFeGs~~dL;N%MemI~jq%5DovWce!V_oP^C6wO+e-n{Uw5%1TR
zS#sW9M_i=C7F61Qh+bmq7C@lF3@61f#VFBZAh3$^9h2AKk8;ub&#1V<6&7hHQ>PWl
zoyAs-k+s4)9|U;A#K=ZXV|=d{)+B?H9C@l63J_hI74%1{055B=IpV1;iOlSg0=l(;
zNZYXay|1p`@#32d`}{+7;xA-@0Rf)K@1b&tmiuH>GgY|RHUjBPhdk;7y*0df!g5xj
z2EWNHi_c!VaZZ>@^6fC@)hp%puU&_h3+6)+YV!6lh|=(LN5r=5GN>VT)1eW17&vo(
z%~T7dPP|^6@)(%_L(a9&K%!{ni}d?G?;KAM$o8t+XT^U?I)&CmcDI}-vS^4=7~(X4
zWvA4z4CD`v#O-&1w}~*zLPjp<hTUPKEj@OOgKpFFH8QnIbSErksSy;uldu_DCS2v~
zrp;ux;lN>^vE>g)^E*s7CjuH3aIU?S3t4R!3mA=34euHJbvEHih*xHKjIoPUnpxK(
z?*zg04#yrwzvZ)@qARo3sTGO<TH_&F0tBvBs}OCB{c7@6C`%<M0IcTW?~uuN^{V*6
z@e>enxr>*)Enw31bBrpQyRV8X%CF2+d3n~<HYVF6eJJ1>+61TleH&*T{+H;55t44t
z;Hzl(Wmblhv1^NAzuP^L8A)#3`^0bI4KQZ_s4_zxOUA=EJQA#@Wo`@AAnjosq74ny
zAtcf&)Lj;4bgk7x`I8VHuLwhcjD?<kC(n+UBA_B(sq5^|6$I%V=C2;t(#AguYz{JZ
zK&V0nu{Y3SM8kq@9b&eoRKCu{L731ZDUnz|p}f=H75L}xD+4(vJ=~7R>HtCYaCOP-
zN!6k4c^5Un=KnH^cLCzDPWoz<KeU#$C4_b1v0AvYwqW=`dfubS=>%aNeRkP{OJi(|
z%@UL)>Z|S-v0prug}OzIQ=d`v82c)apkL;I1<kQKM&m&ulz2LvjH$1Dn48!R1}Iv5
z+|tWntoP=xh;yljE!xo>%&9D+XlF>XgEt2`^=?uCCVg4_B)ETcT*@fBsi(Zfi%X$f
zPOo15W0#8`Jt>MO4J8%D4R8QHVihkbnHTWyna>7z37t(AxPA)ZP9!TF1mk~-Iu`h1
mlfd&>=#Q`s-Zh?%zF!E@J?-VDsWgivVxnO9ZXKL8iUp;y+V+G1

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..fd5e65cf83537bc358e60889547183335455c16b
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2CwH?mLw}I+2IfM=h;XO;8uxqv!3Zj~46Y
zi$c<gpd+rZzT*LRH?~OIk@xJzlz*dY_prN0z)_^~?dTMVHRkU^gP40?nu%kwd7cC2
z@m|pYpzzjsEMh&0y(P8zA9#O$Dt9x^h>}}?tyB`xA{p`D%_saf<tMjq#bIXJHSrL;
ztg3py84M{d3-9(qz^M&Hsnq#!UAtJ&6J>0;WaJY;?!0?aTB6KY2X1@<>Y~5J9#D3_
zF+vaD-&?lMN|F(`h$fWE9%MqW1!3E*fOR$1#rp)qo4l=_JT8E~nO54))+An-o|8pl
ztGN53BiS*uSU^*7)dG}2vp<yv_Ef7AyVeB=NXfM7YImeucj{X&1J-H(uAN@OppYvA
zy2d=MUYf!?M3hU0HY1@p&$ufraZ(Qzd>oRho|N6+v#3_}Y9#ny5DyD%TR45|b=RpE
SCE5?TO@(TdqSp0J*HJcuKB1xj

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..f27d21cf03ec99ba82d33459feaee56fec070bb5
GIT binary patch
literal 1336
zcmV-81;_e}6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2Cx;C*fKReY|%UhCVwgaXGO%IL;#vydC0}
ziDZ!1#iyR68#{~yN39n)G5Cmw@NSTa66E2yiLY`a2{E)z5E#HLdlaB?DcghGo_+Ec
z!iPR66w^r*7b~_1G)9}7!2qs-mKtyjY;YL?5c3@cdB1-^bHde<+3G=Ii70&gub=XQ
z$rjj-zoblh*o=)!1^UeqXQ8M(UkmmJ@7i+x(ZfoPQD<<{(PxMo2ZUqaV?8rAl=x$c
zGOCvKl<aZgiO~(su#x<o3E^~A7eCpN>UrB$w)WB0-VW8i|D^UVr}g@t+;L_NIb@6-
z_z_G_O^en7zqmVp-fb$TncsCq`Lx0qYzIC`NmIp&#xk||A=gL~7Dt<A&W$^PN9{-7
u`he4|xe1Is)YZRDI$)A>P1Ev_S08Ur_6JIAR(Bz-=qz^_m9>i!l#X*{;gDVc

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v
new file mode 100644
index 0000000000000000000000000000000000000000..f506c9e1ba2e1f10af2037eaab236ef6d0527fc1
GIT binary patch
literal 8640
zcmV;xAwS-W6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T5k(hgjeqDgNRZ>wm?NmCxYt5cW8
zYzp{T#3CIi5a6PSP@x(imiHgOjECIgZhY}BMt1Fl*UStMzKtAojrRq5k{kIP_M~Kz
zs<A}dZY-lNFJSD^ib#21>tw*h4D?LZH)uSJG7*-en<8N*=`6VVh#fIXh6=pe>C^qy
z-N2S7!|0toFV^e#8Sl&<uF`s1PvsHG0H820a~l>h&-FjT22ZyLvGlHQv#oow=zX^8
zbdNyUlTkm_Rz7@sC9ciq9!}L>6uF{`WlF-IbMJ6<jgY2VV2BXXQsiiVj8bm-cErM!
z2?TrDhWZv)ki;@%d;myU4yD2fU3V?Nf|xJ}Bz2hVf$rJ+q!*HFSUKy8=mTiCuywYS
z&fI!Wkvj}NUtxRQ4x%24;V4StGg<tEqgHU(-Y<aTR7KovUPwFJ5Jk2crgG(cV8TK*
zTBVEk2x-c@YE2^~(=p71WXY1^E2AtQnjx0?WBQ5E6-k!dzpb*uBe|-eXxn$Xqy^~n
zb-HrGFE9mu%{R$*rd9zdVUG?WF$Ux>9L|x_CSizRSGDO*k3?({Cj|Oby5-u(A<X;=
z2stmE7Q4jBJL66${3HF^=bm+(tvEVG?Kois8*x$a3qTSjlRhsixmyXbpu6(`CPl}r
zM^Y%{dYa$OWlTz|?rH3V#!7Dz^&bDie=Es1v(&xrw8<%}e%ZLZOCtI>V%UvIOO`Mg
z1_{$ZDkdekMlnbUsRuKUu!r7r>{)5cto%hUdH#swZ9I|k%`?@9W$hf&G1XpteG!N{
zmh-w-J+DIi{;DbJ%yzZ&I@6yANHKY&cGFTQt=u!`=&9M_d*`aWbo+K50-9==zTPQ{
zZ4h>HgCfLxS=UFK!gdOl4kK{SlM~JZIzKVw$ia$+!I`q@?IuIro@+e!v>^wy-qL>X
z6jy;R&N!+Q>~?x3{$lZ!Nxm9dqg{@!eQ$)`ER*C28b^XvkU3xt=BwWIQ9%Wu^|c^N
z32GY+jb|p(K+I5WKD3s5xqMFNJ(8+al<XUj{(FXNUl#39?CC@8Kh&9BAWK;yw7d{j
z<)oVxms1!n*xUTPNDfB@i1}Dcz*x+W&&5QZg23DYVPtq1@C#_E_Rjr|W^LE@f*Lmz
zx5dRn&zcj&HW=lnUka{qY%3bB8`}IYd6b8OR<o%N1t{czES8p&fz|QAvDWtmDK%@u
zoP9Fnz~F+Fm+XUu7%$8u&~|r;-A$gc9MPElLLvR19~$K~y=*NtJlt1n?~D%)+fKnQ
zu#vsjf7(h%)uYG6Cg>YoNo86<Z}X!by}gL$KT^$vv_-n{@Sw0C^u;`WJRz<&Z%+K(
zO-{#Gaf+OY%sZMzn23(r?VQ6c$o8Lkg(#G)!V+!oIpGB{@IK;Rxll7QN&7q$Lr9;v
zlw+H2-NJnN;k=PwunOEM{~J!bK!-S01_KzY{%>YR8LQ$Qgylo!Yi0)D+YR+oIGsX(
zyZrI5g{_`NBPk@}HN>Io_eygGmepb302WKstHy4#+sGST<Y+2uINvng`?OW1uVHL`
zoO%=t(e9rq4DoJ&OWZ4pu|ENVk6BG$GQBjTs0DN*P%ndDy<_YGE-k*8cNf>7?Z=PM
zwpk8tHn7s!Ww`AYR3^QD-{z{kP{0{}PQ}&BG2J4jNap^wp#=wOWI8<vq-{cNFY(BV
zH}yIR@I26t@>q(ej=)yxH478iB^jH5=MSXpB-VKPbs!uwwTP;L7MHG4_hMI7RnVME
zTbp(^iXSliI4!-)(m6s+ag@*vUiMJ6wEnGh74>;!d4Umo;Ur!(?cmwm?Xj*%^09n^
zbgjHeOQP);pj+gAAUqs!;-U>;h!1X(WOzyVJkF;FJt#*vAU${RuG!6A8{#8y81XHY
zkAP!0T8kD7{mQt57}T&s&UC5NlvunWS=^<143x4%+|gK$YAztyX$4ljdpCJo*X?Wh
z^4kNU7>R+orqS5j^5tVZ%2Rj80jF#(M%cjZefvNNby^@_YbZ=T+(#D`KGuA7w;fZ6
zT7Ru4=IBWHwy#9TZ`m-vR>}Jo9mTSy{PM+HoM`&Unbehg*EEje8H_Y}-AHu4I?3t?
z>P<B?=@qRp{n;ag0NC|P8xo$yQn{i_>M!b;rZ>XK$S^OacDdSEB?$hB)5G(ASJcbO
z9&e6^>7wM@REAn<aaM_#usOCALO~ax-_<V<By=s&ikB{+<h1nYHU2ExwQe5VWmf#Y
zyr;-`-3v0tEWt<X5fb@p+FhtJSnN=NbdOMn-<HE(XH>@A-31`btX#c^*vj`qr9(R1
z`U~AuP}888T{Hy=C@HDqC^IjG=j}LkEiT<V?bsP+xbx@Nv#er<of5b$P|sZ^JPev|
zhZW1|7D1emdE3gBM}*H7hQu@lb6J{ei{Q^S+bP(7^q;eK=2Rd+L5N*93r<}`v~E>2
zzI=XP{!TbAtAC3R4BZ?CBk#2LpQ(2D3XQjIYg5}Is<BWgu6q9iEda}@SoxG2$Y0r@
z!(!MwdMZX{G!Y%8XUr>;GmFHG!2E>TNEkc|((j77+#h)Ygp^s6d*M#HPOj4+^77Y2
zJ_7cHUp!ZW_8la`ps@1UJ(iE0YzA70aQ&9)p=JVH+W<VO6_{Zjv6K@QZ@|8uqet;Z
z8#&@~xpczm<@(HC){So_U|)T<^or0OqP%>1Pnvsh_V@ZeA*h7f^zNFD$N?$xL45=o
z5SiFHKqD+rnn#{_nPdc<Rk+CD&M9#=jKqw$G*Hk&Ip-S}vbwj+-bth|K-7FF7aaK;
z!bW;nHJ_}QC#gN?BLE7KwtV8Ory9rIlZ7L#1@7|dPB!CUvjbEC3f+UvQYJ9g<6;_k
zbVTQtG>sN`xKRPh8XH+r*E!W$PBh@i*cM47R4M4wH@@B#ggTBG$b7HPI{VZz-+9xh
z1b)SMK6goD?F*UL`rHl#>x5rF?zdKaD4AB`^e+yL5JGByMqPE~AVe1xub1k)fC`=7
zf-*s$YHP&`I_TjFoNw?Rg4&c8nXA`x(7Q`>oVBonD5U1_4LA5gfCaFUjV<_VbSzUH
z9=m{-kd8%JMoA}OhuG{K5aag&`5Qr9#p$Dr(s<U$>WhxSYczf=1`RP=b!z&es|n-+
zYV@EDi>lBoaXM;rKO~*V^~Jbch)IL2GIpH-zfn#LNqccok|nV)9r0<A(s__D@%aN=
zUP4sz{257ug_>vT58e>mlr#!P#aZ}}sqv+ZTSm?iVi%?$q`^Zis5TmiofV0biM2kB
z0Pxn59M*~q);t1EB9YZFifF|Wbu#c~Rz-!PFB&LA&9LlK`VzmW>)iEduxaO2%2~Nn
z<?5NoU%SeEN5_(_3KbC&P34+gqd}*gj-6wEq3TRdb9O=KLHJr}Tp4Gd^R$dpuipO<
zrbj#yM_=z(PCfvJaZ71PlN;auJiWtvs^6S1-Q930$_qZ;>%-y!J`LIg^ov^VI^FjL
z!5x>1#0z+e|6BH^+?tVMd}^Kk`Ec@A2fT7KZ~C=_i<_h=Cflb#Xf4gSJ?d_6c;<Q9
z=g1%Pr$6)94)#{vtZ0?S2afu+5+Fs3sE+C8<Je(Bq8-jT@Z2CR8%C|3-Fglo{i#>8
z;AUUQaLvFK#8nbwGVsS9D<(uF*eREARE4d0R!RUqedjxKv-NIp2I=UnFqET{B?nem
z%u2gAKe#De=_!b5sqX5yFK_rTa7o#M?<c$(D;I+g-JUQTmg=O(E0<fn-$Hd#sRCPU
zs3p^F>PM6>I<CJNzd@1$7;o<qfT}^uo!PLVp-IAA)@qz1i8mcWKMq?R!s^`=W}XW7
zppM;Ve>M9{>$s0~9!x2>o@CLR6J@s2T|19Z?m8xltylKj^<;XDe<X!g&;j-~>8H5r
z06{Bt6{2Dz>!xT~n;XkWznlEmp;Gsc`mu;43DW)3%Y<ZPd}IyC@V&6J^EeV8pV6lO
zf~yi)y#*W#BGxVyufJwi9!1KfvOz(GT#P{vR**m^c~SkaigemsThrNGM#y2DOH0Gr
zopi6SFuf9wQPI|J5EK>1?|R$O{`)ct(5iXQ8rt9!0S$q|3TlE>9+x9{=Tsh))7_fi
z=|lW<dGJ)#NVw{hRoJI^_kwaRBJ1nty(&lt`rQ=w(|Bjci{HE<7#<^r8+vSPe8U2-
zsh^p8!yXRQJq&pEE{N1Nrv7##{>rf@X~fTdd*LMo9(eyn!U&vEx@V^qqyqO;=Kh_x
ze=Zf&?Cl9bvb3^hB*-^M)P6}$w?Ga)m5d>T=-HYzHj#=Ti+3=U%pozsGm&HDyNDVm
zicguEOgZ%V;l^+qqmq_(p$9t)yV(N*-|I$H)n9?f7X$JUOllWQBcrFVU~a%g)qvwq
zAllph0&7WA#?d|acWjLL{i*Lo?NIoX%60h6YIUibf^7FAP0P?}(NukJPeNl*vueh$
zuo8Z&7_*~YrbfLk-G+2#Ir1^<yT2Frqf*f0={PO_KmIMXG+Y(BS?}fYHUjhzTPFjq
zx6VaRo6tnCbPcg((Fs_KQeS#liJ(#hbihVpIjn?M8{qjCV!%MD_Nv&4jF#g~-;!i&
z>k({8G$sT3Uo>Y0MrrrqDWZef-3rWUILgY!^b)APYs_0KMyr+dLUa>yKA<PB<1YT_
zUgz`JBAZwFNRr|`ka9Bq^K}*C_%>x?;@bUta0UW=84)`pwwXRJp6D30>T!%PkLi1S
zto&sYU5F-i1lQ*~cQjdpxSp3oxIqUwRBO7#lo1&>gpNu+%LhLh8Z)r~hNHZn&K9iY
zgS>awhw~!0Ena&i>lRtUB$b`itY~C~zvZ=xgh}LEQ~EIleB2*l8>K{On0)roGCfaX
z53U?p2*Xk$tVbl;JRZxSot^Gadyldc-%m20C-Zk#%Mdabq(^RqdTOc8f$KY<xxYr7
z_N)miVNO-g&Z>f4=Mf!Q=(}#cgVZm3A(@7k*g3bx5J9}d>cY;2SJdp(e$_H(Dey>`
zSxDX^)G-XiksP5jYP796Qu~?HNEu4nQQu&r#YNBX#Dd|<)mEeD`^le0AKzk%#+`R-
z6S_M$5}7Tp9w{703KnFfy7@;Xu+5_#^~TyW?!B_o`7=Z|TFIK4Hw_hPqP#@ZKdgi=
z4lWSPF(B7{gGy`+K;7fyHl54k#|ooP+1~|)V!e1cAj<2Kz=4Rw%-R?VD7VZ(4%!Y2
z@NohK${IYwt4Y?S>yja2nZCroRqQ&6Io0r~97ct~96o25!Q1;LUsXQsE00M}aj-)U
z{4GlP=2F(79+6D;j;h^8$`g{w<5;7zdaWv!CJOD2dKhL{j8I-s#+G%>LUAaXxEpBI
zI8#L%k4Ub@lR0iyu7xo-y7mjXN7IH=9l(OrrcDSgj(KVntQN_o!@RBqjDQ;vE|1dn
zRwh~sZ8r+MCj0JYf)ktxB;ASU27=A>L?Hdu+z!|{BdNzBX9<4J9l;FX0>{i`+ipDU
zeeO7q-NkOF!9ti}!bGe+K*0M!1tqHo8p_YmSD8G;_CKrUOa_w$@vMwP(*rGgpmXP~
z0o`b5S~wN#>@@Ko<B3vij(pN=2}<R25mQ}#_$~&-G(yR>BX=YGd{lN9aTD63bI=}h
zB*yxgtctQDquKF_cAeGAIAn^L%^DU#6*-qU;EKxX_p>OBA2pn0g&v=T%{-@G^hLgj
z@nDhVDTP)5Id7XBLoE2b`ajFyAy@*6xPu-+56(X6lF&I|6o*+54MQ*H$t;DK2S|H-
z`7Fy<o$u$KvZ_EK$=tYsj<`2Ds-t^cgFi-v&~g-rHSQazHF^MR5Hy=fQr55z9Ip}h
z_FR<Vw9x?mi$_^%a_O0!wBECzBu|O02iFa?vVH%jo$sG*3CNJ>R@X<jVy=^`E_1+{
zLE=)CgNFD0#@(WuH+FqSKm+N?>g!hxihKL0^Je2=MZ|fMKRrs{NOE{&0FP`*JoQ3V
zQF43p90!Fc7w%V~#%-@2=z?^apSk@nkDUv8Uy;WyXxiS@0c;4F;1&p8uZx#%bStuV
z$!N}g22$s@Ax1TjD?!a0uY=4%UK8l0hh($aC$BCw0zSr<5uL3RH_NMhHP$qZ=GU?P
z%FRh9kr42KNwLsFjSveq+r&ON{Zzs)x)QeF!<*2XwHhD>I?K6-^hsC_?e|6~n<&Z;
z9P<LY%H&N9^SS{OX&cjq9K6jKzkt}V?=1Q0n3cYu_Iz%Mqe9A-7b7eZt*FfjW~1aS
zr%`=|Y>xQnqDig$ekjOW8oV23>~)gtvC#_?3zsgx1h@80&P#9%mgP})CH+A~*g){O
z7lk&o4wUlN;JBl;2uV305;Tou;$9&={}Rl`7C<@Y`-^shK8dY1iZvYd9iG&yx9@*Y
zVBiU<Y-NiRCpU?~;S7w#zc_CRp8F~?yNllXuNs*Q1fhdac#Dh(+A!GqaQq&E9eJ&`
zV?0py?53MIRr|V{H}#x`jtSd&aTucq33y*9UV0Fp9&>3P*rbQwQTc^VyefK_SD^eY
zP3qG}lrA}~ZJP7LMLIg4T1!nR%#BuSZAFN_mXCQ01p5!!Fc{$IeodF9@xAqn=w@M0
zy3Jq}(<{A2x68r<*D*%%fKh7>2<{Hf2fvOkl1n46R;0pzTZW8TIcXt&{^dd!z#`53
z<scsCZMUnC>{L#@dmOaz>vPGKbQN3siIsw{)7GgoIe>xjstt|Zr@AM?-WHfz#QC}6
zo<ijSrrRbhTiTz$t<_?`SexLCGyq9qAAwesm^EZBj&T54OR+N{g@${Y0j`ZD{hi>Q
zE6Cu1OKF6m;>4>sOCGnw?X+v(+-><`mZrvaC|PpJT-(>DYl;A=jF8)s`mYn*b+~>A
z+hmk%9m3?BhuvM&LkYH;ELUkphs`eKjbu0hcC>mqN$QPMAlLVWvIG(#R-cfG;fW(=
zVf5!Rh@uMDZNEvI&U9jaHbPb2YT<Uh21#Fs3_&p>>VYJImnpyWkxiT=MdW6OolraD
z5=dknTNsjU(@SsrWCp^@V&{Bh3GCMWk1kC9W}xi#)b(o@^Sly7?yknY5ZYj&qzQwh
zm-&ydZqb*sL*uXmTW_{m2u@ryGlZ!I($BVI))I}2cdfJk8MugF!aQ=N6>T9P(=E*B
z;5_%j8IDjn^6}_W^6)IqE)crD`zAF4lo3f};(R?SN5y+Ws!%tXSw{(kAa~RG29WFR
z%Cq6I7Nid@f0GfQ9o15=+m?=X=g;814jSAWwYpd7Jd=9shy7^C0=5^A!6dQnk<H(|
zb}AM8M!Y|S7oXHHhoEAn3YQ=waRe2kdm=n-O&(R;e7R)!`Xb?;arIxyX2zt~!vyIH
z#z|5BgwFpDi><fnvIy5pkbpuP;$+Qn6Hg_h-C88Hx!{v;m{H17OF4kKFba(^!W{wE
zf2*cbja%$6y7Yx{3aS4&+xYALuZlsUhBL~8yE`rJxBYI7vf3+a&gA=xz5BU_25-mY
z<j@9>v8>2NKZP=!ga_d1B@e4_J%<O9%*wc|XM}eO2ae9E?-`O+S3MnTC-Yh+VL_pL
zB0%{%dZXzm$qmx}+yJ}$v4xPt`_&ZydqrJ>*WPTpo#!B0{<g}85Hj%*F+N*5LwL)R
zFe(_P`uElyKF#vKCt^XOcx+Nem1LC(hDVJA_eXfU|1uo70h982!!ksBXqssc=kOp@
zSG%{^3mpCZ%&o|GMTF2wY$gyX6)Ed?$>>o;vJ_8_Efpm$lYDF=3|}-NFgf#E-S>XI
zR^3fOEv2+daT>)!=Cc85QlEvKbXD#1!Wd?%q9|s0xW8DvFa$pEm(EER6OV%1*|8iC
zr&_AF5qJ<VYZiV|5DZYIm9-=OMJ_-k^NsTYlVuUv*kLxJ;a{@B{T<0=ZxocsBsqA4
z6hw<VHj0J(YB}2r`xaNa%s3fy@kG$B5KVPol@=X87*>Fe>qjC9&apeZHX~FmKzxIn
zcNVtY69VtJwRwT<KL~NOKn^fr3h_9rx=v|c(}pG9r_1(44`#D(e9s$UYz<RbHHWM@
znZ*=f54Kw`RDd262<NZGENk-UTMgvd9bY285NHHjpQbV4_0Im7JmNmN%m;0L*gxj*
z9sD8DAXLo~=wNqdZ>_Kx7Y-ZQqEfLsqtYL?yA3|c@SJ(t_*6R*CU}>!QaASu@+Y94
zE9TyK!UeP6dH)#H%4Kh3vB8y}0Xq~|Ov8ehCxOYo+-yY%iFnOJW#L`j=f43omg8Ki
zP`eDs--u(HZaQloPZ9`NZ(Di8{ruWh>=kr(NPpZb63?a_x|tpv=5x@gGv*eJxq;jj
zrFh}S=r4N%WhhrG3uW`5<$^ypSbWzA(1wZsD#=WJGR;-B1%p)U2kwcD?xt$2tRvyu
zp$GWTIfwFr1A!7oCNUNw@=%QK7Iy?pxv6_^oqX2KL%><G;)L*?ZNq4cjDx3PxtJw6
zbSD!qh%mLupDPl`KpmCf>&@tI3MM>1$Hi1a2);L2{4oNi?59Pgt%)LkN#Hqv_p-w`
zI@OhjJHkkJ&-!3m{lZ-%1`3(DEVd?arSdbM<3ogwTm}+_dLK%$L`P)Np<z@0ZB0Z?
z&y5I+eO&$1WGxhwr`HH?M)3#~S4a^V>)%ENCtm6AB%@YPg-HIotk&1kbdyx!qEMwx
zb_EGmMsuVfKEx}r^KjxS&U*s8S}iK?ILAMUI9l(NqY`-8YF~)&8_n%<RIW=ow~<NQ
ztBZ0y>BX8X&0T$#nJ9M+Nk|5*KXleb?(kJC_%AZrmn<N0at(1D46@41i1~^n#pT3E
zpG|j#jHqY2=rIL;_2E4?bKB6$@MCZ*byrAd*l7D>PD~GmfiPh5bCd>CpZtA^`-pk(
zQtyu#O~hu5#+3>YC-0tfuFeZEZNc0(Jzg2=f~-Y4LmNegD~5hSyz`%cfvZ;sfO5_V
z{1`1oZ_rv{*IJMqebz$u?;adi;0snWPPR$3e=+GSq+^@H`=>*eKq)`Wj@*$_YV>`6
zXWB=-rh9M?>a_y$3U}2*9~tj&_-DeF4mH?0d;QzK-M6q2fB4??5sL2vI0fh-?l16i
zyV%i!m4hxT(h7G-QT9Gu%5Z>c<>Mz%&|SXpz^i31TLMO#55B*4Rgi&A)J4;ROkbcm
z>Vwhv?J8E<$)ykZnizM|Ln64VkS@c%DnC3EiWN&k>Tq!eq$4f|vhO1SOy$Xac1#8!
zoTo)8x~D7<KIUkhltdixzG597d4<jzf+gx;g{5`b?t8I!ppJhGy2BD;wH8m#iB&{;
z9m@JMa$;=WqPTJbJHl=RrZbESv144E@(s{Ls-_7vQ35c4Q-Yp}l2#h7ZaH;Z5788%
z*UN3`Dkmt<Hz(W%N$QAH&`55BCd3%`7ziuKq`@0*EXKK=V)z&EF11}2k971OfJ{5Z
z9jo`TUI|qF(jEGk8X`d5NP!uiJ@24~tSVOUYB=3N=2oWei_Bg@^H+4hkRlH(+v7r`
zz!fQ_Kc!-L%u4n|92%hyyjR(xcScz$jJX;b)Zd3w4&J%{j6l5z;O%#`kdg)&t<FFN
z1?X|9$1bDlOVuvGwlx>R5}J%o;vXmS9%QA9Anc0$s1>UvE`&o|7Ktn%g2t3iv1NtE
zOGP5ABgG##xw3wBaV`E195EVyMxvM*OT(kF&TG9_5_$PN8zZI@YZXik62@pBZVE;i
zunbq)?q%2}hZE)EYYo_y|1^4I1YbH+jtdm3!g)O@JOvxBl~CJ)_}{j1EuH5PD#715
zWXa!!zL*!|D~n8RK~TIpVvz1Fpy_SRECEfBlHy~0{L?7@7R;RLC%Me^La~%S`(06Z
za@xD1w1D|sbS6;78%(&;_AQi-0lD86c;3So&cbu8l>mFjt|$%hPskI^JQH*aD(z_$
Svm2`+XRB|9`Lfh6g!dId-o1MO

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..1b6b5342ba00ace80c26a41de81eb0cbf3cb8839
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2CwrVbiu_={t3)hr8@t$Gr3_vv)OQU$@5r
zWc>+Tj`3vAAJyz&5R58RXy^k_0nt}KL%L3P?%rELNlg){YSa2Fc51jW1sq+pVM`E$
z!M2-l5$*VnmNSC1@O;EPSQ+|Mat<+Q&(TS&E)NLvU64epHfd#@v@$;7kjNlviLvV~
zc|lPGEmjOSgQs7_$v(s>HX3(etC9%DaPJo`2X5CmSslCucOL9-8lFmo=3I7lOoV|z
zn(1aeKOAg!o3T%+4q8kcEExt>KD{3xdbC#Z9s0#z1W=d^bztwMwk(#gJSt^evW%&s
zj-idB`u@fFN>o(VJ`V%3<TT}}^~u=XHmWgqxX^r6wk#;rQ?S!uFMq4Ig8wECo&I{A
z24<pGTx(I?Dp2?KG&{}ejs@Zf7;brtT14#BVF_*EO)@zw%{(@t_a=47UlIag^q^$g
S><loW{qY>d_=^p1g<1>m{FMv<

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v
new file mode 100644
index 0000000000000000000000000000000000000000..b40927fb4cd31e0280da157d740fa32054ec72ff
GIT binary patch
literal 9424
zcmV;>Brn^G6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T4z_DlI+3#wlc4c-P`GGeGjh1*FV
zGV8%^s^suVOVef5T`Xt;262FIZ7!u7=|miJBZgRHo+^NEUyyHGtQ#WJ&V_8wevk3@
zWpGVfFIOXDFi8xBm~5f3<P=~!Xa8`6rt<fSB^e$t`w}l<X@+5&@Cp~%Av`l+ncHp*
zKYyU?tUnrPGJ?W)Gr^>C+uooiyc_+XPH4{9kL!h0g)b7Y)+zNU6l&M3a|bAt?s(jd
zjFwwI*XdUG%U^oYD94s)15x>XZ{5@aw>8hA3&Y-27&dXa!7zOnMbhj0+l^E!yFqNW
z;M2_1DTBv*!h6Hk#-Lp<_)n#~m3JI~b=PC=g`rCFJn5YHQgMc4L$&aEd~driC6~V}
zH%RN)4X8uO{5OPd!sDerooDQDuaMZs$?T*!(;zU+<xoN|syg~W8DzN0L6b+m$iV-(
z{N}(YAuZToT%ts5d8JKmyM?N$0!T~TC_%Jy{5$qom@y|%e%`&<&My*`N_D3?oM(Vt
z@Sy_Y5!;7gwKOHQ1zoq4s+e8c(J~)g?N=B+wh`b7&^en*I9dn3?lU;!T2J`?vlGvv
zsSs&F#Mt3q*>?^o;*RFP&mg%ivjl2>>jc5emCUFDdd!(6*n9h>&N29r^ni>*(D~OS
z4D0QSmi((Ktq+41#~yV74kj657meHCmP63#2e_qwI>Hjv6t|CNmNzMQtClkhMVVqk
z!t4aWvY<wJL+Do(T(j%#+F^QQFiO~fPuXswhzh_R0o~4qgN}<zKT_1in)CGpOZ+Bq
zYjI@U=UWn$B~AaZpoU-$s-!(Nt4_UCj+bTD@z24}D7aIDv}Fzl!-*7#;1SU<GNkWJ
zc>4^-!rv+SKl#__<rv_XYSu=OhRv-rb$Zvng1}TrSo_x$l76j=!My5VpS4+Wf>K`N
z2^E1v))&r5?s_R41!s+rr|zR-2?kotxyM3&gzXo2>NJ=$5p-GhIS>iD8NZi=%gd6J
zG>ZL>_V6@LpP1OmKn;c5era+ZU?a-=Q7U`;?b3o6OIQHgo-#?dZ1hw*GdLsgF}=-~
zgPdMO0j<&CA&o<d3HfO5C`UrUv;qlGRDyVpW527;5@yobfAz$TgcqG52OLb-p9LY|
zK0~Z;;3eJGr!K?XeF@qKUJUP#^chjQ&)HE~Fn17C*GQU+j}r>RQ;8s0sNnI~W>Y2u
zM$on8Iq4)W72|lUm1wJP30&8oE52qQs;HVe4_4Us<}eN5;tkkua{{3mA2&gPeZE&V
z2n!C*CLwld2AhQ_DmYiT6@cc6!X`j)zbH>AJOY;N1t4Z|#6kYO6zn5xhcr~ZO1+X!
z#WQyfa3VIIqCS_#sIU^uf~S8++Pdi3`)tXlqU$UOq(zUA{BoJ@v1dY(Vw4&<>t4Wh
zS%{~CB>A_>^e;*s)IV6Pw9i6obb$vzVG+!%6@%l!r@9|bQnze>ZX``*u1iPnifn7F
z^R1oq!<nYu>Fe_RV34wo;5~>#!TSgUfpw2U&iTKZLPS06ov%I-lH!AsiTH|KxnmF~
zr(YeD-3V;Pf$Rq+g*dYCh;JqGi`VP%^2z#{Q!OOY`$`MLlwW)USaL>d2k=Qd`^g*_
zoAu`nrAk1XXkyNl=$b5XwUDPxHA=Z!aTkC70?_iavx!#lDKO~)>Ic>Lai}Q!iofa0
z7~GA5M+`~LlHGP;?gikIGz@$^Be|htI(N&T^6{A~POV&?2TH~6)B3Rs*%ZE9l@QHS
z@0y!7KYW4@r#?MWk%_UvAJr9k;0!(AOU_x)>s{!$mS@lQ=yYE@J6C@G#9t-Fl%N3V
zjLS&)R3*gB;I6;BJ|Pw%^3j0N*qr(lG-3acV>#e-)3A+J?TS1cxC1=t26t=#rGrzl
za0g;{&m=>cwMP+p8sIJIN38<s1Nju!$L7k6+1X9m)_xMkY^CuXONhZ1$3k=#;Tj4d
zvgVKlAw->p7)bL1=cZTmizq+HhKsBgIJ!?}Hua$tU9wp;{ut`c&%~fWy~a=h7nsdh
ztx)zod0CZWBCUX<vP6NN5;=5C+C5G2zy_O`p}|qzVRxj2IpALkUwHC1UyCfO?EfNQ
za;}(qiXb&oWy|ow`Vud=I~4GaL2VAGLSSbxH6R*vpUY_WTb;DIj~pC|O{ZN>hDuGk
z@azKM(*GW;7a^D{hKRTbb3>)mH<weQ4N=2-(#d<mz<=x#03zjU3Ia4ZFe*(xIa0H~
zsilQBv|dISLiufSyEkCfGk~cojv7&}E`98rZ8%S0PBe*g9&R<P$`nZmk!`DWpd`mq
z0{(t30uPhXAQ$J;K}+KL3oP=JI^%|iQ)JP<!|^AP{gymIb;9q~A7gqZkjovtR;Mtp
zKGm#0pXRDDAcmGaYHxaylU-={!hA>%6XS{kmNCmmlpPMUzDP_Hg$^O)6lfaxn!UjN
zjS*mbU+`xBDSIE=;4kFF5m13fmGDnmHPQseVfr3$bapA%dg7_rMA$5HNIw>`d?FD;
zbbRvy|4(k(m_X&oZ8^mgR{iL<jRzuSUb!Fm`ntC0gorzc7L1+4U-Gr5XLroGa@2U$
zl~2AT27M4!>npu%!c5LpePb^sPOH7b;xkDx3Oi=tVJ^OJir4x>UswD9zS{|18L*Gs
z0w()=fmdh>9(0)BxAlO#!GGM*hw&|asp?IGEL3?n3deg9;We>@rdcF}d--GBdspVk
z;ht`W9*FlV$6m>Kvp7+MLuAj<#JcD=QDq9;fc4ZZ0ddG8?3TTZjLyV<Y9tWjQUpqh
z535Z9kU)55xi#%Fz{h(Y4L`fyjYR{&xCwI3PRRtp1z1~GK&bDAlLPbc$F+eaf3Gz1
z3aQIc)&yCt1>l_oJq`(xkl7g5qG}bC5)wM$r2vxDoGojFJ`EpFNb?4Z;D5t7@XuMt
z+E-MraZL2`89W~Az@G6J;~FM=rc=K>U7y&{b){5`S|sNz7}K4;YS(>D3h5f;s>VA|
z>76rj1_x&K0)d99F=IilV4U4CDh@_1R-+5SCDQGUr1DjsMs3T_5#N2)bq+!8%r%-&
zp{N$+t71^|O&s0#@Pd9oMD1RJB4||6?vk6{&ruQbiF!G3&F{{A0g=7N$>=Xp63TlR
zE0-Bx>T4Ki$9hDLy)&XIwVHO0sheCd0{~TOPjQAkM{c51JF-~tm2m9)<C1iQ{yYea
z%d#a1$Rx-o7jT&u&kF~4F>7IWZnqZWg(c~~I%a$hj199uOnJ^7JM<*?|0vRIpVR4&
zhtqEGU>%Bl(_I^~dLWIUsR6bIyb4I3_DY{UTyRi)S~Kc(aofIGFtWZx*zk8MqVGy?
zyjy=BSIIN*SvB6RM>}%ikiAvg>|&Mx#q8@FII|~fcEh@tJSy7+JT^sYCWm*|Yvji%
z(}mdoUGT{s2SQfNKv4`Uu#3wmp=$eReGc$+ZgPT?%~mD(lwxUN!}&W70B}4oBI{bL
zFW4C*@pu1e8RJ{xGN)eZ9w3;|HfRuYZ`9LM8DB0@V0b!VapflDxtz6kRaDeQ7?wT<
z(j){*8-T0|=LV9h$aq2H=hilrqUE4+#JxsMwn0R<*LpJH?O_F6#LqR3%s%y*{Izp5
zCAfk=I&Iv`A0uksxXJcFr)QDkx9&}^nx-sB#!?4^?{vdu^#ViNMy@5$oJz7Ak8QnN
z%F;!JO0?6I!8xC10McgZbM)==%}=e%ug}uj{6UiAwwgL`e}6hc<7VSuyl5<y-%?cR
z$@-|On0T6_7FXbOkkwimrQBl1`6<@vtdA!Hw*WR#p6fOlOko+hhAm22PMhUXvcUF!
z?iXHcT%N1OEl-Z6b2BCN0lK6ubaImc)p5k|Xqn6#xV>>`wnL6+&W_<$W$gl*<nzd2
zX?pczoX_6q(u`y{cY^%!T&l+M%p%WgmG2gzP+S^ErxU*z@|#m3shce*;qU)<cSl*_
z=g4K0?Xp9H$N`rsQ237HiJ%pGj~b=V1~wB{=1vD|ZEpSn9b;r)=%0n)V=w}F1uzJW
zs}A?BfRk4WKL+n=L(`%|JxD8Bwtx(EXtwOnB!y~wYfVWkGhE-KgHm%KI5Sh+O`MAo
zjn-*hoX-DGJgjFPnciXg<ucK<Ht!BW^@=bUZ(QlFF?_IHq8)vjyh<Z@HZ6Uq*6%BR
z2rn*u7f?QdC+R@@6D7!?#}9PzbVdyV2JXsk94_N$QJx=Av3976zQcZY_=Z=YE)zZu
z!JjPWMOR9y^Sf;#N7l7YRgqMcD<X%AMl`+9PQoZ?_j`L@1>XPpA1J`RK;A&wrcqC}
zs0^fiC!xH_c3UH6dAm<0jl}39$@TA751T~yUiJ?J)Y8078n$2FcAh*#059-#5|ZIX
zO}Qy-I>gQZx!t}y<eG=afkMB}0!w%_xi4CuZ@!S4p`GdhA!fd=8phpOp(|gv67r?+
z$LWysl4uLZaIpr$cNK>~{tG==_lM-J^w%tw=!JVu;|KM!&M}{9_5x|=2v!gI8bZ4h
z$1CZCuqDc2&TcOA1T<P$?-m?q4k5wt!$uKe7&=BWv_x|%TT2UaS)(qxiQ7Oxk#6?U
z=#0<P0cTd;rx+*BX7W^wI9>K*G}p=~Z2qTTL|C{1OuLoTAN$E~^pY}Kz0h&4_4>>j
zn2B`_5j|UyO_Rds6Fn|s|2G@oQMS}E=We<*7maaL0ILh#RWGl|XueW!)#EuF*Nr_O
zXFj;evWT+Bf8BupbcX@Zxqmln9K~Ujx56DFKdDRU5_=i>#Fg&=A57I3<W4>_mSpM%
zMR@W99ddxG;f|LABi@$ARYTD|eLc>6a#1Y4Shdmwv|)GUQQwh%RR>e@kf6+VSUkZ?
z06C{(a}TP&;T6&%{3*3W0VppiQ?GAn`V4Bq>`7OX*Zq--5JJm>WWY8oih)Us)^Kls
z5!e673q&JlzwQ~%Ny6E?_jNyqy3IFE&;FxPg`0Jmvzlk_hgQ!*6-k*6Q3;vV91P`s
zI6BvH=k>Gnl7XZsl38mFitPdy>Z{Jhnz(CTg*YT(vBNROn-ouv3XPa-W;DfSiZFNi
z^|FDAn;f^rRb0@j8?4256fi!s-5{ucveM7DjBA3`fBl?TRZ`(U6J-@uFE<yKm~#J5
z4@Y=PfwwuN9Oxshe8X>^`76`3+B)hFaI9%dN+B?DdNh0t(MGiTHdI{c)1p^4bXHI1
z<#h@BL%hPRESVRk6|b$6RNF701i45VzvyEeO(tBW)rIHp^on(lML0pF)!v*%n}K}H
ztm1cX>Ee)e5^JwzAbtbB2lATTyuWnT&z>R<=LZLhC9n|)B#2417&=R0>m9f?%h~;N
z91Tj~Cvdr@<`!#LX(Qo_@R0-DEW>jFcIG|9<5QKtYO8Tjvo~Rxg5iO8q@_Ye0A>`w
zog4GXAMJhJR}k+PIo=En!Fpo|floh^;i!8Ip>uIM2HR`3MQJOd(fGLQwx7R3MDvL?
zDX3{>$TV;eH`9>ZgF<$o&0~F;gsN6LB%Se;6@j&jl2F<((aXAVv00D<OzM+f-9l2Q
zc<4jdNWo0Axx8_2B?5p5J|1&2h)l;(<QwC`Ke~~(aaX)&@G92=z|OlFUo&hG6WtdR
zIAUrqs8Ryn5vg}}0&KZHfXJ^7FNQ<!w+sK+WlD@lAjac!1_xxCnkY};sv~fWFa1@y
zh!2DqAuA=8J6K;Who8+sC2itvpdq1PJ8kUUC4!}{a`&+Z3QR>TPJsJdK?sS@V`Wu>
z=^$MHyj+2G3RmZn;!<w%-*f-d@2*&6qDb4Bxof?UH=O0eaM|X+bm)gWxfq!kc(U1P
zBO7Meq)#Bb3*@&Z1v#LZ0qx7D#Ik^f0$UFo?kOpla=jt^5BYr~q|Bp2Dbi1@E{YsL
zyDB@9$f;VTk8@cILKk5=4h99ZSot>&m<C%s94f{8UILiPXPKOpn|^e_c)F?4T(=7T
z=VntvU9Jw9NT5k2_cr7Hm@-=r7qqHtN0i7qjs)@<GKi>WfwdFU)sSb)Ebuy5UH#C6
zN^hCvxz)ABgUaXZtpD-Z`ff)FN2^kP;Ul74N91wa0LPK*0>pAOYN*uiT6#g4N3tYJ
zhQI%J3~pS$@=3NNb@_L;>xrlZ$b-kNbZEs)S>bw6Sv;%h+2NRP$1_`6mzUsayo`Pr
zX?&F{rR_^+%D!H`4Q&$T4%Jp?(*&YEW#%4)VMcuDnel=uEpp0WAX|%pei=kF1_%7z
zG)1O#B#RavKPPf6((yj-Fx$a&FkF+x&P&5mIjo6#c_gB@S_7GcEaG25);-8F6S=<9
zrnANTuegWaY%6Rz!gzvr6eBfa8=nWJLe-67ke@{xzqG%Z?TpTnQKiDqJl~RZ-g#Oc
zLgR3@FeH+)GNcm%nsJvpwy9(ktR_6un6J~8bLIh7SUzt)B89Lg#$fTr6XXl)L7>iN
zTeguiryvi8md{yM52q)4w|8j;Ow!!UI{KaxAh<R!vb*wFS+hn$i<=}PDo)KNg;((+
z9{%a^EsIr;sG!9#%~+ybOcy<)R<vB;4<gosl!j@gKK$6_OJ6x^nAk%it*W8Jxo^Q(
z4!i5XbL>1~qiOJnWFI$f>StWO<pKq=sp*V2EdJ3~;6M9(Zu5_8PzndmbP1~#lHx3!
z_n-d@C+hn4iL=@7^}yywqa{uokVH|Tt3eZhwT*D&eWd(~(=H!F(*XvaW6HJ4i-`or
zV9@9uCygp_YkPZ@amMnz6-mX7sMZBLvS8{3)&wMkb=cQo`bZOpX!h%MO0hKpS&bo9
zLGVI(Dy9%_nixYp%4$<Z`!I$?QJX*TaX4J)UF#+|jpE4!n)49pfugL*<=%Y;VTxVd
zH>@ytfn)t;lkUQ1INRJv$?)`vgVCO>_K(vv`X(fkk5D8R^>p+i9k78>>*!Fyn4#DX
zSWpg~5`nzS?m_9QKVjsEMh~aaggk$4sgrnIGXY-zTJxgC(txoJgc_I~09Jc8gCtoh
zIN<3+-X?+>7Zcbt`X=gazB+Lf($HHNqYl1PP^Uz{Jke-KUSw9M6vMC`sFT&+MgvpK
zgeqR0?N<+KLFZH+>L5tQBn_V(@kexQh+C60O}30z-%d7E&U!pfS=0h6f#}={mIyR*
z)pkWqx5Ih$K_r#72D}Cdtv#jNLIm(NZs(Ll7OC18p@5dUVMd&=9rf$f0aOT*nQ)l?
za)WU1g*YT=Tve<CyzaUqBWGX2$YfwHfp=(ges>y-voj=BY`=$4+=(l=V-L9|9QZ9E
zPz+lG_X<Idug4aA-2^$elq2F#0Ci$eu01SSVTpk2iCm?@=q5#3%8lrD+-WeUok_Zj
zlYdwhcr%+Hf^M#c>4GxT?C7n|#z)g93x@#Bd%nJ~lA8o<IAa$`17ExStsAQ!uHk0B
z91Ns?&;sz6qt-o@xVV!B87CoGQ>hV|aDUM`IoJrIc(YJM#;Wm}nK04C8MxYyK-R`V
z7(^CS&5$%wEQ7V6mf~X~YKB|er@q5b0aW$E5PB0N6Ks=hwr(?jlzCLbC}Bdld;0y2
zu!I&c_Ahm){dApulVKwg;;+jXlBWVC6eQrY$mBJa{U+tJlkP}hADgbCzq@Hg?<c%k
zQ-G;TysU8Xib#$}e@Y`b5VVpCA|*XubJ(LoYjb2ht3qo8D;LL~c-d?%V{R;RBG1sz
z7QlY6EE=!(fS;EVD$W{zDc>R&!yGj#K3<c1nHfQ<+tqJN^>oTYEpQkY0f=EjzpML5
zDkt09<(YDrRmM3I$<*RvUY!=w-a=6LB7QMa=R3!gIpN)7w8mJkypA-_f8VI)8S!dX
z;Om<m@lu|)5c;SAqdjb;LqTb67nXc~uLckR`A3UzM;zOXofhG;6CTivK<Ka|qV07n
zoi|dx$OXlR=F<l#w{u0YKP#LJ`M<k{3B{d2HlyG@^4v_uc{~p3xH~VuN1(nADO$_Z
zQk>|uw-lrK*R?Ib51zk)MlNwM9)CLNXJ;^5kLbq8Iu|0Pf%ktv2U`{NuNorfO(nQy
z>Kn>r`a_^xL%d)|{KZ|7sqDw7@;6lpEYBtiF+~qZS>1DUS`Zh+65rK=z0Snnb>J2}
zFxO@o^f`WG`*@(Bhei&nKVP(6MJ)julx16RQZ{1Z!`d*`WIAv$EYeaCC%1(rKR@F4
z#r!?p9(njaMY|kz-DJdo>Y^pWJ}Bl3vffi3=s8*rJogW&&1ZJqt4vPXFa%G13&w0S
zN8zAoU%IcK^@e<?v>oS|a@)VlSiw{??4;lW9h$)|Rnp^o7Ex}fz9`}hjRTdv$MKnE
z;2)OUbMcw!nZp2o3U-_scdAO{SfO1E2KIg(dF!EN6|m^m;^N2>k2vmLXUZ9o7zG|y
z#PO!BDPE#<5|vA>Uw#YbY;r>z>0Zv~vry#`j9o&etV{t06L!z1L$=LZ3QquOU&ZnK
zMPYvHecD0(Z?S8BZn)Nf42b6bN@F239T0q~<G9t3Na-`u9~e{!cSE0@^W_j@#GM1o
z=}ZaRYF$e&h<#ukbgxoFaUfc;Af+#l@?Ka9ay^75AgPg$$?%Fz*gt^~{WMY6(YmbV
zKOYbmKviO6^Hee`^SinU7`DCjH71o+rtiBqqJAppv8?}#U4QxAe)^^M|JG{*{P9XN
zHSiDLZ9E3TP{Y5YOFZn0m?&u7CMZF1S_K#+)u+ZQHm-UIvMH|;O_#IcQZBMMW@PEb
zRE6fpus&zw>6Ko9;4dI-r_Z4+B;}kOx1e0^<u~_uK%R<_>%$*`KalqiS-#zOprb0d
z`K?n&f_Y!8ee2qo2cTB4dsmyp<Y3~UNjaBPWQLd0p3b-$buR8rxb#=IM(oUaMRS+_
zs(7CP2=)rA)Yzjfc1J>WV<gsm7xWFPDqE0Sk|8gXXGLkahgMg4LWx>H`}6X6ax|hN
zkt@V)1iv>hNYUSID?#fob2{OJxm27d7vH#bt!D701V@=M3sMAXrYktKyHqjg?1InJ
z+2&~apS);4+rjRuB83K!2OYyKYncG=14-6&o@kBO=!vR^MH=`Z-RuC10zNvnBI*jJ
z)0R1X<<VLX0bFxi0zY^l3e&vmBJ*iI9EQ&x@>#-ru{oV{RP)!UF9M!@T5`l0{G0BP
zCd>bUU!RylRvzZA?jgQXL=<GwWpNx$p2*QY?It&xSc4#i3<`E+sgQjSdQKJa$}iP#
zFPPimgcLP+pWbZ(G&jAeD6$fR30v;{L+QCrMY1?Pg{f(Cg3n)2s|+=m<5?RoFP-l8
zGCD?nwizema`VBZmIP^Amu@)6V71RURPB9@3#D?_=`!Hknt1<4Q8oT`?Rj{br^Mz)
zH{UZg#0aqDa@GF7luQt^7<%@ghwHLT3m}yy<>zy2ElMAYyNvP>*7BTR2O<R}4H<JZ
z+3dvdY;95G7C>Kr9T@mx$c+XPHbKk`H2**Cin$)f{^h|R!m&fM9UqRAxFbF|SXfhU
zW-fwq691^_J~_Bv$o|w=909lPti@AACuNly*S>Yafn?X~X=lc(YdZk>fCJ}&K;0<v
z><#aTsuPZNtQp0{IfS-RO|)vy;WK<NyVTfG1QgaTa|%UJK)74tNCNOAjqG`S$6ump
z8WI&VcurKMQUvW$wIElwhvV5DWScx8Oa(w?QDW5%@0SxQfkbP#286|mS41G8+nCUX
z5D_1cr?5#1qja2^mWZ?J<_g-l<(p@z{$fhI7xBeQ7}+trwho0dk)>XR<`jghlppI?
zxITT1vKSrHP6pHx?f5wsR#p9}?0kM<#x{H5jL4w@k=ZqA8#?eCL4IY%_qjdzxs|lC
z3_H&~doR#7vy`Uw&(u!L?^E_&SpJ58X@v#-1whzXJd+r0*@i2f`i9LxQZlGU8Qm)G
zgUq)L<~VF8wc9eFvYaMbhK&^Om_!OF-fJx%hP9wI^pqJfon@XrxXtKyk;6sXDziV%
zI*nf|wZwKKwf?+b9rD4k0&>BEOBqlzMwHUeo|e5yk}Rm!*n$<I7Zl;GGrbMl<etGV
zo^A!_GeN85C}W%pezQ7CYyslUlLKSd@-vg#V)s$0;;CW<N!Bv?<+_6gQx)GfnD-h<
z7-~59;xa~`YDX5f?W<C(zAG*`t&o$pC2lD;YRjlPJWl$(0klZ2XU#%4o%z1VU3c!I
z+Bj^9#IT1$Fr*2?(h7fzq=aB?p}wqOL{AwkcJ;)B?7>T(0S9cUsu`+kvRnM#VIPUR
zuN%AU`o|Z?p!SF@d07=8I(iUD_0@H)#X^feQYVoncRR!SeqWQA-^0;81(Kmb#9how
zpKUwkTFjwlL{?SmbYxbRv7uWjxPjf_J{~cED8m}`a%B}hDt&(M;RTIqSwXp1)#{y>
zj;jF}>z{1%$#{!#Il>9HhyYR_I@2yyKlTl@)$-XZOM{nH+Hl?s2EnW=1~=qyXAzSn
z;|<>bJJ&5?mr@p;g16ta$zjG&zELc2ZiJ)VGA0O-pXowd;EACYh1;@aM|P!q?+WfJ
zxqZc>;z%lEfX24B=e+xBEU7pXel)#%R>(~h=T|9O5Xd#+UzkHZjOF>(a5Tbi8%ipP
z>sFsAw90lgM~+Bf6!T`W)8*w^cq*CYP@5yQ1V6F|Q}YU+`p&v4JI&CBs@AM3={y3%
zqj>Az$TB~+l!}#pziU=M1#%^MzI?yiL9y>~@!l4@;;RMwm%h%Uwx2-=3isQYnq8Bo
z+uOn9xkjt}ZGti5y@?)WZP-N|)6&t1s@y(@6k%lrEI_wJXaKA-2z-v<S;~JKj!7Z=
zF%5^~?rGp)%pCW_kLhv@hUZTtK82*VH{lQ=U_FEqYlW<)ha3tBPbpql?vkku>PK!+
zzYypEd`oeWiES`@K5*;Diz!jV|JSCtE+;IWhXO_ew+b~5X}_|03IME3)l1MP%<aF>
W|Gecbc}x8WH%|<5NeO*=>Ip(ojUy}o

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..f654f580ac6cc28ce580e418f81fca1b9e0c9790
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2Cxs=otIiTAat|od*1FBWpo2Yx6NtGsm4<
zc+p=v+a;j*ZtM@Llc25M1OUO?8_@NTQSzbN@sBnFi(!lj_SHW9nV4j8dM9x;NxIXp
z;^5k9-&br5c3Y*I1a)$yt0Xu&n>ps<iE>cW5AHsW%L1b()Q8me)<L+Xu{G4%(u%qd
znW={B5R!P>4~mwQQ~c!9#|S0m$sGWTsSy;p*;;2Uk?g#x&&Bgt>djJ;k=AYE02OHk
z4MqsS>m8fGp%Rn9+6u`%E|zG)VCyI^*ySlhG~b{05iJ80@g@X$;?SOkKpv;*ZBa+1
zOQYdu$MxJ2*|ZIGQry9ICAh%_P>X6i!Z6>9Q$;jbdJ7=Eqvm%9nK&<gFapo=F)5*y
z58V-?w|A8S9(SS8#DY8rH&PT@gDd@48U<192U3OXS<P>Qt!ao|VtI?Oa2nG((HpwP
Sb!+lm$vo~rAEto7H6i)Jwx1;c

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v
new file mode 100644
index 0000000000000000000000000000000000000000..df50f3d2d8874fb86996ae09d504d86df1962578
GIT binary patch
literal 10008
zcmV+zC+FCU6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQm1izJo1Jt5<5ICdG*
zFejD+JgY#rk|&nQ`9*zj+bTzbs~Wviyv<x~VAf>e6{rqoCBQ(ch-e5y(l%c%sB72}
zM3zE{$1_d1UE7a4CrAt1^2Hvz8){<Ot7EtkfI>oW#YXE)^1Q;eV^VXp*oX>0Y%)w(
z&KlSumb+xqC@v+9r@=8tZg%N0^|wUI{lb}P#$u&UFPkpnTOgmaxT{SCzOhoT#Yne#
z^X0Fgrg1okTFc~|XTr*_p~{hTVrRgq<3(SjH2T5v?|4crJ#iK%ySik=NEJOo*mFz$
z=q>@7Ux#wH%jF$->rERjRH`;A?ya040K7yF6<A-8gVs%pB-eL6zsPCL&3X!rWk4)q
z#o&fR$z+eGf4V{Nn;yU|CDiA`EN55!=01$FZ;_YDpNvp!Ra-|1NGg!>&6~yDSZwn;
z@g(WP#9;XUAH@1CxXeTwDLL*3-x1TP%qjS>yl&Y?+G5F?A#pl(1lZ`HWTgxQtrH1=
zL=1N3PKG&1l>UWqZOeRy^`2zEoXDDws2A%>4uDE!0JK)&mM_gFSl15&(jp@%)21Yd
z+2P^%3z_pIo~0Mqu}abrygb7S;`E^BuPPMqw;q%NML8F#M7F#0O9(05cNtaEKZK{F
zzx6|&_y0Op>TLGV+;4}>4U;g+izRwL?y}oqb5bb5ITjnWH;c<(@Qu}*3aZkHX{Mtc
zQ20}m0t8}f`m|fn>}vr~ARI4sK~`*DotFt)l%t8S9-3<b%4RpV&bEm9!<DoamuL2G
zb$V>lYZ7tAKl@Ysy3eoPSauo0dzZOk<nDlk1VCEXGyf=q|NM~7t{l=OIN=4h+>F>W
zT7|6WosuVU%0f(!+INL*D(Mcck3tfkJ{uY=G7}rGrACi^g{mJcTwEftk5r|8_zm2d
zSZjWzG*PKhq>Sf)77b(jUfsh=Z@Q}XQBUm5W2dx1$BNguruap&RG)*K2LPdTn4{u#
zdyt0e9pV<qF*at9sf4BjY=TS_cYS&D*JQ<t@wDw=f-srb?TdeOe-1?GZD%47?g3eT
zj0L5q$Y?5t0eHyff^9vdqp^~*Q#bq*k=oX+r%mrZETP#M?cOzn&`|CQ4IbUu+m{ai
zWcCC}>`_yjyxuyCWf*oZrW|a}#U07zr5v&y`HA6&;P<rOQ{FrTj|a6pNXd~HXw_Jb
zFdUw?{E`Y||F*nwR$zx9VoJGksKvC(3KmjNM#!wW9`MpI6)qIW^#dU1%#m5S%sEZJ
z{;_)ZmgG2rjvxN2qy)t-u}K#7HdJ8ooZZMiJ}Y=_FXmW2X1m-%`6iAXq@mupyGJjn
z8}1I;o$@VeGYKBk-2cuCRJ1U{feL(1@!I(RSs|yf$);HV9zjFn8Rp-N+uVWrdv;~I
zLhY5nU-2s&XN)um;Wu$jOa-m1D=Y*qb&)#5U(f{`$)OJU_2W|rf)9OjVZe>L1H;3t
z(f}qSQC6-39YXKrcp`eD!v`+}O(R-#^v>25BFQI7X`|>Ag$=t(r^JEmh;Z%OGXi&5
zai}F04!|1HfUbzrSOS2tKG2Ijp|JTKo9JU;M^`e~|MTJ2c9WV=E?=bQ3LwknhbhJg
z{x9R=QbhD!h0UgtFi8*h&e*7noO`YGq(MqbMvf2wo)_P>j#RikkopcGE<|9g@$Jvd
zZ7p+D%<=g^m6BGWdqLD83C%XjZ$NtS4pjdN(`;A(np4mm^Dpr05cV$i@^{G90>UIH
zE~k!41TG}XRq|UDH^8)`ob(}w66LjhE%CP(v3rpLP`J!p4hyO#UD@05_ETcB+=cUL
z?Tfl;@YdWn2s73DDkqL6B5_>7ZbP`>I!61-N+6<r_S6X|q|oOdUZog$b-9eSUfdr9
zHs@9Wn=s8o$(yCLIlGsQW}i`?cXTN8E+pLL?uLg1ItuV9<tE0O9eK)L5efKh9%e=~
zc<12lj`V##nDF8AAfjHu4*>-*>cR?ics1`b@cSS)ec`?+dXDb$4)EwHvazrVjGnc=
zG2T`R1z-7A#}PENynNv#?DdCtrI|;}VwycP@XCJt9{?<q!t%$Gp}y63c$o;QJ*xAF
zWr@sV`^C+GlpCb8b`g3d^dZA0X&;U8*|%YD)qb1QoqE$!lLE{FjUsP2)wm`4>^~Pm
z#m+GYA$}ER9Wj1dM{Si}uosIQ1<vSbKwPopH6(j!++18Oqx2-(V>)rCuYC^+>3~hf
zF<X5J@LRmquPJC^G1Y{(+DS{w-<YF)2g3Hqp5ANcpT+f<b^zTKqt<Q!&;~L1>*8hZ
z8wtvT=K5ZODwnx&Xlx_VdFu=u+P~-lOoyGM@>=5Hbab=JJexohexL}Zh^pX*zxgm4
zUfcrAF^lkc9Q0ea?rU&#!MiAh*4DP-@WU;KshA_|VA=dg)X_0RJ_HG(@$=bzOLt_O
z8KI%-qz7_NkBI%*V0}?{7PKkH^|@dJztej$@Eielvv4XFaoKG;I@VA7oj_Pp-HSi(
zN7=ak0`H0g>_wS#%X3IH@YO=lF=cG^>w;jXOAIDaX6JHT(k^L39$zTrKdKEKKZN*N
z%-yVkyQ!swC&3fYm?ymxYPOWwCn(k}X?4ELH6?BGj0r+_oNU%?etpX`C80FdJ*9}&
z&mhoJj3UE&3}Qd`bvSQf$XE=Oc|nx`jd8huck+o^xBx*A+4v5Yw=j+X@QIGVo~jn3
z11XL+-+Adl{lb`U;IJU#&pDw&>jJ6%tp}$vJ3DxiGx`V(;j&z}v(5AKb@zp9yChQ`
z!o(>s>8-N_8HP`;DLWDNDKspa5;ZxFHmecf6sjlC*Ey;+s+I$8*gH=431=eTHO%>f
zylolHTv(Hg#)BB~pz}y~D5~QTLl&{vQJrx;qfgxdoS&F2Dq{z$khO3j+`M3rSq#N`
zdf#`%r{N^va$csY&t(v_&r#d?>~i>uu&D*R;p2tbG!XLPjHd4~?x5&|ph-gGK=Dbz
z>0J@E;UrOA2BqVF@$3|IUH}2XPdv_p3$S~3W{qpM3F)#vIT9AnH^Ql6NCio_p@~>S
zO)V+fg+Ab`$r$T1@%Otr|4p`-8o1+R?VrAH;&U-pxCV3qGhq}D`Spk;1xnbF2k{uK
zl8z2eIqhrKTY8hYRpge&nxbwhmA3>5W!ef<7J`YtbL*NLlw;gz$nI!bL#SSvuQUBQ
zDOq`YeLw3{d%DFqv;8TCjI{pVbREsb?*;l!KZlsJ5;6)F6=LLCoqB5OBj2G%cVo;7
z%c2P4m#2Bv6(3<<6UlaAI2s@X9w3G0HOmHlS>zo&59|N8dEu-}>8k#sOhOyd@}o%a
z2pJgyyP}bzPoInaKXKf)?82+#;61?u6{-<20{Xu38J0O^HXOgq3-=qMOEUqM!>X+$
zIpk{FZCy|>gCkashJG&Ad*cE}tTLjyLxmjcGO-0W$;X-WTblZPQzv^BI3Zp7yzrkR
z7xtHyby{&JY8j_iW!$>nDh9XG*Ro-2k=ur5=|o3}AW{c8<e-r*!6Eh<`*j*#W{~H%
z&8`^;DzbgUx)p8uU4=kjs0^y=<LFboF0zd2b1$UE^PDaw2V2Co%aZq|9Csa<G1%#A
zAf|}E=m3R6f5#22XOEXiZ5>oYp4GaWM}^k1g{u^n9L1d(0Dl&JtuTMK$c_pS+<8b%
zN}6kXHr%-db&r)BJaXIEEtd4qXF=pIWr6&|lSRjpBqfdb4;HZ0o@XpULMKQAw%A5S
ztt@Ck(?9HzRu~DUB~lb)Wz&4A{Bu{c#_j6W(N11oKku@&1Ok_v4caQVkTDOYk!qQm
z;P);|$s?`p%9m7kdVbADnCViBGGNvKzQ*`v$v{Xy$jTLe!qEGkdRVPoHT?O0J7~tf
z&=|R9z|>HuMn+E$gv{&SN+MFurcv&F$?Lzt5>vTifL|irpdU*sQc7boNY2a>>SmZ@
zK|N?VOt2$<*x$&4w;LuQPM&ZOySgmxhNgS{b2NcB%s_SYovFpAYHb~=@_V-OQ;*ny
z&G^U1ri7JSz$rZ0P==JaAaB%aRAPZM##|6tD9hH5b;6mW`;Z{QGXM;TW@ZyMF~wJD
zC*%~{$jc+hh;4rY5T)m{JH>7fa9^W)x5i=ff_~f$;^jLP4oUO^ZJ9w9I0D!8yj1Jk
z{Gd6z<*Y_eU~f_@Lkt!a_{&WvqFUXWPytItM*ZA_&~ngdc&}27QhQh$QnK{8n2I$h
zlY)Svsirdqy>KL{Ws*OqjRMK>s(WZEczIa-I|??kp$424R%LiaicAqY>afTjgm7*U
zqoZH%zKf(08RhErShQ8F6kW@WT{vbLzSNUVYMXW;T&R5o{e@N(@?i!|&$$a(jJ`XN
zS{9b6PYX+NT;OE6J=)p|EDVu8=GN7QgzxMcaosNxqA|mj7MtpzmU{uq2kWd7Wke)d
zUCAIYj`>(d8q$~O>Y<<)&XoB~auMxJgVdE%e!&Ux0z&?3UfrM7xH6}Xl9)nNQk#US
z^UoFfP#`G$hycplJ23}!U8e?}i%S25UMaQ~rxqx3MLE-V@>ilSt7)qE9ZWpq{qvG<
z3d{1s(=6{zEkT!hIG`R7O!9sPjC)9E$KZd6Z3T+OZWFsd`gQ2#p%1yVKu95+!p33>
zwhB0W-7B@JGvonxisrb(u}a|NN3xwp<XP<tp^H)k&E+_2mTodpiFzGdXB%TP+Nc)w
z^^1XS@6GM}1FsLCd~(uESM=Lfqld?Sy@moT`=q7=$>wB(+UBa20q%^Ld=i_qP4A!y
zv=iq^3w3~X)3sn4!DzJY{z3-gwVMY+1T@y}xY!zu6(TMO(7I2zYfNXK@6QswUh9`f
zPs?l|M^TA_yS<3aJHk9lGxiNOu5Bt?Nnqb7|9xPWEFL;{_l>pp<+tv0f^QohsS1pf
zctAxucRT94Jn5dxaxl{D7`56}K;8Q<iRdt^@=C9C?6<f+{GMq6_U}canqn$}hg$73
z((J*xNZlH>mOL67Sf>%^lOV^f>&-g+e>(Z1Z_X->Ii;?vOeXX6){SDYxQ(KzlQL$U
z-9Ar{`rw!VjR@>3$L>*bCyI8cW$a+;{og9!DfNR-EvyN+bk4fMOYWZ}lMwd7TBkk*
za*5Ab@vBoUL=(0DI=j3IDd%=7bbTWEcQ={c4;yu~igm>Lfl=j>SGe@JzD-RHxtTZx
zETBIG7xTDnZc=9wx`+-MwHB8|2K0s<vc{s)<?>-4;?PGEl4+m`8fd*3CuMBHJ6(66
zxIA#stTJu()sAQHnw^zY-eX4q5QJlCN$X9J6)1B0(UI|;S8w6J7w&}8Bzo6Rom*4O
zG@OwKD#4!<jFd;Az$8s&f<7~Vc%~(V90!K(!K~22;pzNEUCt;h&hTYC9{^2l^61ld
z$RxKnK^J#uFORl(Ggr?-uOE}P{?}$6vo^>s{~fK1nnS*D4zVh80<BzJ;Ib5T!dE_i
z(C`NUKw7lp3?|O&lxUjSngV~yk8yCpvGw8(2#bBdYS$Qa(a|)2hUiVTr^om=pJ7nU
zgG&m($56R%PI)>N^Z!;AmO<44-<{?D2~z4MbgMuuq`jEIe^50X{TDWTM7cC+LNtH{
zVP~~mY=<7_BD(4p)trR8b{z%s4LXiLKDP54lwZb(q50UKQZ}CuM<P=0El!<WPG7^%
zPWi-n`;oqlohJ(Ib`jzM{=njdfceR9H>CV}wBDG~zK8p$sIsGqJ;9x=d@vpBtUz(V
z=(}n};(9lvlznO?jLw{7XMK7a-u<rjK`|HMMqFnXVrjBwIO?#C#Mc;D#r6CHSSXAa
zQBFoq1>%yQFXZ0VWsAcp=d#T=BV5F+B1VgKY}s-x4AWe%L)`VMQo<KV$9?diV#RRQ
z5CBDE--W)KsuEV^d!Garmsv0_`Yib2!2nmDEiZqR*B2w{T28;Um|AC#ZfgUsoDE+@
z)kX2j4*(_HoM0{iJM7_@0*OSXdm8<Og+b>cH;&E7RhgoO78@tN4b+$Or=6S&W%E0D
zz$rI<E0itYbr|uk+cg}(2Zn%?&wPr05ZrS)^SQ@>pw;zHj1N~V43YzpIxvYazE1Ul
zh`k8*@!OLKcfu<`bSDZzbiFdw^i`P1Gb&(_QGX2KDOC$TTXiGw0i<aiMLJOtzFwH?
zLan3|GQ-l9_aTX8*Dp+|W?_+?ItWc__4r74-U&=lqVp?829l`_WCRVxHvrc!g6K_p
zL=QOoO?`q`n36QC_To%feu!UEP-&Otf<O&aiZO%GfM4lGIu=k3$uxQiohPzCLf;Z7
zIoK&;J`8C0X6cMFP#Sp7<A;T<WEP*4{C0#_>i+SU1F5x|itEr{^wn3`nF$_oWED2;
z;s8{HlT5#-06~96zxh<U<h0`_EFe9LXWOQf0$BHElt1^(D_;yVO{_DEeX3IdPErdf
zRaSf9e&9jeTF4U*k+~+coYxB{y+69NZCwLStkNE$-r7fp_5o6twM$daP;ocRL?;Cd
z^=s^h_ql_twhy$n`S(ErsOHn0F%!7crkMOluZ+2&PasBBGmY6T8~TeM=()>fv2InP
zQCnZ|<-lQC?HXca5dY`3&x>J}qO$L5|2M1&5b$VVwd+P!!^N&UcsJ)`(J*&2UY3OX
zxQig(wS+sP6<W9}_tw%?<h6M#Gn|!0{&!bJX@pm4Kq(J(NI%eptc4RJOr7a9wP$2B
zmGgG;7pwBDit?M1deEm=B%KWB)9)gFAyRd?_3`?5!#1^NT0vJX2rc%gxQXm)b89~z
z5CL7+fb(ei_rlnAL8I$Pt2YGu_hDnT*i}t0;w*JcgytsCeWz-bJk8)78XBMIcADOd
zgrXFUv$n*kq-Y4|f|VP9J<^((uDmj~JG!3?Q0BT9+6%Y43#w7K57wtL5iDH>9?bFJ
zxKN9RaaA}3R)zoEv;!UCgSnt*;yTf|;0E)L@#2A-#tAqsG5FP@(oU4R6t{tQ5?O8*
zrRwm05T)wYxVI3BkZ<3#O4g^eI7N{*kFBM0eL`sfH$(^Tp~5<N><F{p(2q9g8j7IP
z{%Gijp4RxW*<|SfegDJ4zE9{Yl=*7?7FoF|K`B#f4```q7S~JA-s`5@U5nL2s5!@!
z+g<d{NhIGX@nB2RLfI4QMBp%{`wkG%agE80;MxBN#xm=>H--_@DYWxeGPxm1DE<>c
z+Bc|A>G!*YySPD8Z<D8QhC?+2Z`LR=81CL7eF`M1O7Ty=K(UgyGc>$tf7Dex2_s?t
zxvyIXEU@&$-<;Mj-6b~=!+|FnoaUc_KHD&leG%u*m=zE|Pol<ZZtyPs?g&5dl(laa
zxegZm@DlGbC8ZfHtw<MjRu@t;(Q6c>zod~i)^B8ga(*tJ(Pu8}Fw>&s6xbM*Ow>5v
z@Q;Tx@vAaxA@>R6ayeMuGi{B6SH^Y6z28hL^5`vntoIt(sM99zqS{)xwW7UVWCG&F
z49<Oy8IeeGinLZAhwsT&jdsm}EgKXVj^4hJ4U-~p2#gOG&gQR4CRJ544g}lX){+Vx
z0(9XE??x?9{!y-lynW1gX62Hb#Ft%gxSH+4(H8@x|KS3wmtvD#%16=(*_wj@*o-DU
zz6luW)7^6^i2%a^-D(*D-$|TCGJ~F2tgR@h<>`8ylcB8SVu|hs04YzGdzl+;;{kv)
zj#(*je2gj=bC0kIPhi%7sV3-YPwinEsH>UJ)2;t3fc!Q)aX7g$W90ZGQv`+~N(3BC
zTi>!fMU%Q#sbXD>x%VXx_8;o)3ROH2!dP)+q~C0xJZWc5131finFopjhV4$w4#hFs
z>M7GB`E(a=EZ+87R{r$mX*|`$rTXV#Q2zM-Y=IH0YQhR0b``jbs1!N_Z%sYJ`%sKo
zloE4P$>2#Hc)<NpGIg6oXV{KAd<!NPH=%QG59QPJ;Kb!v;EFfY?y1};K0{Rlg#f^E
z1VT2!z7N<jZ*)QRortJ>pX(7vMwdPQUWXp5(bvCW6NVpWKC;XkI2QR8CFicfXK;GV
z?tG3MT#g%Ya^Qv--q#6CQZjAYJK@nOKfQEe1=bs;2b^v<`h?|g=;hfFSBP#$j40%V
z*i9pUV<9H%1@&f~{I_Mn*yK#g%HBx4sd)odvj~Zg!g=uT-B`-Wc(7&n16(Qi3uF;`
z3KX!gC}36E&FzVcOf%kYzu0vJHWW+q!jU3BK-vQ>#3Bp0>L)oH^SY++{M6esQWx9v
zSqe$wB}hisRbm)j$2{5dyxZhg%NLy~E0TD8W=-YA8Or7uva6o{Z2}EsJ|)uM9uSFh
z8u`dPT^g8|X;51bIy>IBOVrxaKXxiYu(?a{jM6F}-n$xviawsfK>+fkg|Dwx>1h}P
z>`nKb0@7V^EG#tMQq|A6IoTMOytS)6yb(%-U+b*|FRi-0k~*ee9>`2M!*-sf4O<y}
z9*`|v%UgX9|Exi0ELD_=sKwV1jo`^az?<xs0rLi{TCz)j_KS$lro`5a&##q`ol<zz
zC`twB{eC8+cu=VY`?j9!>;f}&Yb6`(*+w9|v*s9Z&029try|kbG6$Y&L|j%${`;Fh
zSKIS=wX@xzN7YD3kz0%78j~}lT@JK=t%tCDT3X_nH0Io7?@F{Az0j1>5k4|O!C8OO
zSLN&<oN{fBOEX!czU_srW0=J>=xHJLgnp)?$PW{I0jW~^AT)nmC#XY+A*;0rSs5?c
zID$jnMryKQx-!EkA-bPSR=Y1Hv4+&26OFHhAD%6LHH}n%C^*5$HDxvSrBSqz>=J_#
z!kE$dlRllUC7~)FkkWRkCTnc4e{YOVJG4WjyAH$+OichkQp4q{WBn7n`?e3P?N!_Q
zfxx`ZvdW-s|GV47X$W$oxcE0{#Cw&6R21;#i=!ij!C5(;sbXsqen$*%R)T@Bg}Ebf
zA_cA;(_VGLj@w_cYJh4+cu#ctAG`f8&?2`<Yi%;V23X+Qo`63!hRysBi71=b-P_iQ
zDkeXDb_=|e1KN1z1Ihd#lresnSretA<yadKF1{<fDoy?5d50a%=bhxFon(Y8ci?3m
z|NrS^K05QPA2SnAuvg=h#xvvIhYnsmPAJWsS|AS>pIe!=*GDz7-;){<VKihmE*4gY
zf|k|FKm65{dK8d!EKBGFgLi*|C*fi6E9v?aPGh_DDbVqtZ|Av3YVL5g1oiPS%hDqV
z(>yM;32v#X;xFCQMH7)!wMdLtxy5|Hh-{5)+<?wp;iX0Tg(Gn0_MWje3>k4$#b#6R
z@CMik0M_lN4*+0lSO`Z^K-8wfRT&1@F#amy@<q>OUpAf)C~>rZI$P3Rfwt4+=K|$l
zbBl2)uOQpAJkh7%H<2@k3)9YpS@wT!8gTV;07H8?;ut|!e(DsKtA3Q0W7yuVtBrh=
z>6D}v6Z#a`sd~NBZMK_Xv|;kPVcm@xIY<+XCmYF3Z`_!}(ttst?KJe85ST7xj4ht!
zt>kLE!ae%9ZtT_oBBB{=^3k!;)UT|52u6WZ;>^WZh48Kc{*%uZ?S3r~i;l6cZX^9|
zMd?!=J(b6Srl^pnHf(7}RYD5}6#0;ugQRYDG&|i#0$uy_#1zt{Mc(F5Rexs(dqvpD
zbIMCjs8OR+sj+Yj1!DIV4uNt-F1THV!<?J-9ZL2+yRT3uZ3m8u+aF^}Q=fPK$o>dA
zMA&3I^!wKYiq$PpUMs!rWI^qd)F;e45#YwiMI1uXVsc%1oqk-(9M=!bnd$Qc8ZaLu
zt80?1|D4H2hs{@*^`x#$)9$q??Snqt{TSW`e=?D)sLe);U$>O*luRfEb}F_h&P8q+
z?aQ@Hx3|1N46SjvpA^~ll#VQx%4H3?>;s>g%&A;KQZA{5?MoJ%l`d<ViI5z6k3V3*
zl{vCi{B)&Z<~KEm@jV#ZQrjT}Zu5fmOr&OzSgR_FbVEXiwN(&}Rg<*xG-_#Pd#dNF
zO1xztBsZE^cFUJ=g#t607qYk|UjC7Gt~^DU&DwA@ipqc10%Up>*s!pn00w90iU4!M
zDgO^Fs9)hJtzh9I@KN3Wmp?nV`n<pqZv84(*k*z0?PyZcwA@vx2Gxy^I$?QZTO-~X
z;<6?)q2ESSyO-wUfZ$aWWgueE^u+>^2m!6b$MOjA)tJ#cRHw1N1dQwkTI%+|0Ne$B
zd6rnIC(6^Ff9<mZire!DWleCs#0OD`8=MProkuH98#0o>4nMOJOx2K<?4mhKA)yS1
zT?y215p4$`;3+{jL1zavT5W6}M6>%CThbwYSHA#IV&U0Dq)b8!s_`vtICfYUkYdMC
z=A~^UaCOYn#26TLcGhw}0OVjvWxBeBFPZ8Mq#YqVvd)C-+~z9n{iVcXQgsCHVF{>g
z^~X?Y%q~6jv>`2nI50E5&;)qlzf62ciF3x5YJ_%6W3KE=zvh&i3Wi0Q*11k(!v#5f
z1>}YAX6s*jOaKw2ejX+L81D;q%Iqvjq7P5)+L$rqG_tm!0KbiB(Zsj;6FgkE%0c;c
zvf*Hhmat~Z1sanEJ(T(I=-42P4zop*y5%#-4cnfjFA4pjY5(|21^0w1x!_H#iHU6a
z_!X`ydr*9A^1>SlM%2XfwN^xbd|wa4Dh2bcM-)5$Qx}8WU_GPGxcml8U%?rvh)B9;
zS;oC=I-IJFMArawuV`AAn(h@1&psPfC4k9NmV}M;KSWK|kl<y-JtH^!1E{^ikWp7M
zqdUSq*8wA-H_ukXrUKH(-(wIAz=#czOxGgs<ja!DO1OM{0A2R<ShY4)R5$C2=gr6V
z*6p-X)xN2eXO>f0%!`yGq&A7HD}_Q&D>$}0FfN{ZCA<~|E9H|N?Jh~6&YGDJ#FM9>
zP{E2r?wqzB=&ZBG{$`#{aV25QfU@y9J;8gb30|KTV_R07F%3m^m4x!j>5&C%=fw3m
z!22{dMw@pRjBSu)*$)G-K1-1?$i`8V#2elu`zF|TN`Kg8rwK!>ONr+1sxXIc3tE-A
z58}Kpe2pGXG2=E-_O`!|WYBQe!CtY!A#BI|F8w|Pi<G@@^~szD_9_$)nKR%zXg;KA
zj>DcL>KTHzk-TH9Bvh(2>!?N^!wzEPZh`M}@zrw8diP0lmem@Y2?e7jkF@b&E(?-}
zL4wtXJ`CYrHVP2gf>`^sFkXYuby3#@W7Bj{FCpGX&W6AL<(@abW3{63!m(RW!^prO
z2Dl4Z0~UHXX4qU;_k|HP5?Nez$;zqA&B^=3EJOje+LVo*h;d4tV*%?18R&@ui0BLl
zS9|4BKWUY+9-7^`)49sfJCDW8NJe5}zAu$dGKw;JS0f@Bbua-jpw)91i-OWJ@H7>H
z)P%|Zm<)#<c|95bINh?yO8Jr4gAXE!cC6(sgI3BR0=R_5BX%}!dz4UcZFs*p-`7!;
zD_K}1ms{wlAaLSIeK;DF$N-T<=kl$ad;C*`Mnc`^>{PUYCj4R$nduKM-O?h4Vy%>*
zV>B#5RHFJXEGzH7`$Rm8n=L61;`Q-8Kj(Ue(FVCEaQbg>2CBGPk0&KXge5s_H(67B
ze8``N__V%1wWcnRZbXL5=?BP9fkKroF?%c!pe%#Jppg9^UJ8EABgkJ4Kaam=uE?rm
zY%sD;Kf^-@Y*H7CceHu$n?T22^Ue#m<c1$1+5}(wv+k1MY~mM}TTq&LDAF*lpE#j`
zl}=~?rWedwx8r+2=fx2<nDIn0m>s<@Yf1R4MD8`db>2~x{Q=?PvhqYkh3>X3i}hk(
zm`0%s`zhl6nCu?!IGiaaKn*h`3-+x|<WVhMIYN%%FXigUbMN*=dr?IqyK{S5hA!xi
zvx4VGk9%P7W;t!dh&q?pzq0%3oZ%{+lv)_h#rf<uo99hqt)?=bs{FvlfWJ*;VA6AJ
z8YMZNxz~`Q42S{PM7^R<YBk$;oVC-SV6<yV6_$;e3)rzwy3W%uQ~=~SgAw2FE!CzG
i-T-`L<94uFn6Pgid{6+J+uT39mc&1^qH0$W07~0zad~9`

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..dbbf1a0e6559a69c9c7282e033d8e66685f6d771
GIT binary patch
literal 1360
zcmV-W1+V&x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gzJJLjGOE9!13Re%v%qP?%8&T=t?2CwpN1(XyvqP>+r|9cE1MVxwh`3mWr^vT!
zzUzFoLwRD8HzAu8x9~qY`-0=16!sb4pqys^p0fl`MvDz^#uU&OwyrM$S`lIrx`G+@
z*g0cq;Iu6we<gATS_ZYO)Q*<Z$usbXYckZ4nRtDrs8cvqO*e_Cx#QOc`~Uweo1C|b
zfPbl3HyiV@rUhfI^4Mq=#SV=S-bjeyDM0&-8)nVVm-ra?!-xll#&tRH9`hgtzhHI;
zyBis=c3qGpFhE=$N}PJXe8A}NS4qnVpkwEQ=w*PK5cLR0ON+@Wkbh<jfjqPw_lp%;
zm1<NihE*}D;A7u67vKP^iK1HxW$||dX*W7zX!=S_K90*APwl9V237?pyc%436C)x3
zy!5n2HO~`fa2{J<i<~f8E}z{1L9LDJ=1W=-qTL0Zn;%{mI8pN2CEOOy_k&koTPzh2
S2MuM<oL3yeJ6QsSD*32;V3ZjE

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..6013a28d029cc25c401fec47adf3d524073cfadf
GIT binary patch
literal 2704
zcmV;B3UBp`6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IUTtageo
zL&~gk>}rq3*nGHw6(<xSA1RY=95S339SQ1!fKy%A>J4|Gg~-$corzFz3837dmPybc
z&KZnI6$D~hNd=vxVY|`eigQXf-!!cjdO?a<m7eNVyHsM0<EMUtqA{GM#s#;Gwn2Dc
zhNof5THqfBG@nTe5oKI}HJ7rYoLzRI?E5<|sN5D!xv^&_Q49cYEZ%jilSG04AI*Hu
zM79?f(38N~B~xkef)_iY0l)hxQXxH`$kd9Fx9+sgJ)4W_j9n}uF5nOkAz1*%{rZ9F
z+%M`~iBXxnUVN>$52mGY4?F!%d9CvJq&0liD-;JiFtZPDV3PGiKi0YXgf-8|Eyp}H
zqitB>rl;E3N1>W^Jcz{J(p-SAPnt+9Vt;7(#lD`k2pVG$!035z%~ldl^fgz2vny(E
z8hXJa{Qun+Z1F17ykKlkr>TCf=`<@0^{D!rF4xDmvgbpDGFh$cF^qhKP5$Zw#Uhtl
zi~*9t*VXcNy?rC3s?_xM!h-t*4f`I9&G2pogQ@dWuj@)SmdBKZK=*OBy|S_r?Vra)
z8#uUmi^Sc20^;Pi+z`_&A$B~TUkn7WnYX^JHvbOobUz7h`GTJa>!%a11Kupo9V~Zj
z2lpFw@r61PR=f#6{IKyc*fvK~Poupm`8XK<Wl`6Z)YjvYiqI+Mefz-I9y{P0#yDO(
ztwU+%5t)dHYixfAUkF6ztfY1_$i9q9mXi<N=RmZnRwqf2vggPL)xoGxjU}@=@CRO|
z3M$iWehcE_>F=st*!7@x)B&wh*-&F-^PL2zY36m*ucCZR$6j_30&?_@odUlLQs04(
zt?IK`p3wj+{Eg%0wzdZz8au85gd!cP%o4n}vZ+XP19yW>0Jr6``PA^OM_erebTFJ=
zdI#)&klu%gdG89s|MIKu!uL41Uh3WCnp5CKZl&PVhb)Fq6K<=#k&<b5wxWgya2;M&
zeY&~p6EwzGY3<iJi&8aM8!(mKZ?<vWg|!qbWHw8yXH@RazP!*l?3WoSemML@PdK2B
zmRd1<*Ce9bo_%eN2BH$K@TPjDT25%@f>5pBx(G2`)*7sjYfv}c^=O2fFVBJVXBi-`
zd<VQRl&i%ymQ=%0<L{ToPz_ss2}w!De2`Hcfrg*(<8U^uFGLQKL)m4<IMqnmdWm;K
z9_Zl0G5Zztlk@GB8H=dn)BXHX)*Jm?epOa)OuUv<lbqLG9)_h%)vC-s256V``89X`
zQN#6NX3y*njQpq_W>V7ejWq^rLCP56+l%&Vwkv605<R4;jEOQApW<#9BVAw50b5i0
zot9Cg`cf9`_Bm6NCIQJRmZ);v`ee@Q<Yw~h{JilLL3@RLHgdL&HO!yXM@jFo3F*zI
zoJf^a4x1f>CZwQxL`@0(NwTlm{aDMo6<dd^qLn{B?)4@TgF$QIOncTR?S2K{V*)Ip
zLQxEKQWvfu<Z)UZH@bGHm+0#oB=N_R%+fFmZ~Pvp0FK%}-rxLAG=e;|cA@avO5eSL
z6s|pD_gW>(8h@6VQEj2zb2cx%+cvBxySA&B%$HyKp2dD)szBl0{pV0j{Iu~zMHIYj
zMOu&o0R@`n7{EeTaC!@xkQT106_!)Y2lO^EkszTqkaNFJ<bX1?#jmD9@?@Qx7R4(b
z_7}1uFF1~7C=%(~8Iyh4g)_j(_iSEL{@u4N8-jHY7@xSM6gTtWLoeB*r&fh7r!>6h
z@Gl$XQmFEaJz>wW2BXdMM6+rS=z_sRz>vCS=z)S3X6Sa&LEInw$z^#SOv#cPq+d8S
z9FHN2_L;o%V45Ju@CdlI5>xvQ{y#&g+Uy8V+`V9^Wr?oQV7Lzc@vbrXFkU=*W)9rT
zz?F!N7Dxw{=h$a{e%n*HZ^z>1rWKpJHr$mACMh2XMyhL~do=+iyh(~$3wAJImR)aB
z6hUMB299`pj*E9|Q!!&LsGe9O#M3LR(e30GnlmAv7y|o7p${VQOLQ9>I&HkxyMj2e
zcgRFp0Wq`+6K4llm$<t%klY$7cA%I~|3K?Tws}I6C<&eK$%GS6tdqd>0|B22-)eV!
zz*r8v=ZBmU6Gi_mI7p$=T{KI8{e7dR{NCPEDj8wm{rI&cWXuf{Wr;)OYLn1W+pggX
zTKMQUTA`V;8GmX9u=_BO*UTNH$b?vcvN8U}-aYzVWLboa+9`sZJ5m+Lcp~s`TCIxg
zn<3$g3DX)@`d*U;tMF8S7F3&X(bT3~=<SOL>H&O}6`_swvUGkryS{!&nyNnng2qJX
KROJlmz`l6AmPm~N

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_false_path_marker.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_false_path_marker.v
new file mode 100644
index 0000000..601a558
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_false_path_marker.v
@@ -0,0 +1,66 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+// 
+// -----------------------------------------------
+// False path marker module
+// This module creates a level of flops for the 
+// targetted clock, and cut the timing path to the
+// flops using embedded SDC constraint
+//
+// Only use this module to clock cross the path
+// that is being clock crossed properly by correct
+// concept.
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_false_path_marker 
+#(
+   parameter MARKER_WIDTH = 1
+)
+(
+   input    reset,
+   input    clk,
+   input    [MARKER_WIDTH - 1 : 0] data_in,
+   output   [MARKER_WIDTH - 1 : 0] data_out
+);
+
+(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
+
+
+assign data_out = data_out_reg;
+
+always @(posedge clk or posedge reset) 
+begin
+   if (reset)
+   begin
+      data_out_reg <= {MARKER_WIDTH{1'b0}};
+   end
+   else
+   begin
+      data_out_reg <= data_in;
+   end
+end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..7693f7a10694239df995e070804a5161a99c84c8
GIT binary patch
literal 129336
zcmV(jK=!|j6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC9J9fNj3)!R|;7yfw
zLqk)a(aM7!j;$y7T-r%6g<+hDfNiSyEz9EWt-{q5aqJsFw^x6)!Pf88ZV$d>Qpo?f
zCQA~gR8<1Wq@7+2f34v`k(&#$<e|pR+Z9ano}<2IrGc|$)5nTu!-Et80PGZ2lyLw~
zZfHt_bw#>ZonwReDH&RGGLe5TCASmhYK_)c`op{+)J_Xp&xw~xdZ>b>1`M{)jO7ue
zGD1l3oHVQ>8P$DHPfRyu_VF5gdd*GQl|^aE6-~UR7iZ80R(JG)(umUuaB1P0R!8`k
zz|4Zir(rT}MiRHhCl!*9^`7nCG2YfpRn={|%-xI?v>@Z_x53-eC1JHw3l#HcA=jyv
zUrwaOiu&zWp}*~LsNa@g<!;Y?G|qCX3WWezTrJ8T6w?l<6CRPRj^Our#yWuWe!pcD
zRsW($>#iLC1~yf%(bjqypiid7GhtWb!AtU^<IC5XOm={#5<`eGDL>L~P%kDexV9j~
zZ=i_H?`YL^>wD3?mS_O~2-x}|%br65g3DOJy6(84#9r1~75s7eOLM5aNioRQPbjNB
zR;ET>TrP-NueidNOvvGo);!X%e%mVJ07GH6HyF7te+rq=Mznwlg%p<2vkd~mVo1`u
z{9nrap`27FYatzhC&lo?3bOQoRFwQt8MZaxwLqeb6(EejpOBgv7G;G)#gk+x!1YL{
zRQ|vcnyNBXC9l_G(T{DTIM(uP=fX-SQgq&Gxr-xL_iFaJ#-ge-eh~K;16L8kxH#wG
zw?!l4GkE7S9H6L~d0;K&QSV~i_yZYq<0nuYAX$tGXP)TdKg+n2RB;_6o4>|hwdCYT
zD+&U-zaoIEx{hNKzW@4on)^v$9zwc)-;e_ABiB44|5+%0f+GJcf}lsy1>09J?M_0s
zMKTIE%aJvsV=Hr3E6U!;KxXHdv`Y8%r*t-@*%WH!f9O}QM<_2PWCHuVA2iw}cj?~=
z+_@MJYl{Ef9^C+%rfFMpbUJoAF7f4Y=wi(lvRp1SvoXsuL)ULZ2{{<Gz;LR^gCVzl
zJD%oRv=NA62Bg5Mt9YJ|X!guggox0(-w1!}4$9i<%<~)hDPLx<ThRcW!}_vsk6d&t
z#*n6R!mr*6_&oTvwcb6|@qAlQb&#d!(S?cACeN=0dbq0b6SjAz<Yn&a^@(hVtIu}7
zE%b;~ZyB=&jT8G&^}(H6ZRM`wjipb&sol)WLB}wTVM)QaOXr|%>^uB*N1a2FJuK-!
z8^|7uW$LBKaCeM($NxYC#xGu8fLjiB1HvmrUTR!rgrSPv@vwEur)e`@F#+AAqyJVc
z4LRWo1vpQntS`H&L%rhoyUEx+r_(K{&AkhJL#EWgcs})+ypUVx`rGh9-<^ePGU5MS
zRUv(#T}Ft8U9KV_XN0*Y2%F6uR)BMG-08NA<k&KkBXAzWOu$V_w}^Yj=@q*fv-X`l
z5(=|E%_?9F#Vf-4qJJ;=oLR#Ce-m_q5(K7Y1gcN6L8>O@oY(bKLo?RM$pAoTV=ZZ2
z6zBkZYKAor`sc)Hw&77Wk>wG?zbm0Un0VsMdpq1c9Q#S+KU3Y#eFNGqJg_*EuPRdX
z5H`&=u)2HzR70)WTQ!)iM(5>4=C&?uyJPaZ907cAm2TMIR@j3$0yqU@E|sq)*B0Ri
zHgi?abROkB23?{Q1B~<ix}M7o;5qGi-=Kxoa@Pgz@U-v$8l2CD+Q<^rrbpqpy_Mn+
zrZINWEpNftx|5GaZ*a^kOc`9QK9Q$LK?s=-1%h>U2Tm-Z>hVnz`2qSZ?{7i7cuakS
zg)(KJd%$TOTN+c1CRj(a$n&JP{HbumU}aEpYSLdU)^Yc1R>xuXVl5nI0%`l+bT{28
zwL^O7pIIAW_=^-*8zZUUza6%ryTxjaCr-p{>}}hvX*^_cs`NapzulM_QM2vC$&&hl
z%Hi2PetIt9xyWrM+MLV>Q%bY5BZT5aBtNP?ij^RTU<!uE0Z7uh&kzk&%iAP+Eb~?B
zRY)rxopL)rKNZUP)FCm}%AR{nrJWH0y7+^pFgJ^4IPIdi{g2(-Wi;daFMaPpi7&&a
ztre77_=M(vXPw7cY>G-=5-FtC{b4CjoBm!(#!+@ZiZMU%0bO8F0C7vS2qZoz*BjW*
zRxm-n*FPx<L2AtGH7kgTRK&c<6oY&nT<iEz58a!J#%e;R5OY8;C?3}AI_7&cAM1n^
zw;o`oZY5P}<`==UBLt7n7T96++a>d<k8hDD&PPvSH(A%>JCFrE)_B=FX{aVrIOEQZ
z4-DO;L3$ZVrvv#FvBpkWt*yeS;4=emp&%#ibavHJ6~SV-VQ4aGKa!}DjE*3%UQhle
zl~4m3{Sd}(Q*c8x3UG_jtH$5`VLaPo5BGT3(I-@)g^k%T4Z&%1yC#&1<?r$p+aQR>
z^DE?!a&o3*lRJ88$6w$_6%KPPp5QHOa-ZmWGcAA^rMJf%_X%6RiXK$ECKVr@8waxx
zJ2ZytTriS&>;Z^ifCrM_D9$IK?f~qPES8d*i45(Cfz+9gGPY@^hA^-9K>heWHOivJ
zQFoh69$($PeU0<CdS#%)<Mcc5FcfHyx^A1bju6^7rJ^$MSFzx*IF27cZ<A)47Vw!n
zdKT{R1mG1@58Xif$ctdBwe}HWtc0PL3irX!3)&&Yr?3jtB7hTpA!5=q`nvk8teg37
zU5Ci27o#=pf`a4`u>fg|p)6tH!hq><0!w3vGPN$ZNkQ0(^h^iv$1#@Q;8}~=>*UPY
z#Mria;@RgkMr83qYle5HWc6B4Kx!N9hqxTmoJL=dejIeE7(8)CbfE0gANf~EI0>w8
zR|+g)UTiU;Yi$bq|3Ho=7(~c;m96d=<+O4?-nGHFv-Jz081vDeremC_tEZEzdR%DD
zH{`RiX#Er7o>QEyb7LW5g>-8_gc?OZG}_g&zr;Jk6)A?NJ<yZ`cSxg#vI`#mg_EKx
z>mIn352EEGzK<RP8G{~N2LK+-yvo>Xp8=1u7wz+UR%c|jEU0pJBpE(O$Liox>D)SS
z3;+V-U{XL)bs9PI1+Bihm6~VejdToFB`>V}mL*NioVq+Z`O+tLc1R+OtdgMs7KNEW
znq|+cVLe!G)a~h34+kC<){e;$@e5rr8VTf>RE@*WqxvtRV&Il9;N<uu-(e>?@j|1*
z--pky@8Fk;PSE6T<-lDnfx9A`JP^YM<d{O{1gKuO0pAOT@YGf82>}e{0nWhFe{=z&
zv#Ye~C4N>%9sAHznWJoCybe|LTe=8p<RLp`<_ty!iEiDvvW~j?Q<Ugp^ni|$U6yu1
zGbSh`cX9$z1q7ITjBu@3TFasdWcIRHxj^Jk11+PK!7S<iSK_xKCMz{*4W1FRSU1Of
z3#MXqy6bp3T0YNYP0pIGiC{pB;3kP0K)xwPc>DjjESye0#J6wT?Dl>(LS;Tkx*L<f
zVTWe9&;942&v=G6?FYc16aSo$)3FT2;>BK%cAQ*x#lHXgK0LwicaV6%2xlhY6{hfy
z;6oj+y@dzLU)Uw}?<oYg!X-=5|9?<7)R~q{yLplpomo`maW)@$pUT3=uFy<^Ek=S)
zcVyRVqsxJCOwvGKjp?4Diq?Oi_gMqXbe7=W6Jbi%^w_(&#F)=ferq{{7}5bf+@YBt
zxcafP5JADLv7#sPYP42Soz{hQPMpetGU7RCD2%XYjBD--6+jD0gn_Y`$INBLlP0m(
zjIjgmu}V3NK@*Mg=L{Wkwtdd~l7<w}bEP}a@IA7L=3S#Zmam|SSN&<YNA-PnCO00)
zBjd>55SQ!S0+h02e&{Jj|E~eHKO00ia8?;K#O$NEeteL(`gvT0s2i|5cSCWLFrR>o
z*kr%Ih$lp^Q^{5{>WI#oyBXTdFN~*{vP3n?dRlsr;m*)VB$$^u0OsS`fbNll?ANS(
zUKXWcBr)@nY?4F!ijb$P?mY6_wg6Sc=by)sF}CX<DYKZKlw&jxOItK0eFBXGD9{@{
zcgtU;O*``>Z@ydmaiFo-PVg=u0G}fvjUf%dZEN!$odn$C?tw@Y96ZWUIZfTaXq(~Z
z?#a~gef;X$$vQXqWhln+wQ=C<gbS6ju3}iA%dRIstJkExmR><|U+PnuhRL(cGO2dJ
zseTTuq;tksAd*(?%F}D45P?hkb<D{rfKjF*!;fT5tV|F0{_dLBkN`~gO>DST&FcX7
zx;?L`SeN7}@NZJxk4Ih+{&(-lTgg{T^_XSvsIE`fTcLcv<B?h62yZ3U18xyHJD)~z
z`;sI7$_MuM{oEIAm=sBTWlQ2N{0Zcj(tg{1Z-0!D5>KO|@p>^(mJFqY@CU<3=}$*2
zaLl`~vWG<iC$9r^eqo;&bnl%ne7qz<@zx%?pHA#sftJpN0&$1{(roqLy?Ba?3ujQ^
zrFzr`iPpCYooBL%LTD3U*JI%p5zLJ8tMUtspC1%Yf9nB4az7J8k$P5FP$_ZHGflz+
zUbWVGVy@_OpL_E)DuX*2uD&>EHsX)YzqvO8yEMg;0>y?ZE=~n%uuFHL5UM|LP3i`#
zm~|Ezsz3$yh?VUEHGSJKu(L51iUHh@^C3?`5&`FsLUrsbR6VJNODqVjT{nrWty4#j
zVkn4C*c2K8cn=RH{ua=P{1ze)o1q@6h>Xv8vbI^WKc>ZV@GP>8e(A1iJlxA2as1qw
z7TfcKQo3RARq8L|@pAiK%IjmmkD85al91_Dr;b*tN%l>p?|~`50&_3t(FeH`ChckH
zLlZC37pO*r>WIyw#vt?}5-ey2NMR=59*+gkEEw>g|BoLdeIZ~evx*}~J){}YRm=FQ
z<v%N>i2$=Dw9lFeU$Tl*rpag-(`KKk2_0j?jpKH`DMEOTxM9Q}Zl#l=AyiIB?YoG_
zm3eagIm!-|%w{Oc<8s@=yk<Z9Dje?d3$sb*${Z5Satok1s5XoxZ3`dMi;6x6mT#B%
z*rhE4%v-{oazQv>Py7Xy(NK;2utr8FP7>wM7oa$y;yBbdaWHB{@V>mV>L3Nrb-Jj;
zLo`Sl9w4=?I#<&cZuexS21B%jMjR%)g@~VN50v<CF<UWab)QKMppO5kq}hnyj`ERB
z)R<Pvbd}Mq$MCTuqE0G=0kf~7ltKMxTk*?2j|T%!nM!yM=k&QFyOJqe#n3FB@s>e<
zFk}})@@JMjcKHC=JFqC6RC>9GsO&Mn;^Y?cUtL{03w=gQWI=c7sHu7pQmOAIZO`Eg
z%uuqfSOCwL;18Oqvv(12`%+H5uz9TAIawHSiGZZOxI5+|XnBB*+UczEHBqD9JInK~
z@h3M0BuO*aey9LbnXW9U-U<y@3+FDcka$y<Y%u<anjc6bR?_FuUvo8DPdbK8U<ty`
zu_(8J7v}v<#)#){kDw>PBJqYR@qm7Xq`SRiVO5qGhqkKCl~ScJYEM|K8rIN|S1AbI
ze2H_^!h;OC?=9nAnWE3jZj&^!cnDmG>^+lOmfxY0b`sgg-d!iO3a$2sI8y5VfsjL3
zHffsf*9f(JPF=!%)-S2;GaUQt`k>`Aco7dM1rHiE$n~fWFpL5ZD`D%RvVdFpH2;vu
z<&M?*AU`e>CaYWZS!<iiVU&@uH;hvK9B1zpkaaZWyLeB{-}pNu)!KK*?UP6dqX8&F
zW{-drnn<L1PLBtRbWIK$^v;lDxkxP<CbWZ8tm&HH0hjE=q0?UsEo)SzcOEM3HMbuM
zA5@C>0&ZzFWFE$5fR`-^(e-@EbyE)Ig0V(>ulvI7yj)Px*v3Tv3^W}g@6s^%N$E0l
zNeg&@G}uMC@Aw+@>F+6WVv;y~l4q#$m$(5J2{H;JC!3J^RxZAs#V?pru_s0j+5dYU
zVU%sl9H52QN~pCPDt1xZ@AbZqLD1VAC^urggdonoas;6)sh9G}s4J3Uv*nt0D0YjL
zbo>|9_V1ifk|T&$e2r(W{2F)G;ATtGk*ym2q`R6%Z8R-O9K7KbDoTL8pU)86l=dm?
z&?L;%b%k68@~ZZXbB3UDX-N%B@lE*>Yq$vgNSS|#3u&X(t0Ot?8f&$r69L8_|FlmM
z-Z=`n2Y(-7jDs*RK%F9Qydk74WNx^cbKU0T?a))6^1eYXMS(iz!fZvdj)1Ga$~sXG
zy!M)dS}=aDs(6vR#nZu%oQ#w9D{b0Gn5y$EU@GE3hU+(>38PTf83%<W%s2s<1B#SZ
zB|mwl)lCi-@HX>YW&un!5;a7R+r9*Euksd?0Opj4k%-J;=w|jn@OsA_sVYWuE19QH
z>rsI3#)n5`FX;t<&?UCPjUG;joRw2>tPWR#nBd@R6w))g1G>OigS_@2L~kNF>g+xN
z1ur7M9XMq<V{&Ot8OWM@jsX}oLgHS#9Q~v^V4AFH=t^v#^Hd)Ht3yphVoZ-rLbiKu
zO(d=onuhjjQXr4V^zK!&VvN{mi2AfOfz<@wBq|FLJ?WY-T;Q{NT#syl%_NbA_yN-&
z9}vt;ramj-Tcc4b_F-4Qq*<V=q@3L2Uavm@#Cb810sZOl!%)hAFmhS~tratiVsH;6
z4xR;0;nYGE7(O$#;QJ&s%lPg;;hhK#T5IrR0vpQH{q@~vodo}Iv4DIBydhuZC?5t=
z#A*~9o&??}VL2VmcM|0`03C~p>G`>^;V_Y>tRl}hpeo)C8HLM4^XA5NB1A7~fK1%!
z<6y7%q?X^b&LEnoM=keGu1i^2L5C=b8$>PUYmsrZyiu%?b(aO$4A)l7>2VRfj!LMK
zh;e_37lX9M7i5+ASQLDz(D@pAV7k+pc~_Cs{d2s&!}1U4a|Xa5VJU@#cFM9lBlzKP
zO<FuAoNpX0`Zqjx=OB8u@f+n_euRUJiM&_3=Mlhri^ug_?=FUcm>O~>Xlr9&`o{%T
zMf{IiW>jbD&kZW^$m)@Xl7uzdCaIfiTQQAV4|}2JNUJyd!e_$(e}-x=rw}#VGIBj!
zT*xok=x@{TXqa6V;mgKa>a^LNO0H3MIYe;!DK_y-sb9liKoK!Wwl5;m9LoRi_66yB
zJL>VY+ouQQtkkQ$yRe(<j5YWJbksBzRR)84=@?2svjMALx!U(*^5Z2me;jfjoNDnp
z*Di)wEo*XxTf`d6qJByM&R6(w;3m~sdM~!u^+CPfG1p9~wK)Q2Fk#-K|3Mlc|40sJ
z^Cz%_fm+bhBgdmYi^3tR(YPnT+EFDSVD)<SZ=b>LQWVk=*{{ZtOzL=hb8Gib{?zKh
z%UW(d@<QrtBvPvr$0D21qV?<p&~c*-Cd&V;{f`iq$WnSKcA%nFhow$xYsRpsWW&Hf
z6u$}q-UbGv*hf$q(QP-Y-W+X<AO}%nc}Z$TyZVl1nMYjI+M~IB^w!_~fB7eYUj7H0
zC>mom*E0wZ!pnp@`O~43R<lM>8TT68$8ZCD4^})Vm8Dt_Tn9o>=;-<Y%pL-FvZ5!9
zhQivo9+}`^v}Bq)AdGTsi@`CdJ#W1q4o*>x{2OlJ4kF7IqnDc=y5c#4D;%wlyySrv
z4k#1;fgR0oGeZa&A`m~z02oYf(T2enl}dRNrA|08Tow;Y^sbwAL#x<;34=c@s_lr9
zL+yqnvm7?}miCvpl(_I(?v+WP*hLUsB_4YdePo?0+z=f6xSc@B8|9;?`h?YpC^o~-
zdoHc0J^>ZHh0A4XZ?gD}-vKPAn=<fpsuEo)LG;XYTpDa0mSc{dp8|LfNsT2}=Z=u>
z2%R7iO$^sQW9yTMA$rCMZG={r=JH1IIs+f0Ob@6!G(IpiJFTPJWs(&egqdv!I<?Nt
zj|bxbr-<SbVMYQ?L$6{e!c_l|RW!L=wj)4Yxk4SU^s@W~v;o`6u$|eebAM|~$giN;
zm^*l8`Y2sy!N_Ku9M4>jCjLrdL6vz`r7*E8_U-gU_74$-<$;EwrqnUr;mONnyM7ub
z^J-k}SLLz56xm+ASol5RxVe_~Gy!hvVm`l0YqN+geU=h~*>w3dIjMN*5@*sd*RcWM
zvZvG=Ce`m;73A@9(HWsYp4374^h9<^tlS_gLN`^-@pnXe0vuz>2YNEcE&M0NHvSv_
zHsm-rfEPeDdn4S<Y>8;*^1dq!PMS8pR;9#(Q0vDNB&b@M*9aL$w`>pJwx>07m~-Cy
z`Ha0+%qn#7NusI5jhgw;o$-#WO;J7U>1RNPf7#X^45PVd5TM}u{i(8)kU}xw_g3n>
zGul?Xk%JZv`;d!1VEB@2lyS5gjYuw~RmLjxV0(ot+|xN0=t`7CBpk`5atM^b&ptVS
z2h3Xy<<dJ!d;?yIiYzv?H&!N4w;FROKQqr(aVgmNX;4zM1E~W(nf{U+%<=@kF{Ezm
zANE8Jtvk72$yQ7vaxBA{Z};GwI1T-VC)1Zhk(2s({=5!@KzYR?-i5#5y2NWjIKmRo
z>pHy(?dFk21jzdAywrBD33yaQw?86<pno4!aIkzgDEZ4X1{kMJnTAlYS(=L904_TF
zE;_qBiRjDD9QeM&A03Hi;=E*W96}e?C;2CN4p0HSM9u`OD*<a$ft?i3j2_C<UxdXY
zEf=dEx~!1bD<npuRP-Yr^`dW#Df{SdMc&W~@$Zg1AWZNqyu6)Ju->7{11X)Tk^;+R
zo2+Rhom6d>TrC=4X--d4$xN8k?u*FFMk#c#c*}a$8v^NX&-{pUWRotwt-c0s0F5zL
zNrb>}{rii*+h!4c47}Umq|}uGmNhQ0-jPIoq0pm^i!Qgc#27}f-3G`iz`*&&ujiF$
zLz7tb8@0-h2w5iIJWCqviSgn5CjWgz_}3}cGM_t3VG!)!KR!^EltRXt{$YUk44d5W
zGM*0#1cLe)`=(eEa0ho$%N@YX_fkP_5N~5o%K8ZBRn`$~J0~b<NA$x5QHm-l&NR*z
z^>(oAjyYrzKD!?3N|-!1-Iw-N{i%(j*sxn;M)A(a&?fHAWv-5!GsNek5|R+s@|Uob
z>$}|M=*%x@sUZ4GmA6j(f??{v>0!x1!Nh{Dgdylx8`Zyucto~IEj$;*WCU4=<fGy%
zJIt~efVI+fZ&JKhd&}!6f()V<Wr~S}nuSqH1(}Q#pPb01SM|$l7Q?c9+%@o^sL<3Q
ziz(VhL&m<s<vxQLnXsgL%yP<!>+@dxPeF2#U~^e9m*}`hV_}Ma0WzE+?^+aW8!>_6
z!DKv6$ArQ)tQ%KLQaW{$T)QYz0H#g~?Y4Es&eO|$I;*Ubp)gf;S&;%14I~(vPKa89
zLd>d>PMBBIdU{sMLXnqAMz`k|jcq633t+NU1J$fA{8Gxf%3;>AU*0VZ-lMa!bSKP|
zs@T2?AUMk|3Ni+*{fQj^=qGa(Qt^mAK{8|m4Hhi@xxMx5ZSiGPsSgW~!SS5*85TDK
zkThPq-(j5T^qulr2qKQ}_MgSdb5_5kr^FA}@F47QjH_d(gP1)u_>Ei#)am*cwb;q3
zL2m2j1s-2zi~8nFnJ>G+=cM<tvnzsYjHM=%mwESVwAEo_L`{y;wUo^t(}-`^C?DjD
z%yox8;Ftkq7{UKh#qRZ^Exv^1^LO7g0W+uV@sjA64~#lxFGYg8TOTxg=?^lwk&rfg
zGz_$W@-l?2)6@8BOzu9c#Ns97HhuG>F4UV1170OuX%lnW0Ik9{^)!+b+@i%2%YD9i
zEa|+QIFZTQGIOehLVX;Ngq7U^7(f?yl?P1(@wOrvr5KY1xBjY%TxTKgE(R;Kjwloj
zeab0g{D;n+^REqcW52<SbmV#dS-1&$%#q?0&AQgx!W{5+R0VB`!dln6KB*Fk`+y-_
zT=?8yff9D~jxFLzT_z!_)c5@<@7?eYmwrCog5!*Vjo-p62oV4UCVyv{=BYTON~&8<
zGIvP0QS~3*#cQ=_aTWas@~`%wxhA#0#sZiK%U2>c<$x0fn;(qck!pPZifVf3Nlubz
zJHQ;1EeNAmW9zZyUTOx)EY>wDaZujsgd=hVcMmEuI>ZMfA7N(uA^fEbxwG71jUW+?
zIF58q*OW>CtxB~etC{Z}zI924#}oq$x?ArAC=AeBn8i0xPHKutz@enTKS6hc6J&K{
zh5ICQgte7EInkpPswDT@l!<5*i<h%J)S@`ey#DFZh#&L7FyG)1HqrK3c}|c6Ec%{W
zH7QSrDoYgdPO;deLrEy*VYxB-t8HiJFLas_HVfxZ2Tt2(2V*Lr%f}8=%!YzoAq<Wa
z^<Z+whO|1)G?N_lgro*cLgY$)!d%nJZ%sy&a&a2MjB>KXF$YMmeJx{6QvhXW&satT
z{<o39c1KT4i`6Je!P-DiQF)hV;~EC{mMJr_iFzKPN~@S|GR-fDYf8D9We|gVrPY-t
zFq+OLcfOJCnDw0XPKb)*oB$#~%SYf7Rm_QM-QHQ#Ozzbo5PZGRZuo6Rr-aLAT!4)>
zkb|f9!B%<Zxn_&Fy2j{R5iSbC!jTMlGO9FJ0EAxf!|)way?5|*$hQ8d=tc_TbW(pu
z+>szNe`LM;<la<PWR?$nEHWciP6%%dvBXqA0vhgAmDJ5}a?tCo`=OfgN|<(nBbVYJ
zF*(!$eI8{vaaA}d8MzMQcex48v`6`YJ*9s`1u);a43nxpMD>s6Fc{DMn`P54`;5^U
zyugHHa&YO~umE^9MX!uMz5i2-Tp_0#U-;Tj0+(5e|8>)S&cY`RsJiszTKEeS8S0Dz
zy@0R^Zv9^dyCXNJ==+^^4W0S+J_FgwK}n@rTi0eRb2hfxFBd+uXveicb{)V|$-N+X
zDq`olxVoYYtSjEBvZq!lWXmS4_it7wlF+T`1OhKAgvl=K!eWFZ6u_OY)~Tyb%%6BG
zTTv(%+&cWl*BITh*Gba9qC_4_;FdFRy^qZd931kVw;D{zF;s+V*rmDIz569Rq)l6i
zDE?O&>iUfnKiVp+T8fymZ!VX|{b{dJh~WlBFj^JF-H4onyv_AJ6pz+|+4=#j>{40Y
zA`2re7)%|afv$C1j{J}rm-z|g0+z9@#EEarnag9EPL-r7;L**F2h`4T#Zmpu0Tb*{
z$F^dArki;pXnv3_n4(SPnAF7rQ?v;iB4e3Z5`ShJT9T1yM2dg;jWlG^@o9@bDQUDH
zKD1W$enNE)=O=SQ@ok~+J7>UzCnL(lGetydd{Cjz!c>12br{G)`@{92yJk4Al$1aI
ziw!$de5Ds{bLO*iAVN0z#q&DH%ox%Qzyt2$rEUCedXC!`s#>c(Pz_(h0^`?E_Q?4;
z6D6~yR>{RnIZn*umdMR`RF^EX(MMZy@{O^Xv7r0G$5f|z^OIQqWOEwMWOQ#?9{TWN
z=*t};Pe~<qj4b>0y;xX>a+UiC*65rwIU3fSQx!JNdzLf}=@K~dXb;)je?^||=4HJ?
z-q2-%P?!;sM&z*8+}knzc-|m~paiP0Mw%P%Yu$SKhrwxyqkPa0NwjPc%O}Ek3Kuu&
zwHJ9JBvLu(C&C|7#w18-yltc`2&h6lrF9s>w7PXpGkrg<OCXbr+Mp5b4yt)6*V9p;
zYGVE-QQ*r2dIu``YVI~1#vPr}XQEmwx*ktDH2w7;r)u93aJ3-b+9ex?*t|g$YO!M0
zfuU(4!+L+35~~_efr>p{%e`c6#SJ;ZKlW?74l8kOs8We;0}59Dz*$dpsLbSl(~k>(
z49QDA-hZ9czP@5}6ZHvGd~CSm|EDA54*?-Ld#ztY2M+snaoXM1R@5YRcc)zA*l^?A
z|C?tC+C*;_9kqv#ceoXvb`3&hkUx&3|3-|Ts4=LwoLxIP94YYx2Xv`3|5Z{<FxFDe
z)|6vwZ8$jH8HD=>F|aqBsla4wMc&+bIVZ%#LFHK8{QUP>TdkWz2MoT}R@oaI11YO)
zS~^DcIs9g@9H)GCVk+FT9mnk|t3D{WOX0-c<f+y0&r~@k`j?MK@b}lckE$g@Br^~^
zb??!`zPp6sB+p_V+^Gr{SNPchwkm!-0*Btdo=o@3N9Hv{qzRJ>e;r+jSO!`;<t;-y
z+PN`JD2Va$(gtHGSs<;hE2KoGzGIHS@7p$x&<Lkmka2V;G=OvXS2Je310ccwu0Z7g
z`)O3d8L^Zp?Yz!#Ss)bKE$h9Z=b%RL)@)?IBB-BdWTg}>+2k8#K5Vc0H<0e>m^0%x
z65lvT#u*cZ2hbcsIQD1IIxCGUzB{+tdXyo2<{+W;sw){PoL?lk^eSIYy3`V9`2-(^
zY((an2M4Es1&zJt$cUXA`P<ObSYuvk*{xu7;EWPwTky-FmFz<9ePeE?x9G9&dAC+l
zwaCF+SHq{Os>wxn3N7Kpkjc(^2FtEreFmO%ZRq*E4?#p(sOH4)k0{{Yckt<x$xl_|
z*OBZ!r6ubi_k6}qd;Wc=u$bYlCSMBi_142Q%AexIOdJJ>R8%pd1?X1oQ#Fkm!FyfN
zOA?X37DwoX0`|zRQ3c)5Rm#L?rhL5^1-%W(AuS(}{0?8G9c(Qlz$P@AOUF7e6RZir
zmN_5+C;o|q&c~XHQE2b<BPt|D^_QQfFWIa7JN!`s-%fnc^Xr9ja|lu|Lz}Y1X^f`m
zUk>9(Tq1X+R$96XtAyh0va`vvWiNpb_Fwg>?!=STk9IV04~%BS0=YYT#@8penDKsW
z2Xl|6ujl!8PAa+^&;04YFc(X5ws2>i6c%x4LiFeC@`W7>By=;Jfb`{#w93CrAbBG5
zwJH<B<#s=5b%bdqu!EV|tQ99q&!rc1n(_xVurBPbBY=-a;et|)JTsUJ;f`@)hV*^8
zub(0-x^(26<H`18AnH763>n)V*(re^u^s?)B}Mta0_9E`c>CDJK7zbw3^(KlC)P?G
zt88_f#+$~b*|1bU8e#(b`!S5_Fuft}CZ}f>wGY5ES@@hgD;k$gl$IYADgRKyLBg_!
z6`~gp_7Rc~al04>y4?-YCi}PuSamvN;zuaXS~%#6<mOFfX5*vA3JKlp1+y8A#6mL@
z?RPS%$*DoT{m(P!TazF3@_<z|VU5#~3yynlO^{ifV5mw+JH2c+Hgbg?{IP|^X;}bR
zzDTfYq#!h`4_urEy*j<C;4A(E1Qs5P=6KtTd59Doo;wP!SuS)J+btLIH-xc|JU~9C
zY~l&L^@os2QaR$2aEF9UYFy1zqb_FmG)GRBB4WF^J~vJt1MOEql*-lHtxEIBgL`G@
zB!k_M!ncTLTWzVic&EG5NH#KL)^AVS*I|1PU>6Hj%eonCFajr&pOowOEz)BZ|L{f|
zqNpxcc;?U0Q)7|mwvrt(R6gr@b-Bz3_9Ir7I~rs}+#7Vj*xP&Kjy*%sG0E9eG1t_e
zxPXx-9~Ka&7Fj;<ya`wSyHh$Z-TfaSl+A9$)8|><>!k@HwE7AljsfxPRu<ryRQ2oR
zI|#viUy=ItKOS!?R~AS*orp&&4!WXm;6IXq9Iy`^YX8}bcJ*HY7Jg<kiVnWtnf#DV
zO=+P<v6*qHGzk;IjuUx+guqype7O8)6GG|d0OMZMJpj5nWsEq8oC$OuZttkHFSODs
zVnh+50P=hS#&<25MJJU)fw-3Lci3Pl#GS@?34%q@K=&dOOuN=IpJM3!DBm`94d1oz
zi-X9=d@d!sc7;~hV3%bS0Hms^Jw(NGwI3{TbPW}hjLn(OQ2B>%w}tbktg-4sDfl*m
zd1=znt|tOud>=R+I-oN9NtDLKj35L8L`_i(%sM<9q=s+cV27tc@+Q-DTFbypcG{{c
z{nNY=_694-mX6Djb>phoAUt3<>*W8TRnE`U$A1$B0Sc%sXAsG&bS;N%Br$j142+hg
zxz8l7k7e+y%&4D6T)W1`8)X8P&V95LB(iNz_bX~Cx2&;G!H-PQw3M%ccZP}#@dXJ#
z;Idp=-3%n=gA|i5#R$au0lDWMJN_N!-B5}CX913AuOp<u?}PX0dcM8TPQ9fqLVu4p
zHc5ZLBsJz9j$PUX!(=i`lXbn)U>03`_m5P0FGi(Oizlg?$|UvD;D)ah8*q{cCTGJW
zXMU>jw(q_zyrg3I0mp?cl{~zJM8byI0;qOw1cRu;wH)Ich?o!p&NW!EgQogD15*z3
zU_=^Qef<Vn9`^`?mzKm*EUSgq=A&)O&PQZ#1t=(g0lG>;lm=_*e5Wd<;7_uaRAHYJ
zgiYmd22aJ(=2H5GUi!PCLWdx<eiuTrGnv&#S3JX-L5r{FPhA4uAtFTJ)*y%)hscjP
z1D_qEhMe?#slw>5uUh}{XR$|ojY1xv&(HhPO`-ZTlrJ3GcO_^V!GgcF(i&R(=cEr8
z6WN2I|9WvcQsxc_1Qoi|s(-rl`2+uO;M7rg)=i9D8>>OSxleiWN*8n%uGL?}eNRZi
zc-Yr6X6xVEKV}N9Iqg8U+g!jmAmt3sT3Q!bMOstqDpo9_q3%v3KQ#$0I+VlkiA>9f
z-ddck-R@FUN|~{VyMvRIpGZ!EdQwuIjTvyr*NgSzJa`_kr);o?+RTOZv52y+Lj{33
z3vLq}qS$-}ycr8S_3t#mbdA*&#?97v&E|>nz<NM_-f}`R^0*p-!#eluexxxX$)^AO
zuddjC0f1zS`{rEwCUcoc+<x7*s#rx3!_jC%X^3P_Yh}l}y<ks5l3*BZC|uHp_W|Y}
zQ~cUtGXW9Yi89TOlNB+zD!n)OBCQ`*EwWXLFuI4v!uX`8s1eN|o3XvP{7$ey_W2^z
z$IK`X0JSWPB4s+?qhwp~oY4B#I@am9W&1=VBqzsFwVe>3J0d*%d|Za%;EH<0j$d6g
zEUDzdB~Q76L;);$Fum0gHShGvPRgesxnuO&`Z9m5u^aq644CgVmAS|wV~lP8JwW`P
zEAvTcIsJ!cHr95hY&J8plSF;S+#61-O?+-w3H2$oN-xhV4CVP<=3q{y>*b0{ZWHPZ
zqL@}nd-EyH$wu~_-!;vo*j{a54Y6u2CXZ~hYFx7=jvDviU3XabU>>#=SK62%;;S^#
z)Me6U6u?%6C~7KF<(kUZ2`YPNF-2|i+BTFYuNKtQ@>w~KdRsQ7%R`|kSk7zn>Axu`
z?z63TIp7e$<i|^9hc0U{*~}H<T01H?v&!~*@j&Z|ENA+h(Nb?P3})XwTTKOC&zm-h
zOccR=SgLvBKWoZQiGJ3y>6Q324WtaXN<F7~!tfq}HCl!g#}VU=MRg_2s0=?NgVC0)
z>$C8+>hA8kYr|>awksiX#@hjrAib_TdnU3C_&4lUTP0O|RsIUC)Pb%)XPbng&M>kT
zG2#cvr=rxmSeKNoa?s^~u!>tM{AmVq5YV<}v-n`cQi(TMV-oA^<-_+_fjbTo4zczY
zgnfc=aSBbh$h|IDrNH=XUwMzNP{e~?`b-ye$&bH5rtZkr$f$%sE5rx~D6BmtBwj}W
zWK;LD!s0q;I>1wEn|q)&RGz_*z4&6*>*6i_LrrMkg_ypcS^ZPYW8??H!OdnLkjyel
zy%<3-N*D9F-mW!Z4{CTS(ElQ0N(#m&U<Pltu2#mYDt2iz;n?2t6S5hSgsG!S&b<$e
z+7>(C&tW_EXh!WQ$2Nxoawb-6n?j#i?Man*e`?3bSk|7t1m*)jl2lWl1n{)5d9&_7
z2j47wwwmdz-M_D|E0Phf+bA{N2`Lpu%<bb*b6iu-9X{UffK>n)D@kSS;TPX$L@tvC
zadb=~26aD2$U|%VB?VTJPbh`Z?+&Yy73G#kDyuSx!JrNY0-wy2IQo_?t|{y-d*;PX
zh$_VMmI=(RaJlG!DkY`G-#rA#+s|F@pi?{4{FqvQ6LyD4sDL`imys1Nh>t~T;ySZF
ziLd@~9<rg`RF?-^a5u=ldRE?W3o}Sx#YZ|zn%s-qhl4g&bUUq1gG^bqUgD)N8k4+6
z$l>F&2U}b1YB0yJWpQ+)QgK+PMLL3p_*-*Y{Vgz211%P;$(!gHH}a|2|19GQJ7zC-
zj^g>k){QrOR>BZppKWYSK8{q&u}~o^dpk<?&6N;aQ4w^f`(vUOyh!+ILLhRvUlrjO
zeJuhYb`8xZq2MqO9i?o)lC=(!E>*6K01GCyHX+0b6#*w!9;NJBu8f4!e~@3i*(hkU
z>v9A!3%(ylnZgh_Rj1cBmd0Bs=~dU=k3UjfrFr3#EM4L=`pGU2er>O~E9~xQl)0a+
z4IfK`jLLa(VlBL6nsIM|zy@HaA=r##7A1Pqfu(Z2rT#CjMXiePwCik}yrWN+i3ZPI
zGd$K+$?f8&Q)+T%(V4s>2FUmEck-+sdL_wg8m=~B4UVVlW;;QPM7W<U0E{a-3pfWM
z15SOn7=p}xLV5~4`!dt+aexh$JsU3#yQYK&VC-{=zt<FrvqysEBb|xWtLRMG9DkiF
zZuD<aY^VI~DTTBuRsYy3`dpXwHa@bgNfOmvnjuw2vVBFmrh>_rpNZ}eh@DsQ`dB5o
z6Zgu&Q9u3I#WBdGEba3g_44Em90}dWt^ul)T94H+<`E_*%MH@2YHNZkx^GJMyQ_-h
z<qNoDTwNSvR{RbjGw05I<^T`OtrT!K9t?)rixZW;UUED6?ii86gEGR=x8MvE896*Z
z+Dt`zeN^>~j3CG+MC>J3HNveF{i(X-VSsQ7TV0DcFv&etta}LI4_ARSB9s45rSX!o
zbTjl<N%_mj!d28IcZCm7<{D<vZ4jcwm7qcm``}2e)8bU#Pm=JEA8JHefH1T7bo*Rn
zUs2qfEmede0Dj{|-^}RX>hv>cWt|jp;&bU}7*4Wkb)y50I=!<3W(f1Bw|Gf$>S`p!
zl$RL3c<-OfO?$x>@)zX*MXJ$gk6+exLX(dg0)5AM>SpKVHL-^KsymZcQ+}CD7&Ub<
ze90LGLi4Dz!lBsBy+feLQ@_3F9#WO6=x6kUHh5Nvm-b5?32{G-Mh8)hs&3jylu;V5
z&CIaP*g7<_h2*2VcvDAvPp8e&`BuB(-QU@ZDT0a2AU)?}omct{s<AKdn_EH0P`<vH
zl0)eYHQ6js3zxI`vwQpDM=mVx-ee)kyHxflS;(Qz9@=}W1F44y{dv$AY8OnyxZ0JN
zo1a~_kh7tU;`YRLqFK&&5@;lSU^GyGKN9|pucQq1^h-k!SWd#HiLk>+*VXNrSG7n|
zgNTI9>vyg<edM(S-55UVB3du1Zh~ZsR8_80z1zm%a!w*zwVL?joMa5|@P6qmw^Qb2
zG=$2JoA2!bmIewGO9i)J$N~#u9~;RC#0HZs4r2w!HX<)zv2k%8ys{nhdEfOO;}lI?
zy`X>91>b@|aLHspw5-h}=0rkFR5+m7<P}Muc}l+uMFj{-aXG=_Y584x(esy<#sXob
zp>-}yUkMw3#P=I)+v(UCYt?s>b{f@r=GbKi58NCdZ{Wa`P#K%tKQo=@v=huC@$7>d
zXRlHYf5dEEeR`movG!JUjsd7j^jmG709}R3Z~h`UDC%rj2XzP0VU<+ib8+zqm!Ew3
zQXx;5;!AC71NrcFnVZg2-kgJC&A_4xC`@;7ymqv~i>2AK(zJ9uT%emeYthbjMAC^1
z0cH~;8u~!3hUvB_LCTJXQ0FXQxf_u3!fn2@2q0P(+c7OR61gB8xk53H4cWTSK;B5V
zy8j2mXlbT{)uMMKT)dhJ_}oufY!Z@$6r{N`4vIF3p+UJbFi_pZyiu-GGo=oVi}S#G
zJQ0ThJJE{gI(~=Ec(_3vPA{9aAj8Q6lD;WB$yyFHTgyMCvx_CF#(y!}ZYnYOK5O>c
zzYcVivB+~<-L6v>(*pQL2)nshwX4Mj9)Lldo@V%jGG*lgDUt-E+Lc-Tb_4*P2$Sgu
za!<HT72*+6Xi%?z`*(o6MAxeC@NWXc$|Z=ZNF2GHS;=qTr4X=<uxF|nV%7}k{m*zG
z^-TmzcE7XNy2n2r!V}w0x|iQN1n|c;ev=U;v*}3@-jJv=BH&hFpyOM@Vykp9h%V23
z5V8N>^i-p3%)$`|irglNl?9SHR8$+iY7TJ0gO2TC=DQFI!KL=MWDFXFfqL?lP(A^i
zvq~+h&c#ThY9=y1@6}dDPIPgyh%)Ne=Ur4U_8Hg}%zTh~apY1(_Z9v%^NNSvT6<}J
z?M5~q4E;2ZTW^A`pi_2n@Q(-jY+2~`erl)y(*!9rK9y*Es`vH%`gAk=eS%n?es+%J
z?J2F|UnhJc6Hb0hDI9W=y=`9>S4`ew;G|nUfY&89arlh01b@JQ-9#AvG0M%CGTLKV
zmZ!U|`Vc_Gfm0RGu?uX5sWhHvfo_INq#wIZwa2*tVaJTz60;c9&20+Y@?t0I_~7x(
zwk??JZCN`-8x41OKcUIo8uZw0eV!FuieLE55j*9j0B?0sLdHi%2~?n)>Rek{7O827
zEgvuUdN}YMExLQNeY@WVtM^;s#y_e<3N`v;mFZDO_Btg8LQ$vh4N8ea@L!gIh_Ofi
z!s8BInZ_}t`vLmmh`%IfRRR`dj4gBAT5T~)T>Go0zyoK)1P7)5$y%a!zbq0pweVGJ
z!MckQ_{^LhO1qlbqMf~vT08FvnCLj!0QL*O?rrT4Pv+3tB4ZnXMmx~a6>R8`+*Yf)
zc_h;Y(Q;7jC?*fA%tDjG#jwwL4FL(?U}rI3+vPumEi2^~VyKB*=K9Q#JNEGDQWkz*
zIblVPkW)mUJH;nELODSsW1GxD1e&25lR2=BIe|1_w35MYbGYbvuWsxd&UM};nhcHI
zF<55V{g{;Ri`Db(_E0PH+<h)p)Hk8QX@m7kc<jnpL3&J;#gKRgL_PX0ym|F!3&2}>
z2_G)KWl@`ko?ObPUtFOS-Qh_mL$)g_b1{?Bt?8_4h5SM#>V83iRs-Qv6~6~Am6zRg
z+~7*Mmx19TcH_T`3oOxYnX77y-lb;oSzHIPO`IirR?8dwMTO@)-_-f<FaIRf{xX#A
z7}*n?Qcgw1k5Q3dQq#xQF^`W@XL&SGz{<ciEp?Bd8%#_WIL&2BQqI{O!-x)mhJkXd
zQ*ei6nV%4nq_-jiA-qZtYsrtHWRAUMe;kB)9tha&#&R#yL9<o=Oiw($fUTCYIwgS%
zyUs%LHQTQs4dU?mT#q^IV>eabHaM^sarC4;*k=noKrg*@>ECVnzeophulFsi35(bm
z>`A%5uL29%5r}iA@KA-KcCX-8E~(G77=|DhKa<u8l>#<2`#zyBbT!gdCxjhdx3FZ`
z=o-G-ua{3M4r%S*!`h`waovTgq4g8%9s#kaUmV8y5gg39M<!kq^^z*G6i~2i>br>d
zcpU9HN<M*yY-Yl|BFW?NgMWqe-+mu`8<+c9MV);`Hhi5?MyIaZ*#~uH#Jk<i!z_C`
zHuJ$`-9GrJi5ygw=qsZ6^M|VF4_vp4!%;pRoN<WylAbjt<4ukh%4*E*cSIrxFSDrZ
zzj4Dlr9;0jwt771e5Afo+*U1E*U%xtkPwYxjb4}Xm_1PSD{UtOxTs4nLZP!IyS|;J
z9!TKH+WvjPrXCY7(Zvfw$e-Od86YWg0u(fgt-plfi*ZHvP5^MpD<bFnkAYvp1VCbR
zr4V5at9ZqCgJRIH9kBQnFPV&P?9x3Z_TE~GN^NplZ0Y=V@qw?P2Au2m)*{rSPB&eJ
zmxTP@7UP3xG)yJ=n4s+l?qO$QQ@-E;^(p(v>%1&u@r^aua2};jzOaePC4%X~@aw1K
zb;)Yt`fD-85*%RaocLx^miZeRjl)~Kx$>^bs=`NtiXpF~Q@RHM;Q|t5cDVrxF@@ja
zx|Ha!x&w|PhOLB_p5JoY?wRU(*wn<8Wzq15!RZum;1;Z_Aukx#S{d;oYi0yp_3Zt%
zdjcVYwn*fUFbyU)enf`icOk{PJ{_nAw?h(nJYBCn#+m8Z{dBu9Ps3>;TLY%HVg#&Z
zMZ)`0J;ygr;0}WN&A#a^VlULWFGSp@1Xmi5E?BU=kv%vMH+`gE?#18Odo;uWe#+HJ
z7Vc~r1zkuMd@T*X3{6(I8D&*cWvk-9zwS5{eL(WCAKq`KEDPBMonk><<5w<iu$(KQ
z?Nm9vxrgASfr_~()xbOv>$LX$Bh&B;GjnX*1`HBzPgv7&o-&5x+Z4)A?+q_-B|7vL
z^r9%I8Djb=dx&olfvVg|$=ro-CDkJ=@HgP_fgkcpr}*!apMw&yh_c-B-g3oTBK9~v
zLsY7;qPv#E%vJCo?w*iK7nyc~05d?$zvva+LXqS-CBC*Z14Uzq(8KGOv&Us21r1J&
z-!z-H{&Ycjq{NleA%eO@tr}Vb{t9VNkd`tF*tPvC+><b%vdM8{SHB*2O8wa?Id(FR
z;%DC7SZEP!$mo)57-^pazJ_z1&-}_E#^35BJbnHs!W*x4NQM5dvrbgfMSXje7-EQl
zQ{D2~VR=K0OJyJydhgv_OmpQ7!{?qTo6?}^263#}^tiR%XFB&b;?est-_QHKJx}L?
zpZ;!seUN;{pMr+e94=0}B#rO|x#{y6vE{F2<9mN2Q7np~{8+XR@~w!)2^O5`{bT(}
zLY1np#qh&Hl@z;r(`;KXbF+TFDtUP3LMu|xEsV=e?E{skIuUn-KQ!*5`ta8^Nk9b2
zI_QvanN$R=XADT$&{?)OBoq^dvW(JU2S(GUgcdI@-8~@urRx3rqcF26AJTo2Hy_~E
z?nB~veJ>mA^6xiwQ*pJ|GMYbl%-xnD?+;_B`k_$U`C`b$CWuWXtU`A#5uJOQ^XWKG
zowT@hS%)SjeV0N$7n=xl+NZNTP^cA{pk;P=4EsUZ=jr>D-!OqxtpK(-9XNr+^A4iH
zrHxLy7yJ<+C4Dbfa-QGW*2hVA&q)Intg|1`AEZ{QE?oOkD{qx3Ju&_Aj-$xvBYiFX
zR2IL+$e=)ugWCyTPGpKnu6HMmkORkmyCYJ1(*##=Wr**@mx$zt1j7fsrx$6YIAA7s
zPiS#Yx@t9u_fe9v_gZB~R3{|nd&&>HI&wt1M}FE*mAX=8SS>~Q-_+5{=QoNh1x4SR
z*6K>Ghpi6p>G%LYrUUgjp4A9!JgxYX)5jvy%4<tgO(}^5=wGlRR3vw$a225AbRyAP
z?Gw?Z(CYO0$)*b*x-kjE{{56N!iM9G_g!^@4CGK(6PMlnr%)3cHJ@U$*<I14@D*I|
zk&md$weDv?ol2L`M=S(EI}?Vs=$Qu<0cq2myS(>z!h>h-G=%bSj|Ufjp?dXa=2`=&
zL~)_*<9DDu6<!_)&qJHfUG}eVyIeo&<k(pAmGWVMMVreWEC!rh`<3x=I`FPzs|fL=
zT_w=0GhXW;TM_F+;o}cGRBf(zl@jJ}9vYdihpEbEfg$H_5Z&%6+qR1Ng@G%C^mqNw
zWw8GW9-A)`XD}5Qfl(Y4WY|mKDdR)$z8>65L&-gglRjDv3W9#mDq5(N_2?eoV=H-2
zTAqIB=ZZ2WzKdTJm!4xP;HUMggRCd4x^BYkG=+?3&TpwP1{~O>84Hw|JG9NFbH3nz
zeVkgOU_#V{E?86M4p@^JNGfd6A>G$CV|HI1V}6FLDMn2ckVx%$if^IbFA9-pbzb&a
z$!$)8LXd#`)Pl5v!v{*%F1`q@;5FVs2rvaK87l?%bnr06yJN7Wwko<L_w{EQo*{2O
z+4!48^TQJ<@Y=*PUf(U=NjTXZobUu07_Q6PWGFnQExMP+9rmVI2~OLkx8-B;grN43
zhVWSI?MF9Yjdpq{;3ds^5Y?Q(#`-jdb_*+T<<==gn$|rkd^Nsttu_&vG!Ejjv+Z$h
zdr(X>2-QMC%&>EU;-;+Dl~!8TBt!5gklkKHroI%VvQFj+t7#s37Y6a~?<wmh5rN9#
zB$s0oU3du0uAq1bm8^OqkS{PHjJ4q;k+O*D`F434xC?dO<$$Adm=iNDww9PqW^k*@
zBbzMUJqUf7(C7^CJb9K1NcjU-5!7*Rp(HH<4(SU<XI`z+FbFUSQ4Ac%QNTyZ#h6PG
zl(4VMFGZ)jluJbwm09c$pgEh?UwxT%;Ho9HLPVzA3AbYKp)Dt8{16UncDR~0%H!<T
zMa?jQSTCCpiQD%#G%YbIXjoe1#(uqPCnSGC36K>$ZCq#4zrZRGub6VO0n;)zoQWll
zFt9A+8rI(5Qr{@ajW~j&W6xE;ij{#b0*-;UZ>cRWl9W1a<o{|@s9=@GQFz>NM&dS`
z+IP;*WMHE?6sBIdyuRu{&HWBH!HY@d6CYE)P-);cEc?~OhQ<@vIX_`UR%fFu#)Jyi
zZ{;Tddn~g!Bp!*h5XvAGcIXpN$K9q^el-w0EZ4u=;*+6@F!I_wvSNbojSA@drFy@A
zdKx!DIF#b)K_|@t0E6-Z3R(vM#(!n2l0Do57DR9aWWe(c98#I@F2HxE$Q48=zm@dN
zcRMm%-Fwbj`g6IYt~y}Wuhc4Qn$2bRdd}>DDXE#5e7oMCO010+gj#mgzj0djkUr-z
zZCAgpiqN(%TCY2qjo$<%MS?=p<|4WzqOw%!Ei^F6=av`Yg_^w=aNRr+nmirbij;?<
zF;ZQ0VZx8dl9t_gHoU(BTwgD_B3t__ZC-{ZdzWf&V)$R=6!*iYLlFRcv0an)Ffy)*
zF&J4%mF`qowDXwcdKJigQ`_n)5?UwM`11W8QDJJMKc7MGt?85&3hC*E+AFJW<fyUr
z5mcU+zcSADZ^?X`!#L@sX~m;yFrw0!LdRzDrl^viG=UiFfF_iL*ye{E1(~$jpMf|S
z8Z6=PED)|rkw^22$uI~AlS`?m;`sb4a;?3Q@)KbZBC;&h5+V>n8Pex2Ul?cYnT{1%
zMYTZ7>In##X-of&X^eDOz`bnG=y{k?Jb%YO`L)Th!g~+St2!G1>sZA7b_}{}UzM9!
z+bR|5?hcT23{h<-mLEP(S!MA?;kjqJn14umcjF=?V@s1<&WW02o}9^3mmr<~aLsP2
z!$nu9Eh2UdyF@AoHqd>e=SLLj!_Np#Jq?C9Stk)x-Ydnh2uAP-@AqAO-CvL^&_U>t
z8p_Yf7A-2n0uFsfyDg=q3PJgjygTMvA~%Gr^i;JIk~t)3TZuW(#$4SEB_H6r{qZFf
zXi@~FjduU8Zx~|mZMNnY8SGxIFMw?kh_s+{yydnDG1(X|Dotj2V%^<XSR?=0o$W4H
z*s>R|v0)4G4j*0aS*x`J`^+P1sEG^<J`Al!B0DfNA44hUq6GI+nTQ*aCO2LF((w9=
z+2W;qmG<UrSdGJF1SKe|t84EP?jO_sZB*3j82ZzFq(O+_Q1YS`lrtE%(;37!SXQ=v
zasQ2roMhply?$v=Hw0HQDF}{qib$r51L?7UEHj&#t|DO~o}0wnGWtQb9{3#$mN;&<
zra-9A>3>%Y9%R@U4`>bDqYq1WKHlb4wjD+BD@kVwwh<;-TkPNy4}E0w;xZ5rw=Xlc
zqQ@V?;9?Gw@Ewe-&z6$f)u{&D5`v)R7zt=8#`GY&iBs3py}@x~TEZ#i7@3@8nyDjY
z!Zz>NhM>AdJsnDfDy#`!FlA$p5@x*rFdxeu>!f`5(U)i%91-o~CkP-34s5T2jbG$&
zuTU!Y*StWIrmXYz?S{`o-*@5F+<kfDd~(!6D1IxcF3;9xYV5tksvjN|!{d0NxuiBE
z5%z82+;nW2h-k8{mR|7}MZvtr#sr9OeBFsg*8JS_<CJk^tDuB!G6<MR1XTn*%noP)
zW}*6eaAk-u+Y{Be?2Ih|xvqMa1}z+5a}CyD+&^7sn3mb+d%uy6l{rC%V1Pusj-M@M
zvvEOw)D=adnJ3s^C&A_ZkK6amp|Rl0Tt~=R^7idi?lzsP!N<*d<;m^}T<J-?KC*Ty
z8}}$I`E-3lu#z`CHfCe`9IkK9SEcjyZPELu@?Ud>6;L3+@RfwVIo)>4RG-p1?^!41
z!#+8wa%pI-=e$!90SXdY+hS4U0cTsfEXutJ%qv)y<RM{TYvqjJt{?aV^d2i|!%|ZC
zHy~pF5Z@Iz?7)ncJ4wPVoj+5pK^C2(z8iaK<G0{QthQ``Hre?h@6R;MOW~+ec*6%O
z^Gd?@PT?km3bphaVy35aOKBk@_?>2N?5EWy5g~dxll!%+k5x$W++^UTB`abDmjn%9
zOeLmYhOBFmj@RUdAy@=`n-|((^D%Z54?pb~kfZ)ycP`VsXnWNfD(M=b`eCZLqi9eO
z2k_IwF0m;;;UsbaulSYhcG1C^merxlOR-pSl&5S>&S9|lVcwHWen~lT+V$c&?@k?<
zJ10h#I`Zr5VSkKCoa3kK6oMu~GU;s>X>OF@T2Tv6ewnX!+&SqOV)Lzo3%Xk0^m6uT
zgFuz;zPecG7;=|cN^TCeNp;ipSvC1N#FwiefIn<Dg;iH0Xo><sI}sn6(cPSA@6qKT
z!v8X{k<2QIxXguZ+CRx?L)&Q2L42*hPYV*-rDh+Tli!vov>20qFhC`}dJ!*kRx(Md
z-0;UJrR@Kl7n$+eWm&%eUSGln^|;9YInsYSUZ-Ye=P-YahNEr==76>0o=S(krFR<7
z&f8%T7NP^afyiT57^0#|zr4HeQ|GCDPh$(3UPu%fg1T=4BrL0`L|WMta_DL()&Xqz
zG_P+8g=#4yS6hJ}-9njQ_{uBkzE-P@1>iD+W|41!8G;#2A6=GHzsmk87$A;{D(Zm2
zO%Z#Z{>=XXaX=KsFOSI-qQ(Vxf@3H?EhJ2HIO_;nAof=6wO#d5s9GEycHc{OCJ*+s
za9Ba6OT?2t(ncF{^HK9xMrA!HDwWGyA?RTl+UL`}yF$nj%Dzim#YG<pC!NKPT`S^!
zGJ}6&WZ2PC>>CTu=<2N<|DP~?T3PCGl^eORD#?aPmfy)X7KmJ`Q=z9N7pbiytFzT+
zg0MOk&Z}rV_#Pe4Z^0hWE7?k_$<bc!35e4#7`xcR#BmxmO`gwo{l1;z?oG>tOd(T|
z)b^Q)2&>INVC5~!o~zK8F4ZlbyvA1-NEx=ll7yKx1ec0kiK0OomkuTj3!iUIt@1&b
ze;GuAs1Y^Ny{Td-I}67F?##S<3lJgi_NUviFo$OCazr>5$W}4|308I8f3QTY8@|u7
z>5p0@di<<9CB0MV)n-dehnaQ;{ur2&zZ(T0@%;RP&xS7Ns?BC(hXI?Ud~}(9aF!!M
zHgVTjN9DVKqj4f_P%+!SuU`t?Qfc;rp<)Mt8E#d2KR-?sIa>N@(bPifXZx|Qja&iZ
z1Nj3sk_*8<(zhHUX4X}Bod833s0V#SuU+{x1q01W5C_3q!&(<e+$IR-w5@gYZ7-=e
z;v(yLaep?e)VY15g674N?_S{e$3FN^Rd75{DI{~}%eP=0`rStz+*1l`#bEg^VvD|S
z!@N~{JUK^rbBaS_XfF1N4SR2Uts>AKO|jNNQ`@q}1fj6TK(-Yh?-D9#G}cVPvcZFW
zjatwX#hEri1y^Cp>#*1qxBmWW95w815ikxkqP;5lF&+h5{yZMt+Ii^dBK1=Qt~M`N
zUNd$)!Rf+u3o{Iz@C0}|gz<r`zJd|F0xvd%n&dX`P7kwOI%N16kE8N1?bq09X?NE$
zB10aigRP09a%8AY0c%o@wct#o4R5)tbD()g08K&D7AEwL1he$Xi4AZ#;XTfVi{&AP
z8+&-jYuj0Z@|GhhVxc_9lsB`3{%Gv;S0Q<76N>S)vmTzdO#}@u^RP{j8E3Q^wbV2?
zWk99=n<n4;gd>oL<c^O?@Q66iW7Risl?fvH!o*XT)g5B!%O?_YykJC-xpZ5v#I1{`
zSl)!vSiNFC#uMdW0@=|=D)2y57JV7m5V7JYwEB~iCsFNk2^<Fs-K0uAwl)t5m0wgb
zm%Qil%vC8bddzC$8Zp0E8-a>Ein*PC?w?!aT93CXL)Dx)V-e$wZ4TEtp#lC~WdTfp
zv|g>1`Xq9%_U6qqrRrVGF1HOvoK;)CIlu7M>QNhPFdHS|AKw%(r7h5)*h`NE59`Rd
zc&TM&dTXOZ3#(WhNVHD9wR4hRe{Avu%G^3Wa;E4iZ>xX}G|KHvj?yg5`LL6{+u#X^
zIS4S0Ki7c^n)tP<x$_s$X+5o*J83~*@IkS^(am)%*Y(|F<F6u}NF!(DFM{aI^VrI;
z23eD=8N~1f)`J8j(GN;MGrjBcX}z;f=_fTN)+qXrkZn|mp6%2ne7x6z0+)?j4FEWR
z@ACF$54Zl_0?Mw@vaznZJgAR!GiZ3dLT;H^lpotnfH;hzCC%P#xVV;rpn32+E3!M^
zoMJ$>>)VP(r}|W~*tF@B1OBpcMXDOlN7b8b-glXdaRAzL70sI_DH2oFw?_)YYVNXd
zNR?sIW{ft)zmhc%Tn^$#2DsB^nF$#Mb6<1(OYlXiVw+E`X_0;-(5tP5?ea&}uSWqX
zyPu;0(@Ko#E4v3RbM<$k=WpT=ZbZQ8K}nPwZyUWzb9y)tv(IR+mnEuE*2~vj8O9&6
zikv?`>=CzpZUIvAOaBBrR41U3!Uu_0hvdpllEg$o-3uEPzW#%ir;$@F8-NddJ7UeY
zn%rX4-1A}8?q~tvj?&)I!h0L>92}k{fP!H_hkWV&#heYpWf^Px0Rooplb`k-`}9aA
zG)djaU1KcAubyKb2Op&HeVg%GQ)=*NfVBWIW&~XKd=7+G*jbuy393j)>c{nNuGF*X
zUj;r~SHq`8D)DFmoN^g^md`+9Ez(Rej49DogO)_1*tgIExur&AipDk)QyA%KJqdz;
ziAJDG)#BJw%l=EvAp%N2uqs+UKj)&Md23yfvDX}^!8J`n+6a5$ck@OuFIv!bDAzZ(
z0hxSpNEaexq^RKOn~lnvGd2J`n}#&dN#;*dS;oW;t7)7!0K-Q8vJb$fGR;-1uMgD4
zsD3e0Kh<^e!a)nWWG=aoJ4nB6&Lv^a)n%*mIBJ8=8!gY+H~FCaF!wzTOf~8P2KJK-
zo+nwJqR&r#Uyi&9MkLddRNl4`0cLpPS`;VR#i;?!B4zj+#Dlftd|$;k;TZw$A4&}q
zJQUpv5p|O8roLm7<1NFX)%t_1I7hqZqH#RB={bFHnJ~i4Zq#b(@vU#acBoQ4CC1}(
zHI6+s9Gj@=s7r~O2i$3a&Rqp*$HUMxZ_#{jZ+VZFWH$xDh9ZmIN}>;PbQc;&wEB33
z_HDlLGjhH>2uJ#y8d=b;i7aVr@k?SU`Fsq9b{Fw;IvXL4D|3qXzZ^+|Z=?S!KJ8`x
zwh8Iw`dFob6BE_Wz37?+j$@m3D)ha;)1|}BH5pnt=5fe;zemk&$l#i<MBb+gOUju5
z7-aP>8g=(R=zBk19l*Spt>i<C0`x>RKPu1hJ8W(v!qUtxk%aSYe|5H`>qs5@pkn?D
zFd_ljOAm$v)0>ajJLrKM0O_TSlg~Z;1~qhK=l5rSts;vaEH@_D80{|#AD!m$;<Nbl
zSJ~`^S0qNrg0QlMyy_8jch2+xiha#-?Y~Q@u!O5>G{_wk2RWPDA63|t&@YkWGYTi&
zv@(exmq35Wg%{#^a{;5A$f9F(F8*iTA~&#I6MR&B%$2*w1`^>iuaHUr9ZxOOYE@hl
zDULkN;U8|Lqj_+q47W3M>3+_kYIH_*q@hZwHecswxS@`7nWU{9$U0L@OaX}(z3bk_
z>8VWjryxJegN2Dz&fMu$@cEcsh6pi++}=i|i;8+XD@@z4uCw$@n0ZyGQ`GU&7vVv_
zxmBhbvVhkOf9VuG(S2cWsiFSbn1iP9CUna3XjTRJ*;OQ8P7HO~c{!M_<Bf#H`Em~7
zYOd+s1yU?1*BsRskD%Z$+BEY_1g6oHVu7)rN5BN0%$GZioXNkAX(6bDIpuaxw&7wq
zYV3(45ktU44ti%m>bnoFSzZ<%_l)KV{74Py*qNlO9g!bx7L$;zE3;)^Zje>9N~0G|
zn>`{HC#PdfWyy}m{?j}6?7P#Q%ycr^0E}EXG@YxZVt}E@;?-8><lp$q*KT8wD(?9T
zwXz9XIG=!j_0flYWMmI20}4sgdFw*jRcfC^Tm#9yIR=md*1*)l-8BBp)9{32i#R=n
zK)&apTgL?P*RxyS+4*Z)Amf&{*jZ?{venzdc_!b6lWm)aG?~=PzXWNFXGw|%LyOdg
z?cEAw6z?#-K+OJiFRfquqzU;?e4b`Iz_pPdeB$hy&1pL;j2O-WUSjWv6wf{yz^SId
z&aJo<0BTe9pUnr{>5~yVdHd-}Exi<_pJbNO#BEg$ijtrc7rf<Ww(-!2%g(@R_t!M#
z?M009I8)r=9z(LDTyW63rIpTHx!g>mwe#LKE=F1N&Yp1c+118g^6jF}wEfkdb;bLb
z1m~5w!baPaRiE<wBi;YtlRUA<)W3Ghx5c?7IT5?{@zOC1tg{xLGn27Mk<Q4uas%~R
z#KN;}mhM6l#J$~zs4|9U?R@!WI9ZT1-i?YR|D^td=g1Dy(FKukK)O%Dk{3O-CRKs2
zEwu)D0Gz!Bcc|RB_tjm5eRJ~?N~ZMt(7zNYu*#oX%P9ONX!vRYEAvhghNL&oQ+2cT
zKkqm`6Gaj0Yg1d4aWzb#vb@K9EZTJ}ym@Jma=3;ty=8e2oa3&y+^psvqG5Sy3))Q3
zYdgV6CP;BTpVx7v`d?At6ghwRYZ;26WCV8?W5km6rA$=Y+F3k`FR3cup>nJhm|2`_
zsQDhtJ0IvQ4=~rbQ_=dY6TE#<rVin0&QEhwodWwQAKYoa5sx%Gx$=batT-&I%TFN$
z*3@kl42S`nTGZ;0w%>JR#GFyh<B{^gnY$vq&*N5pibPnH9PWunS<|<&%>5g=d0J+;
z5so%@$p6UL#PM<0-bLN$Lk^Y#_b;tSm8qFD&G7O30Iuuo-%caSCne`w5FZU|ZJlUb
zx}iHz-G-6KKF)2<Kxh7PLii_dt5JUds*pvTf5;vAb}9}f?(N#z;ocuSmelqu-=i)1
zuZJ$eW-4AYI=r_v_K|T;UgVQVsz2U)W>D)obC9__H=vr35vX=y@SiFt@vQa}(2b}9
z*V7KS?Hq)P@=J}Fw3OkA?Uhsk&dWL=AK-r#(h0G{{M$hfM&7V43_%}0BFX#`_QqcL
z%}VYsQ0!t&vd~JJEq>L5=RigQVOI~(E%IK@KOw|tUsbH{*3#vuMWBm~i}$Fk*b@%n
z3c{(q8}(UB4u$4sMoT-NlJL$->OxG8vpji1Oi6TQOq)o%|0t98K^(hYcs0Vdim+=|
zeEkky`KcMp0)ctriECa_C(lEnjRs?E(#L>czV9sJB+S6>EO1GOl%EwzcI?r&HhMJ!
za-P1DGm^E7MlDq)x|~IpX2UYISX!Hc_4ashGi2l&@aOTZ@C4$USVN(O>lxV4Mo>u2
zhNS$C0m?tQ*&X8!H#vFHJ~>_qo;cj6BL06CyC0va9T4@l)^`A{;A)%lhM7+lgBCI2
zbRf-BzF&B{KRSOxA|BoNPy<_5S4>;jtUZ4AIm^#3g3${3N*T$I2$$p;q~^l*P-2k7
z5*Mz$&xw8q9Af|-DpdGO7A7R>{SCXLmIt=b3rdmm%Hy7U-4#VJe_`{kj+TmopXou}
z6?lla9&RiXAha0gybG+Z(o&mwPX=qk0ZB7_Fr-VHC3LV1nB|g_!U*`2{OALyZ+G6K
zf%%m989pK&AN_x^D#V_u(b&%Ovq{P9MrV#^R7(j;80>8{y6dTFfg;#O^0hXxpej0-
zYMp%?Z;`pRZQ>RKDKkoZj+Ei`C(z1z9?B_%G9Q!EmEs;vbE}k(Hbuh7tSQsm4}aQT
zN8j3v><ld2?2Tf%Jcq1WZfmm}EX%urE;Q}c$`ixDGm@W1wh^Lgp;6mB?go=fm?U3E
zEh;Gvt}94!;F1%W>&#8HDpF3<ZfpjM3ayyzL7WmJm{VALDHtF$f$|)-T^jgQfh>d)
zUuh5VUK0M<GH^3+Jr_qwoy(>Tn8Gfk?GoTl@7c#`<1U(DW%2F%k7C}7asEGIUwiZ~
zx@CfUK?42wy{YQ_VdaY(6%M?w3KAVLhE|0(?SWO^lgapLo8U0dV#j%W)I56VFy&@N
zor@V~2i)?8FyN<J7o&U}78vhi->##wHX)ZDN(r?}6;5QNg7%bJbsvp}O2w5sr;5Qk
zlFXP2{RdM*F?-U-?lx+jQz4Ho<z9jruE_=WUuGDZ0r+0;R|z0^)fI9Rac^PQ79I(!
zfEG+6Tw8~ihnP*s4X43m^!-F-_h0>i^|X^gcExOlIGXOBcLiLhP>o!LVr>n_pqTow
z>6BffRCK=0gNn4gvEY%b{rd%@5du~Md5Ew~vt&*lam|4?Xps|glTpclRaNCaqBZ{p
zR%n$O5v4T?aP-l^5uMf)KDw?gl_#URvF1jUW1Xu-D?|Bd5EG{e6xa$4#;I>IDQrKl
z6!j+`BhDTgp9n+rV9KfY=c>)fVHwkaCSKVSK<s0i>lwS0I>B~n_1WxX)I~gjxCvwS
zefwE%y#vDuySm<T5Kw6)Pe$rb)iP-LTJifH?+C37B}6^nWOlk3-N5Zvs<@<LrD%K~
z6>>o!kF{ie+G&-K+yM#i2;(8=i~xKui?eT)&^_#jx3QWPUtFzfkf9(fYrL%sLjxIt
zpMRFP&|;uVNnZ+c5QnI<OYc4U$3b9}*qsLdqV_wgGlyIg_*;uV%NWB08l42Xh%Q^i
zOAw>#4d^)mOCm$S*3D~iP|Xq;lQ#qfsc&`IMBXLL6c@7eL!XT5xjHn|RGF09I(_qZ
zd>gl!&O${=b0#0+PSuUA3*P=mmS+n_0g&UgE?ZcY>6V$@s}V9%nnwvCZGs+<09X1X
zOYKmy5#yj2zkUK>O(rDec{a<mn;R6KBKYA%iE-07@>>RE)0}LPAai_rb~ds4)SDcw
z7o^wyp0rVcnE6>m=bmXGw!lEJwv3|G=0a3Z6HYU-QEV;zrzvd|K_a%iU<L*q8Blbq
zJC#Y8ynUZn9U47+gOachXDxqI7NyDMN;TCdLBqMOf(2Te5bASZ6om8-aQ(vv*1lyY
z8(Liii@)S?uG1y%95()2H}Hte%Rl~(1<q%k-S-|1sDS_cC{x3nD)-<x1f{cI1;Z;c
zol@yy9~tdR@$#Ayv~vW<WKo&f;u9{!qZe`gyk^Gor``y)85Ma!lg&#UNTeh>MNA$F
zZz{{Emn`w&Ky#*oLh1kUVW`!-Cu{;YYv_=?m8<Sep~7XQ8*z$2V~M}BrX@B?nAObF
z#+Y!qq1y(ICm*lEzS_V?R`p*BM^?=zNXUtH58g%voAuA@Xw_lK@4SNrN^rt~RlqGp
z46C6EIjN;pS}~yuaC_`Pm*>gcF1e133T5k7#>a3Hv#GcKK9H1jZ&!4Bca-dc-V~4e
z&R-*|?2&91I9w*Cc%L6;WIp()a>wN1wA0~o0Hl9s0;VcAJm^DhBWciAh}V-XLrxwz
z2pp7zNz-}(E^RUvBR}B@&VEdyN}s)1v3Bw?--eAOoTqZC9b??%w<p9J3)&+=J@D=S
zM3RM~pw`^b7jWtgL%rI)PgEgN<6D98J2~}6TlAeTrb*U=A)ArLL3qhCH&F5x3ceDu
z*2AjXt5?nj@NE%MP9$1Q3&&YTrI)gX>e@cFS%aN(#Z7;lW{D)&*b%OL_1_OKCJY?O
zmpg&NFyLndEXC$athc41nAmn2Dn*S0F%a-c1eYsC9~9P7yLx+SwWgQ91I2t|uPxmw
zr7K?-j>o8W5e>O35@t8!GjPr@a(`m8Fv;MrPUW}@f;Cg_Dz6N5=M<ZDeqduX9pJbm
zJ%r&GKS#{>W>tIAOSqSO`JdxMBsRr>F~-&qN4@KAqM;MJZKSBE+ai4hJvD&rkGtd+
zX|^OHgJvOSAs!3aqMgNtUoY|y?E6_|A>DJ3inn1Ii&{^luKM?Y6HxL}Wsq`}6h$J1
zTF}SX(zvVH`JpGfvCH8^FvfpbJRHhucSad`^OF}~uV^PeQw=B8JsfHcT(Nd}atMRA
z&T)D4s2bV4_E63k+uEEb7r*WtnkX1)2S)G|v+ajDJd{8#oXjHzWJqt&W1WKm@({Ea
z(?v>|x@vTz1Q`f`0#R1V(#>IR4x3MwP+Z&xWI7T!#e=f7kq^6wCI7@DO^!*+hvk5~
zTJ1)idZVys+Rr&5lcn`H7LO@Jdx%*8T^Fc2jpo>VnGvY2)@4r_3~|3%_+$g%Mn1Pr
zrBgf+MXxuP8g6J{;7)k8rS0X;Mqsj|)Lpm$nM);kXPGZYtTw&jG50RmOh8=+XobTd
zcutH+8cDBroy`?E9%1;D>#GX?8UBNl8ju7zj>KoG3CERmSyeSwRlKx~nks~@mF_)(
z8Yxk+z78z0ma45vqd?oO*t_8$DwboUjClnNcc8oEoCJsNq+tRJr@oIz&zUHro&?kV
zX~b}BK<tsL&e7c>&5~^-0BgzM6h(7HTKC(PnFT{;2v)Q(SOe+R*>E~)62Y1?kOoSa
zJ#Qh0vGhhiy8fA<&!T)fIe|WIB5S8H-;l-_X@-!IC8M>>DQ0=wBqaEEK)&yElW`y+
z`dq503aEiAXwi3!xq^^GZwv0bY(jbfCxMeBC#NrO&;<zruCyYlJQHX5{m^NpWyT}P
z_Uy&AU$+}xrqI`D|NX^3F~TmbO2Sp25KMQ<R-*BQWMUW9?wk9Bb__BovlZ7x4W!Y1
zwoX9@UBHr-x?j_P17*PVHrpZH*wRoR??F>qO!VJa@%hS!T?;mDM*$xBJZbMr#8So&
z;mtiQOE`^LjEe;)EW;O6r-q1>iL9j{Ztd<<F6V-CGSDU^(*%3aA@$fZ9$zB#d`%-m
zmiKh83?AflcL&}FFqMX;DSO@Rf)Zv9cWQqIB+@3|y+FK*q-*q6aO;3U3=Ft)&3?lB
zJqmxBCVyK;%9lmfsH#_Gk@7O?s}1{L@<ZJ<30yD&f#+=aE61;^6eP)c>@a_cX#oPL
zXrdMgied7$!I`un2bF;kQNhCl{3~O<W$ZMp))b}n<pV>H77-&ZiGXZ@2`#AtW8J5E
zQ?gc~`YiW=O*dc6+#I`NdU>3Xm0rjOjEuV`k!cfxgrclWcbVs9LJ$V(r=+_+7!f4H
z`niG)0t~Rnfbpr^)s?SzA1rhn0dZrLEg(&Cj~de$t2F$V1_oyi%Z}FDg3fogVxdBg
z+?W+K;S`n6HG5eC<GHm2P)hB#Kmh}sn#0W($~-C!%beOvzk=%lBhvZeK~-d#Ue6CI
z#!M_$Z^FV{n~U3Q8z;>EJ_sn52LFZ7l-0KS^UGE4pX}X{qXM}diev!9;Gwi<>q*(|
zN<}`}ib98-*-|2-n{BnobibEej&e6=5pvBP1)>7KzPV6%LFvGwf`S2_`MKI+g>Ml*
zZewkS=k^_%#I*WFV?E07*Vk9s;7-oeDB8xXPQe8e$HXICDL>#*6nMHRr^HI<LELSE
z0SNl&Iq?TjvTU6Y2iQYB#uH_Cudgcpfg^RoB{xFolzNB3K3L&FN^P=Gox#e-don?V
z=&6ZhDp%e@!GDF@)j6vcJj6Uxl~ZhVAc*Dje;s2+%D$DZ);@)nvoi_3BgY<*9Fsz3
zgjIe`5WiVHVr9sa4;l2oX?#zxY3a9$r3INFAe56T)k@fE0L9<RJv~`)Zf6O!PdKq?
zalk!TL1~k#>~UHX6AS<-2=cnVNDtgizBXA-da{SlMc`(%jT`>bx>$0;lBRnfE!|KI
z=J+G-u5xc*VEGlhN{_gm3t-cP9XNN{2LQyTqlGE5YI<~|GIJk!ARZwxX*)pva10Ix
z2JqaUV-UsqhHV5hQh3GLy&^PdRp<vglbK0N{D<fk7)V_Qd-enZtahflJ#GXnRX;IL
z54s%_tia~UqtGH7!pT@lZ6km=4zR}*F~d!b=V6MMrR!E4CD<(h>=jOlbU#JY+3~UM
zk)<KDyWQ9J^~ZpIvRFBj4esr<aQNy0)v^=vkeo2Nwd)~RT*_tb3&R12U6zy7WkBsu
zc_bedNmzYk(ju`Vi&?pufKrCC1&p6D)P+w+p3@WD{PIP4bxCt041f{Uw>X$l5~!pW
zMp{};X&>~zt9&sDQ<Od@H%o3<*2*Zihq9;abw73K2`S$;>$XJ)|Ja9IJMyQYJh85t
zV<`@|BW{gOnAWREj!*`{ptPjmbQ9-HOo@NAP~}oK1*{`>fn-q?FX`AK=u0T%S2#sz
zm!6=UaTckTKK<xj-|BuYtBATJOo$KXAVG2iUc+0RDqxTk?EdL){hkwWm0BMG+PZqb
z8{F(sLY2ku?^}{=K``TZk3x@k4a)n-Up^!Q>3;r#_YT+!OH%X<>eAQ{W(Nq#qYMoW
zSRqN%#O{>dqk^A%%a<f#)kgPg#xC<=6h=<Rv&Oz}tZqQf&ItQhrB-*5AsgsPzN;Z>
z{3v^YjQO4z{iEF$E2ib%dWy8KZ(nYS?G>~s%2ccGUll4=5l%<l)udoHYDl)!;2LL!
zqW<Rx+}8@Ou`Lg#c7_mloS2v8Bcq<n^y>yplu9c<*P`3h+~4(wyFwEyh|vo=`H*=v
z;RX19&+s=FNcO3r7_&?a_*Ny&j0@#iH$8V;<!6R`PPNf@?)!E8=UuAx8pMpMGj?2V
z&m6@F4<x_sG{dqy93L#MntN9KAsacfSekG5jWR#r+LHBpe=yD~tRET^k7q6Sh`Y-!
z>By+X*%@t!UzSumDyW_$?G?>8<bfmCtpA1Ue?o&S5zgVdOiZlg<oD_qb(#2zE3~id
zjz(?MN4bDgX?FZ#+Z-DLaQr6v%`Q~cN1PFQ_QQwmdt-2^1#q2?iBmJ?TmK(Hq<3P9
z)46dNVToX})jeKag-yJud7s4PzhUXKL3c%DR2-ua{OHaN^RtvD;FTZVHCOet9OVcT
zQOK1N^n_)rQD&w$7`&|rJpPlo9amUCPYt1;Ms=cUIq2L>**h9-L}rNb@!S6e$8&IA
zXzZG4VA@o)U$1GQT)Uy4<TX0yA{%Uu;#?JS){^9L2(RJ!M<yLS2@G+~x28r05zoCK
zis%&w+Q|-TIyQ+E2r&V`P@jn$>~t_jatX%_hPebA5RsA&paQIOYs^2MUrFyEs&?>A
zYA5WrQ9;sH#VgUfn)(gbuVKe0pPJp`-NI2n^WQ}c69~u*E7NO==7C+)w?*B}2lDpY
z!Z|aI%vApX120`AXPvPMy>46lO}@MU>btKQ>^beJ6fBC)Q&LfCP7vL_swch&iD8F4
zyI!NHz+psQ`X8dxf&NPw=Or%IZZW<5Z113V0`ILAxv*)dIjbqOkvQ;D2qg#?*F7P4
zC}`TlaXLq6tKgm}OG!`_WaPty$cY0qCXJ}YifPSNpg68n67=2|KT6OV!`TFf3m_4Y
zWJimBglJ|$>06#p4@OLtA9q|y2(zn;0~nyE9oUVAzLauoWLD|#WCez(!?U!f&vAt}
z?#%?3?gs7j3ON7Q$rNY8>=+vH%0n*1ysxt90ssMX_Y=OZ?;79ugNe9P&EVYB0-9Pj
zlK?;Ax#4j^X)pb8*OCHAdkJ<uqs^;?faazcTs@azp^crI(;{%iwgrB>o8}J^i>jI)
zKQw@HSt&Asu%B>8=m_Qc*2;0XUXO3xPe~I{-Wlm=t|F*)fYB_wZ;;UzM&l_$6-Kf<
zxWTlw5bl=aGD#zoqr{YJJnU;IB`<c@-b)EH8B<QnThd7K-AY!hhJD5+{GhBb`VrN(
zLOVNhU0B}(E9tGtE6VHcV$#cP9#C`-+#-3CM(%`<pIF#he`@J*;3J4M&b3YQ!QBcV
zZdT4n)E(`-16|R7iG)jGi+H>J7WZ>BCs-*X40odVcmhr^hQ=5DFKL;^31E;>9Wn?8
z6*dQF^#xl{1&XCHxT19WMroIF=)>$M%bG+ty;a}L*VK-C5nZ~@rsuPp)|o3g7@ATv
zz#c0V2T<Wr`B0CJT1>~Wl@Jgas^0F*$<v*NLM{3d0#P^m2}|z6ljN?EA7n?#>vw{m
z_}9y-;gH}E=<=**o+79wW17QCM!V2Zudhd@@LZPR{E|vEx)y0be8%wz82ovpf2jb$
zD$T^G5HCgrHxA6c9AAz0<+W`u2ltnz5apoBIc#9m5D8IuMhK}UOKD_t>p~H!Cnvpt
zswWXZWeq*{d&o{XT;D@40zw_b9yL<9eYnXB2K+}rJ|Y}_aJ*B%`%an47U%K=$?8#8
z9&0T~9dx%<Zvm=&Y}5pe=z|`}H;FTOFUPlheLe9iF>1sqYhE0*&-cTW?5S^Tsjhy}
zngj|HmB!>stc~ST`>-RT3sYo{1I3(}=lgSrW*t_VM{s0D0R707kM8G~6-E83wwFS~
zt4{Ra9#uj!E*I358q9u$uE6it4(rr8SY@~krKiP{4|Em_yXrMsgng-e6@fq)K@ho-
zC?GmS?Qj7~5bnVx0ttV=-SKElEY(?C31zA*?g)fp20q;oPZE?^R6*B7xEQ-<s26Ne
z<xc1OEoZz6X%vFMO8oxNsMh>at#|R)Cpk5Jku8C(#Z9oxw-97PS30Z*AR_LjC27Qq
zGEPLn<^sv(rx>4kKL;oE%mh3$$KI-$nC(d%20X>R(+MADYin>pt!*jz6SL)RHYg=k
zk)1aa+?G!k{2Ksp2xF#q@+1rqqP)RRMFtTv#vk&Vly?_?@u8bkYMCSX_Xi5*s<ex}
zX57YwFPaDh?!QA+DWq_;pZf#3aHtNj-+j)t#@UbzP^YN9#IhxWs6ql;!-SQ`Lh%^+
z$cE$%pt{Mtn8rM*<U&LhE)MD83S2#Wj2OM)Q_v}eZrd|#avLyK)1aP);m45wWI4{Q
z^Sd1Xl(Rcy<7r-3U8X+EAozFk4~d+Qx(&5q0YsgXL`J|@-NK}Y(SK^gM3xRP3RE%C
zw8yfu7D)3#Bo`;Lu*-2P-%VJ3LR0PXPuHY+Lh;oGtGnu!u8|(*p&x&VQ+1M;s0zoY
zM=*IjY}6*Ciu{0&>UZKqI<*J%+b~!hoaD6-0~lP7`C?s%KslRQS1O{nBFXYFS-_VA
zOD8!6n{6|wgoznlNIk&u%N>8n+ChtlBZpo4m-8{+pA#2KBKBOJ-DjX*fU#EXJ3PQo
zB8f<@<k1oXgOlA@p+MiQw4TEwM~$U;)?qmt1ab_uZh5AmmFdbj*LSx>3nGrI5bCE<
zvXwi7?q-L%K3=RIJoiJ=IE_qz#}b@-rGWojb-D1D=?ywq4TR7nQG15pNz4wKl5o8-
z^&fgLZ2h67lC)0_>zSLzF70prz2#OaB>4~cGQTWsvO=&Yiy;cQ^lobKIz}Wt=&xBk
zW9Lc6#n96qka3Fbqiw0sycOVXqmL*p;FyAsw@G3@jc+tvJU`3Nhf^A2gp&JqnC-Ro
zhqH1uG@{&Dv~TEyo`tq1j}5VFlpe*8S#K>-;i=PqDD|W!D$|aIwG|-jT8CKu6=8!a
z=nf$0K-FjFm`_JAWE>-AYkIFO4x5F|a^C>S6#k~bHmW;H?^ABJi0EH0gldWN$HH#1
zA#97ArEY$KG&WnEM=K^5_45tIHlq>GwdvwO0*z)>JsqdRerp&9DS|g;KV&<L(gzJs
zc|dpFKM_P#wqk&waykz@8Kvm}HYP!K3kD2w!OsUE=I6?^Z&MWjON-_4yfAL1Pov(k
zz(l-%?5=YXfyrx&pSmej$Goi%EITd$%{#H>xguT!uB-6#LZnz47<If|`f;m1ZLWwj
zq}cDM0=Lm0u4=(z<JjvO((FFU6m9G)cl_`js1`e;A_gGeLT=axlJLUqL=lme+w%=(
zfm&^!(<bs|<4W>Fp!*8Y0QXO4#^1UxbRF-uKlsir&ZS@Y)10l>O`QLn$i?78?97as
zg$sj$pA8x9HpOX}MB!vll0zIUP#z497PigU5@~Ndwiw4Xp~EV4XltBMLVuHMO&4|&
z;UTk08J6-w=VwKLaq=o3{9^+mpZ902_&}V+3L#ZBb7MuNSt5x|obk3k=y=*>9M@U(
zK*>4;3jE^ZW&w<T$;{Br@M9fQpb@0k>J`Ns%Rn}>(5ATspaR4MXQ>0MAt3H47q?l?
z!r)dJ=w`&p&^9U_zyNf+7iVrZL95ieNn2Bvt5imE!v5ar2Y&mOp{kxR8GHyg>jY5Z
zaVBk_H!W7|XLljD@l}DcaW(TVyDyC^?-!LaQ;#6VL`)Zw&e~1@qe_@mMnb&A{37=(
zH>p!S2qKh<M7u1@uX^Oc5*`yiiy27?)Uj(hVLb}uNfG&NR|&*=<|y}PU9>4_glOJz
z0F?D+opi}AypS(-U7<qcvk(4lO@{|}qhV6_P)LheT~;z9fab6bI+Bj=D$foH@%HP*
z0b#pZEa9p@5c>NCKEXcutJ7-4n`A}Xwpy|#TBiikn^%h68%{iFNvPX^+MAr&c(QDS
zB2^3I0#bQ85}!%Z(gZ+)dfh?M8PaCo|34{8)Jqk<G$m^b8;}iHOzVEsOh|iB3(vB?
z9crTUAnYPV_vVX6PzWtpKj@CBn{;HntIgMI6di~Ve^~awdpSm(>GW4Wfl%R_!ITZx
zm0ZHRounUJ5X#o`S{$mJPJj5XB_PIqb}{l~m9X(qPt_h~*XjFjsW756IkDV~Pd<M#
zH(m=g*i}AMn&uWcP5(?c*?+_OGa2bNu0I|djzqv=IcfgBkV>Jsq$1rgD*9F@Jo{8k
z4#wk&vZzx(m-kxD*K<LDZyqi<=H2Q;<;My+A~9^7+!SZ@6NZt#KOy0e_Vp)X6uw8=
zyrA%z5klC${f$Z1GG>L%%zdauep6nRTN5OWq1*vJ<>{q~+r5Tr7_2g#Nd@<cI<7Zz
zZNwCnlpnX3C-W}ko@9hj@MOR5AA`vCA;;OnyJt=3nGXh8aqux{H=sj0VvFas;h2?U
z<Yt7A%c>sOM7fKOTT_ISKqamOt5uQKFve$@KeZ9uNvdo`9X%TkOGUmhZpEZ0aW#li
zO)%0qUd+o>=w~}2lnLeAbhB%<<~ik+PZv?b2)*e)_N28Yp*-+3$X{=gl%hDCGX7!s
zs-J-pMCc_B&_xO<v#sAZBA1pR&M?~gY6uH5d+JZ-%A##2Ehc=AiB>XcQ1a(VNzk<p
z3jB-Wy#CFYW~<_P(T&Kn=sjC_Z#Q}E_gh3eA}NA057y0i(B@Kujlls67rOPLEk*NO
znsn}5TUUYDg$AuFY+Fi{8k||2FVeFJgJfpu?Hhv@(KoiRA>4I0=UW>!*|Lnetan7W
zVN=go7M;i`&?&g@)90lwkHn>U8=5!d7ei`aJw_T8q0=D`y}FowB|?lVmSN<)dGs%n
z3&Erx-={{l*UNy${L#@vXWyu^l?E2qV*u(k_kvTYIcCkgq1Zw!@5<dN*uh2Y9^*|m
zcnFWo+pDm1gwuax#ptIPSZ08(b1ENc<NRlxO_J+@e^_cH%xS~2tG7L!WIP2g|Fx$_
zWnOIm%ljRyXDo7ZI4{wOcCiT%Q#!FyxeuuJw;w$=mk4tdhR7?qvt+PP{FdQM3}}=~
zZ6@4%Xg)(*P>NP(n;#6xM>}Q#to_!6o8d5PdA5<$EX|1-T}d`T>dDSo%W9xLDL?T$
z2%QItV=)y{Wi1lcwIfq$P&!-}s#0?2Pfylx7)GsFBiX30t?ycq#ug9z#;LTAcfSe!
z!1NkF;EErF^{coi;-`<6*@)!}+vPr!*V2e1i=P3$P`7M+N}^vv4CFEXRI?ZB?*js~
zGo#r@T!S7d5oz76ZY?Y%7q(t&gZzmQref!4kT3R~g{D+GdF;LgmCs%O$TVs4keN==
z?Y{4ZN?_qqGDapAx_w;l^|ia#BlSKr^I;=Zv;b3jL<zqRkhQUtC4*8IoMJpv-LbZV
z=#XW`g97FOq+OCTU_LxZ?ZZtOy_pF<d*%K;7WNqFNgHR7c<W;RlZ_Ze1cA|i6<o>p
z?}K9f7IlIO;+w`wHm{5tv&jMd$)aE{TY~}e0#b}|zKz@<?xnZ3<r7dX0R#;d3oT>u
z#Ngs*i}xsRD0Y{-W<A<h#E>xi7@S4m)lmU5d&u*`B%kf483d^V=OZYa1)MRGrm75j
ziUtDJpiXK3Vhas}#^A=4Ac60j3SNbYe}oDF-<FB0+3dVL2;girap#afOP-FWR7CgK
z4({r#;HZX%K+k}w=_?V4T;6jCQpjke>PAVT3kdNlCNbPeguRz0CI#7>7+`m_+69)-
zo*Y0^EK?WzG<8HG<VS$1d%X!VtAuir9~-Zru;sey6EpeP?h8G22zhPEh3z~BB?xFe
zJewx8-%Y|=M2D@Cb0dC~TYD;<aZtaG&VVM{ruUN7OJMvZR&0hB<kMs8ns2#$ewE|2
zyE9~o8L!(?<fUCYXGM^>BXa-HC6n|@H+CiO4TqvlR?|OGH6ZTY<bD~H%Xv)&;0Q<&
z;@x%@pL}b1h&V{nC00&b)7rwcPJN_g%{KJ7#Y3xM=4!l?G9QXgkeke?s)@yo$S)x(
zs?_KZxML+V6W@^na*OQK-l<80o;tl?MAQ*QR8r*ar>wC$GsTJG=o5%z=pLy=>fJH3
z<J9P7X$>lOZ-DfvbZquVjYw+`Fl>yvQtPc_GVfDRGf=N><?nGL$a#6=i^l^8RgE}D
zA7$jSy+hv+?jgkvn>|p7oU9phuL8aHQ0=U;SxR?&Mit7SDTh22_bm0PEK};0Ww6(F
z5lI*V5fPd_HxhmqY7NSZ3CgzB%YiAFgHMx#4h%A-4w#Vt(-BoJI?!6Jmh{9cxUV4_
z${H1kljp7J4)E@UrFK0}*}!UeWr(M}Jf$#TaJ$rv&n(ymPb(j)W+VGUUH$9a4F6)0
zYiYl2PZA!VsVJRorZiV95Fo&#XNxXV2C(yd>D_`g#hqn38%sC3ON(~FiR82upUKYu
zcJnHvGNRV6Ol@GbkfEixasD?wIb%oPAPgcZLHsVTmOc)Y>?L>eN$lyu>JPw7WK}{K
z>>-haCExOs$w{^TfwAme5Ya-|UE#Jl4$L#v_`cz;p|;)KW5099DN#obUx#afYh@tL
zD`NSZN8Dn62Fq%IL5XsqUyBYR^Ua5E1(@t+Uc@{QUa;aDp*_XF7*mc;04r`I?=Ujh
z9SewfFsN+%@J2M<b5VLV&h>C?@$;a^rNoXY>jL?ePx5g^fPSmUaFml10{(;H5J)22
zY@9Xu<Y=L6KsfeRq2`cme81+1g+bSErYnHX2QgHc2Lp@y=T_&VBzg(<R^44Ou)fH<
zlqt_DHTT?iB;mdz#B)la1*Io+D%@#<N~gvx03&<H-TO~kbSx(vh|i3B=~NXBTRwh+
zu=_!o<-Vf!*OOsz?Rd}NoQmt*rvX6eGIzaOKf)9BdNxW4VO-Tqs$Vo*mt0vXi@ww$
zI(N`p02!Mm5l{!e>LFS;y&WXW*qN|72$^ruBPy_JMd<&8*+Ev{T(t=hVPf_rEucw^
z3AQG$^T#J3kxt`Ik+;B_Y$x0yXn6QVevt;NeUfIax0db8UCX^WV;c$vk)3aTz#K|C
z-OQ9NTpt|2RiaI*SWE)EB5MZ^c7zy{n}#m&Uc|OaBNYKc`z~hj!yR))pl69QP+d>|
zSIqEb)NTDSi~3Nw3D2(8+tvW7KbCrJnxQMZx6M#`6;)Z`Uz}jN4oxD5I1098amsgM
zwfWHJS?wZ(mO0gHL$n(xb>s%p%%>ZtrD*&y7tBiSk6fh}kbyoo6t+g)RskLvSQd;S
z`4i``TVYaXDg~V$!3OGIx~WB7S7+di)9K)YGEhVW@Yrw(In*PiY!!uAc>y3m11d&h
zCqk$UCqq8z{7~FCj315rmq1h`TvJ~#HQT&frMXeZgx-fH@kARQo;L4w2z_%xx8xm7
zpT3W4df`ij#GWy=kh&KtTbkQ0&Dn?rZEx-Fvf7|&6jazZ&1e+8Hihadg(H@s$LNb)
z1B}WlqMjfP&$RQIbBpilGfXOe%*2N*641}2oSR(QPKNN00Em$ku`E<e-N-GS>k}PK
zjTXS#HA{^fZ1GfaRMd;B?l9<ymF+g{26TwS05d?$zvpL<Wa9$LBnICW_|RiFQtU2_
zWga_{;S#3_h^#6a3r6t|hq}zIYAA<{HI$xa3mrU^Wvl=r-AWul5-kO%rnLFQe!3$b
z__us>TWcreU~+2zv4DJ33y*l8j;G5AvxCO%$r5N*Id0$#wX{l<jdHg6G4~)#;?}Tv
zYTVQgKANWN?lPJ6ERG&=c|yz}=VK&XNxd9yi_ei>|0k=s2V2I?4e~wNV~g&^`dNGP
z0#7XsS-<eC1l`?WMRCDP*$^TXO^v<tB&u>vW_0}$y+y86cTD}p1ng>aAF~J3-B|Gu
z_$@C;qZJ>uQHuxTn^dE?cch#!eE>7@LsFLb^ph$RqVYZ>HdSrZFh=EE7S&u4zlbgK
zTq6(7%0v}Ry0==U{}<hfF)1F$VVjiY_q3B0MdY&A4LA0UIU1->$_W!wE2a=ik<vyG
zo5y}#SzviZdPP_u=qyO`3tx-#!ogWr4$3a}N-u9$8*HaFSkxJ94DNI+YvY|fmwA=@
zsFw(5o^+k;`vY2x`0yNo_kbD&g+xOw0el*;Ael}mpcvHS@suyBpd&o(TEl*x!deWB
zPW)~UF#}oqC7%0jWD=|MOsub&xDJh=doXD#=uzg*AiOn({Ft`E{ak0aic@XFj|lFz
z^U|@U9SwNcr;YHsjwb-)Spl+gzxOvu!$Q72rDrm(W*FUN)%q7pUr;o9Dr*P<sbf9)
z^F!Tr*HZy8kkFkrg9VP1w}1W<3(mytu52lT%hwCN%6vt$95SL{>v%19x;YL637Thd
zD1?l9&J6YwniDcLduhSK1u#E_GDcrJSPc3Gc@*KXYU4;_gid$)GzdG!y2!rI$bD8G
z^-t4i9XK#?>F@EOldc{F6QOA!{(`$5u}YA8W(jd-0#DmYFyzk$(;fW-G6!NM$NXt>
zheD-m-_m)Z>)8<2YFsn<LX~mQr%)`wU62j}^u~VqeoU&B*;zvUQos$QJ4%{oN!alN
zfw-_1@EPvOcFM+xg>j5u8Wrxoov=(#jSFb?Z)`sZ8YM;+Hba^R#Jwr`^nV-2=@$1U
zgJ)`%Pycr%tUNMpI`Z<{|5g<uZ4eCnLC-+4jP>CFT6&OTxL>Gn-v#I<^HN|`?>|z}
zeQWby#u55ys%-qhM}RaMw)T<UQ8UlR0bSEKNRwWYBCwk@^SCO|$V;dQk~^r<n4g3@
zn)5+cQw(dmlkQ?VY2kG>cpOWIC)Uju9a=4jOnEuA0W#n4jEz(76z2a!m_u6XYAe`)
zHi<MOy*S1Z>JimtOBvTKU6~Z)B+{MHzWkLxYvuS2Z!@^{&CkWsVya^xq%v~i8}aOj
zJ1OGdHUj={iC;dqML9gJgtMWLyfMZ93&B?LhcCvSWSKxb^18_@1*JLU`0)Kqn_nr<
zFlPXh2)|3osNBNp@%NKPXJ_EgRjT2Vi;U`cIJGbZQc(h({#CwCU~E>!Y$*QIxngWW
zu@!-osHUqcdN11^lW7k(&K=q4ZRFJ-v>gQQ7{+g_I!U1pFl@<Xx&WZJ)Po!^>E0*x
z{5ZH{!L9o*{@6K#(&EFmz5K7;V(f}_B}De+&?rOkZPr{@+xdga>4U%QE2Tqb+b2F|
z00uvrb(cb})WNv{LgGar*?g@Z3tSaRP=?~%cfRHtf2NV2lk||B9i3mHo0MEGKRL%V
z^kG4dtF!I4R`6#0OCs&WUwE46k@kUG8CUos25>5p9!?aNbLlSb-q|DFw%q*~Csi~j
zUaurvl%@|21{sPJTXhLB@0Iry70?g(n1dCDbCj<kCk%{R-I;&GpeIWLK8%dt>>B>N
z1wlJXTiG;rpM1B|id!&N;zaVHmzxhO*cX2h^RcyNzd<drjxLC!92U|V%*w2tFD*Fg
z?Sq3guD;?pp=@OvHqJcmG2pSgk)aqDHh3Xn7$`Fq{!fzpGv4U5y}<(zb$|j0ejH4Z
z$Ib3;1Oe`(DXsCe_ftrLSe`b%Oqw;5vco4r21mYqsw~kLazQ<A3X#VLA8-HPeG+#W
zNp2@djmU|F_O|dnfeyQ~bP(QC^72W8rRia*lA(=v?3kouE4$=zAMzb5b67iO<!9M#
z@-#DF191}u=MQ#^eQg=(BtzZQ^iFlK+H#vSq<$d{kb|vg2?5seH_k2q2Quf9Ard10
z%%2%6^?vh~T|V!+sMS%R?;5pf5dTjKDhJ@>AdTg9gOtNW>?`oEpr6t-tqs+7Fyo3B
zoSmeB$<n^TUS-B6Q>=~y+uj=>dfT>DSij*L2xpLK;*+f2|0trxxRrgDWcsQFJU9v^
zs-LO-lqdRl-#zc+5AG(>AKduWW3^Y}BTCqnh6br)WB?7s8<46E^T}*?BuKXf-gTa&
zs<DAL1!9yRt^cu_A(^5k7c5z?j_IaKfi%o6$X%CH;)Wv?z6w@NA^C`LLn3ro?+#(G
zk*)egG+;4dp?75{A}=834;{p5Kd9$U(7$H+1{U=^?RDGd$LywM%+a?5oT}1gGcVdC
z)K;MuQ-eug2U5>`q=+5n{xzUIey3sknZm39+(kYn49@RG02|0iynV2A=Nu&YYZnpf
zRnHK)FsM`LN!4x24*Z_sf}#`okdP)W^Pdgpf6($pgXNmX9$Zd<HEe(tHQ}?JgDrE)
zQLg*j3UO1^DbHkd&#DxLBLDR!_pR{5(t2giuRlcjKw!Gowf7O}U}eHPTUg=R^FRaW
z_;&hh3N1y6eO%(6h}@d;PXBaSTi?XQ4%KF;#i}0mgV?}#B=$?2t(2QU%(9Hh_*?rt
z3%$8uIp`(NGYCuN^;hxM`wk+AY_*|L!~523EXV|!xIp+R?*GMjvudCpHOqn(t0PKA
z|H#6fC0>u7kY!7zUyog`JS--C?5o+4Em1*)QeH{qk4#Y0a$*vSQC!~lAERzA5FOmr
zJg#zxKRIH)3J+~kJved3{cy$~)j3a~uJhd?{EQ`M>meJM^>fTEG+3Ypj#5^o5KHEo
zOt5-eQIF+*COeFC0~{-Sql5aVijVaT6PG`*tTg4!5}z6s6NNaW;NqHn8*Up_8ZE9Y
z&I~NQ^QtW>?Hd4Ij+;e*{*%TVDePfEB0sW=>Zi(g?3Mf6Zki$uVOyRXTSMe@=QwrH
zy&ZsTN`bC!b|&?0QEu${nDMfI?E6>MN^ITVvA0GrN?xUfYyFPWF#5<V7y3IHQE&`R
zX5Y}$LGk%|LN~5?^ZyYgt=u8E+iE8~Z^t-0(qWAY`>8kn;868vFlh&0VBgps>s#iD
z6r#aN#Y`I26^>7)pX&gHOZo-^u>LeIhPLjL4I5)t*V<Ia|MiOCGs^0Rs?@IijTK~}
zM>lhuC7ZI)>fMKc^PU7fC)X$1!Cn66>J30GJdGn&W|d?>Wv0^sQxpzk1+o;n;gZ<w
z5xN=jUJT^OTeck_yMq=IeuDIEWs15O`|5MDp_nbdUN8$?<cNJu-PCwa9JMcZ$kr@p
z(eA>)pS?|%+3I@dh0LaI22Kz|nd~_Z)}I~{3M@k`WIMnMhZ~CrXt+6Hlj!m2Jez-K
zBP&-qBO-J&h#1<CXS`)3F~Zzyj^73@d?FV9_jc3TZ7rSX-z!JZm8O=c6e^$g2T;PB
zkLO`l)s}Br$t=|6goluX5a&^0R@SQWdjI6%pU+f#0>SfR7V1MR(i9&PgQd#AIdszS
z>UxC2Q3Qee_-1z&Qy8|{3q0SDxP36C)@C|VZQ@cSHY~DSe1R81h61(eC*Oqq7N~2e
zO8~05F1>%_Yqf=<7d}>ATT5#-HPVcs5X$eKr{!>V@_^7Sdc>UJu@1@T0Ceij*^YI}
z+oG=1nP32y{F4<4-oeSaP4TuUfpJCJ_Q_t7IujWeKFJK>z(e2|nNlG;Qbj3wRFYSZ
zdTxCuH7-&LP<ywo5Yb#pPNnI-YA}?IQ9DF7<QWGOfr?oNzHN-)2UKv0wxx6z{tp8%
zeuq1y*$4jH2qjCxMWzoOIGf*|HnX?FSkBM39k$x__>0Kl#4Z!bYl##E&@v*tYoGD^
z=VmEd1KXiEoUm2uNKQ`?oG&}}<-7LvKxN%T$t!?tA0ae(tM&VX)K^;@MNHrS`U*ii
zO=^)wZ~YWmwur?yjF3cgH)7s#Z5!lccu{cEpieFVW$&EEip+BiTIlQjt-`p^ywJJH
zOh2rt`}RwxhqyZcwqHI#+jKygt^s3mv*U|67^qW*fpN<|B2Ycf1>O_OmcCs7f<s_(
z^=s|u3Y?SHR1R~G5X4##^TM8Wka}?FH^LC<juQp&U9CTlv2G*}zq+z#;thAKor?$9
zKXxX{AmbWCn))%1RZ=fdu0-Qo@F3eEaDDF8*h(lyELcm>H(9Rhlx$>Nnn_W^?TBc%
zGfJBIslFduhAC@JuH$lA^s1j&b-qhp{<)qE`Gsy3=+4_HhYg1o0mBjH{aCvdA~_hr
zzxGg^k;JmMYp3$_WN}hiu~0c-Ux;LsNtY&+(<1klnp&$JCE<~h>NZ&htzKjdb-@yd
zw4-z_nMgm4eR8hA>)g>2BvGH6@s3gT>jnS)|Ks|1DbvrSLFkW0ieXBbGq@k=UOgI$
zXTOdXGlWmBaLSR}tNQxy-xH^z-CD3LY&%jO=>OWqq821v*ob%qcC%~ycY0G*V+lTQ
z-^qH;O-6Sh!OKgTyy!zHB}@`Jm$_IVPr2}_`*FO=yb#%+@iRvzP)1gSMwr(vg!0FG
z%UZn&ZqkyYIV(6RD5qxc-?W)0k`g6yBa>a>8kgBBy`&7N;RBut@o9~|T8Y~ehE+*%
z%hproYsh!Ne^<J1htY4L$mX6{KD5T|0EsK<gtr8HC2I3NnrvS~r;uDcGuo|?;^At$
z8F{bljz!x-AwpQDxs!lfXojM<f+P4Zd#vwg2K_v@YOjvAS6_6U|2^MNmZ1HgKr|D}
zPq9b2x~ICkaIA(-Kti_Ff@2*$p{QQM3<GqMiKr{N9sS?Y_65mkTaKJYR9-c7rG5y;
z$G-3&r{2#@I02EOx}jNv-b5W6-GZoorfn7OyFG08O`TIqe{^__qbNWJHBpt?i+w7@
zrGb%pMH*G}Yz5WWzI_F(?>i_F0@R+`X6~nelFua<dKL`nVqJqKZMThSnAN5t_7(mr
z6&hYKyclb1E^&!tj~dIyOI<PAGE+)yJw^>ink#6`Q9O)OrUUqbKcir)eVrc&hf|rH
zQ|ZjnAQT}JW2Hg=I+1Z0#0s=L3}SC`-H>w&GN_A5r9)Kb$j5EToc+=O%3#($ux)63
zDR8x4MpE7IE5moTH5$uO#NpbhYor!`<S;dW+C8Z<?7oN;S#FQGCg%Z|yffH;zTa^;
z&)3Ushd1AO%@N#ls6_dg9YA7IRnXAVk#hwcRhj~hRwv3KpQ0HoWA0o~_TK<+a`Msh
zP8xxoF-Od;o+zQHJ=3xy1=98pQHYV-6^L){hry-VNJDQ@KHKA$sdJv@{1o!QEJf-c
z7er|9{5bxlazLvLhWkTMz$#V^6Oi!X+KN>73!PGoJ>gsrFaB-EP~+fJ%SEWW{f!2z
zL%)8x<K8Bgn~?E0t~BRQ&DZfkuD@Peij&G^+mCosYA0}k^>MK!n=%SY5+FgjJ7C}q
zBi4eq#VOY=M_J%gyB^IZ6q*8Rj%acsOaT^Z`()A7gIUktCRVV30=q^2LpH@*`&|jQ
ze_-;+-&Guj;9tHjAFfRud@#zml0ic4pb_=j3DzTNkOfm9Hy2#b=B2ck{g1uW{G$(=
zLzOH}znpm8MMh^ZDBgne<&l}c+R!UewLWv7YH2XQ@Iti0n*#eZ%C6oJ$$Yzz{sp!d
zvu<Meh90ZJEiE>nDhYWlJm`CHp+V!}XD???itXTz=qa*QhUf5WzwHTXg|0gcj*^~i
zm{CJ3woJDM{iSedJp@u~K2xLqoeS8Y0c*~!nnOsHZi2`5;CLVv51RGCR`MCy^&nZ{
z{u<t(0rY<^`RxA6EUXMbDZK9HR3Xf4r2xHWGEbrIXRJM6LDM}G0<>kLdk%$bu8q9_
zc%@rT+dP_JM<B_%TV|Nu3W?}97bGM1+yLC;a0C30K|lpR+gxpHZ{cZDld6UZDg%yj
zyzh_eT(!0+4=QUd&B>C#D32N{kY0AX)kkL^=kFwkn)rtMot(>-I!Pfh4Im71-nnpj
z6iSEruvljpDu0g9`_%hQH;zQqqD(7X1K`qpn_)jBBbkq7o(6(yPR6uGU`P9sM-SG-
zJS4~$%P@JLCQp&LnAwp88V){uWByM6(oY~!!JPF#c0c+}4KYr$lCx9!=G3H1bQUS#
z2;3otQfX<0fR(GuFeA_v>S&aQTfh?@5i9YCK?`VutQK0hK)YrsGC23=d*T)K&eETq
z=0K$6yyD={(NU&*7}?MDY`&M&+{vNml7iM-!%Q2<X-u`i$;BaK9MC<S)}fWEH%v3=
z8XHPzS<}#1dX|fIX}#qCUT_?fb3S_4tAj)FU<IS01px?o9hE5h2X@t$<%2wPt7xY6
zz*t{E*dNcve+_u)@~`aoUwWjTAXb*=nH>f&BBri-`NRGSY3-$sRZ+=Hma!!j5vH>I
z5^hivL{Zxz=b|O7A1eSk%uvm>q+{CA37c}7N>HlW!n}VvbnDQ8^?&)78;)f<5uQd?
z!Cit(<b(C>ALX@gN2`UMB9SgBsB}7wJeUEI(w>Ydm)t@@<ia;8vU5~tb-(kk!6HzZ
zzTG7E0aMp-+{b>_zldS@3`Vw`K=PUf8dL;6({LFHJctBi1JP2ni8|ekD8-51yqCr=
zOMpj}?=uhAMHF@;%S%`ML;HFxr+6#z#k+tq1eYY{<AMy#@xDCb|2WlbqRft(VSXvq
zkRj+tY`efCIT}k~X8qfGy%Xs^Kp^k{n8Nt(u3~YnF4HWY`gudoDpQvEdl`@tgaeA-
znG`3}5C3*&>hEZECS3=89mF9u2hu>x(P&lj9s>ITu;raHZXEXq+l4J4N=OVUy)&1k
zOUzj!#@_p&TEX8M#<rk^`Ve=2toR*qfPvmCCRAVTpAl#0BsF1Xd29@fbvr8wY5+aZ
z7kDJ{Nq#=!6(n2Nu=|HKw(+_MM3e3v&AdrRkOp1xso(-vEJN7tqPQE!|6Qm+%&2n5
z^d#9X0OW8Qb9Sk`ttF)X?hWj&RI@m<<b-erfVC!t(`Z9(VUcb1%NhZImwWg@nD2Df
zn*V4kW{M;y@7@pOr2?vCZPaOLMOAbo<yl;7uBcDzcNA=)TY?So!ZVH!hUqu&KMp9Z
zRk&&Trp&jk>(CGaI6rW#Q@zBzh)|!l>q)_piE@Tj9Y2l}nBGy#74df%*7HkvEr~)A
zwr1YxaFP1I0)K*7DheIU>{7j5En^OS%~-cc<~HrpE!Oxld$^;o1;0v1d$L#lJ(W&?
zq|4^nRh-9;YkUyaTJHM62B_H0^@cnZ@rU;X=Yfw#Nd*kCLyR__A*`#G`up?fL18hl
zH3^pMiDG_D1Ut(XG2tuSx+pRN`^@m;w^bioe+a*i#tE)vYl%A1t$i(ZTyf16ux1n0
zDms0To>$z#S-(Rl-7m?U7bT}*B4HUTo~0#!$D^zz?kX>{ZybWi<`usomsCV&HlM+d
z7BwiBd-c&aFCdTQW=Z_*T$3Vn-zgr2GQ_0a*C8Xyb0{r2#6)>QLB#v0!)|d^ma(GD
zJy5J4)|3Dm<$3IniOmk_o*?1lU+C(^10DWc2EHX}vV%cSyoV0p8JADDC$!^mb3g?`
zcE>QQBxe1&AI04E>o@M*=f;Te{FkhK|0CwXGCQ>ZhFFZG>Nf|Vh`Rj1`{0~FczLzI
z_036}hwkO;?LpaNk8@e#wC?eBqznag(w{I!p)Fk>5&@D-=-5WW_sY)Y2DnRE2Ya*d
z|M7<}qLoID5Ow3$6ZUXcL5*EB$sum6`qm{d_r$%K%bmRd3#)NbX%Y{rEpE#yMG(Z^
z;JC4GZ*)C=c}ba=-;HIOVq*sbGl5O-LoY=;FU=#3*mol=?Ea|+=lh`pAaQ(geqOZY
z)T8)+_b$L0Mz3>gPvCU{5F8dxYx_UmFY3gt{|GcCpNS6)b<AiDe>#%Y4z1jKJ^fiq
z8wm}guH0g%M_PRuU@OL+z}z86{rPAda-7Vahm7~8k@{oUKb(eZ`+YVvEo_21A0j;V
zzdHI26z+K7e^mTG*y>CMqBJq>bAG*elGz~A#j<{L*vD`dhCkhUZ77U1?lUv59nH`V
zYx`OMGr~CtzOawSLL@<U1_0>gw_g9{5#B{tEtgO|f41}Y96W(S3Dr}^@vr{$5BhEo
zsa)-8#|^b{q4;&X$I4X34JSMNid6VVy-FKSQ}~e<DwmVU2A|vw5X=adn8JOVdAcHJ
z0SnnvEWNwX?yzlj1BdD(MK-u8BiqGn8im`rOK`;qGByE~9N7#chr2NWbGRkIy<?Uv
zgR%C-@B4dZqG`%_M>;MuzN!)M1!49p7m5zL1$h-vp^T1{kPGKzhR;ZDQ;z)wlLz-n
zGpdK4@{l5x78jLPVB}`+ByjNU%XzzV1z>+TbGhab8i+>!qw{nV@yqRF^oID4CKORr
zY6^71XHB$6RcPmD<3=f_Qc%xA8PYZ6qxRBXXw%y?$LBrhzDkOu$5u>PXD-j|PmLmH
z|BsrhQz9i&^<MUPpI_133z1iC{8Z_gPi5=oSTdV$Cf$p1gpd<Q>y-oU;rAUDQo`S%
zC}?;3mRHC9`OisW+`wY|_J>nok6MG}8n4Y##-jjt=VRBd_AQj)jAw<@U|XIOggLN6
z{(zfv+)<Qmy>?+o3e(gd2lm2XWFZbj#H&xMW5#l^S*7+)JH%Hq>rskt-vvm#7i~+H
z)CVE)*mY1_vM%>#g2ctn(p1Df=Dt9VkTd09o$)^RSa{14sU@@f(&)<bfF9loB6&{&
zfsyO6qzX)CrSVG{SaWUkMw7f&DC&7Y5UMHVv((a;?NN?<;0pV`XVC<@LOis?2fO=9
zDlCazsFXM(RqQ+GbPY<YALGKX?yJGwMrh?9ZL*$&U2~hqyZUglA!Pq!n}v4n@=cB?
zWuP-*Vhl$kJrrVs;@%`Z*9Q%K9FF(JlIavs0_&x^70GGOFSD}+UwS>KNd>A!oVb4g
zS2v+lTXnrp5LpZxNX@5@?G8?_g-~P^TM%<RLI_`1GavmU(i&CA5!-*YID4t`DVLNe
zHeb_ZnS1sGO+%15jD+Tl&`;-Jl15aOb3HNsn{Nru0kGBnglrb7ojcn?EBRc?Fj|?|
z=J$9$noxnx=HK1ZNV|0SA~yh<S^PNq1gBaSGia*KHdQ@v27{q45iMuJ-Oa;}mw)ea
ztkd-K45ff6H*K2hCs}b8$rEX8#(ZQeih^K~qHc53(>6-_NZa9b1i+0en<fHL3=O@z
zT~dNR{5JZ;7*?@?<u+Q$OWko?suiZHBsx1JVCF$Szei21Q`#B?V9xgP?aLKB@=MaY
z1A)LLqc<bry6|-D6`qfgDuyeP4m!v02bwRoC2k=KTJx1t%FML5L6)Y;V+K1N<-`j9
zmScU43h#Yx+r|#<mq^Zm|Kwk<4y>rEr|d1`IM-^lOGugInJ!R*=O^XbOi)jIf6it?
z$fjCHxccbMJw%L3(NZ7McPNv{Y4^MgUQQzeLENg*b&*kJyD%X>@fPbimxBq`xgwAb
z?cGz@33s)yH0VtQh;?Q6*4Be>>l$u-<cu1Yu^FAO@t1D^lv4r@sr%mde^qDzZSy}G
zU&C}FWUQ=$IZol{Rfw0??Y^n4;{DMf1$*fqNtpD;(AytjAdYABU3JInJYHxs$H0HY
zVT{0HNf{zaBJ@%u@EU5U<IJ{&=ZpX{4LZYSOvJ9I@5RE+be!L#FJTL3Vps_mUU9$(
zpv`<GY?4^NZ6ZEfA-Na9Wks+?M)=%UEPswlq-Wq*HdvQrT=eiVezqBj`3OG^{;z#>
z*ut4X3f+E`^4pbs>9yBZc?+^;^|+;`-FRR(2abd*F>i?bT-E}=6UEQx(f;3bw)h}^
zi5|g$pmnR);A73gK9uv!akPs>DB^umzVO&6Dv!MSq<IL-y7t<o54WF8?@+zN`l--p
zRUZl*iAt--5!5da<mcg*9Pp9qSrS8iFdjqQSNx377i!7tvCf-#YXR|d-ryP=J+@T$
z2q6gxxE~tvV43V#wDBsG{u3bkPh=6~cE}}86&w}xgbx7nqMOh%^MY8huC>u^PEH<&
zt~KVSH4jBp;?!DF_YZQYiKGJLXw*Q}22m!EnE=RHG^^uKz%qTdSXkt)yfPOm^Gwno
zL(Tl0Qf~{8&HfYNL|p65;SRF)nq^vbh}h+D_sW-{M!kFqU$5R;!yA3yzSTHoo}B4^
zXz>G+%h(MRPDNlUo}?We9vpua(;6;|9D-+`3E+#7C}xR0e1dqaXp}%@EkQ9N%hfR?
zqoDy$U}S_h%Z(xU1wD$|PM)aD;F2CvIN8kjF1yQgCpM71tvXt_Wd>F%4GU?MjoL}L
z_#!+VPCP+&rpooF;O-6t=d%7`pV<vK=~$tzJOsLcRN1ct><r7sY_JT*S1Ksy%~maZ
zfY1x-a~LED7F}a!>NZ5P=R-M3*p9R*G-%;u_vhZIvrAw<npU{nLlM3qNr$=W3ggLr
z^fCDSVIARi3&Q41&?=)*;gb4WKNJ!ep}rOj@Ozb|S1%CvkMaR@ogiidZQv&lrAIv*
zyFT+oM{|2AIS9b47CtS7#k{;wcUTPY`6JN8aJdmu?-ULiLS1E{^qce={OaN=3EE&v
zpCUPl?cfl1C$GZexv+|%5C}4F@NB9FVBx!-(YIaiV(6aIvRHYUFtc@$w9}7H;@Q4y
zOFR7#Pas_)&-Mo|ylb3f=azAHvwLR!f2^Th9?I#Tvz#<6is%>WB;e0cK?~9{vc=!x
zbi(CE>cYU$qsok`(co@)l*y3qKNe^CB3GtGGuP&+7a)g_;^(^m4J%Wma^X_~-F*Cq
zGCNSN^<_4sxkn)jJfD#;vD@(dSzH1~rCV3a9r$qHsu;-8InG#M<xVi1Nm;MWw)(Q!
z8zLkp-$vQeoy`J4C@QFSn>3c{eB4&ru3V~-a6JM>P0yLD+cN0tUv_NHJgY4_Zp7q0
z&jC1B+7D5<aKH=AxHFMnu)u%3a3jA|q4WbxTVUvaX><~FD_*z9+{YDXIW=Gfx-$5Y
zC&IpPi(UgW1cG%!){t|Mzhh>FJ!}*K{6hrJC`K(zMsJ2O>ealsvh|gqJ|z*p?;uQ1
z;Ytu7w=C)WU%@y5_}M?hi2EeaK3u_=K1>}W^jZMUMtZ2}RWAqMhRGu9u?c7L6O9}O
z1t)iN9~@Wy8b55<3tZ{WqK#W0!X%b>8kIUUp$h-G$fr}51U}GuznE_r(YwRS0f2=Y
z{5So|YeVhA<14X{xOjFaMRODP;mEYV1}~lK$Z~#>D^s;k2d^;Tr3XJt@QowS@d!J6
zC3%LNPtg=X{uRZKkKf&rYvWN5%Hzs{dm^(1-+LCCMf0`qaFJ=FL-^K27F_7jK`qJH
z6-g#bb+fC+zIw^7VK|oEypo|kxJdJue~KTJkN90m@PGRZvMhF}f)W7l(GB;*G{nGU
zPUx*giKQJ`L?(xr*%=zR7w@m0(>lr4{qO1mS7DbIL7hojXREh5_2n_IY}Cfw?1^;K
z?6F+b16IebxK^SNLme53rJGw?{|u~n8%CHcKipFeCm5SShcn|&w4E!y$&p1<!N`de
z^nl-*u;^CSz?){G`+RWgTZ-Nf&fZ#0hVtp`uiqD}TO0>8Kry7y0H9{MjY?Ne_g>7e
z{I7kL+7ml_gr9O@=*13LO3%kVSVZ}>_(!jFp}c>^qGVD-DKukUBTbF3ct&C9?MG!v
zEQcHohsB9`i!InJwf+HqNCT@4Sq6m@c;*`fCY}$JPVq+Vv&XZn?QROUnF>4^&*6#q
zU{5sdwxWoF>9-zL52Ri0jg%z$wSBer*B9+AP@l#$BoKPW3Bgy#;`f5k^diL-!4p(X
zd3BnINd<T5$?}JIOTgcz%fJFd#Z(<d{*({;uuiYLre;mMgc%<Ix$0o`9qH&<d<NQl
zyFP4C&|fc+X{%k~a+L`5?*Dr1JGTjH@d+(%eh@UB$d!eZvsvz3KZKRWQNSQ3i7&#I
z9wykH{7V7}Bt`*H4hI_5um<nr5??U32%R9+lXRKRar#Ildjl?0ao|{TyIKxA*RUiA
z$!D)$x1N}!58vIpWl-{tvH&%R9I!1x(a-xbe6oDUxZ819#KxRP(rztf%;N`IZfgQq
z&CaM}tO%g=EsRj^X52jYZR?3;B`(?f@sem8h1!?X=C{EbPMJ^wO#6~dx?1FyG1o~?
z)q1JNY3z}l9gv(OA7cXUvT(;9;KMiT4jVU-Bzh+jG?g-2h{LHx>4GeL=P;;2gDh))
zQ!1oS>KpY%%YlxJp)y!<IIuGv{US@^+T~!+nKkf&Lnt9!DTYf>xqm14w-r(@RS&o>
zI@&dCuF43q1nvNgJV(yA6TmlBYWI1+S!0Mys{w=e!wiEJBZZUZO_jJcpP4Lit9R{2
znJ5w8@JYmMMv%^85t3Ii*2k+r@J7xpMYQ=hb5y~`9|z$hH^!@~)h?@msJBIFpFq8v
zIPgkaGuaceISAXP12aMyCYkXvSft8`1zP8@21L!!MR`)os4={NahvzilaC1tF<}+i
zf^YEJh9NotLiwFk0dp4{5UK26e?d~bF2XdnE*n%1S~5{%W&81pl9F+7=HM2%&?icl
z>)$Ihmb{=7jsP3HOJ|Al?TWqW-NZ@3$+@)(pX;>H$XUKd1rXHX#`){TQ~$fcSu2cx
zxn*=?n!3~PqY*tc%onP9fh02S16peh91plgc!(DWSYNQ@8L>}VyO|3q!H}z%rf^4+
zRt(9VA^Qkv2&r>wfjV_3`2EZ&Q9(T4D1nK*ggEYF9iMYS`4gvJ)x+SM>w_Ar(n@U2
zq~xNm)IhGYwwYww!ncJ55Sou8W;+7z4suAW0y3xG$ATZ+bLNMpA$^v>inMn!2~r6S
zIJ>-S1K%wTpy5WE@8-1KJEi@}J{hFst5;mm6;&x?OkzpJ#|N?ix!bzB;;|5b()-0=
zKlzN;9)up<f&u|pHJBgIO1O=^_{X;iN!U`yv3(^125#=XeUFUS`uTi#jQggye|lo3
z{<E}RzE4D74tTq580O$^5d!o^J}+xG-%ZefW!bQc>9a%T9>^p+#9b+(Lkwc5S#q^F
ziuH?fDs<$wT&#w-hsrc8$C4e?0kvrY8Uw1b<uS6dnZ#ECn!mU40(6D;!HSV=^7cb=
zXW5hLVf(0!*$}hIRrk@1K;SA7l=bU>SYPMdTnqn3hYR4MNBq4$9=6$N6;z3ph4r7^
z3!ZSC?D|&&{GvL@*C=`<{J!7zjT1k?I#PW7s^_Wq(5^i5qj)#WEi7lM9@1a}lxKrN
zn(-eSC46<hD?1;?G~tG8TC?zSMJsiWjOWg$SSX8FD@-YIpj9$oqF*j%m@|q$-3_a&
zD&Itoa)X2225Cj}(m-TbzQEsPv`KLVJ3b}Y_pemb-rHm`sS6AG*dtsMb*u)?eX&9}
z@DFn)Y97_dsC|1kTUBf*aJv_#YY$+phX*#7?*WY^CI_;7K{JuS#qubj#&RyR1M<3Q
z7&iQgY9+;c4VI<2a!3N2v(TOe*eX9VI>b#&O5WjG1qHga+%2SdP;dhC;X~Q_%2sa?
z<D3ZExi?5W;;3@CBkCC}wB=x#IuagDGui|3+Q;<Fu9j;InTgF|Uns`4GN$47uqI=G
zK2~PT!eStwp;s<2{69o>#OyScFw9|fe77@M{=p)BQ;Hx(0U=<$t`;Q16j(Qj@kJVj
z{?r|CH<p7|5rki0Nc$QK@dj)Iyx=(n;I16<lq3>oh+utiaIY}l#k3qv)&Ub4Bw%wp
zUqZjmxgT+>5IU&~gLk$(jjTdiAY7WZ5H_3x&aDc-SQDCJ49(_iC}zduB!`8zFmY!M
zSyJ8SjpSFdwkkr%sDnyTe4TUnIRH{{J{<)NqU`R6m+ye~CNK?piVXa9&_N0mD&}d+
z*b)>=QDQ5NrYcP~zbby_Vlp{Cv?nGH2Ysi78OmQq@n_hA!s~QHKR7dh#$!?(FE+0=
z8eX}!CByhA+SI#sW7q@i9IbX%&K_f-rY%*?SDdI&$y6h}gNmO0w~@X`>hNc@3oKXW
z42Br5^^%03Y<3#6acS7;x%G)0IEd}!Q;-Ost_)<=h2Nc0Te6cm{*V8&p1mnWP()-w
z=HRxau0Q_*|L}aU)H9FLqa~^{mHG+0U;uXy(~L3(0^F#c09ljI+OAWm^DC*TmmV@Y
z@M8)Ro5?Qb5Iua>UCl~zn(JpalCRzr%MDwDgAoOBY`C1Hl>=Hip^T-wTC0rD{c^%(
zu+`1^lFj=)jls@oFpdGjMt(fu<bv0+H5CEFA{r-jf+_{ihrboy#~1i#ccDhZatGto
zWm~7;*Z5GT;<AFa%~IM!PzZH^6^0<=Gor2x_gW0|dZq@+EbWJv1EpDzA!&fH2MXUc
zl>|tQ=lwrK0&wn{NR`{n{rU2+46YG(l@UB-Lhq71{fiZ%pW;y3ZnT-jSB}U1{gq8<
zHq1#?_*}FXb^PX}$c(>*ZtXO`u975M$Uk&-E{sJ*&9BcGtos{Q?w!av1Ac!1>s)yS
zo+*cb>z>Y1GCPQyahbhO$RktoJ-^h%i)7CX;^J@%h0t55QxD^4kCg6P7;E$Me;uH+
zCRy5d4U|$rn<FrfqNKK~Ohz=D29MAJVnRQWmQ6JjM*6Nz&7ZIbH|x^?4So~QIYlOg
zj~@C1_#WoNGtybwru-eXyE|HJJ{@tlmd)ti()z?xlx5)0R^A|&XBOM!xRdR7SjgR2
z_pLX*@97|N4h<sy4%%`<G3<HtC;R^zsz7?y5CC8?%UR7<6UMKWv;&g-14<7<FNDG(
zB{ngKHnWdR>J7ZKCgKLUY4OuIfNRv$%C~^3sscTq6!fp7Ld6i<s|vsn4hI8%XY02}
zh}e5_6dP~Qx?p!sBq^C`Ja+k$wY+u)r1~&2i4*(<*?(j4dJ9>~a}tjJc#81dYTUgT
z{<IaFb++*UJ5i9jbgQ7?^jr-AVHoh)&@sMI`)XG=*u0Gi`>F0etX3>qzcq8Uqurx;
zqAdN$`9E>KVaCd9q~sKZ!M2g6N~KJ1L3M`xZk}mcoJ}nQ^lan_AtTW;rEeWLD&D<y
zi_+0JxV#nydn@HSxKHzKjhBL;|9CmuFY7U{(v~*qfvjb|Q#>cJnL58-8dYU<deDaB
z_7>7RI2ut9k}wOi0x0D&fewYjdt$@Bj5<og^RzK+$w_?fMT>Xm=uyFW3U18QZe$pn
zBX+4p?L$ClO5KlPhFHyO0!R<{qZIf&S*QuYuGH`;iE0@k)@O1RoLvp#k<f~lRovNR
zLawE`d2g6+G<`p0-dQP*khytIZ?1Dd_Fr)t_0u#-G1huwttc>dT`Co2t}{~EzDVC)
zHKOqFQw2H{S_DTwenSlTN?jo)pKh#eWxtQ3n*vpo4Ebed-WJq2pp$sv5>Bdm)HIzq
z1<ND(;DpnEmJDq}6RQF7OT*BR<@_eViSCmU;HK$uO6*i?81K0RHINmnNK%1&l_v*E
z+Q7uu|FqLc;%x(cG?ulz0iKC}+!ZnHdcOd21lvA2*)y4J|0<ckDC;h~p&juW$EWpr
zo)dY_Dwg~f4pkXLm?TfTmzGfp-pX1?`mCMh>r4R6^np{|Bxq~-uq)APHKn7eT_RTU
zR=HIpyPPR=R0Y}Ksw51v%BY~G#?T0KZ&P1LLc_&>vvuQFUO&=RLi$CcLrD?pena_7
zE?WFOjfI`?R#Ls>s$`u>#vhxDA9qfd(Y**hhQAs+wHiW86C{a;JgO-?&DID|Mk)f>
zB-o%uvF`EFs_%|ZXA=rL%{N%%G*chcyoV<pcPbK@%rlF^P4(9^KT%_NeVPUjm5yI|
zuFS=+bCQn9c+I<4!ck4bp&v6AY9b{%CFTu_R@f@B|7V-zTm)P*ksxSY4ekAeZxUd8
zY?!3N(ewRgSNYsLXm9Z<jH<1=aQbK2kvA`#DfK@vNUSoW>4_Jau5=}&|C2)iiXEss
zW?COB#3$hB)YGLLXwa&P5(K)#Wu#L9({R(+%Rnb}ULLBkL8p>^I4L&(Pj9j`Yt47g
z(0M=QzHT9srCO5e1xdm@8L&-ZJ7Htx<IunDVD&P06R47?59T!DQ)*M)xGssV2ftU-
zA-f5-AkTos@NtQiUMpE4kEci_>hYau@nYg|QaOk8l_2?VCg|d_(W+|Dn~chfqSVl1
z*58SS*&*$8{3g|S@k10kHuc)i6jzo?phZ8u89#UuOy4ecXD7bnFK$5W-RVjZWP_0A
zR*u*)({-$KqOXR&rC&F^%375|+0B>`0BP;rg>bu6fB`*GyA*{Sr}Z#AHx9A)F%}E}
zBeG?UkXPtGxtC|xUGDb1w&|epp|->n6(_u+N*{Wf-%FYNA$6Gd%G!x)(ma(e(+&$-
zQp|rC@IY3shP<47bWhL3JxHQ5@(Ppb6V!Lb0TbNzRB*C-XdDhQ#_J+lq;P0>5=q69
zrZ_`gKpqJf9VSo*69DbRt+8u49(3`ng)1-H4liniuy*`h9S+DYQF4wmtWZJHgSpSy
zm-{AUBA+3xwR}4p#)rK~`nuWonz$lrXWwa=wF__bP}`ubJn)UDDZpsEP`(l54n>6h
z2H_Y@x%&8Krg>Y5c%$Zwn8$M;5)I{Ytr*1KnC%$Xw^!jV9VzEj4KX*if7Z5d*}=tG
zZIYs2(n!`jn8x`ml^J&<t9r`_`2dcpV~m}h+GqzQn}wLU^jIdF1khy1ltUWiTa!^j
zV$#<dfl-HD3~Z?Gj%FLkViZE+D(I4`DJiYU48!)ACzS6ElInQKXKVtB1H%(en{i2x
zo*plpE$>Jv$_^d<9HO<i<t#0;^?Au1Tp2VilU(^0d`BArAtXgzVo|V%!SyXDV936+
zZ!?N#;d{K>LG(M~l^IN%iqE$(D;FSDNYd5Kb$S(}&~}bLJAWH<2ib;+Du}AK4hx7Z
zX!yu?=%~lHyd;|Y3JlqN5F97sE=s$?*(V6im<(8UMf0el-B%vft;+k7gzE9cH`zUG
z#PR#oBx3pb(Z4AW7grzOek4jHTwmf^glKV6hAzk|BFk~dCkCH7<`-z6qu|`SsjF`;
zf8MeH*9@ESbQ1KQooQd}AijN*<aCyBe;dE?Gg%a77uBs|kPH~=SB<gUs=Jr@@@|;J
z)o~2y4rL!g=@1OjO8SNPhUesB0c3LhmSpw1Qe25jV3Qh8BG%7_h`qCWQj$;*<zZA4
zSH}n9)aawNice<$>zX75Z8C5XZiQFqNoq_-&Q2OHow#GY^<jdn!R<1@2fe?fV!>bV
z5=$^$4>9J>435ZN!{Uz*O?07*aZ#9CLT~>G2gSMY>oac~#Zi%*Uo%P~^xjN<bS{MJ
z64l=tZAwBOScem}o+`AcG0*MDyhZY}vdN7zCmjvYwgS8EH^i2_l2_y0c+Y1jJC?=s
zX;>?DqSIK&o(v9-O2Jt^H%8XW6}jV%RT}eTOf=y5MFqQ~>gqCzP_RM^GC806h(Sk~
zIYk5|KlLib(J|cc-g&jbTvk0zXfl@r)Zs>LNsqMq4ghcsx4FAmL*PdH*wl*6YuEsx
zB`S*=S;#Jh-mi*kFyM06Vq`&WNwS$yxVUfl$&Lm_X=tfa1ax#sUS6lOm9FtRlX;O@
zTn29XoA4@j05oTul=XO$LE50hO}9}>dsl)eZ30`6X;Brm4w}!_4wcmkG|=^KWOT3?
zTIln^9I)+uqeNS|D2zG=1eQweE8HfF<@CQ}x*$9YO#>@G_CiJ^e7mlBNIeXHGP)&G
z&?M`s8hy?|Ii0z#U@y7G3V#g!M$~NRDzdvFSh6Fk1V|CBoWL=!jB?hxYv%{;5w+k#
z+mrcT*Yh=hti4Mb<>lCjgIs{7u1ThQ`_Gl%v4m0an1!J`;E?l3zK>i{SMFYoMt)`{
z<U-LdxThmrA;boBi!(IC`BawwlUsuTkOj_TPUbMxT(PXroe~OO5R>m1{{V|6Jjs)-
zVeN&^s54xmQ!srzdU%rcL+3uYyAiUqmlaJiC5z*Kv6gfy85pQ@10?XS75Q=PUo7cV
z`nLir;RP<UlyDG(!6_&2aDS$>U@F5|=L8_;r=nAu)S}i4)IBP{XXqKZ1)eSBL)CZ<
zw4&&)NGf|HpKW~z(}s-reZneRVIECDRi$M5oHzQ)`r}8BppB(WOfn=2EN<kJE+9?J
zukNk$$}m4+TjOHraX>MfL#(|F75+E?;|>_j(pl0#a1>NXPNqit?`kC?1+|S0u%S78
zmDy?I>6Rw9Sii#=CF0X9MYp&<7G<1;DT(t-(H4PbGv^CVrVo-wX`I@>^0XG34hCbg
z@oC6wK<Bpyj;IRy#vDdY&g<@pK<|c*$Y;@a)4aUqQD9+whvM0h*fh@W%H~$6ooNW-
zzdhu-mHORa%sKelVnyeA;M};CpdIJkkl!_45+!kzU72n`4{gx*Yd?yX-mb!Tv9Ri>
z0z3pGLH$G|$0Mt&*8a+>waPWa<9R>oLxg**1(M|(LdHXB;c6MeCQRj5jc%rGF$^t{
zuxh-;j3!qI;=zfI;<VxnbXYL~^0cT!xCk(kjykt5HlBg*{|c;k&1wCoe|;OW15>J)
z`mK8fqk{Ys`Zi5&Zh;Yu-!xzyJOi2C&1J5&$K1x8j7gQ+mhr_zL<R&&OEi6+P|rUp
zn}w@PTq%tC`qAGtjaXn=OY21bHPcTbm9bcgJB`{`6>i?T#TH#HZc7NvU!GFQ-~bP~
zd6n_snE>m67peV56H5W-povPqfdYYYMc)#{_m&ry#yK0sAxh8J>{1+KHFmD%@hAJ6
zcJ{;u${K?O@nJ~|f6H)BYv7~hlCM5I<BPS~r`}r2+thNCLZ6cKd9n>6(MCp?rDues
zb&677(7pHOKYjQsBx3pc=EG!B4F`u=MF3W%i_0wLmDixxIdxwqzG>huqARR9g0&%r
za}~=NEH8CrN?Wn~K(uII_V5536;y_5LL@WSuM08-=}D?92?g6vt!p;5Q=NjqPNI8#
zH!k6|t2v}-=AYJ1S-NG#o_D8{piDFAjBf=7k7<S+bL9}Bs0%M6Q|`};OD!sGfPBwh
zmR(Qqsp*|YI#*L4L7@Vv3!lo7f!EjsR!aUMK*Y+Z*3vd3i&~ok8mwWa&Y5SSz!CC^
zG#=S3*TCwU-HZ!bi~DQ<(9cD|cbj5{*ScQ!&w3#v3|o;|=ACbZb1kPi=Aw73qnu-A
zn8;bw)B)t>nmH$Xnx5K$pZc3W1Gt)N#8t$z+52CmXk|K@&mWS7E1Rcv6uPE;LwNxA
z{W8KL^@wE|!de)W*qpkH!DeTgsv4125ca28H?`jL=keu3{4bEvwD;S8z7)Y{{SE>{
z;Mw&q6w&)B{CdKMRI%z*P`(LpY|K{atYO*}!>rJYU`0}Ta8hpX%#|BGAsuvehGQ(j
z3y809$!;CwsWLq|-3Y!&SQb;rcCQ0vGW_U<cNDfvXw(>o$r_ckHz6?HLgM~1x5JjS
z91H-G`N51Qft;McDgpHD*=0X-YtV;(uzi+&!7i}z5&cmFxY7qi5D^`pkGSI^^8Vo*
z#SA-N;lkK{X=21Oo3>NO^|YKAD2S3izbkh}v=mp8C0rL44QrPT*a1HIteTJB{bWI$
z*t(41nYkw*=hzzqv;pnj(oJrwmN?Kc-}sgFwj=gb3dof(=|;giTJkJRZ!KXuEYb&<
z2XAuBEz8CKI?8WNP#}dpgDwLojt8X*pKDj?1*lfwn}VV~r9Q((j-cajf=>utS;VI8
z`a#Yni|4bBm?h72aJ-tu>s}eBw6~95WcYJpC--}q_VbZL;=U0gF4*A-=gok(+-916
z%bovkrshX+XHSGc{Bm((4DJ76?Fsdo0u=mM@7xooer-s@r<n+;@^?TMy;?NdV8I&$
zojQcQ{>8CiqhK_3XB(u|gP7qGR-Aj#9*wxjfAvQL<^cr>Y=zn*lDk&&e7;|sSMb=2
zgwTPW9yp&-@dLf>4|dJp5vnFczap&D78Q9400%boev*(yeDYj(!o3Vtp>$fjUeKOo
zDP)RZ<Cte&_juJ(mVIX1+79)gqSs6~a(r4XkQ$&)gCI(~9&SVeldysb2R&s2*j-O6
zk69nPBS7WgsJ$MPg)ih;zztS^61$Y};V%-_e1%`$!4tAXhs-IwKF%UKnseq+Ij0?>
zf7_+09AAj$da;>9iR*t1tcx7$*=;~rLCZxRZSL5rj3fl8YFj7pGk4c_Y7cPK(?d@T
z^UI`Srw?i1Nux7wbv46!*IE=`WcCN!iOor#!7vXiU862mlTZF&tKa*q2$YQ1@aT=Z
zjm~b?<)F~-b<aDz+Y(gTs3W#DX%oyt<Zv_48X$Z$2?%q5zKZLEH4V|DdmduZ()?!f
zS~?}8-*1vW{Iz9ra^=5V!|?Hi)R%Q5uU4#K;>#n@d(z3a%m9qYR}Bn1cFjUk6p`F0
zlQ#uQ--jU`0%4Kgo}Ux#-XgMhtI|&BEr63=+@l=-ji@LvKHyf9pFwujijN!8P&Rkq
zt8H5twXEZ`6q0b%x^`nK7czBWU$jnXe*cL|almH%&H6Ziv4Vg+K6gHr2ESEp8jizE
zf&;?h%JZ=1N6L<%xM;AZ@X5>&-qRSWu$iS8y^P*m^{^L{7M(^yi8O6&hfg^8g>Y^7
zz9+&5;VebUOM+)hX3(-T!zVTtRaG)BhNoy2P)j(vn)l1Rnd-(T(oZ&WfYi}g$u2Dl
z_&W?DakuN~R$SA<e@Pws>M)Z|HF`f9hx%XAY!n>o;VYzlEMk)xx=wICV^|uZg4;9A
z4H_h44UsY2`r;`t2HL6D=2KH4+uQMPii6HAnjCw68PZ-H#p1iU)NzJBhCQwc?|O26
zy<VV+7|s9W4^?Bdm${7^ba9cm@LuF7cD5&E*SMya|E%QN_|>4iz-dg$RcCWpc?SDK
zxGv9Dn}k0aHWeiov4#JSBf*W%^jCEi9W#jw*~=_D1w`j5|DuPEVu4^WPT3Vk>@`jx
z#oox$k<<!9b9k@YiOK1vsn}0Qny$z)Mi~NG_~{Yc3w^^lsFeEyC!MKWWK|IrhCZh~
z-*{gH>rfGOd7ZrtBFZ&OnAu>nim@4l$-C|=8#*D^PrJ4m6ex1r%g`uqN)SCrpm&t4
zAcN)*2>&#s<Lo<T{qN0FYLiWfMNtGU6lqAz0sfq333L)_GnEIR>G-ZjspKc_aW5cY
zVVbY!;6Y;$Gf)N}>qd69f@d}He4&XE#mZ(+Q#dk9`-5+7V!R)d6YAEwQ}y@Dp(FQ+
zI8YT~(P9J8-xkBxe*3_}jueUoeVLOM>k<~mEd~Tus$Qj5>lZtK6_%iG<i#HA9b2<c
z%p#-SlYE8;eN$fp5XO?4A;@JZSodoDIjbv^X_&SGb&Z5)w8m;Qdf2Tlg(a};iCN7|
z{;CUdYQ)2?twsf|SS5fS!PK1-9F0Yn&vERJr0Fh%4;r>g@}-;`ff%o}S9>p5lSl}o
z>70eeJ`4>Kn{k!Q2Kob+6jNQ+u?7;;5t_aYIx}h82IW48L^3OuKHs%>QK0R(8Aqxm
z4qViv_&<zW;_Dy*3gV9U<TpyoV#F%_Lq$DB2wS3*9^vop05d?$zsZElU>mH1KCwm(
zl$B}j!(Hq^zMz^OjmSAd!xdzf4bKCW2Jkst+zJIEh#X{fk`!y~AQ1DeFfDEm$B|<x
z0!euvx^CnJcxnU)!SKR}f2tTLX^;+PeEB@0U~9oRW6aR5+a&#3i|<=1>h(&1U|jL7
z4LUmBg+$J^cL*yTc^j?S3oOlt^N;Z;K!C6p=;lz%>dpL0JJB!<&|+A=2Ln*lX%6DK
z0)+S7KaM~mxaBqqgnQkTOwqdNXH|UmR1?jbwBri=KnRv~P>!U#M&HJl=mH^swTnuT
zQiaa+b)H{l@>6*rN)I?IS|FLftsZI*FS0$mjtOqP$m6T!TLZW^+TEM9+O0@Di}wcy
z!X`*q{>uL?rWqQ(7h+T!!oU3kPaAv^M$@TS{SV36<EyiI8ju}YPAsq(3-9mlVd5u~
zn#Bfowm?j61N|ntgqQHe>a|5Eh^K5O$#9dg-w@OfCykDIUwixKM%j?0X{PG3Lw)KX
zVyY7s%k5&hpy}Z^KclyXYNYZaa}lSnnoU&h%5SA9>o6)kW!^9lcvWfT9i2>VhBUBO
z>8i%hn=>5Y!VL3kZf*@<-*vu*mjgIhk{a3H_mh4@rY+PjB_;{#nm|XLZT@xpNMDK}
zUWTw~-GD3enE_qa>$&ItVUJTAXLz3s&PPQ&%Sf(Y%%hV#xYoO1?m(w(6NrIkVPuZW
z5V%88&57=?`Q^kusy8D}wAA~KXaiDVU^asDsJwzgkij23ZZZBxf^rI4<`gC_I|anf
z4_r)O3&Tqd<MI+B@-di?4g>%CX5X46#>9*6sr+N2FnFSG!m~fUJw`tq9bkpn0PB=7
zqK9Pl9es-h2{|H%anOoe+SdVZ{rnv4bCZ{dg-!99lOn=e*NSA!B*UfW%Y$uvgb)dc
zUB+N48^|VNpW02pGh`CN&sH7egU!2rvu?@x%WClvyE{v_adCC;)T@1z7y_h$%y00D
z@#niXS@v0c5lVM?sVLPI6YwI!V?M(Zm4$cu5oC?{p3I`P_RlyBX@&~PF`)g95K~%|
zih}}gwsC{JBTT0U%6JHD*=j=wI>ZvY^S2&jW=U&~9Ri+s2nu_-k3W9rcR~9$rJ@l2
zybonLhoV0#ZGc>8ysmd+1+S`q3_GDU*l!ACEWq9^Clf*(PYs1XSd)iVotDCT9<y$x
z%o}l(N_d19HFXDFT)6&dr4unSC_Cnt|0as`+u6H+k{!7v$rj&Xz&~QD*_DcSe$xYf
zY!Hftsm&Li*<gicm)JsC`+&S}fX7aO9jgIZIY@QvE_Jgo$XL>U@QdTd+yu%!`Z`ej
z#xIZz-TDoj!Y;Qq2yF4O;$D%Ir-PB&=+ES&-tB|9lA1W(8qnsVfu4pc#**spA=Z*c
z=jTCW2zSgQxRwyQSRBX%HDe(^6>x*GZl_q5E4K@%8B-#5kDRKd-R}!%bgBI^eC!tF
zJaBq1NnM&W@JzR&ozd3eybjFOP;t)RQ5cO_CyABPxMe=;JF=0uQ)WQ%T6=MDUre;!
z;4b-KCfgF(F}nmHZvbrACpwvzznwXfz@Aph*DDfzVQIIdL)IRH0}690I;#j-<-xev
zcx5CPa=rIkGA;d!*0PB_yxgRy-5u@b^rH#(Tq9X7txE!iAfIP<cB=_7_xb%e(4a4E
zY$DL-H8bXY884xt_$e6fG$1S6%@4xebwGp8w++aePlwUQp=uO(0JrKNTdD|Wm;Ak*
zV4bx@6V5EC=-^%*+S~k+Hse!}#MzAL0dR}Aa}Oc3s|a9|nYCCN@4zvl<gQu_)T8Y?
z+~|-Fk+=c%z1M!sTJs(<Jz0;(!lQlO3j$;xOsk>#aCD?wz3>@y7kO&kvh(gQ8u+&&
zm_>WB(8Ou!AYoZtD&X9Wk`mBF#i;V1G#N>ws~u)T@qyU8)Tpu~P%LndgIr=cqwlJ8
zg~?Idhq(_%RDujIq^;A=8Q#%LAl=yt7d;2&Ex9v#_w_}*VSG~h6R6mgy6WmdwkH@#
z$`-AF!H_<x1(4{%o&PF+AhCo@Z$|T&5tIk1$ypoVVDFf~JIGEzZnSV0Y7dXS6}WkV
zo&DapLb6{4X4^jO>Cp_eIy1fU;vLpfvIyy}?a922hA#nTZwpirJ)G!pNuIE<|4sIg
zp{7kamfy6a8fCQ75UL^ZAe?gi#jk$$>7E&Pze)~ErA3H2hsl_Dt13~17W#`MFYuX4
zuSXH34>N8kRTu1E>OlYWQu&Lb8c`};@Sol4l&KTFrx@Avt^Sw(=f5He82KxFveTTe
zH&`6-H`7d0)>QWg=rPi<r;lVcDk6Q{B402BM6+AhjEzS9D3{x*T7UHM|HJPY<Lsjq
zUHw<rMbkM2jkZ=SR(1NvIYwWI__U}~dd(#lkhVj_#bd3)f!A;=z#B;X`kZyQQwUZ9
zHKZabT5nkWVmv!}`4oK%Ru7cZ1nHfGN?(R%e!o8xKYW8hkPe)_)zZr~1zY~AWEJ)p
z(Ocs4{pUrO4GYd}u6ACJH8XTJtAwc^LGdSGDnFf3kLOsl-HRdHNP|8;amGe?cUCyk
z`XDLT-L&L5_3VkEsvJ@(vWCV1Z&IvWZ&Gr>I1x=31AQn^Pu=A@!A2L{4h5ynOUwrL
z&mLuLp|`2~`CA7qCDcaa3=NGN^?@9y)s;+^xTL(txcIly*qJIk3AhXLi`ij5P!-KG
zAiW9z%$s>S*8{JGq<Hr?NML=|I7dQ_eCGKfsBmaFaE)+>RLP4T7XXI{*z4dLGPU(s
zY?aV{#VMrut)D@G4om<S*UZ-1UteH92I}awFsk+?OAzq*p7FxI79n|E$+ddhQc11m
zSiPQJ;g_g*TU&ax`CK6JeD(qS+Twl_#<QwxF*5Uf!?&)DiK~KX5-agj^ePP3z1Je7
z5E#A{<g+G?U}K7v`vMF)CKrM+eW}yT&~5y&z51pLoP4-s3;RMalAay^YkOK?|H+*f
zsv%kX2rX~E#MG03f!oryb$w8CfOX#@uR%d#KE<ZY=KJLhB>}!u#}arM`=aw7o!*Xi
z^~)+M!RPAG<F{YUV!Tn9gV}-I9E#`C8c<v1I1yE1G*7f52D9=mu-gUtY|$Z|z25CP
zpzrU~G(!hU7n38@%ptg)&gV*n0nrwHBHc_lRJ_o+9Yl^CR{o3ujM$jdZ>9!2zAc#O
zZ!CGJIeKeH3NO!_Qw6T&Zs+e*GrM?UUK;JN<%L|}mz|!VpQ0Uri>rRA@_2~o2;v?_
z5T~aH-L^>mo_JC#D#*Kj6R10-@yi?p8^k84@)^mf)%BXd;Z{eM<W4g+BY!pQba1^R
z8l}_r`o*#@M8b#dZ=?aXOb%=R2-1Xak_Hj9^F9{l{@75d)6h!M*U=86Z^e>Eq!kpn
z3&+l}Y7)As)@?*7WKA1?pp2JCJoIcnAV0#Kj8bMA{?5~lN5pe<Wdf#bdXOPPK11>+
zAVcysWF1@v3R=_njfm5mBF)&0#iJRY_~J4tqESghcR=_amhXymq3J-rO}k2VO<YUR
zdPX$>8@jU>3`eX0jxBtw^u=YuAX;o^aGm%A%=i7H1{;G4!?j=)y(%4^;in=#Z~$z4
z6?e$nB{GFj6pX=&s?W!(oo?K`I8C8cV7hH+rzxR$&|c`S!I;DpTqt??gu)m@UNAv0
zSMq~2aH>QZ@kOo|4$w;jmYS>F!jRBQJ&mTFBk?ehZt3?VYKkj0n44{E0ef|I=hR)k
z8|*pHe2kDN)XfQMu32%XlXaKODy5I(aau~|0%TxJRC3Xl4B}`u(yV1oqqCyYr5K{x
zYA9o&>NyyY-=B1)LxLA4+j!E$^1*SNql5?&k<tBW0t=H>h^lzyW&Q(iEkTa>ZEQP~
zkQX-2U4WoRyx5ZPvPrO{?;yG(cyb}~BJXc+iO~bH95Fsv^7Y;Kz8hjYKo8h}?Dh?v
zFDo0XJG>A{Zn?fzLpilaX*9k#^s*3~`ATSk%vjE!R#Oa$0XRItOnl7%S7CPZ<G>8x
zCpTPEP}15l#Fbhd?`74hF{NK9MP%7hjLX35=Lb5x!ZcKr#!%X?OWcdS4Q(&%k~bEJ
z-?5iOz~F&HU4nq?+i4nZ0E9|%Fz@@2*&TW{XQoEL-h{3_Ak?MS&Qu?OF29>3t7|d~
zkZ5Yu55f}D+DZ{M6&9RFXhcQ3*Blx?mR{COYJqnTc?R_Bs1|B35JtTF!pdLB+EWlR
z!yNC>_Rg9~C`IMlWiP|HcROA{O$O21!$CE)4(KCwHQ7pIQ<I;ut9ZFxq;^3vaWgc`
z&Y;#q4h{L{eIQzdJlFpGj$ijcX{bDL8lKupEqx2+d#&YEx(i#0^J4GSVs4loDA(FU
z$F_X_FIw5-JiyO@+W0Mpb`CETykmI8#7IOBhL)rBmBLQ8BCz70>?WRWo>!ItTsnIP
z039~@6Ne&Y@IWkzhYgHZW%@zG?4oq*a2&CaLrBeaVym5^fw+k^_1qlJm5+m0HY50?
z)U-%Bqx=%A+2CJzscC!CefX)GfQ2S!lN-|8<ZuDN^mroI%Y<B=Ancmw!lS#t$7)EP
z`fX~c>7EG{TEMtwev)@Spiu|NI5FgYO{=gYkHxQhLAif2SnAvBA1t>vyGimK+1|`X
z+epXnZ>TW+n*+U-XZ7*o7R8vwa7*7wKOGG+Wiocd<likAT}IyIU@AwOZxeBGBO?9P
zpf<cNe&eksUll#7)eaUxqp{l;57<!PfpFcNWDf0pXM2SEX$OR(RP(Wrrlo4BFY*><
z;E?67iUc!EH3qp|1HmUt-O8eU;rsT81M>^d@>vX041T8BfJf#|cU~=bX|%vsFu`iJ
z*c;ZXd-TAZ2;(svMC>Ka%QA&fZ1Q&;TJUpaD!GzZ^A6}>dq%Ng_~r3YA{GjF$LrDB
zlbm{_Qh(SJTzYk4&q|IQcuTB`VNyYE`jTQ17kHOed6@PJa6#AC#b$-W@gkNLSR|&b
z^jY+&X?taC@l8*$DRLB&<{i9j;Rgk@`X77LWBNUsf0-hJE?~ESP>tNPw`+d#FiS#K
zbPgNij4PD0j_0oe8qE9Qr9B$VWmF`VT#M<}VKy#%Dvo;L(k$5BO0vEVKgAisE)ZMi
zj!~bq@(G**1$OT>>g`;o!r<;0PKeV&i?De8n|u!>{V^wV6aR4hk>HUM3iAH95=+^K
z*HzBqmJB7JDW4nmrna<^D{(&(9;D=hJYVw6Hap*s2<wU}s`8HYn>XGMsOW$ek$G^-
z&Ftki5#fy0=mg|qD#w(dZl<UCvK0~K{ZXSYLj3v2a`LAb=1M2eaDpYV=X0{EVlswR
zJ=H(e5?Yk|P&7A+*$D6Z_3hmofN8=U16q~eAq#+FHQ8z9*;DX}w`t|A(<Jg+Q41=G
zskC{%+ZqLxeo1C9*bT&I;KvVF;!N+wGNmnTe{;{;G4%9c!aDM}DB*Bb<(<m8ynWcA
zw5e~$Psb)es@~YQGeSWF{Jk;e1fdjl&ZuO>j|50FPf|jzS@j3AVHX8O9<A6|*C)_u
z^lRtcqkSm+ciN)72<PGta)wSS3SLIc-CuBAV#t5~K&~mVu!Q{*MVjjd0KnN$<oseG
zZ5HlhFh<`v1DV3jD{_L)O$tU&rx9ETG}~$;rU6cbdtfB{tpDhN$NaLvbTQTJ5OkXT
z(^xS^i1RQSdT=j>7mg0%AL7J5Rt;dpdU*KLq%0PSbNIqAe5}S_gjr9;b6mD!BU@gW
zomWtU2sFzKvjTqg1R@>T{?gdcTtuo%a=`j4TX9Q7a13d?iSm2CqplFds~i{hj}3M!
zc4xLAVN;x1BNhHvKOPY65{~~-5@bRldX0nE_Y!glaI!oM;7@<C`L;39?DZ;OgIuv^
zc!-1w_hEp&vpH^=0rwqu>%!2b(+`fCQsDUbxJaTVBe{?dJ}2`-xaFH?l!KJ0Y((6g
z^kQyPC&rwM1Os?HgzMg~GzXh2zAwXttW+EbHzkj;@arAZl?in0iOIu6ByLrO7^0|W
zl^h7Il^U#*CKo*tVYTum>{d}Y?qdY6By(;sU3R;#agZOcxGXH@&|0k<_Jd;-87Lhq
zqw+I+Gc^%z76S3U96^o?GO&=WoJNgjzf^<AVu1<xEHl`oXDt@}R?pNofPT;#Yi~Bf
zf<u-(X*hT(r(#Dt55VRS9O~zBiyi$%3{RgxB1av$_YXlY0iSsJ6ud*&qBOjPzPruY
zYg|dUswBZG7%AF;#G4@!dR}63BVV^y#LcFVyWE6@G>`jRl+nD-1HGM(aJ|7_GCNP)
zPD=I$jSOcxOzXl^*>{qj`>1F$X|lzsW5PUdP!I=`C!YE&BxCQ=I@gal`z^{mm*T5U
zvRk`pP~*D`B}%w1?ruvz$y1VRKG0}fx=&lOe#-s|icbwtMjU15-w~_ZD99S%1B&Uk
zD7GtqJssvm)wt9YN$-us5pE-Zl2^TQ4{B*9O38rYe8JsIUcG8Mr+G6KVmA?3PpP-m
z1-v!xFQ)I6*ngzr;EX;bZJNuZDvSt$C}>=%LVJB-m+4cFQ~mI1GE`dTjq`lnf}V7b
zgVD87&tt$5nUDVD#RC|KmrX%a499ZhzW^uc{;2FZlP16iCE#?+A^$0swWGE<FJ$%E
znS(^*RwgjmoL@t!qMXJ$O;|498w89uaL($21D|l;Zis*TOZSHChZH5aptp7W@kNoM
zL(wWYB=lD6i0U0mGZ{d`BkX60;N3Aj5*7N#Xn6@bDoQ7R%A9P;qA_QxBP9cSrt*~*
z8HnFFpGrvg<s2R$xAs8v;0=_6no^vq;ct;IESr$f+g~NcoT9*PQ_0=ON!TH<e_qO&
zm*%{Hk-xWSU|QFBh6R4V37}eMz1P@$9=5mwS{X4uS`J+V!T@ElwIuqE(iQj@w}#g?
zX8+wrq%g(rlxqJ&LMF-wXwoMGnR471r!72L$yOo2#qltn)=OORvJr{2{*HE=pKQ5V
z1%n4%twqWqQGz6gVRNP(@8a72kiTcK-VEKx7z3Z?^zqOp%pQU?^YVZ_jerv9hd)g+
zGCf?~Zaf_kX%FQcU!bSLO_>P{*OY}G&-uaA@YT9A-qh@CG7x;gH#8m2?`re-;oWB)
zu_(=NCA4AI6FjpPeoBPXqb<?$m(-dne<aT5Ge*4o11Z<I0k~|uM=(Vh9i|;wLiD*2
z00y41a6eC{%AIJdpp3a)(sgg5#pqP)E~iV_+9jcw%!3w!q13RZ10|Suxq7=&lfhHH
z!;E)_P4Mj*wdY$8<>g?vQc~U?J#WF%PZG%E=6!)p2RBaBbXp4{O7BgSkXOL5BcWg@
z!(nxPR-hU4d2hqDHgwc)i~~J)Co`%l>SE#s=0m^aV~79p1N$wC-ZVr!9wwnep7u2)
zopx?$(;xEg7bg1|P6k0}swiP2!wCob94NC^-gSC+3VqG%%$%zoq}o;x*zi0=>)rU%
zFpiVJG^L4_bKqWjcE|~*R>N{mWPQm%AKS@6bqNISF3o%8MH1J5#bu96;~x*^fQk6S
zN2TtYzpxO(g~UdBj>hj=3LMNQ%Uhie^>Hp22_C0{I-6Id$`;2G7#}hQL72zNBqgQu
zD}K?E(1a}>$aOo`+`A(Un1d9)?(X%UW>K<pl5V>Z=E?-fw`0=``Cd&`Ix{_R{zot`
z&X+d=EG#B3|FW>6M@$0pKC#*!vfJ5Tu0L&^kg(jRGFOT;mn4s__-<%GnOWX==J!UP
z2Nq3}7(gH(18!KqYkdqQYsxh{qE(*nNvJfhN?$~F1-9pJbPS=~cNeGXrEb5RKlo#R
zc=nI%@3gK!1?Hl7w!E4yYIrD-XR1Fxo(GH0826K?OZ_?le9c18(9-}T3PT{e1B+ao
zW`FKek5qMAozJb@`bv`yUA^>XDZcfIOuXj)ah#%W{I0_d5WvoDNsHFzeZyfvK7UOi
z2_s3BE)QnolB)yECTz|3EqKBic)yp$O%#Cel5|H6qKy<(dNfnzYA{uHJgIHLzZA$+
zy%u7-6Q|&Hu#Q$-CTpK$wFR?|%gp8lZWQf83G6P1l_}gW_+SnG`fwJQuv<v5D2RZv
zPb#)L52-b3>I?$3)Lq8({L%GLbix!}oeby3L%0%q4{Qv^z6bgDjYt6At68>v6y?qN
z0+qyGX*JvTp>RFl+N3&-&>d9#75A?-LqnZD(k_qtM7oh}1b1HB&ElOKyrd_%u$&rv
z+08WIF@z?%5?kg=j6_^FY-uc>z$T{H0rrrtA1|$)s6oH*l3|8o-tfEHqSEo?(g=z0
zy_KEHaAeJAMcHg*wny<ppozn?&htorXq#EO#$A*@>YEDA8Z?LAxl+^G;xaTodbX8d
zuY3*TQ#*_uvw68T*cZcT8-&Re3E5?MxR@)g)hvnJZ~K|+zPcO(oumCDQ)4~(y~d*&
z<#M6Y8fRb*+tjDn&96sR@>mJ+PU3?GkqG<8L|0?h+_Rp<>=&z%9S6qV-&Z7YMt8c!
z@Ea6<3j<>t5#MD@6Jj2r%d6{;I2Q?xN`E6N>;gSY<mbneey1!<Ey~L@0WgozR<j}x
zGiZOe#AwQi#HF%T6Q+1lo^1ziaGE(ol?BI`KZd76jNsCdgpy2?{T7NkY+#*8n;VwG
z&RH3X!vRtICAPK7eHrPG&8c`mU2e3IjTT_YZ(=B@bQtF;yWe5kkSg7w29Rd$DJ~9m
z;;@*Fz$wq@gc;J>*TAnb%Jk?3cazPsP4~0M0q|k{r<##&FH@M101)A_!qNjFz4D?2
zDv4k5y7Kkj4@U1e0r#XT*;%Vs`{@{Nd_xfHegOq22e@$@Wz5>m#rZVDsue)!&uF7U
zAam~L`BOk=Xty~Z%;#O-2yEd6L4RvK#^p<T+o4pO;JH5-co|{*$sU;6dSSr|a^8xA
z_s%jNZf1@l*eANs^8QTxk?<C=whCZRgX!A~;X{QnkMrP?KT3cR7&du`9kg`q>a_8V
z>4$jWH8QOmH6mjnRo;6+;4=^y_AL?lEDUr?DQ4E}fQS>>x5S6jnzR<A4J+bvcXf0+
z$;k*Kslu(r3f@0WX#d;W5$>{F{8)UIYP(B87B4-*QHyoZB8h|;ITh<;$&l?`RMN{K
z@BLG7{gLnj^B$Bc?1<ZAAJSV_n0rE|iQi~#aC#h@%Qw%VElXoSCDHAv6#Mjlaz@E6
zDmAWXP0tn0_@F%U(3j$IC*HQej8mZ29&s~Qq$2Xa`$sr~n>WAMM2{1kn=#nxfsJkd
z+_^~tn_hTgGa5o^s_Rvse$gE_k>jjeA$8#ktUPm!MTJm)?sE*V2Vjbc|4d4_D6+Pe
zrmIrVRrj<(<i>Lc8nwpu88M3~Yb!RtPiGp>Mg;^c(o0nHh)~FUG6q&w2>^#u;-fyo
zO|Ro@V)|bh)oK-ko3|qEZm|=Qm>k>!U9=J5S}vnTj5lkX8<Sl3mm2;VBw`xnMp)S_
zp#B+6n3Vc5TZ&ih?T`-4WF3`KR3miS+<C@7;#L-MK3S4k@8@@yUI$Ia@3bd@x`ukT
zYE%#!%vEEA{^fd91pO6a^<1zAl?#C4=XCHgDVBISGHX>MjOHg}ntok{;UfjZOz>HJ
zchwg0o}N+1Yk0(HT*qi|qWSkmriaLB4iS1v`wtM=(J?7+UBZ2MY(b{r8`)07XbL)*
zPEXExsm|NgPt7D7PS;g&@k{4WLa$u*Or;X423pB-hlMlTk(Zi%Aeb!<nOn{^MtEnK
zrM`?`3Bjc=6XOM36?cH-&eegMTj4`xQFmhtIyLyqczgu~IEJKF%;x@h2fOW@>mhm!
zfcU?!!_n69?u7ZDFT-!`#`fH!bE6^z1}suSMe3gz>7P1_)u+uk08Uy=RfZ3q7J-Sh
z2U!mPh1XQ~puRb{y*^AurlBkcht0=}fLzqH097Rl$$`Z6>)<<@dBB??cfML^XqbHJ
zrhSxUpa0Sg)sOU?c(I|)_9%mK8%o4SADs3GOaFR=I`1u`5!M9sXsTZyuUCse*m4QQ
zF4li2o8?Kf&U6kuq>e`Y1me*j3YB~-)K@O#Mo{g=s4=k{<TI!ln){qKofc8HL>lgz
zKo|zg%Bg=a6kZ<SJ_IYbO3WQb*(}K_w!#`whmwW7ICLXD8bO1c5AjzPVZDU~^H}b2
zf!S4PoQje8T|{?L%S@$Rr~aFLV2s06H9<eoJmc^-_x%jxLTPawr*tW)22w=!aAWmo
z{K)Owt~i@0tb1e#sFK!dEJ6_@cJ?gztR7#oPquuntD&yvVBgW}iBzKgxsJgAY7ZRr
zAr|TG3`~@QlRXWMH_!PMZi2X-`HIxYT%{OYt}u|;Mz>GOBhtq?D4hgGq>2ym<CkXd
zIXFntG6mIGWyQ&}PQEsvt&x0DQpiiH_M0+TyP#?Zwv@~F?%Lss<U28PD6rhOkZ2<d
zQNj^<PB<KtD6%U<6xS$t31_l-GO&iEvoQ6QrOG3)jxSD5YmfKS(@U)Ec*>o1D9+_u
zKq|P*QtsYeEN2>>8!pfc5Q2nL3#t7`R!2#FgDQwp;^9R+p(H4~-nN@$Kl@dSvxST%
z|BH4NY02Q9sd6M8J1GMJ?GlbN#B`@xZ1rk~I|QFP*h@%5o=2ioswuVvCWlfeg4`a*
zYzk=7c#y?4w!p<LW7-Lx#xVgdWMZBq<r7D}lG&-RP#&JfLKIU#io2ysT|ZV4MyVM@
z1jX(L%+j+hWoC5B%>>R_*$-c5FAGZUei|WIG1$tRPf=5CydYimQoP>LBrH9{D5b&J
z!8~ubU>(Bnm8QTbnbXGVEBbSBE&&R(V3Jz?B*oTui32=sBa+cZf%7cg7j@E&v(Vi}
zX*sk~%ZEl(sOo)42?EPsT#>}i@e@Oe!yl{ibrDEC!I(IF$V(90e-o@$%9vdp!&BM(
zesJm-P395eGfD@PXDkCTp__e95w)C?=c&%^`juNXojq*@j=f&{PHFjQN&~{J7xkaS
zQHkG{%CBDgIhe~-U0|uvhJ|FHF){-fc#sz3iz8t}kTTOwoEXl#jSZodQ{A#Fy7v6p
zrU39UrhhM%3ayYB3MD{QH1e@WHF);jXxy}N@;kRCTfAmLz&D^(-9PWR3{bI-g8UC@
z8OyJ<{RBWF{7-yxLk2H_ko43=W-H@D!X=Ba@Yoh*2jr;vy@Nak*IJzu6$!nQZMm&S
z1yLnH-Y+N>uuwwcZ_WA8*#$0&_hk|C$}VEWWl*aWs_+^<`R5>64vX)3av<7+Pm^5l
zcz_^g<<f6iXX{6*4luj5hs|rMPxUf|NHrAGkTyT>iLJGeBa8LqigUX+mSd-|78Na?
zY(go!Rz})i>|o)`_)nZD5WYOw`nM1XlCde!BHDIPK_RD&Za=CH$<7vx>r5AsYIe_E
zjDY}{)hC+DcIQ2i@YLuMZch?-vD*Q*!WiWZuW(vFKCu^|l8A4yq2a(<E(-^>w_Z8B
zT1%2BaPwJ`WCDtqp}q8&>3$7jKw9h60FNL4uD})FXM6^zJ~Rbu%YkPZM`ccFH)Qm!
z<~xTtu}ogMF-Rtz5!I+!@ceZa8`PmT4|}E|ZmGJUU;u6!_iIHJVQrClQ7@qxg_1y-
zYp4p~%Tj8OP?$1yM{0!3Y-m<WDZRjb9WbFP0UO);F|oZ%@+mfJdJhqMDC-{DDoZzk
zqv+-G3>a+3NCL|ZD+o1AlGM0>AETZ*l1xT3f;gvA{Qy%l^R(ud%t=PS%ObfxmqIbj
zKWWZ8y>QivAMFb@7Bo8~M5l7!t#*B1JJ*8)jUP6EZ&2<W{he3zK0H}>8b8vPcG3nH
zBCq;OFH4Rmti1pzxQ!{jiGp#w2`&R+Y+PWhkY>pO1B90A8@mI$rE<{+w_TrcWGSP8
zGSA0F<4`OM-473)D!1w;%s}4Lh)I&3Lg1NNKZ5D1o*1s7(XQo05+Cd6_+gKS<D96>
zaO#^fcy0TULT+{De~UOxNj?c+8=oXk$?rE>)?1_(nuzV|adx2eUZvLZi>T%6AUj?*
z#6`VM0CrIEieQo{BEgA9its<1oYg{m^i^vXw1DxGUs#UJ3{Wq8?@JP4KH3+}R06Z;
z0c=%vxBrlJ!i+a=n-D(EK(gm4`ql>2<4bwtBoj%9%N9$)i`QiLaYh&!>SO8hgZQv<
zOr8#G2$t_efP*&AUqm0%ph=HeKy{60MVATW9X#Vk$qUcmdJ$bRm~-e1Zk#(uCVlh~
z=kEc%dhyny@OL1=PmMhZ1P(xgwiTL||B7;&%Xy)%wr<iPowLQkHEMS+ysWO)9a_>E
z9IiN=j5R4X(M~LKZfCha#9Xwos}4TlXVv3_MsT;37`AWw;kerw0HvA@;g^ZMj#mQ4
zKw$dG7i>IiRQs@oSBS&mSrDmD_k_lNN{M@Axx4@kyFr!SP#k;LLcPsXy4AY+qklT%
z6g4r*bbcXH!NTM70B`|2uMJNYy>_#d^PlPCxj)v~=Un=W-EfBt(hhN=MrbClZLXXm
ztk<Pl3tEN;b-<@ly14$t1cGH6I^u!7iu{!fvGm~zT&3l>Zu!jFu+6R-#Y~7uT>ii&
zlQ^Q422aA~9HE<yo$ezvg)N&ahMtQ8yT1*Y0orm0w#K&qn!AL^lc6ahGsnzxl^%Br
z2Lwf=@ZtFOJ*u@Ix;d5flGYAvj@pVI&-hq!ghT6$!J80#GDE{yO?~h3E}JNuQXclX
zDk6_9C$H`jWJjb&d+=C6k1|wrt>JclI0qHG1b;n9g7jHP?`AJKDpQzS`Kyh^)~HLo
zXc-&dI-i@lHyY{5^x<989l^9>dugx8V(-gBDn;;=zp~H8o7oAS8qG#F^p-Tnz&@9Q
zLhe=Zfv1C(5J|TJPKyDYf>(&d=TgJ!59<<P;!m}!68fl=VP|NM;8o=-oji6^P+;(i
z=azJu=@__9%tmZXKogGcj#iM7W8Nn?yTZ8LftHgp9V|?6H59>NxQ2b)a^F!2h6c$<
zmTl$oo<iC4Xbdt@IXJ@s^Xcs6oiP8C&^gG?DQI|&P>ksFS<JK(8WhNrhlwS@bCC2$
zk~ZxY+uh+Jio(r48xkbnNG@xOB~UF9qB0zX3kLp`@WYqj6NbM`Z^{mVWGdeO*#d;y
zFA9O(8KE}@!_B{H>m*SR2dS?K1os^QQ30jwaZLru1CPwqBG|94TqR8Plhls*&hcmK
z3`9BUV#a82HD0kDZ<q7aiN#4WVEQgB-Z!;SLp3p-w#Ckg^Oo14zEdqZsd;Z;!#85U
zyO6%@fqr)3mVw%ySCsTsCRglZ(yaQ;m}Ds=*2FbjsbAhMhlZ8l{<W)iDiGFo)I&$B
z7ia+DxXn>WWt#ssyPI!3i3aL=Xtepim5$pG5DBwtFca?%d&pdeQfY>QA~S&fYkA7s
zWLt(k@ylN3%c*K7Y4RAno7dYf2Rz30-6Q<)OgrcuP{eBCQo!rzen!Xfz-xr5%WwDL
zq%S5bF0~)7Td;8ezdt{aKa-wo%}A12y#f7_AOaJviZJnx)^vM_QUjG2z>;t!9!t%M
z!AI%3&jyNQ_AzmWWR|YJ5QFEn*%mMP3_Q8#bog(Fhu}lO>@Xd^)$Y{C&3#@5C8Vy(
z#zB*wpa0zIqf@|dk^UDb(qEyou3u!dM(6;r+q-Y+$)gbl<bG7(O>Q*iL#b>Wqn3hi
zfK+oh=d*uAxc$rX)flFcOfu!w<0V9H3*M+EQ1a7S9`t+fzGGKm4k85;y8VE5tQg}7
zpv(VIAVOyWg_{?T5L^9qJ_LGs8A9g3BlDr9&9>e6_`d;t@L3w=V?|Dj52a^iz+ua+
zUU)4XuXI&lj8`dLBYKuBZNR4&<0mok<oX2p$`@qO@#I?y$%UDnr~Go$Tz%(nX!Vba
z{I+A!S5&pv|LKaJM$P>Yx80Bmfu5YzsT??a7~ehRP@d{)^jh)+V-Wx?j!~&mPlvEJ
z<3r2E#Ws6ObtInC_N%p*_Qb;{zw1TIUID5IR<>b)UnP@`$e}h~?{>O!GT5}=9=H%v
zD8*e*C2Y#gP@B&)q9MJxIvAIC+emYGV2Y{a*d|p*|Ez%Fls<xi1RAa4Nr?Y(DzJ2A
zzG1A)Wwx@!tH<a9?ouzX3F@XoZi|jU_tpnO^X|wCjHw1ZG<Z{JKI^PVh6JaC`A~3W
zD68yu&U2??@tcp^HTbkL2lWedoBXgd|Iz2EQstXG&=~j9ncWgD7fK1i)EuG#C3RA6
zi<rJ2{kwXS*a>x7XtEselpCA-Nf4Uq6Nw<NQj>X}tIyP+*WVyJ5bWD6nTl31)sOol
zo}!)y)HimL=~5h`yT3j)%D#@<)4a@44s0?{gr3k?YXxK8A@Ib6_vHOUpN_t+p+{J1
zFh;+Jg&R8jsxuV4Ngh0$JoM!QMGi_=jI!f*RwSgcjYd(K|KAUF8Fa`z-giyT$qIXA
zesZ7&)I0Yc2vi>w$iC1jD*_VVSWDg{mxU-iW_Rsn?6*LX;m|l32K6v`ffWD)bKGqY
z3BM@btP^<GdS<sFfeikj;YT3!jt9mpp+gr=6-AY%Ry3@t@AKiZFY&Ghn(O^$E1x%c
z<DB!D1~a={{mnLsT#)0K?ry@4wgLreK+KNojs^h%k}o8M@NH=U?XXQQc}cgny0D*H
z`V({g9Agn7LGk?!_)e5wC`^EvafrG1U7D(#>b_?5?B`~oQSB&!)~wPtUurbKwjL7k
z_CiInC`4LC?=cO(=w+wTwi4i_7rpPk+yuL*q9g4wZ*@FW5m^NeiRszeF-33C%4H=D
zv<B@J^Y0VJNlsrUpO4EA--fkzPkN2Y>)N#9A6*KTts&=@Y%e?QlUyf$4hgw(pMy6!
ziKxu!Qp6)!H;gPAVDBrV))Ca1vJ<y)u@D4U#V?pFDnA|0#;rQ*5U8Z{mh`>*y!IN~
z)|T~$(;;87j07V$CcTI?tg12-@ShxgiQuK%!Ql%OACS;QPnQP~X0jm?=_s?>g5A)^
z<kY@Dqf)H{3R!x^EPOUygS6*l>o{Hu?x}f0u;kpIc|ZE847>C2Kzux|#vLr~35VfI
z|5!af>h!444~to~!E`xA0B)Z#z{J$ozw3xGZg6bUiri?7hQ?UBQLB?@1Zk<-X{e{3
zn^Mb1dOeI-ey|Qzr~Tn+%JR5EWDq>Lcnr86bOTE8Y8R)0t;tdO%_${tS`e<L-q94m
z*b;jqQ(g=+hGKs@&tZFVcNcKlU!HQ2a{k;ODWP*H{Jh)#RWZ%J>!c2o3`vK+b1vO~
z6bNGJxvs6FvH031LA$4B(Ra<RZ~v#nm1oQ#5Z}#03~8Ch^|8JF&#;-nP$eAz;&mzL
z!KXOFWY7*VFtRFuXO>X^ZZWB%q##w6=iY2=s9~n+P<6I@6OIV8_U-MMWZcz($^=l=
zbr9Xf3rvm}7c@g6(nQm6A5q!<Un|aB1<ejGcZaPjOu&?~crGo#kj(M~xkVZPQ%eox
zSCu0tNFp3mA@?_wm-}h!lEp0O@=kHDF&DXurMX1nNUbJ-&3I<<VYI26^8b~0e6T>;
zO-Fq}2kZx$5KsiVg7Ko}y-7r6&0c0UQZt?E6PdygA%JAFf+MShp)sE+xUqn9+z$G5
zl0W$I%MKqd-1(Iiv0@G&2F5T=0gvbAbyOvSN{HJAfHR*5_;RrR$urO_261}^lb+9&
zh6~x*GSjvA^>papLzZi7Be=-Ul$fGnXM>J|j@@c^$m19VL@yQ1s<Vk=Uv37x+Xh5X
zIU`)0Uou9e5#Sp;vha~U(Ml8WuR{KwE+9HX*-b+)7SZihW9;$qnL0x^PPn3E06CNL
z?7rldOf4@SPlA*v=#~xYP12x$;+JlRXuYLJU<P()MduDmW)5M}hRh2ij!6*bly{mD
z=$EwoR|OEeKy#FDsY4NCObdn#(ES`W<f-c`RBlKw!eO4H-64&1R>p|bK<P<Jp9QaW
znMBjUHddTIh*iHItq@Nvh6eFzO8T#<Z)3s*S;R;)W}bR5n$^oaP@~V#ymFpqz8UY&
z@i0IDw--86ZJjXG8u=s}D-IV2hhlE+tM7$q9!lk#ZvBNkZjMQ#puLIuHw7g)cM={q
zMFu`G&7a?xb`-CnC&1gO?&+p;w0?~YW`UD0OhAy2AHVmcrcJu86PpAw*0d^<CKU2P
z8r9j_GnSfAbP}`~!Rrd06t<m{d4vv`OKR}h4O@a7KiB{D1-rjb@0qb$0%c++^2f`5
zZx`l%Pmf5Qw)UYW2jPsqj?r}IAtzRt4jKR1l(%kbM#G()<^4)(=BOL=PdyAFdj^=_
zgwS`cUu~J>i{m>91(m{X1fzZ&ilRwI3il1|eDkA{#73`fX+TQe7ZtJsrsBX%bVT+r
zpKxJS+tW4o_2FA4EMwb|e`RSN2d^7V*_8if%6ny@m2>lmvf-mpyJTcJd94e|#or`r
z_^0kUqpe-XjDF3%8U`~b#~AN{XEfP4;vAcqkj)BI1?|pW+yh8wI2&z3S9i=gkpfB6
z%%^m4ry6tH59hO}VBDRR*+=q9vUAe}m_TkH1OTg=55#i^U}R+Zwe)!rjzMl7#kL*l
zi39J0G+q>q!mEGfvMuF2@xv@@V}g>47|uUA$qk$fVSs$NGAsYSW)<CRE4;tT86CHu
znm%(TaF#t`?y>qCcNEy`oK}Tl`GgOX!$Vk()Y~fKC*lifcQPZ3yv5VK5(~C#`V+_I
z?w(kG)97U@*<1o2ul0U2A5TYn)e<!m?pJxMJ;HNK2OJ-Uq_<E2DqDY+K`*HV@>YFx
zM^-+<kjbUKMDExgpOI)wzlVBnFrD1hZ!<)nfiJlWSIYmWU4yi<M)|$R11$1==elXW
z;etaRtY_r6k<$}9+fQJ7|K=}XQOB|e&L3N~mqzENhLt3$y~}V}fO*5GxtYBt<n9y9
zCC#|}2yCf&c#kd{K!VS=9q|Ns9ZKK>3=p`<3U2*!TdpZRH(ufKjEHD4D|(Hlcr8LC
zN9HKQtPyyazj)@ZRd%^GQZ*0#q;Z_Lz=M9x9apaHF5?()2oRbZ_v=7MOpmm}$&u%l
zj&i{pNw#v^-<BN&Y5)NVBB}c9>SGM6T;toniF2Z+o7O~K-{R+_Kt_hB6QszB_oI1<
zX+jO3Ame{9|LUF=Pi#r@Yz$x+yQ0-UC?4BLY{d2MA}}+lFb0Df`hf{2!i=rx|9|Ir
zYRO+dIfKz|EnJm$0gK2Q9#&qpNxe)0MCzg*AXDMr+pe{PAlf)k#abKI!MG=&%Z{+7
zh6IUboV@d2tkjs~w0ZID5FY3Y5W2Eg4hezh(vyhWoSQD95xDXd(ke&unS{pE0H8Eo
zp>Y%y)(AMr-<6%%!6gvFm;PMXuq<csHvOgtWB>%Znt4_+lj}3^@^PEvu<_foyg8zL
zAckh9<3J$KeUa*DYANw-XEqe}BNQ0Mex}QWy)AQUy~a&7)(c9rMOwR0&?FcfMAPQp
zrUxoFH!kZVRddMBokh?KtBI|^u?6X60GIpi?Z(s0EGjB(?six#TS&sGe&c){vV|}r
z*XwMB0*Xe=CD2((Y%0;=(vK3q-sR%gn8!QB{9JdB4kELPi71e6BF96ZP+IWk?V4E9
zXdX+QynF3KxO%<i9*5&)350m487An_tiWExF8;G&S$k&t-<^##$IS>m+XZc#e1Q<F
z*hP3)OZt+2d3J&Mh!r}#R2pCQv(pE2PVVcjVE!}hE-;n6UEK_?uxOSbKidGu>TCmO
zd*YKO?p;<ou^mv7r#GKB_SsW&uib|=5yB&|Q^nUuxgK&Kdx9u|{9#bbnxx@pbu8`B
zPr9cPOQAPw@|@O7<A(<4&^~GJ_bAum)M(@tm^9#9`NP%Dtx``KxZM!sfb2WbYaHGJ
z8~D!C+{2VY#US3ZC{=h{RqBS~(g#bcm2sXag(e7rf}Vw=)mym7QT@vX{0S`D1(dF_
zg<suC8>v5zP+&nRUgLZL(Ut}YG1=Ewc2Y?cQ(0yX2Q)@X>l>$+)Zi61)1*TV5W%}a
zf!1V-1cj}@XuZ=kP&jnEK)6_Xk}!&_nd?k<$UJ#;b5?5;qHWre^P-_MAGGYXP5f%s
zKeHM#=a45WQn9Vl{w~>Mt^6;Z-9GcaeM&PCXZfrnFPys`d9#EbO7x0q1)O-P)Gm=I
znZe*Z?n?IA_+7AK7|fJ*jVc(fN#AwxeYp`GC=nINJox12spy>5me8NAJ3ggdIJ7t8
zK#3<nDK9v|OM9B3?Xf$A#225JPUE;Q0&&V&Vb6{R{K-@!S&5elOXNP$$u@IpB9ayX
zUP6v;LtnxhoD>~d`8TLZC$`b+T!FlYv7pwSvX0bn7@J0#A$8mtfKvEnw@U*ni+Lcl
zj#R;<R))LkW%9fym}`-6u6|5Wz?qxZj<Rq|NCNV3+aXnH7NEPo1KA<}eA!w&Oz$qb
zCmb?3(WFWDMcz&%G8dgcn%6zb6v`U<0gFcub<yFZ!}J1X8lovi-5{Ukcs_kk{~9VQ
zG_Mvm!YHsdV}o|xkKm0Xgi7>8x6$h-$I`11%v$1Sa)%#<S9nEff&_Ka2<Pc=5Ve`)
zv{^K17HIzM2Gea|Nf?15XBe_C3nLUUnL?c-AyJ&^#+t%_>b0cgZqfp{!ozAZw8SkW
zB8Obz*LVmL`))9|i}EsJJZyUwf|$$*HEWIi!t5OeY5V-L+xcm8Dl6*V0hL@1T>fW*
z5b|Yr;NIQFdRhu|+r*vy@&bvs9d^i>h3z;X_&w`-{-FhmyIC=m*<y=Xu`Z<g<S_86
zQ$gRJS99%}!}AS+$6cVvb)06A`Y>_10)qBNg8<lnw|5Mk^}IttR*?FKZfhxrlsLEZ
zgj49ZZ;~p~kwZnuUxJ<mcmP`)7~!_@-u_n?ZC+o?GWv}eNE?_0*b?aSmwKcp!fsgq
zO@$y_{)ySJ#v0&I7<We9QT~9Fw&n}UxZ3_rHk?vqqk9iS5PnDDns?q1@#HYN>T-46
z_r`c~1@tv}oA*YK?dW5GBz|c|4^8ZT5#>LDoB=5UN6q#*Us*kK>~L0z?b0Fa<ry#9
z(9rZmEfh};mj=}QXAdQJ6v*F3=$x^HEqj<JXzqoI%z!qx)IvoR6&cB%Owz9^$8A$E
zht~Z%TG}D4oPmQ&pNt+%&A&F&S+2ey4>%fV=4OI=;q{WR+^wKY63pN*UxiD5pVh4!
zZjTe9T8r)*K1d;wXAE7Kw9=x`|IErf;*Uz*Z~}zc<vb*kUYWVrr<Babz)UJMU%j6-
zooTb`R_dE&^uO8^U36dsaegumT=|(_A)R&|+(v2YnM}TdY>+<@mkf6W8#ic1fwq3m
z{9s1cp;F|nVM22!Da9B(rW5vK&0nVNyu?5-4U3z8NlhtW`lF`?g!Q0koJ$D7{ffS$
zSM>ql85?)xGp)z^>@zUfdbGGU@-pH`HcEr%k7tbeZs~D8iCoIfZmkZ%4>s6gpr&~M
zC2YDd7>-(BWj(}922)y7;~rzE8!9+7Kc`Nn*U;q_HGI^jgBAr~DcY%<wr7xJ29n(U
zXz?Db{mY%gQg&2vcl^+~|7N0(-OT8ZG#!N#-sNFqaF37quL<u8mC2?)f#B^zzGxfH
zBR7q2*v!Y$#lp+s_^rk)T@_zHvq%3hGgO)3(o)jSh{7vkkVYh8HFuBpqMGN{ud6oM
z`H1f_D=3`Nm$0f?X9UUTVBoQhaXpe(j5jq~-8cWPznPK05aUA!kWaspS>xA^O&dmF
zpC9~;kwvngSjJL+*qK|434j%Vg6eR$E2HCp14y%6u+JXFUC(}y;YP!zM+5AE?mdN7
zM<CwVaVjVB9*2SUh=pPEly?i&hgWdb5+oP_`(^4)D6!TZ>n68_&Q03y;de!v=k`1)
zR=G%JXH(h#JaWVL{Z-Ae2)h?tP$jczWHK~H_)I2<t%VMPqFVG0gxAi{cJF9YAaxVN
zpGGpzlWhDsBdt?eCSWg=3v|48`V~7nW)!fj-K&FLP63y$O-N?&a>iLNWwO$&-u_3*
z>><l*ZJro-V_psw@(_Hnm-hkyU`2DAuN;9-@~ZW!1{mxsg6wHJWKV16^?GMS*?5Id
z6#S>NkiV(D`7xiAE})e&B3;N6CP^7|O%x_9>)@rKHi6g9vG&cVAI>?I`qxUg;8Ymb
zXE1IIjmh)nRTR?WC*qK?bp$9I8cUbGt%N9^Nh?p|bNdq*mAds5k@q{i_*Fex{uOZV
z>{yFPX*UxpD~k)EWEicIQBx$iNx|M7k03Sb4l{VG+5OF{rAbSw0kAgNoTgP-OV9$8
z<JkStW9F-lbATh}s2PLWPp2YZoR(B5qOoN|BXQ@-d08)^SAu`LOQrM$yFdTOHgdoh
zclVVpo?qCPCH4~yip=UBwKR+Ua+1@N##Uy)BL#Gkq28Kj$nt?z*{Vtc38#|^Gb=WE
zxJ^w@_n@&AK+B#t19#bp&Qm4@_yVwAao5LwNn4)zuIP$JUsqS_NU+`CRl(QkF*Y(x
zr!Bq%;->v2tEs1E>-Qd(NwW#{5Elf^(H_S%U!>eE!>clB_`}p*J#RU6H*pUAca;z7
zOq-C!fXI&oS&sZF_&9#v9`y%%KFseR0v2$k=4jrh6@r39CmHez5XCQz@wyM9^Mg&X
zk0EQ>Q?ej&bAe*g{k3{Ht8XKa;#S*`hV~SD*K&5g1+v!-D5FK9SnM)!8BI7KE38-q
zc6{Rh|9j!Qa&lJD9VckhD80Z|l2Lf;inac^tx}Xkl^p$8@UpMU<mh^l>J|zx^UQ|O
z@2z#@P(sB9w8`wtbuamwuiEPy)~Ms@OBl5o0$eCTcEc{exc{O^>Vh``wbZN++XzpV
zbFe2TPOlljfcp8mBkSkCCtKiH^d617dAI1~XtkL1Ml^AgOg+yK$Lr3+Q%k|$%T@P6
zsvQ!bnCfkW8%%e5KGuXbiieyYq!4ZDqR)Ya8LOd{Ajqtx7k<_1Kj8g7YWSWUt$Rs*
z(cjQrxUG9|YG0b)`obA|N~8>laBvtdik`>7;n1g+)G(cld5a^Cbhqg#(N@xY$egnE
z0K+I{jfeJi&?e;U@PGF?Pns73joJ?PBgCeBRThFg*U#;K=w+ZYM*W^Tb%=_^>2(Jf
z_upNeM7BZv*5ulW0h4ZBfCUJbcjYTTE1W`)ssJyNWjbtO0}{<sf<2z}HbS}tZp#US
zcLYluHgyOplN`pKPXb>2jCFd`Z>xc(a^gtY!}^-;u-g9WYwdk_?As7w*OK3JyHM?f
z+wa7uY>H)541=$>%vaYu)gzc1Z%45bd`-ZK{Zok9^S370l)>qAiv;tT`d!5wRLdRm
zBnxwxJHr<@L6>&kxnlLkDO!XMM1l)xqEgVa*&E$b26i~lWNuoPCwi68l>+TU7t!?|
zeucl^L`+rA8?mQZL{-j2(zl!$gmitjR_tqrIm>co;h*qjCE4WoQ)&D-V?gZ0U}R3X
zJrR^K=DH<s7OA?Sy_P?vJfvWe__E$u*Cf-b@V9mt^T=;N$H{V^;+oPA<XU$UIv2v(
zJDwIhaY6RlKaI`leTJ35s%Ngmubp^pEl~8j%Vb2hQVy`QPKZ~7#CkeW2iq${t4eob
zQ<hm#>AWC1-2bQNMjAeh+$1ERJ`weE#1<svU7#Ma)YVN}bf5v1xRIA#_l%bZEm}sK
z<n`~{g_uo1`IhB`U6+ge{X5C0>6B$2YUQbc^bf@^^&e~)4`xxI^I;I&i(Hi%2vY-Q
zS?{GeoIXZs*WMAiI(7(3Gny2=K2KDwSS%Npxx3{cA28a%N6l8G4k;{D06IX$zvA@-
zz8_4hZ!V5#>SWNuw3flGEysEd=3>*_@yoXbm4V#Lb7uL(fJ;=K*!204>YYYfLJWAc
z+(FURK3Q4Q@Ma^gqRkM0@S_tC>Vmterw%sai1Ae%gIT-Ur=DmUz}*?Y89lBX;Vru$
z7|O%ILcO70iAweI9%`$3%co><79u3-#1-9-R2jPa5-rL8$|ITB*uGRX)td<8)Z^Sh
z*MV)=o27kEW0!~|f`wV-of?}->)|&RIx0<Q)X3-hmsGE6&rugos==6e<o_jYyExMh
zhEQoG9XAlfr@V|u+dGrxB!B&Bn?j#5El%PewfD7@zDMr5QMy#aPR8d`R1H~!p#iNT
z=|W>as^KA8-eUEkpLX)B*ZtfkN0Pq($42AO?7jZ0cWEy>YOMhzS)3KFn_US5m~9JZ
zH^XE$#gW@l87XafdoAp7dliHCNUgbY;zMfLEo2o-V>_ovy<IwsJAmBlI_$^ockm>V
zz1nu)xGJ}DT5AEF*d6y1)_S2MRN5Px$Z>LF3%O>73k|ykP{9@LQ@H%W_NBD!vV&MP
z+4`=zi(U@gMZ8<mm-{$QZ>7t>pV}U0WU}J(J+RN&2_H+_LU1vnNetf7;m1LMN22tR
z4y;*{m{T26V*2LeghTKuv<FJteZ7D8owNHs00PmW6F!3#5t<tj7NbCHn&Bp*r`9R;
zm|tSH&fr<4t`BiirZZ>prZl2VhRi%4r)2I0aNL^Y9uc6kEgh2sD%OhFTW4FDcip*y
zs0p5U{_xIih{D;Bgpko`YB(Ynb#ihn*J-Y=3j$G560;*%^p4IE>*A1i?Y$bZSx&yp
zU{GyssWVg0GltP9th0Yy=7L7PJ{Z)Bnte;6tdO?X%ZeRLhSbt<`H;l5aM-He%xqQ`
zGJxG%0a&u6o<M>2${P&yOuZor7r}=Ljr)HM48b*lQ|@Vzq+@u3n<!hkjGpT|y$RG~
zF-A}qg7m`E5Fd<eQca=b7v}_=gknRy0B(=B!NzV)F+74cHWdGFgr}}FcSBSjG|Jk*
zJ0$$m6;a1a|Bwu+3dV<|px%B?&Xz(VnLF3TQD(>~_%A*3z_i1AO6D8A=pXp;Y4kLJ
zRUJ#z@X|gJJfq^pO39>|1dh%3IpVJ})$QHYY;=>1u_Mk3t}}3PcfDpXH5OWp)GjA;
zPju-lrtXu*rPg>K8(a|XsTD^=05<^=xj3FqO_H1)z~C+4Yi1p$I@Sl_x}qlJdlOM2
zsjT}UHl$6{qnYDUQ~_@9GhVV57&FwlWh>Ci8HX)^0%?dzx!h)<h4*|aT-AUae@sKy
zk~ZMyS*dK|u*E$^J^&mFt{d#!6g?S$)6d|EoTShAWE&Ti;<7nqS78KNhQx1rPxLgw
zVpi`}!nuUW&LG_7lE=O%175^ug7MCwbe-~zlN0Ws@#tlARh!2$s11eEQq_3r991hF
zBJBlOxC_{fxd}<7V9UT+qfkX-$u*s^O7?kdGDE<E%VG<oVkPfXGDni7T~I+)eeW>{
zDk1Az3Ijt#mJ$gK2FD=LXxhy5=(bNYyw)=y>cUxwXCn$WQa4pd;J<=oGdW`wmzHDN
z?|nbrm^wfKR3(A|4`ybh*JUjNJx|yqNQ19*Y@`K0o~P3rEm^v9-;zSao<Pzn(&C+9
z92;j1FUu0Uk6<Vhe3%hlOz}CBZKqli5~b4gZDy{=HGO(Kw$!-oxv+N2Vq!zT6Ug$N
z2zd)NZi5ii4R=xZcyoRc3%f_&@#cm>=9Hgj(>v6oUSyu?{wxejz)M%>eJ=2xUya1o
z6e&{_L(NX(#`k1(@$nZ+=3*vetP>wNgz`=<{)_EMOPW_z^mZ3$PxsN*!v;SGu8Ykd
z6d8VLaCj2Hwgaom>w3+NdApxUJ3DvMKnNXPR*(_?E$@9aG1?7Q&lqi(_nLChj@uE^
zbs*w-kHy!2pT4Gp8R3KX3{*K+Ay_wZivphOPyac(JufC6&DF5F(nIt~vlncx(Kfb=
zi0@4RY4t~{xZRA7ulevaU&jE$U^7xwIx1LofQ4y=-sFjWDs%b`{gb%Epaa4kiZdh*
z{UgaZzrK&`{CTdUJiZGAJOw6=)9gt<VFYnG5JQ-*)Ss8gpRsF*O1HXmb?mKWjJSFb
zX1=nD1_?*`+<*$YBhW}0B0gv}s~BG=x<!j7Z_SQ17wXFVua2!`GjBLCrlxqPQ$5}y
zG8JZ?lCMX}-a!y3T1ZR{q%~fD$wk0{f2=f_Xy}TImr{U>U<|Zz?!bWGn1hhCtk*-h
zWw=YZmFG^w2i4R!6K?TYBhu3n6MAIVTC(MN%=H40C<KCw;eNf-2)KPg{Ui?+l%7%}
z3jPFJ2<(HGw#fhNHjzVS4clu<db%wxX-jq}qbt&Ens7R7PtcAjuQLzh^wvDg)6I}o
zfl}rmy84@YcAh%83I5pP@okPKf!o*Y$Zrjnl@|6ev)Z%b&bKc=YFPd=rf*AIL+p^-
zxJi!}O1!)f1ruuvY=#DocnjkCObn{dwZ{&!sYk_n^XmqaQMxg9h4y?``YCAnW4MBp
z0oebPp6zJ1{Vbw~{Bwtss-mW~?9+l$>(4lj3IB3pz6*Sd%hKRiDwlcivV6FZKR_Ln
zB0G=T*q9;|!u7pOOY$<1pq4g#qJ-fiJpBNj_@bdIf}2ZdJfb`401;STsl}S!s-UAA
zQE07t({*@g^*Dg+*|<zE&H7R=2uH9Y$Hs)dxi?EulwaSsBRWI^-$&u8l4voe_TYk;
z*^$}#^9XBComT!lEn?o>RG}O22xezb0|3!y54x|gd#HM}+kkIdggI>m%0qaG6mA{U
zLkUDxqB;m;DRgE^LD~aGXEA<4U&8L!kvAAMm9SHGVgGKS2!s87EZ?zn6SQW+85){@
zvS8I$VOI$)%|y3c#%RpW9pDn(ky8#Zy}5yiM!XOe^K_)P%e5J!N*sd(St*R2@<`L8
zAo>FVdK38&RL!gRP1>COYm)17)LIvtdrXf+;yJ}1i;#`MqK>vceks9|(wyMZUZM%8
zOhEAM>|L61fcW&MVN^btB8nkicoFJ_<%Y>%-ibEq7uCGkfa#w95;W=pq7c`B!cIn8
zRRy5Ora_Nf00}(xM>E4y+l^qO#_AdPTYw9lv1g3c{81M|`PLH`%^fw~U^xVWFoKK_
zmA}}tU4V7>ndaj(-^9ipJ<xfa?&TA7u8!uRlUjn)LHS2Hw9Y}juAzH8FniI7OtdoL
zPv73JrbHo0c`lEs#d@eWEaER=l{r9a{PFTh(+W9iKhl&Pv+iyT6#F=gL+#ML&;i<z
z*$!h{deDDDS&J(gMKNVAtB{F{tv5%pP6$Cyx6IHEMmk>o|B3%MgAU9sOd2T0_Y&+L
za)cd!ffpgE0liq4e9^M_k$nAfxrh7qj6mF;yT2!yL9iQ2D_}~BmRq%P!;T!a_1f{>
zr$?!gjo65f4l1BxyfuL!cP1dnOSj}W-TIps&-3^Ldza?!a^(TpAd^}^7z}gDSYINT
zvSS#gcvW)wrdH}`Ym?XQJw?MfNK%AO38-&t9<J1K*0TM&yyzTlz9{C3p<&-I(Y<l%
z5uOJhk0=vGp3GPCz)VTf%%3FykZA@*eP4eno%T2)a%G*k3-4lcn16r}%+=sska099
zRIr7^&7H)&#9T=0CRy3lGbsP5pHnB`o_{t|WV!L?2k#{WR?!KEHGP0iE<W-JOrD5}
zq0#Zggh0+9>(`@v08kbYv;aC^HLjkPPASE?rAH1Jrnr*s-k%@sw`_5Y=Fu%3o}*h$
zD<|HgqDepb8<u-&f<&aY4MsarqpVFA#usw7e5Sm438Av@5ya(pC`gwCcGiAx1QG$)
z<<rEfr|~yc=S8!TIv2kT3r;^IB#K@=9$J@t7!q8E0o<M&pGHje2N%Jt^&+)Uo;<as
zDB;)BZN&@LNqbk`61T;L#gTjaW4#}}pOR2^>a@u(j{qMPsOG`_^LLIbM70GYp*@9p
zXwz;>^-_E+Fn9!POl+EdrhqAttlAc>a1{ypeY^%;mg8}{#8aq0hMvH^^o1u?>f_-#
zNM8NhV~A99WV3AfPGnvH;c1q_Qitsj_zu>5KUJ3%H(-F-tE<a*e<ky(#U(|Ej0W3^
z-3(RJh*GZG`0wzemyfeu)tD4`bvui{G4%DmC#`n{w9c>$x=GRNl&04(7)dDw7<8dm
zG86VoT-SczbJu;S6?H8^HM+459MqDC1+UAyUcnDJCpo)%X|)%GGz6EbJidGZdBGA>
zi#q*NW4pO|tuxm9j5@Iu;(0p$+aBbj7#Z~mMEBE`cIt!JMX2^q1Yigp6N#!d>IZ?n
zTf764e1ffr9rKTuYC~o@&~%G;1M3}dL`*FK{5B(Y8Ob%BdQWCQa|O`i6C(4*JSwz^
zxs}h4vLOogxol(88a;^Ruj0G+>|LQ$>UgESE@<2tTA$M*0%N*zR|kZfQX7nWOj-FR
zl?f(nWITN<sJmI97*0@O3A2%GI<W2RHpSNhu>KP&+l!&>OK+$uIHpzXaB=|A&%Yr3
zWky?os5k?LV2W+gr(ISZ{>8F5sL+e)_&Nffy=6mZ_5778P5_m%F@7QcqiR3d<X(Y&
z^j-R}A|fq_?`%G5#PO~_Q0o>s+vQ8M;+XibuW6TzyH>FXrTPw<3M2EOTG^+dd{LhY
z4*l%rF@Uet*E{V?oSOtM&A8u?=sf^Rw5U^bSp_fsCt_wgKQ>sN6)w?e{37LFI&`dp
zy%Nt7-N`eT%X&LZXdopx;CX`&q2Nu>G@6Q2P*jd}h*rS}ofAj^iX^F}CoO3JxvAMs
z;Ti`6)2~zM98l5WE>;z$%W$8H(Aqt1h8-<yGd`D2C!BUMHSvQo%TZkO{E{b2AulsC
z+$rR)McQYs#Ma$LwxXTf=e&1oj{UU^xbxKCa3g+w^;lnDSCZ^`Tr4a4VnmgFC7;hx
z-Ood#Of}|Wz=>cYzxkJROWssQU=90Xaagim9WX$+&A$Waz1o;G<)M0ulFOqLNe4Zo
z*y44HrdcEI19!%5MmZgqC`4Zh70#S9&E!>hy*885(4lsp6t)`^zVhCI-L92a7`*V7
z<Mtye5M0xc##-K?{ubm}3RmAuicqRrtR;#YkiR+>5e7v;Tr-~%wJ9PDBS)dHBx*6u
zsHZY$a?twzKmwZFhrOWLqbVN*l!L;duE&8N(Bf0-#Z%{aO)u{QeBvV%ArPa(l*FPQ
zQJFOYEveVReaw<P4qD$fa$)tcPGsRjtx%6zjK1u_UBHUiV!Baxl?Py6*hk3?2iFrb
z|Hla^YEVEt$M0C_Z=<C)I_T97bWA!R)G-yO7k19mp$XM+y>E(}))m&3e+6$2MaRPL
zy=`CPo$7ot>bPhkR&cIDSs&l>#rkkr9<rz49h=xS709zzq(~{-6&)$JCA(y{!Q938
zQiy|J_C&le51Wnb=4%^x>D-W~R1Q6lgfgS}(%v+2V!wpUNHnP%frOvrrad*rzDuWm
zZAdLEQ=$C~w)r~E$2=V6*kvgo7Lx!AgRF>Ln+e&0UsB^f7}4+|<X!yZtvOdY_Jocj
ztsCFNCpqw+kZi1qrh$b88C)K$K<&n&SB>sBQ1_#SeKydpfG#Smy)<{Ln$w|&3DKgX
z+z>VsJLr2s7*lBsBudj*^wEr&MY_(X7+}Ow`gh9L+nGQpxVH%~(M9UQ8k*qr%R6;0
zHDI6-lpnj5&@BaR4HHw2Ioa!nmaph3kwY-iLBlDiBlO|!kIM%mI<S$!#H%;4@%1@q
zc)qEVPSqGR(`Q`c?eWgmzu99@wVEJ;77YVw647GyRxWbmp+r_wSHXSBl?G<aW<k2J
zF1jb7UG@X0kFDz>=jznd{>{A~cz8wY5ry-YL^g`@-J9Wo^4_&u%#`5i2emuya8Yxp
z79SR_*$WR3L>u`<*g%w;5sEL=qsKiMMA>?0$Tt3D4flJ`7+E$T{BtHA!LI*=!QG!i
z3agVPqeeC0%?$xl;k5Hg(vm1s?kPhl4U}#vRO0lv=NT!W{s9KFvGWihD{o87_EYRB
zD@Axrp`23Vg0F&OC9=5ZT453Hg2+ll?so#d#|K*T+W?{M%1PLe8076fsB8wyP%s}k
z7rva8seQvrVv6_HrAz&_FKLT@IU)ez^Pjt*L9K&0TmUL(PX128A8rXay@olb;96`7
zD}*1NhJ;Gx^a*VAlB~Pm#(OLSeeMMm^L-K=9H`dmT>D?S6sBMq0$A1LhfL9)-?zRL
zF1SUF<|w9%e}w+9LQpm7T;WA2p9&;uhWC5uECX3w!#Er{I}GzkuskItR{agQTxWbJ
z22;zL0R?(ix_-g%9jK#-V=`$tm~RFNiwP=MCoZug*|9}&j^n5ayQ9O*%{5>Wlhc1f
z@6qh`^opHVEkn@7UmB%UZ=lnM`A>>btT@{{S&f|3cS{RWaJ-u}sAjpdlKLBJoL^WW
zi6SO5+s5S%N&#NPQQ?+i9zwV;PQNbfZjuL|KMv#SZtvU00+O_x0sF7F)hGf=4!~oE
zpC{ZavO0q^g2(*7aJaFdi`Yc>I)OV}{-O2$8|tqaCu5<0V3d4D-aa7_V7xRoY{6E(
zo&2upGM}^^m#367?V@(JE05!g?}|A~AS=ZwKJja*F%XmHeYC$>3XEOU`BA9Q#5mYh
zz<FHuv_|SjYR283kS3Q-R|*{2g>0rghv)M@Ewr|0bVrW-=^9sTA2MKtU667qt`?(w
zg4F}zD06%ZKDRnvC17crxffyRt5tu2!DtoqibW)<G=L5!>oNx&X#r~Mq;Hp4(&-f$
z7_yS%4$(ecmVT8GGpb}^V&Tj?kt|iW9&}bUwTwt?yMiJ)KOU?_dYdvHPe7yR(XwT(
zFSuq2xDn_0GJ!5NF~jz<&nvnai!E&Ic0k<RgzqYrD~=*nAc9>n4iYl}fY(_;wan#A
zbER{1gj<|;tanoZgUDxw|7gpAbsbA2KH>Z0oe;99mr~q^#JlbKDs)pI4#R0A(B;>;
zAmz``)XO@)Sr#4G?t>bwPPX!QIYs@ZU3d2x_sLJD&|{Mcr(B|FLCB5wsH|7ftgTOm
zHlK=aMPb-oi+ID_3*p|*?&$8lprZr2wY#72?;Zhrnui7oxHh~t)tRDcgvWM!v?Zhj
zd3T7I*^g;Ckz6ORJQ{r)%Q=7OpzR>}CS^#hvSp(ZlXqYf^1o)wGTVEKpuVH-&Ul)G
zu)KPWh~lJ&2CmhK@4*6MRA_{!w<EVp6fwKm`CCeNRi4KaA{Vrd*A7u!p^Y;krxg`a
z`s?)I-}U={aSKtQ(&G$WU(Sw9F_y@{Cje3bF46Gw1u6MR$|qm!6(hOt^Roh=rEqj>
zoGrZ%qw0q{hA-26)>ZR7k86FXK))7kXF_IQ8Licz|7Y7DZ*`WtLu2@1!glau1gs@v
z(vKj8j-((#Y;(I+CkIJ}Y^w^mt<-8K_@v#p<dzIIn{?7Jp6Y<V>gg}qQ99XaZdCrc
z1E4K(uC?#9Kn#&HJTE8t7=x1!zAojFP4GjLjfeJBw3qTHIkw=-j4z;x8_|ZZHblDa
z?nt=N`%+8lNTLdQVWI(SQ-|45XOy-<pTDx)!UC;z8&!2@^6z`Bvdc0V+TJ@Pn{Hrq
zKX>8(R|E?d>DKD$<EQB#5R{1jf?G_#(I<RbC4NapOAh9(Bxga>^a_BG21rR^mQ+Jj
z+u&>TA*DjdZs|t_w4Ffm<3gi5S3dYqdx`?^B%EbU=iV~H2Vcy5zgV_ds!MJK!oelk
zYVV3hmL=(ubvs^#_6;w6r0$#REBwBvZ}IJ}a5gt#QKxT{dnxX?f5=0j2mR258RlVs
zR6yPebI44z5m7_p^Vb@x(6HJkz<Gut2<nEfp?GLwD+k>OuwrIFdCJZq-<E*n;)E=s
z`>Px;R3*xCO)?iegE#=qXZB|l<`()E0&a4@-*08~MXU(Z_g6xmO+6cpNEQMQ;BO4!
z%Vu+DXd(V6B9G8}_IzFF#WlNdv5L&Z%5Xu>FTl|E@xD;7X*Lt(N{iW{cz)19|4HHr
zm&@9+jW4BcM8CcyjP1%kTj68Pb2ZiLqWrl=`JNk4^1Vc}1~z=>SGLobf#sFUZhLFm
zgf7)NDuqr1DcKZH_vYyjk1Ab&iHHu-Q`CZP4G4S~_T-oMlnbeDZulfFCMmC?!C|z;
z<(hiBm>Mj07mW5Rrg))nkgujqJ#q$r@_%n={M)+Nin98>+p;T)cn?+h*Tv$Q*?|$*
z08<}rd|~<$TB+7|q&CuX{a1BTDBqwLAg^CyFt~W057vfs#y>mV@NYg(qJp;r6pyYn
z6%9X`yG*6Zev}s()vRX!d@tU;fnnufF6dI+iQTp(Z7?b-@H=+NQ_N=II=W?kh1)8*
z%o8vDb*O&8QafIZH-__Kt#85$B=q*mlJeKK<#s4h>2QJ6ZPuvi8!Y46`_C1b&vQNS
z*2Kh5F2-X$Fxk_)xYg^2JbUBwAs?uB9)Cryy`du;;_kFh*?SwT+=`*$*>I9Sd5zM9
zq_U5mH?zJ&&k0bXX1DBrXHZ$q&Z)_EldkG#pi1|AI-h%0^m2_*(u+b-NK5c{j}8nV
zz-=Ne=E#p6aiJcEsUbV<DExEL=HBVc`mqztNEv52gMZD{Pb^)Xo@;ZEPJ1&{T4%BX
z6v<7wP(Ty`+&f4*0GX3~FYi;E*XtubkG6wE)x83#YcSt^08tm9dhm?lDlgi6Lp}zs
z@2Trsf`4NF$IfVN(CHv=pS#3`g%T_yUM3OpGF&Cw!uj4~T0Fx4DonPPJ@41cT3Kcc
z>)x#aY6Fo>-z`tHIAv#fm)6?g90hNNnQTlV)nTCg1k`}Dz9P!{{3FS11_)6%b-}j3
zq2foRh5B_#yGoG&puFopN+|kP^Gbs}KZ#OM)u<InHf=S*6Y`LT_>HoX*7v99H;o+c
zT~cFY=#uVl-AtI4fgmRy%S`2LR}(OKw11UQWAKrLZGTv(tWSOfz#N4B`?e;D_FUa4
z*>I3>PsnLX^IQ3F3}BQnC5PuAR#!H1O$eK^z0yO1Z2Gtb;^MM+08JCS5Asgtvo?Pe
z*W7Aa9cy_y<cDJxB5VLQb~*XvR$_}Y@Y|EFSwcyc`c)}Ar=9IbvgS5W`pwGIoMu6k
zAN@vkazAS3Ej;RKIoI_XCDS+yeP?T<hEpfM_r*gDLyD59o_Ba4Rl0+{-eb;hx)a5F
zyKoR};25P&2`_(+E2qol+cF8(78luIiN--AMF@!Nfzao^F3t(vVD(+&i%$Ei6_1LL
zHc2LBLyKE~dGftQOf}<#yaus6y&lCFJ*=NEzd1o{+5VVuKd&2xpoXuQOBl@p1xy>0
zy>eu+(ISHO|E?fZy=|=C<RLJNPRF!##G0<}NKSIWx*_*AZJanP*AZa_UIj5#zWy*L
zZ!K@llBJ15>f&I3#%=H^_AeFEh064rqpiNdIKyd>hc-0Ro@8y{3glkt&y1kBMG%;3
zsEClO@3=+HTr8Lq{=>!telZkpMQpU&bPYe4;d(fvr(0H<vzT=jCLJ2y1I$me$OC=E
zztn~PIUwT>zzhfVI8axBQ0Z^5t4Zi8YE=w6gsjY(H2bQRbWi@i@*%ws{8N~4=o~ul
zYVG@uWxSX-{f;r+FC&?{)l@Mhlt9%74<^+ztynDEx797A6hf0nK49iCE%nG~4Az|$
zVE`c(Wp0o20r@HBi7bK4hI?4z!stYRDfW(p8NurTizAqTEGq;VRxu_lW4vWfl^q=0
zms9vK48;UT8ru~E1pAK{l(l<hrcAYPDmKI7HE}>=Q}BZapQ{R3M}6x)_0G|e)gwTc
zp-XCaW>_Fb0q=j|W9bOh2Td&jtG=i?`)N$s>@=1Hw_5-+QWkG;p7lav9ol~+QmJWN
zjITGV2N^fQI)oqtNUm~TxfJ(<TA`)5Q5Ch^-@*EsP?c4YrhQgHPqhe`dsg@m+Q8n;
zp3#Lwj`NyO_e*FinK#<Z*wHS#OH+r$DdXvZoL`%}(sQO6lCSY9Zem%^_(mA9VzET1
zFfa`Xy*;^;s<doYje5ul2Nnai=zkA*jGKSf_5Ti<_C6kWe?dx4spZd9CfA>&uNhBf
zlVYIfz2f3?k>(J$3T1pIz83y9UMGp6Cq~2jq*ggxw+r6|sn2btwouP6q9kMYa}C7V
zL;VFQb||1sOqM?|Le45a7!!Z`y(kZ|MI@~t;wM2+vMvl!hl&odU-)()28$HzI_-z{
zsDGY!#)+biV7Y>q+4N&7dc!_+nJ{7YCF}s1y;@lOaLDWej8YSyW}E@987Af~7$4m0
zsTbM4+Xe=J;(1`CDqpl|gsBtwI`OchAaAz58jJyF$vgw83B2vhy22yE1j!`ugQXB;
zGih%%8rckzI=pum=h)@jmgb&qZrQXc16lXKp@W(1;IK?93VOK#pf^X=%d?52!*JG<
zC+Vpz2lPy{{R6gKTdW2g@^!Ty@|OTw6$c~xM7zDV{%8H*xVrvM^(3vS*K;U4>$BW{
z;n`AD8_8*U&_11y;y_%16n&RmZ&jVwgu%>J(H?V*$hQW+e7RlOt|D_+_&MX8tb&Y#
zfE3m*ZE>79u*coaIo9HeX@UGD$28_IrMIGAPpjW14yt!&UpNGM1bcoy(+3%1yi=h1
z%lwl7Q^0mvy%o6&UqbNp$gDM1AM@+8-!ls@z9AGWmv3|a0u#?vLbCf#RX{i4z)Zr)
zNNqa+CO$#CDoYCL%Ft}R2LtJ#X{}>m>Bu0e2F1F9aKFB4A--uQvw=u~aV1I4`Y~C>
zHj0>`pP{=Nz#7cHmMtoP<O5R%d!y@SgQ23P^mY-hIIe#TVHZENR_cL05$VuNE=+Z&
zTWQ!^`>ZdeQ9xDX5dP#}N8L9bhh^sCkpu43ZBVI0ZLOf;S~Z}b0tVHpTT9EHU?@2s
zz-(MjAPOx+l^6K0iV6h<SfrG2k$r;{u~B6QPF0nkC|r02D&L8;y!IDmD*$#JOK&Me
zG-HRCo9i88<4&Yl9W@NOKF5&2m#h>`(KR`R<YRn_2U<6X52&tM59XB%rQyKVWZz}n
zBJ!gcQM<$7OT7Ch@UZV3!1J$Vz=~UcLLvnX%qP#*SC^)SR8jkp8>XmdJG80_E-D`T
zc@%FV`CAhO5~#Q&7eD|fSn!dlYdBDNxiop}bpXd1IWBMV+&D<53jL8N+Fl-657WEd
ztn>~2KetG918JzH`Cp1)Oi6=kRM=}@j&UJRw&K{3TaV`osWT<=<PX%F_AsW8O@D1f
z#*Bk7B<gFQ_w3sWzzbYA2mWh~>tq72>F9fO(7Fftz26?(xLiDK(-iW3*1sS#69*G|
z$-QMP@}JR2yPbqIB#>o9X^Sa=90vo<=^oqe>*vurNn&{YgpavJmZz+=Furnx%M1U?
z9%pgKvS4#ru5rF@9KRQKNn2%ggr3fC84Pkd5z1f>2wv-YZ^(T9+y}SO7cl*zhWr*a
zUQ4T1b4N;*Qgb7XCMRgFei}wzKJ>*Ch7H^g7!oZ(VDpxfNc6!uQS55|El-~frTd$0
zhf2zDxJNG{1n)`Eb6swL&O%{aI;0$Is$SPAJqM%*A)+FKO`KZ5I68;L7osk258|h7
z1Bni^-O&5=H3k@@xi<9@uzX*aK1tG62ytKT{bmm?h%Dor4PQxk+O#S#<SXWKr+2;?
zJs2Zm^H@%`))@9jI*l+;66H$XuG#dj$tb1%?rbORj^fS<!M>%;Qssz~z#`Nxh_CSx
zvD{3ATt2n;ojD~4p7}&b>;q^)44;6X>Md;>ZsZ8FgMxIYuZAmo46}Upj`6OTM&QE#
z-%%Xk^<A6ItrWd>8xQ*q@NcgFN<;+TIo6arFtVL&vi4+f_cjW!J6r7$<pCXY8_FBa
zC3mVnA8B1g2ux3OF$iO`x<{!$-Hh8$=T~A_;H1OXO)cLw4aSdoqhFPca0G`O&FzRE
zvW-eQr9mZ>i3ZE;32%&PoM;H=Xb#jiEaV507hcO9Sm3*mr;U8jXay4e<F5en>xk3b
zZV=6%SF=_n(~9ZeaYpgut>5G_E`k!yG8!CwW8eOJJeDz%@<vv*c<~O}_!DMv&d6*?
zjkq|mGRTUynOJW_nF1P@Uu6pin}eiMiIPSvKXrDCA|FP`U`=7~r4WKr`-cADdhusj
zN}gw`{TDo{1^a;Ed<D==Vk>rL^<i8g%ax4V^DMwfRSi5XzRZN<>1kpU3o)^{Rtp;?
z2hAef-NS{r{Hx8yrH^FZe|H^qFa>kHs94t~SdNA@BEQR?N~=W=0Nh!LoE6PN=uGYF
zTBKI(DhnXK9tS2Mj^*8RxqaW8nJoF}(?JoQJo#Bdt}VRw^9+3335vMzF6!mJToE>o
zdwZaDxmP*K!TJ|o-`xl$))Q=Si$n&x8>g`@3~k2g4$#BQo&#Vx(QAj8H?ADEQT0<2
zsL+l;Y0)RXz{Ovp_d*vSo^qjlT<qN%A@SJqv5V{%`+PpL>M{vjl#ki0_4kzme;eVC
z^>n;Oj(_FDjZBDoY?WX&iLr%bN)~hbvSPhYP-Izqi5%k04Eju`-cq2w3+X8*N6FYe
zr0iu-(%==l`1LKjUCfl`@<7MFBy~%F4+}NisScZ0>EsJrz$MbLhg~?aO^KFpaNjnR
z{)DtNlN>$*;viEHN<6kDU=g!_meM@DG6oc^335h~5<9q?cdzvaO^y}}koZ$#5)1?`
z3LPE`YGR1&mUh!RIn(6fbBn)m<YJjjvzjNiI?%5?NnjtP;<Tg{r8URKF(`<&gL3d^
z|6`yNRcJx|`(=WiN@&Z8Bl*(3KS_Mi2?sflA7UIct|aD@$7(miiM1amnFHuy`}tFK
zG2DcGBd-t#ZqXNIb(W!W4%eqP;g_p?{2*CrLWa!|8}YW0sJ-|?-IIz&3AZF<%Q@kZ
z&|Wy&IaFf8QB98mj>f&AgdC;u_QkwM(It<s(O96-l3l7&&F1JFvgcuiJ+OO&P4g0t
znjz0q#iPvVoZJ&wDQaFt5R75ju)zsmLgwY)45KkNqGOx23N7nIJp5u3eRE1MDJC;w
zZsrJC^u-|c*tH=Ep19T9W{jw1aD1!=r+djR>Ub%}eGVCpQ~`6#d>oufSbj~$%*$@n
zWFA^seB_A;`XUlKdR5J_6U44xF1e?+GQgaS)&fz$)!W|0#<z}UZ*z2j6wki7&|@4~
zf}ABlt<7Lwaq9;8Z{pbwEmAVUV~#zV-l1a2d5juTY6}7-k4eJVLC11jk(Agaj2;~5
z#v0jM|CyI6@x6&KA62B}YgsEC!Er%BL0J#r>t*T?7xtu=CE1&FL4(6ffzzgLzuT<M
z-Edes6?|yzJK@<8v*C9Zt(qSqu+`#(3~$8P<*||L_hbI3+a@UQY1O+CXMH4uCW%C!
z=VPrmU&8$bjavs^DX`TE1Hi^6o#`eed-A(P^@h9}Mb?9|on3w@+()b%FHt{NF0Da#
z^=+1N_><3pQnUMfoQKE}W7n*a-9lyx#<X8ul5ISw(yLu5kL+#E7sh(6Tq7Ol1gk^Y
ziWg>T|NNXPJ`Y`f?n!V4;Ba!2Jaue;hDC7xto-HDnY7dlLRX<2MTm-Dg_)^(4Jg@n
zp5#lBRBIMS43i{41LmRq&9C7UY*-PUarr_d$;gmt@r*OKNrWg2>31eCLYH~H*q_{;
zOAkqlF&&d=9dJ=a;V-~ZtDR0c;zM|B0bhKQMSBeh&d82Yr^x$vS&*;6>DT6q5rk-V
zL9z}V&<et%D?_wSX2G5E2$(OreDw&gNClFr%M8Xs2o2~_v)FG*w^G!tm>=s{Y#>&2
zk53(4?<oU4XMM!=Jg(ye)Li(`kuZ=uIt<}-5acv^ILrBC|MBpClBkO#hE5Px-{=-q
z1ImRMmlVpX@9vbBP9`ue=e7MEfFkqli7+Gm0y%Ao*8X3UlJFB+jcw{71rdcFl>)({
zL&!&9yD7{E5y_jlH<pQqQ2&v{FiET2s#&mQfmc%@hISrEF?rur5~^8V(#Ys%Lhl(Y
zcqQc=)vYlE+ucuuEX}$}BcLJQHIMzorD<>nR&)5Ogw8Qi2#*$qC6MUykJj*}B%5Is
zKxa{x+|(fiQM2y2_a}Ob28wTgjz{ba+;h8jU1^~7_G`iRWLQJwikS4ky^VAlnU4JU
zj`Xa?fw0hJSwCsvBV-wP-gqNt+U0R&+0j5n8B=jyo81@41Cb4yflh@2Q0Hhjr%7Uc
z<<-Nss7B|32psTz4MYQ(9$dZacF*>6pXA1a8b?yZ&j}8ZS}`l|G8ni5w((!_4rm-#
zRS;v9E{tM`IKsuuP4RbO^l<P%HR$u8*u#fF#?#8%w}+?Q)R2Tc1rPjfJHSuM4LZ&=
zB)o5l6an`O9P-`<DXNs2?{jmMK(!k%QHy>^0rf`qd+RA*^z_sHc?>d}Tsb(SfA&C0
z+@80JH+&j9&8G)Noc9-OM+=CoJ8g-|IZdCm1@BI)SPza=I-m_W8~oA-bcj`wovdtV
z*lRD#%(>@jbLJQToUvs(fBL`{g7V-QD;<s@=}R>C4t{5n2iNB{4&QQ3tHYkd2wS}I
z^v&4lqLp=F6qZBCqS194NH5=s)eon}yMRo63>rSA9JSdvsT2T!&7P;=%u~gzD7wR?
zz7No@Bb7NKoA6AztQD@jqv-v}2V4%NRu(LnVnC4f$_%l2F26CAtE>|lqs|Pc?E#N?
zJ?m!S&Z<2}tbs0-WLvBXaSb(*9f_2%NGMrATP|Vg84~8R;w?w+vccV{DSLB%HnIIE
zGs+gH&M<!(RBcyfP*1ayvjn74Rsm5|-?eU*E<vH*az7BdUcF^bgb_erR4Gs&R)O~Q
zg-S&{453kHZZzfe*+<Z8<6zdRpi`=;`_s-zJX`oB3*eKoY=wz|9P$DheWTZ8v3|ac
z@Yy^z(fyxyx_d>j>CJ(bAFhU#<vSk5W=W#_{XyFWMnJ!FW;%<r%p39KD8=oQVnU?F
zz{}MAbS^y|-6~(GTijCxUkRddQ^G6p4C~GHC6>^>&VLPwxB#EfC4Ru32Y=eQSQR4x
zw%5P(=FiDiW8&X?P7zHl_;Mg79DE+c%9bkEx$255wBK;c+kjLiaFtRt)wX&P=HhT!
z7L%@+w!x{M(JrMigk05JDKr~OMsVaf_0FtQ$5=NiToWuJA<067F>jdH*uI(>4i?%D
z(6pl|n6%NhvmB1CFyvp-%T#>C%UsNzP3PSf-0Ca#8Wc}jEM2V-58hHjC%&H|!U~?i
zt~w;!LGuNHJ}1O#J1_{Hx}S`)cQw%NMQUD?MFX`pqcN}T6~(4J))#Csw8O(#UpuJb
z+qj**9qrJh%ce0)Y&=cU?-DpZ{<h{l8w^bN%w&M+YLiOXj_yTwG8cGfmD#?nr0@<X
z;uqSspq&*2m&ndwJdI|Vd1PZ_ez3p?^;kb`przX&bs_t2NK!yThHv{$*W~K{pJUF6
z%AvpW=q545pODY1)*Vt4(3>~dFiFDx(gz&UuZg9n1paM*F01htvbxTlkPI{$f$`Ad
zS)QXFq{v#)*t<*bG@gnZ!K0cX_G*j@D9x%FPslV=+e>xyG8OqvB^UeW*EF&ugxl`y
z;5j0-uf=YVa=`Ky0fpi9JAwPMjS4dcn;lfjX>%0)d4i2OEh!ttz?ril2jE_f;Q)zL
zk<i%j<KPX{<c8VzZ`gFI#cu7-%&5+hE@G(46o}==Wwj9=2z8V6O<h?2I8hY3o@kUz
zvHeh5vfrGqa`n2i?t9Ie&`i-Ld^G(p`W!j?sToH$#On5?*+2o@_QIW4zdz|1IE{95
z1+mmhk`TkMh19m7AUd$*puj-D3rDCD-ROo%4=mf_9j@8cg7>ZpTU&3Kss2`~4+PaY
z2!cWi<=pG&hgU@6`7T`%j@z~g)H@a5A=GcAxW3z{ZuU>)>c*E}u=}ce-`q)R4sE)8
zOorm7T3tr(9wERMwxv8Yhg_C;#KfhDNN$u3LovIk(FvrO!0f&>-EsHN1EN`B?3W+(
zTqnS-EJ3qz2*XZ=U&oA9YBlf@Z~jssr<ilHH79Cm2IJ!`=f0xN18ev|q32hzyHt-g
zie^|Ze7DnpHh|=Vdl<h0N-BA^vFMNZz?``z%Ua>01UmCk71@msYV^oY<8`&SwI!8C
zLlPR%?bkJuBt)v&OxiRAy8+7jo4nWiks6*X-eEm#){*)lx!E4`1IuiJ`8$+&0R<|6
z5%n&$BiREsBUx)Ve>Vsugz`aV@)Y;Votnj$ID%N4qPYv6ceR{sB6qCSp4I*d&ea6d
z;o33zc(lWc2c7_X75kvf(9vOY`c#&Ynt0QkA=RR+5Wu~S5YhZ2c18^9RGK{=cA&uS
zi@z)ywjF;?&8#O}IJ3CI<+n+Qk}ex!taW<p{~p&{F=-i5AxcD8KS<aX;?(tmYVEP^
zFy=R-eeNM#AzMBF&(pr>D;?Fq%{lT>qCe1^iyIuTJKg*gB%{n+r81u!YHq{zPXaDm
zdSG`7Q<UtQ%}#)8=ZhtoWUHgJzn>QY!piJbh|}+$ZBjqFvh#5U+d1D%Hb>|n3`@+_
zWHX_}u$=hTR$y6TsSFmcRt@D%*7?s?gs<P$UW!CXfhq6ABGRke$?m3RT^AXDz(e!U
z$zz6Np8Ce0K*iMK`e_iXxX)(Zgwt^*`ru>-<YE3A2k7y^PewVev(d=$f^CWfL1ZZ0
zTc_UfH#;O<C*@wT_|MTe9=~5MlR(sc#hbopS3}V*c6Bz><RfWN!FjVm%xXXzbTu^@
z$}J#_)XWsn^Hr#jVdQ7Sn=8&UW+w{Kt8g$2puG<=>v2Ym^NVpNV%##<(7L**Cw6w;
z|4Ny=3Kj}8>U7(rP<XBOUuy|HAQIgUv*dl3{nGadGWO*trSCPbUNU?uUGHKAWu$pc
zD>q&HIGRGjESjce3dEz4anzFI5!by2<L(irkn@)o;WRoR2l9Y@V4|KC`Jp|qCUe;5
z7nXg3jZ;_+?CfmWO|uCWWUI;=#PY%v$af9*)Wh~9I=KiVtnc#jXf}FexgE<DrMvDm
zD{rI=ad!jo&V8^|O+bA{b69K%=w}?n_K#2!^Unb51`?bWbE@BBm0&Fvdc-mzpxO$y
zimy7OH;gFIU3N7Nlhw>!98()zI1>4V<X+#*wk`VKVW}plRKNQ#UsI$;#930&)$ar2
zc9>Vkc2B5B<>zp=j%*cQvjlFNiU|r|dBi$*u~#Y~h5`9l4JiX?!^+XuzS{f5sz$s!
zJzh*&p+>+Y`LO!`emSf&hba=kCO%C`lAB8RFZ-QtZeU4nyX%2be3eLL{$U_9h*hGl
zm%-h%GJ8z3vhSDlf+u#dp<d$J;fxI7916D#M=R%Y&&za#M&2xZf#BB}1KDXkobb`#
z`&TWwE16*FIJp@DLl)hHbs8Yp^O|Eq|0|2<pEfimdTWz|(K3AFJTen?#TjTupz|c&
zo<S)-AOo!+z#0nOwS)uudviFGg45w2I3cL|%-YCU*7fZAc!KPKJ_SHuApW;FYj}Ib
zW!fELzth^>;>Pj~aQ)yEws3}8-?wN}eN;AvWCKE~*(&n#kI_u;DBYMp&kk5>M9P>$
zD!GO7XPJfq)9l*9b;qZ8uto0Q5+R|X@xAQs>@Fl?2TSYfuwM&uBxzTpJ(vJ9)7V_Q
z7l{DdgP{nNIr6WS?z6sYGeZSZP~=jEh8ZUyd4$2$>E0DkIL{Z!1-)!(6Mz-rRjk>b
ztyrp<=UJ6%g1KJ6{uqo$Vjr-!IU;MttF`pjKaNWMY5j_gaKWa<v>nQ+;@{P*jkMQl
zUFUY5Y%;P4*GL28Yg^~fqb?r09aMFGYl3Evjo<T2Z#wJQ20T0wSxw~OQq1z$8w&~{
z7tf|QsS`SZBPoh$d(rVoQ<bB|_P7Tex8uhTF;|<qJ+Ii<_~lf^swkUPi6ki}{JClH
z0q8;YC{xZ$SFlp+m{`x+DtWp`UFI@E2j_QvPRTtjJ0i_;1(z(jF(D`Oz)Nj$n#{oh
z*i=F6O)zvO{a<Z}?^MDlF2_wIjt(6fV-|_-n=rLT@LMPqeJE72F3s(u6lN3%HdG9_
z5+>aE_x4O@<n){r3$_x<0QuwSjS-3C-nNk*7l$*&By({7LmTn2jm<cXp$uD9Gwh+k
zI!WhMVK-{P;fCHh?$2a~g-aGW7+5V#2?FgeG59|_X0~T-g++jc?(SCD%Mw^3s$_bl
zsNjajhm`;Ug35a&+NCxTs+))6p1y|e>BzFeGEdr9?z&(t9|7?%_EJkv;JGcn3wa32
za|&bG#ScGq<d+S+6Y_m~1Y;@TF_7d_bkNOz>^W2b*ZFuowJKrNMImS<P0~5X+`;r~
zWGFCof<euCjHYSQ(YcrbNfMYX%28<35MW`75ctCfxs>ZxY!;jZF5aG8@E}DRHONE$
z0`1Aj-7_J;UEyGs>l=<V=FVspOanDtVjBVBI1Qw(JYx*<@RU?4wOkNatR+X?6zoH&
z`!>%a-;LPLaY93)(<&PVFpptlO$_KOfM4|;3?Rgbv@~w2tbt330QxEvVWt+l8uV2s
zlM4o=#TVov$z5FineW32K&PlbZ9v3PWYs$OFu`cAxqvoiL9%=Q(KpL_g8>KEkre8!
zr(hBkFTw;7>Xwa-5ntA5#~l??2fXbJ;In|DqF8e4YCF=e1?VUjKn3;{&<fk9<#z^8
zjGct!7{VVh(|;-A(zW(c9T`|fgD)op(sqg)P%~OmTjo?njmE^Qjt`M^S@MZ3^<i#3
z9X8$9)krmtY;P-f8hJOu1+F&uHcBd<%7{#P>nrN6l%3l;*LCRnXY1MwW!)&b{ZK<W
zIfb^0MB=S2;*Bxf^AYnWNCSbQts^z+C(fyE0Xg09vDo?PPem7T1vN08Z)Vx@h<4Qv
zoP~3BJ&K)&LA%I-%7u3xl-@OP;AHwr64@YJ&%e&zqYNa|JVd%@LBwlJ4y<*3%Vmjs
z3Ut?fC}Ua$mzrQqFC3*`5uOK=p0b|*P51Ho*;|S3KBMJb??Zkx-TOjF75^4WIDo<?
z9-zXf9;7hgdt>k)?kQ}A|FaHNW>aS{*IzU^fxCRJkU;0ZSYZf(kj)I2eWx>ddmS=<
zqZ&71@l&jJe*cbd^UV%}egtu+Uzmz1@fY-P8BvO=1Bnr0IzFq7NRf&+Gj5wloO@V*
zsZNSV$cvVHV<!44vEZVQKY_$uJQ_Kz?R5<E<y)1_(uA7kx($7smKI9WSdI(@wbQ9)
zqZwniu+b7cw{DY@QNq49;fsD*ict;(rQc@J7E?7&4#AXUOyc-o&vJUvEoDvOWZN7^
z`R1+|niIfJ;feCw3ocZG{w#&eomc-*vyUpP7;MXx${6vUn}>L%8asijMTF5)*|==%
z%WoE*bLousFeV`<B5v|r99R>}XBsS5l6S)z3=+&{LIrlY73yo%1X-9bpW3$^d4gpS
zTW)k(=ud&YCa;;EC)55+ZN5aT?iR<6Ttry{N_&@yhl;l<X=%rd?FXO-T0#uH<$ZUG
zNvX&5oSHx=?iLHF-)IbG_sSNr(IY}?wM1_d;Azo6_Lnf>RoXx#0R>6C>O(g|3soGW
z{`xnFN%)vnzE;|)>bPT5<+(gyaRC6xn+^fJ0L0|S^%Yr%NJm0c$InDl`c4dE(`PY9
z)#Qpj<ffvxYcI6X*2pY4fKdoAo0<rK(>sEq0h;w!ssS}SBzH_s<&~9&I)vQdV=1pY
zT!oA*1R@DA`@z>wF?tL$fRKd|4t1Cux>`}#%V;U~R#iFSW@B=M@m>(|=VE#|b~>=U
zfV{0}CP(%*>3nXErdx9~>=6}~v7i8uklyh3KU+5BOmpx^7=JRu>bmDWjp?1SA5Ldp
z3%A6q*qeh+ndb}#(~SJ}rO^mhUW8RHNr@fEX$$pux9oa|k?pOCJqS3G<?3VtI0mRf
zL}dl_iKcr-sQR4ugRTL`!gjCA0ZiiOQhWMb)#jTFp81)Kj&?~46+HR-e3%=`p;Ces
z6gPHY6V96_R(Py$k&xBp4|b|l@!|@!W{IQkQtM;0^r!Dx=6HURTCg870@i}VmVWzb
zQ!@@`(a-5AZ$x_{M!S)zev#*}U?V(iysh_1N7nXcrDehzXPX?a_K+2yGbs$6AD+`T
z5>n_WwN#1QMt4Omk@yl%t1)Q!R@|_&{Ah--XK5h%%{xnfT-=a@S*OvQNug?xUxE^(
z2%;LG$(6m2w_<1P;(JH5zKLwZFVha6CS-J^-gNzkgc=HGqFc!#qu^hBb>#pw)<#7%
z6t?lJKv(G0edllVW$GdTS+!yAFOaU!y>wwdH@#9&c7YxF|33oS0f{7ZPC>pKair?P
zn=8-<f5?ya2_|bRJD2G>_a=d-G~#nlI)265x-}iE_o@eaY7-A~HH(;@PVP?k=pbG0
z`VI!Ca4s-CFDJKb>m?Df_z_Rus42PWvguX5ejly<&~vifT6`e0(sm|)8v(Y=3BvWo
zkrHJ(ml=V7<MseBu_iY$=nLy-+7tQ|a(}#Nf9@8E^-Gpf<~$YAQsl;gxp%}Ir1F|x
zi5%i4bWX!ag|)qgD0H3S$k!qo$vVdrELFz+usFK{Rs8)V2>@<e8xoaN-Ka+3f1$E$
zO!544a*x;BIP-!G;yTCEd#}*W7}1AiLCE@o2@l#RB9jF=5hG;fxBeakW^;^+$(Di@
zQ7y*<7j+?6ELp;dq#3jTM9+w>dJ`oGE4V1EIfIEe_YtAT`SWT|C!`{S&}Hm-IEs4w
z#9+zasz*IhvA7Mb4tV8^mX$+*LEq*JSSf>661BZ*wXj<gVNF!@-(4OJ+9$Wu-~Vl5
z_EB3<uY@i_QeU96V+cyP;WczeG$(+RV3CNBEU&PaX<q-Lor$xZ2e)7rvU>ZHI*<(y
z44#hT4_Gn7aR%D?`dmE*!6<4!1SjIz_dwbjqq!$%!=#JQQT;iHEj-|CM>3~txP4K<
zM-v3k{yo%6Z=$^tfz@=X+aooAT)Z9Fr*9BzFwhDV^%)umd5fw*UwS+X32Vw|)yjyl
zizEDl|6rNC7!2}Tq?Eax?wII^xhztR{i8m!q3QS(qHE=#El`%^{C?l&j_xcrm$fuG
z1{)Eadpwa^6VB1X!RKFU&0zoYwRxhm;#)kM8V#<^(5-v0+=54EW4sg?@#|ly9zBii
zW_wV1^q39jl=sUWJ^;HyDw+pF(7UnsY^E+Dl`hEPf*)~@*aR}&*VQzM?T)BDW<EY|
z{0X(u52C;@I#(%^x1^+ZIyiNBeV&@_fp2t?gp*)DAQeWIxfa5OB7D>O#<o?Ewm5td
zUn;Rf1n8oV|M2*^i-&u>-rxe4ep)G2^~z2hnQM(de9o^dqN0@tGr`#{ltIb)i)f(l
z{$GYqWwbXgpoxWj`J}=>{fyM<t7pkm2M3hhf=}mrV-TbUa6x&4f1kGqJ1Sww>4H5|
zO)`#%@Q{%5i_wwRR-Cf&tsFV(2+C*2_z31Q^wN&|@qyKhS4#uGXFq%ZLVE7r$qriD
z-E(mB7w7Kpw5JDb;}QVJoL0yPhY_Bj*EFHIxy{6EV?vx}^|U^0+{kHu3feL81ufOs
zfECCdo7KID&<GHcPwK8iK#R&KQ4ola4SZ}lgb5DCWVLUqQ?KP<R2M#+Sx~e|(?e;$
zz2k&PF0MVmWBW<3-4GE_uRijd*+1a1eAvEeMmTL_CB_;=EHN<TGV8rh!!}TQwN)=K
zqQ!Xytb{ZGGeFG0_M|<bW=eps8x5~eEhxJZ#_Vo1?vtddRU8on*H_`=&9;+eigBBB
z1C#(T&~)iqm!z!%Hg<SKtthz?r>LH;6$8$g*ehma1^E}1-_fpfWiu>GPU1Ixd<~dE
zpB@NX)l#f4cmW`EEDUMP1gmO!d47C#iSTe(W&(B!l$d(L|E-;AS1IXp<JLM}O)L@6
zh~x`Q{bkY<&jq4!Ss!)YD*?_IeS`Id^zT4E1mc8&K`YuBfLh$@TW{335Pimt_dEDC
zT!GqEZ?TfM{x-5ryEkCf^xz2=oxO-~C5chuY;>BYZ_`*b`T{#R>bvhW#rLr|Lj>g8
zip3=>mT;<jCY92L9zFn}xZaE8L8UhCVZj&OJZvFcsXHvPoXBp6te9XiaCWoQe-!s>
zKI7dsum{v|J+{Eudn(Oq;je%z)?5M)H%6f4ewwv@DcV^9UFg@LC)ezTQIU#kU453e
zVgIANj3eU4<jAUX0?VgnVi?^O6mutsliYcM;TVE6XxSjT<tHd8BvJ6sh9EIQ#y>G3
zVR?iR4aB@?c%Kck6FVH5QzI~FI&MHy@H%IXzYO{W;};F(VfNu;lAad@Es6;Vv?3lp
zNrCezhMN^Z0;fwqV_a{XVm9X>J?8`HA-xIQNN{pDf~1Q{+R9d-(-sR8ko(Be38{&z
zVJMtQ1BtI)@QwECW$M%{u8@PxQ#{NfOp^bnW!`(wOkx&LFBDyjH15h+6Yyiztdw|}
zkKS#cDZgc1)aGG3SoXu6E&|+%KN;L@nS>nW^t5w42@aP!0dSrVCSJdd=g7yeOZCkJ
zxl}yyzy$FkVp$XgSWxD}2^V$`g>~S}8iq-V^#m!{Vj+RO4KU{4J02eco;ClY`VJr8
z8EkVZXlo_yfpn?{$Fvh`qw!Mci2&+R%0N$oQzYWgf5=8IR0fZxH4tLN{@y-=1+a#!
zq{&RW^TDSS8j&o{5<CThrN9)Xw^vay`uO!HNS$@~h@~JaznLQp^%7^PYFspvA(I3&
z4XqJ%uB*8dHLt~bn4`CL)v5FlY}!cvrTtEJJ>+rIa__JY(1pPv)Zk0M$wp>s>aLg_
zDMSA%UQG$QEu3`g$o2p~Rd-({W?4Jvqg79IX|-Kd9u^KQ)27|LC(dYS&7faZ<I4PA
z=0;uEO>;1=&+ry;9aLP^!`r*;!<Y=<f4x|kQR(47z}|bv2p*$p9ojh=v1>Z33C#;p
znhr#V11!X*sCaZz_Dq_H%n{C`ff;;>X;8<9Jds=&W-1O;nuKsAh1EN{B)gVv)sW**
z7QR}4!6}0qgI;4UB(q}^ea>n2D_CA&p~pat8}|L)opO~GH1yv7&@F!lu5~Bz75Zuv
z=rB4sCyCaogLY%QHD6t*AD7NN8Arqkr!O{n$VIkXHVlp%<FzdMK>A9Sc;#9B?#@9i
z`z84D>0aYqoeU_tbyYg;e$6@FJrs#M^*CSJPX-K*;)$hd4)QFy%lRmv0aUM#I^TW-
z2^NNQmHSl(Vmr}*&OK{K8c8OLKy*Z4n_=dR;E+e{)<{7rS_BbTK<R8O)s<|@P%{*c
zJcqZTQ(pv?LhysNel8$Yc}3Oc!;BW8N46fsys&34ha-cTS-a}V>1tYaQZ{1zyir8C
zd`8rydBc3S10LTjNx&{39so~cw@|i#7((pwuR3wm@rNzF3=)sW;~#nSuwVo}SvCh|
zw!R#Qp#_WGUjnLFn%VtnQRZj*)yONHlqAVvN9!1hRvpl_$muI7cdh``f0+$-_p@I?
ze_Q?~$|6!Sh*R_TwD6S4uFe*dFkngGX>jA4>BP1Bzo`_Xt}+!Q36UPRT$v~oX^QGu
zYZpICYt;3<%fyA|hM_c<kXANKBh`T9C4PdH8Fo*;+~Y3W{Wl|Hw9;rqG>tTOwtrwz
zjw|>d(7uq{e7)-=;RMR;<RStLy98Q$z2K%g7#F16r`?mNYR2D~f|UK$Z7B|FRc?qZ
z-anh6rKp$j8Jvm^EhS*ft6<73FxQ7GWz}G^%NDc^e!X65ZpG2~QEjJ2bdJI+{1N+2
zaP3bN^DOSJZgtl(Xgry|*ep*lOwTy=Lw?b_X`JK{p8L&R>l~95x_+oe5gV|M=2g;q
zm+hW$&6rSzE|*2_U`ts!9kKT~ya==8R&Cqo2j0@MKuY&ct_0^y+YV=OjkCxbm`$r{
z9A%DCq8KdX)F0pvbba7vMUVg6*XzQA%97v4i*np{LYIlE=3oQIYkXHH=g}Wffd$r@
zYC*;4&22ocDFrVGDsjrAAC#xWtk8j)&#c*<jy2!$fT1A7xdrF8Y`u&z2NFjEJe6>r
zdjtQR?lKYfZ&sA5feYidYtevewblNJpAs4_Nv^2gxDNB_VA`5dLwpR%P5|@xMB@S{
z%C-uziZ>8P40I9V9f7GR9x|v2nfL9h>WM3iRm-+)Tyu0YQ|^w=<n=Ue{e2CwveZ3j
z!^KC6dg<8lofD0w8qBQ@*Pub$0jG>9?BKa$nQv^)J!|hB6LmXJ_ZYlCy@{@F+xZ{}
zwo88Iq1_$7hxQaB+`Lf$>)&krPWX*UOpASKJfng)G)P-!u1B3z<=auoR;fQ+S;#m4
z3A+t1xDDnX8V7I*gUz*_d4mt9(}Br~a;CE-Nn;&MYNI38+o;zy(~%D=YA?Bige5f3
z<}weq8L~5-k+RgTL2!V630VpigEkx2^M%wEzNq|hM#}D_U4?5(;87nB#*C9Lk+ri8
zt~1m6wnKM%davUH$>KPy!Y>HZkURWoO$1;eouau10k&YJ`qO39{sOr^a1J|ZZaI~Y
zC4~C^4|+;_;}f)rG>#O?6-*wc`*+GXdc;mue*=e}e=P&PX?)X^So(&3$OLqA;atmo
zR|ANk=A=s&=Xi-^8a@)^tr<_Plphj6&kLYlRDjelsL7&xecoG&Z8E7HuXvU%*JIo1
z)XMUfGkz=YGTcoup%zovI5vRmQD{embr$>#Pfh$&q-rt8QTr{;FlsZjLet)JgMg=M
zIV2(B&KM})I_`jK>6WgHxmClCP70YgF?3ktp<f6*jXE59i(BhcDpacpuv6y~a18IE
zUk)XdsYV!hhI^W1p?y9frHA0df^IvzYN4ym3)NL%I62+b#TF=$MvupCP7_@Z_rB!#
zUqUPDS>m(-3EaAA2CChDhHgj}oHR^mvbt0cr&g(JxtT?6@vDq~4_$sRPs>R<<$x95
zedt@%Imlkli;ZImn`_ylzWg;0UO^m8mI7)edJyp_8>r{b)j~Bqg%9=X<8ml|V*nJA
z716GC_43yVuQAMAur2cobO67>q3!p5o2~Z|^z4+=*D~BNZDU!(E*$ZIbd(Qw+im!u
z&)um-M{Z0pTIB^rBcyE`y~L9)<b3CF3<kZ0uvH6E(!eH`8l80ma&T&nx(4$SZ)Lkq
z>2Cq(PSv!n4u9&igiFDDb0T)o!lG3tAr(X~c<b03a)$P^8z|M6<%pX>V=Y79Nmp%U
z$Hd)X*G=PRHR{KQ-`zy7ew;G09?j&?)HpR%TWC8Gu`(NZIA#hkqSJaAu)t`6!z`P6
z$lgO?3!5-`b_dyrz4~{(y%V``mEq42mg`)Wp`f@EK^L{5@Eo==0<Yjc$FHt%l;9e1
zMg!>2dff&B3JO~*@srPjn)QVczrist=@NzJ%wGE!e=Ux3WcxybLT|qIO$-2fhTzjn
zuwti$jDvN(h@*axEY)TpcYN(wgn6OJU4lSs*iA8FMIQbS7`w)KJ9ct{nl7rqYe^1~
zlfyx?vA-g|H4WyNQyE|be#qI9koNr2)w;^ZZ}jABd;{Z5D6B`}hIZCQsT6lVqd!g7
z$*OMGRfeayo*A2*78e$&;b8ScKvL9M?DqZ05f!d&!&4yZV93=ApWX4Tq3i}jV;oCO
z6!pVw)tC#Ir`}yx!vJe4$#RUh|A-E$%6~QH?Sfe_5A)rK&QY?mV;(OK4)m0bF@X8I
zaS(PmU%`kU(G=hnXBLVDGl;ysilH;+UM)=REt|e}20}m=F7VJ@D+d`<0rKJdMUDFr
zfQ-U$!#D>rZ$Z*VSW&CUIR)1Rj3?p#OGT)Fi8tECMj@OK5`0TP+ybF5NaKP4Ph`}S
z;oZQ^i|9JFb$d?%FnDd8vyC3Lx8*K*R~K&_ii#+S{>Tv&&?VWxesrk)@Pgo?rf$6;
zaJ%k}oVj&t(88LQ&{|jO)-`pr=1Du0RanuiR9i-S9_E9t{vw-iBRz}zld?h*ZB6j)
zAL{#)-<Db!u5k8vv)miIOc${wD(`{+DW%+xr-0AwcMXKJRQ0t}$b2zMLJ89;8(nEV
z1^oQqu~>Px2|aRE6QvUBYSv=u21T*=khALuL5q+nzKPQ3>ZQt-%GC0edj{c6VJ11v
zl9Lj(BA=$3t-DK@DR6Z0x>`THFiE4T-MLIaGDg6?mNjq<xlbot0Nf5U+vKn<9@Tp<
z(L31?lsu4XvEdOyOrI0Gg39T+5b<*Y-#m~h(IuY!{N@x~c5{>=Af&(G6Ec|?dlZ(Z
zTp3p~eUmS=f;K*BIg-B~N~gyNoe{cejCEV;D|BrdzmoZDR@S59U(=NKF=xs03WV;L
z>0MxxY{nl*nF4%khEoAx17<QBD7v|Uvu&L>4BwlIF@YyNf7RemJ*qbnNCv^#43$>(
z1H#3e7?SUbzz^%FzI85|5VZZ3{Z&rEDM90r)0ZAJ+m?fz!{ky!H?dF%`N)BdSs;)@
zK}$lMm3IeAoA|aG9vHNACvT7k!Jf*;CUhsbY)?WAn2|M^G8F24D|`Tw66{j`58CnR
zvT?g;KcqOnvRiniNv1aEEt6*jGY{cZw0|pcB%kA=9{pu;-LDY=CFm2d9%hBm&!A(*
z^BSAelh}U+Bh94rLRHBiaW?XA^z2PXVfMKwrkPWCwrz%%mq)TROF%8+NPq6e<6M2R
z)kWZcK8hy<DWDNuf3n=qZ!XGi`bCME*Ne(x2R2}%F57q8-y?l}u+b3fx5!FxuogX8
z0#b=ho*KLyt=e`}PWQ&~WY%jZA;z(3g!_0iZw}=9m0c)Ho?Fpo&8-L7;?u$FaE;rs
z7}xd5g#Y_Hr$f;xI7@+6Vz5;VG0@`>Et_@YF&;yAgyHSc*|O^!g*&()HvhsL$N+7I
z^Pcq02M_6=oF?3D{Rv1aCR!lNncW~^Jvrgxu%@*4^W<nDqut9la)uEf@4Jqip?BSk
zeQG&L>|(%7#zLI0+0mKfWP-48C}6hB^PI~o;c1Co8RkeUOF@TmZ^-i{UhO@6)nLsX
zK~Wnz;^KEO$U-;9yf9Km8|c(H*$FtoxFysiNs?Q^df=WWP7HwboYjkE4?^DUG`cqo
zshnONB!4tRu|w>RKMm{uUv+&pLHoPowiDm1!cP`~1!J4NrYo=X`<2Zihh)0TN3oq9
zx64#|suly?2*?eBMyc?G))EGJ!Psgf@6(BQaK)NOT^Lg|0Ab%VpjW-cJcH-mhXWSJ
zbrQxXfAD&RW%L#vsk{ctVM8fzun7m=DehwAG5@66Xfd^x1_GX<*~E7fr-#bI^czpT
zKA3PaT`uR&oD9Z)4-%+_ZNY~v8C%e08Qx`q30*-{`Lv1^zllrbTzz=BA=r_1h*F`S
ziAmsSNxdK$@Wcm}Bw`ag31B4B)KWBqdCgqFp=LVI1kS<1_jMhe*e!f&1wz&ch|N;k
z`N67Db`4NGNf_h{*u{4jI?b8BVOhC<8kGVBHVkWzr!ws{4XLRV^?1NnY>5r8_Aop9
z-d}y>iD`Ma;o=tMteC`*Gajyu1hdpt;g0<xwFAM-jeN7V6G|^_h&9zX1Ntq4MRpL(
zw^SX7oHjFZ(m-)e0W_ek;^UD<b;=~%F8O92<H{LNsrIgh{27@eVWMLf;&ig2pP~lb
zBRX}IGM^tEnGbny@w|d>ih;OAN*8((C#o_;EY5ZR)0c@}zw-rJ-QUO_Cs|6rvQBWJ
zDB4JL7q%&ZUYj9fPjDRs`bI^s<~3@0xx`ESKx#N!)$_N>hFNILtBXmaU_CU$n$>+7
zWT<!Q&sus$${73tzd`|rnkY{0qEyV^cJCD{T<!K`Kaji+HV8|$6o{iUNEqenp(4=N
zp%OT1u`WIjx|PzhyQF^p&ob-yEN^8)7(rJ7T9`sCC-azwd7q@1_cQw4<M9+WSM9`<
zJ;#<9d7A(pRL_kt>N|_xDgMX~e#NFqi{d`9dYh~9t=`g3OhKQR?ThJJCO}O>Xm)h5
zW_;ax<j=x&Qs(H)(z7o!FO-8}cYO{Cv~7bA+hcy~a+F>p$s4Z2_9Yo0x`xY(d_Rww
zh2l7zA5?+@jqORTTAmFZq7LtAeDtzVjIwhm=Q=(232>FK?k+#t>Wf3Ab~z!ZK<42x
ztVU`%mXFsR^(Y4{mT#1$H&<TNBLx@WFjhQC)Q^HBQQaDOr2Wqu@@&a){A<Zw6sxEE
z-!1WU!zG%6G-5R#?j$FrFNfb|C&Q5vIWT4a6_p#X>rx!_=s1s&9pz%P*9bbfpyl{W
zAxy1&^^#}_A>oqF%HU*V3zm!x?|d}m35YxqaT<tqA4~P#<8LSH(ChTCOExu>^LF@7
z+eQR4xU&!G+y^rpWfx4)jvtQgX#bOzdV^eo{FfzC1UT&{KJo;Dl1k?r@e+w%m1GR+
zRPzS;Q2Nm)tRZwYHjR?t=@I;BFMD&fK02`s$d%MTPC7xn5ILI%l%ZjHvs3U^M&$eB
zJFSq!D#kPz*)rAdB+q^-fqQ7O!><>E)8)mBww`8}E<~*b$&)eXOxJr_lVudIe5LGG
z?S1UiD+Q#iR}3}mvH4b?gEsNG@U1OQIXZ9Vq7(;X6Ep*PNOKO>XMRzZbmFd?-*mnW
z1ji$w0}+9wgl>y4z|y!cU3^K&sZeu9sHm0#Vw;D`u@HZCiU0{**8Bal?UsS0c!#>4
z0yWXJTZF2FSPXnMq#X&|!39QJN8^6E0!LPw%j_YCBRRXuTzfOdGcM1>VP^6keS#W4
zI#lW7V!id6P}0A&m=i8O1eev>b+DyS!Rxw5m5R5Z#@|JQGPGgk#eL^VbP&`L9)Ch7
zcgG4V9|WSXRy(Vdg6oGd=r+4f)e_r-T>za-*N|PuE|wBMDGp#~r>K16DMCh-$gf$P
zyWi2$b@xnzQ@)cpSJ^lvHNf<36Ma$Bkp+c+>NHKa&ivItOzcZQnVc>u1hWKiKzK$I
z6HC^O>sAZv*q7)EyqqbvBY4xQE=WvQa&VtJ#$+OsrWw;^9&>59G?vJ*e!*h|8JbdZ
zD0oxS<f@8fks=3i`>Uc36@Nt&J~BTa#707@+lHJ~hhn`wT0TDHx7ox<tRigvbVT9t
zCWPOxWD7-}YT*MvO@|oxw;N-@a3+J;D6FYdo>vKN?(zlSB*tKB{9XbRQ;7aYXD-Ac
z=P3L`wO)&9d}O5|7%V1`zD6MoSwJ-bIY@=9VZ*#qYQA4xn)Pd?1;mldpz76@J}&3<
z`*clOj{q6&K~HqP8_*Dhp0$*%Uq~;f|8&=XsWK9;QUeqo{m0}&J8H4Xvu%Ml0m29u
zg|SCP?{X?txxnq0Dq61N;*nha-*(33tgXOkiGo)9yr+d_TW+U0?KBa~=57*}g0$m4
zPn3t+s2#wLCljN-g7J)MD&}8HvRfTStX&oYlQr`gZ%eL1cfDS)0ecj%)IwZLTrlwi
zD%5WNP_n&UygonCOrg_;;Mb+|oQGso7H$xabRLUb9bf#LX-4$XeQfj*k&ZjUhI!0L
zs20a+X|3VNIl6ZDp2>R9ys0hk=P)_N)3-TcARd7-qVZ(@fm0OE9__YZf!VKi4MFt<
z`HjQs#x(RdFGpK6`x1WkGpMbD3C?$MS4TBH0yVocMew+j;J4DZt>1bm&b4y&NP|ns
z#)j^gqVTjUL+1rY=@~<iVA3;iPeDh?ygwzDtHBNs_;(+$z_T%2_nDH%HWJ7tk)^>%
zUU4Rx|2w2mA#ohTAp>f<152Hd#OT<hE$$gu9pZLPD2srQV=Hz=0i<(1Nb|i4yPkJ2
zp5rdbU^H{YA9g!xEVF4l1@io&v>zN7bAjvXuJEn8i~Do{<2B~d_E6UIsErB4NA=0C
zqB5N@S;K)u^|cpcTe$r*`Bp#ZudA*ZAuJob+I(@4G5@mavV7=8rE}}`(9Z;02uwQi
z{D9J-lHg!OG(9R39C>tQMkgD7A_XsCw0Zx-3keRU-OL!I<}se#t8X7gl3V5R?2Uhk
zZcj2N<s>mT@Z^oSlK>Em_7v1vvYvvi_B~jq=ObvH$Q*|2gVJB4n@!*XcCUUax{>jh
zs=u+}Zw%dOUY8r>M!cJZi?4h0m`7%YgY@o7cOmP80+j%o@bd6gY|dn*DQ!Xm?}~H(
zgR<9SRR<!rv57DX?6DP80EzdxTHmlJZKOZ%y?@WIY-P$hA$o^rJ{c1nT_urTrjP1P
z0zi-yB`jusMIgqQ1<u`_Ta~5mgUd^FojL^@>n3e5C*@&klon)^ED9y4PVv}H(G?SE
zn)pNGi}2l$iMLVe<6B~ZIY*Vsl#<h$nz@JT0;<qLq0*yx!aBj(EV-9y?c4X`3Xw6X
zO3iB2Q3Lp`vou@S^c|O9vD<naSqU<xFbGa?i;q`rc#ZLfO99%MkxdI&Eh&-Lol!UK
zK_n=LqrLp|*QMXQTBkUmQj^D_s$=S3#3Fua!3vX{LL|x_LC3QCNd;@dNr(^o1T?ZB
z=siaVRXXhN2+0y%n`ukc^S~)HI5GN^QkMRStixdap4pjrOcV$E1O@c&ZZYYhPnDpL
zt`bZyj=V?ArBD2J-lMhYRd&r=S}tzK??y`u`~J4??u81m%@1Z$QfW=}B3LX>jXX#5
zKe)tpjQ96)s~JH}Tp|)1qA&)UM8o}AuGEY^V!MAixKko|Kxl_UXlr);o2hsU9ZP>Y
z%Zp6|16E1fGjFQdCYdy+>?xM4W>I?<qQ?t@^ry^c+$Va;7)h-zv6WMJr(w>zjIlVu
z#o8)y!E$L0F+(Gc0M;<ozjV8QT9fiy7I?b+`Bs^R&6;Ibrf(nAc}jo{&F<+bsGb|-
zUH<o5V)jX`*+qxn_?jytB9=_!U40k@XLLX-U3x~Ji{xcy2El?$TZLqTf^vNsrJ|Qp
zl8C;69=&G8(j>&Z7!0wGN_{wAK*q-W`Adj4B3lMDXi&*sebO6$!5-2I<JL;@$R0hz
zPry|nDOScASYodbT%syTd{DW4MjqcuXnYzsp_bO5^FDpL5#WBJ6oib^!2g*bS1NE%
ztL#VhuXKf_5VntJD%g24-bVq+97!GZXt>>B*o*s8Qk%O~z4)#LO-)qwXBEcIs>9E9
zPK&h)_c<LgnN2bxi=*^nk<QeF!&ez&H=5Acei@%{`GInIP{XeLO;MQpm==gF!)yqt
z_q?EX*lMX1o;z+5PD;x~b_ZZHv3C|aj=c%u(J07FchbY{4lROCsvP7wS%_=0>1B5(
zAsR!|2>V_8ij*R}=c#5E)qXO~9AA=2{K=2-rSIEvH$^Yj<{mFt8=W-Zxh=o*xEoz_
zq_!M2pia8u?yvtnT(0H2ts1!%2Kw#eI@NUjs`$T++CzJHI51IoYAo1vK0Gzx)tgKg
z2t)kLDE3Nnb!5~|*ls@6KD<rr793fwV*UmYOvVP@DWUjPX)urzkP$D4n_Q5|v6X+`
zycTi6neSddf>XN@1h<0oe~V*jLa^se^B$|w1bX;eAjd`SI+@8uqjfqnXYNQ>cfk7P
zBQ(#N=FZKm^Mt1)3-D$XMmBSE--T2va2d-z)(f{A4zvY^sOwsMLj;o2v(+7Ha-s{|
z;uYi((eu(U5Ms7=Y%HtLBv20Usu6ULB54NjqX+Trj@VkFh_#2!;f*Y^oph8BXKW20
zfiZTn8eMsYm#)y)e_rKDP;(qF0d${zhs#{^ne>6FcijXW@9fTMUOK&lspuR%gWvAu
z$fHs7?Q;klVP(oVy}!wQr6*zjtEycb`?J(X3P>@VoG}fPQ@jpgFQ{{WFtFx-cyxqz
zs&N;gRP1AafyU+(TZuqut1K(*Lu6azy2B{h&6W6CcgwyF38wgvk}hJz@c43sdW&O@
zoix^6Iz)!iVU;p;Cc9>k@sl9!VaJQ+hNx4^UdE~)kqJWFtyG3;a&Y+!O3$r3s^~A;
zBJ#X*^#F*jyUq=(HtYiM@~M}4J5bUR2C4qhCOA;P0^=J6C25A|#|id0U|NOmB`U+*
zYS(3SG2jgV^Od5+{(Hm&NmWbdv2XJN5#|GE<py}CK+p(m91vMMA^<o%k$+IF!V~bg
z{RN~#h@Zd`Cw!aEu<CPMfR&pUUJs{NJb@I&KnG4tl8N+13XqkP?!jhpIh8(X_3@ss
ze=s?M|4iU(G-KTtGX3r#9qEu!_k8JZ*d%`3iLCkqNG<rRwuY(jy(fBL$YE1ZnTFMx
z_0(EDSN9OME#S}6NU0jwapfZ;Dx)+wo$I~uyUK?@E_rr_UGjb~2OftJD6WJ6itg!h
z&R)qnP(|Lml_EyNOLbzK@v|sLx}ub6{m-EER6m*$JvfFX4xV+*Mxo|$bkvI3a9oeu
zi4NAtLELub>^U!`P-4wJ4@8O>Ya1N2y#v)mmMTn1k*|`o(jRl;FvOx9lP+y>K;%EX
zquEJRo(Jx*ncF>-@&cjR%cxj6Lf~3agkVOP;M&v<)PRU{5McQy2FVxb55-JAjcWh%
z5_YwsNud)c-HXKg8UI%z9_tYt=g?-&>tACQwA;H*G+wtUk}7H#<<-S4Z1wamDq0@a
zxZGA_$FhfoZH#ONvlSOHG2z%<+MG1xkCj}L;^QX(IICMHh=R<V<u;p#|6i);*!XpJ
ztLVE|f}OpLd!uNrBZ8&*Y`-<msE8`%x5QmhFyid5$7!&GIwH>Ts;%<bjVzOU75L1&
zn$~f;>~*~0@HyC1;yfR`S@nR^t*6QOKRm(RJPei;gDvmV%Gpis=JVZuOut`Oef|FY
zS$D~FeU?q4R>}B=QDcZz+S+FRLtT_Z(#$c7ml!d#^^Ab6<PH~f!xy?vSIG0ptA^^U
z3qCJ=^HyG&qSXx&Q$#@tS-|BULoZLQJ^M2so9q{Z517aCADpEQf!Z_zaQ9c}%3eVb
zIPLc%c8%=_ZIdycJ!%-Msn~4*KZF&{Wi1G88gF38B*FFcKJ-?QMW7ya0Vv(+Qd8N&
zSU$Sfsk-H!IPR48=w<!zX_gRK_?En-4+aROoUTa<w54Q$OJ1mC;EO)yML%G9(KgPE
z5@tG$>PP~Fm^~5=^<J43@t#s4!V>m)iQArR`4-+4XoytH?D3cGwg@|Qz+H2iW72{2
zn6nHPsgNla2^Anu_p!`Fy5tHKpHyqHH=Rn9_s6AH2Ss*><yPbTJY!u<KOpp1TDtPJ
z1%wwCB70wV@gHda#Mo{E3uX1Xvowg}%=F}y!=_NcsyL81_WUKGseEZ{ipYKA+g)d^
z*e{@AhG@&{b!|LefifmEBCyRhQ{``FYl?pfxzKh@3czoj$iB-d`j(#I+xE6>E2&6B
z4QK@O>d$aVx9*SXtW^9Rw)ap6J3^$dplXF#d>r^q?|;Stv;3SNjSvIxP!X?SXIL+B
zJ9F_%LM-`J!vPOGrgca_7LfoEcI<XS<{(`edBr}b4<=Tx-?|IWgE>$$jI-tTW#Z<=
zCq(xrP1oZ{cHRE5Qwn#5^HVLJA-$ezd{U?nZcU{A8pVyUvvH!=p%XsVb?&%T1NC0x
zc^X;nqM1%jkQd*nMPu?1M#Ca5t%7hT<d&8D`&8zj+6Ue<Ckhqa9qU^@y-6}FwH#_~
z3W-fOOh|u#0$;lu!Ri-hd)^Sir%VWhew*Js)6h?t$`pHT;GfMaOknxaH@XL-52|Pv
zc_d4E&x|oZ3F9*9hOTe;XCYp*%K>#7c;)y^oLA6<#w1<=<F>3ffN9az14Fc+;K;Ng
z&lc@t($w}Zbdw*B<L`x1!_kHwWK603bQ`O>FXv*SGK=T=4+O<*4VMM&VHGH5qla2@
z^T=HN+W8+7Yz%Z|m9t?`OzQf6@Jy`OP@X-Cg<wx(8Z&6J$Jw(#FWw8=0yJ@f_cJyw
zFtr<1<)P_~i2A+1JkYx8&gX^}h2!ou!`Xi&r+`kJg5Y)h3-|CgCSX5}-DD3EQ)DAx
zFxW<Jia(b%S3(hT7Z)=X9&YlL=%igifSI}9)c^oNFcyAhu0)OlHB%2b?KLb7)aBLv
z{oXeIJa<eBjF1v0LFXZ%6sF<bkW%UOz_cAyCpA}jwm9iNQ$sq+`G@XYr9-@Kuk<}n
zGp}LGGQYvPQ<elW^cp2Cslq?-BYaf~HAtREzil%GeccHd4dy|yeNEw83oYaORxU)5
zUAZVIu`>cTOZI8Kk5=U%;jL%2c+^J)I&i6MNHgai5X2b>zng0P2Ls-G<&pIMU!1^Q
z5SP}<mg<@bw|D&i-hG6mBq+$J$404vfv@_fX#CO1p4zd2bP$!l*#r&!V#p5Ot_o@$
zo?{TwB5m(NM}OQj|0wp|pO1>Q-?E<N(#yczpOPjVpfXkof9{?ZWQ(v#OTm95;v|BI
z1|}hL5{yQO4bk<Sg4vm7_=S;a48qpAGkU#10l=_C-q-z@(xyHB!udUk^oFznkoH>F
zPZ2h;*y+x##ESo~7jy>IAG#J-fhXMT_&RhZ74UD{B`RY8K(qxm3jO5%gj^0vmNE@~
z;YK)FWhW}XKF~+QCHp}$0$5IMSG)0!0wDW*8xxjQ7?%OUp;2FO&OGHyg(h)M=Rt2t
zSeWjCi*>Y=7)^Tbe(ze<;C*Yx%lo<v+Wp6zcPQ$9PEL`Y1AmOHq4fIlr5*EOie)`t
z?D%^A7n=6kg|qHXE<Gw#b!!r|4yIidfiDH&wq2~lo-p8+Jro~cb*0FarksA#+0%?j
z==rFped24ak{;J{8aU3S;((jnOUmX%>bpHx!<>q1BpVvawwkYIPPA9M+VYnckh*l_
z=W3TOzD2p`f{aa!*)(_uE9?g{J3q5v>yO{5R)fC%d1<`qWO}|xD$@E`H-QR`;(X|Z
zInx?K*M;UMhm-+B1;~u>zXyeb{f*`TZ3|WoDg6{Wajk~t{qG0@JYH6|&-~{;0F_Gt
zv%b#*d$xxk8&S+@#$_hapNioJ=9K5G&v-Vm&7NZ~{pb!XHSP69Ob5Y3Nf;sZ=jZOJ
z7J-;22ec%mVqHfr?-<#A;l5&Z+m4`7k$PAh;>JA*I{)ot3mVt%!IKWj3{6AIVkQFP
z_JhQZtFd6e9)sPACwlha7wVW;HuU~IE8urfZo?eg?9ZZb;o4<JsRt%n@IP9*ag#ec
zrtYIe+IN)oF2bc-2aQrUlOUq2ba}RFd;s`=0Sm66^?EvBc3se{)GS7p@Zf41%+d}D
zwvGTpBzC*sc&*WA3X`L6pjTdrC<$!ZtZmi6emgktN=r~oXM!irBW)=qibm*x)KsM6
z6THvZLGRhZC4luNVOO+!!5>m&Kin}_>Gs^_hxX7xc%b!9>$%nJFD)A~H%w;3?FGXH
zpZC}7c=1_7I_*H3+@Jew+~rT<o&-9u*pxapRTn`mk!2H1=#Cw91;i%PmUH9uUplh@
z{`N3sWTpf|%(&CA`f?o038Se>oy-i7@47C|lTYmJpjD9wwbm<~K?eSU{Hr8uh3ZB$
zOzt#bz}~g<j!M!DdqQ6SxQIT%z6TWgKUzgScZTCIwj@$ml?#_nK|-cK?H@K6wnjEQ
z&;;}``?_ZmQU=hw9`-FvTnBNM&&EH#2P^paWN8=fBcAoOs**F(oXGYlRUJ}iO6qz!
zVl`l94@d5fX`*~6UdDi|n*lDw{DknO!=gc-M7G?Dn8!kri0WIFOOriaUES%^VP@2Q
z%}_epA#QvW?XPRb?J)0d#J9~=tvC|R2)+Wn@}DUF$Q7Eb)yl^V-Up51LfuXq^$HM0
zP?iAnh0COi*c!pWDjOB!ojskKRL`Q_(yiLm-8`nQSYMXdAk@(4#CNH6zB)x)^s@Fg
zB*w5XS9c&OsS!?jk%wB?Z3ST;0}a#^+(EH%)$25feB7P8y)PFKZL%E#5fky(a8lS8
zTq(1}DBxIgowUDIy1WDcvIm+cb`y5Itqf(ZMnCsiK^G%W>TpaOLb!ku!9sC1bdU?g
z<}PCQ;;y~mkXDwr);)}~{;8iSr3n|xll~-sO`~TGm7+6(IzO9QNvw9oF=$(TJe6<`
zjQH<5pis=L)hZ>2wjb%dw1fq3iUMH>3iX%eLh7eHf6dEXX(m1@WK&+GG*h;~0*m$d
zE-@cpx{h>&86}aWp#lkA-w3ZBzadN^eAO$PLay3K2}n7l$bE?GJ6=bRtAF_yvt!*Z
zlyZYTv+`Mc=$({cxm&2Jn%kJ+aDFJIWSGl;%Wg6pW`BiCZ^*im9#aPh(=50i%9LLm
zZopONYIqYMMXhX5oQeb1T=CAxe!6OcqRp#|2vblCn<-{b+O@&xdse;1=P|YgFjAyD
z(%aG}PoccI=Dq1^M`PxWBs@-U543;W&|yzBLgtWqzbjLtyvppY>(J<NwMeeSk3|F}
zE`56mw<TKKoZ3pm<IZz+<9Q&I(898M8)Ru|b?9G{n5<A@`_C0$DHS7;!|eO7$vv!J
z2^bZhJNDLl?x3P#{&JMmAzxfks7>(6F80fc*s~P43GjILw@Hu^gXg+>380!?<~9lz
zL;!1c7b+QK6;P6*eV@X}0NC^tIj*MObG$0#H^D@`m2UpbM?pIsf)<njM@YgWDp1A?
ztR8`y8}iE^jkzTA`P0cGJ6A%2|L0FbELzfufpRWgw;ZbRKbc>(<I$<6vC9~M1(r77
zry~zw&U2nZEWsj|T8+C-9&icLzkn2_O{1C+5jL#u1jOEb$26w)<Y1*^J9%wnXOfAn
zK<IS0)lpx9%q<H5_@nJZ(Am8%Sb;6{9<cHfC^dO^k@FcXP*A0@eL@cQZD*Udwh(lV
zDN=c)poLMKhQYXQ>oIeD5aCrRSVLS#!tNq~Mm)|Gj8x!kjh30%l8^7qXqm2`<k8=(
zcw~m)ngUQ?V3bB0fgh;6<?>mYn7NDSa8c9_2A8B=Xj$K_X3*JCJb1EthL-lb$dMJp
zC-{f4NaIe^uE|>f8?EDVyBV4~^VL=x3jw;Pk`f`LEL~7?Q&+QR)RhF^DJ7%JdfRA^
z6sB1AU9rQzndc-g{Nz(0e@U+K*jJ4NxgXZjco>-Nt`|qbK!7t_2pS3*pAzCpH=OA^
z-B3h1m#?>%z@+vN5s03{<mO6yC#KJPaiU)^c@-46m1;1U`9E}N&C~XpLuR!MhQK@E
zE{Yj4Bdx)&1p^?L2VvY$%$h{^lwu5;Nu`~4l#}e;mB>-hS-P<<uJ)2w{@%sbTgubK
zt0KOp*i=wx`oSinbl$cfZ5lI(b!5qCIZ31jxyOhr>?TIG8N?J6NgLWPcd(mF-_Z9d
z2umI)#&fJ9C^!bX-70q9VlNzt#QFA{+@Xh@Fo5IeOu(kvZwovx_gug5@HL^_7^Hb}
zz*T1A07#dQPoZCl-jjm(NTG4BaFAy?YFJ+Fu?BIOfL(!V3~vzO38$Qq)zvGk<Fk#h
z@gnvUlwm<%mCgEoUHL%FyO25&&$z5jeNyCOI;n2;>dIiPI3a}QY7$T)p4Hb?BGxAJ
zoI>p~xOb)Lj-WC~UB-Sq3wn$Z*$DdeT-^IS;mtD62h%3}*yPF<RT5kKXwnHW|IKvf
zzD4+-`tcP?9F?!No46IwPV<?82!rDoAgMa!z&R&|X7GqyFk^KPltHs1=2Vu^<BZzj
zAO;&|(ESg*R!p}S>6JoG`jos1to+c&)Z*sA{J#JV##Vc3H8i{$=#=m+(F&^dEV$D*
zTeTC3`Y9!E0En*Op>@H5S&Z~SsxeApox72cE>UdxCgX$u;z8Ohd0>2#oHDXL;M=H8
zeLP1n_C$#9vImV)spiO}i)P)p-$EI)l2N-#c5muH;AH*!*J~vXNn-5ZuaQ+<atUwL
zY39H~wL~Ich<f)l5G(0FR)(hF_{xTq3H2>sx-dD{`!0fq@e1{VXG5g)wSjQ&1OCL{
zUfw17qj7dglOEAC4~z9J+fW0n@!mLYm%R1kD%v`Y-cKGTqFS(-ssd{kU&^0k83JuC
z3(HwQmpAF#>IogGeodellu;e7s=g~BDA32Q=O;p%^@BZ9!g|i-@DuUxK)d1haIl`d
z!;0G9Y`CPz382FmrEODeKB>`PL_R0<p)ZZdVh@YzCY^B$t{^H$Zx(MJiCg~!B~7Lp
z$A;5Ar62nd9GaznnukVTQ#ih<(<#QXAtY$^cSR-Et|sCa@J3K(D|v-@A)$gZD4UXH
zk5VGt+9E*5Dt!mf7p`}KUuYNo^M&8_>6Xg@87sk~Zl7_8lu9_%xGM;?nEg1lv1&~T
zd`ulb-9pwxXE3geYuH6b)@Q%4>y7i)9){<<r_|UbLTb4xz?ftp!UQP=-A$iew#R@p
zg;R8(<DtG`gtf`LmO(fnpd@*E-O=M1>Kly)`$5+#<V|Wqd|saLKa}PN)ifCp6h(O7
zY-8OefKAd?kn*TqpAT9HC*<$U9c@4T&E}X}6cXEr<@_K&J?UATDl>uyKMsea(Dy&x
z*$3oQ5d!cnP*x!jz#?m>m`e|GFIfNb^(!JJ^QO@|bBoQ~kj%X*8BPOCO%$ue!ipq=
z!KkxqC6Si%nBM~~L4#U(H$vzRCb$g-pSNp9uu?}L!*r@nz4cd^Qgfv@zUwz_^Ew4{
z=aSWHnbMoUA2e|3cgqTnb%sCLWys(y(w2<CDwr&#bSMRhXDfNyvSz^G4Pp&G^KaEv
zj`09kmFU9jJE@^A6x3n&=LWiI(L(?c7=nHF-R!0fIU^(p)*pstoBiraGcfCn5o*#2
z&>A&FZ$H<w@JSM6R7B_LOQhmVn1Wrnl~G}ST?~>2T<6mZ<7$=|aj87&ibpq+e`YAJ
zQ{)zhT?kME-|OEE;b3@jtU~5#yzL5qk;!^ySxtbs88;!##RqSs(di_LIXmz^vd1`!
zL6HbY@(ZCKuvd@b#rl|{?9Qf=p+dMNh<|ACPW#bB7%?uTfrqG+zcPt+_SZdSaaE4_
zU^iOja;;3TYE&h)vFl_^c{CED{0-qrD5chu3g!}ag`BZBssaxUMLx~bVa;W=+#^S=
z+Xz^5v_M2qwRUy%D?vyImRth_)zW;e1Mo@QpA6WY*tWNUHzz;{N7am^M95S*Egjpf
zz|C?JlY;Udm#>dr85i<GOpY+W&2;Op2R$O5Cpc@%zhmO8M9Ydsh&)_Pez=?}Rd{QD
zD;6W(9QH@W(MwzDUOHz3JILY+!?)oEY7=*?^h2g1V4G>7!99KV!HDw({Ar?r>y~Zb
zj|_WQl^yZ(qzv#iJakzF_*xjwYN)yV6~X3Nkq#*3A&;45$6i>HzyG6Id3Rf>=OyPx
zF~*#Vy`+kO7G#0CUGs{nIc&3<JsTfX^h4j9iI#?{(l}V-rNSI53}=f(>IGnG6u<zZ
z&EiS+Wnwq`;mIHktp00G5gT^K$A?YD^0Zb=X63Z-*t_NADBhlkG0uI9dtVB%AQ5_6
zaz7xXWNE5axsJhhj^h1nFtejQ^GQL>bBXTd8(O!NP{YLepW8r0R0CPeU(K);Sa~6E
z#J(mAC6YauoKvMZbL(P<x#gY3rG0l+Rg0E=9QSO|$q(b)Ns`+Kki2xHmc21#d#vJw
zWbnH~zSiNbj5e4$LjeCW#pHjsCwa=afo9GSVE{#-0RK$&ecc&yKx94okDv7SYMKLO
zdjnGA;6dk;T>;<L+36y5&i<mr<*~(Sv3!8M*VjW3wJZWvid%O3X;*VO10HKGvjq4B
zNtYBWdsXfPrQK5vd+}i)AxI<e1UpsH#>Vy@*I@oEZ>=XIc>NwFVU^_9({>o*0sm|9
z=IM4_dmT4aG%~AvyuC!4=*rGg{ej)da_2fpf89&YwV6XE)^wt>3<8lIz5eJ7+zVUi
z{Nfsc=}pQ%KNO4d<n&hP`@^_;i}hLfrz-*BNrVmD1kfpeh)blb+p)`t@=h<WX=s74
z^P<Qye%?NwQ2M4%a-cmtJSKZBUpHF}LnJ)1W54^O|8%%jEtEiLPi4<RG&7515xK7a
z?3zD*qdprGyE??_zUIz<96^F*TwbkDVNF-y{>JPcZis4sp-s%j5j4u1)I<+zHT?$O
z*CO`?u5|1Y%xB@kL4jnoF_L_6YUIyj$Ymt#!7xIJbBL4&NHi}wKBhbb@)2P*d}6c+
zI@Jo21QMecn8Pl$x4>OW7jpVg!PL<{2jaUx0S7bnzY%s4l}7ueGCl3!w;I%1H&mH?
z@iiiF;JV-5$ZECCFbdDm$mI*@mnW9|p0w?hs|LaA`?yVdMN-O7ratSGdyMW?L!GX4
zr#aadJpIjQZXP{6iX!tw7au8EgcC%-PyaItit8Qr;&ZJpdlxEqQXpq~WAhdlm&!~2
z(TjmJ=JVXwpti{h_9GwEynFr+uOQoKhN>Nsl@otJn=P>*PKC1t9Tb$=Kl5fGbysQ{
z@M$xvF)m$wDmbS<>Y!YUxP<3p;BTGxs54@|C3I?+qCdwBmxY6B0C}aSJiHVN9MXoQ
z%rFzA(bsF)4wR`?1WIAea6V=4y6NMMOu$}b-V5DQ7g~)v<j4N;M{`LW1iVw;)AKEU
ztb;!4loqE66!lnLk)J8XFeMYd<Slfoy?bwiy+2S*_uz`8Rug}OMqrr*-#vjg!5-8j
z0jMXefEXe^>EGYnZ?c?F{fdGidc&vlmLFT#-lV@CQE2YOdSrv`d$chm5Iw*9e#2US
z*f#$rBflrwoSH=iL$~>M3|6k#s~I^ak~lFstWHj}?@u@v1nTP2FACK)Ai6g(-PM(M
zdn2<)+`FL>D(9RF3o2hz?FJ5^itFcJHfoE}qM!hg6S@`2O?hpn(s~U^HKQRhvcH9o
z5X@stij`m_i<|5MrbuF>N2<4)_Ds?F^ObZ2!m369WL9I9DP<{6uuKdyvwLf)I5rvJ
z^7Xr|c+&sTS);cH?tQw+%P9>%EV4!M1!WQ9`wc447!hxtCfkIFxMG}N*dzt_iOQaw
ziB6l0I~ghXJvwi&H)S+b*VWBph#_UG&yi5VW~F!CF|8lj0ozZ$zkdddWzOmXu-&JS
zFwOfPdG$Sipa!m^e`8rXVG$*l5-*-}x0H=8N!9zq7;aSMJ^pi{2zN0(+>lEoX^=}Y
z5&f8{P}Fz9QEtslKj~`k1+Au`P*YWs)geHEvcT48F8c0bG%$Y<BVl09GvpB2(C;61
zE9n?6`ggUvVArbLUmEuoUgT2Q*tDO0a*E~bu8nRGK6o>g*hdCqZNqnu2g!us^<}R%
zW9vx42r*u&D@9Hntg18@&yHB2#SHS_OwmCIX_3EWXLy}uyDaM-`W*!x;7mj=k@VN9
z5R!1a-AdgRwwuS-q<;jPw}iLDD0<D8-ZS60$@5UA4|2i4+|0~Q2gDE`C=}ofG<>O_
z+o{4~)F+SZz`Ta`V8uV?75k9)38e=3hGv~m1=WG_O#@Uz?YAZLL(;Zov!V!Yz34SY
zcN}o%cW94Z)MXXR>H5Wfd8qXsopY<p&ePYfpA_DF_V<u0AOz7^<aVH<a0Nd#zKc}G
zqAT1k-SW!~UExr`7W}u++-a&;5^pr2*(eP>63xye>Px%T8=DZ)NjRlvN%UPWHoQxJ
z&Lydnwy#fu;NilOk08?HtZNnyXEj`E0N_;AsaUa~GG%9e=)cVn5}+&!+y`i4N2hJY
zC1+Vvj4;?B=JMfBrh?L#jv{OHV(_7<T=jVSH_`RMj?@oC<?Zhh2)m~~4w6lGp<n2*
z<uPBY>a^lbR7o+u1v}_^m0(r(lJ{Q$Hm06@8S)hQ%}!N4>P&cS02bsB7B<eE_P5EN
zG&1SAf5Uglo3pf>C9vf&b(RKs+h?dvUE7o~+gdPP1`N4B?}m%AI(I^2{$_l3X@jq!
zNpf<))AVTt#KNKJ5KBE!uZc3->nupmYIMn_&z5yqd&IC7AtOQRH?3TfQ0;=IoG5mY
zg=a#tjs3p6#G-c+y#@9g>1Z{M6KOsK+o53YkD~8hcYca?OkNhY<d|Q#;puf!FcVBr
zSESOt#_QZO<A|<13vD7V7Q?vOU_kJ4=@QmX(s4ytj#-@{VUZ&Sfq3eF*onp1f4*f@
zSZj|)!FD&6djN2nYD<MH_qd4-6hE14tY&^{@gxA>i%rkXK7v&2j}7yLR|yA)mq{Yf
zzU)FzKv@P6a0YXY51_^sD@^=n>aeUPm25NlQ_yTFUTkPUjx0z`uyLGg+F|IW)PI#W
zuFDV?>bsD?C00lTX{LgQ+rNb+)X6Mkk)0Udf2)KHQ4jAraGGO{qJ`u72W?*b9!|eC
zjNXrhM^nSgTAVy9xxAl7Vp&r)gY%w0z}Fg+%|pxmV5FkRbZNG((P6S$*F+8jeF+4g
zzJU&BLw1rMZw_cMV<xVg_k0s(b)PDy#y$_$O=D5JtCZJSJc?QDQga_Yf64xNgy2_u
zRm0DFqk8nCXq2Sg*|^tsjr;kNvwRQ{^E;vzm<(OXqKgdM=<~P1k=9RG%ZoG$O7qPD
z`voy7MMoHn+5WGtI7<exad0M0Q(dZl_HkNR)?XP--T73JR;yu`m8690CC*fuc&a;q
z0O*wlX-W*y;oDZ}(}IhH>CtyN8-Od&@g<3obKyFV3na&Nx;5?#(yW9PbUlxC!acrM
z*6@N;SuPRt8v(`SNXh5tC8pW&bbZBrJ3f0Lmz(Pn_!SyA#*^AiI`>cmz3R3+bODKr
z)_j=`3bXynSS`aLkK+eAM)`kY^Y=pEKVSftZz2N{ev<sL#x5y>=~0|H{La8H^tG0x
zHhxq6(2?3X3g}+?H)1%yHYibX+Gpl53PtHwKM$@Or?<yiIa}Cf6b+su-&CF{4D_&Z
zT>p2DwAst1o#0#IYM>FFu|Y|{?DrEnfr8dmHksiMx<F+P>RUsKt87YcKaSwXDi80H
z^=eML+9L3Ld@Q?>w3~}bo9AKFE|NKPG6=t=bpnCb&PoKtlmK37>JMnpl)y^J6ybZA
zmvX}vR<z)Ti)J6B&tIQJzm{Ro^s#NBNkwyRAF8`e4I5coh&F_X7dh4U3553Q8p2`c
zS1yy1hOPGD_Tj(LFFa%?;W_2fxb&)Q9IZ7dvTx*CCzVo}&uSdCS(Qr~QBaO=3Z~Q?
zsvONS-MmR%lNbz3Dl_<-8WU^th4<6>PO{-Y4_Uim506UT+R6n{y96Pg4~%S?JgNg;
z#bV<1J2n3wz6<u(5g6rx75P*?I~g*Z8!1@B`3g>3?(RL@maYKmqXYB5pu4bGAaXf;
zLDPF)sI2KYLZ5#VQP4zer|%jk(!Od}HiAfOviM2j?RflvGl<l9BM666XcPN2AIV$f
zG)`w?H4f-om?ReThydwH`_fR?_x4kcv2_Uyi8l#Bb}WiX3llfNfzhAxpO67M0afeT
z;HOeenBI;xxJB;bDqY3D1G2reD4p$q1C}IUZ|rnV_jn}_?03M)eP6of9Uw&;qVehC
zF23o7_bMDr+ZA(Rqh<0zZ&udVX6&T?a#^|1nMG?05OV00p`E^#s$ORrZfL#zcMPff
zfG8_V#P^ErGQw(~x#EI}eUh|&(Hn@6^tF!_>7zdI9_=s->YsIjD^q_>rf13?^Kaz?
zg_>z68~<a99Y`LU>tjs-NkF#0`Cb*cF%tafewiQ!;3s`0Z!H}my};j?|G~0V7;VR@
z4W?qOCggSyCe48tPcyUX+Vm|UkHMli`jRzB@KEQX&8+vTLraKBtgL1aMjOt#LC)+3
z#3C!{sBB)Nl|>ikU3gkYy;BrXmDChou(_B)VCPr3wM6I@So^NonK^VIFh_4xeVPPC
zWyZ1n1zWOPtJ0YvM5MDqqcmPsNJ55PDdl^5ZIPJCoCVBzSDdubUw!HCi=UU{+|6@%
zATAg+&B_HDywSD926S)UsyD8MdezHPY{spY4|b9AC=&kmBvU$_-h{+99Stx?op<2R
zB@{Mqvz)%0mZt0WoBTY4?6QyEJ4RPurF*x-3aj&mS?X6*AzNc+LQ>zq=swtB(FcEN
zw^dFp7KmeBd!*lBf7LwAnHh2avh^p&HJ!7QmETwH0vo;ZjO&Yqtt`e<_lh&sRc@JQ
zCPBT(*Uy4nw8OaA3pmR6%cy?Od8-^a$}D9l#i-seh}p2L>)U?!K_^9mQDu|QLx;nE
z!#ck(9V7ur63%hohYoD2Uau(g?@&7N7ie&$8e^p_%7Zlw1C%}i?AI#v-A_zW^0S>d
zk^fr5TGLv*m?GIo?&lj1=cN~+{^71KT=`w#&o()&i5&Jd_*Iq$xNEmb9y{?7pOfX&
zo_6%7{J@mZpY@iG#wB&mX5rNFp0BMD-QvJvz3-b12ltWWsqBKv-O=m3K5MtUcrYww
z{we73ev}dsJaQ$>FAu{a(E_%L{j%%1F1Vzg46^$1U}Ic|CpY#iC1-fDuyr(2&sJCR
z#L5E_wpZfCi^ATMB1~G033dDr70J?W_KWixX=g?gdR5@JXKmr*9a8v3?jr|5lI{>g
z-|@}!jn5tV2|e!wC$uBK?jk^hbNjDg$?FEU5fyaD`xQI;poOgfSbt0F!gW|%H?7Ds
zsC~N!Y)aZoXMt?7dio01`J~0hN3WB!_q?B>5#0;fge|4<EwY%uwsO3{T@hE2K`$Zq
zOwnBJ;Y^gAgz}_DTf@06@|JV?u0uX1ihgReI*N#x3emI?Cui-95XxVH7x7v7Uht^B
zcmXyb{z>1fF^JE5!8Ag?k11pmmu#bazX4!YLyE=fQW+BeSV;nRw#JC}3^|a)8R{Tt
zdgJV``6Z5W(AND0_rdzr9Wj<kB{Zw)-_GLBY(Wvrth6b-9aFYCp%ykL)ypcj+2J7C
z(32iB34flxpV#cYZF$&?V3wr)R%TLpl?G@aXBn{#PwH9IM$xmmAUPvwjYD%SesY-O
z3GNBtH=7E+7zXVAFl0B@Rfp*hSv8ifa=BjQQ~$|xIld<57TsI)exb_ZbR3h1G!Z!*
z^_o*qgh#MO20^JQgc~7FtVMpwSu$O=G7Pclicx;Ow1Rc_DLJU-@G{}w7})Y)_-<1S
zewwD<KNQLXqvlSK#t4}ekH|gfQ70v^%sPsHxSw2I0s$Lj1wF8-UVY;J9KOWHTW;V>
z|KSKK-<T5L`UCaDZTVMTi?&K(YJTV){cI`plvxC={WVAPTJ<1x{K`wS4R;c!X^6eU
z#YR#)ud!(4)Jwr7f6=5pR^-~sJDO$6jkGm&pq!r05P)4m!!@O5uU@$<rsOKw8!EC6
zw(|Q={_ymRVgD9hG}~TE5VTKzKVxN@nL1D$vCOieG&&iCs_Nkupv-4a$)&1&!>RAM
zhtV5s8I&vY4usVgi536-Liv|KZC-uuA3b0EIYq}grhnX0BHwQ1Q{ZvN6OH==UJMd(
zO>dAWy?F5YIPPlH<*EibfK_53*nA~ps^KxAi4Sgn$!^2pVz84oo;5naY0Kg~)9@&D
zMe%$XoX)(dRu2SyQI79@YTp9j;8cw$Mn@SQ!6uN~(hwr=MCVsUi89&Ft!=Rsu6{mA
znuFK=F2dt6C#%X3W0*uOPyW$!oG6WQ<LQRGnDtHIT^bHyH9lT_Q!=2ITkk7SL^8nd
zZjN$fv4H)=d6%}*E@|<zJi~KI^`_u52c8*+S`t$X?|~LI-bBN|&DZ2)NqY!r<R_|N
zHo`+TtTaJJDRsnkxeS1iCeo->TBmOwx^5z3KVmR<0VrV}8Njsnav;(WOVB8yKPiX;
z>$Vzgd@xi{Clv~kH|}~85Bv~RP4wlN@jq(tP~4K39nvi%g%G-|c?ux>tmjO=<w*54
zQtsdt31mM2+leRnk>Y>icE2MP-h<mNHTTv6_O{P$m1C|dvwEQ7Uwfg^kmu~W9dYYi
zo0)O4r@-7*r7it^9hy$L^{{N7%RlxU9|==?$YS^P^C2Z1wOhiVm2^_=>gGBQFK5Vj
zaFIdSkn=vH-1>|Y)~L4#gLL|(@h1l)hHYoSIqA$KUXT_*B7w7P*QqZ68q~z*syJ|L
zN=)f5+FV{610S-9<H3>ha?=z4ejWXMXS;&}HTq#cCT=cWE*@=t^pA|aDAb1%CCwyK
zMb}fYTUmoE{uL%`039*3lc39x`!&jNz|#KgDrB6??g)`3dv{IWu=yZ{z7_DWb9L1X
zV4NgLXD5*RgMssx6X`LjR+^ADvSHqnOftQ7z`qmHX|nL^Cy1TN)sg!N3Z)0SVlV)K
z2_t!5jMAmWWG5$@`pV(QXrCk!M)RXWPGA>P(j*}q@%pMBPS?;BaTGE3zIB#_?J;%>
zRoBwd#XnrtWhR5I@;fhq5e0c5>Z_7V)|kIp<;==N(^}m}<f<ypv2WbCM1n_**mkte
zy{q*b#&ImhjvrY0dw2lUD$$W_QDmwxgW!rMI1@=(dd;7pj{|eUmV*Iee4wW3aWo(o
z#2#G&*;mBGmnx}fP6|1<B02oIr)ZsO63b?uI=4@848wN>)~r}Cns8Q0w<*hc^U5aW
z#QqJ9LKEKmp_1Mg;QO(w^#=h9W9;R)$8bR_HX+x*$64=X;=he<1}UVP1N^cogdWuS
zC4}fQ9~fl(n^5ukdx{$dT8hmZCmH;ebHEFvno330lG;~L*b5OF3OhBqWgMx>;CI0A
z3I1;96B(>Ty%iA<=u?a|u;04&TNw^J4o>4C;hrR2Nwo6~@7@6)dk36|Ep1G9RhaBI
z#<-N&3(Wj)1W?lGUm&ysHpL(tEjjyHhdc6yq40yT#1x(1iW|U^$})-XvM;%S5592F
zc}YYdCrE@MM5t{l_hh{AL@*1mh&9{M_IpWUfqx+~Y$uIvnn=FjgMTJr`~GMs+gw9l
zl-|<>M%$M5bASBO;ROM~-Q@ST4oQAL5%{2zAepD@i;YGu!-g59!-qC2%SSKyv}^w(
z$_|b;31Z)RGRqX=4zDK?8;u8a*WyyA1I*$e)NyN}RbIbOm{U9-u=cQ7%4BmgT<vT3
zaiL38kCrQi@v+v<%ItxN4{fJOt2`dy5wZ{Q2uLJ28UFfHm^Lm;IEnP$GSmwR3>lw`
z37gb2asV4(qWfP`bTwCZ5?>4(ZwVeTPi>2`QW%!8_;TPAq!QJHxWIEsG4hQosLJ^e
z?URjup?x2WPBFgVJ<iB=#APF??C^OH1(+9b3$<&N7h`S)OYt%0_oF9L8oG4$7<K^%
zS}N<$k>AOVvGxpwyf2Jb1I9-mq*<4T|0dH&P>G(eZ}UDbhOXg^U^fWpZI^yWSJrrf
z(|J=$@=afbm}hW~D<(@8|HD(EPH0z5Y6>?}1n(x$QTdqx^{rrMVKsLP9WqCpn#ae<
zXrh%7Un3D}3eY`+Wrj%~sPRLr7M!Tm4E8T{8gfkUI+3m#H>8n%=|pR%L)`8nOx;!3
z4|u+u4Gt!RpA7W>ADu4uM$UKrTWr#4;p+!Cu6p-5S!Ns&K1VKMh)*7+;%_%7))uIr
zU{NLmc`oMnct7Qib63}S@L0v}+pGD!!0=eV*}pjQ-eWU&7N!bqMm+GD9t@%$t|JBf
z;~&5nxz+eb603!hA8za79m2~=1hBW|`&e!0JfqaTM`y|?=doQ;lCq||@wwT!Aek6t
z;~A!y^w;h$%1dLzoAITMnkkMp2eOyd&jt&ZsFp_HsheQj!s~i(fHulG*;D3`%ta}k
zu^=l7gJ5uLoCv$}``=KCfM}?4TU;wCU3-2)_*}7sQ(MD<f^Ii7{3B$K*~lCHt5e|*
zski+k50R|Po$%0sLR$Hdobr&$C%0-%_L@R|U<a8v*`w)QeMj>i{pAO-{UO}x=eL#G
zj@l~bmfO^xjn2=FWDHJ7P$a#nnL_cp2}zt(#_rSr6|v6vZPCb5DGLd-5?UkOrdvEQ
z@%t$(i|Z*!puwYYBVlG|eKrMzGZ{?#(}s<jU@871d-3+c)~yj%6tlj)GlGSti>L&S
zgrZr#A%gXQYqiT`cXQqUS)Qx5|Cruij3n-#vbicU<~f@qCOX-mRr)e1dy;Xqw&lP#
z=eCX%8Vd9sU(kV{0`#>3=zUpYeT03*_GVry4!1;*Uo*&#2P2ToNk?uJi*Gus8p@96
zw;r`~G9ss{bO$uh)Gjxx&|1P7a)Fk~T9HJ_hdx@{EFCgh>I!)LOZ*h1uESh_p4k4x
zixn%YPa?UD6F2xuYxkn1AOT<m#6Q%`jx@4!Z;VneBv`e7uZtkbFYG3lP`-EGAHgpx
zzwcn|qM=JLAB5i=`gP1O$r?@L$(s(mvo;k4=SMsohY}Fo`&&_KR__Wk{PTU>ek1v=
z;7d&g?<_99u#eA4Y(Uxo$abv?_?35nOyrk|wWn^-1*#SP{dY(#%ctO3i=Tz%W1J)L
zvmW#B<nFk_K8+7*Zc$Xs#I(4mAa87OVIHyt^PAHLdr#3saqW!it!r^i>xtqJ)*BLn
zg~<XY4qZ`L*fPc@Eu;}j9e#%5aU%*yE5RZj1pX=#NelouSrY+WQCP4nmzB7vl8OWg
z?CzAhW!QQiRSUC8_?}_sb@7*kQ$bzEglPy5e7>bP9<Gun>K7&hfF<Zphg9I~l|8)9
z;TBQU)=zCq;S@GXh9)leHz%?8Lf^_#EA{thzHtgx!a3aq0J%6uFklY*$634Q$yxqF
zfrky?F@x%8WQNeL&A8-5RfA@#I~=8(t=4w0JQbRLJR|Q<K(U*R&;+QjXo-z8Ahr@q
z<P+Hs39bU<Gz>A=Q!WkNV$nat=uT>~ENkfnq-a;X@@drzlWIj77nvLJHq)a=fGdkN
zOjk22ZKtfrqlTOu!(#)EMF7^ZB#jdrxvvM8-8u8d2plu#fH12{#EK${rJM!wVO|^T
zhP0VCf7QRDE=imVXCZr<_{7aefSdq}34R^5=A3NcsSJ4M4`mEzp2Be5M3@{%ZCXw4
zTt$$C&^3$z>?xZ(V!t{fB%UvP=ouCL6mr`+4#8yAWFU({`Q1c(j;TNXWsfly?cPx%
zrwP~W1I<fSQ<`VIEgREA+iChCTyd_L6J%MLgddWPlB+W@X!{P>^Rj~nE#_oI1}X*Z
z+3<?Of=zj|TgOugyB-qm{xB`@TG&N%4rE|cvm4JhMdnq@JIjYvm}XXHho5ZISY};e
zedy4Cln^LRTYK~26PmdP(7`czi{g{_!uF-=U7EF6*oZAzz-2N^6(8+irb>JshkWk}
zA+RSyg4={z9Sj`%k8cfftZ>0B@9}=H<p&F-kX5pgO3Lo{ARY38m^ekJ6mrpWUM#v@
z9y8RbcbG-|p;mdv$n`E3-PyvOv9sEWwjHO(80lo}Qvm?Hg0a2}^PoJ2%jSk^^I)%8
z@z`1C-O?j_Hc3gdtbsI#3)5xaru%Aa1GvMa9s1H>i(aG;Z+FK^Z)Kaj|1>tP3m^~p
zm`^Wzz=CP>)fHxzVP9-x1SN}{eH6vK;-zz6J-QQ_<>y1qbcXLUL)gZS>o(rTQMFmQ
zj*M77ngM{cpNPE-cW#Ka5$97b^7%8WEsqyM^?;MZyRLi9cI{dz^7mI&)F&C*gQ9H-
zu#Zb?Bz0uCRAPF7HZT&luv4tx5Anxfh{vLRa3b8l`IBX!_YT6OI5VK<#(DX>N|_u%
z#thjlEu^e!Q`l5>U{xWmZ~8U)S59ryVO(9%S&<^V0KC6`)h%%4#x~I5-F4S##>2?e
zL3hs*i(khMJHx52dGs8;_;}3Fed%p>75#O5H0<6nrtSR;&Y@zzBE7k#z_!iEtW0GU
zMKHAR^^J>Ix;&y#aCj>udFC<f>%i93;Q!3TX4uBo1FA3<t`Lg<e#%-&^~!w3tk_}q
zGfE6r6!N!DV*LL|Jij3)o<tVH$Mi-;vlH*m(I^MI<$K*=<W}?!b@?*x{5*g_y)$l^
z&n~Dnpu`nlo9r9rGTX&WpI>>tX~iF^l6ru}r1DH+*x_EMS0H{*+245UYvyO$MH#1w
zT7;Qh{;fQnOL2u^X7>QE6^kS96F<(QLw7$_H6Au9QOw-F_xxIgJ<iT7(|7T@+eWdT
zypc;4Fk!qGX8KlZrqG-2Z&;`b-dQjFc#EJ#)D`F38)+xCr4*HG))Em)tr(yL5L!=8
z0eei?%kea|67Ww&ArOz&s6rVAjlbq~e3hW*WDgg@v0E=&;imt6{_(Nx5+Px|P^=G#
z^q5FrQ8@^{Kcw`YuUrq+(C*SZ{q<7C8^`UZ%~PdY>fmI#UGeE*yn@v?v-5|3%EQNc
z9%{gc3;$P33`cE1GgzGBgsWk12jkyNF-$}_aME(%xJ)*hX5J<|SQNU7J;Q?PC-c;W
ztprf5K-N|2y9nRZ1WEC=Bt%<s-*9bVPK$7I@@fr)kxJkleRJ!Sk)&{JdMu<)=5DNE
zP@VO3pbFqK2}PdRX+9RUiKY=zqw`;S-66ZYX&`wkbg#x3DVS45Bp9ROPWWaVivqsc
z-=shaim*n#ugFg|@zD4?Ifn6mDk%>4MOr4PC`%&;WSYD{Rz@Vo<rkU!DE@TlMdbmB
zA@13?zT3#+;qD(3V^dLVkkN`$fhvud{1d&{DvUR#T*}>_A!{O!Hn<|QgPina_DD^z
zeEoB~56gD&dw1`R2C$7Yh<r2C9n1QiEaWeyAcc=AW*bNtE6;=ps2G*jMEct!v@ykc
zjt(}cgkOgI@IAeV@~m<rSSV><`DCoiAEl^;kbQVSCTQU}Pq%?Pyxy<LJ7IaC#q-4<
zQ5H}FhH`cXxSj8I#nr=lwSE!iY%HCjak+3LGHc&JLe^&1GNRO@)VmsEJP;4?aa!K<
zGJ|kSW%ombC5`500CWtXizM}z1JRXV+e&j!dD4Hh+g(SYS7RG{pf6Mu<5b?p0$5Ga
z1F{<%KG9LdIS6rIF}G@~4p-jL3<>oASiZ|xDPa<cgxtv*v{W2!zLNEwkP*~nT(TO#
zp!py*RmLX4NbT0c<TEJ947V<W2_^X~bv;f`e_e_Q&2kj8vHK<CDdnN%y`QxBgsT0_
z@P&{I>m7t}5gj!Nx);bI)~s9pgpavjX$<{S2xj5~i<H<iLc}@KEc3U#a7qK*sD#-N
z!K>Tfz%?Uxd5oAr+KVq5V*Po51658RPISN2wRCtN$5ouI3#48mzETpgT&0@BEq)#E
zOSeKkoSGV#uFvmBO_wX0vYtTG$w0AQ7If?twx3scuPW7jLYGfG8l>ZG^|#y$HuePe
zXas`#hS2cB29+1KnC&s@aehR+t)Dr8&ga8VnPkoKN0{r-;Uj~j?G4)=2E7Nl{`DT_
z+sg)Y<Bf)k>m7o_UI0BfdAi`OP$KsjF^+&X-j#u{!EwOWmAU!*rM6Q8b>}`KC)_=A
z7|px{HIeW+T!bMP+<WmVGE$YF6mQr;$KMv@=wpBFfak0mvx{LAwU>M*VIDYgu-ji<
zv4I-+Wb}y-;&AvUgUxh#3^VKI)7PF)0xstG6Q`WqFb6>s^AKEq;X@Ve_400Bv5roC
zow`y8<w^Z1;-p8&&plve{UC5wm9OT8G1G}I$i4|a^Ad<IFNDc1d;+YC%fbSdZ<RzR
zYaeDQRp#ze_Ocv^2Ydz@*=+A4gteU2l@!NV2OqP+Pf(K@tR7^JunplI^?(o-Ec79!
zZ*r&75lSc&RY6-hwXWteVq6N)BJfUlwv&?mEUCYmVE4ICH)WOMskXcu`2f^h#IzvF
z3n~ebek{H7c#-ZAb;V;wa~@CJTzti{6FhqZ{pOl*PBG+^Dwd+1wnOd!K~9)vFG_T&
zoUITuxK~%xxIu#;i}-FP9(%wpl%wMwzU0h4I*7;t;ZSjec0Lbf%hLZwW>G4P5}q>j
z()G?&r9(uDeH1%spEyGuZMOVuA|xyFRil2G_^ABVT^93f3fvjRShf4;iVHPtK}w9#
z>vj6;*9op(sg?%00b<%l3+myU)4ltWlnZLn!dY<Wx#xezx_U7g8gv-I;wb5_@#@_3
z;Torpe?4jO%?i^=k(JkIOe<{sGBnh@kj}u^!Z2?X6fmz9O(A+q7xFvmBu;ba1{4nO
z$tX!nA3N7|3&A>=)7CNSna&=NU;EGf?l8*@G+h@s7e2Zjj&K*WF$2WyVWKG#yjolm
z_%V)bw}>o?gX6UWDV@dK;(YK8ZOar61C_1KXPoBGj(cr+_(2|odfk^j2jxBs6&<`x
z?!g^jL6S>YY=VfwHNvHt;Hp7T(XR{xL;wgm&ct|!hZ7<D^6h0Oi*!GE(hR0Bhoa?g
zh5NZWgS3%*q3bL3nYeO_+EQ!|Vl<G(0Hp6ls$;t#ugKn+F3hb@*uMerrK&Az83V6q
z?Jmvi{TaQ45<F2u&Th0t%<5*&gHUpEgOaUcN1z>9?3dH*0ehRQSg}>Bi{?Dukbf<&
zEFtP-c1O7$Xw+45KfwIV%sEQd2LrIODJPsQ{BkR(Wr_=@i4nSE{|CXf><md^-2tO?
z0$fP2MD4VX<OG43middCd|@XkXJG21^bOy6D`VloB@sm5HiRee-yt#_MTLXo=RDhC
zCQXesD#d3@opL#yiLN813#LZk-Hy3`574TLhTN`D)Nd=?X6mY5fIruLNVD)o@b~#B
zY6ZrrJVMDu7rg)o)3Erf1Nv8d<zY+yD_4QZ)@c02|GM=<R;_(*R>(nXLvF9$8`pv4
zgCO#qC0jkS5=Q`(-2!@Z2orAt6AFLdBMgguru8IqW{CBj=*`eZ(~rH;#{x<<T2%!=
zcyX|=<b(E#a}tCU@eJf=PdOMTO0bP_Axw2`1dvsx^Zb!UY7;RHS||()rJ=UB4Y2}@
zu)A^kwcZOS-Z<ByAtTfsNHy~vMVZ*Soff2fXTeR|E1|3?c$e8yHk^19vkdxx2<eC>
zeYB)YO7MhN9L$4%814y4_4G%3a}bi;As%%|Q(T8mIpdouk_rairx>w-5Cm5K(IWXQ
zTP!PVM^<Pj;@h!ZJoyOSf|AiO4x)%9f$d^{+Eybd&Xb|!&(E)i&~S_M;~4@Dk_7#4
zQh<U%e~$l%koJ<M95mTYgS%=XV>u`^{FM{A@;-{w1Vs9(r4F)`u(-@`A@3a#GmYf(
zV7AUGY0VKzMs|U?ECb5J17yoUssPy(9{AMu+o3V6NCF?&wL97U<i3-{aSvQ1*6llZ
zGm@5F+JXej-9R^E?eC|zZQ>kWqj7IYLiFWSUa`5cs0V)0r~^QrbinQsi9}@~y+zKM
zjl#Sv$h6rbr&#uZfO(=#CF$JBl&nJ7H6#T&@n<xL;z>j0%z93}tgoa6^Pv4ExWrQI
z7%vo33*-Sn^ECO#UCy>J^Ub<5$T>ZqG*M8nqb+RVtseFMuTf~EGCbAphv}11iL|Yx
zZ3CW(ymnmyBiQGAMCx2$amvRaeWz{&L)HMmJceBInf1=!g$3qFQLR1{yceU$&~ctm
zFQu?@LuG;gKs=LTyAaK6T!2Ea-P{8hu~YFQG+geVFk7w$Wf&D=wGYd7lmlmO??j?&
z(Z)c3Hqt?E_bJeH?}Qd+XnE9g*S+U_4)48G6}08UWiJS`Z9`Xk{zg5$U+uY&=VE{1
zNff*H2ZbCjOR~i$Red6jC#^tNSAdsL&qnq08zt@b%82Iuc{KHj?&U(^gBPXOps4UL
z_iLgW9}s(|m_0;=4w)F^2hIT~)9!zEgUA)6TFY*inHE`($bewI76&8eZZ=rXqBK1&
z9i-+gwL@#?vld(LS1rd)WIu7Twg_-MyY3BRr5p|=3-mSMx7c!Ku9(*RZEw{lj`3QW
zj6KmxZf>Gj(WzPOEn^iPSIi`M=CK2Xjg=!=lezD-HyRjCD;Gs?jk<Msc`HIu#aJU7
zilH_4wQTMWst+0BH7CQe66Z5(=8a6~O~-haT}TPP2aG7APLGkl4$(kk3A(w6qv4id
zjS=sK+<32#xNu>H{K8#2<5M0N-`55t4V#QcqG<d2<-_U9_hs~qFIM9m!yw{t09i=E
z&3-U%Q+ya^w0XzB#!sE>Bs*+=sZP0A0;ksXkLTq$8%j-T_K10<6O(@FKAz9g^xYZT
zr?8nL0AwG$`(9@dnwT*KXxEGKZ&Jr@5Drf5hQ^q_RL+q98oW!27!~&j`R;pGBhXKU
zmv<}I=a*nc$h+e}H#hf|RAz2_bZBf)W5otj?2Y&3c~vf^H1ZX$hxCw%B{XbapgOVS
z6RG+ad@TuRklZs>sdfN{T{7@yw#7`WLz$A*?R|qBW#FTW`^MrR3K_3rmjr=;?%Qi&
z9%pVQimPG_O1M_~U6odfbij2pw7m0+an3jJjRfyiwRWgj0(Z!RM!KH?z~)%g=R)8n
z<oxj52vC$+fK1l4s*9oHtQ5hH#(KFv$0vxZheWpN4121nXe_>SRew7-^lZl)(WR+I
ziwu<BBIoe(fAy8Yy3OZ+l9ydQ(a|$Dzm|dkB0bq%cJ0eg+;k{eysi%!MRdi%AGc@C
zS2+S6LDC5r5KFb*g2{klsff2flR5XL4)55GKL;c-6mQ?Z8bBNw?B|obg+D!?KVTsg
z?HtsM3iW^_fg#mrD<wWqQ2Rn0)-b#wwT^?ZXnpI8Wz+d#<1w>nKB3!ny#R?qH~s1j
z-TyUoM3Tlx-kDPP>L`2yG16A}%bGECewq~Oef=NZXQw4x*&4QBFc;>4;05vzpAZ=z
zW%yyd!*oq+kIl0KP>I3SpSc`ZWK1@FXA?*)0cKnc+`hl1B15FkwwOx89VKC_X7VFP
zrE;u1G3r(;+}NbetTYxpc!7?dOX>Zu?B`YY9`K`r?7hFjBz-*e?l=LJyyOASQBVF_
zXZe+Z8EN_d$oc{w_7x+$V-@qh3>9w(&w-SvKQp4|d~_j?G9Z}7>-xr)2fY;zW(v*+
zW(kTZCM~v^0x{KWAHnJqfAa4<bAdp7l_!<R8!sma#mi9rDE!#5l4i9I=<ktZ2J5Wi
zniopShr+^RH#DLHBC_S5-3-_rc!)w6#{d0{m=1jPCg6_k5^!c~Dw%^4)S(rG7e6h^
zH6~$mPel21bL~bxqcar!rVK}Rl=$S40qHkMXc<Xg1IhF?ArcbmS{l3iBxzgj0W!G_
zc-HwqgWt>32dmh(9*o5~s>PcBsk$={**u*hf;m6hoo{3Y)s9)K5+lJ);sY;<M}fmP
zz?6(ZH`Q-<gUu*~JNT4E)Wr<_DqN-xHjF~!_N4Be+oKNrSD_{A+u2P0n*>T5ZPD_j
znj%90T{Djvr12|wmUO6?Kv0Ro&=LeiAX7?3ajT*HOnaz_RoIPcYJx{iXZTp*+NZ+B
z?NJhs-TN16bi77!iAN3)J&`NgmF&LtUL>^sZKDGe%JTZ~N-6{Hk{xtGcp4tu7#VNa
z_6l0s!ANa#Eea`rwkb|HDg=1A8$SDXArFt8Jua@(kW~UV|M8&42F<Z9D{bCUD>Qf=
zvZ&M@Nvp&;{XnCJU7~J^=mlmO8J!3X-cf*NvN*Jf4o7RY6yFb&DvP$uAoz(@bg0g!
zMHs_+@|Wzd(8tY5?Pfjd|F0Lmc`mRUh;MBFg35#&$*<aqX5KgS_S)l%;&6a154DHQ
zLV)21dmej!6fNhDvIB=-dwY?&w8yU~kSPBjii_B84v|fKx=u%*IvhRw?a~VWcmu+X
zzj3{E?NDR!5F#_%{>q{Xwa)JP8bbkEfIpKW_C!f@Hqu}XL~|U@1_OMKHn>g;%0P<X
ze?XYn`GjC*K151ma358+?v^XW2(UBNb#N<1x>#OLPrA?lh?}^Uu*=3F)t3~wNW+1M
zCD_az=(=kLP_3DKWsR#A8#ZFxrvB8pq-Rwxm?4um8$3`5=}pyxZ;T_2VAwuIBG??w
z7DDX!qJ-^%llPIj@c{0v5-rH3rpP6(L2arzo!OSTGp*oE2RhZXD#vJ-&&_i?AF0ED
zMi-9t_X-f~0K-|SHJ~GQ4ig;lH^t7rS%3U}^qv298U?Ynw&3~4^3}N>=niF9)f5@M
zDjl9m(={@jIe(<-i33UC>vDjo%!QzZCOn}dW|F+OYqH7$V3nA;V9k_H`E>%Q1iO--
zM%Ig;ZItcp!(>&2X<Vax<yJcFEbei&M#De5tPG4h^Pw<d4tftKu25kTZKSi}p=KN#
zwS3qcy(k}lbudKuXg>imV_QmyNqcz-KiGnlwDKa{ph;-ZC)sM?L|szpy_OUvjqzQ~
zbS{|)qzbe%96U=@B^TQLUeY!GbI1!O>2ZWp?r>9D@=s!d1oM7|zQ2F$G$e)&fwr0V
zNk-A}c%jV(FJl~CiS9gn1&bt~j6e>DAFDjQ+PKBEro5KdW0p30wly!R(tvd`iK!r0
zDHqvCxQ0fkK&%ReHsz#Ot&-DY*R0~7D|3VJm97Qxb6B^AR;owyF_al`Y3**m=4%ty
z`;L7yZ>F0aXWDjN2MlqoQuyi|FSNy0AtwVI?&*^fNCQM0zz%jq)SrJ&8455M*p~RG
zh!-sX2PzLMw;(Mvq1nK*j|JTMs79B7ZJP9aa!4*^aZi)c`g@IOmvBAgE|u0@Af+#j
zb$_1tY$6$lky704!CXU3tLCNs4x|VlV8Eb*{w@E94i(QAW~WP8r-kJV{PQQd7qADN
zFqvA>Z&Fby-+yZ>jKSWM*_&$cyg!Hb+ALNT$v)1k6L$9M@!40$?%b0KgVO*27@9#@
zOvpY@H0H|HjNIM<EL&rW25|OU?Cwqt4++iW`+EfUbgZuLAbesy=w$4WEYnz7hC8=C
zA`<fbm_MSa5BKHyb{jt=SBla;&iiD>ST8A#)rtOW2J3K6gHcvY5h0^&Dq`;Wsa*9C
zYSW#g*q^s}Vf|Wr{C|3~7Je&DjDtbwP-x#5V}my&f|6fyJyGthHKTXlTvUklTX!y&
zD7T&m=X;0St}I;`v^GW%TT!H9JA$5EFmhh)a3w2x<;u&V4(&U<5cY4wTDyC@YSEx7
zQdGPg`oJd<i-Il&C?Fh|?8Q7I8(yKT;r#zqS)4i@PVubsSATp06{m6f%;qrKj7kR~
zC}Rw&(nM;m<wXY4Gk!H5kfC@5sW`-~Y5DhI31D%g;e7a;Vl~R5D#hohQj|B{!Xj+H
z;k*o%-K!mQQqOrT-;Yha6aAer_iucfq<mrWFcd;Is)hhKLhUcT;#N3V06Nr~yn$o%
z)_{{}B{W6-;dJPOQJ!;On#4~v_>e|hGOnaT)v}w0R*QXd@*ycy@*3o~1%A~LPL@4z
z=rk>OO|DV)f8i0VrRM$j0=ku1DfgG{st_%~Q=XLPKedh~Amut2qOJ8CO*ORIqw-ts
zRi{QCz+?oPad>u4J<zPFh{SRD@4LgyPtC6<iI>@I3ql?04nIdBkiOdBBcieJB#LjX
zJ3Ha2#7VFmoL#9o?hP~kt7O9U&&<~d@osN(yPaA8Wrm;5h(#>590Cl2bWQffb-XdQ
zi=>-PcC(Q-G#Qm8;`&ZwN(tl9EB&<aX6u$=M4BFi0>J5`U_tqE%LOwmqydNZydGXF
zE#Zco)b62t&@eI$es1zVE%0uhO%UhTl7I-fYs<39g5cq5{tJB4uA^$7)XhEgZKxpL
z2)hW8YXZ^e2UmJvBaduhIoT2u<U>zimT?hgyMHkg9I3}3Qk+cpAF79Se<XUifoST0
z4rwr39Zai+*(`63iYYro0-B^Zv^J)9U3CV=UTw-1Ma(3<MV0Qb`85lx27fUiW}%Wx
zd6XYTiZz7(k1CLb$FaNY!e_(3p>(bRcriD-p3lC@E^+i}&4_WxXrvpI4eb!B2pi|x
z@-a+?BUN~*!YA#w*|fWvg1iw@;k~lmUA#*FMJzD?Caleg<FE9MULh+F-+C5a=MTqp
zaC=-G$^PXt<r*eV%6ym6K`$C&eRCgNDesB5Rs548C^BQJWq=`SORV4Or3IS(C(B3Z
z2RX5WT!Wpwc6mqkw6M~hra3}vX|wF4clx}n);x+mE&MoA%XnM$uslqe0WHN6{{Fl&
zWy4GU)L0VF4YUnulL#eOYbkB$>6!o_MQn|Bv4Fm}rf=1(^hN&jtr3zwJrAmD+!p(2
z#?lnGD(-fMI)Xba$42f<Mr~=c5yl7>AkkkLvE)W1I(p3t&FAOtp=Ry6A9gwdlrm`5
z99Rer4bA&A*e!3-D&Fx^<^#W~J+dz#ZF2Fk#vz>TSfIBdg{Eq!C@s%>`x@Abc6rMv
zv0|{%CYMm<a}sC(Hpu?1gq?PXG1Yv;GcqIG|0l!Ljw5`<^~v%oig)Cn+m+?608<b%
z`lF4@IK(%4fspHIh0?Cl1w2OZB@drS|D4om1bQeT)svn*CU0SbGx?zRk8&J!YmB+v
zii`!VI;RU~AH6~{pL$5$!t#;6pE%!1Ip*)B8CpGa&H@bAwLAOb?&~^%K}n#a$s_2g
ztmQA`;1Qgu*<}8h_DtE2aRt2LeT4rj`o!EVxCFrkAxg3xVwS{xs2(S}{3FW8O?rPO
zE%MK-cZsFV_{mdjSe9=8)gTO28()Lqpjjin0{11$pepG&ZJMx^maY^U4`pOd0nwS1
z=47IM)Hv=CkKh*9ol~WygMwu4w_3P0qrG`5M2Ar?ipRsZ*V44fnd`ibP<=tKINX39
zMcp~8yKu2wVkWg$lwI*#LX70DivE<ZN6D-AZh?Dw!H^PS)9jz79$pw1%z~`U624~;
zIdbou%+M4Yif0nzNw0kzciu$JB<MBVkuuCJ8%A(IW4v1#gQQiqZRFJ{EI}MSmS%gf
z5iyCE^RQjtWnb3oe&*~8MZ7uCLZgybB@=X|RPE{m3fAc1a9`*p|5-X+nvQAhfzwIq
zOhV1&=u5mC_-B|UAT8chDJt#V41k10D9P#)S<ztE<Q<=@hG{@hd0Z4v>k8UsoaQmz
ziCM}Yc9asL$F3mrvzIuYd+07CemkZ7Z0h_oFrlV``$P}t!l%TSf<q&(3#7fu0gW3k
z)q8N8$YdE@^Khc3R@FwTl*8AmkBV>m+|2F^ctPN~2NCn+;$=AdOw=eKt^}hiY0C6@
zo)7SXKVt{=8wRl3n--)-7ON)s-dqiI`~bx!>7}sy(tTRs&#(=2yh7rH6-n*TL&}D*
zuaweqP7B|W^KnjZUB`^{hty;Kk-u-eP+;lJ^dMjTw;x?lnMDGe{4FIQb?QDQwfaXt
z<c6!md;m2XpQeJv81yoaV(6~6VIJDH4nyoqMMN#Utt^p*z(0eZ5RA@J6F!2Dc<9MC
zga<Z_eft=;Dl5>Zzn<1X+x+;1V*kx=Qa0@7_k*I`_TAHpQQb;hS147%fQy1Ljs;v;
z=i^Q(XpAhYZ+g=6V#=o6HbwWo!f~r5XK7_~!(^tB{m+0}rO#aUMI{AzDYT!HRHeh-
z^=K7P-!Yp3S<!yH2_#rhI-Lxrle&H=_-`ys9Gau>{21CX#o$E3X=+*KL}*$-?iAI-
z#DCXl2MNU3Ah!Y<vWs!h#`O4JauikeyK!H90vebe*~IA|&${`Y2jr;>!FI06%#wJb
zRQe+0`o+t35TITaVDu`q@GLm<&k4xj{u=FjEPKR8($e!l2X!M?UxwNMIl@kwdU#+O
z$(btkX?Zjkm`B3nhl}*G9nuXYApX7JpaWn7iF+lt5?hw-m{VLov<tL5+a_@0%bXX2
zpH(GGbh~H0%%v7Hv6?2t4KE$2$!<h@tHHdn<(?jb=~l<M?fTg)`@d$9)%&c3K8>~k
z9cDNKEzmgvrxrToOqpc>gb{fmQB)3TG@r)TSv+s9>yxB1QK{<@s~-@}Yu-m4JgI=k
z#;nm(?U+dNy=Fy1fWKrRl}tbq$2r%orsGof4Yl>i4&^JdW~C#8q)lraG>@C{ykCXi
zZ3$Ysfmf1z{AC{Cu;*EY)eFFR#vkP7h~AOINLc1>4)!4G)4X~wh2aH7Z}<N4{vvNR
z-)Hik<<?)KQ<};!{cgon@MO6CtM(T=sNmhE2N<#Kq%Uj5K>%#T!eQjF8j)leX0&0(
z;<HUnMDi-rsp~ja2_f{q4$o!W=rHU?Ww=?jyiN3_CAe@OE%trj6z<`}y{jEOu`Z%k
zIIPr^NJg)vZk7K7#fT!h6_Y-R@`@+uk}Qo~ui#+^&fNLC6-|UHYhzpyK+9LWWbi=<
zMXY#vSXasDdfH{3H_8etnqbUrG0hr~-ty_Xv1wpFeyo+n;-WAe=lm*=Cm?o)LDX<z
zL^vEG1$O`QO9EdGUxH~{+d3^Egs0r0I?`dRzQr`T)H^Dq##>v%N5+p0LLDNI^US0%
z6eNDzD4&bP`Kd^D5j<j$qofc7jqshO9x<Ey1ynR)6>M{){9)^>eJhF_^>&gBoPh$t
zF!1e+=Unp7Jyp7Yoba)t?6%J3by|q0?T#Jcp!L=a=(9|4Ipx(41Ol*VcN+5(_BnCm
zFnf0-c8De*c6Ii)YxW-uLpy;71{J3ffn6ME8`jU4OcuydU{i5n7_P4`#lR4tJpMw9
zPIOef6Cf!&jYyX$skRj|tbfX2z&XGqGin6P_XT_d&9yJagU_2P((9V<5UE&MuY#R~
zLB7w4^HZbScST|diGgUIa@~3)n7g@#D=xHkhAgB+2*bKtKE))hD|VhVcHBI6dnVl$
z+X-X#K|2X2qEIFi%&$EhxfhGxmJW|nyP()(`Jaa10P5qh5;T_<5lG|VL0%oR7*iN;
zY6K36rx2_r*H1RRN_rucD;V986A;fZhTQM=kJv%>6iw3SAP8>5RV>Wav<GkSu<vPH
zbl=9_K!FR|UlU{jX@$uVS%>U6eCL{*s2dl19HuPugQh1r6&D<mc$jpy<3fQRT#*n2
zcj(w9H)VT0ou`Znzz%=yneHY%^6%Xf0z)%ittwP0!yCy((eE$GRbk-gQ`^h)^5K4e
zyaXxs$YW@oIl>DqXje#OmG;Kd>iVGFXo=59LJF?tSfk!29|h@GgV*1-7MrjqUSDy~
zo3;m(a6QB-P}WXbY8ONP7ce96C9nNvI5vN@90hl5kXLVQj&2<$IX}<-$PM|w4}Ksl
zqnC|5kq<FTpI9=c0eV-%16n7cGxGMSnu=T(7_U5ECmUvluGEf!q4u^;wbN#ZbGHbl
z36Gb=U`>XS#W0hK{NjRY^qa4bFBuK5`Az}u>vvw1Oj8xb2jH<Q!~!t)-6QI^$f#_r
zx2ZEcc}6Q%*`PsN53Q*?Hf6$XFUa;*hf`<@3n2*Q<vePnJ@|#T=8o&I$moCCWZg{_
zme@)s+fVdc*#zORw1xcza`{3ek-}zlI8}cvHm98}mpQY=Lfcicxy+c#chF#pfMKZZ
z30I;?)uEekI9SNdy%Z|i<id`DjBj80$NQ3lOu<L}Bb5{_1BZ#^1^G=d<Ptw1kGOfR
zv;@5+CTZK1rm&g>e_V6?Vb!S8;Q)<aY=`@S<vCshr1XY4U9E0}laux@gYIg)RW0j>
zjm-=mwD02rK01;zPiv`)efnMzEq7FzG<nnP*kUU9O}G?XQu3?g|0=z-kc8eIn`aPZ
z4@+AXnEKD^vUSfcRqArUiB+OVLHlG$m^Zf$yK}cFE#+Bf4l<m-A^)+i{WNugxFLb@
zZ%xnoRl3S-(L2tOOp>{ew2z%fv{1zy%E;~BT#l;rZuA*SMFH39lzRctXmrRJL*8gd
z>3A2ZE+5V$sb@2YqM?P9tB{SNgiVjzE#4}{U2$gqkg#SX&lTvdD1Hh5>N9azr(y8G
z_jGV_C^(E@LsHdrp3N|^Nhy5Z*Pk=U7`=4~%?uiE=VoY9tlXcm#U>M=Q%=Thm-dPc
z3g?!~mUgj6*;O7DZ}6I=9uEn8r>o^*zUt7s*FOBYhQ4nhKv)pTM1HJg=9`ds73T`#
z*rMSXZjC`)q8y5iDsrkcR<4F2V#KLY!P5x1aI~D9vE)v$4$FBPWfRY?05(=sGz)zG
z!@;CYe2BH}XnFr9a}G8Rrju6jC+Imjc)YB%t(1)IFav59)vw4k!1{l`xKkTVir)H~
zGMw+>nI}AgzjHCH>>YR5@m<D9RwW14T$<Wbnp`vdLt;;|u-_<t-@YsV&@>oD((bhC
zEP^6LZkT%P&Y!EqLg=i+O@Qs^m|92&k2_^u>WMO3h9dgt_>PS>Qjk~Zf|4ADYYPnl
zn}p~%5VN^<#Gltbhxm}ptZCBm4}n<9f1WAjW21<K!uSexP8}o3z`5{zZG^4|I?^`2
zM7DlC>xD5N$!q^(F;n@L>K?tNz(bc=WrqrT<15#Ut}lC3rQ!Ixd<I7A#jo30^~4#$
zK0lN7Xs@sny;0UW6z@Qt40HO5FDIT!xGhve5I8={)!xlH<%N)A)!55B4lS;uo}zJM
z45$1(Xe27JY4#fW1;K1t_sV@1e*(w$D34%#%0(>@s6z9Bib;;G;w>wP5Sc<LY{(ge
zf3>Q1*Y=aZme<dI#(P8hy~kSJ+`l@i=v5c<uq#?r{#Q!0S0d`%_>EV_X1rb>Grj(S
zEG-ho%(TE*?y|eGhNG0F&l5(OyNC-u*foX$leSo%aaNSYhxqRle0i99o~7h1s_iE;
z-pZrK#(#y3mLD}m$pDdevgdPYiWZ2pWsp`=MrS(3eWT`6(!#y+H@dKjmhkFGVkL``
zZ1uzBJ9OsyBXqDq4f02wE}fXd?k|dv``C>DS2UZcXQw{UxUQC{o~*nsAZDq3-w;r4
z19%4p<SgwITU!j+xXN<ptV4UH2N`5t!~A*{?GAevPxU~~2Ih}JqBlVhBfsqUl3cO$
zU^o4RIGH~yP4@@3dfEkG6s5l|t^AU4IfD8fh1Mfg=b$+FM;u1j!9}_dPkwtzXnVf?
zKn?P^#6IA@_7wa>O-M0VI1;Z?CKyy=c37drKxf9pFJ714M5=HX?5RY8$`1w_2@$gn
zRy89Mcxi`{aeD&uVrazOfRtHSoEsZf3X&o^w{rI)R|)rSLU7K#@z|iAxa@YOmvklq
zq%LKi@<A5)*8Ef4hl<gI{_U!f)0MG+MO$3By~gCyA8xHs@YWM_?vu8oV+A@s?gl>k
zX(uT$IucMxP`6&g!d|zkg5FVuv#M%i3~;x3J><bu<)Hj=ko2^!++rT)SVwyBqh7(>
zW|#N&@^<h5_W_48{}KRA{NE|aBc>QgTQjttl*NwL8<Z_bp~KPtn%J(ExL8`g8o~C0
zWy(RhS~;2l*BhroJn?-7co`sc*h=pNgtvsSyC|&-NO8jT2r2?|KwzY$jGIaa(!h_E
zug2X$bMwjC;;g^-6?sG<+d<bHXcy=_joK6%n!y*=yKU>4%eD0U@{40XqK{x^;%^#`
zVt6B`zMPG|01(PeZx~Cjwp}yDa%TECun~s6h$xtGrPpLgH=w-A)8^icJI0r8&{}vs
z`FbE!vgpZwMV@3L{aN%4S#+$T7Sw#)Ng>hFtx1wn6hL6~!h|2(R<W3A-}k!V&K6A1
zWD8A3B`Id%`pY4h>Du$mWx=(uOk(lTja&Q`J9=UEY-O-v(QA^ShlFu6{_9;Z;*o_L
z)Z6iMZzG|G$nthl5?@W&B>z=>4DKr354jD2<Ak7XOtjzi!Y<F}Keu$Jk)LqsQnz2(
zc^UCVBu;)^{_d}oC<icXlX8zk#yI!jM35qq<xcRY`&o^vT|ObMvT37kK)e-I0`cN`
zd<Gw-Nxe)D4p@Ip!)U>-m^Ah7Z(FJk1S4h&hPoDd4ccH675&ipxzb>*%^!UBzafZy
zH3o4}ejjUUVSEtY^0*InlTEyN7S_5=Xh_XMO{5%M_yDW|x#ZDvz@Y)8PK(KPox>L7
zOO#kl!yioj8bnd4P8Ay@LG8(%Lmk~^R`VSdwv&X{gjug(nkW7B7%+><s8s9HNIjQ9
zJ!f>PFs4`t+rGd`@&@acLmL)cBSm<sU;sSxrzEv%f^4@bGA~zjPH-sXgCis$oe^80
zmj+atuL9T`F-}1@(}DM<B?(`%M7##YR)pz~6XOosYMxSS0>11fE@3`IrTEggl{Di4
zO(qKv1Fi7sS)DkLe319Igm~$&$*Ks&r7CqEQyN?vA|^Y+nJ%U*TN1VeXF_B}yPZ%Y
z`-@=Tp$^JwG@qbMX0lwu@fAL!dg5hAGK>-!U@ut(%*hq4R`XVkjH<K>jzbX0E8jRk
zJx+vmRQ|2V^kIWQDZ%>k%5&<zm>C7X_MBdK(HN7JrCvjp(~=4z;TxenMnYMB?310;
za^%v(9Q9zz<`7VWu0N~aXfjbPUnxJ?v=!h<sG+us*f0&Ulg;g1>hUW-u9j9&uP<Ps
zy%L83R}&?_EwTynorSTWXl^EUv>HelCeBK5Y*UPE1c^Q--OC+}5yK}fTJh`1LG+n!
zdorDc!D=uf4Jb8s%W$<8eWG>0(Kr@W3Z0T@QTWA~WQ`=dRY}t{@jA*m6Y5QOAiq76
zBuzAN%u!3y&Jvlf%+W)(8``abi+#IrJ8Y_WdgUlKWERO7Uc2Hx3s4Ccr|R)OOd<0H
z{mMM&oq^qXg>IQNc6de?jq=5TfNP2w@gSfn87~WebJjNubNQBHI3=g*({$z|%{8?O
zrHUW{vvV~^4)n`Q686&?DpT}43y1B4sdtXx>tO^N$&fzYJ)C83{po0gq<9G7sPt&k
zMQ-l!19`vDbyx4Pi6L8wJo|!O0mc0K(ddtuYN&bPgzLSR?dbAMUX|oRTFydcc$ou5
zJcJ{~m=H5+^Ar%|<P;XbZr^TWnd06`h2D_~ro7O+<xNiCC;`4gOgrF12X9B3ldX~q
zm$O1cC@Rdib8j1sA^YsjU*sTEE}sl$?DrddSTAQP@T4IZP$A6ZxaWjh-}Bbf!1FpC
z9iLBUD*#NcYx-<=xd0<gf-3=N<v7E`hqaOawUa+uK;1QOQ)l$pjijjwlD7UD%VUb~
z6&FAO3&EAqpp3mhR3un_1H)A%WN(%1YqL+y{{uqUmw(Fqj3pD$g)nY960--GD3l~+
z>HMm-U^V)E<{PoJT*m3frC9BC6l24P6r&+T;14u%LQpkjDB`9iPF0DAWBabm{iW4&
zQ3`Ry6$DkMr$IgKVJ{U7<$4nUwq9d~$$%Wc&WRM#?XKE0YC@r+5#r;h6gxuhCGZ~9
zYQ$!`n?zw+pcZK#F%gMpWp{9oE|DyX6m745qt=IXPvGcr{dbth0a3k${`*%P@Cmv0
zErMP|k4b{qbv=NG0o8B-q2?z^+N@0#x_1G5dE+qbx^y{moLgTPl=AS1;x0y~R2ezH
zNP=rq?&8sG)4q$|?*3pc@dNP0i(w9f$cRV9U0BS!{1hwT!r32n3-K$wgzB1>51G}l
zT7~s*Q}hN+A$Kqnwi4*r{)s$IWqN7V$~<!*V<w$=spb`Iy?(5q)tZy21^y+BL0Xd5
z9<izk#L_nyY&@Jts~IJMuPebbpu)&48*wCgsE3I8IqLYyi+FB`KD_au9P5Cpx?ua7
zVZIucm2DER?&kQqZ6)*JQgx^o2NHYv#K>?ff@GPKPj>y15RFMjTXnVYk^$g1AILZ>
zwdmc5YyU$FN5X#twwxOQh{s#I6Di=j3JTEMY`(rMm?@EEdx)M99J;KAJF^&#c)!3u
z_TuOR$<WK&3aW0|PWfJ^$0c99ffN>YZkG>>jX_KPf@emNWexF30XgX(vNcKE1?}uf
z@-bE<*fG<LYWHJ>kP}OR?uULnN)5bs#(#!powu`sS|)$UP(OP;Ky=Q^tqiFOVYJ;z
zN+TZZNfiiLcg<<PXQ04=9WQYGP>`mpAW8~#>_`_o)-KzOP1%y}=?$WVRER(%z`vM>
zO2#|@G(&IXpvvGMSh2|m5;02<KsOsgax9OJzUyl>(CsSs5u+X6Nxv6FDxUU`#3y7v
zMZR`qHj+Q1+K+Iwk$+n_*2|%y1Q_hC0Q!!kW1u&XnDso@(+b9jvwt-X@A8(y0}Xe3
z_Uu&$-N<S;OS5!Y4ZeLUlTogUX!L7%&@Sz_JoR2hz@d6BA4pC4yie^KCYw~WFPQr!
z)$KUiR6p{%>HEG+?Ggo854ObL$bq1g<S!ZGv)Ey(yX!f0Nw0IcLfH}-x%We(B@INx
zBu129MKy5A(vnr_DiQsO+h5u_RVfKLQne*fNe~Tr{GMEy9OP{j1r&V!&zWXJ_6lTs
zrCU-bpgK#+#3(wp+EjFHAA~-gl|OiYGY)33%<N_+=jwVRL(DOaluyoOk~W*8CTi-U
z5KPxezK`xy#=HP|SjfH{eM_|mu3@Ik{5^Ll`5PwSk*Dxq3c0WJ#_H5|+>f~o9M?&w
zn%=p5oW%uf(3Ndz4P!AirY<kH%M2;I=sM@g-dhrpN&l<;fh6?cIo}6QBYFnn<QD?R
zmGzB@R(tK?p-0WJfOK^%Rbdw=+M1ft5GVY#v*MGfp0qX7S47EPk||?SYlTi51vKA7
zd0<cfs5NalfE^CVzDVV@6J?j&uCc2cd=rI@eiLBiBhRJScp|k6L5e^QCUb0X5+HJG
zr>rlKS(Cd<7@XlyQj&lU*ygb;v~|^#^DE$i9lXqD*V%8CJS8jaoXP#$##ZI-z*MZf
z+c}Sy<A3`rGav(@YJ?QZej73+OkoAZQ|!$qu!#rUA?@hrzg?0C<mEfCUh$oI9l{!O
zKweHF*zKwuSj!Xe(>X(6Fzi=YEbeA&9H;$!5LeXk#Dt<MCLQxB$Df5@Bay?GW41|j
zg^?<?Cb8g^>)4S$ioqVch5kcLGn{<dHc6=ZEW=~iVRI3rEcnhsB7?&%zX?3~cL4=+
z@sxL1GofMLwN3P1G%D#ZOXriF|3m2-2jgIx#F9?ODHM9WHgm17zN1nNjy?3U#!09}
z^|p?9ufD_qmm_iM>;L^SUy*Z|vZZf4)iLlR(>KWCfDtE3j2c{)2G?h21_Gq-s}EDo
znvTirR`lfPkj|F@Mw06OMc{gm)1fK=VE4378mVb09|%Vp3V&xv+41!VbWj%t7~T?Q
zcm-FV@;B>h-!3EZ*p)#;Bg(I_c5<D~Vb~#!Q-ZC}ouI&)6;(0!702~0&6=C|Ed?KJ
zV|Xt1(v!~2F9e8HF6DLmFp8!0OEE-YSc&@pzEW*9#Ujt`%J0B`ozfPNIu=f35S_67
zPrSs{0fv4B=*eb9+_W<BF-B`qMW~{h+sAZx8nsaL2dId-(Xc2nzGiE7m2r$KLeM@&
zh5thAOU$`fQRO&6PWZRGb9Lm7zC*f)C-vlb`2k#kNsuY*FTQS3gxS6MsIK31HJ^I{
z=w><kV3!lHH~83O;kCgmEiES30(gi0uuPbKDWIZKKF3y{71cs<Vd(y47(=<4Z0|Fh
zhkq_Nf4_BbWm?VG4x+U~mS^Z>{bS0@Z=Lz4i5iwWaH)jtxk#Y^`((Upz57&XTxf^7
zSAVKCst0@Q#pvl>o9)@i)v`I&?dxnVDA|eP9DZwmyElid>J1@oEHs}u-`GM`=dO?q
z*(vOe-Tf*-?BEW~W(=1f^qZzhus*088793({QECNO7}C+)|6^CFU2x}cqX_F|FvZp
z_eQe0GfXVWCe^sS$`GxR(6rS}{CbqwP?gfYibi2Q(l46(v@zMCKxTkK9bxi4SPYcZ
zeU5kdP6H8wX~qAg35yNknh0UUV$ezA#K;)M74}!pMZWx}ER+?TGorFHoKqO06*!3%
zeMUQ>%#fESDQo6ka%h*u;3#D7H7_;uA6&d+Qw1n^YODg0<WgO#X1{r5p1J9^u|tG;
zx$3XK*Dpu4&?_A!2VFuNga!JAd|K(7sEuYb)VE4UcNP?O>xeKta*p3j*?9UzA7j34
zaXf^w7vD0M9LToB-qrG!OJm2XH~0BBMx{K}RJ~F>W?_H#V_zybZhYa|EG^XHa~eW$
zL7@sdKTE@)ci%g(pHhM~i3j==dU5|_B!tu96XB|iQ+=eX7>C0meVd(^76lRS5&jCI
zA@BW`S-i#N0iyUyWV}%wQLMh6IOsGUIIRdIf2xkfbKIW^k=MBR3z)U29)LJz;Yc)s
zn;r=}Wm`suDtC@67y$79ITW4B7^@57Ij*izIQmYIjr}biMKdcw;M_U_+b1{`DcSvR
zgs9As5hd5_Y4JZMh#sm#e(2|z{&MZ)#g@U;oMenTtChfuyl5Q;!I@&B(OR|9k?n-Z
zMvtQY?_X~$zOMB@Uok;lH1G<{7hH6(iqMBxW4eoy?faM6u$}eN(r<m_sr`;A_nDN&
zJ-+FBwig|*x1js{H!I$HR%`%VBM`oUp<m#d>7KEDE}Z&q<%R8dU=AQ7L2cO-(yf`d
z@@7N&m<beXZw3d7Q8+#?0*6XB7GSj~zV(?zG9Xj&N+?*q@-VdDcf5#H!SYV|EscSL
zwZ7m^p#e_S*iJd<0}q4`t*A%q#aWy=ZokbOHx*^Tm%ZgAA=hgT4_w#2N8Mk)dCev&
z=MI>neVw8T@RP6Q!=F@%pmT+wJkU&R=g~+#hYpGxFnGkhre_Xj8}Moc_>tU+j-Kd<
zh$-Ki&gwK&jDM~+Pkdb9<`wr>Qv9D&s`Wc7E@24GUlRG0*toRZGmGwAY>F*N^r_3w
zs0P{92CFfgSRsYV_nG=R2MX0dJ;9WpE<yIg6I4dCZ->EwKvi8f`m%s}j#x=d$<R{(
zm^I|7-$u|^mjQnr2w4a5n2-_u{o}Ci%&FGCv#gg+&T1u;o-NJj@@YiGPnm?X;G`>x
z6*nk7Qybio;fK_PwcBOfTkFnru0<<9hCe{7q@-E<iKC90^GT|x2t*cMyLbbCvsB@v
zrXH1=9gzvZXAkjG`J8@aWJL~-aOS$7yarOdy-ZASN1u?Qm#-f6-oF3sT2=FAn*0r4
z=y5fjWbC~Axm}`oYPIP3+2a)q2y~rLEIOvb_0m7scHa{qDiz>Au5AHu;{ERQ^?Z%X
z{shQ~{e}7+>G`S3%ASF&<X#=9$qh^4=^*PO?WeRV+24qMK0B)FUG7Cta-9;INr_aA
zfC5A>X94IguDo)#CWgGY-LWR#%i8OQ+gsPe(OCiLk-&lf^4+oON8CWad;wh@Oes@a
z85*kZhsSjE#Zsi|{^`hQszzq<6o%a`%-O+p^uJGLCi-XMD8-K)V$<8)z&>@&MyGQz
zS5&1@9`D*&1mC(+dz-+40BRdfmJ9HL1Vm^G<Ega%*AjQ`DlR9>4YOd)Ye3N49&_b8
z)YI482%`4}b7K4K;tvFw?kQxXKO5y{C8w&7kb-18rn!zJ%2&Wph<l9$aD(tnWKKN+
z`Kl^8FQ9nO@WZ1}jQzqTAoWZPgR>074ryC<Byx#f`Q=oYtbpC-R;ktPTC$dL&3|r9
zNmH=<g6{wad=E%iIvibteZx328)F;ov;-Y2Q^(j$zQ%@hb*ld!3noP5Oi^}is-5+p
zvLSK<_EUaNUb~bA)G_hhvy#%y?9{*umis5Xc<kMaqmnae-6omk2<RZ7(0vnhBRn97
zn%DZF@_>>Z0>3r7-OJCGurl2M=1sF^QJyKgi;qJ2Yhoy1icrsvrD?e>y(n<rUivuK
z1uU5xVNW?TL#q05Z+QTwC!cRu%k+gcZ{rqcF?O%9Vsu%%J&W3%2=}BRk2)Ukg;5S{
zJUBUgyZ1S08H<B5-9C$o-{<utUq~7HE4ax!og!0V*&rtcgA&=E-sNt8;-(WD!9Lxh
zWu+q9Jq8Ih$t8fbh+nxgUAt#@!X<AuHG1bA;s4*e2Fs*xp5p-GGbc1&6fAzu*nPRs
zXHZ+ltq$Y`Wa0!!mviL_N+Z~jQqu0D@<J(F*a0lQ@x=31qK{vY-d(?2VtmEFd_uxE
z5%V}7c|z-{FbWK=-dItnjWC-`5fj)~+8is|*!uO6oDw=a?1R3AIL>B>xO+7obQ^mu
zhiwSfarMh_eW3o@hS<Gs?xqiQc3zgFaadZ1ZErHS^9ApF9_AJ5qsN%-3(3eq&MDMg
zZ<;qU!n&Y_q(e>xxe_^}aw%bc7ftgP#42p#t9!~GltCQb@KH4LcTsvdUftbJ2T$GP
zrww@5m`)J9h%hWz(FA5*N0)dtfv+V*&HQ_qta`=nJ9MxrzH~&jDEr{~Eu07I+uA>X
zgC~3mD~*YFL!mP84kHRPz#y+G`7w0W!;^IVRNXWq+LB6=-bi=YgwGi49+ss^3pU`m
zusaK$rY^aRmWy>jlrHFc7(BYJQ?WCC^6l(g$epLuNqvhcT*`I(JQ&@=(!Hj0tTx2(
z&<Qz#M6|CPS6`XhW&Zft+^lFPl89v*R9~DE{?G<h$Q9JbCBAPr>b#BfXSw?{)Z^<k
znU2w3C_9B^c5=*R&w3v(opSv98ZLk7@BS<?{zRbw#2fBwa`6tei|A}^CoYFK6!@x6
zU?zZzB$Z8YkJCTP+<l96iXu@sG(64Vr-_9i=h{QBPL2~g2A7mzBAePo?Pt-D>-sgP
z8pe!TWd;Soln)!Xu3**FDyBLB|9|<{%fk>hPyN`AQ$K#5|6U9wqW{BJQfU==zldEt
z2-Kg`o|eDE3tWK&H<#hEDkRv#4kG5hLDSOdl1?<{;8!^t@P3PUTe6V2=arK(Pv@Do
zt^=iX`d3e~YNE_Lofx|pQJ?ae2r2xLeRDCZ0kp#O|4JFTN*_?E<*@B-7*o(aoYA<J
zr!<ae0-14kUiCI!H^65WPARNcmF@b#hA=>cG2zKUg>vbQ;PkkGKp*>j;ELrX2{BHY
zzJHE62!g?eWy)CQLQKb%5f=*(^s1jtCwl@zo~myLT^@q!;rrS=skto5zRPhZ_?xR{
z;U<US#|7(q4j8xrfPs&6>Vst6Zq`cv;WhScRzzScy`&kIRM8N=7H-SfxsO_uyXLE>
zxnALA5U`Z}RT<nnV{7;4!Wd+l^Rq@LZv?{G?)1q+r#S?;8Wsgzz-DQSN7d7q>#8Hl
zW6r#7oPm#np#AHa_0SC9l5=m<v&z3(jUjO&>wwxDTLggfg^B<pI^IC<SqA#g9jgsH
zAufny`Dh`OPkiIxAS@fKIaUJsO6DW(KpV8eFS>;@!OP7m%zl0*4fE}sKAf=BU;&6M
z#e!#T=1mxhtV6+OSt(<e@qCX_M9=3S<asQ9M@YkcE>$^Wb;4Fc;+|L5RNnWc)oLKZ
z$9LSJ`JuZTJY4>heqjgtmgnlXnQN3L3vv~Ajx+=+6K}zXG0gV4hk42m;$d78>{Z?i
z?_4z@E`w09mUnHNz`>>_#UgQb`Jkl}d|FjWJRCghS!|8>Mt`-$_OZdjqHExcaMxlI
zEjb2n40X`?8jCH(^WJu(^Ht`yLiev<Sn@G#narU(%d-ihgJ0_hUV)IeAKA*)gPFts
zuv_%=r%uel1L$|Kghy4befL^uyQGDq5rZYIus!06j>V&<6WMZ^j#ZcuJQe22veU{u
z!)<OX5kHAAa)gnS*mD$Ca5JLh)d3hL6zd)KQ3u!i>!w(B*?tmv#Z>N%)s+8zQyK5^
z$c`Od6=8d!%tudRB|=-^bs)MnY|1RTm!M@)X=^P^VaX<_jXl{=wNo#D;@zS~t{;A*
z!#Y*bLl2-JLGk|E{m%@b(if%Bik=Z?hEf%_+yVks0t^Ec$JijSx2@q@b>gO}GJ<sq
zkw_!hqv2x<uh8V~$DR|ES~CXg>@cI8;cU_(aMP5Tbs(Ygnzv3;v&am&ApVM2qFj2i
z$RLUut$Xx)`8N%ri%iGGO-PR@1~vAD&Ac+)X?mdILpkw71&VbrzML3ia&$s9Dj6-6
z3601e0U^l*VG?k+GYX2!yCU$wSNe$Cvldc7M0%yFJO|ag49W4kSIx$Bsi<-<ianGw
z{$&<cOmG&(%=_JGolFXm@$VIQdXWO`8ruch?zN#`sWWlZsq%l0;!M?&<>gs|Ci_2a
zZy2yG09BH!L6dtIO1MKK&sY1wpE>E{>^7cW-&+qDvi4N5-m{(w6mo-itk;pFf1AK&
zGC7}?STwscC9HM8Z#5|qAM1EY6>(Nl3BdP5ib$?5wi9aQeczOd$<?tek?={2R{l&|
zI%*GCZ0i*K;ic*GyX|+D<nzD7__ar2ABl&-uARi%IPy<maHV93p7j(YgH<|%wIWJG
z;C^}4`xKpo3^_3x$dL*9PMkpoL>c}nJrE9XQR^VLr{${aSnW5+vAqmQ=)cFZq=R$0
z`@JYQdfr!a+uUt9%@v%AH4VLjG1{X`BVdl2i{u9+J$WePN8$5T(H2!N%wX3{u|TEj
zAijBDGlCZ&Rv}>`zI7ZEf89g49q$DEac5|Fw=q6DHQhA?O@C$*n2@#F!Sfgj&W3In
zGMW&1TVZ0i1&G-Mrs%=sqb+fSB8Dbx#>w%1nt+C50=%d~(R~Pa^_4<oZoy*i92wa)
zBMPEbj0}r8n63zfET-p7-<ISBpm}?u)B#C|w)DLg>B)?^%isAs=52!-G%v~_0L4(F
z>7I|nNbsgR1I0440k~7%dx>hY>g+DpyH7m*9d<gu@P55aHy&AqUK1jB;mgUTV@jyR
zX%;d_XaYTlvbn8I0A^FgijBLkabR7s|6f(uZFd;(+h17{?7X<1+}9M?sdvBQPO^G-
zaEbKMWfj(i0E#I_413`<iLM=J7z*{FvmT?J<B6@wn{)-=>*#Wjy+Hm=BLVeNOsepv
z3}UO*S?h;qxUP@+bo(+z&5bBul{<KwBz})}&>nH|l*pJ9=}K?9lETC~->K#XY!f&+
z`#&)(g6r(ottB*FWJ-R}-_F(>Iiy^~QN%aYz$h|Lf5^oObi(UU`2_>P)-h-;Wnqh9
zK$CHzOS2?Bu9?-!5<d8e^`Pjp!zpF$Ew2C12>h)Uk2O04R{Vgc-d2Cs%mb5T;Lki_
zXTc;k)9(3p9Wm{Z<0Bk&rK*wi*{$tXf1XU^RRjbp2X0HYW6w5ckAYF}`hk;Sr0`Yn
z4P0u13!pFy_)fo@-2!KTg$zjIf?xvH<oefyr@sDN)l^;*scJidSJJ_>eL7wwn`zrX
zSL6ngAOd<QDO;$!fwh<aS_zE^xnrNA3gb(E6`a@P>+cJgpH?v*OCxai?<I9q@6PI^
zfj@g<pA*S?d~LMtLm;NzoS*3`cL`{WIWvR_1yVE);=VgRO8B4HDJ>xs0x#Wsz(5kC
z^jMNZZ6gfCuOTs+UVlq!dY<G3!vOu1%Txnqms@i>!z5ZRwZ7T_2R?)cQK}-a0Cyom
z7gm#)^Ee#cugcyIp)C{X3k~>?R^u0PKSqB`h&E}eej+DU&DM?MqM*8pa(fH2=)z%S
zbgB`iuTxemF20BL`BS9bID#lzuHV!@!ILC8x$D8S$NMkBs1a!NV_8OGSdD#VhGok7
zR2pP5`_C|`a9g&oPeP=ZT|#zQx;@Qs7Rj@*<K54ZJY21U66MAPfUJ`YHl{m}v$BW^
zyfyt7vSho-?|m74ix98!-uZ%BRx|;h68>5s?JgV*LD-&jP9iAF_n#~yPAgo~OEZS6
zU@UXVTAg4@XzkH%FC?8l&c$}~>6#$SOGtL?j``?d{g{2mZzmvbo<-5G>QHD&eh;f>
zg~11RF6p#FrVeYiofpWI*ZsHCuRrMsI$7>>ZX1e0$1taM-9{`rp<~&2N~0*!?e<>H
z)7Ol+sUits+lrQqdjbdOjHvJlW4<fK2dO4^JW5m|sb@i|VN9z0Hj^%h`;#tT(76T{
z;Azg#Iw0ajz0&;XR;~!a0B~V0_<?bkKdF-auJxwuN*HG-%Ix`+9dva1%75|wH-M)a
z=M>>Gc1t)!lcgt0&^ZNv@cnNf3-EPy`?_;O8d9Yrn6WCLu)=4@fq1|p=X&Dcr~PR;
zYUF|#6666l#`LOhPN=9a%MkF*GtWGWgc;O^DVk8(%~#%5hiqf>-xh<A_i_XGzab9f
z0mX=`9s~#1^n5$VUq;S3*pN8mSrVmCx~Ylfq*;IH?g)8`7hmvY4gY!&CRpR0dYI^W
z2J`J%0}-`gC8UF46;>aBn}M{4y;r~WeRhEi(AzZR-$GBm=a0gKaA*b33%RWtydT2a
z@~@?57h%(YTX#ax$`6pw*twr>?02^o_;@pP8)!Sw*C!zIL(Q0B8Cu|x#8H|66PoF_
z=stusf2pqDWd3#Ae`@=-ZKr_@!t5b|GC2lU&7mCj0)<-&;CoW>T5q8aeHL;$xj8_F
zvq=(LFqlEiC60c$#9k{MPw2TRRAm$>$L1<Qb4>yGCfgI65uQY(ybxDFxd|jDmL5v0
z7xsK#e!%UUk{ei^IVz`ZB7o;%r=xJ!SP%3kdMRZ}W&|_zVE;x-Lx~NbSTHnS4!X_&
z3kyKyw!1qO%EM06tIL&Bct$34pd?|9==Jm@@ttqV7X(q;^qhD|O%b;ANBPTG$TmG|
zmcj=i)piYX>++P6vJm^Lw$07*4ztNTFnGvNQjv0$4CyZ&8Hj%3K#<65OByC3Ht}{Y
z1(}Tx*hELplVILWW))_NX3dH)R+XRDfqj<`s~bUoVWQh^E)y{(c`XE<Hv)^POWiF-
z_IkbKn8#is3u9OmfTUg_?tH@tCUCE3cx2qt<sH{jA;G`EJSg8&&-FMNYzz-v89fbs
zm2^GmE$TLM6;QY<gVA#`#IW+{8VhhsWPvmLNqHtrSLo%-V_^=WX8U5)6IilX2HA7K
z({TR{iXKRNmLIyFt+{?gla>r4vjtM7ui6E3*KiAfp*4&1aN1+`$k)a|Qpb74Ub^+^
zEJW_H)@g}|uXBK)QAq-tYBG=^I%LSE;YP@1<6@{+$dQ(-J)-Rfx!~mjAqH9g`tO%i
zsLRL=oNFL(ANob|sMO>VXC|zXd$J?NhN2p0eFZb=|LJv7{=8(%v_7E*4ABSRwejB~
zr&2o^1?@yp&0<r@LEomqlRbgvXK0#MkGyTrDl87gC`*^_iO%hWqQu?#6qU^wk!<b1
zW~pyPrUwMH00D|}W(_Z=MAN(w7lKI97x2_GhB-kD8t{x~piQjth^5Gdq4%!JxI-U3
z!jZk;BS=+n=^Ur{X(M}jydwO|ad!6}10FGA{Ai_pydxuic@V>P@Fcix8S2uPkom_0
zD=DNiL|H*tgrUlqYwRq*I^aMt{i7gkZM;~=BN~vyp!+vHC87W_-yTyS>E%-#jwh>6
zoehw9ae@o6`QH5m*To%vtHxrCx6rsN?0`IsO>YQkRQ`&~$M#=_iN!~rgZjC1Y10Ie
z<TYK<QvW67e>vmi%X;^vN6F;z)19C}ptGzmpKZ!z4RGGWYo{jLAdv_c_u;U5vQSt^
zQXn8b&5S|NVFB$m?DmsGjSsG1pfB1kt@E=hAlGn<mg*QY5p8TcAlX~zn1)$%tdY3O
z>RO!&LBb~i^3h(!w!&AHHU_z!(@u!%0~7=_C7~Yzh5J7j!dO*%PPCjmr?iJ<PVhLV
z@4he}1Kvf+70*%4s|R-iGN=RIGOX9mv%_AQRVe}M<T4lfu9(6Pbq~!*iJ!m4Iu;M8
z0ZbI&fPdqsbGASB@~o3sL;<omMr?gy-e^yh`BW#tts4Wpel*-NZ$OUr2F%93Dz&G2
z`wDECW?7ky>>7b_uDJ>oO(7PGmXKq0BpwPFdcNkATL;oACMmoi#U%56E$lCFSgCOs
z@h!M!Th0HJ8OJ65TQ>3HFNyLYKuF%O@qqP=3NM{IXAjRI@EK~SB#l}6pHcjHUf%uT
ztZ={=S*`~P^5khgGy_97X8bu^^Q1ie+9ny!stA;Tuy1XW^|P*ZjD6R&4YwS1^Bar(
zK>lNWOK$x!q<;8sHrZa5I_IXBHQHh_YWp;&Th$M!L|X~BX7rip%iT2H;CZb>V8FP1
zv8)n)^9ob*jNWutaTqFX5_2W_^aT1CXT_nMp-N_VcBvKc>-0=7U<75Cn6`3Q;_|+d
z1n4I?hde017f+uACuZT<C_6vAxRs8t1`12leM-|{Yz{LFV7-T?8ygln@j5J7y+47H
z9l?tx{h~M3Ybp?nQT;RvJnGn}B8EK2Op(vw!xo<gH%U-PxqHECv_;_kHRB@5dcEXl
z^8>rB;K5~QZ9zuF8eklaqs1B*f>J%#6Lc&djU_#~F1-_q4dsZ=$Jd)frU+j~$@Ey}
zR>J>(Z>3G({Q79a-|SX$dc>-m`e3JH0xuaS7|j=^?d2m*Rs~S^jDav|_2u<UxM#ip
zx-^iud5k>W2q46jwQRy7JPch{OLNSBn;}=VmoYNlM^xnb?M?LOx^{Jt{<())VToOB
zzET9)OIJYG-xgcSq%Kj~F7x66lKXR7Qu+7nGZr`tzMf({k)6(nt-s><5c%Cw@5yU8
zno6z}+glS>Q`=}D70l<5=RSONq64Hb`X0~6$ILek*Rl-x9x4<)5&kgvK?9=QKEt5?
zL82mTGuSabI>(x^M1R4Jm0hCVR7T?vu4?r@ccr(>`?_!V!XX?}YTj7%!j$F(8EwrB
z!%BtKdX~Y)Ny#0$tysVp+_O2IkLD|<WaUnGp>P0sM0W%9cdY=~vJWVzCmL0yb8(Mo
zr`Os4Z>FskEO^NUwtc&OIDB3+-v$tYcb=7-s4Mt(=!=+Thdq;i6=9AKw#bPVm8W5h
z+C)p4ows)F3G9w*()oHaaC}rcM<!tqy7SF3zDoOzOD*oi6BX5(GiA29x*wTvUGbUQ
z$D1MRP3cn_?69=Y6TD{^>l1&vH^fh9vU=BlCXuNiusS*a{?q5WP?UkX=Yx0EE^z1(
z0w$j)UsH6|x|>9>L>?#1vf#|2+39Ux{cVsIj0<ZAz;j%IEnoFIFLi;JP&gY=8_ME}
zx6y(-?U^M7Ir3+A7lK5K#GH_oFYLP(`e`-e#j4wIX3Q&yu9}Y^`iS)^xIu5~Y6#dR
z03hOH#iK`5LtZ=wTOwe!C2?sKfkb@VeN=ueqO(GXi&kT6p0Z{f#<Pz_@qK(1VA|q0
zw5a&yatuz+;iYw0DIhnNBcLquRq?BDTphHaq%M@FHRJYB6h(ypfCYG6R6NunXS)>(
z$&fT!^;{*#syxLl$NUCR%v>H0{(6wUaS{f{9q45%51F^oihBuN4M14TdlmQpjXW=k
zVE4$q1E63<R}|pMC>XQ8&D(8|$hf^Co#2<M>tJ*E*p!B;vD8sTXX4r}lT$~{Wa-T=
zr?!!UYNUStuwDVh^9&?mr}Jvx-9qJV4AL$_<TJTN=377xi4__9{q;l}s$=<RV|UW4
zrh<@3eqC#aJWsYtlQ1>j=p^kBG`$o@gpKjusF4-C+PpU9{1{=pm8BztKa}?r-bUVS
z`YP_w#&iOxdX0fJs-#M7ik8=By1wxzA_)<lWi9X#d8x<u2>mK*<?{}GCn+A%nj47|
zN*<8#-3?fAZr_lhLV6V5LvNb$NFqT&cVl?K3#P*uIZxqdI_BPQvW~a@Se~iWOFe}#
zx3k8YPyU_u7&O(yYW;}Om6s@(cM<MYHxPnvME&vFVQ6bBeyPlX!>zSq=$LPINZK1`
zq%^_=KYDf^p~%g38gnzpJeVq_=_m+xx89g40u-l3UMg!#Ac<zEc4Nn8@}tG3des%i
z+<D}s+tF@cO?l=CEDblst)kH5lBW`qrTja!=sK)TlBe=GvMLP^feg{0(;Xq7-SywT
z!*aV})6&0<HnnO^%nYzb`iF>cQg&1<NJN~btPPlm<#r%kf(TI2Yb?~o+pwrlk-;{&
zLlJwo7Z+EcQ8RyZH=>#8lm!E3<fZxhWWG}zF8jCad88dP2KwU}=xK-7r-%OM3m0|I
z;*u19Mo>}|$$G^MXaG44$WveOL0$BDe8&YEbTI~u-2_FJ#w5mMa64#>6dA2K^9u}n
zKkQ}(#I=9cgJ1nA3wsABL)^Fl&H<Po4ZB)0XzO7KnAB7Uk^2L%r<EH)wf7&VE5wkd
z9eGY=Z4ec5Xk8g`BXOu$Wor7K0n(XdYILI}T9stOjVkV`j6yxj1~dXn)1C6FgwF?D
z5loy8x%E_0`w1@CN5ck-N^DB~^fstiXLN#7A%hf*7i2#+Rj<IwNmaT%M;ZZOt6R6|
z>$OE>7`Zv>lbBt(8v0eC2da>S627l+Gj-V}1}R`8%)B!0COzA##pq5>d#^F@GUw;G
zq=Br1B7z3AO)|t-KR%zhvOklcU9Yf_Oinsf{UrL;JeOpM8dp(tHaP3!k^=iNmeDY1
zej(r{t-eq)9p@~08v4|o^)$eKXJuX#?l}|}wicz%N8Q|wZwyq8M04^qP6MB=_1zTu
zs-kjV+0qQxk!{+Z5R`BT#nB#6D#6c+hK}EL^}QM=j6b#obXCugx(-os+nNNcM*v{p
zvp~$rh2a>?r<iZTN%d1Wx<+?S4<LuU)!}zowX*UFCY}QKQ?_Ab`uUd9&|#U)RUV6M
z)3NVr;Pf`Kcw}PFu~}ly8*x&9p)Osgadzyop9sCEb}4Q<sLC$=#+41}%Ai!faly8V
z^ry-bAy?63?5un{K(o3KMX>h&_NWa67f?^>xq7~ZA6!^QT$HuH<>x*GYUki522r$n
z@#Yf#2~h`5zS$FkYxn_qJ~*;ZjKvb?_}P#jQ~T+V)CG~QP}qK>kG4pXjV!*NXJFGu
z*PCs{BC7@S$D!>1EHAhPYas6E5uWu+-u<GN6=O8@isSo5AV5yiyN|0>Zs_=T)(Na5
zv}UN@gesL#CO2X2AfXuw=c)_Mly=YyUa(2Gm6Q8stKf{U)vxnM6hanPOu5gwg_wkE
z0tlWw!m`1vMmHpKi`F|3@pwrA7{kcLrT<qFH!#^bIkx0RoyVRZ;QNX)``aj_kui_*
zWOxAuY~?amo5U0|6DmjfqD7!XtVJ8z^k(f|<HCROYo7f#%}9|sD%kl%V&9_i17rpH
zEqsjDzlwDWX!4M|t2|kSf`<-4w@ikztE?c|5!AbBrr2%sFr;^u%09+d@rKFHtmsYc
zZtmtKARl#~@{;ch#N_^WDstz64P}=?H28#Vpe0b`c)^&`Q5KR^YFlVlYrHod*3DM@
zVN1S<i7_%Pa_30jVIdU1aakABQA^m0A?oEl1EO!y+7hSZ*}lef6BFbNX1->X$K-5z
zpbU7}_`hBb#E4{xp>Ud%z;)7V$iUtWub;ARMf5JB`E*0m7oas^-FelRF#fBRcGEr0
z{;KtKznlg^`6)8FNy+kbwuwchiK}xKhO*-<OjV_RApAUHaO35j1o@Xl%AZScuJI!*
zJj=(ySv_>^?_>0&yPDd8{~F6umAMA&8x5aD2&kltm)Ugp(xQEpeaUDQ^W108G+#R>
zgEe+l=_O<(gil=^{J4j|%sx-CoKkZNZ=p_tIiV7Ce^0m2E)c>i6@#^NdyjqZM6hNR
z#g0eGBlBW}zNy~~Ds#g1WIEm-m9Hn_Y5jgave{ywur~LwHgb4o+2&!RcJk6q$nHXE
zt=<4S)@iD#eO!&JL`q;pvOzXM5THoTxDvD;A52kFN)#epidJ{Lg1<j%!er%4UNA>O
zYSI*hV&d5ATd=6a<8xf)4ZW;}BEWyMM#G|OzDYk7*9UvBcngl*M-?m`@y(idc1~}1
zl@XO{BQ!M}RanxGqTcnSF-XVU=E_QnencHCOi*w#d>KX-0+2D%qh%Ev#^j@rpj5^C
zkrfrgag>R7FoA8X)t8HvKB327P%5_aa*cNBV!+0rw8cE>k0<c>vAibsl?jwQQdQ{l
zz_gxMxYD9@s6+B#z9jsne0ILgy@M^Nx)n%2_oh53DW@?ut0>5ATH3L^lZ<*>zlVR{
zFA(f2)Who`lCD{s@6XcPTbTtTXL%X#Bb8Ybl8IBL2%I|<+sL_Ipa}qcBj-f<2AGKq
zCEoq@S8uK!?oV1laE^I3rg;4$=QPbEdhhj3v??5^nL$$CQKJtZxarUX4E3R_9<?@0
z%iZf}+CHX=t|uoLN03x#%-+#^2^FX?#)rIl3x|vwPsnJFtlU}j(AqFo!I+W1y1cv}
zv6{296coEM&4zWWTBNTMix)3p6Il+aq9=5+g}wMsqt=ULK4g2)_*a1IAkxhwd-eG~
zC9n@w<2FLt=)S)U#C-R}W|SqqEPb5DQCzHE8)#ui9mh1mV7J3lVdXL_UVVj=CbGhT
z>xx_YmUvU?ALJuGPe0N5Z70b3k1>LaoTFOWQ?m?LykI03H>YYcofwg*{TFW6fOY0|
zSSON(@h?=Mym7b{WWm;WTG}tT;A}<_GSew;+cBr~9{guQMBF=PMqD|xid<IedZ%nt
zr=}0bn4og_SfxIEz{d_>J)3KIP1|G(7=%_@xKUzX3xJOk#%2BGSyhoZ=6T{7X1j&s
zPw}Gh6$;ye(guBv+W^zgFU>M=vhtZznynLYQ^}j%ogR);0RQYj@AlJW|EtbdV)bOL
zoUM9u1YQ!(A_<DaR@<3Jr&7XI@p-))mUjTmqY=P>RQ7!)OQ3Xp3+~@+FD=<kl&>Zb
zq=d(>46Oz#il*2HlFwoCvrkpebCW}wN6**EJ-$a2LdA!4ARG<VNPbvrdz<%|sAx~`
zpA+%@aDw%J#gtj8-+iPZzTnjTqyLjPcLeNTbovQ|-_Hocg>xWOUxJRz%s;tgvk9mK
z6{8v-E02QZx8uWnMTl3La7rdFzPr<oOGp!12w^?Jn4z-PU{jAF&Lcg-{fNdDaYO2R
zC%c;@LY|j4AGX_-sm<tZ>;i-G>sT_)8y>o`u&YN>66tJu<-+(KvM*|WU*JcY*oIR#
zlN=Ku+(B6yuEMBLe;f;a(>I`^P-ihIlZf*Mef|-aJU(z*WGr2)A>ushGiNL6R*?sT
z*SKC4ITBmumJR|gof{p$Ik_^?2LBq}W$Bm&8P7Q^AZ(FAMahE};@&B%MYNfUVLL&J
z&BW@LLkhRZ&4VXex0=&UHVgN2B~>~TT&c$lP<E5~`U{YGn;#T}=))(gb$Pfv9W!3H
z@ndBtX2z*T7u%Qtd~ja5450)dhcB%|vy~@d|J~WLh;{=IuKk@;PpRPiP(f4oUkXD4
zC!286M-X&Hm!A>00r4{5B1I8e-J$)NqIAymph6FDDiu3Y#XQz;gr#dl3*fC}I^AQs
za`Mgsn1^l<qPT2Abjc~Qs<s>U!NrRi-N9eq471YWrDJ|}roVp3$0x>n{W0o$0SHuX
z@e>9WWGSlM<=g+TRW+4hVdaF%eWi2{k*h6M=Mz~Eae-b1_*okI4fL90$Q7u}M<ul=
zifv+JyJv$~9n-_Eq3i`%%#snXB(6E@TDSWCas8S_=r--0?Nb#5Oq*9*wEK5r`w+ez
zayD9+TD?2|ReVA-LCpV(dna`7h|j9J%~}=&Y5k)-t=;_aJ2Ai4wl!M{SN8q=>P+(x
zw}!aTgi3}S`_V&Qh>6cWzi?lyD<<%@_L2JVYk~V8WY9$V0IFikk}VKQ6)UG?N$o;_
zT$KwNRR4|=5IiUtdn>ImJ;cjUW=f4oyEKZ<lZ*Rm?kgOIv)|If8*C0d7)S2Df1GjA
zM64aD5LevWszv_v*a)vcnaN-k5Rx+sN;29A<;rT!jEgSh5>DLZfvK?i8TzbhGGZog
zFL^k$Q&UdfZvr||(7hZM*EiSv+|oAofhcf>yrmry6aOAeVe_7!D=H#dqBO`|5w88k
z?+W8>W4%$egf7}w&h7&}^i9O8>+Y8z0~hJvK4LlDhjxxFxOz-pp`YqYS9RZ!@`E`<
z{o;b~Iw(9qD<V64%24{ii17cv<HT<!%%T;YpJP@z>3rp<0T#g*rw<QG`*5>DU7*u8
zPnwlVEbaU~(tZ8t3xb}S?<zz$Dz7%hWHl4wY|0C_AePJw(L+7nh$1!`vtswVn>oPA
z(`!?Ex1G5~B&yD&^UE6`y+%bi70$w&d$y~_`f#X&ul~(`L^SdQW2o_QAA`DCv`7S$
z>pnq%nR_c|sE=>Ph#n{-XN)~-i&v#tp>kys3?$1`qKa7+JYz*E-oBzfqoAaj>d;rp
zX6HPDZi2R6xz_J41D$|!W3+Ll+RgJ3jG;<H=-;LRf+Nt;R)cv~kzku4{u61PsO^iv
zz5gYa*4Z6qwc(W}(6(N++33<(-u%%)f;{wehq#$4?3bY?eL+&yscR}<+#?c$EQ_0R
z`PQOf_f8RIvPy_3pZemRg^5Ut3}?q&2uj{>1>wzf*F6_3WJ{&Ec{#MH&9vBGA&a!E
ztVz=unzvD={zWbLMl(sEKK{qws?5?X!#yV_P+2M;_b$&*77YTG)?4x#%0@v(qp04#
zAbXVwy{5G8@Y>yNQHlM&)_LShHNw}eSTkki(={btFVOmBJTclv<g_uqosK->gP74i
z$MbGdzUr1Di#^E8siP)zo)pvW3Ae%Lp=_<z*@<n53-D~^Z_#`+(}j~kXohx9@QLe@
zHEQN_0EO}P8+rBtyq}P86P=$kR9Hi;w1d9bL<pKWQQ&BbK)necWwp9PD#G%YN&e&9
z>7JR1CM%u6b!q$7zcPmfJwrG7CQ<<4kO_>k4}NP?2U9}Ss;@}5ohUL5xTR~t&5ySq
z`NmP&u*3_+ACQH4x<wxG<5f2PkLf<GbZ?zeOWX?1pz<>C@P}FoVa}AD*aE$!>WGOG
zl*@LPX*LUqS;TouJX(Hv*EYbe6x-SP2-|}u#ulQXeTrt?B()Kj=SE#W@_#wX1Q{P(
z5j7BKRWF!VhJ432K6B6zgh2B;?M}(K9P+CR!~jkkMhKz-@vymRcQ1wu1w=xw;wbIV
zDEF7QRcj8(`Q(3W((q$N%uQ!2P?qE~(xbT2)7>P2ZY2pqt9I5$dC6wQQ@gxpC0&@}
zlBGzS?2hh(B2j$<g%s?#aN9How@TkW_hN-XxcHA~!$Ji4YfQL~TY^iVHYoB>2_xxX
z$7SzDoAH06*?uDds9q7{ooM|WF#7cB1%RTy@{P8l)64d|7yi0ExrcKvVD-l#cbI8?
zDZ*IQ(|_1?gUroLiBN$(+rNWZ^%Cgu92vq#pC69#czg{Sv-;xj0Dw!etVvrUIo?3E
zM@td<y4V2T5bkIO1s#s=J{jqu|8d>QE51L7BC@!<1ws*rhSQyt!l?aR3Tm1?kgW#K
zTU!x1`bhubveOCF#3{jd7T?~F1U@LMW?X^gkNTj2F2?!rM?oE6<lRi0%luoRF4A3X
z(gBdGdl;f-r;*Q0dkmlh(f9*d3I5@joDm9iGgoRnJjsSE9#&Uh<rDKhc(fKlCdpxN
zS}e4}aqm>rt4gca$3?FjiQk8PXBcyZ?VIkWuYjpL>%icM3f!5Y;p#`*Eh>@z4n$~~
zt&*S}sL#ZZznQR~ki@kd-j_Bl&r6<@GvUIJjJo)rT8$!PZEROAgtGECQK!qGlA1wt
zmySC-QU-?1e>>$CB9ibQcN<Dc4MF{wxJHpTck$-^1^XRfzptP)E*ML%b8^<RcFTp7
zSC*^UU1@hR0cf6%u8XP^b^ae_yE7>~`erAI6kH}D{9jGRaX!y{^rk#t`^0Fw{Zq1T
zpa{KT4{+6pL{dpyV&#ONEi6_c-6QtMBG9afBEQDjtI^r}&*lvgVh;$%@R-0MqDBa+
zdcwkM=rG8Jz=%F;;$vYyS;|Qj->A<&$eSs974LQo9MqxHn`DR36_wu_HUyYf#^Wue
z_^=VMlA+m#bo*{Mv)Q^43ZX<SRA3>7?y-UNRj&qi9HJ*~*%)T&4t7Cvp(q>#Hf72b
zD)TaH&gNx)jpVtHoQZ4t?|gdLE>%a9C!SW|$~1TSh;e>_SrOErc0I%u%e!F23>VH(
z5IC-r^p8p^Ig9AyFj-EIuy5_fg_EVDp{m|NO);A7qw)(x<R^O{C#c24I7<?8Pa^_)
ztmB*Au**;d5{Xn@1FYCzl0p7Qzhz?Sr9{?mP@A$L?R&TY<ZdW(4ONH~quQ4djj6O0
z;3rfs&E>=b((K?ePw@(`<Q!KDXk@|7-h#BK`g}e8v*0AP?YVp0)P|uR8vTm)Q{OON
zBp}{;BKxOCrJx#dwD5e4+T+==Vk>W&cCbkr_-m`qp#qpd){_>zTME6ZuBT20ML>z9
z)5XtUl*~hp->-B~sr{8iLoCFgQ6ut9D^IY{fa2rQU@SHahTJO+lh!yD%N{NPvjXaX
z5{1E{aoUmsn{>0c(3Y{IZBduvc~bh%VJ31o2fXA~!e<qJ7MD8b?Q*~z?qH$#AD>hf
z1IV5yPQgIJm#7kq8&NY;BlA)<D6xXnLoN=4j^L)m%N{uxqCi_JldZ2nJ@MR=+tSj&
z!z`c=iP}^b)_RMnP%l0{W+JFR^Y}~=On{-FPbPih;Vpjw`1jm-&e7^&1*ZIin(Td4
zBk0$RI&^7A9F#7at#@~Tq~}Pe5Lw1yV^&h_M={56a5L|=?i(k~@D5lke}@d=sKWPl
zA0I6$$k(iA731`AU92xPLTH4g@vK2zwPq>6nTr<(+g}L-$|flL(nZzlFh~S$7#89>
zV<3<+LbL+gKg0N>49Pb!rVy*_Ei3vxh<>Cb^~SsGhx;A^n}&*hI?^ijC2Vo`Cn5Ox
F9E~?skT3uM

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..0493d997bb83ce5f5536f55d733f9f1993227b5c
GIT binary patch
literal 108208
zcmV(jK=!|j6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC9J9fNj3)!R|;7yfw
zLqk&-lu;{*ZHl;*3YAik2zs%@U$^OlC4qlC@MV3W%|5OocW387bF63hb)F@D_yY@_
zd!bsGU&8@yq5dpC58axcwE8*OJ^<$4&a@e~)B{-s#P)srRe-%iW?K{6)7|a8U2ex#
z%N4^eVE`X{t(y&n>flUE)Gl_!+q^0m@&&-)eiLt>$3MI_VS26S?!*-$vEXLpL<ZKH
zOjbgw)Yd21tH`x<pA3ms7xhDHl)GD-8%nG7vFHfgIH!W2&D;sUML7F<O>3fcMfN2I
zC;9h@w*@d%3=<zpwVigjj3Fn_a0Hs-<CN&EwQEaON(SKSp+dq(2+(R!?o3C$YmAez
zm~4P16t2*mZWa_w@QTB8`>?+@YYqEgtE`xV@W}>)3z@*&0JJ&e5nnl;WdqGB>slT#
z1x!)c4`>g<<`|g>fgiu+`V^n{j=XQxHukvwG`<U)22>0UgiFpX+I#Z>+F>IP*EwrY
z8(@C&#(h`X^Mj4&1%lKIRoG^EVs67v$XQ%u4c_QIE}a1w_%Lwicg)qV=)&{JX!VWw
z09jnSbldw<jGqG(2dt2%oIi&|-ge+CqUODL6CdJmhvoAO=GVd5Z}<5%$S28<7SqOy
zOwwuuQ?Y&0xI=PTlGEjE_u6LD<fV0uE`&!ahS=`Yqbc_Hyc{(beb4t}42m%D`)%x5
zH7Ii+If~yRyTgC5`&QR7@&7fVM%_YO+X((?(<rB<1Us)XpRayimL<e7MnbHJ4)tV2
zmp@Jy_kWvbDAc!*n#koUqXy%Hl^!lgfAnaeCMbgwzmE~mCr>bBvm>0J;@Fenv`-)*
z-($BYMBJSi=-Bo@ww$41*3z+xOTU!t2M*EU<XIC%6UGL*j;*DPVpc_HBud*=?wMgX
z*2Dxa#|*<CvQnRp&w9MJ{XXGU?F9oF=eL>90V(w8Dw_$jyjt`CZmmqA!OTegY)$h+
zE4r>=Z7aY8Iiu`tT)p;~mQPVwyqG(Sv-vGZ(EN1u^Y9K63x-Xg;5NQG;vu}1z`Al7
zfowhN<lPxS>sIIu>E0-LjXE%y(}V>`5JGqVrTp7u#R-pnp-;iE`b<fT09anq!_nm(
ze-6*jl@vAk4;)`ES`)B7p^Bwo(sP(I)-hw6vK0f~2tuVWpy0=9Q`NzAqLg0dbLB7o
zkV@q>ic$>{eAAHd|L3_K&x9rbngywxqPmsH{84(tlv(&qpcznSV^H%{dws#0@pWN`
zT3-%IPfn1E-;#E&ZCBY$w$G$(M|KLgJMkOz8*N*b`bk~LqB1nv!;|lBHhcie+2e=)
z@%IF+!RlYI8?^Ff<r|usI}zCH<lr?!0a9eXf>{LkROkF*z>8y_Z|N+$yt;4w6fXcl
z8`y)H@KiZW%$?Wds%5{h2#u8K9Ur3oL3tZM1=mf8y$SjB-wx>v;4M!Ab#8KaI5rhX
zQYM-X1eOKrNHp|T-I22ftb$b5<aQ5bx5VQQu_@@RqXkE*8lGCqURl$=nH$pQ_1y@s
z?Z(M!*#6r}(K=2l0m+L8+G1Ma0KWI|EHie-bkgXM1?|^HW$YVIY~D-Fy9fXT^R;a-
z2NN~^Kb0T2`-_%U-U6+kEitdHx{3WPnBlC`VL-@?LHYxEWH$L<BnL#G+&*3>g=4HE
zr|5lfC9E<oc)GklF}EP6i#2fQ8*W#X@){6Vv<QerF``U>V8_97Mo=X-@<}xd##qUB
z<7UWm&*PLmq!)hl=&XII>Ihbfb6k)7pf1xkUx#tl2KkR^ceBU?DNlGjZ2fRs{nmly
zAD2NSLSl-Gu1EDwz*VwC$J6KnC_nlZnqUURHH4qj<#bL@(U?`#bxJCgjN)&AcnBcs
z_H17-$=?LbAjgtF@7`FHFnIs$bC4|X%jfAP-^7m4BU|;8))%a}pl!`>2tts}9tTJN
z=xm8Tsi`-Sb+jk_k*eazK=AN?%C{G=?^5ncITeQD$OLoc?sMS$4f8Tm7e?ODMu$53
z|8+ceS%<^M*wEc}ZkRdTn2ueUaub<YTOy{kk4}2fy)z5?i8wNI_aB`(fp%Wi=Kni4
z=i*PfZ2!tM(%+S#d0a~=-ib{=P9f|V(0!}9AxBDdi81}==tGs;<sZp5S)S5+YYx3u
zV#WnhL1KaH1+z0~GfxKwn$3}T8O3Z0QvHGf29roecvvG_Bo(d}^y}(>PH_Ns6f`8f
zm8qzAB~^+BZ0Ij%jbc`vhsaBhl(IrD?g{wBLwvJc4;sPY#B|zf#Yu~tQ3`<X2*G~D
zvtQDqDehl_tk6x_y=BbnWpfcZ(5p|8^eBFvn}h{<h4uP*I+XB=lq~;ORbOz=t6qTM
zRHQJu#eel=eLlWc_cj)qtK!Jh4@{0|h#>^39alDkF?}pL{oW>uYjSpCXV@?*^kW~M
z$1^ds=-*3+)4g^t6CbX4c0G`O@z=<U>H<Ye$~f(5P~0!p)Ea!lm3!=eW%L2cG)hrt
z3|g?YaB#jCOVl0&<bwsiE|%eJ%Sqbd+!AI>RX~DnHO02%qw<@~YGNA<YZJt0@Zk7I
zhLX^iF}K+LPTGox;8+9`A@PBZITW<aKksA;$6l`d6@Bp(Al>0|t8?t>KR?mouLyl;
z7VzfuY?G|<V`HMx1S7_?ze`yP)yHTTRW?sop-&-v_A)XX&P?ayq++SEWtsqz*^8x@
z8^UNRuHa0K+>~|J4>?jE#^|_p9qym11`=ZTr9pR(hw8=1fd&>x28phm|KyNF!Jx`F
zts%TWkGX%N#>ehWM#Q8<rkA)+l6XT7v($i~^BGelO%tV|@dk-yh#-_BVgCm)akh~)
zKKR?gSaQvhsi|1Fp-j3H7>*wq#E06^hS=<YvzVsedG(Z{&7#=?e4Ts+5E*4}sHlxF
z8A8*v9Bdtl@>l4`Pxw_vGGoj0^h&xII0j+S^6Wk}j`@`G=ydrSrUY_R1@^me5btT;
zAK6}QL#MQm7u&tXo`Ey4SwlUDGaV6@i{0BY(>3rs*(vT#(Y-VPdSwFj*Ae>qWqEVz
z1R_1xqvzn;L=tRTPQOj-@g9RE^>sw}+cA{-krE5(mX`<YqIq%1_S$hA`}Io+Jt)1B
zFIFJD2sF|!{)2C5;}$q$O|MmJu<V~W^T$J#IAv*}dMirCgDq)25nrtz-SXH}BI4nZ
zMf5)&(@0eXxp&%BuWW5}o4L*PxjqW<E87c0MFb<l;ZrlQtO!*A2I@rReT6P0L8J_w
z^@Dvk6uao%<-fJ_xXLS`uxP`P?AKOd6ugtc#6#{YC~uTFa%;xS6QEsb%wL@w$9hRg
zAt2t20@A@Jf}R?UUE!E82thjGizWs^x5hxNAqI9(WO{NY+wjj5jl$a~RqfdO4W0sy
z-pH%$)BGb5kz>7b9>2O4a?ujswnP2n-2@rd%MSfl3YyC+0K81FLt^hsMD+k584?TJ
z<?2k}wBpC#+3ZcAdLP{gh&^`AK(!+VUhkd%3-s~wzA<D@$j2#i=QXqs6C*8G$fqx<
zq;GVZ`X5R4;+}=cq1;C-T;mG8OVu%zOxS<3<zhnoY!S;<m>)7luG#;S=5OZ=gEb>t
zz84E`uJkFE&{WV41}W9XhABH1&ToC1VbKft+-vG`IS(C0YZulO>CX04?zyEo^yE!N
zwwQL5@BS0r9?(eM-zm4!hPhoyo*H9_&$9z(R=el*Y;b~ju~S*5gbk9RNkeRPbi#m<
z!ur|=rSPznS$k!lUt(VZ$L4|;&W%Jo;_1lBzN^Hz4cXn!t>JM?_hnmQHal{Kj9YW;
zwx90)Q;D3oN$Y)kD9uJi0QS8f_*gT<>*9V=Dz#yrK|=K*5P3#Ady8Kn#0X+O|0MRG
zYavh(7Y_y<X5kLW6X@F9j?E|$lqvh##YiO42g?Con3a}W#jL_&5HXgQlJXfV&(hpz
z!Z1QKw&b^Vx8*c3)4vCBl=^n&fg~Ff9YWrgD7kNs24mV%^_LHn3<<et^=g@)2Y>Ku
zA`Eq;_7_m2-bF{xgSlpR-&O$28*phiP#en>qouBd2>1!VxCEJ(n8U3A6eF{9lpYuI
zx@p4S-fp7lya<BVSH$IVv$UIL<6xFwGv|I}3)Mq8UWVtIv|-)p&zUG_YXwuRi@T);
z)DWJ0&(#fSESkLzFI$v9I*@zcVOuLHSyaO<=Offwhvb`1yn&Q{3>cseT9>M#+gxHC
zdoo}oyn63*-Dq!DiOoU5QC})<e9EzR`t!-V%ShaBLLEbd!xClKUoVp+zFpN3NO%$=
zgh)_#2wFM%H^#e?6wTP_Tz;(s;T&azl=y>YAKd@vdf)1Hxjav+aOV0Jbk3p3G6e*C
zz=9z-AFwQBXKQqeUu}66L5z0Kb`}xqX21IZk>!$&+w~YNDQOBlASTPdLsQr@v)j2`
z&;uXF?echh*9W+G3^OCp#opoimqEm=|7=#R5P-uRzO-j0x%~ZdAS?C*AH;sbci*|a
zA;?QUl`xpj^(0%tjyDB7@^=lK(rFTKlH7kjxc7lEkkC>NCqv78nCw1G1Bs*kHLM`v
zSq6Yx@60)qSGVh@;{+ymNKdgy9JW$0_8<XBxqQb4BF7eg3ffoOK@TYiZhuWkB?ANu
zWvL8yt-lttx@#uW`#36vL<Ob9_G<%~C9Rj~h_B0oKbdKkx29)L#E^N%Idoh>_iUl1
zYXLpUXWw08RyyB%{a?a!FG#*6g6GKW$^~w>A)(unyX%5KNu0dXAq4NC%d^}CAzWDZ
zLo1J0#>lQc!Fn2ro1lL_$S`g<R~cVoaz2!jbO2y$p}7mr?F#0=BJXC-q^3i2K988`
z2v=V;L_&omT661{lDvJybTm1T{j~Gg44ZE?62!I#elFS0wDyA8UgAMxLX{CH-tK*`
z1ei(GvGyoJ`Yq6k)LGKvi@_L+*xRhU0-KKJcUP#-!mJ{5oG!3R*^IAWeCL=*5g$ds
zw!-(mFpmn5unFlAg&|iPnef}EJandLI3@*-Bn$m3i%{;2pDqf)v1*Q_+|BA7Fsuaz
zulWt&e+C_zQ5`E%#iDk1z&y(Lllas;QjQh7YW+r;FL&9<LtGIDaZ$}|IhY%qq#IU<
z-Q1g+qp#@|>wh(`HZ$3!jj1TZCk<PR1~SY~>LO`nUyEzFi6$Ug<TIpX+EgO@n2l#r
zD_nR6#1OH|<L8gPXrMRlDDuofA*_36KZoXxHHTsIK(Pt%*uUSDKVQrHp!1^rcc#;R
z(+9hyY0f}HOKnd;5pa`_y{a=Cj}dKi_P3dQm=ihY^w|fKKuey52ou_DhsIO)Et3?T
zY>kdX4&9E-sC$<6uOHDA|9_XLV6w87_m;%}yaasv%oJS36F6)Vs9B&MgbhC}IKFlp
z&XLI~2^~b=G1Ws$KpYek9h`_DOD67Bse-U4OH$3_EoXUjUcj5r$qGX5V6se9nn2Ac
z_7=w6Yp@Y2dEUR=+<9Kgc4TPD+wZoJrbJ(a#KA9(Q>}YurxdyQczGek8nz%I9EX2y
zZ;v>!THd!2SOY1Ys6fDyRRhqob09(McXR=FDWO;vat&fJdz#7(49h9?_RyYi(_r-8
z?##?-c#bJ8mTyLSs&&BJ_Vk216uX%A83jy`SD}-laIif`ix7r!-dZ^>>qJs&ea?Ek
z7+gyL|2z_H?WnOSd<7QhsodB|Z!`1Y#;P=Mk63z7zVKH7&U0Q5@w^|8sjIQMmYmS=
zfrM~uzjA_x>ICf)*K32Xs4Eh!vtyk+1Md<cF`2NLtvE3X24?gY2FBgceH&_~ZT9Cv
zklf6?^rBO$z}?gD&6pmMTzc%PiyjMy>lPVz5A%hk{#9e%O|b3X^iFyfaKRF!7!$Yk
zM;00A@Q1!~<0@PLp)dgfR*)QuwT)RN|CI`XFIBNFpuZ}Qs71e~U?F?-(!(!A1~0=C
z?@L}QRyOFw`Pwk(1n2|p@mO7DvSas048vw76g?5#6Y2zpLNR-X_5C8u`SR*Fb?0k2
z+4lVoplBGw3H!^mYly*Fv`VP`SG&3CMtAujQVGE59^%LGms=NaT7*EhX(uP!6t&a`
zLfovQC|%H}+x)B{avJHrnfpGG`e9y&pw(NUhS3UU9+S&F1Z74z>$l;o5!8w@Z`*oY
zZ^IdW_?Y5+8NFx&`;lKJC8Wa+hC2dO`dD_CV2+CqwR0-weR-(5Md{iX8WdOdc?%BJ
znI^)nI$okR6DF1<4;%sg;jTFE8X*=3b2Cfk?r_EpeamcpUPx{XlSAi=;q%)z2FNVd
zM9Iy*n+6FwVeJEl;E6G<Co|Tz*CBsH<kxzol%&FiII&byw5UFzqC(M9B`T>QfT=J{
zKuK`G!t6_B0li)EKNv_`#H^z9%4BPM#~G>{xl92}KsADthl?{}(u8YUuKTL0toQu}
z_=;W3!PXY+a9cc*@|FkikrPCOU}HIkLsW}MF`$_E@4xsZUCKOEvJrUC)pWNBqTXir
zckUg{%iE{}7GXiegg~VeC+gnb46-ot(z^@<Rxo-YUli8-<TPHz1Pnc<y7K}j)G;3L
zc`;ESZMZ8Ouf*7}LnSJ^d_svhuK&wMs5+>S{PK21%BM@1;Se1*vd1Ti&K48~*v*Q5
za9Pf_AXHz7_ZojS)t*?_As7!~6NNv7$O0$t85xz^U)q)nds?{O^Aqbw0R(ech`-Mr
zYbx=Hkv3EOOd(+?hO?L#R0p|ZKTZhlN@T!9x+AL`sN4~(Jjk{|G@$}~gMf1u*=KmG
z=duCVqw)?a6xBm<7>gasoCN74Ntel1Ii|N^gy58lwm?yZ=cIDdezVTBSMS64cH^T+
zENvT7B+V2wtms6W?q-kesMH_8|5rIAtF(EiT|H}wu6@v03wwijCs`N15<k?;v9?-h
zck%!jwk%<>NcRZw@{Ub8i5J<<?17~DQ+c2)&L(We9mvVoVxtYiafAUCvMs~6q3JW<
zep!$#KV3dfT;sgo?E{3{))P!O)Xsu0W6DGP5|Eeg&J9-kxRNLRQzAWK9t?DjmmFt}
ze^C{uWu;@ORRoT78XAsMUz}!(uI@Uqc%JYA(5D&A`o87cYqmgOPsAh_BAzX!q&G<`
zSk$4%49AWhT4jBeiTR2g%ValI#sZXXzI_5f$wT@QS`+kjFLQdIfjE{Wr<wlIljYSY
zdP=&WtGjb<sSEfERG9RiNwK^)dp7e^ZY16(F3A7?kK5MqE7o`tLNELgT8&!VA<PvA
z5{*+(zrcPWb@&*t+YfQ%%r9H?$1C>mk*^dl9oK74q26=8Tjg_YW++PTlDaUNa7|;g
zF0#aALgExHf#i!KteTaFaxW``virT)QwH=*Y;082oMk{sS=0f}=HOT{>rL}YtqGo<
zR@sq&itkxDmhZ%Dr-jpoyx|yo`d(TrXp&ZLmrQaxXfTMk0U?DFH9z?!w$Rd>ESx68
zhi0|C2f)*Bf<RFsYp(ty%g-SE6S#AnW+qA%Lr5PQ6+u$IWPuIHOWsUOX}bPdpUWPM
zrvpGYosksWfOdLo_LOCTlUrHZhn|&!k@p6BWNhVvXr;GV%uh2E4XI+Z^Z#Tvg*eRR
zQy@<X*sMKdN}E92RIS5uq<@nvq;3v7#n+UMpMX6^DTF=87y?yDI9X7vpp)(wp-KV;
zIvEC;VoIX!VFg*PK@$@=?r9`#9o&$O&P?qEv;QUc=ul3B24XZ)SjDV5b3b`sxXTnF
zZm`2Am&yXZ@cf?Hzu_#38k<u}KDr(IlPaCEG&AbJJNJ~HpDF&3Fk|`#LrgF~*)X3n
zf+IZ*0S=23M2)Q%M<M8J;(WA@y`MzAw=Y56JLaz&<&gejgoca?p~(=E>@gnZ=?^HA
zlv8P>WEzDf!wOhE#W4xp&;J$7)L~d;E3%`ms`Ydm9;P)#P+~mk(Tfv)pXga|UXlF5
z&E8&y|E1ocvWpobatjK_;>l0fs8S50w1)k1oWU%TrmyQ;pwqmc_)|;QL{vHMW4K?*
zoqY3qAnYg?2wCPzVmRfc<oAHCwI*i%`TlLIR{w;UQ=ERws2hF5mZC+mIxFZ&hSk3;
zJUoe~9ULXg)~7suc0JFy7~j1_AT;uUv*=mQujrmLp1U3yhn#GUr>`}qB7gJ5Vn{lr
zQ&E&FDR85LK(5pmj4nTRYKTn&%=&u#9A?PAJM}x*Du(#ryr6Qk2o+bPQ!JR}Kd&xS
zgR~=N$h{0JZ#;r%-YgW&`YTGi!61v-6`Ht4=YH`^jee-%31A0<4<K~Q#}8Lsb->X#
zTojdeLOUe#9h#5M;avVI&CMA{C+bJD9>Qm+`<;4gKwK~Xb?m$<s;1X}oj-L6%s9_<
z=*?zm7pSYzLoFlKQ;PyEguGk&xO@w#Z=f6(OogyQm5=_Rfq1GC)ZtyOEH14fc<0hC
z*L%_5({Fnis5C*pJBh!~eK$?KWdd+|_Sl(s^2B8^P$9C?+>(U$k)$~6u3Bt5c>$Te
zY3Y(7TC?HG{Y@3@f7IF_0-~^N?u=XvbkAeAn4@N-sS|26ibK7E@@m*G&IQBRlp0%d
z^Co67jm!!I2uytT?R32vl%y6FiCf^%H|!_ee<VJ3zQ^P;_0ceDz-c^CxYt3*BNo`)
z_Qh~A`=Ch&=D6o5Ow3bQyyNme&P;;M1a*}+vSLPJ`@w{39_f_2nDOiTjmV)VLoe@m
zcW6ujP%(v8bMetKQfKGB1a-nS0&6RE|GSvvFRG_x2oy&JiE=b+pRTcnroxvS)7A)e
zqIDlR-oe2uL)@Y3m=(zx$c$$D(d=n2tw;jEtKI4(w?29o4kxmiwK{5<gyn^F6{CT|
z@I5I%;@#kU%`>$Y?vU+_=(jnVgO%Jxi=UW~<dP&Au#a$DFF7Lq_gYN2j8=IDxzp+S
znjcn<z?`s{gU}-RYdq@zdiQZ1qQUUKKk5580KKBSAg?&`3hoeDtLB9UjEMRfn7_^P
zeh(+L{8+)yRMF#Lr?>CSnKjZUqOYs)#(h(YYbqd5VLFt%Px&*in{qe{!D1BJ%@%_H
z5t7N2R!Seo{SyK)VqH<`M!M?6_MOtJo20A)E5f-vU0?fDRb%oJQ@#p!X|72+eGR=L
zZ2W2dWDKi|@#B>OYNb+cMv?@cRA+Qw!O9*rRk{HmuhlI^IqN4d_1TWuhznhJHGmWG
zPn!4{<1_Qg5T0PhZAy{Xfa*;1t|ZhCAQwZT3m=vAF?zTmu+|sJez<D=f7#5_?<JHz
z$?T+iN(IXKvXBXJn9N((R6b;{2f57sgedVuq2L2hMc)YVxV#zEL@Wm2EVvS5X?y4V
z!<30c6>Llunel<`M^H6Dwki@uo8ZmjBk#Yn(xyRxyX**QiFxN@a=)LhnQ8VjiW$^n
zemw@xlNla+P?ktxq(O)Rp|_U{;3h$wo7%4jC*9io$RX{{z=(75^RpGKNC?d4KnbP}
zYxn}$H{?!Vo0#Rx@+GIh#DAiWIE9m!E+9J@%ns~@2mlZ(ArV2Had5VC)3jH=^*Twd
z+{?up7d2xOWmA$hy++7J16?EV_dy&M=hrN*=x*yuGbtFIhp415*^%Bgx*v_SmKlsA
zwcf5F({LsfnPYL&cD>HLeTkS>PP8i%-+uW;@_gyI6<oxf&!Xn#_tkaA$)rcbPB8M1
zokg>|xw|u#9r<FEKJO}fKQwQ;$n}t8R}dVGrF-M68ma#-wz7m;pRr7j1v_2an=5`i
z$a`6l=HpG(4Phx^f*Hz~J+06)IuWBXTA)zsL%&_#d1NY<iKYQd6@*CNDz!t53OaWs
z(^yq+=(05E1Q;6uo*8u@Ut!o|Ez=yq%whHR0^*EjO^3=6G`Rp$KU+I;_QD~k+9&8g
z@r8z>#@z<Ud6C`joM<7+X-em|ph*pFxUpZslqUUJ6bu+Zhg76ej;$fr^oB0-f)sTQ
z3^s>rSJHRtd3RczVEnzSiX*=z@T^#ncYlZV_X#8*MBfJ+2C>VaeaakQ)N+tn&z9vM
zD+`;y)`pN~)3c@hQX3*boVE<^wdUlZc;M=!vaYVxX+$z=45ms8HlF+IrO+k-bGn0=
zj;Rc6v^3#pi`Mp9&z?=g86Uw#s>b{VTCGb<XJ#HzMj-D)SCSjwgr|1g_vd5DuRp_s
zs_#O;VaqQM_H9R3OQO2OqXZk#{=J4uHr`SOmR}^Jol#bm8ml}2jL_rvwHk0H|LRJS
zsPk&fCagiJspXXXioL;^(Mqor*AOo2z><;_xkZ>-AmB?s#Cx9Jr)I;vo<Ee|MS4Pg
z*F2t;^12hD^5U#Vd>Q1#%j^$|P0W8u)I8DAuKm85cAZ~~Ab_F(6>P%zOCt{`m!Tb|
zK&9>R8<~7K3=E#AJute(i8(83X&4FXv^VmWVNU@zkX3jeXiww?$j-U|`Q@J$E($u>
z=_DmosmQ_fiDjm}Sqcw9c3{4UyX`G<*g882<AYZr7u|`dg(t-^%2QS=9U6<HkisiZ
zOvTi_0xX7sap5YZtUBQH%q_ABZe?J4#Nt@ZX|%kNrVgiwcsTR$vaOSi^0gr3GzGbV
z)3zVOwo>qYg~KK-e?kO!zxhyMV7H;92P^JfW&MhU#w};G6xMD8osON8pXh2!BJ^r0
zF&K1hVRW88vbK@*k3Q?-?<?1gaW-f?A@0rpEF;NI(Gp~!`=?Z_swSOt!gYW<;ITfx
zQ2r8#uJdgx+%O*CKOB<K86`%ZY_r+!Hm!My1ry}t@F*gvjvPCgCFV)0a!Xp2&lkF=
zZ>ajDTDK6gX-L7ks0N~^?x5i*b{=k+1sWymVc-I-)AHU^dP7X}5FrCXZ4I!}-M6}}
zqoj8lMDYVHX~ve)M`Tl78sZVJulMel<oby}J^Y=qFwTnwqO(~wubOpwO<%2&JnH0|
z7u5_g%O8GyW3$p^*u8(NEqbX~1J7XgiD(xTd)9LVr^4HA19J{Tqm`hkZ%gw2T4tZ5
z-@8h^bXv^}(M9?1nv(9z&2teb*D$KHM+?tNET(HlU|%=VL>)E=p^ksC+l1E8hXhV3
zXZO8OOHHzm>K&|4kdZw&BeS@#mQmW;7z2UXPh6x7C|~}R=3?F^ko(7h-t#-?xH)8{
z=>daFwz{plwQ5V;B&KUnCEtBk=%{CHj?&Q!fW~U`ciU_|y?>)^lS0er{e;kXMF;%a
zxe+sJl2Z_L7^!%Op!52U4BU{i|MfdU>aJcQPj)#wc*ZN|NMVqAN`0L)E?@QMRIea>
zPw(+4BLp@co`A@V4;%9`LWR|h0Gk15sKjiofK)<R%1%nJI+vY;8^P70zumRXICMPk
z(S{X8uF^ZX14mLB+~Syz&U3N}D-zt-AxXZ~6@ViN?5@k%&J8OU-tGBtVpwV6)a_>}
z8@&&Q<i}4b&}3?)bdhkLAQ_#dOU!!n%Fv9cUPzet3iaGAb#Q)}80S0yiC1t{Uh&_U
zR?<S{z(_#V;TWy7X*Pw5z<!*7RxVTFWf8*<1qsL!@q4co8e?1lQ7=BZ2*Q+)*l1Zv
zrCuU=MeZ9v(fua8X=O8ru=)_sfrUJk*Z6hR#{l!cO05Z<MKn;0(IYFR;Joqcs_6<f
zS|y<ae#rDZ#^!CG;`g*^#@>u7#9SEQn@DZ+B!9~O8LD}qYngY7<(A*}s^^&dN`W#D
z{7Yt6ApQLTwGe9uB*su=ND$vv)sG=rnJUcEK5S%5Zccth5mp8(dTjo}xTD~g5WX@5
zVQx6WBBOU#Vi~I2G(H`4-_(-i54UeoXVs(n1BCJix=)1)X0O___^N5n4r+_gqO*f}
z*EyNKK8<O$jLeiI=`H)>5|RovK-;;wx;UqZT3KA5P-U*&mn2+5Q2+Ve;|1-@s=0^8
z90&6M=LC{urMl*F70of-F4ri?pQzyqOzIXCUe#BP2DW*aJH~uj$+`hhN97)sqx9Tu
zRkH@hGX4ET3k?~WmZ-^0h---XXtbsmQkVKZOyj^S5~ELfWNX}F@WpiEb1Ysck&nBj
zeV%*iYru%JioOZkzjuc>izHzo6gNv%)<cNE%u*o|J+Cr{iZsRjnGv+%DN?g;7v$$?
zsBkP--||vrIk*|R#Id3ucPyw+eN)Z3n7)t@6L^FHGmZS<SP*ra%)7mMxD(d^cI3`T
ziEL3whPxY$lr{gV=j^K~W-9tm57k63RzgcYLILdvTn<tH6Fl(JXNpB55c8(O1VwN~
zjfz_i2Yxf^d>3-61=O;bV|HM6hG)j66u1d&W0S4CrlU$~iti9&|DDo0mzHR=T@~iM
zzKU8^z{Bul5(e%0z(TzI0`o3qJQ|atbJNQwLeIvEAq#WU-Pt{B@rv0%;923+hd-x<
zVtccQA@?2fWBAXo!T=prmm(&TIXV$oqg;j+BL)xeLtVbBIL1;F`CB`=_+@E`yxpiu
z8jp7Ibk;?-IB5-yzrKJw36!y~`B2VnSVa!4dR+16zCE}L6sc?fxW43fw|?}M+JZo+
z%0fw|(jjifRs&)7&t9~Aj_Ae>=A3DE?`;(*Xa;-7mj+&reS?tfrfG$-5|=cB+>`53
zw$-rb@;r2#dYxrRYN}MTR=AiE4eik8@QqYgDds~iVJ4Ihcsq@C^R(!75~}d2Tc6W*
zhk<&>4^g{w<IC}kxB~Hb*Sk1DF`)(rp6obj>1hrN3PFZ_BmSVo^d5qjuoi@=I}YKR
zGz!480dm%D=aG9LLr^D-R%H}$uw`TZ5@_@q6CE5Vx-9i%5Z2^th@Q)mV!;OO%RSkE
z7Z#I2cu|El@92#*L-}-1WGp;eNQIXgQcea#^;dfb3yBShQN#L29^2%IYr71V%avnj
z=N0Pbcia7~biEjMW_D#oaO2nr+t{$o&VyuypZo0rHT>?IH--vuBy$-nlX`nYG4Sx_
zayWE^?O_8HtAXlps$b5C(Pu;kkwBe0+`FaL9<NLlmznwE1%4^kbk6iRVlbw5W(pTE
zImGW|pKaK#i1xj$hmW%cpWKQ_%ff}B>IYjxk;AQ~nTMCClW|e-jrsGO8ZnDs`R?w|
zS+Z}Vj$V#k+>TMEzm#z9@tPoCP`YDDi6I^+oPchI-VZ8%-w{jExa5Ps-)C8!y@HcN
zW4GD(PCI5|dsj&$<Z&r*+z~z&l~MF;W4h3#6{Zi!e#mk{9nEj^C#<V7qe7Wb)y>l{
z0_Slz*Ej5bT(1T+UFRm8Ws|?+MZfuX=q?_7X&OEVg1<Al=no$x{#AAA9u%3kni6T^
zO#eQ7saKkkkoPFDbRbTYjai37N#9Sw?Yi2KC*iv{IB#np8~Xk3(clQtW`QaMVP4y9
zVH7;|WN;#FMCq0B^$I5%LuQ}gf+FtaLpwbUi4cQ6<M-=W!&ehYA1<ut%XC@0)lGnT
zDpBk}{xaZnWfJ2EiYIH)>ytj7WDmInn9MELF*Bd~3FTS&0+6Exol}<mgQIstoN%pF
zjgc+v85yE3Zrl7n{8%yws~a6kft`kt(zO<49sfU~N9Gkic9Hk7*j%Qd(9jY?CiXeU
z=wf!1Aj7}o=SLxh)j3@|c@J*Kn%{|pbh-6t{boqB;Da@WGo&Vn420#GXNkS=h~MKX
zz8sdm1zb)WYa@fLY%P(Lg(?te!~J<kVkN&PP3lapU9j(kc`z>Cg~{1P1VH><&3MK0
zs&sdGQ2EW!N5+|<JJ4kbhGB8m0{KY6E&g9^I$z;;wdW6ekWWPOUgn#?>VU+N>Xl(|
zwAC;1?6ukTUH3R5zItXejORGtZgn)Rx=-!)g-suN(_*}8e6nV{SZy$NoU>l#^q70z
z`f2{j;yH<>TO?*IhR*T}b2ii7peh<JqV5^amIY*1T$DsFlhFbfpv4=dCKObd9EV~7
zai|;Qo+eH*f%A+hAQSYg0<5@-Cht52_g+?hI$(zDU~rZ_T)E0T7D?tfKaPRL4Ad@Q
z-F-9f<toGQl!O}Lm~%rH{Wy|2sSklADvkX>)bA_@3>;%gJ(X=A;YVn!tU^7+5Mt?9
zbB|LkD;C4|+gf^UcA@98AGY!cGx&_pe5`wm;I&TD#BLpo;w9=#tJ0>8+E&l?k6JF*
z+wKr5vL**<w=4^)J!!m0iCViyaQ(U+O3CXa4N)mo(z#G;@mBl4A32}%HxVZLO5*Lo
zpLB=9*o+QwS%{2oq&X9SHm@wZ78<E8-1a<Ie0I~dX3U5&m2ni850Kj)@~k1XM#~)2
zGV<e9Gm1Iy!@h@IUtA#T6vj3JK;Ui9d+OU=54mUrk($=E7_k>ViYFIYK<lop|5;{I
zudt>&?Y@=-`5V_CB_(#==F-4TO^B=&O|{U?MT1n)Di||xlqw##CfB~$|0mIA<4Y-*
zzYD&6-Op!1Kr}kM>H+Ulr|*r#E5RfHYsHf`fB8b^CW$*Ch>iI9Ue`wX*XdM$)~Dg=
zj2ibYLo&gF?g>p6cO7aSZdU#+c(f8un#H<P1Vx3UKX)6kPkK9L-t4^$)3-TJ5_zO0
z666BGX;rwk^Jhb(xJ_?eYe7_Lte~b>S74QBN8pfOkWqb}yn&1d%7<ME3U%OznYHCO
zj`$vi=YZ`QTAMM6x+rXB4PL}Q-=ib@-ap9u$3PWSEsE94;#Fi1+d&9Fn<L4C=cOfp
zh)e|kWmraa<&d7UK`1102`k^b1;~58AhJo0nops1A>bKTm;U`4lH@=peRRj>mAecU
zjNAu9B}}7}<oM1={kO}T3tmNok*CqbD7D4&O3Y@dw9GaF<p4R_jbR#PdW;NMnmxtU
zo|py$Qz(nNQqDpeAonlp*)0eSO@F3vXlO0%jw%XM(Ox`tjRM5(ZwBPJ6dsGls7qe)
zyqKchgy0nStT-vX;e3dx+$bqTyg$+h=P?(6TA5Yg1^&#)tZ-Y#P|_`c_OLj`J)$ar
z-`|#VeF$NmVF<Y74Z|}kCvWdHg7t^2spTEeooQy89*=&@n6ys~5cLjLjT8v7dOrno
z^eff_K|G3*gA*${-P%XO5JV?wXQ=-8Uv-Fv|I#$$8oa_|8JMU!8q8ylKm_iV$xels
zYrU`d!fjQlbQF6WzqU&B;geDW2iWmnCoCU6W4XH5jg7`<@{ARElmi2l(WjG+p>Wyn
zdI;Dr^2MRAgrAYE%fKv*D@u4TWgU8;8qyJGo%fcKB5-dZY}LMT-yphTmKHEPUw+kV
zF1OntIgMB6PMW-wvyKvH{+JLZvpw=Z6fv<GhSq=`2qdw02-fz5Ap#c-IM5r34jN>e
zBh8NNGm0%yd4^9A^h6B`tW^^QiAETn_Zs$~z53p<4T_iXEo>A?20m4G2!bGXDq_Ap
z>PS7^j~7G$uYmt>zRnaSYVBHVv%f2fy)}CT9FcBt4ergLf25yl_nVeIi9^XRCgYHj
z2ftyqMK*=eeh6ke*p<d}F$j+)oakB)JbYHz4x6XN{5H1!u;ktH8qzHH6>RJrf-C{C
zyhex8a+4Y2{$&H$4)+60TsXtfKo@w1Z2GY?t-<n?n~+$mY?kt<uB9OUm9BivvRd|4
zM1fNahgsX7xL4paFHeXj^p39hjo|V*R4)84R8fa!(*gV%_m`{kJ#TZSy*_Bn)QM@S
zzSueekI}WH%-nt$Ak!aVHEuJ%;CHud=3SYqtC#1|7}nEdVn2D)#cp!IXGXiRNRgPp
zo`<E<ePehY#C8EJ*tKxUV>}8byX~#!wIuM~MY$_Px~gnqJQ98hWs5@zV_AGmzShLr
zKsAU~4}$T9`B!@4Eb1-lx_8isWW^XDtrwz4(%Nl1OB>ba>|itKEwAc&y%xlUa!9ko
zJ8I!8I<A7!3m`8ADc7&KSf-}C`N2Lx9Nek^+*~S+fxmyS>o(HN`8Cpqq}|bOw6qly
zdoNlR&60g&FY*^{a<?YS=UnamdzZO)X>j~HX3$rWzybN4sc#BRp)&{-<BPxf_9^J2
zvzCvp!_(Zi@tD{C2;bgA33n%ShZigY4tI)1gql1U-4$7DmHD_346)J;jScI`WRT4W
zs+*I)6&m%V*){-N?Y8H1bC(OQ=}(Toz4vfD$Jpjr)>cXgj}-{0`LEGvN*OmfZntN3
z9n~3<Z`$8#g{u!H#NIHh!IYx5SZQu(Bd6Unx36&`xz^NiRsuzkHVpKA#Xc!tz6L!M
zXiyz<EyKIYB=UcGNLq2Nq_mLh1CRD-;uA(&UZ}OP7-O}FgbL80^owg}ay<c7C>Ggi
zo|R;^S_uJvnsK!h-{`VhTY0#w^O2>fa=Gg9m18%qlIg;ni>HZq_4Je5zAyo&^PH7G
z)KIydqg_TV2KhgbL>R-B&8r~=#_l`mCet{IJ+AVEE+U8Ba7@wF^O{=1TY3pVU>lls
zR3{D`Cn$bW>lmH-v?KnfB?}m;ZO;O6I_y+^W^W*$)EJLH^|Z3Pcx?cwg2Z5HahW_!
zV6836-G=~(*m#EAm@EhvrIZ`N`bZv{Pu7L|iT~v7guP034#B|s7Gcc7RI>~r#U4`h
zePm)<p^CAbY4A}k#WfG8Qafc))^jj1U$AlTor4W*so=wTMJy-6hFb{HVQyhwRc%84
z?NBFY-0G<Y9Y89$@FA%2?5(X9hAl2hpPSDj>5kEaac>guG1#x4CEV=kRE`928VA-=
z7T&{TtlbIGzos(4-t~veV2@R7w(Anzs*s+Dcy16}osv0*qyG!m(bIueo09OZhj`~)
z_E`0dhE+89(W{8k%m6M**tciui_2a8eg2)}p`A$8ne!K!0Xo+jJR07KY7?^ebj{JN
zMI}XBdqCwJq~I@g9{5qGq85MOO|+r!{HzuLMf-W9{Q!Lk{r0e{AvY1=SGA-Zu#W6C
z<~D0kFwF>_SmBls<ZHU$;55<!fcNkTmXw$!HuJ>JzAIn_kMtWTuE=gkp4C}Q0Ldo(
zghW0W@=R@f?>cK+nU14dzB&`7e<iZ0gU;L!;_3SpI`L>2dbOd*EQOpx)roc?9%V*m
zK8C`d&cf3oS1l1L^gVp~E;h^$Z+_FU+{rQec|{5E2R^qN)Q2}wJNLCb$mHr7%h>x~
zj|#b{#&$z@PPqR220uo^%eQW@s$~eLqgQE;foBd^J(=<WO|i=N(a#q;7e-Us1EH!(
zJwm+Ja@Nt<1|6{SbJ+TSZMH<Ek@F<!qMpPi?op-jdNVl8PAU`F#=N=yP|%y)NttTK
z$mdJ)4IPP{z4eYybQockueYFT638LmF+R@6<24*Ga5bUHHhcDzN}QK1Ckrbhq$I0T
zEow%$moi_<T9(tdT&_FHoVfOjzJM_Gb9&KaC5*<<^iAjIrI}@aI#3DAv$kG58^!AF
z^O1@0FYoae_@0u__;~ZgI*p;NBLwmwuL((|`7|95tqMMYavVXCn}L1mS{;mZLVKGE
zR{x@H%0>?L4q)u?%3|tesgPT>QPxb)RFXtQ+&+#ta`gHLNtY(=Oidu*MpVm6(Sre2
zD4V&L>ghv+F*-06dM#A^_q@LsRDHrF^05Fgw=1pVr-nk%a`5O-_glfjuemp@L~S&R
zeyVG4{1Q~!3~qZ-&?(qh3Z=8C{L#c>6Fyyh@<~qF%1-NL_*|FOzc8b^@h=r|IAGI6
zZIsFNWMOI+L^dU92rqD#ErDs^T|tg67xub_ZFLgvkfj)lmfGzHd@4({D)Cs*eDEBy
zU|6u&?%?h5b}@AfY5JhdkOyKLNnfN|jcyB0J_N?92>tJC3^6CV(e_}_MPWA)47ede
z^D%pJ2hmj>!-27&=6>{ls^@`-h+dyia$bpquIr1RnH;6D|9P8bP}1*$uped7Yd%M#
z?cA2Ca~2mGP+Ts2WrpBXtDVPAZ=jL^+7QICE4J*LrbMxtOlVk#s$XCM5n?Sq1ZvAd
zFCb~=%mh$>#Z9nm<p)D9H$3LvE5@+}s4`y@k?TNxoL`gf)a}wEo^NKEmMVYYrmN<y
zaUaNs5~ODmH1XpJbZtptckM{5X%cpE*De(W=v+>4&s*TQu-xkW6uC)QTp-k=rsr}A
zCo+iF02|Z#tEpe{)VCi#MNV+mhEzXQ*Z*~Ff|^1?fshpNvlG2ZxQ<1VMY4)$`WbLw
z0ADZcqj>TSH&ZGjADc$J(7Rb(RP-+7UT5<^r(XMze=#?<M$42ZWMvB)PUCbUXD)SW
zTJ%!rL}$)L`Q58i)s2o-ZrP_?NG0hMngPStb}H`V4s;%!8bnFGk;^ykmxM)5zL$4c
z_<**0<pbnWL2zH&D%MM52?jWEn*IfrQr6}>djg==KbWdpXC}!v4Y1<7Q$Xb@8*(O4
z-d~ezRL~p3R^Bp0Ej&F|5Wi@udvaJ7a%-mlDt&Lfw*f+9FT2k9zp^|=958W8!h#7H
zx6Piz+C8V2X_`M5l=RNY_}lc9pNB<5yP|Jsy62CX%2Lp5HFXrC+O*F6=NI|%Ol`qv
zZO0aD{^NYB9|I7&nonT8fI?(5a4`?`NS%O`5p~Ah?q|bitz4Anu#3!-E8q5|oV^>I
z#DY4`MALxTQviN!D?rHF>&htK!nGtY#Ur1io2pb1$ukLLN#&O^#Lg+CWf@Cj-yc5!
z*UaVn{DSc{W}%dDr6j;?5++Qw^ZTn^k!*zVGk+X3q~CzNkN^3snpik<MXL;Xlkm-F
z*TRcnVMwy|y@(L-16L;l<(pJyC5D-egdL+;5t1G2O)(t(-;eQopZ?wdY#tQ75mz`n
zKqvb|25I?GzLG`IbvpmU)oktSl^qyK7OJ#NAxTJ5Et&s!DdVM^+-?9byhRdVK-`D|
z<z?5=!(6Z8^9u-e7#|MJzacLi7x;@dom@#n8?A<bIE6A7_qoS>Ra{b3QqQc<>{$Jh
zRIMb0UXHDB=u_Ih!bI8%VUm@o2MAD~V-@8j4-g*js1M7mpo@0XR}*$NBy>PL#cPK9
zrl(a4#hoqVJFOsIv6fnFE^F8Zx>9Kgo|S|=@~&FG*7}#H#mp-goku9IO#uN11Gr;K
zs2%{tgpQb!x0E)58xTc?bAXF#ODt4Xrb(G$0!8^t7oWy7miXkguYwlrqV^#uh^o(Z
znvH~^nq>O|*2)uCN<_?b;_s7k-;!I#*!(#zRl~sLp8kMEE=BmWQux+<Q-6ci!wR@B
z1&(*@#xsXhq*g#<sVi>nReHCT<8Dt4{=tseqd?AYv(I*UT{qgtg}$FMH?>IFsI1E|
zb8JU&6C1zOddGHjMffMFV6Fan)y+$&clBAR=Nj77zEUSWWiWRj_yNmBhbQIsHW)RN
z%PG%44t-(BWM<VYzu3p4VKijEY=ixMM6rg1ky_)U<rpSBNk=2>L8-iHv^WQj@8&W^
zF<-ts8&jM9u{)RqJ%*1AzRHLROTm{L`aj!x5UIiv5s-O}^I?Bbj0<$X&{rcQ;mm_E
zDov}U+>gX+j)-i;rbFDA4wzu{MDBeIM%pC75w0X=8@Fy{up4o)%$4@tS)e&4%J(Ei
zRO1z@)0YEX&j{|S%?o8E6{z?+3YIW?fM?agnVJttDOwVMa$|S|4ei$KtUb1cg}`))
zmEipYTz+A1#<5_ODfom!cu!TB{A9Nie3dqR;3z`nlAsPP^I{L{Z0To=Pl1&~BEyf0
zWmiGR7d;Z!PKE3O=&2|SDQ~W(VtOC@D(OghgaCcu)`v%x7(ZCNJuzlw#}Kvzc*~E1
zVA9Tec>ArNB(n3j7Z0N@<w$~l!e0$hrz($5gkHb1P`+Zc6PDd<xd{JJ_FNkMG8htS
zB#YBuZtr01kw^JzbhE%iAepd1j67uGoG}><Y3swhk-pS5rfto@Vh^6kpQDxq4@ySn
z*6MC5>5^dzf&12CBvM0R^v`z@up)vNu#C+Zrbtz-sr;+;-g~hlLCZ>WbM=FrCcmn7
z7!O99)`+o8CG4-89(S-3fB<6j0SWO49H6!A46a^$(dq+mX)3piSF^0i#_~f0BVpCd
z<ieJgKeV^JW`Fy}YBwchSGXoZx|OvXCN%!-CZ?sOjvoJLW)oaJ{P__!j8Mjb2b<?J
zW#lOpdQeu6z?noPj2^3q@3QgF-?-4z*7;vxsMDu$nsL!P=TGdV=72g$dJ(zDCH2!`
zSE<wKCL(?qA|2hag(ch<+uquJwwrUoDRLFPTpmc28=wuZvt}8A10gQkn;JYQOgM58
zhNc3EuQ*;F5}cF%m0#nPfkqLx03$%$zez$;*0WM54HJ38vqZw{?X<SU{}g)$&d-8g
z#~Z3@Z+ssS6vB#l#QznAsYkzU_0XJaa5Qfjz4h*SY08)sgkzmJa)G#zUTY;}$ZL8F
zqWxj_Au}M@?Xh?JIoo(qZhzm~O1r`5L(wooz8gdrG9Nje48Z(}hs-5YIXKco0MOj1
zahQ|JR@?F)_X|~4%HO3PaA@*8&__N+fZ%bsO~unwu+s4PN;|owra=S?CWO0xm8}w(
z@cA1DQpHGV6~}Y1TS89}y)=mprVD^l*9_8y)fm&k;$VotYHpl9OGTmM1=M?u6)ASh
z`X&_&iv5C-uM$wR9^4G7nRTrK_Q-1D^no%gI^Y_&N~+^TAiZ!ckNPT#<C_0iTXo^O
z^KLup<hH9<Nw++FC0t`HrvL&wYM%IrpS=oX7h`;)#P6$U^LcRf<z(dn2g++%NluKv
zwd$<bA0o_oh-}$i(3<ObZs;<?19=C&k}>;vu8AkZ`r*gDWL+#Ih>ubPn~9SrP(R88
zwp>Aju)>e5j@@v9dSvr13Qw~Sax}DG(#t?M!|%8oieF0j{+j?wy$t2-hGe4d{ER>Y
zTohIOtZN?jd>FQbcGIvBKjP(S*$PwPv--uKg%}BKE7K_-Y1vS$`6taym8kA08UOt4
zUrP#0ip#g_bM+jryHjGGS9ZnT<E*B$@h1lEc|FH^V1q&`HAm`3wnW2j2KQmXS!phx
zlx`$o#TJHM^fx@?>-rIkk3Oa4U5N1*IuI9IlR5TXdKf}y8EWZ+j$a9uFkAB6TEJFF
z9Hk6%sUs};#RpvK&($X+<i*xVLeY9hV~+e7Q_IU%MboJxzL$()&sP97VWB6T4>_Cl
z-_f!?>mpxEpO!$mZ$B0z0jLkJ1+3yS6^2y_{}^nkUPByKlyrb+c7<$0PR1w;wlKKR
zaH6+8hSj0D)Wf_t1EK8fka-aAS~wI^g@2}?UI}7kh~(hxHef?WUE%rCyK!b0!~wiI
z47dwC(DPvtBuX0ag=XwW({?7&0XyrHp?OP9_+l-Mhq=Fgl$YQ6IM(Ag<ssen-u2OW
zb{Sc1oNWKjZJUoij_od^lz4Iu>36h*%fKjLRxG$5j&lJ`-GY{xVNAR+T7HA3ac8hp
z?Ent9YkA;n7{r#g15m!%;Y9#CL*8onY;H3uG`?sTl8bR&JhmgdLmH9^9QU8G311G9
zo8}z9-@3DAHr@DPO>^|R<1_lY5lX9CV<1`MXe>JoW4$Ds3-Y2BySR}hABfV$G3)(Y
zXhu4ROGj?X9t1%k0>5dOB@hQr+`kN^#5j(Dl44p5C|N(f&CGEt--zdR81f`S*B$$`
z4cQwkMu?B{%6}8Xcor0ENd)_+bQZjYZA|pRkaw6pBu=n8+T*t#KwAH6yjBJR%)r?q
zV+<xsJW$DOmQDN+OCSci>1r!PCTP!AjIB*^fRXQaw~e^^O5pa6vOXyoIdoX;d@qrU
z@zBJ`CRg|hmiqNVMmVc)AM{b%6Re`@{uvJiXI)(ik0U3i1Es7We0KSwuI;Ct_91c?
zRIGD2KJ-q{5|PB#W7$b2wu@`2UpVr~!-vt3`{xO;(Q$E%owkJi^j7C+{E2^3IhwSx
z{8vE)14|Y?S`&-!#O#P`w=Pty86{~dw^jT3Vp8gg4YROC^Ki4~b?Bi<C@?A!-ed@)
zkVw9T^okN{DUhGsc6+?hZPD4epbw)T_&6F?Em?*e?b(^$+zK0<edY{zLD@VT-GYJ|
zd>EU0FEQ=Sb0Hu90V2bi^SbKk3N;kr>j#SYg~4htFd_X${q;jFG@*KB=E|nxv`5CL
zqMV2iKub^RjLv8@ueb3!1*2yqs;?c5koaJeL%<BxZV;vw?YQIL?-3^BYmu0n`q(SC
zFc_lOw9|8O2jJFEKj`e8p}!G}hm10AFxs+u#HxxveoM^<VK$@k1tU4JxKuzwZpflK
z$9!i06q*CA&)NU8wRaANXfo&%K_518Z++tBx<hMRXO7@!Rr*@~aB{S)?+8G;Piv0%
z%`^?^*p7x1YoN-v@IO~=cAD>OzRnEt5Uh%|gJtE%LCU%mI|w$ayC)rPLOS`ds@uM8
z0*>iK<3{+U^woCebryE51Toqre3~wf>M;K=G=ul#utaj>5x;9?`9UGn*)0!n^yOyZ
zv|xj%lRR3h@RP+&+#na*YA<}}2n)!5Ux_zTm@LSPK9iDLskYK8A8(la;%oQf#^I{A
znQg#Q;F<LChb7@x31YE0oBQwFj$sEn!GE&8rEzhUXn4`_m_r_3vR>7)fU`)uB{~Go
z0E!<Wm6o6fcr4b@vogtXfr|LISOH;zf>F3g=y!>8gI$-%Jp=(&_Ld2KV5>$hOD;mf
z#R<ZrLUeV|_mJwfpE38g(*Qn$2y9(U79Xt4yTE~rFx@Km=Y-<u-UdADa(l{e#D&Cn
zQtqOsfqOX_);-KrCBXL7eAPjT?6`l(gZb2Uwh96X({~;V<vUS#SON95;_u{l%z=o+
zL39jkk$pvm7RSB7J3-ZX{C&h?C(ATrbNN~rKaDF??6(S!7~n(wa>1CRkqc*4QdY8s
zYzNzgHGr(miI2b@t_YwZaz>RCX}c5S1g(Qni*IktoM4|JPQU!n8Rr{Y&88h4ne?#G
zMuL(3*j**+ijv5tCu6-o_tPV#*P%;s5)OS*JpHFoaJPA-p9qx9)&7atvbG49w(8|K
z$)%3{Ngxc_=Bgbx7RSZ}%2rn~ES43y-+Nz6juY=fg3jNd`v0n1x<aKN!f<KwiM^GM
zprT-grl|RW$l`h6)8rP21w*T|f$yP`=kp3Yk38bCqJ8pEc;R05w#>B)FxU?#<^<@v
z^@QdSGVgu>5F%{Dtqkh(wo~*3JAASqi2$cohd7CQ>1_sJhm#bvz3i;*2*g<=M8YJc
z(7+GnEnB99bHV4l#Xp77yl2iTdHsWDg0)SP0Nt>)VBC~^>8Z4}%BlX^060OwF2l1&
zKL?GyltCjTXxP>@UL}+?niqdBvqx?{p)H3rwu~@}BiijH_l$xAF@35PTSdBSOw7p9
zKST3{TH=52eB0h2r8eqY#xBR|I`(`%hrFJbQwyD=VAJCK@NF*)#{zQz$sW)|4usrD
z^Y`qTT|R!4^}>P{Xqh<d{yzA{T6wDu@B|>~aVByQpz$r{r(?y~&g@{fxuHox!&^(^
z0l|bNEe>>CM_@i>s|$<0bcyI>AasE&ckVwMO2U@7sZmNb&2>t)zf~~ZtxdnW^gH6g
zJ@R?=yg_#SyWFizDR9(yXOZ_RKs4TaJkco(8#5v$f6&&305~WM<;?!xNxg0z*@E77
z!>DRiUYZjmTeCMDj%}Ckr=meCKvkqFV)&uSNQk&3F}{4~sF>v}!T%h(tW-2>2v6y+
zIg$WM9?GgAH~%tKjoNJEVQ;cNy47|%n%i7^%YE$tk5!pkn$%xx0&5sV^>7r9Tnq#d
z0ouT%lS_+8g=oq#TyiA}4fY_Rov*hjzicD_?yY_zUb=0}D7pSXi&N&1I^{1eM|IpR
z9kM)xNCrKMj%+~u0X;*Hm9|kW)_|)0Em<R=7<eN6mXX13d)5{}fb-Ealt%z&%-Qgv
zPmFMVi(pEiIc-9L_fDnb3~FVUD$q`N>2VV*Rkm-*{I)7`PUnI=>EOYU`2DO!MXZ^D
zVXm~A(BHtvv#8_VpnyFIf)+!<7?UDGWV(Bqat%S63Y{Xy-E}StBWD%PBI)N0@A{Xx
zo;<h6DKaiUEefJAPN8eZiPbARogchEV+TM{{Ud}o<5oIBlF^>Cn7HBALXUZB><)M(
zN-u-O@u2qxjv8mN<CFZ;M;$y{3-R)yHdPqqE}x`ewj6lNX1a5$#lRn?aQ69$pTdDb
zgdq<AuoHP2S^W7wsxh@~u*RCtlbdY<z~%e9Ax&Gbj(J`))!pTE%EC7j1)_Pb{n?cS
z#j=>fA>vpSdINbF!PN(D;TF{XTHnTn?8^8B=Rwy)!)dU8Jfr=pqT8*y9lb<EAc=#x
zN-;Er4y=}#3uI4a^J#))faah%ia5c1A35I`4iH^>eJ>;X;@=Vc<g=e41caJ%V=~U6
zM*|Utg;Z`m@{02@IIC#2%WgaLfF)NiaaEzdE|ZIKjF>tfI5)H#$T*W3?8Qi<Qzb2`
z5u0=p(Pi;1Keu60O7>ZWGMV8Mz)~%_^+!G!m&9<FP+RErVx~Sa#Q2383;V!GQP(7l
z2wN+1bJ(UL{vzf2b@^EM!;;MVVq0j)1TEy4OP1%8Exf^J8%A{yWyz)*=Y)z5yinc=
zK0X4sSXY_n`563D6zYM}XnDHX7&SOACtT#hXRsjfuo2nvf*2(M=y)|~{&N5C_WdSV
z*MaGgExqCm-HG+~bRc+9K|`yQM@u<h%V^2o#PdDcuJXZQ_zBq!3+x<aU%Kp8i$>yy
z(*Tjal`nnl^tzyofFnN-G>zxMu1+=P;)!Ke9Uf{m4-V(%FxTq>fcNdvy#&0=sBt(N
zr9V|91s7(q#)uUC8AU?i>)4Mw%Ci*WNsE!4075YPUBdXAB6pn*o2!G;GJPV45hGCQ
z_Bt&=Q5k)k(i0mK8ZocWEveC6bjjKaswwYkxA;bX8j>f0XUH~MRTUDkQBv$R;dvzW
ziywg$o=zntXWd967Hl~MaATam{6GEI6c3$lz>-=PGzX;jj@B{!R)pdN+DVk?z-Xp@
zM2C}s67;O?^!>!??09Gy@bC9CR}O&hQ-gVoDtpTRjI?*`b|^RXmcn}f_eucKZmcCp
z$CSF2yr#^P>$E)9qdQPBO?17%yX@z2lu);z&mFpjw}Rm`r{LHfL}hvxF>@c#^ryk^
z@4BN7i-c`9I}E+YU8UPzJCyuPy;4w3as#3ij<l_vR-}U@gNHq)$pshwkprJ55a)w}
zWgt$rDVT>YvoCFVz`BXi05?q4)Dd4MTy?sI-Kn}0ATC1e&0<#JIyNd77ZAQ`DvOma
zO=&ThGfcns_>j<LDzon?Mq)mvXLOmbM7ZdwNjPlATU{Epc5q4u*IsAWNYiA&HD7%4
zKvegsQXSq_SisZOe5Kd|)&=z0Is5Yb)?|-<I<;B`tO@2LdU`<m)q}DiIKzIE`;X!%
z=eDN{$J*Y^<qOVkaJ<%|3-=H+O8TA5L4)Qvp#b4qz12XmxD+aT^5GW-*|z53`zh-F
z){^0vw2pkZ|F*poH2Q6i;yrx+si9|HjQUA1_MIUUy0NpgpYWi++vAqNJvxmR4w&Mq
z#--m~Fkl97PZgss8E7X~$7G35ruCPD;k+K5EiNq43gP90(XZOorf|Piu^`N@#9_kI
z|HJ)QyK9U=mWxc85&5c@e(Gm|fApZxd|Vu1g`pSc_#)nY*(PMC)D~6445;NsuDw}9
z{vY~GP0UZ8{t3X#TD|Wfm=?3ajnltHpi0UWR{ty-x}O4W)z$Y+UKxr#-{)-ey4c?U
z4SqO>xGi@Nl7sSJ6UiV!5jN?{eZk-;h-aWqY=<S1APxiuSV0+(9FQU0^u5pA((9mk
z#XAv1fGIP0Fx*Q9te>|(Jmi@gl^z8(3ldYQv>sI|R8~HQY;cUyv434ua=0_mj73ue
zvw?Q9kyR;dz{F@_42aKO4Sfjo<S!Dk+a0!L3lk+>-ytCAGb}TGJ-Q_oa}wKvm<EX6
zOjkzlu>I}n37%mBE?rJBr`;VK{8`$*v|lp+L&>Clk=<MXiTfuOLaoO9dss0AL<+2?
zyIrLlu?S$p25&P??oQkkh#aXIUGlmF1~p7iMFx%nXT*X4%gayjsf_SFWd(D!c5ts^
z9{!gXXt1wcGmBxaZY=W2EI?Zr|3SHc+>iD*NB!a?xjAN>BGc-d`91`n<J$wNy+68@
z2$-<0?qAe!9@$%<*;C7OWE$$XS4b$b-+AxtW)bAyB}O$JsL*nvQfe74LeH<AtP<s0
z5-Vw5k010VzywwBD$ww=?!YjeomMWm(j511_x?@)ir@P7QM2PCy>-z%Z=3`%e9*$c
zNpzR-ZuezxHmPy$5*{M921zS#^{o=2^^B*FO-Bs>VBHzh>jAOQR@Y{C;Y}^YNN-_}
z!p9+pn~k)PiaB)UTJtWD7f&7F%QNQZ_}+33*U~1O`XF?rjxW;G^64aD38e3Iy$=*^
zTL;YoQ=HeAS4<tQ@zPi!IP9D(GH5AO0pExvRR+?`Ui}WN=z13FHGOjqc^-_$hMk#k
z>|z^7-&jw@XI2nUs*2CZC37CQJvF7-Bbr6g1cpBTBtLLKR|DA7EC7N@BCJY;w73BC
zLY~#&0SvYI@7|!XQZO4EEqxI6UIpTULrGbXDhRcpl!sH}1B0D%;I-3~LG5QZLI4)`
zZAy5v^uT}dyCU8P@O7Q1Q{c?K)_8ijjzSqbopvS~tb36$(|N2=h)sOhzVgf2OW$R#
z6~&`Pj=s5PcIHQC&S`FGT%}a4-r>1iSaFDd-a)&gOEqS2yGdo(*DxH&xcQGU7<=87
zTQMH?cP*-kpbf<CL63`(cr}|@nD<SGDqzZ)%-sNQPdR6-1o=cSj%QD0`Avb9{fRZp
zB0urqm-XmPs+o@x>LCzJ1x__&d)fzm>s_{l?4c8NRHCYklgZrJ5$N5j&97@G&>z#j
zPy#b}5vR>LrzNZ{^yeF$8g|6UiI2&xT}xv+SSQ#rjDPSvWNSp&@4oX|(`whdkC(t-
zyJ0-X*NS^=sBUM<WcNYEly{Gk4EnJyG76ADV-|QYz=XOMWHveqXKT|1XRkhO_Pcs9
z+kbr~C-!Cbtp-gl6bS=t@abWnqtqVd2lzIq$g*Bl3xh`!_f1b|rR)bAxI`afsP){4
zA(}2S5q3>_hpBptEr$+>UXhQrM#hQMoS}LfLE03zNy@Bkll)VlR;#9GGb>6j=W>eu
zN?THuPG9cM4x_u`jDBpRRqf0&5Rsc*4vZcJfBXG=!yLQQUE~G&@Q9q9AZ^DWMfq#*
z`FZh87b=Z3Fj@?gYM$K<;7yuPPk-kMJ(o&m0^x?n{p|YBu;!o|Em$w5uIOUvj*Fs%
zi+SxK0EvLz1(4?V+8**`*O=_ITMJSAQ5aY(1D+GyiHW}01`o)i?O6_@vKWf<KR>Ey
z3qDVyrKog5{ss7GIleD<wV30pJmcl1S%{EV%+aH-0{Fx)0uo(<O2KSDSDQU|3s&i>
z=9Oo7_J`A&zsP66X=@<AY~jRY-G;pHs#8P#g<PP#WTd1}81=bUvD1fj#{@Q4L~_0Q
z5O>uO4+4@wOpJl~S++hsGTVrpVy9-V+MN6wrc&mNip9N-Mh4IN6J+^T7H<&fR@j{v
zVRfh(2&EcROLYPg<OX7_LG(SaA9%uMbC$fJ=qeqo?c=pB(ed=M&%Ri>L7q&RfM`c8
z{JZB6DXom?Ay|A&#r*t5t2>pJkABR0r!5>@`YxiFe=;?^>O8k>G4BsJFE%#<NCx!*
zbwDZ5x@5dafY-LSXnf16!Q%l<3<90GVqwHGS2WqVJ<d6{MaA;P(C5-H0R_Jrm_4F%
z3c`f2G1>nse<^e=AFkQ*B-e}cBdn9i&zt6y_XAT2?d&tW_r)|-oJ3tw$I)~scF11s
zRx}XFB#C^ZrQU_x!f(5{2`%wAh@Jv^Ts-n3<8v!0M-miS)!S7o#i2xL`u@>w(C8cq
z=`1IA21|RSvzke1o<tA&Na@m$5)EWikxFS~sqhH!hyKYD4|k^Zi?}A-A&gOKbAv5n
zAiO_XjW1qGRXWUVb+wMq*=I7;rxMY*^-C{<i@vbWcW#`4>%abpHo%A1cS1{XzFGJ{
z7H&M@@MO}gq$K=2-?ZCq>l`y)Ymdn-5+Y+o6Hkx_9dae8X)T;>HZ(JiGbIjJ*xite
z%oj3D*%X8f2p%g%BzFJlu37hC2Q#7>P@>9F?1@gQK8j8{HcJ+!5gGDW<+c$dS9Clf
z&o~mw5{VN`>gPW2rW^M^JeRH7FHlE3-k~waT03l;q;U(hhpj0j2)l96b31%a0__G*
z7!TE{#$U6S^X~*Q@oFbvOU6vMLmz*~WhR8EltPEtc6w701VWLf*zCjSQ_(B$i-;YV
z3+e;Ip*zlh96P|PzvV-eAm5Sa0gj(PsrJPNG9{muPh%*!Z9+8&h$<b(X<kE!_tGRZ
z#U07puOUl`KmBT6x(eOtTxB4)n1%DFaLO0r6RCr`*pH+{F7>@rvMiAja=^T8QZMuG
zJK#t&3$#N$xJFVaG1@H<dYkl~@=%1l)(@n_vfMyKPJ=239RZ_*9sAnnE}oBzFl$zv
zd|#Jwt86;Zd4ctFpR2GU3T;zZ+cVZ%Jzr<LFoAXU(=dJ}1dKj*$&Zt~qIsoXk6X1s
zX^GTxHt=_C8Tx!c$h57@mU&cy86*Ss<#-p#A2a5Mv+W|zH7)n#-?2G`R3qqYtj5NI
zMIc0czq3Q+VRh*oaI(t4L>&frG=bm!wa5?d;pN6xxbYn>ExI|Df7{h7B6opRGehS-
z`qY9>ZRqmd!1n(eQ1N&sR2|HlgBmif^j@c;Y?wzzG#PNkTc!^K*`v+j=c9`Yze_Vg
zCfKQ6Cl9eecwfj$<c^<CPEtZ0EDJP%!v@ltkCpfc>u8gRaPGl=2o1f|w>|hr81t21
zGEE6YfVrRSvY%@-p8%q4)-MG|^ia5o8>RrCZxWoAIxK@i7>PZ4^^UxEJLD+n2+qD+
z4o6Z4WS|xVM;*<ymyz(p=8qUOO6=HV%U)JwFfI;|m+{s38m4aWmY#=o!RPhQld^-~
z&vq}57y7w)Go@7!yy2+efS-u6?Ex>UK^<sT^DUP?y)V^JHU7n$Bz3}Pe*WU2nq0W*
z6FclPP(>&3>#h0`Cpk|lIcYaJviBRQ??RN8=LyY5HtYii<42FdEQA-9kX&o9MoJf5
zqP(`Dz>jmV@>_gp`d$V_dwAKFZjvJyu;gb&jM_omh>s3BL(~p|ieruit_nE}i@Gr_
z4tMu0fqn#Abbp}@RJR}bRde8A`d`OCX=c7){&o<Cd4Lhm(*GJwljGNRX!cqTpXgT`
zSAN{Ve<=z9gwQ<|o!J}Q&8!i7EzVD-&l*SOLw_ShpjaNcPBHQ%2pfrB@9+Q2Quj@n
zx8-O45Dzi#8&Ffjs=W5mLt*?D4`9&q!+O_z_|}G3jHq!lwOeLr_p)ld_GX_EdAfCz
zf{VhmH_aEwZ+wR3{Rp##qIA@~rR(hX&2!e3UI9ZEe|S4u-=2D+em9(4p6C6DmekU1
z_1(WB9s8OxU<)BV!tLc1W40Q=wUEsF#8UuK0|W3N{bMxH&<Y>sv{F!&W5m=&o_mdA
zgc&>l^s~xL=P<vUQu^mP-o3bPop*6fv(2mfD-u#SVH+ULv9%EsasVVLAx&Vr(9_7k
zbW)+mJn{%K;l4=KfX<Kuc(di~lq!FC%_1>(ox2|10O}YL=6{AMXXqpRFsBT?V8+Bd
z`x>^33_IeeX?U}kgddDthj!Yw8<?TXgd*|<gpg%}@3<!8t4m&2a6!&hJOJcFU3;hk
zYlJUR9>l0oDw2u*pyq95On*4<r(knU=?TY|jcS^>IY*9<=mGPyAGy0*LrpNYt+&ek
zQaP~tRR>8zUeo&JCxdSFmUtrw9e5p$Gt^Azet%90@=R$Nu3Guflgc3D9sD>)G;_bC
za$XNKT+O_WG}^Ivz5w<u4E*mx<Cti4`?HC^eA~`gM+}EodtnHQaut)+XCC+C98}t1
zO~UuMGYGd)EFO&>Fg`Ii{WoA3FoCNg_+eDn@0^OCYImWMAHvZ~j@VE6kN1R$klO`z
zVa+X1;bIpb=8f;C`Br*9Zb$?^sSdiZJRm5u_>N;+VDb9}DyYvOl7+rbLRK+XMr;br
zM_ZhG!fh5i4S(_rQG?p3NZ3FTeSZm$MWCi(SNiryjBGgzLi&w0RKWo3EZACS{Ipi-
zfK&RW?1-Qsg_>WL!_@KWJ(Sv9HVn7X*mSed({x!os`9r@tp*N?{!p2o5-4P1{dXF>
zm>xQonFTJ-u$BOAiR33-3l2z^TeYj{ycD+DRWi>t>r|eMnw{h|aPhkk6}*R9S_f!8
z{qpxK<MLtYdmW>L&JIP~b_d0mHmbF6ajcpyKXG~1&12#|l}a1<RGKJUg(%*m$@2-P
zT9{=dsvukc8K!*p>qjyGgV>RPfi#!mc0AvKS_Em&*jbo*39=TBODcDC865AFhHcB~
z;N>hMgcHka?`?J%@Jn<F@r4;1y;410@NT8U95IhDNEcFHvZiaFE(CB20+(;_6nS=T
z7N_Mu;M4fez*6EsMC+Ya2I*(#U4L4@&Vx&T<+gP`Dt}}krXTFd+hA;&Dt|dTBW}h`
z(fscU{Q)u9E6}&1flbWc#X1{Dgq$d8q^(KbX{y|7uw~KaDAeH~l^p<DhO!c1qR;1d
z(I57ccyrXZh?au1z)|b^y;+065Is=_7;>%b{B?P-8e#BElD#G}4cy*yKw`%mZS+n$
zns6<Jj$%P&3N&O762XI^Li(X%w^C)vBBSc{yeP3}=XQKK9Zca;KONS(=~DpHMI!Jz
z*dUt$yno)R=HP)q@ws5c%rS`SbJ{rAT)qVf;&D^%_6VxCxXOgKSk+m$g*d@%?NZ8d
zek}Re;{q}*8~*v%vDg`PQ)5`)a?_%J#8)1=-J`Ew4)apu3sP~KOp0WdnvHB_yqI*k
zlMFk<R%yn=+jUEH!v$HBO9Qe#Y!3!3yUUE@z3K-To|nGQF915BkIfZg!mWTPLIkh<
z`CFPB#lvuRJU)4^%8i|>3S9Vpt{`;08dqApt-!dc(8ZrjD^Muz?j#m+i0!c{f61oY
zkwp%obbxi8!$5DDEE82zI_wT^_7QmS>4v&p0y^1;@S@iSsKuj>0;Nm+_)c-VV?6bI
za*i{K5OX@YGIe5pnhDeeyroQC#U1kG1IKn<G*m1m({iN4T|QcP$@lu2_K<H*`%t{<
zdWlnA0mYU)t`*^q14XU(nB0gt;>vaChS}=7TAs<8s&zw$Yn2;Tbqs%1Gijxp<Hot%
z5nQ6``8h=fhXJ)anH3n<xYdNj!U+A^^XXDTQZOPh?g-?+c1HM;yEcT6Dd#P!0hwGO
zw;dtjT-KmPhxCth{QM&Uz-96;YD_8@_AY<#uGc3a>K${@Z^H+cTV_@>mSUDGi3A9g
zQwbnA=JQW%Ga#0amZhTkWES$HNn$<hvmDXe;c^S$%JD2Ll?fj9eHXfqxF+kj1!nVr
zPBx}ewj}nvqXK=wv-rRo^Z&Ed8_=VZ7Jq{xeq$zu4V^5?1A}YyA<<`mA5a7zuiB(p
z3?Nb8te&7d(6mj2#E~gaz+C?;l93D`mta<2^$*ph25V@`!s}`nO!!}st+2*mVRJA#
z?ep=q<Zh0KL1I-Wc1erR+UU{vQaw(vpGW);{Zl=rRiI=#M=<Cqm``gZ#QJw%KLD#W
z@)eelEl!QNn;6X`JL?x|nUJJ<sZvYYTHDmo4hn?*@gaN_vloA*^SYb;i6cZcQ|bi3
z4r)^C`|oIG*<7$9Ucqe*iG7a-TLAj%JSS-p(Ci>LOjI}DPdR(G;aOEAV<r8ye(1j^
zSe=#@NhzvMdkm|VOCj}-Qc39RLajzKV$5N`nvu=VM}YnJs0a1NzD-*#wQG~bb)#Ys
zVmeV%|7Dcm4CWDo)azVR0Mq_1O%lg*Fs@KIF{Qn_AFKo(q~KcicDRiU2!BIU`Q1Hw
zAb<_*d7Y&*g1684k-h*XVH3O%-2S2Y|02urF}{b){Q%fBwDWlSrBv#sO`?erRLO?A
z+H6Xo>NY_e@oODTpL1>elz20vM`Y=_kVbS}P(2g}>Fb}ze7z2V^g3fU1RF_$xJW44
zdKmlwVnGcrSG+!3x)+YITBPP}*qS3BCclLL3e+-_<Oc=;!$#~I984<!hP5LV3>aw!
zGG0L}geOK1n~-(u2j=%`Z~e9|A2hy&MPa2L%w2qnhS`A6?fO1iVeMMO1YIv}rw8nW
z7}rJhywA1Y`sj5Q7iIF!w&CMItbxu4ZwM@7jd?S3zfrg2c`Mg!6+bsC-jc2H+X%6~
z(o%bi9VkEIJS{l3cKnSq=y?*{H3>N!XJb_LZ!+Ytnw!ceraizSfJ9xl-~C37adjC<
zn(?|mAbkI=&$ZL}iGlUk@K1H4ksYHANKe+wQuTig>imr-g*_<2bqmhHDZk;?lvIQv
zN$!l@0(oif<5aY;ioPo<by+$pelT@{TLUZykgYForL$fDiRTT2ZE7?dT*V!+ZRYuo
z_d;lvkRp3o=4J9!Ib7j;@y7+ZHoOTm9O1jK^hTr!@X~8GqcJve#ZsIbE(?ZL-}%t>
zCyeOJtQ0-$;a*pV7lv^SY2SYJ<ksYGG7X69ATPyX1fbz`7d=kN+gf_v`bA~OT_Xnr
zSegadZ;Kv0WRVKhD-;>wd`6e59iVptYn>3_Pz%UX@#c<*&LR8~T>=w1qxiL}h73Lh
zi!SRcGPQKQ190O^v`|Q9nWOEtcm-PKMD1p6HY?NEXwSKKG<O`gLZ(HF**KN&tb20k
znZo`J>n{@4^rNty4NIoL(<+Kua~ZUmMD%Av`~$tcf7<MQRb}b#xw9rP5k+0$v+dVU
z-qW?bUP^?EP2LWb2J-ZtH$5QLq3<%W={qMV8R$Q5$8PpN5<|9tD2cKvbk$M^F~{H<
zvrY+(2?vdTn~QX+5cZQdjdEHhZw9uM<!5@h6D4)ea&({jV{f8+pFT65K%-N=wZR^3
zefe2%J+MZ=)jui35w&NVM1PX(z^@d`liE6iIVHqo7sU|RR|TT6FHx1LOJ1!?;SU<Z
z<C{u<?;YcZLgSnq{L?$0K=V91%Cm;1XNj=6!pix)D%FHx6BXI?-G9&WaWj_?6-N0&
z3&pHs_YT6Fu^XR5-kGLoB#we0)uhUbcW#5sM_jj;7ll=l^dt80+cwW$UM;;8e~?<@
z{5!@UFrvVB5m2g3PD+PN^juB{B0ia7^1H&4J5`i8*N`4t(blEBYhoZmSTD$lpJ?ST
z4F`q|3U`%kp^H??5lzJVw3}uhOM^q0klfKbQiOm<hAkuB2XlV3%jk`5H^0ulfb>?@
z_n$%P1t>fOK7$8-3e_@}R0UMdSD>J)bv96!*{mx!)Fy%fz-vaU<USk<+-DLkh3dKe
z02cs0{RWMhg8DSBdZpt-5)$!0iB~CUFIF}aFhCEW$-s<_@s`rLq>WeA>cbiD9_1w@
zN}q-~IApBARsYe6@~5UeR&B8Ss!?Ns?->+Giojm<Ix19(Idez$<@nIn&PaV9t}yW;
zM+CnjCGrGHAvyu`i~_un>_RQmOCr8iJK=f70;U(r03wZXrP&m(Uj?6^OsfL0P8B3$
z2-(JT<dqK8N3iu}!z2jJfn+K-*PIdB@m-XgdFK0hvcU=^@a9Xq>8Kr~-UwDN(n0lC
z8m6^&H{ypn*;3@!54F0hd;W1-#}>?N8J*PYz4@(rcfn7dX>K|MFB!H+D^P}wEbpXd
z_?W~Ca!F}&<TIYGtN8^l;Dx-KIP5e315oK9O06Dc+G^uU{6k%A;A%bvktdhMk<=v_
zZI_3**^h4wpQ7I_LJFD4)ZNbx3stMF9#FtGG|?Y?c|tBayQX0crrf2<Rx`n%T*Glo
zkm@cH3Py7L%#oBEMVycWoM(dPX)9ASapnR;mGNeLMBJ}XH%BkR1UYd(-Nx8ppwB`#
zDkCpmSrK^d0Zj=a``<zJNWH7qQ3;Ab6s)W|Gdt*n74eB&Z0q2@snpJg6y^;Qx>`*r
zU!!#eO+dS>v6skBU5Fr;$#;R0uFL((8bl|qNTt31E7MA0!l&HG0xTwwL~(m2<{$D5
zvOsz_9$_oFf{%x>Fvn^|-9FErjlrOzZpa_XhcpaVw|eROZ8NlM*XIiya}u8Q4)MC<
zXiM2^D<+CDOtZy!7WmyDoDnfwi5}5<`^wq53$MId_pILc^cjR_&C)69X<<eoF}h4%
z2Hz?HLo^080gH$Rig>sfnM8)M2ee76LZQ1{)fDVTL?};L3RMxa;}Txp^ctawU66Z;
zhi8kT?4>Kbd}`vsWLIXDuR@mvtxQw6R9J+qGme&uZAkM8in&b|K~ac58nLmS)jnNH
zc-uwSOlPlu)v0HNouG?ekKZ;w{l+sKewE-c+zrxowDH*L0niVqgOHC`x(EX!X}F}t
zsgzj!rmLF~?|l)vW^0**(b3F2%8@`jJ(>yJcxk=+f78Bpx6o0(2W%YWqAl1*U4#-T
zMfe;s$j;CJR+`AK@YY^MaJ+{>6k$L-mzSixhN<d;B2VzT>Os9sWVAomE0JAn8%gCS
z+Y-a)3X_+a9wDlLd500QkHH~-h0`AyKwv9y#+gnHl~T1UIdFWy)~M6i=SIf6S&X_a
z{`@REm^#^M5|m=j(|Iw6?05}x062hAEFNYtwl`Zl4Yk{Rs6+EyK#z(o?rUhW#j>RC
zsn#SjqyX11ek-SC>cE{`vbUV4PHV}1MK^JhOKv03zurAs_bJu;3K=PFt!!Ryh=9`j
zv1;e6ssKv)R;R0x%rF;4bE;>6p_&UJIdHLqB>5N4NrA6etR3I)JwAq{aIxuzd_HhY
zF$X9waM1<BiM}b5yeu4VOa19zR#2IMUI8(*H4OhxDkjR<7A?T2(57Ht>_LT+71#%T
z$I>2n5R4hsy2o(CGciQQ_hLVRdhjsoqjan8{{|%>_m3yNsuYxjgB{JIJV28K8`J2R
z_;34yXtly5g!5#59PJs3Sx(PeBLmyb5)N>UrHL6Ia$&u~YPpAi4tSZ_^c3lZqcOV*
z&8`NBL|)TC8){m(@1?)_?qV!PJyfe+e7gtUBqoFH`6LN?F$C75a*^7rGPmuWEaqH&
zp0@X5QY+WXZ15YSh_0{qW4#8GS&Pg0u-NmJ0Y!xmI<M?>J&^(huVwBo$VBajqVAsq
zx+lY!!pTdzzbD8XeottsSQp)l1u~(X9!Nqn_vOe9hwI<-9l;add*Y+X1f%%0R9qmH
zyj#F6#a+S<q3&VOwoehrh|wxZN+jgizo^Ir;Bmng3tH{gNEAq7aTQ|ghXlT^ZnxB8
z{J!tA_F7uIk=JBgv*)+G6SRh1>bbO11MQIxqUg^r_yr;(eh=+!alAziG7QA`gW{fR
z#7(k^ioRV(sAM?ug_*lreq_Ox6uAIWORh!Fg0j=13P3qRHmgZKXNk;7xa?NnUV*BM
z%*<o;AZV13da;6uaxlC5@Tiv2e%#TXwY_o2BRR+EGFj2}QZ>ZK8Z1r)18aQZS#!IV
zK-5!rZ^gy<isz!v>ZUhV!7@{Vh^Z(_eCr5kIwsg3dCv=ws@yas#404~1bgbu)e646
zV=i0VK3~dn)+#71Dgi6?Vrip?I^}>40{Ln0-f{HmJ676lK;OxH0!{|7`7XqN0?cM7
zXbKGR`;!CK`fmAAfVbcIc>*k*bAkrU2Qb&ePPjN_3fy%+(IHSOn1Z(EMJ)d`08$;K
zs|`vX)1y`BI{UOa=@1JJ1E0@H6S5<3*-D=(cHibZzUMq%yOJlVCtVccOV5%tGFlJM
zkmOR)^Xo9_hrt30Q?J0k`>40XC#i8uc_@w5KGfQ4zq|p}Y2KaWaaoL_>Kkk~EvpT5
zhOM<ji=1sBrvx&7@okiZEiICh&TDBs`J6g<RZyLmzd9k7R0m((x!y<Hl|fI9pHm9b
z8s8?0s*Gg#Il-${5-bUI;^TG#-1Te$<1M42P2Dm9se!5zO!}?mP)i*hzJbr?ilK6p
zXtF+>t}iz{&Z==NTy~v<v-oL0uY0%DOoe>!7)|`$6KxQ)zGY&mSD(ko=Ec%gP2KO=
zqMj*gd%KRHldtzTn%K}K)4b|cOLJ)PQjG(w0-+D{Lv<1&N9@-Dg`e?7Qq?rq!NySM
z>@(>c$hQb*eJ}SkGe8&48b$g<6QHbu{F19UrOI*h?^ux8Ka34>j$G<&GMR5)&lZQ?
zW%1)%$lF0~mH1(#X!;UVLD@2TsKAN-^`1hRE+{nuyDNPT7^K>41}4K=9i6OuExdca
zhH~@nyZz3mqee?T$;e*l4Z5K|ej;$4!b3?&rx#0`3HY~GqHDz4;7!HM?`o-PUOrk&
zP(Nbw3&TdmBTa&N|LEG!qyo>py1N(#q4gr+nz3b-V#V7#w*Ps?4)n?x)S1<(OtAHN
zmKZsdQE9Vr+Xdw^mUbQA+zTTX#*5Vz(vvydLWMzi=MMd#4oMeFpD2f<tbt-h1W=1_
zidVNZyGMFCzsVPNG29jfnCiv2x+-1v_XZ>i&y)nb_cT&Ej=`;&Aw2<j*soD2`P&;X
zu+~2>Mutucc0NXrf#e-=dAE3w;h<~HJ3YyQZ8tu?u6bYaj8unMw`>3aw##_Kb+4?b
zT%J;;cO1y0t7``$xH1^fAE9ZXgT#K5Mm8f6gy%F_^wM*+l>>C9Yryt*lxZ7B>Gi_x
zR0FQNR2<*jM{J+Nr^~tTjy0(Zn^LHf&0WBgK7h~+!Y_pns~fcr0*=s~1BSD^!p_i>
z%dSjNFSf!snii6oP~3G+m#Fj}g<?;EZ7U**Ae~@b6ai2#w1dtwL_vT(&NXxT`(Ulz
zIZ+Xf+SX~jeUqn8%X0q&x=Er~W?w3l!AiV4y=_88J(s%`b?wajBl#zrH$pD)3W@0|
zy@coECkh&&k-Qqy*N9}zX8^3{MZf1=9v^NNi4>P9w{Pe&v+0hiCpmsz;pjJOGW8kE
zp8GDLYqPf?j4}Oi%XD$Nde{(FT1c}ePcUsxAfNX9hSo9!=jkQ6fuPN01DT@~W4@@%
z@7?)G3~li}vZmzYq<l|BUHJK6Yl-LZM@i$EE`WNSe^&V^APSW-Hw=C$`V+VU^RVO5
z3NQFr=i2|<R?C`ZZQq^UfWT-RcEJ^}z~=XS0WGQi-vSS+A75h>m6BHLrW5N$$R}ZY
zirH?R=t=l{W>j#tbi=*|;d8m9^!K{ixQ?QhF?scigI-_2=WMvM@(<*01D{8hkh9MC
zXP2m)NdYh6&UPlW?nO!#IEq?08gM%-tH#saD*G1zV3Uo(?*8hh+62s<C_8%8Dw@^r
zS_bGHKJ?T)Y=)HARcf+9>=|iAy>^lGmjOJ3L6++z`=<pwhJ63x+Ur=|fD|b^KgNJO
z@f-M3i-io|+Kn%`c!<GB)&AK=UKWYW*tNxN-GdR^oo-SMYQ%+1G<2MZl?Tn#qSnN1
z_1!Kh_5*S9zjC!zLa`Z6%;^L6Q(49yXZ7ZEArgj_9WPO`W#S<_16?vo@~Vxe*z}f1
zgy#<i@u|w?#*fUNbGEv<suYc0vOK#H5Y2ejWV&l~AhGJ{ZI;An&~g=5u00|f!5Luj
z6uz8vaHK3RdSxnBc#Ney#CY%efFkawupipcc#Sj`D?QmuoFF%xJo!02_cK=A3{!KW
z6(dDaw~l}WPuQN2bF!+J5K8p3gyjF<`&giTm*&UgRwk0x8)UPt$R}u}-ek|tYlaCO
zsNRg97Y4tk@;$|&X>gY-^E-BGY-${7?-<hw$;W7$fSbQA6(S9<#(>=^y|GAB)6Om`
zlNqJ&QIgWGx3AOGGRf%>Ta?{S^SQ8l<7hlteew;yJw8QLJm;N`+tsQFR#;Nmc!U=?
zm#Bt?7U%(~G(eLP352Tns>i{}vRAT}9OhVoXio(ueh!q12GivrRvWcGsH-SRQB=xB
zGp7c;V*?{S1G%O7^b3~6EC4-rtsTj$diCmMd9rPi3s$u3)`k5sH=W*FmZYckHcdwn
zOUsd)taS`PrGM-0Q7}s*ifF6bY}{2EhQ#v!PeU!_SpaX=3%T@73s!ay9S_oOjB3k;
z`caqGW?+9+D@vf{@kuh+p0GbQ6K#29A1vhSHli3ojYhX7e_qjFI>-*pZ%tx`M8_{<
zjLuSU#5!ry8~YXaIkQ96Z_=Y;8NFnExtXl%c@4zCJwbHrLT0*d*y?8eR1<WO@8{&3
zMy}Q`oCSEwsH);()0m$#0P<?DjOe1?6!{wW%`J3o`Y0+0exfNoz(_tX3g$vD23uwo
zJlL{)w`}n4TnKo!(#^-$@U8Mc>+-<IN*y&u$Z=XW^wwX-?wwYJlOztqfBcCwBWb@s
z<zX5?WD977oYMjx9CrjKkJFHJ5|*KJoW)bIC1#g0#W!KaUP=x*y1ex@jb7L{{0n!{
zX5MLmZj%a09XpVmzi{TO2S^>ob~pd3PuD;G673g-uq7l;S$yEL-}KjmH?WyHP@y&g
zy5d!F2lDrneCH1P;n&545Ha`H0iA~$zg$Rc5<u>SN72(U>(_ZSIHrTMOZ$}GTA^5>
zvsQ$jlmoAadDwy*uykU$%$=6PUShIGYCDvk_5^i)IW+`SS!D#+m56e8yM6Y`7Z`Bh
z=n3@6(XVqx)E`xMsj{zN<W(bey>|QXYM2gM0X8fD1c~dO2%Diy<M6>KLp#*d$uZYl
zocMm92&%sWx*0GOK0Y5Tv6c_w7fLoHaD!5|(^6-T%yD<@XVH6P%O^l1Jse3RNvn3f
zY~oVPwPot}AL8X{CYr4Ud^f_{owQ!s6rr#ertq|n6nu)m7t>*=;<|Q)S=kUtUpZGM
zCy;zpS+_4Hs6(b$7d8Vr?31p-6~>DU{e>2J8a-1g-JhssW97Rda<A=U|Klj`WEYh>
z@Bm>VHrKMIqEmjRKw~bn5`Lm=yz~{gvWHdh=_2}JE2C2E%Pmi^x|*(0kApu6p0%y7
z24XiI#&Y7y+IZ|Y(y@@Y(otigVy8=VHA$1ei8>y>7zUCHqBEru6nyVyo}9AsdXU2L
z(-_L8*c%pEqLi2IfPFRb)sY&%iWjU~l*_BtMrI*FU;fYRw8GnDUPoJ*H*9#6TeR~F
zR(G7!IdOtrMG2alJet{N{!up}!UW1c5-Jn-u8;e04y|R51YAoxIe3!k5$6$8?z%iQ
z3#5m%>p|{4`{#U_n2{e7eU8cZ8$o(;bvNWDBblI3#zCYSTDGF^+uMMw7~!PJbyQLb
zq=lu{ixV02=dBDblzhlQdx8lg!wM9w0jlS&e<$fsuScl3F#D`Nd_BPB+~uFiR;B_c
zRpO4VVdWl!AnBE&m*Ja`?_+G$ir2RAYP_=e2<+9UG~ZhaIQz=6yFXqr*d1YP#<4S;
zhzxfMurokpoPwlEO_u=;EIzz+!(zqS@RHOH)?RULba(l6y;@<X_k6}FMq2Ne1A1b<
z>{?D(fh<>L9DpxxyA=X`!XtE`Ap~c&H3bKfbS+MnVkP_vNGmS4Zw)RtqZzGKj%xTP
zmazpUiHJ}<i{ve!>&}-KFkh<eXjn55obTV)_AaxYQvdaApaZeSu?{-nKkWdau5}vW
z!QCXTDh1yBly&Ix*5<8djcl$fGJeG9U=fbILg`(c<VTSwpizW<a<ERvtBUw|kT|;f
z6Ej^I`$#7R`EGU|)A@ONBDy?}2C;NMbx%79K=~uTWLQ989}*3Ngo>|F{6fRW&Z-q=
z2bEE$hH;SLwH!(5XU4%u+Tm#e5bbb|6)t0iiT@q$WR^peTjRx+z!6Q7#bjoV!tPDD
zNvO&F8Z!_qsy5dspcy!d6tQyq4_vVqeXbCBm*8kl`6P>Rs{e#2%Z>?azo6ookG<rq
zH+z#sQ8!cck=&ZPsDkFTda4zv&8><fkpw4=jU_UwxsXnr`DpjeH=WKF<fKCtdLKh-
zN?<aB9N=w{>3HllZC_QF8#C`i=)RP+<bEo>OMle!?b;pP3os8b8|y^4sD=y>*eu*t
zDm(v(Zo(qeW*nvl)h7Jo1hGd2l9)D4VC~$?k@W&osV5qo)L5YZ!t&@4^7+=$n;BOY
z^iq$OIX?&{qFRx$pjfuo5`#CN4vz5c<=&}KY!7D}Eu%;pF*{$hSOWGHo?>qrd%`Oh
zNrKs&i3pmKl>Vy5Pavn#^GcGKkuk1p*BL0{uU0i`XtXg)l_qum18t-y-DxLo=Qi!-
zxTQ?DG_WUKo)9O;Tx%zHOM2-agkcvcL9Q#)#7jqB@KM24biFzpgmL)m2mY?s1BV#5
zZ3Qf@Mgp^04c5?)O%JV1%!_AZAb3(oF<PAt0=QWyW9Lc+H4%nRTm@IdwK}ht3aX>U
zQ?xOs406k_(E1c>{5Y&q#3U47w{1CAvOV#86HaZYnh_gdsYGw^TfbWxgO<Jxs9Nw%
zKmafJVCnk&@h4+-*zH&Za$(P5y4|~-xIIR{{+ihby}P=5Ns<VpIpgaM#Z?aF(Js(W
z+&cRya6-*lzxOgZqh8#J(5?*g)We=TvQ|>i^!x*Cj=D`c;1bXg-#!*yftuaD%qI@N
z^iO`&V)2V8B;Q*B3rwfVx|L~6v5#J*z$EVg%hB!y^mTVOU47#n0ljFe<VaKiR$<P6
z5cI&Kfd}V_t{{+(J=cl`A-Q8VE{^-_Vg0~IK4!JTCM~|q03;gNCWMEdmWkR<dtmCB
z$Q34IY7Tg8UhECPC{h76g!cuJEVf;rVz4?*8aB3R^H2xB!Z3GXlE(`=`RI~=UsrRN
zdcv_8{el<UsQ<iz$8Eye6Tg3#Mhy&b?DTiIV))&;4vQ}`t2BB2JuPa@%iYgPU4#9S
zXJvxL*FLR{CeCrJAj}snq4$BefU{&%ki?6W9N&QV#ri-aX%T3C+C#qHHdOB{oiReC
zaO`6XWtRqLp*2>k4K_MHtX*65T(8k9MvCO7&ZVdnDod$sxNB7yzHA`dJY-pgeIdfK
z0pTr4uO&|aQ;_jqJ%GhXLtXJ#tr(}Zd=Xs`o$OJYe|C}Ea5p<9kyi4lMibu`^kKTE
z#}6|RwN1}ow!cLX`X#8{pkFCOjx~rE`pJN{D+IZVY!PR4C~q$s9ufC~+5M*M1<rX{
zvqzlZG1knNW&meCPfK@og<@P~Ftj?L9x6^u41#JgUbN}{P)k?O?TbE4KWXI}FoRtm
z=(NWyrh&QlNnVb3v_yxLf9`fvT$7FG?L0Q_s=alP^P1!LYdVPlJ1+yfPaAgE3$blz
zXw&rw-u^cX2`HQ&MGGVL5=+uazGB(|>$(3)x9^J}+I7DXXTT-K*TP(&&Z$+9Yy$I3
zLGuHpX+n>n&fJ>XJxYX%G5=#7MDXNspWFNvBD0AIcp<JdwDk|^L3kksAa<(St_%e4
z@8)h7L%R^!Ofmd-;f%Du3>JQS@%}L!Y=4@6e_#)>ubvp1L931`1*Oas$dbbFt4&`2
z(FtFqS6ijAX>eN7{UPok`=$|TQGR||l84qoF-ep5oSY$0J8+<uw_qvh_*9B8x=ysp
z`HJjki}>IRH#PX+w+)yOkd|Je#W!LTy@X(5*-TO97lX<u=1}{)7==l+n+1BwPj=dC
zb6*qkLuF{YE`FYOMpoJ4U%$ezyDFo9smX7TF!=JKI!c&>vV`fc(|BJQ0khH-XxtK=
zwhv_wy<ia|!Ma#z%UdOcw&Sr|aMigB`AwE^t)&l+%Ur@v_R=uvXgPz2W~D9&mFaK8
z0hO_t?`WuE<g5n;bEey9Ng~IPvNe{b9pMF7!dt$8RD7pK+s`Y^9==#i5YsRYX>iJe
zSyA0#B1yDu*n77{@OHJlw`txeB#tcHSRooG@l+eK)OjdPc!Wpxg)4L5vBf?bcw>32
z01#K?jq>$jt2DzCdp#ItpsF!9o$HAwp@pNwRYrJ~d&FU-FMvAM;ncERq^D(>mHXL!
zJ`uaLt$4QxqkWlr07F2$zq28v0!EIng|S$CxAzE6zoZTBwdyh<I@sNw%rGC)7D0PU
z@+0*mVVPQY&bmZR`5MQM8H*`)Ise?)s{BTJw8jGpH=1*z&SY&uWMyBa^0F6K<9#}S
z4`w$I2I@qGF3Z48*Fo2&`c6qduAtS3%H%7+GPkFNmD2<VcUhVkg`^B-io+&i+52|)
z>oN^a#w&r6!LhFnsXvOe{HC~$BA0?URUm?>pdaObtqN0Lfyb3pIc+}{!i-VC%`v%y
z)!jLmcD_#^4<j!EW%Nk!GOGyM2#^PV*%eT*ICG8M_sE4byX&bnzbQtH#OaMMovH-C
zH~_ms{)|%rAl-SN<+f!1mJTl%p<!i?3EQdh{FC|P?)|R#$>^##(yx*6Ch{%6hEk>3
zKws(AqF;9SlnPmQ{*rJI0i%xK_4J6A&)gSnGhs&Ar1#(IF14=)kR$Oe_bFAFEgn`Z
zc&2s!Y+ij+jvD<%4V{g=)ccdtDWtdZ1uyx`+p*PmSDx`2DDuf17?w;eaWX(W$-pyO
zJ&MfpM?34B1RWs+>~A_;p#Uc)D!C=)j}cwfk#2srWDT5DI`HPxL#4kqw;i%3LvLB`
znS><6puYPgOR>x3jxz>fEzC*pE|7<l8+U8`<?CI6Px{ZUlsaILJd_>t&O#ZzudGTL
zb3UmUO40%S8-`ZhuGHjgOG_|i>jE$s2sW|S^c-ixD(qurcs$v$^aSVQg)%c9Y3%sG
z`T?P?JAs-t)_{HYq_ez|ABx^)pb-5NY8h7@^NW|7Te8z7uvng`|KAEWT&5h8yI)P#
zcsCe99D@s-2%=*M+(xZ377i+yfxBhAnJ}Aap7=w6uD?l%2h*kXic`Pno{yyHEVF+V
zhr9R^0F5cPLlZ)BFvY|oJrtc*Zs@ws5tA>qdG9Qc|7uoMrk&iD0#+(F40Q1-NVkD$
zSB)i#WPOT;pu8X<!e8PU_JFI0=am?IT~ZbVl5(7e%Znk+^CI{XS)ym$7yU@kzd?z+
zp*E??lmdC~RcPx`0-6~`$`$qF*Z=;%QS{{3gB<vr<??8zj%{_(BqYAzFb$;V$pJ-v
zAxp9f^iUpw0%ea;eGp8r;xxjwr)f)Dvm)91>NK-<x?VXetD+&QIAbs!HxALSSe-LM
z;5zJoHG>2_>DhOU<8H9r=~|$bqb{*@t5414H()#q)n|vvQN6JCT!%8b11S&CUEYzU
za|)&S5?zo&)!x=hA|D$3m;ofGb9X*JpOOMkaZSx@G*=`^U4&lnzE_T+RgAw`p)&X=
zhW++84xh@2udkfRzbMDv78#?x7mg@4!X^g@ee19?320xC1sh};Xf60VJi8S{|7$=7
z=_m$)a7^3iYP#2cKz_`04*&dNcq^>y#qrhk1x-4=s*MfOWc;VJ3d}B%VK<^MRpkqV
zW<W>XsguF`ZkjY!8U4D~fjKh7PpBxNNbkf~y!h*^!&JVGS8XXc?w*W3?c_Z-QDVj}
z%~L4#Sc?eS5hW(IzaIAU9Z&v7E#+vKk_L@b+JjtYxAq@?<S$u&2?i<yFdqBwdRXK5
zybrI}WJVB5MP(N$V>~Bo-6-po0$48St<7wo&L>5U!wK-L?+#<vYs3+6)*z<bHpW20
zXa?p6y1*ij+ru=|XC(56E}0j6s$ytNn+W=zmM??0h}F%G2>4IY>duONeF@&iuwG1{
z^QUS?5=pbuo46KC!!BLF!$kiJUna~8whlp^eh}Oq%?X~#ADgo7us$-J5B$&F`>T{M
zah36?+VKwg28eYQeG3QUThAVmFyBJMaFS~lxz?t=6<E5s?!!jJgtyWc9{XX4IQCw>
zv_#GAT$p}Cg-vAZl%otfRX^2o>0_GZN=Ex9=|;o&`k^fJ5a?!yAC^E>A*gxuYcyZ$
z-BOvBl(ruu#7b0P*$W`XN%MDLrCm>#22r^V$zyC#wkY!OeBy_DTqz}83KrJyN*!>U
zxH)N+lCCd^f72VNr`%ucOLQe|b3`kWzYppK;HB?1wID~im?=o9LuQM6+jK_{Hj#o~
z8^C|k$0-uv3PV=AiKHr+c(2!Qk%=Vo0ZLt>^-JA%UN4P(>GbUjCrJ~W5!7LhMt#O-
z#dOHoabfRdV!qdJuCOKsV8DJ1;M5V2_VZhRV9Ofrl3tbSd087$p1;o{#oLF6HwmlQ
zsT&!y1-CQDMnHn%fAo06Etxtu%0?qMxf4W@DqId1QjxNS4~xSrHhAcT+9wkAz~gTP
zO%(=BDr=J&HgiY1wQ9xz!Ponj_K^MZwWvC)(9@in|F8Ga*JwbEm*&O$P)C0^Vtgy9
zHzJ5HpRhN>(Pzja%@l7i<-c5&aA8T>>HOga9*`5aW(-5i5D<cP4VlBUSUb-lJ_P=2
z#gqtrWYo}|IXkk#+JSG<t!6NVpu%dvmlU>+W?TFmSd?FYMT^~DFyr0iZy0_0Igu&u
zrRx)p4eg2PlHiFv(b#-4tHauh;KJuNz*pPODH`Q{`VSpr?Tw5dAW)D4yZ;kKP5tor
z>ULCY;7w@rSQl3RqSE}54Wu3qV21)2Qe%s7y&5$646;vWkK8|~L2tlBHl_@OxiI2d
z&J)^1*H6BD7XlHX1u$i`SO}e-0(Qi_Rq;AR=Q{L1D6@hqQb9E(0SSSR7m|K%%z3`3
zwju7K(R;f0q8lR9+<@**8kvRCW47&H$5TDETx4~XvtoznH@KT;P$0G13x%6HQp#JP
z??NF<STxa=`8{!|KnyhdpngO-urKE1yJI4|v$MP4hWTF}J(({xbMBm6<OjKy(o=|H
zM$?pE(DT_@(I(jAujVtqRW|Qp7o}Kj<lPzQdDh?(>);M1f&%aq+}LT^M@8{}Od1E-
z#CV!PJprL{O6XOI70iIIGTu~^A3a@pm`b*1D#I~-_Nun|Seuq50sYc>7~kVLpkj#|
za_h4DE-wgzM^5%_?Q?x|&Io8YQY*sVyxfC@m2AD+@N=9A6B(smaJeq{-?#HNb5(Pp
zO}iBRePGxSj*CLB%T!UgP|rtixM)*|)vGPT2D<wDcF8WpU^50tk>0r9d!A;lqn8Y3
zJk&u^(~j%vP?iI`5i6J2{ALXU;$#!#2g43v#pbWYLIlqc&ugo+;b@$U)N{y~;9RL?
zp7qAUkl*Y{XeW%p`QK{F88J5~HF~Luit`Re9Vnh%vs43n9p9A0MEI2w;hYr6I^zg>
z@Q**4nST7p*GOcf!~mOXs4L40=*Q93Vfm467@Aj15=oq~XsQ`Dme&NlR<Yh4h>F)w
zgMLb9&X0^%d=Pz=yp_i2G18KcuI-Ey3IG^vmzHdauL1#~??S74Z1?%@W9HZs0?aX3
zWZIP@EHHIW>B8zIf-Baz*Q={%$wE7z!RBbwYPV7VD;?f_><2tUafi__Q$6VhouaO?
zpU-#nifLJ>fHa4DWGNGa*AAvU+4J|)yEhgYECDDC;_Djh^@yX}8iQ=MI*yx-Vc8MQ
z)QeN?c3KNd>t2>=l%)2^aB7YH)~f`EAMfFty;C((9=bLy>*bO>m|LP2a!<5rG_zn#
zwVbW=4*U3Ew4nVbUVi$30Ae4xsg3v|QHzi~cyVx#rB@dmm$S%u!>&9q8H%(_X?$#k
z9pOPe&LinOsYh}n<n-!Xvb~hSm_r$_$FIrj?G5C8nHjUuDeY$$|EIrDB&Eg(5N+(X
zPJpFoEN4Gh6>Y}xe1g@di%bD#fnKGE8rvs?`G($lXd)D{KRabohPeFKQiAzscs+af
z^F;COjd;Eo?-_3LV<+0az(_F7{R@(O9QJILfuBv-<lzk~86E1K{vsqmtjv2Haf%yG
zS#fRS`GYxOMyIEO$*JVr5uc`Pq_wb|OLPViy7>wsdhej+z@v%6HtyH@-IBpxe$d@*
z&m~AUPT{r}+s7u=E)k;;n^(}`&-0dOBM3P!HE6Xj3JGMeXo8q`cyIdp)L@JxI3in^
zU+AgkRF`(1v85{;-jJNt0ovPBRcW(59%{dHl!_A_4LI&;s)sDI!28ne<Gb+L@JK7v
ziHs;VbE15L1Hy=$IYAxLus&Abq%S_&355|!k#wEWEMqbQ;@ddE;!)zU!C;y1>ie=u
zY8v23?*VxRH7g`=Y(#NBJj}%xGq-&D+s2l^>E&_ZqQoXQ74dO@o}QdL=ltdOEc_9}
z-<XkVhh1&ox-^ayI*#+!jlvNT=56~kYp$TDB#_>DDQzcs%}N;7G=KQ<&amQHgzq54
z*^3i@S8=WcZt|)skV#bKrcRZ#t<u?)=>SddC)sfXc8t<DjOpT|sPj8G>!)H2VpF8*
zjhaEN|0KS3h{!n}pq~#(sxtf!6c@gGG=F<X<Kwhb;>I9(3^Ai!N{#s)aW<}N-3Frh
z4}|(2DZkVwb&Vw^nOJU@@b;3*j@OY(GHwuSX{0OI{NT!BD}j_R@Gv*a5e9zutOcb|
zR3vR{(PTDQjFyLdW-|@T*prs0gI{?3mymhhMR}XS*Y%n@Gl@s@caaSC^fgC|ELR9)
z3%>r%g)1<9zBhC(eDO4oFH`}-0HBVKbjN2K1xNE_+e~s?xRDqm7!9bk!6n{$1IQE%
z<l<LKB^gcWD*JE4Bz77WB^hHp?tkvObHak2f#h*y5P`8%40K7Z(llF60J>9_XsA1;
z$9bse>1jkZo>8a7?RtxPr*(Umi}mt}dp3Nds!l(~Ps{?H;FeQ?1!7gvLm~{6nQ;xF
zFI!Hw0C|4lAVmn$N5#=p;AA}+j`Fv-^!!sm`EsKAm5J}r7iW=39=gV+v~PEsZ}^H$
zEAOo^Sbh#R34zZ08}41wPqDk&T~x>)X{gYQQXy%?h^KCwE0fZ;S@SpWVpg29_!1j1
zA#-P1ypgwcgloX>gzVBfq;Bv^J|M}OZf}g@T3d!pRkZTnZ&#mnlB~go`~9h$R9q+{
zf@x03X3%ZT<?mlHXlECmspBlvtcu#_oK&3@=-4A8&FI1QxMqFFjYQS##+`Ft*!LF0
zsRv9~Ug34}6q$&6;vNeMIZ)tM9Ff!-MFJr^5JQHdqvU;d-i)Ss+C$o(Xygi%pI-9<
zQde{ytMlqEQqPhZ_}WJc41Ng&GyjQtI3lg-XY7sGP0K=Kz>gEy9#cN)tTYI9Q#;e1
z*Vu_w82JIm$pt-UV43I;`q`tyu%`_AoiFGvF1B5Xgm*Py(7_HgcF+?~fi*DFToZ})
z*2sacD-xleik^Ez4o~B5-KJpu4d{U9Vh(S$v%l21rwx-k-rRUTcFEN`h;In4eE7?7
zrAL(1&6r!vI+ns2NNkY;X<RaR!PB)pK6lwV5EvrL^z{eD7SuwZK%TD{RwX_$vhM$2
zRl+hGMJg-_xc51p^ykg)*5_GLY|ZGQkg>`FWS-xbkCIRvaa>y~Q-WZpK=xV%vo;cy
zez}(p<cY^bIczS)p#0}3RRC8$fZM6Lh<Ov?Z<YKpp-4Pg7u&V;+?Aj%cK)|cR!|Z4
z24TtiMBWwaMBXUf$2)yZjuY0I3a2gj7yyG=XBnUHu-<B#v<mE&gEB6hS&WG-h(?Ls
zA}MtY<!r7aP~Sk?Xb||>J+}F%R?|rcipruXaUaIj?Mri-cfU-ZTFQt>zCj$*Qyk1I
zjVLe;CG;*2j<qq@5SJC8td`JB{6<WQB>eTMw-a8*p&KNyu;q(N9?IW<r`x<OYG5a$
zHadejd}R07;EcINXakTPZ$bBqAu@ei0`NbU-{X|LU{5k>zT~eRa;b63%m_SOiY#Y6
zU?3py(3y6MnjWlEyzjL1y3BB+{Yh?h7vA){072|&hIl6atWssNs~kQ`1FHrcXpz<<
zA2q)jOyo;IXq^7MfRbC>;=%B@Ie`h;|0UaorO?{OomZ*L$EY*{fOYSLHMt_{0xl3z
zi)s0dXmjS$<;1vVrPmry^UFQ7`rS!U26->`QwxuOhqSGVbd%R@iDJsdhkEot&LW}+
z0ezu7ppm`->I-ydr28McCN9tQ$=Zy*Koo#;Rb)rdqR0NaMzeL1h}L}4^2u~wh0|+w
zSr-LkNgtjt)the1`8m1A!L$6f;<R-e+N0lZy(}%Oa{e#yGOE-mq|<sbO@H8*m|mNM
z;0ahp<k6$WP)q9d14M3l*$o?q0@7r-@JC#VgVThvq!7qcP*k`a<BlBJ*pQPEI3>(=
z?g=7uc{7QhD2`)oDLUMmM3GigKPRFv<W!7V_e@W_f78s5XV;gG`2MG{s{8Qwd=KnV
zbQ<1v$rf3&DzJdr<G>~b<JgLrIxFr;#cXNR=4^fsT}%~WKi?e0A}gJNkCh_gA@7#C
z!uM9pnp0~HflJ^{1as3>4fCRt49C2v>~l6Fjuye1yzVoC{?MCm<tdzE<X<gx9r-b|
zdZHz6b1bkBk#J)32%qM$5ol_SIf={Hb@2^RWc>a`X(Ycfw_lgov;^Xf&E;N3h{wz6
zMKIsBJ35dIMLM9A1Hu+r<T!-$<9y1rYIJ@YMY~S9%Fsf3+Hu7F{z!h|kkea}@SRBe
zHCZ^^c@b8?OdHe`VZ4>y^7#&Cw+#gZVsrtVO}GFgb85$Qup!P@uH%<t)EWEFG7vj3
z*eial4eTOgY5tD|RD+yP1lA!4LK^HD1P(H_>1w49>>eKAw0WKC!~Afa30bjq2jkz<
z-Ip(Pi_~`OJ-W$4yx>7|%tHMTggb<RA|WWJ)rA@qenPRtei?0YDyM>>(gkwkoHgUy
z;Da-$!)~{Uo4Nm_$~4&OJOC4SR(x)93X$2cQMM#=vNMUKboQA&g#O=2xZLk0qGRAg
zh_r$j+k<(90+%*eQL^)&K^nbflPlF3rSbqW?UFz)&4|+XrMbz!&&=?%*e%ed+_2zz
zm(jQS$u2D0$b96mTR47(w}9c0J%g59IMnzTQqdJ)q1bG?-xgspitIWeqIi^1yP;Iz
zq%=@c{Vs7^qm#upHLE?_&pngSO!SUw;@7B?DJ@<C!%;HvgBAgeXYi64!SL{-&v34P
z8m_NiUJe2ZB4|*>2;|{L3pDcd!Ok=1T{C^oiB7N+`$}~Y0~U4&I)EAP7lc_EV#ewj
z#+G}LQ0Ra9w~=#S?X)|pjZ_UrtM{H0Yp1fGtglJn?Cx?Ire7r%p#AN6P#h-MB%bsb
z7ZpMw(UfzO#yZ}BafQk#o=y=Wp(f~Z49{`7F9OF61Y<>S#bkQvruQ{MbDR4Id>Ew^
zABb&DMaIt~7p`OVjc9sl_XPbG^OEvyT&{=akE3>J?lI;Poa)0z!*ya3U-hJ!@rXX5
z$9);qQeRC9qRPfVi7!v*JSI{F?ipyz%F_c4p4ruiXV-)m4N~}9<8WQfuo=m8&o>7Y
zD%9FlkhgRF5F>Ah#{)`<bf>@@y^UqJ8+VqzfiQ8kTYYbh?#q9Djg<_|N_W%?f;9Li
z^MzTYjV2MN7TwQ)BNSAuu8R2YIJCZ25P=WPf47i?UR9IxZ5co!NS`njTZ}R#Zsj;P
z632Hj=?&LYVlsLH$x1r;pj&&Ahj4@s1i-AV6mL{0_&8c|{3*C6z~#qU!~lkrle<i7
zl2=R=Au*H^gz{0D%%j`Z!<QyNs0_BW6v7rj4f$BbPA7dr{?VvVKg&+RgZmGl$ts8B
zxU?LvQ=k+zImq$hj9cY339K?&*q;*rzAR`ihQh;x9R>y&Sm~XU1zBP+qyQ7&mAe&6
z0l9fr3RmJKVejff1oiW>kNc*65?i;g>NIC-BK(h2m$7aM7S}4YxK~rL`mN$~--3w-
zF62t0kj-p#%2=g=uPf>y1r_%-dtyKW%b&Q|1Q>e#lf=7xp>V5Sug(JHF=Z#|oqcT;
z;fz)@scwG4b!h^)1K$=p&ok|CK~gOQm>vB6vQq0C)7^bQ*uO18?tuUIT=@ljG?=&Q
zDIbNLPSGJyEgOc24*}TOpE)hfOO}B?sfR~<%nk&xI75EOr;0FPLuPvU$nx8Ma?1dT
zMd{bk_|0RVgn)Cuv@)O;e=pD~!+m?&YGAV)4_t^y^?_iCA3xe?5Kb~?MD?06f=!pT
zA$x3GH8m)XH!cufPn1%S%3O6N^IR&452X27X5r;<67-{ihn?GslQv3g{s?z(T1r)n
z90|=cK6bF-1=*u=*!#>mfLVIl$5W+-i?g#<Uw(<3E7!c^|NR$J>mw%`fw@tZv%FGG
z7{&A@go4haG$Td~zH}yl@Ku0p+Q&WaaNuv?C0d=^f1@RGT?@ZwYg#IqVg=IccKJG4
zkQ$jH1(G+gr#UD0rvaN~j4g#d+dBTACyDeS3mWO9+GZEE{&P(8(dRPunp5Jb&jbJk
z3~{hVP~Zac6e&aD8eX(HP8u&hEP@ZUObq5ToCbOnH>>3=PU30G|Cd_*)A<fHW?#vb
zee>(x9T(uZ#S7@PAOrUOW$OtYYrvwS0@m=U@zg6-k%5VHYA$KWf(+~l<4DFL6iY@O
zFkLAhTLFGTmR3bk79kg9g@*(6X&Qb9)@lfKk;7WNS0||&*`N+rS(UIORHsGv>J?!_
zDh_eKjb$cKSz>7*ORf*q!KaBjf*p><!1Zz_UR-EX7v3rY3lB-ezgev~34REN&<NZX
zrgsX>_0Fm@kS_m)5|B(RHXoY23syfVS(SwzF2vvUmX1C|)4h#1*aWh2O~tfxapJJ8
zXBFetqwRj{1eoE=a4>}Vx8b-)urg2Ugyd~tIfb-I{qPhMcwcSk^@|E5h{aq++mDm6
zzRE)?(jex)1#QDO%d1*4_@C#Hj)}n%ABYJ-`vokFK4a)zcHkDs-(8D>yxqCa@2Gn2
zn<S~f<vDPAc_(U!1vTKuKLgrQRXC?Os959|UYpFv6)F+BPQ6&FMRfpwpBL1uZ<ABA
z99?zyth3R4-_itzKLd#%uW^&1gV6{coE3Uo$Y12)_vLLVbxnPb7=9Q3+Pm(Jwc%}I
z>bL<0lFpB+mE%zoXhY};DF+%%O!2YO^2er%SZZlD1^^j(TxvHA#ui##c_%3KVGESw
zOMFgJFQh#uYv#HuPlR5bm%*;nrvJVK{%kr<1sT2Q+CS>?fFsk7nBw%};vJ)XrK0O=
z&v4s0TjwA!!@tP?!9si=e~0!Uansf4FvEheA-q41jrlT`p#X~f1U^L8@0Cx}IeFfE
z)T$T#LQUaAL2e3$%s}9;VNVec?>eC!NCaei&sa^5)mewTac>P9H_{@mw$Kq7O4TA)
z*Gvr5c1RzGdp05JJDVO}J5K5|&{=!t?Nm$sO2|Hc9X6K9N1`pj0kySN)z*!svhuMZ
z!Mlon?1`>~irzMKuRSSv)Cj%=WAPj&A_JqBxd)GBTH~|Uh<WQyZlj(5P3J4HQWdyE
z4?z0WK8GhWtG=`TTP$I2VCg2pv-X@OQmZylu{iC`nbK@FT>|j=2)dvS>j+yY)we`m
zUAi#+f>94~q=4jP4+(r#F8ou^hXg&^exD*f6oyfM`)g&(p>q6sKM5mROs9sHPSIDh
z_E*J-3)>Xlg#jO63CLY$E{+HbrVX!`M=~>lYbF~~3YQj&r8n1LExoRIE9JGvUFiG_
z7kH5!VxbFX%%Si~4aEnSex8B(64&{tU$Qa<!k<X5R5v-N(7tuz6`GwFmumnnuqPv9
zrMTGYyv(-%?fMVePFMz|G7Zj5<CPh*QZ-6I%K=a+<6z~!G&a6ewb%2Em~IZsg7mRk
z{To}bwRGSEwLR+MQGYFgv@DoOTepU$#GVYc$?uJUv9y?Yp-xG(k3D&!lz8Vo?-mJe
z@ok(;g*BHJGm0k8mgy|~C+|(N7!`-^-kF-nqSI^ZEGh3kFjIx!#uGJJW+6!@@pkp!
zZ^mKtkO8_JBH<#0K&P5Nx%}&nSOn*0%9<A-7j=}5tD}Ch2$YmqYO`A<Or7>~-MbZF
z1A;+y#uSEJEUKVMcinU@e;7ae>LE!v9Ht21&y?ePs*<LXKkh0l6R?aX3b3+HS;?H}
zz^SMSW~CBb)2tgjN9CZu(gJvXA6^kN3^uBkaKIZ{{7yUY3Q&i_H0Axsd~y3t)qy9F
z7b(hI8x)t^Tgg)6PETW;h*=3(T(fq~8?o}$_d~sYWXR*M&yLu_s;}k#rCp}|2SA$2
z9sH1t*l7~z;&;C`vcs1OLEsFN<Ko@ty6P^;^tj@-1PPYXOf&!#$$!|_=O66n0qQ{L
z@FOcnpBLwVUtSu*tsCgl+-}QHViL_x5*S3vKmVzTqC;9(7x4>jQkNovGW=eVZ^*1~
zhwof1(DMok*X;bAb4GuG_5?R$xUvE113UewqMN$Q-H%nvE&c(k4=M7anO8UrGbDCz
z>m}ANG~Dn`Y~_zf19Vo_ZDKmjh{<*Jm2M$^8B2OTuETFPB+QrgxMu$+$I<nR@FF-G
ziLTpI6Y}u|b<jy1k80U62Ho%`e0VSIutvD<<Hj;uvE<hS7~#K4#dWY(?-{J_O5Jao
zuCbjy_dKi3KGn;AgG2)-Gv4!>H&uD7B|Y938O7c#eN5k7$s9aWp)jSiBIU!rH_P!|
z*zc^Ni8t4`(|ODu!FB-NlkMh0vwxoSRf{~AuJB*w4#S|0VMW_T*(}fcUlAZ|BApQ0
z&^RrWJZ#{S_lj-`h({0Lqb;c?A_}8IVj#?$Il?2Jr%(Djj?_^pJx(ND6u#$Guf!e&
zGxXm|`tre3E5ol?0Aamz7qsd`pzSZ&19Rmg+X<E^*?RXzJ|4hk7Z4H}hdC{)T6-G<
zE4Lhk!(YG;?IVY-^cW3QU%+pVMIys7WB1qGu)cTRR?BiN(~s(AFr0G%6K@tKjLd|g
zw|Kn>WGq6KG0C2UhG|*TDr#HhH#uU~!1<HY3|{~#1uPbELDpZ{p^DW9+lhXbgf1B%
znC>qi(TnitkZR)A9$kBF$bXnpS;M<14MpoY@6L6Xci>C6J-^(87~VN4V$_AIK3}lU
zIraO=_RuYu``#t8>wei&CZOqdSu)RHN>cSL66UugT8iZbra@c{@mCy@0Iw1cov9>_
zUC>gcLoVgpCf2Noi%l-_f&0RbR-SMzW_z=8S1y^kK2oH&=r9e}Q*lhsENvTI#B}S7
z*La=Fkt4_M2<&BDU-v}4^^EW_N2wm~6vV(LEm{kZ^+Pn11wW1bhmBLM>FBDA6L}pe
zT>J}tNUlkhNF$WI8?M-js~GyJv{d=fA~-vOMSH{IRX}V)XIMvU{w`-Ou2vBLvvS(Y
zK16Ud6s<Hkg?e=_%2t6TJwMa24JFPYME6qePTxbB?dyZx7FCj*pV%3&mT>Y`0}b0c
z@O3C8;B9Tk%6R0>i*=4cZrTP>vPXAIsn}NeO9yuQ$up*h$Sq)ssEt2u-03C^u2QHb
zQ}i=-XmcQXZS*f(P{7I9e$7mOtD*(<Dt<boHQM%0i6`NZOXBu3flt;om-sym2oCHT
z6eWL$@n2&bFKi+FRauiu^|@;jx%<n+##5vC79B#_aYZ`yE98}jm5uuv>iC-yL8gAW
z69dAb%?FU?V+F$Kt2CpU>TI4SYFkfKM4MR&$8+g(HPC-e>-#<FBv^8lAJQh}Cr#x?
z!h?l}%x-NR&`M#aJ`)^_{?9SbUG~`5P!Bf%{yfd-{Zko`l5%@Zlmp8~DF5t*{c10x
zdS6BeR${(y$~!PqXT#I*L6&M+O}9z#4Y(f4rU->1CDcED2v1Fyh?rAmR}i|YH5Jf@
zrLJBI%{)qhPeQ?uID<ZI{-{|#q%1AZz;p#JfPd(cp{3CfWARI_t)#A(j#kRb$0rUV
zKN!%=fvkqBS5ZG%QzH`gIEOuATYotgE0MDpVe$K`4}6Dsa93p~7Pw6qU2v5?@=1rW
z3YQUiCo1AiO!DoGReKTHCCju*r>{{c+p1YXyC&N5d39P*uZOBv<1re3&Ep@bDlKp`
zh5dFB0A!+PDD+uuETVpp0yS38i(KRw!B!vjglZO&&4<jq>Ru55#Z}uy49RxD-z8(y
zmdF~!qv66;RN5Qp%v3>v1H1fQiZO0yPO~sbw3YEAb{Ss&ee`P0Dxa!{p_HC*TJ$;n
zkFZpG_4Eb;)YZ$6oQYy4=IeF-R75m#Y`KCKUfkh4{NoZg*wCO(#loWctCluin{GLt
zQ;B{513sFeAojT1m<MFc6Nzi`=B9vtVgcpw8%WOsN-9qAqEA?5n6z`EMXR*ow0)Be
zaFQz~*u8-~fNv*4?>lepO`yK_j7C1*?7(K6<nieoD%rAqpomMbI<WaI6Rpiifw<TW
zi8w{+rkP($t?;_c0)-Jo-F!XQb(%8kxrfq_@8xXlY5L%N%%VZNNZx%eNY+#==Nrq7
zsdn-I<j%;GdHnkX=V$s&#NI<uqe~d8qxM3e?kbH5I(Aof16vQIS!{HD&6>}W17co1
zzE-~S2E_jtU#N~@$OR|jhso7BiIS?DQH0;))K*H*V7esbAy0W5br(Zv_?*`|z0z{U
zfpQu4-rpTgD-BKXPlNQ9FkNaImNS^z7S)!))7v^bP*8dBcnKtSwTX-47sLX=R5vA_
z%1Oa{mC3TE$2L*yal#LtX9QG+{rOW2Jz*BKfsJ*!u0dyNsb`X`ijPabWrNMO45wmK
zLNyP5FuzqJE$wCRNJBmDJ$N_6TaQiKydXMUHMQ#OdGt9F+z@Qh7IQMqk+tc`z-F|T
zg`kT?WayWe6t?D8+A7E7-YT6a1Aw;HBgXCG&Mh18iKb6VQ=s&pFc(x@#O#Io|Jz}~
z>jk*d6=kWIImHr4!&Km|mc+DPZW0R=y(G=RQHOQ`uxG4`m>C<Ie01}shEisAEEtgw
zVLH)C;P|(Wys3Tnzp|WLM+stQ)8%d{iS>#=EUzP!rMN~rV|(a7YDP3g);4RT-$go3
zPdU9_45<~O7;0nx>egPlz)h0W+>8rNa0vzmLLb+8EF!qIXg26_aczu&IL=d-i4!ur
zR8wg&&87<7j3$huXGrzS%*M3xR*}*>gTVv47iFsLS^PjXIr7`)%Bl11bs5@@Tfy*z
zclJGoxZ*L2?1A3+#gKY6KdIvHb_sjxY2*?tXe!U9MLqIhuHrt+xKU*b+{@+xT)4_5
zI{EV%Sj9c8TVqo_V!x*4VfadVF=I@^*;+@57X}}HOgYemrCB}V!D{HbWz5_Q+xcGf
zPhO4T{3%dW9AW3Ij{S{WOYl$>ZKS202@)FZwsOZ?KpHci>jn75aNW$^Hl7OH*{|+E
zy{0)0x4@D8uhD5BPo0-GHeerB`lbaC5|C9+>4f?#$n1ghf|s>zP<P#X`ShRgdtDl&
z=sPWsz;L#Vu~3>JR;J{qFFoP2Rt|y{Ws+)g2E!x(&Z!20SY6@%s;yLjS-6GH1JASB
zb#>&Khn=rhDw>%=48eLb_$!~)QMUH<6AVlx6<Y4vfPI*^XBQ3cMRJ=htYu@ceS1{E
zR4lCD(e++R8x)cEsL>4eYU*~!Lrg#wHR{2f@CVS2U!Z(zk5)IHv75Z4<-?wdiayGq
zyAfbHUvmAicwAWaLr0Oe9%l4(QW)ghl=fu&CKli{E8?Ww-N)=PC}G}&^Pq+YO5Czp
zcz3tmH}V_WSsNG>r0r(OobxU)?AEzI0@-DJdR#t~!uM83H*FUFx{AAEVpD9hbaA}d
zCuloMaUD5aDB|9nk`1J)lm?Xw-jrre+<F{G?q%vD4kmbel)X&Nk|`~k?$aPl2QY(T
zSFTd&c(bXPu$=@2p!rC-i}q%RGAib*-RoUUA`v1EZb}k~{U|0Ln;kn-)*0SB36e*8
z*3RJBLRHX-A?g4;FoKWT=O#T$es9>pE%CoT{zr&sr1@{9@mfvI{9RWur#LnA70cN;
z4}uJ9#x}bCm@MJr)JZxJZ%qOWkr|@(MD#)nV}K<f5lb9Erb}dI&2@dw8=Ug?{TV;?
z=iVvum89cT6>HdDW9wDhyuSX{(k70zYaioZ29Jqu%hBaw*hY>xtsYvE;x9LdV3NOR
zR@G$}fT=aM&V9^3oS>~#B|-AaeM1G{hb4IQyv*=<lf^WiSORXjAW`j~HPSv^T{OG+
zrc5BDCsF%DU9tkDH;x!R>RxPFz^=YpXtkSlffa!opo8QM+`%e{FDrdStFZ{d2b54!
zp2XWNw*T@zF`WwFCD+H-9dp_!>52`&`mSo6H`4n^HB`=gg<mN#vO4!sF8#vC(vS%T
zykrvOPb&c2qf0pE)-b|6av3Uo_fw?&{8isxSRU^~dv6zog_VW5x{}*O2DEu9UCf&T
zVF;u}8ycqguFL`|R!$og$UzDSH$8s*y78IMS)8baFu3oUJhjgX>A{{<z2}B~8-@`b
z4k8JWG`n9;Uo=3`%5|fZZvQ2&k2D+&E?~lp-oqXFP#8;7N8UB#hXp!SW);elT1<U&
z9DJK3;0ShU)oWJl^lytZ-*XEaarp9ml{{9}a~5YC2+0G1&;k4LWLOeYm_%c{h&|^}
zj~$=S3xeGwSlA1^OFaC+Vln*UDBRrr4G{wIh-v&~rN&8D1Q}liCiU)cf8?Vv$U5a0
zboWGLQ&`lT41yS|QgdsEXQP1?!D3J_Ch2gq1=u3TSk9b%<O#>GC;?Qn0j2Z@PtkbZ
zidrW{htgj0r|Y>OQd^hKbvQG{`Bd2i;VA<_9`eSx)oi+@M3SGwy%soE;-2V)Dg*)_
z@R2slwW}C!-h$7!qMPr>=Z3QFK$-i!9OM9SzjMTrs-5W+f|&^ALl4IVNA=%?{^TXs
z1ok{eX>^nZ42S(%z4TCN9)O|m>sPC&R?S^3UWvpvP`=A6e_LKm&}Vhe1s|3;GA~@_
z$R0FBeFjE$6G=gDB};EjN%edUH_3sG6S!Q#i=)8{#;|CLNQc;saH}s-hp|4MoZ8(D
zGuuq|zxQ}8YSvptN3U{0nTj+qmpXSVLdfklx>oQoKmy|F7NpwW3RL)HY=CkZADoLf
zy7M-{$izel>qU?G$Np&T!-kt-HMnOspwW2mV#mSG^;z$)Z|0>zyHtjqh<gsYKd{+a
z`W9A(NjAWTKPMBxWJ3=z0eFM~cB-gx&|ity=w5sg4&rFpckAFc_l>iZMaL}D<STT)
z*@)`V*$!Upgu2cB*M%iJ;{;&^luqjRqXomEd{CFABb!o#{geIYjKdPf84TLabXj{!
zC;RWR2g(L<YiTN-Dti-<!abUiYDp|f1F$>Jzu<X`(b{J8Xqy7fc|9&%p&kA*EvPT1
ztEXcoxabMf+<M+%UPu|IRX=dyXuUxqsGClLTC=<Q6W9$6&GF?(yJlXh+5EjebhoIJ
z-kY!`^2}hWGCc>GH4+XpjH43@ENwq^jNH9c9{b$l9(``|Yq)l;1L#L~cym_igOO%B
zCN{nn_@OmwT8y#gE%`kovGND<J*c{vKZibR2k0HOBi}6O=Q&RVz5Uh<=1=*x3Y*gA
z749&wWgR!E-)r)0=27X;<JDgim?xY1PZciTysp@R9zcCyNMN(f-qHjwQep!2MYl*P
zDH6w37re~H-{)4$?RP!BddaWTmsEq+A0&L==`rg4O^gzN&OMsGbtVV3MRvhc_`0e&
zK2eVtNev9!d#iRo_NE7b@XAP2?OqLI%_QNDg3pR)Q{9(a5=x9eS!tZ;WWLQ^;AHr(
zqMWV34qJ*3k3>m3n-(b!r$j{6;}I!cq7Z?KGtcexp{p48#xnmJ)a5w+#}&$knHfqY
z3slBkJY+##uWVi2N<voh(N;s@;bly5FMp>T%rRwzh8vM2lkKB_`|^-9X}AjOzso&R
zbG)B$46+npNf&y;dj+Rb(ZQhLWvS9r6WNk~hv{9)sRS}yw;0^w8mv6+aWMQa&My3X
z7DPuEXR{@}tRhcPKS$K~-ZLUWYCD1B1Unpm^UXLB`jBt0o?a5V<;SK&+^N!InOJAX
z9rkM`M`9aa<JJ<JDu{-~*&thuQee#uW9KR*!vaUcIKOC-DA8id(S5{@41d9X^7=IL
z6-bw}Re&*NESW-;cW^!7W5jwEFBwGC!-oAKf?ryKjnSZy;SN*}dFUIe%yHW6WkXVj
zv3~j1stF9oR6c3{5Cc$v2@8=%-2zn0%jjpo9LJlfTQDxqz+b|7|GAD!JgoV^qa>Yd
zs9rSCV=TdP)`}H|7}mJt3#WEt28&Io#|5!Fx%v;K$17W)Kt^maSIYDD6co7SRflF`
z!L+Klx?5I~6g4=-mDD%by6+Ye4+-+7xjRQj5^D#OINxZKnTF2DRwX`iWfM1}jD=IS
zMxQ`FM25@Xp5FJl-#2w$BgA$2@o<vUc$<s;Y0{Fb&ijIg@U?2AXWS>38&i>BwC?X|
zJ;bB&3!yC!8&s=BR-GK#>~neUW)W`Iy}DdDn=;SW%`xjEO2LWXo+?Ze;{s3-;YD(O
z2^c!Bs|B`{X4(IZ*B*gti_Q{K$v;wP<-nwf8P76KO*NPk)djx5IGxZSJd|J@+Fpw$
z$Qg9J+T%I-KqSf#76h@(o&Gm8Wj{P8=O8-^T)pL*$Al?!+BmlO<Q4(iQR&x5^mpim
zSzx6k22-7<4ZM!#7Ir2zdJ>I-sNNr{2bm?j%_2SieL+&l4OI)nsJBqpq8r(jS^L=9
z6`3x}&ArZ)=0T?8+m1A1)~qbGlC=Y%9NgC&$%Sf4XinR=9v}0%QDhlr&E$ZT+SO=U
za~w}X&>D3@1)L2O1~`#}+J57HVs%T1EcjH-8B~3eBWRIq>R28Jgz%+q96+kpc=nb5
zs75%Y((ma=)jP?a@c}|*r@<vlsW$`BSLgGjA0S9OztjE_6O~7l_jR#%1oh@UlgY-O
zyN8>_8hyxWRQJdbxcj%Aan?Kdj+Ha1(0DWmsd3(9c%V$`dckkNpCSRmW}H!H9?Nr1
zz5`@y@p_CB0^XNlYo-sWotrd8I006F1m;CqZV@5R`zSimmZ|vKLk{Amds?=Fp3#;9
z;=mMNCPr=lJOtd%Z+d@ov)d=GS;jQ*k;0R3jX8B;5-nK?^2~e@S7X5ZO*l69s&rTd
zI>3gNe8yqFMRv&vucvi5VD1g4@83%0TsC+(@;|21WH5!G=BZY0s*(6K+PRaH{PSop
zfwE~k4c36~W{xL3eIQz^Re*v+3zOUeG_7%z-p9XdZZs;E2IO{KU<$eLj8`QTH_6gr
z!`z6!BMheD21cMf0-U`e)8n1{cKT>@z{&2k6^=gJ=t=+!DtjxarNPJf7`<JwEPqz4
zry%!ZQFPz`eOhm<m35@>ACaO03~C%$qEAv^pzTL4HO#gdLaHII)TFQxA*eWyR6&dY
zk^pWI&ZtTQwEuJ1!R3t?v_ogw4_k*IaG0|=uZUSOrB;+&g(xx0q#h{iLaVpDjh~bH
zcf~~zX`;RLxfCsE#UK*O#-zrQrOegSa`DH1TWG6X8|BB_x`Md~K3Whe13!4RvAuuP
zp6Jkq$MK;Vz&oC8UcZU?Mn5!y{;a3$207PLJ?x*tq|u?nmTN~h3#y_0YPPC7kTLsg
zpW=gHtks{FR}uAG6_0q)26LV+Z(OO8eA*rO8wkY5do@1SJ`ljXlp*Vnd45RoI00Fh
z5%KY?%o~Qk7M}K|km5R`a3K;7e!@Dl6&GsVk~Lc~4%Y<V5lkBMw^V>E6@y-pS5o9<
zinn#Zygg8y+*HPniz_QwY`3zXb~1TXQx&rOu7qd~?FoDlkHuMfmqv9Sh@xt>BqG^c
zRV6cGdZ~)&+`G8QlyHpI^%a%4Ixd^u%=PzrGL?5swn5dr2z>-nXcDo2z<BlJQ-WVb
zxk5vW|C&V8#~oDkYOLB~CJ36KGTr~BgSr#?4NmsocbMH6yaM&#$YK?c9bRZW2}_>H
zS9O)CaDKP5a9WjZ&YZP~@JA+y)z@B|c-XhJM}_Up6gq>U>Fq2+f57KkE5#_T1D9=v
zA2sEPNWmRGaJ1QZQe4^46v~SdG~9AhtqlbPiY_@LegO46t6(V%(|B*KIrZxi`@2H{
zE1mJ?#)ciz0=HVI_;EmPFkN_=dPS3Ti*>#`!tr}FYc1Z6To4RaoGM9|o*Qa5bD_f+
zvXWh6tCW!wuylR`$D()`!OEBRml<IrnmH7UmSg?7L45_YNd3;;#*<q>`p7J7eyS|0
zuF`R#qPwsNEJC!nWHmZ#SeuNNKXyJXR9A(YW3XNm?EdQrw=nNH0QfF;I=J5rHCVAF
zuA*z^oGl~FLeG;#?&1fIk={l^vW;O6(~zKuE59_`bV2vsllDVcN$GXPV|-Av+v?_7
zNOEFV6;dGoO5i`tqWy2GohQ3HRP)mB<fXFEj0M<v=2FDsbW&eUCj)0Ps@Ap`l=w8Y
zh=tRU@Ff?ioeaoEK%{^>^iPn5q*$cNJJ}v-y2krd$g7szDE<TnnG{waE6uV|Hp<FV
z>r4`%%|t(Kt7V^zl*vd#tt<gUZMTja|9BjR>IwX$VD^<+6>ZOdRI&^xZ76lOd+^0$
zEu^zzU-wgI1Fw%(5OVp|2hNcU8sbjahjEaV1nI9yQ=f2=>rq>NT+mMlre<ftDnJQ-
zA+aJ7AVIgyBJ8)YSEo{C8_=q#>#Zk^cC%Lug7KEW=gMI$h{zi7TJHcJ#SJ-RQ%MV4
zZzWWK3hE^mucqF5xF>XmI7dbG+&8)w<e+7wOl1!heC9tUf2AtJd6z!Xv?JL<8<X+l
zD{lUJq2j5{@`jEj-%-Lzikg*K7JH*QZ8DD@lkXHpYNnKuNU;g>2YEVh^13<gW@q-y
z5hnl#fJX=*?OARtvNipu<?S-2ZE5*&j^jS|!~DYDAOfa*-Uu5PxFppGAV4)8lZZ`8
zB8}fZ+<esJCsS_)X3t|8@L3(Ws=x@bZfTw^12_5t$>zL_C5q1rHXQvs-X33@G0_rd
z02-2))+@)4eo|4O)-vK6aL}i{DtkIx0uHwGjsqm#<`Dz8sfGSB<NSNK76|*iJf^PV
zh%VEQ({-Rb)(-1)ZMw%gM%+;XUGY6`NWh0asN99&Y*?Gkkh5d9Wx;cA<xDZQL&$h?
zWduJ3fW~27>xE|}ZYX~h?|*6KOC~75n(Jk9X;NPX8L`UlztwLW6RWqVWeHt&piqH=
zSK@GX<_ltK6Wx-}TvWkQQ*|Q9Zbzro0Z)~shoOj)h<4$w>Lj|R@(uy3gw5;vI<W?z
zvEA*tcHATK*RV^Z$13rqy@T#S-2(+?i?~hzu#_`_QpMOq?<lQfF(`A^Mn{8f=5U4i
zqdStCm>0)QL4xVpfVjaP`0`kf;6adBkGBQ>PpqEH@&VVZe$*<`?Aoi_IVa<B5*Wq}
zU#27}bb+8$7^H^@J|anOEi&i2P@|qv(9CFVjVAA6**-$h`8HO=#h|g$@%J9U6iGmp
zs_yA*%;~)ME5Pp)6L2nm)=8YI=a~%zp5X4Fgow$>yIOj%=7XYaj;{t=d5P;nqz?P2
zx4ab(CvJ%rp%e22nEs;9oRMK5^$cp;a--pTwlAf*+_6kaC#i6BqYVv={o!+JD)vk+
zU|6M}xN+rqI7%?-elQlRvy#O1(v|{z1N2X&t3fB<4y}DNn1GVsL$=hw!qv}>YC)kz
z11u;M#my*rsrsf;xpnTSw*6zgPp!d2IU4JQ8NFrOQjB6s;$Nf)w6rk0L2<s%h~@Rj
zMu&!*jl+$DEDY}#?oFtx#izl=hwp<g-f`{L)mZm9eL;^v77_6jrEn56&%UBzLfagu
z^71xhO#z#F3J65Del+>Bk0F9>*22@-K{S=KQt=+cPuB&rEDQh82R1@1GHl;`W#r%7
z3eXyG<NjACr-pJNz35p;cAOSKXHm`bgwBKgm-(#{_6!S@X)uw<M@RmqMzLQs54$Mn
z`;m2e%0akz|7>lc8Yte#3v60QQJ`pOU_9mKtc@VY(fYB&>VM5S9@KgeH!nCRu$oXP
zUFr)^eN1ip3N}W?!|2zW=vgKE-L}G8dCBRN7p1>!(*@%joi|a=g-_SMy>xISnFBP$
zLA0EC%jU|D=GRQMIV3fts@Aj?3wl^VU^I=r(tM_0o*DwA)>aAJNuNnArVEbOfyOjD
zsGi<y6??z_q>;p1FDz&Vt!1^Op~Dd9*Ez8ZT~yog!|s9g?bBz0W*$qE3X9o}e-+Q^
zoh6C-=Kh7|+cC!@+QNuXkT<$FeQdMXr0q_>huH+Sj}g<4eR7+$qp(GsE6r+3i(RCj
z`}mL`6+7lyV|&|sJ#i>FD>{ynST#slL*8j5-lJVfaXnkWs&ChqSSc%%G_~O2);wbV
zBEIS~7qnfSDIxsWx}lw%PGx+P5#(>T^C$;T)S0Gf{0#`au8a1E*BC<K*aB9@zXgkX
zsquG>6MMRG_Sg0IX2rYWT<?Mm5$Q)F%y*DhwyKwUD)NAjn~-OD<69-nF^-gF<pVJ-
zs>%J!r6rfmMe>KumSN?j&aVZq%Y8qdNs0-pXZP~fqAwWLvt(_NV+hJ#7x`_H38TJy
zEs0#lHguZ2e40Hf%(YtNX)XLrvk^pFs`aw**JG6xxdoc}0pYIR$r3R=7Y{%aGpUsq
z4RYpGF0Q3{#PFSWZjNNY871bsowB?_TFY#<toVrEj}qNoFj7GnCW#Zdui0mfjz}C_
z{BbO`od0#Urx1aI>Bsv|=(AgChpHyPNW3gXis=)@L6PRNRg3ujZu3W2Wnv$t%<*cQ
zq1Cz$@WU!xQ;mv*M;_JbmxJP?V@825^$HaXPUu2xwZ*|vv9=9DcF-MH&a1=7dBT^8
zZii)$G#GpxQxX20f|OH~k2?N9wAJ($kY~Sw6chP90QGs7Hdt&zDfI$atNC;J#1-@<
zJLjeuO>x-9EJ>O`fz(h@&U)c_7;*O<Mrj|uUm`y?Y}fEzqopS{H(aJ=NC5t{LsV*h
zHUg0xuNInoZ}#IGbic(`R*rWi=lELzMIs*v*uNZEkdJlnpd03{Zb_aUMUZgOy-27I
z*>a)47%bIM&NBO{q4MdUtdVhBYRSmo3=_3U)_=J!4Szd5TzBH2>HF7-Nm_re>#2ib
zd39EEGSsxb!jvkt;;nwZV%=sCnlGthBykc!;q_GpBxo9{{qOi}ROTSwU@XM^CBhG9
zQ-i?$aM_6;RL|cbrp3q%4=4U=$N}V~l=kF-X;O%!$-J$Bl3i>1(CHQRd1#KWNf3f(
zk`T%BrMqykq9IK0Kv8P;kAK3aOTD`SCeT5c6$JF^ug1kHDyy})QC&PJqvtLOEj_3+
zYo`)_XsKLELXRX$q~Gj4wndChpj+y>CSLlWJztJ{t)gv&MlF=4`&ZTshjaruxLe4x
z!-ezl@rEE^8DZNP?O3A3CUH7I<J@VE73(9UrS3qRc>i!erIv%{*ESCaW9&eEmNMvA
zt^~c6MFva>NKAywJ0@?|;lMC}K?KiIcZ=PN)EEN;NLU+1Sd63UO6=Cq=i!)7xV$qu
z@52O>mu*<7doUdTNrK}qYQ%~APo)eM@23Lgh<)xDCNiu;H8X=@pub%S(l`fzd0LYu
zVFH?5^#RBQrX(5NCe!l78TRITT<f@2f5wGv$#`!;%!ALj7t~xi@$X3Er!bR_4G+}4
zgeyTgzkKFDaIBppeTN}8vsxBjhN3J;c<oQGLP(`qLR_*oI{u(7rf8&y*aMAHoW0Ce
zq+wVWMpL<L)a4{P=*{o2Vk~XDQ#Ype?C?scM8X!MLJR63+FV7wX<g}9Ncqmgf>aBO
zd+=F!fvaQG@Fm>cHf8fyuPD&UukEx`+xQ&<KCy{xfm%JGMVVD<8V-P_7jiM&)ISu+
ztdvtb;<o=G@2RDW*{%)8d@L2tGm4BbxiCd-f%0Ux1&~!007F2$zuW4!4rGhIl_-K-
z4F4kt;8@GrnB$dvN*bIYwh=Mv-T2;@A8VvBZ(L0GV)IpL+C_#`p5Hn`Ds=t5lv$(m
z(I8X^J#qGqStD2ZiwL0cM8f>JbF-|rL??hINY_fVY-QE`W79yJrk%0gMV7(-1Dk6?
z$^MGi5eUnBTn-<6+e&y3cbE~?mX3ezHoxDnyBo-1=<D8pocJemU#aj3wPgN?VrQ0G
z$prkd9E18{QyfSkO*33ltE`N?BDW4vxxuwRN{hJd4ZjFzJ!_itPS$8J*mJZ|;;1@=
z(*4Y8A$yhsctrus<jJ489dDK*@MhHmaY%CFtxiUsh8ShJNuU&f#@%p@VN?nojokX+
zSmT#_vrAz_2`v^!e%fHTLZ5KC3kKeOXs&&-vq-H2(u*Ouai1Lu_Rw}>xh9q-G4xQJ
z+gldY@`2oUO1!^^X@<8ccn~29yMM)$oO!}qxo0Lxdueb5?|Pwv1aAE&!QUWRQ1XZ7
z3059D8dAS>$ua7xaC&S_6l<~QvR_bCgUwxXg6G5rz+D%3a*>t;kQKFV*JMd<_AeKR
zwrnntOtD^*`k-jxDuGg2epUSBY^JBHw@N$!Gr&RF_ywrf)`r9{Mh?LWuGk!-QxC5*
zND|EfniUT*XgO~d2g9z)7-9cR_9E2X+AQQv1xmVVld{Q?-KB%kg#-`rLVErs$^U(s
z)Z=rXT{o7V7<jpzL2(81Je`I_esl!x*4J#FCpV_Z)&;RYSDQ3)zZ$@c5C22A5Q+A2
zMFW}U+-7gKGOiR2PxkKA$yR9t-|BRFxe?Bij7@*E%OTCqp^B6JEBR7{4`L{&@uHKw
ziTAyR)gD<n@Opcw9)Q^y@F*}7ZUEK_f^gZZI9Hv7qb%;?G_S;ZtV2it4>ET*i=9wu
zRvN&2Xc2wlYlvBcgNOk2kxDI_)yzEg^`hDtM)gd3=yTZru>t9v1WFCG9F;cuj6O>=
z0_|M|Jr+^fW=aJ&%iX+!Q&9pTw4mxNgUpmh+j$yOm)0zhj*otERG=b6@fE^ZIU&?O
zfL(yOAeFCw)u^-UIAsJO!u4)+XD5vqVl?zFT>CP8VVJ^K+y1gt5rAvp4iAw`;ekRi
zf<!leUs~rR5WL>AgI{a5_nA6GGPX*IQYU~kKWpu_*78!}IX{M+Es%i$I-yG#$v6i&
z*!B90ms_guODo}qp3i4$6>Q$^kmY_27QnpNV1KG&su%URp}H-W`I-+key85WX6DG_
zVqM<EsA^mtS?+nf_uv)(W-Zo%w$;69(^=KN^+rN1VbTpW_AFwjF2}$=-sH(RZXCd8
z8LT#2vJn233DXf16%Er1N)4xiUf=(KpepeMuCl)}d8#A<HaG=IVQqYuQn*5`75xD^
zA{%_|wbPUAp-KSC-6Oq2*}FUup*>vKIq(83$<Nk%IAC>3&22&TB;t<*{94AHMJync
zoFLyA<Ikh$Xgn|6us#e_Rlq(7OuC_$4kFgGxcikhXn)#|UeiIU(icNhjp@lbKb*yG
zzUN#IqPE{EzFoEfJ>}v8-?cVQmL$H!Zz;TJqULUFL+)1_C7b*}fKM@4vgSR0e>P+b
zFbead<X1vIQaFAya-T@e5qwCP#fw@rMb9*&XAcBi$bR;Jb|;Mqtse3vaHUDct~%j;
zX-#W8&TD+4!xLa&N+T-M$mEa?*Q%*nhSFvRA$m23vzeyJ-rh=8+o_*){GA)!`}R^R
zjL3pA`ViMVxt2w>v=>%}u5ieYp)fuIuQW`iL<hg}=|B^uFFX;rTa7B``NVU$t#v6O
z&~d6G=U6`NQ{hiZ9yYp5KY@p9Fmd-szL)*+`6RU|@1HBe(r=V&QIYRrA$Q7q)4X}d
zgu`@tQ{m~vzEpmU{8NC-rET)^h5oV`Fgu;?<G`#9TGhW&=p(p%zjK;<HK9JsDuc7a
z)k5)#K0G_hXkrzD=Qdlyy<NsAC@|v+j9vVvyB8^{!O|JOCk=>Z?1x}wn_4((u-&)}
zkkHW@+h)3um;X`9*T&mSS!Ieq`?IEBbJuo2_7iZDI|2B^#fs*Vhi5B&q(tyGCci%8
zqVKqM5S-4cjGw1f(hlw|QC~NTa?Ii6c=gJBQo0MwA~`i_msNBDX?)$Zj$WI)Df#49
zqI9=cyWzCe;fgGUo3zgMd`$_i9|YIP2$<xOIFg%V!}YRYV_7M!?TIioB1l6k_B6F#
z1Hr*%1WBPea>hiffnn+$_07w*pT&=^&olPR@AG5He|`O@8(J+e(!;WLae&C4p@saj
z<}Ke7?#1o%*1O_H!g)e10pURUP<mFpOiovGMWgb5*cDmcmfL~as>Hz9crSFah=$i`
z+JLYBc-{|(-<|OZk~3FOXpG!C7hVCX=6SrL1lsUoExLK{P}lVaJL(z5p!JkI+>O;X
zP(UJhOVG`KkH*YeZ#pdpx7!+j$;(j^!~Iy~`iE5>dyQEHs89bvlfa<O(LS4mmuf+6
z<)kc%D{BC8MmXxeJ^IgBwmhM38e~BxmkyqmPXv$FAmpcUWsUzB&a9l;dgt<*F#XiF
zwqlD_zg8uyeZq!@ztsZ-1f$)pwCywm2)W1?=$Z(1bt%-aIh<cnakpPI@<ZxxQ5sJU
zZ(NVSA=45d&mu>gv_TPLU-#N4T&sps0^M>85Vb6G=hqSv_%B1~ah3xYY(A5w{hl;`
zxHf9>D<>UHq{5<BHF{#es~_pbRIjq4BUCA}f3K%b5D|axC~-s{dv}<=e;*cT`Z@Tc
z9r;^d0`?C9eLNGI6C;AJXSLD)m}LL*+1{shf-yh6{cw<m9@r*X6~@<m?6Y-j9w*rc
zhY8Z^W)4CVkas0+^=WwH3^7Q0sVtwva@QE83LF%D6-vmTVA%l1W0OHb6$E=H`b<7E
z=-eJ&<{wO`2JQW|k-kcFe-2o7Z%KY$AjZv7yOBJS2PuW$f(x=t(@G;5AMQ<H8mjlG
zfOy;WYG-P3c86X4);Q!}u|oR(I}C2)?OjwR={txw{6s4I^%s}T83$%NjbicYF`FVp
zEpYIwjgYXv>iCDKQQs72IF3x4MoP4=Y{BA#J&IXPEK(ZCRIU?ITsOmn<!FqE+y^D~
zkQ3CZbY#HMtV$knd<a`^s&suvyQxFXCpz*^-DD?y<v}NwUt2Y+EZ_`E_dWi}D;Rcv
zq3>LtP5yN_*xp0$;?sO3!!oYmulr(|q}~fyy9wg*rt2l07G<GyhS-s;m@s?c_89bk
zJ!mU4){sNN@TCPb7SUN5XqSRX*}M}oMcsbVQ*BjVoagt5J#D(liwm+Ag$*OqHfcT2
z636@}44B)h#*#$oLv^}7FPL9Fkj?28v^o_OjNWi5OVm1D0tvXc`&?2HgKUg%JYh1~
zeVU`5+#<lSw{WKaH`sz9_|bp^Qay{-ZuB1qn7;>)T-_>uXYYrju>tdEz%?&Z^&S``
zniPJrO>?2I=&|eU#em4aAmmI?7a0(iURmZ~=eimT;H$E;B)zZb(0DWxJ#gVjHmg9x
z@MBf50tD_`m-{_XGRFp|%dB9t0f!gK)tjE9H?PJ7;or9^B`ST4e!J`$zSUn*Ixnh$
zeL{U6Go~>~?tF#k|1LhA<3VpDr}pLPMW0J^0n9h=gSM<iCUf(y$nB2WdJ;~$oGKEO
zy8||oihb6;;3qPl9w;39w#r8?0phSJl+N+jWg=yq0`EYW$xa&yFLte<*nn|J)pSFs
zS-=F^V2SBKFV!d^%2t<cCwTtM=(mHpdyX460~Qoe6TnY5tW`1jF5|3`XBKwDRJcpY
z@|>VzAnVQE@;CTv>$AlebsOD}TGCXHd>Hi9_r`gwkyJX$6j<YEoPWFc-@cojVd|I*
z(0^3i+W+hw)7@2%BIn(&qPZ~%7JKlgRcuY^Xuy62kl~h8BE!`jWi1w){mUIe1)IPO
z#PiP#Rc7M^p_b8uN)u}&lwKc=HNqhr6Yc5kGs{SD?BT9Y$b9b+hs*D0lNXw;yDMR=
zzTkb>Xjgty`;r9{sHJ_Nvh@^JOlqJdB6?8+GXHt|v;|3~W2AX#_<&iA;#oa5t=lyg
z+=dz32j;`{_N`OGL%5gpIR5vAv&F6;IIoN8Zl3>w{p}A)3E(vS;IR^lw%bL|T|TaW
z=>K!4Gf($f^fe&kSY<oM-Qnfma!MLEOBSdjDetwr6>vh^KM-&5QNH6)d;WIvxHDRb
zD>+uUjOcR2j;7@dQHjWR<&6>sdF?Dx(9&>a<|xHI&3qmkyOjrCa@$d!xcWL(5KApD
zfR?cjP({KFR~M*1Jd@Tv8Z?j;78Vv;m2%ezmi2(&#7IciR30@y_p+GQT&988<YYS_
z5?-Ri*;@1JIl`=7{w0F?;}=x{;r}~3+%WolMH_MkVX~+@C<K-jEWDd`F+FIEeZ;8E
z4=Q%1d*%?5%gJCQ#0$M#@4?dB(By~UcP`7+%$(BBOllRsWuD~(VZG!gz`*EK&~vj`
z&OvhoZECaIGvVzt|Goe4Kfft9t30FCPqwEO43fGMh?2D7E*Xv-KUxs)GK(v~DRWa-
z^_NzQR9=uU%+AESmJAUCz9vZsC&SWLU<kLEpa1_$blG_W&+E?&_|b#2xxiH0n&4^{
z_C=JprbvVM4P$zP;IwN}IyT-iTby$)AJh@30>L7E&Y=*o(QdS8e1rL-RqXM!`)x7b
zqPOhP?tZlRtiJb-uwbyP6DuANmE{^;AY3>e)?f#FYP3ruI(;J&Pz6WRJ{({xSu&hA
zmk(>pFk~r(!s7sG_`@-DoObDnm9*R3ASau}la@tss#1a~2=%`d`B@&mTi&L#Zce3|
zW|_RChq;Mvh^$mn6=CizEu}7Aw}SRX2mG?DCJ?N=D3|yf-x*XcbCTG5pKpCBO_;r@
z+cml7TqhzAY(1cEN<UN97)p3^{)3sgi24%bW*6YG;UW<^Sx}BD!Xv@YS?&ak;?Zg9
zUV{yMe2>I}sq5cuD-bYZ3}^mO)-N7MpLf`z#X`)?;k-WnwXn9-keNJ^jo_$T-a`It
zFPvvCW8A^d+vmkepy?QxR3*HH#FBEFLLhsSxJc!61oqYk3N~wYXjJV#k1n;+%H6yU
zLDYzSbr-PT>8V0Yo+_R4gN1wqg~xi|$KVjz9yL`TFN0?2b5tvzY)vVcfH-6N*qa^*
zL<}X#k{+08>ALS`gQI1D&^(7f23&vZsaweLIQey1WFxn}Ou7nG4>SDaH}c@}iCJ%5
zJ~3{%CcjnRJ<%KT0?5jRTx#ti_Ly%~_q?=56WH_TtQO0+U5^zI(|ZJTGMuoCAz?{7
znf|fElG!Q}w}XyK0^A7qg>_9DLwy1-);~jpHcA-_NPm)aUJrnl8XR|=_f<>Qj9oY^
zSQ(66tI;e~$wOl!yeD-E>1yheDElYe<d!SU6yCB2RZ$6~NqP>5ayyFk<f?Zg-1Y>e
z`#y1_cByk6IbR<c0<n`7+I|uzw0s(Y^>w`9gda5xCP%=6JouahMPG?vz1;gTcnI$~
zPxD!q?06FKbZ_xd&nm7Wy%iCsn<tU#h8L5C4cRsV*cBX*@=EXrDMvZ4pIN3rRNBa1
zjpgW8=pi~d%fr?SC`ZeX@)zduC=U??)I5d++ac=NhC^flTs7+le0p~~%1c>aidjvq
zwgl%>i~Sgvd(qw&pyi{$m}RPZ?B4LGPu}-Fwqy0-90cs_scMu?Tk~BQs52a~Qe{fu
z>5(q=o+2R5g;Rzy{H#<2*xA4W4Up@{d4GoOXYS75Af{JAp7ro7Z~bVHINWmvwMKQP
z|B|qIHV$i~L2sI9XP}>gTm$7;(sdm?jy^O~L|O8e?JHGZD}zMBZS{3_=0BwZLvjcn
z%R7OYM{%Z%U*^dQb8%a*jGlnsbjj(Pi3m!~cNZa{bCKDn39tdcW^N97!ZqUp0=&uX
zC0{(g7vU^=0Q(B7f6fNW|G5~c=%_<zWO<^TamI0*03zcF;6-L;+b3>#FB{{_trd^^
zmpd!&B85n~_>*YmesJO!A@=V{+Bzw5kkk4+;ga;|p%&-+&o2u7NrCkeG5+zTFkepp
z%L`J;py?5vQu+U0Lt7fr&t5uL!T~yM9a!^T+c$!11e3UiPGBlbw~5J97tXf^|3Q-Y
zp0`o{6tnNOpu@A-yzb8!`E-cF(KM%L?r5XwEH_s83CGse8f4nJ1@3kV4`f}dqX(5}
ziFdTTN#V(NR`WCqZ;JAsb8tb**T4@hEI(mX?E}Kr;iEqUsh<H>&EVnXDP|B}rPR=;
z!j3*m0MP#Bs2!m?-{&DrL!{grP7a~7W<F*!VsA{R=<MzKHI-LRAmxw?YICc=^l)E@
zsoHAcUpY>?U$!~$mi#J(r@|@Y)vS;!FMQn&K7qjg;;CLvd5s)HVtSOFOjqf7ZPUBD
zgldSKvHS!H<W#(&q!D9?&1#<@LP}#^ct$lX^(U;+qt2`*BL8<6WQ<dQyhQbpv@~-R
zgJs!>x9xTLkntsx$S2T)1C-kDEL4Ht-D>{u$gA{X!ubzx)GZiRrbM*-GD@V5fvaKy
ze?t+30wmPrPp>CjY_w)YB5;OcX_33o{(b_wtN+l43JhTaS5FS;wAYG&)VRYtWp%)E
zX9tR`FPr(7B#l6dXS#b8to6!diCvp6keykA?+?OMUdtVqU<E|4O%GJV%|ty+PlwxQ
zF3gqtw1F1|F}AV{DO>nzrWRH#as$TQrfvkngT1tOAG|+@)@zC@6a~$&EDL}HkY8`Q
zLxEowq5*_5&*XfX<Ad~iSR4U?k61HP|Fw9TGjNpzg=W7Pxn$~8@GicB0@G6#Mz@j}
zYdjmyUU91icULj6r-@@E1{0CXmDqCcTR8d&+`B{Cv<>eUIIm4wP1(k84FNz|^=2DF
z!B`-IrbCFa4V23zMlnA0mR>Plz5xs=ITbhlXB=|EAUD~2W!Vo?mfEj&3o<Y8H8-8t
z*e8fU#WSNLLxW&gh%?Oo`ykQ@$4kbU+IB&ueTEy>6#qbz){EGUU33|XbFvK1qhS=_
zdxn-p4B|p>HD!lgjg?IiA`87Vutr~_9dv0|PT*H(6-H5EM-<p3BpTAl+1F&PTg35W
zEQss`b3f%L#&@Y&khMQo=?WpC^xZax%|xe~o;JIW<8#0&sGL5OEP|BGWw!XCzRqu_
zwx0h4955CRwkv~#hzEJ3X~^^$=Om4z&kML`^>G3V%rSsM{+KXYQU1H6zUh9Cv$Gr-
zcyZhbvPiIaYgLopQU#{BgMN}WyZMiWFymfSYiF({-kX?JBi}<iyK&N^Ri@MwUY#D^
zJl0R|w~$mg(2Yg@LQ7mi7EnO1-6Fz-KSks&!973PU*oMTGbbtNz!WOAb_(JSQ6Fvk
zcRLH}*WLe^{k;CFqN87=*uUw)Hz9y3YdJR_IdUKOW;V>ql&#x68!B}foljLAx(mvq
z_|%=-oT%)9P`LZvI-I+GOWER9QEid8+P1#Lu!6f>W^9a+skkcy&lr%DZcX1s0M>!Q
z{s{YmDf+<j!RkvD(c4$xB-ZLkiI}2l`x{A}oMz?h)|uq3;9DfwSe?)%QtL<^ZjK&N
zM_5@RY3l*4(kfxv5;_*i&77^$-H&6LoN_px?=l<0)sqjX?o{pD9AN==lOXFj^s?Ws
zc_yI+*Y~vqD0nUH<)$!b$(><#HAw1H^bUFf?NWUG){e$Quc!o21S8ICLhv0+R#=sn
zH9|RBV7eEAj`4IPrn$EwE@scYipIqI!gq8Tu_U{=9Lxyx0skNG?6n##M2<VM82PE1
zm+wZk-fC1KM_|*-C~(nK46+5JB>DW%lZ*YL@!^`gIM&V5Dkvix5l*Ni0qsIJ&wvv?
zu?GE&&A~&aT}f4>t6f0MQ5{x_ew_A{qHis~{4(A-Y_QOTbY%x?T$V4pPyuDgQDNN-
zm#y*R7I3$d(7z5>KZ9b%@%n-vCi_^lea9J{s>aLkn3Pqaw_3N%FU3Cz7WuM|WmNRb
zCasIVs*W^C&+@mvi}MQhF=zM5Rgp!sBMI}>2w0Ru02gT#HvHTTHjY}UwSqw_D_8>R
zIk6XnhK?oK9uO;7Q{R1150OU62{a6S#Lvw8kT*=Yc6-N9j>P=}TD(S~^GXlDN%kOx
z=jynKvWkYM2(cYfTK`XedwdO=(6NfRD>Qo9JvDNRu;R~HkfTG%%CbI6RV6#(B%Gvs
z<~OnW#I=Rr^TR}Yf9>3I;q%=O^GW*vh<+u(8++eV^5KfJL>K`^6504Wl(K-jY0JnU
zMP2)V_zo0(bA8wzT&*20dM{ACq6Vie-Pi=V6z1b&7A1;}QZZ>0p!A_nL9G{XGL-<W
z>E%(jj|0}8>YuTEt9y<g(9tVCe>r<%l{sYJLCb!nigTf6R0=#<k>($BNduDt$=D$4
zDDDOeh1~2vDdtIoa0URJM!$`)ua)?pKc6=VxrO#1f}oBM5Ng=XsA?{V3Hkk!cye8&
z2#8Tt)z#`SBsV_Rl8l`%EfXSC7?~uKVpo{Uyr~PMh|YAfX#O;h)ypF@Rz;cenAio3
zKAcvIpD)q4T=3rwZY?ohTXLjjGvlb6Yac-5f&ICFuN&&GESL$%RWrto|CiPrQ{nE%
z%F82P>ZNhS7LgkOEcoH5eO(^@>zD{r9>uR7^{0~#Ka?n35w(jHAhN-pe10{h^jtxR
zYbAa%9Y%MBwe97cxq7^1QXne@5z2cUw?++j)6V%bPO5IfeSJ;L1k$|ei_s9jan9go
z-nfnP*5N3+k1>xd@qfOa#KC4&hjAA2QK@s{1ZNg`8FWTIWF%H3MzRKJ9goD>RWSlS
zK|q6u1WRtb#304ibC>UX0^Z3-2!Vaaph>G&jO>XHI}Ajel@Zj$ohCg^9q&VpOgT@0
zH=#SAo@^)y1owFgm|t2;bcZp)rN*gDSf)@cx$P&=;VzP?(Cy4s)9_a#5|%!ADdn8(
zXIaG^MhgEd4ePtrl=sjvH_E<D_RyFhpi@FiX>*pqR#^#*cXH2#1k96H^Tc8J9n}cX
zQ20a(Z~LpBnp4lYsqg5yS+2ElJ^9H!6-kGCG78+0m2;XI*HaW&VpDoVkA{DuV+t^m
z$|472Y-xqEAPU+z>>X3e0-M84-u``1fDr^)0%2@!RLPR5ugOwq(qFz~`gN9s#tnvt
zB8-_PiGa6Uq#@(iZC*Ec3i2~&OQyz4%9s2+y5)H)@vF4fofcXtJ!hvPE;FsgN!*0Q
zYpb>%(CS!wo*%A76sQXNQzVCH{pKz^u`HLvQkbngOFw%CCtzsyE^-}#>C&{GpW!`A
zJJ80%vF24N(A@?yhaV4z7YXC!irkJbwgSl1LJTyftL1!V@feRCuL;qRtu3Ifl2OW<
zW|Pr(U({=ld5>kVk1A&uO}}uG+Ih=0Kco-;_`Ph0QmGWbsj6A}tsza&PZC8@;B@d{
zdl|ISZSB3d<D*;IYm!L5XZJ{i(MR+#?`nZPJo+<jb7T}iJb6R|$hpR!xC`IYB4OJg
ziH4_qWMGoIfT4egasj(4!fhyehY>~m{cQ*Od@c9}Esg?n&;iVQ$66u@j-$ZjlMgT1
z){r^s)3{y_f~P3hBE3!LCCA(;g%nrccEUxq+*BtqxlJN#)q^j0P%v(eQ|+)822$iA
z4)u9x-QWe09_<-n+LLED+L{$3IOXR{v-d~|kBc@-+cSd*CYMA0))?|JZ!kA>RO9@e
zLB=e<M|exXMng0SA0dwgXq_xdSaTlxV;{8H+=~p5?rFP33SdNzaro4kyxIGBY*AP(
z{OUat3#xw%ycyLai^TqEE!W+HdP&NUBD3i9(;P|$6TQ~{LP=!JWeDw<-{|=7ZIg04
z`PY_`fIK#;F~8x`W+(<-B<wlW5N5Q{(RNr^%{9H7KqfPcUiZv2CL{XjjWt@zV-EZA
zn=WD+uBjmi9N++b861Z&BiZ8`dsbm!x6MeW34Oy=UQ@XE%2qaD>#wY-Gc+N~%BJmL
z(Qnrzo6`oS2TM;S6wF^uMLU$7cWlYs80rz+0lP3nKI7biX;qlj%thD=l?fEj(xKFl
zH5ziUBAKk=F6K_6{xj8K5Ra;MJs=C~_p%0$kKGtJcALb{OQi!{Tzr@AmFt|vM>LtK
ztH(iT=FXgBm`Nb)==ISP-EH0Vjsmxs*hZ7^DH-dmgyBmS0!-K^w9dFN7Q!qZ`to#A
zFFVYC4tJKcQkhl^=s5!{EHTfm{46_ya}BO%1Q$4s=GxR@Klcsiw|8l<wiRyQuu`af
zzkBuY(==U|ctF}POZQ0u14>`GPuZvooTWv;*DEC&x8;ASS0Sos$f8Lr4H8n193;Xb
z`V+qop=FKeXoG}ZCWGt#CLkJ9z^R9JvIBx%yG!M9xgJDM7aqF;0%%M6P9*;T5n=3z
z(_+-tc4;t!@4hJhk<!OE;a@+0^Jm%g3~;d(@ow}JsOgBQP~yTqPm2{1%Ctn_p5^BO
z^gFXzOnDA)DglimSzHPzHa?%I!ibH^1xyv>Ao9JZ5RvETw~7>tY~egYwll%+V`U_L
z#&4#`L;4>1xH!?=NSoz*`1k_hs2zA$#i3T*$pO1zHEgSKjGTZK{EtH$WW@`PnmLS2
zvmhpSt6nmTz5;E2g?hsG^T~5Nc`^XeLDxUb-a<wlf|!QAywK)`S`3YF(Rj-B+^v5#
zxmKi9{j@!c8E0e;R^3iEE{Rw}b;EPsnG<-nz;5i^q0<P=RKSpR$sCAAcp#v%ZZ1g|
zGN5EL&TMFzrIFDfOXn@`UD1d=h#{NX=~<!4h<-##^|{vkH#?$mOb_)f(xAg7tNQNJ
z(P`$6(r)>6gWUSfPovN3^R-5t83M-@;H710iCfi*$SDig2F#y<u`KxX2V;o|hz*it
zei}4vsfB+0db1dZwPLxnu=15{#mQT6+^9BF0#z1gQm5~3R3wLv@N#nbTT$Ji#k5vl
z3wwkf_l>LY5aC41kQyW}Iob;d83+rtdO7?IW)!T}VQNxg2;L>S!99C;ZO|2tXm22~
zF*3f^V*x7(hu5HWM}Fc-n!834Pf=0i_0W4X`Y(AKtv2WS9d-K^Ph(_({V=4U`Hw8t
z_L))Fo}^k4f_gvIO!Ww4$15{x#W~IxfE%Ig5L*DoK<}T$MaULVFJ+0%iVAuG*!zP3
z?WMKM%}sQOZz(|T@X2R$LxR&oKAa8NNayR5bvH;lIw7#-T{R{Oq8IC@w-v26AIKNr
zMOYA(_*uQ>BBp&z^^6>9aukV3eBRwIdTg)MS)%JU^#wk2kPy03=8zqycC#f3HLUhz
z5c(w~hCit8Tv{hFjGAbqO@RTe-FBJ8?ibud*+v+}9mf6Gh3U`D1uN{8bS2+DDS-?W
z$*)7rKApW-+5cs=G{6|U>n>j>i?0q+JKr}Aa;V|lp+(V+>}TKfdG(^F0<66-5Wgn*
zIfzY3J{q%<2&q*U%|x6KlvJ}mSG5mrV|^P(m-B~{?sRspeYjwZR`j^S?SS{Aa7}Iv
zP>VfiJS3Pc$(BC7FKMbQ#MCc?SasVcZB4ciu;FuLk#}0sL=8*P(p}I|qRag?D@hD7
zX9zfGRG5oLC}R33FaIE)RR_MMp4FPHD_X!R<BGcWQafj&$~fCXx#|jPyUfWab6Squ
z7!hIdcGrG=2O@Ad9UwR}MUb#0M2|SXfY*OY+kQ~()>TQ5eEyj}eaZgO=8YOv@=PGQ
z0Fiyr-yL&!r9t7im6Sm1dSp%RZ&@orfGux|5U>2v8L!D5#xB3`vA!)zB%hMgp%q#Q
z!cyt_G?kt~D;>3hNbXvz1RX2gi0fx=R4gA-t)rI|wmlZRo5FJpveAsmZ1Z-$q6V!{
zOlnua$#cZ5IGOnmh^R_Gu~g?r2(qpyAp)E?jz*_XT?vML-4B4b9xUip-}c2#!-p!7
zm$@m``JLJYnqo=3!lqt-`oVIE%DFrdm#dj>(GX`-rDqCu%^ySZ&y8tHK#CJE-kj0@
z#z0XQ>(jZZjM1+u2Mo^l&N|2I<e`=|?r6KILpU*(>doeIBdOdN(7ZgvJpBQ%Nd2F;
zC@w*e&bptfitjO&2d9f&5$AQ3<0GW=E2}6<Wnnue_KKNS=%~D}N^K)t7CNxZ&g}TE
zPauESE$HCsvE5%VYA8ZR)H439tdW`uD-13((#E-9@>vhO!#@+{t@4V2khG(OdwgWu
z7*{DyopTkE0HA=KkgK?uFeiFaXG4=O#aLvL##0KY{yUaMlHpE^LU}10VmUOU&^|3r
zgc3<~3;d4`!*#<*Wf1S(DDS4QtJvRyw%$;ORHLK)DYPO57j>40k5Q^Ddh1uY4-M=V
zaJxx~$c&5k6l)LoEe!iZaY_SkNpeH05nv`zp%bvKjX)0#p_G(T0m;9xHWyFHBEexb
zjPs#<eS|<we&4b6y@%>|{YDl(J$X$<@oaaLxf81ztS4j1FC~$Haa(h~DY44*cJ+sd
zWiaYVhy4)IMUAg!eRC4#Q@a3vweIIVN&2FNdW-(t!2$geG^I<~ltGPqCrK3?I#t6E
z5(0VihjJ}+o*>dK(3Cyq&EBd#JC0MdC<=Ah(OB+niaS8lka~OFmm=LfFGf@$+PZw8
z^RcjcDR)&vOwLKd3&Y!dSS5zW9a6R&woRIM6eT~el`6TLRNf1FwWcm|gcuOVT&&rx
zkb<`@PWJumk1OyK%Z49BbY``Z%IEu|Ik|v!2TM!H*ITJl-uOikRbOm;pp7pe0jm;!
zC3f*07Esyy2&&DbGi5(eED(+y++lI2R^l;>`!Y<4(DH58lY_na3|Pus4+~9iK2F`o
z`*@)DIcOX8)M3QkSx=i7C7U1R+(}#PQYz3Qevg<mZ0qHIMWuei?f-izefK*0G+WNp
zT-ru2M3@^$Dj!pvt7Sn<A9N6)Zk*Ibgn@g<y)xg7e;C8fHxigJ#^?K*smt5wBU5q!
z!|l*FWZ&5+*=|EvCt^)!{Tfuh_@V1yD6~wl_WeH8q9YfF+rAiw4lweHL{T6Dg>C7O
z(}|~N8i&A2NE%1@<3oYO2XGdIgc#Nv<>!{piDxC-vQwL%IXoLkk$W7#07~`wm9!_}
z_p~eOA!wXA<MJl^hIr0v(pQxFMP>x{ySDRM+pQUS-)qSFxWS_PijZpg{IMy(D+$hD
zMjo>lkmGnxJeDfBnga}F7a%|I3TrB&rs%}IZTD41wcZ?5qJP9(|4HFAh<H~7auO(M
z{?AwC`&8Ex%nfn+!*ThI98|H75+nuTd&xFEh>N+7v0R4|m%o)w!p*j38`187i#_6O
zZ8rH3hz8X@3N}W$dB1zvhTAr7548OEUB$<=tr?N89x|32LPBf4u{(HD*4E5!HEYkW
zySxqFe!a$tcYlpWZX2N>?!<l<8>}A7bg{xCs}xIqkLrOKEAIy*S>>raJ3y(;(KMO1
zJg4wSoe0Q3kQ0^lW^lnRz3YHF)0?ZIxhte2c%Wg)=9Q9FSC(8U^qk{4U>1MuW`k|3
zFDyI+;u<-Bcs)J=j?DQx<Vo~W4Dv5!KEcEiCBvScV9KRhQbgqIrkLjuyk-*&n`&3T
z)1(mhHP1DC8@;GCi>KLlY@W}3n-GrGHmFw8CaZ~Ia#`m_2?u;o^`ABq-raxVWgorh
z-CR^(tdy3HY(u=!0d^{;^y%O;Q3R&0uBx`bpte?xrTixtlDWqogi%N%<@a;6WHaWN
zV11e9IC;~FK}FE-+NObo+8x~&*leOZJJZy!WKk^;W`cZ3YB^!n+G@))rO;gEDo?#F
zym?XpmtW*>a+lux)tJ7L(qlhBBYUO8HX##uMd76b6g1pT(Zg12z9ZCbKai|?e9knf
z3WH~t7(-@>kbkpghX=5fp{XeuBBdtyjqgfBb0l`O@CJ;fbYe7U>k=g`yYn3d|JPE^
zR_(_LUI!XXeCRm9m>xj(2e9}8Evomq-}*qvygC}fsZc}K2lDk#`Kf$?Jb2&r^=8r&
zgxg+MH%->9_Dqa{MAg)czBw?n6%1Uve%q_RG%>ehQ}F==9^-_KRdMsJ-N`g@MJAvD
zQ$-R*bJ`n($`Nl^f0d|e&5)XiBx`D;eof^Z+%u_>N~icoMD}Mnz#hQ>5rZIi`QN-R
z+2|k^aJ8gahlAxuL}^Nz(`%Nlltw5(Td@)yAIr=oO4NemIR?xlyAEQzH!iS9rGF_W
zanA)q(mF=HXF!&yum+&`Tq*y4pL}Pzv<Kk7IO($IDGDhYx%K<HcnMogA1Lw2M*Dfr
z<l1^HlFMn~1j8#8z)@N}Vc$ds%B*<wmNfI{zKF(!MRph$o}@C;#rWPf3+*v4xo-mU
zvGO2i989OIh&CoqrEK!<>h}H9mP3zW3%2+gy;}EWbgr)z5-%d;%9zAdTDRYii1&Gb
zDg&BetT&L80^+;2d~1JZIHu6yCW|>^4j!&r;#unM@hr8$D??~DK9qRgno|UJf_mhQ
z^vJL+2ZdDmzf%XCF%?hg-o!=0TCre~K$N!u$iZr6)1QnXn}L~HTTQ(Js^Gsxj29qk
z#yQOf>_{#e7DqDJ&Pp|=b`aQ_4j?AB4O3c3*pCL3X6L@t8Dy6|CJmXvuft`at=WdM
zg<wZg*z-%fTRpRYJW$R<k{$2a(T`Gb7bGxV%Jn%#Qv@N~Ak2?3V{@66q@&GpyHo!l
zrfJUOK-I8qDg4fZlCZp^`^ZyILgSXnR2vFdNx}Td=AU75-1Cjzw|)!aHr+f@w4`Vf
z!TAVX2O|%dx)bHuvwj3Zm-Tjs^6bWcWg`cRT$x1Y@c+8SBaxk@c)R5%pnVxq1>C#z
zKRSk|tkkq#D;NN?1i$fivr*^rxyZ^)gH%CLBX-x3jv@>6Y@%M}R^<e$v9o)uI+DJW
z^^`e!oeae#4739MW=h<Vk~eV6@b%N(UAmg}>c-8a?Kd!c@O>4{=x5S<NJn2ta@u-{
zkd?PMh=n`Q3EkR9pHXdE+@BHpAo}FW^}w|PZ*_qx{(E#eUeV{npwj~l*@R6i9=Ji9
zIZ<+p6JTV<iQ50!t!8k<jy3Jf<z~sp0xMQzNZ;Fk*v$x1e#BgK0FiS=;O?>BkC@Z$
z2X4HwMaj468+syh*ELDgv~LnHL3-(30TJTD?bfrqj}`l}JVygcz&aDtItz$!0P;&*
zPwIkEWO9J@Q&+G0&3&iK)kt@x`9Ap3dTwAoxi7}-3tglyD0^dHUnHhu>@+RdtTz5$
zP(a?owS=Fzvw;++?Q{I1_*%z|`<~l)Ajk}z=5TH^D;*mdK2NOB4OznKv(#D5m{w21
zmz{sxWvh_B;%w2HM+GeH`+tOrBlg7Gll+O?qj5Upun{m(19wlx3Iac^z-FtnEU!6b
z05%)&L@Elt-S8~_cGDn6ac&BmJOJR{o2_8X;Io@Rul<Q|zA)y91w}~3T)hwRS{r2!
zJ-E<q_$Enai=@S9qZ<R{a2oQ)+*Oxp-{~7dBd1_(e7X{D1D_rZ@e&cIh#j50o|5^V
zNGd`^G_#2I{>2brC<4otk|e@_N>2=6bi28%y*K5Z<Id$S$HL`W!GB<CDuQ-%7{PNM
z8rHz`f9%hVLrC3p1S|cxdvlfBDW(jyZjF3$?4rUtlfDmoUkg58;kgruU6#8o^6tk0
zY{;D&HpcJ$6!gZqsfWHZo<0sc1TDW7ANJF<yU!@2<RG(D4DjJPIpq^E?<^rm%ZA@g
zHLhwlH`9X{W5%$TM4p(lOzdoU2533rRI7d-@lljGCr*ew2D}h#r8>Tl4(^Dn=e1dW
zFLlNg$wXxYEl?j%gMfFw_WgiLJ^`=s?hN~yGOdb^<X94AFx>z4nV=yUj78Su90M!w
z{DmNJv9g};L#_1s+wB<`*9N+^0*K_N;@JlnqjH=jN@g&d3Y@FaH4i((SHbcPXicd=
zv$v~MsVIcc&BF-$_q`#h)9bTh`Ee(UJmDAw>oM_E=OgQYD}4*+Apn0I*QAkSoRPeI
z#Y@c&f6*NI!e(L!eTJLphxW4Uwi!v=AIsKXr}v+$AZuH3fqFMxclC~Kt3w$5;yI*9
zq0t{5cL=BGoagM$#aeVugb#%zQEb;Xn?{--0=7=YtJ`c`aSK0JSDt3UH!pcMO`Tv!
z)hLCuK){8kEL0~Y9awLG34DcqOX73uI~u(MTvn<YVuj1G2Je9fVZ_19Ug7FA+43Za
zxzZo?Y%I!@QJWk=0KF>P%a=-0Lpu3wg<x>=!+4n8GnDKfoE#vf*gJog<ZHUvh!ZxB
zzv>4i(hF8t{uUtr+AlqxVv#V_3y_p~Bx?PA?LvD6eY;pN>)#y5NiH{T5~iDVz0hfL
z#_#I<^tK5GZmji;gf0kN+B=v_fq;O)Ff{yBc9NZH`M6kVswqZWur}_z`-a_n>fK{#
zdvf$5zTq|(7^}kelM{Z7;iqa=#ZB6bI74<W@E9~#Di}d`5@(8LPy6fA1B{w)KeKS7
zCG&(xE)J1-)G}lyUqrvxc)^bUtCTccMUzUbMCOxfDCywobzT6r!hLIPv7&amlqglO
z3wxtsPEHQZX358?{NUy1NmyVAZ;P;_t%Py*B7<3h8w3@>jmb}zx`@@09MjDRA~rOT
zGJ2TE6wV@tQVO_cPQqjN5Z_tH1&)`{B2MB?XKcMGf}q((m7Kf}J;66=%@R;p3?J7V
zp5rhMjD}P%MMfEu$luC-$>u*}RXndBDp`xT?p2!rwXL$RCYwcfPmxT@f~z0CZFJBF
z1I>D>Ls4LjdE`z$-}_^qc+ky9`#0tU)q0=B;)f(pmlS2q%3c22%=zYKMX&HBGnVA?
zFM0F4ZSupw?sn9E*dvCLY$dZ59;!v!=dz?64LChk5r>)XMaGdGzeXcieL`p1Yv*<x
zJv6MMIas)Fr8!VE@PF^l0e?Kule`QFn)21p5zawL(BBU@h2<bC)^5IM8`33WbVRIM
z9X5Gv3z%A&9>hAnQl+ah<!8sA2;+g%qIN!u5TGe36|#{6ZZ;PN^+ukIaO#ix>X!67
zi=j7kdGb*^D2XZgQ$$-@kxw;#bCjcK!D>XsI;O<|EQgj~W(?R9Z(Ula8lF-=m>mbt
zrl&&}ls!1mfOXD1d<3`hlE89`7ufSQ?z?$Zak~!0lDPy?qg;Gzs3}5^qNOaZi`L{s
zBj*v*Y^b~FC_(OFx+6|;?()&UG{o1sgpz|(PMRm)e?hoVp;`(Hc%Ozg_h8a%>7^zJ
zBkS$!&M=*gY{dPOgi?xWwE8RXMuYkC+ZUN;(j0yt19}e>UAE1Hk<6nN$elI@p)C%=
z6ZKgO(#y1TNV%J>#-83?DlI(HF;k!J(lsQ=kusQ9KCh(*th%y_+0atP96v9+vAZ?q
z+LK&`=4Efbnc=dS1AfqZzaeCB<&(c8(q(FB-yHfVXY}d1icp+u5JMNI5G#XW0{%4L
z@VqG1r31s%Js5IwqSm8U(?!#VA_n->c`2;IYu7Noa>*{H*u-N7JY{MzJWC46Y>ACd
z89p*KWgy+GQ-_{Y%i0K?2po?&Vhs|?{xy7!n$Vcg>pyF~bDok?&)lTz0t~I|aC~~j
zAr<`CKPd$t`tq=!B0aVE$sm8H27jTb%~4}7{TE%+vB)0dVmjL=82+U?tfzGb|C&#?
zFv=KM5NK98{uIM=F?UUczs%3wk}Q3bvo4#vX&0!ef56j+S)XB4+Qb2bExriIeK2n{
zT9PXnhkF4G#%VJgxlRv+9x)s>;AXy_%eiFWtNybUAp@CGn<DuA95#g9L4B)hXtaf=
z0%P_HsNiqZb7Ll32%On=Y3Oi+nSe=RCS7TPf-T)cCbKz8bO(;F2)*8Crq%Y;PXrza
zb>8}Poxt%*b<BZ*T*nOd5N`MVJmZ)D4vc*ix)vtrYG$3a>_hs+mgp5^!C09>z8dV(
zE6-qmLkBDnQ3|`>Q;O-@D+@<19oBk6EvuICsS0NbL7rJ64#&ICYptb)+}fdMy4qEJ
z>Rh_a|I7E!0<5!CWi(>)Im^m$w5n$7q4l%g8WWqu!H!fW66o}oGWk=V9kpTM<1XBP
zqwX~zL9&n=>t;W9w@2W<eXN4d$vWY%^T3$!W|x-IgOv+~#^K}YLOTd}7l0~c@6i2P
zySx->0ah@(7Z|C7q*~9AAnqKwgM(~Zc1|xV!!vV>uWFM5!)W@&-Co{?!G^#6_<y6)
z%yQ|!m1gikC&2KI%f6A6h8>l5HhwI*$YUuGc)xrO^(xtl%h&BNhTe+oG-d_!wu7&z
zMvl<zs_|6{3j9zCpbS%|0JP8O0xN<Rw7y-kqSfDb{LVg>C^bwdffC!;Mtg3IXRI>4
zPPp8k*KR;@FUD5Tu%6csuD8~(fa16W1t6?^LV*NW1=OO8sU}dfZPi3VsDR;Y4M!y6
z_b~KWFh}m7apKb*+b=#OM8WSyw_P`5JjDv%hKd>>C0#e-BgYLmfx)LBz|w8>>2~yw
zNuS>)*a!1=?f~nb81%CU0UV?GA<<WVS8djda(Z%XdSJnUmdzaT9wY@_j)S%iKw8KY
zvW?^wf?Y0v>$1ioxuI3yO$5;$j$%UpEq#3Zah++I9HBcb$Ti@T2+T&!tz_R>mAryN
zH-#2QH2XnP@sO(EtWqkb6=zztjB52MQ&#{RV$(~xL3wr%m{H0ib%ejOb>ew$=m%d(
zTdZ-XE+kkqerfMBjx3Gz)1?T^*UQ-PVzRjnL@-FM8_QxFKvnS4vsj^*`|S6fghKii
ziU0SN7^gA^m|JZB^~@NWn6XdZDY*1>$#IrIXQ$2nWN&9M{~o8$mkD*=1HpPKV#ghi
zG=Z5^R7=IEB^aL;58S=Xm^PNN1$oQTtIeyLJ*IId8NFjS4XH?a;F?XS^YB5tus~-d
z!5Zs_yB?k+h84q)K)Gi$vvfO(MsjnnIyOg4zFEvtIR?IZ0eEv5a9b;1&-|I(Boq+=
zm?B?iq^QB<@Q_R|Y}9%g`!U^ls{Ha(OU$9)+skHZ{|MNyB~Op6F_p+Kvqi7SMy!ql
zBtF~T9_4dsc|i=-(W7hkIkqj1DXL};(~*x4U=hm+@6>va{&5k_w<*5Wor9$rZ2H9L
zE5AO*oI=|GoFzUH*<&U%4j1VuEii*(syOEh!U@s?G$8WzuE_w0L~c9aM--RXnk}U*
zYW~<%koU;;-WShyATM81C+9RAcI?EPOXctDA`21C?4ij&BMXxQq+08wk5hjNaVuU2
z07id|IUM0(XW_x$W<@;sQJ1z30`PV$)g}-#am;(=gQ+$d%GU{@_a|h`z~P!%V=Z#E
zpE^gLk}EU3;V`NpSgC$RtXr_Vz?+z#hnM>;IyC@buoGY<J}!fquF#kroiy6DEW?Gz
zVFqi!KFb5Abp@}2rI_(zf$z}VA^*?95Dhr3HA?<MHo74?s$47Hy$%^I#0NF?r@cKj
zqe%S9tC}+bQWrbKRJO?b=Je(GvuF{1LEf*5HxBC29@e!)SiA$us$!4LD9e2ROtb#9
zI{1izG^Dv26V5o>)Q6I$?-!6C3ggkTW@ydp>R<pw8(p7hd$Q+x+-$EoOTMXY`Cn=4
zk{ly9U*1Qn0m=BQ4ogq*-5@6!UpWtg|5IrL&i$ELqvVeIC$@%2xC4`FVuSsvjjStx
zXcRYgj?(1lH*@Zal-^bUL;v|+Y#t5LVap_=_`*bM2))$r_^o!^=VN_`tzgQ`vsmh7
zZrJpc;;h~VBa<$^`d+<5$v2bXapbIji%nnz8}}R3eZ}1_{WcDA$dE~zyoE{)X6k=3
z6oUp>@7JTi46q=XOnfE0Q-n?i`P5w>k3fd-Bti2?2|_hV70TnL_ci18mi&rp40lSq
zS>M6P6E*qim5mtNBDW0Uz*U$FWT&6?Ya=yp>&^^m75aa*K6BX|3IO_kE(t9Mh6&Vw
z1a<a3Tn4ue&C29ZQPcGaWsAd*)bOv}&iEu@_y)cyZvxieZGdd9ER#Q7QP+bW<ilTr
zIh^qd%r`$`p0zQWhkT?9L29(tI%;Ut5o?aZV}N=D_Z?I|UXQEgP?=S6x7JeDgkUt!
zJ}jAl@ILzMYR`c+dllOr!rvlGH?_R=(GVsVsHB+7xc~7%U96>w`}E8vWsedbR7jPi
z3PMiXivaT}p~G5^4Q)Jp35Oi_JnMH?yY^JG_+f*%Cj4%YL4!HmW3sz>w~p3m!-a`>
ze-s(y4`NN;wvsY}Lv){j>MU=Uk$V+|GC-*opC~`%dW1@giN2X@a9SZjjQ{i8p6y+R
zc;Neg7b?q_LtzxMoowkyCpHSnI@J8ylrB*Rpab!;F2Z=r)XzJ}P3E}X1OVn!0a1(2
z_WaA%m@Z?r+CW>oKAoOxxpox4>XC?|lY+oJ*6etBk}!`3)%tcWnk=8FQDFC1)>*bL
zDa$XoOVaMg*lr=Sy7wY?R93c1&Aa(9#(dI0&bE4Jun3?Vf{2uam21p;acgqj7}x1w
zZzJQ-A`LGxF83i{o#iLZGfu$2?^ZFVq>rh)=Mu=-3E!C;AhAftyMH(JwrNBuHqfG+
z%t9uUMn~@+bVnsDP*T`Kzo`V6Mz<GMgdRrU(o_q+N!PIsa@y65eres<+7wGjWb)9j
zmd=Umdl9=sU{$BtdusXW*HimRUHlZ6VcRBq!miJSwu`B(!>@8W!Q#uijmIH?6L#Lw
zU^loy4wy2pA3Tsm5j#rT(i*B<*NacGoWw+|AHS=`od37A$i(436^5m9<Y!wBc=NM0
zYV4(uc*tHeggP>1UK;g~$$5#?#qQf-JQ&86WI%mT$@ConY;2v&{%JFXafp?_Xxmb|
zsPpo9XIYw$P-bdvC|j{S9rd(e5M3CjBmy4T7eeb^_a)bQS~ia=V&GlfsmZTJ&k>oD
z_i#EkAuF>5X0>Ox;A3d6&Cq%^#I~X!aZM|NmFRmHY<qGPA20PxA`oHlZw)7oi}yZg
zpq*e6&xhB-E}fkXIk=)KSG6p~tsOdo`?h>vw}yxVLizWL@SeRb4$XTT-5QI(KcG1s
z%)Yn~TMvB*pfN^a*jLkDLD}&q;{&z}bqtJOe{xwdf5!!MUDH{u>nJeHZW%%u7EgDV
z(Ea+03QgYUb05lytVBd<_c5BsQxK6?nBW{y99A9phB1VQUG+}=p_Y9h;Ux|y8SZ*p
zcoGW_nd0XSSsxz6Hpe&W-%g~)$OMnOo6|y4$!T+3liUEu(X)pyWEIOv`?$>HAT8^e
zuCIPsv3Q`%{sT^wjr`)q9(Fv>X<>uzWo|mco5zx3W%^(pb~p_et3txWMLJmeyjxfh
zABorHsS4{_5<+}j{ZsbI9u1z}QDteWYmEc=)kR--xz*CFu#?1}GQv0CqHkrIv{T!^
zvsfMDszPWwLsJrpA!prxTurwWdj%&Y<GlRXs!$7xY+M&)RpBeI^vSHQaBeF^Q!?>)
zbW&8e+>>%@05)^1dN=>On;wh*eP3K9FsZL;?>lIFRXqy@y;7EL;&*h@-Z@S%;+&E9
zu0h@*zQG)V)ne@7g$^07Hm;DgS5EGRJz!$!N$C$`DV*bctPenGXb1YKH#+5kp@_ue
z$KmiEJTm7{o0s?8udQxnnLC5-wVb7{8Bu2kjT$>(unNS_Kp_p|{|NA>4oB!hkmBYc
z_$aw3n}53neu&pF3S5fIRTKarO5qf4G=dE2r&LdCV{(i*Y@+7(I!7*gzk&8sSo9*n
zUz#ZwCl~KNeyHVzDVRa$pWgSyES)Ux1^-glM}=-OH*C@$whbA62VN1;GEC0DLa6!v
zxpjNDa>H4t05?F$ze1IQN`;j!o}+h~HO$Z1cH&3FuA8Gp3vRP8&IE{4pN<Puv<kO%
zOWP7mzYDP#0!i;?ZR(1aq8jz?N`v@|c9!e$3iCGo<uQ<3quUzzSvJiN+hx~61<hO*
zRRm|(dPknCsBRUQlMaMt_iivWrMX^Ja^3~VIU4QE_^xyi6sge#><#zCZ)1sUA0TWb
z9p7ua_svpc%51<;HV~?jsf~hWq7a2B@*|o)=s1dj1U(WOOk@twYtzi(dxj+|xBNDR
zp}wBFhZlifM1Ja$?*Fdi!iA#(KnYV|Glw=KQy$DL%Pj=1^;%;q$Fo=Sh~pKuZbbY$
zgOkOuD16;*jgN+*^KVq%Uoz5(0^g06o~cw-#q0@Kb;&<3BcaYXiUq@)OS7?SBNm5y
z2k##;<?2ciHhB^n5e%kO;y}mxBeKo>G_L@YhliEv^OyewNAEFUP6_7E(hJ@arpOdT
zo|Mo9Z%>ZvWCM*sW82p->np_YhNuO<KMxd4D4s4lIl4s@p0goMS0_%Wa3}6dY^vJO
zl7%T{6(tih-@}7*i7K!x%&yOlL!j*5lcO~!aXd95;!c~bq@Bjw8ZoC3Rl^G=+9Wya
z8vy#Cd1{30<kX|D&HU0P@)0!?x^M)4A<7@$4w@A)8Mj$ectRn}N6ZM|zfobwWH}>o
zG`A=aQ~i-!BkW|%8+pO@v%qQrA{e(tEz1Xf%(j>&tR@SUerjhw1?1ZWYf`oV*c+!e
zHvNzETONAu(c)5M(CzVHCe*c&Ed@zKPE6x|niL_Sy!GZ;G(Pt%hp@%fslgVTLQ!LB
zFWcqta9~EfRN^(InR*RLD4+(wVycy4v49msJ#D#Oh8<ip1rh*(+4vZULS|?pXFmUn
zIWTErst$Vz8Hi}~qgRmH<S5?@mUK>3=f)0<c+AfY->^2E)StwT-xUOnJq^J(ftju1
z>!Z77j|lGXV+9waOn(~aW91w>oRgAPJgre1mTN;vQhb%E7DP`Z_Fx()x6I4wPc(VG
z=ntzdm$A`YTlx632K*Zij_%BIys#^Awf^W?hcXgtIikEx#u4o^0NiCvwz{&lMgs%_
zV#Q7ecMtA{MU2Zi)5bl>GZ@9W@MiJRLLSa>(LNB(wqDU?TO-xA74rEG)@eGYDGDyv
zz)4jgYFuDrl@->-fLF=ABr9O|{hn`r<v#8OVC9FknYHqL0M=mT5nX(4A7hanI_;ks
zOI6KeGAIs{-=ZrT?DqB2V4;F*aI|CL_eig8FYADSuOuq0<v_Z8u=C>A!DlcdkptO<
zmx#Yk-?owSfC#hhmb(KM-5V<p|4x9)iegE*al8(*=DTSIxu>bOH3e9N?$1)iSx*M1
zV^4RT!`VToSJ|hoWDEaG?O>TEQ3zyR9VGp&*~(<XkP2414aL@doG?a$uLTxMy%85d
zA%QUx>F2n#d7ULjBzc>6DWz#m&kO1gyf~61IXngm>6v$f*p&yZg$oV10&%)#cAC8?
zz$fT~;PwOp|DT^i4r|eDztb45al8KJ6MMB3ObL2PbOT)ekP7L6E!{J(EAkE{3g;WF
z3m|rSix+6y(y8P@_7;<R!CD%jTWDA<f0f_R+QJ~psv3iR9lFO<=D^^R_8`L>6b@ot
z;(y5<0zY><X8S*j^7ZA&W|f4u9-|<51&|Y0R+FJIY<2UbR#Cq`16}ou>vcXa=KT=i
z^j%izYkuI_wE4lNRGVwEtK)VXS9<~~Z<e<p{y0Snp=_}i0bu#Is}zpm=rj2r>|`I#
zZrSCDI<>gS)Qqmd0K-DhSuf6vB04H2n9Tz%R~ELOO^h*De*F~f44c4v1F;eDEz|y+
zrQ&icBYcn&!UN;x({D6DujJ6i`qRnP1QX1%Y>57(Bq{0A1C#7Up4qb*ve|VDZX}CL
z;TI6f?FMvNDvzF7ln&DGkK`=Kc)&GZT*e=!|M~+F&M&)ll+Q0+Vn$}D6Q3QP8)Jgy
zEL-_75MmdptR9}DpIZ;7d8&;<(v+-QQ{m{o+~DFVFSlu2BNWfK6W(F>a5irnXeH%=
z=Wrs8Kip#_4BOXDqIBfKsk!5#DA;G^t7$iXB$rP52~&kXj`W*7fP}ShYccET|Ev|_
zGdz$8o3Pt3id!!Sd^(BQYnJB>2q9WQH#n(8p>r9boy)h9$`Vsg>LGlHHYr$ME~rua
za35Fa-J+G{S3*D9Lv$4fk-}qn!v_MKz_V@2`6O~D9{8P%E7=*DX7`;TEArQMjEo-Z
z{K=A&HCc~BJ>KczfdnBr|LBz4)d~LSlNmI7%C#n~$475wYAoN%zH#3F^*Q`Y*`o4n
z96QlI@V4~H+#-x(jtn6QPLIp9b$_-aV4v7*12G`-i{`;N4q1$gX}Rv#nSUeR%UV$B
z?%j~w&CQe8gOwLRrfMn-ge>Y)7A|2PEQ#(Q_q>;9#oJjU0?~Y>&1CP_0<}<{2|trW
zRdFMqgez{d`God+NH*{MC`5D{^Cx8m)#OkBM7N2lSNRjwKSx;%bmM=3kxsF=>BP-#
z+Noa6Iyb{Y*8NZ1wU@kPO~!4`?XW0U9@nL{JNOha8uQ2j0(sCox<#W0i@K&oLq7?A
zV;M(9H>}df!on!(K?hd>1m$!w*y2-=e{7BvJ3oOUXRmrnY7fons=UD<rNG4(4@x!#
zUwMh`jyJS4PZ1qpOV}ej5K-ac0DRA-rMi8tmmFX&G<g6}n4Q+;iec>2To{vhqR!r`
z4*flj%r<(JASTr|3VHtT;V5&Ilokj!2w4@GeGh$}%C22QqpI~_!HXy*4K{TShhf3S
z@tu-S4s$%|GK*3hI{5q2Rd*?WV8f?7L6)ZPJcDM@p^ijFmxCx+sC_w;OzzP6yap(h
z$Jg|8D91)oTq=V~O4WswsYdlv;EW2?UDq-Jh&z6;4J(sY#OcQ*CB%BaY^3u5?3*_u
zbt-M;D#G}xwG=ME(o^V-JQL=ND*eq}4o5%SpMx%2UAo<PVLt`BrdOkbJmUBA<>;yO
zF{fG)WD+c$P3uwV<mR_E%M@h43FD2S&Fv~pFanj})t>-_10&m)E=_G;)GdY3@35@I
z*SsCOA`vlJwU9XZlp6|P^5Aw)gaifZd=}tqfu46&`!OA;rBy&cv<vGFPVD1@>#Fr}
zh1)UXOd!XotmZ#TSFfC#l@NR}3r4;`=9Pp@XdoWiRFSTSi_<}lI8jnS!R|5vZP)y9
zm|Fsd<Z8B*_&0Uf_@R?PbHb93SRSU-&F)1HM`fy8H9A4wQI)xvKB-%-&a`vN8MH-}
zAA}6XyG%K`rZu#m#F|jmysw4QOxl6f3J&@0g`KJ6;yC<a?wpK76^ETd+2q01ata70
zy!@-JB+Hz(x7-jW%9{dp%(G0jHEKLNpYxEI`)S>4!d$g)IixHGp?Sb;NOR*wdv15o
zu>uV!{`?<`HLs9xr@FCs94Q4pj&H83wa5-5&r2Z}=5E0$b2`JaU;#LAlVa83{KH^e
z*<+bNkExrz^94&%dF*L~4q}k+lv$^PFd)n=8)eKJ#FvjnW~K`Jy{G*1(Vf1uGCqbz
z=bRkEz`ahEyYlj@jN`c4m)0kv)81$_H5YV;8Z+zq{kjO(N!G4C%T%FOM-8trhrRNR
z8ren(dGM+(tAm(g9<x1ylF046u2z6leD!)fmc2k`4QAW`j;Ufu2<&7_kSE?a#gbv!
zKRYkWNRZ7b`g~up7{$agzJ+Yeb!f-y9_VkTxAL6GW1V)9R3vQ6$iw<dS<9IsPpwc3
zzs`)Y$`PQG&VUvkC$8klnv2-)c<&|xQF|_9GJ+Psby9i=_;0eApo0R!@v-Z&7MRRm
z=OJ)35#sQJ%=BuCO~@<s9>WdU+%1(&v)g~dGQ^zx-ZstoQSr8cfS8Hd%ylBq5jOQy
z(HF3qp7>T#z4w;6>u_oulqCP2hWwwzL1LXC;<nb2*P`j)(UBlh>TurHHP3&sG2auN
zJpm{H^Kg&@9$R>-+>B`&3+5vQ02!emPK}lKEz(M-!=-1G0kzl2<Ig2ANG$s5Nhr<*
zn3?;KcTcZYPGo)Om~rFKdn<JO<TYuAH?e5ojhRfA_I7%Zi#UD@W6yJiCsB)bIX|Ey
zKsb$6(Plf+5#R_pBn>W1x<hG44IBjWo8rBvV>y`9DvQuBXQDIOMU1oy1eho;izql5
zjO&PFCL~+pC<>JNI=!ZT2<dtn!3>Bbm_-tWG2ziBMNutFv#Kk-_ar4G2`Ys0)5A$o
zUYgfbV>&hQh(L_uW8!)zs{68RYNZU2X8w(o4^tzx0ASPz0|73x#o!&q6UZiiqK>{0
zok%8+GQC?Rp!4(bVtN*vcgCqNo=`D59)1$CQDmm0rD+9SMLiDd1Z-yu^(URBUFSCk
z<~DI&=R|gd&dwYHC#<21J`<S{rmth-kWEAqIs6+1%xe%Z`f~LP+UI|YAE9h!B$x&z
zN^f_P(lo`<&84wn%NN~)8$qxMs%-R&I0Yh{+Z&(!l)625As4V%;;N(ZG1*;UHUx|o
zO@sPGS=<5EUMMRvCRNnR4pf1NUwnxYpf#at@}N4H9JSb+FI9(m&#jI^ZnaCxZL<Mt
zO9$kMpVRNN8~bT|y2-n_B=>4@wJwc^n0%<^hk6V<HaC1K%W0KNT2p?4<B%4(EYfdw
z>4#fOw<#qI4S3}`rIM3!XYfZ5a}x#%T4jPFTMCjF0LS#-T0I5{oSwHZ$E1pXz60e0
z`FCMBk;;1Kwz}g3+_s{ZH2lGhNDNrW&@1oMp|nT%<x$r)I-upwTRXWFut=-6O+UCu
ziz1hEZi^)`=Xum6oDBqP5IWK0mp6t*^{4Mh-&yJvez+r3$1kd;lK{xsel0N@@FNnK
zwemW<3roS_E_k2kP5@*J#RGPp_(Zdqo?DpbaXej8xD9uaC?@R=2~<^qJo9<7bwCNR
zX%g^IfKHdgwAd+|Z0Rg9<#It4vnL``eph0e*9r~wGQ(Z;H4qFG1dRu5vDWd_cbPiX
z*H|Vegs{<!GXfY|o?_-qv%r+&288?@heMORWH4T4b-n6#JYk%u5t|Yeb<+s-VcNp$
zol>TcXcU>=wmcNkmI@I@<G8XyQd}f;jCa4Mmq%*D-!q`{>(=lfxevGi53wUnOglQi
zbj75wk6|9a$q~8o?ZIa{r;$kGR(t?e4RnT~!#mYSUO$VX!u8!3;#8FEa4zMKMo75Z
zs+CRWWQ7&>WR3&$SN!=>(lEwSmi-uoa>pGH50zpY$fO6n+NOg{Oh7iAZ*g(Q!l2fV
z0PVd{)OpkCg#5r@a(NU5Q)g{CE6Liu>}Dp_(Km9VQ3)({QywO-_F*!CV*=^^za@6W
zNR7XBx(xUYPndP@WLJ~|G_+;Cx9B#8o*!;$M-4TYbxFS=k^o|Z=9^KaGl0G#`NPIm
zknczpRUkPA3_9tyqj6B;6=_!dGqRsl`Z1+U_UpJ(sf8YD%P=5GkNEiF+_CbMqZ=r0
z<jh73=a1e9g49_ICCbmfV&Iyh(Mkg)4tGrW9%>lYw!5amEFwUTh%edR#3DfPW<cP@
z6d+(WDo?p;pfNxo7@Vb{9|Fo@cEmHOBVTFrLVw6m(|f$kvcXB)u$d%HvGRbA?V((A
z!P&Ow+wubIwDKJ)yOSM;Fvlu#*RE8>WZaBr(0QHP3Tak<%jUXPhQ><bDuQ+F745m7
z%)PZ>64;zYTLT>-)&3)kKk2E#E<aKz5g<%M?fU9f{`zwH5@AEM-CqM+CervNB_*^b
zL&PNfa1AEg^;+HG_vIY|=2V26QbiqFq9K=l3FR_N$jsnE>f?Md9VAAeNrAAuxB3=+
zVW){}rfmp-qHsAXU>($nz(3@jeoz*(p-^ny&|UyuP0^dsqlia_1G(mggD|0)BXxa%
z?NUytl~pM=9RQxBqF9SP1f>(AFv{}?F5Vd``nv!R=-J9QAeMKMpT}Kr^lUD0v?8+)
zO_xf!VJxQ-JKC2Yg@sy8fIJh=tR7Zn22vR@R0;!C@s&C<R_A-hUOiN|pzk+NP^_i+
zY6rl$+$%Z+LHsKR&9>COK!L63R#CS&trB;{7sfyWeEkz`3CeUD<x>8YAM!N7tcf+8
z&y6-e6;&Z#vCe?=OP?sh0y7qQ#laJ<xwP{B(1<PwOK5akX+x`O@ID%jGPZlb1XkgY
z-?B^_*ik`t9sqCS$TzD$XAOB!Q@rh^-*Xopf)S^oYj$?@`MZadpHhH9KBX50DI@+I
z%`sy=q40ZFqQ>i*UZE;OgOHD04jk+lj9?W4-3fV4!%6EL45J0G5(PGt|12hPJI7k%
z@~L}sOy?q*pIcd>5P2GhO~90~2#prrt2s4h*46QsqHvX$K5IkRCvJ$=0Fy%Wo5!Zr
z30Q98vEI5C)np40R6Yev{biJ0vyLB4)>S>E<QX#gi(c|PwH4~Up?o6+X-*Z~=6L8B
zV(+{3%Ph@Rc<o0{MACi>*}k1I10MHewEEyNM0E=uDUmjK)8KrIHo0ix*NnhEjLp;x
zhvO9VQOb*?W%+iSUPbC@dGSzJL?w+{^ixLqE9aQLOZo=QjpE^VOLF6rceXyG4!oKD
zWo;i2aRI2ILkD=ou_%bH+l6(5sMy~0<A7RMJXfrE&%W7*O2ZU4IbV3iIsj94Q<e!v
z;_Z&lc_X}K-hhC!=BN>QgbpcSSNeExr)j8b;bavxsI(rt0^6^zb)Z}+2g|!az?+vs
z!eiKr`83D2Wylat@yL}XO+ATq0HUf930Ya}PN!HwF3T_+f+Dm!UP%8w5UUqegcOTP
zP0U`<Kv()thp-x29-ta`z)pc7-&nv0TJ$66GzsHhYxEt@rEZtTDoggD`fzh+#CMiw
z7C12T==LG1PTGv+AIXClG;VZ^i!{mg9pJ|WrQxZde`B%@<BhsD4(EG!gZSED?`YWe
zB4}{N&-qVevXD8-6+v)X0;{v4%D-oUY(8)JjieRj*(}z8#keF1%FY5HT*uePE(>@4
zSiJ&emO#`5;*vQMhbYvAGCmNy9xoF*^&#=)R(@|e4VXJs0?WPwQBo~DKJ5;1-0$&Z
z3;$$#!DxYa9Bcreg@Bx(1!74acC(Lz{)W{mkPZ(BTQVp#*}jMw09iIT(IkN&M8gn9
zf$6+?j?gWC;6C@oYOzhlhGY$V%CGTT+m%rwaICY*%R+io|NqF20FX}l@3A5wlR@vY
z!Ra}^DMSUYnBU@WGtv$0CvJuwZpBy?xi1RUSU}d2NAp;~XGapoFE-M?^SZV0Yf|Gy
z5_a0@h#d0xT(J`GE>B~|vQPu9GQ;#ZNVQl#ozD9%5jmh!EhC;R>UiI+Z)=mD@y}RD
zCBa||cXLa-eae<_t#}_L6t%hod#uq5KgP<HY|~hA4ygNml&9WycYeP}pOCP`w2mb~
zq{*vG;A5`wE^#k=ga^Pq^chvEf4FQ*9(NhX0ArN7v=2@z5A9n*6VMyAOciQFX3|Yf
z?_4Wbi-W^4M96#(In78|XmmD_U31Sra1F`Ya<yj1pyNCHSd%>6Be^3r_D1lil!g85
z`&|wu4<3NpUMsqMxfQD>EUVUAu@^)feVSDMVlRf9mmmDJzr82Rp_0d2_eKcIVO;X6
z#{IBiOqrtpuz@Taf%I3GW9l}nySQN^Ka_us71zke9}W2z&SPfzO%91h08gDb;<^`A
z5}-21J;jobK&BG}KhtLtFhF@9(F(gpkl@?6eacTB`SLpt7??NXmLu{WLDBd+A0vUl
zgr7gfF9i@oB^-EfUSg`XLj*;Q0;WM<LMp;%%Tu<Xv@#|J2$>X;*Pxmj(p3C$A$Hvz
zST+jLiMt=U);kE^bWLGZzI87IiyE&GNtTay77vh06MsjiPcPIv06Ow!BMj|fN_3GX
zhy5R7M@@2US04Qv_^o|(Bwet%j6Al!9uhMb5_(^*_P2MRWqe4B3=CpXe{^2Kq$StD
zWW*%(v8%bu7u+o3d{XZ#N_xl{#gB2ee=LJ&9az1I?P1jY8fiziPMgwXO&pm6j+E@4
z7Uya(1WJG&wu%j(pkw}1Dr(ORUJ9CJq|7^s+@L6V)I|C@gb_~P-;nlrxqGu4yq)$m
z4?hdB1Gd)Oq~XQYj&Dt%Uf2-Eg~#CvSAlMOE(KdyzP<J!_?IHL5MoN<w1G%n_L$hR
zR1YVwo6h?aS2PGV6ngV<)z{PhZdrZ1J68A>sRF8;EWS~a20w#HF8YM#a&y9w5qOD4
zlO>(%G*|E<ineyy?6&#!{2)^oj*^_4IZItL_V99!Ie1!73xQlyW>xB*Nkx1BN0wr*
z!oG5F$GkbTR#gf1WnLyFSL!KhVK(M6t!8yW<+rMD|J6y6CY^#hDu9kok)Ck5tq^+S
zIOacYyTjoM&NxY99(gaU%yzg1D+|@jVFNM`OYtfQeMK8JY23a?M*AM_HFv5q-_#H%
zK2Nriz|hxAhgpMOSD9+9e+q>`iD6Q|D8Y)hpLz^Cb-J<)bvM}Z5SAOM<0GU=qDbYn
z*dOPJpdwY4DR#AD8LHCB9*@=H91mJ{<L)2pBfNV&hb!+MB<RjH>M&}mKcKhzaTm)U
zS^fpluM>~l?TV{HAJ~beU%fWS@#CrSeuVG0e+m%J?y#}ostG6yJC<wyT8%IOVxDWr
zTkkW+IIo)Rv7QkHf{#jaIqz<7Z#(5qnw`!SwBegZufNn9DhbOfK!$E$86wa!k$7`J
z4Hb!Vjf3aZPyoNZb3n)v9O8f;B?g|Xz>loT?FO@nB(b{dSvfo7^-aGISkbl@*Ll^G
zPU^tDzK+uA%+qpV3dETpgF-WybLK+v25mQz9%<Cb!`S%t<B5zt>l|iZ7!x0#y)pso
zjEo(NyZm6<=NA9onK3+#Eo$p}F<I1W0V<ic;`@3ArtPN}%m$!T1J#Pgjp1|n6aC?r
ztoxPqyPS2sgEj~@B+V2K*D&+lkqWT8>T%twYYybLGX5BSFy4F$yQgv2$=6S)_E1we
zxIt`;5bLS`^SIf>^N>733!^_p85s1Vbzr|U<7s+di10>X3?=mDYZyUl2lzaJ$sV$H
zpB+Zp)<;;%e;~$@|9+puUonSwDbSvax!;tn(LZlZ?5AZY+`8ddVGxAdYOjJsMF6K!
zqzZtC3+jd;noe4eV~MI<z+Wa3`3V(3p^@}gLn7YOUv^ihPb>sEq=>qAiN+0k!K2?T
zj|I8$huY%cR_`SCa9wzG%yVZXqw5rVs6Taw?=*!z2{|XAW@^+FdAg#;U!9~V>#A_9
zj#<Wio-!^XMOR(L2(D;w%b<`RxwBL57KidPx{3_#;zW{nK-o995_lGdp(>if&=s!U
ztmFM3q1M|?8QKJR3ot0jCuo-_Sh@Ey9z^ZB@*^(Kd(`6X8Ba_DLDzT6UuDQy?vM64
zeR7=bNW-(AQySDWgBFMDPRTa$y3dB9?#+Vjyiad98!=;;Fd&9i#|=VKHu~hyHv@Dr
zNO4qHU5T{1aBA3a+h)ChJ~J&DS%_M|bMyKRtTKdrm$>4P$-O+vP;R3Uy41%_z;UuQ
zJKVBh7cH)?_fPJWvI(*KtWqhG5_2lJHbju#<}gfxH00NIj+jRR|B*NeR*2`^@N6d2
zz$y-KWS5y`!nGU0m<dDCMgxNBC2Bc<j!dsP=?GLooJQ!AEXlEjP*6x{Nl0;|GJDvR
z;94UB0Sz04Q~khFL=-(Wj`7_9A1kEWq33#h2rRhEu7Oebg?0(RbofNc?Z~kxoD6mm
zX1Nt))TNx{RK6=_{o1&KgklE8O9lC{=*n<K&5$zIIB}g%ZI`ooYYYGIB}p!KA6?rr
zdfrT^Yil`Yv(9b6>$|I&-?y4*V7is2RJ`LU7Ay?xDtm;Q6Hh2a&e`P6?gvQ?I1Jdo
z>Ws~k<-+`xs#RJsE`xrf`afnVVOpk)NceCgST8w3dYMkbmVq3Va(Xwx`nV`!1Gi4d
zIbzrsbC*@qKJSp1t~Ai3C+L5R-x==Jl`Do6P7$6Bk{x!C>V61ZTRpal<z!~IFRGC-
zb3B`vA5)(?PDk>!YU*Y1Gq%Y5f(FzLl&x1Uv<0ur*Og-B_367ToA`a{a;58?!<z?L
z{q!uu<+it*wcxc5WC7$8ss-AfE9y=dZ2O+3leTr&-EN5FT&aFI>tb&)tf+bj$dU=l
zvAQ!k^kH*z6{zuk33F4ekcFN&7F5SsCMxDSGa3;EGp8UsaaJQfK6UlGIuEvp48b3y
zPsF!)X<X^|W7?kuV0b$waQ3N@b5R}ra|fAktJWr3O^*oj<G7Rn@6IK7bWAjbCzqyr
zKHIMjbb}b+Uxi+(L75ik1zb=K8uzp;jl&Fa%{9(FEY}$aDpc~aYzA&}J+b77Z5uNN
z<dehDg3#pCUiX`etK+p&M^58*pQwOw^aqQ*q+po$ULdtM7fabO<EEz)DvSLcZf^nk
z`9k1{+=}1m`-P!5GYI0v{`O~nM}}UhG{C_(-YVe^@{=f3g>Z@;7@w>?vh__Fbos-6
zjjy~n6T=iF%{LZ#`yy&<`p^!V1)N{c<Y>5ZQQ4&lSg)|y)#p7UP1LDqNF%lie*?yM
z7sISlsWIOaC1a%9O0W>bc{gSnMDvTsL7Ic05Bqui^}2j=$*9-#IA^8|<cpc>NB|^`
z|BxCelQw*CAhJR1asfR?k_ELSItSIE6CJXNm^Gvae88Sunm&f22X9qd@P+CtP^@I&
zHB4P@ebMVr3=uqgr6ns9(DzPFO1i-amw*Z!!R7&ymdn)MHHSyl3ymF#3SGpE^U5LO
z;0x9kUS}$42MX~S-EtLSaua7ZAmT>gmGtye4Ij@<WV2D%ofe|Gqui{27maSYnt)M}
zIbkHK+=W>wFnh{6!F@MdBhcv03?IFI>A|RA<QLX^0{zPOL0}W6QU1m<CFq5$2812Z
zIkwwbrX|zg0A4n*wWS3DQ5s;dk;-j`jR|c;w@<+fa!F05!{z^=n*YOlJ>xCoN<@zr
z1yP|3cskE}eid64CzK^U`ixvqfdMe)>Meo<z5s<O_dLjbRxBXA0l!3yYKz;NR7~)1
zjV^7LiM~Y@I}yaPh|l7gfhe)1YTQWPB2~bAxO)dG@rS8Q&?pM*D3-Txs;>KopD@<o
zRP+-wBFti&{2z^PZuA|i?z-=_((&i65e5Rqjf}dY;qp}f1(SjebWe@RWFO!G|GI|s
zB_o0O=~rm?RWNPaJmGu>b3sYfW4fGHxRS17UC0ReJEUxEbMnH%Py&e{+vpei4fl^-
zI(rcZjju6m_=>%I{VMV5qZTB<thkP?KfXmHuEl7j)M6J24J7jdG`wyEKR<6XIP9@|
z{UL36N+dnVhZ|8#5%~{pQGArn>$7)4^BE<Vs>Mqjeqp!`01OnB$(U1x&a0QOppXiP
zrdDD8S32tG-!)zZh&%1q4xsu3iYk-b{Be<7(y(;y&3x5b_=X*DZeZaJYR$36O?8ie
z0;JYQC%;Qn70#j=)TJghbyv8v>*e07EY!N^7eR;li>FHSo#jXVt?&B7xtY)5z>CEy
zRir$053|5OC?PA1q$_B*(7S0?Ql?9J^^1C|1r9qN*w0H`<%%}#ON+5rlfK_B8#xrm
z;nwL8E#T;X@4L!*k|M%*N2=cKer+Ba^T7DCw-~{srvDHM^oaFc9Abrazs2cvBd?qo
z(7cx^Wf)+<kLlp?_$d{?#Jn+Q+Hp>dQc{N%o`h4dMp*nSwD;6A(tYcaxvJo7G4Oo(
z>HF&Z3%{GIpR*;3xc)RzaZP0XN+f}msRnGr+oAcz96rBwL3*u3l<6A#b2iM*(fE*1
zmafssMXs7$h%A==m)D=>DcG=b4#CsTOr$xy2Da$<uqwfc=LaQC8Zy>GhQMh0gguXP
z@|Kp_>csV&kity>!;`I+8e826A!-!xxeUh^*0kM2Pye9BOG`IrEcEx2@0na;@k|mP
z)BHpg7yKI3%y0+2Y(_l$OB{Gk06_Gl<B;924@o$Z-)<xHIQ2-&!L|1wlQp%wj8-Se
zpbk%}8%^83u9t+RdqH0)!b7rmAC{73p`W|+o;*Ae?cRff4(UkeOr;CG87fjqfj%Bh
z9mo>_RXZ9S2{6#efN-BXgrD<@$6jidoza!8eH@i;rY}0y^Ol?DpYQUUalY_jK#W`(
zCJXs<o$TaPM-o8n&M~&@*d%jppoj=0X5%`N7l{wO?e8i{>;8K|;mG{co(fTnA}oVS
zaDw872KT|y>4wY3P)7o2FwO;TJ!}I<QO<^FPgvv?eA60S7sT8VyYoQL3}dwqt|;<2
zwRy42qD_g5Tou29NspvAo>OOtACD$$bIm{LEfywRljtNs!Vn`t{rTzbX{E%+ZV|Fz
z#hq(=%#0F+*bN5$WVF!PCC&zIsdy6yVxX;L;5(q{1W=aI`VxqO*0bVDFDm>OxLJ=^
zLSEc!g*^^V`?tV&_)sm{$NdYh@B?A$sd_v^DW*ZO*b982(K<em5$Ml==eM}B$FvY=
zbKpO`l&3rS2rU5u65Gn@|AY)8<YWBoN+On<$=N`9H?_4r-xxnuC5nHdNSf(r1pb^T
zMS~qg)JK)D-oX&;46poQ#3EM%e!lVb{ss4;2Bil<iXuVX{u*R#FPYXAn$+CV8zydY
zUD2mort}WFa^&)qQ|W75o>@4b2o7$L1TH5jzPXCO-dd4#_Mx$`l5p36Q`E)Svf#N3
zqx2ZI%$bbbjdQ;F6QR9*P8$^gX$7w;D4M;DO_eAZgf{(X4r<-$l2FRQDfAf*-kg$+
z0%Ka?dYoXd3%BVOBQ0-}DC5~cUa=~=dPeI0umHkx2ied(?K#dqWBB!|-6n{aGO_kZ
z+6PIdq3p9zWG&33tzN~+6$N$!vg=b8n<BvHmyOAV6HBUIlGS|l*V!GP-XKtXN1yF!
zfjtUR^PXh54W<?48IN7<3;{>l>`g$q*k#+u*js19@F!3TuHb3mZ$_TB`cP_?&hok8
zETGSRtf?I3h1p5w*p3N{E{|W0;t>f}oM>j7yzS>NcAWa|qD&;hI$mN#Nub_kO?=p_
zEgT?C`_#k7z2>cB!CKY;=V2jN*p_r1QPc}xeE!|TE%V6hc~ckl<&eF@{n<~u+QuN;
zg~13Hp<~h;h&C!m+c#1iZ?Hr!M_(tC_srmULtyj*L(tZ$o;tp;iB+3RXv<EK|9yF$
z>?dD3T}7nnnUdvU<m!pn+N(HFL+R>Ako_RT%ZE@Rk8`54m(ky368rdmuTu3?J)&6b
zS9Z_JS>`k{9O#@}s3--SdS~!sOVX>XFO#^BM=E|4(kTQocp*unoMy|B^<ha}S(wC*
zGQ?=E%%_?1o8N<#(nFO@JFe}^OBkvQ%&9Av*8QZ#)njh)p^`4TGgfmH_)Th(-J1N`
ztGwvqfbE?Ow<yO@15hs81}O+ptm`9rJ%X+O?r#oIoC<+&4X>k3wtmJCJ{2Ttqn)BA
ztL#(Xnm8KH+AWp`U;F~Ea_r&8uV1%9j1pbxu(dZv#s1qI>*iq>J2>(E1J7K9#o<p_
zoH&Ygh>H&^^q<Q4lCI`}XWN?p=i_Ard?TRbG;gB(6oFWM$ZH3pz;MoX-vZTg&$%~N
zb=8AM`$HrcFD_?Q+ZPTn$~tC7P#8b=P8$c?$hN+Q59<Kn_4d(vk_|{YG#qpeHl8MJ
zV~bz^nL@A>JV>pr%#W5-k|bH|j>@Dr3kY5Qk7u<4Vkg&aM!cI~egQ&QH~qz)&*%^Z
z%V@r$XH8XwJR8#*c7p~iI^u785mUz2HSBugMKpJ&T5-J7sxOh)o_A_iHMiM!cY33P
zkeJ!@hwE&_nTu3SW~T)jrQ3i|5DW38F5b@@E_vAbL!HYkIF$BjZz%!n%tV->y9N`V
z?rR*M+Z{K7{p}n5_({Ext}yUinv@2*+|)G;r7YY9@H5xDECh+$l>Y{Lp7&iRw{Y`<
zxQy^-Xlrs>f}XA}P{wfpn>y!&!K*CsUAT-X;~|s#LfqCFJgurs3UqbY;_e%Unkj;q
z{bb9XQ9zf17<^ilT1mocku6H!+(3}*zRgfYWz5MfnWkvLcZ(q{-hixvu-da+lHIut
zL1@IZk+&{9SREs2iw_>pb>;?;S?Z)zju=jC{ns*v`WkGdWid<aawE3J!8_tXZ77)q
zM5gljyEFFSV!23P!JpLXpf8ZE2qu&C$j-QjjfN-`9dxjaH1O~?6RgavXLS_^pjcB^
z?nXd-J7k#BX-^!<&>dO#fsKsF+imUGibRQT$*&cT*Ae$>4u%bd=6v7vl5V4UA5enM
zd{=$3Qaxt*J{yvZqUHlb>h~L#vSdcK%_395eYM%qUF{8h-eL`uYB$Q>SZ_}TkZfG5
z8c*3-59Iz<fuG{vJ8qCr<q1gO5G9-JX0<ez;+rQ84UM*rYI1yt)=-v~dfnGwC)+-a
zVzerSeRMGF3rlt4W5>}L@xp$N?B!IFz}P=VZ2k6SLGvi&xVO^Rr*)M!E)!|l__EN8
z+UF>=Bd6zUrefB~um<XVdPAdd$M?+oP_=a<3=7d74mVFY`g!07<&n+8#`4o9&TB5(
zi^@S<En-2TzGVWF+j)~FL|YbF2wLy7=MdiMyaPKWWe(tFbf#W6nRVGazdg8*MDzfy
zj$Nb(lhDOONQ`K7k{qz5!LxIx@|3Keo`4~?yn*}!r_7Y-4npxCJAmoZb+#dYWlxhy
z694k;6d)srWff3etU5T2+)&mWMXaPLxesP{NG4mL&aEKn&{{#KV`;a}-Sa~rT{Q(7
zypm4VNZl-$M>lWSlpw=IiAJAo0i}iFoUa%g@O7Ed;G=Ep|1RtZoPsoMvot+ku3e%1
zH*^<v(nI0kB?<`dHRw}V*E1^&j=mw`Nr@nKDn~F)HXM(nasPv*DL!H9lHnh7cZ;-j
zgzg-6iv;=}1kAX`6A>TYR>##{K0-3}lB4X8@m*u+u0DsYNtdtzdk--|U5~sUZJH-3
ztvETO5M2Z$JsrlVA!Z3EXfErfYC`$S_)_xk(gt8qXEDE5Da1}m|4G%ju{$THnH#3{
z7KDm4zV^}8=OC*kX7U*GSctOfOG7#7&<Sr>FvDyt##+C^T3-R>DpbkHQ#&XWGJllj
zSy)J0vJ7TH^NWV9D03I}?}J73&mGJGl;$5hLi@FOMuLP{9j2Ry{%_KKm5O=ZiK^G)
zR18Da+<G&58ez*Xgb5DMlkS((Ml1egPS8hSt=59ID@_iafOsNcHU9`^FD@xXLh^hl
ztjz9Hz&#~)RG)?HzH%#wcgVVgM`fxv+RHxLK^0X^bC!nn*fILMMl9NSw|``Nm?p~L
zc4^D1mv&PqS(@MAfDk-ptpeimiWP|NV!&8bt!;44cl)kCa9CurJI2I4KbY-Q@bcn)
z{DL;D1W>1esn4zU{7!~C##kDyZkk05Hi~r;VsTFg48u-WL<4@W$Ft@y9B>3jWAOBe
zCbp@wzKH@Gj8a}#r1*#D{^g$4N%zjt6KRZ69^Gz4tJ=w@T1$Hs{vSr6C>c(LH_N-<
zfb229)n35f6h+s-D=4CIdh%n30_RNwTeY?nGC@68o!>3nR}9>^$d!a9BJl(|Y6?^+
z+yYcEKztD8@Yx19Z~0__Awc#n<SoM;v>Rrb2GMy=vyzAl_Yg|bzVUS2_;k68??44j
z|J`2wpz%+PyMeu7xvW@cRo&^|R-`DMC2zVB3~|*sA5cHDU$=On{eOrsOMTahG_M?z
z98f8iLkrr59siXI7kGQjs;<o#di^q&)VlwwEm37Nq0Ulf6fDEIivx{0I|WaLQJ;{E
zw=7oeJ^fL{^37USt2SI-Lx>-fTUWw0#2h(1O>IC@q?J^)A+|M{>Gxfu!|UF~W>(6D
z;#>44^svcs6%tObw!>+7R$Rzg6X^X<tyO|OB1%1yKL0WVja|P>gvu3AYIs)*<LCZ?
z!|zohQ@c~5ZyF{#Gor%*p#L{`@NPQ)$o!*FFDM__7*4BSB#iZw2tD*7Tna4j!N;At
zaY674pzN@KaBmbC9?Y1mu~<;}v(fk!{mTUEF6OdcwDA&#=Z-)AKfD54+8!tE-QX^T
zzQg?_<xl+*y>D|xVnAY+5ps@+xh?K`i6E$0yK|xutVB7ENdq|H&+bY^Aevc5f-kkR
za)I1{!4Jr^>-qb&Cjb!H<$7!oUPhBeOxgG<oOlQSzt07pBY{W^Wb&nxMHO8WnLGBE
z`eJFYJ!r%V(_yMPsqG-jV9JCd@I{&;Vg-vG=C|4nd?M+wraOtwxE;c~5ITgk4o@m9
z1M7*-R<VJtU83GPTXdYEM1GSJkp}2YLr-<aW4M({*$MGIsYU66eGj8Tx7s!FxCDbC
z)@@n<HMT<%g|vh~DCC|Rd*V8FvfLGZ%|jG@J2u4xztr_S_n_jz8Ql}%1z*_+BdIEG
zdfK<n*0NDpvzSz1T&ES<Jn?1HMv(r2ZCT%)Olcj_DgxCJ68=$<OsAd^t?SEMeMzn;
zC4L`RHwGzY6J#L2f}3X4iw81JR5^Z}ZXw_S9|U$jFay)VmC4J(7rYY?+~lJr-58U(
zK7)7O^Vf6h)yZP`3?#nN9Lh-$)W&Kz?IZo2Zwc2B`T|6=29N$M!@Mm%AdJ+k6m_OB
zIsvX*FS=f4N<{^bRW5d7+KhEnKnxt{^<i#{$);lE=YV*gNB&B-@P9d{g!n^zrE*$@
z0974NS)%tdBGA!Fbpm`dy%?4ER@`u#@jUIye*B0OiG6`EPrAFKi2M)3VNQcc?6(t+
zVdQ-7P-?cU!vFFQ2ckG2$XBjh#2ClPj1jsSmOs{-K9sNVg!LFiwSbf8^OBS7Q9Y8^
zE=5|h;%MQ==W@oM&W95A@a!{Z%#Q>V2PyoAusRE|Hes1mpfR1QAw}ff5(aT9c|pK#
zLzl~?tU4@Oliav;=MdOMfJFR+{UgP_#r2pPvcBJ(#kVzEPVgt76nM7ss(tpuCXgaI
zrFSR%S@^jAlvQ#e*jCA6!{A0G4=8&?Bt(b2_2WfQCmW$v+=y=Hdo@Lk1tw@P&4#UO
zT>rGpLA^H|3#J^gYus9hG{$edc^6UI<09w(h!g&33hm5Qr5mp2Ve|*_KGE;%85~EG
zGngF4%@LpR*WUd^E_0Caf2ebnd&;`TWC5XG!G_1xIu0o<{(Y#VB@)6e36sh>cXii}
zyds<-f_>%5&o`8kToQb>!N6M+sQF@wiIMIEuEv5gs<(?OFpRSp>+hYn^40w>ZMNsF
z^&-Q0_B;(?VouS+DhWkUf@&peOQ$x=nnl70i`Fg`d<)qAp9ncWpv(ANfyEe}Vaw-o
zjiA8AD3@F>C&sm6?OD)SHdV*{Ab+l-^mim=8HMOzr22!3qf4pT3%u<}Q*ECic>~vs
z?xooixZo*r?7SC@cx=is^^H34+Lal&2k1#PTwyr{(tTG?Fh4aEntV%bTBz*odLVPf
ze||dIMZ-nUH^#6Ro}A*Sl}IVGxD41&<Qp)EE2N)ABA|g|%^T)f5qlhET_+e;{&}um
zO;?P`;Q+}N->}+#&#F}G-(aHCfo3L(%c=b;YG`cAHqd3XI=Hy$@SvYG3cMBwMl?;+
znW#<cmH?hi#!a{IHI*B(Xb=APFGt|Wn;)geIS`kQvKEy>mZtdD#((uPnG`p)BoR<8
z>S09pRUh21a@s5#<VV~@d_cDouCjz6Ocv9*!;H}6*k$*L1^220*~7x92Yu8#?w9W$
z^W06a_=1$%P9?r{)MhseOCm6p949#~q%%!&q?!s_AysP|);u{MVWB%ctH&~n&g0Az
zv~?qRUBc>M?~(<*hdWv!q{!sW=~}SCC0X{cjpd(OKR@0`nK=ZHZF_*N5KWB&$|-QB
zjpx>h7^q5Ku-(ESKiV#KnSo52Tveb3XK<#+vZ5Vvxs|!#`MR&dmtY_3db|FEIS~_T
zP`Z{+o6(Y|m5O!^U1+7uhn7LT2kfH}8}0%icHqR(V_e-Lrq{Mri)5qysp}L+s~&b?
zz1ts~o^HRlg9K3w*mQ9#By7-n(OD=^YBeBsf-KK{(vm&sHMtQgj%n_26GW1XoB$qk
zV-3g+h-c25NcYWPYB++B)Ma)h!bmI8wR7ivC?&1!O%_<_{o*lVv9n~v!G|<d?ZQaP
z!%i2zJRt0I4FY@%CH9NHrt+8R!yuf}c#Eu&_8MX;()3sZ9;RQ;vKQQ&xidPOtxMvy
zQ2Y`lK`jDw8BqE{@z>^+gmUgK|8RVgMvCUM14PkBWct+Iwp)y+zyNUqCUE=b+Zbw(
z3UB!Z@y=Sxfse4LxI}8w@Dfdo7WPQe9tc77$J?-Gyq_3~CAUdLf^0-sx<D*z|M?oa
ztb}=Xt!^_#-Vr+)GxrIlimj?|aU*D6>i<)G@mn^XXUsJfn!V9BB3umY?-9mKP&~Tc
z>+N1!n{x(92&!^Xwt+arHl(M0J*FwS<aeQiEs|>=ubX?>8%50MdoW6n+<~;a0axAz
zu@T#9sz~2lPmLtWo>9|_;06kQ@Lc(3IB6`0wzVXbiAiFkbqT2mQmZU=ShcrgR<KZ{
zO-^#>sUsDwCJBCfYW0N~v3wB4R0}i<4mW*}f<_xgq@HeHI@3pRshW#@gFyC91PhR3
z58rMd|J0I+sd#}c^=ix;&*D>NWrG+-vgZlYMpV7itl1EeCO{Z-StqKQt6dKGvt`%u
z&JK~&_Heuk_;8oFzrrbbt?a1O2VuOU*R)+Vl`LQ8T<EP@Kv`z8--M%`ZkDfcvyvab
z@zYsyG5@x7ZeRpqdW0*|M6wyy68}5CW*PEfIPFdV)@nC$iKD&3W>v1}o5V2XspYl@
zxQjV#J<k}qPj6kSp8LdXN;E><eRl4VS>6>Z3liEBpN3(WPt<(ptbNtMoc8G+A{wtx
zp@3hu9T)y%rjS&kX^*G`xK~;UirN0p>eiu%W>dh8rVhcUcGhPsu@LV>V-dIm4x(U%
z_lx%r=IGSyvUh9)+!km0>%VCy6`wdf2hS%pm_e2}r<jeD>dbgARowbN!q6pUMh%yd
zK>IZpN0w1?<$==S0K$WG;j2NbN00wgXbE%%XBpAb{x%l`sVK~k^C+hM&t^p8){v_4
zFXr%;A<Y6Aygf3JdlfSsC1qe389Am&H=2EdiE%F?9g563nIXOkt{6kh%-Vpcx_n#f
zd6hp~R9ufkVG+%Cvo(qlbUD|?j-R~~Im1yaBj7r7qrM~;Eg@tAI|fG@6}S8?PYIVe
z%gKK+NUHr#B2PuX<2v=dFXems6`p=8vIO_@eP|LxHMd^gx8%^I3x5;R0Y;Yx926X<
zfAj5!rez^-j_d~IhTd*dXR#|l_H+KkvASV#l#VBIoI`=P;^=VfrWed4|0{TkVCyfX
zYCBG<KaDE|4Y^5>BC?Yn5{SB5^Xa`9kZ<xrfQaSoXr(3R=okso?ATLV+{y`6<;)*H
zF65ysuU;II^IgNvomQJ9%a+M~&%XH_v>`)81qN23YtP@LmAO3;ZQ6oGu&q4@kQ4N|
z0+P-W=;=u@{K|_4*EkyL1i!}I3teFVf`PNdQ;XAAc%4~P?)_Y93L?6x@4b`9g#y&L
zz2bHyM}?8I39JZxE|`+LFKDk}JR5_xZCHa4?t6tm@KYqr#j1zU4y_?_0P-p&BEqZW
zdu1(`g_G?C9av7fw-woDqh^?YwG}LzpN7|s+k9g2e_Ym<-Nn+wo$6C;P_^W%yH??A
zo8?;Vb<{$|;adFsW?LcDK)Xh#rf8rlhkBCxMzu~!#q04#j`q#NRn*TgTwE&d2R7*`
zS02WzA_JB$XaQdzLpW+fIDdg-vGLubne9icL@RF{M9~VQG*=TLPm{rQbC@P*b0aeZ
z34|BcmT+LcFmjF!<mUJ}tPq_0*+bg0E|lM*yxY5_9X;q%k4o47@6?@`+qzx%K8#SU
zfI5WP6DOYxH-vsRke0PAB%JQfcVxL51e*<c+3Rrtz}m$#uz_aE^=QvuISH~-BJABj
zHdL(z`^mhpEI25r;_&x)<vHP3t;B8ZTD&e!^0fbsw6kLErgUoM9kWx!*X)FyNve&d
zIlB6<Ubz{n4{UmDnJeBmlgMz}ni&`=hYLg<jhFjLEs~SuI}+E#h7Dk3D)<Q9WcSA;
zfsA1pKAoQFQe_aaVtzOydtw~U+(j|Mku(cM^jp`4Y_giQG;f5KIFVXl$s>IRt^un6
zy#VBXjv9tO<W`S?KW+Jkl)k$kvyXa*@S4jRSbd>Z@-#+><@Awm2)O8VEn)<!cZ;8k
z+`1zeckhtR%C1!A8q44Ma$Bb>SY0)SwQz4_0F+k<)=q#44Ke)?FF?>OCtEe!5Az<T
zXNFI`d*0vE#v4t+=eVz5g=1D#s^-=sHeofOa2YDWboN$K>Y#{$j(C22P$^0ugAgTF
zY}$)ST!BNVLJ{B+PgK$HG(W8o`*CYs`*9AgV}E9@jkmB6bXdPB1fjjS&wdi-8z^sb
zQ+T-cUKC4Ts7zwcOZS?HvXF?io(8;Tt^$f@59?<dQ4U(d+?QYYWk+K>zdS5xjp<kv
z$2292YV>R33hk9tEfg2*$1k{1yk)miVWK!5s5hQRWpi@qvNpRd`KJ*H3o1dCc&2NE
zD!!j_kA^qi<uZ6?Nf0&0o_Rbz=}0RZW)v*!`M|#lY=KbpSlQ<MU3yG(B*rF|hRH9X
z70owwKMjxoeA=FJv_Kfpr9U#fY?w;D;zg_prm&k>mk5NN8#EYi8&E1+XV6^^l<h&R
zXAy^+m2itU1?&Dtcznl4@I}p;6(#DLmp8C8B_eQkbLr$PS){{?tI(8<5j1VVkEMv5
zhh|b6C7`lRN9ETNyyO#w`hgjzmrf?;KQE;eG3E;_7R%sa#mCyzRYtw9JdLYsdhof4
zFpjYq^+ROJKnL`V))xF#DkH^GDETbelrV)}^YX7J>P*Qf=MD@6XF<P9ne4?@Y7n`B
z*FXpKOfv*iY5M36<K7w2!ao|9Z)0RB5Id_4zj?;SC5Al60&i#f@M))8ejlryY0kGE
zpe?Q$s1@by0Frn(2-XK5OXN#_(11E(NroJ_W1HkiV4T!kW|d+R7W>c(z8`!1-3_E8
zePeZs9zP_%y#YX&|Ggp_{k?j>(O)h4!B`o1;fl)DD*(a7e@^WGJ!I{s@i74e<|vMW
zE0X;fkq>3>YuP7BbP+EzuNcnqa<U=x%w_OQ)|m=jFF7klho7~ADmGm*36Ww7f>}=p
z<K6=VbHefr4=L{GGPkC-I@U4uE>voPPhre=PXnwj^4v_GzjyWGzuK7Te^`zEh~^<$
z$XT<Z1%Rrq_+}f5iff!LE?$`B6V7$@8A>N}+T2|~y~CB>+&H8eIM{!I3yy!LEl4B(
zwnQQ;72?*-R*bSbO_@26<b3|uceJP^rs&Jx%%Qv`IureZ=IVytes2DQS9~BprB>>0
zKjFXDo2g8c*2-&xYyPBIc^gqgygJ;^FkhM&CV{@=SG?}TF@B3$*6~(^%p%YnRrN~J
z!7Q*K#36K}`Lq%eh$qIX1qE5U9N)XKFUy`Hfw^gkN*H<dIR(wuVx<j56a4+-fR~sq
zQy9-L*mbgA<vL+Y;?>6k$<hUHXmb&9q_0x_&+0a<pG1t;J#xmDq*rYvE}wtLG+};i
z5>U>?`dR~zjPO$3+W&qfyCbErM^fP8FP3!p(TuBfh<F|M%rjZ$Fvn3PH-S{y^a7Z>
zl)@klat>bOFZa``>>YDEw}D;<06IX$ze1w0%4yT)r=Qku<Miz^yCi=gPRJ#mzXZM<
z4xPiCEdut&9-@^iV$_C1H#>=`Dzfnhd0zrU%o*vb1)Mjn=tXvZj|&(NG+R-3R)HMe
zP^uOfhMWzuuHTupCJxwpr3RMGJvH!lT7&iLXjri1insSMg5^V-D>JSnSm}W5AV5~*
z$B|ia=c>PC6Gby%yT_JbT2uHJ!9AU5P;4ULHwMFI<*Q}k=DK&k#u~z_0)#Q~XRvEW
zP>h}&yc-`cdZ~82fwdyCHYT#bikxt_7up{?-`69u<G#rxF#=M*9ej6XHKT+rsA{qK
z60TRsvFAitxG5dp46S`wCoIo!<xRBamo$jHP@$7%%ECihH2i);c~%O4B}<&x(z*B;
ze<lf_JO~{M-CFq{eOU0QbkKpyG#64!fFPRR@nF)P%jVr06+9VoCt1Ge<U0xO80sQc
zyYf;NPemTyZ+m<sA^C9wjTIC(gub<`VnrSJF}rsFDNU+xYMCe_vzhgUrP~L0#OHFp
zZXQnFn4KIEsbScJ`Vah?x2uLJ349-by@pc?$B2BNrd|0<kYr=Tt9t58AUMznSCm$b
z@`0Oj4)X^(Z@myYRn^xreK=si9{$>Gl=ZL|nD>qemW#K`Pp@tiv?lV@8Ja!ECpm9+
z3oJNEGpr&wQX77rpL-z3Wot9NHwO#*z<3y>W|?xpK&HyIoe}OJjBOkz>ZS3>m_(lC
zF0TSct1CpFW<Far5F`R1gFnu7mLAY@gH>qM@WnPb+2dx`dj$4DT-lJpJL!cT1N+W^
zTj5!O&U;D>n;SKf^f44n76^K5XX;U3xzAvMlv}QO;k4<1l6TgF{NfU*tDkePsgR|P
zy*RYL8Vjp~PPwP`>{mUn4UH@oS>hxJuWL!c{xSd8l+8)KG~hx>F5N{PGV$m!6_KD5
zW8&X5(h<%Q#}#47lm~-OP%|k)105V@c`60WC}G@e<Go={-$5cU+YKuBP)oX^2r;(R
zA#Oa{4)x%??9rZML+PQeqF49YPu4(vd7(VtAx^;`7mp%Bcnluq-Yda_8CPrp;4&on
z`xG#uPZv_Y7a^{YM?N2N*z3BOLWvKtMdAbmp8(l&)8dyyEhx3k@>TLDThz`qe4po4
z#vb2z9_s^5Z|tpeubj$WR$fxXHcHh2<}|+I-t}@3)qOT<0&bP<*Dg#Oo9B$x4WA05
z<=Z?VTlLBMx5h$KG?~ZQspmxxAwj|GyA@Ts{?Lg8*#Tvgj~4OyF)apl4Yc1b%e8#^
zU2{%Zbycq0%?12sM;&(UQL`mLYGadxuIXkGXQPcbQM4T2Zd6bHY8&*W2gU`(XRboU
zEgmEjaOEHxjg?<rMbWw3ih;>6ylAw1jl3gH4hl}Q#mV5Q)9vbh3ueviLkk=<Wg8%!
zQ}ZXWQnN(LUVz^105gjGT)Oh^%wmCv%|R)8b@l(P)Y@7V#^%#5;|41lQ~i9e7*8YE
z=P9dCTgM;ehgNYG-T-e=%n^_L%xJpuUknNls|TQo8EGqY!>Be>giE%jx1(cxAOv+M
z6e3B9_n%uF^MvqAWywzD(zT`7DK3QdSlhRw1O8d;go3>k)lg&6l9w&K_yM3L!F<?H
zf4s_eKdo_<nTRa>{Am*yW~5s0HNd*>$f5(JQ*AJ&NvXBKG2d%JHS3L^7Nt=zV_M~-
zODa3aMH^dB_I!WjHK0v2q0rVI;^^8@Y=^QJ!UfEN6+<Xvd|Lb$9<B@m(kO!f3Mr9B
zNr?uHJQM!o>FDQo&+MfQFmLMjzGW(4`;OBH@`ob&f<(MGhBsj7&G<RUG>0+73yspr
zuXpyO8=3RccM{bTd4rQ)1WOb9GXERt2h>Y8KIykD>11Q&=~}YZyF^jd256u*J@?2D
z3=u;ZA|2L7Rs6p_N=8gH{`1TT;r4h4dDknEAEfI4tR8=9%zR>1kUw2(2c)c1l}=^z
zPZ-zF@PkKg+TOAQLiBlSy?^sYjha`TR$0X=!3(tXj7t8qPvOp#H16@6d~D#2SrK7H
z7HOuRcDzB=U(AA9y}RBLKj$VDG^~EVxdOQFtT}qd3wfGlIfsf)<ah0~Y--yA(VHo9
zv0n>jZ`e11vU~9f2+h>9rQ|wja|+2=9Qrkza1Eb=|A=q!VC4f%|Nootr1ISsG6}c(
z7xJGfbhRs}1pDHolGWrhgWGY^2mTB~4UugMLn&8Y1w4x{cfPp_S0wlYwL&f!QATW^
zw5@of`Ke#Do4QP&?i}gyWai>U&wXw}p+{1WLJ);YfO~g5G0MSX3TVp8-MWs;ZgYaq
zTK&cw!U&I^J7|Utg^GBMGkIg?SJanucFqlNt8gyES}BHigRUiQGWf7b9oTx@vKO-j
zB(hXbM%~SabD7$aOpj8F$h>^>vxjNhY4-wZNs4+4F^rI<>K9vk|NavLpj%2i0-vn!
zv3KF2XB_0P@8LYUIgAZB5Uv#7vbv3d^VuaGf@72=gu0RLOHJjg$78pFAYXOPDd{a=
zll&3(xUkz|>u{UCP?x5cZC!$U8X7%tGEPU6tBi9Axp!R}5C_@Gq+`>m_t*0MQqj%R
z*Zu1xd7~xc1DnnC^YT~i<Xim1B<yhwG)2J@UOs%vSs-!_sj-&=zg}+bo2s(w7w<v4
zzZ$OlB}!`|KPWTS<x2%#GJ8V{DHX-^p)QM0{IvpP96Jt_zGlO_!!E;ETZm+NtjnLZ
zhhPYGz{1Jm#8?4%NGDny)kHs*I^&Z}?LKX)0=yD(w*bDi>l_LbHY^-^f!7)F+iIDI
z(ns0(W&RY&$Z3CX1yLG0)-`Suji1g{n}<M0xlAvXJ@>#o0-uxpgI$f;{QcD{&EPX^
zhJuIXxGi1BH3aBsn-DpZW5bdm%*I`AlQa=)wjSPl>M?}fgnbBCSg1#a8cO3bSxzje
zejgnmelpr(WekE^EociU9yoI@hS#wNNWc8XQ?0eUIao!6@f*-~635DVrtnB16q!eg
zSBHcE4O`<#ZaCW#4GGNk$_tFU`S#F{2tgiGXslPU#$L$TYyIT@$mKB%9)Sxt`<S<f
zcS-U}uDHcLnGXzhYu!CfqapsnV1h$d*Hq~8IKtxA$ElG4%KibZs9WVc3${>}pMict
zk*$<v9JHRJl1QT}=Q=6U3+Rt_Mli)puS1XvGhx{9kEzGn*{`yAmb+%0^bJGPrZ)_L
zPc14Jq^3{6C|Jt9N%HA*B(@G?c$ynYCMXPE+TduUaRME*O)!3#AtgTt>d24%n&vGo
z+~Em&9h?$Tvb0J4+!TQ1#I3#kdy%{!prxsK54g-9Z{qsAUf>(r8zm3-t#1)REi>st
zX`*ZsOyE>{>o(U;*7vIfv>etKhB4pjv#-Y7Wls1u1m{F?=BWP>e>d=vi7M}XJhWuF
zF|@2g5w<34*fegb{Vmhp-Qa1!92=DH{#!oCkhC}4S=uOfDVVsrl_&Dh$|;R@VUSR{
zL32D+=DgxLCYI`ikR}K$iktCHw!cUT@J(wXGSJ0rEZYR1i2<4O6!4^@G;vRUQ;mEs
zN$rTNv*ka|A+BlUf%;o{Xm!VvvUsP^2PO(v5*Vg!kFBNgT*>3PX%*E#_gP8DhwpgZ
z;NZ$cc$x;mkV0j{0nO}!GaPS-R0rpEL@^HRibl6U<@@HeAiNi$d%GBik|E6>K>o!K
zTf;?&yoMxpkxs8Yj}Hs5zZuo5K~2IU4&92R^k61Bvp?<Yn(TXazBEvcY=Nc}0nmRx
z<53Mzn-pDpPY@NNPSW^X8qiEYLOs(80Ti6GB}NCc%Cp(RFFY=7-YH%PdPwg6YPT~+
zs6az6by!k!J;P-Ei{k&O@r_3QE@1rrWZuk=jiRe=0Ves@$KNkRQdV6g=5;#MNQr5!
zM_H+9aKeIJEfXRDYlW1j6v(XYBNE!+PBlV7X@2O*rb$<nWaThkQzEHFUWEIqmQ*m4
zVd+iy^KDPocGbt@u^ZNiPRO6k*KX>{HkrVj`Hj$|IP)dk>%uyH%%Rjsb_Pap3oq%|
zusC*Y1xA~<zh-Zc`PmNe8{aw(-s|!eFs6~pVyJR(0;g6SO^y8W8b9@*arQ{siXf#w
z0snB=x_WZEe>(&FLlpdTgn`E?j_d`+bAH6f!Io8#b#zQ=Gj?rYw;I=0Vw3`9L<dc@
zDNp+X)tsJ(ExZ-A*WFX5Sy%5P%Q>Z6iN$W7f5cnRGM=G|MdPZMPq{x2Vhg+s)Wr-w
zPdqnp@tQmbma<VFaGc#$Ni>pJA(m<ly1B1#2h2fP*=Pn9MKsfPf>a1t(EPSrlQ4{L
zRU$^N>7g~6Xjws6!vwu&#D=uO!*UG~cJsIWwTWcK6rRW5ZYfLL14d7(n*fzIbGjJz
zQN_z>!nB4yuI^40DA@)7(@)Rp0rkXLG@oWLF15DD?Jk!}GnSNClLoXH8W4?pa%y#+
zl6%M>sG<aedSjWP%&O5d2jjnllBc?zA_!@KV7UsWp~<z!K{ILBPL#fuH^%&3!S-bX
z6=A*=9L^nzIB6?H$g!aIBXTlx0TOkmIm{1GJq0jRbdiM~_z0f1KADMpzh21Or3>hO
zb834l(i-cNw?;F0+r+^A$@Lj}56ID{*bBMd4t^L2<r>>Cb)hQMpY#0vE*|Fxgw>v?
zt+gj`VU{c;iq0L)&=Qi2V3rZ=&J_dNTCN`be`yvsny*Z}h3{(u)v{~Yo854I=LzRW
z7Piv`eC}-P0`?s|r5Q)4>t*5_N3EJ25R*P1TYD0G#{4~~BOJ8Ds4DO*Mpwcx^~!dP
z(nr(e-2!ty#L8OE7fsRDq<Jg}YSB1t&e5zvR{*b)4}dAB6Wv@uqmhdV=>FXo#CHoq
zX*VJPIGETewk*MQw#Z`dSWHRM?CUsP=dFM+oh_>+cb8-5IS{7O!B5ywd2&;9!QDe#
zA|b0B3VQ*Jv3Lh`v(v5}UgtJwb@erU76nTGVgI+jGwY*D&NQ`xNyC9(D0jpcAYi~I
zoj*;hk<3kHeX%5c&#&!{<-St_;(Q&w;{{(-{kZU|cmF1jK)!8|dereY3qE!-&wOlF
zX<-HznBkh%octuI2xZe}ml2bjEXrF^wcE8}W0-<vKDtL^@@}wJB*&z2dXdRvrQ2ll
z<^+*&*jV?ZJejKESlOO%dyuUz%(pQlE`=3j`DrmpTc0Ow2knNvz6!+fja65H4VW0B
zr}u^ujB==Q#5ZibZ5%jaX=WTiuItHufFUD6`eI&6E8Sg^|DF>QEo6l@_9g1#y!{j(
zEuINM#F`>KyBe?*Ly@DLq}6<!AcH^Kmgq_}J<{Yw9nQN!&h8-aVTDlOO|z}nek!?j
zkB{!9EsB+5SS!u}pT++ZFWOeMD!QKOrbsBR!1>)K8f2<Z?tFhhMq=3?xY?8h=)aQw
zH1w-aF1$}Qmqst^U{}S5R#6gD!CJkP*YE<W7r&r9p2a;>-0_yn->z-wL?e&OKsoX6
zC`_w9N_XL7W0~rvS?DsSN38GdgaR^X+rgh)&01E4SPz;DQ#~tg)sS-K+Fy%ZuVx+0
z^6zRKGFqP6VAXp(RI}MU3)cwgx=_xpiHA6!ppbd-qYC#s=mj_(aGi0*wGzNu_1x?2
z3?|_kY-aHV4tatlbh;OdB5si|My>*2*vjnz6CoS~Nx(`pY6Rba*AFhK>u6Q}_SB??
z;QEbVAZPprxj$NDtBu9f$~bMZ4N((V0Wy=YI2Cwd*93WV2xB+i5s;`Q1-1i$-MS7J
zYTUvzK*BPPjI&7Skum2v-%Q8oT@-h4?KrY4=HNE9-17nSgcs&r--_(j{39f|oy@)J
zf-0L1xfYZI1=NTi(H+SX6Tg7p>1T(opb+oEI1DSzO)O7BTNz7eyPm%yay}!}#u?18
zJaKV$zou05sarJZ{9F=iz$)v9ETOMtGeL_kH}WiARDwB5Du&20DP_5*J$F?~glb=i
z>0aAl$#1H-8M3^3>AdN05MUu+s=PA46cD!hJr<nxm<7)jm<~Up>E7BR4mqL<$;|ct
z>!my{l)E<pGDi|<Uv9b_n}kf=B1e7R>ow2nYl@jL^|ifZa5n+Ljp9{s04l%yV9FNQ
z+YCJf!2(7qxpu}GEn!@Q{-=_wtoBV^M+s<-7CA*V9(RNsy><vi$Si2e{edll{OIsC
z+DfN|b!z%N)nR=DBq&P(-OFWFFuUu*r^k&DL2#5t@|j`j$@McPKcs}aI|6Vtu*`zw
zkeo|q0-+Ll*8tt2!kC(uE`=#9yL!^bWrkgqdlv@}dO3STrgbF6ZOn^PuFjm97uyGh
zXlOKX2cM0?8wO*5;wWT!e;>VX*<HpK*%|!}iBnB6;`-uH)fv{!J}s?&E^gIfEjJry
z!vD&U1k@T5^?~4|FHW?NU^j-g?6Tep5XV1OYN(M?HN6gVoq<R7j4J{#{*kE9x@;mK
zlQOV8(Y6a0>K|VrDK)vZ)Je4at-C}mC>B<o!L~QrRdG7ONku4x_)%c{)g_ZBhWSMu
zKR8lAmGbV}hFIZXt>%DxP@(+#QGYC+=buSD^Nc_`uv4mQB8_TZY#XbUqcu+u&U3mL
zOxl7G^_<WO;ZCOqw8A&a9i?bhP*cCQ?G@+g;jR9d#TOM~8>@i+`_G=q-ldSF(cJFX
zQtTz$9YnAhU23o<4DJ!o)<~FNXG8S)8{!(j(D2h0rFY7GO`$m_T{#6XGywi$?~#2}
zuX?RBBU}BHiWvfw$Xx`WoJvp7G`@wekM*#Iaw29dYPW4kydvY4@eT-FRV=SSXv1og
zWfRDjDZPQ#soEqh;#lka5yFByv%yefD*jnh*iL1UIBLP+A02?V*lj@emz!?U8e(Oo
zRNkaiCeH`v#h9>Cu|X4Cu)NaM`L*YT13~}7bPN6{S^->RPqQLGP?&ZhuR@I1GyYa9
za7Jc;MsagvKNO3RC;yyTYx7RdWt`k}*UZNCNCHIL1Q<wTjM*>`QMEa86CMf3T7)Ip
zm%zDFu!w=_Q7g+Mh7IJMMq<UBL0ZrQI<6R>JMYp`50QrW-x}tU&sEm8@QOSd^msXw
z9v!$*Dt0wkWic*nKEc1rM9Yi9wARUW$QID=SaB#-c#6&T;exymVe6u}lUlPo&KNxC
zHd!=+LH_U}o}*I#$cI4bBc*k!#(qAL=Pd0EL`(!M-?yKp{V9%j367?>O@DG&H$cbJ
zn`uj7HE)&%9;2Th>x`+FM_gu#t1?k=cBAE_a?qY2**q0CdvX^4d)#g*pQ+ayIy5p$
zA(C&<YJ!YA%$8E|{cmtYG>Mq#v&ZES>G1+SOmqBNcG?hXomfo^P5k{9bDObF<oFhw
z>fXjzfaiHy;H}OO?|ucNP?^F(kUiJbkdCHdq7)w{W7JojAtk;{m$lcNJ(x!LeC~Fw
zftKk!j5a%n9#}j<L;-^+z0Bp?f+R|M)jTJ^B)(klub4FNr|%C=l}p&XWBRAPR%%3N
z7l=|X)l4=)P0-ol?2aIg9R}Yk6oNDzF&H9a%LKFt8EVB0NF5@Txfdbch#K-Vo0R7u
zlR@<reDRze;*hnqL9jo;<5X-jOmra00j2+uN6JC#9~M|tn_2ITf8brthhC4;^IJno
zo-jOg1EE%5*A$ToZQcC+ll#f;<;chBW%?{Ct7}w&8Zno;+}7&c;b^-uZ3&}|i4$A8
z@cf(FnsGI_;C)zo&T#gvKBYdD23S#G;La0B&E8W3iA?K-gdSUp^LC&PGkq-VBVL?B
zNAGLG^zd7vfX9ZWE4lS*%WdvZ$@zm_Fc>|cf%YJcs3dl18Y<NE`V|1ModCm=uW{Q@
zAacO3Tw+EdX<A^7!w5xmtXu_8q0h{d@B)SuUHM&#oAqH+vl@PJg=t?VV2-LA89BES
zwOM77<T%0gOl#JhQ6&+VH^4!HK;ZLY2~keXm9Nv?abz1LrjxSJbeGR7DZlZXu?VWC
zl7ze-yZ#{K%&`cgbGoUrwMu1t8)z4(nQlt0b;3((iYpRsfxxw#DmgfZ3T1@|>UK&q
zT}JbW!eV31zrjd2gJi1}si>q@e@5AlVM(a}%T!hrPIr&Z>A-Tog+C=~2%*~ff14@r
zc^rVq0?ENDbKK#ez@221(?TF)?TzFTRj1g^M{;XLSfP5$t!(5C-xacn%^ro!pRiU;
zM@kd^=(U(Z)%bA&pdC>$cD>kHk?f{n-I<5AI*?vC{C>#WhS*+h)!HY%GcM2#v7m7(
zIa8EDSfSRX3c@)<C#cF!_XGPjI`5|kF!A(;x^&agmy2A1mHi68d+rLlt+;lBUCSY}
ziv=TZZQ#x2)Eo256@sDXIcW&u(I)i+FFB3kL3K>Uie0Z)YKt<`UrO^3KjPxc8oIa^
z9bv;G!{4J=w4)`Cnoj>et|TZ0mJzn94Tt%uUYgJGb1l@bHHktf7HaYVH`2}!Lm4gc
zk&3>7{)9fJzXg`b=MKu$TZAlBigzB#%t7b=y$r!g&WOpV>Qe`_`ggZ-*QSyAT`tpi
zqd-Y`yKh4dUi>XY9(@D^{w{gFWSc#Vf!IAdWzM~{a=S@GkyX=fwmJ{~U*OwOO*j9S
zVxE5eIOzH20bFS+;jo}vBr(#*<L9(@S0h`2lghxtRbyzUev2N35w~m4)*9opNB=F(
z%7oZEjwF3;^wF}TB*ix&?RkOh_g<{`k6`!z49Ora0=8G=0!B`|F_bbW^>Wr>1XTUU
z61qrRy(e1i^VMeYUi@lgTh5K=XVX*Ij5;;QvS*bMpY}@4;YTPK|3{!BgG{gr`1^$W
zgY^bWK(0c;>+Ylc>Q$|Bos<Ku=kEO}ZVulbP*5VxbT`HglDs6?Ord}*BeWxUS_<`}
zZB=@>#30h?n(v7=8{jacJJ3t8-m^iEJEe0&@B%QtgiE@VIsSMaLW9=-pgqDK+_;T~
z_Iv<S-0v4a%nt4B%Se(Y(Ki%FX#NC70$HL;rpeSZI-I!5rLRmMR2UV5J2|evu~#G%
z$bR`?y)@);F<^4IdAMZ`{;#+>osKwNOqwf9Puxq*lI#bv(0c>ZvwAKCM)0H2sv9mY
zfV{<p(5+Gap<K>e%nZ_qeV`U4zcdV|#fO3WOm^Q6sxtaZF$FC)CM%--BRu8&!7ovl
z!s7wo4!-2Yt<#|ku0GdH{bN}kG*=CNh0xE{tQ;z<<hpBW4>ioa=0Dtt9>A*CXOwbt
zIN&JEau1i~I5R?%yM<-~gF@>mWZE!~Q_Yg4xBiQkbaIZ=c^+6^pY~{H<54vn1~rp`
z`XItb`2w=Aj9OGsWNxe%lX@RC)cCID<jIm?CxFSXxR&t1S;tB2#_n}swGN+5_DM|A
z{NY>6nc_qD*J@~i>}1&p2{iLtB!NF|1JXiT7Z!gY#TQlIZ(A)f*9tud`&ybVa@P>B
z(D~oTqVvQ?c)NxBE2YU~4TXQ7G4viv@BRg6U9J>CtDX&n_L!=WgN;thKFP`(6WG2N
zl`*zQ57qS>jQWxcK>~bU0wmj7A(xuA7gwm`x$OQyEX@B=Shx%lOr;0M+=3rVtAJSQ
zX$QKVWI=zUWI=I+0g(|B+I?Vkr4spKuV!60`+@*r*x(*Z(EvZG?Tbp>Pl%|=h)_&M
za}o`!Wif#&<6r-011xELvESX+E>EbpYj0=5!syY<6A>9p)l8o``Q;n+k=?iggZPAc
zc}8_saUC|$tl7@u9MH?$wL?*XTQ3y91QiV{gCBZf4BZ!K{4DoMED^?7JZ9cH57;6p
ztMXYuO+;<-5cC%ZhH1REOX_d{_{Ly6h;@*8$pRF8%K25Ymi--62AdNw0^Nm-ZB=Um
zsuZlJegs`+^X&@L^n1Wsn3=TI7?K&~n(D5_1Qj*g+2*+T!sKz+>YHHln&bz06n?HV
z-Rc`6hM93(ezdY4^<L>mIZ&6?V=5Pl0vfhHFSz7%mT5cAyxOGoo>`SsH4rOI+)`l+
zQd_#xOANrA5d^?MOYtHKcp;KnBry5)GW7br`)s=65t?mCVKO@z^&0YCVcYn2fs9;>
zxDJ(ROwjOpL0AhlX_cgLNo~B(_ye2h$ROPeejcJ6`0uQ^2P+gV`pFL8OC`|q;`F3-
z!c~#Ta=7s}#w@!6S5gN;8yq585i2SqK_H6#PUV*oTOn1-??Zw!zPDw6(9~=1V{22m
zy9tOfv!LjdIuexcNzWPPz~u-ZN*BWnSCFb&Q%9nDR-pyFB)tnDys8?g3@>NAF%)bT
zT+TKH7h5H1_#pEzgHNijc*ho8KcL`SRdlRq;%L`RlU{2RzN=Y3?7?|8Fgl05yj)G&
zd&=T|-IGIQ^+@F-bh)@P=ehHshE6OFag<PBXL6yCg7*IenM1%4M<2Am;W8T8v*bH~
zo1>*=fLrbF5dy?i-F<;2V^m<C{QMGE`P^1U-fj23pRpwpY+@wjY}%3*Kal#c;4_le
z+#pA95O=g!FD!O+%aCS=iz(g*x6;#|-54w(LjErkHoAq;%LccfA_>NXO_=(QKGG4Z
zpy$V>4k5aVKmRVJu8sHDhJpL1fdaySXrnAkDXgxo0gsenX|>~6r?j0i6rTJ9Uy#>!
zk55U;ea--WIXclJxCEGsy!7y{`}bw`zl%oNSG$jsK*Zhwye5APG;WMnZiFYFq(2em
zagAzfY12&agFdK9SdeSC|H<6WsVP&XNo9r|pdcB;YULq7ar<C*>O`m&lQTS6b*K#w
zuZg&7t3{N|p|Z_dVSm#tixvx-!WvVJwSY)~?CdZ3$JI9hLGwBR=N=#R5~r$If{PC#
zOYegjk~DJ{9?49Q|NVfpapef7qE|aF{1j8|X3p${PvuN{TwhR?F|Yq#rrRA4M-T#6
zUX8AWdQ!-~x4N*u483|ZL09p~Fo!8`lhZn=BpnE=Fhv8gK*rk2H1e6?R!4VdM{?~~
z+cK8v>W>4>h3RctG^DYbx^x=fRlGJyT-bDfSnLT<hiE!gUOVbP!7P*+GiZx`0bps3
z2BDM+p_$eZakbCLk_O6EljuR}1pH0$VM&40AEwSTT%SyyqX*iv>TXI{JO(}@`|O2l
zlDPeAyQS0Y<N~6O14^NP5Owz<!|-U7J<d(22S+%X+k|Q!hN|7e=}Fxzt>p|Lq>qc$
z<b@35)JFs4eTi&vF#@{wY&m=o-WeWRzv!BITZ`~T6aVS&%$T(xxPkgjYpqGtj(E=Q
zERfK7gImBu!P-oomwyvYG}hlRh_koPFbVIQ3Snqf$!RX2uf*ylM1Jt9pTLAzh3jjc
zI4V4uR-#CcSgZ(60Kefye&mZ|!~J%rGbh~mcY&PhZqi3FH)}7K9a8B329r$4dv$Vv
zsmc#wdTe#;T18$G-b4v`b37#RZjq|T(QlB*=sOjK;B#Z;@jlzi=hr@RJu?>dQd&cU
zvdyANnx|3!VBFw@nq^-0)JoHt)DJF@Mf)E%b}~-cwx3j%(^9~H)I@V}$&nqn*06Ge
zG0o49vS*u9_<5Ctd{A`IQW3|1KB3|!n=>7bPv50aj#>1j68hvb%!3C)0Okb=ji~ll
z^?fR7`@{oeW7+l>e;o(r2BFAiMI$N3IGZG)h%;H~-`s-}d$9P!qfa#VR^PAQpkTq3
zo9_aJ(G|+sVi4i4rv!TsIy9c21jOc5>sPQbwnSX&_|0G`+>i!4<&^&7l>Ip<`=-rv
z8^;=G@n1x&FwRpkUFtw=dxnT&4tcYYI!Ac#wf>QWDs|Z--EU^(jLBI70NH{~m-DWf
zAwOU)3V`l@fh0fPm<rh+{;7Kxw>-X<*llIk@<~&vZU$e717u?_To-CSQM#<S98&>Y
zA;Z;laW(SH?f?Ii0O4H?8g>(NN{9o23c{}l(oWu${ojf00F*Zk)quDkCUX24CBOSf
z9v1p9Y;kZv4A269??07C6wwqRZIbJTCjywR(>6cRV?fKrl?F7lFkf0d4Vx4Eu-0Xa
z%e*n)SV3Tg8-$YmCrLwU!AkqH4*$U#j{;i#G|he%NK6p12nplLk8z@_W=kEN@0-w=
zT~u{A6`2v9(5&SRT%YKCA70IXRC(s>*(zf*&OLf;l9oc*u17{1BH1DEnFBo&bxVq^
zwa84~tD6EdFI<C8VOGD;SP|;yN5m=%OPIOla0X)yhrYuz@**{OP)=>Ll)9Rc=HA5$
zqK}4^3LGcKd*`GgB7-V%f+S*0+=L7@K7?P>i8XWjCm(BSK9_BXM$wK{HN!VVLPKgd
zKFyOMurgt}fb{SPX&6PXvP&KIC-6L{m0>a{-6lM!c^_((tT6Am5sV0`sd_8V+Qxt9
zfkE83xRbV8T(!1d=R4c?XyfA&2LZY8J`5`*K_}Q39Of+OA=sf&1X=X>R*fU4ha2cB
z1OtZ0S~7=qNVdfhnnArg{0w^FAcL=PTArR%E~J;(k#mX^L-S>%(XKYYjn#_tNSVl_
zGNN5Ay8Y}v>D02;_mt!i(5k%%8eFQMG-SFdMM!bnO<B?6{4?rZu;H!=Yx?n6@Uau<
zT1WoM3l-_D^+OxzupNs`zBQ%l?h{F)Mi`=+MJ-@<wj>Q$fM{M^GPJfFtN!%z$MjgH
z^}a*6AvzER=8`sKcrIZodqsB3Kg<6X%VQ?uwL+4fr}HD(HLCjS$4^tXaUsb{nCn-V
z7~+gS&PTSmHD}UYz}y5$d?Q)vZ$sYMjPiYz!cyc~A5fZ0D!R=vC_KNT%ZA^tB5IF2
zB(hdEAVx;@mSMvj2YLFB6R+Z0Mz2S1mZ|cgp?)|@A7>2s9R(_bRYeW}c(<pJUTS%@
z!HMaWN&Xiym$)6ZqO0R-`n9=tad*=E(U|7oRNv#16EA5@xzSB+T}npg=VApzK3zYR
z0@j(v&>>0>zG{)Lb;@1QqpYxA$&9baI<}_eeIN@eL;GV8O$u-0ihpT%&rb5PW%Oa?
zC2yWQBt=;ZXN1=8oYr$6W7E_23=>o^%(X*@lBbl~x0X;ylu#+Q6u~zWer}9cF9R0@
zDOrx!54g{?{@TrTN|7PC^|(8URSN9g9{j$3({{0jtaup|nquB>R&A*ZJ$dB?X8(mN
z=698jD^`mLR2H>2wx1=wRp=f>5nrr*skUv3=L}0c<T@$R{#T)VsP2L1`kOZ{f4j@^
zeeI0!=)Tm?Z5LUwyDfmbvB8&zQeKifX-tqTOz=jAc&Logp`HgQT#+PXH`VyJ8=8*0
z9<XoJyHlq-RU8i;zBx^rFqZ*s$*Z>q#6X9YV{RG;9p|3A(QkHArz*9b<tX%una;(Q
z>Rfo~o2z(c{ziBKguX=K!oy=GAmoq%y@$Bl?eN~Ih+M$e+;`5NY5*!;DHPC#QKi(%
z0ZH#iBDl5FOF*`V{3=UiY-US~IFGO^xblPeeRM;wQ}S`<nza{WbYV{0pC5W2Qo1#u
z$G7AG>$JU(=FG)lDSGsrI;?S4g4!_Tb*=h=iJ&<kANhmGL486A*i*bSXzo9&nKWtv
zoS`Iil<VnYf!{w#<zZct#odu$==w)|TdT72{|Ck*j=uXlRN0p}P$2RYlZ_bzN(Emj
zq~-LFEJr^*OC%FN@|h}5=q{9a<YRb%U{dzi&B!yWokkc2%XlT(wdQ(1%3=wGOaz^)
zf9TqhcTbs*vXWGsQ%H~@)N-QiX&?W)1FSF*t?IdfFObU}XbEN}Z?pJxHIEzUcHBmF
z_JzTaxgzZ+P77B?^U$Z3TcX?MFe;D(#x*9boxXaR24VC5agQJB$D33-@}uqv7|E)Q
zF~v5{u-7$=)~1~J{E!ky0(~BT;7nw)=5&xZ9Oum4iqpnZz{l9Wk4$~}gt({A>;b$8
z4aNuR@CO7^JeAf=o4h{nVvk4z!n}?TkCO|<VAgOdqaCXyF`${YNgS}?Gqj3-mAl%X
zFCerhN7IpQcA<t?DV|2McU#?4<?gIzq-nLhQ<lMl(A*FY3Oilz!qYW2#|qti*XG*h
z)nk49?iWqbswPIb=QQfOmVrF8wL&#EH_;3vb?PTsjVzT%s%VBg-Lmu9;qI+i9%;YO
zBz8Jv(%Pk11$T$ev~|Q{MJpxRTSV_vdLsJ)XC3v>v&>6$&O+iX_sJA?-=qbK(RZi)
z-1?pKvC0<8;clS`2)!26=Y=-1FB@9fmYLY+s$wdevu2!Y?#{%R0{QTd4vPTj*PHZJ
z8>k$@T4Lyv5%L3-pd}n(A>+u?#vIf_3a@St2eUPD^K;t$9^!B})c*vqoPs#$>b&ld
z2#dAprmJ&H6oj-no}xNAwI%P|Ryb6_wg^4gEzEFU#kY(!UCGWCAa$))J-7jSSP7C+
z|9wwxYWIVbaeGyOo2_S6>10~MueMg}e~tjqghF0t{v`XEd4y^eyvqhj=q14<aBr@J
zDi`*s&M|LpX`R%DVRTEwdqmo>NN=@5Y*M7-%+MRomjpNS=^OVl#)@y9Hb5MjK?X(s
zj68=JC0l+2MX<<Qk5q4iWMl+XSgYt^Q;SsrSJ)S%Y61aHR*>ov?ow^l8eyG*SCYM3
zD!MO|T-%r;Tnxp}E*;r$A~~EBh#n1TrD2Pk!C78^qEJJ=AetsaUc3^+!;+N^0t0oa
zZi$z`Zo_{)H_ePhRDF-7ym`gv6D{NJi7;24S(=UJP#}WRI5VfjQ4n(AfS8sY_numC
z!37_y8)|x_(}!-&f^;j;2YeiLw(QiX3NzZ9R_t*|O`u8gf$aq(Wv8)v&AG~5^MX?g
zU$*uj6AJ4IWIBkSgmak-mx`nWWl@Y-z~6=x{pamryxhi!uCmH}&+uUQHijIALvMsj
zG*TSim8SI{h1t&7>FrrL0v7AfGfX)_TF;3PBlH<x%}{umDMyM;<s{<97h$#0BXNUt
zwx-MM!>xLC>F+J}e0ylQH`A<Qc?1zL6np{X&%7EYfF2ZbItmFpRjB$G$v1s-XW0r>
z%0)Fg%;nj}2nFC3_{CNqrRex)PEgwxIW_@5hOR?aEL0*AdtrU!H@~Efd!^*l5j-j~
z$Ll*~O^4}??h`UA_j5pFwou<}__TP?k5IKo04r}Za4e>4D>Y-0_`x&CTy=}&WAQ+C
zEQihiR&~b?wYCIH#7EB#1lPM=8b(L6k7w==KZ&)@<<e0>hFF79*(mK8^c90eD$pr_
zVxWd?(l)!T_@=4sF$ZgBGk*fc#pBy)(nz(Ma9{GtFv?`36IagFg1txSu>D_J+nRzt
zsuk#Q72Gk&Zfj5S)Om+GcU7)l0T}nk#)pv8RxM>eN`^YVSk$^G`xpZk(ITler2+vm
z5@Ef{EHNQ_LpL^uy3iD>!_tDUYW1g<c-e1G*zpmP;9s5BiXzP^)e3^2x1k>C{oL`c
zLSqE^8{X@!xyiELwm}_1D?~bdV;2bvq3erW#Z==R<a?6ayKDKLl(xgF3?fj!5S|5c
zNBWbQDvlo?{vue>AT?_y=xJBm8;wa3|A<95jCejd@5Ma>x9LkIO~y&Rv{fFV{m}|U
zJ>d^U6PwiAw=CU6!-#5WC2zes!7;c#{M6lxU2UG{QBjZE8M?KUR|fh)y1rU$?VaJV
zzn%1B2I=eQFkHX-iE91qg5Ki5guXBBU5ZeOE@S@sna&~92|>6L9giAkrzxG%*XCK_
z(Sn|lumX^RCUbc$Kgbje#m0`;q7?$AyYquM$#|q=Y*^1)i5Oe9_e`Ygia#E6tOrw4
zl<vD~FmciKoPnTMJ-bMEk30ri$#1HZ+eT-hg|N_Gygmbx;;N$wAuj%PO>HB-Bq5Yw
zEU!W^bx&@8@A}&zt?T;cBtt<@nm`Kfq6Afu5Mgf@(O)Lpik!qSxUgE-bT>7?x%Vkn
z%|bQQI+*ErQrDwbkLe3mTve-3nkA;ImCE(}m}eBMVE;>FbawUM1aYpffO%P^-NnU)
z*jItEaUbRtc=@g0G!Egky6Hqi$Hga&4ZJ+J6n`vPcHPa1rkBrJfN)%f9f{JlcGG3d
zc0^r=)Nh`KI9OX#-WJDE7KGZdVxhN&hZq%bAm_b@KL+F0M)3xpP_a~S241IH6&IkW
zTH-dMfASHZX~8A>I+^EXH$K(1=lID7VK96<o$YGX*(K38krNyo0ksc7aN2a<xJ2JA
zTAalZ>?Ox{SPHb2z$tkBKo|1y4B@jhLI=^$Q;RQ;DKgScAfkr}VM;be`5f_P)OS>k
z$f>>y$9cX1jdX7bUiW^)d%Hfu5Fl}hDiirS22;YZKmtM*(eC24UDP0=3&K01Qg}0Z
zRd_He9oT!ltw{1HS`_DagXE#lCJ;~X@WBzz$4UY)hyRSXy+(5B^B-)xRl)JK@^v|V
z5q7zF`8vxzn$-|OJKYAY8HA`321m)yDvU7^XzG)5GfDvlBe2v5F=82Vou8_$#V7k!
zj9mgx{+-=S>C8agbY5PqI|K!RkpMd!%$J|BG>;FS5n&3;6O8wmMb$lNhU(#fVoso{
zb%g1E=YvWi!RED~$R7qok$F$ZmEdlVD3`u!J{-ZXh3s$`G@>1MCQ`yk$sUJB$OaoE
zpsd4XTVF!vw4*uqtXypsA>1TQB|=k95CZ|2{Tw{i=8%oU^?>NQSxfH&u4u}jYD+-5
z;zpIj)A<6vI89<_A4UG+o%8zGTD<Fgd>OJR^vmq5<&}v)&7oZE6j02iZ5+41(Jc&Q
zdSyXG3!YqM#A}G}jv)tv%X@Ri(S1m{7}*DX)*Q_%GhX*zTmNgT_DMwa1`zn(6veSn
ziL%-fdNW|e*w+oY$Fg-{4*88~>+gKrxcAZ)nZTe~r-wkSt^E^rbmC}LtcbM@4eKJ_
zq(>pA-O88>N`-O)!^81QOi2Q&s0=*E?!xo2XUdhFRX|0t&{tmkf|lVxf^xwxcX7Uf
ziC!|vFoub9&~fYDGX>4xo79K$QSVn!H|!0XXG%`HezO<JR`7(X!XS+V*`{RP2Zo+i
zaxR?fPtwn)7tB8czNRE;%#eK(!@?rb{1YJpcnyj=Xtyz2dX>po916SBzsk=|c9;*|
z>-lH}udIk3i9A0Q`B;vH1A$yv8msN~oL|0#WWpKUNmcU{8?gFEAwB$dO}a4_vQu;o
znI==wfWzLDF5Po6;qtz-Ayl022dkdSv@>LG0|DU=xC_y95mu*#39ghB6&cDz4d522
zDy#_Mz&H4Iob4z5|JI{-?!PLd2~uXqVs<X6>_5?UPTuGuqA{a`6T;DUA}J+nH#(i)
z3NzL>8pV7qKw3G$UOu6Z!3Q}seWY!)T3$d-(bK6G=Kdh{L-VKo+_;&}wGb-#H_><^
z>{sx?>(N<nAMG?CKrP^vMl!pFg+j$}tV@ykF*nkTvOzlgKbhd9kcLdWe;_{QryJm2
z9WCIn5bWz<cj5)~x_XfzO%fDOJI5H8a8w-{fLnSz(jyHwHzf!iOgm&}*XymO#()7L
zHy{z4!$rqL)9+FtJCt|<hQMWIopGzRBJ;KiGu6RU{1udttJ#hYyIJrYt!zW|x|nm=
zb7VNTyevK$@&{{ekjkI7H>tL1nKTr5=V>mAd5GU+zSSW{!pkO}*VcvG-A6RtLBLgG
z*``dISvZP0AXrJ9DQmx;2L%p=%Qn~jv3NlXAlN3Av^FGMk47l~S|7aBrtXP=w)LRa
zgAV{iHTn3s45|o?Ju2ThtBt}zN@B)w`h9BWrx1XZQMlD8cl`ebhxT5S+qU8n28in{
z)Up86UBK&Ijq;U(V^inxtIIy);vhmte30HhlEld#9S}T7rSF|<Q<;iYR*s}Sre*j1
zKqqEA*8C4>SXeZftbgAO%PceIF8Gkl=AajD%U2e8B<ce?Z%2+I-Re0Q41|}rO&J!1
zLu{ckw~ObCw^Tl$--vuNFj6v)E<j1;A4d|*Z5pUL6|Igg%NL_u$!miejQJNZkQ@^+
z=?{o6{eCg+h?PP8LfQ{3%#EB!pZ28$e0b1^wJ94W^Jx_%@`vfEP;?5=a1m#>1W8_9
zuuCIj4<e;~X>s^cGcTXcIvKE$TRpKkzw*D)kuQN^#qY2#GD|_=GWR{nrtMsd@`=H^
zl#^CPbsud#s7%;QN!UHd{6JB39dtb~X?Czp3y|B9n!yNNWZ;gy5(uW>hw2fpbiF}$
zdK}>eXuW<sWJR6|?+#kgdcftLUy{W?jMV_o^R;qkp%6a+1D;zcEhfF0vkX`>>nc*R
zO-yy*ci;T|m^(H-Mun*=SU<L5Ta96#0Bqz{Dtow58hmpf(ASUqERAf;hMPCBlQG35
zcw##+kX5wfm89c1icG5;f=*iYD&4J%b=3aFSx9+5bYC~N`G=D`5)d(*r@sYUs3Lh5
zeuZ}n9h1bkK2~lKFP$6|hh3;9_<kr<ErPs7Ke=Wo@JzJB!KrAt{*ct6E0y5@z21o2
za=fto9zmpOw`9L<7d$`5DP^`@F$d;vW&m%6T{iZZ9FdghXr-i3y6sVcn{MI54#dbz
zjTt7jQGxS#r3k?WMPCE*1nv8OWe6|4Zhbvg$5rtmRMy56F>@)W7w0h5<$I_Doc_^h
z9iOD55E^qy{NpFSz2bOXRm8bK#CMZ2SRJs-bT)3x%a^n~(4wAkSQ8RJv1GBKOzak9
zkQ%z$&xJx^&B|g7Kf5^7Csrm^IMuJ6=S=cBBXh$HGi=ea7kzZHJ8)`U(~K7*c9EY+
z@rH=!N9D+?IW=aS09gz@OIc+_j+LkK9WW2#tE_4}vuaG&V8`XY+3XMYTML}?+&58W
z`~4G>knRUr_ug^qokJj6)&;iL?5!@U`!VqVFsQ}Q^W~=^KQAlt+F1;@jHkP&v3o>Y
zY&vEr7}SB(S8Lvgmi#tuIjR{#<I|+m??#Z5CKDJY9J9y_y%7Eu=T7=z(?z;FZCEQ>
z7IY|g{u{Ev)%E{@5FE`<!U{8;k)JqfsW^8|wjtR9q~`Un#hNdo$T)B4BcD4IaNk)+
z^ERyrw60cG%U>FC$)Ph2gIZ`F3CcEhSyU@>3|kr!u_knGmR6eX0M%G4^nOvkES6Q)
z7hf5KBKLG#fvoEkA?KI9fF#>#*u{vRnYuIA+dlG4|6|S>gg8{R^1PIWBcF;AycxSf
zBd#evBnW)~jZVGmXoJ<0vS~=e2(7@HKLGu=yl>V;SufII6pSq<Es0V3At?)-uXbJ-
zX*g~Bw_hGE=IyRIXbsw>k{cf#!<<}V4a(ty%lsAV|7E4C*X2j4ZOC3yBSYoEpP+{@
z<Z~d+TW_PabNk8*-N5eRn(%MQlIIh)1wuw7?dreKL}C%>Ild?Pu5KF;)L6E&kI{vc
zcIld&=C=#JF_$hrka{k)W;c(M3xY{0cxQqS?G5-}7IR7oD|RKlup(e}Q2$~-&$I{f
zvj4j<R38~DXhX+<#}lUV$%NO7$uQwBd(zq4+w~HIJY>Sb<!7cAD>2ip7KZ-?1_~<T
zF34pYEjKSwlP!TWH##&=c~u!HUE2jW+8a%u0up+nNQol0G?96t@&DAd0&r0}f4Wdi
z>)fn*4e6YcLj#BoV^8PVC^OfW4W~~Wk>^?P1r%L#p-zGt<lA;lNsw1_K9wkpASHo!
zHgtzbjUG(u3|yva>2}l?Qbbukv=KJ@+VCLM77UFZKTHiWWju(afMgrxfMd5Vz5cw4
z_J+1f6RTQ<GmV{-0T&$jHMGAjuamT$Ulz~x2IO}#4RJ`j71nP#iDF9C7{I3zf)o;e
z4!Pv-IC35C(F?bKVol9*4XVj-t!)w*4<C$19JS*2P#`|IQ0OSPd<63*(q5>=a@5%$
zp%uz7Oz4_DfW_<b_is4xP(f1(MiNGON_eGQrN38#Q&5QP&_r>$s>eveIxNSPxHv-|
zuoNHHq`ZuNI2=OBQwn#xLW$@})5W-nRbRju#+s^o%Xrd(a<WqD5&2WKdg%p1;frFD
zMm3JjBja$$iDMVox^?jW*R~<n(nvxgVohaKhb;uc<}B;diGT2Sq2Wl1&ZMw&ccYLW
zJ{-UeYR~m^h_-J1!^Ah#ZWK2YxbnVjA@bqbhv^GA=?N|+Ckzy?Htdoh&W-kE<9h;H
z0p>*ZOhLN^%uQ^k5O$G_p%cTgoX}Vz*3V_#5~L*#GDxT+1!a)@plMDz2q+Yz3KsV%
zT6o7j^SqB(sMIbiCAT<LRhO5kyxiUp8Cy8ZEmhrl(zwh>#!YRSkx78*e%R!aXXgmd
z^-b6!mZiT|r2C{5freL*PvomT&5G>xM{|V;Q!z@;#5GL&^w_3C{$Dz7U;9|@i7(B9
zjX2k>MeO>*VceC-r(H>QWu72)=sQ<A?oT6u=7Um^noTVFEhaQ}HhD2r5Me?88R}vB
z8p94XPbi<mCqr=t<H=8&QS=bf4QfO(W8A~U++8PK_0eL$>05~WBc%_t8<5)}Q$qP`
z_+fGCuik5^KHTnpTd=qchJDTzYnwZ47poA!yPTRv1e+|)^<olohRsjmSC;oJZ4G&k
zNFlqoPbG1N0fhhdBxI5Eb>G_l2_k97H89i2x<dapIpSMn$tn!wb$Q~ZG`IN3l%vBh
z9^Q96!k`35WDBFew`4J$t*ZE`i%_G_=}KOzF~y)NaQeySDPU0Edqi?2tiIS>2%M;J
zya6#OG-48PPLWPmdD)66M&hiPdOHcNO$p>T@@?_tL6@`P#~lA?z3+syoTQIOGXZoB
zJDY~Hi(zU?m4)qoVIt8*OZiEBB)&=a6Qs6D=}VUep7gdwwfy~R9mjw`2>xA&myL#s
zs7jK1dQJ{E!bfA=W4e)klj%6D`ejX=khc#!R1b^cW~qB)C92w?_|2W<<~_OO1HP}t
zsPAl&f(1MxJ($?p0`(88?giNwm#kY5P`HD&u|A7-g+LoK?VR<m0jzX!9oOcdhC4zu
z6xDrj-yp4DOeMw%&$S`vvo55-mP!xfuvixDMdDyl#X<p4J9((BC_!L>zvr9?H#6p+
z%<#XWu8Z!B$uuz_QyK)a3@tob5)~nzm@F7ZYft`GwpS4fI?iqDbnmw2BJ?W-8b&=A
z?yvFHvKp+LTC<4qwk&~BBNR_yJxi|jhD$I<Gd`u%3d?nDCer?>6oudd@=JDbT)Q6J
zbqfg58mLcQtm6&le{I8g03YIwraD<iMy8pSKnLY@z9hWMq0aTE6Ko>&RRe0BO>0fO
zJUu*~rkIYOTeEKh*<NuDEfp*3ERwOm1`a)Q9xP@rIPVVzB@nkQevA$ZpFf#-ZU^1$
zo<ZAlYtz6Rx=Kud;1TMqr&(M0sIolONm(<PV|uhTmWi}ost#YzSdVQK0mKo5u-Y`d
zYMXn(s89^ot9CJpl5BOIPj-3gTNsv~?X;&aX}Nex+5sr2#c0Q--AWqkQUo@-Z;wUh
zu2`%QGbeAga5}~EBHU#o=Kpe*Y^v_p09<;fIgT+)PrQ*PURb6Z-LMy%jv_c(*6W#S
zAn;qd2-4cO5k;A-C1~h|qJSxMbmc|}BM#Ozc1)W=S)=@<HwDuDv@G%lRhX=M*4agR
zQo!<sbzk1+x12$H!tBitlC&z4;1TI|*gCTl9&$-9gw@|uLPUoFA)#XA4AudDc6!aO
zc8P_=@gxRMIR}34lU_eR%0<B*swq=OKZn55^ed`g?BgwW2&&-5YWRFK5`pT5Pr>Rh
zkf~L$lZ&UZ=Iotl*FiUgrdV9@Fc#016VR@1w^pJ7!&R&yc-YG!&)oSL;yK?W5Ko$D
ziJ^^pN49sidLn%{1i4Tnv4M^iC?m^xosGHn@Q&%gYOd5!-TYb?{(fGNQ7DPfsM{_l
z6OvKa!!6h0Hc;Q~{;a#YS1UHd^oh$z0y@smS^jl*MIopGjU{s0hYKJ}LOS4@^0et%
zLz}tBEgpX57wecKEC^}!!`-_aLYWowLs%&$bAToj=>)PGp+Dx>2cAzlBF#t%R0ts0
zD|zqq@+}qm5zoyRt^%jO(_ON?EBs;Br!R)qoiI;p!o(AqDl%A87>5c@4gYpo5bJZs
z)D-6NSABNZID|LKY5mPteq#|&`Xj$v8P{KUnc)qL_0PSk`7K~=#LJJ`;mO%uU9Xfi
zaIg$9kiTyd1d|H68DJhnR1J>54zVLD1%O~Us7+{M7)TMJRFt0jUdI5(o{iFUmYf8a
z7X6~+sHb^J?YW#}Ktz!f@7CtEt+n6aVRo5W`93QF%2quIyUi5;{#^Xg?pfEbh@(iN
zmnm{Nmt@`ysEH{?lV~tmjOGHU!le}}!Ztg903UQai~bpCS<aq34%;;gEWa<XaxB$a
z*_daLQN$dso3XpCx;6_f7L0nZBj#TgG#w|0(j<8>J=>vAoew3|s_QGw*~Cm!(f0A#
zMPMN{SA`SjdL|CCt?r~0yfx28`n6r4jo){!JB~@_wf$f>R#Vc}IJcc}5~_J8nR^${
zl5yGr84yf5AEwdPvM~MBMXE&jIn#hL3u<FLF7;^5qBe)Ff-7Nx!dT7xAY!jTKskN*
z<DPb-tj}b%Kefv`Nko_9MvFy;UxdG`Qf#MJztz{X**kx@zZXmLNPCmAmL0xOO--}|
zF89f+Y;0}<7bI85r~BL^`v44QRxub>B|kcZT0k|$DE%|ay09w}ILoWC7;fZysp80=
z;udkd2@KcBSY%a-E;E0Bl6XcczHmQ4rXFA`Vy+GYU&*&BxiCK+%Eo%cbpd_NNb3^_
ztjF8DL&QH_WS&9$72!-m0Z7O1HhOoeeb;a8pl<wc!Nh{O;Qp)5!gx_I3L~b~Soal|
zPmD63!d~%uPZ(e0jof<M+0>%oEOn9x{q6f0>}$z}p5Hp)?(D-zBS-Wnmd$E{>`7^(
z)2|b9Al#R$bDB#W848Y$OK7j4mrEqN!YGG};1PTtiOSlmGgtrJu=$BgedgQ7%-5wN
z#qy?hy8QS0?jGl9BV98G%f8SowWL;%^^31vXS=I_e*ven>-V9UXmF{QVR)dE47Ty=
zyFRQ}V(o*@-3=x5@6A8f?!RFz^dcG;w&iW)@O_=yzIQHuv?@U1smB5dR{w+31&uk_
zi#As=9zM_)4ABVuM&Bf<*hj)9ObfqhDB@!S%4}qoG@tN7*$r*+Tpe3fUW+7RBKm+*
zR{U>TriN(Tp~~olD{`p{kT)-Xvo-(M1urK_febiJh&XAMyLkjB)Pe7IcXfpf6Lz2>
zSi~X0ml6_uPz;5eH|c001s%K4w|ByhGl;EYHqaG7(X_s1HkEYlG=v)d`!YW>yP=Gk
zb`dEn1Ze<da~{vA4%=3W*dVOlY9HM}J<8XvW#eT~K}B5h&zZq;f&p7><hR)B;&x_A
zx>l2AjtA)|#c3<YKl2eM@Y0$}(7-6pg-WqL5^`?Db{QDoahTQ6Q)!M|7gHOo!TRK<
z{yt13txGj^q*$#R7egJ)C+<6e$Z;+#RF-CZ=03t1m~E-EK7SR*UJ2an;}Ly9Is<D0
z_xwQe5m?Kj6GKSw-pUzZ5VVZR^U7fSNUiBX)<ON8AlLav;>fjtiKW8hM3pj>oSp8;
zPf0~eaRtE>@ny|)qG(NkG7U2x43x*n3;uXldxs*j`T1nJ?6aA(JQr|G3Bas~Uh45I
zl_suap*W3~UvuJbtC*S(^5(jEWHvner-+jz1$a%40i4GWR^r&+R&*k}@q-Q>WMNH>
zc*I#%een(t(gSKN;oXeLOh)jt-2KX>INfypT#plH8+yF-fKra$B<1GWqj-itZe7zS
zF+;?OLNOaKv!-4?y0#cSB}>4(oyRP`XQ)6uWC1eZSX1P@Op3FzR=qB1!oEnKQ{c%w
zn_gtV3_xpkg7h8qz0@%j_p+<T{slK^#>unf_JLmq_vsJ3qLwiWZyNiWz}SqyOI;Te
ze8lI%i&mk2^b_riWW$xtduA$WFRw=HAd)xVB@N4_z%n_3&Ep+7vAEvz%@JxjZ)!J-
zEi-lNw4wJ%;)CXA<S!iffpFfyRl&Q=7l$j6#()^5m>%&&&vS!GRAsQd_<>sstE6f@
zb+hswQu|L-Pn*48n&o&2hHhxHFe$(fs87y;vw%$jwepptpGe{;uF~x9VB0EQ9vEm!
z8<h&(T@L}!-++$1!3bl5;*4>CLf9WB4QaEgc)J7^uK2SkE<;eojyCF<zz<Ev)hm39
zixxO4)&&4vPX?G@wApfi3&5B)xjYnz#bYXpVEIxdR`_MEL{CGTIZKQ+Q5XE#wxTl_
zbasI|t=@$RjnnpJDvieZC<LBZ@l>W)i%K`;_*6d*J)}+8gdLc!P**qmU~8ic0}_w#
zr2iV<VcwyZ$K6R&fQkqU1uT%#XUD}gVo9nO0CS{E!m7J=xzh+@eCf{bx*DPnw>X6!
zX?i#IPaX#s+11d92zxiGwYJ6$o1J^oo^*Al#WRH`Tu>tV6nZ05djIwoN3ngrw>1yQ
zMF_)RjUs%!5oP1LzSX+!LcIWrU&tvfUBrAtXnIZ&`R&E!-kLoMPk<_Wx{Lyj>P}Wc
zkup`m%(KKK*)WTNRm2xMLek}qc6MxUm%Z=<!ZN<Wdg%oqj(k7g)=CUX0rmryNnV--
zVe<;=rTevo!&!%#mwu!eGa)-PEc5Bg6TA$5(pS<trir{R+8tTN@u|Oqy~1568<`%C
zMt#W%@abEpB4z*N<SElbp3L_~M3@~1`EIN+wJK|3+#N<<XcWQ%{0RJ0XYcDhzyhWI
zMGuNTqs<ir2+Q1kX=E=8b>aedXGh}EA6Vai^L^zfS6fO>4REIY4@6IxEHdjiU`rcZ
zaEXuNy>VORKifhfaD--{Vc%)SFTha^UKpnS*1X?SvC6N@UEhljcdV^4cNWB0{t{LN
zRe%1vV5R|o*_EqE&TaDxAOw<3gue#E@Qxbo(9Lqg>JmS>0Kv8ZNj3cBM@!yyB9cEC
z9nMx{)C4Jn$2E;OrLeFk@aT7cB08DT7P5qXgBErZfxv1)pMIxQyOPXCIWsvKl8F{4
zKZ0}EXpsRkuIEi{MP-4gCe=JCDP|pw#h2oR0J84k7rt9Y<PfQAz=XxVhjQ*oGtkxx
zLm7szS|hI#ql0P{WeZF_NJWQ%P$_=sk|l%ZH+gV@9SG##h;@92iVu7DTdT7hc7$k6
z;T(f>uiCjt7kR4qgy>>t+oj8^Lr(lw96ns8!)7xZOgg<3Nu5=KnheiFgANaBiq|W=
zF!m~V-lN8FK(^i#s+K$3TrQ@_z#Jg`?Fg2{{iW-cJ34`NQ%lMC6o3yY#jR#nMPVHR
zDMd&=)M#L$Vt(Er)w@3wU<EQYAXC$?xhy@@Y<&$0%MAZwRAi0z1y9EG3Zynz_1joI
z&iml*fu&qB<Y^wl&WWZI=?nPqO_7D)>};=)aSS%`4HDDbs#ra97=;&}tT2g=Fsge4
z&zSM~>scI1#@rx#t!HygT^T@%q0esyFtR{RP7aO`S5(LidvoGmPrnOu%;`|_60W_{
z=AFk_kg`^7z!kBlOC`Wiq}R71m=F5#P8KkSZwlJlsPz_C2XR~5x(98!3krHLS!6mO
zocw^4x~8bcSAv6<Y1KyM+kdrpE7eS`&)QVkT}T20a~c+R!JEzA3%liy3-)CvUtZ?T
zbV;nBbKi$NJysC{qAj1LD3n-mRQ-J-O_h+5BO`XRU-Eh&t)=kQL;~IGrt9!kr*2w#
zN*~8aRBwJQSt4`!iavO1rYz<ngozlkjCop^=*#xIMAfYi?ogLs&g+~*D=N(1o_MyI
z&+UAQ)L#M28=LDMJkd7F=z}rIF$A2!3>W?&8z+$x9@_;71O>TD{N?%4V>>0CkzXCM
zm;BX_1c)FWe;NseuS8GT_0An#y7+6UcE|wbs;<f1aM+03Y4aTvM#e+4>ENp`i{_{w
zeR1y0utBQ6y0Ak$#eGvbVg+P4xho`<_wqTc)078&t}k3C{<=jkDsc{`rW6I%pdBPw
zyg##MaAwi@*`TUae>57TAgw@ItJ0$4r-6(DrRt%b1!{}EJj5E42W%VsX!1=;rsQox
zK1k(kjBD4wdlZA`K)s%r6m$Vp8&q)K7pBV%JBX3kF#bowFjT(^gKG()iHNmQsW=*5
zi}N&rzigE>X<!mQegIHq%r8HLr!sbR0bnnB_3-+t{WCNsednP6Dau|=D^~AZSHmB|
z@gpsFrdl*T{mUPpSvFX4?VEEB<RJ4LZ0tAi3vQH`bL6y*)nd_k*$q<QGoYz~V?p<^
z<<<VV-23qKeG^A%2xIsDrn9T*wriF7C*Sa^X`LY@S=>aC1Fh{_3|si}>M!WYH&d#C
zQ>-IFk#?9n=nyX62Wwe-8+oJ9?qJ#KUINu>4nGw<bE1JWh>c%i-{I<Yqsb74RgS(t
z^P$Z31Ap_@&1W#@7FD@W>f_yV%tlcOADj($;OFgjU`euIV`5bkLbkf1&Ho2NU5z;@
zNoN5CTK&%3rZ1>|Gf>3c3lRidE0Yyv;&ITaPey7C*gto&TXtVuGs%Q-hLM`FsS>Ei
zT|_tmZ)z;&Rb9Qpe0_fxH-f;zbIk&Ft*!hcl!GhA0vKIrm9Kt9UozSN?{V_6s6maR
zM&_Cf&Jt6KvEwO*s$(Y)8$+^9SDh89+M!g@jX<i~u$_JVNK%4X&B6N`C*6*h5v{d$
zd7G6;-7cl6kvDm}v<&nL#(c~O1{us$igL&E_s>hlj;*Dy)-X_0E=JoFxHz$uF*>`_
z!-0%{s?#Akj}QMU#q!Sz&xcK|40>1og$Ky^?GOS<p#I?&pT{d-*LO^C4^Z~$#260<
z=}r|u(E|jHylksb#a17$gwG<JjyY9*`E^tMY-`UV#3+1?;H2bZY-oMIB@=xA&Myrm
z>LdU63J3kN4ygw|Y4voie|El)W&Q-2IThL;&-$n6s3e$ed7ZWcKktN2#({Y8Ic~H!
z91oCzXoQ`8WYLHaYjoGYPQb7pT#3UDJutH{5{1kCKz&=f^1OU`!h;Pg4=(K=y`-qL
z#%q{ysG4|)USg9j>CML_N-*-^rd9&i&~Y+K!s3QkzDu=i-F(wEis<sgOCSNtn8s<&
zNVFtSKWR$Vjp<kgtMiCC%8uWEbSuRvd+Z?WiGH>xK?3d#lGvZ8V&dM(Yhrp>6_KmU
zkSsg9i~nk-5D_?JhIvb)>El3n0{e6!aNC4cV4FFjy5O0N3oru`b-wNA0DT+I1bCq1
z^Z2M-+xId}*i;@MZ|>itD=;Ffiu&crc_K%82Pe~jm2-cshkUz5c~7t95+}R=wH3IV
z|M;UjOO;|O-&Liq%n8Yp>ZV#`H3AswS#hc;bjuTn#i2<LffiGT1SHlO)*5~FRDyCP
zjz`*FYLfwJb*x*gM+U(B!IvI=A&$2`{B=|9>MBg%i*&-)g=n(THA|wA&~Ix_NgU*U
z#Swf2M<HGgKR+!fJcl$edy-glxWYG&@F_Y@J8qmtK3cd4Zav)Q4jaHwRiSBCP5@sv
z-eMv%eXF^+^<uj8R};i{C`g?qpy|H(&0VXul?*bfotw!UOSlN4K>2&xs=IhxnT=j!
zk_zL^HjnW4)=XU4i?Z0%+cS3Ydp?f=^P2Rj7C{czMAuza9NH0GoWI-1G@ux2czyYD
zoI^YItOy+8__kS(paalNsI5nK2L=GqaX4@pro#pCNTY?*#8kC!N8$DNOvMGfsi*p9
z=0JD_lU#E^-GB7a`@_*eZj0JzkrEA+{?}n}^aaG^iy1m#bjG<HmM?t(iO09(VjPI~
z=2O5jmax2b*lrdHri5@!6(B!6`wLG1z!1;pD-Z1$?DYu%Dm4VQ>MKMmh!VRx;Ux3M
zLi|O$M-4`jHE~<^HL(~2Z7YcebZ8aY^zPn?`^D{zD;PbHS#S+f(n!P%%J@OkS#tVi
zUrEPe-Y@zggj=6lnnkhi_1^~r$c775)cPQs8qhvDKJUOWRora-?FG<Jh4Np^B|T3Y
zLcrEO9m+lv;dF8Lwb`?9eDs)+1p*ZttV>_ThMK!oi?JQ(sO^ogc+(JN{V*AB)zivg
zquF(MM*vUjxW~8cqpGwFyOEx(7S9PbG#c~ZJi!sj3LHPt|GAwp9)XE;b2-+{;NTIG
zADO+lPrXSSo0$h_myomz`c7^#uAxgu<yf=Y4Yv*EuNf0LDlC-HwqZ?)SVgr<F-kOT
zH$j#te^&iC{RBRY+`T0GGRWR<KgfC;x4(ROCk#O&lCpmC0BPfqCGMLmHWI`2-2Vd6
zNGQ-yBVfsFw=SI^OXhfj<Ir+0nH|69e9}#YKgc7Hi#2jZ^RvaEuwrUPI_AI5he&x>
z^M$7lAvQ`90cE3HbSSE*ih+9ukS&nJGk-`WVZI`jkr%{tw!7Cj-K7evfHrlT0k(O-
zW?hj@*40*Wkngb>Ro+`wJJOr~(Jst!nr(7Z(CQ~}88Djor1;vN&;$%tKhKk$!}=Uu
zIKam|J=^JUNdZIM?#4|AW0El(p(r-P-5FLk#Y*E9%X2tbGvjZL+nGEDE(RxSRdP4-
z-vHoG*#g`<ZU>rJg{i9lN~_zu6UbGe1huI2^$((9P@rfX-Y`~`eCdUGSGxs<Dru3g
zxQcVRGW3z{zhur|o`hr1IxF|)>GrQ-L<OxrK*w(|X?vCF0Q#!nDI7jnqO=F{8Mf0F
zUnRv3Q@vBd`_*2f3~3nuQZBT-KEOcFh#9%xj!<z85B8?BrhP<msGskr&+{k$_t|NS
ztio_~GWx1yAHCpO*N+Lu{xlh11L?NsYb%zAcpUInd)tH7Av_!+f9`SbFh{~0w?KL-
z5p9W{L$j#z432@PFkWaPU>k7QGoN1_WWx~T9EAE2%<XsbwC9`j_WFtQG{!o9esTT8
zFzMh(8efw4i!8CtXEK{PxK9k5CW(>tU>BFTw$jrAfTAu8Jm>6VBsQB+D<s97u_D(%
zWZJ56D@io2TW^9fi?($?rtRApHb9WX5K%O+ed~V2C8D$r=J$9@HI&soB~j9Tj!a!u
zQDuOh<q=<pa==#P3mfx*GvH$OK0xs_|Hw9h7USy^%5pZ;8G)i+^J(H`K`lm*ODKCl
z_=L$wD9|g&PGo`}at<b0!%9i91={R%)IBu^XT}&7P2Cc=944uu20}#tNpm+w9cjan
z;ul%dVZ=laq%(<Dy8kRjcdLb`;h)=d<ID%Pd(xTX5#Ur+1GQg^@e<5DV5ey~u|T}D
zjR267BlV6#2}$SjCbWqNSc`%g*GtM-`h5==z}k$D7}+bQ=@s$I#9$Jl>0f<nZT&dV
zKLL%kT{m-vbEn^syQ(ek&6`BAq<EkYW+fMZ*}9ntj1p9H1JJ1ieS43d>?k8YuRKNB
z^{J*l6EK1crX8A6XZC?r5!wFG@;~Ryh6Bo!4r4HskR{Wlf`L5j$~_W7Q0H{lodd5C
zr$U^fULhicp5+$xR4XLI`W_5nmS;atT`pS0kMMzg#!%gN%D8eNKU&)N4f~dZwh7qM
zndcV9TGo{&Lp={i+a0cLXF&v7o>L+W_&r2URF)0N8uc@FL;-xoEB}CP*bl&=9by!1
z<L$t8e{GF})!uz&W(he#J~N&!x`m6oXI5o3&S&Byyx5>?q&Q{cN?rPQJw^st5k$}a
zg53^g0P<opW3G1jm$`d^QJ$M&n(UCudbn+h7oH-J>gt!r+ZxX+z4Ksy$JZ&@x8+#>
z64r?@iWpUq)jB8Al{KDH^Xyr0h31!C5gX3UoMMZXTqyc9_Sz8pLRE%Nzn#ynVloMJ
z#IG4BQOP*|9r3c#z{?r|9t2W@9w;B6XR*$k=%*WGMR;(#D(X`TRdW1EpR;pKq#2gN
zXY*~)laQoREkC<-YmhcirwhEkv#tfVbXAUfpwlM@6YrPW^{2p{_U%_f`0;CuHN?jw
zL%1B5F5%v-%K}(mu}>RRXno75HmajzD5}LSlMUq9TQ3Zkw78v_P3tk~NoUH6z@dm7
zI|AhkPWTX~$15gnOIr5w<1sIkmZUKVacMiK3jS`=1%#3Ash^gP^la!`L@&?ST(hW8
zmm{H^$nseyiY<|G%zhfxdF{MXAe}+2k8>%pVD_;W?6pNJ!|sah;WAtx1sXake(d~$
zjlDAAwB49Bhf$la2@h%bi|DcZj$e?j7v8*ERQFxDz?%-+=u){CH4hcno(b9|hWZQz
zh@55eY+e)VMQjmk6Rx5@jCB6HLopHD_E8IJA!08SH3rSOt~z5|`=wh8kTJ7MNQPBR
zeovDcy0$o-VGfMd1OnN<4<b!d<}B4AMN(gj4ghScLxNKpp;a_TI8pvGoLNv$jmzp2
zqyscF`nRQwCyvfDx%0CxHhJuwX?BKixAm15t}yvL8WoJC`*As`PfQ?S8tj<*v9bFL
zMtK|wvZ*~*Dli~haprG*Rl`r5yRH~umY4&y?28$RU!$qNEQ-k~Oyc~XY$53&&ZniM
ztNh`BJoW>}|7)3jxUB4gxNeC=)Q6bLaww#0(hSqD13{6=65Tvk!&eNqEn!-v1GQ=!
zM!}ab252MLumVGd%`U`PN|a~G7;c)lp#T0jXz5VRO|4&(0t(KGOR9SiO4$jt1t9^@
zS2L6TgLHg!UPoEtSKhZgdBXoIh%FwZ0Pd^T^D?Q@5==MpZGmn%sU@IS2BF(d51X2u
ztdD>`I-3YWJ&Vx2Tp5$or^?l=(+?nw3SGWnbXFhsMkrW_v3FiAL(!(Dff_vGegQ_7
z;-x%PF`D2BNI-xqbn6*AE64$#hSI-oCK5WtMUN_(G>24zt8|({oE<uye{pf72OQv8
zn6*t25iY#ZIuzxt5UBB<<ta&MHlC%pRCO<q5W=dKY}_jb1Fz*oszbX#Kd~|g&%(51
z?%0%tS`)W2ZBqQ`0}$E~bcx(n{1?TAAN2KFB&}B<q8ERln^XXg#G)b;rRx<qMFu*T
zW+>~qcwdZ|{vrxlCw98qabK0Qu?aSmlP+U)kV-uQiRtr%A;)+5=N1JNmK#i8nf3uO
zAqE7WZSn|8{I)ovXPrK#G9Pr((~rn9jrv;etok!Fq(ske2X<%z#a|t4$2!p)QdecA
zxG$T@L*^F#T(qt^{*mwF0ESkzgFKuXly{}$Px_UuD8jqRU%ph+KX~`cXi`o>oeW?t
zHb|*ePTR;D0_*z2HmF;oxOZ5&;D+FD{=N#1e;tgcZC+FAVPBeA$B@ri^2qo@ZpE77
zEXr%Xtz?3~DhMr-Z655db!BErJXZXahYva`?&EW6WL~tmZ+w9-@mu573L71PP}dB;
zNKV$+saFIM=h171a7T_a2bVYBG?#oS3`b!&aF0clMd~gqtsCk8lTB)WmX4acxO8bv
z{sXcQP%lvepG1%c*=0WWj9*ox!&wKRM=Fu12+UzL1{G&~^m}KM+S*ONFp&?STG&|N
zp-?IQBu8I1BVBUKvRqt)UzZ5yew}zMa}ibY;%PjN$@~2oD2lMJu<h_Fme=sjCX=ta
z2tz;c;WIYqv?QIn>Jx1>=xA+0#b-W}hWzRiB^N!MGRZW|k*1a{=U7R$Rd&x*Ohg!j
z!A)VE+M8tQAhswqP6G2|zWK#rKr`GbHX0Koe<=TJ@3L?#yd?fBA*o)wnQB};(giyo
z*%k8VvegJq^ftMx0~{aD&p?XA1`_u0$EqWK{n|{XLkv25C~f_!nzviQKcd@jj&xm>
zOBA6J#e#*j*+<YAM!%3pG~$_e!-2ZUoy34pB+U@&|3>i}3wo8bjjZM>3p>tDoSJMc
zDyEgfZraptv>}YvY=%mL-q6&g@}_ybSaz@+UfNFnyyM!=OXjQSH<=oeX95<e1lQ9p
zVn|q4U@!*Oe_JS2h9Qi61NBZNyqL4#)>3VRQH`Bga@mN1d(9pu8kQSqWoDY_u<F6o
zZ^+MRT%+oe{S-~EF$kW|WlR4uzTH);2_>VBBqMn()N9l(_)S)qEt!o~S0Sc!mbhI|
zfb|N6*}cE4E)C$n57LICikl(YqmRn2<e)<M?bz<>iP?~>;U*MO0vCA5nNWnGa)#2Q
zXHqNtLe~=v|6<?Sx5Y#@%>(Z=$~70xu5kg?)7V`0e-uargObOMi0!I9iClj0r8k|X
z2)>TwCv|fGpxOt}G8sS6g8U|sOON><Ctnf!vsu9CQL)Ox;8(}BeLLWy^uEBZ>X(z$
zvJDd#Z0#c2KpW#0j|RALiX~PRxp(hZWysu-wp0oj8y`&X5J9t0pF;#rgX>iM4V;&>
zt<diJ_Y3V%<Ec1Wael7MK++WIH*IpX`tSm9nEF2YE+lX4re^9dRjOz`{Ouw;Bn<4~
zrh`2qxoXXfPI$-oGCZ~>1XC9AqmRJ?J#qg!KvT=95{cEA!&Y+{TWxNqxg3HI#q<?c
zp|(NbKiF+*a33#HAg+{Phi)xN5UU%qL`PXI-(-b(t#fFoMCSg<JWFkj9U8$chx<c6
zq;<4YGAX72ydT<;^6JYTXnn39R<Ba{sS5Cq9!3NO*od`cVH|h<%4f7e?AP7ev<`^x
z>G!rI7#XLk@pscws1hgh?et*c6>I9+8PGe370g3wOb$3#4~H{Og!Apa>@twG-R<ox
zrXD#mF%?*~ETATbHmDK~x!0dFXf*v{;FS1>Z>ks#A}+qu^AMR&Ksg|}4WzYgB&iy|
zb^b*xz3Mi|Q+el<sVejg{rIx#nC&&I)wnhF20}X8(7_b?0ONJAoro{3I@$A$faBb$
zvCyK$J%Qv?toYN@uYjv6x_b%*c`OBau{(fb%|IjEL98#xd}~FcNlW5fHYF{|pFiA&
zk;bK@O292;?W53&>*F&S`8u-xyNyo{Y&lK7X-W*|d-|6Qj=-xtd(yD`U@BsnC$oTj
zG|}lI^R~7LlZBw?(z=Am(W+2;>JAVuOo)5V#}UGuA^MA>q}s;*s}aQIlDFmGE=g}E
z3nMILBuh-8(B}vXc#o?8=k@37@a~IejzWDM3m@{|30II&31*rNE_EJlwS(phu~Wq@
zKJ25e+uu5oZ___|lNT8?Yyox<HR3r}nmT#T<}=F$<RUgY!`-q>?)G&2ZDm_d<!Ty^
zqvUBY)rj1i;>bn79*>S8=6%ATU3@O?lP!2q9)yh3v)EPT4-dyBXik(Mea}-`UGy=#
zWP2h}o1~iW;Qg|(W%|6ZPY@qJIT!OKlaNpN9t-PDpehl-c)C$^nGgm}H%rYYwwVrq
zNcS4?YEvy}w-~6g#XsB%bC&6~?aEYF_bcEs|AB;eioQ+(G1EkslRed7d|A-@jkFo8
zO^@C%WkVt+yQ#k7t=H)8(JyC`w7Q@U3#b_iY1#mFz%R#0t-LDq3bTVi+F^`@IAo^h
zTkOdMF9j)0yLHnX{0FT>6$&!_tp%z>IB_uG`Ue1MNwi%vL6&m0G4=eMg)W0`=e^<z
z1^dP-X^6I2LgEO}EdRUQ%eOji6&_Kx=x&-Pd2yf8BzHT&QN>|5*I3K3U-@$6aXiGa
z^OY)Z85)A7kRAnM`T8)Q-nWSOi{AEad`@u3_Idzq2(Jt#wsyFz1=Z16-}Zl@VAL8l
zD%GGikWm0)FY(iN;J->uz+<{Rx)+~g(vK10%9$Z|1p8m?|3pRaIzPk^NsXS^C9e+p
zIlzy=;Vx=@>Wi(L@;M5e)j+W&g8A_RG!{#IN~T&XYlV-^`^A8U_-)mI*t~)Nh(m9>
z_!(5Y<pqS>qtC3Tu3wMX3sO4nNM&u`<;2Sq7E+=bNwo_>t=bca{F6`W*(=Gi%Wph5
zICi{QtrZ9UZKihx?H$)rn(5SBznXC?yszS5Dgt$r8f_*s?hgeo^vxLK>Hh^T*qT-)
z^s!GB!%Qor>&2ITZ`xNnQJNvW7$`1e%KI6mmmf%w(c)!x_XR~WVXpXYb@F)m_ku*-
zn5z_<#gA+q{HtUgU#XU&-^~u$_l7-iwK`fxmSD4Yl+*@FCu#v!*;^IEuGn<v3bqcH
zyCSl>mP)CRdR$%-$B>HF@(wn7%<KMfWdd8ROf!20Oq&1uM8C|PnURh9Ru-JNlE*b<
zVFbvZ@7qO$!Oc}su#Cb&7(LHTgw<1ptXp3h9&eAZH|gl6j++$UKo%l+n%)~Y^foLs
zUYRIQ@_#8z4S0-DDfOkUwl|zj)Gs}hR98R7Gz%(6xpzrMpQOju3MJ<5bdDG7FY7f1
z-z)Yy46FfS=a<NzqG6bv4RC+^+n)IXH8`@dZ9)FEI~UVZLf4lQ7;@+cPj3YImbgnW
zNo!{V^OW^NAVuuWgs$ciAt6uFLdT%2c>jpQx)HsYr)_pGo1O%1qr3;w65Bic2Z!Qa
zMq6;%5tJ#SPN;))LUJmm4G;ISbpVfokJZ?>1Yzf0kHgbT`{{2J*1v<uM_dj(dRG@v
z#C)!pp)-GKlC|fyn9QBQ{hbJsx7+=^3I-_ZpGvR6@z#om>&n?tZGQFM(VBWw6_DFY
zkc1(HTnw&ewd&=u4KrDj>=pYH3Lk8ORtefhl$(hR)G_)TGgdNY;!US<Ta$jeBWz$I
zv2cqrSjc9pk6eJ^DGp|Vi>pmx8IB#yv>zX4s<>Wf9u!G}`l5W?uJEtfF(?>(i<mR9
kunvufh#4M<fVIdM2h~3E2QPslUprE>e)N&<NnZ=44;Cgg4*&oF

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..9f48ed959ecda0d6864ff1233452962795f8def9
GIT binary patch
literal 28344
zcmV(nK=Qwf6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC9J9fNj3)!R|;7yfw
zLqk*2a6D8B2Z)AO!HcHC_4Z}I<I`4-hI9<pUR3}3WjG#sY1I#E?;IHixaxN{iG$66
zN4TOyP~+b6A8*rqt;9XJ?c{SDw(9wFy6*yheXBBL>kw-DP7y?kxCycTF=W?z2DBxi
zC4jq2Fyx9blQlYGLSf3Cgw;<D{qI88RAVOtxuhWJ(i~yT>&3^gD@rOB-{8MrqOAY8
z=zdqFGN-Ju5|TzgT#ykIu0`lI9+-;PeP&kt_H&p!r_@j|T1?*OaV#oaktVC<dbw*1
zuosHUi_~L20utSJSD}kQRNoTlpD_@=+@UHN>iB9k%JwjXaBk~M(9^#fVA@>wxtdLK
z_1!J1j86fim~nkwe8gb5OG=WZeGAX90ODc0uYDn{fz}zG-<yFzTQV$q-}(rf3&&+~
zbFn&bhQIR)<t~xZX{+K-H#&YkZ@x<C>~GL8Ql|LGBH!)?ICf20hg-8^ROIqK^Izo#
zt&yXX8HV-+STy$xy*YFXUzs{WF^BANd*!A{kVY7ALBR|<Dat~!w-*vp;?C&ZzCUDG
z)ozuVlgGl>l~pQ@zo=8)Pl@3DjR?3_l3GthE4hGLhEY)l5Un5xFnC&#dQ^eo*XrGz
z{?y>dE^hje<fc4T@`-PZ7C6L)Fa0ho!DfG$QU1B%c}$0V^)wSyXyTmFK*BOb<uHO~
zgkzw{0Yl+!A(i`VP+&=v2EI?uSRS>Cvk#Y%J#P7ZRt#b6TCdgqEK~)o`w3eiKUhQ4
zRc_#C7Z3qQaQ!?nS)ODXkY9$Rm^d0cU9Sr<zr}j?5u1ac;t7o>?Q8CFDFm|!{aI(-
zB6+W%M3-4=zQm>2d^=pGdEf722xA>j>H<%SW&xc8A2GH-0LhHUj;ZTel#tA+aMX51
z8I++szdcCF&2_}v6zuBxNb=LNk7dxMa?btAl8)_W1w=Y$B+KnsntiqLCdgfS@?FL^
zVHSpZE1*&XuUHvDp6whav)oc#<N1H|*!8%nP@Xa7^E?lb+|7t*`n`tQ>8t_BKaKd#
z!M5355K7Gvp^noJke*M5EB^|;=C=yXHd_w%eq?ml=!h$d@8QN++rd}_kbA&HFz!-;
zwM?udF({^EVbFFRh1JLHF8-|s1^rQ-?D90JfQ2Sc3SWR<IuyuUZ*V<5gt_^ya%XD(
zyh(Mo%B|Ex4za#f_y9+1a^u#e2vLFC&v-SHG%Kqz9*e~XOq5)LjjcMpS{*geEoB|%
zIE9`kX`%pu1js+D5hv1@KZM4_l3rr$G%g6OZNVfZ@}eh-y~=q{KL4Rz__qF=ED#D?
zHe#pwqa{qfexlPuIRsfC<Qw;JSa>K0Zu*b+>oXLBjIO^JGAm&`TsGQa%WA}U8~vms
z=%>%94g0=eDyu`_KOEd`0j}8IO?kYFMPbge|Dqf`By+z4cZHLs>h(niu_LWIAL470
z`MmN=MG%?2!1a9ye!+7V7mzH-_DNhMy%Dd67=r9_i@<L<?~ZNT7I;ioguT*_e;9T8
z|BjPpUy9B#q83e*8-^W)B0n%QxlnduQOxayQsZ)+ugOn^m)1kba1+;qbK$~Kr^l~{
zpNqtQK<)ZYkx6;ZPt-lTWIZtah3q6-%_4X{lQ}#6D1*z%X7gp;J#fSn@ZlCg7^{Ej
zJjqk;_U}XcnnR))vMxD}Jo2ZtavQq(Lff0fhkXa1TYD_F!cz$ISUrn!LOdr!Sm+DT
z3k&ik`}8N}w(W#GkVNIY+#ly*s!u?&y1c)>M465&Rg*Jq202z<-M&{k-6<va2lwDg
z8F7(y_H5t|xUA-<OPV$vqJ}34Jk7oK#@rLl2^#)b)Pl&2j9RB>#4m=6Q!~kw&>0Bz
zy5R7bo-WA3zmPo)C!!H`5jT41&re>{NbV?2K#~DC**SwzhFuz?Cmmh-IPe?X7H@cy
zwVc_t&^{)IDIg<p>U0Y|-l5l=Ld102N0FYQ_9O!S;s$eO!ldMy`>HUKJ>S(p;+)g6
zQJ9Ef@w{3%yh4ZqCbW9lv{cyXZQ48UPq~Z0Z$P@;7fgi$p(oSX8mWDyyq@YN-=Fh&
zsh5;t;8a0Ex40F0L9c4@N(<t4!+)|*1`3~I`*0B(v^?g<iJQJ6b%WnO?7Vx*s~Haz
zMS(;fO><>Qje&fQZu#ZTF5hH<SLOr=!R{G*-2<xk<ZoG33H56SWbqj*Y`U~D7T^p<
z-1bm$o(jvCroO|3s@__U)Ug@ry@eC}A%xoOBU}hf<uA5&WrrEJ-8U=5tuWGx*5_MJ
z-zH%&{cjAMyZKG|HT0hW?`zCu@9+W0A+l>Vr@&T%2Q>jL8CN_in!Nj5%kcyEVAub5
zUVgo1xOzxqIKN!f(mQd7#Rt#q^Sju#Y9$YWCMzW$3#zYNi9pd?1`9>a=kE-j^;6^F
zwA9}suwqoCX``DCa^ImxSPHK<B8l8Pf1M%^w6w}VWu+jusKpY6Y#3>5dH3KrtD2`D
z%uFxWjPQ50`vev9(lv%sKzell7Hyll6IG+1#OkP(*ATM{+bNmn>>DW<P_yc6-Sy)T
z$@qGnn)L4U{b8yoM^Imx^mexv*X6g1H_q3rhd@+~Qv8sh=bMwEo`JgkYxnH5(u%;@
z=h?#uXQW}}n$hT?8RB#m0N>#ENvtX`bJ_yN?V=zXZr9^PsYWJx1MBn`ARDt)0xwit
z4luR504(}gu_WeM5s^4QkXibN{&G}$QKVOw%Kx9vx(jfQzlRpow4=kkEh(m|JYp5L
zo`D0QK6E`^kX`^ztc-27yX^O9ixZ`tPRO{4)(SZWmF_l8??W&f%Tt|1l4AW5N^;0^
zwu|RUuy7m3mrW?xxIu+OI!MT~97P(gZ7&%9LgCG_9*O#+{K<d8;Sy4wq$M)6r8^_1
zjgD=wmKVLk6rvx)aiNp*@WYHSQ-ePv&9n@V*}-$p^Pbl@IH0NC!ZKv$U!EbjkC~(4
zXm86A;$4+MbK7o!BfUj5+6{n(7f*ELr@Dfaaa39B_8YN-CKD|mG}}~XDg&)Yh~dw}
zf`=H=?+RsCi5VOUSWa#I9fvVVXD;HgZKMLZ_WF^S627vRK)-ulL6%K4cD%qao|_y!
zCQot>&zrxagB@1j<dJ@!>M7gCXzzDXFFBThf7OdLf3>!bi4qr*C|c+u5zlDwN|?ST
zstu}^)w=0=64ao<iKm}<5=f+Zo(WhKgf7eig3!PEvu4sAN(fPImAg;%7ulm|>T<uM
z52e~*`G!plmEKP6lr#j(%>P;bZBK}r_sMR+EH5#^P09HkliP?dx+K%nsZ1*ajD#B!
z;xqGx3iwfOb|!JJseJ7QqydpbZ;XN7r4nv<l)!TLu5g0Z=}L5-&hutj!nTo+Wej)m
z(`4)^Ajn_lSP%H$2L~)JPJZl`O5n>?f&gR0-6%+7eB~`*!dxj#TCda|%9d$>;l@(s
zy$`N4+y3{*9UrM9+Jie07NU+*lwE~`(NCAqyMituU@|71V<AT(>VuUMEQr~@-VI_G
zyyzB>H1*GO|LxFFq4TXWDYvZJAP@qjW=A{+<Wkpuw=|`}Wtm*Ut;K?8F>RLTe{QzT
zzVn7YvVaQ}5t~<(iOzp-v*<f7EIiA3#VVlK_<h7DMR4TLTm9;riRnK0k(Bw8Isu)K
zLQ%GKvkfQU%$^|78+eD*UA@qGbcR*h(L=`+pM7W}1aH!bYA-!QGNL%)2iV)B)$R@|
zybn^Hj<^9hZ7gpR0mju{9G>aFq|+JE1e=EKrp<z}KZLM-W${**baUq3YUB*;6iva$
z^Z2=$Sl#{&H0~ocES<2iocB$tXO9Plm_T(DBM;>x>75LORS?XFsHMzv+p?K?+;o#b
z@eW7Dy_$A<^L<S79}=iUxF)DA=uJsw+v)|0lHDnPQr<%e!<Es2y$e}Nv^*l>PH-`D
z=_{T&nR~ub$*~lX{V+SWebO2L?On*=?e>nIb&Hl#IR#zMIWcz*<gfVOnx@;MczkTt
zXt9+2ex&KoPFu$YsCQFm*~%NL9_RE+Io-l!OvPA*0b38w2SIv%WR}H)q_lzkR}<5x
zZ%F{Yjmsu6nN`Kta8sKL?EQJerNc0)vx1RGYPN6r%Lh8TAae~qqb{QwlX=8=hdb{a
zJqCo(byUi&oHf>%(9d6OjOMe_NtX8`X1$2kN<aOniN-X2O;>MnqoOnvdR6AAwa#$m
z8BwkFuXfN4a%RER=~Y4@{$1MYVhi?U@B|?887QvRNA?JGkQ{lzmFVKR743dn<F2Lm
zmjB-CW!@)!-%oXbpu<3zhc+aYwM8rp-c`WQzFt}#Hns~_<{o(?h6~c7?Sib)r2w4E
zrO?GaZ2}s|eJdfzAO~R2_*|hR$Jq6(dj-~7C}ut7JSvJ%w3vSW%L{TfTPIRHHx(<3
zvVR$^g=8k-gOF3Iw&|Cl+qw|qQq22HCbLPz9C&V`PP6O{ruITCK}@n7_}6+QU+@A7
z0{2tdq+9D0rxc-WB>nXrae0(q+=0Mrq)oyS&#Zrq>A+qUqVb;lFq=uMn%37oTQq(D
z{_BqYC{jX{^1=cUwufS_+(x$e@Yh(Zqno%q)uZ$P%Jzz`=pS8Sd<5iKe)%t>AVF=6
zjzyic1dCvMq7f$Uh!d?F%M71LAd5!`2O@{tU#T1f1xfE8G!Ys>DDV9~%12rkYDBik
zVcWVJ-phF*p-0OQ4+5IE5nVetR*AEM{>!=EInXroG6YzXaRnA3GW(pOEasoI4kP5{
z+yp9Pcd%(AcAoJb!DhCXbY8JduftCYtGA?Z@?|RHf693zWxj0&bGq>QRe|^;$V!mZ
z8TWg|imGU931~FIYwotFxoQm}H-Ml0z>P`6oxIb^#%Id%4^VZUs7Df-<?kjq=p3@(
z2V!%}J<#sNss>HbYwN_iD;_8y&+j+GonWq}DQ)h2zvqB8hF;5B7lz!C8?74D_4!>B
z8p;fYPzW-n@@>2nRwc4v+*kV@W}HV@71Ds7Y%*!Pj6l_O9^WgN53qLN4|yuGl<7l1
zF6Mz0B4x?>*S`+ix(!bfgG_<cAn1?D$xFBroLBj4owqL^#sL087+s8a*b%(9=#FvO
z=6}t3IW)+>*Lb!1c!Chs-my8-w_1w}7Jl8~%yR<X72W#s=q1`C&jO0y#O2$R#d{)_
zb0>?WRsnkf<%kPK4Eawuyx5&&>v2aD_OhaiDwBGb5hn!!C_n2jQK~oqr{F%%<|X4~
z=5E~{3KN%iZwz1coCg$ljD;rl#~Ze3f(CBWyk|20Yo2cXW_d!ex>*g+*v<65Jo@>O
z+2Yb{Tevbk$Z|~9H9EvjAt1W9qu(0fK3RD#CIV{-OEy#r#9evk${6rIg<ilRuv6pc
zogf`=^X16vjxsXOVZxiOhkJ<<i6{OUTr61@4*ElG84|*z04=KN+_3=EisJpnka+o5
zO<*H|Z7JUm2ufhVd@f<aTcuaYsa7uhU}**8^8G-LEyixQ9bh}#;nU~_+N@aR)-$}0
zaRlO6RDpW^O5gGV5hP%B4>S#9jE#}goEYJ&QlXs;v=pCx^cyJZ#@`WyuT58nwgC;`
za++aL($tREI`gbv0f?IRSwD$VTipIviZ%_2EgVOo8Z7(uqVwy)-!>Q`$DyRDhq(XJ
z=;$?e7w9Aks+Mv9YtB6+Y#iHo_QJ1KWHchQ#@}vHO90(X$ieE_5xmi@ZV#x4Y^YM~
z@#TF#E14$ZM%g34Uhy{ek5{AqZ}mddl1>^PS&m6Yr*gJojfB)px&AD2djv6Bqd?4L
z;o%PLR_umY@kXQfXjRV;d>*VUYVJny<g+ZE)uwoY1TE(NuU{=d_sMvzJ@rz9scmeZ
zYMhs)zMIzDcd7?%<|S{|qgzv93NQ1EYmdK{zZ%qXl#}+<^Ef#Jx!Gz9I92qe+%{Po
zuaw9*gvzgjTbt3RtCj7r*mLzH4m%fIpGZw-sMH}aQ`H}4s(RI_Sl%P-o4J8og?=Ah
z`3F=SV(_gMjJvvr{Nw510N#oF#I@Hagwb@n^M&XN5<2oO!UwWYDHI@P3Lmu^+`(`4
zh}KS`xO<_HK;-$95ZpQVraqi3Rw*?X!*?sw9*<)|3b?Q=uiY-#7#lNqTpDsY+(yi(
zN;PU3qragNYW`hisXB^zoZ|`J&WtV}#2Lrm#>Ju$sJJ-tKIIO!*kr94id-CYlLBq=
zngVdOVFT>1p6}&-I5u=u+!2__^Ck{~FL(ch=pAYIrda=4#)W%;6pgHS_=>M?6z;)A
z6FmRD?bXSh0v%sVd>#CvLA4{ZD&^uwWhUr#N4c)xx6jpV5rYTvU+8R9Ir?u0JL=;9
zQ!u9(zRXuzO@Uaf?ZUysehv%$xZmgHU^OFEp}+kmxlJvY{Tqg|u9Puh2F?W_CO^u#
z+`-CLrxl&(W#YI|q@1dKKSHo5nbzyon0&vWG)vyRb_DcB$fr4e7|po!`t^U)F~eI_
z*kFCD`dJ6TxwRgqCp3})+0_VE2M~wIYwtO|6DRrvLI@)gCXm+-b(Bpe^z0BReL$2n
zVVUp50k|ascRsApw8oJxWz||v>_AMmTbUK)a;=T>k^&xe*@3eIOvuUOl6l++=VNP_
z`6eVJ-&k<mF`6Sv1&tN3>9VF>X{<&#PuK_<RSxN~HW}u@#Y8h(-2y<SOCMx{=a$z<
zUci^obI|JROSJIFbFvDmDy*vC8{!JzamGp)d4-rxMcBUDc{WI4u$z@c)#@B5OBByY
z*-gcTLH9)ObKf^3smeMW$f0Ky>|xwaOX0mB9o<aR=^kn9a}P^?OXqQ7)~<=awB#<h
z+K4++6|dZUg%*a>UcQa3G#03OSlseO1KSbc(p44ylMo(Z*pLT3n)q&<)vJYS4EmDj
zK^;(fzXXG8>viU}S_(uGbS$$~3+EQqEOO*489e~U8SmS+IVs~FX3<~54-*e!5_5xM
zL4dVYD43+H=D~h)lqvehH;LoI>IA;_oTlsAOzLzZsd>R9V);&xrm4iGuC#<RT&B%4
z#QxCw+i!}&c-<our5`-+?3WKrMIonP+i-6InMrh_oRqi~_yo0NARxzDH$&bRk-xo~
z+Q6OjvO{s`AA-T4n&wk{&sYqU%ww3G$0QI`-MI@4+;84kmpYJ)adBhD{IKY-XaY@9
zV9fVPZ}b4@fG0oxUy=UuE=*MUqW?|=t!+wsznd?oK|qK^GJDHl^ZkYZR#$`y!km>>
zI+^t#llT$sM^0YPxyF?fy=!#xY}+3yy0sYgk-tZ*p?HlZFZ}%6O(LH4b*)<KqQz~i
z<mEvk9v-m4E{;^Ev}umIDL&fa4L5rvRIdk1($y+~lqvd0gbL;{vO=wNVRy6T`NLeX
zu85Q}w>mJQT`=CzkWZ2jc+wZ>&!ZW&Bo0OX&#d<_A+Ln4cIJVUz={P9EpS|yvdmw0
ziz$6c{(sD0`2iNUFiNha;{9leW<8;iuipC9W3Qe)7Ds@&Pi@^$?WpA!&N7rSRJwNJ
z+ZhbGslIsE_D<1eL=5f^h5wsa@uERNz0fF)K>5zqA7M2k4+c&)qe16|NjiEg(D#Wv
zzP^Z~cvIPIr+>S&*{y(G%-*9|y0>3CtCEaR`fMh1Ah$e&BjC=rbsRB&5Q8~+8o$L1
zzh)D3;C(<IrscU+L7w*+iW!@7Y@ft4a`sl<M|w0OS!(;BbEbjkaEWu#b1{R`!+dxw
z<LA?HwagVxMuNouNW8P2s6Udrt!o$R{J&(@Eg=RX)lsD1ySybQYlvtfPCgfmHskEz
zB44%<3b~e6SR5*$T~CI)Ss^ROrHw@4`MIofjgEh_5cWiNE?xDC&#y^!GOG5Fy=s)g
zSdSHr+9=K}HyfQKa+5A+RD5hu<cQX!fglX}0mow*^go5NZ&~-sq)`m9!WY!OdqWt<
zT1z*&W*PkGIWV?C6$m-k@;~i8fEBPCY=+2((~Oi3t$VQkg`<N~+eQlZwI*p#S<~lT
zx$&U2<62-;!fQ@DogMgqUQ+Z<gE`n=z^c3D0eV@UcV$=wghi@y&L*gFP24Zg>PL22
zGIR_`!F7}a@bnoO&t>5s9g~^IyWLLg1Ks^MkLwydbF}I%JsXeJHtJ2OTu{*-NIhY2
z07i7NUNCWwpk%>GM?hox+V0#OYydBxU}_-{HpQ&PRto}LN{}k5*BVsP;RzWtmO*AV
zmcZAR1krWU@(@MTvC!?oGg)NJ<|!eOR0s7*E)tdy=vHN|CB_YGtk2m?uP*-E9&Sc%
zJuYRB&W7U3bz6{elK#AxcA)e;YMS<+O=UFE5R!D6<C%&!1&US9gQEdA47MVIHE)Gy
zRk&%BxDz@0bCp>~rMNs(UC`bgyBJeJM+U_^sOs}X`jQn3J+gHw50J?U+A?5ARRhAc
z21Ojd9KqwZA`cKrN^how!#s4^0n5)ALn{^5PiK5*jws~W+`*v2%0Fk>{jdsvoL4Jk
zHYlqyD@Db&0w0!K7Q*6e#-vYO$3%@w%am<s<V9XsPnchFtQnnQRAycOA;wVhMC$%4
zEDk5N0_m6AGtCThSGfZgM!<wG)h^0wBUg^)q%3%R`%V&i(g*H|$<1s5Fsbh+;ahW=
zQ5KK)g6ph6y(<WqX~~aSPR~@EeU8<Qanv84Z{LTmY>+1i6*HBb%t{bdt%p36!M&Hx
zKQc(3$X6n-gJ*_|rbxw)<fV6Wm_W{W11zFEHKhvyBjhxx7v6SLf(DIcU>APGP}47B
zlu>GpwL{j!xp3^{;nv6UFbN%nZP4w2M1xFuGu<`(Z6bHPIrUQ{o$gixBRUp?=cvD3
zrO~qxYFKn5oh&L0QORy14>cJ2Pe^QSf_RGs?@q)xi08_&Hb;Dr5j?L<14#;8SEXVd
zZhQE<R=+TkE;oE}r^(mc67y^Ps1dNf4YF{qD(;^fLa7-~$)21Po^1neu^X3ICY*ix
zP~F*Iey&gf<`&-L5l%0CWn6=gKb&*()DGQ&c^qQ>j5kvDf<8d7&)ZZ9yNlDh-b#Ze
zlM})tW#x}%igREros2*EK$c;tzY=(<|4Z2h3>AxBLUBS)@+caQB2D3evyq0{K`voy
ztp<Ry$mFm|Qa!QfpTP6|kEZxY+50`6Y#vc>!lo#jai@it;t{n@AO579x4-J>_4%2@
zpCF=>VZP^b8d~Tmg;BwGb3E|*=ww`m_0IgbbSL#8?E0$DYQ{s%SVE`rU3|l{oU!&3
zawspU$*^qwi@>-b?;(k6#y~d($x;;X?uffp#e!EQ14VOH{g(#s-tOMY15K;U|5WRt
ziIJCrj&xP}?L)|0gDONw;c~^6t=V(U`(eI`Ak2Ti(}}vvOL_Di8HODtzuAwTcSe0H
zF%!Uy$mMxC`%Fat2f7(wJP8zoy*Bu=UEme|JB$9_<PKAFmN|FtwyvEB^LibSR<2^B
z$;ftlkA;ZfEX-%jLl4g<bu0ntF_3XbNW7^!Vt2;2ELHjhL17Eh|FSLgE6Z{$Y693l
zpN$8qf^IaODo{v`hwoP3qr%CSGTr&-tsiNBM^D;M>sJks;-N-CreS(m<sUjgWv)!{
zAU?^RRmvD@6?<44l;D)fvqzQyT^&asJ9$}p6g~G?Kikb4Ak*#%HA{e_q-SN7sSQ+~
z4w_UmC~H*J7h4fw13!<C1^aF+OOh>Y#sW9JHf1lXkU5fe_kljk?z=Vru5CqG#mL=)
z$7W;7mRS<PEzm5T59ET)QL?H!zzdV2f!MfL;p}4)biVhqw26&Vyzsx6$ILUGidv7w
z!U_0`+q-&sF671^cgGkIW!dmyjumC+t3oR9*vnQhiv+sY)ziGvT>seNpUXU!3$qG{
zx4EHH-iy4N?&s#Y*brG#8y6b}K8tH?=-(S^>ky?nGqzL^m76(HSFa~GZSA=Do;0hz
z%`zVODT%Ij$_fxTnmKtT4i|xRq4?!_z53a(>+pUB1p0n{+q-ns(2%M!wD6mUPF^xM
z7UMo}2xk1sH<K&ucP$z7bxrzJ8@qdQPgd+=Ym2b0QKB*;%*H$c!yAc~vbWs2jkrvw
zy$Ez;JN|=!UTD>hG7t>#L*aH}3Z_IGJvFpu=zG}y&%e2arqHE#ySJ7*cB+p9Cs4mI
zTd1rm_L|~v&N)AFj<`&plyAPqOcn_<qg8d-p;TiEd&g6yr5sgv1hHawBdKl!bc}Al
zi`0ILL4t-&P)6$O!r##x9OmbTEo?XjDPM_EC~gJ$?p4;E5FQTW=iyVonjZv(id+a7
zKpV`WI$gd#l7&5<6a~x2n}s-3omj>yb75p-)E?TBd$@(@OjMa#xrwb|3*!g8lMohK
zIUpMQ8$&v#eW+ial1N86lty@=H#Ps#58?e%ga0Xv)=or_Xt{zmdND#Te*+Fms>IlW
zS+bU8SGUApnbW(~zt8`0o8XJBFbd*K3w`@$7i=LaY+uI5itUPaZ({!D`Y3^@tf{#N
zrfVZLU(&iMhr6O7U0P(qL(N7nP&TZ$+ZVj4$!5O53TpX4ZkWuCv;2eCgiBwai)*Ub
zVU|*0`5#s@oF~7a=SF6RBY<*I3VlV80w3H{*LFyurRpDo%z}k3Y3z!gW5leZbL<MW
z^{b13PxNK!3}(?L#)8p?N&@zQ(+3;$=+ki52UFCf9=%&M0$ihKH&`oTz^5z(7_*@}
zXvAyx!OmIDVYx>FryyBK>%c&U_S@6?)$ZzCxA-6!kl^Q0Hq~1qh+5h`l){%b_`698
za5*jJ52<j{PukbbTG9ER8Ts@a4+K#WjwBI05IBxWlgrY8ws*#Zp0V3o8PVeE7^y{q
zS0*kYQNb@Es6e|NK8O^nYtKf!$kcAT$n=Ez<x6U+Ts|PhxB)Mqa!-S7fEPUH91bON
z-QOtmaP4cat<PgicPL*xeYvv_ddN-N$e#Vm1}X$v_1lAO$SKk>MvmEG1cw8RI35kR
zy?q*-=Y5kDuHeS?FIo-LkhkWbEX_FnCd=Jf;LyU2iVZjgb|*R8>&n!1LdX&|9KJG@
zoJ0NMjw9((>&a^%=9PCv8^ilBA%iZwhFYsU(*aF&I5lYlij(9c_!V;t@D+s2y5Mc?
zVKFM{kTGJN#v8M{k;JhSM|-N8>-Ygp0VDo6@ka8gI6zWTWLf{!hW$@HxK*pDcqgsb
zHmGLxkKiVO#XO%Ss&qN{DxfHnEvizANMojrL93v7f^$OuH+!mJc!Fxg2?d2N)=Bwu
zZkL<d$m)lMehKOVJHbsMQBSCHXAsp*=_sO5UhyLbS6YdZSPRKr_Nin)96SoL|A#*G
zH$irP+2M$);4qZy^D-k;xmSEHov8UuLinxJF9}s%+TI{9jpWMT?3%4y6oX`s$rnK0
z8MTpyo5+x7L~lO1rNcU*joTA?yF~p92QMHHGGsB~THYaqB~p8LjeD_jNZLncpp<uA
zcr1XA7Whc!;7g#_<RS#Ru%!1Jf^KE_kc3zD;E-~14zTs+$CVR4s$1Deddkq#LR8bp
zygQ;1!%Pht-Y3Pvt)~6Sxh$m78Y?(!^P&chLFkeP^u!VbnTLD>Y=!`^HKTQkc;ZP@
zg$-1+kJuArsKYLj9}^x4J|4Fd9ahuiWp!8`JWmC^%~{}?cW!J^_&H|s@Awb(@m5*f
z`wbDbJZQcdvzCrl<=@t$Qz}o_`Xm+b>JuEU6N|<}moDRHDqsXNy^We*nfdk}moChj
z{7CvHyV1864W~9-f}y1rV^vH1Zb_zrK9lhw^N#_wS-M!q)y|uT+s8;i4?+jC1x6ma
z9N3G%N&R6?AL(T}=7Ne9%g$YLXb}k7F}6ZKznlCIQMfby>h>vsgj?<BFWXO}MWemD
z4@dOtA&ZY@l$?xgFRk&xo40*x+K&}hUh_9E^O=4^f_D+sM7aaf6buA6_%RA6^w)(k
zu0V)?tTM@d<pAv5wik`l#d%z)FpT--V=FOt$(%PEa-cE<D<UK}I85#VfP1s>ud524
zVpEy78+dvNb8Zp)WepiY)4KIuk!oL3x?v0lQ2fcZjA(!u;SBo}@nVS=8I4}*0aRoh
zhTly|LnqdTV~W(JtNst3Qa_qU!a+PWm9^pW{W_QudB_EtJqGI*HP9j;s!}8l`*Y-@
z1t^85xvO7+g_FlX2=A+3;ZI-e`;o|7wO~r0#i+G5dEm*nF<6j-kxWk}B(CKWOpi+G
zx3BE(abM$1sZw(VOo6L?7W%4bvz(2{N454hM6lVO<*dYeHl>X=2C2_Dfg^jVd-vxr
zbYpkRxvf~+aM1)B&*f7+;07g2Gp_>*twGd?B0j=ds-dPDe5P{^V(+bRP0OQkg%wh_
zZCnC2p*6)pVXfk8j}u#N;QpqkX6*#-$b~ntt{6zBX2rpe5I>m{Yx_@;q>+ikBtCDg
zI1MN92>urA^J(3t`7^%vL~PfXU+Am-B>^fH!{G8-=83>^g$nmO<@7wsH2YVY^D;B8
z2Vluvcyar#X?I2u(BHct8*UZLcPT~I_|FJVmL`GHL`d=T3W4$3j?jfq3eKCmRB1*2
z2w@A%pQX3^3J<0wkyuPHeMc=~*&YMwwDu{`(?T?m?gKA=8cgmju8cX>wRB(2ccA78
z7KN#N$2c@F&i0xUTnl<d6a5JK_MB!Sk34tNZ~<r!OLE=r?ZEH7M-$pgMg7yKB6z`5
z!^6WT<ig)F8a7OzJ7KS#4hwYD1kP8$Jhf_8fDu~N&G;>9+GxG9wAkljEyKua;q0tB
zC4&zgRmB*^a-Ya7g-3)-ytCWw+U!GgT`)=HtF&9%;P<PU0}CQe;1L;+=E6B9#~FYF
z=2kQeOu0t&cnoJZqDQEAn<&}H+Th3zKsC~{LB3i_WX8!HEY()ZlQS4sPv%by@Wypi
z=yr)!L<5u-mPvPE7!#FR)_{0;LCEXHwKG1Bul5Rk9lc5lj|$ob8v?VlE#mm>*_K#Z
zR;AzfQ^bW6OwEF+;+s=i+dkID0Ruc7MjUrWo5fgLT#Vy-X)1miwugw_U~{-}G7s62
z`@h#;t0M@#7W688<`Z4vt>-KV%1s-7bgWH61Xhk9+wBIDhz&9a1lsbXK{xlKZU;f$
zXuD5WfyG22O~5T)MqYrDdwNxGXdK-lGUMt)*96(J;^c(oQxth;9>(`gq-XbT3QivR
zXf>|<6>ND=5_$<WR5brZUSY&54Bc#R#6y+vGG-1tuR_AOQ}g6rlpbT_A~tQ9*9<H1
ztKA=x@lZ+@d+M^C@EWjvQd9Uwdu?(#;ukCNsJqU7qJP7Hh3~#s9oZ)Yg7W!hdq)Ko
z($)F(Z>)Rxir9h>E`JJ%?NBP;gwVGy2L)+sb`QT=NKn&mjMW2d0oTN@s8!&3xr$)F
zRqV9ZxUS7&DYSO>&z%p?TOV(C*UUE?!1~@Rq_Rpax8<CgVsamT#PkKo?i;N@x>Xj&
zkCGHf_tVu^Rt`5lq}J*jvj?)|bQ{CLW<gAeOXaN)#(B=9V4q=WoPZ!&6f|>O2bHc{
zUWHWdQF^CXK4c_gNr22xKW?OnFXltM&CQo)cDcM9zHSOGW?!-AK`YaQ2vWj(_&GXg
zSJR`3^aoiS*H858atYZ%8%9OVZZGtrY<rhiT=#w?hL(kru^ht*#k=5_+I9>pfV)}k
z&97s#ssMov&OXWANO5WTF|Oj8`30VORg|_N%`B+<5%<8VdUm5nof+;m$bGxZE_s2U
zo|EVq&RYBd*({haL~mZGC;SMPpOPKYd1mFrWdoi_=WR^o9Gb8cDj2b%K49RVnjiln
zW<A-Pg9QPkX@;-BBQ&Sj4Xzj~&{HPD&9Ybanu~O($~(n5&{3m_5%P@JB=n7Ym-tOS
z+;Et33Jof1e)B*>CFTcj!&Q-m8?f!49aIhZ(?5?tuVlzhGs<w+@rX{$(U1pk5y0yN
z4u<|YMbU2@@K1%-Zh`Y&ey^ILMAFm5zjq!Na#)~;FE`-x*-|J~8)9;o&R;r5Eyy{|
zDR&A9z}JrDpmIdUXUUYhl<uJY9C9M)e>dPc<tTX=)l?xz4-$?^pDph<)X}^{EVPWf
z$Onq3RvLooo&6CS-E#Jh^Z+#$Mx*F{7%rg0lXT{zXb*LJANCwcwNGQdTLHW)l!mPf
z_nw^DI?DrmCo@o2Nyx5RNvM2ZUO#9Qa;dq1<~}yt?YI~_shTolz18`c8wedpVO=)7
zy$6;vr2IX9MWEUG1KU6l2DPPXQe6tg;|arrF0q5`xistvrJ7~vd(Oo7?FkAb23&(Y
zX1MsarfE$EHD-EW@G?QccN4B#2gf`BvAaPp1UV@{D9e$4eaYd^B<%<qE{~7~d=)BM
zaz|$mb=?7JUeb^1DA0m3F+_(}B90SmGv-8MVb1`6-dtIitdtf?)&-y}NFs5g`fK6r
zvx~3rSISkwCH_fXa~n9mkOJ(3ebx(=gTb3nGr>{{MI`Qx8R`V|qHuE@5mZ#oJLOG*
zaj2`N{V1NeUzEdS7djF@IBZA$GcX$~L;vavY6?%cf{u60Mb{q|mzPoR7R309XHvqk
zZT$)fTtikFYJ;IPQ#vX+ASwfm4>>NOnzXnyWOfz*jr5V?c|BN@j<52!P4VyEcKyRv
zRYBxolQvPS%U|bg*C1HI#2oc!Gi;Bu>a=F#sCuO^K$cu5EKLAGD=tO6Iofy#U8z|c
zrYk=X_Mb3HUIX?f^)ij}mo_;B^4sDBpX;eqz?<{;t<#m|f5eS`stOqh{FW%A=Q<S0
z{T}3lQPLU)*E|>)e|I05ysH4=>%^elcFY1A{wxP-2DFwfCVsKSL3z51)VCg)Ps?PF
zSsAVHOkcmc<>rlFD*7{;Axr~0k<|FJ5Di_@zJKt&`Y$jRfdeJf;F{vdLcugrP4t@b
zR^xWBaV>zV+FKzIH)40YX!{kEE@zdbu<PEHZ6AH{{en#+uT7-AeZl}IkH<H$`u+c!
z^5ivl8f~IVu-eXyT=v<E0J7tynF3D9wXO!vmR%g(qV1UIKJ%mqooho$zJol~Fz%~E
z@w_Q0`#jJ$oTH{}ur%7t96zkObB-dYl_J#-ErO=MtkSAdL{_$umk=ku8VTb$SK(G}
zSXruWl)(2iAIV2Skg3#oZS^`lERw&{@|nvdChXxe)B%1a*nN;1x!5RU0dIB$Kag==
z(bC8A;!_&%4zEmg;_&Mvg(OlrWd0RLioQl-{jk8eJJ*M5i`XrMI8+>NJsEclU!|b2
z4=l_s22GM1fxk`#aUeld65Co{s2<Uq$DJE0$0nth76}cH9!dD(y6+N{06?Y=>?hPF
zgW7#sz?BDn^(_kk<)_W}n*X0?QHP3=^e@5ebQuFgGcZTBOx#d=ipd1FG8pQS-L|La
znxbkTj(Q7%7~3R&0$Yn9_(O_XQAGjHw2#O9hH|+E$}usZLZZAvIhK0UweC?pw6L^N
zKCo8Q%NYHINg3U1Z9(vPE?=uz`{-D=i8l)md@(X44x~GQ?Kxr#3`53Rbci+Yr{*|R
zS<VQC6~y26!>~CHt6)&Q=58RbkCh1?HyW>Iv<rX6E|vu!wRm#D3cU5h;3(3yd&=||
zC!pnLCL{HvrD=)rSEaTlY3C_n(h|a%p-6ydxR!ZgjFIy@r7%b?A~rRoGSX7y<lta&
z%CLj$;ue`vKy+SqqY?qno*9d(?8^X)wfQDZ`m}LB&J2d(U8|M_O_<+_jKzsrz+^F>
zH|bp5U`7F%0W;o){SN{{VU;fCoj~qmoLa@n*o+!XMVtX4x{=jH!Juj*EUXuWbR>$X
z#2-0<4u{)nJ!iD>#iy(?A<L%cWsilR1vh6XefF^g^b^L-h$H|Tz~?~xh{&u0z=uJ>
zYbXjG0`h>!_ZqxmdKk_J_K>FQ$V-4eL43F1(arJQ4+d#E_3+BtSM|J3_bKL~091Hu
zzpNdIosbu5xNz=gBfJ^Lr*wKsi>_A{%%OTLlNJ2RW4#t66MnyOBj;)nehh^mxxkO{
zr>FWajlGK95gNM`>+T{P=?wQ4Qu1h9?vL~go@BJXOK#l$CIAMWd0EJxUf>0$k3}Rm
zx`JS)I_LkCk)1P(e`ClL$8Oq1d*&0|lVhUo=#T?g%XiPNe0J0QRfbRz4dFyg$&q%H
zs3rH?Sm$khjE4RS&smV)$^_HMx;yX!et^F5)m&jwUL*#2@qM={iD>@LDVWNxKOqFm
zL$w(4t$NwqE2zn9WZieDnI3)1!Bb3E_M;=2W7|@axDWsJ+YnMS9}$V~O{=cLrV%w2
zHHTNrUl4zjW4Tb3MPnv=Z;`vmblXo6B6QLH`?z!cljz{hQ$fjKe1m@Kt#nC_`_8bk
z3YjX7)ceFcI?^(jgy!LF_p87s{)yw_@7ub_<izf#9d(Td{a30R5<;1x^OhwX=PPU)
z6ZMeiG`H=UCm<kAVMd*jr6md$i|4+0RZe2*?G1x2JGX#}+WkIBu3+|7UbU0h%)42C
zQA(#MDtL|J?rM-8!*Drq7nGn7H=F|qL{G9KDhB3^ok=M;8;H*wPC}Z_6aj<zi#e~Q
zGVLlaRzgGV#9?SfRgCQYeLDyK+KzUQ+jdb+=2!4W+V#1phq3e!{1?yXe_0bs(WalY
z$_PibIx1FC6D1*lgxQ#LULo&*n)M3ly{#PmLAr_kGFN!bGsb_BlN783R|Mbbe*VH3
zpMyQ3e+m;M3(C;G%pjg{FF+@LSvtk{2V*TO{s>sz08t2@qysDpnTUsB?eTWR%6B=S
zB%TAfj#thq5*APOzduD@$G^arSGHSPxnD9J5N7F?GPj0#L8^omOhHB9>ifSL*yT2r
zPx&wsNs`KSQ`|0%m^=~k6mQ+>iP8w7qXsJQ#b_KY2W(-YM1HvoRo$O?*qPmDrb-w<
zRjmPq6!Vxgc)DQRggx79=)5!815*4hV_=swQdD#~6$s~`>1z~m1XbjyBMOsV(fo}`
zccJoi-tZrel?H*##3=G?8vCvApz)t@J_0B>3Io44c1Rw92*W18Mqn+hP8?*)DE>_n
z=Dhd&H<)t_V#jySWN~U8s@U`RPn67lyW5UwyM4R-=({43=~enR$!iuG4|?JVf5mhV
zBK{;23EV}C+2drw;+iA0VOjQQqrDk)=hg10oH?n<N!FkiIHvU(=cu$wANpS8=c<M_
z`g8gA+tazauw!R;&ykqtkB>Rvnv})YyYnm^ru06uTk6hM`sOC4cSAADWi*CVh}rZs
zMzxkoj1@OB^$XLbPhvbG&9SFL_|_utIH`<&w^&{!@<G6=)fUh46Pbguc&0py6y8C2
zJE=kp549Z;@lZCu*CuWnftT6#3saFDcTY)uNollr7spyM*uyl@63}cYA8gkeWa66Y
zt++!ussh!;MJ9*JX1ek@U{B^{GrFQlE~m?;7C*fnh*flFq4oN(j(P9XJRG(CS-03Z
z7}m+VaPjpQDAZ;wvlnaf-Kt%~vj#tEl#VRr&pNd+J6Hky7T$d;AQ{_5@M)Uw{5T`4
z9D<|8g_&du+FaS1vT)Vk6-5ci?asA~7-lS>t259nLUyF#;E1jU#J3`~o4rB5Bu3y0
zM#Pc&x-JmkMO@Y9=fXh(pEY=^Y|o$Kj!zwICS}<A+^Ke}IQnv$1}S~01V~iOQINLj
z<!TDgPUh7-Qvv^olL^C%kU~?Cisnv7;Yr4==3?_pb^3<=g!+7aph5w3ea87)7j%`E
ztt;2rXiexQXtx6aUk@n0^79XGSbWRW?Lr^5?NocBb*d><2Vg}XRA0a%2RlW$nBS5t
zowdS{6JhJ1oEabac|JZtKj<&-N83#dn+qxD4k{VaP4#e-Mw(z}xC7b&c@`<}lR>o%
zrEi+tME;8@U&nvc>xfl0fqvjLwa%aCVv|J(*EWoP<I2%@0PW*1j$0g=Ss>RbMa_J_
zI&KdCd@vjU|M^VqYWWH&&)?^qxU%=#nP-bz>auo<UI7MOz?NEkyv*n&e_VkTQ(UfT
zTbliGN(|!F)H#y8{nvqCRiKkJ47&JW`aJqjTRqb;TvLfiTSUJ>8=1fJa-^x?{?&2B
zRXyY_jA>f82>|e}w~V%Brhb(;Vs9C8h7)%v$~lru#=0-(kCi}zsXw6y`b1Tf<%kv>
zIL<%S(X0-}6hXi6`rGu#c9`#%A)Rp%(LofD0Pw#g<|vR?4Vq6USx%jx(u)0*lTEoM
zAA>;F9mt1mS3mpK5_uWEn$2MhV;QYP&R=modp_#n02-A5XlA~ag{Fv_Lg7`uruFR|
zBbrh&2LaOKdiU}91zCzfBofC>24$skbc%-9xf4Dtu}@Bn&WOYVm!hlhi{+%%Yyoq+
z2+Pv|5~8#=IqAkvv)Rje3yj~3H_Eb50_NfS%U4h^o(r4DRbX_OTiLQd2CQ0e?wc#P
zaAZy3^QEXWR~yD$fs!l|<$<UEsLJO4oOn|z(sR*oxydk+PG^ov81`1~6be@n-N>Kg
zhA!M2de;Av;>9dL+B=jqy)AH#suR=0^IKBhkvKVsN0&mCi8Klg(9!PnHRykLjistq
zJ<!b0VK*&?X6$YXU~itu(7ca2miIf#o}N&FgcM#ETP(2IFFp^;Tc`-q5Eq|X#HIN!
zR|*1RqDjap@rx3!Q5CWj%_mclenCS)t8QU{vSlfN>v&~=?pq*7e-E%O!S?*2CHf){
z#EK{{8m;B)8A$xV{tYk(Oqa^E=iRW0QlluEK`3d88Y0XHl!Jnb+zht3Sf)v341QR`
z{8i$owcdJ#UqItEwr7V5%9%p(u>GZiPo<bt{0bi-reENSjnq2C&WrbD4mYTdui;F3
zm%dRP1&FT)%6&fQb8Tmiu~g^gG*&Cl9a{74?_;s`liQrit%K}sck&<g%jXrrD#=N&
z*Ae!f3_KG)taozRk((H5|0drzNM>ew6&L%8nFPkZK(9yWO|-*s+q=&R<45MukxNy&
z5bc&?ugp>|{As+(`VF{yMA1%Ok<zrrQkJ=}09ci^=(bIjSX1S01h4ylafrAgy|T{}
zX>t7NLjT~K-LH$ul>@;57;_YcK_h&E-qJ@OYOZXLj?<cip-pm2b5lq>t=1G&iFlvn
zfat)y%IQf_l~Q`ulL(LKFS+pIbuk`nq+QLT^r+*YC_RqJhYc+uL^LXwOVSq$lCFp}
z%f=NcC>QWW4N3s6L(IyimzB{6_`(Y<n9vS@Znjzp^x<O5VoKRp9^GXgyvqnK#Y6_3
z)_UqoL0v_C#ZO5>E8{$k2@YF|DX<PcddJ=45l5}TfEB`KSzf7Fbwe{T(xnvn)=zbK
zXd;GOPn&RTOqyh|yMn}IJ*b3;;C1{bm5o;J6@EUC0jedpy?du!OuIloD3YHC!jV@Y
zmNU}@Q{SOpinTMTHNTlprHB>_THk?-5tJcPrlX3qa>Xl8mNo%R5SCbrc){x3eh%vP
zJyGt9`whL+nk|zm2tP=elvoBGKVjjE8V+2Q@z?N{uysK#TGv=z3O?RK<h-4urzAtb
zxkpfyQ(4^4>o1{hv%>MPug8^N_cdQ-UPoTU$=`LcdnqArm06jvN)wJTQlrqFQCDqN
zyC#{i9>@@H{#UpA?7$gIg7CuJoeDpue0q8@dnE3*?&oERH1dv=jK~JBXm=!8S5gB~
z8Xdcyk}X86sG_=XpDho{Ij}!S_5w|ixfgE?LuX~#ctFolP|PX{D6=<15He}NiF>uC
zXa~eZi1<4NgO%n~A~<)7K6v5H!p+DCCe=_IKuc^jFOd1)W_|}CqE11j{eDPN209|$
zA)%a<u|cRtSndrjund{GK9(JbWa)#h9yW<h9jO_!+OlIIu)M$UGHkzaHR4&kJ0=N7
z)~z>B_%oPUZG1hU0V2!wp00YUsZyzVr;kY^dbeBT$r&^C4c*-$g(@s(S!`A%qSwfg
zJT!NE!g3{1LI#h95824YvFT<0MWu{Qn`qy=YN)Uq3~a?aXoGt$+U8(UCA`SdZhdDd
z)*aG?s2o`43l=t`gWIz3=xq`i^Z1YDB%eFral4;HIVIuEPcr+kXC*3?AkZ5{P5o7*
z&c!z#VQGCqrZg!<?%lT`1eaDDauN;Z9{qf#^43T#NJshvXdjky%FIon47&gZj+AV!
z1kSuyAP5o>EdbVlkpbu06-qNt&3=jt0jn-l(WAKCkM5U$=Oqaq;maLsO7A@$PD_Mc
zMFVC><SxpU?jFYgsPZ)QdZqHhrG{M2)345ka4sJD9!K0uiMzf)SYbKFbN(Wd&Ke6V
zsA*c6rnn^*g1HAYYX@p&1EP`vTa2I^cM|5VlV<}jwna(klH-;qdy%wkIzbNjFA`Fi
z_ZZd$M0e&*pOTb3r)22H769nVzh!S#W1i%-1;xkK2hPH~>f5Kd$lNMcs=Mx;G8v{!
z^6HR-&ee5#m^SgK@}q}qY?f+6gg=VshTI>h;I9_H8Qg%}BEc?lgQ0{bcS914Cn3g$
z_fwkg+W35fNS0UBieOZ*ZoF(T03)H#<0as1s*&f><e2EAH+In-s;FO%Efbd6!<Bvh
z85K;5SX`M)^<feEL1GC!<Js(CfWpmn-Et!lJ>=kpbjK6mJdk1i_d|Kgrko~j`UlCp
z28lX#KbcUEJ=b-_)T&}a?>v~SmH&H&PJIT`aRbparB+0KwW{^&HWyK2`2FuEGc148
z91;Y~zM+**6daV+x(92D2gcLc>vd{I43alX8$6HI{I>^{q`&zTf;!=6j;y>_%<T=S
zNy6I=^>C}(sK`w23w+!cKd2%GT&O_uT(n079-T39`9^6@!Aoz%SDj&G)Vy6=E1C<3
zp}Oxd=8>~H4zi36Q(PX}&S$yG*Bi{Fz4!GxZ8Tv;Z7@FT*u?W4b7)0iCSH?~dpy)w
zu`F7H_i0Pj$eKpnz)l-zvyS<cf^A4R?9sxB<!WvTKHo$lW-K}#G;BjDVlfWuhEomF
z)IPlJ)Uevv)V#u)bB#w!gj-YGQekZ|Z*PyoenN1kM|QeCot$Y+x_>!ctB3K-UqBlY
zUhbvY4edUMLj0aO@;8Oyo&%_jn8qoawtB1OFribn(Byk)pF&KPYD+4+S^ut=EyG2;
zvlMldm-h|*NaOU3CDGP6&r;vPAcpMfU2eW9-4y<_KH4O|bq7R`PkC`lZ>pLkB22w)
z=181(-yHcR)~nt_ijk@zmB0*7hz`)((0_Vg(n|n-8c%!CGE(dsaVdjLlE|Vw>I)9M
zcy@R;%{L?b98{m{%)-eeDO}iSj0^qcD{Z6gslG=b@eqOY*=a$qM1PqInHTl}^T{E%
zo)QLbcM7IBTp$Vi@9_52RND4cmo^TKRh%oQL+m&od>l5uPEExVeGA<8%Mwq%dOB#4
ziP<~}fi>>MZ6rY9Rs$QDSF8|)Y3oo|p|WKBMDi<pi&nbU&uwb9!QOq9AfMo*%;nL>
zc@qj&<RbbhSFSS`FiARxqKb-e(6+>M`m%41FXAn{PNxJvqHXky0s=u%)1el%rHJGd
zbdMLCKU5#+0Vjs|n%d^0=*e@pv0?~sqn^D1Ps)+6-5U4_=*x}cmny8`uI;qZrtg2S
z$89GNb^3T=^c4z3zdf=S(F#}(azSgirX;VB$jpl`XdBgTg=jy3A;;xuPyI&tdvIIQ
zx2k8BgEzqJh7ivgakJR82j2SS3qy7f>D0hayiHu>9|E=cwT681)g6m~4u=Hi0^!QS
zGnJlAkbOE!Ik5E=ucSXC{HZklZ0NE>K7@gpk+P^Vp}c(YSHs7BVF#%$3~;%k@e-UJ
zkb!^?NKGrbT}rZyLcq#{-fcGBX(aIQ<x<0xp4Tj}wlw-ar4f+XU`;%{^|Lj|_<o8`
z!Uyq9=Bb>MNSf2Hz1@ZNm9$z)J*wA#s>UbJH>>Rc-f!}s?;H!H>i`1hBZ)yg9LbwT
z;>ssCGu^imZj1PUrFf>9-?aoVy;~$*nD(2cCbPmiQE*1c^#v=p6Ct`;<%deqO2NhE
zBy2+Xp!~)h_C`QKXCo_hOlru+8NYI~EE&rc;zsI}b+>n+SbIhrJD>cJep^s%ZYfn(
z*ktYnyu>znmnVu^<HBQyI|w=vFcx)8NiDDOPuu$U*EpEHWUqU)_5zZ)mqfb&me4*{
zO34|EI}Dn1q*`g#8Ehjqfz1{({L$qn@87Am?QvJxc78qwA?ez7{I;8Z!xw%2iZvcM
z;W_|m8dv9QzNC;>i<A1{#{Khw%&}_Y8M5a?aF;;F_MH0e1L!I`w=3Fbq=8t$uZ&9b
ztn~C>XcGgN40ckr$J865A8yqhQ5_$Nu2YtJ7v*a&JgHa(h(v7DvrWcBtnft_y--Pc
zMISk=&)J<CThTl|jug!!5auPkG%U8ga92&Y*z`RK3`g^S0n-l4W&ZP$D9>s@%mtj~
zOJ-Y5ak986{jMK8Q7{Gl6%>==FSe%DHxItNOm%LSh`f$_>QN230^~WrUIvE(s7WhS
z*1K#&MKDD}RKkwnTY3zG^d%xxdm6rA+wF9Adrk|21Rz4b9{`W6?O&TQ71$+}KizFE
zcRzS3ia7$KBg|WMtf+Y;s_7KR2$GIi40vBVVJ^0JiXhun9p_T~jwkVW2g3`N_*n8^
zL1=ky?-X@@VG2<JNxc|059szSzt3O*!lQpK0-`1vRPw}h*Z-y5YZ2;(0}TEgb7?VH
ze9p{If+BwyeHp1p|D+n-EN47~0I@r}H2h}c*p=4sDDi(VG@}bZ!YLsY6@E51Ray5L
zIdWWy%|R5IJPPVggOHeV%vJTzuak}tFPO`+SQ&dx5z=F@)1Ui&0)IT8k|N?FfcX{X
zLfzxu7XCIzGW}oknc=H7<7R@Lw28VuDoogJcvJFxhX>#=m2&F3ZEmXq$^^M~TXP*V
zHe$gZIA8HlwXM{I4<R}1QQuEo0ig|X8^%SpMFf})RTs4C2&irTfWcgV-GV_vG&RF}
zoz_4c(gk-1c3d7()L94r<@hieNP6C6IOhoGDhst7PkQnaIQ2w09DN$kh{q*WyXyks
zcLE`M?V$88{@}T4mFP^MItRF#Soi1p*_LL_rsRy7aWF+a{O|5n*Pqj9^FV>G^;Hz8
zbn~Fk|G4ZbkT}51So8E@eyQm&RTADQrfaD07`th0CKjFZSEE806DtTv`oHK&ZW9pf
zwneb5W|j$vWf_S(eCB9Cs~X)%Kt$+l4}7Io-z2sUZ2aij0uHpl)C|7+opd-|Kx!9)
zylqZ*hTBPJapI$>$5Q-A2=10LTtPI=sU6!^i(0WMtHf<4%4htTXk-0!H*%o84r}6e
zusk@vv{*YoR^$??-F`1#jsmgE+zmlGG5_u$Et3A_UgeyhxhS8^!9%T8a>5YBn()y!
zyhy__o;2RK-%nrQX%Gr{idx}RjC78g*xER`9*8n<6<#PWy>+bm>Eur2{ty@rl1_>Y
zP@x(9_A=D4FTs4q(S3SM><X94S`+t5o?dR-vi^dmQZ<|>bTyqyW1i%3L{|nOk`EVq
z2tr(EBr4ZGPt}nD!VzG;2b6ny24Dhk=c{1Z1{Da#x`j6+;0>sqREH6)U7)X$KD@8{
zKgz}6?JfO%#tIMA=W5mlUXk-6#v|@{4`RCmzWaJ!e)oVjpH+xGy=J-cMQ&8J6Dl!m
z;kS*_wA%KTVVUzbF_~aJd$AN3LgbxQr|<rAwhiY|?%|sM5a-8YBJIez*+BOfG&V)t
zBp77AP7$8pZb$d`NYWM@rG)G@We|zk91oJ;6i0hZF&iueELZ<6r5g>yJ*xW4I}GKL
z2B@|YTa7}R;CVkkLtw=weW@c(MFs)T^||_qgA_;Gs`8D4Nr1Ndo4pq`cE2rFwu4Q5
zr!pdekr7U>yi}_H8`FiR0Uv6nkXJ=pD2>pX{0155<H`R#R!;|tB}~q<mYO?>{zZPC
z?AQZa`&i1S7bX6w@x^<=W-k%p&c5$1_BEy$Z%e=j&a4uESRkM!ji~7zM&X)YD(h&&
z^AD4{8leTIy_ES?esIx<YJ$8IuFv@94qdiffrDYoZhIt=(r$5=Z+H@oNf`k3<mnDy
zSf<c`tCXHQ_qnTfPZPZI6Gh2dFKxk%{z=OBrl*e~4+e|x#0w+zLU%?D@$#o6NQ%8e
zPzT4vy@1Bdj1SolI}kR3hxnS->NaHtRjP{G8Pd6NxZoTAJH6cffghsxr!{0@4g^T(
z5ovPfCB&7P3B-83NnNj{H+Tn>whD9MF7W4T3>H=_%bIujWcF(u=TIR^{F()8%<9@F
zHggCB<9iehcPQ+#kL%k4s<L3+Ew9qMEoIB)68s+4&REKloFD})l#zlM6VA0b#yrI9
zgY7#3NEod<8L!8@Ypcr(G(v?GXMaKCfx(p4?sgd>+p%6VVeLf_#94;&bUGF~_n2}t
zhAKh{5mR!RdV9@tQ}GJ{OT}X$+0AEyXb`$q{zK$aGgk}ntEi-bpxMPVNp~;802db_
zPZCa0)IWuJ`v<vwJ`5L;Q8=4r(%K#8&CvpWOOhFQ#Wjh(CFdk9du_V=*_1sY=e}?+
zvpkE?Z^M)-LmK=$J6pMuFAU{K2@={@>njLyZMY{6X;zz#9J_d$$v*pN`dn9Lsh=P_
zjy{J`T1w>7XBD%<rcFK!kL|~L`sTktS#=(ZD@3k_y}Lvqs6y$aSOpM!l!O%Y2jk7G
zuL}7@cfj(t&KK5e5bNKc^cUwqX-%&}#L3e=gGmkjFZS~}%uM;53sHnZ$qprUucQAp
zF&QRl9_j6r@joEmFH)+SEowWoq_j2Zc}_uR>O2)Z#KKEPT{00j;th!arK-+w7+n17
z;1W%`U_Z|6?AZY+zQU5y1I1orneOfvZ5o(TdURj1g%wmvx<P>{hJ}rTiYnEwLz+#;
z03H6yRz4FS%sM04A>X_Zauyi`M*NO*y!i{t*rTHIL}Jh>t%JiFEVRqbO26LT|7NJl
zK;v)V@XZpqo#`Z-JxNVOrH8$lQ6w7@KpQ}rTaY!)^h#v*SUIR~Gbi-sF;~ILAL5Su
z?g@{Q0jW?{p7Nb4XKy|G3w&wXdwY&}3}sNnlsW*YH-Vsg>ZVdGTZK?yIn)Ie3-)$q
z!qCl%sNz=fdJ@%e)k}2H&!Hl-4&~WTO|?3_8RQJ*7h+;eM+eEaGwrmoNa{f{IRXDC
z2`z44pn#8`cKA*;QZd*Tv#1$hjw>%zc<_@PqF5BK)&OQui!5D+gd5jJQWT{UnxRLX
zl}=qpbW}N$>Xa7eZB&GG^}LAd1vLVaU2iqDJ{0PRgoER_uuiPk?*C0X+&;RfA|myX
z^;V*uiVT&vyr6#zwm-4G>*QS&BbsZMQlm*!a~ABmZyTq9sqM#~=7h6`BNfd`#n+?-
z<#+M_8m6-%wBvcdaK<0mYf$?hgQ)w|d086CD@<YuZo>=!X}MJ^DMFYUzX?@DaO_T1
z{AqP=Q2-T>kof8y##$`hJ4muh0sSqUbE^02G3F=nt{maHKpeStlH&wjLl7T~iJ<Ni
zCHIN<XDyri9er4jo`}z8U>Wgc4|9Nv?4|>50<>$0%fOEt0_MOdbhkv@^<*asuT^~i
zR1t;{K|kN0fTBrORsU1$&R)*1J%>{W#~ON18+%?^BIaF%DgTV>6v%@RO?mR5V-q1+
z?bukJN(w9sX^Hsspn`es$3z{7GoGv*9^t)kXgm=D0G%_&qfcng_a=D6(4G_E0k2Lc
z0N-hP_!k$|;S<0e6{8SVnMHq`#Db*W%cm$cC^Ja*JS_Wo8GGD)rld(J(u_V)(raLg
z%QIacJSG<XvGBy+7Bf;8-H6*b6k2c%eaqxx_L~xL8*2p1UEkV~4&k^Ov<XD}#4u-D
z{&f=KU(%Dr`g8yWseWyecLeZBN^KZgfohR~2+6-hpzB~DSgGU_c*@E?s}(hHxuXUv
zkv;UkacJHBpe(gR+uA7hCkwM3S^YNYT?mM%?OPUlxJMa3#2n*A-3~OHH;tesp@(F<
zU^Cme{ngqkmniS<t-6}g;$T`OWB|Bsir&i)_;T9kfGptVJB)4jFw4$Pp28I!oAv&D
zQ%8%uZ@QcKr_ri1N3^#_7^Wn(fDeGz{j^u=qtKlrp27@d9)><f&Z}>nfU)=~HJI*2
zhD;?{<n~kAmLd+_bf%@6JHp6qI!$djJ|G1*+vm+iOGAfAc?IV&UWR_1q1jLtON++B
z<gUkz^q{7^zDQExJ|+RO)Qe~`v)iyo>)Mg=Ruo&)5opK=>GtsfJqUrbenF=hT^=tX
z(I8_Io#Z!~uC($<`r;#3*J~`YP$pS6o>i-FhddW0k~X!}nnqH9o5Hb)4Q<J2?hivA
z(5hF>`5m^<#EUZk`wow#RQfG;yI7^#j+9Vp0H`*Udn>{qQf``M)e0F+mw<wD+XtzE
zmJ}#1(Cq!%ZibWR;2ybK4c>{Qf_YujHFbwPF4leklwtc%@Ntl%;;~itP(`cfi>cDx
zfYY2+c!*ZszOj#Uui>Nax~8}rV){_}k^AD8Q9{m7tVBA{3|es==HfmHAO~d~r>CGQ
zBzG3u3VvAJO`f$WCC|R@et>dUb3xA)q<>8YIF%AY`ho-gd^l)H3&JY5#%)GJ<$RR$
zEUAk7(r`Y*<igwflw$ja!#>A&%~%BDPc_GKamg>a9h0Hi59a!_i>b}COF2I1*9S+*
z8EzmY4j*)gY_>2e!Rq59cFSJ=8$7g~c}e|B)Oux<6NHF&uvfLKUoA2yc4GsQGn}?0
zipnsE+6V<Z?z?-DG3~?+HH7#I57Szi;Z~&@*>r=EK^8++!|5jVT#OfXWn~sK%vk@2
zU?exuSCV&;08B+J=yn3%tLsBT6QL`WpJ{R1A}(A13i2oixSg1Rlc<r-#CmoJv!K2&
z@flGveq5apK&MPgxf4nA9v<fdR%Aun`bViQg3hiQ3P>he`=lN-H*vHxgdokxpCEBu
zwag=S*kVOwNd&UIj`qS~Z~GFvD((!L-!I$HWg6KW@7LHhR#~^zv2K#1cc1nu=q2<m
zQmJb(e0=}zzmamhxEK^)5E={<xi=)hNCZlOen3&D);IJs;MgaF4N|oO{;?qVMg2SW
z#I6SR@9ud360Nvy%eFI<g;H5HU2sen`2b#t%mX!Ar9dh$W<`rQx)+cDz^fLn#zfj?
ze*&$fA>Z83hIfrh&!riMZJ#o!y;UFYuJRaJ!Ag(RAn&b<u08+vMUZeSv()w~t%?x(
z7yV-^0U?pA86|GF500-<66bap_d>6`9u!-BxC-w?cR^Z`Kaz~uUP`(2<F^TgP;Ovs
z>EUDpzF-0!t#-^*Yz_L^F`~$`S~Z*EqP*)F-6gDeMw%g;lJZBy;zfstA*lT|b`;f7
zzk%vobWcfB<!}l_(yhG@v06p`RAS~a28LM>QF`{cX)AAOXloL`_W|*Vz*y!?q-;=7
zxY0@cAJL#qsJ!dv<#BA<6Non+Ij`1c%3<_9eDpQYB0YnzqSLI6Q0MTJTZ~jB_h@L9
zwWmUeNf=z-g`!JVV9@JmA1G~jacn*zOh8g1>W{b^h7&n~>pg3cI-h;F!tewaq2oQ?
z?vtwq{-aP0gu}OfM(}vHAW+vV?h!mpu6UP|4D?}1LKr2}B>=oanSUd09}SWoLEP?L
zbBo!hcmxp1X@Wj4y2hXl392TcO>3wURg@M^<NA+<B$EHj)kFvmfcZdgurFGYFbw8l
z^pggNlZG=B{C$fgBjv=}+(IW+PUOXTEsNw)6EY-&KME{44*%b$R17YR=W=8Av$uO*
z5^WRwg3Lbbw)3%LBi0M~z6sw(5XM<D7+OxrV^Yb84e~)ix8elcAE#tDr4f|x%PMf}
zv|j&Q6ieDW)LXzK)Xdpfqkl~*T=R?R9`ir+n!U~3PBUh2<%x5{=r;H;iyK7N_$hGX
z)?gb37XX2=;LY$3=Xac8X1uTwg*g;A5$4aMK;SkKupybqJskRaLwqPWtZmB5x^Yc$
z15v4I4_9=?h_(%J1xS7xsC1cxn4jNIDN5<vIecLIhOTP_=%hZGg>d5qHqzg$MorjA
z{}&RZ%><Q$)BE*%LIS>G#XFsrJF+mszVI3gn!d%l`b;QeX+cdMKb+@UK0$~~Xb7;C
z2rgb-DfW11I@PG&6{gWWKd)FeGa0%bwDoWgFK8-yq9T@TxJ+|Mmp+{*P-DMABF8be
zAL&@9Kq^e=1x7D~DzJ9{VwSm4^2?Q)f&!Wv_Ry>Wse*uQmkKM@+Gc87<7cY{L%l?+
z|10OJOv_gdKGG<gB)9DMx+4s%QMT1o=PSH&EcW><R5$=K>y(Md58g)%X1%NEAKeV7
z`I#JION`<~Va_wlwkddYR-g4ToD2JX(r+C<wQ&Y1OE*!a<<(^}3CObb@rEyG7f<>O
z=tAU}zF<2aYbeHTzh!&N^`=5B@&Zl`PU)j>Y$39`iqUNwbVjZ7mUw-U>eCWEQ(yMF
zy1Vutj6DC&gf4q^=I4f`Le)UDmP5lx_GLzMXWy-#5m}++D!u{PP&UTokfu461|zCh
zeg|Js2eV$0*uwPI+o{jf<130^Kvw-PNv`cL1ngqWBR-|KTVy$>tnqO48T*gX9-Y^_
zuNM2dXS?jbs+BMhSOD})T9Hs!`A`(!fqDq@nfR?{m%8g#fI7*XHBZI){d8QRc9Vz^
z-^pH<H}N<LfTQ|N^+z_D2P`>pOhh6ew>CqJ2{=crp+mPzF&Sm@vWoVVk6y2^{myKD
z3XxmU&oYq4#|G3>_v(y<m(}X)lU24Ba6;+8c+q#gRSPeXj~FsTEbP|Tq5BMAl#r(p
z<W>|mKT_R0d*txMy)XmArlAUJX&9H834NbM>pr}~JxwZ&m;^*8XxK66)=MZPR87}&
z48!cB6$v7)h@3h(ehi>$O%5}d>Uds>g&%E!Aqv0&Sgv=M=Orl_&3D=1P8AbIV!758
z=sds>qGYY}k9(arKWN42&RYl5(tq052TrxW&2q!j08UdLj?`t|Ud`rc)9XhhNm2U9
zN@6iIwO%G2kp6t4H5y7w6O8oK9FC~jHbnQBW(ow6q<Cs=^a)%2{=2&!iMuG-emJi>
zAMHC+lBk=FX|aw>rIFEL{q6s1vw3P7IEefqWU*rG<V~{*Hh~Q+(f|hV8wF?$Z;VYu
zfGbZ)Cs8ps<F^uOFuDi(S*$>5tIwLRtjZSM-%Y-6(tX`%UVUA^hJh+VP;8e%KE%-1
z?-@3e+NEz4;bulRh8@4)lKmDg(V5RGK7fptX}~ld!o7fR2ia}8k|sCA^(SO)@WC{Q
zI9fX6ECoIKrRVlHT-1%3O0;x$ZT2_xzLimsad3}C^<0Yf=TR6Q&1j)e3-%M=-zKIO
z9}sDi`9l^go%jAMEhLbW@$DiQ-P)zu-cz7!{u9`yeF<ju?OdX_a`-hwq0Y@=xHeM|
zuA)M0E_ToEa1y@^mej_|ryy2=i1zfoQ~z?T&4Y_dqj4*xOo@SgSbowR8ewPKm;RzO
zb*g5S_}s$#ZpjJ{yD7-TMNBf;cJDP!0<+jk1KfCr&<_XB`IX%%iB{wx0!3Rv2mw13
z`Tf?%6SP0EQgiVRJNp{HgyBaY^q*%b=soY2kLMSDe&~z^{w7tZ__as3#gH2hdJ(IW
zwHuQ9HXh}sa%LNW|M4{Cb=-r+FIqcmSk464#&#@M{$tlRyDQ3wW*wT=`dfxk?nCHk
z1b|WcZVIy4&~`j`6K8zHKlQ2jkNGOs(m${^`=EHutiw{-(Q5&cE$YIkW@ROqUkB7k
z46gEEpv@Z@YCENq+eS8EC0Be?OhjW9{T`D5hmSDTP8r3c)w`R6DyJ1N&eNrO?%n;&
zeK(dP04E^a9)n9WOa6k7CJuhqJKlx3@4HREl`oF;yBlhqF%XHHF*DoS{>w<`W3Lqf
zW(@7x5KBMfjscB7x$7+4@en7K_X@6YkE;XNH<!x&?-ePuZgg+CQb<7~jb_S+2nG5B
z05#z3>ZN2HfTmXEv3^ZtRzmtuWqt=er_$|TEYR6{fsvdn<ojiv(l^2Uq`ICNGgDbh
z<PWI|N+k8Vo+7<hb0PvcD+oK@vhSwxnUavxBr|Polz-cQ55|pOp??j{#jFDCzAd1|
z;;)$UEDXR;bBV?+Oho!}YTb<Bgn#3UQ1FxsMUN9O9imBcSpKK&G6g4)5`<xkYR}SG
zZKGn1VHDUpl5cM9*F*HU<=K@OU5b>2>Z0xTu{H4Z(qF$*qK74|z*wVVwkq4gkvmX6
zR+v1wKK;Br)+v{?<!DA`W@dvMbiGrCCAm5b`WD~(Zj?Xe_VDMyy0aWE8UFkA`_p>4
zU*(+HgMX4|_88-QHaq_}rL}yV`vzgrUQnhIfJ+oUdC+BEs95Tr@4}dvKdohY-399z
zo1qcQX&<JVCNCyf6=!wypS|fpEh_C(N_<5+P3Y)|t?C(<t2{F;JkxmO!vR#OuK0+>
zKMkYhx2Ct`EU28OQf+%_qpEB}T~JF>mO|<|5z#^K4SPh}w>AQHr<gi2X*~Chkrq#=
zcenfV+b8m7cX5!sUb4KfT3h~cTZS*U7IN*ek5-;DT!`sxR<NOiN%nSpW7gmo<Nd<1
z5*|akUcAuds1}-^(h5%o4Q*a)RVBi%!L3-)l|+z)H}Y<xaUA!~6!_k}BrQ`&;!k^(
zA0^-Bd2C~g7wPeYF#$1H6c7{tpMv)Ds}!-15T79h{!GLC7hXgp>=QKQuPLY9DMnSw
zz3nehbc0Ws!XQ${!3LPlThL$UlCm?s%&GUUuFFT8<@p*7N;fXYWF^MU+&#JkgF7#-
zf_z`@qxmIzfdnI}axLU&v`XvD8UK9(Fx9&$x#_c14HanV3~om3uby*sA~#cXRPR~Y
z@jxzeObp;aphhNjp82s(a}C@-O%Da?_*Mvd>~bYerVz_=Zvma-w!c+)Ti`qO1#%Kd
z5RpIz@~Q!B=t-g5<$)ckaNAgq3U0zeFjR(?5=1lnrq0etbGJv%-nq{rii4fWYdn@I
z_8C8Lo=_UhNBYnmK}gMs704*tewro@7zVOV?GsKE+hsgt*ano0bOW}x)HiC=XQ1)#
zd6V7nHA<j0<)3g8TI5MohU8o(&{nf{9j$Cq=y@gS1|S@9R<;5CFjAL(l{k-HIGtPt
zj_3%|T8GsYe-n=~=n0^mWr#bD4LKy;w!-`P(uZ0ZCX7qnBGWx>LB9H@^&CFb+xg$e
z#KNyp*cwP5QD%XScu4W~i9Td|Nqk+IAFM{T-LaRO+1&_gJyg{b(N6nPKa4>Sax(H+
z(8|T#p)78~pfxkZlLim1PJE%vF0H&No0`QjlRXq@Jhz){6s?YIweG+gO;<|2)~)^v
z=ljr6{FfomDEZB{?NpDOcBON))N8~{DKV|NnVG}Z4RiR=iP9C;wKV(sCPV*cp(Zt6
z7nS6+cIdgg!tSlda$`pUp-&0~X;q$m1fRPYP|=USFmdq>iu-)PxCK4F)H)8{GI-`<
z)#Y^CYYRagI-={)4;j#JU($xc8#|i?d>m$S8oo>lRAW;IRPI$TqKA?IiO?7@nZ##b
zkmfv^hxKAlE@fZ;z%RlTRLokK64LTswngK}e7(5~^cKqOMiRa+z!bCarXVaAy%-Pp
zIdpD1q&aPkde0G9zz%rhA+M)gpHoXVb^f2sl34(qwjV%mkp7@9To`(0p5qUGlK(g1
zO$N~;Lsux^ewv{S&?441((K-1SSP69oAIQnHrPjJ6uGR#H!E<>h!6sSAk%)gH4s^<
zjsu7^0P9{^SpN+4v{^V{mOZkGCRCc`$x6Lx+FDliMs;V_dH<&pr#+Pz!+ca*)nr<`
zY;Ao)B3RoUzrp;GHk&?(19Z^N)xpNz-YaRp-MyrV^0rTu17Oj_-r@I^i%heR>Xkjn
z$VYJo{l@p5G8~~tUQsZ~qsdZ4dMfaz>Hjf9)wGe7w^-k<NdrMISwgnew1@KsL2Bxl
zhEOU@fjCQEBep(Cw4IEko^Si7pwRSkG}7*HO?hz4u#AD5i;v|5XI^9EP;$NW6lX=V
ziRWF~l_IU(8L=mUj-$IE&X?zj6rQF0hm}c1TtL2)EHhmTRwpiB{I!<CADvFgJx}L`
zkk_XqGyx!45_<eH#<%%P3*Cl?(eubC3dh0QVE8gkk3g=SdUFk()~6&-i-+0(?`{Be
zB`@$IaFjoQIFyil?Gk<=_M$Wsw}3YAlJ)rWx38uT*d#l#w`yHM|72@LTxw2Fgt4oK
zm;j8qI!vN9BDwwkrMH3CcK##U4ueVTpJvIjE<+LyEaR?(dg1p`BOmj15lWR&a1WD?
z2Sw|*;v{}a_|oRh&kPVfL3;8MQ}wjStudiA-O`c3r&KlV@}-SI<f3h#`*gEPzDQ;^
zLtsfnfEJXPZr-MEYV+i8qK*Vk)MMIr!sG(o*1v7P?cm|n_6USj4WDJFUBl~;)*u6!
zWZ~GNK9hOe-f+z3c`Sg2pcPZiThzVSqV%JGl=gq`buNJzz!*~W@>LS$B@zbiDSxQl
zfp3m_Ej?3JSGfj}KeY*qv}q!uBB=|8ZZZ2Qi18=f%o%G2#3s8$D_Z76^`#1n0?w*`
z8M~TOId9Foc+M?@f=%FzM-yptQ^n>dAGr}zvC!c>@Jx^?vz@|!-jul(v4(bPvoiKK
zCoP}IYdS7Ldx>{Yj9#d5*Joj?Qr1Fi>Diq6>Tu(MI`>^xe^pt#W~+9f`c<!T_}Sz0
zEl_}ztKY+RsKuCQRX~n01T`aHDnNn&01hAx_I7%Q<ko(^)4#NJ&LhL3m&ICpWGTX~
zRdUi?O<OEkN#$CLKZ6ghMk;!CB!IVai6ITv(AuGKGH($FVHYG9bg2q+7jGNYUdB?|
z<mWU1Zu}<3WkO087Zf>tW+n8b6f5Qtbm)kzXiA(!ZI<G(<#aobE~P|>&47x{@iU>8
z<lAJlshH+vXjZQ&X;9puTRtr}tt0FxW|tLoY!rp*$c8cxkNoP@XS_eBYG;LQh%gw2
zbWr5)lUgb9Rv>@}(!uxv(4n~m#Z_ZSmWzeH;f#8F;zC0_eW-f?Sv3O{fe9W%=~KVE
zcQ6DM^JN%{y*-IvZN?{J?55(9&*7|4``#6yhazAi5Qi!UnN)~3NL;mMjdm)g3QK3*
zrWX(aAe1727lEy(4<P{R7CntW;RFQ8gTSz3w672(+nWz;5&=J0J+Cm36QNT=qEePr
z7`;6C7MIbHW-0X`Qp5|xL*>2RDIyF2?SDoCh>F|JgW-S@XkobABX@V&>Ie6z$X+OD
zw?ofQ0kEZO?(i?kE-aq2g#)tsg&3=I=O}tUNZP@=gH{0B+}JxV20^p~A9^8-q9vy3
zd$MXH7ZDT|?p}y>uf;_~;a|k#PpwZqlW46lm-~Q=;XMbleH9M+WV=#^<>MC-Jfczl
z50=GJDsaxi4YH2D|7*Wr%J6+dv@p=Gd^d12<Bid?3OuQ2rJ7*5ENz73L}UxUmuo2m
zZ?F|P=l)3c8(uT<wfN;85|fH{yn=C1(~KFL0?Er2XUceA0?46Zf}_fgdxuASd?oyu
z!E9$}1|pf!?da+{ES}^a`4+$d#d3n3mRWC}B?y8>*t4k~|F?2(2o=zX<1z4nG!wi!
zwd06dj;EiKqhPrgnFKGDhEPnXXmLpye~uXos(bWY`j&b+t2h8x2>RMhIGVvAW?pL6
z+9D2#se~)zq^tgANFJTSpz^Y2E$Q@N1t$PDYV`1F^m`6($aV*dQYu%kqY2?$EliA9
z<o#S&9wdn_p`y-0`p}Gr`ghv{n;8S>39f0QGND}Tu(v8t1k>?XM^`?%Snv9`lLRm*
z<*Hk{-ibq7^WQmH3yEnT8Gib+K-43PmtwV+y}?3zew<Ycu+D#Rxj}>68<1~&u0nyF
zeCOSwf=R9E+>ol&N~~c$H;`)n&<MyZNv`21K>g{h%`;W!b{KD<txyZW$-R_bXLeEF
zT3pL2$PGP$J#N=#q~xVLA@UyW!Z1nWcaw#_&Sz+&AWb;UcGm~y&k<C^^(EE@_mE21
z7aw-8!=pihWldrXYWM>gRPkYv5d}Jt43Moy;IhI!8RdDL8vI0Sezo}H<37Y>?6a=E
zB=2Tz&zT8~E`$^Q5bTswH=ZpAzLLvsPMeEwnC3)sAnD*&EzX$6JcFZowmGapN!{u8
z6OVN`?TRVGvK4b{aJHxMgFe;q|3j2eJ)2=_CTFu}T$X?9JgsI0jlrXO-Lau}IPkW>
zz4-5$z6REoyWFI<+5MBzJKJxIV9XU?b|#329#U}oEV#+*90ZJ=EV5_k#6Oqksj#mt
zKfotMQBmPGLf1jiUqGY?@-A=<04d^ZP2i2TpY3u{APP2#FV^6!4>~N!C4TgxtO-Ab
zdLPb<B_EJ_PG~XXJ=qv(m)lUs*>Ea8-pp}3m0()M5%%S-#av^EN|8!xB^x;|)zi>O
zB#=?$EMiI@Yb?<d7p4^XdPcLvHu4cwpl(0!xCGl-v)0!(A%%SEgF;%#uUe+E+*mAI
ze376^bSdW^ra3)8Av~`W4Mq>^l><d<B&fiK9I(?y&U$icgyNj-Xpp>vZ14JJlbYh2
zo&(3<WOLn9z<t)z0tQBKOt(5sS>ie=xum<FzjmvcG((adm^+^V(eSj)f9lODAmZj~
z);>)kRb`z*r&x%w{%7Uk(xk1kU2YhdqGUR3c)P!V*6~V}MR%KNymJMmRcp3KS`6CP
zhjTlMY(bWLMA>u+-zSKHeqB>j9^u0-&M@N_{8GR%k3Py#Yakj~zRA%H?FeXIEn;*C
zm-25sw9WonS9r)tUx*}%7c%7J+T@vcbIx{{B18|!Wcs}h&by>ykW2w=b6;gj|4Ggd
zG#!hp_&nPIV2_vjbaat!-;#C@>EG{NdVlgtq<m>7ee-zIIc<||tqm5w$@3LENZg-E
zdc;okzvb=2x+f#6Ez<|=Tu%!ba{r2X`#3=_34)e$EmM_6Ry{DGfjzP(lujkljYY@G
z>U|3&ph&m@W6n`0d|hHrogXV?<|n{^_<|w}oY$lR=o--yD!*fBixW{AXJ<M#g12Q<
z*rnL2B|*|&5YSGqK;R-LLS@duC>7i|Nf7=Spo79Nq}4^k47ATB%DD%)=At}WNQ4aC
z2Z^a+tR9(hrD=kY>MsFO@O?ot@9<ZhwgHDVC!3#T-gGKydC#yLG>niBP(Yz0>%Z-!
za3l)Xg<8d58!`HFF&UA<y5YV1u@%<60;Xm3@bJe$ZW=LjJ!z3#WP?&IVkmJY@DR{f
zdB0sF@%entTTw9?NzrP?^#K2svTpq`>@+myNZn5EkI7t?a1B2H<@0v_EwT!lJ<`-Y
z7@2;%)Tgz0&w%_M31h{~OeG;R_5}2H;Q1&Fxvhb~optIPx?w#1!;9Zw-X|RlsY2?t
zB`)K80m}@d6W~_v=U4y-s(1I;<Fi;LD(4o~Un@E2MOj+iV|S5|QiajH<2`l-BFbeV
zQR_8|)4dWLzsURcod88zw6%m6R3)Yfzx2Xs;8R!20!}vCHFta3?T|JHE8dBwVFxic
z;|aT#_iP}Z=og^FH@5P?*;ozdHAmPMCz|>-@0pdqhjphw8(K9dQO<rAWRv3}HP=tk
zma1;FB^#P;z5fC0>jW*?biy4-2RSUMQsb|L*l);03!}9|bkZfANuY><4#^^56Oux-
zXxx6#4_()S*^yJznEFeB@+diKvs|LBKA5hmO)equ|BOieoy@4CopdTBz|0s?pb@j7
zx9)e}MPWo+m{PnMUe)0`M@&S-0hVxMow&%%UU9@If1YNdJ@D47g;)}J7#*Wq6Q8lq
zLt*4|>jT;9pLt*$l;Y<%l%Tv`4m(+c4Ip$W)u|;zg!C~iX}^1NtTQYD8h;B7zOwEa
z6{3KLaUEG|WCP&Ec`*imCXV}<%YZ)E7`5lFVMM<2i>D1rp#eNwI3JK)VBE?h&wNi~
TUm+NL1(;A5B;@Drz5My=;HdUP

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gmii_io.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gmii_io.v
new file mode 100644
index 0000000000000000000000000000000000000000..138f25b0f1cfb2f362427fc79d2bde268105fd91
GIT binary patch
literal 6448
zcmV-08PDd66Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkbE$Yvh3(hC$o0|MV(i$#-TvXAb
zo(xKiVNN|^z+QGsLt?gZUKrp_DNvQHjyvm?8;bQE*;E{W>eT*oES`8M2;~jJ$X{>N
z_*OE&`*dZuHi(^(e78D|P$VE>$!%{Hx*WPuMmx)bJ`3eAk8E}NkI!o-{r0HX2t5(w
zi|f!I-Cg{PGPGa)^qWJ|iMRrvpTflN?blmTrHeGIYnw0E!k$77@SUdKpiP$np|8h)
zz24g>RsuP<#E_hB7Xd<-XAJJT8k*9U_pc+y*h>x3ZaRA`qUIjSS60Tu*k&lzYfd?s
zBox9k>Bv#v3zgE}jJZsup5Q<gKfB0~?x4Xtvuscz^-@(f<8C3b-j_ERsg>0}6QxEG
zI#V$Q*jx_RH1DI`-aoEa{D1@!ko#(;<a#@c{vL#SsChg_O2zcf*j*rYigVa#ivsmv
z>6%_fD#u`2um>(}4iRJ6eMY?D(V8rzJ;<Wzn><E*Ak(7BTWK7<`q_Q*M&2V0iAZ+>
zyIR!xT(N;OCu9qU0d6Z`eHJKEt~l3>%jg<RCWHDg>)C;8jl4&@CdANN(s+72J8#<*
z%K8XOSBF@6lm>VM7Re6}@u~@(-dY-*>aZG6H@xNfuoN7fa=UQ?PI#i0l%VqH#}Lcz
z$tJh}fhtZ%93zyJ9n^_hkV?(R%lzn^L3+9`LIwq_C5{8#?l(Z;w&;X8eap<RI4VET
zK}+np+O6Glercmpvp@XX!8XDwT#SzobDmR}>WO7Sg|UPe5aU?Sd-n2m$P4OF!h=F`
zYlZG?!N0UxHplg+^04@r7WE^YRxuKah4haXb?>*Ik0#rsjEj5@wVS^85DhI?acBjx
z(l0`G!T~w(Tp2#xiW&5od6}+o*uqbEr2muD+jk+-4gzfAH<U@HIV863Y-P6w?m^=`
z=)9}FwyRWr&iX5~*fMk39MHC%wG=tzh0+R17&83*&WfkJ+ij6g3wzu|oFi5WfTIl4
zeY9`onH6gtjtqMul~gA$5UGa>p5<Av2Wgl%Q5HWyIF?G@>9D#XP5a$%EU*}=5bn<r
z^QAP8P9Wlq22VHN-t)y}eL-N80m)5d)hcW;lQZ{`dD0hBea^0BUpG!x7s8yT2>4&S
zUEqQg@wm;rnNpz~FK9Mb93$mpl#I+>)eNiF_RrbzH)%(k9+ur}vXI?hqGH(xh^gi*
zY5wDFxsEr)F}T6@3(!lDelxKIPxo;Xia(h<Vp=ZQpXNRhNu`Zd3xU;27~L(gb%zyq
zyjrQmZ{R_Kchglx^l?`*X_9`w<Do4JbxcOV<oBe|W@f7Jjhm>><|9CAP~`es180{^
z#d4e5)?3N?3YeQFJ1v3<0~T$q9^nu%EB9!vAOweV@JnT+!MN=FMeoX~VO*(Z=lkWl
zoiXv>Nh_8X(TFp{$5RVs4o^MOANi9QX5UF>J<xricFMkgF<CJVkqOFBD8UaPX)OKs
zdE$_5dmE*dn`VrgI^(7so2d~w9?6$9c=l)OF67W}Gwhpr0bBw6(sN;W^so)j@<wfr
z`0cN-ev3a=rvusbp3iM6AIz6nxi}ChET$wZ<B8hy$ZI9_J5qrFcUsdqK$%ybt1vAb
zSzo&5%ei;t%2J$S<s44K@qTSMT;*d=wW}B=n_g0+s=$y<w`d^?Z!M~(&8BN4%@|W!
z>+RG>0H1QA?8_LbO&DEt8{6WJ`p@18uw8xOGJajKkBVnoo`!w)b_f12UfhB-kvN@%
z+Bw1fcA03tb#0jBcc73^{|+*OPE$u24bDU@SV*!V=JLn9On4^*$xnHnQN6zckgaf>
zrJ@tWy15RsQiRw#$%>h9Z4fQ#u{2T4I|0q$9iNL<np$RF#;-^0b!L-mg~A&lJ<Y)j
zh9%FY(k3i@6R4z7kO=+%<g{ygTMmSa?akIMFcfefsFBGsJoO`LQI#4A-9oaJuIV?j
z#xKjMcv&oqSOumn2Ib$IaMd~p9hk&D49pX_#1;FJj;IQ|`!f`koNaB2E0(^OAE$|>
zPRtZQJ@Eee-njI|XT(fyVZ02x?C+GD-IB1=8!INmT>yD?ZDKMT0K?cginq^!cp6Ux
zyU*@E&nIP%+piarB@h3TC1;^E?%2H`<_$ewz$0gUXb>p*jWS&<c}1#hGGGeZI5<PH
zy_qO|7d0i)t3*b3U0T>(hM>nhBst5@Wlk=k*8fjVw45$K8z+wo`DZI4r;9CTqKu)*
zp&Zw$ImGNOPR5}KFP1(?YR@X9hIp6!fYU3HHIpf))qha1C;XSL6du@LmgVeYx7&sT
zDTkId#9{d>lIrgZd49}3Op{4dm3xtWYoVRWuY~hzqhS_k<w1Fm<G<qo_XP4@*N4pS
z;lj~h*|&!m-lTn;EYfo}CI2uzyFWHl*<3I%Z+Pd2(zCm24GCP8sub(ZhF4Sc(2#JI
zH)wXW1E)<q`)1J9mJ^junw{l`WQy<Bfc)^x*hT%ue`?^9VoX9AeQG~a6ZLw>S(!ti
zX5^+E{ooCwKn8~qm1%E@*}glgilik?J6!RN2YfZ*^g^%VyoEIz?L^>?IrVTblpnI7
znZl(GEc~yJmkCtb-23@rF)h6tHX$h9RKMUdmZr91IOwt|f3#tF4PW;us+Ewr3pe)-
zKE;)P7agzSVRk)mHuTMB7poQ0n2iif;nv3rX{CU<Wezi!W8v&e2n=LIt-I_p!JXgT
zS#Av*DYuQgjY(-ek#@?-hJ}fQ)kq@YjDEEL(Cb`K%IhV>I3Q0t6lh(Lw^g0Bb1CnY
z?p!jSql=F+awd}v9D7E>N_@0q-29FyK083)MjNXA#HXHVC2dpCJ?r4YQBuvS2Ss?S
zQjTcrhne5%?Z{zd*K6W>J}f<)D0V{pK~ljHIol$Rwb?dnw@~Pw;OqIH^$9722pNVY
z0AgsQ@C|GmhEvrACsTzZL<%Uh|LutfMekmsiyFvKjMLCEMThu-o-7502&BI!Hk_s$
zH4ku&Pk7_EBia*3c%r?C#rDPLqpf|>ar%fkMeC8gw996T1sy)v@H8CBRjPsd)B#B|
zrH9(w$|=MI^NY;LfSPF|xj1Exzn5b{e_?%jv2lWp?ZxI+Xjz{!z=MDk;A1J@8Kq<`
zNuYXRNP$YDweCq)hAv&|byW<NjfSGKWN8l2TD<|gjLl5tBFa-k1R+;-e&?sh_^et}
z*{wX-QjqyiKB!5q2$1CQm5n|`nL`-?N_wx}f$S+xR_+jJZti#U)9lNGS%UvgbkEve
z)v1AZ`YvLqw|DqHN|t@AOn9NUcqp~*K*yOiFQEJ1GqZ)-#Y>+X0tp7frP!(IPjcnf
zM5j=jhZ?b|`fzwWzGTCv#Vpib-Dwijj3B6<i9&0_XE~}$sH2$)J+6XU*CEqiTcqZd
z5XbEnA~@6-yT+_ez9Z|>pn{+dpA62Hzdf>o=8BNp5G3~`dhASmW`aIhxl6sob}vyf
z9g`J`ED+fNQ!y0Q4PdvYo*Md#KR&rc3jM}6wOf4Fjj@x&)QyZ8%$=LnQ2qgZ#v@TG
zW+<Z}6vZ&5)k>$O3X(&)rv%%vvB2!2&x^KO9bI2RsWKJ3Ww8K>o#;BuX8!6%mMn21
z-v`YpcI>w^(+9It0UzMNt;Bdrfpme5<bSD1_mNpv%lKY5=+F-1Np~gtsz(h+$_X(q
z_Wa|?v!dQ3vY?5v3KS4Gu6aG=-RM!WHE^@qyDysl<t*?-2IO9q>E>MZ9vKKx;!{*+
z7NGDp#_V?_UE>NJc;1=p$*Yh~p5T*q+^lw0B#gBvwKnsbr^71Jqav>lEl2uTO<Lj9
z3&y#E20i6-$|;2KWFrAu>(vnmQ)qQ|ZrLM7PW(i||GAW6hCNHJx5Fq_sE@j{Nax{q
z;#N8Yx=PRn1(YJuBzrC@!R$@x58YOAMn))T2er+9hgY9+OtrJeGUK+kRpnKUeIU1q
z7LA*P>A<Uno4DS_o?1>L(u98Pw@upJuL^r|1*NK#p>X!P-ID=ur%zK6B7WZ@bSAaB
zvATK#(flUqoPV-+-zf&$3ma{O4st$CDk6p!mmNqlIH}3)#UE;Un(|SwK=C%AS?T`w
z>-6~Y(fd&;XXwQW0qWmpU+{7dvNoN`*1IKUx`j)q&t!L02lef3LH(7^mh1D8I*kKA
zs_J2XeG9r2Nht7KBcJc)U1&Ow?}M7k*1Pspp@J;g2FI6Y{t^A$E993J)rwJ=xB=hJ
zmIgDke)D#XIHFsGkJCQX)WJxtZ=pMZ$)2d>sez^!<cfM)!)hy0o`=%JBDzIoynaGE
z3{){maHN)`?8a*o84uj=%@GQQM0}x&Tg>-yzXo5#B2>U=rn=>T^7D*lh>cWNZZ|{r
z^%OO{S(MLAK?FMdAibYsGS(9a=|2pd|F~9*r3V71`@#kxOXKaSjrFoGwS~R8$3~2R
zpA$0IVf+ljvsNsl$Q?VPrMxQ)VItNECZD$QaSu7O1#FS7oa)>r23(82cwZ_2Zh+pV
z*uD~MEm&7U%)EssXJGbF?11qo<*&~I@BC|%=xl#l{&!L_u|#HUa())ht>8QxSW+IM
zLgaRd9D>nczFc-0G=TfwhW?qP$xrctThko+{dfg}1bn{n5}o6u#@aeiku*)N+d>JY
z12O(-oreH~(9e@0kt-$T+<R{_HS;D8@9y5=eQcHVUImF{pRMJEV`7;@WCPNX;^wn|
zu~#ZQ>H7s&!3txuIYv3F@5>_-Zw;q8)|+Hm7PEU{_tx>+y2wXzd&MyFQK0c6w7$;3
zHFNEqEOJAY+x*cDv6PE?OtHl(Cjza;NFd*D#tTx_DDa!lAi*t&w!++`W!cn_0ozS6
zT+7T3icPdc`>FW6r*Jf^qInn}0_CaY#1|0*1-aaI7toCN?I{cjyh`cmKv$L;c`GC1
zFZ2jrI~az_Um*w_vD}h_)$XUKQ0^e)Xfs(S8hy;vTBE}gQ^_uFOClRUe6;uK+*It8
z-&ch5;0#U+P-RO42z+YEkqq?E8h@<gnYGyQ`KjyUJIMaG?|i+9?AOSUM~ingKtSO2
z!)KBA^}K3k;LXJ>0ax$W(7WI6O}~~Q<g1k!rNJv7JE5o0zGaZVeLW5usYhEft404N
z=a(8lr9_BL4g*xoxYC-~4;ad(<=G4TfujFqwR7+baI{iqjX(L6*0^|l)z%;cE%AZp
zpdUKodDs5l8$*ECLwxp`6TrPb9(eZ(ExNNSj^XY7-D&qcWu?P}bavr+g5HjMx!N-p
zkZTh^<!C>Vfz#&4^erXW4dfriNu?|)dj9$Ax)LAHjrZ@wmp!^x$n$8xi-I68mLExg
z#BO~Wn)(~j9!;={Ng+;2N-qb$jE~ntXW@PYz>uDp64t2mG7kYiw`4>ekn9kFi!6i9
z!*xOul9v(QQAjy+3FU<JDm)4MG1AD;_T{UPTxm+Qr9s8op{sA5tfMzKt~XkBwcq|W
zx=hDXW>V?}lGsWORSAw`!f7d#MlBo`XWWb4sCUPuD9wlyW|^v2rwBg@iQl7L{EBOT
znE$COi15B9wZbhh_ktF^`lXXoya<v{a5hl%KxiSNh9Lzho%F`_>#d3_%-!;Vc?yM;
z?o1${-VSKOZ6!M2&<U6(OR=8g4=uLet<BRAk2-|sq{V_=B4}BzKnDn|LD(f~XPIGg
z%yO2VG<&2r@ox^EKVTT60d8oYT1{=K)~GI#tlE`x+hkn@s*v$v1kL6<kMCpA4I;&a
zfN8#P>p^TjQK%NxG^rv7?xuqBqIK0zU4k25*Q1-YaC!!Es7C8HXr3)8qAjx?8$o4~
zxdsKc5tn0h1eNkhVoRvK={QEjSMO31+nwFvKsIwFsS9qA&$mzkY9SsSh|W_2R7~q~
z-9~OL(}j6Jo~J*6{xy@vt8caiO06VajZJ=d=3w(Xea5l<=QIt1J0Z#ps<jfvA8MU7
z`e&L}g}>U)dr#~#7r~)${dGJ7WmnhMN59f#@R-e7DisO%3YBufon58{^+ZJ2ug$kI
z(*MlGsf<F#N7zS^xjM#Tbzw|tofxZo*Uo265pxBH<knJc?qP}=@V$cGC?l(YFmpgh
zw3$~-y@@Xi5ZW)}zpU#5??w4lvj+T4Dh**0xtxyLnNFq40|J)14{k(KzF|%ps%K85
zTm$q(QIr+gE1{xgygk~xiF>>$RKU(w!~M2#hpCa|%bQ8bb^&}bl6tu-_(4eMq1F}B
ztix@;!V6P4fG}gifzA+SbOj{g$et`@IOHd*H!CQC|JrL@CR=hVO3Q1db1)oY3)*Bw
zWtD=^Y`*Ih9}K6u*`?kDjMZ@T%&Kl6stoGnUmA<l-)+hYG>!A9vtI8dcLH5*ni0!E
zz#8(U95w+vhX8JD83I`vE@Y|<mNSEA2UztrB4r)oDS;CGOgDAk&4%F`3|3z`=EZsj
z0YGh7z=#2l4r8MmwSX_=0Kj1R&;D-(mhxyU&_^*4y@}^_sHPa*#Y&9_N>07HFzsQP
zH#_I^EBe)jIte*J6Y7DQ$`a_c3y2aG>*1s-d2KzIuGn`yR)8vYt~2vAdb#jzA9B5Q
zZ7V75FfiIbg;3q>6KBf=#UKbM+`7LM*+e%GybRsze}UrEye%#`TeApq?VTkkt?9oS
zBh$?;Y6!HnG3>&pcUIg%&-?ia(9qB=tEu5Uls(Dn<Mz8a6%4=>C+WLJC|ir;p#_1Z
z`N0~shxs$?MjDfkvzrf%Y@gwQBZHy+ZO{H81BKs=>rYHz*sS938S?mM?OBd%nj1a=
zi{fZ6r#TfNQ}PdQ;a-ySH8bzfW@`x8x%9^i)erlLTT&X{h>|EWvqT!M&ReSeWT+t*
zYaNW5Bw-^jm7D{DyX&Uxc>>j01%&|(ucCb$G*v(na-Gk#ZXJ<>4cqdsJ%eUVGNgvZ
zfj2jgB~zxC9An`Nf6oqa^wjXoB9q+ZdL?gKzpzkIu<oeAz1$zS2W~M7!<gWDsmT1!
K&UG0&H<vg-`I=||

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gray_cnt.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_gray_cnt.v
new file mode 100644
index 0000000000000000000000000000000000000000..e7271a4ddb18c67e6939ca6a5a967e20f6ba7497
GIT binary patch
literal 5016
zcmV;J6KCv;6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btk<MaCG)^pjQfkABO;6n|>-$V1@t
zsP~(#LFcjHim3pRP4I6wy#$AM+G?snh6Ik4Lv^sk1t`2q$lT2s0|O9rR9OFyqAseA
zGG~$$Z};iR2MRzE6aJzqJ)wUsQF4I+bQ72bAIEC`w-+g|J)^ec)Q9+dHD)xKAutmr
zOQwprW3?*Q|9}S9S8-s0*62=1n}wk!x2LkZrr>@g(>9ImfEvWhE?_fG_Q=!PkS&UW
z^4})}s@(NAKKo2}n^qS?hu-&SiTOfXQ;Th6SvEX^dTGd?W+1H~=eP<9z#Zi~K~MoO
z#YVM;7Q%gY@psw`>JbX=$I}5z7oJ}owk@?BI~lq2MZ0BE8LpqV2*V2aeZQ*QlF`lP
z!Ai1^ah66B$^%rZ?Ki9ls6cAKMU+$}R!WuNNQ-oNXZ$s%)Obi$N@&`?Yj;*((^{8}
znyREWX8UJDMsADXyWu+Sg-G&UdFZ_fI5_qPwx;u;ef|#HUHgeq@AX`hVd1+4uG7GO
zQ+yqRDmDk1Z(=WZnA?vVTVIN(+QDC0cqBm*oVZ?`4w&R&mE*+ARbp_xpfesI_Fd34
zMjg>1rSVxCA!r6p@Jq?9OKdzS-k)$bhJ1KY1q|LO7W8ETlrOJS*(r;C*o5AOLeZXu
zjIMt4>Fy_O<2Tr})!f(~;oE_Ck55s^EkPcqV}tNmR8l8(NuMLpx=(ib-)rFKqBiQA
zF`sBI;9`!@sHh?Na+{MR2@^w=c*w@A-T4v~{T%M@V*iDy`&zrWGA~@<-3YEDPkF;H
z(3idB&&#StY;5+46N~MyG)--%LeysWFRyxjOoz#{dYBM869r9#3Dg#--h1^*W<4oe
zSjf3p9uEqjbMOYjix^w3V`zi?CykB;Me&h@vai&Su;|#Eyy5H=HI4sPTYo0aB;J2)
zu@ENf)-a@?XN5892f)#OY=mV$tVYl-L~UU|teQp9Lf_QGxx!QK;MbJT3yGncSP2zI
zHkWf5y;NKb)I55i7pzV6Ol0D%E$xC~)HwRTPB4Fga(Q2ungwSOz;S$1oKHFB+gCPw
zU-$#iH%Q46WWr6(fC_e{4=%RC3<nWpovKZ~U^t!4?!)KdP~*0_3r5{w=wgl~g5@-=
z1}iwghXNTD00-z?Fi9aAC(F^0>z<F&&~6tg?ULxJ1s&M`nlvuH(<-GcBSTl#r1##p
z$!F~sqb_?S4T+)JndEk0<6EqW2Kg6IzMm!vqo(Gm*B2iv|EqSiop%Ui7U0<e>_j%#
z)S5XQ+<x5V=1}F`q>QTqtfI}}a&%|9k<PBpFa)3vVF-UYMGs}X^Y?6bxRY#Ie^{dq
z&Ck!#RF7(bhL8R|vJ3&%+WyNn=wmcjlKz%NZeXB#Lv^>Q_?0bdX^T}^A+4G(c2sSM
ziNZ|s%x1i<h$V$ple$HET-ig87hZtfO<@{s{55yFO+-PA9y8fVmzVml#d)WmrgMyU
zsimU|i|`XfhPsw9*5I8Hv$L$-rvEb@`rx4YGy%{L^a44H;q#=&y?*^4GXQh9nsBiL
z|KPxT;Q@z#r-h|Apj@#L#;934^X=hV@TwZdNHcw-boEz^!LxyTKa%QskX?^h^XH;+
zqkhq7?QdtHV>-}!CZWJVuLhvIA0kaFtk_PmrdI030eC)gd$;J5f5)*a%~#(b&aH0*
zo!3F#)b8p4fqhD7?!bNIM)b4ccmhUMgRl1-X6Y9x59RWx+Ti%O`4>o!c64F1)%Rtj
zmbfJ^b1SP+wrHoTd*q#J^dWo8F-0{kMuRnnAY=VkCs;!A0qeKnBV&ezG`j5kpMww$
zd=h#FDBum5CdRA3WPQMABYAn|Gng8VP{#<O=#m~CbZ<Dco1Ynmt9BEslUJ8y6@I_4
zY26{)s8YyVv+M+kQCu<T@V0^GPt68W!T*b?R!QlOmxf|%2u)Qj2v+S$nph5i5$GY?
z!@<?s9*XIW)aYxBK0Rg~eXs|B%_bCIX;wlZGZ8oy0Y*?^fH<p4>-~bDP%Y&Ar@j7K
zSOjz~?y=nf9_z4ZmE-@ohJaRfF$zFs1%5IDA0~m8me3Z2?qR4l>mM6^syjaS7U|74
z#3N{Z7HIaCGb|7pJ+jUjqx6aeB9><gc6!}ma?3G|2-kx5`+`<8#7HWIGmSJvBNG%I
zw5a&)kaLgbHu!`(Z1%Lmc}4DlcK)gj{DekV*-Yf^g{$TO5EHM?ycdPJ<fVr}bRw(!
z2F?`_l_ueDw{^gH%i&yY)7Ekh*9HTxqt&Kq{-y?_DE~b~V}@MONs!i<LySN20psT+
zxS}mu9=t6jzD7Aj&`wT<V#-6B{=?(p?VWKXsgtb!3?~z{_4l;u%B<fBIrZhV%*Puh
zASm|Q*<&g`5`8X-g*OX{8HZ<4j<f>v`YS+wpszJW)fXTZRp5K`5}#(Ix+VI>slg4O
zWP6q;s%g>}*HmQW-ZXIeojxicoDX=eCxi`R_|1~Czo#@}*9XeNOiLx7d$iuR^OWcr
zqb)E?G%*#F7VJWF<&sg_sp0KI?GQ4fg4ZG0e{_#Hq1Nm^da}83*oTEQ3x1>H_sm=S
z)rR`iXsVWN_%irbh+2fK*7wQvNnx1gsN<B|<Yfr*K4hw>{%ihFu>%0=*~GE*7z?jU
z`+;jUFz1oOwHvm`WSbapcra|edl!u#bg_Mmr`7>l=;dNpcBgj?4%wHmg+ZnOIDnss
zB`aej!05TC(~%A1S$3}X@KG4>xjAu7HwQ@S-0qNf9@wzvnJnW}giC(4GOMX8Fdo4O
zukYxv;R(USx1u;vSIdgsHtl<>uVRN;*H3l55;K8Zc{STRiYE)3P14YOw+?Z8SStbm
zmEI{#a6e#XR$%X)weY;AcgL4;p54GPfeUY?#zTWLqK;tf1|3O|LT`9XIC2XT4(n>b
zz<*+8zF42?gQ4<^a%Ugx$Q7ntw=X<<(PO@Y!Uyd%z3@E!%9KU6JpA)=st-7#c1m!S
zEUDBI^dtsL@3#R-xKAn|e<O~H&IfiC0du<`FZVFD*n0N#Uhl5UlNoDAR7g$vmsb>e
z_y$x#{m2}RjX2`T|M|I_z_6yL6t3s*8bH8K+Q1t<flDr`jM3E_d~*xr`_`M5#{A3!
zoq<xG<AHyZPXCHgB;w^MqF(i^{Jc?Q7A$Y_PRw}JkY9b3C~5$j!htYHjYKM2GhcXz
zPrwDGQ`rVah&{PZ#sK)jVfND|3cl^Xs2qcL@)|+@ZG_&73U*8Yx$Ee$WlQBkXgWI0
zqpEi-YMIxs`(cg<3FF=7KBXQmf4G7@(y9?+c$_gDD-vI(BU??+F<<{LM5ja!3Nh?P
zcVvnsrAw}`S*;-;Qyj&gSW>P^A`wPoObn~1IOxY%qrm(m_<8HGJ=#1P*rlN?@r*8t
z4wrFUP_N;Az2amXTf;kvW)HP5y_PTop#OR69^*g}v%}b_*J4DL@v;-!r(54bgmRC)
zalchmnk0g|xEVy{=r!~*I^Ti+C1eQS$nalL!yv+-#g!1>zl8pJCFT9QwSr?8kAi&!
zLfxwgttp||z2DK$1jI#hC(CuY&mGqD%5F3=0ljEsd%-5p?Js~R;15C16rs%2l_8T-
zn<^)0_F%g<2;PNN$K9%-x}dD9$FsMR3Y<DxS7le5z54N0{06|@&DT`Ohw~H-3G_7y
z^G5W26IJ+?6^Cx2@nGD&&DXz7F402^R%41nw9qOxRslXQ2dB+fG?;$)o&8nTG;a@9
zIaG$E3C`g0BRirx{-xJOR_SRm1H>No!I$6>r9B($;X}*sR!7Y%dlz|G$*|=m15nvZ
ztULQc*xQ=(bnZJhof1b=u1&f36Uq2Z^D=xf7Jua#;Y9Aw1ZIVNYI~a!<`MO0jR$*V
zna3S;x#>QI@zfCGP3_*-6M|O|HM}2D(f88F{#t4EE1-}X6xgb3iMnhnIWf}bl6r_J
zkxt=fR2LzrH4faGB~Zdm3Eroy#Xbd)ylqI;7ly(K?EoYtFp!>H%uEuvI`8_!!vTw-
z{2w-uWL6FQU-zJfKX05@#NJ?x=?*Tu_q8DhKn5O8G&>GU8z=O>psL}~hiYNY4VEMf
zJfKPmQa$<U+rt>t5c%DC2@4bJU;!C035`F|cq`C&Mn_7^^-l8vE(6P$g~m=*8{n+q
z0~qhZft|7UQqWtt$zS41JyY~{;wE`Pf-liwoEzzTDr4L1ZAT;z=%92W+v4j<kPwyh
zb@JIg6fG7#R~|tCyj(IHRl;IMwhl-202Cb$i^-%Squ{<pt!eNPBubB`PwCF2e7w;$
zK-(bB2Ai8;Fnm-CRR5bA&A;!6Pl~s$);#@T2;<LlWSbzSjNvE~j}fo0@f<->l1u?~
z(}@x+Bi(0Zi$jQ|AEJ)Vahc*S(z>vt@itj31@UrezKP7}er<acL#?&Fe>N3kQIIKM
zN0vM=M?iVM2f5RH0BX$>$6N;Wpb+(;4uM$Ow7%XWG1JH>&>hsLLl=5wn0juH%xbXU
znnM%XTdUM7{I-=46y%1203?%Cx%LRK!vmWb2(C)fCKm~fZsu;1sBtA89{KKs>Jrt$
zA9qus+}GjY9>%4?l5XLV|9-7c>+%MJ#9K*Bqoum1xfic~=G|#{YrF*L1;D|8DQw-<
zO0Ptk=7l+ktgHG|M$?-VuShq#gExqS@D^5sAJwa$z+~za!fC1K=y2gIcK_Jl>=XAd
zmjCrwDRfA#APr;hPiz}v;t^*%5%HrRwpOles0qIx6TV5!wued7|Mh@t1}{jOka8|5
znWF7$0dvG5ei+YS@4i9{)$V3YMP-po(f}eR)h3(v)rj(3wwR10?27i8mR$x2Kta8y
z@Uk)q{~!gD^Ui-tG8K-uF5Ih2gl5_2>>u@COep=)KIa?IOsOKHrIl{#QOx$eci?w1
zH1<HvX@a}vrv^2vm7yq`z|j0RaBw)V+4rv=20bq*`^+ykqrc;rW{)rk5K>$z{<I(k
zKYJay-zMRW*>#dRN(!WqMDqyg&n9(pA<q_}E)q!+*!8LTL<+fQVQ-FqsMJ^a(ltP;
i8I(tV8pZ*Yi~iW_zIrT{GJ{@Il#ZWg1(L<vu-kX9qsv?X

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_hashing.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_hashing.v
new file mode 100644
index 0000000000000000000000000000000000000000..ee55cfc5b46001da8b88606b22090d3c39c640c0
GIT binary patch
literal 6512
zcmV-$8IR_R6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlSqpKG<<!F?<Yoh8No!LYIx^xAZ
z+5_jc6Kc0IaAV_U623UJvG=XJpZJd1Qef{t_6=AvxMrJzNf~IB*wPi%8rnZEQvlyw
zz#eY9F=jK1&x5kIt+(DRE@0`9j3uF~mUhL+Q2-R9V~%#OJ7Vz~Y`Abs!t%-3=fCHF
zA)p~r_M)@-SxQ!8#o=`euOsTWu{8C?f(mvFqTkdK7*GPXYjrW$w37g)QZjF>!ALO%
zQF%={K{10VFHYu@K;SJywY40;&Q6l=gFTyMS?m8l*0!GUUi_ZcBOsi!Cpi1olnS}T
zN1fX|uz5U2TEZ``R|J*l32EL;bnhX!QRXfoO0&tX_*QPn@$SBNy^wQ2JvBA$YoT`(
z@l>>{pG-I?5g*8+rf=Xj?I>N*C6B-j?t<M{j=eaooO3a5<q7{eV_x*xq~%Vls22-0
z>ZLSXBjcsmkp$)rc|(M5S=Ry6soe_frj><%XJf41XqGGm%A5*rl<AQ^o8L;TpqMC3
zw?Crw&`35lv9cuyq4LNSrdAnVB&{mlxkmAb(&beS2ouZYgQQTh1DAaXY+=ssO%|;h
z-@cDL=Dw$OLCt0X>A7d@B?1_4d>sEWi3Xi?jY4UDud*wgu$0p^d%S@R<3jMr&C-c#
zHhTv}m@n?=jSJnHpBRc4j>g(KHS1@ctxOMM+h(?bsvT??gy+(hpJ(K7)}rT!G{8Br
z#>>7SuG2HEP9NgNes%#FCkSRH{yQ{xV-lbbP*-kKKh=IDM>`MDiW7|M%U~TyJrER!
zr<>FSnlSy-qw@l=0iL4#um@7u(^KbH|1$$87P~2e6apQ1Nd&IN><MWkARdw#-y%0Z
zKejDnOhbq}vCDXK^hh5OOy$sz6d+KS0E8uJ{Ctpq2Z#Ui%38W12CV#_vkj{TYm4*k
z924j^kqpySz=cf3+UAmR|Fzu6Ydnj7vYb1;S+bW&?uI^RSScE$BwTrY>X`U$?%FnS
zY>bcwRFB5b9DfsmKP@FBokwjR0Kt^etg8u7vpVGgVZ?P6(0Du0NaZV9V00OZmlvAF
zH*!FDEW(kBt<*YW_GQGB-7ruZQ+Mr32GRWe2Yn;BFC<<fKfdo!S@&;Rd4V&I1U;(0
zYL5JtjS#lnFIrxU^&Z$BIhLL#rOt0jI0)TIa}ilZgJ}R!GrQcATAv;`T?}*ub$NqT
z9~+}!>x*oXj4b<GaMqE>Z*6`GhVW0ZCf<L1j0O~w>m~BFR#kxgMD@jo+c_<`Y)t?N
zcCKe3Z{+d{{rKgR&7!WrVcr(GZ^*K35jGNdg^g#HvJpS6i510ks_5?}qxvO7B<$nH
z-}lsmn(z`9nNRiC#(}+QsRhzGq>*LTgnIk1AE+gUpOfR7K6kK_UURTtzKaRix*__}
z=~osMG_=V|5crS#_(*fqNBqE6bjXAa8;rnDzLf(Co6hyak4@>kk){+*9caWrC3NPD
z4z1+QGuxAMZgBcXtY#E-kSA%9_J^(JKSfUmzFE*S1r?>QOkkqy5M)FRw0dS`Q=1c=
z5@n)5o#xSXXH2ax#GKx+wZ-4VJ-cDPrqKDUO%emokeIFo?hLTgD#fgZ63+=be(RCH
zQTtwW@uF+Zmu{VTb?rmwR>cz~R$NqKW-}AY@{559z)wEcV$?C-VZR0+?I1=`l2`;-
z16$4|9N6&Ex5j)vMyTi@Y~8%70bv2Jrh+VE=n#;lx*a!*{5XqIrvuCSPPLJ${nWXm
z5-)%oZZ`_w)RsIV#Coq`Dq#E<v;JhOkSH?b!CY|>h&*!+-HQRUa-yBelWy0LB2V3V
zL&tiKJ*dK_;&;0qOfe)xgHHp@+|hyJ?_)Sq?)PbjJh40E+akZe^j3P2UhU2%H}Z07
z02PJfPs;JjdT2F+A&xcZ5uzJ+FWBomyu6hRtJu~n54fJ>^$Pl9<BCgpPK6GS4B)H2
zc`cXbJ&k*I;GGM}|4~$K@TeWMXTZ5CfL<iwIgcPw+ApwEk72JX+6pZfR!ENoy&@qG
z>r1-wa&ewtj2|9=x(l{+qZN}xY%Ra2t{D`{zkN-IXI}IV?(R|LwcQSzr1t6os=-9c
zuy%rM##Y{l+&j3R=Q4e92Hh(mFi%Gx@90N9*mwJ_q_`rwa<;Q{FcgMT(mD9Z(5ibj
z=P!WGV-nk=%D9Bu`TcbgWZ)qOyn%B1y|c$y6^E|-d;f@fNq;rgjXh0~92N$m(`BFZ
z(*h#$q`DmNlie;+ygvn(ijZCypSy=663)|c4>w6G_%I-wYBXx$YcE9(Y8T!dbeegm
z@Hv^;(f_le`yb^?4Wmxbwg$d`P{9D;y%(3J6PJ7<rzrg!4}zcJtU$soC`>}iUaJlD
z+keE}f<zLLq6e>nE&?}?M>L(m7D3pM&=-GN+LjMJpuag}_kh)Iu!%ust_W$_Gg2)c
zsH|Q)5LW6V-ffG}BnO&H5BV$KT^#9Ptdx0BysYYfkA~g~!gU^TsmvS7YIEw}Y@~jL
zO^i=ob0rZFA^ddR8zuaJ?ymsbtBZ~$d=QN-oL(F-grARr&&DokIDogBy&LVkGinN3
z@iShMkKsl0pa~8|DhDr4wC{zKOF+Gd)PxQ|K}sh5*pF=NWbI*Vbq{ou3;X&82+sPC
zy74SsqLz4e$L>~{_cvokFZGw-)H_2ncRSmtBKy~>`B+o@vd%^Uzmxw#uSHUtk4+`9
z?zc$BvZY{@0clcLXyvyN5J>-hVE2iKQ&c$G4BU%trW@&LJH=J{SnL%d-ty)R1tAsO
zYT!E`f+_tPC&}bf(zY|lH}U~qzn?fH>v|rlO*0X8Z!JZ>+N%$Z?Dz0jcn49AklPXL
z4>CMRjS{#I{*y<c@xn7+@O^z5!|tc7!HK6QDfbeO(i52}?$5=P=7W`V6bBtr4t1=@
z1PHg_Nf0vPS)Ckn8GSFMh~}FE^+~V_D1~KebP8>)xjEP`b`}7hxsuX+(iX+(_}Y@z
za-}FWYGIRXe1P2y%w8Ks9n*-aRk(mXT+y?7T+hgJmYf^zec5IgzIT&lAnaF}Pti%1
zX%ITNEVe!yO~ft^_j<;;URk_@wRTpRq1fzPPXp~m0y4v?iW9a?W(n{LOPQS+gnL+8
z52lGTQ3LzI&PrnwgD}eW!C<Z^be;&xIK`unL}$-7xb}}dqwf9#xkXkrY%I)wxhjvN
z7*~;dC5C>*Gei=R7wcZr!GVdhB29ZM>KHt1A3bdnonIdv!7$aXJIXYtQj0RRkiTIf
zenlwy+ncZ2dkM|;`CBVkttGT+<ZG}LOE`(ptcL!7b#wXqtd90K;_HS>Gx$w$+eD>j
zc=*i@7b}DB1Kc5u@zM5wT(j%<uL`c#iA0LHeL_}{H<2xS>S;3hRd)hNn=Eq;=`x<4
z)E~lzoxdX<6FMnRK0UTy%P-`fyi5arWx%{LKJ!;I@_;0Z%}xs~Wzn!10{Y_J&`Ne;
zVVNyjie9Fxi&*9}+asQ>N}EX7?QmYO+0XgS-JWX_Cw^$cUwXlwl!^FA{6UQA35qXh
zKSx4mJg{OghtaIBgmB9G5nN%=>>+w;g?x<|hPy~Gr#f7vv4nxLNMy&ES&7Cm#DoLl
zs5X(lPg^_OWzPAt3xFC3q$lO%)wi8DhA#mx%_=;%)WoK|dysmI@ibUN%^6%oHHw<{
z9CN5x4@XK)UQx4=A<C9FVPfd7sqI%C<lSoHy*cmAPDD4Rcy_vgGz1P=<NMALV(X-k
zmF7vCv4gbE!W*GTUPh?3A$Hq9r*-c6ZX8q2b@%H!Bh-xEX+4AXClVYZmWWf2H^y4#
z(#qA0&P}^0UT2?acayb^;;M@2fOR@b67x)5?di$f3obu3KpOS!A>P*A;@(wOmi*(H
zD_0SSab%=(#81~=jsPFJaB!g`RoLd74czmQai1f3xU<1_8z83<(<#tiC?r$wK<tKO
z=G#dS%p)hE*qP>Z9#_Y@5wG07^))B6a%-bjELU%`gfIbtu$N6}*v6`K)jPTu9WJSN
z9g-h_o<un#-1=zdFXGJNI+SL*23B^wMq3~iar?%Xa=eD^)+U|e3#YZ$n^JP!P#B1C
z`V$Js^9sZFIEvAd%~ghd3)$PjK|YHpAn5Bkf<?H>f*M>A1!cI(2JrJ-18k1-PRfq1
zYRA*<60Izhm#LmS!(Vv=T^`0rkfF1qjzZFdT(O~2|AU5<wVf5^G_9NJNFb~YC-y?x
znudq6P-N)d;GXeicY)KD4*krRjY+CQ4SIUlbac>05L%13qM3{5?m(#LKVWJwz-eDs
zOXtv1jXxZ?oBW}S%ea;ZBj_YQVB}58lIR9K9jjMcIb&}=__Gwb3y}@h#Ldn?`i4(T
zk7p#~V84cxGOleIybvP~X1`ST!}>=-P2=kpmQ=NV-0cv!W}i~6J|IY=>ANyO7Xw4~
zlDz$?0Bif~%JD}deO?=K(p|vYeh+6Jpz#hKH*)O?v%-ZGI+M9rzj}UBW1t;JC3)d$
zIrP5E=8+AOB6dUFY!ha05gh$vBeR8w7W{ZS8^N}kb?654vi|@Nhlq-z6=w9FS@(5U
zs}C}(kq-D1V~#&$-wYAfB%0qbkfzM4C@pI>+`z$w7IGm-j-w&TOO_ul(gHQR1>2MQ
zG}RkE_7Ck8Y>*fBW#i@ps|rXyslSZ%VEGB0O<m5#oW(9__v~R_aLI;T>x7GH;F$UL
z7ejoxYI3bal(KL55i#9c^)b}pha8<8gDR&iIVsZbfx=wh3%fW7XTuPtnU-gG^=ew$
zBIKIxsXG92@i~s0oo4`+YxbTiW9-)9#Bv~*GrI%zvG}VnT$a5MN2i+T<h#0d^jx~u
z;Xm!X!lYMKy&!%zmAAGML%}w{)x2EAfe!v+uFbs*s2}C@tM2rl<x+dLJmo`&KgCK^
z{;3pS?pw|oP<&L8s=q90-6_h(UIASFGhba)cz=4@8db;w{Z+Nd<_Ct)r{4UijV}4F
zNgRR&P3#`7SOVZeP?AmNsb2EaEqwQ6c(5WyoyK3)0KAEhkF2B$xPI3@D-R2n9UvTV
zK8MrR70-Xzz)06-j?YZU0K0T}K%TN)b)qQ9<TOs#ztM#%#*F<$r>aDVHvK)o)cW_C
zA=cj|NhdWlYWsR=8_<{sS4I!|V8Z-$EPYOKgS}W1$I<m?a^wOc$Nj8>Ry10q@4AOB
zLr|OxUs-kcha2##09!<XX-M8?XTm@v_k$KdHNPS<W^xSkXjZIZI;}C$OAc$$?>zDB
zPLo?OHj%}kJ&4Dor~o_3F*5`E?mCqmCXe+*dXm0ut1!MAbv;%(yKZ?!ObGHEu`R-u
zj;MTdCp<KZyudbqrSOIx?fzAsdoIBh3&mQRJLBgd_4gjiwYbTv?K;*}cTd)gXYqQA
zamxsArLZOtw20J0W6he)nDbO?f-IkEC%mQ}Ne+s<z!)Jq<m&4(I;Td_ftsN}u8BHr
zu`(EY_CRENv&2}4<(U1GuCmg#r=ef}xi2EzF+k<_$VL9ykqd`-u#ShG|5FvnaGU6}
z$;Y^)QaF5mQ|Xz!Z4F^0T*C1M?K&c{Vk~nm{W$-q7UsuIR*h!N%cfmtL&#_#CVz2%
zMvPgQ#Zf%VknG2)k&>2VvOwS!FNk05pB*Kx?q2Ro>Ag7DdsF8dJ!guIoR3f<_Jv+7
z?*7eQzcZF@d&r|9ASE$)_Gl569Sp#;&#T&vA6yrVDVMHYFN}Y!qTI!7ZR}Gj5<{bp
zN^lNP2t2a`vJ%Nq3AXlgl|58G+qI;(;D#I{MXi*<v>{hU9l+)><RTFv7of#=oRO2I
zKA@tSM%ljcA&{$AX?Yx>VDj$Y3<hi=zWNDl7`T+3LM}tZtqnh;Iq>67`n3_5P&Ac^
zN>nHechx$7mPcjuJczpc)P}FI&3|N^5u7FttEHZlz!uTSuamnV;BsQ-Xl|HM`avfg
zhuVA#o_}>3yR{UT$8)|aEwR3F$e)D;3ETnW5rDty$IeGY$>Ly9rxix8T6sLc7WrQz
zNXx3kX_%9!=t6{1J+tc>efd%g<|<xIb#LxMY9<&V?D>09Fl6Ts|EK(J5m*czEKec#
zg(EiFoj3eQ(gqK-E?lAdD5LddN;D34+<T?PX(`iDu%~YH1sW{5DdBel^L%W-AqV^o
zs5XO#R*3=2SuRlhvL|fH;Xnewo!v9(i<*EzO>_?jiB6iuijDTl&Rp3QMabCemOaxo
zUS_LeNyVe5*(yEediRcQzBF(c1K3p&{`tOI@ZY<NUAm>-)au5dg2QaSpE`<*Xgtnr
zNLtG?2p!r(9ZXiGqcm!%sx=K?n}UxsV+rdo!zvG;sB+ooF#PTp8BF#&S36k1#B@#l
zVDKeb><-E|#8~N>t}s4;mwMggg2d=irS{6$@R0Z6kncFukFJ*qJEDXPM@<9wh>HAF
zk=%Lvx@KhM0%G=Gl!Ixs-Uy&X?X+*U{rs)B5(aTn>v~jNyF+thB1cK0Yq($d0gmRQ
zw(89t-T&8fU<NYEgf;Eh;y@ffHUX6R`f>H)(~C`c9gMljN1Egnsw|m3dm5yWxsII%
z-&SOH_vU3fO>Fo)MXDCuS0c4a+W-S8V2kvlnCc_81xg-`+UaW~tiZPVde9Mt4mRGp
znlOJZ#t4A+VVK5k0hv&R>D1j@`F$tUtk_n>czaFSL{(6`ImH$eaT&lvIQLAT<!M#D
ztv7l&R2(NXKourDUEHi8E0fLLqH*rDI&Tqoj0G=bf8J<Gbmup^aiJH-n`7x5d?2c&
z9t`%BxX~odU#k`nl`ZO6{OmxL(MeXf-&yotuUMJU*pRcU17SfoR7tdZkw1w)W{}=%
zdPSdU%(q06LCW72fqb9tkP~b#dp5$4u61$Ycp`Gj<>8S<1zHSB=GA7s_r9jQN#f)a
zBa$lr;=@NSuteJM)rqZFb`EAa9Sic@(;DD7M^qRv<#VWa6s=kc+j1f1fyFOJfc1Q$
z_BNW}WUblBEGEvZ@2V9>c{xoXJs2tH<&%Z44Ch~)b>*x$G9l<|%QMEiXTTOuqlK56
W(#Obec|-rj&$oW#xC_hH@qD6$7p^e?

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..9bf081a1c1b73d463ab5d0c5c4a5f3e287a556c5
GIT binary patch
literal 10152
zcmV;ZCs){u6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlZ3<rV5oMeLt)MdGNV~D5FofB3U
z`+Z?D-j#Cbp!fxV&-VX=iA8_VYDS|*wYP;$1fx)dRy&hlKCZ?M>h=V3FJ1<#VJCd_
z@Uy`_E@M-yfgpx~BRU(qj~Kjd*Wf>qjwgT1)fK>T`T}WV%+`lTd~e7&Qg=Q{vC$I?
zyL4YQfxi5dJ0{FI7F<g+))zDu|EI;D9BK-78Op^dNq4CkIMR%gk?7FmJS;P}fOZN?
zb;V^`)A>|(i&RuBO#)-u3w6y+ugGrdAq?j_KMVG*k=8e*_vLL<1{q6q!GSPEWk1p_
z2<F%v!c@_scU@1!ONFKoa_#RtDjC#+yiY>9MJR(YUj^5fx<MM>=iu8(A0^%r*!p8J
zRogZP;G?u!`v(>tEupDttVU5HS<3SVztVdz=Ob}X+gmXHn1I2xCd`s}Jb;#!CPQdd
z`&Am4mP(B5crC=fkj2vFCVprxvW<0w>7e_Wcav;VZva)~aU2^3MdtQi5Unl+v@a^W
zOW(Ip4^e%sh~X~}i>zpc_#W1g*;@tUiBA1md8xGmAvi$!%m(IQOFc2#5?ojfQG<0U
z8@?#qHs{1a0c+dXKu`)=RCGaydIs*x6IA^O%_ZN<;DIV|kmtQAUm@x{52=3xQ24@~
zvO2}>zpNxD?Dwq2DX9uqxva+h+_e44exwa32rJ^49pQoA<4JW%Y}H0YTxn9i0?wJ0
z`Hj-*sF~o%inGN2<r-DcDceq%9UIBzZx>HMrYbmObCBU_#0Hj(yAn2GGK7W4LOU*}
zJf6lSW!9h*^O4*{F?M695oVix7XnHVhwe@3gCiJ^OJJSDp6pp9ebE$klgcG`>I+nE
z2Gy4eUq8O(;*WmFwO!>CzqASTGL92;=W6$nhX$&haJT^)<I(Ly=slSRwkfF=jr7vK
zoOTZXcPqCG`}mD#_i}0EsFASGJ2!PF&Do9mTryDNHx}9T!Q?=14BkPf;7|~oI#zi$
zcYNR-WAjw^u&np#@8Vva=DB~eaYFOshq6$UCAtB?9xzjqe^W^{v<c)_Yth}8qKysG
zen6G*TDs#kJpmdd%o|LR{K;sE$DpneH}Y9;_2CvHr^Zmgmg$Ovm~|eInyKlsx(dez
z4hbu?Pi7^2@|}RH(H1^F1W0oc?+{e+dD1pcN?sg#B@wKiqxkftCpd$1li?rj4#`Bv
zjXC)#?zA{{>=bP$&5@7v`2XRXpqhZ#ul^hM#&?3qNxL9I=f!#WQV&UgIi}v~?Ytlx
z%wVtNJqTi#Q{si~wmsjNxf#=35i;jANcj%l=N~6>m*Ml(xH2VS$b3TeS1dqsb4mEd
zY;pPoCnCru(YF=;q>^Oj=I39aV$O1_7+^wZ#k*!1fh;1USWfh2T*GQ^n8qs-0Fr3P
zQ0e0F2eQ)RRLWWkCpkw-sj$@+lfmf1^bA2pRrRoDS8iy7d+IoedTIh@t7Y&FZi0$<
z<DJz$otm7Xdb8<PIwsdB5ejMzux0=`KoA3=b~%rV7+C7RcV+JUI+u$-ZXaA?wueI2
zH{DHGIpGWIuO5LBgI}H1Mo;(-NUjU@1dp3(-94`cU(@z|f&XTOPh5-f^|S4FC!o2o
zrxD5#4;xzI2b_VowLt7?Y8Q{~MGj9bQ^{R1P4D(043L?~x$oKYekQba3I4*FsCOB!
zzF?3^eyjLA)UDdB^s+#1st?gx>c~28N}UCkZuYJ^nKVVYkJCa{C_ITp??Uaoe{}t;
zpYp1eIG3|7AhNb+H4i4Qi9mN2|0x|lv|U%lEF>L{9LS?#R6&!+$LVuW5>K$^{k!Up
z7c~e@Bt>?UrKTvsIsutJ*Afjs)kInQ#yelC=nb$tyqlxn+ve|CVlV67W2_x*P~~`B
z!)%<o+z$5?8G*Uk>9v+1JHozfT6uLMg|JF=17}hp{vstJw&;k(A_zT;sa61eK!sW2
zb2VWfI`_q=Cx}eA|HC8b&5;<dE_bpnT<j~~xa{Rhgz5HZ%6bKyLhkC|EiNDWN*KqU
zimy%QS@|Pli{(4T2=BR)W5E>fSq;68yjy_%hgoY~xQ>HH7B>*hb=JNRdADR4-?B^M
zTg3})X<y7X4<hAGZe91MqG`!W`q2BUYn#+scE7A-q2o@r%FENrE%VObiRjedL|0=M
z?*-y}Xu!*ra0%3SajEUN=)a~M4sR9cADytuzpww*XlEmMT!qQo=m9NeMB|>bOj<3J
zG^45sKe=W)xTas+%}uRlujNu67y4Wa|AvH=VZOvEMr%;?1@el(^8B%~>lfoC!zH8>
zv!-v*1yE@!ABQCfcAounqZAVVH@Fo2P{+3IX7I1uBY09h(e2ckMKTgIQk8sVBrY%9
z{ly3&<oc5J;yzrwncQXDFG*KhpTZc~I>V`UB&T{sz&T}+@h3YA>E4O~&28n&8ji4K
zy*iUUl?T$gb%$*V(EN1C`LSLKtZhbjj9!wbZ*ZLt(ctq)KccrW!bf>FvLCsqQctR~
z?NEuvc3P^AmCIINu&J<xgJD=}LvCqq=ZmIFCGrrK^x+z9!3+)mQyQ~_Tlln~BanCJ
zV3~*o9*VPxnxSXM`(O|bllC(RVThHc)6%1Oo<*o!Q<1$)Eso>-0I38UQ;(}uld`kB
zA0aBJQuFu}P|Y=<c@pLx?bRVUTx(ADv|jP!cb^j?1|~GUtf6=wJKrg}zoV}AQVtsp
zBB*UJQUXlL^%mj|cPb6heIL7t^+~+UV~jcu+;H)Th%wY+^&+!pR7o+=^TEae(Iy^^
z#x__><!s(Zr+eL5r`o;*`CA~PJkkYwDa@pFm}K(4;5gd8M+<23GkdGK6XZ{!VHPI&
zr<;pl?ys=`Wa=b>sYylzoG>JYD<;q?aQo^s*Abr3p-cQ|hFu3gU_}Nwn|3~`AZKCC
zaA~jz$y0dlEl5l4Cw_MG7Rw>e(CAoai^@b_e_jU;=$w!WJylW|sDiM)I}_UtB{LZP
z*Pc*Stq&6d8Wn9YQ{eU)6t-*F>z_A@E0PFeXK%DEk~9UXa1?O7RB8X|F9Xp33<>$<
zcLd6+3VK<C$_AJL>?4|&040Gy59h=#7W$d>4ud3zNUO$ITM<vnKwDtFNnYO^bx!vN
zqyI+>C>hx<ge9IYzXK-#)ipttk`wR#gC$HRZle&t{y=jaOAJ2(6s}7EbDdU^!(F}w
zcP-o3f5xru^b9zy=*wK6$HXPW!Cu_`^rp>0Ws4)fWyUEvga@}ZSRE^@_k;|vr@VDA
zaa1qr8sPOy(|m7Yqv!!~C~51EeDqo|7QuARVS+Q_C^|Q~`g@`D%p@=pcP{I(&xhcM
z81XQ>q-Gxr;Nm|tk)--}Gqc#EFltj;@KfHi9s>cOdDhgUeB{Mq;|0!9G*r^dqSy{Q
zbuxIV@mF{^vf%k--+x=9sS1KccjrmI8jIOl=-lxiaC59c$O|cIr|3cOPOZ5#)J-$?
z@LgVb7eg2s#7AHcqUJ@WPiGqHwKQfc^91#M3cAc6=U4FR1hMjTfzGxMXr<EPuBZ*H
z<;n&*mDE?c)q>k8WRaeN7@SZq>xk>aSA*;Br9E8{5bOdP=pIpZ)@KgppHdqD*%KH=
z@3w#7Pvtzy(;ojWGd#H{dHHhA4(=4#sj!F0XBd`@>w8iF|5ZKgby`+aAA@{_Y2=(B
zg$i@3+d;j&F&X$!_N-E4fw5rI;vWAG?PJ`*MZpam1m#<9q=s8_a4k@IFQE37uan*T
zmSN#`p^(7V6sT4$LSf_z3-ZdGQ!%T&TSacK^@c&+2aBxbrE7l^C5OA!wP~Gzx_-x7
z&Z^y2OeR45KddH*wtl~8r*hXxpjV&gifzrJkH>{cW2kS6TT42HUo&>^m}vfd6fC{N
zvqBfiV{h7g)72G&k?WY8?e5h~XsI`dY<9+79mWOg5#Uj5)0|)6J3N$j!ErhC)1fog
z;qMOt5*|i6pE|YWIIWvB^G@ZDmw*b1vbov-!Axh7XsV7aNX!iTEZ77<S`DMwv*OlV
z;e#|*9X~UgHq0jekecoqaC}UxU>nBcBD#0ffhJU_wXDuZ+0|dKBi=iBDBVmGQv7hz
zmz`G>Fp_lzM0Fa2%Cfy&-d`pU(sDCGac}cAEC8%->0R~7(Hf({cx-Y);j*Zg78(Zz
zePPe>`<WB+-?)SwsL0u?u#UPwjN_y1^;`@HtG%Nl@5}xR608MY-r!tgQotZ0&e60R
z=gg<hiwWK@f`mKiQ5lk30tXKd5w>ywOH{nVRC9K6E_(&w=fHb)eZAXgWP)f*>Gh4g
zD2~`Pf2IishCx~G;{(+L5mp&L{g4--_J#|-g=wBg60@~EX;=a`p@5+IzSZk6Oa0%V
zVL1x+!{Vn$YY8xgQ_MmBMF^w3;@UOu>s)p^@Io%b&niLcvU-Xz04X6f7bHl}u6p?_
zPpgVJb|ftkRu^zZ-AqD|{8{Hs0OdDQSL0UeRnH<bXr6rh=8RG%|1+kv%egZ9NLxTL
zqV53{kzg0!t0u}7Oi<YOM3zC&MX|n5b>+NH!!=LUBea&i+xVgS)#j?68Y5VF17oS#
z=-%VuF7O!plYFomU^zIBr$V?KE2Uh7ux|end+!4Of_igKbFEQ)7%J5<p8mIaE+Hm`
zb9Md+Jrc93C5N-51Gatt_-6opg|(S&*9fhrodYmpouux}x<5A8IACv<sr(#OANp}I
zKHWK@aoiIapKvIA>gz}|jj<oL>oH{ho9|D=zIX#{6z>#@fi^URk~PPVhDr014VVJ6
zQ7~-BjN5njmwVVGBx0U0p!bIF+*zNTLSFG24Z}vC69I!{UdQY*-nCcfn7XH+DzlIb
zE&lWV5FZrh@Z6%tV4Vo<+)%7=qyjhmmERysQx7C5>w4d?D(^MNMGYW4@}7=atQJA-
zebDlXO4BlWQqxI=-L;3OXfE>GOZ4I2z<WZE!(v6SxyoFR{CVOw45b9L7&V^}36}ue
zIL<=B`^Guo=CvNw6HIiXac`LRws8JE7}WBw3qW4I{I9~GkH`u$qJEJc`Tw@4FY^!w
zB81>Zm@UTrq1gwaJfq#W#4;1!r@}iy$B5;$So8ktM?ivR4bJKzGu#XR6c|`!8Yugt
z+KrY_$x4H$yuYl?!9=31mS=v2=(w#rRm1rV1$QaL(dPglLrV7M6YJa1Y3pX4sG1sK
z{2XbAvu8#X79laY%qtBbRtEw>tFH(}d%rH2=zznXC}`N&_dzack+<Nk@>ra6>|}sv
zncvB=7>u)c_;dW}Ip$~{6w}tT4Sy`FKlGiUmcblX+$6XIA#+S**qASuciGNkp>$gC
zs$kGb<U19vlguEw(4R&FSFu?vn<G>kjivomjp!rk^`L}B(z(ul9ECv4c0?NeB`B5`
zNx=Y%J_8QZ!WN>)JRMbllK$Iz1oIyPchw}j&u1I8*}xLFu7^e)u#!}<pwityy0^jX
z2)Yo?98@p_*l^CJwk%AV5wJlVqrLwa*Fy5&IBg)8_U@_PW9al-l`TQl?G!jDvkqZ8
zaTnBD)<n~ns!}--)jn}AAUqObsO+)7h8OQ<kz?5`UK(yQ7p;e7a(7x87rRxp+US2e
z@?I557^(LwOEn)(lzFINHa}Gc&bD65+}gPeOOgvC91r)WsU*5tQHi@8HB7S7b14z=
zD#t-X5ei(0P?I1;t~#tLeR2YJB;f<Ic|&?GN+?WOa|e%IkR|-WJ6F@oxX0ds2W=jS
z3a`^R((T__4&7%aU9qyKnk~P3U8}5#DFxTKk?s)Cc+}RZ@B@+vL(dGNk#g>T*mKn^
z7*6XTn;<{e1?0P)xp&@)7s@%RN(Whn4TzH16iz(#9*Hes?NAtx;M#p#1xas=3TObT
z*T}k_0$j9DYx}#G1?dpCpRPSk%te-TtWq!;)Ooa&0r>eWC@I4#uE>+i>ZZL-*M4jN
zozJZ=vrTy@pY78$Q&=gx^8Yi-{(0=Ll!}Bm$gwZ%h;$X&(#0FNEXVW|wGy<p95WF$
zW0=)TD|GVty9ONDvCQmH?eha+_Wm%aII25O&Drl{cXzr@ilN>SW0;Y4YIf}BKLAHi
zNo<!+0XXnBns8x<wk=>F(a|%b(MM>4x6wUHf^hZJOh!x_o&ND805>o_8qprt7ydfD
zcYRc$*CwKncH#gv7GgfF#`@;*D}|}}Zw7qMK17yJkqOd6JzdzMHlD}P5)#WVldzBq
zN#(<y?8K%}-QOdQ#YAwZH7gJ<xc!Y=(rtjNPyq%g(UJwAr4PO&?o8KgkJ$Hj89QVB
zG%_Xl+YsqQ4W*~UGSezS0A<9Rj4;sSWXh}ERJ1B)sB+fT>c!jIFkt<M&Po;<c?wE@
zzH3dkb@Uc!Zc(pgaJ$1EH}M(x-mdfC8E#dGTrSRV)qfPyI-%zK#%$6;T^`cw?Q(eH
z+H@%bBX499T3ftu0FG!>y|h8wHE-YU>dO=8IJxA$Pmdm=mzJY)d6B@|UetIQmlR1e
zI<C!gG%&~$B`f)owqh`3$6pt9iZom6J+3FhI-1_c&V<VDYarXoUtpTx@8cmM^?yH*
zDx-P7!U^QFnD)L!=k<AQ4vrDef<{5DfqK!mjL^!2mR!Xv-%zmWDO)S%a<T%spZ5$)
z*^uU){zb;U+KNzO^EQsYtJO`H)G*7ZwV^UC!$>3QgpNO6v<TgpBhbWeA;cv<GkVDF
z$1+Mng;+`njM4mjt#FxQanH6fREz+kT-jH=(E7*%6ed2|Y$^BogSWIya5OgeZmNF!
z#y<Qz*t|_D@Wus4KGCcKe=*}_Q4Gbua;b$Pm;k5rW<JQ0#OHTQ)5w8=oONyofm-~&
zaXBEt$z#k7v#fOnFrHr!#@@N9U?U0rsV3<;{THD1S}59pitg{Js3{s=VS+46IZb#G
z(~cFF?<|xOp-Jy0){vJv8?JjQv6KRm$IMewy^nnwnotbU3KaS$OqTG#Vf6WStD2DL
zDFf=$d`R3pjncRIem(=T+RJwz>ddPbs1>lnY5y>O<>C?)GqWw2rz_d**eizcwpVXC
zzNT-FyATtJ2l*_$0}ztGynNCmm@ey)#+(nnDT8Eq^N|T7z`uacc2vf1WFrX0TfCls
zIRHb3;c+DIsq#WJYU8-M-|uuq+}EZhwIU(-Bo*@J`{*|(c|Nhyr4u4p7H2Ks#F%Sf
z8K7W*_OAs_AKJR$g#d%II-xHlpsg=af-Qh5%jOa0DN~NyS%m|~GRvr<jlrmII>Imr
zdBIA_mYcPYy}kjlgX+_XqJ_3=Lt$bRs;cvmVlHPSVeM9|Omc~y`IPnsx&?IlY|22j
zDij+Vbx8|3(26c7N~Tm^-Qr)c7OAd@uK>dV^4JA##nXVN_Emn?NP#n$Q<p6Tts)Yo
z^lP-xLjkG&_jc<-DD1VV?IG>N303GLZPf&;GeN4S7}6PsfQK}2_m`doj_uM7$eP`=
z3p1~nqe%{&-Fmd#=<}$H^Z`iK3*2Ph$vivcjj6&r1j`4sfP<^=IZwp<&QhlI{^2*x
zem(5uOY|bv13}6wtrnQ@*^qd!bJk9o6#JZI9%hafdcJB9&CvqioNS#Ns?w=lz#riM
zA&>CA!sCTSwrFWH=Dsmj)MjYzHhAS<&MBkE6>eLad`e+ivJ*hzLSkhM!R$hfZ@FTS
z<Nv#df$V2xifSD4eCGpi8K`unvi$yaW0brhoTIB1L4nU7JCgV!l1Q4ReaP-=^-Bj}
zBa{xnwpR>rd=OF?k5RxjQH&viohBCEac}$6)<vvte-LQ!?3zO5&UT48IMbok(=8HH
zQU}<;jn&SD>ItkdPME1{Y7*7VnnS1!26@*53<Z3=u+1FQ&b3f6yz?*1%%x34c_vo@
ztw%u*W~47%i~qad`ZmC$zzYj)SCVoJz0BxS)d<KXK87I=JsnP&RTbMA-S_w;q28Gr
zA7OJ4DTFo>(=Rwl^QG1rD-xNBu00c4Eabg(p0HO>$!<=dN6o8E+#04Ntv*e`n24r8
zy_!W|Pr#+}-^Tmy61MXtIkWfjG3;_N1p5JDzR^e`ApwK6fE*`Kjt7u%3H(RLU%u2b
zqcwOhAZj!pra-M_DV2In_ySiyLYi%4a&a=Y4Yy8sr-!eTf5@>8%B@xe&@_f2(q>uQ
z+6x7Vw&9&!{FsJj4PzZ6-=luMqFBk&I{#xot=qnJ-a(WzI;QKV?k<1pX5leV6XyFT
z^7jO89pTR}Zij3ym4f_T{m&WUEyem>pz!yEy~-#xoq{%14O3Dy>4HB1Z<1SV)p4c|
z?S|9Y)W-$~2;TIewbQ4!-~%-yCjG0yr>I<JnFPah6qWB_bL(7E4-ZT@DO(;vi3|V2
zvxU3v#oMt)PiA`0VUXLtwxF&HMm24cEN#~OdOt{<gDjWOe3_B0h@i<=NQHW}*9Y>d
zsm}QT^`l!&*Doa?yRS!BoAeAE5nq24#ClH##Yl-R5RpXz372&Z0I9Eq<)eVyzh5*!
znUJJN18_7rYZdf0D?I&QAAbR7eDbnW2cy;iXiX-*-dltDgg6^*<2TTt3r?N+ngPBX
zG8JC3^b*>M%w<6BTZcIXXA(h_5SE8I;(`s2H$ALnx)IWFA>q|2y3HZGJT5qIXEJBV
z?yVg#)UB986?a}|d?*1z3#_kDm+$1OQg|>gH8Z&2t(!OBi<<pyU)(-+#1<j{ak55c
z4{vc*kt^h}Y)|b-m?CXddY?sAQ6oN4&RL7fr&y=gkZZ9><!5hKG{=WVuv#6%L3*b{
zF;uI<kmsnkjqpBWA_9jv(ZzLkcb6LAw;Uo8UImwss?}-rScCQ!)_!%1rV$%2Q3l#1
zYbPt(vb2<d=uX}L69;Z%BJ1d<(s{tr=QfU~K&LU#mz?r3H%#Y}KlOk?1WEI%!m@c@
zIP+9=ZW?UgsIy_}i?bLE!d%K*&#oonCTcQs3?rKbtbV0#aUuobls^qKk-E-^l;nE!
zY8FYs*g(g7$wH$T_dzq(A0b(!{6o|Xgo?-*+m4Lq?Kuo?>>F?7Yu4amr`iXEo|aF%
zjrl4Qd&;>SK4C9echb^?4s)E%f;{bldC3%76DkgjPt4JfAqA#pw1Y1}s<Y3Om&MN>
zPL)LsO<flc=9|5$voE6(1zta^{`wZFsJBYintP+@azaO@->hpCSnPp??7TSJ8$4-p
z!d(Z$GH!H_a5Cj3ZN2mv9|B$M7MjOL;Ui&Dgf*_vG+<|$6+3{zI2B!_`3rWF+ANm}
zuXvqO>VJaV<c0FL5u3gmG8I^0pygVPF4r*YQXWV8bO}u0r!vWJx8ckKWORqQkHHW|
zNY)B&S9)(~&Ef$%j`iO$v<|f&=uqqb34Y>U7^`5PqISL{e`sK89v9!2H(fDYd+am(
z>Ej<4td6b}3(~)=MvbYzktEf4{C}L?s#(Gi0#!oKsc35VLYfrUCi+Nj`uYz06Dwn^
zy=v<~@Oo*U;!H{h1Y~(%Ny0{Fk1YROMfW&`Tbx4MB|cmlk}W*D-!?2iOvuV6AI+PI
z=us3>9)(MI1W+~Tpxom0U+s+@F3FSra*0ho3m&9a`A6bR`)2Q(;;zDq)#!Ca49orf
zPR+aZCWupJjTPSnawUg=YaBNoU9W*g6F$1w{&=$qoQDgw;M1Yd>|r)~%Et;?OZ}n|
zu?z?;;u*??0{<xp=S%=4CZa2I=fk#82F3m=@nTo!(D?ueZn&(}wV~R+NI1P{9^><I
z?C_sa$JG$_d{;5~0SYTx5yE=mCbCCAUp$<pm>T3xS^ff$0IMb1=6>a(S2yN3I@$RU
znH`XvJ2%)P%#n<1b~s9!)oWmR78*NsXpc9HtnI$$pBVVc?wW2&;TQrhEPs_+)pK>H
z)ipNlYbL_ZLn0`}8Wrx#4fz~Jz@8Am+A8&U<u+h8^I*C2d;*0rz}%Xvc;*PMr#V6W
zBq7<qq3Rk^O;=B+y@IL%m>$3oXdeddtmNjIA{{X<bx#Iz>rqiac0apGD(*l{sap^R
zoZk{t-<n=3B(n<3Fbr8RO#O&9w$}HbtmkkF02oLGA<2-F47E-(OmeqXeq2*KJ=p-5
z1}n{<#7ei{6m(V&O(40MOleVR=z4w1lJ-TpXI5K&D~(3`fhMt_<CUasc~5bxtpFl;
zIu`@Hz`+{&rAr{>zGhLGAHUZ!8djg)1mq@S8Wa@qW_d5V6WP_K@K*%c2UuFAy}O7q
zixcXO0&jV{%j-HWz^Y^0jM2Kk#C(btkm~fR1^)%-u~~H^@6lzj!>bxXHK>MBmvRRT
z0b-RJt?J0bS0?FB#~U2SO;)$Mu(!?Krxef-Y!rEgoUo?!mUH5QzS?bUt_{9vtPfbD
zJpP{Vh_aMMfpL>Ftf05VwZJq05a}O%vJojA(CC2@kTYxYm7d<`@GjK{@m5=d347$@
zm83*B!B0|@a~vm%9rde46b(25_IzH`%tKB=Of29<PV5UPZ#({#=qP4(3>xt&IhPbZ
zSJ9#gnI@G(@2|`irAf(w%eAvMr;^;!<bBddmjT@I&{7sRhsF7wSh|fiAdox~1zPW<
zZ+JtrkaRw8I5PPsarq+`Dp#d!h#%zFL+&RcourznAqmhs=VZ-VXY(lfIi47FmS%sU
z_XVnu(Nw+h3-$Y!J833kmOb{;KY2k!xr>zGQ+j?GE2IIymaS#zgi!hmewX+eJAW5A
zYTeb?&ig<B*_o*5x~DkDiISDR6LhNN%NhkL{e<$$_{^^$$J3ase2=fI2Q5C|<NOku
z+M9K%D+vq#f?pj5P8Yx$qik{Zb<JiKpp&<une!`CW>^no7EjeRWYHOb2VMXue@Sdi
z-->Rf+*E!n4>Ox8<O%u!Gw#;kcz$3Y_$XZ=F`*5*@VSO@fCylGtaiD~qQDMAb$<95
z*}FLYBi|;m^Q6JH+SsYz_kCcwEDTAkfHJ)dkm=lq*I8BsGw-(F=&qs#nSl5YMUQo{
zLGHc#qaLe8F$R1e?yjLZOocGZvO9lF7au>~CaG)x+0rRq5S%#PTWZ{gbs&6)iE$R=
z)$o7*EQYL%7DSpfpdQ_vPq#zE7jF2yml)>-3pRFO^>3p_OYOpAKN8-Fs>JpF54K5$
zm%S{pX#ts1UP}W$RQA_UX$64EiG#DOQ;Et`jed(Yt{X_rd)rDy6w_=m2f8)b3Q)~^
zJMq#kcxq0e{{#=8O^5%MJMU@iDWr1paC-mH!6Bp#>zUf8)=e8y<8jdnyF%^I4!#f9
zSh054?;RM>c!%$j4ilb!?RJAVGiD@_=r$24S9(;LTO+@`FTu?D@G+@0Ucf^sImEGc
z<&4H20l^GF;+MoY1q~&n)1o>S7H8(nJkf78)a_E?D;VX#O`~~6*+#a?n1Su^xsbpr
zA)WL=x2pN9#}^MnNK-ZUQW2~27NR3hLJaIvgfKm0i6^ZWnZD;9huHd$?4Yc;PV?}(
zz0jRqJr7ojFIb|oNYa;-fy_5nG-QLQRSXn12n#g8pWbzJFw?hYi-RGK)bVuh!lA@l
zv4Nf=y=ifq3weYS;p^KdK||rez>cq$G=^C>F%n6@tpKx{`C}9If<`UTb)~FUN*=ek
zD7$-bnFxUBNBs(G$Ddv88{lT<XSYLc9%X`Cis-C7_6Y;c2zYLd>Nk5qN25qrhsH&X
z_+d>h2Vz;1f+&zkQ8jAuPc-z<L$q+$F+k2#rOoyhZsVmpSF;X&If>2k#RjzV{fEU(
zW~P>|abwKsu#VRrAd7}*q3*FpSAj1?d6*gibOzt2vZ+seCDUXYe8|Igqfxy*W|+HN
zrrPO)y7y!iC#xyFOA({~>cQm!lrotlY$T!qd6p)JGj&-%OcJ`0qDYy@hs)oq)xn;O
W0xWD#yCZYN{L&4<xRlS;yZ==CwXJvn

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control_small.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_host_control_small.v
new file mode 100644
index 0000000000000000000000000000000000000000..e092764a5a89ee7192d91c6815fdae823b3a77b9
GIT binary patch
literal 10736
zcmV<MDG%0*6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDxrDd(|A7R^;0a?DV
zcX=NyQO+K#tX!l`uqkl9NZI%G<DW1W_@|+(%W5&S(%)@WObPgm@~;gaqpf%oEcg=E
z)}%mJ?eYqt8jw!PKK1l4q{#_`>MZMwEG>}VFD~3@%HWx>j-8j^e6k;)4I}!EgtYyn
z6R32ZH$NC2-4XPV9B8J0GcYQj{SOH}3RZb^BB<&(hmWhynRHpZ-442QC`RFcmL<qZ
zm?_&%PXmtO2Rb_;IfUhJhZ3TqodD9$^FHxTZ?Kwh)|^&f#;rk(&W^-=bZplS05nYV
z8}yi_(dD*tL3?|Xa^alkImX=@J;&m}2=~k?URrM}<b=-F&&Ra<s6y;d{vJ*`f|G8F
znU~$Uot8Xp(oDVar@h}l`KF&4FdS>(%K2aGpmkQW^w7(bbt=psG`i;}rc(z8hz<=2
zhvY!#%wc}XtcmlvyuEWX|KZ!hVv;+YI#g>X+}T!*a4qpY{lF*I$ocFb3l{>|*ZQQ&
za(EEIYHIgGeoc|))O3Oc5F*M@EY!&yj*D1a?MTKm<3UWC3I3M_yd(DOfyp_VJkLTc
zy9*HxnDu$CVrt?G%Xe{L4z@oJlx-2qaA0YHlvD>^P&J0Pz7N9*@7<s8py?eP*b>8m
znN3@RkE66ttt4l1#ecN^mm`Ve48y2L9LtZotvqhv>hZY%-0ka&KRil!|5t7OSZk67
zqbqP+-(rI-(c*Qe!*STKqV(@yNus>k<O-A6Fc}sc#$O(V#+y+>VN}VoqsgyoTCS38
zC|^F4|0xSDJf3cWH>ivs0Eek8s{zq?(<Y9Os&g<n&~&pt7z+UdOzMmRo-zN>&8x<7
zq_c*&Jq_vWEB)AKL`Mc#lon)Se9dWy*RPrsq#iX!U`tE|`<n^O@X7p!7V;Q3KZk;Z
zNBp%B7@ZGbi1&kpWV~^@)6ePf(`Dqz2cwI0{gOQGBw)pu;l}|dbw13{(C><2&D}7H
zuSbcF0fn;$=jjFo)<h)r7$7!DnHjGGusytNXQhOeurs`e7x=c)%!d)m9n6S@Vl3`I
z5(dye15p#9rVF2(9lC>5^uGQ#NIiTfq&HbtQj6HDTZ~od5NKCr;6N3v!v%?;AC%_+
z%-B*PeQ>NVxUuVTNv4Pmif!gMh4=OX{Q0Sv|I3|+kgD%n)dH+W5|XUgWx@MRPjKiQ
z*{X*OVcoGk5I+V71r#2o)y9JIafNfc=!?I;n_@g8f!}zz0L6B&`GY2$^rE5feouee
z6_*`5Od^-DY$D6wE?*_g*_#l`DV%+IJtxp&>$)*o`ze7e`XwTq9I$ds>x)1_@E+vG
zyaB&O8gY6*%%JV8wbt3kl3Pr$%U(s@UrZO3#QqRlEOf)n9YIVX%~Mc6U8umkMTB*n
zEfbvzjXl-$dxXfm%<+l-CtjfkdmQJ4ao19mN(fHyP|VhX0z^G;m$Mz#Y%RRFg7N)!
zV^Z7AB4-|yew(LPS4M&oFO}N_78E6K5sBdKoQK|Vb^_gcFL|n=Xvm5wud2>UG|SD^
zHOB5yuEyox66LVFp^$yb;^Rg_0~m2^BJ#V+EuTpb6ako<;Ol?)UvSf*y-J_Og#G5@
z2|uTZlD+P3-mriVPa;o_1}-&p{fIldM1BbqWo`@nRQPgMH=Fu2=zDM%wKMuVB$8)s
zy0D*p6-pMBkp*|R0e<8@P6eGzzz#p&(+ev?s?MV7GK`)s@2r32lE*U`ZR)Qg?1fPo
z;gdWX!^4d`5FV1iUcHhl7ltY0fTiIqam^P!(*bs|Bo1Hl(+W_fgG2Y2?{49)YR<Q)
zH-~kWjwhKuBMie9ZgI^s^|rHRmz=ob?DLhYJf5<B2$ce&W~<?K<dRK0`>~xj@$V@;
zwSt78#-zX1Bl1D!VCsP>P<X%lfu%CBz8PNMi%f~GD>OTNR4u1kF@iA>F*PzbR_XkR
z{!hdsgl1`Ev9qi5s+Y`;A>1&~2P7-K<?cn?rbS$XUQP@)JyFU%;jCTzT{~u^K1Z^P
z7B<_O?j`3HX74t^@HjHfiq7~<b@yQlIS?id<j0CFhH#2CrXAS(Le+5OQ%KOV9Yde7
z5H`ZpLgXo`0cH1RHR&RwWoYsvW=+(D8*|SA7PKOms^Nze;(^QTOHh)7_!4olpCiVG
z1nh2NArR$OCh^6MS#2P2rduQ#;YdrwXq6*qjPL=<VgN7|-{YFF66CD-5kQ1KWV8ke
zi<8-j0WD>P%6LkbyE9NjD_mESERfHofV!4RWfqc1@JN@yp+xN4<tW{vrb>~Q5O2zs
z#VQJ-syHQp*#+6Nf$G4#>XVg&2Zf(7GWYU|7cM&{0c*w{&_B%4{Ymdlya>cJIaa`x
zw{h&^k`oIeSt&+B#{8}f@p%~KcR1<F<Rb)tVEwW4V~RXdN<b?DHWdTH5bh`4Hy!LH
zt_w%h8ITFEZO`OTrEYqboAx2|F8G%Esugh@>CVb4f%Q9VHE(PB-fV{ZiHR}-UDXzV
zZQB2eDoa_cHFZIX$R0GyfrruCgp^U8cu+Spx20dl|H==NLWV^}gJT~7+R;biP!i;x
zNi(+73`${-p3RYiCw(_@Nvc&g5raG91A^K7RA>e*|4k_QGc(QgC+kW|f34kT7B7~^
z-VQY5Zv)M_`BxJyew7>>QS;~;rrNB*0UZJak_zq1>1vkj%s|8>Z*FS^Sj7tcU}?q>
z^PKRVfoN1_=ucmloyT;&;7$W-dRHM0XCmII;Q@ldOw~!&-MB!8HtCS=aIAT9D7<p<
zi8;R?&6jd7W%`WJt~#f00}{s$4n(>?f>V3etM5jBMYqH7B3T=3-kF}!1P}`4_7}Nq
zbXV~SiXRVOZ(uK`5zi|Av8%z;^txDRQj$1$h5sT}umSf{7;4`2;!e_awq~mxcEBF@
zQbUj-Y`1|<nUEI!`<zb8+J{oPj1vMw$=nWVSc|Sh{3+lb7^rnax@X0^MRN953{rBh
z^r$afbb6;+wz*gDIPA9WSZoh4%0uO72yP0OavZHa%X)am+=hkbC}wh0g^o1z@6yK&
z70rp&B>Wt$s+s%#K=C5kqr^&&=0l9**}GjiD>0lc!E5e`!xh7r=W=@{L{>3@mh{qr
z4FyrIY#6i;i*Q0^ffuEWl96cP&5?Y;y)Rq-8Os9yIR;ExQW<WgL<!akVSw*x=IU^a
zj>Hv0WBX@M|K~a(j!t`uNiKUZvE;%ZsT%x8w;Otkt`?CDiw(oykwJ6KqSmb39=m%t
z49JpR+B*9bBctPoaTgBXpErO;7}l`i+{$JTG(<;F&HQy<B0+P$Yvd&8fEeOS!f8B@
z9~XR{-1LHvdI^lC1y~UTB7EG!p^@Su)+S{Fmmfd*EF_&Tdo@T~<4pEshh#x!RgFW8
z#bx6j60mQSJ!`6}0(i1;lxkiszes%4B^&U4Hy4F<o*o`KPEHtsHW*0vfVDHyl3~*7
zLA1}>g|IE@y`uu6ReP4KkRrfmSwLP&RqnGTY(7T<&(TiGE=lCjP1g*vt9Z?}UVlUG
zPlbX-Vy;u(5`7ksdj70JiRQZ$)5KQBzhrDA?nh$A3eT|wkIF66dFlo!&O#TysUGsk
z#dK1sJXpWiZ+hFNR2J4)QVFioU_Xk9)bZ&$%$Ol2dct4O%Fn~eD@a~S`0y+I=&o_L
z90!%P|9cRWHMnTxmB4?jtDej41KnT%wI|0&6NDc!pqGg{+c|ChU`vQBBJFI9lIlg*
zIE44d6jS)->>l3+5cukT8uy1n)8$!BJDiSZUC8g0rOFQe$`d8rA+WUDrCsy97Sv<+
z1_#_drg_C)5=z}tpsrgscVC3NeyhFEW)G~^<Q>@)gKzZ=#pf5EMaUtXaIJD;KIz|_
zHp7<DYA0SH;|IY2))E-*#2)^yy7c>W(}io9cFL9Ye0L<%cl{!{Sgd&2s)IF%!+m=B
z=)ZmVQAq4lbI?~j2&tRvW4`0JSkB~*f&jsXb7t*mFw7u?i-?3t_xjcTqP2?$rmV!M
z4`k50*V0(~s?Jq4Xitk<;TT-CD+KZ0XR}<qQirt2@XrJY$(&ReU8aB%qmAi@YZbIe
zn%3?Ak#zh8@qt9|U+5EeM_CxqHspyyRcd>{oNR{x$g(#9asB`ZLoH!?K727X-U#=q
z?HR5_{Tjey>zN=XQQ&Jr0lcl=1X^b|3Gx@ydnxP{myWAWC#i&Iow$);nPLpCfg=h;
zJ_Jd=?ikA$jN038P#OZ55S(~`q7>&RU==5uvcC+qFTvhIOE33wO`Y4{ZG3H;Ch1<d
zY<Z`PEsrBia(v8Mcun6VQ(=sHKET6Zwux$)i^!4CG;HpWmZgv=ccW^IoxB#h##c*Y
ziVoH#KqsB4RSQ7)ZLkU*D`=;ZyDm`m+xESILi>LH!;OuHbpI_(g@b*TV`oDE9WP!K
zu&T-chZOZ`TIRk<WPqYCD#+&51|AZsXyBEkpAeq>b39RB19zj!Cs6OfY|StiXyf-r
zl#|NPXW4*h`qL5glRD?3dzTpvKScX(wleph)eqDHo%7475#9JFDv=b-O`PP|^OB}u
zhaxqzAjt9|t)f0`;oSl2b9m|iT{OeoLfXegMXC=5v!dtRc$My}A}QiiSq=?(%y4g*
z&>WTRLhE<>gw_33P?CW)soviB(cKw@u3?6fP90+tL}b{n9)2zvYdDh%XE{K@x^N~L
z2M$_TMcbO*h-Fn@8e>2L^-epCDwjn3lUzYW*q;Vv>JO)CkwAB!er(?G+80FeUhV@<
z3dd#Gv23!qXmqN}gB2suVu&lXD~z!4#a65Ajv@V0prVfN{4yX<s^x5fzY9=*4@4z~
zI}BGjtT3>>r>MejvS>I@6v?+^o7o|%<Wf>uDk(k~R%spqJr1746hAbBMnv4!RxPi5
zS9)|ZY!9%v^a(1lqOjU0cvX8RL$JA$T`7w(M{(~Lye%?3vae>Dq>N<rI*Ky_lvZU!
z5cUCYwUHUaV&2`nvk-`eI4k~uy(}t*Q(Ew{ha)!WBMQO~Mk=#e64?4&%3E)VJc(>F
zCqK3fpjMmYS@)m6ZH+@a(?ss(GDBAWyR}sf+F@`Wb{Vm<cj}UvGeECilwd9Ld`3Eo
zjovg7_$n<mFnUfn+0gMw#O_VzePkz9de*vd@?vP;o&yek#Fv|>W9=<V+eIK?g#yP(
zS{amcm=T!3GCSN;pvKjT6H{$F3xPT!^%nA<2v04Vq{`Th$Bn}7V(CDn;TxZS*iz4^
z$NF^ZDq`m!IP(0TEgno3xqSm`baLB}rukVU{8K^aR6W=Ts#<t}rQYqi`eAyyn=Z|A
zA%C;RaTSF>F1103FDElJ^1_sPwAO3%J`y%wG(H(IOAM0j2%>&^I0jZ*qlRD7b~_$2
zf23!W5`aRaBMQ=8;S3X5m<r-1&n#P#!*FXeg|b*|948$2*z}*g)i?Wj?w;|d3W@^6
zh`iDCe=gP|xiXG%pDoES<pWg5RiMG7ec~u3_D4LI8Qhb+!)=kDf&#)$ky3ZE%s>`5
zlCvHOfgB9y7D-ilTr&_+qGL=E0HEAj3QWhr*|TDNDz7y1yWA1+XU#m?6;*#1)Cp-K
z;6Golh@9cjid&vJl@1@niaO*XDoK35%$GErM@v%{-@Y!boen`cToVUR?YqI6S6-sy
zSA=t5Uqk5GsfEnZi@^70OTe3*mw^lo$TlIZWoc!-vak+J|1hGz2IsGEF@qN$u-1@~
zB#W+{@st@DB$DC-!LXxREDvi`=dJsf>M(cY1y<x9sVZX3Dh`_uZ^AwpnjY&TR`18h
zO5~X`IYI>Q&a*${ymu@$plsu}YC};U6?5Kig-?Bdh2=^b1ltNKw7?;ZyhOVwMWzWK
zrFVX6T}#_lT7g#V{5d%5n>gzyPjZqi-N(mIxx8H)s5LSH#q(fxYRM@7dpKag53LeL
z3~n64m<)#13Vdj;E+n!8If3(*aOoqnO-n`kp!`5?gh>`zrh>%`WI-QvH?9iJhX^^}
zw(SiDtLVq$t?(prn)iQoxGNDCT%3jO;?vnvxl8RE+#wb>?4O7iVfQr<zcoP@=+Q>Y
z5TDvu>dl&0)q}(Tf2&vJuko|Nw@7tFBrAKfZb~&CX#R&=lT9<xN61b44ltKctWW;k
zl|nWB<v>K^C_6F0(XAl%18@g3p1sv7>II6X4b(=K-ju5@t((inKR{5<@b-_+1IiY@
zz}Z$Jj@k24nKpb!L>2deor@dNUOWmR^HXp~c=KDXXQc0s4*vYe-}NYCFw03QuAM=C
zNGgXS?|8UANYGcGQXZt3Z<Aqsg}hW^-7(lnXxfMcdtDE?QDHQMf`d&-QR}PsWI}Rb
z>LOLSM?f83`8(Lg#b4WeLYjfQHI+^Jm4JIt;w_CWc6Ke)sh(K!R)Sye=DQzw?B%FI
zVeoZly_EZ(2g5;w@NidAwt+rZR<ksm+SI?s;;|NM_SG0=>biuSNKdw{mzmS`0<h*v
z?ZOey#~bUY-F)b75r}a-9|4~}s%90Vyu!3IL)yu+sz>-TX?5wWmgDmH%OO4Ih+V?h
z6Y~@l`!a@+<-g;lK<uorFpqcIXWo8p$Gxn~BjD)FTNS-O>y^wqxqrzG)~SQ5g^wGU
z<L9Lq5_uS-9TYaOh<7yb*`dj2Y}9srawfb>u&7{P!VTv~8$=|1TEAypd|F1UT^mG;
zD;&p9GP+uy&70<%bzH1dP${Y@w8NvDZKY<*n;m%vz$v3r<-(=YH0x&~e)X_U)mMlE
z`aB2c5pU6Zp+QTI7h{4e49NV%#61^Bdl<zS+<XjJ1&U|BMxQFj80|`{tncU%6&DDL
z<%IVdmz;smTGug2QWp4rQ>!e=MN7HO%pdS{pn#o%zd6#Tu1c(g;t(~yw3<Fiq~rIX
zt<S@j`7zW=i3a)m&cqE0pmp7+$3Pfig^CIK87Tu3?q%q#SQflZximQ{q4!&-TGCz0
zLwto)y=b;d)RZab`$C;v3h~2TjhzC|#t8#nwWZRUHieyEy%`wp_glHt#=D%*^KKMP
zeuKQxFb*W@1ip#W;lXQLN$Ycv_G1yfdcanBOzro9>8fc0B&=FI_{Hn!NpNU#3L(qr
zXUbV3oo?&@7*11Y34t8d7h7CTgtdn6r78DE`sy4|c@ZcCH`h|d|ERUl@rwZZD>w|7
z{ssS@0gv;+j1>A0B+46CSA^zWdFbbt$?%NyM$w0KEYj;!SE!Z14*Vq9A#Q$53tIXq
zuZlpTJ2zUh`WXs?A@j}=XSq#5N8ZyFQvajM)i?d?yDFXmcgYRKnA#_=#PNFB2uCth
z#;eZCR_6|PhKUca%6Qu(4!%^pZ(zaz#h_n!83R4=e7#BfXwR&SKcQuB5n(!n%ppvE
zCbKj$@7*N6S3q`)b62MsmJ4!8tdSsml5i^lZ0^VeDnGJ0za#mmI*Rq10E~rvu>O!@
z@h-V^ZPr?mltz0P!cz~LA8U%|Q+P}^>6xq9`9ICD78gA#16%Ng5h^<S!Trg2kJE7P
z#M0KKf~odKZ1B#C35$)mxEc9qX!K;F8@2-^GrYA>YmFzlDN*CKxc;<Q4v7eav$~yM
zz<Ak${xvuivL!C?IR-C)23K>5ROTZ2Ls3qBF>W}pL|u-qZkM`MlnhNmXFO_KN+%e+
z3s9AkJLf@4)z3l5UiaTcDDi23IpuvPsJH^S4?#-9mQ(4TBl-Vh!MANuFPNO|B}Q)!
zC3}0Fm>Obi7)wF9djjHk;6!rwCq2w|EOI{lx7YS7ZD`PV1_)vTRT5hj?w?pA6pBOi
zez_LTY&ostn0Bw&hEmE$jpxG0a_%VW*!d)hv@ty|DOXfc-6dl2oi*a{L?e6?cS?~4
zG2;pCz|_rN)NQQKhZfD$p)NzY_XR?)81;maO2gkPXW204Y=0SHp;{>PU!NpaI0j)z
z_S^IwPe35p>3v%O)rO%?xa%5bQ*I_7Kho@e#qiweWF_*{zAMa4N(}-^zX%tP*$dIY
zu@1W}zqf36gUxYO(>ApLf|qE<@f?rZWJ_9op#SD4T9+jPO(iKso)bEb63pdAUUKq)
z)uIJGuWSo*+%yUDzBX!VJM*@w{Cc#waoUA-wts7B=n$QzwjizbXv=W<8`6uch2D3v
z;=HzI+Vtxn&f2S)K^%{p>nq1wyYqya^%Mt}R3+^uNz3j#Ie^6xH@c&aR-<=AeW2l<
z;6TL;x!1J^=0mQa0$iW*RIYECVFW+3EgYL_wZe#a%k3XwVQX``_L_V&l2=e7x993O
zIF)|$7Q)0l>1D#<TrQ`)pI)SJ(WEZxED@xW#yj<m$l!$^9R@`yFQEVDP`wBt9!9*1
z8ANmDe!!99=Aa191u=3AG9h1hqiENHd1gDSS9kcaY|notL`_kr{HjfA9@b7`{JNCZ
z&9kH3^K~MPHG*FkJ{7$IJzoG!_R=?Q?s{1hG~%ad)I$>yl0!6psW_-(HC;KGvc>&c
zb)6!{Q}QmN$d|Sr3Nl-JG$$LPg~w)5HZ|S?4%wW)O{wTJJA6zj3sE+JfrYJY?Buif
zelR!tm8Hy(lJOL%slW$1`=-y`xYz(6=s)qWKw4c$8$&tAgfO9DcofPeo5pIk2$qlI
z$V;^OL=pH`5?t%q-=1M(m+Ex!v$Xt!e$jQ~3LMMo1lHb#R#X>+l)wNIHqX0VO@)KV
z*@+SO^Che)DOQ7{Z4akmKn+Q}o(%+eEEOyZRpK}ZO&uZ-2!$MpFMw{1w--|mIdYk{
z|2@6ee`U9&{QS|>%+Rks=MeHQPSQ0PGJ9Bs;hMri`Gp;`#y#WiH#i{a{>nch^OVUX
z<&rD4-4g+0elZH3hTgD=N|DOm^LJDLGSRiyy%oy~E0HJE7B2)4YJ#^KIXu78n0uQL
zR%m6xTVbE)1`>(V*V*CdpJclU?;kY1QDdK)pAg>F8dZ1>o_Gxde@RC?6S|@gcU9lq
z<45t%rbQhR!QH|tB>{xBfN}Hm*O;p1;emz6e=;R7nb!}pX!&;INotkiP0W7|<HXs$
zu6#Ql?T;85_|gfFldS*FlP9YJse}N^1=wX&24rJl*M18LKT4Ak*mUjbv|XX}xEOSF
zZ+7NXIn&PyJ%38!9N}NZIxtpHwilXmLS!D<WJ|9G!joaUmbyZ-)rrLdHxKoKxDEnV
zHFMaAW+!M8`<rps!l4>NFj;)Z&+0d?-1~2J6TajPbIo~`S@fEmk{sjGHIMa0W&8EK
z%;rb#@WaIO%@g;Ap}ah((_oI#io`$G>6lQ>y|geUwTSJ;GOxHozbpkov#y2+FXZHO
zT^l2pI?NgdZpaRSHE^j@VT6!qDuj_GFZitSy*OokamvKgCX6C#&2het=`rxHONWRG
z-Vy{E`4y@r3lo_?^m;Pb3&4Lg>a4;}4w>nW=}jO%l8a8lv5&DcwLQ=2gpYBD$#vi|
zFL``Nw)Vpu#`P|r8S7v*k$+WH4#E~kybodGdaxssQhe8Zbg=BK=wpJ=!WDz~7>lm|
z85P+Xzlum!Ns%}0qi6j)nIChQiYChx*xA*%OJRE+Ykk!yHsFhy(rq;l*1UnZk;vBo
zLLr{zi@(cjp(!2geu#aOCAZ)3W4TkaSlDCS6bRS3cHQbvn+ReY;96Fxb?az|4^;yo
zOD4hHs<P`mm}4bJM(wO=Lc)%_p#qLs-0FT9KXFje;oZX#;B8-m=FpE^iKVdICn3YI
zORPb<V^W!Y|7)2Q(DmF<qO%PZdMuo|%6D085$kE!28c#<Pgm59*?_AATKFNyE}|Xz
zI0{TWuOw^&>Igvu0RwpSkM2I4M8jF6#{D6fLM|5aASexMzl?m1yci%T;g%P_I`<Kr
zdp>b9xvB@LEA}Rbaxz@?QuL4F<eZ9?PfFGtt#JVHTNgjizrWI7_}fDHqYsd)(6fvf
z+g?(oV0z+?(&B}=!7F54A(Zq|g=x2ZfFwk^w8o5_i@xvnfKeU?uT`!A=vW|se7Xee
z%D@TA|DkBIIXjg_JAh*_tsg1V;~AF2W5d%M6eSe?>6OH9Q5kq6rKlf%W)ZPq-Zxp7
z6JhzWPxNV*dcbKsv@lg>%X>G-=2bpObBqc6S$y`E{lmg_)YVKkd=C<?;tY&CdA+H`
zO>(;KK;D0y;ytskqhBse4%ML(-J$Zi+^q-mxR(zKX5d`H*><;afUYP88zd{xJ}BK1
z_4+UQqJ5w)Jcj2g=|PYeV)SCP<Ds{h0d;`c+WdJXW;wfn5M@0slQHa<e>NN<mv#{r
zJZTxIo?=$l4LtA?Q#fJA8k9~W`Yoc&HnLWf`c>sQqksrWh^NiYah8nt>Rjo)+$Ox}
zZz@pR){~++J3$G`zLsl!VJ>gN(|aYHYqrya>`VUw9oAkr;;V5YfXnyxKa^Q{B6jH!
zyvVsBE3=Gs2t>PY>h#r25XU@uV0bA<d<Dom%G;x?wTpaF)JbVf4sn_aY0B{?N=KNg
zV-5oBv#hWOD0i$mniw$sASZ}~_9dvz;;fP6wu(J|9ibcYnz#XkJIR{e<`^(|9FNCO
zfl-~cO`RY-0jfCbULUtoL9O^PJQ~Wa@3Jt*j7<np)iJ(UrlC6}qg!<zaiGkEiOXH9
zOU~lzvJUJ%C0yk#5I#+L3BM@e7KDq1+rM+8sws`(sKQ_kqp#eY(3L++)9*X-jM?!(
zXt8wc2;hY=eFPU5CR{x23S}eGthbHFqzQ<Fy|Gm)|68euO=C1pje-B;$rD<Vy7K70
z8sVrqONn}Aa-8lzd}zVvJIHs5D+<9q!4>>EU^2fxoi-P9%ji<IEcL(R2a#Y={Yd=3
z%&9l5mc}S<padw(D2uY{7(W2uGs8cUZ^*)n2CyOvr^`o8wjDGHgaT0k$w6hl0?u95
z%t&!+-A#JWjcNEHNqi+t_Hz|cC4*g8mhW(nLaK`Y&m*_rW!Cp#t2r6>mODV|w`W?S
zIIVp*A?%1z385*~WC3-3bG7P%7wRL*w(Jq<43moQOstdK;X=Yr0dctYKUIOtMvx84
z)VY?2j<pVr%4>aM)=4EcCy^eSj$OJTe$;_Wtx5{$DL!D?s>-s+LH^xkS3n2ya4Guf
z2d(-6bdqjKG{T*OG<kAcz0mnD@`5Rw2>e=-wdSS;F<G`oqo1>IC;HnKjXJ{V$*Xs!
z#yNieR^&bvnYOcX7l4u>9=U-*8Zbnv2uRIHISUpRXEB><Nfh+ncG6Rb6C6H|DoJnw
z(@?tpGzC?!U1an6CuNLIcGbOQO+OgVQmeLvB{pmMs$A4<5<z^uHbmMP(1q>Zwh!4t
z13o`0*fvdV54W4Yr;UiOvHs{(kM?ib#ZDwNeAE^1Eb5m)n}kD9!>)+n*gVjkm0_m@
zW8E`pCA%G4WR#9ptQk8ls)eL7(rgu}$tP&+XA)H>LF4j`gn28@IP|leBgB_ym~~1S
zjvbV<og4>CLZ>Zr5*4*4GpT`wXy1{ad|9x@k(WON2TU5ztBy8g(uSNC?T=4AAd%>`
z7=q;{F%1Dr!Juk55Rq)m99cXUzzow)&rdSml-RZSKnyN;(|C0)lBXX`;7((qN}9rU
zQ5$x4`AD3w%>KlYm&O(&=?rS8byzw07aCuUd){EwZ#=KVq)bFkgXwXLTB95-q-Ene
zb8I*F#)T9C5sy|}B6gBd&1e0Zgsx5!^WHW;5uIWq#y$veSyOS27CS!>;PoLLz|d|0
zpOPm}-y1NBhN+xckeJ1`f~S=;K{tLT;8<9kKa@a!FSpc!6lsM>QHo%**t?n<K9Xp?
z4x~XR3H6t#owoV4LgAaT=VcnhTBhm<oE+aiSn=ZP#uW{*8{Uap?Bb)sPgXn9KQijE
zoL{o!>l^?S#X$3+)%tT=tSHt_?RlHMLs+5U743mW)=QZ!T0kq8mAqz3BYqB$qxxrp
z9vVn+1iGv9-7IGmm)NncyPI7h820fHC+L{oO@}&}1nny8&cRQMFd1vo&LoY{iRfX|
z&20=Yk*rqYmj3%|{pH<smz5_J4Z}t+&E&~F&>H~hiQ&wy<8x)LBpn^P3&;KC>rPZ+
z^XkgfCu=YiI>O(M)3DVNT)b|lGlzkF`I1!?y|!K#e{5Vz+ve%3WK5}4`Ike;snrfT
zbl#r(^(V!<rOkJ<;{DNk7c!AY#F$f<|Gp2VVvm2llEupvXb&DosODaycN#HLEGj7Y
z2!^fgpJi7j$xIU6`0wG^cMA6rKJ|)_7Su>IGKM=<K3Rh`6;*Zo>NP3nBY{{Nm!Ue#
z?etH~c|#+U2n_$PxwC+=#9m}e!1zPPkC+Ev(ije}+b<Zpht+aEO)T@u_3<-*LI?)J
ziI@_XbRvQicIn^@|Hh;#ia{d~?cXYZap0Zvp1(OON_~{GIXZ2B;6hccN*~4sy#p<I
zf{=(O>+vHQjX&pZ#CVJzKRH6(S(oUosBeH1q67ZDVpPXD&>X+6QgApOnB`05N7>jc
z1Ue;C<2~f6&yV7668S1klI&5kjc|ww$IbXmgXIDUK5{t9Z|WKKu_2y*zNIr`tL4{z
zEoE8Wil>O&;2^hC&V^NR*>2bWnIKPKs_=;1pRA1-SnA{4^kq!OQYN&{iUA9BeL#9@
iw+$f7ORkI0q3GULXq~a{hVhtULOmL#0oSE&w$VBcwbSYV

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..df8a6a9c8292defbcfe4b912a831b1ccf056fd06
GIT binary patch
literal 3624
zcmV+@4%hLE6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtljLXhU{1TZ}>XrSWPTxm0A#kp9C
z7!7tvqf^bU{9ZhqrGTfojcd9tcO6%_Lql^#h8EPFHD?)ANdfVc&{|4K)3W7a#S)uJ
zw=m_js&j-k{(schE}Hu5^uL(11pjExsvgW;aNX#|H(1tSY*aU(R+h{qrc7K|UN^oo
zLUxPY8bXH@&oyLq02{j$PTJx#AUMZ<E`pPOONN10;}*g>Y2ZSRZS&wuCb+&Z&#W>f
zg*YA(d$Sr3PC>?`3|_lH@c5r|?a?z=s8+uz;FVs=0*#SM^G+*KcQC7Lz6g;?8iW39
zuyALw(uHFjF77}3c@L#8I}Noppm0BDJR`>x4{R*Crla{~#P5Hl^87Uv*|X&7YNS|t
z#olrp0Q|w*8~~eJIxlp)wT$=~v?~aXPH3{I3+{1yz_z1pV>gW)@b7NCt<!{+6Y;0~
z&f^jtZq>B?iqZdi{OAE!W0DFIWBqw1N0zH#d4)n4enxO99<elVfOt|iKzYlBfWM}4
zY`j6eSCz-L`io+LPzZO?LB+)tVQ!*~zeMhLl#Z08Q}Z?Ohs_RQc70vzlqNvT8`?)d
z;gnThDUv_Wmivth%oKA0z~j^g*Am%B0b;&lFEB}=rD|rs9nLFeIZg)vvXD;UcBKJR
z_N+*^>T#1MZc2f^U$6bz`k@8)eS+6z&D0cE>f#l9`dE9!XcalVhzkdU@hXd%uS3Kg
zcIyTF7=SOdOCKNfaK!h0bb)H%GX|tGtTfc&`*pG2A!Z{&kim{JSm?M1nscF_ny8{~
z!LU<(txm~EU|+HAF<@>s^47D>%&Zag#7!4xoq2I2Zveub#u4O(uVUMY`COB-{HSRL
zp@nwHq(&#QoAg+$xOc2YQAVbClo~l;Sc>?*GAZI%{<6L50AP)g!F`)d6nw(3R;cyo
zTk0k#E93Hg;evh*|Apk9qb@K#)PFQHr<K#sij`a(yjO{Z8S;wqmvAI~jk|5xotkk?
zh;UHLEaWO5!gZ|cVi<-lDlW=c(hg(zf-2#dDH^1`d42<dHht-xurhr-dVfJz&v16f
z69IhW5R*aX9Q{A-8z7VQed72d2!xom$B)x+1Yuj}c#`l+^~ht4E;W-l^vOW9!>Zu-
z%y8=N&j^+G>RhlCc3)9f8!BI-mQ3Sjs$C<E*0HUUJfd;od$Yb^dIipD4Me@h`d`Y&
zA{ZhEDSrjD2CJI_pmeXEG$~t7sXMjvX8suIcdF=7e{yjhDIPKY6W7S};kMbbw(1fB
zL^!7^-60Z7WY6`R%y`|KR98m$%!F(>-WC!f^;6wI0Bbd15K9X_4(glL&Re6%%)YOm
zXI?YlG_(^NW9Zk#vwai|W?#7&ctr^Dl7P&EIsMDL3>!9W@on^Q3v7!YNZbN`>1<<D
zF1Q7@5U)ve22oQa#QD<Ei20j{<H?g!-!W$3H&x&t`6<tJWE$bY>6LRD|1ss4jf;Ch
zuw+jm!p&?7i;eIaxfh-b{|kRrMQL0^{PY9ZUJwn0+U}@9&dxxra*V{&gpvs{`9kh`
z!!3%x2+2h$UAfbtU+XHzrK`Nn7WqL8-qHd`>yp`;a(aV@72F<-5fhijYXl)D@vmx5
zu9*Dw9W03!)yIN{oEIH8sXCS<*J)_!vt;)P>w>`TRk^e7R@(?9>5_GRNLCY-{#0Jg
zGgQ9L4TS`$7>5vpKAHV(GAxUuP_tS+h}wL+^3!p72dakPQeVtw)p{4coffHHo{gZr
zlB%!RqnSqvfo3%dSAdbPyE*uaWRG}u=Ty+^j2_aRh-(42#cjGf(#K4MXvQd?POorT
zcQ{)iDL^fs_^MiE$SBo^@JI7&I0Cv2sZTWw2cftul*r{fR2qXzw$x#DU*;Y5f0@x0
z`GxmIg?%ZO1VpQ?Zud75j?d%J(W>NUgW)aTxPOJ312wP+;pwuM{i_)foAG2*%JzHG
zD|uxvdAoj05N*$Xr7}&)Zxu*~mh?mxh24iuW+|G105MGz&>AzxE+E0<dS84goarSa
zwQ2uSy%N7By!B6)qrW=ptK~T9W)ydfV9@Zv1EVR%P$)By)Z%k`ivKvKM>}jYX83Dn
zbgK~(_bu+a1`f0BI|3R6?i0w}u7;c5*d)M)(Cb~l4-_0dQg%^R(5QtwMSrY{CX8z~
z8Maq*26F#<fAu8-p@|9BX<H)+a1)9&$YsbKEN4`1q5P*j&2CcxKC%Y?kRmCy*FaLW
z{6vWaulrIayEv$E)-76f)${)us=VR3N)yjMnlf8*4k|6H^L38lJ*Z?e|AEPIP<Itd
z{L{w4o_rc)?E8*<&%5t%A_i>GBEMeBbsuJ`jR9>;is39G1FtJd-1XDOZ5$nbQ-#Z{
z>RAeb39&n`2_PbJd;A^b-|k^s^S;&#oSG4_`?)cmc1^*&HeRWJ?*QysR?*PWoEP#r
z2m&53OpP7(eOwSVzW=$kVzz_kEHZq!OiS9?kG*_Fs32yU-qomIJnsWlK0s?8kwv_?
zPae#j%*VE&ZU#*hReN+%P4BE`g#|XMWvF7$(l-^?P0s|91$SndlX|pfD5~5^v}59b
z>Ya9@O4C2>w!jrMQul3z7_R9Y3Gx8+Y1mMt@F<F0ptU_D2DJ!7#gRkww<T&ovEP1#
zHJB6yrpS1Md+?GbWXFGji(lR-ILu}{Y9+wW%54^32mE+Qm;l0`t*59ddhykvDoV3-
zuS~&RrbTy`#D{@`Ehfmbx~f^IrUR8(<G8O}^7zGJ(Mc3pXd=m3-p~AU8u^dWEC0*y
zhCqw`^Y*ArlPr00_GDedrA>w&rCp=;h6;A5iYVHEWsG-=cbc{kbyeY4`<h2ce8$ZC
z+ZH!&NBJn+&dEh(&5>ekt5^zI?cAz*3z!nxb}U~W!2vV_B^Fm4eaJEX%KX8sKeB+l
zP=S2t$OjAqg^J1dH-RCcZv*iJEzKr;?cOtVZX%<Zo;wI_vRR|?S-3viLM3#pQHoID
z^FhJN&>hJD`6BSSOX=RL@pmK><TQC^fK~@cMr@bUKTtio;zDpEDPTdYNLVR!r_anO
z_0ISQhr~|;N;fv#tz4q37XQpW7QvjBGs~vdleMV7cwP*=8&aKC<ITSb;|CdYYN%r9
zHCsgXg%uD4hMo&Rbty2YJ0#ydThVKR;}b%Xo-urfYuxuI)27sTaB!6VD0j6p6I*}T
uO$7t_H}w^NETB4e1S0<ZcF7BUXS1;fWkGtdGRSDSN<(s$a0l10RC;%k1OtWu

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..54319284e38b60857bda427111c5a8b7f541b748
GIT binary patch
literal 4080
zcmV<M4-fE*6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlIWlADPVa@`T@6htdEj1bCBhv5V
z8A)Ll+I({oSm$_X@kxgrZpMKyRh@BGbY^<TBkJR?qQ*Io_E--6kjqxNDbRFU9-Nq+
zcR&HMGFjI4hOC(R;-@M7QJq4R9_<~$K<;~s*CY3qZs-oRJT_>KbI#5G^rBB-YG{|p
z+wr0#VfIAe9JtvN#+gan*&2`meGI#7Zanq1yP8VqJKWUZIh0`o=E&GES}wbaZ?+6v
zrCUKVy8hVIYqMtW9UGB1$Gw0OYG6Zgx~bh*raL$i%4eQYNC;3z$E&LARHWVd!qwE;
z$fV!Mu}o;`rEJ94S=?7^YS_V6$hu}}fm`t5hwK1&tA9n}%PNcUx6{j3^{sZwMuuYG
za{c0Iezi<wAAa&Wgy#O<x~sRsJotTac<1G`KGB79g`mRY1ygMVs0t+&@jY^Vi#4l<
ze2U8SP+)^CKw_O{%-K}iCXTi0IO~4R;kM>xht(}})_1#vanYU3e&4==O%zP~x&Mwe
zqIu^_5S)LP1v%(1@BA?WrCmxq{flQ(AU<lQYdPDoSWbLK6zPx3O|}v!E4Qz%zOQGG
z4ObJ=YOiZ-@}X)o`zo*WO6Mw_=hYq}q0A#DWj(wL(dU0ipR1P?c1y-E{nRmsiwW44
z`=yX5%i0zFSm6@rJtxBOg3nr7pA}~z2s_06X8xtvB=s1R`24*G0I5^=8n{s{-KR{t
zCjIHAJDjD{DcTeC{qs|FQi$d!D*H5hV&K{sGFmO%wp4xspJtMwY_fI%XjlLEGEBiZ
zM=|6~XRkHU^}I;}ZEtR0Awq#r6!U!HW=HP2zS9qIz+0F%)PfF~WUe7X4694txpQkK
z@FSSsC_lbxMGtS#Q65q77CapOTv#9rgx8Sn63T~leYl&!#rRgLPnrAUn2nYKQi4dK
zx)oky{+$n6&;!4ARxm=SOqjsaeu`bEVfl0*<^k(uxDYa<UiXS`r5!DfH~lf1-!fi^
zWlByc+WiTIroN=3wZ@VvWMl1cQ!3Ed56Ec&XKo<Z_9VZk^a3+3|HTreT@{68mY!>G
z<cEl@v*kc7t{?_f>0<ai>LfIco_LFYkU8Y8WE_fHYN9+NhaC2@xLLUYI21h%Z__-;
zSD4TF3FTEUwFu$Ep7%!kq{K^cq^V8c`{punOJ?)@HpRiQ>%#l`wEFLwm*;Ek0xW03
zeg)d2S)mx~1^(+A)TT5e^a;RW<~Dlc3jzfX?N|@QST{?hDkMc{9Sd$ZRpg;@$wV1t
z1GDzuI1X`p3@vaCAUEWXajYaOHQwd8tlA?t*o&KV5&ds3#?2X{(jds5s@qLK%M&{$
zW<ifY+z8N+39@Dds0OV<AW*%h0lH)BJWaez;dhq%J!yf4Witr(A<SPvDWi}8ifUS)
zRul&Spep)|!7`RK<t9OXr@5(Z36ho!kCkWrj!*G#@%YSXBt4!wG^2i&R8v?w11hNB
zZ&g3zGKhGjnVk+K!JL%u*u_$Z)}a6+Gmue!SRjPDdZ*EiXq|mb5e8cvgUsO?9u(*@
zGUBdyIvhFzq_oe!c};xJ8eIyq7i{CTd&PE8@GP2>OcE}=`N#-81G=bGFKZ;OB7AlH
z&63OF+LB?K;r#d7k!|pexd~_KeZn`3jeRh+{yDAN52X7{c~j{$&df()&?9ahElR$x
z`KA6S))h6N0g?ZXkO?c`_`lFqw~y3LdCu9Z2L@o5Z+fV165S(D18@lZpIfh)n2skg
z<tbk^fR=NpgTBUI+7t1mW$j_kT4z-AxLEH?H7ep}PIbCW9>{aUO=W(TyaC`3lS1$<
z-rOKY!mjKwRAp(Vc3^)Fn)mp|fiR@wA8vI70C>Q7%95`Q#$_F>nJ!B9M@3t-CveSk
zrnKK?x)}<x!8ahPKqvONnyU&as>daDEzB`&D2)~jbc&9t73^tUEY=H8tKt%=wnz|i
zWJ|Gz>7{b=*l&oG)r_z0!3>8mpA@X*tw`sw-?${ZR3iyUO_<|zcih+ZrHeYK=&J<0
z!=M7B&Z08*4+|LRsxQBd|4Pyih&)s8@#BB9Ra9N}7QUnfRg-={voH+o`BU_KP+^B>
z-w}TM3<hrkK5Sbr6hN_6z2Flf2(ahAGBrH&bSKayd552uVhCL4E;#JRE|kZJ^B<uw
zBX-I@fK9b9<}hvdZEy#2zUW8FiPgJTRW^lQTlhVFI|!v8gxBh8o##6#&(v~DnBH$|
z)4&;3&tC*~tXR+klSWgFyL@KhS3HUGM<R?@7399;C9Ozv+MT^7L?ZdV!&KD^0)w4K
z;d?yRqzar12X!i3v#*q&-bnqga;41pnDUo{>03z6?s|{T#F9*?-1+dO`F0qX+#LVc
zgV_5hEf{3V+h}5bck^Zw#%O#p8vOl$T4pAuLBJWi`?AQtj)GGa?!KiAxCInfI5^;|
zz9s};3Or}T(#?}7OUDP4oQJyx<4pNvN0%miq2qn=3&2+17fBglnxalo<DF{wG1{Tr
zx})G_Kw*GN`PBPHI`Y~1(=0H?>$hwQqFWuJSoV8ausf5jWyu7Wd@r@6Spn4b6CHaQ
zBv7YStx)WkVv4D*vZ-_$<|-og!L=WFqa<5T5Ch~h5TPUd9-i<I>|_8v*M96WkptDx
z7+U*_iY||SWdaY7(exuqiit(Ai{+{(YKKD$-peV4e2P_U7^jSnJicHpsV8d-udZ<k
zO1v1P^p6C@Q9MYo_%HEZTXcIcECwfGb?MmwL|Yd=$_7959-S>#k^vid{Ne}Xu-)?+
zq!iRr9hjR?ZnA$rfqA>o1=+@WLH+c;egwFnGX&WzS28DZM6S0mR6Db|#-*+Zk&~m~
z6CYt_qq`_2T&nYCL{VLzu=7GfFc<Iph6=(nBZ!-iHRcHw50pkgbrTrZ2a4to$dOXo
znVxG@UxJwhb1BTcr~OL=h|1{*>c$^m7-I~>`w|PzKUpJovLk{aTV<ywGyl&omW4v{
z1a%q#L2AFhhP{Zw?-~}+JC$W{b>fUvHt!Rh#D}DO!>63(*j`lE|AV97S@c=k`EfI$
z-j<oJ*O%kQwa-2s_b(m#WMQyiw`9A**o5WVg9+fJy3!zza6C1W4ai30gJRmecM4Lt
znhm2U<x`NLHw3RgAod^khFV6*4o$=tQXvE0d*89v!G!38Ws*%-rY3yHKk=c|goK|f
zn?#pv5uIs&pXb*QSTQMk+9y6kBFd*h3=;3Q2#XgemnztypY<LPAOn`8997hxn9F?K
z1EUJ0#sSD++X6b?-UKR4yRD?U83in{>hUzazSnnJ1WSZ<<fsO(vNAymO%FSi(27gH
zVoMUH{T4-YUe$Q`oB&O>!H6|^*}~E)L9L*(x7HQ@RiQ{opY3W`Jl8X-k;CXC@7YB$
zf|ct(dLr9A1ptN6-KX4@;4fjTD>lNprk|h<@y#uoZU&Qvd}den&<%ZxYIzC)Hxj%B
zr%MDh^%Aih1=lSocfe!GA%)*KFt#V53#>eMk}l7`Lw83{8?Qd7CgpM3R?$B|S`rza
z1Oil@5`-(2(&2YjauyOdU_<LZ;9&n{ipuYhsQU~qk^LCwE%(td%ETRre@8JDiLdh5
z7YN+PR69gr<YI;Qf%Y||D(7J;U5r#4E6^g0FjK={?ZVumScz+&uK^!vyxc?25z2#s
z{Bh5ACi1lLOr{%VllL2SMa?P0Qc9StySKVa2G)R%BndvD)kkcRqb}Xy1alcNnmRGl
z4zktCSj%?;A}HY~T>xnbpbK;0n-#`XaiuL5i3qD0MXfB_4>!n0>S{lR?W9fGxb`}q
iT|+hE66^jgd?Ol<5P>;DGKVkDc@{A+OGW*pQAycpE8~g)

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lfsr_10.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_lfsr_10.v
new file mode 100644
index 0000000000000000000000000000000000000000..8f2d7038d06a41f25afadd1a5bfb0ee7a3a88cbf
GIT binary patch
literal 4040
zcmV;(4>$0O6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btksw4<)KQQ|;aeL(zafZLh_Gy$W9
z+yrYVq~m^HLR?8SE^tXWvIIwj;c+q3+0qJbbArBQ$4~)J(IOn$Ns7mPA$VdKvDBNb
z7nH;VSLh%QydZu{UwBoEoqphH=~^A6`wLN;LZt%d@?Jwpc>em<B#m&lGLa%qV#g=m
zfBx`<z4rnAA`Xj(j$t4^k`3vNn)gPCz@j`36V%UFvIPCz=ut;J7N$XPg<o^6Y}k>^
zhb|YWCH)@F6jop^X>P!YSK#XKZ=N6p1gE#Hv4@);&j=L0;6G#-w<5F&`|Ayx=hEQn
zge}PS=)@U<**cr=c`08dM6-0-4b}yo!dBH31n12|Chn<-qL~n34Evy(muT7KAgj-=
zFx3ZigD5Yffmlm7?<VmTy@gd?shu<b9{O0mVoh5SZb}5_fQ$u)*Z4@VFA0m)>eU&b
z0BysFH>^`!lbZFv=6W-GVha!!MP(7z)4E+Fvbe4@e=m&FHc;$k>hOalPT#tR8*Dl1
zW;Km6_BFIHLGt(QlL%W|X$kr@INi4g^3cP@4lSmFeXH|?iMk<Hv=T1W7<Oc?R3jol
zp##~Hq|Y5(5E(~*1i-7CY)80J)c<LKg5lW0380;oHj5ZCq7Jo|9<km*5oDn3kZwu=
zzziG}A~-FvypSqcbF@JNH14*kb_DPUnI>B|M=gwY{hK{jTk_5p9Kn)687XV&oo;Jl
zH^N;nv48yYt{9_znMQD&xm9nsqd0t0n>!gIHFMJsAeT0cS}D~`bPB}udM+C&>IE^Y
zvw}GOd7i7)_Ld9yRK+QZ$JB#ORKa1NiAbzMae_EAGJR$bhS1CqbC;f|9!jmwRgt`Z
zP)J&o`ST7g?%tF<li9$YUx_$e0N=I7ZX^0pyh&7u?g{BL*XAy<skUt84PP!^PT7*J
zg_+5tG*w<0&F~_=&TXRI7%;%#A(UF~r4Glj8pNZo4jB;mzj++DD0G6b7^_4a9bGm*
z6Mn9igY+>N=;SZWW70As&iWQ8M&?h8vm{-M8zac${s5A^OdeJ+$T_AS?bP$7js+mo
z&+@#C+y=SP*?RSOP(8X=XM2uHoLwqDL|tg&JNnF5lP?-{i%$}EeV^CN1RjPXK&3t~
zipKT0aN2p_C=+P4SvNA2mYqtf>?$A|a_a+~ZLPieNWAq|MPS>;RS*|Gyj4$^2B6HA
zkZe@D?}|G0=0u*#FuEpysAY7}Qkr^633T*iPxy)?^D;EZFxP{NJPCrXQlJw+c>j*Z
zzco=lqtJ0aa)CeNeSrQ!rGPH0f^r>EXWZk8`IJ1S*O}MGh)XY_ru!;N9Z~#|z{wy;
zRA|7Gqh;{^a8-nUe9dMC?9*~*F_JfF5Z`|Z8hF$xVX(kUsp}m#QYe2T)$K%>075V+
zOv->{$v1lfVX5hu1P?~jtPDP(c}@wQGlSk9)+`+PE!i!KUpNUQ3HhuI*L~M6EI+<A
zu%3R5d{hZJJ9t%RLUnJH>1OF`GWS!weCdldjZ6Qh$k>MiC>K>-P~1y@cs0uiTfe+a
zChrudibb1$1Mq<TNIJUuWLckACa~9;m)T(Ws6N026iPH*wPNpN(!aE$g{&H4xu8Ap
znHd>=00`v~a=r++8=0^ON7xbBjKtM8yIUm5ictz)p2_Q*ibI?NEW*x_$d@SaY+7P5
z&2}Kt5uBycyU%ZIV!j=+iXLR<_#i-%YAG-1hu9^b8zMRpa?6GpO#+P~cTAcY&hk6Q
z8+~o*6=RVwB_7)cNN<GQ!y5L!qq=|(e08ST8Y%8e0yvB6Mfs4p)h4W;!a8&W{pqg7
zP4Sc#4mWzMeYd)LTN?jeyut2F)j)Lf!%EfM(m#!|=xqIXfv-Cxs7P9M6YB)lGA1XZ
zIag;7B!r&Fro-7T9Qy|Ch-9+i2LwSG6M3y%W9UPl9AhrZ1MmUx%yfZ4FAyx%a=atZ
zDkKtJ3}qJKK*QMR>$xRBT$Hq-MxBf=aM)s!7XdBnZ%&IGU&RTNtYMa|%lb><xN%4^
zZZR&s1nPbOH-TqKZ)xoL+2xlW2gvQg8^lW*q_IC(M4i@mia*aFTq;==Ggqp6K@AHk
zoAT*gveSY&wm0!aDIi@3R>&PCy|Wx&NwlR;hSE;3P*Y*xKhC4tEbd1oX`$#V#lpRw
z8nWKwAdhT9vT^uI(-=1*=X_c33$Q`#%lT+<?G)O7O5LDgfU-lTbUyu?mqnIFV@6B;
zN6{s{x6}<?rZK$8S?((Xu$fXpbn}FU9{F=W0$P`Ka2{ooJJii%3(>S-!{95h3bpTi
z<TQC1XssW)wRF_;)>m^l<>#+q^tto|&MaPj1UC&7awMb%!ic<Yq<T$FA-Cmni!y8x
z%w+8Q4_)TRwd`A}#w*o8=SgkgXl(xMt{?J%n?4CM`bH6=EdodnC7oss8jtv&;&yn}
zK1r|}>-=AEwwyonH1@X{cOG;^$I2}N1j6>o_x|aE=5U^P?yRxJ{n%qqBYph>nWnm9
zZ5$ALSsvoIz=tbDM5VNkG1UfA2I8i}?0N$e&!|4ybqxF|06rum6%BJQ(xedys_Wn+
zAGVHOp?efcw1LF|kF~jS-mS+;E%p?>ONW;<Y)y6F<c(alqm4YP!l!3CN65B7>d65B
ziL8jGjG0Cu*!aH~>Ew%he7(^NTLZra7|n?Izr_BuZ>c1ou+2IYglM|JVc19xIW5X9
z$q<raX`Y48jk6`gd6Jb^jqsRWZa&2zN);u;W;lo;>+z-*EOa=K=+WUpy_Q;LQS3w^
z(zT)3a87*mM4dXjX}8(!*8ba;%OqwB?aGW|(Tf7&$L8$sHc0w<Vd;^^XY|L1ck+17
zokWUP_gG48<GI<isnrSb4wv+wyG%Zd8qQqD$}!ak14+n|7>ehf-8Xwk#{(@ROL<Mb
z&+!^`Ch0zJ>=07>L!yOel6e(Ic^n_zbng6^r%2nk70#n)0;#qm@Vho_(#$tB*I>RK
zYKvG9g7sfIu}rNnzv=M;H?%E!@_NK%p&#eb0i_(t1}OJXc^ZO;*6WUuNBrfaj=$x8
z?N{SCXo$4*W-IrhlTo7e!7L{VI}sb`l-tItxXj1QPb~#);Uy*RY1e{-T4#y6W?L-z
zdDMc%eKDb0hWj91+pjdg*#Px(ANK!-j9etBZJ&==qd~J_faI2Gau`;$BK}&|xr$Ou
ze4P$RGd;T=Q8-SokV$e1?bq_R2b<?hb3viUbUbdn2XGT0Lhqw-bk4H1ZP{v$wt}YE
zHHG83D7`=xo;IRei2hh4#+RFaG#J39+)e?UXvtCf-@L73k-#sPI1<>zvdCj4JG&+E
zyh){`rUQ9==R^f5MQwi)d|?FDS7<&I*2Xa%5~TncZ)diNU9qofcm#S<cqnrNe2(4~
z@}-GJ=>$pu$77=+l?mF-w5l|IApzjqB{lzDTo3EMcy^r*o_*cjRhGEqXSJsGckAfz
z4S%r#`!OiJrD$_3mr~<5YMBEyma|44_Zu#u?irqA1c~TSY~3dlclQM5dfSn`D%#op
z5t)bK9ui!|t4pr2H$&~Cr=BJ8eHcQ=%@Dt+VG0wtjP>mFU+fO1pFU;!WgeKc%}e)A
znrTc5tQ}%u!LlKpFF!>DsKAf+th1)C8DJ?i$j#MH5_b)XAQx{?7ds|M&m9Be;nW-2
z2_^$y(Gc|E(K*gxTk)r#?^#MV?N={><$GT#Q-q6(Si2s4=3exKNVIv(EFjaa`uJNm
ui6Ewm;bhCf3nY=3AF_xvTuMrK4B$14;3ZFO<pgLaITN-BL90%dK}{n{8ok#5

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_loopback_ff.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_loopback_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..404f71caabb48e6fc696652055eee0cdb621d19f
GIT binary patch
literal 8768
zcmV-GBEQ{>6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btkc0V6l*k06DY8m<?RyuoOxl##)G
z&Q1nE7^`IR9#5Sil&w7fmy>In-%~v=<E4dY>eMuxurJ4jgRu_=w>zFUSGD!E$t&s}
z-zxuP|G_YLP96b;q48!pWL!st>~1^ZFbnRFLIjtEB4}j%(nGxulQm$v9dzP>=WQBG
zGjJW611In3uakh&dku$cC(QBs;d&$I|AyUrooZSLG~{w|5x3E>exGIm%$`&qfLhA3
zP)DEd<=m=+vU%NCaBH^y9K#Kp)Ogqmat|X@q%be7s~UfD_4lB7&9!`knJf<t+adrZ
zHGJP~5N*<hbHZ{^^(LPw7(x;xphg;D-XAfLzB661i6czEnLW<e9j0Vm8LX%M|HN|m
zxA$(S`hCDilVWrFc@57-1ck$eRz!uKO?3pcRW35YbYnO*2hw=ZxzI&wl1W?<G_qgL
z$y?yD^fV*YbLBNx94RKZYY2tj1>LFJIZgxxHK<JLSxXa5QsI8c$VxJPH6%%uvRj!y
z4o84w-B_Znox5@*04`=!$etpWIem#8EFS3=Dy~bLM~M-5#$FR_?ZIB`N!Zu%f=2R7
zo~OMyX2-ZeXn!IkgKbYBNI(H26}(>%Gh%`~6Qgdo0BO0hs_NmcJ_P7uQU=WRf3A#!
z*-38VWk~*^^6*@|c?*r`KorqrDa?Ln(weuzFT`n*@_*OgO)s?Sx=wz{!C6lkMAr&D
z>GSCGaaH=Qn{0&RF#CRO2S?XVKe{*(WMer+a+#ncI6plBY2jZj`4<!drpdJ^Gx??q
zHb?q=j*-5S1UkHE;K#>Ij7!D<wWfu45;Y>%OMfLFB+f;_Pb49Z?tBSj@>zfj0qWrL
zByQZ9qj2<SMfc2=G(}$!v7|>vpER}P7Lr>Ju91%HeLu+mwGgtt_e_pWza8RLmH6_v
zg<27Ek8UzpMKA0c(mlP#wS2X9lu5IckODo2S>>5yTU`T%hEKh@w;RvLx6@%G?>oS|
z@USv604U4lA$<iBylD4`4_=ZN+<ej%%k<6Jkfu6I15&UI(MMvuP-&EW<xHW4@K@bb
zq+?2OCSwi)Qs`Fzc`Nb<hmD(mz7kd!btM=~k4?9Ja&26-rZ#+chb`3*BM$UC3L+|k
zC~q5(y3g@vQ<42G`KVb~rn*tE@jCgtfW)<hTXXZwNy)RAXyt`!BHrH@7Q6XF9{rTO
zCt6xe5A1;S=A+Z$5P*bITp;tyL9MpP&Nbg|xhX7E5;2#;VWZNvt9aGt@<0@(gX;+}
zoqBP?f=qxZ_j6$CkA~UaS=3Md*IUzqv$T(<=_nnaSl|S%aD4S4=I)DfD$8b%rjL+R
z9LZx@WMv_B*9&F&JzL%qYs$1=l4=qp3UisiKw!WfU7P1o{BD5im;sX%^6M||3aXfk
z^Bc6)aZX4$$5wi;8BjX><LVN;NE#CpgNUf!q!MiYF+UjLM$`NxKLzELh@m!$DI{Mk
zv#AiY;8mq0>TKQ}e^9F5tZubYP)F`$4NDeztUTYViy8W}#1WSCo(hxosW@sM?%MJw
znO!joND3RD4w-yO@fB>qOK`Ing{0_&q)li=k;P>jMP(f4o#=oGjv<bADT@Ll`Ryz^
z5-*i1q29+GB@z3sk8D%qIbuCm;~UtdcpL)IVLQV@j1WY{gX>Cx4?E-Z5E?QKG?wV5
zH$i?EZ#(#fXIyNkNU!>qYCB?-*~z2Xv-txl;hk(3kwVO6FaBSqlBgJ6lMxjspYQ4w
zz&b&gxem%=!#pcf2HvX)#Bwt0ytbOv$V1%lqg~T<7Ud)yA9#M!Pv_5D1hP|t5b~n_
zllLL4>Y7qtaNY2GBDaH91g-2YheX5M9soPaVvNDt#tzAH4XmCj&BZv+cgA`hZkmJ;
z0xi>ld&}@^oggDjV@U;m*~T&+^`{s(tQxV42+rR6lE&n4&v5;!&gOul-~}{>n0GQI
zwN(#j%c=Y_;bIjS$Jl+?p)oL^I;yip^{3iB%TM~2L6j;KNf2xe8E*j$o__?R18Loy
zR92VL;f1W};O>yXS!?ICK)zd9GN$0~ptH9x7CwWR=!*&zCnE)7xuThQGNuOZ26X-U
z1`m!6G`{gYxra@;w>$3q&t^^hvz@~Z1%%|VL_B4Az;GO@)}{~BMUR3LsfemJgS`{F
zhn%f~M?CP3JP<6&LXHUBO;G2-opMul+a6^?G<2gB`=xk-LVLPe)ZrV=Tp-MwMI`-!
z&nkM8j~RfINNvLmAqM|(tl;m3)H(~?W^nBMuBRp<5jejO<aW2l@GWWw{h$YHT|tQ%
zmC6>bvwWJNPRgH6og&ClQ_y_8&ZZ>hn^-YP9kwUFsl(P5Cth#E)?>gQ0J*k6ORCPL
z%GJSPW;um!hflku-=NzxyIM#DhloW(|0gL;*Rl|3rkI1zO1(CKeglOF*M(l1G#Nwh
zAQv?#3n>nJFhQIa3^p4>@#F8v*WP#jv^|uGJ&(vly1z6DirnM&2gGrr6tnbzIS^2Y
z6Cg#K>2Rf#bIQRB<{m*R0<z4=c>}zEo*BOT>R&9?=?ODC%v><`uYBJ;_el!}3Z#Qn
zq_V3BRh)V9lu?|QmecE?kze!@yS!1aZbuK(Po*Bn*>8`3mX84ef;MWph$C{k)V|bV
z5Wq%rh-pr&5?ml@^h*(t$L6>K-^gIk&R0Z@FJ>UZv<yOaYS(iZLbP5ufBDeGGpUT9
z`NbN<z47Nb5~9Cz2yLiF@CC4f*d=L&cf~mD8~?D5HJnmHy4#n>;^a^8l|1+GCx5r$
zhQ;!^O6~UN*n%96hU0qKg+xTSi-!&`(IP+c%WeuG@LHx7$8XDjbOr9-^yF}V?=vIT
zZ$I<bfm6<M?|BMr<#i8-4djN8P+oS=GmxKf9{~E&_TgCWJ$~g5PXT100eW$*n#9t}
z|0uDE{}aI+n>2Mzw59<Y%S}I;M<TXq?W7)Oy5fe9UwTwpVsIl%NFu3dE2#FgaC?}+
zk&SX6i8ySFWva?>UQS^Rk|At2J`lg?{w{1cvJK^QziPl|YUb?7P3+u%P88G$eNb9_
zLOijXh`$p!@rSNn{?|<DZN>7hOi5h3lG8#DF)-h6nQ^JqyVw{?qeg2{i*!8_92uvN
z@T|y4UlG5>=!3Qn@3^ttcuKvksY|8~+e@N2Zqckd`yUaRs!~=fl_{_o4}_C4Q1va-
zH<-`czIZZKM9Id+jL=Wn<Evw5to(I{7=BM{%|-|2gSZViioi>QO-{vNC~U93ZfR1w
z%syNXsk7X{dk?=T)_=>Z6^?ubxgmm0Cf!6mqKR0C>|TF0D?oA2lua#;lVFgalIuGO
zZYH$@8>PAd5STvjQ~#E6E1N=js0@Pf?>2QDO@f3g5t2F5`}FU;A4zUtVpjSbZWSMX
zi=R6GUJ2AEt_8C@T_n(sKi8gAapD>mZf<zMI$RgiItd#5y`}2rxc?BDF3Q8`2+4`3
zZP(;*86p!bsN62wORGL#xpwkif>_T5cvak~QP5%i2`AMql2K*|8EKOf3704_S<ka@
zV15l;H4Uf_39PrMMQ+(LWtp1^iF3uLZ%BPlN_j7xP(fs>#56MSYAvCo%kt;$j)VWy
zfXahhH>FJK(JA{+Lx34hOj~hN<gtKP@_2tF3L3_AGH4G_epqUM!HCe0s9|}q?^8Ke
z5*|blb-%DnTE;++^|S<h&zY&w=a7F^$ZZ6%K_y7xmyc}vVlV|N>W?=ek)sIWwj|0E
z?Is})3%X8paRXx|_z6BH$G7Ut^>N?bGL?XIj9{7Ct08P-wk}?W-Yze@4ClQl`59V8
zi1n!QZzaVyMI)uMJEzwOI3yqut5!{pXBwLinbdp%4G~`3)bQPqBdR$Knz@pU&AXYe
zDH0Uk7bUSx-uImW7M5kh`%4i(cu+U*jclZ{wJ{Ju64HJ$R+ZhW0hV$?MLYuQ`+eDh
zp08MCI>}0Of>ZP4vm>Lp%|K=QB@mpP6WZ+4rnXxa9I#8E2M|60F<0t|N|m7wrL8me
zkFW0len>;DeJ{^ZX!x7P7E;px^*t_^jHeioy^O-apKXPVPX#~~q4YGYD{pHLI`Mgs
zxT5rp#<`w+{!6CE!t~V*uSDJabFN_&uE2rBcAyL~sGG5Qp4*EM;Q%T_lxXe5lyl2t
zX3#rd4&k$>BQo^IbYuV_0}U<;uDzpDT8Jb{Yl+Y*sn!R=cphv`J_dvmsg|#p;ii9S
zt7Ks5YvI^V%a6=H@LXxIKshL(47<_nFuTh{tG1>gylshoKV7~V%Xl*O1@W4K<x}P*
zhEYEc)j-Z`bknxJHBYSs0&QxtgELk(I`<nr5-ev4$-x+xC*GkYG)w~c@gyyY_u0dP
zFglr^7sqTs)u;->C1*Oq;}in!t}#bdp`+TWECb3pPxE$N*&8a7EfM5f9nS3w0)Xj3
zV!K-ay)N)F>CtlMxJDl6#@wguy)KOdL6Dnw&d_`;?2uEP`v@C+axK!Ffyuf~MY30E
z2`tTtRYj)_5jUs-@3mCyRGw)Q^xl`6E`<Hvage^1v|vX6;^$&9DvCfVf}vx6Y9;Vt
zH{p{%tiPUka)CT%J)$O#cKCD-%i)YB-)g5uhGS76{cK!a#Xl_(8kc=R7Xak-XEKa?
zM^lq*UKQKF>BmxZJ<vaEGr?UvZI1ob=4L-r_O~6!NEeE)?)6mdiJXgA3g}{$G~6Ie
zjaZdeKig(}oKrs9{?i@FQVe1gm>-A^vXUw%9WJ(heBib8LVUzfgHTvE$N6NoW{~n1
zQQSL|$Wu$qY1~%Y*i{U<03l!kb7<hz@17nE8Ot*Zz)Ca<aJonQ)sB|CUl1D;=!ebM
zxHmSuNOgbdr;&DTdiqstX!fV7@{MEarof1F8+o}NuNOD9_z(z}feO*;NT21{`n7?N
z^S*N3GWkMX<Ze3~7Bv=JQA2JY&}*ZDd$&xbQ}dI879!Ldv+Kx!@EcgD0nH_1kcjNi
zj*j+$GxV?um^|^L5P!hFp8?&OQ{Yzc*cYn)njiB}v9zbh#p1vA8KiBnL+sM1ZaC%W
zeC&avo&a$eCK@R}G)ecV+GlwjYD}A5Nm;#!JsVlHqgO7FM99RgAe_1uyN}~Kwqv4O
zSH;6JVJAmJH&PMpsxFGBL+O;tV*8!7YUB5ttOz7X`!mvcFlpolrBg?ROyrBhE&FYU
zah|UFvH~dtyNnnfeN<0c$B6{{EK||zJUiTx^(p1ni=Pt~1Q71*)CfC%fT<mE((ELo
zY!+>Enc4s<DVX2R^ee$Gp0bvl0-oIGaTdX;a@O9(+7-poo{-oAYM<_J&;<+$^`B{j
zVs-qZX3YWni$7Qsw1;px$kAiQiyfOvGNpTH25h=OQQ3YxRSh6Wuo&Dq;XllcW=hH|
zPO0t4!&^JrKJKWP@@XIBEg*SSIQV4C=1%IA_+saE(m+$EeN|pp!hQNYCgrg&2aA3z
z9@n{&<t?bh0#OWUiqYiUo5eLqgBQhvBflL8jcu32?K>uu;(EmctfbxwPpbfBn)!;x
zw|kErpn~(}%rr&s7X_tC?HSBQ!}x{~O^bq?a2ao>>>bPkdr3k^O_O_H&L4EfmCraL
zX(m*Z%9KlujvK-)QxrQvdy`~>2Ko`>^|aN?#6jMDUSy*}x!+Zr3I?)yEHt&68-}|h
zab6<9hdvCnh-;VxMXWfM!1tayFpZ#pB;BCP1@5!k&3RiL)+<O<d0#|b&OGC*hc-)E
zR-d|CO2yfwjK(FCzrong<h^6VB&fNLzBX>Yn3pzX*V;exe%Wkh&<n-3NzV8JL)B#s
zD_g;;^A#BCdM(s<hxeiC?sHzlP;2g1nMkQR+a-j{og;?4JMULsp?}rKgVaVoe2Zpz
zFKM_l_lLGqmCa)BJ>s1GxBaK)_PFR)f*H}AGLdG4i}Cjk{|On&^PCZ=v|wGZ+N6EQ
zG(Fo;rLDi6%*;iy-^`^jnS8XRZt49g6}{5wV{fa`&0RIzi2yjGZ1y#{%Kk5yO+c!Q
zk(Ri$%%u#C`tW-g)o}Xdld|bYsu|K+$kyk9QZd*Y=X0KDgCbZ|M(f|y^CYA)WG&RO
ziVEGkg<ZqBhM*3eg#`j5Y2F+I#Hk2x0f~_bbw&}=j|1D|<P%3eHJtF=-}5CXE44n_
zM67{9fOSWcrbK`#s$-&6Tu*1}2yAYAH!b0XjeacU{NuM2MaK89ZQ2Ul96vQ)4J2m9
zjOJgusW&0lz5wV;HYdMp<~ZJ!;zO)EpRz3w+nkZ$NU`B4{p&2>z|^jxy$vl#1XYY<
zRquO<SN3<zm3IbL4CM&=RI6AS0dvCJ_-3B#wMQUlZaPsd1=u1xv43n$d`_i{trJdW
z%XU{R8&V7@q3K42$U#^y!EAykgP_9b6o%PB?Z7zZ)ve%>0j;~CU%P$KrvB$T*YY-!
zTk<(?f@KGR1$`P@^Loe7NJT$?ilk)GRNzxUbzYsCrNxRB@^Z?dPvn08-Q#@;8_sL`
z^RNVCX?^524{S>N;&cdP0NzO6%n8ERaVB!Z8VC=M4HD7>X1AGcJz1hML{dd&8~rxb
zxER%2=ba_#@VDLQ+a*G0(L@ovm;LcZnQtC9Guod0?CG*XZw`k6uz+~$0>~U3SVu&_
zaaOwa+DB9eYNzRRZxsBG$%dvMdLz4=Lejpr>01pKGjZE4gPXL`6VC!oz1U0%eHskX
zT#WHm0}$#>Dj<;;As)fn(mFBR0Gx2puM3ZdeUJ#z)Uqdlr9V|^l40B9v_dqR3A(F}
zKF$N<0xT;?eP@{h)7_{@&L)dt2t9PY`Z$n_ac9B!5bdSOYEpc|bSO83SnSbxsqcq3
zcJKPYE`E9N<+s0eH1vvtR49ci*x4bC1guU3Ep+haX|2=MoHM2rkG%-c;|ofVa%+bV
zR3U<5C}<L?kL&LA)-*v1SV^Z!fU72^U}Ko<3(f;R)tYv1-=#_|7hqNRIK|$VgO6VK
z8SFhpJocE##OUSPCVx0{3RLj4vGc^6$4j6r1B>@BdtO(Z3}`Duqik#;flfVgE?tVo
zcwJQBSldz6)-tLM*yGG*WAp1iLdJu)WrVNXg9d&jClEDld;S(+o4)V;VB6;9&h;|7
zCy>OQT(qELkf4_6Kq2hvk79t4&5BZiv#K)>{t-0Zz3Ci<jb(o^;<%bIP9V7MyQd*r
z{?krYot8S(oOkFjEN3rm$b}(~ilVFdhfi?T({_8Z1cxqaq)#3`u?8NYtqtE<LztP2
zhT#u}?aL`K)C#6!AlNdWeW12dalm%FT;}vWsbIo+X7F=H&1;crU&>*&!0Cv{0z#4H
zw3*$~$5_KfH45G&Y{4VhMMO*P9DjiF?16>pQiw_Sq^$Ri&)+P}$pDluu?Vo(>GfB)
zJvdd^-LL8e`cYHLmloI9O4QmA%)*hLA0jzi%5>hnK0I2_+qG!#I%Tmy(Mk^b!T4|C
zheg5IbLomL9sTC1K)d#-Jkx8dJgo|K5mf3+7(tL;l4}+Q!sZz)nR^%)e=b8U$lAja
zQoTW4iq`iut$0{18qr@m)v*!y|6mao(C9_PbNZ*d5QXBzNiE2a_PA#F93o)Wtg)~P
zC;x`atndHdtF+H$j!+2}d1#<V+bS^{wd@X6#j6IhN57G)(~yeLHYLQ*(4v=y5wG!i
zhZ{9zb161J9;a!f<>OMIaV?zasIKnkeK+FnT#$rAFS#J{PFF0m8=h|>!SBX73REWN
zcIH(Z8|yTz{PnJWm~;id{zN;=1}YHn2aWVomQL{DLWDCwXY?oCE-&RxB&rH+MNaRr
z#cq=dWA6#Xs?S8%nWxwQd45JN|HpY0B7wB-%gq_!JfRO=F37%@*%aOcA;Xy3ZM?O-
zXI#-zd_JJ~N~{V=em_cSMqp=eg}wu&V%^exK<St?4gPt*<+%C_M9(f?jUoOL+;9~W
zCNA(SNB1-a=y3^%LG=l&DI2y;!JdmMZdznOl)tE4{x%ihkq3(n^bzRxPioJ=FJ20d
z4UYce&wwL78*<WO#mBMz4gY&ncuCLXn(NIx_|a6W(qyqM-1u9xjJTTcGlnYJT-u2)
zdE#41ph;*CvqcQ{f!H7*$ptbN&ij7dM(DkwisBYco*n4khJ{)}%28^2(YAJuY;}`e
zX_|R%oQNj=rNkZ_3h$z*k~o)zpX&CM5v3^akfj)@m{$4RRaz8o&2U|o>gS&C+P)Q_
zXnME2V5XM*QK>4qH!KlDr$4;#f3X5@y?*K8q+Lc%0C0R}UR4J&Ci%c81iCg&iaP8|
z4-RbIgz?rNqH+fZ&)3*USDQV-)n5Yc-fejpe!KeaCKVKg+HDCM?c-->_4{hE%gA?I
zv4ETFQ`7_v4_anMi5)Eglt61+FJl=i9bgff{ey`q!)KyT)@7qRX7ZFWxzL(_Ern%6
z5Nt3U=)wNnp^vnQZTapnP}dx@8}2(WXT3hwj|T0>0H?ItDZMlJ$4o`;y+@NIOdm;p
zHa2{PYr?;qQ@nsrya^RaY?>+kpoD;1=sn%8l{Zp^td`Z2yuamIOjAwxX1XOKjkd8}
z@E#Xsb*iXE6$B7PDp-s`?A)`wW6zxz3;IUydZf^By2=WW9Mc*UM@ViA_c6ZW5Ruio
zZ6jSIfpDHox77O)9Enf)Ww_M|1WRLlrO)y!_{+j+xG{1Ape(#u?Ta?;y}iM&(+Pj0
zZjor&Sivejwk~(eV{=}`ADS`l5Y6Wr)m}a*?_}i?UV;dgqv<(Izq{Vz(;{#)*H&k!
zwehu-I)gM7mM2$%cQ{}}xYx}e-pZBNJ0^5!&R>|odXnPzZIazkVDM2C-6jLfaC`5x
z-5X_KYy{q95%bxR0(6f;hY1@oWJnC!))GNr)ux03e>Kr-bQE9<QrCA?iLhSF?g(es
zjQIFeR;O|Wkb9Bo*sfUJ7S04EU=6x8yTuT?GJU!X)RCzG%>TL&7{SXjTOVGnH*3{l
zk^3c@WA4WbM^0NB&ZMNFLOZY@Zt2NYF*qu#K(2jGPUYpQB-*RYxW(M1vjybb-2?Z5
zj?F4vTpLHye#r??D-={2lpoT4u#IlP<VXPO0Ha`ekBMt}zq4dZEaNT^%Rk_MUF-bv
zP$I!=mOaZPQiEjMwfb8fixP2fX^$j-UOm|dE*dX0<cy`ckU6W#&~~p%7)wWYDs4@m
zKpqYBkFlzIJnfT}@Y^$m{x4}|3mBw@-%_KkBDB@GbYI{TH;}=tIKQK##c|BZucCA_
zR{HQVgaqWlP%m{_mQ=6#<>(S}^QU0zAM0T(@<293t<ar%3JhCU4rlkMzeFEy$i+bo
zIT$I34@eg4qMhpEw8oQ77;;C)ES8mDM(*0JY)`iSyfeGix=@Cb9E@#_IoQ+|{By-K
z<2%PdDgI`S#gb7(*@FmkaM^c+%~l)iv~`L&6umFDL_6dsmS)F!vv+SGD(5D-h1$w4
zJcL|ISBbSd1~uXUEOoEG{kg%1PXK(JqZnmQ!Q;kkOgF_0?#UWlidw7~-2yK7%B^K=
z9>w=HaPM>`5^S)-b5h4k50=GHgwM&UT&P1-7YJW%--?t%_AnSTVTkwTi*78jG@kxj
zk4QS1PDgV9%A{UuP74MbYn>j!vDZ{kxunRAnD$gZrW`QVZs9hJe^wpWoR8KJ;?~ZN
ze*-s+tR^kPRo$<`S+H8yk5z2TmYH#`F7*6pGJ0#o4TnQ>?9cI?PygQ{H_6m6mduyP
zL>*C=$(D&N=*$)+QuT$vwwYo0GQFF=R5~5t^(aj}x%C1#Vqb*tQRX}+w(5N0VBQly
znIaimY*xG(;w7;+$e`NpUCViIf|t&zpvt&susC6m!pUSZ!RDDPpCfa*7weR&S_*RQ
z&z`t4*mJcFrkA9gut_v8egfAVhNqGnor97jSkOw0lo@YEr)}R%pB1}N5$7huMS9b*
z0p^I$-!lL58-1-UWop`W@(C99-U!T>wgoQ5zFB0c;U8B;HNuR2qm^Qw0p0>ixlmL)
q-N`<=RuHEbbUCKAwZlLAIC=Q>_JG$Ucgb?RxuB<x_3r1VGp7iWPXjvu

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_control.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..94faa441f27562207afa976653c0f9cd496d240c
GIT binary patch
literal 47320
zcmV(nK=Qwf6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC{1Do&#<#lO9LmSAV
zL8g~Vb8IPTu(Wz~eT+{A;-v(25i6h)_zM7ctr=cvA07D1HzgO9Y-5%vbGadr4l%pI
zUMr<RiQ?gxGxil3>+CzSKSVxjJ{zLgBDu==`*jrj<Ep?c5Sh4O`=>;1C`vRB0Qj!@
zh7YX3fB%^<Rz5%$v(A9(B;bZb>XztyQ6~wJ7>Hm3`Tiatt9<7a(d~-riT~d`{vsz`
zZd{i*Ej`=rSN%?n&!f7Q4&@P}el*E~_3h=bW{|{Ciq32y8KDBWevJuxNIZ9nxi_9L
z4@d2v69X}pVY9{=#Y=oSzT-HBiQl`vBDdz#Eg)$W0kAe_=X;q|SEbJGEVxBJqA%E_
ziv9xV?--(*YsoG&BHl5ICdFVzY#(hXZTfUqfPg+nK!xof720;y24lY|b&{Y|c<eKB
zZ4uk;_&%%d<UOh^KfQG|j-4MOf3~d*Rx%6&eu(x=)KA!e@BT&UmS<<`a?P~C)OVXd
zc}{S(j)mbi$Eq~LKQ4!xsrl<|1YH46f%guB;*f<vsF3@bdABSf`fl>SJ20OYnW{xk
z<`5;&RI|`;VY&vKW-jEcF_rMS^3=CO1B*~aBH~`?MOfiIQ-NsQ$mc?KFTb=r-rW0B
zHTVqScSy}=39@#O`)~>S-XpEo)!HcqxzxL1g5k)dFBX1jJm-OyidPd+c;;UNyFN_#
zqaS+lf+(F&DAOOcAw7nC?sfP?TzYs;-F+#4)^tnH`e>h0km38;@Chx4{FX+XwqvP{
z!*ZN48!5ZdE@Ar$Z5-qpTTSlYzU%#Cu(=lH5>7$cpsWz4<T@UcIBHL;b<ok0@#!LM
z{ssOky5yZ)vjgEwxfNzP=yy56&}FM*iN3}~7P@A?R~xk<(!_gZZoGKgeh&f-52AjU
znOP=dSHfyGZdKnzz;O-k7Uk*Kci`QWvFov|DQ@n(_El5;^oG`vFzu3b87(hnb9Ia-
z%u5Io7j=LI>huIR$<{3h%6II3b4ZDy&<fg_ND#L0{gO@aUm6<g9TvnJsIe3uJ9g!0
zZ$W-b51C1hnTY(f?{Ax8#WnH#9Cv;~9MZ54)%i%_#d0P44nU{uh%_`6H{8<r;7Nnk
z`tp;v)q;_Or=gi<`t-;g0sQ5t!hHq%UP5$8k8&ud@%HXAJrfhek7TeF;784%PY`{l
zlp9`cT#kHrU3jhqRA~GO`+N(C2QgIAYFsoU2LSoV?-eivYK<@<Q}UxWOB?!UNg5It
zbdusRzx8Akk3%0Mt_nfJ5+(=L?<{Q^$p&#?yPD(-N@&owm=q*#i4=DK0K*2<yqzit
zenpOOuj8dFH7!9JVqwn5&;K(k6J!+9bhp&{x4v^|y2ZN23IMoV54)1D`SGXO_13)e
z1WKOm^VkV}v8F{p2N9vdFh2Xaqq+`}prI71o;+SVT+8k_w^^HpXX)xm=&SjB&$kip
zV!1RwmUtkoILD$AKfOT!`2GX1wT}a4rxiLQqW7GXNq#rz>qX*h?Bk~D9H|EDrMDX%
zP%jCzgiC^+wyur8Bxjmg27EgKLzX>L4h}^i<-r#EnM{8ylM4YUY0pk`(+-iOkZA?o
zzb`|t`LfS7!Pb5vJIor=RB^P<Q-WPho1z7Y`mp;U!(9D(ln7-;e@8-Op3AiqTq%BJ
zJ<i!Xmggd`HQE)3?Da<(n|?UN=s>&7jfBgIc;6>59_=}$Uijlt$ElBO?01W#Aer+w
zSGN)bC8*_RHrD;mC7N&C*c@mC;~CFh^#1FPb?CGvqi4T?!L=M{a5!UwY|FrLiv8{&
zbPB&X8B*gZN~BkJT{EzW#$%=a8^RU}=RF-D1)upzrX>Z8_+Pt#E9d<RREzK!IriHl
zBwouSMQNtGc~5S4D-4PJ2OW-z?@#UGt$HI}ugb~XU=*y~^B|kn%6|g}M@+?8#q^+X
zZwW;5Z*wkzzsH5NP;xB*tJml-XBC^-amL<$t9$BvEDn(Uxj~xbsv*1(^`05|Ku(+B
z1%67`HULI?pxu{EyKWvPPhBRe*gkn6J8X9uF$cr5`j}W$ni>m1Q)2vSm<kH*VOlB*
zhI@<tnWHzRaoC+BK^Hu12Jr6?QSCDHJOby4Sdc<5$6v67{9dimBg8gBj~x^mmdyBt
zcn3{@dF0S)aoB7y0VBOsi^=>OOgApam(w?z*rs<qXKID1hB>nrw=M~$o<=BXF5A&4
zUJ1;96eqz=HeBBaLZP1u$94T#!Ud#!<o-+6S+#dEX}lNEUeDSI{!9n0lY2h>PRU+7
z=VYIiVzzdNGP~{b-b3i5(xWgRV47x{TO~S~mrKZRDBAk?8oIm>|FM-&xG>$Fziz4n
zq3Jz~l_l@JCAATr%qhS_i(P@Pt1^V=Wr}7rAWvWsc$eVbC7_F(JR=3ji({^FPnKQq
z(rVZry3fglImb*bEy|{4mtz+t?M;~CIZTa_27;HglJM&4uzMj*gBYb_*RBff!C4$$
z8<3G@CY-4!iWCwVHj?uX$sNq>g+K=N!Thj-BQ03GEXb8qp{}kjurl>l$?Sz`4U&$9
zI{bzi7KfgB-P2Z;FVk-5XNFYkqn$X*_3LG{fX{E5Z$o<+nrg9%IL@z-_{e`B)F9w7
z1CBHRmDqX=tW@sg2b`(c$ZDh$?EBi5M}+Q#38_8zM4_xKoxESRs@UfVkRz#+uHq6d
z{1mpc_VSztU-4M9Tpw~+8Y`Vn0)sGNFgC9uANV0AqaVZ5!t@;#)35CvZ$L)%&Y4VF
zBRBp78cOXO595&jUg+I!M`E%-^BT$#20!mFZ_>!bpscM9?!`oj!u(>eT&$jpQQ_K2
z#5~LqkTT~>i}tFFA(XwC5VeZZVm`%-0$GkQ@NAuvL4yCVA*MGs@Pbi~%sSff8@))8
z$FhNBU|^DBu)xlb<Nk6WflyF7XvZR8Vk}NdI=rFxu#85^BxYGCs6oeD;}?F4rt6is
zbo)DRrg*!ncb=%krpfd2f;{^Hf{{IM(?TJ+MfgPbc6^<K&tT9lwtD|d5=ecp-(G(&
zdLd*Rz%y@*ijkc~Q-i4I)pEs>tx@rrQGunKUJh2-SB3wgqOn}UGbpi8c&)6n)BP1l
z)J9^n(q4)+U~uet7iv6=O^9nniDWqBbnM3=-|ulmh(=vjNBLm>gAW&@FYBUW2er|k
z;)qA-q{CgkvoF~lASi56=Z#JU{EkUFxIQ-!!>i?g<2u-zTEAHQbQ!m^?4=*)1Jq}t
zN06ukg%YYUt?IyO`i4aeI(dDAh<By;(fJnXVmMAmQWtYAl?U6^RL3I_7>7*`G`MmL
zoTaj>Oa$*2?#A+6{i(BESrcD;QNDMipHyc+&6dbdM~cp_89F}70NO_MCW(!c+zoU0
ziYY<_7dUQwQU{=<078vKq4(JUImuA#wd=HCaH%TrJuxQs3tz1RVvYzrCP|zW3X-q<
zCuspL@sU#~Q7${sX>58TCQ1~{)ZlE6s4}S=8bUPlgKhn=*$~CP!*j?nNzc3VzFuxF
zp6LB@FBgYr(-D}$bbL)rQ!XRL(QVTA=a7>0kR{HN`DU*lD<2Fpg&K70?6Xm7*SuBz
zJUiQ?I&UYS^cpOk8Wi3|CGLnnDYV_eKQ$4ferKr1jE7f)(BdftL{Pl?C=gMCm8(uh
zO=oVP5TlL4_le$rh!ga^mm|36O%FU7-rwF%2hj6JDQXTJe4VP;-Hs*{y%pJGv6ozk
zN@7$|0YX8*N4*;LV}75s@Si6uV)p*CV`X8=F!&$wF+AybP*?ZQ*Xp1yg|RRQAC8LS
zo5~$+fI7ri*9TU2@BlLNU}UvIz#}G?HLx~3#a2oQZ>CB;^J1(c6qx_MgPnzyYX+_S
z{g)^T!p@uu=={t)ZV}#GLk^9ZaHC1Lgf*#DeS?D>>Lw%Ik3y?2zC7Lh(dTn;W{)|u
zLRQ!eyGjzmHgNk6h2)LOJFaiHWbmFI?lg7g%d{zNeXY9x@B`jL6B6)2#!;Ju2CR|!
zdd0RKuFIB-olJHm3q-!)AUT@DG>-Mg*t?Z5twqDKra|$so&;S-0rY!x%eP@YRr286
z#$E>cZ%c;9+;I}IRJEqQrMur$-rQ|M7%;P&uBB3>4{Hva^#n)Gy02y;B!Tm}<Pr0e
zVDAwp2G<wL>_#^dNNg0r^;|!DWAi38#6|OGifvK;lFuJbE^Pp`)g4Ad-te;a7pZ*|
z%2NCLH6Z<xLb+7THBNO$x3!cJ=cjT9ivZh8g&uA4op~3J@H_UBQb2+cCKxA(r_59_
zf-eVuQI$IZu{7|XEEioCNxk*Ts{#aVr!?0223kxzEAy#Z?}4`sz)N`ti|xhh`eFEg
zv2u%DMv1v;TLog95SvH!bA@ESwH`F?RfY-MTxm@$D+i&IPo~sBrzn_)`#@0C*viu9
zU}kC)r9PS=46YDeTlkm|)`OFlS_@w%gd+?lRg>9eEOcV<0w+3V2rUAuxo>5H8Ot0-
zry;eeNHC+spV~Ag925D*<t2@-&w+Nx)*^=~j|idp<rs7>Yq`tVoz;H+crUg2dFc!G
z4qm6BqW_ki14slEZx-|TG$bjWDCeYSa`SZ&&u2|@e88o;oAv^<tkXt=zU1<VmtW#=
zkWzkdQj-U833D~4?Z_s29zCIKw1vL$0>zC}+fw6lwaIXt))>(ho}83mm*Lgy){7On
zSrH|ce4G)K6$;K8nt-up+6p2qPEwn&#Sthx6)qdbe|bYtf280moaA|b;zd!_2m)A;
zy0AYIR3H4Dh1wd9+k7n){^Cmm?&zUyZU7EH_#>Ir%pPunfoQG-3XiK4opn0+=c);q
z0A;BfGts%^%hutHW}ch(HFM9H&i)&S%{P^F9;UL#vIk@dO8dLU4YWFE;c=A5g477o
z8AIu!xrUokr=R99upI_WwSvtQp6@%omeN+^jZCUVUvTD`3PjO<Tc512+8Nr32)e=c
znOzw8_bYUsgU2G7VuM76y}l-e(7xd&wl6Tgrd!@)0Lol{A9ck~KA5mO^olusFR;yC
z2l`m#a&G1A=U=`4J2tVj1aVEt*5@>LB)!0FyuqGr^HegRN@m<cK23AZalD{I_S}H#
z5fjie?Dtbdr=5e=aEFt!v97nkBRna?Zp`r}Y^Mmppbrv;gzNZg)>^NXt^fJ_7$wgI
z0nkz|vlEO(q|K>kL%rCQeaFhGtkbu~O<up<Br{+e6Y*%4V5=8MRRC=|iV;rfN@ZEk
zgr8o$G>R`)C#$WXf5&cj6d<zEQsAF#xZSUFo`eQ-A>!u>O1mvrm-v@L;ds4*IM*pn
zmLE0~WBbN-Jr1keg+twN76ML{4Sj;Ssd8?;4Kyepy+FtIH2Qe3KUul-d)w}gWiL;u
z==MnLgGEQe!{EBj1Md_b)or~)Pym(5`WHTW%lcnK5D?4d{Pj!%oe&`k>oOSIv&ygl
zrE@e?ihWoTyb&(J4+&fw0!ja)4Q#vU4Bu@_U$GL;<f@+U;N3131ngze0+!7EI|lK@
zuDhUKg%{~lW9-qS2JIU!Q{4>YFhB`5fP#bVqt}<YnlKIzWB|$Jzu{-FU#9@UPlyn0
ziW~d}r{(2$s5yHmYH^mM&(}$LNnUk_XFX(Xj+f++AY=dI;O)C>OleJJ{2g*w1Ij#i
z-61oBdhDg;BTVqD3X2G(uAO_j=Ek17Zd+VF4%r1j^$-VJqTGZlwa|ND)g^<-M*#ED
z<K^(uak&EaEEEpI0Zs$;bS0xEa0ySUULPFBqW&yHxo!1_{r|DHgkx>DSA}}I+ozsp
zo72Po{HRao=3E0Mk3NP6s4};l(vb$)=mB2|2ql!~H`MbyVKh>jmhUw!3t~A->g4^6
z|B--^8A+CA5*)<f3*|agJ_>lxN(QjJsAbO0#h>KjU3ll5yM!-B8uC<JezIrsP181M
zX=(b>yZpt9rVTyp;y=J&?P2-9SE2doc)jlSn!VXsm~Cepru-4>e#a~Bov99^V{ZO4
z#ZF@|J%jhyasIB+U1H0c_IlUk@8-nP^$fYWog8BSv}UVtwaDPUVorQ6)v(u^l;{=-
zX>RVgvJBSW1*z>*&hC)*TY)fI;`<Ir41uW{&40nVdKE?BM`TcvkH5D0Sv48$!|zeA
z*<M_B0oNiTp;_`>Q?t<<hI0QopPat)VDOt4U2%<Um{M~5#bPio{0H|d2HZ~=y>0HW
z%o}|oJm?NNY7d22)pD_fg61%H9rebl=)x<g#Ro4b2?&M!6%N-IwL<~|&Opq~g}gl1
zP>szx6n@hjvx96Uty<h)kMwpE3ePrjp$~{qf%lo>aj)L|%k{e&KnzQ4s-5R@7h>S0
zn9mvAm4?H*_Ci9G!EqJ_;tn@5G0%8r?9IwqjB$hI&+i%MNweb;O-<W5#?{?R>`+xd
zGzIKuBk&&~q8#n5t<i&K0`@V-t*Ch^^OUuvehu(GzQcx+Feoh@$mUQvmx-QWN@Ub-
zUx=8$YarydnK?M~+`|(nL4DGv;W#+(?nx=$*}UN`c(c6_u5fd0(OE7>cytU=0;c3Y
z9b+r25qY7xkI4p!TUo5kad!>LKYS4&#x8k620JC1e|&N2Crx^`3xBA^L0&S;vvAZo
zLwB#zH%8;w<fO$lrt+$aspYr`ZDq9hn0OOFbKWP<OowE<7DJN$KY%?$r3}t=^XYa)
zB?(sRtt=OnSz=a7yf6svLYDY3-~|H>yRxn&dM3rzlt!|_cLU+DVgf1T$c1?S^)VJN
zzeuYzP4aBhiPu?D@ZE7M49M>C1dpW`%2(9aCsp4624UFDA%Jg@dbUdmhVdjU!MLEr
z&2-GObl(RBi*{uL)9nwmXVw2B-0_2jFF5fy!e#ly5+rPJ1oMJ$J26cpcdg{K{4Y)+
zp=HP<ep;i~_^}a)X^xetA7T1Idmiks>^q~5`1Q-wXA*SlTPaUi!97GnfzDUCk%a5d
zYO%)Ab0Dea1Ky)+$J}r(>S(Jl5;2p%XlH~D)g9-;zUa#pRe?fqH`nGw`taO$?xpp(
zwep5-QD}Nt0{%Z6P)6y^ua%P@%W~-K1hir$+woxtG9&~ACxyOLci8HBh@(VL1XGC_
z77R%k*J9lRIQ|U)Cdx;Z<ee)jqV$2|7T>Wnq4=ol%^HJvJ4-}`1)YG;O5tjaYRjrM
zf6Ng(k}tUrYO<4eoz;v~nlFddMzm^!;hr%qr|$YyQdq?oP(<@ff#~0jL4jho=OZd-
zUKU|kMeOhDF$wJ_UGfCcxL_W<nO|pVsAGluXcCf^3f{YmTGO-Kl#YGXjuSCyiEc}?
z0D=D$+x;FFWQ?X)lsuC2gYQ9mt=s`=hK#-m!cy5WsGHp=K`!Fcsq9keIU&;)5re!f
zP3mElLZ3#g%lP3UkP5NhOC1>lSdeH==<XEMSiLeQnG%8dl0`Qw!y0ZhPG3``@A$$w
zx}fM!QbEZfH%1mSYrUFx(G?BQ;T6Hd=}(NTC8q-?3P%j}$ZZT$VN`h%1kq{8RqE#I
zm?tdf9B%|V2$TUBxSxp-kEm$Vqwj0wv}4YasoeTeyEUz1up$atD$u%aw7ZV}6T#go
zsnGba+LB5DrV=Yvtp2bUE`HKrA~a*x)g)=U2~Q#T+2XvQ!Q~=lUVskP8cUGgLYt-?
zUFNXM#=cl~<2WV(qOSE^LEjMpcM93;G)77;x4ko#aan9+D^)#^gMUF;_y<@25A>_b
zKgx>wKjt8WBuGiy^N9c3^j{qpCHoWTuJM<%+LbMt9u27zkuG(k5$ym*(ktrfl<PFZ
z{9f!)DDr5jf{L~R)=CcWqm$fLPuKOv-@Ic48oTE<)OccM-b6$lTy%&{&(Q287%3!J
zhyoB=j0n16G_x}5d?(hUs2#)jZ|1OcL%xrHOSv*5I)v5UNYtFxMGjGIL1+_rYW!7Y
zLJRK6<nM6GYUdU+tHX0RcC9_hW)d*%)TM(#zp4`5sRnxCn=**STlZ!^MuC@qnC27?
zkKAm|JM7Y2)wqS=2T{yKX*+(P`Ndb`{@aDh;xOjjQ_uich2Lq`vF*qL>Pbo7Z%p}3
zew#G2pUJAv)l~|P1=rH`#-=#xa2r&-^1Kk!7ZLH*DG@8?w`kPY^w1Zbt052zf!8=P
zG?#-AMh$y|>NztcYx;E=UJ2<Pk+g>1#EgJ@#`0hMs4WA!f{nHlC9wm8nT@hSc!0+-
zj!AzRsa@N|kO<Nc%WljErc)*k$Pa+RTX22In$6(C120daQbKG=M55!RD4><+uHLAX
zk(=~i$8mqg%Q67+N;q5fk^+#r3p<st#e=~-Ib-Spzg#%4m|4&ExYl)4_)<)}2#t9)
zvnR7^!p=gct7hsjcdvngR&_1!P9csGKpj*b|6J(mL%K<p=blisrA-Yl$G7FzRRdqq
zDWm(=c*N5$c$*rRUAT8U_WeH{cwApZjSd8><QRt;vI8$MA%))YL*GF{9ZfPbPpSN=
z9@=fwtTTsUuI6z7tLp=t;KyL;af37rA^Rr<+->xXMLlq!dl6&X0)xk5`<zCF8nI}G
z)#OukY+Zm~lvH=|YHI+TT+kaXiz%Jdv;7kn9zFhLXR8tX@J6?v(`E9eUH4H&d5hYW
zDgau+-D{ua6MfUm-Ps%m?7X2X61l=8#|n~(c#Uhyn*qe_nckz+KNkR~>EOB_Bm>2$
zs0<ki@moS5ptWj<t`PMY&K~pg5pMyj1W&n4zQis1>WM|T;xzeR+VypfjjSXCe*DCB
z_f#7*N4LQ@a$y`?<31Z(^zMmD6xM>da-F?3K%YZ4pIGMLSk)(3__>?R;jDNyvLe+O
zW%C1tw$vQf%EvAYKk1^A2{dKJB?;qeL=%G8TRi-!gK*~b{@m~V@W2VAs+WFpr<4{q
z9TpvyDZOW{vz6y|hP{bCz=L7EM+}L5#G@y-&Gr6gB0kuc3q8Qu8X2{i1N~fdP~n?Y
z%QH>dF?VCH)Zm^(gALW9f5?ZFNIKDk8e+Q=Gsi|KH(Ga5oONk*CD6Q{tuVPi7Hh#}
zOl&@mG>jd+B|+EdNhm=w?S(jO_D9__*~n~Gkw4&d_tDiTp8a+kSZhESwp!Mo9wYb4
zC$jKH)SizkLX&T}#X;7=Sv4ic2}_jZ<Owv4kz2thW^4rk8bPIq+ZcGZb8=r{I9rFI
zds4Zl*VAesToe(ocVzm+m$c=4^@s*NBm2$^_p_RLPU2K!dQ69Os^piVK)|-_Vn6@|
zaX^OrqS>h$kkFuFRuA>LD5BtK&9#7Pi2$I2Q7?;PCXuN+Gi7N_`2EXzuU&46*tX!i
zqf|MWK{R6UAd9>gGUzqDCHSqv-LzhpPuAvn*-<)pA`SbeA|n6|C7_%Ks$*L|%d!vb
z=?ni~D~-Iywt^HLimP_}b-c|)RJkRWZ~4JBdGoIZ@F|tFGtuioO0LZO1~i&e%<DGy
z44@i<l7hK4=>z;>i5Dpf+Q@E{H`0RNyU~t{Fg<W{W13mS<@hz+HX=YL4gQ&nO%GX1
zp>eMpTB>CTe<*nFgtOrIql{Q?AF>Bo?Nd}SX&H`**Md8{Ncn{#Ph($0?=`pwnl6@=
z$Y^W2b(<(7?AI)QXSoe$iq9#3a6E6g2LG+Hvjo?@hJ-7h1pv6rnhQ*;%p%PA?<th8
zC(7{c+Vu+tiVTuL|Bhp>3{mnYWuJ9$yXl>vy7k4*dPDqvdew<uEYUox`EZ0$`f3MM
zdiYEhIL&)?+J<X8PUbs3U(hY~nSG{!?(0+JaH+E0jVgufVCmM;z22F_^4cuY@Q1ax
zHgW1$R?_2h*Q4)NSC;wV95wy(zlb#C$k}J1KG)v9`eP;NB~};<d<sr)c<d5BsJRdx
znZ>k~m~iWB$~`Hl$C`T`T0R}xtJZN%(}<*F1D<4Bjm1FoXy2FIfXC+VNOjhqJ@w<<
zbe`{V!hejCQeg~X9F_aGwl04MuV#-BOUY~m@^P&y(2m6FqnL!m+$I?fM$4Iih#kqN
zPYxT>nG^_Uv0FY|Sbwx;ppT?;yaenfN(dzT1Ba2^3(nKGkRCGZ_=gar;GY^w@uKu+
z1#K`7>Jm$OjDh(Hn1Nv=V*rM9+8lgCQ6-UxzE$F#f&=B~8tW(&Qc%?Rv;(NdIX;5E
zkg8a8cD})F7jjG_Nt0*JS;`UUg9G2s4A1PJtc~?kjMuM;R(5^1c_MYT=6oh|<in`~
zlwjFG-O9ZkIJ@^leJfKet7q%5UdI7ahc5G~LW;kf02Fy)t8E^1(S8#53DL5H2Moz}
z`U{D`S@d%lX|RNx58@a`$xz0zx7e2+Or~7`*%vl+z~l5g0q|wAr@fjJ2=VZO55B5?
z#CHmwW-moXa0@ZZar<G5Wzw*}Ob!2uu*Zm7u>X5AhJj>)ITcydVdOFYiGP4UM`<1H
z)e3f-v&7iq_n;V5Ijxg1>9HWv*a_?M^|xSOX+;MOLu(0j*IQt3;CpYtQaJdIU)7An
zs+=XIL4ys^!x-_JrSv_uB@e6j=j~Xi<}z6Y=nQ!PQmRq6WggG63}QVR8}j2(F7Y&j
z!t9bd=p*$q+#pU+`w%DZRwxldP!n75WsT~6nj41@@M`Iv&*CZSHazZ^_zpzIy)ix$
z>c&R;AbvGx<YVD9E+r;{@)L7n;jMy5pJq{5(n(@h7>i3VKYX(u#>4A47S)PTl?!e6
zX_!vc{-;5FuWe}sb#-rBSr(S+<i=9g*Shy%nkN3Itcq^bstwIS*T7E+WUN*ch`z8k
zw*d@7igjVPMBRlaOUou!f&`~K6HF+DLOE<vhdi{i8+-GeR&2MO;n~s&mU%76rV<rf
zn?NQs++&gp9eJ%>wA<4$fPl`J@e=r(<<_6On=%U}<v#Kl#=qZVY`9r<!;tfAv<Tuu
zRa>=UnZ}_5M3%31_R)Y!@&ZFY%egB$`$(s%4Zfl51K#y!PlMuQP)WCmn|xymgIsle
zf)W(R7>))t>*SP)SVOI;skioQ_OCJwmF{Nq)}PSh+d>EaAE3rvR42k_+jV#pmHdKk
z`q8MPcNNeMZ!(M`cqtYreTrSF)6(=NZMBeo7sVNM-6psOZ1lh@nbQYdWVU^2XRyR*
zZBeCrv>YTNpkl8WS=#i3@~BLU1%dV869)Kw{>j2^<yh|nBk&_9tAmp@e+@y=^q70M
z!y>(v5^wcKj7d7KHx#UZ>X9pT+0mWEMF1gVcr9Xk(8feP9-e1cdQTO8=S2z@AXH^x
zEW6yH-iSySLZ;cbCk118A@oUC+xa87nhBlThSfj%%v~3Xh7G1vtO_$VeKwC304#16
zHzq4$UTGrcy^PMROKI#xn$~uPQTp?{7D;|W=#JO)q?A`cmBvT=iln60G1+Q+ue-CM
z%$RfUCN|X$F=yN|TZ@{g5DALjBhKhnU<`r1LrQ_k2?KeEKrCOi(VCXci2K@7(OmW)
z7C+(xFnQ(5qrl70e>Y`bsfbHbYw=;emW(o(VN|fby&i{F(wh~Ge0f;KLa`MH(UUKG
z?A#yAop=?Oxnf1(9x%XWz13g-|98F0+{mS*d+2)T+HeY2#6@~EQ*VrQQ_DFlA%nvw
z=axfVWkGzOrO)<`%2hxC7D#;C)MyZ>UQgOJMdhF;6O3)Yq?*y{2au%qS0o{<a$7kb
z5EF3#H6l>jQ_W4Te!;JLw%zr(=nk-4uap+pDFlElY(AC4S-mw}sb0p9dzy53qB+xU
z)l*!_t}YG8BlDH&C7-)sY@u=enC%V274Sb*^T+8TWd_X-IB_fbnkN=B2nP$%=32np
zXOu2luO`?}N+f#{3tU%<auDu8rrlZ1&7pU-eO#M^ghpP?yI5Q&{wBw}(H7gB8w=&6
zn5y6hLGIX#sMLLumkfRaKK}edb+o^i>?QhSvNgyXmlcIL<e$vlyR(?qr6f5ZM|HH)
zP&qT8mAwwJ?%&Ip{j{J6%nM7&U-ZDjY9<9bpD5EWr$*kpn4O`&_3DlpuF>1I!C0wY
zV{F6g+5>eXPS7T9fkgbUt2B7Sx`Yn`&a8AzEupV+AyCCuOCKZi_}S?USX&C+AnDAm
z67$hkd6^;2eba5Zrg3|z8svK8m63<-+WD3GptTx3WUQdiDMGSZ^2l+qaWm5-@LGA2
z!Cd9RI<(;6J$HtaVgR7`I*J|JEcpGj)cjl}hbU1Z7hGp(Ye>?sIWL2&hVB)<v9xZA
zoDHy(nL41ar^X&p9RsOTPaJj@yFsptBGGekK@XwpHxvPzSGGM0-_qZ(oiBl}BY~xk
z{5YL~roT0TrW=*o3-aXs|Fc}5RUSI7m`8cIaHh&3Zzf{Qb*5rX;Bcz}bE=6+YnTe!
zR@6W_{*P`Q0Q8b4^bhG-W~(^ay0Ck}7!1w2AT;eG>CjT<K345Q)+$j@FD@!WPbO{4
zkjnbaV~PQs9(7wYe(~S;FjFdh#czF!6ttJQ^x)Au$6+L#5c3rahbRzuo&Nxj@2|XL
z2}#4s^7kzuQ8q_tIpf=wUYP09@(IpLYKDU=caj<se9^#X)UyT4auIG@VyL?=v$a&;
zU4md3=dOJB(eBP$9{7J^6lPIOEU%=buSR0mr}O6WmPiFCv9OMCJytrPhZ<+DrN33`
zw(2)bF}yL+2Q$F<JlS=bqMl2Nz1EwVOh-lG=0SI)(1eQ-tQ%g^9w>0scc5>ZDFe?Q
z5C>MGX4FFu(nw3a10Q$k9^%ZtCaM?=A4_GjmH?K}yj%pA<DkiPaOoKL_<*$VnubQ6
z*Q=W9Dt_r)F-*WF;ycwcQ8X4<oO$>csbcBcm!3>cx9Y1X^4Ey=MeC>D`=#>g;HL&S
zD-0A%QVvHoLgtBQ1NEnYa0Hi)?1#>UA2!~W2@@%hS;F3SnXl?t%j5I-nlNV|`#_*9
z2F|YXC=)aI;yJTGz49Q6w4cNr3rE7`kh_9R*gv3jK#txbi9mh@?sbNz!D9Wzmm!=A
zkR7BKkb;#1tR%yX>|?ncTigl%X{@Y0r^3M1z^es%C`t9D@EhI^_r9v5%!EmKh($t?
zq4J3_4e(S|vegWd(tw<vzSbwu!nY}=$Yl<=5S3rk#V5are{kOOj$RE*mb<Xzg6Pvo
z)vV7brkFgDQN+-;p2?*pY8VFj!ZDEc4g1tTBnxPgEG0W1a}hw0;1y$R5Z?@xi~ziB
z%*sc150&SYGA~;&zz-4YtGA%v?juJk@Vv_<sp|*%sdT{8xm2H4iww|kX<c--fk!!G
z+Tm4to6m+R<TN20eL!I#>mqn@9LAV#=@TH7)I-*gHiaYtlZ0u!F+J`Y4ZLXWK74(;
zOmg&S_r;XQP%kAKMs)>o5X$eq5dqz3d!u?LOi`!SR!;qwV)UHA501(`;?cq)scbp+
z6bub5qC{@xkW^A7XUzT4vJDdq{hBf|+r-I<3@|YpS>UN?{~wZPMoqU_!Uapw{-i-p
z#0e&5KZ10x^y%j`dzy-Mlfg_%G-EqhON2lEj6eB(B1O?Kw~21~gOwbdk;&G|RVIAM
zmxUadd$uOY;4&i00DE*C_wgRJA0RLq8&M?<gb8P%v@cOraqD*e<xM#2wY0w1Nu^)j
z{6`lFDvQ(mAMed(_G$asICEvQEKUaU(Id^6;mBsM4HoaIPU0`NzU@CbELG7~EQTD}
z&L8;R4I6I`VW`;-F#&^zosD~9zAuLoNi)*XQKX3X3cU3r)7FQeV4lN@+@SM6zfez~
zH<^YU#G=z9L~HQ6dOTw)&|+Q6yTvuj2Md_}P9qr$ZfiDq`Uo%W=*VAEqg6z}`_Xf+
zqJ<=mkzw4gPNzj;jtuZ70|{$YN}hwQsVNbX8%pCu(bHTq85)Ju9Wsmb_HlKQ@neC_
za0YGV>tn+Q*N0uxj%!EeSd6v?h#o}U3cy6nlVKk~Bbbk#(Qv-LtD}wQ2{OCUboS#D
z!7;}!Qt3%RJuQLFiaHdNVI)-qA3f@Zp=#g`1rtNE5XT)wR(jvpfV0*Au9y{Zc7kce
zqI4X6a+&-;ENc8fOwJV(B18Yr8X}NA_h2xKS;B(hSGc~iz?{U{j&6xtJZQC;hYId@
zR+tND-e?L#>BORSXL%cw*=jxv(r_u4x<@5MF1d|e$!#3r_QFRLorl%K!d`1?>T@Tv
z5P>|Rw=)m(S25d+R=$iN$-6Na<@QQluBdakg*f?bAu1#mR;sEF+z8X;bY%9T@enLo
z1A&mxhE1|HcZC!B5Y_Z+A~5yawg{5CzVxzUGYG@i+nV~y+5K990YHVi9FB$gOzA4o
z#|AAWst4x?-pM60JnkBQm^^kdEt##JxABO*JOxjBj3;NiX1hF6fpL1j#33~cytR+)
zZXtt5LI5S=8Ki;ywX@N=4wGV&XC&wU9m&haYmw&*kvdeA6i&2|yZk%efyhTSeJosi
zPc{u0z$t1<mPzWMauEv<Sx^Ez<I_OZO^0f~p)vzk9XSDS*a=?)^eeAE{azupM&K+S
zgWx$Xp7X~iSBS>meeeUjyy2Qdk5VQQQ{;XNX&U87_s&Dc!qxugE{fy_I6|--lAF%l
zT@O%6@dr{2yNzz#g6!5oI)uFedNFAXw~=Ais)jw<^*&n`OSILD#Hh&2yfuVSS2P(s
zj0604#^=mF5*(fHfBr>W&MkRbBuxF2qvraf{`D^w>jP#uhE6c1X?;0snB~9fK@`pZ
z!X7wL=)%(BZ$<do>%GjAa5nJH;LH~Y#Oo_bp^-^Q;oqf~t2J)*vf(=c%mNKDwur2x
zWbo*nws>TXqh&TEDER};*>P-G#aeIfrv_xQTF+HbQ@Zb+2gkr*rJ)wh%c(}FM3*r0
z4^NTX?Bp}NfYR^bk@h-+&^tPGldVD`Iq)Lp76Dc`i~GQA7sbyFSPDJ-sZW*1pOowX
z*eW1@5Kxh{L#e$<;L?6f@K%u(wE962Opj`^={yIN3^8Y?OG~<mdus)Kb)aK^3!`HX
zh$X3J>0xU>P>8xFU2iaEGeS>BKIwK#7a8k-`ZSt(arOF$RUVyD(4O6L;c<<y`&SII
zu8lnT?0r~Ap%y5zQUHYfA|I?zMH8<)RD-s_=Xl1bsslAUs8~lKG}vm*Zz6vEf;+u{
zw0u$sEep1}rBTFOqW)I97nX$%)#sMSjzb1bUG2THKE1+1KJuw|`+1|-GI~A!51rRQ
z5d+@#LX8H;K5#EGxjscD8Hr-vJycfs2+c2UP7-YLLS2WZ4nG!ZDAk^Ck5vmf{`7ox
z^E|g#DR4Bo&L~O$mjeAC-@)a&Zf{5K(RXy9i@m^pLsUk8?9ms_3@n2W#>zs<rTM~<
z>dU?`j55Hw1`&{%Yvd3>Z-V8Vc~r=PX>P-*{!R-0ov);))g82<QFOdd8M}mrA4>xd
z7ul(zT%j*kVI~z7AC1ap_(a4fK%YbI^0XVe*SQvO5eV3iv`=`*1W*ZA(-%Fj{nCy@
zTn3eHw;Rkkr(z#iBThxp@+d4VV~ZsFP|K>n_uQh)I;=P25*WfU44YcCbaZDqL~kH<
zqmJyTb)<MTOy|4sRm3Tm<S~KpJ~sPhNIYPu2?YgKOk?5ej|cyg?_ci?l9dh(pc<w+
z2Ai>O3Kk*mfsg%`%+W4uE^iB};LhsG1}Ye9ywF{Vy5t0ibe{l=D1C$AwWPV9hyT@r
zj`~_XKeZ6$68mbVf-C+pyy2PmnC!)O1>U}4Qa=FAV&U8Ud7P$(6ip2}@?AbhP^Aqx
z`g9=<bA6<1C$UE_Ju$?~I_tSFVAbfYx$c@<GnJ?GZWVfrG}Nl#{g;iJEojOa2hIr>
zvC%5}Q*yB0j)OG*`fK011M0hHJAn%p=IAJpF`MYzj;F$43z3DnA{E?^N%UV-(+Qwq
zkf0nQrulMUt`!Qga0)q8tLBDkycJ(mmgA>jRG<!|zhaxK@QX|}u(KG;1(7-To3I$!
z?_-aH5jzzSxPhA0>XNScG(7@Y$l$+`D$>PBsWi&rA~~&t6=dMble7JQ+<<3`MHxRj
z1INvWUS=`F2jPqcsUs4(5Z_o6WlR$9Le&QxHtTv0gF89!h#Qz~URRC3an!+a9VL-B
zaCA?&yni*nC@VTzO707B*ta&@s8l926QmxzQ?;pLEI7brY`&+Du?A$UNWljGEa3E@
z<Seg9+a}Xb!F1DoH6^Acs$`V<7$i%wh@7efSVIl&g#ktL6@^!<14{H2%N1W8hR0ZF
z_o^S4%4|GHtJ?DB0({Sk{Fet|%0ZPj{5uWZ=A9t|i#g$!3TctYz}sJzXI);oiXa?d
zKDM4g3Yfv66?eKiBCSNLMsclA0tYLa)5qKwog#o6GaWE4=6Q!4v>RdDr}#-Zs(|&%
z6e;0II_CeQn`QMwhb-4}i#KfzVU=B2dJqw0bw=@<$fUjJ{`Pib4NG?|?VBns;ueFd
zC(BhCB`^@5Vd9{@D$rS0@B-VcmvlvZO#Y1DySB}ZA&!|#@sOrad1_jtV6)one6jA@
zkKTsjEbuXpe0x8#pCAUv#K2@!a85-~(R0P}am1t^GzR(mu=-Z)T~3_WUr%_(cc^IF
zv}{R3^T|u~!?s#pFSO;4vqFfNrPeJ6+K1Tcpu~#<Dt{TO7PUBSg_~}8H|XnLRUq&X
zcr0U~bYYPX^FR1<*ZUajhy>Q!;z%@iJnsJtK&0Nd+|YHlJfHs)WpvO1>&ls_d>MV|
z{F`ihTY#T(!yN)v>CuSbCvE~c6!GwrFVK2_{oFZ11r%-(#?sJ?EgjrNfj-qd2N8Pg
z_UUEu_{WENg@RQ6w93Aeu7bQyh%so;P>?pg2uo$ikRV6vt`f|LLICXfx_bqwCS#X^
z^_ORaNgORCXw{Vb3KxR)b?}^nL^trH*2OR9y)04_C5!Z6C>?xcM1eqPs$bJXp~6c+
z=l-?@n0%>u`a>NklF(t#(7QPm8<uG;T;77)PQ{!=zY0#WE>=7eCgirFxmgLb{AtfZ
zn2~g!6T252+-G&LE~*SfK=D_#K*|k>D!P$QX0O8VPK@}$5KNww*s2EX&o4>!Sv!M`
zwdA64bVrEUG4I`4v?8me{EBw|4kzeHOUC=)p(zDVJe>!wk75K&?Z;8IS-nE<FSTmX
zvfQw-a|u#|@xlF9SID#9$~Bk!A{b8#2=1qJ&SuJZPI$zSrU*@2!HCR+>&BIA^)+I`
zEVZ;d`1`1d%>JXD(P=F`Z0IyjYN%u*<y^cym|VE!I9@Rwqq!HU7Dac!705kWrBXus
zs)c&8C_JGn%^x?_6b;NNKfn92WLt-yx_K}UnVF6<ALA@p;9XVRFipu}u^-Ymkdkks
zYcVP}!wUV{g|d=<C;savfGWPXX#C@EhHsq0Apq}OZo2JcG+2F~f+`6<b>ip2!r<?i
z(d>mB1_6Xbyf@_?Kszz9{5+4lXTpbiAg#p&iF09fRycSP*@2ZC1}0tKV<W;k_NqUy
zHf7E_;<F-Kd|DvnNLWQhiUZtkk?m@PNY7nzc;I}@A2KZO(NU8c*39bS_%g5jDGV7T
z82_vzf`uXOZk4ZhvitqJ?tccvwHQ@?9tQU3A9t^y@{pMB4P`m2ETf7LNVf=e{-|xu
zn_FAm(PaQt2&JIntAnu_e_8QKh_3eY59s~(*90F1d3E^xPlrJw%6U#I0F7OhN9|DG
zsnzG)Lf&WV8a-wL-=0%RG2JA<5WG<@zV<7C<Kg<r14Q$0x7^2Z?&86N8rnO~ulQNj
z4(eL)F9by_h$xR}4kt`&=qo1&Z6ay!RwOc=qktZ=E~C>J!*oV7oHxrn9$RAIzuI}I
zR%1IK(<igp*3SxBpSN?doZSy$K?axO)xgW3(KsvqHcnQi3|P;{trFH{Om&W7tWN^(
zo;m+7G^FLFFeY{}s`=GBTxO%i7H56#bjmj6_yKw!O00Jeu#?>(nh9_MnAEi};EoS3
z-bhUr{1#=S%N$`)xV?wrfwqf!5xo+ulH!cRX+?+wW{};&98-wYlYg&(!sp)Hqdqex
zO0{!&2h0{rd>FZ(x`cAlfS`=>ot!rM0z+?&on4T^mj(N5o_9`bBZkMfwV?`K52fAQ
zqo}@LqkcSJ{^=_wbosx4*z$BXJ+&20rjT{C?0s|3EO(+2F9cE1gwLq%w6K5);`im~
zOB8XzdMaD;u|ekkKR#m+)=!hN;7YQwj3o>3%8=!Y#BV`yPYq;c;TBMH$kkx^dJkNn
z*LCvq4?B4(xQA8CbrBI`U6NX*LAabK2gnqyWqe;gbI%SrYzrM+6NHi&RdP?}G}e$z
zfd)En>nuKPSrkoyjcgLK6L5aV1OxG(dhVSFO=qx^?D1xfshN?DV!1AJ3-kis#+Xyx
zC+A}|k?1e%6Qv40L*y9e2+O}l+&I3IhKWy$-5sZTnW?3`y`7IyJjbLgE(mGvZAq)8
zbD<5Rv8DGq)*mT;b$M2%WzI(9$ov(sMr14ae9N?Da-{$O|1eUup69dU(Fy@^z1?LI
zY`IumfFGf|pM?{Pw+WUosR13y?mvUBS9?<yKg6v~e7ypGP!E8hr>kIbSH?$?kXR?K
zIPyik)?A08J_NxM>%{7C0#58;*cqBUre|Fhl@PaPQErg(5$PQ(rCJWL$6&7lCC<iC
zEE}`n=T9?s@jeV+ILmL%dYj+tJr36{dT&Oo7`?;a6sfg(gUnQCzC}S@(L(%)S^-{`
zn=L)Ds6zL5?kGYpOS%f*nhXddQ^+6dV54G6)+LM0KhDzUal+Q1+#9Z#D?5meQkSof
z9_%)ZVFAyj>vD6a{D+4X5A{6UN0RbuJs}h?Mub;prZs>)SWDZnF;+}Q-Q?d)MWtV|
z;$@ZU%Xk&e90qL+XON2fSo7V=M$V4;dfJlRLY2>_p2Omju%OR<^KFu9r;&y|9>fM>
z&*LGdBZT6oofp#P*oca}>F95O__oGw_z}}#iaXm0b(s?6+V~xG?jkVec6*+7(QVwY
zlJcK*4xZ~5#o3wpnGg~~@p!?(zP}{hPfJk8n1k<EO#V;|Afvl-fl;;s`(|`q*P>zS
z7K?v)dd;|h(n5u&uY^rTd5y9q+6t)Scuu`X{*H#Ed4=tdCQ>F>DRPVRR86i6vAw-w
zWjXZCEFv3Q5S>ET%RLGf5mKd2RCfDiDSlR2&(P2%1Zr$|>5txrj$n$^K0Ub~w3rgr
zD?p9$hg}DZRmQCVrChK{s6!>jvk<S!LLhu@P|80PX@KCqx@?fjLsTW&N7gQ)9YQFt
zcPo6<b3Mt+?8ds|y-xyL$2O^s-LZ{)ztkL?{Uq?BuFRB^luyjtiw7NpNuW!_6$fx;
zC#*h)$n!DO0q*?@at!9naW3UK`N7Lf73rDp-As$a??i=9^{ooBi(<G2Z{Qb7-Va$&
zqwb7Bqsf|Yh!nHH0hn3Qw)|{8{dsa-W&7d&j`n$LL*A;pU@erf{5vlRqL=3q7idad
zc7@v=7a{6PVN%(ZEV&_zi{L$Hx;^Ai{zOrj7-nXQw7bJ+QrILbOg~owMox7oo{XdQ
za^&80G`#{D#c7~e2Us!(TV)ulW2C!o@aF0#8nrD%nMQIkj2h)J+5B4d=)=jiXWSFm
z`dXic1%p#b&Q$bkbmor$`A@l0Li@W$J2fyBw3+6uiagzD!&5EB>tMt%eUi76OD|d<
zDhZOP<j*A2QaluoD8}rRBNmi;LK4jG4!7n-#Lsi5S6B0x&ElPT)En%29`_4_=yt8a
z!V;j->#PJL{xh`!r@D1&0jkxYpAujG_X9_(><g_^86nm<O}B0m9f@`FX!9#p_!0-l
zd<^^A;Y>+s;F-19*`a-BGJ~>kefjBui_rs|AFQ?~ur)$ZcUQ%YJ>f-(nblr;j+u*|
z4ANVuqyX8-Y74muy_vP9a3%dKi0=ic$9AH_{lXy=qiq9_FE%#zIcCPSEp1WjyBUQv
z3L&(T-2S}SUy8=#c2JxxeIuiuGJ*e(+aBC+l2o2Zh+QW+b;6gjG|YRwz40nEL>#(`
zzkE~`=ip0*6O|7$h$zONXdL%8tq{(TKS`DAO9cRNh8^hLs03{z7QV9>ruR2#g=-_O
z%mGm$UsO_hW6YsI747WwJ$d<@j^-h|&qLB;CLAI1ra&TY%kQpW^Y(P!Z`MYkt?vWA
zAMc@0J)k^RYI8Kn2J|t+p65RDYm_Y=053q$zo5S&!o-{^AS<*RJIL2v(hke0B7Fln
zIH*mKEIMah7Y}QISD%`1U71zXqH4mau+Y&cK?nIiS*(V8t_DMXjdcUC`1%!rG&1Yi
z+ZEu6>h(@XYo{j{_T%&7r@4|i<^DIw5P@M^iJYchr>>Dew)o}_gwg1VQROeQD6~{H
z6rnC%h`msDEX8PZ)kHJ<bac|+1J;Uwvfb^PT4D&hlHc1t7+jus98_5k*wJbityuH`
zM1VcVzDhFVR=LijuIvd4Zt-luM|}yX<z2oD+_=R4o1*?DMIp+~0@`VeHmo^Muhuwk
zi+&@dk0x=zFS(S-y7GRq3z?e2nvp1G9CPtmzZ3X_F0X&$tspKfpaqGC8ACF7mcFZ(
zC5Rj~IGK|%1hKi|-P8$iAh^bB^W*Kf!w5<*ufT%MT^K)FA*^KNTWA&}1G^$`qvEUJ
zG!KHnhv1e&-&2u<(Shz@_!;jZrpMAmwRRcZL<-lO#(jW*+*7EXj{T{tXz->~scMyz
z`%bQwsH}$n_ngBK#_aM4p-X7{R_xl*xhU&F^^bY+Kmkh8Tn^9Bjq790h<0F1b2UsE
z6|nz!lPdzHBYADt>;sM=^%L?en1>di-;I8Y5!Kbk(H1pri<QXkhxm{4=M}4R2HCIV
z6zPu`{4zLBJ=8H6Dd0%5r_iN4Y<I62R-7cy-_Qv~JlfI7Bw<w9$^xlf?SyoPI|e9E
zvBKDaA;^wLB^%a%La?+9BJ*fNcr!6n$tVjW2X!WyZZ&txgzvVtm({^8J{(%Fc1FPL
z?L1SD!_1STG4Nwo0R!G?9|2!x!;6lO^33^>z;g`<vcS{RDjTHwt4N5Z2AftJjWRCZ
z3lzB`c%1kPD7Ojea&wo?s+1TgDRVyhuT&xx%0C52PUPhb(LcA6BcELK$Bfg%f;mAg
zo~Nl)5xkBvfL^kCn`wi1rwr?##g>VJUOaSLnEmVmjd$mTb`Rb}#>hbjiTvh@<o@f^
zORLtL+V$#GIcj;@Bz?TUbrgPZqL(K#JmnavFBF(em9<b>ZZfnF$;<^ls)A`J5{FVb
zld{EWSWksND;H~~FxY0M524EKWuA3_zr<skZ!0zfAyNuOig7U~AgtiAw940V#GXD>
zqG1cqNueXk;ULVVO_nRn4tpkU#@o57E*nY7Ff%|<Mt7ryK@za;4OVlUmS7ccr73m?
zwD)Ov3EDn4o|%c}42)tTvK|ZDT{Z<Xu@~<HGoOlO<K$>}tzbdp-ee5QcxXJMDIBD4
z-}PD;QHj~f(}O8+J!$aEPQ%4%21@arX!H7$hsA?MU*g^TIg6S&s;ynZ76i;U4DPer
z*GD4FS-8O=+kc^Z#L%0<4Z?wFeq}@3Hn44>WQgB_a1l7M@wCp)JFSNu+pLCD(?^{s
z>5;QYQF{{yhmHQ?>;|@^pp=Cav|F0ZUJB5p2zvWNae?SmL!?m)NDKx2UJ?7nJ~TAO
zC>Yks;#1^!r6Jh@rPsICqhzZ*$*rc*jNJ(}HK9H8oWF4=P44p1*->*5p#kt^@{S&`
z!?<~64|HmeBI`!4^v0oXiHim$4dcAe%N>4bz>cCue^$#6e#H`8MW@GnlBu=kLu8hY
z@*ttPEeZ^xJKJi#p%<%W1rf*Lb_egO+<JlcIK$mmhafxHReLx=J0TLdG+-0`GG!$_
z*K!r+Vw!ebf=HQMxyvX>`%o39(yfVl_x^<^&3hP-w_EGYz9jT!<RIQJ__=hS*Ab2-
zF5*&tBC3i|i}m7MKsqIN27pg{w<KljeR2ZQq-O5dLSC}1%e9#R4-^zf4BYoMty;~y
z`|eiKhBcoGd$?#KeXf4T@ON7AEw`azPE7&G&{$@>W#ugQ<2#(shGEH0c~ZNrcb~1o
zLD2atde`lpiw!=ibc~jIV_P{kny`DU^=)?|2@`UzWoU#^zz}FLE!=C1XQpqWs}$Z0
zYEB{m!>@pkxeI$sIUi`;WC*3nMF9g|HtxA>Zq*WIJ0~IHvB@WNITF>eU~XH0=t%R2
z`J9skw>C?FJKQwIxKnt(=}uQ!t@7~L;!|_N--&CfGmBD;R*)PQPQKfvUgP$l?ghb<
zP1+NlR?A9o>{?8;Ngq>>^qht*@u4k+;nAcaGRR6PO`vWPh5hIfTe!qqzRmI{Ov9%@
z5VwTH*|;Wrb~cV2`>59QCbXnj9P`DYjBeG1zpe~`JG!KtH=6mREeot;Z3S8coob#F
zov8@OV?sIys_*@SrO(k0!j%&#B;O!gsY+tw;(7c%JaHtpCWmnnk3L1dVk<Kn4fJ;1
ztJcg^W)j&kg4QGQBNzsaMI2)3If9E07R+`7|4yVk|52t;?rm1gCDxlQz&|0cE#orN
zp%bthD33P0_jCN9j!8h>_^vCz7NIhD7&=7zd-;;_KX;00PrT0yj7`qLe&NU)zVPwz
zhFb1~{dE9P4LMM<sTij>X|`A~|L|5dyy__r{;zNU_G_qbk}IXd8%K*93RTaZQy!<y
z$nl;arNk>vm076!u1-p407yODiwpgxdNm#%$LRPs=S+HVF?Z>Cs6i$g9|R4oOcd^^
z_eJJLMiWD?M<iWD-nP%|jC2jDsA>^e+<EwWhXX%T6=<C8Q^E?uV0M+<;z(^6)#RX{
zFIN?2oyOh@+nR%FiW9rp0f@f1vD#@iX;nj{=hnu8L~w4zVY9((x<(sJtf0+csaAcW
z7BQ)4-NNiy<W_B#Gz<5iLD=2^P6Y642zcMhq~Xw*ny>l^ls!6TYgsGa;aJssWh#Mg
zY?6j^2VHz<(xN8@R5Mplm!YUIMj{7?4SdNVHQG5^<`aho^oVo$jEgQ7Y$bbm$@HcN
z1X@i%Tqa7p7=v4TBIhRxqcM%5!yD4bfRS|cZ3Z(FAV%_WAXY-hANFJcjvC{;F0ysz
z0I0kkr5l~IeU{NpE@KJd3dRff2zULQys?5oc5`})cP71d#&M43M6WYd!`<JXnX0WT
z-oB9loOmBw)1ccf^TZpr<BZ5!VIw}I)YbatsZy|qGCcNPytgq6uZZxMfQzL#1x(5b
z1UV${gOgkN0&(xC6jUa?z_Zo5|1v8Zwom(m<OBgR&JH<;Qkau^?wB9O23hqG5dx%D
zGvpW^+MQvV{6Kz{mesm*KvC>d1Viu-y@6>Fu?^ACG3qu=EN8kG(@YorB-*z{!ig&{
z3lD?m(9Nw2Ej-esv~7a+z_6ea70uv#0$r)(^)wQY5;vqNfJIu-Ekm8X-Yj&mo2tim
zqxeM!PzGP5<Rk$*H7AA;Oiru6yu7Bb{1;&rXP^2--hzjCbr+MVR-2NHs&54GK?cUq
zrsDl^7zH>2s(UbcC@BdbyyGA*>e>G|F5EyFIyh@oHyW}TibvS-vec{fAIaBpjcm&2
zk>kS>o@@8T959&$-I^<{qxK0-p}1P^(~t&|Eal&xxw7N1fcZ|n_e@N3=L@)VF;6Il
zTqCenOFFpAYY_m|=!h2%^&0}-hO?AuG^<Fl1`v%|!Ap_eFXa=hU3|^Ix6T`;Y%$<n
z>vAc2SljKaPH2F7s7=bPL_&0BZ8CzoA=FA3Bvy3ecEM`H6b?cU8pOzS=oRx)3ezHd
zL5T)JtoF91$1lLOb0x;p7z#hP`!pP_#`{mLpoc;zbN7Cyc_M6D#47C_)+_=a{-GyO
zE*5&R6Tdx*)dm7Xk`QoRkpIDYi{JER#}H;!OEiTDyLY7$0+F<pae1}#!liS)&+dw_
z_ILg_Z%oDs(ggSXwb<Z2BE`IdFt?VIK+x%F;rWzSB|gbTz&#`47a&vNg>NGpJamA7
zhZ)w~fqq}2!X<{m1+!PMSKA2bWcJ{3h4XYSZ~iRb`LSfvkyM1_(`L;(QU?4p0L7#I
zCTB4a89&x7VA7hp&DDmJg|$zML5Sxhq0#f>_WO>({1b_uCrl7YOMFYmREcBq%>bJq
zL0jjMb|bs6{^MR;*%<jKg~cVO8<*c8a6QSL{xL5XG31#E631u-5j0{bl2r<&rqhSP
z2uV4xnm*6B=iNon&fl^5%d>*{9sS3oK?5UX*ugIOmDO6vyL#>2k$tu!YKl);#-U30
zf>?Pa>B;#hO5iIEV}Jn<Q}b^G#kOX{sDb3dY}U|}7t*|cF&2%0a=~1`o&Y(=F?6wY
zH~{Dj4H0z;qFb#cv1;DR05CFZjv|@f?JmDFpd>%N$O(u}sUi%%(Yj4`h(|H;GJBRk
zT-T8c7Aoo@{zmrEc^{g;hLS*`8OAT&B(zdp=VG5+JP|i!AeIO2AH_5<b5yQ#vm(G@
z3()<b3`gS#Bc$o=>W0Eg=R-*EIIcEfCWH}ftr%h3%lDxMv^402ttP=WJzN>a{9iNN
z_q^4yL%Ljsrx9~H_YaP$ZVnh|$Udmlm@BV*rtO#?g;!<JwXG=-tIL4=<%TA(ijfwI
zwv82A4%iJ@e5F?G^R{88YaUdwrolrHU3V)AEXnKPmkMU8^ErGCJgzwSanlR5^UTgB
zGg@B<4-8hIq%04q6qcgC;9Wr2w}Js@MYY|tIUv9Qi#lCR?l%_SeHfo9aKghde9RTm
zS$dXUGt+Ed&<KGqTn(A_AX-)b1xW`3VFo5H@*;}J<zKbu{X<h~`sDh;t0=J11c2p6
z4fl@q#ElQCx>g{mW;B<4fpvqYxsrR+w&q>du%}5BxXkLbSv7$rGT&p3{l5=hk&?#r
zE-XDD7io=1L-xkH;Yt^zvd`<h13yhGAMh83{YsY?3m|W;?gowc7~W;EUo4wkXNVi<
zC}9HXdM~iimry4rNOk}9NgQF(-Q{Qp<oiNnhB0NL>2U{f24mpBA26{<7;rnm=`Z`u
zRD}5N0S=Es2is32-DvM2<DN{``f>wPK{F)@St0dqvYl9c7b=tv-WUQ6NwX9<p(yh@
zIapPc_0qfQe+e`$+Ig4Xu_8Qbq5JuMq>^S(7%J;}sdhwAf9Y|uW{krU={~Z=1rcvr
z7JYrlD?yB`oHpL&4#o@!vgd|rp`WnYyAW#ZrF2mjq2v$uhhS2DDKS`#;XWTUfdEge
zTr(24(rf?PY{)!7TQhI@NQu=Auxub3QmWJSMSge{zPtv|OR@x-&mnU`N`L-im19Wk
zUHgGo-*6uHmv8l(M59JpyKTVzT0OFJM_>{;p+)FH*k+fzYzQ2TwtwMe0RN(&G1X^O
z_F8taRfhc;|31dp9?jt)JaYu%hcxv}D26e1U*)0gIz2-8n!jcyD9tz*;bk<yso{Gg
zvk7>CzWl90<~s+PV%+l0`A$_KJ0U0ALTw~JT&{Cc=O3CUVbHZFlOj5XXkl_htC#vJ
z92M->Vb7j$bXWih8VrI1d5fDRx!^%Fx`T|fIdqdy3!C^F5%akrLE%8ecK{yyhTFu3
zrOT=~@P9712*SUb^fTL**s5K)g&}dnJ!CES(2p8+X6{~OE~G#siz=x|Jd*8Y=|*g1
zUoe6}Yi`Jnbsj?MNkfJ~bh_AOyeXb-!BBov#$aE941DKX;-v_gh>LHNpjHrlqwTxe
z(z_f-2d84;fP}__Fb^%39&Tq^Ivc2<kF{ca%uAI}!7WK$CRD*Rbv*Nz_{b>)<<b-N
z=?EK_J1N>h=q-^?;Np;bpVD;(JPS9ivBL^>1u*VoKKX2fs;p$gBM*^5I1$aefe1qX
z0K&gZ)M-*%Unz;XBz#E62v<N6vU+QW3TAf5MkYYEJiDwNVVSFe!nrn^HMdI539Orq
zQgC+A_U^c^Ax9j<)HIkWOJW|cspJ?#kQv;qn&Y0)BAMSiGeIJmdhhZ8D?K#jQc@}*
zrvva`Z`hUjV=ZwSDHon#cW1)7GSJxqLvWYc-<g>8b*}$tEusFb1Zlbju1axf5k_gk
z%er2RUk+VpZVnzbzEv+*MejYSRAp5%l>qQ{d7MT=X|%+TZ|EN4dl7beTJ~HNE4_5(
z5=bJfAs}--Erq|c@N}V-Uc^-4Z~k-HC_NC7d_jF$8puyq!q~O+%fpC3*0P`_nW4g2
zaRGTK-J5=RpnF<+jFL+523EPOc!VR9BcEM~31lzrZ=qB>>p52O(|%-lcuuyYj{8E*
zr-eTdqwsr#<UpR<APT&ByR;TEhlC(Ig#k~dTxG^4JU!?LXgCn)eW_05$Cb&*^)Mt2
zi`fM^xPQNL!(4%@+KbZpaE0a=CnXmH@$t3Uoxz()S4YaWnkmZ>%yl{P%(j=JQnd|=
zxpd5k9hfqy8j9euT}TvR<0GUx7}$&W1A)K~H@)h9RY@VcGgGisYQ~qC7V#1^_^=!U
zTIM6}AT2SKNRgK5U`wkPoTI$iGZ2c+_{+G9GW?AA#o3FQQ#|M2y~Ku-ut)6S@!DjB
zphv51kDC4G>-vnA<Na7BPY;nbA6f4z46s&<;CX+xuWjj`m3{|;IE{3#p$y~AuB(aD
zL2@I-@yeG)0D{mx*lMO)kLt=5rqgQo-{Nc<VD~uL@gDaFe!Y^Lqx+&%{X%Nt3K7wO
z@jSY1N_m<#bKm&TD<21dFI%_oL8QO}lOLtzqZ-C(r}f(#txyb)L?UQ?Z<CxPZNVg?
z?KJ#pE+>uNM&w!;7~t(H!ik$t@mD10$*EY)c>6%|$0J^#+X+xL@K5Dg4bL8fM?em_
zP!V-O3&uEQG7eId6(nAZ;&(b=pmzA!c2(qP;?!>W<my?E)kiLDqGZziLn983-!Bbj
zYD4@kt75QkHxjqDGvaYdYzydjF}V}raJJ=9m2qhnWn=?P;9#Wq25VtBfy)H2C0yKQ
zgRFL)aGaT<nz?u~r$3Go!rWBtp<xm1Jzic`CJWjL_7f6uePZypfYyryv#t|?sxUt`
zVkyTfS^;+=uMeo@ZVdEV^4Jrp7GN&i=9wcqcR<-fl)aYG!EGs9->2m?grwGuNKAHn
zH07*x7_|b6E7w|m2puTpF0!Ein+0s^;GX^UW5hQw>;76%<X=q{*ncE#X$eQPrFN{X
z1{CD6AVx((2dyMubuCC2?oW~>AeyVQG6hRau(1{og1y%wUXSF>oNz|B|1!!_v<|e;
zXJ>tI-$KIlwH5*>A*MvosbSzXC@Kbgt^zSb+qI%cJ2LW)9(A^{SUxMw4~wqCUFI6J
zMeHjP();jxYBbeOl8gh3nfQKg-KtMzH;J6)DbfkYvMv^(vkt%lU`{N(e^}LkJLU!#
z)JWEieW)2c1d+J<Z=V$-&X6HElU#C3QajvN&dr7uEutj8Hq9&ur_vB>J=~{rn?xp6
z6BKoia4oGPT+-T)MP1F6UM+H(e{?(tV{n&LoZ)o<38f;PbEGvlu=8WhguLQ78m?kb
z52woV?b2z=D*Dg9rbLw>^Iu*&oC}l{CGKVy0ba$PHyyG78AE1c$|}xfn5)MdCtKws
zgknq-DK*L)B@%fEIx;w0+o%Lwz??uN1Sk3m2lfC{lNtm2z!-K8d!HCZseGIB^KbS9
z9`v>MAzJTMlQ)Ls45#I6l^x;=grg7I=@x>1sT8(*Hm0j+z{1VOSyB{M`*XX2TTi*c
z=KxGlaB;x>8sCjQr7r7?J|Gc4$^m;Gho#`I90?KWH;3(%t_40zOu@(Xn??|!X=b4o
zf2e@<ype#vb8BCsLsr=}F+%799tV}cL5+lhXD$&qA!BK<_&7OG|H)Tk`V?$iCLp5O
zS{fj_R#_4(QUP$ti^r6Qqw1{N0`(+gTM+$`psW7CJ-Bb^zMQKqP%z)PgpL%r=syuy
zPUIL8kP}z2me_ycc^y4s#394HrypO7THs|mCB>?W?xE)^eIV-`l#*62pHj=)0p{cd
zZSWmWkO&p5&%?3-sk;=I!$4QjR8$4D+t^o8=0r{cOh4oI^g*f`_y3ew<?2~@c!{;*
z_|%+YD4Uv9Qp)wYNk5>e?K>7b9Mx6wV4l7#eXH`uR8<JO(wSH~t~mp}Jn_=tv2{y>
zNxm4stLQTai*E36wN`jY1(-jOuVVtf42cSnNF$LaAsn<~i!jYR!ZfO@2xE-#CwI&G
z6oieSS8odZz!)XFJK>W-QLlIXfa>Q%f&(+c{J86svHc~;j5(LKjSV)5?nqpuZ^+(m
zdtRr^j^&BN6C3>Sr1inOS8Ph?Rb*!hgsBw3$DZfaGQ!`h<LHtW^(w@xzu&}W{buX7
zBTulnD4-cw|9yrNy+fnNYNJ*2k%O;HqFRWL-Z`s-f!GuMY9{owvD#f7w8LYWjH+Mk
zrmj_f84EK#!rUyLpdqvpGa57_{QUOQ7$CRILUr`#6s?y@GXGN{k82q#nNL;K4)Aq-
z*m+=nbnIcmeX@<*$Wt(|YjX&Q4G#suG-;oA`Nnf894YHLLHVcQD{3nXWt<~q+y+RQ
zW7M{n6NJ0c?{I$;;r<%Vt^9C(Ref`_GKeQYBEVt~Xg3f5yxUaW<(4z@O8t*djw_rg
zoQ&q_Mz1kVi@erMk%*bBLs#u`GBaGF*m!ML&tEJSDvN!6B8954$?lwtfvK3<*~AUo
z7a?<x!g(}qMUqmxJgbR^8%!r)$Jiv(+WtbExNp+qB38}=xIZ)RJuj~xqgZdl)$j!B
z;J*HlBBaWty3R!m6)>s^+n2V6-n45AeFxwviEr?hY8p{nXB9F@f6O)=P6dInjPg#u
zZP02}3%11D7{x^t($VK#_EY#!XwoND`xMSv@7u@y?!OD_4n2*=5Mcz4YAj&cK!uvx
z*sp@)hKR`T*lc$E!H(c-`|0z#{#~$-Qig5W-B`I5>_6<Lh}*TeuJay-n|WbvX(La>
zG8=<z?n4m*vGFC<GfOD@j91*Hc;`1{j8?}Bl^DplSei2idr@k@T!NlMX8w4)9na=W
zC(clUF;yzEGV_v%BH<KwK8G8@wIr0bh1hayIZgAO$?4RZe+<s52)4l^z+;uLD`4n}
zEzr0r<~O#}<mvLJSAIDi)^{sSh&q+OLZ&&rtC){5=YAJ5fnQGUg}cGxCrxy}=c8u0
zAp{>1x1$-o^e<KjIuIZ^^L&cQ8)qyd1eGR>(qT`R>8F=3!5QRc#?7A*iZ%$U1v(yy
zPun*$XB!t%`dOY>(e+%KQA?um+ObRcBg|>-k!}uu1aFen(xWM2bAkx;zx!*UGvXC&
zk}0YVVUp*OMaGVp42O>L6?3RNXnn+E-(VR!h!O&tjw*^@L$mYUUMW1cI?q)8!kf-9
z*Yx3=b?`Iz+z73K`9bdW)c#u=Ue^arxzkuv&Ds#nF_^9Qx74xh`TkaeAP;id378JA
z8e(sHG6&=}UQvzPhdCKNSl1xnCv^#i6&<_556jX++kvYlk3w>43w0e)fJavOIZU3m
z1p;QyW~~zC`U%EvvYg}0@EHv@@!*av`jP$;06&!Km)b|^Qg@b1SDbE3^akwvN`5pP
zbx(=1peeSK@G7M<Km&m;%PLc918K=eD^72WVu6;G!Rvv}Zu&MDFJU$w^H6rFcALQn
zH4Yd<uB_}KpI+f-7s8x~R@)U!Oe^9_RR{a}(fMztYE-I7IZpuLP+>b(TYrT3`4LjA
z|9~`(j-w=BFrU_AIwa6Z-e(u9W{sf)O$wH`K_`!J&rkUl=Ct5fn@`CGiCRK{q1mQ)
zK(1+4Mnk8E>7V5&o)S?PQFzC=t~Q}QFx>m3<o6Zpd}wrMp1Pu-FKAA1=Z6BlM@i+{
zuo@<e0Hzyy-Rh7TDu9^byvor9l%p{K_<6-RxVOiWE$F$h#;MVHrR#=nNvLn;Bt(e%
zR#XYvu+Ag~x4b+&Z5y@<+b0>}st390>@-CR-5YYj;1Nh9f*?|FE>W7KL<Oa$pk0)5
zMofs6Op-P_7uB^edbYbZ+^#A<=J#Wztw@Q`<$#-<xxdA;ooAv2OohE@g9~AIA~N1|
zfPtq<T9=IB=0;$YPse^Qw^C}=wD`uW%xsgY&28kf*~J>wD3Pg9^ZK02JB_L=V3m@|
z&#=%E#gH`>j`W!*_EjL1pyEcA*sq*E_4@@%&akk%VoZas?ro@6o3&<S!xL_<=n;+J
zo&J@=tSU$ZOouN)>Z6!^XtQ$tY%J^owzhVfu|k}y9-62U9B@z7(O}<&pcoD`TpvQg
zn5`hly9Q1Q@x+Hqld#~c*Ex<(<w5Kpp&5kDW~dB&G&AwscnmZ%q81=8yQ-Ui5boiE
z8iTzLZllfFl#tk78IkenBVjN>nDMYf*{~c(^H+&jB9KAV??ycKotNrc%qv?XEE(yz
zw;wp&%xKL2PDZ^pphUaXYd0ymBR}qXJM84Q(ANc9ti(gFZ^60c!JZ4Q_M`S@1nwO=
z9bqEv@tFD`+Q$XR&V3*gQG%BYJcRxyBQGws8&&JUD~poR=Inm0B_>m=psbHyaZgxH
z%)KY;37fUFbAR~QsMkM!UiW9bL&`)59*b-gE8L61_)k+@G}^sl?j1F4hI0~p<VuVP
z_L4ZvKlNi>S-}4<O%K%4u>-y4P@rxo>gHMy#+8=3FPvKM_8fH-$KxGvqbct11dRco
zYtk8t?%x>&XGWh95uNQ$#2|P^8$-R&y8sg0!RsFPig80@OlACX|3;6L6qSP;WAn9p
z3JpgS>wTW2{3=<Ffgd6%hPJqzw``1PPMVe<{<q%a2#MQXl{3A6LKj-+Q@+g{w~I<>
zNYWzb1Zgo!0D<rty=R6!r9nDPxQq{GyrU74hAvc4@q1w}vAj-0tq!ZTBYfMGzn`*=
zOd*f^hA31CcDyeScoix*m}4=}#+?91H+sbZ*QEUSDLg1Ytz<aGi8FRq7n9cktA(C)
zTkmq2bGu&iZ=g1J&IhKJMQ^Sn6it!#zRE<_ThPk0G5@O`bON`0znqaJS5T-aA)w<C
z1?|0Cc0~Ey_Y>2Q_t#SwDmy5#eLFxNomqrzLtlkln7ATap!?Hgghi>3{;uEqPs~sz
z_}BUlP#(BzpEC4@+v--MYKKQ6=tSe4QtBNGxoUr)L2R>+?T6nmuJ+%S1>z06>hm-4
z+!xS#rNs=$W78dw#$>@Qni4(1OpM=EitRTz0h4xElW%_~<!=(i4W@>p&!YBJ+}|Z=
z4=mjU0gdt9R1PG@4}(Eu-~M!*d;9P+&-jo(OddBoi$TACZSy5yt1+y`uT9H0mkLxY
z4k5yZ9c|T`Rm)L#xha_!S1a@n2zQ~zW78&ZuSUGlh9m>!zF2)N9ya8HeLmLDU8qix
zX-l%p9rAp?PMAgUYI~AFmm_rzERuN8V-G}c4kRavM!hnY8S4aP&$}?$&NFj5q3$8Z
zNFt|r7APRc1gIfnCiMSuj@ipU?`hRIRPYwi;wZOay$N1&z5_47`ZVoNt4|AoXd|>f
zz-QMOt)4DqN(0|6Mz2~)ua2^TgP788DBa9MOt2}rvHHe`@oS^G%$boKKiekJR;Feh
z(c`y$@*Qf`1HUq)c5mFiOEbcl73mcjVqkdmInm~(x3cBo^mQSJ`R89{!gkpBA9qsb
zEhKXfBTVhxE?<c;#xQSHDC3*Nat!yjnJrUhAfo=kKS|vs<k?<61D%9P;ZHX2#>mh)
zOAu0K8V)2c#tdClLy8%X3VqA&gPS8gx??6zyZVkM$rUDDV(?l1;eA44hoI2?Il&o@
z!SKh&9b<-|HIh7URqVhPRq=EfgD77S3-N@P8&-n$6*q-@EDrhM#EJeO$5^7A)7h;h
zpwyG2pg-GJOUZGoZg9P>2kMu!RfmKMsU%wt0K%Bh0LMT}40@{L4i8T!%>vJfb1-%y
z^|G8oW|nOPH%e5hVsjR{a%UUFiX}Husv`X6yWZn^1Iq0m#YQ`B0sRWq7k>+3mY<)=
zZK;CSKm&Ih)O2>gvxwQ`HYUkOzuzMyy-FBGVvV@+oJ<HKD7b^<gf@FwFu9S}UMzc1
zDG~u1^Nx<lr^1Fsxexj5;NUUP6Zvyj`g@671d50-N##<wXY9?>w3eh8wE@CyZTzPs
zN~<lcEV)m@jz~`(CO);-xZaU(x<NkR3oN^gkZA=hi{zi`rr1rK!j;#E-iKkMBfAJn
ze+^ailepnqzau{+ovZN#Uccu}YaV_EHEMaj%k*z|(GpJFH5(@ZB4g6e|DoZy$z(>?
z;tLWC4bk1$#Lte-Tp!_|v5QgIv|yHpu$w(=a}ONjUUbb99Ktb%5m6pzFBt%nEm?h5
z4CT>sM$>89o#ILgTzQSuu<qm9c-7Ic+P152?^aL*A>9?8U48{DRpi+vc&7BF4X|@U
zvdD$7bDytJM0?uvCMWO+P5J6BP6`>dgoyU-LfywaR%<^{3dDOK6qHHze1CD%XhnsW
zeXqQ>P;+m%a5KA?==JOSQ_)<UocXiA^m&ZdzQA-!Qm=7qRsZ7Bpyfs7?7bqCrAn?7
z0k$U#-Do)TI~H=2z+;%;8sVn_#CBMRWWfSD!Jt>I;_zRpfspRN?43`W00*#>lOad@
zktzXK@_bWCT6^<ihEaIPL2pYmL~`)*fvoGy=iNs^PO@%;*6jr5?i2^#-H)-OjWCr$
zgy)|@9ZORugGVh<AeZ8X>ST$|WfVh^ZgFG91ur)!rq=YH+Z>#P7t6Se!u3CBCs=0L
z3fm@(oJk;350Gr)dOwThDJUj10}3s;w)BAm;cD&eZWqgsJrSpg@~n#edxTr~Gb?Hj
zclaa3^8|SN4o!UEx8rDRgNii&*xkintN5~F1{)InX_FC(VOlOm_0|O-S9fPwelKwL
zpukK8DLDw)Z$MS%&S+7WR+07SAv0gU3t&fKTnkE7mT-Nvwsd^Q=(ec4QWRy*t-9p8
z0vKGZ*^dG(61mooR7igD1L)F<%JSBWdSfSG?gCPL&d*&LXsiy7+KIx9<ftAn6mg1@
zI*_e)w|)6N_f&)lk;X2SUqS4^z7H4e{u8mm1QZLWjPSH{Tg4Cf5uf<6z^?)6paE#m
zN+RNp>YYL&KN6YQ-yO>N(?7|+{(ru6yyq50w#H`1-H7n|x{Rb7SOJ_SsEYBQ-}9fw
zgI6efgj9H8iQCB^aREPxf4fx0;aN@VA9&e06^Ymm`{rekP9}Cai~Dgle2r4gKJg@Z
zIl8CY3o2an1@8Ln_`D%d4|^~!UoDC@z@qx~j217dK{Nj7J?8X>H`WUNP?EO~<-{zy
zw|W=M-}EGu<+njp2KjH;Nw)Z7XUdRHY?GoMYsnkyx`EI+obbmq$lY`61oI^Vl9YGC
z@IiwW4Wmjraekn=I*bLIUM<;7sC|C!=G;I|G=zgVN9|3$-MEPM>m+gCcWpC_wDteB
zkVFzp9QKCw5lt$<7^%CHrn?H`pl6B#UuZvj<OVbzdJS$Jg&pIT4fAB!Dys{Zb3J5Z
z+z_3KgxXB+XIP{Q6Y<VL6PsMlcz(5!O}L+0+2?AGpWD1K2I{EEP=IwIsD-k1x>e2^
z%Eg)#JbjBd3y<)NF~0DU(!?Fmdbl!r%a(sVetQm&&3D&LU=vMpd7T&5x*Ddran@UJ
z^blj(?CROysptMKtX396nWnQ%r_I4)!s)0F0%UC3Mk!8)=Oi-`W^-D`z@5=wA1NL*
zz=~i`)itTD$mv|jvYUt|)nxvWnro-r5R)h9!bG0KH`JMpYjFNKg)zEApj#Kid5%mx
zqPaRnmDB|<sI4FX!I|e`yyS<L^1Y)|2qpjg+X=*WDGS(F<-MhA?Rv$km-1(b2wo$C
zq~1t5JJkv+^2nE~ZXb%~>}V2l^)5eogPw)m=q^{9>5dybs{zAwAeH+QS@8R-9D^K+
z*qZnzO8s40sca@Pt^U1DB$j=WXWCgAb|nSJVu#H<*)7y0k%s13^7E5G5~z6^_Di2B
zxLfGv1ES0Xwq1!Yob*1<v*l9~MJ(@Mo%tZ9X>t6!j2nJHhIkPG3fbm$2`K3ur6r8-
z&^SMTH!9YyNng-nGVn9g&tGt%FT!TnV$I1Tdt62G@)v4TCg|R^V!w<>4fGYkEMHLR
zKD{eT5axpJMVXZyH*nTYpOw9?*9TW8-UQmwV0FK!5{Us&2z<U;CyK{xci(!*bwf5{
zB$WlQd#?1m0Ub4Up#B>h+{ITSz{A67qzyWGakTXzf?>W_a^uj3b`BwLv_zf~X&At!
zsp=@@J#dFP9gE)<i*n%0Z5nuXO4L$<vBW){62e59>lnM;)=I?WzPy{9x@751FLZt1
zn~qA<=M$KTes}q5$e$D3bjd*I;!vnFhJPc<+(z$LbYx#TeQ(%*I}q`5!xA&|lMsI?
zzc6=KR}dU)eP!4nMs9f+yvn$qJtLA&uFT!^7qY$Ubp-4$Q&!=#xk!1pHN}KKh3Ti6
zA$vPuVP~iVOcJ&sIQiU6SzJ$-&YaZc4O&rU5BCnBA7Z=2@2@P$soe>zXiR~Zxqyps
zqq&|+A=2{7fXBP|0QgLof&~y!C`A!@UirT3@?PKRsY1O+OeR}VfK~Jhbt|zF99dm+
zR<?>0vH4ND&vhxwE`})kpZ}yi=$w7)CAK+<+u0<b$of(y<Q?VQUDimxVLgiLHa@rc
zi$ue=ah}*UI+Z*dreiwFi|gQy6I3PYl>}$6b~i6J!yNnzpcj1v;NNF4gP5JzD04>k
z1Sr?X2j;>9y=K53VBwCGVHA5441MN<ZBKP1(k%U3F_$4#K6}l5un0sEiNsmQ_+ghs
z!im0|^13xd5_12lalbuYWe<LBRcHvgA*q`;C|}3jaywdLvWMar`Mk+OoKe4eO>HzM
zJ&FJouke~+=iL(6m2`dyi?AI*n8nYRhLGC7Q{$t@EY~qqdk%8gGDcbQ)*&2EpET$Z
zV}=-2mVP&9`q(jUNRsKHzI+GD0IxmYb%hr^E-%H{qP4c~7}ISs{vZr;W|?rVJ<y(D
z^p}x&It0=r<d9?o7-;-#f>k8uAE4<MuP?GyO(yx~Ix*8w!I%$CYv-~hr5}AvS*VGB
zHX&|v-jY3=u^a`goFS-KAz?W**#0#=6-ET<M<PZ0A?UUM8`}(}2pD0O9|Wqr<!NV5
z9Tuk~SS|E|$ck*J^o+9-e_R`YdgLHGOY0Ef!njb;;&SAAY@+#&j$-QxIQj(AwX@ml
zq=RoBW>?~`NcPq!ITz0q;dUvma`&4s!l86Baw)K()#EW%OrBv$$8n{h@?!M5BrqMS
zqfBZtK?wbY4GWHIsA=9KdUJ};wPDG*lMRLVh6I_X!WXieJ!8mZ1zWKmwm!Yg#)D%R
z+Np^z_J)o;7q^le(k2aRJt<d#UFzMiNR2?C^Yii%#eqTO#;Qlg_TS)cQ>srdOvZNl
z3@8nsLz}4_B=*o!hRs-|Y#1aoUR;osa;;|ZUB=gt{(1^}S8R2M)8H5Ov`Plm??vNC
z*#x!@!J1N05>wfl!j6+rvKhFS=SfIHbnX!7pG%}tYh0{z$Npa2sHy^D>JXHBx$*XQ
zK=3BCd-EL3Ji0Kk4vjme1;S#=B-c*gH-Xnkp3hzoPH{&!BVL*Ttf-dHE#^QGF=qm?
zapi8@>`oTMIZTW|D(Q-NrR2Vanw_iUiqH}*ep`f3Q&!ou@?JRTpM@UQ2QFQNTb$79
zrR_ZYID<x6Yhvd%_i<aW_Xwj8UI&4wg;xRrEf6Bqf7FK~axPj#(od?<BLqGgrGqPC
zk|ykyFZ&hhph@EE@%rv$QuC2{m~l$BXxoqj;T4Yf9XA$R@u6bGczN~#j-`dW0%wkF
zk3slxRT*KrZsKiXTRq@<05F^86~O0+Q$GogbF0GR6wG}ah+Y6k_5Vy4g>S#6*=~U!
z_z8=2U>Dnu$uf;zGe&9(@>7x~ah)DmoSvdl5%LOzck*Thp*LnsLTUH498AQ)EA-el
zI?{{q@dz|nguATq_2j5Xayya6jyKSDEc*0lswf>DqHWzG<1&dHVnlLS#)_j=3vIqc
zHg)J@raI?JLNcOL<BR^a8xo^}#ocL%Dz<>@5n%31FOl6?Wr{Lb=;331<mAf4xT_0u
z%P_z~^xNo79TjNjVf4C7k@OHonq0}oSgPnJHd7V#5zIryRIAZ4eM<lt{XF5eW?_xG
z!6>=bhty1GRd9xn1czL1eR@l>n+Z!lk4vFTh#AE@B;hkuNnbblwW@+hgMAMtQ$6zz
z4AOW>kZA_6F@}&}JE$p%3<#q))3t78nG%Z+EujR56k;&Ak&S2w&Q0kTgV5FMA{1Vm
z#ZC7IxyTnY$+JzvSI^b;@Rg0Z`Gpr+Mq=uE?;wq*x4UnNNs0#YQ%Nl|!5YNoAF|=a
z0%Dzva7)11uwViI83xwh-1}$rz_9hGC+_4)Po<Btcq*9quCb2wvaXcum1@bhq&<=?
zquwV;<VeNG`X;^P53CWLvBo4|p=C$qff4)~Z5Rj}YDWAu+dLq`eh*_F;cz=8#w@ZE
zF7d+D;ix@Sn*V{#a-PBOH*xlw@RupY8cCc@1MI<8&?A$+^7grpwJ2Goox^oipV(ED
zK{Gg8#VWj}cZw9jnLNsS{^jqz43C$J@`#iifIwV?&WiZ=39FifJitkUKKOH3GR530
zCz4OKgpc#~_~5c0qlI3t^$7;}f3Yd@*qa_%4RR{v{P-V&OgkkVvSE18kyir!Yf_bE
z1W5b-2$#y0HG|!mrZItx1RYwp&KV`w<nqO5%fg!r@!A6+$pUP;_zyA!EP`|a*VkHp
zjJn>^>4F37w>5@@zvya-aQZ7{YWpM$ebrjuX$7om8ODz84WR>{{DAg0l&Ke)W~p(I
zHCtsk_qXr!<92jrwr-!k!b2B>TEUplfYXM{Ze$YAXd`rInke9jW<k5Igme?)-07%s
zfJ&5>5#oNbHwGzXQsoT1>#jP<Jr0PsqkwwI@QusZHBv&im?Kg;*$SE-Z+qKV+pJOp
z7lwVX6-G;wX^F7@a%NmhsD$KP)CjfXvHGnv6C=|~_WQK#pa%FX4-T91Z#c9wEb{C?
zpkPcSG{hgbYh7DO*VUO!L2iW~64W5><VMWTTg6cGYAad8sDXO5%m``J*43_Tn~JTn
ztb#W-;$02d8p=JZe*0hG>nlLA2<Aot1|?FAm`bA&w`8~gdR9XiyX4ccXLa^=LtDcA
zdsfkC{wDEFw)>8*x<Q`(q!r%gqZx7buplZ}ut9Z2HG2&$*)nEChfoIEzqZ;ihm!&#
zRRIal@+~G=a2vz^&oa(P%UT;QyXe6MwnYcU<Ae}n|6$T{?nE-Ljki!W6VY6Z_l<qX
z9Txh;^kOt6oT;3Ze$niAEU_oMp?W$U-^3=<ivyBXk^~@Afwc@AM=;4g+rO1LPVC>{
z=0*RmMc17$gA(;9=mG17b^RBPSWgG`CVwcQ2KCwNgtJf4VYfd{>GpLUGdC;Mc(szL
z=_+g^WLuO(9;<b(`-d`U5-YEK4w1wE)o7Q_NN^_tY>=N{e98kiyu`pk<&e2|fwl8p
zB@eA9rKC!e-J^A|<YlP0-0?cP(578}BE^Cmb_ia3H(hxZFS0hh4G;oiAE>NtgwSQ9
z-b64H7|(u2hp70<!P4Rt0xGQj)VUHa)yHUK2S+@^NgYt0LYSN&R(lGkPno7|*Qv*5
zlws1}uyX^hdfr0`+T>4vq{*AQ0`e!Kg5alxIJwGovJur5(r|oZ`0iyAxG|+?IzIxk
zegcIStR<pF;%vvpg5FPJu~X9;dTrDcAF?^&=6D#&SN8{n_rX;B?Z%dd-qODH&4G0K
z^(@{-M}lleK_PgQMWWS5(56|3VRO&SSF9}Ln5W@XQk9k)4Qi?;m=3sWX6g*wk&n;8
zII*<lgAh{?P{%v!Ta-xcb?EcEPWlmp(^mVBw#Lhy3))Q$^H*<?fI@Vtd+fzzBO{8d
zX-(ZBu&&O|XS>eV2V=AywcfegWI31c>+Dax(&Ow^YVZfSptT#ccKWa&M{cG+Q}nO$
z<It(hJ_5G9)4572X8{dK^|PPu2+VDT2*gg+AR>Fk{qID0N@*)99YbD!213){PclaY
zjZRxgA7;r7oO_8l@HmF%8jO_2+R6W9UFDr{&P#=?cJeog<2YVQ0Vi7#BRbXtcYAWh
zjxvu@rsCNU2F%y3<PCDHEgg)8N-MRUF;wk0g|rEN3=AE@Hko|xC(Aee=zB$ZXJuH8
zAIvy;Q47s<tch>1z!=>4rnk`0B<yQ!_%<y)SiMw!I|Lz-zC7Ci9@Fo)$RzjoqqT06
zOl&JCOF>1vbQCYNDSQ)JP%fu+DLXZ;mB)Cw8u^nBwqw*j>8)YQ103N^DS|hyg8!ci
zS$ok5-}PLjX2uZ>^TM`hqT=)xnbII2g3Vz=V_(rWbfr0w*!qEkSjdpgm#9{EYlrLK
z^;q%kmx)r3`(ZjqbFnI#0H;Gb*VGat>TGH^^#X64wS^|~*O6E8^4$2$+0p2(>BEN!
zgOq7_Q(F52I#5hNM|eM4iY^FlPI{qjmETh1UAe}y7ny0^UOWs)t=YoxjJ9b#=;ROw
zDN1MIhYWerq>y@4y$M6$;i3MFi()qR2=yMIL#P-c0~+fB7C3sVk{IP`%CIlv*36U7
z>v2lhk$#ABWwhWm!j{1*jaat98CacbX@|s#;NU%?!y^5L-OYELl&31PiYbIm==IC^
zj0RAF2h>(GqEAUf9wf|Nes9$m;5NzY7}o-`hv$Hk7=xgw7hc5M)~sOlM2VTMLuQv|
z$l#EA$kQa!>L?<k;X?h|zfGkoe+di41`JO?@{p5QF;?S1gq2?`IdZ%!%@D<)M3rEW
z53-mTzM08fQk?@@rjIu7-ZCumuv<^*l3{<fBXg88B0Ys|By$ve@uQ|-ls?t83uOLg
zpFK@-Y&ivMtFMGnOFrr8nxQH-0ZT2YC!Q5(##l?Uu=@{M6>g*s0CUagjaCx;#LWT1
z7e5-nRfg|M1X|QTya!G_7}Xs;4}@k2@{A5WC-K<uM1#3l=9cNc5N%m?IjnH|@-tA!
z7$^(%IV*`sFH8+~KKFJm7{4T}4`5$UC!eL?jUqF^i;Ke%E#GXJM5iw5(UcpQE-^Mu
zC<zq70E}|%hkE1kHOFGm@M-(~1@Q90NKI7Fk6VGMDfj*}K#Wga_fDD~Ho;jYxU$kn
z#mMK#2)wZz2JX);PUN0OqeY^0Y1!BA<vA>%hHGSce^JF6qb%q-6p)vmR!PyarlQ#r
zzmTpJDEky$b+Tw3oOa(l*VV6va5-F0(Tnru?eg;dx{|Yf@IThtAC_>T8-Xpcu8tGC
zL;fR%2w_C#F69NCYG7JEO;QRJ<{XRNc&JgHx@-~aLfC|4HI+|#y=BVfhxJE2r*AP&
zV7^SfW-hjYI0q$W7{iLjxKc1Rc-B+DfHGd2?2M;N8Bl0a>ZP|odx!*q8Msx1$94m_
z`R!kh{=U%XjQ_X%E0VQOaUN&?J_jh}=Xm(2EJu`r(LUWJy7r}qq9eHyvyELEjmHSn
za(~+;ZHqW#5ihz<bd<XkL8MK>vQI!04+g&%^>g`^p1O2&1N)W0kAY!H6oU>mxbq{g
z#Z)XE=YB%GMPNbIQ-Ui}RnO@bv(!zuuTOJ0<ZnX~(OAWAM6pqX7y=MuRHlB(AEokY
z%Scr0FbO^oalfvZy77h{2C~6<iiiJHv<w^1bvH6-dic*a(dL_8c++O*Ci~3#_SRFU
zK59fFUI0m@R@6R&iR&DP>g}th1s(?Q=MhKvrF1_+i2X8J0Y%pgz6_!Kb^`CmbyCN0
zSj4xqJyzEcIrA8YT0&1;iz@l(9>AHHpdlnpOed!=Pgg@&9@N+w;p>?wwpiZewA>iK
z{I-h<BTfolAu$OBf1Jwn;<}Z+r(zbQ?qUP-^lsw9!XtRjAwa8rs%?^&i4XSDIM{@q
z#=lHlrBrFw9hiJj*#z_}5;gLht9bYVy`CWx9{Bi>Aw!89WwCG>f7*v{qM#wGPj)w&
zw^@x`(_;w%X1LPm@)8gCPNyV$UV4i!>bCc`Jd0BpXRE?AwIKr|BF*NmQMvqRt#%6a
z>yJF+sxRE?`Ka$xH%s|4$tD-|?k1{KP@tsIUjiC3*Y?KB=1r{LMVrP{$r$Y11%&N*
z;Dt$gKBu;FL6W=PVa4cf>zOthca>E}P@11+6v1Y>>i-}<sgXghlhIJq^L5oVf3lbt
zMPQS_IH0aH{lBlMs%9)+Kdk4nvtHhTt3EIH%tDCtmFu5}T?|wL3QJk6h@>I?l#}1s
zkkeTQdS#_#i0;U@*N3H=O`j3Slmh<VS6XVJ4>AU;RBoEc3AKPgDJ3S&><pV|e<L6L
zvIp-;e-_+^JFBC2icB4Sy5L(ep0H5YwOT$B#w;J0fDpUKj(H*!b!@<M5Ezq5sq1Iv
zvN`81{Fq?dABfPq%qzf`s19NsH8Un!&iQ<?hW${@;iB9Slro!j3#_OeY&$o4u2s-2
znON7;>MO9Z>1s$ekCj>sfRMcBp$+tb#B6C0hO#9c4hPFd_r_7czJv+`R{r%Hl^)o^
zk<J8389B1u!GF<k>2Q(B8c1LmNBo$*P!GAwZQr{r=wlON<`dnc37Ml?hN>F<xdQGh
zF)1DlzKQhzUlMUVg}D;*bNv+TV*j+jbnWKEpyUa2^0c;Wg=xK11n~B$*b^fboVieK
z2kd3Qw4k#w$7Op_#7y!q3m{MUA%#K$q6cmN?dA-mkih;sgIxoTW<{z5ee}f5BOF1~
zC?N~Cy6?#$5H^A8+4gF`eh0Je@Gl+H#2QyZeOC)WVS-CSw6ZI@9?^n_bX?L^>8d)%
z{-e1|6R_JT;&i-M+sksp{$UHL(y>~e77y%<OVRa?gD*IOF>JZbr?=w@F`ULSzT<t>
zEC$$$=AN0+GR<PyO#p!A{+uC8`1x~Ll1aXA1s&oZF?gx@yg8sZH)0%Ak<lb*5FA+4
zYzRWt2kN5c6rpX~BD_o1)~UGhY>*LL@}UP46u{$;gji2`xMRPEtww$ZT%?N~R>fA>
zC=@inwh%lku1(=D;23KTzStHE$)|KU2U-boKr-g6)y6IlaxMBT5ozlZf61Qf43?2T
zi(Kpx55pN6;XmIlyHD+4bfM>Ugj^zG<%^|B`>|~~p>1w_+||Yb-p5R5WeUk;e-^Wf
zM<4g(%}Qe`B-VMuy4Cv64pmUg=bFW`&`*@6K@b7~*s!ab71tTK8Ij9y`-qwQE=k&e
z=>M}2Yc5z>J^JSKc8TdaY!#D6hh}jodc!2$ozf76uw1{s7Yc%(rt=gg1EvW9EawfS
z^s+Rlo2ml5zA<v4;u>e5KiXKG71f^Os4~E*`5<=_iUhOY(s;T~I5R)*H<ZCvQ#Vsc
zO%gZQ4-r0g$%15XS>hvH*H*=G(a!R#AIoae|3yy(!+rFVog_yYD>2}0Pq^Zevk3Et
zENw~YUyK24nnRGLa2>G9*v`XO_V@^;^mTq1i~bRE_7b{@*g32@)7P@y21HMVlh%(I
zq3h>BosDF}X#hQ_3{rs-2~?e1#*W7xU=sEu;F_O+Ui>SviG-=84PM1)IKLFeCqtKt
z;uaa9Nmn;TgEc6owAbxrzj(fP)TN>7E&7)e4cdid8$9~q@7DJ1#nNn6JpXHLI!L%+
zeRkGkl=L-hPw&{9QSM|26i4|)up9oCLTPdh<$BdwHVY#3jOfj`1>F=gxz!h*aIUf<
zGfo1=Osb)(4g8w6knj|i;iD&#7zzEuaRxo#5kSSd3-O)$yr^V49M&(DW~^7hatK)v
z|Bf7IV$7M)1QZWn;V<}H%GSLA@%9a&IlmZ_W;5p0L;*)y7u*MVIRhTI^dJp)Vk$;S
zPOe!CK!c`87O5Gv)B-a$R1|+I^iZHO&UIL20h~Bv$J&WLb@CR63F>vncOY5@64&}L
zkbJ}TxX8GJj2(dil<?zHg=9TfVL-e@KG8FrC_m=B_w~v;<ZD*e@!qn0cG^+X$8W!R
zPsKC!$Nu;KKk<<s3HAUrHrRqqaz5B{fw;{nj$PxNk!8wM@1x%fHK)Ygid&<-Ae9ot
zg{>mMa;1a@+vK`PjPmDQyA188i!#Fz&u}I^qtdZ3eQCmkIN@)?gdr9141ghI?)MZE
zZmUrJs-V*@;A9ZVWK9h#upo1fi5#-r)t;MlX#t<<b3K@FEq^ruF>iFq=cc{~7}mB$
z$xhdVRVBiOk0wh@bv*GUB1!oEZ5S^+*s&qg(SBx={;ocpY#UGd@c}sBdB2J8wT!TW
zbXd^WNtR=e)DfkQx7)0NM?gWot7$hH3Y1akL4SX9cqM|dwvtWz?oaeRG`oTP8J$X^
zT~zHU+d9SnK)`31!6^{*GerjfW$pXXitz|Nu0u*kL-Ej;RN#{&jf5e(K%i%AoVmua
zznTAvTIU8rBpjo!W^(GMFRL?L`XsNA>y^+E_f8PD+qN}l>OU|tM&5Bs8nM+p0V63g
zdF~M5f+_H{!sh)&Hlt_uaz&Pp$mMg`{=EV@-aw4jr8bcPBftaHWk+bw0x)0zH8hCO
z44n5HNVOG3^+;_HdOYA>*C|$CR96yFa23=m4MlkJ3at$Xb>tJI9lnO07<L`x41Ywv
zRkbBQn2rv9IyCN;+ZK{Ig6biWKKA+<G<7$Xp&&nb10EW+qQ2EP_T_Eg!wCa@9H9%u
zEL9$>(+?~6<c#>q_79TG?=6;_0N1dpZw=O>)+Vgh4`0M>W#4RHh_b8NKm-xASW$fJ
zp)}7~ElF3YUGo$B49i&=wy+FWHOQ8VM4uk=5|`drGvN7>(`V=a1@u3|>w%L3)eHg(
zPxD%yM#l}l>@(*Zp2~4CapOn&s}U`NCvwC6#h2c{+>i*0TCOM6V%WlloP8c1W5<Lx
zU0>{^e%ig|*Q@*}Us8;LaGtg?h=FuPNTY+J0Q<~4MZafqi%X{#w3iN?itpH<+U~|d
zIRb8CPsM|&qLt^bXw8Pl*|w&x6+t8VYg?ZVmfJSL0;J1m5f=_rbb<;z`2H&dR;w-a
z4p6af>vW1GeBq%(@*-@{H5~=-Ek0^0Lios|o)NQ=^=u(!{~x6G&^c*9X}QK1ag5%r
zRhq-o`6zFdNdrluJGy%%8G)V#`p}A-{YzF|DUvA|>3;gKL<{E*v-H6TbJExtTzi#~
z)uPQIUU3zRU&xVryWPu9Qy0wIU16UZ90Ao7?o~b_hn<TFU5YzjK9D;tOMWW{MF*ah
zdqSDpB&+I1>cFpd7lCd<&}+P=6;iGU%z;cV0cSIVN^IQzs}~axfX4%qa-EjELQ)B4
zpS-!y26}Y+5Nt@&n>4DpU&yi+S>h2bwKLud!97qt2ZoxA=C5Xa9czAHjtQuhw9<)V
z?bF-pr$b+lz`n2YM&(AzlcP(-@JUr-)ej)~_M6L?_hy`?LSwtTveHh|*z>F$Ew0ph
zK$}uT=CvqXbYt>1xXVL*Yer@s-a_ivo%^MC@c`*Bao*9~QtdLlIeQ*BUPvcv0!MKk
z0H0jdC$i1``ZU9Z9551LsIA%@eT8mdR3_azDJ;$aEW*-GrC7iQpPD)Pi3EKBO@<#p
zE-tZ)vKeC+s$w$gZ-88NZ$Im{6+fT%J?fUYJaW$!NPNF?%pf<w0}*ZdqC8qlc}()k
zrNkBeO{}%|#lF|QtEte8RKg;xeK;0y-B<8xt%8mx%*71bX}v0%82nmr6+`3Swqj)k
zI`9*8Z9vu2&0?%4qJpt=;>C<mq3qI(Q%WJj>O}se7tb3aW!;88sn(e!tHCFmc3sl{
z?pQWuG17<fa2twqT#)Q}NfJb_mk5mxPYbpOW@r)w)tBfo-xTc32boa1M3Hy3*HDvd
z{vHAGw-;L;$Ow<MI%2WXjpB_62gN+u{)oJEYo)ezvbR?mG_c^)3Tu1#fVi_QJuR@T
z!nKPR=aq+XTPRg^r;@nZvm8qOSCJ!Rn9M?LQ#ChhYzjLjs%lJZ&l*G2CIOG_{;mSQ
zNjNC?DZglelC7C7I-wVd>yJY`X}oSAl(WASE40T!K!#DJ1HZJ0;nRecx(Ln-LuaJA
zAPkI|SCMrXQMx>U*0(WKmILbsV;=H|@7Zb5*O}4g{h~SdV3AMWz}VD#YJcq?8dCLf
z0S*QMJUUGWOxWUX#TZ7&K^Qz??AnaU-r@SFC?m9_2HEc?(VgF9%GirwY8XMjloOh@
zgp6x}oj9w00RJ~snNkzkkz^4rbKLvVTdLOK(?FvwpT>R53&My$DX~YUW*q9IcwM%N
zrkgax4EeMVycx{JJ9AX6V=%}m;{mQB#_R>yy90A(RQQUUA$Eg|WQ_2<SU!6bEI7Ih
zO!L~!_zGrVUl3DIe_Hw%;uMBNAbxb#b`9>tVk9>+PCM*Q2t9O5z-aV?&O<}E+wIDr
zipq2K1@9PFUsO1yth0yhoKhdn&)iHquqafzLpAkde#jJbePHg_iH2viC85Y`@L0!<
z)4UHaL^?7A9FDBDQm`jC2(-9o@`Ju+kEme1u+jsryDXduvj9~YGD;#$r_3r&b38_m
zuE$!%Zs0&nP<Oql&h##f-Lu?%&LLdAF><uWwiB`PYN*f%$LGft%4}l%^(UY+F^N7$
zp@V!Q{s9-Q<9CKzU;<E_?4H;JF<zj%^JkD1s}viG(s^->c@mHqkmOD-_=6^h1h4}$
z@G6&R!|74stH0(~XpfCvcy4&mQuGj`O{Wuo1Z3zF7e_f(t^I1g@|ycG;AtWakwOp~
zxjbV(+vg?Jl@W-%!!;gu!I*?VG{?A5hRBu!BT_L?n*h>SK%zLb8Knuu$c^fB!K74!
zx|C@vGQL6#AVMfg^yKr}sjJgYF2O<-gjpYKb3d!Ukp0{#g|;BJ06m9IgRY@<L;cUC
zlWbzTMfdeUGIJH?0@;ekjg6K37?gDi$7=nC2Ty)~KOJ<c+qVPDRj|1K#X5IB!`U^!
zZIKk%2+v9=*b>#=Ku2K|5#=%2FyHdH<%`uV5x{A>xF|3b8^TPrj4^u=K|sR?xml|6
znOVtK*WKGCy8d|-fso|kvEJbSW*jFi^a(lojLjs-v}T0<Hr%MtVpIHDa7Xg1gxO+@
zEysWk{%6U{Flr3@YS{2{cV>Q?q2C<85cnoTRd??8ilErWY`JMI&me$>wsAKjF10uh
z$DKXWc7omDtO^wSTMZMQ2FC)WLZBFkSG+gA;X)lV?P}aP)2}`t{Y~VWM;8mbdr_A|
z(RYD+jRffGjkdfj^sT3LAnvp~k~Yg`7jfSn7}jCmv3ns^-ruyL58do>tfdXf0CMlD
zz$$~tOq?G$^G5g)hNOA8t3viweR2VY^wX9CG;`HOrhI)seo{P|-?LqvwMY5wD}VBf
z^gWo^?bv2y>;4g^hAi%sl#abI5J|tv%r#AVW#RHX`6Y9@9~ED1{508T5Aync;05`i
zES{bj+9d3q2kAK8)Z_H?eydO$fUKnBQ_Ca>avhU%yh4bd=M*j$0y*Y0v_euGYZD&H
z^NC}#K)PvHL3RBdU=Ge2^-IL1i#$$L#fa)H*P>Rr%g<JHWiETvzmD3n#K*PJDwuYf
z@_s2uggkd{rCJv??7AwUdL4XySOsDcAX}wBg<e~k4O9jUxx>66EaAkwaNlVcVWF(e
zXdJ=xiladfl_xGdDVOOZ?j0A<tpB!KY+0eyRGj&p>XDb$2v7p34m1K%!VNP<-0kAP
zs_={AeGWIs!Fb?o={qTOSjz1=d>jlEGOisS-tdskhU=5l1*lXNaL3E4MIbJMn_=n`
znMFk{uSb}KbESlL{kcrzCLfZbew&b>=v=2Ul7YVyC(-Nts<h^9&bX(qWB5GW?JY8D
z8(-&XD)In~t4I+RThIO@Gk1z&jiN0$2~OkZ4RrEe#AbTZO<UQ#3?ol<Ju_N_yARm4
zq&a@Y%!K&rVjpd2pwE=gY^t|9xS3mu65H&vV7DDd1=FUAXelY7wE|(1rxS>sGj&nw
zVmXwLx*PcY!JzO#2n{m7)%6{5$1`x}TeBK91Ma62o|Zz5mT*?1MpgN6WuJ`s*>&zB
zv2hIDn_&kyl=(_)Bh=t2nRGiSFFkn{31E}n?_%T*+?nd#OBOp_IvL{6_#UII5D$d`
zrRO1J0dY?a?vhNk!-T@FrPZk1)R5I--O~a9ZvsuRwwT@U+m}&<?xxp2udNvlqf-ai
z<!+>3xD1cZFcgNBom>eg>w5rC_Ae`NSfY=blp=Ym(?bY;9r|GQJ40q9`TegT>%$ol
z;f_-Gj`gcwuTx&Ja>V)V0RO_^hX3BpO;*&ET$+{D%r+)~_Dt~^4oH|{!*@bs8eUs3
zgT<~}4m4$uIN-+a{5%3S=V>c-jr58+F1l?4l5|1Bu0BncuOG6GK_1|O_2CtBCnvo+
z901sm3O{fuuwQON=n?{HhG%=CAz-U-l9uZg0#t7?zKgoRvdQ7Jtj5gw6{U#~FY;#d
zb(|(IKh|#6?zuG)W5GVz)^_>}Q||*e(1%u0xh0z@ld@k*B>2E^_yhHNnA{XCpTfVV
z+~!(6V)`$rbWt1dL!`L(e!FV+$Itngtk;SHS-=5c;Vfbqw(6ulmXd9seo1$0HwG+$
zKAa=3rRehMyA=NDK71;=&CwXzP+4o9Z)qcNE2`A?Afet*IslfDO-0w8qkM9{L8rTk
zOL|M{0fhpvvK;r+)4*Lg>=gG(H=&_??x)%8YOi}XS@O5iei21By{Drr{zG1*FOs}X
zVN|b(U&EUi+$^WD`6Y}1M5*rL3s}nIlJ6K_$^(lwE!>W&h&zlIHf5Z7^TZ)8M>>rh
zGg74rMUzIGcczNGU2~_XR{TZxKd3UL5y{)ns0RUOOjymZj-9V2izFZwVna^voU)Vt
zoS|cVw}B*78!aLv$$XBa0!1*avU*Q<DFy+hVUVt~n<lyH|AIGuY}>H)&i^<5FiFO1
zy>scwlE3!pU5xsMvW*4~C6odQ#DTm!J{(Bc??4)<!3JkCaitcBwH{r$Ook%OGJbP)
z__Q35D^NdIF~izRjJb2^-C|e<LeJ(JB#LU^>Lz7Gq%K~ty$Qjo#+c=ODz!cS#*wFe
zwrb*u8^vqmTc7yGA_t^SZJi3Q)41R9@&-1Vy_qcH1s~z`Pd?h8p+lVlY^JZC!1j%0
z<CXiG^S;O!lsxfZc-b_~o9h;b=o@Zv!p&zk_8j(7ISC~Mvw%pVcV~rP7UD;Of#w&Y
z2nF8uSqR|NXNA>Fs!qzGvXX{u)LY)<DP;f5I`VUi6tl#f27FJ*7dT;D^QG4t_9KI%
z=p|>begEtx40M2VQQCVp(ABaKf-;LzEV~BDyMK**6v=<CDPy_0xFI9{?ri8PJZaJ2
z7XwE#SA&_6+ExuNmM@DO(@!@EFTT!aL1Ceef`xMUg~E$vM(fnIiRVF(Z*~jfysns%
zetHs)Z4Tay56_j;{JXXcOL3p61j$NY&$r0czluN>GAO2<TP2%hk<<iAH?Orl)j%HO
zvc0=+dbzI%#9Aoiror~_ndrj({$!h*?P3Tc2FYb;YL*nX|HcjRh-n<O*2Hi#tP10(
zkFu8~=S=W(imD@^z~+8gKj;D*^@br6Hu1z?Y?U(8*6}B%I2%>Q_K(Kv6=+;WfEF;I
z!n-PBDqS<f2-6O|b-hiPTPFg2w|8?;yj6WbAFlIkjt}Yq;fAdSC%IMxlb?*sO~%Gc
zjw&oB>rCn}v&RI;9w3`Jqz-3n)wf<C$;p$M?-L5qH#y$N#F@dbUZM&B<2UWeHJ=u1
zPx?yk=Rz7%qFulaZ(=pMM6r0G(eM(orZpj;vrYne1GAp|%Z@;(%K4nr{w~s_%O;}@
z>AGTuG=-qp4#Vy8q$u8Az!~Y0FlXR8O<}MgjbVNhCw*Bd@;}KgVgT~bnm*Ak!tM+;
zYnovUQ4MZVH6rRvg`?C-bqk3q)9-mtwPX%?tDA%8nvJlq!)$=O`DU3<VWRo<`8&@f
z0FPiMMGf-vYRp*R%`VQLpRqVa7k{(4k%EpIq~vtjqnX_=3DQj12t*_@mNq_FuevmS
zkwtr`S+PpeXPCOwci&Kfc3@@7A2zy42NMt`g8Z7L^y2IQfb3qpbxMAzmWZygRV=pN
zCY0sP60r|}`&Ck5kJGK`XdM+JpSP52+Zf}FjP9^#bAcIOUg>jVPea>7h-2Z*?t&EB
zoGX!N?Gz{Zr^N3&7U*hx+|^to83fBZgQQH<OZayXoJau896SFweP<U$CE7#bjYVVD
z{3X|6*?_S$o%ENl(M3g%OO8*yk8(dN{y1{AH^+Dvo=i98b=5W?jt>6<f~`mQLCiZz
zqi(qeau%hw0htx(`sFwsg-6z3YoA$Q5EO^Gwyg1<(*8^nZ>Szu=@J-RXl6A07AhZ}
zR-_-Xy+0yj`{ufJpADa;DJ@(tF5R*Z0WZ3DvuhX<0M|akieHrb>;s=f{6F9{Wc|ZU
zcn;qo-gp(Q4H;h>fakJis`;bgu&V9NB43*=faEdIu|S-bWt)bW{sp)v1uigrMfS6&
zn@cayT!K}{_@R;mqAC)*t3+s2(712797f5Qa>z`fF#3}ESU?{&CxXH$F;MhW`9U3+
zD<IBV@>eGgGCS`?9S?h34ii(TPe+3{oR4yow(bd|ib>6ix4kd*mPI6vX9o=AdnLAt
zn4(OChxD;}$wej`zprAPzRvL{DkslR&n?dCa>#5ITtMn1E?Pj6BL;aBOQsEwb6#UA
zYUR<2()i=jmR}=-Hl@TgBo%+bweDzY#S6Z&u^_zew~WVcJmsmrUHUix$;3cJG&T1$
z=<K>s7MNxQp0pJh=u2RTbus%I?nqKbQRk8R$H$iBLXU;YCaF%@jo9QN@^#JkWOxb^
z!U4srr9WT`o~N+?SQxKpaK(2`#X)U;%en-+QFuWlM=*AQQL8tB(CV;&O==ykN~ktA
zAteVLDLMefJ@Jo|Y|ZeeCCYS<#rN&3F1M4n-bz*-m#jfEC&<j;bgt&5TU%5TXQfz0
ze8-M9ZB719EU}ccmcIE}Rjez08>n@gsow&@i*VS2Shc+V+eySd_iwL<x5LESK<Xds
zN&y>xIMLy#FquO@7L;BMRAQE1$A9j2sr{?5<3_0#`fqe=xewB~6!=prJf2iN{7~<$
zN!?5vwF5ixVKrI?H&#FR<Fg5s>c;Nk5r&d$jq&bicsWFNmG_lGvsxO2V8+eTth9Iv
zBtvC!e<BG@)<H_S@GQs1i4#cw#Ez;@SMSl<0r_4AmJRBHBd$tUtMAdTh}<Qo)LH6|
z%3DnUJcT|SVG5eBmOgB4+3Xd?2gCBc#<4G=Cb>w^XSQ-U$Fxm2N}!gdJ}DKx_UQMD
zkHuEacc^JSuo*h82G_%t&J&uH&FO-;-r2ZU0M#lL8h*>&U~y@b0pWo;UBaW$zS*4y
za0ggB=DeVh;T>9I?K1Cq*3Rovg%a0^{)&U;Bcq`QkQ+mW80~-*CL7>GGa26aJvMtt
z%zBzmZ{>0hAZxbQAQ*SX188~8V}URTH`dr}&)a6w^+z}~74)ZNgK^ZvF{!`IGautT
zJ*V5Q@9C`QwfliDUn95eO41=EkuI8v8wAkmSn<1Z0pDua?0gI33N$*flw*t-YE(ix
z{Rd3JCU}SQ2iaaKf~?&i+mU%Z9w$m-Tg2SAK0pI7+_&~u+zz7~Dx}`Dm<MvHgXT7o
z>B}8y>isk8<&A3{mhOdElAq5^uks$NO87sE<;90Scqyh67*p15_1~Sy9yPVS7_z`i
zfNUDZoqA9)-eQDEBgP!!4{c9-=|V%D4R;nXUR<#tJR}}2HQrHK)&ZmFjRfj>0uK#o
z;@tcB=ypMc8^O@jD<D?kYq#CrzY*Y${)4HU_H8{1&IYcU&tVY<9x_bEK2Da>5bczR
z86Wf{7J;hys03*bNfI0;kSOGx5{iOxV~l|If3LY@$*Z_8S_`1Ffp$bzwM<Pfkh|B5
zLy;tRU`I{5n5N8j2s>wtYgST@F0a7;tEW`lmP21?%oV=19+_z&jz7!<vRGkCp0J~T
ztUAX!2`GEwcvS$=0dE}VVlZOBeP`5wGt~)V2?y_a@zn-qDYAoP#AQ!6ub9Y;6Dgt+
zGca2b_p1JWtnoC3eaRtv=Ct|V)|Tcsodm^_{A93KdgV2~307<$0FB-Z>njEyVsqp;
z#(pAH-<49KM2okID0=-+kT=h2OpEj=+K6i6&X%pxfJ6`J({Kp2{TETABjxx9zg-yp
z4EkI_MUFpFJ8i<mq~XX@glG)%Ya(recoI|%4D_NWCidzT-um+~6!6r9X5OF1GDWc5
zJ0)x#^iqXQb|-N*ZmAKRxQIu|y*1#NgG6^QiaAdUM9CvasacAt%!lCGrB5B0oCCk=
z#O<-Ngfy^@8uFhcUnCOxV}uzRz(J^MnjV@WVI>eaw0{&QRLb~0L!XHM8WTso{YQOl
zc2o7QGR<ca2f8-dL*7DIxTGD5w-PJl(YGF&&>{RtP+Wru4U8NSvteq@Y~IO9hiNh1
zcjxs1qhjx5V~D?N0Q_aUDbJd5R?^G!>x{v|Jg?E{LLh`xPIN^^4&2z@MF%v$X@%+3
zhFSch=<tZrU_XRk$<$1j{uh80gkvV2<B)7YEZD$_*~CAL^A9BLoFm`-R@4%d*suS}
zCB(-8LI7Ki&e!@X_wvkqcdA`koe#{eK+3tXD7%*?g1aRZqA*ZK!tc!IB()RPmQbyc
zJg1qUb9JAyKNbS!mT+~&kkHxQ9m=xAs|CpV6!w{2<hBXvv`^t>@op29(kuIFI)G~L
zUt9s@oI8sU)8b1hqZ!VA&_<eck3gbXBrvmsEG~)O1DWaDBIpl~g#Hm1xc>EY{)a=-
z*KPDZl1ovfQXh&mqvq{%e=HGol^FGdSVtXcD-4^z*6c(sVH+c4G+Q@z?MYF0Jthy(
zxL~q0{cUSnOLt8Mob_Qk5hg2{9lCDR2TPQXuX#l&iH-ArR#0mtj-(^p<eX&5v&khF
zNO`VFi6e*$QQoadx^bm0kXWDSj2;q3!3|a3MeB-?Lg8GMThJlB(MDVM5H8$N_RO3w
zDdn7&@mu@f^ku>0=$5e5uRxaxIG<~GqM*cBDn44*%8aXde#G(m2(x1sZOg_*D5QBd
z8zM8lCyC+$yyXD>CaY!m0(L47c&|!@MF-n!FGW0wwKoPPZ3fm5^y$~QZ+O~BoNQbf
z>CQ?Ou~=gF^y3}bH&37^eS?r>iwKzg|98wL6kx{rcySIA#ntG{AI4t0VTOuj;V00E
z(m%dTpg2vb{v&^RJ$jL@p8cdIy#ND7dAWW+o8eE#3KUh)py1RPW$63d-|J9Pg$DUb
z*2&uDs^X$<8}%a2OgxFtTgYt|>QBdtlvPjgoOsySj8W;O_vP9ev%%s;Y$#h)oHN_o
z_Bo0#NA!4CfJ3_mKEviUVH?I4_!(2lvo5G3b+a$?9%Ld^rGzo3Wr;QBARl5#*Pt8L
z?Y%~nYT;@e?kuYW5W@K<bWe)b<@)Z@kL(jJ$Kuf(>UHocP_Rsc-;SNqO%QsSu2Iee
zaRuU}*YMrzW%2%<lP@gsfXO=0ru1FgMN7@HPbw81X>TB2pa<(TiH+Qdk$h+vK-+X;
zt#8Wq+j}!S5I=iQAc7;5wXMW@bJG@-@_nt;5zZG6L2bRfrE~sb!n=pnK#-5?MiPT{
z-ck4i+S_??VMC}{6ax;^tDp#+Zt6Ou)xOBH;LOc?Y!V3z{+PR=HN~>pVUlWYQhG%!
zItT`edD<33(5NWwX)PYRw7cv)oa*7lKuSbSiT?#~uye>#p>&AiRwPPjRYqItga(6l
zfa*gGfj-U%V(0pB#=a|@b-RSMk)#c*FG6qWJ07v<^PbfipMRBxSxzV#zI^?2CS)~*
zsFwJg%Pc6+7!`xkU*X!UMpmJfaI_!78C41`l$vZVg_MJ58YFGVV|wYkZxKaya7w0E
zSWJYfL$Y{Bz}ssWtH(`KB1|vxdw7%YvUgdcrG_HWvP}Ao>AWtsz`6(BADVE#lw=K_
zrx%X)AC1@ipQMrnFX^Rs)m!BD=<4tx`Z9^-bTj1hBDRNG9bRIdDrXM<Rd#GOGTyoY
zUZPrHiDN>UXUw}q|8-{idpSXr9sX;mLr6Q%<E*rX${Xw<!3PQl?I8Di<c8dD=;ip#
zRH)k=@<1SXdm$SIqgfbvf4jF}4?>(HK!@b!3ERuTpl=c5q@yye-Xr*%HikCr?TAVo
zkTFd?F^7OqV4fEp*0${F<>H3}g{)Ud+b#O?y3~AYv2sWyKOHQd3*A0L4>iju(Povm
zyBvKpm#l&$)|6Eh(d6k-{L&YSlipHu_06><L8Sl?CV0Wqvfc^%mRL}&po!ID|G%R0
zl*sf~$nrD28#_pq*yH8dpkJ1COIV>^RVG@_%=6lLiBEoqy7Lf*{MEmS0K#?BI|HC*
zxUEMl3WAQ}Hzcs(V8Q}0rBJK{wfU?0D=O7b;3g|J0Grp5MgB)mh{z0Wb`P-VnVQ&^
zc8z#%@7CZ0m3GHVJCBNMKq7|4Ll@#cfT#Wh?@e6Gzy%8Dd{})#>)8XdJ~1UQ3v4?+
z-m!WvxQ1YyGiw#yH$D&&GB(aT@q=?z{aN13BiWhK{n-PN+>R)`(+h*@o0vk*T_4PR
zp$@k~8-I>^*6K_LYcPLRv*Bz}>9!mwL2VHQl<Dm(I7e^*-d%P49gLMFw>^c9s~%S(
zDUGWG@Kop5Tf1X+8Za|ofjR@xU9-D;AR|$R69M#!3A+u}V4LH<5WLbsQ~wkJupEME
zT6f}T$LP^-+jyQOCl;xjq5K1K7KmcWC`C(464nM)W*Ay`)p%GPK89VE(V<)Jd8UP#
zllzSgs2fIy&;LAW$w3EkbC3etIwqXQ($RaGgRLWF1Tru?AYf(_#j@?oC8trtsAw8b
zZ6gQ29NLD`7D3(Ym!Ts2&HGT=#jHLel$7rk#{ioSh>pzH?FVf>&=A+wS3R6TA%Fx>
z^E4;5b?&Ij1gBfbJ9Fge1vF}>SFxlW09uRyA$r#Tf}PUxeA6iIapEn5oCOqlBH;?3
z_~XD5YS>0wiR^YSL8I$NvTc}%*bkX@09?vjdjxqA9R12LNId74cSN|^u{5!RmS^X`
zl^r(ZLN-P?7c`i`1wH%Z>o2vxSG!aT3VJNk7Vf6lN;Re=`<RFhDmH;tU$hZL{%h!|
z-@Hf4T1Fn2ryi7w5Hu)%n5=KJ`yEBBFW-aHpeUTyVbbBHVkL7H+{Y-zXKW_`8U9MG
zhqEWsNjYBG)-_W5GUh0=)K4<u?wEVCXMJ<LCV%UUKVW){1nW>Np2N11%$f?3wBuN-
zE#x3<@3bK31{jgfp@J+QqP;<)OG}qtOT0a9xP1d^rzBNI#Okz?Y(T?|=vC|5R4Zaz
zw-CV+cGiCj@T~T2=tYJyNeYT=Zf}?^pD$OQJjtvNV{?Nu*<^Y81$WRzklJ8Q#M&8J
zDapD-83lIJf<J~<A;{VtcIcQZMu|dKXE5?=6?r*<lKD1B8<2z^s}xQa{smRmYj*oL
zV%GPt+u6h;KY0ipyC$&}$=cYkIY|6QUMOCwNPs9>)aZcR8B{@JFg{Z|kKj(FFx|8q
z4E;?i-^8r<J-<FPL%k5FbNyBHtyTelLMo&`B}NH;QIrL>6;!=nVE5`9@x$iUKCcc-
zy{;d_%^~v@YzuIz>PoY(j?`q)3;chw6z?!+e!unkvcz-SKFm)|q-k3Qci)MkUk!YM
ziM-DTLjmqcQmLJ(te$kxI+|b5@o#J8d9OI7qY7Ie!D)5DQGXNI^qKL&&(e>YHWedA
ziJ4m%aZaMHSZHQm6&TC}9S2K4r>`Z|9SZ_j%(^230c7b>yhpuYvLFteVNtzM%;I73
z7S7J#qw?Gt)J&aiJl_1H$Fdc^zlHd--J!g`zvCm7<*CHpC-RrvY@z>ax8NM<W@ni$
zEv#b9*IE)0Wi-KP(Y^GpL)MHmo&#E@$6pWX5!o1Y%<zIJgzkT4pHG@B`r%O?csS>{
z7sFK32-;7}<?O=OsURWgNvXKXAs$MaZfvSpndJ39zk24~s2SQ>FSo@iu=ym}!_Y-3
z;#8mG7siLXJG0RhBiKbmBFRs<Js0mx#B|0|f3>*JVYjsTTA<%d)i=bc@&iDil6voD
z-{SVYGsH|RipXvliMX;L7gafF+!|agAt|5DVu)`$#no*|+D{cHCgH>wV4YB+3}~)0
zA|G5)Qrlhji`Q@|plO>D*S^}202z#v2KOu14V|F#qLVDImJf`@{vBOU^xefJj4*y!
z%?tBd7pHnFc{}I3=MBe~zsM0rgcja;9`T8uAju!GXvjp4iCY<KAO&Sc1jevuj}mFu
z)Pp9V!{0{w<Rejtkx_5(=`;EHmy<^VC>A&>MJPU2gTNOF)GUM2Xp<mVK{<pn7W@UG
z&uroV+aR&e5w~=qb*s$N)8Yyyz&b)XBh78Gm0#X4Dz>)DM3tGqVG`%UP)mWY?}T8+
zuk!-%sr9^MWZaJG#uOWp@!Uo5h_-;7;>DwOyVi{iK0E*6_YWZh6vEHw!f;#FR`ypE
zUAJBRqy(o&wXcn!>OS$??iF(9c39!u*CQJBk~+NV#(ruHiL9hWfMd?)LhCUl$?Cp^
z$UD0tJ$csZmz5LP3lb_!Gf2^%+oHFc+)o~<3Hbk;2WG2R=I5EEJ#i?5JTq|Ep^^_+
z!7|Y6tleZF5_QI~GF429Mvn?JelfGm;QLK?1bDvGd@rcx?{zmtE&h|h3H`DfbpO^d
z4!4-*XOb&*BUntt`lI!tSGLN3G0iy4VH5+c(ttLw`U|JKDhJS7&J|(Wje|tzrR_+a
z+aD=?csX)3qrJ%1tHE?Ea;=z7yK1f@IW@_t8qyE?V-QKxxyy#VEkWG)9#(Gav?~5o
zYlni7FTXkNm||Xz+Z?*AIiPrsa1&L$ck#72bx+(Xr2iq2(G<8Sya1Ycjb_1l)w!xQ
z=11+PnP1mW=P>snsGiZ5c2b|1*#TQ8INddgRWtp|?VFoJFuVx{Qp~cF53My%8K9h!
z7^<IV0+6!E$-^n&hJ|SU40q4>D--)Y7WSA>f4?H=-|E^{gh>;c3cLMdG3eyF^F|(r
z>|*~%Z|y5y+}>dWkD*QgvH7Uvgij(3d^SB&+0<zNkKSXfPQM-LdjM2YN+=XI(N|)I
z&CO-$=_<b{X$P(c&~TdNee**^bGsrpdJ^e?G5_2xJ@$Nmt8DTC_#RqHPq<w10X_*`
zw<FQGbJ8osqIL)S=a7QFRh0h9&JWQa*@>C|r^7Wtj)yBI(=AtzzGBaPt?_K4<3OPS
zga23N-&-dnoUH?Te9_7-fP}uhBW3gJv?4-%?*<MHx9N(gW#GvPivQLsWsoZ5NRl1O
zF5Mi|0uQ-1pNGc*zquv7OtM)l)&=6e)b;hg<zf^hGpLb*hx$@H1P+VFQKA$`+z%4I
zEKo-Vohnm@{-~w@!)XA>=wHafA9uTII-_|26?H#&c~GfH3IW9)<%-iZrW>nzeS(}$
z!p|83p)T<0dZS2s*h$;yik2uI)qxaxv0~re(lx<*xe7MC-AONk2?5e<iodq}n21k?
zh+qb{R&Yw6OUN^*Av^g7eoKrPN*r@435-Mn>wo3@()j^)s^l4^q@tAtDu`PcJQ!IA
zLp+Aq34;RjT4~IDOMhSJI$uQ0x|pd<Q({EclXE^#umkYPu+stbP|%cqKGZ*ddA*x_
z9?eMdQ*s_}aEPjm)XC)o2OO*e3y7Z{C$#B2fYDD9Rw67{Ph%($Hz5<XtuOqWGl<+L
zk^<KT1iE&`le&6v2t>jM$DHeHj>uKs+9Lt0F#h_GLrS<{mZk%wl8M_VFp@$!i0lzz
zU)c`)bc+bAtHi<$EZliZ81mxm^w*&TLeq%YEy$D4z=IGv2a=O1h8J^VilSznK4^)~
zx_>*b95@=M#h~Z0RZrz5__w_JLpCheqWcjyMeGSOy1_8C<-`tLjp|uaiS%9Y%-5s4
z``*(k1C$}WX7*qaA-*1U+cwAra%$?*WytB^;*ZfvW?#)*U{Ukx8<q|Z!-*q2a}T30
zls~!iGriZ{@iJ)8?gEwAak1i#5f|wbGR77DSV~Bak}X$-OO;gd`tH%jD@6Szti=}I
z1InFkv>+q8lshd1d(a{Rs+et(l@?G2JIP`|-O@jYDAU3@xn!I<a1;HuDI16`NHNBg
zbz{t|<*C`86W8a^7PkEPQc1xlNNlL4S&r6uqi`LVm=ja8vuVjL{b!J2<g2j-SoYv}
zc*h)4nyvi#cY4_$V0eq?QG5ETm$nd_y5B+EgZ*XIsBh7`<8l}V#>Z>vzu=yx-2lMk
zT|M_z=Q&F;kx8tNYZ+~WiIFR}Ssqa+qR}k8E4s&gr~laz8yum;;O`8-<HEhX0@@6Z
z{Cy*}&itFgcL?R$f$ZNla3XM8y1P?lq>#wXUg>uEO<v%h#=)o42DJd|Kq1!Ac7$MV
zC1XE**`Da=*!i|~4e%|0F0h7_P{EILt5cd-lXDHQ{jtsYdTCmcXU-o}r^;Ky)D9ok
z>$8F#LS>W5KAP^PWpF2-xV;n$NP#M^H|3o;7@i@$pgD|Fc?Shskc_U@P5<}2_su=g
zI5ex@CxS?IWM!?=A1{gVzgVn2U5G!?PE=e0+)>;+cqP}q0?chN9=w9woTd_^t->jR
zOLiUVFhUO_w#0GH#qpZlTR!^&>@`Na#8K_%4<+pJe3xsRy%9G<Dptrtc5<B~nh!Lw
zH-?R)w)7l8E*3-5Jacz_#dKD-V<t;+F5H2P17vO!(7zO*cW+HU%>W>a^A}z5her+`
zlOy<LF8D4r1a(%C9&77OGty0uLq{85uopSzv#15BC^(k1A)bZWqs=v;-uFqGEgz+&
zc>G3I*2OS~Ud2jh_oW~5Uz!-%C0jm9-eD&|TrWHnm69*5@((!XlM(CSc0tT#^Pn98
zbd49Vn>Gk{yYnRbWUu@Df>5fL%MpHoIGWP3)y%-HUMRY6ev!M^c>4X1l5dy*f&N|A
zyQ56HQp%Fs*EREHI(F~##!F6lFN_V=?R!TG-k|I(TqoK>m3jM5_)y|0-}qbA1R|I=
zXE>Q?Z1)QzJh6Nv)d(L2vGQ_nRYp4Oj@(f%BkZ)&R~nY0HkhY?_vj^}QCO!9*wfyg
z08dY!=;}8Dv}}xg<rpK|St<UZBA9Ha6=701h##>(%`PiNTe$Oq6DAKqoab|WVxalF
zN>J%0cvK<Tx43~RU)EG@wR{0hiP9KCOdaF7#M=U4h;+~+Jz<9v7QR@uouhoa?~Ifc
ze*|^+IH=@yA`_U5^<A3TD{-8cumHgEK(wI});feaS|ph_#d~PF2wCz#+&aZf2o1H7
z>jmG+5N_Jd_SPyANxEm^aZJKcjW<(ybj4DBS=rtK63<>Cu>`2w_XFp&;>-dq^!6{{
ze#PsZVM;AA9@k0dO~z?#C5_{(_aV0+kRZ22t43*2;SY4kHNJ*y%ohcfuZIvo_2haX
zS0EW!oqP5!S*5i_k*b4XL+EL)DV_&T`Dag{S@uN|K44i%n*bkX2*ZcN=^e+PR+KBF
zy7D=evJAZ?3IU8kLnTU8au!I*VY&#u0=)_!=dZ!Ld<i#5SlNer5(JQRNHur2hLNH?
zv+h+OVqQo&@Fo!uhM^r!_n38ne$Rdn7EOFR>Ni!xFao9`FQ*X|AgW|ogW(%T-y-S2
z{qeEFhYFsNzdxnZOGSAJPL-*vBKyq`5K2&_ZqYvOL!Up%5lX9&)}7)eXN{YI=SR&O
zpDU_}c3iHCqD_l~Rcx#R!eZ!&kJL}cmo1$0T-sVROipd1gg?=xf604A4|d^z`<v6G
z8Dx^(#`s7$9&XnJ_pnotO?vy3J6~&bg!rd#EmrP%;M_RPP0RQq1^iORF;kHA?DeH?
zF=%>nLa2CJ>VA@OnjHcphUNp)cOt}hl6`sIkquHVnS9Ts7HP#~n&ww}@zNgug!1LG
z5lOoTRO?k&qBIm~pfe)7e%NnI@dRCeTF_5YvUnY-Zc<h{kHH;3!+-*uTgP6zNJ^J1
zo|CQ?hgcEQXTIPaIEfZFfF<nR9^Fhro4@aLl!kZnp@tSw!?R`DV>@(z1<|VE8$7;@
zDUef=`g}*Z#MSKaLG}4ZWk;n>dAkbQk*wjTE&VVxN%jQ&f`0T=I-Yi-Uz(RA6<a4U
zXBo$quJ8U6FzP-b61WYQEAFaTM`Fp{bbi2P{ika%5)WNgW6>S*WhQx%AyD3}-#JkG
zDprJDh_!ZFfn+cEWQcniXE@echHoAofY<#CI4~4(;CLVfZbTcKI|Sy_)L0xD#WpSb
zW&=JGir*B8;3yH{CMoLv4y~<$I$ZPJoiYolVT#3rc)cHFuJZt`l)alnUblj}S;EW*
znftH<+$IYt`}PP+TuFYmPh}_4hNS`v6U8G^cyV@90?QI@BA@z@PZ{p9c~lB_sszA?
z(00Lf+tVTr(Z8x@8y>BvLxCqG#5RM_2BVQV&^*_RCHu=H%%sp{<=Z_^pB@lm<X;@d
z*1sLInWda-O5Tp%JUCNM5|gBg)cYs${+#ufH8XPe4TmGCpy%GA6iznAZ&e@N4pTc?
z_vAl!&lKyS7Xg?f8flZmTc=(QZ-2fNGCC<3kru>Cjy1gNd4eVOPjrMo*EbQ*_jauw
zkoz}Lf(fGl?k3s^EsBChnJX)(A5zcZ`|rAGn`RU;tVqwoum^Kd<*46^{Q6NF*Ncl*
ziEPtEX@y#vlo|X{U-e)5`=HHi9+bApQHgx?r5q2;K?;fEh%yegT~zA$M8;Fhg#_f)
zq9DYmBb3?*_hhgljgG)dqb}ujOk80WM5b9^-t}QXA9}na^kxnmTT@3d8Kb2Qm-kn~
z*Ou^b&LI;-oIh2w>qV4ZVS=Q)UJDTR2pCquI&$Fh$O^RtNQ!mDZ!4D`Mj#zR))(QW
zzH>EzGAV#DKTp}=Z%*rUaJ|~jgmH&s|3U<EkD)f~*Ej2q(&JKqH`{Y)`Q|5U_fQJ0
zvH-S}fG_EFldF|NdWva*hp1m*>~glY9n9Ydauq4l;5<smN3GIMDni3g`bdr5Q(<~5
zdb*wlRQ1Ca<jb#Z!X&^m?3|p+z%vTtgaXrLGJe;BiM7QM*XmIK%~iAdFQ;2+9V!@k
zk=2h^ZvCc~<IATr9hhhRX4&YMmEjmqG*C)uv_)lC<>Mw9W5V>G7&tvrr?66k6-ljM
zejTFQjb=bDsnb!hWr*@7cN#ZJ6JXv7J!ZJhxjAQnLAc=~CjQ-Ix9K7t{oeMQS`Nk4
z92!!P=V-P;3ZK-k?_&6=RRq($E>Ve{=($Wq15|b51m#O8M(<$2Sb(x!_=9Y;Ztnm&
z&LSuplV}jp6|~TO&J10rMGYmXJQ~J7iFQVilkEzb7%fORZuoFO!i|<&I0CFex;iNg
zdUQGOEb{HwpT{-Fm5@5(xb;hTv&*^m-KgrTPuOmakP1B6{q<W0&&&YhwgEQ{zn!@G
zE0-vYE`$yBlL{&hm2aw1aXl|<`7RMWnzP*NNw1^g(R9YVngsqLD0^%gfu;a6i1$jS
zrN!2VjDYAq7RB<MDEq)2IMLDqtuA@UqNk%4pO{D<*k@AC8%=-@+kC=-7Zu@0br_ta
zYkf+K1bW5TCiAmdiLE_)goO<LN>O7UPtEd3!X2+f$rxQB6`0g{G7L?4_k^DN93&zl
z*QLIl{<2t=L?bGJg|vHhHCGEGP>+<*v003~A>2Hu7nj#RM>6rAKtHSt3}eH^MFSD<
zmx<NW{lfP6Q43`M=tU_Xy=Gikw?%c3j*GiCf}^q0`}Z-&u4(i&IU;BxlgwI_m84#2
zt;OZi!?QC4GB2O}0eO|bcNOFKO=b>p!c-E;XV!-GmGB4Mbw5NuQXiitP*fr3_ot_F
zsK(U;PTR)#GV|9Q=n4$L!Pp@9EFM?F&w&$nu5IS`eyKK0{WkfE$PTq`BAV~luwLkL
zjXIedm^cW2etgBzRv`1i=<1$6ZrR?aMVf|0cxe?G^qPY=pa*(!>nCkv?c&n-eJC{$
z9~WIpbA50cD96^DWN&)_Ot9u#3xLCnl4%}DuvE{yL>tC6$b&02GrMvJ*F#T#u9C>z
zRyRUc4fHbD0SzS$$W+7PG(2jRM}-VidcbP@<P%0?IK^GXpH}^Wop!##pN`I)tF4Ye
z9g6*2?@Ic-;FUXqL%D;nAO4}i+EhCN`dVXL2t&YOJ$cy9E_?(mjmW)f@!Ov8$+eQ~
zb)_vqX5j`ON>!i#CII$0fq<JMm*>zQ4{6L1rW)YQ1ZUnlsxR-+H=(O){Te-#4v<8Z
z7LdAs4+ptz+qHFI@xRmcvQb)3GtYL?tju<$OlxEd@VC#bVx&)v-FdyAxKjA6B&vVD
z>M1-a96Y?6cw5rY{@36-5awFWFh|Beav9hblHx}J)>DnM*dq*l|DBTcj;9{ydyU2g
zwZb-W2+p3^9*Dz{Gu|vQGDQ&2!m+&meo5fgiUOPXF|)G#rX!hJ;Ib-0{JXya6OC=R
zX-sO<T3Bc0V5fyqgP6twWJc6xqWJW1L-28&M7P&B-a6r0*O8XNOiYF1F{O&pAKt#e
zxg=Eo3rg#5$9JTajLp9itY5L{If&3&%K+U<{N87jwBS~(RNi|XO&)f`A~@+FdF040
zL|>Mzv-(lN@g@)iXmVdYj@(A1CxfL(gk+(TPrMTiUH%cD$brnn4k<TsIQ$A)*^e;V
z=MJ(>t=;Hwu_#rCXqPgpiu3G}<bB_bV|IY8sI+6v3d`tl_2i2RX?^}oMPCwJbK}Y0
zyFiKE>et;-<8oo7E;`OgzAHI9?@k%A=X4a~#PC-XRQrTAbOPA(<BLG_)IuuZ<O#4e
zoJ4-8iN-k@M7H<OO>Gyef?L~xnpDwmNZfG`sZz&j`aqexRpCxwbk&Mu|5>}I!gz}a
zhXpo!`tuaJhz2)2V^wq*<>=~jS`IEmg!K7iq<q%_FH4)|`co7K_IM<#Dd^sSGLYUH
UOb4OPd?^8WXP%-+uO2&!>>#KE5C8xG

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..1d2a927405fe40a58a1de86b47089c8fa9146e0e
GIT binary patch
literal 116184
zcmV(wK<U4W6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC{1Do&#<#lN<&Y7u+
z`J#{Zn-=11?=k(x!i44iSYHZDhO`wEpIOIO)c~TG93iq0ws+<}sM3dF$&1-TZ0pq_
zxRpYwea?_q=(ej>6v{7D9X+;(O=Cu*>n_XF-|cZ%T#6N`iIV3L*fEu={~uw4>nvYw
z`i}NV^@#AzSl5dJ>q<pqFt`QsCB?Z*gH?y8a@9(Dy{>k)C;FaS!t=3So?;l+S=VH?
z0Ufd}SAuQdT9klS630pV2@0crM)&A^h19w*%QAf8L`VrJ@M8VSrfl8T>dh2cBmWz`
zFj;PgU$j!1eyJ`KEb4huSk~rF3ZP6m4jadXb*21H&2>W%c|l12i2@qh%YSjv&lbOp
z)e|ro8V3WM7jL0iD(YuN*8yvtT@x9|aWT?pEC=5FRFr7#r881$F)Sf4ZN<!9HcP?{
zl0~J2OyQ#9WyV20h&*Thq`a!SC%e^^;AyRQym>&`i|#C~*ZTtySt>d4q>0BnjS9ED
zqpl5aG_N*#Zvj@Pt+vU~9`1u@y1HqWFf}_|i`w6)U&rj@1LJ{e`^}Cxs+5W3ouy)o
z!M$F@$B!++(Ja;wOM<Z&f{e&7DkWQ)P9{|`7-*&Ee3AruBzLy$5ArUVePP4G;Rqnh
z#wSJt_7_OT+-K=_2Fo^0etXlNr2wx=n>Iqab!L2bpXDU)UXW><n+<menYc343%NsA
z;ZwzY9;nHP${LU*mRSdjc7iA>IVgSJa4K^4jm?|cE$w1I&EEt#{$LK6stVjY(9=GU
z_vZcE;{ITevBsitJmKfg0(_tG@?l4~`Sf}Y3DocG?{-15CFHmSEtfFi{Sn-hoR3tQ
z+R^ER05P9c6|*0SHAg4^1GYa(ce7TonJB{0o!(-8(weMs_6FX9xZhWqy)wNqW{7$4
z(Uws*3CDV>8x9|p@uv`w`IRyM1JtC>!#LU2>@mvaI)Q2`kLi7w{P=u`r0;zrO1B+d
zuvmm3XtKeRExMa!Pm+R_V8vijRdhwg6IDI}R?s?PN#!T_Zz**I$#W%A6STySD|(bv
zBbUmS#pEEf%b5{zlRKn~zgv>`!fHM0x;d)IEqm=C!ND_{VZT0d!sG@C{1WtYctfzr
z8}jr4>EBnvoT>1O0Ix*OshKyGrj~F(T2G;?fJEt?Jp<;=^8mrN*eG+U7G2>h_njLM
zTyJDUR{i@;u40kK*A5n6T#%ellid9;Gs}mx`FzV`>{}mKyo9Bh7e(so*D!Gz?2mnD
z6ErcdK%4b<j_WvhGXe?a?<;Dopr#pmPFbr6ZD6x&lCuI`7Ad6-5*}$!+pw2cRyW<y
zzs!wRxrH+}5|<j=Y6q{3J~zNg2bRHDaRE0#nNTPb!XvH|sPiu$M*w=cbH;l(OE|ba
zi92?;w*>HAN5Wcj-b2SzGxE8QF7E$}oE9?oVvB)O5tGG1w$bHKnU^`Z&GP-+o~5>N
zeDX(5eyhVQd#HdZKn2osuPpEaniRgSQv}l&*uSC(KBWq27WrbG>QtjZsh-dSzkcLL
zBpyJ02tWM1i)O{l?UQ@wFH5>ioHd#uD(^pkyK{Jl1dEN=<}7H)8BgXBNO3rziO*AF
zm7Xed6-DQ%%E4QP3qs;*8mMmU^vCPZ?R4%r&TT?%**$vpq3LwW){Y>S&c=NE$m-#o
zq5B3Mc7P$D6g&QxM@I}sA8OBSX+$)W89!fI^G*tLP8eg5;>fS*$pO7J7%2q}wfPl1
zb%Rx}E!F_vfjC4W_(!{opxB1?@0ni%Wy4y$D*H<b`|UyD!nchZp1((`kY7)9*O*T|
z#5hYo>i22LaVy7Lu~&obvH4<1O_z!59Y~+4mzs<8DpsbuLzeqmM}dhV{G{jos0N__
z8a)KAnBelM${i~Uawp_#PRcb5&2`Fa$g-+~xq!kJ_ydv|ir-P8dN^5q8=!8(%8AGy
zf<OsMdN=3Be+xjv3vP7Pt-<;SE*B^od}VQ*&fjUoUMgr&-9!06St%DI6r}R*O&RA|
zr2L?VYW&Q)Q|wX4EB8*X7_N4qZIAoV|NR2opFVrvxgNd>--q>foL7O`SCa#do+&;C
z5=ag{CpdCd;BjN_!?Hv;Ux?zYyO^TPNm(cW=XkoAjz>_KXjpGxbhix>DDAS^fH$nY
zkh#UHIk9<$XUz#ZCE>`g8}0v(Y(kytyh8rdG=x+msia7de8A<)H0>tNoZwO-;WWS#
z(x)bH`d^qTI+02Ua)RctIkgDZzx4|tj=z!IKvqpSwOC-cMo#qErryOr%`So#a=y6v
zGn$RW!5NA(t6vvfLcKIPCYWucV2!z@Jx04(TqiSXx21Hu2GKJ_-GALylcJCNhqfEa
zMKlX&<7ayDom(`|ag>nZ&l(RfiZp}4=fftWC@NRsRXPDx*45ea*uAv@HQy(l>Y*Ve
zZM9P|s=JYEgqR&+fb5;JD!+K4ra@)$1K5WHyJ#m5#xR)ba)VO=Y@pxXNCu~9Qcu`c
z>z&d&enA2r`>xh5xH#X1Q8yi;7e@^D20O8!j8p%lMqX~ond@K1$y;^n5-C!UMPGCr
zyDL|;2ANU>e>;NSY!s7J_fWc0%y8n5_rNdEs$Uw)1bMKF&!E+f7W8NUTE_g48)6s-
z9f4%_>O9L5f0}4s`L(tF>!6BlZabJASU&coS`Qbgz9nv53<g^CQz~sdO!U4N*M52g
zM<ggiFQ*b*H<mA>$-Kj#oq@Jfla7-?_Q7sPxTO>z#<)s>s!Zom&|OU=7<?&Zx%m5X
zr@e4=y1T0k86;?|CGLDTiLSZce{%h#o$bqG=DcnBM!3ZLLH64E@}2xy4Sqx>c>z0y
zWA<gY52!YZA`Y%qk#YMyV)NL07zUxgtVkzyO1cxv+f2)bn_)alW(1c<Ls(Eslj4_2
zt%Mn*_K|Az)1OOTo1Bu8(?Fw_qxDA?B%1En{dw{AD1}p#|6D2SenM)&JyJdXfS%m&
zW7_nAjl@#s2TFhxFyKyn0ALbvT{{k)@yoNI{!g7XGK^E^v7N;oi3t`}#rv+teY2r*
z)Ej}-s!=|50(r+njp^ce$WvE9QB%6Q(9zavzKd@yI~tAj@kxz?cZ8@isy-(=##bki
zb^}@ZMmv}4gB7`TxYK#Pe_~?sSEBf$jJ;XVv-Eu;O(4xv3abEd<h`yT0%*@MF~`f{
z))E1IUZ!>@<L$c9p6gS^P2DW&$lz`kk!g@6p-Xs^9cz%UKc<IeRd;f4y}7g*J!O0?
zr~=UZ&cnQco<2Mjt_b5Kx7@HL#jdoeg3w4M3AAYwJDq0&bDyD}>)-Q}-w0YR6|T9#
zo+2jhk+ZvinD!(J8Wsq5jCpptK_L0}>lJi)FK1{&JXF(0C#Mpi?5s@BirZ~I!cm3d
zn2*G?QjM1uf1;EEifN|wi(Ex7ocFMo+r@G)iDPjBk2+c64Q<ooclV*03R2`<W+gjK
zOy-S<t}1ts*;jU)wBl^lW&!Wv(R8AwgW)Q93wNZjT8c`{CO<qEX%yS~#MnP6d2p2e
z-l^n|E1F@ehq}5xy-#n26e1iwN!C9`MB0fwo4&-Ju=?H~W+HtP+`rVD;dzOW+gR@N
z1`uzyQt_>czJMMu23GnNR34Hnel5;KN?BRr@v|qJKBq5JLSElLXx*mln?Ew7aqGwp
z@(d!(N4B_)$I)d>cOHNK5MKHG!*p3}6tq&;@E7sBYddp#=i;g^U5|ZT*`l+r0;;`2
zLF<{pt7oa%;s$skoH*13<7-*{t5vF8(35(x+NZqs)=Tdx^Ayu|X&>`g{bLw%gGIv;
zCTJ(AG3|$BBh-_nIN7haGS<EAH{~?az*iVm>|hk`lUpl4)e__{;I74Z7C@Z3q%BvH
z2znaK?v7}EEylmR?3O_O73Cds^s2=Dmhg2AT-9kP<++c(=c!AyMi3WO#(6<*FE()N
z;c)*#yyo)_$rSUfYRi0TSWM3tirnA%ym^S^1*eH>`m)ZuKq%8$aMQ?heFsrfnMc#$
zj?B0D<@MEM?{Yc~CzXXkT?23Bt3r~q7r3~sK>Bmi-YU3a%=pj)=j4~>^6dPI-u>-d
zsB%cL)=zke;~*zPUB-6j`8R~qho;Nijy7<x*^%JCl<8l1tAVRBkqojh5N0}T9gXJN
z^%(l4w%nCEB0DQSf9zVbPq=G-8*4{M70j04G9SFbPA6Z?Ki2<;$b>(>a?(H_jF$m*
zvLEC)RVkwT?#V}EB`$mn(J*kuD))6m*{FevsIbs%Y-^EZJu1jH#S|ASM87DW6lLoS
z9jZHRs^#)FGNFIYdUrAPmgI<{1k8J~0@nok$YLLfn?sZM8PzV;R)nmgre-4m{9b8~
zDl5!Xub}MZ?;7BZloag>cOlqX7NENxp~qBOgQ2CUH{J)tF(tNJgP7wm2mN)3T`EiN
zvy~ktCj+R8aV(aD@&5msE7CTbGzZhG7qd*2T%<{+Z}i_5l>j$(G_=-_tybFSL5pvi
z%;}nlmu<%1pT)RTbIzQuNYldpC#L5@0O#?>@L-uqylViCl#>GbV(_AHmUr!l)2CZy
zlRDPV5<&6#b}ZAh`zEHo^fV)Uthlq#i=cQS2I6Wz@4vqkCTITD$ljIK#&kasjd!B3
zn5+NJH<gRYrMvxaA-V5|q4W?Yd)at6+$UB^R_$%7n3cFUO&mkbRk4(F<UmmjSC&L4
zT24~t`}pI(B*w$M+a{$v@oHQve0Vs<sm<jy+6FY8VpJ@tfvRyrzF)O+kRh*KC<US$
z+rUajEWbxbaC<3jHiHrTq+vB0ES0+>F!_~EO~-~E0*!sf<<`6}(M%Nrl!QzwzgE4V
zJU((+#<$EwATB&gkINls>|u#yfI^h{SFpbP#gP>jorkGud{;bqcp8YBp21k-I@Pr?
zvE{ZB8N+q?uhb)U^({g=p<$mHZm)kGte32FP|S3OL;b4QFOAbEu?3B!8k}O}RI5Wi
zEOkKmtK+kfXT-KFjpjE8E+`|((6g$OA8~GuYV`+S(OJKB0_$Om&Ib0a7lIuPBItGK
zJlpjh)+{E&S8k0u1KI!|p|kK3A0=hR1{erMh8#G4Nz-$Svoab*-<wI6df5r5we{3e
zCH6n|++TqDdCI9;X~|5^nMD@g(hd&qymeLiK~0hexAy;i@x#gBm{60H%fiFA(Z(5n
zHlIvMc))@QiR_6$n+G{Y02@HTKd`0o*nc>{3xS<iUyX0U?M9yVHG1AxLfM7ELl;&j
z<0S@Q-sS7KT^FS|T~Qz9MjHoxw<->p?MDD?*EPjZ4WXvgYN=p~hGRpOU856vHCg{b
zhEhd#mVEVAc+V~=0d|u??yk`g!Xg@tqWdR8wBkfJ&xg}2(OssMYz<f!2ZCf(N*L{1
zsEeb&A=u&+cCz*Gnk};*Kh!j|SPIOxR#r|0W`A)GXYiakX(7@ZQ0F=LZf5%}lN=Yb
zLgF%+d?tjy>q_;6&v%+DAdb2+Hb(&z6+U&aS2jZjab%_^TPv>s3}miqOscm^c=Ofw
z(a2`6J@XJH<W~k-m37;?z+40Asd%#pBjF1$n$~sSsahHLR4?yV7SoJLH^T|lirmpF
z@btfw*$;I~57vNfcJI16ok-YjaY<&I>Cql70}ua+I-_;p@H=l>chgdmBpKGZ_~+%5
zyHIIA{@*q&30&SM|NmD)p1$?;*_-}f+;KFT7vW{0%9!C@mUC{`RX?xdmfaDY5CrTQ
zey|vJ5=y)i(e^;Yzjd@ljbFVT4;6UVCJeMunxYwp+?<C`Tk4b|5zug4fO;5q7WLas
zT4+*c_XWvrpMg5d$22G|o8z*?1Aa{jfDEEMgt;fu>0?UDbgvERr=?4Q97zuFFOP*p
zsLZg;=(S?s<Ru5>1EumH`NHja2TziugL80%F~_w{PfWxe3B-xqS6g=IrNgF;BsKw2
z2>1H)wqC^nT>-DZ>(gKb$950-5+}A(5K)v@@(nVC2zm^PL8c9^4O%FfnfGecCcM^I
z-@{r?E6;jN!~Ee52VPkSPtFeD)}Bvp?CJu>5e5OJwcXEZs1UpM>oS$63Y*8W#swLS
zk;Ok=g~QpxAA81_WoCHHoSRR!>uFJD0co?oVQ?9`91(?4K}?_G?WM0zCLlX)*&E*l
z)NAPgeDeF6A4O}QI6S^kVnhFRwQez8tl$mNpGzzdWt}5G2R`vOO{M;ek#Ng?GvjnP
z;bH;sa*oTJfL~U;MiUM_8tIN0KW9*px0G90+y*q9HmKBgzt*L#L^XTw99{w`pNM$d
z)yW5P4NljL*Y8EhS()JBOPsA``LrpBZ3=q@{J3>>DffEu{C_tZ<Bh?)r|VwhUhmc0
zF@bD{{DyaJ25f*|hJAl96h6ZhDXNmb4>Xz5oAf7prANCi#fPTDe7z((undi8l|59r
zWHyn+#S1!q3zQ%ZyTXOC>WKGMntXy^{Pf{A;>r%uKPWlLO|i*v?2OpJXyo0}rI{7=
zn2_B?s2)Hm+_0k(vS}x>v|>2nC;uSU%Wi5~Tb%*ZiZa*`D2KLY+h?tc7hMayLv_2{
zohy}r_tv^B?A)9uw;*K*0Dkj{?9ynC7OLD&7~+D0lG<H|1Uqs8t{`GqLo&Kgqcl;)
z=$=gQ8?TE=o}J*8Dz;Kb1fGOmhIT^K62+FH(U-|XXQ6*cqr>XsM<KWkfV}1?PteH1
z&CIfl5?AEA^K&NxRo$wMV0;RH3k(4a!`All{zL~R+QB(4c?*4V!xH=e$z$tv&odM7
z@&L$|fJGpiObv(RH%y?n4r3)mr?PhPD2je##C7?GOVo#D03#YAgUXc*K#8eUYA()4
zo`3vK<qO~zJG(P4%hPLqflcg!fQij8L>wH=4?9w4h4?fuk?gRb6;cn><066gcn)qZ
ziHt%>g!i?g9^j?xE~g^WZ9kc7Oa>6ENWX@OOm)S*1mQK$?VN1-FhH{ZzB=@+in@r8
zr*J;sOXuB-3|uWw@X!wshdVHoX@bl7D#_UYT}TTL1rMvx5J4DxbVXFEu^IqXul_%*
zO#5IH>S9$6IpHB3`xy@$j+dGZjFd95bJ`aV5&ar1r&7nZ)D-{F@w2xTT#(zT4ns;F
z-m_oKb@eJ0pu|$dX><*61J>)@Gq2bjpr;w<OzF(Lkjv_#MG(|{)`y1I+bTtJ*JI9{
zD-PPlVIdsnn0I(lQVaZ?lb|&UXfuNj^Ho-an8{kSOb3e2r2=j$vF%VqM(nYXn6O@a
ze--2RgX&xLRH5&`yU2jA07fj0v5-pWg12U}Dk#|X;3-eDPTfgk4W^=GZB^p5WgKhN
z-?K$$3Zh79amXY_ZFS%7aH|jE|LD?Yb_$ROnDl(%kLZt^FN7)vP`tyUC!0mPt?FM7
z6+{bpmDq4~zFAYAJbn{wU^~ckuB+(JL?J*}>RbYXYbH3GfN}Nb60`})<b{jdwOjMI
zZMR$}GN=&@&!Ue6$5<Z%EsX!m25SJsW4S|2YvzJKjQ6B%WW|OlE+Peut#kQZUMU4*
z8#&xM2MSa8Y;p44uim_x*qYi<n0>xp1wH)|fw_rZA!nvPtPfX^gY8Heikj_UPvL*D
z!8ewy;JIKgJlpq-i?G#otr%0s;p-!pgBzLZGm}d*6imqhzA>yYx3)aiMd@Pa8;Wz)
zTo=TUQEp6uhsq5FE8I5LB;(44XI>egpI64ke45O<>P#6hbN!Mh1}Y_S5c5g?sBvug
zQTa|<ue>q{FKLggHGCJZ{sWB-D$BM0{lL$5@3wmR9PMJXM2hv@9&%o8*{dR&G#D`O
zc`gs#hPMxPYMa9*go=(_qi*T<fuu%)mlIh5fXXm2YoCC_zrfo9sl0yjTsSHANH2cY
zvL%5Q{&YQE<8(8ApHwB7fZ=gH<HKWN=JwMdV$JGA-4Jpg2A6dkW7#X9G<;UoWRNJx
z^Zf4SiP~j=0#CJPI68ACYeUtP_f&wgZaw2FXLByafqRMgR+R^9Ck5G8akGB>vK?jd
zeIAXYi4obur|TREn`Tj#%iaf5T@F=$2XP;b7cFg(j`;h)a)CfIT2dvvT|<xt{qe%?
z(5UHZGStn9^6h9_E```9ZKm$XY3pDS&O;7T<Z3^pM84k(lSMKH_kH$V<a6HrtU_J!
z;Ow+EfP6D%>5p4P?>&|_A_^E1>iA?gn{_Vo^EpsGW~6tVllEufmPHq=AAgq*ca8kI
zNYlyBev5%D=&Es)*TUF-nS5RHE{s<IRivpYlOWhi;^N?JJ?lag-0FeGo3Z|n^HapA
zje&YXzkxne$tF_{eq*Ll^-OIt&?lm*TY?#f+}h5)%Mi=nL?U{PaH$Wj@jeq|ad9N#
zTLRm)f3_A{0WLK}j40gPV5G>oLpysKIYY%Z9$2w%&n?h(g98MZKb=qT%5eyMo@)vq
z_o(OS<wuqE2*Y$Y6quPl_!{a0xAf|1#6*y)g-U}f7EldoPhmW$8#{*@<C-bbZ(La}
zLjP)+EN5lI+!92fGi#u5cQs4<?048ntC(fV7u4vRR9{gdTpy^->x1mBak7v=N6?+j
zt;<<06n`e3F$6D#iEnJoz2!EFIz^(~#L?|~HJmeYn)^0Byg2+{xpqFF5lQ%nhcP<E
zRRS=2w`H~eV_}PoC~cSN6=&SW`E<_r9GfvAYQ>wT9NywSZZ1tG0~{WjqdY3k;bMj<
zUocIl7ILrZ<l{Z_E`I*IcSRB`P3O!v6;heN+1MHXsh@d<zVbfEX#Ew2s=J~{$2(at
z+=AvmbAqtD8V$kcA+vs;Lcj-pWSg=W-aXLio8=UpV4X$=FZ}qpFf&qd^vo2FzPN$t
zXK9+~va-%Ft~-<lWvl;Lgg6@b!ZcxRQF^9g)jS?VgtK!ylwpGI!Cv@Zr@7CvPBcoz
zZ5Y)!uxG-JjJ9eLM~v;iH<lL;*5U3SN$Uq8<+dipR?Bk>I;d?iP6656tF(FinwjFv
zvHx14GiDzwSnZ)f!DBrK2kS>7(so+$v0Z3EPuxb0^kNv?pWLpZpT*jN0YDa6UB?^X
zm3~zLK7Mx53(DP=l_ymJx^}<*Y#o^)ASJ#RPIE|Z@Gxt5dQ#|&8Xsp8|5K;uJ0g2K
zH%~}3-k4!d&=mAq!@CU9f6NOoqN#zYSWm!vCWxcc8Ouh+V5lU+9jJltaybr=)x6?5
zzf*dXh|cQVs9cvvYG1WF(k@W!jFtAw3CvEfX#miHwH;f2GP+WuL)5qHezJ<y7-D7~
z_ZTBCTbLV1|KhIeW>#qx_&E)kfM+7&DSefMgOP?l$b6OznT|1CGGQ_CoSt5;+eH*I
zQZzVz#z#7PgNp9%6gVe|txf?gh0<_4sbmL&^Q2B_IQ{ktF~Hioo0KB{6Y!Mx`**7?
zV7K4>cN0OhAeb)LE6qpxes?2%S}4$dr6vBNg@SyrlqcPad!Pa!pE;evN|l&ut{YwB
z=XYj{0o;VubCyYauLxJ44M&Ab*(3_)<$fR;QP8aY`h2`a^j$>ou~vexAqD3#=`7c3
zRo|@;Ery3u{S2c{;Hmp}(A00o8{jqs01I}^QP)|YXVmay9Lg`m`uS&6L}E12!fumL
z`4TU;e+ofcIy<2hJ;c$$a`sxLw*4tN;jCI~8x6(2J4<8S97m@pm;WV$yZAXj8;CwU
z8}WO1d{xNXyQTWM_>VAzSd87*GY-D;Lye}L|A{#s@2;B2yeQFl<AE_6gjkUOSpyv8
zRNts7!KrjMJFx<sdh01Zm4V@dKffd2S=VX+w@a3p|GwYmoH~w}_YJJoA5gJ+r#&uD
zes0o0|7&Ofa}@=hC>apzY92I#R}-#e*ACVi(6mi33fL^>8w)Qa`{D0z0A8Jw(W@qm
ze8XJ%^ZDY~KWeFR1tuNg6~{p}wL@*+BttDns|4qGvke80rp^Mg&%GUX-2ZRtqEPZ1
zo9fIy3nGEe6Wsc$jI3RT8T)x`5-KLqszmVVE4=9T*(;=qKtWcA=suAJWch7xTT$Bt
z{EnBMNP(n_!)IXsjcbz)=}mXOuQAF))-^_kxhqw7v}%`$Kx{XyzJgf{GAE;hU5-0=
zR+qXrhCI7$Pj2^Dj>O6HHe6#1x7%_A=c>di0VqOYvK!cQH8ou{m$}g_FPv~F-l3Fd
z8ODd&W_f^G2`kMoV)S!IVxE^#%P=UB4hp&gtxt$dp$naEP3QYlKV7DuB*RmhOY#Gq
zOH;5tV@6w|O5WCeqp+0s<xX^0Lvs@_62tLdphs9<;mh!pLr+yto}>9%+-<yWFUkjY
z9{=&hJWYAco=Xdd8z377zA%&tzMf|G+Pv}k4hE1R+HME&74H`+-dt2D72Bgqp2}I7
zoAB-z*@rkV`0-n+g4<ZuPls#Ciy~?(!jTV8H!FpN$}j%6EP`uel;`$h@62P&q|*Pn
z0c~#`zE%U8c7T_T@IVbIrc15l_Q&Azx&*rL_kLm#inIISqnFBnDA|DJyDnZ)CX$oR
zoPPNPRHcOcdR&UHZzg^N-Zn*|I@ZdsWH@5K1Lk)`q-WmBzM-$dF(86Y5L;dUcx!th
z5P$AWOP`=+Ge;t=2>&zj5;Npybk9r6Q6dwB#)eO4mPVkwo>>(~IMW!tu{%|+?rV;)
zqeHjvVs%iUekN!XN!KSWbl#vP6?iyvJJIjOJzcixq@{TC`!6*LI8Mb&xr3SU)?Qn;
z-0a6DIl$1~e;~D6hNsWznbsC>l!0xes?<&6?}LchQsrI=S6{mR91iq*aiC))9l(60
zyL15p7WOnMG^@8v@(YY==RwtQD_J2pnKnGI2s(05A8{lR#)SnN<nL>V#7?Yg<V`#o
z=1BK0#P8ij6k0f_m1F6nuS%(O9E;>JGpR30z@B#a#go?G2#WJx)PC~b5yB?c!Gva8
zxQ|(^h3ZD`m|n9_+@G{EnjR}2F0<BCcT2y#IE!C9mAC055T44A!_6aidoSH<dZM_k
zdDTs)x42O0k1JObd0xewrH3PS6jFO!v;)sIHcm*R3sasAr0+$2)W}POuhV2vl15Wx
zS`H`KiU?18E6`^v_V{%RJve7*-`QIW=#RK!34htNa^GQ>53;<Kqe&kVM&5j8eUWeK
zz6=$wMehOen$xRQ{=b%%G^c@ZH(8Qz>ff>2=41r6_~KF$$1@;EdF%g0vhb>t#mxoI
znyxI1zsKuglGH~CwQTE)4F!?Z3cH^!Aa&oYB{7`ejr4&ah2gR$8(^h;*gdnL?hi&s
z3+9pI1|Bcyee;Gx%Yn~1Fw%j}^zvb=z3Xo+Iq#Rg!{b)+1JOqb1|}{Xedw443+CNd
z7*Zp4N*#}{@{HTe**fMM6)8$iUr@KNyis8WNWU^N4#LR5)y7}58SsO!l@<W~WLPsp
z>V93zq)`2LvvRKYg16z20zY{m!9LvmulFF2;>O<GW6xlau-GEryc|fskZ}gN_amIJ
z56ZYQ6qw~sm7!>OvR(+quvHJ_5xM$JwnyT}W^1Ce00RHX?Yx~{0Cd4m;tmfeCmV?y
zB8F2JBZCezJk5w3lO?BIP5tf<fC5%K5RtADAso-qs)xB{+4S`IK)JPZsyvxu$Qqxt
z>XM7Ic380Co`lRXO+RqPY;)vvA<$r^tOHhmFK)duqdkyXIzChxaohn0Uv_PAKgu(p
zS6niv^;9!l+29Oj#m;A^Ge_Cg%+`VnIuUyG`y}x1u4YEMT(K<i=T?VGIJ95H)`M>Z
zTsTUF8LW{@9nz+dZV%*8|Ai2v3sbsN2THHj0bSn)jiQLTifZc6zm<bDsX@4W5->Gd
zsAtawnN<n-yix@H2_Zo~=APU$(7(k}QFtKuynyAz_DWdl<b^&5+iF-Nc9thE^~t6n
z&V2`(2jAO2V@=-hOED{P=-Sv_3PLBS-3B)EvjL6-1cwOSB<{~2+{hForq{t#k1)j!
zqMcm-(()n_@WMlP*lTGfgB03L-HqSE6f5_3pk&dhufXV!Hb5ZNHP-AyCt0Q1B_y4y
zI*ea(M^7ZE^(HY*p=IH9zi9Jh@s9cmmed@r8n4i0vnsTlV`0tEM5!{7x4@PUv|KxQ
z-OG1Xm|2<SZ0ni`3P7XWJlj|MzM&s?zN@9^4@o;T!u4F~(I~QQQ)t94yw|NM^-|a8
z5R5*G>DwKm%-KF8?=KFi+a`A^2IOEd)qMz}ePN05*}b+}Um4%An>}<6L2;M!BMk`U
z4xGLo*5%-m0XpK5rIHH4jD6SX{s_}lOI5~RLPv+GIh(2^9{JUDaNqYW%6~kMZMDeR
z<L775LRulx1t$fM(a%unjoag~B!)cw=QcX2-;?HuPbQpKao1YpC>uxOSvXk#CY4L{
z3;+(E2SXW$Pa8@%)Kn7&Y#@H%E7M_xFUE7Bxlbx4?X`%YQHsFrnu|S4%qRRfdHuCR
zj&}!M9i7U31myPM9L3EMql!+rrecEAfrLeNTp(9Js+DQ<JrQQHXRea4IXTuNan%M<
z7UanVs>jOlHJ<yV*a8qs#k}rOOdTStw?2`kYTqmQj+UV)PZUGR^s;OEGc$a`-J}KG
z#y#J~ziN|ba7ePdNq?B^{2n^2LEtdbp!ik!$l%KYiyAS^^YmoVBtM>$MfU9G6GrXa
z2$0(TXIu;M_0{F`b_=AhH8|WNrR2Wd_Y008Z~=q#mF%A)i<>4bSYSLO{>uE|nvV?u
zWQ)P^B>j$0#uy|>=AX|^<&zp6Fnb*7NO?heFAEyi!v;(h-SI&^EPk?7029!Xn7R*;
zCkDdTyqU<X-aAC6V#6T0Sqd;A*KH-QO3E5eV>XoGo1}vuQIk6Yj>cdf*;d3Xm3-zI
z%LQ95sJhd9wd;o~*U^yYTY@1@tT|faw`4Xmm>C%3J}vQAF}46cOF$0mTG%l8*qGFU
zc3_ZU%1mhNwpS$>e-b1k?%%j5<a5@AZ<pUcxg;P&|GTI|(G*6>+?_{a&6xdE&O9Bs
zfg?-8WTLXV<8Y4s7pt?40TyJ{5CrR)8>reZ50pYLNBz<Qeq$fQ-_!LF2vI|(r!+3Q
zjCEi5dLGvBI(Z=T0slnGNzw#-YE%yL2#eG$6w{?R>yzZ#{o{CVf2JCEe^($yH1bK8
z@fVZ4S)f;Zf0OJ`EOULLk@~E+NCHExBurVP$r@-;`IcxVwKC-H)^9AIGq+t!FOR-1
z-e~cKy`{lPAfP%QR1~Pi^KTgXI~xp++C685hkl{#t@>{nK`H7Il4{guyxD_|$-nB|
z`1Z(vUGInT+%?rIlVrCJY5<8Ks=PDZe3xX9Ur|l}zMH#coyTs78JOi^RUi>v1lP29
zx3e}Ivze|%wo8aqUB@byOrhDuziO?IF>hHwkbOVnXdgdFT$1aDXdSIzKOXPy4|!zI
zD2K>My0_XfcQpU|eo2IqyBQ8`kdxE;ZFo#<l&-sfm{{Jjc8O>Zsn&uYt;X?A-=0SQ
z*x#fJP~}Eh4^k`sP-X`NyFn?U%qi%TJ%LR)dyG_+uWc05&mXVJ>|{5sar}*4#+DwQ
zm0OOLLBAZq!Um6=xOq7tBH)f~3M1g-$*^&g{~6K#+aZeeRXz&@KA)q42>(Sx6X;0l
z5BfHVTya~<+-(Ui%67cnHQ|4EDm4AINnEyU;z$idT4*k=>)hYZqrZU>C|F9+#n-j^
z6?b2hT;%q=dpXjjq~y4@A=JVhsVT>TL@=GYNeZXEiri*AXwP6&8Sj8_CW)k3EFzbQ
zS6hOy!m|)4S^y#rx;F_BFUvDMlJmvc{Np97!zu4xV^g{6m!p<qjf04o_D{dt6{F&l
zviWl@%vot{^XztT0SWS8;j4PQ+au=K<~ov>W2_8x8mD4m2v)4TQy198yzqFcO#?Q9
zB9Q%Bu%hdwMx}OarvlTQ*+~gyO}~o~QYsb8L{&@S6u!(O>kqp$Awl@k8SDUzUzd?{
z9*rg@)Bc!=x+j=;=6B`UyQH&ho06cqa@M|0#!~_7y*5PF2dox)CGb0Ij6a@;?ac`z
zr)9M&-5c)yCEz;I3G0`{5EPnr2^?2nUW^p1#XY~OK_7FW-wXz<>&*Mud*^fZw5Mr*
z$Fdtupp5aBSJ%@?a)$AieH-+k9NkEOcSfYPNQmR$6n=>(0aF1n8%wx?gjX6F&$qE8
zfr4NP54&?Q)U}fKwtp^bNlcO``6}U=ekjMg9f9^12l`l*6<WxjVEeS^4$y)wL5X@z
z^X(tGVa~P&aAh?3jWE;RU#+TT^jh5%8W`8_0BZZ;(-Y@$la`XHg(kEXoC-#Q^9Wj?
zewhHq_Iw>(ZKFUnsqMf!U8x~;$leWBPP5hvZG8!Q9bM<6^`$OW$ZY;Uw0hAkZK9i*
zd@acP49|@u-*$(ol$wU5<vO-^NY$n1Kniq9SFp&i@s4rS7$%`D*`=mWeqmU;shkn)
z{ySOEC<97b_Y}Og%_l?YA$;h4X-kDnU}^VYOTrwKANizb)6Fo`xW5ia;<c8uX(*S&
z9gzV@%$xBOD@r36XyQ5U(+1aFrwtdSpKZcnAu%|`jBe?_7acx{7u?~2;ro1zA5PU*
z(`@|>WuLlW)^Q-n7gv;x4NiaYAT~6efhtETkldNwv?;D$ZaE3)KY!8O4NWO0-_?Lf
zTELa(mO@iR^S+&y1m>Y0>QKDh9=Q`?BOc&Yf@_s~N_mgg^*Mw5=2QXX#Y!b>D+Y9t
zoO3xnVg-J$Fml2>zy_drtKk5E>Ij~|*>Ktxvkh36fMdknwDan1@=TOoL0zDuHL7ew
z%x9M)?J`ygbg@0Lg=RmCfI2a|NCfEbSG|g(tk6k*E$jMH*i-bG32(bn<~9;(sMd*&
z6(!>*%2Q-XGgNJll7ThyLRo69<WEM5_Pr;Ika_#V)6QIhwH%u@!pO!7g32M;nwIJ-
z>a{U6e3V*iyOdmUpu%*W`nWEzb>jACg~Zt<2-m3nzbCF<O{|?F*2|MDRt-&xclvp_
zYBoyG!K!-iWW_{||BK*H7T|0EO(V3b`PhM@iTpz8F{u)vlTGmqw2-iLqdx6j$={q2
zeb9P}r%7?<GOp}o-ig=nJnw@%VG31?C{hMYwT!SiTPdjBEhN<!(AU-j#LpzOj<p(U
zx*!|<)=z?+LOi_F6fkbk^K~h7xTuQ_rR%I{8Iez$QeuQOi+J@%OZ>sdpB(wJ{xh8^
z2`eU49i3V40AbegStv2OMOuE+qiOw+?Lv9l<tI1|o)4VFt$!zpS8oNlq$QQA;c0F7
zb;~a#6E~gNUc7s{;G~gY|0-UHB=5Y7s6O1GNw()I+ABJjRQYW#(5@<lK$=D*-a6cS
zj%4~8oe9x(f7z(v3nSe4wwiWaSSP}s76^ISG_!LvI!5b>A<)Cj(-F_n?vxVT^0FQu
z^CAi8{?=~zOL=mN0cHl`FZnIs-d(4^$1R>m08+e7Q>SNwSPo4I0-W5BE?;O`Lnxfh
zA2d4eMvDpX&C7Z!2;h@~&hyPzT4kWgRQFxU?@hF^`)kdW5{~kcuYnn}XK)`A0kBB_
z&BtT#iyUJ+$JlQ~a4QHR{t=WdKp01`4oEM4*4yZer<B96d_olL{d-q_+t^2`j-g?J
z8Wxk{j4CdJ=N~VprXW1Z8ye<Js;;&@79szb7Dzcd0}i#e$OOUPXAJQbh(0FB4v%TI
zg31a)fGwq<u$a$5mGknJlkAd;n9BZ)xsx{<LN(S*b*im0X`gIQ63H`}gBM#u+S?g0
zp)uBjf0Kl*zG%yLIPlXQi%AS6{k3y9Y<nto1ZQwr-*GgooC}*l5HC=q;r>b^#37dw
z#a(6)*NdgIA^$vcIr+P35?1GYx`;$;x0|oV4ATxW-K)4W@Sjs2pRwyOLI|&cJ|;Mg
zV(g|nDb2Z{WTJewlT8!C@098a{H=dVj9?p)qWkxci`fshl?Oh>+X<cR0(L>g(t8D^
zG?yS7w&*EJ6(1;An-#VZ&9*&T<1ap`4#?e>SdJ#7BLbnSH9$3B+KLcS*I$r)^ma1%
zsK}hnbtYP)Pwy3PTQ`NxE9kw#)BCkA5FBTSpB+otRB2lGx6@PWL?xe1Mrni2YZ_ax
zhBat&%Ei!`@ES>LM_-jjkZ|Schk@AC#mog6UT}S8O{J*dI<qjcby1Q%_O4NAxP4RA
z(9)dZlJmOSLae~}ZI8n6s-kFQ(Mq%c(_a@Ww?j>ebQE~wR9c=v-wqj6$2+PxV-*+=
z9IaNIkR3hl?<ecNO)X$o-pfQ|cb#@bO6xdd>0Y1Gy(hn69fmbzyUoT=;`Ceax+bo-
zi#4kh@1cnlgB7!JUtrl0{DR>mZNOOTq`r1?p?l*GnYaf0CGls&tXpTe3bX||wN#HG
zGdeV=uPQwXn*Z<p19pnVwTcT(KFZm}@-CyIDu+_ilF)Mk<6cq}Cx!ISEZb6|9rwfK
zU=(S{F1>>BXW|m|ay!UlzGRK?&5*VMmKoO$K3~bSEeyU^n^ka!yDh9WCPa&MBo{TN
z0iwD}pf?qQHnR9>up7U?;%N(lA%ThHT%}+e4Tyuu%Oa;M7d>{DDFE{Oxuq<sY(eN~
z*?-=6x2jH{e9CpA!eiR)U#C{6P5!h4&ko}T(r`OhPQaN6ntNKZg&iJ5Nji_fLur=f
z4%=&F78!JhhwzU;nn;)xF<Zl|CtVkW5`N&v*JR$;*4-!dibbW-ZNf`zu2Q>27X%;f
z&Z(3j3K`VKz@PIu+sJ6Kx*FkqEuoV5*3xOsRfzlez8h{;eH++W!?OhPLZ0_!On&(<
z;GPGx8y3yK@*e*yqGkx}??+<kuG)ESSQX3?__6nN7X-2-<Gnp)iW%H!;E3bFVQ(dM
zb`6e=9Jj9wrW)qmH4gEUUC2+#q#zdh;v_G2X{axCM_2va=Ss+r(+-|+g#zf{VUg1i
zVBc<umtd@s-7oQ}>dX~xQmP2jBu9eiDcJ|V*M$Z$x+dyPoNVeiPia%C8Ij_Z6(&>_
zDRIfIdGWX&A;Ka<?wn04D89cvmzu_zf!Rcr>6%oR2b=Gpcm8`HFMxN&vZ}I4`qtb9
zmdo0Yoz2TGhMjF=(0WU>X{#f73gBC6#)dN@%w}3435N8Pe|>n4nrK0@JA8QVuSUS1
z9a3@=GFMQ-V16X7k|yFa)aeG|SJ0d_r~8$0!l4iDXhy@~6xE2o&)^7w6td&Lr7SE@
ze0_ulZ`<vd^={Ig7nus6@fA9Z;R6zUDkBN7&~&qQ|8D)*Kvkynqw(yP2yfmt&Lzx*
z*VjM-1;Z`$DQdq*ks$r}=}#(AWJz-Sw>u`Q;@6kyOQwTSYnmd@m5x>(gjWBLuqs|f
z_=C9JX`4m%tauys2m3a#5t(`Y&?Ahfhs*nUaDFUV=sYV<0oMS_(%|Q0!0Nd(f8{^>
z=iUni>DCXl-~(2*CWjMFt`yrAB(F^?<c`@6|C8g`%)gVh{q(S2Zom|i)e<Ta6T7%H
z`NH-COK)JNcwE~#dWylPpM2+PDp?e(-<so0ET%+tOq&wf0;Xak$GOdvv>)oFPHXqD
z_6EvA38(#nafJ}{vVJ&^X*tN)=@Heq_=eUym>UwHJ5K27desfC@MRXB@0#M1b}5$n
z$;4BSVXX?^^ONzmMma)Ua5xCB6En%RQzZiUaF+eUNb1XlT##iyj=$b-XcgN9?c;Kc
z;2*ephSJT$#6?+xakCVQS^`RX5Cr;Gmm^+GQ1sGnhYzZP&0%&#*}oE*<^nrF?eJIx
zl#W{H(pBHGR@xcahCM{@=2(xlt_MHdnh`^9;uYbTX}0IGS&bo1p?4h*BhYqQKYX2O
zkttKgu27dg^KomIctkKana4m(3rr<1?UzLmo+@JJao)do8=r}ASV*)A5CSN!#+dCp
z#bQaTay9U`2qlBxPv>R1Ri8<2EYVA`I!CSZJ|3f%O02AH=`a5x38>_zA<eBE%o)Ic
zp_D(QFTEx!IAjo|^72NLUxl-ziGD=S(9f`)_=-$wL@7^Rm`oO$EsTQ!rzOk~AFOFS
zPXG1H0*%Wf`-Ku4Yr7?ESn1XwA7#zxSBs)%ca0ZJ#bxQd^K*n>x!psvaVd<K`^1i+
zQQAFDQjKYKiUi0(?bybx{flBwRPPNgYuCUmGtrM?55`*o?Z_Sk=88$pwpr~b&%4Pu
z>1E|j$Jiw(_`_D_h`XaGCz5k8@sp20aIg?6=5Bw=gQCMnO?w(M&GidOTZ2$t&sM^Z
zo)Z1wpzj{}+T^4&L%%GgYGBu6A4Uo0w4kKJ-C17v*Oz1MGv}Gf;2wkTsL_Ev77dnv
z{I~vH@<_f`Y>&=(VE~oByTsBSZFfPI6JA8!2@jmn8t4OT@+#Y)vqCru4kXA&1#o}*
z0bSOqHa~!_t7+LtU(JY_c=70Ef7-#`D{W#nYQaxB6qJ^6Xf^2%f~=#1Lt`i-+}aaX
zN<zcKDauMvFLtp-LY*Q{soDR+>F3^IybUe(>gXxPQXMN9)ofYz8Bh$`*!IT)BwiEJ
zWP%FP=R<Q!X`IWU4D5#jA0_@)hPcww9441i|6&ZRN+)<&iMU4uKoJJt$m$?cI01HK
zLSOTEwIc=^_+??rAx*)CWih4!n&gBVjLJBvrVa}7XDZ~Vg)49uKopjAfayWSRE--2
zm}(eEy)*({Y!NqkR7cidb5!n1*QU7!RHHAbq@P!WtV@SfA~Lix8-ZSp{e!0aR{0e9
zr!C(A2`*Qw=*C#s5$qVA55<fa{ir`dmOdjzAyh7?>grsL3~eI}Woz+iGX{c)6?MlS
z7a>+(67d9VY1Xp@MS-+7sF~DpSFdaD+hsDa%9eqAvn42}=^m8}hqjOmAkKwkU|Ls-
z`%i#R#$Tr7hVP2$V#Y9eTnOSs_xxxnvC0g0L}g=;Hric7$a{WZ@*ta4-3!6J=jMJS
zwwoK&wad*14{}AY*==TplzqPdMn=7}oj-ElzO$|^6SR80$Y3xOXKe|F<;F>-npd@n
zN7Bx|#$x9J>f$pRE0(JV;50hm0EIp+-?1_OI}V$~W1NrSj>$Bf)aJa^6sRu3>)j}6
z$M=0P?;o~Rl9lGhrM#DK2;wSVs8%`@%*j>g6&<{HJ_a1%521dG69MPhIOHP8@f56Q
zV*FdTq6b@Lw++iF9w3m1z8qM?p9E%PrRdpnm3VA?UE>sT#L=O<8M^k9F^HjQr-KB5
zb5ef;gzI*-A=JZ-E8e^jAme%$%0aSL!}9(E!nQqM>m<?~AtBo~_SYD}tDC-KaYlbE
z@|NOh1w@~0`SXbkJV2yooB0Tvv7bIMC$&Z$o>u5oIIwbi>8^$F&HOSuNaEZ$>kF9R
z{W(<J#B$31-?8<L!ytW$x!o5$_nVLdkrEM?Zk1lsxd6bI4=IF*zXJiT=a<@))NhY7
z_yxYHeH(7ndL*2NO2TG!OAw|~7d92Js~CuuIE}DL@3F#61$GUh>BT8<g$`o4_hclE
z8(qLh_p(Pm|E?rDUMy?e>UQulvEf2JIkA8&LXvq04ETAzw0+FXK8MPo2D;m>m1)ge
z#tuX>P=r7?UBep!x58HZ*)zgR5)U&3kBDBuRbqlgd$^lY@qWv_?d1D|lfvhQ)V6r=
z2@GJa;yGAZ;=ojiQ><<dAIW#wolXkS^d!*UnqIj1*@@}t2vMiDF+qXEBT^xb=w;*L
zr!N+H?%th`@1dDzPePycnkXyn843OIyytF`wrz0+os!Lr#ix2mLIsGJ^^C?EuSUrr
zsi;9idC&K(<T!AwODr$zs7J4ECM95e@FV%p7ghoa!mwTBpXc2sVOvSj%bwyL8kH)S
z_T2}!hbNWr<Ydbl;6;Y4*K7Qndvs`F;3<eJoS>fb(p@Vo@=}vFT{r(n<x1hX@l6g7
zaU%kj-{oj;$Elc`_)>Fqx=ym434GJJIR_k=k*+DjX@v4LbpKZsOP>(NK*N5|0eD2>
z+AVQ`m4O(gjy0Yb|CYtZ?TT?8<{vd1W(kD9lS}^q$Km!kb4Cz$#y?Db9w69ps9ynY
zcNnrG%JvW#!hFWvAi&W(cvtCM>2+rZ6)uUT2l@(`JnIfT{Une{c5t(emyc`Gzd6R>
zH=NraI&@l}zPMqh1>`iY=vDn_Dq+%Eb8xy=rL*BdtJ<AtltGp{9?igzW@FoKxe_n}
z8JsSXpn837r!FM;CU;9OSL`~J;M^j+g9*$XELPi-7yvpz#lO~qC75$;<PFCfF$cvp
zYNEFku;zDMzU*TWGy{P!poY7{zhbFN#Rx9UZcPs|EA~&I0cBJri)?pRSd8sq=~?Ol
zhAlaam`kp0y>Rt$TK#7F&hL--4`$b~#j|hfOZ2}4w`pAZ-_v{c92Gy%(ULRl<QTGn
z$h_og6Vm0W7`i>m`-w)<z4_=YK^Ov}N5|v0Oc(D<N=~#sK_>w*g~D~qVSsV1vr}**
z^W6z-QI@tk$Esb#Cq@)~O<iaH)e2hDvDIS^6s#3}x#H)T<*ivsc@h!CNs_z}Yyt)<
zPx>fr`4zkWFizYAfj@BhpM}vP2k`L(y)kFZ3e)@y8>*FQup6&fNK=1bE~|5Y+D|vf
zzkTM-&jo}*T7WBZ<Np|GCXTF+qiu?w`Y$fc=o>(aPwQ*tj1R99wvo;S<Y5%pR~AW-
zmFdQ1q3#k*-(!&TtwgKSkIK4ep*Zp`hu)#$$_Czg!;n<@qelb-z&I4+3j+GdNIvRB
ziIXfYE_EgH1!X6r{!|;fxA(B)`<si^D$H@tAN)eFkVfNuTa7(L?P{fr7Ea6}ul7_I
z>0q6n>iuXM?RQj&KN`_bHq(Tvg-E~ro^~MPrKGnOB3aB6gxjz)NHXK)n#_l}HmI@s
z=9`^r#BKyqUZ~D!Dl}OOAR4DYSAws9Bru15RSwPcsc4rp>5%D;*0d;=WDuC=WETi^
zc%0+fWfft|IUL{5I*AIgX1o>^VDqMZtwj@W{yy@$ZkMZZbAnasMg~F=mht~KfWqs6
zau{yh7k&$Vo}pukKqHq-i|d{8jKl-<rAph8L)N4d2pY4#1KrL|bO3gL%1LY&cYgLu
zS|;vrL1mDa@!y<`OL!HW$}S83M}VyjC@>lXU&7YzSRwwh5H5*D#iP&6@dvYg%9bcc
zQU%<FFftNFi7ckGIet{h<;l6%uIGlwbvF3<?BHIb?bOLb2_yT4?7T&()AH?nk^JW=
zcl8*cS_w@nxV?KzpwvT4Xm{AY{L@pnTe;ktZ@zWk7u0*ac@_*`>-*RS!GSPB+M5_V
z@7v+yXXmA%y<ut4<(us-Z@S(*XFPh$LNo|&UG<2pin68njI4obZmEqd)t+A$b%RZL
zaI!k1SWEqnw0x~t3K-gLEspbFxLaOu0$i??KCK9%7Hq3%268M0sX|)eu^(SL&iTpe
zyZFh<K!d?C8|ammJ1x|yBoh^4J0L~UBaV5Jqy0z>GOtAqXlF(L(rQ7sU}xwAe@{2_
z%2%oD(Wt+8&N<?MnH<gehw6S4SPL`f@t4ArGN0?EsHS4eRfb#U7NWQ$Jc5VBLXCZu
zjZ08e#C%qaL%Fq%Zs_QR$rG$y?!Qk}(1F(AnKf?y&UF%&byy1T%`n*Hz|P_&1rLZU
z)@*>cP;V<eK?>G#KfXgbHUd4v4=bVpu~B|a$LHISSpKj6%l4_hvOYryuYx#iPVk0I
z;dBw6HjU*Skbp3&CwaS4k~M0p-4`N4QmPS<Qq@(oe6)c$DF_O}_k>CuvtlzL>c745
z%ypMA1mJ;wY9wnmWIl0o>^%K=Dz+8-X8}cyBp<c}j#R}|^|a!nB^waXo7+JR>jp=Q
z*yk7?xeIffbm>2SdmRgNeD8P0^d&bsxk1WW!omQNP)pczQMvk5A&1={bDi3)WioFd
z?&>e{Ns(G*Yja;D%!VmNSM9p+TUR9_yAU{Fr<^imYR_W~Go@}kW<T$r^?#H^dHe5^
z38>T=*9!~k^4!S~OaL}$v`pR$4J*tu%~%7+?JO0B*vu~9o(i~V(|KgWypnO2n80FE
zYj3NYpbdtdLy(3(X{tT>odn0ju`rdpyRLM^b6x_K6wDhWm(@=Qy7ps#YatHH^hM+u
zDEmCzq6)~EGC`~~aCE$%GX$Wz9M<X>2z*%Q_A#o6(KtFj8uk_*qZfAAVoYNFsafr2
zDXGPY&xCmOH|aP>mGSnoyDoKQuo(0aE?mMtOQY0>#mW{iHe3p8Auiea=yWAr(^=a3
z5<36-A=cpsok8|{=t`iQjWrQnx<WmHZ}e0LB?0B}z%tcMM}6?h628uIlg<Gin2KXv
z^`1M}II=94L9t1h-7>%RF*unLI#*mE3m+Ay#;FgtrIitjcrFYQccB-<SERI2$YOE*
zy3DSO%>ORIY(^pJW_BkD4<Nb_Z^+S}>vo{#42*4d9_uvP=>0P>QINRB&2IV5JlNRU
zMA$&E2yJ<{sM+@UkeMal*M|~YO!aaKUBque+61%7#z!`K$mLd$Ua*hwt6!&KH2kMJ
zSN}&gSI${nC%Hwm`^#ER3$J-xn+09h<w6)>I=V;`!){GC&k9a3@~TED6-44n{iP}D
z?%B55b-PCYN8_|6y_&BZl(i~b{MEl;iVho(yP*3xwJw-aM{$kmwJYsUOGfmDX{9WW
z+!hA30$GxFURPq3W3BnkW$Jbjvks`*fSwiP9&Pys0P$)T5V<&hoOc?RlSB8=!c`KT
zN+h)oLu}hTCKp0)zc{j^PkENRiIsgydEDSb18j6@&QHM#@s_5twtvOxa(4zwYBDVt
z@e+Dpz6mTaa;Pi*y><sNSRuXTpU41&H>T_3;u>o}uV~SvXHY%VBi|Y#H(^-4`B|P;
z2rwAOGH}ei3g)>ZlU$xSy(axbEC7FXRVGqtZHQmoU(>*r?7C+4c;OP}V=c2%2$~7e
zk1CD>_rpbBYK~)8YpZPv&ovnuZ&e&^Hi=>`$ykU~9kK}QPj-sF5<3Ji%GVm;A)GD<
zAIzwpH{cSps#hg54N`sAN<o{-X6-speL1b1*}BT`M6Qyigt9+<@e^V>w!7U?9M4;i
z#ufQ}D{R39TPq@~HM()HDs&K4d#M(MJhks7m?L}Wo8a&<x}$vm8FNuJr4K0-ieasC
zuk72Scz|VI9DFm|XzUmT69%k9wY<TxgX^`2$hCwA3M=#lxUulPh}}X*j*h(8{GQZ+
zVi+Z$d#sF$<MXB>f4*%}Kq$v0cV#7*$<_o(uj~feL8XJXaB7D{V3w^qdH}cO#3`3e
z_BZu29R2+<x{46AZmrZm5E-q@kqjoh5k1+3_~i7(im~$5O!p+*Eyy-iQu9ScDQBi-
zwv1rv8{R_>{l2*=*T)sq<1t*Ds7$C+c3lDBo9LE%r=2R~wI(=AS)16QRxlU}Qv%l`
z1rffkt@NlNrb}~Aq{^=tJ}?M`hy~{K3zoGRVTu00XbPln8rvlOz`V;qlhT@T@t^z{
zZ+K8JgB;+whU#8*O-?~!5D#r|`e<`pJ+v6@pwzXUU-C&rcgu$8U;{A%S96RDK434=
zeg;=1(rj9ES2YMP=W0#K3v@eBySX`gEcJh47R`kvJASE1zpMxv3L&!8A^b*Zt#nSk
z49=br-j}o9z5npTj@D`GbjQ^n530k_<f(+k3{WD3LP0LS!7};O%P|bQc8>2GBXKMb
zgaw=G(sQZ2Fcf{<78nyZlTM5Yi*tztJ*11*qKZP%6wLn7NL$Ap`I(3pxyT_OpP=v(
z!{-qq((MB7$c43N1C73kSk`bp*lWJjjYn}4Z^HsX;;YK6+Rfv=S2d_Z*5&#VW;Mhj
z!|Ogv_&)3Lg})|6u+V%1Dsdh_We;M7@~Zny=8E`ItkmX8^BWmu=~dK*y*Ty_ksubl
z-N9lKlS3yObLucTD_S+rxlA)D>TR9s-v1@ngYP!E2k1nuPaLn>vxzGy>ZModEd(G9
z%oK%=^g#SWlNwBpwZj#M@=^a5S!Rwm8Xv?k!Le?aEndemHCFu@8OW2RXdn!bdQpGZ
zuVAAMeQV4KO8t6;ai&PLmy4_gRG$^Lo3Zb^3?OvBcpT6CW(E;p_qWIEPJTp&DaLQu
z-Tm{%l=X{Fyy(t+OiKIYtcy2Q&uavaN0sdNl$LBvRzSNMU{U)nfw^~jKeSKWHA@wR
z;mFoy@;rGHQ6ko2G+;`VlFvs&rc@Z?YZLJX@Ic0C8o)6`gt++BD5fs$GJ|Y{jK|<X
zo>^HWj_=G4Hw6~Wn*MRUCvr{B$8|;7m*n<;qcIyWB3eUjv!VWtx~^jS8j}tozFaE<
z_V4^z<X)+&c9VHyWA%^gf*_%|tXHTQ;^c`2Ejdt(M?!*QY+-MC*tEaBk7{Q$t^d!a
zPP=hh-rc>r3v&Fh$QGCQ;=>Xdlm3y^iQmu+E7Eyv!LIneTEe5>R#zTCsL1*|e{e9M
zt4cBZR|&X3@z*KMdTZ($()s0Q3&~)zJZ(_nG23w<%EC!X&)v>L1S6I#_XG1gMDDuA
zi>$=TXX<7pc%^z7rOR+ZI~^Nr&%!`|(_B80WPr+2W0i_|%&rS&q;8-IK`^ARm?qSo
zW91gc^A4PbCGAtc@jo>5`d;Qh-&*VL<E}aFhM@7ss(p0_T#{o-N&Ts~B8;r0!fNIb
z`j4@x(uwa1Z^(J2k#(wtV$=E=M%c|0^k7h#7*R#iR5J>+QSc@d5pVwC^@*C3H4(EJ
zk+Fadh;B+*-RmMK%Iox4B*)ysla(_5m1y!fNENR7;VB9a48zD|m9QDeSz;EZ_1_zy
zV3)ZE?^p<#DEmcix~^z>ZKi+Uh|P672Db9W#0MogM8lWeiV}UStfu=@2w++$<}>9}
z#6^3!PP>kSe8$%*`lAn3n|1%b6iw7@lqT!1hT6Z9{jM6X(ulnELUKufs~~|%{x=`L
z3Hs$!;9jht*R}AeL^&d@joT*5ytR&Vbqy$zl~1k;>%ZS=WB}I(B7p>#pCgQM!`ZN8
zKq4M1mfj7^a*ch5ubjpKJLf1OFTEGeSQqGg-O(?P*kVIh0-dxjTHBxbv*8C8$58lv
z7iG7K#%=t?1PQSlT{?EtqZ`9F|6I^k?dJ+4&`AaaHe1mm@0*^^#5<Aa01VCR;x{EA
zPtnFnTnCvVj3&IM6}3nOLqVOP^z)fTgI@<zi`ETMoVB#&IO~VVK7k9^!G_qygRIA5
zZ9oS|SLUe|=6?nyiDYBmL@4t;Ui}Lz?jF6vBmCr<un7SN*1=J>o9{FJok=Yc({o_9
zVAdq`8$D@y29pTTuL-!Cm-$L?OE%sfQ8VMkkGW^OmA;V|sdw<EIEyl!A+KxM!w7We
zbQprF;k=h5FOzV6<Jtbu+~Xh@<l7mROl1eL&%HM0Wp#^iMPQk=Rf&zrHv!oIYT&gH
zMXPil$W?yRoV1ni$tR(gx7N=XWH6`BY$8B(#pxJmRarvo3KCP{yS?lfA*32DU77>4
zUtf#GT+CDl)G94*7Pp*#*g?57r9h)Uf}~L-T0+wC&2`GDL!ExFRX*v)(S0;34por-
z963^O^sYzD^m+Uz{-N6#+Aj_B>YioQVFQF3ZNm7?I7W}=%Py;Eh)lfWS?=m_#MoBg
z`^h4Gb9R$fsst8!S}boNO10~OodxbaYcv2j@~~hZohWy4$ELbEryjz$1=m7E!JBzD
zMcSi(-^GI+PM5D9u^bvN|DZ>&nCrOT5a!WB+n1KTXQbXsBjH1`x!6pY@=bdOlvm6g
z%j7h(kEE4wHo1PeX2A~2P)pi&*VhtWqw8022uwP9xWpTR;bLl27LaYq(^en~B(M&w
znhwH00VA(W;)@fvlZxqjJc0Fe?|A9(5^LW7M_~G5ytcQU(kAqERC&Qoj+4vPk6SDC
zsPxspDHu+|V}RP#IUFEP=5JgXkYccbK->gV0=pw?Xm8c1R4Ug8;w8td{7&6`S!g*-
z{0qcM)NAgXJ;qhLT_v1+c;zfm7l_u>QCKs?`h5`n<P!BfSd=IcFHdS4P6YvMZ_%gX
zzz#SV^!(fWV@lb44+|XhFVLhHs&Kfl9%dPzi3Fo$>Sfi`8XBrLcSnc|cdc8wgFe2j
zvi^p4)-V_;GGp&LxjL$9ZHlF;xnvsB!`vn@z>`F!@UBIH#q+32O3+L3X2PZ!&q)Hu
zY-@*$#W@|7R^dQZ<o{$I!(#B^uhF?0WBriRcB4L#E@v*1x0aAeX{RmUB^=CF8O4#I
zak?zH5q1DI^(I)e-iadT#!YWN{mZzlrZ#8FV7qf>cCawB)`9%|=Y2#k=<#t$f&%H+
zO-9t&*VGgc2{gUDfenN6D*Z2V7sK?q$dDxJPQox_>;s?a`__1UF7}eZsUk*mPO85G
z+A_50#Dm`5rg2kG)^mqQTNLvg2tO_bQY-vj78QVfGmW~6B?>s{KoARk^FQghYx|1e
zUA~Z&Q|WSw`Vxgn$q%HY8bx(+ay98gtqQ|}cV}lTBn~fER^D)9xXgE(3*xD<M9379
z<)w)=G7=91a2ySI1N40r{SfH%2R^(>cIrY%b94iQ!%aKjw2K6_w_LBHD}feOMnw_V
z5uJ)c)RDr$uTH<j1h~HP;K|1Y1*PmojTn>bto7gZ+@9((^w16t;k9SGWm|)_7O+zh
z$JKIw27d<&vHHWN>$#D-e}EUDbig8EN%^8d_z48rCk0sm0V_&9E>RL~&Hcp4v@}8(
z$3W)=ICuSU&kx1|o4dUhc>eWDx!CS4C|umW91>SHSmzpZ^z_e-?<fSIPsX2B`yrnA
z#gQJ<hdNT}*a?a;xq0q!c1<dTJ8oSfuteGx0fZ{{qALvLo$`lWJeoo<{N5OsoYk+w
z$g&DceV5N0NwL2|c%sBwfj(;x>PQy>wo}&)ks&qVKtGruY+3u-{L`UOJGz>G`SmgN
z<!yA%ue_5p8gQsO4)E`Uh}TQEnB*mfwMYM`7s}EsS^{yG3;ffl#dtQ=dc0DzqLYcY
z%ao9+6uj$Gk^ZJZxoF~%m=x&G0L@x~i%#@+Z&bC7L{!$b_!;1_wdY{Q{%5p?Tp$`~
zOFBzlimqtPJBm^0xfF6sLgp;m?JJbOz4)DXYzN=^yU!p6Wb>$xB+KY}$z&tCRi##T
zU4A>HT5aB04&7_VsKL2$R=8Z^n9O4sitOnC-xx>VUP8pt&SUdpM`~ML+Ukv<#1F=T
z>J`r#3)m5PdxoOPVE@g82&$u7l*=Sf%I|PNh;Gud42u~NwCj{poSPH;^bIW*B*l;O
zDSa*GQU(JbB@6S(5ab>yf7}h}-r4V)>1?(ZXwgD$rg=x^dACGTg@<Mgk=jU#{%2K9
zhA6$IZWw3_i?v@c|CD=5Dkqzp?D>6yvaQ3FmdWCib~8?|kQra3*Jqb;ZLYh*lI)`-
zUPBT~4f}m?s;aYq=ekHNRY(U*0OeDVHQNi&qlorvH#W<NtF&uSFv?(yzHQzBm7XHS
zyRZweOd}t4)Us5!w`T@?KtiD$-*)-oXof7hy(Z2MVTlAH+fXy<QlvW1?`aZ+%?qvs
zw@X_WTkI=s-{_}C{Qsuy^rVUO^Vk1mlsVw)!P`%@5@gJnOe168yaDu*ZU6|U$4PS?
zjSxZPe4$f>wH@0qemo|c1mLNgHb*pd9;5}tg|FpU2Zvfpa%@K6+88>1dgeYD_T8Of
zuhh(z7WX4A{_|48f3Hv62Sk@Y3vUqzjG_R#pk@tD>T;4%UvZ+GFNV3hGx2T~i0LwF
z(w?oOyMpElf8WCRMDCSrwQ^Dm7FiZQxK_x^96x+T4sEcGl^~KQ@NcV#iu0d3;Qd)#
zCtL8``HlLOE$*bARw!G?Un`kcnD4i0AS_hvgk1@cWhog3>A9)Z9!Tdvih$Co!&qiV
z;ic8OT$q!jYzNEorUhcxjeEF-<&3YKi=zt-8`gUc<hnHCC!PtHHb|<&0%87z8UDZv
zjPt#T7&JSFrBDSPOhk!f7uO%l2%+PcMI8AFMKT3&!ppxguu(4g0DQX1rGz2&@mv6D
zLl0<)DjxJR);v`Etg$wuYbXs*goTtqD+_}j!x-Hw`<uMHnd0McqWS$gQ0hNPbzul<
zoBgjXT>A;RH`+w4p+zUSW~HmVneMd3yA1I#j*@LBe>%Z#^rb<C2{+k4a{UJH`$N}p
zEEep|s5%PkDcEcr34sO$^ow!sP&ejT!MYGUpT_XN=@WI?>UP9GMBm5TPNI$9OdC1m
zU!N+4S5JMmZkq9J?MczPdjN`DWvBv{S1|)Ahn1wf#Ql2M;`MyV2^m-ZYTQSnpYeS`
zzs9Xz5^0zzI_dH@WiX#Cmy$x)a9G%!KzKug;;=yuvC8=K^>mM9vzl7ExEx+F0VP^+
z=bxj&<!AY>jI7G^?x#yGm4KDEDyHA82VB8beU*E@z1HF{H%mM3Q5J^s)Vo;8Wc?O#
z=Vvy#;;1<)q*A^@)6DvN)3{88)XCeFf#b+_gSs3(ijdk)A=H$dfb05_q?x+^aO|}A
zUp=OV=8@R;`qjpS*FtMp51}Pn*HrSUYz(|rId;KimQnPa456kbI#7O%N|q1-SH{>0
z{YIrT-2RoSxk(=o_ji4Rf+~)5-mIRcj`!bxX<19NPJjiENYC6(@bvwMGH5eCd2Et<
z$UdWbZaUlwxaW*MhP|6^L(iQ8Cc9vJf4BAIOUxH|<PkrdIuPyN9ReN_@Twe+S5?^J
z4NF$ZuD|w;`)Reu$jSTBcDenm@a+AWj4kDoP+wzssD{16(f(Nm^t=Nn>d=ZbiWwsQ
z*2iimH%T!QtjzvN85`ubl+~OzmlglUu(f)%J6|8VMToJrdj;4Sf<iXMWhPV|C`IUD
zk&In>cEQZyObKrO7l5KwO(epWDF4{}B~P91{GUgN**ijci)<n|V{SVu$ApK4aJUTF
zEEVHI>?W;Zz&A5b2A=)G-|pK<#pJV?b--!>dJ4oCg{F)ET1wo?!12Br1E<NK4u=fB
z*#WvzUQGlBKkn38wO-_qjMF9t+Z;;ZIgkavOB<mLfUb|LtKkhq!6M7&+eWq{b*j&#
z#Nh{DnO^|_h6%89YE;8$%6wa4)8U$CLx*2#;AU<mIyR;@M4m$F{**MlpQPtU&FG!?
ztwIgNt-Wwk@+2wI>ga|+@gOhD74(^CnY|!$`@APysz9%me|vl#Chk52<+E>?ZfoP1
zlrbA%fNMMBHGvFAr#xwEH#3gIbn?|OTkM2QU%_|>#}}_5zbQysNw|5*MbN3Wkht30
zcq{)VO@}^N=C-#`OEX~in(6UWsY`V<)3GDSc_x4OWeS46HKh8PKu_~JfN=847@+Al
zOt$)aLb(I`BID3Usq7;OhimFS+eL)5)1=`eh`v%_1nf_S&-R~X6s_Hv5>iyj@!Efh
zjhS*9wUH=E?f(owBGz9NUnIIugioMfmk!=3yvU#@4gh`X<c^)@_1tF=zs`6#Hhfd0
zGHiguo}25R^=GrrY{F%;k+;$R31l3&Lg>-34d-PphX*~szU@Iam@LKSZd{EDmZ$AP
zdR?^BMNVT7q5GhD!RTWMYbZN{p_`BO*AG%bHu``0!kC$ZBn<ja3NeL*KZUyJs;Y1D
zHelTxkQUu0lG1<Y!D*bM6mP+^I^oTl*k@6-x(dpSAdy@uABVu7BhB3CR?~x6@wL#8
zeD}j<3R`V!riaV0@6$1ABuQ3Bx(@sNcQfoS8rWg#ruR%4UAK*dFfgxNx)@)SILoJ)
z3n-q6{Z%0)0}z<%5VH)|*Egwqs1+q05Ju8nc7MV-NhtwOL2tXDecLMRdD*(XdR}EX
zFKDd^u3CvnW~nu>`fwyT3*%;<`QEq%9sxJa1$Y<Nww(C#pj(_|nfz9_A^A}D)4k|F
ziB#}g*M?W5M0@<;5Z{7_9If{o{vk9t<87Hd?UqJ!Y$NG;jZsYuLbkaT(eGcXBLf@U
zS)(}L{^uxguIh)q!>_(Yi3elZ`!8|t)n6e|X#tRN79Yq@Iy>7`?zW!KozG_l?Fce~
z@&XyiT{=4Zv*glEZu<cov(g-G`)9$pe6n16;H>Ajp+Lb6QqL<kZR!4b0fL(40#i5=
zSXvw61iCsZsAQ7hn7&>s^~*SKew0IBvVhqIigaHFc6Aw|n0ptN1=sD@tIp$sSek@7
zelb*U6b&a4m^?S#BPLE3VT!Fc84JboQpCRGM65+yao3WfW2qNU-77kY@>~(p|2N`S
zv_(-bOu%*&2XN9#>>2^6b=@VaA8$%0fqENXl;(3D&tV{`)z|A@F3*uG?cE=nXK|~o
zk`zG=opknlER0|pQ5-*~NISs;a@z+)`rm2wv@5H3C=$Gy9jAxD;J$e5@FS*o{s}E-
z!y<hq=~#LkzA&jQBLaEFUD5&Lzm$!HGhic5jAq6e0P#NZJ_teb^tm1-ISG5Qm5354
zDfeDIxfN7s<{f6+npuo}ZEYq#!TGu%E^Ew4%ut&{tAri;D=pZ=2<IJoAFk*E*aXS$
z^h{Np9LuwFpM)u*e5xiE;4(ZORG3)^n!rmpw}DR9gN)Zh%_Pr)#HWeZQ@~LlTrc1z
z5QxD>X}S&~-Uh{AkhOWTWz5b8n4KPyyn$Ya#O2lzQ_;r~hKO}qt{1Pi1r*X2N+aNH
zvy$?+4H`3h!~bJHp|C(xR4GallJJrQCsvaBL=DOibwa*nqdBrKR8Lw|q%=&Uy>F?@
z!#hE*0AT5_IqL|X=W)SNft7T)XntEq$Q%QdDNXVD=UPFxH5UGdaw>oC6)R}Z6Y_bT
zFy+^6^_2pE#v0>uf6UHo6T{R8G7<c4ScH+NfVx_o@-eGY{#A%3ij(o8`TZltxYz-M
z^@|o85qnF+(9Dw_|ECK9k>)s@N8ER>7`N@46=F1rwOKf(e%1k6D|BA7YZhDyew&Nn
zKg(=EMCx3e!Ro(CY$L0%znmXc*+Yv=AeTgh7d;RZl1S}A2lx?CsQ9s{Xk>p3@j{};
zjb}LTy>?HT*_CpuO2P@80_Bgg^8F3m3Ec#tfZ!T<py8XVUdxpHJW3+ipU6H^4_b$y
z%F<>O-m7HD<4AKV%3MV!<(9tU#5HBje^3S`=bVORr5Ze&iP1L0^9i72u6+o)wg92+
z#l*twqUe6;vP_mr`D(~Q<tSAm1_ZikbllIl^%oKZ<BRtT(h;2xbGL9=B?B?N*Lc|@
zM(>S<iw-|}ilGv><)n+xLu}G8bgw>HP8a=UDP02=A!AprMVR8IqI*J&U<96ISO`So
zXz)iO@_x#E?5VKd!9Jp-k9-#~*!8lBw>E?K9`4!RCR@;rN6SQF-{fhRz?2ZxBl@4|
z%O-j_S<ij_Q&d{HzO@~!<D?@gqp!*fRv*QiW^%>Tar(p0c+eEjt8IkaE67R_Gl)9a
zaUY2oYlGrlhP|89+@u+7$7RxFyqdm(j7xV5P@qFQ%Je_TMJ8OgSG`x=gB>Stm9h+l
znm%i8sTZW!%t;XsL?8&6wse%vFCe-5u*7v=S0w{#UROU|f4KjzC}|*;WnbGBT~149
z=#<O&g9>afQ|h|L5a)``@?)TYjrbhNqgqe^W;Ppd%0uV@222b>u~+s1>C}?ZTNT>A
zG+RRLgrM8hm1$%^%bFgxj%nVq2Q`_nl{b3>kD2wdHKrOSpg?EqR@mLx?$svh$)e2A
zx%ML3+I<0ws(tZt%5i{@VZ?a{0M%|y+>YOJHJnQ6%V)31*IHqnc~h3HGqO*d%u=G-
z1Z5+2ZlUK8tN^69?h-qzTf9oJH4Ex?dM8NdoN$JCV{($^svao34~w;>sXRk2Uc65m
zq#2bjP4_GdLgdujsXfPypZYwfNW<Z<>n8$l;C|WvTa%R>B?@GPhTpwT%bcQXw%s0%
z;kq_{CrK)=k!n**Rg*R>)`+1Z`h-_IWJeP%zr<iwu{+yf^L0SfuZP-nR>pm0zG7lD
z3*aa&{XHefER;+#{h5%Qds#vjRnH+8zs?Gvb(Y`}T?N~c;?8Gs6#J-w!V9REvyEk>
zZ4)umXoI&$pdK(HWKoWUbz|@5zi5Oye6ABY%iDPKi<SgnyDFbtUE_j=p{%GliyD&1
z!_&<v@3mn%n+z&#dc1uBk7F~86lMcf^?lYSsRtcd);~bHI=NDPA&N<eyU6`*rXsfN
z6?DS+?nfoyyfU9dFOm9r*~x$gHzJ=l|9U;71dB*;=4#%-!re8vIFS0q9|835ZPhPp
z<&z&x#MBWf{C@bt3{Q-|OrN6FrBqrX(iNO+W_+bRDs>$|rYK57K`M;p8oOu^RSjXV
zBczct4T%!X`Zji&0#su(4zv{x-vcQ;Js+cFl2wuugpu`s5vE5N1y23(rdP*<jWNJk
z+;3lW8Jac?R?7Kp2uasnQ_!t_2Lb<J8d{ems%f{f-#a<6wD<d@9x%t%=X_pqwt#f#
z1@+yRfXO4Ta*|T|tR3rIp$z8k#5gAg7}YEV@GpT^tvjSpzq1%oB9}D<Mri&N7%B>P
zaHet|Q>cfx*Oyx1HHJGVL-pFx#q^gM2V4fPjIri;{X6Z-t!E$zhXOrF?Po42P}n*-
zssOXkTPNism$u2^Z!O2l&{5aMOh1@hpYpz|15@rG5^!Bea<n(_3jSKWrmi$<jGa6Z
z4t~mRqOC&k!r#4-8L?k@0#OPuL;7Y(+66+E!qro!(LP2Zb_S2hWa%W(8puTVExyxf
zhvt>EkoHGy{js501Y4Qju$x$`dkbg$TUA`1;n45WDQ89V4<ARt1-ubQ`jU|_zyygX
zCR@wpRbcBibTQPl51LL`7;4fYg=kkwEbqMaOVQhIKJk9t10W|n3uKSkZ2rfT&*_{O
z?^jb(qV<y5KPQb#wOoySV6m;qOo}8C@VH~0*DbJJ_gL4u5P<Fb<cp%N(-2`2fN&-<
zjEj+uBkr1Q*gLS?S(gsH>^spj`(1_3h~;Xy;^3B<p_}iL*ki5RjH7jFew){Cy<xj0
zRgx>7xiQ~nzWt!1F9c<XN8ooeIX-8c#T~4PUm+rfM1Lh`lT8~*y4S#@%DA0;D$TQr
zLo!>S19kfX@JXBC1KKmWwpqn_tW&-y-l;`df1exCO+{;R$U^j&-L4w`E?Y<6+Dw6F
zhpoP0Ty+?w_ENCti*`)^js;6Tdn;gss`0M`CV3x%_849Ae1MfbS?NRSll9Gh8E7dc
zIk!GO@hWx3E2r(J!yzbA^22>S?C8a+<(8-cWZqc~2x`Qfk{HCL%k-F49O%VRdWvJ)
zO_|UznTsu)m#6}&>`s$?V~jeWWKPz!c_fzW77S-eaGmYE?*|MTmlwA!(6*nUSt7-`
z?ETXdzH=xnh34q@2I(nNRnrafyrkm7tu$sb9ks&;&O%zUqVDH%(g!79)R;VRztf?C
zMXk(DHryxpD$~Qa6yXP0H-Rd)lEUYv^y%h>yJhUJz*OHpP1IiZju+ikZ$rBpgHxw>
zr_LcX_$ks0)Zv_{`q0ztX^wlNUvs4iCH~}yo7+n!8ZV$cf+#m@bb&HR;&E&87p)wh
zNQyaIyOlR|3i>hqm}P~d?Nq5$fAZKPL!DLQbFQ+43V1&pMOvP&RmkSA;X!}}YY^2a
zC^DzF$Q*7+k1nFRx+zfR6UPwlEC7tN?Gm>iZfE_|@bnueJpFkIc~o&j`A>&nZacQr
zKAN(HeZ><7(={YOo-qH7fY%Q_I2w2_Fb6lRd+Y_TLiF2LOj)bxNFPvHKI>@{5N>$6
zi55&|1k%Ryqr#d4=Wa&Z{hfj#7c15cWh*$m9NJY@pE;0!{_&?6i;jdp!w|1Bl(efd
z5i=ck-E^YUnZE%)Qk@SbO4se$O_5JFu78tdhRh4SY16GN0dm}oVKEm&<F4RViE2dV
zz8`zRRxx~7)ucbw8N^)02Yw0NM-^^^=4}GXX8ct>ZyOWg5I4W)UXio9dj70#b#qUz
z7M0^}1r8vBm)5(gJNa<jc7d$TKr`DT=&S9-odNJEZeyTFC2ZLP5-eSDf+805WPgB)
zanUuzDe*4AJzgyU#H&NsQHWr3Y7AW8JQ@&^y!$axDDKQ68r(yyTkOq%dfQ0T#}QJm
zi=J&I-V~-@+bVd4Q7l;l@zczb?e&8`QHS{R3D+pnE?XK>4YlxEj0yyKLZtsApvfNZ
z(F*V&<G5ZREa5Xx*%&@B2*@bIN?6LL<~*;m&x(?4&&^AZG_1g<>KN!WLD8GplnM0z
zkDr(y_UELexwJd%c|3rSIl}&Hyu2N0FZ4o4%qln-w~lQMQ`0$|4#8jN`UM+uWhSw$
zg-4sVUL$&ENQ|fX;UB*$Qn(JX)^eH=B8QkM2Q1c67?grmSBPQFaUKY=(v`VZl@Y_u
z69}@h-1-<yIBsEG?Y~t*7H;inC4}9;oBLaWx^@&%vj+V2xPLXI3gInMe-(@dFZFoR
z4p#6OUkx3XXq`)yk$5Kf<C`aVT7O1YTv&UbT{3A+kHAULt?d44{|Y-Sb~YO>uJ}iV
zv!&Ip+0@TY{?|!J;FB&mQV#?u|J5ikLzmwsc#1Eo>gNF|9lr{<`ktCX)8fG!HnX+S
zOGet>W9h#we+-^mk&CVC7|m!1ixf^SjRzr%R6@Zz`^jw0q544>NedO(LICx{IVT~y
zYk-`gN#vl>A`rJDabpHI8mlE)tI7Y%ZWgL%uM;0DO0vZVhojbQEfBXdCR^W?IK7}Z
z5YGe9HcnPp<{>o(vRB2C`%Hu;{tc4Bo(vO!hph&dYbAymYotAjp&E~iH<oF*mYIt3
z;*a)<a0b!-Q;&d%FI&n}eG2tN13I-x5CJ>$`7sQcz8%wqqxH1FrF~v`3sg_ap%x8^
zISxYeWP~0^6rPYynYhK%3+t#_+%RR>1*~GBKG1)WUBtwYGDjb$YzdsFnl>U_5~<N5
z>Ewi6Cld)cM=120iukGmUqZkxKXox<DKg2(S<ym^Xe(dPM(5w?EWw1?da+Ci!Us|C
zwPqdcJ{C=RXa&R0PWkdn(yYfpm0_ws6@#WJE<BX{yyD(>l<?Hz=3%mfj;WJeN5y~J
z0$Gt*9CT>>`|X8d0^#rfJv}wIGv#-W#%gsb(J<W@yg6sTf(+Awx1sgMaL<1~3uytV
zOrJ^cDWxN;gr2dF{`2u098|r#_A3-VTJ0QyXab@-`?DNQxQ<CJOprYXyz9ZZ>0RzN
z-f$YbPH&t-TTnCD3nra7ljEQM#&H9aDh#<4=iE`Mnh{0Gl(!2UGR<;zufsNAce~CJ
zeNF(czi2#fOOkVLH#o1bU|B3+$+9Q-%A&vJX2Luzo+cznC(Mi;yww+b=-6U{Xc)Vi
z=_WKBn2xauV$6c4Rzq?%-&X<G@Cb&{&*%Tu@4qMMRgeLQ+*hhdRPm8;I&}*Zyc<tO
zxxCg(x+V8@G9Diyu>}z7Y`?J6weWv3&{2Tt!PGMS(<4BICV%|r`*njZkO|G?vZ3oI
z)0P)UYgFazNrMjy=0-Xw&LrDLP~Nj<RPaq5b#^ZA@)a9x?}vYEC6b?^(Hu5DEK3Ye
zJlD3}zif+L`>-|&p@5Y{mRrG#y7w;M>bcSo2ldvwg@3L`!4vfXvc^>@)+_wG2>ma?
zpiA^K?u!yz8@ve0d!MkQa4wh*gd2w;o>(4dU+I{_%^&2jLOSzG1F?trJRk1rX`q_y
zCntEz<sc8EhT``)eE(}=3ANo?W3%jxnM{&OB`Xu4Q_Pg|$sm%FmG)#Up4pzzL{s>H
zk~eG#RsoeeBxZ~Of^sU`Xl7k*DlULKx)t&#h&bgP=l9n9T5Y`GfTciN6Q<y-uc{(n
z5Yhm^M8ya2f7!VHg{jl3P83@$ju@AU8>j2XwGLq@egs_2aXUOtym_qcXTVxQkx_2-
zpBZ%rv4gL0L*x$cvW-y268nw&Dn@Z-sg`JC8N}WAM@tL_R5;y+w~dkoU0p0olR)$a
z4{kMO-qtIMR=+L$=o1u=cJCMiMP#<>VVdkZ{Sn3I=y+5%j$>0gqZ-*e+3Qe|UElBO
zo0*sz$-9Qdk<P(~mjBQ5f&$7H;r#!6jistu4xWpR$qd#LVF~3hu(1Ow(y4gfT{|xI
z{waPfyOxf=>hJNbeYO|0P|&<Ir_4=;kBaj|*v_fS{u}QPN09O?kyNO3G~pqoCn#{E
zkZaT9dRT={h8+!5mboz7j^GKX>w_a!YM%sZczN{JYwA$0*YQ~4x@#TT$7=t=nwh#H
zygG)kXXrrqbpU$?FpMYsSm1G&cH>M)wpPAz#dB3ZhPiYzYy_Wo%ikO2IX+E&26IZl
z=fTx)yK_qXNJKPDjwC#sE)4^ze)L~f%EYI1ko|mNuNSsHdU0o_RLx_usbyrQTg$ss
zS($LDxQ)MJInZC;NyHoKuN9DuPSV(=YfY7G*Rr=}9xhE%_2crV`osVsKHwFs8&2Ao
zL=u(Sh?`VxY{RE|pd#2A>K&taVVu4#z+T0&svBe#s>mjytAbNpVh%BlJSv1PSbKzq
z!?E&vTf#5Ds+N>duO4qwKjIzo*z+i_DEz2hkl>=ojz5Kn&eW^1gR62AP%#k?L<+vz
zH(P2dOtdoBTE2`WmPQS3{@k{ib3ngL4Y#`y?Hazix`wZzN<f)yA?qVj&2Bs^>pw^Z
zJ1tRgbYdG6<uiT5re=?C^O+PHF|CxPlgW!((Jlnn<<UU-?F=aNk^b+{R(8HY(!sQ^
z0SpMUHj0-=1I+Cc8E{l6MTZ*YRhV|?L)YKO+7C*%lXTfsFmtrvr;KH^Qsq*>vYtN#
z%mTd5l3ocabk4CwJbbU_<NDIJf*}hiRL#~(w;+&=`kjMBMhES`<4W=^vt8K)36JJ?
z1x?=WL=2|Q0pxAOs@k6dDZ*vHrqAO|{-ekwu@&Y<V<!Eu=1T}9401s0+<gmlh2VEi
z%04CxG<?AWZ0eyR6NCC2GAr*3mr6NRE({{Il5N>2<S6Uq4T99o35{WZ`0HZphXAR-
zSo_8OJ@h$=$u(f5*2JIxS`{)m7+_MqkeX7ZP*fbKu1zVUa%AIlyKQ)8t~tvS&|Nw2
zbrcF_KkLn!s?^2b<Wj&P*(+@sszLZHR0bA$C9xdt@xtQtRkFA;1kGAj(Sc+XakAG*
z$)=ze@^Ey;ESR_t9uzM|bOTS+!kXCAkTH6X%nKcrlv#=d?^knN!-;_+0&vX2%h{bx
zEN7Arg)`2eGA9C^2UxV_RPbyuDm_?@6O?!o$z@M0Y)7uNI>22sDXF@~g!7G<BF8~6
znOT*&H;6s2lC@>$-Afjgs#>CC0G{iyuc&BhL*@&<wf-xe8T_s!V#$H%S3Z?MJf2&1
z9C|h3Nd0E>N@j${x?5u|wcrWf5;qAP(;%kNmFObO^mz@^3@ycra2(1i@hnLG+RCUF
zltpXkz(s$fu77eVDRH-^=K)zd@-qM7=m&qtCD$`4l`-1}@bgO>#52UIdE!yY-0C7!
zjkV?OmjS188*FnjuUA5p%gCJRiSKSV<loG>KkV&M@hdx~xkzlXE`6DhY;WR9B;@Eb
zAxOWo#5JP&isXfhaCu1#t%Wi{dMZi-T?%yY0mi}j8e4~OrV*mOQzy;T4N0XFtTq4$
z=IyH{F|t^e95^i!gG)orEoL)Bc&EA@XL|oyMv{<2P^8@b$4jOL0k<)6loaWTnK9KI
zi^faTL|1C|AeTvOTTlL&u%9C9?RPJ9|DxYF7j%jsSqVyc=j`s%`4TG6ax}b3W`Nj0
z_x}10T-T`IUowK3ElJN{rOdGMA&YM36a*}v8)Sb+nZdVGP@TwtO)*<q9_bmkc-fXg
z7@vXF(+>j)*$~OHy#1~c&bEgcQ8wm(Rb=TieGog=N|u^jayU*dJYWAJI)W+g)LuIc
z@(_G!enw3TevI5O_;6QBA#cw%!f{HnC+ZEg+Xv=-egZ2PD%}5HBNj;Z)a6j=zDjlz
zmc=>}yxVk>)a|tfg=&>2U}fX2+;UX}F`J}T+p<qgCsSVl_7<O#2}<T38MnvJMqluR
zI9Fa{5hkhaO|g=?n4l;<1;|1Dto`FO!X!7Z7&sez_C<S66*Om(_hZq|YjGmm)j06}
zw=10RE1jo$O!7KWiICiA#J(sS-vyuT8B>-Yp^v4{0OcwbGD{|{lDx!Ai_|KLQKkE}
z(dwm=@usCCOocNf?a!)g*QAYdI<=&EkH!%LeEH8=&Kv4C)Ld!fTc7WNik)rk$*!I6
z5|x_bIMri->%l9J)@%=Jx6L;eEbeE)<cTS46R;t%XNZn^GgyH3JiL3#qGx1uU`6vm
zIaJ5Q)Ty7Q8eezLT~)$WAT@WKHWcO#@|KDXNcQ~8DJ1liXEI<B+!e7B&OfAYr`;)c
zJ?|t1jE05s;aU;SPs;|VZpoB>d3kYj@*}sMPM-FMqoS5hW{ff1zrsHM8>|gv=VtPG
z8bN5VXZCIQv>~XqxbTOdhvG9*+#+qOpKugf;$QGWJBmnVhk;)CNFpf$)bwN5yvZ+D
zynK5o>`&JhR8hT>S-W-j)P)S`7eToxx!$ZovnKuJcONYFvgHe~7CaVL3O<P)s`f=H
zg-&@i=qc!mwr9(bW)@YR{TY%FTmVLW!k#Fo^jGa9!9sR>$SZUCt}I==JDnoZEep4m
zKg|<jG0?7<Vr9Pj4QHWr%psAJrF?<FCIVf|nH_m3gSGVGRDYP>yeIGVEkXEIG1{KQ
z%G3-;`vL!-0paMZOTPWQoofa<wb7fOR=8McP)9@@`}E#&4bZOMvH!SOog7lK5#Fg4
z)bbC_|BGSd41e{b(Je^u5_9m){!26=Zp49r_{n3H>QOy?Z3S43h<9#lyt^R=fgAR8
z&+e}m9Tg;g^5ur1OV0O@E~SB*Ix4%$oWmEEE~aB7Y>XM4FN*I{vBTi)ulSKd97YNj
zAG2Hbr%VtEILyRxL)H<;xbYR0HlF6~4-S^NoZY%}fL}K%eXG4=RS9+NSauvo)g{co
zTJ}0yxm#iIPCudNGst8o+tW?UCtx?$d0tT(c!q0no2PJDTVb$>@=yo*8cxipK(gh>
z)Dl(5C{UlQo$VCS#CoGX@Z?0NEm$<^(A~;`*O4*S4@XRH7{%U#>iD6{XNrmc;+dYg
z^`AkY84W~m$nYRi=2X#GM{-6qH7f@1|C1f~=_c}nlY$(aOUVE}C3g-itdgZyQD~_u
zRC6;?Z0J)hsr@WUvJgb?*W6k{j3Q~hWGeDbE<I|d)_WkJ3rj%?;t;5kO?=^*E4>KL
zob(3fcKu#j{_acO{#~)Ipeg%CTAsyjA!&KfeF5~k<LvkFY6PiNJ))lgP-P8g0h6Ky
z*s3GDXzH2Ue0-`gZ-j+B-HS$^(&-&3K#2cacXTZHS8N}%Yb}Jppaz*`w5iN^S?eLt
z34(^WhbjQno@VE@UoB%dso!Pg7fDfB2dxP|7Y^^8NiWOB7!D*?1gm8N2iKN_Eo0yv
zczb6UbnFk;_`ujED_Jq(lkfH|h?0J#bHeacY$abp%&QeGrUw&Mt?*G^6)VZ*AsVI+
z+Lepu8pxODeCa%xc@=dR)o-2T$uHvzx&4m%c*zW*(m36`bk^U=a*AL6FLxR6FG^C$
zI982Wwe0p0vvu6jzxcX#wvhVz|7h+$kyvmGI(U?`GM27O!MCswLct#C7v-wMx3*3J
z@Du5bh1tZg=2yY5afN6Ue?V91<J|xuJQ={^YWZ)8__Fy#3+{=tCu>ghq83H}oQ&HL
z@~v!Jg`1OFX@uCmCj9AOj8(M`#RkfS)NCmP_FZGw9=OTdyfm-@tDTijbQUS+%37Av
zW3CW;K|$g+9kzN_;fQ|4RRYRf`F)rt_>D~P%bNs0+)t-zm==cI5m8eaije~`b$`cl
zr@~cbZLWpyFZaXy;ljY2GUCyGM%7a2UlDtC2k#$lAJ(#E#mZx%V7cAkmkGM~7}D(B
zsahuqYBw5KSJZLncBz@TxUg+Tn>Tr$ARLmCrRe_*+fgqf>v3+2ls`XK^%-e+Z)W7c
za{(V5LR{w7PaO>hP1f$k!b1Z^rgrH-(|i+4pzotM;{#f33;~-JEpLa>L~kJ+5m~+F
z=*f#rMwFC8xiw{RX#FmUmMhek#9VF8SW1lY#=Xj0x;i%V_AH>r?a-KNwVW?Sn_liV
zjW{lK?YA|1WY#Qgg>R85HEPL>M6=%b=3rg8Gz)5WcqsiF<J+_f?|lUpldsq2g>i^X
z$1Fd>EB<&Y{SOd#-S|hQcj+OUBV7=D9V(L@7#4h5=fT7p05S|sy<TrSnYAx&{xoQY
z_-3j%7iNYN4wdr6-!7Lc1;~XqwAuC~v<mHG9<j3e%OU*SPTVEGp{r*9;ig<7a^2AC
zCT%H?n6*1Ocxw8kYT)~&>O-zu3Xm5Qc8cfse%O@0+YCb&ESC;z`SmzOD|bo`jP38N
zq!{fKRr`O7(xK@NRkATi4kXyM)SOW4w44)2!Fj4$RCsuZti5X?b~@lDd2|sX%L?3$
zqyv6`uZ_xc_xsDMRsHcT-0M5`W31P(m*CVpb|ZFp|B4SNZk53OMPKi>RD?1*8bR6D
zuclIN)s;ae?L;=xut?2iYq<<|@hfIW?EnGjKbJmmJMbVA;!B&H`|N{d&gTg?@wMx^
zd5yRwVsNI1)s4U>OUFQn8ZhhcV3u^(cz5iB`SV)DLki13%%Earl`Lw&y=EG3C07Or
ziXZtG>(*$M6Xj9kop4!CYeRPeCP$&{w3vh-Op0rmpMc2Oh#30DR~SP{rb=EBZA3Rn
zO^pix{~TLa^Rdy0*2?72?CHB;{4MIVO(TVz;e;JT{3?|uDdy@2q7<q0ASYGA!iEPM
ztpk+Q0r(rE6p-0u!j5(9;|%${=*L7^=%yn)49%7*Ljjd4yL>MJs?5~Q`UeH>Of)3T
zFjLp8YRt{!h9gvabW_s&-<^K&L$KrNp@>?TKkSl7<NR;aQoVj`<rIGdR8k|>X)!^x
z@(KaU78{&BI${NWJ7_I!7Zj_Y)x2znO{_M|T0hc>B6xiPBg2a}A)^lRT2&(9r9XG(
zOfOpmVxO%t=|GA%%wK@w-tW_D7Ijk?cnS<TYuTAi+@`2HUfPQmw&^DeVcnDoWdB(u
z1q6?NKTm1#FD^hdHy*`Y6w*U8!LI$=MQ(Y3B=10u;QMVG=uR^yu&;QF62*#a6X?ls
z=FyGCdJOOzCqf+1dX7BTBu2p+s*8hV)kpr|rSG+jR&X$<4=Pkkggl(hp)e*1AO7M4
zdP!Kc6YF$k@zOUQmAJgY^8}KvIj7aH%kz0wI_8y$@wdwS1iY!?&01T*Z(KNSyTE2P
z4BZh61)ID|;+nVjgwgP<7R#X(*So`J7a$)B>)U-K2X9B|I}(~9c1;Ez#)7U=^e>&S
zezaMwkn4%=3m-H8Y~pw2yAE@MN2w%F0ImlUx^csC$VS&9;gwo?@sMhaWGLU$Zp$_j
z5<Qiyve7tVq?_9-T>&ZHEO`_!DzYYPQW+FoDjW^XK&_Q!gilCnD9DJK#oA#Gvre6a
zwz>2c3SiK51s3?dMsf8?_!~TsyCM6)QtMvk*7~OB?$jB67K^Mn5LrAy`zf`Z506Z~
z_R^qw7@+X*Ldb}&WJlfj?pEygXZL>dQm7ve(9&(<No-gXP$bdN%va|=B9ybDX8Ex{
zePWCCAO^TX#e|{75^}HG9PM3ydwfh}M(nJE(4md{rkO*j5gA~VuK2N&d%HQd?z5~}
zWs2qGhS<=p%dE2OtQM`7z@@A+ceFg}C#Wou%>U)KMX`W{5NfpoAGZ2TU>ZPuCKx^L
zEXEhr!R^{MUesqR1(b`bqMomWl`XjXfi9D1c4wLj*#g<)1*4o>bE&~;O>e<*oG^eR
z84=ytLVc|RQBLGGZ|tBCq45K8CR~osu{3g@%Z!JRL`&@piXt>(V+J_1f?unk6(Vo_
zQ7MPJn!juzvf0qy8ND96kaK!%!w)PeyHXUsw~C)gXNp9H{gCNxj1CVDW>LtS08K!$
zzlEawU5{&GJI{x~{eBJw!2@no&X+GeZxundf^fiaQVRptq~2DP>lSRq8F%Aom4gJE
zG0Tfd)iJ-k?|h)U@Xq=nQDY4OZv20kUPzbD1t9DIDjs7N`WJrbPws}*!+N(#%D2ZH
z>VG85)&VE47hUG3HwwPwM7D^so!hWi+qk+`-7L^PL;pdI!Y=OtC?Q(O9QlA<4@Xf<
zE!m*+v|c^ypCDwt1PCP{^2{BCs+E%>>rgF!f8KkEKRK~U)P)xg1s8?1^Pphd&fk~L
zQ4}AF-M#7o$e54wZ=ZK(urZf0$T#*DI?LK<992H}b2GpL@@wlJWp`$kk1oM38}`lc
zuIY|h^mw(x;;_vy{&|^N1lx+%d}?7*X6M0vUl+$Q;Kl=dN%!u*JHc$}@<?Yjo?7g%
zOK&({Tc7>j$oQ(*QN{g&52_%Z+YZ@`j9ad|6Kq)vpe|in4gO!|4qZWG`)oibawko2
z^TvAz7bIM4JSUYySx)>@*p~pX&B_xSw~y5jua9liCc~}gTQyIWIW7oi(q}${Ti#B#
z2!s!al)U~iO52VOv@_@l>#%s;%n-t=sF>@{`Q8Q}Is?^}UT+3_r_LE&ObKJMbWszd
zobi&6^e@fg_Zd|T!5sI_<jk00oS_qV6>lBi4~2=L&_e>UWVX(eN^7jUu5yJQrDU5=
z{YiDovyj}M$ybWpy7@SYal$f4$ct{w^fF;fy!)zXv;+@Dr`R7<2NH<)K?{#^27k)=
zc$wF~p~pF0xKsTj`3KiL44O=bv-uIeXF3_vnU7WR^;lP*r<x`<l;oR}7gQFrs;|II
zE#SC@yYBMdl+1nKI9{kJGwFips37Tr)6g;BS8*I@G=9C74yS^=iu*Ao9u>A;7@8+`
z)UKq;{{yLSmJ|qilN|KPPLZtmrYA9zrj#+rj7G04WZ_Q(frxWgL{T6|8BHKrjV((v
zsUyO0nK>jvVfjnqG;%Y{pai+#xV#A6H=2*&0JBZMwCkWiUxw;}5#=WmWRoW|PqkFF
zobf0#=tM~imqH3nfby@uJA`YeKP+$oF6g>2Y6jdfuGLbL2m8A^lTC&`+zKiwooIHc
zlt@wmP2|+dsA4A5e}4otx5^MH062iaObd)OlxB(VMi`?U-*b)jF06~=Q_J#=!!skc
zbuCiNJ_7(<zeI(hf4J4Q9HB1BkkMUaSyDpjp8(`G*<_W2yT29TBfN!_H)UT6%Xxop
zb1ieD4$AaVVQ;D`KHiG1sT|y4r&B}@pMTi$EG_-&ci(&@m|kTsrSg4BRa5(T&fu&D
zx%OObgO(2B6J;HV<UHEzFZekq42<$F?2AHj@FR)@WLMiEPsBwOyO7Y;TEEOU0InVZ
zmcBvZK)WOOgjq%Fdn!V{|6v9ii<Y+UsqZS`q2p*b`76d<w;b%XTf0iCIwrlq1}#ZZ
z(Nl4})7lIF{dee|RS3vz=$wj}tbDzD1Z63-?&~B)5hy~_CsFHSWp_Z%uQ$+4^-*TM
z9doz$m^efaQg*shy2Ye;#*PWEZ&`YX8(3mw84;?LIamwS7Z@X&jqlQ|lhiPByYRqL
zl@3tGF><$fDfMO|I(H`~%xIh7<+_*qGJ4DeE5$}z1TR}=j-iswXrj-^87R!a1LYXN
zYp-iiP$|@6d{7=7p%GkFQC^4?;yNWMM8F--=pZd?N2RRAu-M+kQs2*<_Q-jD3B9M8
zhD7t*($;^)3#hlQqQ5&ccIBRuG>A^4?t@14AK?Zm&y!KJE~SF9sG<J&BHNBo!EP_i
zZGD|%Rq1QT2k&_-;-f6BCFc5Gt~iccRG!6Wq*T5yxL0!oAO8%BhOFck`^govaMO?q
z3)v<>(7Yzj7`Qv`9G)^`{0=#6%eIW2xJvV!qYoG4UV)|1AnC>l&{A|ZNjqHh;Qz@c
z6_jeRCg)5e3MGO3R~Gt|*+4J3AssV(^+>)Xsq6xCrEGDiOP-PkZ+=KBbN~j`k`xTc
zk@L!Gofe+aqVYfaiYvO<smqD}M9pt$*y9S@e1Ka&Z{CU~+6zKp9d}p-uQBx}J};fR
ztAwwpwfQ4_-Z+{>JPs&=(9e7KYlkx}{Oy`?CF?lg>C%y5T~SyB5|xy<tV>M;YbXG*
zqkLaZ8uLSmBh4)`;@R-~pSvJH!YxQ}hM}AT;<LKeodT*J3aim1ny1w_#(WJiE5p3J
zE6`}`Tk?t#6%h6IuRjJL4Bm^W4pMJl&lf>j8$mfI9OC*40XiZ@cEYp;ctA1eBDdfJ
zjrjmRGQ#g{At&R3=DESQVl%NtBq})|<eRX$y2bfoig^AblXPcN>?H>nZZaIVeG9xL
z%@TbZV^RG0Z)?3wKbwidu2%58^&>H*ppnvP;<7mVxbH_bs>%ydlLBq-h)`MC7*}<_
zJE1*v#jlC#@V8$!E8m=5<;;QFNyDGK?blvE?@3Cx&03g3I-4<PnR>jU@7=o=X1wD7
zV_Wm777W$FF!OR_0m1g|Kh`Dz7#+KOJwq|*%Hc@ajdOxHriiz-U>;o;*&NjW*L2>J
z+?yW0g`|35{~6C^FdVl-5FO5QbXXZ<0HCo4QnL)v_@Pu+?gx#g%$r<9WqXKz^04_A
z73sl2^}UUM_?nPc6H_i@9%Jiz32s#<w<l)0L3P&oL^6UOF~n<?a&J=TKvY`m7bJAr
zj|@O~qPE*O<4K_4p_?5CT#2WfBpxgEi9La>>}~B~C!IQuxwJFG5OR6}UIipS#vw##
zOm-I00!3hHCpPm}#*2q=?ZvcLQEX3e@|nojhRAaFsYX}fVAcyHjQls$gk|CmdYXoF
zF^w?`P+IZ{1o(t5UKVMCwuze>7plGt?zEV0O{O1eh9TrW&O(ptd@SPvD|JIL1Wb&x
zekuCc#|&hO=2q~nT+-Xn+ti2`yMsqiiUQ_`+Zjz7=Fy-AsgNO5qt}Hx^|lBt*xq$G
ztCEqW`t&7p@B&guvI^=LhUYWWunKjdea*3}eMiM(SaCnnS6KxVR~GHgvOB(7RqxYq
z9#SA1c&7!I{l{o>g_=8*j$9~>3&@pOh@!T5el5g|p9FDzU4OGBDn8NrIji?|OWiL)
zso~U#J90Xg;QmfC3yM9TK|3Aig*u<O8EMtmxi+cgTfJIC5lM;MdS$v7E#a?w2!<y8
zCFhedrbou49huW%q?1)I@DAWGE%Ae<Y9-J%qiw37b@FJ>_=3fcF|ewm8TPNXrt6Rr
zU*tJPX>2E{WZ~RKMRdwOHP)M{_2fLcTy_w~rcXo@(_*3=B@v$+Vu>svPGY8=JlU@y
zuY&56erpn#)ohu#iRBC;`7SCwU!$a!l#LS+nTFoL=e%Se3WGLnDQ{s`BU=jrTMg(z
zodNU{jtQbXD<wdDhZ-d;cl@8C*^)H05v~Goa6JHQlRe^HSV0{p6iK<?0C&mS-AK_^
zSjGBjg-3~3ec7&6WBD-<%3qjE(KQ#Mj2qxUGn8H(Cl<+UhzonN-V0iEFBhi2bAIPw
z9iIqk=>*+bez}T>BK<|_6Sa>C6tso@szkU^o64O^>cP1~rCm<`!~P3fecUp{U8v4Z
zvy$#P2WMkU!j2mxc1(jEhR%w50SpiAr4n^d6|@^AxZ7qC+%zf>s4<3X!Ooj7&Th3D
z9hvtpsqGsX$$}O8NE*_dXz8H$@ZlLqWsMbsmSKl7-#?f!IP?z30BkJz6BD-C|3?}!
z$7n>HJ(ctWFeNbi>6-$cqQ5H7b8MF$7Vjhr01+`VBEShKUt{OJMcYLz?){LxdU`Io
zO&px<pQ*Xg53gq==wh*^SleXh!<}Chtg%fzQ+i#3y1D{f*?-Cyk)+fx(Y`>Dl$Jw<
z|D-GiQ*$7&a{U4`IHOfrt)d4U9pHy4SC``pgc+fw`rSt>(HK9s&@E)sr8rb~Rb=!7
zfnVRZG!#yXijQ!7S@bT<5@`^9BM6pYXFhL7P;MV}!_Ax$OB}WlgXAsKmpl<p2}P}0
zw4Fgpz;0!yORyO?)D*5tAw1G%t4oW!Bx<AOyXweOjOBwCBTLu857rGNR#+`mhSgD*
z8z3BLySLFom%Yve0L@t7{d#n?A7J4E_KDuv3o1f23bZVe8cT6XdO^frz`wmn4-(Cr
zAQ8_(#qag2xA0D97`G5=4uSJC`-%Q0rwZBdUx`$uNw@b;E?F-4)w&HcjO$2X#whSz
z5MfI=6g{Z=jve;-cj-b1WvbyC7RX=}a8;#;Iv)i$_k=Wj4uxlR+0@hyfD6(Z-jo3F
zVhGFraoC`xEphFlj<n;Ll1YawaQDvQl+G@eRNwLaqCZQbq~enwSv4rEw;GV@{5r-j
zeg12m`BUI2c41IjwoHI5Ik7?+^^*`TD?ESWzyTyZX8Mi1eA8hv*Zl2{(w20<oOHra
z99_H;+f;vg-`E~Y6!I^yv%Xjl9$)i2EO*68bJ5~Cv|DKjpd+{(us}XC>>BE#G=%*s
zJ$BwRo|%a|*I&KFN|XR+T(GU<*eTe9&W1gAd_Zd!z*0%Y0%>}UIjkz1VW<*H>5suh
zq?&f<mb^N?9|1N&G%%TK{c(?+^>ssr0j!jsyj-iEm7YZ4gP~|EfJ!esPUpG99-z3r
zCHIn+A)x<?bE!l@Kx6Buu6h@<uMjgs8lH*6ZJQX^#z8!BJ^ubyDM2z6&A{K)fRWBT
zn#jf$6MsQm$3XhQ^F>lAxIQ3~)}04|1A4Ains}9KYv0kL-67+Vt(fp=sxV$DZpVV&
z=8E`q$1`sHmNmNx4y{Jl4JIvLRXtp&;Aq%-h$h`!e%^V=!5^mc2nCf^^fc=nXBv)H
zIJK&kVbY{k1d;w4!$0U&{@*eBw^%5WRn<n0LRRBC+RgE!NYG>ASJmlGIMnq<8gmW7
zFSYpD>q`!5x!VySdOv@XQ_~dALc*D}_NiUm+)own<AkJB+6xgS;&W|&+waotV$d=s
znjNbA=kxqR!Ky@euT24fDVqN_=s^(r8?mPpq+lQSlijrSFU|Se78<3=QuK5&Ge`jm
zG&jnZD6!nhmJYD6`whE2ZV|fAcG@Q|`hAXXybBOZi6in5k}MCLBW@zblTWSV1-@~0
zz=-Hp(C^Y}kxte;I7l_udT!qk#uk2~RtBDzJ{~Y^1~r1xwy$*D7nlox5&I8Ok(cId
zvj=J^Y|li^Ub>^DI}?tK_&R^>x~ZM^>tj`y3U*m`bVM3T{$obD;Q>}R%K?~#HCb=b
z-*1Wu>t|7-m}rxPfT^G>&{}ORuVZdbD7^%QPEm+#|4>QVT<vwA7^4X@P>)G!c?YEF
z=Ys1Y`lQ(VMF=H+4|35Eydu0$_>_E>B0?J#LqysG=b0k<2*MF^$E7}sIu_9F1ajhP
z=lkY_)&l8JM~kvamp2sN6B$F?Zf$G#Rdg~TzJ&5#K&o)krI=ck3sBc}Z48)!Vxk3c
z|CO}`XOGUtH|Bg4co1C28WgtS@H8qPB=GNSc$1J5i^Fn*cslrj*7f~6_1b~001XW2
z)U7*9d4Kvus9~=h@wO6B6$CcyP^|}qT9odyi^XiSBe_N&!$eo5Zrb6_g8>i35tQ}%
zqg2-}tk*xc8Z;byrzM%4a*6OYP36;WliVJNPb*L%0ul^DW5bbP_-e5bN<cmOU=;Je
zL~fnkdVlL!N_%7rFmjdW9Pk4%hNyz7A2z*oUMcl0v(GTiQNIZZZ6BJYbCMxLKZ8Pq
z;^ihER4Y9Z4YD(p-!=(`AOU0_(b8CW9iy86oM*8rA;2|NL27bXam*ozN*qbp+Uz>Q
z^k^fWhLNG34e2uk1P&oClX5PjTQ=fmiI$_>g>CH^WKxk~_z%*SXk2C_dNI#OsKO7V
zs!4+N)Ct_!;UE(}c7`#F(xxd#PrN+bxx`n8#G=ebRR&|FH+AqD({^fbWkV;HXNjW{
z_+o2V;sOHsOg56jFO*`BR>nLY9u71DHTCD4(^YB}ksvCnJbEbNCLpJ&p_HT(({lhQ
zRbrVnQU)N&XxMEw!i63kNE%}3<&F%WNo+kIS>~c6nCaba_rt(E=(7-J<d}ddVmpqs
z#6O7yuB8|*TnMR^`T*y0V2k&>8+w3=?1Q>_3w#~?_T(rPKM#i(WRyE7i0*xcx1$>+
z#F(jDs{SpvELfqA9;?K}vJb4!etk0uhru^JvV_St!#T+KQDz=eCn^kGe5tGH6nXvM
zSaMXX<bfqvXdE6!6ojmlhIw}&Q&PPK>Z5o<S<#Scto-qSK(70uy^Dw*wuSUhqo!{R
z!)tXeMO=mU4VkEe+i61EZ)w@f2jFFO<Qgv+RSp6ESxWE6w3B(ZUU|qF3OSuzGl6e9
zh=|CIS|)hvYo$}nouT*0#HM}-_pxL*2y^@LS+1U;woKpP(!-KGNVoEzwErF~EDn_i
z+q;sGjEQSfqksHmWu&COSRGYu<cPLPtCGDeta&`S5_0~!!OCc8`vUa7?)uhZR58=C
zl~GgH#aH;B?Q5&`ye&xX&})WPT^aSDDaD?>cCZMO#uk3!tS_wyFes(|YeP{40lX>h
ze7}3}oYX$Z`B2SU5u&7O_-x6qQ7$IBe=YYX4GeZ;l76<z2H&`t4QZY=A-JDWE9yTO
zP@X38L5!K@V}D1q?!JLX+$}EckQ-&4<^e^W$D`3l|D`PwtA<oyB}@c-xV&KcO_g1p
zN|asCDOJ<YrLbn;XsDPP_^0Lr{9SJ%Zw};?9X&OLP3vC+9#%&`5(a?Z{yvya3bFQl
zR8)No%{pw5U*!`r^qa@5X{w_8e#HyY8DjE~A11j!B`J%g1P*wZwAd?HclkYL;xioh
zCVKy}I5VE=qS!wCC5`fO!b>{9O+o=rFtl?z4~cM+0--bzitQemYuta7GWNK3jB%{K
z_!2qvqf(dP#u&M)#>25U-A4Ia?P>kJ;i1hJcdRLGahM*{)4w_d|I$!%&thr=me!Zx
z@M6B#RDgoRq?!+jh~A5C-Digep&tfH=p5K>gLvS*bTUOXEwqVv=QPswr6?RZzH1t=
z6}22(5>bznmQcqs^8<a}$ig_6!pzl2_`MtxcXfSW9iG_a0-uq6Q8eEHgh@~QYp6(R
z>+dGes+KcN8lDnqtc{Pgm!ZUs`<$)6p3W)8g4%G4$k_C2J-+|V!&4j)hpmV$92O|9
zmlUeo7z*dK_B_x20IlGVu-kyoF7NqPL>qRJ9L!IJHO{;Ugxv@s<%u3wI)$9EGoo>_
z*B)F&;R}qDP&+Ul;B6fOy!Gu`<EAuGT80QWo>5x|(6fH>XQAPLK@5v&g)^LeW1e<W
zj}KbQ`+7ZJgGKSP7v!z{>RHCl0mQSI=4oQ2lH1#az2Oy!KS)b#aV~yts>iT0GWaE}
zU1YEz87u?iBL?PWg45d*Y*5z-jrz`+$6UsVt-xc@@zxEdT1XB8z7*Q;+w{^vDPDN?
z<*Cb^4Dwuxw>#1IY|bRzt@Fd+E+4?a;)draE8j`QPZO&$48ON;sw{R%>UY$f<t%rI
z`%lldW6Fz{u<-5ETRDos>rmf%oQnP>%#jesk>6kqa2-49YD+;Pj6U<4s~aph`AW2#
z=B`sGX0P9!?u!KZhVjs*a_v#)>Kx(xXzI-fow~Oyf<jI<<Qb%m&E&h7=OsQ3!I+u}
zoWzcNGpJ7$X!@K$Ks<R2fOKWnsAp11qcCyCP4OeX9sd}w+H#`Ol`;BQidLbm(hKtj
zsKH6}vT^|fR0l;L|NO+P1lfUKFX`x#ZVHjo?6CdZp*k>9zm^iKr8PU{cPl6v=)3zN
z!G13H8a<iTnv%;bYrNNiM$jy!vRghC(5ncPhX|2$i4tM;J3}}2HLN1iF2j8)CvGMK
zMs<_Q&R(HZx<U<B8)+<U3I4HLPJm$jYW&`gmsCh3iiN|^Pct@|AWE-sVHQO~4H4$^
zni^99fnj;^;meXNon5{ohnY%;@nKzcjc=PqI}bns3~BjONO^OKTes`jX$GR<QpZkx
zOECpjL1a)JL;LTcxf#D6tx^P~5BZ`h4+;9wN9@XmmpcvgU}?BXfsG=X>|X84w)$h8
z;nnn8fdA*{O+MJHrDhn_XF9!zb?vE6hSUUy=7VGd5glE#d^hD$l@#-e5m%zO!b#Fa
z^E1NwGB?$zvdY;b;Ct*2y`vYtbt_a6P$M;KW61wT6jS3$Al5J{*;dDB`TV};VRkdC
z8TjC{@?xt+#C5r~%_-3*g5B5FU{N1VxBkGXXkQV<7zoFsIz-evi?>z7wtBI?_V6gA
zODF9ve@L8}OJc%cts1v<Wa~nKcO_7fVyo<7%I>P^w+`$5c!w!*u5PKw-30xKI?fLi
z%cOs4X|ySOSxzH?tY@Q^TM75(*DxXbjxsR*33&2M{K5n=B~OWbrJHmIBBIB1P}QX6
z)qtFO0AIa@Bd?c?<fq37U~o}QAs0*>B-CL&!B%0tjmB$pNC<+=)5@lw+eDh?-ja%j
zhKBuOKY3E$QWDGj76$S5s>yMYy%hOYtdq$If+iLX%z*dckQQI>1sMAyNjdXhIe%k5
zwz>W1$;!_q+o03OCfqDX;+#neISOY|pp0!unjLQW0k@GHW_`m^*4WOzB4EySm%8F>
zZVX#%9!&|Z-i0X;r2DGCdkMr6bVS3L$jy@nFeA>Pi=)SvybBOGc5RQbaCTz-n;2PJ
zMMBKaWm-iA2CwvloNAUsz5q0A?C>!w_KPEthWkvg%Uk<_;sZ)foC)6&R<{+jnI7Gj
zCHZrgCRguD{RG$nyeZJXogERfhIjjU9s94XW*Sco|F<@ufud%pmGvPgn~0_4WTHoc
z6ecxB1afW^5-tB!nHJHna*K86{{>QyXO7er9C-qCJJLECm;sI>W(e6qbypn=eh5<^
zud_q>C)r>w(*Hv%2Dh2kX5}nJE^5|;zE6KU+H{aKEt^2p?o{6~v)3ANXbuML_`cLF
zV5X)s_^anaD*B1_^q|fRzf(=!Hk|Sg9?zmra6HEp;_^2WJQZr+C7o`Wf@pI?WKk^!
zmp&|}eDjsjeNU_997q$J5q`TcdrW-PfEq5ku+GqQW)H|pCh=cm7)XreIvi#W;gR`A
z$bJ8)?QgQF-n?(g5(k$5A%h!)gG`wo=RVdZ97-Wn31S^SG4Y1iN0<IuOLUSP{i^cF
z@`sL@xJ1+9(W?}e*hWLHm*S9fi57h|;pUi6>Kfrg)6toZ1Ug+nD~fxTv-on5flp{R
znce0vs8PoTGKNtpA3a3M>VBz~25`Y4yEUfA;Gy3|<nS^Pj`kdf+g<YN5J+5&DQ262
zh660ZW<(@ke1SW&&WExG_mn!RCC0x^>D3gEHn`W4d`W5v-y{kQ_~#tzQ!imcBZ!J3
zTaZwE!m;pCX9=gujvqd6MA8g!FNt4e*4$E?w(`01n8_6Y#Kq<#bL9vZr1N1Kz^y6b
zY{F)S?APSFpN@D@Br!m<$9w^yFg5Tu`7g*1p@%Vp<|m@w6iso9tx<Ji_1&_~c&4;R
zMw((HAOXz@9M@pnP31Dz-7J-E@OF5%xr55GblbFa2~2r_Ja`ot)!owiL4zhnQC0l5
zC1zE{0q_XfxIe{0D@M^3kEjMlq*F`lAw_-p_k|PY0%a4!aS$EEHtZ2eKL3yw^ouz4
zJyU$t6HP8oAxpQ4*M2HD$66$Ll$r*&H=&zbIpZ}LA*a;ae7sq+PBuo%`2>;JyqXPI
zxc}C#;9ByWHai<x<9w@ufR=bwl97&{!ZPrWr;`P_ld`9kQs#AJivUpe67du|mTyJn
zgan8l*6#rzUw8>%GPCcHCSct}vq8Tl<_yf+7C|KAsIwsa-HQ_*sA;Qmhz&X9>7IY8
zH|{nPvW=?kuyl`M@%%TfvsAY+#YbzpYLK8Nk&+1kDJ2<{Y<lR`lh+~-NDeX3kPW=)
zB^y7j09JdPsD&DJ2)N}6{hC4I)ZTLy!!ptj>UTOP4{Jqr!HKXe_uF@}DvWWzVZ*?v
zwrJdlN_2avzp1|@;v)1b^0md#{U?A;qXyx(ROv_~Vs=hI^_NHCm)s<Jhf_$8oVMr6
zz?Yh|sVBljQjJ1yyF~T7o((?=)cfN+L0St)g>dKkUFe9KkOaj@cj28_>Mg3|yH?H%
z&4zOM9zm^|#x)^AX6msh<2i{B!j&mnD@+LJKU-IQZ>A|>pm2U`9tWzAb=3;Dzi+KC
zUX+E0`MmE(?+$|K5hh{NRD8rp(9%ZTf=EzQqM5O<(KUSr92AhPV8Jull`C-f2C5ST
z;m}Rm&g;5$p?zG%M;2GNA+AJ??Ijn_Z0%%56;D)Sb6PQAD%H68(xgnfQl5d5=!_WR
z+b$=WQXUicIog4LZ6}YCmWo_2FpUx>DJ^+@%a$V;h!lc>p+u6y@%5YWRhzpz;n?LO
zpC5%sK^f`5&{^^1T)I%@yA#0hFTc5Aqqky)M7~&Dz<trVeC5XB`7Q<`ewTPB+5^uI
zvFX)nn(f~#V_6A75=}m&>ty|S`!J9>5+l8^?=8{0Ciy=g9kv^!!MI`<NTM?-tOYje
zsmphbT8-@D)(G-|E)RZLhu4mpX;J?@fvtQzh3~M=L0o3jjhRd1)>e2^?E45ra5E!c
zgGEsSU&pt_3_JupnrUSncp>pEVf^}kUpc)yw<LkZ_&XR2jT%Z`QLCbeLV(5p&Lxur
zlQYDOPlVdXj|OKtR?^wT`DP|rD(@>#g*~e>7JU#BM{ZZ$(V=qlM8b3GSj7}_-7oH{
zR0@V2-GKJ(mq=*JLz8AcrOpvj?!KVFRy@^5V^VX8dG%3<)N>@{;Vvep>Z+B?kXZ<d
zWDwh0apq^NRt)BVg)otXvS-k*&EZ*X-*2(yyrS#Lna|wkkAe=()x@uf?@%w_r^&3(
z8BG?>G<u{$j5;i$epU3Fnu69*$uTo)EHCWy>D-!b$B_ZijcJrbe`&jz85^1pz6Tll
zLcdx?w~LMhfd07v-`iwn(lztPS-WLJm@*7=rlFi_;X^v9=LlM=H4CXBy%qyi5Cx1@
zi!I+5?ufNhsuQ-gc9MMb#nC#??1FgKyQVPEd0tG>Z;klhKpNK4PuUbn1%cwuLG?iU
zg)p5U)}TX}0HDp$F~#UL{cDt$QOXKWHja!0KnRkF2%(V|58kNvnkqvv1ZR;M^w0Px
zuN2QDto$+_(UP|5cn02=bj|t>XXL5=#AVplRaREGIy+e_9X$Nt=>oQ(iFOLZ>XQ8F
zhtIxRbkaiUYiDxe0*!(dTM1*b9z{~0D(GuA{_D2jpyVNR11ot(MP9)eeb&%C+oPiP
z;P;<c9J^NEPnkR5K+?4;HN<Z^&Auyuz*t^UQbyTdvWXLcTrS`|z$KoJ2{)yLlIq9k
zl@-3XrEAZ)v20j{kp{L)oRit~m=2P)Th8d>$y?5Kr-uJ4;%D<P&Nr~Ei`BFp)#-~W
zy*SbNM6Y&tlSfP}CFZ0<RKB1`n}hz;*<ymy<a1#E-Kxh8T<LflIct*$mC^wn-EJ+<
z2Peb@7sWw@p;#$m$JtfLJ!DVXIzsABHwgmm35N@n4T*~ORfr|WJ)2LRQLj|Zi0z?A
z;6@TN*C&N*AJx!F+#B<gCO^eyoX+i_yUlnwE#HOZHaJbyr!D~%-b;0OinJ{i&aqAK
zsUqrK`kvKPs%T`m&&c%+Un9zvqZvCrUjiuN4%nh2!obB}&{ErJ*rnXWlKc?80aAU!
z);)mBzir$GN|C{}=!v-HHKm~w(q$DR7C`3LL9|{!<+6vjls`b#tkxf#Ta@sb%uaeT
zY!E=OkIYCPXv8CbP>s~`fZYP0?>|hy?q4`KOQ0;O7n;69?f3-M!<3#YpYPa37>fI^
zA~5uoRN<CFEU80(TmFVLh4|{aOHaUeZfxZnq_X#(h|w%ke}@*o#hfJ4uSQNk8;W6U
znC;gOlP>40tnD5p6PR#btzw7ryG`F_FFdXJY2%0^7O?2Ipl|6|=)JXLb8DV7v!q|^
zsaq|A1<#~;V*bM9l6-j6st45cojXloQh}bHO6_}n=t+N!cAx?>cEzGuy%zhQ03i{1
zuTHvN>r@eUenCH7q&s2Na2G*4-vmKqn#q$i<I)KGc#j#GUgOyESPw&js;7%=Y;(Ha
ziq+dCH)rSAkvm2uo5hF9Ev4SoNgVA~7)0E;tg3giW=&q78R<Vak%0O!F((|C{z1u_
zy}l7?PrKlp^amIXNWWgL<^!^zL4J&Guy8-_9-atsa(qC{a@{CErThLL8NBUoI);<4
zM<NboSN?J-P9YM!P$=~&tipTflW$+_iEP?2s?~!~$B5L+jBu#+OF0#Qaz8*s>Y6JK
z(r%=gsH6TgF*g08%mIAZ5T2LI0JMPF3C#abuJlt3`ySRQZZHt40C5>cSkrPeQST3t
zT+Fp6Q8m#lE|Fj`o>!iOtV9#RY341FhV?W~KvC>s-VNZW>%e4%Z|9l=@(C<e3W8U$
z%Jzjfr$G(hr25H?Y9bCII5?e>OlQ$k$R#QuaS0d_x_L_fWJY%3Tk!C)<1sxL*#UeZ
zSD18j>LYterO9pZL3x0CK?_m7t@YWfE?xQm{0|(E;1Ee&Z<3UXYLQA%d8I(@v-}~0
z5{oUDWc^429SnXw6rUTP5=R}(D+bh8d}TK}Z*u_BeLxcdXb<}WL=;F*)4z4rTfb&&
zFex6GsB||Jp0OAJuIb4wKMQ-X`CygC^ZjC!zC>U?J~7~&z%{mG#A#!a$X{6dvw^}4
z-0>lSa38RpCws~!_FgY;4zdj1$pVZJ*xDX8Y0}&7%utxEkTXu1nciWJit<<uA2QwP
z2qNY_<v=a>*m-d*YYHr@SnnUI{9=lOM2kSV*z0J~)m(1x7oBWUPN_h8E){u0b`9!n
zHg(DZalhD&toz`aUH_FA_#%%QTBy`&9gNe%CjNF-!rZRz+$!YXb^pnko8MSWG!Z~d
zBe2@h?3J;q2!qzuR)Wt7kcbKEpL%p%xhK-k`<TWbWFly4JhYqQgD4Kno4oeALci(B
zp8|Hf@G%i^%k-m!dF0r*7<?2Q)4)(BBY_sr<p}z?K3v!kfDKQz(!l8u^!mUBK*uFz
zIJOwFs$W3|g>(#fE>$iE8G|i6Xsurijc8m`;8D!MsD!ffOZdm6=Z<BCP+)R3<w^Wl
zDbs}3TrzmcbZD$wY+J23gqaVKLnRSJK_v0Vd-TWjQm^(Q{7)^hJR)Ma7?1JdKu?my
zg{v(-tLS0eRUj_UQ%lDyB-+fAgF1X=z?a@Rfrz=k+6D6c&Dyu3#(d}W=r^VVkQ4w~
z%k;+#6DUP&3^s&iY#V1El|r-pK=+XZ8$XLE;oOnRj;pQsjs>dMItOMjo=?T2w*@>{
z0%;qp01nMUhAhY@$s3VWSZ;}l^$NWhsc_oY98}?{dt{cYxNEdyXedZw89doh0C~xG
z-ID%2)@8>8F)z|8dAzOwiVOP$YkndLKcyMjTkT&>D@3=I7!72bu8?S)J)deXJ5H<)
z1&xwP%N0L=26d5~Ly@Kcr|`es=CwNQfO#EJG)>;>gNTeK2^I*FAdK9j5SAmtmwY;0
zVTbKPlAy@s;+f3W%soZs#sY0EtR^WYS4<Bi5TZ11z`kKJ@r+6>qf5R2tTuuISV6|R
z2c<JbonlWN><nT%Sz%sTec&?XVIoUNiBE9U&d>qTp4natNJImaHcSTqqO@gj`STZJ
zh2+x4+Q5GMYHHKo#VI7fT9hz3B0EL|%IZsMZRPpK{6<<v@9R~D`R~a|e_s|>of3IV
zSU36guQGY%L{CHJq|c*96qYbn(<3+RuCYn#@A+9Hn0vGazVb)RQQh@NtR|Ez1Li@7
zr=wp(E)&#DSO*47cKqW;F!+4b2s@npxeZV*-BOX93yy3%aW)$toF!C_C`|&RjlQ8Q
z3;1=iEi<g(bxTwpGmEByP2=ehm-CxmW*6{#8<!#fg6do$n}fG<uP`ZkfJ{!@l+Yun
zz^!<Qwi`a>RwQGo7Zu%Jhq1Aex`f#lXR&)e#pu>A=`7}Qa0uQ|X9kn*I_`?)Tgox&
z2A&~c<5l@qL5*QRmP)_r{|5QPn~Mo6(kpe61~8Wt`Z~Z0i#HD%?V*PRE~cf*fsq^^
zveh5Vd%$RLEZs0<H}2htGgctSq%Q%8c!X7zc!;N{9%6rWF}fP(As}89<Cc*B4b_&>
z6PMJJvL6Yo2O!Set%lmI#9=BbK0xd5&m&5D(MH>c%_#dfQE=3voa?n#suWj2VeWM;
zOX&9qALT&aKO7i_Yrs*%T&Adld9D*PkN?I`@hr_ju+C&VsG)8R`r3t4oH(1l^}BF*
zfrVr9xyp`Cr)FqLepcP02$E{<yd`C&)EN?hRt=Vxtjp8XKA!(xieXClpFulLU6-2C
z9XR_64?<=pY7}^ut|eo9z+*bx{*uVQ3}OGa+R(86QZ4}Ac|yGBazV$yiYvlyEBMtk
zV)1?K%D1N-hI@l)(PG1TAt<59N9rn|A*jy0k**9=i?5dRZH+I+WG&7~4ce4OEr??X
zRkVHl<36mj)QquEuz$3&i0qi4G`8EQB@Tk-Z<OMeLb7J3J=DdhYmcfrdrXLf<vG}}
za4E6}^ll7A2R})WgVFxu?QC6069s3J@jO6I(jgEj^@*CC_8JS&#I8fq34w@45%O97
z+D_>Vyaqlru%4b6I2C)AxSkp81`?&p9mll5;BaEF*L}>VOgs9Ok^0p87c^<2;!f-k
za7$*CDE5Zb7edCh=tf3QI+8Yb14*M#rIWYM>(-Zs?V_FGXRn2gAO_FH>R@+VFBrf1
zg6cFgpu5_bRQR`(9J5XK-#T3<s;V7~sQ!sltXD>bDNsj3UBdv1j)_df%-!cJO|~OS
z9)c2%rATDYZi-Qr^c<}yK9OR^6w*VL;s4so!)72g^aJD;JR_e|2r-Mkc|>C!M!jy6
zrsg%SCkauVt*^3@gGkw72qRnrtN=o7KNs<$FlT_}?jSsdgE39aYVdO+>xwm<4&b_~
zlezRy2Mw<qFF$t7@)KR-sq;GimzW_gk2_gI4I3~;BBg{JrE_fUm_A$kk9PVB1_jGe
z3MpuV8fX=gXv1tpTKF)CKF5XlBuUzR$s1UXxD;NoS14%NY58thzW^T+epSwLywwFl
zr)KCrA9&=urbn-8P5yZ&^ACz`+Lff|G6`Y0boI}eYPgA8p1sbRB~T(&!(R;_$eM60
zZ{(gVXC=~V47g1kG74ak-sGd~EgCz?rnQtkdQlo;lnGkFbe8X?znYDk@QpRgZa#7V
zh5%ITu`mgR`Y|aSH4v!<XZoe)jJ#ysJqrfAX9J|UAQQ_?<L0dNg+ijn*9<jxYv)-!
ztj8?$fi=OK{I<@h^?;>><EZaIXARtwDoJ2&RNEw)rbQ{jDVEUDay~JaD71Q!nlfsO
zFogQf$q3G&fMJ~gjR7$POjaCjx91FpfDX4#)XXHLPCMt-{HQP4lO$Fk>9QnM@_{j4
z8>@216NT_@t7$e6HV%U|U-?I;WT({I_1j8jvy$$Q)D-EC?Ihs5?0mvqv~LcH(@-cC
z0W#%#tVSaubt6>mxr(o2jDgZZ9bGfi`^#PdIyYOiF$=}Bpw$OoE8VXH!jbwO>=l=Y
z&*9I~SMEz4dx<QMjrq1M*s8wn$P++&TDIVJ$ViNaTaFOp7ih^$0K?J)13p!oBoT$&
z3w7b8wm$eHHd#yA=nxfWPh{kAE&6bx-C`((ID_~XDLz1I;oWTXD>31mVhn7~ah#W{
z0dp`HYw@vZF?<{OlJ@Snr^HEfzGkuKM1?7`I4qP`KYE{Ij0*27c(vV#R9kbnV2Z2u
zX=(qG=SBsx&IRRO5kGq3=EwH9nLu5|QliX5!By~x$D-HQ`zJQ@o|^x<&k?iEhc*El
za(|6QF5Y@e5W!L*-Y5)dB(oxLdDetXe#fhJ1+t9-6<nzuGEiN7Ll<zO48x0qZ2aCV
zsOaZRp`$hHg2j&le0k2(Fp5yfraD+k(3i4?he9e!Jo|J4vVq;n!YrY^(^j@Nk%BRZ
z1bToE6~b<3Wj=TUBuUMu?&PulbfTNo;;^y;^)u#poNU-T>dp2@2y&PxShkCFVE)?s
zX{AQtujfMq*Dq^Nzu2k!Bq=d694veuHFQHYZ$x&wKuA61g@IInRh-AZ$>49lS+CwW
zGI;`NjgBi=Oc_=brltV+;MRi1H9g+@se{2Mtw}WPoqJmM6^B6NeTjf@4#nj#tPH|X
zibWMIJ9pO`TM;TRf@%WwKx&Pw!NwncwZF&#<{wdEbfEWP_OkQzQnT>Rmc3yXiO3Si
zoj)mHFQ}U?H43&N#z4JMb4$70`uu!F%W+rTY9+6g++u3aq{OUuwc3)w5EawJV&x7f
z<v6|=k(oOEp70>iU8{Nf(VQ~8_YB<9*ma?jENy%OvVMMue03Fwi^;lKrkh^K82+6W
z)jgP`ii33yQbSi=u^SQACsvf0r{^%nz^-!_YgFoGYMt!C>5Kw21K^?3TnW*xbD@%F
zxeZdljDg#Lr%mp8nR1ORY>9v0e**|wNz>DDln0yWR^57U4t!@l3AzmyWSBS-bSMW6
zW4;)10r=}Rr4M@lB{lr1$cN~p|K_XOM{g5K!Ci2?{-lze>{raSQ)lk5m3va?Pa^+0
zT$}GIUQ|Q+K5wbTSUUwHfp-0j8V&i!S5N|&3Y?vU%KTa5nZ6%tx8;}hIc58aGV#4V
z&<X;czE@)F@Di`Dl<!9C9%UOtVnfE_M?3iqv^<O+N);fBy<d%TZp$atjzR4cZtSqT
z^2^||GTXsSa0%R|pUdtgQ1fmvJ{Hy&#0rdgc~&hIeXl;b@6aFI2hP9Ic)3yMADnNN
zrCsK??RN1`NWxIVM?788^wbUPQAb4-K%AD6VP!&HENpS>kUJvfSfr2nBRx6g_H9i`
z1`9#)Gl%`QmI1Risada?eYDdGIG6QL0pZ107u-LDsbHUI>bEw>r8#NFy#!Fbf^&sv
z_c({G7oAGs8C*tXx{|MF*giU(-&u#p)%YHSQ-~$kouzx`83p6N;fDwa7!Ba>qKM7r
zZ?<_EDvQZKd*F+?OqMuoD&Gkn-*7wP`BF|N=u2LY_1Z)9CkkUb`SpYS|Nht>qe8|O
zor&ci5w?sXSv1Z<dJpaD?PzUm16Ydgf{IMLD+jKh&dxpg#t)TQ@ib*Y_Xx{FHdm%k
zj$GlwA9C{MXEHAg3-M90;RG`X@}X63FbO?zhhaz3MEqnb$j=3J?Auzjcf2W5ddyh?
zQ%NRmoP-6Be>idWHFCtyLBeWuE)Cd&=gldb+aJHVDPv;8pEQRjzIXJ)7}iKbj@5uP
zvB-dkbA5bH__biC$s6=rsh)tksN!@R!`<m=qSc5mhKM`{ozzA@T#VYsQUw99Ff47M
zwk0<NFO_P#x7D^+8XOkNvc95c&A$<58m7xmv@e^+HCB-XAL2*mwQ3zvZupSXayH7K
z1k+L***z6mWfu%1taaNMVXxEnK%uhTxs+ypJ%;mC5`ovb`*LrCY~P1jIV#2eHtUf3
zjEB#`57(|Ge=_rTl(vs#XgbV<y9_{alGk;qcHQfH=ZY@BAX0D2ln9ZK+69wVZ?RH$
zALOY<kzRN>E{&}(TM82~)Oy3R!*%=jhEOGOmVr`Hz#D0>DVIMUjcFV&s|ODWGxbzK
zEoD;!SG$Q#z*c~YW<%^jtpM85%J0@OV=xF~rZZ5HzNjpf{$`~-r=5y^1Y!gy8<9uX
z_CS`BKtct4yq*s3S{FC;auwMaO@jrpJ38?ZT(p1A#eCu>6=10~p7k+VF)2CbNe1NB
zC4l@owoo_9nKmtT?aw;h|KKYO`o=qJz<L0IcOiN0?aQ`z7wXE2Ap>&v?qU@8IMP-R
z($xK`8Vrn?czl@&(z~2dB`;SRQ3hskG(i>96U<elk@MVd{sjmBx9vQ_v!*Y`;oSl7
zclh-@jrRv<KE8pikU(K$qsM+C>NqIao||S=uzCKqHvs-+7QMYmMHFN2p%F>X86VwP
zy@}Orc(}s~xzW6FY(^R}=vWeqQEI$p$U2p+Vr3tMO(Nw8l+AD&hK#Vb$4M1nK_{&7
zEPwSbWgVs$;IfU@G*KCtm|4`rj(qBZ)ET}=pnL|pyNvBFEwEMrUSY3=+4ZAybu#NK
z;>z}`*RkUt?Pf}lITs&H%|v>{rsS6QsT#m!A3@d}K(?nBoyz51D6O}G+)`YbaMR!6
zyBTl6JX#H7N$;B`CFO*A4V(haPb<atrccn7XKbc$L^d&=?n1>(tr3~uj#;+dY-J?g
zC*3#kNWCH-f+chOqBv12y*0dChgsmop6^!HE2VRqhYAe2W&n!g;8~%me|vohPkNe_
z5wItYC3@xQi(!JJ4}CP<4o`V$ZzPk5ecs)-i=nm*dIeiF>(e(I#G_)qdc{3QB(N`x
zCpe#Ds6zs)O1fM4EWh#zBd6ga>LKG&Ea|jF^~e@!b?U@_%gR;?|IPtn_|z%jb`&4L
zplLPhv(zffwoH)!FtvD&kd7G)z2zN;&{EC4&|%7~qG`GU-i*8wP0mm-vp8Qb-&;aZ
z!|=o}@u*t(w4(<MXNHS~USfOHV$Ti2WXyk7%F=X<h~!3E0D4%)X~sM&@MjD1m#Yn-
z&>vthuI8boGgoAA74L8=SP=#6R^(e&wP=nI(ZZB4F$8^Prd^LEtIwD=h=7bBJu2j@
zkX{Y7bszmq@nCabdMyxke@TBPtvma2q$YGnc^dBb;2SH#_;{(B?MSueDOaREF3-f&
zuOq%t4UJGeIPMv6ZEC49$6%;b^<fw-#B!E%P<GQzkex;1wbmqziKHJARfCds-#{mv
zX!B`f_Ltc^XB^fAXr=Gc@4fziYvK$M7+oAtnl-u1Xi5z@ibOs0B_*5F@Pqq&M}VFR
z{y4Ez%n&I4Ylk{?$gO2{s-bP=1?i>=17MU}kX26ji8?5UX*TeDOZ`O7>XeY>((;2h
z7i(~%{8`cb_d=yqcuwFRsYn75PSJTEKeJ&1G7gWj-T(FGYM)z}=+A&kYmzSEOZx+4
zWot{#lxG={O=+%)ayQT3eApM0@t5PX=v$WLb$~s09CPwwYz|XJ3=i@QLO%!Xo+lKM
z&4e-EBea2O6FP(2P3M0E_Kq;+b{?x9Qq*3Q69BS~rg4^|(hQZ4TyaDBiH{;ndhYMa
zF2kEGWf0sd`x{LFs53i#fPm}?q$}U7gi{TS43JS6GXG{I<@>4ucEXR$x>_3%Ciw)b
zxj(kSosx(iQn-Q2A9(Dq(DjwTiq;3Z>^h*Q`QSLeQn11Vb&|w2vtI9lXP*go4xC9-
zZqXwo{0E`HP22_24F1Hi6zhK!`9{s`Px$3FG8zoD2)J{He8!Bx;Ag3IEBrHg*kdzz
z3O>cR+JzNmQb<pNs|`FS<oS%j;EN9WE#1G>f1AgLxw}D3;C5gPw#c+ymm4On>q2uA
zuS+Rf)<y#N9nEWpZ*O!tAI=>~0JH+eK&N5;2s(dX@|iOzSwq7=)zq~8A2XOulO=1M
z?G?j1<KHMPw~a%e7KMkQ>xa5gNUb)i+wPos6&x_ex#36JxMdY9NO!hNX#HgeX1*E2
zeXLt|l%iIg03@YIxe1GryCdI8R*goN=$}p4b498gi>g&k&CCfCtr1B*U5VJWDK4{a
z#^7*Bx#zK|{^)n$HErkP=b>hY9$=i5!v*!vX=@})$w1{CMn{XRo`62QiCCN7=1q5c
z2ufYAv%<NG?sU^*M8*8{%_1F^Bv}9o9;%(<uatX~X$R}uH=889`DSz~7X#&5kj*E{
zQ4Zc$SlAn~+HxqGVK9SRpaRwoEX+a?p0aVn5YtN@&3#E+$x|g0zxuikQ#)SJf$b0i
zSDZ5bZ&s+mu%3w*N00J>B%UGHLCJ8l>GF}pgv=IV2WZui)I+0r&E(1=9h`Yr=4+wG
zc8d0AEZA*FCY5&cJvj@$vc++mB8()4p<jahdI+?s3eh!?jRk}Qvv8cuG>f;yA3spV
z)X-1_P4qzlv4M|_WS+Xd2HMO)BD+}FOejBTKCcNzX>BY<eV^g1V@ErY%6P!!{UK4I
z>(PJ7xnd&bE14LP)pej4*0?5#e8B3y-&vr^l7$t{d!tZAN|hIDx>n9d&Gi8Il2-EV
z*)A}6FrlaF>f^Nm0ReL6)VK!Uc|U}rudd|wJCuc7x>tyq!@`Mb>g0)+^h+c#M3x;1
z$)H>tSxoVu`$L1d2}Y#iDiyaiYdAr{g|f2*_3J`))~K>@bCpAw=kK$*Mfi^v^?Rqh
zz(FEiV7U=27_mcuv#KF`x-h|?^Eys>So;i6arNxRAJqKl=oFVLKm`7NQ!n{&=B#?D
zK1BDRKjisnvShX=F}j)y7lvmK;5-9#2xKWzmAzAQ$c(!C(aZS03QMAo5);-y?C}M7
z&AEQ-`|z!g8=ThhJdPm2)x>c>u7{`2|8UAJI51XRpB6IrHU%5uEau}MNNLYnD#%@H
zzYY{$j*tm$q#xzO5ym48a$-XauDPSNjef{4423oDgRAF%EX1gKPjeL8=M?+n%KN^+
z^>Qd+mZr@RE$cu+qM=<DMro$TZ$QJ(JRLCLE8zd9ltKG8x16%PCppyh8@?&)iY%d~
zOH*$N@%i_YpBnd393?Qb`U(y3N^q%RE<^W}TxR~x29Hl;O1Cmv!5iuO=F2bgOT*`V
z1{=D*G*Nf}M}YcF-)%d~>(HtFz<h|566g%e4UXZ%A`nRNPT}7{uPAN{OUp%T<3(%w
zY1u-C9MWV&WfytGg6I*X=~m<aE2{<in102@I_<983QFmX=34i8G_jXK+60?Ov4jF}
z4h-ieae;whG7pm#`{V^w^h**^r%F?+l`zcoCEfk&#B#hx<%bWUU|ak7IntkZxnA0k
z;BR5haV!vB|Ey|rTiV^{7a{(zo50hMu&?RY#VimTGHbfs@^8?eE+j)ncbk4Dsef`%
zS&QS2TL=xEWsVsKcP|lTdrsflXJ0%cV+j{hY|4eMHP(l46t5c+lS7r~B;%1f5FLO~
zd(=Ow3E=k>3vLxVP(Y>8K3A&4W!ATG-(8<8P+E4ZMXoz06wShrOb6-z<F!MLN7iuB
zD;|E8GNxajLoY728u(kJk$Je1(X0;zIu*zrboNYcY^K;sPKx*^PI;Bq>S{Z1W=kZh
zO7R_2<;{%;*9<Dv-ot4d*k1UD_Oue#2PsM5>fAEV5&eQMBJNs3kLv!FWn=xpVL0l-
z?Nl+A#FckNyu+P$PjROGTb+#?Hf#d#KU|K=g(Gw`{<$myWH@MwCK9fCQj<ET<|I!w
zVh~%UU7!6{yehP+K5MQ%LqIyq&qQb}el@r~rjW=M8A{J11xHE9hQYa=3H*qUf+}0*
zf`L?$&u5Bgw1=?Bs5gD+n<ZdCARrMH<o0VbAzxI};sKq)*6kLzyk4@@#;%`<u|Dn4
zP)vs?#mW3rn}E=H7*K{68Yks_<q1!?87$`d=8C7m_`^8QD$bq%s=(8Cf*IEcEA{Nj
zGR0HzP!zS=HSE5DFGmpSVMQb6u$)5pV|Q=U<aChxRB{|e74y-yEjICe239{up9Yrf
z5*8&B({LCdZE)<hO5TQjZg3CqSG@udCbXNSl%oMPzI9VdKzhO@C39k<RplY<J=|X%
zcutSh7Cfm0D{~^;V~dcBch<E8u~a0Tr5#gm1{XIUrQEW_F6LH?IdS-N$@BsX<amM5
zGdZa~pwqca8l|lTD+HsBOL+)S3y`^FAR--Xj>rHrK+L~OJ4kh9^W5~KYSr@;6FrEt
z&71+Ncq1EM8uK<~vVankOIj}^kYO{Cu458+Gcm{f2vq6L9j^*90tOD`96tdl>pV2C
zfSApir!NU4<8xd}@(0sJ$1&U2X|&IZ5lu-vGtkZ!M+GzJA_1M@#7AW`VdQ=q9CB`K
zO4yfKasoe#9sAgZ+1|b;(g9PSMfH=LXw)+>S%q7Iz3a(0G3h`xd{*8ZyK<1tWc|>W
zr01rFQ@1W*Lxep@gQs!2i8|B}*+(*%q+zGxPejE=-KgxEbeBBZraiUV0|HxbQ_WaG
z#Maqf#a?C=*8YnJB!hS1$0sO}E=d0f+rYSzmOR*H!#ob7T;Yx^TaXB$liO*dY9>6y
z0+J_^{F^q6#YA8*dWuz#jN<xpT86@7IBczmx5}JUus|jxdAk{?nffaa?U6<5D|w@V
z#EOB`pWJe=>9#rTL&?D=(yIG}uUok`a4bsI8I&y42NP`IpsR#}<h}Z`ToU8nRW6+;
zjgoj_%e)+Ep&63d!Q{BC#DGN&V%i@D`H5M6;>656<Y*753lBGfA?Ggd4kk|LTaKH5
ze!ZZUp(x|U`cH0sv?HR>c&v*sYxXmyx{S%OsgKuG4eNasWI?hUitr7R!Z!BV1&_zu
zFxqzSL-9`Nw>iwreNfgBxIe&q0j_X+m1acwxmJvhOykl!9CrviiY%&+JfC#irq%R4
zc$TH)rDV{#fN^B3XM6(n(>I?SUr3aUTI|`)T~aK0`SQL!me`w<0XH2`{~hVT0P7q`
z6=@x2h;Vn$P`#B4m>Qqw7pBN66O}|tpYNbraWuh%TDZA;;WX?l3zG_Yn@xttcRi0g
zC{e6uYn%`bLb(b|gwXau53DAz$e(qA?5y_-_HGWC<4?K8g1&o3gDUdGGv?plDvk;c
z{)4cdckN(@1O-tTEH5=SeTZi;aSF)lvhvWK8-yGgm1cd#Wc|`k2`AeRARxKagjEHd
zzD^iyGl|nbC}V>>Shvtk6VhZIT<F~3@fK5(6*T?ohkRdv^UR)+kh`pbQtqn+Bc-W&
zNX09FRcm3yDW&~bymdt&<Ny{G)cJt?_2prR3*5;r!I9%G>7o+efMQ?6yGIYi;<=_w
zI(X%4Kx+;(N!4bbtG(uHzfUI^|3k_;YEWhwW~NsZgu&7~H_fedQN?pe8#|UrSRpDp
zm7c&y_QNo>oKCQr^%elOleL3M5Jlx50Xq@Pf=}b4n&+C<OTuZc!Xe!Do#>IE(`S*1
zUwrd0emx6;*x9Z9eMD9L6-b7R?;|`C+FQhazgHr5FP^??IFZGIBgG-Im%h=zaH-;a
ztlLVz;j&*Qx+3Xt5_}h#i7;lDBsnA0|BRCOSKG34d(uP>7QNC$81^?K{?Ee+`Doc}
zf?W=W>q0R#ok5R9QQ;Z@=^I>R>48<T2Nrg8DAGsKP_~;s5=2yT3Kr^i;p&Q3CYSHL
z!eQJJ#`-(wot7qCS(K!OET!Mzc7Q@#l!fM`PJe0WLnXRUJT6ARV1(~vP_m5BE!MJV
zZMK*D&%@qJ0D+)}&IRI;F-;KXB^zgz5_2!wE#cl4Zf^v-Pv$0Y5Ha%mWtGpWN6J^)
zD+VRKMg=v0SSiq$YV_fpo$<DG8v3|GO8ftgs>x3H-r_kv3+<%9>Pl0o>JiPXPLw2c
znFHzfijQw_LbZ+rqm~qSj;jpH9tW3D+vCUF)0N=CPC=I3N(<p8Sz-uL`C+l{@`n0B
z`lm#hjp<h&JtF-XVt~x--~XU!%e(k2i>({yf~<};NFMMZFK8K(>gD;<_My<e`2oS6
zc?62MfCG5Y>@v0h2U#%E8hL(BBox1TB4X31I`hH&MDeUvX=-3Zp^N)PqshUbdwe7v
zJMJ)Y8;+3r*+WR1v7gHg+EEfiE!$d|b2_RO`A8l|pg?*R=kUOoRIf`TQLPX^J3E9B
z!121vX<un0$^wsyZNV%e-x;CT1s}l`pEy;R5`Tpo74_;9`N{*Lo@gbEk6Gd)h>gpP
zvj*cZA<6Uq7u@%#bi6&EBy}jbGq{!h@b#75qovXv&6jFVbc-2Z?YDG7c}1ilwc6Fw
z+|&f1cF++3+*EM{N#|?%U-4P(X%L>JNlK2FDn79C4)re7?YS1aHeJtSahoY2heN3z
z!3VnEL2GpG^HYY$%uZLsb})xnYgpdQcO*-ArU*zaQWp*7OR9{`=5*7rA`mRymER&*
zAZQ@86I<^hUVMZT<dI(P)rseWv@tm8O{>I?|8ED2%M?U@J>B$DX$!EcYh{Q^ABptl
zrD0qavrtnesh2%t`2&rJTL2CstzkrRyHG@{sW5y4xA&TsOu+V}TC#^AzHhIz)gN8X
z^|b>AG8mmpO9|tWorQBZDS4tta2G#LFi5Bq;bE2^=23v6MBHyV8-Ij33zoVWPRH<U
z3MXK^9YA`7546qd53>$KFV_{5&j8F(4rX%!L*TF-8}JFCEM4oMlz@tdKlrjPL*`)w
zAGRx%2QTQG9B*xCI*nA0Dw_ihq7HNvK&x^Wa=ndDIHIJ*QQ<!{95r4ERZ`-w;2%$G
zb|0Td`4N+cFbkMO{U4XCt>rB_;`-JP^s}b*;%pOot-e{_6tEEP)%G$vDy|k=Otpn8
zA&pPfq5>j54sgfG7!6a_0mE)ae{0{TZSf18K0)Ff1_4|~J|u)p=ZRz*(leq$akfER
zJ~tv`-f0P9f=6xYfuP8%fI3gL*cFw>0cf9)vn5uk6bMMh%L;z**uNO~+4}^6W46?6
z1RS(S5w}RX3Bx?Q7w+9Vn2-_Bg^OXFS?lG1R=J?O1e#WKBhLfxp^Ibu$28Mt@84ET
zy;EE+FhC4iv2IW0<s31RepFaH=3Uxasjoyzt0W-`RCeG~TeV~Mo@Kbr<6};ni963o
zP!U^6XsN=6IA_$asZJTR0;G=-O$|&i%MaDjFg;asb7!O3(#J(`!7}%L^`XB?I1n_>
zz*)Ns){zzGw6u7*BlXhW^cLWn)J?-lyi*AKaCIJ864u=9M3H{=w3tbaK_bV%ialb_
z9*@NDtHNq<hx9CIcwY8UkcHmoy#r(MbS<6M6i?5w$>p~ygKyt&hD^-Swig|5@HhF!
z(CCfSeM)Dpj@qFu<0?d%m;G6<sg8FirP3WUpX`DTyBs4)B$3?Kpp@PDguxXSEb*Nw
zW3H!j#o}K6cYTL3;${Au6=U{2OmhQD<%Wq?t}-mIE~|55Ec_$!6GBa-Y!orpKjS#R
z_;l-LL;!YA<E7lVveL0y$`l~1B>Nm(J&P)2o|kTT1gQ?lA{*iTD{+`PFZ?F#Ax@Af
zqHh6)&0_XL+l^)(;Q&cCzPTvn4*)qEz_O%zECTfUtuT8>x>50pKYrTpr=w5df>-b^
zPD5#5B~ci3H{G50v7~j1W)5Fm5S~}yB}d8X@tdn}3PU9effLsvfCo!F*XCZud=^?_
z67Y)gsgKiN=-5}5Wk=^MaF<qwU0!d+GzhsN^LM5dc|yWjX^)D}1%_nlpR1kV-7>Hc
zcXC_T+NBS{w(ysC08o4b^lQyC*4FYglMcYFj}={~jIMM0X&tX*zy=I`wl_hkEn6Dq
z`$|?~Mjy6JUa&7HQDpZ=6+Alqc-JYMR^4}Sc*3${KyxLLX9c=7wYb{~0UGjZsDK6o
ztaJLeU$@jz(8Buy504qH+<8Yo_!}IMW#F((qI62Fz)awuQE$YaG;%=2oF>QxvjT>i
zO$^4jK`MlX@~Q9G2fuM80y4J{vH1DR!+|(o!_<lw$f;Ya0KES=MV`SFr%&Swkp@>M
z%&z5I9jI;4jmvtc0gp37P6y|Lg{pMPIX?FcCTb025$Fnro|5Rc(>VRSRHL3Jsa+{&
zMEfv1#oeBxU}`W*+=IC!PrXbSEc-|Oqc?mE8(!1tP<VjUnW#i-<>~Fdz<T7@>?g~?
zk-I-Tc%O9APmZy7+g*Rd$q9NkR;tgYh;3uushNsg8!j%UBOQL|p&V&eeD+#2Gn9e6
zUCl|z)w_jc(;yabTO+u^O94+2Nv__^!XOE&1Y4N`Aer1FM#YUF0I_C2`iUdVuNIe^
ztdT+Wk<IuDqExntjUAkqOC`qNv(5ugqhM4Wjvizv4|_pQP5LTRp>GZZ@SH#f`x4!V
zcNmr&TFigwf^_#bBi<Lg95Rg7q%e>Ex_p`f(9I3trP+8oM}|pKBBv=!R&fG~aV*19
zBzXq-Uj3dbg5h->jIn$`F9Lz7S-5t9+2FA%zw6bH$uGz#x_x0Q2^f~FXPx4}+fwQg
zNbHNPzE`AG77WcN6_2R1@A}fH$2p<-tcnPoEL&~wdjDE!eqjLn0<cJL=ri%!4O2m`
zTlmZf4NgLCEaIcGDk;G9d9~{aM@*mFGpq+XHDd4MDc?FXG;wB=D19ax)4rugK0<vO
z6(63b)4_Lf%<sz_j$j#HOWGI~ba;oXbrhCbWYQHrS)!d<a32bmTU453xkZ?WmR_t1
z;{@qQX{f$0GcQN=1<bnTjAS*DW93hWc~-zS8Ci%vJtq(lf=UrH?TeCA6}zQ6kgwIo
z5FgiD^}vb92v}4HqX8AGLl}oKcQNyZyjh^Fw*YUkhI{c|@fW)s?E{>%Om+P8s_gJk
zPVp(R*ke$sQgT+p%eclq%jk$EnsMCWtkrn~FTm`~3Eh8=`?*QZ)+qJ8Xt{nds_juF
zUds#CLn{$&Uu`rAj$vczmvF&-__Myc*lzo%8@W4Gs7fRD%wr`HFl32Jh+fBs``c7X
zaVOUe>1Kl7MYey(rguN3q0Jk~s7is_>j6o^Ry@9&prPD<nq3)-w}5Ly$A1ZD@)#@<
z@xXg(go$wI@77%_A_*HUwnQOHmIpUT1h@f+Z<}A!>&A~Q9L1MAF#9n6v1fpMPcMt6
zVImsK!IBl0NfE_Tqni0nfzNam`V?DI{uwRv0y}g>&d~+D(Jw?k08&39&BtLlJ-M2Q
z{#S9Ny7Vq;zxX<in8a(s*V7V(gPO4XGhbuczS@W)%=P%L6b^e}@fp$(MVR+nn$-FV
zf|3vkXIv=gZ<65zyP<n0-G)hl9{c;y5-yoqpJL?z<!qW4MYG!jI7Q7=ay$CYROeV(
z8KcqQ5_8fF0Q%EFM`yu=o){lar^Qo&b-*SiC{g0COwqhnn=pe6ihMgn83T#2=$#Ty
zW0H|8Y65!;7kEK7+2&pJbf92aMcJ>?X2TRBmXJ^L5ZPlw`j|gSgNCD6?JyvyFug^E
z+56f__bhWa@O`}j=xoXSh@+DjD#RkQARhhE!Q4r~i0#G;f%|c9%Y=(P@hQL{(iU<J
z368J7h>86auy-dQn!Odc>#k_sxeldWj-h!XWRF;N`@|Y)zzn^tWj(cVUulWBRyO~G
z@NtUxZcsXcodsic##dUaU3OXf`3MyNGdR>%4Qp_pE+uK`&!o|n@T?)L$dSK9Lj@fO
zeO%C-HC`E>6QU;FaMYvRVM}<JnGo3L#9d?YWQ~D1qjZ8;bNplqB1B=tQ^w$;+@O5w
zV5vz~j4*kCT$&o!KmCiYe?;F&Sd2qc_fW)AOC~jPEJ9fkL$UBz)Zr2i%x=?l&xB-2
z76<jNMzMgbjEuCI0XFR?HIOqp9%G1=ws0ji+<i-*Mh=&-QuoL>8<EU;HtPFYLj!ob
zD@`<n(q^!Lcqo8^bNDSlz9_i0q(027?zEPBsp~q$*NV;;2u=1-&+l(b>vy532!Mf<
zvm1-D{5vZ&oZ;KqZ@$D;X8w_MfQb)~|NGw|snnZ$jpdc`QB=Hq+;1N|jGvTc=)82e
z-|MYeoU399TxY!R_ZVAH$TTDXfB={wVkL@n;8LD&%}mL_g|I>bUZV%<?t~3_=${;?
z{;s|J_a8wHY>U5n7zu0HhEDNx&@1xm-phYszW2~7P;opu(v&GFv9m|W`W8IO+QQL`
za+Sm^(rd7VJX=w}*|y+JZr+-?76(Oh8=^MBLN9_mv+Fo)wEriIgXTgP%j9@p-xf*U
zuk*FbF_nyE7AcV+{_J4gyucx%SX=$L8*+*%lFeFu2ei*zgC*`%=DJR+q3g0`;r6T@
z1!Q_VLt`y(u7=!uaH0zw)`94`qA$vF#s}1Urm?K~aB|dOXv-flPe-;S|M31MOSQ+<
zyC7;_QNW_5;nm`G4lBhB{n|Wx-#;tjbY=n9N#$IVknARt>kcMPXLNQ)T5}&=C84>>
zXUF3KtzfhHis{EU=ab#wU#zF#?t?veK2neAWFk$atym65L;0;ZMX`XVE5(~&_s7L5
znS-@=Fm~O$OSML1zn5Crwqr%BIdX%SN^}}pqJ*|++QqWr%(O5FgH~nc?eot_oD)n1
z+b}P5n$M=LDR0_IRz5Mh7a^}Iyk8j(t2e^7mi4TmKBSsJu2y~|_CdCalCdC<kVI~j
zif%6r%gD+-)`FI+xl@vU_W0cAWll*$r9RJbb<d;LvK+yltrCN8+WOuzII{q6xk*y)
z3QSIh_r`=?$K_LslHvBUb+ooSp%x%?nQxhi;}p!LU@v2i8P$sarz*HVVB<GV?m{|p
z&m(vH*85<N5LqSVD1PQ~JZTtahD9c!9Q<K+Ql*!%2eEb*x5&S-aAvD=qA|2AuhFlL
zsuJ}7TwE8G+V`VYAsO1^KmWE0mL7MR-AMAr8)28i(+viW#a4&HmV{d9PK?=1Is#-i
z$M+bq^{uQtv7f(jjWIc<<En`RfWk~(3%I${i*5w{myK#-kP_v5$9Sh6XQBp-ic$q3
zfsH;he(fUH>ZD1RD$J4K5U3b^0pRQM66gD8hq1zea1F-^^cUvLMZhc1pUk!GNjL<_
zifeRSA0K2b@6}XF+HVzx`aPN?l%?Ko2^{_gNi7+EG?DuM{(^T{*ex<(eeZ){SU2sN
z(&*7E-~WxhL8*UseEGX8J~FGi0D&-)Ddqo@+?KU0Ns?;;8LUlSU;-ewB)_VJdY^dQ
zJLCf7rpO*(%}ug@F`=W^dC^68YH{q-RzCSZ&r{0oLeCqN5T%;HrjD;B3(O@x(vC#9
z**?@+Vo?wQxsq#O$Qz9Re$`_+aS1|*zCcnyFZD7kwB6pTu=C1w+dsQ4)tu5y{1=39
zvM0rCsT>{qcbSk|TLw9CLzXKDl5SZ}Y{dfw?g^4s`>B%pL2wInT6$n;Q6VYm(=V3_
zFUym@FUkT1`I3>McsYt&jnFdL-ZYrIORkJ?kj`1s2z=TuX~!j=2kV82U*N%`m`=Rj
zJ<Gz+@g-t(P=1;Z<MMo+>(xeAT}xp_A9?F@UBbCKJHMkr2;r=lF*r!6a_H!Cx@}ze
zs>eKA?79Hf<pV2*Cl6MqxwS7n%nQbF{p-L(63UGI$a28s3a2It@g{!A;TPi5XP=6e
zO}xp5*MWc6dQqA~`%DyHRS61T<SQ{_%SH^$>&0M_Gg*pY;UTs{l;s|0qo>%YC0l@#
zw*R$p$-mce8&lZ5lq`jp%rSsm7v-eR=xL$F=<a_ECLYQ%|9en1#-aQQ!hQa3F*L?B
zl**uFv<G<k-b={Qp8f0}G*{upuLclK;6?9CDkm}?CtP-+tq$Qf><Gp&dzh^lH*rb#
zM0JzE)WPU9&}(lHLJI6<+vV#7d%|ZdnX}~8TpS_pHyruqey0r?J}!%w6eFw=-7C7W
zW0Mx?$ss1#Do{@@#yI4b5Z#j9-5j@-pEKA*eb?v2toVrjgRR3k7y?XE5JBuC8$``r
z`3Ee423mu4V4;bLZW5fS>JyF|!bZX{$F;C$!npj4T@fxIO#W-I<GV|jOw9=Vmqsk4
zK8+n1DLjhlkV&H)-QaV1TTX&TgKM6wEh6G1sorw?zm~Lqs?jq|#Y8ATmo`$4d&A6S
zO-@o1x8{iEknzfy$OvjR`p<P^%`cPWyD}5h)EWEyH0$_VRWjjIC||H#l6uACYB#ri
z92DbF9dL|HUjT(m$s-PGRw43}e|H6_pS|uHvFyiXohB8qs)w|*vUOc?9vV#c)2ysb
zDc6@2xc5XxTWgW>%Swa1ze0XMzV2Owr`dt;4K)k2y8?q2tp$icXyZ3EF%ndA6k9~5
zN<cFRWJ67$6VkfU9V3*1Y~wHpkh;T?4HQYUfqsN(RPJ4_;ss<ZbWcsn*l$Dm@R`-U
zTq8}!-|Z<f*AC7;W&QYk?dOXnaz;2+E8FUrFG;b~y{Oet>aKq#NWpK=fEo+3O)go<
z#t40obWgisNC3q=Nks7#*~$YN_c>0Xm>GbBv{iyNTo<aro=ypI^P{hJx>3rqm<3W}
z6tE`rt8yMFa8Ic|M&sSOOAn>1|IaW-9tP{r&hTAZ$%8|`oCmKB*k?0I@23BHk<3Q^
z<BSoUkFG^N{DT+mpPa~llng7==7A5x?9~%v8*eGcMqd)5;EOFP>-Fopp9)G#za{d)
zCBCu!vL3Z&8Xxr*qL$0B>Covck(n;n$DcYASP>E!5)IFm!zWleAE16?mGJ%|6iAs)
zPR75zW%(}l^<sH=2NG4*7WpLr`3o{Pa~;1ZA6NBHHqLP{qT}^^iol#7owG4)<Oqhv
zXzdopr60G*EM8U|tjtc4pYny*4f}zk3?Oz#6+(Hv{m;l@T=0A6(~^B}WFBTs`e~Kl
zLpws6XF>2G3n#AJEJil$s5Moq%IvPF15lAR$JQp)!V))FI*jt@dB=M3n#F5lX$&B8
z7M4j1^X&=}JCb^oDh}|u?P|Gd+r|CRJcaT5ehVbeNW7Ifu^XT2Oh1D4h@;9DM`1qO
zt{%uO`?E~<#uBMVbp&^!!cf6w(J&$@y<|ZKJMXS*NOjJBIW&mwnwKY4-0-09pb3;Q
z4XrAWAQ`!&zL8g!h-ry|GTjNep^F)UF}>|R_kW}Zl-6bZ?*zXx!qaBh_|Jr7I-Pes
z|BU$Rk#|8gm+HqiRIG)hV1-ADy9t+Ut9O>~e@}Vem?g*d<oV_U$1=c=V2gT-eHmZ<
z9#|E8D2Gk!14>;7*w6xAWFqx~y6O~nj_R!S6I0am(crweS(WzBD7&6ddNlY1e<{BG
zqKcc`pO9KMO`eMOeHi{v50wkRYDvAp#*OjtM<56nz(KR5rcco?%T%ugQ#8_7t<8T_
zB!O<XTa$69U(GTdG09@w<$TC_-gh<}Ql20wE}5iB1FwF7SslfyB8@njvY747{x9Fi
zRuP7`LGoV!&i8?`zgJ&2vnBZ(tu;3-l}xZCZsJuKf;gh(5cEM}#}ZYMigwJ_R9;tC
zh<7R$!nq3nkZc4YtZr9Y)h}`)sg!QPsHag}7d^itvpcSBPL;p<o6z^~n4d89F5N>o
zJ2I4;Tu;#TIr~P-BB%M}-Pdp;B+fNI;)m2p3tJNF%Dmn*p*|#bf^Nn9A(G!?iztN)
z=;d2wB9IR5*vuHWg9|o=h=47N6#RxMb(YosR9-06hwX}$4&@&Ie!7P|snGYs$i~>^
zSi;p@jTC1@a*y_Sx|Y8zo*3o=%@Y5;+}I^=B;1axp|BgSi4$`3Kx%Uq=SVWm|CbA8
z)ODA=9S}D=#sE45FAR52NH`p9WGgb}_E?D7CdMA^GRjnBaEL<!2-V^dQeXBXrRzLM
zUIV;7tkZNI;wdF%c(eqKi7<G|ZtXlN#1HpAE`iMQsRx9f_q@U8c(8HC$Mj1MK#h3{
zlDCJ%W2tUL+h+3vjaxNw>-CEx1FWdDJ1YH?$lcs1a}AY@g7m^(RucJuKDiPC5p($-
z7IT{UIWP?ygxOCt4{+4Y*93#jrPlgp2@T^~I^(-}=cVTIZC7FN-^DEqFwMEe{$1LI
znfx;Mu%wE6<GVZy5!hcJVxyrSt!Z#gOUAwhcG^ekJESwKdxm}0P{ag7E*dGJ#1)E=
zL0HWPsk(j;sAC<Zpaa@d%x0~~1Q3DFO0WRv<Xx)Yqf)?M%UsEYNZ{+FD<h9I6;rlb
zy7CbfNwXMLa+)!8%FUKANr-Z}HP{FNVi@*56%_In@Aia8ykz|b^LIG{WA3i1P>pfR
zhgd||c!O%W`E*UaVAXgtnG^=x+Mjl0$;MK!lkJ~Vqwm=2-fa>&b>`aET%k?Nk{(Y+
zTK<OOOE-DR@I-SEb%x(BaCO(h2<q3XtT&)&^XZ(eUHhFopG0oTMXa`m>V4YaN4f2D
zZviqAL7U+eT_K`M%*$i_CMPjXmao^62;#LO_ERoup$!*(DBYhiCO7NQbRoE}_007=
zgs2FnIPHR!H~rQiFD@wCuIG$VW5M<O4@?P%=%aOIE=Qic#M4b!eRTYhzWuk;nvF1g
zNgz-gazpQKd0MF}GbVboRwjz_4vEswSSBk&sMs&rZtUZGDn-+tlHBx}Kd%AyJM22<
zaVPrba~_dvC>MI{^iEGtv5LX%Oh&;(Rhu9*(kiO0F;1_cO~OiRWuwm<`q%Dk`j<V^
zP13ifP7Ed*W@9BteeAIcrUxzmQ<*U7_^Q9+`vGaAEya`izfA6((BOGq1rAP5GEc>r
zrImQ*-JVc<)agt9HU9xJVAY?vbqU{L))SzxGDOHBiW2P1i<{iImnA2B;CUDbP_JBr
zEZ&JyzRw+CsSYlV23tWkMAEZVlTIKtUXR&j>v-@KqhRE#lZht;(dc`Q0}s66%(n;n
z;y4gYOdn5PC*RhcDwh;(2$<j##j)7ANrIJvPq2d6AAykB^gu0CC&cW>y`PBHqc9c$
z`Q?SXA(yg8cigwJ+dUu5LlPVa_SVikVKjFNAu?*>TG)jey0MxEfb`0q!@|RGaT8kp
zLL~;Vhd`hHaGtp&THxsDHfN~q;E^D~WX3#W$QUzy`D*-)vS8h%OT`ZW%0BY!SMwl1
zG{q$i6l-W+HkD>~?!Jej;(9LcraA{KVf~pDnRt5u1D6_y2w;Uzf|b>>LCO#8kl3ko
zA&Tb11-O@&r;uA5`dy*DpJaN7W7WFSOyCb$UwH;)eYY-)2s&zmKzXM*T-$XrNP*D(
z^?Y#r6;PHtyxAI>mC~Qmq`1KyeSMpraL2@c;%rI}PX;ul*sfvraIDAcZ|zr}6*c6;
z5~Nv6@eEOxfJZ=oed<HrSPqhi;BApKAAi$Ta=vcJf#5g$w-|CDVhb$#40weYD{ebT
zRRiEI%JI;3=1^gE2&=083QqULV+UNOy^7z8YYzy2{zKPh+YQZFyZ8tDdmlZE?j2$5
zp1s+N3cL(#H#I7#x>BIcX~&mr8_ahXmPT1Plx-v0Cs%9dyj%CacwiDY|IjRf;r|x9
z_vOn#rQ+LQWxzuCl)Bij<cN&F%ZP(YSYKvx5K{%$JlW~@2bSdNjZRo_n`tL0@$h?~
z%1Cm0I#|(xkB%xt1Oz*B%4Qu@PyK8j6Sqj|Bm`FR5R4D+FI-uxMZqL#^=4wC+R9@*
z;Dx2XY;!F;0uxGk<1jIV4}9wY4&}k3CWDMEfk&JsVVP*P9}cZ_8P%44uN+!4D_pH_
z0ECnroOavylPc1JV;ODf?t>r8x9*l{#WOg}SJ5o-sqt+hgKxn;#QUu&-`ww`aU`kN
z)$KwYkpuiT;COOxakGFYt-}(oYZKC*8fNu2r_8eV=;wvcx_kg!^#b=;{bagsP=)BF
zp%`1@Tr*Ur-@Go@G_8{czw{N8TqWcQq+{B8=U$3k1OVFvG{J)OOHPvwrC6t!{Tvci
z1<`QQnb;?adh;(r(J8^#=ou8&*{vTp7HOLwF++6Uy7u6BEpJLB7TM-rL~+rTlpz<O
z1{o;v3od3+AGsXj&W2rjXD0Sw+bdPl>sF&KM!oU~Ym_$9Y(;@^i@Q;b*c|EFmiN}i
z@_@#yT~_j*t%@P#jd~+SBeul{lSC4z!!`o=93g7JKG8L%lHvs5J@}a<f)`}N9Q_DU
zLRbT$BAo~VYP9i%P?dRNs(IhUZ(iCP>KoGoFHiZWA!St^=EM=Msgo^;wlgBDm*i-o
z-3#yj$PJ|tX8@v2o=KEi<-(k(8HQEJ4^b<yBqZYc2u-sr`z@khCZH71<}_lmqri4&
z>uaNc7tK)P0GYRCb@wE>;<GH@ReyYwGDXM8HjNkQc9MGH%#b|7V%eOCvd3XMOPGEz
z?kj}j5}oGfB>k?WE>)50`Cg&REPkKexRPd^YO=>jGcxa3Xt2p)y>23>p2>I<R-{AX
zQcPPFhEE#9%Z;Z1c?<PQM51O62x=?o%9U10HUi#0#knX;Wn{OjJ(c6?Y}ho{QHGpk
z!<ug)qKYqv1U;vvzLBN9U_D7{uKMx<;2H;|<M^i-V+2L@24A-A@|Y#<G(>EAbx$iC
zY>WUPlruW>TlS3wi{q4Si1(V(lVhbSK{%egC8w&2Yyc>t@MV>klcx2br^*-WuT^|%
zfihM3`0)!F4A=^cLk7#oFP^xUB9$Z-kXy=@{%vIWZ*+nw9S_*!nSW8uw5l&dPq=}H
zhfGIUIIrFD>YEX!ft#DV^4mq&_OQuTreGl>2#F^TVe3aXcTkn(HVc4rRptp(;m=j9
zq5zhg3($TP%y)WoHMZ4x#$VU<tRHu?bwo|}Y(+%9G<CNE0U+8I3U?04#dbmWsfSw>
z>TD|f)|g2$>bxGTE}%b(>-NKvs5EF4f5KT+zYD2tet7xNKy~zFv;TZ++Xrr@lf{1^
zzLs68Vc)%p4zr@Ym%oG!-=7>iYu)R#%%ILO5>k-sgYgx7xRXmX^A2~Q2yAR`$eb$~
z8SbVaa1N^wSLQX~$(x*+@0`yZx$cyqCZEzc5dueeE#=SOv@Vp)-3GvC80C9tUSi>>
z<^_1hA@ena@TTURXN|m;P~{?960O^52@%tSq8BJ!=`fUHW|d^{FT{NTz;z&y)5j?X
zA?|QO7p22UbA>M2Vx!;SZwEL||7Wflr%pVDAmvrgl1F*sDs*IN%u^fWH6eG`RY3;_
zr1U|X;u>ZZe4g+WKU)$XkWV{UkJT*-_!pwo{?^JmVq?%2z;x$aG{n73j3`*^6&<;m
zYC?td^5yjPQU^dNbf%l+#n(70QVp=s&eyXnCy%0MK!?fK0=BYg;Id4X8H+e=_bYhS
zi#&IhjIoa_8nL(svFP-=rD>+!J<gk7*}J^NO5`w(O~GU%D5u}BrgkgE3Ad+5WyFRA
z!dQ~}Dt!2I8b(sD`%X|qEI}TJyY@q@cgP+K4L_wf$4vUS0v4L5J>*(b;rth0Y2ovK
zleMrxBE%Z`;22s*MJf@upzNF8cjLKLr?5{YLkGX-pT&w5ya-qRUMs2v0Qn*rJ;`6K
z<VNhPURp?vqudh*X5Wvi48%veN+?+PNvx`aAE;wqr*KlM8cTfr^nQb1H5(vv-8G!{
z*-&>0k?@-(n(>YO5vi1AQloDxpHl<&SC$rNswxJ%`(pybLRVM|d#}D6uS~t~*$?z*
zO5q~I9g_RP9T(*iVVRs#Q17(~b7GgmQa1Vg+y+2UTSXSKGv0rcudyXI+z7g7f!G$E
z@0?CX^ko^k=>H~&QyJipAiyLBFr4&O#(Kagn}@g8uMzsz^;egiXSQQZ;WK@7N>~~B
z<=BMj@M~=H5NS|hY!lN)Hk+)7MBx_h>Ktuhwfa@-&PULd!OC+<dqn}mu!6nd>cLy6
zmye~|{N=kw%V(Y-Lv?tD;VLBSW-f_^Xs_Y1CcKP0rY}b&a|z&opZ69o=d3_f7YjQf
ziW)NPk=fa!hC^Yn@TpQb<g8yB@-F!zCH+d3Bkq3hX%fml)f=f-znUrKo3l}Yp|{;O
z69e0BaqcE>IfuIllIf<R1@tib&`^I~vcR8LSRwnnR@I#*bEypfKFDlv^XdVMb*>{y
z>Q>IqqWP;UW)sI9zWdTpPb0+jHnO&zG;am`*$GF0kY-{!1B3Q$Oh11wkxN>5m!n^1
zGQ!lk{op_&C3LzE07<%I9i?NLnk!e9hIpX^mRE?mL}iNqak^C3VmrA^R3U!GJ`Rs-
zyc9VOd!>An!}72Q@RT`50RgT94`DpA5CR-998|+ZAvi)ro+xlLyCaQ@T6e)xSf%JR
zY-=p6;<29c;VW~O!-nMAQc;U=*IgfkN)5xB0FabnzN214THfxRom>8%#W&3q<Vgc_
zFw(aha;Z$7lQ_KkaQ_`c$cpIVl;&EPca{LhA(=t2zRr3Prv?v-64-vuvr*w&1kD!R
z<X?k@;CwaTs@=+iM+w_Hebr&xNeIu|iS>GGTgfF@Tol_W>}PDS8y1JU0%k3>;ll1B
zSBzg*Yo_#u^V2-;(FWiPHy{n{7|keK1N_q5fN8;>%O#Nu;)rwPDJtWiHrTPS0--Pe
zKmQ_fh`TzdN_0r{J!k9KU@?M6lz9GVzVs;3>fa+U%@MJ{G-O@wTCquO+<`2bNv~}F
z@S&0QtcCkKkU9~1dMX5t;{_l3Pt+%R<mh06=6%(KM|}pY=|khmq5cIXlrcz`SVN&_
z6GP2pC@x{6Yu$1vct~BYRq|ZFfRQ2|P6Vde9a%M4kX{p`PZlWYCJ3PErLm1>FgsBp
zdQNa{+vMW5(&<MFcv9}-?vsN5qTtZEAiaZq!3$Mw{!H-oXAnYcz+Gq8we|hXA*!IU
z+86Imp{R{el>;=G#krwcX8g)EH|t9L^QEmP@OPq!%Pc~$I<(Sa4n0ipDASTZJ)KKW
zM^6tj<IS_?Kl?Bh7HiTRRDcBcSnvsWIhfjyRKclJ#JO$s(QE&vjc9|(KHq1#%H1&H
zXye~1JLK(HB_8tl6RE}vpz45Dvanq*N_W{1I|7u2!dsK;RRbEEVlJuEX6MX4zDb*V
zlJ7&Kw**<YX(XZ3FtRAv=t2fi4(=E`3N=qQsLTLc+Stw38jQ~5hzX})2AaCQqFgzQ
z+RVYTNR2Rs7pCN*rYMzOquV*$dGP_|WC9x;0?p+l-(Ne3L=owII!KZZd*pVLfZV;3
z<aU7Vd5&vAfAHhTc~NHF-D!d6E#S=E$l1227KEy@-^;xtkHsSy09OZZikIevAV#uc
zK?yLz#4HZtLbKF{?Ib+_K!@!@krp=iQq7WRg!Cag&SH}i1URb2-8^(OiOb)Zs9`)g
zx)rSz=I|&5A*-(WbiI{AF<imlPcG^@n$2YMV27i|l#&Tv!b{wvPa~e49I+w+)@C!!
z>?7<R=i}Rfz(%k~hb~%}PY1z_X$IL-?)#^`pl^uq*k|rm(Ez<`VGB$PhAOT)L@&=;
z%b3tkUr5zD&{ET5Qgp8R;(-_15VPwy1B}XGN=kQ2<>sD>oDRm6!S+^)Om?O4(5x4v
z)McywY<2yqKXKmwZ9a`tA%wSUcO-b$3RM8F6#8;t5cTe@I1)srqF=3oh}j}AFa8=4
z%v7kg9CuVtY<GJ$&U&`b`R`*GDnA4B^Ea2TKS$wHVc=A)#%fT8_&VncCGlWDyCRa)
z^Uzm(l|hxAKIQkCA5<3WcR+%tYDiQer+&lvU`f^iS;0z?eUndiXKu2jbF@FReyq|+
zZE4ux1;W|Pp)90nLQh_A=w0qT{~j0Ib4T-Yiq#t*aq@q=E;0y?5nn*CVk*M--pBY2
z)u+Q|Fhb@UkrB(p78$W*=oHsV%zXs5Md}G4=qi(Sm(!wVy7+%-aSV$HlkmVK@0|r*
z3C95YzdI1K&($FHw*c2S+Za@UKSN0s!>hP@rm3-3XAWU0v8S|QzW1yH>GnslYSQF-
zO|e?Dl~x$Oski8vQ-kkmd2(ZTZy$4iU#J$bg{kzc<)=(~iSGA&19G$8CAL(9Xc+Z4
zeN(V!F(|)fizgsK1y4;h)Va?vyD|oDW(mDP@k|waLAu>x6N+2!$nt%g5(07c@adPg
zUive=K(iE_vLn|!U0avHAXIv+r0ZuywP(1K82UP(Xie%u&iq?cNDi~~ZQWoohNO&#
zNHEZ`?ndoMV|&4FD<Tll0FUePE6w-^F2wO7#0sX(c}gaL?I2X|lThUjZLRzm?fzqY
zA61Z34C9QnE`gUxDMH~fsZSWBXQYZ_KoU7VOh}5*qAV+oWp11YhH*gs=f{VnDzm=2
zy$vyf9E5x4XE2gcX_-YFDFa>(vnA)y_CC?ah$i%&0Wu15qR!_G#m+7jLWZehZbau2
z@anWFms5@h*@+(!cr?>X?3l<P=yH@yqw9G{&3sk&ybe%QV;(`P>!=0k+h2Yg4$WBr
z=u9Ed=;Lf#ql!3Rr%BGBr+zdRZlUE6?DZlr^pg|}w~prFnHq$`1y!N)uen7WiNn8J
z$im!*)~}hU`+TE(?W;tBS<%Wl38$xtHLg+XR=ReUZtf|?6x6KBDPdsA&>m=!t1lKb
zW$lT#`&W0iHpEYUs~?Sz!cR=gzg%a5h&f~4Ed`YYCYTeI9EvCWnneF0gdFe4!xoLt
zNzm=q+11<ETmE#@$B$K08^LS?zfBs<kM?T#A{m~?lwy_mCv5*+K~_rfkZwQOPs!i~
z(i)-G2kj>AlPjgrz2r1W#0B1On@S-a7@>)ui<njhuR8uosmotEIbk=x+<rs_&Do<3
z?@>NTV$9lZXyepKY0)f)Jn$u(6PC_S;7)U@jLNmt3r^n$sh!H@nUC?&uGE&3OkIKj
zOCy{iPZ{9m)t@?$*wNUPNF<3zAcXOQGZ`|_xIp{#W8)xi%{P`ZSgH6Hm2S26Z;R()
zI!Rp0>PKIQK?0Y|Bjlsc>R(|iHjOfwTxIc77X^q3qUhMJPVc`29C3w!51QwgoLumM
z8=1lS|8fkjYmG8uww3F|){vcHrPK#C9<KC?7JVK5i_v|LSu<Nc;ydjMcV^D%q&;A?
zA~o0^MUWpQ)@2O)zZ$%4Ax{-}1QsZD*2}cWC^B0l6e6Mf5O~K3WEoyTCCp>LnmgTx
z{9b6o?GzFpsr}YglCb<};;qsU;1Cu+`Na3rwRBa*EN|6+96<=Kd4nPCkLhaWe-Mo#
zoc^NGqZ=kE=^j%el*7#`qrqX~C)5TN>0>@t!M`zBOY{diR(JQo0euM8+}9Dh^OfdQ
z*!7-nl%~y#0|UTCa<M8MO2dL*dsf8pyEpS`3yQ7=7abn*nA~)2=l3NQlRt&4;x&L4
zT)d}7W?oHjdWT_L8KQ1;xX4${L(0=$NTj69Bn4tMVjvRz+ioBQRHaq_K|z-6_R45U
zY;O8NH%%L>|B9z}Z_Oxnw40bg3F>QIrwc{`KjRz;Lq2j|H^Ih{g&cfd!1>@0Wj8+0
zMlA_{R4xtyMko~<<p$BZgO3XxZ;*eqg{611&_wehsB^32zv1|+P=4gnlM?2j<<pzx
zl^b#?l^yqm>FMQ9Y@~v5uaXCk>I9B@SV!P#2A!WCXEHiJv$wmc?>Hk)6|TNSy}VcS
zW<e2Lcd+|EevS-Ca3g%@*~P{*fU^!@dg*DXMi_Jnh|ob_KMqTQpLc!DAZ5h;#_MW1
zXVW4`z`#FxMk~lz>;Kk3$-hJr1;}5s)K3U5<LDhB0PN=_@4Gza{luNM@IuYqA|fw$
zV=)!e{DdaU?<4@{8WN7cl`Ccm*)5MHDTdGYYoed-tGCdUER;Ae2eg~xmL<KLbS4G5
zEZxiNpx%)SS5FAavtwd6z^DSYC`Rk69}pCoJC`CR2utbuWWGArOvxwr?yd#04-p60
zp_0XiU}jB8FsBo+c%NVTDW#U-ixWtPJomTF+p(AY@5DFK$^4&e919Uh&giK!j0aH9
zj%qF<D+3E9^6zYScF6cBstF5_FkBze2QV!qOMCCV)QLm;0UYG*%+fP0M+nWBD&_$h
zjLj{{9JXdxmf4V=LSQC8mg^=?84pzuMsXrR?R<t!GINwb^*Oi?tL==s7aG1w#karV
z5?`?4nr|Irw<3BKJ<XJDxEYR+n;gsG@?YhKI>wxA8OxUPVX+-Ca|*SA(7_h(4Cyk(
zms@Jq=ng@N_pUH)Ez$i&=&0g-e5#5knl1CeJ{^Uxl3&3{CcuksZJxHc@QQ)PV|HZA
zmmm|!N)A*sS8N)sw6syHP)JwUazmxX?iZyEi#K2F`=F$9PNN>noh&FQ&!vre;Qa33
z{2V0fWA`)#3EBaeohOwZ1jOLA4GgaYKdE_#0)!q<e1}kuIaGHs@-+^Ck>9eBm)Iu;
zP<l~wsfzZeE^FE^`{9fJ2*|*zRVsd;R|=gw+PkwkaO6`07oWcIxDR!kOuV%6_z!AS
z5N5dn?_=bMQ|+a`XD(;1@jnt%KQX23a#pyL8~(2Gxd+gxC%<Y?wm^iShf>dmlOngj
zQd6Zn)qbpx^cxZ*?tS#yEu~xIviH64bw_GRbK(1GJrbFA*0CtvZS{_NjAK=5jPyU$
znr#Gj)Y`&-<vE?RKJi|oxP=+enzX(g9UtaxlQidwsYubmD=O(7;)n2D5mR<JP$>5f
zG+IplZ<>g@^pCzZ@I==5P}2J)e#8j8pB1^OpM=BGuFe6dVBmT6o@o0MFl~1<I%CeI
z!yX5|-oNDRXaoLE_wIHT&xTS+SKF93bfAhiX=u2`JN7Oy0=UIbBlh|IN=p=A>-6N6
zNm^;UV3yUky2VPO@!@<yl;yuCg|M%I<n>$J=cHM;*5$<sDZFR-myq;6(t|(WA|z3Z
z^G-=<rY|4Ed-gX6?4JkU@pC+WP43>gar}6Fhah;bg4SrrMD4T(d_ClaE|>D|Aj60#
z>-VpR$!W!tlth*%m%xEDRNGp#)su6=Qs<u=A6^@0V}S$l_wzZk@dpT<$vkP4@mFtm
zcQ^hRY4_WRWmxm!U55a^*0dNTOh{(UjxCj{z;70>N);4}V@@aHz!S^%5^+@>If*j~
zdt0fTZhKcj!&Kdza_&1kSB}4FbpOhAwS~U-()vPgW>oBJ2N)hOqg}(H^yGWt<1x;u
zKzD4bAig5+7rPf9jyL1`XKjJfFkF6BmnrC*g^wad<0^zeSDJWYhAWqC=p!hDF*{o)
zAEF6piT_JPbJA&t=Y7IDiA>nZ6RQ~456W<6`gU&)Dp7ZpG2O>p4Q#P)431tX%=}PN
z()1^D=+tGNMZf~%p}|Jw7}QB0-KCVX66_N>cC<FRG<zV1T6_4zo!dPS|J1n%C=tjU
zkk|rj5}d=64R?y=sPIW%)FY`^uu*1>U`se@90bz<1J3Y&pxQJe=0DLmdWhIJ>gtWi
zxXQ9fy9#y|C4(Q9{Qh@|mQf6=S;GzSO_<3YKET3nKnqoomAi}vGMRye^i*x*tbn0+
z2{y+VO*zp$ti{SXrJE~6{;IYv!|!>U8CMjm+t49**28SF&oN~OFN9UosX_lDnC@HU
zx|&Ag2soM(4x4Msn)ldY!9(w>>sw@N)DKtqUtUu$-7L+o59i{bgRe(!1!BX>@WNZd
zm3f=SSf%JjCth^3eJ35}XU1yy@YzC~g#2#V@oVMpKS|o5&FWpS>ya`A(J$1p=(|fx
z_`Onc5+CW_k8qDnxlfM~QX>7z!8=Y%xoufi<v#EJFfPAfzpRbPgxA<{j~iA>WQJ9u
z!s+GdtcJD!a%f6vbpw*{u~mShV$#Ga;d+VXd#@z=7S3@(V8!rpC42cG@WmnQu~P_V
zEG5z7#4`dXQLXuM+UuCGs9WcYWkNw&wSrAd>AeFJ^5OEDf&tGxTx1cQ8twPa;=V}d
zr#aa%9nkGJG>{BY`+CRo=X!qhi!xEx{pT9eRneJ$#$@B;!Mnf<1KzdhMMS4qmCeQw
z#_Q+9N@11@aom=dK^46Yd|%(}RgccYJjf}Sp;V(qRAy>HCToOqxE&eesOb-iZWc$C
zc|;nY^o!LMop4nolf~A@q8j|vNM>%JOUzh|XBPc-Ra8<k&y_PH=42qCV8F-rzIqYz
zS-@WD0t+uHmk_PvgiEaukmpqG|4*jm?GpoxFf%ABpboSmr;JPL>DhQe8GZ6f+YAvm
zk1@RGw5+qvYyP>D*1T8|ta(ZRR}9mn`KF6kYkea=gg*ZOwR<46lET=Lf*dcW$h#5&
zXp}lAp|aICI?-x%Xd7G-|HWJZV|;vQv9R3V6pJPAs=vU&9sV0rRp)mEzNV-4BNU)I
zPro$3cJS)3fGt%h@wa4hMsrn=OcCAj$n>5fJg9Oto57iwV7IA?ok9b{K0JE%EKYs6
z^C!bf9u07Ub!`-t$Y6~G?cI$)w0XM6)fx!t>6J|sWu^Yx>+f689RnQovj&aIz<X5=
zQA>fPH&kSmcVUfx|MZMH<O1Fw9@maoZ^`Fn=??x;8iAx^^llzfViYZ9m6jx(yX5Tz
ztBd1=6cXWF3$|JKBtCl8gqSxD@{tp=$(;IU!isF}TxNa(tv8w$T0W>3muF=I#I}PW
zd2KR^3rdGu1l)<tRPE!`FJf0D`lflppI8t>D&w46B8<?B#0%4AG~SNZOtqxnS%Cm^
zk+9ROwa%evfo%)jhH}?$`wqF-A3uDt26Boxvvo(kk+p=Yvg`|Zw;O!&2FTHeLzF1P
zsKUb5I+D21WtQb^-7Hc`#PZ=Ek?A~(1Wz;xy%7tt_mE@0o0X+2<3vz2bh}>_?w1v*
zx5uFVoSOp@bb~-&0HxGW4RVlbP!qAA^so+ib^DOug&A+SAcJ#eZ;yR1RHe2l2f{Wr
zPS~sYc*Hz%ayMFG21CF4GHfBDNuO0X$OSeV2PSNE&bMxYF9r!x4zbSuXE>}@pgS<p
z6)hX!K2=afyStJ)2S54VM3GsgOLnGudRWs>PS3jCl>WWVio=SVmxwRBUZTKbwx(=i
z6m`mMM?D)Imh!FmwT1i@(xw|K6`C7*e1HoDGDpaauN<b-HvQ@F031lF0u?5C?ySS*
zmU)o%A!z!vV$R(L58#4qc5sK-{Nn~u=Md_*#8BX&Ra}bN4OXap4ce%eaTNOvKTG)c
zbZ}@m_45P;iCTaVlto0ggO-HfQ!K5&5fCkFk%rZ#E7md^eIsSlbe%fuO_OiIlTPUe
z0Qz%^qP!BZvGO5bl)$u$inbL_hh&G}f3-~mt-801X+hZ?0xF87swAPt*Z)RJD)s;J
z@tIZU6q}vo2KOeVA9K+WH5a}_aAsxJ1aK46f~Jk5!uq_lxnBwMOj0*?W5ANb_eJBs
zL*ENviww-Z?`%p&P$gUKS683cu-&Ab36%ABBl8MtQ5)ANo)3Y&E0PrXGN?mFU5Uo-
z+S&T5<B!GiV)!osR@?uXQ#OO}tm&ZMxve|yF57+$oeAm>9-35{SI1~5^@Ev(s8@px
z8M))7Eh^?YG7npc9hNlGH8Dh<jH2o06^Mb-nbJwY<BC3iEf>eC%S?+Bx_LX1B3M#o
zR$d0ynMnG@u(#x>oq?cz<tjoh45>#n=|he8ZzJAE`-=H+Yr-Vk#qh^vll(8U>ZY~s
z;IGlQo>ep2LcGWQ=8G(QwK`h6oXwrPm!#NtkXrLB&Z5@;V$B6p{~IURL`}Qx2MJKK
z3XKjregqwxa{dAhnzc(Qg|?I+@M7hA61}J3yu*0C2bBwi)S7`N%JU4U+z+3ld<jIk
z+ijtu`=&K)ik3Q8_rzEhCSvyEYw=N`+y&%~zA`Q#bS#&QfnZj=Rg4lE(~<|l1NjUe
z=87!^{uyzrF6-tCX4j3T^hS;ew!Nwkh!_^G8ZWLBFGWuTvAd8cHh#`dJB&tU1t$_{
z-rxSi4jA>Z*!Wxt?kti2(=ISzFj$xl@d-%uBJ9gmcAjy90IvT9+Z5q1oGZp1HowIu
z!`x}dugelR^?%p>1(3wLyE;3Ad|>y}3X0?lz%hNAt~=VmnL+d45KY7oFqGZ<0`GZ?
z6VYEsFeYNIVxPA~chjplC*0X#6>BQx=>U5rA9Hm2(n3=!3e^BdK)AmO@hLC4^YM#g
zvY0DDXC%*LD$l!(f|SEZ0}wmY+ak)yHy|}8e0-Uhbf3FtF+ZvMIRFb7xITs#^xQCd
zdZWN=A~4#4DwJRF@dvHm(BeD{>=sKR5a{`H@)xrIV^$o3?eHOdxzh)Y$C|p>NJ<76
z^btyYPPs^rp+Adbh?|Y^#rc#HD(VQ=&atd!1z#88+sHzuh8kDkzZF|G<n%?^nBgJD
zq>$DgLr%;lsP}kA)ObO6%XhY<3M>Rm)b>q~F35`_#xbCj_>0<9zf2AxR)*ixn1z#j
zMw;n9ev2kK^sp=rc;0V-uM&L>Nz(X&LPYDc$j~~X^Rd|uXXjzAG3TGKn#M_5Dp3ec
z=_)_$HI6u)jOF^-#sj&y-MZHqLrzqfWg>Z~XXnTv`(I)2B&-}iO<A~#TO%Mzf*G5<
z7OClZeQU6lMm+%0DJ}ze1Cdkt_mhftWj>jxm*BS1={L&U*nwWgc%_o;8JF&0l`mr^
zpma&e57sy*1iTChBjAs=Z@XZPIr1SfqeisiLS=;udjE2Qn4ceVjrBEkZz*u}Zfi5i
z$JLV;5|1@K>tOeO(ED!7Tn_NVYU|K&a+9ALmX0L87V!p0*&db?==7>EVPzp=LN99|
zy^N2^qoTg}!bN0@xoXN8+T8sZAU-aYK{(a`x0cOELG~sVzA8D|Y^Ik`YTI(E;6rnG
zql*b_&n66QIih~wb8D|sD_$r@^p6<3rCZIpIGjg>bqbe&?!eUxVx!*3$Dv@kYurAe
z^YiF%8R#;%jPEjuGLC2xL0a@*hLc^OhIT-V#6oS_GMvVT8YiVvjOEFLtkGwfL7qBA
z))yrgYXw!*6qjjeLo3nVN#07y0l7mj^06_EqJA{3jyi9*Pj*DPfc`G7Oo_FaXJ-l{
zDx6kX&@EUgx9i6F1}*-krV?KiZXM+pc#WCq$09%w4(_6r90W^oV(s#h(6*1k8K1?(
zxL3X$hj#C<u=A@h&cI3SY%h!%m=mrqXfXLD0-rcLY6f_IsWf$7B!2=GHn!*<7_>KC
zCx@IiLpSSe(u&PjO$>Ng4Qlq`eNpn~L@!-}<DslXelusGe={~Lody!pw?PS$8|czC
zjGs9nwvFPtbT(J%gCm&56&m9|EulycnV$nSiHIPq!+=w7V(C2=^xKKXi97e<MG7gm
z;g^TTbuIIf1m>CSlTK0FipZ+r?#LN0^yi3-bQS<sW~ie}@j_f|6s6d@g3d4UGPLu=
zw1m0xBZ&oAh7HP{H`;{?gkeMV9my+9W-}$f6&0_5zsgL+hH;3S5-WDe{Q8x?RTtiQ
zlznYA{)i8gq^J5LQfcmhdKqLOuo%sD)l4}#(CH_W>;JP~^!z0`cu<~Php#HmjvWuj
znGMCYj6v$VU`&7TUhrs)YNPyHlVK;wLhuCnq5xEl%QO&B2rt+s3<TwbtJvPa<q*^q
zF_=2=KL)XK;g3@6S=Q9_aY^-1#7n1FZJ@4VM}TEc7b<fs3sskVifK&xs=8#DPgPdl
z)E?La3?(haEg~Khhx+te>*R{8XEPubbBH1>%uF9vg_xi|QF^esxos1DGfUJDFdugz
zfPX<Fy<90Rqiq=)Q``B7(^4<e;QZ(Eq(?J^Ah64Mq7YN?Ccf>swof{&R2tfcMCOE9
zFbr$z!{ZwdV;>%I(EBF>Z=rr$NbCF&=Ek)-E#e5hcmD424I#eq)%=G3>YTTsOGn>=
zBzx0UgXM8BD%}M?&Q3LzG02No$)Lte+)&?oEat^5BwmXKw>Vj;EISPe{MLzwZkUGY
zRf&2g3VE_qG|K4@sbx&F`7HV(M;_DgH#Wi*JR&7yrKdwLRyB?xEYQ~4S+v%)`Lb_|
z@Yc5g1sYZ2n0KW<tCWHdCqFedK0q0y#$Iaeh<lSXZ9yHE@G+)~m@Pj~d|cC{$skR^
z8+j2|)ZiFjuzC>`st{8XOpGem8^MyTRMu_zv@mx0%mpI44jMUsNfROTf!T8EFAKdr
zsf$ISt5feh3Y+RyeB9?ssICV*)NYxvyt23hGA`tuY)|9%0-04PxojetnG$Ug!52kK
zxRhBKr~CRTSUQXZXsOgnkvNQVU?uwR)3p@NOcRK0!WXeNagpLBrG1bL@k&u3&cc>7
z;_XYGEHheJWug>`yiDx07+b^x{>mRb+*f2{yJzj`!I+L)evF!uQy~}tvXMvLU*D&y
zAlQ4rAO1MRT2bl5lH8FAg!z{xuP=`HqDv4;<rWexYp|Su8`o!G<j6v8w)AmeZ;8q@
zBUDR8Ft6wacoTLc{q%zHmsM$q1d-MS+C)4`uawa)1x*_L)e~iCme)IC(1n4b{Qc##
zb?e-jkof`vK~qcXgK`&g%x+A;(K?ILG3P2v@;^y*-GAYyWI>EBPf%V3+=JqR<U4Ly
zKJ7NA7KEhFLZ0_WeT?$q^dopk+TJSI_NOOmLGc#Xes||5HXZBM-m&zqGa_Sl-X~q9
zvZg0SE33S{5y3w&G#9!1%T+iWbAFny)ythSrhvil>ZI-y{!I?uWJmLZ%ziQQoKI?(
z4XJ$?cn6NPGQJS7bZ-?poRblBDe{o;kJQqr`BkxJ<DY&9@~yEmy9XHqQBi*?exZx7
z#2L*L8LaOQymjIrs<?~Y2>dY1FRu!h=8n}WjEN__zJHwvI*OS<e!?U>APO%%fhW1b
z+4}M*U=c#8`)jJQ>g}7dcFjZ@B-LWQ#~nR3?atQLzHiKt&Z4<dM$KTo8vdEmM~JWh
z^qmWy1hV6ReKR-Tk<X)Cv3m2>2d-H-wa{oix*^(<b-j2_sP;vn$v%H?-8YlhHJ{n_
z#Nli)WQ;otY7@t9(J!;yJS33c2gtlm@@Ro`=0g<5i^79}?7$q*5ikLVU{z3_;5ywE
zyO~!T@?bvC#vEqz+=lf)pVoe00;7BGKMVCvY==%cl?bTZ!t7lmtfs$rE{Dg3Z_T_0
zEGMk(G_6`1E-2SrB3axl0;Amn5>?~%URZ@IcQ*adF<wiD%RX>a(_Mv3q$K+?6~4b!
zlD)U73JI%7`m9JPUD{tBfiUdV**vM@zMk*UZI;r!5hz&G8T(lkHNvb=CrSL;Tu--Q
zOJmf4;x4-r9<&TDzg4;(v8LTJ(8oV+Ca*iwsGa5Mg1l@b!~Ijt`0~#?(BN}l<<$LG
zflnrmdl)}jnE$<W6d{(9Xpahs{F^~<TDcgwxzt|C<dG&|4%O}YG5*Z|5c|e~G=-o#
z6n1-Da}PiX^XE(U*=JX0C(LQ^A(m~m>(i<3m9SFm0-|_QFS^eV``lpU*%_h21^&5c
z^Ct=>`$FR}rRQTVKjG)-9|?cDeQ|wH)fE^ZfL4T){v30@tdG=7UHK30kYfK*h3)Vt
z7Rka1mM1`?G5Ths36Mym8I+y9%d{M#`$4G-@R+u)rhP#j=)Z%iCOb~5+cN{ifQ4vc
znRkalA%p88gl)GryQlH2J%{T&4IXStS^PlH1baNY1uTG-kt3~su77$IfEWUGz+&wa
zo`;89GQVJ;op4`#p>%W_*>sLxuQF-J0i;S~%o&>%%OFWN`?d%KJ>SHobr}e9rY3Xv
znm+baAEm`nN_veX2Ioj7o$QkW-CzeEKheRe9T(mWO|DTLPO@{P*z)-J8VB0N(lL%z
zGruibq012KoGDa>1#bL;tt2r;@bJB|G_05foSJxKIRqyMEDpO{d*r|w25B%W-FE-|
z-h5_#!|sVFr6^b6d^yu*3-JaG&qKetB5JNWq$n&yP-Hx0|EN7Xt3UC_cu?UUP|Odm
zm@f3=02Fkuaq1T09!Q<{SwA#Wv-&~P0KGmrX8{1WCD-61C<VC}_~}tBjtnQf_%F{(
z#M)N8ioI7V$ti#N5^z_$U0Xe~<etTtw=gv=A$}JN%ItrHQvS>|uAJ=`W}=rvv~2e+
zW+Ce*JbGK*ayKT{_Mt$kxoCq~)Oiw;7!N`V0uw1J^`Ke)u`B#!rk_JY370Y@4P}{2
za-D&U2A&a_Ki(Ce%P<}^5Jz_u;S`^zpnZl$b=2Zon>|N2$%kEGn@Q-@brBsKWDYlm
zlXe3{mFNZTP0O{TXk&6fj4-fUm3W+b`08?sP7Hn<HJssGAO|m?xEH#ZFf&bnLLLb&
z$E&(uT5p&NoG-bwc>gBH&;nvXa{<%5g=L%`N*XL2B9MYv<l>2N2q(iw(%aFsv4)r}
z=1;}NiN2;jOh-W~sU6<WHqUEG;lq3&Rzafc6S7GpxiB}4ckP*(Kxi*F?A~XvW4f$s
zO$HL9Ko5Mmh;<LNB)e&%<tsS`T0P6^ps-?>mp~YcTOpxlb{%Dq=*H@OP#k)~u^&Wk
zAzGuYfi1lTtVHKs`pyHk>Upb90s^^}-~~+9C#coev5@>(>&YoWmT`g#`V!a9NW%0z
znpc8Rnjug?Kp>31J`ug8*mrSHuH8k-<G@5IS+RFf@b<4me_1GKNc0;xFleQqGlCfI
zub6Ke5JEd2EJVyL5)9{~vi7Z{+r$zpjXiwcHWB~>K-yq}Wl$>3v{xTStJ??U25oRG
zulg}R2{P?7WhVek?ZsFBz!YNirOq7mDfuhsV8qGsD-7*&Y~Vy-V$cwvGG<a0Lax<M
zDd8|PXa;+|VDRv^ht`vt391`a@5X;Ftq%~2VC(L}FCX&jpD7{~F}-a^;nSx^WmHTf
zj}q8UUq~fzE%0M8xQdv<ETI$=rFlfJqg;%^S+5*5fMv(s%Sy&CW7}<(#MBdu&oSSa
z=)ZI4{&c8?2Tq~yXOsVtq@pDiL}ht8@-lR6kC^Wenek_f1OFh|wFJt4UFMS*)CeVW
zuAp%BbcIc|1G{a&Q|`0`wxoXFF)))VjE_D>l|n7l_Wk?Yl!R6u=%&$4Rc3b`lwS$K
zM-B|P1|xjNT^O{g%PY7<HNR{?$}aK!CQbtp1G>>vi9y1}t(m0q9ftM2$*ge#y0Y9d
zk@?1;&o6E7PsVu|_QqOk>Hz>n-T=4O;!p~yh&*Zy;VrWzaj~b}4N59Row#5_8^}~9
zgD!nd%L`XBBvz>Ps8Ct?>^=rbvb#ECHW2%oN>@lZB^mbsAKUw%V7O@fC1y|Ai69g$
za?xO`5sKSbb7(ynt{eK58dT_+ylF2!TIGQuMzVqYerBoWAF(QS{wb!0LDxM<?1!<s
z3HpceVx>r#^q8HBK5o~INM^zhu1Pq14_+bauO89u%_hxc;Kd0qfz$gz4UM<gY)skV
z$3kur;1dQhfs&^4R@SPbi}zX>n6cDYt<IhLsR%Gam;aZrR#2Ekm+o=$9||fxa8YC4
zb-f?v$#0*yfJNg6#KtMdAl-w{br%%_g!fdmm0R9gqZB`xD%}3Gmp7N?JJ!9Ny^IhW
zMW;q8J{tO?G1LJYxT}~SVq7uH@LZL&9}wvA4{Uz!O^MDX0-k&L;2+$AMg(0AfD1J;
zrh!0hF&GSGQxKJvha@Gg`7r}V`R1>fubkI~?2?c0MkXZ^*WH}$MqUK^1r;|JYJRX|
z8l7|*-;uAX!RFvqv}j244A__}H{5`LWjycE6mdSpPLlf3o84(U*`o1R7PAkG=|*Q1
z*bJi!w_I{2(rz8}E0%&iC>F@cOtpK-ySbm;)|d2OrkwTLlNGn9^(|Z`&dUTzbnLW}
zl3)u(n^y7{_$T#1e)r+3rfAbH?qhd+_mTNb`at4nD-RO^TKNeZqbj$?7oKK29Ph|j
z-fu9(u}?&cw4cHU?^y$bIbqN?_0K_?S=07Du(m1}Elg`@n;KMJr<(;6GZ;e%3dPgo
z(TWD&&eE%$=DBzPmEmk5hq{~%$;m9ATvq_e`NbuR{dKaS`@$2WVX<uc*v4V)X<UXf
zYY)AUkx1AJCzQC5voN<x!1ZAdyCS2qg;F>bo>7$4oro8vw$=L(y<(ZxTdw>Q>R$6+
zD3||7anSex>iP2+9(8=vebT<RFYF#fv>Hefd=F@y{2DZUNR^cX=zGb@f=)gknln@q
z>G~yfueXQtyc@5val+%9OQI55B$E^v>v4E&9Ml*$SLhL2{|>Yhn!=`#^u=%3T>|RG
zY~jVB>dD9B#-J>;SER9NZRcLB;$*dEm{RIW5BPr`7LX&B9C$rtJ$(oYatxG?x#;_k
z2OO#BqT0BELM)V+NA`?{w&NplT5b_Z0<@bysTPB8>BX>}g`*c?N3odqEV9Bf3LwT9
z_+@CY5J{-c$sa%0?R=X+Qvv*UovxN!3hNOx)ulV@e8utoY@{JABy*IPo^NzaCy3)C
z|9oTWMscxsLV}Jkb#Y0}Y=~*-b=}Xk5mGZUCtc<5r?Qz?$6p#>H&3<3!?#=FzU4ni
zYr&k8czMhV_2BawLtUN<D)sT&@1@SEoz+rfI$XLsf`cXe%p?b1m>UL)pWG1zaSn&8
zMzFY7!oBE6$QsdWk!g2yNSyxU2-x_PdcR+2)o}5txLDB;r^E8JE&+%2@)N1pWd;@%
zgEV3TiLW_j!68rR%$8hAH=SXsIG1k5*}qf=-3TCcgOesnzISjuC*ABX7Gbh+1t2Bl
zuhOC&qza(d+QzF@LZtX+4q7;E+eyQg+O1|sT^I6P=w@b{SCMAK$I6k;N#jo5e7yxV
zd)ZDjs&fZ#n7!a{DK95c3~R4V^eCsHpo^nW_Vmvc1B^SK!C$=%u)JC{F(_&am)}80
zepJ>ze}bf-$3tq|pbmr~9~ZX_<{VN+T@VqhNlVM`FN2}sEU4xsfsf~_X*}V5N<{yP
z1Enil2CtYAI*)L^C4=glvDBCgUEzpuG2UJ?v%@hON%U-Gr|XE>xw3AO{8hkzK6D^I
ztaeH`4}NR^lrjK&>~u;P6ZXdOXAm4RS12VoEXyyKB$4>nEDWnq47NCM8b8+BZWM7N
z=BwYaq#k_QY7v8D_5U=)_?Mx-cIX!6AngTmuKp6VGkpdHC6^e8&){B+ttLGTfoke4
zV+D%d&4u==EY$zOeC8|X2pkr-i(A&(sEPLb;=Rs4H&ETALhp=vNI6|~qz_Oy)_~;K
zNak&wj6isdQ>4<1zC5VGv!A8leA&Ei#9gRIuL33QZ~bPAUK|w6bl>q;GTHXd=_Bb|
zsooOeW=216P{#cS>55EMyk>TW_a`>T5CXu5;?C6tBG|-x(`5$)dIyyRgI;8VSA%LH
zno|=VjSR*X%90i8;jP1ze%mYPP&+awx3-)AzPT|BiGL8rCuK}2eqK%ZpE(esy~^k#
zX4d%jQyz-c&Mm<_vAU&)bTJJRzrcTH86x*Aw6S>1SLqeo;$lnhRz>yj_&bIQX;!XT
zb#l<ZsudZGSzF`Am(^NmR>pPjr+E!B*P#^GEzB+J>B)B3P(`lnC#k3XXm&=~CmdH>
zs1V!Vx4og)u9aWsomKkjU<A51Z3tRrMih|i_vjYEyMOWe=qSH7WZeoQ(lonajL@Y?
zS3&A%Ff(kQl(%eYOmJ-O#s4b{-MG;YRGuDbQ3zIt7`AJuwHtMERsiB2kWhOEMm5<$
zL7KKyF}#n(=T_nT6Htz|K=?@sC17(?$luB8U3iRVrT{+E&+Lr_18@n&(h2jSI`?b;
z+q~Y74g-S53L+(6+$ks9xe%St!0Vr*C|+eCz!1054=1byS6A3dZS_xI=?z#KT(%}3
zn}cW>G06un)!0M#Hv)fC71JTUb(867VGZgD<o@otFXp*!cGL*ANm%ESTluRy-6wp_
zOw>2X=k=~|m=)WZ9a0+_JoF;t7`Wa#O$Y*7jfGtQLXu|@Jt;cSOhieP(1g0pH!iKL
zyv)t}ZHCm>Fee*N&PW%dW@|3>E(TThLA+L-xR{i7yo<OM+xT+i8XaH<SMV;IzV-a&
zJ9Q|&936-v{e<MeFzYJHE3uK{szRt7U5(l-IQLDR+rC4XA#wm>cJyJ5XV?hlP#c2i
z+hz7;z!nq*DZKyvVRNxcFk=#4jQ|fB|JU61U?uFc5mSIidSZ4Zo~ZNl5W~6u@6pzl
zSMdxxNZKYpPCM*n%pLz1i4azxnqEbbr*Jj5)b%s6Jtkegh}<^f6c<Yi4tQN+tLxN^
z>0ePZWZEbbEX2Mgtlt(#E${mpWGYv%9P|EGeRd78dEzb*oDLN?0cZj#{=?E{102#6
z;$VIJ^cijnwU#B9cYnZvyM8@%0}SNHecUDpoHA2Xk?iEue>VtVGj#}69tV*gGmLj*
z6nW^9vmOa42D|RCqUY#0D{$6soY1X&Dt(F-HBQB6f(mW&#IaE()>g;aT6{MGE7=-5
zNs2{rNPa){AEV3s(2El>Z!wH1{;>cLGqzD(IXK9IMs6ub4-Eyt1hK>5<7T%k5IU`k
zJ#tV@a<lQI>+4L0euRbPqU`HLG{a_X9iy#gi$xG<S$rFMzlhBBVrIZ?M^07%wBr$R
zQF)jA2}zn2kNnByprgR!XlTI5(?G<c=#EX)S9k4v_21I7oGL%>sHzwk?)-x&5+h=*
z_jmra=E$W2^}EQwx)V2L2{A+Q;u<m1j0^XTD2CjI%yfNukZ#4@+$@zQ-7<FxU`KRr
zx>AtQCvP@$XJ(xUM!hf#6C=Ny{QN2xJqb@=$J746+=W?4s;i%h&WEH-t_UgAlEr1h
zQZNO(v{=3fw>8u>?|lWkO2h+fA3nkHgD-#o{tbMeHu2f@zfg9Y8Q=YMM!qY2cbZlw
zY<#RZnIN_pliWeLeR?l)4jDRV*<ScOIy-R0D{NYu2Chh>52`~>azotp;c{AVQyy3m
z3@-G#C<x9;AMtM3aW{&jY<ktxtfQ8*Fgio9K{jsOe8N~s+~qVi5@83CZJ~n7H;Cs@
z!$hWpZNK+;T|=?SYGlhNYeC%jyTKKlLm0`lHuUYcT$KdF%^?Q>){JO*#X>1r1{mj{
zYBRiEH>>ou_pU*lB5xCN5YAu5djkO*IP=q!lT~|C%jd~!Ia*yU+K0L(MoW#XLa0BK
zjc~QV2duIsU<#(ywVh6rDzFDgR4~~L8o=Nud6a@n1=RVSKed&QN7dUdHUg$;M<3U<
zLNN%yGqn|V+B9!~8CL2)9sy?nf9YTn;sZ8?jMI1b^58zHW&C13cF`pE$6(-R>Yn#2
z7k<}>YT>`E7S|k^F#S1R_*ipRoaGAQkjkE$tt?@g)o>)MejK-jchIGSBVHanhzSdF
zOHHa0*%Uyk0pCHvw5~f{$wcmc?q`Q1wagby1=ELnXeKNI6i9?B5_2_7i>&VA)qfCt
z2(X?4#M8ooKz8@3u0;@bjpwbNJVjMZUCN-$oIqGHLQ{KokCOs0doKl_*61A&g|Y-a
zc;iaJ0&NxCf~{FI7j6Z)?<ZR>(Qe<F?)&Fup6R>!2GiCk0*4HJ60b1vPUro8(e*l{
zmATy37&wAxjMIbKO89lrUZS@1nM<!~T=%hd5U(Wgdq82u0DlziiLDiTUucPGJxXa=
zVyECxb4c%0GNGx^?@C_76*L5d;_}wrJH|?=j26pQl!c65e98u)>{jd4gMz_KG4fCE
zCaAZyMs~dHbQkuqRv~MLiiGpdLC!Iul989~P^K5Z!aHs3Pja-!$<prkPk0G1DN}#G
zMX@TuC&LmOuA9QZn~*TF!oFZB#LxCHB-l(R8B-ELcnU#fFmSVHFxfBPGvy<11s;}n
zqH180j5P}%Y@sw*7IU_Q=u`#^GM{}&Y|dWGaKZ5h|68gVSB2SInF+A0Nl-5I{8$@p
z+r^v0?kh5rtb}m9ua9cUiV3%q7c||>QHPJV7u~$QfNxacYLPDmUFy*@1Js*{D_bP3
zo~tEkxdeEM-0PnU%SAIgoyEftN<?XDV=9vEzZiH&Z^c-n+#Tab^B?F1-IX!Qbh8mD
zj0SR<NB)}A73hIZ5hLyW-x3}GT6bW-M0Py^>tS0WnJ;n=d8E)3E1I!O-<m+I9t9ZP
zxEfG?@8es8b*x|e+mD7m)=qer?(|6`AqR&<sifGiR(;O)Q9%7pe+)*-tk|w$4^R~K
ztcJ|_Sb8w2DNTmUYvuTs%(|TmqGVd*(Q&j>ZzdYfbpSEBU8&aJ8J$_lYWLhKz(p4`
zG{xJWx_b^o#Cg|?lc_8ykf!o8gndjeQyqI+GnMexsdlUfGD-+fYlmI=94jp<yYT%!
z5oPr_KomLgp0237K)Q8FhW=M}Ke+h=r|~HF%uenU+$W*T+fE9~HO^2@UGInz19$ym
zL3#qANl4}q6>k!oKM0fksbh>SXULtH{`1q6S`<&3L0Z);{dya2O9x-bg!A(JQw&Vt
zCErZ?MLew)WHl?iY*MHiB;ecK?r<V75GSi+{N}d~o{mke2>0S8H!NR`a0700H>Rxl
zH-IZ?fBHzcdj*l6Kyft?BiMcj3`3>68@7&ivNwlZr5<(^wNiwg1&TC-?6XKa0k{o%
zQ}XEwN2^OGO$*B^$sMCMY8-C&i8ECAhM`kxK51K7l^SJ6_WXmYJ5q1pJEA`Ts-4Y4
zHb=b}DrH}tY^3~%I4((h;)n%hW@uE!^U1hix(DzK?LpM09ozp4r(Xl~i@_Jr;`Of$
zqnZ(qQe_vA?a={Zg2fz!h%JMF&y~SuT@f~7gb@pIZw$&kV^+N4J*&(aVi``85j<P|
z`v}$_Dd((i(_!tc4nXo3x8$B{SW2g2Sps2Pc|I~4qiJC{d}yT&T;^owhye!?PJ~_M
z;dhr|69J{Yr(O{>CIvgW>NS`%lD`6`RebBw{1G!M(NTRLY4H^MIAA0-iayvg!&{2D
zY8lB{5t8g1ssx6OCm$|~e05tSyCFF!sB92yy9OT=hM$(uC<Aqv;r)EC(y%p~GXDi@
z3k=tP>-&<_GgUAeg!&sv9|=Gap9>-_Y3B~27|0pwv0O|@;zcCAW_6{}R#KS2lqM?E
z&rSVwA?L%J0sWU|jO?>T<X^0Jk_wnTd?J}IMdKJ4-&J9yk?L0pTj`joP)v7PqcX9J
zX*VzbAyGMpx(9HV0*A~1nmNX^U6XGhulRN5(4f6@c=+f<N2Sw=<TZmq;SwhN9Jc;K
zs&-vBJ<6E*A5{~BczE<9-oRb-?434~=&b}dtzad&W`m4yJ8l-iiD}NFg?*a*ii1I4
z%oSs3eq|daW(2eCp7q2^`>dub=AVQDW0x3lkWAzwXLZ~6%z!-+?R0vPlp4f9T}0Oe
zkPF>x4d}o!xm`gkA#FTUBBpk?sApjuf9AGnVl@y&e^LM!&e!h|h8Yg;5n8%5*8AD0
z-_oh-7SN}m_)xcaknDCelNU2r+bqt&lO=FCAI;kpgA~A<%S95d$f3!<B>NyWgUR->
zbdcSLOB46?sK@If6(rr7N*bsnQKL`|>8nc`o)(pDDNVP7A6X*2Ai;>O$2J0?ctP}E
z;wGy;NFT8%hoS*p*OkWnV4pRtd$-{$V{~~+WDIUT6gL93zdSoWmtYDuz2F`vu;dK^
zLe)&%So9m~htQMVT%rvnqANMhQDV#PDZBwBa+yJUhBDTx+~Y7@3;|hU+J{kHFlwS-
zbWaTWq!$<37t!?vAu6|t#{$@a=<UvnXBBT1mR-!_tfq_-Lq^f8T9jXbv}41Ri=rB*
z&C!TXo}eG3{keM2cNjt#$ZJR)vKh7lScWP#5TV_Zk$-|Wu*2wUotu3#fZjZyN%OwF
zt@d3aufnAGZTgE4kT6Yaw=>3tWOZgM2bp(RlDX>7r_hX`-?CD-_VO5sXw!ti=lFMs
zf2aFv+dbo$*N#!@`8B81l@_)WS9Z{PCu8Q19qX-KdAvr|!JBxz_JR`|qPt#zMcN4-
z3OP!qU9VHG-z>8lFpwq%^$XQdx1XvcDU)e>F2f4r$_Ceo_t8>g3+}YsS;{hhp@8um
zzuN>Y=G25Jxj<WkYfHSen>2bPP^@-!?|^iL;?fYW-f7OS#(b>9c!;Ki5nZ94D#CdP
zO2z#6lYA1gePFdyL{<IwDOn|VqI}>Viwt2>`4)(SqMhI#NB?k`hE&UR4odajw%@M_
z{DUOOYF?Hrz-*>|6-Xs2#1eG%jQT(2=YEJo!K!}uESD8_l>ry=TFD1DcM>)NMD>=5
z|MQS#Q5{cYK*wq<=XTd&CWhqEF$V6iKGKSb=GMJr@|vMSGulHn1-5#?8$2C^23IrM
zbAoJTun{xj*(hQ7@nQ_EyR=&+O^-z<y^7EWd2Xv1E4oJyzKqDl5RRQJb&aVM@6hi=
zO%Gdiva(`G-;>j8bJjc9B9%_D;s2OVNmL9y$WEM7;7<*1s`6>n%Y0rQ<}hMAo5kAB
z1r=ucrmCRJsDQbBrWZ7C-T(<dJld1}aD7oN#I<|!6S`+<P2ty#jolnK(hXs~%xm#p
z?(iZ!#+D;>H}CsKJ&U(-Fdkg7N>4A%-#-&h(K<5M;-1R6+L0;AzjF2!r&SS!l$7O+
zryUK;q^h3;ZSP*kN@J=(@I_?(jMqm>Vl-zQqh)xR4J!L{A^I%qgTVHPjEzH&b1RDJ
zF!P#E=NN#%kxuS|m?o8M(G(MekJxpueCWYrwj8hHtOxU5`O5Cn0wz(E<Mgxzao(UN
zDmJ|iTTd)Xg2o>&i#4UxI8hS&@ce+1VXnu;06fw`9s$!nhDVSKeQjtu+DHq8QrIXS
ziD%mpK`3{s&CR99AE;?|b#dJd(NP2a(8E&Us;f*MQCpKMv8P{hXWP7yGJbP;SOdr(
z+)c6vOF+bvS`}`Z$RSY6RwK0|Pc%cALN5GTo+H9aq|FQg87H>#_mHY|#4AYhwdhXT
z!0<?*z)eYSnuY_?#0mr$Ih3G(=MTAxfEqtnNzCB?1jdKN8IV)Jh*R9$S@%cli*W|9
zqsI@e%~5~jTlv9!eQ*%r<X{XA^eA@KHPX*BxA$Hp^(E#sYvU}_@(;6Qm=Z4KWLbtO
z4gr1?>i0WWe@7eFO<7Dbtk|vy!Or@RB+uJ^L9=&T##wD;b!|JE>n7lq&;3O@?QtnG
zq#_sL-YhZ`3o>RHNp{M)X5P#36RI?QJbec0({@REZy8}!d^&6vvZV40<I=sW6KC8{
zIKTmWQQe$=%zVt8(-1jZ*R=l637_)pq%MDh(IJMRArhSYo%NZjDg2xEcZgCRZiWI^
zOa@l%1Dsx~I#l(`9}@#>O9WemqFxZ}=wUcmD1i${DB4>G3$<N1mG;tZ6<+RaoLY*P
zgqkU`elyqZAfG+$3}^iyw`FJgTa|;A!#snPfD8-dLGjO*rhse5UL&vV)$CIYv&Utc
zDmzMFAL};h@+Ywze(#g3Ec$adQ*XXbLpLCyXj^`NXOOscR_W@XwCxRzVp5BXY|_4g
zs@@32MoKt5rsLA7a&wd_p9VCsH0vtNbb|^k23FVs1^%Ap@gD14aF9wyXAkqF-nEwk
za8s=UvI`fLK+LLIJFye-|IExdffWU5EiLt)MJedLcjo$GH+-27AD;<JyWyuBo9nm+
z&I!H0p43sZt#k&sC>a2TrRhbw>jT3}ws8TN@l~#v_K2R_3Z<N*GF192?SR_6!?rQf
zSu306DnGCkY0h(&<iaGisFr#ea`F(cc1q9emiq#A3_vVf3P9G`g(ym?J!tlZkOUD-
zRxufFWsgCfzfQDZLnR2(<*Y=qf<nN%ExC^0K>Sk)GLgBZQa%^O*v_8Zc*G2#9#dWK
zwGOd?cNu9?pE`tVXCB3EJ-EAk1Pa_^b@A+Xx|@Wi935R>$xM`<Asil3y!X|+Ya{4k
z{u2~uuTCWYn3pOs!LB%ip35rvaO^vWp!Tkiq%9kZvjjCHpf&0aQyc!O<v?sXsmUq<
zL9bAD`H1=2B+p$BHer`1-5d=d0N?Dg0q|}iw0ulPyeO$s$B>k}Gm;2l0jp4*rPgF2
zWOAa=#E}y~g%f`W0av{eS5eQF^dR_^h*yfbVNkkVAw8|2U0-uCUpjRCB;2^nb0%wl
zTk~eAk1TU<sn3)smXxl1E?E8Myj#!rtH9CUaL|kD4`Ei*k6Q1?k@JuaIM-3%lmV0*
z<NTMTleVXD6Qk4}Ju;N+(!}Z^IoAOZ-BY|h*FV<bs@R&=dU#+sB6y*so?cIs-%ZcM
zFb)29C23M3{SK<NCm}QtJund%5y{nNHZqpptzo9k`r6(s-znkVcK@Th-}sFelC+h(
zRdR8<_f<_Yf$cJXhwG~q#n>aRXga%P2)K&oYW`F_`NtC!7Ky{il91cf<wu=w`c8yB
z0V5ZV21xUBL<%qQ-Nnn|L+3W>T5MtnD*$cc1ol}bUB3@kbF0Dgt0&58s%}m3*)&?5
z(T{;F)BpGinq+y<7xZ3$HxR)VMDeh`?V9&^{_+YCgjsHUc0mI9^#llL!yYg8L4>6o
zNeP{$us0E<yz9-mEdd){)xx}@1}3yubvD&hefOje08(mn0aro?0|II67t4#rLHttn
zvA1K~sWmBWyFb(B6+!hagUCqNUTB?9KS8%n99HZio%RH}sx-H0;Q(?N@CT;#!3z;Y
z3bbCRPdJ-US&Ab}H->D<_@u<JX4kMM{tD<T??(NAE)w#VOXU>-wK2M=ts_{{2BPAm
zRW<f9l^;8nnEw&UFnHW88;yf6HPIvdN2$^U=#K#&ET)>1&;$7>{4R>w`^uO=Rl~*9
zGA~ixg14gmp!?{XW-9l#nRsNcZ-E&R^UorGEsqXj$>ICrichH{cIBa7OW^qLnwah=
zrXYnfiuHvrWJp;#bT=8d<f5eUj|?G{)<AWFRnL^(sgb_JnJjD!GIK|XU)!&w4E?zJ
zu2f)reOm-c%>3*{h&>p7cb9)w=sto!Tt-CGY5F(*oJ!0i8^_GB$yZzkBC_{?M_p?6
zUx?_M=ALX}a%wAf`*;PkMsU%ZHKFl%R6nF>_+=$KP&Pq_8G1`g?h^JZW4yqw*pC$&
zK8glS2wk0-En!ytTSH!u_J-NuPRU%-f=Yk<afu+5s2ZkSp|-7p1|TB)*IMOgq0i;E
z)@<HCV4>Q+>=c6J!@YR=r*E0qk~d)^r`F93=1hLFyKf+s>+ZjbOSCMvKT~i+-8_s_
z`3dsNboXv-d#nv|kfRxidD8F0k(FQlPkj53%0YW>O2GaS5Yg|0Z}bkciW#;)Qt4(o
zfJM#49hyx+%52-IJzK6H&`^2oK<~bp@lTZt4qBwv0xRl?vgaX)HoepHjz@kwxva53
zva=NQVdQI2o0inPwy+3|s~>>eas_oD$n<y^*Gl@-kHIxfmLQTxoJ}o9-;j7BqXy%X
z`F0cUDW<Ooaz_UTGC-JRTZXptoE^W;s#1b~{wQG&QkZv6AiHp%l1aumA4pLSY|}+q
z5sq@up|f^PAe79ajeV<sLIyNj$ESz*%=X;96@^Wy*~d`I!m@Em5hp@@LQPc|R)+en
zY$v>P)oi^iYVrX#qie{nVE{~V+%v^=BWSa#^%i@ENmCS2aO2?X#;!B^cvQ0#dxJ@4
zU`6R4<P*rv0KQ=C&~#fKi%y-s**km^nxK;(gX_qSX4z5H|IH$Lbp$3k8(Bjl>J2<o
zieyb43ecLDDHQ8{-?b=MCvHSCiE=`l;$MalFyR~a(ZoW7C`#^nA{@TYrdNF=o`G?(
zKjdG^&IIdbEcyR)(2(WqR-fmck2p(6U;7~FBFd91!hpN!115<paGW@k22;DUold#o
z3n!4T75$D%HWJzR2avXHue_o5o<K^t!V=LB7+rP3&&%ras$V+g*3;yB!kHDqC(+_K
zSFI1JMu--d8J%Vz1y%c)ta3&yJ%f==Kuzcj&Tt>(%76Qeur~+3g(P@18Br)x4?H${
z4aww$g2`)`q~2(oiv+>dqWqP^iaw&rxc~aQe{cXU8c|j0JO2?}M1#0Cf^LnGSObZ9
zB6t<Y$_89t?Z|`Dg$<1Xv9w!1S$}Hw=Uls}ThT!wg)wnBBrO9)LmJ@Gkp%Ox142@-
zDiwA%cPp%zIje2DMot{v?pEFKHN4!}K>lghiQy&2RR)B8^Fk-)yq~yZ35PYj&b-gW
z>P5bZ@H{-jwoE1usZCMK_(GXuaA8TZhh{5GjWot5IPf!f3M>z8AAsI{t7H^fa8yIH
zuwRTRfea#@I4SCe<Jo4~r-W8v4z(YlQ1635+<LOCVvHIDSUsFLm)rP-4o6<TjnTSY
zqZMlFnrrUayH~FqF`p{yY=W*sWQ1lZM-Z?%^@T9M%Ele3ce0Efqv2hmgh&kg!}UJH
z-uHEN3ITUK2Pr~4+++uVj%$I$_bh(PUY46M9rZ6fsQMD*4ONGjbVrPzT!RCIAZ>JK
zQf?!A4`F~_uFPJvLlY}_Az>-I@lfYWfU1kK7n5YQtJd1Pfe2Q3a_^AH;)c})cn$?N
zHMT~cXOOb>pFcu5KRW8Xl?}y>opD*tA1ati>j>9=i8+u6mPNGrXv8<Tuntal?8+L&
z0w{SQ>!I<KH0kUWg`3+3G5tbER{a~wK8FVWQeO6aH*h=M&|JAOrdsxFhWMvor)}U>
zL2pe!`f#AlF9nXXLCO?VKO~V^u+>WXJ@Vf5xm%|{doJY$@;k~0wrq7=g%wWmp4{tt
zbFWgO$+YO6ld;~m@+Uz}lj99t&lbL5>Gf-7H~FXp#<Hlw4cC-W_j~vq8edKn*^2$^
z(y{ajNc6I(IvvLnxvDHkQmR5{iWXn-^bn?l-AGT!)zyISVN4bouS=(S<N4dXO=#Oz
zOVu^_;$#ID2@q4Lm)<t2+183viISP$51of#Xy1@m+FI-<@+qe&C{q+77wFMGapApc
z)E1A%VaY>f-VptWk55fo=iZltBDJu_@GE;N@XIT~$w5$=iO%w@c;V?vfKk0TK}cr0
zZ(L%iW~>SgZcD1uhaew>0l#db?FPRU8{>BFLie#EIcX$eP=mg6v0)rJK}LwJSdaks
z08rghz084j9HUi@#FSjTMnh9dglwUh7T=Xi^YWj)xN;b;{VAhkY2!_6fI&&@%fO7Z
zyKf?)VqUZ&WWnoFbl<x}sVYG|52bCatz9;c^i%d2|6@=gdx%vEy#P+@vao=v|L<*X
z7VLo>%*M2K4}NEP(PC#H9aOyN8k1n<%xovFze!g2!=UY7Q}`3q3~$Up>W-w4priMi
z3-o$2@#i@AMl6VqoFKEU*X{)DK$am^QWO_-Xx%tzoldd;#X1{O3|_4d_HA2<dBZo5
zeg7>pzxw4BaoSC58Jm^0%qML&XA`liWMLChDhxm&iKlu-M#@T!2l0m2!E6~}CTy2S
zS`k|gHa@e#s@+pSSPaI_*V;5Kz?6Rhau`YzkwSB`504@m300s<oxQQ5+poyP!%jNW
zTc#XAms8Va%s7-UcxR7(hauQ)OgRvglyj|p?VbwfKSKGK`(n6yFe63$u;rb{@&{ey
zRwc!Vjj_|NrL)D2ALFZy*iM>jb-$uP9vMKu@sII~31%rpyt>w}`@fo&@%Ba{09W%o
zdNY&b!PYn@78`sTNYAlS8A=#M*;{Rl?E^kY{A)r+2{XL$X~y#`&f?*lW+ywx$JT-I
z)^T9K)Nou#-Y?#b-9K`Gcf&_vHs6Gt+LPuk`V6P(kz83{<M_RLKe8)qBXljvtrm!4
zv54JY!~L)IU3rCREsw44gfrDy;87ORa$WTV3Zv9NJ^y(Gqv$9(DI3~;_~Jb`PeYi6
zG>tpVYB;3%=e}tc`dL2_*I}UDakIa-Uu;hr%JRbbWk(2Kx+HhlCWYZ17trjStH3B>
zVM?SbDIkV>VbaU&)EJrjW7Z)QpOEU7V|H9~m#16DZ~`IeA0>+>`Yt&y!+C|tR(`!d
zsxG?l?9hN0?VyctioP}3YZ!y2gTCx<EU=OB+0ZPyzu6G{$_y;DBHL5(X(WUgkEOTZ
z54S0y6evVHE@L7XKZ3V03oa^yyv<dZeaRmzYFk~7j1H`-_O?yjIwS$oRN=YZoYlXY
zs5>x}l%|cW<HFSsD>f;wxE1D#_O%ia>`9uTwCH)|-Efa_v$!NbO2)dqF>mrX-9{ui
zSFT5x!tV~7Tg)_%+Cq$Gd~Gf|%H$ULVLtF{2@0nScBYgbhY^@@Nc2)r5(uU?#}TZr
zh7T=M^p|sr?;ZDTaE{hZp)7SL7?A{+FYnV%NFF7TTv;rGdZz-s+e~q5LqJzYIhgsz
z?s%Yn8kUL(!3;ucTmw|&q_Wc88I_`7Lo+1~bAXrhgtdUcAi8r6q(v7w+U4evCxM<U
zh6oeSD&+5uY(UTaYQxSD&8K7s#jp~=wu0Wy)4^Whi%L;KfTg!YWqs<~v-{OQ)dK5D
z=2NRl^l(;x47T2{#`VADswib%A3Ucf$0?bI66ajm7>rmQo7$q(-G}M&6VBExV!tYx
zOEx1T*!&;Ktf2ZhRDpYgHtmXb;-t-Bss0eAhC-0;OL~Aoe4N>zEFv=PF}%j-?ydsi
zq%1`9NXt?t-r{%Ts&IwheVLUgT)?+<+{l-kCplqYaIS%!seQ7*o$TSSV$b5H{)#r6
zIbE(eS&mzGw+7I&@*4y!{&NitC1#gC#5IAo#$$hsw)YGp;Ad*RqY;^zP{6}YLZ@rx
z?!073?LROJLN`N>mb}LIUSry^2C*kNa;9SmZ^T3m#LyV!!b>X7O$Sa*5Gesr+Gp|@
zVJ3`zo%8n%#T8F!EI^&c>5PVxa<`Fs1l)~A)4QXR+3^Z@4DU5gtrSdY^LXB6U<!P6
zhm&VNZ_i_2CqxXIv=WSe+1|<!W_$i%E;Y^^eVMx9WB0U~x?Ze;L0aXhMM=IJPr2?y
z6mzymLH6lObVSn1=nd!^g>!RY5J+VXSr>+{jN8ovd@oHRTi})=1KQkoZy^(k|0vt!
zC3#B_#?%{_=*j@lO1n>Rd1q5M>ybPw=ud7V_6mZG<9!uuA#igr;<KV6nrx1}WVUVb
z5G1<CDPKh;<XuhOO}hpWv&ghpV3);nD?1i7yI`G%uc?qZx90Ew3@UUOY=^Gt9qE1#
zSG+sY_rKGyQYDH<**nlaO+U<;=Fg@6XSpAjsf8YfVFv)js_rKo-(K8?LqeK`^0DXo
z$|wH4q30yWPbp-}B4Q(M3khM0M?o>awf|hd%V~SbWJ4B@X!yE?)kn(ru=NGZF*G5)
zTTR=+ijsv6pERQJ--+&miPck*Wap(PLiIV&q2VX~$i<K%jNfU-DDppUP(%k(2c!I(
ziL$=M&)9xxSk$*!yQcd^^ycI9Wo(%r&Se?V?N3lu$q-&2NXf|&Bm2^qh}HGPTk}=-
zDcj(_=2CLqu)-pXc2UNAYPGpln&G2-RtXYu993E9HbG!Nep=Ir5OT=nc5BZXt=%K)
z%#}de6jm(9`FRt~glN(2+@)R%{FPAIi=+*jnJQ@4BQ2GwD&V~svYJJ;>90<#@XzKW
zQtUB-??Z>?Q?rEml%owbC_>S+G==xOd43K7^*cdPvQWx7Uz02VreK!#NH(`Pz?<^t
z*q;un;I1|{6>q*FOOd2$#aS$XO8DiM*{Eq#{J;!??a)oC=r3U;H|j}t2~0~;H07pQ
zi_HiQqDrEM@o-+pj}kaJ&#&-NF=Q7iGMceT-7{1P;Gbh*#w7j2Dy6#P@*5K%g=&ow
zsNFuyD1oJe=Z9_Im#DogMt&3L+3`4zGf-owk_SjpmG0kbm7(OAr_mq&#H(YLBVWjI
zC$^nOEC}sg`PM81^s~13xsJpuQiKS96#-DHT$e?`@;MMOZ%0N99*{{RQlCIw<89*B
z^GNOrb*=zY2Xnp1Q9-uwtTxyI3Do(`)9874encWCg592AM9lVXaXznd_89}VbTu!%
zqV10MbA&IT1w%}RyIMqvcg(A+tA0XIPGCtp#jWb#DCalQeo98lTFJH|5{zvjsqKM9
zv0E0qd)+d=+;?j3EqNQXa}IMY;_>#H2j72Ax|Fm|INv-fQStpIRvLsOqCgr0c%3CG
z%Cj(5l+BSX+!2L!SDS1|J{U#B7;yGQxb|jITX;!jRK>Nstx=GnuMZDj7)^p+D&6-g
zHN-W-l!P+AZT@=aTf-$})E9VKV3^dzy2j)d5E8bZ<~C|8-!+{K^mLc+Yj0NJ_vlj*
zSPYvfglDPCU)Vz?Z&CjASsDSF`BD{)jY6*LWPu9de10R=<N$FIaqEE6g0O;GjFV#6
z?KK3h7$O-^%JX^BA!O31<DcTRM2~wyH`^nTms8Gb^@n?6oGTQj=L4BnEp!i)DywV?
zy}FR?yT2?FU>X=R-KTk6E8-0C`mLx1;$rJc=rho<gqj0VvSg7n&ptdRDk?{ZnDqk#
zVg}e&5>JEhbBir-bLWnuEx=~!Rcqd$Ff6pB{zN&|vN+6BKn}+}2kV*Z4rno6>=d7`
z;Pl(2n4Qn-tCO=nKof~LNiF)Iw>efEWk;s?+ex^5@&pBUt@xBp3vE1O1(3VQvXw$Z
zf!JR!ERD%+>(Kw|V8a19yRe%dtksrx2Te(J3|JAc(=%F~e%{F6K#Owueu84Myv2Qv
zfMxQUcHm=6;Avn-{K%^eRjY-hg{wT4P+-e<MkR(x@qB(&8FZC>*394*Q<!Avkp3-@
zvAMaFeLqXlb`fc#V^<~2$ielEggbfUam9HKJ6OO_#GDua^8G4$E)o2dlK@X@OlI|2
zX8&hmv_1Xi?gU<%4tV^VS10qJaazTqyuU6Gd|Q-xrQa80aBO>Qzst@<;>zmSgqMyl
zWHbGxtkU1En2=up)*<_N-RqTQ<wy@jM(2ac7&jJ}VqV8L&71mkYIM<f_bsJ~y|&ne
zL&-&pd~JXp`{-Vo5e~D8-yVEI7kG4<e@MRq^lHFU2~ZyKy~8T7T=M}K4kWaQ%SdTZ
zllm(WW|wv(w)ww!M9HU8Hgr%p7R<;DGa~zBn^W{y+Hb%slY!GkYYcHnMZbCtSfv1g
z)af<dp4r&1m4v6F7KgA=IiS#AQ)(=uq|_qCW!We2?cX+YClp@pCpfwi9Kd(0kNDEu
zDmj060~T%QWz*28*fm~hg$<l95^eI|cgLmj&qThkdhC9|o_~!ZCn&8dJI-8eEDz>w
zohQPi(m`o=pn1ENKHA&oKvkoTneS<bk&8+5UosmW&Cv0vZ(Lep!nVrej}gSYjeF$9
zS77<m#oZ+OKrU*wBL{$^?<xgAbVs~&voi9hbT4X@xa5!cscm)!0c~9m+YfT=b~->Z
zR4SbY=5Gp*#tGU{<+FbSJhW%w3hqk(2*dB_!u-wtR#mmC!o5lKgb-iCvFRK_ak0UU
znD=vW)e$8(1REDlrob6eRNc<u-i>XazZA%yVr%clJCIFGrrh=8jzhRLK5_qT5p*66
z<SRe*;w?JYMtuqFfJ~(gwO*dE>-jPkkOpEyz@_dN_}=>WiyTIVQ@8D)6glE)WQ@ed
z?knRkZSAh8CDMT1v5<?^o9EnFWSP-q5T2K2#e+vyXk|L3-{#r}=r=*Bfl;7+3|{+y
zjxO`iN8zOHBw|yUPSxbLGO++T{`GYQ&mdIDIO$%pBq6Q+B)H>!)^Ja$B4^_AhiL@^
z<7~WJSi{B}hXk5EK+u^HtBg@0|JoBiSHmI}P?0EKO2tdoRjQT>H3O8$cq`DLvxDHL
zsfzxi`Xiqci`o4nZu(Lppvcf1iuLy$X_{$*jr6MFUs(Xp){*XXh7M)kvu%B*&yHoa
z(w$|Q0Q%Q)!Rd6=2yNZE*&6`KVU7N9nh0z}L2@w8!s#Og6z!=DLKG-9x*`7^40dqF
zVvdQEZr+}G?B2}v@Y9wQ6T$o~^%-L#c_kR8MB0Si4oF!CBea`nw9$$v9zvkimY*}J
zc61wB_9wVhHh<J@tO@`rK-Ryrw*?RJz3iWA)yyxR)QPkj=-ycDXzbNNuA9hyaYO2$
zGR@AC@jU;kctHNyuYL_Sazx4Lhs<{`M(>j#4<Bit=T^mdgQ>5yEQB}|8g5bUvtA_-
z{-6Pl`Xo{T_`={XY%pqVMPcH%jJT@_{v6nGd}LUtX6Y(<n;$ri13vIcxd}q}k;Zj(
zK39v`1IKTJmr&bL-=P+`tP!%PraM$V)s)0@0~Q5pbd&KhGywpQ!0%=$`1CX80)aSh
zdONRgVqI5JzU9U3IHA=Z+qng>KA<*Lu}&!w@Sjr~E-;zXe4(&gH-n3OA;uS94Xtii
z=H&JFGB__D7}~g%_XB{$sR&6!NV|QQE*&Q@mH69gufoO3<IM{}7YW6mEEWEo*DOXc
z4piyJZ2oDe4N~z|3F9>U*SPA9s{qo!ujkjU8MiUt4anW0$@eZoymw>Fgo*;zBnCPy
zWyHrKB*6bodgsZL5fa8`X|ChBp%Czw+8NOPCYH2Sgjf=uXda;Hd+7?EtTFn*Vk_?=
z+~5TMc5t@EU)fNdH*u|!w+`aT`Y;9*bDyi>)Ofp?f<pmh0ASlH@CQ&cZInkmxT7cI
zotr#h6BpF<i?{vE7C*KjfG_#2*t+Dy2S0dXZ^5JqHYD7mD24*Z=@@RZVh7RyXcI?v
zJi)d8hyA@m&?!jTC^9*A_wF*0{`0Y7@j-;2o*0Bxv|fshLv-nrdi4VGK<Qk7g_5e%
zndB|84^93?Q-%)S`7V!5>ki$GRp5Kw)3Qkw+}DNw@GHl!?#kJe;D`<ZDj7~J=bfB>
zkoVY69Bt%L-xc*LkcDzU#IiuJ3beE({7t1+Srvd;_3mErMTdA??avoD9+=0<s>l6%
z7^FJrT)sr@$9M>ug^8#x5W#-}^B3)HERYncEwJ6AzQ1S1`L+@fIe&p7@n=fa>Pqa<
zjcTbUu=Z?Bai3J*SKhn5_*Z88tfGzqIyhKiy22rkJl8IHubXR+imcd`=r?kKHNLf-
z#k4n1#L@sPV{lC0Lybc9<IVX%(@6**P2*Q%_HR@dxIg$91DH0k_2F)PkzZXh47Q{|
z#qh);O7anh(wl-EUyhhHlr?1r>Wb`yBNY{*J{S^Wp@Jj=+cHjn$K2!}2d8nG_NB*u
zMSWWb<xaosWi97uP!y{YP$F@{$$3o5W-rwW4+dLOCF_``X_#$(Epq;N-dAqe(R%N^
ziMK@s62qfMjIeG0rCbWv&zC3d*at;{-b__89l5(@AvK6k=bP)OLFsk*>j9Jyel)Cw
zI#uTgCh47Ben8o3M$ZTp<RVk@An}k^uV!|V(x<)9gSyFF#d6dl75P4Hi(P6`C**_&
zP<0N+QNs$;^#Kz+DI&GTMZ}7w7JX}`D@R=A-+Ne_s%FxogriBTdJAFAdB!0`W9i7u
z6=X)S>=<KNn{e>cq<8eQf;cA&OOf~?I&`J<e%_*>XkC^Pubxn!&=EaE{S%`mm$si*
zGM%DpOz!0&h`01ms>rLezhgSmOnPV&Z8LW!${zGWb+a_6La=GR>4Eq+IXW3Skfh)5
zg+Dxar%Pl?<(^HmzYJS0toQ{;OhQeX_+p_xkDG=VWbQsR=qnx<5OkePXIh_MVTq1X
zt&r>W(SM>B2AmoZ8^#Fp%pat*S48DBf&GV!&+%->H^jQOgmVyY;?7)OPRV8`U0ZVG
zCo(35a-J*?71*WrUpzRf%ylEB^nGAWcXG(OXQ+jAM~880L`rRnW@zWRZyKt>I*`PM
zu-!aUz(s2is1U&7L)nkrsp{9^=YHY!;Gmn|s8?T(>5pT!8Ey-dYRTvm_qZdb|JNGJ
zZu`IXGstVUwRQy#4lQl#q+2_YZ%SM9UQE*)k97scdwIDa7XOWD*&<mcgOqa<O2XHg
z+C~VFX0^utOEWF@8**xbo85Y<^WSc*-vgu<n*-W^$Zf5I;LA<QDGL77BL+=+nQbVB
zUBU)46;2{kU&L=N3Le#Baiy3HtNyti$PP?V51$uQ$4BwwW_5J#6PAr3?0fvgRlz)Z
z6VLe9hnZ0MeC_+`VoAb;v3wLK0_I=~_Os6jANNo_dnmK;$t%~7_i*IO3U~Kveq`hi
z$bYfYo3b(!2!EoFjtycm9Su}ui#go<xkOYozoaqfZ4Zb{<RgZ05V5(VT^w!@db#^<
z4~&;>Hd3JgGw78<axjG#cz<?-kMQ{)(+X4V@6!3WRI5yUq6MJ-gk6W4c3uCLt@|Un
zlrK&+G=e6QORBnKPj2RaJ_Cy)E##-^At7GCMl?9xAtCDOWmQ3b0ks7!taOzG<dr7R
z%zEb)#uO)(4iHtnq&<H-KwVg${)jc(180}&1L~R*stk{lt|ykGA}XU(?-gIk5r}4=
z%`DiuTHVqer`+&Z*V@hQ#7@3p1XUDgg?1JfUw=}YJ9M#t=`hR{@a4~qy6IcZLmI)4
z-)~J)9ahZ0;oO8lDKvzfZLt4K%Ym=!$vVaWs^c*tlJ3FEf)2*CEAptIay@;3A@CNe
zh|u(sWnqP*FFSmUn)AXPZj#hGLmwPB9-l)o10!`#)IWwjRLGEwyVmb2*{BL55&?6Y
zeZ;;062<nChD~q(f<rnXTV4rsMyU*Qr$Khr0F;EzL^H}m`Q~Vz){-Esb~3_Vg;gY+
zd+8)(`R6H~20l;7YfCu^qAVvL29O=247z-qYA5FY;Cw4;WX*{ZXNhU!C~zlANn%dD
zK*{3OXt2f)KZKfSXZkKYdS_&fSuDodChm$|(8ED4Chht8YjA0ff+3%cDEkoRV1`40
z7rWiwu;hjz_J926E5U+s&$Fr&NW5!oWc5jJPWpL?C`nx$f(P-0r&Y2}P;+v*Hf^Cr
zy$x313Yjt(Cb>}D<JlyA@l@}>%v7eDYW}VS$m?mbx(v&5*E6(rfal$C*hMGxuGio=
zMQ8dU)m^vVvu+@IFi9#|<int5A<CC1bH`<-YS|7bsQwW!xxmNjZ*wkl9Qb?z`-qMo
zzsz(?DPIy$KE)yUh7*B)LL0msb$+eRfQ@sVAyMR}v_@Iz`gu_z%G88G;f0)q0~Mtu
zV~)plnIRchr9OO~+>7f9cd%HJnU?P(A67)MUiNq8dlq+TgZ$LlZ3JHHpf?Bqtx367
z8LEy)*$Ar};prfxh({*i9<3tkE@u%3<kf>4_rIFd-0xkLi0;eAeORxl=r*FRa_uE?
z8_U3%o?s!7diew3liB-v4!+2x>!%0RH8%Dr7@b3qc!}71UZc(LYjS>9{+lD*vbOh<
z7lk$WqBVK#%cNgRFwy4V<O<0<Q2C&Wq`bq@!ON=nbhR`6ufoRKzEh3P9N%&9ekZjK
zvz4b~f8eKP2@3S2>9w-NRe#<CW%k5MVNs$h&UTZ_bf=L6uqH6|opDaQ$lE3P;UEr6
z8(==|Wu_`nh>+OL4DN;e(=ZB&z(y}Ui`Ob8)!i8T`j17U^}cCZ8yJmvNcW-H<>EM#
zpqBHxsW)O(t%~$-Pl^ltaN{6qkm$|=2PuUGwGef;*6m0dZsitd-BAwyf6)H$ZIx@?
zgKPEJ|KP?7Kxw#5tPb&^#v6WAUcy77N^#dDH!vH|%B7z%FrFV+8{4>3_l4yVT}GjT
z3{e=0YfVnEP+|%(T$*AOP>5(p9>z<9xf&lrrQJFlHIG4NJo~-@1Foo8!kO&L@Uk*&
z8|(_<R`Q*AG=d8a1wvo}QQ&MkR>YVr!$zEpQyEST3ZS^UsB7+0gBQ?8=qD;6JDbE)
z8~k5sZ$MUK1(apQ4Q0hKJUNjl4+GAniiA1pJ3GcHJ>>0*NI8!S;b<NO&w*I<#)6vz
zI8~A;d&;CT-W}Q?h{^0`L+kjdE<S+&MLUYa`#tfM5e=2j;&{7wS3IskoO+K-3Ru8B
z%QVD3<|2-=FJ*GW-OOboWP@#nLzv<j*pJDo$eGidDEc2PHSlKwKX1LUMNy28{jhi4
z4ifo@)@WDP!-ofo+e@Zsyc~dzQukb1A0ZgKg$kh1$>kOUqEc}-P)Q$C!|xFKv>qWV
zLy=|OIp&*Qnz5*qUX&zH-}k=2phs`=rH<n^FCABSLctMj`-%A!YN|`ic~$N4md>n0
zU$|1m9zHh}le3U)yW!I_wo431k28q(5+osQLW!>tok(>%;b2M|%}HEqO5yGQ-?QQO
zhu(rG$_fXAu{&w|H+>srF6&YDNi{BV3gvI~cqMLC4V2^6?2hPrX$d-ESAahL{z;v7
z%+9ik>*4)EiV<%Vc`Bbgv$dYnaANANI;|z96^;Q;X%@h5^GYRr#?VCm<X7@CS?9)+
zKF&y#{?tk`lWxYz_IP-uy_r8VS>6OE+HZ+n84ZG$lZz40n?yiyc*=MDC-hE~N~xYk
z@(9nVPU;m)W6XccB%x8B{ttPvG_vrh9Jw<<ibIql%Pyd~i-SY4fZr@;28C-zMY2}Y
z=n9MhXG6-za10mba<_h46uwSA?wou)p9-o2meuuR)wL5w0+v16f07ZHs2P+vi{g4t
zs;ExJ`*=L~HSln?E*u-AUhCa`)GP(YuW}E(y3^dW6fQ%RL=A&0=S%EimPr7RC#-9&
z7_}`J2@=yEUDh{L%t28ed}-a&e*iB8kIzk>fOH$^PDkyDSTuBt*4EA6?9P4HXD#zo
z+z8>9GZkLlB*ytb27PtJq4*wEs{eK$#W@Uo63v);mU!LHKtm>>L%jl~EY($a>YVEL
ztCS(6KU8Onsn=TX^o$R~|CC+86eOdM*?}9#PY#n_BLZ>HtAevke#b=L5&|hE5$6Tv
zF1hTs)X{asruq?z?$_dFxsQ{(`T}cUCGFd>Zpf#69R*pyE>xqraG%=@a-gngP=30o
zq8kExsNQnH@9?7lxr0m<8#ljKLLaFb;5E>CbSc5yOW<6IXH;GBX6h~>^KqU98-kY3
z6BLRE7*>f~M@PJq@gz7qJYvFri}ninofaRUA%z4!X$>tJ2(RYfsMi5_t<mYc{hDvk
zrbi)$g8T+E$5@aOtO!U~(Bxs0?qq)%X@3&>w`r4%e1d$9W@J&HIWLs~$e1Isl1ngD
z5xJv8^He~EnqxOF^5gDS0jC@i=ZF9^R<L~((4yKuTZPCoSr62qNVZ0uYs7Sfi&lIK
zy>m8ZekK*_<xPSjEB&6=(!%Wxn42CKxc<+}+bJ9Llvk2>SK10Ha|x{?Z~s~|41m-J
zCjUd|EM%Da&^O*I*<HpU2}?sz-{R?1wSOB<D{S4&saGZ$h;J!9Z{DMuULuJe5qH>&
zV+L&!8C!=!B1(xvGL?TTP19I$28*{eG#V8?%9ti*vQ<t1@sRuH?`Mt7<;$v_ytGea
zA3Xi&<l0TfHC(HnT<yhyJO4Wn(@D3hHZTM9htRo@`MzP);<(PLLI3>s$!*CTc3;b5
z+y%2*-u4cLoWb{AeL^bpQ#ZkQl~-dd_FK)pOopjLF95Uypa!y1e!)guED@mC=m?nn
z;nwQ?EnH9X1;KxFxke`2KB|@>?-q(F<LJpNY=|p2J5n&Sdq|=+`?Iw+yb$`%T$#=R
zvM)hs-go$K>V-v}TrKgwE=^T#AsBw?R=5(4a?%;s_4sE46LoGl25WNbmTBe{jPVL5
zJIX-H>J6}V_wTF9ji4*11ycR>nxJezGC7JpcHf$M@7=7`&uMrOd^nT-#mVeyaZGMA
zf@-cBa6gi?8A2Sbn%!35Pb<so?rwqtsL@KY?%g$);Bx(>jkwIBeOj6<jvn2_Q&$tG
zfonePa(zW^Y?ADG(pYLsgcdX8u!N#GaYr=0`Vz9W_6Yh|+mH^_a(Ki4hQr?g8yt<D
zb7EO2A5I1RApZ)da_WUlQ-F|xQy2slgpSB7ABVP~&`1z5;>m$_=U&ri9@}ACAv%bQ
zc8hAhh|oi+cje74!Fu)EXdeO3q6{)AcXCpji-;`!eRJ5j3gbHx7Xad~8R(Yw@f*^v
zgcQ(}-4qa=;4BHO_mN}kS2+H*G!vnGIm<)fD-XMgW>7<-CaD9m35x3DzmHLBrEb`Z
z;5ieBig4<UR$k1zq-j^2(|OZJ|6>1ka8BC4Et{D<FKVmn9ujf-s^)jcg-0h1OuZ^S
z5sxxU**)dE1c8v}j9RZwTk4I2Q(r4|01eLax2itIxRzm3jTp_Qjx%l*bW4sGzCS6{
z#k!XEe|-Mi%W)1m{tJ)3@baKDzeFBMc<}i?l%}CswHceX=a|clY(2`lnc<b~=*wJ3
zj-HliX^n7_vqqnC0=gbVctm~;6B=T>?lstX#Vsgt(dKeP0)B)fmZsy8+fhQNl~*x0
z8&Dc$kL5m>kaaP26#e{8PtznBaKfZH9t#09{l{R>Eak*f{bq0JcR29LgFBYsa{1)&
zU%L;JC|_0L&Z-3_kh`vjX=x40B5i0PE)3@kp?5l)-5Kw^Ni8zVC~`}*E5`{^t#x<J
zw0XXO0-EFj9H09>n&<i6t#Yfut`}(N(LZ53$18cH1z!e?Jn#`w9X!!Lp&m|CW=oDo
z;!|yR=IGu0L2&JE<<sd4ed6ixIl5e=@qHPpm4x^`Yy%+dz~c+jp-D_uR#HC@XXoS9
zV|2qLmp!Xb=7{>(;OK;moz8Wd&pF$a1$BmLjIEBxbZn|{@A_$(;&nOXDR%^wDNZfN
zw4ENc1pUC=4vNB!uN5P4=(W$}_Y8Hm_5B`WZT4>V;!1Znv*`0QAX}l$SdplyHl~(Z
z%Va|Z76~U=0;LU<T6!<<AQ%ef?q>wrKj{ds>cTLfaV!3Yb}&Ct{j<@*AI~;`i5XOR
zBYxIfsASaZ9(Pj}(`1`bXII_gvF%f&%CtgHAA{U`*GPpG2Ln2HH9iN#L4emvR`KLk
zsIr#54RAWamEWl6MA?#S+0WR7(M!+`sWr&1lCXe$ei%VjW}b32snFH)ry5^5)K(bd
z2+X8lp_@+Fox`kb_-SYZSh>3lR{{E+6n~yKCYP$lf3gyG6TFJ^6kzCe41S9VlVy`U
zRY15!Qq<GI47-D(HIv-{_?`&x7l(Zetw>aPck=Gj^fP#dIKc&21ELTS4(Y7@hQ&w#
z=<=%y{_Pv^ni{~Ug<Ip<DfpbjV7Ae;ih{Bq=>FK-1PdFW#X^*_ovZ|((7tuvVY#@P
zfSTI?I0w7q)GeFYfIeZ%IV(C%PjNoY4;LKa3?0gg$_wDrp@D>M=uXH6Iw@0ec#xH0
ziQUcBn-Zuh*tdO3<rxMshJHVd*m$3Kx=gFM-x`QzXVgmPB>Gd2`rgCx!c?+I7XmXV
z+`fa%CeVDjyardPSIl2Qjrt&rJHkQ#c2`_GQeL9X2^@*b@N8}FWZsiBPeG<J9%`aR
zZ5R46r+8G?qQmI=<dxc8p-7@~C_K8ZJ>KfAP-85tP!m{s@)N4_t(a!o72(5qhvf%M
zBT&rZI^tv{9-?W(sB^die+e_qw-TL?voeZY6ddcdAMljuPg*N#kNZm1%-3UAOBgrG
zHIBENWUhDZ1N*iUAdemrB)e6?SF%9d_KawX{AOA*EvZ20OqevQCRS>}WA>|E*Qr3>
zTmeNNiV%)C`lOa~?lDhwl0n(>iV;DP=U8W;KSTK;Ew{Znd*0?XDwP|3q$Uu|31u|p
zUv?4oJE4)4i^>}rv<afZk1o_#@R`bj{yOSSLy+Dizg8J={}Ow%XV}b$aQJlE?*gGK
zh``5-<724N!U2m>WD{G)JWsqPLOf>woFltj=$_L$*&MpF^8qj5b3kHB40W0h%uU4c
z&o}{@*6cg)4}v+5?LRuk`j5nYDEZfkshO+IA0!FQW{0Au0q<O#KwQ|w(dffJ=yD;`
zc4H;|he(yl&JWZ2RmOMIWTS6H3@0MWTt_9;N;p8qCu?))CQg4gUre5H5DJD%C^wDm
z)5AR1th)7}tV+1LO(VP~;FS`%R^~<XL@1f#f6)?dZWw*drqigoc5bTG8_IueH_f03
z8)NcF<7`7LWULvAgSwMLxr0Fcq$;jwc{tc+d{L#I?aIyC+1PoRKpAc@yOZOp7hQY*
zSi-GKN<cE{>AFHn5g9p+E;J(^OAl(<W36O+!@+KLohfx!f^ZQJuOP7z`AZ39ZD2t{
zLa(W>+yYbUAte1toI+Q)z3mG@?&R;>ck!`K)7W$zi5sDb!EzVlbacOcj?{Ix4$cb5
zw5j0W<l?jpy3eWa?kVC+`*Qzc)<*W3STc}duDP73K{)s)4U=(;BO#X>m=8Sg6erf?
zc#d}uZr0|=Pn}zuv=PcR5J@Y}HU)DJP0d3T>|ko(O<yiA9o1fn;b+ArXF}}sFOkSK
zfUE=&f=AaDXCW7@V3v4%Cm{#{p5h?xAFYLtsJ_?9J#WqG1iw>;;+Xtoc9q!*Ey7)e
za3rgm$fj%#oF%xPtztKo-1W!w(g)l6c!4$IVcZ$ek1OSl{!&`Cj5n5xHw97vBr;8+
z={1F-&JPf@(s0nnp8#3QFSkyJ?(-Y5Qxo4~RW5nD=BO;3;(`11oI|l<O4U4_lCCg+
z`=$~o@8PXN!)yPBV^(f+FK&aOSB)a*h99e)5vuu+`NEgkAySo7e~u3X=gtJF;W{ag
zHGQ#Mh#6!U(=nOS8Pj^FbeWw;PKm#{DN~2h$ywk{V0obB;N30e6FdHw(&F}Xoi~e>
zBlp$(#+^jHJ*#<RzD5-Xrs>+Qim0?q&kTPT0o@TO6B^o4Ke=!WG(x^MnuxzGI9sZ}
zj#)z6zXo*!Cx#LQaa?HrHBK!Lv>D@M1FRGSlF3L7*YCJBdbjZ<biqYX-B+jN#AsbC
zC+#Q68_~4R{~dywh3Z^kCN;(<3{S0zOib44egVr)PaE7m?QJ2cj;DcPYEqaD)zUV4
z>QX254YBTr@ZZp?$LV}xe5R8Dksg`SV?n-i#{TbRn89nPEi=^Fy+hP}9i3$1A*UlU
zx<qOR=pI?_D6;mxas0sweL@_F)WTrbq2YB1D1D$<ODiM7bcyAH+yV;fsE07c+o$>T
zD;$u@fH2Ry0%`gn0Bp~ak3z@l36}V`SaOOC-7CVzPrEEAh(!z_yazVXv>ez6!XdJt
zh!`N9jcaWBRBd%;CNIp8Ac6iKhZiX*2=_p*6X*1dG@CT`9g+%E*7S3q(3}{jblEb|
zptcz>+<gLryNGPloTL1zf{crAv&C9XOCiMgAMI9AYrGlq-)qVuG^v5-s!Oi;r}wTv
zL3~;P?ZfkVPKsI(CPfW0wGqPZ%m~8f9>RgwRhtklIW@R!fb(g;a*E<E|JCdWL@sqT
zezE>~gUnoYj8Y$kr+VPgP(r26Z-|(L^@f2n0WxQmgV&!fhU96>7d5XfIpNXJ@%&$k
zkKKBtW-%>^>3HA0zK+N`mOY$ro#mXNiBfMIB)1`_+V(^5z!eonMQy)!;}RtsT9Ju@
z_!m;=zX4HsaZ)MnrpB`e%k$YBPoI5bTn&&iE0?5Aj140AOj1#`>d|xs9anPWWK!xJ
zPJNF!Lc-ZO>lXDub(cgBp^bJqUYu5b9nsv2vWdruI+Lzm8GRe4<Re2Aj>uD#bC6$m
zV^RO<v^rKu4z}kJax`2V0k0t3=@>i;D}f^@aLS#;83hltKpNc_I&^IbJ0x;#5G+}C
z_U*;m0)k6tGH0eF&Ep@#8m++%m#U4BAnbaKjgA*r5-J9hrE-}JQf{6~6-s+)CY^xU
zPM#~9k8;n}NX)Av2B%tiG8z}ZNnWt#O@0PRK3;6-Y4H()zF{YLP~%Kb6S9m-(iuSL
z>V3Z#IKrd6M`GWg03(3960ewnOPHQOC&)xO4xdvk0A7YbUh~RtSfw(o_vZZgzRpN3
zb@ASuuXO6=t=s(t4wJIyl7!gFG$^Smb*sK-W4T9_rrfpL^8ZieaZDov(ry|fmEudF
zefb8#_!G%1z3k&t1^9dw-1N;V>>tWInNN+Zh7U9HKhuBew9|Z;pr}SUpgO|UshTy-
zb_Ho+q6KN17ktGi4!3mZeRds26WyS0TPwMTibWf@Q=4!g^IDA8V`|6{?=yIdF*%h8
zhLI;4KxWIcprLSGw*mAP(EiPJlOg|bpJYae(|adUj@v4Amj#o;-msM&Yl2m2#;k%q
zJ7Htvc)Slf1K_Q?;{5F!K*y-HqlPfX7ME6J?4Ek|-4J<Z+x62A4d5&0O#~I1K$E5&
z!}b%XeeUxYUY9@<mWBeBLJ+wwmsvj=ZKgUuJl=EDhv;dSzcWg?xN3C^w~hq>tp3h@
zontlt_h<|>o5i3Hfj`v|lpX#t`<_<(31kdRriW#iywheb)G6A^rKnbt@aR1i@Ecn4
z14o}1r^D)Z_t3JUy9aM-a`FK`$L;u>nvIEozs3<<QU3#og|8k47d@W{2OU(t&W&>|
z;<9u30}%50^pDqCqJtMveB=_+ygPK*#<U~3KYl*7fQ$g1*Y^gewqSpDIc-lqzs+l7
z2-(yDi!W#5`*WDYe(s!6ph$zdW~q){HY1je=}iBK1zU_cIH5=s$~VZIN%L5nNuB59
zDs?S7A2lK&Ty#og=*ysGN~CUiPGVms5mchRmI!pZ4O>6v!};?V_YXS`H;fQ|YrkTE
zyQ}^b>L9Q+)pWy!3=W>)AQy({3lNrGYx;wZ7%#vT6n({Y^1dhvK!>@j=PgOTikI9y
z=RnWx=9R@02Pyj$%p6T>DCUlqFn68?FU!l=_i+!SWA{=K4ga9D5>VmBD#sT00cyG`
zjynp1Ju6{SGWUMuH!aBbkIE_ZGT(I@1qxgWspe^^yTlau=gx1Qcb3&Ux(boJcK>J!
zNR!(&08Zymw4{U-hS@SPqOA}q1CV7?bM1KUW(|gikWl74WIJtBo?{=61<iQ@2?;~F
z2OmalVpcU<#8YXjT$yQro<pvhiF4=T!+)nUf=ABBQNlg<(JO@xoHvb;jE2_0Y4<hA
z{-A~n6sxFqLU)}}ae>Ex4aoK@`DM9x^Wyq`u$V5LBv<6M0U`akrfw_82ovn_@62yF
zVdA?_W+(TsD9@=6Mr=dqt$#pkGKsFVl%eDUs1A~BrFAG*Li%Dz^P~SHmq`m3wd_sR
zxyu!Gj493)LmuV6WHwk6P6G~Fj1wDn91@j|Hy`wLj$XP>D=0(6q_~3&^{;T|Q|gGv
zwHH&%-i*R_3&dh+WME|nv`}Mo*3jXEghYef^Ze~jF|kXxk{AimGwe0!u-kXsgY^G<
zhf4-@6o88S`3e<%6T^zF{qJ1uk`<nVd}(d9`hpN6iVu!@G`sCD{0St5;MK-Y&@Q$S
z{2<D`z2k<n<kfUGj!hi)%uPQWRcG|z#x3Le4q%4r?70b&Np)0R;|Amw!TAs0$2qw&
zv_qT*hCPi(eh6^b4|Y}xnc236Gr}R1&2OT)RBsi3@q*Y5&D!~Wczb>-({mr;DH;VD
zW0*kpF>OwG21<`mXDFE*w1k&b3K;z5BlkOyyc6cgf%IRUCk5If-9?V1bA}k8ZoPVC
zUzb;2*xQh`s~_3T+E}ZWZKAzz#FcfHvPn&ppj(^pG`5^=2IES)h8t>=*B#Hz9%t-^
zT~WF`zB(huv;g!;)~f<Lf~6QCgov_ng`(I|HZvhGJ@%Ab5|#OX?<!k?*8^lUHrrdE
z8GQ^}>pI%!Zv+OId-t_g@url4mYDm6;v^OR?Q_7yhTizE{&lp^4{b|(DV9;0!IasV
z$tV%^$Bnw9PYPe)4faG%z#Rpf_uDt*xH}{90Ig}%AqjOhK}4Pe0^|ErR4MM4_Ps)^
z-m?Q+>O$n^V9Qg&w^`|8;}q>8MUF%K!dg9CtgCU^*~11<Ekx&hx-SRj+k}z{PHu8h
za}8b>U;;A<`DPSgW`FS=(bk%4^$ZF%%a#H%Tqz0w3s6D@T#jkIO6q5j*)JuCUUVtm
z3QQ~k?V-`NygJgAo5bp%!R33;5n|zqW!=q3<FTz2V25ha>LQipx_sQ=-r`F)5cFC%
zh8xQ`ePx7VdJEuo6X*L1i6tAw?!R31I1#z~MVx)d07U`A>a?!kB-|PgKoz7n6q7{|
zJ$ik0GmW6Ygz1#t#+4E4&|jZp5uD=!2-n}Nt-IjyI)&dieeu9uL45v?x_yr&z6wZE
zZFqxBZu^9EU;uu2iS*3U;a{FiwUK|IcBKQMCtsN0G+}Jy0}UT7h%NT`cq$mhV<zu;
zL69-uNP4hj;@E&fRC(6A4OC$E6EoR`@Q?~#O{Q$`pH`1DpOONNC%)01*B<~-4V)1j
zq|Y9@n&JtYp%S}?aWBO|3PLpsgt)SH8r)-7GYK+!QIl3TaW#V2UhJDlTvb}Xj=kW>
zPPbj7DYG;yx#X%GJShM7p__NvJSkn~43f<R$T^IT4l#NijQ<}=-*W|CGBbDJ6l*|9
zqMs<?o|X3u`xoMNHG86sjfOpzJQpby!r=YEdayCw;MkOr(uB9)88O!a1b!+KKY@l{
zy9)rMAeY}+<GMv0Kc5WJQhBf=W%fq43qoevmz!;5V|`#&GMBY7?b1Zn9kpq9DNXxX
znglHMq-OpQWR<ZqNYQCR)Fcufbl)Z49695@+NhB|iX5C<62taV#y}LIU-f_=C>m&v
zZtZQ?IV_gh+Yk=ku~jALIWC?t46bRQ_!EBPn?NP5CM{r+ft?kgz3A&p4`Cxpx*QhT
z_+{V@5nOg&Xu#xo<neb*j&cx6kW`R#*`9;=H!-cR&3N6?Mc1>;3>Y8$S#kY9JRCo7
z*Gu!-PDBP*dFMq?i=R>iA{>g<YqAQY4`+V>>7W{jOYk%jui2=QG!YNST~vrQflheC
z-p}+VS~zMG*Ool}YY3EQ4H0#Jb?K<y&I<yjSx8h@gVS&lxw#n$9JnPtf5hMGuXdmf
z>HS2TXGyGf#DL#7XsAMU@;h;v38Rd!jv8_u)>!<h`<LaKH||-1E3woxCwd&}Pm5LB
zZK?BtBNbgGx@UH2ck_E#DEaNIqGP_KG0dIPlm9xOBuj23O47yzb6hq#Lf=(Is;GG!
zD^C_#(qWJKoKdl%8C%#wNx?GCG~k)!9fYUMmZfc2>9p6?1=H<1RLuYHmg7{Wi+Tk#
z!B*v-qT}m0E?$;?74I`rk=)EFg3o{Ov6IrE&%0V-q~H(o-lhmn0E3pCaT5I)X}#fg
z)$%)hjo7btP+eR0JU75%y>}!IVb{(xeJ`dDte-O16Atqfl#Yi4bltlJOK{&u-&^-1
zR9k8H!kp}>Co8%*md*MIfumJYM7mnEUdRg0ts5Y78LP@U2PI$@<DN^oR(}sk7rKXP
zwzY&*0hf$<N<jp%6?ag?up8TFW@Ze1DN52%?-UHtOI7P0ug0yL#i|B4EW1#ci(myk
zc;6Y{fTkss*~HIx7Stcn9Q&@7nu0ZZ56CP4$47=9rf9M3SL5GG2x_*$95=h<wi;HV
znG_6{#qz6ucT4C2muG@@m}6C!rZ!I%F$BCgLz_R|wTluk7v6Fx!#4}`bX^8^&6Bh1
z{Pq>1RosS;(#-!I%a3u=s2GCs(Pb2W@Q_dOs(;>{wM+MA-D1$sOJ<Q>E%xDW_xTK6
z$Vfy?jV;&a5c&BiHiJn6Eh;j5_HQL1vPH;NGX>cGoc#M6i>WOuYCHHp<08zQct!XK
z?XS@ZW461uN#yQ57EGM8rhi<JW?eBiG$s|&h1&z5ruqP&I=AI{S2v{95GM||xFVCp
z)nHx<D$?N%h;d!ZYw$G)=K9h13KSACfKdG)AUYbwcxEqEQ&ea|46r@y^`q~N6)t4C
z^!~MR2My)M%G+@uvp)L?#w@E~7Z7$>iyn7Kyc>%rv#0I<JQ_tv7Q=6b^eoN>m;vlf
zG9(8D4~+Z7WonS}o~*WyGY-dEqipTzvIP9z&KMnA@R*`xy$JvTS?_T-*JQc(w`NwY
z6&vcJ?BvF(DBFD%+3d#EOWY{z4gCe|{x=@v165-Q4j`QmlL)q@ODnhZ-@jF!X5|qu
z)Wo>`i9Aa%Y{`D0_UHvo-@W^Cfg<6W=Ah97o;JH#nHLS>p1VLWQ@GwCK?7xZa84%D
z%ex!gKjo_r`vv#5JpbxLX^Oa#?n+&!CWA6!%|fDzNd7O4)Z^?7nmzJque%x?vh0nJ
z_9`PDH|4{dDWDFoYj&RT2(TY;I>{$cT3mtdmlVnc$ik|%q>Ko%a<IBDWrg7ur2Gnr
zl*%hqm=Lx}b+W=F)w2h(#LJ-M>ISf8f!>M)4c{mgbIrRA)KQ|qr{2B%??)AFSCM<A
zvE0Z9c01p@=7sWhrPdo2i=uVZ%jo3b_Q0>^Tf|(UoR_z_scPqacu+f!khFSaJOV6@
zh|rib`H%R1B`q7~>p!h#J`N|+Q3UgnpAN61o3f53QYpY6MfhMrE6uk+b~BETz$dmO
zk4g8guwK%gQ%};=-=!?wM<3nSB<{+%QmM&sZGD+a(QgEb`SY}!$9A&M*(axlL0s&V
z8IMCRfebyIJm+r}-%5of0~DiX8Yr9wvF+_!O_Nj-4(s`3YKR|zoeF6<n$l!CbDhu%
zv9TbzIb@qHXqySqJ+xqxE1nlOu_u(CGliGh3s$?9qHI;KZl`YwLAnL$fhvCbjDpK*
zeW0AyM+1b}E%8GJ)$yoNf=b=8I$o?kB*Qh=z+sk(X`x0pfd+3yAR_L=f7`P=|5bX}
z11YcB28r{W*M6$)C%13dxWF&Zo?}HaW`1=VI%n_?BKGonam($XKYlygO~z9CZ;*Fb
z(Jrb~?|9Hg6n-UWde1#spxH)LiUkah0pVVQx#rdeX$(J&FR%xURVhXQwQiF?Hd_HB
zpGWN^{W=(E<&ggVjx~)K(8H<w^hUfDBvvmr$PEm;C|v@By6HXzmhV=7cE-q(c3&7`
z_$!UrOEB>IdY^HHJ-|Y<rH{MCo<Ye9DRQxSZicDafk37%xrc(b#<fK?9Nbp9x2tlq
z)W>g&MLG%rKP(!80Z$nbLt#Gwy#Ge^aKwFWbYX$zkde=bqs)M28G)L4A*FMCVty)*
zPFGJyuamR<)C$}AwPCW1jh|~g#2M)Bvdh?I8(V+k3)W=&B*09=i_LwbfuAL~7QvVz
znIKaqjN#;5IlfhFEDF=Sd|~DTr)rdG6Y2#0wbL0R7^S@7+8Fvw2DNmLm??3PyIkLV
zyF6j92D3F}?B=!^V-%m!N?x<PJ_NeL17#PnF3K|BjA5(&X8eQ~L6YgDQM#aW<6J2w
zx&yB-g$=mdqXzBZj|w$Hu7L`pXCZrqC4xj<w7;O<iBSG&CCd-IFX9rXb7VLOPKvo%
zQFI!plD`ky%PTSm{TDIP1spleUz7l<&~6-UT~vUl(bY*7_(n**g@=*s%^>uEl3!~%
z`CG3jKf5tS9V-IN9kaG`Yxczck+@AGDR1o@T%UXSo&)$iQLd8zsZ@^*wlS@;O7b`!
zK;;Gz$D04C>ERWAp*-W02##}Vv!Uj&)~@nJugKS9I%&SP$LRk-(%$3$4!YVFsoqS`
zCUIab_ou#kC}=*%Q_5<Kx9e9!sQ_n#bCeYK&rZ-;%`T9_F)6e|M^`<^5~glgB&NpX
z>pD-jXS194RbeKbTjPA3(E59nX;|e#Mr=x)sfQn7l(SVnHf@v*hd8zBUB($yRLjej
zE?$(};A!oW!*NNMbN^xJWz;`kkL~{!t%)}Za#|6)dugcL$qk}H>!iYbMR#$FSL(Q%
z3#6gH&>L`&>%=hfI*XMFP%U=0GfM7hbCS_I%ec>Pig2_s9&5A+m$V@=34d`WzHPq=
zikiX7?!>CJ8e#30BP<vI>X_?<wR@?=?f#`?bq0#Btl6t8k0<avJd80Q74t(x6!$4z
zAY{bvJo)UC!Y@}sL0m7b^t6{KGn>*cALjcooOsrE@qr*<GS;{M68Iu-o+s*zw}ko}
z!B&#3uJN<5iF97WZ9N+(yXbtgcXYek9U{s2*Ln+7B)I$e^yNEK8FyXw^fQX}DBRWb
z`bZsE6Mh%Y^!_yJ*p0cApkn}_yoKuw<bZ%(*!Ut0HT~$XU=^fXkgDQ(?=0nuINBMV
zE?g*pN}%aqq|Y7GeK*i1WLEvkr{olBB2%#L8!GTv<nOF;D&YV2PU}Ou3hwnP^Spl2
zq=9rEXjnwKJvk!p<@W|IUaa<a->1lmL!>xgO0N-bvk{vGKDDgwVL_8hnBC}Nj=K4Y
zDu&1MB`Clx?Fb(!_jhU!qN6C9oJETOOQ}_8p)#Ra+(DYWT0L*kguFT})R*C(AGM!M
z`<aRDxUOC^1@{r(W8du!I|*k1J14kh!Jl@{N4eq5`cBh=L)l=vlJRkO9VWe4(#!xi
z25`rsGJtODOpxTt7c-j)go=&`ZzjA@2-;(n(OmDl06z{a=ao;Ch`kp`SM9~SA%$6i
zc=BtM1HW?(EEK_?(t#9YSP%}fl+hmaj^{4Q4+e)5{^oh*`>q^B=eUD7mW$PjE+}&0
zPWZ|-b9OU%C3{u6!z%HUrmUjw!Mhbe3b{>+nYp$LXW$1$81pgb0uPatxRsB+IGd*`
zstY{2p<q;i)+PMkthN<f&^UsZR3r=_EZ+y`R-Fnk-`t6)wzu)nemqDlZYk5!F*isf
zRY6$pTb9<;)zQ7+DN)RVRiiqwn^xGGVa?Bp@RbTRDn(B>f)4^pEYQHB^cu!ldSReQ
zQbvgu5Z%Z&2WT~A47*G!H~!(EY>&T1u-pifxR12m_<X2*+1o06l*2REk4k6a+5Vil
zge<>CN<B*g0ssq@`mmlxrOPRxCMXlRBpH@8xz<+4e!UB^D~wg(ZCbm|%-|OSk$92z
z!R*4cE*fDEGF+uSrP58(lH1{pz^(rBb+_lTl`SWcBMeVrU2>RP{T$ON=ku7*9x(HR
zYmOPUqb@~|gArbwssEJeE1$7E)ZfDl+jy&Movbyf`A<=|6k<}B-;N>j*Tp?RWL{T}
z6>@JlHdpnZJkfAd40D&ke4LrWR=V-?a`#pRsHjkl2H%6BgH9GmRag|(Pv&TX0gU;9
zA_CvO1kVReZ$9RHSHWL)j<bn?J|}qQ7)M%*!eFfJz~XgWu;}lrXtOV^f4V-=Zqi!0
z`dIC(h5Upbl5yVF;<|6bpr!_{_XzsN+C;ViO|v`&3#U(g{83bus+r3-YwS3qV^4|)
zfmRABm{ffQ+h;4x=`9Fl*gTqNv>wH8ne!4QkrHQ8<#z76dI;IM=JBGWc(F7?OPBMY
zt{E3cVPPKeS`xpO%wQN==nW5bIKr!IaN{IOCy1QFuU&rn8)eimH`k^1@N_R#-Ym&o
z-4(8Z$cHM1r~>wY-*#$TCB*+X2vC+wK0Fd&kSo;AQgDZ_e`O@xT=CDc1v+V$_`2mJ
z2z|S7I7;gGSD9U%vDX)nzb9c^bR0HIjZ<}K{>0Eat2LVu#ubEMYfM7`iE%dom0<s-
zkH5dR5@-)2w_{G8tvGi)izudKjRVFz`JkmSEa@3k(m%&*g9A!nxyUc_X(h>8Np%>|
zUV~nWwJLhAsU~xUBjtC&^jQqVeo5G5t$f{)4lLv^vF!)cLMuE*)mjl_fcTxST@+!2
zQcqKAV;dayk7LNp$n(C7MIO3ulN~I$2yJxAn}o5kT${iX@rI_w=2?^q9IfG?(Rg~+
zQL}pG&wM7sQo=|<d_LzCn!7+=Oiu;f-}#ge)OV0m{xXzQ9QcvXwF#NjR4B*+bmZ|5
zcQG(B#CW5WV$NM8-1y@65wj-7YDifD@m^D*YXASac+RYX;-dfT!3(rUAYmNC%q13I
zA$H<<&caWkYNY(N2-8~hFig|PE8z>!W>N_R(qme3;ygW_d<?rq)(jYJdzkyP&jJU`
z677`)MdB(zn3)rYew$6hQxfp-iRZNU>tSUPb#?1C+an>wAC0*+W{b0iF-*^W;uH*-
zT^L5jJlz3A2=n`teyc49`J57B*fVCA?74F%u;#f$W2`ZdIg}Fq04L*$`_5qU%JIKH
zqz+bi?0BKVNBM4)s=h-33*b(NRnft?gWTe)ZV3!%SBO)VsTYGjR}1@6WP!F>-#GI#
ztde5-;zYZEOrcY1y!a?W@~@K1+EJ8_wb}LPD^*|P-?SkKQdbkva`S%bg+TmjT+*N#
z4RzPVAUM~L-6#l5?KjKpn{U_)sjk~#<R`<OfZNtRXVDNnZ-5`T1H|j?!FS-{7@b=H
zbp^^;LlfOx1yUQQ?PkIyhkz5-nylm;lyXz^YtZjf-M`7oMQMfan}QNEl_1Y~b&6Yw
zCx!0ZFp`>Q@O}I5bg>!v!O6W4d37MtqHIoQKc8{F#NwV0m(cD(k7yV<s!sA#srih|
z<*4vmjc9$$myzY1Ekx`G4*pM<t)#uyf^AV$m5i>2<WjMlv}6sH8$XxmGgh=By>{8%
zG-Y(;zD$;qy(Db;7HXg9(D#TMF5BuLdj&bOVvE)uVU_=o3w$ECa$$Y+R6NbdghNc$
z%=HwIlJ*!VnNIaT5y&VXT(|v(w9(F@`2uFL0oWVe>Vx?pPCx}oHk%;-OPsi$U<}Ah
zSNzSFf^Ma;nRlc{FX8(v_F5eEa<^T`qK;sKOV>{}tg^ao!m6gE%Q#>E#EeJLE^0(H
zNc+hLN(WrP354W?0%wH)$p>j+o87>r2V<DQP=4$d5RmGxo46+XxmPzRYuT_Ay@BF1
z!9<O~$+JSWAs?keTALOsyo1ngvO=NQGg7P;T`otMYSRM`9xvr6OIcK4c~o1FadrmN
zqf^5@<(0aZV(6I|6Dp*S(uh;O$(IG8_D~6)W?Q0ERI4#`A1lzasC7{{*-00<CNB%3
z$y-ZpEMWLfqA&)Z;{q6UYU`NTi7iA6d$teXizvF_79sz+8af|>Y|`sufhfv0bgn|z
z7qOVAy51%MP0!}M@WJ_BJ4J`bNlcF<k;eLw<vPRZOW>p<Ib?5awfCk_cx(z&7z>s=
zvyv(;nA3ENgEm@0Y}mibIAW5~w&pf(6K*ptJk?f6hCevNixBRZgN0UX%s2>;80y34
zKb^#4ehX=68FW>IXPr%}tQ7xu`pUD)=qEHlOo`;j)OVcX8@?6Uj4m6|doTor-!y1!
zGveVKlt_&)5tx?AnpG<avz|qEf1Oo$vDii*nU2t2r=01A7}3jYIh#iQW(!_lGoB_;
z&qtq*<B^c8zRGC!u#GPN&)oMVjfu&<5i|6%VS`*2@O5o^j7CqpD7Uy2&ve5*C}p}s
zO`jKV+c_L_$S12B=B9lF>#R1{*ytx89yhd+%rT({ozfLSd9+%uH4=Yx$PQvO!c$?@
zsJ+4`I_O0W1X58o5NNRnEDeVyYR+Yr>1ki@P{vYoE?!4b309VG29(>)uHqf2yxk-r
ziH-#8hSs?0XR?<vr^(medH(Q!&*Yvbi<mg2aDU%PqU^*7lduRFsHf>{j44Z(MBu1u
z><FTZI5VC(ccu~@*yA3CI)7{9pUAtm7(3w7fj<2C0*|-T-%I9h`tv9QpuUjEKFW%$
zq|h7qJ(Zatq`#TU(i=J%Y46+>;^=*|PQyT{;;b(pGA8h3UA4pAPT!2}Kqip>5KI|s
zA~meCOFND^b4JbTO*FXxxn~VHmwqGJV=(@?)5rs7aSpf^s)+!pjnmNfVENq1Yi$%E
zF08Zn6wILU^)Kek(Z!`o(x-G7L1p@5Te~Y4TdrgmFMtDjWx^`D1bG{cK0tZ)06|O3
z3Dgdv?Uipu#Wdu{E##0%_&oMT)-Fg{)bdqJuiRutLt5Tv_?S?fb5aM%Y5_A3!?z)g
z9E?qy&~hL|F-fK?&cnX#;u^IGL+6-JkZKf{njpQg!Ap{hBwlSi?rgo92psrJ<qfCv
zNjQr>F=EtZNae9S-|!bT9%EXzLD_(g?;8=WML*nrp7AX6fa>V@_~Ia)+Eso-q36M_
z+$^|;HNjk8IRFsa)k~c{<!l-XB0JVqe(0o`xvymA`7Bbh>1g?GUF1P+y?%2khe3B%
zkVknkX$-gj{jBKZ)T<I37t&!{mVd>7gKd==T|b&P`Had3_`(4dCa!JFTiPKUY=E&y
zr2kk~-=vDAGL2r9%qjM}!Acd}DG)_Z&PQ3Hs4!dGc@^oZwX7Yvx!2Vq!6p<$b?N4X
z^S*fsf=v*|qHl4&Yu93UID8ZH(UWs2%y<NKiG}?b1xOE>gVxFBtKj!BAw_V?@@4F_
zy3rVGvwA%mV-a3|tqbEtVFFOZ<XbGG_fy5}tR+O}qXt~d<I1$xm~ux@V@uLLz@lYB
zaFFj;qvP}2Cx+<>1a!RetBN(vsU-hQ`uzABR$b_>)En6-4Dv+Qo1XW<kpeSg+`I>_
zopH)TK{fUFALVHSQ6VEoF>_Z#^2A(jiFhjXiCppH#$&4_W#2|(rii+;K3M>MK$nFf
zO!)nOSvV>x=ZtJs9^keZofN%)Lfx*myN&)>7CW+i>}qBl;~g#2GF`DbLUxvno!wtf
z&x+L=*_RXKtB}Q|+@QNH;8^-JE0|w&I7$Jm>DNhY^?EEPkMGfonI!)j7x)$3g0U|7
z_wH*PlNeAhMc~^oiElv(i;!a`YRg?(DKohzBeI~w-l`bGHYiea-%Ny<2^&{<x-Q=g
zQT+*XchdoR`HYig;6;;fh%bO>^86UmB&^RIvD{bk+XsOT-pgP|F*C3PmIqg7-h~^U
zmYy6``>WkAR@FP9Ow)3P?Q<4|;tF^|p}%Hl8EL`e$llwpra=--Bo<oi_A9C)IXHsq
z|9(JNW+iMNq<tz7jP!PH{}<3cW2RV8n#cXYv6S8T+O7ElqF*l_7h5dZRC!p9xJ59e
zI%uTcwLV|S^8&Vncv$70!FEsbfDf3WmF)mz*^E{35pf;0+ifI}`In+AS72BPQMb47
z9JX6&zNl&^OQ)vAp_h5!!QHYC%%XQKtA!D(gfS@@%7iJ$e;%R4T((;B6L%DQT>VMk
zQ^ntdfk=KIho7sy6{@r_lPiUmGA5e$6CU?QnYQ&XAg^EZI5Oo7`M2y3D#K>NdV_eI
zfWO|{6HNrTOEH#$tZe(SLRA+g3+}lU`z5{n6h82PC!gr?5*lI+fqKMs9Rc61=Wg-q
zWBO?gAIu+`5cz0B?3|sDOC=Z-f0lqyw-;$$E|Xnbtvp%uYqgWtswNF$zDuxDd?zqv
z#6+}Z4UXwPI<}<b&tqFwT?`Zn{QhyZuya~jA>vNkJ$2OkRv~eAHI=b|<=q(RcAWV2
zzK-E*y%Ix0i=Id;^l4YQH9Ub8<kT!+i0DdJvm){yvdJ73Jqb09thxXu|5u6rHn)IU
zHa$&NwSD(Srf_hJd?T7vIDh)q8^f9w{Lr;To?%Ri`4_=OHUdkNeoL7|uv<wm<EZ)_
zqp>mn0vqMC+E|Sb_Id4Z_=yqcIu4(sBP$O**rNtd{upumdrZ(84GmssIwrqPv&KCw
z&Iq!xSIPKUb=?`bM`WVgJ(znCQAmRJLa?~DfYOF1xOPcn;Sey*OJSX~QLcITC5y%L
z<8W$PZEOcu$;9Rm^0&`gI_Ta}80+5wi1Qn|;56HUl(t)VW@@Bp!(7-OoU$YB_Ye>K
z-l#+*JdBy9CiV(VSx&`>_=z(VPKiIFya!^U#ga9#Ntn&i8Sqo{paRc9i1}8|f_Oco
z8;tWJBRO-dTsFH1vc7c~pkmUi`s&lzwT(>Xf!@w)SSM-Y0VTO@0Ou(1E3zEl;k46g
zd2J{L+`Qf)DTES==*uJUW6UBEDs$aO$CHrG{zY1J=9YlpyA1TI=<E@*vjCflk!?hy
z@NWm)3Pm8hTt;d005L$$zg-evDF|v)73BIgZnmv^W|b0m@@6UUl>QAg%;Z9-r<Lmm
z-s}BG9>U;<JU7~%t`6k_>{@ExBfHeG4!e%RY0lcfa$v5#?9SpT7g!Hjq;w~mS(9_6
zV*-K4p6(UaeamvQ#6l*?a);)scnq==k@O(1LkMpxYP{;n+uR<#p>7lq+)d=fx_xE9
z)XbN}k?|U-_y&v$%+P*oR7RkluK5iW$h;>g6ZFWyu!yA%tZuKHF!O!e+He9H{<Tx7
ze?f&!b;g*?*qv;S7R8K@g;R;a$lV4il6R$dC|MNA0{%~=052WAm<y5Kds$Gc3klt_
zYE1d`L_WGcD`lQ#SM8&Hh?vr!!6^_yMSGEFZ#)uRMDB^_3$vk{pG#G$&)xk&BI~#+
zK-@N?mg;w}6=r%>IWVq&ff1WCq^}w0CmC-lFRY!3|BsIBeps!ho#`E8#IE{NmN+V9
zh0WpL6Xp&sXxSY>?OJEqBg}eLJ2Ofl@cBz>!5`hg%wdn=L7I+2eWn1HKEd`1B-J9B
z-Yo5~Jow%|d)|P_2FTHF&l%z#7qT2tcKe~+sfXU=c~uz57bylwc!-yaIp_xb_pCe5
zjLLF3eT;N<(#*EVGmI*O9_`h<wU=mY0{t!)>;Ij739E9oO#qM$e}Dh@rM8Ss-ec-P
zNe~Eto&1EEdwRWj(l?&?54|l-AXq03@oe3RirAz0lI;U;S6#DHu2Jh`PODm%^-d=O
z?nR3t7~z4VO&YrT-jH~af&Y|~sJ8t<C{jlUqoVecRVG*+5<PU?Q=am*W;Jh-SNX!+
zwEl8}pwG}BHsW@y@<^1FKNqdlsq##Ysra57I6)Ych1&hqn%w(NpCq(IYDwC1esH^J
z*J{qZy(tMGvuylN-V#e@pPE<t(}@PWdl7$*HKU>jjsFD;aM=RP3-x!U=jy}AxhtNd
zP*kvLbE;~mkU{cU8d9lOkKgJkAOW$6298O|0T<~Y6;(B;(9Itv@vVH&Rkqe)|B034
z8jkUZ{y$Cv5{&x=)6(Hf)HOf!Cy<X2yy*_Xl2cQlXnPqb&v^ks>MRCDs8RW*Zd%XQ
zqgNt@yKwLWSI{xHQRS;MkdeuTC+*OeL=G4&5kdj^)=4HzKf~iVZ*ILRccwt1Np0V}
ztZBGm$X_UFx<RTQAOXDjmY3<qhZC~)YfRM#iL&OuJGPpL;V-JGFA;sG{0h6YDtSL1
zC0Pa}Zt<UNh8T8ui%Q~~%W`CTURnjz{Q3fiT3JW>qP^7~<07AUttkxXeBosA2p8~Y
z(b_uunXXIM_}P(LF6|h}w^hu}rf?FWm38Fw$BOleqj+j?LIhG2;9&EZ2`en4D(t=*
zu_ykJ;|<=`(Ubg!h&^SgO3X`d#KC|FkD*G931y@aM@iu#!{%ft>8IW&B+qq_);1Oq
zP_a?}^`$G#)G=lRMpMx>)3Y%Eg5x#+2ZwCR|I=CwS1Ez88Ut!o-A&-B_}0O_3w{Na
zcp%X2d3okMftIn6V=UyPYz8U#%V|y>gjaR73!h{{*s!RQg-i4u8mfe52E0!AcRGOx
znoF|gTPAx(bHV(bUnCAy7GiMkoYZ{UApOh8^GD&LPuhsLSguqwUpKA!mbhhazRFA#
zFgYnTh#3y%TSZ!_d4Y2m;*TpNi&lb6ahnWJsUdufeCw>A$XiJFhSN~|mT<(POenRS
zixmy|b}+Zk3f^yZsXeTI{8P*wv|`obYe<-mAgar!8h_Ki`IQ~iO`7V%hB;&(VZ(_5
zCR9!Oy#iGmcIf7w6zJ#;%L$(wNPrsjGyq?^uTX~-`6<+%SPFljEko<OB+S!y4h<J?
z40tJF(PrcKyy(o&{CncWM19}1LjSAv0!+-vI#4eejwNkqzELQl9A5j-?{()J+)!}H
zq(EvR9&VI+39nYBer7q6?rY3WMhVKq5u2(a9*y*fd-QSHc<D94Bz9QFrm#T1&YA{)
z$Ffh31GNj22zp&8RvoZXMTYLYkJ&ZunI_gHN3yU%Xv<JT`4uhw(K?!Cf^u{BmdUbB
zULs6GQvROq1O+Di>gir^QVH+KnkXgg#1cKv+u+{FLY%m5oVl+lHjYREhm{Z<g~k`$
zo4eeQmC}+|WoG?=1CO>E@BOWXUwMKs*$W<1pdSNPdA)&mPPawSexak7g3t5|ATbWk
z+V_ck!DFV-q9=X+&<YDLlDn}3uC`c2oGNwY0Vc@9fyW0Oi0zL{aQ^f4dAmG`<xKM7
zo|ycC-$;=XU$sfRxUEf%Ex?MjkY1vh+C$P;rYV_}Lsu<8=<R8dbTt~g3gCqTBw_(`
z4q$9~{o*uf9KDTyb4)SW{k=e306?LP?pt}7X$B%u$vcK-8ga&IF;_X!zgaf%ul@F7
z+o1;0u-Q*%_!Vf9Zs1cT1HYfcrr?ub945GI*Jr^aQc>Kzuoy~LcELTg-AI>T1ZE3M
zZ9W-X$B99YJo^9UKC<C8{{a$+8v=}Z0V<~FH&qq-S71Vhgh9XQ3tN4#VK#Jw!2*=^
zuIkl6?X!3{JII>E7WA_UR}W*9(o-;Q<!@x`A!Jls4nPbvf1g9wBs4;}mO%;F9`9)O
zJ+CFjk6DYa*N~S0&N0QY3TWfB4-(#nf7t8Xk5ryn7RsS7{s~hyyGzafIrHA68#y}7
z2C<sf<04lgg#OTMeKW*PVi^o&t-@$NMQVoF20%hrA>c^zIK04A2zyHwWmn_MwD(tu
zEO2YL`}3!asqRBxWF*7eK44gCXdErBK2_53ycR<LS&CeqXnk{tH0xBSn)-V#Rl0cz
z0}kneB>+{UVgLm~d@<`D{(01jr6)NHGX8cm;;=;3xm_ALuY+wC^ltmuw?x9_s3~D9
zbq4IJJE5_?`DpH;1TH0=wej+6Ob^zrvkRO_oHHe-q#0VeJhQQNP<H(|R{~5@!sfWg
zq`2eKGm1eNS={W|4V&st^P}*9SCv-mdL-XYj3b?R4rwe!_jfC5_)nefpz^3q5t*kE
zLnKI1sb{oFB-nYMy!i7^P6FkVZ8{v6QD0@b?Z@*Xg~+)jK{}wmUM>XXj8!0rfa6dG
za|@4|l1a9pJPR-KYO1)-x*r0o6yEi%&ehyN9%!#I?+hQyKGgJ@miC;kRPPyjgh|+~
zH{YKB1h3DQgeKQr1_^+VaiU|u9zoNDoo9a)4Y$$<*W~8LHD8RZTRcqvup$!%=zk?@
zDdR@pj7)Q&Gc}v%T)Ok)>_K0&I#aJgsSb42bCsE(XrB8SoN^PvSWMb726l#?bkQJF
zWab&}RRqN|F4mN$FS?X)t_n43gg8)njD;pr=kj4tobwI%IUv5J6dt06@sBm;&qEZK
zQe`SxU`wS~djjxW90RP)00;ygE4u%OMfNH@#!8ZS@LKTuU;SFrWE;&undp0@lX;Lz
zJW|KXv+<{xRr3|*b+fw5?WXXa%UV_PQ*ZsCwUl+MUA`1IDlb22iXdyrj>Oc9<;C+)
z#_#Mf4Pd&1a%^q5{-=+Ucn|H&AQ^+vd{^v2EXC}}SFO?lLO)`qxoR53zc*C0s!~ak
zV!EoFnVrz@&UKFvQIM_++B?I3>w|4+Ba8kQl8b9o!xcP*J^q;@FJbkE{n$Wb6JFQ`
zic&l5AOmtBqVtbg)mJ|0RC;nq7TCS=Kc<Je<iZ0rJSJRi=GCqtQ+?(&?=5oUsFq@j
zA$`sspaH00Bi%nt^4wMj+*O><Wc#80!5@Ob9r41$w}6Cxf_4#cjIF1@K?H-xb;clQ
z`DK&I5kZD>dKtt3_QxNivlp{it9gQjoOnihHkSl!yq^_dH-w+eDd@ei6v(xgy@Wvh
zR;r7l6v#p7tD$l+xRvGoQ%A+z>k7ABh}u0>i<tFvGyYTaGbe)L^srksrVs9aAVGIP
zWweHjf}x-V2v{jh7`ux>;&hzZkz{6<3N?3j%z*a{^dRZqoIi<w!Id<y&8>Vn#5pao
zcVJgSdIiUBN<?3y9scJof-D}a%<JVpns|s&*W%@FOdW@Xv6Yi_MCsx<b$}!bNNX<*
zozL~)u_kX2z@Qgrfhox<TpZt!7w`wJOAc?AlY#=FHT!A~XM%=iX`T_`i2AVqY6g#x
zL9;BPDAuQvA#%gAiv--$?vAI-qEzoWYwaipJwJ_E08|=NcMZHYrk_-beftCf_e838
zLnQ%O#RKSl_3CxUhL~w7pg<h0sT52{ct{V+6mMTn5OC(iq)a+%EBfeES=h>Z1f%bQ
zn8S;Zed3S3vEi(8Lx=x0Ixe7{WujRBu3R5H6%nz_*vvrm6#C0}s5q4HoyTDkB9d8K
zMon~}4hdgTy*j0-KOokg;lhcl$%*w`M2jf9d1y5cI)d6ja7{VT1OJ`nebTsJf*7$$
zTq+pwAsDzUhXK~Pzw-j4_5mxA>xeGu(%o^VCiV)Gi@yooDV91d7|O=8Kw$fP%tp#3
zcMR{k?=dRWLRa^3*e3=<Kvuo@LaBp7x3exZSqwXhr%hM<r*mVR`q+cMS~Z{pU4}OF
z@31aNtC3i2Fc+dqnA>?P#>#yYr;iGgjkN)#*O<hNcdUTD8<5vS@6i-}k=HNb=|*i;
zT5bADUa6Mu$)tk;aYZ2Up}S&<;-0ZmmQ<wBg)%WTqZ1*Lz+$;r$W7Qha)Vl6^m=X0
zxHjh8T^#&%^k0o(!cnaO4h25CzNP=MsY%~YM#H6<I++`?Qa(zSCxG;QkjP>34dUay
zm(<TX@ydb-P_}zZ46Z+>(gxY8BtKKw&9@%tB8t-lCEjm*=+6LY4E)pX=DxiJxX&ih
zpwX}C_UDy*R^o$WZl+XGM}E7cXflqA4W?YZ=uKK(z4<fHe948V9JhRE!Vf@yIMK)n
zPo+h$C<4uG00MaUix->ExXCbb4CjnZZ?{L4G63#5d08SwxXJNec$cbQqceh9_(N(~
zQw<%NuzCO$b|c91ZPqIk|K(mM%&<3QelZTyw0#Yc+flQWzDU{M(eC!Bi~Ip-sc}*!
zblCbHa=n)Zj98`4YRv+%E31S4wa|pmJY6mgZPj3wbVMZ^_$(ViK{Z-oAz1RavB)eY
z03^~e<UVDLRP~>$8$tMDj$;OOgP-83Wcwgnxsi-2`yJ1E=o%5lCvRr(V9dw6jfQYy
zIcW^Uoi`dp&b;9N&{!s40qN==EN%G6MA#$OKPPba!5NiT>WD-2H++v)Q~az-!B2JP
zxcHomMnCEsu#R|PtZNezoe@Lrc$;#^$5R!rPly^7QaN0Re`=E75S_FH$8y96P#<v{
z?!^hn<ylU`Dlg(H*2Bn>TSrM=OzhL8D}`t;HAyxpR2s3zbjIgdAV{Ih@8dAJiOiM(
z6N8;<lVBX>RZDlbz!ed1EBm7#0>vz<v;B;k{P^1a(H+G29HVf<?F1bv2U>;_9jJ9M
z%%e%ft-VGvzT<$jug$d%U`8+pE=Il+kzG*Y6gK)q`9A!WS8~Iml}k?&ti6nf<jvAr
z);SX+fOC0u-HH>$+};>;4aO4a&%wXj9ACs4x{l6(kM|nIs4jRj7sTJ*b(O-Xq)Gx+
zt7_j}oLt~`=BA!f(lb2N77)ej_Vc^MHaLBVB^J6oO-=aE5G?`}W*q9hGF<F-M9}JN
zG{1>(ODZJ%XR*SpLidA7VC!@4Xk|V&kcXt-5#sD3S2aGR8ck;rQ;QQ7Elb3v;?@%O
zI!+mq!b&q*R3}DKx0tPgSv3N>0;k9Cnglz3D<&mNU(kB_`U=Z9;OH6NoZt+&c`;mf
zGKN78`)7UsEN?Y$#9AKe@mI(-=<a26oC5Xc>zjJV&@oo3S4=QZW~hArb>t&jH2TzD
zB997sj97tkNR9)5yvds*tA1_qSx$k72Dy`~r*XJT;#7kf*gTvR^a*)&md~MYd_#(r
z5@j6G){u^yuqBenv0nm%K~Fcyvs4FTVd%o6(1*oxZU?Uu4v^r=Ix`D~1_A)BNyeOm
zdyUe=HSSOXD}+l!KDOk}+kRMPkh$5ync=5F$z7(NAWBl{LILF!q|=r*pVPw-S=$nY
zy<WnImy^D~Wj2QBL#WYm)x#GX0n--?1U9BeU}<e7PKVy#<v<!ATmD#Q;Dj@r>QYMp
zVi+4c_6-amY!Wo@*ygzL=qt_9AD?hMu_gDApEuOBUH$WV9ssO#pbgOOa=kf=|J|EV
zfT+9<(#o}UU?#;x0Ic!RY6LJn^flXb8i)3lbaz}iHAjv~cUpJU>Nz?GW>x)z$Nw3u
zqqJ^q{20T=Qz94k$~4s|&S<vwV*58vR)2h09>z)8k<PV9anjZ}OJth6SdAj*hQ*1d
z7>w?_piMhBlIOS+778w<baC#=sa-4mhF(9CE6}wsKg1)M8W5g*cZNnF%WVI&r*VQ<
z;L!Utd6IuRJ%)WR>svu+tg(&$$jnsZc>5PZum2Zn=m889w0?_X6sBv94`J$H-zc(d
zZB<8>1C}Pr0Hp$q4^Xs&9HNh1ZELN~av?+15_hMkl7h;BHE>ZQ<%LhoxM5%8($=b}
zvn>f)o^geQyvlGKx|?q3!%>X;`2bYGRo<STdl@-!Zq3-~TK2*fx4AHULHR56Y3$bV
zNpb@0(<5k|ASRxN@;ul#I|^}*qs;joAA)Zw%)2Aj{P7iBaw?E4hLJyr9`mv!79cfL
z;W{2PR8ip%WZ@?rHGHY~aHu!g{H{d+KP0OAF#5%8&%p5$voQLHt5!PvuHQ|0!`?mh
zz-+!xd4(9XCo%*StX}eHo+@?*Sv3}RRu60GBxW`MgFC!${gSeGGM@x*h}}e4I5JPq
z$05sPLg7pLuux+UTb3ytoXyeU%T4Y2YjRHL5d;YG&f4w|hkevqRH0K>^3RU5jad6A
z<Ly5t@UR`)pFPaMAqLK0ch8r8Ui6r6-ZOd+doJRe3tXM!IJ*aTYa)>{OXA8->c^)p
zQj>wIrsq(!>7NW1tQP(^-B+^i&Ial5@tC*vQ(7*&Fsd9Hmge)_dr>Cx5tmmEa46Vz
z22F250_qO<Ag5jr!j$=sn1yVj+2@ETe|C)9EmE=NlHaxVVtw4x3>_Nx<IwCX649zV
zZNH<KwsX@>bo|?3L^>g!+8&-uZNmc3fR$!IOt*juv(f_yA8SxSEWxxC!N58cw+fa<
zc5OPOeBO%r)5{vehOy;M@$I1QPH4*&m-^-$)`cE9L3bimR(&|^>FyHovqHmeA3IRe
z*p4f(V^8H%>{M8F{A8QzNVZnk{nq*1gal39lbmaEnwl)dm+KLH?CyaLuYYYHv8Q7g
zz$8*|(!iK3nHJ1D9UzjP;VB4wep?^0lrRs{aaVGscBKN}C(Uv7tGGa;fGQW4Dj6D=
ztChGju7wFZmDGl@V$!<Dj0EQd{?3#3PC+kTp&ZEzCYtTg)Sq#Y8|jEz?%9A<@ENv$
zWViUE^OonWaaeBUxsY8kIM58W9arkd=NMM3Mb3v<J~W0+wfo}N%C3z|<M7AWqiV|z
z#~GWUh=nwBTO&;k=F9uh2#5r>zu2`WGMtUw$$kYlsJq3Ei^Knl^7VfzatsX}KR^*5
z8BWegxk(jEG(QwDh^cFrGq>c<JCyt0{^#nh)WO~*fz1>`uQ^6_!5i>;IxylDm7prR
zL%+TvYo-uQTd9t`#M(oxrW%C4sxmkO&Ny^X9%udtRuVmqN<r&DkM?LjB+;65?rD=U
zy{EL}cPJDCpa93$j#rQ$+r$}21$SDnOCMQRb)Q3pM6!?#?Kg2?zZ#&$`HL)W%?IJT
zTLR@_5RKGk+UcU{hZQ%TnH0Bbc*1kbkJ*O$=@eC?$9c3I?&x1Rd=kqMW9l57WqK#%
zunF5itZ=YhRs><0Oc@eu7!#>P2tKGDIfMrkkg7bP9sxHrCo+(Mp4^27F{?Osnh90t
zj9yk*!B)Y!n|XW)rK~v-(v7$4q(>~oQ`v3meAP8CPz)?e5N)9;XuDbH0rS}buKW|-
zYAs5s<%t97^X1Qc!yuB=((3{fw=dD3EKmDoHOpLusX!0~Ft~f+a}&+4x34n1q!AqN
z9*D)^TfJ-`cae58kXlN`huV;vC5mB$mN^%+*3gO2(r)Ym=**$Ds+w4AkYp9g+)ib2
zH6`zeetTpY_IOWrm6Rt~(Te8Cq>SH-owCO*aW@QFpG%K@qMrDr<mmV++Sn<!+eY;P
zdmzJ-sR0zEw05Fl9f&rjK}O%jfj;A|BvcsF#Zi|*YI0w^W)d#IG}R3F#~ZG(A;#Fh
zG+#YDL;HpmUlV&rTQn&F8G|aq?m0xZ46kg8ymjU}k_ZM#TZkkcnSz_R_%1zt?Nzoe
z8Vg|Juv}6DY4JzelcaLTqtl(Nj+(vtDL?CcoR80JZ>MGYQ1BsRc1A>{<Dzxw1pjg(
z@nkz}lPo}A<>ZO@tHU82cS=ZW!^&Gp6nJ9a^lps?C+7%nxb&OTu$*FlJ2Xt3uSFO6
zsYJ18jB~j4jlE~3aVLcpRsY(YUL@p*Vu}Sr#X#RbsO`q_hr@<+fax#>$8#B(M%R20
z2f~7Q5OwzBoC-^|HtQFkX4EnLA(BJAV6{`*PN-b2FhH|IYd02j)QTrxy+z7cCDi?F
zxj6+s(9~ELr61HZ$vjsbL!N<T!XhXXdcbWrCO0?*2KZ?&2^4mPbt$N7i#Q?Mp}f`Y
zrPS{$ilu8JP2${+ehMk6l+ZGnCA7P7(69b^f)G^y=g47K_ZJ=1CH3+eD@y&G;7N#{
zUa9i{%?DfI0^~Md&I1~}TTD7Qy-mgbQ(~zEwFlAM!C-W4F<291YI!?!msuYKBbnqt
zN}QDEQ%kYU<b};t#;>I7WQu%<;Gt&IAcf9D4h-Y**o??b!rn+@-pnNwRSCCN|JpwX
zpbCsX_x2Kc(&7?7N9=3Di{N(lWu0-v{49M`D7@oW`{NCw3lNBqjPieJQ_&4MPJLoj
z=kyvLcM}WiBWE2EOo<Eh%aAc1)(MsEN>xyuE;*H-tLh392-eKmd=*gUk55|r>+<j)
z@u&r3G4i14W6fuvNWlwEf*Jr#M@KqmEmEy-`I{FU!-=(Rj`!$0`^R?8_)3kw8wVQb
zqpYKoRuVDrnk&E|rdI|nxdj*&&WWP5XL>1*_s9-G0f3-g(v3bbxA4(;@Nb1Xe~VuJ
zxzEEIshA_{(vzg6-zPnf+RD`A+yY$zkze_n))7-{5zdOf^FLoJfVR!4?*%73l7WpL
zB)no-lI=M+8ONtKi9gemvV<tuZH@<itqc6XQkPgyld)^t0SgCIKcsok57gS36$e^4
zJ@wwpl9imLB*GXPK(2UBOfW7D_Wy=h|ElH2(k*2GKY3ETZF4CQtw{<B-cnP18>_^q
z8doy7=i!2?7XLcZUK8;Q1Qe5Ko_G~n7&Y?2+n0ln0``j4UE9^o?hD}>$<{BZ{8agf
z01}YsI(SbQbtd<CVIcr_v6`?9-F4Og+6@1(Gw;tk0&F${XehuTu=rK_&TMI5_|pIW
z_P%!+V!m=i<%8;n!#Qg{bOZBdcBX6EX*dBy80*?ESp+^&vvx5g<S;x)X$usf{#elG
z;b8bxo%N_j^(T{d+>W$Q;6(a$Yy9~yRV~W+b{91&6#JLM^SNSa`Z2O(nPB!X6j`~D
z(BloJ-Nv>AiB}yDFTt_VV5)&I45PM&S$-Kol=vsnV{{#Dbu#3S6yMMRk``!dYtDiL
z@mzNgd`)Q(L?}%dv+3$PFVvO&K1AQ(lhtPUQ41j+$T3FUC(r<fmR5X?Qsv5-#8-)a
zmDD9UJjw-JoaxlcA%J38I)X~<Y6z?d?LN5d+a>{u*;@fM<Rj=jraQG7hzJoYN0f;H
z^^BwH?j3)AW1A3%(bPS0n0pGYdmUd`6!qSIE+~i2eKX|Bm<tG&2s|oH5x3zM4RpQ2
zwF%Zl`p7C-SrawHqmyFb0h9BniTH9-k7cHKV%t}_SANOI;y(2-yCtNNNi%zpBsU*F
z*_I3bMALb1=mno$Gca`LWBE<O)1@C_X}vsVwUp8oP@(VCRrx!)#BA*Fb3%+=xznm~
zmLk5<n_@Wk171ko1`3!YLLV&?sZuLO)`!-T4a)6@x6)$#MfkyYo=-=!p6PBCAJO=Z
zl8|>|<hLZ6+HSGr0z-o_W2+*fn(I15ujAJg_EQXn;hzYCynM&zI5BP=P=6#Kh-tHm
zOFZ)Ru_;`ZbkE(!!iGYLupbJc@tb;1gSb$BL(h|DLofW&3-@A@-(HkI9P9LeET$**
zHI`}<mpxyYqRLPDi>jPIrpCN0hzDi&@ljXa9N0g)PF=C6b7u~qfuo@_3v@<|Ua)ID
z0a{Z0fUKVwlwL=!NS3kvM6)V|grpm_%W5KaIn2Rd`$#$uJ*#vwlz$oE{L^t;9nLZ6
z14`(S??wSqlOaTTCwwYFvZ*~JD>OOX7mrXDfU7NH#+Egkf0}V~3cioC5Wjr|v}2mf
zF=2QGK4<5ONqP;^@a<l=Et+6Pb^`|9ct6vCO)d0d;xxLGM%Su6`PojKLWMX`F4%hW
zhYW=-{g!VaM$<Lr`N!|DFDzy7#|YPMAy58%Q_~Ao2h3mV&U^h$f|zAB(LVt;``h74
zH~T2^7Auey`uj`*pUcTucSo_>4ae?gvO!C@5)5yIBpHs{XCU%4zM5(JU?h#g<Cr^k
z$?=CS!8k}vStQr4XkRsx7}xF$jq@vZOy=}>C0x}{BV&|uw^ZMf4Wbd(L`X-cvWqPm
z&8Y=49!&b$+3IiaKXV!?^(?%`_ZJmDo2K%T#KHnX8^f(8S9|M0%Fq%l41-W>hL)|X
zZAZig1VMlWb!+vXp%2y4KWu+-_~RfnCDz{L8~M8O2xs_Z{jwN%7~mvdtk9>0cb24Z
zEd#<&eYO*D1=8Vco1v?I)qyRM!9-B~6|2xdbd!(Q)OnVlvB;PXXAmwHeyhxrl+Mf7
zAO*d5o1#o{>m2Ux#AuG{_l!&s|Ibs9XJnIl_K0h$9tu<z!#H{vUx9oVf9~~LGu7Iv
z|HBfb28JDzp~K*r!jkQ_$6_a%CHdnu7GrLT9VD|U+ka%3&|Z=Ca`h5Oa*nwP1WAl(
zj=jBL^oOZZH};*$S!|*T>}CRai6j>=&z1?|^}Y?g&)=HSj5=G2amo$wYxw?1r*2lc
zz#1A4g8t|cP+bG~KfI{06+PVyoBh6QRr91WZ0(Gw#<+W7rF}Yn9%;Q}%2aX7!9fj)
zjxs7<i+hf=m+c4Qlt(Jm4HR^p4N;lQ&jE71daJN`EjFlaQDjrZgam+Mgnx^r|9ie(
zRN@2zV``;Q`TdI2FYqY(f8ghf0}yY0bEp(X8<nZNKDo~`Q}J$4!Lx|OCr((XkC6_)
ztdO&Wi0j(M^<&V7O90I1WH#eMm}3*$AA%s%vXHddchjoNrC4aFIqbG~_xL@dv>r@u
z%bpmrPP!yKxVvW>0`@l>uwwwt4oJ47DruM2m0c~GN*I%Le>z7C?0EQeB^IQWG4L3{
zgewnO@1s_=jvS(r%d#L_C37}PcECR*5Qd97Zw8)#bDTkPCL7H1As}iLywz##t@x9_
z&XyVM<@f4FZzNU{MzTP<KPvpNmMdlg$dCCLsccqFLTx)6u4)PV7ctj@bqit|WDsBC
z8G5W@jdp)#AO~iG-`po0AqUQJ$6NT6nL<^;eEl^paQfWSoaZ)M<3`01CcqnfgYp1}
zrMQ`klVx>@M<jZAy1ikE$U7t4*=f}z`ae4{;Fnx*)i`of=qnyftpHMXUX$@Jl|Wab
zZJb1|`%$H!)=y&dQp0PX+MWZ=vE}AUv`B)5aHcw7n8)uW@2j4I`2ST+N4@PkYt4Vr
zTgxZ+gFiFDBTUJN8vfrexu4_LwYmpLn?AI^Mx2`5B#9!2+2^-85$I1UrJVg=uKHtA
z({5WdI5uw9M>4dNXE&j-Bktwi^vRi(TkzuCw{lcwEFDoS&|ke{Cif0+YG0|y>dL2g
zjh9-4z4=;R(^Y}!A2?e%fGw`GUgC1&iN5PC{%*kSH3G}QIo8M}qDg1llCG#I0wfV<
z;x5I;HpJ<T?ZG$9Loi73eU(7|Mc;YYQI|Fk#c=v%Sntm*)kZc`?0GiSMW;4LD6+Nc
zU<uj?`@Xo0@ruew>oYq=msVxD*!o^r%)nLVB&|&U?30auHJDgz+!{cW;DCzMfU@9%
z36*-DB<}S0+XkVHYm9^415&x7AmGytC9UduFa3p0A=MsHQ^BPJj6k%ApNS{CxFjIY
z+s$Me&6*Mc=e?MI;)Ti7;(+4f4xcX7fL^x`8;476z_o#|&|TqHdigOh{T_5G8oSMT
ztNtBxfa8s!D4zfysRQR$HLJHq4ba=qOXxDdaQt=&Q547<d#(I@y%c0TXQMkcVsY})
zF`_zvfcJ<3<Ue4m&98uEECI7Eo5&DNil66}wM;l8x^2`qOiw@3Ms3^CO#P~vLl;@@
zwMJ;GAa(5fGHDE!W6OvkBsNriFueydf;YkmtCZe!P+dWW-k6_IDu|~{cpt-j>ap%-
zH&SWL`ZA;?FPNLk<=jlyrkm0D3fl6?HL?e}2nMmCXl4+tB%P3mGU%0c;?<;RQyz>O
zIJB2(!w`Lyaz#v~5A9l+qRdkk>yBo%I{<`Be_S|j-=3>~$13|%>2>iNVmPun;BxpK
zZIF&?N5Ef7%3VhSZR3vCKm|eDlv%I6srZvM7PW;Xd7?=(Kffead%r2-Tob+B4@;kh
z8ls1D)<GaQl2=If;C?;W?#uikK|1V6h7qKef`c-yAKzeU&RZ8<xum6()bM|=4}>rz
z$vDj!F@_*?;N7&(B9OdKa#BEl;WlPl$+aNY24w~W69Bw<nzv*~TPX|O-qN+=7PT^D
zWTd%`dp2Rn<Rb3*<xHG{@=H=L^3l=#fI3u3sV=7JmQmw}?}}b`4Ms?RuTnn?Nn@e;
z7h_)2%a!7|xm!FSqW=m6vk1}@njBjBxrJEC`dX79R~|CS5dhLb0V-Ae8Z36)a&QZO
z(({%vwMP>(-q``eLxF*DL}nP9TIbfGr-Clx;f*#}NrXRH+TNobXyL4^8aTfqGSubo
zV5#VQPC?dmo{$VL<n}jb>oiuIgqkdflvvbv3C*a<h<zJwzMR88?ZMk-!pX9eI0rIm
z)b6pf4PSzh19E^(%o!ZLKKXYuZmMyr0-JcjTT;DcYI_?R7ebUmQ*M^r-5{aaUx`1_
z_u5xuwfwdhNDn(rm06j$Zj!}awbIz%ic6ap*_D6W%kc61v-bYbws6-o16)}~mvAju
zlK^5)niCN61CX2l(ZTNn_dusg{JZ%6rAJO?;Yv91K3(u!9u#qNk>!;$xS^6>mEp@8
zJBWZ*qRn&(x(t4K$(lFQo#=v+KsagsR_LVJ+bq<#fTqc9e_z7$3CjyNM`}Z4%aB>W
zV#l^<g7reHz2$nrtJ~dB;bF&LJHv7rtIoem(aQ_lMLD<Au<Y6Pl{<&h+WPF@60!<P
z>(5klno}JX#S>Ruk>UtDx@zqi@m>GjQ0iOieek9re6l0+=oj3-y0#3<3qYb2uh9#r
zZPgy6{JZhnd^6XUsBs#DQ0{>Z14@22HsJ9fDBAlt5$E7nP=1aUjFEZuOv=JQmfCHA
zi6Q_4b>3Z1*-;DW(#LkSUJfIy{|3@G>Kb{f6?4jD4~`1c=71vU&D}7bJt{}sT3_aS
z4qIN85QdkTpnilL0hFMkt7Rr-*)?TeLJ0%TOSd0U3?KS18`EsiWga;@VLPF0(jx<!
zKnHxgse?LR!Z~8cKvk1_K@mHAMbDnO*%)~yQ!M{L)}F`k<76=>wIw>S)T?NDT`x<@
zOUO6RMFRx~3YUJp%uxjlxS41e8$M^m03PP1T<cj8{HpZ>fVn*Q8K}Lgzp+^g#KWT`
ziA8XH?Lr94dXHi^IP^#okU{XjcI5tX1{#@$f|<Zg9<KcHRBeY*-HK_@A83$+<5NKf
zx;0tUh19bE?=XLS>33M(Xv~wSGX@FRlOzJC8qL=u=k-((qH{T5#NUXWR^ib!`A8jg
za$4&Wnj6z{48xCe3O~q;EFSxPm4^Z;x1b>>3sBu<(VesanBs@WV}gEOc#9YI`UddW
z@L{6?&m}T=imJ$#+D2P*LkRE;0;;^s65!!7Q&64S*Q^4e`5SRw)iRR(O!mW%OMg}5
zM0%vpghI+~1u5#miDg#}ES-Ew<($cFQhh0YnE;Q+f*QFZHb3N+!T)&p@e`7etVKSN
zVuF$XkC5FvO8sE}+dl=#C%Dh!S!fPN3UHO*ZPYZrs0SChNZa=*)kr9|#6@SYe<ldY
zt<^IcAH4um^vFY)#A)yea~9Axh-PU{>Pz+OA~K1jzCFI38F^C~I*{%#VOdB&#I2d4
zC3(zD!Ubcx&YFXVEY0mjW7naK4|xZj6W*3jpgsSC0fk``Nt~`l?yh{e?5?U~{)l;d
z+eT+gO+KwWqDDp(8c9zdaU$_c$8c#bJZh)={PgfJ4bgO2T6#P+$BU${g{A!KV5K=p
zKIi2+$S9|bz&unt{vj`H#Yo&KzpqYQbPH(pFvi>gDAbj^)c>08nT@zkv$>6>IY`d}
z{(_A4-bg)})_;tEcP;Y5$Gce^Dx9%gdE_FKUBMq3_+GKvtd-Ls3^iedQ4zpT$*6Vi
zK8BW~+y_XNWdTCuYQ1SYbX(*rUb+lg*W*`{4>pf^2(0HYayi^6bK|lsm5f=?q(|`=
zo+7YeJ!zD%1na7khtB-zo67_XYXpRAEA|fX+af)%1j>uu)Q_-cMnfG=`k2B|U<gD=
z#-knZrwhPYKd}__rSlc~JgeLbml+zhJ00gwfZq4qFdc!ZQcI;D2nRl7>$oGd8)YnA
zM&BJG9hZcyLA`=++^%f&<r`E=JL8;y$>o%T(;j*v<}P*ZB0m&cvjE7j>v@jUS_Sg_
zAFv(apDXBJ4Vz|RMKbv*g=4v~%dpjw5$o<1%^_|49Pkmm@_r3MU#B31J>!eEd_<H)
zQ?29&*;yhn*6KOju)3LN0$#7mI{S9l9=%dRUTxIS(%y#DDf0mtiDQxlB;OcxXE_S@
zAO$CB@ff~;6drUy2X=m-OFQa@xNq6f;<#8hxXv8Aq8eGc4UG1E*`V#RjF<H~>F38j
z+R7eSTvWotzkcdxf^B*@CNM8)GFVb75$nynHiTF8DCa+;4B&wd)U4a(?!J5V*$Fzl
zcI)JKhl~|_j_yvYBB4fxqJS@&h2hE?i8-z$h;^a*Iqiv)CjnI#K}>X0O>3e%LUuY9
zS}WosYv7n9bW(U8V9e=bDGx=^r#c0;WHeSB+abZ2liTPgJjT%ioam>Yd=LoFCDS}e
z&yueJ(;*;>I8gG801~cnt1beAP?T;9WdC-CtY9#kg}J9)=1wM!(M*Q49R5PR`OGTH
zk(Gzl^y$f(o>Fi^FI8?jm&s{Dl>M{S15{`*hSPQQbGomY%o!Du$y4%#F+QY^=j{tI
zD*YrD`*UvI`WmbNQA-K@=ZP-7)@AW=EAVL}e?y2}Eq~q|JS{YT*@3GVs~__(WZV^z
zA>FK;4}W{<>=#O_xkY9R2ZI9~%)%URn?koSJ&%mnuUPqw#w)<zH6^CP3<oQ&60k$d
z!W-air(siPSV;uy$#I>_+tVvNCP2B!H73<JifeqPb(!*H*V<0;(d_*<+bF)rHbRzS
zW_Tm6lG*<K{+2Zrpc}1*ytf+QTTD2BaAqWvBDK7VBwr)&gTvHGtn6W>iA(!4cKRUv
zXon0U6GjYd8LS%UvGjHvDg)TP$#)7Ql_0tQ6U4`))dYClf`7}kvP)OsFkShSd>a44
z5Q|JPbIp%~Kg0oG3llBq^IZyn{h-U{(IEPTq)^2Gq@R|1#A}PZ)>nrj+}H*BLbWHn
zFqnr4tQFQ3_tE|}@P=@vN#vJ^aekUQw<IUL>KGOAtT7RLy(&QHw>KdTCzGtNpZIFi
zJAb^{p2;-LNnFnmT)oji7#DVAQ^4H&L2gUk?l|c_KsL8n2|u-dJ##zWEU0dp(Lojt
zCvL?SaWP<-6Z^*QJZDu5(C0~8v{NuC6xw32!$aZHzeY2YJd3N6p<G|a=>yl;>MSOU
zt<&)vTvjHFb-<?8vo`$E4gfpE%ggMbmP@pYE6*>eO)l<pD3QN6YR-m=cQaEaMxRLW
zDYSyVE7;$)hR$DKDs(66TM#51zf#Y_H*hN}q|ll0SQ{}Dt}8*1&MlaW!kgr_B2C%W
zYoTqoIztM;#&(!6OE+enJ5K}HbBf(1bGXgWd2jpi=9z-uM+|&ff3))mfFCmR-qoW$
zzx?Xi%N)l8yd4|_rZ|HHEWC`Rh}k}9SQyO+h+wBMQ5J@8?M1fP9|9$;WXRU(ocX?T
zRqCv0&_(Ik8y=w$Qm@YdtRAv>0M)$6PEyLzXAF_AJpqcMzDG)k5Y_ScfagBw0^dIG
zNYt8;wRTwCHmQYTOW_GIy)w1(6O<qul(2QN`4)4MTMAq(*9GoB-QYooVw3wbSwXJ5
z3*z<VD=&-k1oD!jz+lx-s(m@e4Ng0%n5MSq`{3fYjt7lg8|x2^;`sd25TdP^E#%fP
zI4cN5D;wZiI%-IohtenrR1<0e)vL5a(4a=&dsW2Iwou|89k>Z|7gT^Wvh>&0F=iXD
ztEb(id;m$V!TBEx$UMf%70o?Djn7$L=oSsPvDnf}Xw=<%dCd=0OxTe`ZWVGVeCIk#
zTCA#SUfi4I5fD!ncIl^Hf5!CB@Y;gFvg*29b^IfqT)(vFAbp7?VAMZomysAPS_Be8
z2N<vVS{pMRoqvOyD9O?n>CiD-(cXmsUH06jTQ(zUK-d({DWZ7`rwe%!^WQ7Jo@NmF
zLi@I0?A?2_6^yfwDBvig%QBAC!UE7(`Q*ag(f)vH;MjS1->Y)0Ym0>M3^SJ0DHy0p
z1%{G&aA4ARblc3+wTiWDba`kjfb9+sRQdX_Ug7`1*3^CF=Dm@+xodnE8waVwY1r!W
zIf|am9Z8n%3#9pNW03{8fhj^ioRKv;iHZF~gEI`rmd&dqpYT?T`HPV?-{jzHhwxYP
zlQ7@G)|rhzChbyr!S@)}R-5i7vjbzgp_ZI`hMXHdbtppiyfDsQ-zhqc^FvIg&e0!k
zzPE@fgpaP-yB_H|qgAwS@#ld|<jerW^LO{+KsB{;O04J0`gms5zq>xmCsOQ*u{xEz
zO*?9cWB~$Mr{y+f9gH~f`61zTO^wAyt*sGBytMPjN;qI0n_S-m03DJd1D5_jD-CaX
zrpdlBv(|@FnS%YL&|nogl+0?tVV9am!yJ=dVCweLL2dgbST4|<qpuaap;_MlrxLo9
zSEuJuU6O-9Wuk5WZl7L`ECfU99(ZcsszW$SZ7x9jjvwsss_zcGvQ1%ZXG@$KykyPU
zq~Y?Xyp`wFeBvE~IzE7*B}nw*398eVs1kogj~TAw<cd0q!qLW9ppwlSID=~wo2>|v
z$X>0mb9xkmbCHKY$Ev0FDCyv4RS`?$Ko6+FE!7g6UYW4LVlAx*M(kT({4NMpa~GvV
z)!bv3M<NJAZE79ZB~~!4Mqh6Ui;3p+Zy2oanX7AX!44s5^yr>3k~lO4ucUBN!Fecg
zT-6Ey5E}7e=$4C#*S5tj9V;2VDbw*ezC%P+Nu@~f1#H3wJVrqN-TJ^voY>EQF~<-4
z!Nr&48-o3*hz?S${pwV|abuYY@RU^5R=TKh4J9TKj=1W5K{>gZ$4Iq&fJ|Hh^aOAs
zRqCoS7S#b9<2G9MbMkDkZYtce;pc2fC(;ygft`p2n~gid&w3vjh$zgt1I0#=DlP=Q
zc&n99q%A{NNp6k~UMIhH;q4W?*oUShYc(6qwK%Aa3{!b4O`9eJUr+m>*AxxKGcANS
za+f~$ci%U)R53e#D#;iwSEYHWz!dW7v4ioM7cy|nOl+u1<|h`_lZoxje2UEWic+T#
z-69-5>k|}O#K2-XisN6%Me`#TNAJG)Fg&fue_}S`wK%AM2^sZU>euMxI%X1aA2%yZ
z1^F3f6)A>|P$*<aSL(e-s*YKqLnC<kxH~hn91eLfCLYT%_fgti$cB1TKf)DPjBHVm
zy72s=^-#@G$YvuIk8>ljh5odF?EjR)1BXXC4Jcdw4j-~wqS0HIINXh{&Od@)t;cC4
ziP3~}0#-p9D-FRTISZ)h1_@a4xi{V~KiyI#y9^d4U!R^@;FPI^NRYMdzHL)+!{9Jr
z6&3Aww|}9`w?5mosJrcCf>REm{@2p6N?2yK(E)J~;0}sQN%GM`&(yJ2w51zKUiEpc
zisX$Ha=g8;@uHfYhpHL>IEr|TbO%bD35vD&aRaTGtmE1R-4yMmum4NjyjiXKRcQOI
zjpZNtV`n>Y@P_U=Wa(5P3%x35L&y+cOq8N7N4f~sxBw6+w4SJqO>D`_FR8gIysK52
z$ue962i0L7uO?jL@m=*kzq4fG9p`FI1)%;kfhmXQsD&h*@pTfho*ET38i}4eX-YSK
z<?DC4V?(kAnf1)hDPZ0b1t2bdicvQVNIq4$ZF1{fFxFvI6YTnQ0H{x7aN$2R1N84b
z_OL!GxakH<WA#PO85OQKfEc$KOmy}SPIa~Z90ymk--!Lk6Yia6LNf_vv{s^FnRg<G
zZ=H8pTmkd5Fb$@Fm7ZkhX53q#6)~Sv83qv5=xLdh2YoD|#CO1T<NiNlXY6@xp|DM8
zoQSQNWMerFbSw*9h65XG0i@*)e=EQ!_@beOfTeWn03VpNYyGq2#%F#Ai|$(ikp&tO
zx!{5A>Iw?5YT8>yG-CrbX52DQ)ASu1%KoH`q+Dz{&#P7gG$qB<i<lHylo|=0(-e12
zZ;C;Uj>N6diq3U{kVe`|)lxt84F^TAz=$f!AH|8<GP7wVaOokH<ye<_q%T%~U94Hz
ziIA0^_(+Yz5ZjZxS2%b<vukNG)5`%LvYcqlxX6|XB&qB`j+3zoSr2AE0Kqm{a^V{H
zJ~G|gFx08zi6vQ**<xWVe^@zhGU7>8@u|yyzEazBDpqTNrhUm{PdQ&yGV)9iNT2{_
zMzBA$MdF3{DkbGLi2ly*#z?*AoZL?u^T$`tTPqD`rP;$o&ELE`j)$shDT4gY&Gh&k
zq3$D+r9;KWvR1&ew~p{ORIIXC=oQoIad+^xMBdl}8abeUdqWZomVd#)(Ae48!I5A%
zd+LnscwfwrRL*>^MFv_R6;b8dUAL4<%%AjfPU;sbqJXM>v};XD!3%vT>~$NdXt~ir
z<{~l^X5PJLeXMwKkBRdbqVZ>mHKn+e;ep?9FrD00!_TFNi?dwnZj|y2U*c!%G@Ry5
zh(QTL0UIaaVf$J~o{qrNF%j=OkNNvbuIxpYM9s2-d9qPd;)J88g$;@@yfZEJaf{WT
zT6;awu4oOD3p!E!ka>(b<qJK-L^d+eg{^EGlY#SPDz)$~1B+R*OA-3+pw4dz0h$5m
zA}X(9W;7`5T>~Z7dkKZEfGufY5&YFMp7J~DEBJ0B=825p^(APCbwRy>?N6Q0h7_{h
z{Tn$7G_O6mFSK%u{YRMhTbPL<dT;@Fnod|;8M!@$r6$+4O9?OhW>IsCnmKRcf>puv
z^*149g)!-C^j0WX;-R6GckeWUv4dOKGzh)SJ}$5-g>*)no2d4!csFC&t}I7$xC)4J
zYcISF!8^S>UO2gEAzt!H2VDerd&tY&N&U;+H1d}bMRBmC3e=@_ccd8UhQhO#og&M+
zQ+N0FaSLmm>Y@KqpJ1bal8kK{venbC@BmFk91Cwl9c$r*Y5CuK7FOIYFe#<wF1^nX
z$ry3$vEcYWd*u)QIsg|@O^h2N@MewN2FrHv<Sjq4_>iu@T{Em<vfAIDA?+ftW#YPB
zy<>*BkK;0_mB&LtNo2erP_8yIyB#F&8^+(naVxd7t;aOPV9=kRz`I0D;>1KCHm$X$
zLtcoSA2d`L;f8?;!Wl^g<iB-$#ee}T=h~y1KQP)X0SNHAGzoD&R^KCeMYFuw8tD#3
z(`dENwV&iH8%KzuE|4Q9D%T9Bzt{q%G*f-A&>_Ql6`M-eSPEX1)z0XJM@j+fX&XEj
z;(8i2ul2B$B?#VZKM=5o=5KMF?A^o(Ze!A@obG5eSJr(faBIJdn}>7{UAI>+G1Ttn
z<T}!!c)cz${i+Jr<J1N-Q1dM4W~9ro_TWBA#R4g)7#?HTt^!1ax*H}Fp2>Up`aUSY
zUiJQ_8^9`AtayrN#YWSKpy4HOfMzl~6MvBz=l8HIPa3;)*v^AfXAg$k_O*PGuf;|a
z%nIr2B&4>Gwr!o$!TxnxtKM{6HLiYi@M2rRZ<|-J8N|!po%c0}bLJ+_bo}RCx=(Rw
z(_37Us-Va~Ien5TBY;v?-xUHDs_NeD1_$Mhn9k-k11vzjIbY$}k<`?>&y?aVTUqly
z(~I-ehCdvgGDFzTL(_9l4s}|D1_*gcVn@HaNO}ESMSy00F$tOW;I9?ou3_&!|8}L-
z`c$rg+QRN!D^TY;s1~x{H_67!D>{^xf%?!nbj<3K?}wk?rw@6{c9p7f<Kn~=461qW
zsh9p5W+S1ncIVABY3#>`o{N`Wd_y5mQ8ewsJaW;gb*}ZB_pnJ#T<`_tENDD$sznT}
z{*h<aVi7SZD)Vy->;mTnEHtY>ZS&(%zm^l%^8BY)f`cH@PK5tX9Ux(07jTo6uhG$O
zaTD9RE(|St0o&k5w#{EEeLEUYqIuiG%EyzwcwZ=11_F=4ie4vOr|H*_Y|RZcv_Qa}
zVuSVMAM=a<zc>MyGLUnwAVG7h<0S2rxL?kAWMGju(=0J(i`H?Nv8^XnYatK-8JBYJ
z$hntgLNh|!tE{<=rc>wkttC&v@|KP*B?XIjd<(=?mVMOUgGY9vom7T6t5^qF-Yg$`
zBfZ=3_~@%D8CVA)Zw-E!7(4bcvczB~+yS;}ItHkmVbm!E_86wFNYcyslgzA*W_}GL
z)K*zWZ;Jxe2&>mHaKCB#*tBdV`1s+~_Gf^Wzf`iPk?U}asJGT}xjlL&EV5MNGh8UY
zhwl|fE1iLk^D25Xj$}PFd^jaE=QtKr#SI**E$USPOP)}4u*LZw&P)LGW0|-2k)3;f
z74-|5{@`&-aM`Ug!x7V!^1oE&ZKdmf-tFYsJtDe)OxqKdUl${*mMdI5MBQE-X9#xA
zyY)b_21G1VyuigBa<~x~K@iL)30gCp_EnYm;>5A*m^eL!*#TODbbNl*_co=2?R;bB
zIh`%iX9%7#Au?Qe76V4g+ryj`dJW{KKB6nfO#eRWv>tU4<%#hT=6vv?Fv2Rp_8%5d
z=L_hqD*|~KUTtF}Tb}K4$^nkvKZJXeYekP!n&r+~sIExc(pqh_oNx_ir?53Xg7b&V
z_7<I!j6cepew#5x1+3_0>|7zoQ6~Ty>8!rf!vaZl<?HN$WKmDs{|=u@4#&108|Gl<
z`e9@G^+EYXUk2TE2`teoHcUSnjUFRd*9&GP#ZmtOq}4oubeH;z)rAulVL>KtwI_$s
zjsvIZisn32SgEQGEpg9GH}h6TEEBAA5MFRpRM0K_Vt#lCAC1?GZ!>wSlbm%G?foum
z)pyd~D|>bucb_$W{>+vFrLW@nLJ|Y*I&<E|g@Ws4dO8gF3&=DXX1~V7=M$STV`kz?
zM{AZ32>A(#PUw+w`zjrTq)uSvYghfNqX=bUQ%ky{LT!Z@4ql*h1)Ei~F_hQKb&6eN
z(PA~`|Fl5tPP1mSAg|}t6tMwk1ep7oF^?NFBnEony&3hQHQrQgrozrC$tEA%aPsBn
zb{X@a4hAi?4La$5_g9kbBV#Uey>N<z^6-PoE8yO6=6HH1?4Gr&wQjwftoekNL&xcx
zPDl`K;kt=c)oWyfuHwr>IHv{Jxj=5>kWq1iJJt`}E@#t;Byi8y5!mg^(L`L*<rRF2
zJDdCh$rj4r`kt0+UHz=%(~{U^Dx~RzEJ7jcF<@VnUJ!=N`bT>2+ehS!eaT(OtVN#{
zP297{T|*A5WRSIkeHGWp_c(r{Lu%r28uD&i$vOKcG8)0bix7hV9fEEaN4j8bJr#E)
zDoD8Uay++XNl_vD0zmPM%JUwMyV{LH^ZD|>Zb3kb1OJ)*hXHfy{|oH4Aq4b$+^MZS
zSk|pZJA#cj-vj(OTe1{G)0i|IQWV_!?23!Q4`4*J+#(k-7l$d&3Sit#N@Q*F!guVI
z`X3Ibj5F!xf8>|dOoBftXNhhGn?anm(xHV@&s+^6bFL8RFFBBm<iCICT|TEYDa>Dc
z5W@~h2JQ8GypGDsmiQ_%&8^`6<5f{3ujo?UjML`8`>)46OTnb`Cu<tg9CDjU-=ZZ0
zh&+myeFoeD?mz9OQngST%Rmo-#~7p5M5%msWr8_Ri!!QK*&a4LvD4yBrW~k=rG&1p
zrXd&7=0&V=yTd{a)mVF=SQiCXrEqMpTWA$?NWo3);YTw;+xhA4nBz=c`rlk69RYM2
z3>9G$*z+tDy8gPCu!Hv8X(N~w6VAUmiC6`HDrbWC=$sDg$QDkZf|%XeS(!;cGA}-F
z^NK6M&=i8tdCa%ahJdi7Kd?m>?R!$le%Sj1FY<Y^Z)J6?Tg5bKF6f}5K_n*Nmp|;{
z6?vk2_~e)9DZ*O%UxVFfU;YczP>w7J$KzGd1Y+Q?<qh>zN0VW)m~YPTSPTaA1qbrQ
z?4~{o=J8$sIOp8Ae?W~A<h>>NmPGhQa4@Gz=MiJm!>0W6#7WO~AHM;V$HJJ(8rcT!
zobuSOhRPmQN<MB+44cTD1@edv`5n33zO&zl;e72_&fZSBaH5^POGnSlZIt?KjrRL~
ztG9O@W#m44C>0_uOZe~?<I2^$E`L{ppiUn*sR9ptv=un5y`(skAxKhf^jRhn>R1E~
zQLJ38OAMyh>B5mw3Fb(iulbB6yUyf$z?x7I9{bE*GAw=&?@nS%boVz0FhzHEfhr|%
zYkz0Job;GhYU4Ss{`<0(Vzk|mG&x^g*EMVf{LKP5@VF99d(1C;257x=PYVGAaxXfI
z)?sO5L+8y#F0{I59jWW!0;4G2?9H-@d*Z922xTEgU#?mp+_o*5q=(-|#_#Zi5+gY8
z>WOYiIzWoh8Ml<Y$@BgZlL>-L_uRh7Y{)>5VR$)dOS+4Hm|*%QTgcCL2X?6?Es{Y1
z<IyGwH9yc%%>>YxOvMak8?!}gCPY<Y_QsCG2H%3Pb(CKOTD^0+=WA5O|L)tR0nrMH
J3lspViGqZX-RJ-S

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mac_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..1a75fae8ce26f915d316fefe7ef03da48e4f24b0
GIT binary patch
literal 92432
zcmV(bK>ojr6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC{1Do&#<#lN@{$*0P
zCKaH%42F)mmu2BnG97u5zV3824fOxW*=$U3jiAryg0@FA$z6CzmKhKp^p8g{rL^BP
z3}Y=1xN*n{CjK!%L*jK96fC90!K*=0^jdqu%oXy9TZe9V+AL7b-CU>uH}T9C#Pg1N
ze)e{!%M9p4%OB)2;|6OO+^`atTl##M2X6fr+w1K;3Ziyhc>&wGtU(=DK4!yA?hC&R
zH3B~>7DE?>DVj7*fOeOEwx>wtI&F?S+jwVed7Nf@Ad!RpeC5YNuQJ1iUVoY(;RmZJ
zq|`WyhTX#gtHY#}GUhjc#4Dua_1a1NuxD7%r#LqE|E@+swL{nw1GI4Y$WQ!7j?MOf
zu5{0-(*cqaouWF^AjGW|5z_n~-j-x^W>t-+KZZ8NPh!O!@4h?s9{MT?Ae7Zl84PS8
z$h@_i*t!^c5oUMGwPH#GbCP76U`)QWgpahH9QeFj;=?Qk@v|(nu2M#)kTpi-d<;TH
zMQdtGjEW7p@Hn~VeL-bR=dbCTCRTbADcc-TGSUOT-E^Hngyr|<Hf*J{X>t!IIi{oz
zH*+8!G~TFgNpTuCco0^*-f~fUh+D1QEW`1^_+<E$$NkXT-XAQNQdh=2>RqNL-js5o
zb)##vSPi^@;Hb-qsr$BLR`66)zUgu2m2)3FgY^cC6rGVVI#_!??`vuE(J?WdEYXZd
zuF{8NeSvkusnvBpqn8JTs+BHx-=CM*i@r0@x67w_A?XGY)V(v$9YkH1EfG^`h(TrT
z1fX%@w}0pC@ZNvd0Fq*HN>+M@(^P!WWB-t>ENecn&;_}BLn44dZOwHBP<E1+Z+*_U
zy8TCA&|01yD}=Fq7n-i%!G$|iT_T`G8caZ#g+WSu)0${-L9?dO5&b?`I`hkg=}w8H
znSb6ge_TYXtHobe*w;_HvO(lqP(fa&Ua`OCs)um2S9$uSFPU?)Md~o(8c)`5N;)g@
z!QOmse25T?UD<9gif?i-P*VRAg8ZI0SUGB^SfiMiFTeJ{-%i2d{rQ%jS?)7T!8jU#
z@$nK~9C(y1YfF8%-l&h;R8(3{=q&yH5Ox`{aoG&bIBmOOCo>2Y;s^EvQ(SB{CHa+n
za0J9LE*Oj=wWbmEMNSe2Iv@+3f9`qpwQ}=u4tvJdJ|4?1#+9@33y_>l41;}m1ZhkC
zka~4lf)`2E#PEpbX&*fVF@UMdBGg1Fz1|;TMwM67waj1nD)Z(xNM$=j-#;2xprptr
zWots62QPf-A=!w8T?m!u$;E}4&pePHO1#13e;8?)V5AK@bgwD;ZQIUoIl1?}ZZqyX
zMD;!hhbdaQa<MEsj9^xiO(>e-G5B>Ciy$uOOkZa&POKgvn>hEeM~CLovRTqSktpuX
z#Y4K+he+ewYm)g|)9J|D)|{d6*BX#bH*=&38z$V+LWM3G%mmC?<fJ8cdIp0-x8N-@
z7k2&(5n0aB>4j}QGv{n@TvM~^6<VDb%PLE%iVZ)qo3dK*JIm#DE<7LNJI~eq=WxK9
z7F9=4%1IIyTJ2>F{GPUkDX_ZpW<yLbqmsXA@QIu*w_i}51jJ$G$YJQ%#xT=rkF$Wz
zY{#d!=QA=+OKq_Mk4%d7ScBPd<2S1WO$v)N3$>}3MqoWEg79Dv>L(03dSvL3Q6nNc
zh!0^u#IC?>KQyA&EeMi7d^9aau}4$eE%@wlMmL%K(@Z0xkJcUwEy99hxtn5EJ`f|3
z>Mj>7HhBPHI=oW=->@t2;g=8!k3bpbu;NW3LQ+2WRDM$*L6+G~7(uD_#S?K@Yl#vD
zefE}bnQ<%{TbDahq;0pcT{I|%9-`3Ce-m?RLS=JkWV7mCEqgCXqF@3J+9#HErU@hj
z-)Y`}tYmO2(#t8-DX)6(N@z>)g!J{;ARbseUQg7RMJe&~t7My9ZfHjzGw!W4`3778
zsS?qAKsgcl4$u`|PW5Bg$b+tQ<1V2sw{jml5NcMFmxE^{G2$FxB;ZlC$D;oNu@um4
zrF=;VT<h5tub?8uyHZJXiq-q~2;Aj$Tqsq)<o1V_@`YNur_YQsFVH!Xv{j0<^jA4z
zqP7!kK;;4*`$+lLAyHI+36c&)uP>$8-sQLV{Qa@o&I6-+F9s&6_DF(c!1%yom?%qB
zVNf!CvwiH*qaehf{X|Ybhi`U&M=d@^dN9Q3U~X?SS~ED`*D}c?n!TO~C?y{g`o9L+
zKb}%UiA?Nl7t<Hv`wNBF+*ddk<UCL)9qwjAo@KxEtyJl&HNwA>JST)AsQ+=GH&bb2
z>l?=@9CgoIN|5c@#YtA;o#kmE!%IEv5yC+Zy&<@Q<KZ+2NfiEOQNS54ivc{_Ox*SF
zbd9TttD>T4BS95jd|QFvlydxpVn)MGzC0Y1tEWR@RFMH^m;VnA@O+!QV@Dr+9|PwA
zwa?eSmurIW9sA}Yo3a2M=j(_n7#OrA6cd>$wM;e4Y0uKsiwTvV6DwFxGL6J4=s5H-
z<vdAPC=fKOKX0sxl-B=6&VyfqT#4z@`1A$Vq6-}GC5OibF+$2r(C)pb-s0M}5#Md@
za3MgxecS|zO#=5&=4MNd8~20$uLI|BMpT~m1UmE*B^om_=Z3TPJYnKANI51@KHKjH
zdR$tpN{4$Jp%fLDFAtq`fJgAbc&%KvOYWw_1M0%Y!9CUo^j=81&&MdQGDRLCK%avx
zA-dT4Uhnfda#kvl?!K1uB(|It09#wsnUy7^E;p=aGfG2NTg!|tY1z(W$mpU2$=?1Z
z0f~Lh(yS-1@aT3_hkFphNk(LZSuukq_8|m%i{fc2IE4|vG%AQPUuN^kA16t8+@31^
zPj35hZ<Xog?&0>_mEt)Cv^bo4h~zH+2C9uJWj7BZnY2Fbrxn7$mTrRLM%8W_6#~)X
zj3Zz*jEGKF1t-y$7D%D~`Xm(VeR{d}n~;wy#yt^piW)HQ6pfXzG)$lS1k~X{>j^M`
zg)Q=Wd*kCahxK~W@wH*YIF=-J9@(M4>wCViE80<L<s&)jR_X8tAAZUNaSJJJpq3Y`
zVFweZmYF177JCsrk!zP9jDw|=G<B-PG$vx^W)2u;2VjQ|8{?e5c*Qf5GkSd~&}%^g
za22-eFgeT5t!c}1nj-=N+cF%0s{qOTD+`lDKB#{&pY?9obu>72UoaL*2{~5I%OcL=
zrZ+PmrR8f73z1012#*J8tl>Lqsl8^UK_P3J40OpYu=`EPw6PpC<_g;}NQ6qQqI#^Y
zq@5H}+XV-RF^5dx6)90PC@yK3`zg9p+u?1jQC?lxp6Mi0OZJ@Y`&Yb8DTOD1&pVv7
zC5pBuD4Je%c9t@Ms*_QgF~zWW{E@UVIgLJS#3y%qH)bCRLulB>Am|Z_yL_ZUhz|^X
zs*$o}t&s-Xr8piB$6PvZvLp<-MN>hxpRnm;#6DWFCCRM97;t;LEIl+XY-PD443>fF
zTKJ%-Z!n(84FW=2N56n6rhOn?a>Ou&P_<$QV+91?^HVl3E8w@N)cdi;kRxZa&pL!%
zb}7e$-Q!czh5$gglKWsFuNwwHCWWX<w~*R*8_>h^ml(L|HQUcGWJJj_dzOis;v5P{
z2TCdytF}hGQaLaBlC^?o@@p*5)v}OrVTr&rI2ZEy?VH3ZrqYQW&Yu7n)kyPU#;Ihc
zVlB~dbF7FI4;?L9CenJfXwlL^vR$|JR)_SSyJ7>6YN==MeZc}#**fXts8IJqJc+la
znIsCJA6%2Wq}@mo*)=f3iK_4T!y(cRg~sc-W)}!{c6mD?xOF+IZ09u78VrmkNv&_I
zl?MTNeokOXYkrT<Y$>~W6ja1ebuzgy)1;T&A(c52t$qHNDUy#4h$F7z!)k<V*5TT5
zW1bANUl9}#dB3N5ij7$BJ8z@7L0Ophq<ugPt3iR%6h_Ugk|Cs*j4y69M~9<hfbQ8V
z{QS+syp6nQhxOQ+8S5K?2~!0<LiWwxg2hmE=qDEzy>|SwmADsldU8glQYew<5t#MX
zz?ro@2|A#8b;FMNF;dFdm=a8}Gwi9Lyv#)NFLn_pN8T}n<?5|hU$B|O5A&w6Hb+w|
zYeUbvIkrOUyWChwZSTWxkr{&%T^)GQOCk8QO*GSFvV*~uT${K}+vyl9_RH*ag$M_j
z&VqdJK)gf~m~Ra)YgA0Aun_DSs7M?fv}k6ZF5x-f7%5t`ZQ`VJXvlpXumc$WzE5qU
z3<wf@CzU#e&6jVfoL$*NqKtU>Umcw8?b%pJq!$M@|NQD8IZZ<8E*oRc?1L4_jkl>^
zL{-OP;4qgpu2Noj0A8HW`(x-BUe7tOzsI)T<MO3lYWKGM>d&gy;%+#g=BHUPM~vY^
z-%Bc{(-zj%&_%!lQv({>qOYd=lE0Wtt+8O*lMLA7xT|wT@vlXCqSzX|mT1EJt&6IR
z<3Jd?<eB_Lu+|^cye0c>K$toa6EQX2hv!C0fWz)WTPGX{+XZ;zuK8N30dXss!-bV+
ztqX48;}z;LYz^_+i{*WFC1fUFb*sN>8_3L1VMp&rxLS_n$m(8it;6g_^jgNRhC1Hy
z{B5{6qY$4J?W!&S%Mg^i;GPY`>JWpj1<6|e5|ZZ$N>0q?qpC==!%Tsx)*|&GbLr2c
z>(|5zkcB<*_@a3P{wz6}&Q`PSrnf7ScpLn36b0)RE{c9PhW%EYI7h1?bv8LY+}hry
z<)DCbsgV#DTiC#GGomqr)P7InT`mo#vO|D3Wm#5Qn!Liv=U(_JGJYJi&5a&-i1SfI
z{~z%=zw#GIl~d33N$CExzTQPuB9h;W5A4FEqsS6D`t9`ze@lc*uR4oc!XqeQG}_La
zMVM$PCnWpET=_OkEu8uR{dz(hbB?Z#l*NaYS25GFsq7Bjt#fagD5`>gVxrKX=SWH*
z7{+i2Y`UP#*|?B$%W`#CJwBsOm{PgslV8G>o--UP;uidvlL3a(#M`N0lO1+ejOG^>
zi(KcPUqicWcFhjXWcr|FFazJ}P1u3}nA)HXdO@{~%1P$fNUfq=+L2GG4m0{ayWHZ0
zLE+wEm0<h*D202!FZ$9rTZH$4EQLPsA@iU_GRuV7aMNrlJtOx<*vRudz)uwv)LSDd
zwG~{6R_zzlzS#A75`!;)(`C{ukI9BR1l}Fy1LjqvS8e7&UT}>|fIa`p7N!;>Q3OCU
z+|~GBcM9w9cqt@xwlVq7nf)Njca;4bUIy6zEb%)~YJ|r@Z%Uj#`=c^^fYZK*lo#!9
zmTHJTDTgX)wz9=y@0X&e)sf~MxIcQ6((!QAzCS1E`H^T3=_}*hS&5}Sx*VKZaI8mQ
z2IwMD>%9Uc8@=5o4G}UKvT@7D>ZLi!*|%4Zy|i4>vvqx5TGMGR<=uuaDptIc^`l{_
zs%H358A(OzTmLXj_m&R`tj9ag(}uRPdLTA8vvHAas(7j+eUIXtCTHY8c+@lRCvmlF
z@$Sq&_ULr_cTn!DE7Nj)lA^{8m@S?iSf-?p1?cQ5jFGI8(327SW;$a7<MsgNpL9{4
ztkLNaDG#?bE82rQYLMQNnR+eZ8P*4kdF@yq9oS#VQek(}y6Y?5w@cN%gLW+Me1gvz
zh9i_2!YA=%2uZr_Xeefdz3*{cK%2ZX>Am3@^Lx~E{*rZ*|3G1=PA+<dKz95Np9|yl
zfcGg38ihjyA(nX-1d20!bHaurk`;w6D_>{uRx%d}NLg3BQmrGi*eEaiLPR4%tbQkg
z#(|YC!bC9nSiBF=!vEuigJ{bCh-=v9r@T;)NfKRa!_%b`^cYiXC~9RBhdPqjXdEUg
zqqgC-+uY-cHaMgf<gf?lp@Zw+kJ{+TZS(4IJ$&kl)tNehkKlnMDJ`DwIN)y3Y7Fo6
zTb;!O>$&l|hqthwY>u>&@|>C0LcqX`2C`y*-}zp1gZ=SXFN|--1m?!1<3xM`fc);i
zpyg0KoAB34t48`dX&~r`_*Q$<dUZu}G<o|DFY%h>48DpPWCw<_HoZ@2UjTU0>?)QG
z8&>|J334eu_ciiPGILj+PH3ROb{G`0eUasEba)pOzdnINz$%%0hRG`fp#gNxZlmXL
z5SXm29q{dZXAe_&>-=JwQ&tvuS`>wg)+oP{>(orE!l76*@9MnuB)-*z-X^^gkuDFj
z?O4~G0gBDB9WEGSmkvGRw7cSNy|rP|@7Y^HOx7|gt=-`L5Zd8Iv)zA7h6&YTmk$pZ
zEUWu=+|2}Sc6O2q^ujvI8W-)?Y+;i62jc>w8HQA^pcbhXP#LHS4o{LcBJ=@FEiH(C
zkg@a#DQCd~e1ml#XfcHB4UlO*Abtk=Sc}jgoE1=HyQ^_z-vV&n=b`OUEoWFVNnFMv
zxyLkKB*VgQ0X8N~p5~x7=&kSU)0PQ%K3Ri-P%BN{ZeOS5d4C+W3-O3nc~~kxO@Bn9
z@U`R1s?<3|?155!N-<OH?t6n^ilh5hGb9=4qeSq8#Wz+5c6`MBwnpUC-;-N(Da2St
zn>|I|13~yoR`x**aifhLHi0ZIfum+ZHnbfFiu1~NmkO}4Ht6$YO+CO>A?a}lFCYZy
zK12R1#bg*&!%d&f#8Je$B^}lbs+ag4IlO{$zGH*bNPRMHdKf`eRWO>bY8IibacTL7
z)1w=cXL7`Uw#mFzio)(GfYfC(rg3EmHDbU%(v|kTGjg9h{2d}s4GgXPUbM(svsu%B
zHgH6kv>R7TP3rnsGSX4NgSR0zjqSg9f}_SmBfjRqxFA5i?%~FEp&sHsEIkWfja{-v
z>>`8B`kczpZWG@gyVO{gI~xulEy(uUtG4#lM;Hc6^94Q=-N|mEKJEZ8Lw*$gS8_fy
zwjafRq~ikG2Ow^z4?Kic&63m9vtF5%>LLr5S{d0L8Tq*(LN_j~L}F~X;&Z|E(@~ZZ
zT1HS8^=U3_-p~Q^8y{hAJ=~d44g6e=8Ez%aeLm$RW9yjFQPZS_^OTNt3yS=|3x8tm
zmIV~&$$xVnr+#=W3h(=py8t(e$jdg#KIR(3v~GqQvoGZ|S!11Ca$XlElWYX!b%TAS
zYcRHh!tA`3sS_Z@8XN1$@O!{qv8k$g?jTPABe0i?c^Z}zO7-repv1=HzxS>WmdYI_
z*SFT{7tRV~RUn+!_NN7*({a~zfSDn<<OwcUebjbE+`cM+_BiuIKTb!s)<Ty1sjE%D
z)S(zJ|B7K(EBE`!7lzYd=2y5#DyXrjwfZNse9#k$_s0@cb`+!FiaO;q&_=o>qh)td
zOz$J3S&ACj!#-w1fBFdcWIaE7I|RUD->t9IdD^Ym(IV{^SBhq_@Ec%78x$3J)3+WY
z=1^2on7|mSsW_wq{Rs%*p33D^G<;mBr860V(N>M30T-;~g20Z{h}kADh~&*Y2({O4
zrx9nen^v|sEa9R0Vv+o7-)K{Q2<4K&Y9BvwfHaNnDn87Fgz;0)Q#@T#7CZFFQzVxH
zv48ZS`%^`1k9^CU!?}YU1QRum>c=-GSydQ@D3tQ;Oe%n99z4Zf(OXO!IgSTN5V~FG
zO1&RN;|bZho9aaP8upL?aOz1d;%k&b7T8y*%7FR}02*+{N$bLrfjFpQjp^(55d#w<
zJ*vUB^k~&g>hUzoQ&cPe;$(PTB}eaP78kf{%jr*_l7iGGEL7)n;9LZ%ZUjB}oE5&t
zFsvkY-Ldo96cg^Hu<+2|I!TwofHVY>ag~sNfyN+pDRa6QUV<MAjNItvkmVZn4fPu)
zwBfCG<&VuIFVp5>DTr^=UzLzk>SkuH??y$TxZi`YzQVgR#CT~+-yJKR-Aw3S3&F2g
z!xuZ5I9wD3QZCw2p2v9b(+bjaS8!}X#-bnV55$3-*Q+<6YM-6VPUYvi+9ulW4OEsP
zbAn%N{pc5RJJB}Rt?8roosf8BdW36%C1YL_Y`+R5W<q|9KNNJnT?v}iD3gJ!rGu#3
z5|}=}Rnq?eggiDkuJquFHz(1s76Bjpzj&AuWFG$6-RqtI4#4c@@iUskiDk9-vRg7d
zs>esW?%GEPrtkGy&vw)^iR02B=Kd;wvNxvwbq;DS+04&}a4*5<2U8IJra&LuG~VZj
zU*LU->k4z<ZHFq`Xi~&F9$qM9_VOA(;}T!Zv9}$a)!7)4SC(a8KGcB}cEZ!A=-M5Q
z^C0=O`}jo_zBanX!*_u{Zps2gk>P#I&3!F{wvnOFv^of}IuS|kIj=e4oK_K5NPQdl
zDr$dDKbxGkB;~4IObsbtbH(y*UHRe=zvWGKl-ADAS5NCWHX>pxp;sAQ%*&91ZH1Zv
zS(G`jkK#WaL;7qvq_AUCYL)j-gZaz>CWLGM1~(tmf-T!0^|F;FRaZhl0E{D32+pxb
zef!O@{8LGrIr-6*;n;-E1}w&2%WC4{2(fWP`Tl-bnJ8FczfBlO@vR}iqs(CCCI^qs
zE4ujt!xKj@04U8~<7KWrQazREZwI7{7f<kYtzt8yI^FS+XaDlqGd5-Idz(TC%VJMP
z0h3(tuFCjy@4O`k2j}1Ek@olpG=$F$oqT4jE_`x<ZA(316%QnTU^=4Uo=9I~t8t0h
z+sHHyorT~o6Yv$&jAvL6)06O7L|%klT(_}&2RdO^2usNlNzT8Z3>LElT41{w5Wz1l
z40c`^hQCUHw-w=U7CQr|Ws!u@6|8d(_zQ?FJu@7!6+4@?QKPNNm_hBerCO?@Y|2oj
zJ*)`y8s_^N$K3)=@3G81CR(^u%|8vNmu!hT=*NDmjL$F4z<=`np)~`bT3ML1je0Kq
z4MzaQS#B)#3uc`u<hCb}Ad&s*<$lUP^^^e^!%TRy@}Q{x-&R?+s)`t}j}-$2cZiUp
z@<{7-?;-7!eCNoRMydyRzsI@=65HV>!Cl_<QL9mbAZfZ=W1df{*C@9ku)yPt3Tg3y
ziogsTJzo-ZD!N!!Hv3~m%W}1m8I<#XpBV9_vdwdDr4(M75Z&|QLmPhZ$UhilnRasB
zhdg2pQ}krTR{6a)a#CrJ{9^gFwpt9Ba+}nF|3>fvRz`Y_Z8M*SV=o8$<ek_Mo!Xn;
zkEsSr^?K~UnLf{aPy735p4&+OJ#(a;7`>O0JEmV6u%YAsY<PtMAF|E-cvY?`;vcF-
z#Yi&1$Dld#bOpYdyk97rvqv011l*Rs(RKfdPhsQ3rH(Y|_&CWydfx&I0SDcbZ?gO-
ziC<{W+1ksB!rs{>T1$EjjKhqe>1O%z^hCZ7#}(GxkQ#EZ^>kH%oNSCV9Z(U=!~VJ=
zmc^ipZfGj+#r~<5V)Kt*-q-mrPiZKCK$3OIY^#%X-;byy_zns@xulLZ{8SWGLK8^h
zS*{hsUGwh~QIkC4E@$qUs;ols-T*rvtP8g*n^VM)H;JK<(ZnXpryVsKqyyO2tKx`!
zeBr}wv+la~OyAi&Ui2)tp)j@jH^x-PSJQlfR(5VOc3de?yz=I37l%-<fTjWC6oEu6
z1Fzx3XS^vYl&lYXedtvOhdxaB&`V0CT-mdym5K7&CA+6WG)~v6DSgJV%_#1ss7&aC
zF%`_G0^eW(ALV^yx9aAKO)#}=M|oh>$zOw#yco*jy9)iiGtAU^ZQ&KcoUJ^K&77>+
zd60gJ-XxI&U&AT;@(Rb70NjPrW^!fi&l0dH6Y!ySgb^sF<cSPAXv`|anqV8MgBHDK
z+jq8db*KpbIug{R35kG}%7O*+S896PnE}E8;YLO3UW}04kq{`vd)BrN52;{e0DZo6
zcL|$8X3>>_z1B18_Whdd!E?Blmp~WN<1Zy$s?5GhB5AcXmln8o$sO!um$VB=i^o?$
zYBmK{%x%Us8K6zn>M3v(9I?!ny#lvxBfF>W<eKr)X2HU&-inuS%{?OC^zw=wtig@y
zql{akP3|<cBFz5M0b3B}!1D$lIM`aYzv-Ftu0n!t33r@jnu|%7TdhS+n!^<}qQI1W
z=0m_><zN-6Qe4RCfl_;tP>RpG0tE$;DS$H-Aw-TzvI!@d$eK0EjqaRgKc-!*kCvBm
z9G^|Kc&(90-vW-)8b2=;*ZvOvQ0mvmw7F!E22`_dk0K2>kq*1#WKh(N`}mP8uD*3(
zuoATQI#K{3b0O&VQ1%BWr^k4NOVU&prbA5TOE?_9K?-?0`ZyE-VVWYThlp}l5{tf}
zfO$5D(aRZh+-=F9=&<fmBWALv4<7)VW;en~>uhp%w3H2N-d}~Eplocy5OMWfoLCzP
zhO_(a*~F&Vqrr3RW=0KQt<0v{i*ubjy7v8q9rr%Ns3Z|#UvMgj1c8yxFTtM&m5Fdp
zv&;1s)(-f##zbs5)X~{!1Yb_1W57QOBd@rQ6e!<|su-SLS0fD|53GUFh+(M-<e<<W
z#l{Vlznl_VI6#g&8()2)GBD=q1C@5N@){YZJSQ5T>Dx!*7b!U2TsZjvNB7=EPE*2c
z=2(qY&NssHP6r~<*qA$_S?F{66CC$WG8ChSC}<64!XJU2uuusy&%DW#H*;e$%xSMd
zYzC|XbfvUfSZcl{`1oj7DsL<LfNy!BeD1Vzk$<Cw?_xvpJ9ObpKCdaCtxbO*jn0q`
zA~mYem(I&fq*ac9rR{p-fgJ3p!`<J#iKi)GU4ET`=}e0K$;eY;F-8g*tnGFr6Xbqc
z{f5lm{(a`==0#4#?3IVI$<KNq*{2jJ&@09e$jCe3E;)3L4G9DuARS9vKtT=2K=`&J
zNd>{Th^d>nfFes2Qc-5JX-AVRrgL?GlG<oFh3NYQb4y|RkmU&Y&pD53>;}u-JmgQy
z;hzdAh_R7MRmUii)4%0C+T}BBH1UCPL_tO5fcBC9b)+$|5O4LxL;vo?Irb(~2Wsve
zi4Q$;XSl9W`7g&%+e$F&Jl{S`e=1gDt`}eM0T6WS@ghSFTBff2nyW^qM_b#eo;Fu`
zYd^-ZDjjv=s}Dd~9^-o&fAqd%7yh<6X=r1?*KOm!w)d(%n*_2G2puN&q!`4~7Z=4h
zByHdXbX&6w60bB-cTGS2<LLFvpA>dKkm8-N6kx4^*~9nKe_<RfbHWLu21;6Z`|d|K
zrO%5=_<Ezi=)blS8Th@ic1|j<%0onc>xxQASA3VVuDEg|?6BzQ*?bXPY@7t8LYe=3
zZC4+t9jmDmn3;bsJ*U$}Q<`xNq8lP!CajYH3jN>rM}P$6OlKQ!X7%6z@O4Kiw&PA#
zLXM*Hp0t!4<?!UVuU6Kip=BrAZbdnQuE+SOB`4;{4Q1BkNet(mGK^T)hrHd)v964C
zmM)7BrU|x`%bJ@5c8}BLsA^yD$h)*JNwl;3tAe=~50U`#;r;Wdmd&!j(!UOh+bOl0
zuOlBjr@Rm7^y?-94!NU{-BMkMK+il_!_eCLShvKqR>V*YV6vs!(|0vvd>bkiRZ!k8
z#`kWBZse2$KE~45ut`TFxd%_x3nv-o)w31x)F5>2h)JvVcbxQ7JbvVH5LY1!pfC1k
zI8|{}r%&Fgp&=yAcMNRPtP`RPyjDO_iDlVzob$#}^TvieVK)q5hXXeCMSB|d^r7HT
z;(E4AP#<ih$j`)xwFX>KcjH4P{!jF&?YWKo=v_i7bA)lPbT(eT!Q!{`&@VV9o4Q3`
z8g_z4YRLbUF0T1D{VZ5#o&#n#1kJA(@8HvqusK@Uc^K^s4qA|-L&T5UL(K&^CwyB&
z;19g)!w<=Fbd-R>@fa*JPJ)bYUQsyO^G|3s%L1`aMPm6xd+itw>0mK)Bzu`6G%UUc
zYA}08E81`0EitD1`EVrnMD@deGo;L?&#X5HxTq$>8-Ydj=GgA{ExJTRWpyn&#cYwj
z^w3k#hk8hqafAopeV4SS@QZBcs5~pp=%0wCr1k}cbBF9frc;)|Fa$s2xu3`bktN1M
z<Gt7@m%5QCE_TxE+kb{?IyVNKP$goZT<CCO3lK-&)FQ!1$xe2ptNmjIRE%}uVV*|o
z`pA7{-pnmr)~C9P7HzCVfoI6HExot|C%UcS!QpSYFu8a^t!^u`#Gy`dRYlay8zkX0
z(`XLMA=tn`2P-{1|BG!hyM{CCRfgC}-edy4`T4ThUR>i+s!;h=Lm>cDcpEg{){8cx
z&OmIfRT}j*59RO<3VE;8-z!;Xy+zk5#Pw|(HC7hdUd$+rYj|ve6v+<Z9==lO3rgP>
za|j7on0u8S2iZL!>sbw%H^R%V^FpEy_+(MW?ueq%RI*|A0T>7fV+vsF48-nmujjV<
z${XLCwg8;cXQ80E|F=gm%iLWGB@BbaeBj2}d`dYq?MqY1Mr%i!R+QxjQlsMyyvCW@
z7Y7igR7!DAs@!bh_9mwTRX>O>Dl7EYmL_j)BvIhekZJ0{Cl#sww)32AxiGleDXsiu
zObiBnvVjQ&CSNP19sx!JWgAqt!rAHmn^i7c;T~oUc6zIDZNd%+4mHSV{Q7=vbk<#Q
z5olu(By$=BRyux=_tCl&Chf8sOEbI11>8kIV#cZd$>8xA`J6ZU<7Q4O${OCipPU5z
zqyVdP;}#ky`BC03j$HYNbe=vjTPmbR6cul@rAvuC0z1=8nT<;-d@Q@AFBy2x*o;~o
zXcd?(amvgr$$wBgFt_=h72~wwaQIbPuJ{*U#O7;bRhn1eDnm*q%Fdq*`1egd$2=xb
zrF`oHwq~)!>@PB(2C0AK!7@dOi}c3B=z8RShyUOBZ@!zeB#$>B(4&{&#Z0Fh1dDLm
zM=9JdkFN=4e3c}%>ar(LxAwOtDl#diN*|vPN>Cvn`=TtW5X9lB29wi+rKz<;_{wrV
z2E|sN5Z~?<7~;a0k?u$XYiLA-$RSHZ%}+_kzsjRyHK9efkb;Ru!CCWGGz~GES#^ga
z6F#!-%~ifqq*lvVIZ7BW_uP|Fy>&zc`Li4Ge#G0T<O@9&@4UB%<g7$On7q^c94T0!
zxc^J8fb0P!*ebRsWaLTbHGq^YQ{o`4H0@nIz#qIBu})%qH9^E|F>vmV2X`F|0mgyL
zZpr6T#4+ihf9f9f5V`~Yq$>G%C)TYAxc{?2J(OgVoHgT5drZ+D*%aB)c@6OR3`9C)
z?IhW#lIw**4om?f^SVQ3bN+r~cBYd;fH4u-svkf~8e@$gWTn$MRc@wFv&%qmP;mvM
z#^J8SRIVEP&yAo@^KyDL?b<>KVo6&0{(K7tY_Z-XKtcWwgH8a3rtF8=&^^l!bcc|7
zm4&h+LerbOA9efF`=J5SkAH(JI5;mQXn(>stqE%i*R7nU5b3&9_FEh@&%=}8Pj=bX
zz^Qnknqt7AIu4tfPG4-B+~jz#{g8GP(PdZyK>SPGV0~z0K)Lewu*H-Ol~Ug-PNzG`
znruCT`|8fwv@@=}@z$u%Vt0dfV&6>*6-y<4IM~aW5o|0e!hgdBf6?yhiMQ9DSN9v3
zq)@tWLf`I%a^R2WRE+}cmI7FRN7Ia*+pSkDU7&Anq$-ALYiLDk-xvoV^}XG1?JA|3
zAo<!3tb*&$%@Tz#qde%K|5+WrV2+no=ja36w(k0DP!+xCSX4LV?`j)XmW*bd?Xn70
zyCcEHr1<cK@qcATR+SV}j(e#8AFrLtfs_*bU7SE!B_b$*1zfFi4HY=wAk5JG$al@+
zTIax|N>69NMjN_d?xMTI#a4FYH`HVptGyh#BseN#Am6}C9!>JtzkTaPlJw~pcwacg
zl;%~%rfPL2Z5TbD6!oDuZ*k%r`bH1_CFew82S+y`WE2(VGrWdLY;L!5ZdmeneXSiQ
z$eT%JV5f7#eIzaV80@xNclgNDiW;)sX6j+!pVo62BH#H<HIsTN1<nm~!xTG&!%T6&
z#4!oxB(5)W<+GbXJl%WLLM~8NvRMdumO$oCjhxz%g6>cHK5C8!RxGd+Ky`UKGoIEp
zE*Wn2@}cV*b@)-%JDVl^Z!<TF#2D@*4EJb>t)#<VlQ-$X^u6Hs3%D*VSSTJy7}BZ6
z08uJS<HE-hh+-$>m52HKo{|j`@0E)23Clj(su0zn($H|kHj~rtS&MKR2wgMp($;^{
z=8d36U<<GF8x%Sq=D%AF2R_a0n>>~{UnPgg<Ch`8@F-@$&qqaxlZbiB=B=l&NAQq=
z3O9lI40)B>tmy!?qc5x=;;NMeUkU_#3AnrB46RsjDTW7=6j@uJc=y_YHG(0+v?ulg
zti&9da%ht~xbJJvJw(ZA+V@O5c#YKTpypZd=Fqv{=D^aJAuSma#fCW9J*H14^>~rS
ze7?x3*E+aOq3t3k*yCiqBZln}$^dE-{HfOJ-JPD60ENZeUCzDtD%J=>#FzLG2|5=<
zQmw;|44|zJshosx5oXmfSIwbqMc1jD@UrE}*0y{yNU%X|dhggx#{a=#R>F(iN*9^*
zrL~LCH>Ww{h9b}5AEY|H%Eu#+VJ-b8Q5~~}%$ADl<-LS)=3zO)aAD0Y?<=xCEql%I
z<v&^@FX?I$+GyIL`i?B7qF9*+f;q?`x~~Iiy<spFDFD&4e=N?;5ETo~!#t2)l=Pp_
zK3kYX@I}hGQ{UL?h>iV%LE!JpjxMt^;#z_^be4p1Ey!0G17`oa;d<(VfcSkl$q=6#
z6IXjITdd!GG1<&TX7A!(^%4dI$RZ9K!G4x&n(=_tE{|e;P)yNT-Gm~uz%s(ZT=Xb*
z?ZWPWoMTetmfGpkKkLH73s$*2L#dL));0{D)f6SFDaLwO+16rH!MrI~|GnAP(6H)$
z=yGn;2|)cLRIX6{C!Tm9L2!d0j}wA>7Ag|nlB|^%`g3*IDcu+%9OO6g658f1h!_8*
zOt#?bLYPvT`rObV8kJbNlIxSnkHM(~tU{7<61r4HDVz>PD5v_0(*pot$j^{7T7Maa
zYHms~k4IZwGjr-&x86n|yJ^3gUz#VgHbET@G%j0^<Bf~WUF_;=wiQ8uu1-h$%y56;
za>u#9+sNo6*jy-9z6@Vpr!ri<_PBmL*!*D2^~qpiKlFX+)uVu!?6sy>f25xyZTZtn
zuBPnT3j1|5X!<;hhx)}idp{}S->VY!1zPMc;g{yY75`Y1bHf`vZR-<2Fn5bU?=F!H
z0LSLiFANp&Cb|MR_WA_i8Ie@jxUi-+lWf64Qi{QraiLd)$C@hdun1PcZRMEeL~GBn
z@ZID!kChqUHeML?(G5S`m$8WKX_1uN0Lf=hYZ@njZD(XF-Kk(gG0SFuF*P|#!a-R6
z$NEOQK<*4)`{gR&OfvqYg{%=D8kK_YnAJV&goR^TtUK!KHk{F3xXWG0_Yi$-MrKG`
z&%$pyv;bPrtC~c=V*=VaZG$QsQhY#3mh>OmAc^w@q>^a^wkW4)&NFG$Eia|98Inbk
zyW$^kgA<a~t3p3`ru?$@R|rrD3h0>R9JCxpE7vS2V7S3#;WNtXjkwahXT;?eq=1*6
zN;MDwVX^UKbU_d-1_SZDWw}}Ep{C#MuRESIT0QI7^Wy(-#R-w^tq0%U(sY9lLYm+N
zDgR8g_1^vp$dk2S!dq@w2DaKZo(~jdi?u5N891mm_`O!9xy(xMWqzbfC^Ro<ENjLt
z_AD>GSI)hisyYaM|EKwTA(ML$KxE)RNJ+vi%qh5?z0e3Br4uVeFzVbB6Qt<8c)eF{
zNk-j~uCY9u{c*A&pBs$P^LS?E>LPbleDDV#83mKFqYDEqY9EYO2rf1JB{%6$@jO+9
zvYeXTH}ybY!))i?ULN({%N2lwMX8GXk~v=RujYde0Ut#jT2-4$&a&dYc{zaKRy#Jj
zg#Y})BC8^pb?tdxA1P^-i``pM2D8(Z#rnqy*`r{K@IV|~8D1fdfR#S5Jplg~fg4k0
zY_LeOy%+2a`zQh%2C<j|MlmqfSC=EO4GtHXz7YAiJ=k$q?5TTK5?q47-n$=pl1$W8
zdPbriQA`KaPc8o^?PcP|Y!Ot7@c3yLLp<6&FH5nTNm8bzVxwi&XpK~}Hn7Zg)_TbO
zLb{bMO}Cf!10Jl|O)C^?aC|ZzU}ks5OQ8<%uxh9_u_TQKt)$~qgQPBvqhsnNFgq%*
zIN=RwG<0~P&VTn9?7av0j1`v7%d<`!4i;Yywort?=BC&GlLNzd*50X`@bj<>2??n_
zTmVwft>Wj8PEW?veJdZwQ$QSQ*$n@EYYq`RR0h0_z5<aHU-E3ZMFup(ma9ZwSMOLP
z#3_REZjP-GN45-Bg}<YkSFJCrla!f7bg4U^bB;*lm2tVuqxQQ?Uac_{pE$Vbp650r
z5a;4C>NDeYGz#11AJTxS_+`@KCj19C-+x?Ti%c~idI(gh6K?Zxare4@Q(>$6gA3T~
z+a`@yfLbxs7wAg<a;uE_o){WOj8x^w4;na?MFJ&wr_JfkEyNq4^|@v2EVZ{h!m?i_
zXRf?oydXk=mzU8+r&-4_rY{NZAI@v;PYoKKY$wt3&i!<-|2LXF*smg0cK8fPH*q>&
z9%#`keHf072N}n0+ALMV<i&J#`aom3ig5dboL1pMN8T)YeSjqb^q6qmi_etS=!<wk
zztE<JKQ9yF#&dR`jcL@pEEZ$`>=<&G)>td^*ry355lUqX;$$5QB#CF3Qs1d3C+YHK
zew1Kf|7`Or!}1O@x?jXhpVY`x{-~NTwBl9dLY#vD`6!~N6QNi1^_=W>=p@mKa5D(p
z4G^4HgwP2cgf|L+_{CDFlJ|bO$f-pa9OA+|Dx7)fj%+c?TJOoR<2;aMN*u6*t58Z^
z@<$A0{BV^G;?i*0?9ysaT_aG><+yvEeCMjZl*sNyN*WlRn2Z4{duP7{xMj4T=7MkV
z*(e)p4H!@lN`o^rQxL9Qax)(W7l)6vS1nZ=Oo^z5&iqOH)pi-dkV~yY@?PUF>I3mj
zZAO|tDV-Wf4rlAhG~pm|*dWmKF6G01d(%Hon*W(Mro{<z79O24nHf}E*#D5OB@=}h
z=2;%kR32J`kVNM+S^g+VLBhO2Phb$ZsvQ<!oTAU$QTRA@;id%*r`lAf{DRR({L<z1
zsprMeZ&iKRWIyQ+$`)((v@03t+}D~qXrwJ2E&HzR;Dc3J$3Fv`^mi&b7~%!n+?7>x
zr{9O9O4T-JCJj(316Q2<tM)k;+m@1>_>v&I#mP2YemQ&QN9twmr_o!=-r9i%#3CeT
z=yZ!H>r_yTya{AC*TYux@Iw>d`YpR10pNzLy5M=pj!()-{wF^LFtXPaB3Yf3%-gxr
zl}()n5s@5n9pG;d`_}W1&DSmdNai$Eg_{SU8~-Hj{nRu>axg+U>!dm(EsHnzrZX3z
zm_DcrIGaj4i4=+`pNEafk|$6Dwb|a6It+y%c<3tZZ0G8C|4;?cVPSY2RK(*thn%AJ
zp~sN!>beWSl?H%n%}9&5bFu(NVo@N!nWwU&4gn#$<d*SOc)LAAU|ykPeK-_lg8d~H
zm8VA`!Qnl?<H*+&+HMrROm8NO>-Gg~BvHmryZLtLydbPSli6XM)gmw=Q|L;5&55h8
zV?TABp}aU?S<6ZfTj)ypQriN1JBSqyZe@TA&@b>(OuJ^TAy{8q-O_0~{yZzrOdtEx
zON=cKqfikz%^n>QQj+sX*Gu|E*1Sj-3oW`*-<s54Kwmd+nf<Q&)v*eUaX@UL>d)>B
zptGTDYwNH3#z(`kCK*Pm>JFHm%=jJi>FoG(lM)bPEO{_P*5>T_6<0!9x?V!M4zszM
z1R|sTcnV2jYBX8Y;?xh><aUA0UI1gdV<Ah}8^xp;_qJGy5uH|FK+MmK#<B1-lHM6h
z-SH83Sfy)3j3aXM`g<ED37c2FFu`j+0rvPFzpBW0e4ZxLcw07GlT{L=0yQH2N|<cl
z2N-ut6zuK@&$h(6;YeQ~d&Ot8G^GCC(-Gbo(x^UyNq-aq*#vm=;|ISJc|4(^J1w|L
z&NuH&DDstpmO)`zn!HX|vfylnmO}HX7}+s|g7}jILz8XoCf2eo<@GO5C_)&8kT}8d
zCg_W8Lu_EV9{P1EJ{Fu>Frbwb4u%bvBJ4ACZx|G?ipy2EbKN_2lz4<*&tfH%B*(3R
zbWkVV_sZ}{_D1a|XGMpRG|4=8R(I$5PdSMKKw^GFYpNPgSLE3=(9p}-F)UbS)1<j^
zcuf>@PU3b{0?V$p!(ywg)pv526<If|aYD*V3vgq&*Z77RH?qiMMg9=K&D%R=h`C^P
zpT>^!c4*NhV)-aP?+d6Jp%bkT6HL9ocS8r)i3ps38iAmXPW95KM(yh>?<py2%zA)A
zH~H)dxLJH?U(R>x!Y_!#4I7;ZOCKf%!}*WOX|yF;rZ124x65TYZL}%$Z(T6kQQqJq
zxmRH71VAb=!bl(VUVX5>_@$U1J|jD;K%8z*x5qZy{<%<Z6>(bf<3Vj!^Zk`A+O<YG
zv^KO0iH}fLnSb?;p+RmTvEIfP*`Dh3tEVf&O`14}l*QyDu^hVLPwvMW#3~pa_-CS-
z(c;JpPio2{I-agVO~fOUU8xAg9VvHBHCfWn&wNx(i%Ik2_7gmTyy)fF9!~j-yNKQ>
zdyb?7>ALGdG8ZoASEk6%u+`5cXA-ZYj8g&>q;lilberhzQ6@S2g5eZmmU?J@CB_X?
z;j#XchB9Q4J2$w?5W@GY;EJ$*`pbFjVS5y?&&h8ut4C#W6{9UZt}>>Kcx|8Y2R!ra
zgT35V0}cJfs1a`gl#GgfirQ`&o=6rWT5uWG!|njPm|c7?pC6lWV^&jd?YE@7WChWm
znuRpFVWxI)>h^4&!*lX8Q(1}S?wp89Bz+g2*;Qcl)GzNDvaGTZU7Cl^I}*)%9#`*L
zmoE06J-yD;Dg(J)0GzsFa>`%DT5mNF&|fSG<e3vE(M*<2<vYy)i#5X5=BfEBQJxp|
z?{lB5wd9ljB|oW-i{xOs&Gp4qKV3XH(_)0*Qi>y)9L!SQaFug7GgLax`3v*iL5Gax
zd^Iu!9e|$n|At89Fv=?2gT(ikDRwZXCBtd9ka$|>nX=*tbBH}r`3YI4!h2M4auUFc
znjEt^?6lcl-BW#}=m^$+Ty5n?8T~$%e2?wFUrblnAVLdp=$6+Tf=`Cy@ehv(?FV+#
zVmgLQWbUyH9_;hHh?~I8hUVHekOcxEDtF`hu~=C$gZb<|HS;n8CG^b6YFqW_Kq(-5
zX*^jqcYoU5`CP>2m+d5Y0K844D(J2+7pO>yCRScLIB8WAsEp9v!Qv(X&<Q<|4wIB_
zNR0j@ZmE>zomJ=ut~nF?PG~xpjY<>#2+khbR}+ABwy8;*qQoiIhSJGa9abfWDaLtt
z(D~>oMF?;-gth?$PlSy;2YOBi79tUT6D`Ihs6<@Zy&AYlxEVH6F^VFfDQFM6Y%vkO
zET){uu}hjt!aD0HQOaVUg6aLCJ@TOx8=tFKqKNXdK5*;E+<aqCcn6-4MSQj~DMUx{
znx;7)M0ZVg->aJJ!~KTqq}}|38rH}3AwKNP9I07|mfRr(_HfBFoFt1(eCe=8-6;sR
z4_^-Q{$;hY%Jw&94kkH3(fng9=8jBK<?^DEgnJsoF5o!&Bwuy?kImLIbNchM(JoW)
z#`6A5KwQ$~8DC&FM<bx<3Gr6E7}70!iqATUa4NaI*`%6j^T{t^<V*&l^P_Ady5Nuq
z{iEO`^6P`hfucDfT;N!wk+!7j>L6#^%>4DLRC&l^G^6}g+3Q<?cd>w*a-p*ZIN8mc
z>8#AxWItr@ucDbwed#nqaE5RP6hrKg7JY+z*HH=>fc!kR50UJcW}k5HHD>%OzZs^v
zrg$;zj*!HNkT_mg6p^$I0Olln7lx&0<J{X224>tQuq$M)jAN`&2UX(<A|lu<&j+zP
zupM-titk+EgHC3m?nv=tB&lfBrsAXqgk6&<SQxKPE#Jgg=#so|z-ybHraqQv+_MzP
z5R>GZ*kN*Iq;05<;A{w*^N@5#+6M1!Jw^WhgpNViq>$#N+Mj3!n2)F|VZ5m0Ds!d`
ztF#%wVPDsF7><tp+R8k#f^z1-d|4JKJh~y*t;Qk^5nT3IH&=lAhh@g|=hIC;RX+Wz
z@uu%w^}JMr;bcVEkuki;o&~*pLk0D5Fh;mS5W*TPxxnqy;AD**rbxZs1>tCJ5ySh1
zzbK&sloekFW3g3;wY9bHOgKgbsIe~*%ybq3;b8INhrY~5+wB1IvExRn7FtcwerIPV
zUKA!kWG-*!8WF&s05?F$zYkTzQ}3L`@?!<K1VSB1D}aH3UXFD$i-6DumY$AvS|24G
zA%(DDvToL-^A|i+0l=rRxNK_)O!i`-QGYaxkb&|!75Y4Py59L7W4D(6J&M@I&p=^f
z4&Foq&o$5431VNf!@XdA9Ha1*5)m=&Cs6Jz{}e=>rdQk?gR&AGSrdJB@=QHM%1+VS
zrBXbdsN>>x2*PB%c{o8)_}(|0yD+9irWP2-aAxGiG*G3d(%DXe`*pMyPwDUnHlF}4
zSyYxC<D9uiW(PIKmedFo+1R-2Nr_nzH~E_sSe5oIZ2exn)I=^C+={+wb~U~I_+LXu
z<4<kpJgERtZ%QPK0(}SPnc0L-r$jp)cP28Sly=Z%EYbKb9R^(ePudYOwVBdEfwK73
zL*QQqB0wLh?F=}d5cyx?&KU=!UD!;q9gGK4nFx(y=xT=qfmZ6WVpcSC({y};v&m}#
zZ$X|Fb?u+I$w4v&zXG#z3H^T8a#YrVS<jV&T20042zMxDaf<7VR&4)xI48GFJ8u%{
zbcWC%ghCqr1Ao)e23t8o{QkI(Ex2(Z<}gyg+vQD^8|14x{VNcC@fyDLez*GN(5|1}
zGerAkYF`r$TbDfw2Fa|A2f4?ExG(YrcJJ&SLv6aRhHH+tXI&Yka~U!!sbsDfy`z5U
zUoa*q65nGP#;wX|pMrRdjh%6>T~qo@lj?K5{NmT7l8NMwF+U2yNI1S&(BcYVvlW&m
zD=nsBc*qBH6V|?YbV6n;)yp{`8dO~Mzl0cZ_o*p7ihFv9mhcS^J$Cr@h$~r(Jhzxb
z+>kB&@rZZ}>tKlywPUGAiTOT?Ib$1ZacwsL+22aBgS+8?O&P<1XT7MZuQ)yR1|kd9
zq>q02lWRkk>^c_=1Vd%x{p?>4NF)a9;{reQy6MXL#lv=g<Ia*-P>H|*$~wpuy6g$C
z@1vAAm4*bPyQd%Rvo(T`o7q@2?!MF)Ylk06Whoe{tuSVK?K5#i<gzWt*!6&A7wqlB
zM0-pwzfzqz7!}-E6)^RdhFf#@4SOG^7-Da5P_VpMXGGGi-`^==%GjIM3crqp4)3XU
zH|EIURq<{^%cwBvnWQ36P#$-z<yCw>3;fh$j#LGrt%;U9g-g&3LF%QRJDr;~`1Ztn
z{SRXhNG(vk6m3S@E)r;-!U~SG9Ow;}HwkEDe21s2C5Y(qh9MF`vEac7NlR_3lj<3`
z-f*A)j5I{|XAj~atziFasrw;h&)Q?EV}P1e?wB{u@tH7egE4w8cysIt=M=JvcUzS4
z+VhjfD6Ecw&kIg5)reL#><2sV?_KY%Iy=GI>>B944~3}zA5Ku|&cH`91VAJzno_P)
ztN`X`%S;=&rl;=SHrY<gROhk&04raHx(@s7Q*JQls&KXK*$<)z6Fm@UcuM`S<f*e&
zLQMkQe!Oodq@?^Y&ky2A1PAx5$niJN+61rHsEs#eb_1s~l04L~iMs(C<El=2L>gDm
z?&Q}o$<^C-&Sqni1`5TrJbn^y5bnVizn6e-@74{whIC%DLdWuo<<tem_R?^|FkLue
zSpV`9@H*+#BV~D#<s!dKWo`kLQ}BIb8P4KAD)vV8Uqauyf2Fl{?jmXU+-N5B_&oos
zT+Sk4w#HSPVdig{GUE7+Rckm-pXv8K?xsfvXnio&70!BjS}ZlV;4&_NC$(+&*-57F
zpt_%HCB}WX4&DVVr)izksaNl24cLG1+oZ3K2Xa5QMQZ+hgsJt@QiRS7@cPk=P!mI2
zAV{x{)~n_gAshKL?$v<68D?!18_zDh?OYfm*~;oe+sE8*H1a_gM>EYNf+!R=PEgs^
zv3Vk+=hCB$dXH~3Pz9UeD3SbQ<wnJ53bbk#R_7<seK<EcwEY0~4Xi~}JN^F+SfN%|
zY&M+|0FB?(zpMLReV|_pP6`irL`ZXsarQO82+PN+iDn~F+!Oz%o<tI6U{$BHhB}-S
z=c#Rw>Vd>cC!fKxr~Tj+N5&?zY%Mp{QJWq4Q9(q4rf%LFC3cb{_Q$&;o)3Q;y(>MQ
zxeb)8;M&!oLM7%3rbA?a17mMyH^(F3>^*H_w}`3m%}r6oDyO+vP=q6gJkc_DlMkjX
zBIY=_5KG62>E*~KZz9K^`b>Xim}%AqQUBh%GO8Eaz1sU{3KRc8{LDeg_Uhq=zbR!$
zxky(F?CkT4LXF;v%ONLIWcJOIb6%t;bfiB?TTR2ekC(qJ%ppoJjTBf86iJ)VWM#SQ
zRJ<qduGf_Y>(qWw(`WF>r$iAV@w%2di53KTH;qY4i8Jsz+6lVBwJ)<+?$oc!hvT_*
zouM$`$GyyB0soWMg=L0BZP%CFfEY>--p03-$-|EOiZc%zb0tht`J%~v&HzqR(xc!)
z@V*>p7;bo*znp^y?^x;1(#*u8MSiz|j>g!CkAI#mjIpmhn5UJf1zq926fIbhk`oGl
zyOQnHWhijRgY{w<zO;T_tC^AGHoEn%?jQL<ucyc#PU}11kkn>WvB{L?1^x^>#~H8>
zKUps?SnOUU<mTUu2AA3nP(kSrKuDbN7S~?eYs&R#dRZQc_8%dg^E11_;|OvLGzT`v
zNC%xRxy3yy_X=wIBvTMal)LVoFq-iuDV<YO+@R8`vpi^WQAl=swRp4$L7@UlCx25h
zBj2r`kJd=&Z6E@G7t*s31sP!W%}ezlchk1Ijp*HD8*6K%zEE`u!K``RCz3C&Ko{n(
z1X)IXagJ7mVw=0XASmoxSCIEh8y76wt5vVA36NgBX!s%xHp3O*|HZaiif<HuqORbV
z*G1-M5X0#!cJKl95}GZ2>;<9N-*&SSz$t;=LagqwrrhQj1qXs<ybH?7|C%uU<aKP$
ze_zANsQ_PKf+se)Ku^Ud0+biQ<Y1sFYdN34MG$J8b1fEFrgj6YKHo9N?iskOqTozl
zYA`=!9FLrq+Gv;Hg8EpZTyiyzk&$QjTZpV3SEnB!DGQ>R&{oi&iVBz+x!$0jW$35E
z#9x2d3ga1w)FjqE#k%BK2+}*(K`Sr`a?ZY*cS&t)0Q6WC8P4Al^;6EUcaty_1$iH0
zwD$9ni+Qp|$MN9)sA35V<S#S@g-CY$zM@PTdu@BYgZ9B|awK769=>A;-Ctg6PJVOG
z%M{E=9kWLO?J=Ww)k5=pqH3qdw|UF_Gu%dA&TFk7)By9}EK^1~ZrIZQn<4l)(}eU4
zl$pAC=nD$W*kPEteFN#uDgXmnztN97F#i#dIy$Jrc#7rGzy8W)s`lQe0sv={z`9Go
zy1e6Ry+(hgI5{i3u(+p^y(FhJTMNyBH}%c-iL?+VV&^JYCFMON{@)8A8VCuCo)~m~
z8xo6}8H#%pNIHR5UxB(zB{sdr#@;3~42#?|vg&AC^LV0uj|vj0U3uxi%U4U(?r^<d
zb-?_AmDs;&*-=XH8=V&M;$t~E+%kET5I2fT>#q`*F;<L5MQ=z{3Mal;(R7M^+vpx|
zMoN>b=E5g+$)9gi<$B(NU-hV7!%E`C&lB26d4Pi+1j6~ay){9E-<4k8MWQ~1tLFaF
zbRHm)yNM0x$Y_ip_a$d8lxOJ}JOAS!4gd8@wQZx175wbqJous7l+Qh1*K<3s8_V9q
z^BG3q=6G38O?8*4pCM>XK=8cv+ARulx#y{Gb#-xg#X(%%pim~(mIN`Z{4>!V7u(Ew
z?6DE;YVCPJ_}pPTLXQb@Oie5;42D`_^)z}QHh9nz_+&#gUgtwKtWq-%j!*yjOcadk
zT3i&b>=4(g%8NuWxxVYRWKaQQ-IITf`f$0(Y-5QB3SVvR&AnZl7rl~!j`5k`uu_W3
z2rW>jor$BDn$2QrJU5>V9PBC{$cY^DziI6GFJ43;b|W0&(nzLU@%I2jO37Th0j-}v
z5Ilh7WR182%sZVU$p0VUrk5SaXsQD`N?h}hK!}Kxj4CU*ts;EmMf%P+?oB<+>33cJ
z-=L`JdM>R+9%l3LY1m-X#M~8ZG}bvB4A6Tk@LRV>RpjUGe1N>fzJ#@#GajL=jP4<0
zjHUS%V@#i!^Xs*7IVa{QpWO+P*O58u?IKJbxv+h9mz(G4bHCFKhqHoGl;Nj{`vN?%
zV>`|TaDz4ROsAYGZ(6(j)LLUN9kViEorq_P_qlVgU){mUxU9y2V7nyy@+&g!hAg|`
z?jsux_HJa~Ty$!IIMnu<dEs?<5OARA@FmxKtV3ZwU=UFpwp!eym76X@N&pPYs><--
zO8)%|HP}A72mVRAanZ(rJ_}E&NLW#gv1FAy?^e|jwY<>LLZ0NeXgX7Rj^9Et$NzCh
zl}|)U7S+dg=E-R?zR#aFZ04**`mMDdzxeog)4HWl8sc$WtvHcQ6u+IbB8d;;-#rR6
z$3_`K2m?bz!#Qs$6X38mX;_37u-%9I!HcfZA&0?|9@An3J)B(jx<o(c$kdNnyDo^l
z2@Uh7#(gN90GY(yd>N3Yo~E4JITs*6=zc(y=xo$SEvdg^)=oWLeYhcY>A&F7er?fv
z7H-C{tPlk7Mj8y%FSiUL;Xv?^07i;^3k^|OcPgRi_^km?p6nGV1#V_@8%KZ?t16UC
z4DJh~2lpQrO{moH2!zBx+eRiS5*sfXivtn?Y&*G!r7?6E<c}8mY=&;=N%sM1MDZ)I
zIU=oXWz1xpG)+}-Z`IX9a~kN62j-vT{Fd?PBJKGNK+-z8%N`nDcSp)+!o5^iKzD`V
z8v#=U85f%F9hRytq;Nkj=J|8UPXo4=yMLbuIHU8MON92)QOB1zA(_<}q@`2Xgi(Qd
zgsT>MJ4jX%#WA@F23)j5`s=M0&2`Trdcobm0uD)RL&*EJbqA4&zKpetv6?`&un!<`
zAEMQvr1QAdt3b=_T%d#4-<vO={o$R$hPc*&Q7~Q`>fXojgxpgc{&X=abv=3dWrrvA
zJmf+0h}94*a#a_a8}htMe$+VdQKQ<9x=Vq5r6W)JHO)9G<vZ{cQ606h)C~-CHGUrO
z{Tp+4#3fja;8CkWRNaNS1(F>qLO66&PaR#a4sgQtMMa?#kzLsY0Xfo~poC!hq8_jE
zZasZR%T(ak<q@&1m6~iBm2`(8NxUd_Z;w?a*Q}$m6WN-eb%4D{SEoM9beWwtVt`EM
zo7|ec<-GQLw4@-HD;krMT?PdSRu2N{oVKG?9VKexmjL7}n<+&h>5B0FvStg~2bOhy
z@n9sXTOdSD;#{j?zO{U(kh>QLUj%pHMD!o%&3R!j&}++2=<MUNfG13%23UwRo2^1(
zT`*}C^u`Z{I938XoH!7n1;d+x^V_K=bstNT6ev?Uvsf3XJOH*#*%0ynqL5z@gzh}@
zAkcImzs<8`xAc9v21UO*fUahp5|`GS7ClJ2T6ZaGPYu*B^MPZLPQfh@f@U^l?}}}j
zNoq$#(XRlrm$v)Yd9+jcI_O>?fQ8JR9u|~Al;aLI(_qwZe+&L{MkB`+%iNGn2XuA4
z2;h6({}Q;n^NXAs$jAl8qORK*2)ZN$hJqxNTX>f$#9hN7_Qg=R-*dH3mYFg-h_=I<
z1$SC@WDox@w@1*?FK8MqEtCY(RLdG_@~&7QKoh=V{}ptxB@5qwnjhQB3O}om(yOFj
zx&ToS8nGkUvNal9Xo_g+kyv9pFr}SUdgQI2+P(>;2Bd;4HakU)cNqbI0;I}fHyE8<
zx4dV{9uzpubJ;Et8<oNr6_YLDrjird6&D%JM}qiD9(_+OywzUd&Bt09QE*-H>~30p
z2kc9&mfI%QbDZ7*(!Zm-u4>%DuJFuGIs`?KRS10uW8w+<v)5A(hC0${J~UKL%~|;C
z#OlmS9$X<fMN&wjL>VZjI30P_dIo1gdR3y5SpX7g!dYcc|K~j~&<yH8a~(%EHLyHT
z3;3`-)5}Cv@#k<zt~4gFlCjZyc{qcmEiO5%%NiIZUcYut&xb!L_L+iNWb4??w#Ul<
zXU7pLg0osxEPRE3{Ob&aI_#v(+AhnSFC$EsUyzEI=|mQ+OD+zlrozIUz06o8`UFbI
z&~7KCk`mYOwI+nEsI}}`0K2j9MZR^AqMz3Dwf7Gr@*s@wyL3PX3+I+Dtg_HCBi-6w
z)dt#E-`!!D_6mFl)NfB-dF|Pg)6EOenz-Bwckma0*91y4U_wC$^ID`W){J8tE%wJF
z2(!LQ*%VA2=k{Vvx6JLF6coE$wJ3u>5-{c#pdezvlTZ#a<vOR~5Q<#3U8oOEA{dol
zCzot$GBx9A1t{f?YlM{*TgjFxzt=@jOj)br+FdRBh}1s$aX9tW+V{J^Yn9m_Q=|(o
zVT0%N>Dl<cL&^3>&$3i)TA}oJ(UXoX-ab`>7`2tY1%fJ(-ahNTwC&LZ0o|=^->pdA
zJQ(gRB@|`*fXD;5Mdq8z*N-E6nVkw=n3CIX{t>koiieCQ4@(YMdGxR`L?%=|?b>GK
zVE48aW0|$dX|q_Ql;f-58^Jki0yd&;?~*M(3!n@Wy^t0NX#RGqjwNWAV&|jMM8?s%
zkd@1serw2?dyH~(v@u%5v2C+-1dDlT1OqmO&D!!p(2KzcFm@6NsfxJ6=<xXNwaj;R
zLEtKY<7j3yV6jH5i%|jwzRQs904^?zNuwK!{aFG_vp07)!B*(W(1d0ioYEjV--fD|
zz)SG})R)+l<KX2}=|bba_>|Qx?GC0oBG6P#amM|k%!C61zYPPHL1PEzj4+Ez@H4aY
zC~k!KN%;i%;YCQbr$uF1>Td{`@*!sQO8mUbD|LO2MIx1ztrwtw5W3Jyf8cS=Z7%bx
zqpud|!`5Ar%9?($$?n@Br?+=3CKG-LdIZ&mvPG+ZGThd&r9`{#(=d#Ou_?I+w5JdE
z-!;>%9_eut!>U)XF|bOyX@0v~T%>;U0MfWxm@U^w>4Lz^!7_V+0TUK<K*#C9G|`Di
zY-fJx?czI$b4i3%ABi-C=|7PZT8`@~W&2BgKsPPe=S-|zHX6R>=PW2%k_byz<mg9g
z%GIi^_VV3+oj@fsbAwM@mwaexRX1}$8!!8{d~Z6lUfxypmybBbEH$Hg2W)*iAaB~L
z#q;&(Jx)(vJ~Hrup5Da_71zfbud$=n?r%P)--IzC1ZQRMkJR^;wc2#x8cFLMzYXzD
zZx7(P$oskZ94I;z`{u<R`Ma)58`{*vcnIJupgPV6b_#o)qZ*Md4?J*f^MIrlQ<QZ;
z(kK&au*UD^Y}h%<$^q;M^!El|fOVlO7VE^2D*7?Vb+UTj;?^^fu;epB@I2f^p+Zf~
zOd&nRwoJp6Fkg}LluMoWH>9gbIqzjaUNFmt>jyz9WWb08c699mz2E#$=`(X}QyF-u
zF$<vFkgS-ot;V!v-iywHM)Ygk1|rFpyp^u=Z;Nm`-wLUFZii$M5$J+qqOTNtMyl{B
zG?M8wsw-VhaEUxr1_bwJTYs1*49gEh$4kz|1&YE7I<sBlSMbJXvu(N??ma!%6NEzL
z^!p}V;rY1VB#m<4z&JRkKTtf6#K+3bmLf<HY%%#eIn){*1liFIJ0B!R*}Z2Pqci7R
zQQr)=yKbZ^HQDS{aKhSY<Kz*h_`Mj+LdJnPCn9tUYDF8`xQ{Hm7B4D}BXpV_85skr
zivOwK-kc;QppCx<6s@U7T!<@~(9fS{z7*%giMWKid87YEqq2vLhGnBKofMfhcxHk0
zuP)FX{(o^jG+wrbP+ra?G)UKJGwhP&T@~BB-KoSD_CE$II}<~T=#czgcsZr)Z6NFe
zl&UR1a#x%yoI-La<JeU*B7e`TyrWc5QH^X$JL~^ZTJ@0aSE%pECAjDUxClG(=WNEN
zAa5yThnf**C(4kYOk5WrU3<%M>5e42?CixoPFtErB7Or$N}XJZy8JG|#oP%}ES}cz
z9fmG}&<FBZJ$~c7z^#_EN41mADIr!BZCit_4-CgH1S0PoQoV*D)Hw4*0Js+mv3dxp
zSwIEW<&Nuoyz=CRHjZy?>dq6}j|ZCb>8FY}()aeysNWa!iV8R0JUQTRDsTVNQCF5Q
zX8ntB>C`RG8Jx17`-zKy@~rerTWXU$$J`gwCg;G*RMZ*r75<lp`SL}zLq(D8W^=o7
z4ldx1z^s+Fo6xWSTbgGiWcXm#^`)3OM7)nnONhDPO2e8!(Guye@mSj;z|EyQo>*gC
z><X=y?xiQ_&fRJB^KabSD>)Q8lBz#b_WJf*hd`|-J%%#!>#QJhgAR<$=*ry@sUWbM
z@Gk)8l7kwh-jAaWClOcZJcQ!zd{nPC4YH=_nwT^jP&8amq&oS0!C7BRw}G^E)ET_B
zMlX(tahCe2!!8&11buPk`<TCaMmerZ<+}+RU<rn(X-HiDP@F`OCW*i4gZYR_a!N4)
zj+D@DvrJbtQ~ZqKpaLRm{z<mfVIP*_i|c7@h-|7o*8T?Rvh`l~uanuzr>7eS<|(ol
z<v!kD^|8OQ=~*CS2;Xjv#jrCZ$Y)b+K&17VWl}Wt5X%HdE-6^BTxv_?LCO8f%9PgI
zkXunt$=nrD&CFAxj$`E>JR-#6HB{JfX@hV>1oYq^o+97<T#S{GzcCt59M}AiOjs0q
zY2`*v>ES!?x(_4|@9D*onww8ezJoDR#{6dJ3x9cJ#Vf6Ior=?F&;hQ*dg_ApV4q*`
z1Zn*^?Q!_@kwl*|+?a<_-&8dX%GNNIh==cpQ5l>*@K5$MR~FVIXym}JwacUtKvWE`
z%7Ox&bX3Wfx5GltK1fFlLII5IL)i9qU@chw1C_-Vr=gx-lu4Nb`MfUjv&5JrcGUDg
zoZ$P=+Z(jSEu`FY)_z>Lke3epO<;IN;MM9rs(p|_MlcWf&xdHEe4&_{iyc_EDM%q=
zu0Y)f9P|^HHq4@%_Lm{(Dzk2QRs9PF!KjZ&B@ZnwJ(8Vi1M)h9N8|qGU|QuV4MX@Z
z^}J=C@2Q-gm&S)5!y_oDy<aAYLaI)@*XlEkT{jn<Lg$?7!1AOSaoE?7<jyu}vTwDj
zlu^Gx7~7tAm(+HQOS=*Mg(3KoD!$*cAC9LAh4-Ae2Y^QofBVpK#-wDRqqxLO_!oyQ
zMswpkI!`||hwQ}~z@p&Z;ZTl_@fDkmkr6a$!ca_$mZkU)848&lmzsJb%y~vw%vcBI
zOhNYn->+`v;jhx1d}Yo_pg+q)aN!jER<ulTRlO775Hp?;&S-#fwTM-+=G&}vv<16A
z_L|$iM!mV^BeN%kLRSK*P9I1yb~9^MY{geElqS-XIDz3{ZZ?}~vYZ;aOAqxI#m%ZI
zp6ZACZoq`3$gC1B#ZWVEDJibHt&>*|CUmVd_!2k+`EmwExx1xeMzOS(c3PSaq?JHX
zmaEw;nWE`0KmKx-ZIZ?G2W;7lDYBu5W}k`Y7H2yCA$kv>Sv6zYaVmZ>>>vLT6BrrQ
z<{lG?<e$mEvS)K-Mbzsz?#Nol@RDv|%nX_OZm8+2TtU3eYNqf1rSy4RL9s)o=v#QR
z16(`MN$9h@)UKPQ*yFM!t6ne?-M6}4NZx4pkEsPf)U<q{&Sy~DSMO_axI0qlAtV1S
zL&8NE2zF#pns8M(vvQgjW>eRZZCKk4jA&_JL*|yo<f)^P*zY|wmqPRg8|8#~l6<Px
z)v=2vT|2+YP1S_$d+)O;*7)#od&c<wPv{Qb)u@05*63-^op9v9Py7n?VzQg*FHJOZ
z+3%=qU5%m6Go0R@95RV%b|qfnIm0jGTaYo$NF`h_-sDOMZT0=*{hkv5-_3IR^)$1L
zac~e9cW$lmdNiBPP$7Cg8BVU)hq<5>veWuraUsVrYm4EIedwDv@Cn_a(vBiPh5QNc
z_7=Qxz2ClCY4q?;&+MQvqc@7IznfRiAarGVx8oPn-yd}3f}8p&k6Zha*P#qYd+tld
z9MZLCh0Qb$ux7Z&$Njhn{xs9E;V0+V&|g-w!w7cn;g0C^v(86~r`3X-dOc^2TwmMB
zn~T4e*WNu6#M<A77$CzrmbBX0vQGCsN`@!Y#v%qk<iAp);}JY90GBoM;A}%$59dB5
z2x05KRaN@}uT_j%;V&Jlt#7?CSgzN-rRWq2Os;F-*0u~TEkhK}5-gzf<L`&52u^83
zz{JBcKNd(=81utz0CoQ0LG|ZY!Lz84FhEO^W}-N|+Vq%jYlI+hHOOdtq>{VUNvm+K
zG=$N7L=-kO$q55r+}8VP_b8-av+^$u)bIW*ic+#eX)V`Z;&mztEA~}wzSjTME8rkv
zX}}eH`f!LM&GaYL2erY`mY?c96zLLaAiqEAKN+z3&g(!)vvUK16$r$ztmGTPxdvzV
ze&T!#3_eW1Tbk#iGy+9wm~#sI5}Xbjmev{aXG;oLA%cm5_uRbF;ukuXr*bixq6ZcW
zU3m&({fmdN93khV8s+emnz|T%25#7C$A^x#@1$;_#MS6|2~xHFys{@4w<IJfmVIf_
zmzCC);#kACSC#$l?_yc{(b-=JTjKN}cevOsauBH9`31UQ4lMxV->gBfdTqUsJL1{O
zK{L$6Zito|FiwS1@p$wi1U#DDxmvvADjsOmf^zd7R)}%P5UM0Wm+{K-O<D<bNYTE5
zvv1ttq1LC@BVcGat4TOmgY3%Yw=MWBJrF&F;6l>O;NiWiIhdgWxE2r`1bd#O5GL!s
zy=Ta&@{~(UP7^bnN$3rCt&J3{yvA&i3s>N(iz?`OJG@r~|2uzIGd0p_EE~u$6xh<V
z6HA5lTpLz}>A%%=mHTI*o;HY|v^2DY16BWx+jHJyx4T&Q1AGQTcNhsD)o>cP5s{6e
zQ(^TGT;18Iq|P|^9{l$9{n>AMFNstAq5U$}iIdg5qEgdYkEb7*I}8c9KL2#BwSv8o
z+Rh)XpJ8{FhPhAjh3L9qx$v&4**7NxIYiyz>Kg8P=RM6ews+_^6{%0}i5xhH%IhW8
z?6uLN*}*Ls93WazK&9FwwZ33EczKBTUhn<0F7BH_NLTv%0UTa{|CE*R^Au7KGek<l
zgQpU&!SXSfdm<!U@tLhT`JV}ZTiJyi?5PQv`&>P|Sjwe4JlH&`3Ge^+t;rg1X?E_|
zl=WtKhuT7tJdp$7S#3mmQA@aSu|fc3+l=?bM~Pm9BVAj`msGeNN>2%qXPh2`nSphk
zO?`VJ3Fo!ox^Qg<-SyClZz<n|)z;`eaCHS=K>AUmYMl5!I*q1fEICUPS7(d$+|s@h
zllJz?PR@$Buioz6?`iL98Hcv>*_^Fyc~7OU>h%9Ad?hX8C_HmVXc4Oo+h9}NMU}U8
zuYtCYmOXb%!b?&@z26FKQu~dta>u2SzfmW*%xWi(_<VqE07i~y#p`3yNvFhW&?sN;
z81zIg3$JIzbI+3xe>DoEF>##e;2GG%0E`!D(7rZIJC^b5JkA6bKp&=hSc})=UGso5
zs@=O5K$X5o3{2$hESaxWEy006rMaj}-tjflv9159!$pErfyA)r;fnr8gR>8jLgfwm
z=LM9x9-zu0GWwMk|4pV454cjLYt>WKBFM(E_>cn%w4Gkmk*f{mtRJt`*jUwi^iJZ=
z7gx{iY8D%y#YoZ|y7%nxM_Bq*R9XKpT1`j<UP5#@Cq>}Msu4|@?QUM~S#1<JHda^*
z-<2Hj{{xifppiV82$Fv@>Ah67(URr(cwTs)Jnj4Nk3E@M_cV=tW{d#v%5|C-C=&61
zKi;*eYmX?)Pj^dJS||}gj}jGJiTdp0z&2#$1v|D05`e2A2l=C>l8no=#d!=*xv-g@
zwr>qhQwm4m3K%u6mfF{522LoAI$+o(%M{8}pLq2$exis9k#ssu00bbzLr<C5;Tjkb
zN2Jf)d$|!By{+rYW5?uvMOF_eWH*o#$OW>Y|1yN4&taBJuv^=ZGB8P#O-8r}q<0d<
z;lrZu8vq@_Z{Z4Q1FE**yoyHCbIS1zdjZ-IpFSQ)>50=YZs_U<m}*BX0g*{MPRcKY
zab)d(F<gD!w5Y&%!t7&)GL+1(@h@kB_ZjE}4X{VPGq<Bg0^4IK5-vtgkYWsa#FU%g
z^#lc2>D+3buQI{I=8ZKT?gYgU@h6n<oiYlW@@-Hdn-RSN!ZMEYnM%DJ%PuAhTcct;
zzJ2A2uDdk=TJh`*rIYe#g4NtOkak*+{mvH-hAPv4_nSmN^AM3*O_VL{B`PwrSVFw#
zIf5`1$(au)Da+AbNIAloKnDu3=Xo!T|C<=H)LyG4iwpt6TV5Sihta3yO~{`uS!(~U
zdDU!aUq`UJy4tP?w$G+t6ICaL{S@HRh%&}jSa^_HDD7RO8}+o^46!K8`2VoRvtpR5
z&)}@#!Zj;q{N`7}bsg71z=KOJi#^BW(?@Qi{@Pxo$eCX3Y?JFB+vtsjWK^Lxuh%c~
zdHXg4pTao{?ptBq%EGF7Ga|U`MBgCX6{@y*ta^Ji-@VUi-0cxK#iK5G3fv<C@sKve
z$<?|Mv#b1mGKowNw->jga;;{^avo8wB4Q<VX^hzOloZMS(WEJIvoY}8-0Nov?{3-=
zba|VIqQT}6f<->HKWp9JVphJJ3*b$pbPoIXT`G{@0Z>$EKX_@%4&fscR78f=NBd2!
zD)(2P=pk1kNr*ZBj{lH1VakilY{6^8++~JALd<oPWjKSTDMI?8bqf7_9S%P~PtE(e
z?WKYMUZcvsQR!7XuD+XsvsgMb?i)9v>BetgJ{t~O=E>;vakf`JuO0x^goHUhq$QUs
zbxO@f|GWitu^Nt5^~+HIGAV8$Yi}4_xfwN~T5N+DTJh;fxyC!O<tM&i1M59@<9@wy
zm>>H=%4WI+5InYXs%EXghCIEgE+<^rIu6_ydtcB90YkdisO$`RgOpR+)EM^Qgx05c
zL>T*lb)0o>XCKZ#aDj_^jwCDwu^}{d@rf*`aNTFz%`059bH8#k-tHE;#jjKvSV9Mc
z1;pgbUVr+g{;OSbrndDQ;7+spiW~;#A@7IKz{f?n&=9cUEjWsccmFBWjG_>>H4CsP
z6^<IZobB8Gsr*vMU!U%v;h&;t*fP$ul&aafMp$=zcX+YY!d4`QBM?oA?3hG!7Pds?
zumN13I=uXsBJzNUlfd496c^J8r3x9mHnA(f_JK!%|L<NOrm_yn3#Gjqq3))8h8PNk
zL43u>;Yo=5r)~kd2K9WBw<Ygb;wTUTtzJ`Qop>&952u4FU=U&_m<}tw%WtdH??kVL
z>yac|_hzFVtSdz8EbEvsLx{D#1!3?=Pl=?LW0p5`EiZsurHqCMQkaP{NoOz!gp#qf
zF1%yq+W})I_YO9`oI8IyC1EA(JvGQ;$owd$-nOH$?R6kSO8+=Uw{~w&cPDlflq=Z$
z3y<=JA;gyQtJ!YJ=78qkRmv6Meo<Ijpa&z+lGw<qFvIZPER3>WzAhrUOem5R@*X;h
z**5B_WT^tH4zWCU1t*Fyw%zL@!l?r=qF(#a4LESwqA-pSLgtyb65k3Fvb3tykbh_o
zrrBXk9GVX|yRCQ}<b8qKtqYqVgO{+Fn5ha|nXud<L*Mt~a=e@`6D8UQK)X#vqKE^e
zZd0*#4z!-7qn2;<I1Ycz)7b1~=-;jvV+NT`O=hbrPD1<0gD6XwlaQnJg0HQ+lr8Fk
z-w^QAYKZ8aa36>IIxMuLw{HqbR5ahpW5(1pTdDWTT2dO2Yp>Qg%mz4UUdyfzy|4&q
z=KN&uadDSybBiTjaRq%BRgR?#2C}i*x1~=-R-Pl?CxQS4xw{kTfh-G1EoOO<nz(Pj
z{ATATB4WGtR_g~`Vo%ITq*R935$;}mms9AP6R6a23^d#6S>_aOe$-2xIew+yec>~I
zdVz8nD&D*wU#@5EnyO+b%?n&CWD2)Avv3x=T##2j{?6O25YZM}W(R}|N^iCv51aVJ
z)|W((A{5lK;raA}pspHau;xE&*H!Bh<5fm%E!cC+AooPbr03Bvc9{~Qu9ri-Fz1d4
zRaCXY(PLIp)d}CJRa8<u^~{|1cT|-+rYOn5DDSSUr-BvgP%g%+Wnoe18D5T?7-M3-
z@_EG<Xr@@{u;9+xpj-ylp50Q{lhkO7_j5~7oT0*T?M;c?%4Uz1|I|oQ)EqP0z!)&J
zIvBhaM;Qz8IReCv3aEIOB-}&|TLO+4(7JF#T4va{heMn%@rNhl+hR!{W_umc!##gG
zOSKW}^<sII2WWzq=D77@axXf^u<CgNNzIc%T%0`L8FdUUAohj__H~Cxy~KeT6~3FA
zaZPk5TsUZNxuQSdIZKDh3r*86-D(fupp6PMI<(BRHN=d5zhrEmKi;}|HD;GFI924G
z7^DF)cr~~I>CflXU-#2tw*LKZCcf~N7{N;ZdzD=$Af-Le7u@XfMCH9^Wz`W-4f<D|
z*8jf1scBwhW|KIgGVBIhrj2Fd<S|NR0!>o|{z|$LEAcw3M*qjIZ}dw*{Y22>NIXS=
z;jiz}q+*1u+JeYa3r*otgI|K*>^vZ1zFg`O6BnF{_QI!WimQNOKsu9#%Lz%qu@UN~
z`L*+AqT_yb#+{>1qaPzC_veme?|4PVrDr6+(1q?Ow`c(SHl-bDyx=sj%Z4x#{<%Az
zaz43*?e4{3mQXDF^@}l6Dti$tV+NI(mWJJAmMl}4;f^venEf_TllgdM!x7&#m+<g1
zv*N)DI8+4I_vrb=e#|Zh>|u%!5D~G>IFR0jIrjAfmYK$cqfHEg3>MKb^&f~zLNwY#
zr~Uy`9u=NC!)eX^x47WWKMYunA4DMo=G2eDxRR2nOJ^8XTHZwa0!sX(Fd%BY!Jf~F
z{GmQuAENORd0;2N_6bR}B!LuU=U_{Ff%y$A)p`PmOAq&%Y`oj<UNdD@x6f;D{>F>%
zBV*zTMXt<rFZ1!JyXDEJ`uf$PEb@gJG_S$s3SOaRZY4=x$Tj&o<LL6u99hq*18tz^
z$&vVWmaqXTQbq$<UTrorW$m<I+Iw%uPU`5#Z6h%)`kbeIpe{P)l^V@U_=aL0!(n77
zd^L7zULO3ghMR=_Y=;IAQ5)oTbty`+kMg~6iqU^F9J*S5fHYRiJ#N+6x<RU?8mra4
za&&mdS>F1Kp`MTYncLJ#6lx;_9OoF%wJ_SjTaYz6V{Jj6SkM3P?r&CaEda#o4?N!E
zUpudlu#*x4rZdmPHp)?;C6UUv8I$5@cUr$St(HUZzj1WK%nY}(73`y~z-V1dnTEkF
z2ju;sk1WIc#hmNgG7Q0Bqt`upga(xw=kg>xZJZq;?^~=SgH~hqAD(c>UIpKSYx@O$
zk?@HkWUDGRX2Ud8vWI{*DF$1*SKBd*jUL+q%@0W#PN{vD!i|Ssbeusgt5ab#n&JV=
zSJ6zEzfj$|ST~?g%89VyvYN;OJn<V<iX-TUItm&@D<x`b33jdJBqyCNIZ1rqb)!Q+
zL56*NaH|Px$sah)8kO2p23{9*C}M1zBea9)V<#J3C12D02TevAG-sIDbvfu<3kZ=m
zy+aSL7A$;<8yNZdB?N+AV^q9o=aOEgm8NxLbDf2^{61+PG%Mk*Vmd1IsL-9BhRG|u
zmFgt?YKP9YIye)6K<8?`grUIsU1Y=UN>F>NZ8lk6XfO<k&MoFfA0XXA7W>~psv-%m
zGR%<gvNKqK0XyqCm(EAigrNmgkw8W`v1Vr(*1X*Mf8Llha{3T@_RTq>w5j;nrGr9}
zXTYx#`(|M=n`BLxJHTHg5=_$yiY}Vn({p=a#e*rDP)#yKB^r=`g^`C{l(CuUjV$(_
zRW{%1THihANC)m?N!)vo0J(BKHPsv~`kU#liNt`x<%1Ci%8dxh(sZw$9JFk)3>JC4
z&47YKS4X)(H~MWNHma77%1Js;*@{d!!Lg|^P*aPsP6XA6Wr+Py#|KipLj_;!*^UjK
z+k+6Gr#hd9MHsHf{4?Atj*c<mTLGc?I$9^>OcaD4uHf>`4CJ&ehtnQ7><e;*<=2|c
zwdr<>zoSQs>Rjas$^LB({hX6aHkbHNA!&2MQp1s>r#cRmSc7!3%u)D)Qa%mE_=sgz
z=J+ZlV@0~|KM;q_C;YqDP!-ofTOqr8NCxqi)4Yfn6wg?Ui*TaMydxGw++|wdmHa(6
z8CFV3Lz=>wi7&K$D(>>uT3`d|R`V}zpkL`g)o1N_a?;&1Bz;C@nYJ-+YESSz7wM(j
z*;opn4C*oq!!g^O39OhnIpQEZOYnayUDB02_4?VEg)vneXUIVOE5!&#5d#MA+F6d>
zD~euUcZ^{7Xmy$BU3piO9ph7h_;|GSis!I(+s14>PNDC^{=MzUx*zKcn>wpSxr3ux
zt;?P%MBO?=EH5I(xS37%mv@c8MibZBmBkt`^IOo?q>|{H19B3=Sr`S6KTW9`2jdZi
zvI0fw!%$D>^3ZTo%KgcXpRAO%=pSKYyDaKvWiUJ48Lj+VaOJE6ozhlc!HmQ&jT1h^
z^-I{-RpL>Vsz?1ef6C_kzY@Br^Uv^#vg%^~8L7+Q)#~pT$TZiGz`DUQy<C93%fh!G
z=>~AS<9)Z^EY32nLPqcQ$(>t7NbwSCM76L65)uNcSw_BPj~v}h8d3c$7<go16<DcF
zlqNladsV|p9F7{JyI9;DIU8H~1Bft#Wd<Z?LB=D)Bgvc4N9T)rW#R<#xGc|;hmMrW
zdSj@-gVt-c?1m+aGeLi=)W_6#brC>GtQ?6}a={t^Tj%6kv689<x>AtPP_W6M{wc>U
zAD9JRAx!dQkK76Y0;TW)je7Ww50$68cZ2z5iMiiRy(t1j@gYa3x0QW-_3RfWMh3mg
z_7<m~5KOLgO&LC0(sE}A$(U6U8^rHJL)B~@_cND|U$WXrNJTPz&?wm%&bTW)@|D{m
zegUwG#%S5=Nq0i*OZzsT0@d2cfabsT?W44bpolf?Q6nn_gn__;it!kNWmU_bh_014
zW!7N0;f^5d0Yf_ns;PuCkHu-Of(4JFr=71UzK1BVtuEjSODjul`4h_?1IMxN`L61?
z@^%~C$%)rM(^_u_S-mn5bV6{=z)#w#e@;6mq7dP8IYcOKJt+KR^7?qFQ+mT-JbOaG
z>P0A6S&g=!W~~<Rz39;KEHqgtvFRz3ACnzdR>(gd)81QNZH`?jhgJnJU3`8I>8Buk
ze^ZIiva}N(THrVb31l{_>^We=_qRHgEXltB^CC$A^rl9*yQ~tKYi4z@bS<lVMNEY1
z<jmfm&_7%(Y&FFRQ#M~$3`mag=1A8L71q&f<IAsU2Zw%xUY2U$5!u1pp}j@?t~nS`
zsZE*Wb-9)pRC`LF>*FL+x3rwf%^Ir&FUW`?bdf-b!s}wIPxkY@SLaIVS|zi9fM$Wa
z#tIc%i>72IQfK@1!2n3O(|<B5jKDEyf<<-1GBK=sNb|O64(VmcQnA^^7|OHO?dx5x
zPnxZx&aKv+hi5QkQAw;dDGx+yl1ZGvdBI;yj=<`aahH6bfyk9;rF*5_+=wnJ-2#6y
z$EVlvKq-&&M^{m$M`(p$U!y$INPLz?iHWj}0>2&CXK*@<hekWz9C;ll)^7;QJt}fE
z_4K6u>^3Ox49vG;2K?iXj8W5s4Ml5>87?pH;)Q_+&quuEmX6e+Uv9$f%FK&RI3!+y
zCUGF>4xIMK_-*e96~6%j5a9WKb0-gMqBAywdCe9SEy%jMQNr{cl>B1zJW@{C$5t-B
zR{Jf-VDGN&BS?Y3q2DpVZ&PM=c53TZQQTFIK)6+}nyFl3zdeJT@*W5efsRZPnH@(l
zV@}4v1mM}|k^`=NESRG3--tA!fD?AuL%#}h+J{oBy+KuX=bg&42=l;wjY<l+0F(7{
zx^qGH=Zmq%Kq<t*#YGUzQ}sZTiyaGAnBZ^<rp22s4WmKj`^<p}ZIy0Oq;O)DJ*Yt(
z8vWmbr*tSF7O}YOLXj`p&uY@I&;gtf(O`$+inem+EGsP6fOC{U(*8s|ILacLIVSv;
zIMl<Gt-H~UIa>{9Qwln9w+Xg4PXB8Gu-Go&HcE0bKzMr3m&GNaeT^Q8YEFy*#qFp<
zgoiTZO(3m#&sCDph^uv7G?Df)HelAM^FX6OR}4j1)&1bQl(Nd&*hZA59Wx>AZuNG5
zKVi$6<s0RS4q&>bSTcIR+H`AS)T|jbs?b+Ewiwmc8DCnrcQ&L|Hd?QY5?Oci_v*%-
z%-dFSr+M*`ga62E5~lG$-nHy_OWMh~ClmasiW0V$mUJW<qnJkIrkk+Ft8J-B&bZs>
z4Ny@rencSS1FoB*hVWUPRsyRsY&s<aK~-=lS6Bj9r&W`+d*|hJ;N}7XJHMONeZ6TA
zG1YCXpOxK(aQq5uT^;}VezZRg!om-1SY)QwfftmXG-sG`<AF@?zTG6W9s};xOVW80
zjpDiMU7!@l@=h%C-HKJnP{(zU#9@Ig!`xhLow}P0A+s;_o#S&m2O*gA^FkX3Tq>sz
zFMOxP9h)3iJ=FBXJf|!Yixvju=Mh?<yO+UdJUDt{0oJ1L{?dhk^l<uJnajk7*D%<*
zoXMDx9PF=jv^K59rpJ1$5Ia&B3P(7|Ksc<fHqgMs$aR@#xefS}oECeN6KSCUkMjk@
z9bxs_>#3a%KO=7w_!A6a-0-d>J5su^qtsl=?13k$<-mY#=>SaP$6FTigo%H<3zS?X
z{$9XxU~fgPFTO=1B3yxPfhWEg4t|U=@CI+ZX}E6m@T(wIRWU~lUrJfW2_^1{acUjl
z_NI~-8f>AQ)d_tve`4f~fY}<5Q~}XiSs9oMh!G?m{<PyWOnaTu!NqW@$SW)M2}x<5
z7AaY{BAyu3PGwYz#Bn?^ob30obo*KK<DG@mfgL>=0CrbB&qONi+9|s07cM`6iT1WF
zP_G-HJvbe=;&|Fjp}!N;zAxUa9GSw&Lrw<f7@0O#k&kJk2u%(|p2Nl(PXD2Bor{TO
zmOd4Gs>sjm>V)Kcl8MYQVq%CLlNkQB539hGa}|f0Ld!xYPxRycs#mesPg>-%D$@X&
zdXjz<C0d!sBdSe^<BcLPZFz9No`F9erVUv7syUsm?yDi;)=ozQNcW3BLAjieH^P`I
zSZ1g39lX4@ev6q2DO3#VuWi8$30ZHkgVU+yCU1nN5P-YmgHtU2%R~>QQGwgWWac<B
ziSQfjQ^mR{_Df<$BtsTXg9LsSZF}u@clm)LVSK<QyD!oBek70SRCA($q_6}^q}%76
zXGoa4pzvakpetE^c!K62OK>6d$d3eMK?o(KKs=35b!3hV>Vc|ZKClZ+BI&|X)LAiQ
z#a*q&d)aTX%i;Dh%xXlXO&z8~IH)1iKn0a;jqW6=_8pp643D!^OJgXJL_}j6_$AIp
zq8eI;az^sc2fDl8@8$`WOXB9MC>0V4v`TNmH4|0f)o!4hqIf@Jf@f6L3Ps`IXva?-
zju4tel_{OMKkeIj%h%UTLnJ~EGic53&2u$0I;JKX(2`?86^f-x*iS}4^q9Xt6Nj0#
z^fvHcK)=QFrI2X<l{}IMq3+Od!NC;EV$&{016ouQ1VcAD6c6(27knW{C4fviB}izy
zmoj7TYNGM}>*BYy(6j$Pq%!|DQCv@7)5CZh81QO+d+JPVh+KB}e49ubk%d_C-YF)G
z20!<uY@DAXVsV&+2{_ShSp>(Z!xrt4twxNNXp&&JB-(LR=KJY5pu(Q=g<qGpiOrd3
z?Ji%eX0L&MKdU?t1X^~ot|tIv?Z3!Pe!vqW3*9ygC7*XRjZcid#k5dNf2QPEdd>(a
zZXMwi2T&bosq2L;?qPYLy<(dC_gZz=U<$N3!OYrr6X7SmXo1(jjDdwQCRz#WWXT7N
z>1~{HdeRKndYg;gDBx!k$)NL(9vikCq?~>%=pc&G#2*<pA=wQKqpOh3mdMwDpQr(+
zXtiHk9b=%$$*BU%pZ@$h6DcrWF12l(GPhxg@&a_oG~Ja_+x>75{Pgvy6%_@?J}I=<
zBl7fHL1D4EaR$h#u-f2l2+L(;hZR6J3puUYFt$1#Iq3XpgO}+4_Yc*E$T5pDq(U!y
zbZ~8X7K1PRO!rOFM03~?8SLqy@h#5ERpXlS@Nf`+49c@xWU=Gnjw|d`R;2-we@uRJ
zmn}4(_GZJoK%eRhc<cz^rB@&w@OOeL*ak>c(42abS=f{n*ez2;|Lu_FfEMTR2X|O=
z2U|D5UaayWBo}8R2AwKtCvp^9Wo8lZW}L9N+~<^aGnGk?OLWZJHV!&qm)a#k0o9rW
zS^6>=jWaDT{PcORafKmmohpl=R=B*d++jS{a{P{*qoKoROUij^?VDeK#}!PW7`hIQ
z;etDRe=QN~SBTeqV=oEe>ic0AMPNSAQJf+(-WaQF;uQ)8PKw$}aYh^Mz`ZGCnf3o5
z&1qF2D-HOr*Hb1zLPIX|XImJVzun+Lx&bNWCFm7gU^1sV4)=Zvan=QF3N;JslgRz8
z+i!FwxwW|(;oS~G7Iocm7SzpR{SON0hG*^W9td(Lmr+7NI4vui$cDYRb2p}SzMH@R
zP=M$$kn{lJ(rGoC>5D%0G+uomD{&kGDQP~kVWW<muDyTR^;dv4j|FgZ1n=5ZM#OuF
zw^`7o>J>3ZGx+i{Q6k-KF&eQ_Dc%7-dBS2$8=HGE!}uN|E0YE$B!ea(0^@<$K~f3U
zkuO&Ae62yt7}(veI!=qqps9%ySi40N8Xh^=GFAS!2l|XFP(aEN`FdV_rKL^AE4G!w
zcFST}v;@1aT#X!}Aj)y$Z<!oP+(`1ut9HoIOMCwUnm5$*YGunFv^*eS{a!*eqN(pn
zL|P8^Y++?-eZrYVLjQDLHuJA(!om3brYyJ>wN=O2uMtY?9eyUuMM-TvyM)Qr7&*F(
z^kxAu&wJ>&M~)%~Ys0HfYP-1Ef%)=4%e%r=?lY*s=@nBKs3$KS2M<9%$JjfV;UrdY
z<w^}Y5k^Q+PyS|(&}M_6&P6?Y>q@y-XM@syMo**{YbvoL?dZ>}TdlbGahlG%$i!pN
zb&OJT*kEi^0l;qN^CXZ1t<`^O{NR_5q9hq$1ioDsS3#(S-FI*l+;)MKORA8w`wp-}
z8b0aq4n|%Fd&}y271)DRn!xW<#4FH=-i1q#*(w9c0JO!ZkXR~q^kbZE=+bQdZF<Si
z<?;TGdDpMq7nvM7;fLp|u3IDyrRyT?7}rxDuv2>fmIiBOo`Tr{$1F9CJX3vzqqr_M
zBw+jNlAEk<wgh<d7FpRnb(FGMOUxB2W=S7b2CH~+IdpDpJ$+j{#uLR&nr|qS*b6fn
zrW&5HI_9u%>QA|)+U_}zD4>uWe5pd8pXmV#nl%C|EuYoI4QguDK2uA2gB3bnUoV`@
z`{*hebqEVOz%DxzuA#nB5bY`&;`q&tK3*++pVqr3byPdKej0>?vDNw0D*lLT@((vA
zu>Z6CgxfC=;SLDZN^&+gu}Vx7Obro+NYbr5r60%6HME;Ld=b%OHs_VU8`cyvn4S$o
zyq)+g5;N;FV2w962smQc8ka*uO5X#3J6rlhOWb;552OvR2e;TrC0TjYZcw%BX;d#Q
z{*kCqK_YQM_qONgHgRR40R+FyI4`FaOGO6Bo0xd_wHzR4$hc>%Tlmp>tP&wDKGD`?
z7e5ZO4tw~s8HNh!_zbu+gqxq#X5ZUq`Bu<~-Zcl{H*75_=pLq*Y`}kU;Xf9AV4N0>
znkRcMoF3=>Jh1AmeT~J}ApDHMyM@^}bz+_miN@rC(T4#nc?$>g_5MC>m5dgfQ`G_r
zSzavA;z*}?hDsioVJmbY$#8631}=JQ05L$$zu#kT01W$h&-NC06~4Qn%jEOzv|RG2
zYaYoUlNdAQ39SSOy*Tv0mH$&!=v$yp_)e(CFMJjAuB}JcRiSu<xYD#Umz|Io``4{a
z-@yjKq=j^T+>wiesS&Mxixy)0if)hl<q9oC^^^WePe0g6yG<G?6`_DE@7oByeHN$U
zDpMX}EP9dXH&~e_BYiI!W<Jeu4X1O6>t1o-u&-O@mRl`aqpj9AQp|HPb{zT`tco29
zvVTTDB<7kXNFyo-FKgp!2+mPIPxk<k{pWR5&|oc;pV?$0KlYGNWhcJik%r!mH*Lz@
zVZh_?PtIKL&5+nqt+dFiA(dihnYgFgQ>(T|za%TDe)zMA{B0mziP*kW*^XY~I)Zfn
zz-zJwh^6cmNk((8d*(=TG~?mjkVxIs&FiWQ>v+4b7%3J2?|}k4W7#$-85ZnL;rorj
z;gZ=%|M|&h+xv+lHdo95_K-O$uN+)P7}XQ>OrSQtjxOq1mwhv`1^nwhnqEw{4XWW6
zN^IPQu;KX7K}RTuELFmb(bvD)pic&AcG^=$uoNAd?Zh|%sE!{JYM{K<DZ~LsoXF48
z(wi<%J@FKl@IKk#MH3P*<sLG`H1F@<G|wG-sRVCDvau659Ht#gk6hKy*($LCnPJ&+
znDYP`_6oVC)f}#SxAbaD?=<4%GLf;d%4K!)t47cpDs(~=9M{Ob4Mw%~TJ%c5kKk!}
z>d<!z6g<AUT+@md#WlJW%k7#K-(~KZInJk4`)D>Xq^6CcsV0?d{{|)tf<GM86%<cI
z&P6e$g1bWE>x^)5kW+8m|D%T4(WmqxFe~bK8$wAUeF<jJCQ^A<hVoF?92p;R@s*-R
zQY@uoiNXU&<m<*-DdU%Z(jJX>k_5F|_%2dJRnZ^nJ1Ae|GJ+^ZJ~rPqX#~W%iw-~U
zd`atcB_|vqw>Nq>94i>Cot#^TFup8)h(*r4E-<}bv3IMv5=O(vtYiCZttkLIgNwsz
zin4pN>n=5!-eNGS{Lk_%c?^#-U4wV!aVi8CbVPu*VoX21;E2=$UG#x1MraA*lBR8H
zkmwI0jRzH+GCb`!9w_iA?j2?)-RqA4%l1FB`vyze+qWVQ875-zZm(hqb*Fvb^DVcs
zXSM+90uCQOyC!LxS%i6YZeE4)GRZ9S*d-+0x*m50Nf!a;&9dJgR6#QGBf0dboH^2b
za_Z!M3j_tubop$EQ2c&{L|gQIeT*nWCl~VY?xO{cIoQhke>IkfepVHi8MyB16I=Du
zMrYTA73Ra5I4^G$KkIu4Z-OYOk>?Z5u4y*H0Rp`LF)P8o7H;+(*G!T^Mz`F*#EKFF
z;M8CPAr1kn49T4b7yUPtksw=_S$L;c-qG&ZV-XG)n>mR~)i+273J}_A2$x0Oed^HL
z*~h$)A={UOL(vF0S{lJg{H=j!lD^x8Q2vFR%kZp#FIukjBMHa@rF0q!WX8HryKzA5
zwBnjs<`+}{f>+FgTnj{`WwsL?W_V$k#XwI^H7fqlC`H=~POP&NM0h=1%$7*WJELsC
zK9_$9egtOn!kvb;kf;efaIt`mk;16*{N~UqETenEr^!JF7`cY7*qghx*kvc5*z0`R
zxltlLMm^v^5`JZL;+fYV;RN$Ri%L9d`tm61seTa|Of^=HT$qLO0yH}+dj6Ns2%Ebf
zxp-;@1TatkQ3(Itiwf2P<zQedPb(LZJJ*6bN$gyzTTI=?vArtd4^4@N_@#}|J#zXx
z)({H-9xh|hw$t@hQz(n)yLG}f3EWYc6Y|)@NZk+YBJ{SVv;Sa{Jk@V9-*|)3F_&+7
ziVbfsIf3MXWry?PsZvm768YvY5uEENNnj6VY-h~ZdEt2IUv{@2(1LDJc~0#U2!^K)
zdTqcwl|{5e%N5JvQ;}d3vYDX5PKDEW3lhf@UKv=Cei>CSSc&$BK0WD)NWf-NQaZ}m
z?2L!Cx6)arB<qZEX;vC6t2c&>-oY6?Lm-XY&*K&z1q^J|&T8NG7zw_yJeR$uUt)71
zjNuaV?rb%<|EweS@;zQPz}FwnDx#P%E1MN#u8>xTgc@D3>9NXlAvOy`co>g0>)<~g
z`SM!QZKP&I0*v^*H|@EDHdFKy1fK69Rj*aTbnM)crRAyBj5F}#1mY-Gi+Uxz`srL|
z*s#`BkMC$(24t4BQ!R*#;J+rCJt)x*Ajh-GI`A-(DW*Wnxzia&J)?dHGvey{CJmKo
zLFH)*h~-#tW~viK#zbMAyM^$hz@TLJ+73RiVtdaWs$&NW?zXg?-STq~mSU^-O4D4!
zj;VwL0a7Y^3{FA_fIBYh2Eck^Lx3JTm}A$_lWDB(<Jm9wZ9s|5{Q$hZ=>WnktP{d%
z7rOueJsC-;)W9#KMK<t1hE%vo9c`Ou+r3VJD8IO^nlo}4-=#(~bM~DBgiG)#Yy0SU
zb184$WJQI|t}S%z2V*iO6@;hoXjUh~z5CFlOp8FIh9;F!x|g!^f(Axk%H~hH64wHW
z(a@`$>$!J~(N0yEcKiAU_w9ZWnF0=`s3Gsh>u%e!tAtl*^#4pvKmX)7q`mjPHiMpn
zou|FCQ$1NC4lm5BgUZ?{Y~Q{!;I;DblYr6a6m|C9ij&&<3H1=Hh6jRezbmXhsN1Qa
z)Tqy$8x={(64}EVb?*0phZw`;LerJBHH9;98Yi<8R+=6)m!!pczIIv3VOUt<Xy{*j
zh8K$@I1-Mt8WUMg3HB^kUziA}a(9$tUo$6^9s-`K&FN&y?gZs`I%lGT;k-<O6pq!l
z%P9)r*o0;99bC@{9FMt$%0=*Z&!b)Zwd<r^ld|k?j2lYVs+b<PrmPF#?_9Xsvuliu
zwB4<F@;rRUQXuw?ALbv@?_y+IVn#O2N2AgGsP1Car2KM<P`|m*$;OcRP&QC18*+&S
z>k|6SS*a>U2>}`vgWGL;4K;H6Z~SpFU+1l$;*i(juWj-Ro#N!0&=97zTuEh}AfSbG
zP3afKv$n_pP;>%Rv^o&W+x_?NapJ(C{_6>Z^zps_Xx3mUV5CkT666S~$Ix!q3Q37<
zHGOdfQ-eyAE+za(X=5w4<T$WuW8R5$XV@n%e&QNHe5m#BG^t*tDZ@$8cK3k!7`~Q5
z`Hko=>6Bx<kl}Tw>gDhbm*Y`LiXMrzv`B$`f#2qn1nA3nTEvp<^^caN#EJvg*W;_O
z(Lmvv#W2A+gX1S8GF4@sIPV$JkaF6hapj>zj2+fOZ2>X{H2tZ$VD;%H7>_^o(Y1ED
zc-~VbU|_HU7Gc-MV)20l@AsOVm3Evz32nFhn53BKH<j|y+GUK4&Jc>jLC?LPx^1Pr
zm{YcQ_M=bw+W_5ix{5qG!5PD+z~?U-6*VsthW!fPouwu}>nu>WM}^_aEqnG_sFo07
z?CpgH5rCSKPkWfPizJl?0z67M`_at_i<2BN8Vmm<yj5a^_X1;aEVa&s)+$z~f*JfP
z>8TRBNquuYS}6FBZ}dh4GC}PqK=#a=a#rdsY*}TS+F}{CW_{vKV`Y^%o=c76w)t6`
z{c7M^)>m1=vsSA9uc2z2X+icHWFPLy@0Ds3gLw+`c20Hmmsvyggs$35V81b@4&&Jt
zX{iCodZ_TFJOGl8Z%S4STcLICvb)?RCPVg<y0>k|7|T=A@p^R`mV37u=m9Gju}6zo
z=po3vt9Wp3WoRO|L=qH5JCQ|H8<deqYkGf?Wb{iSTigVfAZD>i431+Nzf&Nz=pamd
zbuAyRRJX152D0FOYD6OC=lcX4z^lYmAVNKuBD52oZn@s@jQI6pf&IMUy3KPJfC=BY
z<#XHMlN%+~)7X~_Y5bCY(cdnSI^17<@O@ubt}55k{>8frnKD)KY5qBeF{kU`S*2q~
z(_Wo0Hoybd9kpL|s!8!@Z5-u=NDTwCTzL+!4-}Q)gTl5z6IopqvC0e6Fr|V9+$cn|
zz9e$y=-;eakhM=HB@CuaEW{e1$o{(kmS3<Q)U|2;6#|beJX&pr?@m&1Ii<`C&9ytG
zoF{RH!u>oy#(xZ_8;^LotINm)nocg2H!=DkcZn$&&t56%t~>MILOV}TJDcdQTycMh
zFy)XK9YL_Wmgi_d_Tl|uT;ei$;^od6Su>R#dD>>Wt_1fE7#c~Q!>Gt7>Mo_UDP%p2
zAU1J|kD>D|TMOwxPWn$rE%};hM5tEaKf#X`CHU?ts0=QGq-;@#PbfP|=ml%M<Ki<4
za}+9`%qXIIi-hPPQyLq0dknuxYN`5~=I#RU1S9~saKWfWX_}Uf05lEZxRND3Lo8t4
zXBU5iql3!yl^K}$_A?BAhtj|Fu6r6EVb7dr+Oe7rPo6ly^gDR<0y8Kg$h{m_kJC#l
z&(R!o2#E2`dJSf#ACBu6SM`PvK_bSm@q7Kehrd^enWju*^U<s+i-g|Xq;)Occ>a}X
zhKiVjO^2Z2ko#^^c?LBDjD+DkdNe;|0*b@ab;x8ce%GVKFY*McvQuCxyP%|qL)@Pf
zkQwV$g|7E<{wG_-OMq!6hn^SpHb`@p>=fH_T=L~s<KWqOZcHUj=m&u3Hqzbo-L>R*
zfG&n%a=>6<*g0c9cyJcT+;1#&y=3H8Xf-{s7|*zo-?__E?~MqjN*-lI>nT1~8QUl~
z53)+oRs&w;vPl(nnaolV94pP@Dozk^5uzE6++>UuJMlzTqIpj}Ijoyt*&wwZ2n_(T
z(c?<s!NbdV*_nAo<y7aY_QM;kwB^gsQ7tf@mfr*PzU{8k)Jet}7Gj(3dpPPfjpuQf
zPSd%9X|q4*2OaBlWAE1OMEO>OEV+V$>vgsdwL?)@$tq+5HRRi`1Q%|fte$1c7lZ~Q
zNWkeO{%0IOVjZs^?I{H>bX;`n?_!SVLub6ZGf+0mac6)JQ@!~ZWNrlhI*z%z6I(pX
zZ!(SKTGqsTpZ@4_SQ2XK2@L)Qb$)El-2dU1pNY^t?IZ24<GI+y_&`f|klWIrr4^X*
z%2{D%%DLlw*~ZZq_?lVwj<DZxO->^z-11I9&){kNEwUSE18|Fqbw3SvXPVm0r2MR-
zjN0b)F^*qkHbjlP&_bKJu<d}segQb$>25P0H@Hl-UbYV4^J3A+pi-oF6IV|Zui-})
z5R>?is(f`N$LW>8a*G(jIPx{e<q(1Ugym|{T_p5a1xnyej1PbXsi0E_hm$dYJ^ed(
zhu!H}zH&xil6aVV1Q2EAm0cwcj|Pt1m0dg*GC)e2*fRak2?PDNYSa5fmO2hk@Q3U?
zq+Vq2Gwt}tT8#%h2)AZ_y7k&w$b*$#<|5TgGqDIBvX%__91J(oW4R@w^?Hoi_B<@+
z_MwuJE8%6NYY7$wt125FpxX%3;j(z;8n;IzHZsfk=3Y7bjxNAc*yl&_Ab#s|{`A-?
z#Nz*Bb_o`RIL%Y=t$N22qgv|ZuKU94!m3a>Vq3;E1(JI4;zX}c!1vW_n+gd}ViHT4
zl)8*mp!8bJn};P-rKe*DkT=q*DXy|G&jGJDAu@Av8V<R~&2}K)<2+GPm}N7-;s`H{
zb1a&tT?LqkI$Qd&QX!45JoGy^I)*QRAK>p(Qo3*&n~C*Il}!a0%X>UiOE%wsox1mE
zf3FAYIL2^!3<AFf1=;Gzzb>TQymN%OD3@^u(FEHjy&3Wtn+x`P%aGL;W+|eeq<ezC
z5-aUExIanCik0q{pay_SXlg7$P30ntg;Ql5p^k=1^?s5i2kQCi`Vs_byYr-);9Vjq
z%#yxrKF?1aldLI#o5u-5#%FngXj_y^aYl=>T`~b(O*F9q%PSC%xZw!?m^E>pIOys2
zo-IB>&mdTQ+uD><2dk{~u6i+h@^315$CdnC{{|Ae2oT+ZMl>fr;@@ls3qf;OkKo{x
z_2)*f#reAh={3S6WE%Zy=5*kyq6EXiG^2m9)~v3hW{|_kKTFi<^tXgZ4qPKKIbFpg
z@W&<8&mZ@Vsoh%P<$wQ2^^bWoS;PYUYdW&vkOA_CxYmXFGdMBJ9Q262(3W!5$S(v@
z9C%(mW9*wtxTdM$JUOT+gNfS4&wzwwg3>!}{3`RKSDgZo-a8<X@`X1hr1cZ#D;)YG
zgQrEY5v{w2i$1OvBOPb-Fy2W6s3C}&ZiPP$;Ta{KPx=~oFpp#lastS_Q!GptAE7%$
zTRKkuzTFE_AtA_!*ZXf?#h9^h6%YX{Vth_LB&IUirAaPA7tbxQ(&TJ?BP$<+uz)UT
z;PU(XDcQ86BbTA}@DvgvK}I~SGYzdGMt2rz5IH#+4T;MS=%GQg`aUt|8l5+-AFw01
z!Du%4Le`U_JHWm;b<OQ_s{kkG$@n;CdruUWATrB;q=RJsA11^7T+7ZsxW9;3>E5CF
z8(+!B(BLjZ1eC5XUIe5}NLr5N0bu-jl~j2vomI+KC=C|*c)654r=E?tMz{hFdu^ME
zqp(5`c{oehfQ(gwYd6P4CdKVsuW=vMFH-8;_HWzhjjAgdbYHEl5E~`s`{ZkXG&ctT
zdMhihrmT~7{Cb$O*-+Xw+Lb2;;>I8RMWx@m&x`eIY}m7%S`&PeO`Z(U^TqAPKnDpA
zeqUP)bB+VAq)cMt`4@YD+j!}RGh8buPa}*UcWW9PODN;O-_hd%iN-0*{I$U_iCgS6
zWSm;1C5PJLuu`52M5AYrR-sJ!#fdq{sRwEAf@G}6Ma^1&vrz{V6q`ICSx#ioPkxaq
z<rL;1=pe2Cs^#S~Z>)Ri=e@rA-?B#>{L~;k;N!prwV_&IXYP*s^oNP!fEfkZRIeWN
zIydaxyA%u1MA1z<_u41M&4^tL*PT2Y`L)M?2&M!x*kr16s~}SXt+MjbxW)!LE>DyW
zCddC9NRWDxxV8rw>Rjn$lZWOW;U(>S3`|u{6$EJ6M@i8q0#h72#w;pNREO*tdPK{w
z2HYu_cJ#lsHEl*Vt(KC(7(G^~VuuxTqJFmw84rl3@?Pp<LFRY#UAP}75cFpO8o^Wm
zGSz`S^zuq!)VthHMJzAq!dSXq5-Nmg4P@F9MsHpJvsWdA&gDgqe^g&T*V2J~%|LP@
z>ME8pnWCyQzU%}$BPAF}C+rK1)q7mJOvf*_r_?>Na_Rr<mLXraQcxz8!1SKiX8V)8
zJna$?s93f)Vr`M6%Gz&E&Q^YsjA?Wrf8C1Tu@n%4PL}M2XzJ|cw`v`==&+zwT+i;Z
z?$KS%UNbSMq(XKGF_mI8wPSpz|Buzbe?O^yjb|IVmkx}WN(@BIeNf^O^%P>X$%Uaq
z+Q<}?>8KI&BoiV5O_hXmhN7lH2zb8XJwCfRn*|c1DH{JK5$+p8!IXm9<j?845M+W#
zwfX>s8l6^gD?G&4c^f+;3qOzhljz&sWq5_QIz~KVt-6yjCU0%+3d{PG6>Y*Fo4+c0
z&k&a!Es;kNUGq5T1RwD<$$XXjJev2K-X@c0LOJ9kEJNM@(5$`=^q3)&UKE%0CmmYI
zL?ISJH#(ChU5`qG#$W3j8#VFpe1k!0I_`B?x|3{p4F)Q+#nVy(5{+SCOl6wc*!ol8
zbRz>k)EF;PrZKZC`_0gG<<+^Tu-^A^H<nz&hmY8pkm~gf$60TQBlS5<Sf8);&6>qx
zX~(CKDA9Qy`^>Zo3*)M`b7Fqo(8%B)-b1isl?@8h6lD!#*pm26geDlZk(FOAJiOsS
zj=5+y2kegBujl|C!cLH2vjGLa&j69b%AWQOJXmQj!T>H=`96p4E6A_9on@|D`=}XK
zFSs#3VV0+iG0zH89%LxL+x~#BWf?P^;4P#M%@vWL(>R4FGB%E83X<<+5*S<Q!}9ra
z9>V71pHmB@Q4Z5`EcnHup}6x`b+b3Db`vKuBiE_Efpnz8B?g`Q<&*s(RW?WYZxNUH
z#)q<aHN~*XYu{MW<#G%JVbu~~)~>CM^46hFaFL)EYEV-gyZpQZ<+nD*c(Auxz^r3~
zLh*z;G9W`{S9#32nya_q!3;YCET9N0WuTFl5%R356dIU?vvwp17wL2{VjEdIPLo}H
z?h@?|c5J+FKADx4;5|x(=-dbXXNKu%w|l~ElV~Eq8F<a|^w_knLA<-HH2Kyw(l4tR
z_f@+#jP~!`-?oqGzdO#ON{38RpPh-JWkX&Z=Gl~bJ5}KR-`EN1sl{=E%=zB4pQblg
zjw+xkH0DMY)x+|E!WkI_^;J`r8ZRgONHsDoC`uZ6_G#!A-iVFDU11;`Br?9m0<8t~
z4`6mWrwj(g<9f0drz8{isQ}blmYlQ8tgFI*`$NB7A^E_)k#<m%`nR+tl?<|P(B_|d
zpu>76mhxu77=$&GOl%YdCRMnQSL<n;KiGoczU`a^xY}i&NOW(4hWonYH&2Fi7%^Rj
ziM<!`tay#i$77R$=gtY?43J&dsI&3$CIRAvk|#%s{B2?Dd(@+~tk=lN4KXd<YH@|<
ztn9OfGs=(hBLm@C^PG6M+C3nkjYg*oS_!VAbK9#*8ORTY3^Uy<kCeVH437FxEND>i
z@&uFmV=!L{hFs?LKx&2J)X3$I(j{!EO4u2DGHn$iZt%Q(w#8q2IfIDJlDwW7F6Zw(
z9eg-DTvp7#IVxN0?3Fd`3@@h11b{(MNzpVK2fw2onK*$+h<SK_iaNr3uT8_j@jQ8B
ztq%I;TJ0!R_p8Rp+&L!J*f&nFN_jhQ2U5E=qw+;h#t9P|@=qk~u&wi4{C~jDu^H!{
zGN#P}JCa~OI(AmJEpZ~5{~0mUu@o;%lRbL5t%f%Wlv_b@%2Uk~r5?6vNv$|nZA=>d
zTZWnW?Q{L<{)2PZX`k;z{K22c7+C=#*DB<113KY0yY`(|AysY%NEb6$`9D#-4h}-3
zvQ1Rj(-@gJ^&CCEcWHCVh#um;!|~pb!#%$q%?8YSayT+rHXT3w@Hf6$kpn$3f3xS5
zFNw9!CR0?fobPFc+PH|;yRSpgj%3ame{Yz7Tum=o5{5Hhs<O!Cf(w24|ILM{<8#id
zAuQ_*=gMnkvk%S3Yc!7sWfTCElA!`<98#Rgo1W^)%YMDGtAeVBE<m_8NRHK0ng%Lw
zOMEzcKHq2g6=?n($ao8IGA#2G0-NoXKi&8j8g%YLI83Uxg+SL5QY$8LqJ2!mVTD0;
zH$mW39<~smfW?d9JgvP!RPmY3`BXaf5e)I;sNUC6b^X|>V^ze{|ETJ+AVaE2x-?ZJ
zO$mQwFVfv>-LZSi{j4Fi783U9hE7uFr&mQ}OW3Z$HVn;!@|xNe3wECXEj$(Kz#^hl
z$<W@nhG>8MAY_SiijKt})Kg^JUV*b7#)aj9AAl3H9eiIRCaYv_*7zOJJ;(Jz?A=)p
zHCr?7-h^^!ObufJ5BRip{hG+l7#ZUQ3T#Z&caw<ZM6eyedrWR<r4^QA3H6Q;OX^9e
z=(`c=UMMw4@Od;ntbs6LI=*V0b^OnoJtv)WY?+cN@ws%0WO!V*E@Pk%V4~#7`+)DY
zxHns^-6X7XKKMeh*6auxlr+`vy0MZT@W9G#l4<l;$johSAuQku5MZ>B(+=)lTG)H^
zz9Z7YFO(&qjJ?13HqnAZzUZY5CiFLi1EQwAucEjPFxgcs&lS{-Ni}k5z6R|r$j4n$
ztI4w}@mh-3i@f_Ak1?|VhaT$$vJ>8$2Oi<*E6@+TcGQ<w^Oow`<*AH&CN_xgJK_0l
ze8`-1&U{qcFL?N>9Oy#JhM^QJVV}tMn!3g1n>tMs=Tbs#Y>nyuK%T2+lAoNZ7^wnb
zDTn?J=E8Bl`@rHnS!@+Qc%iN7@N>M@mf#PQ3qNN{pIWC$Yclt*D~q<^H_d|v^c7Je
z|FAZ^@n7SH?}0g#t)qjJXP0e+sRC3o3VwTd8D@e>1XE4@qI#VqI6|bbrR_E}3&lKH
zHE0qQ)vIYC_lV`{JV{q*nRCIDICB>I@>aEqm8m>jaLZT-H45Ze@Az|#3S0Xe3PzOw
zT06Ymzo#^2bHF0L@|?K25FY<CrtD6IPVPP%+4`UEM2pbF`&_Za^MW@w=}{Ct>C-~Q
zoutN(!fksJYcN^u=|Rms5IfeZMDfplV}xm$^#$`8b|0CnhNz#?{b$3XIC@~mP7_Q`
zqZ&&_np72TW|VGaV5pri5Lj~R_KS;$*$T9Tp6tVBy(`#s6LwQ1%036zc$aM@>tj9G
zWh~Rwq4+97Q)1`{r0<4uAaXm-m}o_`TO-wp#0s{Y3!-u<PvjNHBPBFJ>_WSY2@*<R
z<=uJARs!t~Q$N4{`MLE>tXB4by|Eyx1MA*%OVf8e2NVtIJnO|U%vGRH)$I+eU3_!M
z&)^5Wmr+OXewYx_Jk?fjdaD78V7KrhqZsXjI`_74ycs%N-IWh0E;Nv4+JsRfPU9G4
zl#vaC)<FAm8QMZS2F6a~q$)xTs-4pgvF7PJwQG!$!3;`MsRo?2hTzQWb7W#1&oQyk
z_A^o~qqaKkyM9~_xPjQ(EikUsFfphs@-tsTYGK#N@zBZN)D{zG1AV+0>QPj9Y%9=I
zsgq#v6V<D}9NI6{=#h-oVe8v-Llq-2H3-el>)EIbY241Bk^Lfvqe{}vms-)usMPe!
z4&VlA%x9im+OxLsp3Ng3sS}dx&qtf#O*E*T=;EdAmcW~Mj9ffZ4;;sNO-4i*borbt
z(3i53BbwB6quj80A@fJ&anQU-;qC<Qf=@pW#_min2lJS36-c-{fMfQ8-=~H83aY&2
zJGqj3{nq04u=#^TihD~}Di-YVlP^W+2h{Gg2+#fuqne(hf&-7aVX{x|{|Od2(ONo%
zFg#^?Qv>~7R>eZJ6f5`jsKG#d97>KAs3-Ni(jFTQlYqJrsD$Hx;yjw2*#PS5LOD<z
znj+3qdOme~NIsVBdkbt4tQoXWj9dO_CF)%<f`LG8Z&<novf&b#=C9-j9;Eu36Xu7I
zlRh<Eh+5&fvZHh~$0G}PEL;PN_DG5KNu!4Aq16c)o;<XoU0w<A<6A@Rq5y3U$Qy<D
zM0cK`(lt|06eb;Ij=?b{b}iTKJ1$e&hMA93(69Za;+-O9Uh=TkRykXXuE=u3`h&dq
zSl=ypVrZ*mXDhxQCVnxiY8!AV?6eOfaIJIZ`4PNX82fvh833vKI3ObatRyb!CN?iP
z%sl8kY!0|lzBr{H590CoC4zVo22h}jwJ66P6Osse$2MHV#ZKIn=uc4m#t~0Uso-G7
z$VH>k8l}TVZn21b*$ZmlQyr(*wi;8Rzs84f2liyW>2u+<-a-NGflfFW?B`#PDz>F*
zuZxO)gx8;L>8$J>18nT=St%qt_`kXs9`Esi)p{^Kxm;C1nSlBVSNF~H__5G0bTz{R
zlyNi$Ela?Y+cB1~yK*?yv!gx&Qc7BBzg&3deR=b}_vn^^{{xdX;k$yiju#rqT|_1U
zF9=Lt5@Ytwdp2Nw+K~eJ%q)k+UCc`#Z7~%=fzmT+gN+2MKCAUBgU>1ZQKZ21*GzKA
z@?SlV+6qpSG7_{jW;0!G*9@ZIDCA5++Kdnwo0_iWRP>HzFC3%7R7fmK#}`l4HB1uz
zbgd?x-u4#<?5~y0XRZ>-rM5)b#Cg3yAsocHfr7iFCuw>huI5&^P5=quz-0RFv}D|F
zg=)yEQ<M02ZU+PSM%vv@V_?J*#v!H7@HSDUo|i$<;)+8lv?Vfl7{sx+RP+iI&9L=`
zx7hae7lMgg8T?Yj)&~@Cek(A=o53*Ay7ib*ij{^Ies{O$Q&Hec=di7NAco>8%zn)#
zv-iFNgd0+gI&qJ<b4~|rqYpWhb2a!jg6w_r0alKvW+6yGR6=lG^o>aL;?^_-^5XS;
z^3dgo^zC*AWOcb~9m<v4P<piaG<0suc3>czB(Z=C;+}dz^j*ZJ`G4e<f5*4D^VI0c
zQ!fZFQlAwd@|_Ym2vz-I9h!+mxq2qsL#cnW<N5l#8~O)SbRuNbcY?35=XnCM0pD-<
z=DIU@h#hce_&-Fd7TnHM^Hemag{E2zA%p=BCjU}+e*i?{#jGXi-%1&oB=6WrtI^?|
zGv;vh!~2Y$d}Jn?ceHZ<>Lz4~+(zZ-Fe4&^(Uj0O26$Z=>@;mEPx3HO?;h_*>c{b^
z7%EZS#cht6nX8JqA``nlqBxR}8o3%Eg!dZ~aG{%t)?lTErTuXU#}4Eh4U>q?5&1O9
zV~Qe$;sNbW&?m*z+RK6bSN}v19=}yt@mMm4X#ZY09iHBIj%XTmN{|k>^+iG?-KK7Q
zwba9k!0(^XyVXMNYYHuSuU{u-R%7!XginSpt<N(*)Vf3E3|ZZN1F2_1<F^tsqjpEn
zyFSxyFV5Tj7?`*Bmu}?)qKExroMfJ6vTn>~h7pdeX^X_lv+|3<gm%0u&4}gW$-HI!
zK*$yEJ%sUb7U+*e)$STOunL<M3a6ZjaB26?S8bB0-J~aoF&}6{1(#RhYo|uc%mCL8
zN9^#{ww|QW0!bcP{_YV4uv9ui!Y6XO&b=-D>$snj=LGTSGNhyTPK_HP@+3q*lDb*U
zCEGn2Eix1iOlm0^2z>rvA11p`gHwaGcw6MZz%THI6<-V*grwc&Q?Cgdx)(A!DW-1x
zQzbMzFymY08OcV3_rbD<B2&qD>k}!MsCFG#@x!i-Y~SNIn4{b{M8}72D51@twVgPG
z6{5bZOs7%QarWq=+*w{XSO1;C1A&yOAkD|DW?TA!R5Zh(FZC~0P^;7SvxU3^6o{N-
zJEcHaBe<6?VOD3GrrA(&bYlHgB<xLpbw2m)A0I{2ogdRjE_l5;%yvp&;l}(5K>D^6
z{i_;Bm$@v?Jc*gTQOf3AZb-Ob#w|eNnq}t@J|J8wu`=oP_7@9vv=I!a-6L6V`rm0u
z{<yejR6Hk1p$73ou(_%lI{jaGV0Y^+1izB@Cdpsqsg3;Q5q88Iv9uIC{1K4$I5wJC
zK8{#?Y9q8oT}&x~AdoZ#(-Mj<;)fDR;YZgt$k?96mXTPV!N*Xa1DiI@ba8$Aq%OAI
zZK|{VL9sL8i-woQ*N@!Ww9kQLk(&AHGfpRES6oi};*Oflgm|#_q`Be6Afczj2Zdd=
z_3s|8O4qt)g|>k*zqt#X4?$+Vre}@8TsL<7d_v8a{1DZN-5a<Wo4l;IvUK?>SKHiT
zr(yg7f(ONhxsaLlam5_g9+&P@&!?yQ1F4Vq^MKHdB^A(A0PKCDU+mrLX8$~b1DNmd
z@a!YICEG|!R->7f(LYw&dSifmuZ=-o0+h-&dA@UGA3L;U@#0RW000N!9k8v2E{VL{
zGs)nr7(gprhm(0H|5PWAwV4_r_q9x>2&iqo75$@_0t?9q1wsot+T2R}?VE`-{#d#F
zmt`1cYPFBzV+(R@;^8)Dghb}3?TP-NxL}M;pS)xVlL@SH0#V(SwzlR6_~NI75a-l<
zTC!EyjUPre87T&$-MiT%fYIF<;tE=hOIx>GDyv*b8ORPXB0k{^8$oD4`^OOTRkk#5
zkK$w#Cgfo2MKEAFidg)I4la#0_e*JWG9`fuD*P4KQ=5E<G(k%OA|8?n6d7V}>9Z-T
zy$Us)`X!-bgj*vEA67zeT@_lwzli5*K3@aT%ui7&cp)vBr?wD)u^g6H?h4i8hMySL
z;gv@3gS&Q$Ykl62@Uv!=G<Gv-j2<%2bHcv-rMk_?3Osu;fZJd`eD!(s#P)P(HHYOt
zDx9^Iwz{*34HdHuOw*xr<4L}5l=;Nkq@ZC$yTJ51x&9Q-gTqJc#%9oGPjYov=6XP#
zVmbGShq?-+pjxOzd78@ans3Ye&3)2_H2F#e9oB6WAlyw6V%n1AA$VKMy)F-8j9=tn
z3v4>Y20VS0ApM4kJ?6gAL*#I{&Sr+O)tY3kO;vcvVm(@>rTBc$jM<*2evU4gPu<^C
z68h&X;cYFq;GfqnUdxc8^%+yu9@{$V5(g?%pp-YhQHFmO-?Dul&fFj|w8GdId&FF2
z#k6|g7?3Y$A<uU`g^tKs+U4O;kMZq)4b(b)6uY%&J&L~^O`M>$HK?kuzPh7+vOk6K
z$V{wsQNXX43wZF|@0IjiFdXMc0T(QJPk8mQo({Ck?3}pLrfpuj!nIH9zuVQa(zX**
zw_U4lXZqLgL-!fipd|m5(;UC=J7`#yR!s92$g{E*`onmgi9WP`ANsmx=cf26xU?AN
zs!nW0%}%9{xLu<<D~let4i%Sj6Niqx=W+%W>!07{HXuJgKp5$fs)nVH8#7g%z65T3
zDVbjg8~X66xsU~h%<(*68qmF}t`G$ChWuN2UT1kr!8na=`_Uo|x0A(cBgErYm|rs6
zT3X{CdX(XjlwdqrX4GIbV4C>S7@g#*<a)0;Kv&Xa4Y6}?l+!HFOs)@ONsS}(PMzwr
z8#b}Q&Oc<BX_k&$3ms9!?RB>;D@DAR%j;}-BF3Yq(N5?S?|;VFJiJeD4tXoIIo<M@
zx#VTE_>KW9MI50q7+xHsz@MusZ26He=0it*<@_N_XLn|ekou%>_qK^^ODR!1(Q4{*
zuXrOe&a=SzO`e4)*QVGuIvR>W0py=s00=q#Os%*FZHurPHH+7ths5GQwjI7BwA5X3
zU8vc-$J$B4Rp3xM`uIUohw%7v*J28fNU_T;bq#u>rFuLj@Gy~7?Q?Gv2+{WwJ*Jk(
zftc<rKlG$m+aqU=BpC+FJ2q)$S7D$Did3r3Qi3b5Gzw0ua1YAQ-us{Yf$yWWk+1Fv
zTKT2;Mo#+el6`D<0^^$8l%WOym_NN7dk_hxp?Tl$oUQ^n!EGLS%#ZGsliXhgB~BVT
zCr{2Tk9Z%YcpKSK1pur|Q|RIvIm~C2QU>K!8sjo`_Mm4Zc2&<Jc7dEtt95(_D-3QB
z%UN(pZ@1B#6|6_6`VXg@eXyw<M%anW(qkqOKX`tuxO1qex`#ftB1tr}t7OD?3c(al
zr4xy-M(Y<P=`PTreCgJ(q;wh1Vy%rT{<U9^2RJIN*|I8C9)%5ZX-ty@7BfPs_Ai6)
ziQ`ayAAsVikR=t9Y6p>_a6?B>jkT?%3>EOQ<gilfXXpM6G~4lQu+@h5$Ls)Euz-7b
zUdQm#P1nY%43}pb>zRxmTJ~J_edbaNRpJA{tAPh$=_NCzv#1z$Dde~I8k={YJ+hXF
zrZJ-4PpH7<%tS58w$S=ut6T~+d<C+1CP>^{KQpZHT+Cit(;R*HmofSCI2re#G{#Vz
zs+L@lZz%++=*!LV_7)}!Tc=`Cb0>!*be$4C&ru}2PbiAhu6$Sk-_#F%1bDHU;L}Km
zHRi#3lq_8HP=%i~=jl|CGC{WV{W~3>+z48$SOz9;R{taOy5uGU#MDK$XL9lmS81|M
z2Ft?UH6Ls~K8;%?lh6DAdeCKhe9SU5p%V?drZgxi<-8MoD=}Xfs#<w7ttV!PQdXh1
zzv)}F=)W3!t1q)R@?Sz?-pC_RHd*<+jQF#ss^jipQQ#bc^sU9ggCJyiQzqiQzs~AQ
zj!lg32zZ3GXNWEr<})s@8T|Ml_q!8;%lCm0|H#sWOCcLCI8yje(swNQPQs<jJ=QJ=
zg>+FR<oV=}_1Cmb>B@IMseYx^3777e)X8GA;l&rSB_QUFs8;w7sWrFz(E73pC+b?>
z(H{@NOxj4w@E@)Uuix)fsaJ)Pq@XSvo|4Rp<B(SA6F6K4%S^=1-DYYa1275p7Qd*k
zbLYU6S=j=6@<qEw4dDi>UX=$8q+D7S`o6H#4S#cdM0}t)7&C*J1fA(yHM!43UR5{2
zj3j$ikowu_71r6V#JZWA8wA#%Gn12`2$P8nWY0AfI&-eUKo2m^FAC}tgIEng(*_t8
zR;hi(KCY3PP*mQYM${)p^cBjk#S-JRvCi%R49#AoA8$-{QI{=Zm~IT|H~tuO14RsG
zNIM|j+6)#s#AXQR%x(U_Qsk*qb0v4<SoB^5dRosybCB*E*>Tx-{$cH+9jD3os*Nxa
zsin6e3QH)6B;OF)*2w`W=TkJh#rCwvxScmqmop)J@mP%H?XWP=akdXz8>M@Ow@9W3
zQ~@`wlX}B@Zg@>p)k9tIsxxUmBz;PD0~tU3++1T7lSC+d?Y%jaOwL=~|MVx4!k7)&
z1IcV;zB{Yc`+1%4dl?uYF7Ybmx!{TVL}W83ti(~)3s3S6>xuo$b>}Lf^Q>%EZ!z|v
zztoT%7w#C5l`cwwDxarAYlnm+!NTVr$DSDpU>iWMJ>0t@92KiAqV^qT;~}|kX;GlE
zF2;73K+g95npG7c&?|JUZb7kJFcnZqQ98_$LHgEDSp|&ggEqWln|(X3LBW}V!?KC&
ze!6VYH%?W$>DO5MBP#{o)0ZdX6D#S}jTQ3?L+Gk@&@HPsG@Yy4G<*j>&UrT=;jHtL
zaIAhI3vXb<7;@aM=?Qx>`35$8K{iVAAfeB$z9%izEERV-7OmmvsGQ-_q6lGzAkRh-
z%$FzU>m}G=qq$oMs>P?{I&7c0&GS2a<NcRrl^kTN9-tq{j4@Nsz)=oVM+=@rd21jL
zAnz8r9EA#m%LG&_Kn!JQ<RcsW3ipW<+6?(ti!#E;$SDS498(5f4h`%i#kQc!pyBKy
z9|HQ)>x9M&Fv1w#CmB>~vO&=GAf5X4ltehBDb_huNfe;WXAtTl%$2NB#W5PPK&_=R
zurEbEuc^FveV!6URBk}+7`fpzMcj+jAY)3gv6h;zG?<5^*p>eNgvqD4wgL}hNAf9K
zhPZnl&1x)GQHYzaTR)BL%V^<FrC9|>5wZ3f<349u2*I+Ju7!5Js!TRfsup;^VnHf<
z+F-WKUvg;nnYC!Q(XM5KuFef9sh-nAy8hraQzP}rcYyRBA7kW5CqBKE2;YlJHuQB>
zj2A?;hk*lZc18WU23unHLaYcIAMZ=i4qq!TXllxFvx4}{DMC2DV}*vdyTse({L2pd
z3-QI9-JYLqe|}N4rdJFfi2&sp&c!f+qq7BPO1D?s)RqCFEexv%Z=R2GXgd|-xN+bw
zryhMJUiv+VmfXG&#UcFzVR2L`g{agJk-R?z*jxPNW7;}A_A#Tm1DEYu;E^R^xBZN=
zOx@WM=Osp9n-k1-To!55f{FV5@1Tm{T;a=)$5yCu1YXx1n=jY61%8C<(OM(;e0Wyh
zDYC$h@<~DHq^lWdjd=A5G9cJihrI8=KM--&+hGc7(PK95DpQ~fiD4mt=Exiio;t9D
zce4>-wUGm>v2=W2Bf_Nrm5pdndxB-ipy)NQn~|O{iywdSb#6n%+3GjcPGKw^CzB27
z*x;pgGAoW@;$8&mYpjyk(@>~ankq$$#i87<Y7|u#C^T&81cZXVo`ZUxo0sA~@J5Im
zl3R+Ab^Da2f?Xa9LcdoB#H_0GR=0iX(nRjXx8p}#wBOWhdVih5*myf<NBYid(1bsS
zU%U}*uTY6s!j@%>ebmZDj(Jsm$EdQ4$Sg##yJ`mh)eAH3v|-{^R3c<u8fLIOW;vGD
z$N5eIDBa`6$B}(`@VgkaP3CaRBrd}v>8r`Q1p3K+1ea6+ptm-Q)iGQE!03(+B|uXE
zmu5*GY>1=-$&JQ3{R}9NWz;9X*0T64;|=pj(gh_N*&m*&QujkjH=NC?y*nVQ-gw#_
zh53%{ClqId^KZo}?k{h~#X$c37*7$%DZIv{V$i<H5Lxjh6Vz41GQ?U+ul>a<4@+@l
zqvR6jP|6w&ztRY=xL(bl%!<rd8pkk&e}aKVeowBQP)22yY`%eSD!pJS(YptH(RWZ`
z{XFR<64bk?%nDe+LlYD)NSLg57G8zlRRs98*OKBnk}IVY@p(Eo>)A%wtEu#4BW#~`
zr!dMQKD!`G<KE%nYphZ_Gv{l1#Y*gGeX>-|5T|m37wW2nIgHW+B$tb!3p3z0Cpezj
zz3{9m3+p9!;Vl*-IKg`Y&9kvdiPi5M&;xv%+xWJ?&lh0!%Wqf$W4d57(95abb@eLH
z2didzFA~^lW1EVsfo&Tsk2gt5`R_!irK@j9^P1%&xeW(!Yo_k@y{8_FtdvbzR*=4G
z-1_5r6NBS%f61sfYyp)tTzxi|nng9Y!o73ix$|t;yHUp@HAz8bp1yBTH=)NJYl`aK
z-PI%~thXEKsK_X_-VEH+l)@Ybpd||6C2m#|x$yY`KNgc40=snBUFY#uu`q0eK6Z_K
z9^?9yjKk5_S$Qtk%+<(uBNg%~i7y)J4;Flr@Y352KbHSY|NX9I848;2)x15)8#8Rp
zPnnb#9p_d186J9W&iZSw?y=&2JHPr#5=E(ge6{sdnm#a^B#C!rp{&;3)`;EiozEqW
zw4rLACML%lG<=v(&8kYBl2!{cH|qVW><@tRo_i;vZ6)w^;WG`L0a>A?os`_VE2)%>
zl{a?)m>stmM)GArKx#Q_>A(7pn)FXWUp0}}8xtDZ0UIiXG*8|jAXxKf-Poq}j)w~o
z?OVzu!q@_YQnx2fXMpr$(cub;CAkfsu}4uI`~8_4q~U2ix^28MI#;B%_QD?Xwu5Za
zy3Kp?fm4>K@^4;24^w6jM1!HR{%7_3TryGUk{1C_m=f5d6sdoeLse%h6eD@{E$Wzf
zxUkZ%3*lCGY#Sl}d~=ApVBEtNvF=>;+`5}pzff-jF&xzTs5h%=wppf75Z!3R`b_75
z2}#BjrCf6GQ9nP_AIY^KlvaA*CgBSHt2u6>x<EpJ@oJycm5f6f+0_^O-C<*BQ~3)h
zLaJGX^#du8GMW6C!fb7mt`<0|864j}2F~DbLO$)SJUj*Z_hr30y><NILy!l`rl#~e
zD9|6tQucwAPUY`drVeW#5SMk&r(fM`mC2PJ5Aj*R_`n?Mg`8kfLLQIIP7REvie3C%
zJyu4UG?lyHsM(frO-k9eKLgudGrMhZ&P!B|U|Twf{x#YIFzn5VyRw25woaXN>bn~#
zA_jq;4vYi*InlPt>OOIn$F&-Xq5@YpQ41E^W>8+6JzqT?`&!T|xZ(GBP9X8n_aLWt
zUf2Yqxdj$)3P#N{UR^Is;GUf?J5gJrQY7)PSQtV|b3=wDTdrTMn8aqpRr23~WqbD8
zeuwUH4)0@Rq4<$+*6bFm&r8?|P=?xKK6qSy^4BjtpRHS}aanJ@#VFqj_?=&s@|8-)
zf;m=x`I3?4hXZhb$==s`laV#h*U3In=_^1%%1R^A<AQ7acJVAd&up<m(P3YpL(bW;
z{g?UROJu;PUTv~$YT(}BRUqk`uPU*OSGvUGB8;_wpzgbtd0)(`-)8pyz#amjBdl9S
z<ZmhQQfmd@UbLLfU;%PNp0i3|7UeEXVK_S~5>K_y<QxS(d_SUmrA{xX3WX>r;Bd0V
zrsvcaJqP3bJN>^9TsIm}qjPN8X%Ehc3WO`mFk*or4Y`D=2LEzk-XemHTD{tkLND`F
zvWtnhDKcK|0ocAw{N%`_`^FfC4p&BS5gTo=5qr*wmO{?rI~R`+j*eH@F!x(|BBHG+
zL3=Z{OD8h{pJhBnHdRSD*iB}3`Gl%CQp)D_-Q>z^v))a7?@~oQN8x@LE@pbAvIRp=
z4JPZk6c@1FQ4kt6AhQ7KFv-|sEgcFeU`^hRt;zp5t7f|I&MXB=X61iIn6C+LHnQuL
z1R}0%kh}9Lv`TMB4rotDporm(ms#FjxPLXa-{PcZ(-Jd3FIpV-DbZ+Fp6fpGcY)}d
zr$PX~z%T=TJRyMBtojqw+P3<<jLXD4K-NSKz8m>(CGdBQAv>X~NSyYuACj@TZ@nq#
zaAzRePWl3WfhVD8@$yR$0<ZVcxNoT9c&Px9CN1*g?a1X@t0PxSWuqbX{941zjTxgl
zz-|P3e&>y3PO0sJesL~9ecp?<?=gkW<9GyCsQyg4|1&k*1tO|ZLV*$y{Brc5@WnjY
z8xX1>0yWo<b=!@dQiBS{7F8=)S6d4{1ySfrvPNYBAZH!)-CQ<%^&<RCR5H2wpH*wT
zciX-ZVX5LcVTfr$iDCpYfEyl32l5jku+S>X-C15h7#a<A$4qC$$62k8$I2xyKj(~g
ztHwql84SmMd>l1kbdk1MI<h@A%tCY(O$8tyG0|l*X*od^8bFH|Z!(Mc@&9VpL8a&~
z3~|e@ma6iW?U_@?iNQ;It<b$Nj{x+|Wn&f78o+tS+(Zn(ZPp}XY~7yELb;zB>a(bF
zFz!kdIfs{tUkLX9P0y^hAgf^(Kj%`2pzS3BIa1XraxfziZtV=nQ3!eU{K(du=-Ih;
z_`%b4=e5*$LO5?kD&~+G5E&#L%~*0ps&ID>14qAn4V{~&GDe>|J{wq|b)_igW&#DY
zzNQDvib5jvE;GN1BH&SQ9%={#PY9x81yXBl3ODoQPI8)f$v_{YF>Xe{$J+PCI)Zrx
z{R}jY9qOp?x*5n+D^DhCCoJ`-+eT11&Rkkh#0c$pViYVo0f%$t+~vMJ+*M)xs>ogb
z>MYpPsM<gGVp&>RYB0xeP9^*ad2#cpGTc|7rPRCIuo}#UA7{ar1EjAS@Cfj#VWP=x
zdU$}v_s8(FLT3OH-~3sex|H%g6Y>gyxGYPQ#921F;<ODP$@Kr%G!>e-$HKJdaR`42
zPQ}D;tl|_Wbcib{g6W4S(u;Pi-?HB+{Al%mgkvd87dD%kT0ys32ieyvY8!STah?NR
za*#%Mk`oQkIde=G36}B4;5~M|MT=mu-rp{?1UnX01`~ibmTy)A);(lais);7tA!MC
zjCUnns+I#tyZienXP@+*fR^{wW#P2`v7XKWv!Sl}lBB1v4(rbb@329>7YnWp6P!!h
zoXZW&S#|qD4TlwZp%vZw9%Ll!^F4YB$;PfMxdAbFV!CU7@dDp97#wvDe<&X3bv$#_
zzYc@epvIrbwS7L6t7JFgQdumX<7o-)&-yVf-^gJj7DDuUO*mzyk;ZJl=3*mdsWxBD
zC@vz$f+qK)-(VcgAHcbt=u<vjdc~mgvam2~VofixS)a@tlz8lIA*-EpTTm~ID%nBu
z0Jz|Lv<m=~%ePPO{pX2sBdMfBY(vhHtz8$D?Pv^)Ql>EZ*nJp0Rh5S8n)GtY6BO`M
zijQs2+n*E^NekoW@P|InD~~GX*fh-b)gGbD3jdQ_p7FnR2fsv;PZDs#`a#buF9hD*
zzbn4flu%lsKP+r|#it6nN3@PHNn?xewkN8lU_7S8dow%$&Dbx>R*V0tTaL@wHm4gf
z!5bA;WvZm^G50GnY)m-jmC`r{8jDcD4K8|9q7I}*+3Dr6ee2Ec__^cuJ^R=~NF!W`
ztt(nP4zSB9J96Y0!=yEojoN?=YxY)P_5*6}D7BLUIgjCG(e*A9WkettoD>c{5at1K
zlDwnQhmBIAO{r`fW&8F4n!Dfu(u8$BDM9UU@uTIM=?c|GYz2#~o{KgHm<CT4m;nuP
zGt~w%%F9Mkl|W`KBx-ERjCooQUF6%X^HlEH%-19T=C76wQoeV>`nmvtC+$Y1ut4N^
z!#2`8a%1p6G{lFi<M9r>3vYjduI~u2XV>E^83;Dyp&bvDl$`duxmAa9uFYX47BEa#
z2+yg+W>n=jb;TZxwhgdfF)f3H<fu~=?ZW=8z^k`fEW&g>vX-_z&WI_S2jaVZ;z^Bo
z(8Iobpt@+nkLW%BT^4Hft%EL26UK7n^wc@gVimr^D3x-_HqX!;;@~xY#M^Bg!^K<Y
z)~%W?d0Qe{;x_MT9vvcO=jiiZPS^aUX0}vPv1W(|Yb}Zxf^thg{<OmXF6iVlkQ>KP
zeu0PD)(dN`?F!~^(nPkN`a%zmmFDBo&~Xp`^{fCsK*7IzDobacA$M_XLjnffKSz{N
zu4%5A4unT4^|TqkZLNLhhzUxGf{ISj>~vE7F6-DV&}ZTUH`jBLx4RkxE=|HhD3>la
z4=C}hu5@w_S)k~3sZ24?q}}~s-bxGkWZD(QATm=<a2U?1@Zh_`03`z}OjMv&XPjDb
z|1+JSR$()_uMHbk-vz(a%c5tFBy}9vJb4cS;Y#V7Lm6@3vkG)F(%+$iz{*Kb4z~on
z#2y&3{D#cd%w_Y8FtDQNfm5zh#pU44rECaFsVkDI9Uy|oIVj&QEdY2~@*7)HwW1*A
znn0IFtC`=UIGSQ!Xopj6RT-!IuK|^q9A0M?k%FYS5&dprcKoO#v{d8a%`+yjjT$kM
z9!dh>PP*J9YO=GQ3-qnu^8Vt&%f@c2A=t@M0G913@aWf=kl4h_1B}#mPXxzDSrQJu
zsphX!HEng!Sn1Ys0ewwnX%aBY{R`*HMPG|#OHA6S_R-2($_#d>dw0spu|R1`TTf!<
z^|}=g)H4~)m)g4CwjVMg<G6tlEP)xrqDK5flDT1ckbp*O)o@2G#wpEh#=>rHYr6Hb
zF7)Wq;bT{+6d==SkxTF$byiej+Pf_=_cXWWOy&Ja!j_CR<KqN8n`3je8bif`3u-g&
z_TCBn`i9rF`z!d@F#<KG+GB@exo2J}4%#DL#msk*#nrpdWO4YLNGu?-kdBTNuA<tk
zt}a#+BQJphBM%AI*fw?8f#<5vRIFR5?*{uAA@vu&Ooy0R47C=!Ue1|-C*DR;B05O~
z%{~vXM%jh2_E-}Df2PHK$~?j~;Ux3R^u0ESi0<RLHrEx}H>J`XpVs7H3h2ctOGZ>s
z&mgklZ0bCQYWinm7}Js?S%*||1tBb%YL_@vC(h)?^Px-gBWLVwTXn{`1uWgA1onn&
zQ5KF519u=U<@SPjnaZaeO6EuK<Z3bOpCCEWD)^vpkpro52`8TpQAF|zw7Z6t%w&0r
zZ=#2g)S66hpuO{OQmcYLB}5`6xr*_GGoW##NH%Lof0}lv?XDNC=2k=HW|3kN^;kLn
zVim2LT*jd7-g<r=O8D_?gIt-EW5BlhyIW+~e3nRHIHQCuH=B&0sPZ2pMx&0zTLdj9
zVRh#PgjhW(hH{%CJ(D3;rUo?G3(_kpTpN1u6c01t1JC{wC!^vMkwmmv3N#LhhR_-K
z()uw~USxM?vg&D2zY12%Yndr$7aMUYn~f8}Bs@$*SNoT1Fxd?KK`?1bwjlRn-vt{Z
z72R0)x24rKF8VP|#fcob3$J4Y-}ae^Lp@id#+Wz<R4S{0p_~c@dT_Io_hoU)I?R4z
z^Otl8+-~es%A|M<lobcdK}#EvHvhnb$tXL|#&K(TWtEnDe0dnCD_L)hG2S)Dg3)<R
z-kUcrp`}FJ;L9C}&oEAkOk}TrMGiLRMF3v^eQoPBy|SD7kiAC0@+~A25}H-gv4M*J
z;CqU6WrJjDm-sA=7wK0uN7mTJYrpRToY9nQwodFFWGS<T+mvJx;(q>Mx0Xy9!eTgZ
z^z`r{`XW=yAc9=a+nUuiYWwk^IcAlLeYbS-vwK!D#+60-K|sVvVQBasw-IiZ{VXR#
zDz(>BV^@62q;p_$>p?Lkc2GdbZqI^z#~jMBkom-g<+6g|KQutGahXfn0RT8rgB-SA
z80z30Kvs0r=%?|Qb%%<RS7P7<HB~o0E=@mqiA`B}QJj$nrU&hu4i1xUBeC{qpi3G1
zoAYXfy|p`nq0gC@6_$ByrR%bf@=D*npd18){*PJLJ;=&`ZvNiO{cy>kPt~0T^_>p3
z4m!|j9b}siroPZ>5rmWLt$ak*`jI?|dgN0t##44atxTc)t)VV8UV^wD;?8Eya#Z@j
zeMrb2ePl8Qu<-PoqL~p9XLpsIoQ9xF#t+nKDM)va_kL>4YZMof8XQMqUB0CjdhHEg
z!>U0?+4G$C(~%$Qg5{J38GkPj<Mx>kk<pdi<<>>7D>A7bZFmohgj;x&YciN#<S($#
zDc{3)D#p4}H57sbGdbeiN84@$yGgY6lYhPOk5lt1+~2k@*0)3B;q=gg=~V~TEjZZJ
z_n9V2Yw$P4S9o49<&EwrG(|2}kj?zZA){+hCG@aPLvN9H%S_8aG4}0rZ5dOA!0d65
z0w!XUh4>ISFfu={pg=NBy;pU3+f{Pf+*0d^3;8hgV)gH=RgVI`yzUiR$|wj6rB0!7
zP><)>;3Ud#%tOu=Gq|Ng5Hxi4*fWASL1hmD{(o&ouC0!Q+ce;SJZ{O3`D*3kU=D1-
z|Kx)0OUXX8&bL_fL-Z<?^;q{$+Gg6>W$jM^i9j&K%YgJ!ftJpN>0^;FuRs?@PxF1)
zZCW9L-3e+DdqI7T&^3%0In;L>k^6wP;rs_qaM(I~>`*p_q!apg9GkwQCUex*2?2N$
zvh{g!&J2qVwfjO-<DMJmv5|td$rJp<s8Z7HSwyfn{lhT8u2=hCJ1s>DfR&Br%_2&Y
z))`L)1ziRcjeM@%<T&Xr>ilsLpiEy!#G6SM7wkt?Zv<feE#GgQ`Caz2fK*8NR*Op6
zW_b*45;X3)@z<}SD%Z-6*E`hhVv`k~7Uzne8t2Y5{&q95$a5!kZDcnpmju~-8rM<k
zqo5q*=y~ru&<c*E$&@x*3ssoKP05k(ZrG9?I9&6-VFyXjkLg-)^_xN6wpQ*faxEYx
zK6cD;e}M@OfA*Lvf60g>cvzsdJAPiLlc`zifM%(5ZaM_=afR`2^7L#cB5{s=PsO_=
z&I;;3@fe^k_;T~loFIn>W*EVvCauP06lT$CrU>xtUn^F}49OKT#_Kw9Ss)LFdcYik
zwsu8HdhMS*6-jpBwt9v<J_IU()B^THA<?<8uKx?9dXB2i1=!@>fubdv2BBl_<GWpX
z^ERX>^%SNb6H772ST939l3(_CxQ|V@2=6#`7qy+Oq3Jbr#;@$T`dU<pGnW!3EImJi
zbll7zxs-d!@6%jR19y&$M+aha0|4_0W+7f`rfDP!j?k%*lSdBss;%S2HiB%3Ph>Zr
z+&4xV^=E+p(0$GPfxHrYR>e7+^VNP&pPvrszRl0>4A}NB9J3$LS76jwCdd7V`HPfa
z>H-uKs0P5u{0;Z0?qu0#88S5W9G(KOV&utlpUR>S#TL5@iOFA=;^t^iBrnn}spkqV
zQFqPR!3hZ7T8F7TuK00?Z}=548k{Z^mDOEiN~cXqExjU|<dzqasn!?8<xL@kU@f#L
zT#($f0ON~@fu^UE6|YQfCIL|A)<9{*Nf-h$$c(3TB9TL)MruN*oZFobL#Rd=1c970
zdRwBZpCuu26PIhqSBO?BL7ue5{gf0g6>DpwciHYJpPDn`q`@FmV8c5Z(%6x0hg$SE
zLwAc4B6d?z#yI@04Iqc@oyx1vlZs=W$!^^o{>pmEY<g*W1x->*0O51QAzCs~=d^4_
zxc`m2wvvcp0LVcX_0Q`P>!cs%>SEC|Wb+fB2*V?yXY6S)8AQX<Fb=3^7lL1yDSEoK
z!?XqEWueND!vyys-T6R$2#?v0!HnB=-O8!#m*CVb1=@j>jhLFd16xHPqL7n5Ck|h+
znH+b0+`o+wjuP>E++UUXayL)NFVvVzqJ_kcQJshhwbRBNV!b3Nluu%9S!MJY|1Rx4
zc`|7yqP$DX-XJ8y22OHFAMl=zzREkEfkv~x-P#u+1;9zKc>ufPKJA%o{aja`2AeS<
zJDK10uv^&oW_hD5$$(D79tuEeb74M!6hk3im&1F7m7jAbk*Oxq2W7V^>Gb-@s$7}H
zv>@3!jHvzd{)Belrnl{sN;QR7h*6lxHT0=Gznr^wN&s70MT+g{hx@wj!Sm}3+{w)#
z0bS$Lfk+7%9{CblOGIS4E&5hBuFQaa8L>ZiVT@c|JL4cGC`P?^G*c5kqIu=$9?*}n
zw9GMtV`0JkSA(Il8xS2_{i>bz7phup!wS_|hnfmzDGOHf(lx-RF0fB!uWo0la|dp!
z+V`T|0{)Tx-9TSNLx#Cr{*Zc`|Gah-Tc3k!l4b$semcWez!j*Sqw461zV^!aQkw3u
zepi&HyinL&Ehq7nt(NRG^V5Yq(CD`rw*(*PH9J)VyBe=afP1~lb!Pp-QWx~)9&>6N
zGE>ID=jr1fHM_L<Wyt66*(qY0!`X|lLvbJ+#_`Nyg2LZ{TksBG%H)z&k9zD88pF%!
z{~%nAy>Ao<{E9IN4wEm0u=vgR?olK4PRet<aN2r%Tf76E&Vcu8tB+mjL9khxd#Vzv
ztcqAsV(^CUFDIk380DFXW6+G1%wSuk;224R@Z8Oq7^lKWykMTgDl-k>rbKUtDYLih
zbRNw-`bxr%`ni+ug5LHjD0OL=*~Fx7?a4DZwZ#9HFJ)rueUuf57w2!~J2G|R*~r1X
z)VzoL-X+#uGP=5UQ<SZg#<;6?*Pv*8w;T2_7?7<ITbJ>*b^ShH`=(~^)YO&JD>i4<
z+QP6yo#I>Y9K$N5sH97CO77rDUjiO3FrNF%K?>^%r&muWW_LOayYYfkT`@z0E1fH!
zGi3RF<d?&j-cyf;Rs0==KVc=86Ssyl$dvfNhzk#9uR{rD=xsA<_5HRkw=1>Whag%S
z;CUhL=N~ablQtRcm9LsQoi{y+7w+s(4z7&&Aka5Q3lpb)YnYgX^ilK1yci>6aa7X~
zCcUD)F6m0t(C``S(v&6UICuns`o@8oI68MUKDlM$+LAd_u95f;qcX8>(^lKjU6NCo
z%gRGf%rh#9l+vB!K;ZDCE*1W<ShyCgCE;~5`lS*8-nd=!>8WsIAPo9TP;VV=4wRU{
z9E|8A2ESLReU9y2LV4(sEB2%5`Jr|+CJ}VXiBIWt^?O@WUmc3dq{@O({>TGbw5h}V
z2q-W?{-c0xh!)PlzSs|pIBwN2GM|t;Vmqz>t%Q)B0B+M0VJyE}*t&<rfA}aa#n^%@
zH%}<raUA`BLk%#o*ZWZR5$LV3cUcwX;@Q$kvKp6S*la#C?@*K{j>#oW@<&8A?x!KM
zfxX{oQ$*7RZx5x;$iuFkdtH?-Of_kR2wYQ@MEx&zzpjf(%oX%LoQVv`f#-12;H6t>
ziOVl10SDu&a%2Bb3%lkOju(9l>=RDKJfxM-zB8Mw{o1=($d#!BayE<st|M@bd414-
z3XfEx=ryKs;mZ!G9&oi)0p7xZhYzNEts&AUrHJcZD#?Eo0n6Ns#mlH&U&Gv9Tr4G#
z&(F#6bCvQFKSL@hpEOulwCDVwf*mCDvqiKPJ;DaY8_SEz)=Zo0jov9{!7Ij}iD);%
zA)N6-Eg;b}HQju&HRQO3Ex<%hw08h6z_~~|m`$3<`;Lm|UmtG0??cm66pYZvNAp3B
z-W1Z(VHPJTMVsuqa708c|4L2N)4%5Sx9AlHZwUtWl&6b^p~ddiRLTn3T=dGGg4O3z
zGK`~|5n*UsbxV4eD76v<Mm8SQ@=thSi8m9PoBAj|oPK)Hcuvveem>Xb>KO-8bGZSS
z^&bY`I3wZ3DJae3rL#dciRjl?SQ1vCV*|bm45GKogt);PAVq&s1)o}k!@3b$+t3J`
z8yxhobKxb9qb5$SxTI;%3z(slV+-d2@Ea(P8^EhfT=_!tUq79u5F43w$`}03_5?S5
zZq?s2sH>N@U@WqKOvh#{e~d%YIdlL?TUtkYoucUa``oQ^e}iTap`isJQ3}nksi;7w
zv+sccZ>%-bn)l~qkT8qh9i=or@%~H@e@u<E(+H@gnIcm7h(AcW$-f5jsfRSWU1G(f
zfb-vVaOHMaDg@}L7|Z*v<*|9Dqk|f);gSbvR?p+1Xl#~Wer=dMxGQ!I@PuR5<~7?A
z^CoZg$AHotghhWWF{PfiqV5)bOoiFJW(w*k@P(vqM<2aaDo^DH*p7v08nXT|Dxi|N
z1%K=~0XIDyLQBdIECw+xAAe<h_kXG2NrVsookGPlyrebn$W*%zf!VLz1^dRq3jEDN
z591WKN%3-)+k?v`TLIj5Q*A2b0ESP?kmMza@&F)Jq;t6`233ELab3NxyVUUfdaB)@
z;N9Y9*a}~4Dn725vuP~hY&a{#gx&hDiKqr`IU*W0y<dr#TywPJcF0eNlWyayBj8jU
zWGo)(jn3ciHHPgw-hZ0vC(5hX8e-U8`?4vg&$<ERImnkhU}TETt7M!xu<FBsDf9sD
zq##?BhwuJ9I{d!0i|hhpTWwSKa6c@dQ&L^sG19K8A+XXnP)=>=?{}`spbY2~(1Rg7
zKSB=CkXLpG9dFUL)cZ)6E%3stA2M^z4cUbE{#nl;y3CR5%HzrKDAG!(Y~}K%5~{TP
zkU@EB3n<?)G_11=GD_zlGhGLx*X}@O)=Hi_L8o?5sIdjjYLr5OC3~9cO09^O2A?z`
zMZbWx1=~OX9jD?XDQY%+c?=!&!d(nwd+PJgTF@Am+c}7N^;&;$p`}j=^k`IoBx^Cl
z_Z^vL?Z#=+J2xjJa$wgaafN?y7C;E6kYAms&gUSwNoBF~FQbF21yMCbBNq)OAA$F%
zGRu?Vk!~K!yQjXmD`XPP6u>D9DfLfJ!Nq1W5&GFj=S1O6AO|Cl$U7*o(OpQ$SkXoU
z-uC<XMKeF71pT6s`hED3!c=Aw+*K_YoyI<V-c!t|GiA883C+QalXX98J@-3ANczM~
zE?|x%3GRd`8-dTv!!hNyPm$OPLnfv(oTINzgj|*KZu+sB;5Y|eO={@ps2zM!<R{cF
zbPQy$6ACtkg=c;Bf4aWqvap7lzKK<%-nHgWlDWT<1<wwf`4D7cMHD0X2)DXACvE|-
zxV*s98e?Ns@X83G_TcMqC0dEDNRzAv{|G&XPaLH8IGc~fcHd&ar2UaFL&Kf?-$m5O
z&aJI`JpqImDnjJ2Dt10-K597d$*-3Tc>qY%_w$*Y?jy>g0jB;=7jdQ4<n6pavg|lA
zdWDZm)5uf=zVj&Bkn$Eh0XK=7rKtk-+gD*00Ig9AdvYh^(4snpN|8U3NFM(-fMe~@
ziXXY`<idzHL?A-R5${v9v}ZBD;Y6WSxZ+9L4NVbqx#?7%vD_i3m_?fT-A=Zwc)W|J
zx7;?|n_RHXmvhak%hRSPxI=?yE&R5Dnun`$+e+=#2(5t$wCt=AXJkB*Jvi^sM0IQy
zILpvviINJXkMjeHy&PE&Vy{D&^n6sm{{VhO-dvgVIDYW~n1@(S8{85_Zimc0P<d{Y
zpMx3-fIEwC$59$Igq%jqgRy={+aKpR44+Ca)<~Y|{>yC=)tDV-DUc*?A33xDWH!oK
zm`3nyeZqNcwrqK<is;@scaHm6Tk#ECE;f{b{Vgnb<HCX{MRL`$lfjN?(F?JCv8hOh
zOZUNFU*S3$&=xfhTR5}97n}P&BMU;M`a6ZdQASLzuzKw@_+KbRfpBjlCvhf+@ieMf
zXeqH-vlflY53tJJCBGHy^Whg2sx$>f|EhYG2gI3@ucwy&EY)B`#5tsj(fq}_nCZkc
z$Vlz8XR`x0uuZ#C<2aM=UDnq^Ovfpct*^bJ3SBdVa}KA66T+nc7jCGfQaabf((B~7
z(}WasR>(xhbj#-%u>My)>|MWsE}S6NSVz%g8FJ*E%M)=5!;1GB(N88iGK5*pwSQuK
z^W>5NDgS=iH_ZY87>fi-|Jwc5NMh5!b_j3<It|dB=ncE2xQM4GQi)?>n@p}O<>PP8
z2=c-9wZr_GL<@*c6NM8pA-5{$V{ORNHo7Q-=|P6)q;H&R32bTy;0+IB<{@A>E>k`B
z`k<i4Z-qG#l296ZcU$}f4m|hwA>a;z3=8p2O*B~;XT@4ehqY#ya`eeH?fRsSq)?#s
zwO4H8{5*#2&drq7W=-C%ZEbv^MoLdC>q5+nSH#*k6h2yhH@x@I#%y<B)*GThM@<Xc
z@|nD0K?8M+w{ae@2TLFzsOR0p<D*G^@8|-S#{Hv^jj8?PTS{*PSRIH~!84M6HH^U*
z{sum;;7K*=NOO)7dFTKTrPd&J+=InRY=W3EQ=dY3V|!HRSWLmg93d_{p_v;I{#uEK
z3KMnvNdWvuojZ)+5Hp_T$JFB0@f~Y)Tj>=_t2p-);wVe;fr$p$36tK*Xb{3`D~!>(
zvmSr<c#j0_NkU;r!Zwo0vJGwC=LEp{=uIS$LrW$!n4$RMYj7FNb8MQyCNHY4&kc%`
z!A4onwe}xSi53PjnMNL?T8Ga0pPKn%E}i2v6@+OGUT&|ntFVkMi;b99Qe$ATzHudV
zy4?y4IE7^xDjJ41lMAb<Z8L~)Ou1~b7U8>g*47K-EH@*RG_H@bsyY}?@j=X>!FYNJ
z4Sa{rJd`EM>rRJ!S!UI>AEg`o<z0fv;mbbS<h~_vZOJVpzjy;_KawQV7%8<&b7J>q
zinofsZ1J<bUvU9H&F6e^60gv)ZyOnx|0#?1`8S-b?OFBXn6#}9SG|;*g(jEuTURh?
zB7_R3!fzjn2dg_k?VC2t+|8!tY*P9-0nW5SNi*V{To;)1pHF-!0c@%u9cv-!HJk=g
zv(4$0-{@ZlrcSg?4m%Y^oiheA)uq;yW0-i)&76S~&nGc6wF`%~EL~TX8MtD$_iDn|
z-sJ3%$FJjFAtdp{xZx!DwZ^~R?_Pgm94wCN77q?8$DnMMsMA>29!93TX+|b_<thQo
z1uEE8V<74nXgSuPT;kbtN4W>*EgG)1eq7Dx&B7!39%clXY@NPxVqAy=)3jyxfkX%m
zVdK4in{Kb3+ZLiT5Gm1U=B3)oJ2*SN&fG#Mlz&V#aQ&|^sB&^VK)OI=7mek1`xFC7
z5wp_MaTcRd9-Wjz<M$w281D?xD*G+T0>sJmzr8{4$ZJPCMuq}C@WZ9r|JaNXtWlhG
zT&i>tG%wqgIw899mp&!KG<owYz)bPHQ*R6uYL*yRruJUR?y(tjL-kHfk(R1Z{vB~;
zxB~m^^xPH+7qdOe{-Jx%y8{x96I}OKR!N$AX|D+>W%4t$s-W_Arap%N$$vzTIJYjE
z%o>XHxFIB-kpo4zX0U$Ea5_W{TK$V#ax{-6w4_|h$$~Khz(R(t>vBsTW-!$oVuNCz
zKv&dkWw<D8Mp(R%DsAa<Y<A&}Y?{gInZyR`)@#}@M1;5#`JdaF{nOE2hW~2xCGkcH
z)gFb%3ey<N1!0b+p3_Tfw+kliF%C4boq@!P!-ytk%zdK5^KB(o<x})^+}20Hw4bAe
zJ+Gleuu=1CF|9~-xBdKPErUg6yDQr|7n{oLQE*v0F|4L$3OT+_&Rolth1UwUweQI{
zqjD4LjyiQl(i;9qIg#}dJS>4G4GtY3;USvLfm{v?C1#QDn<v{PY{n1>l3WLZrL6D4
zkh79CxBF**RhEmKyM>6ObPyC{JHw=imbv!3*c@e{u6V?;F#9=)_PMah*EbGxs9wwL
z0y1vyr7Qt?{p-GPGXbM3dXNAERnh*lMU~Bx%na}Q4YZ$RNSM9D6_oV7y<w(0xz%^f
z5Il2?NfVHcvDz9d--&|db2+Gnw~mS`OhlVe!ObA{N(+D@RQGjsJ5e$?WM!8RJgoh?
zhQ=T6ew!1IiV#vQ5O2hEwYJb&9*6|P@c4U0*-Y8;OZ!bKMy8?|OCXAogaS_ySYGu+
z^wNKM_9eha)AFz5m#!L?2dex{UIuuu_+x&joV=&LXUOJ@M6hlc`&0A<r@C?>R=p{D
zalbSO`n(RJOQ+pMrMz%QpF#?1+=CU4hOAuGiu3<qG8A|(--6&Ct>@W6?Wp1YBQWL;
z-#KMHGqWTRW@wUmbJMZtSj=Qb+p_a{<eZpa3;?4_;lzxWRD1Do$1FLhQBdulcAV)p
z$LVny!kGLWgAQ)|*kEKi<2S|YJt7px?-R06D>9TW`24d1s&Vxj6ccEh-{_2G>z)*h
zY2k4R+gt7H<O7*E%>Oz_C2)n&4q&Iiek^iSi}pnzCpNhV0}S{ugJ7OT6?~FOBtJ8y
zUByZz(oNlxqALfRoZtRfOy9VcAPQ3C{8h{OT8*7n>P;6ivDKuAkf`6w^c*n^IUDI)
zx{!%l1mLsvrs@tw%z8U{M}4sEGSlv1NDch4bT8+5vc%cXxSQYguERE%uuT~)UdC#T
z@Cm^-zH?c<f|jJEfJyEQOj=TZR50Wb5HfzFAN{L^NN|;+!rl*7%Sd_tYgvy{k4eq$
zKJ?L!#SBaKdXz747dE{g3ei%q6a4uE-gh8pBf-`Em!lC=O%=pT0ul(nF|4-zVK5<{
zuJbq@cV!)>;a#Qi)IXH%XLeS@-wM}nl%;-ns&Zsch!P?~sll-(@(hxqh_=S77z`vV
z+A~ovVeHHB`4yuiu!+!=)}3B$f^CTuluC+4gf&aQ{QjS1JE8#!as@us!P7B`JTT82
z%K3|p1eM2bnE_!E#Pdg&;kI+_Y{}B+lAI&gS?2481?;QSXZ*$%Nao2<+q38Sda^Vw
zZAkKKB0^o&>j#xpu26S4E?!yc$-Oc?LDjprR>dmVv|?iS*GY^D-HS+l*RV8wlX<&J
zt3^$02nwU~+V%aw8lYQ{aZBet4N)4Av8((J^+%hDI%$})>7kM7O_37$!Ps{O3%0C`
zS!2wjCJE>4*PB5XuoG?QGm?g`FEe)nOG#brCwpRmMvX=N*fOI`LEk0o{3=lp636hK
zX7wR|Pm<dJ(UPxezx1NOHxThLgQoyNR+O-2(YJ07aT$o*Il76K?=JixpUHogbu=*W
zRP-w7gseU^DAGIOT;HE!msjXS>?G_;XvlLi+}Mv|so+<g`+~`HnzQ{6kkNO&7nMql
z@>Wbb39Ms@Z+Fpr1A8k1a=W?iCLrQcOJdXeS_+GbGIu*)3EoaMZ!(tWy*M|$aa)so
zoLYJVDn8KdR;I0qo(?(Zb=nqtl6^%6X{Ll>b&0Ebvf!y>_~`sx^hR-(TS8jR8M=Zq
ztb(Ob78pQ>%s9}7_6U;g6m12EM=w9@$!eWUS=?;|XxZXwm9*8%Pq`6f#{OEL)mx$u
z@WqGN6O|&_cx7|a&Qg54Ka3bn;lulOf-)S^lKKXhq}?Z%@tt*V!*8hJ;cz1s{4r<V
z68$Yx)ZR0i6SbILg}pjBn~>RsN$?_zBpI~l9H%|f#9*x_-em-_+Y^Rr0U7Xiu!Lu7
z`%<v<&bHmBII$~;-oPxz?@grUN}5D>!OM&s(2K@&C5V+X@}7jDgExJzwDNdV=i<Kv
znxnQ=L#-L@)UvC_)V;aBGI;^B4&;&%l{Ob^L@cnIFW3+YHc_QlfG{@ltJ=>azbO#x
z>QYJ#*Y0pOn|k6JjSLypO@(X%QHGJ(K;%nseKkq1Sp#8@j_uP{%pA0u&#HBfP0_SK
z3D|>I_nsfZbML6qeut>BdNOZJoF>_ZRb1>!-Ui(4QOGjHmBwpMo*BwWV4VFYrJTf9
zgL{P|046U4ohrJF$gP0}lup^%>WHGya&x690S-Z7I|W77D+O6_EHvBj5w#yo224YB
zTVg6~Q7SQd#d@+K-f0VB*4Z2n*N=GzDoTb7Ra%>jY+F%5t?LR@d!up9Gu9K6J|q+Z
z@AY-h<qbXs#?hfw+b7RBHLrHaR7F*nn7AT<)j|Cp+v*i@C*0W93XFX$Ww15#{r+l`
zPjE)FqevB-D=GsnvVLj#q7&OWvKI>#tXnm!Vn_5qT(_H#owt9BbFcRGAy{&ofRt<j
zobAc`4Lw%*xa1$4S1&}-(erZ=Bi-pC`z)m~s6uC2p8LjFINpir`N&`4@D0?tX)Mqx
zw{}Erz4Q-Gp#C9+A%P;Q0HbMU6>~Pfe^(DfX&RfgdGLgcY5_s01xdx8;GjFH>gd_V
z#1D2&?D5qDzPox#%Dv;Q>fL?1d$lAO+-Di1ZJhY(zh*WaV^3m)v&<1yb!#$`@5vx_
z+?lcEVp#@ZEVbm<GhOEpe5L#UaQ|HMhv`Lcm()|j;d14UflxBqV+p(c40h-;E+7~A
z$TgTC!K<j2-c!v|2RZTskjHBUGMg&_esARpXV%6EL7Wse?#yb910h52FxvYP_o9Cb
z!uWTsTuVHM2Vfueyy8Ma3;99iuq`%yOv8pUy0PrsEM_$S`}txN@Bs&B{k8HXe`|_7
zEdPW^;m>D0j0?k<Isyz4@#kMGY^WX5N7H`hc(aE?2n)+y7X<BwR@353vK>8wob@i(
z#1E1N;=9&jRj4l-zrK*jq{{kLL>dAeWv}A@un}NT;97ZgSC^Z3L?i9B?wBC9AC(=j
z>f>C#wjjs}h-YD;?1O&K(=SJs%UWh6<0ym#MRqdWh-D6&!UcMu*)~)=GtIs=@8DRq
z&CMk%B&AKp8PUOo$<JYiMZS&w;6kB`--z201voN-9FR=o*P5px<!kcA(9nf2JekHE
zjJy~~*9lI<To~f2?BCqe?p#>Z<_h!EN!uYFE46BtY!5c~Ae`a0C+LwZ&lCo;76jT`
zP}X|a_@ax~!=Xc!q<p$^yCcx<g7E#h9Q)U1f`^$JA<F~GJ2IuWSY0xwXWjD+fMa$K
z?Rt)(vo1U*ppJh<`WD)Ip$H_L8&Yb1;yY7E<Nz83Wpa#qkfGUct-B%AG<`Oga=n+%
zq{U)|QpgRXu*F0%Nd@Rg@F*5)km!yuZFLMF^)YDqu-!m7PthsKP`n*dVar6<V4ua%
z54?%CfDF^LyyocI_jRWyAIJ9A4uzlNapsguWrLQ$Kr^XLy>TBItEs;e5p5Oxu=1L#
zOw6U21>?!*l5Y-0I4o~E$a2As6DP1dcn){iTmq97>`{Jer1<0>j(Ar4=W$XUQ*<Hb
zdSi4a=-Anw+S_3&ha)Dz%eVs_JYP=L-SqA?2`iworwqH&)Zy~cm57aQ+}L=iYM9Rb
z?&;2U9n7n6-Ys5m?2K8eZi6wKG$n>cchdEOnXbWCG*n9rHX!p0^8w1V;_XEXRFBAW
zWMrxh9!_6m`pyHNk;Sxojg61>=`-dQrxCta1KLc7_NH78_Oct(v}a9T$52O<Q`-{1
z=pr+*)}1$f2$r;jwB#~83i~@Z_C4$bTcljlcvf5h!ZXh(Cr2d86EW`E&($lY-p;sb
zudH5CQwsI*uMxj@$QK9;f08TIm-<86evJ6F3HEwDT&6e7a!>b72sP%n8qRRxV@AKo
zNWB@3gbdVv{>6`^uuv|0L|#{K$A^&#f7SE5%x}5$yz*0WDwx;9iE<fU@l>4YL<_|t
z+0JYZt&i3fcdX{0NcQSTw|74lX}XVj_kPpL6f=YR=Q?2?M09o0IGycX?<*%|qE2|v
zoOLh`jEIva`YAoHB9)zC!$+?v|F0Pty&$&h2enYAcVwIaU<7?UYqs+kO;AC~2*=EQ
z-~0!CrRIdQCD(rY2JFXBxJ*O*I5wb`TOY>GrNhpciz?kIdsrdpd*rz}G=gGD2i7*1
zUi3JloNE5yI*~<(TQdtnjdf!^yb&Cf32I+s$0M?m6<o&58xf!~Y06s-B9vHC{-?bW
z{uPq;WnlSK$PEb)C62LJ&i)bhn2_a&%!0mCc9PO-Po=K&QL4hvwXQ>`{aWv}zOvI<
zk4iomQYMw&uC6X*a46i$blxBH8C#wJPGiYk8^oGLGnpy$4&W?Zi{$q3IshV=$REo`
zBa(749kI&Fu11-;I1OQjs!xp6a(MaR<-F`eLvM(LOhx{ydWztvi#PpOy3_wW_5A>y
zzsUF?b{=^MeKMMS#^01I&+f7bqd(~Yj6Mv^C}3v(dbAr>^rE$h^sc<)StL~5?&~tD
z0*)$}8!ZSMVJCzz)2*eBuU0)X#&{YZ?VczU)Rt0c@$*hB_BgsuZx~f3*ixFvt>CWX
zRj`h{X+f>Xp!m@G<8WY^FFDX;_*rcW^G7BGc*r{vdvkybkAZy*@hMdUVmq$I>D}=O
zC&Van=t#2UqQKaGe01W<Wy>zR8wvWquM$%i2JGCD(F3jAb6=*2BX^t6vW9%Tfp6~e
z){Yda|4mQzA>Rv_-|kZ?gAA9g=<fPZ{vhyd7>s-rGeTW4w$NHw6l9cwf?b(Y`dMxW
z0Z;NbEPs_n!069~xZXZPbF|!HD2+4J2hNq>6PrCTZ3RD>-hZbp<xP3YX$qKonEmo=
zuV=aA6+d<gNOx#2`kb^21jH)Q(=mmGn$cJgOoW@Q;saGi%8dd=dIGL)8B!4$z}@2N
z8PtXQMZb4E!}p>yR`N&CUfUS6b%b44U)bkD{Y&%6;k=Ojj<53^8RkC2bKulR%QPAI
zJk%I2fVevEx73!Jl7~UlFbCZ2l*qzN5)_xz21P+Xf0%*&tX_AQPJwWnTmw&*453iW
zLI_MSM$|45J&Q#($&J24(v$8|Mq|`&)nh<X;&=QSnw`PHq@^)GLP7X4!H&uz5|VZe
zVJi}J;n|UD2Ap^OR>TsaleNAm*7oSJBRxM9U4ZCOh4h%;GuJNz?>@A^K4DsRRaj?A
zBn%_n0N$1A-)!>PAZS(#H#2Zkt2!q@A@o+BYPz4zYh49lTc;Yhj-+qLEHphY69CoA
z9}&NZn|OvaSv4-X<-U&_J`k+$`AP-#HIMyh00ePzVuS4#7Z<Oo4(CAcqpaqE&>jLb
z2;T~LFbz4p5A4D9EQE`^C6F`^COv87HC&_aO^j$i>(IVE4O4g~0G@C`ghetE0;O1t
znDE3!5{S_fIdXQ!cu-)(&zv@Q62?IVfx8YUf3ju;V!{Zd#SnI!d-$3vmtQlO!%DOh
zkoh>`qJTyAla<-y^Q4-@Hjc7uHU3<6YbNtPzhC0l?~vY3rxXr*Aw$oB5q~^~28jQ@
zcDy?Jvn9M|US&}M(ynr#4yBx<EwJxyr~VEd{zApK`Nu>^`C<Pt)}p^xE4d}J<&5uV
zw#PaU;pt_NSb5uX!Ns>%^g?WHYJ)U(0Zbyj3(~u|)=FLMr1F<RKXW9UzH$7KY#^@P
zMsfE?;WGqlld8+r6IArj>ID5GOM(Gp=<s@tY;o{|(C9re`XvrMbOGW{%8@ur*_}+G
zUmXV%9LKkCftW4B%sh|;EUw$8k~KMkkEevjSX%h4$w=yJNZJ;<lMdHFpNhC~8oNs)
zf?NspZiAx<@xr;&9?QZ%$w{s9p6ae70bWBRDzbsXW;ae<Lf^$nP|Ffzyw0P7mo%M+
z*<0^%wl$Y7J~2=r1Q)0Eh{SV*C345vAJ3w_zLOCq(eh`efPAYwZ1Jm(=cg~#O)V*w
z2{W@TNpwSuKyB4&rU$@e*i*D!Ej@W%10&9gGz|o?{;go%(Ub&#NG7Q%UJ>TTZgsr~
zP++&hBgNm+ptTzf5NKEaJw;D~nkiEU<B<;)8^y9ACcLd@gc=CnWp!&>4Xm<Px&l*#
z)XxPVAJUPcD=<G=p-3m3luZAcCEKw@I+82A&ofY0(yw`bzZoyvbE!tja%a9MJfmG*
zFF>U2aP#~Ov_uD|T+tq(E|F_4E+>dl$>KiT-V+rv7x71p>Pt}Q*9O0Wv{-6X3=mZ<
zg!zxJd_UdHzXB&O8`Y^c&XWeNU6HB}2q9B3V@Nf(^NoYT#3^<?!kHomePwD#VZ0CY
zg?!S2Xoz`^U}%rrN1}E#dZ}jKTb-Fxk$tWRW_-r-N(EcfaN5&`#$7V%S(f|GhjR=1
zHhK)VwHj3`WWDA~BH2W6l0n!`+Gd#j<{AO2*0wL36o{9H;Aru|AW-+ODu|3n^~k>9
z6=qFU6>xVp&g)hF`TuHogRf;ARZHcIchke_><|yg#YKY%@NMRMu?fya>pPXm?ejxX
zu_Tjtfjl&JBue%7D+))*4W`Q#=p2jNl+_HN)42Pz-uT10nMVH@^*4d@Xa%Q6Ppllw
zx@a`%Y-u*x`vL$^w`@|<afTN4bW9W`XHbW%pI9ZAGxckd)#Cs2D1)f2TtLZ}Z)@;W
zGAyX*YVBB*#todO;sZa1alEd`L}iC}AA$OQCyE^8;QXj%)7>2un^?(sENcTc5;zA6
zoO7Uqb8ax}VAF{vLI~>c@?Q3K^Q=A9VZl~BY0O~*11IPp!4I<aJ`z;tcR;xj9M7C9
zM0;&YhsEJc{}*Z#92TXPvvDGtK{o_Y`k~D)P!H8i+}+KLy+5#@FHslu86PU%$?Sej
zwQcTY^6vB0s_g7$6~fkn`Q@SnyJS9Xfx^-iwG}ckwLVRLxE@F%-cTR7TY*~!qJRpR
zNn7I4Q4iLQs)4A2r8n!#rvaeq=K#x;%H#lKl+RUWoMX!cly$DK&DpUMD*l2!D<^K2
z07;q_jXJQ0V@6FOO!<u_!HvduaO|pIz+&#wq-JoLd<|6(>})5e=uUT~_}GWyr@vtA
zm3ipdl6x6T{@2ogM)#HGk%>L1Z0)*0kEWodhLN4uoQk2Ti-?Kiwpiqc&C4W17sCC8
zfepkT6U2IrNT2vHowQ`&bVG`!+b~2U4WQB~16xP>$B%1wG#^({N)%H*^Dup{p1e}G
zbY)k>J|s5n9>=zvE5sikI*IU?&&sN73&=gH1~G=pdn*1j6hQ@Z4p8#4(sIF7!45!8
zN2^>NN9FMW^2i5ZJuAdFim)#R&(vuI?t&KQoBPIaGLyETT4K2aK1+Y`s&%qCCx856
z-P<3{7}B7#)9EhA+`^}u%rbAKJ}-xE7cS6_A}=iwOIOY>xNR=3IE=jxRNJ7(9frmN
zUXh$<LwDLBn&|4(WvH`E^oO-8%CBloHXSymc#3pL5uc%7Z&~Qh%!QE-78NTx(?W<t
zkIlM${`SDtA;cub>(N`RW8CYkxB$zicQ-Gr+{U3!W~7fNX2~dKls^m2Qm<^Ch;OBF
z^kJqDR3&OBS-*K5BT?wYG!T01$(b*l^hZOhw<>GqDByP4IN`6Uee+7M9;qcKnqQED
zn~QIWrGkJLfd-$mHitpyV7xBGa$P|JB`u*vSJz!+T$=^NxDVuxQ^lLuIZ>AWX-_pc
z!Egs3;6_qVBs63Nfo@#}V61mK22xYoxbzg3(nqYqzw<~!+!BZTQQE_!_m6!<^7;w%
zY%x(c;G`hynetQO++|#C&H*`w)85Gzek5(8R(g}*Fi*27O0PP;_k+1tkqPnU1b0Ut
zmd7?R-?Zfurb&LsZtu~I*PfvNga!P)t*GIjZBYfLN~d|Mqs{@3e0?+_qxhVi<3>kM
zz@sRfOdpDTO3((Ba_FBw>K(i;i5NS~TvaB-+CXr6c1J!Y*<OCFfss<{iS>{#2=u_C
zBhAzDwOmRnP3jlpC!h&D<Yq8sSklu-dp3G(VM@Xxw^#eBU51<uHi{RmszO^*Q^>u|
zJ7q`a2KlzHu$5LF6){ze8t<$Z%-FLZ+&Ja{MhYz1`tY)d5ZKw9_oPH>ZUT9?22_(e
z?3qR!ByhBPgVq8of0rOMhTf0^wJhlOql=$PHUya%g5J~FB4-j`XXY*IJQZVT0K32N
zwKo4Z&6Wq=4eCOfce}v=vJMmL=-fA^H0?VM;}O9By%`fw%>;WB$USk^a*ciwXHq*Q
zuO4LU(YI^?YaT>dM3n-G*dY8d0}~0R-Fcnbe2zwdl>(Z^VeyUXuJo9`?3IgMlr@Ld
zM9Hn~T!blIhYq*G;+V=OF?9y-Cq^@q=IKp5`I%KbrHX31W~Uy@;ji{I=O+t3(L7c5
zL@Arf-sFz0gDgj=Qg0Vb<YYZP7$)EV%eQ7VrBjKXY#q#S`CnJ=)TAhi9U!QXgtRN+
z=tmDe=HLin<iRjs$FPnb!VH4fb;(#15r$0#<>qY^H0gD*SNbH>rB~@eQFPx`QR|6B
zPYCUfIUG+-(|QgTftw%qETGrNhx`(F)yDi*D$oEb*YQ`ggT^G^Y=n#uCK)|;9<_V0
zb>rVd{7tQ?`{O*MsQ&eb>ScPBvDt0D{tNHskK^gj<cJGxz`<hb{Ad2rgA^oEI7u{)
z(OmzEi&Xo434p5KYxhJ0EZ1elXA?@(km8<%*x^vZE_&v?3#0DplzIBgB}J!9<UZK4
zcVOw5Te?x#-G;#+>=_Hv(ytb{>v`3#On8A!I-=kd9@AfsmDGk~pHEf1pyLxj90|Zh
zgm0kNwSrd%Do?R|4#m5oOiekv+}I<PxDH{{#yhD_oE4iE5!?40;6bmS4VF|6^t+1!
z;bCNdv*`)q)?9Q{`8SHhqtTxgjE2lvVoYj~anJbXO{j4}PeV~XdcQ_8c&5=GoByi*
z{BYLC-6&7Q5-1ZABb}Mw0M;U0W*zg{b8mL%v8z;`v_F#@oImeyqLZdbf2l75D#<bW
zV}*QpuZ7C0wU*~JqE_Z)h}f;hwLJT59R}ibjZq3e7gFLQa=J5ANi;PKP1HkA9{if6
zw&np6xl8=`(DVsTp#q|y#vLYO!483l{RmJUtxh;8yUAF2`B8T*Vg(A}kM+AS|86*9
zotE!(qqg`hQ93aX?zf-LSax5AF_29);*1rUY2RKU;JcvrwTVsX>c|{Z7QiH!|I*wy
z9O{>9MQd%cL?VMqs%pj4o*e0|99lLZVChiZ?*oTmoRkd-3l!?`wb`e@kuylT&{qAP
zxr#5_>Msp3khO=eVrTTP1jo1aqYWx_wHd6xWzO-z{fA-7yc%9tBmR(tjpIe;;-=%1
zM#mzDhJbwzIrqKtbS+-ZW=vu_D6YNHK61mi@Y>zBdtaapC+(^v&RCm`JiV>x&5V`t
z@*Cg2W|!XlJsfzAT{ajLz=WBviNWVJ0E|iH#r7G;{>cojWn&x4tf<Hz?8~}ZlWZ%s
z*-Dj6B1DtzAX*nh&J@U@Y>$^MAo=_<SedROnSM2M9CGkx;XtEm`Rvy=Js(1I_j(BN
zqmY$3_Xdx}Z>XwMgOv;bnf};n^2y7md!j*OnGEWd-omwASYTY}jpRb~vb~z1rzGDF
zy;XeKEN#AcOH}8nKgf`5pK^&EwP4QifgpKrwQ;<$ULU5z{~sm!4Zi9x;&zfu6iIgn
zkYL}MbU4QQV$1+#ViJ9*iUyqvWHKgqx-3TORf$TEgaa0rt7ia&s4sB%vMWkgKU{v+
z6K<4dCIuQwuCt<-=kmu){wH%EyOWX1MM?Dv(+35!L2mm0G2faZd(vBVYVZ7b0Jds{
z8AcMIs@7G9l}|#Q`tnV>G*fvZlqX&l=CKR1L#cBTGLeHFQ#Lf*8?7Z&rBv6iBG{hq
zI)`tZLw(<!Qob4Y1^Siq^n~D<EY*(^w`ISaCo=RMM&=IH4m#5?)4+Z+G4W`=NSo9(
z`URLwr;5Qi8Q$l?^uqnw>?Py-#XRw!j0V=7)E^%D&g@fJwk(L0JR_^=AI!$ddVu#^
zH`QR!@o_64|8kb)qSz=VE(<;4CnPo;O|<~9D^0P4Ih@iQPc9NbyXF)7nHtXUGX0p1
z#j`9wwAP;&O+yMJ2H%XO^!DLPw13K}Q3%mmj^&Sb#xr|l-D=cBCuqfAs8wNJi!HaL
zQI!~SlI+sFjT-G`D`JmjnOJk&j^=LP?TC@3QJh)jj0j`;O^sc+Dx<Y+PPQad3c54g
zTi5HR0EGT_NwNz!nik`xDG>}!A#iK|2*^764$@OuS<*>PELu^1H?itd)^4}@_ONU2
z?1>uc?;u*(TGIt2<SeM_yTj@5%D0Aeb{d+iWA>#8C}-wBA3|B?_^e`I@CW+1c<n=w
z*kNXffEKv!O~P}IojlN@?iV313J9NUzh+p`PzvayPX1d+_6wUo<d`u1bF6}A#Fng{
z^c7SW9YkNBQY)5=eG-?FaO3UO-J!JrC`Nrajc8<lTnM$|aP-d^<)LglK8doQQ;luN
z=XsncjLOAO^QOO<LS-*%Rwy7mc!MZ3KS6qX&1Yn5%0ZCzmTq)xIFbmuGmx+H2Y|-e
z5aW=c=3iHoF<J;<d-0eJ?rf0Bm_x@R_2LDjt<I#e;;}%2N4zL*_Pj{@>_3ssgv}CL
zH~4H6*sq*_D?PJgs{v{vNb8gc4tqz_-%l=*u>$GKiAX=1=Rl4dOmuUYisH3qjo^00
zs{Gai)n5MDfTNC%7lQx6X3ku_Ycc)a;N}#NkJE{20+@lb8Hw4CL3ld)+GJVp{uaCT
zKNuwG74<=W-qyTb4l!_gN|sg}C1BaQlKB?x2oHbzsx<L1fmeD7C0Lewe=6hjxj~fx
zlvXgTP1uSgv&paSb0t)?R$sLcLE#!|G@Wr_CK%Cc_loGn0Ci$KDB(9XA^>~H);_s%
zCC5elJONm>bB$`@7fIB3Y~aCE1<-oMC5I$bFsKC$VAda%M>jV^F0DCccYUn)SA@t#
zd!b9Z+&yOX+<Oe{38>CIzFNU%#x1px)xGlozW%Sd*DL|x|4>HBv`LAr;4&zUj5c^S
zrfSn@_i(N(zETn=<9XH2ZEe=sg$;EFc;#|hv{K8lMC|VX5>swk#_n+V(AE8upD_@D
z{_zt3-Z152YOli87Dc*;)12XVP8Hq-6eB||&*N(0**}V6>){wf1c$RS1k(}0n8e*4
z&#w1|S^T<0{rXr-bFIg1<boYVcp-(gai^&t?k4V%&N2(y!EsZTg!$9>@z*ShwqU)$
zJ@yhEBf=nHd=TxksDe^LqQ)gu{-CmNCTCx_wQHX@Qi{jfK^hIET$lB1t+TsrNTF*j
zlLBn!nOi$4^<|-qn6^YtFfVr0E@L}qGJvzE5+ahrwk$nc``cD&p~w3XT^Fc#j`wXE
z$aHOPVc0yB0F^WJ>2|{*@9$#_Cc%5xxKT2p8iD@3N7^q5+H*{!``x$D(ZD&xo>{Dt
zL%KAmdW_Ieg?Cq1I13Y%1`IQKe^TJNkhQ|NV2_~H1%nv$PELW%!H7P{{jCbBHuVf_
z39JOfeKh}z50{D3ZRy+GousEv1Myh_E~kN?a%9X9n?zn~gmX6igonW$yoZo*TAMus
zZEtuO3%(Q6%|dF1jPzV3E3v<E&`k}RFw(ds2)N7Q{W;ScE0FZjvJpyNv?xo0G=nZo
zykMh?*Fy1o#8y^;077bW)p!4fHDXOh^X45}xh=0YvI&14Vw2d%%-*T#itz$L6nrvZ
z?-5(xBUXbsa~AmMFlwJheju#6>6f5uIT`O>Y|;n;?|8@G3p&cowq&pvd)&whakBey
zlo53BygDAs&1En-^BD}b-vM5|q>bR9OytUALZN%c&~<PF*OKL{d&_yZK~dx-2&<MC
z^)@j&uU8*i3pB?Ps)~QAXLV5<R2ejbSo3n$66`S@tek>^-GZ050Joc98pTYR+9n1_
ze>R|k-Wymcyh4QOslgi1TDX>giMRCysL*zs37s#t`OrAcS5z@8F{q)WteNdyVOmck
z;X>l#2R)AU`T8+~96&P%4_<#}_#j#=Hbng6m5S}yMPSU^y)iWv?basU^hoi+7T8l)
z2HcC9UCu(Jz%3InzLKbI{^t<R<_6f|_0LKbQW^AJ69w74D(v$Zh=J84g?3{k-I?@y
zY(XFfv$)|Q7;SKZjr&qFeumNr^bkfjRPzJpvj;T**y9L@b(mhxB<=R8cyMWe;7h*d
z>PA>AzS4O!t^wL4NJ~qEm9@=)*vdmutV7o=p$87ViytSN(6IT(8oi-aotbJ17<eAA
zfoH?F!?=@|rh4K?L0^~J?5cD?oIeeO63e2}6QpCbl8+{!Wms~b(wp&nt{0fR`RdpA
zzW&_0aRi<_#7dhr`sJae<A9;(kFvqfH_VHcb6Z0GgK>IJT1>o>C6Xc%wgnTL(i~`P
zS%7eT&mkA$?G-Zh*lS5ZpO1WIL*6Rq`o1rQRZ_Xk;)8tZ6LHDJQEjRM)>tFZ`v5^e
zzQ3SjoNh*I5|!vAilVJ7O<O1vQ8xj>lg|NRs(dy8(i04pK$E72Sypx2Z*E%Y5tNE8
z4n1J!T?z3)_8woE=<#h%UJnFO8|4T-d4pq0-wt3_@vbAJMp+2L`o4BVvtEGJBvWKh
zmiKULF-R1Sq_+5x2e=cK<!xCGsSalO*7pmC)0^!bdKvP=vcE|};no81Bk;j3jt9Gm
z#TI&mc-}Y2^`^SlFeIZOH*d2t0IZ<s<!=)JnPGa+3x1Q(vPwZ2vCGvLFPu#7zqh-m
z>@459Z-DYO6U_<vdS=Zf`uNIaq5#nLS+$2>9uRoRaA^j0Rm&=iSke;!XCnX5OGvwk
zg%NEAQqexIvbdR$__g`w|J)=Jq-f)2nMbMrYFfy_^}R8aQW?YLSeufoF9g)!S+~Jc
z6QIhpH8vB2N0ktfq)tx^nwu?xW>wkYG^GhwU}B#{u+v>!`NQqzO6m01m9!0<(OK5!
zC`f3705+BKWQ<QjTL@Y;LYiKmIIPqB^kN}ji2;1&wwh31{2ABBFc+B1bH@xr#%w=^
zQ7ifxfB+L`g{^{o7E<H8weGt1tXJ}6;dCv}Tb1->PV0&A?bH&r`HJg#WI0`f;e}8F
z?woys4?{z>ZTeHoWOxrk4jf^{_q5?`(<=Q|E=#vL^)j1@PE0V^Trt&>R9%dVA9FNO
zIyAk_hJ!LqGm@Pke$i5N`}>@W?FyYAJ{IYOu7dHF*OJh6IwVeh_6>=N*Oyi%@@n^e
z7KJ4M>^%fFYG>78W7yrh<}SHK)-ndP8iSMmWEe0|U}h$^Yg%N_*-?%?ZF7BPRs!S%
zI_L#hVJp?sjVML9m4jG4gQ)wedQ@a@5ox0egddSS9d+*<yB^}h%q38fG3>m}!ONZ8
z^is^OM_;#!3?l2nw$%gmed`W`K?KqcS^>E%lQ|M46oaA*oPWMz!NOPyX+{m9!@NTo
z;-$90&v7%4Wv>K*to_yQ{pf`Bnp7-}yWg2_OOnwLasBB2EZQwKBX)|g&pURLNXO7O
z^|*%;hj1}!ffVxaS>A2-JS?n}4#i>*<mj-`%g5r7%pLb%z`Bi_r<bj4cQZB;CxMQh
z>W7l{B~t4c1>V<F2}oat&H+e@<j01MV@E+fta=EcMxpH$Xj+~l4CG?44ql`0&S=xD
zsO+IfNK4$}!s{L$vNWn<CjHBW4kBI4gVeHrg1V&`#g!m_akx2K1Ox>#BymLGqiW#c
zg{<eqt(m_zku#Dia%y@l>0UNk$wP75kYFTVVAB%up%Wi5ZLa8}Ujx-DN((n+==UO~
zR5{;axW{pFaZ0d?KwTmDMfcXlN9k*C`ZNZu-!~0jopd2hHQ44iMzM2zvrtrHijhsY
zWcb|uwLgSCl|oGobMljUnp`61dSSdCt5>AlOPB^?6P$Z7^RR+CLje;ne!w7q3;I7S
zJ9OpDLchg}+e^Ja`^6`M?^-NIp8iJ_`Q|W3omW;Rv1ov+BVWqHtcX3s$UB876mfDy
zQFM(i{aZp_<y)>G%!D*H8uq<&=|m&(fiGw>F4c;Q*=z-|VnH?t4!8_2S>mX}<m~t)
zXpld{4BQJo5|kKlKg>6Bb2x=*Dm)*dHG>9cqr{_{D7kRj@@}A5L~uC%ouca&HzEO6
zZF#u#>3Lm95h|IRuJ;qj_gNtzrh^qd4z0q1+PwLdeYdLj0f&eWO+H*PR;~z>OQsv9
z=24B01mTfBPmHkpbKO|?+Ytk`LN-(dgU9}K&_EaP5!vzS_ahV&1H)1>oi*n)zYcMj
z41O7iG(T5w6)np3siIXKu&UKM+ugdscD4E1?9?3w6*BaLxs+1vV|0O0rk~~xfrqK+
z3?U>saA+QH4tBC7`n>7*6nUuh$*3<lxr4&MGR_rqxrE`F_9J=eFT}5jkk}q|0(9i$
zqlrFA`0Ra)=|WnI%n&kBN;Jh4tUchZo|{GTv;)v=GF8MDMs~{}rJJmSJC9<i>1nGw
zhd(e5Bd1F=Z^BaiF(hZEG)M$4*+Zw|5+hLV?Iig^wNZeS=>rBnL+lX)6AX^d`5SzZ
z7-%g_)Lc+r2MK(65>8_doeg46eE^Md1#%e4#=TO5OQ6`N-rO_hc;x<(dR`x7w8yvl
zWGSuiiX#T=`IbIdlyVe^kQ4T@2@8KP0br=5diYR5o2PJsDN^NVRrNn=8CfxYZ$D(8
z{wF=IW`ChSzQJoe7WPUC0S*-Ke|N=&1DMn>Bn)3!R!nYq%>C}3ti=`K07V9lW$>M`
ztCWFv2m>_F<ZJ)t(NfPBWeb9h=47~*=gOapU&zuHrY}FrEofs2K4|9>@X|$=gSs43
zv~Ms5=Qw|U=j1uGraOvjzf1N*oqx~>h}{ulv@XZgA;D=BN`^v5+6gj&H66k_@I&D9
z;l-&LzyqE{Kxy=l6R%N_F^!h(TAj|zJbW0&6&P&Pnm*|(cea8hYJrC)Nwr)IdT=k>
z^?pGzCvWo$0&(@v^Ighb0aQM~2PZPq!n`#9QIY=}Kxy%;TJ_t$JU(Fuf?dM(iu4x#
zKP5$6eT<6mb|(-0`Iur)R3)!FXGa1ddp*FYI7m>VH=JCs-`U21CYP>IQkGM*q36bY
zFK>wiu?kWh3bhi3$*(LeG`&=~Gk7f}&^&8VHs@ys?6LD>w_Zr?&sX96#7%b(_n!k8
zX8JGvzE<pyE0e{&ulJuZeUauc!#ml}gO8Cm4Ri2RG^o3A4)fUZ`T>+9VNx=te}D*V
zW=2_j;$q~XDWKl;*-V+8#YorY+SrD?QFc*Be1SLK<u4uW{(90_VD-Z?6~^CH9m%G#
z7yzXYes*K?mNFf}xM4eY>i0MLxPlW+f_qG=lXR`cfm}G@+3U3T4YtwDQ4}p0CD65c
z^u6|g{BgB@9Y6x%R+QY_(o{|5rQq5;xZi-H_1M$5kDvNgLp_WUU%_O)|0DX0k-hE_
zc7bGz;F4}m9Q&a~o>6^%Gprux;1!Nddueo&2;UOxkgto4*J|vr!H|44D0IN|`6D~E
zQ7T~Q_t<IK*KUG!;f9{-TBuENPr1=~43?J;q(6FLOqzzZs`23D3U_aLoo-l%;s56O
zamfJQToKG8va9OMu_H15ENNxSDA|>-o6!}l#Q!oB8vOEn2V9{Kniva#L&RB&XK}Qx
zzis9sBdEW5WIcWS^rluz53E}U2g0>kl>Yih^hl%^G({OR$kMds$H<vgS2=v62?m!X
zMcp8a?{Y;=QyXCz;9a&(PKGiNTmK%M#|(U~g=vg94RhG7bfZP{#X^B4=mI^ghPb{u
zZ}O*tR5*WN_X}7GQK<nUjcijcL3$-?K`g%s7vOXl{Wk*MY)!yEwUH3j52>&+<Y9Gy
zmgFEW=8*~cmFP7iUFbHmyiJ#{OqDL^Kt=fZfdDIn6t#oEvZm(}8G4lq2zg5f1MIbg
zMYB55xX3&0ZgCJ-^{q1V`Bbq=h*7Jk+!M*#gkO_<7Z57oHuZR7yO(5uSdf8YdDWdD
z0^<<_$s#vRgy<PWQg%YA=cDq)go)80rAv#vlnlHD1q1V8=HMc+EdMGAMSsIikcsbO
z?R_>p#>V?1E6X6BZEb&NGG{z1+{})SxQt@wYLWY&d>LA!XVNY<_5OHei~f1M$>*}2
zLv&joIDDq{>99twICIB5r=t(Uej(f%gcsW{wE3YS_k%5`k!Y!@`rdq;3`nI}uYxv^
z3WTVugD(iG5F5HdUB_yDYHXCh$>CRbE&$pgFsTfa99?E5bg`B;(vx3l#ocmXhz;RQ
zJ9r=)RR^<RkGKSI=h5)V=72iVQtxC@%P`o0POLWwyK!=Ka0~hWcp2Wmp8)!uqezd6
zu8z`hqIE2MPjR(0^YjVRxxNi=fYI5K*g<KQ8(2GOp<)dRcwkP>Tt%^-L%OG3&NSct
zv7AZ*=B}{M0$E;wlB=g&im5zjxy%rePRNO8P0l#7*lllAptV%igBI{8AL)-<g{RiO
zwILy&!bb(&2!lSn{c<Rl!ZiBD-mjmLwK=JnPO|Q8@^r6Ao+hT+z1I2Ewd~XGotOC^
z^%mS9u*bGXr#sR3PpB)d$N5!LZ(d#YQJ_)LOcszkXAX~ICF-cX1m_=R!)UH8v8+dV
z5g!*M*pgV_Ij{ZEfZN-(M9bG~BsoXSZ&(Xu^Nsd57AWf*yF+P{OwYU{g-2R_n9^F)
zsjh!h2%Y{o$dsagS?Twn(c3iA)pnlekLRaR?k&usUXZ=**v4d>%fT6S_+x%+612$V
z8atB;_%;#L5BUV;;lvWDx}B2mvhoG)6U^lbEn9mS3^v`>A&Pm})ioMs{J4+N9Ko$V
zlGi8L%)m}gV*MUx%KtjtEt&*bkLEy<-nL9FAkOaXenF(KAZi{{I~t?dUnlncj>(vU
zpS;3{qKNtk5I1gsIcoD4+_|vV%1(qV^erM*j{KdIiUk^vUws5+4B4)dZob~0HTMFL
z+_bo4IShe6#8|35xz8@-2j#%<PXr4+XAfDbLXQu$xz05JS4P2<VQRz23it(P*t)-w
z`)&gxc}Z=-%))o9I(wdU{{&yVMvh)ulDyO|<Hh|!piqGGS@`@uOm`#&i=oqhqmx7-
z<72@7oS2s)lb_Zm;?QH(08J3bg=0{Ezafs7sA*c8zs>Y@gm#aYGnZA86+i=VY<FkS
zw=<DrAj;h?y$Wf|DsJ6@aSt*Af1P9}>+PdPKYevalsC=<3?xCypOoH$*Ufj5`J#@I
zqpMy!0Vd6e293{=zP`H<k+v8Ctw@F0DMQ9nF#jb0%LSmwYne~+j87H0^+3hZaLkh4
zPJj?>iOsbQBzVu1>1Tw2MWh(^YChdI-n)ip9MqM$#(Qe41hB<fVKVMA+Sdm+s-Smm
zVNdCSu2hx=S={}i8sHP=+$`F1$)VkOV?gUi<jFTTrr!(56Ah_0e51~Jcv>-y70xbX
z&Z)g)1CK(_6pVE_a!oBhy`X(I2pjyTB!T<#2h4SXA)zF7$6D!w_VlYEdLKDq&$rq~
zW%`@WFQs<a$L3HDu1o#xIt$+k(YtbAj`DbmtyRziAc_Zv#c+%BoXY5KUSOkEJ!<=C
zmX2)i4=)gv5hl(EyA6XZMcBP<!#onumgZUbP&^<=0&w!YQ@!{=@;6;NRisXr^Q6J3
zRL!lFGIZzqRpoEF>`LIA8PE8qfZxlX4*uHnld$=D5`2z**I)UmV5w8Jio?ENa{OQ7
zv_x$OP^0dC=~cgWT#6<NBVpw|&k7iJ{btDy`&jq-<lG{GwFDhF9w8hK<a6>FZ}ne&
z|J|jGd~6i6m{=qrPOCeY;2+UHOkd%DB(w0*$;?BeQTaR8xUcr3g)24lX-bJpEys9@
zj|GzC3gB;d(!5Y0O*&a_KRI&3kkL)M?h~*?lv);%35|$buaYzd3(yj)p&$V}D`Fv`
z$?&G)M)9n#H!<E49#{xiqb1F?LgP>RD4?eNaF=N{s{R8>huaWKc3|3-ej5n*C-yX9
z68|X$+u)+@Fd^x@m!TeU2wix`dw^^YHWg;F=G-Iqo`?-O^BjCn*mlp_rXXl2_e7`Z
zcO6!hgIdI+W4+o63Tp-rF3)WE|2ziub3R>ChNE_<JuNl)U}LE#rqc+tx&I6z^10Gq
zzmTeFm<<HxP{+7?o~ei|7CGvuA(z4f#tM@Cpt<)q!*f}k?;2xcN3c)VxrU>0H^9S7
znkXctL!6ViKOAo#?e&;kk#RbIrZbqQS9Kq)_01E>mDkk(K*B#Mq>PE1obo2!mcK^Q
z9EdRVsWTX(?Q$8lL*l@Uhw)+YTdDOklMgCP{+nci=cA-3gFqsB8*dbsZ0_d}68ncz
z*hKrX@0r7-f6;DvyhH5k8~d=oN5Ui2h~y|1<V>U=X@kPy)sGRqlb+&@aef#8wNpgK
z2QQ}<G6g|`4*}`3qn-<1P6+J-%-$?k5${=`?-J>p7^hpOAKWp9JSu5A^Mcdu0;cSb
zXJKtL!7Z1o?}njwoEp!QqarQz1-bTAx=PXz0u#37-w7j$BSXN)DCZh&_YFb-t!ml0
zEsxhIKP3dtr|d+n9HFCwpzAP?PAfjt@V9V#8uBgKQmVpn*$)U7BT-EH^)0ZO5kMlL
z<|;$CJm4Cu<Bgh{<@hlgHL-?4znksRf*YfnMVMmXbb1uh2V_7wZ|0T@L|&@liVLv1
zb`2&uno8g`6=?d3M4ye*5I-l(PTvYX`Iq82$M1);^e(^YtLdFS1<c>SUuMLi7=0tI
z=VQ>6p7}gqws}u+&DCVBz2`c;*$->f@G5!Ot11B6RK*hkyc3eAGPsMOt5Qg#n(A^p
zpJfGZ`<3UjrX&umSBgp#)BDY30!T#9O!Krsx)cGj7xWuX7m+^%Uf*PV$#+iL6o@0l
zD}^{TG=JM@kzN;-$6JM(VWCCIV6h~iLj07Qy0eo{r(IYzGfHU>K|%Fz#>ML@QKC80
z@A5ZG?k%mimYeD4^mF6yjkF{D3M(6Wxkd^RGtfyZ&VUD||0JnBLGF+@SHLR}A$JVD
zCEJiYf3MO?4}zG1^cEUoobn{&V>s;CtS{Q?q9fB#@*8&PQd3(8xP!_1-}8}#dAwNT
zik_Nl#@<FJYI2eGFCX|R<`UeYG5ZyqI!0T!fpv%{oVdh*7si+k)WAojmW>Gq<p}>g
z(|ArT6_+hY=t%_KpM;)Vggj~3BP87PJ>cXNDKyv6wH6*9^0iq}HjBwqRz`2NqsVuS
z!n|c*dSo#*(*cf%P|WT5%<vCK<Ygi3!MvaZz%4)D!En4WqUwW3f-{DG(2>d4p5vM8
zWUAT*vuwAZ<|W`s75;VC;6*6cKf*%jD5p(Mg8!zmn1N&t$UdeDsAxvv(+YE{t8(qZ
z{FjUtZSnYrl?t{1gSw^FQx--~1hUwprH&8LJkXl}FO_|J*1YzJ^Q}{Cmu#=9pCL~F
zHn(%@oxqda_<jlN9>3jjjM=ONm2!R;sF=0~En@#V4e2P4wjzrH43Hm>>e$%wT{pcG
zmN#|nDZ8A;sCv>mL%USun>0m@PIbS4r$d;7cLw|*R4x~{5R;9#NGTQwuw;ZNoJllr
z#4<_38$DFEHcu45<hiEb`Y2rTf{O7SB#psjMTK71>ONm$boA(uuo1|_5*36pniJ&+
zJYohTmU<J}zHw}40|zzOMzG+ta7=)#F5A{B291uKB%(>B!*+CLg?IY8vud_H78MF_
zin!64;9JDrXGu{VN#+u<h*1ph0%@Z~=<rxd`QR6X`L_<zdWQ^e<qXhWjxSRc7ecKk
z@fR@}Jtr~)+@5RJES&lf;(@6^aXHJAf07GiG8nablJnBLC(MR%V&*YAG7PRSciYWe
zv3iL>vGn@VT-EP}kqyJxw0Dz#LIH`B7zdwk*+(Sn2#2@p(2-4&f-nYpZu5>z@aq_3
zL{whe%%L$l?&|sW5ZP96L+tRoLovj?p2(YQAV->sD!#VVzD(VE!=2QCNfsnndYjB`
zPo|Z<uQnYso;(uZGtaVb9;O80k#e;A<FVsBg1H{Cp&Kbs;pklnz$^+2&9E!Y8&<!J
z#lCkVq43CV^LjE32z5s8AQ(!eXz}8gujG|Xp)1Ok9Cf8|Y!C_i@K|kbp6VSY;52nt
z6vfPRO}8~HaFv*@l!<x<X3?Em?rH)rU~E3h_QUF6VRGvDQ$1y7nhP-aA_9>ek+%l+
z*%_FJ4ZHUcafACP!lX5Sa$2l?4w-;BW-#We3yDv-tMA_Vphv%+3It!mH6Lz)p#*M=
zy~a50l@en4-SsIDNtef%G>CxA*IEVR_R_k72qrfZZX;7((9=8})~Ln)mI-6#hb=7f
zNZmS=DOLd|*qTs&?6{~^?l@J8!Xgm#P!==*EA{a-whb(C@jLvXA{Vrim~dVsuj5?@
zu6dsEK+1gD+{haE=oDOIMi(~F{(n2VK~3vyo-*K&-&;=w^~9gLZk6|0Nt5h&`wY@|
z>#T3;(a)+vYL4qP%bE2*)lfMEsM3T+aq-0vt;5mr|4*YmCB}0Zz;XbxYIpJX7P%R0
z2^49K^YBGZaG#UZjO=MRBNhK%`HAnSU{B`1CqH?FNsE){ZdZaGn5BQWqk<W%TFQcE
zXJJQ%E9V6%7&?{!b^_&5gzs-LyJPb1w+<qrj#@pzFCZwvRX@Gd-(a3!)*__(F1vS(
zui1KOAv$O+ZAljX>)u0dC)lOaS~uzWwI<-cqjM(*)IpL6G)*(R{%YCs0p49>-GcoI
zm@1*2<4{3LruSj^M=b*8PMGSep0&6srM#ayRnW$V1tir`=8U=$V%s=2p*}F-X^)u-
zD6;myKL<6*K08%lyFUkds27kccsZypny=0HL(0iG|I0E(Hn0OZTRFlF);a2)oeE1(
z=cxkDlQ`*EMbY}c4fRb2!|?r#S)!oFly6GX^rthL8439PxaT{kgL1LY7AWFOtK?}C
zq5Hfyxqc6s4RoR$OjyAlF}1C`6+czK=9Bt&<(dZ!(*&aOMUAmbhEpao1N#w&EP_o@
z^a%HC*@>sKAN-^lsL~(3vQ$dARX?`(2H!nWIF~@JLszQT^=baEHr?@1UXBFwVC;Xy
z<ftLMU$ZNu^ra-;0nE|Uvv<tfoc#6&ly1T(iuzK~TGI9`sitcN;j;)Hy{TZ`&z#w*
ze_>1%YzTiv7CJ@gk<X9q2iy0Ge9K_0hPfk%Ggh7_tqR&n8xe)$I<dxmzdKS7EuyJt
zKBIJu?Z<dWI}l8Dx%#^X)6}eaTUGPFTrSD;XzLDpN6F?ABxSCQJ@1~V-UB@ZRbf(g
z?*n5OU^?I{j~J))bdae!|1F9^;|mSPh^Jk|ax(-*4Ietp?Z2m0jO0t^j>m&pteH{c
zUE5MrZfaK&c~Zl)jVwREY;^>%qWfF`)K*<vMT+;9*D50nRYuk~ZP!{H{2syHrAu<M
zZR%00eEQ@Ro&a)3f2MTR5X>?oyds+98!DoOfwvYaQQuSpFIL`Wo3AGBlA<S5E%(`a
ziutjyZ+cBH8y=J;Io4?8s#>VDfh!k`6a$`BwD@4f8TQb-OdavT1W}Imibe}Fv34B>
z_qdDEHniy$ks}%X4m4X}-l7NGi17!;%FMDXD5Lwet(g$a3&PO8^!vsD&o9kUz?g>2
zAMV^T>S)%-KEH@CSZ!NY;(V`&4{CMJA8=Vl@Z#u1l-SA}s@h85w8(x1den!E&#%IN
zGEmQiVPp_SYye8!g{ulBd>S;QQNxw`15u705=vNj?bb?9?93Dy=_a;6U=50F=<-#c
z7hUA;ykzP{o}RUQGMSv|zOPVHOKk>yj@+Hs@oyfodd5-utKY`S_iJ^&d?t!pNeI-f
z;?Q!nH9$I4>4D_g8{;fmpMingmjn3bdk8U?rm1|&`<cB@wKjNOZ~e-*iugTpODyW=
zidL}235zW39DOj=TPBkSpv_&lRNHP=_YWKy(QUmLFWlaR#V6)4Fi%@rJJO%MnWbCn
zsiU$0KV+I_LCK1(Q9C7QN0XoC<}KPw=Hw*c>p!a|;d~53#ghim2gW;oiC^UgaSH|x
z5@R?Z$&IpDgHwd8y~yv;`*IG_z;KavsYRN0AFG>r^A=m#p#bfnOn?xlfl306Ph}#<
z_T2SfIl&9NtF`K0uvfciu7#(>e@ipklVlGq>#fh}UUg>C7Fl{P<S1Lf^CIO#PFlQf
z$A2XF7^t&xks)0NbAt5bD<t5dHodk0@s~H%Z(fi&q8-Z$a$KgT%6|e<Q$))j+RFIl
z@k0YbP8Jx=3ud0zJ&aP$`IHO(aVlc0)r_C$d$pVV`${pvp?L|=wTo`LONvg_-1SEZ
zg?gzONl-Ml4%)1x5|Qg<zRDrdbg06_)(uuYzAKhp6n7WzAx6Ojv}n(fBnl%=kr>WH
zNGO9^|Isdh(2(u$laO0P*lmIJd(=GCgZFe{Ax|eO9h#K#q9p+1vBqp9(Qo+<lkXCk
zoihJYD!wAjs5<{OYbA$3#d^b%)$94Y8b`;YeOCrE$679YeRza$)l#zS4TF6mqe>Pk
z5PaFLq#Ppy{Q^_t^};55ThCb~x8a97aEaywi(314N1?(*^imy|5tSIKN|3?nowIMi
zmG_inQxXZ>PKSQSP=Nt45%z~dcZ|%t5Pq4Bg}j{FE^saEv_!Hi(Vo^(CM?|ZT~*Bs
zx@aCHjl+|m??EN@hT8~++g}-BQ&<MmG(d^3`Tma&^`?OWJ-U{~oJEZ84%*pshH=}5
zJS4jX&@N;2r2<%phl5k+*m;7yA_Kl>K*SOz<`x9?@~rO$L-Z=)-UVH?@6|sG1ITY1
zm1NZe)s|4bg6cQN+1)U&ItGR^;4@A<>QJxfTA_<Nh90X|{!oo$9QxsHiQlHB+RX>y
zu6yH-NNdh*Jz+LF-@eL1Pdc99XDi5z9WdQb5*HPne4bX4`CnE><9%6`LBTz8l1g85
z>kXcw@4|N(hf*WVQbHssB9?XLO?Lm(%{G~EaPd~I!1NYOhV94+`5exJjY=1Sn2U73
zK@<_fyRyeW-RUMNeDArOACNv@(~c$*{V;27U#QRTGQ3!9nz>K7KPQ>3f+1+;=JbL8
zmi3F9D;B*FzlTj9O)pL25TSABm!4J@t~>?ltfeEIRQJa-JNS3o{Us&`ox$qc_6Ipd
z+E+^7mGWdJM>=qLWKMYkQE2JPPTdc%xWl6FH1NEDNwV&kYjzueaoSt#IO;Ar6=<0d
zVRj}%=`2I8sQ0UyS%YPS<{wE~&rzW#t&*_5XLi+pGa4c6OYCz$X??U>$PumB&i>d+
z;rua%dBFfdCmW+`8P$O{$X%ZH#3O$gVP{aXSQJ$2A&!XCH!$QV1?1^0q_vdg!EgZ;
zS}5Aim~5B(Eo9bqxk{6O&suKUCj!%K$y;gmH1#cOd>5h>&6rXv&*j2jS9Sc7+VNGK
zFq*x;m)wvDNu!EKbTe!L1xt(cCi3>~8o-wFV<KS)y=+Qa0b_lbK#Ie7i3`WO6<T@i
zJo^5IVciCxKsDEAgwsVMk-lEd3jsg8@$=?sFyIxW_o$A>eh%p1sl!;p%M{Ul6otcn
zb17tw2YA5V`cS;+8GV}md9~*K+4a@X0kbvfXc0dK&8CgeamIpkch6fUVsV>6=%nf~
zK@}Lal_UEwkha#MS&LyCVYWj+6tsq}(PdFF+*0f(Fn}cJru?aUN7v;5BWhbx26*xZ
zXGU%2Xcb4>>P?@m*QnqknLLQr)3Gc)9?goTaiY=z9-S63>Cf=O-B=u4K<o-!=Rnxm
zp6&%~%v8fe+Qjjj#+bWXeLhN6Nm*boP?W_1D;RYdo)~$4?VH6$DqWqIzp~eAvIBuM
z*BFAbopphG#FG1gCXtGw4FeIjE{ggy>*4M~-H@Ta$83}nJ#wUIe-`4&L8~XM0J8fs
z1B~1i@iIzSC-gKpax#c_tUi*{M8y$4z=y`sQr^}_AQU6jtnojgHmovy+*a%3!}vQS
zS|#xUD|CW3feFvwOfZYIbKNv8G?_*^g5**i!r<>X{{_8pE}F)be37;Bjqv?d5GcxU
zd<n6M3hYX3vvAqZUZ}SnUQE+&o-$K<^W-I23}G~y2U>=!>q)a;J@7?2@J1Eg5`&M8
zD95`fA|5yNHzX@~@<K_NQa~=!R5fUhCh0)(V+XT}N0_6Nul9^GN|D3bG1~QwvEMO)
z;ct_~MpRgLOe!7I5%2aGf?{AQ*tA>Dz(6Z_7sk}4bUSyQR23Ohxb!9bl2cl|JCkbF
z1c~HNiM2;9MXuwmX#H;sLKmh$i`?M)_jMcrDBAvUXi~V|AyZXl1=!jz(bF9FcMRWP
z#M911f4ZKTx$2-Hda|Q}7ANQPJZ~;yTB)0H>O8`x-23#DRieB^_Bz>PDx#v~6k>e5
zI0>iT?Tx{PgeF;DHBsm0)SNOynYtJ9ArnU(yT#upk0c^^Itdc<_4Ymvs{5#`N<IC~
zhAgslKB_{{sx;s5_b9UE(yKMp$`6b2VRSbfIss$fTl>SkrZU0qM7XfWzs}BBDg}yT
zL_xSx6P)TPt)z1~0ZnPmt2)Ga8?EBb6sS!E*r563wZ?ZAU&~9R+z5aUZ#pV<@c!rM
z=TECw#vEdueV<E-DssjT%2yJ<-<XOV-S8C%UhVzwjQfjDxc%`4{ct5g{Y&DK+UmUB
zL@!~SdrH}oXWKT|&!_*tz^WW8@^~Osl?uiUx$;tIxSoP)0B8s&pn~}5XtYUTaD|6Q
ziJG(M#iy<`eIXb!Cu{lK$v6BXw&8dqS$m<IM6>ct&;p`630B9--_2{sQgDQs%6;_}
zFRgbjAf@D5h|)ZSH&QR9gns%++CxlDlk0p}H`{9#bhp{)RXqSQh=04aS<M6?PA=Tp
zagN|B-9#_Z6#=P<A4mn{KkBJx$%(r*-q3QEsrdAvy7X@PR_y<8ow+{eD@InVQKkde
zN(h+oUTO)+HUht4O#J$ftZ5%_Y3l(v_NNpn3;~j`;?p`KKUccvyo{j&PJcS*zxs1L
z29nb1eD~}iE<?ch7?8x3RQNlus|coKB4=XsQ1O1ybNA(wwH)&twCuDjoG}@t_rYo!
zez&pm7#ROJsi9w15hP0|U%ru?3?P~JIv>JkL1p0!tI-j8N+rw2qXjo7;Ka=p#oCsw
zUdBuEHP|S7#bPR4^%OknTAG<GT2`Wde6Htm3U7BEoU}S})0i%birMqHd&w4J_(K#4
z-e||C6Sj}FFvma4ezNihKg4vTui03^Rx2A+l8tW+gXA4H{o!oXh-?#}u<knlHa-N(
zXayBO)uN2ggFUZ}CfcW?jqm-6rjdO#D4wtR+A}U3K^$<2mMC-*1KV;GuTr5i8X}l6
ziSjVPuTNa->jcWfy|59#T=J0BVTrt1e=|(&OqCz>PW6aRNX512pM-KTRdS(0YjmKH
z&NDuNpKPT&a9L*#ryeLFJ+$7-#`iVPe&-{)x}Hg@HlP~d=n`iO+WWyF!{Xow$&oHq
zKAp*IX2l6(uxu9X2JWX=$BUzYw{q&`Ydvj{TDMqF<@&V(zkIiK`1M-0=)VE%v8(KD
zPG4;;ig&a{bAl6R0<ru^oij5EEw}q0BkKOVP7>3@D)y>x13H|5#XCKvlOeLlu1SU0
zh$2w8N_&TAmYTcf2;x~xq+pTHOwh>ZwEA^+da*`Z1(%lZWcSL$)33cMUT}u@UxSbo
zpwDeC7G(pM7@;m>nICrW?6ydV4ljpAD+wbZ*WUJxX7Y`@5KviT8WrYZ31Upoa}~|{
zfR^w#>PRVh&>8^61;961h-ljHK&|56nQIRmRXXR^#*n)CKX#x7%Gd~X{IY^|60xaH
zBa(~W@$NB#rG?luStY^)m#Vl;XSt_a9k2hQBtlG@4mG#D%c%+zgPXD1o%?7Jg4Rkj
zGd+UamHKr~1O>0Qr9_U^_DUnTYQL{iQIJHf_L2>g>IvkDl{RPu@9j_t8~dac3aZUZ
z@*B{f>0&VtII4d*sU<}_WV(~ZGJ#Lq%0FG>0@ALGP{X9zE^!a82scDyl<REA4MK|m
zGn9uV9#`pxto-C<Kf$FRVV8_^ttQ6}r(xlN4e9mq_1LV!`?TWvsOT8Is!x25epX@E
zXSK&SZv)%%cU6i_>lZq29hHp2J?NUepIqXIea-Z}dqR(~Y2p!cOe{q5(>6GH`iYF5
z2YP{EsuJ^H(m4A3S7g;$t1|RH(=4b=1n7J(#9~WwZ{*<H1L+;EQGf74ebeR&Q56KI
z3tr(EQR^}wro6QCbd~UoNRg5qBmdu(el^Q*-;mv@&vT|G_WfqtV5=c5<DUCwZt!-a
zRX{c>Bl~yX^~d|Bz`1L9*ODnO!PgrZygUn#;*{m{hXRz4a=NW^SrEZWQ8!^?2(ilO
z5eNVt_^3k8RusW?4f?1}WOPHdYSamr>6(IkP{}idG_l|o-42>MX+Ee@{>>xrlJ&Y9
zTJ5@V6!VdYGh)^EjZq$COv!iQR_PJg=2+i={WCUVr3$)Y294npc*6`<@lY}P@4->L
z1kPUsFc3OVm}4Q`hdN-3@SBp+|B7e+0~kc*P#{(aE%ILgHz8#1VxUB#fyu01<ei?M
z7y=RFJ`7%)Xoe2Zv4kS%3ev_ET%B(OBNN=8&MTomP)aKrhYa@^A{Gkb655S<60*Ou
zK}PGwI_u(ytz#hR{Fy=T_nwiY3ikp|l{Sp@E;)OMhDiXm@@ZMoB)<2|ZY}U9L5~(t
zvot>!1<t1^HdVt-Rl?-C-PWMC#Pz_TG=^A0OS~QuCDHZcuk2~mW<?Q@0?>(FCMP?J
zPzL-zUO=k=CM^*d!&sph&q5&>bhdM$McmRErOGZ>)5Cy#tv;)%{qP_6jpD&^3ZT-f
znaEwn@vk@>L24XX=Tk?lhz~U~K_^1g$bC^!+!HwL#9OM+He=22D2_CbrmJBcF<u$h
zB$_9qffvtD6BUU;;AJCU=Z5Sr-RQ}?lj_3-<ST=x!hM|Qpcm#A<yH(GK1L&hH%w`D
zRJ@`&hA*QIe$~D_kV5RW8H~3-<@+IHp!wF)CG`<OB!cp<-I5;Cy-}ggJBeRN&?E^}
zYbqTEvaO^#_TP6QF->7sr^dJsE0pE6x0aACSYZR+0Ua(U?E_e+t<nCJwwgJWkUEi?
z*}B^>O+Q5+ZU6#lixUzj=A)TRw~SRk4R_7i#2mlJ;T}`UUze=zRYm=k9e=ITF92zV
zGwaq|@O>98iaES#)d?SKZpzO(t3RnUK)%TJnKgZ?z6im=^kd->ZR}5%=p?zQoe(^m
zP)_E{xlJryC~>5)IVasrBLDtxuq(7_50HGK+@qyxQu&1;@M|fy{V85W(<`3!Wyg_8
zoFya@JMsb9i-L~7A0>wvV1@mE$OsPyC498aE4^;1ogvVcNtD^TV%4rUHVP$9p{@Gq
zJY4Cp!d1IddOsA}tw^ONhqT1Tmf-N4<Q0pA_Tq%k{|sOTtv=G9il^lqIIB*VQ_k1P
z!d8Gnh>V#JES~&d3#uofNYygIl$&OHb77~M>AdL~AuPgrewD&D1Yulvq=1^n=kMf{
zy*^7tBZ55m(YNi@3b9^b29SV7C`<QteII+OU2%BrQ`~QUtAq*^4DK3{jTHM`zn%Bd
z#E#W(bd*J*y<P`%N%De3!PGw4+BoD~^fmUEmq^{Hn4>nK2h{tZ9|p$*#Vs6Hyk2_{
zKa0_mc7b?NrEdIEN)qGtDQusixxtZ-AM>dcp(fwTnH9Ys)D|8<`{luS3%=_Ezt77J
zQ52CCU}~a(r>xZT7g|;UDDp5*ln!omx|zZjks-ol^Z)9=V5JtF*asn-hE7!QUFy*w
zpp5MwuhGOf6X5E6Ae$y9ZcE15VewOw+zpuki3{R`QMT0XunEdhUX#gD;3EvH)i7Rk
z;?5Xm1{WjO&-1`sBXft7<!+-HeHvIl(#$)O>nrPSrQPlgDFJ*k0h-|PN^{LDV}sl$
zG?o6VYBV=AOYW^-L?K2AVE@BH<rPG$f{6bVL^W5&dwWw=k8khpKsPvzpG8<zbBO;1
zJ*&U}_aMg$pi)>HTpI!j!?uOw@}rQ+ceFgzY={X=nx*y4n^?Mx>i|VHM0=Km{s#2C
z?Clm8-r^ISQMw!(KZ!*+m(Qjy<WeZ^T}v$r6swIg4h7+0YxyrG*0T2{5ZMkpag<%i
z_BO0Jv&P<sYNgcnu{){D=+>eO8n3Lda1!rE0=5oWh%D^FvDzg?jkIx34wK3X#7f1a
z4PlHSbk0$ytY!<!$e9Ktu{6Ti{XqH6B7L>~7LO%9^z0ueH;EmiJpXpiULo+GUEI@b
z(n=xhTc^|st9|XL{zA=zURDzI6H>q7jBu@(;DgP_pc01;>>A*i%4c2nTc@;U1VmAB
zOVP}*LKYm&2ceFcJH4?#rBYU4_RJkV?53OOCTgruH!h>|{oF=+X1sIR$bD`lq{-_}
z<(L<Zs#BNms=@0y8-HiA-vAP=CI@f@tF2w0@d381fZl$iES3a2xF0t+>fUn7E!^Bk
z`z}2NxaBt7#V71#v^f7rmLyC|u)A*KOb6|(am5C>o^}&aE=d9u^rB>~Og>w`6d_2^
zI^s&0Ecr}R@V3~nMRi;uj^ukPT5Kq8k}3N`Z17&Sn@*0B(f|@HpdEmQ%zA1A-@*6l
zIe*c(ti630qu7dgJU~<leGx;o;*cmvoUxm`U5Te`rZQu&^_lORG@10G>uPX5J@P|~
z)!(?&xx?wqsLoZX6P)+(aXA%`_4oh#*${@d#vxThM0NRVN!E(wDIu}#lFrT66maG3
z`2S4LAW6dilxGGWZwj(<gb5tDwQtaVvaFD49z6dA<9abGD(QR(u#|6ho&0Vg7IyGZ
zD%T{1VPkDcITeHYv-%G;B+x2vW-IS&IEbhBWEjuFWX20!0?91O>-bQe3y0Q^!V17+
ziZ$cfb0NXagtbh39w?m7E{#8(-_7#}C1p^y3)vGfn-^d=0pvn01~Lsq2Tk-Wv+T;^
z*03!3M+}MV=(Tag!UtMC(^D*(q+wI)p`>*`6MzEpC}K1`HGsH7P?)$9^olyy#xY=g
z^r+a0l*Usq<Qj%^Wn7A<=GRQZu$axX`*zDsqD~yMUSKXy#E)orf*DtN87c8gFgtrr
zS2#F2wVMB+!=-5c1`j8nkE<Pm-edU7oWV4MyjCK01hW6XF~{Q|lo~jCg{m;_??bFG
z@%L-+OEDMs@T)bR<V~$#Y^rEJBMjSb)M_u?vKKucD#+!EoPF+fxi*dJUAhZ@l=;US
zfsiOn!S@9BxH(i`&U-H#oyxknbq{hP?~=0pWZ-QFcIwQ_GW@;+%#&v86Igc^d5^8H
z-uQ;S$vnoy{6D)e%8xoYDBK39VwNu1+0f+_vL#R1ZW@VYTK}32*i`T90BePaEP_qx
z;uioHmrnZVk+2j&4oZLKDuY=3pgP$$fq})YT4B2+D_eQ_N5L(i!r&glyqrk^s+Y#}
zPRZaK>XLnX)2>GXhjF}a-OXKA^15}Zd@_q$%}+$XjtIkUw<3I=Eh-8#2rPn==yF?F
zv6#cqMV__TP}ZJ~uBc*#M>Un`s;4&=NQyw`HT@7`l($KuI1WUnThb0w3W=%jYWI8J
z%U(a$=JtywT>uwp9DJkAgJ@`~Y4h{`hQtC3L4yt3&{+%)u$=tW2@>`fpsWG~l*r}>
zM6CFEQnhe%9GTwW0gQSfOmf0{ileHGC6!(YB8qjx^P8uHQ6G<dLEQr2)Suu4gU2mT
z6!VjyJ{t(}PBJYDE<Uk_@bA$e@h$qZ<Xg?0d`R$msEvfnK(`M@jc5X3=Smtj+6o)}
zal@u@(gokfGWXx?1)3eMai>$E_cX5Vi<BEVwjg>&yV(c>L_16XN$P^p8dl_bJyNJM
zTz&809B^ermJ6mjlwxG$@<^BjU)n5u)LmH+hi^&@U44CG2|a_PlQK!hb&>gO7wRX$
z2#ldvDMh>z$WEbq*Rr>H4pgX*o&w~7=Aq?&N+BckAfK_7i>VulhJA2O$yQt!z-4$p
zJFd7VN(|bjsWEM|a)QLz8;*h=*tZ?|eYa}H1@ha!iv|kDP*=+~x6-<cb7XiAP-t;d
zn4JEi=P-Cj{^Lag3L~jk@DXmv69CKU-SLo&vf1C++cDs|!P#*IDYjs@B9$5vsUb$<
zW%^G}Jw(F^1-m5t`M1&X?H%5q^-cDStg;c)oiztsL`&@@5)VO>Q{ukmk?@dIcmazH
zsN^1yTQ1hEmCVCWYHPZ?L`DS{4fqj<$UnaoM4eo%Y&ay@C@>$?A}7-}>AZWF`oz!x
zP=_pLmZo`YtBib0HnUQNc{r^xX%f|xYWZG(LxU+Jga<lA(}bF<2?pTChlOlA!^guy
zFM6q;t_E-%Q|q*_>vGP0=g1PaC6x!5()V78tc7~=F{_f)(*OT78DI%}MESw)8#M_z
z3i|K%Nem^C<_teSls*eQIhMO40M{A?Q*tcankId&Bh?yH$^DB85){&!_}K4n+)waC
zR%>dF-Z0%6>VfMk2uJn2VQsC7TkNHVuen@=?@&ubcm9od9{_2ZDx(BC{i9gsmK2zI
z4qe^Xyj|y#ckuz&D#|HueRZNE)uRD0;y6K3KgLz8r=p|BqwzK*ABG%9x6zT2YM?^p
zEkob$j)PaO^BC}`w|#EffOd9{zJgnm(-gitSMkR*B@E<92dww=&+X$I1b&w1|9xD4
z1M!jD2m5?2BEE^Lgi<F9fl(GAw|%+h@519%muNwmohLk_ko5|$P+HwHm~fHfW_r4n
zpqF5gH7GgCVhiRmIk8ZONuR)3Paq%|P$fSYXVQDqX17BeFAD>5zJ}j^KCBmy@>e~g
zjtp%NAzj-T9;qa~Sp<8Z+WT79s79USxdGr$zAZCr#YZ_f?=C~jONEU5Xzk1gDpKFr
ztzugkrOzEO(VJYD+8es51CVAO-MPrw?RTd7xUM~X=dielx*MC1xsBuyvSwJ~R>yEV
zPlOsh*+~juSIcZV7jy({m!1=~u>rv3d4|l5akMOO6gV?a|BV=Hp(7f<0e?7S+>%k%
zNWt#5Y<y6FMRV$ch}ZD5pDp1Pxc>_%j;_RB30{~5pLx4p6md|eG{O?VWWyj3#p?^1
zAGOfc=$Nw4P@xnX#9f(`iHg6cHD5B;M$q?{tI%_Ye?U=C#-u~_)Wsua7a>%R#}BtT
zSpOh8n_X`?$_PC#UkL%Gh>RAe_|MDQ=b?0sKElh(1rFpOCPpESe>x>Iz5|0*e&B^9
zzdhB~%%x^YmRN(&u#*9v<7vjw5X54j;lA~&S5Np8qxLlVR6uo;u~T-Rmvw50J8VTQ
zM4&@P_`~J2bX>JCod-C8NEQso{L;p$8ik^|+T4BM?%IDMGIlXjptx8$O6j90&3I7l
zE-8IjBTSXtQ~iU$w>rp$^o>o3{o3<@6_Og~JK?CHmtkA|0)D3mcTZwjE)1~J0IZ%x
z^zfk~Z~PZJSRxuriU)MUW4b4QL2?w3zD7t=cxy26bcdD-(49P6cOR%98Umpdp{K*P
zQpMAjNB!gI6G1WNBs3Rhl(AnY99{S5;48gqx|P+$FlGAIvm*aXD1`)AX$ij6CINBk
zo!sns=So6{r-$_BMw<Y{(oJxtSvh5tlCQIJqb92@t+xNx;hF>VB!&DB+^WhBr;0kn
z5*wz#=ZamJTWC*Q3!{)<T`-KYvIY=ZZ{068=0{nBxXiv1L4`<mF`{@>i?k|c2#Eu6
zy(m_tksCs0rV=Sqeat==?gdJdyoh)kwS9EP6N6(wv?g@AXyVSP^$d@^f*Bx<hGDL^
z>i(g?z{-ZDb$>V@Rosd6*)cox*M`JC4*K?x*6?z3l^LeW?EW9c5K@pu?nG@tEs5Tw
zfae2aWUI$}w#cfsmx(0Mbvcj>D$5D-6w-0OjWhN_U4+1M?$K~^$vs2MYAsp6az0^q
zpg~gju$QH<CJ@BiSPtSzxAs%A_vI4ANL!>&QCWcNV0Fj%l~P~);yIoy-|~i*uckra
zN(}}<ZYZG<Wd4WTGS8hM4xdK#4<!nkG7P(IwXsRgl?Ai?9vbZ9wAF3fhIPMA%|c9U
z0YxufDFfK(f1rKg$4C#(y&b9Z|1Fr+?0+{p;r|q%S^D;2sju_CeQiML;5mz2<a!A8
z9vl+fmVh29%bb~54g&hZdhCS$v3KdreM8W6F7XnF6C_1(<#^yp;EU7p*F;-3%|ba)
z{m*OPjo0g;SRD4)_soxAo+iv_eqvq2^$-@V1PS-MmbluSAV3#wF}ao;Ai@J+b;(sD
z9!|tBzVsseerH2*M(7dZ>gq0YZ091xo2!%d&#=oVbOFjQUNa3ZKAbQ<F-~2(8<c>w
z^fny6SgfU3^w1+w)!b?{j6^>V&?~WQ$BFU4UB~yx^G)heJA%H1_zvH^yWf*WUo3Uo
zE>#kfWD|9qzJhhDvEJ1ptuYp12&bW}+Ecztp*^lw;{mS&ClD4yH-s!>rsKmwFY8RR
zC}6NJQpeT>@z~>K>Diiz4eDwjZ9|BlW~-rF7_5R7%Wxgk2Pge=s-Ti-MUjS3RiD03
z`@B*@1#on?f)2^S*Jc{nPQ8>6PLWvnYBW{12W-}{HYN&!I4=}Mc8k~K<C;Ca?aLuW
z^}zXO{W5g|F1Fl;`~8zR2iaEqSaeQ&-He1GRGDLa?+b*BW@WB*{DjP?1>?NXY`ClK
z*q**RL$LaZ`B>p@oln{#9>J)iVe1W&e_2je4GA08e`}w``5Q`_H;H(al8=R7EBksR
zR#u;>W{RS~zWClXNUsv&xB!m6(2qc8yO|%;I!vBNKJxUp<qkCz8#Py~()^+*O^f51
zaTI54zJC%|@9!5SuuP^*Q0CKCpwyz==FRP(2guCho`$l_%tY5yx3r0{oiCnVcQ_A0
z%~84VY3WppM!IcgMsALv7nWUM2un8B|5tJdZFYrZb8NIYn}9#&6=1CztbO}3$=%9f
z;I{cHM)_izBZ_>v_?f`4dBBz<t{a=WwjK$WIhZyPX-ww*6~umSJB>;ue^(YN^_Gse
zin|(yb;VR)1NJ_bO*`6RL@*3c2wz*I>J9%-uMU`NT5Kly29aVYZj1^*AtNTYrNSNb
zVY-<FFfR{@4RUEzEkoUu!|V*|2z;;dVScFat3|C+$$gT1V+p7DY!$T)$HF?aQ%RM^
z_qc$aJ_bHArwIY#{@nf59TY2z{xD2_E4Fz+17Cs(;OrVy47NttIzC`49kR<`4^>+W
zM>Z{gU;L5%5n`Ef&XdGiP3h+t_5Di1T>%29IGG_ZdL922^<i@l<sJSPRi}nj%JJ)w
z;cPd$6Rp9gG4A#8#R-+bc|Z`60A*uE$87ecd`pj`z_x}8ql=FJ#^<XZEu_9$Rn@jc
zpDy|TJP6*rAH4r0&NpAnyB9=Z)1q;G=hKcSlnpx)FOlmE?pdLJ9*3Jz>my*5?Zydy
zsxzTw(N^*HdY?BK*sR<95VP<2tJsq4i9{D8U=9e3FhIxIWL>J^=rNil;C=GniaiiC
zneP8EFI}{~x+|IcxwJoC$QAtwogK%+p3S!!_a2r(KVieA^&ZNpJ+EB^K?k~^-#EvL
zy8F7oFd(eSZkisjGQ>QPm>w5cR8)}GeQiYYuru+@a644~q7ScsNh$l26k1ia)sn@L
z<#dWdp)>=1_J`o%>A@iJGx@B~WtTPw)59EoW*>@5;9O-7GY08-voq7zW-P#F!rv_{
zBj@VAM7^Yf#M;3VY5_5t?Jz9)eV9eCO5{=J=oNpjI{aB``5&WZeFU=aX<p+%tS$0o
z%!De!C7@V2MG3nmROCV76z?kbH!hynzPN`~>`N1!1ndeudPu<3RNUhW+zohaHrh|%
ztZV-`qsUvmUDsJR%i)790CmXuaKv^ut$*bQEmm&VTx{d%+`m~Z7>7b2aA>nth3EUI
z@Qy6Df?2-xM9^c^THb9uIKwht55UQzzidYMWt0G@cryY`cHq>XRUzGuP(qqP3Qk;D
z_10=p3f!*5pt?{Xd=X#-l-FR#UT{Nooj4NrJMn)AAw3xYMN!94F~2lA9GYJ2;AscD
zni{(XSWG~__}8vg;q1B6V-<fo94wJ~9e$;4r!>V{bY95H8D=Lxb47D?Ir1ixoK3~_
zx>%!J)>(<6fvjINvo25i)qJ;C#jF*9(DFt7t}!NzK$m%3JT|z<Tz?WRU`}-jaL|Ao
z9=9$mqKDrE<J}_pZVUI57!+6mC@9z05Ovt^>bxEby`WXw|0fV`{Ky`nEeQ&*IIN?u
z!J9^)%c9AkRZ14CZAZO*d+#BpV!-nJqdf;K#UnH0Z(W^v$pt29U3)d!IRI`f;EQ*5
zjfqJ1?uKphJL;}R0IQPwKc`cah=yM>*ie7dNI>05b`xT&>voXkf_G=-k#^zVDX}yB
zd1N?&FRq>4${%h8PQ;!<hoqQ#^^AqJs=Ac!a6on9tBZ7-G%0n;3;^DN?PLPO8BZGt
zs-dyHaod>pD~1?uLgdE0<<SPVW<xH{>Fm{OV*aD1dBEB1&BW>+n)2I@`O8|Obm9(M
zj=4&|ur;K#)_Sn~QUXeVl`ew|C^S}0Meiq{#17rC&EOq7eUddZ<ppbXVlLzCP5Iwi
zC6PayrR88{t5Ko;-vnAOn<^Wde;K8Z9XCXjlNnkVUj~l@+4<Q`#Qx1D#AL!3uhA?)
z^Anc61rgkMp7RwiqUQ=_pC^~W*~uVQ`lZMOOMQ5_@%<58jJwwv6%2e*4j?6TovcSJ
zVkL~{*gHJ~9Oy`qU=1o4=w(X=rwlGE0M+2UXr3Dd4asZ*ww(a~U(}tFPG!G5xg+?D
zT*;{q4-Pv?Eh$Vb>RItSmsrlug{T?S;3=qDY_4lHmd+E8lT!6);X=uhHk@^->87~#
zCv-Z4Z`l_*-#LZ@pCc!UNqLk2U-%dGqXXddV~#K1tlckylk3!4%*0{~n$5xOemE>A
z8Nh#N8itT2fuTKt87#s@II6-u(Yfh@p(-$e(=UX#$xV+^AlhmfmxX1~{Nei(*bpss
zO_0hOHb^L|RY!<sEZPoYo=$_bsCex7eJ<3`3@m{9FA0@q;`|?GS66<eKEFJo`R~(+
z)dCwO-Heij?j8CfGZTrBCh<^_nZj9_PZ{L`L7@886au2&fI)MX!T_FJLOUh$jD3|2
zsGAZpb;BNBo!K`NH!a&2Kk-*kb)=+1rRL$E7jjHxLspOa=UL%DD-<h=xu2$oQ<~~D
zFy=24w(KWe09uNpQK1)+k}#yr(Yu=hbqyyl)b$2>(mXye)^>vvfU3apc|*?IEmYA%
zIQ_M&UyYIBY+NZM?=;k`2xoK=7tQs$P3}IuB&R}FpWgneoV5T7&QBqGdc*34oA<VE
zX)2c7N_*Fc9MpXo)?qv+>`}F@kemPeMiuCbDc+I|>k18=>6svEEFAqV<#vacj%#r&
zZh$RenoAa$1|O4=O;CUqnN|*Ue^ck9{m{6+!72Xzh*BOvSlmB<llNA1DB65JI%VNt
zZP+YM6W}jukwsa}=v2&Xh&lKK7h2i>zUG>9r)<l=Wk6<q7WtU@0u|ftz-D%#a!`NJ
zXH$~X^JMU5s4R#<?V-duxHT;b(Y!UM6_Ylp4-{g>Z$<l1e!^N$<D+3CpUTWUuzB?!
zqoC*iyy+~_PxS{}=Il0!s?D?@B9&3E87ZEIG+|{CO9JeGk`Y(_vcRK^_Wdd@4V3;j
zs?O3rrZJNVSB3#v>m(10CyUcG=_ApNaF>xQlsxZE@+cUXibNo8eo)|W*Cm!@`1aGJ
z6igRTO*^70{S)qpnvXLE@Bow#+nI5R#F1!YPju}}0z<dIGm%Z;HGSC!JbbXeAnaFZ
z^i??wu{a&!U%RHZRtTu~7+m!6g)F=wEts8V*Z^Eej*s2p45uz3WDY!}G&%2LG&e(y
z(RvDK%~rMA?>j@W;P_vA;63tb=4|P#fJk-JlmEK{oc$Qi9uE)c9M$t)Tsy_qICnNd
zYJLVh0;wq9!|)q-x}UqO<%Z!MwNn5y@!iX>e``uNg;Xh9IiDos%@aKZfK3?H3^@$a
zLQ4T};|eo#{6m?XKZsh^E{*{B=jW;z5Q5K~U|!t7$njlvH*=ebe+0ehV?z}9ce(A3
z*0uy6$VH`CpQvfQAH1T+A5-j-3|BjV-B5-#<Y@UAiMWvS(}UNj(a#@yV8&BEf7f<u
zAwk?4W_Op3w+FJvw9l8<ZJ+F+Mt$bW10vRSmM{7$DI!nNF1=H9?q?exWhT<uuhxAs
zI}y&+L6p6#!jF^d+wAKhnt#=4xxfkX)}$7`O8h%fb^pUY&*Pu%2_ykMG7ac%PIsPl
zY^Enq4Ln;ABMzc{QsZ->UP2Oy^uQ$^xh{gAm*J@oM@q>b*_vQ|XBlqPZ8SPFjogH;
zs!B;~`F08-SSGx_oT;^SnIjzG>10}VPhh+~zLv;17~FS)ZAJdrUJKlM8kXCJSRj5Z
zL8O5yKccL6ow=?9X*+?ZCJ4vJQxL;g0Ba71(ld=4uMnpXA#_PqvLn7Lxqg9TF0DS>
zuh37DE!8d0{8ZTl31d{amTGZAx`oY#4u<oGjMNM-A$PvYCy<mEB6ryvJ8xuzVDuT~
zT}Ly(^@6j!Tyi2evXy77RPZS8l|*GL`OKE?%^r%N>>4LM1A24{3J@2O(bMPvqT?FJ
zXKyM|Igxrzmu`y(vF8ul(FcjeHaT8xyc82rw+iD=S%y{unMne^)^-pi(Tq3<c&>La
zZubAQvw_|za@C~63(@S$ha;BM{q`6Mqe9}kIw|KUi=ppq1WCE(p>oqo)}G@+aKlq}
zcs<%-aw4yZ5B4%0U65kRq|(+cHM^{`80Em|dv*9guYU%lg+PF&zDr^1?hnwWcvNvI
z5<5uZz9dM`AfFYLNvhVJ0pjnlVf^8tS%8=mWo?pHHRXluyfAr`Jv;xsb=ecF^$sX3
z>n@y#?#sYnY4U<aVese^$G|~h(QL1`M4eKH{$;^qHH~`B2ti5>MJY0Xkq6@5e1Vjw
z*^;`!CZ||pw<v>0Dyq#5YtO^I6z`f&?o=+tvk2eVniR784A2EMqxvWd0G8FFXg6R(
z5E|P>C`T~*$B{}{P%{$E;<%B5&d#6MgV$$A7E3uZH>gkRLC6UxgkV=xM9V#_8vRv8
z0!9haf*K75B|VFA!{-^Oyn62CMni$wx0L@7TB`7y_8IS{z<(OQ#PgG~YJbvTu3YS&
z8U(8aTHDK=aZ^}iO~LHz#3Ipe8}X-bzY7JgZy0KM%ArE!DH_dT(Z0TYDWccycu%|c
z#m6LnQp37`8I()G_kkt9ftr7k*IlULLlVtB>xMUL{6l<w*X8`*j-TLd9(J)seh1dX
z)Nxyg*L|rhCzVU2WbVkf2jAG8^KWR&_J^1g3e5Bj8;`;niQgo`f&5~T(zWgzw&8tO
zfR$wg_sQ3lS^AVMC*v#?)P!W<Q9%d$QAo_!n2Q7f{|6Qc9#ZWA1S!rM$}v0Gd^n(*
z?OwZWClzeH3WyW-Hjl-`YSTuLOH)omXlk%3C#{nK{JF;p0VZe0^xr`UYOO--5fbda
ziEr{7BHwrpj5dwgLy^yBJ@w+jPl0Mi?NgD%9bWkboQQ1w&HJ{&iEA3Hbw8A$9<!m3
z#WAu;A;=v>3n&?ciC8Cov;FF%<H*34Bf1u>?DsO*U3C&+rMYTFR+J+lhBT7z2qeXN
z2hJ;5SEFMb5a{HoDHwpZNe-@9nU7=eJ6p9u&Pba)tVy!R$6zusP*6;l+_J63s4v6;
zu`u34&Rzu9B1Uv$198A~<JbuCVhd;><xGBxa*9hfa*rs<N#L`1XwdmX2mry38(ARM
zqNgVMiBu0iVzvC#*Byk!|5FZHwbQvACFa|$B@n}M#J*c}FbmuB{%W!wv`5)-#Q6cm
zaeY&7(i4&49usyy%%azu6Yuu`OW%(jDR4v{lCrV0bbLMB5B@aSaKnon>06)$x&V9b
zW3H?Y_0hTao<sR87ekMppf~vg2cad%RDE=8x*1VUjrS)eJh7*kVjml<RPFo)fVLUj
z^Ie+XhBnRfP63)UfR{y3lxQ#wEDafYFWD(affnEUhwWR$elhTkH<>I3-*^`m0rT!d
zf+!^Xp*$^FngC%F=_M53c%jxb0UWfU{F`Qy_BjKg_fig&g94GvN1ww+j0O;hhJ<^$
zd{?-h*Z$`m1xQUJ$6vOGNF{&R1+4sgSMbg9I2&+*C1X9PJwVk`L#poAu70iB|HZiR
zXLB`HZa8^RxC&k0v}sZ!520JDxfI6_bwe4$O`;`soecg1)8Z_5mJDkViCNDNz)^E1
zop4%F#n#z*-Cbq{wH{oufM~%;r`qU(cqGQ`o#*~lJrLv5ZA$4QSUDzbN4GB4HWE)m
zwsm#^Te-hkrBjc89i@szaFXnTzwTW;43@N!h{?b_DZt#gs8+U`SpV@sKq5Wob03*6
zW(m7#2(#hxbHcm4R+l-lGc@k%3ZEOq4XEei4kvw;E1iCggOlvNni-0s*d0<@A~(c)
zZSog<ypCBDe&XfIL>N<b;PbHBLJBxgNe+l`5ER<6iYl$x?&zTLc*ls(vfivvA<gp)
zf8;_ypWMhY708a-uRKu=EBji2{Cds7YX~yiSI8PwZI!|k6YUjXQ6Z9r>jDF@6>vob
zLxO=3*d4O^!*AyS7_>a3r7nsQYk~Q7v{7Ca@%1m}!E+Zi*Z<gWPA|{joX3>cINWK?
z5x9gzF@9R!+n8U3p3p=sG+>+!uox4(zJy|anlo24D#|>9{r<S^=x(Ld@xJ4Nux)&-
z`pH2Y*$-E<|1CFLH%7!3m6R0#=MYPV_vXK^=92BBFhZfm-A2OHwjro6pw`-AWc=!B
z<Hi2|V<8h<5h^>ui_-&zEU^EeZ|&sddHDETzP^{fEiezNH~1p1W6N8uamZ_1A6n#-
zI{ca{qpAZT?|@tMWtn<X5(>p;frYKXtZ$_jlb4?Dj8vX3l0|bS8SRdkRi)_nYg*?Z
zH85EYD9}*1<QHR$Fo2pUR~>G3_lPr;N)Q_ZO&Hz1kGSbeee3BN;nL)${@p2|P7d4S
zRp)f8<8k2diQXFKB55U=NUS_Rl(M=Jxtjc^tg$u%jA7`1Ei9tK_RF;O)rYB`(I@w(
z>k~H9zO@I9W%~Uyf_VLbv60+!*;3y(5~01bBTERxKaSfcDCDfVb1qu-tm1X$V>79h
z?s<|9KM%1_!DRYeM@<tXCkki{+UKej!qAnP`Qc}hNP*V`_P(9%-8ENmS-{q?!Y@do
zMNlzdZEaOi_%J8Jg{UR{uMBh7=uv8oasA9wrXth`?i&@Dt<`zi2&mp9h#8!Pkln{t
zy>PSHnqi`vHY39)ZcisK?<#X*Puc9<1BCB&rD`jE7u5-;5kHwX&nqf!h7(c=@wH92
z_f?ydPg=`v^Qd4u$U$AU352+G%~i%nEW}-Ba_kmTrF1W>L{lxY_b$vdPNy){lZdrO
zs=hHg+J2{_kW$h$bwjie@8FLqzh!%A(9U<uAo~8LzyvHGqcBuniiFk4KsksWE$c{>
zda14z0BguUW$BZHx~{b_Z|smciY~-teY}*mbw&kHH5Q~vszhh5s&Bs%wPfhM_DeUx
zD>c(w2fjDeAlgB=tg|d-?JPrnz_V?mPnbPNc-k7aNNw3)RJD8c#Vq%qC;=1tX_}iT
z9QN;(N^jk1vHi6;;>We2^&(pF*#?a={;(m7c1YO#rvVZPS<r#L3_{}CzNg7IR8$qt
zbG%bS!F)nEOyX~o6X}AzgUll7s5-%Nm5tum>-oU3nwc{lZ?pOWU1oUucCn-;ae6Ad
z^<Yh{_HNya426srWV+?VPIAJn>cwh8k73s&>hl>Fh*n$Sy%*Vao<~u&uVpLwZFBOw
zZl1O0ksA?}1E;+f{6j7%9GQxUP|-bw`XR75=nI;~#pKUKA|ZD0Vx4N2Xf!sMC3s^B
zjsKiNttRgtL=i4NtoDQyM16o%o*EpsMD;UL8QMC}@QTn~XW>k&6yRWw0PbF5(N)w^
z7z2=d+@%l1%sD`~1;MfIf_B$nuZI$d-G!rX7i=KPxWZsKx!X9V=!SqC^QV+CcF*p{
z?t&}+<vPx4?rdD5i@CT;InsXX)Zf~c-fY}UYZ#6&vuBqR3zPc7k0L^PB#Fvf{4{6;
zgAIJ|(`8Hl!8#Qbt=Al4$=I<?qRb&agb2hUnv6~#+TRYlt8g|(fpJwjMF~q^4$(8)
z<U|+si1G+j<Z?fw#MBCPkKV7fu2T33_hw6`(HWvgwOS*TY3E*Np6F-k@cOVmAL#`*
zHlN@>YpKmQkf)Jv)heyVYimH@v2r)0Mp1Elfy9P<UE9MmJqZx!Q7$kd^-dZ~3(-Ur
z^nn9}4dj=$Am5*}8%7owE#z*;c9th6Y%gZ(HUsYG=O9U`Ihz>2eZ1to#Yvz%z{FPJ
zuv~u<(J$A&@{TQqx)4ZJ&VmQfgN1(pM$X#AU$92#jLA57A5~df0iyU(vK0^a0p#cv
z%ecRdaHbEEkuFKQ+)x|CW<`!=96y}QVWidr#`gMkY`c17a;}Wv)%qDgL3wHj9?GUA
zdedZwG%l(xp;dMUI-w>BWLo%a`kFFl2RZyKllp#aPlr+2HfoQSYgyaR@h`*ySpsUL
zY4}r8HtoP?6;7J%rG?+hwOm8>gN~_8=dLGW1rh9u?XvM!#iA+KmT7M$F9_4uRuJm$
zzx#2{fI%i?!~|4$*1EQk546>sJ{05=<c@5sMTTg)uxI8^G8z8~@b-@3(`Pn<83-}%
zeOzmA7?Ypu;unw;#2Gr{8Owuh_ncejyqI_yt{>N~!{}>I-GUC)!0PSvv8&3d&SJ<F
zf}<B{<X8jkiS{QvGrNg%n-!)-(a!s5ppE~GHEz}ts;!~C{>voHLJ2H3SXou5W2efe
zq?6dqw(q1n+H(ttSklLEpGW|LnVrVXF<Bv|@%!@;q?Nvt7rikW&toCO+igex7aMX2
z$t$bOU2Up_ilH`tg!$Em7+LJci;GOe^TWxWkNX4g4)q>f_c>J;Wxv6K8W3wBDx_SW
zDFn?<rgULY2#2h2hyfe|QL>`mdUvAy?8(Y<n*)}|>r8BB+Q0k>+6=BS9TTR8tYr7~
zmAP)mf6*BJ`Rrt|NqsUv`d-ri6Y34GfF!#P4t5o9W(zE>77tihZ79%%5lt-4x@eKW
z^$BK=U++WoW8T@?<9Y&8&<ic?ZORS@o90O)5$+gFI(d}M(3MopD*Jx^$|+zv((?`|
zpa$v*xM}>AWF2$A+xGEOhya;aw0)|8XdXnUaU7C5L*jN&BAk($Hm;EIxsn=8-GB+S
zO8zJo$v{PGNJJn5z`)zyF&EldD;67Wxp0N$G2N`!x4x;W%lZ&t4?F!ntGJOZ`sJq~
zaE%Y{B>)1GAXRRC${Be8Ioy8Y-sU@>S#Mn&_u)+(9Srf7=9p~CB(m|qU@?;6h7+`x
zKHRzG4SSI=gCo}E-mc!vfu0fUemaKq>}vKNADg=|xGYsA<P9-8PdjyWFC{2^XOPl!
zcZbYSDFQcxy$?s$SEbWM<R4#MZZ^OntN^M4UDQ`F%7{h0wAd69msgbLsZNsLg&<~6
zZ+7Bfw4O|$%i!zG@$6q<=Ii5fO$c6+<i!9y20arxnL-_!)_#Ok6AJ9lhJ$qusWuBh
z;V1>Iz)&LK(Dt@=JV8aMig3<+xA{boxJCv=J?<q|zJ}1xYlAja0MGNn2Be>{*>YvJ
z(YrS)6gj3wHeMpB$)+g?0Zvb)MT`h278J}gb`vZ`WFQoU0+)GZ3@>xvooQ)^!6ct+
zbhy4eN)<9W?G2O~7BDMVa<e_$j+%T{m%YeTjVPHWT*Y4Kh*QU+1xLF?nX{)WdIU4t
z@mG3dy?4=3Ez7jzSi9x8emJHzuz6X!kv4GDS7>eLqAMZf_^lHk9IWFmB1#{ggrAZ=
zO~Y?3RO!HlfE+sYSXWoLGw%&9&o88EW8@@rZhmdT)BR3-pSKqAb4b`;;A#$w`!1Cv
zOT7fs<0FUs1&IoXtIsc6)SU}Iw{YnslP9Qz;YgfImW)bSJ6n&eUUL}aL+(pnY(hfP
zx#QR`7Pr)w9OY1UzF<sS!c^tT{?$Prg!*od>RLq~Gjs2C&o~m&3OqCn1=_1T9t|ov
zUr$Ra;C-^*TNJ0k*;&4hWTP|S!ZG_V4)+j%L2em_<da_whS19l?M0Fyx5*QrX{LW9
z{ksj2$L%z0ns4+woAZIuN~q)1<vH*`9&CSlHozoF;T~h)X}eg=t<Z7<z0C8wmQ-3S
zLr$TtpS>G{+l-rd;Q=0f3h3}(vG#cMQc2&RASYVhaHQxfFB$?V*|$#)LU$!E@PZAD
z>QBu5-wmdi<|s$v%Kbgj6>Qj%(^gtC_Fz2cc@ThE3E|Cj#YGMD-FhqbMDeSmkLDG7
zO=*(DTS?(!#{ncPg9<b@V&6%uQM3|r7SvUJeJz&CP&ayfu{Cq7638@-Zj0ln8kT-m
z%0G>Qy&aAr5fT1`{1ETahWUbCSKZ);0(_GBc^pDiPEnoc!tA&8L8ZBLKxago+Uj)2
zY)XNW-0W9L{VcX>&>M|=j6A5A*-==C4GrK84nVl9Nt~nzK<Eh{K*+F(S+#5+u!hYd
z==#)YUABV<5Lq@kEzQINMqHWXk)}=Ya1qCLa9b`L^;c1M%@SSxBDy;rKy@<O!`NwA
zc*b9U<mfFAX>C!?4W)f~09&=}_&qvvUZla=F%5LlU%P8c>ha$*_F7@&)mDS;cE;52
ziH>NJ9k!7ypJl#aWa)}<SXEs~43SVyA9`!fQ9-0#$1df2fAY(-Wo7W9hmyqrBZg>(
z7R7#VjhOaeoLfRwXTkk1REpsS>`2Tldi=^iC!W=FxI$51)hJ+OJK*+K;gkqs1R0R2
znFYAf$Plx{qz3WWuWxh4s4vbHrbjK(JWX7&6tagb-U;Z$yIrRmtrIwr*K3yTYF^4o
z6O*MU+;Im~ugF(gXtJUy*R^O&{m40y04#Vr+$!J0c?{A%CuaDL$4|y!FD{-$Xby$y
z!v=BQE6d`kS>8fWp4XHQ(ZCJG(NQ+}kz&Pt4^uz_Z;Siy7SwM=pT(#nN|E4d;f-T&
z`tsZiG)`S5v%ED$TB+5_?gC!HUJKAb!vmgw=q9e2MiajUQjV3JhY^<ffnF6v?*Zkx
z`_Ud!wH_l*dX~EbrQ}ZMsuK`jyJ0%mqqQJ1G^^Kyf`xlnI>iF&5~Z;`qJafE)|hWn
z2;C^db0)!Pn=CuM#ar-F(*(!dl|TT-gx_SLBfvlfHj3!;6!6cYr>kM&U)Ac75|1%J
z>S$z|IJ&@63JkucGRbuQCKrtW^gn(Ws>+07Y6UO4T*vGKrr<BtQRW3#e-4GdvwDx<
zS4O*nc*eRtHC%2a>k_(=FC!XYbsPmA##+jpdr{12P+I|zf%TMe!8GQoq$i2QWK&u6
zuj6vSI7NnQr3hCy(zh}t#@P=^2jr+&#UI3vZ;V@JwLOxv`~SA$1om6!2YI09uXt>d
z<<<A^g;}ZvY-NW*pZ&MZ17UlIEt5*9zE@wMqdXKMxJciAas@D1J+LgFcaY}6M@(F0
zm7{?)nxl`YlmQpM3p_9;GuS4-$5^H5a2Ab&Kv=$7CdvD3$locu0%Q_KDr<ZyIBKMc
z8ZA5e_#-0tRq+(TVfg<6Z(ijD{;wLc`1Ig5n>nnR7Ap>dD0%`$qFVSO%bOM2w3<+m
zhXS~Lc(`sB3*-(mHcso}jss1Okn3#ftlewOPX*uY2*A#ic|mC$j*Rp|eJ)iNkYSk1
zDk;Xr1YiD|QLt2xKi7jQ0t!RQ>3!M?%WIrp)lDB9_0G-6@YMpd$76sWKH*W&={v*X
zUaL__E(4UmP{RC0&!-U>P`LAK6-%+Suq@M0W{M)YDz5ya>oL|c1tYR7#rB-FgY;<e
zlu5*XI(8<?hzM`-3#SHT?W1)fKJ@(8a24K0&^II!>~}Aj0gz%07WM3jQv8f)2^!<u
z$AQFLL)&h{y-~~bKrH6QD^|8w>N>+!(uKu8uMu%Vvyd`h(+D}X91d8Qp|tp}vN<<U
zJp3N;7gbS;5n0HJv1H@i$wnV($=eSPSdSNisNZpYHALDa#N*cB^JBro6AKSv%N6cu
zFjC)2hf3E#DBp7gtKnp1Z;0M`kD7U%7HqjH168^yA^d`Tl8Ie&J4Bw_4!Fp5s3ilS
zUt61yb0Zo3)tZL30Z?o38zp9j<wJ#`(PQ>hr9)RQL-OQ=QcbCP4Df!KPBqr05)&ri
zLH+Wd>kxN257*Ns$B?&>(Z1^($q$0cf!vVIZ_Pi6H_H-nnUvD5xLxO-oc_Vh`;td?
z0{l9g%k}0ruJve($G@*_x0j)5(Xm0JufcD57VOJpnx`bJ5qk1?HzL0tAR)~-X2Y{}
zL5c=+X6s%MeJ}j3wD9jPok7zRHUpbBBR(06w@_L8U5}y>8=MYw!BgwUHgZB0y5&Zt
z9t)Q#miNDZYsTPz`3yX$<A=PvhF9Uqi8R#fRY;shbQgd(z8%_V@*I%SowZua-Rmds
zf1~x~1x^CByYMYyJ4|Eg{9e+(L0_u(z*0myMSOG$$khAgNO!p@Cw!x;i`ANar&$X!
zUwLmNW(nw3u%<tzBy>2E@QuH;<G=u1aqcV6TL7oAWRj$jkaB5I08MO;d15zUA1i27
zFB{N{y+_0>0*tGEq$5z2u81_cb=};nc7Ot18mn^+-}iXMF?iL{=Hs7887oRY=6(`O
zN@R50=bl*`QyTvK@eKHJz*4(1hR=Q<YjNAhM?Hq^vlfA*1<^8uAfiC?e@9WGzkVUQ
z0?gqhLtA>nO;x>B#m^O2@v+M@?$Vj5GM*&Y2wm>T7-4GBX&!Cr$8&Y&kgk-jELT4-
zlCTmhlp34AQ+Az+N`Vpj$8_K~gr!w0O(@7|f5l#r4~yzB%Vqa(tY_?Sek!M)VIVIj
z&SR9ZzQ{pA)&6`6Pn=9cu{igR)v$e~&j_=erU>DA#%18(1-)lg9O~#BX=s*?Q64Bs
zTBX&50zEl=@N~228c?x8z*aHzU*j#TiGq(EJPy^-QXmf&lii8UB|Sg~#$&2WClI#R
ze}4q@ji^Z^Vi&ot+)T{{4Jull_p*~3mkcc_PT1gbb1s1|zN7`?g^)gxsJO9<ER{V)
z6UvoQP^v)mAcb2FA0Fu>X#z1&U1ml(#SnH!oU>iRB>;r_@uDc<ttP;f(v;Y-FnAKg
z_a&^z{KnF?F{Kw<wS%t7P~i(aUoNbxJQIJ->WPw1E7J_HwdM?j<CQwTIA~sGkX`ch
z^B4XAk?NG_cIj5b+!)f{cF&EN<X+yC;0G~3<?-Gd3$|e)e1P%yr#geJJ*{ZB8M@st
zC)OXd`66`(qYY$T0>H1hra6o|#bBIA7cE=atD?#HuV|CLjKOVZAtB!)^J_{Z^>o~P
zp%$w!0O(i>$8!@+FEX$hxNsfW)=3uO7&RJ;FBAR1Xpo#^2Up;R7R-B08Dbrce~^d7
z!lg~;Js^&GlD^`IULEEp(81@HAGt$JNY`?cX((jejB^ZJZMB*wDrA|lB{3+5Xlu!;
zvCNu=Vi-`tF0B!jFI8R?&WhKG#;UKh`XCJ3qqmmlP}FvT;kBl-@h~#`&;KQFKWF~B
zo!nP8n_u=ZeH6PARuO8>R39+F=ptQQ5y%%WnpWMtpf^1z<>?DEi@O_I^m||S244Zr
z47i4PqrWOwDN2Bs4k%<DxiiVb2-!C!{fJDKhe1l@h=F3H^5rmOA3(oJM8Nw<FXyRD
zLHFTYqx=cG5vwl^Fnp5&_JM97KC!J_1{pgkFcK#@7@j3Hb^_s1Aa9BMwD+Q%4~)zS
zXk*_cXq?KGgVtR*(#vT?k8Y2C_egirCC5*NLgUd|E4^2JkC{yr{0oUZz@1@?*|4S6
z41pLmG+Nlv0acQET$?)3f@5Sz%I#>pT38BCfUyo{a>)ujY;*RWSEOn*ED!E>($u$a
z0&vipc~*@$#l162$$?AS%RzG<KyEgA%}~AFyiN{2<_#};cdp#-z=8UqD%_91BX`Vz
zFO`dD95PW--kuWHP-DsQ!ZrF{$SbGc6{-7(p^6e`*4=O@%7|gl)qmgMiP-v|tqww|
zbLU`AOtcd|7`5i2PJ&_~;I9_vh`0^O4u@8%i~Hi5pkZ!BFD>2U$7$ukYEU}ZUa}Lp
zG(1#`Z<A;3;qA&?8QQijCiHPA{gL8Mjj6dStiw{|;H5^9l_$NZx;b+RrEO89Gp}AD
zvOfnAa)*Bq=j>nF((8q>VRdq>R2(qfy{9K*tS$1~Q&jTLil)SzI<uXFN1HS{X4;1a
zBP)Tq$Phr~m~^7Su66@eYANVg2ZUO{jTyA{U2LzGS2Ei6+>Ajw-xsCS<HRbf4jVlo
zRp0dB@)M|o2_P1$V$LIuvrrM3F>DD+L>%;H6Yd9T5s_`y7(=w+^N!kCGawN;LD=CH
z9R<->+erdd1YfuPE!`}ok<7f_sDn8~dS?^A`3OMSMX?$`^PH^RPcz#7sFtD&?HuFu
zdSNpaifj8Q;dR9~JEZy#adLScoqwQt;I9Ro^2}Eznxq#<*AytZ<d%2hv^j94mwpxt
z>vqOq5T5xqTyE<djOzDcfHz3rNUumQfImwHML?^G@3~nnySSi3SlJ<S2lxwPS>jwl
zJ$8-H(ePz$d*qlMQ!$?6yR4DVj*WO9Ry80`pa3h8qbjQGS27!2%m(7Fs{b6~J?(8g
zisDU~gb__Y@umL$0u|LK_mHA=osq>XJr`>0TC=MoK3l`s9=-tgO_#Emc1I}k9XVPW
z3StYcj)Iwm3ECyG(YTK7uN9#og+W{|r+5(`r26W(u%s-&gtg|wim2cWP$w3q;5%gH
zVlsU-5v50zk3}LN0D;B~n;$%1;p`ZC^+~b6vFSs)J3%dh+}<hSYoe<(kz2bu<2S1L
zE=Us($4k!{Bw}SYN#2jSp~TtLd3Fk`8f*96)435(T^NH;oFP>;9VqTE?65MYx*~n^
zs9pE#dghq`fd>a=X7&vcy=_9D$d>yohKpAkXf@tZFrC|MM||LVDRhcLeaby<Ha|BW
zF5-u_*Oxn6ofVYYX`C{3wZ;#r$6sfxs-SH@MT*NJ*tUc7jP8Gihqp-xXe`J;!>oRg
zK{H<PHPU6#r#cy>77}@HGMW7u{0$77d)jfJwg(oZ^+&TlRRgqVVlt;KluCRj7<}{E
zrI)x}rA*n+146}jT0gKax-iet&h*G3``<w&nI>CMy5t@Mx#K}wWr;Lj*3}q1$Lz3g
zblTE^bv#66tN;u}BtJZLogvdwlovzv%=1t|_C=9lwRiMC5QIQ5A%GEYjD)nO$G-#{
zSg`>~0HhemHuZx!dvdDUN~cDgEB(PU(q9AE@+1LtH!mR(55H5u-V21Ss%e=L+()vw
zQAJrZs^kWz&w}<wI)Q9fs%!HOQZ<ZlSK$8Wz_%F!YP&7ymlY#ECQ*7U_;f&o4=(!D
z&>$DDm@YlF#sal2w3Xt_sLfOq#9kw|4d08Wp&T7`X(!^~O^v+Z8aO77fqcM}%@0pV
zJCBiKz!F0?Kkfds8v*`3uTicdO`;nBX9MR{2FXTf<HAvSkY=-PO9K54i<?X6c)Q!R
zT6&VJDS-AR0J)mk#bx@XD-(883(OT3Cv^s#Fd@raFOlT9EWK3*X4B36ScA%S`BW7?
z4zJh4(Aw847G3~z8Wxda9QSh5yHkTr8t?pB%m8H&WY)y*3N3e^s-pvWrh=+NiO~3w
L_t_hPaN!DmM@5Y@

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_magic_detection.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_magic_detection.v
new file mode 100644
index 0000000000000000000000000000000000000000..dd343fdac805371a83ad095bc8b93938f21d309a
GIT binary patch
literal 19952
zcmV(#K;*xR6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjb%vqfel6hNd3BE8sPB37~0_jdM
zrl+ipvr)gMwpvuzEdeO418`0kwWkAq60>2Xft<A0DP5?Vf9-2&9cxWNyv_=i;-0WJ
zE@0}^_+3G3VMqH#p9x|3L!?jD(r3b>xmJ|fW%aE3zO@0@$A4u!80+IVDzkeV^k{|k
zCdYJw9)R*=n;rvU`fQ9GaBI8bb%p(L@-#5SDl-AN@~DsJ$BTnbBl{b}p17jRi!f2I
z_ES$Sl#641?}m+bpdG$TMtWJE{=Y8wS}d{NGZu@3eE>pom>0xqmQK+-zWH#WFfiq#
zI1IO>XOnzASK!a)eSc%Hi_<g9O^Q;qP}A6fo3jmG7d!s>UBmhYB4$xy@km-D>d=o0
zwx@kHLa~b*j;_YF*$w&eDGhb;q-Uq<8hHhd1)<sp;G6hDv@+-wy69ctMS&{JmO$K3
z7kEqIwQ3&0W$xvoJrNo0cF&W?!boDF29ciyLAcX|>}6^J33q{qx4yKoJW|sx7lsiN
zWWh1Xmz6W?Ps3+|d{9p+yQceun#u5{HtfV;Ix7C&`IDl_fd}6t2lx}=Ra8lIwhzpS
zkYXKLm#*Fv|DWdJwBp?PgMcNoezse@G5@{Q!(O%}bd~i&v#e?U>&J^)SVmN)edprx
z$|o2&1`0gn<J}0jJq7Ujw|8q?Nt;G9e)+`OgJn<hJnsWjp4Gk#McO6;i9R}ZCZx}h
zkjSyOpA(^5hu$=FDgd*51&ryE2qYm?0aCXTcYRCcT1F1!EarrkjXt^~lF!Vc3i}zg
zPo=-O3Gslp;C&?)yS~a;893(sjLk?1HZd+-yqf|GM~(|g8v~8Hf1<PoYURxuUhMnb
z)~Y!fQ#k~ZPQFsAkNQP`cMHYhxT$~&W{k?{7vJ2-i%xJM1Q37MjFN)bG;&P)4i-?R
zNHxnSjXq=B`xO;*q#4zu7*sYrnX4E_L4(nGG^>CU;kBwbhnb*VEGZQ+{zMmc4Azdo
zD#i>HiZ$CTQ{ZCN4C-Duk)DG^Y1YJsO6c`q(6_zGAsIXa`ZIYo*PH^jln~1x5(jJr
zb)#VYyzsJCccJ^Pxxg=NwxQl&9VR%wM3>=>%x3EiTkzFqmFS;wdMG&>iw==F0>Ln(
zU?=j=L`p%Q8kq$GV^sk~Dbw=ssNYkWg2jKYHd2kM#-H<~{2%yj;~V=jdTFCo0D$0B
zO{$CxTLZKYfXHpNxN4Z+?87Cz-Z;@q^c@$c_vE76`-kLTM*yNZ{lZW5C?RRxx1A0j
zhpo+%^QKvoMd~a5Ta3xKYjstZKMWm_>JvlgK4Z^P-YBa3kiz!6A_*G0R2PLKJKN9Z
zW{O_FA^u(M-RV`>L7=IAmkPwfFOc*|YAlJVhuFzQ65>n8Z}?CN>%MlxD*#+Q?7Sa`
z*WO&1(15wJZ8$Tu5`Tfm9q2$Yu{~trNu7gUdnk#O#4M2`wmd?QKl$l7>C2A5DW%HX
z`=FvHf3*7$6_=p;`^aGKnG>mUO|uT5K#HFKHjw#seC*&9t0KqpXnlD3QB*1`3^-t5
zFGnO(=mmnFepk36F*0{lybhn1SSGS0A8JaaqnRa1mHY0QNpW4Cyo`fG(O9&zsEI^G
zz}B%KcA}E-T(b##+8LkT%YLYD8?;a3^c@t|<9Pux03!*67AO}KK7q2;&i6y=C2Y88
z9X5*$<wrm_gK>%5?W9~A2Ewj0h-|ACt1MVRoL&TFjtBN|v(z$iP*wYO*JM5<5S7+f
z18-Rxm-It~`oCEZX^*yXqyx}>g!?n6>usUbbNtArR2a<apoor(!nK#+Fv-noM{4=J
zrCT(=5*zRBmbaX?F+KIawSY`|LP={+U`_Ic5M(NvD)_OlAz2PIC=97n5+;3x?#dm3
zCGJ(01`G8Ot%e^j`zpGqZz{mW!JhXOlRT_lnB%W4UgsRTt9XQcI?0t)ll_t&Nx6{9
zd}xaAO~W%7X!zD7Fh3|X9+-qs!RE*scO;wpYyvpShz1d?tbMzO*qH_!X-Sq5f~dmF
z5Banxmy7>!ZV$``3jUUpt9rkLW1ER|LnJBY=UxMro>sAI_zcq0kh+Gb$%-tEoG>+R
zaQ+mK0>;f{+$qY&FlMq}%TmobA+N(w;hWzTd2~xrr855q0XO@fclFm7kuHtjR*lMz
zxEI=qOj@}}sgR+pdSLnOP;6sGGN*`@l5sjEvr%cCz-!w_ZMse!JS{+ufa!)M0@ofb
zcWPL(aGSH{$o9)0_tkc4CL9B)14qqDIhNg)X@B^9yCakjDQLi_bx=5EH%6Yf5cI)Y
z`rK9#Z2ZDB+fqus^dbv_ju?)MhZ64n>Gzxn%7u-)RGDE4H?a+psKx{nwK|>UE+G*8
z7sppG<H{-MJs~J>A$r^IOjRbivkX!K|17l-Q3^3h{GR6kK!8KqD7KnpBpaB+Ii)Wq
zZ*HBn+?YPsh)OPnu3V5ISXBNSH%mIDp)AnhF|vDFH_y#P<ra7yQ(YZsJP))&KPkgs
zNdqHMtU-Ci%0>W12fq1wXvo{a4g8QgMZyz~ZM7tM+ND1o*Mzmk&NMV=9WiNo2+*GI
zTzgomBXSMpv)h%&v1LM>Cl1HoF=6%Vqi>vh<L>0nfh+r6d&~H3L~UG-U2=bt4j<BU
zFo#f>ueuR;tRRZ*U9EeL{&f=OT!SPpS<Sd=LX5bfHK{sUu+&=%-}O1aQ&64A(RCTh
zATjV-6D=t~)3hgb2fe~7I9#dht1(9GIOht(*q3TW<#^$m_Y9O1k1Ohx#6|fN4*Tur
zI$BbKB*opn!B<L`vzlR51$mvmL#4Q;Prxna-J~$%Iwt_B3$J%UWlGJD014adQ7Txg
zdb-E5k5B~^?#i=1$F7AOm}Bmij9}%{!jWO9ehX=9Uq)N8kNA<I@^A+GXtk~H>MUY{
zQ6R}y5EoVm9V=*LMvg9TUcERbXw!_+^Y+9?1<cj?EY>b4|8E8xeN&hDh1y#Qx}KfY
z(2yzCP{aA3bd!ZmzH)WAUG%n+j{C2!)(0t>0T8BD5lyWEU(hk*Cmx1673sC#c$*Vj
zFR%8B)Ghr<Y9_ElnGcd{AY-t9tl~cSVMV2zq8S0(j!h8DzJKqBa?K$#BKW#KFt)%l
zy@VRwUVs{Zgx*Ak8+nI_KY`r7SE>+}@UM(pxdY^Qcw7>ZaOs}`k7Ix#v}3yIGQqb_
zV0EjV%2~QDSW*NB=j3kK;bn{=5eQ`oQJw}#J#Y}NC7F$2MNxGKV91EP4^E+1Jd=we
zg-z>5MNyn`DoMV&<MmKOaB0n*r|OYEMU9nPPR)Zb&N7%db9qW}yI4C-*oa|Ep3#st
z#XG4-AS6l2Uff)Inv^7&{4cj(<Y&+<S_MUXz;@x*8D<DJAMRyyX)p)Z%*ZYyOsPTW
zHsetf58Lae>Q;_vCgncIWRulRa&N_-T65N5?}H?zJ~R5vskBb9%NX?)3VUuZFiJ0L
z-b(cq-p=*xcNp7@Fz605xoGQkWqZg=^^hNS{^W?W)1b&da+s$lcnRVM&0LhPILz|w
zuR$UFqP!M6jWP5C0%%WaT0eZ!xIE4FD~TDOx)&c`0nSl=mTri8k|W*-lvrzkLM=X^
zmE1R>qrWv|_>;n;{k~@p02`8TdPrTAuU2h5<Q;oVW>HuY;g^u0M1!J-sNR(O6^|kx
zP4~+&I@9!znvh%qI;Sk2=&=WT`ESEkM<ocG##WGz4UdqvczsYpS{n&$!Z){x;EW=s
zm193LXFdm|<BQ^P(^!(HMXp4WuwPJ^Lq{mD@nnT_G8Tf8*<#~ClyEq1PtG2eF;_sj
za%28<tSQ^ud>Ig6_)hj}{_XZ8rQ7NEA73rqCdC(#msE0l{(6D%I50SH70KTA<1MT%
zla6Mlt6g!`0foMjTZMp5EZh{n{wn^K*+)!n!@U_p+%>sIM%z!aM}~5D1>h{tlCUyF
zXEgHgl@$Lnc8C@a2m9DST6O0M3OEUkdXApeb2QCBn9LhVROkNjK}I)~7>&o&DOOgi
zG|wfOQPK641v;kRO1Myqs{77G4;+OSqt@o)leNC%7bqYw`_R@Fbm4O~;$Gl3p5RmG
zBv6T%cc>B>j5?H>;7+7Q9;6BDZlEZCt4>=RWwlv?cjNW-^_hIRVz`=YZjGrxvzFBK
zmz`Ku`4s-U#(-rbf^OyM2}81Fyb*k!9^}<%ujz`Cb(jeLFUJ7U$aYs3i*~2y%_F#U
z{IR(-%Q0A6io<)OzDMIVr|KEb&H;)TmzR)m151B;xph#MyT;xRWhY*>z8*-2r!+iH
z0>?moFrrE}FJKCaa#%M3v+O{qdlW`@TgF6d=@c45AfPhvfSM}l0#WrX&1=KaPN1m<
zqPtm-z~2Ce<a@Wz41!RJfiKk7$7z1i^t0Vc_@*>Z{w*B#vpU(LtT43X=Os7)B`qH)
zgY8Ni4!b&{rLc~U`{~{p+6FkY37njbW1hk1&ig0egV_)BCUCwemcE!Nxj5;!CgYfO
zPJ+`HH(}r*VBvpiAKJn>QrSWok7fUK(OrXVF7V+Nf)IfsO95#9ryCIL=5M~>px`@;
z!4*UJdCx|g#-BM9!H+=tz%5p;F=c6NTZ>8Q(b;IFB8by(Y)PjGrT?DGoQG?EI}l6;
zQ%M+`r5EC{jm-vGWl%F~;&%pnAEu0YjF=y1HQ9aKi@(v#WP0V^!MCPw(cGTYvjR?P
z3kP2p;ivmx2I{uAZV(|1EUfpq?dAT}J^YSCxbiil2!wuZ?v4Ucaow0gquKLi$_iCZ
ztNc(wKv~N3`fUIY5O+dzY%m!65OprBTh{z+OqG&RCM%MRBx9%~?<Jl#4#Nfl=Ii{0
zZpkx3DvBFiTZ1b`$}saD0t6)w;>JS^5N3zw0jc8P8?ETJ@r#`vU%4X46qAc;qt;18
zx9@J+G^(j5u&uk<)r`&r%bi@|{Tg@m9|BDZMJK`Iqh;{T@3acg9#9yO#kh3dlP(@A
zbvkDEa>)WZY<}(wTesgJL5DGV-_91T8?SRRyT}zrU=~O^RDrS($2C__5_HZPM#lf`
zHm6(ws+yDZ@3+<e@tGo2b*n5K1<U?5>mM6{@Qp7l0Q*uDAZ7`XT+-II?(>rJMMGKV
z>=!eI7-Kc}z!7@xu3H232#|Fc(WvJBwMxT^CxYW<14KC~l49acZ%@t(`Pa0W3zA_F
zdM2RCOD1*hu#ThhJECCIo}cUjBW$bn1B|Y8CwM#LoI?eo_T#>0LmNLkuza^Pz${n|
z!g3OlasDJ@ge<2Yp-us2inSqz=F_iH2@NM2nJ}%9!X{=buQ9SAGB19w-elXWO6}}r
zVC$z0K(u*4yX0_TC8rOdWvN3p(Fl&?P9JG=?;N^u4pUYDWf8t|*+21hsJ-7u5yx))
z9E;K)G`eTPLAV6fM!R6WA;uT)sM9)J^^3chHOBmIqo2<LOH43+xw#Lj2^7?1(+zdb
zOd_dc6yrwlS45w$LFdw#`7L;*XYW!;<*5ZTP^TvPCo(kYKh*rxF8ja)FI35FIYkcM
z#xpbrNY%J#IQPr1)3!oEYys)VKmkaznkp}zG*YqK0dML~TIL;uHP+utJAhqm*_Hz+
zT0Uz2Q-+o-ws}`{Rm#lYNmF;&eWlx>L*|;%T7;y6MW*gg3Aq6tXndMv*1<q|#SL40
z2E*A3q3dydR4^2Tx~W@S(F{Q6cfORg=%MK?bZDq>1>tKvCaJkwHw#H;X;XO;28ihW
zw%4dN{Bs{}eRp!;_D#r3AU?*ZsE?E93b)-}>?AL`(Ik&~6_qve>YLQOCA=@?csjwr
z7lfWVp?Wr!-@a*x6De$1<CR*3!Kl)eAfko~SR%<){#8?yJ`*-F!3a~Ox8RFn)tdm3
zVZjEj@ba|!Y{7HZ#25zRWC=T-Z=(cVGDjs>qGm+Qj**o$sEkLD>%+20YRbUG4G{Kg
zMgPd~HC!NtSKj(gvNR=4(Tsu90zzllsjD(jsdV7i3t`-E5+SVT&$`?!ZB|v%7ido-
z6UkNJ>s42#VsA`~?qAJXBqILSdj{OfG{Jj+23;rMq0D}ci66L)E7F_0-Yqp$gn)NG
z_v$hKNsAYu7`}1u{1Y0Ny4|~J=xeZ$;I9&fv4;YTS2~M(o+QnXJKTjPHNt03&TA1|
z!e;VdUQ?sSwRCfL{-+jw9g*?1k?MBDw4rdp>X3;0El3%3;lGdd_}@zyGH@ny1MY%+
z=5AKLGdJYJr!Q3~22&NAM7B03A>j9znqMYa<9sEv2L8hcY7=~Np{D_+gQFw?4=gOk
zsU!9Jum%`>S_#!}cNFLn5Z~BRZ9UbYQxs7iEB^sRHeSG<ys6}PtdBi(?Z3eR7&<Jc
zPU_Xeih~f`8}&pQ2?!<Q2?7?V<?6*}w}+RkmY~l53c>5XPSDO0vxB5K-s6;T!vwoZ
zFdh#1yV|8ya&B(b`z^Kg)Dpl11A%xxPIS%6Hu&%M8?$VuOxG#xQ`+0c-B^L+QJxVu
z=#}{x%<=z&Ie^!QIMBORhTiUb57%!nKPFR$;y?8i%rXhfbMcQ^2a+`ao&rvLrDO;$
z(KN!Mw3=Qlv0tAJ;leFNIB~HzzTMEmIeqn&?ALABH0-bZqgCOz^o*|W)J1@zHS<MV
zj3`A`&O{&PJ3OW0e8{`iCA%U12pc}|@%bliQN^~>?@HKHGp|2txFKnl%*308tPiZ;
zhvNRffq>tET=I<w6=^kVVz5E0j3Ab2Sl9SeR}?Q!RTWN;z4SS8%$z7Hh&_wuKu$xj
z)cD%9j>E9QTScV_5nP`>;(byNcHs!gihW*!Bd@bVqb`H?0ba;qM|fEC0rUQ#2!}#Q
z)Z3CB(7u8A^f~7r^kbM#jpv2H4d+Tua;R*5wdg&}6nqB;;bGv>uq_vl@ll+@W}n<9
z@n80eZnty2+R!a#^uB261F)a381Czt;PW|nk#BPg6WFnFgTI$8r>KrlHc`8b@dc73
zDVRLH>irI`a$8^0)rCN(-*SwotZ)hkH+3Ol2qu73+3<7O1b!&LM+t$GZq1I47-hY;
zz>%!McI(TL;`Z?Y|23FbE~3jv%80Zu4|srcB0n{k;DG)CrFtK5(i>O&ZimreOME1(
zHWn6<E5%`WFG2ABVl)CsCAM<@F+Kl!eb2XM1`bk<R2KMh0;n*U>p5=<Lw%>R)2vIg
zsOW2Z2pC|J4}oB-eL*iq%1-gnW97xT=h<w^SRX-`g)KQ(4@~zPI2Iy@uV_S2MIyJH
ztqF)`MSz$vc7cHbl*$vZ`a?K;{b7D1V%&JkW^^>Lf&!(FmE@W6B=)g@HBk+sm(SeV
zETN8~@`WsBvIc<Ce#L5!^v0EbYodK#R7Tu46dU|kdCh1^^<TkGM{d`oB*hiVM|h`u
zHUBh4!L-z~it16jK{WE+a=J+l2{ugffewUJo>7BrjG0c^Sm?mQ*E^{N^&JrHv?eZ0
zA0+3N(X-N}adrTfv|3r2E;>ao6Z1sfl~9}13q1D!pfo{_;rDHMR6=di9nk}3+uXXO
zacKv|9E;Lsv=kH4K&kV!tc9Q3c4iTzJiLi)j0>kun#aCM2^}!B7G4Bb#UM{^zyzlq
zaa-7458HE(?LN7^+WwDv6eN|}hW!`6ii;*})Z>O*a4XnNqnqvjr+l<^O6=wO4EN8p
zyaU!RRLL54`R4jd1(HbXDDvH{qfNIxG%F5?o-PQmXbiUGa9(H0A@swD2kINy-j?)!
zp~Zf*Q<ozvb#9qVd9`TZ!n#lmWp0)!%gty?lY6=xNF<WZ(`#x^^(=#yP5B>3Huev1
z-9A9Sv~6Y@y!ULMXl~U0BsT4sH#Iha*U5w8w_b7s*v@tzI{h)1AG7jp7P&r`gMl|p
zlw5U~xSbqD?V1NVJusBe`lQUWgq%X6X_kz3YV@a1Ktb_<RSC?56Hzo|+RW*HDMj4c
zaD}F^*`3fug#7hig80of4+aL}eZu!EupIN3fu^HER;+`v<aEmH3QPF@naOeS6}CXK
zKqRGI&R(A?N|hzup)F3+{JI^q;AqFAu^H<OyV^GEp-s%sJ<RXnZ7IBxd2xl}pAtwC
z9d6`sMPtUlB)om)Vr>OrgDS|P11Kw$5_%fgs5D4BF=|{#fFZ?Ga+T+qF}^#<seTb#
zY~4+9JSs?J{=QpP`&bpFhF;`kWY*948Y@LGRXa>4(CMM37A)~*#3NA7CFBfjQWJaE
z%CL7#ijuco79Og>&w+%?tY75gHz=3}_3>rV9*%`DYPMn>r^_=Km-l!bt~^g*_em^C
zF~!GfM}Jrr8#8Th7Cgt$i?E&*IGBDE8fh3&V>%iF5LbLgO_7PLf|t(vBT^RlB$tCX
zJIe!U#VB_3#mg#toD~PD0&%mTe60n44h<moq{&H_flJ0_MNKRI&w}706BA|tQcs*i
zU(J7iG20t(!<zl}2^4aeVp``}w{(SfS5oTqowYSy)yu7OlLb6EvRXE^d?fVUu_&;_
zjJ&E-Ac`v1hXe$`KNxEcf+rM$g)40lwTYh7E;T2&9QUuQ#@^<yl@aqXJ<9(D%vlSD
zw}pAFAj$NW?|XUhbnIXgB8jMLaA8{lDyh8>Gj0D_?fjw1B+HGcS@Ojf#=5#)G$JA&
zR38!;?X_p%<HlCnJ1e^jc`XrS=K>%xOKH!tYv(uMeUL?=^4P)s{YkG;gpa)y5yi4s
zUz(@x27eb$fF4w;iW2rZ{ae*yG7ca@WlKM*BlPja5Q?by{egHP)C{3^Twm1wA9wcl
z-BOq2?&q{RXf3g>?SS^bNO#A|-$r3mj<5^4NWIVwpYssu*oano;uJ1E-Gx-^x-^$A
z<h$!pcV;-*!0W1R5ky$OWPEE-&}4UN#NrBksU(1}v#=XGQ5xBMfw|Tr1OKG4FDGzN
zUTj|T5{Cj5l-8IBOSU<<3w`@-moR^+KOa71&dAC3wGq*V#-&&{Pg|LKD)f5=E96fJ
zSQ#~<)4)^D5tq<2#P9p`feTag-Ta6wt!;(=;lF}IG^gnF-+gZPhW-2Sj#?`2Hb4>?
z0KmkY=$$W0l|m`=z%LRBUGOLCEW=nLOVM339|lZi)hy*#e-)}79f}x@y$lwQRT?rt
z3vHY<bN&#?kaE$;Ctc^X95P1zNYpL4M10gK0a8j5P*X@`lD0Jy!|CF_w3<9)WdZcH
zclUE6%6;ofnJYk~?g{@IO`a<nSfOKrFMEn(pMj7*Je^0JL<dkgSNZJof_aK4?fnrX
z>rkr01W}IZE^XokU^np7mfMQ0wyl*c+w(L2XOZm0esA4Ly-nW$)tf`j;+tH{>`c8=
zk~VW;Nc~u30LBB^uDm)4R5jy>$eD1W(l_vM*KvtsuLMD-w`#ho6)LHgPNw7KuP|3&
z)S0M3Hgkq}J&T`>*P#69a3+Hy9L5C@1sQ!7;}#l=u#UWlmXik3e<(mvDS2UvS%fMT
zohhx}r`w&ij}T-eI3bviU1SHEorR&w3OldX7blE|%I)E~AX+F^jANi-53xioJX&%i
zedx$k(vGeIwNiC;@oqJ8oXC;r_!S8d6TsR~-8fjUOY4)8H-+CRIB6n+evGdbmfcn_
zwIMaZs{H&Slcfo?u5zSYt5*@mQ`Ld=xGQ<4t1v7CYahsqkaisC<w{t^ghX=Ov{AcB
zrX(FTXFJ3wOpqSnjOEkgPxHn!yy=uyc_VNmAuF}u(Xn@rV3w`Ymxg(o5VGSe`ljzf
zGy~t(-Aahx7y~nF#oUlG_FzL(E;3ek)WRxxN~dCr0Sw*9C5epi-OphJJPFQ(C8a4#
zE|4<j({lclWF~zz<1+RazgV7!dJZlQH3RlTXrfJJ2{wvf<|~QmmkNcqyppYDJ@AI9
zcm4N8ft5!(y%zm42gD_OsQa4l>fKRueL6HYPDJ3DPY|w79TM*Tltnp`b`3!2G8B3L
zrqYh}iDz^(e74xoKaL~vDFCGI`}4qCHR6t~M}ZBklAhpzH}CiSSgIEFsKW9+OWIwq
zxe7IGejJ$>cX4-;Bp7_#qT=SrA(AYc-n$_G4c4Bi;8%)>PA!tQ5F>;7x1(YK+I6C0
z=3FUKmyf$l7{A6v{i4??By~UIqO*Twj0>(qc^lFFVl@koVwJ!3Q?%jsq3;irOCj^p
zxX-SgGN2GTkg$#v6Ajtr*Q8#1>)WiT$6{)H8cZk)4%I{3&PkT|OQI!?K7V`<WqX0j
z302_H6ssI~XXk`^TlnDL_L@64!=3Vw9zK>fyu_HHC_YP=LbIwTJ;lcqSm=wE7QfeM
ze8P$~(5k5MXqcY2-YUQbupT1+sl0>IRM7?`8|8kTZ9w^RM$jwI3VB)hLRMG3pb=mn
zk4~Ue$ZfMi?x<!G1);^id3Y{ES3ihD;cH*mhSz6w%i$X67s4jxN#SwGqf5Te{wbYH
zWd<rSY-<`7qCaz*jtht7OL!UCj$y)BY~+{|Pc*S}dgV|i9LvFB-S9*Q70stL)*~n+
zyRqP6#EFy%`U2lTrLS^%u&vF?9YmnvE}i-0o11mkT$P_kEzl+g0kQ0p8C>LsbE>5k
zki^W*WZ;Y7w`na*HoALcN)z+%l7usjIj%;8(_)bRgk!j0fh41bDZ&RU!L!nm`0MtK
zDU7-w59i~nB0A?uE255Cy8M2oX0V<SMA;Oo&Wj~DTLT)b#b{wvrzMvQQDkol@+-n?
z?{cS^XR^|iA!2=Q-2CtP=SZo9O*~y@Niap%bb&M<F;vN`(9I<JHApRD-N!tzo1oG2
zGM6C`PiWe`oy9QmD78Z=Ir8+>*3=u4Fh)}7uJ$}QkLB<bh7ilQPlA6d<2j7eP0VC>
zZIyynbhlTBHy$@d-k@{lv{R`Be0LboZLs`f1@CrGx7&0%D{VU_c*!Z81nUr4;ZjUV
zmN!jcjrS+7*7UCS>}Gvam`jRdGb>#@o2lJpSuBEJ%(Q9wPL2Z^Y`cjx+1hNJdK>ye
z4#G3Tb_>HP@a4Ue8WkI;=oQWXxqny9WU=RUkQiC+E_Zm>c3|OO9QKHosW1+P$-bI_
z+3_&ywncOgag!A!#l^ovRv#0oh2m=kV;oq*UZKTgP9+hDTuM8QEcm5UVcZubd3O2t
z-)d6Z8ROxd`~{)izy{StYNC{b?3jaUZJAC0*PD@n{}DPBZhwL!6xLwd1ioRWhWn}h
z^@~yi66+X(?op>Wrji<4Vtn`YM0*o=fDK_MWXJW@Hh(1>p&BgSg%+R3u|)pLeL2*Y
zPpd#vUvc32vL!^Ksb9Eho^1Se2i0xCb%3f6a6{4hHfhfE&NUx2T>-)`7u?iRB6wg*
zREh0V;^)sVFKnbenL8=#Bpv~L=#4Pju*pY4QH{HTU&*~X-cIXpCK<~~2j^!QW=Kad
zJ~Yr+d%j66pC+N<6pIpBSGncT`Xb1{J1Zi!lRDyIYIr<fBOM(!u}o+aN~{xZvGmxX
zD^oL|GG<6-=KFDrue+Lz>h}q;XiqrZ0jxozh2hkM$`=L03|e{ME&2T=Gozz5@Iwh^
zKwIruZ$FzFv;kVWXp8u-FbY=6jA-J`X{JuDP+tdyU?dRxLYei|Ie4qXSpKxq+?x<y
zyNmY?Po?FH30Rd1?CZ?uFB{jJ_M_lN2tmF`zOF&yF1B64<~wF|bro+Uv%<cACB-p)
zWq~wZ0lpO_y<g;Ylh!&%ZKq;5`~nu^ZL<8zU<(Z@J;>M#c9UH~wvs)+$1`7c`5zbh
zMrMDt*)~M$S7R+4Su_XjU*D0i<}}qMHGiA{k43}8u$bIwIustS5jj4h?MErIJ3vbU
z>5f;+rK9!&2AdB`E=zsxG8AAZoT<05k0)qA9a4i&@gOeN{A5NzP2(<`Ih-IQOjJiF
zw{|}xQKhBeXZR2>ZGC?Z*9J}$F}Wg!>*ZvO2*z4X6bj>oxJ?<wgp0m;NUAjs_iw;1
z%4?za(FyK%3_|8Y(?trFWj)VaRK<FF7pXu(<T@7T9Plat?4kchJm@<Wk!Z=CUUJ&x
zPtes>+stD&*!`IIi-&NMlCSC2#NsngJol{7tFg`0{A~7_XzSjSeND)d8j!gi;jv63
zVV)P`FNcd>j0uU20gGX*rrm1S1h_!#%A4h;pJ___)p(}0PmHh5Yz60jPpomw9z6B7
z(a%IX%z$NuHBA@saoJ)b*Y5pa{CensaSO;Y?X!XyE?wg0=yozo^bFG8lq^DbAws_T
z+nX9Ar(m}AuWz8)7488O9}g9ldZ`rU-_>RS77}gw93*DiI1gvhr-=5F*&8|BdtTDq
zk`5nN#LQpYjmNrJL)j}4R14~>dW4y<Z}3y<Pi~^q!4PFlJl&p80->#Ep|Gs!f<HrP
z3fGY7V;2)#$nN)F9{Qty3KdOaEZdD)_(isMIe-aaoS!$EKAID&CX@R!2Ao&1i>kdu
zrX`6EW0bQE>N=DTR!i>4$%`|?R=w;eKRvWVER2i`=*NLZ{ln}^r0$&8$TDYv1=}ey
zCyktx0Lp%Nww}TDeknFq)Ej|27vPWRw!CDK73@;fkEL(|g_xX~rvqZS8nLaMqt4|E
zx6^TqxGH^%kMo$z{&E^)!kOpUz=ru~_k}t=h6c8g1`S$Uf>Ye$q(F3Vu(vY<$rC#z
ztR&@zG4ss4P63hEuH#Nuf)*V>=2;>3n<-9^s-S1nw;gIBM*-2qwee#Y3<4DPU(@X9
z+05C_=$BCT41Aj+3fN$|l1Ekb0`eq*OYrz|TOlOKstfNmmM6VE17t$E5lrG+FN`d_
z`(2Jveq!!B@Oi03l0!#vXfO%taQ751P5~rwxV_n!%ve%r$P&KRP0!}g&}f%=sS&V{
zK{^;FHCQ&`%j4Qsk<Ll`L-sdVab7;U86`3vM`WrdI+IrtdG0v*w?l9Ly1Vgl>X+GD
z_kZdWo{(zB%_@E$5T$Fs8pL{k(mK~}i$$5=3ncNBX+3f$1>k+69G_8B487sg6ji{_
zr07s6A*)xLq)PWvR65T2xMXUC!nXN^D;lfzSv(wu0qSmv4N^pX4eA&W+A9^^RU|hf
z8`^eLWA<$8P=nK|X-LT1OP3YvV7^t*u;&{^?R(;y+*84<vj-pI1Z-FkvF-9Z!<DKo
z5zOP^G8+&Ym7-aQDSrT+gXQ)Cb1TXMP0(OLY-tY#a<*Pb99mYT4dqFRB3)^za%6NL
zV_d<klfT?1-eL(4TR8}H2i(Fl91!MF$-;#!){jpObsPrg`4V%5V`fwsSf^!2cUU~1
zsaTLWdUkmlmsUUs|0m~IzYTu$Om|=3=>4MVG<nL8-r&=+wOwuj?oPFf%s}`-RRcJR
zFmWluG)$g*o-~tT8lnh9*+&A^9YL^#KQT=q?ISlNA8dYVDMXRj+uOh@gmM50<X4v2
z!S+2tQpw>8M5-daKaDALg;DsH-&14`V&$yY2c|PgQc;w}P}oH0s0!rN=0pP#z+z7T
zZQ%AKfGto;5(Gc#OR6p^qS39OzbfYhgVJaYr+WGcN=3Zz+D*f~ZMuB#ZH5n$G1}$Z
zYX3W6PMSc(GnNMvj%?2Efy3{@ICU&i&fCO8xj%RpqeKPFg&BvGJ~XJ=`0ZQ9(M)jD
zMG0t{P5Tu6(rbqHo;ikm?~|`dys59i(tzb?|81B_sWB~VUgG)t6n5TEn5p9+*{^lZ
z6CAa43=l5`rvF3>{jW|njvSb}AcM(GH*`gC4oHKbs*Gh!S%$DCJCqM$J?LfGtObwJ
zZ@|wS#eV<Q?gKp4)si6f4(@yvEeNepYZ7?h-@(4hG~ytA*gLGu6leE$>|JlAHR*TH
z?E$j{l8v0E+=cSXtc~Clrp|J7+My>^bpY!08Z~PuT(FBue?#`C)FY`{=fpI}XGwRa
zdoxgt#Q-_;DJUi;>fYmWGa~K;lmAd{R;rhXUB5|F>JgVr7P;HN<w+nLgHPfSrA)m1
zNv=UH6DoNsxdpKJC#Kam&b~pp*CV2f6NhvO(K{vuY2%{iDX&v@vX|kqtTz_K;@ek|
z59K&roje$P6@+W=n_`lu?gEa@q(38D;84p`i-(4i!Tl1fWvMg0l(;jWHqQpv=eyfn
zD|WPJd^%@xNJ>S!m;wc@fXRh{r`|s5wJv9ecZTK99Ir`m4L_<`f(Pk4!1SL(-W1*X
z*IkboIX->m2pM6`ceB)8#imyz3}0K9t-jdcp&tQQm<C8#$TQMjw6m<jBPy5+sTsBa
zRiq>t$4rJ*vnJe5{(ULW8twkWib685&~w{r)sH4sxRP>@`-6wEyDeP_3o~#y=Mqfd
z-{cx5CMMk+Ck8#e;C%i3U;L*ah;Vm^6Sr1HtS_XfTZ<frSt9A*N-2k`?@k|PFxz9y
zR>Cbbh-(-t715Tq2Y~=glU&-ZEsDEEZ_gd(`$S|)%~h9-ifxMYGU(M)(1;zFR?uw%
zo>KBs<&`nYIm-%G3If`c<o73|q(0d?97fB62kG9Qwc2Q}5q^+uZz56UTQwwQa*#8g
z`n!<oi9wT~Jdp}_=j)G!D&+_=w&s!u>^94|OeAjd4eAXWsU?R+-EVg6EX=Pr>;JF7
z(f~(T|9GndaA20WJ?{5^9K^ym$AjVQ6e2*NeLWZm9%I&^tZum9w0=P~S_@bPCRqV&
z>2$;jkUbvz0B0+mI)<tOHEH-o+ubw92<mP4=m>#EHsWAX-XZSz?AHIvMDANjxRIN}
z*}mAmp>a5f^#z>48_{L}>^URZ2<99jL*^@)!*<NC*ktBjWwkD_4)ATRker;9okyuo
z4noBfApeFs(xx8YNaN=b6E#PZ!6tmf_<)qwkokGXv-TH{k7WW;+9t<?%~cSi>)*Xp
zE~$HH{Wp&AGm{pkPvz791j;5fYPU`+i<%K2lpNK$bc|rS@Us+y4~?3w&K>e(NctD6
zM<R?-%a!rrM4%5=C(k9{#3X^{er@SA;5y19K0carYJUMR4`{Ov$#e>&{2TSw+<+zh
zgr~s3I}mVV(-Ze=mGYe~0LGRC`0jAS-=-3i*I6B=3i||T+7`-C#Z8Mdb2R4N1=&-k
z+R|?2FZ|zkOgAG1i>y2-1N7r#S1ZCW-P#s!XJF=Rlgjrhe)qwd$SwZi`Msb(6AFR4
z3nS{_#7@Hk91^;Qa!2lW<&CX?BF1KV?tF!{1b1QjUt2g>pv04mCsHcgt%}i|6UtE+
zhf=i$|A-6p+BP!nCR10pSQa;!g_E$2+|aF8ZI|uUcE1sc>OfNDq)jmT%oh*wU18|!
zRm^iq>SI?^3k_||2$fs57)9`wd=wF><^hu6q)ya&d%KDq+%}XBz$&bkB8JX;N!~7=
zZc^?yq8s~hLW)A6UM#rN`H)H{<uv@vti(D<<&;jwu9<~f6mP%3ZIK8H6M)$9#H!A^
zd)8>HQIK!gr7|%rSI6^pHSI0NFi}FLJ|_EmPLVsOBnd@{Gf`LMd9InqXl~z%{d-?{
z)!u#1ZT`*}GN!{-)*-blwXE01)YQ-w5if`|S^*mn@vD+6Iqgi#ryaFL4#Wh-(|f^F
z9qWm|EB`iZJOmZLgZ#cNSkFh+^}5k11p>tPs5RJbKk0c&p#!!z85!qePFO&zeoj0)
zD+9ZPOj3jmS(_U(k->0SIe3MH7J#V_CzsB=R<-3`j}h!No6WG9+SBD=DNwKIn3BE*
zD^ivGd<wVxjl5ZZP4ZS!uqL+DCnMdY)VQE(JF28Hfba97LcN#C#=$1nnWZ$zfr<?p
zmrrU^6NEt5RPdj7j6mV!a6yOi+8dHgzLI7s$Q8Ym<l8;ccK@T!r)@MBTlzHFUeqFN
z+_a@WuIpdcZ9n4y@e98ppmTc8e<;)P-alkrDZr&0f3m-?Ly@jdKJJrv$77R?S?dA{
zR40vF5040Eep+!aQbM8J6D=_oLg=g?esD-^jXlPdHyVr|7D+Z?rBJZ66pUZEJm8LW
zpsNNXjY<IU#I6FFS`CMLPot?>?HQNtEs|1|IZI9toh4f#GN9kkF1exGw||1I!6Aq=
z@(2<cwd51t!L11NnYO(gZqs68g}_dt!Y-sqK6(eGX|xJDmj<PEq-Q)MZ{SQExS2!D
z>)=}73-s3es;F!p&^Sm2XsT<P#_`%JH1#jXVuK#0t@a^b5tN$EIv{a~#1N{Le85<f
zLdb@8-U1{07-mp(U5czKj6eKThNhF56DI!@9(?!TN&b+q9w1RL-bei_A!T6uisgkM
zZ%-`x#^>D}nYC}!xkN=7Ho0a#`c<&R=>Ji=-<{C#e~J7E{l#c+G6>QD(1n>l3_skF
zFk#2-dDt^j5&$Onh`eoBDKnr>MSK3t)a&+}m}1gvgc9!EZq1Icg|@c`HwBxKp<%VK
zgT`ufzDjKPA_w7K;R(Vl2y5kShI%y|s(_b)#;A8iAwCD}P(s;BH>}d)%XETj#;3)M
zT#ucCa;!PQGNY{jFs+uX)3XUG1fh3ZY2rleTpF~|w_kzZ80Z*Zo8iW6pm*wUXZ04e
zr7*W&_EkDkGm*IIuQtr4E$3=$Sn=D7_85)yD`SGe9Z5QI6t*W9h=c7Ymz7*A|7!yB
zDlU~K=R;z-j1T-VckD35tjlZQ&dY}p^~T8u{&aaIP%RM&X~9J!bdCoGzIScLtFqsI
zJ!gayrCk2>ojaR+v~{PG7UZDiySNGg6=Fq7jBt`@m!Funr+bv*wtE&Mh|QJQOS%eU
zMX3?)rZ6(gj1-h=xTBt&5vOta!CC80vxsyTN9dVKF2`gTo8;BY7>Rf<qgNNm#?!_k
zrCBgt1MQioOJKJ}z}%4lUNFBFrZeKO8q!{RGz8ahlXg14B>xCmQ6)nal9(I<@+z*W
ziF@8I*ts@=8^%j-;7HMbCO3;@it`l2N|n50aWA94sBK_n;Fj#4T|kj8@9vN%4&O^4
z2xYjtZo!8zW04JQ@bPd&3pe?%*HDIMmDwqttvD?6yuTKa%pZ;UsZ$_mBzJDpuQc8Y
zfEbz(XfOBZNEklGvH)Zf^0g3j^!;_i<xoCx?yU3)9n;oWApSXQ(Q`Y?l)U49UEjbD
zL8X(L7Od4LiI!FCNq&BDrhqH@(#Sy1iOkZlv$ocBZhK1AI0+C7!(i$GBhGFLFM=qy
zuBwieZWmh(v6QXpHC0QbAI9%0)aIb<sv{R=9^x6wFL>bj|BC}!|8(*4C1jdUkl}iA
zKCSSITMW)z(-Lh&d?q_ZS;=t_X`q&Lhw{}T#qHdczrC@y`LG~??sfPS?{R+i`8;j?
z0=AOE3Ga;Hd;Scr0t6}U9h!IGcscQOv#S_ZG(CHRyoD3V)OC&q^j*Qs$r;*(0%cl!
zP*Z6h19Z&8t2s6sqLnAIUX1OX>F&y2<?!^<Hs4CZrv@dwC)v+9@|FwY)U}FfPGcD`
z_X;n;EwTxX<w|jC>>!<T=3n^BuJL-gd`T8&gkxfWlf`^@`Gt|~v7n!Lg|T5tvQIxA
zJyj~s2PFf*Ylnav^Jyq{JO+&$>d8{==&Hf?NiGeT*QtBbBN|fax^Z!wU|TMICTXpw
znZnq4dBzi$x)u9wzWdc`3OKXAP>7BE?U@2Hf{u$bq?pXTaM5*_t9RV`HD;tui7v22
zRN{JpN(xmar}tKy92CyNKvuex^1~s2>VFcSDFC;Z8}Nd<pN~8)l_6n=#zpA8_%_7g
zZ4?{bDmAVV<SHGGg;z3fV)-2O0SM<o{Oe|nM}hy<R0+ogTQ1?BttPf+rZN<lv<lQE
z4=Wqm3xgR9Rd^W@PQtK0z9^h#9rFj4Zm|5DCjc`X5#wTwQT}pwsC(~i!)d)xzb$sN
zMS7s@cDeF7oE}F1fCPZtBKqugLO@X!A@X$li^{Xk#CiA(T_NpNVnnVHg&`^i%<#pR
z$(C~giMpb@%0GA8s6;u?6d<3VlvJbAr;hxJZm=sF-QEIo1F#U3O=>ZA`<@~maSVAX
za}`wU{OX};e`&-D%uIN`^$F8kC?0XVf5A`ag##Xl1_lLhIa#Ovvq+m_{XyMWg#Bo;
z=>$|U10lbJ4Ia&(5*sP#lS(0yCJAtp@#x!p0%?#DDhb?|SvGp-b>!D*>KhCA<OF!?
zL=wLa{Rl)9r&zGzM@=F&VZQ7xF-U&Q{C%E{RDc?c*2CB<TCa$4_eaIdW;TPufOORI
z$Lpxr;(?#S+*aSex*<!PbWw^)Pi!C+D+#eZeGHmTq*?ZD$BN$jWT5wQ{O|tGU@U&4
zMe5tY`PP0)CTmxsDqH*DiGqTEWJz&mG6eHyhpgl_ZVh86AUl_GUIM6<v7zj{C6Q_|
zExoET1=BeYnuF996HY>?o!drr?~J<_39tF{92;%p+2aE-Ji&xH*%SRTPYe_7AG4c0
z9kJcM#DN6YxAUA8jbp@@$8B{8mVvk0m~|=}mgM)+7eUCspW^bX&DY&4f?$^qvA2`o
zN>z`6F=Np$sS-1^Dk7S7t@~r>TVv%m4ABLx7pVh$PozdAOt$E)<`?W7Z!2NmBRjCp
zFQck1fO7*-#qTL@u-{mYgIWbN0@!TCn9w8$mePiV56rkB`k)3-9pShW5os14=7e%h
zm>%o(sLZ}+1XyEd_Pi5Ul}?-|26oJO(X<Tuw&=)4S}P9=>Kq!?5-RaFoqOY2SL9&{
zYOQoY9`<q&;0fR1sso#MTHUcH?GVrZ@dMbb&4pBir)gR9^uJN)j!Vb`RjvAF@Yp_I
zw*F+7niB;asm^@R{Ji}`XwV&j?!U@IXbh<>AKUv$PZ5EKn(G=DXLD&?>?1-8^Zu45
z+c3gxZ9VI5;Ymw?&YFFeq4>j>GaQVXxSMyfe3QhyXGI!h<NNS_u?E5wQ$#`r{l0n`
zizS%K1JWIQv-j<kxna7*^LB>hsQQR+chvr#k-uL*MI!~%=%3cdaVtg53F+*3WfUin
z*~F(WswMR`f*y5;Tl&kwZ=hAi()qAE*ZvW3%%iK!vF8%El)22l=(t~oL<wUA6xf+y
z?4G=WXtT$)${+yq=t0*N7po9D+tzl*S_{&8V~TRW;+7XBn-Zm=qy>kz<bHFEQ)7?T
z&P4pflzb&953%>p!>*4F6anc^vAk#pS8F8Repelcv$)TPTZKo{Sjr&9wB2;_EFe|3
zHw6zvH!g#*cOhpN7&W<!&PAUX`J~T_9@*2MS?_vt{t#nCX8w|chtS@X#y+_KZ&*_;
zS{x7_RuhLUN*;rbs&*WD{j-cXw4{y@kT!g6XFJRDh!$$<%anW%o)VO;ed}&-+YSDx
zH9r>_8<=|1m-LPx#$@+`8nn3t?IWUMromX~%n$>A_dJbpTj&o|dt0*dX7(i+QYCi?
ztNd&u&oFe)hU*3!%AMJ$=QAV_y%(>kbrj@yk5hY%N4NqS%$oI0@`<u7<G<h<HNv}>
zZ#TX-*rviM%yC0qF9xgzJn#IW<B&I=0X^Tnnf`LU%RDY0F6mh%$@e6%dxA?TM+rMG
zEBVw4X#*zK=boN}jHn%QR-a{x*zs-}P)!`ISN%qEpY{9Dr}PrmDYFmg)AeFa^tJ#n
zPdIatsR7d#L1kPtXD;@+1jBG-Yfk7XwmFXvO?du&Rd+!up)ytQR#sQj^uXc2!vkV)
zFXt=4ri=N%xAxjuzA0$Llo+Dmt5m%JATCHPL>X=ftP_8lz}M%ED!I|?39lq_)gb7e
z+5r$|Jp$RntRhqnTtQ0MqpY|*J!Zs{-OnyMYQ-rB5|qs$hAr&(xOA@OpGqIGypXfO
z8UB#w@rlTU54@cj5I87<ukd^{HDnW$G2&KQ_l>tg{S1p=gk|CGzDQv)@nqrn>fXL%
zn)iZa@19sYm~b#%-()n~>$$Eao_tE;5I!VTR#R$;bq~h}JkLyR*?us6Y9~>PM~O2H
zh;FjPE{x4&8`%-FAeh!k0vv6+^`8wy9bFH!(au3ZM2P*|ENot|Fw=bTT(pNE)!5$-
zg_fF3cMBmXV0hJ`N(3L3rsFe9hK_b__?W|kxv~^&u4!y!IEa7f4Gr*gbTQ+a2NimW
zB&9w4klPe}mQ(0Q<Kg$VY5}VFnmLTn4A90uqknx3SwXLT8;7@ulic#4&VirNT-dbF
zkm;3THM9|Tcl`uN>q!>^@yS7l(B%jWqsZb(AJtwe0n>tyRQ7A`mC?zP;Plg(@Q+(r
z0q6NM=drao#t6_me5d**vQ$9SW;_j>hggfQ?z@zNGe;!EQa=IJ4Jz_8S9vLaDg=kM
z2%zL_aa>`tOJG%;*Pb2zJBCOO84jWs$SzH09+rb4Q(dj7Pi-4<I-&{)>==N&Dk)^2
zaZ7u|ggvA>3X7LT)AU}>nQt#AX^1`#Hoc1QwFHaFNs#C9?a|zcD@=4v(&?-DycHUn
zn@T5+^%xY0cS-|N?I^i&emEc>uEqacxI|RgJsQi2Xb)u*D*xTkt%RIN1I^nk5SL+O
zo$D!u<q+#_YyB;5OWVT9M>*!w^B91ne9ami=9GYVc)>Jk@gC7u-?}QU)U;@NpuYhJ
zO(5#Zv^}|ign01M3y_?|&4@8$%ye5xQ$>Z3-5G^S>Bf%#Du(C~Y<=IFta?I$a^5#p
zXe%Z|A6frcBHv1>u0z>itPb@WfDd~JXhfYfz{uUw$N1*XG8-S4WBKsOF&TChItsw~
z5q%m1mv}dnxz=||j9G`hUQ9yO(#m4*>~5ayf3e)?+gr<!W>t`fnWLeRRj57}k1-8>
z4dR=m$!vI^#d?fK8JCg!?YC4?wzFSLE++7VQ_tPQUvXYAsnb#W^6@{zjTKZWjtZ{L
zB3pJMOEx@S9$8I#3{9fHmff{<)kL@miWnbo2uUta{k$QK2TK^BcN7uwxvnHgLR)|%
z?%}^xUb*ly^E!e6QCW^T$S;-PjpB23e<bbogN0-ngw=rAOE;mMYChINMQjR26@qHS
z0+iI^=O%Mz*rN!NLnGmahx+ld;mW}s(UbHyn|U@~3`CqWd<}bfe3o~8@=*h*xnltu
zzNvT`?7%FV_WrUl4z$Fag8tRiVtY|89S$o4S$$2H+#WB?i)hzUPf{`2nYKqEd5gEm
zBrEv}GCSvBU~pCr&=pS%b`3unxlXB@@bciGTu$fys{Gp*P=6DE?|Hgt0xs*t->6+G
zdm*Elu!6Gw!kV(Hv=iL-IyP_Z4cy0R92xc0f_d7mh2+)i;+&EL`|V}=62;vO@CC)g
zmwNRBj@8cjAzE^+R)vyVivWMpdN@Gxfg$oKr?vF4zBv)TCA(z8&L_srg+cP}APBvs
z5zF5$7_qY>?HR7=RXfFu%95W?{$#+C2eWs{TueJ&O0h{~p%JX7d3xNCGYU9U&wp^u
zWq@>G#MvdA+kf@UrlX8hiWO-U6gBfWW%6iC&LOllrlJw*a?>4Ap^CoeT~d$mk<*o1
zB)nWYSs`&|14GoczTXL{NHO?c-?VwIstmxrW6^sdEEJ>Kt#Ba8>CFV3LN84<GS?n>
z(A?2g9R5K7w$1-2hs&t&F?99FzMcc{PrXT$&u&0QDW<>UL9zf^I8u`9-5_%RSsXm&
zDPZ$V@`6H=0|f#TRnhCr_-|wkf+#R!Igu?6heK1OcJ|-|ZQ8mJzysiALK}@!uNNMX
z+|ExmdIWzUn`T0w1^5%hr}(joIH~Scic{WL#kzxnhp7`l9enw~I*<$I_J3B>U!`Vb
z$Pyid7s65pkWlpTd*xj}e;YlQj1c4<NnUAN&w0~JNq`{)#EV)`y(x3)^I}f&M`1BV
z6py^jq1wai^{L8)<x}lu@WN#%Pv~G}lebRYsSoHi*d1TzQP^z|>8qIvJU-Hou13vI
zk!pLWb=vEUvw=E;TA#P%Yn9crwRj~3?55(W>6qJXvmmUn-Z7*a&iD>cy(C7dqf-Px
zdf`H>X}^;xPc#Ee+OT$=-HAZSb99RX$KdG8hdh}O#VL(U7gaF+dnGz5cGuDhTkht%
z(+<r@!PQ#piT-AI$@8c<X17H?WRN-3(5u?{%_8C_FJx;irg?=aq)y026}|VM&xfW^
zL{MuC^XxSa_jfm_5le_#3)C&I%q!J-GUH%7L&JsaFp=E;UsYj*Mm#YC%T<e;8PA#{
z@I7%_885#|CPX*uzLP-J_fMxT=6f;j3Vny3J-*@m6Ml{)eS`rbAt1Ea@rB)cZ#iOa
zdi&8^l2Q7L{j?G`cXJP>W;`&e08?mNj~|{$7|@j~@W}qizdq8c#M=s5N1Rd1ycd>k
zh2h+_A<&Mtl16*{rZGT3ZyjuHF%i%RGzIL#lWZTHFEB?}U`CW`zVaoBlMjdfSFH6{
z2$tTB4gC$X8bbZH<9Js4wLmHUpMrH5$(4uvrwI{V!=g#J{ALfvOCA?BIncdrCz?K3
zzL}d;lVA4Kz?cQK*r5I>&xcwC4gmQ%x}itNzlytpiO79D%npB2nCU)jZatPFu}p+`
zC3$Blp}Z!w`4CW4kZWZ_CU6_8$#)2;hxEKe-df!vnSf^kFYg<u6^Hxw9-(dO4-MG4
z)X$Resj^`ffa_Ho<Ev)*ka8;m1;>O~a`t7hF0;<}Z{NeUqUa;Bgzr5zgQ&A~K~B}d
z+X$#H52CTK$YGMsLyG`wrog|-5z6|>3f()qK$dW^>(U>}LbVEjliG7fM>~nQt|S;n
zq%&`igH+rD9JT9OUBG!CUVbzv+3Z@Bj_4{3aL_@sl()o)y{WKW3pWSn);r%gh@<)P
zEwnFTZ+Q15GCukPx?dIX0hvYq=zZqMracUo1Gm4Z(ngc&ntbdrS`)eAvcNmxJ~er9
zEH?S{dwEbKpQJzRh=dgVvE{=yXFs2ng<hk%ahw7BMCuOJ=a<B;zkogfLzf$grNl5;
zxr0B7h6sg6guF!rwrFf<rX(XUS&ha<i6^MG#sVVD^wZ7g;Kj)$=%^SF!@TNDFAXL9
zRX%@J{BA=hM)a?#(S^bM`+DaHFV0W_G^-X`iO?IdcJDSm_cdDh%|SJBdzSauh;s}Z
zWd1i(;iqP6EjRei+HG-XV2K>z8Sb2jT%$PdP)4KMCY3ij-z6gr;(sn=<!1lP-y?2R
z#>a=bcEJwDu>5TLVjAQo;pPvZq3Xh~CudaXP)}6GwP0SQ9xf3I>`X<mJf6CBF|9B<
zlEz!;(w1fl=EpqlYbk#<5LY{$O7%e~RTZ7Gm;NNTIjL?=jvvNof0Rl#D;$fe=D_<J
zo*J&P+XlWxhWRO+R0lQ*J9O*@$NXy965yl{T1ghL%&xVp56R<zqf){jBvcVNC%mVb
zrscRsJY~^c$ZqvZqyaLNcwGL>bju08=EZ=tmt!nmwIp`~hEy$SPKh7*zK5;(GiIqQ
zf##R<Q&{s3tJw5-2vS@M7T#p6!SK>s)~Qn(b)2=?ld%LPGPlK#@+0QwUAi!^lGorV
zCbVq1Jt+G70{s&>YIeIoo5Tx@)@+KVZ6=n(<6Y3xEX5<NI4oUvC2_E5Xx8?gewci3
zd{OT`t^s2xCGO-2zHYVR(3tZEh@6+yglu*J;F&Xz*wFI)9R5QD$2N6M!m7A<Vc7)g
zzOpeRdZp#^4_-^kdGCvLdX+s63EG8HwJ%4tP~n-vQDX>MpXD@2ph;~aOVZXu_fIiY
zmt3}clY*-g*t3Ly!UF3Nk;)#(vzU&BWMG<Hs!Kw!v6dViTld&uih<8O9ESJREh;Io
zGe$22Fz7z_%Q<LZrn;ME=r2tJ+|eJfZzH29J7Bbc@ZahgIK~?*<~}q(H<8D?2_ua4
zi7tILPr){0`BQ;z`nUP?hX-&Ixrlg&b|g(?(5&m$Hy!G)CK4ePihc6N0wI3-(W|c^
zVrW`%X}@4dJXDeGOzB#tLH3HVoYMu?YZ&_{1TqkYg~J6CP1GML)CvqfM}mdEvKe_P
z&<E|jlkC<~LcfcQFwT-P8<VPki0~w)V`VQ^n11R{!_#JA49LXEh*;*atbZtYOF(vx
zZuu8PL<qbJkl&Hv8E2@9RiHdyO$%7+7zjtgqGr3$>XMZgT7&ecq-ugm6oepmeH1g3
zV>@j61gumc?eyOj#@WIQ!*?dUFSAVd<!tVS%TYhLZ{GDmhbTyu>#a;34aH^TqJ;G1
zVzOS&`6Wcd4`1;HAlqB{@@)T;Ewdz}cRK%7)@o`FHZNzM-_{?+edM@0ayU<MeP^dB
zN@PyP_~GK@;vp0|rE+i+7X-38d}O*)F0X4a$zf}p5x}o;m=qev;1*edh|pgvRulTh
zO4YIy*sO?=?#@v)c)!S<O={iR!g+Na1&Qlw$^A(4d)n{CVbjqC`Fd($s4T`g*-8}n
zb>u3Ya`T{T&~Op};)gOC5lK~6OjruS4DZ4%<SQ71y!Ew|gB2r-;#;x*Wx=rJB!inK
zI%Q6LBO752DhBYn=yuLP;WB_+wezM#a=ck5d73-+VPMN`tM0VNX6kG*W&;l-#ldNg
zaVkrI;2HQh`tySnGFrX2vAleO+~?^y53X5h&(dzf-<g?mnMf>mPQcTp3O&VQ`?75x
zoETFw(Bn6vwP9{;e>per%8M?5+K#PS_4w|4$UOo?eNrvm^c3HIL_+OkfK2#+*!6CI
zQ=|cyknlSpkQf>wK}cb-t2{3Ay9j5)nK~PTOZuKh%)1LhYA0Avb*xX$?7>Mw(S1u<
zyMgtYt||}g+4*2XCq%NZ6CFr)32l3v@q+Jpy?>K8%y#3%h;ddS!o~4bvoc8dBh7rQ
zu-{zVC(JqP1%0{@Ild{DFlDjKJll5+(T>6e8CN_PirGLF#nmFpyLij2;1=p0H*lS{
zzzaAgQl;Hk)qA*L4@?7%gmPYd8_n_##9p7I-FPjVR1^QnP#_DZHKF2EUWBk`DD8(r
z-W~HfwEYVPoZ<IN7n-{Z?e;DqiSaz!6BE_LHOlnG{e}U((^feGp&jHY7va)iWHzf9

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio.v
new file mode 100644
index 0000000000000000000000000000000000000000..86190b2e6a3199ceba0ee665403de381fc436ae4
GIT binary patch
literal 17760
zcmV(lK=i+h6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkmQ{ysHHg<^>LNv)Fx{qc=O=K8m
z8`Pl_xM+FKEMZ;RcREwe(;<ec9w(<qADkJmwRw8gXlBBqRl%?zn<)vyDnl8v49mvt
zYh}5U#uce|PQp<IiCe7zc8tA0JPLhg_PiZmXc@DYpzTCnLdaME0r#|__-<?(CKYQ7
zucng+>xTR*i!A&X%cf_YAjqrlj8)bJLw661V_o$oAR0Cva3v*r4|v)J`D&4+idRbW
zPU;t7ZgJ-D*~Cu^v{Z>4-%)SOWa1c9YW*)*(WW(ZIyP*$zPm6HLgS)t+HBd5a;cy_
zU97Bxknxd5KQaPy2FY7z%WaYunquqZa2ZC0T1;HNK&^SRS?oV)5^A;88z06A-@j|H
zseQ4q0nuMNTB$psu$2R0-jBUiIZxHPE{!9F6|2b<UYvl+4%+tE_Z=Qc?fQmO+M0(N
zDdthj+wco?R79wh73g~Xkb-HsEM|Ob<NM?5Ckk2G*!OjL7QDG*Y}Wn-t7DgYQeL%)
zsEIaZGLrln<sHh?E|YOVz+AtECq7?dnAo~v_s#Qt?fpMKNaRXlP!;8bTCWNc(G~M3
zH6*h%*h_EWt-Ey+PkAaHVP95-U_*v0mpcaiLCJANf(V3J8)7BBo`wN-JFqsLs1gz?
zD+z%R@`V+Rar#aGrPcFPJjJNywvTHlVxbhg7K<FQfAHC}370_08nuc-Oe95cl3j6(
z#^w8Tqn_GG0dbfky)vllP+j90L_7RJNzBxI7TDtSsMIEE1*s63D4ztjF`!6Yb4$;m
z*_u}w*YJFXDefz$CzqkW{wWdjiLP7V=;geCL!AU3StFM&v42X$%|*d}S%p55qrHcK
z>Fw&J#5u|v#MMU7#lPOHx}qb;pG0r%essRtW7O6v8Yvk6N^!8YXNzSaTU0s|!soKo
z73!MNnkJLq>kajl*H1w74`G@kgyfsi?8V&iqcV;}?YPgZ$fd0;@Jo(z13h@|QXgv;
z$cmT#OInIVb5A6=aR?hbOf$fDwB<b7%1CKkff>z9=<tTC4v-@Jo8nSqU(Rr#(KaYK
z=BtI&QcJyPWoD1({2(|8bg-y9t3MxD^CDY@)`n2Ja2DYZ&Tqb^3Q-U<rS~f%)a}Cp
zf8(jax*`iZ*(}I3@qt>Kwnd0lR?c4%kc!uet1RMpyZS8p71EuKezbxHM^GUhpO)td
z2Mv`w6QSpDrMrg)ybJz2Qjw!R(@>BkJ}!*e)%Sd74TC8wE0@2LLcJ1fNgwmDyH2<{
zOA<G}2s4wwqEUIxY!fHVQ9Z?Vc4X-7-Rd$41A(`*-dzQ2%67pX2|OV4_k8#S|K6f-
z7ID@32g%2jc>Q7+mHhHJ9OUd(CEuN~75Rjlag_^lQmY+0?lt%sBp%sh$SiS8v{FSq
z3ISK}sCIhRcud|}bF)+Y(=e=|NL+hYI^R2b=ZLUHVM~RlG+3XNTq;}*KJ{R5K-y~^
z=~v8(21Scx|8H)%C@lK1%JM;^h{3XcFOs)T`TU}4W-&!)>Zl}%m%h#Ipq<9h;=(?O
z+{o!Tu9`zUS-p0v#L_(n*O?fKvC1G5`qVLZ*X1%gCc=>?#r6(F#hPL3>5R?7B?J|i
zk-;$|7kwy-hLWlQ)kPf)?ls4LrZnT``vO<oZjTF=>94amK?vpz8KTv6kLAU0E-4aH
zQusPc=J2Kf>dn6AAg9M1bzhpxVY%7|D7+Js)fInJL$zvG5kEWuy?Zq)eQCYZQMfV;
zvQt?REgBXf*C-(Ni?1Snj$6LveTrd-<vT(u_Js;V<1$7)-5ga`E<{Uop160!H*kF5
zJtNc@Nx-H-#$9~5Tfy!a@VDb_J8ok-G@jOj`7c=On6TkrI~yI`wu_B?(eJ(pgf<<i
zt6Hk=w`rnUHDGPyguDo_$Cv8&p73E7&me-Vy1~zBEa3ig7dL_&PZlA+&V?hxDC1|D
zfAGv}Gnv5y7(osw;r*pu@%N1}b8bC6*_qnhAA$4EDhTiSRA~x6eu2Vd3I#qN4-!B4
zX|T?$IW791d}d@W0erkHvobNGuaBYbRa}F0A_6e}#M!k+W6M?>b6Wm#YEA?wh(|$f
zH@JKDh_~td6Sd)$#>pg2pWJ}}s1fl=CVy>pbN+dfGCX-WRT!1x$LBO8w>`cf*xSmJ
zDH3dah1Kv@z7nzIb&+MsL|&>!{s|$-x$4XaBFcE1D1*2Nc|dJLrpMGIm_0p1J){m9
znVZ-A$#6`j?aC`EWj94sK=Z%!?jA9_Nhq3D&8<-Pw}jtZX%<-s%9r^xkR0I`1vGH6
zp~ZSdNG3>L#BPr)uWbX<d$u$tEwZ9`x&Ak<0$`w*tZDpJj~-`)TCb?BKa@hH&O=ob
zmyRSw;jCH)l+Kh#RVDt~<a#VpX(5)o&Zk3d96cDg7kKd}XM+4`V{S-Jcz%q4BPKI5
z09tZSbs;DgTAtqTal99y3cuhT2r2^_w4ZIxd)^Nx$#f=yRHo^EW6oGtm<!3!q}&#N
zyb30WO)Zd~+qeb9(9+}lm6EEhKjMoGDw`U;AncmzBRI(z^s}xIvjI(|)WF_e`jvm?
zD3Z0^kZH9wR5FS#8+aUT2F=RPSGCc2VP`fRlsStfRA|d*?mDmL2T1Z>h{)&_{5_aY
zr0m1%Di9$K#4~LWQ)jP6hiFedJVv}ZD`Hf%S_buK?9CTtx!KpunkL_|;ssDQdVyO?
z1@0uHtT)Ul%<SSc#aksa95V|D8_Wx$U@2V9e6wk7RKYD=pv_SANxQ(qIN59sK5#g{
zPK>D(e~C0v@aO#rvYo!zXqvQL3?-XCB9q@;Cg8B=*u_n&gt_l?`mNm_0rW8p^+qxR
zmG?}#e^LlQDZGdkz9SgH)Ia@uXzW7of+lOd!w2CtbDGpF$)_WO@03MLE?vJ0uUUmz
zmFs)qqtqwg=MXah0NmtsCD;e_kqQ#Hxo%|B5tOP5ryiA}zvn5>z|GXLOek;;2Lit4
zMbf#3!~;8B{pJRllZGpGkg)iy6-4ADR0TAwqBbZp!uET`pt{OZ`*1#l?hhBc|2U_`
zigDOR_k|8eKuAp&^e0}3tTISPaJmMsT~pPj9lJ%eqW|rfGkxB}6N^Jh=ttEWvJ|y>
z%w{9v+-?_B^OKkt=Jze^V6Q`I&jpaj?$qcbYI)CDlWo2c8e3$oee0D~hI-IFj!8G7
z>&~U-{PaL~ydFNBBVjD@Yq$|yh&6#_v;Z}SG81m66(>WL5{_kWdV%~G?WDpE+dYzb
zHWL&>`l{*sW16?~@MZB3vgtD@4#XMB;=r3R7KbTL!68$r(#}L~@fJjoO-78Iy3chY
ziTGO`mM7$n`?#pm7q#I&G<%E)dY&CBjjSb!Mby<XkxI`7MJ%Hv<hkc2MVfTQ*k*X&
zPVBI`pSQ)Pv+qYB)LJU{G47uN*5qD8mdED0!iiMlc>cOQE|xF?f+CS@6EBMeDW+*W
zZntHCx2S?MKV-E+ZKA&Dlj(Zj!*W(+)+x@~>?eD<Rx>E<j#CJ!RHwY3)Z>D0Y`4~)
zgB}d-D#{lfZp{3UCmQVBS8|>Zc9T_Wb#GY#%r>&H@w;!YIWdb*&*t80n9*N%Nq?u;
zbC5Uft6@O&K)LCcKegZBJP0bkI%C?P=`K?P%eA>U_iJR)b8(n6rGnZ{-mLnrdy0>1
znM{`K0+itO$R_yGm)4VY_oI(Akn<iwZN@2NDg&q~>+BiX@xQ(@5sMl$w&8F1AX}Uk
zXts|<Eewyih6pz5rVB&0l`9r2(7*Wd{Dg{pwZNpi+qu2vq}kvm04XqPmdzP%nBqad
z-nQ%x2A-dZeN_M?qWbynNPo@qbCHN*jX>#H&zoE2Epoy8pb|%1&sb5bwBj3o8aKew
zS6e-;+z4*z5?zqOXsgZ$h8u6&6PNl6?Btu0^M6;X!O=J2f+Y$)T77({BVgmAZXnO8
za(&qlKWB@<=EC+JGiH4FlM*Dc)SFmME@BG_U)uGvV$9rLorxO@wBCT)7lb!j+lL{W
zzbqr=zA^g{XU)zs6m5#=dh@*p6c#pziBEJ;O0s5=(G`qZACTN)MJRZOh$#L?ZQ6H$
z<;BQHJxz8KiMqQr;vaXUGm=HhdZw+6-k+9cYgbQaXNdr|%E#uTGZXg6XeOB4L9`kF
z9-%>52izkQnM4$>WpjFSRvrfmM>_JkPh^1%AQAjsV%=ZRAY5B*RL;pkJSZF?bIh2H
z%&;R#5Fnr3=;jLD;P5M(u7E5pVKBn=vs>iLw!KPL1}o~>8bfpNl+{!r`5mZ(9L+c4
z2hMDp&y}+pFNZ%IjL1{VT8x&)euINjG%g9)d(A{3_e<Bn+ZrHxG8uM5-Seh+Ix8HM
z0qPAW`Y)0mgDosS4#EO5D*xZ0K;LKK!t!7*;Q-v@|Ee1~Spr0ML`a+{pd(8-@yW?H
z7%zWaZ`!976*8HP<sx*iEf}iwrCIiA5@m<?Pi6X8l<eb#PfzE7OX9KK%%_K?#L$KA
zVCYe#ZWQ|Irs;TZoPKhRpDqQ}(Rz`~%26%H;rcg4y-R#s7bokUiL%}ZE+9S<R=o`q
zw)CDoX6bZ&p+ALWg&QvfbB?T=`;wRBD$P5sF)DCByb~eDBhQ)J;XcIgBp}ISq0w1n
zAZfl?jKiMEA}4nzKS4AZTj&Po?6p!l%%N{sqhCJ}Ee+UZL4mpa%O}!%%xk2la2J`R
zGQ9C+sBtKW83XYm^u)*$eTXEX^&K3788IP;ENv%G%9}lrMBW2t!E}dZ&_-hzn1U1D
zJifLuA&u#2<n2{XB*{-<wQR=AR?|<|k|mR-6Y;rm>A&TbO77UlLco3ic7?l65y!Rw
zIJ?MhJ%sDvn_a>4gCx0vbN;F)t#)aQC=~0_Vwerzfij<=EuzQ_oz>WxZh{7DHXQxR
z4+GT^B%I7Sf?iN=M*dyF9saZfo?g@Y9bZ4jx4y^TO!WXN=5T7^gYJ!mr5yAb9NihC
zf+-BT*(PEF{AKxH@fbGYBo#fu8d`>mA=!gM{}b93BNyt^mj^0TT5TG#abwcZhEq-$
zTZRLdqfpg#*D?*L(}{$3_4c!>RoMucV5T<;Y>URN2#Z;b+~-h5sV@C6SBY_y+-6-7
zHY*nA;Ria~bSeH6GeVTuoC|p$bR|l9zSZCY{TD-;kasU?0e!S;gtsFKzgH@=gpXx*
zTPW*lKDjNKqx}<b+{zm_Xt{3^yY+|^*wFSR0y3tgOP^1A0qCAA-LUFYYu6?rA-6Eb
zZTJy{*p|$_gH7qx#P+KP9orV#3K7wVgs>PFq@&pC`pVN+hoRpN&6{aT@I88K%RkRM
z3x{_$JR^S7&)uK5Zf&K%FEApZyD2Sgd|1H(Qnmx6A3y{_*>;R)rxYZjCNL<6$ZP!E
zfV=dY7SCt=a!bg+^q~w@S5(OGKhsC#T7A7dHNfjQ6%{*3FkbL<PqWIR%;-NZ&A-W$
z#v_~&N#3<54+V!^DSt)!z06VNeK0$IeB@m&(){<cCD6G1iIB+9bp6HE?w!ASSnS%%
z!sAn$M!A?J@{FQ*rG}<L7*l^>7v2B`a^!(mAQv@%ix7=uA}G#O-xvX~hIDEveZ`!n
zZt1^(Ug6{3^%OA>!roW8jfCJOoKY}JD?!Ksuo!hd6O?Hy7zRG1C>>uoeGQy<u~2?*
zhGV|o%L&iG*6)~1<B97j4-_)aNtm;?o5#IL*UjR0uEq$lhZ{Q;spf7CIwTSeB`9)U
z+4wAexr03r+r^+kre&Emq;^w5*1M|)1zTqWkiXyXZ;EFbbre?Fg$%Qjaf?_d0;yU}
z@Cqk3OCcf2l*gI~{jzkQZ%RU5<s^NLDN~uETKTUi>DRMr=U(GR2cxJMiu~7(XI^&V
z=FR84Zv~C^`Z$xLza2IQMq~gY%~p67H-8=Pylslz_?CTk8$KMu-fd4>H+m@u94i=K
z>i@i!SMP}ix;&f4^zBM1w3qs-Pma}l66b`j*;tyJ{wed){L(qA#Md5|yHZTEI{X-M
z3r_2wpBI(78G_hF!j{zdYv`k4LRZn!{{c5kA*n+yMw0?Bbm}${44*5FX}xvV2V&YR
zQyE5U0`{}|g)r--$BWOR8uPhnd!&*m66q7?e1m$)KK@)Xycr8TaZlMKqVtzs#HzzW
zL5jMpP9l3#vx$N<%l}(6m82z)beS$syM3_uR`m9JwF*6YekS2UY)QERWP7dNRxnJz
zldD_4%^zS#1zo0UKWPT_qO!Qi^TZG9oc{`mIvyQK96T3db?VR!?9zJqZK!C_CYp@0
z*JAFm+V-#WK3@eB%bvE9pfG|hu0>1`-FXbdVWNFXTlNQ^b%z6FxpvrHQk6HTJV5^F
z0-v0TYSlV^4*r8K87#IpjWx39VA!g+F-EL7hK7OFwj<2qP4<=#({}YOj%`NB=T+aQ
z-iF_Y(At@<k3SYGaWt4|@Z4Q`u-t*xp>pa^vgG3h7Yox^j6@3IPWave?z8x%prMM^
zt7(v^r_93_Y{sD9^?|RX<5tCf(O^l?WF1JV@Z_?dHBoaL`rKAr+xsGgxwt|BkfO{L
zab{;4`RalUGdWHV0B5!qmQ?3aZM`2Iukix(l|2Di)?Sak?-LUqdsbPQDOW>EPIGOg
z>!<*ZMv5kGQK>Yr%3axY`IM^kO*pJz6|A}#>M%27w(!TX<cit}>-Bc8ikm^#RAw_!
zn{MWjA4Oy9;HR2;3Hk0hzAZ9A&8r~>XC=Md_Mt5j*GO_{2gMmEs!cw!lz%4QH&woN
zdivo!5JVN|`J}$v)ZTx2D)qIgiNlRfuMm5midcRYjvh%HhP{LAvb=m~WSnyTHNtWP
zDeZD)&H*=A-y)rRKolLx(DzGrfhz%q{yz*L_9y=`Eswe)U~5+}mk7B9W6|}rGl<MH
zLL>?=8QhX)G%-9QpeYFFoej0N8^982xB7RR;3Mz?wwacXO!n*Jz`!{3Lp&bYq47sE
zEP70){)6x1%0FzkPqsnb_j*CTlZ^%KS8+ux+|5edI;d2-CZHW`^A*?Yef*XCwL?TN
zgyN;;$kUw1RL%bkYaYh`qphphZu*g6562T|rYtzWc?WFBt&}Hbs3a=-_g~uH$2c$0
zW<8!+T3RNtxgi;1XXLin;I6$j<)%0TE~0S6Lr_Plbf#u4ln!5rKbpU-`5E?sQlB`f
zbwBSX{A?W(4E7X6oKeiiN`2YhCgPWeBPwdpTIc>Xy7mM7Y{*txUT$Hjq`w6{`R1{-
z3Uw%xg8+~2lgP)?70LtQN91t_A;M%9gAHU~8hm6#s7PX+Zqw!Nr<K*d2Hm#z9W15a
zs=P4LBMb?FhHHly`F9o@CDDze74;rJO*q2fl>Vlk4V7+}w`#OuVRp;M>q!6l1D@b2
zAU`~|fyY%w8?~#uddVjo(F~}UiUNUa$waBoeh8R^%c7)`ND!)KSn;87ZDtSxi`GpM
zXonXf$lLR>%%2V><m*jmxm<+V3PzVfCrw@24#qdi#;}OkNE#euCao{he)GOJ<<>lD
z*8ZG;pdaT7kQ!o`(uqPlfqtmWxta35i*Ct{GYd7tWlDNrZfAOPf1@-0Kc{h@9e8>3
zKODDYK+rr_&_IE&733Rg5Vqu)XwsUZ{?wCt96(jP`k!Jw!5>f)?D|Ki8FD7!K&TL6
zD|<?+(92l2918APe^;5Zakos0w$nAtYhZ-!SoC9_Ja5T9Q0$N#A0lCnXryk>;%11;
zbZWEyfo1DYTG217@p0*mMIRzT#ZFM1pjyP8B0okkm}0WWuFu@BcQL9J8E*S2+E+}M
z)xi9#JIuA@nawc)_tKI-nH*^|d56w1L7QX>L@ADWKSlu4AdxktA9v_d_GiH2pU@L7
zlA@t*+pd48|A+3arJp18=3j$&pQL;gyP%CjRwtzu;DtC<Y;FSdBhVWZvFIJ>a9XMH
z3}8{gd1k2)YJ*AA=JVIhMTnahW_oBo#Xlr9QGDBd?cWMvUjyS$|FzfhE$0S=jKF=N
zWdOxOSX;(kr`W{Lw>1&7Rm?w}zX7nz;TgpiXjEhBLx}t9u0gaDR_tKT6d!MbJnCdt
z_bQP@BYNEjKz$+N&*!(?yGTcuv>B)Vp#4tFicKslkt~=kC;{5l$bE5s`WC_~u?qVA
zeZwT&CnYD7FpsQ&b*5j2kerZTZApoZsPJL34x8}>n1R0<AQ5QDlnEmi0d`vgYUCnR
z2TGE_=z{mHX3xds%ae39*+gu&0Pr=}J%mk>wPRQ}21AfksHWKVt~@lmgFOk1sh#Z5
z#VZAVz3RWs3f-_mLTRH(mF|(BRQ9R)+AP@<TSmM6E22KxrT!W!d^UJj{xD5FYDj7L
z!BxV;1Fwr!L2i?nl+eURt2n7^5{^k}Sjwh|6ut3Jj5+VL6?DD0aA3j~@c(F=Uctoh
z${0BK=Tp7hbH6G^)`sJy*}V9RXt_JrX_~Kci31;m!Hc~=kG&1NO&KxV2=<s4kDc8&
z%~yiTc>uJ)?W!6t)xRvFtv}}=ltmC779t~fUT6_J+_5N^zG)QVdx48f1DIV3Kpo6*
zC}ZFi;?^D`)`i%fe0Kg`)6NCK%Ytv)64nr%kLNT~#{*Kw_@wX;i*#0ulg&Q0st?L>
zbz_Y~Q!{m}z2N~muP4}9kV|TuSd70hdUoRES(i&a?!lzqG8ACqzI#`oqS9Fpwdg49
zEHULZbfwfqBlqM|+nd}B-^Tbh=Gr;I(&h3htwKOM%15_ePwvZ|8}+vf=joE^O0Mv}
zPU>`VK*@}2WInd|bDr-5J7Wm!R;gyV`|OG!suqNf@XUhi(2I$9yNI0`BDX7nJ|RBe
zcK3^r)jO?<;bV6v&hR;yH90|ekuTHJ)UY(Dq}|<u!2fj-N;7KApG)!cCc8kj&3B~!
z>v+p+caYn&P-}6(owN(f4)#E}`$#WhITeqkU5l*F^e>f`>MNtsxhJ5s7`HgW&}|$X
zeM$^AA_<GTSj3bt9YH4^1uUoWU_%W$gv{Nx6b@IOS7ALxez{CUOH1<Iq8Q`-qH<`M
z%DWr$ov`TZPJ>haQ^rl$?35)X)1|hODSb9t$&}ROG^Wyu?>nzj(fZ)3eEJ^Ur_>77
z2Xnt$&|Vu<XCYB1`rHy7?jKES&HR`w=kl77*_7A1-_UrU)nI$zPm^0{bVfjlT3{?D
zrNEwHu3(1o6N4~baY~GTsjk-NAOxSxjN+U_Cr<_q9%_>`Rs$*)Q9JeW(%^Yr3Ou3*
ziO$%>==Nh3MxZ|<-)eWiDspDAW072E2};?${)prTo-J#eOR(Fd1StRdIM*&Q@vSVB
zB85hE<f}TAHBkUq18Fb&c;&C-Iw2i6K0I_qa3`jsff{n#+9%^>b`u+0C0Uu47Tut*
z{n9w-CzMFMrv+A}O@PH}YgKKn$n)8IjF@Dqk2s<Hd-#XX$aukLMHQVcYIW+guY4(Z
z#?J<-J-6O^+E6hCQ3=W>P+%PPF@nrSvtip3UpBi5LEoc!9}Y&0njW4arl2NFAl#|s
z5N2xQcjJz0Dtew3kH)S23EWd+#l*Ih7Zgo4Qw)g_I<)09m{@Tb+q(D8=2Lr&MG3^8
zI6B*5QZGU4;i(7#OW|=(DN>h1X|Tmf$mewy`PrY@)KWg!JBFU^CU{QXdWXaw@30_{
zT{CmHXaXrjYVzg&$+<L)>f=3k8nE7XC`TIo&t;!qmNxii5kz`$EXC5s%q<m@Jz#w4
zuDFDGjq#nbhVMf^{n}y^V-6Gjm4){w9gnbb@#AtE)|euLw&s@H%nuYiXnpyWC2e*?
zAFm&JIVhQ;R*cv$B@StkvSf#?DUR{gp9TKQx;}79-D+o4eYKTM7Tzk<o&BT1@?c4h
z6Ki0G=*l3UVx|JoIjmb8THGoT;9oGO!@%Z!P_m}9<$<^~ARZoyh)Zej89Mn7qiZy3
z-8UY}uw;zT<Zd&40poHmvtz-ty&(rs?uj07s`!xZCr4&crzblGqAh9nZ^;i#=Oiv&
z@C8G~jO|To3wU4sUyOXwk}j+%8V2s@V4(!u8>5r$UAi*-AK~e4RaeGA{~1W$#=Y%i
z0m1(rP*DG>l8XcN8>9wn{S_b&0-u2A@UfDM@<EY=!^p24ug(A^g&x9Ln6{S&yr-54
zdE9BlvE^)deu1Nr*}Ht%TsglyL#{-M!b-RJ?M5%Y)4`GNW6u7!wOR;QkIz@$Y^I72
z(NB=~XBy8$-}{D`H>%<}I#S_3A;v3r1)NT;ht`jzcHHuBF()Ou$3G=tal>H40UcV(
zKm&)I%F!e1AA>pMQObQ~Ft00uC6%ku2L4yp$|X^7SIP7K1`ydt^!rc>ySI!%Mo_-h
zQbDZrl&_nS;9*<~U^aR%nV>L42yk;-tAMZpKj1Sq3Tdg;c{dY809`Ilyp0wKLe^R5
zPF#!Bb6<cpR`K`GHxPMMBze&JiU#Ljl5L^ZfXuoP;CL8Vb)NEg;8i>$*Xp~cg+H3K
z3O9?B63&K($gOjBYlhEV-DIewV2M<^R;a=E7tZ1_U|I=xsat|tbBrD}tJ+(ty;Zo6
zp#nVkn!%I+;%jZB>4u|RQw2%OE1+w`Yt}vNkfwc~G@xiwzTntBb7MO{TJvKFli|Ux
zKE(`8Fc<9K20^AEo|sXYR0<P})wQMK+Chq=Q)`a)w$Y29tx*E`p|7YA*@u~QtarH3
zogk@4v|$);whQY&`sSNs@j)_Fk&hrA$9i$*VJFIVE#8a4<bI|v^xY&@FHe2$nRMrD
z{7pZH+_E+F*nEiG7q{j!xrM~*F8ETsHFQZcH)T}s#A?Hq>y4@GoCLDF*fOAaETv8y
zpw9F=1Xn(xAmD@Oh^0dIT_EsQWJS8CEVT1%;GN}l7!~sW1u|3ai~UMr)-r{(>^frJ
z7B(2E{v1e|cp@nM4cPOew=$qbn^mu#WBi<Em@Z()ke1=0U<0AZ(8a1g1TQHf66NGy
zhuia@^3FdT#(o25eJ#D<GMmi6YzRRz*sNIc%%@GO!m7*k_hV`cB_h5)q2w9Mx}c~)
zGH813)KZV8U77p$xSaL&Kwx5!pWbvz%YNUpFEj}+gFR$O6v={;SR=LRSdXJRswDj2
zhhbsH)1D|m2C*4KpL}?ZcofEpK2h&QpoH5>%XP1E(~%aL`<YqF#m+sgtvWVu!*?-O
zUCA)oWR^GqL>M8RFWKB%GsI0FJ4RIJ*1Q>snl8{K{c%^W5S&49=VI6pO~~7xdvO{E
z-~Qv)RFRiuf&*i4vYkJGg$?rijHh9nh?b5fbjK$eXiHYp{Q|spt$-ms;pm;?|299v
zcnkQQhNaFLd#3ZySgj^0l=}x>FjMlWrD^uHKwzvH$WRO114SHtMsdb<ca}EV-`ceV
z=2!zJ{UXhc&}PuZldy+$+6n0S+EL2w1Z0iYL8jq9NK_8rzkT1^n<52E$i0quR8)f*
zj!7grs$lUSb0fJYh6lx{mEa)KejUYZAmI#-4I;p>tK`JoGBLydPw1M6V?4hh84hZ)
zM`JNGlJ6+rNgocy`huy~FJ(<}8CxgB;ykm({)DGd6V7uau+0V7i0UPfx^ch%@48@l
zZ^}`biAvhSMrUhSj>Qs-gBefoAQA>~&o1d@?k6eS^LB{;*cG8}nsSy`5-^7Z4IOb(
zKk+Y<2hFj({?-5^b#Oe9{Q8L$U#AX<FfH@$?pq1RRU~SmF!0?+=|_AZ(1I;5-hn4c
z&fxY^Xu`?l%0w%I6iY<lNeliJjsdUtC#JG(q~sCPJ&JkqBki3xiXG3NOhYwEukr00
zmbh#vF{VVHNH7zLq1+Ey!}cuvxt|eO)}iQA6F4Y#noK@1xdOc7ebliG0fY$DC>;T=
zlN~9nZWkMZ9smpE8VN{EQkxm#lryw74^9J!Fg#fa;1~dHrRjEPF|bE02+aKZ&z)mA
zPMNS&m=(xnR+o_tE66I&K;G#g;~`&RFQPXxSRV`)!DAjE6L5P14yvW>=~q`tr?G}u
zW{~pNESn7d7RP|cz|7&|Cx?_#S3X#3%P4diI2dnl5?4*pc9l&fIh6IO4368g6J=^F
z?NsMFt}Vh7T9}gRd(fwt5#RHDP^hE6|64d(vAu6szDs?DZcfO#o}YzpnL7)>K#!?2
zfjgVJZPn;|sLCn?aPKJC!L<33(|Bk@ahCNAUqK?1<t&0CN*7Ff5tk0_C(rwQ@kg)x
z__0Lb{8x!aAuZS_5U!{o(9Y))veI6;0?Di}^=$9<1(^KS2W!@6kRBY_AtUBMAaKOE
zlN6I^a2N9Y;?Cxx`0pVGs@(l6Wv^;sdo(l&KIgvKP0Veg<v4q|oUos#keZpUMl1SM
z8lBN!ooK{PMTG_pmYr0K_uB766ol~Y4aQ4)5Ye?>*}+i+s9-N}K>saBP5dOqmj~0@
z+lLzWr>XBjuJj51ImNwBM0uO+#3EubdmkiR$rBKzq2UeR1bnuNiJ}O~#LFR~IQ6W@
zk*d-6f|Ii-*_+val8<v2wzg_j@Q$cKV`?q1?4JLgo;c3J^Neh(SGs=?uCEy%`Xqlv
zV+jyX*Kdt*!{Z#3=Oa1HBz+<kJ7EWx8&`QtP4{B!w!3ns_LweSzo+6Ibn%*u^;$}>
z(qeSz3}nXSqlWLBrR95wPSW?go3?=I+I9*iw#?`xZUld;V4iT*Q4WVMytikD+UnMC
z1jDjn4~upvdQ^{~yDi`@;g5^CDjEfBI($-=A>%5KT<5~OxZ-g%ncua;kk}ca_5=g+
z3<G%vG7}Eusrfv5Jhc=AD<6%17ZZ-%7cVLsE?_VL_~)LCz00CVt${o%a0r?}@-~Sg
z9fprcmaG16t0U?Zv1;S|o+yW!QHRTU%r%LRW+q?O%8rZ1kqq`wzd#)w5I2NphmD$n
z=$OnDJUZpT;)q%fYq{J82-9=i%A|U+VXu2;^>Ah>!d&Fw7wKn!)bJWM3U%IzoqHbq
zSuvqHNwd(>1n%PJ=EIOs|AC-2MXgc5izn5djSnAehNBW$tJv1pEzG%l3tOxpx<G}A
z&ceOBhtGVKt<K1tX-BT0fldLOWJO=)x016CY6m<{%9Xa`2)zSYGJk9tB%dY&U?2@z
zDEc1=M^yD8t`wWmI99c3#|t2GQtWVE=>oWv9^SXPXUll}GHZdJu@glH9Sc9M;GUJ9
z`TRLlX+L6j)pJHO(QE8dk6cOC|Ka{Ah|Paskl@$r1}e!h0dnD5vKDZ+yCc>o-CWyE
zmotw)@YPfW$sxPCXQXh=^4KW&$Su@MWYmx+eQ!7qO#1pW)a;$e_Y#kNEWDeR^r(uX
zqvvu{(AegnbLgiFr-{C^(L26&(!%r(J!s-~!W4X*BEx<5B6XN`4Ss??Bj174#b-A$
z!y^`mn183Gygx|9gH<BpV38x!VY7ySqUOW9a#%5_2<$F%4t!QaK>!Gt*f@OCIi{Gg
zH*mLF{gem>@3wRC2Wy!C8i3ov;-ACo`6!IviC_dD8hL3OOaz$jS-XtLw+2<Nqomlq
zl(7CkZwM4OlJVMO&E>%bSbTeT9a-xd?7uy?3Y2ujhmaE*BFz_6=Xsc7vsk;dAF)Vg
z*O0CpIBinB>w|u1HQAh~z=>`pWpz+Ea@Y~WEEE1EzE36kx3QUrKD|(@zIeLZ<Tts7
z*sxGun9X*Mt?m=_l+-bS*dq4LaDf_Q#7+a?R<->}k5a7?W*&xj;_>$SO?c*n7!a)z
zq8AiE$$ZU1@rJ+UiG(4FBFSP1O|EhE2v}M@`H34Z>YPk0?g`d^QX&O<lgqv*<MDx8
z*{;zt6C10SumIU9?9XT|DJA|d;jQRdDAnB=hF@1{%gK>RU%Mb46CJ(jQ8z-a4Khle
zJ0Y%-P)NQXtn->aF-7S3vYHunb8yL3)ttTTI^KrtZi~Xy*Av{pwX1OazcXHI__}se
zLmk}skV)8Bc!)A4er#@SSk6f-suF|NGUHm~2bP9F&{`;h9CY+XbG)zL5yNy~nd&ga
zP&Nqe2@3jqlzAq}u8m}b8TPp!@WvTM2~G_l{V~fTOaDDN%I+TrkS){32lHEe2K=zF
z%FW{~78XXkZ+x?yM1iW2Jp2#hOF?}?Vy)L0KIeO3;oHXLo9PimEie4`6bZ9)^Az_$
zlK#zoLso`g$lajaiaZ}GVnBj4pMmS+X?k*(H%~f9h95zkzqkT52~9HqR75^G-$`8R
z46T(WQ9f(+mmUQw!4`umpJ<`kzGJt-g3>=?+Eo=Qs-3-${;02q&-4ULVJxWAe|w>y
z;xFC)cOg*K8%oCl5+#hMK<>Fq)fAS13n%x2H&tU<<Q(9laf_uE&tR1ngx)$ZJ@sEi
z)_q|~f1`p*(7Pqj*tb{{zJEozW+)J-9vdFG3w*QjZiCnjX+i2>by{ze-BNtGm1VIm
zz_Qt`GdIW69+xbI?=nu9_vyxwe^hZYTX5hMq0KfmVdsDQcY^8IYS$ZD#lELthRS0C
zrEs_XhlUc1^!sr5@@S!b{rYFRBCdN_4iC5qeM+P~qp>tF=sVp-_aHClpa>E1-0pL`
z2spxKy{(iU;k!l#ID#PK=%Q4VhNp$r7Eo#ze-V&J#r#61>aD(SW@;}h5Qc02B+CJU
z=VN7vRu{AlEHbA_9Pxz!wPgJGiWb}%Ef<|T7=wWiu_<{o&<&AZ9o_xW^IaaLbw4>2
zADiHzn!V1RaM~KE0Vj<rbv>M}p;@1<{`O!Eft*fPdse!^fn8B`*Tb9B4g&dn-{62*
z`3Z*Yr~BbS1ulUt{O}SGa#KvXJU5#Q1=;oi*=*&kL<>(vB~lU%PXz+TQ>7KH=liWj
zQpiD?WgYG=!%ReN7?9zskx4g%LhG{>>#h|{a_6(^M>7nXjY@H+U{Z@`(WV6f>aVnx
z^k)&!DCEt5)$YKy@<4>iC{BUtoMGJNjc`ZzdrEP~+H~f4>}!6~!fsSyx35#OU@VWn
z@75YE6@2az=CF^1*fSBy9w6*jjJDm{Q$zrmLQgOnc2pn9c2yiubEfa9_fyaEpOal8
z$1o9~zZ^Zwe6`xFbZksp52{@&khX03DKzUP!Rx09$4FN&Ab=K|x<vYz*=M^A;~03B
zux!WYf&5q)MNK{LP4-?xyca-@eE^Kk1dR_gH)emx&J2=RAGm)C9EeGbB=1++D1pa?
zs2h{Ug!ysgfN!6pB*2INX4KuzJ4*ixL?r2^Hu}^rr(@$O!Yy7JkM={~U5vA-@D?Hc
zYk8g~TMY(9P{cYQR~!={=Rn<F=9<J&2*YFNjQ76Ohf4%`C&mE`_>iR%>^l`5;$GOK
zvxg9N@46$+Us!^SA77;qVxkzkrjdgTd2`@d%O+G%X$psQcl6d3adbFB^)(#oM-|XQ
zCq91Y#*ItTjVk|MLvXiNZc%_mG=QcKjVy_G;Vj}Y-2zwz*ih7~%E-p;3KMnDOK^ZJ
z5rdq1Z1WM`pM@bz!&nZ#SvC6dUSS!58KJ&hBk_6Pf?wndY+nlpaBLCt-1zZKK1tdV
zYuquU*P>*xI{S>unUN0%@BX&Zc&Qf2y{)ZQ_kN0s*zfmll<!xS+D*|N?59qWX^MJx
z$H1wyt%pEOQcz4K5uo-^`mvQPGJ4_*v7N`Kq)D}9bKC=7?r^DD%_9T`wEXSHg@gMd
zInZYi)47)%Q#&_1dpyc6_a1b`(9+iupBJOUfijG)cu$*K{Zqm91sKvD<qirPDSWU+
zK8I)FBUe;Grry9xMgRga)^v0oqH{Ic9$cYlC@nO`ThWz(LaI^5hHx0c5VeFy3HsYh
z61-oY#?|v^Y(~0VTahLlWhZi#x(egI_tX9EKH{&Z)|#c}0=-e9Chp!3_5iaM2vtwq
zCYf(8=n(q$Or#*NV%q{;q>GNghue{jQOn&lG_FgRAWmD|VM^z7_UWst-`%ZTZ@PnR
zv7>(}@9F@o2m$r9n;{oBaDsAd=NA;p-VMuGDmmYxYNeX`7-PvG3|{GD6Vv?-bFV83
z*UZ_rx9g4n4Dks?+p?uw-R5GFj@#@A;=HrMbUTr<ZBw-?4LrUH%P{B?hI-q8*!w$f
z#dC4}9>tscYM?5CnF?svixF=;!k&N~4VzPl|AyQ~6Rg<PZSWT1^#z}GC(7&d&5;eX
zfsy!*S|8|2d$g+Sf$w|JVW_ApOC5?MUkASxviEE(1(FQJ@Zi~Yhgk=#Hxr3#`E!WG
zFqpBF*AxIpFw4aDKQz9(mYdn+wF3V*xJ#okGb}$mQ|*?Z)R<kpPoOssgB^?!p8{dL
zWJCT~Ny(;Td!ox#4|A#A-Tor1sw}=mvm~IiztO?Yb{M=7O20W%Wj4b)eEi|bet3hs
zNQEd(B0s;1o@viiNRq|z4;gH|@agCv%Lua`%#wVz>0+{Zb))C1NGrH*TYGu6I6gi+
zNRTG!_?otXC^k6_>;18LL;iAP$SL%?1J!_)v@WGubn698YBB+@z|PE1fV)5sddxqC
z;R5RUNe^@IxG}IOtt6i9pO2A(EGt3EHd~8jw(ODp^>BEW+v-Pzi2>C)c>WB43Il|z
zR@e}ZidNT~35@*6sWt*sG)c``vQqjYA~3MjVLDAfnpMm>{#<LgD*)gYz-c@%0)P7I
z^m9sy7)2VEh=q#_Z|$V(?+T^R#>w9IJ0!Ogb`;I|l^eEsgiLCIElV**{V*N^P?`km
zJ`DV1SjzxZ*mUWjt3)y*hlj|`(vx3JQ&9^eDLjVJ%?=gj{c-G)*W%>Hwv!PGMak}<
z;rhi@x;UJMvZd3V2rp7I?DI)eJt{oKW3=J9`k_fpxNz*sIA3I<PfQ>IXx8L@q8CHh
zM8ckbNBmefK*3~A%5=$>Yd^JQbSR8)T_YAXC*g)QY*{3^NxH&jSEHMsBZuy%oF&3)
zIw0Q{)lAhziu6LO2}JO!ItMU|7-nHgGf<O4N&s=ktU8en`odIzK&PeAS*;IG4+V0i
zOOg2%LJfXYuE<&j-U9DmTDH5NXxNC^mI)-W<}rO8+o=}Ja*Jx)*ziCz=OzZlQWog5
zOo-ee0=F@z)u+&*9JEjC!d;er8RKwAZ-wKh-q^x@yTx)^q{=XdavcBXNCrtz*ECJc
zmgMjgEa-6z@%*t}o<)74M@38zz!j6h^t}PBCsk_<6aM6*Z3Ue$M-rG-@s%`Cx)t#M
z5r*+nH<xsOL%J6g?#E5_$C{^)vH969ujBZr4}3AoBoLz<TNrgsp+Hf^huhV^t^_^a
zqquLyDnM$yiKEg<8`a+laaFuRNt#a$aYt$TabiT8|H6(Wz}APEr`Y57j0XPY<{7E^
z_hs4~Prt9f)bxjUzR{DI>FW`0PtH{$i23?2psbfHFN*Se!L3Q3%F8@c8~XVc19BzQ
z{{77Kf^-;1oV-~)Ef&bABQx@cCt;U_d66_oyf!a8iW}<A3Est1Y?XVMReYAns-@!Z
zS-v$SYKQ|QK^RR=`aq4X%I6xPPMpdM$k|rx7@ciq3#5E8SM#>#@f3DyU3BStBwaf9
zHlJ0A4!>UN0{RsnNN*EEok>{10n#uqu`HTF-yJ}w;#k?{)dPp_8E8K4+|oh$n5@w;
zxZQ7LIcp#w+tlPMPyRq?1UOsXHHgR>Ml;dYImjo>^5E&_tA0YZl21^|_k?E)VH!>s
zT{$W1FFRKQkTt}57t9iFpoXE^7q%w%>n9q8G9HS6^Rt54Wr);sMvF@n4$MD&j3%J5
zpq?HB75&^#J=W&mN9=ZaS7y|oztMe0jEh0pcHS_Ip1S$f^)fTr^`&nTyN6gE2_UIF
zZxq{iXrXdN30%cHYh}CJ@RoEKMAUS|O3gTRQQ<WkY$Sqgg~{L-JCTlw^LQ#bSi`z$
z@NH<COtuI3!Ww!~wvSw+9LnHMxKzv_S+tp$or%d{CNly-oJC(-thw)zAtF3|jQf%U
z5sAsRM8ca`<_Kp&g-O=9+@8{~IKlJf3phh_xjH5u(jCwXX`u<S=pG=(0J~-iVjapz
z00z=*=Ny`MBUdRP3myBHsUbYK!l4bjg(NtRhiQu6XxGk`|GRhaFq&jOVgJ|nQ+Tv&
zk0`38bdrUes!b_bN--lzw(>dpS4P|~)gJ@V=q7f3GFE+}_RC0q5$_j99g}>FCb8~M
zI<xD^G#=1#H>M}fr-jN=+LW<&wgf?Zfw)@Kv|$iz`jR?j2Y@0`@D!{8vYR)Fg7jA^
zUg&XB+Ny=LT%sY$Y(lE8T=h+hi_p+wpV9tJ**{ND*txXon+P*_gS>_E$YeGztAc8;
z2y31adA&-t>Tx}4)C_zwb4$|O<#xc4IFVVXQQUO!)lw=Gu5jd=)g;P%2O6ouL~0?#
zG^W?W=VkAWQd1R--CzzVC;4rZKL(Qu*f1?n_zZT!R1&dY>*jjY<{4r<?C}<-0&}Hb
zhhmRovx~jjzTzK#ed#vo@EY7MqgI%#DsNRZR!uckU9~f37o;HTUZp@SG5vfQIc$!n
zh;kLGE;yLgwEMhBVF;V$^nSMft4XE@I)0`AEz+5Yq^_k;p%!o(W=wK*5!>IG?1%yD
z@VG87Jo1g!2Vx_gswj{k*?Yv%3`x-KZmvs5)A9vB2W6Pj7}bK67=?L!Y)D)tIAVsy
z5Pnk^ANFX<{d1@NPhCH+vPOWNZC7`Xk?Uk~dC(j|9oG=_ZveqLNfc|PXm<wnD<7qI
zTADQ&t@?i@ms<z+03I`ktj2<TYR$^&R;-KJ)K^qtDPWvE0I@ym{XrdXVx>Y|-4p}}
z&pier(YMk$skh5u!3Pm+mJ1opT$ZHF$on4&Ip}=!K59I5Ju7yxHoA(T+o=>?`E)Fe
z4~>ClanF|JpvZ6@o9PIUISFW3IM;)NFM7RE!#_AevLYPawXR1yk^|ugVB*GU(H%HP
z&uFJ?_!HKrqGx8KK*JaiE8EhLykqM_tk#-I+RP4Pnisq4Q0Vuld4U#|6?1_R2GBg0
zF$hdHEMlFwY0m(cx_Ey^O~>K~Y;Ae4P%mJv00?UIsLQaOa|({@LzQ&5t^sI8Ihh@x
z4g*|jWRtKxjl`f2s}b1TMGlC(ASJ(CJpdNoc+E@VZ4oHll2M()5<qm?f8cVvc+bm2
z8^%SyDgqx?^dZ$TlQ7Lqe;4RG)CY9aT1s(3_(Juhjc5w4kYYQHUc@E}yvl{X0p~dR
zk4iI#X@v-f)<>!jFHHn>MqA-CcX!$Kc_$FsRD2YUNfgm3FcF~1_Z7nH81V&iJfet~
z5#^qN*|v@GhLNCCzJ&@LmRf2Qq;o9pe}cEv1>aD=rPF<C&2eC>ra84d!pLaL$4{c{
zKSf78{b0+v+%R~^*$_!8fY56Zf~MaE&p!{B_y>B|p~`I-*iR|XK87lpK}C#pmKtb+
z23I^nMmu;95TD$yIXviF4Wi*c`j69w+A;i>=b&15RCHY?nYgEkQ*5iIm2=~o`?gjt
z?wMdnwr<+pbk}+v@~|5Q+lUhey6};{KAm6-CBzP_-$}B0B?r*8K8Y*EfY2J<GWPPW
zw|k6V0KU!!x{DKS8k-7dnHlGakM<p$J?+@~Ji^Dk<CL8o<Lg>dsua$<PHj~O))_5I
z_KW&>4{*1}I9wg$?0VYpv&@+Rg+=gDYgsO8of)iqqxkx(p!M<{a91PHH!GC{y5^gd
zx)L*Q7|DjH;zSb<Cjqlf6S`#3)%Vshf2wTO!WTR#a1#~g1U`BW;p|#=>&C$7m{&Kg
z?&nT}7rxY@Bw3NOO9$UUFCT)WpV4#dUydJTK2<>A=byk0r3XUJ|1$p27ng^{fb11e
z<}&}_W4PRyR1x;dv)3n9TZme?eA@IoD09=txFHd3!pn^!>x)-Sl3{kJHs!uP&Q`Zo
zBibh1wTfP&-0gVf2h<>la#X9$>;^b>kn&}_l-zt=dGaAt`lE5zJ&KE9(Faqy_n=Kc
z@PU;!L<XpBtY|^6jGwB&OFwzWJPV<WH1WmuCX*i!%H|)sH#U$9RP!1|F0Sg|Bj}wR
zyH(u#5W28*e_U1F@i%8Iuwt#OIs6+9&3VeriaXxpe^Hiah_v$1$~WI)8!cNdOm8TE
z_z8NjLhVauH}~bu->7*Gbo=Mw<eX|S-u_GyD*ox)yZ|rK8OHs%8|yJ=l}C57RVi^Z
zG9%p1v8(Y=ul&Jd=v{bcA`4B*`11i(1*-b}do;+w{Qz$2WB0UV2YOj`oM{Hys<=*O
z#`5}cK?H=Uvf4o%qDC`E2ydQ^SqZ>>Q*wMpkMxEn3U$-@l+*)HoO$jf52}_eSa*8e
z8M*izG2=q}QKw0(Ql^Uk-@WTO^uyRp6=Q88wo`lg+B_PHj^cP+*qWl8f^s~sdSI%N
z9?c$CcEDn<zeDCbg?r=v$u#O0vOvFHgJC$@ne@QW(!$MlrikCB$80O;+ND86LM&20
zQ6o(am*p#Z)?@#Q_0~Q#?W%m^W8=fQ!CjA)QCvYG|4vu-H*%!B;80b7hM<u8_gsyn
z%llv-iv#H9W-vZtWoMqNc5+IVorG(JwduM2xda2+t0~uGR|!SmN^VBv#h}eN?qU}C
zo@u1TgKHk|)^p5UbH!$S59h6Ae`Cur4f$z*AIBL@=!KdpSRcy$tH>$ja!+AGf;-Gs
zRxf$j&((U@0dKhbJ|cblj~_mQ$%phQ$u^Z*)aoYr3b6A_z0DPBEnsa{3}0Fz9fM*|
zBqdkWzY!8jq!?lCo9trC)`d|cNR)o8tp^Aos=1hANINAfC*Mi2_be`~F(91C8ofwL
z1T#D3o>2L+W)HHW%vZ?Fx>!h|;JWQ->v##f?x@cRr48iY?=Pa{7s)+7!ZXPC+5)WH
zr-F7!(fUn+{G_K&=O@cu__3HGA5`VTk%lj>F!M22MI?w#)+U=bD7j7^0wQ!D{VrGZ
zC2Cs1<C$mbp_95=8yDNL?fQL1=5q1Mq~OzB_2+NC^5~78TAQ1om&UHIinun;n4W<!
zHv|G!X>kKs*CeHqB8Y6TFKwpys=1WTNcb8{AaoEr`Z_ga_XtPAOs&?>GN&w_srP(L
zY&TF7T_)(E?6W<wNWv>P3D2J8+^K38z_hXpmJ&BuQf;2FR?BrBA15e{#f)L4Sp_39
zH8gx^Eaiokj|oaVh3Ke9(<{=Fyx>HADE%DH7+S4cj6V!%DK1kVsqI9pLB&S!oM)C>
zBYon5$$upOjQn~LrsY!qH1Y%xrsI|l4+GxhD#UPUg8Od(A4Q|BH|pdI@ne9{EQM^%
z0Zez+zxh_#&7O3t2q%ZaO@hubF0Lt-StV!2(<2^#NSB`#szKbhIFtQ-+EOn1(Ot!4
zMs9{0AcsVSQ~3DL-DUnKyfVJU@l5#ntST%c(D|-`a^|QjOcN+uPB{<6SRvDf3G`O7
zVk#|RwD9JSw;GA^c^!UMOfY9pV**B7oMEYvr{oLfJg*~Mg`1AS5*Ba!EL_Y?SP>%l
z@|x4@2k`<#OPjG?5SO=vr!!m3(FL!l$Kpicmyd*pbV0cQzh@&8cz2z$0hpzAQpvn`
zUN8oI@H5~9WfnucT1<@i_<HZI@RV^c<_XgwVTNo0&g#7cX3y!xlVPJ2MKv&dnsM<z
zXnvG8S9jig#>B|r7Qw0Bb>dyuIC-f1cmwb}5@gZ&YrY+lWevRt&QI?SkS7R#o(txU
zG!5tm1{L`Yf^0eJk3X;|RIa29Q=D4{v)_zoy9QP6NOB%<c2|5lf?&+rmVsnvw$(qs
zg|g|O<~V`QCp96<l}aJxr?YZ;?=HP@GGabs_VHrsP3v<#&XL}QFC#3XuY8p1qQE&Y
zNw}cMS61Wa0eHf}W*mzME_?9nqaWOaiPK5H__O$Pl%!=VdDDOtY@^6K67$6@FJ~Ui
z(7LPQF-DV&%Wwnx;8`*HBaGY!bRT|Yem`Ox=~e>dOYjI4iK?tjM*=P-e+YUcZI?Cv
r(lA$tDmswasq+t_i;lz*2O=>K&6t6Xx(RjAwem2DZtT_Q-cF#oGwg$L

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..e158e5546ba1e615686269da07ca9a0379654c30
GIT binary patch
literal 3384
zcmV-84af3}6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkmQ{ysHHg<{FCAO}3bAGTL?zPps
zsM5AFYBjZ?0||-y0@oPMbBeSZ{lreyekM6^VUq_mb?uRhqHoGfd3})aiaP_x3&S<#
zF*l{v5cno242DZ0oN__$YrACUlWmsVl}~)NEZHRSuM`*1;-bdy36k)QzI}7*bG(Nh
zkk}r~HXtEQJGlkz*|YLvw-$Lx;0u^(x^lp+j7lPmrgJX~(vIYc>z`Uub)Gptppw`n
zg%hAS^Cjq)N{1~~jv8z2+5+w`9>gjew4K!j{Dd?qN2)jjEb_ckO~!ph<V;!$-DRb`
zgy!}mJ<r>l7n4Cnqc~*pMgi8v_ONOqh+M-c7L{S3ABp)Je`*m&>bTu41ltD3i9U7S
z<jY)e6&(=lAl2DVMxQxV?idg{RUvx30l3%G)F#dMA7iZSww1V9gn6N-dWjF;Gy<JX
z5AfB_HA~#@P#-x1u3Z4Rs&VlosZfmAf(&foDU)x)P*0o<ehQltG79=JjQOT8`t+77
z;5AMMz8OrP<J_9%4v3q2?R;vkr%yWRlg?l|&JXPT&~)Tw9<y6ObVb#3l!6{#^h{E!
zQb5D95VoPc0%{%B;rqu=oNy;)_20f9ulCl;WRE>*UU_`g)GU)M0ZQt!c3Q2vUUG^P
zUV=dGtP$+K;P0)F`+P~{GiLqkQV^Vzd*Ag7V_X<Ke>+_uZ_}`rIpM%Jd|g_AF=Mh<
zk7Oz}7nUi#%gtP<e}EYJiIe4fK8g_C*XvstQI`Fa*gM|Iw7u`w#dW(~!!IR5%_dHz
z3yORsxYaTq6f2nU-D1{{REWh)S!N+SLypg6$Qkvv>`uw)G;js3GCAkhZE16!@Gv8N
zU8K=Kp6;n=R>mtu2m?zgG2M!x;yH4lsJ{!tt3%{BdrR>sr+&w){aWn2nSlTm7B%0+
z!U*Q&5EH*T&GjOB{sa(cmc#E&jek#98I{R?O;ZxUnB3G$Hc2MqmxrlKwsZ$Mbg<}Q
znqQm@6jH-{<SvfdS8=xhFXuqvc}6C2($!|4gVz|YDR)zC&vH?bEeU=n*|=Jhg(5Jo
zxfnEa1c|ti!GktvIssG*ZSUc+_7oS+ZcT4Ff0`xlEhiP5)z%D`{Fr~OTj0F%`IHuZ
zrwi%*#Xk@xukG?!eeo_rnGk1eHZR}f#}j?-XZczJpTfZ=yP#Eibu(JoXVBb#XitBR
z_!49Fqz|dI(Ja10C<_rW1R;GBq+s_xmbd_PKfp*-=)E|}{Rh2(`Lkl}P7H75GLVJd
zsm{J*J}fzOw@r*Uw9L+nw9??dD{pgrlZ!w{aEH@~px2jdl)?=GBBAc3M)K8yK?|6$
za`@S;;Gh%DX0Ih=CRXQ>$9KvqB43(hgIh(T&ZZ|~=*GL*G6KSoAXiW>Exsf{Wf>Rl
z3yIO4rL5w7=5Bxwewcro1`b6MqLkh0J*4*oOD6cE%Hu5>FO6a0gnex4$Oz{EZp@1=
z)3G24gz3t*a(4=t0)rZ-Ru(#c3jwP10u4nO9P~5YdeOIx)?sw7HP+nTD+x(GfT&gx
zy=}k8xzMa(ym!dmY#+uVeoJ{^5KrS6=rIX9IgZxqr2Q~qh`R_<X~j&)zB_d9ZTHl%
zAPFK?B^1(ss2Nmf&wr}{5G^osrE=qARvux0!fpn{oy=nRB&TUH9wNE>NORJTt?dPp
zJ;Imajs$+9R|4Lilk;-tp1&PcJzCbrJ_HhVh7>Xjb-O1V(^fkjmG5}l^8p)8lAKHt
zQoRImkTE_*Wk73<7PS!bX|46*HWzvZSfWG_eL8YJXb{*9J)P+tP7WgqQtMWop0zb&
z+L|$9<!UjwaLcasW289!)CuT#_QELi->y#KKtBbQi_Z?ZANKo|$7yI+qrWWCZPNKI
zy?N3xaHa0eZ#kVxAa~4=Km2I-7$*6*G6p8}ObdCH)FAA=ggZxfCxu1>h?l{3+ux~I
z++Y4551D4ZA8k~C<ru+Cof-{TDvoy`R8IG7C&z+-S)GtetM6zcY`Fd6VK-$9hV>uu
zwcplTP?r<!*Y~Z<tH`ZbB81bg<f*hg3lzvVfNVoWrEjj>O4EM!&~8)J{EnsW?O%*(
z6dPq~)GTMuUT6o%O>PR#@h@Gqj-mC!sZnS+0^6G7QRu9YC0wO|(R_!%6#{Vp@P=l|
z;-%tRNEw6fWz|+3zL?2Zpb8}|4JuYFy}0`U9Wn<?6X?sgBZUt6={u(rLpp!lxPf)d
zEhyX^b&hq)-^&Y)4%^2dz{XO9x+f(A6z0-zU!O>W3W#cHA+qMyg9HISTV4W%q(~IE
zN?1}4+ai4`m&c%)oK@|Q4pD^@e$LT1^QM$hLNsT-3HgnM-(m<=Ic*pI9M+Uaqk$gR
zt>Hu1rAGYCWCrv69*q*Xfk<nR7y9-zgSgGP^!=(tb6(sykbUX8wMO<TXk9xq*?HE~
zNiKTP%dax)K?~HcFX+1Q+bRD#D?<?ZPASqhFT3Vl0KnHjL??-AVz_IL<q`@ZcSbxa
ztI@9t?JD!PD-QZ>XfjzWP1H!o0KWBmrg!?Eu{rfNoq@@`6})dMA3*za=J7V;w`Nx6
zei6R=uK*G(bpCi#Jx>SxXl3!xPt3Jw1yb$|Mvh43$#%0X<jO*M(q&YPxh?LkA|PI@
z?g*v5iD1X?`~Rj7>&)ezJf}@Ai6l^OI-1UC=xy!;GCtCpa*`e)W{gwT?4OTLQ8s_c
zrue>^RZ;%^r5|ONOM{oJNL{b6tf5eGqlTbN6^n1pfkKb+2b#tq&8Cz8i)Hu#O;b4M
zY1?=Qkul9|%VZeIQ}nR{;lMnkS71Lpx#a=t9<4YN2xQS`JV}xSAV`H3tonAisavkk
zugETCaTtXdBvqb`#^qpd!)F#*9Qp=Mf)k!=ND&tfYQOT{h-~B8Z)~oOm12Lw=wZc@
OP2EwAN+Nvt-So4kXolbb

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..dde16bcaf68fb31f28fcadea8d3a7d9b02609199
GIT binary patch
literal 9232
zcmV+rB=6gc6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkmQ{ysHHg<_S))lF7mB`b`t+o5c
zH;U)O`V=Z1=ZMjd8wys$b2H9Fu-$28anV>3z?=eV^GsD^ENu-I;9v4qJ&+<(MUb}k
zJY#qwD|2<LT`A{=a?tk>x|VsZlA~^^)V9e6F_CN#Q`V=|Vprk5MP=GMGEX!=dq0?O
zFzhcw7vFG;jHmOaoBR*D8=}6mnnx_b<4s6q9PQfBa9>3IX>&Q~;J7fWGy_obv7@ev
zOT8sT<VKTAix>2H-(vbct~=gOPbp#Haql6QRt11>Rro6rRg!dpkqiw6xZW;l`)w_3
zFS>Y^aX;ERr+k!Q^w>7I5h*HMY5qIxzQB+P%An~dgTk;7IRb)WOs3_gX0j~uBVMz@
zLhXW|LNiT4V0KIt6Br7AerJllv@4*z-v-yF9g|bd90-_<?ad8{YK%624QvBKWSb8e
zRrr0q8a3NLoVKnbRjiQ#@q|CG?zg^@{?>6OH$$7+i3xCVk^l^g@DVJK-y@9ER}@Tg
zjD*=8ZUM4KzEpLFwZhWtXfoK8w^8@gj`Zzr8>+;|4I(9dVX9T(Y~Fr;w1E)N%PBpi
zaxVwHFs&{b+kt}ujQMIC9t(L69HO@=d|hH3c~aCGJs{<2<(<U=-eC7$i;hu<HQ`h8
zBM?28o&bkKk93wHYkyp8Y`$TBBT3EQ&{=&W+e=EZ!{*XUS#dBpP8FXT?H?*1iLV!-
zH(<RN`Q&y2wIcn*CmKP$6enyYX^4yN&SvGq-4t9>(IMpb(^OwNj|X+>`RQ9VTI?<;
zH~A{UyB?9$W1TWhSv>daEu_QOl14b<fCTVU+&z`WNn61s;*{SoAKU@*feNZEQE|E^
zyGR^QpS>W=i`POocC<jRpvR^XY3Tcl2|jmf)kGl7C*0w^7G^<--d5o%=yluAbKzVv
z;U3*ova!skXSdXsUsEpP{I_@9<5V2w;^dapIoi1Igz!b#&;+{xs&G`<d>u^376ZI(
z_;G8a?{t^t)1;JJ;AgwA&DWB-<-Ci87q6JSRgutOCM$vaVLzT%0tY7~F2(b5Dsg;6
z51@q`l8bAt&wT$=*KJfgYgy4;YW;{Vx?2frHWRElV09o$H`cC@loQwIHHe)IYRMrD
zmTazZD!nljx%wyF<|xln#?)eoiMil+d9>`N5KCoRvZ|)*m{dzo%<!mdfj2O8K(pQt
zbfq9xv-mJSg&UhWc2Y1(6E*?0*Ev=R;$s-wJ=5O*G&O`N_dWY}c59(n&~JzmdVv4N
zeN2hP<I8a3O4-zb2|TYP$ToXKC@R1vy2lHACQoM*kj1N^XRfSP^|D$+iN7&3iW<$h
zX;FM3IKbOX*?D7l!LI{<u-jH-uP`Eg`s2IxR1Co-<ZXFa8U5LSr`5NMsvqRl{Fg0C
z**#`FA2Vu5Q>>n)$Dy6-d9WbQhCKL5k7`F#gdX+g)7CK1&3p#VWt|+%<HzSF*X4;u
zzF|jufFWP5fKX*E0_Ic{e4hS&OgZOY(+ua4*P3@JQp`f_3jfK=F(^L@o54gbEPZnP
zI?hK|a#sO3YT}GOU$LIHZ%4=ZaPqrSK=y5*-#0Qy9;koCvGoalsKC>ji!bD1GaYoJ
zCo`a}Ec&sHI4z`ud=g~dpne<g|H3P6b)4b|2E7SW3{>mpqnV9>9zlD?OygLcy-+*u
z!52{H`6!87Q@U9yEYFwh;XB09`Z-}z0)F(rn@KRrC~EDnMS$w>60EOgw#?eMaX9+P
zK`C_AYP<s?rR{FFq<m(qfoF%E@J0z3DhRkWcJrKpEyb0h+D2CKVTgLw-C#jA3_}6x
z+YO$uM>EN27n?@#$vG|QZTH|-gy&WlXVHHtAaP7xa^5tiY6T(=ovLY>Q$sZ<hyFIf
zbkX<k)J0%FCv6b_c0po`{$02HQ+}$SnBIcEuP{S1X6J%#emD`Q$i$fQH;NO(-jnE0
zCTApB)5vic0b_aSrC*1IV}+@1gIpv_J-Dckae|Gl$XvVJ>Gie{%liBU{lY+VonX3K
zJ{#jU*jbqi2t}e}OLb@)wPwi7gqB~%1i&&&8tb`Z1A_XKPt$JQI}gP-m>d=5gwZ7v
z0pd2d8m?CaKkdG6_hmbk*4Nuh_2DaCJ2+R3-zd$4$vq|{hzou1^O=cW1KDg&!1(-A
z@2Ml@9h-t5n}BBGg_NfGkEowyCWATTz#9iw7zR6;$(9w;OhupIz2Fx>68rjAlOiO8
z(?<W#)Nq?6Yhk8ALEmY`juoNt4<sOn(*rG2*OV#;74@To(A>`6k6oKuPE;U<mB(%=
zv=jG7A#f~={5a+2JEB=?K|JVi*JzJh1P#->)P_(cW>RpN=;11p;<aATWh^PT!D(XR
zK1+c^sD#TEdhTd1*Xck`1<s=W_<ydzOueKgG?>`D49ig<+7H(L%9I;zkJhnZxOkO`
zK<#<t;geaIZVEvcEgLC1oauL6l1Dl-2Hha6h&#LGIBda23;xV`EDT05KJ$S*kHA)<
z>+G80s%P^9$7&d2N!;i28Y2Oux5(?sKBfeUZAW^c;b8ad!IpgsXbL}GXWzjE--{Ar
zA?81Yxfm8JeG=z2@M0b#2Iun!CV#(h{$LqxTE`Zt*@ZA?Ip$G<4=uskJ^r!Nvt#-L
z6+>5z$&F*x{*Aqsz<Yah<{71Xn6Z7`40M+;g)08W6TMQvh%(T}uPdP_jX@roD`&t5
z^W^<-j;)l<6d(t+3QI1fkmOK)$Y38F8#n*<5;ORVQ5Ta6j9R&gd!2Qy<o6ck{O;GJ
zpO!QvjmZ#OI%y9<U=%>!^G4zEQfagm+_LM6v7$L@u@e!Li<ZRf5NSCyq2<TZ>+bJ-
z5T0;1J#CVj-*AOp9KcS57xBM@5gESHPax7nk%O@JHF{z&E%r1Lug0OyXb@IvTSD(F
z(QLPD$)96HI-*IT{PQjDEPbtV-k*XDFF>|dub?xH=Pj<T7#YXWIRRaS75GO+O@~G$
zWE2I8qE*bVAH@cwIY3S&5QFwlEC*;w{<@QGK6{=Gptk!bd%8s*r>jRhZ88QTyhZL1
z_Hy47g7~VL_p7>{@AP|U<cAPo%SEwwTk$ncz!Ecj=(T(jMl^~(6ikY;eoULZNQ;>Y
zs_qQjc^j>K$uddfOD2cIwiI4VfrffW@OQvgyx7uT&@WjdG6;d8hrKy*JbC?nf2;oR
z#t7=iY`dWFaa#kyi}m^3qFcB-KX%HDkjtJfgxyY_{Pr}TprUt{2|=+~q}q~RT0)RB
z44|!T*g!QP%tfOSYCbb}M5j+%F0D&QB$E38z$|$WKnIrX3ZdGoOv%+{u{a-<WxZtW
zzKmopLoBI0UljF2PiW{p(S^m+;y+g=3}&=QMh>Z1SvGgj0)UAv3a)DTeRPPlB%1NH
zPxk#jNv7TOCHJWkA=p;{FSWMkBtU@tf%oQ;?2-;!Zdj0~nOH2RXuzvB(}qqX0wogB
z+Ts)2`ZmTARkIEI*lt_bz#y4Zq3?=3cZ`n+XFKdz7-&y!T`o+vwZ(i4Ih(eP+*YYw
zB0x4b$)IM=NMJy37ImseEIp(bLDf&u7{NNKb`G<K9xblfTtgCr&s*DDq7fhE!IMd>
zpI6EFh3imHd+6(3M(fj~LC0>UOe@XlYGy#;IrIe0$U!WGuFizW2>OKNM(RxTTa-}=
zG?~hV^oHESGJiGaK=_A3y^Yxzc4ysc$-_Ut$9DBT))WH&`a?`{7^B}Cv!V~2j3M3`
zYniOIHEsn=NT+h9>vrbRt=_l+<0r}Q3~|orgS6UoxdQVdfOd8ZgbI8~9%XHw#CqT3
zA35SL-oOfNNy0`3&eOOs7&6;A^0$@Omy2u+WpgLrUSY+nmyva?eX!!^0?;6D>wL%$
zGTnU46B<O(T$VR_8X!)b20C2G?EhaqVkyBD=Cf)585hKpM;YqrH|x2)FX5YnJh(gE
zgH}T}4vA~C&@yXy;3tTKi9i>(qi(eS*-;&R#-L}~a}1-Y3cV|HO)B&E|BBhu7g^=o
z^XN`NMaVHWGf%7DY~_?1e2A^%15nKMs?QHJS&;%u=RRvt>3>4>`&7abMpDFy*w(OU
z3(j*XS1IHtVC;L9^%)n%B0UFx;R-+28^qMa6H-UAQlbhDV>ht2iL9f2bAC?VuY`TE
z_NZtCtp}Cq1SvejTu*KnFzI;<EC8uBWPS&WV~tFKE5as@?%vXPJlLZtY~vh{cmm!(
zW-Oe|3p@Ot)K-Z>OGs+K#;kyv%jrr(0}?IrXZIgfA=(g*>0n5Xc3JK(&XRnPaGwhc
zUy4L)4TUVeYLN^)tfn8f?~89xm_8Df*68_V8s(AJdSFXET~09j8%tiEnjqXeTQ%C^
zW_B>IPfKej=LrNgk9UwJX5i4Ox=zMp76-~8T8^^(adT89X1pv(vx*r7OpFgihp`&8
z5Fh$!6epD<Qr||!inPIvWK*@%y(A|mjRfj%kkKE**0-pgu^y%DgOm>VxgfKiXO;oJ
zdOFDTCEc)&IkwZ?3y^`BP)JI!B1e9dqo4LHvN8oH_OVb@ja=!QgA3W|ZaeG;Z|A7V
zuGnmiixAQ0VPf=wRbv`X)RTGEH3Rg7w^@F9e|0UnF~HD;on;zY!Y=^eWfOz<n<xk&
zE0#(Vn1tI6%{!BhHNe~s+l4OL7V5h`4YYB8B=6`fT3n02BCsDl2IeEoYF>E*wUKn^
z^~^afu;!r62dG){Pq(WZTK^>H_dO*lA<Xb5K>$rhu5nr0?pZBdh{4b?KX5t*WauX$
zUISkgS$IBhUr+@#g0HRL5qUX+Edw!Ty_pDm!FsYCHgR_{ny%6kmeTR#y*ke($?C*=
z?MpL5!99vy)bNp7Y2e=Z2vF3a4R0ZO>4;!UD{&b`BiLDtXGs=<C3(`YhBW&W;+(qy
z5sp`7s1LkUYY&4^)lkJ9?X=5Quc+6&g<m&jjsPx%G%c<+L3zW*CGHQpzo<X!ygVe(
z4?ja*Z#k=AWH+*p(e=4yx|?7p^#V!xTsd6K&ju4%??4y4d?yE<2Ig$<@n#ULMSVTR
zf-50h3dRxlxHZ*dH|%z=QL!KN0JKCmihfwIuBP0m`ucu|BUM-WEk$Y^goziC%DL>2
z);ruO#1~Pi@w?;#+4$e^n{Ywvinv%zzVn_))%KY40>LGloBty%>7_Faur1+3<N5@^
zxy@Uu2|b>4sw8$v)iOC=%d$2%wSI*ihNFay>p4GnLNcBJV@t0(N~H%3I4q`7a-|97
zvbDeY@<atO>7{8p98Vh8p+pS)v=_7=iwlb4e)+BYKD&e2H0~$?Jc@96(r%ND(NeQp
zlcI05uSzY;ouD1qSUg)^?_oU~*PI_*9I+`b`JWgSIYPgvaK<(aPEU2C`jH$ov)SRQ
zs|BVcXf>|301CWXCt`hjJ{eRLf|#YddJ&9_)lQD$Y|B#2)1+J+&yy)bdiyV!#=b-T
z=zo}!s7FSYp#>y_(vRo+D$VUW8}?&pw`6bro=YyUY-nPVA9s+IzC3EX$)NKXz)to*
z1>sr79Dy&*H!*PADx0@4pj_pu<8|b5QTLYT{iA2os2M{NkG&KU^|})DjB?&WhF?}U
z`iX*T8%J~^VAU!X9o(vz_&w=f9?F0iGT*o8Oh=tDF{rk%G&`M=C4@x3?(UmelJ3})
z#1A*zO9fylJmJ&cpjQ+c-ejF5ViM#X;;vy0!>-$WKcJmfEw2!xd3Et|Ai#Z!AXeR4
zK!FsKPC<UD)QKUaPb{q;O9tSq5`63%h?WKL_$np<l&K18CVQz$Vr^&;i5sBt`wqcT
zZ=V^HhT9Bu{4Hy^r&2kLIsx-_q_#<lSuVCrA;6boSH_?>y#+EvU`ixg&cA(Dj6gqw
zuR2dFR;eVy>6-AOpjcxedP0!4w=+1tBo4H*c%+s-A9>0Wy~^sKiC^ph2u3Gd9_klg
zEsRTOqNQqAb=A2ag<v4syla=g-Z@XyIP$dArJg_<z7cO^2|1dI*djGhtCePSifPl7
zDYTKuZ;9M#wE*;TI%;P=x834g<{A`<I<iEwl+Kt5G1`FWJ>Zh$3TV>+iy_nnPbR`J
z<eCdtrYwG`-z@3%Y=%GAc3;pnxE?cPoz48eJq=ozGZesTs8x*)8%q%q*~~y5@-Ny=
zVjTI(Cnr6J>@#A#sFt6jNmeW-mBeG9oj0eJ?RYF{7H^5&>?&(eRMsVBK)~g_9XP^?
zK&@AdnLLSQz3mj4tJXdj9CF`0c%+JiYz?&o8L*#i7#JGS)n||Gshh+e(AOsNsh(DI
zu|F}qvVduc5J$LJkr?j@q!FhpgN4Zt-9dq{Nx}K!!um+|DnarpA-mz?YNRG9SiKYx
zwh({3NZ|U9&0HR*4@4Dxy&G4F!~x!fLc{h~lR=)|tteu36nwD!6ilEb94yW)h1Pz<
zwx>)9F<etkM#E8&ie2Wor`_a3eXuCbc9{+HQ&pK+nEp@7JW^{d<}&$%RNob_p-Q}d
z^{$({JCPDQ5`Z9g=fn?o@e9j~J^^`3%^{T7b$zq@3q1J2W8Sspa-Ct`(e35J!+n7K
zQ*w|We~cWYO0s>%GSanFut`04yMHioLetxR@zdDnTQ+2ZFRIM0LvE?1+wje_yJdu>
zM)>mBOmO8)bf+Ka8STfD3`xZ!Naod&5MypO*;RlU1L=v8p*WrJ;V%0)Efxn&D0K0G
zTEYPBmb#CFHnOd}*@sf>*UA^0v=LzsSUghOC}uo3mo3<I*>QrR99@HxECW7dW2}_A
z1fKZiv_duw+go?Td<A|dTIL00Ve!&P{(Y0fp1aPeGP_PyJjCNAveWu~uQyIhV$Sw(
z!F`jEM%!4EH*^p((>qQ0zO%zbco*L<KH?nbYNxTJW#Y70bkC8T)4ua4rJ}#13`eAx
zm0<%j0}Ck-(3e(ot~6|#T&=-0vh{L1T>t^EkT<>41JYD&S$e2*uxs@nn?E=~?X=kw
zjUW_o(gn^D4#BhaC<2`bN7S2T6WIe8IEy~op}lKVV*&X2K}6FoY=*coI4Pt24oJ7t
zN4U8Fc;1T`HrU#Gg-pLdY=_wo-py?Afr~BrL~HdBO)q019xC=2!__JGvwl6j53%XL
z|Ed6iz+Kv-r;15f&<4B6Mm`QZL$aYT7Xo2?cDA+>B&K|JyFB0^C{de&u84GlhryI7
z2L8PjW1IdM@B$k##_S}8EM|Y|B<n^mydc-RI5~owadrt3_KkCw{@1<$9m_a952#7`
z_r-!TlRTrRkA&@bCMPy_U#oL`Owj{Ox|*gP;S~g!?4lXIIxZeZeAnfpFFtn0TJ&+d
z@RWcw<+RiQQ{_1Gt1Vs{vsH65cIoC%d+5TO&O&BsW&#h|o!qNjDaeK8wTkXjoJX(k
zC_z)c^2FXnVt{o;<mAbNQmsBNVoME#F%V@e<g`Ro{e0vB56$k9;m$UQ(>C3w|Gx0n
z4mizE-r46kD%CZ!*iMkxWO5~deRrV|$RSq~>Zj}jU6PK&;<q@p&|azm99lj^iFM1Q
zjifKv<92OtQ*ecWXkvF5J121yy^UNj-7g+}8*|4JF0S1Fhj41>EeGGoXr_>tLM3l@
z)|%KXsK})t4%!Iif>KFUVdTxYV>UTn*B%BS-=8$q+2p;5jH4wz3||hvw7OBHX8jVu
z^QlrMnMP>y+=#4#-4z=Gk2+QjH!uc#-9P`7Rq(5_+k6I`5_O4OiD=Uh)eR&bl^YLm
zs+1u%vH7fz{@w@UqdO3<SSRpyMwTC#T6uw(W_3|Y2uQjE&y}Tm{C{X!l@9Ydn>!K8
z(u072kAu2ZRZ*SFW@T_6;sTN#_`t&<RYi0L<i^wbd3(?y=nZu-$%qjsZ$8_r%SJiQ
zAAZk8%0u;sv6D(_)HBga%A=S#=TiqSTHRCF@CJCE7SA2|7rZKw2!K4nuq~|C^-d1n
z*p7(+gJV!WE$T2OPRwpx<6e_i+bbKr+f$yaXcf2DOhV2Q<q-jB<wGjypd0XLn3)Rh
z&${i=3q20(dUsz-OU@@{1PvaO(m#z!G!a{ymdUeD7Vfwnz4l93fYTmJ#vettuf*qe
z$Y-Ya8bITbdAQojRA0%!V+>fK=02EO;0DL5Oq@wU2)zd}L77brkk<?r`%KpK<GDqf
zFv<km!PQ2Y@C@q=rI;2<b(c;A(Z*&gEEiUX3|~Ipu>%lVgo-P_D2V1wNec`hs-TpZ
zN}td}3&$WKlPp+CdPV6e)Vp;+e1GOl$1+J1;1E%_K8US=;)9Pn|9@dLgU_vbz*PU~
zpRN?EDQ5EB=h9R&0xEpB#hZGb{t;Qdh-k?IMn!%_a6e)F1QBBP8($+@Ra87BA>F>j
zRB|yv#gwRrBXkcozAjDdqAZ#LK}nzyhu1i4ss4l4;Ulf_hZ)6cA%LTpTwwo)MQX>S
zG<3WpNxJ226lST>Z_8Zt60{VrDpi;ak3koksp2O#u#`J3RL?0?S3gx8BM17pu<3kw
zSUa{EQ!1h{ma5|T(!pvFrAY8JITcmcLh%>-`fNT77y=R7G^CF8EvkD+UK86=SCBQJ
z4D6QF_GFzAjB%sFR0Z@d%I2T^w@l>v*&g>k>&m2Civk|mPgseZk#d{J9zRY)#15Ui
zbkinAWAZ3F0%r0!$5nR1YNPz@zP<r-ho&fQz@|)!A-}{N@kb%9K?xTww?|14LhPx&
z63oMqn44N@;<`WL{bGo#w#kt%il?l>K{ku%IKc;#Iv<;o7Cj!Pa`7-g{gorsr?<=O
zZOH~Cr|ZY%U!yFVv~Q_L9TGp)TPjN4`2<H#iPAHtNhvRk(7pUN;5imtoVVG>(j){_
zH#7f;AO-8)fBA}>vsbKz$^&)+cN(-^fYr<8`lp~qNkXCg_&|Roy@?u+5ZtTb?%{{;
z>afib6@O022%5!2yb)ptK6o3!9=o->ZPiAj8OAnNUGzVjV6M+jqQhG;p(EeDBcZrW
z*D<QMHGe*aJ#Q-kd}!HYf6vtGJW808cBf2n4@<^rfc7{p5$L9w788pW8~_w7uQeiO
zJ3_Igf<{355?9f)pE#!=8S<plI`9kuK<o$S5bnR+(M^z)vbeIByPQ|6yi~R*dk9B9
z%16Ty0f%BKqaxa;iRxI%Z6PjC+;ui~fUt^)I%nBv4_0VJ3q?8jG?hr<O>l;%RRWY2
z5=W&Z{fex{spX~p@F(dtLS)z;3zv+c|7d?3R%d?#&tsh$<hq`%#cZquRsE?!{(RO;
zyDn)C%rzaKVF+>y(u(QVHWHaKKFX<<-rG~b>iQPK1jlz`Kew?w323o%g|XizMHdpr
zV~ZU!anXTXDmGxxoY_1KY?K7Lh44zPk9z$x3)r>F8z1b5pEDP67c^W8a6kU^#ZTA6
z?et~jKBse#r}qV;CVwK1Nhn{0(UHRssNhwifFdz9ct@n7s<)Fx4w+;^6D?_1Dkiqt
z*~`8syMq4E2MgZBCI!n&kv%0=?zT)t5?Q|l2`<BWl1!vJi2)v{Grz}~gc?bu>z(ue
zJo7JI@j4|TQn_Z}bD=ukn?3|+`;dK3!OmcHCRYI}e+J<pr%xt|j@Xs5?hQMhixrvQ
zQ3I@b-Ff#pdGb$`MDB|}-ergwEKlsUfx-wHk4?h8iF#fMDe#MMqv?dTrJc*0{m`lP
zn+3m%!t%E_*4EOUw<+vwR_P2=l-X0yv7qY#M%a`I=u5TpTdN+%WdVLN+--9(Y|u8%
zCHH9Bj(xaKCbuiB>_yH|0sIiRubV|J%iymS9{r#gho`AvEpn7^43{c>i8+z}^$iW4
z_R4r}^ij6bX?f2c-47Vt*bmMWq7%?o8gpR3B@mg3`@vI3Aw40dWM#?qSq?OW;V=XT
zQ!*ZWAicqEb{6wgaAR#xLvR|rf~}PuM;nt4v0i7ZM*rCm8o)DnK(}6mF)X8Q<u3jy
z*vWD2h==4jcdwD}?P;3^Y~3Z)kaQr2ZzV4$=3==53=V&0{yZIlwPtYl^=V0?3LvQ8
zM?oDvtbt*SUJ~`j4as`(aD^wMLlo5~=1KQGGVdF%!t^1LOo_tp*$GZ;lHfd0k4+Q4
z7g>s^Z)Y`2F;o}Yf&O(d+e9Db|Ew9$vyVJUdD}B>RjC+zixoHlLU)yjiNmeee_;5%
z_m6byS1#&vyf}cF@%MoWL9<LmN;N87Yyxz5@LJvh07|~E&=TJY7qAULHQc^-8G`qY
zk<I?EC81bXmk9u)VBy^uq$g%MvM!mL5r2!m{uOVc9pQ1Lu?Iec5fxTp9TA~(za9lc
zl_<Is@fUa*+mMTLkb>~>fC`_h8KiUpo*I6NEC2N|m8d=T2ajF6NE=bP$!Ox$>gmOe
zwWIdX{JDwrgRo_k<kTma&BGeU?*1l2A_!Tj+Zlw6&!-?iIev3ddGy0Y@x&DFOn5%W
z1eR!;{y#|4s(!a_VhpCnB8;G&b0Zr@UiZ|IZMYRiokk<(yj`Z>_7?1uel|J?i&7mI
z^Z&v8?jBS1oy>bQ0Dm5wv8Zk5G>&8fz~C$ObSpk3RZ5_+4Ip$&h%HV))S?Bt=nclE
zu^o@H_-ZA_I`>3Yr>B)I3MIohvh3*aX-_=LF=MbjYEc}Nhqj$`UJsb)E2bSuh}#HB
ma9?;AfreW9+8HYo!PS}wABiC?tb5*o4Mwa2K9a%xg<@kofuV!|

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v
new file mode 100644
index 0000000000000000000000000000000000000000..8cdee1370849ecdd47a8582ea08cdfb3a84431ea
GIT binary patch
literal 9472
zcmV+bCI8xs6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlQ!*GZ$O$ymhRz8@$k6v&9l@0j&
zc}&S=IT&X?HjSMFg~JT8QxnC(f}r!WRM7eRloWV-Tn66OJ0*B~HAXzqI;uMYw<dvP
zA&GuY&2q_`Hq{Sa2@RRn+un=Jkz%CluyWA2iEN?YmX(=R^dgzA^CZMnKU|q|pbmK&
zIlM^`Q5{sACwSz44&Yp2i)2_=wTt%(^wtiJ*uyIDkceNRJf|t`lx@0y=y|0qD2V^w
zP7*4F49KHknk}Or5gSo5=F*gKorY9~{-eC(vR976{Up$Ia8e|f4!q(zNO5lNPxefO
z*r&iPyzEei6id=QZ{jpR)Vc5qQBKxvLdWzid1s+P$7o(|h{==>cJ<W{#=u@c;x-TX
zPB8ogl+%py=s!K8?Wd7r)<c4Cf5PQ-{-&vCS(klVVNE_aU@T9-{ENx`l6HSIb!NTQ
zhmCECPh#`R+KSX2=(J|B1n$>L%CSBZ#)aGa1-${iFF^^o)?0Ij+n+;9g3w#<idUoT
zC<Gwm2`C`Iz%`XeWEn9)Q&{((T8!X~23;Nui2~3gb>l<HP5xA2ENZ*QHffa4?Wm^<
zk7hOzV2~wTt#y<v^GH<kd*Q$wRnh1cP7*Q<BWqVsT_ii(5r0bpRZd3UsGOp9SF5sT
z5_zQU{gEKzWiW&&+1Lr0<Jv52vb@|tT_4pJRsfve?H2-ye2kLiPpGz4KMjCzWMJkA
zp&bt%e+2YB+_GY%**;vOlKIRsQs=Lk?;Okl07wy%0?u7$j=xgcesw@n%ZA02RMu!Q
z>(do5WPNg8AbPc{(}1fUkP%&15Ug49%~?GJ({zpR*3-U)`7yum+=I3+0_F-v3ZQ48
z&)ju`r0=!uaLl4A`dRD;Ny;o@zuV(qf+wc^h&%SgF++(;Q*bw5;1PA-z|QJr!j;nw
zgFX7R2mW-ODx9fB;{%-s8YCH|mbL@0{cS{SikkD!C~N%H7d;*oh*v0-6eX(4@hfB@
z<{5F82v1TDW9LdC)_Q|5I7{M_h~}Owi_j4dI$v6i(yHhF8Sv4mB`Xo?O+<qQs-0s{
zB4k(N?e#~;i77a&pjLwCL+>j<IF&S=dbwFxJR#w8(~xU;d?$!77gZQxdry$13bb!o
z1GFkx^7PeI^n^+);Mzyq+T)2>A>SU5v^o8udhQ)&>2tf)cH1xSG#P-OUanU`Cp||u
z@aCLtML(lTQgtXi!=@64+x(Fhc==Y8f|S31SNm~(#@?C(RGnxPC(_T1N)7vFY~hyw
zChucgQ%pG4sr*x@8a+&9=SLn%?KK}ybe4>c<y2=WW33q8*g9OJjHEr^(;Yz8_Yy$-
z)^+SeqH%od^Q9v*JM);QRgw3X|DW;=2=6%$&^TWHaoLo>bI+X$feh6Jt|l8zRBl*5
z;#9#JrX4Q&bW~z{_ZwHu+c|k#sC%h{N?SG#pDO_@Bn2l=!N<qj1+regioWy^;qT3$
zGH#Uo4flHQ%I<>F0#j^lyRkJ=u%`)oC;4Z?bL+V`xkQ|I`Tw!2Y_-a~n_?>Pv@cYt
zW^(fX<8!9FKHVv*w^dwvx~NQt7U7Zgw8@h;t~B-S>xsc}Wl&k_CA3IjHw_Eja~?|P
zqu9)ruxL7OQm#sKl{D#?HNs371WK1tqH75k92uvA?6nVBsp*&2RoB^8v{So++7pY@
zmdj*Hmh6RFCg6WAcmBxO9!*0qe7jgJK(qglubHiBHC4my!}jDL&QL#$vdUPd2#=dp
z<<vBNmE8hH!#R?Lry|&8T~^Z(ZPufA9Sd*Hbj8U=>C@AEsmH+^c1ZkmBV%?p`31oK
zr>+RnHUeyej6~T)s>Z6W+;!m0$Jb3lL>SzqA&J)v0``-g`kLj|-2SY|;hwRx$3MmG
zXA}&4cDKxx2k-E(a2!h`h|GhY?uFcSC$fZQH1v0?S|sk_#JUQ$=|()jciUpp){%2B
z2C(l=AOEU5irXiIlCCxzEmE6vCrLv6HPw(V1&jIiB!hvQ1Ky=eB#Q5=uIGoV<92lX
zdMcMnM;<scV65eN%|<HW9gJszm|wAi5yKA_!T_`8DbHksg}dqJYkX#+^gE6^U$aoM
zloYvJxGxOA?`Fmd7N(ZD(Koj#vbd;@HMzrXEesfOReq*7iB~^>$;695iUvCyyoDhO
zw#tAl&m^MnE-2{0xU+%3bh9+rF_E&%aq4le{X6C1fqu+ATkxzC{w8cIp_J@VJDSU<
zBJiQ)UrIm-)wxvuU&O^FzMBLVtLRO0ykcTAdh-5=8%^564A<`s5?Uu%2cRyMS89tB
z0KpZrRCHZVWK4UGuPNtO2vW5+Rec%jRX>_qNUaCyK{)@NYZ{+Sp5@BnY8Ql!sL8f=
zdI~L9Iv3{fN<o928+d92m^B)!!wN2H`ujKHrKSW~`Z|oF>H!mtFX0-IeZ3D!g|7;b
zTo%d7(;-LcFwhTL_WTBsWVlU2NCvAEAjDa(b@hlPbR|n6J;y(er>!`bL_TCd8s7bL
z?26lpa%Br?*e|j!<b@;y7Sq53iJ97CG?#83_?p3jQ)4ww?;rO8F2n8fcUqMgWKBgK
zRnT$06Z~(Fk3Im&>C5{_SYB~F6r@*u2c&^9#IB|-tur`AcKik2n#6$Pac2v5VmWC3
zAH8W#>yR)kFp;cDK(y`Tvbk@LXD!)CBtCG}Bb!B`puc<#|3HDec6x8kQYR5!nUTc0
z0g+bS7y<xEOFq<4Zh0uHDV^5XHbGN>2i+YGSrKt4+|moi2qPa4`uZby7==sRz0Y-(
ztjk;(7~Qxv`U-q%KuM0=A&HSr;$wDxnIUH^@3*>v(ZbG1Wa)$jd8x0N%@ZA~UvCW?
zucBPjs}mddi*di#6zs$b1vV~t_HpzPZzKl43bQvm0k;6jKk~d8bHt%#W?8n!5llo;
zUZGlgBcPK7uq1n!MeKk8(Q}}_FU;Nr#y6RI{&@;CTpt^u`y)2w1@&pH!9E}`#r5$_
zuS1f%a}B09k?}9ekVL#@?0l~&kbD}Klj=;W;R}3i;t&Qko}kX&?|Rl_hl#=L!`wA!
zK=5C)$QGg!C~N~Y3aHa^ybuu2zy<z)>OCoto#dBl(AV){DrDelB;uKge-vogL;fg+
z31E+s<w2<0s!qG|>`Ej4Gu+iB6S9vdzIX-<`HvPoAwE}YQAmCACj9WLt<+#%&pTvj
zxn_8MMd1TF_+1TfHzuzhC2)GF{KH$JoB1mawlGr2FHE2kiJx8=vhE|;lt$?q!?>EX
z-oX0ih#)D1r1d2)C!#A?t$7a%{sH%IZUe`h(DZ?qi4&W<H4ZUNO5D5lC$iL0@n`2W
zC8*ZviXnw(md97>E52}vb)xHHV2RrAN=6%7ea_yYHzHeHQZjhE9km#Sd)B4!7E;h1
zx#Z|0n`F06ez+qB?s{+6pflqt;tc1AO|<w>n)!L&mNLHCE(*h$bf~m-;3An2&e2PC
zvSwsgy;QR~9CT`|QgASGHm__rHc(%#XqSdSOOtcU9RU2t@Vf4C6&u#Vf<bx88kol7
zIAA(-4aaNtd&L%(U4nb@;Fzqik;8c3T$CS~U)>(e5GbEf)^FZb{qmFMtzwHySy=^9
z8QM>+O4|7JX6-PpSAg1O$3<QhK0a!@ba#fX_#EyNMn0i#BOCY300SB<pop-%jyEhK
z1xLYwm#F%9Qk;ouOxzk+l`#XCB}=^}9Z_rZE6PmJ|8Pel$qE0U@f(oj(%3KGUUU;-
zO%DHJyFMdgVa;_=$#4Wn+2}|h)tU_p+($PHlkUjBr)ImR6!pC~Fi2j{8?4z`?J6?9
zDQ|#j&``PAC3QZ0@ldw36_CI^?X(V+D6dl+5?uGzd7|0-!G7|^fqw4tu0iK>@rF`q
zsLR1GnUGI|`@bf;8=H~r`purNS`H!Kmh^}uN8g>^n4;i0%QJ|_d#bcmE5`hvP;4zL
z#os{9!t#2myw5*TYwUzIarOnm5w6*y%PhM@uulZGt7OL)CG{!L5|f%E4JdwKK~IAh
zzgjve7$!ZXtq6Ovh9v}*;tGQxccuk*^j9OP_v#-e)_+-;$$cm5Y^ZOzVqA#)IF;O;
zYQ8h3OIERA+z_Jq)3WOm-GUCJmRe*zD3ks76A9~{^M<_$lQS|b9r7U#XPj_|san~u
zEFn3ZcQOV0t<$h#6<Fx;$<9U9AHydR6ygMPbB`(oV?Y|zM~4;Rz@$z69fH80b^oeg
z{4cD>9;<*O>ISW6oj9A>Jpvl?1I*hAKGH>?uG5!Nh?YaB4Q{_w0{EAkc3-ctZf$r+
zX}o2c0z$7#L^Ywro0?2xj-0@S0MgjAAX0DRh~}vuaJ7Q%LgD+D{fRb6C&Orh_qCpj
z<zqccBNe!EFjGV3O4ZscQxHO%|KH#@^1s!mcKy<S6^J_gQ%9AL<m^Io!9aJdC92sH
zu0wZLn@Io3?8Ip_UWB!3Jw70{+S#tCx@K)fIg@32ZY2)z{CACZ@t&-Q1ZLBRLy-b+
z<_N*Y0FB2~X(T07pI6epjgmG$^^~}OI76l%p5)yYaOb|__h`8Qm-n`>_IcMnK!zYY
z3jkw2_*Z4VzoUl#zsv?HBA$bv)A8J697HULuh!$P8ursW7SU>x0IM@@T2)}4@G-tM
zK@dDlDIX6Owe}{Xj_<Kee5Ne`#@9>V?KJE>Ff$rVgW7!`T}O}pBRsx!aIT*hE@dB;
zl?TFVX>0)p%s(%vJ62@ygL{sMynyiFlXo!W(uM*6`<uReAVG%8S!`F~kv$7!%5Dx&
zdRTv(&73QkpGoljZ{jN{StO>{AgPrZC)Gk>QP=EAz#@M7UE~V>#C=LZ%0w_$J_G&d
zBYh1beqhu$PT08@JAOSqKb2n3#+|cRzXPr2mOXTN)w5k>`p-XI7h7Z@men>#Bp>1|
zE7?YTd@?IbHi@~@!s{JyAKZYxV=M)r`K#^WbSndG@{3J`%5QyKy<?8UjK#VJe|;KV
zS$+HEvUqU3ON00y(20Mx{V{!ol}znCu@5+~Bl5nNs5g>9H~z5m&2c6%;%u2f8c2-?
z;M`EOz69CzA9sKsurqPP9P1HS9D&nRp;JG)jxr{}OS6E$ci;er8c^{(xmrSfDmppW
zXY9z5=kj!O^%Udw-NLacN&wb3-IyMQu01zNq2+Nt;vuH+v!T#oD@h^lOc%iDxa=|6
z@OL*TxnM!fri3Cv(C?Zq0~m<m>NVWNo}zfwdn)bp^P)P$X@$&9Tqn-(8kPJ09s?#;
z7?&N^S7uTuN53<XaR^??REfS&=juw_*!c=Ow7$H7$W!6x*c<V0@H9)A2@!5jKEK#4
zu(h9<kEv>)O+=(A91MqX;+Ik_k@WsT4u|W+o_zKm{KIV&Fz@dMSRk(26QDms;H5&+
zK*H6#;W|%3t#O7|vw3RuVcg*FPor$9D<hMUPD1tTR9TjHEd)E`lKs(}&Hw0pT~dYz
z!)^rW9kilPukUhdg7mAJB6@-AB8y>#(cmZMlh(+uX~^p&Yt${vZHe=gK_xfAzKV4}
z5lHjYxQ?D%aXtaUTZ6Z+RdkZ_zzD(0Z$E>!vs4wMyAnzdklm|mp=$5{*XGR3{lKpG
z)UKro!GoOFpH+SyKAR(N<}q=uA-Obj)Wb@|wB&{(q>8MJb2X|siFxK<3-4n+v@*P6
z`v!8i8=<lGx%1rpH=SgYFw1Be7zNb0RYPO40htL=?&wc6C-*HEwjcC`*<4`KU7blP
zMY|`dmQ{4Oz*Z&zW}q$@#!P+8jn*Q<D&l^iY2J>|GMb&EEK(=2flz|7-6zy#JfwCT
z8WBUWK`r96{zCv#Q>@HFA^$SXq-nIpua}I;DRFO>HIMdjbX$ZQ3LIna4zR1(mpXED
z#Z~LI^eP7YB4M$j4p;PYxMX3ZYCF6~*U)d7^{`yHk~Wn5l@hl>fap2LpA<xTVVrHv
zL$9U`!i4nAAayQzOsN{<j1P#%v=mFo!DbfpnLA7QCO>hE{v_XwFk3K-3+}RXbk%uq
zSUy1x4{tQTwQ)DO)Crwes89IRmq1+oe`Ag9384GyJoQf}K4*WypOZ<7^-lI_6CzI>
z*(Ydp8PK3<xZbyLz2(m*CgN>)7jKR&(j{2`{6AdTms`PMB#$~8E6+$tUZF9y8qUbk
zbNu3q?lw9^#_GN_)$LMkP1di+tp53;9QwVJ+E~aKr{jlP@4e0L8U*ygLk+_7k4vwo
zc&IO_M%8T5IeY2?r#08g;XBz7D<;`u1P=bpnR;y-T$xI>I;qi(0#*6Jm0sRZ7bScx
z$65u399=T=xOBTrU<v})+w{>4M?jKY2}?>#+do%3s1u8pa4Rm6X;-1!y6E9Pb}AN=
z3hNAPcoE61==$^8k_xc2&gHz#4zB5>FMde~K0TLls;8Cxxh_=_i7Xuy>0VchaX@w9
z-SAg(Bse}EkBy@z>yU9nOF9qfRsN1d4h~!FAkWr=)U;b8XsErpku9SYmnC|=Y!+op
zdKw~C2qS9|5BN4p$s)W5?)t{VXgs6Q5H<CG8S)cBwsS4qW+cyvGfiL?En67#)oFQ?
z<o8Y>qqE*2ek)H~0vE`?cYfdC+F_YlAFqa+RyjtQHDl7;4yoq8pWGYebroog4C{y4
z%{*JeExKK8E9XV9E&c83I+?3tFdw)Nzq3PXibz{3e`jpr74)T|5Wd3umlWPzme)+)
zngoVdVRo}bGV+@lO&}Xm5=L@(^o**}Z~395gP(XR(P8VMF8!Q4QQd6+1Io&3I8pCE
zrxHc9Tb&PpaTG#ml1=ezwj~L)3<$iz6W-GxK~d7Zg~a>#r{VU6x2EhK$Y>EeO%nyU
z@fzeXYYb?R;;4%7*L(l(ca|(nX;&b5qMgh#qii|NH`~0hjvbJ^v;|AN?>*S@;3*AV
z#rQUP)_cZR@EJ$wjI&P+V&0{nFAJwvbj|7f-{v}EOb)1{@fsgZBB){FTDLpUs!~W$
zHB<ybfamm9z>#ik9FL)jxAs8pz+y%8UR?(Z-PH;YqFjP~GY~gMzP+=wP}SE((hf6x
zj|bbE*f1kz*j7=Y@6-j*udk^#^PLKiLzOoST@EMpV0$5JA5jr^saeqEJ$LVs@ayFC
zI+e<?IT<;$sdMN$m(Us*<Y^F0?=;ZG3e%UeX(SI2%0KJ+c{QO77}RrnL9IzvziyCk
zPuiC5YKulG+-4^ZO05ml{ViAiLf%HH@+wmAV<!9^B|wFTB+evI?DF~>kQ?{<FWAm~
zNOu%g;_Mn`T;b>kcJKl?LNIT<De;s8uCX4eZ>Tbi+7G*!|0x;jx`Nm-DsoMdfn{JW
zA)9M(VX2!cav+oJE)(CywyEVHEl$RB|8!V)pjL7bV9a^_L7la=maPSDXms74C~%Qi
zbw{WG{(phrcGpdKWGi}t9?s{0ZQnE*t$os|y_=qbOlk<!DE!$>@TWP-&L*&ekTFL&
zTp^4L3293Uv#r~YdzWn^i&nMC-HrCpK2c5yO^vuuimr1cp=&Ly+-Q^JUN87#eC>~Z
z5}QC0yjrLG8Iz>Sub+>T>TUGNA|E~ieCH_r7+A))PMTx}U_SQLc#U0p&9G-J?l`a2
z7uKjow;Jo%GXqiWjJ1@rKOZcDp$-^p&y!4i)VPPGg%HI<ck4m1{#3~L9olk6wF&qA
zt<O3TdRb5Bh!5swjZ7Hx1H-m-RMl%;Y7%8GTy(Rix$%p~p#%Q7Nr=~<k&hmgelLIZ
z^2^WaIx4b~IC6&CC6^hPeB(y*{LvIM-JBFfsTKkwNRLR_SjpTIA5~eAx<RIB317AH
z4Tv$)Sp!^ph>&d%T2I?Ww8)N1*uNeg48TZ5lQhffGmw>_RbsXV2yQ^S&T+XQiExu~
zVH~scl}mzYrTU)^lfy{7&glPvveegVV#r?PaoI)Jh0$s(Tk1ELl~?T7^R`SESr$Ml
zmx{X65WQ*7)`J;J1a=Kzm68PMWW4-Sw?!T~Hf0}IcDzK&mj#i4`rG+F62mO@M>pR|
zs0(y~B&4Myp}!J~^&@A?cJ6ZAR-D8*z;^3k&5xZS?^z@+N0KvuSai8qaC5fe3rz<l
zG1gUg@k5m*snhfv%6+C>2^?D@2E0JZZdsuml5Jd@BIgSrX3Jo|%k<@$_NQn9TO+mm
z^d+7V(&*w%Dg30(OlFG=-U_Ipql^K+P^Hzhv}Ftf7<l;{Wj02y!&5RS<Bdw3w@7I1
zj7umQfRfw%vL7{KDWrEA3^HLASfBE}q5Za3?n%qoqMkXq@W~_?M?`?_hUGJ&Rxo_y
zY&5@y4oGywcSzo_xYqyp1sp}i@!&HKy?+wVFGojJBT%#|Wy$er_3taBF7D6QBV=p>
zq3~!Mx}bT3m(P#S-+v9m{&&+XKrJB2Jc{9<27_&`6=_<HV?-+Hc+9cciSB&TgRVZ|
zV#*(rIVNDShTIP+jm8*#S>KFC4ht>+#*`_0R4=nX%%1%UZ>)JDAP28xVXZ3Dc_c*R
z@thvXl1fa3dJ}bIYEE4Tx}+11?yXb=0@XpYp?7SzcxcpJ4-Ol<+wK1g$)+^At54(%
z856#_lAp0oSFsCLGh;ODt~jE=4({EMk3rzzV>!PbEwu=0M|N;VPo+^;t!$#Lr0X;)
zK*9g+q8s{ZI3s?$I>}7|u-doaegnq|?HZi|La7L+co?sFqJSQ+anncFw|-sc?%^jQ
zCg3?hlOg2d?_3?RGPSt1qpxGWXF+Dtj`dgle>k!c(txfRVT^nCu>sh}{naxe_RIyU
z@Vz0^J|47pTTP_DL@1Cnx2~HqUbMsz1VFs)>4?D6QF_pXqFmwVyV`52Yf9ABhRz^1
z$+nLS&M|@7^^Y!eY#G$5R_C9lA<>l;bQduM9m8LrQQ4pZ&ieIaF*>8FoauF?KXo~g
z%V6}}oV#;Hd_k6Gi5`$HFd1{tOA{HliHf8DLTK55pHx(^Q9#Pdc#RbZL%~hFog?Oh
zMI`Og6nyZ2^a%ollM}Zf<Fe#2O!W&D|Mg%gEf~=;I6UlB4SF4ak>=ls9j1Uhn4Jg6
zdWIt>M=&+b6dd3R8drkAZxt@p!X<2zvWL9z)*Wx#RO}!<X@E1~9Jfe`JXaR7gv7AZ
zf!V@qI<afn<{cjFez!$b<B#R%{IZoJ43*fo4ymfYmT>u$aYAZ@s`Wyii-ZZG&Da5>
zdh@+3b~dV)Nh_4F>@*O5ZMRhOnr%K*GJ{?g?Y{B{zqZuPb7;)4yrL#{h@5T~_PFf<
zHq=tc*V*4iJo&%d*35475Z)H1(@)ayksE?*l6}Ne&HK<0J>`Rs76fv9XHGF30tif<
z3R(qm_L3Gj%IF&4xMQDP<;q*&6(WNDs1@%S<`}Ec^DdRhNkK8Wd)b!AQ8-t!NgNDe
zLBRbIw_li9_A*R~AwJn>oPO8O#H2g5%R8ZhXp=s~N46s${C2wa{nL&AZ&XG^Hkw(;
zL}a^!)T<O)=D?;3#z07gcFgm}vs?bI+>YK!Jqtk&p4R^YQ<Mbfl3{^SgZ)YZEbjQr
zR)wE{j!5GS0}V#*=g{b%u04;Bik6G+#RHl;_RZ~2zvCm=zMgWIsZHS3tW&Fc^TEs8
z^`ySs^$f!Z#;8FJ1=9~S`t%mhplb404KdmH<IztlOx4_<4dg?O4PK*1>Mq;npaO!9
zW@U1_w7Fad)vu}<i)py~*~fs3pNjKs*oJS2i)M9vO*1Du--q_qvu%!Zb);r9NYF>D
zj2P-hq+K*C?pZx58-jJ$LUA&9nI#e#a$Kn)YRW{Z1hMpYO@KQ-2}n{@N|GO>o)1q%
z$g%PBX{BOc+NfYNH|H0iq2vMpFaowM-TtD$JgH41A#2u|9-;vPTT^LdjZ6#IU~v#0
z1k5|(idBldT_t^bar8}hduM8>h_POUB7w=4+lGWqLL?u`slCurTfVc2k-npkYspG2
ztJTn&un@u%%k~G}8Y(n~(zYS=fy&J82ZqPE%jEH!@zb=JZSQx3t)FIb$n-iXE-+x>
zqE)yNGT7d0(7@@Fl}%Vb9R9x!<6NnYd>y>>RBAaL4|)OGKb8$#9~BlDlP|65Veuvy
zj5a^O?cX6OtF|j=iW3VY!$LFL<@%tbUjY}EcFt}m#D-Evju*4@EhH1M4R%tx>(-D7
zG<o{2K}Zl)jB8t`^6Z!+d1G^II?bO;%WYuIu!4TA=TfM%iPPO}X-}~yT#MYXdimq=
zOj%fnsN#w~WlWWIPLPPAAhANZM%dl7DkiBRxL6MYms&jXlIP}Do&X`bL~!qXAI%rZ
zJJ%qfvi;LQ?eCYIX4(!9b4FKdfpFX9-l(X0nZZGc0*$r8|Ky%33A^EV7m?RgRiOS_
z5BsLA%qmB{QTMlpn6OpfFL)ac+&T3s8|p}&N8|tkBLwsIw#W^aqbe2S(7Zs8EQxG{
zVL<*k+h<bF>Vv6EMOXQXaz0h5DqNUKNX?gy&OO8CP)0uO4$0IyI2k91FrNO+gSUC9
zAc1yu(k<yng@fL7;y)qKS8HPJF3;T*=!e+FCvxCxI)wU!%JYC3@GC;H7BQzH?#XIN
zGcxaO;Uch@^+c*#(t;mSfI5n^it3B2g;K!{cm<L_iROk-55(Uk+4R`&wPlaeM#Ics
z%Lb*N!2s}6kyUBjHp-vcItC#(`)jqSw4-0f*&L_*uR)P(IOyWJu{+us6>Jq7v1aoD
zwH7|NchNe1?&WGd2V(S?(+m0>GSJG<C;a(dB&YAx5usT6+XZZyC6`6doQa=*AG7$I
zafX02)-WOw<47F|HtNbol4=9szOu!mWCOPgZN!h=(OWZoFwq>NvrMi}TWWD^>LZ?#
zL|%>^_cpbE<53$RU87GfNE6JPnV@i6`$9wXcC|+yZc(HLwk5`J`5f9lJ+M667vOG@
zUG;L$z@z+|@nVt$GH0K<LaPcZFwn(xYW5tav&dc{U}gecJ#-N8-W4U$qkx)dV%6}8
SW-?!8!b6sonjF1@<{>|6opWFS

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v
new file mode 100644
index 0000000000000000000000000000000000000000..e1617067a913f945858bf026e2de461da4d8b13c
GIT binary patch
literal 5072
zcmV;>6EEzG6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlQ!*GZ$O$yl;H`D`+4dRE9B?Qv)
zVuMD4kb<q1m+LRl3MehIG%n%G82h03ra&)SQdS^yakkDOW0qUjvX~chIl`dj-c)AR
zOw@k3gpRh`WmVHpKmcr)*1CEzBz_RUkW!hjx2g@odE_PDD6S0PGL{C5-A|_PS(V3|
zbXTuFq6(wEHikZ((`m$nju`igHV4p{lL=H#8;HrN656d<q<v>gN|3ghMk$+A&RBPj
z4<T_t6fkW@VD>BKE$5|Lds}VQA`_e;@>2qGF}M}LF>E7Yg=U)95z9cwQnsuYO*@(}
zUqtonI3K-T+yXqt!}e3V2gJ*%`_;&Ewk?BT7Il0`TwkjvM3<E=6F0-k!`E=qFhZC_
zyl_Um4bKl~y^jO|Kd#JhXG>fW{EY2<qTO5m2|KA_e=M?>^v)~CwZR7$DdC4L<QVa9
z>uMkLJ@WY!6b(S+jCWYC5Hs0#{RU|f1)x=zj#irha!4B)oR<bqy&HNoL~xnhDV!&Q
z`ydgkb<SyC_tX{@3(MIo{rTB(%q2{aUiO*NwuvxUALA`g=EI4~3sIMOl1=C#@U``~
zjH4^1BoRuo4O??VWstQ4bu=G0WvY%YZR}i#fJrmAZlTHf!2~k6qI1yfi_^0Adn<lP
zEh(Z0&EC<rk?a@{QwnPbM-z8Q6RYuzb8G&{{p^i5MR5{B=lSBI^_D2K=}XM&XJsSc
z&H}ldNtoq*-Irf9m#>yMM_9+JYXOUy{9QVx(|40^?_4+Vo3~jcFVZ6O605}YX1uIj
zOSa6oIl-S!wx0(fRp`pv87Gt`GdB@TQ1~JcsWB}?mWXQ}LXI}<lq0G@4GO&>Z5gHc
z2=J}^%yQJIBdF)4s{CSbOV!>m(H950x1hTfgZP;K^H8LnQ)J_kg2n>O-0Vd~n-cR!
z@S{A#()Ftj-UK{cRWzw{0_-0Lp3p*~n&pd{;c_lIZS0V;4I=|`$3?qP08H?xoUJlJ
zaZwXwF}2LHMgjhx!)qx}%o{dXHTNUZHhDewkSPenXWSq)|1Gz7rFn-~>h#I37CI9?
zUm|C<UXu&#s&Y=?RlNwqSx4v0V|?N*gyeE&Q|KrV5TaqSIYa4R=dHR2!Rpo>quyuO
z92kZ0qU>zt2}zM~I4QU`frW7!9mb&Z6A6F2AQ)@g!lD@J%Ej(;PkP>7@Fx}-+ra)y
zJe(K31NO%3Yc7PhinfX;6Hz3{$1)iURrU`EM5h1P)T1DPV5h?H`pCz&sr%l7JJ!T_
zQe*t4{9b9+WUis#Y*4C=>2@d!E80K&pllnJ*-$Cqot1wV1Dl35drv~{w!76KjjyZ_
z;arYLTdIE-ZCU^M7CUW}P<TgD%BRUr1aQ4pCzYH+zWyshnoTw~GyUTXq&3C$wFswN
zVgCcZFYxJtZJvtXU*m^8;*`ZLOWb0*u}K<w!iwb&wl_iqRE0<g($_U3FYvHmYIve6
z)8<C$!n-?G)^j61ZR^^r100!hitW3Gxc_WC-kh4rs<eivDg?A0s^#@On-Vx^27FH_
z&tkQ7#o=v&<xqw0z=s^!&JvTZd1uE2D~1Ju-yB2WPtqQcdKZPD1TvU2wTsIaTpG@|
zLJugYz_sctc66HR9LfS#*?W=ZABYi2z{l(>{vx6r7KM{~8taVGS0Sxd)SPVITkqww
z)whBF_bYXCS1WS%BY8^Pqy~JBCw{9>P>o$!PGtf>2b}v3@cI$1;O+^HMA@yZtzjZp
z*nqg@X>}ezcttf?KhW#i{jLwg$?;pmBQG5_Rn)8{5tMFfHG|6IRIp|&AO5b(Cfiu5
zK9wxfgreex*-`pwsADA%TMVZ2p$K%kH$1ivuf)IHD6A6xV(T0V-U&Q17!5t(ia6nc
zlk1N6<VIpUHZdpu(v7d<G-?n{E?TYa5qMu&lMg42OY@~<32^2GF|LWP&KW2o5%vt9
z>*!Vu$&0Cl<aAakL9QIk_&S@}^2){i7X2aSq7QMb?-Qxr{e?*KFMYpn_Rxac#fTRs
zqVa;@D=Z1KVWtC+YmIRhrA%feDMZH|zBRW#zm#ozio-4|WI~bbr7S{nGuh^#pUmkF
zaFljyk9*_PH>)q4F7?^kz`~F!a)Z*js=T-egrG1vQ09-}z=w8X8sULUMwc}UjlPIq
zyC<rEC?A9lf^t#cK{DNrB2IN_m1|l6d>_8Z`a=ci#FUN%6i4fmUYc;UJ(~6}7au7<
zZtRjFuGODG_M4LN&Sp0Z@5RAakDWO3xS`}ph84vp(E_?nRJVy~M$UcoC9B8<YV_`&
zWBAxUUf&b+!h*KXxF73C;q;v0SY74Dpeud+kpL8hOw86PnI2K(0~D7_XQI#K>AvO8
zVTPQ|{A${@Gp|ZMS@hHcQ0!X>25f`Qqd}=O2ifJ8;Ipi4^O>3$ATnkr#bk?3@5VNT
zduRoNK|IRMZ??kN7EZ=uDK2mG^IE<U4yd{K6E15Q=P`CovRNkzajj{~KOQNqV(>31
zhDaCBz2{a>ktDJh86r@-w}mBJF>m`h091Cvr<z)Cng{q?SX`c=7iWVP2sqvPL`tW`
zI38FtquZ|^M1_~bVIT<wmeX<R{KB_2aEXHwSIi!fp!nPoEUVP|(g6sc_t{Ot>{K9Y
z!z{?#5N15)$2#cMEdE8AkRWV2Mrh&2lMlPd2&3Cnx!3%7Ay4paXjcw$E#>7hBQ{3_
zVR*+<bCfnDirRNX6Gzxf#tp<9dhCo&&sHe8NwSx8T*&Jf?m8Y8%0+1^6f+TMn;McJ
zv2+q_Y+n^=fvswJrt(iOkw$4-o@uWi8&O{zwK=!A=ZKAwdzM};^S+y)b%5PMLy!XF
z)M2C^L)x*?MnG<`SN@=U&3;OG($#{fl0MJzix42p$lbS5#a|in`K20^?0*iaBwU0$
z416Qh9yU2Pyn8C3-d`!^Yyt<{9*U;9Ea|2dh3FGF18^SSElvbTQO+QU3~MkcudA73
zD<oh6*#FLZRy{ER1I{9(_jp_^ma>=qBLt>K@P+~(TVKX1Y@N>B>k52KeJ1hdagXiq
zbV&QjPeb<X2=6AB+r-SvT+~&$oe;@_;bqrQcsmOXwyA)$jDQ%>KLgH7!smH1GOa9+
z<M(u>p*+0U7)GU~5i5c!+=5^O4MhH6S+J}C$XQ*7Z;gelGiCll1l`I8$%W5dQ|3Y5
z-UQfHdU<ca12JjCX0{k3d|s&?^3oX8u?Q3o5MN#Fak(xoMCtiyJ6KFI7|k>;hrBXO
zHNDQ$OXJpj=T54#M%?$G15$?uAoaXro`-pcV8f9`lJ;f=>f<Q&ro2A-7F8Bd`Xne*
zlk!NLh8A2}Un!EdLq4PWXv1+Pk<KjNIPXZ-_=cHdr>hV434Ol1&<dHeT=44OmrN)W
z%-#9v57*$Imq4hb^TIg&%Z-WM2tpx@qGiU(sy*QDo+!Ud6V8O`yIqipx{@Y<WT6fw
z7)zfmVJ>g2%|}=2)<|AE7bRqBpVb@-qCS2Cg)s1|ty1Pj)S7_5Z1>}3R*RGb1D`%8
zCM?W$RL_TzD0^ZJiJnk5ZHZqKHO?2IH1MK`|DF-xa{jDj*fwORep#mOhVZo1W25*5
zo6b=F+i^p8iBgGOvwt0~TBP1W_ibcN_ZtJGJu1^PcWjGJ_=q@7sNMKolRdfd+su`v
zdF|-uLAv_Pi;F^zO~H^EodnuahY;PfFr+wIdh-unTIQZT=U>2V9)6+wKNOH?PFfgM
zue>~xzY{j1RBB`(Imel%i>Z{D8374mnVHN&z|${f9myd6z8}oES=^OnDKqOlluc9D
zz*&R|hIU61ULXJ>NO4IhsjqNXEZig@9{9>RI9)S&MjIuVZbl09!PIkBPx4lJk^v0O
zDArrk#UXt`WNA?&rL}lk!1;Hy6Ir~2FBK2;a;->iAs^Q;p>1j1ju#0Gn)+M?V)(Gv
zq)=}2c<Aa4gbZfNzo=}$Dc_X=13xGLw0TV$Yv2llVO+wpZ@1+nw)&J5YD(L$S$a`>
z(&<2ue?EXpOo|FXkKrx>{uRu>@wPhg7$SL9M0v!x^8!*{vsF56++b!5Mn+T_s%Qyt
zT+lIO?6Pjr>>;eg3-t(qQ9JV@j<X3B56G^0w2pB5(tPw6`KFa!_W~oTW(cmyKwGa4
ziZ<iaKN2KFIXrd}jZU^wTVmxOs!IC8xxV%VBfgjv*!F1C?tHPP5Of+<FnZX$qm8yk
z-H=qhx$j0J77o)DIs9q+^8AB8!A4<hN&j=BU{hx-3>PjGKt+cZnEEXRqm-%Eqyx%)
z<A3(OjPn9Z5qk@f{}F~fre(cGNR8m%o-05OZV;k|ZZ_1>!s1r7&o8=H`&U#A0WB-~
z%R0JPr2gI2QDhm*b0V5_?nFVEhN2R%Weh2_$f+{hGm0I_$_~VU+F&Pi0AR}qPSQ5&
zkLw)Fg&|7K=Ty_uZ0HE<2UmB#KmgsO269AdB5=ekRe~kq4Fr4>vgi|0ak9Cshv|q4
z*MK}Fg&9MTKysIP`;&qD^e4BjB5KYdCFs&Vb|lBv;{eY0)r^Ypmr-M^p`!YUh8*qS
z3jH~8)P&<C!#RrAX|Jh?O;c6t@MJ?c&>B+rCFi&Jd*XFM8R5wU(JghB7A+Z^6cDmG
z$X)}_Rm1n+%u#b7sU5hxcA8|j7T-cmytge0<a|?gPGj2N3{!tp^1)(k#gWM|=zTYh
zusy3CQ4oZ6ad<`~lqw0~Z4FToIzLPLb1ooDKol-lg$e!nLKtd&19Mtz%>@VIc*zw2
z`Gi}B5t7jwLXdlWcE^eYZ-G2K&=STYU}EEz9E=Po^t0y4v68GE4H*6FNQd-gV`@oP
zG9SDSW7MzZLhVv+)bT`gnoxx{sQT1$DHp;ug%c3Sbs)dL)oQo9oxq-->17j@Kmej$
zyH@h*#~8R<F3o=BZ*A+U_fmKyR*ly5kNpNyXT5>f?RHUAB1Xfl0OeQNFeXG}_fSs^
z4=NYv<<qQ|#=evvrdGJzUVN799^b20TMVu&JZ%_>h1JDFDejet2EZ6D0{vDK2%mdm
zyh6k(@Q6rYNI9pjCKvd%Q*bgo6z$%X*^)0@t%ga5yfG;>!<T=AJF~ouB;_BWPz(AG
mX_{#*;CsM4HLg;OqSV1>2rpR&e(ByGF;C+^r>aJ$hPK$g-L-H4

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_nf_rgmii_module.v
new file mode 100644
index 0000000000000000000000000000000000000000..e7253798cc34988c5f3aabac5884a6ddd7ec196c
GIT binary patch
literal 7368
zcmV;(95>^O6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD7DRD7Sy-syKn-#-f
zh1>mqiDs`a;<9YGuKardc}{;un(v++g#mAy)Worc2e)y}3GjZH`DhE@j(5q*-ypt)
zgFQInbCfo5zo4l5;L&%>{D$?CUjq^Q{ItTPoKmo-;%3bk67o&KK#t^@b^F6K`R`dE
zKZ*En@-n#3V5dZFNoZ;E){0c5`c^C0=~7BSqP{FU5@;~d(d9-YLTsx~=&h7`vs)?o
zl1kYE6qTq>neNG5YKBc7uwU~9r<O&;j{50q#f6>NmawYmvskIb_rhVF`aJ3O1jG><
z;+{T;X^m7&Xx)6gt!)Oh09iS9r^b*D6hl!h&Q$P0i@MUIz4XISV5gw>sdy-Q%+5@}
z+`o$GA=nvz1RAbpDMIH5aV1-?+;o+S9ZdwThhbL}$C-zV_A8DQ@u`DZTp-s_GF|r`
zbgQQdK1iI7olN@QMScT$;Q;7^s7Q+6{rz!@2L?n_r0ZvLYiOYD+7c`B`1UfZaTfha
z%V(f^e1Vb^ONn7PN6{P(A}2Se4Lo6zO;EwZlePDe_#Hy?=oeUuS$FEet4q_=cQ*}&
zbr@DlP_S?F50s43{R*aEUekh<qxPiRPq*>(eXga1H5g@mbo}unh*{)%G2RI0zNmV2
zDn&Aes5q3MbcoI`afg`|$7H(a!>HWGa?dB1N<n;H1GOny$;vQLxOO`H3m|nbKT!__
z27Yj+I^}{%YZ!8oqWDW`SDbsOB0o}>-B%K8w>oWjp~Roo7CNs0<uGym?5fhu)M8BM
z$>08l)KVUU=)|k5LQF++@v?<V3_05OYm)gR5H(+R_v6Ws!}c2X&+V|CjvyeyVWI;r
z_ZNo_f{aLLtmmVd+KU8{JhZG!y?O2n{^gc5L{H;eavtI{M}Qy9i`n2S+?l=)j&(q;
z{CJltJn=yw{;rBFr5yTOQ(!uU%I1q)SS0WTV1`Z5jM+fPxjm$jfOu6qS`<LYf9WPj
z`%m}CIo{R0o>A@LdgM4(nuw>`OdeV5r!<(0`s-{`$OqBODT0!KuX0iV!Bk3h(2%q#
zsR{5q52by$=EU2{H@4HxR|Rm4dc+fi*n0R!43xaVD|6d+!|jrETjHJGP*IrL&foqH
zd<OwcKR^$igAPzW-7d2K-33Z(bZe+_V_p1MMDDp`Hp`8OLlKPM!(5IZPrR`wyV2wV
zZ0_5qAAF)h?1n)JHY8!qW?|+f_v-$Rl~aQ)K{AR*i?^+TPEUtRWyb#J!ylQKNLdT(
z)^_$1zr`!XdOKx$tka?)pPQX3gST>SAIeFx^1XRMBK#z|-_eWHvJn=Lg4-{bjGGUk
z#a*^B5+)^LDf=gT_`mq@LcR#d7wKhbT8BipUG9|o9~m#KDg+Rb|40wPjsGWohNLu>
zZlg9T@l@mso~=XVfZ&gFrJe>~&eGSz7lLOK&}@uqv#JJ3wtWmnnN23zRXgBzYA);`
zpSSG-@z2FJk44<UU*jl~2YOHE&~o<P^7~VQZs)QMU|yJ1yT{TNgRxk2KZrHB?r*$9
z|An#bBm-3c?Ab*d4ooGLov(XgUdoW#1{o-Wz8OH(1(T)q2_%Ch!(eJI>at1|xr)G|
zfz6QlT<5=oWQ)Zimg1BcmDw)9EW&Ztdqmfh<l1*&D|a5CF<P(#YR;&NDJn!WqW?&x
z9`Ae`RVlMI7-=bMbrQ~N4#;Xt^qIkh|CCc>vlX$6{5lC}v#88r(#vrO-nYb>n;L|6
zRV-VzY-(4Zwi~Gpl%ilhcjwZrz_u+jSkZOL<LKEfQDIHbxAjwAw~;rD7{vC5yj#+q
z5dtoBRgQFn4Y6c`e;~{cJc>oW%V^wDZhvkM?A*#~t~3gGvckP>FslRGlaME7ezdm{
zH&@Tle|b^HtD&*8Gp-CFSgE_)4V(kTfil|{W`X}{?;ahO$+I&4Fp19{`0|tQqu#Qr
zX7^j$7PqyME7zA&_h$!Y{XKfVs>f1_>*A@LAYJ!8QH20-FLD>(TpO>e!O{9t%a~tK
zip%d3n*i5|<=;RCoI>jY0tMIW;3fDk#^eGjw9Fmh>w8WELQC|^)})3uwsgusb6+`Z
zNyrlMxhFL2yL$tK)A-LGTgsxcp5$(3I4fmqDIi?Ba38c()UiOR?F<Jp7~o6tqf3k#
z_d^f7=i3IHf|Bx8$nWVL^NqNMU5(0SHuVCLTbyOKoo}yGXTq@Pu+CX%Gx4N5K2UhM
z*fqPQ?G(^isO}axlunZ_4q~VDCD2wEFnL+RV;q>(A~3ayMBi8<5^<7gsr9NMnr13L
zXiL<gcLXpWUeHa!4NGBDrQmuPSt+1rRz*iyIrsyVs`5&bTw-3JeLxfDHY!#HuZTRa
z=hJOt>CldVEq;Nhd;ge{KCa(BPzVbirq>pm?rH96Zhz4b91C|-0f#Gl8P!+g&?nH1
z`yB)IoB=^1gHeq5k48cke#!tSQ4nSqO;v|RA(6(G-y|`EP2+Btfdg(lPTdva8Iv9F
zrw;CmoMl-xh8hx4sy72@0Jm{9(JLj|eCrnBZWcB@%WQd<vPX{@Ufiw=+&N+yryRUI
z?q|sNfDJ#}1xRAwvpZu0b%R)CqCh9|9P<-TqX9JIL>mjH*DNfk-~aen!7em2uUyD2
z>5VVk3J)&<TPV@DT=?_iM8$;V*<(paMR@abHTZF}iJAPDr_<T%G)T1}q_OzfScf#4
zJ5@;|n}!}zbY+hwnAH+bqiSbM^M3!6Tas#rk5#6Leo5S!lLhPTF>R2h0z%@dzOJ<}
zi9=oG-jB`M3j@&Qgx&(`gjMU-!fQgc)bK`*X7=>e`CLwFNWCJodV1-scAQ&AN`4sS
zA}kRtHk30jSBJas94zO9ec7dsH{&)lGTvT%5CHRbHlh&Ur4mAk&J69s-<H;re1V-I
zs$WA!4WPJw0?6X8S<4YXr(?qa9-b#c5l_3Ve7qSv?D<M=Egbi&W|CB<M<V=Z=3Nx?
z=R2zBr)tW^v9{6b!;0B^cOz#tm6&e-pV0y#?I83?2aUbVC@gh!z<~FugF}=O2hvB9
ziWQ<x*OPfbC%+smS%#4iy<%j35xV+P(ixCX>23*r4_SANM^@lQ1}W;9!DLM9s>5fJ
zT|$bEd#4k6Q4e_Xjac-seMKUUa-^P#Qd!pKW$f=uj=ky+G039CG#bf}z8A5zqawE_
zVY=O;*CmhuD-9A;1&a%outwF@Hi9~DTkZg~AdNclOkj_%RCNE_6?TPd(x$3B`&;yc
zN+nABtzq1nYJfEPYH*3Z16?`$Wa<cKh;dJnSZV=6BuNzFpM>G6ncmDiN+`t9U^ifR
zC-Rb#8W;@pUXabC;NCOE?rTd<PP)1j5;^e}Z{6l}yfM`sA4*ZhF&tnwbbNl-By&ym
zO72Yg@sIOPQu3S>mT@Jj!quRB5NivPM1=GNhR|5(p>5{xDZf&{>RrhBQF@fjlx*mA
zYgA_f$%f4`@;Mv`sJ?BCO*fByx0u9!Yr43-I{!W|PvFP7dO}@X&If*BMdi4R;%{~R
z5h+m7P}<@git&Gw*RV)^IJF(dbHuBOy)4Uk@LWl_qj|4o6`N8kkmjOz)t(x)PFI#(
z>Be|#MLTA+8^O=BusbEtL^i70j}wK28XMxvu0exR98X7;B4ZQ)$~e4I6^j9d%eS|9
zD?`u70{si2O{@*nJqUWw2YOz!bEJ2ng@iZyQduTTBmofox0OtG!43y|?kC2}4bZm7
zARwNkhcb$CQO>+syCW%6SQ@6}89}D`y?&ln>F%{`)cMYd%h=NIPi2-dgiAY_(i*}p
zY5qJspXfyaa>`VRzi}bLMTSflt(-Q;RR=9qOiZ-zB^CS!nAtSty)&DtvwP!^L2l`>
zp?$e=8c=h88``!b5j%k@#9C1241lTEk3dFbIUluV-d1HiJ9}J*p32?=F|x<s^{YlQ
z^WIT%AW{x<o?-dRc2G(*tPJfjM?sb;5l(feJpgG-&)K?oOXO1TKO0zzbsjPxx$ROA
z(VwREg|6{N*lEFFLq<34ULpF9<l$Y{z@zUSJIXDtV?oErxx^h1Y+r0x0xc=n_&Zd{
zkPWzDETgCdH5K$(_3T;^ZM(<u3#_E(T-i~<fc$N!P<q^hHUrbrD{>J@Yr!VJUnQ*F
zVA2SX1)-Y+b{MXX?*`;z4Ujnw0crYv0Z_2y^7_q5gmHgkdX_8&e81A$xQW+rcKurY
z5X3l?Q_jrQo3`hSUq_1kb|{(o+aBjcM-K{qMBu|GzX6;4*s$+3@TrDOp0tEaX+eQ1
z{K3eIjki&IqN|l5FDlbSue|Ml<i_282H1{TZ#tDw(hgATzi{+w^$#r_H`wjw+P<=C
z`Ry0tovieE#-XP*!>B0`9|NH{D{Su`T5B70peA{f{Lv}zb;(cr>4i_JppT0I=DWxE
zpVUKsk(8JDvHPPh!S15eRGyE17!lc30kV_?2RV5tqBC@|h2Gotg&~$@P3i{-M+9G3
z{i;O`)Db}B9#jolV;b14?Zuro-LZ7J_u%N;Z6k5T>ifAOSC65sH`)+uF1deom-1X#
z(<o7u87==jMc95XhIi72T@eb&373xl)|`}f{49uwMQLqdSrW%?y8Cm&XJOuc=ue6>
z+42lzN#>5jAYy<EyP!a<I$;PXyYD)Dxnaf}tsm9tB8FDUnH;;q1ZEYS0ncjWFT-}H
z>F=xSWmIvy@V^TxBNDW^KEDJ4AzN7?ZiOib#e{P+Fvy8hA7pmB){Ipn8cyMQ<W#JA
z!#k(F8sN8Gil)!1*Bxs=ZYB{iXTm)HMII2f@{UpzRjUo)fLPU}Q&%56$2}UgUk!7W
zaxLd~LDjZO{PCbBj@N}Vq8cG;B0)D6Vg#Wyv<(^24>xh_CTxTU%grID_sB@{X$PP)
zzBNb|ehD5^MVE{}BW@s6($_n_%*~1#c8?E+Hy!p7a|&_@S&Ya1*S%pvfu><VykbNz
z`4(dxKObCcU>Jczo{)#^rTSe17sSxC85F5IR)JnSES#cIve9RAJXGQiD);w6)m>du
zf-k{qE^8}0D!4DC$bQ!o#w4PrBKIG^j}p^wO4gR{<gDb2ov|FrLeK|NznQDUs!5mn
zs-5JhH`L%UbCK4=@P}Odyv?|-ceBeBZN@W|bt*`ld;fihu=f^4w2x<`+YROmkvK#N
zz$*9<pi@1M@ZN&%gmhwzrtpfho>TsW#cbm$(CB$6D+xj`>i<9UFQ_MZ$W$|$quK~p
zS!5DmE$^mv1KocHI)^^cE}WESiuO4og)NsX{s2p=OXQqt>njV$p;+-cq}s0E==0Y<
zD2Y2JEll^cW}IB2ZnI822FzmhRTx+H3&Y5A;&K_%qDL-J@-s13UDTZ=N;(*vN-`f-
z;i#p%{ae&=5FC`GotA!L%MAXTn#=XlblKDGKxu5oPXZq0U9X8O$Ko2js|YasBGNiE
zuW|&jV!F6UIQM61faupH*!dstmlu)APCcn>L-HQOY$8P_rR9>~Xs7R*!S<C6=+T1f
zy<^m3>gCuA0u%3>yj<y!KcTw=`;+YZZv}KZ<%Ee2=IMdkEpX^LNeu4gz8eB3Z`sCU
zc>RCh81@8Nsw5ijVKUF~nyJUXE&{ePyxXD(&?wO85aMrf*(8K4L0xII*p~zvrr#PC
zhW-y35Y8sY=w&<cKT)Hi=(Ig&uE(tNZ3degwl<s>b-T?~Ct0ZTs0K9{Pl%{({C;M!
zMO6@|*pV?oxGg5Io?tihypqBL4!ZDnQ3qOAHCj1sDZ-tLNZ+g!>E??&VgR^Ufl)qu
zCOx@2>F`m6l)GE9Wt5zju`rd50Q0rtVdljKccz;%(4}oLG4<2EQS9{{*0y6AP5#yT
zFwp%o`rumY+#qR5aW!9}^?@-tAY%+``~G`b5`v(GF80L{r)Td==+($AIkd+~VQwW|
z7o$A$f71yji@xlTaA2^rYdn%3fLU@Be*L-K<Yv3(CwJesjA1XmE+P6D2U-~U&KQ6@
z0l7W#z<MAqqPpNvZQSPdR{PTGtTdBSE0KvpSrRtdo<<OM=9*bu;70?*weVuOw}=CI
zDej*;s;;bVic<x^)M<uWr7T5F^E8RcruTvQqs1ePr!2Iu1Ip&~5E`5^&`7c#-YS#5
z{VqPB94Pf}uRHhwS7xjw{`h2en*?*24z&F1Ctu#D7-989F7x&>Qsqu*$Lr`bbz4ZH
zWWfujSuX<tyGEW=txJR&LkT@l1cpD({0uiZbaocc40Pc!S8$|qLff|#J3qGk^$-{S
zvwvKr^dw&oscZVPfVSAa%p=SOYA1!V`4I))4zI$5-Sx42LopZ?|Ld{SE-ayP(S|U#
z1vm<(xv7cKWtN{GmazyP1Qf(CaQPjh8t(V(R!y2SefG4Tfv``gxgyV_r<n5|Clq1w
zi=lA<5YiawV~Or|Mn1MGLxGM4tW)1E?vZICY!xXLZLz&A8VF}mtTzA+i~5jbqgfRo
zDC_Y`&Gjg<8qiN!zKED^V)5|ZoQZb7HR4XEc*w#1UfQrpTaAznxbJ6reBIgc(`9yb
zVIgLz3eRE_DLiu%$o}ub<yo2gRthw>|2m1uW2q?%)3X#g8}I+A`mGtbCcdqXwD&Y1
z1ql`;IGfmV{PA$MZ(J;qgH1M&Wivf*$-xuC0p!%j3r3oCZ6(~6Nm7mnNe&+p3fXzS
zq{OtaVzNRN)n_c$J*+kmF3dt;Y2}*?V1*$Cn#{_#EPryg=4r$(tsc^As7^lYi^J_)
z7qfUVYpDR3Xr*V;lYYrEt1!9FVBSM1Hx<&GAq?l$qtWTK5Z^@Y0S!y6Z;aSkhO?zS
zsTL&sFc8glgKwZ7)JSWw;GEo#t&_-Gp!#KID$Dkz)M5p+a^=OCeaZ`=J+TCWB9fs<
z%kPr90(C>*nOR09zYJX1*NMx9slgyaO;cx_*2k*%l2S2c5<Gr>lGI*r$|>)y(<n}B
zuWI&PnGE?qQUDuW0dGe1(Z$Me$J8!A*5T_>VauBOBLr`l<0)&Lm>~`o*ieqldqs1>
z@qR3fVA5bZsvy0SPN04@{Zic$D}t%xu*(Fmu@|R~;qT>x+j>o(Fak!8zmSz#u(KDp
zp|KY14DslWMnaSN_JDQ{kTy%C3sgwHX?M9V+z~mKs8LrtCM}ke%6Ft=?f!OXIw%Ll
zUxsD5WtB@f@X{vS4zve--6@g{6r^c1yp0b+#0?6r|ENcpANVRoKn88BlozZ;gr!dI
z)N<FRW+Ia?YZc$Nq^PFfptZ8Xgd{6I?B)2O#ug_e4}|nb3kQ-LZx88;3X<@D-Y>TS
zZc}4YS7YdX>u8K?GIHIqCn8Z#VUiJ7nX_cKZKZb&U7g+Tj~sIS<+aJ_lFb3x6#9du
zedB8fpYx>NK&#;;CAp&@xqnLtSJAUtiU6#Ui4oi}M-A~_`DgalyTQ>gi95@-FS5Z~
zgHGz8TAB$@&%nHfu0mYozL72OR!<Wzvu^wv*ykluznBWP()0z>X384YFsH_&lPzcK
z+^9Z2imdfv7~;kQ!OZ^u<=retjxp2)<Chmx5tEhY&&hMw_aHGpx?k0_PzJob>7+%I
z%e8bV8e@(FC%|oG$$LU5GOOlH?6NK;5etqqVEtJ>_C-fuDv_30SsMH1ddSgoBBmqG
zAXTZ;SBEMdU#KimHV@;{fx7Vs%TKV#9>2#iK_WdQgl;(x*3n$UZ83{r;FCXX8YaJ8
zYe6u!)*<3&WPUCa$+7M#?agTDQUI5*BeY3x`hcaiV&TFkJocnr-n66k31;<Hi?52W
zUE<bYvAqEzv;*&(_jco=4uF+BFdGEkF;$cEK2J>A1$^c7(AD@un^Ief{x!jsDV@~<
zBkM++ndfUa^c&766FZs`L~Tp$?LfK?ixEp+J8^4wbM1I{PeTDfP1p~o>kIas1$Pda
z-Ai~7oUCl9=I!0qJ6QT>qqa;ti`!TG7$(hHPL&$wqmKQqj<HA@GG6A@(0cGK4}W}E
z0xPOtSSTmmZ(6NrjWaRle_cb>;ps+0OKOh0O27*HNY?VJ#fQk$c{lCTXF3zH`g6Hs
z<tEDM{!jFxV24*^x-^`sa4ZpVAehhQB5W2QJQ$9bkC@|FrG8@J`tA_FN5UZdR;%Rd
ugaa>r*!w8Db#YKWNAlMv3rd*r)B<cHF#)LzLZL#SAXw?Jz<OHFDoSd|rdfUf

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4168a178fb0c1d64404a2b7c5dda77b685735d02
GIT binary patch
literal 5760
zcmV-`7JuoB6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IU2bs*Z~
zX*faQSk_f#7(tCa3c*0u!TA(1ilZe)K-FAcR2v@9RNUL01febJkKQOmfJOkMD~iS<
zg}j$Ac(`);y|O-QUTGPr_{}%*7DnK56R^}LqQ-n1x25+Vd`+lDY_>Wh&faDwibk?W
zW0PU|b43}1W9&Z)Yvj+}^X-m9jNMk=Gi=!?D2C04BOiPJg3$37G7gvf4SS{sXuYmt
zlnvl}Xxv%NcfngNF6FPU{SXRgYR~|v_{7s4P~<@l<Mv?hV-S|;>L>@nDLgYN%@cjh
zGt;I?JBJ<*Cp7vss8+1ws<EJcBc)l;#kzyt@^f7gKWP<Bxl@ufH$h5@$z-nlw~q1a
zI6RecO{!Y@R!KZ@*fKXjcvI&iM7)!~v4qI>p@55OLbK@pf}|{*2fJvwt*M{i2=7Hl
ztm^+_br(8k@_s{8H-3}M%E%sN284QBD8y`rhlSP3eNq9@yVyBnKB`Bt*A#kzxBNf1
z5e(XMedy~>_Q}C21cj90e8~|D9M|jv4o9M{K}UxrBCrOrifxc>WCdi-;IQyb$`tjo
z48IGz^!o7%xYs=m9VY7A!Z3sab!H~q{v9Jy^tA>wHMhh!cwM%9|IVwa#eX4ufj-9}
zxBgC|s$)Qscvf>32!+^psNnqKE^Wj{y&`m&)I1}0V~O1OyDfs#u-scEfMSJpIFseJ
zx-b^&iU5b%u=c?Uee=qa-LnVT9#gpdk0w9P!!>4_F3Aa23a64*%Yu5*$JUyrrW^Xv
zAc5vtf^TS>D2Oy)8l`$6Yj7vAbDh?Gn<4Orvpjj~vt(3nD|^pVHBaeTCJ6ka{WHCp
zlmN)RzSzk2!n%^H8Lv2nRj>M>|5!|c67~<4_GldC!sH*?%f>nQCRVcbVr>rY;o+tf
zM6Sw-9W&`!3T2D{VG4cZ33Qm(M?ze8ME)^1vLCkDyFo8^Uu<4TpS}pws@m#_indAZ
znu0A&E~iDUBZuG9ji#0ClxB4qKOS&2)_cK&K{frufsM}{*u!c@t4$P6uM!0NHkW^x
zGC?EuN5-;08?H@{^e~Wnxxocb2#?xRd`GBWuG|--SMVNJ<G3rOR_V(z0g*e?+};-L
zpiGn(4^~|ItJXq3Q&3d~e9uWOVAPFZ{{FJB`U@rCd>PvFj#Tu*kd?wEVc|dd&a{F~
z!m2_lv;Wwb2%~5zDJKqfnXf?1_w>x)Wl`&8yHC(&+u(sV^)_%$u?%u)Db>16R~q4U
zMxv?TK-RndD7~&Y&ks!-s^M{lh#OKvr$HRwv2RRlMHrg07$?|s5NbSDh%@VT^UWxw
z?C1{`!2e{NjL|;2_cs7^A&0Gyb9TOkhC4ku>^$P5;)?86K5?^B^K)+3q_XF?neJ_n
zPeuS_i}x5pul+ecJ@tJ%gmpe@AKd6<A|EG&<_uR%B9)AB@`}TM3B&`C^9Wd)_HfJb
zfd2YH4*HXY?{Cyr$27_OQdFiG#;-874OGb32(#S+MK6`{B1GpWn|}}~LnulGsCvtt
zG2JGNs$7pSc7y)=@q<=B;Xu?c-qZ;Smo(0DybA9ybMJsIU(&Q|sMFcb-1|*CdL4%h
zU}~kby<5uA>Nz#rW&#QGl-AKX3c$2+8@*e5goaqu#`$&7Po`b`qd+z|Ui^j)=-g(%
ziNMytd3HbF0OkkQ8Jt@-E!J?t6R~Dsd9IToSAT+ywHPvlh`~?kPv217sRM5E*JW|Z
zp~}oN*sjf0!f2A$2iz@G%tl%Q!B<w(N3ipKdeFh>5e=o0YW&=3kB(&)c5WN%pZ88s
zT9)M)EGTu7Yl+AN00D|j$tEEUM9iJn$o~XqsBL=dWm4}6b))I`*H5#Gn}37b<C**s
zdsP)3-)2TC&R<e)y!Zd#DpK5RGqrGnrk4d}HlXFma)Wg`5=J~N6O2UXY69LAAdnQq
zMf5(kBWr6(@H2=F`B7ToC`?Rw@?h3EV@&`B8gS$A5D?JPh@Dt3KcPH;(=)RnX67yT
zF_-DQ#tsmsO$9Lw%Tr{PVO{q0<c-T76T~P`mi88ya<CNU<N0#N<8E%hs7}4F$LR5R
z1T7h&Umg~uD#vljbaT7(P)U1Xcl>Qz?H9deP7h>uiAosioXur)ZbR82>MfH5a^mEP
z6jrYm4Q<1gf?O27XgH7gN2U2aHR$1RoHH8NYUqdm=;sIko~?s;Ot<9bsYEf~0h8G$
z4rB{x%YV_@<N1YadsDnnO>KJs2ae}R4U&-46P%(!nmB@6GSS8)e1IehRs(iIc|Iy(
z^4}{_tb2wJu}YqoT;Ph$+9!%-Hh^-@N;*FpSsl<Xn1`@^Bw!`W;5~&oIVC~zAkAF5
zEI`JWnR(kWJ@FZY-IFtRg4VftfbJfa%mSPZa;^5MW)zQ1@fhNyLacAh+t!)`;Z1iZ
zl8CD)7>vPP^uY&Q8JO;WWAUOd`RcJs7VHr02q`38x?o*EkY#sspeR#okc>C#p!9uC
z&DhyUIp?o}M_)}XKpfFOdfb_fk}zQkoqcz)gTeO--y`;5jC{UbPY3F(nh7Vf`9*!*
z#5wPt1i>!-@ivS`y;R9RiyPsvX`*g$ni@PRZAg-{v!L*K(A|=@rp9%G(-TFq*%Qm9
z&U?hf3y0|Sik%BY3j3ocLi{81l75&oHvdvDH~ja_UcbhcOClR=73mwyD@3k|Q{pZ0
z%^zdRHB)qAe9O`{0oUWp>lKYOC`av0zGolui_A-q&VKF7;<oehl3nUu>~S&`bsF09
z-hP!1E4WljSYEY~%q67RJ;>8I{H9NV&4d7Yt%G5k-@J^XChjbg3Q_~h`;atpO7x+m
zV+e9?QLd3)rA70CPm<?GL_E|BvMzX_Ef?h^61{QYM)<9+!;XwMm66!zlA2w(vBAG;
zx7Kufft9z9&ormBg<Y?^-5)TEi1XO8Nru%mBb&H9qvx(^LRk{H=1i%aQqjouO!i2&
z$vMEpPh=m>J1&?3?1{SWJntN%w2e%o@SEr9tYiJtE%@}G;)xyeHqGU^iTLoUK@&|$
zgVQ>h)%%P3XzxkD2BKdD6;}J)vdbz3p2>=YFTt3JqDhaaM1gsoYzuC1)Mv-LqNCJQ
z&9;$aOTY7bOh`s1+8k!dH;Qkfb<W#}2bktX;>McoSb;r~3qT$$TM4GuoM6PoGHO_7
zN<RiQX%f~c47&u5th%V6e)Yv(1Z_TpLOqicli-+VQa3f1wdg%i&Dh5!f{0SUeZi_j
zwxx<bGt~Y24K542;Q-2ppRft)Pn^ftmZ3oTiBO8s+~&;Oive2<Kkt$Z$-y986Iphs
zIpyzRiGi(};Cc=NSXlY|xJqA+j}*SIQ%R&{vCy<);LMCNkk4ZI_p^b67(#0(zoX<w
zJcs%uH%JK~Q7+oRLTJYf%diox+%;sRnhV)hH`9yr<^KR3&6<R5vtNtoK^SbJdX3-6
z7(E#We350J#K9dE1joSM+Hy|Er~VlS8~0FhoX;#ENei?Bl#SN-a_s1$OZ;$b(*QvJ
zt<7<RDNt-O1=W;^-N>XW+Jj9Cjei31OvWZ1v&GH06UiMdI%Ww9Jt=>iOL&Pu63Wn1
zTx0Z5?kL#OW=EmvA+&(71SZw?Otkr8CitpGZ=sr>QA+#9fs>E9eqsm+=qCj`#c%Y$
zr_&cC52JhT?29OkVS%ldf+wpIG1w<gx+Q?B#7E=Y{XBb_+)Fchixk8a$IycNC34yn
zWgKg5E1*oa35O;%_C8wI_IXj$IB3hFoh4$?_a0$3Tx^(KB(wE=>@ADtoBHQ#4i%H<
z2=48j^e6M1D{26Y{9FqO{R7*Q&D7!=6=$VaXGX?xk@-=Pnfe25IfGe=a^}-A1<v?T
zB*qWDHf}E`sE5ly+wvu<+JeT4jzM2<1A->9I>5S%Aolk+M!q&-7Xi*kMjPayhxl2y
zi6jv?2x!=e8V~Rh8)vkLFLR=zZ{)l0PaVU_K%ED`iiQFBQDah*x)=CbqOf6tei?Rs
zj&(rGNuI4;6h}_o#2C+4yo}CD<8>3)&tSI0+C`5}`>suE?FA7Bq-N#dQ`L^e05FFM
zXwZ!=nW%!*Wf&hVhN;46!%_Px&AK399Rg9#Kg1710Y8*QU9aPR8?uHk``Q1yrC-VS
z$@uJ058z|o^3C@hzk}9ud(H6xS0*N@@N8*hXb)S!^j#_MYTN#zSaE3)ll8fy&g=5v
zoO!^$!$_ki%K>-Y%onTg4&`z8)0^-_N%Ni3a=nyvUDKLh2HH8!AP4D?e~Z}m{EpW7
zQoA$Ltnvh4P3Z}#%E-K^jdYvI%b4vK6zlBJ{K#rREYb>f%h_9ivrHuEZVYBN8OB<+
z1Bk&Qd=AXgv(kA52#dGuGO;TJl1SMccb-RNmCdD{h=DEXtL=wktZy=e8eMzn9%lZh
z5g;gvdaMCA1B)$*nJte;is=RSoE;dqLA&nifR9t{@+uZYiehmnoaHWxVhm~lwFQc=
zJt@o9Y+FarkS!GJ){8G1wVgI%d7j4DGwkxf7j#5)a~}Lmchn(ljY`=jDY&F;!4nY^
z#pZ6P(jHGs9*kgY-f}MJA>PtQaEj0P*f-xAn|v5&yFg}C;mov1^ibF-Ma{>^7i78`
z{S+X_OLcJK&;QUG468mYjeC{m9`BWrcd?vhnlp~iJFua~I@vH_1v1R5nz|QS8EJZY
z<JyY23C1bGcSzT2Ea2~MiG`ifvdS<Fnr2wUT7(Uv|B5GS0kWPNzVUz+Z%BmWsvZK&
zdZ;0cNxzI(i&7T|JE_bc|2J;l@*hnG=#Q#oF9WYzkPAKI{h6>>lIq+uCfg?VeDX~f
z5RyE1w*D7hF$W}Up@SUa`Zfl%k|E$h-;_5x3n1R~t#{(ta#w(?rQZnpS(s~@CjHI{
zj0@K?{2^!dfsE53H<k&x`1P>At(UvHMa@8r4SGdk9_8EQ_tZQTgs7LcYYjSH;*t`(
zAhcXbzsWaJ;(=E_DdC))+7Cv^if94U@02sk#<u9<!wZ3q2wHDy@mTB((%p2*HRkZB
zO>^NgM|tP&H>9T}=i-+`8DsZ?=9M8$e3bET1mckY4y5D>E-<QozMxc|P}@6^-=j6{
zPJ-&1OG23)TGoP`qMOoD6bshY6&DZ?jH4bOQLbTmuIL3x@FFmS8YxY;Ha47(9raQR
zHw-1jokPVZ2D6ExKak~V7rLX15ZJtpsp^j|+llK6EUw0(bTRxi^d3FsEu$Rq1mF<^
zU5*zKqb>jFAH(Z|4JH1Y%a-HE@Aj5_64q3LEdm0nDi3+#JDTAt!h?Biz@%kh02#=9
z=_ZLlhTbwGRrHtD?H5;1TZ~*jnF|BOO{%+6IGF4OAnj<<hz6soihvmwy=EQ{`Ob1$
zwHKq-_FFt3OE_UyZ`<F&_Um7^<`t;$10#^MxTJL09+qCR0#-d}5RJOB&cy>8Sr(Dp
zeeejmd~pxF_pf8k$(x+o-`jbGnPfctq%<530yy;j4p#JApzn^nO9y$;cW$>X9p#^F
z85@Qa7qd#yA5vj3QfU_k5sd%Ty&`r6p1niID$gkVBz_5DSB81jWLF8L+ehqs%{c}c
zv;JmnH@S7VMK$+wthuVw+uOQw3VtftmDk<P6!i?9#Sh+8xK{txl*q_1CIsBbzUByw
z!21y>MhLa>=nYjt1TjCl9@e-Jz?7D4kgHBuPx>+Z*)sfW>slClb*Mc9{rSxl<>z9n
z&?7y=-{NIpl6F))(VXdO;I2Z!&a!G@f2M*GQt**sqLuvHL6yXugp&YGO?+Z>qQDN>
zhpI0ig8a{JMeI?_UAfab@19%ou#*zq2-f(gCK9^7XHF@7PGAD#Ci|q6w}M&1Z`ycS
zLhjFIlP0ewA$vRvyy7(!GL-bfq?kB4hk8~=T><t&21oON{hav6NKtukn0!AYd~;rX
z80c(;23g2n3OvLYOnom|s*kG12Lx{0;uasH1ao~68I!-$-Eai(U81y{_vmg&>5CSW
z0NWM6|LLZVtridq`c16?=lF*u2L~q%u2jnS^=ZDP+#ITvUe4@qb(}CI(ARHzy-R>6
zjV=ugWL#o37I{($P({<-abM~fgv9=I*`U`?EJ-xm=c9YQ)|vsm&99Jvv{amskh&u_
zw3dFh_0PY&_E$IdqfLOcqZJFmWPTebL~QrhLvOo=cWi<?bcSPWgQ?#0ueE7nxzWQ~
z;&TAk8&KXW8woR5b}_(Unu5$>DmIz)abA_zwk;L1iqUZe*y#6>yv1`g()PuferzB!
y3oc)WXVZ+1V`^+X89D#J;ZK9{VomkwXT5PX#32%zf@_wn6#6X4X^U_}IWA&KqDp=M

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_base.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..18402d1d9be476e68f893baddb225a11305b1a46
GIT binary patch
literal 4280
zcmV;p5J&He6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IVJ@a|6U
z%q^Kj>-?UPxrfh5IC%Z4J3W#4ILSxhxyQ`Kl?V1hIzt_KXOR{xXpmG^b61v#n75FJ
zVBMZ-0oApqSm{lmKH%nQmehWk!iycG7EJ{-55+|pW0tz6bMN?vkl_d<8c|LqsjS_m
z42RU)^k1sfZ+hzw6o;NPKg_h&q|P}vIk|hw{i1KP*^d@^JZ-W}4K7W9a^+%?Fk^uM
z0~DmqsTNcGmmVU?|M+^gtAg@eptu;MoaRUcVvnnG>CpTc@C*!8BN&^??}MVD!+`-q
zt$*=W(Kjx0ygi=Vs77y+MwP$Oh=G(8<=Ln8Ol0(fd-sSA41n$R+(>dLI{v=C$2cUr
zIH>JD&b$&q_VDs_P0gVxmPvK`iSYBT&+`gL$6IceYr*$>^lxZLpCy5`R^LPce}h@#
zaA?rvUd7SC+NW~QeDCpUZ0ULGoNw<*;oB3!8%@p||38vRfj&#4kSFOF!Z!AmsYs<G
zK$uTq>U#DIA^h(ac8l_^#SY@<H0{a2w#A0}i;*o?+b;z-gL7QgMdx}+3vpvefaUH2
zw}Q%1h;!3a;~D<HJla4jC=C~J#}b&%&#;CC9I_#!+Z;8sPD=Wt6a;o?s}<Hi@$V=X
z<t9cvNaJSBijJr@fmNA7W^ub4)CuDU#lC;7<VMAbp37*>nGJNwUNnYtI0-i^d3`p@
z4fi0qi`drNjrAUC7hnCH4qDKXm)MY?#XI%8cHlx9aJZRST%Wi*T$_cJ;{)JaOhHeG
z+c8ludaekUPgH;76v)F_V(;w&+eV_o^qqREhrQbjEc5GD6Ixw{-U**t=blCVmcGUa
z{GxgB97pN@i#qPCo^$uvRLIub8?%BOrtXhZdZ}EcZQQBu2vHCI_O>`>8R0a%>Vc?(
z?t06h@V42XKsLTYG-~d+mp`$XIW6-);AdixcCh4pu(fBC*nEL_VSHDdfiL4K-a&3=
zO|{*@e@6-mY{JL!s#4;Aw3sZ8rp4-Clri)CunS5p4X0OafWg6x6qn@L(rt!iG`kkD
zWzBo|0RIn?dSsKK$qL^d;+_Y46YZUWj;1(;?;=aMb4$s+t(1re_*y;LZ^4TG-7ZDi
ztTw6n9kvleRW|s2{~&8WOmabQfCEW@@u<__fQxZ?i8<(NK!IP5Mq)2WzJm5?GunRe
zF<S9O;_ER$InW;AU(jA_yzE!v%J;S=COKUU&=SGPLAkJ8Q?<lrXl^$eZ$(!3Nf6f2
z4SiU&%q_}%qiOgAa8RuKmO}&U^$CWF-PF$?0rT=zVl%NVM(n}ArzYJa>F5KoEYQE8
zBJB_qIu0mfhj@@8p~?Dd>%ktr0CPzP?`pmFN_af}d0Amm2Nd>K7zbN$stB?To8<Tj
z{rGw7xDJXj$xy_nczB0w>BczzkIpf>)qPsF{<{*)2{3Omkv?fZ)t~xYpN!}+w4<gA
z+7yugm$jmO06W%Da1f#l2BZT1GwpDBkKgP6b3g695fXN#SRVD|CBVIlFicjQML(*H
z@B-xG<zku^91WR#6P>~I1R-#m5PY~-q&=z(uxCfEGO{EE8y~IZN==~!JqJT2c!Q@o
zYrGAev3}vJJJvPk;I!|16Yhp=3LRT1P^lU*IP;9A2`Bzi-0JN{k)M1Z9M?kT$y0Oa
z9kHlMC-+=J)2soJfqh?EiN9WzJUbUqW3z1AE@S<)K|T?K6-25OhMC^0Ig=C>A<t43
zS!oF>mtYCRdn}eii(Auo4&$qaNXBhPriB(ky2?zb=36*m<Gn))B}s|q^CXOE!iad1
zbSR`x;A%R?A|hCVeL~L@DE8DG7}o^?P5q)T#IEOKtz%?r5Cja!jDa`4j+k|XioF1M
z(>x(dSEoy(S(EQ<iTLx&7Jo9)#hlqi2COK1VfOM%bMGH)Jw~KQm7ADzjAWrh-GH5z
zRQHoI@F=0ZYR;BsdepJO5l?f!=8?+>EF6Ycvzf*`W|q?v)D<#pQ~gxcGWQF{LMORG
z17u9xQ`nWLE()v?%HlR}3HVYig}wi<AkBcDI^zf(u!S^*iw&-HehJXTH(YMqy)Vv6
zVOC-ru~BWoM@n>P%ggf0ktFx9Il1P?{2CGkmspYG{~%%<?w*~nKut0%D>Cm%Mc~>M
zL_(aO`W1D+SFKcznc*4E+`Qdcn?p+kXT-Ods`{#>K77%1Nl`4C!+r?&*Z8XJpe_JY
z9-~`%OWNP9UrXIsh{#h;(OR5w)?Vnm{Lh=B|Hf4l&3-q)&QP)y>;}$O2q<U~-{;7y
zmHa|Z6+&u*ujBJ4=1B<EAfU!#-{Avzuez9D3)<*oOg9DUiaGiVvmy;YH_ft6*^SJ~
z(oLF~vw?9Sx$a(qEz~)z8?jvd6km7IK(_P@X-6$NRXjclA2Ee7^`)~caia(AKI)HG
zIrLKBSdq$xk$pKQD%Rns5Wm+F(XM>LYc=<O$$sh74!6;Y6@{boftJK?t?vsbbyx*S
z*v%q6v;d=L8Y#3TV^i%AGPywtzfg?9d9?KmwVuU$8=FGUEN+c7+KUb%-A_)CQ-n;K
zf&+`h87lccbT1ER%SRs(UXk%K@i$CD!2*k{D~ifBei+8Qc*KGxC!{&1o_)4#>yBK&
z?*WKK!7PT7G95ReXyNC2#Z)@>|0$_AJP~<zUWdSCN;(@nwHQon_5d~sb5L{Vlt;vs
z?N3>l?F^lDKsO7E`=%6!nX%h+efkD(G1^OU$hsX{s5lUqfv&>NP+hz?ZAY4*+-6!^
z6&<!(eyK>n3uMCFB%a1{1^KEGF95M~v5G5I<y|ml{vp2VULsb6i7xP6ycK6DgUc%}
z>@r`+iU23kDsDfyHS`keglTy50v0AQ%(SDBK50Ch;%z^wrd^0~HG8sd_ST<+f`elm
z_TjSccqz}ZIrqrr;5P$4d+^B-+Q{Rj=NANCLRvg-7L5wiLYgc0!XP?6I&-HB6S7FE
z6Ngt0_we&1`8J$1j~YkMoM$cAx3~j7D0$#$^)7piSIa>7*K19UzjLDQV9koHk_&uS
zt^fj3+QC6q`x>_<P+4@hUGZmhrYt=S&WEOAwK*s2$`$~NlEgAn(HYMQK&Umi(;9-h
za<8hq#O3&oW@9q;@`TH-=t<bLst?~r2ba^C((1c+7F?k(A2k`GVYcgB)B_%2e95(B
z|Le37(%3z2&s<VfiZ?fTPr8tGkjiY6|8xlU?)95iz6HOJ9NWc0U>^6`Sh9^bG1^uN
z7niO@lV2MV9>K;cm{LpLUy$W&!?Rn!1nGskDWBzR@|w#?j@xjwPteazN@f$D?$oob
zo|ZEE<dMB#=Fs&XoCoOWVW<EDDh$z1zx$(%dZ?SWNXGYIZ8nWP-se-MeHH(bgSMN{
z+1^=q(buJazB-NjGun0KvbB9?|G6-p?lBfu+#VYMXG>sbZB)#~z3kn<q>p1gyL@?{
zE4VkC&}K-Ke)&Dfu16gzd;AX2z^#T#V{*e*q_UasJt7z|qb59PUAIdBZctcPqhp!K
zhdmH<E1`{Du$w>|QpQWC8HK~WU+^Q0PS#EY4Zp-O?4Xct){ypm#1aD0xE)(q5IomC
zh)SC^sJJ?QvJha8H9ti7%NGzyAd!$nE`QkWYl+sJFbXbFi&EMo-@7S=?N1eoqd`CX
zhnE1gjQ*I!_v)S2zsJx&3$iyisR+1|ald*k2NqypbSs?0qBsCwK^ayt9v8_Jo{F>H
zva{+UQ~<l9N)jeMv~cK{|3Ql2Cw$AT$)~ArhK=f^TECbEAhstao2a1W`x1kj5+b9u
z#ua})X@5d^{xJPaI&+oI&XaJ$rZaHj#jhlL4t9~Y<YgX$no=ic4p7x5z+@}Y+|<$%
z{=;d;Dt!=&48G*WWqYxPvM0Bz-J1^**|6e9?f1bj^EF1t?vC2I--^|&6Jf>lf+c__
zTZ1Jt@*aJqGIDXEXmxokSs?cC+OZYK2KLvee!_;PhljQN4HUmn{kMP9=vLt#!{B~3
zAd2GN#8PY>?iPSGrr+2I*aWY_)OKDUCiNa+ryK*==5HYx^WzjA+)-@RD=6Lii2=$g
z2?!Q^inxyaLd;kk*qe&au2^`W{@4Jr$h3)pf1KJB!zxiiJBdGX^lw~aBEh<|f?4zT
zE~nPM8|5vcnYsSIEo<gbFCN=Jz7T^pxvbd?hWXe?S6-;#ir<)+?7uRxIP88qi+zh2
ziq#6Pfg|jJTi3l|zaUrkOh*8KhgRpJ^~IMb$f<)Gb}bCgH|B7SJmw0x5<7X#i9t(~
zA5x`k7T~;(N~^rvfqF%B{POWL=icOLa=t{Qx(?45?(kO=PUDhTL&d>O?KV0ky=JE2
a)~{c$pxhRIh*{XoY0HD9le_s#3kObt8)NnW

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv
new file mode 100644
index 0000000000000000000000000000000000000000..e3bf8e57c8273bf959f1953abd00148f6a2c7d9e
GIT binary patch
literal 5256
zcmV;36nE>36Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}>;ei8mq`m3O!dKv_~T8IVJ@a|6U
z%q^Kj>-?UPxrfh5IC%Z4J3W#4ILSxhxyQ`Kl?V1hIzt^|%oUf-;_wk2L(N1Z*KL3*
zRy6m9%D)yo#<`?Esge|P`$%<d`z_w>l&LIfzf8c1nqi0Bu~M&X9dkfRn|eyGfHxTv
z>IM3x1sTgWUW6NH#K_=}&1k$C?UE2|Kv`S}>pazc!io_{zR@i>ox>zEBp!}ebV!Zc
zz<5kxxIJdS7ox&dR|VQke?{|{jV|Ktb}cIqKSkJfUAh3vxtWb1R`=LdxJ!@?Cxd;k
z*<vsR`{g5(wJYGG1Wz=1ZRVC$0VT{v9uHoRwwTJENEXPh4*APs5mu}?`OjxOsKsUh
zMxo4U#aV+5uLbB=&6m&Pi@bB1!l|g>m}5NmX+H(*kA&dcx*#a1Pyj<8XztO<zh{NN
z_bn#z+sARUlN#*$DxHQom)}yRVnR*r;1tSAm)`GINp}0Dp{`|QhXBJCN7DGb&5-Bp
zY}`>~a&5y<kkndnjVrMK+D8|aOJt&pfoP4I_EP-Py&e$??q23sZy%hUzDW5-OS{v8
z-O`e}E`dg>SsfI^!MNhT<%h7F^mG`iUt&u@GQ-fgnm-47ZPimj6m-LyWj;N4cK=3G
zx-7skx~>JCNA28U<YY`&>M6?rHPgs_-r<g&R|+sN&T-Yy>HTR6?MXcIMLt&fo=!=h
zpQ1K%3V!{3Iss!Qf?=|vJV9(<kUIt9AMxyXOfFx2c-Gt`$312!%-lg&HT{$^z&FnG
zFu<b!9l_MdMi`O*s1hzIh>H&u@cucb5f2)i8&ZW`I6F~*15u%fq#R(b$4zkLYQ_K{
z$Co3_i9k67V~5r>ig=7r^R<~vHiBQ#1uFI^L2E&FMLbb{CZ$6?u{VZQis*tCQ+^Oj
zkTv*^wE+tQ11q<hZQpdMN6a~HR<?y!jwD9LWGI@Y^GM`}?+i!!)rlBGeE-_)&er*=
zlFYZ7%NTwa*bgoBPO3GamIAD3SK}5UIb|2p#_wI0T^t2Lfjr;TAbZyB`u!dq@h~An
ziG?F?XrlNBD6)&u7xPI@x=fo5T{s#in7_`)C>tNfUmQqa4d;7|%Ftqvnm6?sgC)M=
zk)wXS-p*eDO`ETizeBU-CsCz9l4rDht6|0}Zw2^;$Xy*lgz?7Y()?KSyyYYzyee;H
z=T?it8xG4n=t8P|t@}!&=)*XDnxsX{RPag@8XdXMB9;f(uu2?3Wl4X@R!&MF!(8V%
zNCIzeO@@n+t7DOpr;yHkm%QqR&`Wy)ddF%*VXIC*xNl7c2%T6Aq0Hn0aR*SgLPBnC
z?~+XN5l8hvY!q+9Q2U{>0Q^Aaa=|7mi|2h{VWeRS*^};4FwdV(p$8Zdra|00`b~so
z>&ku+J!Jw-C5Z@SLZuCJ({u7<zix8y+s;D<-IwV&xmvo6z(n8ora(`?Lu-tq*WSzU
zs{iyf(wef3*2sLZ%yo#G;->gidfqc#GS1rJOh8zq_Pb&}x11kf-b6bbrbfoYh}S(^
zO*cD|gff9eb__PR!>7TY{2JiAL(n)tZz4tdpZS2pWh9^sk|=*~FZ%MHXkk^X%=X(*
z>JP$p^%kGhf*5z%NVk||8+;YTkzH%pNW0UTflRpX8x;owga{J<$F&)f_Kc*FM7+LX
zzFd=fBiaagcy?Cc$UWd?Ixp^hUMsF>KDugKQ<>^C<)1HiX-9fex8PkF>47ydTxrn*
zMgNmhd@uazk|u=_*R(3bK^8m@n)=w0&=)W+V?08PRsp0PvX}^~89yz$<Gs)7_EeMV
z`K<Xt^-K>g!JoY{O=dpj4Wc8prB!E)^Cb$iTs|NQG<LFB2^k;vJTWO_SuJIs<rJw#
zzbe%or}L>|vZs<4zn1J3!2P@J+5uS9F_8{2ND%fp@UR|c?+iR++gRNDJ0UPy>AiRT
z3At_!YZA=oRJ+8u6K^BUp5#UF@Kfn=d;m01D|0SbQEk!PO`4i-`QRTrDzpYpv`+E!
zp8Z5WT=N8#4wTXXN%WxGIBZ(*n5;sJB?=_pG8`tTUw6aozyE!pmx@GLli`vYB%D7*
z@~m1jrGz)F?fO)8qd_KXA=CuF(GT#4n#Ucc*$?YMYg@T>-9GQwTK+LGJ~G+bhQMxb
z-Kl{%9nfu57hI&evC&e4YW~}4xJu=Y%!!t<iArBZTcm;~pgYwJUGrU{5G7*b>V8)G
z%HxtTC&6AxPj?3J-EO|oUUZR<j(0NiYx6J@F$$cA8aAVmvk*z3P(|`plEVnzqT$P+
zGU*Z>87FuXv~=I!Im61<j2h*vJEkZc?l;ja(+=-Zc`tjUeF}@!V&qxm2J3pOK`|>g
zLGz}y@2DN7?X;H0Zqeq2H(cO++#Oo5Bp=Vf7rY2fY~S~25yD*g*ZZ)lllJ|`MPU~?
zi|Mblnpp|jQz2n!<KU2K4GSL=U(8<xp~`%xRXon7ZzoGzjZAwH4nw|ZV3z*-oU>Jc
z->o%(*!jO5DV}H-$+K~7Vcy=W3eU`XJ%2&x80^!d2Ffdj*GyH0!Md?0p~5B_f?5(M
z>MyIS6n@N2d3$8zR8%U56aV{ThI$qzSYgl3Za4PxtS2G57>(R6iqDzT%2S~c0IW^a
zZ0bUmQkMe~YAMO>851w=G^9ub?d-Laxi#qF@nJ3p{9Z=So^7vqI%VV_a!53J84g5^
zJAg@BR`L5B<2uA5ibQ1?o!_)ZH;qOLdr7>DBA;l|&pT&bONmb-I&>6sq#ro;PZQR{
zuRIA_?vK$|qGaP1NpyGh)F{*tdKkRuX%aLYTfQ7Cg|A8ols@qShcmK&g9X-v|9puF
z3-`2TwlU&M=&nleg6`oe-c`qzB81svs5fX6fOJmdr0OrGk&9m+ZB4&|@e>{uT!{Uo
z*L_X>x0QUv+U;I(ph<OxJx6Cs5F!hsrXl(bah#_WhR7q<L(&z`k3xIR_<&(f+Jmh|
znu`^H9^T{OY!PR&Si}UIaNcyd7XNU_Mxe2)%^+v5=IS0Fe&r=?^kKJa##s0ex+NZc
zfWqr>;#`F)SoXyv1qt`36M*Q=z7p98J^fs`HkMc4?2V4aQi9t@$|q6lc}|8R291@9
zaG3%Y1R%hwudS025~O|V16(u7Go6<_2e=V;-^l4TG?1qBuEO?@jjl}B4lzrIv%rqV
z!F>(Kr`8N-k5|gjvG#~dKA%*2X?sFk(os)3hTg6^0JN$n)+vgIhxq4vn7@uVhIOgD
zu(oJ^hgxXgpItZ<p9Qo#Q~j#yBHoE8{^57B1|ckbQ1~22mY8l}H|Ftt5#9)~c+cA4
zHW-k)5dUozo)w^jL@H27l_sYYI>t$#_oN&icVcNR{W)r-AUnxB<??O!!uyJJbC@dO
z2jyte;+hxfRj4d<(_?^#5H<=)-fhFa?$XGo`ZROFkR_QRF5}ppH`N2#Y{?twh7`Tm
zENVu`hGQmHT;*5VZ_}|$9B;xoyi2tgd2nKpRfGw|2EJ}|e?64U<%kF7Ac5r_xz8xE
z4DMwX7s+!ZifsiMC3H)InQ1MvJhL}5?E71rP(fb``nAt3ME1)jFi@F+GdWtzDT|{-
z!|HtCE~^g=N-v+rD7Di!R^AFEY5eifOuCKAcd&QtaMsL;%w0xSF~YJ%0JOt$EUKX#
z#Rd-{Okbnu!DSAWlb!!Y_R>6vwD1tRSvpX4>18#na{a%~EX=;Hv$}jv8xqa6&X`4J
zORzfT^H)X)L>h_d?6IsOASdUW`{WSxP696|Ag1k^>PB>l{3j)YJB%vt&3s^U)!clf
zibFX%6J0d7X6$=<s|g*ao$R*v<z#we?gzA##=jxMNc;LC)8A?N$evCG($JVk$+}PX
z&ncYaTl3(xCh6X;X&k#q$ZmUkNoj!bWkT2cR~8Gp4YnLR%AL#p4MaM|^rwg;=dc0A
z5SUQ?bnD{!Q`YMS>7sNG_?O&iOi#maaF56G+p)0}B)XnfNyC=mJE`{a0BT#%o|K$I
zwD^5Ghi`S>kPhVuIsoQY`K5+;{iZbHTk*QO52k~H@n8_IWE6bLL6)djkD~qFb(P_d
za#g$fYXZ{e(D#3fwv)K`sWj9W!9~y62$8%sSaO+*6OOt%SyREg<W26!b6M0__QRmn
zX$7-KQ%ZX}7-0t?6DCXu<)ouS3s|mxB*>5E_Q?JhRLOWRH}|D@$*L4&7J0pe!a4fV
zvN)Eel5aS+j5Hw%aI-`{@;t_50-2ylL&YgkIYs0Bp_dz7++d&0I)wJ29izoFfgmDe
zIUQvJn}bExMZ$a!*}Ew%{_HemjQWbJ&iXDrsYsuIDZ78l0!o0A6eA60itE;4TKtoL
zAa|`bWFk9{uMy-z{=oXMBz2bmS!_L@)D!XlT`K_|mC=8YbkR(X?fDydzmp2#(j3+_
zY(k6Yy?xFQgVmcu(Kt|b%FG5JRB0~L5I0DN+RZtE6I4wQrWY-pj2a$`;UFP2^IZGF
z*{*Wp1H!}n4vHkf<b4hzqf4&bM0t7LR_R4u5ghxgI-c#dzaYE$WXrp=U)xG~ha9u+
zb1bI&>Z*{b6LCLmm0F^Hf&tQTri*cS`JHre{=xwp7@~thsS$OwXuMxmzez$vuN2}U
zRnwDDp{Y5P@v-Bzi(`dHyrie8MupWq^ydb`%;j&`Oi8m#1;bdM1;jPnV#Jy!NfXTn
z83U?t96>Ut)#tI>M&FQrtGZ_f_Q=+eqXS9fTeGI6j?c5K5K|~P?yv>tqUHJ_2xpjd
zP2(o3Xgp=NDkT;YI=`W^lR7uIAsd@fd3NjJj4m8%7QCTZyIklx<)B$m_bEA`Q@myD
zFq9=-9kG~l|5>u_;+?Ar5k2`P6v^&3#8oiPsIZs^4(4{d9I0L45&1757VR`|YHy3+
zofW$`XL#~ybQVFl+-;72+T2RPByP{2SZ-y6>TuHO*3F~q5PuSbq-^8s$4+gchlMR@
zy)HNP^j{G)q}RcwGr6--GP6W+mk*@zu_x^k>HY()$c0T+T{r8xZ*!^ygy?`4zwhd!
zCgKKugP1=yrK%6j73f!q$VF4z{jQsJ*eKes`R4Q<$1e=kXb6p7UJEFx$?sZQ=;L;A
zieHn{)mMBJZ%}3qF!{fTMSIh>+$!xE=A|%!LjXgDwof_!X!scee>t)5wl3K}t}{AP
zRFK>FRUB$gpOTOI`y1~$g>YkKA&B&a8RgX+vX+--dN*Og`QHl6{`9_JiuIj2C`u%!
z_Wi0aNsOtL#Kfl?9_M0e=R1R%+fjJQ%8AHr;O9X^v#duq7`E>D+i&dIh)ISDwfuQ3
z2FL7<QbJQmoy_G%``e~vgS8xlyPf1fR&Wv!C}yukiN_|WGdTH!ae$P_y>C&gA)2(<
zNl<9>Rbi`+5ZsgrW_Ai}+CBuMfbT(n*N3G4;M|ZhUM=0qbju14RT_WquD`sQw_aM*
z@r?7K)Xwsp^I&5=oQ~LLNdG}W(cMO;xDQP3GrX76+WeYSejw1QQ_|s7QTV#2(g8_D
zkUfR?Qo`*=DBVg$=1;fys+<VFUe&!&)l`G>u#P#pu`MB8X3a1xNkymw$l6v>PVj(9
z9GKlL$Gp6cH%XZXfwY3OkbP!Q2(QH3f|`JoE^JTfzWh=VO~`Wat)o}CeGyfwjsciY
Ozs8MES0)YZKH|3Qc}m^@

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map.v
new file mode 100644
index 0000000000000000000000000000000000000000..8e3ff41ddeb3b530298d7f2cf1fcba07247fd040
GIT binary patch
literal 98272
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl?M$34HY
zkb;M8aI>udS=rmWuq`o+Q`nOm`O#yYwNxU57JEIxG<5qj0sChFP9NjNiGbLNJxp}N
z&9QcNIwb3$Pr?xIQa<(sQZ_w5`i|g1OTM0zjuv{p+Jfn~3^{?fGg}cg-Au);W_e8n
zwieLIHs{(Trf(oECIj$*Alq+d#g>4BBuZ*O2LfMvkV)Xea-djG$WGZg2)n1ALB6tQ
zMVr1?fc4%L2KU)7`v~v9DN43hjZXlz^uX9A8s7IIFb(`F@bm0n6G>mc#q(jezTzhF
zH^J0-5b`7GbJ@|Xn7HlRzF8b@l_1f2cALDc6aa3tq&8fn&U;0GQbP>onUB0SVoC}a
zy0g88aeQvs#IxH0Xp*fpO=o(8i!1Dan6%vPLmCM4;H9QoK;rXaDx?@07Byy1g#ES9
zF#W~ivfG<Vl=Y7}kP=%LWi4bPUE7-wIj$3nnC79gNE0uPIZlbRvteT7S=}(4?LY~f
zqzjW}1CQL>p^0v=15LKZ%?|+iusyKYjsX+?6)_H-0KiD8tDdCH<qeHt9g4axKNJ4w
zF5~Kqjt^R}=&e$W6D*<IRd?dI-V7$ne}&DQP`N!G$xl%eTK0^X*k;$nFF{dV#O2*D
zxDy|A14&K;p^9=`Oew^doB85b0ktRuS#tTwbg8QV`_I3o#)ACz<e>^mdLmFGhdYHJ
z0{cmB<hPd+`k&^K{OstU`5b!$s7cV|5$&*~0X(R-+li<{MOCWmTnhplY6$I>6bb@>
zGOoF?0VIl759c<;g+eY22=00$Tn5Dpn9Yhxx{}CuRLb75480T!gV;{Xh2#D9{6KH)
zc^Vl|Zlz(VdErnH`8qwuB;NFF!dm()1~-&I4`iWsg!vBnFPYpUnvY_jsL>RWV$#yH
z2|x#5sFl5kAPgdAWHq7}nU~6qh%pPM`kzOrje<SM@CK>VfGB1$mCs{aw=Gzokp-Q*
z>S)-!-mpAtNx@KXsyS9~l`du^BGJMYn4P#{z+FKIwHE7xU)(nLE~$S(@s?*o_KDR6
zb%x<;I?gm!(Ti-M5IEZ4MD;+T%uADlNZ@@2u?I)|ZnW&9jJC_K#&ky-|69g=UuN<a
zsdBDdYr;(M1t7_TbI~%#*^ofc0Ln(B2Gx)1Xsw>&gRii4eL|ps%WaKIb78JSgX!xH
z9Wa*FZ`Q_8zufhWT4<;J6~>6H@8w6kRSSY6W=rX$T6py`0yJU7L0~BeqFf$b%)=zu
zhX<9oLAj&F;3Q;y<x$JhYi|Az#l{SFRA~&2ul(w+ywyjF<lL|A>KrghT{o^*1x1$k
ze#{#6IW*o>jt|{lxVs7PNDWw(dM}?x8B5E-S)RL;mAg^BAy+?~VUpof^QT@{NI0-~
z#AeO>7AOX;4q*F=+FhFAc=rX3qq6uHpPj--1S$adNNK2xNvFTV1Hm1^PPOUXlT_-L
z8pR|;Vy=JXmQV{Ol$}4RX0|@w$HohUD>uyLQe}av#XOcR)WCLzAjjWH7qtv-K!0T*
z2qV6zn%>7nYqZL5ccS{Pyr^S#GRX=p<BlK;kX(s>oUZz!5Hlyb3!TluRGV*wJeYyA
z3)JX`YUO4S-<h6cB7&Umt31$Oe9B5dPEHEQLy;`BmWEVrb8UMZBwG~Q9NBtM1YIDr
z2zM3A#DCTb!!5Q9?2_OE1=%5yC9x<O*{@T#6LRmCPr%iY*naIVg=w=HQ6oDpq$zL(
zv&d3)X9KJDg*}<%XmpQ$(lXPT9ibjSlc!au46Tn``c3$d^2*zLHVz;GqkO%Q7&kL2
zowi5e(GtA2N_(YJ*axBm|7@&aA!1|I(2cY8GYNEAUv52TobA4OKHoyjRcF@t1R9D)
zURaGTrVFq4ijBw7CLXZwgvXy}J-y<1aQ=%{SiQxrsp@;l&}wGCfs5#t%e5g$9XtDD
ze}7r1n^omaY>Ebzw<|U;Zo%ZnlBQ6I_EoR|BQ*KkNMlW{w2Djaap>^Psau>)qVd84
zAh`VZIEPGNLG;y@FwgYN(vfCdlJ6cbEl!9<DUv;Bg`6DFS_#31#$m~^yxw&eiSGi)
z-Vt0(R^jyz-HDoj8~g!52*1t%JWwv@6q;9Y7oi+f3+ng?7ATRH!F)6ZvSq4}8Sz+~
za|dDZxg2l|<r{4lv?lvuM{XNMdPR{X4u6!E3qs86I+6p{wKO4hJS+!<$awW!14x+9
z*<4c0RhaqL5yEC8`UbHMAT#T+PHu1iw`{Hg73{i`p2>P)*JtOoK+;@lv@xDQD-A(B
z0k^3p{)-z3WqV1DO%3n=QL)&`TQeERnHgDEB7YgJYXrb9zB>!4lg4UV{!;xXM8W^d
z)OlQ2Yc_+YS#~$yF>8JhZ5IbgNHBczFV*fBFm%$|O0v}Y`Rf{?nPc;oEfQJfVtJU6
zAfC}*67!!grr*bbZgepQ@5aKKydht)pfsVM^fOIbBHbhAdRNp`PCP>=B&We>j+AcF
zVzZz~;)a&JWLaZ!fLk`{9QdfAfmNniycqRcd6klPq{#<XwV)_|TkV6dwaS|hKN`}O
zFU5`@TfyE8Y?E78wnFYaF4x!ejF|;(Xsy)_72nFz8`v;+Dt2P1vAHM_`kWF3PcKGu
zt7(fUF35sbBTyIbg3(6pzwkS?yxyS?R3gIQl5EBbF_qId8_gZwp=C(z&zJ8hQD{q)
z39~-nta0`W{<6Cm_GNO-rPXEVxqS9`<puT^yK18KQ5WupReHSUmVGY{V0u%AbM*5X
zBOtpQ3!Mit;R$J3i}%;<XcFxns6Yv9%z;B1>cysPNNj;q!K?gwQGB5T>;q2n3gRtA
z4?RL|bYBoO50;f8ekCG86vX(PmZWs3fPo`nnyc$Fm=z=hVjC}YCQ_#}Sk)BpjS1S~
zOs8jOi%o(W!4M^Lk$UoByk@cZc`Az{7?2+lg+an&CY8<<(HtB+iT$a^$gr8ktXzQK
z#dBf1-<MHn4(VMAT&t#@?wJ44d-u8(qvbUTbnvu?C$7RfWeMz*xY`5|P;@<N&+DVN
z4-e-->)I`ha4YRC(KM?t5F>zIc1|8iTrcMGI#*B*;C;^_rn8Sc*?YZHon+e&#W2Yi
z7}59LK6eRT!Aq+E94US>6xp>i2`>gd{Q(#fZ78a9QJ_ep7*heZ8GiMRdXokp1{a6E
z=bec6dvpx}06_W-OlfJxOCRb&`5wO&fha&=jKfpXH6k+@bOv=gc<2UiihjW1o2^*f
zD*;l+5Hj)k!?E{Xjijq5gIfqFQVRtsqQ;u~S#=jzwgFc5NX8RK<GK(hGIGY7%>(8>
zdp9_i`7#%_y45{`E`+iJty*%WZI;sauF$p6K!uegT&2sVV7B{ZGPE|1iKJ9ZJiDs%
ztL>a}k>Y!2BW$xzSnv2;HFJ>C2(2%5eK3R;nIOogzi=(&=P(B7ML_1gU*oEUIzLma
zAUoSEo2s#ktID<>I>h!drkx+|L}4PCdCixjc!28eV6W4YMTgFR?A;zj$H<~FvV6zk
z6U9J4(DJ<a6*sBdsBk!^**D+cfww}sO6@NfDZ%ratC{d&WMb7vOFFv!>Ps_!)d}K=
zLFN-^VK(w@BRf<SV#OLnjZU}Hi=Z?MGLTdZxZB^R@as?*1x>JLjSls$JOW`{=z=Nq
zpJ*GbwwiX`7pH$PFUb13Ih`rk6(K5#Q0RlUpUpo6PJa#pm`^^5LlgDnTC2s@Lat?A
zQCW;Ex3Pclsm)#TkU8X?((dvZHGfTsP;>uziI`1)#NNg#CRVHKq&Q^Ek<q&QrCKA(
zzqr>GDMH(^RQijKjFdewo4S1vauMe!9mYN`yHE8s)Mgl#_@_h+yFIwl6sE)355JiE
z57D9UN2Kz)pt;r|t(vbx9$W7JKMYtS>u^$|EcXBG&;o6`SA`nVj?zv?2c-EqMH_)U
zdC`n_^y!04yum1ak`MG6TEy*HmG~oO4N(#iMI+KjWwi?c5x^0c_h$={+r7zFZtYRT
zD&Vn*gZLsqWY#a)GzYVH?JvnM1>+5of@8=xpXgwcxz|z{N+jq`W9A##`#EDG+uXf}
zE?^zIU)I!!U_C4BIoz7qJ4OylXgT4wOoT)g#HTOJ&q^yuS*&Ok(pdmuMH&8%;KfOm
zi^3hS_H#gMbIrEWF8^T6Y=LJfcZ53a5c7Wo2q&LC&*Oz1%!d8Y$QgSAY>;6|KV&$T
zXn{?6Jm1PijSkrt%T6XGtcZyspwF|H#Zq&P7%tXrsSY&%fLYtVH3=P)@1*8c9;(9h
z>MbCE45dYo3_Um*7K3tWNQy$9B-^^x38|A|;@+I>(q9w=6eqXBMjC;lo5+oaAT$ZL
z%WsDvLSrVo>@AG`5{bY#4<Bq17%m*p=CbE>Z|r@jIaNgOoF&RsWeH_h&b|ix1A>NQ
zIlcGrI<|27bt1NpNhm%x-vQjN9NJZHlSha{9HR{3C7d%i(Xe~MZ`fOb3{f>pxqXLb
zSkmQE{enWP`NV$~CN(K3#Y;1}NuD-g6{!?fSK2Vi8_=(h6i*>vq&&>#NRwnb8FaF*
zd9aoiQ5Zx6KAav1!66Uad|b+koh^l&;y|VU6~bBmI;PlS0FJCy9{y`evs^LmPsRSM
z+57Bg&YEzlg?JyP_cEp)?#r3{k{Hzw92}>4I6j2iq<d_)F5TvVL4L2ziAcijEkxW$
zDf2j*Lf0Wr&7V5`Kw@mv7C^>~w1R=54~H+nOW+{HIbM4mFF_WTG#)GbI{*%sN*pZH
z#>TysAJ*<J;nPYzQ89KuWm1`Z8}OY=_c*-u;5j@Kk_KMFp|Gb>yOMuXupw~`IQG)Y
zAOqGoT;E-6Wnl{0-&JX@I#Y6`fG$CFOTE?2GU6Q1Rkguz<0FE5;APNKmo$gg&O}JI
z7o-rRneVc{zv53suTgdw(KoljvzHF>f0J(~&hMYrAB~;NTRYW9c2Nx@vQsi!1#&nL
zfwt%m1V6$Hg?7!)BgU~&2nPVA_?To?A0pV7eyD-*UM_H=rQyz7?4!gmBgY?WI1czB
z<%=-mx<!hqw=_A`yc=;Z6U>k9S+#HOt0G2a6RfaN#uac0F4lYeUEcEMv$Iseg*FVD
z1m0R+$gHg5GqNYv%KhcgG`}Q|l7w9NNcQ8RR6>%$^*ziie{p?zw82}jh3xiT(U4Ye
zO5l5wPczS6f&iD$SS|I=>Z$1njJanF!yThW$Et~Mgbsn&jia2sB9ivt=vj~Pi&W?(
zFiJd<sURVRHJeBUWpoEe5r+r{^z=sk%9Pn_#Gr2@ezajh1#c(QGbD)H(j~S3we!V4
z>NYB!MpVz3%};uH6d$eSoFCmcRda!P-yfz7h&p(?2XJOlwOpaGo^7r~S1930y-Ei5
z3yV=J72U_?{-}(T=deZpojBIK9=#+P;u40*)vCX}l+JiYH7@YC*7~NqU}CvJaqNV&
zhKHkJ!QUT6pY$XeYFJl)aH`>0OzNfvSsLv_EV~nfnWj1K=yvBj_Kv=vuoeH=rfv>C
zVT6r?#t-)u<XMAXe>G6|vZIE?IVWI@Dh4OD2>|@6QMw#D(3I8bY4sj~_V#*muRqXX
zu&y(m&}!H+q!a;m$$fJ$E#(ENz@%~sCkV|_)aQ1Dff9r~x;m*c#>nBgZ2}cl;L-&c
zZ8lQbY8I=`t+U^~&t#>f+0g~syp=%sYx-AHfbjvEctnvU7zvbv&e%1Uta^ZC{eUZC
z9orzwyAsVMF_*8*Zq=*&!5buLu{^&nOp~gi8Z%i;F$#rdmrO@&WmC8XI<@embI@xD
zv^2IG!H{K%%U&%_<Y+X_T@^}GveKcCMDUic*7Tj2juk%WU$8f$pUTKG8BErH!rEU%
z!TFM&#*b5#!7)OJ0(ykJV(t<DXuH+VbmCvO$p7;Qt#J$-{vmXiGOYi{BL=Y9?8smo
z=t?Aau8hBs6C}{aN5+=8@|1a6H*GpD;hw~bvbAtVu$=yoA*|2{j^Xc=hd>!<J?^L>
z(?e}3bb{I77ybGsv!+Xc?_WwEc?9+ojC49hRt1Rflu|5n7mAme$b<@<UpcR3l|vR?
z4Uenfw({S`Gw%RMqp%gGt_{zS!{ebkrLiL=M$crPYfbK~o|`y3`ly~6!%v>oej!MU
z_g(m4*ADPfgHFDjvQB*wUWuT6hb6IAeGT85r{-oVM^5uyW42t)+_|A9|8P?ja7O-#
zV*DMK)Oqw%He5&<tN6M_zD_hOY7FxlqpIy;jJEPw0rw49tnSU2=wC>RZE(Au!Uo;T
zFjCycj_M>RurbF*CDG*UfNy5|LQs`F7A069Kn6(Fg?X>%<9*-54yd-M!qb$f;ef@1
z0(Cdn{#ohH6pxw=1!^hyi5RS~tZ^JnL8y_Bc%_ehwEA(W%@p@cOWzEn5;nQ!bEDVG
z$k;^nARDKNRp;A2i&_t|XVPhPAn*VJN#ZIOpVcr^G;sXIdT)|GXjXkSCZ_?Z8vpjv
z^vGSh99;S23Z1|-+m^=99#0Q_rxX+hkh%<+a+xN$3rN8w#s#Qb4ow@(*pgloe>=k$
zN{r_n<A~mF8CPu(#YAE`NdOhXj7}j>hGABWmHb9|DZhh5w-6LG8|4`32ujmsBut*0
zm3$Z)hb9)}HRK|J=44ksUdSXB@sDg!U17r{oCjy;GvjYzXc3sYDgT`lcI^=<%eh``
z=%6)jHv{a7kX&Q!D?;l4r&2GuzNgS|CKs1#EP+x+V@oDF0v_J1Y8S^$doXPH;3!sS
zQDL$}&p^shgcfG7Gbc$5+!*-H1*N8L!ZJ+x$BQ@gBfZ`m8G8mwJ$^g_8Rv<XTf<#v
z?6(ddY|Nqx`jlX>dy53lIJS!I8GC-vM;qegxQlZSM_~S(ZFX=vVZJxAr$W|ehtHlU
z8GT!(hxN<dy!|o#uYuG>UcdT3(~iz42<bMe5<o!R(;Ya4C?3MmGb<-lA0Tt!r;<ZO
zWz=l`ZPvCa36i4?5Iy&80!!n<gR`IX4FyJ$X&|(jt`{TnPuu3Q6iSB+81Ey<KuaNh
z{=hZfpqHSUb##Vi?WigMnR@yP6*%9~0-bR8ZxtTMA+_<N7B<U3u&#k^83vFIF{$UQ
zYMh((bpxtzkL-pUyxIpXmi{-%P^PD&PC4=wIg1do55$jT9;^$nU)587OqG$FSZ!Vf
z3C9o@ZM(^a+l!bWqAOK`2vb$rnt>$IvPDz?Q{hQ9!`sW$-3e3#G?hhI5ffDCD?7cK
z$JRdDrAKJubO_p{i21g%Jf@)`Gy%*)k!@H3RNYt=tg1Y0`eLEWb`-+Dt+ZpaM0AE>
z?_ZR+-rx6i?G|D)6TKC=&>N6F)nPHn?6R>%OmCp!mv-rHlg(hA*GNkw*ep1bU-zks
z-d^Ef2`re?2pVlb`2BrKe~s~E&|x{7O4WyW7XV9NTD!2Z=wQv(oxUx&Ryk}^&8%no
zzbH9tn|#p(&P@JB-_9%IvH}?*b0yLYDo)l+@@!c=S3~aJ67`SXrP3KDP99E4&V_>A
zCJ+LH_|GMrWUf(M(e!rubg)hG+5v#|tS`-4t@{7E_pk7@Un;q_dRGj@YBuCx1JxPG
zjzM&$x|alsQGD-pTOZ_zM?4LQJS?81WW@^Re<MCze^ah?PibwD7eEQ7rl|S>HqQGz
zd>~{QddgoCR!j7E^U((|to$WE3b^{!$qP7+?J#@nx+ImB$I$D`VRywh)PI|Kpyj$Q
zGr-sUIdP|q8(q}36?3Jw3`!ORl(e^d&DvV#$B}O!I^S%uPZsOjPd6~GUY?ztq@23C
zE-ARYu<_(;&P5-cbFuMJqJS3&;oKzA@d+fD44OJT1jo!zrmT3lN0D9|!nr4dQNn9U
zH~6!*-YSNY5Z2=HPV{@AP(LKN=A8!Mp*GL&wa=R^WlUJC!C5;S&!qk(FkXJwY5ZO1
z5i2PgB!q%Ep#E8m*SAN23=1UASv19B=8R=ZfST$Q58!)lY+(ROUYz{fg2nLQ0o=+&
z>tZ0fhioqjAtU$tjTJ&^2wuXe7LS?Ary9{>hvymh@3{$<%Sla?w&hRfXr{h~qOtIX
zw2grH*DXp8e}a8)r3F-8Aq0gJJWYiFOsrhD0lv1)mQYH*8OjD!6w^2AE;6kZB)N&9
z0eSz$@29{WQ9Q3J>_nGZ`V*z$M)P7H!Rk;NE6O%?59s6_5O0OJSN0%HBfb2x!Cn}5
zIrdu__17frpMUt0tkpZ_CbrIr$G8uGh3Jr`)%<udaR6FKv-hViSPD<VI^7g;6|RS4
zo*~$ojC-7rxd_pTUDUMl*1y5K;7~bixDJ!`GL-XDBDha6OAUcRZ_LYYYl~)9Rid49
zkV6{LK%oIR)h~34#>B962zA{vCh`A6k=Aw>gM`t7X62q?jfVZ}muA_9$q0!{fZR8z
z51S<&JkBN{uQ+myxD5ya&LX#OSTTQHa6c4#AgDZNU2Ydn$8}IcwbPznX$iQC#Fnty
z5SlAhO4Z?HZ5}NO86pV|A>!{r?8Hecm%2JC+zrrNxSh`XmiqB2;%kPRV<X`w;*-oA
z2?H9)K>=36I&)%WFlz8E&C{Ytca`Mc7JOWvu4-3RXxp|%KaiaXzg2c~eDq7e0z#xE
z<Lo!A=<(|#N7{H09aCEG{uo0j>I?2l^yJP}=zIKuk4_M`-1>-g4O_+}Kr()P=6@0^
z{I4A@K%dGc8DBLI(kaH>y?yEPZT^|5JDDfQF|V}}kM=NOxZbe%2ELY_@jD{BG_H#O
zB+o0W$J%wdm1z5Q`Hv%4&&NWkDQ~Z&>J+1<efa41iwtE3986Yeq5tg}!{N@M$@G&}
zfUv`1>l&jk{gwBKCG7aHrPi)U3I1lqxHb#XV&{h*gGyP8@G9dFI)>0;i#pS6Q72)=
z&F!<Hx?TFZx&{qZ!RDGFYdb6d4up-QFkg0;mAhQ+#`Jgg%a~6>?D$^|rY;me%Gj*J
z(_<(0qxALeiW?8mF+0CmA)K)SlaCU(R;7LPLN-aaGDLGFAXn&Y2rl~^J`62HeHQ*x
z@HFo~_m?#KhLGrkScS;e={y)`FfzU~wx*AxAzP^9MsIqKgEODtH{r(sDc0|f;(@Ro
zac%7X`I#zPOXlX}_wgiwZZofLnJf6HD{1pA6O{c@f4PpnBJlwM1h_1{)l?Z0cddcd
z##$>;1^YRAsKDyRhDmN7B&o$mmeAnd)xo{t+B$Nf#2m-l`bS=88GQ8^Y2W%^=nd1a
zJ%}#N8N60P?M4uhCHj064^*XYQ>Ie|)H*o5`m2vXpmwCo#jxnug~zHQNG$&&Y{eJD
zsio&KSI#{J)qTzk4;O4(pN?zYwQHxSHiK;l;Z-_kXL#Y74EX#F_<-Ix3C~r14FsyW
zWcGTu3DDEj6q_FQs2`i;$cdV75`{$&WGvdp(%KPivqGGpqSXvbh<cYZeXU_1g~Plg
zF9u=nndJEc!2bc0ZE`kbztBhXMQt-5zXVcs3|?Vk!4ks5`v5al25L(b6pCRuStuv5
zWVyO>de%@kX=h!>*GC7_btB99qTuGXM3G=Y5NPd+*`}lA`#OY*q1U6rTETwt5b4as
z{s6w&U*jJ#mPz<es>8n5zEra)s`6VQqNx^o<B21ONX>xi&Kro-?4&XPO<*$j$U9fC
zLG<q841yj7ZBDFOTTnIX)arze$<Q27H~l%ZftL6vD_uP9R)h?w#l}%8XiFKjjNGu`
zzG0YOG2zUs;W6kF@tPhO^(j<bCNf?TVzAO^ANb}_ijFkG!8+NPgn8q~67&9u#=y9E
z!$l)Fq8F4i8b{+Qx^5LX{C8CbtRL*u)E1jGt8^9aP)Z^rr`Lhn0<ETQQ|P;Bg3*1G
zogjk+<dSJav38zUw~D)b4e>|9j`qCPkAFj!pm+%E;5_esjmQ!!8-#l(xIF?XS_yd~
zJ{}+F#HaQvaP3SnI>)55BsUpqt%Ey}jYRF|-;c&pvdwa9Lx~nUYQyVLq-PM`{y8@g
z_sNPEVV2!L`i;W+N?uJ(-(UCRO^~f4JP^}>CGrn(8-}bcr_Cc(C*-gNsS8(m?-BML
z_8cy^VRGpQEw3#vo{S`G$_88uU^%m}_8=h3lf?ow=IFotMFjz*onCaTscqnS=akUp
z=X*6QBfZFP^&S}*5pa_Q@s*}FlTn?Xt?R}*%msmydx1ZePcFo91v5Q(cEbuuj*{}=
z?2`dPE$T%fgiz>|Dd<wcJ_LlIHJc6^1Iz4OJGQVQ53yt4r3WhS8Mrffy~~{HSygL0
z(`K9PWG=R})`?08#FKYe_k(l)%GUdJ$2Z6(4^)4~`3W>Ohr(_9Wb_7_L&oH#hG$B_
zON{K=5L4o(ZN61ub~i?^&jyQ#4U%sbQ$?52Rad5>*~!4E&t8~}bW?)M5H-5kw6K#F
zzssO+&(nVnv0Hpzn>_J-9evSg%TJA-JIrixz8aYeeDMaFIS3`!9BwOqW$^~yk`5G3
zP3~NbUsCzf9-g~g<eX~Gd3pFpXG<XoYrPX$LO*c-y!BU_R?a5Kq&`g2-ytKiz(Qih
z<a}6izQ>-K8v%fFZ(~H)Fs**K={a#rBYY2U8r?lEuC>H2?olPh7mN?FR6nb4p~N@h
z_Z{w}ZBP%20k&;cNb7AzbMhphxE33UPykJHRr?ZgNrF+}5)AARqQ$E**B%XTY$b%Q
z$Q{0SNiK#vf5ofmNr~?&v86HNW8{$-1ziZ&b;i$tN(+XW$~Ncm64cw&?aJo0B7bhj
zBN~egQq{$zzUG^y6TwNXLk6_nA8+YvWFJx3IgKfpS(h%PeA4yHEQ*%f%5SgcU;eia
z&)rZKy*$6TVS(JOuuck2RhHjBRj@UB1)7ll%;3ablAMejMzq>8e4smu%d)JQ13dy7
zNq{c}Yqx|Bh_vXLM!y!tiFOt97_@!yf2rd5xtIPxMwyF`r^#DS9l%eKEV?T|P`U37
zRWStYMH5bujt|Y?nf(8jXww7JZv*KKt{tz-05M{E#nJ&LA$C}*99L|-5l_^}{jj9_
z#q<5qzO$$NlC&VZuCxTtc==IG`ZW5vLN_msY}~8&xp-D^;2o5TCyx^qMER*1cJ{`#
z_6NG6Du40AX7eDAM6xE)mh+&7&zg7zGm=f_db<_sM0)({gVeJO<Bsdl9hgrvg!%C7
znJj0QP?S2%^S@%@Y?AOdbrnh>07U%fO<8WG{#F=PQoKDuZ1aj0?dNJ(c~77CT_^;S
z(54~djRr?q*d>3$dnz|VpbFHip{mc1b^>ekN@6>wY54dV8hDVk=QQHbc=uWjG@ai#
zt+6`G*fI|TG-7CYhq@f9CquJF9_(4=Fu#P!bW&j${<?My3XDIQ?3@H3#sSfzi}{pD
zXTnU&(%r>iw2N%vBVbxZjLyK+`zG<9wCzdT*(p+c9hZn+rCr-^UV|qJ>S9clO%KH;
z2<@2P?t+1B0Gti5-au(xs%d|)l6gFGQG_oHP}0y5>V`4iM+U4h_wnjMCujgc8`pe@
zv)9T+3IVVUcm}?W6sz_fKc?`hvM$+*4~r7zBEmgLijGZm7+Ja{$Ar=^fj_1C57f|K
zAaZl!#7>31b9#Jk%N1mib}eJ~?8d$)df2tSHE-6T_y<;iy3mS~`Zew4Um}==``KQG
z@1B39fKPI09AY4uMJP{%!G@RJ&xw3_XLj;Fj+Q91BUaJ_JROZ`wcUTmxtu)<g><l2
zKDIyiO82*8r895q!#<@O02grEAIv<)ckAer1$O!1SUNb?N(s#ug)>skph_-y7w>Dz
z^d~Nd+ZW-wBPFx5p}rVJ<8dYH+mUKfi6$Gl(<k`4%*{$NR`Z7ghOKSzhU4|}MptXa
zW|MC}nJ6{MHc(x5zjVGWq7T+3M57h6$Nu+5u>U6J^(B%?A}j=nPdvGUxN$^Xg*n1T
zU!w;zDhL}f3syaXYs9Lb$d!Hm;t8Qva{7-f!%dXii|*;Le_50(t*LWT-z;Yhc+b%L
z+dX}xtkiQ)ldJbzSY}{PD&>c*J$NJDcMT};nue#fRF<ACzPg9o#U9Qoqx>2t`zMr5
z(#^ZSt2CKdB{YTOc+_&2{Y%l4!JHq>lU0p&4e8HB%FV&#K*oE66LZrF57S&@1%&D1
zRS^OHR6ZIJQ25XWv)WOaZGrp1R8<F}id<+(M!OdL`7xd=2sI1Mcpt6lV_bP8JA=6;
z+S$8tb1^bz(+@GbsUG==slbVMkh>-c_Y3oy`Sw4mYWv#jm&oKwS*lXNX4tT7cf;M7
zDgQalJQ2hxy6u*}bX=mc96Rb`j|`&}-=wl*`cs8X+FuaOp$o<b(!_YgU~PdtSg;O~
zxP0aE9O_lrlPsh(5swc~`r_p@XL%HtwqY^GGN14JtB-8H?Bpw=Q@HOrb!x~UXS)44
z27s#BY8ier%e=8(#aZXE^=7xXl?Y~7f8pl=-h!kn0cLyvOK8%;1$U@NaYj^>ZS~QD
zEeUy|?U$?aS$qL>w)zSwuTus#A@0)+X?m58S@4jOlAY9_@r>Y+9`hPG@pH*BPbN@F
z&mi#I5aNPM%);88O?@_zgMLGS05*3Vz)`5+Eb|wN%bF<lj;Hnj4H>inbecy$iWDea
zGUE=F9LlsEcuYi#LU<${5w^E4Fz5NdM9tE_Olt1>k=sm5y*1!5yY1`W6cg;MRHvU{
zs-&1UKyL3FVEit$@G+M5_3wkdWOf4<R`@z{aUu*eUeC)z;HSl!yVC{-K$?Q4n&|mU
z;a?+b3LlEXuI`>LZiN7uYa;^koQE{0U~c*wMkt8qYRKY?FHl236&+Ih2GD&Vs*t;R
zg?|wyZb;1RTa*5_`ZAGrK4a!5wd&jnM2%zWny4jV8v9y&Ki2R?_0?)*wxa9<REH=O
zpl@Ej%~pcp*f^7>o(3FVL7WQ>0C{>s11E%6)~IE`t0=};DfD9fu)t$gK}~-gp6~<<
zwAb=F5ssW4!-8^QxF6WFHES<u6BKh8PHpp`x+`DQZ|*!9wlCg*ktN^OTqS^@WkTlq
z)T7gLx;L<fZ+;=xnsw08#L0fSci1uFs+MDSApj}bSKR~fl`aC*Xiz4rgUFi4Lyggf
zN`XXCsH{{ZX&nvj7MWAYV12_gBL^CJ77si!hduN7Yjo@8yA8oVt6HYn3#t$mRIqw6
zMEfB0#GtYsn9G4GH_@t(x25&pD`GwpY|M8zU#Dw#-#4C#?^`3)Vpg(3BN;i&QGQn~
z4hO}v4dUdJ2<wbiUXe&O<!!gK3i4)N4iWfSu;zZ*R$q2ojMe&1;rmQ~>tX;I5<@7X
zF3hCQ`<PaP69UbR%|yFD^a!t<F5=*E*9z{HG!k|fbo}JG#!DZzdU-wz_T7{ZKs|)u
z>bgTrmZpUnSm(8W30TToF`t!vughYj%fU90ct;^lU-R2(2B}UIXN96~-uWO0v5Z&s
zO`7s5LYo&DSv(&3n}}Oy{NCN`RwP0_5Q<hU`*vM9O$D)-2*#AfQ!HWls|7~t2|d7-
zeLBxQmDfTpEVdZJZ-gL`%Q4jwLfe3uq?TuA3)hwnefx;6^Ykh3OsL!T|8}?syXMWr
z&B~9fk^k%!33(jlx0*$^7NVe@OWA2-5n)zB)tUnIt|vLu=omX^dA7S{ir{aJ@vy$H
zVfz8T*pv5rQ%$VCtgl!T`K{N^LJ(rYCuq(50L|@IYU73jLSh+Fnrk-*p@hS6%_>zR
z>PhjHOLI3ZTmf}b2y-@@lfWc;9kA<dwQ96iNI$iMpaZ1CMbasy5i?d<r>kmvt{{Y6
zB<Dx6MxjtI9GS4V#Kr2HaG?V9hHH#Wl%NzJ0JJqp-ovt0wi?<%amC}YNfh89scl%B
z9r6S7vLHnXVC&Y0`^fJM+j^=1{PL34CVeT;y{pUBuUFEtKE2vrd`1<Cg9hvum1tM8
zi3}){EFgj6^6mgp3}P$?lW2J@h>oNi8>dXoeo<aV=+7=qA%60h&`DsAQkLClHC<~L
zsU5WiC6<y@01cty{H8kuG1R(3!{c!#Gs{-%3`83{0|gbcr6-xvjXlBv^#q&@C%_RP
z-43U-I5I&p1340%w|2ievRm*6u<#N3oZNX}=upp-z4_kwmXV9v<^;=0wuFV!h8A<F
zagU9X$_iKMkW_0PX6!-o;2w8jH-{tOCn^w`WFU&yyb-uUH!bj|8N_d@8oyI}DA}+S
zybf^_Z`aThiQBiuq}Rp3bV=p_c}%TVUzOn(ZV$c7Z|$GMmXG;;`?*?V$(RY?b~NTf
zDxDKCPPZP7O%R!-huc9t1wKZwL5}&H3(K4jSjOK3fQ5Ju@)i5w;k_-&)gEo5Myt<k
zjN1!Z)wW_%>U+aWmu0x(7~KJ2#_@JVm@=|xmRkSqNO3~Xug+%mbiO+PN6dkcON96e
z96BkbICP%xST=7k?M;J|0L^$lO0I&p+%)`8dq2HJl%zQ+feFl?Yb3`v!XVcQF&3}^
z(9}cc+wqHDD18$t^>2*O!+|-Z)X1g(#!L<aYH+MgJPdas$|3U{uS*D}trh*<w9Po7
zQq24ab7+%ZJyGR!)axH`#n}474+uQxUaG<Hc6yfLA?%=X(BOV{|F>V+!Lq_>`RW$2
z#1-5ls8U}9Maru;ck_~>LRyNV(@(Ypr0a>P#$@7&5FKB&UWIMY6}4d~RGDlv#H>TI
zXUD9MQOB||<ho7RW*)CirO$?;Za`&2&dGOO0gBBO)SM;QhGj_WFPm#91nGS(Vz}HR
zD&vF(Ubt!!r@o9dklh5na@~q3MIZWQC6Fysw2u=k*o2k=#-~VWsU;=;dv1isOoD#y
zM_JUSwGKL#S#}XbboU?^G&@}_7Cf509Xc{w%C)MVQ*x<#(VL3pNzk<G5D8B(e3l4x
zv}Zi!2jm5N2!ZH7a7yV5F2|VzERCnW=?|MzT>aYXek&R1zdt*cYc|{49Vd7Fb~u_+
z3p<>xZ4&sNsHK-vK3A^(>_uC@lGhUE9Z#b=-V!6-@uhyBoW4|k-jMw>7nlfuvxMH%
z$@9{j<`IhZ2)@xNL2Vr6A5L~{i+%7QGAoEA0|^-h2a7X5>L)`YG(*Xl>BjaH&}!~9
zpr|FsNE@{ObusdR%z}vOq*ly3!}wBijrhLq#7O~eb}9z#^PZB=BW(6{dB<c($HoPK
ze2yy;RHB5;1rTi~vB8TOZm3x;G==-4fzM!#yDrK>s4%C{4gMM;t$0g4NFzRX%sX*E
zm<T(GrY?zXHH)W0O|5mwg#!KN-Pz$rw_rjSqCtrKQoW*I)o|ybo|7>qXXe6uPG0Yo
zQwgMvN4J#Q#6?q3+TW9o(tG2PT9$+e1S8Ehben2jmnOB;vgys~ANPoZoWi5{345BC
zsr#7bkCq?LQGB|zeI@ulhES$Grk!ZFDZvn=Ir$#+8x#RG&|q`+r$kwOF9L${hZUB3
z!2bCQiWb<kP%AvXk*v7ocb32IZb>7R*;`#$S`U-K`TI>B8zF2zQziFZgw7H4`YBj^
zje(DmWfscH@!+zLfVIw@;o>Jd)dLUrqc}4o+Fo`?w|FEH-PezCcgd;NoF+y!oA->r
zbK0T?_S;g}!zm;ET8yT(BEUc-W0SUW73XoVz%wrJ2T#Es-<9sn-7|_)3&`VOLI8))
zHiBSNJO_lMQe-gL^HpO*){4|ofUI~+{`s}j{~wOg6iY3niBTt?rU1#z-!GIo5Tf&O
zh_mrJnh(hyZ&G!a^3joVU+YCAX#FOG`V13>YKU-egDOePsv#S*c~9I8dnmPAV63Wx
zB$gPkBZ4YqsYz?#b)%cSC0Yp5>)W+cv{wb8QP@63SWm%8<PQ@(k-0rL56IsjS>w^*
z-kUbPI6f79Z?FAB(p-W+?9}=t3urod(UI~Bj1}t-%ocKCwHLOlH7I+R0D0)#yxC2w
zJf`=Z@gBv-3CDYE))v|E;aFSML)b))ae`VCF)>S|WVqv0f34QN3B!Ix#?a-!=%~H_
zbe%g+g&PY#B#~HMVly0?4f}>jz8jaun1F&<9htN^9B{KZ94I(Y1ipkXrLBtqLx_Ey
z<XY2MBKjki)}+OlU9nc^_IfcrkuwSfV46<qcQ6n=Md)!SlL?^p%X=}tZmxlRu4KL!
zVn(r^V%=xP-v83{-6j44k7+Pm1}KxQ!Mgw>xZ)kx<?lg0D>yuFTX@Wr6ZSkFx){E-
zx0ll$)!Qv(cc~KJdR5!P9qE7ZdUvH)%J}q?jxq*${)}EBa$=~R+%l9;${S!I2S>ZU
z3tHl<AB7^V9r0N#D3R@iN>aR0Zx_`7Umh9RhXZl$5e`B+Q{Oz@t=-e!QMPO(KW`*V
z(OIsJ1a=<^cv3d~1PaGb+7BO(xO)@%BLif5b#;nNdNPs9EyXc~qHT3xCAX6F%7iyG
zpq`dXH&*KzILT9XTQMod<LMSEK`F2MO<+PVaBBM0A<g$PUw12tp|Q;RZQa@(?R_F*
z`anYa?DOa*y5jw3D&a3_E3Jld+#Qs6B23gG6&Xw3e_ejO@dF6i-61A(F~JNh)d1#>
zWptT9{EFhQ#aa>YWvW@yt6tn$122h;CPmKW@cPNk0dGszF&Pf*L#o?DKL;F3cTcbR
z?F%?NRVlvV$V?A9tMyE7si7!^I`Dk@VKuXrf!tE{I;}>J*zWP5a(8uInC<qU8o1BW
z)~IaFl7&=QEx&Au3u?^L*NiMz6Qyjww5WTshcLIrU%>Q)@>YN2F2EGUL)sbpI^qn?
z_`X<goZIkbO~_Yd{VwbJ`qhwpjvsWC7~oBpPa7SQcJ|+nY(~QUD3Ok>#KMj|oKF5=
zPl!&h_64I8*(#DW1KKqz^H|PVTn~&t1Stl7oge*-W0Qs^Q7Z^rCVV*QpU^28A1Ct4
zP(2P2FltAvE{J-9<ShMMQd>8Dy*Q-PT@}}!@CaF>K>X_)w@g#5Szd4@wRAqU=C00$
z?}9EJNyC%1na;i~!gLW>KQ~ttEL7|jM7S5?IFuPPf1Yy_cWgG?43rBZLtyXdZsY@`
z@b2<(K85n~YygB;+9cJ!hyIR>9BJ%K#DQP2k<{UsHV=r*cGNBOivS3K+pphRW@s1v
zN0mPO=s?+a3H&PW$7rg>v>O*q{rQgqK`SEnMT!Vohz>IlapG&9Y8Bc8qiVNfz#-C<
zRfSP3BF050%&QUq3ye!n94_g`=ye6&xB`IluPsj46^JvTvItn(xsx6X*MN^%Kn?kW
zI!9rS%eKg>QS>?DLhKmazIIiE<DLX8j2+On3BQOZHaaNOlaRJ(@3!QwoqfWZSbQlR
z%(6RYrpi4IVI`8(L*sM~@j7XG8DHxc$I2IE8ix|7i~?g4NOZn?G<<=YbGUhma?A1z
zhh*zwe)xJax^2imY6oXdnuyC0e2*=VmDkD<_ZToe9%SV`xo$d6z8t;00U)LZ6rK=n
zg)5^(9xov!nY@@XIk@m_My|xKZ8^y>9{?@jQ&NBy1o&q}vHb`?tY*xOcLDFsRRMjC
z;!RS8mogKgXKiA*LhZ{I-f5Ry#-ybUlDd5pLW);yl*F~j8_Bfqlix#8_0VRJ!cZpT
zvc-0`<w{2OrPvyalqZkivg>0zaZ^eCqvihcZvH4|o3I79M??mXz!_MQMp>8<mnXa*
zL;y>ZOXmmI0YdOnPsgxOm@V6C0}pX?2LjAkS9%RU#ln#7{bE&U@DLxo+i`>_(wBYZ
z^<PXhKqg$O*u%m0J<ffrNL?#_?mZx?tyNIvi!a^vGaOYn5pd&vqKv0*H-<mlXemXu
zD_mRpd01o5{zWS64WkW9iuR|BacY@S7;>^-oNRxI&cY^h1W%z5hQlfh)`phvVMpm%
z;F)(IOpOtppr&+#82m=Qp9(Qja8L#-ZEidq(h8|9&kfG(lY6xM3o1mFK2%1CG=A*n
zkwNaWg@~GZWq9r9TxX+f#57OPnPSfj%<cHt;p&r8JMAc`i)P>zRNShg<>hzG<30|~
z5mA)urCpX3Ru-c2ifWw!^pcn2hfmpG))899RkGVgAA|U%zn)(R=4{_c6eschjywiI
zGrJ-}c_{L5KUaR*4jHVueuP*X0u)7MNKQ%}n5VO4QuM00hb9akuF#o;;Ik(qp}TTc
zq%FwX^h?l~z6p`(xD5CJpwue9Ygc~Cwn>Pt&T!e$3BTg=LoDtG+~gS@*uxUZ-mkWy
zd1en{qNo~iGMC*YpSNVl@$IHI0unJ|>ptQ*v~3JpA1A8!=Q5*mypG7jR|o4Jisk_E
zthKV(Su?c2jG@AA+c7mxs!XxmdBFDCqToOzWhqL9SedGoh9Tn7S~U!TCI4)sEGo0K
z>(;_3=Brb1d4ejA2V__dHL%A}lXQ(5JFF53!+MZSssd(1?8Na{i8cPbvPg;g>&e13
zxc)&CDndl4$ep_gAJTLe*MzH7y#Dkto0l|<<l4txn!PZ8zt?eNw(~M+7~VqPhFe3z
zynsiPe@~8yq0xR{A}htG(U%%gqcA^u4cLC<H+f5m)qgIPP1(3Q#0}U$4p~KQ@P?*t
z2i4X1N+8+JDpu`6XKRwAF2&XS^N!OrNz;>G+>tGyYw70ZYxmQb2GHC0NE_#Yi#-!T
zLW%n^5(sG4Fo*fGF*;vHa!Vk{+57E{|5{ok0s7Y86Zu$(^rFf_820f<0xAq=N?nM<
z%FT_uykN}w1kBsz7M*`GNV+H9Yv(lJmo~I}%0x!MP{Ye<uQ$EF_2YmS3Rs<Fl&r^I
zoX%4nz*!7qdMI5^24BK6j2n^QL?5juLwHC}pQ<p0q;H<7KE1IADZYq2((U-#@;RxC
zk}&Fa=~C(Af+juBqg)@v4mXNmvzZm_%TbUde0E@ta<%p>=)r$+2HEW)dSR~Tw$gj5
zIf_OU!+m0A{_c(^uP5F4U8uO#aqo@zDGQDMwT?$~e03&&Om=NE#EvwKv1Z-Df)pxM
zOwHM<R~nScCn#g29f^8G3OpYbCi&*Cd2<jHdneGv^PXjGISy@iE@(UdrHqNwpQ)@M
z;C<BZe!yxNR>$L7(DX!<X2j}5EFmMBlv)L`ttc5}G`5-vvLKf!kSC040zzx>eR#Wb
zIML{HBj7I-=7bwwPGy%!MH#mlyP?5%e-FfhcE5d3eZZ(pCO@G1;0;H$@a!osMpzuL
zhak&LeDfkkQWVi`Q*o)+C`X?>5(25MFLCXRaJhX<Bk=1Ue@pvE3MkV&FH`_Xify^u
z2Yjg0>+*iDq5Jo?nALG%RgD(d89~j^w$Ok)MaOf<|GD5m72u~AF+XLC5}Zx-5p%%X
z;99Ob_Webk1Yg<*4pE1y?J``|AlX($aoZzvm;b@-Qm?2I{X;l5yk~MJE32nKWCXiu
zL}Rw4=_Rgt0d#&zWJ8}tYw3&?W}EqiR#I2#qjB)_bS#?+3YPB4+1w1PNR>6di}BQj
zdACByE6NkmbjTcPtr&{n+DxjSxNRK*uL8zvu75D^EiJdXWlzq_<&dUvF$7Tr@U%$d
zw4jq?K6~e0*2h9TdBzT48?iURi^Iy5K`|QR>Kb}WULlEx_#+2a5RP+jWq~RaDVQ^Z
za~z7+Di$dmp>ERA%-sh>+s?B3bS{uE<iDO@h@(%%&kq4dJRBMw*S2`!^00Jla{w8P
z2BDT(t}zU*_ki{5A0*Yc_b`K)7!Oluinbd(NYR5QQA0=I=w`IW{?x8&;TuVEC^9Y9
z|C)v=5NI3LbX?Lwg>~rpx5eIJ_MhVIc-1-X(id0efSQ($`<40THf6p^4<mDEAYl5d
zO@-#Vl4Whh>m)2jF#<L^nX`q0HhHsi#gB0tF<T^pC6k`nQ-`xMRH-heQ~~;$Me4M9
z!Th*{6Dtn2peLB_igAO&l<N{*26-+KTQ?A4+AbeBxKTSSWatds5$p^xq6@SiOV=9w
z*K2m9l(saJq-*Sl>jb3;LNWWKqK(?UqAVR~7+{-ol9R_=i1!bwped}k^K>U`RpVLP
zMF})RmHdtHv=k4VZaZS`IiPKvqK&V#m~Pflp<iY>ElYZ}pJGkso^KAr*OJ#7YzXVq
z%MdSUI98aUED78-0h4B1&_D!5wExA-2g_Aei_d*Zf=y0H(6}`;0RcJ>gq=T{8r<^B
zPV%b+<b5GyF=O_4hZy70TGu&qrh3tO8n6I0K+3-o>drFS_3g*@%We+Tpg{xq^Vibg
zAqEcK4PF9`q{JQ0dFs8Rsg6CrMWcInut@}*JUKL4-?e{;(lPdbfUa(=wKPJCqn+*O
z6%A_rLL1SugAoa{#d!^up_G+h?Y>V(lQD5(r|6B0yh-CkcbP+#cO#2NdwlZujofBd
zZ7V>X^JKb&Dn*xYtNdDFi<VPolD@j^%dywZr4+k@?AHz%f<_&7pFj*}`aia#(zX${
z8B+M{yG`ZN*Wp5m{Pv^$+b2<*(y*EU)(}@`JT$dPKfc0&x|2Q$!UIQ4B1F>Dryq|v
z`RE&qYpIXLk=5WhEw~gt3|SH`MBPbudT*n?#V<H%7IHcbh6mBZcn`7$uB*UBaeJUW
zQ`FiGu>Mi|a&S98SPRIDtP{F0g7nk?q(`Fxe9zqJMofvo&c9dh(G)NfuJtJ0%usA>
zBrwnz8*ZARI7_yY6?hp(4-o%SKN)|V%`u=N%(d1Q;uL+q*?abn?UA>No*oA-G60kc
zkz3Y}j_k$YPAk(AW|m38sP1>SG^$oF$y{YBy%7zMMj-_4d44oO>B#6}xi%)XkWs&H
z^6fYP=I^BbGJ%&)f78;#GOSl$Li0I%>=fpoV#g&yErDdJ)7$nuecYxb>-ZeeMT1(t
z2o*TLmC0QdcL|Lq%>B^NMVR=_rdSSIq!q)W>6M#i76ehnGqzdA1)|O|)*%p59BtWa
zgpojUNdLEi#=hS2m>ajNtz^!_be?5oK3^#@z#pf1W-MG#+s!g6#B%0arE}>h=%xhs
ziW!Ubwu&cO0@a~>c86y(m?G^4OAB?HX``uWgCi%BmC!&!965=cK(5Fosvpk%f1A(Q
zl44|4&3|)4NeJ1`5UE9CqGbNKS_-eo5&w4`@2Cr#hJt>VNPcSvI#dp3bi8SniF4<O
z14~g4P8YYL(!f-d!zDvVcvtGdZ~AB>J?t!9X&)J6No|Jl^sG7RSyxuGuk%Gn_xYLh
z>!Qw-Ma00j_w4sf^)7HqCneV^G^SXhgp0D-=1%9MbH(L!e8%)3f{fFFSY9AVgJ@k3
zZT6|U{yshzz1iyl%=WS<wgr2q18O_z0H-_7&&_WV=jDg<ggOF*5%x*`O+Y)5#<hZ$
zl@1TlJXjsQ)Bv;KpLV}WwF!}+H8iir*Vp?#?_xQ6Ec|KPD4vy4x21N7h;3cF>|$l;
zwJbH2S6PxXmeHu}XFXfx3rlISQ0}P-U_Cz_ifiN!qRsCm>*>ad!bw~71CSEo?yx2b
z#ln$e0$AI=0@tLHg&=v{NKyI%j@C8cvcXUo7QF@B&JUW~OH<O=U{C$-wEY2u9L^CU
zH+PMSWeN|`ip0Sn*N@YR`8Ae_cf{t_cRT>4NXf4F>lWKTg@(Rs@~sA1Hb%RfX%v|8
z6WjJdI81(ZXr(7-sFX~iM2yl5nm)e7E7**vj^l94^aR#ew1*BU6fv!KUKL^&!~48$
zucLS>I0g}ipWb4$ZUO-v_C9)4a`;dnP<k^>Vp%BiF69)~oQ__I>)YT{U#B%!9<?nD
z6!TFIj^1{@Hta<RYa|LhXDTPfZHQqeTQ&?5`}fo<>#SKiJPWd1BizD5mM|2|#s;Gg
zS<DbES~mTCOwVEIW8q)CYI~i{boXJrEh)j;mwiEYBR*I1tll|}3GgNruFLs*h<{%j
zmbD5%PG;`S#vdJ5YaC_HHCyZub+-!1TAUfcHGdaP5aUG8*bY7OiU##zDp=-qcg1--
zW7G$Fe$})bH1exnaT)i{lk~@*lLU0pfbwv7xZ5-`ANt8qnRPtvZ1s0R4nzpygjT2{
z89%%2f^<)U`g+ATNYDf^xUaoD3RsA_3;*)+VZlmgU{Z7R3|6wmT&RxfEjjI)5TZIn
zkq{_T0rbXta!;Ox&bPY}Nq5_0U7?n_khB8{v$RkEmZ}}`2g{-lQG>sJ_0$c$Iga~M
z77cGz$%4{G!Gh#DXJa<ZN7-9>SsQ1*EQ4!)(|B^1;t(zwz}h4Bv6lGh*)V+J6IKx@
zrY?Y3OEEK$>C_{s7mlm7(tD^~sLG?aMeQCpB2d^m*b$PnNkuWF;WP$1T#m)?VY@H+
zW|y7b@*T}OM{wqNdn~t0`olKJYN{yJD=VUyr-RIiMwYq>pm@-bo+S_5jv$;y;yRE>
z4(a&kFY!^AbCsX?p~PYbh!d1QT)amM4U*D3iJwyT`RCVF*HWKC?C1rPeR*|C!}F*k
z;?aY_trBCL;dVL4q8tf=rRIwPOMgL%jc8X8Dvli@kOY~-T9~Y-30b!HE#6Nx+4cUC
zq99%b4bn??bh?G~r@K38SJ!6ql$+bOUnMJR1aqm7!8w&U+ZCnfCh6m!-UVk20c&nt
zh~LtNKPp=J+s#PUoGsls;at)%04<9lVu5u{-6rq@a%+^4r?sPmys*Q4kcugu?HS0P
z{3CIB=nMfKW?ECbp}=>vuR;~5;q#AOb1APkNbrh}V0-R1f0$B)dn?p+dFsYlWubk*
zrl{~ChQm|U?uo8M`~~3oa2iFBQvB;9)k>Xdmf1=JD3ld*lPNac9*iNvd-7o|TabnG
zTdcWMaXq?E`=7(@lE#=+o<^h2GEABGAH@L=RN9?cd{SCJlUqeELwWFuXGqMJvWA#7
z^+wI0Et4X|#Pu!eAE_sz7uH3{AaUw-`dT1g%R{;X-H%Dus6sO{?t9zeIUx8d`yVXW
z85jZm>|Cd8a$fljyH``yG=?<99n}wFGDzmOLu85I>XH_H_z*MgSSLxb0SUbd%OV(<
z^oHgH{u$9lbSW$siY1M2yX*|A$>W7e1H<aR?HGPpdycN4%W=M~KTzFgb?Zuz;WGNN
z6W!)y-d0HC@nN%*fL|X7Fi_8esHEbZ9xPd&)jrt>aGMn8HiU(o<1A%r;<s{*Z`$n4
z@z1?L*Xi4O^ra4ohaUf9*ql#E9gSyD>zulA=f_kP3RIZsIRqA-kQj1w{UoW#vqIHi
zKAl<^st<vA(=&AqeYqo3c?jnb#x-N6A(U^1l`PI_#vA}-%$ju#8Ww)ajl7h<*RgRr
zqNYN7vJ4M8<`<xZsdPnhQbrv7={TWyR1I+$O&50Mf=>l2ks4U+;Lvn+#^KE{5^VLr
zY}PQCRV%X>441@*E&qbJ-zm=(p!U$iw!8VkE8Z8Nu|(C*?p+~yV}U&|SDZT;=S@Df
zsun@2<FYt%_mJdUHH9nm)@5)(j3Las^;=!}Q^s-jMwRLP7=~^Py+5#sFbVHp>+>Fj
z1UKEQW?EM)Kbn5rtc$D2z!YQ*Zx>F9!*>K5mJ}QxznbJT<Vw2@)Ds=yVAex(AcaWP
z80n6WAN$gR!e~yd`@0!N&QnjW0F`~gm{ms9#x1qr*+6cxO?-kx_%ZjQnX(fjir)_K
zeEJxtJp^jON<_j<5kuKsm4T8jZbAk6R?XZvSp9k5`l{?PJ|Be{-*4eNiGL)*8{FJD
z^Xqcg;G+3@nmD9W<(4*)kUFhnDvRBIW%)I?p2^rmA*dSpE@q@;QaClT<Wk71Zl}Kf
zMwLtgYKF(y(<^hGWLMh$0AofL_U4Z%@}M=uj*yNjv7n8MAZm07dlhGDI%W#D`5c0N
zaR%NorH>DvJXdoV_qe{UQ(I}hY)o>@v+dd_ex-xuS<_0myfn7+o-*`%8LJ@Xi7~#@
ztjI$w;lyNGqX3bR#~O@^SPUD|L7SGyqlHlGT^z%ajH%X@o#D5;o$vX3N3rP_S-+(t
z&H;itnLx`>;Z1aT9$(5VtnXGcmoCLU`-`A!xkT+lWfa#nN!T&rd0QD@yDkuXN(O0)
z^Gp4ze;;~g*yB~e8aqD;5>;g0C;Oot2~x0sXJ*ksg^?`%n_xgtcsgn@xzPD!IjfJM
zBg#hK!kwhP1jT+`oMfzosOE3dZfvIW<hFR7g7Ot-@e$lLnRiVoQv;)aCnZ?HNED$V
z0CA^@^$`tNd!qV{5-97dRQ|;L9*-p|hMg{ysWC^bmH4>+H>}AQK)oh&jvRcec^r8-
z@U^IB^mM98JSEP&^rS*Nngrw3vc!Do)NsX2D0+Vz(&H54eGmy?+;d1Et%`g>sdy~_
zd}T3yhhNMS`B3CAh?$|^S0D*zAYS{2SK1?K;17V!YM|nAU3Y<MUS@Rb4<abwr?81-
z_KPwGjTjLy1xMGpby(xT-XafEIf+4Wmv-`VY{gbljNGvRo|ykL;D-Sgp8_(qD4FhA
zU6!(VRMP<$9)&Q#j)`euGC(c)fVC+Rgd$%z9tA?(wbwd*;Wm-IPiSS~X@-5(EtU3G
z-TQRp!Au_M*1ZfMOeJgKF8kN))ZBasBqyLhUFZo~rqKi-C?*Owv#11O6Kwl+RZ;8`
z)M!vno`4f4cSD6pQosYDbyQQT0TSf~SU~bSentmIBYM_H^x~ZNEZo3d*<qv=&D%>u
zTpao6b#V4Hbk*V1FwT{T#ZS~Nl-L@;M~(#S&q9>s6~pabQfu^ZV6I=AA+dJcfUPzP
zMo4Fjb-rPOE1Fb<4sO&V>y4aEIr|(>&sri4;SyqJA`(FxBxkiO>|t?ERrzxF>M^xA
zhGaZkWb56Ml#haIL?sX>nJ>f<9=pw|!@-ZnHF4W~++K}z0?VGWXDBCTc@ijN{Uc(}
z!WEm`fqZmV^cmxk#%rm^2q|6La&|i_oLa!SnI~Kcz*vhNSQ=1nM>`l5_5PCbRfae6
zi(!)|#l)@@*=#Ioo$aT4zBBhQy?MGRAjN$!>AepqOi#|uArC}Scoi^)tFbwg^=V33
z_<@PHm`>a<Ig(Bv$i)D_*SBOd?>x&Q4(ce40bNO;9ywv!ehqIN(aah7eBMpRlQ-TH
zi$zKcS<^6`lfVtSA`o-boxMjB_`p{b&=g{%z*iqce)`{N&wns|(>eWmKgURgeU-lU
zial}Bdp4&_T^`ABs0rgZ?vXQ2^E-_Wsby7K<r2d6vHr$Otu>9?o)UHC*D5%|b^{f-
z)Ja($FA)+9*`WCXZP-RjC3*d5ml9A3VK>LhwxKY2KGTSqvfOw)MKdah@-S;!-IJMu
zv!G;Mx&2NEGx+m;z}y4ln^t4j8l=j9oBs-NFeod5rrt_fvrF>m8VNFGjK64r+;Q|v
ztV>7{mg)6aOFo1E6jcP~uO}+|&d~i{Co$%e@n|mh-FYaFyP9M*ZmNUynv}w0uI`+q
z2}obh2zFJ?(-~87gAMSMBi?3FW8;{Ro*Hx7Ojt$IdLEn8yIIBb>`JTwRh&}FPU((h
zy+;;Nk8P8<yg`jbdxf3qA^s5GHZfrIw<Q)*0rmM{!HO0PYB^@G%Wx5|KD=&mDWPj<
z1*R&zu`H;du-8yPeE`*i<&$Xv;hwf(Vc^LUC4(=Z@xJw?-`+1Rkz`8I<J?#40aSsT
zp=h?!3FH<Q@!|_~OCnN7oyHG|ok3YVd57DhUb+Cz6P+*si$#LlENPlSD1l{zdRTBw
z)k(*<BY2}c6fw4hHYA(t$1p`T(q%BJ3G3Pbmn;imE~n<w>_FpxnIEU6=NvEa{H(&P
zYl>|uMr|~HFL*Rj+3e%X51QLve$JLpU018Glq2n(QrpgWygu1k4gQZvRpSSQYs&g6
zvIO<hE~%k?Jz-S*T-ieDAP&nD9%?8TR2UNt&h26G4?rJ8$5R%#r|53JVWnnOl?V}z
z>+y1xU)jCxs=qp1Q($<yRv8~UMSTMIElYNWsnu<(+t>ph@YkrF=bbbENR(4Aksgwv
z2KnPfJ)h7;lzp<_GVIZvV<f^IJM5qJ3#O}Nnq({STia0{MOH-C!YGV8yVX5Pt&$YF
z`d4D^0&)kqP<;F3o<>2^BfegLf@nuOSE@zQd9>di_r1;!)_V6Y*Dd0UE}w!MCrF7Q
z+aFBDs02YM)PlYotM?F;V54SLwS>fpIGUY5$2X0GwVlkW>%?_B-;jr#nhf(?mX6)Q
z<qF@qi_#)Kkaxr1c<-XLh&8{xL26DZWC}<Z%tviyUFj=h&B~uYDYid7sz|pI-x53S
z-q0}`4M%@6s)*HE-`GIM?-~-XFglxxjh6*(>R56xzbyxQ4b(bIY`S+qFb?GqyFq?m
z7xA68a3S8zJb4-QDj^A!)u9|G;&BfQ1Zgje-Mt*rIjLGSL#J1d+Z5xEgkGK4Dyf(Z
z>ob*Y&Tqn`FmN_x!82((=>Z0e_YAik1zZ--CToG??{jx?OuGSd_VG4UU=dr{<E8_y
zvO&tMg0jP+*(t5e)Hv3o0bmJZ?!v++TK>1qKjarLqjPslzg+;Fp$7D@?x3SW1yk<+
z=}Q1U_`hxQC;br>QQV)rZVZ>Lf|4TU8u-W+8C#<vi)#ce6jx`AeLj)nw9eyYf_w1O
zx1uT_g0BHUw4u2jCer(-c!Y&YmNCb^vWH`Z4YVkoV79VvNp_QysIML|X*}r23-`>&
z#pWUZ5eSIzd5ZFA!q@_o+4lKolQ(6n&cqddNOKw{dBVyDMgh)WEzoRJ`+Oqe-ys&;
z);Cp-gNGVx<Q~{s&D`;C>nMD4$8?)<*N%C<0u?jSs^5rW?<7kqdP^BY_ZbNS4c88v
zj;2)LkFzJ4q;NZ^XBt5l@60hululpJOy+8|s2J6?z!?QxskG7{^8dnJb|LiRaKT{l
zg+Py#t!(F<4@Y-aA15dEbcH=mpg%X%CGlbKRI-7)_n~6%B@u|ub%kHT;8^>BZvKoj
z0RamH+muTc9Ff?51&1>*PpCHmpk_#`dC%D~2Gq6XCp4>NW?cOKaU8&~N&e-lxrMak
z@9Q?nw+xMoMj-v?dNM3g<GsPVnM|n{CiYb#sYI*8;;#MW0-RlNXOUZz@E@_&owP#<
zk`fLtkFYg7sAM<<*CeP8>hoP!rj*BNgPZmn2Aulz^E2x-dcD6D3T_KBYicK&{|yR{
zdl53LJ$HLftd80G@@R@9l52HP#Glu_FKFl6XY_N(y`6Zz=%=3Zxx|AWlkpbXN8h2!
zmaTDjiX();*$Cq{lTJP$eYC?v{cNbJaHj*~WY!!3roFC@JPz*7o2P1Xw<`c2q2J!O
zn{rLwam%#JCiOOOK&r2`-Mx_b*4#QFz?={&(PC7wo+q$rt0`0XSqejb4Mdz24bJBI
zS}Cp5ej+#Hc*LN4O&-!PJ>>JGEneWkc>$I5c<;SjZF+{!2!+JhHTW!qN~hL5DtrMW
z|860MO<5&)uv_x>V!sJEgQH2+r@psrGjt69ydaU!x+2}S*6|_r3K;e#ut~L}s#SrJ
z2b3aP2e*nW-i(BsJ!vQh?^oq#*W)^Wd>*sY&9860ily_aPaI;bPuQ2xr{zZ{INq>p
zNoQK~ua^=XQo((=WIXW5C*wOf9*!mws(6hJbzU&sDC5(sCzc4m7(;NzwY6>(A3ftt
zVX;cD?rp!E4W1hpy0#@qPQwKS1`V)kG+yNrBXxq-Bzd!$qcY^~)ihZ7FIbUovAU0M
zLAPH{>`TkrAf<2F7Tx|Y3$@O<C{V!*WPTmR4RNDJ@l{_mS9XHB-S@?Qv8VH-9m|C`
zXnR@{EdYUKM!vaAcpO^EW#8UxCQ^Gnn3D-ZHIl^m#-!5cD<mky3EGI$4p!Qq6QAuq
z(9qQnZu!1;iInL39}3?5-Hbb%69v!(6Jxi6^i)M_7531nIRssyX<bmqaNwdxS6f1o
z7FC$q-c3Oy!!!#5e~rYe@6Tn$zMcigQ0`a2Co5Qk{ye!n;jGGHfstiQvhcJDQ0!G3
z^AcG)8fN{a;vhhDo3&PGzJVp5Z`4b3sYK0;30ZNUjxE7$4zLiZg`BK%x1agSpJ<=b
z!u7Xrn;7s8t@b23=aLJIdx-)<@`iLn<y22%?MKs4S~dfSwgT41LjuK@GQ=cZ+J8wR
z1MiyD+sc|1(S2z?Q+uIg>V6v?Bj0Rs`1m%p8azy5ls165IQO!6rDM_uI&FvyRh<b0
zjG$r;rm8d*0!Z*^Rq2bXm_YG5W*xNdobmjQFH|j&4K|BeLt;g-3!Z(}hab(6uTT5l
z2h9VCX+6?p+4RL$4g4hgUc>Q!qX_0NPmgD1f#uW^OK!_yu@ZRCdp<}!aRUba6ujY8
zHfU>rz*;Az9PnBdYfM7We>73=ZMo#5LN-2&IH?D^d3Yq)?Cxx;%fC^{g!I~8a3~K7
z7`wTNxh@3oQYBcQB?bAe6rdb+c9Sw{e%N-@x)jxQtVyi+_giY3sVwn{G^m$o>sNhE
zxmht@I~^y>Y8`d7oSbG$*&Cpi%Q4m-lX*Y)>&%(yj}h~%@co-YdSrzvX*K;yjP{A2
zkOlpMrje|0Mqm8H>Yc`9?o$9R)XnZS{6ei|isafv;t(XSJQDMYwNNIF^teLYDGkVw
z7*`b_Vudrza?n-!;8cYvKvMFBXRkj@&lt7qF79RqP5__I$dVT+j1IL>{#Yf_3xbBP
z=Ki3Ct^QuOl+^ysA;VaAHRtl{c15nm?dw3kO3vt%<3kNza0pf-C*KEU8wQ#z_V+;I
zDY+Snv<6a#w(X{to4+DTgo<Y82Qqj}JNI5Y?S6&Ar%^$&l=Yr)2@yei<f1D$qTGx1
zUFG*eivx_(26-<2-zsF~Kbsiiagxi~I77xKFptR(tAau}&^gBiM8C8^BVSD4f{Z|)
zLvL8cjgWh-)1KwDQbACj9Io5j7?zdp<pUuWPSZL2gk!QJ-_qN?ntfcx<`f3Jg=LJ8
z73_W1el12X-8Br;o3_<7D<_dUU2trdtcbFu;qYudhd0FIs7{pzF-VM-4fWN_z}-$K
zw9eQQe;T)f@L_j@n2PX|n#1kCIFY!Bg6(O8!RvbIjQend9k4ZHR-(Cgms%+6KY~70
z+^b-!84SD#T7ztV7&amceNq$eVSF##_VvLXrbJJH{3Dy;9ZFyHSJ<MmQL3w50j9JF
z%)FhW-^*GEhZ(`=rGW0UrN8du^Q^_|T}wZDOo&rRGXP~8#yS!Bo!TK&V=#a*CUS9y
zXm3();fG!u0a5-*z_y8Y^oY?1hhWQmZf`ijE_9qeJ+L8NBa{?;hah-k%Hs~-p2&2o
zqKp?;SlOtCC#nl%!l2W*)F3~4HTydXI1#;xo_Z0XMZWDXFW1&Zo>~0-&J^jhy)tQ~
z_il@HYYZQ<$h~8(Cn-2Ja3vId=21oJdOY8(_dcX)`bQ0T+Ii!S<>e~h@2f)=izGmo
zdHIo88pn^kr;zX<FLg>QCQ~eGCkG_bUF<RtJ2=vmiLZ`%HMIkM=i(-Zq{WcaP5Z|^
zq_eIf{me`+W51#p^*$DzmzFV8#;~ARBpj9f5GA9%j7FS$NrN%00dhHlO^2UT!aofl
zR#0b0OTt{YATyJ^jEp*rSOJ}Kdt&i^|10gRnW;cg`*`yonhOC-qolRRNF>c=!`|Bn
zd0nmuRqF{4#WEwB6*-`vLOgx@n?t$*`iu200pzU+qfmy6D`_~at#m6w`hO|hVgdV@
zd&cj0xD8<uwNRxGj<^>FhpF?u#0OV5Jx-0-n6PHDQQv2xqH%@hS?eK!$wncyxB^9L
zyAjzV*F^qC^z#6l3e+F9-!U;ZH%MJZEYBFAjFg<&L(d=`x{BtaT3%wseFX-&F+2`E
zE8QWaM_WKeaq)8QV$VSM_V#vOR;Tr%w2dfeB|arc!u>Q~Gp%e>OJW^Xv=F|hwzO_3
zGV&9#AAH~cgCLMcZE(!#yk6%XDO7Lu7qWrt--d}cgM2V0Jwm}YSuabaiN4o80ZrOR
zr*!DiOd`Vp_wD;ya`T%`A}^#5L<5J+&n#^T8(^_Dsea$Mg7XbH&C>Xf*$70oQImAs
zH+@;kzPrw7QJA~1$nla@7=U$H)-*)Ci&h|*x7-pM^bbSQ>`G?z3vuZy`m9co(kSfA
zW>pJ<Wo*FD@xRc|@Rd&aea5lORV*BEg1Bhz<>PM-sxWTYGk9Gp?ot$&7W`S$2O=CZ
z41sm#s|NOhu2OS*X8z3JP~*_1SaaWCg29|>N{=~bA!))4e>2en?3YDgU$Zg1Y$L>a
zi~$ycGJp(<s8uzC^koQbFFB_1kh<MMaOx#YHz-H1uS<?ALDUovZpI3yN`+*3@Y(?0
zssC0vjrroUnI%vQg~ZfVIM6V<6Jy2s4}yQlI_e{+{QcrNN(zbcrkZK<O}N#`#KwMh
znCF%56({9+ZNy>|cq2!+|IS$IrTKK`@c85`!*J_ejv@c&{FB*6ftD8Pq`bPV+AX-m
zS0oS1du5C`$}nP*p#g9ir-0?<383#fSy<w#2rigJF53Uu^r6PDBJE%X*XPO_21kl?
zb;3@*tyk0<jl^lqo55hZAPsln%D(YHA(~-uBcKat8m+G16M}atmgKU{m8%{Pi~-|C
zZ5>1?N0nZ0$~A5gcH>PndC_@9UUPaH4KE*#9i)~_bT+yut4n&7H9v{Au?<Xnl}Tym
z$<*CqnQvN?;wPGPQ)w$%Z8@eEGPWZ+s}_dM`=~S?5qeB8@J1wetSNDA;X~CQQhUr2
z%GMi|id0sQ=T4#8m~vn?ymBKsI7%#a^)1?*tDG2hcQ@6_Pt2O)3|UJN(>om<Od)}*
z26c(*rlPo2rBvnugkDp3GKU$8&Y$Nc*}<Z0@cySF3tWHR9*DVuFk2oa+|)vy9!i~e
zq*bIeVIzB9eX^PYjKlXXk|+N$LX>-!VP<uFTO-2qTgiU;*`(rWkYG{mADWyNi1Wdx
z6Uh|jet59*k~(A4&rE(Kx<*e^0|7OuW$f{9K&K<W28FgCOG3p=qM?dNFwljwjj!=I
zy!Dn&Eg_$i<5W+~1OZybb(@O9!88r2rW6Qm;6%FR&0r>#M@PRyo3<$eN$U=Ii+9$w
z^8jP?U)aOmG`M|I)Y98hvxmo7W}=c<OS~q2Q0O`uWX?mc=LUU;YFVjI#N>R{$#Mz>
z)aLtgq_dvY5J(`|E>XQ^>1SP41ggg3nwc@e7snh8vW*Qfh)nCca)LyN6<yC0+Yq5}
zNJolW(JKCq8v*dr@@i^h=|{#;MBW~tV9y?S<q%axfabyO%WfR+9GI|RnvR#WHqUX|
zDzn|W;BAwzkRUK4^V>%d7UdGqE@1+-^Lb5$Y6fnPe5{ulEvRqjhq1sf+i;NBR%~2s
z@2v5l1mGY+ZEBu%OL6cA;d~-vp7xjGKjIWU=UD$ofA)g8`+gv)3G%MkhVoN%1vv2r
z!U-D0s4_&P^L~+(R6;Vvf9xupJQRW<cDhU^7o{p>m}#1l*>KJ1vbf+O;P>N^U0O+A
zu8LuwQ(*<?nOk77p>Gj1$hRG={xyVjkt*9Z;?}_jxo3)fsW`T+<oJEkOVlx4t%^U;
z)T4cXEx?WzlUc9%VxBP47H;fRKzK5zx}0@9r*ol84^P?<SEA-he9Eh9b~UeX0SU`E
zVA4L=WG^wG>URXGl_1zd)~0Sz9uT0?<ZsZHIk(`X_&x?vD8>3a1k8<`jcge$r;vhF
zFXF3An^zhYEBW8WPp_wM*$H0bZr?@U3La(+?YpSsMC{g|ui<*uNI{ifle=QqFmK<b
zmt-yD$}JpZJ+eY(p{A#96$}C%kp&vDtxZDtGrrPx^<ei|sbcBHuL-NgjUC%1LvT=P
z%RBP!c}ifElhXy5vy%WiRgwSj8CTm1R0Rq%KsbIS9Y26{fRtGHwH(7_ad@PXl6nSN
z`{74&kk*{lE5HV;PakdR&H|9-j&Syh?ZlogFj~cbGKYHs5(dt*84PyzZ^mus-IF{b
zQIiHQ755pKSuwinb4P_zU9kCk!x^VaFc2DH%ihrFr2Awp&q?gSfD)fF%SiRst)9aB
z@XlSWF95)vBH;%%k`z%_-n@AJyF3qa6QKw7`7acrc$<Zc7}sp?m3o19dTbK<K~6#`
zC+S7U`p;v(969*^vv)-(i&0vv;Zw8Mlp*H)Tx*!hUY?jF?qgPC4}b9WDyhcD!i!*K
zAC7}7xe@^$s;?-=HdF+F(Sne1Aykk#buOGFw7l-u3$KmdR@9XiBVyel=OhfDojZoZ
zpn-BpU$S#ffNS^M(A&M|XYkq)hL7ISRAw&}fPD_(f`^pjIIq4Z%4Y~YSRuBZJKO}X
zG2J=m0)&K!;GGdxjX8kgfmd<R=Wpb9Balk((+5%*4zNpG#=O;M;?UAfR!ialb2~{r
zj2tHJ*jO0<eJ~vrytumE8$!VgQ?Pp-omq)CN^ckfLs;3RI9}ta#U&m`%2EUmm2_xL
zbke$Nj{(u8^=a>k805^n<bIywSLxPJ>oA^&%r)H5*LFOQmkyU|m|qhij5q+3z{*tD
zO+o^Z1S4n58H#zzwqZx$5=R?z)e%U-+%a?L+4Q8Xq5$A=l$sad${Q#+F!}c&Q0mW7
zd2?u=wjFTEc8c5@KpPu3wELb8_(of*F2sO9>=A5@c9nq0r8iyiakPoc{a%F(<83sW
zUad&l4|u}u&MtC-6cidKTsq<Hy&=LX=%)DzuF(vJj|Fg|069gG*I1U=fdIC6h$`k^
zn(nRqLRU~0+}D!{Yj|jKKgw!F{>IXPxoT*F6NHl@@Xe@3+l;x8QCpwi)DDx2IC#cT
zbM^M4Sts<~j?crKmaWxFoX3ROu50TdR+!@cn$pjXv$NLc6;IqF*P!x3!h-(`d`|BQ
zj$A82NANGP_H1*rsc{Bap5&&4oQid0up7=~(#=${#ry{*rgj6;c)@Js%}#Jq>1d9*
zEnbZlu=YRQJvCvfjx{Oz2&{_ZU`B95v<%5*1vS|yYIC{hq3PcN<QmH_c||`Qk3OGr
zFu53wtm=*U_jFTnso%&WBqqL9zo32b!-v_8jm~Z%B>1dlbGEN!M9q<pP3j*em6O$e
z=;iL=+_W|3@X~wZ%i!YKx}+OJF7L-53%d(A2BLwc>2Cwo<IJ@tsP&D*8MQ<snY^iW
z3p6n>bP;*6FoF^n2zo>Jq%xG<_ZW}u3w{;+KrA;PR18%&1?v)X{gI99?Dt$>DP!wf
zZ<P<r&rG;#QnC3X^Xf#Cz$`}Jt-kd6xufb8wgK|zW0$!pIos&P7fnPa<&WO(Ji*Tr
zt+(#151w+(eC+}groLc!`v8Gx<^I<9$KsKT!p$U|n8)SNPe4i^iu5K6GZ<^)UKYT~
z%}RF4p4Bh}A9ul_-x%N1!zZ|c<|Z-bDJDBtmKlct`JzsuEt3Ha-sL4_9(ik|DDoj8
zI?EY2a4}z<Bd>LzC_@O67AwJ@RrzugOLuKHO*X|P60g&<Vv!d_Vhn9J*ILJt>?58`
zVy)S&h>=7xkcqsUELKnNuQIo%jxPJ#dyoTx*X{j&0ozC(I<$%W4$>Pq?p6~<p~c!8
z&(W|@lExcql@#5&aM+o>`^Uy#QFER(@Rl~XUfv<xAo@|>*1eiGpy$uoI6%Zq&0y~6
zn#Zp7VADYB+oSZ^sK}KK(H|O+*bMzEe}BIrs-}dObtUKZO0m`6W&uVj@J_c5;t|>-
z=8m_ydLmQ8>xXD)27!9h8%U=ka3`V^GH_QW)Zg6d9bdDquZ<mM?R2Sk>vfw!rK><o
zYJ10_O8%x#DoM+^NCELN=H(~+(i-=ybL||PW;8k-w)ByKKTNHMU2LLGCXN<dLn7f$
zB?~qksi^n7z6P48cORJ^$9eU;wE=PRO#PC-3J>3|YdlC+Duqw&8MCBXjma`NKy57d
z|F60spA#D80x`5rvN&y#uc;`3tmq|awxBuw{orTY*cwgSv@Ztb$?-fpx>>5qvJ_sZ
zL#PQAm!SZ=mr%`58?vRc@#8{{BPVt@r4sqBf|ucj$hz|)HKY{vo_Fx!Q~sX{rF0FX
z3fe=ImC4Dci~J`)ZIgA&7{-AJ)*s{E4p&Ws1FS)}X~;55M51YJ!QFZBw0A*kb-rUY
zW@z1ixw6vS%f*MmAM2pid>}G1ok=hL0mw*r$<mzVr{Tn}CWAZMm?2c?A{wS8d``oB
zA>FKlYIrtD(tz8FQi_{>TR`h3+^wL0ZMRO(F0+U9C#p-1j7@*Wh*}uXb~E|GFOQ3;
zm#Ka(V!X>LQf`O0U^1j5`Yscj77g=3+vmN&^q#KyGeBnlat~0tBw8;$!I^gT+r_FI
z??S2~Y^E=X%2ZVby9C`tUm4M!vUyMrz=AHHWknUGf0?U=N=1NbP$%6@$h$_n_eutL
zw-=y$lspF{XSh~k)J{F{2n6QY695~U*E^DKsgR!OQz3Zu<0_m{0m!hvH_c954qZP!
zK`X>GB^<caBZ0I9&&2#9$$pFg(uO-ss5AgUwy8`ehcB+;HspnsOnH`j87OJtN$<fg
zs-%Pqbr%y0r(ZDI;7UHrS4~t>Kyrqw`f;bk=IEMO@moh>p&Dtwcb@4FTd54lXnA!K
zV{b~DAofUImVpGDVlx42%s-9`4_b{guet%e?R$Qra*{T?$`jOBH~2)_v<1HI9rYS4
zvisJ<R6Z9Ld+|KdbmBsjs3tSLy=y8^rNu#_w20C^f1+psx8vePgV!{;hXr!#4q-(L
z28yVu4mO$}W@}m1s`*cRIYPQwvbW_nxv87y<8>y~zdkVH_+~K)*c*GzL9BZ@BQ!?}
zo4tyU&7@>_N3A$t02izn33$a(@|$;z;M#kOfQbR&^UCc20mi5rIXKMSiJYX5bjgBu
z5oq(Jdg{Ao+%(Dg(nd97?Oh1eYR3R1XXj~4hCZ`J_#+-S)N|f2#J>jxR1AXbR{r&e
zW?@A91hfe2!nM0&;<@)|-lA^18R*$!`S&k`r|c7{0wrKEZd0H0h5a#K8$==4(C}#d
z`^Y0F4Gy|1Tot92IS7T)`WV`oEmaVh2cke5L3Z=vw;<COH_|X6-3Jbr<O5g1(HbBN
z&1<0SPH<tE`nQo2v9C%Y=4rO?%2E<hY3)B2kiJE_sDMf2RL5!O@-#vB-ItNCVD;_P
zLz7V>K5oc9kj(JRTA5qh<wb80x;TYKo)8T}Rpe;i*j3n%l7jh3^`dE$Mt)$8o}_Fx
zNF>Crtc_F)Zc_5))-JMit0anFa<EqBacg9AW)zkr6fMuVedEGxhbEdVR{j=avN3uf
z#@0b5j>MayUI-RPv%QE+s8O9~R6)T`*~@6w-N=FDP7}TFT?<Ml&2KM`e$c4bg=^=#
zG)S?3ZjZiT18~=rPh00gwZ1ls;X`bd6eD!1o(ohZj>yos7%3CYHcA|DP~|`Q5njpd
zMpqN?#T~dib`yUzXOeZn_*WeKIeS2zCimljY1Vvf96lu5piu?%v68i_*Dqb6OTfl|
z^~ciaL|i*Md&%0=Jh}(Ww&6DV+Z|aLjcS;Fcec8N1n9sJQKWcB$fG0!2AS=QxvETw
zofy?Ob$6lY02y@aVKeaJ=I<u%aZEn-nl3}ynjQv>Utw99kX4+id1=108lU{kxi_KA
zk+*FWOek7oP(;E+KIl4muiS^u6(t<en(~kb?_<p2X_>(Aj?L!37<pTLH%YUVX3&@Q
zA5O6+GdEZUQ^;#y`9Ya%`KqFxuo~E5rXN?d`K5=#=S0d=`$U(eh+^~p>Hhoa`fq`K
zS<G^tW>GbLOR$nFx7?bco#fek@zLx&g6h|C3%FL-wVNRK4v<&;s&JU7ODr>J@|@2o
zrT8})AXc}*Ljw0^7IjKuEUX>E9FH*3JWstVRze$>`HOr#Ah-tm1*Z1*sx>=7bZww9
z{`j*MN*ZvG=_Hf^J6gC-`TJX}e;+6i0go$K_q_ea)gqF)!u9+)a~7wMesS17Jhr;<
z7y8)qKE@`Sa2N1fi;+C?HF97!^*$s+hgbg;mhF=r#tkHKTPxo55Jz4UCKHPVK+JY+
zY@e_2)TKXIX#H~fUT;VfOAbN^U0X+D$$&#)Q0sNo+Bcj1|H)Uh*XX&Iia1pmh1gFJ
z+n<)@(G=FtleuV|8&_0C9LF59<O3CJC>B5$ebb8gZa;w7RG|gfVybtSbGDQ;e~AZn
zQU!Gtlgy9cvvW!B!|GYOF_$thWp?Kl!?)?FQ6APewu~K^Ar3`08c*<$F2qJ5a7fh4
z_m1^&++na3O(~N$fUI}<K%KEkz{3=9G1x0~hBGM+jfVEzDM2E&$SMW=!R$&fpw%Ad
zRQm-@@6p;~PYKBDNv0T!(*P+ce;<69c`;>~r9ggvs1a+;GBBQXkf|_KcF=Y1FsM6P
z$KAQjPFeZQ5}nzDjSAhn!^hjxC2aMuN;;88#X<xv!L|_kYtKb{9aw|?08^?g)7(m@
z!Koo(I-Oq%IW~9t7kQl!M@WTE>8n8`vy5eA^Soc4$b&rUwS(~0)oQ@^OPw0f7j4kK
z+r96I4GImw({BizorijHu<7$Q(*A+hr7~X>tgXUDV?a&QPZ{>5je?nANW}xUn}ady
z`ieO6D2wgsl#J$Q@+l|}uxPJPBFkT1X8F2Ge!?C&yM+s~-Gs-SF@~`yr`OKKz0jM6
z7f!{8Qttu8Kyx<?BpFgCYcHauWvdtcQl_=Oc=ddC35T9XxoBm=@k&}n1}!%>13R|B
zxJ2#2M75G_?Nhw%RYv~BgDZ)f_Q~j7&5%yI*x<B&pB$hGQ~PE8$JCu_ks_-ubW;7V
zr>iT!e<CnHCawrBvrN9{9g76J3c_7GX3Cz7vHCl*!8@$UCqi_E9~2UwTO%p`$I^q0
z;-|tqek5WWm9EMXuTi^g&UCH3lBAU=dixFaqyfT$?3Bsk7%T{7;+GMYH{>GE1*UrJ
zfs6k2RB7+=fxBK_Xb#e>>DZ=kr05-TEDu>DqwJjYAX;os5V6HP_BYr304ZboWtCK{
zYe6S;=)glt+<F~a3SEe%^K<dOFqPywrMG+{B&*#cs5LH%O?iCc*2)xF0S)$^VqGUs
zmU=!d&$v~b#7Q#zbYfCRHTezX&LC@t`0IinhP=Fz37et`BF}xB#71}Xu}<aT=nf<P
zptEQCHbzpJS=FP-=-`(9+;w)~*Mkc^WRyHWSiIf<hKe1dbY&QF-dPrPoYOR69dA7l
zXW{AwO3$p1YFBMhB|^Lv6GCRgisJ<Qoc(T+`jmGgD76Bn1<ydrf2myG#x0@#IW-s-
z$-UiN3;H@x+4f*o`BI<fe*-paXv`bYVT*#`QXxpoy=44aj^}tMHGM^5hQBH)Z~qfZ
z&GS5u#bWlfGfN>Hw{P|B6U!x_zObvww`l3)S)-{Prt3ExRn?<h4h`0ecsn_8-JjL)
z>wi{KJ32%QkhR3-@=k&%uFlz_Y8BR@r2+h8IG{TBbSn$%C=IJQP`KaPEQ3T#6{41-
zWUy!^YM7;C@ve@{RhFk*J8Yo+N?uSI<&CCOx3&4bK$W(zzaBFVrlMddOPxYQ@=UxS
z(wLWK)mW90Ubj3hbgKc{xwvVcay=7+3pFToTBmKO%YVIssxgXFF*TE<${*Q?6IG0T
z>y`eSnxJ15i-h+5IsF(3Hhs%IDG4=TrYw&o5$rgkpliF|pAxhkT_%@EWuPlfctTSA
z^FG=-gLqNX+f1sm5|%{fLQLC6jth|BN*_OEV!nvCPCTQ+&99LonWI~p-OwtU)e^vp
zZ5-OYH^T+Yu#9sc%<r2O^xsbEtRCt*th*n?vcpF>gJ1jeiGFN(V%Wv6M6_W&1lc9r
zfeTQ`Tx?TyYFuP`118#s85k~rl~LDLR4x%fdPZA@7V(7Qm%ZH95<Vkr=Q6%KToM2z
zvgj4WWex^t%%z$IO@GfutDi$gJvzpmN&d!WqsCo(%#MpU6?REb47Sqy6HW5#ip8Ju
zfF{@*9Q3*C8*8ScpG1OwzIJ~@KZLtxv&tfsuT(wlw?3F%ShTveGl7#NXTjHdYp;&S
zM;=$<PFv{n8+2um;{2vv^pJ}%z~8$%MBr`)D2>YWhI1$W3&~@N;u)QYTI6g5OG;&w
zg1-KjK}dssdU+Z=IFq93s@EW?^5|4?RrfjFuU2Oaj%@>h1^>@J#x>T=W{eJe<`ATP
zY&r+u;BSIO?Y{^^8&QjBVaPOB_7LI-A{GBR%VAgwo)7YtTK$MAT6m?USkc||m|-ml
z@E_3a13~Cy)k@q94y)iN1~_W%=l1Agwph|q&qY90XLJcmq16R~%)Woo2#YDNl6qxx
zuXd2OVO6MJX#<e}!y@j9<k{H}?@mb#Eg!|>u`IHGAQ{0WIBF0k<KJaBvS8HaP92~-
zZ}a4|jE=A*$d7@_tQc#P{GhAz843jHcl>K)RI!yX71ZIz-=d{g>BCZ+na;w^0QNWR
zoXrdv;!d?`>ga(2?59Mh$$s)qTW%_7N1cLgHm6DLT8LA_HPqLAZCwSv4DUq=SbfKu
z?RwYVYkWV9v*Ss*W|Hj80x!)qH+O}V2^p}rza%rz9Q?x0256zUGM%-c2so!ii1-iE
zav(cU1%DnWO4z=Kdwvqa9_XZR;~OA_FhSXUf2~^#@-ckewqMS#w|8)wj<IOme-cC0
zSl@`wu-nB)Z$0q5k`a9F%oFj!Zw@RP@sV#2I})yLP-dG{a;H)C=Zn6w0odXrT|03G
zf0X-GK~M$s9$WM?(if4L)eCVxR1)G?J$uGT75c;6W!g@Shg*7htWtv^UaFzZ1FN1Y
zD`Avo6GIe3OWm%Xv8@QxQo+W|$`uF78?fBur;~o<VD?PpMZiEZqlOKFc$IJk1#`?P
zdZhq_eR7wo0+%i~95zIEGx~g;)Df^Dh1q=iYJ_tcnHq&`u~qYNzvPT!W4OblVWtkB
z)$9%djIcWkq4J+BNjIT8$}|w1Ma(nZfaDcW{&ZL7-t>ZSPk1`^pP`F$$m1!cbH8Cp
zUthe5q2NMN<GbHJJX#U6_y!Lh1;FSrr>?b1%F4q>cx~>(wX~}RCE&yZ^`REM2?tko
zT=(bhnrdJP_gv^?hII}%mA3i|{PjF&>acExY2erL;vk{l#v}cALld9yy?y@k;u0^f
zj-lc@Q`za+hT8FKWjazZvlNC>OHHi0h07$P)qnMqF4ll}j3-vOTi)oH7C)y|bJgRe
zsf%K`cRnaz?%~|{3Aa9!{R;vy7JH9i_u=m6x&e-(6~ii=Vzc#$VHz1cFR8uj^>~bn
z{RFFMtZYS)1Fnjz4-jQvbc>|BPPybrOVoyRajbWBSAMvq?p8R$F;?ZOA@KlgKsD;z
z-PJZCSN1y?oEH~Xl{(eDL#zckX4#=lp}(!wsW+H|K4cy*QTsUKHO7BA@Pt2&z0c9#
zeecZ<oKUt#?HV$BX@YrGLwif)`R+f^yzH&ONjyWy!Yyl+*}8?JhG8agY>stM#GU#5
z3Y2OCdcw&4gzuw)AMIlwG3bskoOtWBE$Py0^jokOQJ&f~u)QHqh`)$Gl^uG0!D%I7
z9dIOXXWh*f>&DdfB5Bp?gT;3{38oypiqVX$9dO-IFPT?7OO?b`MU>RJdxzDRSCN4w
zKNCEkyZJ0i&lqYomnjFeIH&;PtbX&EmvIP*FfIVI7)9qE$@0i{VB2hi#+ZDIK6-}E
zAb>D@moBmY>4hNSzzQuaS1R*NKl-l&wHKirpBId^&Xajyi01ftT#cad1$b|yv7|Bh
zkFnug3|DVCEe79_>9OByw_&{wOxI1nsouD_p<pxR1XW>L)5wRFPkgB;dGhf1Ivje3
zMQ}01bEDc@6&zMqD8@AEzR2Ut%9%s@Q4_Lj8xO3UGIhVGObB^~%59Pf(R)CVf6Np-
zd3oxjUS<{;VvqZ>O~@4tq;)C+A~?6!3<|9C>7os!X6^rQxz*RqKFQx{2`o=4>7Xg@
z1+5QUfNfra{&)>nt0Dx+mzi~r$^BVuLpD#S#2^sHVBo=(K_5cD--3QG$|T$2NtFhY
zhU4zuS$+@i@zz4l4FVlajLHub?QbkB6g~Wb?vwZ@q$WP{+IyhUMc9`m8Jf`Hl0g2f
zu)o$e?AhI+15cOYG3Dp}kQ}N^T@b}dlzcTylfQ~VTV?<R>QFG8LhaX|-BGVQ1-pml
z;U5`lqA32cg4EU4O}pE%(gqZSEVV;UfKdFqfPw#D?`wrrVIy$rHpN@b2WxC(A4i7>
zH+$Cqpc^XbSia?()t!hnQHl={L7E{a9TRjt4biq3AE_fK<G|AFlHea}C9!mp7x4B9
zEPgJsNn|BQ2Ra~xWu1;f%U{U<xo$8P?}6;mf<C!{tIaY5Yh&f(*ut0(pS<bGc>V<K
zT@2?kir#DyMFH0v_6Q3_HUdMGx7IxN-bxH1#KLM)xK$d2VWj@qZ<xiaFGc}(@xw^(
z=HUR-v)1g}&8E>3T;%40XHoYR<2=FdW>nZa?!obG*saiadkNFnt4orx<gjt3V~yx0
zO?$aHV8B**V1iap@KC(~01OmA^Fy{X_CA2ia#5Uh3qJsfv^E7C1i?U~Af=MGzi9Kb
zx?#8w`8F_$qffV@FgA6eQhafL29#G}NvTmkDuMAZyj;;HIbA!*QQ>KHD6n6qnjRtM
z_FAaZsgqj}e#J}vuU~LVZ+Vmu&Jr^-qP<5!?!;4d!OS<Dn8JIKSC#@5S&fa&wp+B;
zVz;YEUcUcjwEw{2KnQz+r~3UaWI(Os0H9J}%JAwqba^rc(RzpuYZyjpHE@%gF;k+F
zSFw=SU?ACT$V`Wwm|as?awwkyu_x63s%W2*Br9l;Erc91l*(*M8uedB1*dZt4LKs?
ztvF+)t{$&zGod6sR<Jn9Mb5(N(^mfB>s4_O(tKrD8*dO0{ukZZ-Zt!2%2|Gr|97(9
zEofC|Wa)X-Q5n=qo>S@5T3Ka^a0kWquN?d&%IGpxQv7Jn+t$Q8ZPv*#$gRV@w<~W2
zA9E2J_tFDd{c`6}q80F|%5zA+BOu=1x!KqE&M0(g$O;d)owUpa|2USXx4Lk}dR!+@
z7{wV=K}I03Cp%c}z(KNDk@y{cG=4*x?W^A;^3f?F(0RWLukOpNUvh$N^T~>wJOUqH
zG&J0do-K4ADHhJ9;?Vm5`HKsxoCI&Io$=-E0x(D&yT%NqIAh+Pc}y{Vqd{<hl>*4a
z`&18s70mo)y%li$>^tvqlqY1fT6guT*=9OJLgI{!$th>90(#>Ve!W2i2UaNX>?Efh
z1TG9`L~fXBl{^voG?vLZF<6fFJfzy?^=OS9@ATo-NQ6Lw{(82IpJ<HE%5>FDC<^M(
zbbK?5^N|*5q=S$@wBCMe+GDPgVcU!|Q=Y^8uf-o%a!E3uTVquu(LGlaGKR^y=*;|{
z8v)uLvo+4o$x6P3q2M&FDgYiiC$!<p&c~QJZx;<hmJ~BGVME5f29Od;YQJ3hN35k#
zo(l+bBU_UFHyI@B)kaDRI{H0R3le5gVE(&uilL)HMW;Wn8>lm`mZ+MW(UX!rB5Tbx
zNYr~q-M-~kY=^`azJcA|irR9hiGQfG-XFB>G<OL5qvMqVrP27kdO%wMN|tZ5VsSr5
zmDPpFHBC0Rve!r2S~lFm<dTWpCUF^AVd)ZW_WYaJ*oW96=^Q78IpI`{d=tIf+Q#F*
z@uUjevKkC>fYm7QRBc8>=?aEBDXv&9_06ceAeaf$P<7Z_Wd)o;t|+VOw|VD6acGWk
z`)k4CYK+ZE-wdq2d~mUD^b_IhO6*NMpQW*YSSxS_42gbi3@W|r5~T()$CJmgD=E=%
zVMQHS(p~i*FR-O5F|Wa)+|o!8CU3D^>H;Ed(bX)}0W#QWrVrK6(VF7A5K6+Y^L=HO
z_!%|vvV+uIb)pe1P9me`+HYCf%OeRm1O^2{V4QNk^&cL;kD^N1&^>s8E`1{aO~6wl
zjo?lTp`d9EHE0v=Dw*yT=2K9C!S$&xS{ya;Bd37g)U?gR069R$znf;gRnp!h%vpy?
zerbwds`jCk;Pk5xMTtFs_q8(&YcHyv@EXGR6Vr_DEz+@E-|!x`;d_=LhOzrQ8&#82
zKhet4u77mF?~Yj|1k6}zXbYG~Z?!x(mx^T!gBIO8VCk~urghJRCfXyNgxb;P|L`}T
zEYrr#S&>h6z-(b<Z!g%YY;uO~YvCy=Se+U5W)Ez0p@#${-u>V>7Ed~ciZg#T6*`jR
zLzbXmrGia#Oy0R*jcus8Ts8Ci^*88`&_Rt_IDWHoL1vP~f0sRfrr2?aaw7y8<f}by
z-KtWzyphB@GO~Ffrakmx_uiM!^ig$pA=k)26Pc1ULM4225~(#cH5lCx3r0zWr&Xib
zkAv5I%#}%1pu7nBODo9<p3N^|7wrtIX3TLtyQF*cm@bpIg6o{rsWaEOTCywTp4jWq
zd{1XC0?$w%t%-3igYVOap#Gzeb^g)dy!?BMjeX62#cTc*sHVx7vRU4&#5bnXDc))X
zUEU=x!YmU17nZ4^Z7W<2?|rf9dEh>VIV9o0^>tK<sbbj2*yG!}ABm!pXU+O`A^L}*
zcug$n&^j?$VtHc8VG?X<kZXs~)qKT`Z@*lyKu9pJ_56CV`#2^p9~e(Jx%<URJ+7vx
z1SE{y@B+9n^^?ZFRx<$tXG!j(9L5UDEB7z7uIFqk@=>t=3pIYxQ*{l=H(VAin>}}>
zC0zzqkFoK!<cZr`9jZjj2!5soq;ZG74Z~_0MN3BcDbY*jL~%U^$(8{Gaw})2??HaD
zX360*p?3l@Q?df&y%<Bp%tEE|Qh7;l*~!kvuWx6dSXAB{ZHECz+X;0a{h9@C_wA#Y
zG5_A~_{*<L{m2jZTd@0M)?v(k#g#7aCy+YTeNp>`hmFDkga=)QLlf%Hh{_&C@iI6k
zSUTsC01Y^!#{o$#cyvAYJFY6(DuPX%m1))x4U>N?KD)5CSjc|<-m2d==;gj*dKV*i
z2@z1NyW(+G^6KAXZXUSIAv64nmQ6p%a{LO6$<YVc%aO5!*!nPBoDeJmfiC>j{3TZn
z5$lvFXp_h$Yz!`*WJTV_%V7znMey~jv$e;~t(&t0mS()<F50Sdr_Y2xbcPKCL-N|w
z5xmS7%BCHnqoFf6yhNO><j4waJB<sUSu5A<VY^g98N`<;tl(@$37hw{=vylrC2<`C
z2pig#)luRrL`v`bApuuk&o#Z~2RDoY(|Uc}X$7*oVR^yeQ#;xhb*jHu6;jK9D5^j|
zj*)amiw?LAnMV8qSGrxA@r3r{Y;Cp4f?4W!K`l2+n}D>RXPeEJ(qx|&c>WPk5`T@5
z%iTuS-fpb+rT_OQAmoN_&~T&Csxc|coS~kcZTIKij7J)axf}k;ls1Gsp>9<Ev>Tq<
z#&E(f3hjzYmaC~cU0o$?9(Gm8d6LT|bI9+&(sPK@-aUnZ8Z77330fn{IZJZX(HDkm
zx|fn0p1tz<x|)X+EB93ZtDOyFa=g_do$8z74vbSvIpK!kO*Qkch{$_R@js>dt7Un(
z@sJ4L47J1o9w-Oz=tT#eqYz<S6UbHEB)I<S#z{UI-OO*{%B`?o@LTBD7=pBTPM-vi
z<i_La7=^`$UkolZ2N6g0mCHKS+6xl!+5bGUGyCd8E$FJP@5Nf?syBq_5i=NxCXGPk
z>}J8S1jD*<QdOy?&bqv_1*oU1QepnBZ=?~!#ziNFgRQXt`{0MK`ww1JzB80bP=)M$
zwdU(AiqA6Ds`yfb0#1ylvG^ZEmk!`^`YjHOcD%4HcHH@m?DMFN_yYb>>Wgr5uTi*Y
zBHi6MQWVd&ba#v?XUtMDP!~WWy!_I8J=)zwXvT><_$EA*;4x-wG91{By2(3cwlRO8
zs3E`MR=#P6=7(Z%<ehEVg{0b83n&rwxG%{$N{OD1zM_p&r@jUg>buJOI(IeYqbYFr
z4f*wL1KVco6oFC#s<6b}{`kgsJ)G@@)-OC-1?N1q`G?0<l#r8#H5=oYe%^QW=x%34
zyrTs@=v=ZS?z7s(h6f?aW7n`}4qkHejVa<+?WS>1%pST$3{0bzvTHkp_0_2;@p+Z^
zo5Ogt;z!istET@$goWg{`{)+!gV^kXThe-pH&EX|0a#ban0L~$!jCtFvu^)CqN4@*
zUk$X2|76+q`xt$2PX?JA!$2xn2Pd>U*k*H~MXGyGcK)#b#U2Ti@ytdra%XBRHXXIX
z+y~%@{be_Hix`7pDJP#+w0DAp&WP&x*kJE#Qq+dy9*$;qSPV-ZvxLlt81)+Bm2L6P
zFl_S0g7sz6dIQ<ceN-9LA`#{wrPd)08s5!WD$*A8|D=w+D8Qj|;=seA=oyXT02=5U
zT5&F8pWlUG_sLWmg>=?CwwY2%&q?yL?EOuaB*eO0*9f3tgYzF{whXND8hs24{%&}S
zQi2BqBogRla<3%+8*@sPIpJ9H<D+Xi0hV>(M2-mktjM6`g1sbr7uIYZOR?dM2*WOz
zFn(3~Yg3@R;TZMWkrj)xpOjVM?#l^|wl%w~F+Dmykt&2Kt)|Zv{3>~3Ab+?+kIB_2
zt}@cxSs_2`WN-G&Wrgu^Va$mx1~}LY<(c>zt%wATj@ux?6Gl;5&oQ7n0-%KGZv;Ef
zN;txnw(up*-(#U*CU97h=OQ2Z#z2EcOzj}7%zVpgCGH=CUn7HDOd<zYrIJgoS>qQc
zS=nunvOuKA_2&CvCz*}XTwfQw`3k#q<ORytrDu}K^1YU+F(vxWbE9|EkS)c0HFa0o
zWIDjn5nHXPY81P}87=tj>QNo1z*kz(<+}fY956g_Ll8(_5&!VA!Y#S^c6AHATKr{v
ze$>xqJT#4IYAr1|w?o%513FWet8v$NS+i_lk=#(7$xU$jVT?-Pk^|Zr=}v^Kb2-t1
zs;n?sz#0zey9|&`r|707Tv}H8<n%u5H_SIKg8&~&g+pR+w&Hr5yzw_bkJN~nl%%4@
zv~yQFI<}ii9GHnC!l?3*A89p9rJMTi0|$09%WjLgTQ)Q5I;fWS71wX>h%1=F@0Eu(
zFXcPzQ)l9MQ3N$DX!@F5z=5ov;(t%17(96hm@vHq>@jq0%n`znnqFo!6@f|_V@a!=
zo(jcu2boL$wdD&74eN)_fb%0To@gvP$CIDB4(@6c@T;!=mr!Xy@f?m0E_Sb9atw{J
zims2?!A)vJJR$7p`w1VOR9_4wu|?QSBstf-sG^{Br2Ui}G1HrG_!{&2H`Op3V@*;I
z=2lK;aqcQzdqSo0_~|c<=O0wTVvByn*V7Q61jL{jl)uM15ueUZ3tZsyc~RQju2?Di
zBp^P+>T?KeQr&9E`E2$SV(7q=^I{I5Luk2E%$8olhK^|%<XMzdN$PE`SU=Ur3S$8Y
zB{$n5p#m$eQ{TJWmPSd09G*I`BZt{(Hg1e`*Lj>0tT+OZw4yx~py)kr+JhgV_oZ7G
zfw2IIulPIJ)iVamS*C~tuic6Z-M=D1fh=qN*hl6~|7jd53e+xs)NfX!_T$}yn(dD3
zb9k6M@RVY~uWmm*YWocYD;V10aV(d&F=9$O`p5L?Pcpt^y<d7p!%DYAgMr<p79%Q>
zKHERjMo+QGeq^8w4(`Gh_IDA42N3`?`-^*RdCs@cxq}^Nq5*DSvA)&%Vd8YFwXjJ4
zIXHj?4Ua)^xfyc}&GO^GRvskflp+)tJQk7A{g(^w4r3uJSp5v6ZsoF`?uy7!*kOs5
z!^hiIXPtNuguFjz)e*tqZ<z)`JvjqQUy0>a5(1c`rz8k3^cGdX#X~6cucu}X4`&Qw
zjL1mgNqS+fG*RWGcJ~451W!u5hqz5V=K~Fi9x?=6SnN&Ck*(Gkp#paWZe7q7-Bmxj
z!Y&%dY~4KJ--5|n)bf8>QVV-X`!y_WCv#Fh%1x`Mt99g>zu4YGc3nI*H5zw}0)4h?
z|3AiH^E;!!jUN8JO06H9Q%V*1FFc7=f<o3#M5IA}>&cD|lJ`c#W5>xE?&z5ExqIvl
z9I=6uG&P3>)&9%Oj*cy5SNIm_fi{=0`bEBGdi+{|E@(H#YZ92=5jbyaR1F{OZx<H+
zsWh+J&k0i6ZQgKh9<ll@t>*od`h(rm@Ao0=sjw-ML0cRevx6fws0naOq|ZCl;C?<L
z8$VDBeeg?4qLjW^yOf|ysGV;Hrff|TWCoHxBbnvD6ey79d#O!HKj#GG9ugu*(|^AF
z*NCH%0uw}8CkiE$keU)vh~2$te@nVK>UILT?!%={6INbTm9iLZSc-`w8i+6}g4b%N
z-{>Q5k{(93(-oc(<(nnfcf>VxQ;%w%?SJq?In0v4?ZXK5sfkmpt?riAnuVMQ#7yoF
zc^_ia;UN@8T&DB6<NqqVN1{TO-)-OMYF@Z6vGkQsA|bli!d$xLS?1gXDD;+D-R%u^
z62|~`8V`WQC0|Mi?TbO2G%poyig9x{cltaE?NZH>^s*YOeNgerOL0y`ODdcAsF({=
z#WKRQu4F`yATiZ7VEBvbT}+M*^40*4u+v6EAZs-9<r3HJA_ZD8TW;rH95?D7%1?#0
zX*ed)iOm<Jz`l`iB9lS=+j%8Ruv1fB$i|%2v<gJlt-6Su9k&m{ZAhU@Gyr<oK1R9M
z+tGQOt6Y-6G^wK^G72eBBZoZUush>I?Cbyb=#tTDm9WeVwVo^SVO}F(TJzbiN?-c3
ze@&urCEK)j(2j-2O0VN!J&SH2&H`@3>#}I=Z4I$fnSDF8m=19gu^PD6e1$Bs$`&F#
zwml4n^xdVp@d>G0490pR-_CXpxX<SIYufF>t7=`$x{LaO71`K1<S#~V3iSRly$ATx
z+ChP28}q#+@wle8^0$6)jO5G_iN`91O>4tg<8e#HSth@)XOV5;(+*u3Gs=eiu$3eO
z(n=~Yj^ol4f;Z3qvLPf0z2iI;?6Ixbgn$y2i-&CHZxSx^<MygwA`q}nWsb@1HzYT$
zT5N4Fj)ggOE(YSWXPv7*PfH82C=eq48|dQ1Ia`Sxv2`>G6Y1CtRk;P)j0L1!8DGGG
z>+fQJ?toFcw&FqxGHgrZa&}|Rs}Sa#FDyo04i5=#DD};{H_wR#eEiuLJ!LJ~f&%@G
zHiyEbbb+VBxWlW}`@PP5@f}=~d;}<Vm<wU)G#h1Vj`~Opov3q{7pz`z49im_qPBUf
zLfIqp!LH--bsE~M7&#<4Ii_%?Ek^JurW)hVcAH7nklg=#4Dj7ED<#bNI*Q|-kIyT5
z>V>zL>nhGy!D~2I;le}=>5B9eS-e=L;?t`ELi^O(P-&V~KACTC?1eKh@5*iR|2kO}
zoK&CGR~_1rG@FxnhPE^CQHg&J;HMq;JR8<W2!q9JOm)jN^@ibr{NRPawyI<Cp962w
zzr^7JwGfSD?S{r^vXvMJ7hlCb5VpvxeM%Nwx`wAz!!M&LXiHuMb(WUi4I=Q4apwKj
zvT?x>7GpxTMUk!K+SR#M$24>)o%4}1@miXhg}UPG&))og)Y9!OFe;g(9=oSt20&9j
zxzw$T@N+7qlLm*0T;_7t**a*RP=m5y;Ja_@+uGg2xAH>mCMH6&MpPT4-USMB|GdL;
z=kuJEJ=&M)yS?}$rCO^nG|*Jhg&pxy$TGe?9*A8(cc#}jTUDPau6LC8A?MWnEYq%x
zH~2n<JV`($8LpNdwG4RoOB|Ntqo5O6EDESIe7(!k>|#kT&bnqCZYqU*o;>qgeG<`!
zhRbEp``FenS!#`9sI}c!iqi&J4RRi&mHLKdwJAUf8pmG_EQ!#twq4cFb)&k)?S#h^
z#Em2#(P9}l{8)1a41pA>wF2T0P(tw&hg?VnR_av@_&1Eof%INd7o|UCJd{G-qgf_S
zLd9`1d)}y$#|o-}&5Wj75yBF2HjO}gU;#xVUO9PLt$B4qv4Gd+vlkCY^kqCW;3!|H
z-(z(!6ho(iA6z<P)O-B(tAvYFOYOgo;Z1o6oPO=lS3mKgm@i?7sBukC8X@5+1~_6s
zEm+mT2LoiDZOXqnU6y85$yvAh<|=LmKC5aDw_TCjVSJ~9zt(-nm2JW8bJJU!*93aP
z*=tYG@GY68A$jO+J;CL=i4$L7ZizY+I4XLq1lZTChkf@aSoim^D7r^D?#Rd>$tOVk
z^zj6?=O|+`Q#YF6zxi#1jxB=^bDcvcvqq>+4)CkWWG1%^07GpE0fI&5Zz2h+Oogl_
z4E^+-Gm*+^@zcZI?;h+Ks2B@fNLbzsk@X0wDmV?uV@-QApG7uD9^}!F-l+KeTPHuQ
zMS<dnReaR9gaM0*OQ=p_=Nm3S7q?O<hO{f2f*=D;b)-`*IlHdXa?*?GQmhHQ&EvVe
zJpi;5TPLaT4FtZ@B05g8LOM3gcMzJlsz_SOgMd)7=$0}it<ZD9LTk^F$pZ20tAV_t
z@e!jSI~0TQ;b-osR8o^9oOm_HpbJ~;u5K);l76PR?Mu*mUNqZD2QVc0vO+)O2rc<2
ziB~lu7dzN?RL6YWzLTl_;#!UWS_UZlQ?$jG<q&GszbUB788QWB25p|U^VC4zSl8o!
zC=J6MV`)|{{DQTZ2NL@hLAY2RQJyv8iXJILe_*PpC|={$XLDkQVm2wKG^ziHQdx=@
zY<torPH4_|(mhy-Z%9(7w$E5zO=;4_?Y+gynst){HYu;&y;Nf{#Ygo_I)kJNq%F?K
z0^{y19w&jh!TTY>k)!b|R4@(}No5bnECjPf7Tpj*V30yLw`1rcVKv9`aTj$xlT^B1
z{*J2X0Sah2bFOHnt(Krg7R+co2a~)vf8>S)B+)Z6R&U`gs{=%|N%c-VUBkC4375vZ
zuqI2f!`65Tp+Do|C}CS7P(jqTEheSIpg=fZmLnwV4Q2`FiNS$5yAAz{aGGglL*=h$
zXn{-1pbD?w+AR>Jxm;u5N3STiA3zRz&C&cBvwZ!|2zuFb$SUcBNg?htSMzElGq&VB
zbYgL=7w+TL`VMSIfwfo>|NFP$;#3bqVF(q>|Bg7UVoGy^W43?FCIy-;1`hL;LuH8z
z&W)_e&Y}iqxWxq6o=VJU9r4<JZ9@}M@rwHqd|@!0(wRm9gjpKR<jh*33Y1rao6g=+
zrw^hF3!c;%hdmJgZH`iMXOy}C^q-sopfS<)t6Yg?oXleY=0pNM4DndgOBhC--d`;o
z?T|tp+R(g|;P4O*8+P)V1n2KYXZ;Zv!ln19681atQa(KnmXF%^&X3os>NL?s@Q-!v
zkGfrGVBbl7sC}Y)$A6G{Wt%;9^q}Z-@i5aIieJ+k(7{h}&gbc{Zw7X0kS#szoqRX4
zzD{8HtN#Xh<g>s-aU<%S$WJ12MR&isLDl$oM@5*f)qKA0FpEd~CqFCBiX_B?ibtPC
z8)7_?zaHMkEEGg>ef-*WOQ+RMkGXeb>uMU^5Swk%ugzny=RU?{X9<v&$w((8q5u?m
zbLPNxJCYj&fv&89&MezpT}~C=3(lhgsIswIY&QTavw65K|B(lQk2bDaWcY$GJ_i<I
zpJ-AdFBS*xJn`&(s6kBABcJL>0$k+ah3U6*%ExgeN&o9?MXJZHz4-;F>^w=<!pz#O
z9*-R2n1^QiAOFZWU~04*u#7eu3rdM*hDpW3<+mwe9C%X3KY#N+ENH*S7b(i<ko4Sr
z#<xQ59jX$L^~zBahB(w(aPq6`bVETX>LnO@H3^q`hg|F=5{D~Y;@r5Q@qCz9_x7Ka
zE%LVMOL3-(xuZnXs@5|BjE``&rL?j<&#b(vv!nlp&27ZTzfU1$e-LsY3@oK2&<kOs
z&yj9Oe(2tN8VyKWv|+}~Dnoa8x6u$Z41Ek4meSiEdo?O1knMVTZdcuY;#VqM*U=?y
zdn=IutI$*31HfOPij*RP;gJNvR~&+Fy9e5s3<ufx{V;Ef5Rd~kz)cWGfm|8C_i{Xa
zYJ0YVY|pDO^gk6468gk20ri&nYUftlQVx&a#cGNmesF~bTE$tEO-}H6vKMm^&<v%c
zVixRrPcZuUV8|`P*byZ(ugAZ)==UScV+P<H^m<M=uxXxA!a+QZm7cHe3nD|aI9VRZ
zwVTQ~w)g0H8nrM_(}6gD;ghv6zXY~R=uE5Xt*D?2(?1*oqpgY`%}-W@I=ezKwmQ5n
z3o&4EXpznJK!{u7Juu^}gTgccjzE?we5$G2w^PXVYXeA)DjXxF!$cj79F66wjS}`b
zTdm~<qy4;C3h>a%icYutb+;f5N26xSBalgCNLp}j=|grShmE4Ig4s~h=sd^R?b>@a
z^$p?EK~n&EY}<GF=z1jsYqn&wsV<bR(V1d>5M4n|$$elSSPN;T`(!nJz`W-59csFc
zH553$y=)!@p2#a135uWgk)<n|^lrak;O>*()P%?I@Nk&F$Ks+r6Ebj-1udm1(ZlWS
z33arsPVTMR?#sjS!pm_*ZRid#zCL;oEIUS8gqnO5E~_tr7tKoUJk79{XLt7kY#HRR
z18$vmtxVV}Y2-umZFfeRn(5b!LEc1<YCgn?!MN1tagy>|PZiA=Fs2DmSMlE9a@2m=
zAs)JMU4GN*Pj<N<Jep)eCjUE&B1YBsNoXu);Q0JJyB0TW)4;!1if<fYcY}+0E2(T;
zRzm-2X^ugILLQODjI6MU_8L#IY-;JMOw%DzU5v9hSwTnzB<|DV!O{&Ou=j~G+H3_J
z3*0pzIJ>Cgs6*P&c#<KjN~xEW(6tr$%8)vqRErDCBP1H+8Bmr?8{h~HdHy{^*jF^U
zpp7L#b3-{g!ISTrmE)GH!*VMMb_~zR>97Gws`w<p&g#&-PYfW<ZXfHYlQYc`)my&t
zx~t+_xNlzCBj&4}n%0RU03oS9pmDCzsA8#HL%Ze<u})Yp64dmbLMZy3f=CS-+qmCr
zgJ-~z@&zshc30!iBl#^IHRo4E*C`&MlW`Jb)XRh?qXs(fYzCIA%uspok_-7+>1vdx
zC7*E!u7t!Oepz#+H&wfy*~a|<$Lw&;^^E4<xn#eHkNCZFn|*Zvq1>xz`?<=jx=6vP
zP*!eJ)-1Z9GY6Tiv1O}$=`)>OfUrP|>KF0q+MRy7JF>F4mOHJpqN7ds2SmMzT^=}+
z3K;9ZKrwn*!uB2%AN8d_?AE_kPZZ!Js;SV3L6L&AHeG_m1q-|ZTtC{SoEFjNmz1j&
zqp=S^sV;2S#6xTDw6-$?8z^9KxN7uilZts%EEFmTULaDiTz4*M`OHsFhy_Ce&qS-_
zPy!t~g2-vZn6&H(B%BM@taP=i!*hI_2yn0fx19@9YX{9RlNb~Ls(-_%2hdpETlxuL
z2m$jamMLzb;CcDdphMlq?`IJbc(pj}o;a(#NZ)cd49B4EEqx2iXzKgjTu0`?5}g_s
z!GDtSog%jv1KZ`-HdX8cqUNp~T?o={mUxXIZ77~0>=bZzld~2_f(XK+77UT%s{nzW
zuJeY-=&Q$Dbr&scf)*(L<D$7(NYuRzS9haHV8Zm}h%>L!CgjzY*Y3(n7W=5QjsYCJ
zcHus_-~I()8(D1d-kt$GEOo1g+NUY`6lSB>1f>9m2(tpva*^-_)YQj$iiA5IcRA{I
zE)y}Czgx{Wy9kPZi%5qR&e1|a^a!?c|8YIUZfdV0>8N&AU6d2UiNz16ju2oQfQY(8
ztlg)#;Qyas`w?M}$cIYna<la6bTckxH7Y#x-Q~Ap-e{SRi}s<m)SpXM!)rx#2#Ax+
z74wZkB@GT;jY=R&1Zl!awdFxx)|aL#60oc@yVw9i>d^b(+Mreu>~{)S<Kbv!ci6tJ
zS(Xkqo#F)V)K4DPoeTMswT!|Ha3Ng0K@K^*inR;mFi~N{6lVJx<^G0gknkYYbc@6V
z65*z1PG;gHzvzPy^uIJQ0<^q<Q+I~1yDh-uxSPc-6eB!ZSt!Le@qE6SBxyuDnu?X=
z5yw*C0{kx9m?-AABGGbF$QFGd0wx%iVOM;-v(#DJ;uPssAo2P-5^_a;22Ya_ocqZr
zg;$#OMSa{Q*QcW_k^bUf*e07jVKzJ6i90*U?^c)jE61AVZQIMV#jCeUrUX3%_C&-1
z{yn%8p0lIiI|c_N$M?j2=@?8Gg^bECB_cX4^KITGTJ%4C^zy6th%?{u6?v6FVH@)(
zjAZ*_Qx7&~$0yGiyH}|TMtM_DwI&pph(K<SQ3U_hzd&li<QyBE2SIiY`i~0&B_iHN
z`<YaEM-LHb|Kz$K9!|d^yOoJH8vu?=zoOcw<>m?zl|c%|=hXYsXcs00&+{in=0u1Z
zT-#W#6}p1t8Kms`%<QV6=~TRbCPi#MPD>mUCIy_hiWK2%JVG6v{+AJ9>q#yl>DUCe
z>5qU&1nU#t0X(BenLvgmgh#OTrq&B~^gL+~Z?-N@nE9@Fr-Mpwqcf!sRc*%>WtehD
z*n@bYFt_@3^W;qH)2e1*%drDJKYDm7tmjIaS+C?e=Ge52l4?~8Gzaki@G@cS?&qn;
zrO}jQ?hStyLV4)A`1eS+o-D=gk4<Dx&CF*83jp{2h6HYBRsNNK(&wu0T-f?BR~;hc
z)6skK!qA?P-A#X}w@rLjjWiG;C^j0g)s~SBl;I`?03oAKe@8O>qFe{Qp?;<-kc-uD
zVFI11?>e1#qixAH2{iawx|OpeJKmvL_1y7dC9Mtg0F4XOd(%r#RMc4%66HS-Mu^_3
zwlH5AQH&G>WxHO)-gs++lHK6VcQ&;!sr3as9(|vTy&DZhjmG!XJY7_-``)~RM+e`{
zzF7zCbD=jv4kTNgVLC7Tr(Zrz%LK9(xElde%J#eRvA`Hgxb$T6z=#ORGP23%17<H6
zWt{mpqFItQq5zEA2`#hq-uey3_^|FbebOfTWZnek4j&=tE*v=M^5dN*7M#OumvRN<
zpGJZ`&=9ddZz)-SLYi}o0%lmiR-aTJNoBkaCwjMPyRWxr3^#(yXv(RFV|FNDKTCA3
zGbBqX;s=Xh;FbsxXxaIA?pL}=x5L5Vqgo7mPQ4CO00;?!H$^c0VgBtZyE_S?V$&z4
zOLzij{0AgYbE5+mvejr_Gzg?Pu%0ED-4uo~v2jdkbC+?glrK`#!KYcZR|6XGq~Zu%
zC~q52Yn#j?M(y`WPB!jd=g?&TF7STF7=B@C$v#Gy8}kSyEY`!2Ec6Q@qN?r9@Ykq$
znzW=9vv*&B90$H%{P#FV$@lQs7?;$ZypaEWB-o~M%<DP#%DkQJ$YPX(Q&lDzR)^$0
zbep?{hkE4j#h!~tvAqfWXy?HJyrhVJ!^M*t8FD*5SQwH71|D5>_%#(r$M+mmvi!lh
zWZd+1eNH}ee~+k`^^ODf<AEhctlxxZ)WBFjsSX>TY@Xrs9_o7ou;evr0ZqBb_<Art
z4@^R|>c$waUShg5bB>au8_4M-^8E#H{SVmc4)>aaRy1RohSZP)UNj?<+*|{QV3*JZ
zK5GUNm$;Ejy6+Agk`L$en7+;y)b9<<MI6sGIRr(Xtv3|NrD<u-NH-44T<^jIh)F&w
zub_MM%~~qq&<Jl49XAGR>qit?w2WzUCz?o%GKn(~M%x*9aY$YhucrRN6OvzXG5@nA
z4N;)fo~S2R8pKus6g!!tNb^{9!}h_eb-oNg_wQ_ejrTwKA{MIsJb}gnZsq=ZCb;-D
ze_lAHmZ(%r(c$=Wd(~JPaMJGRp8&|O;>cbEw9#cFBnEFB^a^Pr0zk5`^vSM}cX6e(
zfkA`!YTZcoMF$z0uankLD~gnQYk>tm45v=?DR%Z0Xm&gM>ORF-Dvom^nO(Xl7@Gxn
z(k3v1RE+6`w1%MuVVTBYwvXra#~+s2+N5q0KfkZ9D>b+Q;nnf`EtNp;w=A|$gYG;W
z-O1Z1+jB5U8{L;x;_XZXfrwN;2G<Io-i-gmz6{jmvP$QaDQgm0ZV=3{wK>8;etjjG
zP})L8(N^v9`A@uq<_}0(*}w}%RHzik$;aI;Idfk)ov%^2QwQ5rdOzu7-6sBUR^Uq$
zjp3~A;ZGR^vqNLkFDr&bmjFEShP&u{lDa#p4b*u1R-9l%QC7<#gI+zUkOUdWVXh4X
zn^8%RS8FCGJm*PVTD0d3s`A9B!_{W1G}>w7UK;K`X|+B1UcR5eR8Ls4gW}wE^Us&U
z<?HhgD(o_xx2Ip(aw*-Ol6-@Vo@q@}<er`zSmJ@x*+NVZ#qx{TaDPf${F_v6<?6+1
z5ed%e`gr1xmrAL&E_+267tvYZpo32<N$4Qqu#uuR93)k2&WU^xrP;OU&{ZHx;%btH
zx$_>G9>R?+X*K~tl4cdwlAi#;`^@Je9_#@Ry@}8GO5Pge+&l^$0`f9=VCrAu(C;Ju
zJx*~>ExB|-^lQQ-{;KY8tzyQPfOwxS>`<i;PR{syfEGTpW=K;;aDBnLs(F&A`L0fS
z7^^fRMn7C!2<klfI)j5+jyJ<NrPk(URqKZX<~gMLPRA>vWcOBxqT>xUcepo`2)~Cw
zl;F<>Ve{=qJJ(fb+Kq@r;A%RmF?1EE5Yc-^nzTw*BId$-U0Jq})^tOa|6epQsLCK~
z$8PLM1%F9h==(>=kf$|?+dQ{d!(WmENrTQEQZ~zt-~6xS*PbY;5ay6&yDCmeRiA^n
zRNn0S_De52&Qw!Vq8ZrD!#0=an%)v)h8cu&YykZmfk~Yu0lBl$fIPAfYnj>Aa>4?S
zcC1Q4&&Z7EK-D=jkj)brUHn^{V{f<)rQTlQGIkGO(_`DuOhI4<y06jhXIb(c#uda%
zs~|NvEWjMlY*HJQabzd%QU14$W@Q76`tA<n!048y;_iuTW6~7~{H1(~W6n+=lHMcG
zi!mD3hL3LpZ>n?rllXxyww#;GXje{~taYM_Gl%y!ZQFX>Yu%-h8N&Dx`YgJ0r!H?<
zfj^;1qG^By_z_hB$s8kG@Vk+Oe)-kzU~k|#^i9}!z8!J8jrD6F4h>!9X5Jehb{6WG
zsqy4n+^2Sh#oGoQvq3+vBK{9N(`Yl_O&pEH#4zw5_Q<m;Z=t)9g&=TGePHffZZ_;D
zlVPw(uK31sl~l`2)NFr#KlqfR2zt~9yUPxFIQ)Glj=3BPFGU_eEXk<Jhg#IDFQ_OO
zACI;LzH|SI!BEXprSCTj66G>hk~6)JIG=G{->G-WazbhrAXbf7Q}}!rE_y_jDb(Aj
z_?*JxUtN@`5psZX*NpfCe|y;jxFycqRu?s%eZj**69j_&fFR%DZSTS>L|}f)Chu70
z$m6H4{NO1#lULLrN^4Uu^g=zyh!~j|Oo_{{TySYJrFr~EY2^3v!0d@d*WBKi!Z|s{
zg9?+eB>LeW0v$fbGL;098g~kj`#<qhjV-&Y1lH+B2Vx2EfS)A#wM@+fCs5}9Bl&;-
z+j!=9@iYeB*$MeTD0_j|{MrIldM`lAmEGTR5qZt%`2s<oysIRyHC!n73gI$8(3smd
zN*3*91WI!|inlG_jKFEjnljz(I6BxIC)n3Aw-TLZ$La2Jxe4W?Za02_DJ0;zrA@M?
zbnDd?Z_uic`gD~j$P`o{aD>wC6^8b$gdZ1Mq_2c+Q5teHkC<;De_ROD|2xn?JjR>K
z!Ci8VDqh{!q3sK*^LoTS7Qg*RX8YLS@*Os-5Fyj)KuDLOe`2mvMZj2q_!r%@WE421
z>iw&!n$!hgqnU6^t5-GS&^REa@=~pzOb23|FG5zWz|~`g$y5xQS^r)i2aYubL^53|
z++BB?(6SLhbj6f$Ivz{K;-Nat2*qz5H(r(j<g^aiE^FnZW_9=x^aq~n5`9rLncT;u
zm}uZb*78>RC-fnsJAD%}Ko#NFz9*LYN(;SxgB@E({#XWM=BNl=D(EvS0(pc<^VM}$
zIkoHT7T^7jW87my@U=F+`Ib0<-Eb6kil3GWW2L)IMJ-I{U@`ZVxJXqV5iH`n!SynJ
z$O?%>E!@nluM*nDl%*NEET+jpO}a7WZGG49_5Xim^#Q$BbzH5S0W(|$z463{SK#oh
zt4yAzzT~LS(3u<aWY^ZF@O)G0l4Nw}4K;rwL{rhyYeql{UL5UM&aZoF0}`oVk(XVi
zi%d)(aE|s741cwRhV>Zg=$_e**YMzu##8Q@eDpU`K@piek&m-k%BqryG&2&K=r%_6
z-`dN0(~EiH8Q8coyrE9gz_%AivRxhKq|3e3TC=>h#v>?$Ukl5Af6Sl$+X3t36$B6R
z2L#2$QpM2dFbS@dts1Lj2u`I9NmM7XPqjiS@Smt=k$3bj5g2kndg<$`o8;ls`!5tn
z_oNVA_aba8MPbY9;Bmso+<(26ky>i5SeJ?<CMtnO00YXCm6=>_Q7&F#d9Na#2x&EP
zxwW(U;E<UzR!;-B=C_y^^aHJdMy@ypw%-$#K|iESex>7g-oHOVz6{8R<>dOvgJVA~
zcl?=m;BMr;mU+GG&}bZgSqMr+)vqe$>^bEgY&TX0I9;djco}SGsZ@7ONd%py<=&=;
zx$`L@G;U9Mxy1|iak=D4ZQzp*NWmNglhjN+_n-=Je)GBqu2B_6Sp5N})$4*8RN_~Z
zc>%Qt0}TY*3b|q`#}=z-dUmD8gVtCVlK)LAsM!NeAA+&P$Su~eJp`~W-x^Y58*HG-
zaQx~*(osLDR@Q82Q{>x11cpe55Tw5%ux$w1pDNw9uWxWcB$sKY%^24_esjZ#g3rKf
z2<~lORE9jPF{E==L|MY`Q*t#D^+mNTjB$I#9Ks=Bw0S|dXufJcX4;Hv`0i>o{(J~1
z#BycLzJ=2UZaZp(=M0$J+1a3X>W4ul^%w8uw!8(r_Er3|sEy0=1@7i>dE(?+zoLH|
zLd&q@l@0^Guu?ZWw<-mib6&@ZUPYD2Ni?!ktY*eTkdROppHi6|bm}EwIqPe@lL#3o
znb3KCu^^QIgslr-YRL$If+?sAM!Z7oB?kmAkJ<MhWX?A+vgjL}BySKQ7v*{;y$C!T
zbW}rhoXAtyCnFLq^bl<IF3-eqORClWP3c6M>Q-4n91rVJtL#O(KK~?LLo;xxB6nD>
zZs~I*eL&Z+=G?rCQ1+=Gk%x-W<D{cYZ$QidfzF@l9-6Su6_muu@)#epPW?Fs2dvST
zDjcK?4DsqRVq!c_an4br_dX$C$WGKx)TPB{Y(n3GW9o>fcgs-KKC1?ykD#n1?Pp8o
zw-4!8;pqFL{+XM1j*w%!*_gV|+4t4*{oCxX4)gWGpTs3{MN-<_UsA}|$7htHA$^1<
z%8<a`dIC@xwJ!EYx0gp-_3&<U9RrAVQC3ouI`?R{5dG*YC1a=L>Oaz5u;}mQqTG@h
zb6P{Z#B@aluxxfZbA{<&s;TzlW`-;^4^kn=X{qemekdx|%vc92PRT(^xb^+6*}`Qa
zuy46cE0#cI?7o#5>_qEqhTJaQU+jbtXanTrThujZ%xvzNFxGEP)%M~}?n}4OI+B*;
zyjd^#cISlHeqMFT#=c~X@+twEaPa$ei)kpO**=fUfKZ1apjfy-QP+hL@^V@)a&>a<
zOa+GV)67#PxQGh;kv5x@{c)>#wZ5l;*{%3>$wMPHSR7#h>z>i<M!5)F1w(&=9m|5C
zC7CwJ{bBqIxeazLy4(6j_C&ZIpnw57Nv3Z+cd_rpMQkZ`mo0r|8GHVKBI7d?vqoCR
zLVv!d>KI3l3sd70Y^=bkZH+=VKhG{7y|j-=S)#}wTLrtU(7F><V>uqJn9W;>cPEMX
zQ7p8L(R4x^%QvQ`#A!>m(r=XU#?L6~w9_Zv2LHUfO{}I2QNjj%r880M;-kVCP|mSV
zqHOaApP0=pfT;qNND(LLp6&L!Ej$UdjYG-D?-JDao*F6)j}smYWU^;j(LUWcG83_T
zk)x+oiF_pR2elgo*6Xf(ib=ay54RDM`+2%swa$C?Ns`z&Iyb83s&_Js_Xt8s<Zj0I
zA(zy%iVNdiY#7HR=xKg<MfhI#KCl6k6!o?}BXtvC8KaGL>}#xy&u$vvT0095TpBi4
zc;A0gZ;N?#<qIx(puG|2?wa9YZgHN1H$Fg{SLhCcj@Bhm(R9E$(7R{U<tj2ZcMb3o
zmhHXqLu{=Iv{MHzIDirLw|9xcY{D8Lyo*33bk2O}*fA{80wd8=;;{n$2rQcB`zn9}
z2(<_B>p!!(ttN#_|FZ%{PKLqh00mOeTp93)&?j@b`cpvmn>lMcGn?Q7yUQssj&b`O
zDK*@5%(?ovQPBF`1g%R}Bg=VOR$rqD*085R&Soo9zvHAIrV4k{ywg)GHf1VgU}?4W
zMOIwv(NLYBhIvN;Plj^YY=~8xdN}=wD)KovzKz=`vxGaCi9fukXzQ>cjxK{)rCiB^
zOjqT;5-UzMT(X`}%;6U~&-XJ1*-^~S3XG+ZkYFM3_TuGHh5|^UWqsW~6&hE=72>4@
z@_AFi_on$hD|{9&2RHzxjf$u3@SS}5meN%f_&66T??77?Rp>$3j>uX>IdeZXC{R;7
zfr`L*2$SYhJ4W71F>JPtc+pkZQb8idve(#of@&RB_uUtzqnL-C=<Vap=m|<_%W}kw
zo4kp$aGy%Nvz)HZjj`_22Qv0u%%DzU?1|qpwl$_MdjmkJLEK8lw+CbX*1bdl%SzLk
zjn5j@P>fnx<g$T^3EgnB=zf~QsHvD^)6n-SWg#9B<4l0RoU*QORuRNT+>m<@gR~SB
zD15Flu>osEuY?WBdtoqwywS-HcOy+C?9r#uSLDcf>&A+gH`j2f2dPGOBBDrqz<r=G
z;EQYcSX|G2d5{oXqYM{AqgP|$&EU-|9F%_D`nNg!9013&i&*t5ATqg{KApgt+*Jut
z-^H+exc|&bPtBueTGFEH%LaSzQs=PFBv85yZN6(UVXCvih4*&|&hlX8D%~CG-wKm7
zo}h3CbNz-rZq5H`9x(JgL4(MQ2O|9@?%z@|YZ>37bQptr)(Id6#22fEUAsq3q!Q*}
zbYr@%!?IxcMQenn0jJXSVFUJ`osYTr$kahZ6`x7}DEKRgvx=BA-;<q(ecipdC>SM7
zvC!a&S&@OXkb3M5SM!spnbt6Y`AZ>Xt_l}paty5+hD`K2=AzfT4oI0+c`CG*POO)1
z7252glP&DD)l`LyQ&w_yXxw-299{A+O!Y_BsN|V}OLI?$!bBP{DeB9b%vRE^V6cPy
zkf|j@xLxoJ*83!yUt{C<Rw^we74e#0thI9h8?=kXSHgp$s%@i{*I#d^-}{bIX#WSr
zwq(`sx-V{=4@%(nfDbQW;o*)*4h{j!Y+vk0fZ5*N*RYs|?Ihu3+s2&8Y&a(8i33YJ
zUT4nE2K{(QF4JN#W;A>Ca`p~R@+-A}e@qCf`%O>lwmAi>vup_c&EQ(OV>k{S*_)5e
z=RK3!C#cmBMrn*MxX&eT@C>H_g?w;>?Ns|ur1!I93QqZ)hw%5syhqFVbP4at6{8_Q
z;kQg5o9)&;5oWQS&85Ng{`bPeuhk%}HRis%trtkU0;<MQi!djzhYvC9J+W(y#9`Vt
zm?pncp0X%82{z6n`pZXh;XL&tPoMj<Nu+(gZS_+cYPY+Ihmc9*Ga<oL)921D(3f%=
zJ{Mppw3L~k2((t*->Ua5u+R?BK2!-nH(?tmJF#-8I$fsbMAjMTWYO0=l!nhZe8@E<
zb$5Aa*xA`U2D8r_-nVk)?DnJw<myXg*Uw*+wEKo;2Kl)(1X5UC|46W3;Ed`ARYJWQ
z47n684bks07?1np-U@MbZdMRi+Z;O)d5r>T7_v=N54^8xxSmySVxZq69d`&lzh;{S
zxg|~T6(|Fu@v%u~t7i*QN-%jwgH5duN7C;9K3^S)M6-kinxyX7&QNgygwtF*GN;*G
z+81T^m8^+7P4CV%mabIYzVOF>udSQ53j&SCe!sH3CcFk!ILbqA*pq2_*G;H#QP03j
z+X6sN`SvjZsS+`WMN<$_QZFS=Aww8$2z*5<ncAx9(c2>x2GlhmiZ#(Xv$Spsn8M+r
zj`oK-D45NxB1>vZ3D^HmM<8omq1XmmpMnoL7aIyC;mD(RS(?qH*Q7M%)IG^BL(FWY
ztVUbT>w$bp-PHvm1&a(PP<>}9(%DaQs<Ua+ef%$r5rK_V9@^92m@XX5v{>LN4g(&Q
zO7tmFoBR?^MC3_E+Cj=tbcRf>K5uV+yh-jMS?>xlk!KnSH_?;#?lgt3IFI+O!yYEG
z0~c@ekg@0zs$<od1$vx9H9Fd?yowVBFl5j2+Qb`0&!9(l!+@zJT^c*XtA~b6wt6f1
zDl&PkFnyDI#IwzF?J+{Ul40OVA{6F!DfM}+>;I|Il2HTPw$|YZMW=>99JorS)M<f+
zvZxXPxPXx3pQ(2I#hP+viDBArqop@r`LzOM7P#>uADF|7$U5mXy8o}@q@J@=fR=r|
zc%;9SOd){&ew}<Dn=_{{n3pRBXF>sAohZvfroE#w{-Pp{Bc-Enb>*aiNo?BK{*=Mi
zo!8)((2On{J`6f_P{F~I)n?n3blgsf3-k5Zt0a(^+}2tLf6kh7&y0_4Bo^KQ?aM3-
zvtSp0rz|DVVFgG*<bn|AT9?X}OJK}=;j)W$U5)ncVUva}ZNH$uiL#grGgRg#n|SU6
zSOi_IU`ta_>{_ot;c~mzft4<ez<8t5kLCQMN>8nsVljP}8MX$y@_Q6j&_tS{z&$Iw
zDt(svYLUh>z{5#T^f|db{XJ*H9_<%j&GpS+|EjebAV=)!zo?&pqoib+2S;0yCfr&s
z|0eP=88t_72(zFQ&Hi$>PRAsdqGqi3B@(U5$;Zb-1Hl#NN6p-!{gwbCebeGUj*48L
z640YQ+-&O;ZA;#wLrd-w6W1T}+}za&-uZ7A9d?gzK>(fRjh??Q#j)`jDX@`Md=T&4
z&;o4F8rPLFJ`QcOo<)b9#TCQ}CD3r&Z;>uzD<mM%Fu@=3^+y8DzKyLLZGlIRM4k<N
z@I!?O5p^ohop4OuT2eS;x9rQ{82Hiyyd}H&wHr?r$N546{ZxkY$~|#-Eyw`2NdLLD
z#DOsebgg&qS#SnkS|CcGWGwQpN!bV!^RX`+DITtdYIV$etFPx@=)WvEbQ~+|zn6Ur
z>*4<_h<l5OP8yI{EN+Hi(N4C{&TQkYB!mz^W-JJ2e0l9B^ta=j)>fBJxlq+wbJW@d
z=auOiDd*=Q@X8BH>sPXv6Be_N)x6FQp|nHr7$vib?w)*mWqitXL=UjEE}Iy-2}B~#
zwvzj!i6Kl<Z(v~^OV|U%F45FP{s+n&nF8pe-nPF*RM{PEhY7y2p$*G%GY?33q2Fc~
z(!=HliV}dUc(a@m3#pc|RvdSMSuNqb45816i*90N#xU$Ivo`0EK;N_P^cQSf6JYdu
z@_~mM`jwEQVGu^Ez*Mjnk#hNywZE9Zt8<Y<SKiqnn%?1JEY}o6D8&>E((Q9gD`}*m
zc+<HjjJ)oMdY+w~tmYZjjKOOk&n@?Gog19go2<<jUGeiHr|3X&DSsNp1Prk}Ika>)
zm)Ns^?ee^zS31UTtng<z&^7K<YgzBx>YHdK@xBy_6j-dfcaCFr(bIe6Ku}!xlL}|G
z%ZdjCHAc48qzsx<0W6`+<ZEvC-CE-mtUlyOx?T+edJhK6XET?>Dd!n8lu#%m8me3h
z%B@B0;m?o3OTT)!iHZMxv4)qOBSF!6k8&rZB*Eg?xnfX(f3&)?j#Wm5fTGXGo#I|U
zc)nEhZdCR<97c3x#hFoEd24+RyHCn6auyIdl5_H4rINS{k57=zznt7z)(LLmb2IDC
zu`M|4oEXB3?tNYbaO);U-*2^H(HG6~PyG~dhVvba;#%`gTZ~6cT#1k6!%GDkIzajv
zn13?oQ_|w_Zd)iSP-0G8?G4n?${;HgMkL*u<9h~o7^lc25FXCErop2_0d{$FtB0i>
z9!qd=KdAr;<g3Tnv5K4iAX<92!abQYH%B?_h!2>O<*TE7;*;dRy&DP7AR8fZ#KWxT
zK>$~ct%n<5w`yzTR`>6ql?8e)KJ9G^$Y9_`D?T!sab7j_xR0())MF9DP6ELSN4p_n
zlK2G1FhC}X#o%T4w_)|Z6K{7>^`Rj8GIp4Wz$ypwbN{Yz=$td6ot+zwSs*<I?h3bZ
zc&Qe53O*gYg<0_l_Piu3cvQ3ZA>ifPW6N2xYb~^uj-{_ao-@J;N7IU$8a9NlpPrlW
z`Qc+SVTa)3YMu(!G|crsyzzC1S=-5TjB5}~e1OB>Qc2FCr=2a?UD5A$04~!U|3v<)
z<70?pgASDEQ29wru}dy!$-D`%n%#LF^IJ&WvuF1}3-UiSgf0j8L)=#czD)Qvn@^x8
zoGkr>CCgHxr;i!+$0Iyj_A7VAoqgJW-%gFF-(nDDJvVQ}XdIySnp6fyu{M^Pm<*Hi
z&~@|!$(WYw_62Qs&sWmpYd+JmLl>l|>U|;P*<2qTkVxwR;~AslIhiP1S?=5%F;8NV
z-A>I_gkac``)0?*lKH(T^+JWtI{8sjYe9p3T0PH{(kbkZGG}l}7_{xD8u>q}F<znd
zB!(i;6Q;^gz>c%scAGo<#L&gn0<W7&B=)%7i|bo2S8)yo<s=5tmyjecmiV_*q_vVQ
z5P&)Yjt@@Z6GAjjxpCYGlLEV9V+0`Wh6_C<$(DIf;}4>m7^Jdfk?x=K(MPRp7u7FA
z(Wk1(u=|w-<V$$uGl?nlho$Dq3yt$hzYny!4ba_bHoj5UB;HN+yWq56jVkdpfH3by
z&ak>WZC~5LC~@-qwRl9)HoH4r+D~cAeK^gj)CWP7Q1bWr3raY21f|&l)`Lv)&G1t4
z=EF<Ntx-nc-Q3k3RopYzB&p004S+YbPJM_502-(|Fc#YJnhqBc4q(s*S|MAj!ha?`
zVI)jK2_6Swaa)uX`eDP@;C(b6PG2l_uHG1~P)Z|ANWKp>VTZa6TyMSK{zEDG0@1If
zCt8b`QGCwSIdUrX#3_tw<dToMsHgyx2l>8mBt8={jf&Iy!8O|vVgbX}2P6Wo%>$9^
z<t9o@fwD9}Ri<n>Nm<{%FFSQPKxM!^0||+S9)fj>4hJX{P&IF|pn(iTj&B__RksXF
z0d$3fg><9e!^_LcRz$jx3TB-LyfCZQu}CjCC#@Xe>e_w)j;SlQ-jFyr-{%;D)C$UR
z%N58dz&rxBT765@r_z26Xkcl@vjejZAmrAkl@+b-n$vu6rKa5Fbb@Yhi*fs{;gERB
zQ?)XGYtc-h5ed2WCNcboCctB<4q3NO&$4+fL$t2SFC)2nDa14i2Q(^x`+%Mr6iO|m
z3kAPCr%V(y#b;q}^9KV(fQjg`adZt{?_|y*kcIX}_!973(9;KPo|~}Aa%4iE`I@rt
z#EA(3R(&D2wihRxYgPR9$>S1q9o{&UkSLxLo|LDLzc>zDI{%%RkfQOLkEGj4O#l!o
znCA@~L!vn2&X;~!z<Pb*K$D2K9rd}DR56%fN#leckQRz!|0CqM$wC#&cC3NBE+=#O
z)4!|tUW_N4%{VB{mX*OE^Dto9>keqav-=<#CM#9HfdK~JJ+>yw<nY&rcCq8}8~BNL
zT4@(51k*RD@K-(6SQEuT&4@um2HI#ORU5d%PbOX^5QT)DdmZtQNqRB09;!xc8O;0A
z`l#`iU&PfPDBJEgqox5CU{Rp~3kuJz+<_<Bq2jb_oBZLBWjof(y?q05^p!ST%Wo29
zUWON*f0M3Prq2a@E?fGnnRNq))#wgT)9kkp3}L$8I^p!KOIF>zI9_#-Jm(eYdL95Z
zK+3<DLJhLe60WOH1Y*md%(#qNM2_FRi!SIHc!w@8^)Bj4>4uMpyZOD@3?@BZH|K$A
zgh*jh{59N4jPBOqK)+SC+18Ca4J6j<4!T)G?eE+TidYQRj&H~lDC*JCSJoQ^rji@?
zflo2D#uPcHPYQj*K3a?{7almzzMpu?t1fPmz0T}Roc$d93!=|?P$q<p&4{!1?E7N3
z7I$<~z_ea+feu}A<Rj|jD*6zi)Rt2Y9Go;maKkjwx$VI4rT@DIu1@UHddGZ{a26-|
z9Qv_wtTp9>gTi#V2CyF|!@S_Nw6O6h*1K9b#INeBZv$m8+CSaDtb`Ok9`<uwg52Au
z9z_hqyyD#rMg9Dw-x_@_n19?(yX}hGa~4Sobc!Aj<FbKt+#BtHXt!n5#c$%La-GSj
zK--xr9C^VYmV{l&Oq!sEA)9x-G3lci?P&xSl|O)%m^ai9XT;?c0!A`dV5X+u3~tJE
zwr}<mZ|jEtgLw|EmJyO_KH-WkTFv1?{!fcFV!sKxft1f4Mc)vi20RA|*@4lR+9v5*
zP*9RsgJFs-?`j}aOR4z*?c)b7;LLVpipmzp4AD`I$c@1o^}Ango>QbFE>^mFkh8Pk
zWK^}zc3Iqa0=NgNPHdZNMSPV~C&Tbi2bu%UJWhl~hTBzIl1U}#?lJo~ZdM#=Ts<&H
zJ(0~R;BjtV18(Lo_R<fBx)Uuk{h?cU;@D6PN3HL!>)9u*6nD2rLe+2>9h7F}f3W0E
zNQ!^Ei^a3)N66h|wd~+z5W$~J9t3D49sz(F2JQC$PT!5kV?|?(%JdI0htzo;Q6CDA
z*HEJj1_Rf({GiiEE7_n9{<M0?)xelylbwo3#KW-Q0=KGDw<A1=RcETdM39W5yq4kI
z{8z*KA=1Z~fZNPTp#bVYu3263=^ToWU@lqyveu<lv6IOm2#2b@qEHaYU#hx#Y7X#2
zn7u?XyQw>Pg^qjmzzPVABR3;kT)W2F51+?0>FN+?@^jiGT@{qp)|GH0Dz=WXr|=VN
zjuljzUQLEa=lVH8&ql&wrv)vz+SIBxnWb#Mz-F;cXr9h_c!k(?A>mg|S3Zu+*as>z
z0f4o6Shh^#j~%!$s*o}%YKIJc`K|DFFmXf#-3P6Qe<2r;=ap2iT30IR$A+ZBTbI7g
zGUIGo4ulY1YMsN%TwtzEG2}afKhM@YxwEWj&+{CgE8kH%mrE4ebFqcNoj3a#4QU)<
zOya{x3^pnus%R)xZ_1>rtU(M1;LkQ`QQ#zSdt1JB?wG(2lM<6y4x@EoBnQw$d$LH9
zef89!1gNkLP0Wi_u>CpTvJOy_SpNgTVAr<iekhs$A(yew??@qN`}GF;d6(FJBFRZ*
z@aNC5r)T!>Q$J6en);ciy6xatx1U%_#v*^hxx`l5x(6O3to-d6SpJKT%;y`1Si|-7
z+tC|IUS`Xhsb&INBtsBE_9BmJGr-Ob3|ADek!a7SC3oPBzL+nQ>iL(MVvZJ-{ckic
zb6#zRY=NYjH3kRLiUP@c8W*T%$Fytgqy<p#C`$%LvQ80@sLt>dq*b)Nhm(4E=WPa{
zmW=hHR97>qI-DcZJvT?2y#MP}z0IS=ZgS_<MvAu;^(2ow1mg*2zy#9Zwv_38?KRM|
z-J0~rN`Gw`gMT$RYPl8jiERl#A%;bi0F;V?jCNf0YAJkwGl4=MsQF48@`V(`K)#v}
z4IWbS+9-*nwQj!aOXNe$d9^u|%ztu+-{aM2v3;COcf5QTTay*0^6#sKmX~*+flmc7
zIk#Z)q|2J8SlsX7;LREmsT?nqJ`dUdj!pRr4j_$(2y6=wdbA9s9x>td{%D<3#V^xV
zNoWJ?H8%V#MTGh+a4o9_ihBnav8bKijiLv_(i3rB{ttCen(rK;aApIJdV!|dAcDhV
z+>f+k`9wxrr{s-yUH>S)O7R!69Qr}pp-_F2Ied`-pEsApX_BW#)I+z`j<cfV%(OJF
zeE;>*l?!%Ma$3`4u$5+5X6J1ts<LJYHtDO6B*`}pzQ$ZC0vDyNoqcomqCti2dXect
zcgONPX}|tcd$VE1b_)Qkt&Q+~#$=R3ODtk3cP+vWrAJnJ%k9yOlg5f<{Q$bH?_#~*
zD&ME`F9bDSX%B;ht(J^2^07itE*Hw;%-r7ji_l+v@{y@{C3Hbqp(Wj5rSD;xkd93*
z`5ZsLiV)3&Mq~!I*A}XQd{^?C9{zsaw)G{jdWhBDJa-2^;RsfUBJmTv@VH(?HG~(_
z>xc!7Ysy`Iv<!Bw7R1vh`M$yMUQ@R7$}jUA9&n$#SJ+qTgdJt~y$d?XI(st0LS*Kd
zuYMu8g$XJD9Eemflu+P)sZ_lH7EGt7+{;%$v*<8|l77BtY$>b|kt8}rG>5x^X!))$
zTBOVQ<(aV5Itb&aXs?&Rl8M?AWTC2brVo>~d)qPm6Um*SUl_?Q?hA`>o&le1ZD(@1
z0Ozi)T5XhM?ml+3M@E-kk$wQqjwmJBh%&IohpS`#7i5=4pV;~gzgbuq3wEy4CVn#m
zCXY2$!8jU3g~yf%82d)HK!3M_0lRnn7MWXEhM3l<ji*z=iFp2%^~xEs``+$jQ;HsQ
z5@HZ&gve~&9;X_9^k2IA;CZV!Xp45cp#pIY)Or4gEJ+We<x-fB#VZv)Q*%m!cyUz4
z^n$yBcB(Hc(k~oTctAD7r;^l+q1!%k{T6KOo60^FvQTSZQ$jMD^QjKQQ}OYZ9^hD#
zNK@R1icO0InwTC9V|0Pz7i}6>j1gBrP?uf~ozPK_^(~+eg-ko|FpzRzeqt_nxg5ih
znrj0#YSf%Qo;qx^W_t=7=FzSyQAW%c!Gh`^Y<*WN*IBdZpTXK?4%sZL$>nFyB`|tn
zB&Hht6-Aln+RUx;MbnD+Z4M=l^k%P++_YmwcbO1DDkYH$L6aytz|C?y6QT8WdsifE
zkjs=&7M=UZMF~mIoRhaFSG#zo3kj!jEgs_Y<SW5+=*877c2IzUHU_(h@e3g=ith?v
zO_EEJDNrk339Y{kX7q`iT>#$pPG9-|yw20rNvY=_q*N2>ayHmB6Y#p#^b>yU`JMRY
z0Oq3#lPYe`u0J%Mk74H?=LcY!S53w6IuRlZLbiV(8X4L2pO#6ClC{mY_?>6g46T$g
z1(!`*^Zy^xw`&dIc}|UPF}Jb-HKGYTD`+(TTy#2nQLdloA7CcJ6e;M~9COO+UH}Mz
z&4$ZlDo24D7@9Bw9vogy3iFxcW5p`Phs|KLBIe4CcxeOyc_?d>>giHYTiY}h0zrpS
zF!$rkLp<N{s>xh-y1QwccvF3W5542*zKX2<>Wu)42zz|B4Nhtf1!4idGP$d5kv%^r
zNW4mM2@hON!^5iQ@P&j@6a3C@fxA*>q{ZUW>TgWzYdg<(wwSlFz5K+9TBdXkH{dQH
zj_u-Cu*G)o!|hqQ7K|QmtRMWSIQ}xO<m^Q&sB9zK)r9^9*Kis$2Sp7X-?3$mh80!{
z@;;z{zMEI-{(C*A;bDeHHhAc-WXvQ}@kYl;-KB5c3=zHHK?)hwnq<rDUxIu0c_zzW
zJgE?^-cDEclT9ilgQL{h4RG>iZ$k&Nd;$jMtdj~rU~r(AC*!g`sP$E%<DV4Kh-wYk
za4#FbgimBX3=on5dx#BFQ<SMNWRz0zt5~M=5_Q@cM^pYBmFnnl@4KNRw8B+Sa>Eun
zz(BVUimush9G=Bv_AUyPX}h)q$dNSj#wU1-DGlbBHjE-g4BL?|Gjl3c<0cT!+;jSB
z+v4yxoA!cAm{olA*Rw<~ndN*7=F`2x6Y+i;p2Kfk;4rFml{4xsP_bZkea`#NfNknz
z-w_}nqLZGSCj^yuhZ>hl60r*!9RaV1Zt&>c8u;!!T8~5@KTd>5FO}HS=7WPo;4rk@
z%7^FhM-E?E|N4=tvf_cI1O6WH`$?~~GG&oS*Ve~3o!4H+?c^{=^b^VojF&GC(hGFC
z$B`3BFgdiK?4rNSe##I$VO73iV2;l+dRuElzs2oL15PBbg*^hkI-+HOJpM{dH9bQS
zLOL~~(CdrIOf4kFgd{(RE?T#oeE(^e>)Qhh8-LB8o}iJ>)CoFt?DEX83pm;Pf925?
zXWBFhe+ofZ;BLPuY!328Cq=?78ZF5awusZz*mQkSDe@m|;F=`G^7X``FU-wrcPolU
zo3yfF^(t*xR3TrnZ;QBmrvgQHDMD=~5^XvEk26D%&KK4fqI5wLo3qMzpXR<R9dCSD
z(LujK6R|4vDL3wNuh_q>=dL<$YDi8e&~_IJdG>d%LVGRur`v;%@$)Jo{#E6L13!sS
z$|``waO4(oGy?urbm9ng!Bv{9zS#yx7%~eI8i8dy7sFBdm%zP;9@VwdEWJjRl@1_@
z*&X{f$)#&P4jjaUIk3wj;7<_&f-X}}`hUDW;LhX^v#prIA$P)E{HR(eP=-)3yYeh4
zgXu&@%5H}wzmR!tmep*8jo)+I3t({qWZBoM%#i+8e3gOg7>(vRKa=7rHgqqHd;BE@
zmG<t4dIV$k?svHNQpef}<|TD-bBP4*ZBsf??FdgK09qHEW*VU}y`#({_6lF2u6NWO
zMf9kB+?0wI1*?zN*4rdAsll}?cIf;&-_;(beYirbV5YN^X{9YfwZJAFPdcz_Y)2gv
z0Dmg4Q#c0*uTyKgj>+nn$+CWqE$+LE17tDRTInJd#{ymBrb%yfyBMY=c8OJNK;lqv
zgUJutX-d)lDG{bvDF{sD`e3LGW1=HKbX9INZ_d>y#~DILc)j-4!7Kw0=`ih3jO@s5
zv5x~CYerkQKMwEM))Z^md9Kqaxpf{AoRB9b0JO+C>|@0Wi=d?rYSx3WcjUDaj382y
z>t`60({GEMSs4RfEUIr55SwbAZh>b5WLbmBh;B3zg4z6b%VMO=_W;mnVJcL=cPREF
zA@eoU|Nqww6F#{5>=l>kGf*acKx3lZqA5{fy{7Vw?cRdz^)evG#=(r%_sx9^v?}|p
zW%pyc_w{cBJeqA6fSIA<{a}(z`3A;}8drix)IZxbi3HbmlpI_gHo1pBMzG}58`^Xm
znB9DT_K{%JXUh5amTryuL}|(eX3-r^r;^VEe+TE-b!!OOwb0;xpgiM^dsL}Q_ei)B
z#Qs(U@yI?Dqs~9`3v31e6}F+IV=vibk@|Tr3lkAz-|%3393jCaVrfx>NPZkG{dxLX
z=5F-B>M;e!$`qfyrJvBxe41F}@B{+fFwXvfdN++)szN<2iqOy76$N*_U{mkxIXnMz
zp5;`k-ysTuICid#u`|50<JCPkH&iYfBNkK1E!OG|cI>;>%o8O|Tv7|T$*hUv|53J`
zUy=DdY_cA5s0A6!6ytwX>s-b}wb)h*A)u-55~j?#M(Xe-KD}i03lS5oOeosu*BWXw
zS2PM8x{cbceg@F1Uf!V~zh_wt?=3~G?i9hR|MJRB{!{3yj4Fi;4gt4emd=e>E)8vn
z+8C3T>A;h<lKQfVN=;N;lo4a;bh-*dU>IYB3aR0`B8sy|u_KglTAe$s-9fqQ^X0v;
zfG#<USr`->a89lLU$tqL$A>URc7HV(*J*YXxU@am!cQ{h$9TRW2SN~p4&K?r=b_9|
zRCa@$39^g%bvf}(iP?VTVZly`ae}C9i2Du&1!F1zM4_lyk!~J6GhPv3jJryfym)?Z
zh{vH^nH%tKX;r<qqpH1OuT!Drb!W^%W4DY^<0Mt+a<va*1~D$a=YAP=uL(Xj?3=)Q
z=!in@o24$0={Zz!IOt0GgIuRY=RmBC3`q4;mvvq7hBTpHi{-<<>QgS#{N|^J0D3jP
z5<cLoR{4r1k8)1Vsiz0WtG<b27|Ofc@FFJc&raz^>l6NiOjghQD<44K_Pzul48I$)
zah{Tq7f6iH-UQGj_hEPxZ43>1)zv{>IJ~9|8jRsC^pF6wy&v%yspu>#7)$LQTKh%x
zJ=|J9C>Ue4*%p3yyDv}#O9Xq6(!wyN`z2rY#e7!*+c0*vmx>t7R9PHhcjZ0SgTuKz
z!>dVWj66W4lp=wUfW+J3+iI#4Dsx;b7#dg((Wo^LQ;KTG1qQ(X7iFz3_l}%6ZqW;i
z1gsCkcwRD;PaloW)YgjCaPX{N{RL(hS!KP9ZiFvRQ4gFd{C{I_+xhEVMPL{_Z)xHK
z%NC8TQs-LOqEEhq-3sOhs!&8wKJ1K<>|%KKpldeJ-{T*z$p+}6P5I=Av7lEV)->(x
z#i;Laqk;|moC#sD1#4dZT#8%PK1`y29z7b<GKHbWqeUA6YE==2u3KL9KX9%bhs9wZ
z{aH*lyigNmNU_M1@{!LFv_CFfXP+xf%`@4IOHg3$F%ff>8S?@7beC&1#q3QtJ6UMU
zsAF^0{R;IyAKF%h>B%~HGoq<_3Sg~|D_8@)vjCMdVz$o{z%f5ssYkPn6;2b@-P`@`
z7ekMPMfx}}*<(6@9}%KyEATbQn<2np$17`;Ou^tBhMESJl@V7a2d|96Sj3fXt@qVl
z4sf^-?G46j@_?%L2Wfi*Q>c|M)K&eYgGBiZ|2c;8wrJWlD|(!nMndZL0HLCoz$KA^
zmy=TY94#c%ERpL+zfDBt2|}h`u_hnPLpIqIG*7c8yR&a2C+bQ&U_JP;ByPz)%z^60
zir>uFNbR4dNp9x4d2<qKqV044C@wrFQ8zNI8A~>j@ALu8ONPyq>G@th<bldJFnj^r
zjv)tU;xT{wK&q%({>XO!vD-N)Ee8qiEddXv6ut%fpyAOx;ynpft(#_e3unG>DS@G2
zZ={vu%Fny!yy}=law#ww)&WsL$iV8co$D-ydui)xxU^IgSqyXk_65_(exYW2?77y7
zU|HB4{_{F<e`Y!<7a~pKZRDozmLyqlAM5J8GhtrC`rSguH^8o#V-4I@84bK%H}Ut0
z_VJ33T7PQ5T$)gCg)jY9j+b$2jq~9TJ{M^;oP@nPVj9ZSw2%qnJt$nk`fPpp8WN&f
zFW2x#jIY6@bc_LRH|>`};NFMU>q3(FE1O%B{-slRdtE&r0OQIZ!!7c&<)k8}0E);v
z^*HAO6mI2~GbkFWz>nc%n!(p+3MsWHq5~XMSQk_5$+f)1<DF$7&3|%`wMW00?)Q=a
zalQbr=h8^_8+wtD;ZTEJrrs52auCc5@&tnzv@sMMX9_@*t1%FrCzEuv>%DCr9R7&=
zRku+{vb_KbBn|5UIh5c_1Gx(;7TF-VWPppiM)Q}<8|$^cJ(n^D5*<$(kP(b<M19Ov
z(4M1KVzG+GlSiA1mw^(LfH(P76<y!r(}P;7k%qz`8?(OyzEQRxHqFyITT<6TwO}W|
zc$}aq#IoeN=groC#KmZVb(8m1T<DlVZi?B<7jlX%k_Kwk^g>P+j4n`Bo!Ni{30Xzx
z=~%OnIQW>~Ql33g<kClF<M0m2C9FEHz37peq*!CmrM=|X4yK+%FT?HHr=T};AmGQ6
zZqN_waTeDwZE7v1y?)x(ai&n~P8zdN|8%2`#VCQ!P6r<?E)tVgZ}y3cb8gAsM`d!P
zJra;3TY$p8T+$~((*zIS9D$QDnYD~0uEyJ^f_HPc>D|quP;X-e8oFvAKu*}HuN7|n
zz8LcwsGfijWV7P;si=`%q02hXJ^b#rgr`=;bTfzD-Ofo+YJXOMM<gd@T{U`L|I&*)
zG9U+r|GfhoYOpz;ti>$+wUk`t$OyOuDvotOrjeC2uR8lx`Jaud+AI18MOM~%_xosp
zpl#OhMuNEGLkK~B+(i#@`s0J422QAUj!W2(?qpD!7~vJ(7xYHKTWWG*-uJvU6p>tq
z89SWdIUReRsTgDp3{Spl&498(aaF6Y8sIVsGTIoQs<r$gu0;220@++me1i}8ZcT*<
zCLz-86T5M^-#@pNB~G796zQ|IDtEQWV}~UXUWfpdsq&Q>Yhu}an#FvhQk&cf3ZZf!
z^@tf&+E&%Z9IXW&R?g+-r+VH_oEehl5Sng9J+zd-aW9gTLyfv5NVw6lW8$B-Jh(r-
zfk44tyC&P*rwyL#870<=c_KKQ{BXPZ;BoTOR9K6kL9`5!b1kkdJuo}G5T4qQ%yT(|
zn3no+lq^hvhX%>WFB5V*%>Sow61PFwO@1+6VS(qO)=S`SdGl{OiVACw_qUv#TX#-+
zMOBxdH&~aN5h4E?2f6xfZ|zFA+|0DL>N~%;NKZGUjXvvR%JK&n@0=}IIeD};?oYae
zril32Y)&%$eqcM6NVk6XQ`c`UMz>740nhN4gk>}y<l#sQsY|}cdGA*OqpLj6n1KNj
zKMW{ogIUB~`5`anhIiGB{=_1LC-b0T%pU<@3ao(Ax2}_<&ifUH#?Ed+z=s~Q8YMnh
zbYi!OsgSS@^Q#&3771lpc{C9-2-pyB7vakd`*vF1c9Ki;zfb*_-L)u$^>Td@yJ23w
z)Z{^Ock=~YBMOf0KP}y)wIBIRey)Txe-)RXpLPF#JGG$Z!}cb{-6%YA&?8Td<axBX
z$3!qI@;6(+7}GJI2}vfuyYL9o*EznU-MjRA_Ej66_rt}Z{v^F<iX5k)mGn&d4Z2${
z<Obtz%wjsFwukM~pGTavV=iElYT9|Gu9if55;_FxL9zg%)2<;&UIdbT6Ci>LpGW78
zbD*3<58bY|U+Qeca0lTNO)aC($(h;wUrz&SEvvA5N+(Xr7+gzx>3jd^zzwYpDc*^*
ze`Iv{{GB#J?rW53SAQTqH4Z5z@nDJ??itG*DQ>b`+}*joM9YrwuNwjv?-MSZ9+|U(
zNv>#XG_8Wh$#+es5&AS<$ZYmWR|~s&#vwa)AFQ>|hScPIYZS0kf5hGW&|rp+-;lS>
zzwBF(x1^kDXdB7e&)X1ZZ}DmNlSfoa6*(N$5^GUVHJ_O*s>eV1+X`wFXz95`+@XPt
zgMJrq?SVnXnUWzkazkDsXvH&2``U-n?YuMrhDn+n`jI&u9riWkcQPC?hhKO`+F!n2
zKz#^3`P`pZz3}`$Dkkh<izXhEO%|5XjGzskipPkP=Rlj8#F;A)ZBPL8ayB@QBZ6w>
zmIVOg)XF{%78cb7{nmiU7&>|{(XahvLcaW(Zz6lr7v@?vz_ZNGmfg!`5m>h&dOt%?
z%8ayQBzvmAH9sg{#rc#i*i<R5MlW}W>`L*^E!nq^BmI(4UxGvVcdYuS9)_#tuXAnd
zm3*cZl&?@9W_Ol3cH-JUQZy*aYG?vx;B*smOoNwhO)fJWGT|2kSot{Ls3;u6YYZo9
zQxc*l({)%dXT)<Is+A!<i>PBdd+kN(_;pC&dg>8pIpmur^2iH#{W44gitIU`SPq1w
z;3Q1Mk0Xz=JT3ba<sX1`9U6XIK0@I()tk2bc=vbN4Hfx=;vmmBy<r&_<@R&M#C_G+
zXH^b`UMR9M$~m^EQP=5-1;O9mHI`zZRc}71dPlHXXk~X<lMRN(-!TCLHniA(|J6lv
z^z2HALz3~_t3QGjRnNdi_EmcB=VtI@+Kqo7e!<J_W0Ty6@gpFyaAr)fwFRH=p51#d
zw;xb&O;PFndwNHZa{ao`&&HG&bO@*g5KbgF@;6|E31f<c^;)imC|^<pml=?@@8r(c
zN-I*n=2bo8!>)?Qp|#bu*u<%aXSTK3m#UDS;?xpN<UyB62eE*sQAjkBTGyV>4-Ep}
z0TM<i?GF=ATww?T)cDly0%25XwlkLQ!!Gq0&q-f{OWZjdYT$dEk?y@~m~_#(lwI!^
zf3OEM>mqihRqAO9lnZj?hSaeY2MM5?+FwZ%VQm(Kka)MUFNJ#3*mV0P={e!zE0Z9v
zcH_=Jw^h!MC(#7t9^>JJcZQ4VECls`DP+AtbR#T^4&OGo7o<ypV6-jdH}a>P*b`w|
zl`#Cl(XKcXTS}%Q<TdzTJ&$IG|DZo0p4yQC0%G(92cy<o{jnLt_&?NN$Q+}@DAsU!
zKvg2{H=GsnDkO7C+uJ3A_}Gh2bYKy&kzD@XO7-K{a-4s`Nj{3A2U#KauMelK0fb3O
zD`D{6Nca6}n^>V|&HE<lK+|vqw`6O9d2H+i5ec>e3C=x3RbX5+L7`LWYusM*CL0w8
z<_af(twm~2NozT_AoFSn>ZQ~OLYOZn`$MD(Ek+ob_nRV(5uHVhjYlo5KTctd3L`*5
z$$wT;g}*Ot7VRfA+f0!WQFN?ld~6}Ne+}%*0H1al7T7s!=8V3Kq-xtcD}gNbto_rS
z$@#IrOW@*OhjmV4v{5Mqb#*75N12F^22N(I2hO|Zz!N*OslQ1I)@oIB!-UE)(?0Cw
z6qGC3w4hJ=MU!egZv?GA?1YXz<97c-R#MGtM>mGkVCIi1lR^e&@j8uP456|xRBwK^
zukuJeZsEP+BF|dCdTIsN013+g+DbRuHA?T~NkN=%FHR-B>$@NGM4$0hQ3h8RLlQj-
zUT+roFy5JZt#fI5v&<jlJ`O^`xMRt*tmTBOl=eavQM){VC141LIqeB4t4#o<yXTrX
z`Cc%gz|Mj)kuJ6eFT2A=9kSM%KZbzh4!7%K^O5F&*}0$B#y_#Lbh_0#AXyxObF7?&
z>L(u86_hVjLwb}}15|x-Bu?xPAwWpZ@=fMI*Z%Rc(^#00X54BZ@maIm#I=@zI%2Fd
zs}n7>oJ!K3^o#dvxdKyETh|KxDV#^<wTz^_{*vGuVC?<Eq$?ujToDpHO5O16RBUCE
z0UMI#`c9n~VzCaRXX>O8n$#FJ0o84cNQp(+m359oJ3Ay8R?FLR2h6Ckv{q&Ps+*&r
z;F%Zo<LSOP8IISi^RkTOcj^#hXPeXe+DnWBTd_ctD&Y)9C~4KsF2O_<+Q;~^VW)cL
z!c}p`2s>$Xm7|KzM8ROwCk|4{sqGPxRsZ(!X^ICWvCPSiQ)q{HO7f(Oj`ICvZMOpT
zHqiGv)bf{sYYG1d5sVsso=a19FR?Sn>?PRwQ#0TD+1wP`DS{>>{P4ohj;;I5sv2NW
zJ#ex_U(6!2@({aP!!Uq_%ib>z$83K#hGF7}R&?i?vQer(gcNZkaeTZZM`J>U01ys?
zZVj|IZ1U`o>&fDl!~?1|b9}KUvc9QEc9(kp<1(r60^t^+_j#+<&&Y3Q0YFrKyg1!q
zgiUx%+<(R@2CGxTc{Uu}2?roJVbg_N18+x4PF;e#*cnG?m-}sH6feMcPuC<Y=?dBJ
z_wL}d^Yl>K<54wjTxK3X?*RL4h)Hy(FQWPnt_IE>41`8f`-t!M8+2st$=0_T7_0vI
z(Lv%67^Wz*Kf18^_sE`F2`)?;VT7PvV2XqAgTF$<65_#~q-UT?fD1iKkOPxT5Xe3L
z*&l3}oBn-5fk2G*|74_yRnvA=HioqbE}_x}$JdwOh*On8>5g{j#!rP`RtOMYRN7K6
z8D(P4!^h`n1<lC{Ye=-|5e?DuOR1hyv#o?XH!aur=(6ohBj^C}Q_3n`az_kHh^jOf
zl|*f)m*_@E`RS9*He+Tb)$+lH`nYm7sz--}@j(K(T!bk45XBrIru4>quY(pup3udq
z!DbQhffg*EG2&3o3;+%bvv3Mev;&-?x74%|i{2xSDDYI!oU1an&g#pO`!oZ#$B>mj
z@d5q!9y(>b&!28;iZLBnR`5me{4vt!uTAL$f5A`+UrytH=G5y%H-M8T!(Bog69|7z
zsf)b)%VA5E&YPYGaDEcO{A^c8PrpKRqtzj)_EtVgp*Q&sYD}`;4{9z>KeYEcfPhYI
zZ3k0bsY(*7Kp%?7xa~Pu>D1AdWb&W=a!t!{aX8kagxqbB>8|^!{5&Y72$(1``IAWQ
zozT}KAuo~}#D0<My`)ps{4;}$;;yy3cP(ye2ypQFd<9%z!YXrH*WIW`&FgjNMZi<_
z<Nk35x<51xKt^&XgnoBPx8e8y0(64mQ-;wewxKb36|%fz<Wj$ApwLvcn>t-2hfwqp
zQEkHIeO}tS0^<yVg~D}_<T|Z-xB#hN_HjR91Zu^;%4+qYYVh5$=k@CL@N`EY$YnAW
z7rX=O&Z7}R4ol|ak3T-s*;}1z;-Z~CGS?fMN@&+@J%u?%pVO2fm#{Pn%rwOCviDvu
z-APfmkiB$mEKstrFfIxVtit2v!4bWR#<DqmGg~^eS57vZy7YPv(s9Senz`i#Nvy~l
zC&SUfrCO|$k+n%@wsdt;Y)YoP!I43hv*zc%$M|`*srHI!%((-7L$=cV9plB}oi&#A
zf#QB=lv;>8M%R&62Q0@s<X0Pa6)9v%TY|e&*D=*NMfq=+f7etdoJTz`iqkPVh&#Bv
zg;V%3+j-U*svs-u+>M3k#Ic)BM=8B7-0Y!Q?d<FyQrm29v2eXCeP@*)MUKW{`qX90
zh5ANH*l|Ie1YT3E3#yzY#zV+X*VRsLgz?RhMF{<#I_@l(fjQgnlH`|vapfyJX|@=@
zWEf5tj*I&Qx%~y`v@Z$m_a~H`S(PP@zQ@+0BjWMac7YZC;E7)=;K!=?#$rC#uPC@l
zS3IV3!ac$U>G%6+t|1*#=JF+-R7IOticvz4NhKEX{o_^7kTEPA5~}1~^}6cT(O)u>
zO5niBcwVKcwzDMTrGZDw1<ooOAjUGp9Lz~=w<swB3lcmk6oi}q*+K1o%Jy0MZYL=A
zDbnEIccWE9mA#ae4CgT~qP9S)a_Gq*tfp(tc1VGUF*RN1D7-^1R*bMAt;a?BzI4$X
z@YRod$F<>Mi-|Ov&P+4KE`Dtk0>TnHCxuW+<w#yR00TJr+iigt#Q7@zZor0mq84z*
z;~fCTfZ{ZLEt-asgJOkCrVpT$p)_bLUlrn7_xi$QvHg&w<`VzLp)fjlCgYF00un(s
zdZ4CHH$T!osKI?KR3ME8eOuwpB@$r_PjMVI^AE96%)i?SQjNG08m7U6g&Ntx^ppkh
zqD4{-nFHq;^L2Q=pZ9O`d!DtvArxerFqbq9z7*o$_=>uu5T<)+EDq&(cxJM!G>T`$
zyRDpE)e>+37_nbn=Ef;lv?u)LF^f`I=5trBv-8OlfnH+`@InlQg_?p0!t&ioPGS4L
z(T{8)%bS!TSeS0xLA?m!B>Z6G-g8p1=mAyidb6E)uy`VpevB_*=dSxaLFO8<Q96x6
z^RTACg5Km&lIbOOO+e#6`Eu%{pj$e_^Vm1xZ!<8A?k4#8q$k~R*w-wQN7|87xYvkf
z;xKLpGG7mzdOY{T-aD&ch0I&663;&N%qcy+gspgDex%0hwpeWH=|EVP$`=rW%x^nm
zA_dFVdcuF?r(s6)ydBXz>B2Z)5TFGiTe_tLj(VJYZt5CZG9H&Cm+5v>0=CXA_-aa;
zE~m9<I+nDSAZeo+*^y4$H)*0Hv)084)$!ob8F{VE6%i|ib<S>AVK>rj9DNedrLOu5
z>2Vd#gT;!}IS2<ksNy6U<5JZI$qy4@@YyAsMc8y0{o8tL;Qvz@jI853!2wl&a3HIk
zW&Jyo66VYY{*Gvi*<EAmN4tt_PjTMP1|2a*e9oB7Dy=X=;S_s}+k!sPsXEj*;G$y_
zM?jbx4rR)|DU4JLs4mMuL}9DkSF$i83r<#eqTR#4!Dq{|gRj|Xd6*WiaW9zG(eimx
zyh4pBQI1`>V(N8mAaP5}w3U5mUifr>TwB}uRZL&}HlJn3#VF=ZI)b#Rtxz@{2i~PE
zVIYGxFLNSRzgylw2{w`vmeIAH=dvunY3d=iSDx}}&lKckf*(Y}${lUQ-B!%-@cKSB
zo!D&7fSJ5~ZR6(?lU<)H7$Q3@>n*OS0z_<!skwdIG!MuDV#xiUquKv7K&r7jta~fK
z*%)n}yxF|~U#HRw1D#Q)Xoy_0kpdxBHWyi4(t6a(@AAr#Y6@iy`u#RA9h1&juG&)K
zQv5Ts0y8Hxoz`1BhYgw*bw2Ms6jm0S`7c~;8RGR`3B{eRAqiM8!aQ?VKVPG!P1k(}
zj7fR%8ew!qiotE^aM>C<-K)Q;2I|8ZTJI%f605JM7rNEa#L*6@9B<6mdTo!V8ctGl
zV0681W@;I?k{K$@YOaT*ZU(iSC((}7f3@SEO*f7M5$L^A0H+9c;;pCO{^07b%f{oN
zQdQ;jzAPe}mdv2)CS=-0vp8$mt2K_BNh=NT&$n_{-G&mF*Ek%5^oLtla^I4kC<-n$
zq`viV5Y7gc-f$Y1Gvjo-5%+GT)Y?W_Mw)LGo)$y3OhJu*=Rh-@pwWhzg`>xrdhZsO
zq2C9}!ksrA$h<9Grk4UdVZjhe-#DG5m24Cv6-#I>G=MX_A7H`-oeHMupzvK9t2~iw
zrJC2ebMB96vlVd}HkbDLJq~u1{i*~erslLp;c#h-UE8*!<<gx3<wmp@>%$qnI}uP_
z--Llhw=;!wBg$;JM0ozD-Dvd`>t2Jke)+!Fr4aNOG)2N!n#7VcC}Rz7?`R%s*T;Ej
z4lF(=*{`Dc$s=$!KWOBF3qwGo;=W!!=DpP?$CM04Yc~(f00u<K4VLa9dcZ4B<s4HI
zaCx<uG8(t{CioIF|IKvo9HG)1ap9w7jf((T>cEIo`8ID8x%?(j_0ddW5aU69YwZcY
z#pR4RD_|GZaAx5OlRJhXf_lq1?E;Zem-P8jxnd{XFrhknqveGBfTpA!kk>Q9;yuZi
zl-}|W>-aOVll{-msZF8&KA>P$;$hdu3C^ER??+jI+832q8RxiTXu!}$YIo7$ZVp}&
zr5ONuWKiElyA-3oLfe2wVJHB5snohOM^WYbh2z7{_qUt?t#nz(hH5ZhAK=C+#l`J^
zFwLh-GU6{QE)7J)JkfGo4)YKYUQ=r!v~qq(5BFX}tpwPsNG8MZ=74J1s10a^G*2yW
z!c=ib0!b=+-kjmMiXVKb)+&d+8`qTl^Rb#mTYN(kZ?bq{yy}TH%#CU=?RyXl8MADq
zEa?F1ACT{8IDWYhU-B#R<C^MTHAL-)`*@VBhr3ih*CY(3Qv}yd6X1hZXPWGdf1ps1
z;pGLp-Dx0!80!iq^LUQulE<FzZk9&dM{1RTJ}a(nuSo4-g|f2DE(-I@!oJs=pG1%8
zz$c0reV1U}1>>ht^%bU2r1#je&pMg~{lM^e=Y#^|V$;o4q3eo<l(s9-o1b{hYmS^g
zJ%ANtw{F;wa4w7srcm9f37Wt=qmWE?USXKNX@^U;1Hhl+Md0!xn$)fZ@Sg7UM?wR+
z72E#&iZSc3VG})@I0x(c6U*sr=2U$bViGmWX6$1}P2TDJ=+$u>yC*2btWuT~s>q~o
zxQvcBs;X(H0*(R7;_DBeUpyS9=DBXRtcK_7dTAdwGK?-X!DLtSW?U1i@HbQE@7kkk
zf{10YOblkd`~3(1uOKQm6ir@9Nq$VsPA{zp1(5K_%^Uek))uJU`b3nEh!v7~HRwwF
z6V(^jMcx|-y&+U0-^5kqy%~*|UPuRT!zUU|vsP%5|Ao`}3feA@CUF)Sl!6118l)PX
z{b~Np>1=6Hnbl`+q@k<Wfatli47z65%zR9T7g@Ru_e*KCuFz!d8xz`Fc>%&eBkt)-
z@e1x;z<X9D?W4!z+kIM4qN;Sm#JYyiig!o>yZry0TR`OYVQgQ$Tw;kBLnd#j7GTfm
z!_~*oM4qV|Re-u}aQgv--!6dt2|2J3HnDaK+?577eT;Ic5_j0T7BPvE>e6q{5c6b9
z_G2%!&>Bj5<18uM-4no8nh{k{y0M-A@!VMPl6_GK@;eN?@Y)Vghqi?fSXiJOfwvMu
z20itBt}c|#kR_#ouOUnZ<pyh*^vr-7%mLAl`m^{B>5B?Ly}Up8z)xakZB4ncj#|k8
z1f%1-&!naL%U$EULFztRSY=;358FW&IdK-H>pNJ+ROiP?D#Sv66fYYm`7Bi!yULk&
zhSrQH=z=*kNqi`(o&x}n3;i(m(Z=)Q912Nq8JQo9frXuHx}&*6a9s!%65JOmC7x>F
z^%IRpbj<|miKO_{hE*eT4tTS=Brw#{!`M_@MQjY6>09ye-R{wezg+BsUDeGgHjx0M
zm1-tuc736ZEy*7*kty{9=hDI19AB6poeZx8vbKT{eUN_Er*{}jwG5n}yAq#yf$SHN
z9|w#7^_>GB)4sP{Zlb}|So)~S1JC)l$l>J*Zf0I~o8RJs+9URWVbILiN>Iem1bmV*
z;ZM@OdW8325`T<jw_!i?Ibu=;Snm6{XiR1y8_bMNV}UoONOHRzut4bHXL+_ags)Fm
z{1saN>;rVXNthnWeB2Dc8RE!5c3)hP1g$ywD35Tfd0YyBWZKVTbCqFuS<HaII|tE|
zz6ApsS`X9F!l@zG(Xw1+*v$Q@6LA45`V<7h#gZl<?}=_Z^#vLzgzgB<>0#~H3>Vwy
zP5s7A67xX_sAwFRG=@)tJa(4A)$Kt9ja!~g0KP3u^qi0P{=6lq{b)ZP2kQSk)i<;Z
z)R{)UnidLZ-=!rAZ|hiP71{Di13(Ij;I5oH_AWzgjbi%QgshUgBBbA!p~!cFywu~v
z!@M=qNtyrjdyv;s$avvh9(NHd&Q*4%E+_0Mu>04X52y~JTTqFCGqU(dmkm9cX+>EY
zQ$Mke#KB{z74z$f1^_g2>1GQ(YpiMn8{~7!w0Q4LwkA5iN2ALn-tiT}b+0z!ZW#>+
zc;2c1q2B@Hmq-+zaTjA63!Nn63wA`~k4`+${-i6Xck;eawx4mt--{+0qG7R-7&Uwl
z(=&6N#3cNtmBYA!hRVfT1@ku3^Ku3bgl+q2Q`f8~KljH5i?6?IE14_Ou6#Zr%|FOv
zWIpLGD4jXQFLb+9MySxywn4o8jdIZr>%;S9-})e@{KsAB^AoeLF-WQNuMx$rp)LfT
z1!MWW7|W=_E%h@2`Z;;|aR~i0prs~js-<(49!Wl2ELBzQ!U@KnP9{f)9yy(;&L78L
zp}XfQEiGX{@DWE1SMv-QlvM=F+JFKjuow~0-8WsGbM&UkTs@)NkaTyh^8~7AIAvnq
z-CTL+5*=0G1M^(8bk4<5o|>lOcTo?$F<@+F&P2WN^GxARA?k$-a0dEe0vqM*FCL6f
z4%zd1n|I!Z0(P@E*xkAiV0|UHIY!Q61D>_#LF|V}r}q!3m%N6{=d_-rD=AuX5H!)q
zp+LqMB#e<d{Q-g`;VPsR&<HWFwnLwx8odP%``Li(8Ow65g+jx)WMJW16bgUtil<Sq
z#&bXn)P<Z`2qN9KGNXqpBeyUHPN9NfVDpUCGvr^7<;^;O7>lnz-Y_AVaxMjg1}KYu
z593B(2-r?NM6)99tcH(+S;_#%Z71KM|LY&1hx8hPdx&v+nAzs|MqAr3WdI(Gp#MSj
z2?`URfbJza-&=dDe1ALksD+wj)?qm+n?lGBAT6Gq%%KEhIb)CEr<#+-JKy$${2F@V
z1Npcl{!1cw>r?C9XUrclX?G!*Hpy6=YJzpiN#8m0<3lxxJ>Bb5Jg<SybSktcvRo10
z$>XCYdZy!0Hk%xqrrc4T&=I9!LWi5Q#f1P5scFH#g`_N&F9x<yVefR;{a2l^A6UU6
z_p8|zZ!UZJyrdLb+pVPxCP*l#dx_FBebH?aF|(Yw&lJfu^h7w$8K<o?^F6Z_;^Z0j
zsNdulwRo{}$nf@R{w31NS%*D(orj5V@z(2JpoZQ4I_&+DP06Z{hSG}JEaaUtP<`$o
zK?zmhLsnS<>S%g$o=R(aOnTYg)z$|hoCO3dxL{U<?aV5kn{XW(&<V9MX`;8Hlgen6
zD)N{R<6>kB<ss3Qc|Ly9X?R(4=xtnYBzJl160_@?LrKj!-M~2kUM6X^RmYO>#Mv%J
zAtyI29IxoQ#Y5{pH`a_kfoSg2#FW8Oia};ZXJmW1;4J3gsovuP=HYT<<RQ|Z;D@v0
z#*BeOT*t`DJZon+M3#|F10L`m7|vvd379%oQ+QZFVn8>+DvM04@!aeC0nZ1jbe!^p
zeL@T%HX7_g`QndO>#>E~&#5Wv(})h74=6d$nTWILVX7-n@s~y=vE?5d-MG9_?!5G3
zDZQxW|2F1Ma~vY$qb>hY%JOZ#*W8q$y0tf+Y@<#hCelO`Dglr9+LDWFzA!XJJdH&J
zo)&@K$u8=yWfhF1DxEjaIZGKRtX{`~>VPwf%5qf}HhTT?Uaj(2q=g%u0KcF3*<QRN
zEU$KKU%mF$Rc5X?c7eQJSu+L;a{;8GO@+fCA5*Q{NC6M^`G)17Mg$6eImY782S(d!
z-ry$Qp6kje2PhXK%JjbRVA8Xu2q3qVil1U1;#~Xg$d!pqDD>0&sVcx5q6HfmE-yt!
zws<74$ZHo2kj?+X@=GE^|KaHY?@$t-D+dW2EL#Ixb|UbOLR17OwGz=uEOAnXCr?8A
zC)U8#{-#&$BjPwNiCBv--qR|(%}qb<4(Mfhq(qi2v-y_Yd*Kw?*4lv_T)Mm1K?ss3
zpi$d9=Hr6$=VE8d#7o4iR=p$}XE}xjXON|Dk4(*nG0+I>+5wS5P}qWH)n|HLy9n^y
z*Dx-1MBe$^gX9=Q1f)3}1oydvMuP$IzE)U_Ic)Rfc@J#Y9$0eh-;<J)z1R1`vNPX7
zJ}vo#Mx&$=oy>ZqdPQV@-J4vo=jtmAXmP672;U8aXuru`)G7!BQNd9$wkOah&aF~)
zsaxoY0;HUN0kO@!iyox-__}E4JHcU!hWC`xm6|Ono&+`zEP{=`p1<L(R&;r^6BrTp
zA(cSBb#gVTToroF6{*2MnbPBt9+Lx&ys^O8=lX2)RCzxD10+X<2pD1Qs6SOgj=^7k
zULXcMlEx*oIzuJ2D;a>I@Ld@w{5;Yh2k`gAnd>C<`EodB__Rk6Row5Gp33~FMZH+6
zY9z*|X{o7+;Mqe5E?S22sG`BUz?d4%+)RzC{<hQ_snme_5OF5ja8=LJIOz}6{Edx&
z+B@=*i0d$jTZ+A|&*M;M5;4Zcddd1Vfg&JKryG(7e7Iazw9wKKm5^>a)r1ZFDlBb`
zWf1rc8Z693y9~OJ`#3Mal&G#7Hq?Mg1j7CFu+aAP67Y)gG*e)y3_R8h_kYlOx9~ID
zLZCuA(1PXhESn3NZiQ{)`F|&VQ9FV_<v1uI@`hOhp$UxhnHXKR;b5L`-Bv&MJM0$l
zZ;`;muw}@EjE?tn@s=0UKWY4?A@l6m@ZIYl^yS?sz%kdyx?IAImT~$8MKfGb0bfu3
zqn%TrnB|^&<zl4OhZUU*l=FI2T**bJ$4M6(I?EJgs>8T;{_Au4Co+coIK~wSu&z=<
zSFuw5>hGGSx92nf2oU<fI`ir6Q_jtoP=`F8XAr7xxjkO$tmgROi;2jzUX)-j2P6fp
zW@-P2+dl_jPs(=;Y+51JP5m(wdDV1jhvUBO_k1^M{m#u>Hu-|ppB8d3wJG21!NW|o
zUHFWcu3(g-;UHmMZ;S>$r_K#BnoT|Kl3G!w{qiE(;I?VyoYEb7Bg4n&lIj{w`!cA-
z()dg}O0x}U;v+pYOz@6HRbfnjm%S>Yn;c*voA&)XSpO6C{{Vna-(rvUiOwE+PV~r}
zK;^zC!a0RN5FRG8Bb1OSqI}!;`dhmVCi#yvWnswAT?j(}t?ni_9_;lrs+%gi9b5H7
z6<z_&%pAji6vv+n(edV$1lvn6b`YT;|F2Gb6wK_=9x=tl>jMU+*!OXXWo20$<kl|*
zf4?{HQvgl`NjsQ%e1^`8Lm*e8gtjM}XEH?z=}G`xjePzs#jno@YCgRulvcXvZAxz$
z#=qKgLKSWRaZMtqDn@M;jBHa+jOJ*bS+Pu53{`QE1%v>rABXj0#&@X1y`&AdynsZA
z8^o+&^#fng3MvWGo`-Cw`~{f)KaL;cem@(LZ%i0hC2%`6?@8@$;8E@4W#{UQr!)hf
z3Ig=Fx^kDCJb@%b9GPJp#)xr^9>&{?>Uw`+H*=^Xlpy#I5izNgxI>q3FY>ppRp<OF
z(_Onhe{0mtzXQj$MFt#YkJ_!U22zHvaHvDvG(*r%@On}3{hd5GtmMLfQ2jvnNoHA)
z=_9sat*o_PAo%7M`T%Lhg@bV-uSm;7o{c>lw^i&&HX;96)@6ioWn^p#MU8Y+H_22U
zip1z3NVp!Wh{h$96C4RiJ?NxyN?5;*eeje&C~;IpfiF8?i5otdLBGz!4@c?7<gOp@
z;CQmjr2A;|6u+luxpujO$`JtTnZIJ700k!LiQS;|z0El!c6-wqT9yQr{m0k{)s+x3
zo^ai#%0f|vJNq^NKf)XW5}rzRD{7#W2P-aDdyYnB<R*~K7g5_qh7N{nmT&((oNrb(
z?jHf@s-uQn=5F33y;0bAO{F&f96dgZlLlUlpq&wO<b=!0mr{YUO(8q<19L4~j(?FB
z?F0^VP8Cf6VfSicbhUPj&%@h%uwE8LAul-zMjYZ!@!4deDH42=tS-FrT~mpbS<|Z+
zIq^DSOlL|AS~%-#vv#mq#2}X#GTEHJgN-%cVw-~n7HRJtN|qE`u)2Gc^C$Q|NZ#p-
zM@aFD=h;#iBD^$Js-cLjcmNH<Y~O3=U%91Kk+*mF0@>US%k}E{4<iB0H_t(QA(&f~
z^H9Fjp{GqC)fZcEeTl%f$6!+fXx4X>HHZA6(qgkA*mdbYlCdl1c;Kxa8Klg^1tL=R
z)5F7ho0b2mZwVVYQOsTaw11ifV_?NFEz|uah$sF`7m=9MA(Uf@@}Lvzb8O`0FF60b
zQgp2JIyFiVT69WHCfmDsH<|oawX>xCW-X)A5;HbuyZx(JXp*!B)bH-mnFnepW;f@}
zp>J<_r0Y5}p~I!dLu+c8I*ljJs>Hx*Zs-CZ<hPxHG0Qz!r@4G-L}-faF>*+8I3V|=
z6<Dq8Kiywaag2KM+-Q(MAnn~M;pb7J*MszmLb}0@G+nFD^)OEnFA%X+)}>dyuY84=
zlPQHqvHTnl`u7vb&6kRb6^%`k!lx5Bxp9&uRDw=&UTd8^zY$0+6YpYG0As>BYPNmH
z?qIF5<KR%YlF@Y0sI=kB{0a!t_NX2DoH0FjNWugXSZ>6rCgf30#9$6{g5+Z3Nn37C
zdlUB@KCQX85)>ix&T|EV{kO<3{}P%-FZ!gr8wL_bwrvj`Uz-Y>MX7Y-Lc}Qg2U4j|
z$fs>;+ym@17nwOp9+y8As|0gXi@3eB+iKQ+mp(IVv{FXp!?Jhm0{JR$jq_(e;r$Dt
zzuD5@c+tTzp-y(}<+ca8ZYa))La|^1SQ1Cxy(mQ;-1zX0FXHzya_p|EDKJUvKams+
z13L@hNZeF>5;EcHwt~+5pJ*9@u_(Z=6#YeJfmsRRlUjPT&Kuvg^5*qkRUlE2YSP$?
zak~ltfUq#F1Ii4i!L?lIh1@k;C)*5TcO2Zmv1#1$A9Xt;+};v8(gzLACVj+}-H98S
z+Ds0}wgWQfUX&Ob@=O}IWU;1smzD}M9@24B>R6O(okSHU+vm-F@R?sO%u@1&)EpQ$
zW>I04UOokU!Sin4>}R$EFnIZ`)5Bc3gf#{~JO~uiard-SfogOnW!it(&Ebx*IkZha
z5Ne8|^frt9XRdM?n(SzHpp1J*=P6w_rHow*B(%#UAhWcPWMV<!>rD&%yiVt;bj-Q=
zTqjqPCoTqDWuIvpP*w(~6De^s3OjwNCo|RVIKj^%$g$T9KUV({2!6vnagt;BKeS);
zkomp)m{d=vJ4?UaRizB>8P4zS^hwNXym<>R)TDW<?=0lp>cQIl*U(U}KfP_&J}20a
z360)%psOwk08v1$zc51!EzSiHkqwPm4YwY8S)^O8neI?8R}Tunaq;@u)kkjDA}e#B
zeU$#fpPCWrE2@JJSw-+{VXT`)#C%b>ChS=kn!F|w021dYYj<&&Sgz4^(I%zmtpX#6
z9k(Wm3h7#l|Fsn+sA+!MUlL)Mhl_f&a*y<PEaR!`-aova<KR>LPEXpjB8miZ3J3vo
zHtKsl@u<~C&skGhx9rr8uCS}vt8xIcRb(XSA+3y24J+T!?DbHU_G~G0xf)f4RJDvO
zY89hB8XLK^gD9y{{bzE>M}^o#4igTTitt!gd3mwP7EwHHNSq`{@Ck&hXHNGMLEs07
z8S+3fNlOVKYet!qB<K4on>C-d8NP@HVMk+dFiijUN0l$+sx4%ZyO4)1!({lX-Ezp{
z!tcNH9}DGzpqBy|=H`L^GQqyJiFx!6pz?&#wb(zA&Ynkv(rHk0D>P>l@9`0c^CVZX
zn$Q;w+Py3ZF~=lG^QLHvV0X>{x3;APcwzup1?UWTbW2b|Bnu*pA^~MVfe2Zq(Oa()
z2q7585uke#ip=reSr`TR+1r4b*ZYUQ;(HeNy6?km_X%#^aa#uL;K!03#x%goYtMgu
z65jA2&l?zt8++&wmNVl@TWX4p{CBTBYf~7mJ_E6CXflzH1IyH-n|XKEQ`z}(A$9=S
zW^c+JeTy(Kgs;W<1henCsFrU}l~=d1dvbD;2Xb#}<3EgR=4}I7Z{9bM*>cor`+kL@
z2*x>^bk2r@>hW{@K`yd%UGF+$ejyfUh8G~R1WD`?JuZ6_>cI0I2p!x{A<XSdgeW*{
zf~wNI_C<|D8ZWN0Evk(<PZS5#mhKK3;_=?&%ZqZ`9__b{B4T}gz?lL)IQSo%QtYNk
zr349nw$gRZz^LVU+W+pmq-{3P*6$D*UKLa(*ZobXxune^S5@Bohx2NEEqgVn2S=Z_
zgB%~*Z6m7671f$;wLeK2)Ei*5oN;O@%tu+;C+kS&$?Ap|ZvryRqVU80m4S~(XD5|h
zAs)KZ5nQjXzmO70Ig*cDdv}2$pOKX_R!mVL<<u`4Lks?;XB0a9m^p=^@^ynIN2!21
zv|%rsB{%82W1&T6B6%ZMNeZ!izgzgyc{9&6(3*;Z9v&g~0szONbwN}Qan%e^Z1uRY
z%e|&ICuwBsly{Ji-{*QJC`FE}Ib`-q5%v$<^(`;|*p{>`DbLuA7TGfecNu0nl1JvL
z7z=6Gf?@R-vFV_~vNllBk6U*YPNs-`gd!@OVka*<8qDmP(s39Lb^^>sX8aRcvmY}U
zIS@xz|BK-RwwtqZEO`AH>*U?WgKQh)C;KVqTtJ`Kr*;<i?<Kyl=kHqGCiL)%#sX83
zF};~I_pFzXDsH!ZhRPGPR-`!&5h<dP?##`q^qrevRcz*nPF_4iprJA^Wv&9_8y(s{
z`{TV?-#%_i3bd48t$o~9ggAxVbnoLqI-Ha_I71%nhx|bKP}6UhdF({&>6h`{Di@ZL
z5!JIrzND_FC)$`_-_G!6?9N3He>~RFxk=x4<4bhYsf_A(43_9)y{(BUAsi(e^QUD(
zvTq9hHfbTnKll~*j3>LDwo?E*k-8(>m>jg+*IC!zmS$$%gNA`wc+w8l`&hSzzfrHj
zAOE<>0GUXv8uS7l96ZB2i}&457Us_0TV3MXWANW_PBK>;3Sf&<O}y;^k8Y63Gp&Sq
zQc!NAZ#u=Gvxf29Z&OIiNBv6d-kf90QP-S_5SBwPy%Ky)-KNS}SD;tgP*|lc2bE6O
zPP>JQgwkGtxpcnMjy%^6-{AP{v_7fp#LSn4@`11n=Y$p&6}w0L4URWYXcoD?RcaDk
zfN80p@sHD73K^;>or)z`Pi`*qfy218ThrOlaJ<KD5dW>3f5=E>YLQ^md!|9V^~ec?
zzM<!2Yg5S}M0cqwRi2-fiY{6WC+<)|sI%?S<2d#<6}row1jtq4^e`M#y3vXekn3sp
zfD1m%e$qQ8|220>*sF8~i$g<%AC4^FJ4!M*+Z9%$nzh)XL!2hR0fQ=Obse`Un5Zd2
zvuwAfeohr88W(soX6$^EB)EeStxSvH=Qz;JRCUoaV}g#6!4Urn<*wA4;~zT&hBJjM
zcSaL)Y)=Q_pDBtHyDGOm==vVpEkKF>^+1lD_&iRHpnR>R2hZN*N$gNQ(=`hMA58&h
zK&eN1usZixVX>O-k_$h}!^-_D*-3pMP+9L=m(g1Rkl8X&H3O?RroRN%B$u6{F`tPE
zM`YUk>6<@QyjaYqw<F9bs3ws{a*_#PB1Xg7jHkH@0<=}>^(PriT&>EdcmJ66kQfF3
zs^j~!XvVoT{?`l0IG1Kdt1@t~`7p&YoJkRGtHBACAzr@8CIfiq{^IDqJRF1I8%=Us
z4d?QXnNFF08RmUS#Wemt0)nZ?ZGT^5`8vmi`{67Y`Eejpk=Z~XLP4_UH7FSgiy?ZA
z4AWAnIVLJr#*v^ThNw<R;nU}vJ)O?C;$~7nx#0>^|I2$=!%(KZ@Mq<(56!-q4#TcE
z``EnWDtdQImcPi~l)#Khho}Vh@{N>aVq#Bz8KZRg;e4{V@^b>#4+ABp@m8>pC&ZlB
z=-F^~{XtxV&fC04Pmt<|R6G7dsvl7|noYaBgfhaQ7J*{+nyJw(C77#JHKfDdRD_ox
z=7HZlp5{;maB6}{JcMfrCw2r80Cgxc18V;CeHXDJhrglZw&nMcEH&@B^pd$tj<F9=
zzWeo93zw<-CLT{$WQJK8j~%@-hfCzobsfbNi6NUijK-bbk^W_z5`oH+xc5>XzK%&y
zU;~D%2(M8O<=q-JDBEqtH-my_f>v)hAArHq{yHBvdQ<+GJKuQu##OE(66mGx`tra7
znH;Q=K4<C?_37UuZk!8r*lyH~`WgbwQC^p6qqU1|eGMNzB5K)7t)LDoIkB~zC+t-^
zVo~@Uq?eSZDjMMrYn5shor84KqCFMi%gL{O>abn5$6k0G>8a48(2j~J%p|k)E^<Jc
z=%Mh(;9;dQa;_BO4_kg-jW>T@Y}v!`!An0{HGGCICn~ShlCgW@82zd*q=Zclu2e8M
z=TNWD4;c4**KggvVMww^$E2yvt{j_+W_g%6!r?^VGzvJQ64o#bns^r*4PKaDY!niL
zGjSGR!kW2!HC=sP^-lfNV`;0KWg&3WLa)XRBzp4O%`c5{w=8s*GV-!!F$mIEM=Vef
z?esUV7BY8u$amgT6qInknA%^-nZ9a3s?`+WCzM>N_<Syx8@1=8oi#MIAw`b>mNoad
z1g<7c{*anRro}1PgCiXzZgVC+g16nbU0lR4UQb?!^Yq+BN#>7wtMGR0)n8w?oub2p
zme{VCIu9aKLYd?;UP%Q*K5q=#Z;F*&g1(0?R1+>8T|3)_3&;`^73it01j-MG6@JWo
zURKXFl*e26ixLa`jECnX4N}S9n8e@MhM-p}8v@?vA%kE<)DWZMXDdhzYb}x`qGCEt
zSD=zY&Fo+z)up?%pOZ6F(ag1BKb=LHalE*VS}nu)+xP71$`~O=M<4E=;iQ=b*tV@!
zLRneB?w^LBXRNbXfy`7{$q51iH;Q^~!U`Lv;`Q=?6bgAOr$qBrTp#d6F(cdNZf3Md
z%Z{eB!Pzjc)hQnuDQcHN{;vH<z_N=-s%f|9J%WKuI#k)@<a&EIwu-dn8M|WvRd^51
z1f$WYo>}a}9$TeAQ+5LL6OEF27;$kOciiM_HqZs`fPqq*)4UqMvxlwzjF`GGw0vh4
z%-MG8PqKr|rNP{KTixDd?Pwtp`RhbrY;T8h<Wg8v4=JPBlxA2LWPvDnwZk!I4CEzY
zYM>qZZ2|!?U5=A031RjzK$;jmk!j8gQ@)Ep_5!aRrp<LiiLIs0Fjaor!&i^a&XIRo
zon3#5#fv-uZ%#%BO@WB#JnlvXLcj@<S|n!5lM;uDOg|3l=|VJk@BoU0lt4F`pVf2G
z-PVvhJ{ZYeV)olHAZV=r=pnPH%jqA$PO3SZ=FzX{k@dg7wJ!EOh)Tib1xRE7Jy*ZM
zkcSXn_&Ze;=T)`}b*SNVf>Zi#tsEHN2MObP-D+YdGvhL$B>Ekr98;Jl$vr!bgQ;Rh
zgm-EHBwb47z45S^4$h_uB`vf<G&gF7+^30$Kk9)EgnmMBLy*!`G3{wzygzkg4NGA5
zcVwj6)J1m}oXq&{y~vyBx(iSwPRw@Mo$f(<C?nE9yVPO0&RuO)8s{R(;kO58!q&<O
zEG*~wFX&%X5}l*E7XvQPkcG0~b$x1UCp+M{+%}|o?Ey`He8RZvH(kL;<d@;xz(C6l
zaHe+q{Yo^yk48b$$KC~>9s@{&`ma-}Vguw26DR*ERGpFmtz~g>e=GleU;g&kFsgDg
zDG@(I@JS)WQdnnTlbjvO8GQ4N|1r^7+Ol=JYr~G;v6153lB}zq^d8o;dnQWEJ@`wl
z5G&vQJsZ`PRu(7adw%l^>-ei*5^gXv=p`_W)5>A1VcUsW_V*6oF=yR}#D{AKobX}*
z<RQW3y|S2sm_b4gzw`FedG=2w;Bl;u?tM)-6$lT!K}SGiK0>W01NE;#M(^H>x)ZB9
z(6ev676}o0oSk!}p&I7{=lXpUg~Eic#B78$Z#Q#J+|GVWp}IpxN%0*F&^~tG`h0EQ
zvnfO2#w7FaLWs^=EtFE_4aGC2;3t6uKlaay{6Q;zzTI~39Q&^iG8Ae;ckPJM$D&Lb
zsf;kGUuX|e$oR_`28Iv$BXCtSxc^8#6O#RLdMvMf4428j=HkZWnJP`@h{dM@87g{T
zFvm0N4ggFu53Q&1@T4TK<yT-)Uor^IGI+Z(3e!Bqi|;sZYzft8t>+NkRHG(nmN#n$
z7{N}IQ)+T3SLkbx38=y>=LiGJ;0ivK-bmaYj!izQDHF3$YM+DsP+Ye`1dI4jqI^+@
zPl{C4R*Ev`_F>@HB8TI$!nkZu=Mr1?5Tk3$JDJq5u8g(W@(rM7>*%f@p5qtekOPd;
z`+e(I+x4=6cqb<7PccSOuCV!|yI?yK#qF~C9&`_fGD)$jYV<v6#kcqx#x-VYO712i
z8rhJCP$Q|!<0XP8J~cqaw^K)h%=yAaEhKT}O)4VTs8MS>Q9vzMS_Ty2hcdqOUo3ze
zXd**HVb7px83k;ST*8TyaQ8B4Ycl{Mu|~*)@r~>Vx?<bAO;xH2FWJYcn}P`udF^3F
zk=}>bF&7~OqpPRiPX%Df0{ErE5k0;ZJREuU`7z9>b9@AOt|x2rFybq!EB-}d-E1K8
zyn5?jC}{b!>p3GVrU+9Ej$;XxQ{q%I3O`Vr3#F*QNjhKyQ!$jDFn1Cpv_D63@A?oS
zs_RFJd7wr+q=Ak`6lA%4yjwGlFA!PoRguo0;x9iKJ3GyDMmU3rf_7)#l)4DRAkY92
zpM-dsv1%N+*>wct@?!Xk0=h0z8K#@opB^Mya}naXI3%Ttl@&_2baFyfFa$_b0v)u>
z>3$ew`oddYj_pywr1xA7xann<=-d6zhDll(L3mfX(A*AR1})(;nc=|Tl&2Tg0WX<p
z(>MqR##^z~0)ck5yB2g;gBG{jaR)hQvNPV`Y${e^7Q0qnL6z9P^8f0GgwAXkzt*7+
zH5I6!6Wm0c%O^SP8xoU4aKK&rAS7~H)5RtHB#X3E30FFhw`3-3#|PEL3K5gX?`Ozl
zTScJ9Z7(3fhL{ilL?+Qhf@Z18Ke!Og<Mg0TVi5rL(ggNi8fJlVwP%nA26JToy8rwA
zhAyqoUM1h7_nU@Pi2a!V3#Y1E*qBtB0O#^auCaJFkH?BN7o%ia$IY_o1PWDl%Y%g?
zb@bF*Fki8FtX21A&X*`NM3qd~-G-mCV8&=fp`|ROv-tT25SIt6!CLyKKh>=eZm7)q
zMd^G)puMsEbT3-c#yrepqH#ds6!-*Zr(FJ!4l_U$3tep98Ohg@49b4<KzPS%!FvTz
z=s1@j|M<R$dW$qiy~yNoS=CNfv}APCV`gxrX#_gAo3Hz0N+o)J8tHhBZ9?hVmwE~S
zbcZ#u-FSHUhqJXsKyVyzx0ZFzYIq`ch9nA_iqd?d$>*zuhqH=b_raspfko+SCK?a5
z;B-x%*<OF<N@V)14B3)hjRxq?Sk;pEhT(S=tH?61xMvSJcl_k(pk`%;)d3cu$*?D)
za2p?%LuQ9`ad2a3iJj|U#>iiEOk#LQAq>bQV~YcD+#v+07iD*<j|;dk0<VJO>KN>{
z)8f?<4i<I)Cvb_3M`=UMyy2-$)UMig=tWx$T0MDiG_&U`4N1~$6ft0A`^gb=iWyWM
zGM142yCP34{?He8ZC}fNx2`2t`P@HsIp-Z1;aO|&R1Z_3NcUUPvG~_U1&M?RE>2s}
zP-Y?yy8ZHog$4czUYzw($GCc=?uXiu9_2bet>~6yo^YTXyUcU3v_OBDGUHp9D4vNw
zJ!RwK))1WeID5znKO`~y;};EPS<ydV6JM+~|1Wly%1<=yd-nWJc-0M*bf3c(tA3lP
z>;C-C{IXm8EUo=a2tTYJy=!a{iH9GHL+Ot7Zhyq+3oC$vwk*87%um{b>r}$tO)HVK
zw>u(oCy{Z+X>6&EaY-{vWpl?@N15lEKNm`{FM6{*ecKgQOut<|fs^fAkZ9!Rv|NgD
z^*n()uD}2n@=+a)v_>6Zg1atnc+otfOb;FxFof#=`ke$2?|r_G5dn}2a|Yo-lmHIA
zJ%CC)q?NY1eIeg2g@h6KVVpULLRKHgYKE_oHc~+n;YTm;gdBr1H#L7ILDzY5_7+H|
z8~06TWt7(DoyQY;R&?cx_R_4aKXQq#-hVZ0=QAmLEGm=WWuFfvS+N>9vgKhcP8sHc
zP_!E5qCQ1G<taf7lAic@R{a1RU%&mN48oo*UJyq0xB0u$!FKupv28IH%+)OFNqL0<
zwLoM;dukZGOQbc7wKGB}P1DL68);xMn|rNIIL_gKr9iBVVkk#+laFj<yQ-;DWWC)o
z3d^ANsE+Hqu&P@l-|wgpzY<x9Y+u<pgXO=p9+WDjCOq!;n8F+ulIBWqL&xiDA;>nl
zLJ$SsB$S$)jThZyIBpR+^C{Rd`#?nBoM!Z$jEmqR)4w330PlkraQ%;*J@T4x0GfQk
zw2Va_P;)@p5?E&AKvl!8R^~@#Ew={hH}hc2st`WC#)jFyJho&W8}3>!FvSRT%_&I8
z_n({Ca3`6EcX;B1zo7*|Ar9fqB+1xUx)_*2PSCn^lNPS=Vy6s8v`w87JPrDD>i571
zVVZL1tDN8Y3Gl(o))R^q->FEB@dB?`qS@KJks2GN5mo>-7;elsK0Wzt!FEG+m{UE+
z)H<qVZ#@o0^3icGeWH}Ym|PCWr}{t-!>PTpVb_0Z%4~K<J~6?Y;Hy9N_1IY(%MaW%
z>DU-t^GEAGLU};@kF?=#co_mnfL%6@8jj>qGkfrscL;_WHI3HXn-Ll8cExL(e9yx+
z0b6t&{9dSC|MX}i^S3`b4<L>nni^A8TZzwe8G!pKphx^MIE@-;9&(u1?*4$P#G0e!
z20WLR<QK`uLa<|{Fu8q>$VyPtz1dI0dCe%yi`Mt@R86LjiVv%@T#ny&LEkA~*wR;p
zy5smj#Vv&O?H@7>5F^x&kCz9p<&LPGEq%MjXc|{HvbydWV(8dE=Rg*3WKm~?py?TE
z>kvgb`ykGYmKBBjs`2}&&Z+`Bo`>zs{kUPW!4v_m3{L+nVbA(SH|YJa-9SBLFix!=
zImFG_)P}{#IXN20?xYGhwT9TF3lnI8549n6EDJ5lv=pTbpo%n+olfej;|!?436je$
zW8<v~s`QJ$B$w}v8HM2hvF5`RZd|c2!Mx(gZ~hIF;D(Y9XR$v0u~dvBNu{7IqE13T
zC%w~5IJpL+*Xl5~#`rCoz&&Zrd&b&{3D<r>S&k_~UFkCorJ*3ko#Z0OX#1V3(=$y*
z7yylp0>&2yOYVkPNQD6vu^gQUQ|n$NFK_mu85IDdw*7s+aDYn6i7@s~C3l8atc+^&
zgBAOHlj@;^10}yh*t%a!aLb81nmKCz(vPi@5j#$)M>pJ1$lT4W8$LW!gc_ntuYiN4
zC?Zkda)x?vF%xw1jopfJ%T4TW+o#2hFno-~kV@uMC-$TgAGaEgoF=P2_VPbYXJZ5b
z7o^y7StCQl2{Db&i8Q*m)>#oZ>eSLr!OZD|!*esMsYxRDJvda}u2{a1%YAvz$qcaM
zpepJGn-_=dbfBsTTlcs7u?brsHd7U#PYM>Hm+XDdL*`MQmCq}i5~@3v$0n;2Hl<x3
zP?nC5Xu1DiTuZO@GZp6{LeU*j!zE$#53?^7Qc(D1H@#@wr}o~q)Uc~^^d)dp9_}KD
ztkuGfp$r6Y=Dz%uLnMk7iV_%pG1uaKZm4||yKgJIwVy~offL9Bu%n7h00Y(N3JoPC
zEH{MQpe#@M;f^5+=$TmMcZD=wIbqnaUFBx=S5RAg!Qkoo&{gu-KOdFeM`O-4<akb(
z$sTzBKzL=Rwp<T=hkN3a!%I2$v$j2n?y`DLMxoWLuHGqz05S8zQkDY2;Y#hRd{$Gf
zpS+hXXm1qaliOhk&+dzr0a?T3QCF%Txj*p(qvl$Y*tJOUar?rP*;nzxkHeOp285Ue
zr`Jxa9o(;%+qyHG-of4Dg;4+M(0fhBA|PsOA!CEoY4{#mBh3fBt|ldESO_Oc@&-=B
z<hH<iO817mjE{rrOZ(i~d18Wisf$POzDs6WrE{jBCOE`*Pu=(Cozo&X6_w9K7{d*R
zl!Imak{=k*u(!zrR!27aUiyAm*r$oYqY|k;2_GW4ee6OsoXZsDQh@ElA(tfQ*FHn)
zy-7Rcz3k?{Sz1_XMx;-HnCC@Txtwk`pbBAdH|JupI;Zd_nI~GBQRQi>jxr77s4=!2
zLlkD64))<?NplXfDpXM<kuQ>orl6gMlG9>+X+C3(W0xf~M5a|Y)i>$~=Fni?m}|Sq
zaBxK#{30Iq6St5!*ESf?*^w#{d6t<U=*zo)D?NXJMlzFS(%L9Q0Cfv4#jZOlw9E|s
z9X!weSt`^Z-s(QUDnGPts~>w8Ybp?l&PA;G&QP+4z^0=@TBgmN$!3d^ZAM1+59OP^
zH|Y*%(p#PY)(k&N@Kq0j;dA%MkZd`vV;<(0b>UxQnTfYkhP>$>H#nTM`q%YRkt1H-
z?|u?|aV4uI6aQ$~;<on1>qVjmV8xkb0G5aAP5}zm1Ff=6$i&tUuZbE5yS}9?L4|d0
zA;|x%K>g_qcY%j#IFo_ToRZR~g|SmBJ21ueqqXNN`#*`a8|=q;%Bw+a>A!8}?ZMwL
zv3K^d@Z}L@PZUe99Ur79+|fx_usm7@nLon5ZoxDN-8Shg?`aQnx>GD<i!o(@9scg*
zFC1xoKl}#)ZXs&4r(Je|P3<bA6j1%2t2vSvEe(W3CS26T-Iiy*9_^mq=w~yC<JTi<
z9txJ8$!s67^E$F#Qp;TCQz68WI5+?V_CxKRPE^#m;(kv{PY$I6VZDN=;~kygh3?8A
z2TZafNGwbqOS5eG=3RxWu(oxmQ!-UgApPeVHCHg!>T1QLiolS*&P+cE+MRfh5B9<j
zR55_qSNo}A2PFoGQf8#vH!jM{fYPG{F>WGNMUuQO2snZt|K5tJJ5?&`{FgpWIN7jZ
zGvV7>qQvEN8$#L=o*<o9!hAtEF={R@N->`oS)Wc1)utc$>=PdTRx5%|7Eq?EI5-sp
zXRCM=;IOoXe07>T<;8;FXzAs<|8SSz>3*ViO{l#5%P!%)jgQ<@G$m&eQJ#?KhQ9AO
zPKQ@+2R`<K2q<x<Om!3SDi7TbsEAvEzx^VIL|p99e}5cdqU+P=rLF~^M@7}{oYWFe
zCmp~3IS+I`!XCjS+ndstJ=M4in<t-w4&<{0gz`zH693=~Yi$pH$}AWUt_T`QoxU%f
zTj)fGxH<-_kz}5@r84<*r|^!nOnTqwH9AlyHC*3=!(@+NL1>b*UC2>UqcAMf8n>%I
zmnv<F+A#LP!ITPq-GFjd62m$7Jl$5_NLj(ze9){Ash5@mwRIW=Qu-9zdLi@y5W|bo
z82smkK?Y_@i8QQn*;2&Dre}umsWR1BJ>fHPwhQi_m%(ue-Ehajh6S)=x`k@tHvD&h
z>M?aEH9`MW%I1t9<QZQdHU~}6uZ{PIJ`rzM7$?!=Z>2T(_=cMfhDcB{iIqpfqe8-P
zbd1&GJq`jqgp3N4N(7dd5UYvYt3fk_EFkv<r_EAHinsS8Bz+t<R7B)SVyz<5Ry4P$
z|K`)-wtmxvg+UMhbBgxzxB2;T(W}(VFW{ylb@I=GNd&Fk&pO1TdIL7qgZQ0VNKF0B
z0IS+zw>p80+apURgx>!Yg3v50PV#4i{eF<hodCPn=xf%n<7bx~V(2k}3*Z`EzB<bJ
z!RA;Vg6^k_WTAN_*Cn8b)gVP8U<)R8cYh^Z&-DeZTok5BMz)EUrVz-fEQuftjg9X0
z&?e1JPM6M!$=nOdcw>VYmE|QNOJ+ftCx$HXg7u#KLnR-n=VtLFc3tAzow2qMngj$T
zLL-Fj<FSdz(x}{zZl%6moq=CIT@~js&Kf@9y;)EiJ^z{>&w-9Hb#YP8V9Cv}#Lf0)
zKtzrGFK%Dzy(rA)m8)eT9`=MYNlpFsx?=c8q=hCH>BHDHHyvw~tmYCCIdMNWZ?_bx
zHTrBI?IoZ@TxRhZDvsh%=ILOO8Qz}uLzd9NcHLhe5HbD2(ORY_Py4_K&qhHdTL)cj
zvEj8F=j3>9Ni9dd+}w3p#Z!WoL@}|upXR`_ui~=soluh+Pk!_k9sSEwb<RI?q1?Ne
z?nLAj&9|BgjJSy|ICCxdq0d(81$1Y5=>~|=?L<mCiIJFT7*I`TXaTTr6PC3CWe0$B
z4YTymCjyZHZWU&v8>tqo<~&dIVD)_gSq_5H(eZ$<Kt3f$(fPVg7%IKwP$-%r&ib-T
zyBiTtWMnP%eM4PYsfZ)@2;d`(lb1U(K9Hq<Z)40Q4F1wczIeZZiT|X6q&9i5o>BDT
zhx85r+s!l+D<tJW{L||kEHU&o)ZZl~;3G&yQ-5u}aGQ+vl<QE>qSwT&a}wv!zZyIb
zQH!vN8h@hZFQxP_6VRyR)ZvESsB9s<yPMFddPM15X1|6&Qw`jq`w#XtSHp{5{LmT_
zCoPerwZ$u*U?GcSq-(Iae<4o{lG}&!6<Ag6!eI~N1uiv1%FdP?YLPY3qxwj+iqhzB
zlScZrRrX9d&}@rWm80PQX!_5`dt0590IGyxVBRZ)Fz2#+T51|vI5F~eOY4QY-M(Jx
z#=@sw7p(-X%$P8*#*8hVv-w3cDIzs>ZD@dPJx40c^pyP5A-$EH<T5*-zT?eHk6LI%
zYW?BG6}_G>yD0d@ag(44eh-wkZQI$GJ8p4b2ugMXK@IU-e90{wX?=}Nj^4_!L@r!S
z2^2ELc6bZf!hSF;U7_dj;VtR!X7h5ep!AaO0Li`kVi)h$5{WM47OjiZpB`1%4#}_v
z8@gcuR)7P!JGPmb=N~6x%H#FoYqw?$EwCIEMz*_9T@*{t6dPS-4<_CQ>Km$#$0Cy6
z$h8rEB{|*uTVuQvjKYLGq#1GEudaABZ)BlTAYWSforE}x4srl|!pAJDpF5E(S$r3m
zwA-y#&!@;FXi>KVN(6Pe>_^gx_Pr(w_4O)j!gY7k!A?!U#=Z(00?X3c^M%e6>>3QM
z8sce^N}t=W4x=XWxw6My;D{Yf0AyBm1N=Pc^f_Kw6HJi<-1!0nlv5Y<X8Q_qW5Giw
zamW3AsCI?B2Z2IKS6*_$x!lR}V0JK%Jho;Dn5;Vpu%{~7>4(*~n`Y^;b_U`yvHI~W
zOyZ0gx)?i1UbTIC6m>KgXpU2~DRft?oI(P=1_Yd6E1oCNK+olmlnMto=7)YmH|850
z*uK2NV!F!~yX)oKFg?n~;>-Z3NCc1cE#JWSz2F-|P%5>_c4hqj@JCpui`l5vq<04+
z?rS3tMH~+w6AN-Y3ZkJDEWwvg#qWEfU(G`{#Uf2UAZ)cP1{0edo~`V-9t|@m1~1)k
zN8vL{glWfu`#vD$u0tNXQ@T5(#|#|*hpgR(ZK}PNswT*-NV8T%(|uUK$Dby0*AN7X
zXkA(eh|p)Xp49(sf&WRg(sO{UXThm9{e4RP{gZ$dBoY!_>9F<#eM6-^<Mit$YKhe4
z^(L2jv}G~rpu#wiLe#(<VtUI*LR^Dqi{Sqpt4|R>DYlUgSD(HH-%;L}h9#!z@?c9k
z@5VfP$98$wPV|n2cpDpbRNQ#$8lD;JPcwsDH1=FI|9SPGPR#7qP?0dDjv@`gO$ReZ
zTfC%?`rchkemV@s;id_ZATC!bdm3~UpwQ?kLdNMt=47I3^|<Fd@b``;oy<dbygWRo
z>MTe8HqUA4i@h`l5CW4p*J2Ud+q$nB;F?%VN4c3kOzG;Yo6qL2)-DI28e0A0Qr$>K
zhbvJo@C<U8vR~c}$>5y+uZFmj`()_y*}wog1^CVSAAzCPIz9lTAod0{^lUKAzdMv~
zK#5?OY)lpp8MP`%cn19X_X|n4eHG72hqWZY$V*%4jNFpOUb7>HA}o9ASD@$h_Pi)7
z;hMO=a}wvI0=&}C4fZuvX<26wGOOAEnBgr=l$By<18e4=$azTLNpK(gpePgR@*{dx
z85aGREUoUoENVu26<p^=h{r!(d?)ab2J=<9(5n*&Q-(?Jq>2hh^l61RPKc^atV(x?
zj~>dmV3u`yt<9CL!KJR}x7SGta-<AU%g0N9L8XDTAUX^?7wW$YsGP<-?xix)-OTKw
zcQ7?bHzkk>E%5N5qul4AGJ2i2GMU1!;#)3xWQa&RTPja19aIGo?M@R{FL*MC97>O6
zcVhfrBf$HfvwH?jPaMp;HGQMMx5WMz#4vLUWfQt)4ts{hJ%uyMR$6GHOBu4ApqD;<
zyb0w(^E&BZeS|Z|8Eq}BElX4TiOT&H`F6{&#ZsV0HFA9K#6@41P8e-ZX=Vlm$f6D~
zkgp~Ib#w-bw-hquEsFJ*c2Qx-g@S%)0PkxEPJ&lMMTVIgPx_{I5G;@nfiNgjhCN?8
z1o&nN;bJvTHJU?86KbP7gPdmcZ&8KWZmgltc-(WyvDi!lqHp2Dq$Oky@)`;R8*Z<H
z7L{}Xm)JJRQUzN|B<?s#q11?WGSJCQtb5)6{TZCW@3EG$P2V9%!6whek7w{-)BJ_5
zBL-=nPfwhuW+hycs#m+=yemf@FW9prC>e*!cWFaAcnjMWT+|ZX?t+UOpB8JKUGC*m
z%Y_1sP?PuG(~>U#sz<;Q&K)L7DmZp&#Wr7!+^vXR{=wQJP^S-C^|Ve9kVLZ#8b+Pd
zSYmVtLK&n-VD3@0v6pb9hyod{(O6|jgG)(2z%9eeu7?syCqmvD8MyFK1*(bHz0g(E
zdI{^h>)&CmHX7z)tz!$8(9@|Qp74RsNi`c_=y4BSU|<v7&v*L73=M&bxj%dVZRvP=
z+*?>m2(!??gon&`k;GHnJX4x~31vwKlSzOx=m+eu!Gj#RCBrJB2EQc$;SD+(2F|AF
zAa5BE>P4$NL@is&cElwA!nAfU^zoE}9EX>=ReT&g4#PVYw(nv!QW_~$AtyN4(D`e_
zwCU61^^3!nWf2U8OEw|0vH5Of@Sfl6v$QsWD#f(=pU*1ZBG7}^np54WUy=zsikUr7
zVaMovNd#OkV93BLUtiL)xiT-bg4QW<u+})p;QmXMV`?XLou}f0(RldIP>T_44Y<5;
z#Q~P)a4O=3%Cc1~W$hN|IIH&qQg1BieJH=nh3srHTr8S;>#Nx=fUq<aY2sxX;$Jfj
z4nWWnz1*KgW#{0uUd)OCdtKUc=7Bh#<$s+gyfBOqOJxqwZ|MozSYiUzcyN3ii1?CK
z$dEK_F(^RVv|Jp>1Gm&X@&u!xXzyC*Y#F_1Y4xBpKLb62Ca~Z)5n1vFj<34983!ZP
zJSxOLTIIJvLuIFTjoB-NN9(qE1Xor;Kk;ITZPJZ;P}%)sfAl>BX`6&%&gI}+d=`mD
z;O{VU`cOb|JpUv^)xkAp44NDWCy1`zemwLHnx$*S<b-tm8R5nU1+{8b`eN5^Ci{3;
z%=xD_Cz2Y{)k>V#2=u(Ho(;8~)dm`^TWGGjZw#=H$%9dD=N2da4N~9-7G7rsR0++j
zU`>e(JMN@;4w|XB8MD^Qo}<?giyjksj<}j!ssm{9Rc(hklTRN=dw<A-vDF5EB~P7>
zG_6}9M$*i<$W`fQ#`|9y)T#qx3DeSXws3_|R8F7sNmT-csuR{<gytV6TO|}}xiqt$
zNvI2pPQT)~RRj-u*ejjdh1r=Gt%E^N(zs%=gis?#1swhUIx<zYNap@7?9b-c5xbRv
z8MNmUmxSx&uv6}CM_pVecKoLZH!Jic746Rw_0iadgGh%jPLCdTv9I5GP$@9Jf%x7>
z1*4P{l<%qs#KjyIT%^cXAAeUutP6KLzsCOY)-BLX7cpVRKSMBeSahJPGM?m!Sj!2v
z96x_eU^j>_CEC_dt&&<3_4Cg)jZEQxagWO27LN}Sa=j1|<1o(`;egd7@SWWNo^Lsu
z!HmAms5Uu}_Jbv=RyCEv?Q1~)w<&?`@<)3Z2D5TxpWypdKiH{MIK+?WPL8dxFTQ~3
zte*p|{g)R@W?A{8(%IdBxjWa-n^>cgB{0G2aIVi`cvT1%ez?RVk?E`%cXreNEcS7P
zV+WjVUPm1d`URW3!h0SB*{S(-_gsi644%UG?NA%Hzx@-EA1>qGylWVvF_F#W|C`4_
z99c-zNuk_9pDo;0Pz}F{2s>#Un|;bI7^x=A<m&VxqGb?U0Zmkuw#<O|n`wd3QU=*m
zBb`+rF>LU&K6}IMj!gdOc;)?QHcB-tr81+yVJO%xG!}^YQy<o9a%fW+j}!`9nR@fG
zoAq5hJMaxV%YixutnSesAvb-rV*)W-aUP3=ue~Lp!m=Gqy%HRg2ay4sBA6U&+&M`}
z)fqw29gc2dl;jS)-AzTw!EYmuH$xaCJ=O#hAh|Z&sNWD+#&dqZWfm6SO80EBv6vvj
zH@RQ!WjQ&-B7$w$<R>iS1@~9}a4IA(@fo>SC%BVgtJ*N{&U?sBNDGZhgl#6ScS(aM
z;c-EKK|kUG4`=E<`g~VEhr@~s^Y>_Up@&`tNsBz4e9Ad-fa@>rg9O3ioHlC$t40BY
zTM#a9#<22Qn*EWB$W!3oxm8?%xxwuc?KnI6@ZBq<?o}2bx737C6vCz$!@8?}cZWfI
zoh6!}l_zN2MlbOB&ELd>_=_A_yqat}El0Z|QvL6TS<-jOu}6kTkRJaoJp<<YXjvT+
z#I7xB{49|{Nbl4gIq%9eiY*En$f!6pR{u}TkTwO2{7&`I5)k@Exql>=VTW~-u{bf|
zDNqd<;a_#f_L>UqSZt6Z(w<b*An98+7OBbv|9dmDVhcO)k-Qp5CBv_XQ6Fi8fl^JP
z@v#IW2xrPjHP8vKL_0b+O>omoQ#4}JcRh_Tt0pac^T0uoddAYQ86sQ1<!vcN--SA-
zbwQT%5Orh!k~=Yx6gZ54dtoP!TTCgM&KQ$_`m8QApd^$h>$wK4f)jrgw<~1u1wD-1
z#8_c{t0uJ6LW}T=*JG-1^2FdUZBkFHR?>qb@eiZ96|Xi2L_`I|zeDp5#AdOWSiw--
z`I_DlZ#C0E3m1Z^$N5^sg+bg>e2psXlxpZ!C_iro8H6VUe~AppRu5q$<?qf4eNPXP
zuvfc9C~~ABXd_lN$^5FJ54|sSDHX1vQ!KOoD6*<B3RtLV!dn?R-&fz%=n)$N$1a1^
z=IN+O*C$pemxbER|967J1aLgBP{U`%@1$(^2jia;WNcgaIDB>+H%|8=v6RmMERyXl
zIBk%^K~ee&8OL5ATW!9Clv11%Ow$56?ji_E^QHqjZM+_wV9aq(-)D~NpDy~Mzx+Ch
zZ&qoM(*ntaWX9Y^JF?v|>fE3dg9hZH@XbC<jM?ObJ(N5@;AC1oxd$X^#u+`u7Bv@x
zIcs-SfViZC#n(|<<eB*o{tLKSi<FoCD>|9WDB=I9DuXa2c|5B()Qhp1q-iBA2q4f_
z?17;Dt{zsg>k~UM8dc|>Tqpc*IhQ>p`;u;c3UZ8=)T=#2OeUmsu+pY;uhho7nKBhM
z(Z~j`_0<vF9wS~um23qr6EE+3tdXgpQMs?5;~Yi@&qk5d%DWQ!7Lp!+#o~@bV6?1!
zC6fnYd&e$`_nhzun*z<P!5e^?nuC8oD`eir6yj<7Bm&21<$;H`BZr&Cz@Wv;xHC4A
zpF)5+zQVi+H}pt;d}d5?C~0rhvf^9B*2y%|mlIFgVa7u(c`jYlR@RkU^;x`^`yH_A
zz#=-d+FEVPRX`^_m)(QqBVH!`$B)7K1SJ@To}$oX_F7u1+eQjK^FweW3GqJYoET}N
zsljf>T&Ul}(+u;Wi)CfCE_8mp4tp+`JYJ(~b=t{u?4n!W9kQYV!yqX&{O{ecNMOss
zfNb?s@uf&CCK&v;8AH1O3Xf#=lB<GMt3O2Wm?wKgGN@8(M|Bxx>y;+9);+hT2Xk7y
zvu1iE@xXa5*4K$dYrYaC=aR)(D0dez%l2Z8a#{_O7A7`K9<0{S#}*qbj1Qc9ib`-H
zM$v~w4bP&6_*Oxt?r9oqwTGisWUnavOnuO<+C+YVh)=gq?&tq({CIcluJjco9Dh-@
z>WzP2B2L+uMFy0UN^0NwYoW%XD%)N0q^1!HF0-+C4;jcW4QcBvoKdAQ%Mw!_M)ny~
z)p7(BlrQw50Y_Kj9}pIE_%QchPX9&?3WDLiU_v{tf^-n2nR4joTcJT`SL{2eqWNv!
z?Xu9{x(o0C8;<>>ML>EUITL7&@E!O7f(euh9rCf(551W9R7q^eELS7iNay}oRA~;A
z?E@ceRo=kErOLMY*$Cv(0}`KkjV*l)#o!|XCqq5Ho-G#Kg3Xh66j4jx8%xpT<8Hl3
zz_oYvea|RCakgFgX&MT{-$TRSZcWHCZZMXW!942xT=O}daN0iA<}FUTPV<BYX#>ji
zrT_YjB$%d5L5uUgb2$CYC0N)1vr-mnOa2ak{c%gJu(fAgK-gcQ(m?@%XP7Ebf@Yhc
zqr&F{_)Ko<7+Wiah;#ff^}`KR`?GgOpGrbLiW8rjv{54TvRCo(AHKL{#O}?ULAVFh
zuQDS^WM!*?TZL!>9KmeNsHkpVDk~~hWtD*n-}0&O@kTnGWDZ@jG%9Ns!OWw-7TK_i
zqAf0IC3c|)!}(<xG9yv%Y4&QkQ(^Oe#wk3TI${X@bA-+IH#r9vybf0BLd(k%&cJuj
zvR}pwukfXCZ=#)a+%3GDi8_dsllk%rCg}-n+=3?r+SD@pdEynSta{`h1E1>R$=iod
z=Bq3BSK4K28f`&myG$dC&z!QO^OyYyB*u@~wI49Q_Ev&b+LcL?jtE<^cLs<V8)||R
zG-Mwq-VqHEhL-Hv&4y2$rwXRTf5-kQz*w`awN2Qd0{Udg=xHvHvJyw`i4)iHI5el2
z8rI4a$O-5vGMlJg-LIM~<JY|E&DHROtWKv;m5q}QQ$Z)5E>qPL+vc-;Rlm&7cn~E?
z8DC%2WbfWI)8;cCWJG#_$o30U!0mn*8*&LhVRLxqhsmPAohNo^VSQkA0{M<h2BPYL
zEIdiP<$xc-Ejsd7O5R^Uuy96tymWWn&Ul75)tp4{ZEQ6|m(CpuJkXN3z&-#L|M;^t
zyE}kSfv*$7Cs=Ik;qC=9=?5+5y*}5)%^vcc;WiI1?-hF7eNqa)F6>f0HPT6OBe>&~
zPJM?-z)Xj(k%#frFQ)Ke?|GBhSuJ!A6BS8qQm8LO1js;zJ@6-2oNTc-M7(smyuH=5
z#?4@u$Q;}u1cCcrZXPx&Pq#mmbpz882EKtj#EO8yi>T+vEb5brRzjeHv%-+06Se3|
zGiUPg(>L+lgJ&&DC}s>8ZS~uXc`!9&CS<k|+@2^a4(r8vNT25w(8R(q<7^W16AGP@
zl_5H1o<26lf2r^rSYLb`klFD!(>xGUg{=6n@$$fR+Vg`Vx&JC3?DJ8=PXLk`YRIa^
z)Il$QdZiDlwN+D<_13s)w8pge$+x(Z29-F`cTB0$kL)yQKDc8@#KxaOGV!%rYEJ0z
z)FaRWN9y&wRzo94po(Sa=B&()MQ$0ChUS@HW4KJP$YVHML|_mee8WBB70ZN6aT7sC
zZEYxn{7-SnK(m*%5T=jEN<zsyI3<Po*30--Q7rVd1IDcis756_wQulfzH8;$-8X{l
zB=W{_2vO5^!fI^pz%Wd=^ipw{YK6-np<@-JV4#T@*Rg>hdi!a$PE5?-N!&(fXalY>
zJJ071RbbT@;~Bbq_Z*Y_AVTVqQlt7=2qr5T$laz{0_JvO5@bD2Ca#Q9ZMf)BKgrf)
zYk9$S>;d6XBCIB8vnwJD9bLZzUf&Lp|9^ka$xdjOs`9Gc*`<3xzvzzpQ<65lr*6X7
zhtJUkVUkS!-ZF4Bfj^SB<GOMJARwz{dcEZdq1iPvb;Ry4I`g^17^cXq#hgb7fIenX
z9g3vQI9R$zCR5%p4pX*}D7PFwmB70}Cs!N;4{F2KR@q{C(wSHk-TGh^T>K=ifMq<S
ziZ*rFpK!7eW5%rBY{pNiqmL{NJETsNq<tk@;vAmLYsTgTCfyai;Ip5UEP`8q>KY#E
zDf$Prj(R8>Fpu<&2e6%zO6}m&Cfn>Q;d9r1NtctcpNE}C?wGk*zB<KsyOf_{>g^i*
z=j*W!G2P=w&7cBNiHdMaKk=7lJ%{(ma0Rj_0ju0R7@!R`N6Uj#=_P-v&$4zZnyoRO
zJ?gXGPjfEU|Im>6y32Xmph=c@__2!A4GaVd5ZhRWF<RhD+!+Fr{xXy1&WV{b6u@8Y
zJ437<Z43)qURd)(re_)Z;U0;KmN2*+ScTwoueq!rGBv^`r64@l3?QPyWqoLl4gLk-
z%}`aT)74ba#(GliV_p}#LFd|18Sm9|rzUyxe?>!BaCIknW{}uAm*(o~7bZy|u;^9D
zPF)B@mn+qE&*k@$bu#}OSx0PLicfq&M(mXsU7o}vU7uv80?v0Ss98&`tPFqHaHlQa
zV{t*WXR~KRUt94~6nPy7vX$(DI}h*n(q)+1XsqrlP&$cs$z+HLf}hKzAVSLE<u>m0
zr6pvuQNw2;4sNowgbI}zS~;Fwn-Ms*AaS2#>zlH=EQ<im>P^hG>LoP$!~;UFOhINj
z`435*SulU@4(!rJ=xHs+SbUn)pM*VEGUYt@j%New0LpB@*{=~Za@9B0i}kun`Ut-U
zr@V>t32Ge2RAMuY_qWpry*`Uq{Ubd=EuJ1esE_)snrbZPd}+Vl8#vp8GK5smdWsa7
zS)(E55%Lno-;=As<(^l64au#e6?;-T@KuNXUD|thdK?&?-ARs#dp=a%Sq;fzl#s5?
zxb8(O^x5Ypwh@BZXnqH7my#4$?r-c)C4)2-sR3T*v^GUgxp#(XL@tuUvz7Vb4&Qug
zbEvrp!#iqQ-n%Pu>%mvH%u&gGmU5LzYA7vyp#UOgqb$W8b9-TFXnE5eZR<<c81UJw
z_gb>Cz8t{S1ddt3XvgnCFiiDEpjLO&T>J+7<|KQ@0ZYO{su^ETX}Wl(R!TT0j<x%N
z;^3fDUZPl`M4zq~SlaS|lTcd+B8WiX$AeoEe_nw=pRmAC`68hFSRwNcL0R<IS7Nn+
zhJXj>f|S0tLB78;Ch^}D+M8t1kcd+K0RxZBDsDW4ueAvLK%Sgs*YhF99|kKFOlOPK
z%edmd*9u&tKPdQCJ5|?TQe^H!b{?+^Qm@O0L3upR|I%xMEq`OVA(|ONv|dYZk-BDQ
zdiNz(u^YFE(iBXNi1oFp9+*qYDW@yzb|pBW&-9@1OLos1UV)meQSS8Di5kjNs)JnX
z*{3|tzLu3HBvdJGva5obU9M5cX>r0tk#lIrumrBNH}0l}w(8h)EkaS*1h<H4B(%M5
z5p;}hh3@i^*>WdC2XpE%w|;I#+)?<H4ii%yoH!`-P4zA^lU#YzyM5&gAUt9EX}Ge5
z_9EZ2gO1^9BGEz#=tUcH>M0hFAD0xzoX@OzJK-H|X_J*Pa_cPK({v#R5&w&GeCpn*
zAPiXpsuEw~Z45k{7%NM`R$t~c$P)ld!aZ!1Wm8YuLA5o@$Tn)=0ycJ9%3ftTi-~N+
z67OQj^AYj<kc3!(#=6YcVEuSIA)gyungsWH*ZSy!S{m9cJkqJ*uPx%EKmNXK`wMVE
z4L`>yr~6keNZ_It;cye_8~NLW>pMzd{P3&t6B-xn!K9Xib80~Kbl!DmQfh}1^O%Iq
zYp5Q!*<g_)jK|cUgBesvOK<mbmT_x1GOaB(Brx!m#Leu5fWtGvjmvwcD%<IoZ};JC
zrV#n-Xcc@^p&#Ng+#>>_oCWYmuGjQ)6dXMomb05NS+7!G-keI^G&d7}>*e=d_||HD
zdlH)vf>DArU$~MDkiRWHL4GsAicN&V-sji7XOnaieHh!<{l~2IiVDt_x8eRAO@`+3
zP+R^l{p@S)mm4n}x+`>rYT!pn>j$Co(ZhsAZ~g(Dg4CopOXVhYa=Ve+67z;rM@Nb#
z{ojV-lddvnZ4_Dvd4ei>^*$pKtQwPMSkgC>Yf9;&_l?%Ir8RMPw3r7F$8CPWZXo{e
zgQ>gbfq8TPr!%>fEV6&e&ZRhDyCWq9LHPI#mC2nD!6eD^>KQdUe~jv!FW-ub8FwC!
z30ElmI<%HfD!gsCC-7=PD5qnP<9^p-#`N(RD*=~pw<Q?^MlBfpd0YbjzE-%}69S~f
zZi8!>#2sb(M%C^MCi)BCKlREFvV{lLo%eUH+Tk8110U$;ay&w0`{R-zQ~s3$Oz(%}
zflaVGUo$}><X78PV=(zi#H`Ko%Ro)?q^O|+>Z=!yUwLj|No(EBH<q1;8V34t>3kS7
zqj&%7b3m;Ed<C(tzv6=A3BAhzVvNxy*&Dp}31Bs_)vG1<*-wIe4>9O_0O@O-)L*c|
zZM$bL59#{4(!VMb!|KGRW2V#-J`-5tlN8PNl73&fN!8Gh^OupBBvd{}Y~>o@0iQYo
zc@=`y`Lu-hoS4YpdHWLW=3is*M90O!LoV>N*hRJCf4g(5_(nCMsK(c(dFoF#3-MG?
zFAcQeZ(*T*q*^hdy^LHT>3}B)QuN>h%nDa3yiBTPnHk5Yaw^d%y9JX5#To(_Up&^1
zEmNl--3QgU&lV>$W%s?3!g>b16wTG{#s)d6yK&OPZJNmnPl9l@>M5cg*-F%bC})5Y
zA8l6rF!oC-I_K@D=kQ}zt{tjLdyIENNn8Cu1I$<kpF8g0Vv$vGCDM+yn!sv8YYVY%
zUQE`XU71fLf|#6fT4ps@?$d0dQ+|P(v`h3N^ZI7DkyZekM5hv~J`W6NPw;o0o)Bn8
zw4FY_eTbUtz)^f_#8VBgC!@=@bvPMzmVytFW5LhpE=YlmNmsX?cw0j$$WK5x*MFVy
z9~;*L?*LyQ`vtRx4R4C~cTP_IWCI7d5VpT}uC9%_<<1?k*pM&wih6{9S1aXgzxA>x
z;RE}~jx4+Z1XEnzM*7n6h+~rYd2SZ9>#ji8Wi?R(IRuYT>$)tAg3rNCzwN&_c!!Ex
zOn;J=j|^<f@ib&?=b4SYCw0*Czdk$X_!zUdISXU(kS{+g_sL)|T9D5*!jJ*oJ|e-T
zS0l;P{W>dXDbuh_H!a+Uhpl36=u9;`q%phORZWC-!Z2sn`A47fTg0f3tsz>zPg4*p
z8#p_zX^x&`ne?%fLpf&A%lSt;&<7To8TQSZ0y9?A2JlcFf(e^*bi=|=G<I{WXeL+H
z!he5<GR6W76Gc_mKB+e8B<~r}*8+>*GL*uCb4z04w*s6YL^v0D?3!oS_a!A4u})0x
zM;w!X@A>29>(;m{1a!W9v3v8@(a<E%+vDPcUSHJq6JoB_{gaVX%fgEIg=+_Jgb{FD
z=B)~me>T+|O90bZ)6yDFgwHz(H@B~l>X&9xB8aEWG6|b=^;&cdWu<X)m#KW~^Sz=8
zQl#7z$Qh7we>Yk7=Jl+cZMLk_+??i0$<C^Szd~il1GjuYGx%s!kKFz>M$`xE$K(d4
zr^tEDeGf0Xt_AO*R=wxDka!b!oO$@o8E$eQscE;?(WD_o{zzS|F2t(mPis|ksL{h1
z0D}qag*alk!4o@v3((dhc1uiC#`UIWM}W)4m0Ls8>B|CSMM7g%^9s(EGg$>xvFJ}z
z2$x%B$c13*XfY&@5~C;!Knc+k;`<&yB+LcKCt4)=Bothj>jhw7TrB*kIkb1VPeZkw
z?QwW_o)HuwI;PNW+8)F7_%fXA*2==$C*0j=0=EyCTAt^>0J=&*{wy8fvr}sLiR%%^
z$2C1VeX9VhL-c~VuAByGd%MJ6s}H88edqEy5qcdR8dK7NpMzyC_wSXG_0Wg}+e_sG
zK8%K()*NkkIP?<s>l%s@8YYI@8$pb5WZe8&jz=vUXnED3GW3~!6!RdSxY3y-MG#YG
zJ#mFAx7r|j){A29I5Kq7ihh6t#Vf(bKpYHm(em4lq^bcw(YJ*Alg2p`)zsC8UE)GW
z#zBISNXSPBvqgzR%_e-gO%{&JT=?V&v1z8ITooIK7_2BaxTMEzYHKOi!T$Qyrnet;
z#DQ+v?w)+wT0|fok^jyGBX673k*Vj@JMw02_LIM?WGdxpx*XJwlZU@kH)z~zqa|Cf
znFxbCAg%fT{ta2dzH+LiEE^!zx9~}Jfr$oL9KOAtZ;X7tSB$8pOUakJl-M_)6dNE$
z47Imt2mFFQQUBG1gSLhn#R<YXQT&R-+bDlf*vATlBTxwq<k^PGQaW15snJ8#eKwvt
zQt|Za3VjUfAsIA$#Y3=JCbj;UevOKW;09kexda-Nera^TwL#O>hjaMAdJGaKa+3Cv
zd2Sq>*tVW#zK!TpnmQ*>_~Rn8@LmU~<X9VpH-_EXFpSE%lVf%cVMQBR@U%S_3_iOn
ze0(eRN8wm6_z)cZ%gt_BZK{@zI%_bP7vGEVGj4kOluXtEAol)&)bxOC&+5gsZ8#9E
zl-_(klHY;c92J;#5$#2ox84S~kYJyt$`V=!Zo){o+z4Bh6Pnb01>W14&15H;AdCFa
z@T-@$YCKKv(Yo{&cB#<ylg)SZZ46#VV3jmB)I=e)b$dZ*hqKisTgfmujt+g#gZ}5r
z>0JjZnJaGL0|Pfw<B<^LuAMcUd_V-@Iv*TUzr6L7lRz&gS3?BxWeGo3v#TK$0q@d1
zdqTzpe!FR;p~O>K>=1jll@AHs)ohd<qII~zrXX0Bv8W%wmdIr{O$-n5i{01bP8U}8
zoJ=Qn-68v^xIE-QAV-#~zUTIg;7aS&Dj<X$?4WVQ)RKmD>80TS-2Q&P4AsqgJ4Pzo
zm^!~^^1+E3;jlb}5;p<{3VILt^b~}SpIO6$HR!F~Ic#*0$r*%YC3j+{nSpuqne<%Z
zoe<6!(8;1WuSTj^+6(ZV(AkUJBDF5dvOb38^VSpcBQvdcX%@(RP&VJ+zo&}E>Rz$E
zg{xM5tiFbbzGr5WqO(<$^h<vZqBeC((W1T%>F&iE-gDl$#a0{l)B8cD17$>AtC7Du
z)oQ|IK$9!v57*#8F-my#WfZqlvRW)gMB;HC^5l6JJwWyWsW`&^fOb@SJ*cjup>Um!
z85&xXWid~O_?icot%ZIKMGQdQG5dqv;&0wroQ7D5Oo(*cl!f`ffC$*nhq{q+F**wI
zRA}F;9qkKZ<ElWMguGb60^8eknv{e{v?wt=Bc8=Bt?}io_hn9yk8~HcOq#h9iwkvP
zhj=ipabfdO{v_FP7k?cH3TFhco0-PO*XkHr(ek7}m1%JrKXLkNp!`n1?rC9~cpL-B
z3EiJT?zK7-g_5O+ALGVI2=ULjJlkYJ>Ck(50y=ad_G%T9*c(E;HEM+uS`7qJ1&XOH
zkHq#|8_#yzgcJ?N)^V&!2=9(+F`gwr^iVa$L{pD|*b@@cB9X#O<Z<|^QKuNUuH(^)
z57G9k<jJ1bAgLG@v{gB&p76CLA&27Q?S`*FWo#znf2ld{A+peT%S`zBV>zTh9_?34
zr|+bx<s#N$#?oMnv}Ne@)@(wsGM7uLn6JSPV(T5`I6{gGoZCH0<es{1oT<Qhk3?=7
zO0WMTS}DfrfPphJM&<$l;w#b!jn>lOA!B#x%C!PSJo^DIt`A&@IQY`#Q86xEnVJWD
zTNB6Ct<jg^T;>#8ji)pxRM{fS_?AvgkQFB|_u*OKPRkxXCdu6&-nPngE~P5XkW{BM
zG@GvKN~_zzKPNGC)|jU4eeT~TS>NVRrdcwr@m8!1owi+-u+?)#G)!3?N)f_%yIjRr
zYdc&B5p_LT_UdJJV(%2hzcoyK*(WPZNjyn0H}))6RMG=4h}6};J4R3eT1ym?Kb?+$
z+IGIc-T8DK=$Kf74L*!f4uoGG6CIt3$da=U%fprak#cA^ZJ!IB2X+YS^1^A)VrIzK
z@WYl>dyc&;-JCx&j}|j7v%Hg5^*e?6NRyD(UU@AX5WJ?SCe#8rzDZ*us$7I}uDP?b
z8{6IALRidu(w4tGlAm=)rGxMBw{OCYWVdk%nL2C)3<(9-BWovG&s!!WrCX(dZnnGB
zP&*Tjg#xg@i^`UrzW_|JRxgxBq~B6I`&}=HQNRxpU<e$X`O+}{NQfuL!Ns@B*n4dh
z;V@j$*b9?x(s}E5;sl?H{e;8Zso99ax2JCv@w;1`&7$|GujaB&WqOMYiSDGK_}Z+N
zLbmN4sZTNdKe3lAdT5s)IxoY@zTc!dJ2#;BS%>LCc7Ywr2cpHfe7Bf$f`J#mCyMkX
zr41HWAfHsszm-1+XizzvE+~K>X?i=>&h4%QpY@n5yJAEFV22<}o$?1~AoLj49$o<y
zjwb_TLdQz)#X=jcxiO1tA!+bN36ddiz>PBqGd?Iqvk143(Di{Ot(OS%U=RG}%Gitl
zZr8Va8uo$j!1t;#O4{qKhX;y(DFyAX<-GFGQi-i?b5Jmu1V~vP;hMe-c{J$hblWj?
zN*hpiYxxCL%h4DUA&$hc7CHnm*^eadZt`B{+o-JiH5$^HXruJn*9(=hsls5odO-U;
zTP~;#fqkAG5!P-72E|zmba*!MQzNr1#o|Gm`18)^Wob*RH6|U<{zSypj!69a`~U)O
zIY-#PX@w6tMh>~ioso1w>CT+AxeO7oI@Q*Mun;qucMAFS5RFKE4l8`H!ZBnry68h+
zI6<%$g+_cIhgw<$u!2YnUpA+8;yiIJlm#~RKo*|568pj>)+!j4n%C+D0f)XMGP2u?
zuVn#xj*=Gm%;TT|ZiyRYg?sf2o4ZIRd?H$SBRgNP7a<#-*T)eqC_dDQC!g0C+<8Sq
z=vyvnV_m6UL2eIN>@rU^3Y}(BJ6O~oCX$aj{#8Iz(V8=3xrgr6fZ!?mJ6b8!lQ&PN
zwZrKY6|`yv&X>aN)CeY;m$Z`>@g=Pb$2?aBwUt^oqqr;Q$H@6ERvaO71CI<SM<+T)
zlUt4mC?A-l2OU$G(H;tg&GfIZLiTAj6Q;SznUG!x{iUcj25sy7&flk0h;Ef39HQ=i
z#hDI(U%3QpvtI)C+Zbf;)?W@5r2?KBEPGio8~8p0+dI#G|N6*{^@j&6@ez-zC-Tqw
z#&(di7aq;xPiNhdt{kfVMzGN>Amn|t@g^UN^9EkSmO;^X`9}xxC(NY`b8ci^l{YlT
zPOx(5AP+NFqU;V@eBP-pomw-QM*QJdV}z3~`dhKrl6u!@37<MCW_deAT?TW^IROo?
z{J*gqG98I(LybCBB4+kV5d`vl(Z4V*;5z!>64(V`o#LTv@kLORXr931d9cOlw8ll{
zxr<nW`Zk@6wCD^<7HT8rC%5+rF`P~hM9R(=POCc<<9GsY4X<c%s}Ye{T@Y(RyCbEV
z%hy|5p78J>6hxm(!(5YO0Olhkx>S6~K5pK(6E~M@_9AE`J`r#_SB$&Q-wBI?1Y^|i
zt^WTW&iJ1OB0bGv7dZnHUMSkChqa7+zpRQm4~jGS>&M|X)jD^$jaI#_QIPennMNmD
zI!kjh?>wKvDQJr!)XQw~q$+6bHE)*A@A$8VXKSivUd@h02PH}5JAE$IM$uZF{L&ER
z@{{ORYdSST=bexGD$VyW=o4Ic9%z<On0^~<qXIL2y@1+<1W8|-y!2(#s3{o~H$zYo
zteiF&O9m+AFe3i2cZ&D4i1^w|AAc{Q{=-x>!FLr6!XF(K=5W{LZ13$qqH&VKgNy^3
ztAPF%PynYe-Yh82(nF|0WnwEytaiwYm2J#L{&4L1c58PJ14S=o;=<aY(ed$^bm|+c
z0;^5QZ0)F_lQRQ8ozMxcQ&1lR*WSyVy2*b^v)olwa5#<a`27Xmd3gh?vSkAcB$k9y
zsCmBK?}~{PDBLE7`hL8Dnx{3fs#(Y5H4+=|yA_sEv^ri*h&wn&QC0&=j5>GNVetHd
zw3xZbr;oc^Qbc(9$H&Y)Tlg<M)s0(az&|Qn@4}}ob6DSJyKs1Vi`7H<a~o*8*4uA@
zQClx&{X6G_(8d~YQvZ0XSf@FOQHT!^IaX#wAdIt+OSI+sVIYMC$R#SHDZsx}KlCVY
zc&tNTyzPE5nxSldWZxWmHwhE2W?p0&u6(#+q{7dUVEl?EN?vkikJ5`_T?Gc2mH54m
z4nVvHxRWgt2|dCFL~J93`Un|W2Aq$Q0#v1A0Tge%f-tXmHLy7t$29krUd!6c5XfHF
zLN>be5CSQsql43r@;^AznapN8TD@hL2JZv-H@dHq8Gw>Jt3Do)UV%A38af{Q5rSq#
zMOCs!UUrSRJ#eo$hZp*Enz?p|$*A{L0F0E_%+C(a|A)c4=DDQ`SZivWF2%@;v%3T$
zL6V=D%6$(cP&MGE%{`o7BMayO>3n_|-zDL7sF>ybgXsXOL<PRBMvr@l!|9Y8M3YBy
zQeqSBNyM7xd@VDxNE50k)Y{A2{mYgX3^I#sBWjXX#uRtXJX(H5)7^B88QneTlN|8R
z3_)!2rAafk#pA3}R$~44M`wt*cgt&|(F!iqQ?7BzH_a_|u9?@WgR*#!IflIMF#xHS
z4ioB49C8BOMb&dY9>p6_DaH_->`e4k;>Ja`tSoe?Pj(ZsJnuc`=H7vb6&!DEv7^_r
zmuCPYX>~XnQ<JWPm47lzq^XUb@j^36F@(Wgido#ZhHCNqP4DrZC_eL2tg-w{cs-UT
z-wEjfW6<|VpBVP63~<#6eM!z0)PJA`Vl)ojr?R_mbd;GyAawtx;!vw@w+7>wd~+c;
zfkCy#`e_HGC_&#-L4tuzi)%WE)zB{kEe{KShA!ziIZO_#6@GlK5X|HQm1KzA@WB(O
z0Dw7i9)Zu23myC12N;CM|2n&Yy}9v8S<p`zd-ih1NWfkX$~~jZyHzw+GplvF8#{>^
z5}8+ZOcMp7Rz%VdH*8^dBCfM1z0J<q;^Ve~8B@G)wSv)9Qmy}RGUec$=}9|KVkJY1
z#n(MQJ34jeYdYfHlJRs}$@$kEl>fvkV0vLa+7PlS)o^XBoFXn`be7&Mi{x(8B=kR}
zi~TI+8H1Qmb}DMD#`MT?aO)7r?5$ivPGzmDGHod<qL$1CbpPK)%BYKDJbx0Ryl^a6
zK#8skdd=a54ju4vT}}pY+GjULcpX`m$f6Jh<!QG`JL>MpEW}Efx)`0gtJ6n>M=NxB
zm7|u-bX$G=BZ`BkjF+x6>^`Et#w{qW_ph<-;ff6A!<)`>)EO5C!4-p<87s$~$W9WV
zb2{hu1ypu-11!qvY&}@N6=_ll2dCAQn|;S0-)k)Y+KFikoWady7n!ygSf&+oMGgXF
z+<B%seMeJ;#v)Hm>Y^8pv=GaLN8NwrPrRh>8p><pfYjk$ehW|4Q><8rK3YW#cyn|<
z<ZIQ^MJr?;Cf-tp_5P5jE9y^=ognci!!*<hGVSm1%rS1QzS-kF>}I!@ug$?GC3-y>
z8q%D(8lMR_7DB3KkO#e!fNh;I_bO{%W`n6QgT)+)THPmCJ8^Xy+;IZT3<L|S=DZ5T
z6NG$wFId+-ozi(}{V6%Dn(}R2XYJ^ejOKPH<|}N2QyqWRKDzMY!%WIB*#xGWc-@sW
zj86_X4)#s-LEuAk#~*JBiGD?DjST2ii`18KrSQz}8POpSB7odn{==dWPL~sV8{7mL
z=<Z?07Pu@jO%8lLZYGS6!dNte{OC7u7+>N-A4yppYH*@&tV@?D+xk*`V6@A8NBMza
z&np>2EFsjrn%(O1|HD8MqUnx#4MkjAaz9r3)ehgB7q3^I{pwmgp}`-n&j#F=)<uuY
z{Slmlz2D%hz`LB6bguUINr`K?2O%VcBx`-^R$vVwziH+|-DEYIHe*zt<}FzJc8g{N
zg7mV0DN7}ic1>{{<b&M;vYcdaF$zcd6uT=YN>9oH@RM1O=y_asDo(-cRr!i1RNN^H
z%u;DJJ8?AX%=IEmdxak{AjMVkt7lVsK{;f7U$`{}0j{D_VV-89e8XO3_>2i)0v_(>
zdRQm~<Uj?2Vg<YUS)iJ?$23z`05*YO$@74HU%YUArmvrliI3E>8yt_0xoZA|fUmh~
znXL!-^+)j7ukh&j(WY&2QruXY7x#M$OJS(D>8qcAn=HhUWN?-5D)glvSJ1rO)IKCX
z{z3`eZ!A@^52eX?ma95+n#o3-7XbA`1UsiCeAxyAsN^3>YyvxdPN`<;zvR<bL>;S=
zpldb{jdB25FEv8^453ed+ehNELi@AL*}cFtkXLT6=A~lT(N1(^#dO%KcXa<R;F2`|
z74L7jbGoO6C3jbK)7c_eWDs~%Ovz-i?1BuuN`KBM8_K&`>6ZiDxtQhnuRHd{wyXow
zW6xHPCs&&jz}JpBh`f<W%@>%l+@Hg$A>t*NAtvS&7w!RNtM~%Gh3D~}K9f1tI3ypL
z6H6%{2e!mwF-fiQUnMV0(Ul8_6UC1F<{<6QyZGmU8CrD$2J@&iDaIoidGCMw;i0_o
zoU}2nB_(jbd+iKa!j@ej7Z~_|tz%2n?rDW-508P@l_g8e35BH#FxiBVQkl^|COAGQ
zh!g?f^u;2yB^gRugZ?L=Q&Mf<i_%uQeK`3%1+E2$Y2Up_^a)_md7Kwo(D^M^A)>#;
z<!*4D8Hn~Tt@h!Zm4e09Mm&B4*4P<=!2@PseFl}g>fODCRA|UH1rFH*vJ^iU=u+&x
zkmlJFfmC_gKe@ebXnFgfls$|3`7FK|ESSyW2nZImYk+9I*ghSvJ*QsTvPjRGEio^u
zOr!tE{&is92n02B$mD;jb!NVSJJy)k5A}z2n5&U<b2~g?OKOF0)1BZZ{}Q%m)s#*0
z8}aE%c*tK5rWNwg6QSC6;cB{JrOze25aV3>Td(n20N9CRXL<>2KvwsKocOwq6R0tD
zAMm&68kdH(E!U<o6+EFOoLNDbZgt2din6~A@Gm(A?1;7ev3tX&%c%m>1`B}Zn?x(4
zdySA*t4xwiA?2LcHa^TImx@P~J!xxb99myuppk=#$o9tcs`<@6+w=xb=IqlPyV^t_
z0L2DBx^)~t+>Jl$nP!sbuyBfE7jt!{srkI$tvHM%48U5a;ta3&k?{0yF~Iha@vq#&
zD9nfDetxu`ZIt?s!E;$h`CSt{hquv}kww!&olkgd0X91u-OF^UD-<4D%L<d<isyQx
zxUPTJ(?tsmLZ0G3!y|&+nr&bAa@zH0WP0tGY!TPD0o}!QV^E`7`!JF-xz`SBbV2NX
z^;LvIEUKJlM<;JLql1G?(FE3Q6(kEYl0SjU$(7Q_W8b{_Ith&stycKqJTWKglRj1s
z2>~3`=vpqsx`%YRp37=>nYj-mW^mD!&E3oSwX$~5<4J!;23|RcUx=}iYg_}SSK<g2
z4}WFrs!iu)9No{RyP2DKA*4U>j`_<Q%~oqlKz{}FC<)PQWv<!Kau9147h|_w@g)A<
z@FZcJPW|^It`=u1aIn1=bkCFeT37}GA6$K;QH-@A?X2*)08lXSexqXYOt^1e$n|#L
zGVJWP{5pzdMY62GYIV=jGiY}?$>ry%j0iu&WSt0X3Sqo;HTrp!1U}yc{XP)+dKgGS
z$)HiK1cj!J!|LwU$}bhggZGd?U+he>^CiwS#q$6w2|3XQJT6<t8X9)JGOHv%R{^Li
zg(f0?w`<;epoV)^j~afIyOj^?47HdM6@pm#0{z<){0agF0~-OvODn0^G96F3`VcQI
zXB|;2BSECQ-h)B98amB6cQ2HetwD~*yNFU*h?P-g;P!{A>c5Z&0o6G%y>w(2_kAWH
z_{McN9oTTggU%+ry7m*G<N)n)e}LQB7=00Zp)H4G&ZWrxxJzX(rI;h13;oVBf#>jD
zyd9woRa<OG;*<n-E!C55*Gn_=c1c&k&zT<Zf%@MA94|p;e;X}j9s*{Y>t0AUBOYtu
zN>C@?q!3ikz;=fqm|(K<%SCL8RG>eB&pnu1Pv+x=8#3z+&_5Wl8AB67Shk%|$g~3L
z%cN3go8_6UT5qDo(~s9{<7Xo2wm;B&C$`V}DIE(V3|3jWqQ5!?kQLG?0bzmFNK`=J
z9mpiia;vc8+R!Y?mD{1N+<_4SlvT^chV)%m;bX)Z67GPfF-Rz{A%M&daxmII%fH?3
z@Gw)<wP)|Z%>y_0RD+Y?D2nwMNJdzA$W6myol}ie1)vzR1pbaui+5q9EF>d!^*3y>
za^LT#LvG4Y4D$O^zR_r=<L?;6MwLaxz&Uga<(g|Jr|k67p>~wXpOY+R=6BvX!JS<9
z1|naP3D;<Hr7mX*8SG(Z%NH5AL(&l{1a?EwkD~<_WHGwEc7x4>4bP*w?RDwVCe*#s
z&<a<TM$Ga=Al45sESE0~$TNrkPjWL~%6YLsl(3i&9G5YTccwc!!I7L`3^n?R0d06k
zjfHGvlf3#Q3sICgmpTAGnl9aIv<?oT@;9<N<~T=O^@Gx2Q1V`;`a%EfoKJ3DYK)bk
zCL9B~u6<^!o=y7`=Q`slBDeM=EBGs5;A}k|6QL?d;unj%iY6xaUK*z8XLPY*A%dMt
z4I&@axFwxj=$z7h{4eKQ?$Nk!rvF2QjKLCmwyn%FkVCO4!wyfz9UI)PwYS?%02~UA
zI^Ff_5uJUT1L0!EB&z66Fi$lhMcyM4PSEt|Ed+Ps?Ux&it=AHBndDI1_ht2&8DG~=
z{Mj&c0XLh<<mto*eOPv2`=XD8)eb`%DsLZaP)j}~pSb|wXLCtfvl?eCn=IAi$D0(W
zGE$9uprFfH@yT&agAGPU2s7l6xFqvsab8~#op*+I47{w0i&j4ouAp2sa*KZR<eQKX
zQP8c+VAn?iva;DZir<$m-G$Q+h@rzb+r=YzRG?nleT^`m0ETBsaRY#XgXBFV0pj)O
zN|;l^6CuA|0PL7g!=kb!q4-88TM5N2o~sco+GU0uKoJ-Lv$eZ@nfWh4`IjM8mbD63
zTs6?RWmU+Ik6U_0wkwS*U456p`sa35<ChT#<L#^C_5w&!A#J!0IJRbT4LX-E#that
zYx6h6W=n>Y{|l9a7M$}mPt>0KBw{aMGGLi?M@hsjeY*!9cL=im7V0#@$tONxEb|9+
zLs#5-QjuL~zjC~?D&dbELdz=YGK1)Vi?%;jW6pmaB}kVRFQ;lIe-Xw6Qd0l<X1?%T
zIP4P}JgoY2fQWS^bynS5aG6%xruN{+&9LkVT^J&k#gb~5R>UIxyCN`UH1|B&U}?|*
z6KNj>C@2^ysB<>JksZdW*w_>RCA`{Aa+T0)ycvIZSz-R<8trr2y03tLv4-+)Sq9$S
z9X@18gi}_yK*R#is-5IR!-~NF7N3xJe-Q`khm3ibJw#P(bdGHXaFX`Y;PQv|lJX1p
z$9~N#M`zI(a}$NyYF_6YrEsRUL$c!oeF_-HCcA$M=Tff`*q49Z^6lt%w#%LDO=v6l
zt}HAYWd(1Jpj@YZLri`?maVZ_<@E2%bQstRZ6P21j8eMnjU(gYPy=-k@76E3-O~w%
zFoAU6!?5gWg*%nYL7@*1@q^hh7h-1vq<P1k<3QibbT${Ea7!Jf{{wEI8sfR62L}|<
zK|*Gn2O%;Db$w01b)JvhjbMw-ad5#<JE#lT1}g=$xeco?H+qH1X=zqD@(am#d}Fa8
z4mUq;n4jYwNN}3m@UugCs}1rO=Fd=ST;1S}{|xYPzZfDs@+zXoU(myI?b%W)0z{gx
zh&`HU2L6DN7I6$~a@GXcww_-M8nm40K&49JEJI#yAK#SN2wPIIVfFlA&a9DzcR~D~
zy49&8LbFOec%s1ie+EC~!t)n^6+IEvu|%CDULQ>k&!DcNKo(4TAcl*7^~)5MZm>aZ
z43c7U-g6VpkJ=BED_!844FV8?Cs5txy*X-2IU(J!3`PGm8TvZd)^iFM%@9oX<AI5z
zun<q)(;$~MRHe_P_$UhVN`_tz{wlQ2gO?$TBOF@eclEP@R;(pt-x!(BR{S&eU$FpJ
zPD_2_Rp;npiZ0KAmqB_Kh-{uRQQDCCx<jNrcvZ;EA)Lnbd9E{H5a!6qWd8>ir3(~y
zyKIOL*cO{v`WON$1L{91xEzky@cKe%t(H9m7fjMd$moA_|1RVs#!rU|n&<YtFlcN&
z)EyB`;D38w-$2TPMU2SRaDa19d5^HH)6}V?P{|`P)Q$a5&X!Sy{lJXOCTDH&1cc08
z-6JK%ZQ#vi5pG)vtJuctNwVx(xlVIP79aFe0L}(AX#E$-*mh6oQ)p}+tG!Nacj$^I
zN0mvsl1I7gs7lnHQ~_QM7z`#VI*FC4*PtWNE=qENh=A|bH0g&HW~^f^e@ZN$MU|($
zS8^GuDMwkAEMN=<35~5;!zu`xnRn#<5=EOxYuexc2jL6fr%0hd@Zz{NUU&-vUtq#U
zeg|3BOREm*e$_V}+zb-G!N7YI(FRZ!QP7}E75M$+H&G~Foy`$yf0>{f7|i~yrt;&u
z*XleNybM7Uz4U1PIsYAw%CBpag8!vaVK8<OawK8)&0a=rsr=j^MrL&iIM%2K4@{-Q
z(>u$qPi`|61+%pY*s}J8I_?{_Tw*??-~59B1Tz=4203gJ&#1trB;l*YyWDf$kAQ{Z
z0LzkTh!EQT&Pg!1^MAxh4n=xJAzOuv&_vG}uT^6vUUjXz9)I1c?1{*1d9k7rrGHjz
zDbvEcDL1<4TWA)Q|E|xh?x-_QHgO=oK*Z^!Mi2lMI}uH7u}B?$f0`s^S|jNI7Tj#4
z>vhdRy4iBurk3p6SpBWP3l~<SZ4yypzq{+*>l2fI|6hx#ts6w50Aa`oC01|3g{r<p
zAn4!2ORmY4gHFu!3K%Ty^K&>iQJ|Ca1S;!<PSK^wm^fgBB|M^zuQgXODhLzze#Z>o
zb$?lS;uFYs@R~s8HQXd1BBS#uXd5bl?PgQTIrn-Cy7X>W!S+S0s2~_~Wt0n0Toxm>
zgdl^a6f>Z`Ahwa^^QQRCE?l7vySxIzmLH$xM$6!qPsb|9>@k^>9AUkjv&4x?QBT8&
zt97=y6d#u?9J0_FVE?f;wPsNT{vvC_+MzWl-HWdDgQ>Pk-*rI;*61|`h{f|g!a4hX
zFMpx5M*h#{_ydoDI2a6hp{gNt0%P;$vnNr}bz%20#4J9u956!@<vcq^0tTxykn9jC
z@tG^K2*n9Sd=w9NGFlX6ZJstePZ;6B&TiOJ4LDsNXLc-C;caZ^tAyJ)#KfEPZfUU9
zxxiUHZw$mQZ9<ZjaPLyo={Hpv>zAGzGRTLF@R<B%#H^QP-VRj_x3pRZLbmYn=JnCN
zKF{eOx94}~+AzX_PIbGV>h_nh8Ba?xv3#k3zABhE=uo9LoJ%d?8$=5JKaJ#UQIJ${
zC0Z(2|CNN%u$gsnwWBc6Q<Vh?$wSqPzl5!+)z<q$%=s-rdPab!>2M8vgg!P0MNqiL
z=mlR*z#(c!FTTdE&X~T!o*URBm2!3=4XLvECoUg&EFKzP*;ZS~3I9VZoxOR#^^4oU
zisxJ#hh|+nuYnNPFL;Y(a)OKUKq^IQZh8mBsyldq)!uKLZB;fv{Qo4K>zZ*I5;3v9
z(qzWP>Gm7H@LDY=<W6A!XdSQYNTSl%=O6{aLZhtb?@2B-_vf-k*KGR&bG`7oQ_{b$
zY8=?kNy7yv&TIm4wF0$nw@@_D!sEOBH8w^=v;`r*jJZr;r(!kk$TdTLnoY!zE_A7Z
z-dx!L8jBC068LCO3>GPnHIIOQy;gp9LsW}`iXBNKkio2sG0bg2A`@N1o?f)i?|lY<
z@q7$DwLD}|yKlsen|I04;Gu_zkn;daZ%VW%BNYjqtrMP!vf*Jrzho%1sHi%Ypyvos
zBBy4oFm&$e+K{YYb>(Q}y7h04ke{MXC>V8Rc%e%n2WVnElguDOi$`VRT42qHK}D<;
zdi7!`k)DG?d1g-=7?KQG3<bN1cWPieez95Q%B0bja2A%#fryS!)v*PMSdGL`Tmt5m
z+JWp8!F~DbbW^&lHGjhn5L&xax@WB+!jDPoC|a)atD|I>7(I!a&^SvmW|60g&v_CI
zySnxk`G-N3oUsFl^jVXx!80vVpxk5!SLuGXB66TCUlslt)aHvFb68XcXp3yU7rU9d
z4xAHr!N_j|MGmDpUAGlqqrW&cUJ+x6c2Ud@p6rRr{O*iv2lAXORhR{cJ219k<Dx=O
zKc{fNI~N%$qC-vD1vL|h;$pXse@?zdQGND6ZogvA1H%eD6R)gWPBAn#I3@eN11rmR
z0qNfTUTujPl_K-9sMqLPuG(q&I-RPitaLF8Pj&4;9I*`RIp&DZ4Bx?^qd(VoO>DDy
zQL!xID!;3TbisLALo(`>if(}{0N-obG0XW4Rfl`%W&6yYojbiJ+U|+mD9y<YmO5v3
z3*|YUB_fcgLERvVM-C-1Ruv^zdg1gJFFZuPo{@<w!YL_Zf1j<Tc?5)ePs!xus0y0@
zh?ygqB%75m2hVt=y#@`;|NH91>sTt|UX-$?j#0lGM*!xlh~Z1xAG3bFMKd7ti(yN)
z5@g@fiTFR3hd*$0rQ1Z-=c~(j0!(#62-n(=nTLf-el7|qF&*Nb<L0x-XH7{YI!(83
zfz-__bLjk4x|xpgMesB4uf|(>*r=)t9>`lC-zjyx;$2}2YD>~9(6)%d@$01G6=kEe
zg?&tUnGOWXwE=H2$@I{gu``Or6bqbD>dkEYCc^SvmYa)>qJ(7B#@5vs>Rw62k33(Z
zf-tzGw2i-;{W`&sYehTcPb5RHw=;UwzvAfQb4V{UWHri3Eto5{RF{(P*7umRHE=)%
z&@Wyi_QN*tW;9F|c7uye%GT_Y;-^c~Kq^sLso)a(Nc2Lsb$AYb<7m;0E@qi00v{k7
zPM$Dh%+b`z#a1DQzW6GirPCV;SA&G+$Ti0=ZD`!r{hwsf3=2!{FQA_xrc~Kl@|lpY
zjqSH17Z9dDo^O~YIFX6X1z~-`>Z4}1LLXvc%HH=ys^0lZ(VT<g`JQIBUM{IjU374S
zILL~Oa9F8UnQULX6%Z-W2RJ=IM2+M|A3)l)A;<K8N{7dZKcky2a>Fpvty@cZeHUF3
z`wm)8a|lFcPtzQ=wH}j|a8{pc%&eEv;Je(jY5ERM<vGE2@{YuXj7Pu5yoV)qk;&o=
z;q%3jCuK{>3Fpdv)wu_op_^*bX9|61{<3aL1r2H#KeQP`cwnIhJ1{cZAv?U;q)-?}
z83Os^LtE|mx&&u?6d4itJ)sPtcujSD1*lP3_v!ON(!dKrqj!Qt&&NQqdtu+kAPZEj
zF6L(R)YGOSxGEb^okOI0t8X=F08kZ;Eepp)a(%gC9zJb?KXtyzR2rvm*v|JoyE}iK
z@Yq(8c8-@3c&DX6aQIB0z8IRNz<4;;BJ3EFAslDMqO^H@*hC-|wZTq}`ZLsOr=o_|
zrhFTFRo{7ED<S8$EBgpROE12#1PmtK{j!`5J8_gIAFo4DX3uGOl`U^jhJ*&xV_rZa
z5wP_&7JAZp83M{#{Kj~5sqWQmAQ+&qQY)`^_F?#r!ib@}+0g;1UPuEyZqQhvI_PC%
zDm4VG&f%7TxX=mFAtpcAa03o-PI-lY^{)>-ZO;Lvc~}X0&rnyqdwHQJAT|`a%sCaP
z9vq6gP*b;Uw60H}cG6sF9XZ7-OUD85R(Uij0gZKd)sV~9oV(<Emk6+9rrRTM>skB3
z*9jkj{V`0&{qtZ^={spgwmIq*211bg=_t_q5xD>!>XpIH&=HG^fVw!g)Q6r=yd-rB
zsm(?z6*eGbdX2?MzzkGG^m5BA8hQTPkKTUSHVD?91IlqG?F-;SNl|x3#Qf}^>!{XY
zuQN?6Y}KW&4EiuB4BZd0a3QguP1_nKay(PkM-~{UjjP(k+>?@)XBX0s0?8|Eq<zoF
zSb@&2TVUJtOz$#a1$Vb&O^z}!<`!Rb9F_kg@0_;suM@8;m+X?R+!#hmrs<-vMK>95
zSO@sEfTK&81;+O%eZ@f(B~gG^!5dL2#p5ioS|gGamO`=^Q2<*G<HD%Qb)i>5kx-cn
zhPt4kGmS_IT-V8Ye$`1C4Q3pTI(e#R#Vvkd(*i)U;io<aR<z{H#?93wg`FwIO`|YJ
z$FK&hvm2@SAY%(5Xm<*i(z|Tn_<}WfPwH3XUYNhajtgm&rsJC*N&%_ygj#d=gNf&F
z&wHObtPr;?jE%Sfb8K8$V~%F7_$0t3HL$_ad|rCNV1D3K;uirYbNB9BKzB*OB^yRt
z;74i+hM8%LPYEkX0m1P6s>GZ)4f;P_5GEv~>nUk+`&1vmv4SwO*fyS;_o~S~CPaGt
z{?+o5D|STFHD;a<qVm|zHA4m3oA!Nv@YEqA2!{{aY2id~{M7i1fy*8rx1f$0a>taz
zp!W9qRLvogqGL(E18}s?gBJ33<ns6eqQRxY171*0a<uW~Y!23F?8)&cq`2P}Y=Oy?
zTz#@KTtOktJ6(fOO^(IH>G=mn!{%RR3Fxx-!jdx-UK+2M=gC_CYfaZP44j?aHK}!%
zC^?rI&h%tilK}td4-fWWXTG*Pxrt-UA_!OWL;zOkz6f4g`l}B6g%~0Og7VvxB$=QV
z36utz{8I={#lH^$V!{KU`KrRrZXhN~zTysizg?;p!O6b=xEwg}*_zSaLL;#IGNL)#
zYk~l;vDXCrE4w<kgJ}q7S;gI)M(Q~*#xWaj5bM=Q*mxsVn{9p8F83gmg$F@HF?4Yo
zf~`i*n?u{#BQ~o!oQ?)W?ux?l8(Dko+%JrtvgtsL1Rp;&3yYPPVlI)~;`wj$^vCI!
zY&8SPF;-f8`k$U5KvbPDYKoe%v4y}PjnrdltJzn`Tu=e|^)=oa+0_@$z$Hh`^YAE?
zkjeB3T$_9Rh*H|RjC})#DZmQC79SVM^Q@gSFSrj00SF?yUL#z>OMKkSw@U2Mi+kEJ
z5(RDR!5XZxnZ8?2YHbE0wUS6X;&{uYPrdpP!NM5Y=1#m?Bn@x8if;P*^CtpY4(eT0
z2J^N&PJb|JDxSr4lF9KzE)nU_p?e#{V;DUwNxa=G55xqUdKfO1*IA=uTl-p&pQsTw
z$eiGZ76B*~D1^wubv7dSf;vU8&=x>=8Gf4Y#S}AU5rjt&Q@H3M8mVD#%F%<xUxg@Y
z5}cEbD}&pVx+@ZNS4v8K_!$iLN>nD!f3Hq3b8=i`{{yIU$4PP@%|m$6=Xf2S{gQj?
zpww6}*J{tFqX!)wA0?kiV?mgV*0O66A!bD10S2C-5x>;;77Y3p1R-rhgI*k}bpW30
z^Zq7@c5y;>j&`CEVL87$J8hUQxTcGw?59$RqIb&I;2}vpz)N>$jKLW2I*c;Z83)Ro
z#6$!9G~$trRABdL>3hgc9gMbW*tHnAM1z_W<?<bA(&kz&AHmZqZLfrjA&p=#;mv7E
z#nRcg$<@(eH#P8;IrVnBv^Rc|8#Y*v9GbRx!-o8^(_GHzkf-&bvBgL2D_YI*?^y~;
zTmlU~3iphQ7!d#T`W`)XE5-VIrTMMvfK98?J;`^sl@v}$b52Y3S9m0jjb0$f2HJJ{
z0J1G{k$^&uwhypU|Aretc?>1F@t;e-N5spOrAe+l4i@6x{-f+XsY)hos)mcm_*W<W
zIo*<|j;b=uh4w0+LA|iDmca4x<y=jIJJ_pEUsmGVhcK@UCWhm6jO);k0=qv);WdL*
zlMV6|k5qgepH$`g9qOyB)VUK0WWpjJ5fJ*d0)gHCIDFWJa;w%nSOD8Vl_&ujKRY;<
zCPSW~auo%y;PVM1{GXQc2O=Vv)__PRQwe}xbvD$ikxu<_DU06vY--~0s71d1|8GaS
zkmiDz?*`aKh-{L7>{v5SKq&80kpjwZjtUQqHV`NC#PbbVge(3lCE!(vDy(Fl4yg=e
zinnPXl^3I<=rO#&-jqQ{KC!c9;qYx!LWKSghUf~62&`k-`YO4xLvC6K<&B77ybPek
z3SU1ty$3dtYw(9oTzX1^<7kBcgH&nxt~0wHtW?SNNhIjZ0t(-3?c$$jqi8c@{%u6K
zrMXd8&fwdHd1*UiT(L2pQo~kry0oVQefsTs25ta8Cp8*^>51}Kvtu6gd!2LxY*oXz
zSN*Lj_xq!hz*+ZKT+Gj*j~Yaj#r16b+2NG`7MgieQIhtH-7;A&=pP9}i)?eJjThsq
zYw>TL$ybT1KOa+vbvC#gFt21GXdA!s=BrJ~+ME}zex7P1mHtPZW14J!V$ODIZ(36@
zk;HAY1Jk=F73U@H8hg<<pyD>>jXn3DyZq`h7$G_RI0!2Fk|$eO0MT0xep$9VcDe8d
zbaLp_hA<c_ZY@Af5=Y9&7n3Jft+|90LX39#r%22TQjEbl!+c50h;a=tDt>SKsY5U&
zOnNxPmDpI`sNW<Vj}M0=f1A5(56y_ceR2Yc<1fn07RI`SV;gIcBa?$-+-jCbhr&Ni
z`r_#mW1G%g-^~rq;8mW)@^o)2EP=8}sY}<ZT-il9Q$28`kAYTCK0?I+OY;{Wb82@{
z98%|O6&u#FG~yj<)*cZ2xXxS?caK*7RhYDA+Z#ot>hk7_G>iB7aFbQm8Ry!D;H6HD
z_QU^T?)WmeEi^f3z(sUPLz(5lM|O0=SpEOwAd%oJWYpsK7MH~qFORgHo~24Rwc<NX
zZr{WoG=LAxa-ra`vxQDG{?awC6Fv_mEKYtQXF)lcv{T-Y=P85ew(=0JK?BPqBl7^y
z?uD_^&fB`_KqKks2!ZX4yHcmVBu+e1dls<#*>ndqnm&+aaA3)e8}EQ@JKEsY)qQtq
z{{if=n`kw;auc>yH(>O^OthLEtt}FU<JMns7@(Fn)kK6#Ux@{Pb6{KiEVY?I$;^0h
zMR!SGt0Nv6W^TMYf)`n_DNf3E4KU2^d!85Ij&Hzo(WIGC^u2u2J@RT2{|he5Beb(2
zf~*W`gabW<srW!yvvORruy}S%Nb)Dj@(s&fJT3S+EW#sNAHaRxI>7DkTOatVieEc?
zyzFjq)9E~<SwEg}inOrIj^5qpKy>v`3$Dn8ZMQ)$|9~suo1wO5h|8FeK{|Msa6NrS
zB$#N0`YgJz*D3@FDhK@}?0GB<v(RmY0r@s{$&zH6#gX8|@p*4x6kS_LZb#f9-kb6+
z;82IeEf1wbp5xuIX2ce##B1B1^QdVavmoi%p>dcIQg=e}M5E2u@oE@Xr2jeCj0y%{
ziqRGs1#aq-YS&0Bq?^Jf5y=3;#bm%;?X`4{ET2eW>wEFgI98QOXv8z+Dq+w?xqfXN
zKp~TPdN4_xFaPBIFO&N4S+L31|4i74A>-7X4!D#m0XNOXh2kPA1(OeeB3ScL0oYlj
zqt&Or1<NKaVVmXW5?#ZGIDLD4mH=!AUW_7_kIW8`u5|G_IiK*Jz#;eU%H%X?8|z%U
zKN}V%`w{gV3|8>AQahkglVlb923mX>G|9bdm+27w4etUF4i1($`GO97;2no`o0EBJ
zu}u*dd~m$$Jq6=tP|zlc9Y9=0f&-mwWKq#kks3iUtKKR?#zB#wi*E+fsKF}ve`Io*
zZ)WFee1W5I{L>8t%`EJ%Pt~xcBqKn_F{8<+op{cm4j8*nFMe^!r(Gcw50m8wjXC1+
zV<@Y2t~Wb`?c&><&xRt{HIYzh2pZ?%n1EaA?8y8z9}FJ$dpacXJ&qA1{ZhKDkyoUA
zov7lFqaJb|yXe`#rG%Ae#FYzN!=)M#42xEy7n3jnt|u+A=~|t{Wp#M@GcKsHC)DS%
zw3ZX-L3dCcg_PR&LJicjKe3ZaNIk0NEk_;6=%q;@h&Cq%4G;KrdPAG!^Z6BKx2vE{
zPJ4!~@huGv&+t-bOvCwF-@(9s>n6{gZj83fLqLn&q^xV;^Kb7x4@=&6x-Fe@<Rmp3
zb&5_enjShuw_ekPCy|p(aCXEC-&79)UQ*O@g(6ffchu;lYHu2rl{Pdn_)Fq9D5EaA
zNoL1G&=SC>lzo52h<{!Sf~PER#qvM&E4^lmh5SKA<C;Kc$NA!Xb&f8e(Sfh?ysUUC
z1j{Adf}lrOg4X^Qh#U|mIt1A7$BemNeegma)q5*jRBC|y>R>&*3Y~vF<fLc4tk!6n
zmIyTN=USPM@PO=+3XcG%ZA&WTwq0HH_v235p)Ppk>gbqja%1s~9m#wido`~26Vq3~
zWE7!**x0SCcfeg2wJf}W0l%Pk;p>^u@TZge&Xb-Cl@Qae;RRbP|C9Ztr<}w41VX0=
z4*;4z1Ms<lKnsPk=>T1?zoll}dDmIB!0sXcC9{M%x{}{>dfVAUzzFEZ2$}g4@omKg
zxD}@oAO)J{Pg7+(GoBD!ini>re2@BrXob4}H?dP<xRJ0}0A9?oN=K~?7~|8eaeFvv
zRXkz<Pl6gplp}?Ru-nbL@sm81YScS-Rq-?Qxyn)pldjWuCKq)V?p@3FV&(Bd)lgK*
zdI_=wsHQQAC;RQx7?5pAX?2x4Fo?kC+@dr$$rbWP8GkGmkCo|T%gT6LcRW1#&iWWn
z)iROw$!v98M$`D(q_kQ>F8gqHp}ksvUJ4(LwL^P0=zCzYmhcfeToJ}7GJoD{2b%;x
zq#AdytadN_MB*?^0c+VvKR<EJPJVHgYEj!-sKo-$7SMXiO=i@p?Df3<qGr0E&&TGN
zJ*@M$dEmr$Gk%p4Gq9RWDUW0>TG*{QI5aBBN?hMxEy5gpvPLaBA9su3;e0_hK2ktq
zcJ+)o+1B2HcqS#9L+F+T332%Kdk}@b!&a-Jx~VH_eqc@E>G$LCeC+;AJi9B_bRE`S
zRu~&C&A0INtfT!v1wPYcc?^Zmb&#Y*qH4}R4#*|6Mw0i??$Q}Hm{(W2qW-1<!3Q+a
zUb5*%0>fmYHkqXh%KK-KVM|Dz(>o-oXt%ZCk|Ynr%+W*t)#fG9kXBLLx>jPp-u%j&
z_Lan`8mzVgRN1k&^ZJ$ws0=9T`LjigRzTjNmmM6N72w;kLfu~i&YO~7F&`+Q7=05<
z<bwb>22GnS^Bn*J)JPfeI31{iJYWz=M9mV6c?}(Yr2(Q%{N(zts_+E_WwcduP$}oL
z>T7@Wh$`f-vjbZ`{wEn}p{3a7X`M%&+mOQawNg$B#w$4KN$WTquwCL^Y|>gnUsnF~
z!QE}I)eJmEa<LUN^Y?~qxw3pa8Eijl8>)JNI$xs+nSGa%Rdcgxd63enOBAViFvXm<
zq{zDsO7z9}wHs~$3vMt(jS$9;s7~5RdC?%xKo(%95Had>pXC<B@VpNk85}J*oa!#K
zfA=xsT9XIRm_Vm^#j}KgDbo;U)JKpx7jWjJJJ|Pat>8f<xHplzf!NPy&JtgUzGZK`
z`bTZWOF8zmjeW5tD4pSqhplhW+Jzx)g$aJs@<iF|!h3Mc&r|;~KY~_D8pi)GqF7H!
zjbRiMBV2e^l`uFyDf;3Gc{CiP9j2uG=Soi!H=Wb^*R_*)*aI?qi{t#_3uNCWd_Sv~
z02QAHf<7oJbSA5FA?r?#uS~)$$g1On*SJoM-U@Z$Ha?JaS72lPgs;%oxWcRjAD~CD
zc5E?!U;aOPC$Rb%Woo_D8PbKn`zZf&5-%B9wI5%^$;MiQLlNu;d{Xn%%@C<z>7WA4
zv*L1kuEC_dxbQfoS6Z5rzbpvU-li0Gfgg|aKpcVdkihlC!UxaR<|mh2EoXY>+u*(o
zRy!G#3DW>WSP5=zq~$F-&fYw?p4`;cXHW^M`;(JW8=<IpfLrOlc0#({?4P%FjSiYi
zJpt8^$+_A8Fb|a)$#j;dEU?)rANui-Z>!Ltvn3ric4D+9ICgk_dNzKp{|sBtPB*nC
ze`I}j`tT69l~x)ux#E%3A){&OvgsX$510LCeq<_UjHDmigpBV+tIf-x{2yVAnXbqp
z8?Kv$$kQA9s?Tke%zCY|i`?uA3IbAtc*T^l0hoEy%ie{w=gHoT=zWf<&)6w;3$jnr
z4eDu?<+N*8>vXOw>}`;UD>qAaPJN#bW5-1I>eK=WHRy~^-T(;Zp~{X_Cv}*AAd_eI
zx`wgbhc;rM7YKSi=^WeIHsw`~O;t4l*Ji3bkx(EGWb<SG{osKWh!Jvso9k&$R_QjO
z?Ro4c%CJ1k$Dx4<Im-7QD#-kgoTOm6{db4c;R<zE0}qszgY7^A2?vMdXXl%iv=l%v
zPO-M>%@n7O?G)<w9Mw-1Wo3m1XTkhc_1<WPomW<-Y7B&w)riRap(tB#)qthZ$gDPC
z+`BD5IPJ<DoQ*O9d{Lb(xvh;Ccw_#lV^iER4M`V$OTBxVPKc8eOC@er>PD}6DuOwz
zC-OCS*4H+u>@;JF*%oeZovj2(%NEKJ+n8d%8OPR2(b40tx`JES6QeBNBe}{Wm=)&a
bA#pT}$R-A{0dv*V*+3Hcku59PKWW(6UGf$!

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map_small.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_register_map_small.v
new file mode 100644
index 0000000000000000000000000000000000000000..8c1b43f7da3ed8bd7dd634aa82b94d7bfd01ea01
GIT binary patch
literal 88576
zcmV(vK<dAX6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl?M$34HY
zkb;L;;}LZ}UV7yhdU@(%WnDk}kUU^hMcEfWu8KT1+JmvJlHE$?%Lq**)JvU~)l$L3
zy)dX7b0SFYpdm$&!mz?8b-UD8F}np%pT^Lo9t?kC%6qBgwfMQ=ZL^}wGd`wG+QHfA
z6%og{Ie@y&U6TB(O->s9g)sS$P5YerT9Bqn`LS?B)&+~fS3+?-k%=$DWSbn1YZJNH
zLFP}Rh55!1SFR*sG)KgK>3DV`wDVQ&d=%<lx~*NCUX6lOrknbVGZCxKkij!-YI9ps
z%w!3-p8A4s$p~v5CCoR&9XJYLY69OxCGTo7c{%M9^&)lF+I~=m$_8cX*{8E$fY$fB
zco;U++W#APZgGZ^cel%Kz*7g__%qMVZz;ok6VG5IT4Y4}DP!)_+NBYSE;I_%(A!)z
zUe#9?5<{W~9IvA*N+6!G>?pxRn#M|A-5r6|rf$zIv|>&jt2ScA1Abv-To=TM2l^u3
ztc_lNmBtG9XPD<r$Y!W|gVua1#KbK59BUhh)1{Nd?_X!_u^_r-k!+vy(yi}Hn>r4`
zF?_8(z$-f_5hIjsv*&khhPhNZ{@5q{QtyTlx)~*px?zRVoF%vkv1U=0j9xfV>ZP{h
zgWIzslN)_5Q-oC30CINJuqJ7r;=wcB`&i^sR5vn`tXi<B%U6If&f4NCX!;7Z5&<><
z*cuHSGk&;>5X*g%Z@^}yJ<8W9Y(*PR$t0>i%*KP_c8zCT_0aI_wqW++?#wE9BUjZe
z5l+<4gk;ySfSVS;4JQQEa8sNWFhxi$_KZ7#bi5Ly(rgrNCBT}<^y!>~k)>7Z5QeCZ
z;H3iZHpB~TKJ_Gw3@g6QkD)Bru4uq1$nRKU<vt&jyg_%1$FHOA!&i;C5_eXn-#J8H
z_I1h%!?F^&wL78?CXjCQ`374DtlZra-ygX~L^*1QOtNLvI1~|0zClP&SO{2iKM3h4
zyuv_qDI)?_7g$sKQZ$SLuiQ>{rZZDtq`{yhywndV*}Pg}FgS16UY1BU>9pj>6O-$V
z4Ue4Obra6uXo2`ttFQ9nHxcjg7lROY4{oyg=`<#g8n7~9tCKcgfxv)Dh>hvp@63%2
zSU;fz7id5^LU{_GmNpF-xC6dxB8}a@w-JV;a{C+dUhRnVrQko<C<Kiou_LwjS+(fM
zRw^46HcAKk){b|gopU_slYU=y4(IeGMorh1Le8tb!BF~PMVKT6rUCu~#I$0d*o}av
z@<vcN)WaxO;eN%2&gh<uV<B*|lCk*+s;yA0Eg+M<Fjq_RQGi41L+o-`C6H3?|4zm_
zufQ*ji)gVky6A&T(d}zs58!n~+=V9~mWAhAz_}A^b7dWW#`wUc*IEF@pBsd-OL(j-
z7uHCRd`AKlJ@Ov%byl|<hNsPzMNM-wy1&!7n$x|=V0QgutMW}gDeC5D;xa$Cc43uF
zL52L-8UVY@_M1-K@zn({ZUlm1UW-K`U$EYfnc0^|>sZLF>zg!y|D5u9Inz^#SV-^L
zNz?jSe@Y}P`)m8HBq}=En|-`0D!mrlD2FwuEO??v$pn{)$Oah(l8ttyRqNKu!vV_N
z`S)<uDiB)nhq^XZBQaX`ZVJ@_Ofbu}nUtsz?DKdWt8~8|)3f0Zv)FHNk*tL0{o<SM
zD@QkdRMv!II(q=(p~_wLCA#~~6HwE&*32?(4}7|OzDJ0Q`ax0XZ?4pO?J$ct;IZ+J
z@#}Ux{G3MWmHHm2i0@1qRaLBN(~lu(j}2Xs7)@-3oAyXp+W;Cj0C-L5RyWzEMQJ#9
z3-ZI&G^5F_BA8IvKiTGwJ6J}y`a`l=B9<|zA+@Z>F<^TLd>4i-)M(vi<IIIl<IT-|
z!OuzY$wWc2uSual`fqhkV5ZQ)WlF^c0&3W%XKQ{x=Vz+6Hak}5FrB$f>Hdl9dk6CZ
z_pFv7LDLPpa4zvNDXE0DFFgUSffh<SM6Nlfk%6q%Qz<1Bh{ve5L{hYdZxjK+yNQ8&
zzb2I_v-rN*^jw8UJhJzQY8mQ_-JXbUoLm`8448I}nVF_G!l?Wr^(%OCuZpP->ssV@
zU-;Mo9QidCR6-V#;cc5Jg>PISL<1MpS3HwAZ0MfCQ@>XFzr|?}HhS|6Bxim}70p;%
zdegyWzj+Z?PErG8W87DFW1>6)B~Ae~)VG=@b|5aC0=i4cd{fweB?PH$PT0sY5cm*;
zMCim1x}&d_5`PgTiG7v#ZHGM{Q(@*i$R(QpFd-pAJ4C?hx`$0e=AaY$pge&WY3IqF
zTj=-6;qN#|)I5++FfFn-2@au6HRYEK6h%T<vREMO5!Ib0`+yM%Hx7X9q=$AYw@yPy
zPIZASe{#b755$L%Lm8kL04sKCW^`5Fi@GGU-_zLuVMV3F&QFI%EXJfIV2dzVr<c*B
zJVRN3a?(z}cB+VcHF+7g9~psm0bSa>)I%Eb`KTE)`1uQKK0H<Zk;^)%c#UMT+jY#k
z1j?u+VQ4CTdZr@D@0((D(Ya7xCH=(|W64FAUDB40r*!0Z+q=2EN!~~bSHd@O6E~m^
zjSLn?oC|VIn%`*OigmppbySTJQ<s7}V^p9|>m`Xri=G2}Vl2V9<6|M(h|#Orr13+i
z)~5sa=<3|SW&eOqt}C^0*6baz_%xI<FRCi94qcOqQ__a_9x%kdzx=sX?X6lyxcv2r
zYY~bRj+w=7vz_8T?>yX77?^OoTxAyPKNo(!CaM0nW|*I}>_obZDl#;{uPXPh@K$uD
z1l&sO<va^uWrSWKQ2+q`UJqB_=1pL>mZ_5itcp~;H1<s}bc9=@-MLTH4YcD_bXBz#
z+{17cLiL<JbiL#<>*SR9Env?-dlN5!R;m*wEiB^^&Z<>jDl76@BTyVW1xv0e{7FV{
zvD1=5cosNVNgjdmK7hWAv=Bx)ix430er_b{A^Yv^r=6{K-Ja4V->&0Jscho^RAROd
zU21ZhEFPjQrg~_4RDoZ9&EOHDSKkLet0`R(Th;VdlRJ)yZeh)OK>Y@rr4XH4oAAP9
zkt1y}e8-_o<1fQo-;`AqNh0f36j2(GLRbKWou}^80!y{iHI0cN$l=f0IR>7$rbMBI
z5I=V7d0q|BtwlbR{vnwGvXRqkilrc`SCP{wRU^BIOJ#U@9H?7W>EQ~l*8G58UjC|p
z(oW6#aa%@L4p)%pS;QsQFM05FO_tn0l5sd%x$@W}<xN1PS_dF>3gFu$o=?5ANA}F#
z=XpCYf?x<N`hZ4&_{G-~44SK{_Yu-3kr^Hiw9he+&N!XAGBBoZ8pujr6z_&GcwC^X
zfL3-nD}*0>f7zwd263_Sv@*2^L0CK`PCwhb>n_CB3wAd;YP4U~yrB`W!0C@#Ot%7W
z70r?XWTkQOyPZv})3*-Ra8~0kJFz|hojpyo8~<7NBY;$I)efddG|e^fagm9+OsU45
z!TfTnot!&uUm1C^wg+m@9a?)mS_db<w!;8<l(fSE8~-N!C4QSJg$+F&u#5dWyw!$)
z(*x`b*je(8eo{8#=W}@>l273e5;Dz|{TxNOEAg_70t8b8IySWEFUPVQ6RmFud&?>y
zFdDRYyFEX};|{O1*(2eyJ0*8b4HqjQtdE2FrppGX_vF(G)3t*3_1S~ziFo^Tb9ZtT
zZC4Ug3K^bcnk%Imdw=2nZ$=B=H*N{Ywc<SkLMe{zTBql4Vc@R^;7XAfNUSuCnsx!a
zwT)O}@U|SkpTHr~!ZULSn)yv<>N|b5;od{jH7SuIGRuks9pOyoGF*5Aml%%R`HcX(
zs{zmj{dQ?wtf4u5A;-(S3(Z;(K_bv%!|h?d`Qg>Vq1^^n#`6{rv)Zm7F%NXthKRta
z09<$!r~JaLR|<BxyD=+GqPKrOoE-KJ@hP%#0a&{Yn|Ym#j2-$R-LO3}P@UTBYcr3a
zvt;lY)%P3emj{KFcmSxexxCZs-3F^IOvFZ7)S4_SVy1Bl1d@d!&D~%(4>jTRlcw#w
zKPxp3m{!59%k&E+!1f37R{DY!%^>W8iunc@T{9@dJreKw6O8$YE86w6@Us%AH;$4a
z6#5YUkEiopcaZwoE~3+#Bh4$;TNb3bc6p9;7!lWoNGjc5y7?6rOp?=(1u*ggdQ<g#
z*7*bDZ2nn;^iUb^u@Ol|EugGIS~*tR>eI;{%%G0t<3;A#r7XL5O%7H4IdgGT(B^<e
zt-7aX+r9t7gRGRS!CsWi+bO?-BKV`jAQiv39Ss}w?hkf4u|@YJ2Xy;Q1{WJXBc_0%
ze%MA(Qe~{p`rY45g(#v{_nAcw0TFo)-(UN?tEqUWJ->7=T44I{VP!RQGk$1~c)1OI
z`gt;`OI#;((mW}KKGgIM&`udQXnZzU;l?<%^m8ibo9c1_HRjNeJ7N^uI@CxZx~A64
zUu5_wNnveI)5w1T_aG{7qQ`EI)1nU{IgKgWq|;1B*a6mdgB-l_KClgTL!xyqn;L$`
zwpr>s$T`hJK)}*7+?p<B9-xa-?#!Zg2~uoiB-^W42Bxdu-B<28o=dX@Od$6k&PqRz
z9MnzttM9m0*=qQdY%Rd0czEDDJ;LBRkLpr@m?Kf?lBK?e6f?xoAcUIfRl`Q!!$XIR
zZG;L>#A~fvpC0@dHWG_l+Rt7dI<`%gqV&62I1d!hJv(<6%@U{HeG#6_06w;l7|3j{
zm$1n4<5!cWXdt)D!K9kLC>-5iK1wR7Xdy2xlVNc-Dc#=mjzk>gO?UG{H{3fzf%_GC
zg%>wHzwpau5!L~^&`s*Uk*gQoKe_h(P_9P&gbSUhPP)_HWx-%Ut#)vfd1p1Xkt^t%
z_wKxJS?7X8vYXpsz1{hq;LKuF22%bLUeAdSs6KYYC9jfUJS;AffptM&u7>l#1IP1_
z7O!Usm?{VC3z=zKhx@6!+ngPIZ_|GTOsZFm=Q%#XK%$9LWSOiG1vz=6GRn+;OCS*G
zBk7CzNnyFXVkR%{HWZ))WZdkAmAZ1LeYWhWWL2$_AN%&Yohjjw<}4;R=B^RCdO_9S
zhioHTbxpVx=_V^98{rUFtUwkh353Ro>nWr#Xb}?VBBWXn?q^KJ4BJv2t=}2*@1g&#
zK;2{W7HcM%3Ho311B=3C<@VmNA0^0H+UTpld)~Y_W)0o85pV?wkC@P&Lm_m|<+1_O
zr7|sw@O2oO-YciII`orXYzI_V6CF^2NYkFQ-9_OVW)Glx{f}Yj4~kh_5;1cFdzp=Q
z@R!Im@$ZzT^c`9=8Pl_)o$l6+o;JDOgg9N4c*2LVRB85NBTVE_)0AF%o}2H$TX1d<
zX|`kG^>rx!Ovc%Hgs=Q=#K@~pub4SdVj&$IC|{1DLCUwNqad>zJV&3arXHQIn#hnT
zPyKTxLM7%Irf7!!O5vY?40V)UV6`xnQA4I~7NyWap)ScXiSlH;9|WAG$D=)m8&5O3
z{CbW#Q*!W+0jW6NFfa@2girnTHCusC_=X5T(~p~JWy!ZwFBA<}5cep(y8{DuVC^08
zBd}+SXOvm;<JuhrK4QM=;Ha;;rx2X8Y~*Z$<<P8=^Jscd-ixn_w<TyyYf{kj+-XCL
zj0cF7tT&zIO5sx#ULx*s4+H7l7tTlG06Vh;e6~V74A?>&S-`BsDi#kV7b^2zo(7Jn
z>;iVKM%jnx*@3--^az5}10w0_z#6OFv~c%el!lXY+i2&=;nf4_I9l6xzD*J6#i^z1
zDKA6cv^^UVD?B=rKa1p$QD6L;OmRl^AX|4O4ol#**?%ol9Cns*;mDTy?A7zKRrb;r
zh0Gn-T(3h%H|7dE+1&YMa-X${J7V~*yrQ$QEME&^5A^JV#lWY2vdVSF5b2NH3tMXh
zl(TfYNXqc6K+O|{*GlqYGSQ$jAz$JsW=qV?`;-#3alqLT!5KgsU-91oE}*{Q#TkJ6
z=AZ1_lKa0v_QlGy(s>k6kYbP)^3+CAd}xsrpkRmd%{e8u>jaxl=XI~q%laMxcyVTF
z-(mZbap!8##F33SLBnowm}Q1?+(@6U(~i6l#T)FZzHJ3|$=Y!{FCnNkfz-a0vM=dZ
zx;9=nFUL#yWK%4#&yiiy7x!0nOmz|2p~eqfiPQh*!a4?BEU0Z0rGjOQ1f<7Mb_o_h
zr>|j`$bK%YrC@?1nao5I7DSWMB{@3HM{8Z&wD^|RPL9fxdEH~VdtuRcEww;NW$ONV
zz5CipmGTLXxBQMO$8D`mm<5#IUq=!hekVGm0q{jd*2}2u%k{A^*x?(O%7mLU99!--
zeG@zOVdm$<Vl#`<pJ#}AGf|>N^7ne1GP_|{O|XsLX6TX(P-42M2&|(l2%B--+Hhc8
zE#}<{Hu^hGxm<>qQ6|><RepP4v^$s5e4nPBZyS~GAXNpbEp|tWh%XEw&I(4IMl1Ge
zkarQEX-K(l507zgW6u<<^pGk1@f=}Z(%Ix!3vVJC{_lhCT&ey0_~pMm&9Zke!?iq>
z$kl5Z8u&C#g0R0;P}ysTHXP|3%#`~aYnDq0p#%~{ioo4fM|iZfMWn6xeM%*16L%HX
zVb<xkI<EVF++2dxLe00xTC!YXeA`c4|7o5N8~#>e`6hkH<MJ$=wb&mog`LbM{>C`P
z(`%w2rzPHJ>P9@x=S)jQY{|_R3Ba!P@A?Lef~B?-h1sfs{E)O&+3yyow3WN3N*ETY
z5TBvgK!!%`hA3J`zmhVl4EUK~Q&~qT#k%uZ)|Q!uZZqSr1Zuf{yty;eXh2TN#G0Ri
zlyj&DIYS;TT<ThAxTN;dHU1n)ia)bKzVH-moOv{sq*nB-AE@66qR62V{mQ;4+uf&U
z2^sH+AKmv&Gl;Ig@kGKs{e_>jv@Tmh7_}%L4=N6X5@o*m3ecnAs8o1qXNWBpR+LTS
z5!O|!{;A!{JAk;BeMy#^1NHetk?4X_ii}kYY0tZSlZO-7u%`ujOs7(S?XpZjRWuw8
zvuV#|`#b`^;Wa@bsytM^E2Hw;zKnYEtGkRB!5*G8qG`q?$at!Dt%2B)?rLEw9S`DT
z5v-(d#!7@yIM`_+XxD8~6V<p%c2$9#j2-BVkJ&Yq5`XP=CnaKM|JG^DZS{SzEG4TH
zr43YqRv(i>?$=~+1(#&v^HfMCfKb7&_0NT@dBnQbaA6WFYZ3^f<#vpbE!m^9zyoD3
z*FeUypaZ{ODH1UPc*%jt8)>&pk+wDM_Ln!iJl6sidK@d)DRRylY-~gY3Vhoqc{KVB
z)O#*!=LIjSU?##9@r#Z2QFL2LD(Oz0wEyk6q?6SrxXGiS+hMdqOK}`X@}w(6=NzCV
zb<Mt1vkAwU{GqlV&j!>)5*Pp*OvGwK9n%fe<-td6;^GKxITL<k$4aTtgYr5M`LReB
z{^#|Y#FstcD`)ZZA#EmZo+30wIlyQH>ZrGp%0&RmYJT>1zr%aYR>UW8MSbn_ujec(
zA>Ta{m&xR3b4I_IXV>Uj!EHhEIk(6c`7fp7$Co~HU01<sFEt=T5=IkRq3A%-?oU)~
zVYvt+Q4;{&JBI#-cE`~NCi|q*M7ksoq58P4?BVE-?p^NcS(uXv+*0{UB`6D6&e!fv
z6pT@WI1_|0q%fYn+McR)hA5#(x9r83qJm2h&Eg>jCFm(#I)JUTIXjYQ%Z7@7h8YSp
z-6w}JlBIHQ#v|F?-=MCvTukrWtj69i-eaFhq1XsX$I3mN&0X<xwOJ@l*bBDJ`!B{g
zw7vp&W+x_eB-y$AqgmYWwuAap(APe$PC*A&P+dJ1o;xV6uK{{ScALgk@<Qx#l9dV}
z_y6=DEr9A!*Q<OI+^2f8i92(MS!FhD0-?210BB%87~I9{Bi#%x9hYav4vk<KUR>T?
zaW~%9_SaL$M-b*zl$-q*z?M;>=2p1H;X*M(l$1A4Yw(to%9e|=V0Vs5jxUK}w@Lj6
zA``37s=|S3fLCw%rGHBX%L~4ej$e{5Sd{dVrzbtVXKgi}FUmHPh|7k5(^5vek}OVI
zy@M%z`>KNo+|S5fNCaN_vXIT<FoBB^^cl}jcDy-S?M#`L-)S}0qAfoWvms}sW3?cc
zJz1@f?I22~MkvT|LHNd{VDTr2(#zg2;(+Gga-;c=!*fWtZ64xkhO}l8jl<Wc08~jf
zRDkLm<_Ci#N`Kx!Sa@yT+Lr0A1TJQPzibDW#6LW+oK4#T{c#pdiTjzC(Q2>J6<1FZ
zP$84X#p^j(xyaZrHM4CBW^p7$V?IJXKX0H3O1Nu=!a~E4gI1+ZeUmbvV-vT<_jZh0
zr2r}q@_^A#{pf|f&tYM*21~T)WgbQaq3*3AF@oZ_shvK8PNFC|2MyXDhI$pAN2Q@6
zIi<w|{P2nLSl!`(#of@OeF?6@>z&(NKNA;wN`2mf+zq*^lfxmZRyhp4)x&!%;9jfp
zlM`!iaW~Y;Uf<UoJ$1*)g=p3c$7VYIL1QbVHcyG-7GfBDm`r*F*}c+eMH@7i(jqqH
zBznk*Vw5c5MxZO-lG-D}GLcxd_iwEEn&-kO9RRA#zf_Z?yf>D*CaiPf?W%C`IP|@_
zOP*!4x%yCG?R?AMTyB68QOTD!rw7i}?t@3p`penn(~TsEV7L1uU#B8OlLdRNs!G|S
zb$aSyEu$kw4v#jDMA{$02h-w1xz8?XK*_nDFwCAq$C$JL`oRMA!GDYwg_|~-JF1ef
zqFwV1B@N^47jJ7rWb6G)>m-pU*I_Q%bsoHe6{w5UK}J=B6+Rh(T^{Oc5^t_;CP{Y#
z<nZcaW94CcX3FVNntVYzN794ht;zJIG|yLT+@HL`-J}xn=G}1<3gAZ!Qi8fGYnq)^
zf-T-c53DxSE(vfiwR$G?F!0w>l3SE+8*AbJ#ictpzsC2iA47#@G$Tbn!_A7=g%!Gm
ztBwS^qJj<{50P?zWTZ660MU849JuBXHR<aOwYJJd0iA(O9BH3!mlO@d=}ihPciNv}
zkV5Ar+fae#&-VPOFhUJpygHi4cYaTD^<4cT3OF>q-yH^ojE2a^Z01DUf9MXRF8P{J
zWjs&pxJI`LyE1y$$9F&OXoF0anb3-X(lA0{OsbM-ZwUjeldU>9JGTkN)#rsBxbIZ@
zx6XvE#Rz5JzY9Q9G~1xTk;l3rh4f9&H_V3!IPj$WzsLno+ftCP$UBiYd<i7m>}k}7
z14<GsIYsQa&lxKrY=U(Pa5-yi%2b}+n;WL9zfDq9NuxTG{-+Qtxa)(yg{=!XFF@*c
z=a60vxxk7VI;@Iilm`Vu=F`B2JBhAF7N28AUit9VCIiT0>?zfWNbhEx+dqB^Z!`99
zyiLr4E?^6UC)I%E{-MFBZc)&^Rd%8Q+nE!^5xJq>UvI=Uzw19JBmzj9zo4f9GS;3_
zSqA=@d`HDY!+P@DmCq|oHPJy3hi?K+Ib4~$31sORA2iZU`B!t#stF;e(-}%5K&Q~V
z^NgvtO}sG^KgSvaZ#O)77pOwJPJFan$MNIz*1OFmQ&We);V^hD6Am^@I!wSV3wU@^
z*%V*s5Ov5nGTeU}9RS8K3x9E<3{%khL9P?#zDmi61@o;vA#u2xDf-1T1JP{KM$LLb
zR$#BW;}@5f1Rkc6R5Gw~J_NmFgrruZ;iI~3_SZdNV|tXcCebG2H>KEfY-*njH4xVq
zp;3M%#vK7?!BGBnL1>I<KFJmCR-x}es%ip4Zp6sh6%gxo$(fAo)}`TSVHrInV0NJ%
zIH@o__o<o)!DI=A23W^GA^8Cl;uM7ZHbMj3(?-Y(GQNWLY@`Bog}^;M?&}MTyCm?K
zJpi^A<H53ljYoGs!~BsVz!B66ZK>eVHE#NsfrSJQZ`dl{a_lh<2uSLkg3F_^XWSyF
zHdAEsv`0kMZh1N%WpEd><RVcU5o$6Fsw_L^3tABs#}eT>-+F2VEVT5S3c_}2n?G(S
zc1-Z3@Mzgl+qx|i3g|M(?h1fs%mECwmHIcRU3%EK!-1C<2%(LjCX?7(vd`28PvYNa
z%GKn+L`<Q>SoUE7%I+3A;J=xr6-9XSucC_DItcPdI;6?I9<h06%(>^jul$-FpA-cz
zv!EccuWoi3hsA@NxdN>fA2^;ByHunbc3UDu^g%qtD!>Au5r%+;@BuS|MH9t;>LTmN
zh1-Bya%SAgn9x~U>wfN2y#WOrakM|NhM8mKkSAOhxFSg^)!3GaxIT*4(}LzhH{fFU
z#Ekdal82VM_Nx1d9VkZAXx?n;dFC3iReIr9#aqv?X#<ATvFJh+ELjQSr`zMk+-pXz
z`+yxGc6&(zD6eQ?vUS;UcMvb~9I_G<W9OjOW`iu9*BEBo*kQYgMgW_y*wvpk`11~-
zi^LN^^V7Ehc})89mI|}gS}-d47NYf$2g1}bmdjb+$(*xH*k|E86(MM3LynJ#KQ%Oa
zjQ`CAV7F%}+}qUT#N1aco8UYv2;SIiISt@<&nw;nfH~{36P*{S3(A2X-aTUq+<`i_
zC$~Mf5RE%cZ7Pk@2i&v){9~F3q>K=<MmD=vKPe=)*R#D|y*0s(O!BTyxb~Zjas+rY
zr-aK6@zilSTwhOZn#-Doi*nQ1S6)<j7ycly#XMk1OWY`YBdig16&!ocYICI7z;wl{
zFQh7LP8zjtjobWf;9d>i{voC~8T}f#Uf>Vb#3z+Xp(<yb${UGE4;Q3_wFZo*_&4P*
z*>v@mf~hRpQU)s0T}Xxhk81ha@Cq{Zx5xW$m_dfB0q!j?kjgJ8O2{M&sG|hN+RJOM
zD;hGOp-!5T0Q$iad@sUPK5`>0pm7vPQYj>{=4Sno;XBSWJ*M4=9)*8{BT6<V$E3}3
zFpv1_=kFON<IkOXceW>Nr=D&;TV0c*WRrIt{RGh8K{+KtD!n$W8>7qz^;h~Yv`K++
zMuAXD5c<J2sl5r1^0E7LXM4LA;cq?H28h2tHEN%xjfI$&!lx*sx#Y<eQ+AB*@Y2jp
zK7d*MIQ&R?(wuyP*i3v_LsSRqGnvHBD?_VeF<hVj6A&%~D{R-&1d1nj7@B5L@7P{V
z7%`S6jV~z^s5DK1*9GL9ruGj**;-QfQ=8f@tl-E7uU?CHua|yKwDb01Rlfs|r_=97
zy;8-oN(A<hdB|u?3v#yyn{=P+;~Hbp_OQ64fMzq1zb-&mRPNJSyvxmu8c`JxH({Rw
zwBemsVQfeDW~tMlMqDw}#tSmyXQr&a9f3pti-okRI1&dVDDn@Lr(NoEYHO9|h;XH>
zRONTlVgTFXyA?ox@f8wZ;wpMD>n8II_Fi4g-qew9-CDfK?B5!BB!l+wjm-=WBrN<b
z^nQ2(T#_m?g~+czM35i(*nXOKvpk;RnNn@Zu=w1ev(%%1)CRtF9<Xttk$J&c?IpS(
zlbFW}2()2Cg42uc@nt%jlB{zVRnZR^$5ok4yRne%&rb7AbY@`a8LnB#t%beGVNbgc
zO!FDK`3h3*_Dr6r$zD57*#=@ktiO3lmMwpisThF#S#3{;9Zfik_)eTREaJbAk)yYm
z=y!YaNDzy=j4~MU;J(7Ua*3?eBIABS8z8Rn_Pw2KCF29DYV2Ufk_+WkqXG@-33zrx
z4R<Kab`?onws_z47=RwL2MEG>a33{``|wZmL+&LM1<#&%(P(8Y<l!2+n)$UL-6c<i
zV*mar+Q)jV3amr*2GZN%RKIcrhS+kynYT3Ll?vt@(}Q$5v3xeO@>`GcZNWeGn}W5h
zQ?m+2qO2j7A1uY<UdtSa4F7CW;C<mS<MXXe3nr7HSplq_g0gQvYVXVY1JZnPZY9pg
zaxt1QKhoaiiQq)<Wookm#!doT1X=UcqtL%FT9_z}y}?CZmQ0hL^o4Q!>jwnO$GtRi
z=!Ni~f5sgTnPfBygzSq)ko+7uXX<O4^uY6p1SN(8%)OgkZ>JDLebEK8>}=Rfsg4px
z@XUiOp4w7*Gy2&<!qZNtPq1<8m7l^=Sk-olu%tuxA;pu*5f?8y1oK$L=r#aCBjvr0
zBYQ$&`YBY-KtUX?P?DDz`?T6fls<vgPelF#l*A!X($Y#TG5xm3VZRNtM0*GWgOGt!
zbCAPr{5h}>P5#p}?K?YFa+$>%f>$65>uziq@#w(rKF*mtw0gN$Kw`|MN9Z0d$7lzl
z!=1~Gx0tT;y!H~mBF5TgC4j750Ko!+v%~afa-$y#F`cauRGTtB*2_X;H+d66QhSY+
z$B}deQyZnuY~Am+RoS#+N-36UjasZfpXlm{1<%5$<FPG-RDl9zFNnWHpo~~ykjG|2
zLMVuk)2q>0{^+LG)kJqGqa|>+ZY6-Df*0@Keid+=CPpJ%BiJ5wM9ok12~W=%u!ZCO
z1-a)$J20j`-I3IHaZj%?$=-YVMjdLNi@?gna8|5J_-SCk9A->wKl1@;hQu8RA7ODL
zD8@uf<Zp}I*!eVa5M;cmH7$r)zkrlQuzUY!ChjNk8?ikDeb^cwSGcLu(I<!C%a;Qb
z)jnyMvQ>lyjMI%^J;Wu}1i#xr6W5Y`vYV9EaE4MO7dj#>1dV`D;uJ7%K67q-bgwq*
zC8UcEO~(T(M&`Py<pdfbPcq-SgD#gPQ3nPiJMl~Go^#{)yvxu}7{1zwb-fQg6$CVk
zcC0`p)Om3L=3gwPYjIs;+G!P=-<St4%G|Hg<Kc$y2hTx1;Z(uMN3)%q`AGTXqx;FH
ziu&ZO=rT4V!789k$J{}TUWq@)ZCAck71+-<+(AGAq>=Lq0U}%$OIkeL7M1(-7%ZmD
z<>G@QpUOsOa-zMYbM@dvU~MPoHgdk8Xd0P>?(sEfi3gCJojSEnSQ1u*Rj}tFPq(L;
zey$~w<xE>oTu2IpWKP5_XfudJXMpM0DWnJG8r;!v<$PqPNWFL+W=LO`D_jMK7sV0L
zKfYWJ;YXzlWL?9Fx(2SSU`-Ujp&(h|Ubvrd9v=86b#fS@(@udQ(5lI035L6dF4QOw
z@p*2u<HuS9Rr^vgOR*^aavR#c73c1w^(qQ})IjH^0z{HNGVLN=3*l~aKoH0SY8V<3
zvuAfjeLh;c1~5^G-A}Y@ER@9-wG$W0!;O79FHjFC&){1w4o66xc`iJvA`aYxpb-WP
zniSbxovHv-DeG<p>g<b{&!N{useU15`}(XRU1E?U`2C*$2uW{dLm4d_Cc)He7+w#-
zy3Ff*^^VqfGDRi`tU0Z9mGpyP-_-3^zbDLjpzHa3uclly6lSHwQOn2w<q%g~lNQ~j
zR$b`iJiuq5>qyz%8%Vj!VUbcHj%!0aSEClF`IJDz6QFo6A?;^#=tlR!wI)yULuf%D
zYJ3ee09fJtW-MHs<7-6S0qAL$E5(okK^4DNpL$?Em<D4VL=U)Bdv_H8)CL$!^&S2J
zxI{+Hd7a!N_kw*Pz`7oG1NpB<pVkd!>B=>kWT%)+BFA8S&{k2+O7MopK?TBq+`?tK
zb@-C+g%a<{VD`fnmeayZkWs=RRr-p&vz#))kGGxfd%9PPeYh#o{+?s{(KYiME}2RP
zTT8+1A2|<z+S1_3S~~<qba<IR9~U0LB@3*ss=B4O!90urbYhWQ8MEo{Mos(87S&5E
zEMJMG_RhQB)=(O1^%{B}Y!9<P6IBM;g|L`SaQ?s<LR5&id@W^k3Idoq#*=r%R0y8v
z%ZS+N9cX78ol2{IFce5w4u`q=B_-2&+`T)GE|(@r4_0Cb?oOf@ug2pK58Wk~H&iJ-
zlUV5Sm;e1uX14k$(Uv7%t0|8#$QfcPH(vNo6#yKchE01~eyA_t<VFHJBF3cjDMNCu
z9?#+&{km#hdHpj(_9PRXAEG2kG7lQT<+4iawXU;f`vq!{n2)Bj$z9)Y<j`>o;sETI
zw?U)`%-W&8211fL9TNHRn)`9lz5~T5WEdiiqc^=e_V0vJ5~|RTa6m&`B9#vu8T%)b
z-><T#bzgG|j=`CY)WV_7e*1YCQHH-TrS${LD9LXNyvy{Jr2L^kHH)?yG<9P*t@soN
z*UmC`S8M_T6KpGf+XDZZa;JKXq!9u@62IqB2j+qO@#ZgjpYboI{>IEbR48CPgT%I)
zw+@}RkFp|s)=Otc6wkGnm>A#C>YV%pa<@1lBiSgIYOz=x2`*k#(YZa}dK(iINJ1BL
zow_3c`ZTqPFiAu?IFQqP^7%3;StGXSp$hwef+(|I%T$PHr$Py28Wj_Un$*U8>SPSm
zJcckgLZawVa~1E%c8&2Lw4nJ12vV_{;wq;8Gh*&d^=88<Z@5%n^X!p;Dab~}Gb?G<
zqd)GFUoh1CLnpSmpJ|C^48nQZ`9;v@>#=JWvWlxXHxuok_%=>$w9T!agkq}x18U#i
zxlF;iZi$$)dzF=hQ&3G=o>MlCHPkG(peA#JLVj;W%U{xu!O`xm+G7pGTAD3>eTV^S
zEBXgA${{`U6x*S#zbH%7osVn%9S-KK9B%(2>q4+`p2IG602%(R0tev1@fU*)#_fhn
zH!8iuIhT@ELwzT>_U8sd#Vzt^OG@5(=AoA?=37EBwflh*|K6ipZbt94DpYWB-G?-y
z={vg{O<~wac=PDBx$YgBYJ-VB^Z9-%bDfbQ9Zn3fSE>dc(eichAl;v~F6Xad1_Bw3
z{OgvY&R1oK6n7I%|4&X$<!{uY;Y?lglQw9EB~=ns2l)?NOw+!XbH53^V%_CnGt`$8
zQt`(ND!3#=0CV3=Kv7Zg(Nt?;#%F<xVTrV|Z&fic2~xd@q(pa;u;<aWP48!_dX7k4
zIc_R&bP0&P4UgQ8_;$WZ=xsate>!vG7|HLw#{}J-TgJ%<twB}Ds;?uvMf9*8j@MZG
zdB8y*t!tJ_BTC~W2|&3{7lQ?k6~0mZina!fwGtAW5~i~mN56fMU|6QYj)~VerU;mY
z!E;n|GdFy6rs91Lr>2P1RRM8-F-rxssdK|KEN6ZarS}I6(orWOap3xyRn-pH$Y6E=
zG#1l=iRxzFfQ5|_IOO)0L^h8@*t~50NU7v?(3Na0j+g80aIan}&0ns+dy#nDHmBgT
z*OdR@(}2Ku!Nb9y>w2xzC^_os6*Q)9`!6mIF@!31DwBXb%jYs*e;-S53vfG^tvp@&
zRv%Btm6o=MvZZAeZufnTFhB51k_b+mR21%iVdwf8U(MKD3OHs6@XNhH*q0fG7N~Ru
z=m2oBA#t&)R-0|>4Rs+s+?WV4$26i*vs*{`jX<j8=aH5}8rw&phKM0XgAQ>xDy#J9
zqpHn}Kpac`?A*cbReCil2EB~7pT&M4Bak%d@Iu8FS*7>3p1J5IosO3P)h<^z-jj6L
zt#xlyey2(Li!6hx!r~*!_%f51YkkG7je=2(CJ%<J>{1=Vk*3a^wCG}gT1&=5I0NeG
z87XY_uHMIy%+g<to;NEI^M<>jIwXbm{{Au(_{~jK)nb7(wqlUfZ7W}qCwE-CBGRBI
zO_!Br5$d%vG`tpTrFzSm@WW{4UcdJ6nH7oVdB@Ir-V&DBeO5n*NJJGkaBmS8v77ZO
zVqR>;m$cU&6nm7)+BZPQIY^H9;8X|6`s&+jZZ_D{K4NuiX@d1TQ=(!Q^ajJAe?R<b
zQeYD+wv>fq@7cma;zh26SXe?jI6_AFGd>xvU;c~Y1lX@CY5vsJRi!Lvryl;eSQrB_
z=^Va)sS2Ujq4Sw59Tu>Br780^?nIF?GZ&^!YKKnW>AijH0&}lKr_A_3J8S9s6la^I
zS9o<cd)t$nApQ!dpQ&004cFeDLe=w%b=hfVc5pFGg>QVT^lj!p`m;ZmsUR318^R@F
zV7qU@G_j-!sxO@~mL~v+5H)pE(t&+vKI`W8vSC^S?)Q6<>y-@SmxMTDEkyb}9q7&L
zCWkSM9C1V~r+~rAB>%FI8NVMx^q_m@CWWM=$tv`YXKEJC$m$zNlg`dOZi~2cymEzj
zZpJ#13AbG8w3tO@%~)&Gj2Phut+vUuKd42UefnXuDV_|iB~N7CI%$g)jay2y{#k_&
zas=k}eNCi{wksIKji4r4%=`EP;?oii=q(-cG#&)zKjbP(hjIy4{zOkmMGl+v_WRbF
z1#qMB%$+1_!uK)S#S*>-H8AsEI^$z@=*b=Uzup2=KA&)(a`HG~$0fzgnFUoZ1U?^K
zSnfFYY%rs1y0z*^<b24n{r0UqAE5MH)VzjnnD;BzGKESr*srTRBI!$+IHpbV!xK(~
z6i`KR)qE-R*v?_Ig2Td8gS{3av@T&2*UjJi&Np6(#~0}%r?&mJsQ>W~G+iLhqQory
z?PK#)jrXe12*VFV>iqD@BDjGp(Y^yRqi7OH-2Ok>I$UKC)d``Q%z97Pm%Vl%Fz~Zz
zNw5!nZBFGtp^A#dC=>?&7?($RpA1T9)<)g_7b!$|iNp#sfBj;Xw55>fj^sLAv4t8-
z0279Ux;97#j)6xwD4kLKv^_MuREJJJ1$f*LdB(`K^W7YuO&X6>Xwq2#ZOi^4^wK_3
zdPV5Z7T>|y<z0ybq0=QR)Y){gI%K<A@9%>O>|B|&w*k=&6n|9T0YM~0t6Dj*>ugDb
zvs}5JYeJoTJV23eAmb$Wy57`K3ebrZgLV;;_<pOvE!dWZA9Y5$R0mm6`ZgzJX;tdv
z-#pmRo<j<-17CFX@91bZfrCf*=-fv3uWP<MDq4@Q&zLhZOr-bfk#!jnS~w|)2@<T}
z4iQj07<qI3D}EHVR{ra_FH@8O>Byn@L2G3NH!<g?skvhud^=HWZ}WaNe!dtv-dOMh
zn`@;NTccKJ2cQ%E$les_I9qgH@pSPBk9!<dScsP^QVmc4vUru?Iu1z7ByS(Hvw8(0
zFD|OVXaRLK64IzDm}Ygt=uM5@=!U(wc!aR~<KbN7rG^@4b5EOj;C7HmSGuirYsl_e
zok3Fvf+Vv1*w`jS|5del-_RorG=<5pH29xVcKqa8nS($&iv|;p<<(QU(Qw|2OG?h>
z_Ut1W^=}vP<j0U%_FULJw)X(!f2fuq+T1QzDwQBvz3Q}|kPqd1;f8f|SF271Bfw9>
z_E1U1ecW5!mN{z~j76-vX<P|RzvBz57}P@STHf9D*iOHfJ!!`spop#uHS(<lNuxGz
zKSsa=g(C<qPTTj2w+;epC%eE1qEUNM)jB=tj@1FfaOLlhohr}mY#3UX8J>=BD*l<E
zzb1)ug>p-AST9?p;QM(2#mm(OQMYQEKEu_<Glhbln;5>jK-WVdk)P}Lh6Bl<8);=u
z#$#llcnuu)=|>XVKj(HOsiB;XX}Pq*QLrcHG4-_jQo&$!jR)E}P;u<7>v-I87shA@
z8bJvn@4)D&taLti`hBmSHqRq8EL5JtSOa(tDi$`;@!o=W7Tizi`)TVJG#!^`h@+or
z#Pqh=eOWY?2|Dzw=uu=`MMX^r2R$@pq!d@fmB_lf3`Na!1A9MxSf4iV0?Gs@yv*-P
z`1fG>_7)xtH;)Cp5dm(G7rf4CFy{)O03;amtGgUT$AQ3tFOA$STQ7(S*ztpF?J~PO
z&D9Nc4ubp<wK#E~@b*d})y_meR?{E+%Rb@w!I<QnB7Ls~yf{si@w4Jg<q;;h<&k|_
zpCYLx^p4fQ;oXhd1tQ4APq{eiV1LIA3W^=;GE|m9cv=ZHFCl7?O#cB3m;~6FyJo>J
z@MiqUHc)#>FJJYjQv3E-7PbHL6f|!fUCG8+1F!UpNFyW1meA#O#PGim3h7}+8YAL{
z*wUh1u$HOx=|_q<QbbSU?^df#vj~~<F$b0MWw@!QBuIe!oi%_>7aS^YdbDK*MJ;--
z$rG*eK#;Jj>UKNL<Dtt-e)Xt&?XBSg;xU6ucfpzJw@7D8aT^h|@N9we5deS%<yO*M
zgAfZpL#^pIkuU4LuKRd#s-<w$0sRmHp56<0km@zCj}vKm3*Ju%#oFW5>fVZJcTn@k
zm?)&FnKkqsp9xwGjrcJ0n^HI&l=AI#j+t7%3!&z3ffw8|_rQk+FwwvHd)xNvy=(=x
z3@*w!<&z_^v6^tIDzQ~vC&78A9os=IWJz*?KkAI^a+TeM$;eb6>N!XH+81_TI_{0P
zsEMVc9c@sevS-wlrheuSH@yyct&d(D(~Ath58zDLo{HqIYlreP4)NmkS!|{y>0Vl9
zH+3ItGY14QAMYmlpckU@4u9N*_|h|Z*lfP*yxujO0&RYnOq<%fIoA=-NwhORq<1KQ
zFrU2gA@nr(f#fW80;9yQ(8fk18=dq^W?>0HP9$)&@iEWH7Ec9fL@kS2(gjbTrK!r9
z#~|sky~O@*|9W6@$cC5qoh;!O=>RM7FF9{uEwQ~@$CKI*hEnrqdEhCT?B;2+L~j*=
z(L3pt*{%txd6-%ws|_ikrAQuAewC<*jK<|a@oP8QpTd5?PNon<(8v}bySB8V&+BAX
z;E3*;HIzw*kQYa<<vZYMny?PcNJz%9Lk<eJsc2jlA_jr9FXj((?{3SxzXo7f4N03~
zd4Rf2$}bae8?~GgoLq>yUIyYCpU+~1@l<D*^d=6+-Bia;Pp9jh+B8(NQLB2&vN}pe
zV}g2b!SgvipOrbtzljBWU7o|+y%O1s^9G+;^05|rwa?Mc?D$#Os?O)lUDQr+ReHZB
z{hfXntm$nn0r4vf1h=L&i`g7&1nMJ;jYy<&A3Pauhd*#uQ8U{I6Qzc~Ai<VL*(@{a
zr-}xA{}GwA)FfUqn4q@RSV4`T^>_Az)-|JXLzL}|Wc?|1!E6-n$5B-^cDCZ!t*z80
zW3y08Lp6`QpF*vSm4Z~f_;*57IVmm0XpI8%Fh==niX<_cOJNd^$x)(-jl$w5xjzn5
zil~Tq58sHs;u1r@h0{0j=Y)V7sEIf!9hDHggH-MkDuhR`?mCPpQq)IQE~jHNngXLg
zs75(Ay=eK00k4s%^W)2SR%F^l5TH3Opj3%&3HbUQXM3%y&b?kCV=ThrS+!lpVNVXC
z2S%ka0z|5>H`(@aYDx+^L)Xq8PwN0b5#z1vjs+lWQ#wQ$1<=AAn=YSLB{;^ey3$8B
zk<W9Wh^BH2%1BZ)7XizCFmxZ@NSEJjY!(`vx1DL3L)sG1#KqV;1ddtBI6}l&n;PM%
z5m0v~!m=U)J5n7KerKYufd;;u`VwxE<H1RREzgR0TF?yej7UeP1HI@0Uu(A_v;`Zs
zev!k|xg~0ocDz|$h;%qzcm1w7^q>Ql=qfo5r~c1URwGZrDfhQiR^d+&EFwsCQaTfB
zT8|;o#yI4}voET<{z=&;g0jXPg8L;F>sZ<P)Lf0~a_VT8?=nLZP7Nc_ajt$A)yJ7g
zZR0wh2UxHEb)90GF5m_|uoku&D^RZFC8C8}cj_$&Cq+u6(BZ`D7LaAn<2*3GPL;&Q
zvsu)VA0k}q2L<Qlt+fgj?Ni^DU`~uu)S(VjZId!Rbn_7B6|%*UI>*sZM2z4GH`(EX
z`f>Arw=eoJQ2Rn`-L%z5ttM}UjK=#X#-HzL9AmTYkaB{VE=`W$VNiuek=Y~0V0HTG
zOch^tFft1+M?Nf5Xdb1j4LZ53n2LM+<wHaE)PA&D^&8`{!XjOc2T<%(0<mPc2k{(~
zRqcen;(IojPympnktMInutfjlT3p6!D0a^j^@dYH^xpyTathkDTaO!_$<_a&lZH9_
zvyeQyLKZO9bS?nU!h2hYHss{t+JTn}Ot^2JkpPB-I3{zP<?jk-B=i91p>>yj#-p5%
zN6OS(re-1hXq(`3q#Z^WVS!P<2M<;&_(%ORVPPb8#Z0}Wv<7j{pM|#TVGyPLFL+Ys
zs-oh>5^8BFEuAYtMdfza3te`4nR?sC)<Lmz$oP=;?f>YnJ)d<M>DTBBBKYA2nHz<+
z2sn<zbS*{HE;UHg*D8T}Ff4$m_TRkK&sU*XeA?M;8hM)cd|pWbd|P2v5aEhe25Iy^
z#S0P#jQS1Iov*;HxC1C~n`BgwDaAx1H=)D)P3X@0g{(!kh{xrxIg3j%8*7}VRY3rG
zLdN>Vc(#Ccq~vEOfWQ<=I<VGSiKD;o<<n{k%he82uTG|nP5a5*)SMm0l3^@7j<#$G
z?!VG>hzpFlcOLG-v+Ht{2Y)A^(E5g*qY3P+rDGm%V<-Qy5@DQzPqF-*LtD^(%<MbE
z*Hi>C!mnxwk%b=;iCX8RxYkV>nvX&0aW%S~S%GOJ05L$$zczm7KqQ|Hc9^4r%}E5G
zk4Fb;MbYc!ZBeC1jH3k@BMwYBFnp;c16*ne<Z*BxH@HIfJ1P+h^@ySA50=RDZ~o&o
zf(Nnmm#2sS)`N|^9?N(P;+>l6L(p_Wr56mh5+irxeJVNh$Z3y6wZ_BMRRvKQFN`kT
zeEz<Wj&^qVE4Aqf^U<&RECT|+slnAWj?oW2Q+Mxlw#FgIqkV~$APkDRb4RP7ARIqw
z)EFz#2gW-g`^|GWT8F3tU{=`hsX~O%I_*9_bH!<ptFi4JUCg>h%JQd=8Nnq8jP`N|
zTKqND%YYxeCCo<L?J?L)QT0{9NAko5pT>6+ZdP?XaZmU$C>F{1IX}YoaT45jWL)aE
z+Y+y(_GS~J{&Xy!z~V)Dy#f7AX%Z9wSPAy8fk12W!dGGc84?8r!8Z@qaS_^b919JO
zIRk0YsGfm#eLYA_`dfk#&v$b-StQw-67mRfHY*8iCE*oXkaZz8Ob%6JiB3bYBYMg@
z&0I=|oKwVoLf|4cxnQ{N*zHNlTD)VAQqgVf+DWAy0WeWi@gcY&*u>b!SYnOX@IEBo
z<2Nq`rxC)h%clY*?!~S?Lh~&#7M74r@`U)}oOMzf4`uY|(|bp?n`3<to)w3!<A4M9
za})oKF0USDK~9T0dte}kzlt;eu=-;pehrD!jP#KBaq*Z{AJ=FdR4=tfT6FfFk2;X;
zCFvQK?`44Ish2*(jfayLTw;?noglknK0S5-O5$*%h79)KcPkKoIkal8C+cd-V|wEN
z-K}@h{eOl%x>feu)3;8l`YMc8E=FJ*fRTpU5g7}bH`gI_d3w}8Jcxl9)pIdsZHa?}
z1u>-!6(mvHwhVe2$$G?bS^Er)bHQuta4Q64z%d1U9@n5*@59|2EOYdkVyG3h9Xa|o
zTG9200~uzaYNBUouXH5AuM0Lt!(GCFMYAF#?vXc6a`^2IHZ;&Bmg*PP58A7E4Jgn7
zL+6l8Fy`b}nD*$gIHu$*j-6@@<hF-Nt%rhDSQcxcBr&rIZy}#F)Gr1Wm7i@fiUPAd
zI1yQXm8|3Xo1h<Iuov+)-23*bZq@DHTJ8}*D5M%dlmBQ=bBl#DySTq^CZ+=gN|YJ>
zLf}aC!1I=rPP<BIjna42W9ge-7*_MxTKJ4N&Azop_C0YCT>P3j?~}`^;^n(fTLrQ@
z;`kGb*uFRO%_BZ5Sl<x=8hiAu__zWxJIf#Xp|P+u<^mI>A#2rj4_usbhVYr*%L7IJ
zk4x>`;t*Atqf~)<Bn^`>kV}<pTr)pJCBN(K*FesFH>J2s^;adexxS6NU8_(l|3jQq
zU8Ye3d#K{c?hQV~p<249Xb^M4z{|d43ZrtaA(#W&oo&IO;(3-VYHg@j1vVtHGbSB?
z*WWI{GTmhWa${5sj)K|p&97p46T%~1?xX$ZkL9DlkBs2z9fLhIUo}0m7pN&Uk*Rag
zuoV7d*bbMnXDHJ7o3qiC*$E=!;OEu08nQ9&O-EP+DYOKDd65pCIzqSR=TnM#QvcqD
zmY-Db>xYrIZ(5t(&iRJ4uSuRajoBa*e<4rgJUp!3574IVC6KQ_6Jdru?|5qAAPA8N
z@JDZlzDo3UoRh!i?dFtvsNms?F!5ei=zAZ4w;gTFw(j&w!l^kcv~9DRoK$9zsZFLH
z%Q2g4Pq(VgI8#zglBzC+kOQK<dTT972UF3wn=|8{97~8uGK~+hP)c+nAhAY{#qS3{
z2#NI2lA+Z`uc<$x5bU$!UkfNJOf7#3$RZF(ZYWg}rLu4PUxVEGZvM|tPtPz!qA!LZ
z_F6ha`?o!E6DA`+k#ab|zeEZ{SUldMt6-1E;F0u`_fjyebLvU8BI{r&rlZmu_V@)M
zA=w^Ms7Ni*fK*Ydf^m7Zso8j*JGfM44xIryj~Vp@lG(5hXw=N)2DLo56S9)U-h;m%
z?R`-s@!FWyrxbXlR<xq~z1Tz~#HWMnJsy|F4}|sc*_iF3P8%$JNz)Fz3wcKbNEq1v
zDOO5uG{Lq<-jA)|Kg~J{Qid0@Pc@J6!``#4!!Ync6zKj!4S4MXLZ9i~?l$Ez{HiFs
z)i~w_Y`q{1x#kN<+xV!2zBmiqMQ%<i@wa=+o9X(V0tV14!$cPZw^dHzs)rczaZ3RW
z&;vS9Ndv?Aq5BpwLTu{`quTyCMGYy!#-tUiq2b$=d77t7bZ7}+2N<)k&ToY$K!i5e
zeQeL%&b3oc(8@C)QxsDIaH$Y#X1^H=PX$%4TXu78znulKu~igiL1dV&f$f~I^G-Yo
zm(LeJIegv{-j0wA{dvS`ps0y9+Q2;|WD<gv`0#b3HD1eRNMu&wfOy6QmYZd-9>qh!
zWVl_!Hf*n)SVJ938AJt;Ah6&Go_Y<l{W1HcKTLLDcBlQ1N4ALDAo~K>Szk;SFiP<v
zEg`8%X3+YfsR(s@8bh#@&y1izl5=kF6zx_aWPk9_tO=tTH{VI3@rrx4GXc#ZixX2q
z%cKpFzHzwZQ!YgQzQP;c9&9i;jYkW$x^{TpjD2$|=rRl{(3=8dV{dlAK3<+o0jK)<
zs*#EzIBkN}TwiKh1b`ezmxR><x@H?YyXpco$2q@tMH13CSXsWHgb7n-QzI~-`xhj0
z^bC^}iP?2Jg<qGF7A^n$YI|aj({Z`|bhf4<)*J)Tj>|iS)B_IN7GIt;V7>)1rcSxz
zDAq9QnDgy2HeF=@&4Pp*8x(dq>!$w&qH4X*r4l7SDgK>M>NK$97W7@ryPk203w(%i
z#jW~l6dl$}_gGq-gX+=Z3x$J(rulBEo11ObrPMhgxRwgwPC20mL=7ti!CWyCN89|u
z5S$w->Hf={FQS=TFb-YX%}9|U?D5nQerFaL_X-gpMZ+3|?iTfn4?f?MUMmCgfSFnF
zJhHzx_N!)Uj!p;i8Trx15LgYM-t~>Nr-E!H0L*J9II74P7JQH<QU&sXYLtd5=zEGQ
zDXX9W>5|gI%EA|oz;1keJuobZ_TdJeIp6QkpshFCqN&^8kJxd>clwR<u>X(r_I_!6
z`K-biO%te6h$|5*=cVPTug{UZa>w7=d~4Nl;A%u-CBRtSUsm-R!Dd5w4%-Q2s3((=
zaPQzI*^40YgTd_C-DH=h?ldokE>r`Hx4Sna;1<H<hg|elaM+kBtTR%fmf>9Xz?iv}
z{Fu^pH81!c3*4*A?SXC(GV<3;bApSPhJO$f=X(YyxG|WIF3@AJHRTxZi?O*#te-ro
z6ry5gyn-<vhZ$SFdbHS@cs}2Hidh9u94@Fpn{ed&zK)X>%q4)Ftgedr9k=7NBMglb
zEtn}%>hFgf&nhx$*kkNTYC{rKQyIJd^z9;PBxZxl0iirgwlZ?omNSi?f^_955*YFZ
zuvjIe2S8MQAEogKk>?=eUqCa?)rbz1U$m!jxF}(^hEP3!o*_j2A6C`&h_nsTQZPIZ
z7Bz^;+}Q}D!}ZF{)tW!9i(dWn>_;-si4bO5he`%k4+$v=T#Gy{^)AUkQg(a3Nvx-(
zEfAf91e{hIU5f{z&sW%r*Pr2^XR2HEeU7J+S;~>HHQQq8vPoVR*lGxpONpV<WvCqM
zM(*vvtP>+-ljukM<S*DR{tKtUN5^DIJWS1cl1}yw!T6FcS2Xy>W6{{P78bCWAM(w$
zV~=JCSfdNIuURXp1|6L%q)Ncq1L{MkK#q^NJaqn5EG}6-FgsgN1ipH{GjS&6qb)Dp
zT`F&K>Jcn=lfa!F{EN9(qV=w@&VKgGwnu>Cr2YL^Qh#6^dfzDO1S1DhafhYsFYg3S
z|8bb!TCrm+A7EmO-=y$F=DtCYisNx#Dk9Z;8-$oAyhfXYy(h$t=9C#go4B%mk9|4V
z%G+K#wPF3jR<cAakNo;Fo2L7xLoBqJ535=^;_F=2@5A<mMgl=J=vRZT6EX-&+0$6v
zyn&)<<G5HIK4q=35&+5)kN2#Jgnbiz2)S{UEBi`b_NcNrPX;^n!c_+F8`w+Z)Y_5&
zUz84ADPl>1>{Y$4pF)E+&keU=F};-jpUVhQ(+~y}Q!*;*s=H5=t3&wGMWd_cxF+Sq
znSeG$>SG(qt>qvGSo!$RezjzXourk5fc8wwes@-YPt2owhQD0$o`A%|^&}(uiBP~R
zN%Z4nxb4u!FNF@h5<s!()yT(&SMRMU1fOM5YCxJS`&2|j`=P-lFvqS9FjzDSCO}W8
zB_1HcUM6(-6aA)B#!8Qq7+}}@)rEXDXegzp)oCU7!pI)ZArcT|H2v(2jYU-32sz*{
zJW=$o`1&Ja(!3YF(_;uZ*p16WDllrhbY3tzJiX~(jX@6a>E0b)TM2d3%TP_edw*tr
z!r^NwU19A{z;}M19sQiA5@Qe$Ts$!Xhgxt^DcRZmVP3Nk#dsSPv3Z(%|MIx5h0_#k
z6cGvBjh!;WWG`Rry&-`Y>>E;2dB<cG8A+nx_Itz-KUXU9@1;m!B(c>Y^|&xAv~?hR
zu06wrn4k`Y(1Mw9*o&NoCS#cL8-W$EsIRXTJ_&8OKxK0y4&71IGgLyQWFrzA6PE_k
z#>7QJAtSrWRQ1mIKlY`xy(Dsw+)GbJFG&QO+xl;yRWH~Mi%XhitSp!6=@bc?VV6!?
zms^hD;$Z8qLN6aQ`DZX3ZrFjo`);xKS5W*<P~A-k3~)-GhXnp?IBlQ-T>;V)ns}LS
zq0e$d_FS2nsq23ABBIkA`#Yczzr}s>Mb#k17aJ%7imdIX)9SI|g5LpWS?S9D&;+nu
zhb}xqbS&F9+4$G|Q(w^foYl+l?ioC71q_89m?<MvY_1GDZ$H-oCu8`vRCH+N4ikXJ
zm^(U5`qY85{Oj)h*wlFkM$rY_ygFi*nrRm>hj~GBIN4Hr5(5-Yqg)!`9}vdGYe3Ph
zqc=I8Cyc|Yw{INe_^MaBzcUJn_V;Z>)d*^;HX>tgI<R0cP<5oTtCK?qedo-&#%NEM
zf)jTIE?tYvuYJW&hpADOv~cn!Jft*mWK#3+^&5tj8z+3RXR?Bvf&CnZ4~=9rR4i5U
zx)Ks3)6LH_F*Sg4QvBDFN_v6_Rn0=`@KWIfAQ!0@wd6?TU3OF)Mm^)(s?t+%9h+#3
zua7wtqPvcM{vs#`AB$}8N`_zp^Zs>yEbr?NnG<{be@t^Z`~MowhQR;*Wl)&Y4&&O#
zc)N(+8z}vj)s3>)hFxUZcq|lSzf_+=QiRs+pFv_VxOq3$7dIEhP)&)x)lQQ3Z|L8v
zEx=vzd3wJvox#sFD-*NKr|~=O5r^6+yaFYjpb_^JO2y0(q2e+@ByT$1nfva`Ipgtz
zgSgTMeFEE$Vt!716r&R`5DA>LJ!=xNWf#|#f#2Y%to1EK>4QbRQ#Ybp@h*jesB7Q8
zoloc$N(K@|`=HHnO$x@DbUc3AZ8my>8VkW>76Ur_#ts7%9OEv#?Tz)@bS~XB{7XQ@
z$0?AIbNt2(7m517!*H3-nL))l4pepzEh{lBbv##Z_X%MRl$v_Hs-u>SGoGBGXwE8a
zr8ifVX<36I+=9vm7aT`L<Z<F~g-Bm7`jtvN&~ifu$!=fmu_cUU5_nTgjQ*q1lIB$t
zxAvxTW9cN&M7w1FnBS;%nKi#8wPJp}z6si$74Nb3(SVtNIL^R@8yqd8>1~+qi^%F!
zIWCDBIda!o9u%yGlcMKCa&6L}BQgO`$Pc;KpMt%R!mnNH46r+??MYemZuM+ouh}RQ
zNz>X%wfOiAgs+gHKh`68>)6U1>^sXpEsBI%m@AP*U$;Te!TF?be^u6)=`+5y)VZeX
z?4twXvf0qneomOcn)P5JorCmv;XrPp-loz%n>I@SUD-q_)MF$<OZhR?vEHxV9Xe;C
zN}R|lrw@IW;pqa|Oxt?BUYV?MFN3mVUbFin!4kh?8`}%(XXNR&8Hy)IF$NF=<^CRt
zt{#cJ*sO&!WNwXyZ2xTHD?pe`BMn-yNft3X3hV2qoA6S0Yqg0mlSBGDBz}wep#|P4
zXpgX|dS>On9ozpWyc8(cVi9ujlt74=64v@JA=SYM(#d;+T9a9FF0a7u)mtf=4Qc64
zk}|+<wHjJjGJ^Ldun{Wye83y@!=6x$qs=h|faKBa1@|qPrEhIJg8D!tJ<V3btZZ7K
zFS8=%q<5p)aC~;p1O10N+_gi-rxzYkb)GNE{T)`_0;!7(bzQmR+r~J}-zV8SaY#IQ
z-Wd3naJ`G!CDGHi9X114!<)dJB>N3F(c>OKayD%4xB9uWVUHQ&bBF!w4*rI0q*=pa
zdzoyM6L!pZ%{RrjYqlpKc5~x6xR&{SDltJ_`Gj-F8D!Ob=O)ejXN#M1Gn$}!knuSL
z+6+xv-*htP@bBuEA8G##p6><M%!-o@tzxQvKkwOjX8M+&mQp5C9ajYbJHYL<i3Q~5
z(_iUn!J5P5bx(?>u2a*F>Qs=T=FjHs;93qN=!gjL7f+<ERP+BD%CuWbAR#-*g4#;Q
z?vnOhT8BtfRoe+kvXsr<tOWGDk*49EywyH#Ba4&|OKwN=5_K`&H9;3A@@)6K-%v{M
zN1Ehftm#|Xd$HvXZQPSO9uH_JzFixAUVA%zx&Bs;9yQWnI858vYhIVq%N&?JjvjKg
zYS3|e3c*~P3yd1Re>BD}slPI8AFJ`uk63=D!b{%RTJ@(xiE8J}t`A^lSeQn_&3?1x
z`vDBhI@V{}hFcK=dfyUZS-X{T?Zu^X+B@|#u4#YWb(BTV9kJMhwN@55#JiK>iurD1
z{v~;}D(yy)uwgh|{zcFfA64{rgTp2!BE35q-D`_jkY+0dK~|`ZnfUfoFdI}E{+5V-
zYwraMJ~$S15)7qDD70`6otNUa+zE-HP};VUgHrS&s)a_Q(f!;)XEasKs~yWKa)aT7
z(@^g-FCn2W90m2<_ebn4sl@*o)Yi^TKQMDpV;*EH-eV;2%R<RZ&_3~U6KJ(}AM9l$
z<Lch|=OkEGpA6snpj0f20GXkv(5TDg=r~9WslcC*fF27iFF+S=2j%Z|vvagMA0~qq
zkd1}scdy^N*Zf)-S{jl4R8lsEz}FI)5xbG2fmq|kqe<dx_)1smLRB>Pbun8;SZXA@
z_J-w|%}H*xf9kjox3o$z!v#Tirpe1I5O?Y#<B-k`J?oN%IRrscm>*&b^uuhFNa?_i
zp4EUthY$l|TPPm?{gC?mv{7mjw5#q$8X6(trWrFYCJ|<U9vlIkrEu)0Sw5Y60pZy!
zjx!~~nU9QmbCD-a|F2xYK`us2IHQMN?^~EgxN|QMd+^JnQ?I@*htzJLk7gv%AYE8V
zdtg=kRFT~kAs9`BDx5-moZt%`>^BJ@PFM96v2CD1Q09Ap`$1*JrjBG1L*seEPcW*G
zkuZJvmJ@%K+diwk3FI_<bzb_%41c#SBTJ{Acof^YStorON`~k>xf5iI4?or8zIA=4
zxk)iwW|hatII<rGWvOGdV%^*@L%$@0;Ey6oeu5PouBKP1m6U&IgRkx}v&R{lr+);l
z&42lT??14@eK*}LuG6iI$r!;{n9kZHp$PKxXg+O<8Q3X3gVir-r^-d-+`?UM?;&Kh
z>-rr`oZQO@yrU6@b(O_0_!MzUO-Uv$oANJr*E`oNlLJ}|E-P}|R3KtS`lU=3nkf}f
z8@}CBZGq@@WeiJ4#gP$$A4}Gi+40{CEaHV20&Z$VdM@wt59P%oC%g%!&*t@zVqjL%
zVm_~X_&g>8g5I%4^Ee!|Y9wY7M?@h^2G-C!rAmY3z-G8JRP2n9`hv(gLmn^w0KaBh
zX)l&Hvwg(bT>anq+!sOA`IiHAtLu>Cqh&J@9P<No=KhlLx^b&(<2K$(TYIdmv2n?Z
zw7iiYB5CL}y_4#Y(u_cf*CfahFy4d+#Y9ALfe_jyLfCPlg@yr@GkcEW6l0$b<@J;G
zaDf}(<;jd6gg7^o5+r_|2+dS&FV2<)q3laazxyBvj%iu<D}zUKy_vo}Y4B4!kZQoH
z4|SF5tB=bW6=}zC#q3|%8*P<NI=b~gXRf>Q1<aAB%WF1rAKXXS_^Dr&87ZFmF$tbw
znX=<RTv*T@(1xyHlEtUjg|s!i<E6&BFNJ&7NLbsDJuyB0ieI*5GG6kXCd6aztY6kG
zgH*(p)MdR!^z6BO8dE4+k6_F26O)T7v+3z26kuJ+%`zP|MeIuWQWk9N9TtUnZIvp`
z@Xfj+5C)cHI}VtN7vxPo#c0$s>n|=O3|j0is}Uf|%#Zb&T8d9cXOu*~Zq=Zut$I%o
z1=~sgj9k5FG8KuAzW)IVr!Il!!%d{ja$NRyo3oM>*NSL>1K9C<N1LDcoZbk@+Ek?u
zf09R4gv2}aE+S>*OTXJe8RZVF-y}lka6l(<zqxAmDH5UF0rs#!i<~?Ow(b!!bfL*X
z2J8C)(<tg*cU}09Q<=Mx3X_iZ+z<1HWm?r^O`mD{8GI6V6*0urBNotQLsETvr4<&b
z5}Aw{B5CP-(~>0M%L>z?^EJ%feA&F%*P2KleQ!4WUYJaIlRq=e#3Oa4C(4aJZy)k%
zH_#h@AOY=%dYz7(aBe#qmIXz&ohFQ!{u;W+vySpNtD)lsw@Lq@-}}Oum{!^Cabc1`
zfCW>qh2A}9cAJtpBj#t}_%_{NhlmJ(6e)~XcxUi;f3WnEvf<tB-$#H_Pi<^zJ!zCL
zZ@48Mr;d>!&AmR22LLvb*EtI^cg^bJ0{`tLZVdP9`Tu5PCTQNE;!yQs<5-89iKCSS
zORhUmMT&#bWI7>~4%Ime=od|qR;y_h<F2oYz9OLk<)%rda!V5aR<`9()UVq;e~YZL
zwQ%A$4cN8t?ktpfp7+S4Q+R!Raby*4Ei9S*coL$Jg?b2xr9MS9VOD581qCJ9^}U2*
zas+b=1JD%D?w%xx<<RCTUP_`ML5$`iA@Rgoo#l|$0so)w)$+Tsp^Hp4e)G1}A^NVy
z0;D4LO#V3};E9BUO>}@PN)RD9I#F7@lq}y5_Q5^nbEeZLtOL6HIuyoY5~b&HMQkEL
z9zM6Hdqm9J%htpgFPgY3HY2NbV0iIYGQ>Om#kk$+<B^c1ik|OiIfj`$BZriTnAs<U
zz073zw&h!2A#pYMD>WgOh4A=#fq1RboGTUP{`pa@5FbuOyzoFZYHgBL-b4ttwVXos
zUTQxTdt{?%yYeArvky7vzyH_VhVL|QsC_i@hnES|h@U^L@@Smy%RBHFwLKqea&KN~
z=!jYwG=&Y~&7e2_U-%kGs&1baBn^eEB%i&0N%Dvr*zP7eH&+JsM;dc{0~0*Qunj>4
zfIz*a9C*+NIk==|9ZW#Y2)V7m{a_D7ApAu(FwHZ`(;Yd}@QGjrf8nN_eiX99+9m8s
zcTtGZJS*Bau%*{eVlC4OtA;nu)w5*Wx&-INAw=FlFL-lqo?%b2`*b8hYLn&secslw
z8ybI`+jJZ_gMP?J9d8CbcFetl$UGrAzC0KYNRvx-UysV%%hO4c(*Tx~fcZ=B+NJf(
znsp8J_qbnKed+IiSf(zV7A(hbOE{{zeT6h1GpGsJ2Zmo_s;0B~fXN}T|Da%|GV^1#
z47Qg4_`bFX3vCHzb!VI$HiD6|l)joAWqq0r{x3~GCjW79`(uAF-Eg+GRn!~k|F-Xz
zW9OKk46^jJ>YIQe(KTN_#auyoe?UWRw487#h!u0MTl~E@rrb6A>Jx!!|1PWveXN!U
z_1D3+n6Vz&nL_k1<mH)U4iY&uBvH#ZVyR5=a^Rey{hUd%E11oPMwzeP5L*la#-g6Q
z2*N}nbkP2IrkD4%&csdL0<R2O2RP;LB#z^%C3UC3Ol6uykd1LEVH8{j%ACNE`(Rl)
zo1kop6I>^zbMV5nzuZX98a=MPHb7ca+?zu*)nl*KDk2-^^N7DDoyF~zdnsxcDwS>r
zqdYk%ntce$kS@6q13rj~m06)Ge<)!Alu_x%Cgo-t5%eq}Wg=F%4b07#5__D1h8FLU
z+t7okK{A-$iKJGtR^V8^7Z`IM+8h(+3d@H2EtrE@N8$&%cyBirT&-d8^$zZ<uT!`8
z_14O!%mz4OElL3)@;E!wZQb_rwoa&B#bzS{lMx<HNAK!xNICSu6J*Ur!$fhZ`qPSS
zoaA8)3^=Bw&kCA%?Yz5;>t2zinbl%E8+TO%w5|f|w(sdTw+7m*O(j0IBGvdR&PSmz
z$SW);7ZjsndygMELUNo|2vod{{r$2#Cw9jfa^<Siluh@(e5v;EUGq3*tk?^$AzeXD
zQECsf{YDxCGr|-J3;eOcZbA-@J!A_-@+06~3Pl$djfWo#-zyZuFrMwDUS!MRHb=b0
zoMVk7sb3(|+N_Kr*mijarsCJ<-{`R-RUq*WvI@5RO;hI(ZyAP*e(5_^HclqxmyEx8
z1NyTO%f4TLeHgN0wrx_p&ffNSKv5776HlNY`z#Q@YU|OK4YIQ}ufAl9cnT5QQteBQ
zN2f`@M|k~lA)Cwg^+Vwx1VxJ>76lyuF5T4LsWIAx3$&$@%>&^vD82sr(M2=rx5Qp~
zYwbdxbGRNt5f{%mF+|SXH!PdR{M+8Lt0N?CcB)~MiGek%wyeYRVCtf1b_sv5#K!%|
z8gwJ)hsV<!4R)T!+Ac7SKmMa5M|!6e`Y@0rsn~lY%Tr+it44Gq?Os+&xQ>BP<~}#(
zM3DNuiAo#1NaPZ89vEWz2`y*&bD@u%9EsP~=JwE0**8dKbQ=1}YD-|Qj3+uaX~JEJ
z6Hw9UG~!oc-r2%t?f+wyRUxrYSGA%h{edRZSOnh|dbru0Q2BBGf-;UdswHakTW3D1
zFQ!4a$+N|^Ze%Kr0eN07@^;raKx@)=`n{go)Er2&yCj&9wv@&Ud#TA`qtZmA-T<!O
z&GS|5mp(Jm_Fa}K*W&>*kdspq4g5hNgBbWt?J6exIY!K)7CVG3e;UcJ>Qcuqb*x;~
z1+U+ztOgECviKJf*7>e9vncYR4Gg{YL#;PHMO|NG12YnC*-R`puQirJWlbjQ2Eu))
z{=T=$EtZ^vvk<~aX9H$i?aQ4&DqOaSV-x!2yNjOea5*X9u9~t<4q|e79XTB0X9#5>
zoxrP%t+Ixxm3;gM#-YrGl^Q~D5}so=)`99PwjT&U+tc%9NwtW`{$nN&rZacvt|3<*
zt5(p#SCV~_wKC!Cs~`jygPkUQP$4HH4C#TvOANZrD@90r_!RtpTS3$DZsrzQP1hHu
zl|>|r%N&f^XU{InWeMCRq?2DC8=g<hLqo|zPc!0V@<*;VRK<Ant)!wMKrEd0^hN#I
zXYbdn5)O@PRx!VPFU_!vUCa^q;iK0Nt>)G4k>0)_{cZJK`z6s}YgUh}RR#m<(gI^}
zRz?E)#N9fgVF%$K9eOu7Ek!y9W=Ea0RO5)Blplqh3D+HNSa1JBgMmbKGc!u8#!i_E
zBVGX(^zJ<{h^>=err|BXHS6OZ;l)-PXlIY@Lr~~39s@5?ab{k&pdp|`v_5_rxC!7f
z-cCw*EWkyPZh=G$P_w1VM0Vnix$qmpF)+I<`Q*i{>ic)8iY!0j>Sc<$1rmr`C{Vf8
zt(EUKBTCUOjNd!{K|v#?`<L<?Y>(TTGpm=>J77a>Mj5kQatyN4e+Zz*4!Lk}HICzh
z74GFYx7+;{ci}@tM@-ONDzwnK5Uc)(?mRD8flY6bT&`|0>I6JYm`6dbbZ43WFvekr
zRXq6{DH%B9$^v&4gZvZ&X%R@W&3!<QLO=XnAO%KpNe<CM28{XQk>7V$@QLB3a2>CQ
zGv?yjD$^gtJO~Msoc<2JHiw1cq@ww`mOX>#*fGO2`2{zOvo`R<X2v9}NJ$oUL!L+g
zlJ2L4((5ezo}cYSAT7eM-l!O_g4VPkqBTXW<%~-kbwy;Rz%+{^ZDkoZWwzo&uu&8G
zU174TA3wP=YZ?tvVTJv(?T~?E?MMm5=GnL(D8|f4)Oa8VTsD@j0X4TRPv+4>sV{V#
zHuID$)20EE^whpW^Y_}+So<}fxn^pU^rGu_r%+nkujze;2*uJSa4-n7I%VPAH0U`2
z#rg9Sm@dN!!4cptL(m<w*r!nJL2mNzpZR?%<A+b0^o&^AOR(O5D&AK#YJJ=-JRRe@
zx**G#e6uGCb%p~zLXwey5D(Rl7dgl>JAoujFAJ|$NCO^QJD3uP$pd;p=JDUEuao^T
zh4T-+h81y`{Onb@i!tJ+VzwnGW_|)`)fbRXZ8(YgR5M)D&mbR*L1l@toXY+Gx@dYi
zig1D##-NAJE2*KlM$OU<2dVfiBfq=8L<4HfR5o-{zgdy-;SWbovgZOpx2Bb{AMPu=
zDt<Oiq|n#K4eK<|EkPTgc@vRM$j+Gk#^`!M>=w+e$^-cq-`^`y3KMHv)Z-ptRNqIp
z#oK!xWHDl7Yyq7H-?_Ep8woP7lgPGTAX~U4X??{)Y=Z}EDgUPdN!YOx&pQHwO-P61
z2=dUeD#WiIoeh?;K5Fk2cT*238pPEV{rDj_^K1{vSlxc}n93N&ygZZ8WAi*Tzr)M=
zEi&`x2nDVK$eLMxo<tb{Zp@pfD253Z762I0oOcA>S;)`kIPRwY{&cZF=M_ufnZ<tm
zpX)WLf%7Y&6-E{1gdDA?*fqsV@J%Y;M@1??(t35P_?)|UagzW1L{FRmQELoBc9)uS
z*;iABIP`3u21_frob3FQdMfak?Y)OIiY!vDM_z=oLS~>L0v8s@vcS%z3uJa9_GwuP
z)dy(lznnK|+01K0D>0Wg9Ulop5uJfIo<;?3_~$ybcbQ=&RC90Mf7UV0AFilRVQ7MK
zPmdB24U)^}RHmQs0^Bu#PQttCtdOnH?`!TI#5PR(e$0qTU)&a{g)od_<^}C;Nh^en
z5rMzTt}m%p^-!8SPA3wwv>-{Qqf<Znt6~+bE2rY5e!?s2u-`h6DPq4b3m9ZP`c4cA
zB0YVdXN94;d*@$}{t{o8CEc78|3nyVInqR%<#-2N*%uq7G@uzy;9)h06Og^yd4fU`
zZZ{51S(5xE58X{1LMRCH0wxJfFYv8W{H=R=3*xAC53|QGP}gByyK8gZ={=mC7w!PQ
zPh}3E;<n8tIz;-$<T>&<Of<o)jwgF9|2*kHU_QgG1fN~`TUgx4ptQ98<)hw=z8#<R
zmiP59J?Tvn4JEZR&nM8_$#Gtz+-;jtqnlu%eRW>%$Xs8Sssa)P+7wCCDlA8O!$8A$
zsh#i7a=&INga>@K`oQEx+j44mN@s2heK39)gPTB$>aXC8QV)Jrquoi&j3F6Gju!5(
zpUf*!6&r|jl{>TnuK{}H8(h=XvEkt%hY#RZ5pV-ttR-dmmNz6|3aHgl;>8mRnDz2q
zX~vM7cBF!y&XdrfG!4Y@*Z#|A=dU|v*Vq7I4R81YS=%d*bK*%qTxheCcrGPEXsl}r
zO|YlQ2xAH?w51KfYdgmtB-vM-$Kx0E{iW((cWF?U<<BtdI92?sy~0hkzstX7_HdIH
z#{uO~ThMBV5URwdEIDKy1YcD48=Q~4|1T>4nvi4QQj=-=Djs5dW;}2+92zN1dx{GF
z=0RpESLfB`fuZ#_30dctZ@?<vdI;Q~q0W!Al9u_S<X|_xQUfSF*-W9O=07_JhoBYr
zH>VBGj^Jz7lNTgTp~~G$Y_Kxbs}F4~5#EhKA%IfSGsa@Jur@Z9<n{8{D!@To|L4&k
zsP8#KRQ5#2Hb}V7fUDQr@)PUp9yH#KoA^E(fb^I5RmbNfzfOT6!awKZu<+>FF}@e3
zv=?HrB|#QVeUbe8CH7tVnkpJh+07}-4@zR+0SB`Fe>&ktI;7_tZ2$z9ydr0Chx4Sx
zl|SIvSk-?mY<7t~G8!O#eoOF@FT0Z;&kSUtZ7Zx1GA^FM^M=z!bST*H2{OBPq@uG%
z@&SHs%b+u^1bjT6`1{Q7NylQwn=W#HazQBI`?|KpM)G(r*n6@ybw}N(T%msnn@kL~
zF{lhQ{h<bI;aS*lQ(u5hngTlBPEO-HmEnr|5Jdi#I|1g_K0d_}Fxoh2Ta)lEiREfg
z?C>wK92t9TSWLujV|0?K?XO6GYl}{5w39qD!`zdF&;N|iJ<ID}O|VouU)^t>c7@#1
zf}1Z;NCviM*{^3Iq#zVbh~tS$H~WW~F8U`pi$;pm&gx=ghx}<rN{*mT!Rd;Hjj;p4
zx>=CRzoFT+P~ONjpDHs(O<n4{ji;-H+DrPQxH~G+^Hv)WXy1#5<~VzzA(PGDc*1wh
z2+^D@*=GQR&X={Ck!0GdPD|WzP{B>F+gk#llg}pbn`|LF{s^~O1h23CJAnD-?6S4Z
z069hmYsg$f`68?SjPiR0n^KENHnd^}2;3wDwhrFe!WJlLubIxASF+o1Y4NkIL9vaL
z`QEaU`HQ!#f`m7ID$aTW-Ti4_8;=H%73>NzfdWYle4OZMuCCgocg$g{KPYnK^zuSY
z^^24ibG&wt)UIa}Q1p2Oy->2L$6$6+O~2lkXQ1E)U5C-*i*zxJX!BXw7zp6`740+Y
z6jW!4x)I5_eU7jIf7z%tYKX;?)_U#u8WHaa%EOo5n(FJl2$^ms?$mHQfyc}KxCQt4
z=%N^4Yl47X{j4aB1{zdt?Uq)N^|R)EV?Hd4x=*QGa7c=~V8L9!o2@=Ar!wFi6|>O!
zi##vF!O5RtdhC^$PvNo#D>tLz(P{}sx@DU&zi0|}t>Tvqo;0D4vJx|q66GHh?mK@A
zhW0SB$huV1TYd*W{||$(#)75DuXp2rtrEw$k#;%lI@q3E{Nz(>%62Qwa_?k)(4E{P
zNyhgdo=Yx0N;wAB1>qR1m~wDRqX7j1Wx(Ra9-$l99fbf5bJw-=AHZzR*yV@p+>Vgp
zL?pp&>}Jj8#SUQcClWaTdmOgIWSD2XBg4ydihBD{Uk7AbsTW5_`@*q9XSyH9GFAEM
z#s=d1+3%|EpksSe(OdO~nAO=lclQu`>e26gSgd4U&A9L$@vNC(eM8W)5y<$1XOhvH
zoLT_xA>u_CGAW26MQ=iboZ1V~vO0xlZHHzAOH2P<{2e`CBY9qyn<xh0o-HNDtM2wi
z5Bq*g72a+#?-eoNT0_1;4R1L*MN!CsI@9T09ivsMCXk=Qo5%v?1&c0FGB&9R!}IIz
zRQfnj`zlp8L%Ye}D{s<9MAqg*emSd?JHqFSo@0yLI6J_@z5+`E2+G8TiWSGz(4i65
z`=excGeEze&fA)gTW(1ML%)}{5VAeNt26Yr2fI}i+Sa}EGJ5*M1M|3QaY~>{{Qa?=
zc-Qp5>0B{J^l%kI!8=SsdX{rp?+!sB77IJ6Z53oX!T=EuGhNaiXOL_L3KSvGsr6PE
zH8K+1?5Q$LsKv=KL|9vv_VgGLdgxBstd`_ikw#SFrDJoE@MMKfkAuCwNJzql+|NIs
zI}vV|%xnL?yGLR1f`lhRnTF$EgBVZumA<8P{ifm2(<DCo31_8Ah-7t}$GbWpPz9wd
z`hfoLeFiU^jln6whlxXwNW@S$tq%}e8{~$c31a^ABMO8#EK*rw8@`eE7S>T`enP+H
zJ7yUan)bZ+Fe$`#a-*ln+|bC0(;vf7<EcY#l179VjuAVfGSn01Kn3uq1`fnFS4j>i
zxGWh!1v}_k3O6X>vGK$HIdei^9VQHM!e3xgrdDM-*Y3+G?Wph^?)%Y9C^Cz$c+kDK
zg|>CX8MzWW5@f9SEn%#>Y3fVsN(lN&Q-@4b0F9wL)YuVHiu|$Pu3k5XN3mw5sK`h8
z61iL>I>wVt<TrJooItf7yNSBRu&7+7gDyYNGa%8Y(2YdJ&o_I09L;u&Wh9UBT@MN0
zQnm4=4rmrBVU_7CM(SZPcg|jxO9M`pSRpPNF&8{kF+l|Cezuvf=$Pn##sMTz*Tb5&
z%Ii#F2i#54w-sc5@ij7*Aod0wlzNR{^UCj1gV&wASArZ_@JP&;K%)(Ho{v&7v@EE6
z&_~OWN&lO}Z+j=_D|1DQFlW!{(WM4;bc8FKi&K0fvrBGl6Rt9sIMXq)PAUE4-9*fP
zn&rN)Uw7#x+mTYRrWeQAhMjDxIz)J%rlUoJ$<icu^-4n<(&~hcW@=u%ydV>vGG@w*
z5kmI41p?XlFTsWxT-7tJJVIRr6pg>3GuJYOoSWp_HgqCyT{wHf%!C`5k;^gn2jc&+
z>xIK<-a%VUDt0QjzX`iGQH&Z%yb3}oshM@1GgxL*&Ybxuoc{*kKil<FY?#qZ<t=Mp
z2aX}=+<2xpW7HqaR#W~Poy=-}zZJpsnEmk|&@xF?3V?GLLOBOR^!wBo@!^{&_mb{@
z?P1!IjAC&45_I8$cW6UdHbCS`gRpy92<e?>0-40*#O`G0{tRJrKh&QgZg(y1Rp#J;
z9>{ns3npL(gnGWQ?9#xL@jl4xLosb`gAoJyq&0A{wPOAA{j?-gGFOhut6}AkAH2~q
z8fSiGj4U_+3Ej(Yj{BQ@S;`$*+F*`$6e^RDr33@WFs?Kqulf$+yqf3CjT|Mm6F&@f
z*U}C3QrO~ELl0xh)+_Y-r{5qI@Q+ch-42pL%EuVMtipX#Y~TkpuvPn@C6!zg+1r-%
zG=<s&w}zyontgT1k&FkRNT?VZR`S=Bc%nq4D&4au_GG%<`&g+gHHvT~t^IAu0?g$h
zB_dafpxkY*E$>1wl2N+tiBaahmv-%%Sz;_`=JVRbNmC}k#o*>U)NE0`iu^)51`;xe
zCSyCPj}%eLq9tT{^&lKgo5Y871x9AkF0_ea20Ko$U&ai6rs|)vwpe54LwqG!ogiln
z{e1}t#ax-CZ;a9=Zv%z&ztSJ0oQ3mHETfEvG4S=({BdoL2#F8xUH^uYkYXwK@eUBJ
z8*5kyIqvg(VUpf~-X1D_ueV*H=<3U~UU~9YV_eXX1C$^YrXD$iBo7{>pLFvYA{7Aa
ztRmYmU3{cM=_Zqca#ubV8N0aV5_h7Zl%*PE-gkFr&73Z$fj~1uyZ~b5D1T`Fv&@d3
z+HIUjaiKe9K4(&}K~s|E@g?iC2}w<SQaAQUP<80%SR%$V6GmOm{4LhY)2X@4J0q&F
z)c^!`tWNsM9WHshKiiVBMci;oOIb0p*&VQuwkGV#G6=068wsc2MW24N4VRb$2HsYZ
z)Kc~bpZfRdw8s(^MEzgZFNt-(V`)Ns1j9^-GmEpKr2jt69XNcDt`}yeNFt35EaY|p
z0Hhn~75-k*FemV$f-6KYnzxb3C(sOTmn|yR?k$>cSm3Iq$=7lX=%KwCK)entzUihn
zQf!uM?u99%k^?!DS^*T76iK9`;I2DD;(Za94PU|}z_%kVji|9`hNa=J7v>EPDFBLl
zc1V_o7`#Zuq5U#tbTQ0+8gC1uXR8+A_h2F4%miv~;;qu}_0hUle?Q#8>UW#j#tZPl
zRfsn<h6=LQ{7a-h)ToSBMy>e7qX@N`T=Vta&5PA7p`8Gu`kZ7uD$$T2S=Vkha#T;*
zedS)HJK|Pb&m1NggV+yMt!%PY0I*Me%k)^L*WGU}M<-DnkonPLQs2F<S+;rA!ehN}
zBi8zN&*DHNRAerqXT*~}0y;|AOQPFIBBiHAE&v^<Lc;B~N+LbK{q4J!?e~*z<`pt2
z^$gQeb`n4l^nCxK=H;McC8!;lQTTyrp2<WOp(1P7l)7V5*b{OMr6$ecwbfBNq27+~
zLjz1X^MP@2axJ@p?k{vC%iUp@E7Si*>XwT9u((qx8T=tvZZvr5xL(o<4Q%%^f7CSv
z2n<TQi2bXg-?gVwx%vLOF=k#Y%E*caJ55epkrMaMpRz;`d*LxhT{97ZQ0B$1IdY6=
zCcj8lL6{ZT#T?%tfbibaJlx`yUNU*M6Q7*sP!3)#TWn5<Z}s;Ts4T_Ay6o^ABCF*E
zAAt<V?cewNId)VU5@e{dW3jL`&f`>#M(E9zH*L8eBP;8!0GYHX%FC2DHWA|pv?dVw
z?|7&bDsRXO%KH*Gz)hL6rI)Z41f_mH6%Dc?nHmltL0fM4qW`FdQU%4oW63Z6B$gLj
zYOY5CrM|vXedITpp3}hne4fr-cexG0g?Nvw0l5s(N-ciFX!uRcS21gc>5N>j1U=_y
zhjrT;vdNnd0_)TdE?w#!q;wM$j3wY=0Bw@0M&e7n$KE{a7U5*jA3&LGT0*Wr%jx(d
zQnm6}{>Z7W+9}@Enh2XYO|%aL*+{98){&k5OZ|wOVjU6=-Mq7);pGvxVb7A)(uyVA
z52*5=w$BSY*Lux~u!JrJfV!#SqQc&7W>dbE|5B*FK22NN9TwIH3e;!91fj@<*x(7+
zaWhu7tVF-_6w*y|W)|Er12SB+!S_Q90IJcN<?)j4UuI?h9t0!}4!^fWf#)NAWwU>A
zg{LikBJpIn26%DCsA*Iup7(`(p3<X>g9l|BQI;a+dv8}Z-@Rn|Dk74t-Rz#G*cMQ8
z9W1T$v5M|O9<zbU&-Kt5TQ}*DVtaW#A<*}86dgBp77ieQ2e&_KeOgyNQo|qD<*ols
z=lyOqH8f?m;)|t0Z0o5*%<t64*EK3J8z$pWn1&TxP+JZxal4A*x8uE2#nXhXNBoJ#
z#YIYr4Fh8`im^xg8<=j%&ML_FM=#fYRwYm3aHJ;wfn%T~6a1x|7DXDh%i`i={Y(1<
z{Rks9523s^Bsxw%7lOreRhpN9tHw)Ep$SsW0=$Okg{Aa8o0S$=1V61|+qsFHE)=od
z!WxmL6(5y$z%puTbVRy=cMQWlA4~BFU@u)VA@aP$uLeZtL_N8~<Eln}vXZA2F`35&
z8UN`tLoc$G60q2pgJD8E|J(YDqr7aW`SU7PoqC##wmnc3<tLWn)DjpKkV9JBF$Vo*
zKLQnwHi5M|_>D@5o`1F%?0Zxb<%1wg0lvkE@V|8ZcntK+)eOI7{Q!F(YPTB4Mt0@H
zkc9i(BPjHA`1x-@%5(WRTq*(@0n0MEN7O@bnIM=7Aypw0>Rm`(w-#~V%5`M$2D2>X
z6|Zu2)01s+*feK7ihIG~o{O&o1pIoB16Dq!T>&xp7tWq65PS`XdUa3X;|g;^hcpkU
zv~i<%oPc?*#<$V|izFuxBft8Fm~d%&+$s>9{`8kKG7xh0O-HI=+7nq}9HuDh+J3x=
zqR#-W_Q-{d%h6aLmUy@5ix2dZ<TXdkCPA@qwfDv(ef6yuTLY2-ruV*`Gr)Fqq$zxI
zXwcM>dJZdUt~w|-&{YKam<~!dkd1IYp#j&#B~lgvhbZJdIgJM_dj}|0Na1~rUz4x(
zYB^|%1p`E09$1$vN<E$88n|6gLEoZ?dkoA4uxeXEX4{3=M(l77v4{N>I@y~BRqhFs
zJqS`*_9xre>EprmEF<UXW#@@@k{s@hPdyR**35Fm|A<jafP74Nm?XPnffb-u{P+^p
z>7W2tRpf+kfj)k<xizJkNdvT1ImO1CgKQZfofajmzW#R5M3o1jI}J1v`tqTA_60Ne
zYb#^rdpK%WBMQb$hn%Os6gXRZp6aW*hy4VRs%iXvE#+GlI$QQWnm*xSiMl)e-#u^x
z?#j`1quge>j}5MPz(EU{iwcASQBn*soPTb!zwMbwAg48}+>QBNJ;>a3JuGrVE#TL_
z>;Z%5>8(piZci}AA%1VAOnLC1euot=C6h2*h+x4T9IcYI(F-7>DT9Oyl`Dw+aYhAn
z;fbA{Rn1q_D^@(aEku<#3=!oLGp1BcD6&6mhZqHMBpiee*$Hz&aum!0UVtV|RhhuO
zz)24}LD8SDwnpU)LnNYke8zwi3Z909Y~YnQf6DVj5mSW6^uXt8Q>!I2Yp(Y0b4)8m
zFe+|t&>hL$`*5t+n3K;L{Py}pc!49ZF{qYffGi^xcY=lUSVcIYvH&U?3H{$FM)x+K
zgAhj=K=xU6G~*d^(1pS_V+N@{mDf<yzUfSo!gXk34pXeY35zI?_r@J>bU|RN%h;nT
zsy%JMVQt5{5Mr)#QD&BhMShfTSH<@9?eOcKuNNa>BELN$=-h7Gw&2<t3L}r1a@V7*
zrc8HioL3P&)p$w^$tL52%R-<Lz8Tx3V?sIoAA-H+kS^1xtidBIy1B@8JqFX)#!7U_
zh$rH_NIl&f5t&PXB{&j+;zk+#z5IS&TsOeSgqh*T5te0QQ2RDa{|jq2kWQ$`d&LPn
z+gg;{p;${t?r+ko*u5NV!l6$_wYGCzZ#fkzjwt~Qaevr>A><8&!#JE#%?|$%P3$Sq
zy`@<RADtxz5Oxu`YHMWGCWnr|k<5AHEPgjMf$hrC_*PLk7%({gcWz$B()8a6Yb7_%
zVd{da>bJSg@=iZoVfOL<<UI;lW!m)Pe6dVLmg^k3y8G@axKMvTmIm<Kgmou=UI6w7
zG?k8kq+c%?8Gmq4bPRQ^s-+dh42@!h%b2y0i%$0Cry99ht+}GN@N;|kp8iq6IA>te
z!n5TRG$93jdghP=#)O5eIPbTnj?P@*tFe3!=Mg;f+2ZstG^SnJ1`o_LG_eFs57fDV
zU?Kc)sW;37ESpcviJhEVqdT@bL=~+8hH3owjR@8JQ@lQq^Tyt+u%%T~foW8Y3kcR{
zs<fJF_p4E~m>ua+L*#>HY;n3b%n3ch$*(F(3dFFmGBVzoNSgpYlQRqQ{D6{I3x3d?
zH8Ayj&l;a=eFSgqn&<Fuj3Tt{vyV1X&R@O>?7Z2iUa$f%un&gDULAQ~nDCLX&Ho1T
zfFmDXM9@VinikAU!QaSwmKeGbg4U*0VjG^ehf3R?n-ca2A!`3>LQ7mQUA>U27#nA<
z3)jT$O<lug_{y3bfnv)C?Xs~rxDJFT^d3r_N72=E8Vn|U0^4|hpLkoK?!*GTYK7EB
z85b+`K->~Zf)~L(_LV<cmyeifCCCO=Bt4{1%;qYZWY5|Eg2}f+AJY9DBGr}I_&imy
zqJdMSSpaJMbx4beUkegHBP235qYa(}scbe<hpJ8S;>0*Kb15V6+Y6V(|I5L@q<R26
zI-hc{2HZS==z^rGcq|#5hbQ@AnL^x;7wCfrytNmgx@ERr`yCSI>AMYbmEApTC;|x#
zq-m2lTd>t;6!CGhL){38Tb`R1JoSgAdYKmq)<MMn)MX&I@HCDm?{aIb<-gdqOOxdG
z)OrL9Ng=a?ZP^DRi|Nj6+^}HP!&uZ2%4DR$V)E-oYF+SH3Pu%lYQfe%O@<iCG$5&~
z#Ci%w>`9BBWw)?JX-dEO?o?%%J|Fw2>IjTT)2(eLDvlkSu|_qyst~+^W*h}RJ5ca&
z8r+PKvrt{<SBYr&G&a}?pVN{4kSn|hSPYmrwiFmAjg9oog&G58j&I!(Nzcoai2u#q
zWdilY;iCXuLZrK&V(e=}dTZRIwRKQk_Byb`spgs1roguc;+)p<o2C2ZQ~;e{!C(}W
z!mYIny>G9Q107v1w-WJbsz>sOG-z+zN#KWs5#n5%b=E$rdAj}pUhbcUb7wk#Y5OMO
z$^49f{yFh$O+~0;EmgT4_@2(d+nv}3AEzqID};cA*W1bu5qMx|A1|12zqmdZO}MYF
zCa~<PeUQ~hG{eie2C=k&`$6Pci?&@c`y2lyZ{&xrc&nc@0ND?(-J4+bYZ~m!f#n)D
z*L?05;u&MqtzJA`RSTi?K~bT&k^9kQ;i4%lq^@@l`10cQRnnh5Tqk3uF?J?G3dh!8
za1Oa<_L`grDQ>pP-*B0SvOXw<_S#=)Qb?dd<mtnt<mF*8BB=mUK&`*<Zm;pR6pg}m
zr3Nvc=_CFK2iC3e3hGUtmyQZ)B{=GdHwg=3S7<>>=cJUQgc=x<aI5YGnF{QiT3zoR
zA)aYs_fRp}DeG`bPny63!6X`6uKM?E%|{npsOSOOS(-w|GSDOijQpM*H%X$!nxGL!
z#+1O|Yzt}u8h^0K8d@%9{q7icW^Fc8yF;8aKq!-=)E>1B@#Bi&qhJZQIlAfMYLR0C
z*kYr1b7gOr*|58b*!*+-)=7&l?!1$0EDpr<{Gg96t@p+rQ9_aGN)AF}@RB10nrV<|
z9JI<C><7(>BaG!J**ruMWxfJgOx&deRwf$UHfqm{`NdT32r(a@Qj15O$sCgb-C;c;
z?v}iJ$d+EvOSl_Q-=m{9$=0zH@1suy%8b$7Zj?lx36j}rw*XLeW6e&UYSUviKi=5i
z>&e3oGQ(JvYXvqnL<8+%Dgf`*PA#O=26p1@hU0}Yc|Gg8Q#g8$iP=xldPy7k!Xtf#
zgz7~oDKJp&*2b-7Bl@*xyhsz1v}X=oFCrD{UkeKa65t>+NY1-dGWIyheRbqc+3?<*
zFcjjv5`Xr)j#hU=fs`AoTKnf&F+b`T>E*K$DLiK=T>f8cj^HZ0s@2o<@XIxW{G!bE
z>H0E`olkf&G~QD}xZ|)Zbe##YQYmHgJ@<mrNHgupzd3ixf~<3iYMqK^-GgozkkYeU
zot%lh(mQ|4ehgYcQ)sz%4G+Ib9)WAG2|hFZwCx~%){GFb1YqZVCG~v&NW4yOOoqk)
z4MW1HNL5eI=az5|!q?;nXA8u0drl)d{9lF$L)JlK)SK7&^3T?&ry@Cv=!Pxr+^#JA
zswQ;R4C!=G5?zR$>t9$G(`V)@$A#Xp3@R8bV!C`j9mSY?{w2zLJ~Xe{M;UX4unNcK
zTz1VWGid8X7@3df^C<kigxNIV<S^BCYXnD!2)xbO%&oQ?JtlI$rd2;Tn{uv|=4ZgL
zy}(XY_eQ*&@e==__lT4|7Zh!9yQ^Grn2!_zie(vVqg1c1W3rdeJsF7t=FPAS!U|yp
zk^-&1opmo#n;=2^=uH-gZdR9=z|Vdc4Nd*kAj{+)H9{~eIAxO$7}g`kh8X;16fMzf
z7rMQC#-aw>G7@TI<g3DWHub^*3BU@yPK(*QB)*Z;MRFB{`5Id3&r8u)eD~l71+XZj
zkA8*(#&ao*A0)`1-kF${9*}8<Gvi-p`17yhFX4-7ND+#(kw6@O%laQmjV*Vh80TM9
zDG=5J5@+t$Aw9P)nd~slrz4?C+-;aNXm4C4Um$3i+<FZk@BRCV9T1oB9dJ{kbuf;=
zQ&X_|!Qy2K0X&$<azqcoVUdq<(4GQnE5P-{0D<1G1`8nRLzW1YASM`rHj|xk;j&)0
zT;{36Z8;z&P%_Z^q!_y-?=^NceY?+TL?r!~6;tua+qR1(q%&7I+Dnvz1;u<QpoSy7
zpvoAZ^hhP4vHSJEtvD8VWtzdXmi=O!>~-DREJ%fL7A2g8R03h%z=r*5VNu^$+SgxY
z7J+Nu0AWN!)ZJewX=R$7a>K=yYsb72?U~QJ*^w8;W+rqAWRMCHrWNa62r=PIi(Xxr
zQQ-Vdw1o{Kr4Hy0OM5fVu?FpsbjOI;7fU1!kD$nVZCJJCWmO`mqlm^r7gaB5cK~$5
z7MiFB|4T+2!KmabJ+yV#oAB4tJ-P{!Vm|L_F7-O*mLA|SM*qq87mr51QS*;WzQJWc
z7WM_<ml#kNDKf_Zw^PBcKar@ND{~%xFia_dVRxeAp~jr#_%Yyv^##-r@mCqm1d^g(
z?mJ-8z|KowU$dxXh*&=eH1{M&@7sn%Fo5<8lXb~8<;;7-;uUx?n4Rr<21cXZ6GC<`
zxW&+Jjre8_Ef<CnQs1%3*_Le)w+4d$iZ>Kl`}64e=}6|YuCyjX*_e^n=DAc;IZecr
zDh6xUv<-qAAeSoTi3btO7Z3|bSwtE{(kJ#_CD0S4lQZIcMeY!rg9xK+hX*IbPDTc4
z)(Q0yY7|oKvu1A?oz5%vlD)TF#3KRHJme-CTt8L8%6wvi39L*Y0Pg1eVaE0_+~K5c
zFKjYOIyw}x<EIs$1rnekUNH~$ZX;=5gF&4inf|+q>@jSdak)HN{C59Z=Oaw`S%HV^
zqqVEWhM{WQrD6lr;>YmSY*WwW{dzjOjpJ#I(6N>4OM~t|tQM#(zL*T>o9=>69uUfG
z$_&xXDPHM|Z~R!2AYN4nxN0idGPXI#i|~0B4;YNw-DY+;Ff*Eg41vYB8FR5N#F+)g
zq+ow9q3V3gh2#jJ+fF5uOlG+#8(rae7dQ|5R!*Q%3}nOJ3}{b8r40&Z)BwlKBM^pi
zXj8XU#wi)|C|CUw<2Fe91dX1QtN;aaKmV(vzLx<l9-?*m!Z3Q~gL6KaFk|NMDt4*n
zUYWMd^gEn3|BazZ#@5zCelevwM6P0EPNrJc7SMNwhRse%dn=bsmftFEzwzYO6lcL6
zr|6qk#xjwRA&&$~*C$1@8@bfrQrk|>Ql>b6ybrr;<R2jUrl3`hCb6MXtE;!}?|ZG_
zt6JLx;NxaMq+d<d4DTsy;{&ew-7LU8;|k<d<xHF{GnW5BSO$?sAw&e4QX-*d;>zpN
zCyjlY9NI%W2N#}o+kBkR0POk`#LD$~qGB~pc~=NhlmT-?Z%w5SN|{6Qvsj|^#}u=F
zGW6kJc_ufO42)4;$gDzf!Y*+g8+MAn;f_=nGHLF#envDYNoljp4fl=Lh$1yQ7zYbR
zG)|;vM;8RG^iM}qT!i2lTv3wGwHGiz{(d7yRiWIQC6LE~>jxfYqNdij*m)9_>~bwa
zw3U<)$P-^4f2<0Ooim0TRAR;y?Wf{NF|+C2+!Nh0)@lz^Vyjam00{N8=~`pysmx7?
zj72W<|Mz7e-IPx5MpRQz0-}2CpNdGWlceR|V+y;*tVY5sjW2%Ft#g40v{>5L6aT%W
zT9W-PtCE7j!n4w!A_ubEVZ^(g^d%B39D_ozdPu2Rg`q)e8nz?D*gMU2yP*&kif|L*
zdIc|{nA=ZLBa)IzXttTy65CH_<yNW!MWVBam^MN(Pr;FfEsDbMZ&xoGJO1Y+TEFzz
zb>+}oazF}Yx6zXB^&7D51gE_Ua0fg$%^(eYK}(kklR}^%RI@t1%K@<I@g<LD-UZjd
zGO{D*Ij{g+OSVtPT!;~wjvS1fjhsly?^a*C-XFK<Pm*Q_ZpxmlEo+1#R5!*kn>=(Z
z;K6pX>G2R|u807zrPmNt(09Tnb`ZEcdHquWBQ#bgiEU|C5DGrwsS5#4qT9BD0M(mC
zX9E?4`Ldmmc+$UX_V$c{A$AUu#n?yYrO*Y9qK<>c9WLuqZc&kEER)Ap7Vp3)recdb
zvLMx92Qj{m#8wWZZxT<5^oro*c`6YalF2J7rIS?5*cQW&n}HLlinIcq4SL|NHych~
zNSs!pjY(zi7OZ&lK5K)Y>1rzTDmZE(;sRT{*)0XZI?T=EHY;Xe-|JFQq4<YYU!V@N
zy)jg;7QlbDm3Gf5TDB?)EM-e!PihZ8uR?zWMoeqxwpYf_UksHuK_~MVdU0JRM*!rP
z!A$bru>SXEDrN(*Ztb#=)4AfN8ZHI$CtqFs;R_S_OQDNgZbazLF`c~?0LC|c)|ktR
z&g2@6=K3-Xd_EK+MoC3OFubl{gxA-F0t&f4fboZ%ntSbcddVx}*S7%;RtqF4uq8F0
zdf{1Ih0XT+g%-;V3gjG~WaI!LzgA3vjbTh+c+KwS8mZ3$;T1ra9%k~`=C;)U32ol%
z-vRy5QsHtKfDOlvTEA}!nqIR=_b@@wC==b((Gw<xxa7rJfp82ruhnl*wE;eFjnjEH
zweX`g=a|)CLAz_KiR5=yVa3p-(MQVt$83XT9wSHxM|6rVuV?N1b|$q(!)j-aW~oRh
z)bOpFn6s(d!7xo@a<F31c)Mxe^~^=d?iEH$n2Bko*=eQ^E8PhMB7-Oq(KW}3J1el|
z9{ZD~cOQuqg;xI;yG{0lwBV-0IMpI85{*&{G7N$3+-)lHT=U4TOc|>>RGyn^yV8L>
zB!DIl?iCJR6h~jz`Tk!}VKJPK4-Vcj8C-EDScaGy*y~Qv7Vr{z?xU$n4w95s7BfF?
zT=~g;_Np|#(E?RFCVS+UN=ZRymPX_8leRh|v&HBcm9VBA8&(JwT*Du{Ev-z&D!TxW
zr3-E#`EcsK$N8i@*Yh>M4>zho^6*5UpX)prx-QQWVR+6BzAJCUS`9%aYG)5PCgW?q
z3%%j$iD6nO023YO#lmWU$UzaVOc{RKN_s^$+E{Gv(+9Q9wguIOh6n<<Y}#M7Xi#oz
zN--h40gV#k9!cD*-1kaJR|^aWHUnAOKiBM`a9rv;XIa!VAt@#-cu`|*rG+*BLZ~jb
z<{RyGc!78<1De=qeZ%q-@_gkm$+A{ISk5CC8FfLlU;v=;Qs2w?{=@$KcHg_BU4(Z{
z)bL%yNQ^+GedBopsDU&9sJ9GaKV?2)!*&Izk98jH(KRU_uU3`e*SYNFpmldh*(F2W
z;3cic8#rM3Y}>Co;Iz*NfUL^0sm&GXWeOe}R0L5Ex-j2&pU2jnfZJ{_Bp`iEMIDmI
zeZylV`Nu4I!|Kuo(t6a)-0OZlg2Y>|2Q^<aQC6Ay5rUB<6u^NPFiVd*9z@Bfe#}X|
zg9-FGq3CHH-tRxLX<FnqcNJZG+P{?#5O`gI?;dqa(B^GlFqhf?-Z7*#k|F8COrK}R
z!K^?R9km523A_J3AnuqTD0Fuf>|si_1R<ZrNW!k3CBW+>At>dn<I8*Au+GDKLdl1b
z4!@r%U%w@L7uyr}B^He@*_!lM5-2FJT@j(Du9JwOQ;=>x{ZA{Sz;Vu0foem;ywjQo
zcyxF8Uj6&2bGnr~ykMlIDD(VLDsxhxB5AEvEe!AP4aovI4ewrj*_y5~=5vPDiG^t3
zR9&(ZhrpSFUfSOJ42YTHEho~GtVMApnTK0dOxk++z&7joVTF*I|A*dF#$aI4^sfMH
zaOkm3Q_=>V1~P9Z`#*`NTx5d6$>mnffDk0%3%O99i+OZk6>3iUMid-p6uoY1u7`1R
zkV|U)`BpDR>%0)9&_mrJRI49{ng-b6T?mEcGi(Xfq7yUo97nx)#eIJ()@&}yX4QDQ
zSJStD^%H3Lwf@5%uxzso0vd_ca>+|mZ_OHjG}^OK+G!@9%?!1#b`N3UO#w0^W!fAz
zQq4^UuhE1>pWJGd;tBMc&45-hF@xX#1s^+Xv-8ghAT)}PW;-*$uWCm<Lr+lVu!GRa
z9ml|sMlckWW@sNRQKXeS#-saJ2wtg5#z;>(xk~d8UlFl6@7Lr;&x?m4@HnqLKey$<
zBp^qv*Vpu%L-$F(uAchJerv>kvlYw{A+-{Du>*nWk^~L35qO2KoL0!mNW@HpVsyO#
zQ)^YS%zT&)`_Q=)8rg#Y7yBs_!_zc}EQ?Qx?n!(B{v9Kv>r3SX>WHL@gYhY&rjB~U
zwLOjbbT!c7aVLe&)*?SV&QYP|7xS(c26+21!<d>o+iGoxIK@ly^I#tM>G4R@tUZT}
zxf`4$qLy-5)|zq30KD$(PcmqxCHpYAe)Mxk{Wp*%4QMudL_ecC9JZ%UEgD-1MsC!a
zIP?0@m(F=&wVBXVa5w}r92EcEMt4{LunG2_*EiK?${0(WZG|4jKO>m3BmrUXr&P3q
z3B(g#Hv(}KiP2AA3kEJQ(7^dKbbnzSp|_meK`J~k5hF>`ZN5D<XEchff}S2jui9b!
z+>X3lNM1bcfO14gEklUrVe=bwo!eRB^fy&z-CP?J0F!E(SHoSaM8*$~anT{DTl3Tw
zsZ^A2bu5Qm`c)w+`YmQnPTQTCa*s#b6;|hNf0G4*<3)c+WD7R%V|K>w&|mCQwjs{2
zH9%Sg^K&6*BQndN7jqKi7HH=}aofw|v$ud`WvGqEv@60HlQ89~iKQ!IGWq40*C?-W
zaVm0+#Cc*ZUs)kHEp5-Kll!#j-p2ct8cqw}m{)If;vA`Hnd<L`O|#p`>xH!|?3~V^
z?a44dnQRvu9VEk=RA4_+ZHw}Eud{GiW8Mo6WrGg&p+x4+6&-yWm9yzZ$5zd}jkbNZ
z|J)Y}P({2?>xh=k5d>?OWx@jmBgs#|O*WP*MOm;S-QGej+1(R&hQgPj7kOTL)7}Y)
z0=5L!3b}>M-71o>=M3yqDXeKu4?Io=em2#`nPddBfYPfNGWCep1z6X-PGvG+M*%EN
z5#Pg_ddvq$O+7(m;X>V)AmO+;pBe*r;T@|*)|dp4AIzeUD<cLxI0v|5k|F_dLUtvE
zKI_$};Mgm!BS-(sinD}kg-d7(YvGhI+@$~*(@|E_Va0${QSiSx>&*JtjZtLtn*`ol
z{0m*Oo1w=y^snB1Mx&D<IiIt>!YnnTu?2N&4JXh7bc#xug_*x+NkJrU-}3g#-mG?U
z)t3V32I`&EM{wki`^F;<&gI_^d)#T!<{IgoZ@j9($FE8dU{#e}nPp%h>nJB`Zkdos
zi4sP~Ks%HyI(a8njDBNv=%L06N*e#m%i}E3x1(lUv%t`|fQlB6km7yb=?NEj=+m7F
zZ<eEb0G*-#KUx)KY59ipNBc>Tt(QbE8eR3&HJ`Db=iuy%GCYJxwwWV#MYf_P@mLL&
z5v)NM_}rT2c;|n3h)Bae?TR+e<))(*EfobJz=fxa+|&Imn9Jh$G{a1Al$MlsEC8Xm
zB?4ojf$g;xb>;BuPND5yWAD<~967P_<V2(he0<4tT?flix`gSZXBu&V5aB#PgkCo<
zvN$5`CV*|m8>K#ad*y@a<a)_VOZHz1j@VT;N7_Gnto;xIDr0`@xVdNut8P%QIq@)K
zI;pMfw{tayba|uTTOYgMz+&zKW?+)=C^az!y{XOND21SqXc?q3xiac(>qe?0=vT%H
z+bs<n$^M{pS(Li{%%3`>io4`q#Aa(9|IRn>)Ij^WSAJdYGM@T@C^`P1SWkQY#;Eg_
zX-5yk<&jFA4*+rn{j~dtqO#6m&)MgE-Bbd!5E~}3A%cfJ+bl7rbN^v|E3y<Gf`M^x
zo2|?%?gtH0>HF@9vw%HrY(0?b$L2<ngUohtiU&vs>~_>*eSo%E9DgTN5Cd=H*wIpq
zRvFNu3L9*XA?KauG_zPj)bw+}M478$KFV%VY@fz)POM7War5u>#{RhzZ=i&lxs7EN
z6uuJIoEiRmmS<RsDua4>e&##X<NW92qh!$UVMxi`jel8H%yf)A%H;$8J(k0h+`067
zsv*!jOTnb7i;zfd8pzF+QA{Qbf{&0FHt^ArZ`m|LI>5ZcKNHFo2oXFqs@SY|<tmq9
z<h%%m7e<I2oiTehFxRI%ZOpNbJ|RyBNo{q?L|nExO#z9`@$~X&F?>00+)B}4u3!N2
zPrZRy)Spc6ROM0jV)jFQP4Xz*Gvov@i+>S&*AbZF{{i$~m8+zMNZn>9QwU+AZZSMm
zp;*&x;pHsdXNWo+EECrWHskvH(L4J|gJl{?HOvawE~HNA`Z_Xpy6zuIUaVeq3d2^i
zs8n-p)2G^VM;|TOrQiBokQ$BxYC*FIQ=6l;7IFoRy$MkGp4p3xp9IhB?_P$L!ho6X
z(^Qm*5VvTQYoL6P7F+fk9Q!Z}X4UMqDIPnIZ1|rpNy|3gwtQ~paHrMwD+&n+{~_4f
zL$67!^Ql`$C;Oig$F2W&M3(YV#3{DZr3I{!AnJBKJYzstkt_~^AbJIgPqhWXBg}-Z
zr6mHLDVeW?xaUH`gV6_G02##;*@6An(Nc0k+via%iv8kD)ryi(NP@EY*$|XM-uL>H
z73IytL&PH>a(D3$_zdwHZ6IwrxU|(CXxKXkF%Gk<4me4?JFRiLL9jsDXn0YPgFgOn
z6uXw}SO}j>#Mi-`WZrU%+L>IP^f%7XbCl`Ka(a;DGvB<xLZXRD`+T2YQQtI#Ku6NU
z1r#`<G=;=DzgtHyLd`nAxqTd1Hi-I-q=559NJQ~z=7Pb21h=L&O<Y^_c|nc#FbSsk
zuiaA@xJ4TpW%23}1C!chmVn~?Tm+@KsPiNzsa@n@Vq`F9@=WR#8rccB0)mf_oaC?9
zkfF#sofNP0Bt30uM^WFxbjj#_KrzY~#Vn@DnVsuY<LxLzIgS@goC?IF(*7Ay8iBC*
z*XgZ^@p=qX)IC|uJ8YE4W4_8vCLNncc+PUFKSmoThvG99laIJ8i>jb<CY7Sl3sFx9
z(w0Mg!2!2%x2B5`m*hSXPI-4@Ve9jrZw)dN(D>|X&y&w=RXI}okc)TA!n7kJ+_r9y
z!QiFG#i`2?-F=PoENPrMcfGxYSjf$5-mH|8zr6w=HO;UJwP3(7cucI%MlRpA6$T-{
z4fSs=BiDsXY<a3MS$3FNYe;!qG*dfjBDhJLSN?G#gegPV@s5PqXf>zUMS9jTsNz=;
z+`ApyVAPah6Z7kS{ve_sXC|8sQ<)D#Z+np~EQ&$UUtxChgmV%7NrXYqYh5K+!yS4h
z$BCe-H!FtR`#@^_`LsDC)c73Z1nGiP`Y8V%YSo$@_$p_5!V5|$s64BKQDBGiA693M
z^xc?%7V2@f?W0|<i9vZI)#8jh1I@1R9u}U?k7ljr!aHFqw=8M%`Fs-4@=)uWoRW8t
z99LLLrj+n<o8(RTgF+Q3$%DVooW{PI9)bpG7#CK#l!u~jXC*01i^_ufeiQN<9)^2Y
zU(P#B=i;pnlsW;k=RmIQ9P%Y7>DmEWnskVb6h2-w#z4#B#1)**qXfdGp)ws_b^UMb
z-`K-Rg*?)t7kh6+`+AqVm<w!F6%6do>I$v?sNx131HzjCwe%F$M-tPR$E_R+B-I$7
zF4MG@%8h)#ZgoXc*ZS^}q0cdGpD7fVE*8`H$p@`i<f^c^d29Qfw*<2^#25Gy`XW#k
zk4LWK{sZ&%mUI(ZWiRcsJL9gqPKU@roImqd2x@F=qNq7Vu!8so_SPx&R|U4#@=i1u
z@>{6pUxJQ4W@YcKCB(fpD)_af*~2*m{*gSVc#D{z6Vb%DpBZ~%oe>p2%uHe)bqtii
z;IcHS1At|&R5tYYqpqVz=K6Vyhq9fWk45LSJyGmc5TxE;7OdD*Tv9o_pYK$stZ;Y)
zT3!hGz|KenT1VuB!$S$e;#UFVsH6?02EV_fIhilAgSF*kr#e81uc9M7PMlcCNLwb_
z^G|cUBaFcVqCDmH&yEY8Cr)nVAfAXn^V7?FxID)&&00^3D48CCESbA@fX7C}dOlS8
z8w97T)JrM81h)>{Ayrr4Av6q>r^>3Q_Dw+wl*ZOV*bwmHbT;tXy81~ukm#Uvb=S?l
zgf%NfiOB~REW8O1W$?cJ+_eM_O7FOP@K(Rq1TB@RmjENt;C<J&XM*L?zs;CvgXc;0
z)EP`t(4VUUTP$a6udL{4BM;;%<=8X4Sil1;^mS_L+uP^FG`jp5OoFCZ;uAFv+&s#Q
zOG%y(r4&?`$MlkZ744%rfjHL|vGq^jv}?bI;}2(y_cBS&bdDfzol>{wRHhu5NItxV
z(&Q{;&dc^0liwhmv|OQqB=QU(ukjXL%*>@$qnx}wMXZ*98(Z7ThDZnZu~mH@+WUzm
zAg5cOM{fK>!j4?fs*D89P!^#ZYI<E`?6+=(JnzG4^O)W#fmn&H@_W|DiRcYyje3tp
zBzkT2s-tX4R8=DIgXPCE7GN|^N~%c-{J=RC%+jf$^ZA<hr0F!0wd3yM4yK4BozCRP
zDC|*2*%ykLX-5j*=+0>mCEBc2dG3zDwo=!$a0$!ZD)9!99dxv3b3_!T#33N>XRQbd
z2J!yK6Ijrn^=wSh<sZ?@hlxq9_Zejbsm-oyHB#fhYC=HpuFs%PQ;!8hO^w2yTKs{L
z2^(Mx)dSir#X<fGwT&@lFiLv?W9u7#^i1o-y=$##-9mbhG_AUF%LS!0lue@(FD=Xn
zCT@rI7LdB?2J!!pRX!r(z7xZ3mD*x2cTlkDOLj)-BJI|lt=$Zc8+{vKZwb&5d9QzS
z9S6#4COoPQ9KiwUAwksiOB2XWnnzaz`gYGau7dL!xNqoN7pfsgEdimU(k%xjPw+)I
z;-v+u5UN>R1YfXW%yDuTJ;N1b3&*VD_8vj94Ri8~Jh269ySv`hFPPs<n)yaDNQRqx
z2+zZ2t{NGRx4BH+lH(2Rk1p8-1r~_pLY}W53t%(-IDHDeIL6z_%MTv>c$+nP{=B|N
z6;S7WYn^1U=-g3@HCfL_8<DC})qF;N;S>`~m)9}!<b3$!Sc;eET#cC(BZ>2)jI6>r
z6Acfh4ig#ohUOKit&OoUtRA>|JXJ5KOEj??arFI3ccsNphTWWry(M%w+|ik1X=$4}
z8zD`VWMV9O<&URmG)-=#Mfu1Y=1}5jx1)zB><KGfINgHu2>D;-vY>~T@_EJ;gL<kh
zMrqMl6A;B1rEq9fU#_R^@>T<}!SJWR%>OfffYq0Bmt9_}+lz=K(tA3w1;NC@;|UC_
z>BtnIsMX6OBd4?TpQv~&>bAQta|XF`2Ke>ns~kM<dw!tr>cVqD{Oe*t^$0h72mY>)
zD&<lS8#6R1F6ccI%O0l<Q4eGFCtJ=Vv1V8KF@!0@aRggJnhJmE1$feKuNXl~6!Uv$
z1E~dktNU0|rv+bOznyXH-iTtH3*-@S@$IiQUo}S(Z>gUpNEG(h#&&BJ<LOI$XcF%4
zGVBr=$J;m2j@KmX2h>(1bj+QqA7Ux(iJ*sYd-8XVEZ7Pi;a2fx1;JN44;B(V&eG(V
zfgkK>ncw47&U`U&r>%^Jq6gu<T*kixNPnCLtX`A96Z;~2h@@pfhUGwoq8}iYwY^L{
z91yjR#7UCk3}QgM%QbaNb)<I8!Ylc~75(ygO$bB;kUWYjEeP7yA@D{Zl1=fm&wcRO
z-%2?6_R=1$YIj##JhL-|`(K!beTuE|ba99K&xH)%nI-qgg{X_FHXUNg${omQWx?gN
zdR>ownl`+f#P+O738D^qskCds(VAj*A>?r$Yt_IVxD%#G>*t#YAmWa(7KG8TP;=Rf
zraqzg|J7h)OW}g{*hVhmBCw|3l76wr;5&dzrc8*b{Gks^Rt#_a{Q?OHnQgnx3l^0)
zS~k1Uw}svDm>9*Gy**GBEqIwCYm#o<I_zgnpTNQEg+k0jT3&EQzqmd2>Pv*&CHZC4
z9EUT!J{^4nxg(|D6syL(RLG}tvO=wN%IPYchL?cntsv_bsTNBETQ3l%)qUbls{Zw)
zuUgHYeoiZjS~$lRjke-)c9U510z^lw=aLJZy3Y+8YfQG|oE~dvc2y0~7)Olv`O`)_
zQkQ3RU9*sj4UhoQZz?UzolZQNAV}_DO3y@QCX{4}gv~Ir?et&4O=?^e6Pwj8SN)$1
zw!uTAE+%z%37Gmm0uC{^LYY59<`usNotE|A4G#mQ(xoskA#1N@@EvewjON6VgtE5#
z3|MsFmU$?Uz{3n7W|5CJ!D<~M;6(c#JZ0|goHr5IcCMdCP}@uidd|j1gO3t1``1S`
zrj#}j*pH;}^JTkbfcoGQ;G0*AY$EvaN65;n!Du1OPUMn00rlOly=<fy6EV=?(LnNL
zXk)5^^smok#&$Zpcqz*Ip65(s`rR_<y=JAph5mjjE?0-piIrTidw4D+ebYP5m;;H@
z+y-2JTWi4Y^rIa4fqL-R;&m+-rs93$SARjE$zdBA7fmCy9}jCp4im3DDpx0Xoe1Sw
z(1?s(8{olCKz!AOXe1P?+>40M_vx%Typk$S_|y~NpXhonsC%8}5n02QxaH`SLV&*T
z(<$HubqJ*LIL#_1!%M_yLevng5QOSt>CT8=gAZtu#<0=?DZbFzxEzI-v4T~^81d~B
z9SO=y<!JR^pp}Y^?YBo^159fo$8xhERA*)#>8U*tfPQ<joop{8pMoTJme_5i9TFwA
zXCChGKeH<VE38s_5Df{9povqBE`f=$Q1p8YI3<t=Mq+ji4rZO=&*T64$bvjKI7e5_
zV>ZDH#jW2KO7-@Uxj0+*<GI!U8T+20>BNM;9JnTFO^5maVW~7k=~~RDeB%FXrybGL
z{O5}201<98JhoQ@qbE5ucv?-IjR=lCE0ENTN@~`;xkfR!51F|`?M7hMOQ#T;FrYo3
z#^Tu10NkGkx~a1;aO2T3JnTpKlIar!8}WxEv5mpp`Iw3-d^D0P;QcYKmRUU*#m2B~
zd`<JZtC`>y>1}9*W!ZK*;<ksu_h%&KZbBhx&_WP0d^~UcCWs@c#}t8yJ8;BwsK8%1
z=s&uWck_vs3oKfa!~WbKLGj9wo)t?I^eRXcws=iGIXI=L!Q&{okIMC&P+}UN%p@wz
zTP{d-_NNGb{+lfju25186hc2HtDIn~{VPRF6jq#59NW?ImUm*35S$Vi=G|e#w6}SN
zD7<CB?mUebQC<w*VV2Iwm+aGx16Db{qucC`{ytj>dwPnjQ$_(#Fr(Ys&(fcmPQvS5
z8cdKA^{I7Rb;Ct|*7bPiYN>PJNLhjZpA5$KoYuD7*377-rN{lG7cw^$>(QCKw&KQ)
zLPAHCjzQE_t;10RE1fKp4R-+Ikf;V$3$YT*aurF{6qCKd>~@h4bAbrt?~SCHT+&QD
z<2x*0K>%%JNwAQ7E#-~V(J|mdFxwoi2f}-{xIBn9_VP-yH#BZ_L-d+l6k6bTC+v5T
zA&cR)nXHCi^p|u_srFNTVw+6gX6rI5cCl7sM+ZE+1`-XtS$KtM=@-4I2&o`AYCFU+
z_i2w>!K`5~j)xI1S4~FBQRh^no_G(RUj1*pk<r~ibb=9K`y1vLSz%p@IW3qr{<;n=
zN}`iJ5<A8BswwMW=GD5;8_5l{Dv<|&|5r&SW0Q2Er_sZW&V35T)}IR%;PYE+U<V+a
z*t0m#BU9WSWD$-L^wzm#Xq$toK#{da$BsIX$b+iY9}p@;x8C6O=oU55NId)F5bWa^
z?}{NaUU(}Li|sy?NEgYvIqCFEXgl*&@--WdyP}cDXgo}GPpxix<=vVLqmUC-+F=^*
zlNS4gyf5@&LD4`*sjXyjFFn9O!%+4Rt-hF`B$rQem~`6&nhSA;j7AIJwcfXn&z;IW
z@Y8_lhG^a32nkw3djAE>nbk4)3c*R%eGQG<@yxdG0C3SqY6Ua-6pWQNO(~v>^ju|B
z*|`fif5fm$tisalBG(K&gj=ADG{GnZ3wsW=(9F3g&xX@abFx|WVh%+9XZ70f7Z?Mo
zx|XePaL_f}<@B5MN2Np93{uVmmR)E@-_`)of`yx~jEvro$SJF8!TTzY+xciS$1u`e
z8%V%kb%_cgB;4Z!OTi7IukpG0!8kt&EdD8pG9iM_bD-J|VPU<%CHQ~eyb(5(4U3S6
z0)3irsgDMEhN@_z!AVdHZ!D$s>@=xCcp0Jr09LZ!ZYoE|(yK3$<`qyGgy^f+utmUT
zK+*k|%}yGHF5t^gP7`c!W->CpX#q7?Ov_2j!^6^u+~}A|MWY58eHk%pCzy#bnm@->
zL8v&A@4l}NXk+wFCYD821oD}#w9TMs?V&HQ&P(uqwBU8$SZ9Ald$N6*g?<(cbs?jH
zgzG`bH3i|46LvAPD0^rGR@#i)9^lsXDX}QzFh8INgS4FddJWKVH~c;mE^1nN!G*(E
z%HD<WXO0h`oKK*S^aP;Z>?sYP+>VXU!orL--#z1GxoaK~^75>?>d|PzW*?Y4@>{R^
zlY=lZy!5~+H?L41TbY6u39z53#T5iMZ+CLN*<UB#gWFNfgJjnaX$&Ziga%A6LSEIW
z57|2Ntg_o&h4}Sr?vdICC;XJ~lkto~AL(Xvu|h6Mx&if7JB8j8D1YMoTnO^d&pKn*
zKZCI~HFy{#!`F#1iEsnLq~X3IQJHJJyQx|XiPJD;UHd7-^95w~TeNx%;Hw<*3dS;^
z@<N*u?r&w;m=J_@9>sgbPX+jSl$IlOiOlCPZaI$^k0+JhOIHr?%d9lvLfiK|!Bn<u
z(j~<CNTaZ~|2;daGuPvZx@W(g8QEle9I8>7@wX%jR6Z2;X~cJW<N)XRgMkt^B-DHR
zk3@lA2yHdXU^{_v37ERZcw5DAg>c%pM*B1gv%*?~U8H-@vMZ!q$dO<bBa^zgr-=Gf
zr}LKHODOnfy2#?>=?D*E2z8;pP&Z)6S3keE67{eLFD0*-Kq&X2J_yiyOwM@=PD%_k
zRK5(0uH<tm_6@K=gbu_{NQ5btBVmcdl~Oh2GrN8EN>)e*2S5R_liKppcn_+vBy@Ib
z8R0Kz=mToEqI;sUNcMnRJ^rSF%F091hvtNttAzzc{}kB2k#1e`&c4RtChF0wrx<?V
z<mis14DG(+bksacC~SF3l@D-)8icBC;8``Z@;Ibt-(PS{RoDCmsOE3tIjC-_>}TKj
z9^MHrE9V*yFMc(qDm?`|$w78aLir~grnI5>YRlw9^TQLAwiQg<X<M&LbDZ6sWRJCa
zy&7GmDp>{R)R^GV%IBn*S95q;aKn)fxf{g3nskxhFE&Cy#jP-@hj*^MO7A;+xu71i
z((r&qG&<9k^asKXXyz2(`kE{Pv)9FK>9Pur97N`k$b5+Fz}msVi;KX3--C*73b?XJ
z=<`T=4A-jE=}D%%*mvXdr>-LxVld@qi(|}`t*^TJc(R?>NGdu6qnQ2OYz3BA0y$5l
z{0U@dV*$ObT(%YMf9ks;#*B2_C?V%fd&J^R0MZw>$D%j}`odH$_iW>NX(x+63o8O4
zZARSV#uFkZKj+Pqu3XCaAWsMnEquZOWOxYwoy*orqZ|O$lB(}|&52PqZGa=NSD~3-
z?#5rj9{956;nrq^ak}+$PGu$f79@v7*sIZLu97Ay6N)uhUaOz();D)~fu_T2T$qgW
zMJ#j?x_Qy2GY<@X<+|l!x7M~M`H{ZiR<qQvGSMIVqN4hcMpGfi4=oNYb*N~6Im>Ld
zNPo7@N0g&dpdZI3?`7$2vx?!|I17&HtK#en=Czt9eY>whxaMIw6A7Q2dR*%td~i+|
zxywNw&Fke|SkDk_AX<UKCG@4Z1Q7l$KsDaqPE}4vr>Y3-Y^m8wZiY2@JY6rVSnTdh
z(G0Mx$UO)U%n*(%*fZ$c8h!<k6xBE{A9~Q858NBB*;=v>OQDqoIG==nM1|ktw1HUV
zjZM~HCJ-NAp|3Hl^!A&p%fw>{fJC1k?to93n)>p~+U6Sm-A(WHG9f@&smIlUMq`kW
zcGBwrTVh73t;<*R5v%L}&3h7ohF`P9oy!cVU`~&vn!oJD#yG3}YjlPP-shgQo|M;h
zVB$TNw`}b|@2Ukl#vub39hOu1*(Y4PEIvWh%RtLT+iK!lhX6V=*OYsysQ!(|PP->;
zG28J@uY@vRmjYFWaEB0RR7XAL-4mGP08XgXnVbY;7pX3w>-79Fh-g(peg5Z7eRI9P
zeGE6$Eg)s*fTQt0EQM^$mdt>D5t%wF93;PzI_#C9#L$6{ad)r{%oJ)4J0}GJ_!r6+
z_vR>WQoCcg>;pKTO6)gaX6~e++aN}aZ)(lkL(*dJ2wf)Vgc6d(@}<S{*)6#yRzy?J
zBHOHEHDnQHea@`Nc&t{v?$-C*vK^WZO8L?*Ahn&>ra(i-mx&c_^FN?|kA@J>Do-5a
zZ)@-5+>;>Q9xPcA!s?AW=;wrA+c04|Iw?wJ2N^Q@T|{lCr-CKm{h$-y5@&*FS7fbd
z!Zj0o6j>S(<Kf!Y#19mAAebU^4T)Pg!v+v=525);qhPAAXf)w5I%3FF4wP(g4Z8OC
z5paN^1Ja2^sBths&e8J2TE7o_N;YSg+Q@(oHQI7`Lnq?~5fp3FMM$?ct%V$8(h7M;
zkA&1Cx%roFwIo1I;Az2ZYqT`OOyZBv#B@#!a#dV0aa(S0xUfDx0My#IHHp4U1FbgP
zRSQkE*pu~%eXOi>6kbiz-=LMU2Dv|ZoFVL%f{jo&IL<8U1Tnq4Q)WWQ3Z|p2%xPft
z4dcw~9*_70;T1|E22F1Jl!%=EJmGaGYvX`Fk#P?Hl~SJFw1VC+N=He~g#3+haxKG2
z`TuGwr0k{$ltm6QO|9fK2MLqsBq{&0fVjKv`yWNcK13Oy)xwa%Q?(KbnRWF$?sh!;
zyx)Vy;QM5ZAqMk;F)7l*g2Kv1mU!Ea`Zz?j)j~m-0_~tt8IdcMw8sp4KiZA}y6sn5
z!VJ-5SM&BtD9syVj`I<<6GO_4LZ|S)v`+l}EO3Mwh&jT*S$Y6Jl9aEK;}SlY6-9Z}
zFCc9Yo4vA$Av;S~e4}!FMP`&<^Y+n$6cWtTXLyf8aiS>-km<9I4aR6bAgE<GBV#^E
z<-vbd{0yIZ5DRl%2ZDNj*s_<QEdoelQM&bx)e^9Nx8v?SWXVWSkU8)L_;sloMT#5~
z_e`x51%5}KQL^vr8}O;>%rbu}V3$k`K%}G5#e`epne!F(OM=9XArQ+wrI}Q$%3YW(
zr$KwIdj#Jba-veI=UGCcQ{f3Vztt|!-dq42K9RRo&%&F11Zc2HhylYLTPm1B<_ZO=
z&^c$K9j{ivnRb^L*jtF$R5P4<GToQ<%?y;2JP!AyK~j%!w`7v`9J?umnjC_nwcyu7
zJJY>rVctz5U=2xra!TqTLh#)I!4^y0CH`;(4c~ZR=nIuO+XhRlJ8j=f(mng5YvD0S
z<D6=8e+WRKGy~qsmp)}Pt6N?dAGSTgum%$A^_uUE{|w^R2_60T|5$HZohp3x3BLsE
zdArsK(ya5`?pk)g22b#!WiVTpfdo8=@~?nMH|M7#f|In4XM5IVPAIu`Wn`6GFRSlV
zatTXW&SppcxmB}uOajsT^}J_94Z7;gTNHp=jwRW!uD=-yk%U0^ECs$}BG8aUfb(h{
zz3k5K&s=MavCZWP;W#CvR?!KDb#?FUJ~d?c4f2_X*a4u$mtL)jaM<X{6NLnOQ}~nB
zEoLQ<nYrU1Xl3K`sD9h%KB1;l%@>cY%v)WszRmE9LQPk%b*>WIKO&Ph0Cz_Xu677u
z1IeR&+)Nrdps@TITWqJe5?zx?U!C^o=lzJlZkv5UQ$TK~hf`tX^c!e^1>vfrP24@_
zC?R5r-())Omk`GpmNj-&IA$AvUU`R*ZK|+OER@;7@#(JzMZOj#4}`&Va3TQ9<wQNC
z#<ZdiVkphX56>IlZVghbii>}0M4mwJvB&ve_is8yy0j>g%bz&?@XozRSjqnb)c{)j
zI2y1ZD++=f@Dfj9F6GJBe7W`BoADwCEgw)4WJPy$^mN6v_dAO)c!v5qNDIM~%-8|b
zt04p;s@me&Y3K-jAXk?s5FiulzvqtfA22a*vp7Px7yjL>qtVpFp3LXgO#6#97_F|Q
zW_6%y@qN=X_$Gfa;z3mk+MpM)`0CiGo{Yz}^#LK=>B|NbPao6P3|Kip@1B>g%?6&;
zsoVcm15RriDV=%c4hPq{B6JABuT$rwCm*doa_F>JskC9FJmjLONran~4_|S`vL4}{
zFcBZA)@wF;n6os{{Gk}rHv%U+tkMKpY?ZK8BV=s3MS_u8sJg<wyvoRcE7W&W@bHtQ
zI#FL4L^KZJN&V(n|3pRc`=U8cS3ZMN%rVD+Bo=yn5leI87rSh?B;kf&s+c!K#`6c@
z<|iT(>M_U1ll}RiveyD}H5N^nAW=Lo26lh_-eRA1PEvYeF%i}#H0bLi4C7o~<<4!w
zV|n384j+X=u?2%;F_$L!AT?80)eHm$YxqG}&JY8s&ryboZfi225D;yfd(lOI{pO&w
zUe@v5Uk6M9TyWj=fc)(cnIl|Ud;UQ{l!S`F7)KKM60p7spdDN$+G^dFFx5{$<~uS^
z8N94yag0<_^^;=oY8A-S{B(>TG=sSoMVuS66MUw`ToG-zGqthzTaBzojo)Gr3ke>=
z;G1~P(E)wW6M}+*Vw$;uvz{CCg;<K8h06My!fA=%=fd>9bnTt~F>)xB+@KMyv}v9m
zVXtRef7c4<m(xX0%zS$HUNP#W+3GS5BYG%4;Sl(Q+w5#?<9TG5`#w9kS?e6%-M|D(
zA06ee10TwB+JM;AOqx_r{bZ2Z(}KGjF-%Cjsi*_8<9hd?M65JT0PE@xmi7K%lWch2
z(WbWU=%6<LRJG0a0vR0??&Z<K#pM9m*Cv)6Jod3bkQzGxg_vxeTQ%o38MjKF_D&<~
zPPqJHb-bqPT6vUC-u+Ny)O6yZ6D>kH;C&AN79>*Rrz5tDH~m=4F1HNcxy*dx+XbCB
z2<nV0ukYQoZlDg&#vVl<#5|vG)z&Bb@0+6e*s2!>mcZwV?4NApMl{p5`OfaivBhjx
zkyAL2JNwe<x3jxd&eTlk*FBZn$VV3s{G4)PrG5hCq>qTuLs)eEfc`#-P!jcNrLNLM
zC@Nd2%@lL6>)RNw=$l9jF`C2oShThN^(&}gAW7Y=-_}Cj-)WX3`u`zOG_0|V8=|8=
zu}i`DdE|@3QQEfnI%8?VixoD9puk|Bz8cF+eTZ~E6Hw8j)SoA!-2LXJ?v;OM$&6$U
z@6@RW?mkq=a7Ch}mz`i6JIsUKiG$CTQj;}u$+LTEE)v}1z;Ru62hhb(>3viQXViOL
z-tJ}u#jJ$a+YcPFBfj{mSa8HXduFHY=B5iXOXN9vGzRxNcXOsx1{@rifQD1?3wg3h
zd+}E>FFIhWepXpW;6Lg^%i$bnL}+zxG-i}`h8_OaSRx40Aeup-w18Zq++tfs8YE@`
z!W@{Z{H&_dxc_X`v$A;KyM2fk2j|gEG5tppB`FWe-dSFC<N_yx{gtFdUn$mh+}RYW
zqJW#CJ>r<>qY(f7>U~{L@U;PsUu+e;3dZscj^{ch(_v_R9PuJ?Ise9tbCXSJ-5pbX
zDZ;D^y?#i>(<+MNN2$K>4%hO2(O^FB#f(+}20rNZT^v3LM3)VSU5VSGTfcP*i$&7x
z$Ux7Zx_*TFCWZ8LR#zhU%8z&Lf}7-Y<2PPyb$y9dw|A8Bk&eDW<(~!>WeQF~wh8Cp
z7;9s|lEOqceRj)~wGdqcTmZ?oC{yzN+n?fyfpa72hir4NJFK1T9Hd~L-vl7V7w*hq
zD|-%d*8#$LF$`7$Xuvd2b#Rbx@{|Id>D%|c^Hl`FY@+Dy&lTFU7ni~1WjSN8y0gJ9
zlB_thJ{{dsV7b+97Z!C<H;euu|EI9#p#gvM0N=U<2%I!!MZyzRvbzWi>GO22)Q|v+
z%Lh!744t-4%U6U!W7cQ%QvpnBBE7U-$!XPjwPB(jhak?N95;W;#JvR<*oyIv2x<k8
z>VgvzU-y!MtvuqID_2<PWXJS84hg~g@)|)p%s%AG3a>Q;@YQ+OLf$|9Gltzgou-f(
zP@(Y2Vti2GvpF>o2=w+NAx1teqoiZ4GKW+;Ke@bxaIKmuP1s*b=SRhhMT_KT8H0F9
z-o&Ft72XpK&}aaUy!#VeMy*#+w~QyZ<;Lzyc2rtoubEOzU;DPtrxn#=fP7MjTOVbU
z57sf4mB}b}G*Fx^!~tdD|FI%iv0v~Cx_H2T+*D`JGsyuSlCmlyRGvAIIg?26!(8W9
zUIOMz`J(5QghOorF=%)Pi{U5d|M$|zK9y&trU|*YNgjNUCh~K#fPdi|ZZn6BKciIy
zlF0~A1Ub~wWgy{`A+-4trfCBaUp`cZOBeM4+T6>7^J=rJ%k7Kz4HJyNGwBt>1|jYg
zP;egu{>82Sr;bK1LPBR{gZk4Kq`AB#E~9XWak{E>$>){2wb<FE8_qzGU!e{y7fX6?
ztyC?pVv%oRQtM>|RY3@5ZnKE)%P1)FF?wRPDzpcY`ovz`nivMGX_*@abfgb-bDuW(
zL^G%)KS(PTL&6-pN)V{J59lRM-|N$z+4o+|XKjo_Do%_c-s;L7&H=e<@J+i0pPPGc
z+(xq#I6N_~?;LY~H+F~2U;`$g9jlJW=(B!hMKK1{0xGNSh~9NAUsr^ETx`?C-8(?L
z!3qqHL<c(&zPhqn0bivSI}r`Ve5;o3%{cl{Vm=c(iV|b2##2~o3Sub;tbck!lKBr=
zJokT!QQ0Qa=#YmuKb8PfxyLM+JR+%rjHZS%DlDWx^od@T#1JCX*HQ=@p%9FFeSsZ^
zxv(?IBVf3wojz7j=^J;vAUtBzh0&g7Z;F{IG@<pwbllrz;nr#<@gym=a{^6X*r9N~
zd`J!%Ub%QL)=?P0%{khpx3VkbV&$L~FY$N>-j_SZZiMPw9}Pgwhh0G3*u#jYXbR62
z`l80b5BAj|;qeI(^Rz_HsVz{#a@AD~l9a!YSCR{%AlNf(NrLjAaX<`21#crGYa2n(
z9eCar75|yqM9!IpVwg)}^Qr$nCLIDN^52udQZmkI!udwoScEJtk`!zk@$6h8znAD`
za&tS^-&$yT*NR)K2RjWV46JWHSK@@6@P!iP_S^*%O~IN~2`}$U`2xYE-$bYA`#_A3
zZ^~gH{K-EJ!6Hfq$&GWrSXQF3gfYJ0pUy)gOPcJxAj!415U0K=s79o6)gk(0BC-Dt
zhbupYsW4WIx2?ze2h!Lfz9p#;_Pxx$D23T=9l?!HPRxoLed3cC%hgoo!SOd7qmxZa
zPs7%CCR!MuA6pfhMVY8ya}T!HL^oS?M{or~%Q&Iwrk5S4-K>Hqn|!I9s5m%$3I7t;
z&rZlM51dCgjMW>O{hc3QxaAWT#$9n0P{r!Jkopct!IQ_S)s!`VS+fey1b@j7k!~{z
zZL918Jq@k<Ms?AN)pB|H1WbAjwx<C!TBT5$WlY-V+88!&pt{~CG1mwIxgts&u%+W@
z`9)}!wB#>zR5qDXPWo$oW6<##+AJHSzpA%wWra~l$euPaKfEz{+hHjKrP4!KIRfI^
zk!iz)%G8r5Vf}<!0`AJ)b~ZEJ6Nr}=XhID-C%J0$fG)Kn8SFsF<6j(Xd``XzZmPe!
zAu`6P>1h_!Eo6%2iw&bU!l^_l<uHJt4w2HY%d1()(LY2YL8UjYhRKDw;=M?{p)X&t
z;)Sv@X1@Y!0u3gHaFe5?k{b-Mn_9R*<X|caOOFiCs)XvMjX%1no9XMThRi}O=~LEC
z@<d2&Yg;JQIK*9>tja4jYUJE8o48%UR}7LeFrr(=m-{e*)w9KZhn@F9@_D*|@YnNx
zKn975Cwqq%zTeJ;HwqnCLFjXS^B^LaC|#BUrVp2So?trVR>@COru1Fznov3mqvLNr
zv8KJdCUvB?Q{$LP|MYRlVh<^db?fmIW$@%s)l&7}3J=!oRK#b5<#l2X!Z>BgB(If0
zxYCW7Z(mO-WE(+wvZow~!~hB+k~r?c!xX?yk<xeueU$OiG8tR<l9=Ojq3K3N#Rvhe
z_Y~d^r}wb^H{B>PyB}=Phh`KZ8{lFuKFr%r?$`82Lsk;h)5tv(3ny*ZDmJ-!$I~EZ
zM=w>!Yv%3#LRI4U;Vv->&rlmdW++KwvplsQ4}0lv)uSUMeNbTn5@kijwmIcV^BkX^
zDI)PRw~N~h%($uISPFw+ee1h*7QV)47GqHmkod~BC<Q-5>J2_w<}5NJRJ%n4?G(+-
zdeWR|b~bt%&lt6sntSqN2Mxe!D&P6d1`CJ5ASh@Mx;-WGKs<2MqvW+n)LXhr-0u2s
zlI-OQ5ykrFuIh4t6R@!Ej~Hf2H<Pn*w-H4#YA)jOiYlM*Z<uX45q^C6)Z}}b{#X2_
z)^UFmr;+Oeh`s;LXrC;WDazQ-t1kwhVgO1&wZF-L%D>T%Ed(e1`v|`{-<jXSzO#yc
zriaUlAz|Xi&hF*!jzsGyR1L8lAD$jtTU_D9D$IX-^SUm86#FwD{2YcR4wh@}H_W&B
zMPS$H&U6E)<xt4x+V-Vyp+2U@lAAxb9hlg2d;yp9v~`>80OG1}2!bu_qU6GzyT$NZ
zJGo{_)@s;5|0hCySOFVYZ+GY**YlRAVebR_R+_saM6L{k3ZQq_bFJ+gho~{rfD(&c
zb;$Qa;MQ@QnHK=xZ^KNorz|K-2#me25a*MmCbPd=++hR$weafh_H@zt>`i<!1$EDG
zQR>_>O++^5xW{VPAc-#Rrj=7Z%{|0L|AB!S2p@CjC$}@3Z7|1I$|O9qboM4#D@kf0
zG0=G;Ml`0yXKyPA5xWH5<sEYmS`iu(`p&{$`Vn_yn^fH<)TJT{gDOU{6>JBO4LHRC
za5*FpLrP@sQ~W;-c?i|jKQoq>ah7#r69fn>*02nO628tW8n`(pt_Q{b!bw>`A51aF
z!%&#y!FX*l>D+sFvY?-tMCtBT$m{6mPKpHvXq=yH79j+-F3&Cz2H0d+22|W1CTJu%
z(n#oMh8ig}B}qwUkMhp!H?b~q)daNcYgA}6pkkAF)kFx)XfHnZOz6az3Mwv=>C{Ob
zlG`{_QNEHv+MA<_$TddSc{9X@lLfL7rd0(YO^3<m2Z}<)te%`LZC2$zm_bz9twJJF
zje4-$Yb1F&%?hfCqbB7HuAJUp_Jp7oS7VOMA}~^JjXg<vanR6V7{^FR^nwOdc<YaZ
zQyf4cIN#Ylb)DvzOj9^*(W}t36`5V;B4x&~rD1k}LRWwfAY%-UDyC}jGqb>g=D)D)
z38v}0!5u%)_ws|JL!Ozm;AGNBAio=l95uJ%b@$$b2npy)o5MPTF>d-rp!5lIfnW7@
zXPnh=I}BLi`UE*V#x+1#r|y6C`Dx>c9Y&_#uGx^o3yBA38PMQ_xIBU^c-zdx^%Nbj
zf)=r5aY%Ow<4hd8&GnhDg^#gKB<~bCkjWA(5Swm>h6S4fIL^u$Ieqq1&K&{3Z921U
z!ppzecpggFxt4@MF$<f>etC|u+Y0Gns8jWDds$ES<SQmOYjW9>sJ;lEZC<z*uKr+V
z1pXJA8jvMBEA&%^{u~#dg2~XsQ^+9SP;J`9M%>LCS`kiQ&S7Tdk)uSTqvn^8ZqdJz
zL99nFnHZcU1yg!;AlIX^n|5`PiA<O|5V}ctMh5o4Aua_8?szpli@gfg{SYH@kPp&&
z#}?*w!pi^uNeU!LM2W6-z|fI3Wj?-wKDd4-ckVM_x5mUPC6}P+A)5iAy!C#3*@Z1@
zEx9dF@KW03su>|TH(`ye9)X)4cZ;(eZ;bd>tDFfO{R@Dn$?bs`puFx|JaHEj_q;Zx
zM-;uaIB(B?@pXrADn`S_nalKbw=(yW>SP~WIBm&1;ya)d^@QrkhQMKuIZLcXIO@$n
zXKCdcA`Vhb*2nCHqwg(0<ZIhsU-dbZ0}OD1)lX5hD_CyewGES6ZbZ69@^y~npDM(K
zNn9P){kv3EdPmDZ4|=y43g#W@QrJW!l^BRCmVO}F<`X@lc+KvBcs`lj>P5zE{f)c0
zH5eT(7Ds$*wAuL>*7Qco%A#8)3FD<WV*2+&$iFI<K4QUjt~`DQHTGpsn+|UY-l-_M
zF9R68tn-c?c;KY)K8n&O?YC|{NXzHC{*4oWPJym`3e!vji^gj)GK-iykJzYH-IPPc
zxvxP&?fh9$-Xj$f(q2@7WFiqbwuf)Wv^Qj|SI<;EqU`9R8mF^EFjee~+U@xwNp(*7
z$KqHcQ~Dy#wi#qW>7Nvy=#FM|ZCM<%t_k)EvbkhC@|dI;P9r4Ig6q?Tp7qfq<)F%P
zzJ6!C_IVELMZ|w5f1k=bs)=N~S`5)5tNtgo&0a}z^^Wg$O%+yIwMt@h(yEnDP<})Z
z>yC-n;v9Yw>$k0Cv^t!8rrrGD`jc=Uf1S3+5hJo?cKD4c%NUvU=`9xp?iDpU#*_2N
zbsEar%Sw@oKNLDf$v^C~7g=yHb*5Oz2wNE$BTZIok+(#~ssZ;gw$->zY%<^DT>CLw
zRnE+I6$68tWorU;d-YVl5{99_NXx@UypF6Z!Yh~fC}ZXJ%p%#4Oj9U*1}Lt^<qn*R
zc|Y|*blZ@sdW037l-n5rVHB9|VE0SvX6=8D1qCUF4I9!OV?xR&3G_h4Bt+#w?{aA-
zxZ$fd_+FpUkp_5D@bnh+jbLx#JY>nY8~ylR1mRRLMn@EUl?it+^=TV~bvQYET4s%T
zcIm%+Z&^S)<7&aOe!_+3q15u$uvfIreR7mE^ggD^Fc~kIc(u`%K;zui)N^{pGK|!e
ztH1|3w9jthf(Ex>V~nc`wCFw4=lwgxF*Wp|qGO()@9Kkb?)|X$+j~V$2g8uGvYj#W
zGew$~ONe4`YQF+<3M;0Qfr{lLNybSBnf>*(RQ4oXC)LZm%L^Qr&iheR8uO!2)omI|
zaF^QM5dl>tBQh!|xkVpp_J(6Qp^uMbUT)!^XMaDC#igJkW1@WS5tQL<iulsfl&D#k
zKDjEt4thEGdQ}9}m_-w7S=;?}{EZ4T?9Fopmue!7cPjo7{aiRpBlS5K*!*WX7ho!I
zn%kJQ>F>YrB3zantTAJT1WNu1N#NThDhCc52>k3>b6Vbn3apy`lP<2L-1fNI3RE~x
z<Z)IlUn}mwf@2Pd`-EC)cg9cX`Ayk8g&fp*EK_%eqs>J{JZWfb>ut-hE|MR>;5Ipk
z)|yy22ZDit{@jx?5i>*MLn`z>;f%w|2)U%~4KUuRRMmHn!4=R$zj#H6Y#BNEd#yix
zu6lL0V4iHc%GyvO&*K<tG=@dwIz23iIvZMR@DHl~E8_KrrH3(-LK|K+VPdp^9>_}#
zy1l}q%d4u~$!58BQLgARE_-D}7w?<e?q4UJwOUFvL0-3bUn+us7xI;rL~C$-(_%Be
z|2ESYFyDu4SWF4$$WZ-1Dmu?@tB3zzOxz%KLCI~0DmNoYjB%MQG>2_o*d<sI%iPLA
zG?IFhTJhK)T(TYw%jE=ayg`@@ZPq1xRt@p=et3$FoE%H{IA{Vem!)*sc-~R9leZ^4
z2Kcl6Ec{itdW=h`z3AFKo6_|apL}XX$MtRA-cn`c?EiOQr}5nRdFK?n5=sEl@g$La
zEobA2Ac0AnkYQf<o)i7KX=gRXJnPnN-e2~Z@+I@`)W^422C5#cs@S3#m3i13;9Z5h
zvpT^wqMnKk(ESY7g#mT1GuZ$z?n^9y9}KwS7STS9o)cZ+SvN~h2MwP4o(0e=ht)06
zd8K#cEq+Tb>pPG!>TEdv0~X(g;@?fV%UPa&>O+pa;Rccd+s3{4uOt4LBj2n85~TjC
zw%BMS9ZI#Vk^v1j?=CxfrW^K=usR+lP<>jA2t`G-xlXN3iV)iuvv)6;uKQe2j_zww
za%p{bIHDZW_@$KamH*wmDw1Vkpdjsff9yT3jhSc(Yy5J*sPao_3*gZtG&weIX+n83
zSn_zS@w*hi^lc-gqD4^v4NTpuBvn;mt~m>cr&NS`gn+x*q4mVQ;{NkcF)#ae(3STU
zj7<ya@U01-<LSA{@e3Mz^;;7|1j{ICfU>%MW&waSZMZKgL;8AHPB|E1=gOU!Eu^N|
zWU?x|=2cCzWk`bMsTK5YR+MJ%>)ssZf>D*^`jXtOYj4$8c(+?Cmw*T_N}l|BBXUTv
zj!KQXE-F5lu<W9!w2|Sr5op=_rstbzli%3@KN{}O*f{*ZIQ{y)vVZmY_n(SPVmBe?
zB-aJ4>pW(`ghAt-bAoAKS#j&ULf(ohtmnD<1PiP`iLpNhmWjgh>-nBu*5$BaT2ZZZ
zrck9%P+f8T>NGd#_lDlw2gbW{No#GjI1({&+nWv^FW3<ZeW|mdH-K?Y2JDu*rVQX(
zq|>~bjgIiB!?_)n3}>G|w<C6@8hEZ42Qrdth+6>(e=&=}+`#tsopqyYpC~=tE1m=s
z|K3oJtx!go&w1DM>Ky~@%mM6m*!SBfWV`bFv6|-i<g)i*&lNuB#TxJxice^)^)Lz^
zqgNvbJ((FAHt}i4*C8?%XfiABG*v3JO;n(Tx(24eBoi?i_eEw<XweILb7X2oT^v?=
z6qrZJQ7tti)Mov(^N+jFuUdFgbO((~^i=K#ew|8ZB&`zZ>;VqrG7hNw*hO=1HM^&H
zT;Ac)(lZL__#R3MPGtDb#cSAVD9}c(MV@^W)1mx2*1|qdtZ(e2tPC$fUqbyv&X(R3
zLFPVV=@n_LY>en9RfER*Sp|J=D<d9%DYqph${qq<rF5Ry8Ex(sBB)WBQ;Ti&dE!)O
z>)qmZV>p#9DBf2Xno8kKPm9>MV7`F2^-zmA%9fUuOY7@4!i;TaY*Km9&hH9TC!-$U
z>OtA3xKXwfQ@vpxc0t#*$rn3zO%N{RQx}J2*>(^X-XAK><hj+x(l3D0%i|_os#_b2
zyT}Y02lxb;5ic@7yQ^pokVKR0D>cN~r23mff|Ns;FGKo6-fe2<#3DTcGMsB>*zK(*
z;r!DcSyVPOX1?#yI<Uh_Y+lxtX3xCZj>L2rgknbckBp!ozt%-8k`8~6p(_&B2-h%a
zQ*)%NKANTx#6ad{Zakup+isP2omxi1d>O=RqYFQNh({eYDa;ol;>!XzmumnTM`rSy
zcRB+T9xvYptpmQ-|1kg#+=6Lb@hv4dRx(L8Ib!j~o%d6_qU7j>NT-vfABdU$8g$+?
z6dg#BE0^%;lLFN8cZ}@AF}Y=ruc6V#qAq*r`nAudAWIWJU0WLE0J41cy4-jr0=9Qu
zu^|6z^J8#q%aa!t2}Dw%@fKwidn<yp?G|Pu4%>kx2QGFcch6Z<h**T=S>O7)rw=BY
z{e{G+U~h6Tm)idiIw%HlWdNt6TJDA6i+69P7awaYRH1N{qUAZS>haq_2bLo1^dP;`
zZi3C7m7qhD`|~Ww`h5_B2SsqwL?6lfUijvO{2iK!#<wi>6~BvuNp@(5NLGm{lKYCN
zvS$EshZW^j&mt_NA5Te1i_J<YiEnZu2csIdsI}1nOEX#w|MJj$N2OsPOpr0m2%ekN
z#zZnw>!qS)?6}J_dk9sQi5DSq`5E{4FlUfxRzaC2u2)gH4@eh?c77&Be_}r<^aJ3^
z{&g{^`tKK;l)o|R4WwUU#@11>+?vb~8UuSkt!N2$ts<XDC=JYWGPlbIMqVafv)7&8
zrV}wjg$*867|mE;Z8qD@6slY<hY7Nl-ww9{PPoDU#~p>eJF1F_Qw-Q?ZA*H{{APtt
zo5tS8o=y6MdkkQNPx(<3r*Nl5cbqDKVCetyT~Xc@u13VH0qEcjMKXFoYN0+00h`fL
z)W5qI#so`PcaA|Mm2xUm(+m?xbl%LyDV35US&!{A*E3K|ODleYA_KgO4XcSZk%oC;
zcUMVTYCt0XBnyT1wknZau{htRcIEAVtpWk3CoB5X82}KfoX;V)|F|F)F^^AegS%14
z4n)o%QBbG1#eDR1gM!!H$Wm;Ox?Z;n4<y`VK97HRHxzb#h0Rw9K+hkL;9-hEtqA~s
zJkiiST-)aFqkPudjZzBRM^&lJ(pJn`uRlmt+2fk^Ty?gE5tyS4Gtg-VxB!IiC=`qi
z(w3sVC&5@KfRVjt)YK-Bu;bklY&RE|PN21!P$bOoM%<c1Wg-Jju_O#JHnS7*#%ym-
zL22Ll#Dh0ju&?zhr<HAPU}O$p6*6d_1xI3tPV-(2PKXta%cGxo+=?56k{s?HR)(6w
zwJdNs^+xl!`Wg+VAs_7vNls-8${)@&^q;S3I!lGaCc;@}LR#L&SlBY^#ZKRc9cA!N
zBBZ+J#WJfkdo*$hJT`xF1A#-?`tZU_OSwz;dLM>R*HjA541v)16&o!)%VOu5D3;>2
zpgqG#fShEw^gaUe@!@FRN0Vv9pP~=j2T$VWA4Rvw#@aWd%lKA`dZjs&z#zY(@LRsA
zLF?b#Zwn*4L__A&t2|V-m0X&=?IVHj3n$PxM$_97S*t(KQwY=4)pLYT_&v)qBCf<4
z-{)n!9Rs&H9huv}^L7qLBY0Iiqa@_b%jNJv5|0Ob?ivn%Z|=&XOGDxHnsLvoeaNMD
z=@(UYl`Bjk3Tr~I`%D=2-d7bx-KP)klTEc;9hEj6%5{K6E>mMU8~Y-*pJT!bL%rxk
zr`G<i&kS&d<&JGX?AbZI>ZaoqrqMv*%gP8bbHU#AFrv<)b#2#h4?cnrutH@n-x={Q
z{_nNHJum6624M6A2%I5mZ&lhLh(BjgyR7No!*R68Pr{H0n+wz7aYYhIrD%bpd?`CP
z9LUEdnM`AdRc+@-sPf}Yr85*b`{-GF4E@?oEZw5;VxG1Kg=G<P&@W@d%V*d3hFQXg
zR0s8rm|`;%Tf%|(8N$0n$PB|us!zRnkK(TwrsWco_i$ts09ALv<fVW&CUQJUuB1V5
zLe0ES=@dtMoDJvV;Pr<6IqhMi?KX9cR8|9tOpC;Wfjw(<GB?vY4J(geHqz0Cf)wJo
zDhe@ws-t&t<!Q1AsCG1wb|oHOTO~UxB0Utq<v13vpf858#NX)k`wXn%^FSJ;KfT&i
zY>uoV9PaTQg+?C(9b<M$p}aTtSSWQE*t}J<b{kXSriU}=kU85!q}~aECpXpp4eP_H
zYTd|l6?E%ROm#*GAJ6G&(8%!x<$9*@Z4vX;{WZTU8vm@)`K<=tMun2J0go5s-Ltuv
z;c#6(%%+}eP=i<Ji7{-mHnPKWU$NBIT6=B>H!bQD%v^b1u@9We42yY`iZu6tqn4^z
zVJjNZm9<7tK0i0U)nB{%1XT(cea~MeV3!wESMgKUanU~iSzeCee8mO_RF3WimVams
zfW~LIWU-;V63gS#Tz}iuR1GnrwF&6SxWCYM2Wj{Mrd^zVj$&w#PZ1MTSL0FN?87)V
zkE`<j-bXWd4sxC$P{obU3)SI&GGa3pI0nIjgSpG*zF|a^pZj`M9_nIwZU-~pVMkA^
zKFt6<m@~gW+wR*<yz&GJt+LJG>tbe*KGe5BNE8)j(QxY`3eVq)a!k#0N*1T@&b73H
z;(hef3LGlqPfV#C>MAALXEAP7m91u6cXv_20B$dZiVhFMz^twe{={Ra^ojSsR)U)*
zNG#rECi131*?bBXeg7;R3oZY|Zj%mX9UK_K37%#s8Mi?*<QU?T6}cnq0>f{~`(^DP
z$#YqT_ee6iIAK&_r6<gf+C-nSy1OvP0@J)tt2Y(}%laPl9v^{+u~6xe>4s^>aC=c>
zSU#R#)<<R!Uepu;CQaqGV-2MQBQTrHFy`seaX&jpfaoy=2_uDjE8nZ6c?t*NXqk^U
zpuH+!`t;#(C*tPhEcec`7(HI1Dr+6?t<{&)*RS!QUb*1x$C%Oyp<|N`_S-0Z7Nv^x
z2GrV-9lgvK=A%UAzb5HPBa!G|Lt@*|;iTF)W)(uCseLieW~L<^G`aM!cOI>ee;-sZ
zbO~I$sBD_<@TifA!oBH+NjQDMpz4~Ix=T2+<jgHkzw4MypiB7>GD6shpvU>@lUYZ|
z-ZSl5lNodCa)b5C$m#L{LGB>*N;1uWbw{c~zld~I1=~a_Kod@<6+eI7nQCUikbsRL
zQl&T~kQ3<dLse_^%NN%7Xh)XH1*3T(D1LpQnpp<g!}i?Ld4+vt!C;0%mtMG>HCaFG
zdpiHF_SNd>QJ;SNG;D>y4kR)4m1ZxxYkaO4krh)b9W4bp%Sh&3bO%6F>y;tSSNexQ
zD(&WlpVl2W`VD;(1zYjc)M-jayy!-rwIF4hOboJoS|cGQpS}w8)A4|>XkPRj(52zB
zghsnd9gA5e@um~&yi!_(e|M!BB-jPNLRmKBzrm>#ac!X4j#wZBw=9uJW|)VwWS^(v
zF)<C>L?A<t2?#W^sF5cvOf&1;v^S)(L3M)!%>TV3nS4qKnM>Fh3m-`ZnFZ(f`OWv^
zO#m`M_+x{=vH)c;vkV0H;x(#t{0aiOvgfRg%mHil=_P5U5`o#$?Gr2HE!Gp><%TB2
z#)&unQ=*22swQUrSl7nI%#uY3rIw4m>(!C^O~sUM-W^9c@JJCJHo}AM+%(XzMQN`_
zo;qspXWrrdMT&Or&^c4%9WEIy411OejcL?8`!|1(C8+Ib1wO@T56f3q?>&C2$&7hT
zO7eDk$EH~%na$GvPkxE*jW>yO-i_ZS0j`-C#dFd0usV|nE_n#n^2)NcW<bEKnxZG@
znv1K3<IM$&@{%tC;51RZInov)s&)V}y!M=sLDWwaM4a*7sr+p_$P{L(9~*S^uo6k;
z8FCt1z-t;1chYG^506wm|M0WvR3<>9wWQhuRwZ!N>NPdyWX>HJ(;%E-M5E=6Un{~y
zmv_7Rl@MX|Ruox!Yb89}&?@`Q=4P9I=wlH6JKol&WzUNS&yf5Sl1kU0xE`X_C$`6>
zOh-lv{@vLdI@<xQoB!$1kPGmq4w1A=;gM{rlxM8$7O%qd(w{+(OHl0tE0o8$2~TEX
zk(Z4R5z}lB!9Q%KW$4boNA+1+^mm@^h5B-jA0aR)^`LGPiHeAqC3BL&U=13d^(DKc
zJ(}s71|_BF%J<*NAvCLmhWYb&@==-IDIvNY4fpR|u;RCd0e7J9!Y?WTCQ6_RIG2}^
z+zqs!bekRq8&Ju)FT5zMLBOP(=AxkAtW%|L`R-x#FZR5NqXhnvW31#~0%hHBvnbt0
zc{N_;B(-pMj5;!T+N6Ji0JNrRrtyOS+T*n!hP51f$7EkZHjz<vIwQKOhRN#kx{nam
zh;h@e%NP+qrTy!Mu-{YTGDEazH`Qd`HpmeYsoN#T!OaKvH5x$AR>-;4<=@bX4~UxY
zzH=BozRSpY{N_4S!$r7U<sCtoO6KAHtp0#}t%$fYRCyrYDxvqS!*~A*g&Fj8Hv)$A
znA~B}0)g_T8Y1&`jEVrPAxF^l2`V*aY70`8?`e+fA|{>4)p6cgi!L|dB*weod}4_1
zt^!??I|W)EtY%&6lPB?<T=N%JTR4uN5j)zeNIe~hOtxC_?f;d{xo3ITXDoFQxo5V4
zFu_|!!+p`VtrJ5kWyh`#Kb-*RC7k^wC$GcwF4VE6+8wxS0$k$@#&3aYJ!E&Wf4n}6
zG9@%`>$*X4HIQBDNseu-)>>M>S8WAjZ7z6KVij{XJ)@sef5IbTq;+lUf0Nt~q+|Nm
z6ElY4%w7LUG7jF)|FGl`T?g6?kV$dw!iY{gQ3;#DrySAFcg^#!f8sH>8v(`X-HwPD
zPq33>1bpjGY)?EXTi$BB26Y!bWhnY{g761xlJvn_**y#9yk*FSe+&yZyEw`o%R{9l
zg=k{oNvA}iQQu>#t<;g3a?jOJk|}=dtQ#cASBC5&^`^s*$6B4lN(dR6vgt>+lm??7
za>Ww8uoTQBG<)J1jG5v9MBQUigNho3y7j-=tPzyT98-7K|3Mf!GE{lYg=Z;g!PVGu
zpDiWE&|_w0KR7@cfpeCkCL;1G1$=b(v>74+0N22$UUQq-cF=?fadbFK<{$zLc_)e*
znbvK^3;2^Ye|6$Vu1P@s5v9Y7gAmD+)?JhvPXUUg+lz)+qt(qF>+L!;>j{>HNd0a(
zt8@=0ttlER$n8^3BfJf&Oww9yCEAFm*TY0@%r!i{_>>=UNWKJzUTUZ?8U}JL@8hK>
z;`#>6ONI>NjL9Jcdd6nA9IMZFc98a?d0#;R%h}|TmRU*+wMYP4RW{@ICd^$TXCTZQ
zrni)ppb_ai{ps~UcxMi}#J;(uOo1;%DtTjg!=26feulQ^1NZM{1rv3_n$OaKyHS|%
zv+mB~VezG(A;zMMDU$V!g1pjhUgEKR7R&A6Xd{ObW~M2xh0>X-7ZEII8YoD4%ytXb
zXvHXtQrW<tt;hr3c{4WX0P#n{8pm|zm_EF8<M8u_dzFvO{k7-wl$Q}>UR;mZ`FBmH
zl#(sc7`~oUbk7&1A~TZt_v6cSm72V*m72c+u(XCwA~K+bpDTYpd*aqyI$r!cvvgxB
zXQ~Ky2e(I?2#jN_b3f4Ib(Nk|S$QlsI=;Cgq$PSumiZP6p(yY>l~5<{+WUIOXnaZ|
zp9||Pt7Go@82!6#!Xko4sGe2%aQ9u(9O5YickJTj(i)W=BVfSlF$?Y3P5kw_NFp|s
zr(Y<T@g^`VHAV~lv9Y3#b7Jm4MnvJtAzvK)pWJQ2w~9$yeU+m`ZLTg%Np>$;COK2+
zj?|I?#6G^hm;69fkWBjnQ>3>X0M7X)<m^p?m!3t*#&C^6b7|Kr#ScYphjcO;NkBYD
zpimdC<)nTDi*{mdwe4o>Uqfa{RIorqXQgpp+QtWol+hJZf!>NFL`dfW(-B?bXXj3U
zzH>n2JREgb)MSJ-p1_7=Y6P}T>moB0tOlG<Jn&{773T3+7EC%*aW$>^m@R?gL<X|h
z|6^Ci!A(rUzKiSEshjwu+rdolD@-ict}yXW70Di|Lo{PJhJ>}s$bi8@iJGo+?K>-V
zcUKEtu~D!FG#=-6SjwPb(m;kUs|r_fV%@EYt7@xaby?w4JATGtaOUCbiTqkp;9qBH
zvYM{HB1%?fXK1Fw4nbI7C>4Q9u_XUc2iw+Pjj3GSldj%;6W)1;&Bg8w`c_fpIX?T)
zoqh#W*XmMwa%U7?|96|BSjWQ@jB05JrSlY0No{`gVOi_v`SNup@)u<%EGseuncJCb
zH*i?|0Zuh)j@O8%((`>zU7SfLBj^umXL-fYJgq5FT7oX7<;5Z@$&+ng3IfZ;tg-#c
zIho~WAR?;zaQXM}T;1v<@~c=d&O{^eI-<twkH|~2<f#-%VtMT(j1reR{L}<SDL}+X
zxk9hDt^AFQFU?$TO?;+5v7oy1YK_G}k}K<pTPD%wJE8YJ@9h1gjIA{WaLH89?XB%g
zD<xLtMRUhcWpon_Xr@~Fo?u13>)0PjT(eaTJw(A4K#Jf~R&BG!L`>yx?g*qdQygit
zIdLgI9CRgvid9Xu(AH54xl>RhpV2J{5Q7leKR-&e=FSMi{~&t?B!N3=mj4&;r$yRe
z#z{yJp_5X&-IA0+Xu}F4YJhwES5?xo6TMRg_Q-bK<Q^!zmFVa>keZEC@BGR5sG0(>
z1DvdRuIj6Aw!z=5v+WHTCHG)(t~o`wlA`z5GQK3YQJ4S;!KAx$Lze#{XrQ$I?_+DK
z($CH+lS)(g?ar$MNpa_yw*K19_3>KrDn_zE!O~UpVb&tCuB;q81*F79JF<`s6m|~W
zS)?_aSoYvPS}`k=y2J@c@90koIb!>=#OiPn3;I~3E4kWlZNOvhXTq2NAvBqmz8z;B
z?&*A`+4d>4IcI~zQmSU@mK9Up_>+ff=cbs4qLpxi#WJ^<^)EXjZKRE>@rV%k6p4`r
z9K?EXTyrA1QF=X9eLRQ|CQBKsbQab}^)WT_;w-r$U}AvouP(wn>`SN_FjpRauA<e$
z{f6PoE~XLvcc8;ZN1$SAZ_+WpBRH}#)QkT)k(vd>2DDK$IWD7J%YhJ-!g8Am{K_uz
zMjFqC+9WXTADH7?#e$|HlG0<FkC;FtL-6rWEs?O0CskiW#5x-dWh&TW-^?vNUOQVN
ztW1Xe`ucc<oJzaj?YowLYUfQH)f}s}m3W!9bH$^{xc&~V@(e=sYpU21zxgyv;o{)a
zla_|jsr8g10XvwLZ1K6gnb8*gFYZJez@DmBC0`eN8L*B4_%9z~<eMg=Z#K{VtblMv
zw^WDX#F*Ih9d{}F`=-b#`A{BRa=BWsnsJ3=aHL*9D8Ws;Iz_?-zPI{E#w#U`o7wo&
zArvquEPD-rqyd(9+>`@()kCnkZ992CtV990tivLy;Q>|$OoG^lh#HS1WlWcH&EFM<
zKN4rJK&-^mUW%n4v8m(>ws`{OjCN?Fne$C|I1O~%rpK5}&J=YsG6?PuHmySz)V=>*
zmUv<R=AzK5vn)6IO33Bddgvvv%yWN6Q}w}^dG!9|dL7&db54?YH^{V7^gn1OJF+%}
zlu{`eQh?dVTGYe7IoiiBoMxN`->IEgWGBv@%h-%xV`<MCwVafZ1k;F`Yw{Tfrl}%E
zRTWTrQ6`W<I5+0DN4WjrF6V5g9;fVfqxi@VVrys}_A&^oT&Ap&ubPlv6!+KDQLQA?
zgLuxj?vZ<+epz9~OSyzGKivs<a06#s)G<;G*yUS@L<J;W(~yByZ;`Y|y0)#GT=GPC
zbDSTGC`4LN9!4yV$L;$N5<DsrkE3_lk!m1sJJ-a{H_L)fVtEl^rSF%2Hx8&-Hj8@-
zxPANxrN5ot5r2<ui@{|Rlk^qm8hd?Xbt>F9Cjww2!oZj1mKvDCljbqE#xsLgC^wle
zSeeXk!8!5`=FN<}Xy<BXjO{dAV;vk-HcSDiqc5^yeJ`{|V!6Rhr+c2tK-&r?ky{I{
zRWV~bt=>g2vCkB~)`+{<u<npiR4Hm|6)|P~uw{+>U%?%+P|im+(#ZEvw&i}Hq`c&p
zlK?o!LnT|9>BxADyeWS-nCv)e2|Va3Hn}NDgpzBX-2v68SKCc|VIFw(G%y9`C^WTo
z<h3~6@7m#*Dj=VecDlKbj_hw`s0x5)>ED;dU4X}mI6<!-wx?F|<<diT(IPi@BG1pY
z&PVc6h<DD4pL;qo2)iU>m8509QU`tuhkxJZWALXG?#v1pFQ25rw(CC;uqAiu%xJ<K
zUt^N*m}Axt#@hzXsnU8Lm@#JfaSr7J%@sY)Dp|tO6`GZKPUEWKecIGxaOg^tJ+sC{
zd5zOF?N)s+M-uZ`I|92Q@_H?&mMkS_%n|$*&KDc6TxQx9P@cZ1Tr)Lt*)9YgJ#&!1
zZgNV)1=XRpmoW!s$VVa%$iu1u7V6>y%rVr%*#NpWw=MLNPMF>{UJ=BnnGO%W?r+Z8
z(ijBEfR0@y1f+O&UEp7Ztn{iy2nR2s$DT0W;i;Zpw$}p5rhVLjqJeEIAF}xD*V#VV
z&7(b5$_NIqy0WC!o>Q@rV|jn;vx6!96{tS4lH;b>$#3AI(5{wQaK6z^>0q^|udh}h
zKg-A-s2)sX;VhO~0Q0b>D+|^*N4<nz4JFXCA$gbejESIRxT<Dg4Iqxd{B-X0WPaQB
z^>THwa2<kPg}~bd{o2$~-#{VTICc%On#j{p$S|57M65OyM6&1&yg!ig3ba_*HR{9O
zOvs@ZO1<aJv@aY{0m21>&O?0jrFWJO4`Y$8*U<^oVFweavUE2_6&kTt@RR1yT4f67
zGHm060eK}!%h^W6!RL75v;UfM>H?47jQZ}6r9hO0+ib|Qy&v-&B0S$co%is@^MvK*
z^X3xQC|vmL=db_AsplM=57o0EjMshDa)6Ay<H|x&HHKZL?gxALkwY87;e-NVenN#-
zNDS<GXspWnHi&aLO6blz?vFv2X>~*6k`qhnqT&f;TKLAS#L+j`GO6tX!}5&VbXKWC
zBiXv)<<oJ9FD-EW@$QT%7ra6BX@)BZdRX4C>Qdy#X0`halnli#SVRQ4F<(TH<q@aN
zo-7e4)=y!4(}p<N#IvEkxN)5hpv2L|-7>EpYpFMHG57NEGVGh{0pjwCtEIa_x&E>f
zf#_<tDt$CkvDL#bjZz3AU@87<Oi{j;1>a*~uY$ViT_F^73pe68fC_8NUT=u0<=F^p
zh-hfE^`1PMmLF{|6SPIRYkh0>(ZAeIn*U%8fx{F;T4(7ciqx=AvCNEFn}}kK8njf+
zA-P#V33;1W$3)MwSN$6fiw;U*!f<sK1uSTvX|wV!Z$c2P=#knK=TU+!TI={vXT(~q
z`QY{tQ)pyI;???swn`-Rz1kF%dE>aY_H#6Cna4gOp1k3h2NPZ*f7VtYctRk9+th4g
zNDc)r4Gg9c#_~7G6ye;RW65j1izAXb60<cy3hViTkoXh01**6J|NCre4jUNF)}Hc!
z72!_wh)F@U>Foi)|LA&!xZ)CglVs}kVV`Vzg|g9r!dY#GPRZaZ%PxhxJ;hOL8Sm2N
zlWnWD6crQ7_JK$W?giayTkoa!^Z~(bK~qu-27KbJGj4n+F~co@p#WqVg?gr}5D?>d
z%QcH9<h~V)PfId)uT9ubzSYJ%*yeenTp>5=hs%}e|BOGc=AxhuCunL6T-WM!um<))
z^eqr9)vnt1eVd%KTBCKE4xhSG&9)q70vTb`>)>tkLcE+v4FxjlUs=D`NpOMb?=J9=
zBGH-GeeBkwq)ka~87%Jbe$UD^lZ$im6~om|&@)~-=U*1q#Ovlj_nm<b=?P8|u^wm$
zOB260yeHffntU@!IoNp3<i0kJ;~9wdFw%_^Ou@LpA;rTW`;?F|sK*%bMzFZ-5kTlC
zCaJ}CbdTK$6v>@P_v*PPG2Au++sI`g;~fhFa!FnHS`5}>Q44UJ8$Be{$NhK<YAE1D
z#OYXMq7JlbF|Pg`@CdeSYM0GXhpSxyr2MJ_o}a^Lxgb`9zZLbrJV|i-Yk(QKmY3R=
zJzE~0{9DI7#FeaP6M+C)pvQ0@R+A+QQH>{<KFwUn*RBM<+H+<hMeA4lXk1RYU!peL
zt~9U6^ayE+_8#p+=KX$EI-dkJG_3+D-U_36ui2n4-(TE(6#wPWiHL-SGAG&xz0;P-
zD*w}=;H7urhxa(-4AdVMn62~rb7tOctOC&lb(z4hwMVtUU?{e!`HUpbK?j8i=Ra#{
zDuio|jo#1Hl(Rx=T%5Xoyfow2J@gMuL^Vq)rY>wbu&lVvU%uu3es4gIdq&_jX?8gM
zS&O0k{hR7Xb2WcK*pTh$8KzBwrG1iFEiNyI!HRMo{(f6j<-??STmL^!*+@;<DxU)j
z>Y8gfcpgvF(~5OpN^L=Nk<;aWi4gj@=m>gtclKsYg@#!gn+5S)dp=R9&+y$+1Jw}J
zH)Zl{e~=RpBqEuISo*-A0)}*4V~=w=2f(<r^(lQ%pJA!SP_>$1Sh#v9Xkcivt#DR8
zpH@Z*k<<_|pe@?rnKC#3El?MyNI;~Cy(!9M6YMl4aK?Mtt_2(&Bu|rP^FDf{y-6-H
z)^JNFUTOxIX4#uYb$g|&ZC^HaLJi~5C8NqjL`VI0#_^d_PKa{0@!j*$p$xKXbh^>?
zaFr`B)9_=FFkd%tjH+bXBeZxvjzc`IA95#<$?ya{4wI1DEfFlDcHteb%jB3L;vtmE
zc}$qWW+lmjw4C;>%_j!d+Mzrw7wrB}$aZw`QxLZ|&WdGctC3Zv%|G*Dd`viX%a6)Q
zabFjOrF)<8X+`*9Lgan@h%5@kpEJQpl_!5dT1`>b-(x0g6h|n%fXy3Zb?@n8WyqGJ
z>48tR*wbF2t3~ktM(eA1H%HJ|QAB<!0DEpG9C>%>M<Q#k4=j>OF-S7E^+&X%Xd53&
z2B*n@XWqiD#_-GA)8pfpK&P;{Lq&%|%5|HesDB)tXjxX18U<=<gp}n9+hT@qe%wc0
zBARp5Uaeph-ZTG&MB(v9uVELK_;fd%HcB8!WG28VuA1;cD+zBs^^izI&D>}a4C~~)
zWWCds{AeX{p#}{h62M(Ms$m2_NmPKicT<wn20wN2>UtmV(NIX`4|ncBIPSIMrZSQV
zZZI?88(Qwr3>s;|T7%q4@YsAbioYFYd&~S1IaU=(gf~j!239{VDLSDmFZ-Rn)1<<H
zK=qTuIAf0j)oHRq6n}dcq7rB~3R<a@sNsY-fzK<@?_Qfe<=-n!f*a&jz%SM+wLBk%
z6IWUp@3HV?xx;?01Cg?}B2{;tf)RirQIU^Np2C34bQ%%mymp<PXDb7<yqrYjAp_mj
zmDg>5s#w0)D7iB4N`H{xLS&M6Ov3$ge!SL9Ce`e-dH9FG0i}GR<6|FE_f-P%8fs6|
z#hZ%hn7ySEV#2}d-}H!kley70<Uu@|4Ikw1JG4@*m~z&^IXC{dcU$e{;czo>!6Okw
z05FJlgV0qtw@{M7|L&y~7g)@!qQH{^M2luJRL0GV#JeI2s=ou2$8*^yv^Hxtc0z6*
zB?=`5lh%ckv32BugXr50L$<?)<yhOOF}aK}3)Q^&nZu>EgdGv6dVy*Y3W{Ij3+67$
z;#h&ui1f<a6P~*vk-*BCwdlsnStI(v*3B_ze!C<jH)bs|6u%o_6_`z?zN?Iz9u@%m
zA8@6BtcIAty~;YjtWcBkj}7^~rVUunzv~k*&H+@E+Frgj&l=p%wMg$5Y06l}Nttfx
zs%i&nwmPQ`vhv@Xy`w$sN&SG_>Kb$3mp^#DA8$qw6Z+LC)W+QI<?^h&j{6nVl)uqD
z|9TL!z6~B6G<#U&r%|fnVx#&!t&-7G(yCJ8$27w@v1z=(3S)O`vjoyf3WyhX%$kT^
zND0>8_VM(`;KZ~7GF`T{!Yg3b(uqCzS$YpB&LocEQ&vbaePq^JjK1%OvynU#?n07G
z-j4KoF^0n3)ZC&v&9fus=bj*Jh@78gS0dKBllVXi7&D=o2KNc$MZk>ZT+w^I=nxj<
zVr}bT9jvjQ)*43*N}#N}<9{t~%#`ORl{@n8oO2&elD*Twn5NtU*gs^5f?cs#(=P5Z
z;QbU05}~Df3zn&(u`du>W2!U~>hE#xyPJhz<BV;iX|<BR$MoUlV1&njMx}nMVtGtu
z7XePk>X5c$HMmCM9v4fk<cHBw!sKi)a|sU#ATd%a=&+Lu$VUj1mr}r?LT3|9)GYrU
zDP@CD-$5pKtan$K(3lRj3*MgTE`)Uc+%b7>s-}*{s6(xsae=OaqfZwpY`BtpFmpV^
z3TWkK0(y%V$jrNy-^)Fzl&p6<WZJGDAZb+rX8Cn2pIny<Mtkm-+fo+aSBtG=jUHe5
zS7R?<NmH@?Kk}3z`PIERCLlM~#2^dguIFXd=3dHOHwt(DbsCwAJo+LqLka&Ce99Q)
z`tyHtwJoRf4&1_LC+NT>|D82xG5W2jDik6I2d#lQO;Z_bkmhB{$Rm|^(~ccB4TSzT
zBM&V~$p%G~UC@BkgvYvRp#MA%`qxQ^Xj$@pZ<^!5q+x!|^62i=u9;kG#jUJMj_`))
zW^dM%OV3fam~qZenOZ{~r?#kZwloA?O&wYVi^1b^s=|+Q)Tk47ZKC`x4m_ZIGJuAr
z3)b7+<&~S+Dz|MgRuYua!`D`tpuri=B%d(WbH+=V22swW3l0h(HFv!%zpxuf5^-LN
z=WC#?pa;Rcwxz7Ksw^Lcbw0jnFgDV-utP>6MM&{=QH$>AFUr6S4ukH;0*v>C{^2Dy
zW)Co)(Y5n&DY9PD0|RWp#ag5aWL`Yt`iyfO!;)h?Dhwjp$p?e0WrL1JVYwdppIfQ0
zLV^Rsm}byJFW#7h-uA=2Ft9YqUo~+J&SDi<ABJZeYZKEY`W<Z+j{4#<ptcwAqcD$0
zG9zL%DK6+sj(vWiS<4xoQp!Kc+5<NC5;3AuCygF&^4t1dWy`d7pZJe45%x57D*aSu
zbunrRrxXEcB*LS_`5uSqkjhubMk|}B5fLnFNEqqJVt8!Ft9`{qOY3a}JPC@2R3+vj
z&oHw1ek=vTu{OqYfsK-ZJLV+cden!_*crCN=WfcMLn7*=l6`5`z^*yrY2>&F2}@+s
zOD{aUt{PzgcMv9k=+(gwr3&zc&)l@9rtDF3-O>Mmq2=xj!{2(gft-LTn#-Wi`TTGt
z4_YDchnX$ulp*26XY>QS_;Ef@81?8T+D2+a?(WX_Co?7=x@OzkJp$=k6aPz2_ovJq
zxV#dPG&om?aXRQ7fPUiN&p02u@+wdC(k3X4X-!5W87M+c%pY3ady@K^B^0!JE^sL4
z1n7zMm%10*pFrSsFUF%~81AxJ4GQTOnK_TA^5_T-D>(|v(a9LYAbp^zPQ<Oke16L)
z%HHJ9TJ)(U^=SQ1iiVP(g8J@^6vYwuY<Q^(iE*8tFcvQCLpaP(!}q>L%jh=&xIa-&
z;$}Niq3QbV@Gr90=|0Qe_$4_VfWfTC6cj_@7cr>Q>@0s3&F%LGy@X$TxPzyfz-*Kq
z_=W5nTKn-XIO!H3QsM)=Q^S&j4IZIo+Vue~N8n5A>=hWyQI2#5${QR(qCuvl)ReFo
z=3y85TNmXx1YO%!r}WbvpX3LV?HS^!_Aj~CNq)klcVN$l8l(2ZV2-Kd<d(9V)plaM
z;)<U7&D4iN%=8<wc0FhmK3Fe{3UdOz_NtL%s9X%=7k`1&KUAcYly(!YSK_C%p7^b}
z@^qx*9Q;`F6%gv093j`xEyaHw4`spwC_}pZ)50~xs1KTSHG@OIyz7TAA@PKa_^=Ao
zeyUmqYv@ab7O%BGDBN4j`-}z`fs-Te=`?VUATrNQ3N|jT2)^Q9mTjr`j9Utj9(I*i
zC{H(i!HH)rc3vuu%>lli)cEmr0OOF24DS%lEm3zwD3)-;sqeMQW!jb>g2&YlQTxFr
znq}D@3<YNe@r&K{CHxnh9_-jKpJe-K{Sx?R)PCADSdFNoEJx^ol_T>UNf6m*tW>gG
z=`Tk5@BcvMGSF<1Ycdc`DI;7hlZOFrt7XnS10=R5a}U$B$FRHTv7nXQ>`#>nQBWFV
zW<tn=5(?Y8ax<U|Oj$XJh)w6f8RP<EUw2Vpk17_K3!eZya@icuhsn~}iB!*V*1BEm
z1CIRPOhpE0nF*i=d#?<r@#l3K>ZZGQuwuv9QMeK-qj)sF95wr-*!Uydo}GWxJ7Vz9
z$@Ly!f+sS*p-20I$Al|SF}-}7<0d>dbC=Y$hWi_1k@O&g^()N<vj;Z6B8m7^O%O`y
zuSN+St&1v##sA3SFbW?A$mQe(Ar{uuk(NQ5N40(?bO3SJ;lJW+2~dn0s>}pkAH^6T
zEZ#ecODo4UnazYT3VTtYO&0`>1{L)2y%KtuDj%>{5!H1S(@*EVYfMYp`jFQThUc<#
z`Xz>%&@s==e_u|D6&>L@ucol9&V{Xg81D>H+ju~%$ktLr-t1_-_e!#Pov1mn18ZQ{
zNUk*Dwmn$-=7BoFIDRHGLCks=zNw<Wz*dvdEg*I@d{cu+<m!BQR_0te1yqOfRSKFm
zK1?hGk^(LMqcUFTK%IS0Fr)uAs>D2=WVF=rNkpQxKS{(-4$MoL&Kiz@^zeT%#yOCu
z`eBV_1G`Qi<8Wp>$l|RrI-_%nbQ4rI;-WD_yM<^eSXSRje%6g|d&*vdrvj0js%u>9
zOVck+d7|e)7`5L0VNdAZ_^fdneJL%=a818iar-CwJD(^h<XB6{g6)O*+cXONbBMIm
z)CLD;6k=WMp`K6#SX->V^J@&vSPtXio<*1-pcuS}WtS1kJ+hB4jAF03^XE5Eq@Un=
zcGNnPGjWAuP~pp>(nFi@uVkl8^M*+hah4xgoEaduI9Td={3uIr0OwWbSq%0d+!gSq
zZ`u2Fhs32={r--DU?Vx#Am?OaQ^m+l4-8qCg0RHelwQ}K?)e`D?J1eW^}~A93XYh{
zLh4@?$;b<mSd<D1z;9L7ICKJRS%0@V*&{%`da%@R<|AHIU@tmTvYRhtvUjqW5myF}
zj%s!LLCGu%<6*U?KlP@P)|(!>BVme{qms9fmD+#uNa;EhU41ll4K6fx9g|aiD20l4
z{+yUPJUP!B!en6uM>q%fA_ltoY3?XJ`)O|=J`uyT8!ER#^W<fn*s5Kqon9ek{kJq{
zIVT9vHU^d-p!K1B@GwYge^wnwn3*Kb!hj@l)(sY&=(zs#eI+;bq+j<U|APrkFQ1K%
z7u6X97^bSFNhV>x6oL%8&8ai&6HiLCfI(%_qC%P^RLR}ey+1hww#_I71~qM+L&XV}
z_WMHo9N5V@Z!luvG%yyOZwZMD$6$0><>;yK)bl}Qe$seBjj5CJ=2iL*JR3+P6W^9_
zS&twmrVP;CNJ!=MAPvk5M4&^d+3#U{N-siT{`MzNUL@|@@x`TC8>KeG^JozU)oy)j
zxktmtzvmMvw(<che|u0(Ih*P+#Yi%DV$Is2*JbBzMkwh{(!+f76ufz4wX^a;(|wVu
zjrKT*aEfYwj)PT2Cwt1^i&){!b;%bhyWz?kosW7wk0z(&Z_ps8MSu1?a_OPuAhQ#*
z!gho#9zznNWb@7zWUZXW158@z=^YIM9uYee$3UZ9d>+q@sHSYmV)4r@ma-pKdhG>0
zZ(SyYO~en6U@H4UMan%pO@r6^;fT*I0Ph%fCb6APReS}TCyKs>#1<B*UTVMmkidVL
z^k|Lu^_mbnZ{|EhX!G;(y5F78W3K!-bzZWw@^zE7#w4VUwj4W^<pC%d1aGjBMdp2$
z6-`ET8yMJ(VT{8-6{g60ThR7_nweyG8LZ=(zV*&jE166zJzK9PwwW*ryzu`y2|=gb
zj&Um-D|r{8He%=>y!ss{SLK&$yiQWFEgs)(-SluVpQyo?P@9W!D|R7Z568{90KA2S
zA$({p;!oHLSJ+`PeUw`3>VMi4hVCPZ6JOa}2vR|ITE$%gWvRMhve`YBzy%*w<+keC
zv~Fa6In?hyRYX{B<#O;7E8(_BB7v{CQs}Md5;-zz+V!U6;F&#q0g)Gz=6}jy{-b4n
z79U+7>%>WvGoiQViLRHI%~J>ZD&JtOuw`JJm~Fvx%ifg!o~kLG3jExwsr+>C^rOX`
zkmPn8Akm7*859|jMd)0O@L?33MDvEay2v&Sr~HiB8HKhq8tRueapqO48Po-OfQ)A4
z)e47l5)(2trxcGKNH4r{L&yw!4N(s@Ryt#$rC!&~ltT0&VRDd3XpOi%fo*0$2Q_Uk
zM|Hz0^M+zvMtfn4fF%@`ly9~N{rFOES&Nn0HpC2lsGR%bGhse|17<qw`YrmeHDht!
z(?n1y5+b8^I?-j^!~cmQMWV+hVpJ*d1J1C8#T>HWDLhl14=kH9pjW_8eq3g6sa>IM
zX=QniCIfi5GR0T~?^JAB;~e)e;vTLFyi2D!c0{8xJ?79Uk)y;xzOe)mWIL+n{)%uj
zEq8M#FbFE^Uh@EYaHEd#-o5KEfmER`FmvBye4p)&f<Zd(4HsFhsEuqtdK`1IHJO^;
z!P;n}oQ_f*Ca_9`)<s+=MPu>Kw`oXjX`YQ}6q!|~`((9q%hd?z0<r83(kf+9e34Dy
ze@Bks&_Ke_tpoM}UCw{0usOh-GFvuD%QX?bKh<;8_e6!_q`lLa&2i7y+aHl-$Pl?-
z(KGdsr~{|C+{IHsV#r2zEDR%SL3G=0`k*}O^jyxb*Xmjvt@)hKg_kH+Yn%&cW}%m0
zI2=xwJT+n39rEsfNS{TXmDXFDSik2o{&XeFGcoc-PQfmv8xVsWf`X>`l!%N*lDW=}
z<s2O%Gz0<OQ2{Pjc75Gh4~D@CSM{XD<dk!52F3W3L4-BR2M7b!opUtSKZ6aRu^YL5
zp*d-q!AuY?eaPfl>EKYoEbY##m(jH81uq-poBew-<@EwujCdXW?s2_Xeh15JPo4Iw
z&NSn*bl=s<ca^oBSlZQIDoiznKAQfWz>Hdz!L>fSa}{Fe`S*0YuqeGi3H)jIQFcrX
z&DAZG6eLKX&aN_VxSpANL73x)!CY*hSlyU4CJO@biv=?+?HcpIIloQfMNL<qnY9`7
z>d})y)RGK4YS5ntD#iOtqM0+(p439)ED>?(7tsVuHx&)SLo9;zaF?n@7uf3KtjG$+
zxMuV-n?^@gDJme-Ok@cWN2!{X{p}=1|0jE$ZM#XB0O{RBFqD4IL7+DzA>w835gDHX
z?V>vl053q$zqZ$5bSi+xL54jLvi6{<oYEP_+XNK6;mN$lUy=Cu{qR_-xV9=N{>hJ9
zS(r~41FhQtabx(nTjrkiX2|RO)THe_zcf}5!J>`=?gB!M_5LMj6tV;UBaAgaKR*8z
zIegx7J&Mz__!o+duJR!rNwpXu3q1wA5Gb&$+}Q9H24rg@tqB4kay2~)_6ER_-vk0|
z1g+H@k>mlO`$Mz-kYwU=x{A_80B7*~>{U3;MgdPs4yy6<Drt)7d-3H;dgQr+Nn5|C
z&vnK@|09l{)ul@<8<5_WCCR&+K$`V^3jZWEhZ@Zek_x+W3HZgobn-z0xQIw@vjJL3
ztLz)JKscQqIrnJOc@f~JP$BB;GP=$yreNtBAtvEBYaX^n+^T;2_?@-ZfKSrufwM$<
ze@V=VfT1_=&DxP}Ub@o*loF&|(w!W-P824B83>h(W0+t*nSPZi7zWl4c0B`bopino
z-yU_Rl(UOWA%M}%nk_Etf^t!Bse;e+<nBBUmjnG}8U(4kg2v!4i}?1S?v=iqZ|;JB
zOI@wuz0?*X{UiglhtQ40uRFC%7h`PK>Z`KgS9Z_dL`K5O4|tGWu(s|~`mg16pq^+j
zh^y^u_GMV!vqe|=BGQKAptKA4j+pVQqN<XFG$euj`AX%F_gJgP3Ys@mXfk!}H{u?`
zFu>B%*GM-VD;y8uu~Xib|JJb8-ewN^P>a-m2M^uHtxg6oqI;e7IxZ6GSknCPz2q?x
z2I(>^T6}>7ij$~o#vSn%sTGZsNR|T^+^qHZ587a6V<(zb4n4u7MlliL6QMDV{fc*E
z$tQ$SjTuK(HYq#ktH-~LHBqA~!PC8&oxo&6b6I%Bz|<9d-D^IfOd$rl@RZx)HcVa?
z8niP@wE!J~@^W(Lef;67IpG$JurK#*|EhoCG#pJ`(@-dDAw#!lbx%L+^#bK9w`~Mu
z0fh25@z3ASC$Zzs(&ZHyA6Q?02gQHsc+t|M;|Z}wN$_%|sVOo`xyCTXwrZdiGSx?k
zC!$$t2T}}s0bk~N9*{JWSBOGANpu$qL(1{qYyGAyOcnc0f_>}2U?;&FL7lEgtmt{I
z1GIA=7Nxtog|EmH#!zFOm&{D9GH@M$%GMR9oKkql6&`6HPw2bI4q??3L0FB8c3a_)
z{vZAWst(n7Fvi8K_2V>m?4sX;|J%3_Q7|`e*_#sW@A8Xr=A_`)R2rBj!K&;GCzks8
zxnl?7uhho1rfB7*$Q)&ohm#<Azg$m7l@7izPB>guY~$7bH0maY8U>G(P}={L=K6*l
z5|_g8Gkc2}`T#9jSSRv7V#F3)m0gU6hh=bHZ~VG>4@BPN^O7jk<T^&&59bjmKL(d$
z@C*D7Iifg|OA@a^wv9f$$Bi@&IbP7+WM+`oqqmNxPEyqzCFC@cTnJe+;j1!j*SSVZ
zJcQ<G@;Vo6l|(-^JdHM83hTxOcBjL3U?5m>Csh8w-BPGtf^H=}r7hHF{JP<Uz&jrH
z!?j3XS&_%wdyiy@#|O}(f&#2n|M=_Tr~a5E_7Mv1;=vV6`~JIRw;s!TGPs7=3y!+{
zV1-kHn2oZSprv3D7CQJq1fQlzRMFo)YvSIgbqS^07M~nksnT7~UxP;5N*8D6O03M@
ziKmec@-jM;PLFu@8XY1=uMyxuUM}^=FO^EsL*SS>l|;oEsTBIE>3EG4bZr<`tzL)R
z!0Vloj7tr&t!<Ov)FbhmNS0@%y`YjWYHe;>$+pDkq3&5-0ThA}(&J)Uje1}FuABk8
zV1K4|3rc^Y=d-Q$m%j6In@(T`&OXh${Tou1Ca+s3I>JR*;N&Y#rd2Dbvw#iRWLtKn
zFX&U_9}~sVwfqhL0H;)`Sb`bcB~-)!bG7W~!(W$=QAs4F@xO@wi2;^;`k8I9t#gem
zco_Xi+CoJ3p7<;}Sy&L367Mw81SZZ`MfyjbTT4L@&rh#I7Ln&WKK1~>@&kw*9IxBa
zrqLAX?3?{JSFt}Ia?qAIhl_Yg-)%n@0a-DrxUAFwcgZn>^!=}9NqX4OivDkIZl|5L
zxx3DPQR<MHGXU+@u1P=QG_&N!HStEN28-$X5Wi1zdVR`dH-sWW@q87US<fw=IAeOE
zr!Tk2_qfajR^ZpJoaTU-^e67T72l&~@Qo3jXhHOFl1WC<dqd%4{4JNPuZC&=_J9LU
zcie<ROnu88?9|`NeOBqunlN7T4Cc-<!X>%g(jaRlFhj)kZU^$3S#9L};3P-R1p3^q
z9M~ugFTwRQ;3xEk6-wap_X$sTw*X^z2^<Ht(>BO->ypoas0R<Hlt1)!Y>9l9S?vn3
zy}g_pIW`uBI!klECVOHatLC7D*Uz=`@@iBGLoPvhDX0H`jSp}DB)Y>xa!o2rt5o#c
zDoq6Rh8KSF{-5R57PG(>WX9fzd%W^JVicjgEN@Dp1XsJ4vR*sV6wDZz$bqiswswEU
z&P=eLNi}LVW{C`#Gp;`FbdQ_X<0huaRZuMpYaQX3+R!RV2nRD}#djM1o$ig~2W(3h
z@~xqs3uRX{7R*CHrVRV>0&?J6OfHn0^N97MQevD7#J)#37Q@JR<4j|^0+>0^5qZ1w
z=DHuxDUF=aXRBq})M+E-r`aOGY{n5GSENTL@3f}*3%_aTyy8(6zG7e4sr`i>tUCeV
zD|&K)2B_nA(lli98;^01Pu_1MD@Zr%e&;ihxi?11KoL9|e|JPz4cp71R*n=pvP*fc
zqs`*N`}kreR1WE8J2gpv@#Xq^%@R#f^3VWyH`JA#FlUcM<AG#-O>pQQHyZBufy9-Q
z%=j*PWa5_u5XUWNeb}<WiL(0)FmuDS&;v{l$u&E+DG*b%novFUwpbFQ-&7_t$Iasy
zSC&$|wr^F@_Qk^@>TC8(WuaFTbyGFE`qo|sZpNalmbFj%ZQ_I~4>2J${9x|yC86Y^
zk<xA`os~=WN3&Wg(P~-$3I!4KdcV%YyP8pmhC1@@rE56S(-dhZ(wDNeQP=<%E?|rO
z2NA}15ATc9HTcQ)<&u+yETqW41Y(u5#a)AY3MRG!Yeaz*NaF#j#D&S@q7cHnSSuyW
z*kFL`YNb0n6Ntw)Qghue{#AJy#3q!Z70C-uQ_fiZLwj45U3_)<^X*w$Vhj(=joR{Y
zjmbs`sCWA~q*a`{!x6n9f|(2N)w!xL?y=Wz<*Znfq}@hZ?h`%iO=+;pqiem(5ApN8
zzCZz%2y?qrZ_(qx>O?@Mv}OZ~E6Li`{0?SCP*CzUDsCg9cgU)KGF{*Bb_kB?*_79y
z^FB+0zz>L}@kb>XXV=FHxQX$No>~x(Bj{|ywiX2mL9GvZ!X5JX+BP`_*A)qKD8I6s
z<V_6H?sg#h&xaR5xSDJ);J8oaB*BmF#9;}zf`bkyhxn$gD#A)?N?U_Ck_5jHIDab!
zKGt-(xtrapB1tw=OkJ}3yc9xAvjJ~pXOuvv6B`VMH3bsJbw-IQzvJV31lAhE(6?Mx
zE6~5-ay>vfFc*)?;``roYWs|dHnY3!M-zS!h~RP9<Wa}vG;Uzn`PF!VR3ETKc-^Yf
zbos2o!$bt}K{5qgBWZN!q%ibfQBjBV@Yk`1w2h3m=zV<z;xYV~CUl}uh^DMj?OH>K
zu=QR8VsLS5bOO#$y3@D?kw7~!VeQpsNDYkzA*kG^zGb%SpSC}puZ5F|Q>0vHuPfI7
z%4pxn1P5spzuP#xc7Ye@hc7g7-ex^4f<M=|?cMn(uRU5m3zRQz=s0?d88Y1YXN_25
zpz$iE?yGf}WBKsHOT)rPuyhZqZ|I~A_%h2f$ZaqN0*_La@u?E^_$$9#;{}E(bJ5y(
z;;|wqf$VOJFXe;An{a)Xn#Av6*)PJHA^sY|OEeLcniiD6WbIHKE#UJZxyapx-*bVy
z)je?XW#buXh>(kZZCFRSnc(e{-<x*XwI_r6l!Hg^;na!m<)l{D`BYP9gHl^}mS?~d
z;VM{AYAs4?>Fjj1kqAI`s={@+VoI&N;hAh#Y5%qZ4tqET(d8*mTJw9$G}_pt^wxLS
zj=n@VBO~44_-@;@*pEEqhICL87dii-11>@6oF$H-Z+XYMV2p*2h{dbQiqF=Z-DdWE
zPM*x!H}_8^_CLhG$QmD^@Vr6iptM_Ao>G{UoF&D57aRzOE*Ml#Id%u|N1aSKEI`{X
zmUvCbk>&%~dA=V3C#;#)s#|$)iwi1RjID!Ks0$wkc?(lrX03cDu7WHJHtgrrHm+Z~
z@;B#31nZVtnvMc%5)r3|iLgWSeC-S=yPsn;*S7lWey{@2F1^mWR1S>XR@|Q;YQbt9
zWqxlvgvthnZ2BQIAjls^M+#8-d`N5@nHZ2Sg78^NH@?8Ph&T&kDox~<#)4xqU7K2|
zm-V=EgsPgfqd5%O@SJ~jYA5Sw{ng&i?4t+_l#)Y9f1|6&Ra#tP@qg()d^AW%nu>R4
z;J#V$gg`N>ff`3rZitXDHG(0*v9wxglAYTeAap-3Hba7Wrbm_)5G0g+$E$a7I|t#_
zXu9BfFy}%kK2m~-oi6{pTPQH!r>f`dJnb1~q~@EXY;+s-Zg}2sYQ%Q0bwme<&|%bN
zC3(!AWnB%LDiS7LsXAXM(gaB4z_8V@zhM@l3~>8*(pIyH*s2#BjLI8{yFrNZ6W-)I
zNa(0i+ZefmeG1?(P<s6Ls)YJDa1qeimIX^Vxp5+tvWuP(9r-&P_qx}%47Ev;f#))x
z!=H%*TKzJ?-IqKiadQGLAlvM<Fk&Uk(FHfP-`N#Lk0@4Qz_x+HIbc@6Oi>PL$AUYs
z0Vh`rV6w90k0vZF<|;(`&Fvj3GMh{v7SHs%z~d}41ISQUW41b1e9!u<Ko`$zIn+PP
z1;Ndp+$~_5D-OKylb4@c2db|-ymKrX2cbBGnvF_b+0dW44uLp6EQ5}{yNN>O3UQqR
zJmQh=ar3{<)6f{T!X(eQHs>$~90F2YdhkTb^3l8zm)c71QbxV%l~DBoc&C6`zyTlr
z5s=Mn4>US$%S(7L|2XZIdKvKnLhPu=xCJAQwM@3x<qzOp)8@cRJ^^A*V_`z;!e`e@
zuso}edH>B%zuXa17<XB#Gkqfp$Yn#-x`Im8#CcVPtwEtE=qFhf2-J-7@&%J><v0Ry
zbfecO{dF>*2{%vbuH-JYrCDToSLZ6uvO<i=yHjbzu*%|@+lUP6mnO|V<>X)$dNE1G
z9$9eDl*Ct;;Kd#pObJTnMG|F4<Xf&4KBwC#ru#DtrY${F{6`lOw!i9xhqx(cRCsL9
zy`3$;B~DSSBQqW@^^T(5WCizuQu%iDZq_UnC5`V=I?rRHV2ic=p7<`eZ<s=#+A5tl
zRUKH@Akm@w@<C%x{qn_TMxPTJmJ<p}Hy#vMOP|S4w2CuQ$xvSbN)B0ZP1g81kYL^T
z?kdpf{P^?Un!<%uAV|I^fEW`8ki8u){JGR7W~c0LR9>B(5=uXT2CVsbS^QfVGNRa9
z1cBCqPeATfx5Q(SRUVi$CdvksN=uxSZjtN_s9A;`JuR8F`Yq7y9&}BZPCgcittHAe
zdLQ@9(CuR`@6$@VtCT}5&@nMy-5h+5wy%XbLw<#>KbHd|9994&1ZM`Or-N)N0~@fQ
zlak(MSPlj5$%igR#ncTZ*O^n78VdJ6`s$)J6wi{vmZw5tRF|eaMyESfoZtry!o6sf
zbGUV2<)4oR^{WcT;xR4yZG#VE-h>Jtwz;>&0k{wz0ZDj#sA=Q73eHSRY}J(Zu7MNe
zKSG|mAgg5oM0k}AsneO!)yAy3#rUzhp_nLv^!UW~5{*IObZvBvZf!%W9&SIQ=ypmi
zi5O642@uw#B|<zP4pA0Xxv+VvmqWxAU#B+L6aNc!A_Qwf4l=J#^d*P@66;@Lvlhq8
z*vL>&1uatq@en0q3ADXwwYurNR~N9Vv8yLQY2OC9(%h||pDtCFD&m3>KX(rZbW=wy
z7CBqC)73|(tdhWd4NEPv%6*5U8THY?4=Gp=#-1kgM(Qo{=m&xs$6J)R!=TO@b^kX_
zZL9{clCuXpL6r7ZG!f<>w3WU%;39L1FMkTzj#`hGY?Q&*3C*Og!4$;eW4TI1hmKtn
zUc6^R)RJs;ld_eHmjf-CjuPK>-vGCV7HXQseKbO`E0GLy+&5y}*dw9f`~~vC$1<^0
zk0-5`m9+R_pq&tQ-9Q#{g;@Usju8(<dKmo`8@{TxV_-7c2W#HUtv>y+Xmkyj)3fvv
z3++5!77GOKslAL@tYUh0Jqa3WL70KK8em`#wy9FTwW=K3^msFEMeCAX-2qgR>#`HJ
zUc~t(EU`PLZR%iPW3`U}_<;nDrl~fGg*GinDE04gD8PkQ+#nqLGRxnH6r@AY#w`L1
zBloW-bUr{Rbo_YN7qu&}QRn=YfD&zKV7D}NJB|B(x9P3i4}T?P&Qsk<m*mbVA?Q!O
zQ?xDEAVbxWB4l(TIfH(I1ykuD7_;S1{VGR<6|>+d_^nP*@OpD*uE;y{0I39WY!{Lz
zG>*z$g;~+!#TT@u*z{cbwuU`<C$|CVZmoF6u?58UaYcCGuR#S<bSje$@yrFGsx(T8
z#Dq~CSC66FnO<6a<~S3i5cm#dAyxv#GuEla6^L30+*<6ExbJXhj8**M$NWJgR`XJ-
z^oin(C~(;7Np`QIL@ft^CO(>kmPVRkr-rAeedz|3o#<Bs7Rq;>=3qsXIV#d!u&8Ua
z%VH!~)pdUFA5Nd1sdhNpohfM8lQCh5a2nlS8jX^ERkBLU$Tu46-(6Ie2yWiyHE5w|
zwDpyN1Hr~Yz`UfQIYy|r^?a|7%ACdsU&1uv3()i<a@7oDDOLOnML}%4pfU3-&z)4E
zUpB);4<Kq9!OnLMA+EHxedoomkAZO(nw0U#M8fFD-qmS?-}CKY{cFnc7rvVU&*~!6
zWEa$CumQ=*s~=bVvz$XHQaC|$6N*ACa3z!?L}aNXA+X^E9)e}FjS>}i?l{|Y>6R0M
zZok;m)h>G3mb;YmOzYloy+8ZoRX{^?;_{MR8Dl}N*fRm8WTe4oItC=KOUjgH&dDav
zs#G{izH|JWt$lHo5wG(<cF;v<&xm3{tg~?A^t^<XGLd_f)30E!?58I(SIBcThhdLi
z)7>AJ6_di~y17({-^1TBmQ71&OpCH>+M(m2fK=;Hj=bv62SBZpCm9G>1dzv)RJ-gM
zj1ligV0F48!0GGgZn70wP92KAmg|1R?Ie5k7^#hWC?S(&z6oP(7DLXcWgeafLJtzP
z@?-e3D-~`q1vW-g^{Ie8fmmFkg*a{GXne{g@zAWvfhezL&;HCIFH+t#>WzscIvl9!
zv82=6^<>691w0Ni`TfwVP8`qEOk8cTVKnfGwElxqX%YvK<si_lw8a`o?P}xXGY<Pv
z33yp5q5H>m>cg^waEJ6RT8$if^;m>YBq$i><R570)fo_;R4v|1b)h|^@4^wfxoVwO
zjOqMR?AHd9NyquvoZl*lN-Sr%<oR@_>PxQ%j2~!8@$yj18lOAzKH;+FB?Pk9FXVuH
zLQ3B1``B8>gfNCp2#*_k{-fy#0Fz7RV>o`?*fZ%|ZUbb~V*OnX@7+Q3Sv{e>T1S4a
z)ixUd11m4}VOjWm!@N=K4?6G^a5QTsIz;T2Bf)gj{@YmgUi(bOA*{t;d2#6G8Y&_^
zP_XlRgDS!5+YL;I?O`6CWR)O^@aT&#Y+Gr8fQydi?JG8vR#O0sb7#d#(Hd`K;wVy4
z<xLGy%m0Z%tE%&Y{4^1>=4v~5^i-(3q$+Nv!(7A^OBeVaV_WLD=BWXmd0Fpe6pyRQ
zx#8QWT{9U`_cGd2A8MBA92pTl=$1(T2Ut0w<?tSth<%#Ir0Pwz``Z;%Gu{({kU#(a
z8Rv@Gh23S{HjM&Vll-^HcG_(=`%ntzH;vqDyas7y2XPXcJI2dlgdUK+&Nq&`4+`S{
ztEw4cS~<89tmDQ@P)?VEb##GSpd;gLmA2gsEXlv3fN^Geg9z};rNUOKqx|nAH<7P9
z-TcWzPD2od2FA$EN}HVx)@@FP&rX<{Gu~_>0CCy5Lw6{YdZ07$r#iV$B`Wf;_tG}r
z=YopzaLuI-HR<U7XJ`elMKM9PaG;JbJt-uu8-M%Q0po!M1pU^v{=8#^4xPqszP>D{
zQnCnKBx>b!m#B?l`EQTDB2G5IOfKr%1oN}X#>A4{+W$clBj7h+^;p6JNAzdJ@<eyI
zYW{(xo(LaS2rA==m0dXy?6B?wDhEEivQJfd0};lK#V+|`TfR^NovaiPTtC6e^OgvL
zL32TX@lD)lI2ct^Sdx1fsj9@%IF&%8I^3Hf@WR76h)Eer6j$2?`!veW(`$qd2PGx!
zqc&5_dy;ynX~0ju{=il{G1IDHo|4UU4#pq7ylg6Z3yGfdt8hzP7-3$rG_3!-BE`=5
zv3X$7Ix=gL07-Q2Q(q3UBZ!@z%5UUMw?mc+G-)xJkK`&v%)D!WbhSt_9|-WbJRI$E
z5JMKntzF-e;6_c1d#QM0<Lj@1-+b$1QWe_RT*zmGH5mZYW{nLjoZ?8yp#lI)!i=+~
zfP&&QX^!$zqUDxW7X;NN+=AvB1&UDXJU02Vs6RR=0*eTulIewG9gq|f$~P<mpExC^
zWs7Kue&Z`zC8iI(W)gF5&&l$nv&iv)-7^;ArSit8T-GILQ<YQw^Z;TZ0%7wj66{mk
zL%}`z%e(kO|4Ilg=ny^*57o<1C|prk*l`FC@7=0LSjiFI3{zfq$#AgnMV}42I_w3s
z;{~?@oe5>xV7PzqbkC>lk&&?m_Ib1|K}aZFPgkqG>*DIhh+dL31gT!9KfmYB^e&H<
zAS4-Yd3A9-Py&FEQ3R6^6DfMNv7|tt^1g0`oat61ecPjEiE1w1=SHz07r7#A04FJF
z?tafVMe#8saxQ+Wv@l#?>RndTrOS`}(VmM!(x=R7Eam^-$Fyp3SXva}&oz<$Zauy2
z@#j^A@<b8{E#d)?Otx@5d=8g$9?Ppg2F$_(*Z2_Fg7xti{6ypfeW&meqdh4X;4}V3
zD9iTV{0BdMUa;95(padXRZX(KaTdUkHi}{{6PDB$yc62Ndba}*SL|I{0!@lZdEDF{
zY~1Cd1DESe<&jd6=j;IkeMcfs_x#{hFdR1bduFd*T6RN~@rC)aC)z~Z6aPY=>IHe%
zv$rL7fN06&0A*d{ls#@XggJ(xbjpeI$z96vAG|(PYW3`FE+R2PlZ?CAuXY&LXN!Ei
z>$>onJTEn~*pdGlRaQMYyIVui6zzzxZU?0iOfbKs5GudvizV$P?HNAtROPshkE;F<
zAqmttQeq%YWLWMC_GL0_PHFP9!lM-^{`Pd7W?Y1Ds756SdG^x@y@?LM7VccHWW#wM
zD6F-;lF}ISVUg+s<Q6e~IeM+O<fqM;g;i?|3jMQxdyy^oW9%~*8*_Xb!l`LK?uU+D
z0v-tu%Nm*xr|w_oi-Zj5O4~S=tKE_}*6Xo=x$FRnyODxAN2@d=c2m!^GZg3neI_qx
zy-tF~t)G-~8dT=KitrPDpKJ(Xf;!~Xu8$?GM9<L<(`p9M?MPL(jif~8)#3A3`k(Ar
z=S@TmrMS|%JVd1?xl}XpApS3ycReZCw~fMR#YVp;y#!fxy`ZJDI#x)(J<gxyVkF=4
zoBW=T$@fTnVLKd!;<)_nNy^Hu4fXStje0T2x>F>=#20@)WVs1<TRFaw(b5mU(GTd5
zj$~8<Lk_$}Iyf(SQ%*X)t--Tb?w%_q2)bYlz>Y=WGWdV%6=y^&oK4+&x->>HoY+!y
z7X%~X#*dPAfaN5;QMgL|IGb54kk#SQoRd1!i=xh{7srpR{XhtvOvGgDNv9v!3>>)E
zn8PEf%5~C*9~qflD1F_~v-X`qerZ+r<9|Zljq7ew0!hK)eOv|9>C#7-hf{yL4qt*R
zE4Or-bxhC~s^6)(X_1Y%Tc8gcmx=ndJ9C!l#S}0(BaCQN8|3vJQlE(DcR7nKM4emC
zx@`%XH8K)Bdq(F`&gHPu_;b;Y(wi;c<m(*OwYi<T9R50_r`a0Be97PBT$#y9TJlFz
ztDkpNoSK&)NR(h6w)JUoZ2+P1Z30|qYzA}_r^ZgC#8F0O6~sgk3xX2Z;Bw&Sd$fjL
zFuHv+z1J?Z9F?3NM*_{KC<hK=>>wI<x&H!RNjf?!J#_rpplNxe%bi$|=xhDs_|YVS
ziLwQV<gwOsttH|A;pk}h#@jIMyl3>o+Wl@*F-y!jiG)%J;4vBU>$()T=;uslc>l}#
zG<_X^P$>Q|EwLL91^m_k#xxL5)FoLM8$OO1xvr&mo!~|~2z5XD#oq^~C(_lF5SBxc
z`mJ_=RDUCAcRTN6&E=2T(M1JcloX;l%KvPdx{-kNev{L-6afT~R7~%-ejhJ{JM{Nx
zHDy0uT8nDL*yd>I%%KEP3JpU@s9GKFH%JgUTp(6%d8>E)PB3gib{fC2)55&$F;;0^
zs)DyBk#6Ko_z9iZ(NheY)qmSMuYdw(eX|gOFqYvfDE(n-<yPtxFgN4j8hp6BwQ+Ep
zNUZ8IVV4N7*Vb`8e$~_&n1*eUn4^Y;ukBbCR<raFHKjunrh0XIt__4%339ycl`kv$
zil`ADg*)1kFwQE^+iyJI<xE40J&}?)z5c44gO~_xny?MC-&N=^%-+9|OW{Vl6<DrA
z2lf^!faGezrwD-0|06d?-4GNh8!V>LU)OyuW(pODg~;zJiS|{JN_3UE^|iwF3C#au
z^rLiFt=;XwS8Vn>zKgfUZZ*Hmg7}f=z75JXWX3cbez7Or#AbY=)lglF6elH2<~@1b
zkFMxcD}scXWf+mLvSjv>ocAhMG<w%&@vQC`3pKNA079e=jS;}_JzyUY#d`%zqtsQs
zU~>Lttu}c7=i<_?jR1yKBR(j_8XlFtF94YNeSU+fpd@$@FOrp?TLkR8fD_1Q@Jlkm
zAwYS40WPQ*jb%NqFbQjk=I#hLxap9VQjXsLu_bN(B~JCahtAa=+l3)48Vm0sD5O*Q
zrB=H~NF)LIorY)!w(bG4TZ|t4;o*5i`Uo)=j|chrszW8>hRP67>=Hc0nMG3grH3Ul
zB^vV~Czn@BSXSSDp?;PjK&Z_XjjCg}X3nIU61NK~sx0LNetz(IIT3izzaFZ;S^qxy
zOZ8W50`IH6n08L=V@EgSbr=dbq!etkl-c<@<czY5&J`Vkw90_0195XUR2GBDxkyF>
zFm&B8nde53ZWSmq+0O2bYkL1Cuc!WttdREE5Kh-~-Yjq!ZK_`&*Xkxn8TNXR=OV(^
z;u9MXaHjupxCZAc1hfgzWh38jFsZ#F`YhsXFr-}@UP`m+yCiqY+G9X0H3rZq%wtJe
zMD>GK<O4_oW59g4h)#ha(=sTWrr6E>gH+<2TeATZnz~*4xP^Dm<ddS2>d*F0uYugI
zl*ncBQzf5?K|~E(Md$8l(Y#nk2zC<u?XJM0q80EBfjV4*7v)dU1}e*SFDw2k;Tb{b
znh69Bhf*#&Oe1Jp-BPlJO`V$Re7@cjcLs>On2&fYQ*<-0Izqxag4A6vN{y|H6TNiP
z2Kjq%<=iL@auv-En&18n{hE<Q4pnr5`&&s$v%MPtoqZ<o@ieTm`(jN!|9-|#n|bf9
zwMY0jR0#GEikW$V!>Prq<IiMRBRnAdNgTP^lwuIL>Av}!UeD!DbYoO3{<eguj2}pq
z;4-6-bW}myl#nha?f$Aq*`^ZSj!Q&Ng)8BA7+#5W2wz?BDiM&k@morR^~}@?+{yHd
zVy;!KT#%p>1Sxb_v!Bc91|!|w$1#6CT!Mh-rX|X?aP7G3@5r8!OZu$U7~Q-ok4pzq
zT#uw%JTB8nzd1RVZD9$L00r_cuJ^J;JvpY=@i-aVk$5|qxXf<{<#Sw%d@wO^O?Qo(
z?wDBiZgg#nca%3_^XdWtu12p_5KV$#EW!B+nXi7e<r6gT5e6bb$8Xp%{*H*fn}jii
zSqJ8##cH$Qv#H>vF_r{|O-mkU%smcD-ICMYn=oxEjz`NM?C}QTWOF*N;=Jb*D>!G=
zPh<`l4G8%<1`N4P$D+@kx04V=q|n5S{5Q%MPA}gYRjTF^LcZ*EAM0D~ToPfQ-85y{
z4OAPK4UsyN^`u+Z*eYbf1YU;a(->fG_@~t&A=49w=WA2le7LKG{`A}<0O0{&HL*Lx
z<Ro}`m5$(?n96xzD1p-#^18COs~B{#%-X6B(DX3|Bcek?SO=H?Qtbj^zb?S(n_ZzB
zT+mfO5pDBwu_<8%Zy8pcF)?rtYB#Acwqo!-#R}{>wY*&PMpuoHU;5<A8ltW&<8E7F
zSd9f%MB?^VH!d%2ju2oSEBB1tjIF|lh-Ng2wPe)kGIfJ>kj)Q4kqq~YZmazh0{1C=
z2wsYKKQBbY|I)P(_xe?$`m`oK=aZywO4t#gB)Jx`1swl{S;itX!Ke(h3B6XuiSQFJ
zVSUB6S_NHSHvwGc=wP(w1Nwb`D+vK36)En5@~+!P89VheA85!RX_W0nte1jE{d9HD
z8fm}o_-5=Fr{Onjd#XFZrT+x8U1@`IsNbdkdbCX-cc3y(>=>d7YTOwbI2^(NM6ExD
z_{UIF9_cjry;xW?g=px|qZ(djHS=(ke*D(|xxQQi!`r9rYkfP_#Au@vX^ZKgQkg!;
zU&@zouET4y%!JhaL$Yg+G(=NaRjAFNuLz@EN0sgIeH{v%yx3dU?Bx@iTyDng^auJq
zpsfr%&GUA!!!`9#sc5UET@Oapu<U{uP0Wx6_FRkyKPYhnj(BNp+ud<ZvodTJH8C{r
zk7JPJw$U21Ms*QRcn-7n57mKN`Sxm-2_j6*BKN2G<?C2s8o~5z@(vB#Kp|%Je$hk9
zXAjBbk5Dm_p2hb?CIpqWhl{LAtlBE)I`R75&%F!vGrDps&b&3rJQC}lf44+v3p->w
zQm~k;?~4`|aNDDVE}i}r@=D?(E<C$S^vSw+_cja8T<8(|{Mcgfy6sX(wW_StNV1#i
z>IAEe0`g0ss}_-&4H`?SHbqHR12mo4HkUQTR2y)?I%%7_uVMh!q|!8$4iOBp-V{8U
zCn9W2*;;$ZvPdpm;o=>TOj`^_eVd4F-t%Q2(S#x&b=<JLU3^o$lgqdI!F@SJ^}+Q8
zUgP(f2aq99QW8|?-&=fh6)t!6uB&#zpNsS|ciw%Nv!e0|U;(RGP<y&~vL&n(;9u`r
z;FNQsm`RU47O4LVc(_&8vfm-6Bq4ADwtC?vdFgfuHEO9dE3G#mP%OFY)i(b0%c^Dk
z7zCT#B)n&C7Lb(C`7Nd{Cfz<PpHYDUnWewL^VFIk*F1AEFbKu7=yFF&nwMQPATQ9a
z3M|D~f8aN>KPu1Asd%$Kr6WM~>~jg=B`@jx9aw9NDvrR(G#4it40k*6aJ+VBWPA6!
zTIv5ejMlhjp3K(~c??)9<t-378UwUJWXkT)h71-ho6!m7&%N7ROjp@tY@8u8Zbk6l
zE;S$F&v;iOmC!#Q3J}_g8^uO|G<C!Tgt9``7bpbax-pEW%LHk$Xt@NK!c#%|+9X>U
zN_R{&x>Pg*UA3W*RRn~tFyjI8UXT;(1(K;J6kW80uWxufA7Z&(D(iM9<y{gN?9%9f
zs8Eacjf>(vh&wMGnc4479h4vI%D07sZy4<Y&dfSQs9F>8h#!xzZ>w((B{PXJ2}b5K
zE}~klb^ims#JyZ#Z*Nb6@8cf?P3vaC3VmBga;M0kwmA2aI!Vp*hc_Ll5F66r7#%$+
z#;EJ6d8I;&x1p^e7C89lMAFE+=i9WE-C-|(8C7{c7oesLH6+GTLn}ZT^($6*6L}yJ
zOM!IUd}MB$iHZ?-v@iBXjQ)H<v%Zl-o4bIaqAo8jXGvY1+TcnzKQV^BFrT<oI@)PA
z<!C_N2mJEv^%3<L#)0P&;$(r65B4H@-HFQU<Idy|B4EG5vCUJV9D<PNPWtTE5ww2V
z{*J%aFsvI=M&{WbTW?xI<vR`t+M_Yk<9`kAGIOM6A!(fw);6?bs4?ZtHmiR8Xu)bA
zw}n$x{qnXc5RB^1X!NR_lYP+-&0H{dZ=IN#;~VTvRc=igF$K)%B1U-U5J`wX`NZmQ
zG)PkZQFpK2X2wH;4keqKnyVoy!vy}V4T_rltwujF53&VKm_ilQ$M?7%s;J30zcCLw
z*XDka8ygGlz%kzS=Gy@5N_QxzNVNek@&iWF=Yh<|$I5Qcg?F8x_p2w-Rnu>Lk?tbI
z7Vc%*BTa1s%cq5anAjO#t6Z<a|DkXL%Jwf6$i*XlS2Cmb_4dZ5o;*6{FH$xh@RFRR
z?lbUo<Gahty8w7t;#<5c!~ahy64CIC@nSv=%O;K32|nF2$k?#0?MvR##B9XiWGH9J
zZm&V=Po}tU$%%CMTEws|C|buUn-^Ywari<V6B{1fUbi;#u;4TEH>p!(XyYJENjPwS
z!$xet)D&IAuD6vC2zx5_ZYk318>b@uOyJ+`Du_9=lQ=~c0*|egnK01eLW_7LCQ})Z
z%viM-9uV^?Wf2mlG9QGFGmDXe80CRmG|14r#BAOCCZMrXWb_u^t<ZzF>!}L85$<Qk
zj!oQs!PK-m#RH~Gva|%I)Dw#%L8~qk7=_Vw>O$HCoyoKK)vgRyIzki2>?J0&%)0c)
z+=iJc2}L%Wfxr1nT?R#ky2n!&`}%?f*@o|8Ah3Cop5eg<lKliS%hzz8_liN(?YS9o
z8`fX8#R=T(OEgT4z+IY8D7BAVznJ@%Vorho;rm)E&u{J=pVG=bHWxe&aYtJpkrZ;x
zT-%byY5xnPn9;~1a&FIu06iK`-aH9bYy;}(@4Vg9!52R{1%I?F5+J!kHMX$-FFfn?
zd2kE2SE~lW|9xbO{I{WYvp|cmun=dJ^+c(~{w^-}>V5wOe(AXInEpzWc{|=S0ziI2
zK~NT7bcmo%3vZ-42=rL(c8MDrX>kC<FH4S#u~)m02FEnH6xnF_APx<AM|_-mz)kN-
zkPS9k>aU03$O<nkiIWjIKqP(dwPWLIPhY~uqJK-sJ1Po@60m~3>w|AMwa57_p#uEf
zS}cBb9*qCvBWA)QtL=UJ-;<9j<OHyH!E@kGB6ba1G=>A@2n7gYPryCSP6_BlPX#3H
zqoan9><8VlYkztab$Hy6(*Y+gDDQ+C_ZN^*xlI8Z*WkBc{4$6uNWWeDbia_A$?$W4
zOXuzi5PXlUap5}boMac5uoK^bt2elkJpW6)O%r=@!y+Ee1IP3b%SBh%BW4D?=-7^5
z@n>>U(!AjTOfX@`TdK^c%?ipk-SrcIA&x6`t0}<H3MJ~ft^I$S`cW^S&_epmfg~ud
zl1?VgI8+btEg_|CpI_ni+s3{qM<MXKeonaECWp4v;G^l_C5vNk8yslu|KVkqF>&6v
zxhbQ;NF&V$;#`p3D<pz#62KEqzgT<m^Sc~JE5F_sm8fq}Yzy51F*vcAE?*$Sm7bp2
z2~|M)88d1ESwZsAfI05r>;D`@+1=YoP-%Pf4Q!R1k<xcHEEJb+MfVhoWPo}r*e!Io
z1~)SkF$e@jg*K=kJ%{#r@)+8{gLIITf*<?Fr>yZZv}tnzZgicI!E)M+;wq-dS?bT7
z;?kTT#U;6&@Cgj1P+!d~Z9(F`;Vr#Ts58{p>l0J$PCt=^>W^+_4iy7B36>wzy3&gD
z71s|h(qmL!BHK{9d5c}?o)~U3A{EX;W?pTiEf6wAQx&xsAjQt3=|N9#Gv7m13n9@7
z8Mk)zzgWRRQby06HmbNJ-;=NnBJ${>e%um1g4M&w@X@f`kUvDSr0<4fwkzQ}Q^^~0
z?NVcgp$`UCfq(Bpx<@$%^7cD~Ga`crYpN!ZqOIh(xUC~V?M0#TFD1ejADAu(Lkq1~
z6(|bNSRX&|ZkZlp_b{LlR%E}j*LWl>a_O*Nnw@|Y#(wbETf-24%~`!`#*mVhde}nE
zrWWfl<;D9spCs!I9Mk}MBeHA1!Aj1FUFYU&4m<=YhbcRBO8uav!~j<j@*j3@-Ukcf
z9|SyY8pHfvi_*dvXRgcY6>@>^FsW?G(i)<4d0JH+GQI*z(G9b`KeUHz1>|O3ui|_%
z`v+M`V~|$Ji-2T$gljts)X4zLe`c?*HUGG2C@_?r;{1Q(;yc0XvDMJGFpLrE0;*Gx
z!AZmFxLsuien2Sa=Thn(sg4!AS5?Ew6o73b_%)6YoKn-rt&W9Qx^f6CMFM!%Zh%m8
zwF({1^}?Y!i<t-+_*OZr!2Y#48ei%Ym1QDkuo~D;jbWlBOyiym6||cet+<>kn?*9F
zjBk_w)H-xft;wtGm8bqC64nwkxeAjopM~X;XVCTW$9sPSpEp*V?Ye3GM5y~g;$%Z2
zA^b!KN|n=)=>07_05%lkQ0l?Hl(HrV5D5JP4(e}7P0uwH<UwTEQ)%0Mvf<d>Z;ij=
z6e7u|tBBGXMsP`@*RLScb?`+U7HJG9s16v=7=_++@|m4kMgAfx4;i#OAH7@7jLCuO
zv{t)n@+!_T8j2DaNpu*mO=9TSZ>W~Ae^H&t)$AX20}1p(;#EU{Y3)zicYc0pG(b_b
zjv5CeF!^n#wKiC|&H*ar`Y)Uw!7Pgca>g^%D6meGM;jh!WU!$eXcE>#_?C=r6IOz|
z2qyNs9u`@wezOC!RagzGgJz(DeIrvn>hM`X3cz=H%N_%!&U|HAnSZ8vZr74!cC8Jl
zdZM|7UAjCLTja$&V*BgXYx4LcGw7j)8>@v>QLc=q)s+Ct@STL}C}QDc(%O$7YNlnZ
zCQe5H)cStZsXZ02_lX2@O=;0n4X7OQH*1%XcqnO9$m?T>b@elX4Slo6rjI*KTh{5G
zwrXxkr<z*10XTrKyty+K#)e0`v>V_xj|P$I^c*a`y!a)uM36S%!*ML^pFCl)DR8<p
zr_Rfy^*Mx=KgQ)V@xmGg2DF6!s)(`Zdjp`=jmyc1Q8KtI0VVBRT&OgQgqSs#`USKJ
ze(F?la|;DE(4wiJN+BmR0{D6?0*c+tJxsfzt0bRLBbp2E&|gLl{_X!cnINnv)+u@g
z4a5*Ygf*Qen(Uphx&|@fo*eQ8pMu-59tHzR6_-fp_4?!NW1t5((CRD=R2n|N$&^&N
z&?mRn36{MLmij+F&ZW7@!5v<+ydTXg_zt1pHq-sPr5086*pf6_>Yy|1-{%cP<cY`;
zr4J`_?gI!qto0cM2tEQvm|L@yvK~A#xeFNZD_5XF4Dp)wEMXAu;TT6l-rK0w@LkhU
zjTC`3EoR@}kyHLA09G$mxcf4$`K!t{ZE48(Bn1BWij<@dO~#}!tR-z}zP{pXBvmzc
z@aN#F?Dia$F{hN?FU~tXwGzy0(?&0l&_Vvb!o-27^W2%L1tLs0PU8zb(V@T{o}7BF
z-9x>7O3haX+;xq9knP`zhJ{%d-YLH-aZYDc*S=em>vit&c&Y>KZZRf+x+{y5Dqg(9
z13W4%QHV^m&<Lj%-m@a?56QXlK_go)A|!~QYaSf-x)*On#kb>HT!j{tB1%9tpGwp=
z!8q(yluh@p5#qPZ==|U>Q@A%msY)Z1LJb-LjI>kP+B+`?>C2az2RG=O%Uy=SCSMR%
z35@y+LlR<&&4DK`JZY@*(zd!}clev6sEDrmY<DA{(kDpqhqjDCdyU9#O0<(|6n6rz
zt`k!@!*4CW12rWgjBlk_{^V0pI|{Qk=AMYCLEB=FJ=K)V;q!iZ`1N0+M`l8aj!i{e
zrWF6Zu-kEEKXrF)4SwD;Z(U@15MSRey3(hbRU-SQe_Ds70>;L4m#Mxb&#qk7Q}0)?
zNNOSA{!QnbI0JBzMiGohFvUR^8;ew>sn+%LXCrq4AWqi^tf&^?^N4b-aokO*-m5w=
zb#I~avk*?K`G$Kn$^@en;Fksz65M^rRm!)k@NGsrM`WotIH1_tMrzor?-W9dI&b;F
zvaE~LqXh#96LzwpqAFD$dewg9wb<OQS(bYM4UZjmw*o5Nw5~6C;o2Nyu5?l6oa8;p
zs+Z8Vi>St7u%2>9l_tC?Tq@)E9~ERax*knTT}H|QeiDH>299e>f8cga2+gEg_?2hz
z-b_z33r(Ul!un+j4N#M#ycl*;Owg_@9sbNspI@dggD%5e(W#|cv;IZ@Izyi<a$d1^
zrqGf9x41Zv2e{2MxrO7)9FlThp2r*Uns^ucV9b6wENRFf-PH#AjF3s*st`y}G%!3l
z=0<6YMX!m+rpz$3uQv~0FAslq@q6`|BC!vpzl?+PpESM!nBvTs@<R}MK)B;X<X*$k
z;J!)9_?mbjCi<g)bRBG&=+8hV(0J>{XBC6wKD@dv-z9f8hqv<l7hELRF3_E#gG!jg
zjt)W|`)tIm--n5k)#20dA))v~Oi@X`QLT?j<*~QvE_)vAaQbZyNaoN8fWpYsnsDl-
zO=-N-IyOv&meA{)8;)d~rO4c-?S|B@ZxCDZu)6uYW;;M|@M0w6znyN6k=A;w6rv}Y
zs=(By=wwkQ-5GWQ|C@T@$edUix?es44`$%VW+jxcuecEWjDutexg3*cTX74!6*lgi
za;cltJ*mU}D1JEv1w;dcPvNV<M=paPi3_4imFdlMg=&@nrrfn#8jdp50JMG$Wi1k`
zBjsp(S|R&LOhThjBuVHCU#{Nc2P7kKoMPNqN?6OFHB@n<>Ix}$OUt*NQ>xh68e^D4
z!zhgnQpX2WL|z?KarxJYvC@UOobZPHEc!DTT*gn}DxztoggjH!lotS>91&20hBlT~
zxNKLSd&;kycY4fJA0o>wMN=v%@4Q3x^+A&ex8(Xl61u42RJ|5Hfxk(Y*e|FItOzOM
zY-kf^9W_|I!B`uT@H`|XIr0f_6v&}^25h;jUS^_q9tY!w%w_w@x2Q(#gYbi!%tfV9
zNmtGvTa$tB^wktrj^!e1k`za3e4do#E($76l5b6WcFy>SQ#`5Eb1Vi`O+Q^dZ4Kuu
z$jGnzte2@x<*9pA{x>o3jcjfnsU+F55>YS#5o4d(e62SYwX0x(C-bXNx3dmHC=g(J
z$=EuL_xM-<=;H)^oX+PoR<{|A<LU%vdE+$?Cltipbvgec$j61yH*WUYqwDEy;PTa%
zVk{>g6Le(~609nF3_zpXY%oZT1<9%PlFQ;}!)F+G#S41*cYGLT^db=A=$C91ADFVD
zxS+|<dCx)?Q_eBshWHj{X+)p$t2k@DkU#jJT}0+zWmgE5US6NZd8{g6T4VS?#ZuIp
z3LOgh+sq>B%UgX+rRX3CvYBip<u9=W3t{yN3;hx$G(o3gqkXghc7GV#xJIcT-W``4
zBGpF{A>@cMC|G0JI=S&{xCZ&Ks}rPp=~kF@#H4V#d2^+pSmyuLI{xitz#u+s$=-kc
zuH7HL4hio+SK%{n+o}oi`vmAmq$HNB(s-}IJ`aBa=Yg3Niro5irmY9our-M^%VpNJ
z;H0MzhTkofYy>VB99xdoJNb|UY(8>mF`a>)hTNwJCI2jJR~X5>eF88PAops)u^^+r
z`FN<VFP*&5B!ijCQ;s(ADKe3M1#6O#l1PH*J2xeDB!$Y7#5-o@(UM_a5B|a%%xpT6
zMuR7;Wi#a^wV#{!V_z-1S65uJqD}PD4R?o0;NY_2CAHyHF0Y`r8m(JZm|uyPncE$~
zMkf~LsE_V+YA6afP!R55JCn19;VeL`e6P5Rps5a!MN8s);E*|mxI~Szwbt3CiaBoE
z=-v%Oh#g7~<hv2-ag~+LQE!_*)2pmt2ljSne?}QYPz<1_45C4qIG8;w_dD4{VuW|R
z#&vNuCt7)nC&mb+gnMmud+S22H<RBs3=sD_SGDv5C)D(;A{b7P3+I}2TcP8UHtIgN
z*3wm1029SMa+zq1ox4s|tple*$}jmtiZYhoN^*Xo!0e^p%4Iok`g(ok<2zwfPqf;D
zuM0LLw*&lM<Tv#;i1^F7W5U<>&(vS9gdQ6FczkXcL+tXpl2x*(zL=OP6AUOzed924
zMCJAVc#F?;1RrK#y%f~`x(2fOdz*_HcIHg_(G$IG{ZW{gmPratW**zzUG3L-5N4{?
zkalvHdhI!;z_B7)N5>?ws7bgq-&8H1vbxF<)<@y8hzFR28YQOJ1k1*1=giV$)m50R
zMOHl|rz3hrXqP;y?v%Mfk4V%<l^BNqyQg=Xsi#ugtGV>7xf{8X^USN?3d{O$ht3-Y
z_#!@F2)O@`1?y%IPA)?r+ofAH)OwKtGcqNbo+OS0+2ip=x+Z@f7d~Bi(Vl+?&6e04
zEdnKw1UTMlhev0tGS5Rt$HlD|^q_5JB3?ntv~fAOitIur2Tw<`!C!Dno67HYU3oIG
z6fS#j?YS;U)Hc~jQG1Jo?F27y;z^`M&rX;=--s4eN@8&N<`XmOJj|2(4eP9h_fAw;
zz>iPfiFP}7{%ZWNirY$L-!&qU^f||He6-z`o@RwJNIw&3IMP=n>MI3mb4H#|Di79|
zSQn3hg!keOL0<T1etQtWN+@Mj3ll@N8g?>|_U*sO4N6sv(Pl{EiAYe+KC!Zx0%MO&
z18d#N)790NiXYT6zK^~Lls6jB$l8QQ2{X{)A9!g{!W3Sofr`~P`0$?w;T%lIR>maG
z9GQ|U^Ale_81E==5U`d&X5HM9fQh|i8f(`GZMFSKZrGLjIgDD{aava0A*B=9r4ktS
znAD(^^}wa>#YsiXx`64CyY6`MqF39J0emd6Mv}lh|LyVF#EPaMDHKDB*(Q1hev(>W
zbf$}r7Yd~R>T<y6=VKR_=*8%MYG@=zX%y&QD#j)-sUN2x?)}0n-*8Il4F68074khT
zd4`+d7f@!1+<MSlKHJ(}Z8xwPV1Fe`%me!TZAXLzc~idm)k$V5gdzJ9gd?^u<L>Ft
zRcuA}cDh7@{hqjB<o7?_I74X4WQYh=#2Lsn$t;~(tAa~uZIf1~E$mW@pf5etgy_dq
zq$gGpL!MMB6Y5p&`hm#|so3-k;kty-(6Asb7;S`CO}KTFdq_U-XwLlBB2Of$zbl$I
zK;7)JA?N0wuNC*m+En`#Aly7AN-4j(#dQ{?fM+>MD0W`rTqbW-j>QDgaix(R`!!#U
zC|qH4%EM%N_EMPZgf|@3O00DUFnI*4x)zT?bpe~mz#VNnDP5u8v}@Oii!}jBSm4Di
zX$u!8c-Gh>6Fs^R<C3UKJr$C*-0kf@czak9$CV7q`8c=AGfE}u+L&2cTnsDYOP3qe
z!r%nUKJ8i4g2Me%omB-YYq&faAj)vPN$%LuHx`~7UeU3+$R`}fu!!GNHgaqSg!z>X
zCE=rRX<(+U_X`-DPP7E0>UvNvx|RL)HY*Zn4*GpmYei!sz?w<=2wpTIbX|8Jqu`Mg
zvIE?E<_%NI)n@uaz6b6I>k~iXw5LnQd&7Q~WktG1taVh_b#k){A1}CM<aU9KFXo~f
z^yS0M2n%u8mSjnfA~l>>7<i6zNaah<TR)uPGG*e~DLY0Eplt=u^KUSD#xb&Me8I%q
z#kblYBc_WgBzT?j1m}oDM!@S;O4GY7)d5r4$qPuiWT>hE?(U~qDLh?2Nn(A^MnUWO
zj)TpqlAeW(mR-n+{d3)X)}4F4k$GH;2swBYiil0^Wj-Jfk{la~Da)t*Fntn1uYUqj
z!zJ9O<sR1(0q+<P=jB8f-`@)$?WF670q7!43zW~5yXaq_g*j(%0*AaRvg&xey}nCR
zWSq<(i>>za-n%s9bZTKGyEt)G43y&!O2mRn<CB0O!Zht47~>U#`wTX6*-u&U^g_BH
zqXtba9dwn|Zx0oC(tOow_7B4s6pJEoP(2q{EN<+^#^?f-28-|RbiapTQMf19zPQ4J
z<&i*+lNh!6X+vJ=;_$klu2rYvoQEcolGDA5&Ef@#sfr{?i^X|Gre0sS21)PO!RrLY
zz+cCcs$+9?9p$1l)QSw&g)~JUKw)y7TRX38S&tu4g)H5E-zQEgb9`En3TVp}81M~!
z9H-ss7h;8=bH|(i=(v*u4xOLy0$g>KgU7xN7C#dT#NN1ko0@Xz)!~8<yO&1`-WuZR
z&|E*b1b#KIrCU8jhV+@p{iGAVx~J}<kcqF<wpuiUbmoHvErO(1L(n5p@UApD4ffJn
zP5VmG`V#@D@b-Bq2%^J2Y%PO|%Nm>tR8oRQe^lb!^rBuzE=^kAp_IuDSV^8WpX2cp
zAtF3;$WVg4IDnjiotSWp)eG8vg93Tjx8-IH9nD1jpyEllQm4|c29rjLVwA%!zUsIu
zgD|*68}bKEJ%j1jx=*(~%Ryo^V0guNG=94mu+wdSfk+g^v54rzS=)QJLMUm&GnYeY
zk1nuBF)^E~Yrm?B(=A|DxfNw{RNOn!l$tgAU7!2jtHy=beHtDm9jlP(VF&@8h2=2(
zBYU7YkIDgYOqNmpD=sa;tlzcu?3N!9VxyX!o~L206xU1e?GsbbIfeC<z%p6{#xUUr
zbxd>S6@e<-px{`;jOw3C@fuSEE6ZH{4S$)r_OX|5G!_k<yYzdbQv#Z$&p#O_dBhl<
zk9n765<_v;it=b;h4u31Pw-|Y1|UNiPmrO>9wer#pl%&o`kJ}h!(dV}rJAB98)^ZD
z^fhkZdimU#ibfwl_<{MIO4CmxQ+MJd&!yNLkBg;N@CfxZZBxrDXU4C$@qaloqp6cf
z<;)ij3~rm!h}^N;FrylA;+m(8rOOGq55p`&?@RZ=i0M9{0?J1nDApfG-m*<x{h%HS
zD6h?p1@UtJT*lbjMSwb(A+@_yI(G<4(XzU#;?hyTyie|gv%n9%k{K}eAhCoNYgs`T
zdKZz%UF{up)ZXra!UNht^n}$=H(W+COXQXi%_G6f+7oeXNCd;~w27K8n#PbGkgoyk
zk~-juF8Gb0A<}Cn?L1*^DEWx8dN|LSaTPa;!@q^l-<7*~$%W`&8Y8fAYVMh=ClX8x
zjiWCpG`YSHbzha|cdFuX6|4~@e~CjDLISH}%vsfJnJlY(jv4X>2tOtlER^U+!y$)E
zH^hRS`Av75D0g9xI7&gHygCf}S?=y5XX7Lyi-AUro3f3p!PER{nz~BUvC8F$<YFTB
zaMLgV780fpdIIvsZIwGgdV~1Dxhn>h79+#X1DUAvp^FboNnWSi6Y%=DqS!7+*r>zz
za@c$+0LR^XFlEzVXD|MjXW2m=y`!#v>4uUzxYXSog>E9?^<V!F1u1<dKWfw46G+@Q
zU~>lOc#Q*>_Pzxv3R7B-mY<|c_0OoW@jgg+XBJ_7vGfS%`S@Af-5LitF8ZA$+i4Bn
zV`rlNOXKTJ<3u+;|3PH@1ZQoIPMB#BVN6gF3#?-oU?m9~sUinV1=LGDV|_ONac}*b
zC~;)DCPqgsY-m5`+IfWs@UZu_ypyDR$tVvKj*9j0lu7T_{Nq9a$5ZE^XBntbXw1sl
zEKRqiSXt^VVwa=4%>TW;CcvnwRoRKHAs=80YCM<Y=wj6E@LdcsNjA8(9#p(@3S9!j
z>PXQGl_C<;+HWj%GSqDvOOnhb>{Z}2azh1`v_kBVMSI2@?L(P!XRk5u936}4M?e8h
z5eNN#`wjEt6JgMS)vGMl)JZNO*tv%d>mwTy>;#`wkWHzR^Vws`qq-7)c<LW*O)PHv
zWD<V;HR9p_qtZ5pi~n5CjGp4$o{dH_^gF?C#D-0zN_i#h-k+<$vS(lC`8f?tSBZVw
z+;LHs6M7!1#$sK=r3@i!QlB##a`hIc-AlS`tTqPT``~a{{nQbt0!RQ1PRiT~VWp%{
zvmJs1YqRNfFd#{+yFlshh4g-G!1}7fcTm#t;{GmG&rjZA$B7lmz9`Q012QFV=iGj<
zIQl01bIHq{v5hPLM$svQYL{-q@K~FdBw0HZe^w`<+Em*_h)zZ9g~>56G`8HzH2p53
z1DkpbB8+tlhHA=R@q!a^@ilVsY%J5d;1X={XI!&r1z5}s2aWqEony*mc2)(*8B}s6
zs5ra0F7~27un<s<>6|Rl8zQ2CCsFS)goWXc6;+}`in~3{6l>hgSqwISV*qnS0BUy#
zUrh$p+F<yXoa?*0RB6bNz;`<XK_RMLnA7dKWT<52zo=pV<=sa6l@C(k8a547n+-a$
z3ZqOOCVX@kXH^wcV0F>D=oI8mTXnR(2%#d5rNHj$DPv}Eg?Z9VU#vXefzUpxH4j6j
z^B)zA&emwPm1f8@P+I_0g{t?|_>d|NIqQjpP?nSyQaQnBt|apND4Y}l&t&+_M8X%X
zWrqfgovA{-c4OfADTY^ufNd|Adj|djY_ZHC(XBPG<rg+sf149?T%akD)*CHCj9AsT
zl7#RWeGJO-V+SeEDHA0^ROXGd=EsSP_Sd70jDQ&=Qte6wfhRDAxrP8siwc?f>+#Eb
zYeKrs(AD%cm7<K+l^2mvpBvT#7%%FldMPcjPiM}2K$M<B`r1I};glxefqOs`QZ6Re
zFNkNlP!Ixng1X`lR7}{b_tPZBPG?V(aJg!-Vn2#BtKo4X?1oum;&TgU_^BWcs%wo4
zc=X5n<PW-tOqM!!lC{)gl%<;{Qxv!(WdJ-E56Cp((Jo`RR;qptaVyjqa_fJwctqy!
z^cLAIA~vpn0BowIwUgs<F%g>+=lKsSWUzm9HU#C}l5VS;0qMW$Hf8cRYN6R$b`%A2
zi)?o=Q%)#bH(%-~8%EuJWMr1Bq}?AVUqTl17j*W-P^^sE8~s(i9{Joa1S~ll3pXSW
z$3F^NGh*vSMJEi;p|-H%-aaHrWag9WA@5LJ1ku@{(HfyWq&lcD@z36I@1-fOg$u0z
z(u(+NT8Tu~yy*+eO3XycQ@Vi4yaP|Ai<nEwjLLe+S<pdjGXAXlcg9Oi&;KDb2D*Jv
z+nK%6)Ml?cNIuC{C(@Q+q~)X2DpJ|pzK7+0md7~=Jb+{xr!Q`-JNQ86<lFOJV~WlD
znj<vgQzux%p%5rIC-u^XBu!-+-Evxcu-!=E?M;gQxGA(L)3w(zJ()wLJa_8t_FGyL
zc(_E@&=Rt&PmN8b(ND_Y{8dx=`RNC}<AeBiDP>H$zV0LAtenc>hY{p}8*c<3-nTxy
zBm+vg<XjPK9)^sjL&c77ssxT?AA!lnf_l*>f6m@WUhh$ETGK1@py^)Kc5I&=@9KBO
z))g{Jb7ZQL#^!}pmwJI~548G+UJ%5b4$-4bb{^MjD-k`-XPSNVTD`ZuS_aLm=9ejl
zcpTiq&7b03B{v1%3BsO*xs!V|K$x8Tov}sk^DRXEy*?q9X*VQ1rSGl4kPq)4&!O)n
z#fppUJR9b(Iaqx~G^na>W7|n*&#!mP^@fJeck!^>Y|%^_-UzYxw}n0`ojYlj$ugJ$
zo4A@CcJLKsey1@iXQ5mYiojNwg6VtyHyj*oSB!&6%)>T#vE<HTOoBE2Poxh=)iTtC
zMx9!>tKJ;556SCma#Rh<3VtTIkkJihO8DtRIs^?8qt7*a`GQZp)wmZlh$BHyl&1ot
za7w_3C(2$SNYo9<>cl@;=}INLZ`Ub~>S>i`vY-J50DE2}y(R0eE}QN+lz;SFshk6D
zzef2;!fMRG)n<6mD}EH_EA)s>r@IieTkbfv7?>zuCxpO!eH_KFzd8E6QXog19ThVL
zp%{sP{UESG0YbPz<5ddoUThBk#alG56lS=QPZ!4FX^-ZNhPV%U)ZQ;27d8Vn*HBev
z!p7V22)GbR5c?FG#B>;jFCg*k7_Pd%?z*F@xlfeLiz^Pg9Qy#b3i>&u1(2)DtCLW|
zTHPOgs)D_G5-5eE5{yzz5Xr)p%%ze`a2P2zmQz4|!-$OXq_lMm)DH`U%b?P|*!&H|
zC|WNJ&&jxJ{I!~;OfO$sWMM0sF!Jm47CuR%jP$H5ow%XF`M*-^GjXCJf#85L(IE%1
zJ+uuFAR33@*?(iwB3eH8-**!SOK)(IOW0w%LEWzioc@N2#<Bv>5j!SbI3D)-wSJEa
zkV*+lC(2i1D+_v!)OZrU@CHCQs5Ois0!OYw0!eS%0Dld><l;G%>tHlRp`0h*hRiLE
z^=x`S>{~#)9+zf(Q|7R6C67XRq2;Y;+MfS0cTKadbQ2s43kFd5gR0>{CxL*{$(b;1
zEGflW;HG+z3j7R99aC?stZw3sn*`u55xg~ndmwoY-8XL~Iq0%3yb%mF$QOADiZnZ~
zxBs=}Vt2_hAXAG$fE@#&$+n3Jx;e9WZkl=vX;$VbxK|(}E4>eE6~Z>$?h2-59)$U(
znCknLm^WuK-N{9*^RT6#O&zVwM}cB&iWg~aA<;MF+@yMC3O&`<p#c?l@S>9$wPXpz
zJ{actkka)<<>YZn@h8LMSI}uBA;s!J-D)JfAl4QxE4V^H`NQLxdBf)ru0DG2N}x+L
zG?@S9Xn;FV&`e}+OM~YyBV8M*Wich$;BivVhjI408g~6{XXL5vv2`+bdrEtzeDLKq
zedHnUfVqSw_TTjDCS%U%@U0^NHyxF=sO01>`D8k<)-=bzAjB7BSkIn&0?t34Ay3i+
zc<=9F&}n_Ie(9Z@A<u>*H+MTcd_Obbln>z*0j{j}?!ty+MOeH0n^$_eQH~6~GQ^Wq
z_9I>ssDIIQqwLa`*i>~k%a9Zg$UG{hO~jX6Ce-H{DP>CNP7}umv(!TKgtqHc-GO|k
zQcZ91S<H*a?{n@U|Cw^2*84cMewm{;R}3xWt(=C|kGP=oUutx^0~;ug$JI319te@z
zn6&O<qnFyFdgZ7MlvD0G{j59RiO+JcrDfQesN{XAF6cRft79+YCV-gQw4cl7H05?d
zNg5sHg2yCDwRkv3!Cd7rYA9xKUc&QYd;j_OM>9HG_+U$Y`Roo=1J0<?eS%D5PgV>n
zyG2FDJ1O^u8<2E8GH!YiLeglz(EE9DfD@Mo7roygjM3jY=7V=Uy0XgMtDBdcl1ok*
z;X~?ZJ~6-v*>89A=J&#J4tthpiL;Dbj#HguW|l_SrH;p0@oGRbn~lLNn~8Z9$E)Bx
z{SlUG8DKg%>)z-b$@pESB_w#p>L~V!&|6XWlcI|Fl1SKpAx9>1G%jey#oV8M-$wB0
zqryHlSX~v?+USBvMeKa?9d1pGeC$LwuESdTHpIIRqY|F|@V1p5l_*YcwrpRVWs782
zG&60m8_>DNwnkf$$<HFCap8ungL4}KMXWSfm86DFG!ldIh=VA+c0n0LqBRBluyW-8
zxH5avH3zAM40=~ZFE(0<cNo9GYbsE^{$TH<NWU|&#cV(Sc<IGo?0%!0%fwh?uavHO
zJ$1qY45Hux6-+Bi&OfuRbS^lw^FWRax{%*Nn|-*1Fb8>(w}-MEBBM}fj`|^Xs748E
z2Db8oU0(>Rm=RH0Ir79pdLNPm;TKJMB9O9IESA@5ZCT(X%7k(*Y`WL79q#DQPve3f
z4X886V>Z`gX9Uh}vq|SI0$<WWBo)_h<*kg0#$*1UPl|_17`a?Wmk@3zEvPQMoBHjE
zbEFH_?aE26y4${6>csMJtc^3c48&D?6>88EBTM;XlJ+qX=EQ1u&rwuA_QEtxnUG%?
zB9FSeC=DnZ40nK-$5Yd%@gBq2iVydm1B9<Aj;2pI5Zyfz@p$R4dx&c)O1R`3(?ixy
z?ekIr<h+Ua5UEV)qdN;y5L%_C&E|A=Ew}#GZ)Igrf1#4T7*)-K`Eo|}sAQgms$6d^
zZf|0y;P7Ngf0|@oCV&Uu^v>{z^0fD)CM}r#ZYh=uAi9zw89MT#@rGIBl~)@$Lrbrq
z8S{>UM1Ta9!i5{%&+WpLotQhf7Kt)ktz{DBwe_f7o@HMEjRlXfL34yJ*UKx};>Xvx
zq%!((xxobW74LW%mSHK`cL!+P`yN}<zwSivRC`FN)GXm5dqpW_nb*O5Uz5B~roVnN
z!O`4xJTGSuDsSN}FWPwpN*D<Ilci=n4`@%l=)O}o?iS8_%A}XUn@^|5im<okE2Y?d
z&<w+H)`r`1H+rL~rR|BA1u;AOCv32H@6!o|;dt<Jw;yX!x{;xK<cdP~W^(D~objtv
z(7RVcA!}x^D!{(s%*!u*4EA;ocl)9*Bij89-<-GzUXz`Ozz{i6RRxRZ6pxg<l%Uk8
zC$vj=<IeG}-p3`E&Ml-s0p#6T;8*Pa+<p0QQ3(kfs_Uaj8T2*PJj;i9viT;@%;_d7
zT90}JBduK4&ySXBHhjtQfPojwA2>CB+;;FWw)O>AK!pa<)+MADl&;}uKgnFRykQr?
zG&>+(RbqUdqzecU$IPv~8nR#&2)&~lP?~2KJIK=Kx@H*CYf~BZeDA5^+c7<&N-n@V
z=f{MmJM!~s!6-f+<`DH$Kag1bX{*{CH<6`4a<ectG_08hpDVhx65lF9QF?@G?=CGr
z(-HDm^)`$glhz@Ju*yRe;E@rks%J$AX;gXnXnxhxT>pEvN0intsLg}W3U(&%QL#I6
zWyqO%uP#3S2#lGmSQ*{3GM4iq1}x3*e%RVa?nCtcIb;M62>!d5<wZ_TaFjO?6QLQd
zj_tVE(|8jO{NO1M>qer3c;1GvW(((ETiXv}=Ts<1O2pdE&)MueH5crTW_!FOW3579
zgne@``$6C+q&U?GKe!!tLP(ra>47)JoHa~5nTm~NWK_;y<eGX6#tiv`a4c%UXA00P
zE@^_`FL#Wb`%llchWDh?0?&;?5Jx)uD>Sp^2|^8cjMBEI)UDN$5=rf9ovpcu>|=#8
zc6uQ1>kvoSKlU2PA<(Zj5y3)=`x}G;{?un___L;RsuZKfHUN-oN6sLtLEGf~UG_u5
z%{@Tj(O1Zh$TCozJ|GaI+eRi}?%~yzRE)gvUH7$(8PZ8!_1=^+-AE;e&LwYd3lot{
zTYHr8?CPIy%`^cca-oGL-`1=_-cEZ4tm)4cfBXN*Kk;7w#_kNk)l~6T#;YZ=kH$C>
zm|9RAw__9ikf_{IifNbaJn^~c)3Cc<W71?$W7vh_1530BqI7}+m6m<v2sRD3y9h%r
zN%>Ka)l9EAdxp4C_aAf^80Gp=k9pe(X-|1fuoWA9Zkr)uw&1S#1iRkaE4NdJbCV@L
z9mL6N!**0*q|E`1AUKFMWK}|rK7BJMu@B$8PFlK%9bh$Ddx~las8}8W?Tm}*N}@jA
zX2RwBzPN@%pNhQ_!A0UWA_P6Pp_!$uis;;)#nbiRURFwY>uBNWVHChyHQrI7pb`)2
zv;zZ+ST+KiSf8)C@(%9ao^|C>{x#e(!Z!Ko3r#Gl!(|GtDIJUJ=CkD{_+;H;-dNHo
zh=a-iKPGb{WT?m>@edRAv0%{#=_NcHvJydSX4N`cxR^_=C;zv4)RWan#-(XrT(?OQ
z-i>GTaXs+ps0kK$tSmg_3#}94yvHrrxQ(W3n#G7c6)<_2s8tS=82XeJJJUl{9L$Jz
zwKvq}{@g=6Lk6c-uyj5^rl>HR5s|&U@FgO|bH-xSI1`ue3x+s_jF_e-bB#0S)0r4q
zCRu7tV&p#YFt>2X;ohlI?lmz{i{p<QE`Ky&k=>EI1q?Ht<zc<Z<W)8b+Vcd~qnM#?
z-*=Lphl(HSG^zAsr56x^uJ<`9V5~8~aJ($K_{9_yVDDYt;m%d?E&q#kZyxNAx=*Tg
z<|c%gYFTjEDnzi)A>#!amR8rOXm%v?FX-WSqGtd=)rz5m^9+cKnCbmB(1=EEy4-sj
zLu%*lM2wEq!-q?bh&AA)y-^)POuw7m`P~(7pu5o6_u`aMPx6Ea51MZrsQ3-3kC<^;
zEBvA$T`UZ{vl||(f6eSEE<DlEcrWly7zcI7Ay&q94E0#^%^3XPcuYWj1MYOHWcS%b
z?UOk|Kc_A8$DoM7#)is-X|)4+vjxqRdA31dE$OC@;wxhM(Jv3atPon1NQItm5e<ar
zCh{yQalmfGT#BB%<juW>yFC3;f{;Pbos5Vg=a5s|N!I7nGP50H!Gjz*M7AWyu4w_w
zU<^vFuVmgl>O@T`T}(_f_t-3f&A-n#@a!YmIylw7CDd%@oP)EmKOM%DXxwg~Qv49r
zZ5M5FiL}dEH*zfwP)fHWWxVmk41Y+RF<Urr-wZKmI;O<8-x{HfP$y$XQend8Kvk2P
D1?y$}

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v
new file mode 100644
index 0000000..d88f234
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_reset_synchronizer.v
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
+// $Revision: #7 $
+// $Date: 2010/04/27 $
+// $Author: jyeap $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    // Please check the false paths setting in TSE SDC
+    
+    (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
+    reg altera_tse_reset_synchronizer_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
+                altera_tse_reset_synchronizer_chain_out <= 1'b1;
+            end
+            else begin
+                altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+                altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
+                altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+            end
+        end
+
+        assign reset_out = altera_tse_reset_synchronizer_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+            altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
+            altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+        end
+
+        assign reset_out = altera_tse_reset_synchronizer_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_retransmit_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..8021c258d18e2159b0ef5b16b39378d2e713ca28
GIT binary patch
literal 26112
zcmV(nK=Qwf6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl?ijPk#(
z+KGD;{B%w^0Q$*0Fx`m-h>3*3RXtaFKMPT6D5C6EdEJ1Pu5bkmB8&OSq!Z}a_U@X1
z;D%=RfvnY7U5GP)8mt<|&aly*B`4x0qje7FvT<bIlKzMJ7$*lou$TS#A3nws?iW5N
zYX_{yp}&x83=AtaM062oo1=G)^4&!jprOkQw2ejA(8H+-UWhKm_0#yOKoHyA?>StU
z2_c1g(fzCa8m!B)*(1qLJu=kvpW}T>-R!GOz?o@2nk=l<PE^yd0MKIoH))%90i$%^
zN*~?ksL+hBa$=$iE}<Z5vc)UXIjrWOvyJ=wH1UprAK7qc1>4dc6n4w!%?LN)LzVYv
zIc_^Q<dX^cIpMle3pj7&u@pOed+7_WC$9;M-^1JMe6XOk;?A^7pKFPVc)>4nQeTew
z=n7jzi`|@X(zc#R+5Cg@>-GS+pO#N9t~btlGJq{SAtZ!Fp}Z8A&~0kf>;Wm|nCjG*
z{K2)uNX}!O(}A5VSR~hl5sZJK34lT6UuxO05m3!i#<(+`4(tEh5ozRtGoYu~HiHtV
zUlxQgCPGPcsaa`(P8?XaeV{X5NdwH&6*9Z-bV;-?zC>BbD`iS~o!J=Jtn~<!ELT-h
zW|z8$(`Tn)C86tZv90AN@)v22@cNp@n%#RWStUKvI#^Drfu-{&e2oRV`=Sd%3iE`x
zPw=Z6`FeZRYe*JqS{AP?pcd(@xQt036*l$Iyjn$4_J!AFw-4=NT{oXGkvuqBjWOZ)
z#%T${PoYd>fv;Sq*Dza*JLo|OeLqR$mhXg4J{Vc?%-ij%`<-0p0itKN2eAx2n7pF8
zWbxAMNRdUJ4I>lH?9VNOJJ|An&%J2d-gZrtEBtvh#Iu~Q{r<-daK>~4VQP*Y%?bTQ
zuyR!kP6%F-w4x=8ic`RgQUf2;hsH%snBy(HWg}uR|2+4u1tU4?3?x$?TM$G7dOL^#
zp_qdps<^zcJr(P_nUs&-)XM?A{Hv+O_Z=F!ROE91fD1#)(>kMcO23K`u0DyW^=iN%
zAHp5i)3b0f&$XDMZWvGb3rAxP;GAIsRlSABzcrk#YJXMvG_LkSMzP7IEsL8WzQhg*
z;u5$)FWzd(w@zU`Fvk=u<17G~t*AI8<V90aT@UNVP#UQ34Yu(A_A!B*h2g@#EznBQ
z;d6DWEPB*pgZ(L4(N_vS14v)_roj#zHjTJrA)jS8H+azeK97124F)~Vp9We_7l29M
zERLoWmA$GJOD&E<BiFuCzX}`xKfI0QoVc;^%wJj5=2eO|)np8>O6G8koB9*ing-9C
zRkxN7o(7PZH?KCF&wtoT&JaI0-oiMMU7@Bj)CY%}S?eVNgjMv5?=DE06Cej04z+3%
zDc?u-1W3>_T{X~R{Cp*7nYNz<Q#>}_@~(CMvsk!LF~i4;T=GeKM4Yzi5?=F);Y$t7
zeQ5w>kJ}leahx?B`Jr}t*5DWIg#V^@0ZSP0hk1u_IhdbUrhWi)Wy=+Y_q)BnynN``
z7DH71r!te{E9Bk7NYohBT|Jx5(G6taY<%DKxU@><&U#p+*H*%<EJ#&2B#=Y1_nWxI
zF@^HDix%3BxiJI`QiLV-yz-EWxjEwHlr_$@^Qf3X%r`(Z_}Z0~cs!8sl;ybOpO)97
z#xCr;*<UnYc|8jw1H7FvHwOl&`v#|dzTtwjHeVCqYGWDBS}uY=TvzD~)+gAoUnkmU
zQua#jyf<xCkU_S`Te|1{6J~9ODtkUBCBtkD)8~*)BKMhnpk>^$Q>eOw_2_qJmt)oH
zV;?=w3Gb`gW-jj_EgmQPzkW}sSxHY>d0aMTdlAwWWAdXttk2oX^M~Y>!)~)p%DP^Z
zKy@?rC{O%*ed36i`yRLq*G92#oEABqB%%k#I5RsA%~i@){SMTpeY(|((6f~Fn2wW*
zgiVR`kJd{x7l=NYjjx2R+$<L7ru?1gz4$Lw9yMd`1W>f&KB6;AOK647(yCx{-LOt3
z&i;5EzcjYB?3r40)6-USmVBk`O<R&yHc3;C-lX7&$ntmr*;f;Y(b<FGY@<9ZipM>f
zVD#*bji77JX6}$4E;{4L2_H-m_s+p=iMZ@W{#+&j5TuoNAm?r4p;Q5LM7fma_h5=G
zbyt_U2G}gIY$8j(ABWiBN>?EJ5a%2(RbVXzT>7rE9M9ybu=NDAV&&GW@M(kGx~dh<
z5zXt>J`_;~4(c?={$G#U$4Qc}=80aL`fBL%h_vj4RJL>#d^D>mK6Z)mEU1-s3aEGm
zovSdHVK!1mMFdwE(GM_cSVqNKkT=L(CwY_X9&RGkTRNr(f|-ocI_&<s@)%T^eJje&
zqhI4sXEcKJV2^~7pG#|{X@xvg$!EER1j81b_%5@U6Ij=v->&!J0#Eykc%hV*ylc#?
z2PF&#pf328G+c*Ig!QAUAf}``g;I52jCKjFQ5@lL3+b0VmS~A-G=jX8koJ3VGwarD
zH=%-w<6F%4$+jzxgth#ipny`|_S|7@0J;OPkFXW}2hnNd6LYTTVxGRn(w!(vGE;nX
zFN_Wy6d2^Y-c#9vcZP;<6}l+e!NdyA(Rd}`YnLJ&z!{@Pxd)&wB>>^gr@z}_SM&D@
zQLl37Kft41WI#Jm)U?G7BHNt_z%Hv#kX-CD+XF&%`of;89U70L(0@kVTthoEV*C@H
zC#DH)0MUpqP;~6=YVJ;qn+5Y)TnzZM?(0+ETkuKPF5-wY;O34!+HT*NzZ_w6p0Fu;
zdA-!E#u07o6lvS4iSsd9_kgzxi%zXMIIFBVOg-#-Loe&tW7o73HweTkc||*BLN}Aw
zniaH)YRvt9&cK$UI-(tet(dWb4!OdX_a+Mdq7Db^xiJk!%SZGDsiEfcYt_1!Rt|iF
zh!rUXV7;V7<6jS8){t8cI5taXe+9d3UH<UBo$+||2jkns1&msDIC4Ep98(8x>MCEz
zN{#X*tiLMl^oki_0L%RX@PdbEgOsRnG!#v<YNzHMk<G-rfCdZ+>ej$>GUSBl6d*Pv
zE&FW5x&p?zz57rZ)2nkAwHaG0(VxG$7x}rsNTtpX`St+?9b^aEYdO<^GIiQ3(&PKe
zHVJ$HcHPc%oS%Ydwy09f;_ytV=R~&hFXOn+$?rLQW6Vt58~`yOsFSUh+28RzLRHua
zD&q!jAf!_i>Cf9P5?m<FgW(GkiJwJsm@mzS#0o(7lYediju`fGj_7D8E3l7VQwLuB
zi~kl~F*wK%5i?ue2e$V(5gr!>mN|tk1b^_9db^c5S~3hK%r;NgFtEt8{_#4?<wHPv
zB_$sh<`nY68fnzKZ0M^aw%Wk^;I7ow$k90{lipfjq{$caqyKUPl)}{#p+<zUJSTAz
zh5_lTX#R}HSbk{m+%FS>AU4u$oS-HUWQgR%w2$z6KlQbaviIbFh~|xbfrMQZnVVLc
z5X-Lher92{J~9pcI{S8r)^IugJE2n@<AFX0b<PLUZ;W>iD(?4J(j+90<R;2hhTOFp
zWqZwdvzpMxx5L+z_KPQHAjh|Zf`C;DT|9jxO4gc2H&3pc+H)LT2I_(#kr^mRq^25H
z=xaG!QOC6J&-^?IURQ6Eo#~R`zEC=QD@97rTMwsmix<b7WEj-4!xxOnBL_R=nxtYk
zGBb~$mUx=0L7#x>G77zr+Wxy^WIc0O$NRpmtUtr-N-_-UA?4G%-Eu<p<WJ~=pt=^{
z?f8)3%Saxq_7zlPpY+E34>73yF)_;Aon%0}(ArxiU#V7)JU0&4_4cemQ6UD~parn%
z{j(Nno^6~Iw2+gpL7WKqq)K9ZH}6t|#_-47C5H;RFo(}|+@3C^R%!ek$&KsV1w&O(
z9_uN?`~R^*bJw-*x>Bn>I_!cs6s;JH0ZGb&EZuC>CJ_zz?cJF{_~S3rN^KFfD~7`%
zz$quiR?MO3dNcUnWc%_Hv{WvfO&=ec_Cgc3SQe3UbY5zkb3?jUR`nVjmhLE6XLf!3
z7rOB_XXI4-v^YjJy@&jmjS#NZY>LI&Z9v~4WTbHy=s*JOx+kFe&__<xz2smR;3a>I
zm{B8=6$jIh@AQ|Zanvr<#TGDrtPO>Tl9V$}D&NRN;YxPWJ(Hj$1j@0BL*+mS(AM^J
zcjT|Bp&Jb+(eK~XW!Lce5I@Sc<W7TIOJ2LZFtu2wi=g^c+74XoCZw;wS)PjjswqZY
zn|~5!&Cu(W1_wV*5qX8c8tBq=A5eax0TyDEU;+V^*Y)KqGJqcrYOt?!J@{Q?;BB=q
z2=JKnFDlua=)m|<1KdD!E#Ck}Ch?&KzY%XpW6U&oMkt;PhUxVNKtAdnfyg8J!RwU{
zRd59g#qqS#svUiZx~&0VPGK81qXw_lNyqIKW_NU=WEyzuq!2Vh@52#^qr_(!v4*nT
z(x6F;2T4i=K9?R4nw$oh?i16USaVdGv4kXnj-kBx(yL3zi9@Ql&I776UN{je2@h5U
zErN1ih47%NZfJC5jqx@M*g%IP5E0M^c-tn>^NKVhqmN$s6JFl89z$LP`29_T-9C#6
z+tpV>Fv{<xt*s)1d6-uM?%BhhLcmJDARB{$e@9PETP$&Q5s=rb>Yb43qQvG^VfZ0g
zJ-?}R{<aw-9ieS1oZqN<r$x$Sho_^U#ts7{eKV;|1-4INy0DFPQQw8Al0z~_Nbfg3
z+2BBEjAT#^tta8PsH2kaX3xXPlB~iXrA5?1cINk7BYgJy@icQyIsle=?>;n_gFiVC
zd5`bA@ET#?B#);?oTz2YyI<UUpyCUB*j-d^i|=RXedT~o7F@|9U4>zrE)IO|fjO{^
zCMVWXX-h;w6U2PxFSJFEa4qC)m-&XyJ&y((kB!h^yy+@3eLPnKbx|8`3Qy{p<eUvF
z!WpvtM?Ccg<^v4p3oWseY@sx0DKNAgbEN!F3W3d9uV0u7KbV2~lK?)T*AswG2wh(6
zfZq_f?)daQt!3=OV{}=&(N8N(D#F=nFL8mRq-?+8=5p+x$_zs#B4B%_pD^1~U*}k(
zilB6tSqBI&GMs7Qkb=Q&sisd;6t0^r5x@@ND=tCDTB4sYb(q<M@iSo(pNBMvNqi_(
zA@RddZrK}$L?3ESjvf3?Ne1mk61$)Kp3=8idhndj$!Or#PP@rAjAW`{HpNRzX~6zl
zdk32Ed?kMbzB+wg5?}V!A>_Tn{DLu0lPLJdJb)r@0GK{Zo+7yUKFFzWT%F#Bd`2JU
z)(b)BQe^z*9dg&%@CEG!g2hrK6`Y2cwjp`a<)e0P+lREYWVcDotE<nU%I(~3!Fomw
zKO(pQy<+mwJgo=pG{8uD{Yq2I)7s^;$yIKT!72Gbf72=1LdSncz^k>#<!7E-z!`Pp
zB6o+ZT&o~vIIefJ&z@+CA&4h~o&hL7v^t5q`*+avr|<aCQ|-?!CfJPs)e0_EI1vP|
zI#W^H=1fjIaz&?`VdAi7-9PJ-TZsqK@vhVFEMLzV+?rM}{VEHTnAmcWI|Y?eZbeO9
z2ieIOjda{Pvl8kT@f#ep;-7cg1SI<yvsa4;uON~v8h%{uew^BpeL%lLJ$F^5c?m=W
zmOe78%~#fFC5n)~nCEFiNjLp|;-BS2>W~$rXKQ)US#H!*>jqiX10;D*q)@4}*Lo_P
zwAo3TGLSdWU(gvAW}fc+=&e8H4bUNc9hb%#O(70$<h&t9XGPp7{m0n1eFUZ9-d&cF
ztY3$&+H1rgLbSi)MqGl#^3>nmx#dA001Q^FJ3$4re>trlPCCwL{fNhC6M9@cGX@sM
z*8=Py@=922<lh#)ddpU4BA?;Fci769H{&2TE)C_N7IC19mY9JtkAdaCUq!u^$9?nI
ze=Pe0b`*Y$EZ03KGsrLeG=jT14DqxB>NFd3wA-Jj>ccM)wHyE!mi+PRGpua(avzd3
z_G7xm=#Te?Kl%_jboJE?@l}|~p_uM)XQT;elnzBdF+r8V=HB`p;8X2x+4x9U08T94
zWr%nh!|XEI@ps2T4NvaJzr<$5D+HY1ffDawMsTgm7r1pBWaXNy!Ltb5fkZftce@uJ
zk}Hhsft`y@^BF{H*Y)bS5AwsTto^vDutDXqW3)-8rCM)HqfqBB@+Jf)F=M}qEjZoS
z4?{Y9RmA|xE4ge#%+(<ml;oH+t(>m@!84&>$0}N<7g*!7H>OOYMC1qD+`;KFOLJu;
zD$kPua;oH3ob4e;pVi;pQjgeaCW?1o?&>v5mV#793stKjFn5V@!AqY#m(gnO$t~%6
zOMKi6=DS7=jKkP6LdBP_rKMv2<}WbNWJvVmf)cinuv5~WKzM(ZGko>Umh|^Db^^pb
zIHiuL%2|lNbfLk7eM~byb?hVV+fC4>kBl+>P`_|=Y$*sfyWW|a-58qWWPV6=@c%99
zWXHu(J<4cdDU7aA>ZF|YL!M>>;C1qr9{?gX0G=9@bQqxrqv?FiBcbUiR9@6YQc5)x
zDfR7#eE4+(A1ru%W->%~#?BLTTa%9<tR}wyqBEL|@z9pz<fX!P_xOSfEYPb%rZ-lT
zxu=65ASC0G;~)?+_u(+5R&}?3k++Ke<aYn$TjCL%2fy*g|6+}sY_6Ej@CJ3Owo<EY
zN*B}{Q5MgO{YTejgzxZ`P@S2OkqR$;!2Zr3o9-Q?+JqOEy!W<uDj)AaqY3{D#f92=
zk)vC2JNjvYH83cO2e+03+H%hk9Hf0oG1X#=)wP%C)58L^NOu4ER;HT9Z`GLaw78EG
z(W;FfiduFsVJK8r$%K;R5_$B}dO+deKJEfkm=?e(`uGp#_FUH93c5@mwG|BT69ewB
z+S7>{ikF;7SWR1YAhXb%7nm*+Py`offU`LkB8^tG2_Fj{M#v|iH)D*`3{0iL!|-)A
z{nlX7yZ549V;)+To%J-W3e_QGL-fBViMd*O%OWv6;5cgx5V3OblmSgFJ{4CpkpF2q
znR!Rc!avXOgKUk%xRdyCU<J}w&i33gb=dCc^<NhD3?Ccr^W<Cm=Zmx4tL+T}TSERV
zCoTPP#U?D1h}j!qY$_RK8f)JOuV6KQ0JGGcm-JrPP)<fBKhZ!JJja7Mf=z#0z{NE<
z9K_CF7f$bBW@qTrsSCIg^pS;gnKv9kHP>e35_)#5?oiAHFgexCIuVP5^__Z6^hnt(
zL>$WFV@xs9ALKe}q4%+c<sMj5iY%sg36*T(TMSX>gu8k$*JZTA)xvVo#?c@2pT)`d
z;<a%Cujd_Nt?Sw(AcZ7}{y4#^zm)N6vDry-ILDUg3!|U+yN$q<0-FBfkin84)ANp6
zeHCSqRDM4;@NaIenB8%VRy;Q{3O~dwW?evyQeiH-bfyQ<wmF{?fqZ|fWrg1}j@z@{
zW5;^Ak$!15qrg<?=YCg)rhHHk?<B*jbea$C-H%z-A}~zO_M2HnAivKZE7^v5>(_U|
zv54|!&vOlT0S2EB&$kYlxS{)TFuMd6-P!}M?@{c<mlu`6wBK_Nmq8A!&_uU~V$1-_
zRQ9)C+#gGIK65x`emzL?L!0#*Fba!cV)QDi$;G?!xs0k~X%o&M_)SP25}aThE3krN
zkm)Y>VVaUbx;Px7^dfENN|Z)~guFeMEv^?})!-QFm(mangJS7rdV@cVh;HNVNAaVl
z3QA4I4ZDQ0A)31B-3(y>v&-MNQ#7r8?b48z$0rscgA<ZX^R0EajmAA&+PUm6Bwgd7
zjm+hRSb<qS{qKuN+3Rd9gBHUb-`u+{$%&cJ1KBF`3x%w{HAryb7010}m6DGx>pnnh
z_qaS!t6k1gANNkLY`7L;C!2&tY7KsrC_LCM+IWbISmg=usGqZ6#r6qZn+h^IM=S;^
z)MkFWD#0qth<VH`5q7JPj2vA~8Fw4Oy1sYia7RV=BIEKM_{bG!v+CvLCcPPqk8ea=
z#XMb1?3WCrN8H)Rx3j@=5uC5MF1M5jZW_&8j^#T3Uj8*MXQpP^OPzv|95!6_W4fsZ
z9wpfdf;$2?gz0n`_$D;+=mC*9Rt<{Q>qIc@+xx&yWS=o9LaQAWRMZqrx2(_7$9<@o
zYo!}Pe+i4))?XmR=JFcd;9`+UqcsxwT^Gc=beqjb`*BNEaALc2L7UGh|DU`;ycV-Z
zxH8pX#K1n4ts*oPRoH%$w_9dB2snWw3v+qdl%P;I!c;6S1!qao4|J#O`<w*5{aGlQ
z6rxcei}kYW-f?z^c=0msI`-y29Yy^nq#Z3|N@RdOChux)<>+v5vF-OhmaR#CNJxyL
z^0~pjEaVjp7Df>ep_YNfVQ})<=0De&&xifbMEM;nACgvvp7y8YcO*E|)*`@u<O@$s
zX7PTYI#XuBU)KSb7kReIWPsPEvdPsF_2B?l`AY@KW#0nxWV3T=>)%ihNLuNd4K&Cy
zsVxA~{5I$81^OB|x#IXMR{-j@7995m%&z|%)AI436jaR9FO7{G*>d7`6EOyQXkQHs
zYwihBmZGHUjV;bge58yKYQ|2gKl4wr`1WG&KDV%gkiYK!?N0v(l8g!)M1?44P*>y_
z)BAio-8dLL=id{L6k@`0i`8o&$gqE#p#<AHn07^N!jYLKdA2>WchkCx04xO7ZxY+o
z;>$iw3!U>t{%?i3WHQ-&;+(O3hYuDya-GN%Rc-lWx`hHlg#6q-An~WHq*FEI7L-@J
zNs=F;2%L^vhAwAJkxm}A?{270KUuFDS~BMzA_&LB#-g+`s4DW*(fdTpw{m5e^gLwC
z?lle(y{$Sds;SOgU~k-GY89o}-i=i7H3wmR|A6B4)MXc=l7df6HmWb{JRzqs369Q7
zKl9S~NzA0S{N!BqEZssW_WE`I_3Y`{*MiJ9tM{Pe5f5TR5Tj&Vq|e2upz1TCjJC%i
z8i51KcAQk{OC;C;Ikq?&Q}LCyS-TE|vH2XGD3P$?_)Ukdhq)#>gV2=UdkEjc3gq|*
zf~;t%A-SG3uC05-&dj`W!3uxB6rBt0AaBNvb^n53cDWO+netAT(u&}7T{=-Q?mZ`t
z2Gpq=jX(CGF=R8FU_{99uam%yC=Nk;H@{?3ltV+D@Lz`ciR%G!0{N9ij>vZKFeuw2
zgmM0d0F~s^2Cx(Z@_Hn21?bSKcnw<{mtppFgPqIjIt@53RlrweNq*-pO@BB+)xXdv
znno(jt^Iy{^VjK&-Y=#L*jfI7#T`7k=paA*#DG^soSu^!9wwf$0`is65BeV0IO`4B
zE(t$C64M?EF}Ia$ez>ZRR{;1Ys-M1AWT%1t`;o7JzoqdHYgOE63f4nCiJ9A&LwO_;
zXc_hxYHZZCXepEJ;&cy>jH|58-&s#T`?h;T@tZ@nWtJ?z7(Q~wzR9#<<q7xOcObq*
za0hP6Y2i3VwLObA>+yKV`PS1&r`{#mP_n8C`l;(|w3&EKjOS*Qi}8y(C-VKV$Hj&8
zZjoJ~qj?lEbB)A9z;V5%FXU3AcJqMfcqIpYaf!$qj7l~uXqo-U=26BIuWp_L91*H?
zlA8E0T`Qr_C&K)#>hn)>$s^|#y4c@4HM=J$xV*!C0>5ZW>j0=YlM|yCM)faEx3ahY
zmvI8^qIG5_+0eqCe;1>*c9h7?b6G;=)!e%91Sc_?N}u2(;%m5ZUK=^}`_<l-#=i85
z$DFW&b9?E>!5?xxqmjw%0=bgMh&clqK17#{Y@Ld_N5CxnjnaWoo@&^{rZ*v7r|yC<
z65j|+znIY9$XpMxNSDQ`MpXAvE9o3#s$;wfHjFNU_W{Bl>s#6Q<u8~8T6Bm1cz`fS
zO2+NEY=|PKm_F~=Dv#?vda0XS&RoR|I!9De6>|<m9SwH9YB<Cb2~acen<M^V=c=-y
zG-=0Hr8BT_Na7yWYqTn<59y{z;#-iT(v4$H>h`}+hZ;hi;h&q4uul<uzMp3AM7;fd
zbk{gU7e%_4!cYKw5_rN70{=SZnAF&??p+7&thx_>aqA`{;Q#}|u<UFVyQ7GL{B%z2
zs|m@t@dI`+U_;MhZ!`_Y)7-knRylh7YfWil-8ohfB6s@Qo!-*U%mv*6rvk0jJ*mm;
zVj%Yf=1FPZqtV@7ReA+fIXmumo!t_+^P5Q-Pi<qG-H{?SJy#`afsZG7J)N^k9u|m3
zL?1WSUo7Pk6@9n=&R6EB{t9IHEsekMC1pI~PV`G)+1E!1aWOc?bw}Rq?q&n}KaZdf
zX|G#?DXmx`4Dyfpyhrt(0na&!=UiclcSK3f%P0Ady1r*vZ79WqJAjC(?buO}S$)rb
ze1%_`z&#ZXtVc*=5(g->Y!8eiI6%6afQ9k^0(%i4%_2!0HHF0iRryP1y-Ny%ZE#h%
zk!o!JlSF+Vs3yMx9xr`f)Bp2m_QmjUUdoeZl`$rt0DgnmiJ_pZv94Ux9wtQS{q^Pi
z)BydNHcIVPWvgA$ISSkzc$&J*dzijbqTn2*FLHkTFSf2Lns@qS0dqTG20ZeeaO(}+
zNIWKF{WdJe7ye+2POr|LV9<mU@YL}yzPZ&ge)QQlqyD+~Dr8&icKd)L`nYU1AAc~$
z05VV}kD(|cLAy3J&lnoQ!MOaJ!*W7%k6ExE6wuU|2txF(4B90c+7Gb-5Q8gi3$N(x
zXP)uWU*G6=#q}1+1<)8bPsJEkFJc$@yM1=AVKceX0~-sE7A{pZyK?+rXsGFYpa!!l
zCuVa`|5_PpI=;z{uHd-hQl1z!+&GLtfbbp>5i`LCq$<ovg6MGSfV9#fN(QVW9B)P7
zu-EX~uo+g~kh!87TQ!`$Rk~D^p3OTlbJT`3c6?tqIa>7jfH71((vf%hk5U2{Y;aLd
zy7%K<4*9naUn4pWg4~mr>{AIUYdQx6A*tcAimy|TcgvabEgu*)7xbWQ{WVXWE2o$M
zwVzIK>9EjvO*JSaq5!WyO-!Hdd~VUfhN_}tRoSKmci_z%Su&rtZKuQv5|Z>9JKALz
zxjkg|QZ6k}qDu)n=L~~(qpO$@a?7FsanMttDXQY=Cq?c}7?bn)>>!};$>Zzb(rBSU
zpj+(($++lw#|3q@k$w10HdT!n(4vf_xqd=PBYZuC0$dqpI*b;Od(34!{oVtMpe>8S
zNP)SjFCB$Far{!dG{*vpJguDDbWc?BBciYUf1t+bs(m(f>c;9K|Gabf#_gOPwm<J&
z$?&-F0e*6XSfpU09XOE6Ixo1>_A+#uwH8JGnlS%cde-rxuRKE!uc5oV_P+fqC^JFM
zur`E;=v6|EDWg7$1!AUG+Z7^RF{ciKWu0F8v``Y+&OjLsShy!cU`V2<ZdPb2go>Yp
z90(VQo}R&iha4eP@!e;CW%q|{jC&(Jhp<I;XQtbuo{2<?s8l$Yktg0QPPBbdvh%ea
zb=i(`qNM^{`h>4f9r13Gf&$5(t#Ekdw)h;iV8*HJI~>KdFAnJA%#F~i7_bltb({qF
z$2H(+b%gURG(2|rY<pMz@YTAY$!_Swy=Mv6U>+|jaa1SvkEfdaup~Q|lyeFsBRl!^
zdM4v{swB?dd|a}(Jxo$gjc;C83rW@cM>3}w5*OI~ICxQ<;U{j|DWDlzK%lSB3}LXY
zDWcR_Xx9I&q{5H5V8kq4xh`r#r0J+oW*uORzNqoOJyZ~OqF5E-``Wmkti|dIZ?ktK
zFzpjQ%-Sg(>G44plD7;?OmzQRCw|8Amnu32%<39)qVrDcaJJauA6ioOTQomA<YP|&
z>#c70=2%g)))srCAir!9#l^0rxHJ)4;qwaH?e-z1kSYTfy_Cc%XP|Geq!ybgKwFUB
z0h+JsROD7o+~W6P9>(eu?!a(EG@HP+Bf8esz$!DKwm)G>E7+<Xk9EGUlfPCAhOU_|
zwcSjiC09Nooz`5uOy{}LqKwgF8h*CLLz!Alno6je;;yNU1?Qsaf;e<scY2;Y&TwnJ
zd$LJ_h}hLlWrT(Cns|OWoC;bC?33eSKz_z+s398BDJ&RU@!s(Mt|>^p4NH+47@+FS
zqSqNhfCZrVrGJ0!Vzcs0RL0yOq9b%L#v6Z6WdBxCUR%9$pVjnBUCZC!^3qbx*1Uxe
zBJ_u?hKjdo2Ycz>AjJ>%XPprjQiO+AD_uP%PM$=ocgpZ)@0T<KjiBFo@1YKTdRkXs
zG^bu{lXM%lmrGc?I#}#`ckSzM<IV6AWBc*uR}fN#T3eK<4uL<ZxMtd}aDqF*R3RnB
z*j`c>HPX|YQvF1)ba(XEVp-L%9F;pqd3~KQ+?>)x#nbpQlt@8eX>z&u=pQ!O$<G2S
znKTdQZ_wtN8<w;QW66kk&T5DWyX~7LDMJUEd;2HjsF@_u<rR^w_8tqn6y$XrA1G`w
zJ%wk#wc@P2;Pq4rG3ef8*FpyugCP2NHU<F2b>)}w;%pDm%O?xr1IJ)gui75*O}dPp
z#X*90^Erv_7zoHvk1p1(wT+P2LDpTdr35a_Rx&0myjMYerS??(ZOX?!V1U+LZ!syf
z8SN$J`|ihwisv093(YkYyl){%a38-&0~5cG($1~QJl!*!+t>2Ali$ervV)k#w5qU9
zDj7GIGV;4sMx{&2`zURW?Fmx0YgX4Kodf$7UJgBvdNr0I<g9C^0z820yaoY?zMd<0
zSjx74w)hvD;(%)>7{XLUaFiT#*XheKp1}?e>~XRgE2&3Pmv=2R?Pi`Olcv5nq15&L
zH!9y_a~A#~3LXe`ATe3`!2Z{xDiB;nweYp|e)HOH;cVNJF~M}Pi&em~+Qw?@RW5(@
zTylGuzF6p3D-(bq{ypVw1kCTSDJ39qrtZ><ROCHtIy;p+4%49EieTYVaFsOv2}i@9
zsU^c2O^rTjb`GHSneOSlc8!#s{7k7JGNh1&z7fLQG)SWd#9AXbSE{mS=gEt?9EVR;
zuR7$ZoUH-A7F^-?puD2g<yb_}EfYNjDU5hNTT$r<!grp#ysTy80dcktYB!}_OsRpd
zG#WovTdAkdzCeZ&81}jT2|}d0z}yBbd{D)}<zV_RqSQ6%YbUp`&$)cE0<|r+RfOfH
z`OIt1Z)1B6iOIln>9{&w5u{`Ce#{bZ8M3n6D-3&S*Fl4S{(j#BJ4b(+qdx3%Q~%Ry
zd3-gxBv*ub1h(VLH3UtXc=uxGj(dhK3}MokSH}{Y!rz`}n>m+xSX?9N>4_KWK%mC4
z%tMLCVA#F4nwoMp;K<B35bIR+CpNXp%uPvYaBy>x4;0tIdaf0E<yPrdle)iCT!SKi
zdt@v}5c}>kdv?p+=}c|;0fYOtk7_ZGUiGoFxU+cM@wawo<<(Z`JC)nrH&@6IciXd^
z(i&h9%J{CXN1)jRWv{dAlE@piQ&+CKmnU4kayOQ{Z~}gHK02|-6lopBl$>}Jv(#!5
zk@>uzPUY<7NYr}SNyn^oFgfn=?9Uvi3^s6kw4B&javivuXF5ptMa8;aOj2;R@Xbh3
zsq2&u#br9qnKtRo<BHu=jE2;|G5@Rhkzv8Rp^0PtD<YDgdK_#ClU8`^kmqOr1j&un
z!A!<7W}u|ssu0!H%C~0`pxmn`JydbvvwP|YGU?kn6?!{*`L2JT)`j|eR1Q;>S*Ge*
z|MnOvMTJfx`~j~P_3Ps#jw^h?fc520pO)Z1*cckPK&d#5&rX5!k7#-pM#+nA&<C$4
zDP93E+<sZQ<u=T&-KaM**elao@Z1cOYh;igi<VN6d*tIjVx?gOpOiSQg2=qu8>?RV
z_6jFhOac`%v;<9ct2Zqk`%@TyX-f>uW&UJGw3>@LNcEP#Y!F$acoz5h=XiheUY7Ls
zedQhS>my-S6{kET)or5Y78?9)_%-@wPXWIQCI-ntP(y0+6gFjpQruJo@t!}|L^>;=
zVmwUQ@NN};4_b3f38<sI$lsoH-;ANIOKR|(okNRis(LQJU#qeX_eeCbjKu65BAQ{K
zdsqw~&%MdvRn0(#H}gC16FMRLyL#`}OeaZoWbyKdEhkQ$yjm;;0<S2=K3nrv7DdeN
zU>;1CvHnUWR!ERRA$L~jdx{RoW%UfH%AQEkFT>c4->ikQ6A(FaaR{Q4g3s#`b#acH
z$H<T|x2XLQ<6`&pee9|iM(M!0tR%egv}gvl<Y`YtytB@7r5s>X(+8hKQmNyU3iaMl
zt*)N4;lr<@o^~g(uTY+Lu!13F(X&Vt+>`c*!mY&?K{qNb=xp^tF1fy!KKCycv=u|v
zI&8^zN~cxiP{GM{u+#rbj#Bq9Wtv$Y*|fYX4NP$8Vx;Xs&fU9{-VOi5lYyiONtVC_
zuHg+ZXV_E4H%`VVPcicMOGvt))IRdg7+`$bQ6yoeh1b`CBRc6GZ)J80yg^pekdAR;
z+hDzGilsXtgTS;An?lp%G|55tiZZK>vYJVaUwpgwxu{LHlvZXpRj25tszM#DsI`e?
z>PY@D(nKxEl`Zt($hCr702s-@O{KC4LRp!_^{?SX?3A*_gI$14z#lpwm*B=pj+Qjo
z8+-cq_8I1Lrj_4GsW-WlhfmVj{jjwyUPptZ+MoXgo;FF(P5FUhbTI^D4p~09Mo-kp
z!2}cJORjngO<L+OP8aS*rIDxPncg>?Dd2=*xSJoumog}=T)^R5Edv&mWJ`{d2>mL+
zMr|M`@05A8mKe}*>SmwqrRm!%jChdywZTf5OuSKhTzhQ+-#KT$)|eDMGj)<i&WBcQ
z*aMMIRXLv?HDwU>)Tq95eUL4;7kvYfjs7r*^*?uJ(ch6{BC?U@CE1^g)}=AajxH}O
zD6X|_JObDMjzk05x^SD^zgJh2KNCp)p=v>pJoC}r)peIIRc$lhls^0hHyNfX;00GZ
zAlw=JV+Smq=TE{w_~UYV%1?p)^xvA1;*;%0j5RyLVeL{m=L;K)SUlW57ep^sPZiTE
z_#9inN0qBz^i=tZ@Lz#|k7ob^*({lxr1$3N55nY;f^uB%Jnr{V74n)uWbbbHYbhi_
z->?tq8kg9Uv5(JQa))x87aHaU5QrV{QK!h(nztof`u1;%3Wr-B5{(}dj0o=nYDli_
zD2|IEl&p{_gw_z!s%2{v(AAuo)qt?v_qh9#iTE2{DsyXvP9+NCa&oCC+O*-OsftK%
z3pKZkPajSnNA&pke@<x1$D?8CxrkL}DXzT1Xj~dnC7|B^i!wMt53u@I{D#H)_I0O|
zl$3&p$T85@1Eo*_RF&w+eTZVZgw+PO9@yv5Gqyv0sAy)e5*E|nCffF9YMzhvlZL~4
za-#@GG7=vTcCKW>8pg-eQ}xnDumDa5#ug7Lp9Q_>5|;%=--C-o6RATZRnohNt{Z<V
z*Y}?yPS!NDWhhEFJzv7X#-1yPL{O(J*uh;#4$GW);!1>+!@}LcKxswd6LbpJ7sF)b
z<#AGvIQxLomg9@DqbMP|n?xnuCj!IL?nbqZ;4uNkdBKY=H0>U_FAj_^bOL*||1JKn
zYzzPgKBAOYhRzrBjFA@e-cHPPbFxWPLyDIJ8RB{HZ++C)f_AmU?SZw-4G(2JO5SC3
z1SOjE3r}6n8b=@x9G5f2IgE*1xdi2}L>4N|$<fyT5uU|(>!|%67cc3xMPk2-Pc-MI
zhu{4*`fy3Cx#E=3gL$KaH$X$0GBBjAW27PVo|?|dMS!kkIt(V<`R29*Y4L0+xi4cj
z4kRJ>_f1bTs-z2jns9dvGGc0U$NXK|YWQO40QLY8f8)}o{@)HuLQEkn^(TJ@yCbY3
zPB-&5_BWyd<h!PEFoE|NC>CcT<;U|KvT)=HQgIZKPUcK#mY0lgMnvBwLY_G3rAxm1
zWp*k0jR1N5X+cOna+a%1YlFk-bugB54O7UF_L_gs3(ph{3*>Lji)z364wq9r0`3VF
zR5w(sw@Oxdy^8B^u~H8u^e%4yR<}nYFT~(;&Y<Vw-!k%@Ta9V$NO~V?)z$=TEI>Ke
z@Db8zVd;J57N9}j99oe<f_;9VRx??#=BhYGoO=`=1&hHn%5d-j`4I(qHGry(Ej^@-
zRuM#d^Cl(lr^*U?3H<-Jh1ZH*-Jff>aI>E53zXnal3S4%9qBX@zsbk?qNh@6WJp{x
z$I1u6VzPW;UM@?|HvQYqk!d<18Rv-lPMRckGXSHY{?26@L*M=Ob3<2e2b?*`epOHX
z<qQq#t1~Z{ZJMYB9g;948m~p)fMe&)$eJ82Q+uDCCfcSeFY{x&k^*rk`mCv7sqfx$
zIVI~$v;*Xw+6|##vJqB4Q(w4d`M|E}t^iPO6|^g{G08mYL@4bC>Due<JwnW#{A47)
zPjj$A<&&*lSX$}@?-&Os=yD=5r)%)sQ_6((^62F_J;y~q+SVh%V94A9P^IOPXmy&@
z5}ZDqq6FuOeTs9i07>_ymm~2#COFT9MW3G-t|m#_C^qQA>S6j0s2R*7n_v`6|5Mjy
zTc4=DL_^huKfx<O?9i5N?S4u@t!ms=Pkm>*q`Y{8eh&fXk}7}C<&KfI+{mnngH$PE
z!E4~5u80c3?`X82sDhaCbw&k2IWqkSc*hM7ZU(T7m|stJ!tBukh1Nke2S6Oq13dR)
zErI5>3zE`)fTv0qzh&ICb#hUtV?aif<UwPK^j0-BXH|wV8(?CBS(?;Z0vkXKz}vp|
znB<rHv<GYnp20POm7FLsZE+OCUwJ1btj7a+z`*!E6oL;L`8&*mXio?TkF;b@_Z?66
zT{v2Ri{wZ}(Gzs)*5u`Mp>19uwAYti-<XHGyA92Bydu(m(WT#5Ys+-t{-9ztOBweb
z6t*6&RL74%Xk^gmsIF#aM~O9gdpfUZymdK!__<EaVM7Q!-K8ub^(*iZ9@Y^x%lIb=
zARkNqTnXxXh(2~K=UsFzZ;IG0HC<an0FE4_02{ZIp-Zq@J6~TtvsE1RM%QD>kqEDT
z9l=7(I=+xs3X%Kzj>8{qNPO^upAxuK1DQ6xN&*T6*iF@M|L-g}$8gxs-eh&RF>O(J
z8ksKXnPBdu%vvsBfCXh*uvBbNaX$<BAwMVQ+K~y^{b^ok{vb`a6*9O#N7*Ace`2wW
zEkG_%I+Uj{hQuIwH;<^N2Rn)W?{}Vn5<qLUbpXmoa#i#qy*-rKTp^T#NcV5r`MPo{
zAANQ^0Zwj0^)dmTgtj0?XwH3v^5&z(v%c>hJ^Lt^rh1vFGpys7E2Y_#7@W_=b4d!h
zc8$|QlYTXF#Q0yr|0zxd$9<8l6K=yj{4E1<4Y{1Kl@y(}?e&Ud;__`bD>voM$SypU
zq!592?~eR?*q8=Z$pTvs1&hRUrUM%?>k0_>^*)+?q${J$C00VU1q2_=?9A<xjzXya
z3RI^5Ho;!<N5uT^ZY|<yUw%iU(u+x>;a)kmhnkLRhw(%JCS;bwLGQmVOvt5Df&FgY
zUj1-14@NXVGx02EeTELx!m~P@c$dVxK7bYY_5Ukmxd8Pm=~~8IzK`e|3Hcx4>&$w+
z%WpeQYfuWX$oD;{)kT=FKcJV*xIM~*aDYfjwOeK`%5t5JB|x;ga;74#oCWWM5^MU`
z$pBtgij5fIe`C<7q!1*=h8roz^x-#XgOx=Lh@yQE&joSKcWiuet0De;|9b-@>TP~L
zQ0o+b7!@q8a%B%NJECyTm2iw!4G-K9bl@QfeI#+kwDgGm*KFT=(n&%+!S(cj!@sWE
zjZw(s0T;p6y+UyN<U4je1H6i)Lc;AKqx%kzOag{N4J?zm$DQ@)sXXy4V(=@0=K1E$
zk<N80dD$z%i=aQ_xp%T><t{zcz^Tz$jQ9r8@eNeoce1b3EBlY&3-7ol(IlA#yVbfS
z*#zFY`|IkE<Y)&ae{ywEIIAi&=&u;jMx-gL0AE7LT1&E9jOgFe`bUd9RX)=iH(2)=
z7Cc^QP&@2|Y#LWM*}x<CF*eu`uCZS=>{7oL!IGT>nf2Fa@sUg1CMqrBlIbEi8Sk>D
z*Wi~dr&FDPRU9OTiG<Xkp1u|#Fp&u_SDRG;8_yMDEu68vv*1MGMvkiRSSXY-a}YRd
zsH9$!1DA<$?vz#-rDoqkO1eomAJ6b%Ra5DuuLl|;OTu_fnksX7K=GhCJv*0`DzNE$
z1;&>F7bsFg&9tf-e{twz?$?V@3$*@TsBz{Riqyu_Khpy3kl1AC6c;el_q(iAAi)JK
zDjMs3@jumD_P?uF{cLQ<=NGpADGG>YXri}e*mUkz7@ui}!haGPx|6&Mr;7ovBd|LZ
zk{lRa#MseEQKcQd6ljUp!oMVKIJRD7Tp)5jlK#kM5(Pq&^d3EM98Mumao{1nAwOuE
zNV6%yt1Hr{quUzQEsSnNTs&-v+rAnV$jK@E2MaUl)@M03q9c9p6nW$vcI~e8+!?L)
z*O(KrPrB*6S2ylpOctKBXWU8v$S-yQ5)cQs6X3BgA~(;e2&;SgGs>kL5%IhD^7Zb1
zBF9;PI9_wk`0lg^e*Wyo-(PJs<@$gfVx=5kV09mhvI)Z)(Ac|u*tXA9fTWn^_0(v2
z7B4;id)H-A0HIm-Sx4Zm@xdvoed{ohg=K>>;)3|joogvrRS(9R=UVv~6Igy`&&0XF
z*Hb4_%Li_uNKE-IhyV8j$<U))kDb;@8&*O+zbN{)N9yTCF+~;uGQ0En7;$G(*-=AW
zgxVH+x*p{QBC<^#s&Z4^jOO(*L95W3NVxo_O&T7udatw2ve`LYB%8NUNL>glZ$%gf
zv6IH|9-zmgu2Rz_ZlcsD$EU_aA6X~>#*Srxp0rrX<kBU<fSXane@9&T*)@j1(MC&!
zb*2EGm|31^*On8UEDsT~U(!Lf{NqdV@kaNVyp-DhK`mGhv}9f#HH=WaN}MsP91`K&
zhAbo~9-9~gSY0a#8=>{kI1gecw-g6Fr~x$`3Y>WM$x}l|*R2RDw1<$P()MT1YB3%@
zyu}vrBjob{i`ALS;Hx0Ya1;%b$6e*qJpMCme9%POP6`yXxd`UHhxBlv*h;}8f&CJ<
zFN7U$tdk`h*1_kRZX<W>H4qt-<4-Pb3P2Qzu-xjdM5C=<Z)kNcYZpTw5Q^oKsP}Q_
ziU)Xx6Dy+(d7A757h)DwD@RbXktjx*vNIB;@c(<10gh1)Q_{>VsmH%6o;@!iq9^=&
z_ER8Rz$XE%nkU~XE6LAfdd9g6u6LTh`bXqBUF!jd&HPv2N;`G(l-=Tt1#IgW1{btn
zcv0`d@bTsb-JIu?j!GT?cKvPV`;ek$44bxdq29hOL0SMXDXD%pMr`E0;-8;E^WIx>
zauFuAJ^(QaZxqwAkpd&Z|E99Fw3Fv<D^!wWs5uxwoE%Y=B>f~voYr@B6e^BCBVN^$
zu<V9uDo|)Kf$8@=>fjEaQb{mI%r(4h+&VR$t5W^?vAr&TP%kj^h=VK&P&tuC3n^<I
z>$$YyoZ)+f<Pk@f+YFP}6&(Q&O6qMJFJVPbEUYwMPvabziEK~YbdK7JK-Kx{R`kGT
z8F=Kfd@(_Nq_!g_Ml371f1U)%?WscqUnmi&;@~NdmA_P%Y_sSW>Ke~Y>ifM9EvNj2
z+i7JS&CgT&Irn=;5^;)Fon4sC87;ELiAGHAyg%wugSKv{g*Y5LJiI#Ytasf67vuLh
zg<Su1A5zxou(&G}qa_OZ91#=qj%^~kc?W3NQ-l{!TLk_cI94kM!TF}n*3%Z>-oR8J
zvy!&B8{y-8X;)l&UUc|`KnpF3<uyXnrLvL)M1j*yZuMOa*}!%o548Q&gL537iJ+dT
z*`<^0HNhKjN8=;V>Nectv{Il6%Aa!d8ocg4aoc%3Pz7~uaWr6J$D{cN-r=r9A+Kdz
zn4!0#`5gjj2Gok`?>!ATi@Zt75s=*Z!gnVC+YI_T6!nS*dW<L-UP_e2<3+9s@<tHQ
zP(pglO(l&UF3z;V=-cCSfJH}WRy|4_FL2~#))-W=E?(FgfYT^ohRD^ENxTh^>W34$
z-PO3gK(HFR#$VBy)tMPt36dQI{LY#4aYL9XvZtY=c#W5$*7L}P@D5+ln}c)pRNxA@
ztFVu7fUDn46nhX`kfgDP<4FjyKd+Q*Z@vFU1LP>m`Bsd{w%*thCNgLek2D6moR!&t
zUUdlmigm2vJfFbqT%3m(T>`w(oF5QW#bG=XWaKec?Oe~<61*3n&yo&Ee)E-A@mj+8
z?$?8{Nn?@FEZ!4(=bn=^pN@q6lqQj?0rMpc+JHX8Vw@mMK6ydVLPYp)&GYag@HBtG
zof1N+cwhl^ZFsx-L-qe586K#i|G!19ixHv<+_~4Tj2IjQn^9fYf+52F`TZSMarth(
zYz93eKIh(?lycn#czSVHSLI^XxfOnjFK<B2{eW`N<6^bJg~ULJ)qOz(dO6gaj%~vy
z+nQz53YBS-N%MM&M_os<9WGs8*1;_6h4hE}2GmE~>*tu8*97OsM{}L0*qB4MXJXFP
zWPi}BpyF`dNtqjljs<S2Z$FR6xU8^*4PlRK?R?aagp=mX*}(*=Vol1VtsmWM5y00p
zGB1x<W|_)XY~|sK&c+G9oUSOy;-Eydlyu=?o^M!>(`C^2Zsf47^y&D|-6qZtw>R|S
z$Q5~-o?j)mf=^&7IH<e3YAG+8q)EJx=8U9S+}-E=5*Lu@<(G3W_pz0x*gn)29H8*f
zvIh^EnP#K=5l~=bmxjM455De8j2(&=8Q(aCjK8LK1OmaJC$DR_W?_tVxRNVRNo$(g
z%tgDH<arEIm3h$HIl@vBFUD5(%jUEGxkLRRD=SzCcv2vrdS*0NDwz+d6l=!{b`+U_
zM)T<1rRl1*O`p7k+I==tA4VnBcnTO{4>3F@!3&xgqoqw=%ul~w{ze&XbC-;1@LRO4
zMJso_vPX`W&6#M{(nUz9!mIFnT)4)i`z7;wGVh-zR@f)~IF;^f0KvgIB{n>ih@HoM
zNBpfp7w?3L-C|xEG`K$V+}TDs>n9po9!*8!b@2eS#yL9Rgkd7A^gsuKj%K`m6p@+3
ziiqrjGdqEK`Jkn=Q|?kt)*g{k0_~6)HNb8ouy{VaV9hd9<$0dq+?pTc!xz{oSa(9I
z#fD34h&LuLO%@l9n>fhB_aMqPhB7!KlVtTLa1A_+S)L*~;R`dO+FqK#(tU(<U(U`?
znJaYTRSQGNMK_p=QUcIdL4o)50ofKk@U7IV)(h5VI|?}e-Mrt-^QLYeLfR!i%POp1
z5K!iqnFO|*J87gYB&C~24I!QP>I@syc_{Al94IQD6E``*q%pPacDT#>iXcA3tLZX^
z%DA5?f?&i+m$`7`-lN0|YW4chHhi|fiO0rpmPtBvTFaD8C1F?}Q;Tzy?=UEf1SFdy
z_+{j>@#&88K+1O$lHl7vQCXfXjMp4(j?&AX+&A=@3FOwzxB&aG-f=ewc$Oh$du$vg
zZzKj;q4+YL(!oZCjQSfl;<V@o%U7s5jD1F)6kNL1=JkEO6rN8e2Snr$I7jPR)xr+Q
z1MvnwdAWt7oAp@(m5OfAsRDKy8-W$APQt5-&yGO{1Ja!(MYlroZt+_$f}G`sZ$&3k
zelC7C=3A}T!fE5OnBW`s!@1g5Mjm?4WYjEft}A47+M9C>HD+sRk&kc?dSbdfrR9q$
z!`5<^q+-}!t%zxiFZt}CBP+H!{<M~wcYObrcT>1A24d{<v;fQ_`u9piBy9ldTUtw6
z+6uf^EYhS{;5<K%5?$yw_&|u``zG!d?C_|ZKBs2>?v+hg0cH`USiztgc8<FAA@!Cp
z-DXH`JmTNEPC6vl;tTeJU5=0KG`5;WrRq5cDE+RSd_U$9TH3zLqA$dng)6+1b<iK2
zv7oda0?+QqG<PSulUyD!f(TZ%f!?Iseg<r_u?zhfbjL_ZNVpf+xS!<d)o*ZLEjsyC
zIo#4@^Qe!}vZ-V6@o}^HyXP$HlN3!&#pJ)Xo<>Fb2*O>!i3n*-pvH?#{Nh=c`91~^
z>@Hv}07{Bx;1JJcvrdh9#sr{kHb&tzX_5G7Rai-8n8Gx6;ZB;UzR!zibGS|J@20SU
z%v?85K^Fe{MaxUxtQ~$R8K25Sn-~@baZ-NiOdz=1D(K9Fv~FI#(gXL34aXnV&z20&
zclC2@`W_;B<V7K*BJb_Jn-hJasCB*OCT7G?kNmW)P#N96m>!pn3wXMb%9^HI%|`WH
z4z7s}5*dcNsuJmUmOe;1!?C##HPn@HzUrlO?eV83Gtj0cxGx2Q7l@y%G{;e0O6j}P
zQtUhFv0vBUBQdH1EbBtII(`@aOgZW=OJS9R-Ikgf3rFbrCpFmmf`YafI{4H><^Ug7
zP>^)n&^|5^H-=6)t~KByKYQMiVV`WHo0JXFbRs1ZqVX(h9*1;6=}G?^HZbrGAkb3C
zb<Y4eR>d!?NvI;E)4h*sbeZF9j~{y5?g-jz9#yD_%slR`#|!p>Ndei+oz0FEs^$lI
zMgrkVl*5M1km=4Uh?tR;^-p`Z$NR>zDt+zHC^@=F$r&TyTFs$wO**DjwkAtAAW%{z
z8=5b^&y#xuYgS~CfuUt~C{U0;X`DW_V^cHCzz5uAyIvS$Ib9VzsJ`Ub1WICzEA1+S
zcbMZ{YR7k9UGGZ={LJ?=gZ?pYIj@I7?ySqa4!AJy4oh+=0Ex4H@3mKrbC>vz6=A}A
zb-1cT<I!h`u6qbbcrxIM;!-U@y)lNRxVjVxEd8rm*X4yoD>@B~ImY@PwjyV(Ls2V?
zSKSan>n5{x3;NLa1Xd=x*}|pI_uNvi2=~a8M4m8T3n$nc+5wj7b_SgVUvr~*hlo&O
zjE%q)AKk8b-lkogPc2U?bFJin?WaxXK%RnU9jE`EvnZF?+c6q)IPe3h!*k&Pa~4)%
zG5|DlvUE<hNH4JY#qi?u2s=0V@%;C5C}I-8c0BGBZ8=kLPJMIU-ZI-yc}+UP3~tW`
zo=iqPtVheOLTXvd(j0uMLheA2{t&v|uP0YT^3;yGtmHgB=5Jxs!>eM<o&WW?h5+B6
zIiCw{G`M3XKF8wV+Tjv>L&V=LrO8RgfkvN67N8#|^Gr<wJXPzOwnP=sS!4e++|z3i
zc0Dqr2JzmP6;3VMhuGVGd&h!9CoK9h$&2Gj8xge?U$a1{Y|&#nUa8c2)FfY&*ky@f
z`qzy}S*luPSUyKxM?nTYCdtDph+`l|A~{ju81$7fHnx=*{>;(8<G!_c>)pYR%OLek
zrtfmbJP+Iw_d2(iRvm!3Q|Ow-PV0ST?~59qWoo#3SJOW>c7?lPkE%>3hHNj|v4^@s
zyf!qob+8hB`@}KL0ZfpC#Q+j8KoOf)h$KVc7{)5-VkkKOaGp3G$5u$Ja>P=i;&m1}
z-f(CY^@(szi+O4^ddQ?HR%e>K4B2|6X)yxa)BC(5%hslbkS~Qf#r2g|KlYW~PfU1r
zFQxY+)3g?=SB2>BU5e@BuInXMGkpG|tUVwUYp*3=R<_g$QS)QDDWz_ulFjs&K{rnW
zGEwd7nVH$1IJ+zY?!w;wZKr_;CN$~n%AS}u+zwHxa4eW3AV)1qEN?gzz0b**>?1S*
zdUsARP-0B)&h8b9;Vh*GpsJ&79PdY756%RFF!w>!b6-l=UmeJ)A|X$(q`Hviu8Vp?
z?5jal!*lpQuJ~~c@)4dG(e&^Xz-yNEOy*=#M-DJ*!*g^u`(*gdaqU)(#PUj|RYV{e
zELr`8_qP~&;?iRQkcGWtfVr`$MNzpq0xPzVnb8~ztn-+z$tG4&>2O0sx0Cc*=yt`*
z^y5{;kqMFItVCfu#z~Kh3c{H_JGipfkuZ3PB)NWfW!oaNQ=Va@VCD20MvaC@zxc4S
zoc8$?T9$liJs#QL*IZE!YRRRdGW)s(9}TTf%;-KtzQohx8sS*hyr6^ioy!ej7_4d8
zv$QMH=2=$sD|NI5Y*Fq$uzT?Q&hh_3_7@p9<zX5T9}OQGo*)x{cpuqrlhapBSKTQK
z;~5eapZ@>S_?4p&^0CCt>=?@8B`*nRZ&8HiGaY0U+NB(!8_MizF!%s#YcCcFVV8|J
zs>-jlSxCkEIPjaKvPKW&_-G8UX0_6vy|S7?J8c72bhAsV(8S#`?XPiadd0*FP0U_}
z5stE7G@=eyAAHP)gw#d{nh>4<*ZbKJHv%x|@d}Oc!{<$<z+(fq*~x&>R{?DO2<L9Z
zry>(*88L&Gys4Jf!zAxTWH*;zF8NFe8Y)-RGm34tMe>WE6*a;3Yrdb4HRS+wpm6;J
z6F>X}&qcF_bbLHdi-`F~pi;#13f>e$bHi{;%T2#B2!BniZcnm4f7g4zmm#o6i&7zC
zozLdaW5w0{csH4Pml`I<B|Q(kvF`LKnh`~nVKu;vf!uxdPWIkEm)9S~B|2mdrN8WW
z@gCR>-k;))iB*-#{u7$9p%teigj~sX%?<IJ4ZJ<R?&U>U+B*&gJL~WMQf4EB3IMpR
z`W`Pz_>MPbs4Cu=BRf>&<36gNW1}Ur_%R?yW%?pYHN=Vo2NYxuD=t?m7`hwSC$D5y
zGf^B=G5D;p21S_2#<e;?Pg%T=(2VB)*2;66y?Tg?_=Pdjgt{qUqjz*}#|N}fB5QAf
z)&8cRy{2We<^Z>6gvpcBz`=i8(DWAPPn5~RS!UG+J~kJB;8WD?|445a>)OyB*wrWW
zouT-q32H>;dN-Y!^{lm@h!LdQPjy?9p=rJk9bc2^Bwor2hGYgD*ierbTM5299c$j(
z4|Kq3)lY|J>=!8WAUuw}@!uB><=mv^7E{$FE)7rXZK0&KsnYZWd?9O$3h7Z$@V|0;
zDs7>|Z#YtBMduj__1y@Z!a$*7{ct4~;ssF*m=~hjbk0Mm+xUd7%yJzszUe0?n8$QK
zkVtNWg;nRkW<TOit(QbdBB5=LGp@a1tI^1pXB%7!);3?N2at8o{r&3SKbDgGVQj1j
zZRX#adj&3?EcOy@7lD%Gh=A;OI5IJZCc^oVe;Z$#cqi_+43T4imZ&DPoU{*i*WX5C
zECwIfICAa?Y`vvIM8T2gcxaf;*NmlrEv8MB-O~`RX)2{8)k4-DVTVB$-3jp12?!Sa
zCSv+??makiF=EP%3?@4%C?G3;9IWh*`Z_D65B@9tUMzy9Yl4P#iCa3dZjr__O<@Ib
z688!_sUgCnX62phAYZNkE_~=$mVa)Xuttqj&p|mJSmDJ5#AgdM7<sv5D0M<{v$*(G
zFv4D~CE#h=a*VR+-W{jC)r(}(j}?S1rBjG)<NY-o7?2m+O88Yv(;FlKIu+2!k+6rT
z#G(!&hS!umT4ra3_~Fs%RnNZ)PCI#TwWzKi4diyW?!$1m0d_v1=Oq$-Xq#@w6CnQE
z)`bWKTdu@hqSEqZP(k6ClaN=(7nz-x7(bPF8)~cKYSugZ;gVVpzhM~)<u%RR7^S(x
zW_Lu5F8E<9W@5|(aQI(0@^>EGk%Bxo(J*Fb_}U)<Em6_=5sB>C*C1S||3gL-SmUKm
z4ZsA_(a;v#9bmscj&az{MYDj-I)YA(MWui<dP5JzF<F=B7=NLsVb7s@L8_qnJQ*&$
zaLZWSu8%%z&F0gw=~n@K#w)gE>~51_;dq{fTlg<t?i17@NOA&FwhXRfj^l2LBm15t
zYEq|QeP3Lkm7n_(W^ZC=cR!j2!XNcwBq;7^emZnU?+e)XpT%H;aK$pF3tJ_+uJq0c
z9RxW_&VMT#Dd^p^&0-}@2+d@zOYO>{9BdIS10(g3E>?CUWJmSTJPoG2Ze;Z1){{W(
zbBt_P9%1bno@`skO_($RS$22_X7j|19q5%QD0TkxsxJQ+0=2^BzR3>7upKNJrLoGd
z8q${p0ecIP`O)!c0zFY}BikbgdBSHnDRBdS0kV06A6*rxB9L`&6f2|=@514@Mqd2F
zS$mbrbzdczv4X1b=#;xE+#{Su6l*W#ES2kI{*+P7c-V>7wRA5*nxl^v==RReeDrjN
zz?gE*g45%IWC0e6meMcD5q6>ee5z^o$!3cgXW8fEnOY=Q#{Rbh;C;@-L8*c3yq2oE
zVIicupQc0+0scD%{1Ku&F#+7E+di9gz;>_;q|VnNLjI1q-9}`<^Bxy$uO#JT!H+rL
zgFLzOYKId>reNrY41jQ=#;&P0hQol^jkFDF`a2RtfBh}taxp;GI+B`S;E2GHjD$Gv
zx*#wM1rbtvO$uHo6#6yxQsI$kIy-%D)>)t?ZEAr+lx@Cb-=)-K8S(7__??z$#m-Bo
zi3X=mi&}epm_=DFG;!7341li>1kLJ~#O&qx{mb+b%P(R$vQkYx&DXHP{7=Xw>)|ic
zbpm|e%=^jvMBSR|17}!4bE*S2q7^&9M(&;IazC~KkO5v?+bA0f3#V~opxMiQIqqjb
zzZInk7PjturK;wTKZ6cTC$hG^tA0upSJl%(7F|Q;azg0Bpb3mqyeW>4`MVpD+5g<p
zaG}eW%~KSy-VE`!FI=noBRyb2bz@Du)ISii40!m$4>uTP_kdm|t@$1TO*g4MO>$~#
zrK7Gz$`XkJ+KW7Zx9XdQN>g#NgaQ)W-m0n>45I-qVZU#o|6Br3I<dCU?8hg2(6Vn0
z{$AfK%<;SC-9m#xI(lscaC%_bt%idEg1-aqD>3vgI5RA9JVfc>;vrzA!XDWKk($>R
zY~XYyogL0Q4iTFDOIO{k!4-_?p6gag0Je<<R4e$^q4GNvBt)lGad_KGi7_&mh5IB1
zHIFZw{0I6quT0cTv>3I0E6kStv~2?Zhs&0?z`e2?iQq$f6ec7@%SGG<EV;45*(mMg
z^GclHj=%eO0fHSU=<_{UF3JEU%gO22eZ(R&m&k_>z&5{OrvAkfyVx+->BoeHhiH<|
zBxj01;Cpe36TgLV(+)h-e4twqF4FgVTvK*l-dU}~ejnx3q^WpN$s8<Z!aP1ODNifY
zGPAHuy=88l{zP&gleboa2vm@xM?eRmY#1{|Ixfk6MZH&&$<Kb=8$?zRn|jyC!>sjp
zi^VIvMQ>^H-wuYlGAXFOR^~nm^554GymZ!ukYxg_l+ORo29|5sS~~{>&_5psW30x`
z0jq#v5b1fH?MW-Mby27cpdWOiKoO-jdJXl+rfe?$@KP<L87ix|Mun)-mr7!sP#a})
zd2Dh!X?Oa%*Bwbvk$~kBZk+esBFYZZ8_&Z3LM*Q8v?bv))fo6z)-YzLZ)p7itg46|
zbQXqEfm6h$ZVGnrTTn>#iZhvr`ZQ6uu8K=YrBc$F)a7t>)JAZOIec#U#O_HplTnF4
zt9seQ;WfEF$TUjM5oE)zxicL=P4)zgu&NNh+aJR$*O;gX4hk%H1rPr3Bx>ixdQzkx
zFcEm%Lw`)d?#EzYYTWEI&^LG>vGnT$SZ}@^)8mJH&s5{^EDeJ<D+7sIvq%yGZpj1Q
zrJ(T?nym5y_`J1^*ok3r#4U~lFi_4bjd4~3d^xZXR_92kYlE`Ngy8j(r2lA41$b5^
zv;W%q0_AyMD&kUW%-sQLeo;9e)!s#78XN>bVYC9k?Yw#$`FkQ=$>MaK$)_0ki7EjT
z9g(FGh%H&47~=i0VpCp_1_%5+gkQpGr0Z>0MP7(S?(=BXb%PObO+|KiIJEDOUfz;q
zB#WF9X+l9Z!-L&DulF1TvDn$Me#%JB0IYF|=O0qo<&s&iqqtBb{_PkM0o?&RAvhAY
zI<He%lb15_=<3^7OF%XAQrB`@xS6p)QT|o-vq4;t|21uKt+zvQz9Y(9M*{Xk*U35-
zWDd!BFUe{xpJ~wQ;=zWTR`Sm9e9m~L(JlG->rA$o+M7IQi6mKmkd>Kk9Oyr9iMnL0
zt?D#as9L3u>;yQ}FiereY^d81asE3!P(MKl1K6ba5}TuDW%QaY%(|a!r=g1mpn!Zu
zFX*6s+ckGyhOdVH-=kJNTG8~{S};B^FJp^#C@1AlEkOi1$&cw*0zLgov0-7y0j^{V
zw@A<G`h3YFp}XI&HP^M<1?7lfpJ1V`6}YcZ31t>9UZ%#(TE6x(2`|&rS}RRRv~x$g
z?{75<UY2cHRLuugQc`Lfvi>k<!WOHq;?(jzN09wM5LdNTdU;P2K-(27&V1q=zlGR(
zY<FqDt2{9wCLhf>ed!mhsdh*A*EqXLijzAV{opQjMM%HaaEu#<WxsT<{g!48_JunO
zN+;L@z<f+CBic1}QUS#aTbJo3U(DhM97-e)wK%4_mf|YV;{0vR@P|)EkZ$zJcFeL&
z26UAWpi;?Um}hM|w^!mku>M0+{Hy~-F`?-_eY{p&V4SmyE4bRlL$Y2SQoJVpih8co
zcw_iO%z`~Aa(twbp<Vsg>KUdx#9G*Jq`PlCZ#qQ|KyP9#Iim3oZN9}E)~Fbm4t)a#
zlwt@79)A^<y)9Rn4o4m<39nM{8~7ijR=dxv_XwkhGVRqw^jVSyxL~PvJ@^P@Q-|(6
ziPRb>W-5Gr4H)?}F>>S?41PUW8MFcT^dMIi3pNf-Xc_%ju9<lcvH!CP%MVrtW^Hi1
ztL8+(qOA*Ze({#{bU#6+lwpmc|8)mA*@D5m#dDytw7U)zO5C=WjPRjE96-Zy+TXF=
zWy7^)ygh~Z>uJ*?CsSJ#U0$q*qx!Pq<#MY{Y)<hIwS4VT0piMcsV0t#$5T$xj0kg4
z8u!tLP*y=rS~7X}B|7mdQQJ?dK+T1`)G4uKe%h<Z4xxXvhOyv$e(heZaDfCBm_Fru
z(+JN-AmxSswuSkRJJQ2N%`xu64(6~h$Q@XnHr0oepSNoT#J7|z<ua*N+8O@m)DRA|
z-_;Bz?gX1T^5h%%e819SRaY82rbbk%tm@h?Zr;sG$&L>C9uD5MyK#u^K?hX7z^C_w
zzkhHyV!|ON<i*P=O$3be!<$gO@P>iq5HL$QBr;1J7T3Y+ra6j6|H;CbUU@GODhZR?
z_md=dXX-$4^`E_$doD@G9ViRRR5Dd?a!<o2<xsLGA2tV6bgBZv0SQrQ;Rej3DTY(<
zW#cW?$Ul6GXI0S;h%Pq6K3}!9nSJV&co1N;f+iG-wlZRhviL>>;(A%+Cj9lg!;ant
z$oWS@Xlvz6H2ko<fCW=Dy$Ey@1O+3ylOT5|vEftJ1XlNLw~I8lB~Zl1v6+4Q@`;Y6
zsukGs{ib4|%Fo^t9go~YIVS9ogdv+CODyeN$Oc~ccl|*<|87l~+&OKPyZH@6mjUB=
zc%OJPX~Y=}HLYKIR$qpTpVOYDcwL&WB%tH~-Ji?Qcag_9tz>g8<5qaC?-Qk{pwKbx
zbafoFU5*IMA4{S7lTU3<(9UqE;GGtske#@(d@`bxTZIhq;XhZOOKO7Q1t?o>7lTiP
zSb61MY(()woBLq(|5gEp9arAyaOHt7GCgkb)CgFG$LTmvX0?eBK((*oft~FnL`eH$
zUn_8^4?hzk@Z5sYOOZ0*ajDvDdqjYXDWSYO#xaiAtKuE$oCtTM%};p5FwU6B*81V#
z*GbN5ds{-rX+%1qc8p1fk9y`+i1FaMVGPFZc)E*R8X7E4PYv`(@cEGRpfZ=J@uXf&
zOl@kZrAdvi(~~utS3XZr+VKk?VJ}r{Baalanrt?xg3A~D!;gPJ!#tAlsq@8GG2^XP
zZpKg+pX`umIV;l<A>a81R!puN;GZId8qrSE2}zb2!&B=v1!5=9hnpJ3h7~tY?a6jQ
zFLT#9LUNBnEb4|_zh0zml;jfA?r#7Tx-l2bK{JblcLRo?tbWl_$J_KT>0A{>eRCAa
zXJ@^5qM;<%MCzTfW!--|U7I-Vqe6wJKkFyU)VXY+M?~nO7uu~J$|Czd%d$<v%-m2I
z&Q{=JA2eE}>;&D^;-s(D+J`#RgA7u95%OlcWI+CDrw`HrpgO@Ov{&EN>0Rf`ZYWo8
zK{>RZz<}gPW?E%hF7c$)3)sa+dRwYgHZ)3_W#_pt8O6LDX%*Fz2b74GWJsc{?AqJB
z92w*?kZ{x{LKR)Txg2L2l`3kN(x|m@1q{pq`W+}-EzvH4>O7FJe1M!|-_sG!o$k)6
zK29Xjyt%>&bjrCjJGEpN!yQL}6|&IEiLOa`lyTwK3`lq1tAJY+Rs1SEdzI16soegp
zfkOcprWJAaEVW=SU_0ofqQB@Tt}e}^-&W?ihT1G<O|^%eC0CysQvoF<C@Pmby^%}O
zK00T^)~s);s|HUUH)dRm>z!JaBP<&&mgC^=@?hf0mqQvPmE6dita8K^j&0M57|9;H
zF2^*^*eZqMl3Z9G6(>k+FW!it2lK{IXZcx$=x$47<bm!M3N`YoBAh4b6K0u-I-}tO
zN43d!P9bkHNmey#Wm;kA1J=NckC?nr4@Gd0pw>gTSeG@({8Na51#AV>5_HK(V=*0}
zAaW8uXM>J?y^$>F)#L{UG`d7kJ^Cl<DTH8XIXDvtc?QUjc0yNwc2O&YrmhBwAQvoQ
zDWus_RzaxLbyIql>sS`fgNT3d#f?B+tVtt4S8QqX)jR%TKUI?9W=r2n?7AukJ16X*
zk_$!_wY*?P3x21MT;F39Hmm)!qdgvOgs9g$haGf46<>!}K*xVi*hoS=0HEogBNUOq
z)a67_X{Ra1Nb(}M?WU($E>O)F&hNe74?qf9|3PbVcFGh<pisMU*Nz=kNU(qcw`TRm
zy0I3E4EqD5moiRL1K03h@<7-lrAG`fB6au^;1DaaPlM;!jC^f_=M!hS>P3iXjI}O=
z3Iu5<a9f$Et5NQGP}A4N88s?I-=l;R>K*8>yW^jIlRr9o$f-D5x(<<-Sc+?0Bi}rq
zIV1iv&F}!nj<N5(j-pNiGeQB{YZp2^&MnUBT~~7gA1?DdH^{S!&udnN;P}4ls-wER
z15|1e-Bq9F$@~0y_!wELS-}|Ni*DmLmkGQ4e(K0102qN*GDdPuXN>PX|K{d}5i}JN
z01-#)9U+N;*X9Jy&{cC2-*4zMOz{1BLDG$W_g78JB?*n4ZchQrl97&Z>deXIC=!*@
zLP3h^4<Yg1G)6s}hMSgnZyUr=Wn6u^os)pypAXFMiCmQ6=j>2Gce2mQK&s&iaHo!%
zih37A{pIc%u)mCKMz}&w0k<S(lmx(L0{;Vd|FtgqG&Y;Ou5FYtDSjCzhJashv;fp~
zd}l7=11KF?@}FwX_M?6IKuLq|NR@ISlgiV$vp3m+a9!jT*iJxWP8}MO4{cb8FaKz+
z?9tNMaBY(N%6EGqGZB-9b*U+Irl&$?^uSd;LJJdjBm0;-h>$(ic8W<E`L-}(Ctz<P
zKW$C^!LMJ9LMiLg<8l&r&r{|8|8u6Xu$<upQ?iw0CY{3aF_<o~x}w%e)Y9uj367-v
zq3?z~*H{Uk-he3mti}Pa_*UFf5X@E%cu&AL`QO*V4%G4E`wi4DYltisVKO`ohR$G6
zL4y<x;V>;)kLT-oD2c@G$PY?)VMKD9*oo(H@CHI@oTby<Q5L$zTj&rryrbJn???j;
zRgW<~&kEt9*EUKNRoh-W_<w2aJTOj&>dPg=k8q<&e|>_EaKTl+x3qHDs<EZiJ@yTO
z>9NxI;?4(DJNWdjhc~{a|9p|U<4Ewj=NpkmgSP$nv}0XeER=@{+99|Xij4f<!7x@}
zl?sM>55lmS>Gw%+XDXXVti^&$I1SzZl_xt=5$%B2i7mZ--(m@`^qQKTbD;`I`<zVk
z9z@M~!Ua646x$~lrcY(KzcM0Es~Yo2+*zbJOe*D^Z3f+$_m2-GexAei1Q0!W%@?6?
zHKTn!UUVWc^A@MJ(Y(<>izXY5ZhiJ7P=ER2FSV&xwdzmlr`?`X1aea&@0+jX@Kn>1
zACgvPO~!7!6}X~)ESPw?0x45nIz_RMgaeUTf1QM&25!Glhwg4H`zC{k<g=w9Q^=~Y
zk)Bu+pwftaow~0C|GLTiT?j!|G>8M)mdk4nsrn&KIp44c4#L{b<sCF&nhO9RUtcrL
zfguH>&Ux=@*hX~;i0f%K!ZMk)9U!BIViOfGPSvI|uVw2p@FbP-fH;dLl7L{;9D>8L
zIs!YV>eNUbh9U_pLLfogsuw%k%qLiMP8xDLTA3uVII_%`V}?z}=W{2r<XOF@TN`dB
zBi_@BtUA4GEW^fv{F&$Uo?5aqX*-{kGx;!zYI?dJ3Z}$otdKY?FeM)Dyh=mGh?_f!
zfNBBpl=E0w>rss7nL>*EDKWB-e?!i<75sttI)Qy}h`L?_-;tP!U6LiUC3d0Rs2Lj<
zngGZ2)hZXs3Ol;n37Npg)}0|BFu{OK6fmdZr(SV?5|h;!@E@)KPZT{cbc_I+JP4QP
zR7brX?6af6E#6RyafqG#L^4+VX|ERBfCX_LI$;#d6>F&NO^s7TG#PnU>;aB)=*w%h
zh0&h6UI;`^R){*{qINsAiZ#%oc@@)ney67VjeHu1vYq#C0_5Boxs?n5aT#&B+)!#R
z{zYwMQ&JOAZ{I0%cs45F`l3^j2W0#zw<es46G9&`@h3NE@LILZoP%K)&&WJ@Lz<0z
zl%_biDNz#P9Infv%eSm=QYNYYZ;sCjXH2!Vugz}*H2wGaFBRXg+&sYQum;!4>XGcR
zTj8#j<<gUD-<7kVtT_8-ETuQos?XP%pE-rYr^LWsUDlrFf)QBUl0xQknHeT+2M98_
zv*xC`gepQZ`y!KQf4vvsG-w>64`8`A+V^NCxEjH`B!6DNq1UUeGq&ciF{>qf=hrWy
zUKO99$a)XaW!6~jlUoFnBOan<XFK&QKPmxFd6o?8?{MkA^!pqY57oiq_#0*>G&Irh
zotn(z7h<Wi;*xMB5HjgeP@wsKyJxU4rV;l*Q-Mvv*}n*}^!GVZnUS!S<}nB4qX%y%
z^!WyNGSr>6MiBo16M4fnxBz$)#g2htwI$>_&|Pg#w=jSn0KM}|%D536Q~cJkd9fU=
zyvR&{(Q-Y!QPN;Sq{@+;6<)%{4agx24$RPAw4;e1<?fZPaeOoFz4j6pP-N0%RI#d5
znT*Ha)8qa$XW9i#vw?WK0{)CXcM_&AJNDGl0?VT2vsZF)ukA1fnRSJ(as@MitN8FR
XgSpU8B!b8<$uaxHC01x?Hu$nSkz5hg

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v
new file mode 100644
index 0000000..8b7305c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in1.v
@@ -0,0 +1,119 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in 
+
+// ============================================================
+// File Name: rgmii_in1.v
+// Megafunction Name(s):
+// 			altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in1 (
+	aclr,
+	datain,
+	inclock,
+	dataout_h,
+	dataout_l);
+
+	input	  aclr;
+	input	  datain;
+	input	  inclock;
+	output	  dataout_h;
+	output	  dataout_l;
+
+	wire [0:0] sub_wire0;
+	wire [0:0] sub_wire2;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  dataout_h = sub_wire1;
+	wire [0:0] sub_wire3 = sub_wire2[0:0];
+	wire  dataout_l = sub_wire3;
+	wire  sub_wire4 = datain;
+	wire  sub_wire5 = sub_wire4;
+
+	altddio_in	altddio_in_component (
+				.datain (sub_wire5),
+				.inclock (inclock),
+				.aclr (aclr),
+				.dataout_h (sub_wire0),
+				.dataout_l (sub_wire2),
+				.aset (1'b0),
+				.inclocken (1'b1));
+	defparam
+		altddio_in_component.intended_device_family = "Stratix II",
+		altddio_in_component.invert_input_clocks = "OFF",
+		altddio_in_component.lpm_type = "altddio_in",
+		altddio_in_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
+// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
+// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
+// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
+// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v
new file mode 100644
index 0000000..c542a4a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_in4.v
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in 
+
+// ============================================================
+// File Name: rgmii_in4.v
+// Megafunction Name(s):
+// 			altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in4 (
+	aclr,
+	datain,
+	inclock,
+	dataout_h,
+	dataout_l);
+
+	input	  aclr;
+	input	[3:0]  datain;
+	input	  inclock;
+	output	[3:0]  dataout_h;
+	output	[3:0]  dataout_l;
+
+	wire [3:0] sub_wire0;
+	wire [3:0] sub_wire1;
+	wire [3:0] dataout_h = sub_wire0[3:0];
+	wire [3:0] dataout_l = sub_wire1[3:0];
+
+	altddio_in	altddio_in_component (
+				.datain (datain),
+				.inclock (inclock),
+				.aclr (aclr),
+				.dataout_h (sub_wire0),
+				.dataout_l (sub_wire1),
+				.aset (1'b0),
+				.inclocken (1'b1));
+	defparam
+		altddio_in_component.intended_device_family = "Stratix II",
+		altddio_in_component.invert_input_clocks = "OFF",
+		altddio_in_component.lpm_type = "altddio_in",
+		altddio_in_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
+// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
+// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
+// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
+// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_module.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_module.v
new file mode 100644
index 0000000..8ae1cf1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_module.v
@@ -0,0 +1,302 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_rgmii_module.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
+//
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// Check in by : $Author: psgswbuild $
+// Author      : Arul Paniandi
+//
+// Project     : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description : 
+//
+// Top level RGMII interface (receive and transmit) module.
+
+// 
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+// synthesis translate_off
+`timescale 1ns / 100ps
+// synthesis translate_on
+module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ (   // new ports to cater for mii with RGMII interface are added 
+                      // inputs
+                       rgmii_in,
+					   speed,
+					   //data
+                       gm_tx_d,
+					   m_tx_d,  
+					   
+					   //control
+                       gm_tx_en,
+					   m_tx_en,
+					   
+                       gm_tx_err,
+					   m_tx_err,
+					   
+                       reset_rx_clk,
+                       reset_tx_clk,
+                       rx_clk,
+                       rx_control,
+                       tx_clk,
+
+                      // outputs:
+                       rgmii_out,
+                       
+					   gm_rx_d,
+					   m_rx_d,
+					   
+                       gm_rx_dv,
+					   m_rx_en,
+					   
+					   
+                       gm_rx_err,
+                       m_rx_err,
+					   
+					   m_rx_col,
+					   m_rx_crs,
+					   tx_control
+                    );
+					
+  parameter SYNCHRONIZER_DEPTH 	= 3;	  	    //  Number of synchronizer
+	
+  output  [  3: 0] rgmii_out;
+  output  [  7: 0] gm_rx_d;
+  output  [  3: 0] m_rx_d;
+  output           gm_rx_dv;
+  output           m_rx_en;
+  output           gm_rx_err;
+  output           m_rx_err;
+  output           m_rx_col;
+  output           m_rx_crs;
+  output           tx_control;
+  
+  input   [  3: 0] rgmii_in;
+  input            speed;
+  input   [  7: 0] gm_tx_d;
+  input   [  3: 0] m_tx_d; 
+  input            gm_tx_en;
+  input            m_tx_en;
+  input            gm_tx_err;
+  input            m_tx_err;
+  input            reset_rx_clk;
+  input            reset_tx_clk;
+  input            rx_clk;
+  input            rx_control;
+  input            tx_clk;
+
+  wire    [  3: 0] rgmii_out;
+  wire    [  7: 0] gm_rx_d;
+  wire             gm_rx_dv;
+  wire             m_rx_en;
+  wire             gm_rx_err;
+  wire             m_rx_err;
+  wire 			   m_rx_col;
+  reg              m_rx_col_reg;
+  reg              m_rx_crs;
+  
+  reg              rx_dv;
+  reg              rx_err;
+  wire             tx_control;
+  //wire             tx_err;
+  reg     [  7: 0] rgmii_out_4_wire;
+  reg              rgmii_out_1_wire_inp1;
+  reg              rgmii_out_1_wire_inp2;
+  
+  wire    [  7:0 ] rgmii_in_4_wire;
+  reg     [  7:0 ] rgmii_in_4_reg;
+  reg     [  7:0 ] rgmii_in_4_temp_reg;
+  wire    [  1:0 ] rgmii_in_1_wire;
+  reg     [  1:0 ] rgmii_in_1_temp_reg;
+
+  wire    speed_reg;
+  
+  reg m_tx_en_reg1;
+  reg m_tx_en_reg2;
+  reg m_tx_en_reg3;
+  reg m_tx_en_reg4;
+  
+  assign gm_rx_d = rgmii_in_4_reg;
+  assign m_rx_d  = rgmii_in_4_reg[3:0];  // mii is only 4 bits, data are duplicated so we only take one nibble
+    
+  altera_tse_rgmii_in4 the_rgmii_in4
+    (
+      .aclr (),         //INPUT
+      .datain (rgmii_in),           //INPUT     
+      .dataout_h (rgmii_in_4_wire[7 : 4]),  //OUTPUT
+      .dataout_l (rgmii_in_4_wire[3 : 0]),  //OUTPUT
+      .inclock (rx_clk)             //OUTPUT
+    );
+
+
+  altera_tse_rgmii_in1 the_rgmii_in1
+    (
+      .aclr (),            //INPUT
+      .datain (rx_control),            //INPUT
+      .dataout_h (rgmii_in_1_wire[1]), //INPUT    rx_err
+      .dataout_l (rgmii_in_1_wire[0]), //OUTPUT   rx_dv
+      .inclock (rx_clk)                //OUTPUT
+    );
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+    begin
+        if (reset_rx_clk == 1'b1) begin
+            rgmii_in_4_temp_reg <= {8{1'b0}};
+            rgmii_in_1_temp_reg <= {2{1'b0}};
+        end
+        else begin
+            rgmii_in_4_temp_reg <= rgmii_in_4_wire;
+            rgmii_in_1_temp_reg <= rgmii_in_1_wire;
+        end
+    end
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+    begin
+        if (reset_rx_clk == 1'b1) begin
+            rgmii_in_4_reg <= {8{1'b0}};
+            rx_err <= 1'b0;
+            rx_dv <= 1'b0;
+        end
+        else begin
+            rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
+            rx_err <= rgmii_in_1_wire[0];
+            rx_dv <= rgmii_in_1_temp_reg[1];            
+        end
+    end
+	
+	
+always @(rx_dv or rx_err or rgmii_in_4_reg)
+  begin
+		m_rx_crs = 1'b0;
+		if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
+		begin
+			m_rx_crs = 1'b1;   // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
+		end
+  end
+
+always @(posedge tx_clk or posedge reset_tx_clk)
+begin
+	if(reset_tx_clk == 1'b1)
+	begin
+		m_tx_en_reg1 <= 1'b0;
+		m_tx_en_reg2 <= 1'b0;
+		m_tx_en_reg3 <= 1'b0;
+		m_tx_en_reg4 <= 1'b0;
+
+	end
+	else
+	begin
+		m_tx_en_reg1 <= m_tx_en;
+		m_tx_en_reg2 <= m_tx_en_reg1;
+		m_tx_en_reg3 <= m_tx_en_reg2;
+		m_tx_en_reg4 <= m_tx_en_reg3;
+	end
+
+end  
+
+
+
+always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
+begin
+	m_rx_col_reg = 1'b0;
+	if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
+	begin
+		m_rx_col_reg = 1'b1;
+	end
+end
+ 
+altera_eth_tse_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
+			.clk(tx_clk), // INPUT
+			.reset_n(~reset_tx_clk), //INPUT
+			.din(m_rx_col_reg), //INPUT
+			.dout(m_rx_col));// OUTPUT
+
+altera_eth_tse_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
+			.clk(tx_clk), // INPUT
+			.reset_n(~reset_tx_clk), //INPUT
+			.din(speed), //INPUT
+			.dout(speed_reg));// OUTPUT
+
+
+  assign gm_rx_err = rx_err ^ rx_dv;
+  assign gm_rx_dv = rx_dv;
+  
+  assign m_rx_err = rx_err ^ rx_dv;
+  assign m_rx_en = rx_dv;
+  
+    // mux for Out 4
+  always @(*)
+  begin
+    case (speed_reg)
+      1'b1:  rgmii_out_4_wire = gm_tx_d;
+      1'b0:  rgmii_out_4_wire = {m_tx_d,m_tx_d};
+    endcase
+  end
+  
+   // mux for Out 1
+  always @(*)
+  begin
+    case (speed_reg)
+      1'b1: 
+		begin
+			rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
+			rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
+		end	
+      1'b0:  
+		begin
+			rgmii_out_1_wire_inp1 = m_tx_en;
+			rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
+		end
+    endcase
+  end
+  
+  
+  altera_tse_rgmii_out4 the_rgmii_out4
+    (
+      .aclr (reset_tx_clk),         //INPUT
+      .datain_h (rgmii_out_4_wire[3 : 0]),   //INPUT
+      .datain_l (rgmii_out_4_wire[7 : 4]),   //INPUT
+      .dataout (rgmii_out),         //INPUT
+      .outclock (tx_clk)            //OUTPUT
+    );
+
+
+  //assign tx_err = gm_tx_en ^ gm_tx_err;
+
+  altera_tse_rgmii_out1 the_rgmii_out1
+    (
+      .aclr (reset_tx_clk),         //INPUT
+      .datain_h (rgmii_out_1_wire_inp1),         //INPUT
+      .datain_l (rgmii_out_1_wire_inp2),           //INPUT     
+      .dataout (tx_control),        //INPUT
+      .outclock (tx_clk)            //OUTPUT
+    );
+
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v
new file mode 100644
index 0000000..f521fe6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out1.v
@@ -0,0 +1,123 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out 
+
+// ============================================================
+// File Name: rgmii_out1.v
+// Megafunction Name(s):
+// 			altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out1 (
+	aclr,
+	datain_h,
+	datain_l,
+	outclock,
+	dataout);
+
+	input	  aclr;
+	input	  datain_h;
+	input	  datain_l;
+	input	  outclock;
+	output	  dataout;
+
+	wire [0:0] sub_wire0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  dataout = sub_wire1;
+	wire  sub_wire2 = datain_h;
+	wire  sub_wire3 = sub_wire2;
+	wire  sub_wire4 = datain_l;
+	wire  sub_wire5 = sub_wire4;
+
+	altddio_out	altddio_out_component (
+				.outclock (outclock),
+				.datain_h (sub_wire3),
+				.aclr (aclr),
+				.datain_l (sub_wire5),
+				.dataout (sub_wire0),
+				.aset (1'b0),
+				.oe (1'b1),
+				.outclocken (1'b1));
+	defparam
+		altddio_out_component.extend_oe_disable = "UNUSED",
+		altddio_out_component.intended_device_family = "Stratix II",
+		altddio_out_component.lpm_type = "altddio_out",
+		altddio_out_component.oe_reg = "UNUSED",
+		altddio_out_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_bb.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v
new file mode 100644
index 0000000..2f8912b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rgmii_out4.v
@@ -0,0 +1,118 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out 
+
+// ============================================================
+// File Name: rgmii_out4.v
+// Megafunction Name(s):
+// 			altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out4 (
+	aclr,
+	datain_h,
+	datain_l,
+	outclock,
+	dataout);
+
+	input	  aclr;
+	input	[3:0]  datain_h;
+	input	[3:0]  datain_l;
+	input	  outclock;
+	output	[3:0]  dataout;
+
+	wire [3:0] sub_wire0;
+	wire [3:0] dataout = sub_wire0[3:0];
+
+	altddio_out	altddio_out_component (
+				.outclock (outclock),
+				.datain_h (datain_h),
+				.aclr (aclr),
+				.datain_l (datain_l),
+				.dataout (sub_wire0),
+				.aset (1'b0),
+				.oe (1'b1),
+				.outclocken (1'b1));
+	defparam
+		altddio_out_component.extend_oe_disable = "UNUSED",
+		altddio_out_component.intended_device_family = "Stratix II",
+		altddio_out_component.lpm_type = "altddio_out",
+		altddio_out_component.oe_reg = "UNUSED",
+		altddio_out_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
+// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
+// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..d59921b80e52c75934a20f0176e522fbbc3b2aae
GIT binary patch
literal 31016
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl?CD$Nq@
z6Luk-ZbE4E>UM4N;O%8qXb*XwJ84mcW?dJ7mJrINFo8tp;B)q<ac5c4jlk$_`&+v{
zPAV2<8nj#rKGCkNjt!Gj>t?J_kFEbV^i_{cuX%5#12j>b1f;VVm<w_74S<8e&j6(H
zWTjzeo%q!b|IEZ^Lacn`MbN%@pIk@2)FFf6=Br=<B!Ky1WpCKbE&cqyt(CrRF(GHL
z)32PZk{V@Ifv;%sipcXVD5iDyZ%x}wD^>hJko@F)z}4GLB-SYQ>On9@RrA>!Rw+s<
zdlCy7H#A8e{00>gtbAj&;|d_p@FC>Ed5y~Votd0H)&~E5a^24ANWqBfnv29bdicVQ
zd{(v=O!CF7fRO5{|6iB|vz~?+g0L0c3VH(oNEpl29Mi>xPt5X3AiL3d;Y0*PC7{2z
z>1Ag&PCnFKERRVT@l&gcxzMn5L{&%OX9Kh)Ji<yLkr$vz40vesT9oyS?Lv4V))zfA
z0d1(IpAJaz<L_Z-_H@M<PV@sA2;2{on_pl4DfQqdXG&FUI&|pZ=ym?3Tl)*7vPeyg
zBptQUov_hDX<NwOU<2EMrnrMM&k9nRVrF&F1d6{G_BmgPfiM#?fVFsvL9o4j0=1YD
z)q=>*45|uf0|h>mvrg<(ffctOs!u!LeQ6U@zk&RsF;@Z4ezw=dCZQ_N#;Y^)pDCtA
zm)%*t6PEGLB)R=)tyMLPJ_VIss6-sEhbPWhSfyb~JEyrbp41hj99Y|A_bD*pa_UJ1
zPE>Asq}Aj+@(RARd2?5ig1+2aG+m$Yz?*upR$=SmGDQ{8V)wIMZW&(*9xsMps$FG(
zqY=$Quz}3XuJWM1bUt@c@$1Y4P>6_q(AH40!0jfF=`61im2Ro3Gr^qvr|)5<taKc{
zt~4G??PY)Ico~|$bv)f(rFOLI-kzh7fa57srETYFJD)oR197?|FBB=b|K!t(!ngb8
zeuvkc!9Rgra8T$o4gq%CfbNZ<Hg1PL&%HXJ3nn!nJo@6hz%yS4H2{IJVGBc@Kq*tr
zZfFrx-R!H?OBSdy-lfDgTSPo^w-QzkH|UDUid-CRW9F^{D_F-x*veu(2{bS%QW^3v
zS6h+m+ip^c(`QxPt4+S_Cf!MyTA<L$Rtz4p0J76~_RY=h!boEC-6E<35>12vyOCwL
zAgf(%vHLcexWD6x_nkh=XRdBSe3;s2fluQnOqqxn%!)F2-mAYr9NKgQ0ycH@?f3;Y
z7rDTtQP2g1=G&kRZtl#1UGacEs1;ug6MK#OhpRKO;tsyQ1j?uegymaw^FT!id5<XK
zIDZ@+IEj4-eh_XBqFEb`FaB;=tk9ITXLLn%vIq+_P-4F#8`51WHV6Hz%qJkc%V3X-
zsO52b^J=odKd%mw04!t=IoImO$Cl4W0oYAvwgeI&)qLavrSUEb<7t$a;Ow>@=^L_f
z0&9rO#_wEGAFVtuK5z}%tC7fZe8Ow%yUx~PVgW)pX8X@8pY0MvybZADiAM)qw~(pi
z-Mu8tm!8+H(~ptnZ^DcVGPQCfbZsO$c~Kg;XvxqW>cF2nX~#-FcDcWPi(h=+M4L2<
zt9?AX95Rgpzho>xKMjIzTfV*((zA_k(s+0f^_Fl{d>Uh#@o4lpnx9MfN&9luDT*B)
zC>?ExAg4nUCq)Pbhg>1l!Cwey-&Ga4l2NV1*5r;oX1M<6)(|>>EB#`xGtgwfLcN+-
z)&>pDb_YEu-tu$6?Y&YGkt}TpM^6l$I1~Eoh6F3ST1d-*yWPRU&Ff^{N}nOa#MyQ?
z3c`6%_X=Aym;Z!7aJm*>CL{bKYWi{6ixjdy+glq6@CrtkC4@+ftOlm;C;P6Jg&@*m
zML-x`mV_V!Wjd70pL4-udy2p>jLh##UzDVS4$CV|+QBwHrrY<R5(o+$ZtXx*!gBk-
z($v=a)xhG5qD|1-HAgpj`3ShP9><kNEa^<vBK!j}OV-y_%D%MOl^oc*89xfIboO_q
zElZ|~btq_6`hn}pqyOagzg_@lrg8o$EPgt&EfcZ9>ByQs>MqK4AU{FbWdJ>%gEtxk
zac0t=Z&OJ^kDBl4wfI)VM-05kSv50u)nkiBh13HZt;;=Hs)fCr`DLzN6sGQn&wX6R
zS}i>*y{OIrcy}o^3Qtg_d}r+bUVJ529KYwPkhk4xyxl^zZKS<LH=9+m&l+XMAon(<
zaUxYrW5tUR?z?K82<2vCv8z@N{Cpm32A$A}XVEX-IOFs6h_B8KG{276Fs}HiFU}nr
zK*XP^S#byS3!-ijXTQ8?=&%NK0sa}&!8_qSe4x$5MJh~{64@UT84t#AzxvpB##!OJ
zpg^5@ma|@Q_24cdN$aII#38eiYE9jM$)z>iOr`1Icp1bm#oEQsoyFwlTg=leL=hOA
z_tT@G1j1TI4LXWPbgntpuLCJ|S}TlcLlQ*#ZP)@EGmI4-IZ~yQ42jjx)Tdc~yhEs!
zwH2Al>IHcnSubLA-5pyjGWes?yz#jAeKw%Nz78F&B!rZeddyjHst_hxz6ep>9T19I
zpG$#-?6l};h8-91-YBTgc22NUp|8kIMu5ob`ZMuzdy12`<~4IJ=P&QyIPNUyBw@D<
zY#`BdF|@!L=yW81YwgTuR_u|l=oXzv@aXrFfRM%@KqR^kH@CB*cYELK@d7h5m?S3o
z{&_LDJU`yq-wvIP&dy&{o>m(|Z<(lahlEH~4--mTQ-;F(tjd(>{zEn?8NuPahnTmA
zdLFo(VDS3cStF?2X7fOnFseP|iTCQ-vn-k*bJ!>GQ1^p(=5EkpF?oFA%}fp%#^#_r
zEkUC%Hy9c<u>}Z;Num#G;vzlmyD)k2BqLpMv!U9szOlC7iRQ~ZYYLdR^S6KY&#1)Z
zZR~xzS@2Rgn<UrK?Tbb1ZQ-Rur|x$+gAWf$XT1Pg2}V1^?AN8}C@o(FP2pEav6<}F
z$NC}9d9ddO)a0+>(I3Qzmv+t(CA6QH=qXykkd6P5LvZa(VP=L>?%M7J7=4=`OOY((
zI_-%8Ho{myz6_%EwR5H$8{fqD+Ql)aS2v6a<PU$mB;mAN@`v2ad09H{N7s-{h}VP?
zkISR@LcBs7_6sSJxfpC4yMUc2=D0i9PKud_$EjWw>CVshBAp%;dXt`fS3Aw|Y$H=N
zg|8L&zPf;LR@fX88FJin(T%tJR_qf@Uy6N3H<P6K8;E@078IMZ?NN5f@&aPmt94_6
zEG_}siK9Af;2i@|;^fzbnB9$#0m9TzYh5^^=K?JIqk+~7zc$D(DqU<)4_xx7*QvkO
z%C&{DWeR+>NPK6m?*Lab!GoX1%FPHI)?<CUv&@91`&wICmwUvGKp9W~r3O^REC0mi
zIZ!FUL(!Z+%Ud6X(P2GHvy#Jf@!*&1JxE8hc?u>xC+7<1M2rsp48|ZWP6cM%3>Mj#
z)5=S=Iu(ynTee6#Do2|z-#Py1!xYgy=V!sRcQS&d-Kc|3YfoBQwdo(@mv!tyxKkkP
z7wh_N^o>XA>1_*!7>eEmT+5TvezIu{>{BW1tuy~)NOODLZZ(MCVjZUfgV-P_$qC#2
z4QKwLc{EEclM<OB=e`8oJ^QxmyE`RGr>vEV)OxJ8C-M=Dyrd)X8bwcVN+z3aMcT+i
zCeW}<_Vh-9F)MCIq!RCM*c;CouhLodJHcrc-sXPlSaCCUkPt1YB$AY@-<Pj3L$aO8
zQe)Xz&w^6+#rSGTRiJG3CMaMg9|X4z#Ja)pLqVT?|1ezV^$%}1(`@`hV}pHDthKX_
zLSQi8XGY;?#{D$e`%ClGbU_o-BkVI?{r(Ip{Hl5`AsE<vLizs(H-Ccw<8{EV^uNzO
zGpg`bsxy}2#db6*+T)B#4{pTQ9(jU&51}BM`bEqZ+v3HPky@18)&%XyFOE`*WAF)-
z`Pap?HHI}VtLHvI0#bg1`wjJ|+quwgfv=4>`P4=ix9%QAW03*nmOoZ#fa)^B@(=CY
zU>eLcW9}$Ty$d(_=#uR{L`h9JBL>5nuJDc&yl){xl)}$bx<*_A;ui+=@1&3<t#f6D
z`&njKG31#8AKWG}5Qr5O9nlj4YU`l()q$28a}xXff+5@1JRJM&Pg3Rx;{%hU+#<J+
zPFmM>M6s0^GkkXFk7|YiQycS%2ICVw-!5V6rFhnud*Qj+#ArMG3)ZZb;`*HAl+U6y
z4DayyOh@Bah$Apv;N;<ali!JX@7;@$N0V$v`%h?e@JW0F0)57bu(d_$Qu<J(-K%ev
zethOwiSbFrE7^Q#B$&ANwL@=;zvrwEK#mNZuN&ef-0&cRV(D?|eJ#GZeAtgP0GxKC
z)F+&wQva-HO6SPcj-yHJByPCYsz7e-!vMgko_}xpv%1P8Ky{u2?=Ti>V<(*LibZk`
zfZ?SoKJrEsF|ZsJrGOL5tCzz&tG}LV0oAqR_CJI2I3Sy{Jdyz`Fv2zmUiJ;2=pR<*
zrLYtQOH^LY)(jb*zV~9mD!8%ya7rrB@4}uTY3pZYlTn2yJe`&PfJu}nd|3`!$D-vv
zu{D>a)77)!-N#Scj4}*}=-j0BMQ)C@re~qeg0AEKL);mJW!mj+X$%EL$g5Xq^KXYe
zW)1tV>ex0j`m*a>Kk=rN8Si?0Ji#Bud4BRI(#2_Yl>$_XWRVJJ-YYO&pQ(S7TbIlW
zX4^=C`<{IhKmiMJAcj=3EQOUVUGn31C4v4zmbRjQ!SS+@%=t9=uBTq(>@vf^nf+eo
zT7FhwXZTUDYR-nmJNKFdMAVanqh!P+Dp%7C(jWAUhpQ|a{y%UcSNGFWL+^KDN16`^
z>O+Jcz_Ie#78$D>o#c|FK-K{IDR1Uv=DGD^cS}9@g#XZ<q7z0pC=n%`D0jpU$TK+2
zuhU0&Xo!1R`Y#)4%F&i1?F1WM{D>1xY0l}j0=d)T&$7yo9T38D`+`=vLLkn1dr_{1
z!nsoaP=GH^RW<4dma@xX-4=q3v5j)!N?Gz>u!MS<iln2PO<fA4a$uGq_?|2<8yGe?
zw+L+iv{K>sAcF@x#0CL4nSgi9Yin_m%dF-0XnA$(liq1M_+)|yei`@YMG<PEHf(cG
zZ13=j*9M$`Z6KbMbQ81=##$Dd%9t%%=Mi|0gu#f~B%<_7HJmTwG&(%a_{hfid6)2O
z?u!CZpu`1GddF{Cdu;9>UcNVw-W^lx-rddeNqkZRg4zPsA*!!7vMRF=a{!O~t0xh7
z`9J4}?IQNLtXsKszJZR-h?r4$Oy&_(L1H3^S0?o1^v~`01qX6M-PD7}W8ZHcKZ9^L
zF_M<%no^ght(GD@g*<4!r%Vj-s6i71qZ_1=4r|Maxf7J!zYj)7mOOrI<3j2<LN^cu
zLG^LLz(ozUFK!_M4h8K70|yiYfl;b8qqXpSS}+JQ`|EMx2SjtiV{{G<(K2RevS%G)
zQhLJ3KvosX#xVv(5fW2{-bZ^%EDR{W4rkxHAX9l}*z&a^rPj{ARTST05qy{Zt9?6X
zO$3vJp$Q;gbw(np1eX`un37DJ_9^|lqLV7l-R1D+wHh~`d2zn99jXn@bOd`61S%Sc
zO2>wDkK*;$T8tw!w2nNy<yjRgLdG~<y#polW-%(ty};Cb!5-{7jYa;JmZY-a|8$sW
zk^m?hoCkKti?kkYqZx8wF~h|6TgI@a{_O69qc%@4nlf+&IXUS}FuAGVr_Gi1m$D}8
z+8(;F0)@hRhbT<~#)-2J;Uxy4;XEZU^Kr&qSzj+EbUxWGYxv*Le5<W@Bblg$0O<(M
zpIDM7PJ0L?{@%~J8tVugg^}XDDaW46cmK?zlZZfD-cGDNdWMTs{)+`eJ6m0!Kyw$(
zw-Cy#lyQt8+2Yo}x*9q!*dginJ+VK`jL2SyJj~N>hC}E8w<4HFRQKIe$x<T3EXZ>*
zgo{>?sT@-tho4yg6dcf6{`pn@z%4dXv;O>H4iONhRGIKioj{;&Fmk7Eg=+WXWU^r&
z>2}9AAhOAsvY3Xukv*7JM?mla)%R0P!X~9u9ZAMQT^~=?<jOr%OP@PvkM-;F)O2>s
z#ddyGT=gzH$!UFG0%sLCh5&jl?+VSfO0TML{);L@R!m}z>L(P+^@^#ldnSr;{hJ8p
zq`Z^CO_Bk!%0r))_Ut&R`f?!7%ST}QgF58rhtk$pq1x|oWtD8wVd*ONla>77*I8WC
z?(p>JU>sfw_gZ@dEasqs4)bEhOOW|UR9bFH7QU9l7z9a5EBaB4ae=RhQ*L#4N8}+H
zk42$o(k3^@yZ$r;bXzvfqpO1E5};GEeMW5G@3uJ2D`HtkP6zAjd_*5pIlzF&@un7c
z9dDpz{4Uc1c<r?CwNMhnUtt2O*naK$O>g=6_w_ZF-EGWV<QR3tt_El#EXSI~K{8c%
zHhFvc^7IZC0@*IuYxe8$*C=<Pf`o9cm&2`IY5Gh$F#IblagpKY)`MB}cmY*G^syG@
z*M7?w@t<*BLA1Wf(zxZU8aQA=Q+>9(q3Ovi?BA&v{^x9)SiS7$GF-8|oa>1RfH>*G
zy{!u6-aZ({-eMu{O2BTzUihe}3M1V(eKHrt+<2Zoz(-;;8&n^<Rc0Y`_n3I)0z~Ll
zWA`3y3*PZ_CC8NP3?gyoaoARn>!7Mtp!!GRGk@j|k}wg-F*LK-rZ$-Q9zrKZ-3rL@
zQ1<#O3K&~fn0~CDKHBl^FbH8LU9s#}s<-@sl$>8uZCkn-ju~(c;gVOG!fKUdX^wIE
z_)7Wp$E!ME7z>hAo#lvp+^}{;TW%@}F=i)}hImRM#CvboP#YY|D=4%e-}XdU7EC0d
z?NI0ynq-J|V+)a4yxj7jN+Z7BbFpW(#zjbSKcOAD)e{o1tNScKE$}WyMb<LjU?N^K
z3p-V?{#j)ojnBKdOs0PG9(Q}%8c{C*rqmkGCO5gzwJ=+1IERI(aI<bBEmYzh)YnMy
zwOb}b45L&JSv!d%*n=)B1PM!SIf*5Zcv_vIp2)wils$<aHqtouKK-Fj%wx;DFUlW@
z2A9DONa^bwCsF6x4s_hzSby+gpS8JIhY~Fka9wMWyrZ>ak3SCFDhnVNyZPl6+I3+Q
zG(vQTZVL?y<j~SW&OCl;rblfFUp?ttGg<grC*4RGZ!0pNnCVrXViE>*mKNV*0m=V#
z!*wZ<F`u)d(Y8Y|GLY-31{u2DF?0ei>0Cs<>0Bo<+fhxdZ<&K;AB4rJV1(>|$BIbm
zKSpXsxIjxZ+@FniA^Vpv_a&V5$@`1&@}my~MFg`0TQ`fm$vU9UDNoca$y(v6m(hZd
zS{mmiTQ!!XofOlKZbTjb%xsyBL<c9tUV_f$hytyS5m1ZyS_heW`0@24SmtX_lqz*p
zGG1jMl6L|;D<PjXP0Mdt%O}_^YJaV9r2b_;IisVwj<<;yvS@_2;=XLM<;f^>8m)Xx
zOCS}yEqE>11D*Y_fA>eNDDAbO>A{!7q<*}oG1ya-z5;3RtkC)e(9Vlo@|-%UUv1wW
zr(eb9E;q1O?M>d6)84xPGE8fuRyX`$y5<rs_SwhcY9TKDX`C4s_PYxgJghHV;1tZE
zNaQ<22Sf;uy#3TX8nc1hsEFf)TnqRi%g}FQJ{^+Z4YD%!{Z9N(Pe|l^V@l%4TtFLN
zLaP8VUtcCNB&REM0<+lbgZv(4Mt@<vE{i}>;+ZPOS_E-YFR9~!1Ab=3UxHl>Ka+|6
z4VNR`r=qs70tK}LMA39oYa0lj3E1jp+Mc%1QAd;||NgkuSdEE1hUX7*#EpjitG!+e
z?Ocfj{+i@m$TA`j#29IHdw@$ABA(amHH=;YxLa&b#ULefp_ORyDkH7iT?NkFLk@>&
z4u%>ydCWXjqFq!7723&Cpex6bt|cg38+yNvWzMPApR>shsE)OUSryUYI|b$kzw4&r
z%9<)qi?OV%aR0BPrf>FP*b)rjjaBC!=rL9I(6FYnt`Cs`0712b&m%j=1^t(hv3KUr
zF2EzC0OL<{F~mk@WPDTN%&7SqQ0jXUXCrI2aprA8Wl!`GU#b<jsk4rirNZ(2$g7st
z4!D@|`E`PnI36qCN{@)W<@(A^Bd*F-lv3liygodozVe?Wx7w^{VqWSTi`m<4IRxv1
zMcTCZi2tyF$dY^{kaT|SlgfDhNCBoBXM21~LMmXu8&my?-I&Et@?3SIEKJ%AB@6Tm
z3-BA<OhwfrvyV!PW*E-4oG1cX7=W_3Zx=dB^dqNKgGu{(7isFn+bY6lK4H~)p`O9H
zQ;j+<w6^8}@$O`KsQN6wYog_thm-W{Xr{RuAifM5me~Xu3D|15%$}z7n#w^N)Mr~#
zDt<Mn99F#O+E23!^AUW%R^>q`f*lZDP@2NZU1~}-Dd@sd=(-igc}7R|$*_M-I=`7y
zLZBN>)T!h|3y_4BCEKeC)&x}f^>Dik(9(8%TYt-NZ{A%}_8Pyc5G>Xn{87cx4{0Ch
zmQzMiL~;SU|JdARF#)4g-M}#DNc>tvDe!kWp9-uu`GODWBa;GK#XpWG7C{ULQ_5hB
zo3|a{b=9UJ>0t=6>9)n1$~Y+j>7+xM4LaN`+t>XzR{8By1CsN5w3~ylBS0XXQQa6E
z*$D#9iIpEE++?=<r~<$#OKORTZP0lFMmmblg;`JNQWmvRw*>3_AbtBQ*ZaB0B5xr-
z$du0A`;@i34we!rgCK)@A$Af^m-12~_m==8Wqw`wjWbtQDNNDZZiB_(U@5+}F}z=J
zWW-4-Iu-|pD>%BLh-TDoOdt>MsN>jcv8u1-u!8n=i#(iJU_gd!_78X4Fhy{lHZBhL
z;E3zj81S3H-+#q3+mM}A14~+)JB_U#9n(l9zp>!!vwmE$R%o%H%}kG=3*z`$I++{E
zMZ10FcCm^%?jkLDcs4gEwVgS32Gp)yH9{tqD3G416LfWb^IBir+HBH2xmRn!JwIOl
zTM~r!y))bWY#Xq!l5yD_939+iS1zp?`$lYXI_91ZSPbztx8FGt+G{Q?2~asn)|S^V
zp{(*?s?=o?)~qZcR`k-u=e@)Ybcq~%*j?aH)W>3>axCRrn9tL~Y{|j4Ufo$feX6L0
z0M61j*ACKG9549}9&MyjR$llmoYd{zB2N<GA)}`zV(9b<yIR}~<FL0gsBvkK^_Lrs
z7Qfwq`#^2Qmq!0d|2&9I;GZKX^Vh&(09W%5U_i0pG~xqt(=VfaXYRY#)5<OCKSR!h
zP-32XS?|j)*5$%H<f6J<R)6}?L2b)D?Y{3<ms6=UcxDlxu%W~Az3q-D`3{F-bC~g@
zPj1%l?18ofMX7wB{B9*4xZcZY;{H4lr0|d@KL?KKaUHAj5J(AHZ)r$PTq6x64PfO4
zVFq{auSFO>ps(SiW25)q`|sQXOK;`Wk}T%JsJ)ODxrd1Sr-JEpM=OJ>SY?*B9UQCA
z*i4&0+<}?}tx_2vbdzFhhyaCs`rgb2*pMBde3jzF05fr195`j28KC@Q2t@x*&CMx`
z6el1(<|H`JDY0;;BdQ&a)c4j=t3c?_2&!toF-GhvmzEa5W59`c22g6(=}ITMiWNxG
z(Edjj3E!*|dRI8me!-S6pj9{LtP73fW%8ThYgTs%fCfEK@yQ}D<kxl%B7&gbOAMez
zQ$>BD;14mX1}Ol(m^S*HcU(q16Al__G%5JP>9l>Y>~<cf6Ue-mr{Jcg%V(U{<uyMb
z<|rdNlaRNGy>`>OZwDWJGZA?}NeZ8Zi;6>X?X)|&UOlS_y`OlVKWL_CBti4D@<nT3
z*0lo)^I23kfT7j4?>uZF0Y-`<NV&lEOusbB5D%W*2|d6?;qv>BV3nwvN^Am*YZP}3
zY&!FL$-{=~i|tBk4@@R8ha=8yLHOut63P-ha%l8=;?{?E4l+Ozzp(YtPbtDBZLl!H
z$ckk^P}znxJ5L<J*4376G3uxmJ6vyBR|1jxCY$_4#tOBLR{^Ekuj&-Tv^&U6?i+i>
z8|r<i?D{fE;SqOM(t5w9-h^v~(&~=k$(1SVM$ot+!i#+tA73@pd!$P|<1QhX@FoeZ
zI+%={^OtlMRPVKSF(XR!guD=K)fWuYSC{tkE`0PbrBpSg;*N{>Wyh3)U^Fei^y5GW
zuSuWz$aPf!{=t<t7tiBJ`@WJdXhdc2CPzu|hJ}HmDLpCJ$tJ?wPM4qcaNHSa<RQK9
zIv+6_a4mP&T)cYne81)tpi)=^6uCTDOCOx&;V3)ds1(Zj1xRQEn`OXHo+cmNRUQi~
z;pz<QKt3=t4tlWJr%H|GW?oL{5qoB0I>o%t9w`K4Y31nEaI@pm5fscZ1VrSwQdgiN
zu(t@f#Tc{mU`fbiU^W17|JImuw=VhWx)k2KVA$Rl#<YvvdJ3L(0y4-erky)n^+xqA
z0$h0TcVgto8Tz6SBI(28T=kBVSp+i0dG7a3V|ieY;0glc%VJE{&?a+h8tR!pz%Vp^
zC!bz^60f=BpJ-+Xeh~ZKlDRK5J>bao50sDEH_XS7_%Mq4+l&rrm_ig`qbiNrQGCNP
z%bD4EzF^HW1TYcWWGHH#Q_kDe37*`G69p!vi?gsfJ^OmOA%&NiEsQIcT&Or=Qxs67
zne1U(q?{pjDIbafkbm{dSovLBfBoYW6e$`vr-#$`CaxTw!POg!cFEXzdXXy$;G9Hr
zZ|tEHK?_GE*g<gmu1ox8^qf-!(t?M4u<@&;`JPBAo+ErJi_XFyJV4D0khevP40QX<
zaO7!SwR&X_XEiLTI9+@Y$q>cMY2BqPbtDC|1%_iygUNZgXBT{p?>%R+DkPgVadLC#
zRn*nM?NtE1FSl&wARuw%`T34|u?#8u&<`)Am?gcA@)mDaw5EImjN^c4SiVQ`s3fhO
zdOQ&)B?IEAuIhjbn(9OzvN9WWZVL0d&^9Ru)X!9nE~rk^+twtu(0ksaXJ<sB0WamA
z*`344cPK{bJs0yG`60U~pn*QA+oxjpEwud(nyJclQM2eV44{!oT5g0q3Xu>)%F^0V
zmF{n0J-8-pIqP0b*s*(Ey(PAKFr3Q?83}lja+sNBm9dh>ZtjBk4rpeZTu{v^VuO>R
z5Kwt!pPg<HU;h^%{|GRZ8C{24;hflgbd51U_52^NCMGgQzMr3YCNwRLPQTB{0Loc2
zx!TrZ^!4%QRO5kcJq$Cq|2!|>1l9|Z3@MKhKuj!Jh-Phe6E;GhGri-tyiP&dtnb1f
zZj&DH;2m~NKZ`|T#Zjlt7PXHZ`ZY9rY89tPhqt5WXx$=8uX;LsJd*jpCm*09C9XIJ
zUx{BdtoO=ympjtBot}Hz;WU8xXS(KOzG}8v==@Zm$5L?1Ha9ryKZp_!3u)f{V&tQ!
z@-8rm1@?jLL)}gaPhG^YtyI28YUT3txz|0BHfH$A!8f(lz-$aDkAjd=TsbEh*`_lM
z3Up}H;sa=FR=-rKSkQCtPPbm1Br)J25mf)4mGyAlKb0vS(C4z$1S@r*lOKwH5^6P-
zXZA{%RlPucD8LU*Iu?dpk2kp0(~3kJ+l)eZQIM;o*n{tkw1`{PbR2v%XGWa!b%=zM
z=kbQ$lVc@Xn&>Ii3N-LtJ!d0aE}j~P?i(m>PYNFbYP!M`9TiervbrYH_nr`s`seZR
zi<mliM3(Ksi;uSLgbPW2+fw)IXg&A#XOKePuAgr%gWYAo#vmtUG_>E?c3{kb&?nf)
zLF0r<|6cgSe_ihDM=>tt5OLwcyY?e+oC@?&S>A<pkrlXR-uN%qIrs07>Mc)xZ&dBB
zkBY1E7WyXl*UGPW*Y$Pp-D0U2e@6;hm4x4O2&o2tDhPO_NM!Z93b3_)EZG+%WjUtv
z*`>RU-AL|Or2sVwjbr{wkRm0q_Edi^8Y_}-4j9kdI-XXu>k_!<Z`6;PS{%0mYt~-J
zW{85BD5^R+xa!-|YO1eQB4XLA2*Me*kX-?2wuF~fDy~dwy+;AP_M0>z@MEg*I)ns`
z7D5fkI=`@Hy3^`oBezKe_nKtt+prLuD|{#J-0h0UEQsgxS8gHpefZBf8i4a&v&Mtf
z$_1l9FEIwDgNE*U)@j(oI+MA+0T2=6wZg!TM4V-54tv*&*bHaJucp)J$oif5lym^w
zPI3X+@y7FJ#eQyAV&9{rp69zb<`RC;sRDM#(yNdRD6va?mpX*=>twr~FgH#dpd+WH
z1iJmT<hupPy+TLyJx*6?FTPs@2PEDX`GsUtZAh=q{IK7Fe0Vw&eR4E()g}_D4wu82
zb^so*sIjoM^x3exATFF5@onM_@r5*w{_qw#CB=1H9fDyf6Gb*FJtxyXh|YIfvVfL5
zHQA7>m_=p#15CWdTp2&kau9FLoiMMviE2yA^|#wW^AH{&x50!VjIegDAg1Ds1HT27
z^j2Yn--j`eivH~qG2$8CNS|x2cn+LXJuk9=<zuL3;loz!)-+*5n0;Nd=!LYtO$ZlS
zMzQ!__bMj=kU(TXPKFVwLGEiG+-BJulv&b|mI<_6wMHRnI?k@p!(NDgLbzPzIREM|
zZ}S|Mr88w1pD1L@@9JF6uN!55XMc;&$s-reUYfHd+qMnGKdt~69MZW)rg$FE>ZdqH
z4sFt0b%SRpTsQJmkhDVHO*fff+NA@#$923VMagCEogipBS&d7q6v6{9S6ZVNsn(yN
zw{Cl3vLYH(>{QeLM=G&T?zrq&R^K{uGt?F>Y^8DkV7|{QSEd0hM~+R%g{+)W28U+b
zGqz0UN;h0)Eg)<;<MXZxCyv2rkHI=J53u)3A4%nbCKlfa=TkoccKyit<=g~ph}7D8
zbRlSNta_mFfd7|mhD+zy0M|HLIBLI&UMMdBW1JLGHP2vu#T18Rm$RC9kr#a}#kUlQ
z4cW&o%dOuJb&XXJUo2Rl3lw6`Zg{CEyfP@LAy1_3n?8R&jX_r`t4p~1dPAH~;>P}^
z*L@MTr^{sS6h~~igheB0L&pz4#@1FbK7QL1Y_Z-PfloGzKc?{MJBi`ELO=>feLV~V
zfw-7(V^JOO|AEj(45fD?aeRL`Tn`S!S#)+oOrfe2*nFax%~AANDl0eJ+4D)WqX*?8
zWz9NYa9Wl&A-4tgY15U83NB>PR{=FQq*QIN%VWafz0bQ46tTW6)f*&TMyWgLxbDQM
zoc)ZxZ_4B<*)mt_P%qp2`vMVybgmpMLzI=a0HM`1nvC-=m;g{SDTQ1`=MW$var5?I
z<{iOB7KA~h0l)uMxAyx!6v@7;RCl&O(tGP01KM4&;t}alOxxV4(c%c?&99!oGpnBk
zrEBn2<-1%sFuoIMf8fZ@*mp9ODmZ-8&HY5crHpm?HJ6T<p>OHGX$r8*$Ys`R=B1wS
zkRPi?JrV(3{>G9t-2-=X^m6F-xQIYer2KngZK1@0t1k;4k+qI6^@jMCpnR-IV=7+z
zvCY~8;SHj|K|7oB+w93`KhlNc`bBkOn!r0M`4p|Bb>bRpTt!%Sa0;eIVl6b0c8vUq
zT$fP37{(=OJ9Ff%%b~<GfDoXrwj0qBSU~`xUbKE9Vt0I9hSc$evAke=0ry4~O9}l`
zjx`xl>4|ACh~GEA+JDG^F&N%&CFP#fwB@5eARE-b9e8Bb8I~5J(u?op7#B;!Fw9s0
zy;u)1Mv{pxOeIj5+18d?&UFx`fG%gk_5T){s)(cx<Upx5KF}^=+(=DjBetCD5fL*3
zXLBZ<D!E+jewH0s@=r)hwx^FVf5)$!$(F~_`=NExSO5c7cR)wm1dKr1_xwL!ceTc{
zCqGZ<&P<wJ5S`;&Szm5k@Y0+j{-VWd_jec@zM98hrdFfVKMUaEE7U3(u8w^$2V&72
zB*3hAwLug)u?Sud7+KuE@kt>SdmwV;N{C<*8M;I?2!cHgN96MB3<uNmywZYGjO4H-
z-cH+S!A-ufzuY}F@5NbefK6(L+Y2>HBoJ+)E9-ps0XgKi?(EtapvfRt{6^J|_5Cvx
z9hNd-oOBpN`W#hoBw1M%rPFZXQj<QYI?N@m)G9*e2!qFAQ(#HX`m=l31=g1!ScGwl
z&=Q`bkKbMdHiyDCqOYmcx}<!g7<Rtx|NdD=FD3D&hT6-1%ZzV7uM?mFCIJft(!hLv
zMlPPWERTnhu!GOb^ALK>Zts4*C|jm&Mz?Fk9OGA*KZ9Fg+>qP%VYU!}f&rQgFT;JC
zTJM37EV==m6k*(>gCxLx5N$kR#Blpd3WMqfcX1EzlNNGJuX{`*8l{l8C^61bx1fV0
zxhBE@$s)7(OSi+WbC}49d7(}&-UbmjA?gMAd>wKXmsR7MyAjYnG@efe1T@0QL75Y#
z)a&)Gx?_?CMOp<w@T?%;{^~C=F<jenX5*xRrEfgxHF9a0f!5+e<9n4MnCk&^!I{kj
zP)Cpt&!|O361Blr=>hl(+O8re%TQ-{go|X>gFX7_$x=wNBn_e7+gtAelP#H+On{2Z
zLW{wku))G^02x8C^*C)AHzKdCjOP6grlZ{@7hf16d2CJ$2t!p;Zty%*DirrOab-iq
z=z{d|D^GtmT8fa_{Cls`H0&2VrVET&Uu%-TF7C1yPaqkT9ohPbpKeR%1%PNM+{zo!
zchjj9qt8U%6{YO*B3t*A`}!TH;ZW+_-!;dtb<IgIOcm#E=A-A-2JQ<c#=;+Ml?yU1
z7Vf+6#9TOoPty~4jLBj&ZC_ScJx#FSRO(t8+HrM`Jscz^!ME**j^#Ba0lSMcscuaf
zVuznUUvwXEC-+cvF884M0<a1S8|N{=ss2glU%_stV)3Jeaw6-`64e}Pjq33sOV5fp
z_^Z@4z!WbTUmYHUI#JusQ{T2&50aw3FtMvWPA;^Ld^XNY4~Qua3e*sS2KMAQes3Yt
zmS{23E}i*l1EUN>lPL)qp@opmZRwH{Gf&aC(^WXdNpIQAjsRHtzB8sZN#)p_P!1aC
z_ER<vdCtdm6(Csz4ar;Sko9Ezu9~@CFlic1Kv<(r_X4w)h>jAP!Wd|4mdeuCUOIP)
z&bD?oXW}1lt@HT&%hA`nc=?fKjAy{n(_R!`YhAVqZr1KqzL2VYj^$v?YIrq4dD)2S
zn>y6FSKZH30*3&2CeUiH&uk)F{Fe^0v9;yD?C!3$@ZV}38Wb276TF%FF1@HQ!#B%N
zUUOeg*YOfzQTOy`JkTNY>l{&MLB2as!|y$Rf?TUL{>u@yuip>j_A^6M)G{x#ZuUm3
z9+8`OL&e}%F3qh5STkOAhL>CAZYdl(6^j|5cc)?Aj*B4h1Gs~dc6?@w=6BJOmVZ=!
zMw<pw*@pb28$Bj9R4#h`bce$gd*o0fphy)2BToDR9iQ>HCveeXlT)wp_p6WTsEB1^
zRobGxPeO_~3Ob7;ZlMCuiP?b;r;kCD0{frN-twyP2dyz*9doA3K|-@=6trJ4PC&?v
z88j_GfwqL!)7Syt8eTaPz<?_p-Er`ladvMzdmvS<Zq<|2@&$O$;Eio^R`aM9N@$$V
z;Qz71;`3jqVHL!`F6i5~*!=~FZ>{H-CmEli7d!z+BTb2@P;wrsa^Ca4uZHMx846_7
z6Q>9OPTeNsebDBzRbS^Sun8=*gtIoKIx)0`B`?<slUr@w&@|+Zm^Mn2$%$LMvE^@w
zk$?x9_XtqAwj=Bf-51|n5yc2BcvW9q+(EPPz;OcFBPtxK^x~AG_CrT^^q{(tr;!Ci
zcN3@P!)>$9A7DZSzJ%lNZ%&d2te-`vMr+%GyEb8`Q2lW2sRNOH{`fb_9Cw2YqvCX_
zEt{$#56jSlHv3*WbZ!ZQGsMdkJcrl$=AmHnLrKO6?lh%P)RK^gUqE~Svc3%(T)y3V
zJ$$?}IClpLCT4;plhx37Ua-SjPZIKCJZzh3ty#)Rz4e~^Oz#Uv4-v3A;P+m#IKcTA
z9bQPn6o_k6C5eqWra!=jIPSDoZvHAsP*#1FHljCyU1us5ITaA2vk^Ht1n5k{Dsrv+
zP4NLa@!QLC1Ap7AQF>DYBw1RiGfzPAJr3kPm={=;<o9|pa}C6;tQr<Oq5)VL<MMI}
zkOORkSKmNuc5Yc5-r5aN_laF&wbvmPj!`5aJG@*@ZOvdSGq2jWjRh0DFc=UxO-32i
zG`w>z;#*NPd4K2*<s2}=;hK?{+wyFTgzS{OT>pCk)3C${My^^F8Xj7Rcl>>%qCcu*
zyoO7mVxloGW$`b-a?KhJ25As5t-n>C$ZW*JmWvB;+C%>Iey(92c_j^lQK5x61=GF5
z7~xVon#0h?Axi6w`891<we~345HSI%(UupoX)V5$;xb7q59HmPYrzBa<w<l8(3x{t
zpuUuPKfro-yHeiJS^}$jtys8S-eKsvH|n1@Vh*aO>NhW}Vs6AsecN1urI@xwp74v)
z(z6++SUkq^VBi<h*y-B@D4g5~*Ofn?Z$gzip5eVj>z?|AX>DHe+1pe3aC!*IMT(d=
zdVd#j30wyVVYa_8i=4%U1iK{9^}UK4DwllIFC~*SHPvhD8|iTIc4=B$$(gz9(qla9
z*yDzCD7weMz__CNJyLDUNe85kIWX6kVLOL@)iR19^^jo6IaN%Z4RXBUy~UzHiqPgX
z)HA|e_#7fnydka%k(?=?Sc)Ba;e<qbx@bn}@!Nm2^>5!wSC*66b~6ouyy*65MuWel
z8P#?k&Qevx6SqCp|6H^TI(#_JjhiDn45(?gs}V!G<tVJL{C=zmsj(C_v@GOxw%sS=
z^&{|k`nZ6E+3>U^V6-BDw#l$Cp5m9NVI^7}3tLYjtjlpk8&w&@n0GwLbTl2em#wrF
zi`s1<8u5xi-dJLFN6wH80o7mF&-Xw(e(YaysZd~(N1Pe4Na{F^a;O5;C7^AdR5VPJ
zbQwH$)+<Tk2U&7Yk?K0jF`kbP*USy6*?E<ly{D#ia<*P}L#UX&s~+kRQU+H(+=Ls%
zJ1dL);5{I+9_W*Lev_@Bq5{%6OX1w#x^dzB66+B9jGjh<`me<zWkKEv(KB(JEvDlv
z!#1Bj6%HM10529RV1dTcxFqdb#S=tA@=rDx;>%O@Av(Mm$=vRoYHWJdud)xM?S0m)
zk0&Q_b=`6tb7f8_6ogZye=JHfL8dB+`2xJ~v4s!(vK<!{0Ft&*wkS7k&8YX7L9(xx
z`dti-cca6ocW8DS4U`fcgRe@z`Mviyy05(g(Qt*Jl<3PT>b(>`dY}WrM`Ap~=4|rb
z*|k_Q>D>IY7X9$Bav=v&>-pvQ?y{RgYv%H!riP%_9DsSLK5m`LiEY&%nhh3O-&y!!
zb0{6#@H1Qf`Nw_YdLhFNh#n3wwUV6Vt`h@#>_9MMV!vpALf)u*c~h_%cH9d+_~+9&
zJp+<{uOhXylJg^@NSYJIj@E(7Inx1as)Ig2Sn8_Lx+A|NE4670WXk0JeefuX>xGyc
zRH{^tu?<W^tEwDWtz}XE(TEVT-l^wTb&T1m112*^G&w;s?Ynw4o17Bw0E87#CPZQA
zk>ELq(*(aSC%1#Tn_eZVh7C3QUq@g<Bl1aYPw}fJI9I3+OeTV`zPwN%fVxAwlr$0W
zzYI8=^;!~+a7WM5lTg^)3$)j=x)zf7XTjikE|Xj4f!A?Cpl7)OMbWqniq$mCvgjX?
zER%1&HkpTE7oj?~o0FmfY73^2{>i3|pXv`!7VRSZQlFxgD<5HrxF9?2E;rC%A$d+%
zytNYtu-j~b^m(~|jA7mx0yGz_1@9^0>^CrZ_|gU}NgmyQ&m|`O_K_{(Uw_fUPUG1Z
z!=iwx?6-jOmfKJFQ>7^6`5}fKPEjloA408c0AYZ<%eLN_;E5R9<(NL3#+<z!xToOb
zQA@jDAHS8Vx{V`tWL=jPN1h<d$lwrba`=BqH-#G&m4QR``JFP!Wq*V#((Ec&(mg@<
zc4N;rtPphXEKIC(ng{H#Zj(fxJQam`SUj;b8jv{Vp7gf@ZO(*+_NmL-vjQ-nThf%%
z^q~Lg$YP%etrpNkT9Nr=c%ncAux7Vi%g7<iX*y%9ZwpWIyrg{L2z5o3j*6y@_#&I@
z`yc}(S&vi7b~|x^D9POs+LU56X{dE8TUUp)s%5PTRxDqt^7nBR^J6}0AfdmPW)DT3
z=10jPz(EFg{rb#0$A_T<G&Dq-J?|*!c|ykyv$w-S-iT0llOCXY{OvYt8=YeS|H<6v
zkXt5zb*@_wm={Ms%CR$7z1_Xvr>&Qmi_sIq?Yc|aCO%ybtFueWAsgWq0!Tbei!Xs8
zX*lALS=v=0ktg-U-iv?*HJv<xjVNvavh+u#z26HDCxTYX5Yu$w6ob*U!w<lqAS>%7
zdB{o+b|iP<`ITd_c)1^OzAn-J+889TF=;d7#BrDui>;>OuQyN&@S42Ao;|!zu~JI|
z9h#8%C+bcO>ns`Ax3L96H)N(8bkJa$L(!#kMx<>{+7yWY;=Ac&z7i=1-4>4%`4UQH
zC)Q6IE<M6`3HePe+^cb5@!6?|d6Yx#8!>~(0<{~pnZ=S_)rfMi<FvKpJufw`|0=Wu
z9g2-duewSS#p`M4?D39Z&^Bc8AK0NtdP}Op96_}~7u2Q+uD%uodS!YtV-==>%H}C!
zY*ghZwFPJ<de6k7tyn~gE6?D6vkAw!uR<?7?qe{vX-Xk5qC0VoCP4fO{%5K2FsgU6
zbHd@`x*>$v?r4WrGrLQN{wrULM`2_Ks8i=1`gl@Xis4xsEMO3VEftuXD4Lv-P(!Cg
z4g44pGewupvrxB{0K}`#sK3F-`-NGcFL^3tINF6FpHw36JPanZn51w~lHV8PF>ET#
zb(`1ayUhv&lIP^txKXYbn*hU*QY?6Q15bEO!)zZO(&!#Og~af2v?h+f!kPQo0I6+k
zj@*oTwATw3|7a4^TNfQO3!u~?$uy!P<P+#{xF2(L<Z-Z-6vVzm@J`u(m3J6uMocg0
zJ7-kkiSL5<ivfaNTOYnS=+ihm7}u|ATQ;e}i3#L07>bLDt+#D5?l#X4kgK25VoZK=
zmkpxPn3nNohYWu`K%iS^ZD6%aC^2E-Ly=H|K#uIfNj}5RyI%RRDo{LQ5C@VR9JBMz
zXg0^oOJW?8Rym)VOS^IiW+YX<0ku?aM-0(BbxeOiR}stVmEeFy;XhrfOt|(6O)axM
z1W7G#%{G!?qc`=l*Z4){z$Xmy#MBG=N5{?bB(->ko>>K-RBEPW0q1*%eG(fzJ%|@;
zi@T=$d@(tC63F5uhWrLhg}f>l&FKz%_SyMWH}D{-O=$;q=UmNefUYZu0ASD$lZcdC
zHK%qx+QJU+%QSR(>VTJdpZRuXTu2DM38=;Y;UBXjI94xBQ<y!h%9Be0AeyMQ=p%d)
z{Vf0j&sk+|U~(4WvcmCx)fc(*H05s>@RG4XvguUHN#=qaW$L0zNkXCtbH5|U)eY`I
zj#`^ih2yYYOp>5v%k@`mj!|u6_J)^{J;NGYCB1thx~FU3!s-9tk2mhgdZGiQhPFV5
zm|pOsxNW-uUQ5ATpH{e#(EA+?^=k%zyA;>)RoA~O{y0zsNY`kweqQXG^uDe2p*GS0
z-dEqOIB;K#lI!K!teYUvvsl3<T(y~CK-x^E(R{*HA%&6nlT0fzgN#A-9@_*bVn62+
z=G6bO|A+51U(}x-jlk@;p|hElKu;sp8*P7e8tv*c)?4tYVmJ4rq7Y1l>07bXN))%q
zm;LWgR0KPv#9fw7DO&vO2WCSuJuAIo9lZvE@182d{u<TAJSpFL++3OsNzQg&8i#q(
zom#+a&;pb%s^_upR{f(LPC;xS>D&~sgh_hhu2%#o{~oS@dZ$p$=o?K?*Dayv4!fCL
zcpQ}`$a8xYGt>$gkWbN5dl(}-)>jSW5}||^)>k})<})o5)*DQO$MCA}_eW{gGAbYm
zX3D^jU=v(Gb}=2Z<#4qE|MYYvD2^1Qg|cK$Qu$mq0_nD=#o~NV%VXGr5=;fP^v^_~
z4KO2d7P;lxmOYmH%|*tWU$_xp()tT9#7~@un7Hql5=rSORe#uUDyapD8`AKwLz%iz
zn3;eG?UQm*dQIho858UpIO4(5@I`@8qk;Y69;je0$91iciK-#C%`P`=J2O3Q$QgA^
z+3T(QP#6Ye9}Uzrko1UQkiDhuKB941WzYc`Ip)UT?@3AQe(|G2QQ&`ziFDKs^tt#>
z<TpSUqX21#0OOE1H1eN;=FM_Hv#MKLs_?v4)c}xLboaqlP>)3VMqvoICLRj`v^!ZJ
z$VYaFJsROce(Yq?`KnVWwy%;?gw1Us><R!z<}0Y=D4^;yk2XWxE=UBz86>5&QusnU
z`PW?uy-+Hi?9f!^@j}lbSW&I!9`kf5_`IG#&yR*9o2#BQa^TDmcjRwN=luq~)>SA>
zcSAQuSV60S5DB!Sr)wsps6@GBUeGoN@!s9&%~7-`?-W5-aO_M$-|Cj8XJm)?`me&M
ztwA^GTyS-g_RK0SvnJf?5b%5=l|OgMA@FE@D}xSliwKNHgyaL{FXnn=Ok$OI`b|m<
zNv=iTex{WAH!i6?M?<E>)h0o5>4Zt-<bv%6t6+eVE~QH(VJi*|z-<&OUb6`72ZNbn
zUOQ=!cyB6JkDr|yBCuYAQWw?5baTy_ur&kUvTqO#EWi)Jq1AkASC>JT`e~*Rzblud
z94|SSFm#(YJZ=^Iay+91|4}k(UZe2UJ+@u4bzxDDXghD!TMVvBzR&JZMa!-4`K=0r
zDtF!tA?9Y@ox`4$P*ILCw&@%>BT0_dO9JisEO*r~5m#)h6~?WPn*-Xh#|$5?7vnhy
z$U$;S;RB2b0}y8BETdP0?(%xnMWSE^An7-iG8EFYi6rfmr3lucC+o__&06bU2*1bi
zxMH%*U^j5|)}tr~W)O4@C6J>b27-Tbhr<6fE~&TnO)&o^g?DR4aQHwD1_nQ?YvwFB
zGW%f-XrSwMb%%O@9`F*SjHhhq)#zF!WXxEdkbhS%m8QV#z}+|->m>%1smV7PZE|6G
zZyt=$ox3%^AYWWdHk4l!AK**+&7Rrmu2222t{K?)RMxIH#-!EYk|@E$F5gC}IZjNZ
zqW~M6!Z82?hJnv1+ghU(bea-rFi?Jcc?=k=#}>liNfy<=)=~NcX`Q$eM#b8rivG7}
zK-6vqI)}!H<0b-iL}2o5Y+M6hOrqk;!7Z;;nNDz=M)wy1VCDU<Y@u~t|M{!$4$S0_
zsC_RwhrZww4dIhTaE`Dbvev96Y@4DsnzwVEW55A;Wd8r3wE@kUAI%M<e(MvEeLwrA
zu6}<9Tlwf}C#G1X3@q0+ME&rMDsH;^zEXmM`#*<vW-6ApDImlQ1&)V^B09ZQEezF6
zrQ$#UKIRtj)A=@^oEWmymT6pH#;11XD^~i`xmhmfp~OhV&-Y6z41*9@dGA~MXXfLZ
z#Y%|0yr2I3u7UEmjTEir`_e1uI%^LgOO^1-a59#vpp<C@A%xS@lvO1idyS3d{}T#T
z)>M5Z{Ff{4RO|E*bLSCmsf^l4mU?x%p>RoGF(Urt8HTzkCjGs_CS^Rf+yJ<QY`Pg&
zue^M@^x@b*$g`}JR{DfLLaTl3B26rh9qV*<_a*art<wz4;2+U6GPA>rUJN?!UGn)Y
z=dr!lw`G8ZN<3>{!{wtchgLT(oc`5YNcVVwoX)E3+7qBn8O#SYQB(3BZ5T}=t@K;N
zOe0c6J9$ZGy`{-nyF}{Bx(2#^&#$9DroVu}S{~~c*hT1G-edhBSMX~`fMz#y(fyo^
zC~fXcYvPeV{pMhWCkih(iBLDEUgTT+pgO>?d*;C>U^CbiGn%ocyDS}eNbi@w`m^Kq
zhoY?-+6Q}17VV<PdahF;K}gz9%YdXn=g~4o9s=Y^!dgZ=xHAR9)WK6|f++$_lREj9
zGf5m0ESL44omWg7nR?Aqr|Rd_`a46vQU0y7e;+6j!W#*Mi36eEiyVq0jq{YQ0I!>9
zT(Cz~!FkyqDz{fros%H_A}0KNrRoQ+hV9R6#k5ofP@!fQjhOWr{(uqbxj2%le#whC
zS*L*6wIE)&Gw^jWCz8|#v+gf=@Dk1}3)rV223}^kB_2ysz3$gWn)LArI3dKYkQ$@L
z1Q<{fQeiF;wYzR3j$iDliN1fCg+<RTaiA?fTn-%LV6m_ghP!(~SczyrL~89+lq!SR
zJ(TR=j8~}21OrGVM<b~}nf+sJrO<7Gku5P0tMA#Y>cC^S#~If}429YPu#OKri<maU
z8knenM7_=j8}C#u!L+U1Ya!cYK7b_LeNidEz89o5T5)dfMO*=o<(ryj*Xxj3ZFKO?
zIYcnRtRg&apu!>1gQOM|m_p-A(t|dd^c~cXB2&-t5rl_P(W)$bA<<{@uD}}x`d%aS
z4KB^q&iZ^%>`(J)oMmsqZ}iS$O4Rv|ln3GNT@pP;y62iZl5HcUaa_Mz+rS;E`PmSn
z_irW+(c0M>Rifc)5tfj0VEW+g@^s<%x0b7a`_4+=){lYGEh)Z<{M+8jgd6fPYZUy|
zE<S{PI=u`*FSN^{6tdTWslG=D`;Q2miVG#~pG4Lt*X>f*b^*YLJ#t?@v#)n|cb4ST
z;0fcK6b?sTD%r~tAZkA_um?>3rd;PsiUjup#jw}bPj_zB_MYsG?lA@sP762P`^kci
z+-xv>Fb-@Xd}-s7KBS`PK7Ng4I#q&BKxxRBs%%d&{Lpc&mA96v=PT4dV9|D-F}r-A
zE8)9nZSqw%^YsLDh+NNb91zwpY@o$ME-oN2kxNEw2~R3|{3jhD@jd#2npuDY=lpUr
z-?I4)I60h1@%rWy!L?6spAYtVFz}Q6Nvu!tLdGy+GQjdNgzn&~fUB&t5^YFv{Nd<#
zrjd>HJjasFEo-G4i&gdzPe$WO026Upo=te&L=T{EW2p&$RILhvR5Gp<uk2eF$!R)L
zkHc~c2t(l!SvmPhkfU{arE5Q|)m}^86m)iQ@JD+>@-NWGdT1q>C@JcD?T^ErrHtBg
z_c^F$$e_yF;TG!#!=JJJ2-2^Q7b@s54;8o4H|78H^6Z9w@T8<I5)PeA1kKQPH@MK1
zCUY|0?4-^n6T`!K)lf0yk^hwW5|PeACj^hjvjXAd7&13{z!IOY-ERFJ%*Mi^BZ=(&
z_C9pq4YK{hyRe=2GJt&TBY(*$acLbO)egeLM-4d{Xry6ey9Abn!NTU~ERZv2eZxl(
z-P?uF+R%Q9VtC|p1TWV9595k@Vt>!D(qezshOzqbl!Wsk(t2Ke{x={cAAU~;)1!4Z
zzjWh`e#sFoCYpG@C0Sk9MZ>**_N-X62f!#Fu?o`zvFh}X;`xq%e7eT(AO^-Q9bqF+
z3NRyb@$_tfC<q7>iGBi&)ZV^s5=45k;hR?dVN=vUHV1}6OzidwG-kFw{~M5cRa?F6
zo5oJ-P70X5fFuLDs3{ygQBzq0koeWBkZVK*aEW4tOc<&ddC0S`zQ!?8#FgM=R!ye)
zTy#XjoPNQs-RMmCgf>v}oC+D{$V-72KDk5R1T8a63EZ9JgTyJp|6zK8m4^I++%Hnd
zygzuXn*_<$cx0r7UpG-FFEcm#z)R?k+DAN7mSlPQOK$Qh`~6!1H#gAW`xBzZAirL#
z23Trg0|Acb{tJQWrM>}JSqWzIY^TJhiY*-39Ya!71<;DK4~<@_%$z1q-o#bQr;tCu
zDkWE)Sws7kvTV6s9gMxIsFPIY%uOUDP2#%5yj*521{e*0fuFXPHU9A&ASdORyU?)U
zpbBx!MY(s!zskV3$hwg~e=bH8jYwJsJj3}qK2tJJep&s*x(!qkQ&`2g1pVuRN1(>=
ztoMi%4jF65t(=5-Z$&fY!1S_@MRv+?OX5~H-QVPev?sCx*m{ol=Xxo@)LK_pp$k~O
z*a7pSFX>J`0`lNRG^5^JIB#5?+^>)&!-gRDP|?}`U~j){!mQAttfAyM6}w+O-V)?I
zBTB?OQ#DPSK$Cjimu0bTU!VA>Zt*s{Nf+X4JA`7qV;oWB--Z)}j;3|AM|i+)AZEQP
zK!<7w?>u&`Wr0iHX0a@**{^wQ{f#vLH^uqtddz;7#5yP+v>-WQ3&nLLI*viRNV^Pr
zRBpa<nXERK49?si+RTq#a=Zu~XcV=>JPBLcvozJS5;`k!lR?|^pwrkIyz4&C^l(W+
zeKMBHH~z*8c?z7W?qzb3xi&0NU?<(f{rbL3R?c<-AuivhT~@Z0)49~0_LnRwbEC<$
zgp=Ky#i`&tV1V7#{@czSf$bN6gh#E1F)nv0_oC0;vJxnP8j6|Zn;z;zNl{gighS>P
zE{i`EvusL<UeMWbi|gPDQhNr}H;PT?K|<hq#T5wcp!O4omlKXu<-=W>Y#NI`;G<ZQ
zARVJCcLO-qf*Vg)3&7o84{l-F@%U#Q%qO_8p$<T?cTBaArpi<j9-GPM&FY?*@WN$*
z(7y3rU7#u|$585uWoqxvP>v*+0VMxX$LOtx{C&f3cx6bW;RAd5bv?VFE<<Ilz*Fc7
zZ*{6Z4JJv;<Ur%3m@|WYrQn$a>?|FZ;Ab_t%}3tx5x|CF+kGvL?$mPf8`&PsI2tVU
z*hm`xp!GkBIe)>$8AhO}R4)F$en@<n=gB0s;WG1$cbzWUKD%SI2~wXsi$W~|g@acn
zUG{u0Ze+5d*Np{P+YBS1M)YIkiVv{^eP_Jm)P_dddk*V_{{PJ=hkktsKr!B_#<v@2
zR|$QO{!lE(pPtPTie$b;+aPvr5QGkEw$YNdU`PUSGG<<BtsixCfwyCN+h3QWNi5q4
zkr`l2)#e8~OwPz-2e~pq&{4EXR1g{bq!BqHC$WsZvW7+eDIdWz-F<$UWw1?Rzv|o$
zWg19_CiXPBU9O#A5hpB&-LF)g_*>L>(s$D6xOm{~^Tn0qldb8+JO=78N@U_u=}sp7
zsra*5TVB-eyAXd{pe$_r-#T6dACGZVSQl8Om8q%OYw<PN3%XKO13FK%@={{612F-V
zHa(o6-W_)dgRW_G$FvP}P%N|phc;@0E3f8N!Wv*H=y%2jF-mX@L004kdTW&kxo8f=
z@Uj&#x<C<le=BAiGcsbbxM1bU>SLQH*1mtaDV>bG9xG3m`OuEmdLfXH8m@~3IC(u2
zQ(3NW<47X~5KUVi**x1l^^}ZdqxTizKNNa=jpF9*#-t*Hoppmr=B&2<95RH(%%jJg
z)Fo*WXIVqW#x0R$wQ|{{&!6VpAX%AhdCqzx$#&|%4v6wSnOxYRMhm{9X3&3+Fc61o
zxP4$+=S4DQ%NSwUL`M{b`mO;qd**oK(O<WYbA-P!#Wtr7)r#gIR+zky`H=!iuKu=;
z*3*1<hv%-awg|4!VtIW+ud<Om^xH6*r4~xpELDTEq~wEcppt7-Pc%<XI?UH15+3Hx
zoVq_WetKxTeoS7=SPil2mk6IcQFl(1P>TTNfbN-q4o6E!cL?5VG*6^ID0aFlTQuzK
zYS+eTyJ~j|Zn#UI>yZ8pA4Sl_{7$K;Bpc0MNDba7fERd!w<$JMY`m0-xSVteDklE)
z59y!P3XCl)RE)Dj*Njhwwk>p?C{;%Ztu1YNo{ENvuAF~l*52jXbiE4#sgR3O_-KHh
zj-rFy-T~>5NI;%OLU8tTwM)<0>v?lpOIWsap|}mgTq*$dkRi^(jmHSuj_Yej$a=@Y
z+auWQoifO#La`e10g7FWSjXk~v+tu)8D-_nyWDYOeQGng$Pwi>z(?!Oh8}yR&GROa
zcgH5oO-!d}#rL>U6wB6w`hykd%onW2T%7m*rd;DE@p%m?Z$Jd{FgHQwr)^cjmM5(^
z-i+=!$~xi(Z*A9#FA53l1>6k~0mDC3vg*aCL@Iv|b8h`ju@p1w?Js^oyY`-e$hk`Z
zj$n1F9Xup|V?g)cTIXpNqngBy(G%U;39hV4t7=|$R~%n~afKw#Wa#p!DpjUKQn9WH
zJwfzX%y=Lxc%iV9>~2VwtbZ;D^1|t@N_Z~7`l-+1H^a(VLqJKmCR0(t8>}CpU1nu#
z7!SqzGE%MQCVkW_uy_Z>jqpeK^LCJzI+l)B!W8#WR>dDxh<JEBFfzIofU<Z=9`W~l
zuA9mJRE{LiX~*=X<RGxdq5k?#?!gb5-bLunJJGP^`uRzvLRjM)n5D@X)?Ktu7+G8V
z01oOvD%WlbQGj@0wgC_X_t^ehlhB^@=Y2ECOajBpT@-+c9xt_scU{^8OFZFDK40G7
zQYvqfG5QvYJI0?nwinXV>J#1)uO=Zanhp~x0TVVOt=0yX{|*Lt%zt!!=TNdUD>PwL
z_BHdeUP*@7->;iY9lM)H{T@H^pv58#Xxf_#mBdzlo-qKf4+HzIzxr<-jjI?MN6z#R
z0(O`d+TxktTEFV1j=dgisG77G4<Y6#b-@0SP;OFCC{_tjMnf`h=TY|dNMgK_B8)`j
zned6q#P;0Q2`e_o^nBLx;#cXo(UxV4q@5>MceO^hqH8|kb`7w}79Rct4v;g{JiZ4p
zY~7eKV%ulaI-!BYjkMXhcW;_xw9D}}`V}0B2GcobW~R3>ObIouz88u78lHS0_S)=a
zzVrFEskX$>Xc|c23-F2pyJfu1M64+xWzfRizzn=bb0)2K>Qd4#`X_6Z=__F@I|N%)
zWQ=#HnR7hcrrr9u4-{+InuFH-DEd=3uc>$ZPWrS&rOV{qKpLhe<4xITg(foGMi`D$
z!&T9?MN@Ep_^PQ8b&$FJ3b2wL84sj%;WLKM5dC7)yLD$^MHlux7_gL*&Su6P>C1cF
z)cm4@Uw#u1xFS#emj;XM+ZA<Sb_E8r)ztx_0C!cD;TcUj-ztGG0JRrLa`lB1>VL4K
zC|sc&FQswkPgzx1Kd+&LrGIo<#Rz!7<oq3IH`usfqmYK*#YJEq*iP{Ta{aJSFw$x>
zoefj)Mm&<=2rgVt-Zgob9k-X9W}O<HFiP*#3N3f}E)I<3nR6{wDgidb7A{(&8v-mv
z3%`aOub{I;_BxpRIY+)vHNT-!cry9qy0LTWQvXDru_3Y%#tFgQ1tq7Je*#kyL&pQs
zktmBbEPy$YZ|**V0bX7ie<6{|n-eNXl=Uyb32xJ|rXXf5v#S*bpAki*i%<(f&YyuJ
z1YjD5OBwG2U+nrcwoYIQG)@*4CW_W!XJwt(GL4}(B3Ht)pkFT}v_n|a%VAy=i0$ly
znyag<o199Sby>7EqBXEUGLe0v`l~DPqu?ZSwU-t?v`4^=#T+*AzV#)awN1#kbkiT!
z<T>Puq*ht`K;LmaF|Vfe>Z4VR%2e6MfYh$?AfRttV*zca*#h?V{>&BtS61d-%c77~
z)kE?eb$j*bT*Y%!^yjlO|2o%|g-CL-&bI|2rk`0|TXi6G5u+;p6v=p&X2*UiwOX@9
z6%WTg9hRVrI|+&BJb=z?$72WS`v?PSSyF<*wHjw(nfR9q@8IUwiqttm2D+ju*%F@w
z0YD1%REHWG|5u$PYtu1B@_~qc_zvn96+h;evs7;InJJqye-_J#r>;;})|nqX75|#1
z3=-HTsK-n!4CyRE_ES1eb{bb|{ffB~9Ha_hQK|8mHh<+|{>mQ~mz`c%xN~8dN*%1x
z)uL{NziJAh*y!e&LSGam2)Ad{AV+J%728Ey4g{1K`bH^eo<K#TxT9+fA4L;~XYI@m
zm(cN$)T;}{azxNUz^z|%BT9iArAg%q?b6L}WnKqne95*UpYvMIXb8;5=&-zBT8)=w
z1#z<sruyI@?ckvL3!-%iU5ld^(r~OgbJIB1{9-A@V4dTYD8h<GSwj{%6MKLQXBUib
z+^OjT`eC|0yWmRNy4y~)yWtxmD6%~(Mr57OrN5xYU6}s<q0KesT8Al<wAID4(36IJ
zl_dNYqc~?lKVJJA>)Oc2kgL+_XogmMzf-&CuFllSHaiR1C`Pot-4iDic7+<X_cp^X
z)!+GKFoUcw$r+^oJ>z<&2+xSn%86g~9t!to;Y$DWEi*9b7vi^#HlWI`x(!q{xz?_o
zX#Ybj<c$vQtU8)!&@8l{`yLHCjtM;Bs;Y$SNaTaFsB@DD#g1rz1E4q!Gp6@v5P>z;
zZJZY~*YrNNna%C`Rdr+}zw1xG=I>k})fo`mB5lojH}JcbZTA%-xx<Yb*S~e>!8fs5
zu!aEmd+K7c0|M39KLKUo*mP`=sj!&l&r$AOFO0zfiyEQvPT}?i)DvWcpr1Ecc(qih
z7*HBkY7xOY%kLjuRb2ov9vOhqjK)Td>BX9xU-ejA#j5a2kka1rN%vJ=j3IZ$^sk#H
z7*@K%ele>sQKSB@a6es3sg@8!&$m@eC~{sy^x^ydK8duU+v%{NCdCLayQrQtWS|Q;
z`_8%1&X?#5J)KsKn90$wO9W8$dwE+a?d`ro=+fPAw&zKiu`y*i#9wL;v|(M{2_?$G
zpcYL`l^@)=g-GML?Kj=p=Vy~7(^AG@+?;y&lj!pw+Srolpcd37CA7erNz|N_?-y*2
z*^o>{CTY+3Z_>WB-V8AJ946G&4dcG~L!y@I2nPyXji4tD4)qd6kfI#YamkPzWotYf
zEPr<lzo0;r&R7gOH1D`sa_S`s0mi7q&4co1Br^&g3wc%!XJHok&8eaCzuCgxP#{<J
z&YP`l8XSvhCcQuJz>$5mKc~FwbxC}mzY0jWZ>EGkqSNxWR>#(b>*8pYxw)S+J;8iZ
ztD~sUj0)DarSXvM3%jeYj`|n}rJjBY@e)ETQLb861#9nZ<@y~?=RG!VmJu7WsMUJg
zw!dW}rrsP?92TlkF4%bx8*1=YL}JPk$%JM1WMH)B6;y}1Nh$bb7)?AJr_M`G7?EC>
zTCOg%Xx$du)fSQ6Om+;qh%FLHYEJ}2mXR}UhsKtkgZbOY&0Lw;?00u(g}Xx8fs4Ie
z8p?~3FNZHc3&s%o7M>_byZhbbVB0?&9;gd75ijUP%=wC@Xx=BP?Bmy7%`7c3tpEH6
z$$#I9QlBylb`|;5=PReV3hd(v+m-t4AspYdl&XRJm%7H%Xg~>Z;ghyqv#}<Ox3}h<
z3n}Xy4F?Nk>*Y_%M73A+Y?IHTV~Jf`gqxdGtwfF-ebT#)$o&seie<B1i88z!O0W9A
zm24XG_MUYjl`RXWWt7V=Kjh2{ruKeU%}hRSq>o9tr#L)yFE8y))r_;y1w{(90oT?7
zjAkHrDlIXG<2cWc8giecdpsFFxXw$fioeXg>Kcg%e8^2G0fA57S-P}I;!IXAHqB!c
z9&Q{RumRfY7HwT|B0w+`@Ok{sw^bkwj8DqE2L|gbi>XMBxv>oWQmJEDvt%ZTBpxix
zJgKQm+>qsE_PkYc0$ug6)}?fIDe2`^`#>bVR0JzafDwzRp(cNeTWjEBG$6VR#qYt<
ziIC0>-i**}o8(d5KN)1z`wbaaJCp0!qzndm*p96(^~6p6X$TwmxbkkSb0wJuQN--X
zI@;naF`A4K%WO5B+7C~*wY;_~%*^-v6(TMssr#l<8Oz_yow&+lmIwK@1?}D=(SlmX
z*iW}p;U<x_w&Nb8M&+#|hpQC2&2|sYLz|ZlR3Mbrvs<;?Tk0ynWe1ld0PI|sej(ky
zH5Y5YV=b>qG2fp7cLZ%LphkAuCdZY?V}EqPN6^|d5NkHlKlyy(FWo(uz;9Xd$_Nsq
ze+UjnrOs8XR@8)}$9Ao3F08__NV-!<3@^fl<pSvKuj(z^U+db`v~<__c(Q-<_wqn8
zk{F;4QUaMhlRhF_%epD8{Me+8Bj-Ulu2(Fq7Sm+_9Z3Z@ry4_!nLdb#8$$@<g}c9$
z31gD#D?onUwx?g7d{Y0{k$wuh;o^q{T>=kfM$RAzC+Qi8b)5q{s_&nyoT$_m$wy42
z@LTW3k+en#`853&{m?FH#2@i7TD`+CKNwN;sd;CUtQlfa`Ik9!OVtk$*B%LLKC>O!
zcO$O;Z;X}DrRMop25;Q9s&ugtXbdnWaED&Ca)v*a#$P_}$=XiVE5onyJbSNUwY$Kz
zZ3Z<mazqt#4NF5Ep_w+s=Y1WcO3Ufu&P_2rSHf&yy3C3WV3if<*}wZ;jFu(xpuEM3
z^q+LC|6KN?&3vaskZ!;7zbKcyn>jR~AT--|q--b|OLQ0En9i;t;VZ`c;0ThJL1OI7
zeN(xub+UnI|4FSYl~KHw>ztn+ff+(v#(<ad+<<v4J+KAjJ`(~=%@n8^#_giAk9p=*
z)H-3&3XOnlefG60ZBR!aVX6XCX`I75BHz30(1A~elGfXz9(=Shh@mVE)#+^u@l?oo
zJGplg@~^#5KX>&A!gYxFI+}@>8gh@7m!C}a=+l;MougL}l6K5f!PAGj?|b7?9mPQA
z=X0Vp4wqk(O)a*Wfsk?he4A(?PJuVy;({k3L)n-nKL&alLLX7FW(wHJ4`-wP0bNgf
zd4~sAVq^S}GSJ0~NDzLt*52gtOYVm7y*KPXg~d^4BmhghnXs63REL0QMhL<QIL*<s
z<0xG<<qMwZ)dK4#cX99pB_eZ<C{ABzAgp}7RQW8qk?B-7jkc_;lPxtdNLieW(pxO-
z$Bz1s<vV%C*nT#-q$P*`aQh)Yt9Y7QFh^~;lmE|@3b%dgb|SbNSP2TK2**sXsOrjz
zpP}!;3)nVn4#E&$tdGe$rof&Z+gCKhL9OBOU&&7xSU!6TmI;rwn<3!nE)4ZSM(naw
z#}@>d$kiRlZ<&(&?U36EYUBON*e`3j(mZYBLb1m{3!)KmnskKNQC#%WiEQ9Uo&%fU
zL|%>Axq|2<K>-5AEC$5}FOvs7>S2`fNU!=i=%z0FNg}JpMRgyX*QbzAx<h(IE!&BJ
z0WSTEn3n*gy@5uAvn0?xPkK|emIk=hC|R@l4sb+3u|Ypd^IwGZUl}NH*5?l`5(u6O
zZv(<_aUPq>^O6P#?{K{}D>wPgIJ;d7)o?Ow?F~NcOVZY-D88f&+IXGKF|IHQK*)AL
zQ-`;^B74XJ=!k5$uLJ+LL7NOBLW4gC^h!=%y{U8h!A|rFvu!3_i9z#qEIO7iNjv*n
z=?aPxAln%eP|m>2K%}V;<P!ZbhQ)lM@eNMBNVeSD3voa3KG1gFO9fk#ws>SQC=`g7
z^%M#OGJn0GdGJAGWAwda3YeE<5FH5oY%y>3O<0DH7B@)cj=ANy-qD1um)0S)W2TFG
z!-M@MN;lG~7<AR=aSSc+81GY5Gm;kdT(D&7^(=`Td5^;6xDQQAyb`66X1~I(%Ruqa
zASKfqi$Pt~&^{LP6Y_0$1{hR&4j~1fqve70zI18X%s5F$*`)@JJKRm}|I6pnHZyv2
zmQw@<-9hEN{G#-Y^_3_=H#nNS*v2R?H6*#~nYMJc))WB*ZNsj`r+rDHdGxh+=^D(5
z%qAWKC>cpJi;ga_#Zm77G<b^m^(Pj^!EC8{yKCVB&ZF886Ao?h`{YylphdVBRgeFZ
z;NpwAhsSj}NM}OiZE79JHAxb!s_?@lonw{>hED(vfaexr50Zx@?8u_IyJL0P6mi4S
zsPdSNYwh%yBHsodVx;2wj1~5IY5r5qo^)vk+8V)DAn?{}!e3w(`dbRG3K7Ze{&r)1
zxk<z#fhH10X$bJMN5))$<-}qjkTuOi`2BqeWd+_}s`<c#BNGB%)0J;lm`BEpnb*q9
zg=?x6zg1IGDngi^LD;p#U_2h1QT6EWu<+^e51}{0zPN&aI{Szo=gNzu64A)T@0FBX
zs)Vr>$Y8goZymw?p#jy@8d?cPn}=<ArE%#7xPGu+R<#=57<7q{cuqsmnULvDn%KA9
zUNR4McIX{Ib%V>jbBaEQu~Lyx%c|4&=~A4S<2BA)AnaC&I)c)JI10g`_+_vyI{_~p
z6|Y$Z8TH{QXGS@^+L#63Rw)e8%KIhJ8HXz5Il4&0eW0IN!a>ZOW^~f0Bn)I`04&k7
z+PZ#KBQ!S)72#W>%hEgf*q(p@bI~C=X1L7OEbb`~h6NQd>!c7tg@><m%X)NIHNvG*
zX=JNT?MO9)ULscsEt(LR9S17o+WG%wFF8djF{~x7JW7W{Wc*8|We&Qs2vnl^LQz=Q
z^#!uwV^xSEL*$4~mDhH<(4fZk+XqXO5-NiMf^{;Kxf?O%EGS7dDl|dTDTCjr?kjx#
z21-SHyAlarY3idLD|iD3X0Y{N9cY*<5SI+4KB9!*4itGAuw8IZCbX4ZTP39RK0hx7
zrzfg-1lro;c1a4^I<=5dBW1vXehd|NTI*ZoB>Pf_@{O_~amIK?x4}ZT*o6Wax8p~%
z;q|mzR4-Vs%ukrWRFlY0Lo10{%pJyorah5Dun!^5py<8Yf6{`nFLqCHsN5upXcYNh
zHH5*}I1Gp)47@kFzP~4~x8F#!sA{qe34Z`o!+AUgPPXy+VQk4msuCExpSYT_9Xh}?
zmf8jpVd7#u0|(k2o#Lf}abp+JVS1)RIv!zYatdDj9Ob<8G%cvOw8uafP}fNDU@^zW
z+G2;)+%^9mXa86%m|2C_j>@&vDe1$?0frL@o^uKAK7h4)n%;P$ZyZp<Y_HMBDQWZ1
zX@q6(m}oP5*@Q_@Kl!xKM}v}o6y-*w@onE9(~gA@9!|v+#E~EuNtl}DB2I)0D{ft*
z3!pirLt;(G4E-Fn;o)0(X-5AAC<xd<XU~r2u(k<jhhn04%OsvzUz{tcL!0X#7EZYG
zVYmEOVkbyolZhE7Ze{^Vu~t>4%j2CsbRE+0N1gC6U`1w>D&8kqa(owb3CVAbTN3Du
zvZ%+TGhnhy-2<I!U)J2tQJ7EpTXI_|TI+=2f*Fx&8Lh|Qz$>w<nb@y{O1BRdv3j?X
zLiFZ@Ru+?Ut~2calq4pLx40Sk`v9%@4GLD+R9?_%T_*<?FLx%71UOs+W+#BQ20t#t
zh#5M^*0bSWf>Ah~GDjDXbU=8#$X~%&jCL9477x9YChJz|L%9u01hi9h)G0j_$Ltvr
zl8|-TbxR`*)o<GSxU*o=_&cpAFwM3x-SHSccxeYo$n|VVyGzW6(d)@VWn;X}YH-(l
z#JBT)5^^C#bj}?7Z90|rie&Iu0Ky}ZY%`C%V@5V=WkLeAgg*K*`MQ#)wlw41k3YS>
zBTSRkA$K-vS4W8Qro?(!4hk{_Us_Lan?M&x21c3?R0mkk-TVhA#OJR87JoVX?YpIB
zc;^=*uGpIaI3PX1v*ULF@InoJ{hllbr2<l;Ln?WctfMrK{74o0k#xFg1b(GRK7k^3
zmY<NrFT4<}UkrkifpIb1IP^|p&^vE5TEyg`azdy<up^(M@T^_5MK!fjo#E*+OW<@U
zqa)!^(A!E==M$N}J$xu9+{CF%o4OR1omxeN4ZY-pH!Axe7|`*-LWvamrhs%bw{Z-D
z*29hraT_A&e+X94u-igEq!r$Tdo$!%I#AF*o@D2e5wi+4W0<3ub58^!@x$3+wIi|@
z-ZDlnB*lrrsXbf#b!TNTumDK-0SC%8^e(DnIlxruI5f9f3eBMdNUO3Ow+c#hS5rx<
z5yDFm1A;A%de4hyFds#XzDl|>JSXAK<$d4zMG4^f%9FB6n3c~tPTWW=owa7wJ9Vw(
z)<sHAA<4SL=w?A`s?_6gM^dY11_<`{%Dl%U@kmik@=Qd<9YNvSm*owxM80|^wkt&-
zlp*k|8P*dYv3n<QEJwmFMUPG)!9@)4k#a`HpUhB;P{;qq^Rd?O1L@r!9Hus>GV~KI
zhRAQOwQOxy5QTv^;a%HfrQLiP(PY>Z4R)w@kUi};w}+rS>7}TJO2W`BExlMKAoRkS
zZ$C%ZGJ`UqC4PL+2q$|a7kjGLXQ={~>O?C7#t6`E(sS!Gj^t-W1Q&nXO$Gzv7{)1}
z;-Ps~R7EmjCA%kqYxziNX%Hu3tDLd#O?I!w@$s>f?zGfnWQkpc<s$tzbMTNRT%{!N
zs=*Gdz5|F=B4>D8>{IrMuFf0&w~vqw<}D88rAWCKcn`3vk@C*oH@F-AvP!aO5Jt<2
zy;vKH)1e(dxyud9N_?T4zJXOFY5cTSi=d#Om{XA;ck}8u7pj@gN;{MG$c2SkmpLV6
zV?BJ`*IUyEc*+d>lx@&=SCW^7bt5{a(ETD@raPoK)tGr@d1Ce~YgggSjD})h67gX>
zqH2LHCofwjB(MGFY3?Id6p2b~0|WwoeAVKC$f+5mMqbC|mF0?sXrZC3Q%t2X1{pkA
z1Ol|d;ei?LOLhYIZ>c3HnK(r3O>@*Tb0`*`=!~Y&sLu7YR-QGL>pmv<gUt4vp`!?T
zXR6orq=_doT{`o>&>I9KJQB#^#TXgrk@$*r{r&2U*cTDcgn^7i{bZbw_2ux@eJPdx
z2H9kYFZ<y%)2?V?lHZ&vf>FW3x~mAicc}^|uj!d+^N>)O(qag0Jo_D&30nu+Htz{p
zLG|Aw)YGrU?8HgsV&gI?BtAXVBa=Vj<Bkz=2rF?#KqX3^XwGfgx+Qbp<~;n?NynE8
zf|>MoO~n%_*rejVQ6@Fesg3I>i)nW1tBtWm6UWafJHZR%*`3X;@8&(Mz^FY;pqYqU
ze=_Wv3^LFFed2ldodWkGjSa_uP_d@|M)a7Fec}?N)!a)n5wmuw4Djp}5Z%v1=C7<~
z1TqBrQgo-L77~Sv=@;;fqAFeG-<lptjjrxbA2G3&vxtkUG(C_(#GPUh@NG~7nO<R`
z)S+^C6r0<(Nb1<vpTA{?!izpxp9!VVCZZCQIW0=QfW3K9h06E5mwNT2Q!`Sib8?fl
z?B;{qRlGohZ_X=syy~Mgz@Z_$P!ycTl-VC~ay~~r)>7N_NN4DK*leD`<m<`igsq<l
zzothM{3l!;T^HsC`4VBcs|;A&WV^s>3MC7&r_@oZ(7?%~c1;Y4f<Ew0S9|b`&x+lE
zug(o~TN7_&t4cUmw(`-b>Gt61`TX#ri`_QaBh6k<f`c>kbIdCs>=61gTI&M(5BCNi
zQ+j@QLI2Q~yI7W4kxig)n25s6Mdi!8u$5YVULbneniZJAZYq>O%i!cO#kX;)j$d&f
z-#2cY5pRS@bFjjjX9V`P9pC-|o%lL)pJ!C^w6UsD>EQNcETysEC?>}FCIaQ*W2${Z
zgm4g2Am>h(xe=LtGCYaBWB2nlso26yqe;R}A{}lc;rTqlVWeo>ALgpF4rPF0J!xnV
zB5i}0_8Po;WN-e9j<&MWRZU!k4#{$E65};(+;-TMyR3Bp)VN7$SASO3H-$hJojFu@
zLXJq49pI;oSooV@3q_Pf)Q%jN(~Jys+s?8%!Jj$$zlRd<BO7R=I#eal{7HtvaSlpe
z@DqgGD@%b2D1T1kA;To|dKq9eij#=s9z4MF_yxQB9>9=sG!HX-0Vva6ZCJf6L^)M^
z%(JYsoH^h1&OVhtGk6*2M~CRLkF$(gTM;tC1#eG2dIU%CgR@21?D~XfKwM^WJm|q&
zD>Wft9tJ~C`9iciurR^~rOgm$7Bklli0_U_YDj+aIzUp+_8*|&wk3e#ljB|QM*u!<
z(&vO;f$T&<lhb5J;dMN-Ef(o{&`v{zB(bcm?n&{Z3#$#Y4#COwb;O4OT}2lWs=s)(
z)dOuiTlWi~3H@c;&9qgn+F|5IE03;a>AyrPw!mJS+N9`etl7v#bO+qgt{)GuUk>fh
zit0+B;Y{M%zyTlIY5FZ-v5LQaDL2?U)HZm-Ck5zZZHsrI5tnJ+k+Z^F5Wl5mtd2x`
zrEWpDIx!VYmz$9xh%)!aOZum9hq~x)z^TtT*3%i6D#Kz_15S%9|HuMncpaO>6Y-Z(
z?*P5hbviq%69}8GAw}D_r!P8kHOuQxctg!?uRC!!y#FTyzm#bOKA_qeV_`s8j+k|{
zsBis*(g#UfdBWZzT%5+Swj`O=f+ZlzivBC|(+n%Q742iYlzPUtMo?+k)C!`jbMRHO
zp9T_}Tapn5XgB`~*?=yMlMFFb)NaSlFGILy%8NfR=DHyGj_^t`F2q^CK|Ssk;Pv{y
z)=N<8IB-ZARddRZeFWV509^_dz7d4Ts;iLn(jXIU)|T8&@Rs_AseNjou^#Hx5b7Ca
zdVT}XAFDK9rglY=&!iImK@f#xSAs0NPD<-@C43@|IW^BycfwO+&yuNHoz&j5TEMfa
z6StJ!+Y#1Gf@mJ=8m%kYdq1lz<W5s*Chbv2EhJ8#H?;8TT*o&{SoiA4v_CKpbdWnQ
zbcIl3JyloDQbx^q%h0VgS8>d7I5QH@`{*d8*^xPWJJ^w)du3HlWs-x02a`Y+k4Xc`
z#b1XwcEfF<;<)@n(L>E--on$u=AEl8awpG72r|P0Y&e^`J@A<}eX|P5U{)_NnW>Ne
zdasp+?@qrQ0fd+!8HfdTmiMIA*VYTz10s>uEdzCl<u{5HXJm6R|8V2Ba>{kzPa*E~
z1ZCO_PjMZbRcyz}P$n`Ki$e_-A(z5xiJC`!UUjcGkv*`PJ94g$rzk;vu!%T6Yzv&(
zHL;B~5!7CY=T<z{8?(7w1xt(t9f4lD)DbP4o3uqsVHGxE5|Pr_PAy=os*V!}Y+wVU
zR}jNgLw6pp*iFQ2EK(RotCs8=(swBV;B44C6jEZczY}%g#v!21xMt!!Owkth3>kYu
z4bl(Re@0PgoqBD&ff+&~FWs|@Q$dcJ{?m)XyS_7V?m89>m##OO$jRS%;Z_tx8T)-X
z7K#@yGYV~SZLG#NeR|0Syy!y~NV<LlFRDYd5pI4p>`9hGujR{wxxMG37CG!moqGwa
z|2QyHLPBM>PP^2>aJ?^{L=BlQ1L^q=p=K4_uDnR~GOapfyR9|^Yu4sgWJ!yrCpc*)
z`s8L&r85roF;{f4J`fK;-{QnH+uJUb!N0uNXS~SR^pHc+|HLa;|9M~5WoH<?KfTZG
z$b;1{z15LaAC!56YOWj0)hVi4gVvy{{O#kF+Zk8+4MP=(2XhlY1Aa+?#OK0`X;3Ve
zk9qjzu;%_DrdP#_L%A66!hkoSj(U*=(<_k-f!KZRe26f<gwAa^mtB0s`kvIS<qj?U
zn7e+4@MFpW4&_C3L@s<8U#KcB@MP``j%9B<zNC_eCNuiy9gYm*bXm9q_M9BalOhJ}
zU$jz+b)A{R1!F+G4c4HWjNdD-lC}uHU;i}phX3Z6Nz27}ehO|e5u*k?w|~VMs2>J~
z*oyNhr>p%6<nmL2b<k%SuEd-?kz?)CsBj<`;7Z<bYSYfZhg7h&87&vjH+&}l^{f=z
z^x%ahi2`zMBR>0;N(F`fAKI95&?qdoGlAs~ic)({Zxx0Ajq<SndYt|BUot<%!|%Ot
zYi$9CSM1_TZM+<;ApYPMM=fTDbVj7cMi3;9VfSuS*k!TbX(=!6;=E~&RuHMq)KqQY
z>nsPIX3EJm_Dr#ZQHtz&)`n%}hn<ht2J?-|kLb#6Dbf_iMh}311gj{z$7yS{KI`5%
z)SvD8tqh*!+yC(fz!WQO29G#CHH8|}-QGpg9C)AYGmU!>D1BKqW&^mh38h_9Lo{@-
zNg7AA=pW^5L9~mI{|vKlYm4lEqdtF_(Ap>3-H?AZ@1)op-;-l<a{YBA4|hvIrlNum
zdA0kxz<nx$m&)~`wPb1<n5d&ij@5UjD-262k!z@PY;%S>j^?<#^Kbuo_&B|RFMs`f
z=w^C!*%C3+Xn!7AO{WC+c{NB%l^05{mQ{oQCB3tV7L7L9ybm{(Ym#fWTev{seguxl
z`FDH93Xh+kDj7ZilTO^&f`fV8U+LZHs2{oaxV33;@re9(O^y`r+|Ws5lOj+_QW%3U
zVzne%Go)m{n)wjOYn|-mr)ZaW7#e*`SD;OB@q|FS<w>TAYSTw2MUq2&9V&!H@uf*9
zT_Y>JU21!#3-+g+QIf+!0YvQQ)sfSu_K3O*|8S=wGO0F4$`_4)Yp3vWWM6W#cZ|Vm
z{&3z-N}#)kr$S$@1s|W=d#HZYTZ7iw0NPX<519^da)jE>&o#~^VOTG-Xh9bPa=N}=
zHzuA{J}w@3F_>)$j|wSBbQ@uhxIc^;-#tQn`}$K2K4y8H114<Hb4|?nR+-gYme%99
zwh&<mOZt&SSG{jM<cwIcS8*JsDfOzIJ!@$ezB)+&d)Uf*qvgfXuP8$+c{8`F(V)ij
zWW@Mk>REk@Iq+G0#O`i1F;DD&q3ODRaEZLz|K2{%dd?3eZ*L_1_#D=jvuQ^z&{mZ=
z>lz7A!h|S|^cKwDu<sj01qQdPrdSw|T;->v`G!@DK34EN^7CbNziK7BxzamJC%cg#
zBX|Kjg&l!Hd#XL%Y7^FLj3C`4X2E)ZdKzFFzNWLyQ-ts3ul8%^*IIx58~w`6B8tvx
zBB%s}P7$_4jQ)jww`d=yL1%Y9UFxCZ=DtZNG64h=(t>@UX-)=OX_G_9Jwb}#KerEU
z_4nyejXV4({D_Pcon4Rw#R|*&$$|RT+PWKtv~nO*V`B-}3#@ELk%E84uJ66R0weD0
z(aHfTaaIkGZx*3d$NhfNvey5RV-W%pG}6RSdcn@yno^;~Izg|EE)M)r|AcUDya0Zn
z=&+gCFZoHE;@2~tK{m9W2VFAXAe=I9c)t6*k1@;2g_!}_h2H<m>3!bVInu<P-1_oL
z{c1Khn%PL#Xv_UI?Rhq)(2tn|D`wBuZ<NaIKO7UXgHNxUbiF`0JAlwsUI^JbTO5P@
zx)aiYAXdO0mQ@@Z`fH+FJo9kepEjpTq!#`7tj{^Hv*#nj*j_)_tY2~?NQ}HBCZ!o2
zqA02^rMD-LA+JaYq74@ade!gYq0i46DW>`f_uLhrg@gX$VV`8KJNYesnxmUhYe6fH
zF+D~d%frl5&VSnnz%vs-^Ua_yC=|eQWvQY5I8;^?BV|XZW}`nu7qUG9x?Q4Zs;8N{
zISM6Z%yqP9XXdpyr4#s@uXy$2;%)HY>BWCf<bh&In76i!9GH9zEV*6fm#&{sh^L<Y
z=QpUGaaW}N0)E^UIK^RtBm-<fNhH545z{T4jvzIpUG$ap1)7AZcVs2+ebI|3z_hrD
z;D<_#v&kSbp+5`SLT=f|K;@CcRY5)`{~77)eXFl){UXOuT;ic7M*g~Ow&DS0_M=B3
zUr2+>J^Lo_&wyLUK8_eGLa2g=^;*&jhtPOg6Bq(-l>q527R2O&eq=TqvbujBYBK{N
zO!|Keyswbb@1ERm0FHYgrU+F+l<NI3fM>EfTV+z^!zf4R*hQL-@x78A)co#yz!Evl
z9X4Q%{dry8(tLeqrZVG@J2Fs+V-v-1KiI+?Kq|CHn)iM@fF4ry3xI2{6wZ?;)KDrt
zZS1d;286S7nsPS%v7C)GD4V&vx(f2c-+1-PEg-M)+{o&~S>XN)5;l-OqWt?b*T~Vk
zgy=C6_rVPj{#TC3aq$2!+iCyfg|eFXjZ#1owriiPMke=cN;-#^jxl&>uADsEX#=ef
n)Fjz@#O|xYnGR2hm^h1I>5A{u(vf1}1M5DM@xC|Oo~trt0^woa

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..24c31446cb1d7c37357b43dcc074d9670acb167e
GIT binary patch
literal 22776
zcmV(hK={9l6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjz2xSYmn@<OyYmyiQJ>u8iB$V7)
zuIFdrueM&ckxg+<?C43|b3{G_)6sx4Zj~`~yF@`)v*>i=3fdsGVTUTy>%*gWkc?ll
zC(B+FzI<8>DFRtqs)Zy*$QSKFGRRxmVmB@AZ%p*BZVYk(?y>!BGopy9FcNgd^GA}%
zUJIwVRMf(6v!uh-k=~vBzG<1pyeeOIcRQa@7S@7^zcQ-Mefs3ymUR<^xTgQ!!w$f_
zdPgF_rrGs(Ax;hom!0`K?@SkcI=Zmi8thY{yf)R#@@tW_&?}jlM%BHL3X{V%$mLCV
z5ZB`(0PO^Vh?FM;7LRu`3yJdcKy)m|UX^g_CA<rKT@-vNKVKsU{+j-^5+U@uxasxN
zs@U-Y!gb(0sRE~^{rr+<%m*rP^F4Ed?Bsj6dF^noh+jw(rruwhh<t<Zny-nIB=jsa
zjrTBx-;U#G<YViEy;n~X!2HM-N(GoHln^e{ih%oYHI@Jj@A&m<RC>6x^^l5bgd~r2
z)37pugc1zG^|QT7v$6tmujceM#8@*vbBTiUCj2?V$lQHlq)M|}fAuW$BLR=Gkp9`(
zyQ6XchK5VtTk@rDO1l{^+!DBonbyI@;`R;5xVX@7Y)Vf1&(Iu2V78H2-ngRjr({nH
z8zVEMH6uHF87KB}l|oOSCD?vK2=N~OH1$ewPBW9c|IXpzIcs{AagJZD1w3LoHg|TS
zYpl8si+YIf;bs!YF2{t2uhdlW(~9gGRfz41D1<^f&~|3}?~RwtPgtRox92Y(XOj&a
zTil)nW^Dva-LSu1I;bv3{d0tXiOA?OU!o%#UR`HTA;|JpI6McRVpP$AzUaBww*meN
z*d%%OL|hVe{;BxjSuO^H>jMoGkgZxmWHX07O@>vcCLm=?_Y-@(S`GADRE$vM-OJ(t
ziQ}dMnZl{X*#@RBkH*k_U4A=1^w2zlJN{knXaP-J!6*c0F7z(Ar`TyKNV=X|JExh)
z?NrxauP8^aZ%JjnA6Z1)1HM-(mf<Bz+nWjs<m$xGM;Mq6<tpHxUu8hA*x5%|BOX{u
zu{b@zJEIYC8lSals1)bllQ>J)$6$_oPiJgd#R+2cq)tvqjcE)l<eJrUayc<JY4;wr
zcS6jJPGB(8oB^cT4V9!Ee}%@g|Ijh$H(Sag(?@MNM;&{y4JVfKPI>$CwD9r+VKtxO
z<sGtdy&)S>aGxYG2G4Zp@W`Jmnna1DykKdST%K<YG+lIe=c}L~5wCx|a#fBK`?&xw
z$|e3BnfEUz%$<?AOO^P`?TgB|<Wp1_w_%$1+vwwZdb8Cp@HOw4s;wu@$ny8d&-mG%
zOvdRzuOs-2IpdUZdM`&gWmriIMJ0gV*FCHu`n^i7r&z5>I*;e5Q%0??K-5ESz4yOo
zN`)uv+o+kHQFX?4xLfc*cDX+x)7?g<f6Rh}z%PHMBvL!vq6Bch#O@%NlM92%sUdqH
zFTXLjte`{9%a;Siy<z{rloA=66*8?g<-y!p=8Q0$<zED?QKvZ`!?Qt~cxWXXk>XqO
zg`|Sbh{tCOI50NatU%te)tTsIuX$-cryFXa>qjUY2@Oj&8G(74LrTrVa|0>R-Aw|=
ze-%}YAT<HhR^UePuH0C#ZN1Adi}#uCLR2d$c~lxYYKUeOAo9?5>1OaROcmN&NC|M?
zf^}QyH%r4aU6xdcT!gugC!<fJCOs1N*v2m}xVfNAD}vESw8#!CMbZK%uU{;y!7Kbu
zZ0^Q$^sSkj;NE%32`gVjWWp<G8MWOKZe7(){WpB!q{wQ)q~-eOP=D~R8!XN!%7)Je
zy`Lj(FG^uZ5EB>*pC$M(8-_F<I8U2Y`;Sra>^gzax$r_oLosz%Updue$Xf7W@A0pn
z+(j|5bq{R(*>TCGXcU1vQbOuD#ZMBdR4v?fE;GL7S5&yJKZOsB%j#E?ss^ThL1KU5
zK*fC<0(5qfPXH7ZD`A)JX>ZzyHTIyY=0`Mzm8F#-I$#ZooTP}L#W68B(NMcG(UG~%
zL?GJvF8C%1mirrWrwwhI1|zJSWCRbxBSu+tj%4iU(PDl{u1#$N#>*m8raEgR6%f5q
zm{JAplqgWSTmwW+N{HON`Dzsbc-jyl8TEx8y(8ECSNo^3ruC)qn`^(-Fk-7u(xq?W
zTZ#t(t;xTTZl_QS4YmKv6Ptma8wy*^H*T?eemQ#Rx6&`sEB^pi;|q&M`zOn3#oStm
z(Y7mSJ0<04rT~jDpd2QS(2<WPN;tP37q+ME8%SI@V`HS843Oc1{ew(YWR3Y}HJo18
z(^sJ*t}W=?Nck(oP2YKIai0@a8)zLJa_TSgCB)aD9pW@6dc>`0kw6B>xBR?j473th
z0PnQ{L(h1|Y@-X#*H9Q`(>K83x7+zpL-cs^^ZCee^)nMw@lxe%6k9C>A?(D0{(o&1
zEKgKZ-LQxY<>U|mO9-t68U*fi!3uMK#q{vx_X46n9;jpfet^tsb{iR|ky{~f6e!ZX
zKvw_!n%Z|l>ytH0qU;389;$T(0xr7dscn9+?ou+uR2u30EGpquO`q(@a*QK5V7g$`
ze_MdS;!`a*%}w58NmRY_rXSEA`{GbSc2aeUbec&2#Ys+K;`=1GHCD}I=jRya&hWC#
zwLcV)|BP;JO{h>g80w~dmhfaFZqA^m#II+#z-_{?fB8c!w3)8sNz#r7`oy~+J<W7O
zC**R%2|~Ewht5mn!I(b$a?b3hj%(GTaqssD6lqn_L`Cpq62+aGzq&wqr%NzY;<i8X
z<H9xox1##)xjDXMe0a^q6t_Y^(vPrnAs}~3ED{jNr_!NGIp5RyaWLu#FPilybcHmN
z>5QYUWH(>MdFn2`&ryW$a6jMQv$eENp%1D%OHG|z+&79Gqmyq=NUze1Aqj95Z*!g8
z@(G9eQ<?fzxK_79p=yXn(=;(v5@Dg4AK6{#qA^jtm;L491GUg<Gxv~0py0W@0m0S;
z5!3pbc`$o5$FeK#-4z=hBEmYnp(`dj+i<ZNOBy9<3!Sq4H?HoWYHN{ak5vPDlUser
zVIDgJ?&XloaQmWF<abP=;xPcNpZ5&%mRs)zN;rSuJ3+b>aC~@pYn3_VV|!K`Aci4A
z$X#O!D(t-=tslj&=0mku6P{)v$2ALrfCGD`kr~$D5+Df(;MBo1^cLXF`Ni9v1P^35
z0<kN_Da;vLGxSy>qJQ+rx=sy{z;B{WZmQflFL+e4*0}?kEuxE(!$ln`rVM3l&gN~e
zsv=-c0nib1leBic{w|)VS@vHXtM=K=#T2Xqwjr9|)pxm0Ad^sW1Wbva4X8lYtwPEo
z4aJm3<w%4vYhDeH?phiM+zBJ_O+Uyzky>_>Cp%UHcCnoHfmZ8VN>7m9u_Et%qQQz)
zBw>_8KbbXpbQ@o1d*}JjaB3gwf$7}aTX*?$;Rpj6Ks$F)UhE2?Rc#gaOiO$-0j6+P
z+fx7gkmY}nR*VF|C1XWa{LI>x5QL;Q@UXyjQR;Klh%01`U^ophrHsd11sQEq?O$`=
zvgFBRK6wT(JnKTgQ{^7~n<!Z9#bvSz9rj+T($~(<U^^HtL7zs99d%HqOhXPAFsyk#
z<KbY?Cw-5`?UPs7$K1pZNJ`BXS4^Cch!tCI2cro~2|`zF;7b&ln#n|S0)W39^dDbJ
z9l<(E&#6q(VxG@%)QL#Eit}Za@1D(PL5HzK6>{5J#2S7t(NgX8=T0Y7hW?e>^~V7l
zgh~2we$P=HNk^wKGWAu>Ex5=lf4~)TGQ3PG{>#I81Z@9_TVK%i-u}!{3a5SXMNiK%
z0e2!=lek}_)3I_83x$2IzZ2e=Rq$V^_9V20tz0nn&^>t41yE^12gIC_+B=c5p-m?R
zW0Ifv#AiRdUlKn63ugFvezmqZzjtGhZHNr|(g%D)2575!dL-6?J*im=8c!neDbnq7
z%&*c5qCHLt*ANBKTx&lJEfE+U=o46R5n9LYE3YNfce-iLA=;k-u9TM8<<7*F=Dm01
zQ{w*Nm`(`D5cB^F*>TQpryK`+W7Y0AQ?e?%1Z((e0B!~fD5G7camHk8g!;0<Dth;e
zR2D>;FnlOP3CBmA*Z&35m57%XG)x)i@`p<;Vglj}gp`%9A_LDV6AfBAO!K?5&EbGe
z21cDQVzF6ta-ywWn{0NNJsiHnokLkMKLnYPQvdK*hnrR}N3tz|a(&(lr`2(HITKnw
z4W6tEVaN>AFA4*J&K*j69X{(1K*p8Q(kRg(<aG0J#*x3y;ZM$|*=AZJ&a7=FC4mUs
zzOb3ESQqH-;ISMbyEg)A3k}9O5gbp+wCl?@@R})mb}e!tviwwkyn7(Z5T+!N@<s==
z+e|J~B(Yp9x~3sOhP_=C(Y-6?D9|^L(Z8T(8RZA=9>2D(E}F5WAEvY}M^FY;_`<HL
zRCLG0ze14m@*TD>_eoDqaZFI;yPP_%q*54llHF@__C0>^Qm*b>EiHV&?cw>K!>3|2
z0BX$j3-0JK){Dd!>M@Od*ll!B*D~*v4u@8h4749ih$K7Rj28L!?Jaqu25shn_Cv83
z>Feu!nCuVLt8S<BpAPAdM3>I37f=qyf()^^w96IPkF3e-)qrWfc{K}QUrUniX}RJg
znuNUK>3$9ZU)yi*m{f;WfexM4Ev7g!-Mw<KxW*1Yqd_0j7R8)J0<I5w0DG$*+$*^%
zbPwb&*lmCJvwPy+nK!9w8>*#db?|V@qVft?ImC{5fK}20;!=L44hjc87m6W11k`M4
zPMmrrj=aIo`(RyZ6~8zzM5!B3LC2%BkLCx7$7C|1UBV8bCMIWRlqeX&FkCvpILbb%
zR?DSm1HKNhxHU8oOZqMPEx#q6vcSj~<BJc-4RthU0(y$~jLiSK;~j~p-s`Irvg>RG
z<pT{2G%S35W_({N;fIW~3$?%P`RdCeppv>#f7r^AacqG?71w@&)rDR~2c`3;$f78y
z(KjjmDU<^?pF&<2DTrNzl#rQ~m^DW4NE%!k)6@>vPibJDPPz`VQZo8hbWbEywo2O<
z*~H4j=G+$N()IhbQN(BYbC(be`vGp*LjMWv?^)<Fy0+)cjkd1nDzD2#$GMdxfKJqu
zsj-u0@0wd(lhDsY#5=?21;1E}VocCCjRNFvj?lJ(2D9{ExUV&_qx`1<u+%)TOoN8t
zOQQu8$m}$JjwKr}Y2;-AS`U5ImWPD=jx|XJ>Fu!R@ehtl24Xxq#Xp#0)dEEpwKNKL
zNBAVE->icNC}n<t_*6RE!fZ<w`SB*rLNNI7-+pm`tdO}`V1hTP27(j^qc8r&=^JH2
zMmg83(|n(Y*Kpmp_cH<-!Ux!Ey1E%`;x8}Nu(71|tn!^xeap*K<8}oB@WKIeS(NkJ
zgFP<It>yv6V+2mbEEGQf;FG2j`n+4}$sKUdJD0e!XYAEWgmwsn_dk|2TiW0C_+9|;
zz)Dgw|D@5jLtoZ;2!#6$e38k|ytB=-xT`ZHqt<v4)BeF&fiPdEUohLty<%u8Ml)(f
zu^!Y}yXHWYHS(U(KdAg+Q3hF}^9{I3LXPc?E!3aSMQVugi=$>E=%~&d!)ev-B1BYU
z1qkaAdJBijV@Cy;dj3lnYQvf9$buU5!YMm|e+yI^ih7d9t|Jyxg{~ZwYE2s$@O%x`
z#`7q_y-|baowulDjM_VWxB(Yge`LwymGzOVGP6Mx2&GYMGg%W<co?c>Fy0v-kW9EB
zyT0-uP3lLZ4(?1fVaRu8QkyQ@M}TZwM&(Lj8PtnKQkm7E(MQsNEMY3q#K6CDcj)&a
z@vI6NW~PCUtM*?#fT@Ss#jiFQiuN4ryA08&`HcOl7<<ZJ#w<bY0yOm?sJd3rS!>nd
zXu-&BB?7|nc!7iX&w4}FT}`t*{+|iCYNv6_u8MPU`%*=Tl45jLj_*mIdmwbyoqB90
zZP%fWRB3AnP4D9}64>Q@|6LF72nN+j&LUf0@~#CjYPm(H7umqGGN(pGdnDoNUi0O^
zTAGrzPI8NP%H2To`dF-*e6}xS^l3oHrLTPhqk|haZMz*l6Rcpe1tW?COJ0mq#P5rS
zS&8LYf9SV@|4Ta?3Dnisgl>W9FOy$lGIm_-r@G58+-g)&_J^dM`b;-D`wNX_q&hJH
zU-oWG+*1U!U40M-=KdpUFE%`XlOEXmTq-q=xPrLB+DoBMDM`ag9<j4GMzW0GNFgZ$
zF!LB<tt%w}lMu=V4}Ps79HRyOqFnwD8Y9`y9q%=45?#`N1MW4k#Qp~`_^lBvUg5if
zHe>$Gx5oI=__!JkWRnFx<hjvA;1FuJiVLKkG)jvneQ!_pMSy6L-qR){$|ZzlpYJ_~
z{R%dU9Az|AxyxS2z6WfscVYvNSzW|fmRsn!_SWb0JR?5zTAbG#)e}syYv&uw%6G9X
z#@5s3l~^Xr(gcvk+rC{1Pqq5m$>HvhEfp$QG`fyHxi|^<he4*2qtuKj5JK*S8QBUW
zZoFts6~&6g5?5zuF~)TIk#hj?jQBEBZfF<>emgPdpS+RwWY=5+kvP796MpkbN%xLN
ziyQ>~KGF$E<&tWMhvS|mvQH#fMUuOL6M~9zVkzb>2c&WpxD>%#Rkm~f06?jdw?J}k
zzQo(sz>E(#kcvZNF=4)NQdsB5;fuz+f{BRoMQL7cmiygVqj$jm|2u}}@+d4FzWi1z
zMGG_uAOWfyv8ot`!`v0ZU=w!&AZnF-yJV<p@1&ly5U<|EYy3;HW|aC?lu@y_;Mg#;
zDw3uV4>40uk7YqQhpgpaH>PxIrFf|mm3Z1Q#^;bu*$n9a9)HU8lYXE$EwI<%45PVA
z<cqO?S*^Xf`FNG*tWBs)3h)&q;vk{$RDDXE{9?vhXd-!wrYhLR6|y@S))I$*VkFTQ
zQr<^9BQX3R#JGeNJ<DAMxgo-X(Zq$4VQ%TaJ?t@fH;5Xm@VylFRf<XYFgv1(SPxc&
zi1JluP~eVoE!9@(!-b=q^@8^io$461yFlmnW}slrj14>)AkK>if8)&MHO!vq1oy8&
z@{+<ruEZu}awE1CdgBxa()~<${S60NvZ|^<CtP<Wzlj60#3f(wimkFAoFr9GjpTw?
zLSxJZgmB{=1^5(-z8=+Chl){>Q*nxqY1PNLWn0DV$tKGfLH1LaEGP&F>U!(ML$58Y
z(5G_#izn5Uqnm*w0jrOuh{;HVQTwAG+@?C6zyzUMkks~DcI@Mv<vR?(j4+~L4+2XY
zBQb78xn#*uoA#T+t*y5@vVRh?n$-4uc^8WQN8%%0kfS-7@S;!*Si+SVtuOB!;(=ct
zn-$Zxkua<e3%~$Ys|JyWryDJF@oy5XoZlwjem!=&H{jb_?nt~A$3qRtH%GN9v2RJ<
zTIrRt<S#F8wGjD@me;RiylayR8PD@0j^+PWoJ|kSK03`k0ds8CiHX0Q*2;7!xQgCz
z=|aY_P()!=Y__38FmB|9_#UYZ90r_t!=c{nVt?I?e_&u5NzbT_*L2)195#Z^p~D&Q
zo*1{vh(h-3OUv;G8pF;g$N-ilx?!R_mF`M<AFQMBCD{TJvU>kiTHB$_^-%2hVq%8M
zg$x*s5@?l~Yb1OW*#*LAM`pV*lIKqPHaOz92hcM!M8A)HGer7>_mznmd3)$TaV?#M
z7KBV;iXMaGs>8RxC}eCkd7cVa6=c}EF8tGpOMO5BNqr53<;7%Hf=zk!3Rg~q{^if&
zVj_T+-T0wx05)zh$QhP>^bafw)bMm+-+|eQ#d0dfTln~=oblN_Iv8Mf0flrZhHl7`
zyC0ZVVWPpJVE+oAOox>4R#USW5Z#h|-__|Z>-ta-Jgz|Io%grAj9Tgrnz~e!`q>f{
z32MKFr=kiB)kzkaPIE!6?%i5!$iXJT+;}ZW@zaVSlSxVsw-(S3XBaY-?GKC7bMG-=
zDoCiw3EM`<VDsrffS=ikHm3v%H}xEVt6A-%-e}(Pt^TdBsJ6{(8fe{H<TnJ{S|)?V
z23IP2#YY88Ei9@>bh>EUDHVN()*svyui+AG!CuEMN-&qVBI-X%flOB&|40p@y%Qr0
zutU?VEk&wb-|+5ZPd3EY^91{%5?eE>zKEa5ir~PcGry-%3H(pH?;@LyGJqx~xe0BS
zG-!1=;8y@AHAr+^-?>>iyoP#rELb&+WN|$a5r_hh1$d*UYi0guV$!(<WR%ikWEw!5
z9_m;O;~s?4TL|bijqma6kp;kBz;=(%@;XjC&dsR<=U+eD?zj&fi5E(haJ|1Ng5HQI
zQO@bP(z4#6xRiwV+y@$-#hm5|Lt_bEbUy@8d?N)iA8%hPdJ4;sdM>{OVyR+l$6+D2
z^qTi(L!WzeNTD99)TfDV9MLCjdK66rdKBg~j64<Qvk%yU&%<2y*#o22L*oFcU7L~K
zw0vQHaWXIE4J1rGFtD(5qULiY1OS1e7wKLQ<kSerqV(sKR#Juba^FGIlba>>^L5-X
zbgxOL_=183`hC~hQizgBTL4`IFMe-_xr6B{_<#A8fRUeu^_&XX)z`fu_U~R4QW|Vl
z*P)+rvB7*9mGANi$zx`SK)A9d3$q~>EUan6um!Z{1~tD%772c>9t1&<&gF{2SFJb{
zQk6=ow?p?zxP8$hti*Ltp;<X;@|AwztBsZz$msa;UV6v7)VJy$(WG~JREJEHVC#z>
zD|bJwB-Z;?1lQHiClT7<3nCE~mG{TzaM~{nuITm@QkUuFib}!4E&TO<My|v1Po@)w
ziMm56N2CTc*!ao@Y9T}qxuT26-D{=_;QZ#q(>9?McA74(DhWXPEu~|qAv2@Gh=L0Y
z`!I%%Ews6Hw{6ggkd5I1IE6Vm@gJ3|`-LW&p+-5)-eJ(XCcDAZ(U|sCw@4$^>4Q;&
zb~monEkFaH-szO5;8lFvX1Tv%edTh6Ae>wfW`o?{igMCyzi2A4i1{V0)}1$@6OlDt
zuP39}3R0#$tdPMhFD!@hHR}RE4WltyZrBfT1MeXb0yI<fDO*|~KGTe7U-bkL-y1jX
z)0=s6`{6+qTLp+kvE}_17(G)Q$<{qJb~mc_6cG0yqZoYd#SEr?13^SS06r<354cWc
z%3ho@Ze+z<o|<s}I{91n739`N)qyJ?48W^Iy8O|I|3B6d!RC*pe>19r&^RO2TTP4I
zoq}B2Z%-8=V8)p8HX~1@5mz*_HOoelu|lz*+WUl~jrlz*Q(UXYn@}*=aI1#o;ALMp
zLzhI5CNh^|>&hxYH=o?8a;txr)W_Iy%3u@K?Rj>JEreN+zF{ur^&1wv`O5T0&WU*6
zI3Ph&M(HrY?S#m;euuaS+6ILP9aJz4C9vCXJPnIHZL+3q$Aat&&tdD@Y%9qneQFq`
zJ@g4#Tdj1Q%vs-zkG}i~^YeoB*PG({RL+J&Cy5~32r1^yPv1dkqMQ%>f6~19UL;S+
z3L$3%vQ3CNk8@ZkNA+9RxGG;p66GulG$DN+F>V;qWuRYTU}5?zHpDyK7;+yc3xV7?
z0}f<PO=a$)G<8a?q<~(mS%;Grrkn-vIWm=DqeKDR$5@6YgA6P+DZhRt%u=7U#Xp8R
znEGSs2#RBqA=CWESh=x${bZDV1g>%RkszOILHT}50qY?#0S(I4QyPp2Lr=R~6m(}6
z2&HzhVZcXVvY&OZQgs)6t5QIq(})r&pG`Rk5Z{6iMi+1PLc3q(=;wa-_E#^IH8c({
zYd|M7CY=*~tz1d^l$!02DMv$?Hv$SNa$YRpGHq+~*pW6VRX=DFOYLwCo$9$oSl|k3
z{1!f4wlNgF;dm@S*_bbI-irNI?f&a(;mJ6B-=|`jFnK~gVmC5}eli2Q`ASYzIbf44
z-xs}EFs?V)vd5?--o=yFUu10Rb~fi0B>pnKaZ@3->bbYy$pai$tx=G^;F0b91YeI{
zN#Gjpg6WS4+u2p4w}P%qVjnpfdpZ#C;uIjqL%qIro|-x;d3>3;NuUJ#<0`Kkc7a5&
z&=@Y%IQvEL2i>`BBG-aetb^it!&eH_V$JQqUoARzAZmsh6wEa1Zg4|1x6O~Q(vE0r
z^`FhXbt_F@{URoU^wMe|VoP^dBgX#NmA89nCVm)5h1}N#kEZqxmE0BG68K=&*L%d~
z3vcJF3#=h9RUa)Dj;=f7@~otSU4aW;qi`}q&II_XjfKs#!PX+yT<7M&PHpatk|5fk
z9Edv3Tde+Go0>9LO+w)x@11Vt^FCP}^r${A1&<3==jjwNui*Bu8MdVUbi}wN{9B)z
zwe01@gkT18SgD~og891vOilN(P)r;)4jTK(Aw1yD<b?&95xi2NEw)UFCi{rP!%42_
z?k<x37mL%R5?`EV$anf9SoQ1>%F6Sg9s~MZl#$iP6FcjC1~D_Kab<k#C6)$V5LBM8
zls)frx;!I)xC#;z)41p4s8gfn_n57$sO`=HLsGlpEkEMh;xsxSt%N?lD3pz=9AB{~
zo>8q5KC^e)BVjdNz&pMl<8rs1?GKU1)=J%k5FTd4v%pe?*KAZ{=Gx}1-V9Ko5&=Y~
zeGLqhtrrBjo@A7i_fuH!mnX?a<39YSEmG1|)^0ll=YjrT02S4m9kO|51TZ150m~x2
zEN71M8>vsY_l)oY^NSXfl&d0-ryg1C+x^BOmMiNBbx4>MHEXC;3r6uAW)@Ts&G{^$
zSXw*Q+8^yz!f~mNaj8HYg2bvGazw>zPuLVmD;=QDJu@658kXHilhageG#5ovOmMQP
zRtBGSGJI;`LCau}Y@(ON-FQ5khr|#pnYm@#E(O-RvOhQ+#|`xp$D1($F6}2&UfCzL
z79S@r1~Q9XgJ&?bdf;)V^nE+(4`*-H-y2UqP4&ZqDhYQQF?hi51PmgVu4}xl_<Q=A
zAt-3fYcuugQve$Ty<i_dgwV-G(Br;fHcF5MPZ~M0^><dv6HtX&!<3DrU@YAXWMF!_
zfv+VdMXX{7sl)Igw{O2op|gGHgX)@C6R-;{>4wr+%{96JKMH-;24(!Qlj&UB>@<`s
ziYSq6i*uM#VwI@=cKe^$7t95Kcl_2ij`lIfIMdRRk{+Rjf2}?TL@hapU2r6$D|Zq`
z3CAwc^uC(5q^VKuuFQW-wQB?EHfWA7uYoD<;mNryaZuSxG|j6UNA&9E+(RQf?TfW~
zju{wTAyaxc=EwmntQx!IlAzs%a|$U~78Ynx0y<l3h>MHp*BL$F3#X-Xy~<%e43@Ed
z{MDuXClxQ5K3W$uYV=Bs;LTQ5pzF9+Us?v^=<oB2lFoux6Sb%GQkH^Qigvk11Ri{*
z$!-AO3nilZ9etfIr2gx>REMmVU@J8PnET}VwyG(?xw*ko?YD^`z}_m`Of7P`EgdRQ
zB8k#z2`X>a6WugR(iWII><e1gazqCD?~(lA+Dr@U;>PPLlbZ*-PH<cs=rN($hex>1
z6W!CxF6}aFBqP8zqc&%?lti6xR0DR_y1t1}xTO6+q<q>$())y89npiRl_z^(586%~
zWBYz9nMIsoGVqW=x1;O&fo4T^^z+7T^jl*5BJ!dryrDP+N*`s&$EygBBSC<a_~E}2
zKeesaVY)8(q3@2N=E1k!(CYGcpJL)=QAapnGVFm5X?~KkG$^Q%?mfM~6_k7YN8x9j
zYj#wuiV;|{4(3Dv3Y|NpXYTO=IB1gm5<Q7(=ZuzVChUx_`JI*|LxUmJBAKCzuwf5F
zZ8<DKR}q`WKv8B}Nqtx$+xB_HRbFwVs7y)JdJoE~*<$g`8uaB=HWOjOE1OybQzoti
z*dsF##Zz=?&-(T0D6MREPQA~E9BtNPx;!>03^12@*DmDuqQDnnr$p-DKTU07x~F!E
zkC&FfUBrl%Zhe_ZKH#`|b01cwF4(HA7Wa%R?+NYom?Kreizbc;DpfqX@slr1Jx4o5
zT*8F&I1n{(j3#6IBP=N3*J5_zpKB)Z{AmdmnDKo0;S=Se!xI=rmr`rat^TX~6l5C|
z{-AhEI~lVJ<h_El7TV1R+zDP^%gTf6;%#|5<TuXNjY{^>^e%%-S(WYEkzp;w*UH|9
zlxBqmbqL)e!FGgif3`M4y9JL?(dj1cCH(HIwj{A=TJUUPp%}cq$|kh_`I=wBmA|Mi
z-8?h+pjp9@kIj?Ea^RwDpIjSAR+MZ%mUHe&NLk_rKXGt_YgNVmSXg@afh6zXL9Qf|
zYYZq-dcPf~ALC=4V!bDwJ}5Acgf*r44q?tpYc;O1#LQ;*LD1$u@#3V3E*s^Q$tDqJ
zUBDeiQEs!u^j2in^)umV9eikh<d>!xUM6k9HS(=o&6Q@=e5+(wGy-XIpgMPbBlFl>
zb>`wluUs_oCUjrJ$trwe2^AxI{=$if_lvtM2r<++C5iHiejMYVzBe*^BJuZ!E-01s
z27S2!IKaNmx?(mLXSHX5WPyBjc@Jq#v!3_=B;JsL=9Pgfp2dxjzeFPnb&GJi_Q%dN
zy9H5<oL>t<Dcd<hwJ#Bw>#)S5sr5*IOY0GIUFHzTIhC?U27}tNB1!tQHUem#2$qr4
z0O_KhD=H9bZ}55n&~g|IY!$PhV(Fx0sX%Fe;F5xPO2qh<&O?801Tl&FH7OM`d})Ee
zi3l#wfVNV@3qeB>ZTpVhM_?a`-zqbK-UwJe^AKr84sCC2E}V{~#9b#$S)h$`JGUNL
zr>FQu;F}VI77Z=AvK!aS^x#vMt0`|rVmqF>XwTZC+Qa7JY-oC>O}Us#<gEEG_Gn;4
zV6q}!*Nb)D)*r!fmIoa~g6i#<y|!2)^J8G0em}9!+~NdrV*<_i<A?|+W!x_(1T`Z2
z3cMZ`Dz!Wr#0;Ogy8zy5l7Wfj;T*oD3HZezj&gTLnpY8Hm;-LX)b?zefoG3>!&5Q_
z3ZQfoX}X{T%xlBrNnPtw=LM~bynuO(+xS@q%QOY=iU_-GK?R6!R(y2?`|k@+o7yHA
z$|DX&9%@)N*3RyW_~>lq1|t<jD@>}urbvb_eVfIJZHf<<Sbi27pcC<G+;EuNgoM5J
z=$tX1&2^jL$9Xufy!mswaU@LH&QiU?X;9p-Byj{D=lfujPcf)R!8K7tbC1#vUDPDD
zR`*wq_o?|!kx^?@a*0D)zuAclm%5&B2U%xNz_iiI4R3La^md#;e<1y5F25|zG*M8T
zdj;gTGhgw1kyzkO@*w|gS_d}G3^@Kd;8|b)LStJO6t{bwbY7^?U-;~vuDEB`uRgF4
zm^cc%tSbPprPiI|<JaruYFSse@>ckOa<5Thg4&}l+m8DQdj!zF*F{Yrp>yrE*Qr06
z^oQxqJM5x7Epsl2o~JxqtgX>%ziC`PE>Y3t4BPeJ7P#MaN2q|AfZ+Yyb^d)nUY7ca
zhL%&6>T>R0KL*SRcVAE!zB}A9sl*qCt-%oJ2PF?_?o5l%;tvCkpTJ+Q&E}2f#`F5(
zq$0^UN+g_FAp0lA1V8<BbBxH7s|Wr0i)pe8YJG>mo@PyuZI`~szhnE5OsMPk5q80X
zPG*f=Hqk$RF9edj-=(zS(;kD?M5Snb8w$h_x=l5a%4MYMZ|jD^hZNScaAy+Qjvbw`
zwnv83iI7gjtjr&H)&1%E7SKK-Zr$AUeAtPGaEE5oSEC|Q1+Oy7BQrp=t_wHHWW?&P
zNGIPF-tcVUt`FR!9}b;aw>{l<Sx*1~&KX55{1^FR(>@QV?`0+alE;V>8^!;N5hKo)
zc1=rX7QwU-l^pAoSRDrc=!%`*LbahwW0`S+S94Ll`zK6~cV(U-@VXZa6=bmzsU$Cg
zU_WMw02d`_SWf90{&4Pv>_}+!RA~AkEo18LEKIK)$RaLMyd9}*qsFHw1H^8XBS1N}
zL19u2m_JEhouPjPUBr>!t9&6d=}8@cN_*Z!_TrwwJe|5=04ANnf-4Rom&%j<O%bP1
zH0amojp!{pbHyO831=CJSE{vDwo^}Ts%-9?2J`R+S<Mx+beE7=kLe&4R#N^hJw_%B
z0>Ag7+2DPn60m`TIEzU@BrKs8Jie#RwNQmQicJ%^qyL7kl|MflpmTX>g(UxS7C%tG
zjkn;d-|*kz0dBo0)LlhEXumRGAb|MPmK_Sl6)US<1tKHk2*{7osUjO!{0KG~2s5+)
z4%kswXgOqCsT<WsHJwah3Qy~*?@&Em0D~~XBK8X#QYO`mySU*M?;gAAQKe5z+5^!u
zy`f8LHvX}o91BQaJ@m0Y%xG-Yz|x0%{@6I0f`(hi<pT9zSdloT7vRj2Po1;Z6Ikun
zr|ENQjc1bSH2Se-+izxmR$UMR8UVa_Jh<e>-_E{jpUQOoMNG*z=+ZL(;CnSk?HWNP
zaNRC~qStHyQlI$BG;JAV)rVayRbV~X*?ll~Z0!ydB6SI4@m5c6E<}Z@;AK4H^NNop
z$qrdDdU2|Xg7bssbPek3|L6MFVCmN%{eB6AEzOY%*2p}H7^ILN%`naRx6M3=!1ueV
zuS$^Zgi6&z^goP&q+u2~SwXc7YPCNgNCt^HKhwuAr*B-KUCIAGJaih>G3g6<i#|B0
zS%soeIo8u!eOcdl0u1UE*1pFom{S`(W=>djL$3_~EPTNZYE<{?h&x`0wkQDbGH=U}
z5gPc&|M`V-0R1dZ)vGk2mc$U{yqu$G=4PSJw$j~~0H09Vey(m}G8jg_W4A+$#7r1@
zCXVhXnfVVMbr^#%?QLql-}KQ>s{A#@#4el>AV+>9NUT%?5$~nn2Ig>4^PipDb+H`W
zg7V{_3Amch%3G!(tIVXZrBh8O8ED|S4>W4~PD3N>6}*QU*uG|%S}B*1T-fI^q4!Yr
z@`Sq;i~PgPA<lG|zPU{V?v-?>K^$GN#C3tiS>vf6=Tt9ab<rs-u$9f@YrYmn6aGC8
z*H=H`C_zhZ-e>=9rG%G65WjcsL}+9)c6Mu1=y^LZ7zCNULsv4=Cbpxy%T8R?hFHng
z?l)d97wpMn3La4AjQw$#%dEh|Omw0zNOGMaKVMneBljb$yqU?_6EEfhroK#4!B>6{
z*fKR6yenP!A^7hBGWqNCRxp45@gV<T(edWf%A#C2zt2C!!^3yXZ7kS&N^&(wk0WR)
z8YhgOhvnwJ3iy?>G>a#l&wVq1S?dWXB>_;yU+0b*HkT0d%;h9AcUx6tYQ~M>bPS$$
zW9oAzeK%#O3*DH|JNio@g?d3*a$63QQk0C}o*IKJ(H>veK*bbpAhpKt$DGox;R}*t
z*zdkl68WyiJijfH_hpTSlbc}U^EJuO!BneC<(0m`9bRmK)b=49vqZc`lpPwYh~f3!
z=2gxuR&{X-Ms7NdG(~<1_hC-J{}{?DY2q~;-RfJHSIq?yJ<_o&ua-3j%oLiPleyvO
zqDedTzwwgaHZv0FlPJu&z^HL{Q+D>*A0l`&aQByK{O3Y&t@o@G6xysl+odzxWk{58
z;2O(Pkz>*=*Y6r@7D~1EGf%(m-uZBugzK9{gYN)<$0kWESJG~gCW$B2i^{LT5&HIJ
zk$eu=?(~pdC2BeB(EqFAA3lDqHyHNq-woo$I2R5S$+WT+!N|Fr5)n#a%epoM50J!?
znw&FS5Y~P%KOiLRtWKa=_PBXYYlwSa_Yg(NK9@n7wOGxnFG-kzmez0s7(HdS`fWA{
znW=z#MMRaW0~J}*vU6pP$m2&6#a@Q;b3_lncX|rc3L7~NpO<Vi9<&7a)?C~9QHVLM
zn)ta-^JBAtIZrBzskeAagC-1Pd&t*+q%L54H4baTx<FxQz30wbT6VU(J<|?xlT&Ay
zKn_JC{CxEV*)QUTgqoze?C0yNw-jCE?}i=C@~6gjH#dI*S=OP?!NjC4c%I_TX&r?&
zwUzKe)RKT0;Plrxc4JeIj7I*JL0DbT+@Z&tf=W>F#ro>Nr4<FJqI#e^*4n+)+A0nE
zfz7ICYGbUSI|0dp6to6S`19JiX}}lHYRiaaOZia!)E-gV3_nT|wk!ITh{k;H_18Ra
z<6zRuBTwh%OQ<R~3f4gp{Q;l=jT1T7E@rkT9O+)-q1UA7877*CWjfc#rz|sC5Pcf{
z(iv>IyxG%#^J*w27poRQ!$T>XiR5vc_`%QKkI9STQ14e@#UO$dz1CUSAb%JyjElG?
zfeg4j7}@!<KuyFPLMM6A*S#sK(B+bDEl@&1v?zdnEgVp1?6GZ#AH@LY8BlBF>cogD
zyPexyWupw3uylv#6Ev@YWQ^e{Vkub&kGH!Ga>qtCB4j#6c%ytGBu*_DrLeb+3y>32
z9S6to=245D>Wrf#Jc21L*ZEY7fDrVXMM_L^HQIbTYHe?+vXQ3e%BsV}q#mVRdw^TM
z7X(KXK0gTBD`@8gc^HV~F0)V!Sxz(&v9A#sBqxmBQFsmUv1nF{k<`n@xDGBrotTNO
z-LrMqOc^LMG^1|#1`-9$W=2uUbsagA-us}8!pWhLhmd$=%F`q1O_MeCUy>8FlJ`jj
zBHFXvm7q>YAL%Vv0n@C7avZ?)93p&f@(?eGZ!C>QypF|OMe*cKQSVsD6yc&oW9m$y
z%E^rZposWY&3f#t?54!b;`wOLc7Asym>2fUUVt~C?YZ|Q*lot<-(RzSfmH*_T4A+%
z5x7T<YmCrbo#d%I^W9ZyB|oqc_yEBF%u9~+P~qP%>6HzWno*~cAgkoqI${*t#nmu+
z$y!}BF{aX4ys+z;=T$yT3XO;eBOWM#Jfct+qc@)@YHe^2dTXeR>^M2a+bDW8MJVA4
z6U({3h#9yFCiM8s+<MYN&;^qV-DDK8mFcS9OwZvUJ@A2|VjUDw_x|^V2x*fQ*XIIW
zsouLqEZ&Iqy#tC|vRw^SNrn|wW2&lN6i>{AH`D#l`P;@jH{*i?Qu1u9VppA<^eWj=
z;u}!_7l%Nqs&><{VA;`6F@@-6XcCQ|rgQ6nF@f*1q_K$7a@!)m^8hkli0{B0D+V6N
z0yD!c7%N&?YNCW4I3M<6IN{9@rcoiiE~oN5ORq$aY4xx6s%y$9LHk9x^Znk_MI_|p
z>GI(v4q@1>ju!d_ped#9sxF4YUoMstHja^=4&NugBnWebV4DqiU{0|}lpr9*3JT_Q
z4m0Pz_xHm`hyj|_SA&%LSo$;)Nbh*9py`K-o1X_|i0+Io$z@`-YePjpjy52tZ6Z%l
zz$pYGR~UIJACI;nSIy*%UzG$cn^VU<dR@}w3WcqL0-EPBQ2EoOmyzO~s!otKqapui
zoSA;W2d1QU0~+86n>6m$Fkpd4Z9W9>p@ozO6W5h0>U(%UYiVZPmyPknEnBbxnRl<=
zku5O7LH<0J><i1q<}^BIOl8y$FOr5Ht}F;{sli^OtG%?&LZ{j0%fQ>D1HqTyKFH%v
zvxS@HMY_TSt#igalXfS?A8&ry@(S)Ji5m0WAk$}|Wr%5+6BVxSJ-$a*%{@Gcf}Urv
z|3-;Np2OF}q~_hU%}BP;esO=t3=OaM96#Jc-y(5K3r<X@<lz*n#+K!>Do@L$N|lz>
ze!D*NT#*Enrz#(Ik|&#rl&wnrFWZ_|M1Le8aTsAgHxgrw!g!|*kWQB`FX=WiJcQip
z_lHUX3b9nrGkN;~c3K%X3p~}7fZClNNSQ2JG-E?FZrM?>^LNqc4QLX6l$N8I>=)V_
zle|>-fi6cAWY3EyQ8w@_=tH7x{a05lbzC<gQ;6p{WLnlSqbQ=nLTbbsX8kIOp)~a(
zO&rz_{T02T*g69HNQf+!2sj|()Cx(r5os)y0;rQ@Bzu;&#v^FSz4^4nM93q@i1LK6
zxE6)~Du|&FJ0Fv6?NutJtEY^(IK-w)GKJCYoYJJ+w{|_Z+ngC3$p~2w(3JhS`Cb5C
z!5S#TH;bp!;KeELA!@kSGax3Jdt1v_R0k$I6#qebtEZZs;j}ki@10S#wT~561LO{I
z`ebdw1#I8trxl}DN+NSQ&6|Wh^r@S*p4ag)%I5c%TwmhV*-J+*4qlB~Yb7Hqk1TvV
zV-dw8oct~0=c2RKZr5S&Esjvd+Vzv&aA;iAijp&{;7<AGXGTR2$Mve_&}@=emy6zI
z0lTwj%irCXq})2H>`OHxnbEFd!%ta$pe202CyL|1&=Upz4LrzYBkqBW2$GiMT30Wp
zWVL4en^yY}4R{4Y{z4*xzG|BbDNt$u0vJ@tX{LL`QHJBp=vomD`@H9O)WEePc&ED#
z2_W@@wI6PIUhJh0hH3raE;g=W#EG%2=(4`76E!t)(P-33q^D#VW(_g%yO+=i4rhB4
zjz`qeByj0`%>QGr#|)*vw7ZplQNPmF!yxjqG46&Yqv0xlbVd88#e8eA`$P{eYS=i8
zsq3IJpC0mF1qwpZH=X|1FG#eSf4bQ4y=ixB;t27yy!`9iuR;g`&Q_#^Z+2&+(t%F-
zJlPD(Aj7si<u(|hzJTz=(<>IgsprVJ`^;F=k&AYEH!v2ZlH<X^Gt4|bga)aLhpxK7
zsweGVseM6ufv&h@oobMFsd+E22=8vt6F%qC7iTR(r}q2IMrYt*AE8d9sYk(;dmKI-
zT1arM86&X+>j)43S}*KTm6H;}e@kZFfO)1mF;PZlk|Xt>S5|?|$ydiUNz2c=HID1}
z1O|9bq$S5*vX^BL(65~<NAy$pANk7vacsOePFjM%W3&lWCMt5ff;>tO-wZ)0Ou&w4
zq%589+ffTU)UM>gk_+7QOT9-5bAlhA&$i_cBg`M%Mg%Kr+D*2|-I#begz^tFK&@65
zxULp;&6o&x<B0R8f4O^R%S8*#;mF+X;;zMk1~X)>d)rA#eC=>29%Z~AoC`TS9zB$n
z92`>6hvHZPAettfkY9^+!hHv>ov}(^IR)5#ic#S_ytrqYr~356&jOrN`ChBb!vrJV
z_x%Uh>P`l?k^|wH9*od+JWdrZ5}pkutB#pWVKd5n`~><&C2Jo0LIMK(krCGiR}4dE
z!n4|2?QhFRw9@TgDA?X3LsLqz5{gxg$gORm`2?qeq=@inQQP-~8jaZdSHWcbBl;A!
zXUUz`;uM^l^%^kzA&A}z6B`^Wj~Hn?s>3$V9pZ&y_~zQF1wWv~C-XFFbti9?Ors6S
zLYw3YS#ay8%Y0sU#cXarOR}G3A$PejN<@CgC~uoYG`rU<h-1TPzvNO?U=~+J95qfR
z;N_HURq0saZw#D1SpaI-3t|`=cgOL0`r_f=UU=2Pous?fs=631UidpyiKzRH+@R&`
zbqV<nuGUXggF<MC-CK9$7iB7xOXZ&YOt^ib{}(=wt-0MlB8HV^rLcW-M+oxh&vdn8
z_`@)6L%`f$M9)Qyy+NnVzq{F4g^w&o$;F}1dkQUFxqCkvkd}>$-IfwwYrTD_m6ISt
zBa=gzVCtJR)~x!z6hQE3JK;AK`KPESnzkW<YX7cNo-Mr3Yvp~=;2e+kEKUTI)QL^}
zevah&(T{FpaZU)q$_(Om5Jsv@E5-<VNroD@p8tPaxrOli;n96l)XjnD9(n+DVl{H&
zw!^l221+ny1+sYf$Rkf%4eKXvT2VJ!KZWKM4{7tm(uC;^9yDfK1kpN44g<t-)V~iB
z3kU#W&t$Dc3>@wkX-N1Ft)_18a1wF3R0x~<>}Q?12SzGe%Zx=(Q4%y=UfGwDjl%C^
zDWq@QU_Y{L-h{d3wADae^F{sMuGKwoPqUaRXRA8AC>T5vp9Dvh<|2<6t%IM4@zj9=
zOw^<MJi(QIgBO09CN2c0$AS42WnPeSZwB+0g#5QH#G*gR(n*Idkx4g2T2?a?7HGUj
zHyq$w;;<P<=MV!KYQdyIlH;MLY>RCDfkbAHz>&QyK+$avG(XEMoxtZs{<$U`j^CU)
zxudv62jIrYe&lG<(<EL3SPYLRjrwj7Gxqmp$*nW&L`{8a@N`arRFbu-7RZ${pPcO<
zi(Rleq39vazG-a<iH7b;&tZaOweKUa=gIxEg`XjGxrD=R`1M_>kXRp?cpZH;PL;N!
zs}%ly=F5`Hsd!CN+i{@NiY(Ju;dDy9fB*TV<53N1HN(f-KTz&Nw9nw`Odg{WoUkGR
z6U@8|X)Pgj7xJDl8s)g6O6=(f%~Z_3FSdLU>2`W|CgI0@LquVF&>4d0imlt>5#(@O
z%UP9Wx2(431ZxEHFHdA>A}|5*7!K!O*I`eE7T&1y*wbSrXQk!x1o91@O33r`9l*a&
zr#ChyNw<$<)W}-i6pYMd5w1e@DdS^g$CgJ|KfQ}aAE8P%L^cUk%Ln8X^SYqTKckLu
z!*=#`d+o73NG1A+VI6bL=aw)@7x!zb(Z!N+Ra7cM{tFPK31I_DHUevu@%k65vs0c|
zyF~&_*1%_4?JDjpuIfkaYWJmkZd_*I(NmsbnK8?}%gT}9dV-x(PX%)f&IX4-6NL<b
zsp-y(@KT5HH{e<5Rr)^-RP)~-;F60u$Bp5d6*uh!zIe_jbL0x3&6-IMT#ZNvxAr<~
zkmA-ECW5+tDq&J{9f13Tw`z#ZWI6(E$iE<pK+V4}Q&K*CooZ&dEu`*7w!Y*mspM2=
zmYD;-TGWSmr~taxEt~HkJwkkvsPQZNsN<J!#T|-9yw#mXn$xZ<9`#dXBG1hdw@`BJ
zzqV8JcE3G&prWR!Z)nWRx{enzz@4b8wNp*FAZ{hV`-pv2W`#KQV#CyK^IYW%kVMIY
zgI&aAp=j;g9Xyx^MJeFK7B%(lP1LTDlp{Pgb#IkLjV8`cGLHUpeEyT?Blj2IuPvD`
z$ljMEi;(p?oO%c30bsoa2%w(_>u=YPTF3QpoLM7p_ylHQ64Ay%F`FyP34dx=(I?a&
zMuK`nzh~k<%RdRZJFrai!COJ)42}0!1usxd*d=1AOwLCDgHYg;4z2N3?7=9B^0q%;
zmDFC+0qZcN)4tL&H)BLyGUjKoMd6^1Qbj17B>|u@5?>N7jMYV!^+vX@A0Tr;e6VJg
z?$nM`Oif8H%h1SbDdTbn)AK2`;SYY<@|J*(v^V$|#3yWf;{@brgPI*uOvz`W4iDgb
zAXa0k8t%)JA%yqZ{Uqi}m8Ik9mM+al4Tn6ZJbR9T`dcDxqTL--h4}RN<;1Dj0v)nf
zRk0@u05M1b<Z9-;N|Ac1RyXSOZpz+M6c%pF*WH7y{7dKK#ghy93l>y<WjIiZxZI4z
zlN`O-PtN&>NZ9OX&ov`LITV&8Qh`REx>&o%rD$Z((2GqNA-%iWkt?N2yolC<lJZE8
zNyZ=Bp*k7{$>+Er5koVBc^Cyi^8WPgq{!qSLwbGcwj1{fBotp*nAjWJbD3lwpD$rg
zGol(e2nsG_=Fp6EKuMx<6fPfh4nrmXzD(m?X#OWTu3Q$IQV_FLa8ebCK+8I*@inDR
z;`YU1Rj;eV<>{jLh#H1qWt-l;Z*|LqcaF@s-B~tGg!~=S!i!(*^z^XsJAEBj??Q#^
zWgh#kr-atvcfH&ww0G9_Bq^_MV-~M9;UO3&pP(3Ja4p^ih?gg?HD@M8r>^ODzdnwL
zX`$^w%l(?5iYq@X??$&+H4h7w5YQkb_!&-y1^YCUCuc|*ApYETDK)dBZN<_F8>!nL
zbd^5869_Erm+=lytKe?hKbDfN16Zn=lW`J~0OOQP!cDF;%*katK|mG>vMj!jFV6xg
zozk7y(w6CN64M0Xas=<L=`1R-@}a>_GNM~?f#c;99O7^fIn{U-snA^r`*oU~7Or~B
z3(5VRH=_2jO`QF@()xh<6A-PZsP|KP1hkjs-vPHqWi0RjnE7!yQ8E+cWD#@1W33)_
z$ldGg-~1pWne9JVwu?R-ct1}w_6@6hf@lg-Im#t|J0N4023i0;Kr)Z36b2zCbc^@%
zgdoYnNYg;9vm;)f%51i3tiK82o;s2ZctwY&k9438A^Br$yt$e4^67<EySn4c6Wk|%
zp-Hi5Aw@_K*gm!%M$DZ|_TV^O(r#ov-vnLoX3c<clt7w6$tbwz1Al+}1<FlO58^JM
z+f=x4X)UtLz{GjTg_^4SB*_6qW=7a*72=Z;;R(y5c2`nO6<^v9Jq1JLCN*UPgJNk7
zqxS!q|C_TSh)6rOTod&$N$(tX>uwDJ@wMpQYp=C@(XwQ|-OpYqXQZSHCW~_tp%M-D
zJaTQvQdNJ&hq3p>Vnn08eeuScy&xg}vSzc*SBJ1^%=B>kP)s#w!hwc}oEbC42zszS
zV!KncXi|F!D@*At|6an;5v*LP9PEgaweO~J>GetvgBJsec}6bDi*VJ&sQH;Tkq)S~
z_iLix&<%kxEnt7I2mZ>!SzFsS=^rSKY0XD;9hB<(_F!b4TI{y<EpPoT6LV#um{wsL
zR1IKG)PG9(e(oGn%85a8$=dBge^f&%^o%a`6|9p7!eLi&7ru;^0G?df3gIw~VohmK
z4=;Cl>tSVmS5K?3W)G0=nOlX&=A>^k>QrJAr@>g?I$65iUKJIrJ)*hSQw~c`Z6Ab1
z#GU18(B~s5)5qh30P!a++<2_Ylue(tNhbiw1LnwlNfc-Yrk=W4iaH1EFJ|=HKItTA
zEldYpA{f9Lu2y~&KIto=dYzVUGEgv&0?=Q1&Cj^Si(E8dE5wSlU9xqkM5821SaKpB
zVC)|>xZnax{aPPRhSiJHdZ57z6e&)3g>4>k`mRAbtRe<z<aT6omOfZT9NGptguIF3
zx%ACIXsdhRVe{OeIV-kn1EZhC^$|MNnpb=NlX)U4#i&!UywfnNn4jb@r3^H>JyI#&
zRg3`GrdG>ms*MwHvF@&Sw}LnADja-MadqGA;Z321B)Vq1A!HAOHhU#FWR|5f-G~Au
z>G-W5c~%=<UAK{>nKTSce$DrK@>5Hd?v%F{6yEK%Lb``of9VutM<T4dNG4)xHyCnk
zjr8iG_PPB0yl>xTgpByI0js`!mZ$#(#As|sNLpb2?<s7K^Y$a7B1GQV`MEU*qJtX^
zW5VOUa@7yAabye**A^N2(~|yEQ2y^<QjAuJk@4&OpgmGb>5q8sU1?U{TUA6~nP?%F
z<n@siG2l7U4WQJ-0GiC?r}J!?r?{6!$okgY^#<|6uLR$tSv}IaHpj97xyL$(xcAS{
zI?nNVOCJV5CVvRUnENVq6gg3<%PPG%=9V7j<|~P~@#ow>cf$@<Luwp6X8}2#)$C?l
zFwmO|!RcgCG*4dG1P(<l9Jeq(F*|4Pg;h`Ujvff$LS9{68dLa*`qW2ebi=>T(EHuM
z=-L~``@%|3I?S@w$vi?ujaiqDIBrv7<I_!=?jA$Cmk`2n4b*E?hG{P6B#c=R+v$OJ
zAv;xg${Ae7Ug`&2c}mT38oNv<`dF0HXxsYs4151mEyTF*KhKSz7O0Bl6<~9@>>{it
zm!w1XR<M@^5=3BFwp%|L?9+tN5DxA$BW%1{aHwF9tb0rkF?g7A{@uWCbZeZl;9qx*
zRBwrXGSiwcimY1Jr7QO2m;agRqn#0_f{gGj;tNA8&U~+MYFZtU$c(x<Aw7<Y4Br1o
z!}hP7M+nlJ*k7o2X2EJVtyYnHh(V9I2j?8=cjM%tifg+y+#n6*&4>1w$TI1`2gq_f
z!V&S8Oy><q4yJ<>+>WM9g2z(=t)}?J()%JY=QiggZjH2ukR~{G=&)8F{0p_FKT*^y
z6t3Mz^`Te9mmHo`Hp;{96|N*g8k3DjUrebZ*My69<9aiET$dN=Y=;Z~xB1E<fAt9-
zg)kz-3@9=kDRR&c7dn&{_P*pK1G*Mufd}3K=jFZV?6)@QkRMBq15$wX)jmlx2)6HM
zyg-eHo4ll71<fzT{Qye3D0jq5DiF~V*ygSuRHipNl8*pkjPq+~`SJ6Ly{^euD({q)
zwnG2p_1M8=&Op5}Iej)L(}Os<?_Xy5sHt>DGp>*rA%YYPW&wjYte3+Z`)_sF84>vz
zY=!ZuEglu9gn<!gl1c)p<fK95GBE>D(ky0iVet#e<uDfF;Qi6N@y_xU(F0++q~Ezj
zenW`f;gC3Ly$^kDR-bmfLi$+{*+F!aOVN<bF*L>l*{`8`8<gn@t>Z1<loVD7AJwm#
zW)4CRuoliG{=-0;@YKo$wuQxMHSbVDU77gs&5C>n{FYv>bE<KjLJ>|rY%XP6ciMl+
zz^<YV){t){9;XuRakJnMRr*=<kt`snF3tIM5J<RAPIvdQTIOr-^z1y(+iCE30!`t-
ztc(U|_t2!4fI4j+`x?0jkYP)~`V3Phl3_47xiAJZrOi^qQxWhbtpUt6S$+Ydr%*tf
zHH>c*MW(~%h)DRAhctl^%1{wgM}=OEwD@ATg+w=eg3C&}cpB%(n&P7sbe`CaP_3cC
zlvas6yDE;waOq8&?U&0p2*)&FzFAB`oF;yc$OrGCh*Pv5jWl9~7MzX;)%3?FB@U_j
z*y>?JanohZ=GjL%_G>7`8ott@C?VhBjs#Jn!eU_$JKw)7N60z^$}evI0p;}iS$oQ_
zGVhAK3jN3Ug^x>AF{hqEL&c1gHJbeyK34=QC*k|_z*tRh9meJQF3Y-IY)a@76^<sY
zqloAi)FfdkcbZVHO4@fUZB{IM)qq`GK8H$+cKOocmdnVZkGSnf_`252sb)&8^AaYX
z*~1InsE_VzetePD8d)O8lsA281hww5(;8j(yNIXH1*VDExt;Kd#9y<Bj0kXrAAS2m
z9pO`a3$RL6fugG{x%pOa!DO(f@QM=z5eH!=biu2zSxLc_P!QH9saFP7lInde?vzAh
z;qf%T^hm`C4QXRS-(PI-j;zJS08y0l)UJE!Zk-$6$FT@x5n#ENFzDn-i=-hbcS7?r
z*C_0wT^V~09=i&-->UMlFW@TB<$9)akUG5EjL8rMP)~V&+5r-kLn|0pCbKOL?qqYP
zh7GyU_22~)f!yT-of2?V&<tlLei<3}J-#)cK=JExmbrQsck51Q0uG%4Z+%OQYEXg`
zDapcz)Kd#bK-Tv7Go#!X{x9q#p8dMl&h&sG{&}+nKU&iypc%xEmcA+9=e%D+1j#Aj
z&f8A>%CsMq(hL(J$2#NpYJVSj)q&cY8cc=dn>8VpS#07{=`p3ld{@bt9NUg5fG#Qx
zzyZ8RPUDn#I_TgI>-$uS=%css5lDug`&XRuT<Oam?+7Gn3U<Osf>F{8hgf&@ONAtJ
z9!&1`M`Ol+vjApd!vEjEz$v_6`g!J|{^Ecxue5d|mJ`BC(lbpUZwCg#K<LZO(XLNU
zhZFd0s}$QT|MYxWF4tDo>~{x6I^j;^QbnChd-{wMBlXB+@YFJS(n}%BG_c#5Gdma1
zLS`X`_{*bs&FwD1e&Kw`fBG4;!io+akjfcZ(a(uh?C5<NQ`crQ$?lBqiyrI$k)!NH
zw?5t0Yq(tML)d&SnatkX7%e&dIB>Zto+?pyyvQ9)76X)@8)Y(Jq;<nq-|2Q3E&a7{
zd~fLn0g<TcJE<5`Fm#HScEQWJ8nTAZ-fo`r9nQ#7_TL?zjl{cPEoKPIvVOdF+prWJ
z4frZ84|e(KdCj-`g+2qOk=BKb7ucJ=YvP5RGG{mqShMDJ1?Vh@bF>%q&8+%qW|uu|
z=4D<>-`v?=GO<yxxKIa)-~u08&F<6#01G#Q6A`o=08GO{r5A{7pNBU%c)DsD0YVj|
zbLSh;V;ZVrHBjV}0=B3)3qk=c64&|@lC05D2GZ>#m9LWM&a1d#;Q$1b^C4o<*w}Z&
ztkPBs#EOnJJn#YBjtV4i2$vqd;z55ZOedSv{&jR}4X9Z9kS50Kj%#b6s><J=)fE6W
z*G?%Z{%dHO-KZuO*kKQ|ui@Qy>OzSkI$-p~sF(%fqbd}%zd4uy>Udx<6`QpAAVW<=
z0p*uEqrhnhGB_HG+w@^ht4BU48s&)hGaMiX!u*RBX9SXlh$r~VF^^0}PS6C=RG0WZ
zOL6lfcm_CS^pYmH3=8mW{9Q@IxNRwE7cH0Ewa$B+;t?sO&~XMB(B+CRJG-0;w`;+8
zWNci&uSBIy!lr6#g=o+xi7c<4wX~gZrWsQ=)y!U=T%m-z45Zv4H(r_>z;etB|C!`w
z$GbN5A&sDFI$z@KsIoUEH#}a^#CuSB+kvi*xpOSpj6vv-d9;T9g9r~>VnQ#vkcc`G
z-VtFi8>%+N<aI!fD*$>fYahM6^tasaD<pglKv|6m@AEc0&GcDR3)o6Rh{slFi=>Qh
z>RNpA6bJLQr$;^5T%S*|)E<QYMz$%OI?2qC3m~2uFknW#y(IRsp@K|>fhQ#&J}}jc
zj?ic(buffWEq|?VT!>9|Zh#5fNM2(jxv>(p8V!=CRGyPfoCor5-L`@rjz>l(L(GKv
zGmCG@V9D*WGf9(*CK8)b6J-?Ww{xJ6&+tclZ>c&1gfI~hD9E{IV52N-oRIm>QmBIr
z$ffjW+L%}ljx@cTE=T*h(lulU@X83xSiZj7U-e}AGSPMK9=3gU81>p}Op)(pcAZ>*
zfBKp7{0L!o&_fhC%L?KgMQ`j15CXjt{7pfNxs^CXNYV;=a5AFQ{00(YK!aP8ON-aK
z;PVVJxo}ZoDDaz<`5q^Oc3BaDB$qsD9O-u{RbCkwI&y*HPD-4`OTi>WPq|1*`8l53
z%2+JvcGH@O-Q_N+dJ}fk@t6>bDQ7EEe6h2ild};tokK;Q@-E{}Pjr++#qU>kaIV4K
z7&LC%+?o^%=AV1p#*Z(f1&$aK{zI1EBU@XR&=IOPG6;N@OKkajq`h5yB&@O4It3{!
z^zSDD?K^;89t39ze5R{58C;@I93T;pP26IJMWh|gyuNuZ8%F2t&IQ0x8gOhw+eu2C
zj8-r_81wf}A1s;JAC3*nIqM`#@`D>Rcicep@2XW=)|`Et-$!7FZI5BxMl<Yv<-Jp%
z#CIXh=(tXel*Sai1LsA91cPISS%<12C-QR-|E46F0Q+b`)r`Psl>_U^?mMXmNN%ux
zL}Oz>5dEJYIw<|~AB-$)W8dSURLOND%54|%m!)gRsL)i0lUhjL*~yYUZ=n=FhA-i?
z8W!AI_#h4qH5eD+-2k1vB4Rc}Zjt`?H+lZ$|0fuHqb}Obg-m4eE2pqmvvHMiE1Gyl
z$^P;nG%4RF!)TYMA?8=tPjX<^p}y4u`5hBN0(E(4ZFklsUZdWeF<)~A4}Z$oGRVSP
zD=0`(5h<PBgCNGW^>6XYSxj!Y!^n{frbUt-VITb4eUUlXqP2jy90gAE@IPXxG$@8D
zTdj=M2eN@KPig7L;*<x+na7^ab53dLF}UfL`JJMZge`D3Tl)S-JR}U}PXbDe6V)oj
zl))ND<X#pgzda^DI6oM0b6+Sa(smianZc@837To%V>kNBq@Hb~OZt&qXnmYG*xud1
zI%r)s&Vh^`xm@oA&5Zi7wQ1u?f9k&Pl18D`KC$yjW`k3M8RC6c>v#UM+3w2c-@W5a
zc#6og>CJ>erX+W2*Z?l^gD!Vp@onP!B7&q@4wlbO2n--IE@ebD&WEN^Sc*N01DjiM
zTa2DDyG)0xLXg|MxG?A^$9$C1P=wncV@PG(!g3ma;*VNy9un6+Q0|$WL--BW!wGkz
zVl+C19m+*~tmo4js0g8z1C23oz6U8xM+-~lr54X9u2I?+Rw)r(vnt9pUeJ&|rSq2u
z|G3Bvm*H>)z`YfI@%;v7-QlkXmeYk-f86CNj41QkYm`5iGkP|BRhbCkl)oI<a&T8&
z4<raCyAjkd)PP2!WN~_Qe=@#mxAIx@_6kdolq&2~zPoj2l2;5#fL(`q^B-c&$%;`c
z*bwhAy%W@x-Jp3O;8~xhM{QJbt|dT+PeF-R*rhz3aM0LDA)R~HvIRvG?W!N6+fQVb
z<n*dwdhicmeoGrE*I(G+wUkgWCQ!fQtcG2HrXs7t>&^65zU1rxjCs(z?DPAL0MQe+
zCs9njM4l07R~Jzuip$FWE*Vhv*^p$?FO-ibM8XM%%Z-Es+Q_yK(soo1n>y!sGIP;=
z{Npbo@4C~(rF5=b_lq+=BqsH5kouISzpZX&BC?Z8I{r=;sVH=?kDUre9JR0Q7?AqJ
z_M_%WIx12*whnV_BR7`O1D=C`EMZ$Ge-o7g2sqnEDAy@h##z2GMYy{Z;n19jq(DA%
zN=w@jiEyNJZTr;4-6Ttb2>Fg-clAT*W~o|{^@~b6Rkl;>!`8_k5ssi;S$oernJ|pt
zDVp_7$UY4SD|`gHF}XTMuVj@Ctg0;MouFK?GKn@~Snudd85^0Lf0`X`jm>C2oCre&
zTLHJtQO+y~TJ)ZfQ5`V>;2wX(a+4kzC1|*6f2<9WB_yv10Vf)4yKe&88oZ`WkaQDZ
z?v`3h`v*pAzUx@|5}6>M!F~4gQks^PHo|K8Jb#Zjb|KUp#J3oqtk@RJ&2FFuXQCqF
z4biWMxavx-bR|ftA1&P*D>Eexxg~AKH7a=#+kbLa3@~2%bxpxv+8`g^)!PZRH*iL>
z-dX02(7-=Sc{as`f+hLX(vuv7ca>xAl=&NF0_4CB>3&Tc0xf0E&({JPF8@BbxjuZx
z=65j7_@WR+FPFjt*A+;tc7(TRU(D6Ya-MD*tzt9(-`9CDG^nYfC8sW1{V4)<L1z~-
PzBXb6<N#+_(LQ4|`dTyN

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..4671486fdb4535f72bae93258d012e0e20586d98
GIT binary patch
literal 20784
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjz2xSYmn@<OV-~lAqPrW!-eZ)l=
z1r7wGgTIy_*g1Uu&5FoRg%2VFJgf=lcX0!zps_5+8cXNuy@n0tsR3CRCJGHK)B}zX
zaRhJ+R0hBBuf<ki#Nl4JlOMtjv)D2yNpCfR&J5}oED&;?^y6bd_1f#}eg^01OL^sy
zffw|ib8nZ=%sQFW>oa`M)mRKs`*Q-s9M%1)k1j={Fe{ORMo&JA9`eb>n|s1B^W>HS
zM`}{z%gWB!8|mbm=M~V3G-@pG?R2;+zBTM4N8d_cTj1!qJX7fR{|^L^a(}`R(<uXL
z3y=#EnOfd2Ny&rMG(N02N3!{VTd07cz(e_%*3u8iOpFwQ`-@cp*xn)c)nQBN`?jIV
z=V>WRU;|S?AQ@OY3i(%-cjjypM8U(Vo)=Dq(zH&u?^A&sP!8j>C!1Gc>&3v+vRmqu
zG1sBJs%X?lLET%SqahX54%w+(PPGQsOA`06!Bv=24$!8F&zn*(TPKp9fSj9%e^b}M
z>X!Cb>(A&PUe?lw#3+#RCV@V(e*Cq3fm!g@?plY)bNzN&gjNE-Nx<v`b9xamX6<m5
zF}yQqCs_>fG5J<v^I-;x<n1j?%A5>ibvZ_pshxQ?{lzAKq#}UaJm?KAE!i!vMQ?RG
zCP*inlJG7E2(O)Z#L!&**~R%P`{*O4i0I+c@gz&?^TKjiWyH=l&@uvd-e)R7=G51$
zRSCZ`SVlo?4{DQHcnZfcvQIHREUOG-7z=i~3GR0u4A{ZM^waT&;c<3GWIdpjggQ|h
z5N@X}*nG@KzsOAoo`ld{4h?*ND>0n>scks0qDyFbY#_L^L`)1(@T0Sz9tO2b2w}ha
zVY2nVl{gV_;TC#3l~sj<HnkuG8)!*fPU@qhSH1?U0r2_NrO)?~3R=oJ6wW=Ibg8}m
z<9oTvxYvj%1a92D@@uT+S$qcq+er~8UpKba?}AyrhOHJd)VAkbEYC88C@dAv-=vtV
zs^kPI0}7j$_U0j1vlLS}*`@qL6`ts!R(fVik%RMkxuIM!sL<6gV{;Rc8<gvF0+@ty
zy)XD-fi2-yX20IUPD>eyx@mpS;+V{=FONNH>suSL)IHzZtl%^jrI3Z3{{&L0EC5WV
zPmsgpyfs+r`8;<6W4_Kp)30N;-V~^3JU&;ue3uecvMl!^g(L-VZx+td?hMLKuheKB
z)iNo&n06>&(&>tDK8N!&(Z*7C%&YMossj_xS3N#z4yDlLrz7B4J(d562-rN0vI&!l
z`Jad>=UJ2^Y+XaQrEZ0ci{+;qn2CwMtxm)UvL3?eX0sT-W|&)b+;azTmpZ4%LlCw7
ze>lRFOBkDr%Wz34g#OtYrLTyO0Zt`CkzK-$=~B8Y^>(UEny`@{^IHbJ92f{vugVK=
zK8udL(U&s~l_}aq4FMeP>hLL?+`2Nw0*Qto6F{S)H5AwJx&^ZH331AdCGJ!8d`-2C
zsC|kw{1|WG;A;ki^Bx~bo(^Ypo7x8L2Bc|X$y%+BS-0u>gxN|qE(x1yp8(Pv?LiR2
zr#Q#Y$seVj(;H~fbq|hQ&4U(pu?U9yAx`a`8u^i4qlLZBa^(a}hDWnC9b`XA?yNy)
zj~3sBctD6&92pZvX;^asOU22pD<(4^csU?LD`edlQkOuzd+Svmk25JjSHOeK)UeVA
z(1$)Dh3G*Us-xSJjAa&o9}GwzipiJi=?^`S7_okR4)<iX|FzMoPIj?}>bZOXFl;qw
zXQHk@?%O!Sm|;#myp?wt>DV!De*&!5^{--4qctLJGQ!8Ss#(zdY`q4-&s!?1(5<4t
za~+l@Ey;CU&ED<l5b0Pjm|Z_p8N?BqMx`ps>4}u1=kNm)87x4nKv!$4_5xP#|7|*7
zG<hFBx{rF^o6TFRo+dJ>X=N6eu6PQstqt*k!<QAPM>PT1s&6k7uK>;mFa*ce5ZD(t
zDnx|3k3+%wZk384pW!fcfG<*4vlgJ#1JN^n$KIvI9k<}g0`9L<p#%sH01J{E0~2r0
zwu9Hjt*M}DAe4FJh_!uR(8Fo7;wVdjohp8guKj0tT&j&1&m|LflZYF6m(*xTH8s@)
zq~ad+s21=;Z^$9>)P^z=Pu9Nr11yB&(r|;!LfO!Js7+g5S58?!sQ>`4KlgHEeV&55
zTUvS0c2L5*7t13lF(jZ{>G$6U_*X%L!5#!~3TY)JrYAQ;H!N4=f@ixM0~jIiTEQN7
zz!VA#=onode#MC-oL-8uU9nw_{UR13<POU6LmR|Zix7V-dmfu-?E&XhZgb^{U3Y+R
zV2$#z3Ycnf{A+)9g_<yFVD7WU9C^p4xtjQn3Z>6;q<1uZlzIC)*DOH9-ft@Ob0Sy(
z3m`4(@Dd-Ir>~{%libzjlfj&lH4D3@xSW%bI3cM!11{FMt=W`Cv(b!DpWcJj>x?vS
zM!C_Ms5ZlsF{C<c?ANs>W@+0YSuOar+iBxk_<56d)I2c2aXC(kPSecN!^q{0lam1}
zY(i5q1-dI^0+BqaSnzxt_E<l0ZMG9rnlQ#(iW;<*U<XX+7`4}kUDJBJE|PGlGIWPB
z@!nNNsPjhv{ftrRbuEz7x~(@_b3|jb;tfMn0<SkQF}hmDtROe!XO6x7p)|q(Lbj}@
zh$+*xjW7Cl6N1br%;P~NP-&ZWaBGypC$l3*fkxJSQ(*7$&f%v4skNBR(<WIYwD=I%
zyIbH&9cz&gh#(6iHf))&=_j~J#%q<~+)WQdq-Sx!Jd`Okpdee0I>(<mYlH@gMa4xT
zXC?BgvLWpftrEaiv;px_a+(atd6mXC?!8V|+NxxOk2R?T>!8$ec<NzrH~bYp=M@k4
z?j3*8d!fJsgtZi17(Da>_xB{u9yIO9N=!Gkl_;=?$W9%6IP{v$uai@=dsxyAKe`eI
z-6QcmeIE)5$?GMJB6c1!fKg_|F4cLm%?I+<55LhEo;aMf>|)d8rWU@x$EM}6i$I|d
z?V`RPL_1>Whu4H~P3I#yC8hI?%s=9)4f*Q0l3iBTppEb}kgNOIqjq2^#w#T5iR*?1
z_8GXaKimEp1r!W*KzJ#7W>{Y{)0TBVC@j=b1NRu%Az0|_{t(=zaPNuqG4<3UP)c9}
zrS+~C>DZU}j`(y<J+(c$YxY2ism_MG9gq9g$O|r?cl5^R70r)2ogV~K0>quVRToKz
zmw~?iCc0aD>X?i!F}mu3e_AR@RuDZ?tj^rtwEqKNHZFq=vS4-@rkcFQU%CNhiDYI@
zeK3W^7}a(h>1L*!mG(-u?p?h9aW_pmC7N>U5_!T&-|9o)k*1}Q18R?O6ZI++VRsq(
z4Bt~6zAbI*0Nb?}F|FMUA#On`FV{~2O&<u0mtYrFly(whq|QGkm(+&f3{Ua#4d)V}
z@`(n{5gT<Pz5NYk{D3l_jYw&eew*2*+x~6<e{yNL9bLzP8l9UM3Q*51HSHr)&Ow|_
zwscE$*d7U29HeL-x>Zs=zrn!IV`wUd7j8?j3hI9%wrs(rDCr10+47L!#`+5uK1wYQ
zd(!sgD_^L*puomiL>ulwoyu)uLsyx@Dg4Nzgw;Ug9l>h*nivyv{k%pHYL0<<G&Qe(
z*A@5PS_+)2%05mu9<mD?vDQhjcLjWKG#@$g_s8w7+#a0qI^$gme!tn9%VkJ_5tX9h
z7qjQ>nL9b};o>#bs%H6EsFn#0M?GI+@g|DX%tQd)^dkHRY?DIdr>Z=Z9KO9pQ+e`i
zqhG*iuXWFkHAq-x&aUil%&!@wI26};Y|+gWE(mD7;wTA;n^o#q>=w4)tUY9?uULqV
zTIolMiPgdGxar2^#d`9wbuRE3kdYKz;}iZgm0X*8ln%n5A<_JD3aG11S;@4=PcOS2
z^o5aWyWp0_jSS?j8|bb#Heu-IPcQqd12SfZWaK%$$mYk`cgqPvB<p_R>r5W!=yS;4
zp?K%;rWVn1#<Yo^DOBt^PxnaI7Y)E6l;$xi7c6g)G+zV!Vqsmr3mI;77f@Cr`Trsy
zNoE-fW6s>LCD6hRp}<OG&6utz;c^TKa^43ei~_jjAen2T0U=?dCH(hDeMTN;)%y6a
z$vD-E5YTbc>Bu&#^AP$)qB-XRR8LCJK-0mJ5wvgU(c*I<zr=gOvz^W+nR*6{^dOj^
zVOP6O;2?`y;sZWmP_N7g)SZ%qdBHzuE#%J`6_2UDl?D!@H~^+R3NAF@|0Ud=M7mg-
z(^yk0za|+8fY60p5aBWI6q!AgjI7^n*txyTP#7LU6d=$xGE|{r7PEu9Sb%#WxgYql
z2^ar*Ei9CG>`=)AOjW<zJf+|3|KspS5Y0&P`PJQwpT+T19E%3j?J_xAzB~H??yJ;4
z1$Ql+Z1wMStsGp!lT3|8kCyEU)e1H!4@|JnWr}b4y3rOll(RQ_);7a##+cmc98-Vw
zd(R7iQGMdBEoY8(xdFxeS1vxmp>?`^0PNZ}5VjM;?)~oW#oCX^ZGWuz;-4NB3%+H%
zQ$D&s*>I!E((h3>Nobg@B~o0oOp_n>dO>i&qvc>*k#H>4{4}Er1&Y3{IIuBH%Zo{U
z74bFo=M#SKjWp%uQyT+Cd)fY|QIF#pHbhC*cOGm>R|)6$h=XHKs-uecOsv3@k=Ikj
zi^U<_w|p9|2>McsD${XLw^^vctZNR<f#56CvnjCvH*0VkFiJxA0X2`)SSNPH_u0CD
zd|kd%H834leJs>66bRbp#*bz?rBAVnQdT@g+o5FO*g>9l{#zne!&P)w80S)soQ?>#
zH|vt$(b_LEoXe3$y8j*@)!1MZMBT9h2f6o^aJ16u0n;T*GHjBtPN%!_WriU&#2+KZ
zW+=Ng!}b!_P!xW*!vd5Se71Lg(EoLKq3P>m90EbmwKYmJPP%p<;!=TibOQh~a&S}s
zNtHH>t38&_!EWLm#e<AXixv%sRAuB)P)=NqwcWuRfq}{MN1FC)q+~HCVPb^9yuw;a
z%ud!n&X4JnDk2#V6DS4Al1;_)y|nqYD$^(H9J!f>4juCE<~&&MtSw#jT=>4f0SDhX
zGKBn&nB_m#fK#DED~UY4j8*$!p<V^K*P>D>8->_KlpLa0-l&zW=OyxtIA|jK(oNY|
z$}s?!P;Iwkj0mayS;FQe5<81L#u<_zXW?+sd+R4~#$5Hx<FLGj7wUx56$g7~V8i~f
z&5?B+p2ipwXzMYyunc2UAf2x=A@G$i9Rv2sHCX7tC`t%UkuYGXPqg%Wp{`h|=OYR!
z3G^Ou;p|RM>e%iO>*6itCD^2O%^`Uav0f@KNr%kut0-n)pwn+vxJN@Y)QJVx-Lpb*
z8R<iYckvW~0E2oH<<4jS$kp^2wyvT8!O@e4!<h?klkz*PHOrMl%OILEVy%$y6fzAe
z-aYsD*VB0IgqP6X_~9Q+qQZ!o*7ui*@hPr`p?$zvs&7BYHYy#3^T(dbohaF&T7_ff
z+i<-#Z@}eSU*tbfH;m)9`aru11oAyrV0moypiNug&zf<{5QLb>npH&5D>v=i!IlKF
z(2UP02^>HxEXVK66?pR>?Z8KK0_GQ_W4*CMjC1J+{=Z$k|C;W3eya8N)Bqm8YGE<W
zN#>$4%R_tX0A~UD(5eYM2#aZ`Pn=k$T`6*wyl(gYA0`(Y7-t-eTKUoq5F~y0JT<p6
z{-VbCxZ<t!yS>#D<E}#cy@Ek0vKu!9WKYgwXWLab<$PDct!2Q+7b>a)F43t#=tJuv
z)&+Hxj8=0zOF2XH1muj;JT`viM}a0DmK3|5>jRuUe)B<C?cK=T&$i|j-HOB=n!tdr
z47-UK0K1+4pw?n9^EzEuh(?a$sW#jSz!YugiJ+#*i-zN;;dfQ}3-gm0oDbcZvYEyr
z8^Pfuf|+TfGVP+ZoUm5vpntY3C!YSIgt-*tlaE@)OkSN9@>}>fb-3I70|gw{AQA;k
zy~A*)3?NNcYC6A~I@WQZr7N|IFAoO?YYs0&1@bs`pKO%E6>V=?_n)1?6bLFa_od3_
zT6gz#2b;{(G%D<$6;MFN@8@&Ui{aWvof#@6yyY+KX1GXpcl)RY!*a}$ca5*<*5;Qi
zo+=M#7dvOP&|yUX=FlmrWy@q^<Jtw9R!MCG%RI`FG&^HKdlAc3Z;cBfA*$*0sVJ0e
zM((vB3=at?P)lXi3K2@E3XZ%umjj#SIlE6<0UeN?Q@9|snLR4fFtOtgrOUxt-gXc`
z2;P#Qcd~Pc2}#Ds0)O(>=fWcGeZVoAA%v}LE5vasA`qVjS$>HM^~}F1E5vd;id#~9
z$2>&AjLSD)tsBie4L>acQDNg~G85~#EY^u`tv>LnsFh-7z!Q9|OeFu$JANXiFJqe*
zRj!nPU0JGPX=`<X)0D1SjaMP_U!A=+x^Bvbea@Zz*)lK>_-WKuYSUu&v~7}18c7kt
z{jg<4d=ge~^EdeRG5xz#Mo-c8d1oI|l1~UP%V&eFWnk~JQpeeIX>xdCkv4roBKwQv
z#AIn*aB$~H5JT~YeH$3Hny3JLQYOY9g$rNVtxBim#7XrSknT3>rgS_X888P_m8baU
ziuBJ~aW(C$Sbc7%2ZV!O!mcQQ5QU-?nEwUo<es^4a?Z3nl!`mVIro+GsMyz#q;+$y
z^+MX3Q#J@DJG@=|({f1TZGgxM9m-|4lWIn2wXUE?$cUrcOE=NL&oA_MOMVJqToTk-
zHGx$Yn}%e{#s?3+MaJE8SDTF6IZayGUUd*49_dKP*XP2k<vX(*vT*Wh_78O>`g6_Y
zP}zF|+Ln*N=db*udpOjTuKLh#+jV(%ywzdeRWc-5V#)|S9UZ$M&z6GtN%oCLxORV8
zl()D*EWwhr+WvO2iaw7r|8~GLNQ;nhYs}$T<3EI4!SLK+$JRn=+cf-ddTzXTi<36z
zUeW~gge3=}5+wO{dCz)`k!x<pem*XvrPY(fAz?xzO+j%9z|2Z>L*9cST)Oqyh?oX6
zA8^F&*05$nv9u5Jp+=JI@GX*B$<N&`X?JP(nk8pLBtl(*pZ;4>DUPrg>kosq!^ODk
zUEou#Q?~*s%=A<jG3lj}f73|F|IX#P6uqgh*kHjV2K`?%NOsD6j1Ko&gaYX=zqDop
zjS{X^sLp=gpP_fTQ`3)`yHaHsVk$vQ9QB?Ed$LT%7De7XE8pB*vq)cChRvDf527qk
z$9%9u0Vf`aR<|K?&bj2Vpgk<&X^(dO+-0fGRz@j}r6>9UKwqAcqpv(jk{GVJvAB^f
zKODN_$UYJ#Tlp1boBonL?hF9UGobm6K3&@n(%(H<r>#q<I1-NSPc8S|rvc+bq*+`<
zLs!K?ZpY?KD&Mk`D6wJ>_R0Lm9M379ZWh<hhfMoEUMDDtCu|Pv`wH+%=;97$n!42|
zB1mqr<s<;Q!SCiVLsd>UyAyRl9p{aXN&@t%qXKeV>AtAi?CuT=jP-#h^K5a3&Xx1=
z&>N9j@7HsUs)81PbX<!4gnpI(pPbUUrjlAjC_4wbx#K7M6W=km;CpvRC7C!K_Z$Gf
zFgU6{lrvhZT+TdK;svJ5Ui&qTC7W_Zq*VnFEnB&ic1u%uR%u6r{Nw$JXpI3D=6g_A
zs?`RbM&S|_OhLoq&*zTon8cQCORv|^$aPVm=zTrr4a9ThLX1xAXxF;{0BMy*tHEPt
zGS9tR^im{)sf;)Ih+Rn&GS10_dT}LS_Y%^Hx2X$+x&Gpb2tL#0BpB*EQ1u=+;oJ}X
zaCLch&;Nz_Hd?hC4)RcvUgSm^y;VOJm+ARAPiziI&M*d@c-56rDIO+RAWw<|7NtmJ
zpb1`G+Tq*rN>>ujhh;N%Tq2?8XrWLNm)575%BOq3KEQ~{jb=&<qnvzhrY{2T)8skp
zFmn&}aXmwYILEOb^DU{6dj3UKP5mGum=SxuE(zF~>Sb3mhd(iG(z+x-2sF2IPafri
zOiI)ZvZU;Lvo#A~OpN(Y1fA1)V#71Y*WNMuS#8w_x0lwMQ~b6VThaJ`U%^~BUc0y9
zcX!#V57Be4>tmsWkU@^nY;efofmH=O@R@pf7aXqN;hcIS`c(l*@(}215pX0Rlp)YH
z$q-hjzd^(wuS90U!}j<Zz^+btff;xt>djcG{<eS1ZU3h<9qNOO*c&{qk9c0!5|ni9
zodx&(S}B%-64_mtWcRB{7E(#a^M@?&MJj!udl+dC$L~lHwf$*)%y_-!Po=^%506wA
z$y`HaqmAjZ7m<`z;*!|D**iy+wOl@&+yoKF(O>gUAiUUqkH!14gS{+p*}~e-W7|z8
z;MV$?=M3k;k2KVcWl6N^lWi^zY8-7WC)>oeKp(`?lt7fVQlU0E2LFD#S1RM-DbvMQ
zpdb9Yg>FztQ<o8%3PyqVdqe%7dA*zj7t1iPnL+#Wk2p<Ct5Ee^#oMhgmJ#*}ya<-E
z=Y<OIue$!P(4F}EhsQq(l-p^ChfKgY^KK?*TJOx@LmD^Z{D*8WmG-@)8UNH+c((wc
zm^|R9lE(vF_+K-2ovm4HG%RW>Vt&*bp3D?|zfmnoP>K=_r?IBWExy}*1eyM*E{lmV
zWOrWH3)60%l}*f)EUwZzNSsKBK)qj7lv{mLHH5QVS$J;e*X!j}YY_c6G_bpekdqaO
zB*PX$@$WOgT9{i}^Sk7bG!GIPv^df4vdAWm<QvnlBRi9R=sx2}0@Yt!=o>v`7EoR?
z-tHB<i-MO?V!}(6tUzJwVuehmy~&DI#D2pPYF(cy1f*i8W738Jx8TMjE>b@>qnk_U
zk?X>37y`5XfvfbHA*d9jj+}(d#iz_P!d!?=w$-LBy|!y99?3J2Z1Hzd4UkPGg1?oU
zx`_zhd1NEXpe0^qQH!jw=@2@?Et`eRO*B^&3WP!2@?y*-N|ZEF$IiOSE7^CPt46EC
zjND5*Czw37OPlWSj+2-RRQ=>QB`NOko|*lWBlBRDp4>iFSl!`6Zf>;U4;7^WPr|Gg
z0opy6y|gIqIkTtkw<3PtoFC6?(KM(?pvEtuvH123)d9?5dMDR#&VYkH?TX1h4xe=0
zn>>-rG{J)MBoZjfsVArjUk0|&XR6#}<4j5T5JII&p`P`4)(k5Ye<{}mto>%_@d&V(
zZ*dmjWv7zAEnb3yTN=~xwNj>3U}H(JvfspN6n3?#7ZM^FDK4J1Mx-#P6GrhbXDRhq
zJzfG=WoCudv1CCOCt5n~JRLXvr=w9!D&v+v2Bc35Iv;D~xMq50<QaJl_=tQ$BNaG9
z8gBi#@6Cc~7yjkqEOXv3YQwNJT(Z}UbJs@uJG?4-Ec?8@L}g6J|G@CcEVK+Wh$RlS
zpZ?8({UhV|Cp|7kPrZQ377*@kEt4MoZq=Wt-?_W_;Eu%6s5*DZrv*%kALa#!;g5+}
zPzb33Xx=z!AO~PNfmB9IkPXDk99qH7DB{YqLsYR-(XZZSKY!gHqIqc!gUNeMKIO21
zxbMAG?3qLg2K`6~H;=DRVQ6ZoEfxgUon;4xhRYEztlMNsDg-NzENd(}Or+eQOaGg6
zuq5BJgp>v|i_omO?M3&9hZ~$k?C9ZSJRF!F^!&Z;UYsee7Q^TdT?c>n-$t^hm{~AZ
zadQ*9>Gy$dqH2pXYACOEnJ0p#7aIs`BD}Js1a+PzPo+qO+lx3}IE7OY04)!vw+-<V
ztN~jwsPDi7#|IG&pWn9>9V|#uxKQF~I6g?l*OcrwVJ_8sx@ohE#cR)}&LO-!Ull|v
z9xs%@{CGEvS-Ec<@|XKADp!>%XnEivQ-{LNv{p|X;7bVA3Up6<_+u-P(=0Kq_45Lf
zyf^eV@-0k8q=J8LDN;m$e3&y%Of!|rMx_)w=%qGk5(-B%i^OggVC?(aW}<B#)IT*d
z8k<sXnqyZ+gc)W|Qs~BivWoCZvh%lMhYdKacQjY7YHmA%HBrkQ+@I<{UGEWk^z?tY
z^W_R$+Btg@s4f1t#So=O1(y@3A!QHk`D#=7HUK>a_4LFN_`8^p(84rMLH7N}B)7xn
zv9`ayW^55S?&LnF>8XR1mkwn{eC&4F8R}pwcIfDD@dzA?_eRceR$}ezF56f*Mlh-m
z-8$v1wS*D;mqp3%y~HO8N^#@^DWLnsEhc!EKR?le4?01Tn|9ZHzA4I;+*hx(?JpG#
zowR+To7}%sIdgL2>Y3lLJ0<5qs{{r4=Olr_8oC>RzcA$sBCcN5amdQ_cEC%;g6`Ss
z!OK;%5D`FV0)I=vf*BETxot)k#|DqV7U2<pajqC2()3eWMM|+|lI531V7x8)2emhj
zERt&E9k2*bxyhx-)c~JUnAz!`naUGg1<M8n&o6A|d`!F|Bgy3mbhrWbcdb!05Q)qL
z{xSR-`$zJpT_6M6od-6j-zDV+jJj{h;!#9?;Lh_irh|NQtKh-w6`REp9Ac!7meF1>
zy7Ie2!b%=_#k3;-LAhi#-Rc5q|Nm&d`#)9SMMxbyW#{coijU&K%mJja#3+?|_zpR$
zqa1zrk||h}AngBM2CgvoBQ?eYW`9dVq3&471j@W&w3QCnfcR)>7%Ea3MUnU8Qik%6
zu6q4Iy7~X6)u>g5gyMgY=D7p%D$RHBZ7g^G7ErK_n&~ZYSRU_@5I6hc36;55{?W`d
zE>n27(x8I;gc2*JAiK_d9G_S9>@_t@MA1&VP*MaQK7FH$4IkY-{#_{@aD=(qFHToa
z)AyBir&V(-sY0yAPj)wr$#xz4?Shen|5nu1<>@2igP|joAzVw@JU{8mP1$5=fD1CA
z*oSxL?-8C2+9j=#p#lOb!Z0<Wr)X*HGghMPO2Vyz7k}Sp981Cg?kIt*E$Ol%YQ`O-
zmpJeFSU}h~edGGKWKjE4US3ABf=RpRC#P2>5aW}tBim}{8LazRf(wFa0*vO#^8)0(
zYZ~0{BT49(Rn#1#EfY}ZF2@^lDnsOzH%}5^pLnz0pjx`U>RJ+=%gN0P4s>+&ojm_?
z@Fe<8au1RN9}3}eN}y`dmb_Ok)WF|(XNEt7C2`Sg`bMwP|F0EF7f`LwJe6?Y9u-;j
z3$3&=#-{4Zx}Hm9p5{036WN-BxjY(211IVTx{p8$Xk4c>iY1J?vZ0Qj9A|tFVs)I!
zd3NDT!>`$lljrey#Bg}fY{AF<`U{}!83y@W{mlvFA&IheeUXU(DdlzcoG`T|0R2xU
z*p2i5ekYwATf9>CaL@znOHgPa^YH$&!Q1byvD`(b>(#CZJr;AZE7HvkR20K4>XZTP
zv^<F=u91{c$4lT6yFiAqz5_hLO0|EGTx&;YbU4`;nBPA(jN~l#DG9K_VUXUrO_gf!
zJyGvnDPgQQ+63!9+XDBw1gEzK|9#V(^PHlA6gu&=P)1|x^M9~6dvfMLwLkaw66&j;
z^WN%}^?UTRZ)Y=DHvz>iZ`hjB!ec$QBhb7l8S*W+OT=QcJl}iaPr5XQS#Hu7o7OE3
zFVp_i=4Amu-*qTPZ>%u0K($1%c{15KvTrU~0&rA2ah5>e)^-xfhgkVSp;y$a%&BjJ
z95Y+Ty5inW4atXR(mI!JFdeXUcG6Onj|2zr<ug)d^+2(2WSl5!0651)BOzB<fVNoi
z`YyvQe2;Kr17P1DZY&hs#oo{wx;J$tOXxTOVvqh5vLuP=7IS*}-&l!H;)+@E48oZj
zimt6xNm(^xN1{H|ZIk8{UyCQzFA1bbZwtW-Zv(f^@p>5n66uu*xgad{c@^&MCP-@P
z-aW$sO6nn1sZHDa5;-bT3V_24G7L^Tb2gm_8#%L>mOf(8y%Iqd*>LHnSML7AcNtL1
z<#NTdbwcQF0<u)0-V^W2f0E&oHQ~#cxtQQ37Qp`5me>()@*$4uRIVo_Op*exrEIB|
zEQvH2#|N;yB+Y}_C)tExd5Olf^D2b-%!EjN17c(@q9g!zlS5OEI05Op&{f_bd);ao
zE}T0S_DMz7b8JSOk16k=X_d2hR24~};|{}~z`yvH3pBC`4qanCF*R_tlfH?(dUazu
zjXG73_1gCAKa-qYN!|DMF*2T!VB7WF6agkE=IG;^j55y9ZyZFP`Txj$U73>Cro@1s
zyS2F7rhqMs`Xb`Ow^J@OABLQI%HyGCD57R4P3X}>PZ~3xQRv<dWb*Cx@Fp`~w6nHo
z?pHigBG<@Pb*Jb+5eL0Yj6cXFKl~1J_l^aeExF$EqLCIW{|}pNusXSVJdTQ5mH+4*
zArFhk9hZnIFHwf5vsIk#@kqD>kSH%JcD6)h(^7V=2g5=)fe)!r6I19J4{dH|yapVM
z708;}N|MchFGNW_bl<dXM{@n?*prQAd8dbNZvVv*kfCpUP2Hf~12J>XQ<65M{`|@5
z-32|W??9KIAqag1ss-agNHfe`1MVWWz+rJ$YAxrxeLMw^;jVw&%X)7=i$Sv0R#@>m
zER8vN8*rr?ESGnPt9(h^qgq09{zbnX0i}B)a4Qc%c<lSQ9J2zys4;9pJLr(l+&&^}
zk=f|NMit?ZX^*zGO{KKsy|^4!ILS4U^QbY7W+-%I`)VMOhD^?|kXb%w)1D0TXm&|1
zO_W&{r(2net>EImy_q^7S#J9B_B$?P6boO{`gW%TfoDHFFI-6jlb+%)7ZP;|f{2c{
zc6mPKPt&_|Dwu`E_+C(WpP!KS*1u=Jr~V<}Ex`eT&x{(0bDWcNcN)ogCWDxs9|D##
zg7TZ<XUdg+9b#U5ALVHtQKbN&R!$@;cZRqG^loJy85xJ#)K>Q^blq5S5ih8Ldb6kJ
zK#Y`nidD2$v5$$*NF>PYlOGZ?5s!7CA$O0b)4CCLDy$g(X)3dg4U*a}2EbkZu;&G0
z=vL~XQEV}ak+6P<*Ah<X%tAKcd?>eBJe3%NBk`#O6<oT^og;B0S1%^S(^R&GSR1@O
z9a|KyT*zp9gn*J!YOufR8|(6BfZzfgvu}vHgT7^*dX35zuH|Op;Vbzeh+of&-59Re
zE)~WJnYQe8HbGHQ&21}`)=k-^e}2BkK)rQgK|Sg}kdl`e5@O1~qHl~eE<|?D+%>-O
z*i|py(9$$XjyU`~RLayB%`&ReY3j{Ny%t@KFOx3@zBRcgV~KZjy~JsR3iY6UQM~RV
zIxFpBMU_`j`Q5P0TOS+KTp5sJ`mj|n_W+R=`bBNy6zEOf3w|T=?=);2th6--8C1Du
zR0^)I61a|Kpc>8fK0a;^Sqxmn3IZ%q3T{0;r~(RSOptBPu)+iC7VyrEobfKMC1XEb
zv`^LX#NX&o(b8PGhl!<h`|ivUKPQbJ&?M23FowQJrOrS{;|wDue5tFL$@c8KWzPf%
zXrluzq;%{GVO44PI>~=MKrZO7X&vuzjgZ&l0xhodWf02*_^~gXqU9ZwS3-cxsQJb-
zzIHF-@w7=*f@kmIXYPttLf{RlNf<3Nh-DiST?$DZ&cBdubQF8Wov12kin;pPDPyay
zV_Unv5dvR@=bs2%dH4Ip5#~26=*rVHV5=awozo1rRddE<25dxRidn8kKK^1xi6e^0
zhYDmJ;$0tFxQT3!Hyt5(Y!j0N7-b+lO?&60*TB{nkfRt8mxa=Z&>u}+)?OhJdaN+L
zwnmP`I`=@<3fzr{enG#Azq1<=gsn#yr2%yvSss0^(Ei8?UL@UhZ!M7=5|1a697}D$
z{4+IQ7(d5+U;4>!;s=`a!Ewf77w<sq^*3C%a4^Py?nMCek&Zw9*~X+cZAsQ`!kLxP
zyYX^aPtM(0;HfZEvKa33ciHLNQO~P5u-vI<aTPBG=tD20%yMKi?V?(Fo~ZDRoNYAt
zUXHb!kl-H+qatw1c?lDXERC0Y+o&$H4==(LtAB{GiFvS&Tm3cJpzcx#_`W1WwlD;G
zG!XXZXV@#asAtN+=de28udV0DHJhpjmnAK4=Kl;OK8J*pwvg4-S(aZ+1P>tzisBxG
zy9B`TX!S(>aepJDo~U-6=eR?dRUkddUXGR9w%J^mdimV^tZgREhq!71mFYH~$3p{%
zu?+5{6vdxo*dY8esJ%Enm1UdWc?*(1+T>s>2&VRO+7uOl6Bx3Gw#{qj4S9wEpP0yj
z+(y=fSx)8`lA+K#B2n(Nob^P+_v#$jR<{`&#ngfn_HERaPKcf+<O_*Ep>lDIv3-W(
zMv%h~^l>Bc>St7ar>`(W8Y*OTG5;2S+RQ%|zcf8BVtT9#uu$wtj#!^9IhB5Er6Kj!
z<!x9?rHV`Mgv9t!?-JShADmg!LQnyV$~Z<aLlE8MINgOa5;X-n$>HHQ4Ky#jzGP<J
zy-h2ntl=uzBcHoIz*%<opP(};I*)|Sbu&&g#OPN$GfUU+h`t(gm!J13c(`K(uMmW;
zrO*y;41PTlLQwwwd%GiS@{2yIW^|yc`u>|^J>K-NTJuy~_WX$KW<#8Y72s#N$NJdS
zi*|=c=DC#cn>ddB>Pz}`LWQ68C;1naS_CFca(|n?&bDh!l@XvX)M>z{d^bw#&MK(M
zNV@(MOuZ8156a9|PJke^r~Z<RM}XlhSs^rtrd&icME~Fi#e*#~IW(@=AJ2EYm9e1@
z=9m$2yk5U6>o1Lmh17VG1ioDfXa;O3m&(Ve{|v#Jeb_aefzmvxa*L#2csZT^Ml`zG
zB;l!ashK5OK9`1vJ}}Wtz=sBU0K}|>w}fn*&ya?YGwB<2ewr!EkMrkgj!bQ2hp~ke
zVy)LN(OFM(x!*TW<_CpLjanvA&b)-696Zj1h(Vg%f~TR&E_2i$1-KAmls5pQbYl4t
z6HeVypcif5Gx8n)waS7z0qM&(svM()J{?cu0vkBVEv{_F;AD#PJyWHO0lEw`wwN5b
zTph5;xvm>P%r!YSq)xzYIPS|sHQdta9&7(usSaVHz`LyjNSLu~i8_04TAv7W0%k1c
zOS7^<zR|jbk7CX5${vPDTvH2T(MpRq0((QY#sR+bqX>FNZmvxC(O7sqSzQhrx?Ny1
zUAzEzhG0%wzm@6qcxq}X$b_<lfY#4E<Uf2ACg3Bb?%(ANy*oPRJ-Y2k1~Iv#q&Pta
zO(?Fa(Bc<+zd&EDo;$eYb^^6NE<ZV=nRSLX<`+vZfCZTNhqXl)f|mycGcBp?OVxd5
zuZG$)Qbz+HxzhzY#+gHu6^4}$d1W2lqU8@x{KXN53xiPLU{mG@VL>Ad<}{mwuoa{b
z%h9t4^%3~X|4fJxhUh?*=_<}+A0`<N8doU-Isl~CfUV?YylWau_Z9f-EgsL#Y;UcZ
zaQ+->_8bWJ(Zdyvb|Bu2!HkGVJxvkSjt?y0(g(jbrT+U`k`?l1q!k@yt<1w;dRF?I
zZNH2!Lscx({}mX`2T8idc5;5W2ESs{*Oj~Bb=mo!zIIHV>OGEM9G3UFDCr%2k5$G$
zAzd51HJO*y+gbBe+QvTVQrgMkRPo{~tNhH~KkpWDzA?Mk!Q0<Jl_EnP>IvK;oD`>x
z;&4f~T5|;I!Zj>!S3EMesrRLXf)UdMkSUZ&UYe)_I!aS~)J0;CAu*M4Q=EP5DQ@#D
z2|4+SREORAWa9R-wVNdz`ACv?Z!8|n@J!D)*1Jq(>>(g%0^-xRsn9rX+Q~K%F?c%D
zo41PK;Z$676Z&#Xg3-W4k1e5{Qd#dksBYUsjLn8*d;hB{PK5R!q39SYD#pcf@E(*t
z=OWq1cnTMzF@J3`f`akTSO<F?26W*qKf{)uIsHmdJQjE^Hx)g+fP?tS`BInFg-)f!
zYCoyj5-9TC0M1#u|C)U=;6phF{W6;&kf|}J9DjrgsoBz9N*-*3MNOrK1(R0~wTxr?
zZ^WvB@i5x%M~Q;=<v_hE7X&XwsXr<JXTt_n%lUs?VTJ~%5|ifo!WPlgxRf@mhwZ$i
zgY(yR2DjWaL!Y1qWdUS}m%(J+vzq+%lK6wcCzyno9c!Z0qZNIcXxFIVW-9XtMmr3y
zP2dv_4sx>Fb9<wJ`O0sG_N1dh&iU<T4KnT-K7?4p$=Cp7LYZdMa31~W3o!4WZ6Gx%
z8KOkxBV=Y9tcj_cc%CWFUmhf9vBQCIZ7Qa6ia;DXE}tto%Pp~&pOWsxR*J<XcEOqG
z1kae1nxZJC2G%z32kA`$xLA2+YI18ne?|mJSHX#Ci&hUI6N3=JvcB__%Y)>9-l*u1
zwi(o==|w+rWZu4Z;R~RjxE6O_j?s4WqPJLRMPyT&P&Nh0N<z(e<b@$IH@$bPbe^LU
zbXgkcex#~NWp=aUl%*-c+>Dq;pCclzK~<dKzA|vLg#yFQ1pLRGi}39}WaDREHN%Yl
z3!osK`A_dFt3AMNwL!R8wX*u?qfqb2k}DP29Y<4#n{^am&SMJd?cT5XAcI(u4xUZ=
zjZNd&N@jH0C1`j+`-i=JV1kk9W{8}k3j&lC`0k-#$Y$sDW}4@IxXAuWtuJQ#-p@iD
z%66oo!fk2gl^&5e>Q&OD93ZY!C%Qb8c65ih<2~Fl8ZvgC3k_SM&0c-XHM7!d>rnOY
zn>_Q9NFdk?^O^f`<fbL8VWqa<06^o9z{uaF-<}rLbuawH%M_=Osn#x<X0zRoTG%rE
zR>QCuJ8Xm0m)-`q)Qp2+rMEuR^|Xp}cku0!ia_gm-)#ZG{4Z;H?nA0O3FD%_5o+%#
z=~p+w{C$F#w>`(0>sQ~$UP~5}c1hb)f}(h+0`CxR#=;(*gk5FcVP^vtlob)6j@7D$
zJzvo_U_i5p6Q{jqTw7d=m1vz@g(KIT?ca(|f%edwRaG*#DU7USMON}H{1;K#EjD1E
zxPs7g-(l+pZ~sFgcmzvX4zOfc51kKkQ^+XoB|fqkM$`OA+IQ1>NxUzc%}=Q_Z;4%4
z=%FjGdz3vDp;}dX1^cbC@!RWTl7rHqMvv}X!|oAhy1g<2umYxq=e+KzNWMkHQxKSW
z>jRGm$dGvin3DXvi!)yzMzT|nnAOP-(@E4fBA2$H3r~IN@s4T~2Gem~&|@*A$2L1k
zj=((nP4k$kNG21{E$|`Z86I%^VUQIw_V&uU5)!+g_yDNQm(XX}9jP_U@`DI`dWr5W
zl~14=d<Hcdla(Y|rl2<HbKo;xj81-!2(7T(S1$R%pQ$m8PhHiOr#XmyJOWDIti18x
zB?GcWoGX0$!qWD+ltvAb&k`}yyW2z$&(g4y3$V)$aOA)bRgrb0B+#}WO&8--qG;Sf
zc(w38WFRxdmS!Q&XrK4_CiebqP{<!r!BO`qkR~MVc&u)h--}CXA@qL?nqD{OO{>d0
zgZz?WFWP<WT%%579GU)gsx~+UYe+PHfjd1LgJwavux~d=1Ha|{-$gI~Y%B*MMw;z}
zJk3KdjxGQ)aFxgMlR8)&YE`n$C;=S$h6ePMo%H$~FtdxWVI@ms-h})_K;&g9KUrOr
zvi%(ceOENVpmc&(=e;nDi2R~A?;#NMJi5%QY#Dg9p?oqwHfPOu9oiVlo}6PxG{~Nx
zUAOG`qJ(H%uISxq-$?p#1$7wyS1a|`{>rU^9q!w!(o1#JS~GyOKdKoN;WXq}&IAW2
zzXdc+OaRgoiio~lI76(RN{ILe$G0|qJd_dbFnfPjR<Qvjebl>SZD3Z$+5N)_`isv<
zJUtZs7>n{iGfEc5Y&wRnIp~<#R&as5Ilaj9f9Y#$FNcu$Ad?GjiKtCIMTm&Q-3e-!
z)GFA{&Ya;?8;_2K>zn<OHc-mBcpXukqnX+%*cV1>hV3{*x~}#UB+IL`mJAt1-mGcV
zaHnH6U#WZv;K)`y<c{HvhoS6=5_%G0Z#8$l@uXhH5BOh{L)DtRa+vM(c-+@uq6m-x
zQX5H=a-DH5E<A8aG&BSAn5_M<bv1W12Df0KmE6CFoypD}Xb`$c(VLjH&XKc+a_4V{
zlppkuz4(*X8c5=Zg3D^A?`vOaA`y<vl$(nkUN~E9`h;zj6FuUz=Bx8fX>rkdS#)UT
zS+uu4%~d%lKRH6nN>Kn&Gikbv?kf2vak{%Z8(vZzPebG%4A9`CFO41<W>8`ZE};`z
z)uN#BFzJ!ZZ;`XXLcsX{m=8moWVSH{*&^qA9NZx#4F@j@LJWLgIl-=3m7Dr_T+M==
zXJK0jDnlm!RVPs{3N1~FG1pSIJb~!#f;37Ra%%!T0K4r#&?(!Q1&pf~!uNc*ZKDAa
zR82Wri&k>EfPvD*!M}~yH<(Zq@L_8zSWy@6LltnNFx2iNKzs1>+W}A~?Itgp8})B|
z{S(X{dR-tSUhK<FA@Q-I%+ncbg5FA!(C*NIK9>kHr%bsz1BR5&El)2=0fn!})Y()s
zZ2XF}mO;UGjv*t%t?#rgpZ6m`-p0%Vc=7VEN@2iqVx`CmS=)zb3jGMyI^nPsFM-K5
zqwcSy*PLv$8?}Wma25kw<Xq!NW3li*?}U`B^f07&>7}0-ssdkA@bITtG#ad>9Swgb
z(Jpa>c<J9ZXT@y7Y@IJIBEg*jZ8;L{3u)Pn!E*}z+!=r%v;dZ#{5lZqCU4G&Tp*My
zzlooe1c%fb9F<EPN*3MFt5?6KK>{bAtX5jNWS+^1Vo?jIUz+-mwf@5Mj7>!vwe;ko
z9HpNe0Ch3hGA_`W|HZ)Nv<GJTLb3%KP}2FL7Xe}H2C3JY3!}f>%m(<`JTljoUPndM
zXYVD(caXM4aj&HQ=SV1dBr;-+olY)_2BX{O!6?de;2y_s0Sk!FT{D_&i|=adh**#Z
z=kq4P-6NSnS@^@m?-p_lfUaE2eQ|b<<@Hl@f|qTM;nBfRlax;@5k<vt>M&XknC29<
z7@J=f&K11c%T95}&U*J%MktvN%20T&pA$(9p!ly4wG{G=KQhS?81=a$#j`2Ll|_3e
z+kJpe;&=LU{Qaew+dP!dOobfd`wYr~N_PbKbQJZuyc+?N#iw9k0kb<Jr|1<=d!gDU
zTqIrKK>{PZPbL~ZRJ3U|#w;l8Mo|5^&sjkeu5P428H-D1CQOd6kfM%GuE=j?kex##
zBur!f?>E!x&Lm_xC}Dd7!C2vb(TKH8xPSLzI;bE7SU0Y?)XVOk3>0gb_OR>1W;I2d
zR+mcbYmiNDGdnz2E9K~?%dbW-SVLtZ#+Z7=aR=`HplVG<wrL9|5=82P2-Tc~L6TiN
z18)1^&#7ddSEZ#N<s_q6O+W{cvN|XALOmjlVB1I0fuD9FjZ!b2`8{cy8D3!Hijqc<
zc-;MW9QaHN6v1Gea+P{b&=NiHFTb^q?flNdTU5Pbdp*+v*r1GK>D+Qr!D#t~{4o3e
zf!uFv&8>?r3mMJmOJavidwxe4fB4m!_f}G(9B8JdM>qBGd`V?NxSNp$133C$?1>w4
zy-CqS^SXcT<lnb%wMmwDyg51cS5C$sN=!^t`{x+i6#;K0Ly@itIlA0fVi&aN)sb<;
z_fQ-|c#{#{G|czrK2<!l<XU`z8!)@!J-T~9&<t}!5ZXuq%+Jm>jcRPGP}gq3@v@wh
zr>{}+G7R&zHuFL))ZV(hYH}lyp3z&fpygV!c#&0)bwq2sO_mCXYs!UT*KL=&rN|M4
z{WnxGv(co$MTgKQka6-!4^btj=wJy`tfozrAPqQfx1>WB$jum<xu36RdozGQiDcC7
zrtMICWi)N|)1q6m3*<{jXOuFBuUkGI;Gt?YGM1c!0}~4iSdA%4#gFlu$i}}I=u`tM
z3O2>%TszZLVBq&QqYHoUY5{p4J<F)}Z(3{WWwCL?JiV}KBGnqj0#vGvgCJ+&LWI?~
zNe^3pzI_A~OF-txo0ix+ps|l{rx$5DDT>O6$+u0!G=v+ty9?++t=)yfvVXS1`y4}#
zId4@ngf>dzk0-<|;W%E($Q8i`c620lUJs~u^fg`V{qH(ga0Q}m04`q}?2|R8LFoVP
zI8+0PajLLZd|j>u#Ia0|*>m2qQGj72ooUXcp`|`s?zIAW%i%0sJ;tB*r4P|GSCifx
zDyx?yoeP;u{PQQ1=I-xA4xn$`+R4PFmh-&BQsjuu3LL$A;geu(>{G%%JW0nG6^bs2
z4{`f}^EeJE$%V18`Ia!cZ<MIE-3J@FxHK97kUMR#i)UTVLQcb<1sKNDBZyQCf~<@v
zM|vVL)*bHf8`(F`t#37x(;@A?#J=e2)SNz-6%#O{>jW?!jfoqMMl<lNo@AR{8|3s$
zZ`FA7k>)#@{f*W&YIZd2H;YH|WR>h;81n%k5#H`wZ5d6p%&PeG{r`qrB9U?r>3Gon
zxxfzL2n=J=Qrg|^pEU?IzDnf9v7VNjT7Sj64cT?vyxl~2m(w|nZpIdh3p{0z<bMHO
z)mlEtVC)k1bP^7!^HRDAmf04O3AMBjMi<F#Q%DAUO0cc@b34~di-mdzv~`=uW$}y|
z1B(%sU*XeAJzuuvHBVON|NfM2T_zo^!!A89hZH*<SvmmaE~~340FQ2FzF&p@O4z!n
zI-aBsz)btVoLCZGRKE?`1Wjz+Ri)qUS;00`0u^7yBuP;jws(h;{nVVG<dpML6ABsw
zymD!mleGLEtaXpkj&vYz0u(&n8WFyGlDK0YRDgahJ4ZZ6EDsl;_(GHW{L~U?L4V>o
zP0SM<v;lV!^eKnhAx3<yU}Y-Ja*skoMExPxFLSp(3Z2(iBLj<?=RjCD(@bRbXaw+C
z<}yR}RSOeKE?+Z`I%K*2q5zhR!%Cw-QcvIrFn&CO*%*CX8)=Ts$7jmE2Igj%s(FXu
z4umj3yfY|=;<(H(<gY#>2{E+gKIl3<zar5}xHL312##^ltot?LL&X0^8j$uORJM7m
z$~#+q;*O~_v5e0Ep$!$h9t)8qZn!&j13G#hn&xvf6169>%8-q|j<dHiO@Z+@TQO7!
z%bP^cu&WDK*2+8G(dV2FR3~xWF#F3LK#K7OZvVJcG|DA{wayn+eGjDd$5wa2Y}pZp
z3#w6U-V8vWjK2lAMihNlmle{Y`HD>jR4Nrp<7*qKZktnAvzcI`XEfi$DL`ed)KlW%
z6y%#tBZi>RwcQB#SUu<B@#r~@e4_Og1voUG2<P_g0RO^8$?T-zy<?so2^lBMz7k-W
zvA}xX8(=%S;|o0zbJD9KI(bRFp&DXYavZ^8P>#92EHN$>O~MzbFTgxa{&2_YL25?V
z-$pGTQj_XvILjGcb<DHxp}eJEXU=*#8r-2g`}`j&*Blhch&Zr%#h<e9w;%I%nn(Yp
ziIjERRi5MFwDz1_qLrYrRKnmF8NK2cY!AwkB$8=l^X`HvCX4V=Rwli@y<WV4McYlM
zj5$Ig*_b=Qy?C7F;<}J_mCvn6RJQBVdDyafH}_p!Za~FV^Q)aEvB?LwF%(BG$9ryT
z8Lf!Mi{hzhj$Sk@l5R$}MP9yXC&Sj94uJArY7FM&byKrzPO{xPKFOcp$;}No;TJko
z3nTy<CR`-q_XLz!lG>Q(-9*fwYTSq_%O7YDZA}DV9#oy#64ze<zS+U);*QNX?)lkq
zn4jmZNgbPbtjZStcc}N&3hHNGJO0m(?j_HJ$E07i$P~*e85q_C>k^U!8B<om*bfx+
zXdzJ;wj~~px_f-87Sw)!=~I+5dusA9s<7+?X{pmVcV#Eyjpbyu$BQ4miCl)=WCA+P
zq)nGHJ5-U^d^l;U{yf8Uiigsc9sqzFT<`~#`Khi5v{q9bV=JjbC88a@>8J{{OW3t3
zFKj4X?ARDI)yj{UkvsA5qIro`A&Y?buZ<ef;US$%UQKh5Nc1iwL7RlM0Ea6Az4dl4
zZR;)xNDj=lh_bM9xKMANR;i>DyvEKbmVUlmU!oGrLE7M1R$X1D2`ozzdmiPq-c-ur
z_$UTuYY6O+&Cu|7toIK)l?~oiIlM%a+3o};1dy^~^&y&2!M3gV%NV6-1d2TF*yjrp
zo3)#QbJ@{s0W_X@vUgI^;QXDxoGfgt+h1Klv>EdeSt#j6w=M*AZ$`=(HD);`E@c43
zC|-v(3t~3$Q30Z}q<2Xr4rwG2qJO!BGCeobZ~qCjQDEqT)qzi`K-UE>);~lV=^cZ+
z%e=y>m)iYOD$jUeB~{Kk9-BbHwB!Y-uMhzmxiyZ{i}5vlc}gfeCFc|&(xzHTdfeee
zA}+$(?i1xptENzI0nm68)(hyq$|*~1)6#cP-=}wdinbSUI2v!PSDo~-?C7tw1G5_o
zLyU*Hs|~h^3<oJ6PcXF7{jr+G&y10MHENd945H`J82_i+CT{-TqX;4HkRe&#l49AC
zLZebTwn_^T^^FXKCV9;lILT~#J=_cVH;t(<3Uon3Z^`)IOb<o)P>GtJhou@tSQ%QS
z5f(e`fSYf<4jq+<En;e|hzMwjWu)r)i({6gX;5S;;LqS`t~2>ad=J4j1$?}=FTLg`
zeJ=A{k?V5{G-X_he#);9<d||prvAK17<|nNYL>UyAOVD!)F7j<AhAcvfy7_VjMS7Y
zN$)FI>|bUV7iTA>G3Bu(X6tLJhG%v1OxJ6Ok=2`17C<XWE>%AvF6a9Q)BGhq(4Cv`
zw5We{3g1J`1VJ4lf}qzwwSlxiKEUU2aTwuE0h)}nFmG*1&ht{`^^^`@dPq${6pHim
zK34YKxeyX_qTfe8Hp=UMIO6riDbDv|_GkVAVdwu=VmgsF`%|*(#OTK|j~Y~uZfYlr
z279J_XVGBsJ0iOi0m-wEQcpN-lQ*|8k}}1?9J8m6Ii@YdizeRWXP-Kb;nC&ens))(
z7vI@2Y0$2TN}}p++{@>*^1S~RiH0Vb@*g&>HG1_||26q+YS~`Ray8@Uki$DjqN0pq
zY2}B+7x=L7Dcm2IJFR^G2@Nb#af`f-seN0#6Zs9~Z5Gju7$DM}c+BQVVVYmr^H;-l
z4Qj7pH5CxznVMBIKqA(}$HS&z>ZytqJjVG>G@|>Jr{AcHoEkis%l55^0l69b)=5sG
ztPoOKTkb!_Pu->fTLWP)>1>i3M2!MKE=iM^23yUGL_tHp{@`BVS$$Je%GdWN;G^&r
z0l)WOp1%=O-dzI(8S^4;zL*kPRW?U+C1Z1kR=f?CV8{ZDLQUGlhF{|R5vQ@36EiDg
z8w516R2G0irLCp_lG5J>1e^58>=FeVu!;CYngRoQN}nz)VtBYU6C@HE{BE<Uqh8zX
z|DeJv@UpOHjD-ba!k?Zu{&Wr>DXPZ@xPBVA+}=&VBD>vYuh+9H<L5D}QOm;o;Ge?0
znnXC%9TXB8>7H`PC8B5mWP4XdeP%K!Sx`M+v5>#Ke%;3faL&8vQRUvhQxnv)!&3v3
zC5mVf(qn*B*AUT`(F<>m((<<JGhZ*SrouKTEW!l-K(lcIkFhA1doq-WhX9{DXh_PI
zrP5T>3_!i@EYX2I=&{Z|7DdIS*Fs@dElvU^Y)8k=hQ%He_>?Ca_Yt%@d1Ml>!%vfQ
z*jnP>hJZeMHP178G2%|Lc2RGKpO3-~k|K*YwR-CZac>gc)^Rud&Zkc6oe<h)|7VN_
ztU=r7`m~STa}(;_R|gN0z1@M2#6M8Pyqh{#R%ZVH?smhxPphNX7&3{(TT-KJ>N|VH
z4kBFl<Fw~3x0*`6@m7sDpa&o+Q`inxhW6Q1GUhe@4@drbKh12lh##U?sjLv$Au_vT
zVVVYlHBu?}tM>|46gu;m*OGP84ou;CxR(<HW(pX~$$Di)`^EZT;<)d}GE2l};qbjQ
zcGy@?&^>Z`Omu+KMYw~hWUSt~Fwu*74Zq~{=`(Y@l85r3jg(Q23M#t1M*=unO=}1V
z^cL;+j8keiywrrEIj61y<A|SR#Hjw!W>^WUw;+Bo7Nx*-n;W|L8$Dkm)!M@w@T+3d
zqGat)za*A+dv1!T;&FR}0s<kgz{0esOTGq2>C3^Y*JS7+!Sgq=Q1P)E*~2!;3A^g%
zV-@ybff-tP1!R&Y7oslPob2v;c#L%beIjbGI8;3%%=E(l!{Y^wU2vJ(%Q36tPP-Yw
zc1%$I%u0ym^`1OOosW)L>VdP_2%cR)p~m{06{|Nm<^gDl@BgzOda${J`LdcAu=ln;
zu7jcWCxDq3%!(awtbB$=8OO;fd4q^Ri#Eg#yfM@+jh2TdnyyB^R%(?uR)o$i^j+*K
zLen5xpEqgEWz%eq_qz27ZcqkUkIOL;i4NJc9E2b1s3|A!vfExFn|}PDzuc4xoGzq<
z=6FZzAE&zX0r!rxXn01(@<WU7EN7&}ZJM$X<2?T9Lhl~xBp9CPMuLmt6vV-<CftCx
z7+c)Q3oh<CvWkyLmltK|s#PX@MO&A(I6+yJ2dw9)Z=Fd~kvSxAi*p^s<R+No%k)#q
z@SnkK_-Nx*$=b<`rf9H`c!64%V#qO2rmnCJ>q?&6uQYWeMqt4}_}xLr-(11&s=9ai
zkEfN<B9PuQ9%Rm~!0rc><VpGb6*mpcUU^v9LFg0j@`TuleWrFhku3@{OuWabTu5!K
zoJRlQ9^H7Ci$x8U0BWd)>e0jXHEBJ46-?)2j?60bY2smxWPcus&xmk)2s!a8gb@n!
zQMVx~X{J%5N-^TaPu{~%K)D-&((19G2kUPN_{P6Xu!#t5c@SgIi~pAMXg%75Nq|{4
zt9}d_mpoult&gB9)qt1kp?wWJjlnyb-nXR^7yw(49M37cKWWM49wa4AV71>HLTa6r
zg(K}MLPje~x{Kw}nfHzwknDNRZ+%qO@cuf`CY9WkgC$AtV&goODROSDGpu&3>uG3~
z-edgBwT-5gPNZYvai8s&z5TdV*OJ7!O#vEEhfre6=$DaV>JqKRz5tof8@E`~tPz1&
z>o47sbd?-NOU1l^fzf~P4ZLiu##p1-PHdS1%iG{vQgq2t4yRm&D-d1va1mk;0}yOs
z6z;Z+c-pQ+dd-0EST04@^G}I-WEQCmz;rcgPRc~c?N(#brj{`zxd0luSqh#ZI#*Z~
zqNk%7A3&LLpQd31r`23V`m_iNQNoAluTj7?t;(pjekMe}PN~$~S&clnshy~AVcMLs
z=-yd6_Z>CW{l>+wJc)K8*PZ>c-y(q2cFV7uPyvx}Us1%yxcN>CptOf}2N|Tp9HkNb
z<o_bkL(4Ujz_8n5puVx6*90zrizni<&nqix(%Bgo+xlh?fxN6I`1WT2Q|Opszo}Qr
zJ;{pu!=5rm@uK~MMJ06igdee4Bde%v6s5I7D`p#_&kaSJL0d#;;J8`YA{;{ptecbC
zHc9Pngln?3oU4?}N+oa>d9^8B6aoxA&v{-oGxn!nJs;#!D{wbkK1B;af~tQ94F0FZ
z;GGsa{5)A7MI^nqfkdNGwNblhy9vM1CsQOx`c57;8Tf8)GL)5>4V@S#q$#~U(ZakO
zkg)AQ#S`ar&5xTQ{gk*5nt?;z?Vu@ktx5o9D40O#FxpV9NdY|5TWt&d;d^Jz6|{v9
z?&*)2Sk2cgohqvLM5X;}tmYoE<iF#~oZfm=PpYWfd{LKOt_FA1r}%$yF9o6aJi}7_
z)I@k*Ap0aX^(0eMrQ+0TW2?(Q{9Q=m$>z>hnTjr6-cL8pLeG)oo!Erm1P||c%^#22
zlK~33kKZ})8-ozH-d*Skc}b&A7s2e@;&DfN(GXHK8Nr9Cst=YeIP8!7sWA%b)NbNq
z2qOV&%4osutmP2^ksv=|ppl(O*-jO{7)c$o6N2~*owKiF?avK?TikK4Ex<ZrN$8zF
zmvPrjfa9BzBnUX|HA~4i-8Nuwa%x{D2C)9fMWc$B-7)XP)nKIy;|J(eJ$^X@8168n
zJKKvtaw4%4X(^tRvkT%d>E9&)A<^UR!K_K{)?jQoo+Cikq$Tr+4XVljLc8n2UP|yJ
zE;$=V%NwH0cdPA661y3gyH8l%n~E^e5AB(fn%SQa!(g!jtDng~qa21I=)4ri%*OMi
z@=ZysTf}NMC(f9LVuwo4-Uv=9)nD6G@OP$5k?XoThpdux#!A0U6n>|bAVaKML0&wq
z8iNmmc*m}EMHU}(G4i9^G?R0|yKrXM(*uUC{b$*$DCe&G=W&crlNBIFpv=hRGD~Vs

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v
new file mode 100644
index 0000000000000000000000000000000000000000..ffdf3829255b474bf1357498105a9c7e3dd277b3
GIT binary patch
literal 22368
zcmV(rK<>Yb6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjz2xSYmn@<NY>G_*G;3G7lFN))7
zpFE7%-^q+~Il!(u&R>zjCvD4Nh3+Q9qxW5q_(iMo+AiN+++1svTea;;jlto2J9}Te
z)H8#Ek;km<`VHw4-Y0C~o_dO7Cb;WMlR{gnYOb!|#BBGM9|{<)iD;_PWZk7x^1X|d
zQ`dr{-8~&g)rRxgcOV(g+KCh2N2;^rV+8kGLohM5;|Sf7m=3D;9X?m>)RNY;npavR
zdvgc2I9&F2ox+%|08pNOMZ)%}pR;|fOL@BJ(yML<ajhdH5ghoSTpnI0ko+8L+?EDj
zY(@?`qvJV5;gZ{Y1X40o>@@B_Y{bVlc@;`;RzT&$3CQ)XIDvlZ)7OIYS!3036{W;g
z;9?B`be=DtQW`)ZrfUBjVb<wFl=;~&ss>6c-7KP@iPHR7t0U%9{9n{V0Psa|r^A3o
zryi(zTnOc=df*)z#k}>@ag!5=RrvMRKdjLSiA}w#P3rQ44VpfHda!>C)qLjSg!7&B
z5o6phC8&;CLs+1=eCj0~hM<IYoHVUS>o*+$I=M2s*eI*to#gBd7OVKa&^TjO*uM0g
zQ>TW7d{(3EW}r7|U25wyf?Lr3@Ph~v<{J(vM4C-?%nCmvL0<x6n>X0aGo>cl=qqXe
zRYg_BB04Ys-?YxO9oBiPnNKe_1J?ujCgm$5>fbynBzFM{p&=}!nfN_OsA!O+TY^t*
zQRs+SRUC}XKeM`2KI5$9IN~E9@Aj|XK{*pmZyoKQZ{B^QpK={vzOnHX?z_HfTa2Zk
zPsy_qO1f)i$uD881iLP>G&#CQ@Nlwll~LUKQs6xSWs4p?i%(O~bbYcuRN6y!e-#c%
zPtneznV4Ko)dD_QlG0%V%?rw)rQd!<C>HJ*hgrS?O`en2+<b+Qv;0Zm8dH=TmsYR_
zhPFG>wBrMr^R=%U?IDIGul&H(1HmjVV(rHF$l>D3gPrt<1K=@6cZLU?dpV?$Sd|_Z
zDSE&q-<T4O8zL;$iPKx>VA8Sy9o58c>x9R%J%HC6#9Xua$J>FUwBEv3RlRdY2d|R<
z#dY2>x);;8dxCOyf8XApL}IbL=PQg%-25PZ<L}F76qjn=fRGUfSw}6m94`Y)3WL9+
zG@NV9_WUC2ETVlsS9C@QZT%f>D`&?v%rlf*Kh5xsh+EGnVR7S`oow?shzHb8!5$sS
z()vO(bfZ3?@jbIXC;cs8z*m*My(k5XW;$7IEKLjIISf+#v1Z~PXSw{2{+l65^RYYO
zrhI8)QSzf<inK^pHofAPf=uN+o1fJ*5%3MFK6?VRb?nl^O)cA(MSCLJTqr`e=G|i2
zR;fsH+oDhSKUtf>?cn_ijWf`7$uJFD#Ye%0aTh{^t{xxiW?s4iXw?z81qb{L!>D}J
z5BppcIrIBkzI8(FXPMW>|KnZs8SZeb04InBfk<undC(3@V_Ohl-`%bc3t32}Taep!
zSIHUJVe`ltO4}We23pG4-biG~QzRdjGh(ZeCdnYcoWrccO};VTa%k{4wy?4v3y{9C
zNxHx@cPY-!{PMmU>YbrVX3VBa4!O#)kugL`-=N>RDFsP8;%RXa2BbQXR|&x)*vtd^
zc6-l$rD4C*zM~);fZsG8n^tioxH73hGshQhGzX?Qqz&lydJsDxdqJ4^9NfsJi+)9N
z2d%cgCdTH{b)7-Ph~4sI^=Brnv;SQMZvkv!EF}fpm$V17^SC$sHqsPY_3bqx!(Atg
zqAEFndQ)S`56ngav6BovOwtxlyY{Ko4Xa5_hZ1;8vheE#b2k)XKJ0RqO94oR4$0z<
z#@9&$*5Kj=y^jix<33k)g8s1sjgbU5IK2s@ksQju{S?9tpca|j&&*I!lP%rU>y~-_
zFI7X{O+a!Y%3QNo7r1Fk<nf@`_!1SZxxH}ziX&9pQ}(XOFLIV1o=ar<)nlms0^a;s
ztV!W!{%=GqC*jOWZ-XHh2q`Lq!B+`cb#}zUf7todaQ4Y21-5Gt`_AZs)z98}$QVd_
zNim3*PTYd|tR20WP05i#3r(g=+ddfTL~$DSZ-}ekDhS3Kdu5qGs4C$OjGIR;hmnJD
z#X(rx6nup${gm3t%GcCjytZG85qwC@Kuu;sdTXg=QMa&~NqRVQhz9ImEx6RVzA=z^
z7BnmujUyPA^OG~=mIwp$fTx=ir5&@8E8@2&*k;a&CeAgLB9GyX8ICXtN8-X}U%r_I
zpT0B|yzj>QGF1Xfu~Rkq%I%4QlKDyg6Ca*`lOU#s_SC41){UYon*Wx2gXvB+4#33S
zQ(UoNj{95f$!ktxnufXFxocA=Ng>?J!H@xOsjB67U7as8IB&jZRZ6q#=W86NL!Ih{
zCqe?%{*a6;A1(h>sR0}k2uz>t>RS3qc*_bN^=Jg}UWaq6yr3NV<hx)pewP$exe`~*
zJ7EK9U?pOrV^cla7T@ESH9o{ep&T>iy`)^2vXnXGe^U?8N|sKd*b>*f?|ja`EAB0h
zjIqy+AT>_VBEJ1N8Rz6vk(?0oBz7D7KY=k+P$(qO&9z{eB^%Uv&xCk%`_4)vk3m~)
zqn0gL+&XO7^#5G(_Q86Y`<^Ss4tVI^mm<>W@sRp{t$vpBTifO-<Ut`<Pef4CmII61
zJft|o-;=mZ#e}jMvvmGW=ZRgu^jJvSbJ6KXgOBj*GvOd(C$}^5tsRfhrN}%ApuSh`
z=wS-(jY-1~*y}Iub;La;MG!#a?(-nhI*Np$vOX#SGq*#<Z&)cNYfdrVL%0>ZZ{By@
z=={pQox~>6!*wn`yvAfqF&0J!A014r9P05)3?=AA+Pjq9tPm?kzqm~WT`ThsH)s9r
zeh0Sm*^QR^7M_c`Yt~glCvG_Mi}TG_TNEMJ!ue`I)*_V$0f#+N)ArezSMmGw%&EwA
zi7=6-Dd)3dKJ_=>R+>Eaf@x#n3qQehvHEH=PT}|a-!FGBuyEObmc!I6fv*%Kg3c3N
zP_Mf1G4?;3916hnKd|jq768UU=*(d3)|DX_*gPoR%}{~8Zms)TF+yES`mh)e9hH(R
z7I_%OZDNdYONG5`1-#VF6C!Q{C#L~4hJoVUR7zSFowLRV%#FqeXp*bzpy_`8V7BfV
z#MalU@l52oi<2ahPfHpKWS((1bTI{Cw19h(C0QfaE7d`JH7diJ>?YF<05-;=#xZ*q
zTzI6f#_8+Y6yvOL*$HBoy#Q5F69z(8D+=GYyvLUM^#^q(QkkKSJ1yn5*i#Vf<9YOG
z>LD+($d8F=q{DR$7fst8$5KJ3ADj~=D`?n@hgJ9ho{oSlf?8V6DEs9)%^8X3?L9Y$
zfDI#KVUCq}YtC;VC(v3*2E#YIqOE&Lju#>{rkP@&dyo7M_+>wg3&-X@61&GQPD^F^
zg@XjkelO(nIn6w}d|qwdHW%oFt2L4EYO$Cxm>nsqOhqYnC8J*14`s?)Pg<vct2?Ri
zTnh(;cXvOqqT+{KV}!Gga$MlapWtEj`~m@)1JCo&F5+`|=Vu`K^u{5>DL*sU%*gl<
zN;c7vA@muuzLx&(#cOiTVxMF4+9^Ww9XE<b><#g~gpTHp?oL<NXQb!$B(22vP|XDi
z8jQx!H97zVl8ssdQr4|sjpe0}`xR!(fdZ5DXT}-GRfI@fHNnM)crV+J>wq<Awn8Rt
z2QC{P-lZkX(;zswLecSTk-oTqEk>pp$fF8&h!ri6g$Vtvd})4WDu*6X3JqCkD{?X9
zN+XBo#@p$fqA6AHV<0(#YadY({hFq8TJ^&sic0t4G<T@AQuv_JISbUk1|%$u`VJvj
zY=OkBr2K`B4{8HZqXu?nAXq_5O<6?GtJGBr%UeixM~=bm)~EdlR{Rv>OdYF;CPQ{c
zhSoF30&xsfZLcHz$>^L*gQ#h7CX1>Eej>+%8c0#0Oj395`YUr?f<zZxbdGBqqUIe2
z9B&J#)DUQE&|<?()=}3)=4LJ@AAg&&haZaj+zRj>yy3MxVj67xWmlZyS(TS`vjGc%
z<-`DXsP^3--~7T<nW2-O!Ag8&Yg}NdywvKxM)7)t5(4!Y#Api!f}})1lql*$J^0b`
z1p`Z3l1k~^x#T!)?>tfXSg2=G3r|rn!T@?+(`_sRX6QZe)6fvjOQ}f>9}E!DMliy0
zOt%NA^0MRS<ni6#L`(sCC*|g$TW6*uX(jE9fZy+&fBw&ax|8)czHV!e*IgkcEHCv-
zS#G1cH<QWxVS5Aa!)JwBFnsPkbYGqQ6dtlk>~=<~&gisFP8dt@M%(pY%!l&chts5e
zr#5EXc~^J!cx>$oCcJ2skbW859vgd!g?7)`m}^-wCyGZUb%KFKEDm@Y#O%jM^9)0z
zKrMlC(a-~P9x}ZJ=KuaI=1(?!Ey^qK4~DE@p$g8sB!n@%&}-eFg6gAy@huXC3<{ue
zC50Z~_3Uwu52%aMdU89N;|^6k?pj@mrcbY5;gu(87ott~xclW8{G8K488fOF0mQQ!
zab|w~3?)b*Had-S4d=!qfkm5*vqDZZcH|Mk^ACkflPOufO`f{zIASQA0V&IOaX!m<
zuPxt;jCZ$nw8M!jrFbLK6*^BrZM=o?R-%&;L6N~HWEKCxiq5ztE3s#7sgMNRq3f<(
zvJCVV2pv9m@OSE3Jm(UBCoUlOfkG<Z_qXweokfP3oO#Jk?mqYu(T*d&6ALiZ172Dq
ziWLu`lFb;RULbk*B}ZMw_-Pg@cd}w|htdwfJ`~Y=ilw-Vg6=nfvuCr|bVI9b$Q@!$
zmC93|>*iE`2%$*OJ7gx_BAH27(NWatoUUq!mZH@cQ@Ubwm<o*?v8S?`Mt*JhYb_)u
zzq0Z3iDoKBWcc={VS<3kam$k^n%J9X#9Z%|w2ZKX*`&_f>vEl=ycP^xw5ui9oZ<dT
z-xn>M1Q}#UR|X`e@xD|uMazHZ4SlS&J<s<(Mh$<4w)*PnfKbMWF0J@LgTXR<?ZTn6
zvmN?T>qoT?@)@O5A9oaY*#pQ(adLfBQIXuTE+0SX>^7#rIuo)$SQ8PmyN!)h3um}}
z(s1`2!N;4*(hm=Z!eNE@TzJzafvq64y30c317Fc(CSsMyfs`IlXq}%W<N3wl_Q2#S
z!}B_;UFo>qIOk{#i6&r2_`D-%wj~l@qJN~&_QfC!6q<mg(rlIBq8d`CwA_d$-RAH#
z@Kf-?_7o^06<?m(NOCbGA1B-vOb->es;2YT)Ime=Cl_hE{)-)i+4RKAa2JhbUjEPN
zJ}37MAYfZqu_6(7c@wl90$%VsIAsmVR43UT!aMnAQxJ0lUBP#acP9^+C8U|aez2rT
zY}q1~YYg!rzG*DR1G@=Xa|SI9i!{(P;pgWjq!5qL-j1>gnNHB?Lp2HtMa5p`!OK`S
z6JupEC_qI1zh7}BW&JG03enTRS9(~Tkss{h|0OLzT`U<bzDn-+WhXX2k3};I(^S<N
zELBn33gJR>u~|vaO&5GU>z>@J+U)30r>ozeVYmZr%a%PH3BkQ<cZLFjZvmX0@}QjZ
zd0yTL?M!8UP^t(!zqa)dV%Ym%n|NEB@XH@HFP4|_tzu)NXaBG^I_|P3n;@e#I8V-!
z(%8@wlG3UtY>BwcNF~v>v+7Tp4VwPWj6si{xN`$^^)Cygl={rCGotZ6E#YBD==Xvf
zLcjj?dpLJC^N6bLnoD>n#|iODivl>u$>wlLj{d2RPX^1Wd0O7?+qSCGf2@cimlb?W
zhm-1X0v84U11o{GV!AqB#^)l<(E~-BYy?LUa9AOMjbF}d`fPZtE#m}?%MHcrM*M{q
z1vOgRK%G^WA4O|_67%XalMbd}4<G!;S@bnNyRP$k0l2;^I4S9T-$|RR0jG%P2s7pO
ziZEfM|N1G4?j<6mi~?gIBTJ(=38R5YxhyedASRQM+~KP}(%6ANKS^GHHRnQcRgI{1
zfHxXOIy2KHj&5=oVp?N;6@yvoX~W$5Tb{(Y8!RgI7afGMdq?>D41qLEm<sozX4Jno
zLu|F55^OktRpQteGtKl})+v3n_#e30FUr@n)>lbaVkgis5d%@1Cx`nez}k;>(ddxv
zdf9a8ifsg~$v-I)hCtkUx4^2%X5KgszQ<1<`1hdgnjI|9$H2ZfpQx&J@Q41xR9X%5
z2V+P0h-Y9AY_nI;B*uE+%y|06&a|kn<+hcd!Wa2qd9~LT^)P16mTGj%>r61WB{?Lf
z$=G*<R~dvpq!nBs4{436^2t%>G#=CjJHWox5Jb=WQOnm>jo`W7(I?RlPFid8o?->s
zGn%rmmYRnKCJOK6EDu%}xSs@kNIPW+Nzx^X>$hqx5X2+(>I&kpZBKHW!)Jw`;Ql(R
zr&oEv_^Ilf1V_z=hko=U=6N0|&{9OXQq;sd4U!%Q6)Uhz&hGm~CXa+-A%`RylD0<y
zr#xNmUfn4$6byj|+*ZSo^ibd`(qss(LIYWJqaR6$QI(>;Bf;*4+F#lG@e0VyQ8AF`
zjFvx0-j~0@XE#E36&qgp8$juUg&Vwi&h<bwEdum|B>!m8eJC?XIPl1(<QXyZiW~}}
zJ}Ak-GvWx52~-(R5>2A%#&_8dxbb*$#iM4?g969(IS{#zj#dflQRwM`DMIq)=z(>r
z?QIRb%Fp8V@Sm?o;rr%f@#I=A569bW2ikUSFky+>Aaz(j>%yN#N&Ey;@pN2N{uWwy
z+Pe%}S^FsAw5~-<NWbN&cMmpruJTi`rKV!4fElv;y)OU}BdpGH1}Sql@5r7hD5y#5
zQI`E`O3#yoo3NZq!0euqIz;OPZ!_qC@=-O%0*VvJ0-r_^#utPotFR4W9jYootsF1y
zj06LdVA|^>%-iTLzCX25k=)WR9Dl??ng;Gtyg$$;e@o?J+1?&?oQ-<Iyigz+Se<QF
zm9=Q8WFPeh-#@gH*XP|+;UvM-j5;TiFwE6Xkux;+!QIv!o1cT!=XSeL@!qDR0`mlo
zPRvn{*X%G8EEwt8q?}`Pn%3oROul+y7QGv<;J<hENox#o6_F*o9S@>5%2vnayHr-)
z$UqVv299qzlqF&i6*fZ3GJb9VNl94$6RH*HSSvWuS1&xP8U7Fy@fZ|A7Fm%bRVy3v
zn(+`mnP|dX=ey1DuGyG0D867)pwt+AZbBs&v%B<GT2!uAVi$NUfM#%A3jaDdevQDB
zS~<m4L(-CT@H%^X5b`<xh~x_zf0%bOQc}1vd1W?X3NxJVn`7!TMIh`oM3!rYuwwwn
zFMun^+I9-y%Z))W@EiaVeK{K`mYl@mJMG6SMEO03YIuo1+pSLd3;wg4B4=bnLnCB&
zk#8(=YHTd;637s!DSvk{k$xnaut8v;6>XN%e!vCq2^y6y>-Nl8$)szyr&v=TgC9hV
z2F&XT2o}o=c(7q-*T+Of${#YCZnq<bY)^FfgO4zrCfKgH@%H+hxP3VWX(2aofT_c<
zU$FJddN7b<A;@eS+;Sp`O|hs^|6#+)fcS5kWDFm;kb!g7Aq3?-)6amL!8P%Wk$`^!
z$Ctc2!g!hbdB3{*y!MRihLLHqQZ6yBg^Bjrm#eZl&B0th?o2RHu3=R_PrHf^L?)Ea
ztlo`MJbkoun^E;=#+>tDRpx6y58|syFfJQ|HS}hEcxRX#6a^g2_%|1f9rfQ@r)6*a
z*#enfXrY?&Ed<sSpqIN0DxYq>3c_$dsd76=MMkd2imk5gWY^%$EpN&Ft?jPJugeku
z-|OLqPka~e#1S?936}{utO5(*O6?Ud2pqx&LR1$qYy>{h1prCpmKcpGV>y(SQu$Zm
zcbg+fXpiO<J>+c-!`OLbkmy!Owj<Eph1jK9{oed8B2zcyyDJ<)Ead6*-9T(eLlpMq
z5>8wZ;GmGVWfx6dL-7JI{DKldc{l12e~b+nix+5g67fqs@P(72-(w=K`>DU1r>nzg
z`I9_JJlt|ggy{Ov#+w9lxu>R+g%w3)5h**k2F~KlUyOb(w9?+!l(-!G8QI|6Cwr79
z+<iEVnM$1guJ7<;YL4oEJY90TCY=SuebdH3-Da|vQ(p}ZQ><2!(39sLpfY;_w@;dL
zHc6DhZ52DU@QU{2f-sY2FlqA^lvr9HPp~0BtvpU`M8u}I=NidC5<$iEevT>>pZo{S
zEaPNo7JF!l2hcRID`IZ^!4Y5fMTeUz@Ll~w8)%;>^(_&f%&;@C;=YD6>`%_wymx2*
z+0eAnNM^N;j02)i=N`UYr;|scB##c}klAiSiYu#6JMkd1XUbzbKg}bBukvJU#iX^@
z^$Nda6|cIu<h0VP&D!b7lTI^QeU<cQ3d1tU+Vd{!j*X2*NkO#9N8p&7PbEjE52wxm
zloJ4Mb9$m_<hd2at`MZk@6XV~<P|Lv+$GYn-I0&D(zWCyVR6xR$~$;qN7_xFTr6+7
zBnfy^ThR{Z+RAffs@;GFp{gOC`N)AGqa>=9jFWzo+w&qaqTXwa%8x8d4Q|!3YrNG~
zR1u!yRC@TkVQ(azlx=UdT;gap=2Q?Fl4*6O#(P+qj#(mcFpR&Q)gjr+W})*!UcXbF
z=^**yYZBg&YkO#ui6bdMx5Ye``$~jgrAOrCRKa<Ti=WtD`?z+jhPEK`0(*}+A2XyE
zl71hgw3NOvSq*@0p>zti1FPN7Cin@!Ay7eD<=@V#%yl`3ymO_n{yZmNx1#Nb)8Ju3
z>#aA7*@Q8)iIa=;PQgrAFotUYS~#0`b*dnX?_rE@PR3_S)&e|Q6*vzk*7|JHJdtXi
zc%7pkTm%m-XEu^u<St)MBpKlQ^?<$JkwYA0w?<bN^A37#!yrq^Z>ztV@P{>&*g37=
zMB@;<lK}Rs$i~Ht?OaJP4O4GEM_hU8$^QJkPdf%=<9a&|iu!R<xvs<#V25~+PTMw8
z&h#D-K0o&Qa^$y{SD9_v<Ldn%Pw2;oCJIzhI+F1NTFkEtN=HR@Ow(0;n)>d@w$9W*
z0<a!I*+GaI_LxG#c{a^Fjc6Np)SpYO*BZlW)Cf~ejaM%Bch%m5QgZ{(y9c~+1_<Bv
zqe7r#8jpgZq+(d#kk>V#zda`iqwO{T8YmNtd2P5U-l#8*S1^hfzcJ!I1zZ-Yx*A&0
zt<rG#MElr9pcp9uPl|O~I3SX;ZIP&aRw*V}odQ=<8|>>|TY&32iu8n>wHm19mC#C$
z@_$`a!>1c&qo#dW%g*x(2-<BL>@e@-%G%t^8m4=}tWOgv0-Ca>3PqW|B^klh@|(&`
zAqJ2U^|$fgqii`m3Tf);Ya-MUE=T*4DBzi2<wRT7y70e*!Jea<o@i$mGI4=VDdtiG
z=m0+01frZVeuJTGHAaQ=0-@+k4%3+x16+@$jC2kC(v$6QYwSLC1!dle!CRnRnyL%s
z+Y0W%b$3uVD0UuMELqCa*<`R)lM^yjQkHm_WUjnDaIu&lvsLU1mZPWz@}=WXq){XN
zuABYjwLA7RX1=!<y5D65eIJ2hp-vB`8scr@)@mWuxlR>v2NDlo@@5?}z^EFv5e$sW
z_ZEex1|3!9LlNATh=ibm6HvUK&DR}54NX&@`21nN)dL61e|4E5tCf_U=2yL{Uw?lE
zu1U+6A`;jvZ4k>j*4;7xv-bCP=x3lO<SM$BL=|&<LJbVk@+giaNB)YQ<(v&(WU06F
z>%EEL2c(b@|6%VIl%4T}pbtJzY^9X9OQ`&GP$`04N@7md)m{p^W%XL)@=cza_TPCD
zFeb!zUD&z2_QBq4qgs=Du!^r3WJnpKmJ>Q=O&~61w1Z_x7=fLh;K7Idz|GdUkKH+F
zpFrbh)`1%=joXU0Y{uROge130RPxNpXV57~BLL$7Qm~gUv5?P@C3jQ)6!ke^E_lnE
z#mKCxAzKsv6_(n8bfvzF{X`M|cBfs}t@HSgTKoG0@;YB9f{=XsK@XCR8{iEFRoBO`
zMgPj&KRX*>V_4Hny`=cQdH*h~SCyQ5DVUV0R$T3eo-&&Jp9qG;SHoG@VLz$2#`}w#
zeoT7OlOOF|I=_;#U_Dz<EOW7BUbFffOGj}d4XFkm)zKT<@-@Gl{sJ{4KQti1K7t(J
zT_5b}#}e&18~%;09~C-BK7^Bn9x3RMEAW$mrFoeWsSU_}&nb*`Vdgtil#=08*-vTu
z^^WW|yUf4l;Lj*`9gC6db*S1WH}(F3^BMd93<4oFFjR_|>QK3RG>%YST81_CHGUr}
zMO3@T-Bp`Xc1&_F$EgMy!^C^T`C@)LhQ31G-J~vJ^p8KeYj|kw`8%wt<&_|J5=P^u
zPr7w@p_*7ubNhA5=dS9+9sd3VGS&){>=MgC6tw5ZiI!1Iwq^TP^S?j4k_RRsv=8ip
zykgXLQnxOc8=|O`hX#*Rhk(A6_-O5Fwq8-qVi0ErD5p7DhEm#0QJ$a6mQ&XcyU6FT
zHFYQT%hcw!`}&1@!rH4G*x#MEX}m0M5?72LoJdcq(Z0SBQ2IUEv*?n-|2o~Ft_3os
z0((ZWfTK9qs~SmktZ$P3?+wgd7+ADi6%@6gt4(x-6xb0P(eTLSqLRwvlG)e^$B)nw
zagDtt@}ic`Gm(+IhV{f+nt7QJZyU!g!kx{qbgR?PTzBCtLiVxw94gjuEb{jr3wg0P
z>XnO}Jeg|e`GnPt-Rf^{i*Du44E6CgWYfm8D*T-Vh$TNpIUAmF(-}Cdqa+|KHqD)^
zP7Tz;b7rO5#}Ee8tqYb}1tVoLl}~vgh==jfXbExS?9u)%&^%|296D+_FP#S_<P}ia
zQ_Us^ljQ1pM8p-(kp|wEk<-LaHb>AXb3BUUL9Z@MiX3u1Y;H%Ok7>8vPhoO;=*ub_
z18n>E5kWiZOv?F4uqXPL9FhxdmL>Q}PmVqPX?&u9{6q|NS(UWMIGp8X=I3O1=aPU3
zB~lz!RV$-u@kDB8zvF97ERZYj`Jjo)h{kla@Ab~zBu2qi<*m+KDi~psG_uSr9d*@v
z28lyb$dgd+$Xj^P3-l~3X=JG;4CwH0t&VWRxS&Z;W2`Ug%M(~0LksYxwuGCO{U02Q
zG}8GvfB{0DGs^tXRM@~+qvfnfL+pM8OU{jphLQnl3ud2_<~St`6VjcIHWxxwNfxei
z?(!&1m^y}`8v&-sa7aq=G}&BxbJWixF=U2*x8;qDIKQcA{7afTp!FS#6)6t;(;t;6
z^LjJKHqZn=sr|z+u%}%3t*BxPA30&IS^_U$kd5?!0ngjLo1l1MLBsmEiLUFB)*HSk
z$v+mtAXOF+eE|L5QnfRYqm+kA4>g`N3|0$0jC`KLp>&=FNK-#~{n+&XYQ6?6pR)|T
zsbN9_*D0unQ@R#XOF~_^{(lZ!NL!8YJt2j%hk^P4H#VJ`n{GpFVAYVz&6}I-$Cy^x
zBZ;Zs-NDAtd?%Fa@Z<kX{(>C(C`Y`!u{7+_2#O4~5P$9gr*_Omoubl|m`T>tAG#t7
zRC;wXjd?UcuNf1M4mx{g2q{lZ<NU_!g#f#RhKrxSEuj2cU*YvM87ntz@NChm$UQi}
zm3Q}C+%=2=z-1J&ZvSzq116~3V}w!JTRLVo$Dt;B)=QMonURXPUf$D^FvU(WNRx4$
zMRb`{vn>q7anV>oZo4);BXZWz%qM5X+R1VeA{nI%c0nZj>pVyzZUkxm-ssOzWNZt;
z=Wz`Z2FwrGOE8STvq6Pev$Sut?FybVAamBgwuLDqz^VQz$h&y@v%L6);6@*8m(C4J
zYA9Y7;td!ZAAS|oj3^c$y2rK~|6MW{z3E2DUJ`rDtcqXID6ByOh0oC4SeFvpBZi=P
z=fx)N3K+e0QE(0bjNdHf753fz%m!e)4X)sWv&!$vNl>!D*|S=r;}}m8;IX<{+iD2+
zO62Tqp#OqjK^M?GDPF5N+9_Qn=f+)&+0!uzF}m*#OyF5F+hJPet@n;1H|wVx5Jc%U
z1KVWhBv{;u4`N6_gs}K&idQur8)1CkB}a$CdCEUKQ|_OlfuH5Kcd#$7Y#d<EW)89|
zmh=^bkHPpX%-Dc`O9*>Q%6cxhb1uI&!9yP!TfxGY78W+S<nMC8mml=}0jD~gv`zHC
zmey1Kxxr4Gwpy4JJ5e<E0EqP#%~?mt;8Dk-6vRuzogLczChDWlwh)=jomKJ@5k+R%
zcEN<fXZk?tp)UL+t)0bTz2^_4dpSypD<tUf@ih%7Z(B*ozF0gF8qOLD?A<p3HpaAM
z!`4Z}$6(#xOF_fowWsjWKPme#3yIf1dh~%Q+_GU^?Yzybns}FlETad;0IrME^YJ)K
zA5S&9(~XYC=4=5Y8ry>{Pyt&=qB`afJ?#b?rEt~)V{bme{_N>UYKzNy#HyUmLroOO
ze?>Dn&yQO-R5oT@MEK0y0F+BtU=>hgVr7J}$fR4ZE{X=9^j8W&!r})N_MI1$%-_fd
zd>m1kd>qRtl}UR=g?_1|;+0U<P!Oa<^sMUr$Rw=vc=dL$0I0Q}K`AnT249<36cV5>
z2d$5VVc`+Dh-a;|VVvHC`U!O*2bRj;AsLg0vXfJIQoA?LgJn+0mnrCpKr(D77z!B4
zV{`>_D3gB{hVw!o>w%%{s{q|Z;w_k2$}d*Rwbb+QB?hs5S*W#+>)0)+8Egi|x2Yr~
zABjBsaCTv4G7BwHgq*z!uW)$@I+NO!b93`-$ej*;;Ie}ntK&uL!iN3L0y;3qa@wk0
zc*ojAT>&xNB&k%yU-U@HsaMAC;|!s#$B5NQa82%KF;lMPW9hy;No%+pr8a@T8*&8#
zV42KMy=z2adOT0|pR;XWe&;J2fmwG#^SH2mX3^}D2ZW@WJr3>HLZfc7wAe~E!)-d-
zh%j78kDteNihRnR0KPG7*0_UoNZ4N`M&|!*VQaaT-01}@`#ocdR7P=|x*mOuLgB!s
zi6q_)>~4tl#{eP41mHVb$HNV|xQXxpl}bBwrbhjRuPWq>;+T#7rfEBx#T}@K;5aCe
zOb#+Bg^6gQO(^VY8~06c4O>u1I~q%tcQEKjDh8yv|LqM@v>&>%XzHC0#m}LAnK-<)
zkds6hH?yDjdm+Pr&cNactm1YPLw{;;amk%u=6j`=TZ!-H@pHTbT$#u49q_4QHA}~I
zvRBOj(+rE73#sn`wkj|x_06jg$#pu|3!b}Rs|DK!O87(n>zh?yG8wj3H0&>pr1Ti0
ze_^w^BzHE-H#}B;Y^gxG;<P(+E#el+zU?2^G|to;C~;N`(JVqe0vQjxceh?(1q3UB
zwg4w$5&085ON&Nyv^g0Kjr)UGfgGa=EqA{?QiT;Qe9HzX5ea>w?tEzjbv0rb(}XS_
z5E#_(9cwr)Ej)}ji7D7#b*0hLDEuqoKh(rX^8iw1FULBJzj99$U?fZ{A)27Ci$bS(
zZ$<2mFEq)SL;e@FBb(JBv9%6V|MD`f#>2EI7u8G%x|&n!4Bt87G=m4Fkr1hS56N5%
zP_lorfI@bKujh2z@bzHqTQZtX9w-E3(*EeK+&<ENj{m86I%$wj^22z0QP2cVK^B~O
z#x4dMf#`o#p|l&39Nc_r&ov8iT2dsKn5T;C4pc7Xd3YCumoUy+uCjNkEmY4}kG`J#
z4$!89{LRoJ;bN9Qw`X_lB!M+A;L7em7YJ?}UTK<wr0imC4D$7W%sHAD*842*i83K7
z*_`n6EY@njFF-26n@V2>D3uUezQT<XISRaj9{R$eo%}%^xODHa_B&)M)<Mr7JT9q(
z>DufP(21_aeecL*u0s=q_LC#SF2O+*KHSDLhVwl7mgy;(7{gr`9ggD5NmoY`XqZo0
zk?N$dg^7$OB0I9}c$jBBQhHVXZEb9L9P}+EfTi6vscR%_ee=nJej-5$V#ikd!Ddmq
zyNC|^B(BIt_kPtmSR}M=*LjU#`73MxxAcK|;Nz0wfVJGYyrC;i6xm`jSNgM086>)}
z&Au+KtWaL%KplPAw#*e$+1|0@{FrJK%)G!q$K0a$Pm^?HHn1BOq|_;0kq5o{waR)D
zh)T4aoTQ6Wwdl=G9Ue|mE$n7r{ckM7=2Z>Di6s8#oNPS~=^r{1P3Q(1@R7C(%WKFN
z^c8tu@;NI)$O%eQ1UHHP|LN3KoC7qE#%D9RlOpw|x!TX#$UZz{#oM=Jkn};H(Tv5R
z8Ty$c&DE;+R9T~$IvqN-@Y1`gl^_c5ob02}z8d!@oA70-CJwrzBxcjbc+~2`+d(K|
z2wE+2SAwiCr2f;X1SPz(erQtTkSQsM6T&UNESGbTk1ioaU~en=@etymg+C+2<g(sD
z(v^H%g)&uqDQ_ly#4KMa+swYR4p}dQ2dSb>O<X$VOL}Uqxk_>m6>o*L=IIBUi-j3H
zoS!7gK2jTWuVw9O?F`70E-u3J52(KK={I;0l8(~5$)W}+!P#6_!5x(%sd(i70O;uS
z9FH$fd1>c#PnSzlH@>F^tpZq22@EL@1K8ZAdZUa6V{rpwLc_RHj4DHFIIap4DVtV1
z_LM@UTM@kEY;=N!4sE>wi<(^SeWW#u=O8!=v5xX=sI;iuZFeT%GlM2({5puLeCJq)
zA`nTCQL{SdrV@cyyWxvG*O%M(1SVPZn{Q`&b&9K$<pPxf(d3~(quZ3ajyi5`0~&ap
zW#>jZk|2`!PJQy6RhtS(7ZH_cndR}3ys=gxPMQF@D^jM5gnCzpjGz?yMcA3GY67+u
zQv&-E{ZGu?Ml_bayRRCvFxk$m)(ze$2Cbv-N<|+ak2J@T!&eT`a<0QqiW$$rzjC!|
z;KQfCPf$xqkHc16Wjn_>8}0*5rn!)GqW6V;$39NrJmNsM_tjg)2$|zNG(8a346f(i
zeRCo1IfpXkY^jMw0wMv%RM(KGBRX~*fv0Jc{=OsiEb~RT?8n)PO{C;JZUuXTrwcwg
ze5z#@JN@}WJA4Lwt*Xh3?h|7!bgQ>zF<6#M7GK^<gAKa@F}@I-SM8w!o`j(%<?Wz?
z`?fMS%r(I_jNdN_SsJoa_n)+47M|9eVbQ@=5)bPcea5<&JoZtJybLj?sZRFF&7397
zAK<!8a%5VQ8q4gB<Q`-g&=$uxL0Yt{4bBPTS``zN@m-$zFn99?k|}wq<bOSZbhH0C
z#^ZgO@tYYHk&%iFuO+Qx&z$~P%14v*z_xHAix*I-StzkUx)+Wyf;GcLeO$t!LiJ&5
zx=|0vFqTbZrm2dO<N(Tq@M7ygORaHjsx<6RN!vLYbsva`JO92noVK2cyVR2u1QJW6
zO;k9!UCB_^M4J<=TkEIY^n8Jh!U}n+#E=(E^urJGxf29p)x$)`6j+ggZ*TaSVzGQK
zBF9L!dUO(^fk-;Y=E8t2W0tr$Wwhw+jo+uf|GrHj6i)F$C__c&<W0Sgr1F?(>0>j}
z?VZ!P`~C6txn9f8*|>WN2{=90ToAhF?$?)q5f}5WFUutGN?SWT4hiy&hwbI>5_4Ay
zrT__Ea4&pqHB5A+FjC-f2CoOI1kfU^eJm(T&@ICD3|%}>>*VN(v6dXv4@m<i+7Yf+
ze>EgWhFoqdeE2^iTy@7?9B<`bpgmf(tI3LGR_K!PX4@6_R0NPBBh)K@{TOBnPLDDd
zKF`OM3_~iOFdV$W)%@n8p?afcMWxT4{D}T^cjTBeuw1O4)MSAhJW)*CQj-6|td#a{
zx40}l0-B)`{+>i8G$#vD$Nr#Y>|UYacQ$<72@ADG*0gBjtb4{j073V|cRxI%xQW6i
z4?~>k#9Rknz;^wJmbbH>l<~t=4s%#cHTV;>0kRYqGq^gViQlf;ASlI+ML4xqDSuu2
zdtY8r^@3{L(@}0C11PDk<Cv8vGY(G`AE9Y<s0b^eBBRO?e!B?95g!fG7OZ$VQsO3`
zI6W_v(@K%8`FpTzn=ehmE6_fV0+-6(3B}ZJQTm6c?U3%J;>e$6OB(P&!mf=t9+-m1
zoI7(+ny-zx+)j9}KEr_vO@U2n+T~#IDIeyx>eBNRky3~t4Zg#n>mk(H=z&+MTsYS}
zuKDoWk2&Tfuka{(L5Sd5?K&=x-HG}sb1mwLVXz`4C2C4%=relYx0p0XDvdbF$s{j4
z#Z5-Cp|ND{?r^%U@XZ1XSjMNAtQ-QZCECwW_RHc>BVo~)_Tyhc9(`blE9YjH`ta8-
zibPrSHN%B;$48&^Ksb&drp>C-C642HsRQcof^KwqsmO~tF8y;i=e;ijImy{f9?zwP
z6sTnz4&&|^?7-xtRFX+9cP;`i=XR-~4<MJWeveZaGI%GFy>yS%M-}|>(R&$8%?;?x
z3`3d#&<Weihl18_`mwC<l(E()H|+`Ey<2Mo46q$*=^SHNNC2<F*1|!>RShDi;Yg6D
zm|2x!$J@lzdZw-5h~#0d_UKL>!OdKq`U$zAwSIFPQHs5ja7{5$4}^af4)8q#4-2lh
z0M`!<t!}mjP&}wB%cV*!Qhrh!Seq%bOErS=#WYF>o+sU-pvV7WbV<H5RuGLRKQEi1
z>4lo`ld`vfIz=JXi=G6O9$B`t6W4yz<vw?*Syq&EN$`O*uuBUv?yAIWwFOJYN47Lu
zRtH6==dq2Sb+HV8AX;81An9MIPH-uTM_)Zlr7?jNSXMH=>KlbUx}&3cZn>$p<#om4
zl|M>e1!wo0n8oL5`<IWG-GMw@kMU;3-sn$OyK;|LfgWRkU^s5hBhP@_2Y_`Hij&U`
z=F?_hQ&h%Uj=CJ@DM+HKeM`Pv?I6bAy#M7vd16ady*G!`#*l9J2)VQ8FZ@L~sb#X`
zlnH2Ok_YFWyK#HU)0$RrgLXD(t1kws$A@K6&AC3k1P-RVF)=n9+wZFr`Me|6mNMY7
z<yJ2H2R|O*m29~JnEOar%{KAD?hRL<X<=5s#55>)h8fJD>T3HUlvw-qhm&sEx94S(
z8Jr{;_<}y%eAQZoYvv>k$1I6m5&7>eIl9qIM;e9|MQv>!81l8|B<;J|r)6XQ&$gjc
zThhwVkBp#^@r<4ofe8nUy?^RMeKuaDPhdOZ&X&GOc?3^h-qxmk0{sYv#XMtcid)&w
z3JwLCE#kBG!o<|YCmO?HcC;@ffEC}t1;Fb8CWt=L5J>|>iR;S8#2E&Nbg<zJrENEW
z+M~Y}qHD<07x%qR0?sZTx8KFz8#N}t#%5bOmwj_m)C5sm1a@=5p&K*Qt<;~Q5#9a8
znnAwvTPhbIl8=>YAdkMVBPu#K$ybG!+jMTmReg*?I%vglbq*Ey#p2P4#lp3#&X|p?
z5YbE4s%Bipz>OCD$;=+P&*r>n8GBInS4fI2{<b6=?OSFUQu$6h0W)Z;cngM1mNE{A
zAhpP}p$UDDt;UH*LD~nhC@H?e`#u<kLxRu9NzQX+*vxw%#hO*m?n&P4o3a)FJj3rC
zLA}bH3_m4#Du;8nup8g8qi0|5)eDDn^Ur-W%NJO}Lw0?m%e>^B54QLx7mYP|Ae6z0
z)8=1{0!!q=JW$uS-9A<_3J*8!v72o{xr_sygb=I*n|i>*Iu#(>Zzlu^Sox^)U`q2#
zJsd!7@7&>WC>rf!9IPHCT(H&BqrY}egVQAa2SHIcllqxGrWFh^18>$SGtHu<SeWD|
zLyJ#}`X>fba-4`o(Crck-Qv+q8@D*Sdr*ya{>DlzQB?+9(Kp}f4RFH2bW*9N&gph@
zkn)z>hAGa6$NsfS_5Siax`e8L9+kIq&~&F^b3qq#%{jh6E~k}l!ziN=se&$mx%u!=
zz@!j9JOcMs(*{)=0&rY++wP^3WZW7)w(-rjOarWXv<Nza6Nc_+SH*|XbQ1oFvk|3c
zpG~)Z^qyKWlB~<rM3hVImkpZ;`9lNVa=u<F%?m{#T{(IRfwft!Lp?M=d@k(ag;=&%
zy+nxHddE#<Z7RdCe}ORm1~T=Rg?=2FA7ktXRYkaHCs;32YXL!LyGgx)bYq7VlPmPB
z(sDMAT$0`Pn)iKH66k7iO(wmaW7{a!YK_cj7DUg12*(<rbP|_?D8Gvp+&>sV5cgY9
zUppZtx|-v;={#kHWC2R~E3lOJ|CtFr_fhQfXF{|62#ZNP=;jNxw;MT!&mwYw)S9G&
zEr)+&k=8hch@Ur3OyUai5TvEGyg5ED)@YMGkJU@c^biu#Yd9;M`q_C8{OuEGpsW+H
zlwUa_gv2cPRgb;44=jJeI)!8<TS{UB3vpD%V3vd;>yU|Qkr=33a?&?)4&jC&EXV|u
z_%ncbCRmvH(zAolDyPM0Oo@+@Ou7*;sYJWZ`UAi7kSr7wn(sT2eTrGQ(zXM=47$q5
zws)nVV0A!9A=@tGPm$vK``V2#HxZ!wM07QMoY{6iq`qV9R8uKDWmJV)94>MShtQvR
zm~_5t(9c^(vdT&U(o|WQs(n8P^?<0qdOWWoOW$Kzv+eTFRJ0Jy>9N+YE9{&csbdkg
z=_Ut9wd(qbr-fI1_Rn~-qIL(FiEhQf9bCxMF+JNhjgLL4Ug5Bwe_XSiiSY2;6t*wF
zw%dE=>KFrqtc!j=KqHP)VS6cr$wuf7ED;AhT~X=0(jBnpDDv12w~tZ@7N*ZsG7xF0
zP4=Pt-k_J2Zrk<X%O{I5FB>EgX&nptO4F)T*uAD)yUI7^pd|Lby1<0#_r5@P5kWTU
z#POxOQmXbLrE`X9xNY0380EukuMtJ}ooq96_98rcQ>?MoSZT<NfMlgR#z`glowR^f
zNnIuhs`|M6q&hZE&@Ru0SH{ZiL|4~FM|I*SW5+6|gxFnucU;`hJ^H)jx6rQzQJgDW
zqB!cWnny{ORYY2M%GpU^dfZKAOr}J;hBLdbK~`)=%LE}NTlHnvgTPxGXo9@F;~!xi
zQJzYsMKAlT9m(`Dm*Lp2=PB}ZX;-(*)JOLId4KJuHr>oL5=-uGB;69SK{=ec-f65i
zkE708bsnkG5MevVs$C7YvXEEAia-FFveS`wMuVOaKn-7{;xJtL%<^*>-tZ9LIpezM
zIOXRy<kv-hMmq!gxoEkfS_P2iQk#7Q`4JLCC?t}l90Svgt>9Y2ax4+kYAgd&^pJes
zUk)R1@cstzUI7}F>J_BGbVZ%E)dT5K?8Os!07}-7?N}zKQe7|dU4c-JdhU5ftjbuF
zA{VA~jPnay;~$Mvvc$7K8t^l^h2M75V5Opv`I4i7x82!xb;Y>)BA7QXLfuo#>?$oU
zNTkUHGH3)~)kSumv!_bi>LE=+40_N4*xU=@zzSpGf(ZE=bd3qjFNr|Q*gi4+#0Hka
z-ZfU+*HqMV8M4bm0sr4zExIZ+%d{1mqawI1Mmnh$sr+RRK|(v?1at_2=IC$+YVGnk
z{*`f$>2WIXe-0e-kS-1utNqUS@Z#G>K)^?I9yblgJzM2AI5Zk}trrQvQ8<g)9f=lB
zY(rzvgoERopoe4-WiGES965}z>_%+Jh=tcAJA?;*nEd<wcDcEUtSi;qp6493DDSy@
zynT%?Bb@$eV9?{Mp2r49Ph6(>fN8Lvw<Be5wwqT|<19W7FL>m)Mm?3)AsI`kgXu@i
zIT-}5Yja!9ijHb#@aETQjZ+kY0m%FvU??wq7D+OqO2rm&xt6P9`(PlnbsW;R6Ti0J
ztL2eBtIwY?BsR-K%lxU)D=KGxeNJso6USdw(a766kAb`9r{DvXS{;-O#gw?wgkl?C
zo#??cRSmQY%S^wX9w<^)+*Ez246dbhTKP-|a|3=Kl)BzJyj`0#vfc4yMF9RvGuI-b
z?8$s69cOBF0nu88?1;)u-(6Z#kD0Pps6B9jUK!<0xOhqwQ}jDc9Td#=3qj&-AI{^-
z*P@Y}gtz_SEA4Ptjt27tneDdZu|qa0-@IE%(*a5eAs6H(N6V+C0?{}?kX3YjiYj_M
zW2H8{K}1IuchdLLR-;M$V)zMy$VO)ArO(n4<vXc$r_omF)@X44h1`b88iV-b(+#FD
z(^2oVFJ2g*ZrAE5lus-G8yK(YgekdHDr>mnN*D8P*UY4Vsz$SnQ3M_KTaHLe$I7fU
z=xLxuCu|tYpII`=B#Ri%()Da;Xv)ctz(DX^2K%!b!^^;$7M6N`7F><D%WkRQ#a4K>
zQz}u+3Zf9(-ylJO<Xi;RQrRd&sX|s{2zI<a`EY@)#k$?_Wz_S!l1YsJovoLKt`igb
z!dkTJI6bbp6R8<Ga&Gc{B0y+mP{^UY7SE8i0Z$jO=<tuj1k}w4yUeO_z0&0#ox-s_
zF~BFiZr-fRn0zPIA9tAr3;MfC9h|;<V40Mv2LXIt-E=t{lMWM5%F*^(P)6jpL<*N9
zRwF`Ohw!LY`eGf<_R33F5}62YT<QJyhb<%bpocc2?R+D+dV^cUextRkwC@fV5km~S
zfhriS<+ZTb8x!8BeEf=Z#ey88XfBr>N>$QcgX2EWhd{mI)9_81QU0G+a5l#>?qHG$
z)2OdsHx(270pd%qcO#<}e&1u-y-h@jy?>0BRiV#tkuNxRt#dC)VHj{e&8w{-FqYW@
zc=$=B|MWjV-jP*J!9!diEJ>3A)-l{!hcEA1XgxtrJv;+cI*ZYxpgU(L9Ds+Ipkfj)
z&CzfQfbF1}ySfj~fCw#;!?VjJ4g_y{9cn?)i{c~r`qG)!=BrI)Q_iy<n&17B2;A#V
zWX)s?n>9pb;@>I&u<DouXOD4ZooCMGn21|ks>x}67{kmemy>Jn5hS=|55vFO1io8l
z^NH@}o%V&^7x2t5xf_Y7Uqr=CBnY(I90wwA5qV0yI=#FEU1EpmC!5gyZ%&_}#suwu
zw7If>$DC7p(zncqPdixPTe$gq$?VGLdOB-Mki({wFRH*}Mjf9b3KKMj(c8{F*j8!N
zugYecm`_g`q=z)axNXlVs}{nbR%m7t>=^cxgePq`8(h*QX{LiB9>1AV_^&e2stYT*
z2%qu>7Ml@&r$gBu`up!<t^p_+eyk2nl`>YU>)_jWr-Difr&AdpIADuk`AtPfVuV%_
zRM}|CJ-O}m_VMJ)H~?`Tb>>Tae}Q(8!2pQBemKfj^Pq-tVl~S@k;H{ZnKu3WCMM?y
zH^_w-@O4t(j;kL)Sh(9TDtxE-Ao74XJ#Vv*r3+Y3n0`T1Af|bUYM;=4;Xd8eDQ0F4
zAxK>?UPv{lEmm*Hq(sx6K7md6N#q0Z?coC=T&BUcT-Yr-;x<kNUF3<tgZ&uT;_e$#
z`4XuKK<!T6>`##67P2<MTk5%Y$S18+!x|n687VBd`*%deyt!C&!5J+(vFTs8<OQgW
zDo?-eJcQ~hzn?53UbXtFhMuouqe3K0x0bA7_k@kdi~2-Cj6*Ex=bC`6A@56I&P{)i
zXyp^6aw9j;J7n?!WVn+`OFI<~{{RLnZ5JbqST4L$-5u6N<~A4>*O#cpw(y6ujgamn
zeWK{s8Gz>FQwCbd0<zTN80C;X{nb;k673W)G<#c^S`>hC$mYVLxJzq<OMtilN0R(3
zTV99b9|^ESz$T8+iuRj8IFcR1VT3xgBK)JbEv^<UZpA{sws7P@b!(=38pz8eYoRz%
z3Rd#yzm{;bDTdKu0#8UG=io@gg260E@bNxxM0uj(;y{{p&50@rY%s-@gF&JMS9`k@
zXG*F%<CTPoEVUQsnn+z|OS#`#23HmwB%^rwGJAyj)qVT~hO)qlt9KqiP)6Hhvy{@^
z&f~Y7VrBgL7G^*UbzfTxRLjTo6|%AZuOnZw1T1Lj*8q^FhhL?nI|Ro8-KJg#)#prp
z1F37LsB86>GX%~zAOK|#>RjPhR^srmIjlbrl(ifwd{W}*08MZU|1Qc?)Xp?_G^Lq7
zWa_u_PDVdc_mvEhQ*_nL7~EEFsF&6OQu=i7mn5!rOc@W};oQh^)A)nWFzi~xDcq^8
zebB7YQ+a&0EnI{6qMU!=|Fq6nw5^+Is;IG=3=iE#s0A!{?*`&k(U!a4LuObi((!6~
z;md9PJrv!+(ga4guk2pzCMqG}LfH}N!r1Ft4E$hfEyQ(J*Cmj73@_=0mnUPEEdBx9
zT^PAgscj&%#C-NarDVf_8j{BvA;&#)%n;K_trqze3K$WV<^+Z9W#+0ydlvV%K`oRh
zJy&s&a9s*Tz<NcdS|b@kOiLhpA@%SDnf{A`McPP&OwS&wjQ>GoZ7jF-axOh4>3X^~
z+T~?yF9$N!49UGWMU4~=I@ZN<2;i*zZ@he2gUhwDUXb2znq8Wjr$%G>3`(tK>zz&I
z9te5O`DLE;j=M|)If>Fv#0?e`tvOWx>7=$bn3Dp2C)G`^(5(G)u^R4Uny_t}J2KLm
zn1zobZ+P+WNzzMVJ6#pbDay>V^@T(~UUK&JjBH=C9EP8kTbjZj7Ih{c1s+Xq8z};H
zuWxlUfej1(f_)9@+Q`SrEffyjiAS1SWW1X9mM7sBDCPGahZUe~1HXFdki&W6dt%ub
zOy8_SQaf<ae8!=!v;s@FmiG{U^~N2X=D-!JfJ&^B*V}^gJ*q|D&o-yv<P1lgKQccz
zk0=W*L8-V~D?Mjs2MvKXsE>O}8h};1xBrrW7&*qvxJ1?IC7hc!e8~l@{s*PoI@ztn
zh`AN<#uczJEXV(xkLBAFU56v}(r$R9fkf!Sg_iSL_?&4pv1u`9y1z}R#^Q#d*~)&`
z8EEF7EN9Qw7D?PW1;8tMOX;1nPUcER0eg(`(j0kxq)pI`Ots3kw&)*?&J;kBP*9fZ
zspNbS-VdF9_OACxZ&WYVBvlPjozD7oUKopY>5;DuEV?s8+w?*y&zth5>*$#gk1~_H
zx8d^j@YE!SjW~dc-^+7asqU=CyIiV05=Md=VJOdx?0g}7b71vj|DlcOPD6AGv(C3c
z9Cv3bR?>YjMhmwyW(}xxhJj4uw3)n98)`^+>F5SP=Y&5kYjxmvO?l+lr8R7x`6l$e
zQ$&obhUu@H(~S(b#lzF#EYsjIwg6uY8{@xh4)EGvJNmZZX2Bv&^vqy;5_N?3j`jO)
ze3Eu`Ghbw6%?obz&{rc|kuNqX7IsP9oLy}{kT=lGV`xFyp6m#HfV1A#J_TXl^3hYl
zvk;n#!0lgjs@0g}0)A6&+_G-A`=ouy&}MO`UjmnF$}OniSO)UfY_Oet=NyW(JLD+5
zDz?Qv$un23T{NhB#oJ~$x0b&Zzx8mL9HCYPz3^()ZCT6VBK;|V>iR8i2A@vCj5S-2
zZO*xmb0@WYE*4HM$Xs;=Er4%gzxM|8UJ^p`lL@L^;g)cO4?-E+P<Z$QRw5;w*LDZf
zg9YUb`%s7fv-XXgf{bd9R>*0U$`cckr6S~4y47pT-{(?@KXiJ?(QRmd`%Q!0G--?9
zhTO`o)Z#+|nWRsb<79tIs-qCLM*go+KRPpJtuU}Jz<+{<bf4%H$in7pPcgaQX~~dN
zS4>k7dJa^9o7h%X#YXvZVyWrr&sJL`7xpkluJ1;QvvcJO))*pah>)oqh{bA0r5Mxc
zPo(x^N*<}f-^alHf<Vp>M(DsG-8(V<cw&duAGw|U#~jQNMXXGdsga2`4me$%Y2xgm
zbknOdhDr)8Ywu8K4AbBjy=aLaN~&QWEr$wch&Eco>ZK)5=4AHyMrFUQYA9MEWJrhC
z+-lxP4c);j-|GE6phkC?4l(x6B&zUC9I<DFWR~tFa1}3*w-}cA-uugAmvKNV5AjHc
zkG;HhxhkX;k>{2I|Iiqus<3&B0PT0cS=7T;=`-YIrO3xg51$Zsn9GW4^G<EZdxs~p
zSh1v`9sFby)`4ZT=0RR7Ald&2lNUY^^58vVY(mEVsF7e#{W%Mx)YKAk!ZctA^69%H
z%4C_~nXf_d##i8uMbp5ItJ(WxOU{tudmeD4vh7a~!&Jw3nJbnpgmbT(btwCo4R#Mj
zaiLhfc&IN%OF1<_&H4<E^ZS#K(Ftua^s=DE=DNQQdc(39>X{fO5n9P>i=xvOxqUxV
zM&?>VNjLmgrac|}pt2%+Q)ri3M&um<+ofi&KU=1`9{gmYveJkgj(6H{Lci_UffGVE
za47>hmW7_;MuPQ1^Q8u4MOQFeAw4U3y@JZsN~JNteYwZOM(wRp0kKlDE04ELPiiuO
zCC5b|Edut1q^!%X{rnY{dqpbeip+ef(~}|bb2A?m+QoC#_X(W(ee9znfDz8Wam^;f
z;`paUKvN)+1L%#+iH4g7#aa@D+l&;cVW+K54%IijL=3`pGl49dd<t3KuM;aR14un&
z*Ibd|gUOs~ia^I$ltW8zLQ!|w&)*ebM<^t@TWtU}V+C!w4BB7rE<N|}`xE$&jZ+=g
zzqBtwqdkABb8|#al(F!htFhv%pyuakZQ;y13FJ9^<sDZkg}GzC+J36nVsUCdlhcHX
zA18BT3}AUIHS-epJAX&0e1Fh&|9Mv!yk*zMQ<<x2vG187neLSHE%SdUYJ+t0KNZs9
zQ;5=wgOE4(12MK!*929_@cyCL6lgQw1jFsmO9Rv#%1)ED?jcoRz>MWRjG}p319#lb
z+GCH~JJZ|&Q=!Y)fpHrjA%8%@MuB|6Q$d7q{`@s%i7V-i1nWLpB8F4SVm2@j!W^i4
z#S|~x^$Y90;=aNb@-l|(tC9lb0!e9z!Wm_v-K(avJEHy4#=`+{KVEQt7NrVUF0}^r
z9W~_JPE^PidF1YKVx}T+4knt~LZ%-3&Z;%%Z0ePJG)qdo(t6ME<5YsB#nSEUfl6~y
zMk#>vPNu<60iGi6XF<MYbiVOt%7qBrj9tnPNtaIq<Qb>$zLHp!+@N=J@MJ>xApd=*
z8$%RPH{=N$`k0Iha}YUQ-m7u;pLW%KW*X9q&*;19j8t5;&PjUYil&^UkG0S3(ecgu
zNs4Tzn^Y5ns;C=w6Rtc&AM>(YO&5}le8QGE`QMUP!#1u@lZuu}hH6%z1`xyXD;=!L
zgfwbv(}AL*FvBCZ@}+JUA)MJgspbnXxu=fff-LZNwU`zgNynkn58N%7q)^sUbLwL9
z5RR5a?hSYr;e<Pmi=zC$6Z<vC#M%0)2D2X1b<Mb?EJHkDUe4wf3Dw=btq*lKvMGUC
zX?dOuigKO9;CluUBkaLfb_d>q3f>X=-<Bxfau?!qRAIkbHCsnz4W%hb5y6oEQ7#bz
zF6Q{MGhENK7QgmaOFU9zW4Z~9*~srx;b*o#X@NW4f`V@Iz{&WIqK}UC77MWl-U~*O
zB^;@Fmve?M{Of9AyozBeOBMKNk5iLRcE*Fw+BNkbIXGd_4aJRx{VV_6eyD!*6%}6u
zkCHM59}dU!<rx$pXx%n=Nt+j9{-Rs#P-@rp#`k&?t0}mIMx2ukDct~-OG!k&Cq49E
zK9~%kj(GcG0~q{JRzXYk8M>~XAjqVXlEe|Np&P4w)CuwLo59-M-=6=xF5Y{huU8R<
zdZ?6f^t{ki0%g3|1LS2qs2^X>yNLP#*xX4Au3~E+4+hph($E5Hm)MuWH8pAohEb2K
z^=;bBW)W*)wznZxfFR^pl$d1dDH&AS=goHQ*6G@+GTVUHY=$L}Iud>dP2Ng~zcA{f
zO4n6Z!r}L52cHx>s`1D3?Ft?%48i=FT=32OGfb(@RU+X+2>xH@D=r{S?(8;BT0DRV
z725Jq6E$EWD#vjlG_J9>5h4TAIgx-X-{xVx#rSDSm$N@04e%4TS8&<jyw%LGoKT?>
zvxb;YT+lge(sf=X_EebYB+X<xtYN>e0{9_F4?xHt0hu*5t|b=C+MlVk=DK!#gwiA{
z3=>A5zSTVGf2tofoW8geC*7&nFUy)zdt7p$6Ni{V;-I5eeHeThGI-o9+8myYkXG3v
z8N-lT&J_<F&<F;BQ&;(1$VSzw8W&rnOL-08&<L``2WA!>wFkn!s2d7NebeYjR4AN-
zb)9E_@Q^c+Ls{pag6CfvgoXt5R57LMPxrd(P{iDnz3?07o6l0r2_s=zW3!`aoQ+A{
zg@r2v3fm*3<|6oiNNzngQIPGd0;tM?{ohZbHwwI7Bh~SmR#zn7^cEOQ+A2F#Co8Dz
zJz7Dvsm$xeHIeg@Y5Woq=AMaHPcgGoWMi2~WD_OYFaqJvf>11&6k{cQP!q(0p$TZ<
zTsYi2a!9#69nY=57d$;!MVLK(^sgvO4ybOAtfxIS5^E?g1CB8OA6}jL0K&g@3U-*1
zc?c4Tg1j8lXEF3%?<ss#Gt;`s%C2;kB;)GJFt}{B+e&9ur(1?tj(0mfMz^BIDMr$e
zoOh-SlN8XG*!ttI6?$n%2>?t3VH)Xvwd|ppjVSOmrb|+l?0O5(Bdq)Yevy12NHLUC
z$!%H^-ueZ+EM;aE-2Q~%5q@TA`LRRyn0kVR{BzpU9t8wpu+iB7>;*zVxTu>HzL-pk
zr<iS^R>6{WlTO;EV-TuaKAO0ih|@Pr*A?_szT~VVE|{p}>AZZH51WopGrrV*!f!SG
z@wD7EA%q>rmrLIbG?=Fcx*ITQ<SR{hX6>QrZP{(+I1C(IYkFeuq{DTaPgY?VFJ-qn
z+gy_`{MUIF;#2-9?quHK<xc?U_=$qzQ9!%{p-&0M>w5Yb@u&dD!jZe#y=Q4|(Q(;<
zA=8WsbJ{I~>W$Y#_Z;95z_rvVYKEl48Y6Yf+?dc(U>Wv)AZIsNc`T@4R%0w<a+G-3
z+pmGV#VtKRE^W3lMf5<pz%HVf>pp|&Poqu$e2x1tMQ&EAO;t;s2*B|gDYQx2O-Rsi
z80p34s90#K3|u-^u1QX_MInbQ7*MK}c5(|IT!4g0R4xSWx*V)CJI**x5eDfg%(UZ;
ztFw~4?C1fL2;IEcbMM#E7WsVKNZL-g?Yni%f9|&ROIAyiq;jX@kgBV!`3v}_-rT6C
zim-Ex2RmLWFXF6hW@mj@^UiaHwSrV&PajxP;4MVnCp$I*YE)UK>VB19cA{SRrcJPm
zNf}R1N*M<5#+;c>=lkEhlUZ3*$>_U80ExkxW`mIO>Mg@3s!jLU!p~SKKTD~7+Wi|M
z%nSdlD9(lfrEH--ptq;*fZ=6<%-N=zUkk^$<$yH5zcPQzCPO}P3WiGA{AsR&w`~7l
zhgD&)>ScJaun{M=usK^X+p~Uv?mf#K$<HLhw#m|ll9#2;9&)su9{^-#Z|2HV1bp23
z9`zYE8~T(LlBqpZQbz8&U{=h{J6;s|z{27?;pfxtas4O2$=vh?1%Y635%DDTHS;xl
zX)ld+r+ye$nL6O=OM%tm1t~cEGo3J`PISKa;YLYhF=5XC`tVddu8upsrF=J56bnSP
zktQqFNW_mz6Mw>Mg_O4GX+|3<UT22a(Eb6VFBOkR2$);@gV!VS0$PE|)rs47-k^V!
zI)?StrBh9`Jb}QW1Bm7C#FYHRt9Cn162f)K=N|{^yEa32aV6BBx#x%aoy2?f7sFMW
zpHPmYDmF`T*V7{IR1VbzpDvgLC3TWr!jCzd5HWPCO*_#8{tDd}{*$liAe0Gl_gfI|
z1U-s^EnE2RMN~dWCb%oaZN>^A?PtxbP`okl>YLLBzk)6|CnOd(9T*fY4KKFM622Yk
z&H(Cxakc$J=Og@smcGZBv!=2}?6KEMl$R8SDAmQ+poOl<2vc|yygI-fe!JC3qyXf*
z6^x9eEw@A*Zhz98(Hye9-_j9%P5vA>xL$>9nH_oW;DG$&@ugP*P=qe$--@LS4#Y;S
zDIp;s%9>`J$6tj4+K+LbD(^q2;z^`tHVg=*m2j&7Q%klNdVVekCqk&H9#HDNXnKn>
zyaUWX1mFyfFFuc&L?^Qf3i_hUlog4oqFp0UZMD;y8~H89cx$2pgnQE_{#P-c<8>N=
zRJ%y|oQPZ~h+CFV90cTL5RaMEuZltRQq}=8dcANt$_497xwF|QcX2BBrO!@qLrk%Q
z#rLB{Bb@n&3}#|SkTEP`nwe4VAvl3%)PFL?tHD$$G}7p+1hmw?wO4iU?I{wKyC++K
zx}U|h0RnbyMhVIiQLBkApNQWnAT0hF*%F*HdN4?aWyPJDg&6+sBIC|L829Pf=yeT5
zG(-}YzacMYD`Ho}PWXgK%of5Sk`Mm&IP=li%m?1GC_fw&G-dLNpRHu7-bCob4qAZV
XrV>%}8{S;r`SA4n<~OLOQGVP7$vT&%

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v
new file mode 100644
index 0000000000000000000000000000000000000000..b35ed6b2d9636f5767daf063b76cc7d12324fd28
GIT binary patch
literal 30800
zcmV(rK<>Yb6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjz2xSYmn@<NY>G_*G;3G6f5)3Us
zNE5LykY@a^z3-+X2@|&CmrJDL)_oVj{)aMq;&}3Q*2E%yTBX;A9U?WjbDLOzAFVve
zr_0OsEOdK<?KW4#ATDkh^VhgFUj4eAeS*|{O+BGYH(l$hYx=;bz1}YzUDDwO6HRz6
zOkA~PtiDGm569)Nmg;xt2F&@}FNX6Gf!d6QLZ12fTDyI<L9wWNT%-ywagifjikdI`
zxo6hLANNX+wVMu+&7Mgq<9bndzbH<44VR4kB3mDvQnbEu+5yIKoI^4Ao!g;r^S`%2
z*hh>(ijw^-CZSad>JkN-7sqc@r~p=KW^SpI_Kf0#B@Rvd4t-`QRJp4jpWw%1*03!*
zLMeVEM|kjfsUXAbDY!~@hByFPHjbv`Ta~lW{V^VeOvckRs?U+&c`vjEw{m%5<C`OI
zL5)i6yBV#(rPeIig9t<Q)L1$MWKX(%ND#ZZ0X!|_jydUcPNuleZTzHLv8NUQe}h5~
z6L8tp&C0VOVGU9tZ?33y0GD&Z_zMEaK#2sGSG=p&CiT|i;%VFR0LQUjKb1MxTuOAt
z(sMP<qH6%LcntFX(;R}$1;VdjmX@`)<=QSABl946hM`k}?-~yk-+n7?m7uH+wp?=k
zQ>0X(He5VKG|$M6<d_`vRD$VC-pU`o%wJ6fu}v(XSPJZ?&#Y&D8V&6zDYvewJa*y5
zdtciAP()Im(|TwYr7+nq9YHf`y)Za#l;>=d6pXNDk^D$|D38l4MiQMNUOr$|(%KVL
z8bXO5OG;fwIyR1R=Pj1!7TCxcx5+CMyMVgrfv(LPf_R~UT8H}5i#CI<2Oq<3GzXzs
zup6oUAxnK0-mc=Bt2Z114JiyO2oMXRh8yQbwF~gb;op*GjNI#J>~5Uep^<Vp?e@zW
zs3KxY$S{^8H*)_1CF>)t9I#4&ZqpKrQUl#_QE4bQezxR=>rfy2TuHLAFgd$Gy0Jsb
z)Gei2xVz(qEJfhBQj)9_j$UZ(#0gw<*`gpB&=r`-#~^B%B);?<ljF+*i$`M1h5NlN
z6YTvPFi>anKuIYgeCdJx+A(s33&PY0fYwv@tk&2>flF3(tf0s<y+7>)_+m8(#ozrH
z57+!!Z<T804Hm1v=OT%pGrwx<K{^4zpL>}Gxc)RcdI>Z+*MgwV_7{Z@Ii<|=Pw~c@
zhs5_bhdu~qhMZ^=I$vJk2dWakO{Z{l{0|XJ=3MN0KPXXCmPc2J7hIyZq>8NcFrM)+
zsxoB*RMKY}AKx5=EW(?LTu}S<8V&40bWKnM-C4*%d+u$sZ@nx%wnCpSWG6xSKifmq
zZ41EPFl#Iuc!&z<(N!9iqL|!=zYv?@ejCN2_U2N}rKu`XRtgB5bDwc2-tcgiNThrP
z6xdRxT)x*h&i<Y$*aIifo}iJ*7_mh$X(AQ-)K!wTvbOtKP$-H?YF2zZ-VVb(Rub@o
z-x!p67V8pNMx8urLhI<R`a4U>zZt7nSJ0WlrCnfJh~)~LEap8Msa7*D63i)a-To=~
zmacc#cK)BvxN+9s#34u+qy=Rt!RTbROKgmKWjo4EsJ!q4sxH)hv#YR`u(30H#qI7F
zhm-DSt&0v##|Hl9q9t_Z<F*=z0mL-khudh$leiLc6uUtzyUhSS&&kXHY+p?}82AYN
zF(>#;N`@wzj8pOUo^hIS0U1(&UXXgrKrYP9E4tZfS+kQ|t}pnYU4Dp4{#d0qgs>+;
zGmwrZnF7kxlXrJYMhVzydYGJ~De+~R8o*77<GJVqx<*H;FMhE@pclre!Y-czZy~~H
z`Li79r~r*l;-Q($${64qWkmr2kOoS6H!7A!n$=KL#gaxb3d+v)8^Sy5Qh6CyHfVuS
zBUzdR3aJ{81JhXIA|=`<lkhdKdH^FCc16s1CrPtfmL|(U$IBg(odb=UJ`zX+cklVn
zFS5oh9vddj@Y_e|I^ef=D{I$dIpfoOurdD3t4sExj5K5{Nu|YiNIxg02vi1L5$|8@
z-_`)=zVKNm@fM%7CEXy~spT@6t(F;1G+PLo!NL*7X~+)Nk0{Z#;0GV^Dp|39j}Mf*
zXx#aV3_F2rrkuE?dGf%jO6F<3TP42;1J;ZwTQ1+lLTj}&=}}0pWdBlk4}vsO)EiJ7
zIgz-;+;E|;mC_9)6^MG`HH{prC-QS?{C2<n4HER0yehpfay$@^l0TY2eE=&kMgC}M
zXvrTM|1?p&F_H_nJJyo7vv+K&PGUiW8oKe$#=~aw&%-90aoUN;DjfvXjX~0g0TQOE
z3Hqwo96!w25?GyHN8jOAXYwkwj(trJIi1pbMkHtk&?G(Sf9YUmt)tzQs;fY!)a5(Q
zb&Ug?0uzZXo(IzoW<O1Md~^}w8n38W)p%$Fs?}Sje2rNRHsN+~u^mzwr}<1Yu!un`
zVU6_uY{%jlITHGB_W?!$tZ$w&eaem|b2IPF#2G|_ZC}_M)}5}2UP34J3&7EEQ`So6
zoll`hJCH8E6MH4%Q`HkWR(W2Nx^&R>*XRiq?Rc40X#a`lGn7#izOx2_Dz-LYLGT=0
z7=b8;sXonKk0^w!B#ho*zkbL+;}bZPN8UZQ-KK5jn8Vtx-mC=tE37g-yD1t2#37K!
zRa*?*I_8m;FwI4oao;6_)5b+_WBqL|W@9)ds))_}dfS3oin<To^X5zM6!W0how{eb
zx_oF<%0{6@7(9T%8J@w~1*ZQ7A~GyE?M=MRCLyM=Galw6-b*y-#i4B|G!rYUv-d!h
z?rj|?L-K^*b{{cdI%@?5o%90y8Lr$}R{r;tStz%2D)zX8zD+fxG2PnNb22A3&iBIo
zhX*4Rws!shU{IsMVUE^7Q_p0D_rlh}t}e(ubT>P&NF$mk=`gncG76&!1ER%|6?<3A
zlfNgYfWIFi3*N4-Aksa+b$dH+!pLC7^ltujSU0i31En<)GGh05Q~m67sYc36uN*s2
zj0O#yA}A%4mA+4bwE5}GdH}RqIZA5fTg2jz2>4&8<m7)T0>}|^ieX;E0Xfd&`0|6-
zr)`k}{IS9>!xL#ae|=ioFIy;zygL==R%Y6U=m72r=SauR{V2y=X_8>Z0@52gkHdU+
z8L(lkhiuyj(kDk+3^t36B?1om(W>g$pmQ$L#bkn+;K@G-_bc64hU0VL+vgs7yX(I^
z_QUy8cNAt5t51}KcPx2_Jx=jgIk|(%xi`)unq1<>DRtpinfYg9TftJUS%E*ReU_?i
zW#O*uO3B`@oRVrsdDj1q9L_*KZXMGQqBaR_EqQiWuAFv9s^yzPPZwQt<ctO*zoC0V
z+en2xhTsgdbyn!hm7KbOXhp5(+WQ{lE7BRERA6Sv(NX)Jm$4<8g06EiIPcEUxzsmr
zM*O+!XITlN4QU>5d%yt{e6g$W{+n=8+W9Ce7E*)S<N*$#FU6|m4mB-PfY`AWzC*f@
zAeD6kDf%2>Gj7_rq{gu+7eEa)6rFf*pTM5TMGUvn8lPGjdsQ#)*j=2Rt0&edlyRPT
zK2J~1Lm5ObG=V@>k;qnkh-rD~e&yJpWT9fS?r_lIKFl`w|3|rf3k^zlnL%F}hCWwg
zLC=?Hc34Sx!4<1fPuA}|7nagyiW6FuM+ZC4@?Q}i2NY$dPc#pbh744j&*463`)KKM
zSU!5S3f31{)Pqde^CRhzD9ZJAn`t(!WOjZ-240BTM&@1y-|?7$<JH&AQ%C5zOtU7|
z&9_a!eSw)Dzk(0Ft)E=03Io}qP@z^qQ6EFII68+nev$+0DuUClJHr?4Ssoxxu(uXd
zES%=9+-e9WTL-{Pr4T<lArZ3d*vkKa++J7!*FzOdlVJdx=_h1!xMe))B!n^9Yz?3e
zZv>;2Tr4MDy4o%3L1;F>?WthQFSBLjnwTXf-;+NH+X!}H(l~)Oo)}@a6kUtcN{GEp
z2F^YZ)Sz2v8tKWU-v|ymCPY+uY6~&3Qrm>A`!?%hBw-~VpH}(XS|n`H4*VjIN87tE
z+KHfrBg=2!szM17#q<QV99#Oz@(h?_itO+`OCB{XhbhsL*n2L7yKRmjN(~(+#z9bV
zWGdMyShv@``k;!~C}aRKerwsY?NC8u$A=q`jthJKxjfy0%YRed*h0xtiO=3UVIr5R
zfP!Br$)oM=rRc{_`zvjpq82K#86e2uH0Gmh&dB!bnke)&M`vo;i}vaTJk#XLiF)|_
zVGHk-`?oK@AJpvU|C5~zM?yl|Y0I{=zK}YqBly+g@sfI9w^`Ca^5g-ZIYZnw@qE85
zzv)gD`bD8%ERPJc5cXJ~C~*7PRD<ceAhLdP99AD`ma3-e5{hH=+yg0TPW)_V*e_00
z(c0U|?4H6)KZlWS#~7YDoDtPlXR>2N-65^FRl97U=}8T2n!=;l5+?4<1{7V=mf3Ct
z24??>hXaus2RT?%^T-VsiK7`Wou?v&fXGUZCbFG^xkd=rX3iqUxg*y8k^nkZxfctT
z?ggt2o#Cn!ZV^Ywo~NIy2LHZ_zDdT(Nx6%ynb64=54zm>QGEAsQuC@l!#OPo2W3DP
zV7Yu}U#lH;hystDGX)B66koYY=?1Mi0T+pPozDex#&0%Swp_wCR^lkD%A(Si$Ok2n
z@;IjT&(%jK0B%0rk#`E89XE^wx&^hY2%%q3@?Vxaf{HMDH)vH$OWyXqSH4!rY4v?D
zlS;%AsGWf*Og(m}2>3U`xDHR2l@yOUE^`&xYl3{rHqBco@}7ARuwA$<!qNY4KGCah
z`&4e$m3$t|q!h}uC2O<7vvW#yfdFi+VH|mUS3%Fov9e@unFqS?u_CTwClx6kL#6^(
zgHS40^vz8NdC9@w+UoJXG@>{@g7d05OCU_^N>W?4IY3TFAG43?xt(;TVygbHHW*%Y
zim2P3Ajr5O)}3P;1hJpV=}G1h@~B&d0xE9yGpDPkyrWeq6GU>$)|y~QU2mDYwD1R7
z&^4$-Q!kCyYIHYMq}DZ%g+7$_yCcN}+Gp}`Y3-?kN;!BE?7;#PY<-Q^L}+T>a)U3l
zjM`tA&JssKZStM98&?F1O`(W;rp4BZMGSViIy9eeMp*-Ixp1-;f&Lw7PlhtS#qe6t
zMMn_d3{5^#{)3pM&y~p1K{!ev;}hmQ<NDm+wywEOigDn-p1xnli=T$D5r2#&by7(<
zqv72&xw_k-STP^F&VN~ncVkeYJNG<)i_(9L%t+r9(b<3hud~yx*T;Nc$ymt7pH=SI
z^bL_(DC71z-^zSMmq`8VsAwaw^IR8uf8H1d4a2%dMj~(Z*|wCB<aV8r@G8qr9*Vas
zxMbgBIaa+Fy1-3P0qUf)tJ{q!9CG=L4q5%xRF^#{Eb5nh$}tmDd5|Skj5v?ZHz?Vm
z>e7Bgn4T$i{1j38gL`)NkVfCY85x9-lhc&Dj-$(-$D)`ozQ3Z=yKa9{pw6U<4r|N%
z6thC-ATR~|T1cbAbs+v=&r$o@E_iYG$4umek`|85S|ucGuu`(qD>VodhY;jV^WVSE
zp$v^Y&R$2Y*ep^H=1|7~U1P1WI_DV_3&pfdWEfW~ivq0#d0Sw=cqDH5-_yB|z;7Q-
zIYlG=cUWRAlFimUgWGFg8kyM91naKBI9z|bvkN{mm~<#kfl&A8bLWg{C~2k_Bi#6-
z;-v&?=YR>@H>pZ_ASl5FX0N~sbUk*!#fp{a?4Ws?eE*Jr!H^&&w=-Y>sJD)P8#Nl+
zJ7^4<A+*xkKj6XwwX-2Tm-@V9sl(m!L^#&sR9_*=lw(Rxy8GH+n){si7SSEaTxGMV
zY<`g}%k6R@bh)iyZCaNAh1fECy7eFXCSVTAuZ&m)`%>HQoU?I1lW2<$1!5zVMz%!g
z^S2kbN#Ei88*0FC`O0#1V4C;FenYKUic19roR=-p@M{JQZmn3JMw+|ps)|Wn$#e61
zVX)zmlI$9{CU%<4<ScubntP<Cu{niM@OM@@1itM|!{j(nQ2*SbW?9wFRnHJHS%_*!
zZ*O=(XgpT0<(vHp@a34d!CEVqrc%e7E}L&)G7h(u0w)yN723-=6+m2-y_YndfUV++
zkj@&BfNHBCj0r0o3qwBZCr=^|92+w+@vrpmxRUZ=API=w>$V6Nrz|Me!y$)i#jfnE
zqHx$6gMdk`vwK!YX#6<@xQjktIq}`$!Ij3epN%n&29|D`NIekBs;nJMV<e-hKc;df
zP;idHRcFJ8I>8g;hnxZynAhcb6h&DIq*a_2`7_Lyg5e}gN&MumM{#|8UIXTF<%@tC
zKVsHtDCa7(3#tpgCZ2k1v#}w^mBfdOe0iX=n$C-a$A)_~Wun_@c-^4GP9=qk*lUiA
zNyB(f*4E%^gzrakW<RW7AfuR0k*wpM_Rqu*2?kj+(XQz$YBOwSAQ?~^@ij%xqkcf$
zzC~0$kg=QmWDNrZm-C~!u+GzfOqf)sA<fub7HQ|}Bo3ho0@ICHnBu2^;A**8<UueS
zGwi>tbYK(mo!_mt<QOAK69l-)unw2Qk3%b$yL3HT5IsH6#2m10OsS2k;}QEyi&w%d
zjgR%Fu0g_)PKmcq+N8^u=rOSpRP?8cMll!n<@*%#yAbTLBCMlP0pPiw!4c;emG!K^
z(N&iz{^OygMr}op=INj5{x>_Jm^|-N1Al=1;k$hBHLBLYRE1x4*F{GJ5lO7W=`HCn
ztQo;=`cNGWQWDY*RKh7Ff;Dh*pSod-H<b~Rpx&JWQ(3jM{no-ocf9O6ZRoRZ{B@}X
zX_jBAG`efn?ic_OthGy$6*WUX6rOB>x)YR3%fj)qy153gcc2@21wqeL%T*0{K(7lt
zBx0_BysnQLddJsVxRbB=^5bCI_S#gJpyY?ht5p*B4oy4Zy3l*94doRO|9M=igo*7T
zjnHW;J1~m#pL56;UkSPxOxSQ;p(B~M_fhdrPTXc(1Hqns%2yq#?TDnNhv6LmL6h%4
z(~H;59Ph(;gtRx~e1Z$YHD#SZ&32|;0PK@7PjGI$-6c2`NDZG_8~ZA%`QN%5581CX
zvUrzBm`_r=XE#^*%Xd`eRK%rmH5$H0dBnHfW6VOfC@(TVM#-FD5ly~iR>;C~1QJG^
zL{}pCN)9NP@s4g77grJgq}tUY*Lan&)x@KD$A2_Sag3n?O(c_YA`o4L??0ZD&V1EJ
z^mZ2%;xsg=vcYQl-8uwhRX$+|h*M1V2<8M)JW!N>`@TQY{}4hL0G}2WVK~f{Yl2;t
z3W#NvAgcXZIf;V3S1Cfr3o0GwgqXs?Y#7A!B2VZ@51=B~tWm5~xx0i3jdSf7-p+4z
zjQg*@bqB8^VyC2$bE#S3-ae>NOkg~&z$dV-D*XWHs<O;+o-ey7?*DK-YhqIGF&;<|
ztM^3r2~p$TsX>2To4SLxfK;z+;9C=_Q#?k21e*PG1{s;0-*cON0K?a3j<{#H%~TQS
zM5NVdb3h3hvCVFoP(rg9-TM!^`yz8=?3Le)=FflTBBFX};!5<;Wi*UrZzXS@1``)9
zV2jI9mc9v)yH487%QE5eVtQI~_kekGdIb%?AEwPzo(}G~P!)1-aF^b>NrT(VeYao=
zO%23&@@upOk&pexvz%G0+X*ZtytI5J(#sl8%V99v%J}u7+=lY!cG1EIL`@zTQr$ck
z_E+Sm$%v-?*6)vcn&zOG0g&S7$s^50Oi1v9$^EtV)++1-Hny2e(+Z~<3B!H^iJxGZ
zngFU*1vu=T9&ozDu2zKuc?88<AvJt~8*hkbSFi*;#?<+S-mQjWfmnr`e&Qv}rYTz~
z4@rK-AJ)h&Au9?6cOe{-NOh>bK|<&mDhi$kOR^V#VA46CQf8{wf5s=<hEGWAgzZ>(
zYa2>UB0k4o3U_d8aNxg0G_Sfuad^=lX;-=w$>D6Pvd^%Ma4!|Or0>D}fpVr@q_FKa
z6?EIa0%@o#HBDr}UPw9tz-6ug)4NZKtQ|J{G}6)A>pTHWVuI=x9NsNGLd;3Q$EqV!
z2?+xB2(UryZtfbKbx&WMSMy*!;C61uT5}R;Nzkr3m)HM%ChPUvl#tC=wA4<`mYvR8
zQy99iDTI}GD=4c{me4kOmC?m=v|xUjzOavaMV=5?JI01gL^=PufLbl-Q%K*47|wL_
zz3X80G^%^5y?ZW1k!|O=qA%3YuKsk-*l$Kxw(su*Cj8HQ*&m4;mP;7B3FEA<u6{3N
zO8qHX=F?UzOoV`y5S5`N*YKn+Dyyk&3mRb|+Y0zgi0adO8AG7bW*4bn7E<<!dLI*#
z)BX+L8DeiDqdC)PJ+1X|kfF-iP|R^=ZvJ<K+!zO>!<n@s%$fw5jXB-<39TALX{vs0
z^dILqdvG1kl^`o&MoH=~gvTYYXimedxB2Zb9jB<!Efa$UxyEofxwLdQl@Z3%u`J9H
zHyQYXf`*2bH7cMt!Xt^NwnH0HKZvKjjqo;DC*h_L1jz)X;X$5uV%|FqQ#Ej++1fo1
zn4iep>y<o42XF+Qjd11&v8~(=lO6*!#Jl1?cgc39=1Os&A$h=$D4MpAHGYy<QB8F6
zPVI#zpn%QU7q`_}4-nMp(LGg+0n}R9vrR0-Dr(%-a=XZ7Dt1wpt_TFW_FTmGP)rGC
zfJvnDGXk&$gRtqHHrKe`emVkHVpdLt*9CXpV5l4~pbazIY%uW3G<JVO-hJ;wKJo?t
zSi<L-r&}cNqZH&ncSEyYvLNZ~3VcrUC6Lgzj|BY!U1N`^@D5OAt0>$%+k^33i+$pR
ztNA*%*R90$cY+5a($QDOP8bhb+^j?TrxIuQZRnlhxYBp@m#;1xg*giSSB~V;iLH$v
zisK4?S3xwW2>eu?e9ni7+#Bo<ccd+#l^<pum0e%M2B90cNN<CQ$4FxmeST4Q1dmxZ
zhqMxIy`xHP`(9a05483smNmN9QV)*0gZMwgf!@gm*Ru-5Vl_y8gbHFkd1r{14QS%j
zL|tuSD-|Ol0}nO5(biO$p!T_<KWUUeI~XumY3Eyaxymn2n87=A{U%Ha{xG7#vzbn&
z6{ua2)f$_I_JU=SGX$zTXa_iLL$8ciEV?X0>;M;IX|XNz-Tty3$+XCN1=!T%CS!{+
z;~oXW0Nm@j3wxkj^||3+rmx>o_<OSw=%m_pN^TAF9;z$w;Q~ZY3#hFS5+`n+rKX@`
zlrOi5&Z%?*!?0?}FW@qM?X%VK_lXB{F7BL*T^-Ts+UCGMBN?Q*z6*?!p?jE;5a@eJ
z`|KIlO|q?GOn!eEZ(DydvoeLxHFHapK>SSM#c1jc7{(ei!C1PM%Qc_XrPL#o?#zsA
z!>2QQs#Otdi3Cl7#sQkDu=$4OQNbs4wkhzc^B!2oJJoJX{l3|`6xc@OEV9*y&tX||
z*`GsE5<IhZwA)dNaQGi&==zOU1iAtZSwn^<0wZ$1g{cR)A@2(hcyojedsub{i*kCL
zg<CZJ1^HO%j6$IU<#@<KL`F=LyH_ITX=xArL2r@GL!llx3THJ=Z%tuJIahLBcACvj
z*Y<7BST2~(?aS?Ss&=S-SFed&1R@<q(?6PGN>Lk!Z^s?7x9)c@;^K!=e5`=<HwjRI
z0gT5V_dW~Tym3@0+eM}pXZNfk-Qb%TvWoWy^Va*uy8(pflx&mHY%FR6ZQ@pFwjf-)
z&JH98#<a+JKx|(;u_5_7XnJ*fiNikCn=CN~q6Icc875L%{-sjaS$nC}1d>$)A6Tx?
z+nRQUWD0Ex?0<9rB{sVW;}*APDdCBc*?KIkgqq26z(^0xtlH9%x}BQDJ&fG1?Okkb
zqbu(t<l7+MvMJ`oOS&kTiqUWOA_83iwyQ3ZyjkawXmC}8oAB&G4DRAm0@);Qvqse_
z4;lq>6)`bP{Cs|5@JAH&`^9u!G>PJXpN`m=MhtG4Oh?1k_yuGAXhc5vzkci}JIJwx
z2<-o-Bt?7k(9%^m>;1RG!1OumOarU~^*k$vbt@76Dfx4|n$omf3Y&R)MhIZYQ9t4s
zU>Y&O&T1aYsnp={;pg-azKQ8?M{j;tSVbq^Kb?<$z0x&0p7=TRgjK@rR*^)PRW_Cl
znXCQE1moY?;OnZ8YP^RjbAEFMoj7O(XV~!JccF~?{AO=9jT*i||7y^uO}2qUr1gSG
zeO89J1dxp4uMx$*;Fw5(B`fT1J1DUo`NfCKCh|}p>VeHv3cht}J?~l(FF+=P0<{rN
zH%@8wIDY7hj<C$8`5hrf#?esbl}-ZMCn)7oBOyk8d?$<~0S25U-rRmkS{>dIcO$dY
zsm8>rGL)UdCw%FXptsCLiP%$Q&x+7XI`;@F5?%wI82IObBY)8GN!pZ|Ht^{VTTm8%
z@uQ}S=*<lKmU%;jxS{~9N+^gl8H`Op+PtBrH5v_L1~-Z-s$0HZpHf7o5&*62e@UIA
zN0OVQCXT}t768QT)+d)E592614qkrUE_@?=!qhB^x|VKmVN*^De>j6ya&c1&T_Wdx
zv8;|4fD0lv8EibssZvW9UtF}S@2ZR9($aunYPuj?L^$XhaKpO`lVXKzAMGJ@6P6Yp
z1p=stV$_?W76%WKhbzV**U6gEI$SD76s2{M3i9l{hTdB?)(fXm%|836<=1gs6`hmc
z_C!&x1OAfHLlz|pm&O`X=ADR~LWop`awe7brelvzY+8uHGRR<rZ)^GlB%=+KA<KOm
zYs_)DDmUOCj2HOVqRBqH`T}u>XLv~xU7AzWj@m61+>gA&st3j`a}WOzKDfx`*wm5^
zTx<CFKdjw5%d*V=g+uM_%udl7d;N05PsEmA{c)1Nc6o+1kAo7#c^Mk0>MweBKH{D^
zCi5Rgdom#Aysie`GwQ62r1UZ268xI(My)kXCOvb(DNb&GcXw24SG_>@=sFkdB$wT(
z((*YT<$XS%@FwSX$^`#iF{V-8Z#D<(m=~s?uI+X(!zH9-Y!<@aa>JGU!+VPS*I`q5
zB=t>{q)Y1z(He3I?Zo_9e$SpiHnQt=`JW0YGL3*9J*4J8dXvHziLbpHCq|U%h))f_
z=b0vEovph%1}MUO)e!hRZd|gR*W&If4EA5=$#K^LjV#jMoXmLUY(0LN@DMdOlx9-p
zOmNI&j|(Z^M7Ns#=DhU<KKW^xef?ZA7iZd@E&NSB{`w9qU_V?PcC)|_D#FsWuy-CD
zX?6D)mfmeO33gW5M1uFC6)t1q#{Ny4d;c=Z<=-f|lJYb6RmfKaDmNeasgV>;j6DQ#
zC?<F*ALh5ob%vWJKM+ALGyGFJX4mp_(D`55HDe*fkv3dYsHc>ct^3ClTVd#OM)C)@
zLk?T;`Y?_Ue<`wJyiI`c-8!z)^adPo@)3aUmQud_dj4^Q>gqKU2x*!Y=7Qd{C~Wkr
zR2k|`LH3&#rMzvB#kL3r;Ae<QG&;fyJot_UH>x-rlhomr5~%9m$W4X`nRTY3PKyiz
zHdCQdi1iUSr04$CM~P_m`kv3YodB0?y?rxTKvvplA3GZ1xDt2Q;z>g}EiTv_K{S0m
zYkYlQ{%8+6q;+IuE^I5Iy36;)6{(2x5<V)~9BIvq@-cOnuLg)Zh4yMKrtL{L%{+u@
zcn#1uW)8wsN;JQ@kZ*ZWZ`xx#A$1xC*f8}Suci!vz$HZr(=6m?U5(JlI}{c2>}j&~
zM!-pX-1Nf^;JSb=dXB-y$G6BMB81O(JY(>*CHGkKrt|0r=LeG-iXTrBwJwx@p)zE+
zQ(vP}F8mRO;Y2lyhXW^y7t#U*?T8R?L<>5nuv&GX6Rqn$u`-8>!qu7jQ-XYP{!Zm`
zp{5tHC+(*;G-0>C<wb60tMiS*K$3+`J`d*XNvbJ=wxta1q?Zd9I!D_2KF#;)<oy0^
z6R&5J4;Tc#5UAs|&lDs*_f&hlTkKkH#r;1zPqqLa`vQ|y)XKjx--tY~&>p}4xPMd|
z8^>2cv8Y|R)#ogTOYV?HWrnRpb$dJ(F{_6|k530xIxkthE-<Of>#j`vN=y@IjwONw
zibR6^K>q_XEq|J2A_n&dscHU(8h*yB^iX&zlQMzR7V)H3!QO=4V<$@mV(XvDEo?3S
zTw-pEMMploljzo_eXzTT`q0_>M+PWq?`PYxyHiP#1AK$-4s=d}*}Tv*AY<Y(*a@CB
zsN&bm=_Ii4+X*e=Plx?PFTtehfn^s_{h>wJQXz%jSew1jp|M_~ATAv$jX|Z?nt%63
z4#`SxZ|54Op1QX%he#v#RvibXcWJe86ut^mRsb>ThLgS0{|gG^^SQT7>Aka&y6^ge
zKK03C3ZEpJ@5zf*6$4$95yPaErz=9N1jf=9@KWXyXAVE<B&qHyEt_}z5xj$GZH#7T
z#q0p!^*hW(sOS5KQkZmoK*0-QYP+H7h1_^863!?5!Qlls)k+%p`YmzO`(2j*t(S_+
z&66gv8o2LTQl{?dXQ^x+uOnixrHe}NjHpqB=t#5XPaSgmuG#sS9zw&Vo;s6ZeNJx_
zG~5~T?Yv!191t&vTlslaS&uX<lDS$flgY=|Vk?77S!fx|5{oE*1EXY-sAJ>jbVo;9
zT8S_9Y%xR5oc+}e#TEHb3i6Ch9c+xa5vo9kMl9X4N2$x-pwrfB?c-igrNe(kAa;)1
zXQPIU@`7-eEU4QT#r>G=SX;fc8LmXH7ki>La$@b@F6;pUB95OZiA?w@n|Fd>z*QJ`
zrN)t!p2-6v*TuyoKCh~IGzoWabEzGi3wvXmHeE69oS4_1IO}TXuOJ;Wo@7iCjlYP5
z6_5c)o=9<Mwt8|ChN$C3z_AZ45W05pRq06&9}c^;4^*jQzBa=z5leLiecUpz7nnZb
zPf$C9j&em9nIq+WSQ-MA3+5(w-0bAD)?LreGE^a~{6Gs7ji++GB=qMvIrlQOZ^d?n
zHbv7+on&m>>$^THp4`pa?*^mN!dX#C3hE*fllO_nTz3RE0Y%#7+Exe0qI1~TU`Zs{
zzH}YdQ;7*|V|`RAKJ9X2f{=E()p!Sw5d}r6M^EiM1fOr-u&4T1+Ig!i=?sS~GP|-V
z!Zhsy!%%3dPQ}UF$R-O^jsAQXn?6j~2m?8U8WQ>4LID08K1%{&70JT8dLOg~(1NID
z?wH%d%lxParOOIAF~VL|@Q>i#s4;|x>a#`kk!>(xSN7sGcgt>tlDAc8Jo@=Eqd1<A
z_}3FeFAH5$aA5#=S*!&#iLpLdN0|1PQmsu^>ONE~VZHLDzxFV@5#{+>B4p21<IHBS
zrZ=^oTR+hNMH{cF;3}z(jBkMmSxwN^2@oV5+<H(=*c#uXYUl*IEhO>_oCJHXZVC<7
z0xL;QQJ`l+l1HE;OvjIc*t1k@bt;2O=y$RDj9HNZ_F;NvHJK(fieVT7K)vtbyurHI
z)2hD%z@>hI(HON63Wn+g>-2$H<7shl;PgHPwL_!41N0@^_L`D3Dj)f7iV0N#7Som)
z>JgdVGQT+{xFm!`Att4sNXDw%#;4wW&C(Mg2u-+cSC9~=+X9oZHnl&%5`jA~>drJz
zb&hRSPx8Hut!S%tdeo^d+1`A^c?*jEHIWzeJjm57gZP!DQk2L-1#*?7Z?GX~4DjNX
z4>^f$_GNk=P<VtF`x_80u%V&o&qUOhalGyq&^4WH>DVh3akM8a`GwZ4`HbdPNPZhJ
zcDj0S6aD;GkZBpup0WhQ4DAJAlC&YrjK&F6i7XCjSs!KOKXz8Xo(VY=#gJy+HP{_A
zg~T^M!J^gySdO~fp;n;WE+}Z|@QM+Cha>y{9!N&R3>vuC5Xyde*<!OX=s*w88C}7h
zklMle>{Vs_m~ncwW(B8^4R7o}?r~%Uc9iycJh8HA*J{cz1seyBfyXHXBc6-{_+F$0
znC6rgc}kQ3k&R?|uov#fN%VNF;nWoqMUs3p4KIuCO|Hms<StCRc&O7<&IJ4mi}qm7
z`RLISAy}s7^9^2|1As%nPUSIR9~rrh8^$K3tRV2~uuoIA>N%oCX5X&@usi<Rch?fo
z7S9{y$AtrOf!~kS<V#%a@g~!}^bz3~i+c3J`_2u?pP=HH3sTgiyvWJCMvaz7lC!-o
zLU-a*A!M9+VOAw-Y-+46`9gMKv+?t|Zct=TD`nO6e9a*w(3e`<`@=nMuE|z`Zj*;;
z+YOo=iL&k2%w{m$in6P=&AC|eN6@;*zD@9}3wbqTkeK_D1CUXVA}>KC7X=fW$n!G9
zM#r_2EeJajEhaV1paJErLx5Le0Ao-468?+RYq5I<*YU`EAUciH7v;-=^;fK{#kFe!
zRpXgqNoJM452oH(Kz0acvWa!e`Knq~uVdDP#IdzlEyWT$+|==7IOs!IAIiEB4@HIn
z7t2RKd}{zs($eq!J9ZRX6^fsw5WXw!9C4EAYkXh3r2CGHs;O-~#%D`)7Lhd^8-L(m
z<1X&KziQK|5TZpI0IM$r4R<Q`@Pm+^VXWX>^wVMsNw(GzjNnIm!6lIY-@qcCwC6Pa
z@AJ+>uc5~=&JXS=cA6WH&VMH&kn2cfzfp<l^<pvsc!t+cY44B`Hq#B=*LRtkRMhlH
zY5uEZ`zhN~KiU%%L>QvvTfXg#tW7MSYeX;IkpZeaAxD!f#y~HeXTD<Z4=~29OxF*@
zvu5CyA>Q?4lW;}(Qae&RV%KRaXsVLOXj5^yOm}X?iE*RIcTEEX3m-5w(d_Ql;~bwC
zSzT_IPtM)DjNT~AqfIZ9v+!=tq`B(@;*{pgF#FEzOzrc*HVRY4A~6q&rYG-t2YrD-
z6T(gfXo63|pg=^5+0*eL7%&rOuGDUK=NUac$;v?404ocq^**TAe7n|vVWmCc&cH`=
zA+wC$&d>bZsXmN8IQFjT=p4r|zgY9nyXI_?@3MNGZA>vuQz;%l(Nr5Z${CS7DHk?=
z@%HGI+J|!E+aBlk1TyBHpUY0~SHVO-^uCnZGZg-QBDrF7PkH8@$;%#Ti2GZ89dV3a
z<CzR~0?0?!ukS`**$O>n79&<0RMoM>DL=e%qmQDmy!UJT^Sc0w#XMuGjG75&F%-=V
z*qh+00C|@(oQEe5M-mcrp?rPoWt-rrZ=yg1;@`Z54}|wDz43>N2@tYR?d$x2Gzuht
zZi`U+j@>|l*IP`V@!lVDh8%EaK*0Fcz{bw3V^SO*XC)8{`7qB!gQ5_~0@%vvIW{?e
z1gISKFz~IrII(E8YDS7}@Lom{{GvrT$g$hK=I+>jgvHC<Vu@6&Fde`cO6;lvTuIY0
zUZo;hiof!+#U3*DYU*<dDL7=;bpMLxg?^yGKjSdY`JP8QG2@WCgdeG_&WBBpC7q?)
zg05y<5GD+x-Jg>i5=S_76Xe3NLA-xtPd^^h?)7EBASqcM-i*07j43{jNh_K;=}lqH
zatT_p@XOyb37AgRsBZ}Q2y7Uz!o|AGLr#6jf}MQ=n<NO)0iZL<{?*hxm)#r$fMYo|
zIvI!?<duB=0#>mHGQN_vw~Jo>koIlmGp}>HK7fvzIx=wws`%%h`1Yz|E#>iO$}=1I
zkW)jwdfV*<w;Reh$pJ~j%WD3Df(NtUJkNj9dUw++hVk2!e0GgXE={BeQ66A^%lk82
zsO1UNbHFTQj~<RhQE>j)OCD&N|C$l?yZqmU^vx?JF{_UP<0h~@9)!6&;bDRWid-8q
ziZ&#5!C-Y5Glu@GZttO)13kxrwic6}+ZNlk%Zn|#y`;KQ=tTp9c+v!{c6Ef{!tsKj
zRANvBP=?YhnVDvSiH0^%WHOF2FK7>(rew=Ad<{WBbifyx9bwo?-Z`?fPCa*&GCHRR
zy}w}R1ZD$vDw(iU1K|6T@w!_#3b)~J@#ENDjzfukLO<$NSctsH$xI`c&JmlC^h}J<
z7w@`oFFCeB)6V4^C(&KQWnSzQALH$OAr{3EttD=wEdX-{>fcZNYEIfrg0E@9-!zB>
zkP~wNA%!T=X$@e3)VbO%sU*2Uln*7;8WPx0^R?zGnv$~Vhlh6Q{2I%9cUA7IE`_sK
z&Tid_cs{8Vl*vBAnAEU0c9!a)_4EPClCI5<M82Q0T+?3&kBg;KVinj0%<CMT&27Lw
z(kko0u-1)pBpYj5fAeeOngu59>Ex0>ur$ne650f<1Vf7U@K3Fxj9w#*>y&N_E*Var
z)J5pB&hQwb%?FZT?gp5POuM0V7i(?pC<N;#Q~Foegp3AC{N!@TK$*JJ2H?hvPOk&v
zdxUYhw$f~3CTJ+bAoq`Q*!eNb{T39SKRZ2x&z0ZM45fDh$Vw6Eb^S3q$`h#tU&0f*
zB`z@8;gL2=XQt8zE8e7X)Q*ZU_0B?FYI9C)jXedob_io-=1UW0_{ZVnu0`lHlf*I<
z876e0ISdf~hm1T7m>E4)4I(2E5*S4L*T{vS&8$|g6zGy&I|9S+8vCJwDy`Q*F(^k)
zKRZk#F-9Lk<b$AiBYzyHcytt>(A9732%-<W$A@@i1)bzcG;X~Vx_u?3N&i=~qO1EM
z@P@lWZJbXNHRXKo>Jj!~(<9Aaywmeqe*7yED6vlU7A$yc9DMeLb{(u*ow~@ysy`lW
zW9`yXcmW(L?amJ4+!UK2dIJJ2*w1Cp)M`9A-9ti7lhX{Pt!{ByX?S`6F{9|7Dx-s`
z$WAc(KoNXMzj|4B){`OX4>I?0C)sL@1~kJQi)Q5!XGGWp&#*wsywxYFEvMw;IKPwP
zirFw1Xpuse6W**ssMKsTzRl=rz?vqgW^U)XE)P`%KBoL)M1p5%`yG=_l5FvIKT8kd
z*kyu!MPraPdDBF^-LGLEnzfG}$Y5*fS$5p;5ngPb0O;QD5i1PR9%*Irp0qTMyqpZo
zKz@M9vv(Mtq%SJ0Mya+5e5lP@ynTq9{zs9pROBCxy{fpq7uc~&{23GS8FGQg17qJ*
zq=r2RJY78CfJ6T@q(SV&38d5tB!zjOUT}Re-!kv|yB5L`Aui^--6(0Jdd)9FL>g^c
zseA4Tu}qx~74V<V+ju~aY)U4kL9?44>DisS`0#e{1--3cS~3Fc&FE$C^|-IRA28RP
zes(B?9Kr-B&Ve(<%T1cMgmpqn21kAgywEI5`f~iKND*u!NTQZ1I>Z^aJQ3h%qv_y*
zALBVv{C)va-h<W|ai!X6=>n;yWD6^M;6;LC9Gll~P2{X06bypPf@EAH-|nq}YQN)p
z0^ME1$PEXs&6Y}>7*bv_#Y&-|+y|k;$nZ$P=uTdKxHAiKy&puyGgU`*8*YbpJJ8F%
zZql(U%L3;0;m>q4>&c1iwr_AYz=Vq?+n{V&>7Ni}#Xgu=NhmYLshy1x9o12GwSb;D
zb7s>Dpyv9eOzNE0Zf=#&>^WFS0#%%wESV!diP7(;30N$yOAz{m#ic-qBwghY;12oG
zDvDDsk3X5r#M&dgmLhny+|XXWbBrhhGOjlQh9oKELEsGGq~d&e|1(P++--Bfs9p~{
zS&(#HaWgXtB#aUQndLO4-xucCLhSMqb5p&i{qS@Q(`F7#(#ft(Im+*lsoXcur=&Mo
zF-dLMAE@?|LLV!HqhAGEBot5PnBgEiiO{Q$(4BHIn>DD}6~YcW-$(l3v-zo&SQbG$
zc!t<nHcoet{CscP*Sd;)*%dEQM*5uN?7Ti4r&Mgzaxw(L$+e56AFWip01<DRt&p~7
z1+0~l+)kra*^NBPk=_49D;vj<&_p0inKp7qw730EXZk?6SlSRKxQL_=B<fB733YmM
zz8gKr>N*RPlQ8{PD;PU|N`PND0L16WeJbR@e%qL})50&32WEGvwz`nE3?7;0ayS@1
zBmh-3jn3TV>S%OMLHrU8F58Nd@hrtH7iZi(sxiIEx$#71)gCwf$7MN(vcw~WT<E)u
zYTiBU=(YPfCsT-GB)xqHTj-X3la6Qy>tcdivL(rwL+Ge$2WP$35*#66k3_*K^sR#p
zBz3VBm)*@s%cN@{Uo=2h-5`|?w9<_enWy7+s_cPVnOr@W3F`&afUe`lOhDX*38CVj
zH;mj7xy)R{*dc$DTNAyBva&#bI_$NSl3t|AcM3J=-OX%J|Ne4*<;Ro`7z?ocbnQXX
zaMXeDaik?XkQwJ(J>s;trOZL|75H4AR6Ow9rI&^;YA?|r_msX7@gGoTrX8JZoV?rT
zwmU|gS^{!<r1U6KQi**8B@9lc@fj~^cB})vrl2K6+r0eY`#IN0o9e@C2lj|g^8aLi
zcI@CN^Q*=|bAV%<iIQzODQT_PuHWNYqVMn}HNiTuL$(GC{Y7z~jvvq4S3QjIZWN)m
z4+6N1PHBYvYOw#d1|Gj#<#X>nCD!)ZDXX^`;v4xajTY(ji3$sS(Xw)?t~zVC857cA
z1$kfyn>-t?2H{P8-R?x|{RmJ0Q5#<^Ltl_RwLw{rOxZ<bRD9jbNUUhVNPq41vp?w}
zrg-|&(sVsXdzZvibItBP)!Y?s<K|%(<MY6#el5)MaUw<AHd$PhQD3RREl>M^zqF<Y
z9PV%|maDakxyIt7YrU0b7)FNu(`PGB{;>G=nxMINX4w#?OqZ4)&`RLW!yds=m33h@
zQ-|P3TU`*F8ooR(POyNyiPtwon;T!hxV?C;vfKt@QurM$uY?Z>5qN@AB_4-Qq~lq$
zN4$}Kb7wp5FjgljMDrKrzSHs+>I8F{+O2NkgybKaH7bOm2KzZIId@V;<!LnYiO+xO
z{65ZGNRe$|j-5~`9AnoB*VaWSa|KV{eZR{+sPLY>%1aS08gWgZh{T_M)_N=PL`5|)
zsR-JtfV(AkTggb~d>(k6G!r((=i~y+HqHg4l<G{Bz%zZ+#9n$VJ|5cjO>S*8@-N(0
zH}F(qa210keIN<fr3WBp?ndtV3T?3xY+sw*8u<4CtlrTi_3&;kuA;c+bL}b288eIT
z>WI!7rY>0@$<hWU?7!3=Dy6w|>|qh>=Z6SLiXf@Y(jCMF>T#UH0DXzxM2d33aY~q=
zI%BgGpw#7(z}re7T?V&@Pq?Oe9^2Ui0Ro)&oI{ywS%$XFfcLt$)ykh=$p2iMj|+2c
z_WOW+asLuSu{x$1Sf$2A1*~FL<p_h?0ri1B`5uUz!yr6e%PvI35=)=YnV@x?A?!vD
zn>&7bWp6SLup5c&(?%1#P6t^e?pG%L^YB(?^2;(_#@p}1U`?hnCB%1;^tdsF2(xNS
zWD*PNq1%>5#-f65&^$9!@6oamLW;opyR*Eq{Tmyu9woFN8{3oCCxfO7m^3GKy*S~O
zhxo0M$J;i`Ml7OA!SSxoW=LhJ!J`--WX(g2r7df3oAsYJlG4CE+E#-(I%4Zt3O%qG
zzWB96<}$~e`p-Y5TDdc+iWRXoCjeLJmglI(7Iu1vd1u8!i+A#VbYzA65!t&@K1<wC
zxdAx_SNb(m7NC~>2wlchp<A9>&sE~Dd8vB*t>p39Xo8jU%?4bgT(>S)9yQ;T$(Wo+
zKq9gTY50;(T$sx}54Xf~+m)TJ(j@<Qs@g0rA=nYdMPclZC^Uq=u$c<(i+17?j&x%K
zvxJa$sEaNFxNWZ~b>@2!?y_fe?ayg=iu)Xga=L&e6p}FZN9Q?qNTfA;DITWK<&(c5
z7XSsd1qgf@R8(=-R>cwjhUG!+;)INBbh#wWc-yAb=(IXk?bLqd=O(CnyMEY%;2U|A
z##BIC((9fmK9;&d?UoS`Z~Sk7uN7HzUE%~)ZLpzCvjh>BU#CIvDF?~sBbJ`O9GL`b
zFkh?=fSqMAVP|wL<RJQpNFWD-ZrBs5vt6kKJXkZp1n(M>*6iX!AIrS5<!v=)pl6Z%
z@}t99TEyf4-=xi(qALM_h5AG*EBA2UBeL)y$<q0ebo!h1^!YFz$(E*@^a&xscc(Qe
zh6Ig_%Ah@Pz{1Zh>pArrO?T2Cj`Qr`c#q;RF}G|XBS_YxAAhZW(>>u0$74G<Xt7tx
zY^vCzgUJJ@o7f(yYsGpWeTWy1&lz)w!d`FRxLY_4+VHOMv2<$Nu=XqCNg}c-V!Qt<
z%gS3&MKX<Lh@CKAoCzJjm-42kU}o_xK~WkaVkt_sP>f!1ly(Us`lYeXzISBEw{MzL
zt@UP6j{`u|xu`<+bYdv`Xs}F9N1a}2Jf=A5_PS~r&iDKCZT@@qo}0ATA3dr~{iqM=
z2aKTpxuz9XXYa)fveF%szP!5uMk6ud;Dlv~0Y5mv$6#j6X(9Bb;AXn+;AO&Ce{buJ
zPvhE#Y4*Z{CP(5g7OZ0bGAA5Rd~z-5pM)N_y)sG~T<vpUp^q7i#0wr_WlmetEaWIc
zzUiz3c2u1Wjg#n4Z6l8%Oa7Pdm!$o5haSBx<I(A=OIHhIRTfzeF=86OGEDRKIvz)!
z9QfT*)TS8%XG+zTXC8$6NcJ$(Jqq^^UszM<r_ofgtjEEf<f1)tPPmS#sC4f9`$X<T
zWfxJ#A1vzTQ%if~pqOD?9ddn&L!s%j`!AZUB;p*a_nZe|>;TV4;x6q@@XP4AJM<GQ
z1#h~C`K-9ka_lAt3=pi7W3_q|$*QPBQOmi%44pCfX$@l4M4_E`Mxq`m%V6p`Bc>CG
zqJ{UItaeB!7#`g<CIWJ#x(j8V>wC7|6&@iN@n*YhIVTM%Y0j%)SC*7Avb0Hn3fo9=
z^lawOp!?R1e&1pDPftxV;{f^DU;nYPYL@JpjQ}I__5=@^5)7BSx6+q}IW6+KBAH`<
z2QaKWHMleP(7CRhp4Y&KeK;r%KAWC5N$-uo)D9(i5Ft1$D0ajQsG4(@4D}S)w_&bC
zaVCCKU>zr>z7|O+uIY$F+0if_7G<rq5?kL=;A=*+G_tktdV$%vkv=V_KyHJvu;E;0
z>{5D0*703io+{WvG!v-^TTX!{b@OH>F18w9hDI8_s(70ZjcC==0grAikN@WIWu(@P
zgp&pQZf25T$W<Lva`AVGE@Kj9SeR9|xm2sXX#CZbH+Vci?!3S)D8@)fiL4>}J;+0y
z)+I@X_P5w=ym5DIEW>i5S|%)s>A@=+w5OQIJsL|S$E(2oa+I-Kp5?VloA6J7-FN|p
z%fl9m;#AD3tZ&hX%bYo{f#5T<R>P{&yt~nB%1@_Q4h(CRicVqTZ7fSmi-uVh)J^!C
z-D-@b<VEM<B$*)W4+#z3o?4V4kYHW|-Wnq}>y#$YGMbW;=HW@TINk6BfolRdifwMQ
zmzy{HVNzVu;5(Oin_+)w8a@BE^LW$i?jB<{Yv6D*dqlpc8_74x@`DHc>XiNRoV3on
zy{Y+rMItLTp-&6PG%46qB};(jlm8^<fe(QRj+OLL#;6jZ#Fs8x@vDvK+b87^t<d4$
z#@cXyyh4;SKSUQ-7Q-L01!yB-%IroDGVT`H#l07i>Hj&%-)WifjqQq#lSi^_xbhbX
zf{K`i4jnWBLbfRZNf4U{uqo?qvKS1!7>ig|G_|gz5N11)$X}8@WSv21rL;4RsuN@W
ze37;BwGM(CsOnT|IE<F6SE0tycMdf=+;u0U<Gy!ySGK$*TFy=sU_9PAv<V=pm}EBb
zZeV{moU#&ATeScJ23S_8CcRg-i7qTC9bB)Fs+GtAzB*h~hw*Pm!mG-Y<CXj-aA&JF
zpb;^5zu124wReLgZ*H=!lajm470GL3oqc0KX6?fz5fiEv%4%uDo3r^l*xArIWRxTJ
z?m=qPe-~nMhcXr#`a!g3OIT^v9KE?kKee<Q^$Q-vtm!Ph4nAp*GNWj$zu%+fV_cEe
zBlG6|bFQ2aSOPMga;mHWyn4w{xG<Cs#x<}Lth|}?0F=-0SPectuWFAm$mKg%-A&pP
zR2(>*jlTCn^SA((QVMMxkVxj8F{L%lhNL+g+`46SX|r?_qBGnLs3DXS|I*K<D@{TQ
zX8vc_4ox@wO%tdv9C$N(2Mvgcn*Rq(ZSrIHF0WMe+!M41*(Z1)+#6D{>*L9Mz3W1?
zQFLA4j)NM@Ns|(nURRwUy(s3hkf?(l;#*Bx{%x;oa`m#P_kIM}<+Zb92qo48V-dT6
zosLwQ6<RWD61CYfjgk$`Il0+RG7dzGKw)7-xOXv@{F~LlDw;i?3>dY9>9plB`vNvF
zmlbhY*g<cn9+73%FuYt$fiWk6V$deQLXMri3w2>5o&&$>^$qG+{?_;N@G2)5J7N3{
zuoXJGtJ0Wl;`kcumb1c{V>uAe4E-PRe*S6~(R1eKi%|PhR<&d?UR5s17&7%z#C`DZ
z4Qp?takmsPoz7c;8#le`Ch7e{Vfh!Ke~z|fQNa6@4x*$;!o@a<_k;(L^o&1~I|z0V
z=<4AtPu@UC__DE^Z@aQ9vzn4?M`?fnAG>X-w+fTfq{Unw5@YNmyM2_2FyYxXJ4hSg
z`Ph7%<_;5|V!c)}rcntReJ8Ata0{Ms0tODYjSH0@u!AUOUwSOeybdK5MdS?rEEs@p
zdl$OMV>rN<wS*UUHrFkz2l82lE5J`JTDjt$EU9O@_;N}R9LRVzd9D$oY|>sN-)g)v
z87?q&WLA=kt{YQB2<b7MM4H*u{l}rGi&5Tq5{)uXRvw~VB84nEBUus;KFqHQ{u*|R
zBn9-4Yzu_qPAP(Q$p$8+Bo9Xmk`!y6x9+dN7}0hBrP9P)$0fM~G!SQ%?eElVM+lnb
z8x)Lbb8&g<dA=5Gnnh@M<wVawt5$Fu3gC=E!h1u6ve}pZlHKtGLT>BH+4}{$wm1`k
zRG|7{ueMp6JcVyaZe$!QPg0JBb~IA>mWkfs0kT#<gXZQ}Ic=+cnbnlS1FOMU2munc
z#H<C;q4E+^o||5P2J4{OhP*BN6MHVgGb2xkZ+!h~nHqt>J9Y3yq~kS9)*teBm>-?k
zz{rAtJW#W!YH^OvmlEXe%B3OV9l*4lk~ptpwG+TAUz|?_{HWwA6(um6wB_4N0subu
z6~B!>1{{k2R&m>UegYY-Wv^@QEP;(sX&)Y03E;-|u=ddN{*eZUWsXwFAbdB1z?7I5
z?fa!bU8iB_;-E}qZo!M7z|h3V@vObH9-16JG>Xr~bZs7J@6dw5tt&`o5{A;gFmMtp
z(BpM?)PC`J6@3fl1DfpJ58g&#P-PSyiJi(kBkz6_6Mq|6Fh&S_L|F{HHG+`1dLuO%
z#`m#H!qSQqb9s6MVi89pJpx-d1GeXV1H@#yo6?HWpO$m0@Go>V7~1$Z*!V<W2dybF
zjcbAAUOfp*!6%xfM<%PyKOx~Ua{Op`5M#Zpe7?3eO~dQQd8|9penZY1^u#^@rgSy~
z%!XCuNs1Vd?X*y)oxivb2a9C`58RSUcF-3QK^s)b*dt+i)p7YtclalfZoMI|B;7ud
zb#7>nb#okE)x<F@W<SKq*9MgwUbYqDCz?|2JV1COo4`6hVWL<Sb`6}}Bfc)%IPBMH
zP^!5(hMj4HCKO8-=QTM7%SS_}z7p$qfH3SGw5Ne?ALS|;>#0@^>X3Q}pr5rk?%wz7
z4<p^YZ8S@Piqt{gqXYFo(wS}XLD=)fxz27(9Pt}ZvE1dCb$8tD1f;5eeaNeo?X^hy
zOS)dez6~nQXF2io{^7N}#1Mzii@g>ar5@#_Z}*|R*+F_WPMzc-N8vkdm7ge+n75Yy
zDSZ;)5L$)bI;LBwoi`m4M}W9lEzjtmpj4Dq#<L--0!GzDuidwJS8DacVI#lm_}!b4
zu)f+N6X@ni!HJV8qB>4DbeEY{ez$Gy2bY5RB4weZnmmwW91!wep9u*tv_NfxH)qQ(
zi@2THMCu!D&Fyi~l+I84-h*GUCRh~<<w~!=z9#=ulg82(jwe^|!!S)gVx-1v*+S$-
z4<7hg<x}-;6l_iWS=zo`&QDi7p|EW(K#}fh`w87Mzz!g-&(ah+A38cW@dOcaV;_K<
zrK`!!!j1y}l7DGaL-y=J)%^1H$H`B69VwgaM_Oks7FLN@5}#&2N<EO*H_gwbQH?}L
zG_>eB;FuIC&M(XEq0Ze;+}TXer8NGgoZl;`|47<dN*TH8Bi`$lgtbutaITUv-~{j}
zz=ik$YX_f2fN>OxT!vNRN(q3vX*g>Scz6E;Vod(79O?s_cj2(<p5L?cu_@8lbiq2D
z=GJfh)*;EYRQHj}#xDhI5XCLvmY|e*SD5^FFRT=DDgz?BS&f)n#Vi``cvz_7grwbw
zoHl3^NyHR5op|{>XP}VeieyAcE<K6;VXNyOp{->g0RaBC=qFd+z)+bXqO)&{&`4BZ
zhDPp}{I&PE^|DPV=;1lwQh0(_s}_O11rSe(07;m1oRnw|#|AAo5ToP}(f--o7;A+I
z2kmf?34}~vlsLp`@z!kC;{}vHkkX1n(tPXk$YzSP@PkD|gI6B_30p5HXyg`wmfy`*
zZg9;tu#)hkpSZ}V7mi-RhFcJz^fkhAC@lIhcd_h?L^<nukr%G|VXt3Jz{}1;K;xvy
zZPfn&?QMU`Xu;2yIOJzoFVme-Q#Ky@4*IXFWYh{V+xL)=>Lb2Ju`c6mN=#7Uk@JY8
zloK8^`y3WYvpzcP&Q^_NWbg_rc)#v0X@xe_?n_`Kz&Y^fvL;&Y$(MpS-<rIUwBLk*
z%L3w6MV=4jgzSiEE`70H?PqKyC40lmQyWl8ECEjW!yJ<o{g~FPT|iPEG<*3R*9z<{
z`<vovDk2URA`t%OA75_h(1Y>}ETd#B4wgan=(%FMB8_lZ6)3fI`WS(grd65B=vXR=
znv4wp*H3<RrM1Km7+<z|moUC^gt$oR<z&I+dBtgc94|fFJoC$@zJHG`q+7Mk)T$jS
zk+feYmwyi4k4Ouk^O3IT2UGU&VcrA0th{_j)SW(w+a7D9Et3J0KXbWv&EQG#L@kq1
z*eb=SI>sH6;wcRiL2!o#TQ~ymz)A?_T!LU!5U&Y>_>YC?A|w}sY7dCF+j3=Ov_r4^
zQuGh8W~tFmfDhN1lt>y`BGxj+K_hu622V02u^@90QM5=>1q^c&7ABAXu0jhi2VfOG
zBiM8NJkdIwLx9$}v0+mz$0a^l&QcjS+Uy+~HE|Ej8>Vgfp0_N=3Srvsio_unahSsL
zCkUx_SK+l=W91iLjF%JvwMwH1WgIGS<>!c69iaWusV&tbV9mVj&9)3Z&?2#WZkyK^
z5>JtJhr#rU+0@1hcP=*9d}VmmD`aW$Y*vj7B=L!cxy6Wn?Iz@m0iXkhCG`}Day9S0
zQ~i1{ANVo^z&|!C?c>X6G~H9zl0NyQ#7T}ukH513T~0K<F&1P~%z9#-gtwE?>2k>G
zUKMF;E>Mrzh;}r6?kL-ihO7Juhpz+4-FLy+TufrrZ$P(7|FFsn0QD~QTQBPiO)fxX
z(Dtt!F`yJT0ofmyBJyB7j|^Hg3USyZEG=C7J&dvjjCX)<N`jdc$ppJ&rjrc%>=z_S
zJD|!<e$7pMe(VSJuTwqc5}@Lgga&|veEd|qfKi3qksyz)hjI2l#G=vH1pw^>gUcqQ
z)l=9}a<!lSGY_A~Jw;=S2I(0}916^)pW*{(-EqNK!b}|UgZbBVe~VqFMsYIB{$&G1
ztBR<GR_;Bsv4&>|0~w@Ljf7*Ff(M2V?Fe4b6?X@YTgsM3rG+KDylQ)MmI6db6z8ME
zWb?J_&p8MxRXv1>{6kR<>AK$vW!(B4D~O=|^9M1{T12yE<&Vh5+{xhJLsE?4<|4kr
z^MnJ5%II@Tl7|^DdyQH3P(ORz9t`CXb~GzesEhTz?(k49EMP0)L&5y82Uc5LrM~HK
zUZ`D3jC$Mk(Bm}V%~=V-Gv08b+T4S?BPl}V&X#wL!>v+0k??<JK){LSCY+^|5WAVS
z^%MyhPQ1{nCFZxyDEwc$pCTVA4KA=k$|NtseiAMS=YV#bXcLwz<$n~gGi*V^id;$U
z9T0NjkW2by7ys}Q6<=ZQW0DnQe?G&^3kM*My_Nd+7_d=863_d=op=o$Z3XOq)$oGB
zP}TFm57|U0n?=Vq3vt=-oyg3#y!8zW)H#DE^w$h2Seonzkp5@uqd9>*>*UGZ#owdq
zCT~}veLU9+;I?V!^t=~7#F#kvjzC9AV>>X?Qh7@6n6!suFQy%1bY9~VT5Ny_@>%cA
z0Ns@`P@^}WjWL^6JucMM3j;y!>EjYNNR%zu!NQlN%CIi7h%zrXSjX5$x-kN&<^N3&
z%pmHnND78m5ewd{bE5LhNE<@X@1D9GH<HMX(T%}@1Sv({N;;=>V0C3Q4hF#MC+1@Q
z?~o%m0*aaRE~PY}KLH*6+K>*?c_Sl&KZjsC=MLs3<Ef}&bak9rGv<7=%Zj;s`WB<5
z1?d^88J5PZ6;Wn?94enn2$yGc68)noU2vxfx^psg)~dSmru*J(E%ZGZJV-bu{Mx8?
z?Y^SU1M4|kq!caiPh@16mT`d0)mXyct^j*%@h`nPxd?L2IQFyWg3}*M!C$zWrfSaf
z9`Bq-(M)qhnmKoKKczLwPnEIWo?bc^3HdUCn#0>LXEhn$7~I3cdV-J9>$p{;pt08M
z8n|&3zB{?S1TEdVn3c(_ZgG%j7svtpy*hTI136$<UD0U#;*(`KW5!#_E9J2}sUkSb
z=b%IDzkU4?p+d1#uKzFwzDzSvTBzLtbt2M~9A}+eTPC$RocR&CYpfr>c+L~oo4F8P
z5iK?#gf-r#NLDogrM?5LMOB@O9mso3x4MaL-XBOEiYLn*r6ma($3$m3^vv}1i%mm@
zJyCnb9|rmbksIEoVsike`1N@{{mw3tfA%3gy+?9&u6dh?*>->&QkneUc7^jLM#ro_
z2P#~(4a|XAYd#|Sv^=UAT=9cJcMVz4i~k(&hoT>fV3EwMZH>$|3`fp-*X<kw`X2u^
zIGopS-?4xHRc-QGPWYy5d>;b0xL$Jp6?fCVY^Lsfr=en@iEyg_Lm(?@Y2m;EMI7Yp
zk#=+92Xac&<V49Eao>fab_a`)$xaIz*+2|^OUs|&JK(x_x@r<2p6%vWPk`WGF>=s2
zA^QaOOXxvQNtP6yy5H{5paic#$p^+~orl|BFYV=xzo&!Obu~jB&+?ss7t#Sa3bd%^
z&py4grDh`W$%!zUZS>%v(5k_Y8hVGVwMTy5M>A?eV$^XtXa8y^BE@wnC_!{ik=Utq
zEY<%*qmf`C<<HFwa{vcGPuD6O?g$A!9y*^4u^65fLYLfqG-*-dHgOY#a;GgmCi8Ja
zp8*izDHJzvU5Jni=Xdl;(zniUU%c*5=&?AW_FHvP!`ZOY1t6{q&-i9LB_jSM=!67%
zy8wkM>@?$y$kbsC^psjQ&d!Ki?A|lzINqq^1rX4-M4EDc#?a5e-3twkR+HUx$PEEa
zL4yR;(XZ$0Je=y8*hXy*7qcJBuM)pIT<?u(T6>uu)>|Afx4~BrZd1!frHDs_@2Mvf
zJF$kk%%?aWg^`QX-n6Ct_Zgc92O1wj$F}NPg8juGMD3zb%-uoXP!x~QWBlNK?6W*9
zOe{QP(+#fn6My=7@c3VtY@)+hB}Iyy2Ic{F%y$psQ%eziVRf32eP)$``W-A<)K-><
z`5R_Hw*F;6L;2eH+-eHvpnSwugRP%F%;L<D2P$*W(!ek3$0RaW=x1htN*v7FOA#hv
z=impzJ!46s5EC)0Co91649~CRQW-Q&-WiL;pHKCQkaSf2Xl%3}25QRJ#m8<aQey&r
z28rA~{kZ?AbgBu${##0^q~=+T5KYI`P&@$o)=0$Ta^)7*Pj3QVHlT6Cj%WN{%xb?*
zm+uR^KUZN(^*61p1Upbuv0oJeS=5KbR$usuQLh&%PzwqT!!J<xg^EXh`9+a>22b1L
zx>ob|XWjkR$C%6H(eCsKHPQDwHf;mKnap*b1qQ7ADKbchs*eigI*NKRV@y}sPluC|
z6hP@IHyw<(F@gq;1Id%Ektm5hm*ki4l?1Yf8C6!HY2}FdH<AC^HN$IY9Q}%<O4w`m
zkn1GvrYTfIeRZJ|gIALo*}V9vPTNFJ0{+!I8zV^^thUrJ5s5GogwH3&Tm2Y>P;O8_
zVRfD6`9SIe3x>!4@kbNmi}>}!&d;qYz=l@AJP>tcsymK(*Kuy`*6p<2=<Ru6R&e&#
zfY-|UM2C>w4h0r<IV|8nOyzVj8vAth{1gczsh~_z1s>zO$A@dDdlAvwc-%D~Oxi4B
zUBo&X7&!=~Dulyhd&R`N9wfJ=tFtis9|;-A>N4>|yoArUb0~qwL>cJCofrQn9B9xH
zP<F*TC3ArWKB7^jy6sf<EB&y$5mj&U^{sq41XCMhs@~ea?phgvOZpV8>IPEZ7|Ur<
zDjKWESGtV>{T-G+8wRXt%aO@RoF%5Et>9eR^(&8KQ~^ys3Bi{m__UpadZgD>d}77E
zf8sl_4BiVEBo<Ye;=mVR?GGd~AuQGv_oYfzEnd)voN@4{X{#!QdNa^ek9ckovfeN0
zB&W59@AoKi*>6ffq))Qkp5l7dM}vJwE$+YrRBQ!b!YJj)E1^4-h=DPs0UvlG2b#ca
zEJ17+t9<cT7!TQgH+{kuSYtyF0M=S01uT&DuLzxMn9fU^U%jE+y`hVjD(JY1)CTU5
zx-JI8LFx%ZX$gK=7p6Zx^!*@<5y{7HvfcYt&#!M^brDR!{D1<&ZLar3al1D^LJoYH
zu?@f%$wib0e-nk;1nd(8)2y8?GVaJlHevL%g7PqIRp|G<qijMbM8U22br5U8!C9lo
zPOcf&a^p3pF7h*UntyXC$t?Xj4TFnBTW-}P(#V$Mnq$-A-W=~P#YWfu7kIV_DtO;m
zo9AZgYg4+5aQ1Jria6gT0uHLnfN1dJh;AlhWw3bBOJaut3Q;XN=M)8xkK<qjhBhvh
zV9O&v?Ko8v8Vn5uNRT>T50r88K&UkpD_j&6?=>KyEOvC$y&pyH&%MDfTheqxLr8&8
z>)(esI8$tUC|1xvl+n}(t`|oB=>G!z3)6qvw*{8i?P#x!j*tf8lJiOG(A5EQ7paV8
zeWh2Hl+$Jyo3U60(vedmtWhNT_+1a!nl&k+7`zofiw7Xu^$Tkdm;vYQkV|WHovl}f
ze>?jH&3@!AgezuSZ;7^%EDP9Klkf@g>Nq*oSpx18x?i1AL+d1$6XN>W;+)~h<6`VN
zs#ph+RIn+$fM@OtNHokb8IwI%<d<k{EUY~6%pNDYlYh=;fDFf1##*VH^G_KMjWo7@
zUX%V~I>=Vt>5|Ez8ElwEc(DM~g&Gv(b~<nepHvDZlL5dr^X9ZLXDqrds*v|d2mH3&
zdQ~;&N?D4lr&z1Wo11<NuV<CHF1>A67Gw-Y!r7kP7$arvp&lhy6w}niVcDS)$Q)W2
z_1%H>Z|-Jb-|Chqk*47Ck$hWIc$Z$k0!6wVQUFI}64VNnNs!%Yvf4w)a{99L1S=$+
zo6wUYLu!b5`X@Qj@^>Fqh3rqW+@CL$5~%p%qI|od;9qc<3SyS;ZTPd{@$GR~D;)Ju
zC(Pq?5X|d`Pl+7y41yflhap^~fM1qRek9$OoiwP#1c%_`!#nK%a>};jt~ML%_~}O~
z{cpmb<;yuR?8jA{JM_G=9}--41Q1e-G=V%&T4nWhqUAEQ#nmjze>3@zWUxwxDb*x(
z?tjzw;8{NCiDVpBrcA>f5_8G(3(k1CQUWbJN_kjrj+Q>2iEy|nj=7qae27S2`j9Bn
z@F9tQP_iRF<LbnHAQFtMDGc#J59<6%Zzoy(5C;5Lx@Pm2q+Fid8?8LO{dW?Ri<xA5
z6Nrp;i}%D(J^oJA$4!PNgdocD8!Evvg7+$^0D2}JW|qAfqpS>{%MPmrrz=?1Yx76?
zbcm-~$wuRT6PzziF|ZJ#Tb5PhP}(#K@><=o@-hn#WrnU@@0rk6!kE}%Z%M;SHD+Qj
zM$8M+pCa*kxnIEPn1h#jI}ky{^5icRg|}QLFBkIG8OG*@M;ZJ~4YMKsVpmt%aVDBE
zB4DX*Q=WcRhC39cb9+89Vg@*Ac$5`3{OT{sc(v7JCL<!5OW+#KnY_1nTOvv?%e|vV
zPZ`?(dZdQBd0idbSCLki+~h@@|F9w2mIf%qmj3gW_|$x)C0VzW1RB~H-i93YC(?g&
z7A3`06>#ZO_gKM}%Gmo}XPG-aPFjS7@qO$&Pv;twg~W+hcq8Lse`_k~<}KPPkRaEc
zp6V)2mj^n7V>w|3vna!D1*!06$w&|^y_Ffdu>z9x`}OEAxyyH@k0%O)(QV<)eZQCq
zqeZU!lW@9B6+H-BY4t%x!_NFycvVw8AvoO-SPiBloqtv(`qBY@Ua&u{l(3a{uf5^V
zb&$P{JP`Gvwk?YUFqAjrq}U8@N^1U6w|Ta6?Blrq`4=vW{NQdBxjuFMdR%_wKFh3C
z^(mXBh!@#L@^wq1y%H0)W|;!uoK_FoJ3-tQc<VdCG2Px3!Qy(-tT|jZ{7dG<*L)8~
zx77%`Tjedx7bu`oPJ?}x2^X>IH47BiM9Vvwweup=r`5NXZ5nuMZ;>LEZ$TgnWH8h4
zP?xIyFWw?5G%Ofiu1dTBv4cFwGHzNyQws$S*`LNz^IwAnfX@-M!QjDvj$hL-3&M`U
zRs}q;jAypCL(Flqs4&d?k{v<!B#8#w_0#5HalZA0lGi4UlaCZye}qB`Uz?@cb8x|R
zzXzx_X%5NvUASKeYYT4dTxpZC@UAsx0_{~zHK29R$4>I(^n5(__pOzu4Pq^PtnWwg
z%0pb#CASYe7$k0&e0``Fe|~4FuSfs?iG8%=?EV?oE_Ysax+Moz?aQ+|oYC1<ScLbV
z7elOkDk|S_$I+7~!9i6^?)YZC8s;r%37DWhA+qzVQg72oQIl>*roTy85b_u6cSl$z
zONDi?`J)nb(T&m3<#eP{#KZh<42lw>qm&kh>5W$`6gV3_5Ue6jPyPj1uQ)XRiR4UX
zK`1^|1X8G^s7P#pEyhfmvX~14U_TvwhBEgV@f7%ey*bO~ML#<qxFZ+iTVf?x%~7sy
zM@Q$INKAi--1Zj|w?1Ga{I8<$Gb2AQld@RxN!rLZ%YJB0pFxQ0*wOSei1TEF7tEjb
z9(lG>mN$5CZr2)<@3n2%5aB1xwPE1#n^$sOM>+rPyE=gK^QwO%r?!!8Wv?w17qO_l
zbzshAaW7-SNS;>|l$${h?khl7?3$CqUc`uJnPDeqOXZh>3kB`HU^nBW0<Vp}S8*&*
zX9#Xrg;Rc%aHP*iSRpRi@ti9LsBck!PdF-(Ca^IcnHSI6c5X^)di`@P6`g&D26kih
zhmqFa0&-jY9Vt|FlHE@SS8=IrDmADc%ig);_P&!fqkt_-dpo?vbP;UNALh=Pt_D3J
z8TW0KLr8$nh(I;O=TxX<C__}7B{flsa5`EF-qJA>$9BPL<AGs1R<c#@rl}(Kh8uot
za@-xqQ-|}(RgOOCGW&|E_w;58hE-F@S_es8t7LbUGQojR-<GKZHu<${w;}SajbuWW
z5BvJ+%EoQ!Zvf6@_Y(go44VDFiMG51>cmN+M#EyPN^gGwSWlxw8i0zA`gq0)oKz(P
ztgltk4|_7hV#8WdTF${-x;D$-&C6Vm@Tl1Kjaq<d>{t!?pqBx@;7?L`F*T&*{=#;U
zK;)x6O2_TvhW(#Uti?F(KFgU4vIt}z8tQCGmNKr0ICN_qyl<}F(+(@3C^3V+Oe&_s
zd_hQqU|ftV14?zs#-W<Cjy4NRx$PXb#uh=JT4i>L#$)?DIUAT~F;o+ry3^$tt$NBH
zS698Xy-FpA$|;(QoJ`Jww@Y-amb<`&=<19X!O=EK)fkZ;BvYg*_~FtP7Tv(6kX(NX
zdj=kjWTQ?WYn0$$LBU|0cc#ETTjFPtk})oU@)4%lC<oNJ$v-hT63#sX!5v{WPAl~6
z?q>si{w#dmpGg&fh43s!Z+Ouqt0vDP2l#pF<8Up*3aYx(sE7^^X#9$njO5nzQm}SN
zP50;jPcHr`TuB?IfvRsIIGLmLs1W_*dFEX^>-;Dks1FA$&;VZYfG`k6@fikKytbaY
zdAoz$NWXn{=s-ne(&Z&(=ORWTOi7x4uO3C{wLH5wNK3ORB;^Dv8lWW+_wck=pEp}E
z@89TJJxmnRF$gUX)zy?pZ?9;LC7>A0RI&d9BWVxCGkd%zM6GzvqTYo!!jA2Fc5B=m
z8UqD*GAAQsMaxZ9+Jke6w9cgeml2DP=60?#vWfIx7Dyz|Jst~oYk78n9%LmM7am1$
z?_S_>e-Y+`HF;lv`%{)-oB!_S1JRC&x%h}td4)L!!WUMZ3tbqu{-R38Mof(6>#vFz
zT#k7xuZdTZD@D#(6=4ct9tAofbOtZ2n~44U_11LdJ*dT%`$L4JCvhlnmk?`JOkvhM
zkN63w8FHZD$~Pl+aQt2glM2@(6R=GZkds$JZmj6v2gt|(uHs~vp!C>3?xhx~$$TEy
z**(P>h9mjgH3p$J5R`)Zb<2?La&Og-lP!0bmAv({cj0#=i%ezViF|F*bbaTa7k9+v
zPyy5lxtj2`2>`-6x?Gs*r%w)&h&$HoSTF@A4kxGz=+mhJqGFYRB_)(A?$xo@G{u}=
zrcK$lY@glV0IEcV9Pb$K_-i3NxLPEU8?g*k`;8oPJ-J)j(Yn}Tn4s4K+Fc%cmL;7S
zAdNyJM3RC<3L{7Cfa#y2q7MTLN^<<t1uJ8_2uZ^3URI{C^nddZXZszL4=ZG1?I`*A
z1LGT^>snh{%#ddLkalIEh-yV0NzXVG4i41@{RYRwMInwedyi#cf&w0{JAnG2T#Q>>
z%fUble|KxvFTfGdV@7mfyFEl^kNQe|)-o<-S3mw`s`_O-b<0wgV&fbh6P=tqm%0k-
z@rWy0<_0)p!0?o;erPk?ps7Z_Xk()&0~x^~aOL>bG}ArW-v>-6f*z~GRVS!K3wuBo
zQ8h3DH@2c}5SaJ!B5_2G|7B)33>Q9@+2iz~dDcp89{N7>5t!HwFRXZ$TAPPD57(&r
zUpVL?=F)IHEuAYMR(dLv<;;RTpWW1^BkwNzP~)Fyj{#&>Iq=mup$g11p9h@-H@TIM
z+V19PZ_vzJo2f_A^iE`zu!!|wJ6y}l8Jn%r5)|qGLZYWVN;#3l<5*6+WDpD!qI_rA
zZ<l(jOs_meO$)C^jVMoYkFHLzME4cV<a>63QvcJ+c<@m%QM{uGQ7j;3e84@YK!@do
zx43b=Og$*iB40s!c`B8E7Qrh$9}-vQ7FB^xf&)9+qNZ2MsAC8Q4LQT-HBEYs%`@hZ
zp(d~x#Qy<ma|2mA$MX1tUHM-o-iR=?EooHHJA0sFQ_YZhFaP0(_scdXvdS@K1F^uI
zAUV)#)b8EqhLNbeU%j>c;iS5ynBbVUJa+0?r87TgF2OAx)yKU_Q}f`BH!iocN(h8h
z5S{16X08Nll53}1l!5w_;y{y!Bg~9SSxdk-$WZP_qtBYulGa{{rqp1WN<#25N<C_n
zr+>kc){aas|F;N$eUB=DnCpnW{gMK=sjYfj3p6`!n!;I}LXNt%S*q(Iw|Ee%a+AxM
zu(&Lm#SPKq`hgC5dLc&Yb6@K*>ud2m^{7!R7-5Jil3?&+aC&nJU^4Ou^_^4pk<EG<
z+nnKvSkWS*(ea|AF7s_tXCBkn^$NR7!_8AnP{_6tyu=#Ie`%|*S&CiI;jI`Rfhd%N
z8;i01S+csO)Y&$8nx8=rB<z2}>=(X0DCZ)mkhsD1XJ+{_Ek%@buMv8OBTc^j9`pYd
zz#F*g@VQv9ssZ$=Ig6tvu`F9A!U2R|0zSDAe3jOY@2zl|`vAb}z;~0QJhkDSf^VbG
zo6LohJopAFrU(OP4DeI!2zGg)u%<%RzaIOuJ^(pBe6(xeHDk1{4RV1HIeAaC9L}0^
z!p)7{zaO*6R_mI%!gges?TNxO(;>DbGc4`bnIW5;BH}B^tYUupAb?w(6)0vh=XUW-
z!?<S%f0)9|gEiKHiJf-ByXzcEANC;|8=0=|Vkg71sBG+3;{@{3SQ(=Rq1^vMK@xN#
zHa$x=Fx~UV5<AN8#P!-<-ziqD<pwAB&`@-*v5VQaWd1-8aZYv<KAx6CnAvTaOQfL`
zq@WRq2TU6SxgLgB9lfMotX`00f~sNh*UkWJPF}PI7%$(I=P-1apQ(QSrr(KJaiHa-
zIs<967v&Kz)I~?x#+J9UCZ2ih4OUAZQ|ciz^_HVa-!G&iW)jxFq9whl3k1f~chp*r
zk(q9;HioRi8OwN9(XiXm#DF+xI(8KAqKWwirUfM4X<{@et=aJl!MZh-l(CcNg}x-u
zEmH1q;QVZKYC0(W0t8pAoHL*8S}kZ|e&+|l0#-0t;3mR}T3*>1?9E8uZDn*FJOk|A
zOhwGzmtUQb?+nFkFd=w{ZKT&E;v{(@ayN-YXl6^%Tl4hQEf8)ntu6gNY;uJ%CKOAe
zBd%yr3PJ=I#XUft@65NS0tB)lI$(~NGGBC(ClY{A0WAh<{O5{T0L&G%(=^i;wtI{y
z_^0%MKPsfiaf}SkiTiO(t3a@4_X2g^Vo(1gw2j0>-`cKVlM!)ruN#6&NxBtTMG`dn
zowF{e*8`CX9zjI|+FfICB__>N{p{sKN9wcDp?i={FWhgLRM6~&JRgxjXuHe_yk}G6
zXXPxn-0o3<bcS)9SZ%HH30;KHSxF168rg3hR!br*qYdoy+m09;Z-Z^rx)*EaBm~g4
z?3t53Ym@T`>iz8;Kfe-WSAeje9Rm!{!=Ffc<+;RA+`^ey=b2__ooZA&fxX6!C6AQv
zOXd6e;RJbzmQHR*&`~+$1O%phthmXY)ZCFs>Yg;%|Bv&Ws>>l?miPaG5M@+>PH$kF
zD$5TE2euW;*YW%Yo{#lO6bQGKBx}wy`faCi8W#r1w?Vy%nzrdX?M_(2L8=tv7dqo-
z%@7}x<+Nr5!U9?5HRG0>2t%N!bpEJaAwc6*%4mv8H7}I-B1Gd|kG+)E8)fcUzV|sz
z?z&V9Z#5I~PNUpmgOM<VWmRe$K~|W(ikcx6MM^e3Nob-h0Mw^L5UgWb1V4LG<-PqL
zxPzor){H?ng~l;#$c=MsrE9=scu+rGVXnii236hR4mAD->toaRY^FPBm8>e*bPjb}
zDo+TG#lHG`kD)f5MS^fAIzQ~;iSUst+F>d9Zbdx4L<t;!4%Zaz94ACfWE`zZnV&rX
zuBlGv1#EW<uvRIj!KQh2B0FVzR*Nk)WV^r|S)LulR`8W|kk;kBzShy`d3liVyLn!<
zC3-M<T6{%IE~-Wq`{q^3y@vA11pZvOtDtb(05JG{5g?6&VVBC@XxYs?g|2C&X;GHO
z_TsS-ws})IfLNd@-}yibpwN(hFC}Mq$up+FS{8pe<)e*o*g4Vi-9&-sm|r1MIY58X
zPQa676r`3YIR5=soUlR-fm#NY4CkzM_Vz^Fm>~K6JfE-&ZtCGkac*$a!N}_>gw!8*
z*yk)Hvy1XlSCO!{%_jN9@!-%<CT^75r<X<tGb}T8SjwUEzr{Y56<3m<VRb(4mq6w3
zqk|67Dw6CAq@5ePpvHrq=^4vQ$9FCH$2w<x*_r`_KgRBx>}oFFEUBSVrKBVeMrhV0
z1<GF`PF?pkpiuQD+6@U7&sMP_f2fwWw)7oH_#DWZIiP>9oh2Pu#J%YMbEd1lmcg*U
zabhhlzP3tV6(LZE!XXb!+7{am#_^VpMfH=z?ECWf{BvL&3$at;x23eK{Y^CiPHPp0
z)+-R~)o>03c^s+84`;M&gntyM_DHeTVO=yl*xx_^sdUIDSqc#SJwes853D<fZpTux
z8GsC)g$6wPke`Y{f5X6cgp)ZJ%+cxSXuP4qx~||?;q3~QF=6w)$ue1LjM01N#Fq!&
zr>sKQHdm`d<G1!~nb^X_yVX+L-mC?MY=X5T`%@atwZdQacV3!IR{%V7fnz5IoRxnR
zD@zbIt#el~q`{!5+6`%~MdcMi@wOO2s>>+9X}q$X;5A%mTcis3FDFInr)hOQ=bs;|
za?4@bFI+I1Vj_hku@Wq9hje7qbtYimjql(rjezX6b)PO~@wX#Qx?<F0ZDb)EpqQ?x
zX0p19eRs%E%<lqK!MNAeR!$tOo0%4VCSr4Gd`v%t_K#KwDhE>Tnd+nmV-Ag~(MhpK
zUSCeqI?)t->xoFIE(%-K<?SbLq<HR%`FVnAUN@k6N)^s$!!@Yw_GSzob7gurtIYtw
zmBdP(3>$dluGY5ke<)<;pT~bIK~Kz#`B^uMTa7*uAyUVqlY?0m%dJN9t{}n3f80Fj
zSHSm{|4@wLgib@IVH=cM^_TcAgm3qxPg90;yoB4osKz;1WMWEJD3oissRL@xRLFT6
z>m087z7=<L81WvtKxMsbl)dRGJ72dpV7vw*kEoWtK)=;&-zk<A)kCBpmDb&_j`9JG
z>cFtIAS+WrZ>UYrbE9+C4RWWs74Tq-p54QqIj=f(rDx#A^&X*gVQ05(6%CC}<**|i
zr8Fvp<*5H#TJ<q`REWvn4Shs`zN=~Tl2u)T-yll^u(dJCpVtcwt0LS*==>0qz=8T^
zw;;s0AxdgnUwz*FoMC44Db{>sYhG7o^{ARXEE`pC979CTe?tON`@p>7j8cwWs}ZD?
zaaX0V)M;qfst8Q57;njzI8_hwPV3DzJedD760R2~5p`^^#Vl*gZ;mH38JsXyS5`P^
zmFw-fE|=135_)%{uc97e^SY>4?Qz^|<zDe2B;S<VcvL!tn%aOuFNhWBCc`9>3L6)+
zs|T!m+Axz=l3(s<1zn<B{^|=Y#Ak;v9vnui@`ZJnr->FJs4Z`y;2dqQJ9)mh0PVlQ
z7>H54FBJu}w?EX@&J!?@SkdOzxj1r6A){Knbq4m%oL&bh6A^j82u9uAQri9G1%vQ7
zqlP8P?@gT5YGiJb;pP=8CUnIQ%LN6w_LnR;fn5YIfqi_#(qC^cD(?o+Y7l*5p=h5%
zTUosZ4Nl69|4Ri*Js*|3e#3EGP79h8yI7V8&1?8kIJw|tmCE8lX2v4NNSEAi$TOvU
zINesl{?>wcE5u9fS(S<y-{<^@X`nf3HD9WX)!aJRC0k<-#zGH@jG>Y(&%Z0!{2F5+
zL%5M?d^1%;U!H>yhxq$y3c#c*yox?;$s&8@RBO|r5e{bQU%E>tv0GVD&D!+q7Y@=k
zbta0+Ty!qZbNszCkuyMxQh_-Il5(Z`haA`BC{HlWN7Wt!cY;kKP<B3);_?)QqxSAO
z*L2?b*>OgmzPEUTYrUtF>ViF`#u{oyQh!;}XKcDziK%U$&Mr#|qF6i<PR+`<k&3#)
z750Puh2{=uCDl%2b)O3?w1S1AixrA7BL^<}%)wetE#Oil@FV38ZwKJ+93V7k1OGsD
zXYCtEBcoiy=yI!cLjO{hv91ay@%(s5rnDPaag$l-j>v)#9~N;qPKYGgP)z;ld||Ot
ztQWfa7V4PUtdLrq3Co4b3orYS4C?iL*5{gb$$|RUHaiW=(%^2W7bG=Eg5k2C3W5~f
z5gwV~$l=q=OvPF9RpG}fgIFMYTeii17Sk=q9ERS<n>^9%j9k|-KW2nauA=9sQyS@?
zSY`oA5sFSD6(Ieo8TDhsh5tmmiPEyz1lktJbeGk!Ng7f@IA*%5)tRfEpixesr4)CM
z_#v)d7xzUd1UL13uF9X(Iz>JptIEr%-BoBGoGF{lKGc6N4EqjiM5F2Bf+DlBFP8Pf
z6y$`y6OAk)F#<zLq3YaC8FZ6}Cbs)?L=|S<l8kxb;n2x)g5VcZoHdLC+i$hCJaMNW
zeCH&2$rAS_5<LXp{}XKt9AxU>?Fqu1if`(Eu|TERKO&TT96{vwW37$R6z{G-L7wV1
z3rmZH(&n$HM%*rVoIukI;mw-Q?(_r+jOCX1chmKmd3`i9o4a6hbA;??2y=O8$c+Kz
zpc>?hqbHN9sJJIS^mpOOvG^~$KaJR@6#H@2c(b;Ly0Cm5ed1?YL{-!Il3|HZ0gXiU
z1LJ9N{@Slwn4N^t835r;U$df_aqjSYAcl+Xc7CA1=6UV<n?A_{2Ir9X1Y5WgaGNJ4
zBwsApK9;ie4?>(4Xn*}%qFDFT>mU|9RdcFXM?LQSj496NLiQ0>YaP{rLJ@3kAr%X=
zsm>?-4!ocZvF7z6CpqJiu6y=(qjY`vgmXxWHF9@w{@fG1EACGMPowhYTJt9xay*mq
z1#RC!M&rW4CS&^PB`mm=v3jF3KGY%<!)~W{*=Lg(rroH&Tflp#gPMf28jfX3_#&uk
z_h{k2Drg~Qufm{}$i&`$mw5j%IcXf~B61y+tNCfEUxL*M1pkq4eUPluWK~1JJ<<#`
zx8qFIqAR*^jSw<u#Yx{G-K3_lf!9{~GsjWSk5}E+lwV~IaP`heNFVyV0t`Wnj@#T%
z8_8Yjv%Vb7KD8W6NOkLMW_3-7MfD_(Hcv2mePY5*p;66|n0$-~a+Bz7`3Ud`ke(c;
zb91)p3S&YOI6Oqx7{nqhImRm(ILe^+{Vz=*#~%bZM3R))H7o_{yAfIbqA)5dPV)!J
z$T7vrGuBk9B&?+rEBBFXFp#*DXsuE#<&CZESxokv-mUPM&Q#?%Y`+bhCK0IKFSqg#
z4v@$1Yr7=lUdy!h%@uA-;1=XV(7n2-DqXF8*Z@%DIiCXfTEvNvA~qV(rDJeFleM7)
z*Vl*pN%d-ap4AB2F^O@v`(Zz|)a=M6U7~2896p9()WGK5j(?N;zEzUFZA1P?Cbqf<
zenV)_7iY3W=xaJFte6T3Y&FHpMkQX$PJb3aZAvyGNh4~%g@0JkY_Zvl%+%DpwUUlu
za4{tyE3e$SCJPCJuOk+sPxSWaq_f-K9xF6Fl{lqhssvG4`-}vBFRPY1oZ7Y%bsSu!
zDFG_{NJ#~z&>MUl?w!R@Hl;MV-D3Adt5eo}gnNqsoC3W!bo2DK&LNWiOv3&helhVE
z$be-j$jX<WRXml1p;~73CIBKi`3e<}B4^&|tX>BKTt!TFS48zy{B!Q@?qkug?a-~`
z-@z5GqSRrX>IIYHJ(JZLm%s$%+6I$CIlgUHGz);7?==#C1r+B<0uIs@%$uooE-x@G
zpKX!W>+^{OQmEzq4CH|?VFjI+!U+2(Zp4fXiJ7Sj^qw!=NN!MSOH~4P$ZsUrHub##
z^)5!Y8JB9Blybwlh2RFD7q!CSyO)5t46gO?Kq{MR>_8TvSFMe-1QclO1sINL+>S;k
f^hZ3>xhWHwM;yjO7d96=GokH{fn^e_`aYG>P3NkR

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_ff_length.v
new file mode 100644
index 0000000000000000000000000000000000000000..1baabf5b41ecffb783482690f2de6f5d6e8e7d0d
GIT binary patch
literal 3928
zcmV-e52x^p6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btjz2xSYmn@<O2{fZFy5pR;~Iws$Q
z!Iht>q+!kR<Ltju2Ez5mX{B<xpXAhnpa2$&={`dy00iW?E*o~)2Lp1<)NxqD_FW;v
z_yS^J<Ee~zJfkApw}``)zPkiKR-Pe%1_sVzo5W%YHmsCMd9Y8+c$WbrBUM5oeRZ1B
zdT(c2XMiifsG4Kj>KVg<+0%oHx>?HYF9uUo0_)jh`5L}<N%WDea%k^t1yU1eHV?sd
zizx~WEEBx4Z3v=T-zBQ!K_?%xTpZ$_phv0$J!p1}XLAm+C2@b?cWfv2ZfSp2GF3kj
z!8U&J7|%|-fdTmO`jledRd7RUmF$PmLXxvCLzM?{^=legFrlA#<ro(pzMYU(R3R!p
zRafb<KKhL(R=Q>{i(5@QpCPJUos$K2ApYQRE`@tJL*F(9)L90aMni%dL>?W3BSJ7N
zsz9_G4@IFB2DT1?fy9|R<D(+4RUs!lX7KU_vw4o0h+s)uOYu=eRPGP*KS!MmY64t0
zLIQrJ=e}gEP;atkX9bhK`3HCJ7+h1`r1@iN%m1}M^6^vsjTk!9&UwdRV`g=|KD^LV
zeD#iZNq0UVZ}i7_DY;SKcQ&YId|{sw3f#4*$I3DuO1Z&cFI%IffX0)kWPkK_ubSF%
z+`K8L!{?fuS&x-h6L>yk?y>Q%i%kgrChlWz5H6#{ax~GLR!`Cj*BA1u2Lr1{@o#EW
zuRxeGU+QflT({+!HN2EuPTKj(m(!XwOAs}a+iAe!H6=DTzaGeZGsiLo{S7k&-^sx&
zGt{Q^Rd<2hXrc1QG9E5zRlY8Z3_R95B(#nP3lI!cfDD`AsZA3E6sJ>tEYKH8tmB3%
zCGZN41syl{MB7;#*1zA+*r>5GFQJoaa&KczuObKmXm8OZ!$x2Ag#bO>!Ri>Kts*q<
z0RCZ9N!QY)jc{A(f}xkSLp9ixXaj0%dcERVlij&S(ntwJhRh&c{SsCPS-)-`Kb$^e
z?5ln;k~ljO#Y#6u_K+nR)J=niFhXI-TJwxwjv6R3u2);jAE8^PPFM2H<E)ZwmJcFX
zzhTMPsgJ6LNA4VgcM5BW-5N9mzF&l&%u{_vRHP#^!_v=+(auNRCqaz}zyDsq?d#;b
zhV3Q0s<l0!kqJ)f3GF~_ijxq<o2&=2N*~O*KG1EKvg%mU^4*~LI%~y$DW)G{5KOn8
zp6R#>B2`&$tD;aHpy({IS35t|i;a<w0RC*0H4On<?xzD)+d2LXK95|)G1O*WiiyZ;
zmI}Q+Re;U*68%ss45r_bGuhSTf$|H>wo<!{K+@Pk^RL87SZqFxGb>=><vWFzU2v2E
zTbs%K8==0Frz+z&EvfWEV@S;_44MOH4{Z2XgpqS-j}-5CDV@H_+h1ouJKAJ^|9v=F
zFMOVLEDj^hx_(HKk<^5zV0IqD+by5JhX#3Bt7hxbVnBwF#Kez=)U8FO8L&BUwX&2o
z=;cU<OPOz&hbQ*0Lyi`N6R9|faBp4sZZXSYB~xo^U@Bei?}U$peM6R-GiYt_$;~bi
z<Wr0}_!;Ec;K>*^Er)fUZ$60p-ZL^b6?-MhM|->Ymi?GZ8foBf%Wn|@k&`v;#Ku4Q
zb6`Mdr>=xS!|t4!M^U|~kdBQ+uodFgJ?B{|w0;i=D*<Ub{2rx69bUEX{$C(d6o%nZ
z2zsH6I|<|mCs==y5<DjBxz|sZZ6ZTLm)t3?Io9Q>+Y*aWyR5W=kq4M)uHjP+(v8E&
z3!jK~j$ETF_`kIOrfUt0W9<gZ>bu?yu3SXz5CKc*o-N)M$T6R7#{#A5d2iOntJ7m&
ziDPlLE3%O=zvN+XY%-a6IqOAzR^f~`JWJ=Oo*Rq$+iMAdpA&72CXw7E!y%#rQxHo@
z8K(Xrm?#;V`Y|%~f*}V-sgwIedNyIaTB$-Uf$*a-!4iiA-{F`_6^Fbhw^RLz?$E24
ze7?-3<i3>DB5%@#nWIKj?F&Cn$*sU|urCIzfGC&lgpqFPD@8H>pgQ)=(j!@9KVZlc
z2=rnQ3_AZ7pliLD#1+ji)-!CpY;Q^`wa?}BF(Cg!lTH`m9}{*zCPDJanaOEH$jzd-
z&1L0-M~2ALC@=&p@OaR-3}^akwD^A<cY74VvT0e3u96?DptLDnjnqd}W9#5<l@jHT
zm!J^)U}VH|BM~RsJUk14?{50qubH%kK)?p}OTP-y2MU2V2Ts4-<SI~128^J9Dud#%
zVOP8emV$%RO`katKmEX)wcef1h1nT{ub-E*VsIJP64%lAAM<uZa)-Vp(<?_{82w^0
z5BkVmA#j%=`jLr4RG}DHaL-cK-bZs9trA?!zmtID9{gc+Ru+{%uah0daY<x(YI>rY
za~)L-qb{^32tica9)lYoUPf#joAKC3(1k_IXL~fS%lj#($v{D(5GO8jHoKu==W0rJ
ze~@OyE}3Rb%&%*;>>x;9qk>3hmC?z;w?Ti4<1vxz`nza=>22yH^fCE?zrCT$)81rS
z`6AqTwiGc2<&A39u*Y?;EEBVz==)>X;0@r64wlqF;0Z|@T-5lC=W<9a$IU*nc+biq
zUn4KZWXW1RcOtOXhE>wl)^aP(y65Iu2tx$}al&f0?=o&>{?*EDbV)nq=;c6@bSjOs
zh~rbrk|{)Yd3#cu6TTlm6G=A74>2~54fWX$pLD&lFc!Wkw4=8@l@I}M;LN!z<MFJe
z^Q6jtr$CXi_>N8hDRj4D!|#_af<9#l?AP`T#&q0?Tl#)e&^sj(iyb!>K^;OMkB2l*
zXmKi!d|XGvVF|6zhSIW`ar<t^)VUTtj@lbhA@uq7oZ{IWjW27{aQueRvK%Pj#=L^?
zT}5U<ziTdz)6#4aNmiu#@0Bg6sjl|G-(EK+dh#q0n%UrySt6J8fwqs@YVkG=co1m=
z8o>)rEb25XMidc@Y9URKEz5BK3HX8AEr7F?g<*mtAdI00?)<TXa-rubu>I@p){u(a
z_PXxwVR<bi?-4P=MAK5tcClrIttBHuZdx4|RE`)1wvXAV=HYdVcfGoE?8(lvyG@!#
zNVUCPN8@fEEKj>daTB=PbZNt?Ic~ZuuE%XL{e7xAvO&fLV=4=$*ln9e@?0+UX{y<b
z-%%=tT;L>_{^mgc%Viw^a6^%2wP-b^IshPh6u^W=I_>R$XcmSWAi)FSgs^r)hyS^)
z{T*a~6*>&xDwKjQ%@4=1SGKJi_j`cpA~>+^MpCa4@oMRtK(<%gC*fRw`{anP1#fN?
z86wkH;pD+rP{kV!7N5l@Zy#T0s4~MFj_6%iKX*>j1(j6y_)2w_6nb3J-Oy6lWdQiB
zl}t3XrzW-5_RRlRanD85M~p|P7q=--t3jq4S=1EG^5I&5wBB_bX*M{V_5>4{0Qq-c
zXC3SY97Nnz@aI@uBi3+A`{=vytFm!46%?xDDLx7XFsqQYyWVt1z1}vqYFjZkF%FjT
zB&uXdHK^^7w~d`}CAPR?aiaMRrlMh<e+Ft9Ek^Agm<Ue?QIx@QFb@B`xyID@eS^*h
z@~scw0T2gC)I}3!`m`~f#sy<CbVcZ&R<Rn3aGILr5e2*P&KZqDLx-E0pga91AP`XS
mgC-6S7^<|`oQ_ZngM7!?cCZ&iKXLjvUHEI&w~G~6yP`hU8it_&

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_min_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..9a7d739e63aa064bdecd76217f26babc8d91b61c
GIT binary patch
literal 41992
zcmV(rK<>Yb6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl?u59eOG
zZVhHj`h>j|18@v$D+C|f#~VL_VVFk1SLMS-DjmM<?;998^(xmsXQ9^3EibG@6=&7G
zE9Oc>wRcvyvCruXAGOGku9!wDk;233<h}PYUFH12@;&Cf^q@a<UW+n~&y@lNoWai@
z^(@SgmyeIk^LB(OAiR1Vq<<gC0b{x|V`yzC4x!x0%7q=UTv5~j_;3y%1~6Bz*4ri6
zH*2f<PJ@3AE`ld^<*FKmUJ9%oVgI6~8NSn9;!>~Ksz<G<Cv60Dz(^(6KWg8ApX~bk
zRlXL2O1^H-@PHWUBk?p3bYNJ=3p%fleIg7RaBHGNX8DM*JJ1JJYr|O(Cq~h&SY(7D
zFV*Dud!#$2dsoLvq-g2`e8;8v%j4T+Bt_)BvYrxp<KA}mD}<=ib78$jcKz++LRWe;
z1;k=ZZ_P2r>emtG*{P+i7Opk*-+7m*$c35ur~*9@SJ^^Grow0~c1Q#_J<g4gk6~1k
z2r#A78;i7q1`U3GI;2LqQQXdE>Ih%53CM^kRd{9)4}LHG@T$OC-ea+>TeEeNS7}6-
z#-R+Wjsqs5SUrV~C%z-o!5L?No#S7Y7;uZ%U(Ser3EhRb`rZDbljLJD<d#JUGWmJn
zGlLLi7cjT@xM%56D>!k=rLFO2h=k#jd`!1qGRhA(7hgZQ21fl+AB4BpK;Df1ZMPRY
zhUrD?c08Ox(NW>xJu)`Z;PEaXcY9gT`m%=Mo?qz=H@A|_0bjoK!5Ex#z0@k!GjD|q
z*R*-Br_$2te^qYK^VFlEcbBA{9*NXg9prUWPH1s+EJP-5&It!MoS-h??C*TI&rOX~
z(Y@#c$r+?Da3hnBlZ2PMH;$P+UJRU?HfN~%ygT!)YtSfJ4xPvi;>d#1L4&B>*}hA3
zQ(Ui72S-`1U#w0@dZ*33v+WWLoEd~LHL7tGzGMh<2MTf-`ZW3YdWF{gdp`cY?5iqs
zLkZ@p(*;_{(xS2#q<8WcAd%wAVy)(4w10+@yzS#(NTJ>20gDr^b#MoC(hj}!hQ*sC
z74Dh>u9R%;K+^SI9{O!U$?x-Fb+g=r8kD9U<f~ZtrT^V+Ea+zJZ+`civcA4NLF%pb
z$`dD;VyJM#7z-;g&TFu+-^P|X!?0M=`2Lm=uy20EIaPY#imKeih7HZy)~3#o`##9X
z?dPsm2j0YM29#Z#Y6~FJaRln6;Y<bv&F{T%8dNKcn5ppdi2)zXjYeLQVN(~qb2{$)
zoDSb$L^Ow?BxnCcn0?`tk4=CL#oMx&6k#56T!9q>dVX~aCB!{QLyF)AYZE$5utt#k
z)<Lj|Vx6i7%0ZSTUg^fxyYslac#d9-p#s76!@IU!TOs8F$yB@<zIy}2=pO-bAtg1g
z)(HJ91>|n;g5f8^b45Mat^XwOMe^qpLhjPeyp8<JjJ~NnyxIyAT6Wi)dm)iy0S-5u
zbX8+s{=*(D>lqG4Q2*3{(gb`Ky}eJ#0Ou?l^h>LV{%K^068jm`941<2m5+Y0NR9<x
zm@D-Uw%C?#>hjGCOF(VIed=<SyAs+!NKw9v7ywh2Xxi??(VqAFJ9F*;Mx#4`?9lN5
zoYJ@V^8lV}Aoa-0{AS)G1K=}owAZ{bl90QlyzoMliP+5)P`PyyN1z?S_uTQFx@dTj
zd-gx+rEq2x2Cy3nmg)r&6Qckf`1Dqsj&So{Y=0he4^atVGSNT>O;l0>k~C81oA9>2
zm`r8w+cq}dz0;3R%W^a=`VCLBo^OwEr^;`OWlha>ECP#}eOQ`g-jp}yBF{)}Yi3g3
zARw0>#Ct&o_-FwQU5_sX$}vDzJzz#PC6?dPaG-#2s0|METDvoo>wZ%bsO9$~sF@3+
zvZOo)n9uG!*hQlemp?463DizrzBK_=YsaIn??%>Kz-<!TjCoY1U_bPAF6anT(qa@r
zu-p`td%X8GCF@Jf=|#GR+!z-<%c1>S9wS+P=!R-%T}{XH;^=f2#G7@Q6Vzs+x7)aM
z?dX-3f#<onkuDt^^wI+3Wqq>Tpjoci0W(|6SY*&`?ggxR18I5%X4lrpI#v&&m!z1Z
zAuoOIXyziBO|z5fEQp5$Fc=nWgBQB2rDvX6v=q#GuZWfY63=5rN(rJCqeTA`X4k)U
z8;vH%yY)9#^NgZY5PQ2o#r<AA#yhxap}LyR-IP$8=~<QdAxX;oY8CmA4Oo{*M_P6>
zi8ED=o#V-&RcNA@<k^Ij=0sh~9sR%ao#D1oOuj&D(p*B4?H;Fboq;w(YrI-Hjn&PN
z^n%am?L0LfLn+@pnRLao%CtGr9Zyc*i3>jr0;@_^?5+>{z##VFOAqL((#FllYy^w8
z$k2RRSRRi5nW}WhDjlXMZYc%7v9~&dO`b_XQ=4vBibrlEy$p$81BX4I-gv-6#>j;5
z%&xdffD5(1eAe%VO~#d8^IDI%DfL#1La6P}EF0sfzR{2r$~?Ceh_P#0GhkJ?`wNFv
zA?5p0*zK|HqPFPb@kOghE@2Be{c6!H9X&L$sg_kKq<G8tiuquw;I(_>Lo5N0FKLXX
z!-Ca?*cHv;Q-see5D*Q#`xG4tbi0qia6cuU5ps)9OAOyi{=B3i6h+CV#Fcm!;$(?|
zcnGtl1xSHy%^#K3K!tXm&;)fHH6B#`*PTvHR^L|(mX(-iurA%w?7COrEKH-#M>pBb
zb*Z9TRAtUhnNnV_QRE(NxuQ!EL7s-@?L_eijNDcXf>@?JfvesR@NqGLV$?%%MeLiZ
zZ8#Yv+UI=TMXj|;iY^2x*9%zp_4kUDO<grxBa%7!baJ5<PPo`(&S>!5X@*x!+*QmU
zqj}ajTsY!@|Bzkl`@~GMj_0i9euIfEk=sGE)CR_maKv6R&F5k0h=qCg(cRDgejjNv
z%PbAfp<&}cDKZHGp=T)3IsqdVN2hj{#I!BPMd@HSMfkP807J8e8~8GdJ<*QZe!pGK
zm^}P6@M!WOhxh<z1(dV{Eo|WI8Yg-{J)HKxuAp)6GoQc|N|}F<>}n&3&(lEA#D-RY
zsy&mCJ!^zE4^Q6j3TgMCciJJF&IL$)VlyGeM581Gu=40Xin(O##6<3_98Z44Kp}%<
z!XIlGcT?YH($f3^%eKI>1vkn<)OE#`2lu#gR+xqe!0I$)q*P9Mv5Tzix0#R+$)5uU
z+smre0nd1N$?&flFYl?Nxk+{YP#ul(4X~Kam?tT9TN><?S_u0ZPtoVOoTE{fSTaA3
z&XE;jHJH-hxgDrvwofT7VI?H-u^7(IuG6x|g`^9da^x~j&^buy6*KziY3~~odAH=D
z%JlYPFf4tznZC3Q7Ww=M70c|%G~kAg_WT|ft}N%bW<Do}7DfGhJIl6~yEC0y84%k4
zj^@tGI@ko;J_g$}N9=fG?lVydAc9OGvo~6&mivyi67V(;SpTWqxTshNKad-vA}1PF
zna5p%6>x*)fVSy4{I=Ts*}aDmajSmQ%RX>#WGT#VEypEFE=#?tGPR=*y^TUBN7J=t
zz)r3>)wk_!_EYTcD(yJn=lZ4atMb7O(e#TA0@OX?StZ_#{BZFqYrJP5t;nlD3eNvU
z^YjRT0y|{l#F2=@59dUCQE*(Om6gX)R@z(-v;XurpOAqNPUrA!#+Sp_++Wp6Ixi<O
zu22@07`s%$?VF?UV=#=x3+9c^`php7^c>b-1+bX9Ws$NaKIxVKQoH<oG)cE^UkA^O
zdXZ2xv!?lYy)mD$<jYY~&q_gbTzY671HoCyWt4iGoL%<tZA1N#`unaV3xU=0K*&5R
z9AnG_^W>QZ07*^3Z=X4y9cYoQn~vRtY`(%V(mGa5;Ar>6t94_b(fH|5Y(bWQ661D^
zEOnb-ue#43a-V0%njOAmxcc=qS2vQdkrBKw_zwhVNqQJQl5<zf61^Mh`vUE37TF-^
z6dG35+R&M1m%p+t6oPU_Eo(Cmf_4i$cw&@euk}uS#TwNP<b2zKCyPFHi)#tYVxTlD
zG&{;S2wp<?IosK1el;-tqFesF(R;}d$@i@R^rx3d#;P&Ru9CP|!!CasU(EB{^?mEA
zio-jYED|P;qEZi<8U0653#8)_AA0->3AJ$O;DcRH01}31s(?#}K5PxU7Ry9=Fe3tx
zMS;miNz^`>py%;X6C=R9rr79Kiux6$)${7Hb+FIrn-=?)ltX;%eO0y>j(~E25?=dH
z?M!^e*f<6z*HQOKi)LPWD3t-g@Qv=YMMu>ARTKTg1~=<6&tcE(B1LMKKB~Mgo&)4h
z{3^u5rN30JV0@s9x@^qW1H8edo@0iHQ$NCq@H8fxz(HD`*#&mbT2xQjxRbQHo>f@l
z-~)sf;-*>t_;=#$!+)p<;(TW-$%zM}huLMWE)V>pwkE-S$dTJw#saf?XbRtSPTUF-
z??OAOw-rsRW@dEUJ0-eu7I-da7-JgcR;;fgY5~mfCk%%{w^Ai~es3KyZq2slIctoD
zJ(OPdUtua@HX(vf5967QxLB_B1nB8n?QVZ0`A@5g9nH0uaT6*>>vC9r%1s1i9wlaC
zd#mq9O}6{2$fOKC;J)mIF-He}D7DC&<wotXI+eAQBfvKeH=mb`iaIG&o<py@puK<-
zhi>7uFH!`=wMZ&`ODGHHo7h$VY{qu0q&q#7sM+w(vR~`vu8QPeORGsej?w!Pc?2Vj
zySMB1cy)`bKd@EN-a;nyKv~O$CAbfIQSEK`$N{+j@c*v@&=->mzWbn+l;iF!d1D><
zkh&U*$IUDBOvcgj<`oqyw!$>B2J?{Rhcs+|3?EXS!NG`beZB3hzkaJEjJMhK2)$*G
z+&rbdDcO$LyX=kvK)-=B<2;FEy<$ZNzfS|L#?(?<U8FveI+sbE;<fV)cU9+o&%TMx
z&G>BqY?dwp&;3QCjp_|RenW(5;e|d6L)2@)$OPZ^RHLNuYD5>wQ1p~X>eqp_AO06B
zx28eTvyZym59r1t(8hG3uyPj|`0NS>+qDI(ft3_oX=g{BRG<lQK6sdL?&V2n2Py6&
zcZhkVGTp%5yVm#rIYajJRL)||<?kL#f%EdmqPz6b8F<S$R4ebudZ`@=m<cU<rObq4
zsoxh^u=8fDjDSr><gj<UMaDvu0SKw!-j5_&)QEiCaDn+jI;`;FV^TV`-=W<mV67R{
zXHTOmEfM?Lj@{F?vXeCPI%~hQ_jUDuwjxyjABDK&2XMeQgU8icd`?l1l&{?G`5oYH
zZ?UNWuacBD$;p!eh|1&O5uKPo9SM0%{jZ9rIoZzbUX|uP_}RXTV`Ahq_XRt8y&SWz
z+(XMlY4HSNTW^9@;xX*919G+G>A|&)nW$c}^Pbwo<^1oMwc9=S>6)(<%6-GV!Dfv|
zL-1aruAsL}@AxKjzrH?wEuJ8SGy-5q2L4}<kv}PRMP^&={UH!mQRMd~oYg~feJ-;o
zF%3&;HEy)OBXL7c;^c;tJvgX1yZ~)K@9{ktECDETy#_1bCNy=^t#Vu9R^>`HJ>)@c
z-P(cR#UqZ_U3h3q&Rfz1Hz2o`=Pc;sJl@2?_Z^=)BYz4=8Kc`dfd1>TyWjjj*`ON^
zUD+V3?0~!!8S_68jq4v<JiKlM_E%tWE7oK~$RrgSMCm{}TQIV#4K4;ifRW#Cx^ZFP
zQ9>O~+Nt?cEUaWXUs5D$Wd7vqe}-WeoRdjL8ZB-d17E6J$i968f<q#NJW)<GBN`7y
ztSV*lJ|SLi#wEQef`Q3zeqd)!-|!W1KdsRf2CWc)VMd)hb<a_**HC?+FE*~BQWmL!
z?0goL59Vws@Q&~&jPk`AxY_GhD-L*b-P?+#h-W}39vWe{-pe{!we-{Uesb@n94P1;
zmg2OLx559+TMJ=|g?jnAK8RyF-Q6ixUax!O)rc8p`H@D`n^ehQ%2yyWa;_a0B=_90
zdjrSrNkC{<1VMh8>RRRyQt#Z}k)m*$P<9_Dz3)~gqzXVF3?JB9cElCAQj&OvfN0f*
z$}az@ZdUN|q+6I}i96k8;bLV!na68_0=bESX%ZWRm*JqR(&=})p=qcl)uxW29#}=X
zxkI8`6pSQ1vVu7xKdq(@5o7+;<o3xK1+=)bZ73|g4i4qw{YNh_P6FN^$5wM$U~mL{
z20|8`2Z*@Av_jS!G`2nIF;OK}id<FZ`*G-aRujYd64sxuHHPDi)3rM3755OZWl&(s
zmPy<)n#Z~;<5G1tqHf12OWSyPw|SY-Eu^74FoWPNOCi#<eX_qqK3w?3oXf&OT}Rmr
zI$}gW?i&>-7YfX!tJQ)x#-7b4@)EMZF3}OWR8k`i@xNe>_B})VEbJN8(ADgDUqQeG
zgFqkErHcuw!8f?3!>=2`6A+GCydppAc?}!NsWEA-z$xi0!XH9-+zwzj&Oadx^u@$f
z7x*h1Agdxnqp|Hyygm4*wUu`SrY`McX3KYYIRGFRrarsazoAFtCj*%WxHjbF8lN1(
zp&lWkA&Tudbv-Wx-D$F4Vfm0sAvajBz5_A}H}OsY@3{@|qo^1+uYZih7DTmU(z=1F
zN0NvujwjSC(OtI15T0~g5gOLdcfMYD67WBNxa4s@(g26_itszisWU3roZx`Yl1nV3
z)rSzX@Ec$N1jHAzO0!L)qu}VGHh^o%Jn+kV&qkqE*x%ktBC?jYzBavaCV<#g2fvLx
zc;<)&(5U%U7p75C;&;N3s9Y7uOxr3<-1{$MqCe>OV|pT=6NxV^g3p~dqD7N(#buG=
zsfkfy!yGy|$Q{%3wHUtGE;sG#2%4uHi2p1qa5#G~Lp@ZRJt&%yncsckO>qDS2hYC;
z(2WZIrJ$rOmerS$J_3^^1#oigM2f~N4RnS1Lb;&s>5rzI1?Y@b&tb!U{Jnc?^zi01
zJOMW>1}z<L5vbZB;P)E)lmi>szvDk2q6>`HT_7!EJ$hfOO)fp7GrzWBSqFV=&2;+m
z_koPvYxDf<Ms!l-w79rf{l$RQ;v|b_^@O<RJxU+3h$8F=-)woNR-X@iI6X-)3nts>
z0CtufKFE}4aoreOaBd}&?W$c~^mumk26?t&C6Q=`>TC^3U|xH+61pMo*@iN&`SGM-
zl8#mgIzAqTNj8YIH`mLprfV#rD6C7Rv&X6~iS;=EX8^~~7l=t@oStj@4Z6rfD5DTA
znX-7jPw<(+$#0^(PMO+$({Cjq#(QW}5gBl2Kyo(Zf<I>NL*hhp4ro1+`A}<9Eqji5
zWv&4kx1Uk2)n}T#*0cGngYIR#&1&1~%VCNE6gxwnMj9nh<*WYcduGhF(V8xNZVK_R
zM1&?58nE;$mBK=0xmIo&*Yz)Qzoh4{da()SANRg4XYN_{wn*(l<{x=_2V5><h9;=0
zxrXbojl2EGJA_W+kbBmG^YcQZo^iqS>44#sM+VLDf)~<=ZqOttYe$JJs4?_*ii1R;
zstRqbEoRtEP!dRO1)j@uFZ=HkONUOTsfIrkT0RbvlgpnrouXfHHwat^mRe@b+t0B~
z$D|8!#S0d(a#;9{b;5+4xFq3`d6(E-oh($U<of={RK=N(#Ez=+#XxwV%8A^p)t_gZ
z(g3*Ie27%(B~3U}b+Iyq;?JtxmGAlB9V7Z2aX|y${9ebIrZ!Mk4s`bVFX&R~+;xmh
z2@kg{e8HjPb)Py@>ROTjo$=71%1j)~e&8<9)&9;r9QHur;0cqCdkcH_`z%g2SvI4a
z8s|i;7F+yw>O|bYJw-*U>`AK>q8g`i^-|rM^c{N-M)i3nyYX|v)X#^dfmZIuUJ+$c
zHl$*QS>N>Ge`A>kq<UeEwct*5vV+xx^FjkjkfM4TF{V$=rB^A<n69Cv@BMQ8C>+0Q
zxe)&<5iP1HemvV{Gyv=bpTR!3KDi!6rQVo}92cTLl+G*`u_Y1s*U8pp3heD?{CWwz
z*81t5GGcQb`6`edLqx%RK=Z<jZptvvF?iNIBj1?~aSUL3+lK*munQrA%7xw7H;Edg
zJvP%)bz`VAzOiZMhId2uVA>=#>wG=%9cEpUONllb&?um%Q})1e+#PBaG#<4Hy=0uK
zOm8b$k&A?OV-34d-J;Pr-J@mIU*>6hI6)$|nCvzqU`<u$Sx!)IubTYSzj*J2g*H@M
z4z2GUrgg7cE~Y9st#g8D)mrmGAdBY;FJbY*1l1TAtciHTpXc>)8rLaAhHHYktfmQN
zu?QFHR2t9}&6;gsH3767Hr8z@=+c{aVPO83rHgvUn<#TE2jVo-l7mm3wz=p27Y3yl
zF=as>kbW2VzH5p={puXuJ%P654D|SuIYw+z=`MeoM3b`M<Nf_?fQ92^nfl~{;`5{+
zJ`!x8AjOMS!Wc~ZiaVg!s74mM^HShvax~_mH0Nfbt{}LA2rQNAlgR+C;0-uK*_Gnv
zx={=vUhsHOu>1|bQi^#BFbr-;Z$f^dg*&5Ul(Wl#e%ph9d5b&1Pr(n#xsl^9=1D*j
zSS9L2k9rZWYwXXOeJRzwF&O(6$TI>X#hhAS9b5YW*$46Smsu!7wPuLmoWIh1ysIhO
zk@KK)OQH}58Jd5C;41x0Sx3O1etYLyOVKfpe>6dk;Xo5$+PF!fy<qMql5xXvz%CnX
zyg*KMB)EOCkLtw~Yr@(*X_jV&g^t_6&rr!9rZ&>ZwLsreOyI8udy~vS0x)&ZoTzxj
zGpeU*&j_UE>u?wB34#3Q9vME2VFX`NroFc?A$}Hf?RNaHhWAiegE_|wo6^>rqt_re
zb8<q!Ppi@`4M}?xnyEs;&x+_MEuQiH<xn<p^*b9F{B4M?z-$h}Cb({njIaTi@s|bT
z=PIm#CN;yF%hd1(XUy?qqSJ#rC#FR3d_-MP;vxEeg<-JEpF6l61uQ|2-HiEaZ8NVb
zCB)C7$_4#1y`v#fOix@S-Tsv!RES{*f2<1u)v&e;DAH<Wij%r6pUXvzf5My{ppCdY
z$bhE^VFqDE0JdxrD24&5I=W+S3=VbHT@d{@eB(nxgHHCEd<5&#*@Xzi#1>PAQO|>x
z6Ct?nad32WOb*)d+vvpDu(dujhUv6(Y!|nE`3!4<y{j-}gUrggWS2tcPdq;d+u5^2
zaut{_0S>^#oGg)rh0=>Cun-1??~DmHp*M1!7|Oo;ytPXRP9w#hroH!!^}k01-~ub6
z4|7}=3RyD{re+Yy$9YHgnTk4b=tAvnr><}&ULA91=%VJ;r}bf>%TlPCVAsE$(*Ak&
z%gXHd;4ACr^we4k<23U#{pZlZeTTDRJb4G|zimcyr`vrCPl%7tWyDJ`f2^N}BN2uQ
z8|sgw8OE6Z61VD%ZHKJ0d~l21mwfV3sxj0fRo+sP4WE(<zzhqPM)FWAEIUQko0)SJ
z{ZZr+g^}d$Q4t>}{(rr-amxq6T`O`eV$dh*&kWK<*yoWV#S9HQB$9kAT{fV?e;x}u
z4A%XGXbf0a3=kMm`-iVfYRD-?vEc3eeFTM6p`6Dc_(R(<$mO?~S0z}_%&UM9PBPa{
zBy%a68hg8PXfSV)JRW&=TTivClpdLU5vyX=S=qM1V5@kY2_|RMFK2kZVZ@M56R`Ax
zX6<&9hC_g3lFf{KHt2f%e?`TmuE#7^pfI)=`dpj@i0bpU!C;@`eJrI%K5%=AQBMK}
z(@fTGU6v}Ichbf2TigZasq9Z<{xilM`*q|@#lb@A)JiRP!J)~u3;u7W=9GrIRXNUz
z2stgl+BSNW;$}v6gwO@)IApc0lcK|~F!VEk8JWf_9(T5KmD8FcEdD}BfrTB7X{qa1
zGABv0%*#*p_)7Z57K6rjIeZRcD@uHzy8Vz*u(d*~nJOzI(`jx}n~{1J8oa2A86Yp;
zSaZSye=O;PB+e|>rJ8aESRej1r1Gi;9faq62>$pAbE)|LHYCZ~*yT0~z|oYX(7o}h
zBD;eA`znAgj(3SkAE*mDxj<*N7*<D|sVjc|sa})atLwIe7QrBo&f`~VE6Xg7_YJYW
z{Y4P<!^gv}+Aee2rij_&RS)wFNN=R@iCBke%0WT2wO}7${G*#rD+#N&$r?F<nQZB#
z_-n2I9`HrxO!NkRGJfF+1;r{~Ht`EzN#@=7Ag~khuC-#&B1)?)1IB(%z6TYuz99+a
zneu1!%!;YGfajSY&k2V)B|CQR%c-MI%t#1`<+8L?@u0N!NI5M9&L3&I^zW`_>N77Y
zWAPB;>W+kOVZ_CBX1f|?ZDcT#u6U}(_*NpuGoA8hSXPcjyS&A67Ik@Jy`6Spuh+LE
zSe+)X6Adox9El*kMB@^!$zjJ@EJRLhUerZWB>>nx8yMYL9&T*>-t(pz8`a4}+bHn@
zRH2}AF_UK2{OFe<<ZVI0B4xT|#{trqQ9&FDMtAoWj0$t<;@&uEghrmb5oL?t3ukZP
z$On3D^{a^6PN@v_IwFhTSz@FIY`~U7gEf*hTan)2NvUv8sYOMp9{!;kH3ze>Q*H8*
z?&_m-ARs}aElsY0ZGzF!FC}c7DIj1$hY`jY&V8QZFqMMRS@fiT1;0|A8;(-pfo}6O
zJP3r^p)Df+o6!GJ4dh-vr|j%D#gOmrV48yRM}08h#A0)bLegl4jYF;)?wEf54-`96
zP8~0*!zdi<B?{5)mflJ?$TV22SUZaj8+Yfdj?fR$d@uEk!P+`qizkeusHJ!M@z)7+
z;?Js_1@`6$;3L7t_P4hIscZVVvIZ9@=!t-hqw9$_B9O%)dx%7*PPb<=C6_%}5h3T&
zgtFH#Hwp6GEaXn;oIM|wEV_vK)c{zCzEUpnN(>yIl|RYO>Pup#t<0b>kwGEggw|nl
z&Ow&NZqqNNJLrlPRQq@Zd^jD$<(BilRLa)r7To&gWFF9MVDE2o?e<cHLFGaE-*uC_
z+z)9)TCZRAnRr(x3LcWal94cP02d!8J;*uk+=|F50X^mO3e?0z!HH~VyvB^~p2`mI
z$t*rl#~!g~VJOy}#rX{Rwqf8Vaw0vxd;%>$ba!AOtfrAP8ufD)eK@PN;Bh0oT+j{?
zAYSV3Sqy|seEParKTT}VK=w1cvdE?jA?I2EPzHPEZ|#p1IoyhhS8=JpSl(y}p9_RP
zGw^QM$0^GEhp+?*^gBJ+ZR8ys3odw1_i4k}hTF@nFlTFv1p2I{ib83Xyrm85LOF5e
zrrl@@u4sq_{~Gx@=mQOtBjd2GPsO2#|5z9WN+^c*TPhWJpTPMr^Att$gD<9=Nz|NL
z4Scj5)3v0oU=?s%v}ASA_EJR8iB|WSLBH9pyoSVT|5mn@0hO3<e;sC_>>}zwwsaN^
zJIMlc(ZvXBVnil?f`f(~8%&f8M^X<q0|4g=O4+u|(CURWgV@-dF$}ykh8mExTFmzg
z<;+KGBqi5qiMyAr1O-Uj22Wef%C=+fNjLy9%G%?NiP}Ds%?73}c!zdjRxhyFuxl2L
zx|G3e4Bb+Vj(hHQ28z;-Mk<dMGp-jj{)EdZ(4xt^{g&Q1)f!zsyam9)dhQYl@?4<F
z9Fs%E$;s0N?3rT0cx!HQ&Szg1Rs?E|G%~fKmgm&@Ep+!sump8E)L;jGA^8RuzDejn
zm4@qDNUq3`1p`Iuh)Fdq1W*<oDD-&%fG$AB*2yndo~%k$@`hby!FdeIwFi4jefT-<
zwnQm4KC>W_)OHC%#}OlLAmEMv?nAdOcj`aaAac_x`zuQF&SP;etQ<xd9N7^#Si!pN
zBp3Rm3kbZu6A<=m_G4}(Cm_RePNcjF5HO}N<x8uAT*o_kXYu)`p`xp!d5QIEp>JpD
zhY)0Rv%J#Pf8GI(o}Pi(Oy8~X)u++qf_PJ<q@y(jpr1$pTdklXZkI0geHbCsx~hu3
z30PzOD181%AhrkK{#Z$1&LE7gxg*>{?6du(IM*yUi~tqN-4|R+`zhq>W-$F=E2gh7
z^8QR97Scg;4@BtTh7CKS6F=ymEn(P*oW|S9luyTQ_>;z9+8lxOGH@!2p!ec#N}w}<
zIcL)2xtXQlXY+!N*=51WUD3JrCEh)bX>nLE$PM{<j*~Ye#frB*7d}eEvu--9ZEF=4
z+J)~UxM*+`eMN!5Z<UsVkx@)Pn$TU`{P;>SBOOy;-CTr&;H$peC|rUX>&zLLVjl6R
zxw#Qq<XEi20${qPv^ZW(7^Hj__g_Ri8DM7!K1m0AAMa$z9lYvlxc4(9`W+%k1>aPW
zQqbAuoW+q2uirsc8HkF?df!Xkju*dL%i!$Mq6f>DQ-b6AD2foIq&&CLwEVo9tyb~}
z9R1h9QjD@}8ZV3w*A=5(wczf-d}W5;#YD*@R|}+0Q{)(2g^wQ7|9EI*#foL6q8AsT
zbLRXqQGq`ru@|^vZro0t!`8x?z&p(}@=;YC8bC<Urm>s7!T{OLXlM~FA6T{aXSQ9K
zZo~gHAWi8c3L6g;1`&D-;Uw_m40s3W2>oc5D~C&&l+g7s0p)}$BxZvmv;O7WpA0M<
z+TG2k+zZ4&(qa_Bqhg<Sfv3t)wHigB?-~$1=Z*n9yCz8$5zG<kmFR|#Xd-ni!l>)s
zp|ga@^^<_;Ogs`!c<J<RPx+fOiNyptZ{Bt*NU}>8n}`BHCIzg*izRNHYPJdRwe3VQ
zV_WA)=093`BzoYAHrh|h&(a#7*)rmxg?~fzBw(=5)CzCY;M);3^>GYCoKH5u@=TN?
zDvj{hC;=|Wv|>I)miv!_l4|;!4_c*No0<@%iA5i&dag=_OevG`&==Q@2?)$R$qys2
zJEF_XD4TAnF^gqIM_%cMF`c}p_BU!*2M5Q=vm_o>bQ;CxVMT8hTFR0!*&TzG<&22k
zKJ{9vxUQ9qp7sl7_m(tgc5GaL77nj}0mO87?Gw=FSJWY_Z419t^ng|J%A!<8hhy*m
z>Qm8m*nrO4s_1hldjXTpxfC8}?`a(w<tERUra?^b9oqxMnUjUx#-mfZ2ZJVG7-fb9
zx>8zx5y4#u?ikXgE1RiXE+2eFX#9a-=Aj`-_~tF!rq9Q$*4ZPnm%M#*0a5g`$}p^N
zc=GQ2Gq9gVV;V3!cbF}-=4<0kvu$#abu%Fii)VY`Z!cJ~GYBQblE3MH+@Pe$#)M+5
zL^__MhH<Kz`}Xz_NEabn-$2c~a>-!n$Z`R&gm3crxM2on`it*~2*3mmltMo?uh1hg
zq|=PA-0S_+*8!o;E_DOiBK9fcRa6}w)-81rwYYK{9MJzr#AKH{1-qfeSteH->@cKf
z*{Eyy#(p8@#bLimB?uBkG!d-6y9B?Kt<by$XcIJhoXG+4QyU1~np!yJY`i@ri^kU^
zhMu|h(Iehzl*jj;ojqD$y78945qZB4v7Vqgw;ks1Jp*}=sKcJ#F8c&Ub>+Z-oW8a=
zMR;02n-ol^d*DC%GX%iXO8Uvhb{VbGMgCKB6ZU&C_Exdl-6aWpWo}FjVO(~#ttP~E
z3~-~Rj9jt|FDHFO%yg^IND()9gJgS1e@KW0G!_UU_r7{Pq3AEJs;dhXiIBjV1r>dW
zQF>fM+|dGzN0XwgfsCIiyp-Qhpa?>l%pP!Xt37QjQpI72?@XknRA8Ur2<%$>n#f75
zE4m1uoDayRgSFL?1S7jpI6py#8`0v+IJy)o7LJx!VL{oUoIE2~d@cTF$7ym)%NHgr
z9F=o9R|Qat{;9$JM2ujBiR@!u6BlxL*|jrgiKZP-G19h(5cYSb6hDA+ZF^qv=0{Hv
z0CW;Tt2nmcsUbe5p)@KNGY?Hk=3)sg=_&-WjadNOE=;IDafKJ@v;A%&e6MB7WZ|>^
z0})Gv>EWj#cN#x^X$8nI5CEsPc<eN3{1M6QpX7z%8jFV%k<GEBp{F@9iBhNSxAxMd
z;TL`r0%GcP&$$Gd|0rYKnSj~OsUbvl=+jq8d<!&mnvFTL%#?bUB55I`%RHNqfB?yC
zWV0+)3>7F<Ozh+OQK%`DO(matq>I@U<o(AT6;yhAi9R%+ZO=`iOrWvEa_Z5^Uq)M}
zZ1|!|0-(%ly);cC9g<6M;GK-1f>~2#$#8y*)z#4EJOxra)0DITzpA`mrV-X*&n)^D
z-#dvtd(=sh{(UAh*yUmq`gVsOVtBoYa%~bVswf%Pr?qjyho4_zn>q<hIk?Bg_gKn<
zSu|~^_kC<V7GypN!aOf+^xdeUSl4PpD~|@kFH1~qoYsSZ1SvI6^PKJJyNo?B6GX1u
z!6N?ENa2fB1e>(T<2r_$Jd>@?zvm9=<3{M6bz#f?Gg6(O>14Y<sg8%@ks2K+xD!+<
z#ch|M%94KvXldlBu_2p!bQtW>J*V|)-4V4qiG8q4v=Yd|V6H&W&K+G&7g%0VK{Jgv
z02om;C7u8p)$Oy|DVo6Zny;glbw#)ssBKQH7luJo=z&z+S}HFG*$U33nFt-mk7Gw&
zTTqU9uw!nsX)clAEH4``Kljoll4VJ4Q%ax95_HHtZ_l8HcT%73zO!QMIF*e+-MMeW
z{85SN?_y86awy~(4S;sgZVf<wIbAgHR3h^)0#iN-vYBoHgcl;QOHy@FC~O46Nb5l$
zUi6@G=-r#NHqc(gvUSPHhL639K6+rDx$3@MIk>eOD~WU9%u-F;axQS4B+?*1c4g$f
zq;JaK>s~05<aB)OOgv4-(6~Mx4lOR`Wf76M%|p4UEpO#zEX<4=2wXm=xE90}sLD6f
zn9bHp@{rh}n0bO`shqI+b<T24DVl7h7)^JRy-t?YEt2}U=}?amv)7@2_ra3;pM;O)
zkEM|?pg(OQy2q*|AVLX)rhxCJu1gZBLh^KzxES&U%@nd>_aF&IHH>IcHNv3xu^z7C
zf3(vn2z%oKM#yqYxXN6FK9ge-CA&&a+5zP>e?bS<k69Y)9?1;|%Mb*)J^LjkD>a~f
z`d;Bk;GqV#y>=ovV+b&nfnEe6crK#Go?5ojA9_|{Ih2ZAn-x+#>NOej2v023Xl_)q
zU$f$(qGZOD8Q-=&3Fcm7J_t~^)mk~&<Rc=ww}86@MNZMq!;5Cy!BE2nTmAij^Lx!r
zVXpi4<X_+_$%e|#tv$wYR#dY8L>YF1G=8vasIQ%O!F0!34Hdz}8<MFY@N}%4B4)?{
zfhYwUCiK=D{SEIg{=n#79(<^F4$dQe;^=ppD>;okUe(9GH>w}%46Kl6Ldk;;ic3em
zOcJ_ImY0NJfHy4~hLGIdP&h#0LFBZ>5NZ5`TevVIV_rw#IOO0#4!C{Yaa^iQYz(}p
zDuJN+!+HR&=$yfI-@CUA;SAEVn7q7=7#W2!vF>YIj60-scGcc$-*cO&^wtu1QuA%=
zJ6T%m?@MHnZwN@c)#F8)_*Bq(Yk4xT8K3AKTOlSg`rSX3=`O-I;rE5vw!D~YigKJS
z&hUbRz*p9Tqc~*Mp=<XPtE!nSu`5#6>~Stax-^&=3X<y{PE>IhWYAP>WZa>jT1E~!
zPWSZ0nlUbqGkE{Prnkt(eV%>iJ1T@?#jL&SFE#cjm+2lG%RWbBA4;GP-_vI_W*LfW
z0|vhU^dl*5PgfPRLHEU_u&Q;~5!OqwTqK-eiJ|~;Q+1gnRD$6ykG{m_T8bn*V3vLy
z5>Tv&GcJaZkHc=%oST?+3~(R~6mqT?64pv+wJB!9^DJu!o-Qou733Z6BO)d7W{pXv
z!TmsGI~MtkL0jPo>St=Ql3p8mGa0@^{%&c?-*MnKOv7qc@^2fv7|g&T%IhaZbV!h1
zUly<=sBtX245i7&Yquccc4p;z5#vpXDUxZeXJ-h!v8=)&X!>Z1KZpZ(#iM+1d1D97
z<F;mU-0$R<JXu&qU5fim1uV*Yosss^nq**ZYlvJlNgPo_oTU5lL8>(`uVnKsGSC+D
z#!Ir)*IXfybZhdNWeZT0X^DQORie+76M6n_?>(yU7WNb}P-i3T<>0p0q`+rShq5*w
zvc+s<X&<*)z=f4$5xf)ZiMN$rzc>XRPC{cW*Zqy9^T)0Wi;<^_5?{=CNC2d?H(Af*
zNz5paBAWtTQR#I+Rpo9cIX7HKG-t%4V~J-Y)w{{FJ)%2(P9%Cr|3gj`=|R3NsHxYD
z<XSYb!eN{R39UlHmF+*rJOZit5CIuNR`l-oz><Jp%~LlnCJmzNuQo!CckF{=kAT_2
zCbLHA+1T?#FcTJMhr-dI%q|>);$1#!$Fz^9^k5svLPMPJ)tYWm=?rEo7Q~j|xuoT*
zUvDjjNqVhch$fU%TbJX{Jd4d;ApEmsj+NJra_8AuOCOB+Uli7i-DojaSM;NZQQ8rC
zb^%`l5)Vy2N_+nIMV1+;$L%4QP1P;M75BUE{fVvH_o08{3$-nr23-mte>BS>R1vHR
zBkL`+0eS{XdE7vD(DYG%5VwLs+-qmM6DhJyUz@qUEdDPRw2_wseU6)Xax`n&RYH1c
zG2nj$k1eP3p0gcsz%5&>o_4v{IXhqV$jWHzs+{d*XC343px%=0Lpe(>C1S|5AYq`{
zUv@#9dhi6-Lq|xm6Y&`&e0Wm{t(>2A7H4o^MJ(@o{TkB|dLA%>VeCg~6BTSmVmj5c
znJ{(ac(<Mw8}W<`5+3wqu%)>l%9SyZVeZ9M=u}A`B3L@WzE#GrksnX~{cLf)rvwau
z()-`Dx16Wcy7xgte!gKEi-}QB_9o*VyYC6KROo?=^kQItk8p`U!Xtl*4N0EBlVo&U
z1+VsEqia;8VPxbm3GG?rd@QiSZA>3M%Rc~pMD8sxypbF`IIO$&HIwgPVZc>%Gm4dD
zB_fDdTVP1;>#lxq(3a8jDYP0)96o-&6oxkR5^g=|_Y??uwKaks=<)U|_G`K>Mw;Lp
zccvT#i%#um!C;oSMt7GGUGz;N8ouK;c|_?of4{RrXL8nAi&cyZ>T8Goh4NcU2uQ$_
z6Vulz!%T&WTFzFPJ6TJ&?Kg&ZO{*OsGYGKhKxo*sNm7&96X3z7eAXYK!H0=`BitYC
zy>wBfCmGzXCj?xTvm_GUEcMN0-Si&lY^W~T?x&^TfLlF-L5z#5$Lg4SP11a-bG&`^
zE@AI93#P*;^^wGe8kF@1&U#B0Z`=E@J_sRVWZfKfFAGAo4C_LPmq?61pEk^bRH9u4
znr>Kx?MLG+J604AFid$mdUnl^EJaT-6iC}B`(BW~D@Xl9MNkNkPK{fh61|bRAr)pX
zYfTG^fcN0nc8r&t6G}Lr+SvC`S!~~JETyc04?_{)IV5bC#byBZ1qMWQ^0`_3lj58y
zasu3=PIv!fGf+xvp5Zb&VEgCplcFg1O$yi~vg=1;Uv;#!5#Sp3ZN;$D;LLsgNqp2J
zyFaRwivvLcJQ42{!(oP|_uvu`RH~OT{E&8kQ&gAn9Z~TOc%+fv-Ho2ISlr|c#2R-T
z<xg`C#GF8da7!5HdR^<n9?|8*J%A1vF4%*01QC-o_%c8QQKSRrmIC07ZfNy>0e0nT
z)kQaQ0RHh@;!{L8qCd5*hz;)5?$RRm@m#%%#@_7C4t!%tLffPK?=ki{9v>|X9TTaI
zYc^kS>lgh2*{Sz2H&!tf8oE31gGJv%SZ#aZo;DGgvgnjFkW<H4HbC;VxuI#wWgOc`
zXofgpgAljrfRt-A8{@8IiIlj`{o50W+{&jSfm3%G1D@yv+qs_CnmR@U{w)WPEaAa&
zj~>3Q45~up>O-SJX#Ja30TOnx5~{;*8#sCiWPBcI5Ytf)@>jCSlai1+kW4~Ke5rMR
z(kwl?aWj)Cj_tqyYZ;s1ih-52<7=D9)9q>UJF7XsZea?TS<R>}3z`FK*ml3luCUvt
zTLr>kpoc;qf}6Z^OI(XxT6F1PB!cPgb_G!!(NBDYU-7R9rBb&{uKlR|R~yx}Rteij
zXUGGfeCD!;OzNdUFC!is>h2pQdVZHdvu_!8p7Q^Rm>1bExYnGzq`)<Hxg2grA-B1#
z=ko7;`9FiYM*9<4t}w7*o!@>!4{ea?dwIMf3Kpc`>RR9_nB@-wN84T;xJHwY8bC@E
z^Lee{oGpMjR*~Eo>CXz5zgwqzYhl8c?dh7jQA~Ug@h~fE^0=KSC9jJ`b+45bh=O&~
zXl&3t8=eM{#mt1K5y%;)dn0fBuVjyY(mm4?y_FUM9UGJ}jR(RBDW@0VZ;w!kL($J~
z)4YYVg&Jh74O{Dq?<%1L?_vOCeIyt@ijsb7=1~?1mVA2%*~_HtX831~>{WK_f(uTI
zJNk)O>DOjLo|zozf;nLuk3}Dv?dr>1CXwoBHG#w~cuurhZYbq!3`Kc8@bimM_$tOR
z7(htVW2+CErQmtKSY?;7c_(f|v@qpeKmeNoMg)paoLxe=@WZ5ULfHM0Z%TuU5DgzY
z&E^!_%I*Ichdd1<^Jsj|$Kts>5Kh4sHa*$6{-+xZ_Zwn83@7MqlB@GdIznmCfL2jA
zGK#`R3Vj?4G*z}haBep@fK^eV?!1*vfwLX$DJW#0?Y!Moh9Julof{E3ry4Sf+-j8A
zVqPI7_XNnteiAk>zUTD12NpY_%i-AJU$=>Pc1z+%lCvb$u)OQE+J;#PR+7P9ej`C0
zQMIJ?=V~Ix5v8H1^<hP2Qq*$-u3xBMg^C36gS(KY^rY=)pd?S&Z7W2kTOu|eZx^VP
z-R`k@Zrka#)rN>!368!a_m_aSo+lQjfyjMa&}XY@FRO5(c(_;NXUh{i3L;{d<1~b|
z<RAR!)qMhi_RQ_JFD=eQ^YGZW4>)oy6_f-{W0%4^h`Ad9Pu3Dl^u)QoKTt!fBFk&H
z8nQwV-APZ5R)hte7J=AIKjKcppEH*ji@LOS#~i9Qk|B;OvqphTja#zP6&(emV|Od@
zj`4wJp$Vnq&5jh68Bt9qn6u+!$d~HfcU41A7~-tfb7lsvF46pWt%8owLxb9;`LWaG
z+#hfv?{O>&VVPH`wRKE`7$kZY-y$F4wVLm}D%@U;4KYMR27*ra<ttmG!6ynZ+WJ&V
z*@$8TJLY|o=Bwt4a@aXF+#@CuW2x$x{hB5Hl^Tyye=o8l1!wmGtkOdVWaAvWdR8;7
z4=lc?u5cA-d7fmlY+e??V3VEbv#RLA%aOIOVfn?k2uNP|#U<+#-LIA=brIasD9oC+
zBZH^3_CL)am&(@4Q{_t{BPpolae@yyN4^mE3n`2n{AeOK@<BaB0ozPzC$Hq<&gysP
z3mw-;)yP%f1Htn2^(E{zyJC}!ul~uncRrMM*~gnPfKzstyQA3aE~WX%LZeV-{lGxR
zV9x86%6Luaex|3K;g2<TjDQ<Jq@U6)w`vOx0@-y(?AjevzjBQ!r=MzS2gu_;EWwN&
z1K!s)u^*i7cqqAk&^Z>j6T^qXpbuL!;9}c)-87f-sxikYkvl=wi$`Hm(4FCmmccIa
z?pJX&igs;L77otJQ`30#ARbUdu9jP%*?Rv*<S62(3iva%NYW=T@3BA~NOnP7?a7$t
zzc~cOy17D~2$q9)@n6J;{Yg4qMdh~Bs&lLFksyHjXba>)<gV|3+woTshB`^~NFG9v
zd^G1QQtv1}a8tWND`{E)=wD^czHC&{Mv$NZk&G|TmD6}D>#F8$jshq3sRw~*5d(h4
zo5vrc^u9)|;<*7aH&Dlix)|U-la}yU>@d#d8;3DN&BrcV75dc^Nr38T8R7Z@2-_2a
z-6E{UP}CHlDd&ocsYQslt9<c)(;oMq7J-CyfYZT_$1}(GaJTl87Oj1WSKhVIoO5F^
zal6A_tej1Q!uvthlsWW_#Ii}wdrHksC|?SyQR$?AowDAO*D!M(fm|P=k{wTRZbhxe
z0Pc#NYc46ZvvUkZ>jWKw6voJ!VTRBDEh}pQ-v0sh@Rvx;@nn*czc*{O?vc+9#8nX=
z_0os%mWJI}KXi*|<I%<@AY&#;wz*v%%nrNFTMDsweAb2}o;UQ#7SEPQFUO|)QIRHX
zd;Nwx#=4gDrIrPRpVD9vFwdSNsY=;pme_;wF|IGHm@-$OIcWWg%)CE>;cnq#Y@4rM
zRgVTbx@2Vjkt$<%t}$_RAU6P`Wvh@m_b3Jn84DLp61`1XwlTom$UmN9lk+VGf{!*J
z{q0M{YkX{3dtq+!bI7hp=|G<XYb6<6t3Ff!KB?~>UWa0vuYe3?-^w=jHO{Z<^8V6^
z2y`Af>sIho$8fPrM_q*q5!_<3O7y`G<3Vje03AT$zfJe9EUMyx^kEmXR~L4b|A-{`
zljV$?>FOXK4w&%051_gN75FK<Un2}RF0dxz%3Xt^{6@Bg_u@pbZTxKim|CWEe;7_(
z<O<rEMkHLGZ+gD`*hCQC-#ANjU*lBVyz+|(VW!Fc@Z{>KO3+q-2CII-TD|1h?!E>f
z^xlQtDFMHDH9sIO0(#Mpoh+}QUA42ierdC|RJ!RFz^bO43+tB(<oR15{yN8==RJkd
zr`6<p_&ZOJzxskCSkM?ONEY@Rm1Q_&erw;=ZdqEz6+B>9I94jmb(vqX%(BQL5BFK?
zhQ*H5lGkmUXqP(|&)zI+lf^`Tmm^;g&))4yg1&-a`PGk@VXpv^i?QOUvIS(edVDFX
zE+wCu3qm8%knx);YBFQuD!t4=VdWW(a(w0Mp33{G-`U{(gXG-)&VOp-pedC{3GtO0
z`5^lwqFTW%!^iC;F+8KIfw$Nj+6Ha%ld+1w7Y8ZVz)0Tjzp$H22*@n%3MesgL^y{C
zXolV7l!Jg|7o(PeIyh=M9<B!3$YYknQT~H_6d|#Q5}9ToRQ9FFYPzzS4^mBV^1-W3
z(^bI6^J|?^aX_n5-EE9P76bCtGuxMP2Db$Y_+<E6!lnmqMp8h~r1OPnf}oFuU9569
zuMyz>T?fVrRG&bMcPRwdX7;=~rO~lQ>;g62Yudg%`c=R4DYCkupa6pkcQ>r9d+eO}
zHNDMfP~b24{<(-L$UEyDW@*Is@H57PpDlre`==2xqQr!CkA#DLX7`b51dbo;I3bDE
zWGVDBrq$s>95+SIe3tyY1b-($;o<?i-VUnc7V=$^VH2XH)J3H@F{mJTLG*Zo^m*Nl
zQ@!1$Ptmc)v>n4V-6ttOW(Q*yYZ-;1mL1YLZKQ5!2K%WXPBH`6R2!<i2;71L`znN$
zOxgVOcIJ7#y<{^K$h)mLLCDUgMeP#tJh3MPvJf6(R#F5$Jt1G0Fe`|3P)zs4z;HKo
z6YfEPPp)1yGDwook8?mU^>!B8VUJblP1$MXrAq_V64MIP_7NVNtgE^{$FnN0GPIuP
z6M#HF;&GYR6>=&&s}M=UcBhbs9lM}SoXVP0BPyN#)PC=c)3i36AbHg{090cknGuM2
zivU1`aU?q5M})|;*j0sTl2w;;u=R4kSb4v+cI{F2G<)?W2>7^hs#s!o+&a~1kY@pH
z9vB+&`Jbiw#Stly&^|B9ID&6d&5)5~Q<dc6if`ZIaG~-i_;Jgz5R8Wb>iaCgwsob5
zkCt74BW~1PB^@<;d~{ImaBXZM5EH*4$}C!R0{$qHAzZob`ADyC@wmb?EC9i4OQsjd
zYq#=`F%?!!iAtW0$$6GAJK^jk^Za*BVoES*f|;0bRstumeQXhijHaL#S49tMehA<j
zC@Q;kt=F3E+Ej>1mq6q6-7n^f^xk|&gvtw403`HS(GXe2D#1_|1J;@?QM%K0$IxfE
zDcZ-(9?lO%fFt(Rhwr*t0ve#^QEjHQsNW`dO3CZRZ$vf1oj_S`n0t~VeLscmO`WoQ
zJYDjT%TC!wk>vriPfJ*1QE;I{SQ@YpLf0E31trYdn_(C#$;6wP1KKL7Pmc}uJzF67
zm3b4V1BH(8REXnc?~0AC_nL-UYpHocJYdK4v${Zy(Gc%zr&#cL>J}N{b><0_zhoU`
zKOD`@YGK^DLfAVBu1Al(t3{VurZA6rv(Zg7qQP&wd&=>`4O7h!-j)2y33aInm++VE
z<gOb8kp+bgHGmb#RKMShZ2qlRLlyQsdx!Y19V#&IUh_OAXxy=#QlkD4!Fp*Q-OtEo
zI;f8hT5kTh2-(T$os5L2Y**(Xro1o}nRC;J0z>oh99Sq70fHw5m2>q`=1<clRui2<
zmg{{AIz$Ky`93pvl^1@p|7%{QQylE(3Rj*Z3E`8-w!h=y+b`OfQ5b&IV!0>Q_8S(e
z>&sL;)1nD0TLFh?t-htjbNFea%GRw5*!LlxS7LUQyrsqb3HahxCunoNUVQmIzz>@G
z8t}p~4jisHiwiy}`N802T7G;G8EBn9!1{DkHK!H!PlV?GbOVm+&HY3q2~rFdld|E9
zq8nTF?WV6B?y#TZEfSR%fa9sZ-+Lbz`jlF0UUv*Qoz>ce4Tg;$$P8aCeJ|}uwA=h`
z9NyL;*t@V5G7WoPeix)n`DJXX2VJwxHRK}){FoU`Gn!hdv^sJmWRLsgfd((Cu94hE
z&O5uK<v<s$&z{3Z+M2ihhDS~ug5(fZl@&D)N@HTJmENBJm87W$VovsOKq6cq+^3w^
zhBmrgF_)sZ_KuWHFz1Vlr^4)0172mFV*zkI#CR!H3Qu>F_;E?doX=y@n2JCJMj*k?
zza}C8H>BEz;X|m2mT0C?{s>CI1y8`UO?a_{twLyXROStbGu(#m_d0p0KC=7NbY~4l
zbE&3aECMR8_WvV5mc17m!%h`&fc+w8;fsF^I|RFK#Tr#$LREaBvc#^!UL&+U4-zeV
z-yT;__w|e==)y)Y*sLzj-fE?_udOIy2BeZ`eTf$`7mO%SCco}r)@!70MvC`kHQ<?s
z)>=!cL1Qz9-FYRF8v#?-Pd(k<KoBVBCx)Vl8$BzLc^Dfj!+;_!zNfFz5UuCZppEA$
zdTqAJ-K<Mq!oZSNt`diIohabUMw2-^`iQomyIC>HZi&C=T}f{}to$U17D`hQWN;C&
z8`VW=dcHVGehiXR28JesdRN!@v&png>F+t4`gq$*(Q{6IDs5Ad`C`7nuFN9S3YBxn
z35m%>G$yrMgn8eZ)!BJlEqZs#eXvy*|J7KF(o{fh?D<MOE5l5q&&$N~sKvx$|NI-j
zcH5R-E3$RX^c13bV)_{q+C^(KDjAJxcQDW`U3ls9DqSE2V931Z4Z+CjqU-p_Z=1`o
zaz_X`L;0ytLSXfzQoC(lD8G8LD%FS-*aeqEJ-q(|?lAd)&I(T|ownPl!LF<pWr4ku
zp#!s;)3=S;q>-W9Qj3S&YfP?t@2~5)KHaEEfg#$4GpTLG`JnCGr$s)=p&6>dfqjt=
zN9-<c*g^Po59lmCc`qwAgrL*ThQ2XZjN!4&HVieLRhX@9<Lq~l)-<d2Tcfw$o@svT
zCDF$P8@@zcIF#!QpsxgPdv?NvE@WpJ6#09fx+k|+rT9pJ#Q5+%{^k6r6*y-u>pJe;
z7e#4#QYEj_j4}9e>O|U*xT@$~e6X>qSP+35{juiv`cSxEXhhnOEfwY%nnrjrgQio~
zz>@xhAB);$c*})#R!Sl0vloozd)z^jv*QWP4YXKZ(F$`;f=%RdQi?I(`Y34tw<F|B
zJfCB#4Z*lQ@8k!s`!9Z_wFfS=bUWCVaxQ$X$eG|poKG*%<s-LxLH7*nh;fEdDh|PT
zGOc)dmDq`S1HvkiDhy)mX`&_b!(KOr6*N&(#V@?nF;U9vlLogLnncRSN^^*BSnF7K
zRlC^JAkQhq?>T`Qe-71qeR=_F9$-TGC;U$CF^E=}zKF~r1YCSV#Zo#GIRSrE1a3Y7
zTwv}nAErQZ^z}6uM1XTPMX&RkF$#i?cIHmTd@HbM&(Q*!=4ds|7X$E#XkG`7J{b36
zPGB(cJZE;HYuVY4c-)Cnfy!kVt0<Molt=)x3|(uo#8%8U=wwI>^-s%TsAKc_qeED}
zNAS^INCe?pI1rHeZQy6`p9d_<odCx!>>;;-)$JaUPrmyVKlEJzHUkxQnQOe}O<>Kl
zKQ6Umry(Qv#aB>e(N7}z%0{d!(0e}?34C_$(tt>$iQM18(sF?kcwkQ09)gpFH2WZ8
zs<y)njrNfqQjK;A(Kt#9XTQHY?nQ)y{!YQ+A$Pcx8?%~dA<K#2TW4wit^1!p>=!BX
z@$vN9l^bK$po{i`nm1^o*~#_Kr$jb)RsH#)C74i`z4TN`Y+mitkz(v!VIv@^aVp)y
z9<t?A$#Z`{lXzMo@N|?aP^32SMPvgtpyfhBid?38M{vIC=1?HGSPi&n5dxC<fJQgL
zl~nU@Hj%gl4e73L+#XK_QH8R%M7@KIht1aw7q4o?u)`;;zq9Tn&T_myP~B2x@!~TW
z1hrT$$S_;!*HYq~;rkn&G#-#imJGsLk+&7k_6dcv=73`;LFqGEJ2Xs)?#S2R9hnHt
z<{U@x@uSdMN$-f;zzWW6u>>4xeN8UV(W{1Ch@S{QwjsPht+hoZOo`@$n{^~gSCRO+
z*Y7v4$ihA`8dKM0hXyN|3niBIS{7dw&*+>cd{>0FzjrQ-Yr}%q9fI)@x`ih7HbM$U
zO{9JATv|r@#V9dDV89vVG;G5XcJLBF{G}cUxv+`DS^SBS;Qvl6ivty#>4A5bgeSNf
zZ)NeYtHflR{zSkmIGoB_-1{h#oYyOg#!lgCzQqDcMwI#$hoR&EsC~I0XuMR3@ZW2?
z0WrkJjGEYTX-+!raeaGXw$OG17)VUBSmEj%LVV2i)otfc$F!Ozxp5QoC#9;iluiJV
zb}+L*wwleEug8jD$7dpH$*|*_l{>FP?m)E9bk65H4Aw6vDOf*)5^KdQS~Ql?a~1Na
zzUUSb3?hvhB_|(5L3iO|qD)QD*c+Psw}akeF!2oHYpl1v+r<2k8`~_AbZgh*dlA9o
z_rU^7EZk%l)<5wlgTH7gJ!*S5PY`Xnn?eUA9<d%vBpN0@rkTC$dXy&!+BV*&Abect
zl@UBO$+v{@0=qg~N}TYxUjiCvMSS@PQ<V$6Z>QIrr(T~qweVtM@Bg>Q<VDUG4}FE&
zXl+U^jT0txk`rWHA6a8&Nf#StT_mr_m;MQQ)Y0A=5tF8YcpZZqTZ46Sj=KHF5f30K
zooa|UqSm13&RAh7Y3`=Trc7N*l@&iTyQ^Err2@S&S)=x>6I1sJpEg9M;W;NmG>Zj1
zWnYDDQMh*mE^1CiR1}jvWB{~tiYgnGO8!O61G=Je!dM_a{4t+*x2N()TAQqTK}Q&E
zE8<14PdCd%kBN~-{YIbHO6ZxQf$_P5c@$RS38Jy0AF8x5?5IiV1xXU(!n=y`c$Bgi
zX<3A1!nEKsL2RglCgQhT${y#YpuaO#;qL(XJspTn#d@-9$nw_a70QNGxsx%i137J>
zO(=He(aL(T)8aRB=Dg^STn`pB0!L{;aU4);LsnRcbkhX(R?hKkXCl;pT@~uMd_a>X
zRB9+ePL*_b4*+8<1dNyz`lyY@{L%4C{TETM?jgw0p&c9txk=>U3P3hAM@Fy5Sxu<M
zW7Lm>pzdrN^(=ODUy7-@yp6!!29x;23C5b7r_;rDZ1ztUTv7OgzT^QjCE-DN+<YxS
zZ7Co~ibX*Gk;T6Yv2M?km(E*Ib+YnKJ-Qb@=_11Qu7Rt1X3;D*Ox93Y9NW0UKUU#@
z@@)>m)3SpMa6oTVbI6PQdVp{YcQj=p)YpQ3B1~0%0PYZGA|M~c3pnw*&f6iP2j7<!
z#=x+!o-j~e-nfpy!(0w{BqvE?_asw|m%_HZucPhu%~WH}Vvaj9O|mofU(fd(Z1|5r
zYZm^20lqA;@2GvQ3L~sY0N;2TOk#cn00ku%&`#JYq<F4y=86Be3Pk~i_~zBjI)HLg
z5=`>_Da9iVbyug&kwTR)$B>DzSNfiD_VjN0_9b|Ae-0hKz}U$K^_sL(R3MTXCciiF
z_FW=MLkHSGb0P=xC0(Jxr5CCM7PF~#mJk{95TWY8zZ7B|3(7HN^y9KitgTOSN++pY
z=FA8d`sL&*m32i90zx>2;m~JGJ#g-T<*|3H823H@^xeqt4H`KUZq=~|v&I%~odZu2
zktWz3lf2IF%*mY6zF(=QrJrKXA#SCmpye3WJpihaZn9~ntYdntWm~w1)^gR!bM8&@
z##WJAgyeu~9*bz9JjnnEY7J>ipivTtyuymcg*qxOafxLNMm*YuJ!;x(93fis1yau5
zSR3ztO;UjG|HsQx3x6i0XwwsC|Iglr$2Acid8;#M#|+rgLb(Ntr^3U~(Q1R610PI$
zh`NP8r;Ol7PA47&XP{yMn2<LH703P_r!`T`tGqd<F=stTv;KO(N<AiOO?lYUy_hlZ
zBCa)J0_FN+P`Q&VTYGf$e0E2CgZ4s@&R=@e|A}BJiuhB<LPD=xsdP%Sk<|GPQQ3u1
z>Z-&fZ2uVK((jb{HjaOesxCs(7a_b9_9*vq){B9X`^J_$*LIeNs~FNo-BiQC45Fkn
z%&f_KKZ(N^u$Hn<WZ?Qf)WmCY6EEKK(3_-YP$#WmkR(ilgFz+Ioz7?eF~_%QKe84z
zFCVhdsAd(MISDwKv~Cap7$HXn)czzUc>^HqSXdK33PEDW32-v0E(*nW#<c29i<eU8
zR_=^ko9hoH*$rVrpM(}{9L>8cf8rOYf0JqMi#u#*K^lI?bqhFYeccgn-DcbNwoLIG
zLf_lAKDiD6p^oVvI?xEJ*^d`n_aYK)0CRjy-%GcQ;s_DbU;PTuJ4A^|+!5{{-{C^7
zymG`nifG2b5V_7_ZLmC$^#VtW(J&c9Vw<g~cXsIjVpQz6(k24DLlrg77(WI{A9beo
ze8!g3t^3W1hV%|e9+D`Jj!t7Xdf=2JG)bFX=h|bb^=nubTO$9_N_V_*y?dY|;FjUS
zkwQVA3q@(uB#2LL#SM?BgdWc$FAQKY>1n60m-$gc44_FeP9jDhK1f^W?8nrUoK%Y^
zGmm6gK_xvR=KK*Ame28bbBq-ejIMR{bLHuARMwK3;)oI<)8J8SP+!z2P6W}_S2P4V
z&mu7k*`?>6pv`BKbp$y*@<ZevYX;EUB7YUis0!dBxkv!Q$eieo=@$=fGK3V_&pUVi
zRG`b}j)fy%;T?GMeqKC#eM1yorP}KAN<SZLFz&&Se`Dr&(f{&4uHtd<ZC0ebZr{@H
zl-AOxKCTY}j9xmY!x`hZO4hG~I<SE^qrU4IQ6fnz@!XKNw}>7>cA&Qr^Qh>ayjB_T
zv4Str@S}S#{8pf-9ha9kb22uOK}j`o0F~r$v?R)i<;i|jao}WPz>PY=ntT^panb<c
zF`OZ8iiHflQ>Kfu;$^k^<#s;NaNPX4m3&GdMrjyL5>DBVw54Dg#3)Lh9AE)+pN`$B
zQ`KH&<lUfm$^<Lmjxu-w#|zBO5XC?>R8CKHMrGGor=~R7uPq5%gkT(-;rZB75K{X>
zMSM@Dxj`ItapxL!2;eF1xz=naLl&4dFOg_BOA9FNyvQN^CJzK-dP4~nf^p<IOALER
zmZlWSTPqhb3VeLLZi^Jae63yPYH2(hD8<&g@FK%h`81m4eckLbV#ErQt`6IIZQFqo
zTXS%`AoG!*qleaR%J*sgCt#!?k#XK+y&gTJ;6u_f;ePoV+tDw&-l<05awp+5fIpj6
zc$GhaQ0%+ppuya3(w)fDg#3MY!$S8r`ZpkLbVMPnW8V$+Jqpk)e+%mB6H22QW2uKS
zb|^7^dT)N;6Y)YN1!c6tQ$j~Lc*agv?e|HGeJ_?#7v_N}pwVO9KMwG=llG}5D=?;l
z5FTir#t#a|4+EsHPilfe0Cgo^DLb<FP_TOh;Rk@8&=n4a^P=lD(z(<tq%YodEzrDZ
zbQYS)`8)t@FJ;_RVjT!9oW}#BGmuLrw_!)VTr)`djmw_C#;OBRDJj&V>xe|txvzcM
zEVf#dc;z$>M$?vL<=CQ;tbVz*ck!^)Y`MyDi_iT6-F-OKyUH&SjPyV!4@18Kw+I*b
z^{WCBjWjxFf^^y`GG%KI1I7#|d=0@c;r{gZm+`FE`x@a~COrD!^=t9PzMXXy8gLty
z^+i0KvEg_-ZOK)}An@n8z>@F&Y6fR?Wm#b)#gv8i7a^u3&R8@Fd;qxxuJ&pitEfAF
z%nRiXW;_kV$P%&$6JTyIJc{vX`@XG!YV15edz6fBOBHj{N}zL}l_A30efBTUusEA(
z>9*4v21RIvWsc`xQh>pwrH|Jq*2Z<zrr%tsF3MJ5H{tS}dTHl<#H84&k~i*T21XmS
zmcE?|0J-@XlvhVhl$E}yTv6v`V~vr&FS#QJBl8IYw3bKa8QkJg8tHUUhZl;$d3(3u
zy=A}TaoQ~|7B8wp>2@S(WSs#+J+r-*`cn$3eu^j+HHGB`6Wa6Q*VCChkrZgJ6-)UJ
ztkKs@vqhc}>_#&Uqu9;F#P5y}(7f8*Up=e`*s>0^pPRQ?iwnc|94Z_x%_e@1%4U<L
zP_v7euz@id!f~$H(qfz>{d1Y=;mHU%{qo_Qz?CK%^8bbPP^eh2S-yvkF8ME_pln*U
z?Y9P>bDTY5B()S@7CgF(w<%GvWCZVaMU5esM1>xLJCQQo7u(tfnxlMsI<p`~C3K(5
zxmD$)p>k^JRd|!a@0_NC#s$}85{dYYG7iE0(}(|^+q12jfIb~I2QmV8bErxVfPmEc
zxq5-J&sW12k7ZIE%U+j>ZxzFPO2D5j@V#w;8e~nX6s&qQgby3<)lUN<!XaG{U&rl;
zNUcjT2ayok%Ko(AK*r1Sqg)<TBWV%B&cvJ^JqjwH^V9!6erb_;4K*~dws@_g`cEXQ
zM}Y)yYS}O7g>_3dA}W8`EfS0jfE=$P2I!flC%fTdSudYCHriwz#V`+GKE=8;Vx+k#
zu)~brljS^fcXk+Y>|sPTX5|w#98R#VFYAM02BlQ{ahSn75haY;mTFslYM}ld=I%!5
z%=1hJgllbLzI8^Sx7HV7tA|UM$ici(pp7?2ZSI0H1i$T}QYUKy)w)|E0KC6PFu%)p
z^oJ(8iSDwO`O+!U?g!xVJN985tPlGMvk~5!Q8%Hy2V2b_wWiOBH@Lp(Vet;kt8+wK
zVm^U~xKZnTwfvHKujT`^f@0^Zyn7I&K-55>iY64mkmx-)XtkN4Q;_paaH=86Cy8cg
z>_U_R!k!+T(Zju?{0rd_Ns|jJbNga!GWi621;Z?=MY`CEeMPJ8KqiLW!PQMulV@pH
zRI-(dXdoRM^3^)SEo49J9bl}iFtT2_F@^2->wI#NM@EVn`GO5hk$PUm+^k!LNsvjx
z*GmJ(@i>h8`h#(h1j@G0oovR&6FZun&O0EVVHEq(n>BipwJ?!>EBa)T{r$sev0e23
z_12tHM~p`{R0|ytS725loW1F@N|f3nldlK6>%$MMP+g<gbCb(Phpm~#h-k}itpiwT
z(vJ3<0_e#48f+}KP}rJgWBLhUUjeO?7r+lQ@JVWifZ>Q1wnX)TA-p4$JKDoX-snnq
z9LfEqVuywdww^D;2Z=73S7QlfCW`xfvVxI!V3lSxX-V~cUz1_IImWE7U7AcbLV-nH
zN1?CRE@%l-6ZwlSZ$(8QHfVmhPWOLYe^Z6_XE#I-VQ0CHDa$8&Y(WRLfrgh5GK|OS
z9NeY!KacZ=$wHW`dtzNlh8+-u4H=S-?pF~db%cESl`r=%*;}y_%`(TM;PSxh7G0so
z9EnSB76-Q)WNP<@OUNMqn{K1GL1rD&^G9{bo9+0W?gf)Vi+cX@tpT4e-x4M#T5_be
zBwgf*XA@PJQz<iH!>2W;Pvi5nGqfsH?py~&5s%(Q4rHQIML;OlAhtSk{m=YH-<r?$
z7-VRcilv^;`y3z=`NH!FLQX*qm4)kulNm9?TIjv4uFWFZC7+(CiR}ZcO~~u8rrj0G
zFjNnr5K_}uK!%n<MU&<gx2<V#^}_4CO0u~5+)5I|f&ky^#L-B>l`Vh}`aHqC9Y`^G
zYq<7EfO%73i*lt)d8%DIc~;#o1RHN45pr9Z4VmI(m%RRuLMvj*P_M)pvG!R;9|#2K
zGV1tuwh15Yj~OeL3qE=fz_r_x|M$N)w4p39yM;>20U>#mcQ2sgKOtuQ#6%_CA2P}8
zFQ9MDtbv9n%r;FCr7k(P=AG~g1JDTUH28nd_#Htj^u>Z*&FY7$4CO@z3%gxhYoHRe
znGjP@UC``ji<m86A~^)@k0;IeQr>@#Rt0PK)6-P;_)pXsK`Sz>`*nF`*)1f7?93Jp
zU^)!wZHi#N^gVt(fJWl6CL#6ykWbcIK_ih`sLPKo$7DuBrG({aL@jW;&=x|FvC@a5
zqvrltZbsraTK1*@>$6`S$Klgyeqm`yS(K&!kWMbcP*ztV!E-k}RT?OH%HbBbVH#QG
z1?wv6saz7Z9P(oh=UmFWVMYhnBW4gBTwtv#?JboR-P&CHc0!fFEcz4wde2s%^|3XU
zp!vS=4~`?9^j1yM6-zMM8_|hy^bo1a7aO_~oAQ-T+9EXT74mE02EJF?A9_!9oI~+Z
zVY1K?d}u<`7K^{Km2>~5q)ez0hY93cT*etx1ZOudY;38+JVW=q@L5lWrP4_LF9H~Z
zV0ft?+t@O4Lzs)MKO!x*V|9;-INBY=k@bcf+0~t{bvs$M9%}93Q8y+`7~an&ZMDCM
z`M^Nlp`uBHMIK#8&J&8s;+@%KEmLDq1=T94DSVn++D}i6p6t9xV)YIW7-VNO^#FO*
zKKh#LM#O!-AemE;eSOTe@(rhm%o_A$j0h#s7@n%Ya(K7NN+Eu!^6)rb{@8cPVQyxh
z_{z_G8(5ptKaZ|(iL}e(l;=Q}lGY@iseblIUmF8^zUU;`LEJiHFU$cqfAfWLn$m@+
zWZ<6&c!zakysxYrC>BFJpi|v6HmP&(w!(j<4i!(hw|!k)-;qW7<SWOw$I!Y<s73$z
zCK#Cr9^d(s)X$0FLM0j1i%jyT9R@fN{#%qQ0o?33-68Rb7<~6&>bP@R#y@KqvZszx
z_e~E|N#gRy3yNtt!i^mjK<XOA1iguQp~oZMaLQNfvR3a0Rl&6H$C2Y9yj7h5U4R~#
z%J_g9er=#_N*}`x93_ajBcVB>oG2e^svP*k8rfD!tP1y%v)m2fmSx+v?m9h#!|W+=
zQn2TK2r>}LEP?|$Sh}FZg!3-s;|UNMI87+c#M?#F(GgY7U&;sGO{0Te;8ye`RbYl)
zH8MQ(H=4`B1B8KeeDjNe(lBSNLzYYoi=na<zOhMl;2#BHn>Wp8Dmizd5E$siDSVu1
zxi;$YAng#vAhjw^^LyOtS#X2-*u6gAL@{Y@9TrQz<*I8(&=A~otI*LY_ctNBj1?z*
z`czQn0-ROa1X@q-+i;rSJ@7&+)DWheio?b>H(6ZpfCP)cfE{VnS@i+Pf&i2V=>*c>
ze5oJKqns1E5(Gn5S4}!&XpBmY&>vga(71KuXbTWDnk!p^oOOo=19Xqh4UKpPhODd-
zDTfOHVKx|S<>kU)RobDkwIrKKw`*O<Gq-eDS+26-t>@vkz0J`_438a7*htP&6`{O^
zB7o%?B%c+q*<f6@?Sd!*77SD#-#_bEFL}B^<dGQC;{6j}5BZZXw}bMR5~#Zt$HEto
zy0(oQF25%)#d+_k(e?KNa@g%0@?BAg9JQ4wUD+0gvX*1F^~gtgNg;nIc!XUO+3p5U
zcu_O3I7Ak}uA-(sgD#p9${(sf5;%?6mdaj2UNd|aoe7TZV2Qr(5rX=Do6p#Nf)zf>
zn%;DrwW*`c;oOJs*KCDd?DrxBU<c_|i(H(g-{cqM9(5-CA%szM#;lQ1XFM9wm|}sX
z7L&+X4;j8CP!u=I@=*@^VO&O6JH&xF5n>n;aI=N~iDEAb3~>12gy$CYG`5U_oW8i^
z(j^xAuNKO=CH+wfvK*j3=){LtS-EO**q*-(NUYI8`zwa7XP4(tA;jrZk&G*Gw`URw
zXs2%<@xUNqw>?2tDa-d`I;eO!4UtMMW56dH^eGqXNyHtIpW%S42gZ}r`bH?chZJrx
z9S6w=AfUUDQ(uSSNK%W7^UAia$jYUN5!Yq7cS`j0S$q<qs5dJ*UBWoC^UD;;$~X_h
z!sXlvkw>aWk)GDKyjE{p|9&a|=L&EA(#j>|hVSl4PUbv9H&yadZdg7#rurg?c!s2l
zl0))d91e=O<`2$z*ES|X%Lu;8zKX(FJw5XQP;YCY%Si#2?&?@C)A$Nz8!u}N7Pp0`
zd>$-KFRD?l7F_j>Y4Vt&^K}@2=IG6Jc#zEW?^?ye;3}2f)#VPNQX<dh)A7iZsB<Kw
zJc28krMtwCmnlro*!jY4Or}Qb3+7sdW!zr9TCN_4!n`C1iYmSk;J}H@Y!TAhz%j$5
zxC*q@Y;ln4OIa{_6?EL*X5Wd1&Dhnv6#=Gz67`U$9j2&m3-~G$aKdVu_Vq`j+YQEZ
zwY4zphxQmsEEZs^bY#9?J(Ko+fqoFQ<}}9pIa7Br@9~;xD{On-S7%?z_^H~VjDW>)
z#TX>iQ>Y!?A!&yy)92kENcR|IqFaQ{SiNV|`)^pvs>`kUnx0bzsJ&XkaLv1%qC)y)
z6A2RznCEU0FJG1SvN^j>^;=B!LB4}j*iOsB5z{b8t7H5*>q$qq;mOH4$r8<rz|(Xl
z4q*yU$gFcNA;H(>u{~v3He|#|)Q>z>>6c#EEF!Y>y0S0QW|MFihbZZ1I&sC|uerU|
zgW<Nzwax0YAwyXKXI!|cI>8`;Y4u}^jh??4qhn*>xsU)XotuYS&J|Ji+09M4fD4Dr
zr$>*Yu#$bCbo;s!INy3dK=uehzHogwB4FyVMFpa@Acp+PF+xtnjZ^dYI7ttEW<V>7
zRAE!74$kYZTL|aWbZIOC;%y0nOA4%WanJxrLz*@kKd|pH9u>dkO0R?-?p6hEJJbxa
z)Q2c=`<#7-nt0~2v(s&#uCVShOwo9?A5C4pZxCgS_b$~hiT8-U642||{#M27wV*2D
zi9;=nt2=+#F_oHLkYX7s)JQCwOXQ~c-bdA|Ftpv|Lw&o3F+oL)Z2I!s^vqih<zf{$
z_%1v>A2sH50a~bnw7gJv7e!b9_Jl7Gc?Y0*F8LwR*<Kn>3FlnONE*9Og-mKAGydba
zsJ5ZUh*HX0;I2g|r$Cc(c$l-&-{=e~>EwG67B@K@rg7kwszG2)-k*3*qD7EAJ(5fT
zVslvZclg$p*mvV|Gp|LQn8CqoN+dY!3n(v}cXR_cmwV&=h-O(45&f|ALko+(f#MP5
z3FQ=N@3ocwZaS-?jAO=V6{Tl|7`e!Xda$8yMnd}h9Yhv#tx6eQi(tWo{6B6TLd^M-
zyCGj@B|vXEOJKVFMY!LU@`K7sh}oIc7%VMrEjQ^1@Ba$QO_J4QR%7{vlGipv3$zsz
z@HN^F2%7!oa(n{>Q=jb*r3?BjL~B!a5%ZY|Dc-r+uYK`x(!vCRM+B9b5C1gTwLt6T
zbL{M`{5x;K;!2JJ5$?ow@GA#I53a&i78hT(QkKfc69!<HL6_~*q5r4QT%5EqTnU7z
zv-Knqy}Ev>S3p)p>uz|sHM-gWC<37Lt@9K2OqKEcZima3FEd>L@ScCYq%a7KW^>l~
z6zXM1o~eVF^rl-mP4P~<Q>9}WU!!|SWAarNP+micz>|cKQQF}SNh3E`OQkt8B>_&E
z0?t2Hz&nlr5p1{^q65Dt<8R8Ft1G(Cg~$>juJqqa+&Ig+*5?887-H(q%N!*F%dwJr
z#Vi~4-g+t-Y(zv(hJd_zH+_oPZ+>uqE)N+Kk6>8xG0oUMPT2$a`BA?%?%#uZ&a;p-
z+K)j3wUlsM;r_es%RE{eG7`#sUgGu2Ptb}-HTD(9Pvrlc)I}~-d;_>n#0N3k&9Rvh
zJw!EtewFtbsC(bOv+n?OgxSa2m$5Ec_7!kKU7^LT$@?>7vJX172atVaWiv*B2l6Nf
zOmk)eVVr<^1D%JiVtw5WCl!5F!MkqA;bG?PhMh{OFv1*!M|r)aO7pgPQ@ExoW@plP
zG_8%~-8OkEXDFs5B;Af0q<oo6NCSKr4DYf4KCUa$aX#IrDUwApyYFfK2C*ncZVn!m
zK<gNp`_?$n*y@g8e+wNQI9!T)N)(z<sQQa3VE38Ck_uL;stj1h$zB&gd|MJyd+F=8
zf2n{PN<3myJZmC%_7<Vk(QPnQplKr7!3+8~g`>Z%>(o5n)%*@plXD|gS1Jlqy~D#2
zz9n8=6<{}?{q5NxA*twa6xD-4Q57{mu$y7+5)S^>1Z#jU%}N4RTM<7Cj;yHCGR|x%
zEm<z!IKHZQ%v1^-)t(}KJaU1NeQIp}75#$B<;`S{avS@kz2x6*w)dCp=z4bc+;6CH
zE!e==jmX(F+YTv}#jtqthBMdp01~qo@dFz5h&YCCl@<T)`s&fzO-)Hp<rL5nDn-2&
z6DyFY>(?Ml!0GC`DXZQxH|>_|K*=J0(m|A6^(`wc3<We3whZ5ELRwg9GgcD@M<b^O
zpQbECohUO!l>)rP6r)pdBiqIGteAfb<PV8#eJ5!So(dy@_esd`RTEbTi#Bb_%{>e+
za7w3-B&6nRh>&~-ZKEw7uw$*(i+&OPI`~~h)gn*ht1APTrPyIIgJP1u>TsX-#`FwO
zQXwIPya+K8{mJ$0qL`jQY#srE4fGhw8AB2Tdv8s03JF<mx?_~sodg1Nuz5UG9DRd1
zCNic`Q2{snU6$cz&N2PjFZ!`VvYPHvx^FN%Z9ROb7{GMvEA8*Ve7Z!#S?VsJ3%MSO
znHkF`KdpNtw*V)w4v<as9%1p62)_LuLrx4nG-7s8%l%E0F!f6NsaBmH*7j8wH|vtb
zP`=>Ik4mu2a*v%@iw7kB+d~Pv+h>=M9dGttqz#pG_ktK4AEo%#un1}nE9k2wQDj7B
z?yc|_y&I^GRTSLu8RME~{>yqU?{-0w50uiRHK6-#0W-(vb9fguXi?cN;|43)G51{W
z^ED%Ff4N?fb?n2Oo-`G^uh)p8kanbQ-qb@`Gh2BgeGRuXNRR@>OGYlWe{uijwnLxz
z+o1Co>aDOe)^dVnuD=_o7VjIxXo}d4fZ2UL^kd1q1=67^N|j_a432@Kq5|i#8#Ox`
z*geaT)T3O6L@dTFeV+%PZ!1`(%dwoRMqaPi6b(E(@&6iNT>e1TV07(66y1VDmI$rV
zjtP26vdgQl?l<<0Y2O8Sk~OaTWk`p>j@JzVo699|twKeRTK}JeU#H{$NyHWn!knL=
zpZ&FV!aS{_xD50|0Mp?u{iU0`bpNLBO;`PlDi=o;3j4UwHv5#!RY1%<kv((<2gu`t
z#k+;M;@PK63b=+C1ZVWzfeTl^P&a{LdXGqXDtjb4O0OBvpm0IEcO2qj$h`X{l58m^
z!VElXHEs<Z(tPOq^agr{JFXasoSDhCnmGTMIzuleJK3Q1z++w+QL3DCDe~Rmhl_Y^
zV%X2virLFWq0TL69niL3VE1-N-X!Ojne+3zc)6ODMBE}Ja)@m&H5J|<;IDePtLgr(
zzl#}Nt3JJJ(05M~5Gxs;38|#uaaS;SY885AeJKbHqw7*!MEqOHhF2v$1^-3b;@KXc
zTj1z5L;z-;(<QvjT{3%xN13ctQoVovkVDg_)-mOpRrdKcy*}yTJM#PkUON*h;yY!Y
z;j1FDeXZ`=&fYY|3-Kvk-=KhrYQdtFIsoo@0}5X;`*^jaW!m6Nts9ezm^5;YT!O*v
zaa?OR25XBj4E2^=HxO~y8c%E87@$Pt2T^<w6tS#u?Adq_%n@P+8rBN2dRHllg$XI6
zCjFgGU50H97^&E7ayh>WN!$9da3V78h2`~-v^Y-yFn18z#Fi9A5EKdcZ2z}rtdN)4
zT+E<e>W~UHF@P{hEt8FxR2o?1fZaRhJ%X24!U!5IOtO+X!UA}xL$t@P+L+ADYPo$}
z_KK+9j$1IR@kSNrx^)F_Y$&A18+(%Tpz@UQzasSr&pNr7yk~}h|KDN`6NXyDk?%WW
ztY})aK7vp8Cyks_!%_KT@L0^wObL6Y=_^6rY-uSaj`Wplw0#N<#Ya<!xy?_GETw5?
z6s!&R6+l88R9buUG_xi5Q5l(Iq%d#vonc%n95UJ^oWXxt#;*A6f3K!4RWho7M=?KQ
z+DSPdhxCba4naak0MIf1F%c~9JCl+M>$oN*12rlYd4zM4yO5vTsE#sUe*r1i14hYv
zk;g~=s3ar0H4i*G_H^I*4Jah2u=XR%+og?#eEy(R|Iz0vHQYC4%UjMz_2(NtNyU4Q
zoFI;O;*-ahYO!G2z88hsaa*M3ku%PFkvI5N2Wo(Nw>Ma*L+>3Oa}Uuf6I>|W($Ma5
z2ih;gg1&JqR&VvLtiz`2jjiO|@Fq+5=|++!YdE4-J9}7#QpO6ng_j?_`aL%ficPav
zDi2A`xCmmUk$UVF_BTKGtfUz_n%J;a@oZ^(Zpa7beCaYiD34EcRy6MuLFGyCy&o~>
zVKF78g=?(6g^J2PSlB(ERDm2VX}z9yjSX(#xBqiqxR=N-b3dvx&vh|k-ANIJ57G|u
z(*K;mnRh9Qo*sD{23VYz4ql)v{91YDibyTV2}eEL{NaTd&~<91*%k)pVr{mR+Jv-&
zo7Ryh?RPfFj!1`n4mjoIfnhW5!ZArP#&K}vq;PAIR=SHZKUt01r_M>e*>K}VPRJsP
zd!*M1Zf8Itd%l5TxqR+Jq4AvgTyZcY)bb4mCSc_<K{u5A@ugi2kHvv|!+z;);JE5G
zE$?}hqIA6D6#5C(2YZ23^K+-_-b3nYeEcBO%J_{{fHRWC!H)Z1VcXE!tPO&PpRs{3
zG&sNEM4e(n>^^8<k6W7bWN05GIB5i8B5b_RC?B=_<iPle7!Uyludk`yHDd)EeWPH%
zHkhM@96DwgWKpLw<f8p_ozo^BCv2G=8Y|X(7~zD8DB<Sbd(BS(AYjCHxWBUgl?0nR
zH*VHO<)9JQqUl6i{X(zXR&9vbaj(5Ps9_eDDe@FG(G{oWt#GRh&kVnzo-!Gm2-^4$
zyRI^PHG!nzcv9W*#qs17zSfouM#);hh5CnRd%-2}B!VX<_hC=V0{y<QDZVgua$1kl
zcfS4_wDOt<b`z%kfv(nls0X)99@q|lPm}Gb`0G=o^g)MR=cN!4+ETv_n$ZgB5n0Tl
z4<vS%3QVkqld9QG5$|0g`rdemkc=z}Q<*~Y!f!<pzQRrDH>pUyA*7#IRa15k7W@QA
z?Fo{mimI%??B4Dh>jeVJGlf4KItb{H><p|3kqbT@HW-=CM7U7bU8A(4Ky?CI58zJx
zs%E4QjIWE{HrtE~85vghmWm0CoI>6aaqgN*Fg#$PFyq5BeMO-nQCHTF7<p*oyfn1Y
z8r2_=iUXh#4fL499Vk&XXo`gqAw>gqu$5vZ2{q@p+eEI#2zEdqU1yj>HH;7f=`))e
zznraTMji8kEOERO2zTv~*+(q-0OkwF#n2d6vJhk}D!#h@9)UB#B@*lj<6-_ksIn}9
zKrKw+W-3ue^von*sC$*`54baZpBN|ljzPYNK81k4TbsrbfE`QZ$Wv!|f`()vi+Po(
z*`OP*HB1WOmKL#e#u}9_Z$$dL1uoXgV}naQX6x(edrN;^Nsl<u$~l6;f>|BU#vAQ-
z#n49+O!FD-f&WC)zRIVi)^L@={-<vMVoD;8|9*~TM7T#<h9+Q1EjM1L^ZG#82^O%d
z+$|zpew6D=s^@{9$j61PA|xi8-RdM<AF4r8z3$Mco*WQ{LV4(@5yW_cfxjUeW@xp%
zVh@rwrzQZP@OYA4DPtdydJwaM%y|48O6*x5ehN3XxH5-KM14RjS_N>nr+Y$KW|egk
zUYNiMA;52^GDWyddhA<Z;;9Uwrm_nDS)M$KQb(9q(JwtMr8Kuq=bTWYw8VkB^s$4$
zPoF2G6dIVwBY~7K^h<&4^NrbEZRI;SM!cgE+G>#Buj-3)sR^iff`RXw-H~X!%Z|Cd
z;u8=^*NzAmNIv*+q!QwcW5?`Lf$-l|a6>A{Kdh>4cU@4Ohe=h3zDm6$(Xb<P{;xD*
z;>lS|)sNhE$045~c*>|AfwckrfrFh6JBli)t_M@nb(x7*o7>$x><X$1g2Jfhuhinb
z;{)VQt*m+=WOFO#j+H0Cl88^LdcKB8=c(oQ+wU2rx^BxI+FU(h8dYAYvr5npvxmZk
z@7t1PW>D9F#nFbQa!s(+#5#z+^Qkd<+ttTb7y$L@|D%EL6-c~P)_|4pFiBe3#LGsh
zOITrEdB>G9l-xwMLHOgI?--~$9wQ?}<@j)Xd2J3a3!Xf8&Fld`_TU}yXY~RHm}RGg
z904)FKSDA;ntqVu?lFwlXfCrm?dJ1sQgp;q&~h-^+B?&orB105qgxZfK9RrvrzYmB
z{VxFI;v;rQu-Nb@mZGho3U#FEDxkrtZ~k5@1&xi`1Ua=Ai;1!IH`RcYN+9y8d##<h
z0Uw+j8f=~tYWB?rj8Xm3EM=)2$(=oP-Y7w#v^8cKW=7t7VdWMu18|Iap^B^JzYKSG
zMV}|Y+JCeA6uW)R(k~R+)#>}cDIKRHGz0QoIcMj0&5s!j-06=2@<|<}+**W~u$3p)
z*kK7J^z2hhs-wdSKLdnIT%Kcynw&*Kpg`&ni#;J9aovDZmnRm7p!9|9I-ulVD$TnX
zEVkaA0ZOv$a4zO$7e3{bDDwjA3a~dP0)s(0Uzh;jPS2FQIA2MuZg#u+3qOS?Z?#>n
zdBC{fLyF{~6?~N)ayn>~J+@fzWDBRt<fF<Ek5&6`b|gl4iMcn4fx0b?<@L(VQJy_?
z-BnJElK{!`kfH9>R9qfjqoM{&UUI;3tch0$nR*p4J?K=;xDWBR?2Ok_?btk4t&Eg6
z`oM8(7~<}QHVIHI1y*6+(I%R?3x;%bWMDm4B=fk8>OyL5M_r|mA4OC|!k~PUs{Kmn
zga$3%9{VBh1kyKUhjt!ao=M6(MS85GQ2*STrkaXgni;#d!eLJ~s*!@DMhw9q0qAN#
zJXhF5K{F_<uQ1mp=$*%Ime1<m2cKZc(7pJbyB@vnvjX8=o~hj|Hxm%dp(iR40J`_8
z_E)=Q6YRNnuZJ$UyeA~40!6!lWVjy(3XaAsXLvG=VriuUIOcF%x0}h!@*NopVBDU9
z#vR039KUJQtwZQF8S=(HuE~swJU#sxEE?%;F62dXJlG|cUvR3?fSc<f$=$h+W@mxt
zPc({pdeq9DgEJcGMt+v5iyBJNY#c<t_;fn>)MNka`|61zj2CX%{Ogi{^gA0DR(&KT
z+gFNFr>5IfI5GCvLbPvqOD>eGC0;-A#;Xi_|5SsvZ{RKzxOsyNu=rDd<3=WF6Vlja
z<`-W3HvJ<kRfNu~&T0)l)Cniq69~V~EAf#PBJ~ftcwsXjGrFBic|N~|LWq-5c~tRu
z+3j5bBNI@{o>AnT68oocp#h7$GBzY8U(#qNG*9EI6tq9ZjFW({#Q*a#urM_@(gY|C
zOFAr|C@rd6&ROa<!+@m!fQL;uZZ}>@p4mi$_plROgvo01cinuQs0uH&T`=_W0cLD3
za1y%nE$3>L@e2PVI$X~{m^qrrg?G$Mly)w!lnp^_^P+yiI<+d%?>Q$=5`BF=zOSg1
z$|4+6cxPfRvhZ`RlzL;jZ+37=G&r7G({LW_cbp29Nq8@(|NUF*e>dIT$DfU86>Env
zv-dsC(e>nuZnxQTHOoY|$KMR?jee{zXT37Tno;ooe#MD3FFui(k7<-s0heDIzfj-v
zPLr;2I9UvG1hAB7PXhk~27$uX<mm2jVns|l!v@5s{7XX?HeH5r#u(wEa8Wkx9OBV4
zcFqw<Umv9P@x$cmo=sG!g-d?xQ8JakhTpFIEUq2v=*2r17p^Hz<M(Py`j0Lzn#_0X
zI04sSYwNdRhVzae4+fjBslz=TF`w&%1AKou+JnyF_#fi;6CHEL?%tSdV%&t`4qPq`
zr>#Gn0p0@7Vy%_T3*7UT+V|p7kZ@E;S$L@|R>GH|bGvb1Lc{Gc;{Z&W^3bEGx`PYa
zMm>R`-?F`-O*-bs18E`C^H3|I(=^t3_qxTbt5t|iXeyT>U_RDNyIqmuXaT3X)**$*
z@OT~k|IhnQ!2lz}bc}jay{IKYAb7(5bpBiZ%|;7#Gbm8{;xH%@oM7T}G89p^`NKT|
ze*2=qfG_8lN;F3UTDY7Q({`>>_MXwUj3+@^3G^D!&3k~gi~f<alShmc^`1+<)O#;A
zEp9joHR#+bY9y$Q1zjf+{P){Vm95Qu=Dp&nHloE7hF-#|XeAzP#NEepNcABH6t6d2
z1N(jOGv=ppDN%{R81f-St}XDVs_YT+r{O%<S_{dvq%lxTH7d{0hU{~S3bFH1RFWsb
zrA?Xhp22DpP2nLfs;CuYLQFP~%R;!XwSPrakZ}>nqtUUJ9;}$eU>>Eqo<~3G?<!5`
zidhhv+jeX8Tj&<pMfO!@#MB=`YQ+A+g%^5NAw{w~t|v)B#@RXfSfj%i^%aZied1*4
zSk^?<4Givi>@Q9^GunF*mUb3)f|sO;q$HHe-6)0onm>C}ov(BYNey+3=)7XF@$L>%
zDKqfd1~qsEz2ZhVQn+ccr3<AoIuN*xSv;JeBM6F3$|VE&rz+nBXUpd+lLa62$4~}Q
z0e(Q>e7t{JW>v`wSkFE%G^6Los04qvAd>!4`le~!upJ~m-q@kgS)VoL+8urx2euZx
zp>K1)d#)kue|D34%3fd1gN;6I0IGwhR!G*aKcVPtGb@t;B+_O_<tAi16;iPqx{CdS
zE<4Rt?cr?Sez`b1otAP^7N%C)_x7%)csjkHdHnqqT+T{2N=eQX-UPCPrU?cS%eAI1
z9VePLLhWrW^Im+&4u{4w`Qjsq?gi^mo0s%p@!=RjY${LUS2DM53kGse+kF$^Y-~7=
z_@SJ~Zu_l6en{oQ>IbILUuG_p(pPyS8$EC4oqjrDEozzLRGm(MdX}-2u-feQ8#aEn
zDB@jENFdjzKrFD`MYYUy$I$k%TB45#5ze6GXcg{n&317dH+V$iBmZEq%<XFC{~MT6
zN9K|>Z8K%KyVsI~z*&ciG+$`V(gC(N`n;r0i&#L%QQdD7!~nav8ho{1yUTVXWnC?`
zqUE4LOgX7LmL-c2BMI;nQ}b$5u3YF7y=PS>t`~|7)i$o0=|=ZxPQ^90;D%X|;B?0D
z4HN{oZfuWCs0pmt(Vq`jqm7n*dVQKzp2bqv3O$NhNsR|LPgI%AVd8Qrh6vu9&re=u
zTs#rgaDWs5T@P$DFs$yQY?B*bd$cfQ3<48wvkV$q`PNSMPw~gdE<MxR-IeQ}d%c_X
zcXw@ybr!6%0MhnDt1l(<GC;P{@v<R?Ic85)XKS#zXJgTbqQ_dPOFP(@^|coXr)rF?
zpOqqrw1|y$_o+q>l?7*8c@bM;YzaLT^{+|06GHJ-YZQpf+#sc;z$;K$NNQ~|)PHXd
ztg$p39(4vgT1+aayusUw@_F6<BW9wRc+X@!z5tA}-^FUSS@!qqXpr(SOhZ!kFge5_
z+2CUBfDx;)S$|yjy&Z?s5qS93H3?0aufPdDH|VN@x2<11RyH;ASzy3A_6qMNsvN&X
zy34jSqt50|7z1Qdm2FMp-lF_ngDrph+Z9PZ9+bymNto;^smHDe;gGU#`=Nh}iJ_?j
zUg{J#S$o`(1y$!9+Gr;u;5qWhrf+6qZJ%;62e}5u*yx!$;m%daot+=1u^VlH$&e`)
z6VE1#O|gKhH35~xO-X15J&a+@8m8-Q3Wg5Jm2S-%PYEJb9YRJGht(u9`N$cs;PnRF
ze^=SKkvlRoN~Y_oQr}E-{(F!O<EA(j7oyCcb8;`@TsU66%N%wJ2zCYj6PhURyC0nv
zd&`G1QANiy6pm*|U10&*BPHBUf~+vgKC~(?MYWzP4&1_?cZJ0JER%0JdPj9I#>kQ~
zGiP4WHSgA-lJ2HCXI}5KkDA#kBG%*Bnap;01aI(17>-(Z>K_4Iy+*d0i1X<3K(31)
zNyCxr2+wslp6wBePCzYHjv#TmF!N#rw<*LmKzO|Ud%ZVp_C1K%4d(4<sn2~nSxD&W
z8(wq&h3pvWT3xmx){W|PqI=SpJkg7~d8euxpZ9zuYj5Dn_2?pj3mwTs^4&(os&LAJ
zARecg6M~+A?H`r|qqOa~TO9RqMPZ!(jk#7z0-~2sh0Q+1jK0D&6b~$cQLCSx7OiXC
zcn<MdLTnNmp_L{^&>lm5XOWPq!evCBoz*=<Dwap55`{yjU0t`}GG}^Jsd1>cbOxLH
zKtTLySV7%B&7V0ToGk%YppNLdfRgxs$CTnDy~zla;2jt;RG&OII@4P(Igs$Gnge9?
zovV~XVoIQW`u6}p`tP6)eu1SwZFYK<zkK!|I=gvD1}{k=%jkpV7xPY#Z>0E=DF+3j
z?NU{=kuJZP_{wQ~nq;|;b-Aan$@!EoT;~^#p@T28Q8qYddH}Y7&mnMdWcWJ2dAICl
zZ;IXR{P@L`QS#{iPk7*aU)KxeB!@QOBudXE*|wuyQ-5oRS-AzeqXEVP*durm%DYOd
z69*H~_(6fSPw=+AS=y)D`eGf^vRVp)tXgsVx#b9^1wgFr{(F)qnDT-v8AcBSb1V>{
z=?cK?(w;YzBKJ{2ydkCx%Hjceb+y+C2hkX@vx&Iny^y$9qM}~{OP@KJUP#|P)Jq}8
z|9NwsG}<oOcd}JBf7PShJ1%umq0oPwDAY^_%p3|(^h@svyh4J(kcn2++xih}KilUB
zcy=jS7|40x6&BZpvf7=ucH`?*DU%4>VD4{=y0}%EVOPQmRA_Vex-va76JVpe&n*bb
zV*l3k!H8?5=D|G&?pjK7A|LkAh$o<VQhr8f1nnb4<v=ky@q|LaS)zmLQ+U^1ZaUv<
z_$6;iiw+&~Fv1u_c*T?0!?R!?z>ES2`&~gXT4lR&<O)92bBy+2s@er+s26sL`C8w3
ziiK*9TtG-cZFoNG`+#s2EN?r7l+J<hv?o6;=n((%2l_Zn`tx?Bt&W%1A_H{=QIyeI
z`^4Inv+Jak$|`3^#H#!9t(tgtnt!Jx0vDO13Zh2*j9#Uj8jru0aqMU@k9kU|Tmayl
z*TI!G>2-&_zDm)F6Kn0TyDKffGYGFY1xXWj%pyBaFFvf^IHcv6GKzk$1z7M@M2S+z
z>M`uZ8!~L`Q2ZS$u5q#nGS1;Qq{xSy9By8_vp}+hA|8)=yt)j@L2sWqgAA``U|#m-
z`^}&7YN?iWMzi%)Ey&BDVUL~$vt}Myc|MoswK?q`oW-u&n9p49ZeYY(2fJ8&H!zt}
zi;{(>mR!ZJr5YTR2+tq5j1iK}hG|0@EZq12wlt0NT}F$akr8^8K|WKM41lkSp}28j
z%<z9#XqR&Y4}PEhlYg2Xh-!;iw5Xv{nVzUzCK6f*2m`d_fnEXr$-GQO1{v3Iye4YB
z<v62Xw3i7tExUzE;FkjGL}xlgkwt{6Pg$_Qk&L!bsWL93d{Qpbj2@S|+I%D3{-rT}
zC`&1uu_|)7usPOUKaXuVj8nc<f**WFuYM`J0svkDh)M6SNe@P1z)z#abv_k?n0$mF
zdRJZkT;itUP|oY|ak=QNo4)@3wG0#R@VBB#yumWwR>3YnU9YnY&33e8E(0}Au=M0%
z!tr$9I{q$wPVb;T-7gXeFQ*1RxlN$0on9H@ifn{exF8&ip;_HzO<ZGydAdPtmvnTH
zozg<B3ciU!Iu9%8Y%0*qfU47^60Ytp#W8gP2<eGm;+PoAouEu|E@G0x)_c%CN?F&i
z=ye8B0^2-flhXw<h~LCUOnV^Q3;D3@iGuwCk>JrH9o~QY4<yJGl^`;<I4Rk<1jToS
zq;aAE20(|5Rt<?j-+VMm$cJ5JVZ&Mv8)7G13t%RJ^I!>D)`O{5`%^{Zl0XcE(EeV|
zE;UoUKnHBd!))+U{##w-!f3wUOqu*C-k`jB^sb%7x^9*BBMx7{DSJ$yd*&z2^|Tk`
zJ64YKk3uR?x282$Kosd$uT?9NOnrPn?72B>^w;+M@f6IsAAhJ}{3#Sl3L&`##S!4=
zM$(a`c;q!i!<vlQH%wkZ=ONwyNdeJV(=qjlGn!t$WvJ0Pyv9Wbe)FCof@FV#0#S)H
zwLrCxf4A&kM9}<<Rp2!F(84bX@}4H``z}~Ykq2g*Wzg^_|D}>L&LyS6hyDbAqLd6@
z62b(4;oog-wsKM(8GB2y`W&m01MNn%It>0b#?mKZtFL@5>Yq`dH2rPq8dm!>5}fD(
z=gWvglr^wMZpR{Ch8=z3+(wJw)*M4S-{!zcBtpB*XU!ir6RT`%1UjckMiUrKd*AYZ
z^<|tRb-zgg%snhB6~DaI(hbW;Yxf>aHnt6+@s+s}{s~&(zNQCl*)aoYr-x~xqm+|D
za8po%+@U0U@l^qovJWA2&a`DfLxg5+xA{LrrWrF<zu;oe=OzD_*vfb1(gcxfkU&#_
zqmQPhU4h%^Ywe&%U0?W0wJn^66s06pn%S*jOu@+GPHm(iLSRZsUm#CVg!8?59wudP
zC!;GHPV%WnF$RqKT25b+^)U&N0$Ff+HHgoRc<1v+-|B{TY={|4MAzR96g3n_WAV+p
z9yYSc=!O#7bT%v;g-Nx$&q1xGMJpkYS)&xAtgU9Eo~&sC77N`DiLCG>Pd~V3fpPDg
zkK*-*2QwxD3gvBOv7~?7Sm86I{C(tBxKbDcW9p~*+$#!y32CgiqFTnBW8i7FUQx%o
z9J^ZL>RBTjwQP!52W`L}7u(|%T_AhgKM69bMCX)Glug>%8j+~|pQT_JrG-d$kS>Fv
zJ38a9L|_oC9A~OSbf{D@70rY|1Nb~C6ROvA1ccqVy5(s(<52;s03Qnan|U)Pm=vbX
zhJ6cW=Dn^nqf(^zs&$-#hs~|zg-B=(DUAq&tP1cdWpd}X9xfiTlE;hR&dc3MXbFq5
zO;5E>m&4e3=C(^F_7eiV*oJm1?__|Xo7qz2Om98LrkbVVUK-(AefBB!S*dG78nn37
zv);+TCIh@O%Wta!$a%qh=($<Hj-cd_WWQ-LNq&m<VjP%7+aa&s3LEZuNqyG$HZP@&
zd66&2T#M=HQ%JId0N#2}Fxn|6!426y@`hWq-IRbGQYe?Rdveh`{?qci?0*R)1VV6z
z>Wl#09;ox&slU3|aY3A2u^l57_e;*UOgIS{$DiE7aRzqR$Ekp0sAeNx%kZ(H4EC(S
zV`D0=$C8!$FabXNc@btAlt7xl*#~g1b0Ly@XgcvOf^4Nh<xp58r#s>9Z*udwO@wTk
z&AV=8WwQ-deR2EF;a^%qizM2A9xxh?(Gvf?(1NSU;!F@3r9N5{?1-0G??}ufX4F82
zA#tIOkGrJv*3DUf2SXiO?lfI>6;F@BpB3jly?T=;@&!M&96fx5Y*Jz@p?3Thc94$p
z&^2zDI5MZrWcdQF<qV%%!K@UEf8bR^swQ@Ey@U}LKJ;CHThS{JsBbF$%97uUg@aOi
zAK%8~+ZpP%A@H~;LW?d<Yno)b11XE>j>HBG9^5zXKFv)P8tfR_VwB;*<3|d1A6vzQ
zs-=GG=@DTYYoR!kNgP&i7R8`>xKX2Yex(n(c}a&&1U-)2xKXqN|AgjbS}C>$7T4!<
zLjD}>kM_*QGa<(N07Q}QM6N@sm01ojl9MCew;u~TfXTC-B*dlN*UhogF4`+i3C43X
z(U@~^XMe>T?CtfxALZ^y=ErvZ&fzm7=hgzDTeIswJ!#%CZ9^*2gsA3fV`aC^kp8Wn
z?<&94Hzd(JBd@@oLL!$LI=Q%z&sauMDa7x<?IL6&BrXNs^mr*5c`la~yxsdfNX#(?
zdZvEeFg;puGCvz;h+<Rpw>D%-Z%x;=b%b8u1$}AYGOn@JV1X5hf6h|-0c=Vth9*t&
zo&QN0IeyGRn9kihb026FfX+aO!mNVPllgk&f8wwEG*(T3sTU9fTVtCeS*ZPPFz8Mk
zFZFo$bD5R+;g)1!d}Z|Oe<m>Fn_Nd3B}nwoxoEjdtNwt;QN9+jvd^MF7-3gXn<GcN
zjiJ5*O~j%3U|dK|*+s{%OYQEtr8p+i$zD~lBkwk1@>Q~1tl){_FL`N}(Z62s@68pZ
zUP+~~qY3_=v!UMDg?}4Gg-y_iL_xBWD){Cw>kZYoCIYYRB=StH`mi09XPBxBWy2oc
zC)lfgf1rBN!GHYf5zClX<eAjET`C}ot!p+TEdWk1(Ri&+e5Wkfe~L+jJ)*TG&6*Fp
z%D_MHtM*GLtivYF7A4JOBcyA)0CtBEO2w<D_fTNWqjzyaKaMx;xO_K(hS&@mq;mLC
z@;s}$AVyMj7OKuM;zP2js$+TRP=yiXm+T>gJ`=JB^Ttl#Jo2OxbTk}q_-n<d!`Y!b
zQ=6*(bfCMi4ez)-v!xfTPE}TOv@PJk-n}hq3=E+G@`qR4#KrSjS;0(QIG5%q!uqsR
zvMI`F!kNZh>ojt6Z~gZYK;%J%1=uDb`ziCb*#fISx_|ZB14arK<bWyFrjERsBvf|?
z{I8g1%Mlep*HeDP$1BjABv<4b@mGV;isF7TK%ycvn#KnkbFl?&v42Z5H$xAJJJGGX
zMcqt9w&#&lz`X3oOTm%eTyGM{!=d#^HKU773NnE8xbK9s!^b2&pQPi;FMOLdN8!-k
zv8i8Wm{pa^;}FMe6Vic)_KMS>inKm1zti?<=tI8CpPVHfVqp+SZnzi!SW5%z9m5QB
zjyTsn4E9@h08#24@`TxI65v(WSMwYSR|Sy<R3l&&!<sm0%0C}PmWur24^?HygI$%L
zV5<@n2i~(w_=a?wG`dxVVRgahT^nZa0;hG~2W;h4Zw{?;@GAOpz&H0<OCa>69W##C
zTE&iCJMPPxCHKXkn~X;;E|zBl+sDL+opQbi8)&>P!Utp>=R2@Fvr=DKfQ<69aMQY&
zwe@hx)G{kub=@9I*r`M78TeK6SLva`TPNkd^}3^P#k4S-i$s~6=KFzkk`~M<@jM2$
zGdVZH&xm6cBpi^)+1miF0jI=(4e14}!lI(Vcy>=cp|uT=X8QiwiF`7{_)p+9F%y`J
zH=Yq6#2yFV*|Y`q2KT)fuLgzEFNzekBc9O#JEC}*yoglO0S!Q?5qm|b9G#)k*obY7
zlzX*@WAmxsC>|>FgufI<i>9{$AdCm!$6Vg8>SrEesaIj)ow(Z`!r3}B{3jeYi+qpN
z<9Bohe%cvPo~k)gr}IUT<$}`ghV(VWm=hbX*lP$b^K@;ac~U&PFPlaF9COdgj0JrT
z+UCm^KWvlyaKpSoE^nPh3?_-WCznew=_I;hqyJHDA5l0M+$jXb%ml@_u^tHneKI8;
ztL>{RO%OllMshOD4<giIR@+|>?kO^$^NN%r6R>_$tr)c^ZOx;-Ll-mcYoZm^T3xR4
z;u+JAceke8KLom|p|tJBtOaOqv~$0-?ZgNXy&bmJ*%D)8eaH|{)m>@U)5wCiW^T(n
z{e)^WsL4z_UE!*}3y)$$Z;-eaS4RM4M1_%~<QB5s2q0hmS%nzny6B&dEHG)wI3&S^
z(q&~l2iI178KhGy8_B`iE6J%~(T2F*$iAAFd9;qR4!YDR^8U(Eb7<A);_83j#ay%>
zzLF@%XbTAW@B!l1f+sqCcw8ccVfreKTRhy$HCwkq=h{~`T75iWvtIFVC%G`{Hoc5p
z==G!nWAYNdEC(F}!G)~((m!GIIE%!A3&@Af+f<N?((~1c!p#{JLEy$Qb8+2;7~wa{
z^7@E#E^Nvjd5Ofu(tqQ77u+;x_oQl+w+OrLWAaDE4B+id!Hyx`_Tg!!CgSO3F!5FC
zXlLyTiP6jemCe+FAB5;CMS7fqR%SZ-!(YAL45DTxblGTuOHA*<sagb7z8&@9K>HH2
z(OYXn{A=Nq+PGPCrM+%6O)4ZXzTRki>yEVh&z0eEiMFY(HdZ~!UlWP`$!9nl{itBg
z1vG=Tl$k3>2n)}_4RzId3Q^JO=w(boYMr#gd8fd|&|_*eLZz1_UAxHIGh4w=yOQiW
z${RmP?zbq=E0)udIfC4X)0*tOKCdRdS)dz#*J@7h{|t9)8EHHy82VHm<28LUc@cHo
zwIbYsVk%~pn}~+(l2C+UCQTj=G^D5%g3(Y-q=IHt++udG{sC_kJ4d8RSs=CClXaGH
zqR25=l1t{ZvRPK43BRj51zdyMzQW~=H+wuud2#or)Tt=}hF!gmcv=W$uf?HCGKbd)
z7e~uih-<u~&Ou7F%qUi$uyD*7ha-Vzo;)MWpjwP)T8heJU9lYTqg(&%YwnAn^hEC-
zpW{2lj-<*ERE|<;GhciSNMs4L<%udkqYyI}H7jm9KXBcB-0joxasK7SzQl^`sBSeZ
z_^+OItlYMC@=-_JBrWYh2ISj{xQ-No<&0>~noma4cF9|zM#Y^5QmJb6;OZN|MhD+&
zXsbu0!MlUDO0oo<I;<mm=_P;LJieWTW%gIxRJD@T|H-ze?e-S5jeH3=m9o8__~9iI
z68oFf$E*qh5$ytn$Vk+x8!tzA&t>NMR+8N)UaOr3TsSjQo)&Udfb-&>{0B}V-haKZ
z$U)(lh#ty=B)<uEWMdZQsOq|`TGfGk>*M_osc@CRAKYtm5rV1}!Q5{9AM&hGTws8<
zG`m-?KGABr1T9`L{LWRX`q1)nvErVnT?mS;#%}9cy^pAb0eKJn)?^9q>^@;8iF_5~
zWT%}giltL7!2*qcow5!`0K97NZ7uBi0lh(UE;8WG#Gj!UAdHphaK>G_PjZQ{?3SQa
zstAu>mWM0+LY!&>{O*}O->59fPUqf2ZC4b+;8V2s{%*R2n4Agd**Z1$g)+8MnC8q+
z*L7~}m6XDt@*_XI>f$pb5mt_sTSAi}(*Ww&)=2!yP0x~cg8rZ(`Vv|Hg9MmVJ^#@n
zmGL<CDvGNIX?$gSs-IaUj57_Z$fV5n^-K=$NObOGZ@PR$oex5>v~zx~@pc<g3Wc{P
zk-v8osw<*4i&YG=e9!BxVn9JFZcx95>vra934C3Mr~6RPTWBm#Cke=8W`&tRH9+#i
zPg6=t8Cz2g99rkef%RZwc@lj^4?`=8X>r<8Y6Z@t#DteNtp=Tw+g^I3_cFF$@dbo~
zGc^zAHLa=W&Qc-d3<+iT(g2euZm<bWg2FEfo6(AIy-Fa(!HJ4HoG5Nn9<~h4zT;P5
zbfGT1LrlXza9DK3#`LD($u!=VqaxA)XWh`~A~(5QhtSKS(W{JJP9wmR4$!H{y@9=W
z^0Ozh;G~z|JA;P$EUAV164AGar%!I_?mc3j4OOp)|3MRrDd}7PI*+XKqxW!tp8LF8
zXEo+YS0Z0NvFz7#2%Mc8ocm$2dpRjpKZMA<8}rGEl)mHS^cy?Vi`xs5U~xc+&<teV
zQ=qAFM)p7sESWD9=18Pv*4hD2V=xNG0Rx%CO%W2lZ;Uz$Eo&R`QUB5E;m914dL!C)
zF!X|AkS4Shg<Ux?{OmNKO+4ojimp-qRjhD-`KkpKJDG<T<7&CVEupyarGYiW#i;DY
zV$RXU3K-b8JxLpNQoz)h$7*L1WK-s3gCk650W+8ZA9v;anxCyU<zv$SXqlMG^_Ac6
zySTkWqG8OH);Q0hp!ro{wxceUdvNIswh=^^IDuDz)NmmnVSoF_o^YhmX2(=t&Cgli
z{oYR%Sk_L40}u|oj=&OecfFW3K19+~J_LB{22YFK$QleNtply6<{t_~(Dc#0LTn6s
z7AtkcKn5U@6QNgnEf_f5nq0Jy5=h1ppP>Hi+<22p*1|<GKOpW`(!}Vu8;#i%89z-D
zv;=v{mK>`mj6|POQA5KJ5Y2HY=a%JK_7qsU-I-Tsrp)+zVBva4V8eh5RQuEgqudRF
zgvRvjy~T8F+x0q_pQXN8h`ZuI3fj;YO&lxVF6x6|@v9nYV1zK$^Z&aVU%J%46T=_0
zy8yI|%C4dfz9ZHOdH)%fF`?H<%5}p;@l6`?f}X->=bQMQdzW`5m+%KT%juA&TCe}W
zOyD&oM%6~@t_ch{7=?tAu?9A89%MX*Yf7cAN%N`?GJt0?)*ODvXf{BIkAXB-@)zQ%
zT=P?&x%Y`0xxdzn+Sj~^?TPlH)lq2z!KRdR6n@FMOfvK3ZzVwCOV+VQTXe1=<)ns5
zqCM>!Y$7l?!&YG<=t-srvBZ5WBvE9_lPwHu_G0fPl{3h3Pl<@WR9n|7d;M%8xS6L<
ze8sqF@J0Rdq5#Pb4e~$b`WoN_<&>~_XYlS`jpoeQkb)E6PaHmMw>g7XBi39R5X#wA
zKAzR!cgn{bk0)0(bzN(e8-r6|eX$_R#(>HT#@=iHQ1cD8lZ1endB=jQ=@Al{&TFZf
zgbK$x8xRf;)I-&!#>-uM`OjjvYF&1N9BGEiuEpn9J3ZwYJ-&MRhUyn``r8R4?J-I<
z{Dt9y?lYK}XJ9Co8ncU5crYRUwkf8G8Yt7UNtakYy^vyNkO76~2poWA?8>03kXaC3
zc<{pY6J_0nGTm)X_YEmU-&Gaf|5^JXupr8<kL9e}1%*@<MyrfP)f4Q7f~9FUv@hBX
zY}~ACRPLNdhQy6rIvp4rleqSz4IqT2qMLnQvZ}sbdF9BKe-6aoRqybcj0ZUz+yg>6
z#`a_OW+yH_XC8p<5qYn-cDm+HmA9Yv9$$%0;bCt^qp+!xqS~X+Ty27i{9Cd()c`M&
zU~(szEm^s%p(KRV(lYnW-@gdVD;64Foot7#u3q!niZrSgyTw(swE9;0X*m$4#1kIU
z!a}p3>n!xkO~?!I^9-WB$HDz>9_ANGfuO6j(BX$gf6c=^n()ZFwpg+J>LQI9sq(nd
zNGK4SMK(^i!|E;_z}+2}n($CObjA~~nHHUp+~p-9Xj;?XK9y}KjMcKaJZZer*2<~k
zy=RgSKo}k7)zSkHY<m=ypsHC<;8d6KFSxl<>m-JE_Z6AZ4{rPnby@BkL*{9&nG8eE
zma=?LeYgcUkn0~=<}NxFXDelL78t=aS9@P96!EoVGe}7gy_R<2<RU_sVl}Vvzi|`x
z4V@tqbE+{pL#f?ld(-VTV^P!>VOQfKjtt4Wg+Wi7r4FUym#vP|t?(qFoV1%AnP#>I
zgU$|K?TDyFJC3s9Q!~$<3DfIks}`a@&c)aV?si-(QmsbxVg0UdSx){O*86T1@zU5o
zuM{ogGw&ci(-K=C?ckil4J>1G5f(M-<?O#CSN?cX7hS3c?)Lp@=WJE=$DcBRv>{`I
zU&qf)FU(wnz=wQx>3S@y3P)$Y1UMAOqX+88f?Q3l)GAR-kDQ3T8gu0~%yOhqhxUti
zHKpG^55s!>?6+lXqVJI2B*xbhFN08%l$cEt=aIe$VHTKb+J~GSi^)-_?*JfsJ65RK
zT8rFpOJtE3_Zo@Qr+n~)Vv}1>U#+GBGF1AQIAOjcj%%B(i_*ea>==;F9IcV~D!#F_
zk2WEGv2b66Kk&y5pX*@a4x=}UizpBz6k6Qg5SEy~DYb4Z_I`^qh%N0T$3EkfaQS}M
z`$ZRvDW}7&UQ<w`yc~fM)bv)imPEQi=v?1s0XY5*T-*(V00;V>wW=QTai`iaEzh~f
z9=EkIKt?;hF2#GU;w=S>Aq+mi=B8Ekq1ZU2@2(9*_gbhNlJFaz<*~g4&UBNvUHrP3
zs9w(UL?=D?5Un_IBs@TFI2Dk+7=3LJBg&~c)}`rC{=nqjzyqB$#BeH|_RkmOCCrB5
zB1)jRIg>mudN5VhWi9GHZ0&a*0xAk>D5r+`G?64#+7Z+q-k-NQa|)QGXY2vBMG$*!
zn{prz(<$`~vZLP-d=K&M_EM19q9nxWeM`cNnfF|(n%xM>Dp>cibfqK3h($W)NAL2t
zdSxE!N`Sayube&6(~Xr#I9?C6idph*MXK{4>>0wouXUq~^cc(qD~@~t-sJK*tWy@y
z3W}z6yG!OOK{b{%*Rq)?42dgiLv}6GG@aMI>+)7%?Jo@1{unI9Hupg$$wlC;yw+I-
zEj4X|Cr<`lD8OXN=RzotrjWZIN}dZ43hmA<P$KAD3pe*`PHa`;yU~&F+6}*;*+1bJ
zM)Y6ija2@KrbX8*N%=v}@_m#i=`bU4d-Bvd(68PB_JMM#mZcfE4ca~BX5U-wJs|Gh
z1Ri}2m+eY)?$(s<-laI!@V92#Chdc7MD53)1pxCkzj=5@?`<=|`Ac`Yf9W46iLLV~
zjw7+F&OUS=UNKqNIZQ8=N5v=~BoEs1_GD?YrW7tX+7ouS9l-Sk@~L!lxhjpDCCY?N
zvv=h-asLA<mU~FQk0V>?A=_IV)+F@%3XO6RkdSKPz97#ffs!ZtqH15tCQ`wFQ@HE&
z=!dA8d;TIR-}rZh<g|FC6;;hbq0#=Fir*uL`@r1N%&o$IW|;fuVt>??wzfLU#-NJr
z&Xglm%l6+M?Vrp(HQCE*m7_07@b40Tu^Gfv$YZDGo+KXA75N4k1`q>Kh{Sx<JOY>w
zuF<|_w{nCx4Rd|RN{`s8>->qS1$FhFuRd*Z3m71er`!)S<3D8Rfatn%FBFYwMSeRe
zXs6+Bx57LIoZ5;QcPg$b_ATadTL-TASsu;CT)CoM9m|UmpSZUS#!?3-&Mk>lrZUgb
zz#Pb0wL4Q$lO$hTk;J;5Pd<x*QW}(cfrD$~jhy3^-R_|VR2Eq-LCT%<@QMNvv~|6~
zR}!<uEK>J1MaGOpV^r?B;0)`U(%xm;1wvFbeV>&3x1_2_^@-PTy0f7_7Q~j`(glC0
zjwF8!kFH=L)<RB`(iF2>UV_#?oi_u2oOE)$Cl;tw6@mdhphG=q*^8OlbjLaC1<VYA
zgRJZbqg*!r9usQ%INdq_<wsKUQ&A4|x%0yj$*Q{nYo)+rjGlGBZ;CV^w)fbl6pTAR
zBGlxJ+q9&DC?J%|FVAgPFAizMgW1?EkJH}cOX|V#%F9)1Ql<ozb$x0QEc}rogvdQw
zg_%kX#HogH6Y<VL^Zji2L}Lo>KPy~W2^gv}5+fc}#uTF&)XG(4kGR*}U8id7ieP=w
zlpUk4)OCHZ5>sDc{B0=|tW~Cv=zv-{gB^hBo~$4&Dit7O37J0lTult(N`#;Xn!f{6
zTm9lxT{8|-U}f{%0m?QZYrT|&q)K{UFu^|Du^)Dy-$-bRh+L05HCS;mA%?b;@Fj`^
z_Pi|zW$NpUq~9AyY78yt#cr31L-Z;;B`zA~LCTQp_0Oeb0J6@wM(s-__kcP_$U1xP
zi2a;kz>f187xOc#u0^>uS#8g(&G)W2$np(0J6re=jh;UQU4Ur7w|>XwvzU@JqnC35
z{5Ehdc+2i;lDu?dGb^Vj1OEJE8h&#CSc?_n1dMq%bL4_JxYIYs@*-$yeX}t>%D+<|
zYL=zY8dUfC=D{6&!fcQF_Vva{URz#inky`CrcG^j73c&7NmEl2G{!_yc%4e1x=kR;
zt|g5YW4F3d6HZlr4}-w0Kt=xRF|DOjY1kNY8>wHt!|44~jXbzn*Z093p~|%4_~gp~
z%W0P6c8e2{mJ;_yrOhcyxuoB-v+5N&S%&YxTAlSr6@<!#frV<0{&83s*FdB{X6RGQ
zyp~Th#@@9r&@=Cl2Y2jOC+p37qI-J-QG~aY=9)|+8IOTatX3LLDJqNbOKl1_x0xj3
zsA^%JDj@t?0un~~vB;}LVsx7%kKGhvaz-O#1V}y{>;LMM6SAz|cM$sdFvhb9bkH@+
z^eH><Nxqkm)PpF2$YB~zvjX5cqp`gxEFRgN715LRw3^!dU6N&)A53TW{OJsJLanfz
z5AhJ*$!Bi74qZ08Jd>7W3(tOx9;PSVV)QuwJ1KN(RX#t7cd68HJA_Y6SqGqXDGIK0
zqNC$y0+}<rg!nvSt-D+?3TY{u!#Oc^fCF4*I2SQw1>T2*_|`2&G*yeHCy!|*{Bz2m
wx)SsrN+XF~G{{BooOL~k6~QYV$po|1f3zD-eHozaBGhFWRt_y~`e`WD5ILsPO#lD@

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_rx_stat_extract.v
new file mode 100644
index 0000000000000000000000000000000000000000..f4aa4c0dc73187b0dd3930a9a315e7e0dab47dea
GIT binary patch
literal 17368
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxD2u3I2(6Tl>8*h(kr
zmrUj$vDa((G+eA4A(AIuVF;$m^NXH(b<g0w2&H7{b!?HkhP6KmUzqjhccO27c;3kv
z-nO;=^vAKAV?$eE_13$EtEG}dPCbTC?E9jOA8)AdGfdDM=hD+<m;avF(VpDeySQwO
zV#{mc7~yN<NBteb)iX<lma$p0v^NJsa!uOHV6IDqEmWT?9ypD~g_oZH1$w&TT3Z`%
z-A!NPV%eH6IK09(E48+GLp_iriMe^U)0W#n94PO7Xcf}@HV{Ru|D8h!WnZEfjDA|t
z!_Hc2<n5?wg@Y@Zum^pJcFWUZwErSHLa4a<q)8zrY!~xC9<_nD!2pCbg+6C02Y8O)
z>AobFyMQlsP+yZv^#Z=c^}|-DL=(G^ynqyv7U79sDwM{#P@RoToFKnq^;T}_I-`I~
z&uNdU{abJG?F4E}Aw|T(Izr=&n#ps%d+qGcM^qoNZL4mr6J3vSw}?oB9kpJExwAm6
zL!(ab$`zv;#^&-jh!3y2&xv#4-H?v{>feBYfqkmDL5tA^%spk8=0Q<Cil&$*QQLm2
zG14?+YG;;DH_ZDeT<max!87q%i6-*)<vAM<#lN)>bo%do%)5^JpqPx_W0KBNi0akH
z8N9fM=5Fb5?v1`X*m|uMy9y*E;&^^UvZ2{!j(PyijfTsoH$NZ+M97emL^R2G5#7UT
zr5w{r10E2Mq)1<};@cv}keORLspU&guY7HQOgb(u)X+fXNs4GDVxGjQGIxi!Xm)O$
zPY%k2RzTw01HYn8UzTn5kb6WxvJQYY6>RB;Xk^-*sQZv;*w25j206@nCL_s)=S0*G
z)M!sEKZwOsM7<q~PSPUTPnwUoEZ0fr3%OH%D9q*b#f#m&{24O*&0G-ySiP-ekORxr
zkHFU`t2OJ}?2jfJ`H$``cwUId<um2}-51rlpWN4rB4+5#ZDu+#SURvR;40s#ooQ$S
z+DmK%R-I3q)`6|hh$$><royze6jqN|BD2RM<w%-#>QL%Hp4M`kKE2hk^^d}&&h4lY
z{@(OXU~n38fRK3yGH6HiZZV7Hp5x?d`M{n%%QQ4CVL~0D`te7J^|l)~J8MpE6mLD|
z9TwQ()Ep*i|7JE?3T!J9m_xi~&DPVT*2MYE2zK6Ab1@fzIyao~Ls?}VU3f|CB+zTW
z4t=_(FqFqavBWk8w~+wIK~`_nZe1Z<&9s&ifcg&zGZal?SyocWj8+e4^T+4%V%a~~
z$%L<+XiJ;Q1>8pN%r7@AB2zlbe6=(P$AKe0SOT$KEShqWP?NOwgr5s$GlZ&uEGMC7
zGeMtH-J1XIFYT;0F%b;vN+h~nMXHWCl#9xq_WE{kyXVe_S>%Hakj#$q=CWH%P3h~Y
z^sbV=*4X+Zl+46Iha{n823__dJlXp*CJk!9teG5YQ}a%oFM`}{5|uqyo?7*ePgI7s
zPfVDivb@_CTFfm%YE%vQHqCV9Fz;F$(YEN!Uv43fZSd{T3CQ;qjC1zY7+hr`hv5oC
zsjRgp+rW(!hXF>$-qe`hdtpxeh{YhY6e7WQuCFZSNzL$Gn>+TT(_PZz*`{Fum)<s|
zq>G1dSKsvw=IyjsJq`l2J0LYQ3h%27^pnOI_wpqb-o<<(F)i2eQ9b0tcHSj8H~e(B
zyR8-a9IAz(?v}@B4FL2B;D({ZW>cQ(#m_5^q3PTGqKEXK!QIUkze49(B@RxwcmW6C
zA9(;oh05Jm%>K*0;dql@hbxOTtYuEh3&?bFAUzzM!oUKtn&ETi7BFanw8p>~{nk(9
zLY)6-Fl8m2|7h??wZoR-)^3<m^s7_xZ7?u2G7!nb9EaHGS&Je=v<zh$rhy4REb<=L
zl+ahO2y<wcTLsc-H8>)AX<nIa9WV>_!>>IV3i~&bkWkUr!kVj^Q+BJ1l}>n)8z6ZF
zIY@BYnuroThrW3hSlR1(A+9z`c`F3z3D_TqxZhYMfc2Re>T-PU9;x}QLEkyA&9`@s
zbM;OXeVeqL98_=AL)9<}iMawb<t*#-aTW^uWnA>qIePKy<<}{yphPhA|E>CE8&d>A
z$EvxU%BWuT>9%QI9$LH4cW^xV&V}NeSy(@z5&t@q(sKA~)T3({oWx4QmPtoJ{T-k!
zeiKh3xO>evRb7?wikgUs(WBMoi+WEJF?r{cL)q<*sORy?wsYjf_@YR=beA{7VX~&&
z7sg%1V(t6Rozp$%7lQCL=#x~&x|W!^HJVbd2&7dQ^o|Tk;$pQYV_>Dg_&wh9m*olC
z0hJyR6i{)ULpelCSt?|xoFOBFVQTIj{6XjvVyaJ|^?Bv=nxgQiQchYQO*XO|E-^79
zC34r5JY>=6Y_6(ij{gUCzev2P4Pz7xEw(8n>*K%>yGeU3E4qQb2dJ(jNC_qO!=Fvf
z(HiOiz$j?NbICf*K0e;nF9N#sO*kO+?F@pXa=z-|8_W0?MI0g=$vA2}rM6o&U8IYQ
zVKHx~pDL*kFW29E&Y0)S#dswq-~N52WxyO5<i999D<BQG08u2_-GggNR!zD{ABG|v
zkhSVt#O!uP^<y;^_sz!joJ<S3^Ga%#(J^k5W--PLvnNIduOXmJeRQsWW@jhi2zpj@
z;=4BOTDjm3C-F^p%VQ*02Y-q|z*JY}pG*L_U`ZeaUH^c21{Vw8OSma1>No-5YB>MF
zsYVid9VQxjn_JPq{dyp=wRnN2$TbM?Me%pc>^-?So-PD)yz~~yuaWizr4QPLok&t4
zJ3f3!N(0c-NcU9V?0mhRE)n^my(lP~&pN?_JoWAOsLDNbuU1uwCOC8>3I<fXm?d#b
zUQqVwcG|1r(<hf1{;Ipa344*nXA<1{5BI@|Z1EGV@(xhw6)4CUdFoID^Pj8-+C;*M
zArRls#(Iy085WyR`AP_G*@<UCFp|zD{E)|5ub5DM2JE%urZ{oW-~5{oxLsavC<M9i
z;Z7luOxa=`dbx9UO`!IO@JEbf`Ug5H>%_(<v76_!uAF#kn6`AlMBc`JRXy;tSgwd_
z#wn=LN!&kcBN3D8sW`ez*y$a^Ew%f4pG<u{1w#p$OcE*d&v4yLdR{1N`J2ISwG~U{
zc8}>e0>`%q5&53EdPV;G-}Y%J=wz+`2Fk{;>U%>K0<9<$rT<E0A<$6X0MZXgyglp~
zj1+{hmZ8gC#9u|d!hs!V?a__!IjDbj$-Jfv`If|GnNUG><ZWWe&+4Twf*jObz>YcW
zft@WxwPZ9A;v4bEO?{5a8p+mJLSBfIt2DdKbzmosS155GJP0BS^+G$U&6fq$s!-X8
z(~y0P(R?<>(dE&e5Ct(STlDnRmA~Bwo2c7wlI#ElY=1DSlilpou$3Si0{GNbM#@BF
z$fXACZcS0^5I^!_774DHyfi|0rTZ}JL*J-kMe4a?tA3i5Z7bwWrGvK_XK_NOBTpbb
zs93spHi)t@8A$$mqpu0|_K60M((LtTOe{n>bapXNH%^Lj(8A2{T^B%WJ|@*cY2)A5
z6@%a=8MV$-$FMmBwHwuHF7nFccK50lU1CG=DAbWTJAV$3l)_ijTp+w1tGw&PpG0V^
z?f_stA<z%2OSP=TRWn2q^GqM|UMgvI-&+Te=&Qxvy`u@}27Ca>ozti5Q5$w5Mx;vw
z0Z}A}CuU?U#nSy0?WP{EuccyGY~{q!Z>3-0TmQ}bS?3&WJp%PD?A$cUXBt$l)DJ;N
ze*88PCJW|^pZhV_UpwY?z@HxS;7kJ$PUT-{0WR{L&NaN)exudynOyRek){8Mr|JHl
zR0;ms`5ArZt382H##H48k!Xv+=^ZiUR;s6^J#lBNCMt<79I36!m=PRd*Z6Izlx5>d
z|By;PLgR>wxQtdDMKE|xXXX9Fy3y;ZR!Zlwm26rPPach*&Sdh*62{)$jOem%78YTd
zb<jD$UE7lF6%NSNKQ!jwe*?vP)BL5#>z_V=Ux?giyN#rL9euK2ptbYtPoAV_=tFMm
z53lofF9DESO|+OTobwEwENB((hK1o$29b+r`#ldogk>8nRJ}|-N_bt!apbR*aNd4<
zgamNv289~B42dzaLf!PNZ3k``h3duBfobEA4t#^4u}ZRO7MlGaI-*41WmppvJiicm
z7j#@Z1>wg%;w*HxJ4a{+iZnr#<_6e71<-|XT<_gE>SRMrB<_ep4+CCE*yRdq<E1x?
zqPXPeW8#)b4H*$|U8@SXW5Uq|_uWneJ&+Hv`ee;@Zp_%{)D*mb$i$W=n<DXAn>*ve
z5XKUZZ4khgJPgO=UaP=m{yp4zwr|QlQ|X2MO4D+5F4tpVh{?PFlkVm^n+zqGF^$Lv
z^A*%K(#?p@j&5*odtY6kJY^Q&e+9xfdw>%xSb5RvlW*CMGNH2uSPT1iXZ}>>?W{q{
z5UT;7PdtWN?g|BHn&CELh0vGxXEj24o8W;sZ+w1*lJCR`;g}?USrq-slPFNS>-A5u
zB;^)FLKGt^)<9^8b&$I@zk<=3*WB#|g^sT)Ja;f|3upXPsFh*Xz|h4%hYFZ+>zMVy
zbhP@8h@z{Ys$}*X_^)?BH4f(=A?7G}P&Q_mys#nX)}ADpx?NokUbJnd0ew!fxECj=
zCxkM5z2#mO=Lv?%?aXwf%1kNl8;*4E-eZ^ZcnCRl%k)u|u~Xm{wwS7JHm$4eii92?
zyBRM*MlFomar$v|&NFx#;-k+ORMXTdLu11YJHW*%3Hs3PyWcN5i4WAUtfi9pWS!$g
zMUH+6s?l*2|5BMVCB$}Lt%lfVC&ZQv7*s`?_r(}R`@f4F!P04cXV9w72|znU0fu(Z
z&a|Zrjr|7AbvaEHV(7@u<I=+jSW=hHp#o@U=zF9+V=AuiTJsUU`G8xD!viP>(K4BS
zhL!C~hoKuX8b4qxpQ$ZR`0BlE7T%=}R32BfvtB_OAOWHBMgnvJMf4=cHT{9ruUGB>
zD4!CEW`pu{$vLYL%Rw0^P2L~w865V*rWejQ15k<Af+?Z6qd^EP_ZNsk&DqE-lEWpt
zmaE5Dh*)GQGZ+pN+`f?PS6JH=u_$3R-u;(O-&udR*G|wmYKn6Z5=u7d2ug}2n#Hjv
zf%PzD{MfPrV`jjCcr^gu99J-vaR$g^`Xc#J4#~eo_WlSjyOYf(Y#}$(>)E0Ke?`AR
z5S213P(Zeran1R9P8DYMV*5DWmYrGp8VAWxnR3LprRL9A4{LV~nJXqS`i7gySwt$j
z$m1T_9ag3CwS3Xw>qMG6-TnU8Qltr7eE6y{Y7u&m-bNY7-R58oE#6q)X)F0S6k-nv
zK?-u}cp2FxEnGu3gx(EZd#i;^u=On?q{EB0L(9Yzh8ZyuZ7+_^Fh(jGDW&fIu;nzZ
zi9aAw8jvfO_RTExpYRVt(~lBN*=NNnYm5Ib#z^+jp)8f$TeHDq1A&{j@#Hzd3g8;o
zuA%aU>n1W>+|eH(QITp8zDPG^y!2oRDhAiB(qLYz@;&uf#k7eLAuh~*lNzo*6`JFV
zsl03wS$475$&eS8K`}wnwjB6IH~Bb1<kkQOI~vtKC-fjXlg_onwyb~2i60R-1=0$b
zdc+9D(Bj4qLY}RslNG`y%u6ccp^~XSiS<jRTv?kQr)FfhaxX!NSK}e4I-RVy!@qAE
z%7Bs&JK@vvQ_ZI<r|lhZ;{|zOH+{Uc7u@F*DuTOdJmB<g$DCFBTT=yJ`vXP9ehLz7
z{@!!*;8K(?A+W+8XBaq^9sFSXXjv-w$G)+SadwBkj{d3%?%}<kxl)SrWiDE84M-f8
zDj$c2*J0@4;$Y3jz-u~hVCAMO570<F*AX5gI#~mr#f(G274=3i+)O|6FAlc8^0h;D
z%==rT@P<$H&4oO~zl|xXZC6W;dUDZ!UhcKYoGwa#e6E52N}QDBcuD-BJ>W)FiiGj(
zI_-kVK{R7;VcM*)!)8)`d^xe*F9C1YHe%TyW)-KUi1>#nXp*da{VFUb=8#$qev|3-
zxe)h1nYf%CN-TyT>sShu=_<M*tTfo--s?*(-Vs%rPiXB7=1bXOq{4mE&x?J@lSMgF
zjEgar_u?d!USwv4qcBm^JxpeLxUkCe?5YlRI{hxoZEIGx>$-T=t~vqk=EujODBcEW
z`<xz7Cw83+0{u;DK$%F9Eu@14xeu~0A!W|&x!Xx!G*zQ}q(kP;qCgI_!yrNLrvQ*W
z(E@(68vETHL(51cg;F9J*-JdjKr>Af3n2-#dS8oM;`5FHe-t%=JPf;*;^wZ|Cjxzx
zE=fq<W;LWdTt(<0x_z9{{GGa!Z^URpBgDtqRQ&rJ?ZIgCkq_}1eF05@*HC1hod_O!
z*heSf+<olR>_=wC=&z6jZ)`Yh70-B#g+Je$TJ~24tWpi-+C6S3^kT^N_AG5k19lkw
zi(iaU+)bT+4QTQ6cduplr^n7U4^1MW`q;YHH}pr(kqJ>mBb2M*0jc9nC6>F1QIetU
zRF(HZFdeM{-$N%2IF3^e?V02w<YFwd!HO`Ehj{WpicU#KVR`9w=)~mYBRDxMI6SV?
zN1Q1ckg*P3=bzJFcvP6#1*XmATTlIPJm^8K>pjs{zMm%1&7X(H1z58bTjG)GGydlh
zyJcA8Yl#@;p@L%5>N}U4d^5haH$zfXcP^|#z$m!KQQmcL#hP-hz56IGXIYbQ8jR>y
z5%_eVnb5Fqt|+0o8eip`tpFGPYCl`35kTg*e)hFRBi{n(ZnAO^?IYv*M=8O%16xf7
zU`T%R&%<^J3lXK9P$fHJ(n<+0jvuJ#W7ZPPKkovGWkX9H&l(OulRrTe(93lAvnd*g
zdOhEM=`@m2&MVzXyEJUF%<$mLh%X%+5_>0;1gs?0J*$#4TA!6Gc2g22jsq_uo_LkP
zh<pE;P3o2iF6RA?&Ad|`%{3+;-OOoUEtC@Kmpj83urw8bMwpl<{7?)Q`ZS$@LP5*O
zk!PqF%OGkv2c=g`wUgoN9+1dtZ|`^?iJn<S^+a`4JL&kdqw)t8j-i8s(5H`_J0(YS
zAyX{y3<$5TG^?}u>vDy)gGuhu$~Hhe@eXeuJdy{Fv56w>ls`WLc79nQV<NVcIICew
zmA}SS$V_`y-4#!=)|X}bRLNgU)@*LAXF?xYqnXAP00!2_bYT!=`dyts_n7fag3v!Z
zxc{j=hH|?rG_4ra);{MdIsI=qnsEiR27!tK?QPUkn}}Z`)!&+&?X`<^G308v#WwU0
zhlFr3Ck$CQH?LA25T^<-p1u6KihkkAAh#d8;UJmm$Groih~5<YRU2vI-YZe2LHCSG
zpK0vvMeGR%ec+}(!eukHXY`ER7*S>o{sq#QfLX7Nikk)!7wu@QkQzU4<b6#Ndzh%=
zh6F_Oq{p3L9*4O-p;Y@4P$t5N(p`cRCR%m3M9TDd7*HRkbD&q1ON%g~^L1<rZub9u
zev6^Lj|D$vA9kvZfHo*XiNG7heeLvwyIJe{nQ{F*1Y^)KkyNq=j~1M&06%nilq|Y$
zNoPOT_52-iRMg+{+5UpZaJ}*3M}cIu!iXUF1Os|JGs4?&AzzUo-Q&j@C1c%8LvG=y
z)D1Z-(C_q~l@q+tn=RUQY?x2;`4M+VXPE-(#MyYq)t&Sl38zjJ^;GflNDkmV%Uyhk
zC<!EB)H=5z#RtXG6eBKzwYf^zAd8By4v3ZBqQi1nk-LdPdzBuejyI02mAnV0bDKI+
zT7}jPWO95_{!dg?5Uf^_l}QhRBE>h}ZtANq=_%+~P|gxr=#&n0b^`{w%=FuE5RRBg
z4m%#d)2D5M42TutldL#ABwAOwSB8rc5s7BeVMuRid9>%;99s^1Zy`4<gup&evKqLH
z(*tjY^>q|WouIL`J~XK4O(E=wG}{ceZ#|7!c<Ke;d%Vm@oC{d}(&wx<7183F$ZN|(
zjpw``G%4hRH17^Dtf0yW&gEbUK#hmr9&X91kg&mK;MUPSKCz#h;?H#*6&u`_aJN=u
zT2*}usaRSS`-R7<dpQ|Y<DdQ-^`3LpIFDjnDU~LJVthys9$2xA$3)GvwWH&AsXwsR
zp72_lO`sK6^r`Bl?~5EGF)&z~Gh7H}lJAHZbGq$@{&94nh}36F0cW?&d$?|b#4IbD
zBXZ$N8qenP#+-BY=fgBf04J2@OzHN7K)cL)CiQZGUI#QekD#$KhO4NPuy@NR0nf(O
zp1?q(YEH20{rXup1izI=KJW)NSWUu{5v!CDeJRcP(hQ#!xL6=z-B<WmUFdzF?~lWv
zn{|)=jaFtxA>FB>fZhU%woC0+77zkBuh2=`?zM=Pc-FBlRf7ZR=i$5ts2kHlOURxK
zZEL>qC4it}e-T)O12LYuq}EexG^hEM1@-!g#aiKtvobb$bz2%OwUF(eOE)T#d@kLZ
zS<tUxO-uMpR2(1Xqq&7_ZnaVVX<+b|aLl7q%VCdO-Uvn?O_Sb}0Yn0OC=7O1>V?X{
z$FM**)a_y=v~g6Ya2SUeQJk)9*_^_2HWn&Ak-{~Z;t<iicI_(FONF#jv*!+_jJ26E
zZ&0H!KS0$xIf?eV(8}I@GI)roL{r_}CO>datXob~K{36x3)fW*FM4@x4xCj;jq`^m
zJ0qiQEA(&e#c&YpzO?IJ@AEds&iuCfc&rGL!2I%{qh+9lJKx^<VI?wP&}fCXz(CTG
zKalXIC%dG2yb#(tj!z4%Rh~(0i<;9I>OfN;HRVz_-n%cUY68BBh@NZv43>_O%~44c
zH!+B_UzQt}4rF*M{d^e;@T}5J895~bl?A{lRF4wWQ3NaaeYq*fyT}0w&&_}yVRnhL
zP07UdnX46a8)d1QHr$;|ll*8pFG+*2(N|CNb6utO1+f*NNoYMr7o0enlc|)v^k)92
zK6zkbReDQM?!uQlNR*cN8Wpwg>4PQ@)uGE}+8LWmjQZv$0ngF~{_hJ!KqUn(wvJg@
zv**Y>)ZX=H9D*4V8ny1x^jODm&Qqz)w{B02!AxEA>4k6C67YDc`X1zNakU+f2l1zS
zy|Gb?++IhIu2~XkV(Gjdn9Ui)nI{v1c(+`>Tg9me`jLBC*d_<7AFFxGHomRPMn&O*
zM8d1$kKjx(RowhO2H6$jeC$ERGN~}bLj^G6Ym-I&WuPbn@<%nQ1Dir@#^eiL4+yyh
zOBlMOL|~j03(8a6@+@*~CltP`EX*->DJm{Cg_qg-<7X?p_-r-=w-!z%@l}!JHJI5i
zpK+6!?=SLW>J$<sa>{>t!%WWN=jNVKbz#9gbh3BRHh0Q_u<QIbh9Ny+dR}jSyfG&H
zZMR(n{mI&v2LWh|9ZtNy|F$}?n;)2`3N3n7M^~!@B_!6RUZZ0P&BJ1*cEIWL;@0RN
zfh65lH3y?QymlC6%PAA2NWjh<RaErucE8nB+k<!m*YkqSOU2Pa`*DoaBc)(?<?=fq
z0nK!Jn@39?nMl24gwptCS`eAjKymLCoQ4^_cPFdZ0%cFzGY1Q}rluX=r!-dR+(hfu
zc>CI^3Jx(QeWP!_tg9z&O9Gw#>1{H@AR`p1GX5{ts1x{t1RZm~vC+~@!)Xr0I{DJ4
z$;m*;9E|wLVao7}sc?d&XFBat8xI|cbsoeL)g|zjY#^Nr*cl=z#C+ppOdLiYl1QA7
zdCtE~l;aByuXmh>>}e6vx|rhIGnBk6{Avq*N<WP92<cevs&E8}0)>j4hmsZ}O?~2C
z$ilu-v=Bm&-kc6Fo}9ltFlm&FA~R`TxV5wk!yW=+B*#PD<%ipyP}GAwjMGR&YzcJ}
zs0r<#43LdR41_R*s)mO5q@6n$cjirAb@{UF-CO>8_+>eUF>5Wu*<dYIHkElyn&Y|3
zNxUDS$d(DAnwf28{)Hd*)ifLt)~Xh|{7zb}_eE%rAyXPQj;34HKOMQP28o3x0etP_
z7M)d5h+J&P%Xe;XYy@Iu>;s!LiH#7apuW5hQa_@j>8DneF+nmrF-#CG)Om4&*YE5P
z8O3^CVYR@%--CCwC+j#leof1CFIu-9TiQoWMoWgfmZT1=K-Wy!i|8LArrai4q{B+s
zA~5q4P9?}Mqi~CwO3urc#YCCrHiWDIsXh;zo`Wev800}j;Ga-!`$G;wvs|^aG2WjK
z7(W?kP@p@nG;~O8E8C=g<}f6>60`dHOZ)TvWi|%G<(^y=+|g{ND=eG}S)~U>NcP$D
z%FQK%(?1!U@1(}Nbg&JHot>4okZ3Jle4m@_j958maGP2sB0p}nCapX!l=&5W(ZFbJ
z0v3S>@>in$FUvXOEA;b>>$vF53)_78#}kS2whI~u`<>c~Wk*G<R$8N59Ffe1LJFBb
z%rn&)ArFN}NW4``|Ll}Cd37>kJKB?l*bOkZ%PWPC1&qKt5196LU{w#%LyAkNMPG=Y
zt11K-{GiADycS<%D9?VU(VV{MHa{&m2_JUD8KNrzyXV`BB=F{s?qN*e%NB)(&!^x6
zGm!KQgm_y?pGrq7w>x2b4H}oBTIlwNHbEQdT+De#jdZf&D0G&DRGy3bMa;|orJF%#
zy*P(#ed9B5-`6Mc01Adofr8K;Cub-R1=0R2M9IY+JFiAEqccnonkZ(Wq!6|6l1hD4
z*$ntsb=XsPBm)P{d}M}Uc?RF8BzoGNjz6!NHMBDfmV;<Y{y*D2!mdzl$15>yY^oF7
zgeSxf-AyU_<PWvI=Iz-IX(|~85GkSe*qQQ3gygRIN$1c0Q-NRje}{{`@XyivHJG{z
z`QaGkLLO1js%h&P<63Wr3&oPK1uRwQD>h*<XZnZrg$;9d^CXGbi|$u%_0Rh<ah__y
zBGyu90UEvvt2t9d1ixf862S3vWNY0<+r9(2dv)W2S3RO8RJGQ<0%<MD!IYgj!Y_Qq
zL1f1%L<Gpp*64zvFZ0s*Z+as5-<r^s6|^esHI~Uhz~rCnb$A+96i1=t{}}&64;hXv
z`?$@ItfxSm9MX90H40uRoBja&W1R7de)KJMVFlNR<3Z^HdHroSkV##2QjSjdZ)QDS
z&@FvFz|^7Tg~d0v$JhY?!5MUkno39*n1jdc3=k&z0iQ6+bbSyt#uVPT1o;k!JWR$`
zDJyP_F}<5)8C4N{Wyi3wp!VZtm)D|{Y6t#L$=VZ9pw6Q}S2)-sFX-KNN<=7CKN}mQ
z{y5UreyzsjgQc)qxf)J!^o5(yKpyBw--;so-L1NQ8W|`r(H_h1yki%9VL~isWbh*7
z^^G{8TqmA{iS&4GU!0bx(9J0R3Fzvnhy6l<Dn+(??+uUKV0EnP*2@TqO-=c9wnBy+
zm}k-`-^L66!2#Pu@_0ZCp*PSxrGXSE5-tdM^cD>OJUuOjUdA1W{t~=#-6#m}0kJ)t
zZX{MMmEz6d>6GU0qd1h&ZX2AtD+Fy{U;2Doi=ir;-Si9Xp)_~RCXR@VamlVr<L$qF
zGdjKidtA!d!q1F6&R>`wQQE^(VDZg@{8e`hZnRz;OR1coc0dO+u^Qv~h5vCT3p5%h
z;E#yxnj`RqWJ0Su=wz4)TXNCrUrvK#cQQoV$cQYDRk6xb9UQPk$f2|q{N#V*q<wvv
zVS!#~3VQiB66U$)+h`sh8%>7_ULFzmC1U+}TKUC*M4#LCPZahC#@lRR>b2Fx@ABOJ
zrd)YR4nvMK$a0i;$qF2=uf!5wi{fyTjHXkiRbhcwu1=69lQZ)u()&o5iOIKfm)*C7
zjJ>?{_#c~rm$@qOc(>-?Vip#xqhkjCCC4@)jrZ1tm|Go>a;;VWI-DpV<@o5g^|3tt
z4{Hxy&o;vKobzY_fW9VK{Q;0qOAnf@V#f|!kyFIBw&IwSJ71kSV0zJ3DJCGwDC(fp
z?%Q%_*QuMbp$z5{c5$12TY$^8`kMy_ST)4AUX*0eVV~V);q=cFnQR>Qi54qijQi&Q
zym&tYX#Q$kn@-3V_l`9a*@>NJrLc>Vet5KAEtw#?k>~X;$gHx#-knJ$_R+r#r?)ef
z8BUgHYj0-?jk2nlKSO4C<xhGyG*`2>gya7PEDceO7_E}M-NjoE7*DwZkLMfJh7}cY
zu)`M$;}kq;a_RamEfV?fTB**}O~}ALFqM0NwQ{zV<%&(cv+wK>Z!2Dwoacq1dRFL7
z>=qf0Mszg@;A5b+gfDR}pXR&E$RW24+{aL6ek{S#S_^%{TmoW#?lo^o(`G}o>h^0o
z^}8`P(Z4-t2*DROO0Q$^bpRM!5{~$~FI(3N%P!R}f9F?McEq(G4u_2XWnV5$3K=Bv
zY%4*Ds{AlJekdnt=_XC2i{AN5(f}mZCRtAsF{l0$JcXYIULh{$WvJ<Gbpy8!uHy<4
z_&OAu#e?$_8~D8?D<!?Px!dKTFRvqYND=kkd}ytEesh5DAOcXjGGjoh^~MRfd6l4W
zt|`{m?BO%8!ETl}H(RrY!bDm}D687<4HB5~?7E2JT*7i3yje;jYdCqq;{dKnLDSF#
z2BD{HK-Udd#eN~&;53cOGbLQI2y+1XU{lTXZ=MaNI~*fnx14Z`Qv1eSjI9O>S0y%T
zykD<UZYlFR7hCCsmwGPNwTLP4)YVqM9}Gv@b*V@MDLt~d<t=vVnDZf%y@H?#7QH(!
z6h<5LmSQn|(f}GuVkRB>Z>UguGq#sSN6SZrz1A2kz}&qT<9F;iAKe$2*|E8+4rKKM
z{z@s5SFe5uPL(mdf-!0=y<J=&3HG;wS60oQn9c-Ftu(THv2qF;UHXwL(#VbB%!^qJ
zndch~9i_{Ct=^Gv(vc5k5JgGqyGM=h#Vlp%uNymtFQyu#?9@yvrfiOeICoPi(Paw8
zdMaib2Ez_?aTE1^k2^O;nh^fMeyPwon;nXNPm#?N1~klP@exBR$BosQYrO}E<rO&g
z258T$HWi~}s4qr$W)W2ev9ty0f#W3@X(xkSdhOchvr|F4qLLgkgjY5j-Y$INa(gNk
z7l%i6Ly`T2<Vyc%@9qdr&@b6+*H9#c^m_#3XN@d4f&ZVMs;Td{et5#B7Ssx8>8^}f
z#$rnAW~lx*XvAuBG|nG$T1|cx{*>z|I)^&^A#F0I8GjN|OFi=_m?0v%`qwjkwywoL
z3y>@j6alf5cc?qap7$p<MVcjcy%TAfNLkMta9+YlPy_OPO?V2E-j+Xn4uZTZSicNZ
z6_kb9=UrD_>9i)$$8PN*n<cb!4qyF==Y;#3d!N0Pt3R<qNhqXaWFR{xwABHV1$S$e
z18IO`kV1z}^Ep#9B{~s|5ED8}e@Q!Gb4<*}eGTJ19lpIqY{La1X9Ns|Aq+bPXY6B@
z!<%)GOyw2uznQMm3zSq0Z9MVCA*w2c9<UMo3G{jeK6F!xVP)Ru%mG<N04LtH*shB+
z>iyWde?qSL+_sxJyHjOFh?v?4{n@Wig4LsT$NU+TY{<I(e_6p&_}=WK`}<bDOW%=?
zv|n39Yc>fpBl8v293RWB<78{_LK=0(bcu}zWvQlYIt!e2IUf154y*fwVDVZi@5+O8
zSuO0Pc%B_sA}{)`Fab_Rt7ech;-?XadI6mI?`V$Hvoi1dZ;zS#T!iN8ss08X!>6?9
zx4~Woc;AC02{pKU;fe6fhl%rxfcl(L5D61<OLRokd(c&Mq;X%St*Fn=ilPQHt~zaT
zSl)0{(UQY|Eg>|qZ|w(Hp)U<ST54`8vCadOg3tGtl^5nA<_5ya<;1$~LdP0}1CNFQ
zkv%p&#)?`Bc?N8J>|P4ps0S_rG<W5~MAepZ<Jj5kow#M3RS5^S;H52g?2&CnP?d2n
zNl4qjgNID)8C3!n=b=lEnxdo{Z>E*MEtpV;exX6QZ(YNz3Uu6<>ZAFo-Xu&k%{ZO-
zg_Vq{At^=;?f*7t<9P4BCPLy}PR<?|3!YCN2DLq^0vl{4^k|4)Twa9bWi@vITY(Q_
zPsq+-a(*jU<L;bB^^DX!hFL^=I7MGOC;n5G!Dpdw%p2E>V+MyD+rMQK*MbHcGyQtW
zkGU;oK*u5Q#ymWB=QksCIYGlyyf`e=92*!7Aj8MZ?>^RwS?`#DjVZb=UJq^@zET5E
zk=g6=f{*)Q5oJMNCX=eAO;5LZij~#}4iSf`2#%?$qTD_;Tuu<2($wshnXAOt%$vDq
z=0zfMRA$F>>s3^f-d-BPuhED>;a`W-F}#;ls>w#&v=~`8EgiVz#k7Gw_!?1|gtsfy
zS>}1xGYJY!oOt#pdH)Z-K93W6y<rDFT4$0vrdRHpbFv{S!~oJMAi#uhyLNDw;eoJS
z=Mnj&FCkg<SSj(>htYazz%&4kdw{XJh$avHdL-vxi(_&?nGHMlJjaZPL>;1yQ||xM
zKCRh^w-PyeD%K^RK>kb>89N+*nhCK_Na2eq)_BkXyzQ`=4QR)<K)cIZWaSn06z==M
zIt(OK%GO~Dk;l5@2oP{v0n~Wnh$fPEoLTEx;L74^`*AS_R(3FnjOr)UYD}2Mafmpl
z0W;|dvw<KDI&}pa+*O&S;8u)DJ_ZOTL}rm=@sT7-T%1====WF-l|~$LRmWESWnsMt
zv6?-lUTWg&P)1BBH3lqphUV@G$%X7-x>Y&Ga0bk+%Lc5X2-Yl+F#j3#{<$(c^;Ee%
ztT~Qm^rOrirr)N)qmE#%TqO>2K&_WGIbdgBgL+9`{b&&nueH8?yjQabXr?<-b`A5g
z1`!`S(qI~5ky8FY6bs-fMTt+OS0~V|3sSQ7m?7ch)qoTki?37<($_wBJ9!RHa;!(V
zT>t7yUS)a}AZQs|SV#guSD)9c^P&KFH*WX%J%qc2j6Q&6g=2@-l7&|Jh@>qjgBL0*
z#!#3&*}k2%T+LZFP6ZlnWSF#fei)f7PtrzZuwEl=leC`cdTF-qhf^!LcN0j4y2)_f
zfntdTAu+qcn>1QDCWP|&uQEexTsgTw*Os=pcZwd9%em7L{X#!&-+3STw1m=@kD8{8
zO1cE}<Usm$iJ4v57D5Z;LxN&b_mKnxVyRsxO4?iu0TlW|VEh~L(|u}R;?L$&$w{J(
zuI#feM^RS91I}x4a!h>yjRw>=IUy-5&69~RT0fZSlNxB7M&5(D>wECx9=+P%sFpdQ
z<&1y9tcR0Mz(3zcw!gKLB9e3!<-mo8@i$uE;lyES7*<hBt~?jfSFt&mLs6_~wGyFP
zunk^y3Qhpj0k0xs{8?g*fysCiZRN{z!RHm*&fFj4Kb>-#cE!z;VHGdcbnDMouAVxW
znfeSLZ(RdZ7q<%LQrN6f&Co^E9wYDU&k11diL$T@eAu6Rcw>%6rNcX!{pd^-C|bM%
zkUR{`Tn2FD9+~v%Rj&&y&7`3hH2=YUQ5{ShMgbK5wP{&A!Dp+dj{>1hFa~jmuiwBi
zoe+E51}$uP_^*o&0fxu*Fgp^+#igs0&-pW|SPf6P$A24;#koT99$CfnR#IS!#aNzD
zR#wGUNlmDr(I2?Na;6qv>6i*T(IBCGLe?{-_wJC0x3&#I471^QLb*oG4ZQNOoCa8D
z^AZm|VZ=gQd4oJPRCNb;oF%mooN$H6uJN&tXU#^(MJm*~6&;7=>SPFRzI61xj6!WN
z&0wwhU=oRRamU&DpQ4sPz(FOi=IPS1Vx_tI`z)@zk5ZLD#db>d+9P6*LxT1UVV6e(
zEX#LmfSG6{Q=Iy&(Hw0sX*lQQ<5@-<ioSW;43Bj-R^sf9&g5Htf#R}=jhQkZ>hMlb
zhz!KdwP0Gv`6d@8%aJ!aAyBa`fGIP3A=+!dVV6#Y6LVjhBn<s@k-?40tsb7bgUpzD
zPAh^#C^m_gt`^UV!)gnzn}S!22CSHfX(;yLI%BK0&W+h0O_cFMWm+U18meZ(-h)C2
z&Qk;ko@-*pyzMic67h63cI2zqLL>#|DjL8{MHb5nt?;B0j4EmNr-Njl;gmeFsr=_h
zM<a+GYCO%ZN2Luk0Ga<+S<LAX+%U9H0_}@F+3wd<x|3fDB${n0^<EKs_$irD@Sh_`
zrVMysrCD?AU_A7|JHNpp_GfM!<!Yi3JI)-VDt{XoAZkn_RO`vK4in}jUfgH8@EGS#
zcEVE1hSZe7ty|~T<6W{BULQsd4ICUB${F--V43Z#nXUp4o<Q6AH}oWc8yEjdFE|GU
za}Q;NCM6P2sbpkd>UskM#R#nhgmH(TIn&jfP5n{T-F6o2tgfwTu$H9L5ARblUlFMK
z(D$Pj%=>7w0fw<KCcp#l;uqjPxP!KNOHslM_lo$JRF_pb`JFfLYsbG6V9kq+v<T-Y
zrD<DweKg-)5=CYHW`0Yl>BE}^Cg%Hy2^L+LRhvKWnBxwb+-lIxGrvp=DdI5LJKF6r
z=G0)$-Rc~Y-_iWGU(%O<i0Sq9!ese{{?yzYN^5q{m^Yj}g1%J983Qfl!Kg`uMBlzq
z8k)SkDI-@r4c$ggVUD(3h9sCRysja{3*&Z_+WF>v9_7qp%aZ2qdpa1@Z76fz>~x!c
z>T7UqC6~%(yXBI_ylL$V<F3EaVV!q5BPw#Snxvk!N>iw|pjS7vxP2X`)wTqWX-1}P
z0Tir=8v-?A?Gnl&&Omc)Mio(ftg{9`6*s0JmVp|C;oj4KUVir7{m>>aeDB|CP?V{M
zhe4!|Rut$~B{j>OVj>Y{qr-)vnsR|M%{?+;)gtrzYWVZK^X0BdOyPx$4SDGI>8^~x
zrOJm137)6k*`2QIpJ&W&ZW2$cdosRk>_i??r{>Jxt_`K<`PnkH^Fk7?1U3FoYwO6D
zfRl|4RFrP_v^DkLgjt4NZK(oir;4+x;#SX3FkAEq<Tx3P^+GFbwbm6E0Jc;0^nFCA
zWEboTp_dAs*JI#zY~7CnQ{&+zxlVUUqjC>Sb&o7f@i?*Lgyu6K11wv8qRjYp?}ii)
zo^$!$tR+-CSq6{PZy4L7&ObroR{tguQnI7xQkDxkPIUi4rfKJ~#q_<Y?<Puz8-<+N
z1KG2JaN??qBHa6(-2zHGeAU6mAY^_H>S3%g<9%7Ei(Mcr6MM#MY>V89)jV1epxMS^
zBL7tt?_3+m+URvq1qU|2xh}8Xi{V7WL`c0Mf{L{+GlxVTgyn2ZGDb_Kjg`;~y+{Ti
z<)z!Nkj1>XkTNZG`ng{dS#SM(ccQV)>GSyxP3q#B$iyE`xO8<vh8K1-bB+PVCoNKM
zz}+n6fAhACxtA*+N|99Yj4GOBssSX<=u)Kh%>*vnr|_Qs{C^7hZGA;p1Jekiu}HWK
zMX;5oHUu#9@0}duC})bpkC7M+;~42d>#sDCJ)HlL4z7QKxiN=^;IPn`qYNjneRW`M
z9rK_zsq4bgCVu~gpXpa4gEAR|`ksDUFG_+l#FyZ+MPUHBz05CqWntiXP^@ZepZy9t
z(?PqsC2arU6yCNksE|vgIi~?Cq#Fi6MrhMs7>3H0VL<IEwz9swL(3ZAFZat)Ia4&2
zx<nj6KnmHbEg>tHZ=CwgVePaRGcyjRCAEScXz!V56sEC$gdY~Z6dDjZ4Dq;4d1%t}
z|I*)dSulW{EAHDWf?NJ~LAzrH4Z$F>DOvUnx#S!)%F-d+=1F{Mw!wNyswWw?o<2{K
zWQ*wRiG9VG*r_@Eu^^Ye1V_PH)<Zmwm6XMKh?45K^=P1`0zcf*KxvsDxLKq~F}9Gj
zmLkUf*z6WKRx&*YM9fvs*{a25n(Qja5{6+vKgpK9s6TIqQ)Ty!n@0+{JbMA%W9IPb
zI%imH(WQNl<%yvT-7nnfAW%z5)=?OlBQtB%C68LNjJmaj%N;wY46{pdCeF3V1s33j
z-N+?^F1i~dm1&g^=eqexX&9f=Z-1?C{%@~iDt+dfvJd<*le<YFMQMmFe-q8E%Hkx$
z<EqkhiU)h1b}BZ%%$Dhdwfc!Ou-0Apg&r?=^~v)oBM%zlRFszQgd&mIAzhP!pjMi!
zGo!}O4&+nVOV#cD+;<DxjrjXpXC3P~J~MV6r$Mh3RA#3}!)-rPQcB!)Zg`~|_#KY&
z7c7rOQ<!NJK`uvC<q>ez068a+HGcxXZu;0Vo<mlcxT%iPKCqODmu`7mhUVd%tEn)<
zswD>@Ci><OJv^V8?-I^Dp^E59-}%m6?!?rsjw9w&k{ry$k=Oq(kfH2J=0YW$b_wRo
zu=05p<FbZbD4nrF4c>`APob899Jc%FjsDPmza4GE$-v!@N?$n7g0|Shtd>}bImbJ!
zJrab;Sd&Hi?q!|o^PdXH;0jIy1Y8e?E%D1QQF0o%x*=OS*LxK|<Xc~T++xln2_|t%
z-*iQjjl$#-sy%Qhxj!!6DQbYCsZ#?55dVW>>l9N%o~yNCicA-|tr*FB_WMZj8aCpP
zE8uf45E*HUnP#hvWyt#pQI@#_NrwWIyne!-ptP1?CI{z+hzrmiuEsZANf^h^UVeR?
zsqukYhx#N`?2(%_9cM@mJ<@OwZZM?72(%FYOll^kyAOyDUW5*IlW4&m6Cor|Jijq@
zJkkGNG$?McPHgRG7CH0(4R^;#j!fqZda0UbU-;)5((y>aBf=}XY`Ysdrme%}NC)iz
z+^&a+s28Vvx7XpZSLPMZcG(51*nL_*HK#!iSiYvo$PVF?yg@aRow4Ur*_a3VD2fhF
zf?lK^siJguV}HHX4FE+~MoH!>B__KmGoa{Jaku`BxLWf09;cGOi&NKvK4K?)jST?x
zJ<}QXY5=;FQY@$MkdHDZJoy4~qJ~@O90lJSRswKVn#-3_z%2edBl@S|sJ=UlC_A(>
z)~+2M`Z~1W1|x2dz~e0-w$O$2U%3rQ1KX#aTz2026B(B~a-vJccRttc_#P0?j7Gh+
zH7v)Xczvp`Okf#tG0tA)rLZY7dq^ajkR5M9dL<*+dS<VY`oP}_1CE=_+UPXDo?Wds
z+=G{bKRWry`(1%`EAXn+3hh;os>R&p07PZl>T&7#DeM)}Z$+joLw<3MS1?XNZY0_&
zV%BcKn<}~8{dmGikfI@)fOn(;T-Iz`%IOJ6ztJ@mSfPpVNY*Rgm==h78rv+|@m+sB
z{OU=2Be`(^{(K!#_c|QoYl8O*O~{a5?^TlgN5gshp2$jjd9693E_ij(Uavsjx+yC1
z`1NMMk`bD<t|YH0zzO}Jzlez7GbN4mY7Y%QxdK$wTn@WVCI$QU2#m#N#b&0yY^<I_
z<8PcdcuCxeoGA&sCcVuGgQT3^f>hOmD_eu`o7Vg`+v(WQE{t(ZgPCUQF>PKu=NoSU
z2??pBCI^<Ds&Mhs1zsh)?P-}vz0y9T%;9UAN{See912d5ME*}6DFt$3FUPFY^T)2|
zh^L;J(iyYKDECV)Mvc-Z;5?OMeA1-gtEoaqeKtkzzikMNE3?Oe?}>j|+IQP$t0A$C
z2YEc@3Cb$epZWO%L`OiyN{B#ryB~Y5g)RBvi;e4w@8*|u;i&nBZ^Wry#X7&Na@F8R
zLay<dyZIV0RRu4?J&eU||Hy=%bm04V-!ngXnJ_H{&P!Z)uu6)Eo`yh%+&|xS;p=c0
zT(0qouYgN6sUg#`1k(1px4N)tkg9swYSL-UO`}#d4<8~0KE(MkD>Q84BM4g4`MNvm
zQ&S{AFOG{rKN>D&MHaT2f(CYfmDFlm#sg}G%%vF4$t>)5<RgUUlr(WM2}v|;K9?>J
zL$#tm*edxSDB>wzet*0JIXc>fmM_D9cTv1)5KhA>r?7%uARKq#QTFbOb@;wd5fSfI
zT$USUX>j!9%8{yS;B6=syJ~(bWMq^}Coy6;3sE`9yVBLy@1n>3nhB>);X<fXO&PJU
z-Ezsv!@6!Qc<E<r&AjiN-COFJ2;LeaDvXI(Rv0^9Xcc>cOcWHKUv}Ar4%lH#2a08(
z@FLyX95_IGZ^?}ZeoE!2sZ3qEP>5)>s#ML-M2%LxqaOIFw+jDqzQ%8U9RS;*)526P
zP6|us8ClISHK)R3)X$Z-qwFs6rZ$6956D--Igj0_xrOZe4-{g?6$bpZ#hh+m1YFt+
z%H-wAZG$YZGbG=}?Gy+ahOW~<<#>-YY_TgF5EZBw#U(g8-f_xad%hI)r<4#CEA8|X
zTW5TZUCv+Kc2#7!n>Ph-?*;#;`@H`wz}U`XM9DlG9N{#l0oF{bf8+N#h4~173AgS-
zmIGC=_uYktPnr>-S>ib5NWiit%k1kgLq7q@12+6KFN+LW&>7BcWXXdoh^TG7BT(!a
z3{GKk>q!~&GGSZLjuFu=r(JzTRd44m0C@ck=t>6SPmd(Zb5JdzP;qZfFKYn380@zZ
z+^E$vnX%9<VntZqqD4xORfaEMs`|C5pdV{;JH14j+9GC~MnTC+KN|zSe@AJF#d%u1
zX<GMgMvF&}8iwRhJus~6iq=x&waaGO_YlPJ!BjYk*2<&&ra<x<?}_k0xJy@m#ar4C
z)MG<NBrC&%_C6LpW3}{NFE2WyH<S?KQjG}y6k>|iB>#V_E&rgel^f8VCJEWMPUOYj
zP}@9(6lm4BN#0@`C8>CLL*^0Sdc{mF&9;WGoI3#h-T$zBy`Xm~l=`9<k)?(&enVcs
zRdqBjM1xu<ULue6sO`(+q$V?TEfJhiZ=;AiX_AJ2SG5X(5b<Ewx~?JPNExRYORj_t
zQ~P?kUH{?pJkLuys6|T1iO|Q~zDCq)(?HKXs*3XyTz5F(EKZY$N;m8okS+PPiiFvf
z|FakmA2!jFjEwFuL5Ki)=DDhWD{IvUFxkUzbzs0_NlHCxmep$+^!?D>dN?i7N6R0e
zD6ulK8%dAL#Y<bYKP~ab_?@p$R|0@=(QOlu^=-94Pot8;f7?eo4d!6dJt#I%XtY<6
ziezGLtc75vq6TUH5{lfnP%u@`UZzlY`yCm8?0uxxP6?Bn{xH-fDklRWN=X}|KG#aY
zsd~-yjy)A7aV`5;y&`n&IpyCBXGD_EEgtz=wGjY7iHc2!px4}E?iFPNY5G@hIqmMN
z5E_}FdaJ4nDiH4V=+Z$e98^}^2-abfK-JNx{~Q9|m7IJ&#!RFm72?p&M$xXcPZ`)?
z%Bc!~A{5(l)!9W9y3hW?+auUpAtI1w6|=!vF0yqVT=V#%O@vOJI>%I}e;tQMdewr-
zzkuTuvOs72!GIk|#`W?6#fUQmj!pxx2Sl9;HDz_3d+gEg+3UYIx~7vLK|eUIzW1`8
z%L3=3)O`H1Aa9U8otX7|5y4gGan6bfgW9`>!2fjyRV*xr4~HwU-;~fqI6P<+QW#Qm
zVZo$mnz!h$0sv{`MR8qa;7<(+b<#RGZ=E+(tS?8lu{U)6X4-78((R5HFg7mqG)YwF
znp{^`<=z0Ug}bQKltG>I$k)1qG&xqW=N>ufH-f?wrq2Ju1cD36{yA^zOtBDonQsbr
z6OQa6RN8kO7Cb^~RU<o%rhU-13G!h9(x3(%l#<DRpk8TtA;*cfw@s0mM73FXJf6{9
P`)nvX1_(x!X`#6{?0~YV

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v
new file mode 100644
index 0000000000000000000000000000000000000000..108ef111d2ce1d0c80ffc7299fb397fdef95c750
GIT binary patch
literal 3824
zcmV<M4iE8*6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC5pxDS<YIDsTYy|bT
z8hj=c4P&_(3f0Zt>IAk*oVQUa3JCGmEy%at!`f+-iAmYy5T647cbHRvx^MzhWj@I<
zf{%^=0NA$i%QeWf|0YhQzAF&LE7CHXcX-?Nb+O>4(g<qIl|zIhdjD-42mphWQ|S%_
zo|0J11aS5xIsR%}#GiDMLncOO_Je|1xnT{&GABb>h-<xnu-G{wa5I0uo!j2?H<?4k
zr`$M;RHWN4`LsdaJtxvyt|J!$FK#r?Ia(LqJSRQz6*q(`eGtB*g|R&ck7KY77`Tjq
zDg$L?ZOepz%(NfZ_!=QH<uA9{WqicZ1H2(-Cg{3h%-SbW9f6aN2oDr5$an0<ZO8r6
zXrwO@jmi38hBr5&j$K1Ai?^=FZ4^l>hfF{a)uYEHR2Uf2i6XpE8#n%|>DJ};oB_N!
z{ova@d&}~`<3V`WQgRep##&YFuDjC?^0VtA0y8R}IZ5zya8ctp9yu!fxLTZk_?#0#
z$#r|Yb4CRV=x)8}Hq&H-KAL_IsQe+A_#P1@+~EG)6P4EJm6v1x`H$*tJEZpskrcG8
zf?EBW8IFfP)%InAp(nmg?<CwM563gbrx}~UJ&hhK0PmCV{Ul=&^yf3>kdl#va0Y{;
z^Jcmwo=HFohBBp5Uz?r9ro9aLC7Ouu6VvU|Fc*bOOU&I`3t$19$%2N9@J_BmRtGd*
zR!ZV^Mo`JZ?afyUh{zVT5Xz7rDuo|U*Vvu7ZN7<#-I!V@$I8Vy+;TP^evoF5+Tv~e
zj;V=}0B7o$hbxV(AV>*pEQ{@)_F48wvn^a-M*9@n!o_(bgE=Uxc}1oc#9~`0+#Bhu
z%WZvqa@UAbL;+cv7*5d`1RuJ2m=t58>A#kGpA(d(+A9uV@-Y!bcQq@Qnwr@eaqlYT
zN{NcbD6_5>GgGChNN$)0=Pz+w_^1EDs;5qxzw-wF|8L%gE%$&GTZ3A7z`h7~XGp^w
zcJo`0ZSqpC@T;h~)FB=AIb?AO@7+Pf>F0f0=_MyJ>f7+Zype*~;LpC!VnkPxW~CMC
zCL4nwh}``NEQ16x0f6`tD7KJ;6ey=D5`w@a5YxirQ+%@!r;$!G=h-1wTj2g@ozjzA
zj_(pW;eR5YRv?5zbgyhOGV+C`6y1+YzDC$Aw=~QIR}Aee)Fu9|4h>O_f}jVQ^M}O8
ziNhG*9pPYeZSwbNv|p(k1)?HOLYla<biJpTb{+f!QULff;*<ELbE5slP-2e@)TUm!
zyZi@C2Y(-f8+~|AbNFO!Wm(3R=?URHR2F4=s1KS=-0Uc7<6U84Aa*Ai>(?kK|0b#{
zy&@EYvJCt$T!mda9ej24<^~^BFq8>pGzo>&f@K2+XJ~A?j>VC27B3PiCQ3b?9f41v
z*m{1Gy<Aa&IC1eD2H=h90MMr{J*&-A+sKg{SUHgdQ(tB^J1-Nk+d!`H-{ew>sX+nm
z!FiN+&qsa8h1j~-+)&(gN2D7ph40(iuFZ)ZG_`ot{LXx)5`rlPRG_#Nx_ZK-D{uMX
zO_0)8CAT#XrY`X^99C$UV!ihyC~y~Y%Hh&KG~gMF>=KNtwc70{Rc*h+V#G`Kpc}Ix
z%lQyCf@`dxh!2gn%9dD0C+*_l)sX)_ePmi&$&YvDXx7qNSLVtwymznRCq}$k^uha@
zfME_{*o9(LhgHKegJlwH_zs+FF`fE7v_(>2V<x@lDH80ht~yLND$bSVLqI{4TR2ms
zCm+rAn;5>mc)Zrc^7>(gp9_xd3qg)Gjjo5Zj5?{v4p(!>XxNj5iY%qCZqnt2WoI9h
z6sTOs#MZ#B)GsVgiDRQ~xE|(M4**={dD2QN1(XNzl=Rb+Fhgl87E-k`L(|B4R*b_3
zxKtY>Wsp~CZ>8IN&Ab3m(b#p1$<=a4p_J-(R7CYc7uxtC!#DU+owx9G+LB55<^sJ~
z>Dq*rc5F*1*xEq^-62f9oVQ~0Pc(WYOU#L^8E}zIM+~^X0M&K2<YCOR-!y)uBd)mC
zVxZ^jodyluCNSV`E*5x&--dyx)4k!yAv-wfXG;dT_762vHHQT7vF|CYCL-O2_eeFg
z`l<DXGL(`$oc17+IS?jglCx-$L#c#tJrorLO%&T(Cwk(0U!Ix{DnSC~P+$eEJr!dg
zPuy7N-{{aPJ|2X~Ne5m5-^Q-V&L$^Ff^>^%(X%Ss%c65NrP>N%cmO3;0W%hjA6a}9
zh-$5o_{5Byc2aeowOU?#UvqTJc#C(=J`x){JyMRG6-ag%o99!NZm(+govw>XYS_i2
zq|0zV9bE?LE}*HE7$_idNoEqeQkZ7q8F3bKttntj_)REK$8Eky&jFA_`~!1@76XYz
zznfh$3=t@tCX6qM?q!-J-1u9C=9nczxW~zL&UWU-E<GgerND3k?AGEO{-&t&K*MvZ
zr(U*5wOFMQq`{NCml-<<9j6}Vb+GOQiW=PtZW)Zcu7M-OFqewf(N_fzj;QqjQE*q`
zE&H=6OVz?i8$y}w=<T$|T|a8{xtKX__V@yYb%Ts@z<4M(85J1{oFAiT)Yx>NApJUj
zb0L@w@AC1?H@jRX)QjZ3#n!^Tmnq8P>i0S>2mc|1V=t`?xgbke5!=w})02aPZcOD@
zf-AbW+K4unNC1nD+m%X{P7AxBt65|9hKt4<RnVV7U-IercyP(2R1;UO!2}JPf`wE#
zLqf$*-W*#F#S~@f>#0G=CbRe7>f@p|_A2%ph(`_o6HqudGq?P3j=^``mQ7di@BETW
z|6Wq3v`xIRmj|gQO{iibe>@2Hd{*4r<1;5xWYLWa{c&>lvHl+26!v&iVNYdrK!z_!
zEi>e}5;?qwxEw|a=;g*ZLly}X{FV+{PX5F~9+4dl+Y`LAPSvZ9J$%3HiS%K4Y0w-(
zK^#3lBhFz$a(`a4X+Nd57D<wtYvn{rp6@*YQa|t54*(;PY+f#*pCn<yjle7kYJy>|
zh$yR)Tfb7>UcmAj+gbbwL&GIat5cZ=bkX}&tzW+xn#M~g5CBp=5@J9?-j^Pz(WMoD
z#?Vn_;y|4eEI@U7jfkvXNB8Go*Avoco?(eAZ2M^M&^yTR`z*WJxZKHwF?Z+R0r<}W
z1^+XZP3A4C=xw<ICRvqrl?AB|p;e(x;4Oy7RC7o;;8Au}Y?_NKGh<Nqqg6Wdp-Iby
z{#dzKe0oM<u*&pUH_x1w&c<LUT1q03jOGmfn{9QayOK#AVpTyXh7E?XhJ;un%HK~D
zdKrqRwP^e~hLfe{i9Z-i;<%b{eXV?L+2-yaxC1eZf%z;t7@DfM;?^~}jzl%?%|1je
zW#xU7pmmb1@^?b!%vLsn3FIkes)*u;k0r3UQq36cu#SS*x6^(K1*j$|VLA^=5oF|I
z5>u5}hH6i@Xubc_MrDIdmueG!?MzdHC~#tXf8_Q4`<m1_7C*x`*ApvO$`>P|L0#?9
mLkX~K`^F=if?(d!f=%Cwe|vl)Xa9)NVr`P{L`rg+!_!)vSzB8G

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..75d5a7149b16145bb39391d60067d20385832152
GIT binary patch
literal 2520
zcmV;}2`Bc86Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtlR#(h?HO4CS!nnij46BWyR8Eb3p
zzS;v4otk>u>wZR>o6rPN#$wNErLsEfBs0i-KZp^G+3=CEko!>^tM}&&pTld?tYXQ5
z$mRy`m`JD{J9aO^N+u<cpDh#QoLgYq5mu(V`<5xMVDGCqWb{|j3C-FwBrb|@IKsp7
z81PS>f8#r&_EW>$@MsH~Ktn3n@SIT}Fv;VA9ps!5R+lytqywP^4jDq~;d(Cyt5ZLj
zV-I4!c1bQ}W|4ZL5H<6rPC0Q5)L&1*T8&|k)JGW-<TVzRqQ$ZdpK8oYiZ1=rgLK?C
zrhyCc<&j|Y*d*(N8w5Qi)xg(pVsT~E-^6pDvgRr@Kj*Q^E5_JQPq9Xk<l(g6rGgI#
zid}r?#l917osm!}NE({PY6gc9Mennfe7%wIseOa~u}$Zmkw4i~lF<It=X_&^C|?f1
zkKc6-1b9HGuU4Cv5gjP&dIA&Z#SR^vWFn^@x*S#S3L?cb$=YjPLY2T2k#Au&gc8a{
zs9g)ETaS%Zfz^&)OI$5*v>Wl2)pt7_F%ETC0bjh2Z@_4rYO9AD;xe;|-?RyKTi6kK
z@*pj7{nW<8>n?CmN^O}W`hgSOpFgDFD%#W!72%FG_af`%N6dbfsGnM{3X{PHp{C22
z#!ETZaremR=+7zhlhcGgr@~UD>~O#~<IIpN$S-cVA0zMac#rtJ(mS_U@>(fJhV(Jh
z&W02-%J4X#FfQq@C|#Y<{BpdhNxp{=+AHuKtwMSDc&q~ga^LNEg|`MMsz>}q6W6q)
zQF;nva#5Yb<P5g}20O2sH5lqfKB*NeGdgZgUN!>iMw3z$_@3lMM(hdj#VC}2C~*M~
zLUex3z*7ypL&OiG7UNtzd&|NSwiAtTAjuReQg%O21?!0;!CzyfiBg#s=TL>H<L@Vm
z9PWNRlcKb*wmMcU9HPJIifS022R{wdzY;so3x7!vUEtdLZ-si{#bzS7&GIrfY`X0v
zuuGQ{$5(Yji~@!E+HhPO>>L>ZIW@L7s)uy0PNq0<vzs^FXK~x9GGb~QvHsPX(9^s+
zKfJ!vO<y@AwMH-Z02CXjKl`{y7k4SJW5g9n6F%uP$5&l}sDKx}3sBi>4n8;`5v{>+
zV{|c<oYpSp77c0tSQ*Z`W`F}RQ8Kk2{87>#+@8k@NVjA8zuvKvtG<*b4I5Ad*nWa;
zHvH$9FMP1W&?jS21A6Kr;GKU*<eD2bq_9Wytlv=vtm-DQDH!tv%`>}hb^vyEW51++
zjndL><5v#=T5s9y5gLN*Am$2TyWqFDyvwHa;&ie15Vfmu=NI07iWPBtI|os`VfgBy
zrize&hj&85J)N?hQt%t8QwllZL#=ktC)2In1GcfGx&&WF(ke`ogvl7_G~!*_FsIqV
zAw_YGhX3jyIxAekw=Ty!SPOf>ztTQZ@{C$=<_$T?xQrols0y#-HoH3Z|K^;3ltc~K
zh9DDV77|t4D1aH)KU(;v`lwlNQ`|NnuIDqe%wUXwyD%)QGfS?C%qaV>yM{M>W=rZz
zvXBr}uUPjFr4)~M$j3aV%|P6Q6Eq6uybDRtMImU{fEF0`ovD<ysj3npK6Uss;-_g?
z7IDcBJ6z=P9rLlBpkS9iT8}LLKMjL?C!jP4bN!Ac9y}Z5$>B^&9{<pqb}@Dwk1hW@
ztA*HVb%^u9%3;OAi+YCW)DHgU;h_^+_XbilM$5@taPxLGFDN$aAL4?%$QtORR1Lcj
i@6lO01M$7ShC;OVFe>W@xl41&DB`o?t+1k)i$@k*hui-E

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..95617eef05fe6ea2725be6832b552e85ba2506d4
GIT binary patch
literal 33976
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC5pxDS<YIDs}z(`f?
zy?_yoSnn4}Wq^`9>e*DetF}3ohI~pjeo4gxGVRr7YkG41S45&z<Wq~B39x}KA<mU*
z5kpUHc3eqb3Ev(n5))MTGss&u``lxuYk0eSV17a+*tasCUImBapcs5EQ3HPHgFIW=
z|C=NSjWP8?@+2(~Swbzylb$vqkdDE%IFQfE(dau5IeuZ+%*oS771G|{=#16ek!lWM
zaNqx83%R)vgs4)9C>@}pENL*>ysKOE^A$gQp_C9PjJmInYzl3<MOdk`ZquHUKqtob
zCVGg~yBX&20TX~P->RI2nurUr6WUq@<4kjKZnh=NPFdvz7nw(LA(W(aOhQLvfjUgX
zb58dUo9Sd7dotnTGY&q-37WDKE<0VFbnbf=e{EESKC~Z{RF=(DA6B)4I!-jdTx0Tc
zyM%Pd3KamaK~CpVgN_`6hCH@ai97*>z@9XG?Mvw4B9FH91DJ|H(u?lRRFvIMzmSAz
zE5q4@$rY7G1+`VQK?_9_!M~Z!65kEs?8k3`_bo0yaCHLkfrRg>dMF1sngcVB{69x_
zZle;+phjdA=?ld7vH^`zc4ONZZQmi3DsUpX*g_UHz^e~iE%#Pkttng|yF|xIiM#}v
zz6j~;sO`v(HigiNG-Kam@)w*aXM+<&)^lT)F4YC=llH#A+EU;WgRPH0gYA(7HR0<^
z(Lh?~MdIJbv|)rw5wNxk&QoN;A|0~FzN;XGfq>bw$LFqbo}C~fv>p+A3EL%LYBKlM
z$jfwMj5@r;0y+!Wg`$yOZx5Q=?9_xD@)T|nT@vKTF#QK*LU>ZCA*#5N;r64LJj#gU
zjs=)?FYIDB_J>f~Zw+T#^zg}~zb>vbB{+$tBvy_h#;@r3rh+Kp)#`_j38tGP1)NET
z`V-aIPA~ovVv0UuscGgzO$=#z*U1BRa|?AT2vwcsP<MhYAFztH#xgO_cLoHRqO(!i
z^JW`aK1z7a*s)51kayQlF1|u4xt(qHvUJurNo3%04%949TED^&!hBO!nitSXCM0s%
z219(t)IOK9<s=9kvlv~|a;KeEeXvrXhj&*`m0Ho>OwKZc1^;KY$e3jRE#dT#OyvN)
zQW|WOaI~Nt*!@^SgClzJ%Orzc2TpKm#oHVDili&#^oyN<CxHNBQoSTJG~3|9y@{QJ
zX0~bhLkGfUbm(Pcjpe(p&$4oAZB}g+i-s=)+4^|7N?JL4zXROOc^w&&Qk?BUBxE$+
zy*UrFi;2!hI#Q|STY)e{5qNu{VG?VFhlCp#qEYwF+~62%9wL5=_yat`9$VB8WJLcQ
ztgKm2Z?PoVkM^>9Uk=Nkys|(0a)X=^0ad>znvG)%w!sb8ZU@^nfErr`k2|5ji{J;~
z<t;peHHXR67P$qB?_Pgr550U8AteB8E(}MIuYtDQ9cUk=qmOKyhi_G#1r09{K5PWG
z`}7DRHn$yu5zW>TG4^4*J)<U&8Xu?rDgxF#e%Za|V=g?B-^J6?-u>W6WmPq1IyUZ8
zZlFCJ<)Dlawu(dtB!2q5Ytm=q`QhAk)l?c<cnn*4L*vf@mibiC*=pa3c5n<`j;=Is
z%Z<&kn*S!5y%L@L-sVsUrAl#iQPxa}Nh$?F$tHaB=UXIed9c|=!2=Z~6o@XMzisk`
z=!iEm2$zL}2a@vQ*vN$Th@^P;GX+?q3!LGarwo&!yg5aYJ|C*;p`<cpDi(hd5L1V#
z$&3ZHSemXC@OsPpNg}9UX)42VTd#V647yCu2#q!>731&d5O+SPdlat|*O0d`Fq=VD
zM&D|_pN;+woU&INUEsp4j_gF>I)v%u`HN^L{MUKNY7B@TZi!g_Il6)0JiQ88vSXI)
z2q!Up4?kI#<ZDug#_b5mXJ}vsQjpAf`cD%0EfzM9Y!9Z5sHA&}GZZndw(KsEHaVvE
zCphVr^iulHb<I~|*^|!X*1A(Op*~sJXQGq}_Tt0faf2lK9k(L6#ptLqiiiaqVASWr
z3wi=V=@4`y7`KgQ+?CR{IW_FugV>@{{|ZNn97q#*Ef0iH*P>s3lFrB#%kL{SV#<k(
z1|ZbGAJ8*5rYKozHDI+p@MITeGNW7tXrD))L$#Ib-E^J>cu4*0x($ITrXr5b*CQbr
z!uilxUVw}KRKNQf*F|LCII$d<y3FP%b;-J>3!O-2d10Xz3vj59wlP4?A01ZZ#gA#Q
zp@fGkF;K)1+4L)y*V3+<d-SHL%=rBLlcQ(F`-0)terPE(enfp;_*#*mX(Wa%vs{iP
z*1UU7mEH2bgtUljY~-@v>N0YeyuLS1aBlPX^Ry`lea?F9;REVD9=|whN5z2o`*ADf
z^&{<{{Sjk$3T1ZRnfL6cWJ^8fBfpBa`eE4Z-~grosI_5|7bPQe=q{UY_=&zh_6no2
zc?#V8zm$+=gL?|Z$YHPKmP0evpm0qZ^$gnxnyf`hgzn7-AL!a%!<=x3;lOn}6_z<+
zwM`q7e7b{W9DP;h<|o{$N&>(iKSjnfkebNNC8&!}X0am&`Br#&E3{}+DB3ig@7f+W
zJn1Y6j|lk>HAbp-=nRh^*jYcDP-GU5qZGse)Zjx5{0NX2M!c@(b-z&t0x<!BQY-+3
zbcJ7tJEjhb$<s9Z+Nq;RNq1RCqUPDnUwEu`4GRn^_|&)kq1F!XUlq@-8tQPGAq&RP
zq%6P3QN0?3-l8_9P_r8*+iNoGRTl4_6cxQ!X3E>Z9%YA%souBz#S2Upb|-6kV_}>7
zXt^J47;Isb%`C*B*Wx?&vuG>Ukaz&XQ6*04$<#Ihf@s7Yc2lY0Ry;mQmi@#S8c@S?
zZLu3JnF{jeyJ)hi{EhCMJ-;YN>2*d5i|#idBwQ@cB6Mk)$Vj(MLYrU2vXwECM9M4M
z#)5jGpf(cvFVR-q%Y^E^hCjl+5m`V!ef)W(9o-fGR!l0KJb+cp?QE2H5%dgoxD{(N
zt$4|Nayz#%oEBa8W@Abp=l4-cJT@3K(ASUYx0jwlcOzy>spl(kFN{8%{ZFGkTb<vp
z^_ac_a1yDor96OgsY$7}Kv%U>)f59Dw)ZkXk$>!&=-GVRZDHQ{uzdf9#umztws&9F
zB{Xa+SN-|f*W!snV9>j_ZD)^NVNk0G<PC7tFioY!UTdohE=UaZ6vx$m7aeLW83Wt`
zc`8~0y^M*kxy$i{-JKI7U;qNFX72#B`&kO{Dl$@OeUGj<?L6`uQ<H$B-YR9C00eZw
z&{6Sm7-r(r>e?s<9_KoV@5h`hYykH0C@0a|ALid_n+QW9Nh}UX!B3|{cU#ngnk9=>
z>k0l+t`WBpECFG;*1$jr$h2JW$N}n!<k1ARM2qHDJS_eidGBqYSCO0>$CrQ&b?EE|
zlz9a&;V<l!jY#g6N<7q=@9urww^BU{D>|W?bSCI(mB<uD>odGB{Re#UBp!-KJfbEd
z)TGnl_2h}bJBEugMJTW03HjJL_&=vy74GFKoK6**zRe2q=rh<|k8EM>Pcx)XQlat(
zJ##rIh!=cC`U{k*z?m$7ddsQX$HG5P;aepM&o<@^eA52p2{j0cLqqSgeT%uMLfEQu
zaJl_VNlm~(V6LhzJE($3U4U<dNE%BJD^FEY=61_@+%!E~UcDdEkC9g32*WTSH6xlf
z(AB6Rsa12$<anyf<UQ@h*xRK_Y4zLxfnVObyGNNrToU4`vB*Ny!pKG7#5e<!yi5Ay
zGt?}ZY3~t<0SLbzyeE8v#5e_H$_WuDoE`Hu?KZycFQod%C&AfApw{5yMK<em+QOSg
z-vCx63&ZvQXL%}wrxU5GO+%z@7M<EzE5+Z7agkE5qabc_E(mGGXdvi0S7W_mMr%+u
zLL3Pd0MNdn=<Y|83uU<MLxPz!33)sJW-q{o=BQ=Rt%&gDSk}6vyKkm{Zk(C(_K<X{
zMl{ZP`*pFt>emwuxUTsUJIC8}-gbtd>7!bn0iM_Zbc6`;82N)FqmvpIZKpP6V|U2~
zS>DYFi|Jyc$GxF)ROXLR?nG%Ek8p%bn><MJ^;nr)%`#7}mY>a<DZ|y?d5z8TUCMKF
z7%2O|AQSOnMroNLhf+$~%XU$viZ%hPJbdM@07z2zYQniGdbd?k`kzre`PsCMd!({b
zIOE2)Dd}9&gKo&LYU^>Xit;>v1~#xFhcmJs7fW<t&IvjQtDLb{$v3>q{1P~4AL@4F
zkx}@x6)}N4no_}Ut<?8X_j-oW(ti@#!8Af$0DlL%l@hDL+M-|0T>L&V5bUdR*+y=G
zhuVV(FTW0&DSn=`osVDpVW~1OE<%VLrWM5sjmJGqgQJ!8DFWkyNg16VDQY3OO;Ipa
z^_TjspuA6zm`j%TdF=Bm$&^5L`U{bB%p)Zp`7H&rf3l9DCrHOVhc%o2vAbs2U|GE&
z&*F})PABx+6eJ}y9BGkjf8+xPlC!r%Ev4zd6$};=02+6d%wmCy?&7P9(oAxqw0EHR
zpQ>J6bilHb?`d+96RHK(MA}}5m-9OIT@#QWuMwgfHkto~_#MiGe;S6AFI05w4Z~hO
zlxe^|pEo82afjfo2bMWSLra=<mrtC%Sj5XDnEJ0w>Mhq4xWuqIw5li9JPBCzdUS*p
zB__&5>30XqmVFKM`>gWLEXfiY$Euv|1eVY^Xj=BAeF?J4Q%>1!##~`QewdnhC2|?f
zL8`y{kT1Z2UNWyTP@<P%N{A*4|K!@n*+i?W5rQ#%$WKM^@iG2fH-b#Aeq>_J?QpWo
zYa;;OWs80Kfa{d+Fqz<@qAKoL5`^R+iWb_oLodmv`T9aMqYhI!0nQDr9qJ9Xlscq&
zB_gg0$MpPssyJx6Xl3fIQo6w2@$MWA>ofj$7{5U2B#pVnLQ6+(WNzJK2_eF%-qvTc
z*46A$_5-A_i)zCkqJbf-TDI?hxIkacbFrK)!A*4x?T!O2P)L(q&M5a1y?ybG)-hR(
zH^u9e9)E-Ui_)p4D8ORX2<u?MLL%ot_86BX;l>?LwvbxlIZDK75vlmnI#o4$I}KO`
zRtf|^!Fy&m!&KHXq}1Yaa5+Xf658%O*dJ##fPO|bxrAJ^^7FA-G0{J0iEdX#g16A}
ztf2h%;+c?&J8a1;!Y_<d=@Kk0v-Un(l**i+SAZv48-Q|tikU!|ctJ-1H=7lk9Q_Qg
z!LybMWWc4Q$-BwB!mbEZ5j<=?;#2oKoVHU43|9!NoGtf(-mo-HwrHS{&Bg=XD{(bv
zzC!0i|HSwP`+09Lm~VoQH#_$8c!@?9l_xd6n$PbRoF|ywg;HlssQn9|Pi#tL`PHwX
zJqN%2XQt0{uR+}o{yFmGNcKCD#hpyg2pXfDp2Noggd!u_0`M*rfAO7(_U?meT&D=Y
zPMCu&p+2HZOvZA?(-nWx&dw-weU#}7`;Itlk!h0ltwKIID@3|SYe3ZjmOoephNz2r
zN<-xn?DNKfCoiCbV26opXx4M`uVzjcT*mOFgUGCZXX(;~q`B?Jb_ufj_#&m|IlZdX
z%#hDf>bjRVjtL17;BbGhXD{X~d!$W2b@yADzoeI?s8Af_KL=}1zKyM!KiwAgLz&$g
zrh^Ar&F7X-GJ7HW$rG!ConRZo_dIyAI^HoesHJ7kAsd8i{x8SS4$XQ*Nt}*>p;`R8
zeZ>K4bKkha=F2NBy4L)83U-+?H)SVg5h<WFr}vc(u2wc@t<u+Gzo#Ot?*l#HbYN$N
z_K>9^20Z=W8Vs?yZO-T0y@cJ75UZ$^Up<Uy$UGG~D@!MKURN@=__SKmV_%}r?@@)n
zZ;I>6?viBil&*N6e1kl+4y_#B)ksSkm>@vCtN(_bYt3lH2`jfKdyfJu?u|5*(E#2{
zHBUF2j7e3nJjwz=dh<K}?|svsUoyi-DiGle$olm)!j))Z1HvU2J<uolJ<a1zrc@*#
zx+X8=sQojlME?iXE7w##t!o8$ps3hCo=2x}7?x;VDNu}*5CP;y*KFsK)wdf<3WJb1
zG5opfl^WFVuO848fGlSH8i^$CGvdDVsPhKChEVE9Yb<yY>Wi@J-i+yZEqwW80Lv02
zP96)eMc+2AxyK^S1s_8&;s8-RK_A}}VB?XFETqE|s+NxU_VK)`G87oQy&m}FWq8Io
zedFfdd8LIRl+OYqvCseCKl@)o`kE5`0oJ1lAU>GIldoajohksYxpcJzO>2N`JVV2g
zA7KDB-Iti%Jh;CWc-?-)2_go$k|6Opml7>vl+8!D)T0|?X)ZbHu2^vyw2Nh}SW{9<
zDFr3#!xGC%_9j?NhEyn3)MiP+!2`buDr#Ne4xeQAM34a|L6Y!eb5eN-{?fs!Srf7K
z%_+c?{Qx+g+q9Xe7T^NcwP!@|vC-QjUT1|zeYHP00wC&8EI$IMjk--utIS&t^B57Z
zXObSW@{ftBkj!F<t$Q=;v8^|Jm}Uv0PljuOW-7;53(B`#WLC$(gHz5@0m5yVuiyf2
zH4pP$NXV4Wx8xjMu`mBsDClX}w{_Y!oW0MB$dp<Jtq@mAdo-|Oq~_{ZA5o*L&)Qsz
z!<|KS*bhOUdTjh35U5nroa&fp?eV>Y?Z2e{-`Zw#_gPF-IYf+2s~pLl>D;rlvjk`|
zq5@S&vv(hq`DMqc{}bol_Xp@gH&&=pZ_<mjg1c%U;~<-$8eO`AvQm6$s^e6}Hwk5`
zCSc?Qq{=rTyjFDv|4uqs47};iy@kCYPHHOTVO49(nRa?1UB!n(!NE5Ur0_yHS<lq9
z-(qhu|6h+ucn}S{GTo?}S$gjTegp7K$)yfxPvfk*bl$YC{^E3+4m|G=^>!J4%p%Df
zn(*#K-Xhz$zmRu_*U`|1T3%kv8=*Ci`$b&jn1rx-jsah!D(XZbXWVgE?`W2G+O8lL
zp3QTV46q`*v3bkCW5{(f-gE3hIGylvA%(o#YM3C<&7P~pIL}-C(rMoCwzy#>gSP%n
z`wrU};Q`<kb!*X(4>c*3v!>xzkxwMBb$i$;8@`A_03GPBVb(P^>Qba*X}?~-&EoU)
zG9!M<+6F7YlZGR_EYWhz<y@^tmK+UHWO6=>*^$W~cBc^dv;s<YpLlc&M23ldMG4Wf
zxALe`NFx?|68r7Av~w=FP&75M9kz4pR7q$0L=y|h-;!<1H8wkhbV)WC2{NGYSO9}S
zJjvJ!L@}AsT5vZyqK?w+)iX!7@^2wuMVj6pMnz4Yg}?RGWA3F4N)gFK(V>6BFKu|<
zWMwQ-mWnSDWp&Jbs}+ubNeU=1OVp>YX*%~;sV;dJlbeUNm9B-N1JMtF119EfsQU6}
zaeQkxA1Hf3r1&cyB-%bPRI}u4{CJfp<=akepGA9c@$xdRYmShL>fSLuvF16~^}gF0
zc;{K(=nPmtx>t$B!!2;qd&vr8!AobQ_LEZ?Orzj$Xr#)zd{NMfAD=9VTqMCGy_NxW
zsQt}St!_=k5#S_~_^;z)F6JG(7D)b&QsemADM&GyfWU1nQhgAzKY3<JL{Y7CIgINO
z`l(gSrQNJnqjZ^}QI!*(o1CLpr*HC@)Qiwp!@UyquG8}iQe1PUgVSXz0y<e4)jR&a
zP$asiZ^qn+izc+3G<3S(6JCkl0eHPUY}>ISodbq;K3m(W^sz#B2PnFmIJIQu;WYdX
zNvQpUZkW_0o%<eW<gW-vt)5Nr{)L1Yt`5jNErvjZC@$q$Mu(Tzf2-BZpd{|t=N4=K
zH1mo~DV9`iFN)m9<e6mTQZQVoe6`p_MO?(@rD%UfBBkEyfk<FJok5B@33jnq;yq!#
z*2tyPkM*N;pWUgi88hl(%+K6ozqoe7_B+UtUaBF(`8b4sz*!wR>o=WNz}Xk<BFf;a
zB8TaDKB<)C10-A>p-%UP0pCXB%h`4f;^E<pfg%fA6w$paZtZ*tsAu<|g{TYqw-M=h
zhmoPMh6{Rn`SCDQ90woY&Y*AXmd>|njjWx$Blls$dSqHJC@u^*&<v(MQ3!Ww+Gbio
zKg!ci0iC+0NUv;OMS&msNUqA`6IB=JLrwQWdhPnxy0V#21<wAC2T9YX{5EUj#0$tq
z^D*(ntU$^<T)Cn^OSysVo?L7seqCp1u{M2;4=OFOf-yv&&UV;2;nk;XMnAA=Fg+}r
zXlzG{(=7b7Rwh`%)sruo6h8!?7LirGe8u=3b^Q*G2wOgP*GHPNrId|byh{ciRw}+p
zw->M&SAJ9lZs|9Bgq^n8lJ-Gi`(|c9Z1oP3>>DmBb0$a6$DF>vt4YJHA+}OGbJfVt
z4q%13*w#Y=@D*sDTIOS2g<)Z^H1MW<DCodTz7=l{AYIfV*#C1Y{q4jh${zjw(s&rX
z;h|`|dv25b%9WJ8PiPZfs?a-LGLTfO!M<Kf`RLwL!Lz$$Gu;-${8~!DO>H2ZW_aio
z$pJCD*MxHvm3L@)g(2h4tl5ZB@5C5ry+-;qa3lWs5_njju6i<mTQ^|MNkw5*)-W%e
zo(b~FbRCO`M^q)wq}~h3qA57)NSC0&7d<uUB#-d;A7MRZZiPnd(U-@$q18_((owG2
z%&YDW62|d|O~Mt2ca-Qx4;?FWjzyE{pXt-U^R+;#$eZGMXsiOtMq&uA;67<MAIMXi
za*2><tt{7Yv*|(?CM#!~(jH?N7+h#D6x%xEd4(k5HLm0*86S$_tUMdYHc6!m1d~m7
z_II1fvg`>h4f#vXJ&-XST^68!ay~y|R3clLjH&8EJ3eD|g&5}TW&G1w*<3eGKLtZ;
zQA(9Gmbty4i5$54jQ{$l#g_oG*#Nkwkjz?g;lHOf11@jL#seuV`kcF3kR0sqHh!st
zUw?8K5pSh-Ws)F9FzRDFqV-G1?Ai^e{lh;=|DI?<kzH>Q>OCB~koIn(jtTajnXAPc
zQ3H;kMlpyyc0srKP&nZ;U_n&^<4B$^S;@2yAdo&}Q$3ztHcvA+W>ab%S0A{U2GcOu
zDhe#lFfu;xKZmmm9(Z-!jmvUr#ML_hDn4w7(*8Zvodc1Q|E6F_#!H6bWPe>JFNcms
zHgD)q?b7HD{L~&$qj=k8**?)NY}2l#zN%Ob=v*vicg6Cm%S)!oZuYe$8wD3cpBM0K
zs*eEb1sabi-Q_2loETc`ETG>5W|)b{2wF=C(Za<T6*ecrLtD{xQLy(pZObDdW@JL#
znRLINn>q{B!z!3sw&gNUJdky*iI6HS;l}@}1q~PWM~cw6md*OzKkW@YUv0M$l>?IA
zHQ%Tl_-$c~+j#3n$tjDo8p79Pv70Ct^<(QHgth@Tb-8~p>Lb;QKG)TG{OL%ff$zvX
z?dE}S{6u)`tcB$_&M7YFY~dU6***uN<w?Ij!UwTa8bSkpWvz1K7(UR|cj=FRjrhFZ
z(ufWP^@cz7YMRa}(wA)B>@D4iAD{GyX!h^dze&+`y4xTGZ(W`nOhbyzL&@W4q6BKP
zhQji67W4T^Gf?04dUQ_=@V>`vnt~%op%ej7&K8q|=GspA@HFAqspK)epuB+w$TVo7
zw9sBBQ0&VZ<m{Y&*(#{s9>kNA&ssu3M@lK{K}-T6K}DOKnAK@qw~g~`&0laK3qr>M
zlgE+FPmgFBCL?>$;Yl{Gg{(8rllG62^^wWx*ba+On%Rh2@id>8Mm-n@p6@88v?0{J
zr&7S3B82QGsM(kwm$=vO>(|DnPLOD5D;7Kmg5hpt*KBDbG??7eQt(D{WTAp5Ij~SL
zfX;ay8l!OKHuHK?94n*^c3+N(1z73mR#}n$cS%*3eT=Q?{^<wbcM3NTc0N?NK7Vf=
z$21P-zddT($w|^Wp-(joC`Nh9lm}r)YjR1^_K6!K9Pf&2gwBd8R3CXkkD;&AvB?Ht
zCMh%y*WAENAB|`}n<Vj|TeXei$O~a-aieoJ7^p?I3BmSO$w@#aMNW~pq5#Gpvr{%F
zPKd1;S>2X*k1K{?GR11eR`k+Qt#HMjl0{f$DS%lYyRR?tI_Jic0=t=H-InbPlqVpr
zIAoZ6BST#ECSOQnUJ%47(95kll7JvhlJ8o*_MhpL!&O+*9#c2U2zPTYWqtz<Y4Skp
zM1hbjuK&U=V;RrqT$DP@$uex;_)ocx$Vzd~=IlWPV@>WI_JcLF2?lmV4N?abdF@^j
z9-Bgb-D1S$o1)H|`C_M)ggB&x?-0fh$m)@&!}A&fMBW*G@o?z@{9VH8{d#8}Ne3Zw
zE$ndwsY_W*!D};LUTamIxpLwj{=}qzI%Rsmvq8J8h!ep<B7ABDf~g_13U)JL%F(yi
z)6)bar-2S)t<r})DTl)EsF<vGW2gQBk~^6(6&s9#t1@raW}zrc!`$S0W-F1}w=)iA
zzYLkxI{pu5Gd|CY*}4%2^W>kUQ>d%cVbF+jB*i7SmR{&(r|z7i7OMNUT@`rlV+8O%
z3Agv2zEfet0h8PWrhg!J<_t~+9zkh6w!@cqTIgKJmq2PamH@?lh5R8oP}Cs~(vYI8
zUCQT3F__0A;Syzmc#R&qJF~wj0urv2nI0^M%vA@L{g#g{$Qwdm#{SUvpU)DjW7y@%
zdsT<lVrwPqqX@nPOGG9SCP(}?=-$BTI4Z+JepLCVyVU5Wn(=ysZ-eHIw!V-~d1L0o
z*X6XNd9<-PI`2<Gf@fne_GiN-eH?)<DDr6!D5TkQT1*5%x&0xnN2%|7TqXU@9^S&9
z{km|t8r}_EfF>GBmOf?>5xKfzwoWpj-hu7^-)}D!V2vN|oluCu^H+|Ha~9B=Xr%>!
zk^dwlvXX4Hvz|})3=3ABy(R*m@5Dff-mq+|Xz^vYvfrrZYvFeN6+EwWjb1qM(^z$4
zpmVU!Jt!!B^@+lo>LYLku8^?D^r)@gQ}|yqqBdX>Tq;A8Dpm5x^~kh5#?F4@^B4%R
z*qGo9kuSI8#@mMl$IDUBNCn>sKG{=Kr>y7ifI~wJ+#K-krq2Yi1{F=Yte2%yurr+z
zov9#^7Srb>is}Rqj_jnW5UM2h^im)ni(YGpMiPASK*vo(dV<Q%ID!Cb)v3@|o4EZY
z|5X}2awe7BujK6C3{otA_o?Dt(vT-^@Ub>1<9e&rY;i{C_XGdJka_Wuf#xVGdd<P3
zp0nM>e;Y5IjtenE4{7-^GM$X6MVnb@>CjR<=8^4ng7Y9%WIoR@DZ5g2kCEr(9>GHb
z;{a@@A@y+b5u_ll1uuHYioR<LOXB8!rMe5{XnSKY+k#Q$eTVqcwI1Qvs;(F&4UQ0#
z**}m3Z9!q0!nY|~?6Q1Igjywr!00V2NQJelDI(sr`$`MOTWj$DB;_HtP0npu1H**q
zzT@Y}gF0f47d`|1gnuFsceDE*Vn~i+il|#_bV6X_{3~GT<X*%#b@dcgvS>6L-?_2$
zO^koz)#Uon&KlI@XwET2re4d<Wjswc5s=c_XgQBWMi-p{%O-6Z#QzcsQqN=jS3BI4
z*9+Q1$^>MNg<w?3Q30L(T8A753+%smaOfQ-!7t==B|?zS7(7WnPjqCI&z7X`I2Px_
za_-_J`-cX<kt=W|ix|@D{B;Yz>CkW$3hygh04i6cSVG_v3liHf3SM<e>7sMCd)vUn
z5-CvRXQKL6VheGj;lU-_e0<Ex8f@|*lVYow^wQnB?7hb8aKNmvs)t;k)0Ai0F1mc#
z{O04<cb>qI)@V!M9yC})WF5|rh^xLdiWVl5L))AEIPgiH1H0_%4kkp3Ex^5$sCrOq
zoYZA7C}1c+c>wfyO+wGT@W)3K58jaY(KdSIp8o?iEwO>l>%>j&YQ0(jC}<gP3yhQR
z4L{j}T%!ldBQGI2v=4eLAxZ&^+sE#s+@#E`J{p1-r_XG$LPlE(VWU4e^egV`Oh(Pk
zau}&Sn^(CP`$sQXkvoEPtN(E45gugjQ#V*TQeK_^ppI>-;y0w0W|$+5v|8E_<Bjin
z6ra~xkE+C7s-pOF#}AD2<7@64&z1dcg%HHJ4wp;Ik!Gv)cP_BeKl<^vRKgI@@-$6%
zbU7IMfD6RC&1vi{|Dt@{<C^r`awlph&0J>;25W_xp!?I|wi~~4{hO(nJ_EE+7OiJ?
zN7a=0Yh;;duxsg6o*=hzm2VG~r()TZ3>r=Tw_qYHU;)Z$055uSpn4}ig7n2?oW^{E
zQJ!^)w<>x<+DeC9HIksSdsRTghhH`c*K3-bX(!|`E2t)C)hkHns?Fj%Y}P>&_;|0?
z*`v?*LYGrCW-HlycxaE~;n&r0ufmXaqhvJhgY5MB8mk}*^9YPffQWv3q0U_;S%?tL
z+ogg&i49_iKvB<4o^pUTi)HQ$kq0wa@A{z)MRp3usj`Z?Oz>15BCHvqlwswp5k6Ke
zk!E4JmIsO>i>W(^z62kYE9GzREAvl2MWdgNZ&#9D1b1ziXe6G_@9)2))O6tnx5JwK
zqFMHcOJGRP67wR$<hu3DTvHoHPsN#D`2^G5*ZfVQU7N;Q2W4#?vX*cg)yCXv{mCbT
zW8P<L?RMc=59mq7f_|-hhi3cf#h^nxDK5nFB(%nlqt8V%R9~+^*!*ZW(#?3@j$~(v
z8NR|#p_(SBr986k@R@I5_id*AVaPs3h`gkowx%J*_jN2Onu<rT&k|K-e`~Of){+4&
zaq&UI{2VRLeL4%1jfj1`?u+l!?r{&#NDWOa_-kv{4fL*9GI>f@h1_Y&0DH`u-zkG~
zo+XSS`hR1^XRdaAEd`-KkpbEG(WkJxzTR>opTf>M<`-<2VSY_-Pu&lv*Z?wd&_&jY
z1$xm4KR^?+$U+*jBc?gdE~r>o@0L`~jEVZWv;uN6)?+G7)o^C=?wz3hk#e6rR)<kY
z!0CyugUt^=V3coai&%~*>#ES+-?z1}(^W<31F?2(NTCWP)wbx{1I(gE@AzQNISFxt
z!3V5&=;6ip+6{9*WY(JfnHiM&PXg9fC2-bVR;9T$nMT(KE2U^jk;^w~qhU3>uHopu
z&_=_O_Q>gPHxH0Prb#Nob|7surYMylws_oCYidMoC{-&xl*NMJ_`mrQRT?)5lJWoO
z2Q}<_#8$k~P+y|(#((0L@q93nfm5CF-Yt|u7b>-o+Leu8S&kN^G`dN7Ol*#7R_n;;
zY;cUYuL-b+b}72@?D5}KLYMdMixk~1^F*A14!6{eWxc+p$_@UixbheE!p%5mMUE`q
zNiY*=$0B}nc-Uk_C1euEdU}>o$xwqamorm`^ro@*LA6*Q(J%f(xZd&@Kodx!r6JHU
z<J^VFZ>F&oB_4bRW?%{tE~NxkL$FVmbc6B8wRh>{)QT26B4LK-7UCBE`5q^zQ!3E7
zifzxgz-=y83gwQh-N)xcW2@w0`F{MRWT(bK-z|o;yJSg^flU&t&^>Xf%X9osB2iXE
z&UjgOy_32<MhvWP{xPzMqxVTHOy`H{X9>7IoX)!{rgq8R9_Tg45SD2{t*)>}NsQ!W
zeq}O7>ZUusC|p4`!UJL^xII0;5AK--jwrvJ-S>X3FAlec#k}GP33RU@s49cUn9Bzo
zO3UyI(^q}pF_J^j0LAiaGVDd?vT4#XgEOS%5Md{Yp`FL;0oy1Wvwc0cj)|Er4+OaV
zTGBDbc)#{GM@GjL*pG_isvv+gd29Tf&Ep5dz)=xXwe0`)u*WU_|DNcV*2eD8D~t5i
zZAzi08m+`*<;Td3pnqO~-aCO%7j5IbZ|P@aD~sRYr4{U@ew`I?bAhq~d(SV9k|}Vn
zeD+R1HMF!yDnZ8ot?CbKz8!7T3<|LJ2HOG(0Y>f(__xttg_nSP=X@@w3mz)r+Y~E=
zt7+`F?VVRqksHkShb6!kfCon<4w-2#+O0{C;mp$O_?Ev1W&ryWi9(uo@NzL)dfiIi
zJ3ex%c^CFV$#Jop8^NS1p5vZGgNkKSii|1{jJl2xI$=Ts<Vb-GNajAy{m&(GMQN4b
ztORjt44R#}BKE~6W5YS_*Ep_58tR*VC4>-)VM6FjMPEvLT4pbrIj~g|gTZRtu!Ss_
z>4gRWD)Qi(fMl_Ts-41({*l*Eh)NUkw36W)(Z}s^o7cgkV*^KrNa!S0?~H3d3vRSb
z>L#KDhE1-KX?()&7Z9xl>B<#a{~s&n)<aES-jk0P!=M1RAOL`wnmjiiVGqs;%KFJz
z(CT?q+2F*R+3m^i78yO$XrD8?c1SZ89#Ep^sBo+re&s7%Z4^UN<oO3Y;ZAmt>_fvs
zd(_zw2?_{^BBAdJ8Xd#51$@*~S)&pIVEr-UV{9eX0i_uq*3`|mbq*-nPI$JqsK<d~
z`ApZ!sSR8Ah6$7JG+5N11+GOHiZd*^3z0M>33LEo8r5~nQ~*mg5r3B%MT2($Rkb|6
z2*wG03mo@5kLJyVN3#Mfe%=<vm8)tV)mm|4t-rn%gv3a<F=&~vmkjPNn$BRd1`%ll
zvVc03#)5ham;XqX%Y6>z;XjCJpSMirhJT3PsOchM5QVcMp1~J6MdYZ?lE2dN?!}Vi
zVOfNR*c8?zTTKhu2^?HX@`gt}-4c|r`LBaAG{d}EN#qF^^jx}fzV7qQ^7xx|bFq*o
z3{=Y*$P==X5=)^XkFY8H)CWCkh&NEL8jYs@tFeR(x)yz~K%4qxtiHO^`4UCCG6J^h
zS5OXOHfzxtIY7d3$8`y>qV^E2CYLInusND-%L*L%^g>Zh;}s#N5%5AB1$Ay;%-}2w
zFMPnHr>64Q8WrZYKHLI@<Hx8UV5<^X9B8BA0q8nvJn}Cky{s5JI3LpAOYw6}dr|aH
zumOnpe&d(5r-ORN|B^lznEF0UM;Zd94z$VWeZfb**Q!FY$);)yA6E#K2Dtk_2)>EB
z*FI2GU9$<{G+Q25y56@-pwu_OXX}(W>+THmlwrz+<FD2<(AIGx*8vCsT;r<|e`Lta
z!^$n>&|(}rpYBYRnw|H^_HBfNooS36INfz6YAiSw)v;~Cd29e|O_7}Trfa^X320CQ
z<e?XsF`b7LPu^%|zHU@t-M51V^XBL#$%RXw1lG&dj9aHkA(GgE9h{BM_;-OjPV)wg
z-8>F2@2q6f%*Bh4zaUQ}flas+GS+zJ6NL+4Ei7H=J%EK>j_Rdv_~zX+hjR-oLl^nG
zUj>WFD#_k^Ie<t2VfXT|(V(E^*pV<Kv%=-QR4i~g$ATt@T&t^qR{n#VSQw?2lsn==
zg(Z)U?H08J`<<c40l7cQ4bvu7uYD5KH}RTS?)~ikC!}a!&(Lm;3#~11&q-yMEMtwW
zN-G*i;*r8|itY0O5ofOyJtjzs`M^V3!)?SWjEJ5qvSBAGRsAcTQ`RJt83p&!faS`=
z5eehQHkE+pT3-P2Oqvq_T6C?Tu^j8NIC6O|v{_=p2+`~<GN&YIRP6hob2rK1)bq0Q
zknwX7KdAL$fUpgKz-sx?z+QhgEY1BYy*VdJ>hMB^xV!*z<LdYW44PlPN|DE4zeLlm
z7_vwcv){Djn45A5#`!o|BdDRcWK^bm*bMlgKN`lT-(CQQ7IN(81H+yotPI}ec!9>C
z%j};o4>4&}UMi(=4!cywiAY1blzi+tnQv?wWXJ$ys+=umlMoT*)&71>VNL8myr$zW
zbEt}61j>~%>(@9BUBOS?00k=5X;Oow@7u&Vi$WYcb>2dKm8z{T9K(iMT6&B55O<h8
z+K*woF6Qm`$?Zp(j#IU^phGo`{wY{A`F#C~x2F=deDndK9Yh3OykX8VCnQ2&+=s1r
zz3Oo7M}mLW8R=!T&nDm1N+3V*^+c$|NS7~2;8a~|z6}!lat3FqIHOi*3Yep(0T3B$
z^*i?YI>B$<pH*t_w?!qWQ3{DScxI7U-oNHorRgvs9>*7jS*t+mV34_vMHYcd<Q|l7
zE>+guLv%Hf%~S+eo<0!(wN4bGGMOzgInH2lWA6F~$uN<pL}anJqe<_hSB%klX9N0q
zMEOQwjc#OQteiVTq>ZYD237vupr%-A+8$pZs$dlgmj>Z%I*ZgDH*fR+Amj%rj0iSp
z{9Oe1oca{t87lO{6wOh#V?`^A#vLZ>7Lrqffq>ir%_@9nf{K~TcfT(eH<VV(kqPJ#
zgTxK%^gIoH;sJs)c=*GnXG*zwl4ZG_O-r?$n)i>8(<l5?CapF`3p4V~Dl8p;!eWr8
z)wL5M+YZw?gh>ooS*e8!1;TKQjnN{r8BB|W7NV>`ayp#8{+iz>Ua)5KUH4`fgkx85
zl`9D^WSD1bTOd`Z#qcWC{fz4x(RFn}cmfq-l!IfgQj{xuUW7b_r4qu`+6<cd-{Gsb
z$tg>Oa`QxM<)41?Y21`BDF0M+{u2g;vMgs!Z156D2Yu4T@H9Y1#10AiHQv1FGvyNm
zcf0+`=9YNcg^8c*>{NA8-0vO7&?{aznP6gV<k|z&=l?Er?EWLFn+>iL7#O(_ew9Sk
zMYdz-I(&05erDz?j07;sSbU^faeg;i3a9ZIZv=mg3Z^Mm*e8~)7xt2b`ze*~vFG9O
zaO{p)HR6=v_1Tv*8us%W5^y@ed-W4Fp>zG!ZnE!0e`gCiE-0aaGkY?1WB#{vq744F
zx0pdC^B)DhO)OXx|JX-z54Sz6oi7szK^6u+R`Z_xR_?4MGqOBo?Q+vfYH0&dPINs+
z!`4|~zjk{t9p3jKy&5OgYGvD;&?C_&SYiZbf;8Mp<W<=0ck*vGn1KPq!e(d5;I*iR
zi42<&+Uq-{xLSeO2sV)__T$T-bbIzjzV7|HcFiD3{a-Ig)4V1bdNt{t&Ht4j|G`;e
z%}=lhH%j!~%(_5Liy~f?-0LhS;G}XdHn5L72(Wf6^0^YcG@m(^AUsd~*gV`Tkp!*8
zy@xi~gxXzgY$A@oRG4M}Ysv}E7ELTXr&Xb(g>P_wbH~In08Y_BM)(QduezFR!4G#=
z+fjQeDdyu4@xIa_G?B{~V#unVKY(_R3`_v?RTg>uz)&J9JR5V&AgFuo&Z^nlQ8VBr
zOq!*iPj<zGz**Jo_g;ohbyEp1Jd{~WdutY+%r&e)Dx5S#zm1I8IcAiBg2xo5G-}-Q
zzL|_(5vXQ)LTu6)zI<zW{Dq!C$#W34Wg41+KJluehLyJJ2IXKq9$Gu3+3sxStGG_n
zl;Nvvy8VeKh6B<5GYs37rCT?vtSL2Kzx@E9u(OnbJw3twkA}m^6Mi*3vlp7B-F3NH
zqS-VFw5s?>IDeqSQc$JoEqNP?h_)Az^^Nz9zb%T{7315cay66v&09tWA#=a&Z%+PC
z-|9xcd}dZkit-`}?r_(@@g?9W8z`s>en)a8|BJ1>p=e%)L)q7it^o1<s5h0J%UnUe
z7Kuz{T2tKNZJ77S@29FyycNxhe3C*1C=&-9C=oG}n`-4g9Fer&_dlj#+8*^{K_pf)
zL$%fObIXyg#mjQup`j&ZKe#7Ny~vb)r-|KVgl;M3fRM~fD+4Om;iyg3VvZ7)_aZJv
zk=ph}AhL5XTiutN3Vy36_uaxbb9_96lGQTO@`69tk1oEB2ThSA-TcPH0FsNJ*ohK&
zN4jFw5&rkG_S)8$uR4HjC)##4qUMxKWk(w|xQm<c5r8em*(@0e;Qoc!$YW{#N_0_7
zF(Cufi*AI_25rT7F~mh<#SixHFjh9^8ScwmaF-!V0RFaQ;=E{yKpw&e^!X&#@l^1}
zY`>wKg_QD*vNFkuvTHyVEkgNSTPw+);bCF7Z2Io?d|==YHmn4f%sgM<nu2S&oMsXv
z(@klPUUGkp8%k>H%da*nk{*Fh&J(ya-hJc{3TEdYATXk(EYe)tY~&_HQJ{eF61;?f
zov`}+YjUufa*By-{N1P%3o~>zw(UOpwdScO*Qa_~Y~N=~jNqkE=)_xJkFpiO%-yBY
zQtri8ZtGr2k0(kmE-KM)k?xeJDv(?@uX92b6$T&PgVuLw5?3|+6j2+}9nvgS1%Y=H
zW*Vbv7kFUB`JM&C{ISc_g!6|mPb=_qxY94CdTVg7aUzXdhmp6IBC7AYLVI}LFdqCC
zgfhXL?h}>T{MEhwNUb(YF|m45Tnd~si1Ho;5_3CF8uP76K6B`FmFg|WHW;0IPjD^@
zE*vY|)Ujhx*y=zqxw|*p0$`Dj;BhOPVK&*7$c<k?Le)(arsAm5GXN%8ry7lEk#H?8
z6n}~1e^VERsFElNbtX18AJSYgvg7x)f@)rs6e_VL!6XTCeBWDhJThzz#yAom5gIUm
zysp%+s$H=(|BQ}V*$;IHEp^4EokUqcL2{OE$0zZKji@Rb;NMrTLeR&PRq5!8vjL>N
zjQ-ua7oh-G%*c&2M5~SeRdlVR!#xE~Ye;2LSOD}E_OhRY`*o1Y7PcnrP#?8tmj;ep
zUc4jTZS9V<HjNs;C2N$f^6eFMX6F!eK^{?D#R4QYTHdH4NtHd;s>&3=7ELhDN;oFt
z5gVNR`0Lm$on^iXT$X>^Jw>9I9gnH^$`;6dl2;m!;*Rf|z8bc{1COQCpwNKAC>YHK
z&?QcXH6PeXgnf*jdr6D!P8IG9!NG!If4g7xFx)_F47-{=8{Vc*@5^&o>%%~i5Gmnw
z5IhCdIw<%oQ=%j>$(|cQ3z@;fkWr1d`p1&|#L4SS>SmIbs}ksWf_}riag2{uC;~S=
z(`9hglGDxPkdR6G#yt}4LrWi!YJU)9*ElG`E@}H#hRWQSL7`D>@RDT0kVF^v9T8#M
zcOl8N(=L$9!IBk@5!7D}H{>K<_L}rD=a-9wG5=V{8#@0bl%6}4*AxPu5X6%fBJU1K
z1Rdl<qThy_h2d2tC>cAFeHh+)a%&iw*!{sfclkP~#C`P4`l*H_)6w58)J&_ESl(1X
zPX>nI6(hutK@0;*Ym3P}{!QM8EQ8BZWSYn?Ip?_=^}Y^+8Gdn93w@!#P7!33ouk8)
zDQ-t@eUR)MII)8N?1hN}YjICeHn}N(xUpO;w5x1dff3@Xly2z0q8$O;e9Y3eo?t8u
zE?&F~G+H-%)$`wqcbYxwrIjG=13vcwjBZI|q?VuB%vv;b@D%<jPx-vm&E@)pVQP}1
zH{3*pIcKQ^CF?3+B*cG7$z8x=v)GCNw>@V{u@6)aG;IZW($t-r)=Dfso!Y@1-t~4H
ztJc4O6N_DS$zT<Q%DyOaUP!NcT#Xd%d_^K06CYC4n~fp(2v~wf{tY0bcjVbAgqYhO
zj#vIon1=P|3v8iDSH)`shdW5b>xR2^(YT4tsTF~mPH~o<TRkIVHb&Vu#tcbl%z*x;
z&BT*gJJIZv$|LIIr9*FjdRL&q)FZ}!QAP|NL7tCM1V&O3z?WW>S2LR*+MCuSmhC=6
zoDZi%7>^ndDK!m;UjrBO3)sdLdtc>DZy3eb-E+twQ0IKovcfzNs)_GK_!x%^%^smC
z8x+0DUoW=<EkDTPz)!4syAF{~pvDd}3-+Uqvk8{mJ~JVxKqKPMg{E4W!LuAl@(6eD
z(iQ#eyI3P4VL$V=69V|?xiv;Wc0dwwr+zI4d(kn~KyW?@&%ySP<`WVAD<WUq=krO+
ztf0j+9}H#N-0p)k3DG%wus(3Rrtm=;l;ERnp#nUvWkBLx3zPHnFFjs&S9KI_TIcWy
zI0ucvIcfuhHKu`kZklSo77XBq$gTkCIkR2OejxA}t`1<JvmB@$Q~O9U8|k<B*eqtO
zpAfdl*mYFRLQ)Y5@DKu~u*Y!{c(6|-hLw2G`tHBloX@zE!_9^UV7)tCeF+sa?e!&a
zdPNZvZaf9I_Kl8U<7Vq_u8=^MUts_dsq*X#T2Q6h(0a8R%F(UI>LBU0Pcl*V?B(Hr
zF5z~=9YgB7_>c!c2h8Ytokrm?AT8+m4y!@2M~KR%yO-CQPs`-5YFXX28`*>db73P5
zW<N@Yv#~HL^WuFp?;vT3;QBHEu-$IJ-aGQhkxs?Hj^tem2c3xwg^|&oE9QZ61ogJ1
zr{YAMWhGwz*uH4w>7Pu@DFm$SV+(H_@?|1dS{L$cY!x|qW`YF4yo#sG=932j)tuvr
z-3fCV&gxpR!zJ{oPp+Oz8B2e?@8TS_^ndtO<4|g*H3k(5s(*lKt(9bJWl($sjAN`1
zhQo{rXpAxh=^{=;Rr5i8U7EZgnM}6{2HP8{`e>fXY7!}@u>y+C`Vf+h=E)`<&!_ws
z=<Z>^9gSWS86rFgjQHQT=9i~p*%kWZVR!&4K-IrP?NTnuGk6w};IUWf;wt7~bBY`D
z&2Z^s9(X=o4tdG>YntNAa3)It1*^~@rNrE*_G|{!-DqLm&9l5DY3XhzQwDNMyDDMd
zj_5e-%J+MTvMn2aIPDND%aF=UbI664=_JjJVOnbrmsj`HqlwTNY<v8$wjMtb&u=JN
zyP~Pi{np`?BPG%#@w_Tamh&BQ#{G=j2z{-p?bWII&u1^pi~2(COC1A5hX1!Kp@@90
zcRp7~IC8E22O|)zWE=npE?-tzY|Y=%5Z>O%0nTO|YY8nlOTyFKcp4SviH5m<uS$^!
zoeX=nLdmFdVs=XfxYUI_OZ`8R-Cf$8Mv*(InUDcSW4VAO+g2O@sj6IY<^3o`@82!b
zUwwcBX<mX*@$h>ipM=5d@{~+N)B!{u7_jIw)^zLt@)_4*PZ=GGm<rj&*$-)@SsB))
zRzs@r?zNw77EaTqm0_;6_`J4c({+F=yi(W%mM3`GO#=jXuH(m1FIkfvkw4`&IpkPS
zmZ07AQuB>xoj*k4X+67Gv#}ybC{k<GuSmN8*c+q|OZUfBkSvjg96XMm9R=RYDbiD|
z0oKlRsYrA6tswY88k?`otMeexh#@7R?Bz{=%}4oAuno9}+;rFaF*&|wEsk*%Ud}(r
zx#(=qmg5ntt<k*wV>go=JWb_LP2=bFOpFVn`~^)gcYLa@wAPy`x9GmXUI8t}S&SY+
z35&}8(s;<GpDxtUkjd4~TNyCAz1O;qA+0hzjwQbMR_A(+m#E<xlORck*U@YjV5|{?
zQ#t&R1OYtly#Y*@i9v#Vx6``Vr+^K-ch)&%3S^Z3gLdLXTjYeI;rGPyxMpAOYauYD
zcxmCA;4%%$wYp5K4|%gp^g&Q*QfO}~UOOn1SMFFC6hmrOmH=U5cCjir<UoPpZaIym
zD(PSfjpc<{!YbB)%K|ATPex0EYJfLJB}S|YL^+>BEfkhCDOws?9aHi}GSlegRz__B
zo+}6xhX87KG<_mqh`X}m{Nn0;t3X5rF+#JctoNAg*O--uoo!fmjc)C=oQ1HJ3~_mE
zUmjq>V!PZ&0URDe2ivvz4M;AwFk*fi-2$*uwLR9Un9oiP2TaBDFS%q*Bgk5Cv$hHu
z2;Q;jmnH4N*|v^kN{Xr;Z4$fX`*k%g`YbMBP3aS-Hs$26vZRI};)i)c85XVJ(WLei
z-!i$z$yWAEMXJdmU#C>Jbh8w{cs&KzQ1^S8sKoX0nK3n#vXEncNYRmTT$Pk(BsX4F
zoio4#E%L^G`xnCChUtVQ(<V?~!BS5vAbR3Ze!w0@93~CuXm)i}G{}>c-)*u`$a^=d
z!x}nHxdK0v&iH9gk2FqvV(rm9%~bTD=^1{Deh$0BV`X&@0aYYUkp|{`klX@aP<~UA
zrT4Bv8T@Z7eupm1QBdnizSZOwyEh01l?xQdP!_L|OHOXWx_ncW$SWO-+^c)b<VjKs
z@>(rFtg$Z(9HEb)HG=)|*3SLISw+XOh@wd1$}i>&MjDSidPIsn&W^&(jE3>*^>uU~
zl@vw_f-Nr%1FFIa{HH$s2Gew%HW_%5FJ5T@5y?~Xf@r&LfLH<zDB}@$ffAYy;9kA*
z!PMS(jTN3la%4g|q=b)0{14mxe-mgD&W68%3Bg7=lhI8lqu&!3;+hnCzm@ymQ}>xF
z{J52HVjTo{<P+AjA!hu4?m8CoGZ_)>cXjMT4RelMbF0#(=*FCQMjV_Lm4!6>zLzoG
z_8m9c=@luBBddVCl!+bq9vSSgE0?e(enY4f5`+~?J;)cR8zp=?KC~GVbfkvZRqb!z
z2i9T$QPolTtU2o<Uxj`M0_el`S|*hlU!=Stz!}Ns7cHU%Nwt5OSr&&MFhv0MU_U{$
zrl0t!dit8MQ6f$G<yW=N{|dzi8F2wkniT84WT1J>nVGBse(pD_WI~za$E#g-(zUiu
zeec77t-yCTr-MZ;l{P8!L|DY_RivE%CF<n})OQVOJeqL6={O3Ac#|3*(?>zH7N6IK
z85_~JUZYA4&gNOkO@<6-ot<Jrb^8F+AuUpEG-1oc!$BeZ`x2*Q8U!mIT#Me8-4>s{
zD-qCE4~5QWXk<>vQ*2wmVb?_K7xB`+q8ty~1qpej4OV8Z>mhO6d5`w}`KP{!@Qy<-
zxa=JEtOn%2f7!#bD$3Gh@(z`a>Q35nOFiLUL!IwW92(mo&}biA8_~oN(7wM+*0v}@
zxVcYLpSsW2r3_kn0-N@Cp&J)?UHjw$h1xRTxqB_%+h4ag%4@M$b1qL`i3nO_sH)WZ
zQpS`n?Dz7Ew=gsbOXKm&omEuu(W&eFsvuUpw~j~n2zo4wU4JrIByr2YC5-91qsejg
z2C^bbPwP?b%@^FMlp`tX5uJ6!rojCO^Ix46N0d(;jF5qV@mpiLrtdXm*7RfB8|%8B
zabpu45>#~lw>G>wqotAGl35@^p7Cy)L~FDVo`#`ebmmnlNUsw;IHx$A%&Y`cM?j!q
zW0eXXRiYBvf0Y=VN5zmF!|Sd+))xL&^4cQ)aJjfO#L6$vlAKFm-UUdFkS^?;|MgXN
z6M{nggu;rm3W{2Ft*P?3NWp<8oZ=UKm^RSOhZcfe?IW5O<4^ohzc@ngC2^-cCyA25
z(!M9kDKNvNoQc`|gx|LLdqI;xsh(hwMWw`IH=&V4!Za`2`I+uZ{LuW7_}q%uL7%?7
zfImF5?dHkEtpWkHtK?4A&=Tf3Z{uVK3t=T-5P0XX9=l{cRJ|o6LV*<Q{6YTviG_{P
z{OzYGzWNlb%kfR!JI^TkV#eq>OFk(CcpiO$|H~ONEmFF-s*w!Z4<rX~OKAEzpH|G9
zC8=0-*?qo&d%2;LyHm4GI8Q(|wnLB2(QHolCdAp8A<NLL5?dCRz#w$5doN|>0M4G_
zrUc~0ax%#oVN~rMJSSnupQbW9-PZq$Ik9{wj9;G%N8R3Jo<4<Z!^t9o7Cb{8$XeTf
zfFF;Iy$iyCyQTfqfh-<zkZG`@#zCX$7X8Eb0*|E8xbRE>>k89Hs}97A<`7M23+^`v
z1)lx0RS<WsP+?w?^&9j0RBVB-0V;3x&=Xi?BZ=AhjoI-pCvTxIAdJlg3A(_M4PL8T
z@pc!E33<$)xZz`-<2KHvw+c67f)OC(uk3%xXYuuIef>;W5bzv<ob(b<F#>_W$!?b3
z5BDIA%j|q=gIol+?l-^kH>&eqRv;c2xKtthhSC90Gf4(n7zbvMsFg+_lD+iTp)0cc
z|9ARQr07tIv{xX|v^p8wbs)&JhzSlPevvE%x)qUhb85XWTF=9Kp^D^|c~<J-8D`f|
z+j6mUbPD!f`2m4SGs3_}QOkZ1bk#^iXn)W27~P>oTPZs??*)Q2?N=)G#$e~34KJr4
z?^S9QF)oCGSa*8aN14<A>5~5dSM=+58ls!w<X)c`?{>@=&eP%Jm=YNyd7g1LwiX@W
zeWkmLN>Fc`7sH9vR#~vWx3f!I{r(>7mOn}YJ)a3~NSM_y*VT&)M^kK|pIETbD~`QD
z$m^YVIIXcN?lAlRmzvw#44}lJ0@R+8$5Z{_A6^VH4c-2wM6iE1QI^ub8SJ3Fu7CjY
zZXkdYmMWVcDz!0txC8GemP0fI|IR&Eks6`n#xsA-pG#<hdE!hQk)JLBF$KjCTHWkK
z#&Q7n9ukt2rD$mH(CgIf45fMRkt%eBCW920&aHa)$QUG?{M@NY7z*8aW$0go;UX~+
zK_+n&tWVTzC42irx|$W;5tUKa7jyC=5X=|NLjFhX>qIvOSobTBSwXvy>kf5@+&kTr
zR_lLkdrl)9+W26Ns%ELXQ+jz4fDJ8J*Dg0iAu}<>fsg^&{Ax+Mort=zb6fkvECFDb
zf8YONX8j+quT4*+<sAXPK<%iBHE?y!0zmfDs0FmbSelR5xi<qYcVQq1KWUIDxAc5~
zL+%OkQn6MAy?MIoD;R8(R2@*+>_@{7b=RIsUrAT!bNSKpM~onbgb=Iv%ucrwPfS<b
z_vb9Pc@6M0kr2^6zw5AX48Gmcd5g+JQiC}!p|2x)R8mkc`r65R)@{i13L1I{++>RU
z*NM#K?h{rbWtRnf%D2Ki07F@Ohfuvk-JA*I>qbU?lX#b^25e&>z!`P|&b@EolHQ%j
zZ(3a$A_3aWY)n^zGrswtsV~uG>U!8KQ_Q|zuD{UuC?y1A1tu&e;bslcF`iDqZ6CC?
zv{PQY=bph{a4hICx_c^4Dzsf6S${1-2v=__hHHIsxo7o+xHpU;B%t|vkj_@qalfua
z0$#E<kZYjkq~caBL16qsV!Pnrm$4oh=UYNZiZ=<KK0tuOR_hx*uz*fY>5#ezv(ryR
zJoSCer$P<%<YH2+34W+HNxA>9oG@%?`%C8X?b55_!jXTPz1|kAEnEuj&-h606g&?c
z13n9j^nd#41pcToKC&n`i`2ZN65+R|2d?E<rhG(s0sOlT<l&E&IiWTduMiDB%cCd6
z?KI%j3C2(QqPK!y8F8R-B-9*Ah}KSJX=~}ui-FUrvWld)!aE-VXqPgs_{h_cp)=K_
z+ERVH*!EDZr_j$F=xw=TV~z%7O^EW!eTxm3TnFRD!VVcvoB+^{ih^^fm`)U^8&%$e
znI(eP!I^()gFp-SO?g>EzYHMM@apqcO!K?MPI>Cu@&x`8I}21B&;{Ik>(4VPavvXC
z6=n?*Ee|eYTAZ}O;+X&?o$9>@pD$cHwg(N@h0AD^Oqbi-eO3~V_T?ycB(p?a;BWfa
zy8W*zz+<7S<}kGgfp~N}Nj;&RwvZEbi~pgZFHBs<x7{)3)ELLZu!I(185ZhGUiKmI
zUTN>UpmV{oRDY<|NspEQ#B#Ru9*l@0_FA5GjXqX+Xi;&kClc_90l&6<H8ZeuOS12%
z&C}lx9-4KMxW~>mfy~&jZDJFtYhaiYD!Hue@3uqTGX69e@K21I7js_<xw*f8-+c=i
z&C16Vk}hVo-y<U=PAV;@-0}&ehRjv!suDW{K)JkhDPb5oMOV`WeulK_UqHu6qAbL~
zoS(Dr^Rln=u2HMAWRMl!lI)ENZ~|mPoe7k9yM+)p<*O9T`LD@v;dzKbL#3RP1H^6)
z`t<yCgsVwm#HDAD&^c7TfW%|3gFBmzk5smlRiPGW*A);Cynt+QkX%X1U4ZKSy6X3k
zu5lq2vicM*v*1@yG5<VaLHOTop@H$>y3rTRMj%4x?-9BPVxrUei$A{e#RGd=#*wFb
zhLXgWnhhDJW3q)@t-4+$l)O!I^Mz>}Q}i0*ubc`N>rV9Hu?N=tbq(Wd9U>8mK29+M
z(;ckR?EWJ~WMA@1)#zVx*y#ClfsZq8TWL<W+Ucvumvt9QTma3&MlokKuu52ST`~fh
z^7~%Hpa|F|SvzRp$A^$Qg);-Fg#);TN3jq<`~sj+tzOaFkNB7QJ3Q0**s4+VL%iR%
z0%i*mN{;NA)y<m*Z>UAs-Vxe*jtX8qKsiIs<Fr$wsd?nPh5^lKrBXQLyB{rRori{l
z8T8~jYL%wL9^NybG-gBYn<q>Mr@rX;U`5$1r`0DQ=Vd4DQVJBHI=|TkhxF{B<$<kg
zaUY+-^laTmX#u|1?RIeJgdkQ|QRCrd{FFs#a0I__TN?4IO9*wnMsBF#ue@vwUD^C}
zIHiLtf6@nT3Par~XXE#@*Cv;SK9dzql9wUOod&SI8T;s`m~i@=`N!491QTQl{E0Rd
zv^x~W8|_=HC2)&Vhdh1~rVSbtF%CvuAUXI^I2}Bmle#`MgY)D8#u}T)^udo<6~A~#
z-VMdPeq|6td^%U1vb^k<Gcj|iI<|=)J!fv9Q?4k#%XJJlFlzc5xyYRGLM_}<HM?&q
z!2zfNU3DI(uvRGa3uwX~I)-j#Jub=(1XWA@cxrGm)XDj_!;|Z*f7Mo^sCr^$eMSN&
zAF#Iz@&`X8)9{KFj0QS-TrxFr#p`WSs{?PzgLFmmYxrk0j$Ty#7<G$J2_;ev09ne=
ztRYQ@ZWVFu#*qd}asT9wr%i@Io*0CXBc(;fl8ll}vxXX7KNC6KFfKRtKVL)x5Ov}?
z^O4N$S?wN%_nvmrH=vp<mAi~4ULTron8CEHsaLnYV*R7zC71fe=N0i}-&_J^Yb<Lu
zTygwqruW8mG15d?V4WupoMk6z7P4-bACQesJ74ln0#;Z?o)n;qK%v}(8$Zf^ztMOT
zEZL=&Tw?Cba(9y#?vg9GFzTSaN{LSwIR<k)5z|w>?*#iqd;=uxwV^)N@}$ZX(lCHO
zXR0AZu+3ACu8N{(`s8<PkiQR)zj@*(RI$Gbh0M~Pe;L3_x{|si?yW*8EH33`91JUD
zP-Dw}7!BeN3qT;2uV(=6O)A>%Z9mf2narD$fGBzqn>US%0PNbr1mXGdt+f_##k(8;
z8Ni|uqJ!AeU~kJ(F7G(@L5l(m{aM|#!?=68fN}fcFlQn$=lt5enL0^KCMc+*tTh}P
zrB!RED&Yvw(oJZX%{ZQ;Umn`yfE3)cW)vb5vr7f~G{#fIO!>T-c4=k6CgNFS*SztJ
zNicl%Z1n}tn}ceAfK!v3Xw3@9-CJc9<2tQqY!aI%MNoyK9b7A}qKu$gWm4seY=%Yw
zMLJ9|ZA?j&Ac~<1<T|n5zg7Tm#fu-xP#CHejVX#rSug>(pFY_;iCau_H)%E<yHG<N
zRiP88x&{$YihnC=s8i|+zQk{Rv0)gx6w@)IN!58fuA}}v-F0hBFRtX#yG<97MyCby
zQDZCpnUqfeOoPO&j?Y!#!;`9Xn1&8)JwT$Kyo293!@qx&9e-p`G84+*##WTHoMk0I
zEpU->k--goBhbn&vGZe|61V@?P69BV!XcEuVQ@8z)T0&jYVm7qS^BJ{>o61T$?35<
zWkopeIFmc-Y;>tiBbCuMhA(1|(r1CL@K|KJ)=$}hVduN}n}_k8+0iyMJusD#!|h(e
zY4EEBLY9BMMqB0M<94C{=$zE)2~VV49bs=K!g$I$MCC$=4;`ff@j#M{fl|F<B3?E@
z!JQx+;;W-ihDS$5kb`Qn<anhw@rh+bE9!kjD{;fhoMS8<O1BA@_^J^D999@A!9N59
zg&z&71gu(aKJ!kgiv*=-tQcCB!B8X1Fgo_ooWi;e3+3QerYxp*W9|*ghjW6zQjqMW
zO6SL~somnJJlE7fAELC*u448Z5ED>_)%&)@0=bh^hjh-N1(+=moIwEin4Zp4Lr-)X
zd&Ra4tnHZO8(>>H(`&TB{>$hR1JtfXhsUa9iR8R2IVNYXBF~;uzIO?j*Og2y@Xey(
z)!{U|;ZJW)uir_*#3ckeZ1NKfd6@OD*5ohrpL|Bgz2UZf@y*~%C$E(H{W06X2qk}p
z*tqS*R{|2?p)&1Jq59J^pVdl$^GIORXf_QI*(Uxo9)tU{5}|A34RT6`Bk3h+Z_xJY
zOf%_y`Un|i5!h1BVLqTnK7F-0K2kJm4&qWr#a{+X6anz@$G?T%@;#qu=O{%hH&fyl
z&^}EmWoj97YUm*kxC7WEy%9x6Z>=yBW2EnC+~($8ywq7;B2OgWtd9nyAvicNTYqBK
zA|PYk5v6*{%@X4fLtk~#=QqO~)-CJH*?IQ7#W;fh4pxO(wc3X)Cnk_yuO*ypGeaVq
zm1$K3xKSR9w$}Q_;=&Rvxc*GEzxHQW6l*HN8cR_XbaWvfNVXay!CEKWnS(2PN!W`J
z?D+FJw8bG_Od<dBka+zmUob!@ws!BV9fNv<BZjS|F(l)g-dVJKE-wM@J%u?Q)=)x`
zB^#py&ag6hpW2VU6s)e;5+GsRJW+o8?bI9!;36J7BSNRNxR5x-AeSRNave3n52C;>
zL!Yj|_;pg4=)^O|KX5d^42Qbbgk&Wv@DImh8t2-@Om+rZ-?~r~My#xg&qnMcN;ghv
ziwk0jtFe5JH1TeHSBHrMnf8e|&%D<N;n(DObn@qVW+k~er>VEDt%{6h^f}yVmp1nC
zd^~Q;I158499vbjWYXPJC5g!<8R#`+===<TgUP`o+9ZAfc(6ZxTdX1{J2QqjF<Jjj
zj9j}@pG>Y-zEge7+F?=RR5n*7BgXD$w;yOvfy%GfY~&*85|o3W8T1~Ho@q&j&YgPR
zEk<cI$!{sd=|M~jE%_6QcYp615Ro$s;sgT(n50XvXK@VZxCpPLGZr1pXmm}fo>QbK
zAE20w8>ER0MGq4~cb$hqc{gx7jYId1Jzv@WpZ;vk|1SU8(&HADK^Jal1tjv5wSgFL
z`0=dFKnWSh<F&N|@;(f%R~KUxv+yIHjL7%!;ji%>n*A0DoZW5Xe6Dfq>P+C2z$xoM
zc2bWfpUNxeH6EB8QgY0cT6{E-V0NV-`|75F&JV)vuWR4Dn>EgwrkbrgQY|ra5U14*
z@OS_!3pcpj0n#rZoKJ2Pc5-}INo^>KtcHu@nu+_?Np%FiJW{7i<jZB-U=E`0*0{ee
z8XjWQ1f%vjaSKFtuJlCLv-l&5Ztv(GBcUXjp^H+CcHPaF?C<OVsxHtf;`|TfpnVw8
zv$4|Atx;|>_NuPGEK)R|BDh5cmH^j%mYUUQ+`k0V+_3>aUp4FC<sNHLsoO3(o3Ffg
zga>snPj|VaCb&Q>u8Y|;LjXl*3dvTn(!KMC=^ZU1hDXs)r$u>MWPw!KuxD6?$W&!u
zCn&7!4^%|mz~G8Ra}4ab@F%%#!LipwdWB4`3P*JH#4%T{?|%oZ_AvW(442UAJ0J<o
zWi&Wj@P*eX#;xFsaVb$1w7=nha=e#i-4M?2HgzPzIRaUPan8e8(4U7E8DkUl3f)kA
zUR;Yqx77NSr?*zFVHWhwb`c3{Ig{1j=E?Zwg_4&g^6K%tdZHH%Rd~g4{q?tO6}9K%
zkQ~nAtJE(Qss0B62*64^v0Mg;h{Rm@g3zc81;1h06d7vzRD<25M=Cv!BDj?h_tqi0
zREa9Z6*i&{71_D)c%2~>vA2!*<<x=9xQ{heBR>PX`gAo8Kk?1C7N-rNld`L^#LCjy
z(ED*na%qdNcqiDzBjTM3EP^_(z6K^yXpN*$DmAm1i*xMcM|}|P?+gxa?K+EiO!;{M
zo4KMvh}CDFv)CP3Bsn-R6;5N6t075{584sdaXtx`VGDU}okd8SwSsAGS7&V2^CZC~
z;l#{W6{0|x<w#=41j^u3W@nLslZUdacmSk{IAuKcy}Q|j_e7b)sNjmJXnSI(HXfkA
zGwemV1Y+52`9CweWTJ`K#XCt7D(g5ibFB5jc3Rr2ekWwdOwp2g3tBTjG5a#ox~rj2
zde>lQetvs7NmT%eq5MKxO>T#2aYPp;5+Cfxl4V6!?lPwbj}n!Q)JWPWO&^@e0}*2k
zJ8tq?romFuh?YcopIb=iex=LyDIe%M4bgP%IR47OLv>R{A<^E3(+LXb6__hvgOZ23
zzgl*R#n{nVBFn^>0%(Bv)IoKK5kJfdvYn1yV3i0u?u@a9e)Lt5M~c>MhpkJYn?09o
zu0^GR*I_u)k`uMxWfD;P`*%od4Sinba~fly7`Gj<kkt5y_d5=f?mG;z+r<N`7k}Dm
zg~yvRvEO#@UBeme$sFsG*i9mmdbiRu2m~}Ty6Q=KL&|m(B%t<}YXD2@>!z87IrkGY
zIpr%JjuW*L(P!X(ng(6Wuy1P^yZ4?V-yO)twuA!tVE$c3<OIW5`=99UQHW#-edX^Q
z4{DbWfH&jr2Rg+Sdv@{^Q@dSiM;mPLqT+UiulsLO2a7W6t|1~@z-<)p&;Vc`nD#M_
zpGUd%GAI4XJmAaHi2l2~@d3Hb?0AU5Cp%~2zDFe$N|?7Z>{D}u&fVSU%Gatf_OK+~
zW}<-ZMZ1cPZ_zFtS=)~*$BIbuHl~66;Z1*Vc#U=kVHy>vYV_Q=K1?eF1+CY4W_hj{
zfAU1W8vXzYB&PJ-NKOV9^NDLvu8IPjTEIBSpJB{5DmDhmm@!HO!P?i-Db7a#u>;f0
zN9~Wna6k4~o)(opkpl_WPv?VWLHSJwV}H)OjaVo6a!ZXvDsZzAY_OT`t69?a?#qvO
z6PXQ;)Q-KEB_KK5fHr1->ykI##8r#fa)8w`OW_W#q7I*11foDaElQ^bvJzV$sH-M1
z4fl!4uJawdLR*aCIw$EoG&Cj66!vP+QfO{DpOgdQ@4+rVG@~s|^$yW-D==B)AyQ2}
zLldYUfVp9wOI=HMYL?-kO5rIhUBqDXtc=-j;}SuOiv2$QIPMh8KVVy{fVQd#vJmym
zzMq0TbIcM@6K~h}L)cXLR$ze0JsD^ZtSVNQEEz`qy~wI(F9gA>+L@Y=k~U%ue1^_g
zTK`#p#)&c!DmJBJ0bhSQM(@Z(aS^7AW>-uNY8IJ6XS6(TSy&Fxv)s<G3_YijYATPZ
zY}=|n=tQl~z+-a11|<8r_IxGV{s75hw$DC7i8laLNBQEq)?-{X4W%HaJHU-bHKgs>
z3RY-MCUab8kvSV=l#E*f<sS8C2rV3|4WY6yMvNVa^H<u@f3;>`)$b*2*bIDp#8Xt@
z4FIM0dv2NPcqciHip)W;;63xfHI<I;qD^y?Mk8>-ZN0EajE*#RjT=Cr?aw4_OcB4E
zBUU2;z6kn(qjWr@yD|yF^*p@<8s<4e(!4hTMNnIJiE0D#1*xZ8c+X{6^fgT&L5{8M
zS4K-iQaySwJTcr5^CVX?;&`|<{@JBge+K?!?0ZSvdH4?rUiKfQP<1!EEcLm&w=^rM
z9J93w_oIFt8ZND&%MVMiERU)(W^a496JrxrG^Ia<0Qa%U6-{?ybu`PZKzftmn`r?u
z9g80V5?6AVZrqin7{R|Ztkx`#4ct$m$6qn*=~s{;=9F2sKN0BK);7KKbAVjneHm!b
zBJIz(DH4Pnl*`8cq(TsizV|f`5}Ye4Fmhf>0AAoYGV*WJr|p7^Tlo4}MSs=_%z)zv
zrvVr%`_eC)GSCELZO-!%f1$fjzT1??)Jyc|GgmhGp}i+xH!4t&`?`SD7)CdbPDHoo
ze494WS3z?xp8l%WwzVzw>E4JFEO|`Ia=s%=%y4(rk^GXcXde~87Gi<2u$INmr;IsI
zU8C`hf0tYm%HCLT6NCIRQFBH4b4=+m72(3A3DvFl1we_JVDwbqkvuNH1#O)!c*@z6
zLUmZ~2#CY{`v89fd^gIH;Zs@V^A8QD7=CIS>Ieqiy=LlA9IrR>-KKr%>%uT*6oESv
zNPqD$^IGv|pQG(30B=m(<A+Pmp`d#jC~|k7dVZ}O;KMHbyS}9}c=-4c`1wBsSlOm+
z2hDSgy@Q{rb*Kmym<}AEiA7hiDe`J3uuB#Y+XEy2|6Gn_CXYekg3&jM#QLk^B&=Ob
zJ^VE5#_taIxW155B%8c@Tjj(ij=BbfnR`fUW^HjS{&LYQWNZjKGAx;*lo-4lpW)U;
zzeMGIjs}~7FQk>6QFbp<0+Aa#?5KRH29^UVzBKP*$#OT;DSs{v7Qj?d8st-jQN0-+
z;-HrxqnNgIBGR{I?9^g8t>Z@A9h+nzu_Q2AhF5^b(n+WTF;qBMbe#?w<a0QU^cpsF
zj12J?O9mdqu)^fFe2FfGDC*`Hd1zEHtgYJ+fg163>roYr6<&QCo~*l|xCT~Xl*YhW
zWZcY+?wvX0ffSJM1`WyS$`DKp?j)fj<91m5;Z>z52E??`Sz=mS)`~Zz#@Kwx>RuPc
zB`VyW^ov=1^uodbU<kcUufJ8zvoaz+xL~od^tepku@LSI{!Y<>$IHcKrgK~vAH`^$
zeD>nk7s`JHth$WJ6mh6z#**W!Mj80r40EwYdw}qqqY6J<G$nxSI96*NDkLI!lkQt{
z3Fg8BzdBo1-gMoIQt}omsVj4_5K1Vq9It|Nqe`PK6(FlLNHeUiG4ejz=tyHX=Wzqy
zBb|Jzq^8l+13Is9J%+t>%CUXJOVbE9p$#g$RBnm7nd!nb9}1V&-to4#M5k6&_sn+n
zR3R~h3Tm<cguY62IH(@X5YA?qz~gc(u6>8!4{rP5=S#~k8=25F8DvX;G#v+xmkDMA
znb8+S^Gq<+S*~J;evj!Y1ua*&ZazlTm#C5<yzuYyBl%xkq=_2z_=TZc`(-`6z6C5(
zSV;xR&oXfsQ`JP|%437EGIea*>(@D<lSjHzyD_6wNg$%C7B(%TyU+0ByfvN%MOhBX
zM(KCqN&Lr)@b7U0`2JX<u!cX5uZJTMj+gQ_2NId!5VA$t{b(ARC!w}A=Vj@_^o_w>
zQwPXV%h_rNq|>7K92^<Sc4`vkCMwxlyp}+#d$<3g4Lu+2uo6>7ej;98i+F6`R+NI$
z)pdjPG9%FV)p=Odr&{|~0U<`=)A+TR%UpT&OfYxTG>whp4)vgG<57*gnl!A2Hb~m@
zjOkOO;+<7e`__$~(B%zR<igz-zTs>>ZcNay!iLY}03$H&<kUgxAzN#BKgxEIm`kPk
z08jiX4-tPDXU$GkC9IZ%@L_{I3F821)Rjow-^>g;bcW}mxaTrBSpttlzHe#DRqHp~
zjb(SaJ|foIx_7as$t(?eq-qey1y>NM$z?q75do`tQ%GymJc4p3ZYSRNVf{T$+}gfa
zdm&4D`LQ(R!PL+<=~d0x127v4fTQ4Re4!Jh4hh*(>S>~IXQcQe1nGhCn`V$RGZQ(0
zT1m&cs_?ffvPp)eo~o=WS4#R3o--$zK3I*aP#dZOq|w$)!M6k1W$blmQY@q8B6(6R
zam)s;u7D;=Q7)T2P%et_8fC*f!1)t_ym^0=WoZ=HKD(<hfaZ3mU+g&e9@qW&9!&6L
zT}#$rhAcdaD^BXO<5&}O2%=^fV<xe{6|y|*(`A!Xp&3}^lmPeEMFbZ=PU&L$TBi1v
zW#GSnggHAqH}c%IA>$7b%c(S2JkHwVp6tex6hfRw?`%|Xnsg<kmZMv5q#a0ZB;7JF
z=5(5g`4#^9khG>nnnPOZ5LXPZmy1)cCbx)n^Qt3O{c8viVOJ1JS^CAZiW~*+c_|SG
zqX997rN_$ZoPhZlP|(!{hTW1SSeoH^E7BqI3Jg@K_jY@S*fFF5yF2~HMg`>~^O|WG
z%1N_W<gW~KqRlF4pLzJ3WXTcm7KbBAx~hP<x2b%IB$?g}9qsUfF2LZ_Y+#>UJV-!^
z@xDSPSB)ND>fhqmup?Ep8Kom~XtOYSZ$~mtwZSL+O}2rfxt-!$`aY)K*eR6O!<sS`
zLk36?xDRx7tJ3_&z{C<DxHb@(Zo|)WMLUjJf{AMyXl{0VE_LB?8%&D^npp69D%~Hn
zHa6kX7MWrI>u4G&!_;`_VfNDBv1z-Q=f)R=Zg1*2xQ&&iespmhx=6S834Xu8!)~_l
z8cMmL@1j}>Fa(64$_LyUrIbCQxpB*|QiHg~w?DJkoLA|OBXkk1IL5)e_W9<rS$MN|
zDOj9SGW6k`gNv#QsOnXwZ>AJPv&U5+w`yQX3D(K|!=&4S5ej)~)kF6w^&gk_CxgC4
zaI5DBd_u4C{7B+)Wk%<wL3E=>&3kXW^A>=Vxhf}JscDpBpGOC409{~U<yZRi?Auw_
zKW&lYEk^SIAt+64V`zhO*;3#=K9`bV-du}~>xBd|c}qGbg;4=m-W{UuMx?hFNuiqa
zFj?3r1bhKpm6cd8rd+1f3ApMazV2wn@QhKl-MOorwZIQ&J17~!`9N!mD(0zGxhC)T
zvvj^O3j`wB1PVoaEAOE>uT5j$oK}6E*laMkdI>e!Ah-JpdaqA*1XS&6M{463WdwG`
zj4A(J?nX~nbn<X^mIz3b!TK9ay^`heUawiy?)Oe%Box6PlV%~m7I%ywu4sp0JuM6@
zQVxSk(=__@4xPTVp5KBiK+^}vEv<gHuh@BscF&5`^v6w3@O-9n5nKX$gtH|+0XD5&
zd@^@A&S3?h9<R}!;C@hR4xYWdZzm_1YCuD+?*KCVQ1<EwWFz+ivh~mw4Erx($53fP
zK!ngsWse_!yJPjc>dH>lXc1Nsk|}pUcN2$v*>3+NW94V$Pt20U+X0#2z=7a`0%Vtd
zqKpMJghY42hW_qK9tq$;Ff%{?nr80;S6^Q?LMZ8P>yn0f?cqpZxmn7^0MANabp%E$
z8a|-N?(U)$vFa#_!w*bmJC(uKJ?pq_3xBJL=Jc39BM4!CpXmP|5welTZd((IafSnd
ztdp15Ml*<uD_KCR@;IjCZU2<#Gekhy#81R+Q>>#Mhos(qjD$7Kkmp}H{5F%mFk<*@
z_e<xi7TIZD`)g^KUqhk}sUqrHMfLzn5x<6Lu%0GI$5B0za1(zUi^N8y9L*agY^Gd>
z6L`P0+I(6v`Oj`%(!jLgM@VlGDOT=Cih<pllUyl0pbTQ_Hb2b26FnPBRNaTsf|`8m
z@OeLmY3{%=x}LgAO`CK~u~gC81HJ0k+7*JGb5MHQc5`NKa9+T#W;A&DO7H(oZqM&}
zjYL~^@lqvlH|5(%*%6g+MusqmCK+HId{cZgbK}Ti+H-IronCGh1TzMQ@}^5)CG^pE
z10j97U3J&=GNWFR>ArLm@J>5ItAH=I(G{WjC1E+Suh#JVjesA)6(xMr>FX&+;4i#L
zazGgFkEq=a*?vj*k6}4GZJNYRJk0Ba4Oq+Nhkv?oqq59T()x1+4M-W2Jtun+pUYsl
zh0S+k=vm6E@As#j)^bUmK4qjtJqkCz6zvD@fGm|V&7A*Q)giyKo0d6-?(|~^3G7v{
zQ-N+hONR6kn)47b3YR|U`Yhlcht0fc<urr}svv}iT}DGsoI|^4&AeFJZ8NgCxc+9n
zMqL#g=UW$)ew^ZjWSKu5w&YDd&)ivSj2PC%S0rUy=hloU2`1{ugGM`WjB1ao$w<97
zQ;1$EjtYccg0aAru(KfMBhs%+-`_V-pZ&P3ml$+?+x_=iO!{9nkkYrr--MN%3`$}L
zNjZ&QN?cDB%Udaer1w?pr50#DX_3E01`{!`4*aL9dC05j#XE86Oe&4aVxw^1fMywh
zg*?W5hHXL84Q}#}ZAJGCS2qHO^=49w*p()J)yB)0tC+e}8bc37a4P)-37wTfS+VeT
z{co8aFprhApbzz@t*V>ADRJ{ka_uGD>497--!6=hWWRaXNq`4mKP-l0)p-EnQeVvl
zD6p)%>mi3V0&44tLdEL>|HBKS@D{Vqboqi6pw2ggK!p70Xd#@aKPB_wzX*5ZBygY&
zzvtbY=EqP3Zv8v3_NOf&v%{<zd^+gd{+x75mrzn#5Q3<Xqf~(Ex2-J<pb~svVsiQK
zmUe5VO0eYny~*a8r~wV-R1;kceiwnU&P0ROds~J9&1r{uEAZRASTgoH>5jh<dl&Ya
zG|w1|-ei58-dpOj|FjnJX8uGzo`=0|i1VaGEbsLAw<f=V`6f^f^}A1WTfGeO${k}w
zp<5xm2o1?(+r0Mu>I<|xHaTcfL0mtLZaPjDX$l#8vFY{peIBYeOaX}{MI_Wt!ROet
zX4<VbwJK<xbo~0YX;4R>Wu}pdg2GORW=n$<cmw5I0gM(N*GPzU;JWdJdY<_mdeGt;
z4#7L>Fr00{f|V6MLh+Q<o{Q={FG|y+pJEYW^b$>lGfGxN?95Gkpl}X<PYT}5oMRvu
z4*)4k&;mFG{c%6rh?O(Mcv;VTHM=0$UKyCyrzUTZF@7L(GZs`dXOn`0HkAq!NfY)m
z7BBoWxyXK?Ef84eR6!RH{}NlR75Bx3jIFBE(4U}|aZm^^Aj{}(B)o8P-YQ^B@H#Y9
zXKaeO7Z$SVUHV4HHMQySu$6YW=DmNF;jFfZA%l;<S~|JDNUE;Q?%DnCf>j4`D$M$6
zQfB0S)xZxDctD|$HNY~oiX8yM6(cK|{-wNnV*ww&CPzEl3wo@EP6m`0SewP#>^1Kd
zVLRpMJWR*hho{#c#|poeBZu0hN+If#y7=(klOI%=z1rl6(mk**wEZ}~swDkC_Ir7|
zCGicl$Ok!Th8QL=NpygMi7La06PeYq&tP)+R+lOpCJ8*^#Ck$3m(W{c?A;Jwuj4&n
zZZXGEa6dcWSS4M|<ddwLLrae^_iWD=@OL17|Kc~s2huu?-;b~`mfkj@Trq4MYwnlO
z*D=>bNVWKix3=~5Vf9Y-b-|v4NaSKsna6Y9zNi0ovT0j2nNd)rqUB|1@;LT6>Eocj
z3f)40NH58_E*diSu$=I_e!M&(!@xC1xfwwUhl^8f6z}TO{C-g`#a+<ZER(R?pHfWj
zrSSY-&kf{*w;CT}P5_xhG)cs6C;^4K;_i1$<tjE~3mru(32IM7m%d9RNFTUlaO$A#
zT{|I6o+aSwXC1qRgV{)YV#XfeXfi+$sQqd3<4a<BR+!3~-mD;)6Db#;3AeuDsS?Q*
z4hSi}DAO}xo_Rtbo$hu^f8IVhmn20!V=Da*4F5>>o?<Vq>VJ?8m4FVTFLbwFt1awK
zNlTKo_-_5(eg3AUrQAMF9g%?`H7J%BvDbi`A&-2$ef2Dy03ysh$j^s?cH);Tc8Kcj
z8OBxY+jN;!XT{L@S7A_qf`VGV(q1a(%%K(2kJqQ;!qcetqYPGJ&y}%Pu1KR_SSW<z
z1g_^=r!*vSr3GTyAd@v60l4;j;Y(GQyl=}4EP}5UmwWNjL=->r9HAD*;*IA+US?E;
z6#z(IfDE0iho1OJI(fUD0SGa>JlefbD`4)SVLw^lmqT^!v9glC9lP-?6YrB!@M`wx
z9bZXCBPP2M)Y6sZQEPyG_I^m|S5{TyAknN*K?BU2)EKBj=!d-HaUW}iM{MPyu<NS&
zC$!bbg9d+Hw9^X4Q|1%)e0c7&Dr-k#vcTSC74x(jORe?fbzZ33bEgN6PV_f7KrE+K
z&79q=m7Cp5<;Pc^C!%khsFk(9qnM5xiL{ul`Q_T?8=oB@NONnJjUCOYxdTTygy4^@
z)Co$pN(;Vl4c~H@Y-rq<3C$K0iHIr>1uX^i40FHG;EM6%th*E%$D3!BavZ6{4qMVP
zt32wIUZ0B+D&}MflA{%+5zmd=j@AC=J$@ht{63;q{ScO71JO+vCa#`RIc00stxFT3
z1WXn=e4=7Z^!Z1gx-U)29jOLOQdyk5lytxd7>_G+IiX-3|H-yxzRTlWeWoui8ZseM
z|0BUp8~Ew+@Np~gtDl*|j4@0eJwX3c*uHD~BVGyz;&pI$D6>g^(#I?wHshlF<uF7J
z_$8@($fGCm%`OfjBVXCYg-=o+>Mwic9tHJ4>?LQER1Ult4fDgS0^y$_cFXY_A6c!G
zS~?_>Jn^|*t_3o}st8!xqRN!&D3(PGiDU@e2Lfi$Ki8E$dO&w@+<I@-irMwR!xEHo
zD=M;WFPgSpGLl<qK?|Xk{kWey9Y5`_??q}2{X>UdFU(4T#J4NX?TK0JruHo4T-cu7
zW;GSugdQ|`>zb>=u4LOo;{~^WR{o3>8xGyk;Yy_j;KNbodvs&D^Zv>25D7KYVbCG~
z3p?J9?vq%;c>c7=L&->JEX+D#{R7?zX9ryvLSvW$riM|i9@B9&^o_nSJ{G&d2(YB>
z=#fN#2+BEjpHGq+?k7b1pk6nuz^`iBNr7aApqr+!g^}_iynX2FP{+gtoV1I+D}Wad
zs^wFEPE0g@70$h)?t6;R@B-IQIk|sYk)fbcbIs@WcKq_|F^3PSs`iR~PkDgWb@xP&
z`p>!%0%x#xapH;WobxFmxht-*8&94+(tG4%#e*HU(vW27&fTOBr}xepe!p=(1Is`S
zESjD_1$ZzBVJFH3mBbmd7L44Obhs`}n-3ihv$Ljaa`;Gi`4j!!rJn0CL!9Tz^?2f1
zr^v##jBazTxE<JDSU8N0rA|j5nl}@md%xK{`foW~Hb&o>mZec*)`n1|7q8710Gfnl
zL`@}9hv$RX2MpsNZ1H<mJ^Say!?VjC*ho)hFV{mS`4rau)_$K89|tA=ovl0uqn|l_
zth+n0ZQQqfn~oX@R8CyMS+r)c`|qxtnjhxvlh3&atX)$!5VKMgv<lp)t$5w36hMgn
z&xnCotc~tYaXV@H_3CH{-GY_wWWtk^q~~a%q#IKkqv!B}VJrQKQHqrOV1mpYQ&lCk
z%$T|>JEOb=0><s{#H(~k-p3lE{iAP<g?UEXE+?shpYIs+$ii<-bs7pOq6fg7{&3Y2
z`59;x88#Aqel7?BI4z&LG;yM-pj*j&<RDpf8)Q4pM1=owLrz<LO<?!RJJRr>T<6V0
zK<f_qbhKNJ&n8pqEAn^a#JcJU5DKFv0R(o<^{$f?=`3n_?)KoFZ8%<io}f;oJ21su
z{Q~zScQh{tO;4DwVW;kURXt^yI~!L;xQKveZHI4~hMFk0(y<RO(0tdWS|O$oYt8<{
z;GPP47vw>^sWtbcTI)AibW^Yjl&>RP=n$a7S&rFpyYZh*rp29?n>Q(Rx(2bKoSKx^
zzmcyqnlD7gdHe0gXX^Z_tx=Al;qJ1!)bVPNl85Ib4|HwQT%I;JG9?;!%~mFEYM>{}
zqS)zf461(kd)&Wp-X=^r(1S1zB4aJ7L3HK4EPNAm^z#6B08Rkw1#VvKbK;(vN(<^6
z3Q%uGHjGA}q0Rvi&BFgBeFc;c0_;qtm}+V6z0VfQ0xROOvqFo7Vy=qkWt)`8^AyUn
z9P8r7hS<?BO`H5uTl1}c&tNOD!e4k9WPkp1d@n>eeb<NpUM0c~3|u6+7MezOd==^3
zEHZ=GAn6cS9#3$C=Ja<t`e18%ixY?zo2DhMb*R{}b7bHmfip@Zl1)dgd43~@-%mm{
z3HM``+l&XEgusHKb)u~tj}ELVSWk}d{^JcFYd(igJqufxAZo1$Gf;1Buw@qRB4d<Q
z%s1^1A}e|f5E+4zX?Vgm-SITbj@b@?{J<f=aILf1!C7cRm&KDG2_<|v&%!V9lkcY1
zX>7}lJTdB~9po#&&5GEC3O8KI*-=hkMh91!2W)506In?X-R)5FalF80-#CM<zo;><
zXWPWhg``HX9Kld7(7_{S1FeU5F+2TQBej?{`~FB9-;~tGYf2)0cuLKg>sAUq;RtEV
zrPg#e=l^{pAHvM}Y~qE8T!)iav{>iL+gx4B6SrXNOj9@8c>HDMcXH<&xRvs3aBCGg
zLBUIrQ(bsj&AwSP_KL2V>mhJJ7S4G5Ru2Ta)Y6%?q@rRnp*2gMKfOW*Zf?<Z*+%6p
zevBd8lt_~7flCmK?`F7*`WTeLffz_F8GXBs41Yr<6N%d(K^%>}udvH8FAK#u;DodQ
zamOZqiqj6D`2{GJhdd6}0Kt#p=F&n=C1jaGNSq(2@5J{e4y4tUv6<Qy`g`1lF7z~r
zFd`m+nyU*W{^vkeBYF_rh}Yo2z(3+R=JEIGFUmGv;<>Y#nL4CC-hGlqt1h^`>JL8F
zb(OImn}B_Gst3hIr9n}0gxzVR`XtfsDLUUyoHsFJ?4?1-WX!%~;RD6r(X^BdJuP{@
zIpAzTfPUZ34t^HUek~;;VS%-)C<((^BCrQZqj!Q;b7B;bEEE%OI+>ZQ9zEzNV!RyC
zX*4{d=;2VBfwbWV#FJcf^LD1?6%qpr2_+#f0%Zg{%WpIgmEBTV9(dMlPXihC^nd|D
zxB0p7L>IziXHl9liz=;uA2>ocmL}@IWYoKrbNKPLM5q%&c?b!O-|(Yt<(f8&hjhG1
zV`|tDbnJ5`xs_aN!#emAw=<*!AU6$9@c((X`=j-zA~C86DnyqX5&qF<2|zouAJKN!
zQ?cEX_%j}F%TKaYxCjTK4;GTkGE8>&Mui+o(d3OsKAlL@hjNHssdD%p85rAGDnf5-
zVqE&^UGpt?GNRU907xbC(|Q*S#IhmX?~*SPt}EJB%hw|~vNv_*_rHHt$h*;4K`15+
zYVjlNgMTy6MAO5TpL6OMF7!21_RlcL!vWFU86Ps%@AXD&mxyAYW*biX4zSI5ntS4J
zT?sea{VQc>^z$@i)rTV37wjp^k6lz?)LXPBh{}?JI2nOuj~OktF+Pf?-lzmLrHSim
zk_r3<J`o_XevoXO0tp+$i5XF_sF$G|`+n^0mIbewsQ~gq%NN1}k)Xclx_NHd*%<a5
z5;HV;Nzp#SmuD2^s;VEcPloa}uA{x<0R_&zxLaG<>QOK7eRPt^%FtkQ{~&-m`bkZ<
z5;Jx_No*dyADf%dZ70oz8U=OuT46(w_h2ry2BEru$IVY)s&FzeQe@qLX8Be3X*&Ic
zkTIT$D%?Vl*P~r7ll+Ewmi{U|5z^BINzk%7ZY0q!RagZe*DTP6h>pRI#80nc2q5$0
zJAgwGhI5u4P{=!eC%^*osRleoC}2V$n7m4Z4~X5speW|ww{E<@tsC(;71>*43U2TC
zpoN9C(`yCy@NyV$DlHt=rYfLz-Ijj}4Q#n3D7&;yhEM~*i4nUUfX32(n_HCOf{PoI
z$Ek=jNLSN!XXM%o*aP2%d|-A?bb{+Cnu?+Wy351gau+FQaJ1QIV{E>8>=l03?M{zJ
zg*#T;A5QTnI<6>I-<ou2N$*imnwu}1*SIeCuU_l}S(C^O+Hzw5q5@VH^bd%l5+9Zj
zYBs)m-p!mrdycie3l?=ZNR(9EruB|H3Bah)CbG-gRW0mD_gOJe;U91i=SX4-Q{84(
zwhKa*B=A?<Df!511XT=bCp@j-nWCCtYThjb!{A=2=Tp;e7n+H&oFw1CB7!W9@dl+P
z`OWf@w~iAqR0Dj$6F6-BIv1Ta=d2%Y)!9_<a52vyVYjoOrZozeS{N#tv}rA18dcWP
zr-`>X`mR*=6z!2Ky@<Q`ol8rLX4tYs*M6%`u0ok#b)lksfy2qbtCKdkMa(#6gB}gE
z`VHbo@LkK#Y%>eJ{a5<xFvI%x0U7(#Ia+U(^0bQOUBQX%<sVrm?OGw>s3+I>4|8w_
zIyyBew7)SKZDUA^o?z99OnsMI8gft=lMrzfJtTi-<z8Q{m{Zn!P9LVoUW*Y05PHhJ
zG1dXb5k!>Dfy)j-{rHg?BWb$<g_xNL`rYcFQsJpi<r7FrTsoAs@-m4Y{fpvUsR^bk
z+0OYs2)T8fGqC_DP!@SXV`yhJ82H+rTWXe>rA<q9$8XWn*M;ZLzhO?j{97>AYMHAG
zmRK|73G{Je+I)Z(l;MyIaC4uK?XUMC<J6mR1sL6R-%+zk*6~_s-T0rgeAA|o!)?`!
zd~j_?!LiW^-CK)hW<}%1bZu5UFc+C=5!u8*f6WQpEX&Y|jGuaXojbT2{QX}$ToPy-
z+fsjr2ISV^ibgZ~vRjiHmRY1+(ipO$OCOV*2aY2J)3`ZtKdfECpOtDZu^E-{8A^*U
z*uA5VS#RXIP#uvuq|!K*zn*JgS8&&YPK}*uq*lheve({JU<NvF=K95K0`El#9wyY5
z!0)}QKSZ3|;sTob6MDp)@5I)hS$mSQm$9<?*DBgZ-TD;Tskv<tmBM}l;!}36>>Y$I
zewiRz%o@i8Fc5odb~-A-0n|w?a?;Nf9tyNv{xSKbM>DPAp2`b?77E595-FVZ^$ugd
z39|#zfhNjhD!~Qii4%-=Ndaxu*fVW_umtK<bN;_d68oqb*XW%C`S{)Ia!^m)!}zp{
z9s=6W_H|*Dw2X{$Ppsl{Ql(>&=rsKo*=LTvzyw4r2-#vR&Y}X^U5UP*M(}646R(=*
z9`^UvG?*)yhq%{5{n$t@rp9XY3RZSM;{ksJfcqbRX}8m(8hYcfWPpyTnayET4san|
z3I83N=;Fl`WumBUkc0ckOD5{4Kr@+Fd8LB^3p0E0^GAnRBgxr;lHSxy0k&Po7UaG*
z<<&mBD)B$$oh@-%EW2Mrz;`?FRsIcJ#&0!ob0^RHgw;w2?G{HU%e=82gH-h>EM2=@
zLQpg?GGa;CRYQm9w_bC5Vh?OFTAE+@R_R(&_1$?d*xuKRD8sA$W@qRw^qU7K5{9tf
z_UC_&T~5O;vF1@ZT3w=2xzps|$xb`Gd#Jh~A*9)ZYxJ^#@ZoeD0KCfn6q-V+QPAxI
zs00~@g-}%bqsqe>B&&x8c2*#NC#tf88e33cY&2;0>p`LGn%RLtwQzJd3PeTfr5x8y
z4>8oHxZU11O&&}w7fkIfEB?1D@T6R4f$W{YPzm*e)Vy1Mjsyjhj!d@Q&g1A>zURB+
z+5gK-MrGRs&jL^oS?Fn(=A9n=*Eys7s^2p)J+X8&5V|Me<H^ZL`_HHD0bSJIV)~kW
zgVwz;c+_Zeb?7`hS-PO)R^D#ud&pFmdLTt|KD6+$jxQ7rBo@5p7t@4Y2IBS`osGN*
z4t&P8*N0~uWcxd(mFr=_Z{RO?Li06U3=~qKZX@K9p(MT3hJZULorvTM^5?t>hZ^;_
zGI>ICh~<$n_9zC7|65)Pl8nTUiO^C0Kzs#)l2n+<EZAv*@8VS`#NuPOM^{yj?_)!>
z!1;5->E1bQqIO1}34#K44s}Oh2<^CD`ATVS3W$C&US}X+Ts__VVk?1BseyEu+0Mua
z#RdHUl-ea%B|xIZr<Je-Gp#_09u~jx!QxVnFwb!X%~`|iJH6%z!>D?~hd{CfZI}O5
zMkRk2<>=Yf<=<45!vkPpB8`y@qo-zg3;+LQ+&EC$1EPtMNGDu9&ALE>O^vixPo3DN
zS57N=RRSs?FX;%<!{mW0(a_L1fVU|L&2VGH&||SCpbdq=N4ZI0l;&?1^{6X!u1<`)
z<nkdL9Tccm3=-vtq;Jc^L1~NwvlK{^O%`H?-slopfW!u)0!M(WMGy8*<0sPCEck*R
z+14&+?o=|<*gv(vm{~sRYvQ)sd-N7CfMqBU6}81@Q~)jpS!qR1;%ap3zaM)EHEco9
zZSz2!n%7R%%&-JZ!e^LPR}h<Kxc$4cbuJI%>!uCSHP$?Tj-jmn^BRs->M`g;94K08
zY?tWR9|ZHCkL(uvV<htoK1AV!1^U{>w4An!YWA#hFSD!GoTb{`$8fP##U_6gh`j@v
z8o4l@DPyO86p#?7YoK{Cn9&^0boVD$d`(yhs(P}7we15?4@>$RKO|#-?GsOx|4@%A
zz+1KM?z#cnJX`oG?ryne&*h3WsO9;Y_<TnxH?_8jG)}E=(=*0_K<D7clZR)Br6`qW
zUz(dGkjd<&36kfs%Sq5yRt3}?SGZR@OVsEEAK;$Z)c3bj%to}SdF-7pGz70f2mJm%
o(i_Gw6U2c)c7lC_#fGWPcgqpwq&0!3qD``+3x%7uh@-(4jWbIM-~a#s

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_register_map.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_shared_register_map.v
new file mode 100644
index 0000000000000000000000000000000000000000..1aba8be887e2bd63e8ae8abb8ec466479eeae133
GIT binary patch
literal 100400
zcmV(lK=i+h6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxC5pxDS<YIDtf4=?4!
z0^AQ<KbU0r_CdxtEN=NNi%%nPC2XVS$cJYZS97^9V@rJ7O;1ea8X9r&qSD5j;)RD_
z6Qy)z1Bto8P`d1=F_lefH4PC$uB&6C%bB(FIu|Xx=7vozho^r$;OW`G?m_zP2t;bB
zd#Ot-80SMZ{q>|LZ4;d=WZ`XH5oEW!jhUrTmbyi{i5`}f9JHXR%kgwRJAWEojK!Wx
zcGUY3JQfgJOmL-FciwBltGcsAai+7R(>z}GazW;m{B`h--SZ%0=N3b3*e>JG>}?hz
zL-;K4qWofRgP?m{4lY)RWkk3ky%0Eid-jKA@6o4l&5^}hVtiVyC(#;Csb&Kt+j`QD
zh?Me(fWH2LxT57YlWxwC=NJdh);Zss#9L!dBDtf42MLYFsvHRWgls>rpTBHJ2OP6P
z@=AkDLq`NFqA<w>X1Pbkh8W=40PgC$jd}SHdTHR5{SntIl{{a{?y-$uE`&3;sKF*d
z_T|C#PTpnvP693^OG>u)z1&hiZ&gqmix5ghdb;vwtY#{FW!qNCzwgBFR2|tzxK$Jl
zYhuO~ic+EvwG*wY6v^5RK+bTY*m#L%&<Kuv9TvzgG}XjZdCSM?!2Rzn2Tig5t_r|Q
zWJ1_`?D<heTLy6(sRN`JfFMNgPW+_`QCR*MyP2}bK`WgUG@h(RedFm(FwuOo<Ux}0
z1##bDf=A1DHk?3=$jXe;S&L8(ns*n@!$829QiJ$!aNVeK&e@7-Jghgb8I)<k*Z5q~
zJb}&t00yxzB*h%ZAGji|ElWLyU~G1;Quz$jxhG@XqH*a9B)S~a3VM|s%5{g%E;CeX
z-(r&?AK;zd5)2T<L?BI5vt`NWj)ooI>Xz>9TmNl$m1h{!d;W_vtJ+1a>8UpvM#j3p
zpfGc<gqDN!T{b<2_h@g%pxI6#DANffNIQew2{^1`<$6iops0@Zq(?urVKPDndKa<)
zYIo7|Q~dk|mJz=`d!DOeQPN0Hfa$KupnMSBil(v+n8}T;z#eN82sJ-ZpR;ZlI-Z&y
zj{cFJ;4wtQpoTb69gHWA!#P2@bxGvinmbEkg_|-`dms~Cm@pf6Y?cp1kdkfL4jNz_
z?T0nl`pBhlnR~;O4`jO2wBaneil3;~h~dR^CKKs;#5*L7W6Z=Ye2HXO9!&fVo#{B4
zpJhV{&U(#U>V`n=>OB>*b*rK2TU&yXaR6#MQ*!+XOQiZJ$t9DK`rZ5#7&H5{#pwlw
zb&WA%TLn=$Ne9t^*e!=FINgU7JrHjSX6MBidPy?naJ=jMdz+{_8mKDA$IBv+&6gN9
z%Rv_s96$3-5qQa7pu|<t#%YS;*$Qvcvc7{i5_3$f*b~=MZA%=%$P8%svK48cKKn^+
zNVUsyloxiZI<W@Ca#BzhBT*?EG8N2p7tEh4$mmmboIXOM{tvej(0-K1)SX6Eb(+4b
zw7}cQY}lXTdf#$izl!p1j45ga2);<V;TYq0{Fx{kEQrp@fM~&vKH|>6Qby7MZ1uHs
z5G|n;hr+AbR$bOw{BC8wo3>qKd*X6{KVP*T3_;%6KU(u!tHpUSH^snu_r0~C0`p|I
zJf~WB@!7BTy7bBQQnFY@5d1Cw@6Shg1~^fH;87B%f9446-ep@1CzakQW}>jhb5mli
ztSfq(`*`z^#xpyQ$%rOJxbkxOIis)?!GvaARfx(pKOCFNOl5zC;D`WVtg5Vi5?Ui(
zYxZJHv7mB2d%;`DUU=!Q=~F_0Mstklghzqq2)faYc>8E-E!tU7z8BOqJf#Kqr{&t=
z`=%51XW8Yz>Ku^7A2b^3nAMm<N@4$;%}Xu2Q!!m(#XK8xm~Zj`+b$e<-ub?kG@uB8
zaj<o#cUlOUnms4I>pLFqP1L4RA?1}$T~0T8$C)f^k0~^Zl2nm%FU*rEx2Cz36~^4G
z!3@>l?wo0qMTPWhTA~{PmtVO*=DRq$PbwG&OlDlrZA|ot)Tluw5r^qJV+lRv$HOvs
z-1xLc!HNch9($qjYem?5&OLr?TH9k(*Dc%VvK!O6c3VgY%~_-zsnk9ffw~)^4Q-2}
z!dF5mAiS;q_ZeK<kxH-{SvE%MYcenImHoDvdc2XLDprApvWb+;07T;`EBBYRhLPA~
zS`XiT{9!G+>jrQ)lWS}>AD?oLIY*u!pZIQw3z771Yf)@}qf#C$@CQ2WB+bdnnK_)h
znoDD!{=RkYr|(PG%`gC7`RHQVUl59dqw!Ma#7F&AG{8<#J^EXfAX$huM?QI4uGMfG
zivpveH_S`k-cq#P%}8Z?iNx4q9?`<P9x~YN)^SR*{Lg$2bxNHmhc5Lh#sc@sao$06
z+>mwg8GTrUcCZ<yIHLi#3CUS#K8BnY9Q^#xTS^V-!38XbMb6rICm1=~@4M-FXn#M7
zT`!jxP*5>^VNHe!^0_Vvk~-3`Xn!`6MYVbA*Nv8u#Kh;PPa1VuDUx>H)L?WV9}7_3
zZW_&bqNDOMg7HmNUY4<=;P~@dMaHC_WipK`YI&b8r^Jte#AK#gB((s*Vc1@aWE1LM
zK=4G}lqMZDGv#{4Y4iEfVPf<nD6Wn;J3fgm_Y$&7U9&C-PDG|LO&$qzsI#%cF1j^x
z9vUEizRmW?@DK^hgzSh_sd@^0UXj)h*^QBY;N}9~jru-*^Ql!w{gOmNgmrQ`^2;#C
zvJtYkv&BHmRKVf}9Ut$XQo!bFzoGYC;3GAA+%$6~mv8UEXoZj^!8A1)6XiR=I5h>L
zT<)`qPW0oZ-$W2Ao0+>kg@{btwHNaA!cC~Bz`Pi*`)z|_p;-}NzucKGcW@2)dosta
z%s-2#5P{--NFRW!D0uz`*ZG)#_33Znol<slc{DbI0}kL^pch!U%KH2{ZjN4eEKOc%
zJWaN;dFt+e3}avhKOAfXMve;lB8z={k|y-d2RuQ&fnHgx+A(oThe4Ka7Y+QlZ#)Fz
z&9(JS!)W4VNk%j4Dt)f0{HilCtspkRiFMg_V*r!0B|sy5x}`)Fq2oG(tU%Gls?J~R
z*sqmgVWqa>9|94<)Z32H5wg#A$RkpGe24>W<rIILC)ik@T&G;0hc{35+7&wjm_BIt
z(2PGfINe!<lTcB=fiFoKK!1Gb2rVji283TD`SU86xSsYatd}Q5xJ!XI9pOMX)x<n%
zZjjcmq=Dn;x30nV>RLdq<#Vx*W0}mjb6ErTNA=SR6(}B$5rS1TluzozAcs<`zT1!~
zdgoi(Mqn~j{^JF;0|`z?aqFl7^kp=VGb+06sbpygcJ@sY_k`F|W9!}40n;QDn-yaG
z_qcwOB{g-U0Dj{1`+YByj%UVurv&6^MVje^yd3Nk7Emk6RK~TeSU(&*66<D-Z-c#R
zDMK{H)h)89!3;<Qe2a#tDp_~RHgkQ<E3wh$qq<Skvjf&vf_EC)&YYYevSe@4B~h~f
zILU;Z8*X{V1hWP|$`K_mU{5DGl=WnY=k9v4wNeFvx|>b-WQ|WX0Y4c9sJJ*<R-#wi
zd6E<zv`sf2G#TC-?q-gQ?{RIJ)n87fZPEE&5&+<BN_jMc=DBc71;{%DS%EPd+yh%<
z6&zb0g>ji>qUSIS$qLfQL&lJ*qn2{Ya+{z){o7P$DOYv$#K=%Ip9WjD2aXnxjOpSM
zRcl+4UhA4;^ix3OJ}h&>K~`lap>HUVJaimX!_4X+suxM&$>2+Bp+Al^*r-RP5#i$R
z(?Ta{Lq83FO=K6b9&8!gicc~@FBkiBQVCO>z!L~#FQ!c1JIS7PZUO!01Gn63A`cU~
zoa-q0mPU265xOvoQfv@D+4g`;53o&En+iPc<wuLLcs{WH_Hc;0djk_*$=(oX!Z_~{
zS0arkbypku_E#`Srsvq7l<-#)0#Xd*8XaGD7*E}Yt4GONJ<Kw@9;apbF~QKzYw!EV
zA8eL1aUr9bu>{-xY#5<*%y6n#Dh_9*&Z6}+%{9O=K=Fd0YA3EbPXp0+GW&jJQ#zP3
z0qeCGLC84v;J2Pxw;GHO_s-sOvKgvo@MsHXJ2Php0aryj9#6@(ab{u-z4G-}Os6kY
z64Dpi+&`ms?uSGoyFu(DRmG37D&hz%DoDq>sdI{G;~`OLls%(pH?~UPLMO?xOwnz{
z_C%w%0SLv2SlT%;u0hu6vq{br8|J;Sev}sNYju6p%3%s{<qhvc9_zxko4H`OB*sh(
z`Y-R-$II@2DZ7^f+Tlsh6O%q>@>Ep~?ayrCB1j`Gw5fkV9kszzCyMJK%5A>VOK!*t
zMI@w_<a8i4E-ce8VUC_cu?hDtrZHYUKb$nqy3AZ-@b>py6FaGFI7<Hcb-_?80*u=O
z6`tA~l+44nvuc42)G|i@v}NMUiMuw~oh}Sd(NS@&7m!Sh1j-t0Qi{;l@&C4fIhpiy
z2Ha6d{TfhdQkPc%=;Fn`3f`!g^DtCuQIvkxR#CXgv`xD2e;#_#3Xvp{A%6fhDOyJ#
z{LbK%P0{N8xtMWzn;BtmD%gsyM0SYJmZXAC);)j~{odd6*AI3RoMgNDG&u$pCY`O8
zj?4At6|E)v0j+atc~jFE0WTK^8AiWp7yJ+-Fu0S)WwkOUb_=D|FFlM=l^LVREYlYH
zEtRQ973E_HZ}`dxI<9#%-sV{HW#_d<_Hx>o&yf4uyAsyR(L6Gdl`nYPd1CRhr=>Wd
ztIaFN=SLmvQ6CCAFE)3rvDIC#fwLg61flNd=GbxF?VfN;^NVe`XGI&nG5x$-g#+99
zLeZF_p1+b!!QjAf{fq;EzEKMb`|YHKZubZB+{9=_u_i%-de#>-cwpCJ#5Wu;%OU$r
zk@F+ZuKUeMjA->I#vgB~vRoSZ8voO+NIu+N(hj>>KGoFQ)PhD-Z^S}<Ps%}tznH0Z
zd0c?exh3X9O=|CK$R-@7SGv@sCb5euE3&odAzE%?Cu|!CQc;JD&y8%mNXR5kAv-&=
z6Ho~(%pyryP#R|5`xB1To;aT?kC+wTs?SU$xt2y#j-o#Oyn2UjFW;f5!Z6KaA(-Qc
z)VGa`Y7S7YH&n+1QXp@Uuezb8h7@HuK8){9Z*5lyuE?Z5dD0m&)@?&~2S4?*K@Lbg
z?}Embv!~@|x0D3;u#kiY*6JE1#ep32K2O74wQt1ZR3q><oj~>^)^osXsY*>GpL~ZP
z^8e4nx{p~roteT0g&gWgZ0@xdo;$}B)(RN7740p#+B-*hl8j1a)d;=+NN;U|)E&q$
z`)ZQ@Ha#}t4%)>=tREj$^1U@!eS+$&jwC;?TW=8*9V4i$-OjE=*^it8+crdwxfxf!
zJNaU%t2};kZa(Y|X&}*{wK0c;P@L|G381ce<z-mf!3zI{#6#&)^7i}+9p@6#OW!z%
z7WGh}ay4<=E?vtvQd2{toM*!Bt<Z4#JB(cD0!^wTk(!uHYy2BH0wL(wT}J69y8XTa
zB+FiNH=0^2Kr~;UcSR_CeH&Ig&Ry#Nd)&k_lPIq_H~pTwlF!9~i(73H1M4k2<+1xt
z!lJ(rjCt~lq=u5EdXV+6&xV=%{Q4dy&%+p05q2jt+caWNpCl37fQM2*`s|YyXmJGQ
zOccK;Di6WaM%~_rhh1?WhGNlT@M2_iQhCwj^sBma$EbU*>B`%^=jxUg*!7N{R~Yzf
zQP8D*H3j972JUg*x!2pnbwO6FDzKT8#&Lu7vY4+$Bkc2!5LvG{rbo_|W`q%vi6#2P
zb-l=8oKH;49HU*qKE~*9{(#iNvaWhBz<8!Z@Z5|q{5Ha(7ES-=Rn(w`vhP~1C<>4n
z@N@c0Xu=oz%g?e3pGx7eVHM}z>UhuzbG_LPt^O@robEl~<Z=S`4}r5Pn5o1u`o3b!
zn|`#NJL3CLrY(Wfciv1?#q}qkm(rtt5xO}|Om1?GjP=0IrujJ3KXO{CGvg-wRh!~V
zrE=Pxg0L8*ocrfZrM-I;vqs;gzB6(ZU+R@p&3D~k2L;j$?+UH+Vd!q@%&AL%NFx6y
z)J}+}CK07t<7@|}qYXEV0O;Lc=FKi1oKyybQsckZ*1d>gIATqiISG1ixQ*SgdA}D*
zUz$f73`Y@%xGi#@2e%Aj(2<uN#Inczb8qR4VNbcL1f#)&*Hv}}4*-wc_7kh68;9Vk
zhqMO2N)&zvrUChfrNh>mWE0y&Xz7lR>|PRT+rtU9_V6GK8&HVMr7KMz^PSd%{mlvS
z1f(3o$7ANYI?xYxF^41Xr4n-&w#}n!e=%@(LMVQq5K|`axy5_!kx?RQurEah@6y$)
zm!383NNJzDR?y^g|F$EPj0>7xW@g^Lr+AntaJr}ggPF#VprO4y+Z{4g!6LH9P7Aqh
z9Bp1Q(j!{kgnjNgTKc3Bl-Rb=Q=3zZ4wS8Q`<aF0cHkGs<a_>|5KJF`PzuIe>ye67
ztAjgK#eZlL%R+!@a71k-Oz)ar2zf(=#^e{dgX=1iOF<7q#h5`0N^Y@}<qW<kX_9l(
z6Nb1XOmDmZAcqi}raoY0WOt+YN`77G#6tr}n^Cc%3gqI0>`d|zVc+cPnkX^~l=sO7
z>(bGb7eP8@+Xs8GX>iBPTHkxsIX|T?MIz^D$5?2{Fr$tM^AC2hq&z>076+I7)M;t?
zGfFH08ISYE;J#;?SZtZHBywNu!4<Q@m=a*BhhFeKZs|#2V))0M8GOLb%E>QHY$Wt;
zzB*QmVq}5H5vpOVHt`{PD_v;IkUPGWl`E)wzC;$-_Z3m34!9-dhze7diLsFST6g76
z$(agDLT~TpT&kk9kWqNuUL5%Gtw-?PnE(tOB9aC%do0`BU?y6vrOg+@r=F(O6qgfy
zUE)Gj3ZN)qZgT%HpY$o}6SmcfW1KopR?n{fPRsNDVmx5?-q^3j`v8JYFYI0jE_Wov
zGcozaZ>2Kmc2hpu%%i|Nf|T!vMsn?4gKUfrXc^H!yS+a<-fZ`OzjUj+qp)7<kDx|O
z|BTA7aWWqhC1YRYoh-$P;@8o6D<;CojZY!>&Vy>?JINnPRe{D>`$F0hfx+}>WDf=g
z|D76p;i(y7mm)Ay)SY^K(4IZ!`TJov0mX|_%^vxWZaWUW&j1yBTp7#Do3#C(H0=K@
z0;A4->UL;%yEv%rMC_rcCU<YWtJ|HRdh9xHg36OovQ8(ZMqo2IN;hp`i18u&5*Lin
zWwTh3)`@+|EW;B?@9dUkXu_2O9jih-Wm_0=5v2Dn$Jua1#^y{y05+2*_pT-U`}m~*
zt;?4zsjZ=v=<203dvO9@VW|!F22C69#8UUv^c!oH4J@-l2hqL+>HON{$8dg}G}1>N
zj5Z~J&FPo({@qP;qPYOnObn&~@F~3X_s9O3qkRF9zm)iv)5FGsJipzT%V-08x(LvW
z3`A|e0CLt6oWp0(L^)Tl^b5jvSjF#eygx<Qj*z>8)~KZ7nit!3@j(&aRjGPMA!g+{
z!*(a=xfPS-J?Ru%W7yv=#4Lzo7<M(ksLw5KG-2Tv&N&%`vJ5A+uB<7eFi0C4_RYUi
zPxcKNSA=tbO1yA49j|xH#hU*a4ZGj<xzRypoJA_3XVUj8GV{$IlQzJzVdf_qrh3_L
zB3c^tzvHAE@)O3VgTV(9`k?M|S{#Ea_knaz(s<?dry$7Xh#~@)*GWDjwGBnx$}B2V
ztap9Bs^3kt*l;QZi{;cPn?*<UOl`05FYk$f05N~u3$97Zn1@}WeQOb$rAAca4HvU*
zD^bt2+<JdQ=z7yi;!)4er?hGB5z}=FYQbhmmu6#RD1SOr7QFL~Wrne5M0LOwU(8D|
zrd-e%%jbvXkmH1o@&h@GGWd~;BJ3T@GNLKADwmdqFsZPbe~650JSPfwJVns{R%6{Q
z)|*ze7G0DV-oPlM4vyOuzmGHneJF@GXqSFuL9EfPRt`R;r*~h{O6RyW6(*4k@lX^h
z3xEuOqwEzek_5MfPlRAQ5koAL#Et7l>Yom4Y!RN(Vvvlke@|7j)xbDVNP{;CRi^)S
z?uRd_VkBBsbYP>EhgXWhb3kf;<h{j43?tD<^XOe3B?2}WC+1SJk5zGGn1#_*7Vhef
z%1JP{iqY7RzbGX6?T9m-D=&5w7pQKb1{+ZVgll=bYl$o;rHS%0g8TcevTlFvp{!Rh
z1}?amEOCUx%s)#%L+?>9DCSg(iU|N0u8)-`R6YqD1_0T(yBpv4e?$>C*a*Gp+{oLH
z;1cltM(pI#>>ZR6L_X;-7V8`ep3XCY@Cg}3jV~ISCSu8zn1WK%*1Ey%{gXN|y_xDB
zSTv>0$PK(7j84z~?TPQ^FR$>4_QvMA#CUq%CU)9gw(U^#DL9`9KoD^A440&rP?i~i
zGa0BRw(L4>ZY^q_Lt8z&-zkRX_&=rFm%yYGrZl-tStezQDI3ryRMYnx_h+?JF}Of(
z96cw3O9(Uial<|02REs@$2TEgtv75Iafxx%=q%?xOMAOp1HB-8n&a-~=6e60YSmlc
zbssLJFDmQWnG{b3>-)L1{Wq_lImcz_yVngw`B=9p=*R*9#FvLsD(E{)9{q?Wh-7Dc
zF8~^!5)$>r?vr{c9mmipcX6M60p3zW0&e1Ahf{Og&686d`dW^!cix)iW{y=WY&Eg9
zK(w!u2ts>vqI{I9LTI+0X}@7kc2o5pZSSXa1*_ftAQm2@uxa#`PRqATtd_x|5a%iq
zO%Au0Eu59|CAv!*CN}T+>w{j9)c_n%#ebZ24HzwVs3NLvgb=%H=!H)kJ~Zc!1L|s(
z7O`1r;!<}wq|F9bgOEj*3?8u!eIM=1%5i!o63$}J?5}q_hUUzZ*Vt5*yvK&$b-D8b
z*!3V*kW~!g?lGp>6mc4pr7+o#iPJVK6SQ*GB4^4N?5VkhDmQ8=Kr0ya*9p(_Hii-v
z_6#!7e^GHe8RJk5vr;e72IRgF?4iBe&x~#j^VH0lwnj=Hc1D+RCafNhJ9qED0<tiN
zwD3&fv>SH^RR}yTM^1qwkEmUygbt<s@vd+9k~E7s5>)!37OE;rTwqN6McFFT=3=hk
zE9Szb$BZM*GtOaC!)cLfkkC-alnHIO<FuxS5?b8Q_A3wu6cW$&4W-r!9h~iqK=`-x
z0X4RoPRF=|5sHj#>ZJ}9;cAs-S$vj@YC(e>c7ws`ZHTC@lkn{iE+pXH+$%sGq+n{o
zZ;k(4ok+Pt#$eVg3DYuXV|N%TcLhP`eJUt8C<r;f1NfwOdxW~BHf4)PvJX+jGQ;$D
z-?*dA3Qh<1<`QB~KkpAT<2_^tm@*(t-Z$a-<mi#y1?WujsCu~OyD(#r%<Py)@>#?H
zWpNJ4jBv{VcLGwkl0u4jAdOb2fgls_uR)@ZtB84FXo<b9>|jWJtYd7i4(m&;TKE|D
z^#EUb<qAGVeew{KJvj*)-cteUy~-c5L=j5l28X3%-QeRq9f_#@%`7$(qokZOkf$0{
z9nZUX`?3Cefo>NqxfmLbU&OF=bP@7Ra#rqHi5C;eOjyu2Nv#S5SQFOsSQg^#hHfpD
zxIH)o9kqw?VtT{5#&5oOJ*3%?KA-S4;6q{fpr*^4?`n+=MbY1UIWUEzKl=!i-P=Et
z^^bq$@O1ezs8G>V-WU0^Ch&drT7kx5epR-!;-lI40ox@S#BMh(<+0g(?sQ%Wiixe2
z_!K@x<HZ<=C0h$PE-Q)pd_^4~&TTWTTap-9Sl<3QBhF6PCMKx;td!<fkazE#{M%N?
z9RI>brhlvXS&xATVEC{46hN0vJ_#kX^|~30S3t8-2Mfd*oV(BYCsUq!jmP57dcq|^
zb<<=bQl&|Tp?Z-xlK*9!tuZkAiFAJYZsgUBL6{Me8qn>M41PQeoA^9t9mUJBz3}Z~
zd{i~gIsL0YD#y@lBLCK(zmxX(KZ*J1Pi(I_il8NFni<%P)rcoY%zY)c5*mO4KN)&D
zxiV1`fX%b^LV0K)O7toKl5`{?l*MG2JfvUyfeX1Q8FT9KgeN(|XfUsu{8xlP*RdGj
zs9(<zib%2+rRHVzTK3NMX0FAtug}%P@!EcHVep*3C}nk@QUlNzZPs)HLr@PY9|Ehd
zADB=<_<{Yq`IHU!veFeIwb=+%0awPDoV;8KIMAVJpgnn}o}qpx$)R867)s8DGFOw%
z=T(@yM{bkduK~<Zp2YYF*^M??rAa4h6C3%`4Mt&GZNFus6i2VK$Wo3@WwBS@ttKtw
zGie5)9mKYsFNe3JhS9yJWkwYeTh|R$qO50?Ud~ytJU_7B;J~bP&K^g1rS|db2un@=
zNEgb}Y5aN|Nbcwm;07fv3LSaHs)~0%^Ro}p`)_pnyiuEDa}cX+;-_x(&{-y>XFqVI
z=;i51;hw;!(>H#!-yAt_U6sxgBU*XFaan|=lzT4|m_{8m9D3hKuBID|6SJ*<IvZE;
z9oC6ds40x%T>RDG<hr3?|D(V#Sm>EqwE}T_|2S1#oNh>+p^~21IXhW#ufI>fZFrCF
zOi*A=Hz-cnGdpLkn2rfw*BW01;Zh<P5O{t1flk{)(<=n5v+`NRo)tn=#Ah~Y3$L+-
zM&ZeO;QqiPSs{N$o2RBix{Z}Z1PUMEkmTbg?4qfJv6}Z)Jn?sKSN;sNiG?Q4Yum2p
z<6&zOZy9z_pA-4ojI|BtcdHiyuA^hm4_PTzOj7_=0Z91(`92`E;ru&8FQ+u)d%Xpq
zlf#}PxQ(TBa5kh(Nf5&58<z|m?_^bcv!y{;Kq<C0=(FoBkBl2H1Ozp6Gs4a5fEccz
zlHzSs-Hueby~-qyfPUE-!Y)^TmOMW_1$Yx|y5;ji_XDpryqR%%`GBbKMIW=1X5ROG
zp%opJ-lKJ0{h#vlM@ABQ0=&jQh8M)*#}w?&qB*Jfu@#1YE^)6mXyINeFIo5%jS7k?
zOj`8ObHdMp$;pquz=~T=n0K%)%F^lpM04Qu5JTk_^jkj?d;nfVXTB>Ia)uCT$cNJZ
zEsOieoa!&y<}PHTMOLpq+|ojmnfrFpd+N!y)=U_xVloN8I0uY*?pqxfnhry@RD29W
z2V~c1AAi;3HYNuVDZW^nbvCe^2fW*FUo1p3vAcX~`9*u1dP2WtdE5R(11z`hR&RWF
zV`-ZjkjtcI4B^J+&-}b(eV+J)eSC`+9PTTR%7BjS3tTyI^&Iu5tg{8m*B57=NfTyy
zXwMwFX==*xaGG!ev*XbOyBncxG>^!JuVd`mL!19Lf(}VYU2rQ23ZR$==pUB_Vh}2<
z!>WIro3=eqv%`CBWv8G{ip9DM8?O9hwM(B|F(P5%hQ8V8ok(P_x-!sl(Lc~@%q7=R
z5)#muq9uz32o)<PY%0+Dr4Fc=U(4^9IX^bjL<Wmbs7y-+XyFaoI6h$br4N=em0r-1
ziyEb_1n8W%PfUj&5eK3>X{s^O%1!Em2^gVp)XNzOYP9+8sKljAaa!YBagQis_+EVC
zOrjAeMlE+#84TsOeavmPXZ_I?T?>Twb{wy3cUX8-4t(`#e&);gw5j;iY4OMLK^<d@
z<i1AF<f(=hk@LxyzpTPXIEyt_N&Xng>P^bl{*%l+w`NNfb}U@V+0u*g3}(Yi51v}R
znF4=JPDQsj*s0v0#q!)>_i(EC_@*0W<pA%#tYqucc%IBDJ_-Eo2MNXk*ze_$cQ)*N
z_ur5o(fo;;OdyB%lVZS9ySQPaq^@FzxU)j9erU(Ny2_<!QE9w`vIcI0EMi61%2u8g
z(>SCUv>7U<Q0?}3DnZzlg(%$0Q~gyAE<mlJjS}ub2CU9tut}#hmxFL1+fWL#y9rlz
z{GL%F*t#gE!5af4oC1U*lwc!fs+=TS-5D<B-nN!(Gr+#IYA1PW1val=5(e<KfVK-O
zviUR0g_H|xZt>OuemAo&c^V+*mOSSa$kyFlXv$?<d>U5q13V(JuSVWsbYKqMC7p!>
z6xCH)#yYeS(ZX%XhAto)1Bh3^8X}^(^^`K`Qul}MxjrzYscQ5?Xy+rQ6gSFwPJ9E7
zkbu)XF?RwZR(&<@3uRgd<Q&Q0qfK}_8#i%Ml!uT??7dj#6VITl&AXAvM71<=w|n#u
zmRctORa4C6&i7%dcASL>eQOJFuGzrcWj%BZQ9gIn<5`6vX~&M3X!@O28-q;^Dw0uM
zts`xRp-p@3&I<q_`3PVv(?14I5nsLO=xs=u@Y5~aBoYU5Me8?TCpCH!Y!)Ka0raSo
zvJhCsaF5!OGEzG5J0J;}o1rIL9mm}CO4-HY!oyc7uyy(=u`c8dVC(;7v&j7UvJt}3
zPEvv$3P&jb9GJ`3o526Xa%5ZEVnKJo{3#A6Nuy4mc%awDvJAW0y8F)Uc0(excVH^u
z(!7;!1?P;Th6=N}^Wyq<@rgj43g@Gi4Y!K?Z6QCst<0&Mm_!~^bp`SW-x6$RV<qm7
z0{%Z!8$b?0@Gjp%R1l`WOlY(kMU_L}SBu@T|M>qo5O18sqQ|~zeWT%)dn_Y{DI#-+
zLQFa)7?K^^z=}b|e&7UF#b;=^i@j%g;Tl9a{t~^O8ZeCtfyLh(UbIVs5e+GDBt#h_
z%b*{C*f*HYW}C-?|E^!L(AEm9C+^SeVT~j_`=Lu`*)f%_sEw*;S3{u&FnwC7gK44&
zByk$Ib*q=NC?02-0bzvCD9A!yiLp$+Q(}UBeEK!!`htT5!;mh+6b(Pa(a?nWg>}jy
zp^~7)&E}|m^ax(djMg}3oCHBKBNvy(Z_LoV+*Pg#6E%B*Bv1Z1fG96QVyJDdS`0j?
zwGl3+0HM7Iar=#+?i=Hvo<~~F2<4FXWGjU|<<q|ZBx%Hl@puok-v^+{lwOwSEyx~c
zm@bE?`<}V*!)CG8FO0ZqhK~IXD8z^iZPIVzsANwjW7;wiuMufs`Ze~9?n(o!CF3BZ
z6W}dbjFkB23Y6?_a?Q{cJZOmPAsS-QK~;j|IsN2czLlzq(v9M}{dn{VUCexxlB#*e
zfo0Z-$n@I4HO6}nhsfOYE@eo)uh{@@#<ix?rx<Wg>3=}CkaCbviC<|@H@ORM&&$=u
zNh6S^QJ-ox2bC88!g@!+fE}Ho>X6UffrPzmiP{WL@q<O$v~2Jn#Gnx8Q9o-1_LH}b
z>c-kxOUsdx0EZ9<f?4nB3&gID5Clw030t_9TtBN_fe(ltnrCNgSs|Yvc`%!Jgq^0D
zBTrVi+OsRjzbLY}{mxSP5ks!NBY0S;P}(0)x1L-Dl2Sst0?FG&RlO4w8FCjZWDK;|
z)werF)k<&&fzk2e?%4?z-h4dybcUNy`D_2O#BR>2OQQKb>OKfhWNKgdg}H2RYR$T9
z(gNv~{2<gsHF=W2+eWzJfol!_Tl;^oJ8%z*9)B%oT##2#o(m`#SG0&&hnAf`K4amB
zprJjhe88WKylYx6MPhiwkeN7W(kympqB^R;M1b}%{hQZlXJ7&U%UPO(C8v=h%sLH^
z<x&yR>bl>tXw-v`8mOrbEJG@cMFMw@Eal^S-Sm^>aP-Qj`9uA6#~)jEU$s=$)Q7#C
zoXi7@m0rR%6VQSgXCgy6(k2Di8p5~Cly%3lvq^VLK@i67r(<2L0VJOZp2LNn`>!hB
z9`cm=83BaGD!?4LOqTJ~&z|W~6sX**MYcAhscKtSLRBU>PaY2Fb@rnnEsnPRo6P}}
zPHhz8ywYD0A>XO#H{SoUm@O=VI4TCmlzQptkDDiuBU{b*2f^vT@<q;}<A_K$nSX~<
z((bhms<PaftB6|TfLXFewj`#e&Gok5(!9Ajw(Nm;LI(k;h+XXW(2NApm1t}>94W%M
zfLKkl;mmg8k3Bvh+`!1CGct%nZ1kKqAeC;M<p_2p;!=klT?!bAE?ozru4UPQISn}8
z!vgftl3!FOd4Y&!tR4q(hKV^iikW{NHieP2za)}VFmF!T(I(C+3R+@I=S>65%64my
zK-n^(W4hOaD?WS3`vynPW?11szYLR@2M@SE1<u96s*Rc|RN4;>rbE|2k2+GV`={P6
z84T*T4k%8que(7!>adj5S--Xk?Q3yfi8S`(&TasR=WA8eu*cG8GVPWVhlp~$N8E^M
zn84VZn>8F&PoLHLBySns{@np?{|16xr}#q;5A=VMDU^~ex3uzWW4NJ4Js!t^c(w34
zB~V9bkk%%~Q4nBm9Dcz|*8VX|p}3QrnS*pnym_t7OuZTDUP3*d>F>Sv7f=I^nK!+A
z)>Cv0!-3Ytg15l`Y9MH0n-?c@9tp+Pn*uCcgD6KsKRhK)a35E1?hLH!*eJXS+hR-O
z_*JNJoJJu{-9SQOhuui~O`BvX#X7<Bn+09e`5$QUL3LMVnNAMkFkpE&R>;N57DQ=~
z1T}$|p3@P-><J1toqv>l*=tqDULAE9eu{jFpW#i0TnIhQQF{RpFMKvYDJAeXO=+O{
zHn@h%+QrCwHnr3H2F_=t4QoLjOhWLY8!%APS8-?jumBT0fSwv_-C`8b)<IbwrFCy1
zy{K|C*dxP5=-ZK*VcEP3Kf#Oyz*_;~k5x19qI7MX3|~#bWld@JCxSlMoUW|jB^^T{
z1@(j94%qsg{}(S8gUh*eflPv{$e8vCkzLr&?bsA^r&;~3nfYkA)!*!qA_Y>|_mj=&
zHT`ImGQ~T~U;)`3!!pkFJL_`Wh6EzS(){J>i|p42-vdsi-qP1f1z#k^{medC-=47w
zYDhNEia87AcI5`hmGG7dFzS0BrHnD$aB9&g#ay!&jkjcCVS8KIEHJ&(Kri<yne@dn
ze?LFRD<F<gmmtKWO14M$_syPUjyLZK#OSVY-j)|9*zhlthdULnj*G;4Z@vg;m+Ai6
zVjmQ!AoO#uKTE-i{}Y03?tskLuxrPt23%T4(Q7u;XaB)3;sLNO%OzbXSchJO>aB;-
zr{eS=ULysJd&AHzWs_#T%38^IYLdq&pH4h*!&gp`&$T`I=IQzMjPH*+xr<1U&^Y)l
zY6!D_p_M~gXRJ5?{8jhX=Q=7U6|=aZ9~@#sOgcrRMO!Ff#K!j@ve<gpe1$ecQX{Uv
zg>3{ylmM5UjD&zHIa|U*xocRqSb<{DoxP)r!2FgI|Cv$(r*o7{8>UK2RbbdUzs`kP
z!r^u1nEu8PkYH(QsC!QzAJzi{iHG_u@eZ!g?wpchtrbG1c(M%{RfN1W?xW{ki)<za
z-^Pd*K=@G;H<*9Q9o4|7slkL!N-dvaWhjUsUoUZD=9reAqZlACO2_kNQ~`aT*aoG;
zf!8G)9n}Z02nT%$)pn_Rw|+B$R~JLfC6C<NeNfvIy{Vk@-;!Gz=;O06198iL;f=_{
z_To8r@Iim1=@o-I#xhN50KJr{PiQ!o1Axik;lgCCj1#*-DgFoLYdJlIxK}oWEvY8X
zUw|26H9nl`brcppE}=B_Rv79=*q4u13czbN1y%jW1HKku{qS7j*<aXfk|vtz8Le-y
zXK@A*(Tbp+1=InQ1rX)`%CiI{$A@#7pSWF(l~~6%FO)<maRv5;^^ms>JW|rwj_lMo
zp_!9(mh?AO&&>0%A(4=#i-!4i*(%84c=HLQTSVFi0mX=}cEyCLw0PS}Jp+&d5KhH=
zJUT<cae%8jzsTE#X|lh-l=mljxCK|@SCEzwm@iyWLU^31-QTYWD(x6;F38qEjFm5P
z*i$jd%Ff&|z#8YvT9t-^y@h+LzoepgD=_CsC}v}Hjmfcc{~Pmc#rF_ijOJfF(%z3e
z3mcg*v+O00H6+D##<TOkC_r55y|xMKs+2zZjqs*cYV@oU)qwg#ZFo-am0bH3n6&L|
z#v;Kky2dYP^-dLIczZd%vkYw0zZ0s+sA#AA!)d4f)J0+)-YvT%wSXd)^CV3tlkS4p
zi`ETiluD>PhnA+m5)Q>_`~dNMtz5hEkxyc$uYuSuTbktv9XW30zDA$2i#l8Y>tqs5
zN}lKb*Ndin+?LZG9!HJ*ZIBM~onqNq#wmL>Lco`=B}W!k#41;{SPc@8rw#}6{6uqc
z7IoBM&iOIMr#Q@@K~!xkVB`)RWAoPGc>SVNRnzh9u}LI2P<Y}`VdS09tM8EAE!q}k
zQz<)fvygxcFYLks5M1+&aub0Ah=@>K+;cKKeAt@(dDVVL>ZR<z?9f<`P<%A5CGh=)
zj3mMW<)6M8J0|bS*VKY*D#)y!H=I0+GRg<DtGp}~;<%zC`BGLv#V0w(<=fTD2t|v#
z@f%<P`u$Z5g%*EO0t${{z*B<@Qs@yuWhw=k-#vKd_X9HD#WB+x#UoyxH`6)nFqJ=v
zdajy&E>i_e7SF~f<2X|dgD*@Gs-MOX+IBQEn`Z<WvAAVZq@CV(*rK|PT@&eu>}s%$
zU=Tt8nedsaaDdr}g<p$)OwsXN`36H7C+5ER$dgeS3%TU0G@Cfjz?uU^Szu`8opXP~
zQzcB3QG#1H38k}ymRiczPc~0{<NmOvOTq%ku3SA{Pi(D@z!xI^mF)P0D$j*2<hzw`
z)EBr-r~HcxkI|;nVoqok!v0QlOf9shf0o(FJx!GzdEhahDyotU^>OBGwYx9Y@RdNj
z(C^5n)5A1;*gnIqTK5M&_+eO=T<CMq1!Sc|<qJ9dKILDX{-)7vN8wpJHQH)6p~lY(
z>T~+#$i>Pc;5X#SO}bt973xmB^d)I&Wuvs>m}L~nHwqfkopJY!ONde};G^X{2nKfd
z))MN!77wy20%$_>NJKQ+^fiZ^ZBFHFmg^qp-Ri50pSj1ngb%v5@q(E{%2n`H_y><!
z(pM}pX;Tnc%D@KvKQAnPBHipJp=OPzQ65oWa06@=rKfmgy(0reqkvSDm|K0++$uk;
zeo4gI@o53#bJ(;tj30}~SU)RPwBRb|a`OoG5T>ozz=m2i3R3Hq&(fPB%aWvYuL_PU
z9hz+oU?xLrG0Jb=#ysUo<m4xj^Uu_xdn5&k;^aMrT*_*)QDnwG-E;8NTcbvpE!Oi6
zG>tO;-D+I|{ZWb~=k#dNB*gA7;)Ia2-DN}1mB}z1Q6U>?_jG1whP21gqnLaqW_VuI
z%|@(~{Kc4m_h;O(i0PJdGX~v5Q`&(bHfZp*T9<`3O&}0w`JOO_0pbC&Zt}p-5M8VL
zd?g1?pQlW*7Ee==JaV?2W6}OV@iK8u^K~2^X4_!c4iQ8`>1k(<W_ZY<V=C#+-Bn@T
zIa3#E_rR#>xX3%|9qgVW-`;CyUOG~V5qqwh$=7(a7_FPEcHN;ggLc6TdApM%v&Z(i
zTyhAykey<YiJOee=Kf|BEXE+onur4OvnVP+3QGzKs)U!Q&lJWbB()=tnR#SmmTOG!
z34>4>xXzMHQiRT<uXk*Nml4}`ku$M6N68Oub_HQoEtCcrnM1d=!bp3~CS2AvgX~XZ
zXbChg`tMZPt7hMK%*Zn`?JZHCMYxv?N8N$XBe+jfOnk8FuAu63S+F;E<D6Mf<05HS
zd#N2q_uwiC%By}DAwCES&*4}=g!nPs?^xB)V<8~pgYV{WYtj?id)(m1`je=d+7z=W
z$d5pL6%rxtt=M`c2@~=wfkdI<>w~z4dkO-xf8bDj1-}xH1EfJ9Pku=G5LHvVG50-S
zxR6rpwe*QDG7V|k^vgKQPBVe0aSx(t8Mjs#i$NtEN5F4WOaYB9@)C!P>3)Od?rj%B
zumeX{6a%TOr>8epD9hG{Y?NNJ2nG*>hpb8v)Z%`hx9uezky4Gvv2N}ZXv)|QLt5xi
z&Si4Z@O)z+#A&dFsT^tTA;7dflanrRD;fXS*@G}li5#G!)$sT?WefVrFGVTw7i^fP
zrsJClm!SDgDaV-#plZ%^0_Q%IX36KS)UcLY2n5%=nl^l=dXCbls)g9Bqi<Zd)7cbn
zb(R1`(qaOEuZzG4A;<VkIL+d>@O9zDh+(m4p;7deX@iHr@GIn1XH&ipJz+m;5a^!F
ziWE0$!`z5-5z?4@Bj^<Murv-)wR*XrTs-d#Qw<{+0EL}hX6zsje4{gS1|Ag5^Y_HT
zVnKBHhAW7e9nVd<yfhbQ)}{w0GG4ju=cuClOI5Ys@di{VHca_XO>&ofTM!1nZF}|D
zr8Jt2Is?NX4<j&Hj;tjXaZDkKrVJD_RQTF>*Y1L!%>jpgW95my#1wTQI=w1IWiYQM
zuFQnMr5Z97jr-uAD(V)?x?5k#M7XO2UOO@n=dc}U?A&3kNI^hzZ|bQzr|5!8(Lh_e
zw}+F6g=9_ww6F6{d1K-n7Coq`?agcrh&(N3O|r+}K25$i)W_pCSh)a8gC82wg|Wbn
z%NYVW=q=sYm-99-dQYyQ!BpV!JW-Gybd$c`e@SI9O(P3l3thfGmCH!<=4J-dRhgdb
ze^~Wj#Ivje{PuT=FpneNyWRhx|0<Yp|9C!k5D>%vHKJ=K2OmelR<WdlAj$2z!jFO^
zCWeIh0=8{HT6>c$s5>Y`a;B(ks{okrD43SX?SK)%zE6y{EnnMXGG58O6XP)=b+y%g
z>gsHhDJ<S;V`k8LlGu~Z8HH9}u97|*P4%oc2zek{I>+woP&`fmU0>5GxZs?DHKl(M
z*Ne8r>-5625KqgWRUN~^DA+oKf81PHZuGf<y2Z=JQM13J+%Yl+0OA)EygFbtw8aLL
zz9OlMcMrlr%l{j!)(+(jB}ri84z03HVSz$#GA6t_tE^WwNfukM9>(F5gg|Q}MRe#Q
zDZ+$j5oSQ=xg$;DSxLGS17EW)b*%(JC9;Lk^O24ioXlxT{QKcd%8NIv-f7^G+!(x`
z2W(-FKl<OyqWmx`n$5wR{8n*rHGM*|f0LDIdoEbq3#e%>d@VCv14;v<=^4a}{OCQV
z^#l+ki4jL^TrddlwdNw`_!&!Rvj-P<7-&D95|$%Q#7gR2UVef1A;nx$4nb>%;YHv<
zo4~}vz4x-!h4s<^l5A<JKdS{H+=L)m96T;)!aq2uHC!eBAE<VNdxgAeo_L_=k`vLt
z;9yAL;euy#EFkzd=TZhn<dLJ)`XJ>9H<ccHkdg7fPOj7Yvt1f|!@be>7OA)}3J@)6
zEQwz<A&VXzSB=yP74lCUWZm$;Wo@gTg|%hq_0j5ls5?&b#1(X<w3~Ur!`;4>i>28U
zCz-I6;4(5;niJtF8M8$pe#t=vfR*~3?_wGC>n`*U*gHpPxSb+dz$ZtZA;*T=0(W5&
zgmE7-<o~3WTISgT!kgqr;<WC}3r?M>Vq)VU1Zmb@3#wo{{jjz(OFy5tvq2<X=>`^J
z)5u??d2t>ok2T~%uUeaNP~br9GJ%wPU1Tf>ixNA~(AVT?r6i%ftz!ABOi%Mz`6!j|
z>JN%KeOqJ7=kranVQ40?=wq8lU6eauc?T1cPNXOUGeAGw$h5O%M_AH*H7&V=N)RY@
zg!t3|+?w?Ib$%cn^Bu}R08$%^;;F%YT+<aG))6eg90sUn>{@@dc&{`mwBMF5yb93j
zn{6}0oS;0QcoLZ6Fz42fj5?4ZIGu*mrqc4gPvDbw00=Dg?Fvq*mGv(d?IvUnwC*Oc
zHTr&074ubBM1X7^@E(0ZBV86_lm|^lQj*V_Zj#*Yy|e)Q5px=*7>=M$@gq{!-`5D8
zCA8V~rinhpB(8lLe^bO2jj7QULf7l}@Vy<hG;buC)v$2oQ0TA-H2kD`4gNP%Js#+H
zadO8w?E?hkZB$?i&G)GFF<!Mn*dwGbCV~|Tl-*NaYkPZ0)@>+7#=iUFqlk+TF9C&G
z7(yj2Y(WOc8p8;thp#2f-HiEUYwT&WrHKCKN<*)<i=5&Zk5D6uWRWgt83WKhS$V`M
ze^A(UkcPpL^&Y)0B#B_{Lru&~4o{1C_5exsgq~h~#lz;`?%71B5dC&d7M*pxZIFX~
ztq%f5EqvH+QqxAj0l+JIVS*FBNGqlPY9nm#rh%=Gby2>epqTjq$|o|3;O9@n+X^n9
zV>H1?lCh}Y1x?NTfW^zQ=>Uh6HlzPaAUJ+(v4qVnTU{XdM93x^oX+&%y!stxM9=6T
z$QnNQvDHn%u2N%F2BZSx5!AK#qRf*W`-4+ypf+M{eIUi@btx%=G=x(ji}TyLV}APZ
zGUVRl6I=oTONb|MT-+S>LpkN@<)yz5jBsB-Nq~+?+Y4Q4Kd`CMVK#BP&&d`YTJpA6
zoq85ZPG4j#U<EqjidM^RPE8T40eJvDK*GOV!2JWD#bqRkJeofi$K$>N^9YXV7pLx6
zAUmP2PMGUr#H-Nxt8oYBV=Xy;rbcXE`kLSA41I4Rl<sX6auC%{0#HC3kBO;h5x}fN
z_lAqyL;}NPxah9w{7jXah{a}PE5%Ma`vkb#f05U_e}q8xqZ}<mWHR52bd~TQraCL1
zntl|K6u3SchBuhCki>HF;eA&oR{&=l=pZ&LLQ=X)9HM>^qO=(Ze=_~7+28zG5gpv2
z?8WAOFJY^zYy|0z1-6)->qA*z4!XjW6d<Dp&ICiF@}^mk+UqP*fWTj4j1UcOP2~jR
zr{pD7+EP}6huHWVO5L5l@F8)=aClF@5E@|2D~z`YR|ePfs{%szr^`+^G1a%H^1Pr{
z(O|;%#w>k>o)DkC-l_Noa?{_R3=X$sj%;f5A7o6FWL_e&*=FUimFCXY)J5#911GMS
z0kd+svNX{U%&~HzoRYn>n-#o?_+ddRx!#*4C8ftATo=htLP>mvehJ(P)Q8qTyY-Pr
zK-94;GW8?6RmvJu!|w)8EZVksGLMaIZ}%xMZirUi@Qbio)!&kGC!td;$@OWU`8Djg
zLlk?*NC%x&e;$o4$F1gZj7=1NYLg4$eTq5v23<a!Z*N3SOI5%;;V6v3%`b(S%~k1W
zos?3>Qn`B=j-yimqBb}^rNakPd<d7A?A1}k8AO0bHr&uo*fOu2$5)L}(2D5o1~Usn
z0=ei~kHHnAQx!~KXQRBtqmeNi?plhjg%|@I-^qp1m)$#8!Z$aB6HLJ7h3j8&OG#OR
zXI!~vPr{`apnnbou#T&-s<YH9C*%}EE4a1oJf6AfqzEmAwCtH~TuMr>stL$mu%DPg
zC6CqEDj_>x8YtT~7}grPaQgFZ$c-#~9_eUhf7*1aX?)ZwP-~X#8Qnn>UTSHFq-GIw
z@R3TU8dJ}-eO70haOH96xsidOSyu0h-)%p?Hk*FM1e|3%sMC_JE&0bQCA^Q3U`krZ
zJ|i!1Fji$y=;7FhH8lNR;#jzC$f8Sx*QL3`(nRwXYngc?9lx1I7}>r6g_|ksH(h30
z^6`Z7ONd|fM~oZb%h%BnY1URQs=?J3NSkbDnPX~C=z%1=u(9P$5rLf(p$I_nqRID}
zzDty?=g<YNG*<Y>GdLR))_~tt_+M7;jy`lWXsdbDoMhP*R70R+TFrH7_AQ|}e)$&T
ziD)$x)1BagI-JSt>;hFdx%MN;P=twA`Se4(H7uM)7zJD+h*T6)E9oN}0R<PzukWmM
z%_fA6Y;DR4`X;suzyJN2)9!~sDg{ato*}m31`#}ht;Akxhe3r_BZrvIr48*;T|mEh
zQQECrilCKK)elNNN}<6kheSSP1rB5B6RZ*AvxhXtpn+43CFboZl$!iXSgbE>4(dtI
z+em_362F`El_*h@I{8I&N31>NG7F;}#kHFr*dBszw(LuA+J*DGmmYAnKE!QjYp?=C
z#$Zo#BKn-w3(=vkxDYc#znW08*TiCQ+Pk@Y&l+sT$Y>m<8XQy_5T-2LA`@anW;J0o
ze(3>=HTn91$Aari1+I};{B9bCESHpU@zD5Egw8O&**6*EWMEg35VVNZ41}p5V!?Tn
z*-Ik5*w_tClzKK}K!^<9+l3?LyobH6`AS`rS3bAdjEC6=CqxAm=XrS)wsLeyWvpyz
zli9SIUd4d1=cS=WUm449?E@sSlwHT{R5%Kl?v84;sr8E(2B4nF$#m#Jp5JP$VsW3>
z$U-K^ixt%ZKoCTfD}AeZcP}jj%rtIJb3eDA?77}7(c5+~^5;w|608CR-k4ikRd9!=
zq2Y??obyal{x5}-oD8*g#UU!^e;_3ef5m_eH6vIt39(1-6n@>41A&-kk6|`W4dmO0
z=c4^XgWMR*cXIDSg4TD~R^K~YT#?5XOPiuG+3Py!5d7^cuRE+5jQB!f!^-n{uKdzv
zW=b6X>R?%=Fx3OE0U>Ys=jscdvREXVo~}A+sGjS?FN0x2&H3dnK<Je;_)*UiQs9^(
z|B^}iY=dKkzk^$O(PL4L>&7u@ds(qq53G^tW#|l{on-aW)&B(0RSbt)D#-q<f@ZU%
zL^xr~)MM_)FN-|4dX_w<*qWN?&z?T#pb@n{k4Hd9*54}KH(@)VWS+`xHn`zPejM<w
zyr?Wae^`9=9Z$O2H!py#15<N;*4aMT+%W3&z#+z?jJ;<IS%U9de^AgU^P+73tOuM1
zmD%LKN$z<)jPjIPSlvw9?!T>7r>aQrWe;o}LPHhfW7IB$jJZ68kF2(_ZGzVk{y@fT
zKIro24Csx!<VH9$U)HoScYsu;rR1J8*s-;qnjZfEv6CMw9LpWQr;#~U;f8l@l=nvj
zc2~~#cMWddbk4YZE}fJ3pJmc%>Hr<*pXo5XJ2`Px?aoU=17L}<ow+VT@wAd##1&*k
zgHhHXHG0fG!&qA^<RF<XP*lPE)g&rqagBMO-VhaEl`WquJoT5b7{?)6KUtnXSTUUF
zw8OJGY7AQ<e&qg#v1+`98{fQvZE9ei0K{=cVCEm<Cq6Z?A-nyo;mur``f14Ge!`08
z<vz7-Im)2iA_%7;IAOKSqF=qnP0s4)U%h54QuIIe2sA`<9L2250)?TE4zFY_V;61R
z98qo46EZWajHc!_y}azr&=c)ztdDXX>z<DpBP}6CS*<xTiOeKB;seG(2`a!&D;l~T
z{;&0K4n|IhIv$lC-;aE?_zGzvgi+4{WJPT;ZX|*4D4S{VDVw8V<eAEKe6CAO`UQ=k
zpt>61QU@H6LRWlRr{sOB54pY#giNW?FJY@{jUh$umvS1Z7;^@W^n=Jx6$Y7BI~3|;
zxlVu0?l5yV|6)!22}m?Wu_O3o*-eUGPV<Wgye;*3N>p6R@y*OJt)&*QjC5HHD66+c
zKdXLQHz+y~!vH@g<7QI(c>S;n*(}b`iCz2g%({3`6%QO9Nh`>>_;ZGEliRN=I=m2%
zl2r)EM+iN0UQ)gWl$lfyo?fmMLcKBd>T4Ay0R%~7A2p0o$uw9yoDGJ3xR^i1;Some
zyFVT$tpTlaQ|sD+R+eQ!&L(BmY6}Z|+O+!~MfOY)ew;}KpLoeG$Q?$1`m30|(*lgH
zpq9{+J#p)i?IMn+M{Y&hMV`UVb!?L5obr?;r&BSi=nFz=t8MRpUDtuC<gy@xysAnN
zcDVx8_Df2YGgQDzC(0s6HeOHF2uqN7cscX5JWmL!M5Xl1^<}Ji)S2xY8dLBAnp!Ly
z9f`++NZ=fCIIv4%h`1P`UQbNpPgpB4NPfm1;M~pUlj&4JepJ?Kxcw4qMXKKFWA*$@
zC#D}OfCi5QlX0=qs+tf6)4rze&0MKgz!;!6x{W;h*|PzLjC(M|C8Qbd3-8}MvOlRu
zJ;I0KzyTPrz8J=pgT#3fJaemk%JQ@zMY;AIKV=J{Pb^mSmQ`$kZW~gS8OJ;RIVN}h
z19Psa2v=JCm~1#W6feWa)zvtjFQoYfDEM3!Mzj#OTB9We*2gTf@MWXR?-*s<D|9zW
zjIdz$lV81h{7>!{{T!^|H++Dy*ioSB2kBB*t8^nG+>$X`^@6Qo3}Cw@MJ1Wi=x>T}
zFojm;*tGLdS)Vy6TioA^^G!s8)ih0971JF6Co<g^<20X)%W`82y<YUKLL(N6ek4q5
ze0gH2P(YxGWwgsH(0nvH<zyXW)_}6NX^UV&j-+CJU;meq`cNH!2^Q8&P?hmg{ALvc
z+M;e6nG@@hH{?Gw7fKgO_*h>TG9_akP8OPFegE!O@fP~6uLM&@h&G$bu7a419|0A3
z0F3@fayk0I-ga&}s4o)+&`E9|OKQb>uH&oup26#RS1NQ!Sv3t=Tvf#eb5KUhOD1hW
ziNJVQq6fK+8F~_xQlo=B|F;_A9!?)hey<+tgchNee_K}g97%Y2PnIJ3C$VR8zVoUe
zr1q(qokWEMSyBWYp#6gN!-l8-a7!MXSWC3MV1mKKe#D#s6ywDS4AifAnc5X{^EXME
z74mG0LHp_PK0RBCc%d}gB*jn+5oA7HbY2@=(XdG>(}J6DFo_qSY?ZRehHsh-p_S9k
zuuyb155@W{nDva8T=LLjbnS3LT<P?L()I{)Dig~)#cWclWqO8(Dis^3jGO6I-DnsH
zv{IQ&Ru%>uk-4!mWkSVrpyjxBw<$&V7c`au>>CsFT1B^`Qr2PPZ-*+!JR6dH4dXVw
z!q5TP1UNIf-JxdA>8uylI7fjWN9hNEk9+#JH8G^D^9Q;?zhG9`e;z1sTDjnhVoeH`
z$$C!<?pMq35kAg-W|^#h{Sz_}3k7Z^m8q7eIP5J!#V)GI_9RoUK%{JFxmu@H;bIVN
ziQC5%2sb8x?pFt;!Csga&bIXU42d5<I&@TFci2fBl~BF6k(#~&a^STD`0I2;WQl83
zD7Uff8VG~b|AYDZFV7gI+}+giP!7E8W;CG8bHM4L{>sl3k%n#uSFTKp&?~5&YzVnt
z4U}u$y|<f9)6=YaQaZmUg3$jwtRKnHNU+cU0i`YMJ;kSX_8bDkRv8r*r$B1(S9Fc4
z*4}v}6}#~#1p)x<EO6l*eEI>w6bgCEcdH-NB(yjHl+1dMOpTB!deO_6!hj7QxlNRZ
zyvtHG$DcNK_?xOA%%;aj0){k*>owEm;@bF2fd{*{W9V9oa=CD&IoI0LP~h9oI!!Pp
z>zC2@Ds`H;`v4D#mjEdknysLj0)~;X){V@fX(YMX)}4<*BTmJcWKO2@fQ2kxFYU)=
zPyVg?GrLUL1Z?oFitp5xJl56Bnz#v}K@O+``qrj>a}5gTxQNU7kSaF0hVxfY2>?KB
z0%mx~R|><5-UiW{mz+Wdg83;J)3KIpqhMbZ@VcxkRC8d*b#x|a<j-r1Qcr|x5mzAO
z`(<58E{E}bTj_-&<YfPDHVYRaT^%WRklu`xPjnkA&~jckbH@I)2(`I{+|ahh3IPz`
z_5NYk`T5;qu~P^EG$!Ru+>aF`z<>Ymu5-d|f;)d^x4+AC0aac=026V=2q?!Br&|*f
z@uh19o=89?H<|Teq!4p>8XrrZMu#Di5FhVx9_co4TvWxXNT;NlBCxtdzrf_^Qa7-o
z`i!)EA8R~omkp*7r?!G$A>sUzk)`;`mZ#&p7Ah^FURd+1oo73ml|P=7*8>iM#|*|j
z!qUt}(7Kkdd^NFiAdnGxq(MD~Q;}czE7c`57o9|N>-h)`JOE=+fqHX#C-8|>?ohzv
z5Z+Wk9Dt)Kax^@58{dmf67K8%d_IihHl$+}O~ljeXDl4>1DVl9e0Y4OwjFk=ex|7d
zgw)In>{~+O)lRI6Q(~?W*pov^=--FAv=^VlDb!Y|_z9~@`sVbI$8R9>$JRl9{XFe`
z%p_@sZEFgUvQ~=oo7PU?Xy-XF$zZKr>%cdV2tlO=A6JxS=zR@OLKi(p(zHsS`&Tju
zqiqNhL_lesqHv73EBd%Lc<ar*0-geg!Uq_n=j-usbK3S6UH3#R-TAAIpF7JKnBX{Q
ziMCEkds;@Np)i$o<JA}OU1bF^Sgh0+JCPBzf{D=LVQ2?${FmWYl$!<5#!|%#$$V<#
zJS&;Znw!@Zse_E{0V9=j*r7!*;2lCZGpY~{`JP{cI_k^4EEtzQ-uZS&QSJflVv}jd
z8LF+2;H|BHm+^N^74i>YtxYjU@3bJhKAm`1YQGKLfY-%fr=^Cae`nDeXYy@2LsMb{
zyoTc!Ho~a2oT`BuD@EPj!8=i6Av`BF!FpVuRzntr_}&vxT5o}UHn22Q`HIa|Qm@^&
zym|G#pBbq*%&X+vJy(lx5wxhnf}Y>JTSph$_F>Rv$k$*0A4T}Tmp~Jj(aZ8wZxR54
znz`~;hthGe0}0X;b_ewAAQ4L?K+n7`2`Jw&1+Ff1ftf+JEtXjgnV_%&!KMlhTSsFY
zA=h+92%i66cND*3NqkuPkALp;C4%Y$SdplYhsbHSTwfCWt6#P;A=Y7FQ<V$$<InKB
z(c^5KkRH_<op$vUnM=JZw%l{3D)0^|;CEY-EVkD?I}Y2NEkF2NXEAcOL<f!Zdj+17
z`{Hl$UgQ=(Dt#!m%HjIXF$H{|e%yoS!pu`xv%J?Cvly}FH=*fO6?a9qEMW-#J+bMp
zp7;lUSSU*>llizQRlIX$AO<5K1j(Ks9o|r`;q1`?<mIr&{Y9WUCdv9Y0<)x(1wc?g
zz&F}5R_RVjx0WobV2QaMfOeEtTcBffOFM(zL69P;=Fq|>F?}@*q!0v;S=cpWECkk;
zi%3Z*3luXCg(I3mN%5p-FAu8d47$l`i_QC3<K(5GRT2BVbKVYeFU84PZ~(J4_uLZe
zVY&JR(o=Rwbyo$wwl7e&U2@lL!HXD*t$Rwu1LZ08c4dy452`<E1o+|rWIDWEF96eQ
zTd$@}a=qxiAfAAVhKD=qb`H^#im<RWt-4dZc8bTQ0V-^~?b&X(VfKqIK@=QcLmH+Y
z%CoWny4o<j_v|ciBSq}j`%CmAxR8G^F?~LF{JE{i(k~~>Za|1`_1mRtTKb;=uWFLY
zijbLJ-h9=QMp`{}D&0gL`k-uU%PrD~H(35_76px!_kNTS5qi|kvUqh|pHPCxKT2nl
z3$d!(AySFeP-9+|X)3@y5Xr=-v?<GW7kuMfFX4!#{wu&K|HV?QZG3RYaZ{-$GiJt;
z6ad%7UvW-eSN#AqwBQFomv`xw98NWxQY}0=-?yZg2Q@503w26WmV?pbUaQYcJ*}v|
zHFPEbt`#i}5ivyrd>-hCAJ!9(O?%;bkkzfQ9q~}|o*1Jg)=x6?M#X)tU7MvZzmZ(O
zd`G3Dco+$?G~s0RGkvv+5AMu{KGXyqEOpDWcCGL`_Eve%ds#TC4Zu!%TQqIbxUfQR
zTBEZ79=8?a1^t%#c6;5#-3Pqgluf2A1aslxv)5(=%I+?7e5iCSh!{zLOS*Is7?Pjl
z1MdvnM3)R`dea5HH3CE{*3sD?L`c@lW;OP&Cs90bJ~#}3=l_pg(s_qtx(&VEk8jLu
ze=8?{BJMpA@l~L4cMPy6qGIfXU!1hA7=idY6luFBm2a*!;~x9^VarmayJX5pDDLW9
zH^@FrX7ysFE669FgjU!hAi+yd2y`pV=T%tkVe01><^<7_;^b7*@GUZfQWmp<{TdD&
zk#Lp;)@~%j3Vw=bw{Bdtr=yhbYPTfy8x(kyhr&_2AKT56`q0_96{Fc_ZWTAA{zyb+
z-IoR1VV3c678h-*e%i&M7Q2wI^V)a*fbN_?-;kN*3OZ=gtHu6wdGY!XQme~SNsC30
z0o$`}xP`Q=D{3A2<_l57vSJy8fG@I|_(QojFBLODePb;kX_4sTq2bVk)#8_D0z<}h
z#N=fs+MemL*<YaG7h$o<9lU%T&ZuS<>VeT+jy%g<dci(eq_nH*E9pr=67&$iX`U*U
z^4zhoYjUE=U=Sv*!8-OWI$EF1ue)L>|70aru0rIW>nD6FWJH$e#W+tc*H2&^8-E6a
zp-CsMzQt;7V@2awNf=fDy4$Oaq?Rw1oY%fML7KUvE&72Pbv<S8GCKe0)Ck$ZO%I-y
zQ}nf1aNNz5(n@^MnZdcqf>eg(aTHVnw)<eiSNb#!wKNIWH^8j?UOdZZ;>X27l9a>w
znY#w7`ycxY;p{Rcg2Y;c?p4PuFO|R%Ymh0xi4GVx8i=s26NeK@VDQSIs8Lb>>jEPw
zdk3Xr!DT7D`azl3zaBhjcI@4RDCXDcCNxU(;o*Q0Mp1H63^kc~q=o6gi36qJCMnC_
zyQ$mp5pdkeH;cw;^?1$bK!#<NCuK1BJI10LOg{N2XX%;3{zbwu`*iEa#*dQ`5D);D
zV7)HWHYIs9xJbbta@nB=VD|nn#(UU$cWNj-gr&kOJsJ_1mMPe(y*Yd4_U$rCoQFWe
zGSJA)n9CP>l=sluD`GpvN>TXw)oL;;QZM*Fz|MynHdN?_k2#%7_xBbxAGyQiP?DHm
ziR+EMwaKo?w|(xLbbo1@T_vO5He-S1>a6La<?Gs;f&t#~)Em!)>)l*k@{YSD>I6fB
zfp>LZRPAIDO(F1@;|Lu1ned7{@hL|7SHSZk1`*%!1Ew4^xf5F~UqE-0D7WiV?fv$3
z=a`pnznI~NP0rBpxjk<T9+fXJRLjLo#!_rNX?3bsX*jN(Wbd<V?@<WGjsCI|CY5UB
zhZ;*{sLzi2$}lA_)w(l|%s11z=)gnJPJe)BXS6B|U6Q=DaxQc)6e{^C;rKS3YGPcN
zf)eUWIG7!Ei<PsS#kk-1#Z&XaZj)Xz)S&*n8nAMy&Ox)7b5kN<!FEj9De#VL7)5hd
zZe>SU4FVcUG5zxK6<nl?_bO)cct4+qIQkzqJ!D(KS(j|Wz(jP&rW+6CN&hn*b+VGU
zbtM*KLXNZJy%oJpMrJ-QQ}jz<_Fe$>Z_D3(T6`2bVLr;kw(U-#pg{C3=EAG*xq_#d
z0Pil6sb)Oug8`3G?v9Y)6?{%*X9|HIAIudxhkwdUR7og?eS-9iF9{c<cW=CoPu)4L
zy_>TRUfJiP^%nYH8mRof=BJ%Ft2keTW1^reS=D79u@xvXCk`01@$?klFYSx?RW#g9
zfPwBVpnw!tCn_+Cg}lL-(*<6<-xy!%XrgaM&1owp%1wWYY^gB=RG3b&jgr~mQa%QL
zTV(epk~&T#Chpi^MRj*`>L^W=Nc~dOFa!`AnI9~8jb!G`KX|aWDv)OIM|<%30$IVR
zvk>Y&@6Mg4-0Bo}ShRU#jvJH&IM)&0oP^4YYdzHV<x>H#7<WYJ5ceI1%G(IzH$u;-
zWBv{Iq18A2d#^Hx??vt*I!e)y!PQzi>w9_}24F_-gXYmU;u4f_fyI<pXM-Q<gQ+pm
zK}%PuT2}5TyxpW#>HBBE;R}T%`y3nCRDq<NbV=s8KEBzy|3ff~S&|=iogAnejINa?
zyQ$}DgKk#l*y3_NcB{4wCbq*9J!FS=S6Pn5;i<QCfa_+jy7MhACRjE|>_>gfVlhw7
z;BLr#EJ}{`a@j|rGQ0$WrX9vhuQo>I{P49g$J+#~rj-~4Cnrg^?P>QIvTiXEuTv5b
z(I{@#hwa-U0Eh)2*nvco_ST~;1ZKr-1`u>JdX?u>B2{n&P@D%&IjGR7)=Y4%r?ghF
zlE;8BB8OKKY}d$?7W))8E7zExdF-0y;IH4UHzZ!ZW(weP{tS6~`RpciMXClh5fHVZ
zAJh3k2r<cS%s3O^t<KM5zN+o(QO?P3XxTdga}q)V0jI?`0!mCV80t&Y`}CMz+_9(E
z>Fi6j-Lh3J&<&lbNPNnPPRy^jZV^)q4A_y~q09;nG+LI=eTvHjg&Y=8Lj?DEIKJ+<
zaM1tknBoOwEA>{Z-Ejd>!c6ml*ukaVsUMBf$&KB$QqfEiT-Nrh5yVY>%IXn63f20F
z&`K+t$Tryh7mG&&nekkw+2U;?w1R_I8)V<pPe2~3<$Vi<E^40QuWvCGD5qwMpVXz*
zTHMl|uJ*x`;Bm088pL~Oz~h@09gNz8(&LMT+-=`V2d4@jQ^&nkI8m8+-dIm-n70s<
zHNU#JyNZeEiBdG{*g8CvsmY8Q9~y_6KO5yUpR1QCbdO3`Xo6FHXA9!#GLlo#t!-r)
z7huG*)RqPvK_v^cK6$SQ(<loP@FW2jh4-%8b;bqWQ)hzn%MbG((YF|28>fkU5e*PV
zY$zpY-Ai^RqJFJVB&t$&L@jKGc0TKSr!gUR<Z_gezRW8ZR9%Lg2;CqwX-nJbdtz>{
z=V7#!oEgX8I2>i%5aT^mIjz=7F1@gImE22^r^_6+inFJZ$_KZCeY=@f)H~!vH@je#
zqF$ruTAU|`chZq8JaceGqCA_0P4FDklq|5$W-+})k4-s&owb03?q^}qDm6bR+l5e0
zgNG?xGt=1P55JQNs|Ja&<rbTZsH6Dl0HK!JO19IJe>Oq;p<pbS50fOKNx<R(N@*~8
za@$k7lQ`(1{qCJnyz+6WhtM3ZrBvg1GG6hAW9a8+2tcjm{-#P337^|D%n~jle9xbN
z5xAxl1WB{J`dsgY`iJ9gIg<NAyO%L7#I$&%Y2nt|&!T`k8sPjgzw$7Q0*-*SKy0{S
z-MXmmDpmfuF9FJoZMhwbOG>j_omx0^e(krr)0=(W-j@nbKaa)~XpC-|(1RvM@&8w4
zF;CiQJQhBad10}m4yR64LFW5@s|<6~!lsc6ZXq3SBQ^M*>2H2*vFi>G=eL8!$eK+#
zAPoE@(|u?R&-FOzPG$*myldWcATlq35cO9<158A(*Ua(@NyXoYu-GPz&{tJ?#_Kvb
z(-_b0Bi)3Gwm&~=gRNbfm3zc3ZFH7pki7vCrf;^*M0Oa@L(WX`3&T<MlkGDxF&?*X
z8U<>$=5&YCCF^oIs*3R2kSw{dj1VofoN`FpLBp(O5+6J!%5vBG|8sk7JNtLmS!L@-
z;<HATf5Mwc%J28RlD#osPETU1vA38IF>-C1o!NR)F<osSacXqm+yAUJ3(stVqyCKz
ztFW&QGzAck+Y15Lr%(Y;!kU)L2_X%+Lz&c0=m41eu$&yAlV-T7&{HXvoGg8%xAZLm
zX`uN+|F5nr6o1IZ+cb9HHjpZn=7e4dqC)CITxk@KWU`J{h~o-#y>Yzm*Pk&-eUF;H
z0S4wHd^-r?fj)=PJ9V;k51m`*43eU}G7dNZ1WL2pLjM#&xGQK$IHr{p;ww0!%5s#E
zqZCe4p~YiFF<zosFKmngFLx^-@Vo2a_2v2#XN7)0f|?y#|17;we1QA-<`Wn0W&_*a
z9=EG{tEtz$pSv;qu45(PXuT7GsaGq{`*<V|;|LmHr6v1{_1kS}(f^kk%QE-8U|(p0
z<K7)pVU-t5$)l9s+A@O+GpC#xq7an~pH609IVag|sctV^)QEu{Ah`3y0YV6ip@std
zq69u;fF&FktCo~{yH`i+8%FJtN7+<Yesc<$0!v#`k7Dk-<^G#xaFO+^lB0HGKv<7?
z=F@81!D~*@iukgbK?gY~m~2l2X@d0Faj4B?4&RQ#_*0>R`l6Jm8%W`%d?nv*aPMM9
zG!n)y76Fxg)A)Z!HIF0HIViI1|FQ`><xlDYM;ctNU=S3@D$Eb*LX-{qAe9iGh%-k{
zEqJ;y_1c!#NWEjWDxI^L3MJoavTm>`3n39H_vp77*pi5kC~$X8r6)$zxI#Y+r@97@
zNNdL8Dw&%2efm#;AODW(w#fN7vb@+djP*NL87Sr}y?zS49QZD)Uz6^K4aiNdDnjDL
zN-aSMo-U_b;X{`+q-`_r(@&kT%%{LjS9WSFaVI+mWVql@1F89gyDFCJ90ewa7c7wE
z?dPubgyhJmj=&@l+?|<pg&%@=ZEomoZ(R78e3U0<S(}1DlkZrpTbpz~XG&TX6RP(G
zkO;(RrLyW!om0Dq<)6_xoCPY5VDe>~-I#ja3e@$N--TWfoy$f(o#O*aD<24rDj6bP
zCW#OR32~#kvCbl=vs#7=H0WK@#CopxgiVe@{YrmG4=_uBzkCF!VX5>Q#UyKksNOI&
zmi4>#78%nVKH@?4pJGl0esfv6tOOV7)H_lNR=nri=+lSUjWNsBD2cO)$tKw2N!xl4
z@n)WD_>$MN=L37FyW9Nb+JaSF_aA5Ggys2$JwWp?)s;ZbXloLmKZ6^pcP_>#(=AX_
z!Qw=3hbG%2h=(?V)DdPs30c%?r~+F|72)^TtQBE_jWzJC;p5V<ne6Ezx}>6*7Y=>`
zZr%hg*4QCjqH(F}s5e;}R^-?zCeOA_XgE30$;HMD4IzsenvB`iJK1oiBaNxtFxxxd
zmc_P~PE1~g&Y1~HJm%WK?6Th0^4G&i6VWD^I_s|PI!ef+?;#Z|Eh*uPzh9TVzji~1
z1vpV~*Kf7d9UNF;DPVVF7r`(kYS_(o;GmF3Urhh;aNOJtp)&N?@zmI`M2D2EqH)cd
z&Lcr*UxrssJ~aT@=1`q0dGDI$f>Ud^ycdYr&kh#uq<hJGgV99mUqgZ}6TY3@a*KJ$
z&9HpPdUM$;bntT%%cn*$!=Q4_4vzv1MAv43dsmVRYZoHU;>9u1Y>G$^EyO_gqO)A)
zV*H7k$QyG9foa5_@!&ZE*~w&lzrT5-$Snhk#!1FPR#&kTv)fE(k4Ilbz@<(ImQupg
zKrgV>;K3y>rA?mL5iOILl0a+WAav%m`d#&>@G*}(Kp-AHM=gQXSN7ud(H_aUOReij
zgEYtuAnY-8V^cgdFX0F=5ByNhFEWM_IS$M4;fN6@1>weO(>V$b5vve~fan<~K99Wg
zes*E`rl3i_QMZ5ru>AkRM%Uy$bAqX%bw%z!KJ<&_ioE~4u+WC@S)#lRz-pRBE3fyf
z>kpS2<3^Or`KAOz(J*WfCKx`hn|WyG@F7_x?o@d8JRiZJW=`SV>!o(2u1YsSzqKP}
zwqo>v=t)c9JhS|ykkKZ`W*4v@^lLPM?E(&Rc^mWkYHOF*aWLvqbBp(2t}q@UcE-8r
znoh_zN+xZbCU%>C9#^ww2E9AUo^I|K)G50wAxG~YQy<KUk@#Fu`2&0hCzS-#1%{r+
z-GbN7Ex(K98K2wl0MZ=PLz3$fZC0X_oC&}uI)aK6iB>^KQ1f?NF7Q-pT8_)+{cV`_
z=?qMMPyN!WC~|=juZ|KM-iP5^YI>|L>t-t^g}W?e4oM73Zs7r!!3Ihq_-@_2R(?G=
zo$PI)1CLgg-Xw=Z{UpyW+ADh#M{A(Rrg4NS7y4Ww5qzI#&v2e~u3%OAhH0$|v6pNy
zjB6=Whkp9=FwbUDQ2Kw7TH}cYIF62Gt%AY!E!a68=~}fx#UIf;ZxF_SH55C`JBv?`
zG{UP2nxe=jZ`;B4@79G&xra7`5oRJQ!eY*ntQa1Ovj(@JOzeHpKtk-eDrc*J&AiHL
z-r${g4P|UgmL<R9I)(G_3qVHMTO9@pGgP9dLz()YJ%olq3%jm-Ig>*5@bwT-aFvdF
zL=$d<!cWRx_?ie<xz3-sF10V%Ns<4m&Jf355w^rp=gf#p>vl_B(7q*cqw)_ldqkUF
zqJF=<ueYVrVOWVZsqA+o#3v7Pij*H#1nF!zk@x%tfvSEpp|H7m!yB{z7@w;UgW$1_
z$);|UFW7U(24}AvZjm@$6w@OQDAcRzNl4bRW=H7#KZ!y7AJB&`ocoksI4wYssO$-K
z@aNGT`Owdc^6~7U*G$r3YGTo`4v|@yYVF4(J?xaVZ*p$6(kzyVGIO^s?;ITz0#rbJ
zJVRjv`L;%Tb|%Ao#xQYsd(uQ!<!6&7e<$xjETPasA8IA@gU{usHB?HV94G=tuFns%
zKa81Xh~zx6y7kc(t-)5zE%#=Ezf&`@_pWkqHtg8ms@NYBql<cr1Nfj>!3_^$UT_i*
z#<tOjdjD?)^&%szAEXE49^FN8IYke$nyPY`6nN|S)g;8yypCmau4J`MXv$WjnujId
zTXDZN>RUu$zF2GlQeaWfXMfFd9w>h5FBPq4*M=_*C?AZPIG7ikve^S|dIGAUd{Z2k
zuJ&xo!4Ew&>qp5xBY*LW^Fa<v1op|I>x93FVk+T_JG#FNPUjgjz>Aev)EbPqBun4X
zq&Y(+0!`);4Pwg@w!H@JHtE9)!(`u*itP?8CucJdwzVM}^-ObB-=O)q47n9!3IGd$
zW4G8z^;6vbIOf19{EL=H81bDfQ35+(k1$p7`T1x@<eOtiNK!15XGp44Q`4Ls%;<k4
zuq-#4@|HsW7hk|95Jb%`_6IHLp^Au`^v-P?&c*kn-!VeVnTW{pVJ!OaKz0@P<PJ!R
z=VErKoXnE|u2Ht!K!FTDc}GINywL;wH*x&jKrVm6#?8R7-Ft3FY-+}@Ir-`Hd3ZQ9
z(X*#e+W>*bSuLYNyw~Cj4h-I5aiVh|+_wv9(I!O<wf*@Ry}<gCHaxAR7@}w43<zI_
zFpN`X|73$g?})BiHun&{JwP|&kCZv{^c}}q=i@^||09|-kD4iG3RA3Br2}7{O}VRC
zw$Ng7*L9y!a+u{#r$Bx}lIlAlyr(m*3194LMsFxUp~@YnFnWw3;S~BY4}U1(fK0GF
zjU<PS*-+~$i~Q1wd^v57*kRTMyOz$~$LPq)Zt+|qnz2MM9*xt6*pax_H1z@)+jhMS
zPz6U~Zm)=N@I-?35Z7y7^mM@9iS3fe5Wo<I8xD#_P3+^L9=np|@uptm?x!_%NX~y~
zmPMvr4?cCO)8#&sPpc!}5Qh?Y;efo)81khHk4JX)2aImyouiH=JA<n!<&{BQ$)F`^
zIdH5>)1d8q8Q<`)qW9gFVZi{G;A&<y@GA9sIyO{VN9$^Uf`JH?vB|f_4~q!A>L~+K
z_gTQ>8!O2jSy;9mlWeoJyliIZ^>b9ORwwdRo9nL$BS0!v0wpEL?IWIuwvI{vluLLh
z#Bc#kA@uyh<Kd2e$8&WVB(8IV>eg(zmXsfjafs@DwH<_vMe1kX+mVIxDE%si)>AHW
zyCaSTxOS=(((Ij#Sxpm#(L>yW0d(*7WGTk6`pC#J0e15SA|lFX0Q!fONFFlowiGS#
z=8%>XkX-6?Q^OFRv3D~a$>((=(hhliLc%k%nC;oCB(-Ue$Q$TY1EIijQke$Qj_lc*
zQ8phK!++T^@&U_A?^Z})>6{(m_^AUn_E|HzUUpg}u#M5DMc-(bLdCJs3dW1bb3Dpt
ziPdp@<d2>i5Oq|}2Z_T<V<)1W&9W$+eEsfmPoP39w=z|oXPP4J=OP?zLs+tlL~p&Q
z$C}NWrfy(&+EPV)9%KJBCsCw_-6G*hu{L3lvT!85GV!`_#6O2&3j_*y^<W;Y9uX43
z*#Y4;VcP_#0KhAY$c~<Q%J%Jv6S;G-@Z)PL3r5rm^p2kN`N?`R_+eF%cT?31=z2vF
z_ObN!5M5Z$2>NeQ3wI`+{XuOMr$+2??iE?)%@Jx9+@h=aG(6<O(FVc&9p;#1XoQ-~
z1Aj%-7kF57Q4Y~%_gbp~e&8js0nfz7=SLVmw5F(+g&S<(*c#zpP(k_{N`stDjPZ?Y
zu>t!LmfHHAo0y$E-v<VwJd@{VTrGN{@}w-Ew9Txix0e%lQva^0_bG!a@B_$;%5vZu
ze5m$|Vf2!i_N#pmI{e>>PHTjoLEE-jL%e}~yS1+)H5V(-1ybG2bW6c=ZX**8XAczx
zK||gYn>9$@&(}Z`{m*~<-tlSZf4|Tki1~eRwH5m^Y0mKl_yQQ>A1Wb?;k+D_YCaDf
zJ0B%Lomz70V%0lLCOGB*Qi=khXx1jaI@ybRzJZqZ!@CF$MM3LuUMVX6IbmtVsi4$+
zaZ}S{{!hgH(~1){OXi?W0yzIw^qNqv_4Y+8K&O%URpED3qst}+ibL$K8}$9^<StYy
z%s|g4plrN%PFPWPoBBm`?#fAAc{(7Y?@Pf#s!X7{%Y5*g`pYm>foOpU=867v`e)W}
zRh_0xUqlfwOI>BmSN}!x0EATeDj(yHT`+XCXYCz1Y$j8~-)8j6$&xD})ZM#Q1bsZh
zPWd!RiL^qxV3i_bS&*Wl<m{exu)!W|gqHEP9!~TvH+Z+*;9jpw4qh%{Fc-Pm(KOp(
zi%rHIXu>%gLWMdktDGUSoCNj2Vhhv|PW2<STW^$9`tq+ccEU0xfY+&cob=U*9WmRl
z-+HEAp{Ve}M_>8${3}N;njNdFkhm-<VL@?5Tm@U#c34yt5M6y9Ki}&>+gJY=5rj0-
zWB@iP?_aR7T}ZZT^9d7}wzHYtP@R8KF~m(Ys_A3AIHHEMephS);vBp5Dgei#7-nZ!
zksFkISXo`qX5MYd`(2(SQV(;NSz*(UG#th&ve!-i0Boy&mzHh=h*_hNceGx~5_)j@
zF~|Y@I86i3Lbmb>bNO~wUBA#XZaQ9svcAbqQvKEFL4PCRCyB_{%ZR1lRiNA_BdSH&
z>7>8bY!?F;O$OU}ny<jL7Pb1<meZVER#QpeYgHYQ%lla)RVFRx^@**&{upvVza3l(
z_Ff1zeh@Xj+qdD8@J$H;)vR3lha@sDFs6i6q=+rkI{BZzpV`Kqd*0|jA|#UNE;!Sw
zk`S{$=>`OM%f*@<=;z@s#nSQQj`l#x0bInN6@4QI-<lFC7}L6ggZ$Qsk_4KDNblC_
z-qutOp-v)k0p*;%Fw-ysY_nde4GDy}>ZdVd1iR2Q$$@uKdTJXdx6&caX^1`Iah)2(
zIltP<WNy#&>;N8~d?J~@ZnQf8yS*|fIKOoD5AAUk1_0CUz7(vLu5!PhDI>L&KV$;E
zl?*qgD3aed+_`0zU^O(;C&Cy%;W7CWVjWU}3mGd+-AM3o^aEN9$PE%N8=XuMnuY`i
zC?$R>?h4X9*2D$zH0(jh>9Lj|QKYTV4whI8EXZT?k74X;V-W}?d1WMxP?TkV1y?zr
znquP~^ZwoI6=YwP#Q>#S)r8be8%FhKP|QP@1WAykqPtX+)T7p|Qy1=&dozFc$&nKK
z6a(v^YG^f}S8xxq59S2Yy>N1yG0G5<Or0pCZf`Ku9es_4t{h1A<O=Bjj7#896J&ng
zTv`o2jX?txJZyIuAY($>k}4MHH@nsMX&~wvxpq8}$liy-;sZRRpbJSinlGvA=#+6^
zq)1$l4$Rjj{@EaaEpwOI!98P}>}E%@D~UGZW{R<k)tVnJK!p0+h#N;Llm}<74qkPf
zz^=7%Ya{WXV)O^vw#M9~O`{LjJibg~q&kJ5V`+Uv{P>q_ihZX{2K<BJFd4MO(xU@(
zSEwd*h1(DG=KE5<|8aab_NFI)9X!Sm%S*|DvN;YNXOO2_s1X$9IAH#=x+r(KBV$<|
zbciniAg$6{H}3A*1jiKaI;{wd(^%@bYB~`pS#?MiYedPQ5dMgDKp+?Pss=zw7x_K!
z&0s{;yFK;h7LR5;Lm0ZSjW&s54y=mt2QvcBvN)bN6fs}BG!Xa*qE)3QtKx=pRgRY)
zhj+t9Fz)BuZ#-*A{mS7JPb%2!TM$l1Ys4H-L|BV-%AP&2^0|nU%iU#naOazsT|{!Y
z{y4H|wn{uyD0MaG-MIDr4&S5dp1yJ(jS_(uJT9=p064O08#m*zQG(FUDd)7aP#ZLo
zcwU*Wy_^zns+^|Fu6BQc0ra9WyknB$ulX65I>fi@x7vb?T_w1UZ30!z(Iopc?)j7!
zmTkJ7Rp8Ddw8p@X3$7pJZdVM$%^CHoC2Y7-teh{^4+WhVP%_2)f8K?wSpd&Y-D67S
zabZzO;5*Uu+vjA32RAdUT@I(W=l0pJ%jX-~=7bTM7LVs=&wzA<GLSY|MrLb+lO=S}
zyXTC7R*;`H(jH<mkQG6AmJ?I0;>rDUHz=6`aA|Bac9BUDanU6@NOl?jiXTfO|1e#X
zOm!(TR2GBmTj)_I>LaZ?yUf~y`^QTDS!`EtTov_Y9*c%}ZR01oo17J5D8eizL)I!n
zZQ&3`ellGp%BY6f0=5qgRz^6wTQsh?^-ZmdXn;h#RkwS8y!FQ4yYFivj*OY)e*ncb
zF!6lV+vV7N7vZIizX?WM;e(?x7l;xxFpSE%R@H7$4{$qDsq|x9%L|x6{`r~aSdv{}
zqQ{nMX%s!)X(0X*#_kV$XCi)?ctOzcxWg5tme|(hiQkt@j^3p-e);jIi!It1L^G>c
zfVEhJg;P~b2wecB&Z9~{RthWfoq_ctnU9Mwj>vr+V)h05JjM$KtcjqvzCIn4S`x|v
za>Dm>`$>D+`O@PFA2h^yb?fE|5;;m(*w(^pQrqyx5gZ7nr<F<=g(E9uA4B#H9uY!m
z7$C%HA3LaFRfLdniWq0Dz-lllvOw~;4SfA7-r%ZU4+zd5I`aXTY?PkoG)ob&GPiJ5
zb&KyU#6*UB<rK^MZ38|*62Rrb2@WW9&2A&s&w!vXV$-af3y?z{^bHqrky(RTWW79o
z9x4T%HUuOj{URRDSpZt{j`I=yP%TW_x3=25+ltUlkiv4+9EH9oqK2|chr#!vE&Hd@
zvmdIeLky@3=vN=-fKA7KN>__?2%J#B5zcxh(aXZ&WW&Md{*?F<DjxHf=>QM1Hf?cM
z?RhqiT8<=P8FvX>*76SZ1Xt4+Dmf00iM+y_MsN^!mLV<G&yIw&9(Ab589^01wh?#H
zxOc+;!wD=wg~AXxhkw(oGmt><GXZL%RAfz&5j`fd7Y+`bB)*ft#e<jbGzqnaO~8M-
zr8f!ns4Vdjnvb&CIlQ*TKe9^6JFp%yu{}BO?|^>j1(}_hPxil@KO-In(&2AADpvnR
zM%?!!;oQ#UURym!2FN}UR&9vrL9X2HjCA%-IWqo1QKe~v*z2ac+>$oAN{fA=VRvp-
z6WQohmr;Q!_Sy(3dz`xnGzh%?+eq$ZgV>@*aEey&9wFR>!N#ofwD3bbKji%}sKQ*M
zBR6#>=g(~IW^hFk`av8Cj24}GItYopIzz<F>`RIY7H1iSinSPk6^_)6R-XG|1!G7P
zu}Q1`Z^_=%KRcjOWvM6?!4Ise7xb|;V}T#{9PdBBu)<no!KOuxcobtnef3p3(~ew7
z>|DNh(qatUdkdr*@k+d+{OqviUyRO(c2DY4RQ34s6sILe8H@_}w0DVca69%06$baq
zUso2k2*jgyhkP9djH0{^h@dOWTnLNJ;)JFD<tn<<*g7<iPN3uWbB`Z}ocNao{AWs9
z&1B{3a2wRfvYaQ3txqKjNAW9|sFe8-y}%p0nC}Nts&aBVc4RYzm}!ka64tXi$v{Ic
zc>CFi_hZrv$jS8k;PgCw045~tWKco9$`3o_xI-QTwx0jepd;5R2>_-)Uug)3nMCD#
zx+mSY56ySMQ0v6cn#9ao+e6?FrNjBy)&b6{QxSpli9iB@BKuZU3`R7iw;*(l0Hr>q
zs@Qb?6D>CMfho!QDJaZu_qzL8@H`xa@DR$<VpSChOU+9>IYe2f<NZGR-b(Xf`mt#>
z+x?7(*ao_VUX}YhT8PAT0Gg6yCYO0v%o#X#p!y8(G|<4n7GXp<+{{_inZh+XH=jzR
zK&UQtkG*U9wOim5s$~8a=$jrv_iBBS-9P}K2%5wQ`HNcxU>tOEn6>19a_d+w0sNL?
z#q}M(xL_pPr8W!%oDDmf@Cgbbc_Y2Pkv`cWRd~BglMdx6bDD<W@HPz;kr%d)p%6t?
zM5bFy;&8|&oUjmRA}`=-(!?ul<|V@9O5?JV!vDq=0EaMGvzCzSCBAPK57_Om(N;K0
zM7Wi(<|s_<>pd&J0T(L&`nQ4sx?4|P2ock=tO3U@q?w}t>jy8a;-TW(IgAB4;wUS4
zQ`AX_C%X<8k~CLPxH6qs1~2{C-oSxCO%(68U(O!mHzvR%ml*{@hJ|KW(u*_<bglNY
zSFV=LHd>4g5tOWh(+Bh}Qe{hor8f=4P)&=hBpDYCg8zPxSF}U<-K16H_k|hOe{cBP
zBdcYPqKEl0JiZ?-SleSJJ=et#8_Rf<4!tmOmH&?!#sK3x-lc1-94N|n?WSFnt|hu!
z@V++kwkzV!%)4wY{BsW$LU90vAn@3JluEq~nKRaU177)>w2j%@Y%L8Pt#PBQf*iwp
zf;sNowx}mUFEL{+`Pbn3Iwz~TB-DJa3U_5!%-q~yaHdkvsE4|Ck7h2D&m`=n@Vpx8
zJ&V;*w~SxgKbKx@nItaC-v=CxLMgAm$6i?H(|*c;TKNK~l&exJ-DvQall5N!M3O@=
z5Ba(I<Aa;CLQ#@11T~Z9ZE)qfXTCDUjKU3>xB{O0*ssqE8wQG!zSc+5Oj6^(JM8u*
z7o>UB9eo*;{z>9>svoi*y^g11=lX*E4Fd6lXodL3)hMyOYo(_Z!9wtk<M6pUf|u6V
zBU_6<x!dVC^5U@kYj~<3rDs&4%IKVJV!h@a1i%LE>zfVIWa=k~h$}rRSS)hfsHCna
zx@Mv5oM@zdqiLHic)7U6@Hpo!$Ws!<n6!W4NyBDxkV<A$pC!<vJ}o<iNm<T@$=e5E
zk8h5%34PUIh_Iq>+lDiBdtJuxG8n|PCT1Ccqz=OEOM2QIG$L9|D6d?@pX9o#r6=($
z(8J~1G8JE6Cyii{+HyP{sX%-+eJLnI+<5>e8sNu*a9^`U#1Z(rVM7B%WdZ_kujF16
zSGB=^Eazgx4Nt73u0a$5h##3iZB0g9PzbQcPObR=`*F*PoccwdqBPH{OD?|n04~;>
zc09d&wEGdRs}G>FvZ5za6suQ*Kj^yfJVVpx|E5MXbLm=E*3(XqSQkS@8iM0#r?u}3
z|IK+N`<%Cn!y@sdktzZI*ZvCt8F4MX$<ac_EZd|)J2p#U4`(BdhhPdEvf4x%1;px`
zb8c`~q0I!b&?<5;0=QMZQ%QnH?Y^hUGXw7~z$rh8oz#0*zfKLy?PXHeY|^Rd>H4dZ
z9&nBsE^?Y31);4KrmWT&DPW9lN<E*|Mld9+7hkVFizoK?bWkq|ct!9VDxwk!b(TGb
zpv31|rvmAm3bIng1rbLJV6?KauOlr;p0&6;l5Z@P=-S=`<ws9zxuWgXK^2NXF==|P
zqUDzZ90Gf`tkA0YgFN<ZG9?eV3^QRJ7yvqD^VrFcn&{zs62f6PggtOVB*Nu_(iO_I
zdXQj(TlIf?c*h;i>q=-FX=VxkBVU&m_N@7+Gf%v5)P>*(cy>L}Z*-%62FUzV5Gc_}
zXs|AB|L^D~)?-s0!9M~0chn25x85H@<0+t~@^B0ylmdWO*Re@$!np?2JPn>s0*@_&
za$RNEZK1gJ>P_XoUeGx9GXU+g3goBiY-C;qlTU0rhK!j75K-x55!%ek+l79t3j=ja
zqYbJHyLao%NA~24b>c^wG#+fuJN@4(km_#;i=bd}%z$Qz6PBndOZMBhlcy9>uE)Pn
zrtH{B;5*W3HO#yuZ~Z4IdY6^N6i?)ww{D*e38Vf1gUO&TfWOB#)GMi8`Ke%Gp(^=%
zsZzp!@=R{e`db9C!j`9-jl2Awzhvin0kK;ExE@Y7Xqd{ye%|n(dsKZWQ@l(VhmlyM
z^7#9dDe~+KzA%oiI?vA5N3oK>gA6*EN>XVpl?D$Y!PGp>x-c5b!gVBjwLQ^vFh@`x
zti5zdgOm)<+qz|iIW7@E>wvBreB$t$<<pZAJq8XVSy6!hTq$+fi5kg#5;WvcIbBvF
znYQp65b^xqH1*Hmp*(#m**uqHV2|dnM+S&E3=%hcMWz1dUo55V9B8zxTItshE=85j
zje|qsY)_<U(v8vHo~W$A&8B&4E>*gh)LHTila0Q_SVd3gDLUd}Y{?WViqu=GTbsh*
zPkn9I+#{*y6E*(0#=R5x@B}^1^DV9C-L9}siUmb}E3|M!S$E5m+zHQw26-V=*x^+N
zv7sQc9+@ht;`t09hoJFb*fy4O*bf)4;scTjiXN>4k8mis3Pm(UGJ!%j;s{CTjVd@R
zYeLZm?i`zKSwvHGW@NXVzWg>*uRCHvmCoK@WAb=C)><1$N5)^8MWkafKx0wDa?=Jv
zJk1s<#)D#a;0?T-c99j40SX%)NgjB<2O~RUjLo<{J6afpeDQQux$<g+KeGCYImT}e
zltqNU-ayBg|A~0vd{dIt&ti8{+1=ye2=b5w&H(nA8>$9L@y0EjV9VIRX?eaH++Seh
zyq!d3rL{<6@nRFb;~#9?)#Zjz^rqPyJV04Y6mH#(EAyM)CPsm9060L$zZlfLb5qPp
z0dW5+gV>;4u^B>1FHWvXN!Un0OoPKf1dv{Bq`>M5dz#I2zaj{Chv=ULywO6<K!QpP
zNmZMgv{#oqFcr2ghyA4~8U|U)mr~bsq!d<2niDk!{VC%LXT?HbC5Z?4QqiLUh(&8g
zyadjt+gnzN0wtv>MFebcPsA9e8Zmv;i(H{laCxIX6yv_iSuQ6?urC6nPurcMEai??
z#2Er)l+t77L2Fe57cuv~WTT+K@CAVgM%<O@!{E#a$CrVHa|2I#bMHWKzAd0Jr*G-a
zf?qHKRps7GpQMGeo!C2D#V<~Z2onFs`_wjVGE;iSXH;}Z-{Y&WYFE*rcaT|_W~}~=
zdv1mbEZ|lpKVY#DfH;&7>1=9XS#?^!JgBiTq-M%inx|BQ;8r(@%M5KAv~bkFMR!I+
z11|$|pFHsIT<t3-qr3@lO4zbbSQkf5xTVZ1jx-<rJ9G=ZLtDC?u2PYOZt^Y{IJ_)H
zOJ9Bzuj|D*qI_J7`Gp|Hn%aJ_(kaXZAkTpgc*Vw|J!2^F`LY^m!+STA={!;Rgt-`Y
zB@=fOL*lXi9v3#adX%oMIl$Ojz3U}d>MkOE?DJ9;($i5r0l*v8L~`1T6&9xm#5it}
z2U3CRl3>F>n-Upq3234o^{xb;wx@q&o3gf=ACl^w&1&a)u=0?n%V-jnU)>o(#4w`k
z)B{|oXMrMbH9h+%nwi>)XIg=82VTkEW8gGBHb(0n1x(7Z4Ci`2OS57ZO2%tR=?fTw
z#A9Q7Be7tYWyH8A7)(5p-7G1wfHso44;aQvifw2{R3DbjtZG*{c1|}>w%dTJJ=+bh
zGC9lc<H73qiL=(Ht=Y*tFs25sVsJ>yO?nk)3!#o#*}nPEmt%ndn38!dGQ~R}9Z{B+
zSV&dOGFEtzPyA>C;dePiuh$UQ%*zD4m8KGq;%S05i&cTuG1XVs_7M2C$A{c8Bx;@e
z$%3E49$xBa1x#YWG%Pl3jm^?GJ#d4GnONA*gr*}AO}*ZV9|8dZZp_eNp(vDtT|2BL
z`ms=*1=$l9%BO^GL*n)qhHu6t_YVa~@%hJNk}M^z5UlOG;-Xu;hbGVuzK9Er8s8A8
z()irW(Zh2$v|I>BaRJ)g#a#1>ADEKl!RBH90j$iz2O1C~O8Kvzo(<s079l}*fZgJR
zw5w^8N@a`S07iV%rbDJXIj=}$z*NBY()SdEhY%ieirtXBC8(tuY4(^16D|Em%G#7C
zxtGvpx&-i;t^Hin0)()_tp>~wpM9`VMy9QODPn{zpaAikJVDIqf+-GdXyV>8b1qSo
zyUX;v)kjb2^iyxK{%>qmeQFDyBt8L=TC3XfEO_jT@ZS$m38Ja2i&m!)EV<nNn9?_a
zGZ&+%+J5BpVwN1`62kUipF^U}F%aGfB!qbKhGIRR479f(Pg^xbrcR99U7aH(eD@QG
zGz2UuOMn46&U8#U%5$fj;O=6W9ny(i<M+&T7&uxeZel|H!Bjiq6X3yS7yzpo5{DB{
zn#!Vrj7uFnSMmQpm>GTIT(#feebBi1#+nG0DPcm(2v0Q}PRsIMguYDmUAUF3$7!if
z$daI_+DaHbN{dSm0^@m=SoI+GDE0GBOb3I^#^9C%ncrV^zVdHRmQsA$$kZ|fz8-~)
z>TFgaa0-{7m0^<e@PyT4RR7~W_?B@sK2wuoHHE5QS4R>=qm=~`VK|rb!m`d194y2&
z<w6iv4m>HQU?@L@Yg6z1O1tIM-@o7MB+}j5**u4f@Kqu44!*j2>I3KRF07S~XNZ0i
zP&bcad{LMF5w<^>U8UAE@v1+jrMNDzU6X5!1QJ8ay6|K?`6lG7LIcwVv(t9S`f<P_
zI6|wa%{XY<d>KC-lgfVOC_Z)fClrk3qV}Vs9iwwy70<T1V&pIul%rmGEU_9~+6x^z
za(G*Ib`80{gGWIackYx$Xg$Pq{pwow-$q(g7H?~Z=n-0dz`*&uOE7pij*;H;>P`a`
zn&rb}=SC-3h%Z4imHOsyB_cXNUv@tsm8C7ZD;V#S#VzK~qXYki9RisRVo0mWEV3F;
zj9@l4=|oy@=Ss1}<U}u%U++@bYSyP<MIW!27qk%R<PEvW<#w?FxAp}?{0k&k90;qF
zg+Yr`O1wchqus($XoRW8IG4V7`JXR%5;5*t5gw0~J?RA&A_EtqD0sLwMlLIuVbJBE
z4tb|nq&7~=iSl}LqN}FFs;f*Keh<sIL?f?XEVW?-*GcHWKN3^?v2qh}p6?Mzjm0gI
zxAKjULJK_XmLaFU>S)O#8@?(6rOvxC^AQR#1YaQeP6S(ILAj#%p(E3W$wPh%|4vHR
zWY=NrD!xd!LZmgwU{v@^<1pLtaC9Xh1Hj^;`sL}(0WSJnYy$G?Rdxu=Z)DUdmqUTi
z;S?$s!QIl|zK^aurG0vX60e_e$bvqrI{)Jr_qZz04P@Jm{H<ZyvPK7wHhza{#U3AO
z+pV<_u=;gO4UwT+3CM?TzdizFEz!(G{UdCp8^dZvBy7V&zJr9Zzv9ZJl4hnBhs84r
zuDT1JUPLPmMY%Y$;VL7LqYvT99S}39v;+A%q!L5YDDc)595vvPadcFRQ&k{i%C$s8
zn){gXMS!oXH4j@cdy*Tqy8OSAMOnIi?)$}3tLzsRc|9G$yRoE8V9i%BuB;xOtb(BQ
z!L9TF4VypNgdc`{N?_ODCTVg15O{`pN!M?9=W6=2_QHfHnZ<S<5!ZPiHrNaQl-1<K
z9VuwzFCpKXgc@92O2U4vk%{lGi9k+D!{F}A#Vcv8;Qn<eX+NIJR_&eM0dN_`^UTKJ
zp=eJ+G<0beoEGSsCjsT%5VK-6g{ofOJV*-$0~VT<?#RZ#nTX^<+RqdIS>QBu-ScKc
z^tCT~+g#`fSom)ErhYfF6%al`^D`b*uHFar#EhXw!UA_>-1?9Ql1_X)pu#BffL(*5
z0F#`8M@URQhi8qRw!b}vM&}H#O)I7}nV1O9E;)-8`nR^n6@Bj4LjmwfZUFN~%4i3T
z-mTlu&x7O5T-e0wnRDmE4=z@8mU0J`#5a+r7wM&_sxB51>~b2E-;|5XKgx1=-^8ul
zQ8R6>#7H8JB3-=#-cE`mV!JTiT!r&^aJj@GE^t>CMEq7??(}6Q2S^U8ZG_l5mfa|d
z?#$7Qe0yRyUKb^XZ&UYcIz~zTRey`mbz28JG`;VuSWB^SNn{5z(HKgEuf0e+HJcAo
zo@q~5uye@Lw1tktM~}@$!6Ch&U&yO>Ekm*IMH97)E`_`1L}3pY2dDVE0<%AoSmycU
z$;AG@*%hcX<*exIc7$5w$Bo5G1fEeEDR_A%x~`a4hFvw7cXdW-!LcKl$++Su=!9nx
z&odPNPbOb>@hmKrmfQGofrasfi}U;B<G{2iI3Kl|Cvtkqh}TE{${Oo%J?V%b54l5t
z=ZA++-V{;bRzbQM88mSK_Od%eK9y)OAE-K3lb6MAkE2p~=)G`=1i3J0;VpBJj(}_4
zaq$W!zEl5uyI-0AB8R*)TqjB;f_-sei2DaTh7;CD+@3}y9op2mT~p#pKQ9p%Eh|$f
z&4P&hjnk60!3{+tV@9u{vnrJp2AHQF5QIa=q{*Oz!WI<OcdeI&#RrBrJ^2qq;uSNi
zi*t;DaMLl8Z&-yDKCeps(^XFJx_3^9J||VaU7ML60!<A-Oe5(hGNVb4e(<x>tz2KE
zVjOxB|2n&4?Z`jRyPox)N>T4C{Zm1moV@o(;Ka+Gd!g)Z4>;=h9YxQ_O1PppokZ{R
zrB1Yq3+XH&J#)5<UN;A6XgB`ar0w&{)J3%SMEOF^8#K-?v`b0)(IrLNI;71wwSDP1
z>IvGrmv{(|9(Z7eG16;M@XCmdw-^I{p{7J*Gy>ypQO!jS2>7U9O!b!7qnA}Yv*vXm
z7Xz7$+57Qkb0$00#qLqmBsZaWRq^3X*#-y#5kPLKxO1x*23pXr>5UmW)R$A``n%+^
zmMXWg`&U#b;rfZ=bHb9Dbo8Q7ArZAxOUV@Ju$Vu&##$;uhTayhN1{zwlhfsG?>wVZ
ztrbDr$6C&Vs5NC&e-+1A=J*I`5IohijxP3|qFgmrmU#tb1*M996=?cdqhOA8%w={>
zvw$@d>`CizitzZV{I>z6D~jYd*Snwgc{~Pw>niNB>74{E-4W&)4r8+1N`oFWi!I5R
zEouL2DC&q+$6EY`HR+R@@kkE1zg=+{va+9@(B$LRRmq)8w58sN0#xm;p<3)8#ZT_*
znI2_PrZ6GQ9a@(@<)6~4wYMH_eVP4?2&+QB7Dp{Kcrr_KA2k#C*BJsJAtF)%WMbKG
zLTKf2vfpHggDC)08yDw&XwqG1y}()>h+Ld>jmXiupS=pQ!JIy42mK2dobnGKgM0ht
z8Iv;a>~7=qX6Nn%gpi&rF(9%&4udTb7FjE9j#chlb+7_gd@=x=7!UN7MJ}Rk0>Y+h
z`S|)mmUUl0KEt#=gYs~+O`SlxCQ-6!BFA6!I+Vrie+O#Pa)v1vgb9PQ=4d2z0PO%b
z9D&Uhs`zaRmb&Y|K-tMO-WQlo-N#}Qxzk%#2`lSc=h56Urde}&!m^tIzcc$iko0jv
zXH-#~80?`-y@>r*O6@;B6TA+K*9G~Zhf{4GROqi}i}yyaw62ShEc)vNnv?m*15b*)
zk@x%D(x7rYhY(2#ZAC<QV76g%RZJ?v$HH9(3^XhZ2TO`0mF8?uQgO*K^C!c5AZ^7r
z<nqKiIB#v}yi&{md_P#}vSXxKirH{+!WnBOkXrw>7eLPN4hg-uQ~16tyP(-ld+QwU
z^nkgTU%XbkD$ISn!7Dzz?_k$mS#e*sP$2GWLzGT1MokvlP<oqa6_)l$6#$Z$*l48l
zk+FWq*Ug8Vb_4?{d^YkZLPoAEHe!h7?36e6k~=9pWIC<G(dnnrH?v|7_%EYE=SU1Q
zt@978S>YG?L5X>~yzmNrB|f1QzyTgr`|}z-*(101BkeJFRPQkWg^(Cdaf@jT$6Nz0
zqnj_sK3G%$vJgzl{7e*veCjL<NQsyn$g<Yn3ITRA182Dk8PbE>B4S-^4I10Lcb9C-
zmHkcjZk?R34sF^wk}<{xUYk~tpIB|*8HNagb~m!X-6MLcJD=4O(rKh*hW-bv&?F1B
zF#{|wB6-IZjnHYtr42Z0=_GF_-Zb|guKmks>snbK#2Y%h18-6STFog0m<EJP#)1Sc
zXI9<GIbM@%5IUNLO}pH-vGcG|Qyxq~R;j_GR~>UAlQN&4f97}T^o_s*7ly{1*12QS
z65xe2q)}hFexbe*he`bxsba*(D={gDp6YcjlYCmA74SZ33f2*nM&|ux8C-k8q*^=d
zeXENK{p)NvcXby?+U8jsTY`Z&)%q8m8QqbGk71idWIvWA73BaaXl#znpUsMl?d=-;
z?D;~Yce{!rATUJ3?7Z?%frl1dkBnK|)r7m@Q9!KoBfF#M9{2n_b(4y$C7uR8mC(W$
z6%Of;xgE~-%T=FAs9oOGpUNsKOJHhc>1aBN<Y$FgX8sqEJ^i76UG_+h1vQM%eNeOf
zMG=o4r>^gAh>4e|BN}H9hm4Z1$5$hd&+RItRgtp>Vj~C9mE2%geOey`v5r0}>$^Pw
z1VVL`AR-8X@kS5z)bt`=sQsAT@jHV*Used<Q$T3~%%EO|KUN?w;TAhA72shJLEPQd
zMlM*<+#nE8lM>#NBqta(wv=}k8?h8kRwmMFeHM@b{7C!ia`p9vx9M<Q`|wgGDQ9=C
zyi-=)WhxA=JL(068b7$D!AJ$=lq}PpP}x{wFNVk>7I!G+mg|y!+d%zjtg1=h@$$^%
z`hrCq*Bx0i;$R6FNx{!L)p4%VoSaFsKA@tG))x&ZK}|xJRIn;J&HnF~#al|2ucUj4
zdWdZF#r4(uy7|_hoa>0J<DNdr>X3-VFdtl1KJB|=VPYyI+s%yKD0CY}%1k1{6em7X
z@tVEl%Gv(rl;iFM&p*)BfGGIus7t!1<Rw>g6J+d4LRjYj3#|~)lIx;ce6JOU6^PY-
zr1`Ht9xiT8J2)4Vx+5m4|0O|J!A8yy*GI8gV=H-*X`y;JZV|U<63Yq7JHZ}Oxp@&Y
zkeN!V&b}LiP`ZDBQ!@v<zl$4u$)DY<6WC)lFAZ<>&k%UXy19AtR@n+qtrL5Y8|~;2
z(%u6&@+pKU604nu_(Er&l7ag~dGbP*F4cQPO%C~<TeCL+hz`&izDh{&H4=AqWCK4{
zoAgEl^3lQcwO5LfKr`V8=8ZNc7Nvcw%!+a%OJSjQ+mo>;(sNOBM#`ENGkLTpBx>A+
z?@;VhKTN)~3Q;cHF8t^EM&)C~zVx+sY1A1yc^NxNx^EWvXmkUB#X&&(TDw6DQ^ywe
z%dHbY62dr?Z=422r13$Oo`zY^C|qM-ikSfGo`hJfFYH=d&=u^bQ}HRw@5Q0UqD?Xg
za>v7XexHkGI7@4V>{Nq=(bwY_$&M-scSv#$ubcU=?sfex@lLXD(|ABwqGJT#vMWwa
zjKSF51n}9l<O%YB%RCXcTYIa02TR3JcdpYt%f()3Q~&)Oq+F)}V24bofYvTUZdpBf
zr_Ta@qAq$~hI!xCg{&`ct|tEB`ODTs*4lJB>K}TRj-~dCH-S8J5TS^3p!(DcgZ$C5
zYzQrS+anz#-Ip~%w+;dW^jOa2C6A^PknFl*?gE4yut&dOi)=z-$+=8?@dYs|wtH>H
zCk-i0EPx*v)B%tfKJ3xhHwhWZ0Qv=+BJ-AR^7?2Ee5?X_3W{|C1{1PgviS~nk+md(
z<2;tv<p{Y2R57=u5f5X0^4<4lXGHf!nzTuXyHM%SV3y6k$)7VyBiY)Z??9j3zDoZe
zyJBi3Owz~M^@{Pn>!4bK%Ii@X(URMrSKCD1n^V^uvjX>PP%3|15(=K<MB&=%M@;#C
zan;=P-66$2%)}?@sDUI)a|lc5IUCZmUbETqtFC(Rx}Ym|fXCyc3=wX-m0g{eaWT_K
zq;kQRmCgg=Am-NeBs+ocn~X><?q1<J+il~=)*HOxI{);AixQZJkdWGfyUXX(y1Q{_
z=T5z;QO0BoZ@6uoL`kA3h@vLwU4*GKA<6H28m8{Wrv8d$9kwdtTCcg}*aGPZX46w|
zIDsI_(+e<ulzs2=^L+SYvaYeS#oXe(n%!6Z5i_SRj7shzq5erh(bFoEeW#;J8}`qY
zba3JsSA^-;<L6<wz9uiCqwOkR6&19|ciJmE`PXw~_0MA}6LTC93c3-fN|oN4HhZx0
zTpC?b@Ns$txqoF0LmdjGDFMV!h4ku<c)@=*<hI$|Nh)P=)TKTJujio=F=sRuf66r+
z2wFb8<qN9v+5UTSsju&iH23#pM?s-~l?DvZl~F)BF{?Uwns;pG_v#1igKylPfY2A<
zy37{V)2fdK5np8{p=h{P6z_)tgA)R6_!&@rBYn3qlJa{~Ccz##BUE&~9BrclyXQBM
zb-;w4W&nN7`b*qFZ)@0<@q_M6ChMhWU(?%?={QRH-ZmycRX@mSF4`3$+05@-ftuV1
zW(qTi>71pl-cU#SDgO)1CXt1LrUNt!Nw4&946!CW>rjs*Jv^yO`*Yk}?qHiR#7cc9
zQfgy0q`ESp_HZ)BKAr`=J*Le5J!4!BE~_rE%a_p!9G(DxMy0&D%hg)t-$h5Tr2Wsk
zK)#t`an=5E76n1lBJc%n99Y<F_*hrV>t}cIf1WzlSau<y5is-%QaXG?mvS!@LO+51
zdY1zV9aTie!1mx=GdC{)(|oF(fzwDe6Q33cws0~gw-@8-!hissbG$eU{ThrjX4tDE
z&YU!XQq(|cIbG3M8UN=FrrD`id~6}~e6mrPAYFjzd0$f2BN_A`&o<fU*N-fDy7=u1
z+Vh{Bi!BYbl!>uhzlnbPi|BfCR|w!JR`Wl;n|6pjHwr`}&ZwfHxqcfRFQi`K;6TC*
z2FVN2Bd(qQy=~kEFD=yzu%MHOb%nIVp|yk7TW{4(bn(4q28?$C&ZJs9&U<`wQf{fg
znUu9(F}UM|FI+CRDK@*zIE$*{0lR=TKSWIv-lcEbedL#86?fMh!R=-dZr`Swn?nII
zVlIuAwg_t3EL&qBnx@PK#QpLJ>Tf*xEJA+Bh?}@FJjeg*s^Q-68Dzx1xDO@qMtD$<
zwO(sABP>6!8t#n4cY?5$?R6`BJmIMi|Fm1@YWtVtW)E{oW{JG#V=9x8ITEPWCMM&%
z8vBJH6FYZw>+9VD3SgC=6;f^}NXnj`=x`#QV9@jnyb0e?Wcoi9%k#{}2?0J$)V|Ml
zw0Ek%E}-i`#{OU}%$RELC3j?bW+!D39q8-1G=je~#3UvVwQU4t`ehgIn1(djvaONl
zW0b+kY;y9z*&tKP(UtzA2U>5CF3AP~mUwmmhCz1=xjj?w%=r2wvW$DGPNM)p$LmBq
zZ0#v5G&VQo!)60x^+n>%(8)-g7aBM~39AXM*O@l5q(PM^cc3<BiIMWqZj}w3*?PtD
zkM$k9vrCR44qKV09nVQGg1aIjm@+un8@|RL4dgjFEC5$`I=!J%#@r}31SuvB?7vIt
zom4T1f4Xf)SbGzGqa#J1x1KsO_+qcTlg2Ij=j}oKofG-mOYuY3I@K94zqESb!fuSJ
zs`89V^twX$bLVNtvYvAM0Ri+P6kT7G5r@<AyifRV>54w>uvX3g7}lUWDN#ix?EKZ~
zM_2>nKc4O|V2;-&eEO7;>(da*5~RQqCHc4gKhW{S*Om$u6Y4^}Mc%KT9kLWWTXs8W
zLo?9X9FUx;?;ThejeKaa0<#5_Yrl{7_yr#Zb3=2#>F{#w?H)*<DXv!SOljYtErw|D
zMx{{D+(DHX#&mjb_1pxr_qOrST5|Nm5Sm@tX?x6i_s)gyT0rw(fu$mZh{?giUHJ|I
zn+?v69Wx;@BA~u9kJak`Z)14?tT*Uyw+*GFMG?F1!B3`61y-wnYa1(H$?)`hlqd(y
zn9!?s|0%a3mkd^hVKJXMP5x(mb<9{(ZrTDv>;4k0Hr5!$M9R`_kvF1-avg2v1C&Va
zM0Pttq&Lx&YAnBs+F)xHz^Y7`W1C@)e@u7dDEpKp(XKb<I-{KZG^%G`iuS>QyZ5tW
z^tpbL+?=FdvMj61K?;p0`;k_*DP05On?4$L?QgYK_VR4tbs&Kn2<}&_p-i6mN)Y7k
zGo|%;OJOPR?>2{$k3DlQZ5#<7aQdCtDb^?06@TR<uegJ-J9W;DIll;9r-~yXxm{7%
zjQ)gv?bT7i4{1@Z3UL{f@!{j6+9qm;Nz7Q$o#nT^lf5z$o8K`CnaS<WQACzb3ob>6
zk<2ykpf#rMN2MuRRF{%2ZwXdL?o0YznhgTpvCcrEZ&ARkoB<m=QNvm3p}PzbaiSe6
z!l@FuE+4%Gxf}m6(qCP1X|53GQn`-$Qyf|)<iNBCYoG?iAO_F>g#fYq0><;O)@yO;
zYBg{U^2qw{Ds*}yS^Qf>2j#d*pBFZzShDu%EN#>%&RFNKGs^=HNcZE{N-r~flIUtS
z3&7f@(9QBOZ*i*@2)ouMrLl8C2n`kfEBvgbV@fYA5ty={;unLRkAoO9tW1A28GD$Q
zDBX!=N`Bt<=lF@M^9$7*l3Ffv84~At7Ku(|Jn(elb5T9JeO*gFD>&rk93HS?*5`?|
zq4Hh-&qTY9a4|h|bB*->^`-3?AE<>OCFxz2eR}807QUq;x&*{7+)i%;0fnT>P6Kl%
zUALe5FQFwuR9a3{?oI7{f-;IHjKgDk0>x_)=yV1uJZzqRoTftoA8Xra@Z|&WXCLLB
zPTMM|VhKMXrC`&ZfAwG3Ta3Vc!ifQr=TMUiHL3o-E>80gbY1JrNJ9xvcKPba(%F!e
zK!Yc1>#f%NBgm$%b?MDz1bS2HYJ2ccR=bSii5px`@@h!d&!`~o-Q~!(f>2ZRqv~J@
z3wVtxnQH@KfAV6h59IhY`~Z=py!YV>=>=NDYq~#VF|<faqYC3vAaU~Do_zL3?(_Z#
z0YfEy)7yQNm3?K4ui=oEu3if$Z<=0t4;FfDC7W#*6a#ayp{=d+IoqNSy0R^W&?~D;
zN1^%q3GRT!IuzLfHAbC}Xv?mdFev0nrocT|-qsm6F<|+^GY2x`FY=QpBUMta9>VVA
zsskMgFH-R#vo(s<+5|ykZpEtT1fAIq#EH1ovhH1p7Y*yXSg}~7v6<}9k3L90v!ez0
zg9{R9nHb?0;J-hgb$Pot^m)79t2U(*dg!DjgE=GGu4~KO7na?3q`o$J9rSpL`2)3S
zfi$;zz#`=<%60*~YJ7+_AuP?qm)Qw^S2}>^^0eZ}S<G7tLhoD4uswC552SaaSfmHW
zJiNX7_v}ul|IZK3m9P941iLXUp)J;+dPZ%-_g&h~F@#Ts%C{s&SAUTwM~u_fA=i#*
zMuFpih8jx^bmgGjDYkZ`1Hvz(sXV-EW^+W};2=ol^F4jStjVQ{BEaX*hq?5TGs66f
zs_Lk=_9$pRms1iP6BvX#Hpd9^);u$f`3@dF*`1Sofv)l9gCC?a_%uXlh>*@ft~{B|
znrBE^{joe`-0yns_9pBISC{s-QGoswdFe9c*DyD=N3^6DVg#bN5_A|GK+A}|X|!-c
zZrnj*6+ycZER^Ggk+a*gzU5NOW-7*T%5;$b9X<Sl>47mc;*~vboh!_rvVWEJH+REv
z*LhW#{u0F(Y>KVp^3I`KOK}7Xx+f(l_6Yp_gW@ugxxb+;K6rA64yULSatU}+-7(Tv
zi0CTW7gjwu*B&}?zBzC6h@BMuiif6~C%cF99gJ8G9MaE%RCfmXN+YFlvqObgSRQ+M
zmBMhkLKuV;E@|S2;R6eE3*_jmdSH-m_56%tZ|bISZu0;slQ)gT8MKuVnM??QfRDY>
zzecbU(!(ex5hYz&gUjweHCU9N9{lY$#7Hc%(|J~rGNM3W0nM<bjMAGynL)6ggA7Q*
z%?xH=)IF%&I+_g%2kOxNVlnC@e20O*7z9bg#h9FGucjPiApxKOqapTPp$5U$I^GbC
zHUNs1MhsYZ*fNXRaBo~2%gjSvb5beyQmgvQM>W>>Gr88xCjZI=(*RZ|$3>`yc=qax
z@{_1{c`QCDBJpykR2c%#MFV2wU;MoI)YV4JR;&^%Pq>Hz!*C0~9ou>xFpHg(lCnS7
zy3_2oUrIj?#v$p|y)mPXD}`XtyQQ>s9ppot&}FqQRi?k4IPnn9gT7rl0^I;F>PE<E
z4#G}PGs7jx;O;^U5|q6}kCdTb%_MN5fJ@5`c&RIQJ2G`)3t%<d(V0XgaP{x@Jb;DP
zR@=|mip?>o`J7vbRYSC7yKK-@9&)**Mz*G-qx#qV+esisU?>rtT4B3P??#J7*aP4y
zE2Q!cvA=tYwIW^2O;-6d-PvaNVY>cMuO$NDU^7+A^K)3Y&S#_+*?gjg-_27$T(dp}
zvpiP+k0G7@r)<L6yA1B)5_=h=u@4Z!G80x+)kt=t+vRUhlY*<q!#l;o9guEku<OjH
zylX4qbDq~6QaIWzi@K@5;oaM|2!M%5F2-^w6D^w@`9h$Y?9`4wVN<8&xk~$r$RINp
zuUa;ZhkI0>QOcYi$qPJA1ND*HS)+VPwCXmQDd$V3{v-ufv}z)GlQj-1C#`84ufnpy
z)Sh}Ir!Z&*>tnMz%0iCZu>H|Qhy9c?eR_&l3BnF&?2MlDXefwsxxAU0^}ROn!v1pB
zF$5_V^N{>DG~=b+4-X*9?Bml9G(=U@t3`zPb3xbyCR_uc5kkgxLeba}b>41WXI$I)
ztq?q;<~SR64ezB@xVoucZ^)~rPVwy{ERY^1x`?r~-OMakFry39r6u6W9s4S1ry<{7
zlJ6!`JMz{WE2kE~y+fdH=mYm-(Uv3TOrNure+TipQ8wZGBuUsUiRstKS_r)p(!O^V
zPdo-zLQZVdL1gG4I)1+pi&VLNe}YUWkOfMg1r#pyjV>wf1hUPY>9NYr&tisg5fS)i
z(F|BTiDU;7^Sj8$0@`y*0;QB*dCca2vKoW6*~aMyApAykpLHD?5+``tc-C8jX>^+2
zjzIQFc>ZteZuy>`Q*?~m1B6R04#qqq?p;&gmx(&_7N4A*!(D5qD-NoYa$C>Y?R(?a
z%kDRSSE|=|0sD=iWHK^snVlHorHwIe)DGfC3ysh1+Q{7OXauFS-qKgD7bzCZ`4@Ua
z9!i;(^E&Yb{011JZLCnpYqsz!)05mIUOoexA38g9*a0BL!~yozI9MD>f^UsmK5*3>
z!(xePbGZ$D4?TqwZ#8vsIA0Dn;`scOk_%je%`5Qa<6OSbxQL?4Pp6E_07d<@?Qmme
znnPrt=ay7*%;Xj<OS$;=u_4riG*SZ|7=i-8Aytf1Q+-PoX=a5rWkOIMxHuG-1TetW
zwX6HEF=2)4^tT#A<!^a@SOx=~{Y8)#{g*s|$?U4g9KEEtSh3AmC5J^wk=}0b_*ygE
zhIPVaH#28oW`}Un?*DH)5z;@*&q!kf<Y_@4YXWaIkO*8q7il}?4Un7ua&;cZ=3m@p
zggWYg_n$@@UC3fqridKZ+U;^jp3ld-_76o#9P!lwV+0v}24tLT0OB|R_aYmKN-=#-
zpmfoCo4cJ1KIdJ|uxwNXNLG!D6EyWnH_O7;YY?A?BV7%OltsP?PKCs^(<P}KyPuV|
zUl+bWbL!&dR?XIOTMwaw)REX@o$qJlfZF?tkLm<TdRGb8D#x4Ea)Pfh6Dj$WtEb6I
zm@U+kPCsD?py?qeR|A=UO>#$-$bSD_!{OJBb3&$dRn>~Kqh^bs;lxv3UZ?=D!mm>$
zLAmFioJ+^Nj=?xmo=I6aOzgX=QM*BM4CT5q@(mdoV|a$)NbuvNoyX)*7zrzGhF^Ir
ze$`?v-zb@T?(Lr9#8b|tSK&ln?X;!e1F)I_Lrz+$%mLh=sJ4Pc{ieNKenJm$knrI7
z@&3b*tYsZv@eQj%VG2}IGPwB){O>CX5}qKw3vD3up8q@1<8iNpz%=#b#UCS8C=@yT
zo97!wdCh{oMW}EWRub&4Y&)u_dH=+gd-1D{fcMv6TI$!XI9`6EzN|5P=B#}EYeUzj
zZ%WYv%xy<^hq+jV(Vg<!D4yP+!8&{naUt|`a|tG7m&UtvdSFaXx|J#d&8rW>iMa`v
zh)w*L-y5X98rso{F0ly|zSXkpnnjr>ll4Q|9noJ4G+xmJjEjpT+!OwPc4!r8T#Dw(
zpsnH0qPJl10*ddx(OS5u<RC@NNLz2RGiMFjC!*zOVZrA%3z`zur;>j`s2uTIISTgQ
zf_5fDOXv+fAmDX;5j!y1ok>edrCh?(3U6BytbjfH1{}C03=krB{Q$CH@e<Nq=?gS(
zJx}E%#{~V$1d#yVSsBsS#}#jF-g&-DdKsy_Vc%9HfALRe6MaOIhV(d*SS5PwsXz9X
zZpJb%UNEh|H9$CRGN4dH9-0%256ff%klSU`U`K3=RZ9#=R7Cz+Xs@5|BVCGr*|X2)
z$K;v2kd%UvM;j?KPic^|)$CN#Lh4>8yDn(kO;Hq?0dUn5LHcQA{Z7>+n!9*<K+*+l
z4kDsNDU7Co^o_I%YeXJOw*f;|z_c(x9Qmh6<;yprU3=HS^ker6V_ihI%AcqHHNWWZ
zPC33Xi2p6@BB!}#UtF$EdhH<+>&S{hs@O;Po2S~o>eR@!?6a!hJv~7gX<28EL6~~9
zSbsh;hAL%3015y@1;-%bDZ!H%aSlbglPxr(4Yq(4%ph?2Lgs_y$*y!`41Kx8U;a63
zbgthAdx;2~Elj*h#x9)HKSCoIGc!^YF+PtRT=Ro-|C3=(P$B~+3~rBO{E~`wWsc-G
z=sF{_c0I#;a!5~CAk42z?;5V{m`E^o-8yZ~g_t>wYZMXAyJTisx?K3kO9?g1>DES*
zW?lA|O)baNzF(Ps<2E{S30#PEFRY|*-j$f&{VM*f!fWR8yBnYuqbsxvU38WRDrmZ5
zP#)baqMAM$;wt<@;(3C<V{J`5)xSZdt&EpG`f{@n*nHayxfcg;li_-(5}9(Nr(^Rw
zPNB_h$+A&MKbpis(q!4cH4<i&GeJaWa|`XlTZLNJgXFw#tGr3+d8%#YRtd6c{@9z3
zW*O&2_}WlG%u9VogBXTWp{WG~LG?!fRV(4=Zn-~l*-i>oW%wU*@X7UPewn+csT>GN
zY)j=|OU#1l;G9hb*c^kwK`4OM721rtjGf;qK>UuR=b&g_-7jkD9~GVe@BhtE2LkNw
zcPXe2^t{-2eMAOB_=(K!Ad@woWV3cmM$7S?i1}`mNd?79clB4$0@}F0(QWfN`&YB<
z#}s;E*ca$h(Uu%ldvB^&gBdyZ?fjpRW;<4w!3&Z^OQw!-fXs3xSk?N#`|~kJN&(*3
ztNe+kSAtyQ8x<7_&q7Dvnf?{}YnS;pFZHeeMH1v(EhSTd9XAi<?g4f+BMSkM!TWP&
zx||ABS6k2a-g8vDG2d>hjY>hS!jvE(Rjoo^ig9)Hax8<Y9Pyq=_AJ?FTdKX2JC(zW
zk7jR3vufLET1`tE4CVSCZ;gyihsOP>K8b2UPSt?)Nv7mfFfPXlP&adG4@A2IFQWYU
z3(OA=57<%M!8JF??&&PulIk!I@BO|3C3j1-^eslpZ%pT94sBhKy1<SB>fo92o!R2H
z4|qFm2)?)!xg_s3co8xiL-!kD!YoeEIA0@O&5RM2<sY$DR6r#I4yD6P!(u^)joi;0
zWGd*M7!Ezf&}%4i#S$d1VjnYwy-%}&V+o}N>hD7sJmVQ*X}gcqINsCJ83I(J*Jz6i
zcV>;&pUMOe{gHOuy5*ZW&WXT(y3y8n@xYNxwM^G&lM>!xtJI(q)QR}Beha&oQ2F+n
zl@i!@)Oo*d@uqN2hkB5SeDFOAgl0UO1!1Y2XK&Z!V}>v*PFV8+{^2C5qyFi!m^Q^*
z^G{1O;NQ<LKrPfnbI8YWfavP5ZAC(+*hCj$nrT>#Z5}Zr-AKrL9&FJTj6w=-n<^aP
zL6QYXC-z^|HP#hzdKxJ)v{J~c%UFvczCWl!lu9gdeL-tRx|v5-;)8o@t@fU$ym^YT
zXi|=D6Josii14L0vYn_Zf+W=rdFZa+PIh3T#~yL5x&=6RnLE3G%G3iPmMteiSGC`1
zD1N5`QDsD(FcSbu$Q7a`k+ET+K~7voy=7H-oyCoh`)fwhQ!{G_^?5-mx^PZevvO5b
z<4a2+8MLaM@Bbc&gHK-B2^*kze>Janj1s@TA8B<KS1Q}7BgkYoppg0nLVKVa2_-xP
zg`*GJYaj|P;U_cMN>M0IVlposkiNJ5Rbr!d<PWX!Je^xreo;PO=ZGGaQ`U`H5hU?D
z%{@)N!SxA5w--Ts6-9BQ;SGTmDJDrt$m>roErY}V+VZxLWI<J}Z+Lfq{@QB|TRmlR
z&awYT5vuZ+s^4MZP)c7<E!35&PZiq4P+XUm6@^LV?}F9!h6H%&XW}e@RcDg_yPPBd
z2*|AmK6u>927oeK%0t||?`Mg$6MOCsP2%IjEN8vG0S~B8y0QhK#Idb>&Q$_u(C*HP
zVVWLi8E2~Nf~WJt%@{(NbA)g}^TWEoyg>m*IqC@FB@?oEd%mDy(}HA%#AKr%&jAUo
ziR|jvwS(6@YB7Orh!ZtB*A2uTUx)2%6#AlEe#K__WB1}<8PvE(`N9BP8c`j*ptho;
zgB^P(xds#4$8rj}Bsj<r``Zi%ue)&V_3aeO4jl60(h#RKYHoz@CBc#tt;7OZ#;Efw
z?}^Q0H$IQEbVL9vxYC;`f*?7(7$viN-?p|ApO88`HRuH?Fs<Z0Hzx4ZFIXE62wcH{
ze^LaOatk_GvG3%a)$epo6$Uk)QZe;xhe>*u@b8(@%tOQpxXvs7CIrwJ@I&b-ZQ7i(
zzfmSzVJuOuKG$vuqB|L!n~&h*lC;hjXtEqGU<ae8UIndxF3LVE?A;+mzzPh*hBOaP
z7yO5t?&oLt1YWnmu@o}GnyFS=keoE90HUEf+9M1aDAtBe>dSoM#ot|QbK@Lg?w(5h
zU~`lI!9M562iRoBR@evQCWIL*kys4Qwf&9JgrWQYew+T#JAY|bfhAhyM<F@Y+9^0<
zn<QdZgq6@e{GS7xxSgiE*SB-5Tn07j^g>(WdRU(1#q=aj_dTtc^B0wHdb4=Y>$TRD
zN}T8V$3PX+CAs^#P!4kH<TD#{Nw5uaD(PITT|nBN&`rmBE3~oOSh_PnV4vn|JmwpM
z(mirxTkXHo1m%07O&`Z21@`{0)g*@aP%?}t$A2PB41soaruF@6|EH9p1eB<9y_e=q
zK70Vto<&|~RHFQ{hd#`s$N8FT)xTTAZ@YtuiuAjz=`HP>=;gjYz$lO*$>3lMev;_l
zJS%5OS@}pvly<}Ni%;$&ynRA;R7f7eeh7}OdQ5mi3F(*3%nFuMLhn(j1VpZa_cj}O
z3}&u~Uetliocf);)ZGGQzPRdP6hAY=Mw%`Fb0{Z(#9{4LotVFQf2DZi{RB%q-toX)
zVD<w<lyh+0T_B_T7_pmzNdBs6kRib4%J#S)2b%J!B`1K<BMdA6Cb@lFo2c}iupIqi
zcIa?7Hqi|)FejF!i4Hzr<_I={b^lXvxSp*t{Rh6lf9>-5PHcD~H4pHV$T9@lF-}t>
zb(EGdy)u-Xn8USGuYb*InEsuUa*OKOG9~=BDx{JcuyZF=G#|Ez`@TOAJI#lRH~b^G
z>Zb*B3LTW2=V=Fd0q9y}lmLK4M*L6h4%<xOPEfq^JO=Li=b#1byM?A?2&%w7*#3Gy
z;9;Y*H-R}&C~Uh2p5VL*yAM%U*(&FD3V-O^q}{uF;^7+}x^I0opX<1=2(EeiFI}az
zd+SrR$X*_)83E}_<2jKE-8Dk?B@$+gJDA~aFDNYx-0_ES)};ocdeE6Imh|$TqslA6
zt0)#DZ)?<#VZ-~OEc4{50|5od;}3d4AKP-$->2R`gaUj5Rzq+CDrn*w95M?tFR{O<
zpqtb)J4Rs%x#1DrCOFv5)%vLYk-}2}*}L6iqxRT*dq{e}&1j^yM^xUJ(@4*(SHcVn
zEaS%8+CA-#U@c}#*O)L6Qz<u>2*F+V3HZ-eXWdY>HNV+(N)nQ?^H($T(JA+XJzUYI
z1AsMZj$%+wqvq4~X<u$%yPsFT0Rq88_P@kU2$sTM8;Fq2yN#&FcD({FG?o1zESCOF
zI^;?x+R=5<(HiowCK6C%j$39IKb|bXuE5Z$qy6Qsd}defLp1Na%i=ungvK}d4Swih
z{bo`WX)8HO(E^*?YsYGGz5DiVLv-Hh21RqT-y-JvVV2og8uFO2N{x%lRwvk=V3RJn
zST1O&3y)Qupnf%<9O9AK&Gy2>VoGJ`vRMw#+{><j+x2E(RQdEs_GTV|k^TITa@Ar3
z8iJp>lxQMj86ndq;DMETO#iDB509f0M?4BVr`Dq;emqg&KhCG;V_a2RO|j25DGKFq
z@VaBUtsi64s5dF0p+$;E_th141i-$*@%{z*VyePL9M;HWb8VNG8f51bFG>wDR5oX!
z*m~uoB?P;`3?(|PA5l{Av+CidNCm*|6PqiAh-7{1dn5~PAE}fVv0Hi{VHHA&zP|m{
z_U!SA*<3~ng(6hvahQeoT|bTjQR#KDOZQOwmd1rl@RoY}nf}1Vt19!pByrTnpuAJl
z{kqlNwD;<m(YD7RzCu0bJJ(s}f}swwz+3R`+U~ZQbWRA`TkoTaYZ(Q*_vabQegsF4
zJdx7(w`*hl+)_=4uaci|iu{U3KY3iv1bP?=tPCkHjKDkwTc9Wk^xbnr%gJe)Xx*SV
zp-(mM6!(-f=DktSrYzlBD>Kf6^ge}iI$dDs_79*>!Ap2-V*TSZ|0QbuGt7AINRYGR
z8&qN(W`C72;$5{ll>^HC)|=zb?u|q1`lTqH(`Am1n3w>Z)m1W`HU+9o(N|x=Z#H#x
z)g%$Cz8^^Zd3SK8(J3h!ADuh5UZq#07*1#l9&h9AV|W}GJqAg|YoMMNN99<ZDEs_%
zFsBsx?Z0Y<0R_4ZkB0Q?hEm0Z=P_WW=g(4F?m!Kuzj*JXU}BAkS~mUi&t3LZGP5|(
zO?4%HXDQ!=Mf&GE<ID7{v%YraluCL+a_y$Pwj0HS^{)f8ubwm^JR-P;0F3lJra-7h
zqw>ZRmGdrVVUQ?v!Jb<8W^J1AG3ND!FDRmRfvC|V@E*U;Cg-c~iC#SY^>=?|z{EY|
zE@MvH4m5(5XR77KtNr~r4HJB6)(2IF!p=sulI|a``e&M@eJU`9!HJATu;#s*<X7R7
zyG6D_c_K)q^$Ug!-3WN*?fs>C!~!zZ$76bW+KlVHZ+QHD^9>foM#yrMYj7Wz!WG>D
z&CFq}!R~9t_94t{we7(T*3%FEDBBOlW)9trG)KCo*zJ7T<qAoym9Zkoqmes%elkYH
zhfz|PN$YaA-fC80#%#{Xs<tR6g*(2ll`Zn;UU!Os8MF9=efBgQKPsD&sIyC46b{QE
z0KDd|{S)ZkLSUweu7JQK%Q=iTKMi9-)yRW?EmgrA<xcl^<mT8xwNT<Jjr7Gm-s|rJ
z3qo=3$WJ}cYe%v&@$hR~k;hnj&??OjD(4vOv_HyXB8-=)K%I!4c-vI7;T?!9bFbpj
z7okKcwID)nBnag-)m+Wto{Wtb%v~+kRo0H$pW^ztg18Sm{^)a;8QgEtf*Y2uyAPgj
zGPjz;_mmLv$X}L7#A62F_^clH2-GFfUV7yBPW{|iN3WqNJG=7&+PsO!$K?%>_Ga8G
zfH$i#yenhDTFZ<ob<S~8dOcA2w)RkVkyS=D`$6!#j<o|0uY^4)>qA>j8*)*de5NZ}
zIB*a!ERcbo>20bi%m<RUfriTpbq!^NSn(78?Kd>MDW60H8tIm<ZYSu)#*&-+kN3<H
zZp<2O+$`Ke3FquE8v8@+MPO4<LCvIr|HM~WM65$vOEC=sHRLVp3R7&396Vy#q#Trp
zwNgzf<j=yKAfb)=^9PoaGtqu$SPx@@3h3h*VjlIkZBOpSSg5Sx&a*K~|9`mp-8@aK
zhceK+&W%xeY3mYJ<jTp}=w0ub46jqM?Es>6KOrh%oks+0u+`8t8INF;s{5seQgOXT
zsghNj7IoT@JGGrmEuU3K)DxHYctyVp`kOWr?D*>s-Pq5vUL8JRH8~i5{iR202SnUb
zfZ9rfq7CDt64Lp)DT?A~3x~gCUmp(>e(CF`YcfMLiWmlcn2{~>>YUhGeGS^`Py<X$
z;*NN~K9K$5$DQF_4f@s)K5==AaXmzZ7(O%I8qZUK9ND)+a$QcS)+T6~YKJ$4Dg6rG
z+if@Bpi6<_uCCJP{}E%)JiZ<+RVPi{LZ843ooSdb9&Z~4ZNAzYujIcYz0lT_h<91%
zAU$;|NgGLyk_-H^E7t##%9BVg@<>Wjsvb5l8l6kir};y8tafW<vD{>@-6p4otMSsI
z(Z=nNe4uEl7FwF5n<FAE5Kp19&YR3et5GwS7ndF}V00LSec{Zjy7Us{e)!)7Y3p-c
zhl4hvjqa*eQ!zx(h2zLgd9Y_*D_uN0%@)X`#gLXlJO1>^F`!Z(SaB~qYWN$K$6W^j
zYaQjBa6vd_0p=>EX4>_)1kDw)eES^+#c8MjWvi;k1lfN4UO$^KvJGmX=4KqW+VHJk
zd!=Y6Y@9xWRPtcVDJTK;hN}61T6&&nlsA_XpUrtCXyeHrAutIY=y(Xf=C6LK2us=v
zH__eCU=u>iTUE+2!v|Eq3l}`{s9Qq#To>t&Ph-(8`=#r|6Nzsf_E|Ijk6Q`{$z4be
zq6IO1uK4U7$spR}l2o0K+UUCz(HQcrFo;Yk!VUXmy{k`{u#8WtSu~{jgX=4kr*8x(
z_MF8LO<PQ`G>r&)Fem&;)8X6M_ASkJsWT?I2ItKa%v-wWWY{_~nDM>gZc*r}cT_un
zQTU&2KpAU6R?sfejG_u-^t+M@9H3X$&29H1#C4vFCNeNi6*<MeU@kBIM{^z@8ylR?
z*<fzcJ~K_Qm!{!I0w{r{Lr!c%Y6sjWa(5TA8U$?UlL~DX*Lz+RkL;~WDdZkY`v6x(
zn@{OpEk1t7I$sBTtse{>D=IGTt%y(u>ar(H#{ovUt3QHY+220yyF!ZQ>b*XE1%W1*
zMHD6opU_|iv7!iz^hvg?eREKYQHrjSc#)2u#{V|wXkoOgaT#ShE`}mq15SU91p^`i
zn-qGw3J&L#;WnH`=GEGbVaD4ys?qmKA8cm2RuD`E^U+?KD-mg@s7GVyOLk-PjQGJQ
zdv}^Q<VW?{NWUf9n{}fD>CjfgT+7G2HYP`NlIm(&PO-1R*Ky$4mz^mWZ_(R%ZR&s&
zxOAgsS_5E6fouqaTp*no@j8%dtgqxfuQ5?hO+I-Y5V-0gh|iMM$zK$y@fvR9K!KSb
zxfj;}+{7fBg=tnE_f>(*jd}w|^$m<0`Jf`|Um9^bT7wA<wrb%t_C{U~07-J4vYzZ_
zDG?!8!6YZR;@TX{8r2(}w8N9k$y`Gs^Ud0A%c00;;WabRC9e_6_1dxNnayQ~f%-pb
zHXPv;nSCn!f7k?bAk5?GPr%6kb0*^=su#cU{dATbc7;=n9mq|4ASYC?n9FP?r1?7E
zjQ7!J{M_+T(9wxEBLZlS<Ni?t@+q<F2x%e$`EkeOlN!Vj;ER20J@?^0c;~8CN?K~c
zBfEw4;jg{cx&OF2&8xi4jt3TL0S1>%*_MNAEeYw8aN;XjH+XXtrLUT#%g)F^M7FjC
z`lj|ixI!a|hN!E)vpCTX-D9{Q_2$7FDOrx`*ZrmM0rI|oE4C?P(Vz=Bzpq0o?9F8w
zdV191spaC60z=xG4v?)M5SLaRg>h64%FbulpXUm33UZZ8+QecI@0uoubg7k<3eeD&
zf0}l5&Lnl3Wo-WgN&-O#on2@TKPk;m%IC{qyazqJt=Z8R6pENaue4TlhnFs9YJ7^o
zXcjyieII`1K^5*-cIQ?8e4hF1%Ka-_UH~zl0h#{als#9C^zwTLYPSMsfeQOG6`P+`
zc6ZV}PdvR=<ZxKOT<c^{Mv(DRW@I1RUH=^xWK9s$gONy;6hn<_OPI90r0BRxqP5-d
z0FJF?V#1SV+Ny*W!&6bjD3A!C+fz!c4jQPuy`Zk{1`d4=RbB?6MmEh<yv-*GQ08tl
zwja>WB=Ct|q{RAPox}zifm13qvo{9Jc4GSv2Pon6n%OB~L@+#4Icf1)$$<P*kn(xk
z(gTEXp8~zmm`2JvTxpIP!Et=`L9_`EGD!1rn?gX&#8!yE_n^}gbFi~6q{xdZ_sMzO
zoSMN10Lpg^Wz@E8?<iS=@7I6~c_E(~J%z0xwf{XctmN&;uvhdM7LKt;Y#-w&<Gtd3
zJbrEa53BYHL6E8q;6<Gi3B^H6ZcRGExdD;+Qo{{gB^E4?lj(?t#v!=xo%O+jne;?x
z3c<h_*!jvdDNNP&Ld`)pvSKrE#DZ1=bCobg)<7bc8Oz}PDijN64ln`!XF{Cd4P*e-
z#LfDKSuh4`%Lt_R-s#3T7a8fT;CV@<ORQz^sZo;cMP+l1W|B=HL$K$@YCl`Ts0_|M
zcQUEa7U!@^z7G|jW|ZNUQ~S5AZkjL6CkXR%^1o%_m$P}gnS&2j)2-AHp(8IU#b^d6
zE&xeDw!a;T%lCrjG7*_VK0TS<ZdB$bEWXAVb<<Js)M(Ybwiz|yor(KEAqAbn9YkIJ
z`9lf4EEO3GM{6x#9$#%92?@JQ1N_mzYkiMaa-=G#o}6V4RHvb+U^`S3e4J4IuVAab
zC<x3HdKzwz<WRL5ZPRGdcn}WjGEta<JOr##*YQVOWsY%V&q3@u!EJNH5_OJ<>NwE`
zWDZN{ocog{rabvO>B+}xdH}WBifhz-fapT;ne`AHt1a}rS*s4qfIk0F$9s0lL&ual
zR|vIIx?p<phAvyEMuccac~<x`z205bJaP6Fm8FaidWQ2}G)*JyJGy*s)gts%48o`@
z0$Xgiz<_DOl-&BOwk+K(+r77TH-oNNP%-o%l?WEX^I-+r7fA(E4D**W=d<ONZ~r^`
z7-8>-=E6C4M-DD~EwoA=bKDjGZQlB$=(Gy>N08SkTVUUbVl0=(W}B6xtDNUBO1M4z
zfdr`VqLe&+7fWE+?UvFCkL3uA&w-4!j=ac}<h-nPz)QX!C!ziH>D~qkgL7yRMsV51
zIsMC(R$U&90F@*UL^E=0FTcPF^kp|Q*yt|tG3CYpd;auGQ+&Uqp~1U}Uqu42m>~1W
z$V^Y00zJY?e+?pdC$H-1FDXoTD*!S#t?PU7^{QI_qe#V?vt8Ns`2e?cW!=8!k2O}f
zZ-;-&-<P!&7?Pgf4Ok4DMDh7szavNIua2JzXVR(wP`vlt_RJGUo@n@Xd~4#ZZ`c(X
zBdF6~gox8>%PT^wG0a-)98-KX^V6$8w<5;2Pg5PlUkNEp4W~(v=0er5u1E%WTm#+G
zkjhPV)df5X4q8334;AU{#o*3OfC&uMJB}yA5v!pbOBAhAu!Q<LpK=E0Q|i$8UMm*!
zL!O9>ZG~zoH>k7$Fv3qF5F}BrC7`ooO`t&|k%e_RxU-gZ@GZT*JdWufAF-V{M}x;G
z21J*>bfFh-8scg9TknUlmFyG`^n+A~JT;?-^Ae~+4(T%dtA;O7iyDg!7#D=vJ+wYU
z@6wR%E<vA^90F_J#=QmNnkRMilL8t*@<pR=)ht^)OjQEyd%I5$rWk88!+F6bL;&?p
zfFDWXF?83<(K<A(|F`<%nAm*L>dc}N-cW+)1JQHB*mNHJWGm93GyFr%xXKrgc*>4S
z@U2)$pSUZ974+wJQ7b5zM{#<_r1g^o@R{x(PD()su@v@oH^T(mFkP*9#p5pQih_cO
zg#3i;wh)i&y*)W2r^7l`R3@MWu%6@cP<VldRj1l%NzVraT&9u^U6YQ<IM!_>I~cD_
zT6~Tq9igl@x_$gcJM<Vzi1kbQQ8JJhBmQice784_oAPR1FU<Q9_H-C|i?b|YcXic~
zMJO`^0)G`&`h9V<X2psZe)NGWM$CY~!$@m!cVprkD3!K_)Lj;dSXQLuBJwB$q5o0?
z2<UIOB=e2hq^vl4n+a7bG}b(^<d+jy4PKCwiilKQ#!phQB5P73=aRWA>R-v|*)vO-
zyt=ubTJE|pUWsZ#^XS*Sp?ky|VDgN%MnmGVia!lM`n~aVn7rDc2QOXT%VNEwI$wmh
zy&653YH;kOIttN-u#4>ofW4C>*DdZZ+`>+}L(EE5F8)lNBecAP(4?gYC}(L=*RSPY
z=9Ny59i9;Qs3#*!*`!d4cq44p1ENo+_Gh^o$2*`qs1CxEgv#*eLx^6|EKQ}4Ep$1s
zV{g(Cnz#{(dJ%(RbBc&fPs|+Vh({xO0&ujPo!=syKAXExP{2|obaJ()417*N)K<(=
zX`<_ZnMAW4R`H)-Y<{~kEgDW*8)FZSIGnTJu&asske7eG^XCv*<#(`L!!Bfj#ngMc
z1D@sGYp|xLCTD`od#vJ!rEt1i;P570%nYxWL3Z*jnyelkhcF!5=<ev(XSG8)mMsk@
ze&u+T9ehlJo1-2#yGt8`<_tv&4MQPj)@qCEApzM&&4`cDZSak2;FFUk+PH$5Y<Z%z
z`1GC+S)|`k(J7~2xjbJBMna~mFS&Ek8_2_gEcA&tjUste-TW)K+j4N8)fD{p>M6HB
z-LO%tLUnO^q^p*3-rZOl!DiB37H-m?Wop>XnDZ_dk7yA0YoMDPPg2!DAs&iClN@CU
ziDSg2hB}DE4uGeXt6g~U4uK(u7jXq}8w_ze723DgMT|?uI6~8vXo?;GUhu~X)wgj3
zf)Iu&?`@2~u7bPEo@fJ53rrbjN)Ag50m4%vV25zbm-0l5TsK>I|E4wql{<THwzRpW
z**CMeN>(jQz23B94%|JrSr9&xlxP_ZYFI3*&8L@S9&vFw?c>8W8Nhtk3W`FL+~)`y
zYFst3ur#}(Vr{rId7<?GCJO$gEBQr$Eu7n2G~oCj*n-7yMZyX`;<y}Z%|_IE+zXd#
zxsw0+jMqftYp?5;NJ!ie3nXVUzlDtB)k!o%8B7H~OHm#p^PKY1P%e|{c&=Yp<U}6%
z)R(Hx-&KoaB-1x5|2sv*$CL~~UGnak`u7Qf+VW0`=Q5+?PK7Yxr<6x7O8&c@(fy1i
z_EVGs66Ygqn@!Tvbgt{{#4m!8wd?2UkeAs^_l}MBh}dL-72eW9kob~hqIW!iCPm4;
zd8y|8h}vKucBzVh*WB>Q#>AQhYtRnZi_S@szE129FL1p1trY5qg1RAMpl>7|OB|bl
zxJ)_Re5bR7g@6rd)6Rc2^novqQ~*85sL6B{%Q^s+#_x-=O;*I%zqeIzxEyf0aw(jy
zi!-6p#-edSYa~Wv^9uHiFFdXfFL<-foA}Dex@P`o+FV+Eba1o=WWt?*Qyc>%yGUwg
zjM(77M<C>?=yor$3ME0mnFiNb2{K&U9z7dPpMxqZ0tmG4WE8H^Y#l!;Y#A{z^hMXA
z<pByCAVQww6(?tu+K>{It(ESGN7df8W0T$~zLp(Pm1d&-`){_x7s8YiirK1^Me#-P
z=g=6@buRR)OJ_mlh+4P(1$0>23>^6;^sR#D(a+um&k~{QN~&4?0;fCPBXTOz7r6a*
zdUe>kt@vVC#)`8lnF`mjctZ?K?-LseTw3G>Xw)&c!|PbMx-}Mhvw{-9O=`9fmEnn9
zFr;IQY?CA;Le_q=NiHB^c@>hnD#hD_w^eU<E3KQ?_+(8!9~5=ib8kfceZ4?}bT#)`
zf+G@A=nxnB)Rc{i-1@EDssJPUhQaE~sqDRC;hG9HnkzZPhH0-O<}C#v+GFDWErcX%
z;Cd=X{I#biGMcT;s*E0Ml%^`f+7Iurh}%quu{5({IV!cZv!geO&=7F-i>fnD2M5MO
z8@At&Wci~<(zxSyQ-WmWg#;|9D8q5<x1p0T_;1{_HKbkBTM>6R5_24si!2FzbBYb#
z-ygTal}1e7DfUU{tSSNSn3ypi>-zD+ckLo+LWY*zDrX*rg!g40I8^FA2Zvb-kv4VH
zZw$*`YB-xOYlFNVJHS1sM%>@)X98?MI`&z@vw0d=v92r6k?Nw9U5rnPPk4tBV!^~@
zLJe}l?vRFQNzrubt^F{7x}2rAy^R({4=0)@UO7R?voE`wC%41wXZBixTv34&_R~0Q
zoNM-UR~=UbQJmfXzKa-E^>GOr!1Mx36d^oak%Bd0>KeuIb*#ccA@PDgivnPqICEcb
zuoLvn(HUIq-U{uCm1oT!<a0y7f(;7@2pjVG(TiBX-~~XwR5{z?B!9^I+?ivw-Fhr2
z8Au3TCPU+-Im25v&TTotKvkefR-~9m+yMv-Wuk69+&D7RMsW(ZMm);EUa)b&altXJ
zi+a=o%^7oL0eWB2(2n+ORl^(|8heLtO9Fw7<QCn+dMxSo8kk4&db>1#>L#TP;=WSI
z^?Z(v<))TaAwOAV>}hVI)3n+B-1tq)C+`wGMQzI{{Ttk$8dm{Y1i5uX<$ssZAA#8c
zuy@FL2lI2RYwoEbCKx*-qK|i>pACRVAUtor7sxU(M{^2$O`%uJk)c`CZvJZ%<4B5N
zS;9rNV!8~U$8EFg#D!RcaaTLJ>LJv5`5?Nh`oWK!<vB#B=PX?prIN>O`>Xw~xJ5Yg
z)Y-m@R?aYplwsE%mLB0zO}K$53m-(>KKwQrM#LU;@<>>y-*oJzu7;jC1&^Lg_sq^Y
zM-t)2FQ8~)p0tZSGBEBSNLm?}$NDlzUwC(_FvPwsyQaw2_M+cx@-;T=20FPmEpqZe
zLrFgVF5dPtjj;ASX{h26!^Sf5xZ_0UUO5oFEt)8%QB#Sqgv6|ygyk$e^DXnEeMZlb
z<-Jb*BNvId8^<c-I{Bk1@}sIsWm5m3$)f(uunay|ddY~2qxd`e`m-;MiG35B5el*!
z12KySfqU(YCEC=yT)VrVEx~Mg5OfNRMk%j!c!)=#!Sza1s5Q9QnpPfJ+!DDB@qk_A
zqJTJ-LIl}aM)a<pk(FhO(K*|SVyvC*^{;$j;m^^&5wk(wy$q#Mzo$FKQaqqQ;oFee
zN=M&iY4NM+PgOpv8$?8KAnK}*q!{yPuXeAOx)f{%+FornFZ1%C$)OUPN`^+;xn6&O
z!G&+zb-G|guFCRAzfDnNgA=v)#*2&5NED9)spRCNc?9-1_+yXf3wAz5aT3;hb11eH
zOk1U9{#5l?5#&v^g<@7<?G&+JPb=?_Tk}}s(3!#UU|*d5!6xc=Y(eFUl`o3MQVM4B
zhrJ~u(7Um*A<RYzy*X`7=!wyCR&xdw;^za2E74oXv}zav%UdYFEOPriYIX~RsgO2;
zC56I7>;2<(lrWD_p`apxsr`nM?w1mQ9pluZDb;oF=r&E#SbQPgqV*!v#O{~}u}u=y
zOY&~9H~k3Up~d*J3Clf$x3!F2ZJGPsFrS)7HQ4ZxrpHaEPr0a)Mr*=X!5|?~5#M-<
z{75@E9#TMmR1dxPDbBquh`NPsr2L;$KuUbaGG%AFLf~VL5mbD{qXEj8Uf^UQ=GV0g
z*nY+~dq%Vd!U7Gff5=_I(`d?~%B60vjDhLAC`&~9Rf`rJ4=K#}4w(P^ApU3O!lzs8
z_4~h(R-uMCqr^-erS8;8U2W@j1c2y2Fj3ZSK9c-97`k41Xu<dVgZvE1LWTY!SYFAR
zi2?R;BVUqYoemmGRNc)IEVIL=z%8mXyC^erb*XWsHT)!MJ38WNMDeY98PMiQ+X<k(
zsM8Cn(<RG5BB!y6vxc%b#-?^^X*18xDjbl|bg1%MGiE}H=*1<aCt95!Sju5^i#0Ep
zz}hU1NOlo1Hl{WPI-v(Z2l#KA!G;1?P+LS^J5sHp&5fVPsMVo;)O_(5YFkOlW?Fsi
zH2Y~wE@%r3(2%l{P<^YtmZnH+NE~;d1{%m>Y_+vAq4$*=wp2Vhxhs1KuOsH3KwCDA
z65|350z*h#sZbYH-6RKs(>RJpY)<Qgxr~r4haqXJ)3b<jti`~Ex$1=`F<Z&AnZ{;V
zTUD9%RLm@3tfx#pGm#;un>5ge{dTJ@xf8h;$6gU~#~N&gik>>U+p%yNM2uy1WJWL`
z_zzlo@)G=1bA){|FdWc@G5v<wAK?{^2{!YQ^Wy&2+B)TJ;@`Aqc#Y;qhu==o!UCb6
z`U~gW$!bt8`uss;_s%6f5ap8(X`c#C;0!Q_>EnC5={}sZvXan56_qZc;hl^f?oj?>
z)D9|qY3g*OPr;zPo!EG8IE3qdydTFMl7JJonn5<{o%|RS(6J~L<ub0j&IS=NirMCR
z(OlV`T;04T!&}#2kE6WGw{6)~9z37USlJ|evJzBiA90eHY-D${W!USj+ePGx+MG?r
zHyn`1+Xk)mviOgm{CdDvzB4QkS_jsS8EX<t{8<d@;z<@{s}WF&s~q;IHu8dOKOjo%
z2u0UXrYp3jtk}c8PcAM5?cD2h8WQ;6Zs#S>m(9P@X*&}lZp&bSz?LJH0r}<i8Y7V`
zhZw!cJ$6&b_ZyUX>clN}OIQUS%+_BAfr>m#;yCGn)L&)mAS|GWa}jVB&T=b}Tqfn0
zCx|qMmoYDjo7Mt|C!Pmva!m~BL3R@lJDs#_-t?@E>21t8zW97-oUVvL+nG4n*UqmY
zjS0bCYG+7d`d8OJ1b2hto0jO_xbWX<e<&R}xlF<N#DvR;FX2~Ra^SLNP~%8Gz?($h
zfm`n#{z0oV_%Ljxg1-rBP4GzdP`C91h;w0%1?nQY2<)V3W4TpVgQA#KNj^5X8_r5m
z1bh|~Bd~-@Jc>96rl<S+eBShkXTSaB3%U=3oZ+==;f-N$s@90n?_9JRXSL#%fnxnt
zEUjGHfyNceuYEbyN<#ZngsY()$KFw1MH?$@x;G=h{zJ^Rspqz!VpbmDbpFl(N2J_Z
zM4S}ln{pL&x#_3%%TtRqj(l&Gq<IBjO^cc>iEvadsJ?lGiz|;>`bzXBMpesFUW{<f
z5V;L5Ao2P5+(SgtxahQ+*kQPw+Z}?p37{?`Jkj~IVX_f{5#4YeiERophy;Uu`c#3b
zq22^?r0bQvZyXz1k>Q*AX%5aOh2nAH0z`A|HI75`*H6=g(BoF6fU#o5h~Z|{opnx=
zoxuv2L(g)_l)Q|(Ah`+U{$p#c08Cf+nv54sO@;Enog@5RY*kAT-P}U;%QQnrdanwu
z#=l8f7j|&ir!zzH<@x#eoc04T{J2=S*`AabtsKh7_cZ%#j<{%G&1t}4y}NY!xH*VP
z)ml@CKI8NO%y6Q}x93gOnGMI#MMx<DQ<=?(x%QPjx?<-~g3fo)X70c=uzNKj2Z-uQ
zO1+9OxQu}B^KmlC0bZftW2hqIKv|77n!hAJ@yU;b@X7w#2h`=77o9FZV<~)05lkv4
z0CDZBYR^srys^wshI7>YV(IC6P+d`YTAdNFy3TvJfNM$b>4AHsIa>&T`PgS{%N*@<
zgF=`|PrmJ2_I16V+gn8PuXY|n><%Mo0dYZWTi8B660`R=_AV!MWbiOVn9u_dmJD$2
ztmCWS6I2AiO$N<lDp?MC;txabjq+yMmE+q+6PKI(TZPy=J40a|n(m7pN=VCSzy(R@
z?b6HgNOa{~HeJq-C7+96=K&BRJKx$a?WetqiQwB&Qg<Bo{{Av-BRvhJSaM6ekO^ix
zjuD|oeM@=SZ>%mf&h}TfNJhI3-$)@I!=FpJ*0w78v5a`4tGYSskcw8xdK}NPaO3Tu
z!IxQsN|^iez$vOSw(1;{6{Bkg3sQr9&NwFm$SF2TxIS)}HJ&^EmZZ&H{h$Nn9?)2`
zb50gO39wO$Mdd-AGk*guxf3lZK;CMC^}JqV{&j+SBf$iT!YgQRxzmXy>n=zwjcLU)
zzgBd4Abc9@-GyACIaZfo=BFnDLMjZgp!N?98H#}td&SZtOhdNK&w7&l!{)Yu=3Biz
zmaZg$f^hfXfOZv&>gK2W1z<TG4z0cUK=B6B=_U9ZmXYPY31B4ll5ENswUH*a#!!k(
zls<;!aD)1e@i?JP%xyuY=PJ~0LW*X2b!!VGp2R0a+v(IM%<#u<H1f(THw_U6gjD<g
za*BHcykqU<_H_u6&A(qCE4!2VTH#O+rKf&)nEKjIc<){qipviJWP7(a1y;#<;fqg+
zAUpTba}Fs!S4;9d7yu>fQ0N2S%zdln?WjQjniCElS8dp6uC^qF(b*{}9<4dVmzY?|
zt$pOK4f@BUNZI@#{fErGCGKQwmR-~Tjijt03=alH_4Pg1y6dKP?1fEwoLy${%yTZ(
zln9agdCy^fD)wogCg}$`qC>3}PTsvE5wUj&iz8>JQEa=LM>S=Q4w&Ikeb-;=ikdvX
zISV$wRQn8blJ2gR!R-T$+n$lT00CguCh>j;m$lM4<kf#R(<UnmYXsmPc)DjLUdmRE
zmFS_!SGZeV_WSx3mH6wDiGc8`(I1S(#duP;O}vR>eNFh~0!>N7sMH*Onz37%!=snu
zfrANa(MFN$tbW^uOd}O{hZs8chB*$XqOr<emT$XY+4~i7nPsX7+FsDFeS&S#BGhE}
zXu^l;ppfg-btuOV8^<emUCJkvg>ZDSHY;RA)f?5gtY}I!5Buf)8j0Suk>B|@XR}Li
z^~=BX9Sm3@?)l|S`6>p_tww$i6y>k;^7kl9{Fm)HY&Dni^-{;r)wR*cI)S(XQ}rl~
zkIJ_&lWB<5I8js36B~$YFOt@-_kx;(A%yY?+yWQNEFENLV-nZ>XSX!*p#)@oK&Oq+
zryM^zlO?>iv@cT6YUzC892p3)jwE(yL?y4Iu`13&bxgNUT`*am36nqD-M>c0q>x_=
zqC2SdZaIB3ws~dzmr<f!R>VCyd{}Vv@ot-iW$|H9yhb{uYC-@d(SZESy(}$Z|4?KY
zbm3|}MR@R<a&an>R7p{mi$u3x0wWmdaWCJgBcX!i#N>KNiQPvlr}uNoveVT+f@lGg
z<McfCryRK1NZw0;a=MJ&`%D@1BQ&~eiD|$j#B6BhPa;_kw*b$66p1kLal9@reX02Q
zkmmyjbWg5-YeR)|&Beg}&_uC3DWyb!&J@KYpNvV*s+g#|D0>U)iJdq{ebop`5Y!9_
zgX|2C2J0dr)XFTf%&X2Q$lgw;@r@z1P8Bn}7K4ZDp!6SW-({NU;PHir=CK8JH~PPn
z!+T=_n$TW)l0^EM*z!u_jU~rIpTLr)DrP?sqvcsVUDsLK)YgF}bpjuZ`uoaI_{W$a
zIBb9&=Z!}4*i-4%D$l*BpOpqg!Hx#VAuL+ut>bh(4S26_(tng<aMzMvD5Lr<$MLeq
zZiny&B#X3A?Sm4>32Zc%hiYI^&9vD|3{q$k+4?#>+Kqr@S{gEV!Witk(p9T*h(m)P
z9s3VunzD>1EmR|w4m0zU4;^XHSjCrB(Mi6&6QtE2nAmC^3oRfo+DIz`EDI91<~cEM
zNYeO|ICXqk8ofXOxoxD&gaYmDfkx6p?3td{zqJv1-y;OA0HDDt4+%H+#(GP84kH@O
zf4bSY1F6hJCKE(<+t<Pmd=pEq-F{HbTax0y2pEbfAKher5T3VcfZOxV-k5vr&1vR1
zdI(a7dO=S2^}Y1wAX*Gep1RB*;)sAORXSyg2uO2H7&BCmy_J|u9s$V20(P&cNiu^U
zq%M2x8dmot2!+&3@3GN2<+EbGajOD63%T8Q8I`Z8icQ{^XxaUIp;#t9QAkzeFK1hm
zDYI9Xs90Mn#VQkjnWBQ2UFU~_vDN`nb5P-6@q$30RntBj#y=}vLW{mr8A&uE&FG<-
zcfu>#C%9pb%nA`j`#@5ke?iQHb&S_njhatG1m3ZHp=S^??{LeFCyQuLK`oe(D*2GQ
zZfY$rvuE)C1)s{iyF@eW#_-aHgGuT2d=%f4M5p@sYI_Rs?kM#M7KZ=&_NVTC|9>8q
z(E>EaG=Nv*ds2*l0;?|@cYN(ic(K_PD=J~hzQn1YJ};^l3P4aDst{BHJSgKvOZPni
zlE5P%rkU`kU*P8pEsE#`X@~?MCFOD7xf<3S(Zy`N$6j&V+5hYubaZD9n&tqN`~xh5
z9c;>5MQY6$0{L^6x+Nf=akgQ%jv1C{6O_M+hml-sU^zM2)LzkPec~dQ|A)rdY%oHa
zzNNzRGU+H5STOS;3*D89XAn#GIm}(;%oiROK9R%#-h>x7!O9Oo_UF}@6Rtm3t&4co
zke)iR`uFGFBn*ge>lj@CH47WneSQAi;G61#%7fyEp~0iltyYc?)fwkAJf{R7Ux+NF
zQ?GZs07+I_rWT+B7Z0c16q&pJOp#|V6+A~?eK6kuMM>p5E01G}4<FN*vypaO2QL>v
zPvkLiy?{?6?`8txy}=c{7ch(a9<lL%>T7<P<7N5@^7mMBz)A_?Fag+;jlfc-SKUjZ
z!`{+eXp&W-9t5vOCCe&&3h>n)8-jR8ekE>t=8wsjtxfFnO(|<d2mwYUF{I#48Qmot
z2{E5$bJ$%ft*s}NZ0ROd^9_!9o2Ot_i&##i&PJ>9sVZH)h!I}N#t^x-q|DyOJ4%WN
z#y=Nhek)0?#X!>gw)6a#Lh#Oe{RqZhjl<T@eu*Xf8pFt&i9kEPY~r251ZaaPU|v}p
zF)S5{l%0kS8+1FvQM)4OAd>0dEYdsB8ZE#Hr>%tec_9F?Ls}+!2iU_`MvKWti=g$+
zsnN%u+Z;O_j72Ygl`BHB1Q46wth{A<Y9xx<-Bc^}oBpxQWfre`3_Pn>GyiSb9`{mL
zs(kq1g*{-|e@rFiPu0SgR$Ne8y2w?DPAW<&2h&W&a7Ac`B3s|5`Dneslzt-6oOCT9
zzN)J@d#NOidu^|{AX}w;rXpSs(i+<lVn+s?3?P#?Bg1^`pwCp|8piAgc-~<;(YYN1
zQ4&+PfQ})=jB+<Pq^YYQR+FL+Ph+kXLeDmjkAl~?Nn4^(;bs-#AO1?L)aT4}Zj?P-
zT=XY2L|F>FL}{sb#u5n;dPcUUek8&>gW0568xyZ4N`a#?H&PNiZzg7ik+V(Go?y&|
z+3DW3Bs$#6@9bp?MeJM=Ncmja=}-Jbp?d%Yf1Wn2dQ#F7ivrvKkty#vz50JJnjp|x
zr;ya(6Y9z$Za7-L<`E85j(u&JdmgOy>P_ycSuPWGO)z4LL0mv>DGf#GHbl?3Gql+)
z%Jy2WG#K$(UN<PE{(MMt1oHmIxg(H_{sUg`0UScnj`wO9el>8gCr4w-eS3iE%TTtT
zudmlSYH~xU&NfBXui>~MQ_bDaH{@ViNS~-F^=r{LiC7qsHqiSt{p!s5T=i0n_|cVD
zq06GB<}hbyC~mMVv3oe6Q4O}O2d|-k17d1rYpe5@!OhTHuax3XLBf|z;cC|@|KwY*
z$A-H~|5!E3E?B!~N#s_^voZ<kvGkrSMuvB85kgREmQ_3<wa$35xIL_>gj3_mXToBO
z5}JJWf;;$nn!&{guoV-$rurw?KjAZ$Es%zQialP*o*^-7pc0ohVUmx)0NgfYnt%~|
zN-Ph~Z9s%3ftRQDIcr3o^9R>N4R(GV$7Usg3K^>`aPWU`jK=)U`0FxJB`s+Ea5j6)
z6dSC2NQivy`Vh992PKd9j6%iyhGXUtTR#eXwpO9#mWvPmvrwq!nh=2hL6Vde2i5OC
zbI2p-Giu%sg#MaLmWg~6?t6Zi0qxp;PfXm*35dyNUsDFwCWW$bfRth)K^2Z$VFJEB
zuT%~#eQc49nW)s1wG<aHpZt1r8(@zmOj4$Y!+Bzy>~#NZWKO^nAwrN0ss^ZSr=q`2
zRh_v;wR=qo+fsS_JR!?znP7oBH3|P4?YF9E!Pesf*DP4>(edB^hej3fwQea&qb7vd
zW2^js8<FzNa<0-q!A@~QUe&#ay+EfB0L!^@LSFktL32`I*`Hkg*I=oR+JZpdqP2~n
zcwrwkcXFnF=Mu6pvLB{+ZT$P(kh-@z+v1pGXFEvuhsoaDXiBcGB=fxb9g={8H&n!Q
z-83Li0IIY4F(czJqlto7kLPEYeB30ia{5d-P!_bjx6vHYwF7>g%qEfBmL5uhGuSH+
z547<VZTb$VO~xSxpn=trIHosDg#?~{$!a}WFifM(Nxai_T%U@?yS08TIa<$-`EY-U
zx(=)+I6eGmIlS&GNc&RjNx@%>n?V<k^y0!a+~@r4a~eYAh@h^F=~Q98TyZeIaNal!
zv-njpFekm|1!|$_eRMG*l<l_28z+C+m-Nfff`iBC70WmJifan#VWk$1#JWiz)o}2r
z88ZUzEdW(Y>wd>nv_ECZ%`2+<FW_Z=tVqfZZnE(GQdYiH@&cFN@$#}#d)5dqgF{A4
z1KKQy^-;MSn$;?q%j=fmY~IIkk_<`_<Mh{j){LQcT$GblG)H=swe(Yk72`=@`8shE
zL<0J6>AKaDe;oUqN)lG!Af(_9cG0G*PWQS*5>+{LAkAZ-RN}75Rr}9bjeJ*cOkJw)
z@#)W%cfulvmQ9Pm+Ec((gk(7&aJYP9_u!?G{wFa2l}D~WKAY8#q!+!otEffw*H2`#
z*jgm=`lA4NdFt&_Y>Dwhvn-_Bte7hOFINV5ph@IhfJ(;J1EwRZLMn3NAPsSTzo<*8
zpKPYK!n24%Q>;{A=XyCneUX?5Dlm<>JR#GfYm)tCA37kgxmp7`P~rba{*IUq4#h@b
zp8ZFzb|Rg6_NeEc)Jh#|i-V~adzoL|j}of=*w~H<PJYFzq(?aZ87;6i_)oMKRyFhE
z75$v9ez3z(zi}JaOF<z8D^`EUM0U?N7L#l>=ps46A=CZeVye&@?}h%7Nv?YTde9%W
zt8upm@g)RYmIYd-S}zED8XqRQcIm)R>66HGA)pV@>6X0l$hfgZHaTQ0D`MuzTC{K6
zQ3W3?02b#k<7k1_Wj_MFhQnw>V>P#UExO%(i_4Z(Tmwq&f<;db4GL;&;kO}_g^c(N
zJ1_0O;wU!2h0oD)7mZlXJ(VrDtfVT}JB}J_#UhxkcOc_H6W!kr4NAv%>47OlcL_=b
zSZ)VBWXKbV)Z|KNlJ22xZ)?A|q1*hYI7YuIkZPBsv69G3m!u9o4PN5kj0lo8qc;hB
zIPdV-zEYW}l-5vI<$XYgYZe9z@WN4EB`@^jBw`r(A9svJTI|+v$0^~e(FonoHZ~7Z
zJwZUQPJQ;!&v`$lsb5j_rrXQ`8rzZehC^anK;|i}+b~S!FtyoONq#Ff#R7~7B4ebe
zeW@>=Fl`%zLknXek{O3-Yrn*SRVw`Pbiw`AI{F(VyaTR*f|iElE|S)I$Eng#AKP14
zbvS37UWo1^!agwgzc+0_3nkh%EI?p~URc=u7e@ArG;Wy<c(<b=G0ANoZNp8dRA>Lo
zB;QB&$#aPUU9wixgiufEaAMo-;Uz5NM1ho<>M`&o83jSTCfbLi9Jk0Y2p&?YI|b=D
z#RfHe5$m;fI1x`Cum+D#B{X;5=0Gg12%9=wNY_pY6$VEJ`nBudDKcvk^iJZ@IZRV-
zq33==UN;pG?9d?<b>N}$9KkU<94(Q9Vm-7+-yT#S-RlSC?Sm)V4;JmhX?EE-+4&zn
zml?@x{>xL{U1->dqh+C#hLyQ+3Wr+>|21kHil^MdiO!17zk;{<AZOQEYzowcnoJe7
zXw@SgIMq#}>giPtC7U|lQ|L}#Y9&)KWr2{OPCH;+;IQD{>o}2BoiU8Qyu-#|J0cgO
zIf^9{7Hd^dkY>@y^sGQ_z3w&5)C}VVZuWL8$@9`Ra{Ks9K{?&UV#{xy8YP2ODxjw3
zuxXF6CiWHH8Og$Hi(FMJ^|`Xi=DaRt@2(mgvFNziE)VcY&Kcmxl|KT4F=G;0GJacA
z-b6ilYn1l2x3Q_uOyHi9S$xC!V+)&jIBE@2_woD!Gkd;`i7t-l6W0KR#RfdAs_b~Q
zmV>TFE#yux*YIEdux>SXS26tg+PL+kfxXJuH^ifoVN}5%zmkKmW81O0YeQMyeDYS3
zmrtfR-5xt)tZSM{&=RgCDs4Vn{!Mm7Wj~VCmy4-11P>)HZce-1+h)~~+dB>{Zy^^=
zf`Ip%dRTJJrvZ%cS0C?}c+%dmsA4E1|1J1q`AN!aX|KCMs}HC-WUY!<cR_rhf5YGZ
z_z<`$V6Kr>ro@Kqz`skGiS$-xCc2cvT4i(lyUB;U&;a!6SQ=-f(b^hwlr|KNZ5Brn
zHMms#L%Eh)8L<V#|6;KIQQd1$T0mYbH)IdYKKTSn_&I$gLVdy){;&fU>ny>VO~6rL
zj*YR0*?;g`W+oBeIBvx3+45jb__FZ4+4SZjEM;5}nqpV}WLUkfAME23?d$zwDRh$e
z>m<q1Z=<MwWIk{{j}F*Lz@OwI5B4{(>8F|OR3kvXkYNB78tQR1JJY6ymO`eS{zZhc
zZ>}WMJ6FgyumZ=~Y>M%HIE=!2uBH+r1DQtEn1G0FdV#SMmkhg|Y%e?6q6<E|V?>SE
z%H^LX8L3#3!^s5{TLv5LTIc7sMuPFsFLxOXwWT4rKSZ}0CX$uODP<%+UH2@DgaWka
zO1^motwOulJ)S1ac$jwKHP;_!kw&5v(7l`=hc^=TB==yg)QGW`x+oAYHmc1{%&(F@
z1fjd-M4MQ836PL4fu1v!2)mw2vT3$T!I32HHJRM`ca(2X1+sGa<Su^FZq2-bh2~}^
z9NHUxJnu?{<QX)Ag`ddxZAgUysit#BekQb~mDxMO3%SWrms%y&M+F6Ctj#&Yzk|*X
zTABX5nU8#uLKGrb6Rt(~BnHGst!u$svF`!GD1zYzzy|x5awHK<(UAy_jmg+TD2U1x
zhh2HGiuk6ao*M-M-o8LY$#j<U%8=y&bE~D_ymIZzQ}K|`^I+Ng;u0>Exe~xs9n;7@
z+Fg6|r<T_jxH6cd69(e&`t(b!)Vt|~vWvI!R@7ICT5O$xJJkXeziwtOP=O~M4g=|a
zYLsUbv^@p1gE98fGAgAWJQ#hltf8u=ys!s8n^pWAO-z;xhdAS9&|3GW391e?mC@M>
z3j)A`sKMrwn2N%qt(KbWL%=;1AV{^!A3VV75dsIvQ~Xz9kQ1O!j7U^)_}=sf^FSk&
zpJ%IqF=5Xb<^|NtD47ElH<oteSVPEpD}(h<!!Ha4C1Pt{%3g~|LnJF7L|^^VN(izD
zW91600&xu0SpA3T1TAz_lk@Z9S<KB6vY<v~!De&0(O&WM0Ix93YXvQYGb-2%DG}<W
zq|8z>cF8pSvBVBq!h*&mbI>%hIb)n!>{~)Fl#o?o`?jolLR7K`1tfwK8L{*p<9h9t
z(t`yM=h_#>Ngy;uq1!RE2ib3OIp<PvtFyy^+lvy>9%2aPe{P6JytyOe%!#W8K&F52
zJ}T~V)ihq%rk}SfasS3cU;(FcQu`c16c<A2OZDqL+A0j5=`Sz;c*oc+IB*U0%D~yG
z12#u4r}skVkjx?cYU{9?Y$>-*X%8DSJPJ>Pt=ISw2^8!SkcdW5B>21>dDdX@+Z#A_
z$9WxxPN+Hg2a*%-SjLc2N)Ck#8k6(l_GZncC863SY0oX^1bXO-l=CTpMa#B>D<GB1
z$*5)mQ5~Sv$KXy2Pti8L7#U5M?T85@0mIGoyA4UT>q<}+3?<MaKk8G0h%+XH>#xN3
zVOtI7df}O$+2zhS$K9PjKS4WlN7RU88fWKI=Ur|SY6~;M;Yf=XKy%6;X^MZj@;U;7
z>!<0uOO<OO1&{6*o9re^^QGF)DqdFc^aD{~$2%mrO^O-I&{`X}!^;@P*vsWmjIBEa
z!*?7BaN>b;kEEF;341aXw&n43-}MX<5sTT$Bs8xGNgm0ES~N-8pA!XkveG=VO5O3T
zEo*0pJJ)uKV6(X@rxyJ``e;Q7)4Tq%oX}_Mkj7;x$VvGBm)=bJSPoP&-<Px_wIpM-
z;&Ywa-*>jEJ5-K&i%vGR6Q&FV(W%A1QH(RbABz|c8}=1TP7;avJg9Y5PObU_q4O5z
zHQx{?SUNlaEX@4OkHTZrO+`pl31TQxfBV4I+>}AMZ0fP^3Djl;2GeKYU{cWgjiO>B
zfpe#_2P8-7T}TY6`Ubqr5xc_M2Le0={{!Z4-Z402wOglqv^sz(ruA(Pe-4aHbZ2W5
z|J))4u$h?1y0OI80tDRv;QLCEkr^c|NVZX{bS)Dkf8TrJ=}x;%37sX-dzQOTE!Jo+
ze3=Jo1wbTk3m%AZeL?ra-oXE;r@dzQ+l~z>atss}cphlyTPM*_nMSJF_?QJiYs`^n
zUHSpAD(xoz!Sp&Vz;ep4UGci`m{vd{0`nVH7C%kWku^%E?iwsAh5I<d2>Ny2T(G$2
zUL88R)I?)h^tLd!WGfaWheJvO!t^GB{HxABJN%hpXTZr8YYsJGv^s>D*61b9(5cw?
zvP)4z+DgNR?JN6&^DbFn(!%>mZ3a;H2Cn?*#Ms;kwW!IY2uE4eu0yZ_4acO~RHJ?;
zc0vWtosYunl5Y<wh{`&n2U2u}Ef55sFtSyBGrWZw+}sNRA$%wK7|G6C0yWPv^+9MG
zr;UyK1B6$g6wi-xmy5x2A-40y0DOSe9|2MW*08mdEIa`5G0%~(I=Vn6)T+dHNFeCR
z0`u<N>Bo1GsK~QFITv{roUL_WDI!gFubXD-5lanfWf0*Vu@p>4w2@K2$t}CVuhmj7
z#GTgX)L(SvDHuR+bQwjUpja|fc*_*%dRvMT0;2cOpjaxv-c{ZGBkV1K-@yw+Z93g=
zysYFz4v+U=66NPz3}ubYgFIY*vBAU(+-hj4a*`-hv<NpSWpqVfsh8Q4>EP!%pgJ9h
z0C(@mtu=Q^NSC!kISWjIW^R&m@X$hsI7hBAK$Eyjhope^ChNBp4~jiEt{D7JUxRiC
zJ@c1)#3Vgl+eXIw+2P_Y@<K{uj2a#`X9lx|XYnYgO-`c@XdXIt+>Iae1X6c-`~@SZ
zU;r+`CP}6rnYJX$I8iZb!3&)7UCkP?S<v`(v`sRdI-jrIea(OqnIGXsldarjA1yT{
zk721F3Y<fJ@Tk*N*%+aC+l2~RTuMskv*Pb!$Y6^uBAhBJz@a60s%toixrmZdMrxK;
zz>GCy%O)Meg!RKBzw{u~(@sLVEjQy{E+^B#6RzBcXLxjClVYlHQ`=tfXxUrR+Rb6|
zr@Y<=tqcJmeZ>x&>l5iJ0fgr5&tCbs-I2sF#tbhF+T%iGeB#>zI|^eGU5T)p{?Hi^
z4%n&ucUHCccRnEM!tKyQ{P=}mmf_8D`Hf)4cRW2{ffjt_)`S6WYm7EtSt1n}_a8dU
z42JZ#6_i4MR=!YgEBsO1oftlcC>>juZUGV>ruVHVWBFJUeIyWFMzFZH-*RNBUlMmC
zBNMetPfhM_mtuxtXak^D;Bkb5Ji)$+4>eRfjDVEY(fV31WTiLvo$w1uB1pCgW!IGN
zfyBXo*|t=13UK&c#OIXP=MO2k^i5inA8tg@i>3|FjJr3uFo|T9O?uQtF45LyJh<lG
z*PDwcMF_uMbmE$NRG_w~Hi+$~-3B<iJp@Yop4?A?S4*gFiFyF>DuQceN9Bc7f>Hki
z(EoL%;zFj@$$}Zv*Mc$A%HPOXdzr0@l&y`uzaN5SmNt|^#H4SCzLoH)^R~$pXKfT}
zHe9WNl6m*qcHC+c$fY&VkkxZg>p7==YWuP=Q(xjCV@}5O_Jx^qeh{OnM?UdIK^d@i
zBL_2LDB3YVg;)#UKx!pTFJ(MAxer|F|4%zf*jW6?PEg-C)WLNTDcVypKS*8f@8XNs
zW6_ehJ)gb*Dp4G)#KS42pkla~KB^H9?!zgA@^gGA>7fNK9MNv^pJ^pZQGvqpV}L0F
zGCiJ@Z|_9{5iuJP(Fdl>+Tog7pD~*>!$2c$tR>?ONotw+pE%;qgzgNHeA=0NRllC;
zsG4@rL6XQ>&LHbpC-fNjY9D7251S6`iw%1g(6Qj3$s;h1JbN9TAN{8GyRqxh;5fL3
zVCE7GY)}rC=lAy24d*vo>!7wgJB{Aa$^Q0jxYdsFD0kfAaLb=DxgB~85PuadHo&I^
zuAH}nZ4TP>cq2bg8jkdJ4Ie*Vu5$Y2%JLASX+?acp%(P%KE<lc-<~G`PL9fH?unW;
zR6?EgmK=%g8QK#|9%@K^9h49)DYat=#*|_DBI<a8KlQ~zUe{ktAb!PTqQiNKBFMXI
zv~1%mwmElvsv%9^XnWmNUW;j`>hx%o^OZXMro#tsP{x?713yz+?6>&}Vysw|jv#)X
z!nNtkKSi!;R{RPso$0gw4@Tu`6Y=oLNqm|sVA7NM$j-#=p10m27~YZgS$zi6>WbOZ
zNm($Nf)dVD<1B7M@mmBCw2&#51oL(O@v%ku<tz4KM&RIz2V9tNrTKsAINV6^^S?Z^
z1Woh%#s3ET%jfVR1w7G$AvMv0o^GCV9_~s{r1)oOT=9rs>Wr;+HN6KK(q<&g=roqQ
z;G;FWV=P%kDr-%QAg}HJ<sZ5dYeIZ^o1Sg&cV`J;wqc+%6M$Bq_8Iz&bw>&yiYlMl
z72$kf9dyx%!<0Z2y{kH;xC>Tup^-&NqiI;^F-eFx@V<}-aeD+YFZ%Nf?X3#@^s2rw
z?RVl(x|Jsn_q4J($>ovcU*iSFHu`!FiuyCGSXyaJyk~Oy@=-M0s@HCn1>K>{SMoK?
zB5mC*M%DHkWV=-m)YOFWS{p;d{^l^;uDR&|AZVxUdo+V3=Fg&5vNBS-akmdij}S&Z
zpRKAcNt<BupLW%Zzxik$xxHe$J$^eKvzE(_Fw~un<^ZeWb$1I$_VGK7P35J9S>Z=k
zd|p;hiSiFoyZuI-0$_GwB{XTj#g?Tj9ZZOiz^vavMA$)ygW_QODr2vCofYSMZd*eB
zSX14=$$T|4F8gMPvj(Us&GP6uLlXi=_9&|%yG$shWA=MiZxdsWE~&t=ptrEr?m}5e
zBqcFM&m`jp4B|?g81~Q9*Q`0{pO^Dyt4#<K8|%sbCX-ZgnA<th5eJVem)3kgzYVOV
z$gG#~nw@ID3b=ewG2-9#lUwEoq;abo7Ck0`1`pBg8-EYZC@gjlYYr}L`8^>z?ZY7i
zceAT6ZmgOQbVs>j4&lhp)a3Y_j&Ttt%Hf94Cnu-NX7w3A95qT*xc2Xlnp7SRH)vFM
z!p^Gn%#$qC8<S^4CNb_s+wv{wa@(-I=`7saFW8Ngq>Jb93T|iz?JPGV=w!U=?dnco
zA0ruyZBus;+N;a1_z238ZtboyHQ_I#n>0d`v*ZOi5mSWgrYV`Lqy-Ip13zB{)8fd}
z3AkMrOY2~3HLXF7()CdM(b~x!9U7)E6|Dax+WMX-$n6tZ&*v!k>g7{ZqYw8b@=hZe
z8jy};p#!^P?|XM4k6JjPO)4rEk~(?3-})a`?Yo6!3#@?FS|m)VXAbrRj8I!~)wfE#
zc#*WE*O}@spId>z_O91|{njv&0?IpmVZ=PH+n&S~hV%xhxt$A%o+Eoy_BYRt6+*C{
zYJxD8TIU;~iL!^ql@&4i@@5vCO69>w*oIKZkUdO(n~xnt=w{Q3E~bL~pi!28q4iYz
zXZzp!&)wim9g_y`$pGiMgHoE<ZEod5HrF2Zs=r6qNXC8>cHYac42#hiU^B5lICM6X
z0G0NoNVpRzaZT=D%(*6#L9=GkrQukn%x?pwn_O4W-(BwITYfCcK-VFc1mzLFSy%En
zPMN(TpH#IcdioC^5b#hk2`%w-htksC%}~!`mK&;8Ka#Pt+GQTV^>?2V+y8+eF~y|D
z8(a|$DGv?SGZyO>EXy^(Cw>kE`;f)m<qZ%4*PCHz7H##J%8V*lr!!VV32gxBdnyU;
z(ise2tJ1!PkgXN=c~R}PxR{a=j=+Me!`tBxTP=oH7UjhA6C1vXkKxESG%N!|wYksB
z{>)FM3EG-G-7~4Cm3yOd0An2Jq`rALJboe)#>9-lbPEfYBr_P(yJ_8(xC85l`TLd^
zO(e3`e&a!T+J`8O<Z8UUygT^=Q(nr%DpwzS_vBuTOu{YEL!NvJv!_VH521_1ub<<i
z-6JXUKZHZpIa#;E*x7T9nOLew5P@fsSt~nv+*o_FLGgP7?C81P!@&pF{sqdmRZl`<
zxIZawePKjcA~YS}-;0zptP9ojn@VlTY)zlRTF4-~XS0%IAy&+`8CL$tiZ$}CPI9cJ
zjnZM)^ROcdQ6eM$tlC%D#gcF8LK32XRzJJlMIU_Mh}<(*cZwp!h^{BUBPOE+41#MY
zmO2gtyAEA^2Qt20r@qNzPBXGV{M27kzEMK+b1jF~>Ip%#`Z_=JmhARZ@S`)MobG&S
zX>o%E^>uZ7wT8~>8sbUQxP~HFBuYnVfqi>w*z6D)=Zf@Bgh6SRrL!+_^(X-@d&e6l
zqixk0>JsMDf|jz%Uw9Y~6~_`G>D>mI=D3tlZfP?Z<S*jb9fVK{CdAf2wGV`LaB+<r
zVrkHx&jJY-rQ6fDNXN;nsDfM5q4Vm!p<vDn82P3ss3QE^QP4of!-?=m|M94#lqG#D
z^XM8bbN861DJDfycz&`{?JDi<A41p<Ph2*#s(oAOwCfHv7&sjKN(mIcLY;WG1sS#l
z!NClpSL@``Htpej?b3Qo$5}gLtgWR0l2W$ZRFI8^a`W<5aARD;9aopN!{L-b=`)ia
zzvWk|`K*4Q*Eb=n7PF@=HNGXLTB`HEL4#6QIoCHEV5}T8<BqqNZW9;B&tGMWk9Fob
zOugc!@tlmxt%V&h79wP3476c#K*k$vF5d|lzQu)*-D)&tbax^@@f+=rAXGjLlqN++
z%!F|1N(xnnv%f|dQf%8KI`lm^WIr<(jb20XSXuv0;E7t0p1PHM@bN!TF*36~7c#J~
zh?6coFk=rF_CP*`iG<p)0{PnG0OtR8p#*V_A`g*7vUFJrUu>*)Gh)9#9gq@3a%A94
z^0l7IBTw&-p1GMoj^Xc1hO0x68;-sM<86$IyNj>zOVCLw9iKmoCVmUQYSPstb$$<N
zZyYn%kzq<K8b13R%+w+cAMF$G>4o9Y+`9E@?Ba6@{0_OW{k>*#ETORd11t&C=Z^gU
zE%FE~CLy!6TF8TL2~=|pkCZ{bDM%(b0Px5=ScfES|7ne`c6a8sgYF}Se1!iXw33)Y
zHvVIF3Htq@43cf%8VR2JUoGfUYX^l?Z@qDuXZ7p>tS$HRdW4#A@H;+6&{aLy-gx18
zG(?NNH2$k5O%OCF7(HlS_W3W#V7JJGoR81xv;^PDRqZ?`xj4`>nGifF8A&9<l+zcU
zIr-oO&quU+J*GJHhy-sLX#R<OyS)gbZpT+PspTLSHa<_U2IeS@NWFQPCbgyg?E143
zr`I_92A4J~a|M@DIC`Rd3U!opM*0UNhPHWmHEEO2tR&VG2cZJs?kH9AQ=o$OW=y1e
zU*K~8@{T=g3svol@UjvezRTjD3<z5!VBsbFzLfD%H@IP#=|!DDA&ZV~83KfLL`GTq
zIt?+b<b7cxOxMJH`{6RGF5`<d&fZ1C`VhPZX0=+pml9uz5_r#E{o!o%^!{Q8G684H
zREne%uJ5yF(OYft`J+CEh6p-)?~Bo~0(FeP_sIFb`x$S2k+3o|K0p-|+J$$MxC9ig
zjseuvF($UJ40I#nxx#_aI-SEJxv)u3wEN#%@r^m-9jbMx2&C#<VM;2(8h|p{$%#!9
z8nziGEgRNISd3Wx=Xk1ApyM;<&A4P4*iz%H<S?cU>^%cv_?QF8KgaX$HWcBy%%Hs{
zY87`Sz2(kI3t7phOrxh6mSGaw=9;^VU|-^O&#9+s;TB$Y1ZmBk_TSfa0lj~C6$3^d
zKDbD^^*aKA-VzU!op~o2OM|D<Sqlux<;9G}lph`tM8W>WxMoW+;S?B)f{>s%1|%MV
zQ}?AxxA&Mr5WVvz#1MD*w(%w(O6PWnN(01`hP(ny$F>pf1TN};Yd3+Iw+_)7Gq0%>
z88gaN9K>Z<e3u$8C0OiEjI+o?#(`)YYs{{QnNQE`a_~ThTA#tO6kACFg{kz@E&;CP
zcKRfmyAdVwDU@VBKSI>ZMH(8|*Ni2hS~<Wne&U%!YcT=SJC|F7K5X}a%dktWnfHnt
zCtXQ|e_}4TyztLbWiv8SmYES&rxTS<f=%LH#8GU8v9>$?|FiYwsff2gBxgka_Yqm>
zU-9H%q$8o@QfKU+x?M7tDhKqdTNORU(9hH1<*d-hZtO~?Bsz5nKnM-R$lb0!JMSl(
zS}rTxEx57AQWa~+K9t$ZFyD_Sh7(iWbcY;kuw0EWvKg*^CG>TY{Arl8l~(|QdI05^
z90+eOw-ZukWa6ZaenYCUXup)0CtNGdvES~bsC#w*JwU?0aRIjQv8>7>5$XS0q?Xu7
z;|z#HXY>75UT7|PdB&TIn130;m+Zkx8E)E!!<q2yS$nquVv2;70nOb^950|rL6w6q
z@PF4pLdhIIrfQ+sCA=;&5YU*F8+-+3_~JY`!WEK3m}2r$KT<aA(n_Qgg51|)ckd`<
zzV}<tK7v?V?CRd3k>LUz<WLOp#i~TT#-jixE|-gU-&`IQDU$1kdaPICRZu8)FpT2R
zNWU#PFQt9o)e-0ZmUH}l>bj{BCIko#6QvSdUo54cAFnH!M@cz2L5;L&>=1^Z&J?hi
zGdH#U(5zI_>+@|LLR3fQY&HGUNsF~+ibXiF<hb?FXI(AM4_0M7t}LmG_Lg7?*(h$A
zGp>tcV2Z_C1Du~mOM!Ial;Y<;ZaU#t?@q7{H@43a6tmnsm7xm5wEcI>j}PAq&dq%J
z2S}(LtxZ}1Z9{)<n-E~6n;k<rE_5BQw5?VI$$M%>GE_;4TA;s~DFVsapb1-(ETnmJ
zU63wMA28FvXMxljiB%s@NhWq-D8d-Qh}XZZS6`XON$|Y^4&n!ON_2{a3hU)A{ie2-
zVx$yTMuY>y(vse`jcNL7{f^zHMvsi(DRoXrod1Ck3XgfikShg5;Ii<@4tohH@HP}r
zQz?^q9U&i)9y+B(T9b!rp{eWV;@UI=T_>E~tHE9#%9ocKT0R2!$T-#~&$^?&EGIbi
zZcmbZ5J>2|#keB^d>rtSgS{t=cNJ_yj#`||Eg$2&4*H*vTwSb+xzq+dM6YgrWXu05
zf~r_>z|52cV2IWbXy-Ht!0ZJa3YVDE%Hw~1IjzD}<WO`$@v7V>p1|Khy<G7D1#LZt
zz7=&<hWZ}6di+nICaHBhz;rUr$u4ZC@Et~tj>W|-<uMWfym2IiaJi_s+CeDnI>t}~
zL{bJdV-HNG28iX8Dg@-EV7OTNJ2fhP_XgrLLkAgKJkr70Ze$)CGm_oe($l`8zuZf0
z%IRi|;rxc)AYFgW?&4^lG|-JLCa@M1)`nKrgni0(`sxRny!dIUjxmkE1|B_}oM$b~
zq>U8=qVyI3nQ>fJ4FsCt>3Qw|*N4Y<5Xy7)Oa+^cCs+=;>lNZ6R4Nw6bB5_kj$$!E
zW$Su8KM>~F1rBSk#q8S?Dtf2ME{LOi31(dN-?$ymKli*_i<J7(Bjg*sup!yxaEVFb
zWN?~SHoF%E889el`B>mhQHfp7U$9NJp#h(bPX@QV=v`6rvSehy$oJ<ipCNdWcYu?P
z^tf_)`4gW~aOyrJ6Rc>-9Wr(EqNNW!%Ya~S$&PV?%BZi~%-I+aSYrxB7cXY2!Cfi}
zo8YS`AYG$F$=mN61U58pFA_*3G=HFW&i1jDg`hJxe1(+l+}v<pcb$W4o;i7#%>5pY
zCF*_b2Y>L;Dg>X4MT#AdPdp@B_GNPh@-KEC6dpN03To%%9GJE{aWXS${um8^g%(t?
zE&F*~_q`4Y<0>sx+%>z#k^c<wp(=Af2_R9nU~hM*@qZmkV^p+-bgUP;e>fN^shmow
zZ5xn%Uqu2sKwr2-N+G3?3)gSs?`ryPXgEXnXbmI%o9ZJQKC}_?zXEaiub7jDKXDkG
zmqXKb^lYH7NGQ@792aAL`XcZor+OfYT?t+xJh!I;`C37S9Qjjx?jjP0@c*TDUAdo%
z3Q23iY?`_ZNO71!Gk~t10hdC&0s^QzVW!&9XG4@)#j-WNP7X3`NFsK_NO2hB-4|PT
zg37VOx>+QhJfSD8vbkZ_mj`Ogj&EadSUAG^3C%q}DZVj^x@<+ss{$D_-FcY^Ng`n~
zc}x$OK@xW}KomE{PNNe(j^F2p)BTlPM*a8*AYMTD>xZkg{9N7!h`>!<dIlWXW|v}5
z2g|`^dPi&lTWFP;7@SoP>`tj6n}HF`8o`DPN(5}~(EvVQh6>wYic%CqI1D6Ie8#`Z
zBN7|9J0jI9e*RW!RJ)|nSJw(IAPkT#=9Wk8^d1<|jEmHST!d3TL5dQ?#PD+La;Wm)
z*?~z9Z^gW)BI!wSReeo$INq5HFpXK<;h*#iW+%o{+@omVeP0s5edozaj#@aLvq=7l
zTdpjZw^9z<Q4oCak!Sp#Z`G{%Ul!;fXK4h_hKzgZgHD@se0VpTXRWo=tAD>34gO7R
zoU8$I$^8N)A~mHizjS{lT<^IuP)09<9c>6pQ{A)UI_G8{k%<klE-{~(%Y$u__xb#1
zO1-2@we!%uN(s>FOO;DujSpp`$Lj!-Fp!t$7-j(l=eOKAtN2xm-YG-P)?t(B5W+{=
zV!XC08Uh@Bv*qlSTteA_B-u1Q*2@D1-KYgkVE-|4WC^a_epjSlsrxXjv%GNuY<#Xg
z94d5ui>AUxz^+e1lK{=0gDkf`b@MpS0T57^b^*>DC&sAIx5T|6KA*|+bq;}Kn~ux;
zsmqp(G8Vllm77XBtVsDbUE`Zt%<Dj)juXn!mioJh&GCXi^gr`pwP9>|Pv0vwp<)nl
zpSIi0JL4`j$*tndUyVqckj}C_{F=B|><=<O<8Z6eJ8{^nDB_j~jWZs!s^H-wf}y@R
z#3`LIW+g=H0)L-1$j^UJFo%|rcD<R3B`q<efjd{4u3ftTAFJ?JylK7^DMnM|ILxsj
z{ST1-#VXcvK>d9+1y0(#KEMy>(v`*;wHTKw+HF6u)&JCYK<j<`bT7!NCHq9#{||3<
z<7*W&m1vUGzFHV8<-mnt_K+z>b51Yffl2H~w7Qe*sg~JImmQ9>fTV@2!M){B_r&9~
zAw%}8f#d+p{}E{I5zaCJ1A;plBC<H8!V^e1;lQH^<Sht)GUz2kfiDt1RAcB?%*vc_
zeheY=q05fj>u^lm--d}FOebuOzbEX+g|;ynZ?IC1aFets1JI+DE<Rr-BglbuE**Uc
z{-K;w%gGtlYts!DJkhk+6M2%Io3&x#-+1M%TH!&%P+NQ3xK}qbMMbAS8GfeRXS!F5
zVr%g-(7|SI?u-2Qn8ebZJh@3sF3@Hmv>c|c(g69O<;i67xp#JYt2I#&34Quo2X~lH
z(<UK{TnJ#0uW;Hri*j^OPLu}z`Pla-R}IgZP-!Y!_b|XM`mI1@8k{d!1UJ+&owEe6
zF&pkKTd&qVnMe+M;gfd<M*pzJ1s~ZV;5g?09zO}611dL5N6N08;>sOYZpH{(>V-!q
zF^)T*V^mbI8AVL9$mRx$D7?p73m63K@UH|>Giodm^^&c8t{D4XDqbN9#ZC@rGU?Ig
zT43kI`D`@JP5Y`ps;G>kH$uaLv;CFF@Tcz~s%sC>Wx8gnA?HLzViK;#INEU7tp=E~
zdpV+VXg(1X2#P#B&=>W5(Ng(#Se9nr^}fR;)nRzR3f&V_<zs^P|Mkj&i6NRR%Dt7(
z&zZb`79^NnVkxxwa3AGR_tZQkw2H;y1m*YqY)yri-NjI2xuS9z4ex_(VOdmGdjRfK
z-fmMcTy5#Lq!TlWs0#aFDLv~hr2tpf-40<$I9yU&s$mT*h2Gk}<z!WUsI%C(jU{m{
zl4yP3Y{*^iCdHtRuwIYrBMRnSIF_`2SS-x?El|lm8a3WuyUtp)yiPBoQVSCswNd%}
z_kI8)pb)=LyrgLQo`ymLt+2wQ?FzPF4&MY<g^!uSrHAD%%aoepVT#qotK^gqi$Lj4
zwLe-TDW*L;Id%+xyb~=Rr8)-dZtMqPtA-?-MQ2mM<l({Cymv_;1JNGfeE+tIarNrR
zwpxU6ys?`7@F_hA4hjGs7o*?8`67r9wRy_og#U?GHpLU*oIt*7+u~4EwluwMrKUN+
zxK6-J4mwOizHcGAW-b2rC*k`%VeHwpE%M;J%RW1`fz#@<`gvoU>9tKFnBWDB@5c|n
zo19f*7NpE6AvJz|NzAx${J3WN!7d4driXFaOmmAF$CYJs@}FCX+}r;V_K+&GKDRGL
z-eY8^Cd)aOY*I_xix)yS5_A18CZE&ma??^~oNA66Z6u=b@Ve{j!@wP&O<fLe!P6^#
zU2N_<n~ZX36B?2+QteiG0eAFb$_r)*VSxqy4J;9|2;{i{ZLTd=M=SlfkBy*yy&qxH
zDYCza*)^X4j~{(&_E?a@SpIGZ%iN(Efv_teLLD1$jZl2r<sRH}(KF={tCMv{Y+m_z
z5G*1f%EINWceC}buXYc|NSIM(q!;)Xeo)}IZz?>y8xeKD%!63FlBfLq`^35tAbfe)
zbV03hxfbaMjBhB=J;5bX)T-@isus1<`Ij#`XPj!+S8dmgV~oi^TLOzB4MFS`M<r+%
zJk{<RJ|Nt~-{4XhCuQfaVcA9~+^X0oAX8O?o6t);0W?2XsdZx$1OoR<vK`&1BvrnE
z4h)nVR{~)?*H+1vh+2{21!CUAu|_aJ$VdD)f24wQP+psD2I#75dpHV?zpc8x&O|S(
zS{eAak4@(<mh9Z=<GBf@LmK8C2zGBqsV7x{BTV2bA#ycF@W+VQAXIUaUWDAbp!jK~
z-8}^UWXFpt%bg+UIx_AlfAvXp`J+E2_c8P}DgsT3gC6~P-Bs|vvjj_eI?4Y=ej!KT
z_3S*%DNQ7}TAlOxVUBof9bF!q3@up?{Z=e(&G-UG{<|X1YP;@@P7BPDmaEchE`ztC
zGa1H=6#3=wl*JcxwwLu;H5wVq9i0;kH5JOLTZh3{Ivp2@ji$ix1wxH0g>Y-W9)4AJ
z4I(jZSzEs9qKoNa9fHQe`E_^<F%D_t|3%CqWanoqX@Y5JnFZkw`GN&$A9w4VH9mDS
zvsL*EKXnij6j3_b^DjBCMg9kS`Fj*Yffrk>4Nvs*p1!P?f{cEJ4u;8*hMG{AhuCWS
zeXn=^<l9vK7`42FcZ&_Qq@>{$hu8i}`JniW2h#u(JH5z=6pOo`9X;a2L^v4wTj>p6
zyinV11^H*X$<2R!rn-p!+@u;fuN3*|>MM_B1-OIkeU0c-#w6GU>|@>zR=Ju`O&Y!F
z1qKm%<{qlRTckxX%b5aM)G-)DiL{S)_%c@s%onUlf-~-Wj5UZN-tF#r(2v;61zO`U
zBcz_rsrp<kxi^6wdYEaWlMBGv@73nC%e`*PpHQGRj^B->M8~Dg$6c25^m~XFSDr3U
zYfoSp=c_&vA$)Hy+fl-BpKucu(HHo&3tn<r+X_4pIGy5ec5qhOyi11vH9h&J9p?g5
znUYBi`4tlj+BWTp6AJgg4OTo@Y{jHMA(2Z3w|(S-VGo&Gkn5JP+*%TWDGP1wv~WkD
ztz2FSoz%epY*NFdV3dRqXIkt`p;6k=+vkOheC|99%>S3L5oY0<I14_PDQa(*L-%e4
z)tdP)^kez~GbG`KH8*cE{X{3vY*WEoFJ$iTSV6w}cH=6(2jvN74u+lUN5@WhmJ&lB
zKz=%Lw$wlVsqlXb=d^K*Bf}2Gn5Voy#!eq%5Lgrc@Qe&A2`PHzB%@xLV@jHBf^|nr
zX}-tFU2O|^h6kqENhQj?ABRlZ@o%$CG{=_T_V$yj`i8wIDao?|sitUp-$1W9Mee=7
zfA58yFzO30Z`s3%yidsVskuWfq`Z<|JgO4rL8NIY8!1miFQmhUeb?m_JjhJkr_s#%
zk{F7WMZntH5XeL^X2ESmI#>9L@7cEOrLLtw#$18+BuoDv@RGp?;`u<b&uf4A-%p+^
z0^JtFL=-wx8{&8a-wGkc1)H{UuiU|xV140Z$H3p1kKQ$drbX&#x_qI?`fE(q2&`O`
z{v6X>U+xYnXKeUs*7FezyTNPyBjn?4N52IOyZ9x0G3Y_Gsh0S6N4N67lvi@q6>HwZ
zl4e172-Ez&rnSbIC3^M`T1<tVN0h!$`xMxP@W)XsU~yyr!SwGkBx}2HwZXT2%N((Q
z<1dm64y(|Hqew^AY;1iPBP9pstllb{3x#qeiqMg+Micd85>*+?C6(-w;G3||D*F6I
z&<<<mWght4dXM^N{`E0F01IJFGPo^fFj-SEbwX@%rB;W9BlA~ME*IZ}G*^J%K9o~{
zA|gBub<fC6JxPvIlDG;_j^5aipQTVw0dOWBZ8wT$AWoQXR!!@Kfq=JHRp;7)E^|IO
zgrrwI1dkQ2D7(Jt!zQZMA%|AS32ke;Kf`4>eB|Axq$olND0LVMks|YQO}|BnI_Nuv
zipEd!%vpvWs&-dGT(QNuyjbEIwVoNF<t4DWvG4ky2s<HC;KIQNFa_XEc$nSu!p}lw
zNKQ$4?5*&wq2fL#U=+rztKwe|=&8c5g&}<L*TM97M!XfYIM7ie&8gVW_Dt*X=;iLo
z>mQE#3NUJi@xD1+hOg8n*8_V#jRFr<WTeEwv%!Y?f3trIe`v!KlVao5ySNYiuLKq?
zfCBE)y2&8&iwWHB80wL}LkicrrxIF5^}99rbSLk+-~IfPS^M_h)@%mUngdcTyymzX
zWdQ}vQJ}-c7Uy)IK@pmXR))(?*@FpaCP~FixQ-U>UVmC-p(TmbZdzme4|2!O53J0_
z;X$cdR3D1Hh5h_LRIHOJlut&8{}*4@RQueQ-TzAA+<VF;LbL4w5m4-l#H)3H=mFTE
zcw^dgIQauXS-VnU3sN1U3C$M{iw0teJGp=Pjds-(%-Q>MNRhC;Bq4l+L(08_aa}bt
z=BrL{Vl#_-8lYGo#}nSHMZg*d$g2xUY)lPvuyZ$m80K9H>$&{WoP@Vz(8HZde=cb5
zbZ_ne-a4W6oI*$;Xt$GxnZ}l-K(5D>pm(IKn@u>u0KO@FyvPxU*lc7D7o4)ZF7L^X
z2_*BCCz)y=!#&R{t&VXAAEj2H3taG<xuHK_%vTg!T2X+L@XMp4x7gS+-P^2)N)&f_
zpC)INxHPm+&nh5naMlTSO!=pL5sqsDS9tvld0dlV5xifXsvuyui%_g&4nD*vOFK|W
z<Md1*iVUFTq#~J9twVTmTq9^#q0%YBn{Ll{Ha$3B2_x@g`?Dq~BQI<n*(hTLDo~{*
z<9w+cZf1=J%`~3AX~8@$7=0A~+kgx7_IUq`?~gZ?eR5(lz{@4W*+QlI?oXJqdBCVS
z*kj9`Ug>~4($_g&*P>j#(*oe{@6IV~`OlaB(3vGA`?XEuiJ>LB)w{ov*o&Lxkkg*q
z6>sCRuzm2iCOm4E3B1Bhj#QjFw_huiY!EQr8{b^3&B4=Rfz(-Zxc1>}<$+0_S{CLs
zz+<YbA+cuO`XKaV8(6tq26k8>hta^#=v-M~O^4~}G+kvub25X2(*Ye(_Sf3Bns+$k
zjxW|oyHWvI`#7t{9L`}T;@}@UEwj>b^dbTA0C_B^@%-p7clA-{KIz?Z6=UDHEuZtf
z_k)hNSY(HtPQcoHd%)t45!K{Gx@xA40G^J(SR+{hc6}vSyu^T(xZcsoA~9s@K46N6
z%9SUs_@7?zL2W_t0Ss*hL|Cslv;_pjYc$u9LW6jvf`3Kd<9shzwKw%>1_X)yK*-96
zI&^JVd8W6aVIh36T#5HuF*;hs!QlIDk;3UhaYD9IXOSX3)EA8`qY<sH);O-IABo00
zBlAl&sXB-^*RLV3bPkE0?zAu8j?C&N<3Du580;qAXS+$@b}LH+zWZJyITfftYawWl
zx37pJVr)g1Pw<zDP6b5@`8u+%$4AFrl#Un`4yOSi8gOA{H|_m#Bh^ea8@7E}*4VK#
z?*C?^m%tFiRC>%qTZ$9$jn|kW&9UBndO?b*cP!^8BeVfhyz3W!OpS3x(t(iX=}2HM
z!ZzI19=`kX9xAQrY5c6jlAFyqoz@23D3#>%thG;vHB{?m^l%>EY)I4?s)qTK=^(U3
zZ?L_+Ul@=XsV=ij_|{w7Et{{%CKB<Rdpol(pcMC)gc9N_<8$rsO`5B`0$^oH%b}2!
zIJ{PP%o2R8?|+H2<p0Dz!jboSCzGHavm$U@OP#|?iY$toA{|&O_x1e*uAZEKc8yUH
z$gSOGvcAEbJsU<s3F+x((5t-4vF^H8L30D{P~Ghrfv<sQ)&IUupz+7D%&=pAal^^>
zZbsgHr~r#F4#5&@zB@>~N0q?ed&6rp@W6}x;dqycHUY2h4_iT9tdhlN0(Tnu2h5h(
zz~C}rk4P-f`a3R}<6Rmlj4w{$UT%9;k+$Fh*YeYdFL7&xiZ`0pJXEqiM@V>95Inph
zXU>x#yqY^D=q}Vys3<zOf^B7HKChRGL(!J-^NiKaEtZ?4CfFcnZ#bT5{dQwsj2e={
zLqq0^lIrylR9EV;o3A)rJ0dOFOsh)FBHSkGQbR`WT{!CCZjf2^d!lb4!ms4!mww<)
zz%^iJd@<#`OHIr8C>%!7Oy~7#@*z;S>S!I<$UoabM>m3?yK2a_y)`g(=J57jlz#W%
zhTV&zuqk1JLO-4>Cw;2hVa0=06+TMj8b{;r;hKJf`RU55a}ffB%mTyHG(NEPK=9po
zqRsH@auLP4HF|82i3nh+Z4@4S_eBmy^g<#k0(fa_PSjMJ?sa5#=XK+~<n<||ifku?
z05n`TL=|;^p-+_ie^hs@yE5nxDM2+I`MtYXy1y*~l2?F0zyv%&0a|q#$9$PPJUvKL
zMLXW>y0w`QE>llJt<=M-Eg&%ql^u<I=WNDkF1-h?Lp^5Zsw}m+0^<Eg`kAY=#7zoF
z<=6_W=?ms*zKKdV>v@062Vrd^qN5qxP$Ut}fHw=4=r7J=4EO9*3uwOwIfqVBrP*eO
zcliwjPh67dl5F+!sH%med!1SIZ*|4OZ`TaQ&@Q|u7-5N+q@_hVDDu>BUcVv&Y!j3S
zaMnGr{w&ZYGBI!<0Qq}!<)fP_3aGG!Rd`9A%8rL|6jEhO`YRxf$ruqeMPL}5nzn6M
zS^CB$;4X=h0g^bX@dqG89Iqa@u8U${C4;v!mMO7TlF-h|WisEbxaqKKN($BDySacE
z>;}uHz|!VgC)CK?8@-n|zlF_1C5E%``K)%qZQvpA*yBx$^nRE^Y+5hyQa+y+qrr^#
zjx5NeQ}m2X@JB6xu&8mhCk(NcdWG_=t53R>#R`|+JeD@!KtFY<U2MioahwZF_<*Vn
z^K}9S>ZS0=O#Fu^&u^kKAAbPfg0Q3M!-=qAW=<yNVs1zsWJphEOc8aD6S8K)NnFK`
z%paW0iY_meRRHl&T7#iDky4ZRW-N)bdY+D7oQfO!b3>nt_CWka?99@%_2Ug{Q6QRR
zq53mzP(FtK#>?CV(4!=5@d(iD&BX+lAh2SV>__&YzqYBnyWC5NxZr5O?VJCTJY8*X
z#2cTu^EIDspMu|tcA6C}w~nG(A4J#^qS3f6%G;W%>S+yFjie98lGlspI8^HsC0U$A
zqk!Q9#-EL*)Q15!zWV@M|IMl5AgG3;JKrANw$$}{?Q9|8a+B-NR7<8nvuUA4LAHA7
z5k1MbLGGcWlSL;KIlCZ-e2s5tF!t@WEE^>U#kESBr5G2o2irWBvqwT@>WpXy7A9xt
zo1}}eAWTpH{}?BH6n2omE;SQs@+ciq>wBaK{qMb>P*IL4<-;eqgy70}beOB@qT%sw
z`=T_=s`k#@?<{|hD-Y_}run~7P%wlQOCDp3dHh}X8tD%(A^YR_%zz?o8qjNI0yK!`
zZyl$=mr}O&g`a|^V4Q>(!GfisptReH8&?^7j6hnSd_KJTkv5AO`2&#o{5c-A=tgwa
zM_W#+crZvB3Iru=9`eY(>CoL>CU9yteJ=xvqy$zT9U2CrQYbG}wU^iK5*ZNmDooc_
zG{LS1OIvOy{|Rr8cB>9AE<mr{o%1Wx+M?9QXDD(heJAR`j<AvH-~2jQIyeIQn5{e{
z2JfAS8_8$HnZ*pH7@n+rw**$#deVWC#pSmQ*YY-Kcn-yW5umMH<H9Z>+G$ksA67XF
zLl$FAGGx1TL%Q|0A!;se+FR6x0^6P(7Orl#*;Jv5fu-gtTZ5}t_G~m?I|6~xG=hVo
zpo>QxfjYFbkHHQ$=Gl#|F2uqa$J4&5V7obc*BgOeVivEPFafoWED1mhk469%RWt`w
z%{TfGs`93>{A4mRbE6>t>BNf=o^}LB?Jud8uc^Y2+>N87!gEVvkri7B@L_F14OjU2
z4lk{pyS)~WUatg1lJh0PZ{1ydmcZtm;03pM6(D;|98QL!hJnb@n}|~cR~$L*ED;Af
zZzF$r8>JVf<HY@IQiPhnVVm&WJ(6c~=NJ$zaXgcUGkmQr56C5)w)#9J!s^&8;kXw^
zd#A%+jmb`*M;WteS}~_9bsj3p6Q^Cp12>Tgeps{G=moz%P+&Ki0DS*2<_9rsfM<dU
zL>q_iNRCYl!n!pkK66NNJD}d6=?Cwz=|3%!@uYda*vKUKr~3_Fb!^$ll?~hk8^nme
z0+RTqa%7|K<X9T9S(bn*MUpK#)^0u@?IgzVupjv~M?k@tQqjwrLnZLC-+DQ4v1HRi
zoV{Q2*JnN_`@K&G{5JXLVJ7@`*>I*13rTKRXA>Ey1kO1k-7SD`K)Cf+Xbl&N6a$KE
z&TRZDr|~pV4=J%4B%*xK6Ukc?C;q<xjp(lp_WEN!F}FJFUWYxBh9<?TefuAHqThu_
z^jH~U&4vxwRjr3xTx})RY0ZR*oSZM8^IPZ5`bB)xywg;2{)uBkK^03`8s=%rn#QmY
z(`M5O!svHPG5N0JKtccLR285=cG*-%=M~rqm1x_%D)hwDo=f68#-RReLVFX!MW?yd
zs1S!J?-CI-eGP6u6cBdkjW!8Rv(0fJD6p%gP$>Ru7qE9|C+@gng4>Ykp@T?#3_;q9
zEkQimA$4m-P5@$oNS5#`kD-KDd3>Gu7}rYvbl1RA8q?+wr411M&|i}RN)kn18$L+I
z$H{6WO5H&RFjKba&_*Y38Hg&vNDAHU4}#kCH^KN|i6?hTIuzT^DU`$u0=|KL%40~1
zPi=VOawx$GMfB;GRYQY+4m46T56LxyFWD?{aR?_XEQ5-6HTOSthz2YmkRBop@P_J$
zn<YaS#~n8%T7n}vX<$<+8NsfBAt4~+jku3$0QUl1C-oF$Wao2w4Vmf^ngXS-AB+Pv
z5;`K4%o-QitjgMiM{$8h{S>>tb{ZXW*?bY~ZaYSkDOPq(X3&(`?IGw_a$w!a#tU+y
z6geXmL&_Uj>`AB=Lu_<TB+%{f7r<xtGPlHL0P}R`>cpkBY8q=1^0smkr7yo?#JSg<
z?!u1bowC2aBJ;jfU~k55%<LP3zL@U1H<Ptj)pf#$0yP`*CifpY>#P5@ytBA!Fs@);
zf~Ri%#+)zqE}e7*O6TC6@4+P3(3Ye^`l?YH!Ad1sa@Il^JCFZx7NJ^jT>ZYeV(`z>
zFT>~?aOnd}4$ApFg^TZJt`Cb`AhC^)tS8!qr-@C>^upcn{r3RnJig6qJ(89I(hWZd
zzqPNXHcaUsqeu*t?rf_&aWS&tX(`3=0%hews>Xc{W19kPuzsO`4!?h{)`TQcy>9kJ
z`0n8Ptu~;xd}?Ki7}0_Q)m>VUhV-0Z_b-W6W<U$gt?uhNA7AY1wM$WB0#44A#>lap
zJ@U}}w&t;-%>tvnO97=5!N09BDF7&-?&iSVbG5|ub{yJau1eL|sUe=w2koJ1z)=|;
zJL0;3T9mX--}#QZf@Op~olL_{BSndF>bNv<r4EcK%6T~otBeYt<p=Xy^~AJpC}wu|
zjj10z*q^1M-_C^7Qj<}BkEn#@Ia#P1QVjEp%!MO$CWJ#T4UD?=PJT8p8&vf$jyk!)
zr3^0&u=^@ISY*nw?`S=AVyO_D$0%{6`GQtzY&#~DI)}F%Q_^<3Jz!}a2QavJD;EVM
z6`&xC%HYu6#6?j>Tu#rt8_~QIv`iyEuD&4y)^4ZzG*FBT?^br!;W|j-ZQ9T^1LVR%
z5WeGG%`BG<#^iwdNeEqB%ns;*YxsI9GI<_AR^>?;bV>M+Ed4CA=&?R~aztd<e!zMf
zRjkd@^rGuUxSO#vzVT15bX21PG$>snPZanW_0id0>k{f}v}i`gRioTQ|57TV2{b)=
zVNhi)+_X%{^q2jzbM=P$GrlT{wfkw81+QZxLa&j6Us=do4ah*2(Nv$Bb>Bar9Dx>q
z!74z1<l0=Qw|>r1byipn_0=;C=UWwDKq<NJ{Rr2`0&3{fTx3Yls$4LeBz`B65tl-*
z5EV4GbBnbvmTx-h8#K*eH*}lD5&|}yzaMqqN40vGuWVrq6PidX?L(7jNcv-^aT^E!
zU~+1LPNNO`^6Z_OVE+w9kFy8Sqr&9mj7Dj4icbhcu!!C)9y~%viEoV~P06{gmW9*%
z^IM?ghQ0yYV3BzR2}IT-g@hD+R|p{_|K!AN&F7(5-{EcwAY__>uoS`*EUKa*P~%<i
zOx7w6bN(P#;32YwyY-r1P1iCmZ!CI!#ep%KIUDyP-Kkzq_M)(V8S-4J(l%C#-J!DG
zg?^DHY)uMYKqkx+u|Y*p0#Khq&dNLT|D1aIu`(lyZS}nfa(`C+u0*bFSC&~_<-blK
zn!7;?9mL=VOEd|^Fke*%f!@SXW%Y9aFb!s%Us!!MyjdKVFR(kB?nrV@26EBN#Dy^T
z=uYTN=&j%RRrC|<#YD74FJB>};xQEs%QfF%`M(14;R0`aJ&m5Xm~p=JA{Q^XBe7a>
zz34469By$b2?lxdVdw7nIQ=5+9|<zt%|41iO?g4UXg2U3>3_jZ)j(!{02&JUe`X1F
z-`{S**VG%)*T}tS&{KnnU%l()r8_L45oiou5WoeBZ(N#(R|oOfnkb7>OLrfxmOslO
zU3#-Ldu!QP^T8t7`Eu8Bv|Z4QT3u-LEfnEercL{9Zo&%Ca;Sr>xSDay&Z~SH5_M1n
zh_pZ**xtzMP%pEVfd|uNs8sE)8f_Z*JCz^U%>-v$fRA!W5aC#*zz%@tt4;GJX?kUS
z_5$VFqt_!GM<}(9;Q_IzK#ogCt%CHj`TnZydKNrq!yU~2IugKBIPZ+BQb1QVpVIoj
z#TH=x8W!<HgD%gNK?_qk#YQTsjKM~Z^*33SM2{p{jgQn1q&P!WK8WU`ta7;Lj14@=
zdzRP6c$o-+9E5;?V&c}9Dtoqg!ie9w*9c*j%vrbOS-&a57BR)Z4y@J8xMUz}2d`Z`
zq@x~z`uLjLDeCrsu+zbQh<DKvWTEkqFMV;3`OmJL{c3Vt9>n265E><wuRwtY{oMCz
zj=Cc;`NCs}%5AQG$GxZ%+;)!Z6rQP02h}MS&_hH));KeY+)il0^f@1+w~#^I?ZnSb
zM&5H2mKayg&0h_X*&@aE(+ax=A$f^8G*Z0c{?)U5a#Q+siTm`x==GGCO1?-PWSIco
z7ip7+4#7K=&8fiO@r;vFMfqkZGMTOdDhPj0y{gr%=93IB`#a)&*l901)}C~1dUMq=
z9J#3V4XD+L_$HtyIBU`aBUHUHH-|ps`L0o1_ft!lKtQhK{#HOjA~7JvLehUCh6%j0
z;%EOQ(Oh#gYqV*<Jc0ZPbW$nPOb`?ykLKn)!)3TS5gAOL@@1Q%SyMj8%w)SJP+X8V
zL4u&zb4s7o6ZITuk<87QTK{}4WFS2YEhv|LWpH<2u&*SC5@oZB9rHBLC>uqob#y}g
z^q5Z5E{OS-gv_<~R|%)PWNrkc;LzZ41wO0Ul&w11Wu~Q!GkwD%Lq?4@`81R*)W?)!
z$QDK(0QX1;f-QRU99Z~*pVIQ7Pop(77YDPS6(|@_n!9Lhocd(Fma0o=Cjc*ZiS~zR
zuC~-Cfgb9KN<}7UaK{bvKVZGCB7&{CY;-NfgM5%7NWOM}1n3keLb#04#jH!rX60JE
zPYgbaL2j(qKG1rIN!Q!FzBPQ7RdjA$LPnD|m0emEnlb(*R-R#l<}!riI&Ol_W|H9L
zwqE~m`YG+bJtS8)!Os-SD{=e;MR5ObnJ{kLX&`r}PTmp@AB}NWK@CU!zNJ&49L#f?
z6YjXM=8TRRL7pI@w2_G3+R`WZ<0Tq~IL4w)<nCoUO#q+!{x1r+J;YAbjBLj2OB21!
z_8A-wr7Y4rtpL69%jZ^*AG%sD;#df4H1?W>yhaCVY|ZswLLqNq<3z23tSh)L+jK3H
z-(34t`3zifW611QZI?cqx;Hn*bZ6JT^;`X976R~DBpW7{uOT@JWn@I|nRf$N<7?E`
zAKvTRSxOUHmT)Qb{;6Fl^Fbceak<?LZ*t6%wA)!~loH-0-z|bdIfx1N({$fr8WqK5
z*TdY`c=2E1@Cf`7&H#4SfL3<{Kpv$(ptY+C)}nnvnOGb!j1CXfK8}7*RS_}IGLy}c
z*!)J6n1E1DeLf#`g3CsmN}XQlK7Nfm=}N`sw=YIICphT$P|;K0AAj$94TBL6Il8i+
zF9a<ABh%21WWPs1u%o@p;EszZX+bO+7M_Z!^T0sW8NWzIR()?<`0%t(*DXNx^0c4f
z^_vJp1*4Te+jSdk7w2}Cu%5@<0ZyAR16H`JIosk1P+}*0zgb>++0@98b5k5m3<u1m
zc9->{`?cO@f>X?$)xPOWiV<ML+zjG)>UoMVu=LJ^8(^&wip=@v()R?yRq@ytk>yG!
z9pT8E?}8Hmw6ccnE{?GbdwalxqFWI}l?yNrd2dp8=NGfS!ow^;ACvV}GU5?c8EnH6
zzAAejZ_jYVxj<KPCll{(f+S%;2e+3utS;@d1h@fD5+R-$=!U(QwV<V^={BybBs?kh
z_qw8~2WVpfOecmKSd|lhCicu=s1MOWO5Gz*&?Q9b_#c_VjcYfx*>^TY8yc8F+G8&6
z<INxeY;3ptJ~R6nuo=^1u2!JbMV!5HemXc!1X(_FD}OVl(-GJM$U;(|l6J<DF35E3
z3~-ZA2Y#!h-;tN^phD=b=FAl8s_qRadvH+WasnuUaV#khur|?@YEeM%x)MmT$XV8O
zplx94_xIP~i(H0Jaj{9B;90^>z4O%C4&=Sn&$5UUyl|!KG9X*ASpnA#%!k87h=3uK
znxFcn7}qGHlG~|y;L?`r_G5nHSXV@A-1KPEtjai-NIIXVcD`Xq69KNn*`Fzx>+hO6
zn@6{WPSDb16QPoeNd{T=aG=PR?-O3i<GOBd{38_Chu?%@>{JL$Z?bO`MVwG5u03jB
zkeh>xr2T@U#QmM!R7=m8y+j}`C8=_AO3WZvsWu!Kn$FeNW`ds5@5}f!3H4-RWAxY0
z(U@9No#!HPSL3QeguVwug6sL|AnoEHTxBkwRZ}^9*}xu5E`*}7=5tzR0&*=)zVm#U
zv@Ympwn7>n%`di|o-RIQQsaE8dXoZ&_EYK<w;p#sq8V@(L%kBs%D#`teYs3H)-dc@
zc(r{QCEAE>bKQ>JK)EiC9S`l17u)Gn3vJHkiwe99mZDxiJZJnoMtRleJJ?)f*|n6X
zu~rZm41d`bjWTf`pCp6IG7t)f#FD;{Ga5ar7`T7}0?Nd?^W-z%pw6Ky!CWDJvqo2_
z=evcyMnm4miMKrpj#><B6=&6s(ig_Q0C&N26nU(KB=ict2IhUFnu7-0xrr20To3df
zN`MB7HlQi|jsD%GyC7~TGLF~I*DnA7Wv4n!wd#pT(;HrC&--$cE7&(Ah}J?mj=wZh
zhzsd!dGB?YTR!WyGzYJwi4>CaLMrNlqrPdQ@E2Ks(h>L;#4iEEO^CQZKRMk_QrAH?
z{2LL3x!qNglT<*sTj1pTd}sMb1N#2u3c(2>sJqO>&lFZyaJ7dOI-l)#7+v1%h>{%s
zaEYR7pQrk#BpaTolAQ~XzBFu&i=@^aEz#NsZ)XL6o|S83yb^psFTwiB?2I5dxtuQc
z0cT6OVwLFr!9!^;b(;z3dG{EBa2<<yEY;q;Z>Osh=X+&0F!C!q{%vw#ci%dD>Nhcc
z2jow=X30gIY8p^;DwNqZrdFtwh(>c1LZH7r7H|R?5(ORY+)-9hQH!B<>X)vA7Vkbx
zWnomXY|qt^PhGMY>LuLX*d4`C)J;|w!YXz1=a-M79?T;9d}t2hBU?O0nLusyEtYO5
zv=B~~t!C=u`6`I~z#!UPN^9&9p6=dX)OhnVOTTU3uC#>G0L2o=uC0v)7mYavq}VW&
z$Yy}}hnpfxv?&(a<k|T(9|)J`eiO8w^rfw}P&z#_7N-GtZ^Fuq(gW)z6Q;)~L=>ce
z4=M5z$;j9=dO4}ey@~Ifg$X9S6j25o9Rc?^#gcJVCVL0P)UQcI28@!zN=CMP2Ufh6
z_d2}Vaev09-j>DuqefT{BT1OVKE?hLhSeALM9OU1pxU%ytZ$=+EzxXy?3Mx)Zj~^=
zRjQ1cjMUYnhpLt>zSY#HA>E8_PtL|LlO$$&O!{EFk(_EPlpA)e`Xro9S5VA^FvP-J
z5IGKap8w#gPz2q+&UeqSQljxWGE0B`VyI~^+-y$m5r%(9*iy+A>QjtvKlMl~E48)+
z({bqfyPp~ZEdd*zA&%c=6bGnJU4%C0yqw0Hz>BVD$@!#;o_bKpHE&n$34g8mnSelG
z0Oq!71RAxcn7CcqDYJ-di;+?7Ws`B<zvk1;U(Cl~P2=TTx*P0KM}ULC4xSqvfh^!l
z;u7R8G}b54-GnnfRQCkn8@yEMGM|J+N`G^cU;O$yikHsH{K3O(0kVBM6e%1H)Iqs*
z*xTg<tz;W({Ma#Z){rJg(_@oG>wjq3<3Cl~W&jWRc20}?<RO@hmXNIs&~^Et9ekrp
z^KUzlZ@cH6tHOv%1SEyJdY?oerXfU|NqG&z`I{j0><d-&pT|%uh}$)8ds{raFW-&N
zk1QMDf5<zMrQ`#1@^Ou%0;X(j7ts&N))b$$P1KkY?ukzgCPM6Lx>sC1v%N7x%J~~r
zRgPXvCWoOy-pZ@u1`6YnMUcOd1Qh%%Nc2v>lrPdM@+DEU`acW3ws;p@1<E<fa>vR(
z<K2;RTLxx1`r#6{tW~5#iFMTbVsxT~Df7mP&St_mS}l03s`Q`4cDNtWU)aK-Bz!A^
zh^@hDnFTUI+9cyK!vdbFt`_`hCeLJZ(hJ23wSqi<2^~(?K5>QTkhw+*wm=)AwuU~b
zg6;zH-WA=XOK`~!l}6UkSqa&*?_2=s>YlK)=jU7Ng?))k;<G`)?bT4)6OT>*ngKmk
z?J_(CQ={#TKpQ^1IC>tnVFLug2Hr5t&nxg>{LL~?;u?JXT176P?!KWcRz-Y#BAeSV
zlFoY9BT31u1|~TqtCfqh81J^?Q)<$Q?;jV~;8y^9cVbOCVc}Oh8*<@~n;7tk16i<#
z4b#5p1_k_%UD$TQBh1|ASl0F!Z(T)90C?9pwbCCN`=O%y2yVeDImT{SvtgxCxn(dz
zF}=KYCmE`pQi{juCbVm-*@iI<A6~%K(o+k$d59ux2LUPQ^CZ~AA50D0(lq0uQ2YVO
zrx-D>**1XMDZk15%7slXL<KQ_Ja7DK#5eCUDQ=LRDXE1YhU|<>v8a+!ny#``r%w}*
zTVB5gDHNxbYtQSP7}rROW&NNh$GKw^evTp>Fp92+wefo&B=S>A8L?&R#v_QOIin<g
zR#*+n)o?Uwb;g^BkDQ79*Rmu2F{r;P)vf}4fAmD-ssRL>7kW@H^8QP2xabAiEC+X7
zUbZegBd3i^ka1~4#OqMkBV$40TBB_WC%+8YAf}Wx4)lY-gPBP;5uE;Xv<Dp0-M-;9
zw9}(b%_QdS*NHw>Q4+j12l)o+abV_KP4%57QF4Nbc?0MX7Fv1~X-`3_l=MqK^tK(A
zEuWjxiVyC_m*SF?%f#`^EF=Kw;8Czfz)xjFN)OVWcti6n*V|h{^Ea?6_TtK&(d32T
z5!mKPbljRvK+GTsppfiaIbrnn^d<1ygUD2rqxP9-tI=9(1f79|Ma93<0rwbmFrU7v
zw}BU>$6YdGToo52AOj63j66T0E%K6kXEhoY2Lj?*HspM|0OYAUc?oA=ng{0&#tW3;
z>)|q+;n>}H?ue3&3($$W)7|+7v6}F{3b>R%{uW4kbe41VVKdC5W|7A(rl6ox)PTzU
zGxB6+b`Ae-nd|KG?EE~&(|3D2r<D?ux%1G3f)n_bF?5`uGB$ldw@k-s+KS5`zWDk4
z2$<T_y)amA>?|)+Ru%8{j<;(;hNg0Pv`H!Vg706`sjSpn^}@8*hiWt&E|YGg8$PsO
zE=MIiU10(Pn>6wSDYc3%u|ZdJa`@=hy9}UM(ZA7pSEulkM=4i8QUo^^LKYbst|ZFe
zb}Qrr)&_<K!W~9rhKMQlF_otCtRUd^XELN=uR>zZoV_N`ro(4kW!9HYTEaI8g$#d`
zPHXN+(k>@#rNrzaE_K>;W2RLtbr0IoYDXWT+mPC&h+IrDT?m@jluTL36h!V4u-^46
ztn@7StY25d5G%&B_-sX%mghey(smiZo-ccM^7CQ$Nj&v8E(i{dH=lVS0j5vTVL_B~
z4v4_*E6z~EFbp0S$z}g(XKEd$e)e<1fYFF*CMUMLcbSFUwEXBotnqN-)|+h?hW(%9
z@=gv%WY*|1+xUCT$;z)V9B~*eLo2P3y#v?DaVbFlPpe9f;t+Cc{rQfX_bC&}CZ3(m
zV1kW;Txg}MDZ%Ez1z>;`a01N|YkI_##qJ1c?2H``$qI`LX9=XbKHqM9d-nmLvt0I>
zjs<e|zRtP3f)>!6>?OoT{)s-dFPXQIaxLXwnp{UkM0L*z&$d!Onik=Ldw1y=ysD4g
zn-<@kldG{D&n#3gfW`}-HK3;!W?E{f2ikg!rxNWkGpQEBx12ic+{OYfJLOSXCUz7N
zhdf5Z{jhV|QduU#%d9`e%1zp&mwj*Vy33Wa!g{!X7T1+)uAu2$sNLy_7EeHp;h~Mq
zt*V#RI_;}HH7FQUwQq)>Kp=HE|845tE`m8GisRBr?4Zgf)k&tOp-)eU&LTy@D7$+Q
z#aMK|`|p|fUpsoR4FDDsJ?7is+Q-7j?(^f5qWH7nNSJRu19PUqU_C9iCb6=_N`h>6
zv{E3o`xRw$AiqW;w@4lGN0%fGzRv4V9~U-eu|NyO7m$m$Iw`CYt(!sAJMiiqOs=}e
zBAZ-MR+y!B?Lw)&+jBhh4){@N%o6+O<65L=afSwBT4yc>j3GW*!E#s$tl5XBKlIW!
zeoILSwiEUp*J@GpzcmO2%NvmQej{1ha9T;ZpQR;8w{nJ?PNrY`3pk+3>T%|82;Sk^
z+j_^Ma5$c8y-5C=4NN{V9z0nVA|CFNr{M5sT5{%2sioD?huI<<5-Vi%`5L}`NyfF;
zLe{*-fH<I3vL&&=hf#1fe&%%r143V`enZ&1lK?3m@_edyZKqJ-E;0!An49WAfe>K?
z;*hqUc;fc=!GF|-OijJ+G68Q>5>g;#dh^NEF3h)m!~dFWz@!+#>wC{jkqd8W@32KU
zD$8B*T<jZ{BZ*4Ag126i{-4=__rQP>ITLlWGi!ChJVpHkrC|L|UX7ce=592+n*w(G
zvsl@EN{86A^WL2xX)+X?`k*eNpc^VpY4n^LfEj8K<&JDuuCeRid@eKjjNZZOvIfas
z$y8VLP<^s+SV=~XAZpE>LW?BoDd@2IB?lHbMU?2x@?oCP5%Woh_ja1>ZNh(5=d%qV
zptQK8JvVQ<(0P@_zvt(3Mebe>hbGb)AEyHgICiqh!%@yxt_Oiz>C@Ei5Wz`mT@1W3
zw3Xk_LU9MVo(9ac*ZmUt5<M0rZz|Q)G|IEEnPh%fdB9=*ZP7caPF8L(4Y3=)7pMQn
z<DM!Dt80yJwZueRTYi*LRms6!lP;T+iIwvDnqcu%c-opV8IRo!;YA!x&b66}Qgy|j
zAOc;=Xj;O-+bs)J)n(VD7_WE<3tks`&}4ROMwjqDCWY4@mI)W~OaXn0U8~u(*mKh2
zYW{Y_WnQ}&+K^kwO0po_WPv9#-}1`OII{FWA^zG&_6e^kJLn)xrZMK~(3Wz)Se>0E
zwpO>MfROW1ZcVPz7MmQZ=Tj*Zc4G`VQF7jbY6Y)IpAlP?VN(uoganDTJx7lJRemUt
zwE4jT(eUC9IlIuppReB|DB~nKmZD42N5U}t?iCdP=Je+&=nU<YQ|frG`nzh+u~pvq
zvS33jx~%9Y$m-D8_8>F_z@5?WI&n}}BiKEfQ|GUvuX}OuZTuIseYk%9$dWGzk<dTm
zrA`Cw({_+~4BigFxDJyiH(>>u0UU!D#88fTCVA23D}bjVqEsRI@FZ@`$Ohn}>jYUg
z3qxQ5X>ff=<805saaFB5P^_@A8c}n`U_%HgVBxTt0}L%UuKQ1*LVztLoRT;m4E7%Y
zK;9|&zgf^}70@vHe^cGliRXo<y8v8t(C@Xvd1`q=9GB0bDo>Z;P9Zr8y9kX6s0TNC
zt4BNcvmK$PvF+^wymYsg8@`=GjfKhJxJY*^5H#wGoI_r%w7ec9rI{E*HBHCo$1X$x
z@eiYns-i2R=}G4=do1KA`<`?)LaF#(t<^||p)>ai9~o&}^mJ3D*%?h>i^w7L)UN|g
zAtaHEY`URYdIq;5;D25Fs;lpmlsH$hCPjM<{xmW>`M<I@glDLl0bA7B8Ji+7z_8#$
zBq#h<?ad{DwZl04OAE45$27;jpXODD@>*J-dVO9-?pA5}=(+bGC+$Nou`QmYYwq56
zkuW?}vEy@1gz1Y!-RQ<TE;|ljc-{`0303o^pX}r8#wis99DOa<0UK30=LdK@(?#dg
z6+Ov@PUp5&C|ctrYNO(cfUjPK-z_K!M!sRovss3?SzW^8TJUd!))<V5wRyN17F36R
zLdy;#OIXM=&G&V^LeTP^ss<Ne;u@>%+ek2;^I8EHP2aAxkhZk;=i_Y6du3QoBL&<A
z)0j=<dPT?fgbj^j-$^YkaG9-Xj0baA&M7gwKai<k^&SVR1q@Afbc0D6ja`)QIAIhX
z!00M1MhgSBm$7GQfeDyNn^SYC3aTo`3}#hQ_Q-TqvhJrg;utWj*u`bes6J2xJQdA+
z?$VxgdNhxCw_%4sno|#0i!C;?tPY&+a@wCnvJZ_m>L|RTF+Ve&xVyf<J%9zJ8Zc3X
z7q+xs=UwA`qqCLv9xoV=9|oVx6DfdH`@drs@_ADT)$2qoWdO8<Y8cEjKBCbwGmiHx
ze?;NTFy<Eln_5=xjr;W-x=ib$Hj6^SW3*@au7ZAC2N)FLaKs2oza5D1>P{?;C3_a_
zI>G;hlR<@rHe?mgEVVtmUTd=(`Kz`8)UT|9pf4hz%+P&V5|89i86}4J99-flxw#{S
z<@lz27j3|MtYpXsr#d`-;Z={VB6hcEy^PU)VOl$a$xs;N!8cQGba}@MKs^~vRG59B
zDLfngU<luV%1HT7`r82ivW_QLcvnPKbRihM?_95+s{~w3W(Kb-kAZYyPVb&aL}!FO
zx7SlOw(1tj0XtKi>knp1X5T|Lcjn!uF7*z!osBTJtRntUBHmUGkrnBGumHhz=)HU#
z%AS~KJm&Jn{It5!plUZMZ=bP^zi1XcXU#tZFKW>8@7A-53{p#G8rLA~VAtou)3`}x
zQ{%4G3on6u>jf&UKE*6nHqBi-_BeCsV`Fs<VAKpbP57+C?rN)<yQcH1xX+l>z+yin
zrsA4IAI!VW^0dZoGeOr+?MLRThwpw;{7^uCdeL)KRB>Tw!|2(U!+G;)j4>uSokRH$
zAi52apt_iBmGFK81UPnC2J$7$3OqyX;xNL2_<qJXNhy5!;~jb+aD*)nw}}PiOkP>I
z!Kg5$Aai>Cc2hd2@9I5_MItgBDrr6Ho|gPV-5q?W_8N`kzx*yY>i!C<^6T~JB>*`<
z#=n3!-n}efwTVy;`U4n4_<tMyouja34#J03i?oxy{7#?d@P$9PTLNU>=tO>&#cgpZ
z6wyC=iSdoq$*ZVY?<99j(w@qu!0#>{$0x+W5^u~yMgn_noppvdJ-FWOrinaaAy~T~
zl>&f%vJxtuq;2~@6JL`2%3AjQ53G>nQ}RIOw7pBQQwJLqoy8Q3XW3(ZbRaLT#%G?+
zI{#!8xBl)($IFAxVlw0_sMevF-juN*xS6s|>Qwf49a0P<r+=P-cSAmH&4V$}fJ3r}
zjVU}<$*AT9lVj<U#^&$5;0Hzo>q_Jo9EC8WltCRR+VX(cj5hZIKmpxk8^Q8%q1q@N
zao)>)o=jW2#BAhT;CFO}$b*7v8zKnQ`6<RHM)q=rW{14K4c7q=S_xTO`u+9ZF6H#m
zbg`OJ95|DsqnJi``RnN7;;jmv+N&xt>?^n5`$lQ(c!%Fiaj+VJM<g$9hfuW}+5Jzo
z37JNKAZ<-ZOmult$wP&b$c?nzlCifF>+}@j2hMqNLNgWG&qm%m62qn7;$|(Cs(2LX
z5WJ%=uL_MEqe+=~b$xwVe&TSOr^yUtpueM-b6uOV2Jvi(wumN24e-#?g%b|_Uh7kw
z{u0aXG!Qg_OS0N~eKyI~vKskdnc)DNLtq%^IL7ZxZz^xkFa$w1lBkQTfnqK8DSi`e
z)(J#y7Ao>4)^5y>Er>cU8nVd4>xqf7Z4pq^@Jab}^pUrilLWy8D`jW=irEC;3IBMh
zTU|LT&kA+eH<!}|L3pYNTb2H+$-MgnsaJ-_+n8r%_$0G_KtW_i;+fmfz_%C2o-ffA
zD>a>{0Ka_Eo2<!~LecJBkdxyjY4>#Cf(gKGg}>anJwG&yi`)bF1=(p<7Pp(RXdiMI
zJS(7OSITCK%yHJGaTrKN9Bp3q6F=_ywON!X|Kd;qDga?%T6VnnifXb)d5Wjt+syZ_
z2G7zG4Ew-sV2G`o4LF&|*GxC9e{gIkFZjw6$l_^FCDl9SjP^-W{8}$T)u%rq3}r&m
z<r$W2gpn!glieJi+&`9cW=%)+h=99H$2_j3?^?qjQ4Q{3op!orZus3_@L1%AEYLFA
z^6Y9S$^bKX-w52{%6s`oW!Af6R#@Ox;X)SOeaPvaJo-j6V9g)n{J<iLZ&@DdQ3ZA~
z9UjfI{^5W9RFx8cfE!MuCiYPRh@L9Q$0ONskUM7OW?`cXgx~c2-80L&tw@q+Adp4|
zO)E5hN!j<J1)TXUY1<&qX<yLx0ns1LV8`mfm{U<OqSGme00~Vk02em2$~MRKw6kiS
zoWGBk&Tw)?<0ZT)T-PC<Yf!7$nPz9hi)O7l>b~zJrRLZWWi{MsrwDzls7oUsj;-5@
zJ&qT)unRtsEVzRQb~dNvp~mvVoWO?8E;XI4iY|3()^VPLw4pxTHG7DE;qp-biLo}v
z@0vuVvpQzgDfJ!*JJ;kfZWsvs{yr((lkAMmw?vUD>+QvWN=_sl926$h8m~w<ssD)<
z^P?_Eihu?1ohdCXgA7#$)@K_66$~SKpK(p!1fZYn!Dpt2&|QGK`(fpGJ(QPzBf1+c
z5iNN;@NGI!Cz?G9HHdV2r083higuI3c*J*fzZa1sd_vBR_agMThm^cEm)NKg^6`nb
zw7<X7G~?0qZ?pxtZb`A7(4b#d5wdI`YucouCsaW&CO!InYa6W?WCMLaPE>-MJ4Mi{
zEN;+*;hSUJHdW40{S3Kd#Tz-T!ac9-Gx3p$ViQJjwtN5M)kcb0GQARO1vP{%Qe@{P
zAOWBb;&p2lt^tpqU+hVF_b77|;!$kXY*;uBQ6QU?|E$fR_nEB|ArK=D^OIg!T&SU`
z%+qPcM*r`LI?~08hOzE)77{s0`5NXKUutVGNE#h<W_?R_iY?O~CjL)g2U&H)u@v%0
zcjYh=E7eQ5$b&=a;Agk(Xgc?phC6pqQNu8+(CI84lp$ce%NKOI<y<q8y+Z#pQSZQ>
zMBlzQOmdZmBk)2Hw`^QS(nEaHy_1>RET`U<A)!!KCqE6cJ-I=Oteo?z=LdL<y+d9v
z5@k}#1)91*7#mWAk9!|BE$+Rd0r)xF(h)voa{F$6ePV;~{wiO}{gV#u{GJ*iQ13s0
z9?6Th{sL&_#5|bMwNw@t96|C&m98rZEf)TE-8PyR<aM{>hI(*!O#>_+?pnB(*erS;
zJZTtm@I@Rxr!G~ok>ZUGTH)nwYQ{KX38@NFK<v=glQN&3i9%;N9*orCRdTa7OrU3?
z;l&Blw9rsm+lrJb>pDha8IEWgZtEuc@si)$bMf!@`{*}10KH<fCfLn%P~5k2-A~Rn
zG+-3uveO=G6wUx$e2^`c)5#g+Yfic%ajAtuAGF4_9=7x~V^8-a;#zWDi3Y*u*viu!
zES36_Rh;~J$eM(iAUTWUCdS~N)x|kBW*_DwaM6<L9M!EuLPg>0$FQhMZ`&@ki?5IB
zjXfSHX{+?eSeN&NMS+57c;Pxz*YF94%+yieq>H;fnh!Sra-$_&15pBZ4M_u=9Z64o
z@taw+#U8Z%IPl90Pgm1Wf7kx+*VIOlHgMKNm6>|+iyTmIqfvGo_1UXl4JOEPBilIe
zxwol6P2Tfs4nwpB1w<85UYzG8<G5W4&=p6%wM)>XAwNmbX?%8Ka9YXg;9!dSIYQUG
zMtsGY)}}$m#+1sFMu!ItxuaRCl19E$9P(?zk+Y^-r^1gMJNA(tRv$Ie`9Onp&i0OG
zOIu|3MbeE8;prJWxdDE2M}JkbW#aWe$9_Ssx=*ltxO^ZZxCLLkYt!u>4Mafn-PX@;
z8bS2#xAI+A2-3zz+nuA-fM#nc5n;85Ha~5MqzKVdKjR)O1L$uy$FYKw90_)??Roc$
zFthd0nKjbEiip6v0W(8-%vN%#NODf%D-#&2+c`U94f?CNuRFN=hUACv@GbrEDSaMy
zfa^3O0znrEgUZOs(vV*}ARHKeCBw%Pt-M&viS`?C#a|iX5f*9)dZ-PBT(?g1WJKc>
zuXhOtV&KNdR*S()eT0Yi>@_H0@zJ9>VEk8dWmkSvs+lGP-NOIT^~$_>=Z6}x%{X>$
zpxv^vxDTJpD6;^kZ&g?T@Yz~KEh5?~5_u=Dc60Ov;$`q(qXywNrB$k+(EVy^%Ha(`
zz}Wq=co5^{pG0`<q7w&LTkMc%g=cOLbjpX+D_=NHqAxwGMX7k*IFWh-k_^iLg#qU*
zz!_%WE;QWC_&ET>Y80IAvx@?p7-awd;f-3^v#;8WMmAo+gt|CNhJz&Ki4|^JI3Vy_
zE-h^79H33Ey!z$bXk_*z&prIheIoR`{&xa`>X?^Ca}Qt*dLbzL@fw7S*bizSq}g`n
zS9xx-E>I;t;ssB$)UmJsHYr6l!QgnsNI{ZcX|zu_=h4ur>IMVYCX+1vY2N)2bwBv$
zDe(iGVF#B_{eYpG<y@jhoVc!eadgF_AuuS6B$#Gfdjq0p;iY324K^jQo=h+!_mCKp
zARPS?S2ebk3gejux8I+Fy^<z1Tm2{qZremi%+`rx5Ze-94aAMHPHt>_#B9f)kn<Vg
ze6zP+9O{zYM}pKV@H5S%xspydaYOAe?M>^d{5;LL0Vzs3KKW6L#W-dC97`Gy<kiib
zwwE>z({b<3ag;g$3u9{o)FxA2?<dbg2u`})oCkyx_JY{C<-s7l&Q_bTb%Y=DsF*L6
z7)w$I+5;kl@7yN_*mn>d$k`UzWB1RKT`lW%_zHiU%8-;1+Ue7W<>ZPKq*#~OLLI#T
zzqLRFRXg*~;mi;{7^mA!-+&GUAjEKz?yXjk75)<oJx>5o6o{iy-A7d{oL-yLuW1BO
zcR?1(p%~~l9Aq>9V3~@=M_!t6Zw7}c3B^vUH&3Yz1>u<AYGb|b*mqG_T<s2w<}NkT
z;whEJMD0OvGI$~w8`1Z78GB50t=~N>D8i#M=T6mam<c?eJK5f+kp=QlDJ%k&Z{`%&
zDrhTel%0;rbB&Qw`C2VSrHQXAWt?D8K0!|Y8RP!IW)C%<dw%&AXaRDfg~bT*W3B>Q
zmg{X(Sp>$M_gl9&tODs;^WWOm$icUcuus_dDE4O=(NA7J@(=wXe<qtkwj#Q;`eZ+r
zA&f{7>Ykv}&b}@T^*&@O-oIL+*-pS0t}5ZDTho$;GXaCfZnNd_Nz=&lhMw(ER?U^X
zJ#?GUkb&Nd-wpZb0Y!?l!V|bR13{tJbi>o$Y2GIlvN6%0Pe&LMwJ*cHC=<lC;|tQ7
z#7U`pvXrKq+yE8;&o90+lVs#biCd0oZiM^cuVX%95Q7jZ-9-Ukkfy@=1%o?pmtF`W
zH9lpF?qU%AGMdF3Tqy${7nMnLHfWHxSHFMx*Q7yT!jHhh+RgivR8Ueu#ms|g`FMra
z#qb<hxXmGde~@yAh*Bq_?f2W+=(Z7{Nt+Kp)tu$IGxnn1{3u%+Cv~oW!V!Ja2S(Uw
z%2Su>;nROB&ViWw4ZmiDFYTZc@1OWoS>c07gSYsfUvaE=CpmjqKxT03>3f@ZAAd@j
z+qj+}p*LmU#WE_`r^lFOVZ>Oj68qmhO_WJRwy?i#i8Z!`@sT<StX5FW6pwJ{|A**f
zLiSU<@Qg<Tm0+{P+bE|0dphD6b1jn^>~*`&)&u<}Zgh>?sUBvfh&jjI4E#|&lbtQY
zsUwJB^=-WiFiK^wwslnR+&m}uB1RHuKXlrkDv~4;V>!~MJ}{ueI>e=-$FQ(Xr^W-3
zp(y@{Q012DXmja}1C1Q6QF^^HVeJzMtOF)9vS13WkbWF|pXCJhky8aGJc&1y0h^G!
zZBpZGu7ty-A+{n`3)>QS`ChpB+U#===dr71O@4F>?q~ll$-Hpx+ASGdvBpYz<;fh<
z-qej(3XC3Y*E#F2O#><2dv~{x+;K#gCUXukv@Qg?1qS&I#Al+AmM@AZ2-#zJcZRCy
zyCmZ9%3mswnyqbAPfCPU%*TJ<YGqVun;vzI8xa}@v1QsANiNn+q`DhQuz-*|4PTY0
z-4={6CJ=47f2vgh2@Ua%N8uKWOexfvL75DGKBv{oKv4gom$)0AK7a#8-7Wp0DKC1D
z^h!P%gZ5Y)hRtlx0W~sHNGgZuVk5cvBmXq$8MqCR&83(&gVOBA#)G2%hCv$I0MIvv
zWr`=A9cFF56416)?R32X>|irz?CVEbc5(ew3M8B?;{J9bi=S+!iTP(}Z9I0ZA`v(j
z%g}c{oVB30&T@Tv=u8CE#syYB|3Kdwzv^<E1g&f(ZKQfe5Q*x4((y>N{_ZR71_^c&
znL7w(qdk9G<5G|cuh_UIk!0M`!cyX^tVO%)i1uTsrn`mTvjet6K>4>`t=!v-YMhEm
z9`p&}wuz~0HH&*nb%P5YFIWXVIB$Z^Vt@u^@Qd^4WG*|&rQ)ieL>?qK96?N^*UimM
z4S0$PFtVr0bUOyj?zG~f@ia22f`OhOn}5ofe#8hhD?ny<Onr>ft=A2Uo7<b9Y@>^=
zz<)f3N7*(|^F(8Y+k#QBB;(>bGj!@iK5R@Im=ZD&r$xXa30pbq7xQ*Hoj;c6W+JVv
zKVyU?sH^vt8?4xpL*VQf1`>6@15kq0UKr$#I>7lQvW5M_)9gcXhkRa=eQ4hq&7%#-
z2XNanD}jN+ZXdDa?S8O^XUslaEK7vuQ}Le%6j~==OO8r}!;;6<o_Nz?AGH>GaZAq+
zUUwRKim;!a?ZIup_0j{z$`b(@Hs?T8urD`yg){NqCX!<IcqJoQXi)!^b<P6!N|x|N
z!YOHjKqB+<WoUz-CRg2m3IXB5y6ukLb!a1_pgK@}o>}3k`u=aP{^VH)FTndiI}q*!
zt0d)euUu>OLf!Oi1u>V1&EQq!O89yNb%}=-u24oI4L6P!A=AZscyZ<l%Wo&j#EB6w
zz2bWcs%l*U*uUw6ID`gGa&P_Q=H)vpOw(47BQy}(bOkYo*H0rohszm(m8t~G&f;p8
zE?8@Inc#}jGzf5B{#LC~iaz*_m1~EpCswSu9IvMlCc1|4c*BgAsb7wl1swDqmVc_x
zu|zCL<}kt#8(FMI;{-_3>BHOH3P?FDg)$04e(S5|+=x7B6aF`M34ZZm?uW7r;f?-c
zBDIr(5&)%0?^b@tZi4dvtj@e%E^l}F6TCATq6pOo_3zLx#88}<t-zq6SSKx}dYdNa
z;7Uj>{(_uF@*g(mX;Q_AQ)EB86Xs1zx2gdy0h&;$Tc@a52|5kv4vH&=^`W&Xu9c^o
zmf;Q{cFVCv^w<py3tt!pgG_Vtw&P917tJ9gD-w*#aR@PkvLgu$6RL<ysNTf0x5`Nl
zUsp9cL~2$^DK(sAU?E(4bl}`jpitegItOj+UlT8%!TFcEtw*;(%n)Q4Tg(FB0<a?X
zVt_B2!e-;;^aO!+tafR^+5}80Nx583P`!u2TTT2V1iv~qMMul=dm}_fn~9*HECy>i
z;_LLAeUqSs2AdVYq5{dmrg{ycuS>z{lp?`JN;pNR40WogW`8nJrJlRa_7F5J-VR;b
zvk-^CBo3{_Paf^A!!v<B53xzFh~iS51orV0708qxW%j7j?_FiIf~v#vPB35!N;D^l
z+(Hz}J4TxG|K<wwg`o)05^mz4-nhv8xIkYY>e=yIz&>y=o83ybtmRO|EB&8O!`&EL
zOGpOpD@8E9E=Jv_<Lh_JJ?6fGy*?qsmOsY?SkED!p{4`6Cc_O!atR6W?V-CHR_m@I
zDeu3_7CE6i6d4m(5nWP5dMagx_nW|GL8LVNa0Ml-k43Fhq$5!i0D&bfydv>Hog;Ee
za=C<r8MN>kiRBSA+8-4;QQINH%`rQ}{iOkcvLN7XYX3UZdg9I@zwONU+w#X#d%R=I
z90LtWojYzq_>W6o6TBF#fGVr=gOJ>vj$htva@~J3tHeno;ZA#Vr7KRT_M2=d<+<Lq
zH*L&;qDPk`ebfjG^aWA(aVpdu_+yr;^1R9m>eUsU%dmeTp^y=q#fq_?Rgv{eo5)HM
z^2hi6DXWYKzfD86bc^=74}DpP=rLo)lGa#+#4~vNs#jT8w8QlM%T$H)ra|0F7@l3r
zM^ngAZTIl;byt-J<si3Duu{DOvPsS3s4lhHKXGs9jib9FXO&wi*%pu5%QgP_Y23J?
z(vL3rXodD41dod#*%59N5$iSXDbuNtS7%dyd{b3{^cK|uts|P@U<B8^BEMkbLXC~S
z4O6Xc@4<^%OwgppCh}+XNE!+Nip_xL7(Uj<i$<~P!?YgJae*boqlO!Gwaq4yf_7=g
z6$es^Ct*-3WRr|&s_BUnfb<&dBQCUWQ=c}$>a-&c-2U+-Cn+t4zueax$FBFd1=by%
zEb;!FN7~zFAdAIGLu$hyG(Dbb>jcx?5;<dLNSJaK3OJxxRm@PE7*8bi7HTHi*kRiK
z_&w&(`JOcy9t&5@t2s1xPi1<<^zfdTmv$>z?@msK+=_q4SU}r2bc_y5&XV3hf*eHe
z&2K$iR&&Q&m-O7xCUf}yo5^W6?{j&bo>kHqDIA;hMjNuq&`-?qHOpe^mZILlwQlHX
z0$)A>um45}5F^jHa~n$RF;7T4NrQkQc`^s|Nt^b_{?rK|b#dqg&4W(Y0n-3!0;yM*
zNd-ga_0b%bH@ZcO-EwkADa@os40^ABx%uCv*6KHcbvcG&L{iFh0<%iThHT525|aNo
z0?Y)*FI9f?dE7pSL;|TE^Kfbob03ne^bdHotwZ)h4Yz8FHP9LVtWP0FL+am9L@g{_
z(aMX=&FqViSL@^NgjuJPR1`xZym(ZpWjo}VB^nxd!i@03!8^w%*j+qi(kIye%~4|-
zBjjN0Dlq*UCkTee<tx!9|LA$seqoG+3B1%YYuq-DPdQL7JpNGv7_yZ<mo%z$*ujy7
zH6{!lP_GT=vUiYY3Q;{G+UJh9MY#Lm-S{MU=i=a{z=YLftq(Y2oeuippu^By!t_9f
z9aU9}jSN3yx#N0qoL~zFGd~zWJ3|6#=-drc(9P%w_Qk5n=T$l~N5D>s)z?*aZ<+)8
z_ropj2_z>e;H>JLXyM$47Um8>Gj6B7uWX5Z`0*tC-A~vnc4e(92-w}$(lD2%Zwf9g
ziM;%XmZZ}yAmiZsRTSq@yIPk$n`@=6T=?0^rkUH99D`o1Ja&7a(xF}auJ1>DJ`_o&
z7n@U423a^CfN$VQN*e;rDXJ^9!___U_auKxLdpmZbIHGugT>gl$>R(wclM|);#Ku5
zow<TiYMOQhEfe2JqU-aI>-}#&NrLIo#hgBu4Mdl2mEMbz>#)qWw+%IJF-KlX`=uC<
zyN;9WlLFkPAk1dkkF@_zBd<u`HJP6rU0jKCX@V=Rsa=3OIYW0U3>)I&w#XGTP`;&u
zcQ?CXua+R06lV-`xkJ^cKcw$M4ylB)ed1PUIbU{^-p}m5QysjE=2tjII<jf8YuaLJ
zW!b{~&tQ1ClIAp=KEZFD?|vKL>lzI7DLnu10zU+Soj&=yJJC47ViuxU<;(Y1D-GN#
zI;evPM8F#HnVDm4UkPP|F^N5dfrJ<QNFPNwv?mGcpHD};Uw!7m_fe^49pM148Urqq
z{C8q%-h1^#)_t^?pI&?e8lNfj{J9b%i7H;S7vRenJU?FVh=NAoUblfOCW=}4T_i-t
z32vq<Jcdi-xNw3gl~#Y==vC<59o-dD?94|{{DswN6pQ_S{UJP|;l$Wz*~G5oL9Cfd
zS%_{hLzoBWb5Vx|j7dk7#yjK4aR74B0M{POX9o=oZFRnR5xElkniAGZkO{Lj{`1;W
znA6GdqXLv*l=LR<1VIV*sKii{$wA(2AZIixsZM3*#~Q)$+uUa1IdxqWRT7Edao~{M
zj*-Rgx51}JtlJnnQ?xr>w8MiZZ*YwIa-iWtP#U}wC5D~$_S=#T1Y3B&&%EJ#!=l)+
z{N(Lcy?53;6JlPKu&TJXxYO?JOQ-vF%T_p7UFYNd+M9Z8Yzw3B3yYx1Nw$0WyKnp^
zWqR1Q-U7xvGj7RasC%|{NR;*rS8K%U@MU<C-#9)_aFy>a_Ak)Zs?)oxzVH@ANlZWO
zdTC93sb7R?L(<fuP?r+fc7Y(?s^IgHu(8UsDJ2X;bK8P1d4)kH29OQ(gx%$SQf5RD
z*QA!xuqUB-wWHOJrEi?{@9yP0q3uY2BP_c+@#@QhSJcyET7U+uR&{18UIChS$otgs
z)!yvjZh&EUzM$K&=F4U>FrbgCnPj@b%jLmkU(wnq+M|w%=jhpiQ;cU;Y=d}V`soqo
zkfG6wCQ+!8Jk`napBd(PQ}Z4A`WbA|57LhEdu!&iID{+p?=czE<9rYK`5eiXv-ZD$
zH_0(@ddw-|8PZu?ls+T17GCnsKdE-^5T6ON$`v_H)uW#4{uE&Jf4s1Y=Sec8-_{+N
z#90?Y>`)dGyst&uy(EqR%VT6ykIk|~Gv52u(evd~rV_+kE6j2d&kslaQfkQ@edb<2
z*bvVd-v2Y&V5v#AO+X7(AI2#Uuz6LPd$bzmfDi>I+%w*T<onEsS`oB%aNLHlK_=<`
zoLY0)Q!nvG5HT9gQM~=cm%7~TO#d)UFX3Q^u<}6XlT5s&Pgl|`{1nv-XLX`6myrUi
zj>bocHvF=7y;J&vG>UnG(kDLcu`K3N!9C0JlnAGsi|3Y+e}XOcD?_f4t(_t0UYit&
zVotFHKp5!e{)^ZYaLIkuw$LFuWjBfVo>5Q(pE|P9fI97hP<VF%n@0^QHgU^U-Ekom
zb^LBapt11puteZ~B*>yO<cHH0GC!0@m6b0+g+<y~TC#~RO2pE}7pWCsjYB&atebgM
z8Y9uf@UifQDxv+M@E+KJ@t8EX<r%M4rjcN5p#&bz+!ynj>_zivR~$Tl@SJuQxfx;x
zGw~Dc$6xIvDHl83^SW#uu<uvj5s+d3-?I-y8{}52sneraj(lJGClzm7)1wpsvtx|x
zT%jmQuhL!3hVvCj^B8iojiLf2G3aP_<2gz=R`$C_9@1j)m<$chU^yJNtnv~4ndY-e
zRT1+<&?}?_u|c)X+Y5ts0cYC}e#S{xLKi44c4`->OSfg>&uhRN+Jx7}`G96I<m)ZA
zYnEk*HkK|jE<HQ;4qk9MR@7MHjkm9Y@kS@QTe%n6Ksmz#!RxfSk=i%@Aa)+i6x*?8
zfzgXUQ%ZFOI}T)Ld2UZ|W0@bCav36=VTvWP9hpr2>-DXDGyq^U7xIkjI!*-lbl%^1
zsI#0H4zBi(*<V@2HIocmI1WGVRp-XQji}|+zd>&l#Mqtj6PN3m?Kz7XF@W-|K71Yd
zKPuypcn?mrKlE6A0a7;1-SJ7HBax_l73!q(&&db&hlc}&E)TJvTMqoC>*l0HxGWt4
zS}nt>L>)pZ4?w1LENiyB=V9HZr{zc_4vKmN_krDIpu~{84;fE$L`MfIa_|OGZ`<ze
zt86P^q3kCqQIKgn|2vhAY24m`D$^j+gX%>}qZ0b;({j(8Q)s@sO@VY&)47H;KJ@t)
zbUHHgz4bh;7*`3~oziMbCs)I6vc<fZU^nb>?hAn1Cg#v)Qm*KzIoy9{BJEU0v3{dx
zHxT-+0Y3h#v9}zBoNhphrVC4D10-bAzj*fcaD+ui)V_f9C$#~-x^NtJk;>uL=y;9u
z2h_QDs?=UE1HbrZC47C`1V3V)0#0W!_Y&po=)zrNO-y*O2&GLHypLCWue(B4wB<a8
z&$Q;n$L`7t^G(PkdeG(nY?&Yy+C-0*H9HD^?R%l=?O-*^mlLT+;!dQn?V^r@iU?jA
z?k^aXYJAo(D+r&$E)IWJ8W_iO30E)Y4xC+qI5FZpgG5-4(BnRMn^eqs?QLa$T;)Jf
zSWlwPRHn29$AJB$Cv(9wPX8(F08{2E(SKAQd^-(x^kr|hPkSb1@g|i_>;>A1<JruN
z3<dFDcdsX-F3GHx8QyPFc|7!AqN<{`f7j2?Ec=HE)Td?0&&bg?hd1x{O4sT@*pG8r
z<+*TrnGc&ko!(M^x$oP_vr-G#t+^h_eU|?Yf}_Xzeg-x7lDTajjE~z(axi18<OLh7
z5WJ$p6PiT&@-xHf8U>IMH;$$^4g#lNmxl$4o9BCrY?5-4xuqn2k|7Rp-qg>5Kc*OB
z{W1$w4-p5>{MGTZn>&&=bG7yjQ=avjJV(Cg>tR7YMM;n6i`~O(bFl*AKREWwU{Js;
zr?OPREbDi*HRD*r#Z|}_VreoiX1i;*>Wey5^-SCx7EqOZ5xVL+OGO_*|Ha7)qqn(i
zdC?H~#4!4+?^r2=DrJ5}chNqxDyw{b7^~!+5490(l}@|I8n|fSr3RZp&l{!^0ib{b
zz>5E%jR`mZI<jTD_6;>A#fva5^E=&?;ht%}JvBa)(N6Y#3E)d_l=fHF#DUFP>sFw3
zDv_?wcN{s5#a=YtIX&6(iL!KFl?13CG!eH9J7plL(vefDzSTAI{<w03gycM+8TR1X
z<9*h)>(BAo5Q)7RrIW7$CdtD2zR#g2el#9(Mku*qvit4hFzZ{lb&L<R`;V5pI}>h>
zBC1{phAp)IdaI#Xnx~_dBs6IygrA<o(j{omEcM~RtdKh)tDbY1r)XmXY*4ZKGM0U7
zJCYY&Qwum1>;oQ$>o&;_U>*M!_>cJe_+?r-lXUx`X505~szD;^MYPj{!ol_Pjs&eX
z)Y1alC{O2v5uDl|5)*pDTw(g^K29=6*!w^%@|Z@uky?Xsx{?PIbE@gq#)-q3f~eSi
ztTF{S48-GfZ0C^Ce!Q9a6%W^ui3*17@Uc(l0q%(Ykz7A3*Ij!Z;p-LKFWt1C!R%Nw
z$Gc$9*%M)}bX$|X4Tr-kJ4zW9qo_AX*+|kX=ups<*xp1qcM8Oa9K8(sf=f2akzFl#
z_LUhFqcLEBG;s}gAGqJ!UsK<uiVKV8qW~T+%s&adl2rYy{xUgX#&IA<)sOnfX6ex?
zi3TOII!~)k$XmAV{Da4^Y)fnufBXg=J+xVMjQ?G_L1u{kAlo&6nghmc0J)h|&kl|D
z#@#`PaKS1N2Fkt#A1ZA}9toqlP-X|co(mXu@dq$&bP`f1Q`7myuKqS*Lp-+V+oS`K
zPw~R?yqCjXYLS9Q<05*7GUZW;FqOMN+#EQk)i>bPxqf@UU)k{F$-sgW6#H+L!s>;j
z=W<Kjz`;wMovT_^+0Ver+?*9XB_MH?{T+tQ?vix8Fd^KVb~l7oYH`!2pmn56Y`OK(
zw*>1<ngA1+B&<<XB<uas?mM(06Z?)r?5z=!j6u*Z6-UO+HDv3#H)kH?gz0KIA>zO*
z+5iZ|eGW$aU#JxQh{0DTE<M8alSJg+Zu}-jwzYCJ@AHAZ59O<JoxgN3F_!O<5_ob=
zm+WI}TRL~%ehFt<c?`%nF59YQmFdMQulk6Zh8)nK=8w)!-8shS;QTHf3)NYc-n!Mb
zEDinA-+V>~^-<}q*aX_0p6JdHEp@@fm2ahIH~L36wOFu#7%<ehLW-O|Dd%W_Zau70
zn0JEQIc8uq;3uJU%LlNX#u6Ov_i7J3fFbeCiuFf2rT8pG<t0XTdG~L?p^MT|0+}5y
zFECVQl4?RjG)IvKjjlii#}>OUfGuhzUXT20(a4pL`lyAIpO}tQ;kdJeh=oots6iW3
z^SwxS@Fpff7e~>lBWTzt?nhQ|cU$+9c{?1+8uIB6WEpD`XB`YB=3O56o+vVLC5A6T
zx^LB~)c&oJt4#5{z#rEks*=Npc8NANhjx3PE7KCtFvM#$-Rc#GV!23yU_n)wB37uO
ze;po=QA3H$L9||f!7j>xBVRAsmka$IDmg+ST80)$4Kk!0)_`AQaB_V#Q&0Ghhny%E
z4wt#kT*ITRUS?h)Y>+mVdZ0!umBNtw0Mx15MyQ?oQ=N4DbR|M&L3u5bCa3hp8D?^o
z|C&j39Vjx5ItS!>6Jzc`V=h{@hH6JF#xd&euuqXfUc9{Lf!v{2794Ib1C@iRanY|)
zk*J~u2|ZS`z{shk;aY+tGM|+gfQ&(}Ut@Ou7&?_s?q6U7-hApgMQCWC!LXJ8rlOl<
zifS5;7U%C9k20clDz$<wL`g~nBQr%0kW}J2TZAG1vT_m92A&TmN@vGs=84)|6>k(-
z`tvitL@a<Mpcr!AMlPzqsYc=x{G2F>lbV6S^QU@L<dE<QrND`oI@It)o(D-Yb+J0R
zjJaLCM;@c|iJ`XV4Qg?uXW=%lE=>q!Tlck-l(Jzlb$wY1-_>;_z%1U!1@BM9)gkqa
zY^%m9lDaBQW$i5OS60@Gx;Q$naAYvWN9~>y24Q~D3JR%M^A<lrt51JMm!g<A;Fac#
zhaxQpPEV1|$sI?AWv{nzjeJEnJvTwZjf_r>WqXC2(^u~@&uufrH(^Pb=tSx?f(JN^
z%HEt+$U{drVWJ~B-|G}kV<&m1dl)sk60Wjo%EFE(t&7+=Uo4a}lc?8%<zXHwy8I@<
zp1+5!KEcP1LebqNH%3q$C8K{XGgx_l07btB>V(fKmPkKwJi^42TLM(fVQ*Aidx*p8
zNZ>>RFAzK{Pgmm9RqUkL>SEsZ`|ApM&Vmr|*g?@SDc+Q}y;h-|g8_nO+~rZQv*<Bw
zl$(=eTrA;#pH`cD6*OaZOyLiCn;3>Ck!8}f)wmqQf`LFC7>A1rZ!0xHDTU&W7EZNt
zCd((q9N@j{8fuS88I=Eh&<Gc-!;4Vog4nuTOj!P_D&~7Wcc4}zc-9yWLr*ox{tg!8
zKtLWK+N+0p*oOiBy)DzL<_W@!<J;XOs>Lai<M^TNWt!>G<j)w-tgAnAW45ICFvi)9
z^^(B<*WD@MI^e<u2fDqn+2wNo>7{GdEVtQriHs=qf-{ycEYOS3_#sn5u(T?V4g|iW
z^vv{&$?yY^IAY3Hit87#C}N%wS*tH%luh@F<Z)_~p8ePHc#M|9^~9_HbS#C&1ZXte
z$x{C=DMq5u^0`Ka;!-qgff#))YZr_PH2v3+#5daSbTPAY`UpUU->&_3m->FmTM1pG
zichL<mY?g6^M(i7qrUbLOu94MLe|{LO9kZM(=$tGL@g2Br3N8cp_2*ychQb(2(zpH
z#i=mtv$ykpfDV{8b@%p+AO>k@3K=KV_G;^H>S0I(=$17NXz;|i19H3|7hnF<j%o~k
zDn_Y|etFqnxlVwYln^~{m6v4qkVVa1L*L=}acLTZ_jq#>VHaMouzwJ66?MF-N;3s_
zdkgtd8u_cfE8lT72VyQKT9B}dwW6;-y*-al0FSJT8MUeEisNU5@Pvl(7M9+M;bY)`
zB3uCUKROv;nLCjIo`qB|1hL7(aFt;{LQrtwLNIjuOrr7t&`3^{bD@35L>A1j&thbC
zf7W)fLork21K>*ARb7;%D|6D2#ksA=DARI~!V*^3|LW0UI@^wB)pPuH>{)8E2)x$?
z{P)4g5DT1Pl5*(rclYx*U!J2zMvTKcrUV2OE+oBlDq>*KC*F#MSf81nZX{A_?=5tL
zm!q28I#wHA?RLfgLe5PQsb@)5yCf-?7591*_=W9r*&cv+u@Q(T!C@F(^y_D}t(H*`
zUDnu+A8xp_&Mpus`#tDB_ah^k<W68lvIx`9f94`zbE)J?7aLhjtcaK}h5-f)qEu8~
zWTV;^?0*}VgUiTXOu@Pag+<(d<nk-#Mey!0{Rm&orDPM|R9<gWv5p)%kqF@c41$Sc
z@^050QkU{fyNFxnO<v^QPmA5FKVXlg1*EA2e=y#`f)Iea+s;<XL_>6QBkL?qSaU11
znK0-yxuEqt)M3-f3nlB*kSR|~rO;@CF^iBNYpBYv{n;t>K@wPBe7vm8C~IyE+A8eF
zz_=q%z?y59PiH1AST=~$S^bh?UmX?DS#uc2tMlk{UNF`U?yw=MPP(B!=TQkBcS;&m
z>?>sb%zOVb-FBPKj)0ka7_4%xB(E<2sYFUV)CBoeIs7m89oiiw{$$ge=+76z>=Y~H
zo7mtis7-trKr)ww?-qS83RmD1jIr0@j84wq)3|BYl+L~amv)Biu_mWH)cIBoV;Q`^
zTk?lKBLv^=@y8j1-qGoo>b@)Ek_?lz01DJa>FGU_ucl+znBVGxmH2uxhi>X2bhyn$
z+_zBUe7VWd4KQZ-UZvbo%UxB-Y8WTnYs>=iswG>5VIqC~Yrz<z@}Gs5@o*nx^IjvN
z6SNvKK9xXfxMbL}G9y$us|G4XEN(@hL=BIy^G{vO-r$OvD9&H9E{({sdehz%i3V-d
zTrWKq&Z;YjA8}Y!8oeCz%T1k0Rk!a)IbFD%gCwXBdzip{MYhvY$JknqJ9{$J@8vdl
zhhW4b-6CMyT^$rkHQ_;Pn38qCHE0|3P>S^fWCi_lLm1W{yUJFm2x_6jWwhtQrXmZv
zUmJhAY=l25MYD_;<48@7jpQyaEG=mfl$YY@K-~ZsBdA5(TSQN;@LWU1{C6F|r9~&n
z6tX}#T?NgS`TE?2f^?H?0HY<g9!NMG#qVK&lcVDHLUd4HJCd~Ld$*k`ByF@Qgr9ON
z0&!|=B|gmidU?HBhg{svJ&nYdbDqZ`|8)syUdn7fc(%a&_{|FXc00eL1?}%!1pLLR
ztXYT?t@Hi^W|+gnTFRr^p~=Mt$4V~dTx*`ThGv?rDAD-9^>1Z|y|lP9e7_%M2ef+w
z46-1f=bOepUfr_u5#PR9iDRc4FA|U0?ceLpe{;O8ChG|KJ^Wbo8~m(`$kbqi4k@d|
zfrewj{z2Pes&H}sper*6(P@kRl0AeYTtnS%m$j2ac&<bB$zn8zoD#d-*E!tZ+tGq<
zjKHps!PberM4MvVZQM39L`5gObS}#o^=m;NW!FU*W&YJ&F`|V@_zP6c>XH)(0{N)J
zkdRlvg=U`%YY@b62Qbpn9j-n|!HEG=0J@tR?UFj%bE4$N&+zuNEf&fT#O_WUy*!@3
z+1flv3K5b<HY=TrVsk>D%2HRgttfnKTgx<c89_2*G#a;BkUNcjU>aKK6Z$sftT?>6
z_zK9W|1Bxp1$>ZXnA<8F0uS!05ns`)hNK)et1*Ysus`2!vq+?5A~|2=-)I}9`y7?#
zNla8vRXsoIjZfJoFir!pNz&<kr3<To&|C7K)m{y2g=7+tOO~IiC7h&xLB5igmJR;_
z86T|xxSr=vi;3(LTT*_;&xn&fc>F57^6tV{U(Y~yvFsZvm=^Xt8MbP=Mv00Gg9Jz|
zT$eK?)D7#Tquqz^(#TTP()ev5VUt5HM~!{GzI+bAfT5DA2v3J_>y?3^8k(79vG|DQ
zI_8}KX_>KG7c-!?$*$CLPm9JJXJ>ZPj?NjUxOS6Rm<+wIJ{8&uVx6__+stRBWlA^e
z^{9hHoOeJSe-WI!2#Ln%m9fIRs9J^$a4eS#P~`mRx7tW9Zvzy)Q*U2{DO=e2sdmb5
z$vo0CyW*?ibOdvVm~rMSp`P<x;@YeM-9;?MDifliN#co-0aq3a0MnU~2V*LZEm&TF
z9qUZ%s)qyy)vT0>zzG}97vJ%5fAcV?$tUK#k5`GEl_{&r1V@~jT%`jpnPdY*(5LkA
zEW9y(&~?aeX{eDUFjI@9PrufZk?(vs(b6!NIXi#;Mtw8Ra&tSr!tKqEJm!O$5?jH<
zEdB;(VK+~++*)%Jyjz5ep@s7GD8$Eb5MMa(5tjb#goSy0QDI#e#zuDEuHEMQz9i@3
zXNm!StXF9ic|ctD<Zvnv{~>n-wEYAU;D1WazU5=Ap88k8ni<ruNo4wX#b{YfsMbVD
zqTnUuNHn|-h0-Myfn9{npT3qjHMa-}6rG+3haH;)Inv+cP!pTWNl<1ikDaJd{-zqY
zk7#ng=%|#XjJOSjgrDOD7h>_v$vbcs;2!2Yz4)`w9NJ_0i{b+Oi`M2eTP28l{y>xS
zYhvQKZ;2h`IROkueb4KX>`)Y~14QK5*-#pffK?_j^dKv%_T!Wq4o_6;Z_gq&>&cFy
zipa*K_`-sGnpWw+rvXHp9Jt8noa`|ikuW|{AAlEk$Hb&PtS|meviop#{orTscw7B8
za*L$FF2v5I&d6stO(CJJbMjBvGo0$95!Epxv=gw0d2;Mtig>3Pm(<wV17C$kkyEpy
zmtUz>0r<JUbwgO1_sR-HlGNcrMhUjJXT(q+vqPcp{EU|3Th>^S+3p75-TuuXFYbZZ
z{vi}<XJ=exll}8;z`Ur1I=C<H;#p=Y-pizLKm$wyOsLm+E<C>N1LE0ACb$ofsiD6Y
zhVg51Drajq86WIP+!oDs*$`^Muzn+vermS&6bJ(DQnSB-rvZ54ML=0D`Im;VAFla9
z^C3HCB>uV{xc4}`O7Q>X09Wpz%d0%?P7{e;NwNA~{|GnW@Ot_{_wB+T6waibKnHa+
zfqbzSLJq&P>ik3n5i^5YtvSenF`H9^nqrjKhcAS>g^hRvIuX%F;ZN?78z2{ZxuqP{
z{qymeVG+72cY7oN#QA8h>t?|t&3W^%{~Lb06JsODS380BdMJR3veO|W$Na{YY6bxn
ziJomS(EHLLu6Wx{FgNO)Ox*}olC<Wk^5zrD2L-uU3vII}fM$^zhv0u-rv^?R6UKx)
zrY7dN_VJ+pVSm=nQmjBh+c(5+%r9h>3Ik(QK98uS1I)Ph|66_LZ{ZLO39W)n$sDqc
z&vks{mBOWu87e7KH$_JO&qs5M#rC*vJ5=qYZKqbk;Z`iI@ZNA#=&oYI%cNg^o|BH(
zBOx}n?W4N=oGcS8JX<dkoJeZB@JdoxeB3G_4KK%_pFkSfPyvlqqlTcU0y|Shu@YwB
zG7Z9_RG2cGMR$x$PEp2QsT2b~I=~~gG93oo(J;Yh*a|5;!=D_ceq#`Zto$j#H?+PV
zZ42qsqnUq!-`}9r_t|`H&AWxh-Y-aw_e&|;qO7j5Jz@&s*8hfF>i?xuW0Wigbhtwv
zN_=)0%45VpdpsRp13bFM9I50_dt=9g^-K%^c8{Wu`-7UqTWm$YXn}W;CqRY9>on~O
z$@bY^uczrjTek+1;eMsMrUamat1A=;A%zM+h-qCmHmPr5py~>PVuZ_IK6Mfys3<aN
z`33&ly_9=Y8x3YoO5YAh2C9oXT~Qy{80e!QS8U-NGGj}qx}dYDINIu;mhUmshn9q!
zoCU?d&@4l(7$&A$W%2{Z$lpq%94;~xpLHhgG7D=3<>Ix?c_Qle!On;?KU(Z}iKCqg
zjty=N_amBDuon)+QUq1hFnqjIkE=1LE<ce9Eb>5UNlrrdRy$zH>e4|Buxt4Yp){J|
zQqQDZj8WAA8)e5Kt6z~#dxBayC$dN;quM*1<Ey{iK6*-~U+1Y~G~2=K4C3yOUdqrw
zhBz0%+g-?z{{scdfn1*L_H4wn7C6k&w%oNq9F)74p)T&zJ<uA=#qR8z^I&EC?*h6r
zcAALXcc3z8GE)WxrB1Bm@8|vS1##!L<7BRu0Y{;9;9-EVb;SB|6G+N=lt3Cr?w8PB
z|HhCH|NBK(0g{lV7bcvs1e5hD&ru4P`A9r>HcCo>{p%l~-@95<5g69MZ&8$`jNUma
zevXdbe!3QT*}i64Cb0`kDZ0(pql&J)4cAg>I!mkTF)5|K_%fwFjj=s%ux{&*<Y$MI
zP+e?K5b}JIlm;|FjFjl$R`RX_S-LaFmlA>;Cs%Y6ogZdV<$)*8`H$uYT9Lc^H6nsX
z)VECF1uv>Id4npVOxO@bz(by;d$OSrHJcUjYX}@vEWi;1SEPtmCY{1D)kJ;o+mE1L
z{jUJ5u*uB_TzaP57veQpt%^)InTb}8-<N>e=<Ga^kF$c3NZlg?y2@2I(XJ&CqrKfJ
z{psYAkS2!!^OpGF3`@-{!f+ezmy1B=muEi2VF9(27>fN!(l3?x6BK2;L)=noWkZkJ
zX|Ej5Rf)elzEC*|X=q=2YFh6jsBxl40k-oA!HnAAh)_QIdMR{9l<1!W3<RVw%oVqA
zgyqK{dU7#5`z9f14Gp*wSi9oNF@<Q1IzfzTdB!y7LH_F-Iq(Y=a_z}pOunoQ2)A>>
z=c!f*+Fv9CoA4iQb3xXi&o)oWD?)fHHj{W1E@o>Wav8ljBZbC@r8rt-m?i{xOYrM>
zY~(&S*?fjE2IUBPtxD02SFCzcZcLjW<hA=68RZMGKnP5ELkf$H*i=9O>QYDgAZPAW
z#*$n-QcA>20dB+pzZ5|1`Q<y`h*Af(O}y+<9OJQv(ODH!q;gV3yOVQ=Y%qHu8XuwR
z9V-%yvZy8@%8>4Btl|!yr4Mr4`7Aijm*1;Fw9Yx<zuSH<NzkplR`|>=up8?`9^AY;
zFPH!u@8wP5u*&4c53UNXa604KX+Kpn%5gTX2MuGcPHf`Pt8xN$jj^*~+LdoEE-4$!
zNMqh7S?At$y^KBre&Xjud9@~DFpVlS{(u})liEo~dm!pw1FedLjw~?ZMOj+AJf}4d
z_#%C*xtYH$yH6JRZKN!FrWA52`**{KEUl${9ozo+H%T#QsY96l{S04S1hGgjeRUxb
zW17~A%H!$_biXWS-kdnReqUFi={kySVR0%mz|bWp@h_qL+S)aK^CK7K71$5a0^Fh2
z19n|cK{<bJNKn{t@(+xsIHzb~UQIO_K(!agUcq4oMR`dDONkd}mKn%bZ2j#X8kk@N
z1yWdJbN=V!+eJBb`qY|lz|0W+RK=|ML95{j`7d%*Nd0<zw+9k75^!e#HST6n%=Xmf
zT1unrj?ZiTxlAz7>yjV(I`xZ~_8EieU`z&nJ;6;b=j*>P!>=;a5^TLE^N$$MVW1fJ
z9t3uO;F6UN?*Rz;_0AM|?izm3lsPdqPgWI2yiVUYNRbF*YHIJLxzVUX>RHMOZk~Ia
zBaxQ?ZMDkXmXNAG<L3~;LQx<*jU0xJ1hM@Va>n#UBk%qh11#aQFyxB10Jm8{d=MML
zL?II5H|O5Kh^?V@VabS$59#`Ol!XM+aJTY2MzCte%RZax6x+lva_8LGDcC@+*$3rq
z8pQ8WxEp7nPzZq6wW}yMbWL<z=4hFg_f{k$Fs^g(%waRDxBsCqs1$QNzb$yeZtmue
zFwQEFg7(dBAY$?gjqW0%=Wq$B_ra~_fKSa&|G|EvYnZEfva3L@z9@EI!>P1?B?LA*
zeh;lK1A>c9OfyeNR`)$7mWt?z;C)dQZXz%Dn6y~SpCtp6O4%Z_h}a^7?SDcMSkzll
zpj-&f%E*A)nSw6$rF`AlMvTk3zA7=+y9@;?xwz@i+--`YOk2HRL)$=3L|z|(8P11&
z{JejyMZxZ-yC2%_o7~XEKF)rUm5Zw7qoIFL`trT1d2nrKwvvTK!w)`g?Pd`o3VV~{
zY2F;IQ$xjD)2KG3a+B^#Ir#BKwdI;Dj;uj6ZekyIbzem#^|p?{a%8?L>?ZT#3lj5h
z?Az;+4DWn(%;pIpzzKI+SHD#PhXp_MVe!aq&}q<p%r{-qE3H`aqgv1lFP+Po4OxFQ
zR%pG)kCM?KiwZN3pUK)JQ4nj9@eU3mdU94KD{J9ss6x=<A{E1rFC$CcSCx00UVj^8
z?9a3kEtz|JJpfZht)E2{5&ut>_#!wBjT~O4TKuq3L004a&k@^6qGIl?XJw0a4<!^U
zQ0r!eWbIhHnd=%Xs!py^_>ZqZ!B*RpFkkcGKy(OeDJ|%XDfKK_mO~KMyTb8G-Ph^1
z1|-wYq4^fpY+3d;o`$<7q6a2a>~`QlEKrfApxx5I0(h;`<D+H1N2og&rs}r26^!nH
z4Iugu?EJH~(xvl=JFGz-eGtUL6nOj&3FURw(#Q>K_;mY2wpr61TjWh7Us60)M}{s?
zdYP#dpiU$8StFhH(0imfaQf2kfajmFL=4MFH>^N2H20ld^Qs#4`)z*cKd8zfe?Oee
zy~;p6&^C?%Q*kLc0Ff%{ly6A(@eSst-3C~60Y7+$T6Mul(BOQ^S-$Zew<LN0E)huh
z__2t?$Y!;rd*$CWTB+4ukfc|Oc_%{N#|e1d5o_Aew`o?eiE@+<*74J=mLyWPE(fk+
z0S8vgw#TDc8wsjMFkLM=kseK9TS?prw->NM?N*?)fr73KfVRJM^=WMciP%7!+GaZz
zc+X!BiABztB7Co)n_JM*(TJ9Q1zub;x1yDBP-?vFiaMO?AIFl_eV7CLLjd-}$%<9E
zi`gD0c{Dj$l@)4RVmLzYHtu@xp-^m%vp9j_F=<C@e3Z^h5C*@>x`)dHDzfFU&Kw`V
zcHg*O9uBe#8)Bp2&dd~(zCWmu1&RU3Au*m_2UDE@%PNnJ08kAZ4qEV{e21m4IyJjn
zLWGV($%e}riNHIO`tDH5eTU|dmpbAkEf0hii^Yr8yQx=}oRf&H^)(_};ZU?dhub9%
zDx5qCMly+x=bt}hVxlNmy+?BHUpHu=qDfPpq~K#?`5h1$G$W1csgMHC!<jo{c$Ag(
zh?u4NG#>ldldTHHR*$T&z%Lt9PDS~LUE~$wV?v$|T>Vpt!11SO(+_@!4xXOSz(4U}
z&cT>3!%Lo-Yrcc>6yRSEtZ&A<pE1NeJ5B~FRUrNp*3e{@8n2k!1`%1wQ$LLJm_-Hi
zr&ZM1956)kB*Y6&X+R_fgg+1DNs0vg>6V9bKs%?DQTv!WsW~ge8d#qU;dUvOK_yh1
z@@(7uuX#DaZXoFgx~&KFm3nA7r~LrqbM~yBRpJvwf4ebtMPufQpaW+!t`<9U2WTdL
zDQ{|tnQI${XV7K=@dgh0H~LKI^HT3-to0Te^P;t7^ZXhAj37`alTdB8C?BFceAC;n
zV{gbSm?M+(rc}Yww6e^(!LjBcz;7#-3HwniVsdTvP?8}FFPR)lD%8SZi|g>WD-Sd6
z@-jH{#9XS83E|zOAmliM8U7RfpEE{1JU?ua8Mnv^t*%>b38XeU>aAOs0A<tR@*pg6
zD7|`_#UDEFQF~42D4(`(wROYKZ-Es7a*x)s=`ubj=zJU@z`ox2=Tnql?7;kCriCwS
z4gA?ow5aT$clzx$|LoIj2!gXl{MID1_w9tn0g~Q@6=w0xlyrJq%px}$r9mJACg_Y8
zY4ADrzV~=iGQFNkS^8EX*AMaz09U^Q-pyjnk`*=gw3w<)-WL<NV=qhs<?=r4cLkj2
zmGGLauGKTGJcqGoVNMJX<QCI6dKUE*+?s*J=T%BcPw}OY!$Axn&tvJbp|*xW;8X^Y
z>SLATq1^x^UtE2&cmkXi(7w0q(Ww>2x@Jl~M$MPb5E-y#oF)Fbp}s+$yG%KrfxwSt
zXCSza_07?ZWp0KX3ngPN0!E}0gbM%tH-0nEsZ(OLj|Mb%fRpI=@Kx?B7VcJ3h5`QZ
zFTp7xdEGJHJ2xbEXk9#agS_btFiI7QkhL;vpuy9j!j)&pxGDBM_e3GWFz~^>Zo+9(
z&m!<X<2t4xxlmjfhW{y~1Psi3e8i?6F(G7ZSR7TsE0mO8*(#?JH`%t}PZgr$JI9G(
z<JrB{wnoH9x!2gkeKf?=st)BRWu&m3pbrmw{ev7V0d<;x(Luo#R)1D=Jw#({#aTn_
zi(_v{+fNg%t1YBR%8DK}XMRyNU0k#I=odc$&WjX5Kb1K)upfPek7>PrF|ItH+zURD
zgzQLlG5KA;7)VuB1j-9}@+FX4n(;F%4LqcV3SR2IGHOko@&3DdI%_x5&UyiWa$z_Z
z5C+MRjLE_;_ld%21MN`vw~lMf<C(t{k@6GJ)q&a)a;LnaEKx_$qFu}`uwerssSZ|H
zvWyBn!r|m7ElQouwrHTTe5@rxPl${b&cRO00b0xC1+ifP+1jcoDvjaa<um%-E+UDD
zE%iT!V@U@qLY(si_%9xx^}+_^MzSlEaW2kY_RP_A%u#!O#;YL*Wf7vpd((FlfhVc#
zQ<`pmOtsNZp^`Fz-eS>}<xk$i-(Vc`#l5*d)Ee?1fdjxI)yJ(UbSKz&=?z-sl1J9F
z$?gB{E(=bhA@Un=_V>qMlx?dkT`jVy$PSF(DUr()n@2QDMHA;)5-(yE6B39VjVk>N
z)&6yo@H-CNK-Bmz&Dfjw8tT)CnnL-=t}qhkMpF+PjkSXslYNb_dIAkeObI-K6|lOY
z^!JRSzw#Vq-}$!5=1V7{5S8>`7r|riG%(dJ;=>1gaQrobqaq3wi|12ObA1f4JIdyI
zH1;}8Xk^gEAl2qJ+49Axo941dBO^c*^k4_cPE6;O-mk*xQEPBrr11>$jY^hP{F=yP
z81=Eu;Z?bTeJrn%a=Qh}H)ozO5v*dptI8-F2MR~f9SPT61gNL1<xUIiKi2WA>^mN5
zW$_3u@miseAf>%TzJjYQS3)PsPOJLESt-)VOitp7z~=AY=U^pPfaOOy&r*(ck9sS3
zf=xJFkFj!ea5RL%)VzT$WkHal<CY0ikxqm_{4{YVJ7BndP{(M|n8?ltd(Gmqsz@ob
z^-(1bB`D=$99pH|@;0z8ohdIkUJ30vWkO`>*=7Ty-f(bUh}EoEb>Z9!y2LaCpf?%{
zaPF{4QA_bx<#*68(*_Qx*5!6$$OjZUa3<ImtTf~YtQ7gnG`sW2Z{hYa2Iv<JFwMt)
z_v>K(CdB821NYl5V|61&3V__Orejsoss7YH1EU{h-n=Nsa2qz0joLZ)!*h-9gyuiq
zzEdL_aEU%mYbF9#-{qPcGvuqxIMDtHN#)lLap9o|LD}NF4|$*x5Fnh_er;AY?`bb{
zFBI*a@bG$&own#>XvQ(ay^cVXvM&HHJX{H!V8PN^hd*fiJ5+WC_XNeAP7^lB^2^Dm
zuS%Aq0|cfhHa*VtHm+<O@Zc0M;n7;Z@r#^xL($kK0edUVn_Q^<Jo-LD0jzXbbY&@j
z8ejSr$8aHa<YBxAhB0;>nRjH?m_~%MhX~L37)}K<D$%H=7KOfDQb?Fqv$P`I|2pTs
zgod+1Ye|Gsqo#R}BIJW82wq^<n-o14%g4wQOoXjih98FggGt*!^?d=<8vB4RBC$C2
zX~oq$ddZ-NEo1&*V{nrmFY~@J7t{I~<HHJ7wZIG8Zm2B>!_8T1HIKuE1-=!GWh;`z
cW5xL26+$+=F$D4d?DigGZCibkDsF{IllD_vZ~y=R

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter32.v
new file mode 100644
index 0000000000000000000000000000000000000000..94039a985b8bcc7d83e3b301b48b97ffd4e40b8b
GIT binary patch
literal 5512
zcmV;36?f{36Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+aq{Ys^
zTpv_+l?YyYmH!&r4WWN{$0;YeoPKZ(C4E!mtw+-YBVMM<EoxmKDZC|Js(+yWsDUjp
z_QiHv2|{QvA>cFWxt^yI+G$M1>(OT?-}cqP%iz=BTI@Nmq)}n19N4ARA7HJc)0JQG
z=KBNC|ICWcVKbrYF0dztUNnp7ne?Qu$dfV?0xCr>V24*eylgX%-x6$rM+N>h8=)q2
zR6@De`~|qL*~S3-z}`>vjIGEiF~iyhT6c!|nu;M*=4$3Wi!@9@a)^Yk<H4_oiCtYc
z*p>E;maoHL)ACdO!HoHVjIS<gzzMN3psKGi24RwIn}do>HZ$G2g(qP>B7?5#U1q2q
z1G}YAK{Dpml1KVnZ-UfZhxWe^FYd@9lalk@>=cLv0#;jnwvcP%c4_eWLy4zA8%y{F
z(@If*GF3cr2>cYwPyeF>j~FfC{)*5xG89l|#lY*t2<p9Z(Qye}JtK076+Svs5OpjV
z8r>^oVfPvBK+&h-oy_}c18x-d0$YSoyJ<Ka>svS~W=zi8>ufJT{ukmt>CfhY9~e*y
zsHf=ppU^IsZhBRDz<e6=rX-<;X1&N-5T!fXV|zfqzE8y7LGOGjp}dDl-_V#p$~gm0
z4BP<=P3nYGj@cI+<c8EO`mT)5L}4&YPUw)OSl{-c|A^UWbG~~^_HL-bH!U+>ua4!{
ziwM`kT*kRbA{7@RJ&F6Ri-~YRrX#Hl9M=KVBVX$es3_CmE+ld4H1sr}R=aY8Xf0OL
zaXZcrDdzYjJyo>K-G?)saQWMD=GjEKnx}(-z$GcV;)?F1e1oqS-H{po=Z9~%SOH%N
zNaR{cQ2R-s!epddER+8Y=3WT%h&UTJyEC#9;u$>B)oxwpNeBjEh+bwJ49^F`H%50m
zTP*%5aLPEbFRbRWy3Y}bZzBezir6d%>Lu_fi~}D`n?^RibhtL0{>K!X!4)%mIJ??Q
zc#qFkUCH2V7y(1H?v?uG@|IFi5(g*POn0N$3Oo-OhVI;{tO@99RhVh24*i0E-Z*ZG
zfg?8{(HHWiL?TKO&h8cyuOUPB%?{o<@Nln)9JMxsUd>d9nx_~fF29ydSbBqHRRQ(I
z>d48;X1+gGSrFwiDililpBpO-Q1;q>d8|zn%m3k9<su4wOUTf*BFlLX&^v<JGb}Pr
zsjfz->$CM}-hN-#b=0NtQ5p1*yx9OOk=3UJQ?4P$SK7y0#m>hf6Acq1K=7hC;3ni;
zqTd4b;`VQV8yXmU=ve4uoQmVTy#IGAtdV9n`)aqp=H>;BEGFGPy>^$fBUrZZ%Wg}$
zf%ukNG@m-L7m8u8KJOM4$kPz%wWVWuOUA|6^`>)|lsq}|<$f3geA)k;O$l!s#0Bfk
zk{3)B%-Q6>d0C?MoPDYlVQ1<mYbBLF%Bp$B;>nCCSba^0E!rqKqNG8?<RsA6$`h=;
z01Sq;IS8`;B@RM19tcNG1~UXH3TM!JnD)?>H+~Sm`jl-ppSeP+nXHun2A!+F)Ow2M
znyFn0qQ-`+p4anlc0AoJOBa26?OtM8(ZiIR##|wb6ThZl&$5>K)TWnhJ$w&;CL$q3
zF5VX3cjkidvq<-?rO`t-etlTheWwyyvU1FJl}Q>k@=x+*lHj1A!c1+!hr2|`JSaZ&
zW<>N9r%$*)CD)z~HEhKI*r)xUzTn}>?|eQ5gc<GYtk_f=fvB^86?eBx-ynWg+s)Q7
ziB|};1mM*BPSiG7FS1aIN0i=9fEn9^Yw=P(v`gSfH%NqPt1-r8J^k+1K~&08e(@Id
z4jCyO4q^82K;Vr4wa}@(NO=qO0FvlVu+NRo7@lhh>A?A+?EkF?b9%v|z-DYaglJ_d
zoDm8eiU=h?-t1aJ0&h7_5(3?#mml4zeglQLs!U%*@;Cmyj5Ph@T$zGps%ywf;Fs9i
zb?OS&uAWWWC|(ONb#XJ&qikZpI&hzaPSv$VIHiezCf2+K38Z=A#=COV(x9REdc}^J
z_>wk=odK&?8w1$VhEM?MA_RG`dQKLEgKlTk=M2R*+QMk@j3_e<)?lva<=tU-K&FY&
z-HcnZ<ecl^jITn{g9?*9n1Wyq$_BdfufM~He*Ov)k=?nO-fIz9Ae|j$2l~Tylf)S7
zN4GLQD<8rD>(Wh;lrsf;_A$7VQ`oX*(?YN5&_qjOZhlK4GG|R1cpS|z)PLq!9;rg~
zo(t|Oj`$)^*^uPWNlV&jvKnZ0^?(j0i=QK9-2t^Nt$*;i!g*!U*dYyYH$F`~85}aL
zz_L61k|Wx*^HG|)lHQ_=RHlJaZuz3(Nw%r(f52$4yCe!Zrh_!jkmrp_Te77u*pI7p
zQ9D!Y1s?Eu6Ye4c85_M-gFQjTJsMvaqG1T7t!lnY08VJpkaN9Q>|0sE`1ihnzpw<s
zIu36bzP*PLi=5J@fEwQ>+(Q44QW&Jmck`U?UVx!MM20yIgs;f(88zPbP$ij6<<Os~
z;EHl)+j)Ppkr%T4PelCxM0_ODcjB))c>gG&-ZA(VD?F21z7vgGVeQin2jZKJg%M`E
zg%v{9+lgyHyQPd!NRL7J7V7jA7_aVfMO+p4E-2LWM-_D)*NX^2HL26i^MDujoNQsf
z!ZLGaOpdV<zTcOc8H7Yp=s*SmKGRnC7#+Nks{f%zjvY}C7G|8M#RSmi#NxzB4^L~x
z0R@T{zfkZYi$=AjZ8Ync01tQUua3mmC#Ur#FhvAkk`!#<$LbDi`F#I>(gq+x?SoLh
z2Av+WSkGGz;ChBo5u4K)#!g&e8){6@0sWtOX-Licb1exgAd{7}w%I;XK}h@aCDCl9
z%uZ|Q_z63@xCe*+pRS7o`t>lQtl=9$m6iFW80+gN$&F2nZgOA3$nKMt#t*CmvRW}*
zS~MG4`EjU}M65-82-*FM<})jV7jwi?W-1x(uP-v#a_tq=;|Q#CZI`j_l-b3)2-<SH
ztS}5hd0@S~!a~Jzuj6a;zl)`{xqcYt%1d|_uYr)8Itpkb^>;xq9x@Lv;%;>UewYGa
zT%Ycu7q!#xfgH-Iw(P+JNQ=_%dlB*n49qNo#ai@Rm9@N0hEqe*{~RG}lLp%mf~I!z
zH1j<S8@zs=q8eoii-uyPm+BT<7V3+pgu8qrTh#bk?7nXo(d^E(+t+p9;kx{<0QAcD
zF0$m!kBqOF%Tm@bN&Gdd7cB_m#w<#wb8-KOw9P#-*C}kXWS~k?(9>^5+?umnrtZCn
z16a9<;w5MqCL5P5x3(iA0ThFtPnofYpv5(N%Q?YoIta793%@=U@sTX6{Dh*8fZ6bh
zb-+I{kYU;F@|m7S$3M8z@)Et)#VG0elhoFeYo$>6=vD7&m7wcKA!^=QNcE0KFKyE6
zjsE+hfjFB8%OwUZX)QX*u>7XO00rsuGxYv*)0|T+U^2xKiCOOC2QCh~n&VeGIjIrg
zFExI1Dth1RNVk+&aOmjuY_5)~){CT+f|?)c?)h^OdW|hTPzT98JeaUem*<b1hHJjP
zE9z#1qIXQ3=uGv$(AiM*titkt9IT#-F@SL3+teEAX$)c@LTSU?cvl@H4{uQp=uUlv
zyeDsefQHms+gp@I%cUzMARM^hk=ZBM<S1h{yV?a4&gC(>l(Eh}+@|k!6~6-Hz1Nc;
zr^cf1mnyv;ir&0MTpj086P{v!*-e$vS0cgJCPJ!Lkx1fl`F>Tv7p2yewR)N2I|gUu
zHh*S1CNd0rH`3hMt0Lauw1sakSdkADs;HX|!?1{l!6}(*zBYjQHM<4)n=M1B$1n_s
zw;^=l@t1iM=momxKc`E9D!zC_+DSQflxvWJ`nR{nA8dPs))G<349{`Y+3few0Rh|*
zKW-nmH)#RX1Bs(#wmKdXP=wW--NI`v%)r^)v>aVIw<f0jVpQpTA{pDfnqhZk4^Uh^
zJu>{<7a;Q5%3H<X7&IF}d^Z3iM0_-N#X4e0YqsVJ6O6o%MtYoto8Mayyc(>9PG+KZ
z1|)ibd|DCZGGWfx`UlHo&MLftnqSPMjAt56r*}Mwdo<U+$o+>v=c`mM*~RHFL19Eh
z+|)Q$`&bMP1o|rB(Ak^b^JiU!k-NT<{ERcK871_M)BZx2Rf*2o-sdxHk-Pe_tc?nu
z3fQzzr)=W0v7T(vMVdjQ5{r=%%b?;+x;_XDf@VLZMEy@}1fnB1Z}u5Oi11o}HOWj$
z6W{c;2m$n(rT?Aj*cLj}f+|+5kv70UyIY?;eBSxAAF(;xF<SK?{A*BS#S>|}Hl^Po
z8R;OGeqzx#*f<9`H+Szw?~z*48>rbR#OdKU`K<QS&@;l8gbY$ocwO{Y4Y8wcsAnw$
z6)c)^u8kl;o$}RJ*mHLqaO63+tBuh=5&^XLnU~FzKp?IcgI=p9o)wi>Cj%rw2WiJ-
zwZu+jlQ<^2scWI0GZnROPI{JGNbeyrnuey7BmRfa&%eW1Cebe9dt_0?&PkL;KBmf3
zOS_>K1onruNr(d=Nmwrjtpg){uLmE$TWa^nS_)JN2}OX!q1G#k%=~uDTgjIXtlshl
zDsN$j0Gv3ogZm=1vdx_PIH7tMSbhBYq#iw14a4C7__LNxm64<xV=Q8lM!t<W42R<e
z)<OaU4nOzsSDDm>1&`%FPnus?H|z_9OgMCK{So7Fn$~hw)b2mUy@wJIUgr)Y*<Y;B
za}N7p$*0)bQ0K5{=XWUWd_IFYz0`G=XjGw;af@s=uW%%sFPqz7fDK{@ZiRW2r?cij
z<YduUtAJ;p2m8|^>@S6PcxP7K_Y<b5WM2~<L>f)3=WB*!e7eHww++hAfl|i5WEwXu
z-**<Ao~vYag-W95Dz2^a4`W*HHHk4)9A!pr2$q*@Ccx2ZqKzv*OQh|nyvy~twcf=b
zfAfv36ITMiv7vEEd}U7j(}Q|R2m3!L-FgwYtd$j+&)k)afnvAAfJ?f*!pZRacNEhY
zm49r`>_T1()o_GrHpx?QX0JDt(^W{6o_8ywjPU8+e^&>OWdN&fx@wfSSqF@l(N}al
zzzY$m&@k<nii6lHr}^kGBY+<ld>KwZx<~hGrTTkx+PFj3w7n5%3d^t=%!d3!^#WSb
z<AGd~!GA<%x<$;)13|keYi_owO^H7{VKnwc%5>0rswCd<O^9N2!$8J`waD&SJa)H~
zFKyoj=Ef!r{#P8smQl45)Fr#6<)Oj<{Xvj_h~5WrY-9odvVEJ0+&gXo*ZV=cyt$VL
z$eqpQy02fyeyh!8fNeK|)L-dvjy%20j_*i&!mZz70UA_o<)&S_ONf&&cx6Xx(>b}t
zh`q5OLoS-9o`79>mV=TRm+^`isUjnAoTGy;sU#dx_`Trb##$uMAFOFG^7Re>2Y1!?
z`q4>>Efoqsb-wSd>&Ipx20|By7q#h@=?(H+&FD&!D*}a@H}I-G1e46prs2l#n=!-J
zIkCtUDK5~;owx235y}A@HDq!)o+G9;V-g~sn3nDB#C}oai;$lWkP6raI;q3~o@Gts
z5P|zkj8=b+D5sU7qMfooo4D4QL^(hQm;ZuGR%YZtm986Y@Q148-~?KMPBs**-}SU8
z#>HmSnd1!fDP?*w#*Phm3F`sU1qZNOerj)qa9=6NeO9INgF~%TH9mIFBvHh>Bumf^
zV2O(?FZyz#ppie)P{lW7#Pw2!zUzslPsO|fsH3i`)Wd40_-e=~y9~x6wIOk~>mmc6
K(CVsO{4jTQBF(q}

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter8.v
new file mode 100644
index 0000000000000000000000000000000000000000..2101ed859d2f50d0857a7b9e4acc0a103ce57078
GIT binary patch
literal 5320
zcmV;(6gTUO6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+aq{Ys^
zTpv`pu!8Sq<tz~211C85St>@E$v$91+X5r!bosbESRHJ3a2y5gn@`q(thI=AQ&k-S
zj?65R`o`&%b=m2;Q_X*4u7w(|+A_7=tFnk+o~&~I5v`VDjM7Eyamwse2%m1zGOP!>
z$Nm<8F8(WNmhnZ!kd)P~bVG6on(gU?7h}wFfJUE0amq^i^Zqm-{LjW);t#t`YVx<i
ztY#tYv&98;ZGn;O22?kGh01=UbF_!o?K~czNM;25B_!Dyiyfj4^s*@!ZSkiN$of6w
z0Quq&djdqcPa!Z4GPdqgR)$PXz`Y_0tVcr0>!4wZ?c?UTKWVM<cD_bqpQnNQVu`}S
zOHou@c$|h-##%krKH@?hZd8one5@gYerOp21_C>=w--bQU}w_&KJ9!5#bpnEF(M_7
z)yXM>sQdSQkbA-X<GDI@4JdGyn;paZKR+pp*JonqkII}6fkvdZeH4uxoouGK>ANMq
z!YD{nqaXHP2&uxdYR&zjUvS2uDwJ)QtqJgiv9?8XOc|ErW03M}ITG*?u$K>{ItS-l
zr!mIb5$sq-miu_RL)tbxUR+CrW$;(w(}8=XHhz^d1C<Z2f!>NAmN&O8Sl()^4*CT_
za*t6_5s>Di;IYI6ut7$KQ!rPb<xS(VJrq>9Q_8zrl@_lz4F9jhCckXJlS;vB;`dx1
z6K$@kDmc1k-#eA*1IWkU|NE^y!FJ;-#pTo5k4t6ysKgZ<oj}YZmT!5q76GD`YsL};
zxWr3qq_=dezPPl@Q}iu4<$hWwW<pWwjH7@p&#l|om?r;D3GT=iTOm_ih1RW#%B^1z
zp2D0Uj&%iWmg>}Zy+93D7yc$|A&$85rteV!@0(*%h`ji`usm!JIu!O(T^qEkaNZ%F
zecVor`#!5D9ir@`D|8%oJx5tM@Rl1DDRUz?awe)%9{5T#MsP?4*TrXM7OCtXYtGoF
zEI$Fb#JD=T9>>9c6Y!L@jl^6CJKVrZuQEMDEjty(<Rq6sFa*Rv1&vz@*JET8>GCE_
zIDJJfmzBN<KOqQcBy%mURebT9c>Bxjlhcd2rK3t0Ew6-r3Ft>{b6jI7M@bK~`yX0V
z>cE=+20?}uAO*RdrO?_mjR3ra2HpBqtMe~#<Gw@8Pq~~QZt_s@Km32gXzn;D+?D5_
z^)L1LotJ|8Lw3{Sx}lH*`9Jhvgp&=}IjY#Ky_DY%wrM%DMKgbcLc@&&VKviWpw0N0
z6JrgCriZVsc$g|t)|&k_m+~Q3gH4LrTg0K4%?i#&_Qmtp9q5f3tFM|PAgMf-2<d+R
zv)?;<IDZ|+qVZfudnsgdttcpLgjc4m7!)^k8=XH-`|gxYbHM%p;JN&PK}|(8)c<no
z8PVHatIfGiyY05I8vk^F@+FDR9~B#~=j~O}ZvaTLlF@og6UD~-NF>H>hUd@i#+ZCH
z`~=67-?UG^5W#?T<5{CgYUrMgA8O&jA$}!Ab76tMG!+SFm_2$_RN9{xTzk2kT2O+Z
zB8LtoZFV0Qf@a2Wp56?=2X>+otfC%)Ld>*)ILRxljOA!+_+h(!5D$s0D3fTzD8t#|
z`e0rUx}VqTAPtCTv(%M**t0x3R5Wo-Lvp}ax`zH6LTiF+%e?zSl~z)Ln2XxWn1<A%
zg<oB>O!LP`1ZCVmG8KWnt-1WIpm0~ChnTxkas6<Dcec5~0GI|NmP8dTkCljG*#|YW
zDE-74d8NP3gfIao`29OJyJtrilG(=xv$g{L`kV?#`MgH-K+df11s-MYvREbq8Z(RX
zZC8`|?BH8jap4}b{N_XM1wp?=IPvCCCARGqOR4>?ClRPGFr;b&Wxb?~4azu_!*zhM
zIZl9W(l%UU5qyS(X*ya9`w|P8zeaB`-4WmQVd|JxxghAISCiIHkR0Jv<4Dc`F>YqP
zAwcwk`U*c3@;&$WG&3D;CqMM9TBvyoH%3Scis^6{%xt>@Igq32IiJz(vuCjr+=I)i
z<`QN<iB@iGq-&etw8NBpF!%SKqqo?(AduHYNU;(D$+0bWT*4vq`$TredU4*K>vYFp
zoIp-~$Uw<NCZpRNY5vI+#5XCD0!I{^r<W>H?r@L}MJcrui?Pv9q(m(%_Jaqnz#B=$
zKs{|6iO^%k$`o@{O^sRYJk5_-RmQ?ZC9Hd`bm)Jq#7cxjU1rT7dQBBUj;lzRp?bC$
z<U%m?^I<rgCs_0^D?_>}qf5)fYI?|xmPa+pmaXu~4ybjhA@9~D>0L*XQMoDk+E^E_
z%v(C5S_VjVC6(h-4$HD3Dau4I;;qTAy6ZjTU5L3-#((k4u>f>`M3DgvLa)BA!V)-~
zusYK7ETmVGw%=p=U=7I@#GJL##^Tq_PI;CT^+tp8{FC??U56OGw%`H+c7vh>Z4tb*
zb?$J2-fwgHB=zzqolA|O7m0daVS?Xs%Z-xHEXb4%zD_=DOdbAhpNM3HFoleuhly(z
z2%Gh@jAS|mG&-guA|Zae8PIEH7s}$w$E>4z;uuk%p-f;{Chw;*SaNm=d$CqUO+oN|
z%%@GbTu9#7i}$S(#+3sRXX*w#MImkas3Ls5#lgLgSM`n5RW8a|1XW5oBl^a0rB**;
zQDg%!tpu?>{RgcnCnaX`t=D76`W#D?D74;C29@-nlR3EWp!e)=GW*Ql58{Mz8Ed7e
zHp$<GCY|&&@{2`B5Qk1xX`QRvZbeK{*5~Qb6zDkdQq~=bZ#sdV-v@2<->u$|{&WLm
zVLT4214=I91~lE4yn;aXfTJiO&8F69K%PXK%Xvo8=9uQ9(BIA(PNFysFhssjJwt|_
zKmP-A?wqhqRaEsSmF%$$4@$|K2-suW-*JrQ4s_*k+gbIDoLNlE8dveTMq=pnE|Jnj
z5Tu=EBi$C)0<SnYW1%k7b%R6~$1qd^nAToofTxf=%8FqL5M#s*Sdb%1r}I-`nlvz+
zmztLZZXWu9?I`;Da$~KZvi4)OO?2rZ^$H3Mok<$Lrjv@Q14%;w?7qj5b(iy)W}nZ&
zbkp(YFF~tV{&?MdNV&@F^i<9Pkkb5NiX}@R_<p>1cI_J_S>pA?3Pjw$MOV`4D>6LL
zuh{;+4O=Ij<%gHz&jJQ;KaVDLN7V<plJ1WhM7`VNcCEc}Ki0yGMRc>2j4hNZC*loz
zNYGyI>|J2>E>r0VVzi0y#T%(DmY*XQp7;qug~SjU7^Su|PKxPr*WjebNQYi0M$38`
z{;lr9H~l!F_gapX=K0TL)jm{bX;Jd?NXzxoM<u+^OuMm3x>%)a^6T;eVa}DAuaIpZ
z35^2w)=kU+1~q=nttpm`B?-e`R~?I{U#lSK`yxMh1vS=@N^Vw?7bkR(aho0}^hE(Z
zP%wgW`YVlL^o;5~3$!XVJa9&)Sfbbyd~b3Iv~t-3`{PEv6T7(Pj<hs`zh8bQTw#u?
zFA)lG8&G7Rx(bioDpsGk_ag^s4CpRUJ$yO-?U;0@Y$Z0?zb+6TdS8+~mW^+KBhk;V
zZS?N}uG<8OThq>oLdlmEIBYRekjSG|4YH}Jx#(<Y`PvW}!wWZ_+eJHNIvA{pa)eg#
z-AE|8Y+%P0Hjd^@k9A1U#$#U=D4X;6$85w@U!91HsE%Nby(oBBnbY@1;Q_Cl`fgXe
zABuG4#JkA3MKR3bAzoWLK_fw?h1&^zo8*K{E~VmE7>FZ<rhf;l7pP)hoX&jOYfnsk
z$b}Yc_Bbcr-QkL0<ovF=QcW26T%Tu0)PEz^f?}RrPj$<}V7>DpFrd;aBQO=tiSbh$
z4DfHKy73fU^<g6e4O@pq2^Y*oI|J?zs8&9wAo0d{6o->@Zz30;*i5AIsmj5ki~6K-
ze*E3Yv>_UQ^b~Ckaf(-VfojYMlAnJ;4YWN$&f0=GgZ)ZIq=Rb`ORD7epaAxFj-GEI
zedSLHBqp+QNK`ZQS}ns~ZMQ|D!s--XOL<7;ng^e>IrMCFk<8-tRkJu<yw4h@#OYF=
z*Y7p!>_4cnqkd&0+LKYt=>vplYm*u{e0YbYGob0wzU~4rv}WOblwhYsE#%^!jQ`26
z6_1BN&@AClL%Kqg77Jq3Anjr+C24^h9PwQFfIXQgva28<vcmJ}`%3>LZd*b)IL$ei
zk52A`O7$2wwr*&*v{pPu%ltF1ANEBH0nvMXWHgD$X^uEs&*=B-vW#Y>zA@~-p{IJ1
zp~^mCfk@)_Sny<w-oQc$K+yNZb|~!>m?~fZWx3)rJTIOpf8+g{9N8moKuU*MTfZTi
z9WiB9kAs$Vz%`QC(>Yn4I{?eGP)7S8&iH?Zbe@*q+=SxpvFBRI$3YB333QGqLQ*F=
z-96<XJ1MJm4rVTz%R6B?1Th%Bb!-~aLccoISirCZn7uCw9&)%tKXx%tPyjh2<HEyN
z_0fwGc|UBU_vAXd4J<BKO`0I`cCU>LIUEe#*c8Gn;Uvtzu9UzM3-=nDr?}|ARf;vM
z?8XAF4Mf2{sh(jK?L_BC0ByF1p$k|{I6E<xxYbk}h*+FLp#Jq<#t{;=A_}jT7&{uz
znVb@#8%x8FSRqe^5iw@Q_}`OdYMO2woZ$E+jd=lLfNmuAA$_`%Y1>LKMgjmO6xTSY
zNgRqu>btm5N#EaB#=sPis(fMEa^TQ<xcDWmM|9p>1I#Fm9sclH?Yj5pELQ?6H+k66
zZX(VA!lk_7q+7k86kub0P4osuKo_lNQd5pgXH1WwPY0+*lZHH-RXab{?<&x&4(jPr
zYF-@kv2OV_uzOdfVm<`(V815w-C&FJ{T(9oVpcOR9F5uW@SoKA9r1U6;;a~TKLqky
zQ*}>9#tV%@4-RO&wrHK_eF%G)<o7J_MX^t_1D)>>JP7G_soVS0e2v7InU~;1A-lG@
zJbE6X)?ZV0W0$V&>$gMp=BAn03e!m8NfeatUU9dOI9MG@U?Y~@*IUkSX=IaLzsSW^
zDUU~wi6cMw@wm!#mNpgBA(dgr)I{83<J*@t0upi0Iw+xpq<!(n$|&+L>~126Y^StU
zf&+Mpfm=JRwX_|gQ+r>VpG9q4otGNCy{I&}+jrd6TuH?#p-W?~k%v+iTAzKxutw=H
z;N$K#@2he6ROZ%zExJUt(~DL-?TmyH_5)IKT?NN~W5c<M=X?fzk>WnV4?K(?LxtdH
zL3Mer_7C_;M<=iBK)^vp*XhP34gb=iD?hqjQ8*}A<B#%($V6bd^J%%l)_Z3|Q6`3-
zEhYoU_^G@?-INBIf2is)UshA1f43MUS0tYpoL|`IP*Yegrh8RLUS^nG7X=*bt-M>>
zd~w&FfnA}vs}R;&oa_R8G!+MOpJQzQ%8n?)j5QE^lKr3_foo4^;jKNs9d<+?nxKHr
zEJd7cg6H=m46N`hb?=ZQ;65V}cXSOy(%%(FLJlt@_S|lMf>X7qN4X<>8MI`{)Hgma
aUeg<rQ;S}G_Xz4PinM-DcByz$U{ul_I#LDz

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo32.v
new file mode 100644
index 0000000000000000000000000000000000000000..499adbee77c81cc48ab94e46b0c9e9386d325391
GIT binary patch
literal 12496
zcmV;>FfY%G6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj!OiS|(+-e_kzWL&;-J-Eh_?)&I
zhNJU_C>dcxs1mM3^oSB-^Hh9H0m4;VQvuHw5b)&qsOioIEB?}~FX#zQyt;!|=Ql_+
z-_ex~;Oauo_uE?)y=-apun(xe>DgJ#Ec`9_EV1_S3$55u&FK&DUy5$zZRl+K`lQ~O
zN*P$dEB!seJ(DdOdg{^ZEg^h`PMz@w#$CRSgF>=1#SV#}5rm$|m0_p(vX0|vH#cOy
zScrGfA7@seBrXGpImDItzT`Jx7fR$P%}h&8Uupm?)c^bq^Ul*O?35$s^XrqrwOY(W
zlFEnWM7m&-zqn_FLkQJ|Ds`8Cw?RKRx-)<6|H}kOGPzz7x8`)#;~C%t*`NFMDAGR6
zOmKH+QY4AX_Xmc)9k!?2CbWzL@^2p>3|a-qh}28UymU3Of=_4_dBYeoEGm1VyOf)+
zV6Mw$C@Cvm1zAV7$TItS%PL@)Sb#LE3L|ss35szyV1v78|17SOeH|8m|4d{JD3{Wm
ze3S4%zEK8qIYDPF2Um)Cc7x>b2k0SY6OQ8wen}GI!kWrI_jfgfpbIv;mgkt)+XLGU
z-}7^{2D3y<3w5Jg$^idjO$yJuAY}!)<pf0%Zyr@{+(2SX4XUwArYzZWcnaib(~@n7
zwrH#a_dgh`G0$Bn99-ITR730^IPc>!wS+KNn9ZS@&L`2750~s(I{(7}SiR1}fuRm&
zOwka-{Y4U*j!2y99eS0-p$eq<_{AQhI_2s+8x%w`;22SrwZk)!(te@jrD+|;^niSE
zFVqrc1v*S{owNgd=7Ev^?-6?G5puBd$XZ>Pt7fxG@sIrwiMyj<DRnnrtL%jq&l11;
zu3Y#L1oa&Ypq3FMfgeaYodP_huQ?YoXdQo;!<_Kl@!2y$VMl3e!EqSOBcd{D^lR5i
zI(2`A#KA|o$a7xg^>%@J8cNG3b43j7<x&!lZqCMZh`8x-FF%ieXSE4kAY8AJ6Mapk
zL)S~Fk#FMIq!g)=w&2Y(p$W84-)3{&jv|oUo)TKpIWGW*iMXFW0}{q2|3z+2dj?D$
zKaXQl8t4@jhg5qK$HjrUDgD~k`832c9=}Eod_iAsNOiTx-jAZmI7rU$x<`FMf;Wg?
zk|j6(2w~F+p`|GaO^j<{i#C<E*6PBvP^I|^O?)Lp+BHsI1Vm%VlLLiXnG#C7!oj%@
zdg;yon#C9<dcymP3}8A9_y(_~tQ!M+?esP?;`YE}-<g-L{Uo*|^z*Uaf)QV@DBXEM
zdM(wAU2-D#1skvxuLM9pTA>*3bJrRhV`I<H95Ypx=s0RJbpb=!unwo|7~rOrZLh#6
z*?87+DEkOJwz24LnX*#^62AOA6|Ls{+Z4+)PFkIXVOTTit7CEwb6|}CAChxQwt-g4
z3h9VT;o|^#$MsEb<OsFtm||wJF|NHk`h0|ukZ{;HK9=pNFdK3TZ6I|O7-_+@pVqd9
zU-hjC_gTQ^NBvFMLc_hP8aaw6P_U-m5M<WCimvlYSCA2Tn5EK|a8<d`wFs#{r=kr>
zJa<rw{#Z!HbSRLgT&3bH5}lqN^BK$)(EDC#+mcM~DbSicMk!4$E*HCZ#`g&`1&x41
z+j$pMDXV`5TPlE9tFl_Wc0E-cu>V;|0S)Gg8xz3$-E&~5#sRu|AL(*WQimKlj3L-I
zW>@lC7$dNeV}#xs%Pq_Gk&-%OiHeA5$RYdA?0;so`ljX=P&2<@;NrN_jaQ~@5>E4L
z2hSMq&_|a--k@azmUo#|yx^S&-x~HQaKbNL{#&=p<E`w5oj*A5??6pRk~;-9WY-lT
zkJ8w9?VD`gj~PKkaot(}5&M%OK+<J>t~&%Jy(!W&0j=>=jK-4GuP6P+$I?4<&WF*f
z2uxJT#3!tYV(MJz*+3oo#L^=3VX}2wKvQ*{S&b6`L#PS916c3p6zi7`si9ycy*5SD
zvb0^T>AM2fi|^yIf$4?J)z|5Qrdc-rNbsp#C!rGzI<gYq6p~)j%G__XPsq2->T0D7
zQ*tQMp`3B~$aKW?lgdk`;7kV4z&BBa>wxT;v>XP$(}^sXRwlT4Mmzk^1DZUUFv>5t
zuUz@aeRJvVrJdOC?RIF>{cd9P7nX7agRt+#99dSe{Z+K9V3WnwK>Hi<tM?bYyhsfO
zL^A^%aAh#2Y510St&*mJZ;$B-3{6yD*)!iow-j?P7-~Yb1fJ~m39QPE@^oqE6F}Wj
zqAv<|z^#X>Y<)x~nSibvQRM9K2-Jxg);x>S5OlY_-PF2xrIdQ+c-EyLHqDD|a^5gt
z{-qDQ78VGa<BQ~wR8*wLOU-oQ6J#jTgwK61DJT*721)uwo*v}Ot1LzFcm|>kh4a@J
zhlrC{=%W|W;1rnq;0YW6HFQckX}~sc+rDy@Vj%*n_h?}JKBoH;3YoszDZuBuZA%vl
z?eKFG@JV-dKt=;;2|QdIyAuR;yaem<c8U)?XWPofNIy33mkI1bdgOx9Cek*n9*Z@k
z7!;MjtO{sH5plm~`m2UG<gPz|+I^+6IkfP`{Ch0?)ed0;-FR4&z#UY%%dvsNncnAC
z<ae;m*`y!d5sxgkMbQ9$VMOs35}C0AwNH2palZ_`+;5tZt_)Oz4x+IK;g=(Uu2l6@
z4@351=gy8*ypW+j(gIzkBH=COzpdom)ngX$Ln1)~Pe+~B%<mY2Lxvdyk%q+JR~m+8
z;C1$!EbeR#)VAv4o$Aki(?bzQHsPS6vI;?i@YcK>H#r9;f+-ar`kDZXH}i+Ye?A1y
zh>Y;|aF`EEM0)r1T)RH&wv?mNBkXfiN~)R>cfL?YN-0{RN0EjZ>OO|{0M#%@nc+&K
z`6t9$zGj?g5=it=G-}mW{!bVn@5dhrPUoS!j!pB3uOHltf)4&S(gPfsG!Ii+_7=mZ
z%;Mk<x>Lb_t&}GAtYlZCD#*CI9(9s=IDAj9g>UK!(6t+i@5f)AmN$-YIW+N?`#_DG
zjR0N^L5!mYP@IZwl(0;?$_sLq?tN<?=#aw->YkRUH$?P&$m&(Dc(a9jTW#rj5)4b@
zDfaagIfZQq6&5E$#&h?2{<c@LL7HQf=MgCm!ph(1FpoWv^0(MFMG=zRGcYyOaMuJ_
zx|t4Cz;!Ynm~`;J8R+UOB97$39ApA%A`Gy@8Gt=5GMiUCWWQ-F>XsV5oMY=vnh0zP
zs%xRZj@nO|i>x{~O^vdVtjOQ3CWODXqhcCE)TuX(iov9lZqu-mng-qIsy>@3BPJ32
z=h1QeU5NE<xirCwqX=L9K*kh~7<i2ST;8^W&lGb_OM7&N-kS>Ic%EJ@W7}X&)O#>$
zgyv3QActuym3wT;D4Eb@ACVKJ|5gmq(2J^xu`kRkt$u30d$0G-B)!M?GhsPn?VJ<E
zuxmbfB`b(<Y`b9Ge*RwLst9uEAs35h=u;ojk|1)$E8w5+vNd%pgeGjf#@wK1GSBq-
zdaxBnKaAc)S3r>FQ8jFc7;rC!oF#G{qWt0NS=dNucf8jaAe1nzJ|qTm1!cvNu=uf#
zbnI9Ae!Dug*C#)TR7~efYXRv(WkKV{BJ0x5TUR=@*J0egfd=t@f^E!&BW*tpcx;%0
zi--WNm-auSgfC+~*0WhfkAVSe#82q*(7xCCp3VBiDxlX^^*XbHH)JI$pCd_tY2&CB
zB)hj5i3cC0u=!8i0ES`7Sy{a_;;7T?WIaMl`Z3`P;VR-RZw>nk#<5n(3w*T-knxx#
zuK1g;Q9Ip~%OFhDxs$Y1$_hl;y2`Xu-(GZyMo)aUaL$)Oqso+*In}g$;wBm*en>?V
zY|m|L!o_r!NP#_YM?;HBd=$p;<s>R%5sRb6Ii*2b7O27=w5uz;eAW`$>|Nk^I|%Pv
z!yB7kxi<fh&3v}#6|Wvf@0UNzAd#EH(|q)e@$I>;j8SB7h`1QA%)H9H8Q$6;-;v+B
zP`hlwk_5INE(JZZA$Jc{t!M3~l-!+*Wf)Y(e88-r?~C^&$eF^?vwO*M1sW3Ch|`Te
zxc;$SuG2U7A7Q22-B8XEO~BXcq{MYhxUV;HLeoGwYb=n_bjg+bXZtbi^2G-MmpLK1
zr-j0-#AU0T#f91Uz0&>;&*~g)8+)+Rh8X2VLF7j(^f+Is>q&?sEX$350lAE^KFX3~
zwwcK>8^<phP3j{954fm_TBeZl?sH&>P9){YF=>+4@a8owg(F8}M)OI9HsAMeMQzqW
z<A{3yYSWbqvn&<!<jt`(GpF&8Np0Ws06=0&<%VqpyulU?Ef!t~^I=OC&}nQykK%#(
z^L+KAvhdBm<9^4&BL~lLKIdI@j!xL&!R{Az1k4SsM+ozZ{PrSagX@O}+IM22#l3z8
zOpq{54W;dl6&t>wXmmMSAQ@tR3uGQCfFWo-?J0Heg+6+|*MdV0BAd`N7!MZrHn`kl
z0w%$iL}#*_|7d1Fdx-1rBlboE{%;I-X-m9U8)rmk{w}9iWeUvDW`QGo3L`=_HQC>4
z$t_@TVV7bfFrWTG2)lHTk?7&Wtq5)?`oZ<YY^h4{<>5zdEx|C7<avh64a7sQ)u3*k
zhswCYHju9DRLKRo0<0B;T*!RAdnqGK8fvpT`KQprd4nElXL<2mY2)+4F}%e&jne$E
zh1)rNe+%bE7`;`dAo$g3d4I?GRW#bFZiQZLM<y;mLn0VhSlRPC(Zo{y<Y)#aFIKR*
zICXJ*ok{@m`j0NY3&mxG?st=_Dxa8CUKwBEab>}Tq^id;joVDUkAk1)`Dj=~JhRKH
zn3%iqwD5^8z5!Ull36wrG{h?Rb?iFbHM(*T?1#~GkJUVKMzGj7mW-(7+_UN!O;7(3
zOj1Y?@BmM{+ue8a@p@{cQ*$aCt1-POp|-9yt`1?(g<7}0u*1OT7M+%Pp&)&*AA^+l
z+fv*F=-UvqN+_J;Cri{9OeH$7Lo<2d&nUeBc{L75uJ>7U4Zm9PFYAP|iv+}VpS<$K
zU8KC{LTPe73}VrrO5r<Qxh;Jl3CkR(!Q9(o1vyGVHmNX0Eqr0&W=6cccDP!P?g^)F
zFePTbc3L5|hLPd;T+^^`bfpOTw$~kmeJ(C@q7Jc$q$&N7p4iwqbfcCM%!v2zXkn<(
zHnTygPO}42;RwYJ_r3`q0k}%3^ERVaiuAc88$%qPIhHB7Le)oF0MvSxk%y)RT1PU<
z_cilPP*ytpQd)ospnm0*EOh-SFAx(=xypqL6RaEf#Z`Did^f;afZS?VVZ#8t2s|k3
zX_zA=XC5_dLAD55X3o#E=Aa!u*naVE_+f-ms!3N)1sXggBquW3LV8zg{Fr-Uf4H<3
zsN;%t%)Z8{XOuxhmF3MX=+9sN8Dxprs!2aZN7yc-_6QAf{gC1)0HaCn7IuxbRBZ=q
zoWrx}=mFNlS~7oqEgq!!ALvyoEU&B{0%q7DO}$Vdp^wBC)5a&C;>>2F+i(lp{B%)(
zLnO<qN@C{LG{^gMjGjOGm=XVzshN!3*%>C#i;RQCtgGtj&c>hJU*4DlrL)*5OAGQP
z-#4ofSIws!{tbL9!w|&yiYBj>z8TdeUPjjq9S$$?ly@_^0AtwNt2!Y%^H1w<9og){
z9E$O^`XM>o<(s_}#VOC)!H9x#3Fa-;Af*Jfjj9U1JLTW|r&MJn3fJd<Bqb3%OF8z=
zT3yX7IRDSowTES*2o|sbgsTyR#O>-nZ>i|r->D;6L`Mc;Uaq!YToAV?DJAWhE|gqz
z!$2PosyCBU7}W_eD_>&}{H|my;Z*!UyF6gZPk)o}4x;GDKsgm1St|a%a6!|bYdHa;
zHVP@Y0`CWZIwPoB`}4#$!EYN-;Va|MH-5gKw&rWk4Q}0dIUo3M2cf)tXLe4mQGB)G
z-X||NRF&ww45!AyibTGk;wUfHytFN!cOOS!?J(!JBd63?P*$rID`fL9W?D~%isig&
zVM#P^iY-#x5958kNNUjCToc_H)PhPadN%OeQ4EWC{xW6B0TNRebOCv(PWH9}&7BOw
zM0`A5$6G_|kQ%x2*J%Ymy=_Ie3Ec}+P`oR%Is}zRfm4M;YIN?`PTZvEFMQqo_k77v
zq~;ULtTsyXp5Y4n_?(B9xH!N9e8d`MzBih8sOXdjEW~35uTkJe?Tfu*)5J6yj!Z$p
zIXTXY0+S>N;WUiKU#pwcC#cTJq{P<ZO^)S=TWR=53jcEFj3m2<)!rM;y#@Ft450!F
z%5GC&(&HlQUe#>oW_K@A*>fqb))(E}UAb+sl3_nnXY;r2GRl$fcfDIZo+ARkN}di%
zvxb%NV4$Lx`_#ck;3@0ODTufcLWN2XVylaayz9cKd)Nrg0MCA?5dM|Feeou(0L5**
zz{l4G)ND#*9HP$V{n@vg$!!-;R?jVwjtD6>@LYDl8^Oq(aiXT7AJ89;iZb-WElg}_
zh4=y-<z~l4$V@xTn|`C`<RGIG>kR>uq3Kh*Z8*AjM~CD*>7DVoX&TwSA`{sB*vAeW
zgTrdI7KOzkh<Le=Ofp!gTlJ*-ucuza4%XyK1pe-DWhnFwROR*-oKqW%teGGuDI2Uy
z2zPSBa!uSW+vIeK4x*sZka?w_btFk<b7WzG<#b<FcOKK;`uSaa!9LsC`#{O&uS;Wy
zb!(YTvec0$ctHO%*}ZSmEkN%2fTEMbEQz|a9YYZID)L9HBp*oi0<k)M-TlCWkNt0Z
zzvNA~HWB@7wg?S+V@CB{28RTP=w{=)26%a|0vWiS3#S><ndj1nfUen2A;=S#D|pTg
zlLHG6dY3~8nRbBeH=E;n7UV9<Mqnswqp49^tH~LYgdshnTN?u3J!7?-Iar2c@%uA2
zA4v(S^=iRm+2E_=tfPc-cX<{04Lx8^^4Rt4pifG>E;7{anejN)X>#B8y7r^b1JpR*
zfR`WYeSF&8zG}G0?}DR`CdB&GSn#0r0gU^CJwJBDLT#=AGZBBF;f4o)x<X7=V<Oq3
zJ%{y27}JkFOIJ9nVS#XBK}`Db9~VNcs)4T66_9X;t4VjZ^v$!_S;i|!Mc}Rt{_W(a
z75l$A_aq#<Vs3|d7I)WpE{a=GcmA7PT|>0l+Gr4dIK2LJjt!CIKWjj;IBGK_RPXn`
zr6d7rBl!OZL1Ct7yLPjAB84K2A--@#I~Z~JeJg)K^xOn7w$o`jJE;ib+=j@)G9`zN
z#$rsfQ@FoGEBd$HeE29cR;7r~_fo*UN(r3U%j!b7<S>=6uC%&(sgyNh`hj?+48U0N
za-nkGoOs$M@Fx-|k`n2FDm|;ViLEwE;_WEiuOV=m%upk$ip)2AQND;jwk1t>kdz#Z
z7xwhVeBL|h01%R>Jxht4NjNSX%668Q<nJj@h@a$hNdAfeBc{mp5%g%<VWoxYRNV3q
z-|J~!UAjz?r_-k*zDU9GTYwf9j*1Tgc{BrJS6BK54+yF+AGo?|SaUeKM3m-@578k{
zku(DrIJzLZMXKmiMn=0fXUz%q!{a4vklPkGl5Y+<%L_b(7uG;fh5ow!@F+Qb7%q?p
zDUoS}O-H}ZVeTD@lxo-}PZ?E?B&QTyRY~-LearEUIHT7W!HE@&KR0Gk^yZ@O8LyR7
zerJe`1&TKpf_u#Y2qWkgox&N}_~~HWlMlHdR?YgIh7ARC9I(2ye*H_2f2vB8?DWA>
zBpI(hB$Hr`a<bn&5&;_Bx!9>c8e)#|#ZEniZ0-x(&C6kghk7Kl^naYUTWAIERkPf%
zoiJpo6vb}Vw@AHC`V|A)rATw6wK)Ck$EH9TVbk`5E`I1_hV2nMI&9RR(#;)5oJA{%
z8tM)($lGWdNv3=Gy^d4sGYJO^th9@otQh#O7i+m}nkOoL8epdZ??3XS<}JL3&9Bj)
zL=D^u;oEq{PW}Fd%c&<tK-Wd3a_5Bo1LrXK#6jDB1IK{Mv{uyl#SLo9Ni?xBl42~H
zh&VG5M6F6K+<v@AE&^8W&s=G*a)CA>Gld)k%NF)z<c*gqArPVeOo%u1vJ8>d8IH)~
z5qLYhggAE;+ocRQG2A&Vi8dDl6uQJ9gUsHnY9%th<*Pv)FzIKcI<iMo@%-M7t3p%x
zA;$0x8A0aF)=@8n34}(&1WX1RV1jX*{mAGFK@z2xi?sR$)vl54tk|qlY_CVx@zBOB
zYZPSq0xXXC#aqh($-Sc&-~t^K0#&fc6F40A-b=A23LvP~PyetdM}G!EQ}NFgf)k@6
z?5vltF<cK?#XZa;_Id2udE62-+rfLJeXUXq-WL*p3vh|p)VV$)JFc;;HrIXNgNqav
z9L}0)r0+3TKrGm<)YDR={|9Dww1rv0e%vSBT0ewID~lv$dDQSE{RL570E<MvJw{u)
zI1gOq$54L|Tl7X?`&OA8YT`Fo_GPzeyGM!cp{MLo3bZV=Hn!=S?c(w<Y*(Py8VVa=
zvq$$qXO&;O-eu>Q3}0BtC$K5m3L2Fwo!NvvpzHwjE5g6p2EfWAoerH74Wj40xg?}T
z&`;@X%D6cPiwSQE^rft~o2ITZq79N5cq|_73Po}TO}X=$fI>a|(H`q^css4w84}%{
z7VFMPYIoG9M3?`F>Do6yp+Jb@Uss^oh(BA4#iX2S<}7oC5n!s*pr^1ZX`AGLv<+?!
z%?fNT;r7lV4YcvZxe(dla{SWoo3R^Z@<!L;C^r)Bb5q~aS7=D?dQOT&!R&S%#4ogc
zOi6_G1-YCEGD;hot?6-LLVAo=&x0%zN;>MTjLDj7Cz2*Y9<$fMqaYoDzYQBJ&r*mP
zsY0A_*LeEhu0`3TEwE=+-zz76ENcxF1Ca&n!*7h^9l!XA>*-}S(3T63RaFwKJ5=NJ
zk!6^#t4t({LLO7Xy$%LzUf;3OP{HtyF;n&&<s{FMqL2X-*8sOU52F2Kv_1jMCe&jo
z)2msQaE!9|nA84rXq>dlvVaI#iP&Ek1lqG?wS5>9?o3%gKB0O87!|46oBn`PL)dK0
z<RrsM(1bsQI)uSUc;o4FER?Y<m*;Rj8~5qCIvnrvSi8e1h2}XD?JZG9K}BXX>Z$t0
zjX54+8d#4e?gQSaulW(`pDAkqPyCgcx{xim+{c90XXsn^pbJfF;B}WxBQpTJg;q!R
zSmU5y5IhH;?6+LJ3LL{8Vbpni$aW-nyBaQ~&^=v>m#Nv@){daB=qg+FGm>V8#5+AS
z%p^ng;(mXir(4h5_NapTP9vU$%-^6%@~rnAjX4}Vn3@!tXn#vy`6?*00^9@lbqOWy
zw<X>s-%WmqBqvCdW)KflXjO5ek4thvj;&%ftDBAGctp$SKHOX~?^8Mu%f>v+MQebX
zUtm)(eN;_E9*8r6udm<P_mlJ`1ZBA5D0W<Z6A>*svF0mq<DSaO!!vHcfPXm`%_BDm
zMJOnpdl}gtA@|ptgi=QisljhWoI=qb))7IBP-`F5PRy@1_nt+K!$$tuB1jxS=vge0
zHd+J@0?M(DwS=%>8D-rbm{q6X^LEEBS9H%*x3jCCb$)q-2cQ({Z0;t2;2#77X-|)D
zPw4Fm8wz2-!+gnb{H3Q=dkOrg7VmfE{Vro)QKFLvHycGE{G?!9SjX4`W=YnOrWBM{
zU>LBQVtnIpMfhx}Ohj>fJN(|{984|YoNm>JkW%!ER2A$#4XYAoWtOctn)ljlvDZcH
z%nldYjoMOerI3Fc66}opTo)wwZ5)#gWvcXWqRI3oBQ(|8;?HkB5&xbtv5KLE@D_Pa
zZYEL(O$mnq1u>Pb#hjX-Vk0$&*MDywvZV26qkqEqpBYzC<{ny^eSCbV`r5xuvHdh0
zm70#Y7Fc`}XdZS4Z}Av}>*={}uw<khQOrJ46^I7<XgxR#XZmE!!LPY5{OkoYC7M^X
zatT;*opQejV&Ont%ce6E=4m|9G;9QSxl(mk?VwD7RbUwYsjLc3ILyA0ud^K-R|iXS
zGA7q=hEPj?WM@uizd*Jmpq~8O30W@Q<}stedH%D6wMK(FCJdKUA)w(9<;WRX-XyH}
zrJ|(GnvRw3YtKy5FKP>B>370g(^vcT7D)Agsu2zM(`Dn{ww@hohi&|2f+cmIl8*bF
z0}Oltg_TBR$fInSI<;%VMgIjIh04>Gg~YKw7ot#%2CH6h#u$l|b}aMI<ON`HSAQ6Z
z^F<Fw^X*`9jV&I?+z_)UB38;W+MGnmLCW(dFn=eVMn$S4Vm=vyMDU3b0toy8%9b%u
zx22aEA<763so5B}XxKreBLc%I6sI@|16hGge*TXnb81J{U(zMSW9m3?ck4wKQezXT
zvwYSmV!1yw5}I|gXHlfm`K+Z|HYsldzW~97s@}<y-Vz~R0OP8Hua7tlO}N1yI}Vl6
z?PLQ7>sJzv+dw=t*IRv_es_|g?PcTSY4i94`t|x`8;DKMDAt;r2X@PQQe~~=ZELJ2
zE~e`eNhw#mg4dz);|k%d2^MZnZsYdpKXf%HY7o5%n}&&oI=5@(eB=Z?AO?stk8P5e
z$!?Rq^lW*v5=6MUtc=^F{rq)!`!_pdhH{U0hMvXjD0XZP=?x;-7-w`cpQaahT+a0)
zuL74x0Y;`-@EX184_V|OYej<#4Eu7@w6!jHNjXyQu(!0zY+<@OI+UKGj8dRR^UmiU
z><$=mSZ3?b`)S6n<dJ^h%*l4{5R1(B6at#TG+awN*^o&nZZ_{>XU7Z9+sFS|O&YL=
zMSKIKN#DVW9JCTo>XzTCRIYhyim390$O4oiJzK>-w|49RJNcfUg28TlWHJ4fO*-3y
zk^^l369*Rn9KD>d1qSfgVySKBB&kW(RO)Jf1B-rCSbusWm=8@!W3eLv4|W7L%E-8)
zeE#D%z$pDeu)#bvHaNhnF{-rx5!joPC~^Ov$!AMd&ge%IOhbcl2veuAMS6cT(d^M)
z;mf#pAj#S?PrkRX(LL+7B)JtinOseJRcpABbb~noZtUS^xfIyH&2ZqtPU2y2x-vd4
zvrgy7nS_orwhR!M%9HeGko;Eo%A5+JR^^o_oS`q3siv8?Lk8C^t4kkoZA&wl|FfbE
z--<gKqrQu7rU@moBn<K(jk3a6k{&iW?U_{7!_qxXk;k&z>-qQq*SCFs8dsN#bbJN!
zg|DV4db&0A-^((l!m4btn?yan?6P){#*vDy@HwK4I0P7Ctiqc}Dy9mIxBJDgi(ac=
z!n0FkAfD2yS>;6?#w;_=(O*x7r7h6rG_noOn&*j(+cQ@XYL{Y-&a>)7sVmcs^PztJ
z=AQuN_t-2vJP58OAV7p7%hH5$cEGzajbYy(Re)VTTX;%JNNEkZmD%ls4_0v0a!u>L
zzIxME8`r|p>u8mJV)U)2(wGA6th8{-Gzd$G^SdKZ55a2>)W`65f4K(q{t;bQ+AO|o
zfXiOX4*UGM>sozVxam6xwR8TySJvaUZNRs?x?OFWk?+<(&|@S3xw7Rk>Pw!AQSj&h
z%V?rs`!y|Et$I-o-OaP5rr{3*cxlQ?{8+vc3-YYBkACoXb?WmsbrOp>%r@EQX(75D
zkt0=ih4Y;aiAsFiB7OG!pF!ZK<L-f7KyOt*uak7X?}uq~L{cjJ`>V1@;1fj^z#HOQ
zFv-cCw<^U7rD|d3iX6y_MUb!&g-{t?hTpo}_z?}Dy9{|xaA7EF3iKtQ{oLfGvF**D
z{Y4>;zhOZ@#{!)2xg+=J`b(L|?hRr<a3`wrO4YHtQLVIgbHT3VfO7DA<*s&|^!OlF
zV_TC{{9x_G&n8=&vVRZlp2jdVivg+a<ZXe;!?0SzPtZDhwgqM8!^MP+EIsW=A<O&d
zdoPM-(dcicE2ZFPcR0Lr$e|%nnWn7PjWZ`s7s^GFZu!RB!2aZ2f$-W8C^%vB@h_?b
zvrU0bsRLoQH6X>Z9ChOZ)zE#hpNY?I&6<bnKF4F?uzbu=?>40jnA*!p91U@SV8K{O
zraNwdzek4pc7=c<5hQc<MQI;z)`iR(<|asKgxlYxtP2M}6Bo2r_%IaKeD%C1%|}ys
zB}M0cS_jY>7pO2`jFyb7D!j&Dk4xFdCkz}(4qe<F!;^HPLWo@SB)>vWs#I^?`ajTg
z%_5KSw9w{x_!76fdHjsB&Vbb}=Rl*2>4ePHZZ;s|a*;>Q{iEbhyhU}Xo-`z`f^i>k
zpO4BeBL!k}M~NRU$|_4Z8RGWp3Q~Bd?XP>Ot`Sqfy4f{DXPlsKXRmIVJ*(IJbDObq
z`6<K8U@OJBo|j)Gf(vm?>QxaL8Qy1oyH?LTNHj>ppWz4Qo|Nm^;xgShP3glk^vo4M
zXr7Qxp@%$94YQ)G?27y;9*hkuUuP@=9>THV4M5reDb6a*ijaj_PB?)6A#MOtt_l(I
z`LwQ@Lq3>o4y4^0S>5yhUO0u8sC_!>tQ8ynL3>cC;od+hWTy4Fi|FI(?v#VH@^7+v
z2x>(YZ*8s($S5H5&iwMEfg`V=k6nMrh#A^90S=gxcgDomr9zB>%`+B!$oBgO%^e8e
zF~<ff;jn990f!;D!#g<A0Ywqg!x_5vROv+HevuwU_qI56y`72<9`c!JbPDZa*j7Hp
z=G)4hq`9Ypl04tK9-@BgcLM4{WoTQPOu>fX#G$FwxA1rmXHZJX&W~q|SSMtSE(ObV
zm}H4o!jnfvN#%CF>&W6ZphNzP9iZIh&ZNgk_}!Dwd%XSaOAO9(m}eaM5fO6@oQ<!Z
z&9vR`mfefu?WxPP_zqoM?8hRrC!HNFCgBVGSb%%cLMn;8I<I!%6m-rcyRc1kAVQe|
z8-2&a`0o`6kQ<Y@3&mx}pP+;%OFE7c!U!847B%7(;(i&6gS?Jf{BFm;hu}1#1o3xs
z!vS$=0ze=ngZYxnqwA?&V^YO>u#_D=dco)ogw#S#I%C_1oXpDn_S%ClFA(X;c2J->
z9M0G)dV}!{HN^f&sRmRYDnF5h$=eF}YcbFVxITXKbmA76!>EKQTU~&eUobH7tiqd~
z5`~3_{n0=Znlv>(&I;DAhm}}22R1>kzQ%P_21&rxqiFlRwoXnEhtDxK12{DGq_GT<
z(Dza*i?!^iY;wwRo#$>etrA?S=$~RYokIWw<9?8rTUxZ2J2S!H{hoa!)X(FD4n@&3
z_hMj{_TsuzI6)v|fZhV`I-a7JWhb-nMpynM?NuqLbzL$|e_=ZnJVCi>b-Mj!JJT<v
zY1}jBix3ptla)tdJ10QA9tOd~pf}>Gmjz1_yq8ylghH3*V=(8NYHrcYbOhu+sj+*b
z^#RPWS%OA5Y$--;aH9wP=b<}ZP5M(;PT#x$tWpr;eMs%uqiW|JO2cmP><<06__(;^
zbfXF_XX5{}R#r;oH-H`sT;oVth2uXsW>GQ=Lm7VTPtGNm=ibJhS|)K3c!`$|itobh
ztl5s!lk5DDf$U$rq~UM}8Ejq>t|e)YB1kSt;Q$7qzN?_hfsr*(b{JP|0BbfUwhYq&
zY6XKlS(bjiv5S-DD1OqdB{_cS|BAV;u3u4QXy+A+x6Nb9Ko+9^j@ZssLVfZq8dkVV
z4i34})c2bZ1!1IOSsncNeczu>DhE&8^8sUzpq;J9u^_H$4-}S`40%UyMDW`6`f({;
z=-O4q;LXjsM0PQ?W>~>ZStK%whEx@E<D@kUlo1daOP?OsC3YA2&Ao$6;kb%b3u9(b
z2i@4rxd)3hM3gS#X!dKjUM@e0el8R~W*Z=}yZ=31Osm8SCqHt>5yKOb92=z{{@mj7
z>U}6ky4x1Tw&VCFa57G_@p%Qlc&*J7rTIr5?f3^KqCr1onJX1cz@oyj<y_W*GUhv3
zpy6Mx#L&U^iya3vIT?-+bUqUVgsGwrrD2k&kV3=vxB8M^87L>_M?jTMcT>zNdyaak
z8w7waW7nl+DgAC?aw%tO1<wyT0^&b&A6_tIj*}e&wybd^z7tQ8$p?{z2^>QBi))GM
zCI!L0jy#^0>5&h*dn~yE|NSW}Nny)X@+!{DZ&A*==e_W^D7=$fxzURX%cG0NeHt@I
zPa%f3lv$PZ*g7K@ciPfRUkC)|S;Y5K1K%6$tvpZ=T`NcMvhQ;NajbfPi*yW55Wi<p
z8+utMLpup)P)j5<sIm%f^B<?L=y-#(&b#H#D;(58ZmFdd=`lEkM>)<MJjRhph=!MP
z>}SLAaJS#{E_#Qu1kZLxRZp5&3uly`8*Ysnft9mTmfwVY3sxiL9eaV`%L@<&oBf!H
z)%9aJ#G*!(vV`N+Y(*Yq$cewi*HN*7&2&ilTFoMvMnjDtQD+jf&-wP}6k*ocn~XiX
z=RS2~C4M%07}|})=gB41+4`TQ_FFGoHStT=p`;F!L8{<(2*G~_)r#%%EQwW0<{-9J
z*Mptqw-Xtmy#+15q~RdD0biuBzLSw_9(bbHp*niB1ptS4s~}&w`Aa1`Gn5dQ%mHhO
z!bR5$?3m`C!zXGOg>d1vTUKx7wF@Sh8fcw$zlJ9L12OAB_Z^hqZJTO&s56&FbB8C{
z%4&V@li_QTt0^A#x=IhE>RLjkDm#?P{fs*F-w&wb#;~5d&Y&m?Yh!{EL$rm*#2*k5
zH97YM?Lgu~pH-;o4G!EZCDvCqVAPx@$U843iQf#BUQb+7edAwj1}(ejRvrdg@hyfI
zD){~u-0i?c*??wUh-x^tY0TuILQsmIEX>T7kF=lIXo$NWd?etBTV5WpMW(-jo=<i5
zVH{AnKpJY0>!ad1mqVTFoW>URKZ4Q|_7l?XyH#ODV8nBR<w$eT^iQ>^#0E6V5@#x+
z!!h+4Z?&=*j%jJSljA`<J3(99q}d>eU%&m~>euJYox*zB`g8d^5l*HH!|r1V3zVv#
z1?@0d-eM50*ND4_K7*Sj7oDZ~Cv>f0zV%mxo`hkaPxrHuAtZ~?p^F$5qXkD|vY(X_
z;lFO26{J=mp_D7gYXHC&Msu{73(gwU!Ri$Wq))j#cJ*U8;b@!Wa8Ij1H#_eGb)X+G
a^<cMPiS2hE2KAT#`1=oICgiDw?fZ*|<6k=f

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_timing_adapter_fifo8.v
new file mode 100644
index 0000000000000000000000000000000000000000..de7079a1ff4c6dbcc344dae893cf58da9da5aa13
GIT binary patch
literal 12160
zcmV-`FMrUB6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj!OiS|(+-e_kzWL&;-J-Eh_?)&I
zhNJU9vD6?)zR&{3dz45xk5#cZb~=^b$|XngaSeVL!9+HDagOUruZ~(E#?HU}yV?!s
zyiXiQ@F2Q&c6z&TD6X_(5u1YgJ0+tGudpD<l#{6G@UW#FVI19hfDD|j+xf*;ul(%X
zdXr*))!$YWGA|Lp_R;+uw;i>5npC^Ujh<`+)qCUVvIzZn2>C2(cw=!ov5+s9MbCGn
zY(uk0=V+pdcjn7U)u={%C2K!)48|WqB^F2THIVQe1ZmtlQ%}MHdF1J!SeqLlR<`Vh
zA3M)o@YnhH69nuy`r!(z!YOsQM9WwHcsXZpC9GIguWS7vAg3~8<ouqr+)?-CG>unR
zJ@Cw$E-QsmJ?meWjUm^me;O5gt7qg{<X%$#iC-d&TiL53qtgx<nY|9%+=$|!dq87V
za{;tR{OHZce62zrFEKIM)S7A<MOGqA={_*`-fZ@jUcB?c=OgcU;A>LXVJEKES4GpE
zv<X1xpMNODHX49{<AUu6VXbJ7)L})N?<mjH%}t#y&7T#qY?%n#x~XoGKhhtm)+7E$
zqxG6nKipl9b~(T577gcIf|sQQn>XS;m?52RT+C2EYGIDWKFFYv8AjYMr5CNC|M(9T
z0yESZFX}cG+viH$#L;c^k1#5xg_nJU?ziImaR1jE`;S99v#V_mIw)zVE-U>rqWT;*
zY<3N_b&;E88p@RB2ASfZnYe*e_nupSug^NdJcI!zSX-8lrMk(gt+V#ckGV#DggX)J
zz->nmYOyQ>;OG90WRUEHdh$Kn$+fvXv(~jZOK8^IBYG+S$wZ9e+cTdauM@UCfe)8f
z!3|R5bZ*n|ur4i}1KeuQjSX3B$qZwj4j1<L%V=jF4{)eS6l{=V4=Je!^lZ)BPgQIS
zC7Q3CHcO0z8sX2g?9As`7+<nv+;GO^=ZB8s%Ka^uc_BzEv5)c#(5oxW{T<$XWF#g|
zUFg^o2X8g7BL_?@2`u^Hx-4=?`}m!3X|+&W&B)xjAKpO1i45JI?8_{LO!>Hxx>47h
z)Gl2)F%%Rm&-UolE1etQ3g4Hf*!`yWwG9EvHacT7NCipC^f^Mvs8zkAl5#G^@rq=}
zHyW}D>M6{!;%57cL5E@WZ;y005c*mj*fY_0j$Zlw_kF@^>i!H?O5chaT8$(Qz4Qvy
zR_nAfcBymCSiH+XDop^Q&~A0KXR!=8;sma?tpH317s<LKwTQkxI+*=&)3XUjIjo$W
zmr53J_tTa}r0WDs2wgd8k79#$2K~n2U*xUwBsnG}NL}G;l?=pYWY1`KdBa_cMYNE(
z_TW1!hTiX{grNcnH%OUt&}dJfD{uS6Rwb?W6?^GMZ>dz>NgT<pqAwy&k{RXM@H@Ac
z9oNN=ft<gK-7gCeaV9D&!*Ag%Pr)G6b8WJ8UCrQcQFYG@TZ|mq%Wp|ZgCumxg?!d2
z>%_c20chNu0PAsIiJIEhu{Qkksc!M~|AVZLoz-y+_975C;+j2MU4$O>gM#t5`!mpO
zwB`YXtKt^tJrq;tJ!$~NDtO6}+H_VY$5g#IG|+Z@mD#DlGy+C3W%;gnighsAP^dBU
zc>Iv)`dTy2XEd$j@U!Cy>`iD#+HAX5dTo`6q%ov4%#k-kz~P>AFDvB%{f%{w)BlN?
z;*tot8EwIsYn;MrE)qowbDc*HT~Nn_ND{-Mb8Fzqe%0THim`4(>&q%0^dXEO&(mAg
zp`uk_8htXJKx08yY`!;|!{M#tAGi)<`C@-jy?j`iB_Ubei6L#e$X)mo+XsuRU2gBq
zVoaHoDFf7Yd_Htow#u@IL*BaSWefDB;;F6Ij>V)}c?p|3@?)HfS7bk`!IB)Vwj2Rt
zb{5j0Xhs4ZhE{rRDl+^=tLDo_pR!9?L1p#G#(U51*5^BsOHX2aC$)m_sO>GTni~8S
zTg-|L0SGhhQ3No+`l_d3J;3~^SpW0VWi;f@_|oU1hnh4Ui$a+8bVjH#JNx^u@j2%F
zlc_401@s_;I_FTcm34%yCm7tptm#+L>i%O_g_hireNg9wXm4FA6dv7kI_fEkV!o>*
z4GFJS>SGVPpnPuv$_W#5vco4CpJKf>F+;Kdd4*nezFvCvaTt_Sg?V(+jwrmuTCtPw
zQWFQ>&K-T<fD;pA&~2RjyE_&&zf-f5UiTCVW!0lTT(<+tE=yZf96`HOlXUGyoZHXZ
z?w<cWCH$j<v%dLAHg^WFpbALcmY=Sh!~-Ds0bh)(#UqN|3!dR7Fc+g1b2=i?P=F$^
zY0WYD?0kLKNPXPR9I}Y{3|WNzOF_K8PTi#9%{&Y%!Kr?6OJyh5=?odY+!1T?7>le5
z7>~5S7buQ#Al^4@no#*4{Jgt_e>Kjaz0ZPGjp@44Qo)x#qh0E$R{z1e|EHTho_@s5
z!OL`D=4=c;(QJ#FTTtHPRFe;sXr!KEr+|hwgZ~^00zem==99ONz95Im`l2hvkDzVL
zOrnvNt=MLOTi7FkKPMmiC4H}CD3{(y_N`o}Iv^bz?~(p5QPq`~Ni*w;GfxxRnBw^7
ztLsNrW_)$|^1a`3jbY7jO$z^sN=KCg=N9S!$^>$YqTCQHr&R|5MQjIU1nCyM#I@X7
z9-~z01k8`y`Zi?Ha0Nd#_NGqn(F_?pcD5Y;cb2nYpyY73!%|pt746tXh4WytGw7NN
zV&@}4V{#*ADM4EaK7de^;1ra(Z`cBysBW*HSuIc$CFZlEQn!ARg*>8{Ew-T$rLMD)
zf@$d%X7**QG>15prm1};o}p2WB-_-WbR<WJ`k0B#iXO(|Eoy4&fGmk2@42g>k<4)D
zCEe-;Y%j_VaajhQ;@K@j`w(Xp?`5=P8pl@laQ2B^zT3ti`^nB*mXT!q6g5^1#ajAY
z(7XN6Z&!pj8}AE{4~v~p&5Biw_#LLX)1K@Diitxn$W7@E5-O*{Qh8?+7fM-+rSGce
zm~f|&!t)31Jj`Gyw;@Ai|B|wsi|e1j8{qZbxxf@eQuf)YGYryZ4#X&i$<jdnil2Gg
z%Wv6p#ukk9%J{nW^&PRp@b1eIo?Q$V>*3W4w5Vj=J>w?LarQz^&8jplwp~uva!ePM
zr(EDhAs_kIm)RFx8=0o;aJdVR8YzhMN-C+ZFISJSJvkh_!4T#vN<e3}^a^LH>Gsj>
zT{5NJv$tue!T&u!IO-v9Z=M`&bGgtNW~leV%AAS+c~m*noS+3*-?18b^HL*sZI~<{
zwE|ol#&>kUXAflY>P+JJ1=~lb-mM|RE()6jkpdn*&tmDTXX?Ovu8VFz-mW@}6QsCX
z=<4(u1sVtyLhqNf@eCc5Q((P$(MNHiy@=0!;Ze}m-ZWTPS}4hRCe)@DWdzjOEtlma
zct(or-OUES#5Yg;r#@1naLUv!1DUID;FqOADrFxQQNQf1)35da@3QPL>n+`Q8CGkU
zmcu3QLPSEt!#D^+JSTmX%zFJ|4i0`un%;8yNra=+sv?@-i0YzcL(9pSDXofNHN2r~
z@%2J-_cQ*Wt_{-!gM<=UwS=o23S6$A)2@UMEGtS8C<GEF6}%U~nrsYAv^WVHXlJ=r
z_oi_q9t9=svGZUmj~tm_2K*8JROT5AvNTDZVM)X47vBezpzdVg{$_Zex1QT(3V@Ub
zBywb)cOlf|xAw{Fgk*lYAGUyRX_eO7x$LFecpmfVuQ%TD)S=l@Ko|nBF`2Uf<JfsQ
z^pb}k9cg6rV=yA3Qv+$nQ*T|#)+A6!AU!^EhqrxTJMg<iyd+OC#2mHsCMst^T|)MC
zNUz=wj|4JZgw{uiQg+323S7M?-(keEUbg1c4Efy~e<=~1QT`qnYhKD8{SXVmzF<Nw
z5AI0@3yc)AM5?znnq;ecJOv`ysPbK91NLqBc!_9j8o+`V11}sMpf@6YA_?a3vDwri
zsDbPpZjaP@sA}_#HXY0)uQb%`{5ZbY=%Q*{jiuAUt|drKwE^PV;dGdMdISj~Y;Ky{
zO%Z7^8@%7-icg*;^rU$?%rlMOK)hyc;Re7l?Av!~Jhx%r#!~j%XNr3m7n?|NozqP+
zv#EVy7j@%%4?&YdKh@)rqBgfajBmMrn_Sj-Qv8p^e7_W;&Dkr+|C<#vX#L4WW19(K
zMEmFDr-;CcY|%#T&57aWSJNfTcQ3T?n)vzGLrd3&DiYh72*TFAM23O3d2U+Y{W1O4
zx}LeaRmUw1ig#eqDuLVuIPS)IfpQ=wgE{f_P9>aY7u*^3lP;N#n+VrYWPvP-JT@N!
z0H||8eM-f$nX#7+G8{C;#4tKR=M2;$fN3wao`q*$iAne9rmY_Zv@^svHA~gV6qtPH
z^@kGQZ5GlPu}b!IBcPW36cI|p!!J7Sg_L4{i47Ie0Uv+evlsg1Es!Ra>%bQ+RzN5J
zGXO;vz8S_a3vpF3r;_8Lnf%%bt+IatCpw)xsn~Qa!L-*C>7SAq3nWV(76u#{{Iz}~
zA4?q?jC>iXlLMgH@2sD7v`uDC(^#BnHx3Sb3DbrcfIt03l8M(ln2eU};H2OG$bku}
zU(iKG`17N3b9g;80j+`x^xigN<A?3zLyDHY=viRo328Q`os^dPTLRcW7CSBn{MeW4
z=NYr1Hh=LP<IfVVi{rhqU82G5E&Ap@aS`IxXk(&Fmn`-+wH9-qfyXd)l7}#;VN)Mv
z&^G}p2;3wYNqrqMN!Z^G7Fz_i-U^wGRhBk9T$B@?I0tV)>Lak2hY=IOq*~RD!N;e>
zV`YUrFAwpF%P#*^wY9$CtB%@+_+K!9yD6Z5XXEVYBD~NtCjU`XT!=qw7!2>Gzfp3=
zfG7#ROsUx-{y=YUzA;u%mD#PU?-v~JoPM<GMpAMmfMMC_2RMlN{uO5RT%Ma?`<_pj
zWf;VqOe4j=YwOl5;poA2(GW7EZ<q>C(Ie{q2C46Oo^VW<PE6|8a9N;z5Gy%}j<N9{
zMj~-bciZd<$z}KVKkaM&4^hEcA{v3{{=x2cbhrmFoG^zOI&Va3eo%`K#hWVRkD+O>
zQN)J~$%Ma3xsSp;>%=&Bzu?-S_;n{h*)Ui`Dg;LKK<>DQTW=@D&pRG~L6ju!);;P1
zRp%v-3WLLjG%%@wKFwCiex}{8r`<oaVx<Y6ygGAO!NIC2JjBny;j~Ctbw+N8aL~vl
zbe~44fRenlc9FjB_7*BAC9gLTcY%EBH!>)_kByQ{i-$fIFp3t0w^^4pYM+UYA<JDZ
zj4_>2_K((3%L^NEK+<*ebvz*A-!eS<C{wE<gp0;z<3Q=iWHc0}R~A<6Cn4L%GMOr*
zQ3gQTwF|Ub)!%FTneuWL=ABDW6CapB-n^lWwE|Bfd(?`ocGeV}=HC&q6izDF#Sl?^
zyn8%k{#i`~|Lu9dv6p_arzL<>N@lVKJ~(!O_aTO^f33Ay?v;C4Ig(|c>>Y>U`UF<!
zg8A6ejmPY;b>|s7nLfA~CAIG=GS}XYdLKHL`3kULBXHZoWEtlviV?8Ojv7>=a3~%6
zVXO)6pqb*nonPI0rmphpO$=zq-B`rq);^F}X$GN9ocAFGv~GsPV-Fa(#^X56;MZib
zAm2N>tdPZ27p?=UEb0p-?GGwJKd)C2_f=c311|nr8vLqDtn33<wj{5_smsmBp+%|$
z?h%YoB*1K1JXyK*M0q9=IS*f~H>UYqcY6q;&~cN!%XChgDR=m^q=bpOy3iQ#$Zk@p
zjgWNMpF7|6pKXuGC=p%-<-Q1&iXaH-kI6h<`d}PG%*6NQN4m+6)xexamzeXZI?Njy
zkn8x~DCG5lbZv7Z?7XuUtL9BUR?%TFcF`v1n_Ci6J_4<hKih^yfmMp?_+lIbfl#C=
zFX)>JcWS)qK)OlVrW=8H;%xtK?=$RvEFI5~+5n~47o<>3p80@H{<pH#Pnwtqguwgu
ztbYVc%2U;dA@5E8Dl8UVEdv_rN4H1`N22#Z3D1o33|(2rHW0zwBc!yCxWML|q@Sjj
zO4O=s&GMC!dap;{Jzsus__eLkzwPSCF(G{RrulM#cVoD&pYu)bt$&3ZezsXj77>JL
zE}E&eTEn<U!xOjf7PS9WuAxKYXLxk^tzSHmr{VbxA9Nq(AF_C_x7dV97n#VpuM976
zn7|6H3;zTW3y+A&L~6OmK9*fj0bz=EV`)&(&L<b)oMXi8-J?(0(i*tx4ACiuxb)~I
z9Z%)Y4t_mq6`ua(!zkf(^}S!%<W7=9<3;#Mhw8c`%S^_ywtUSYORgoGLrq!gTp?m7
zYgjfV&w#Viud%QC|7omf*6QmPr1XgL$t@_VGB;M;{kXg{WtsHaTRWq8`fuo@I)OJH
zhaw&GD%4Ui?yG(&NQElFEfYC(h)vuU59p<K-1_OS9jJ{@yUx$wB=Uy5K%kvdA?TM9
zp5Z4HcK&PwkBG>UA->SgT+oNel8J64XfrxDo%-z7+{{z&_Q4V|oqf0yV|&zb%$7`E
z1c4zaEy8UWFu|}u3dx-$E|=PXeX`JW8gw*(>8&YkaZJyHU6ClW-%e+RObCPvKi`{e
z+*ax9t`?0M+bH174jT5=z^V@fvTXYQs0lH;v*H3mcspcTj$*VxjA&(tcVf-U+N-2$
zuXz4J*l(M{X{Pi(2@^k>JT22I=XQyHH5`_gm?n6)zBJa<-hEx@qwh%ODWQMC-gVv~
zcw4ILG<1w!kl2d%96?Cgl5Q@{D=G`q#g}U+u>rg2e!mrvx=Vb8e@}~$BI^}WaT!jX
zyL5rhUrz->T_xO-8|a?PA`owCX7MH+h$C$>&1ihfc3E+{vxto@=ma?Nc@N-|+A%iL
zSTYHDpUZMfPI&4SWW>Xq<VEeu=~)lMP^Sa2o={@XBH&)-s^DK{`%M#yJe+f5;bI;K
zv9IE=-+aShL0;&-yRmI^kx#P?$XJa(Ns!%ug7K2uTXgYw!t_C8x8N9fOj*$l{IqiK
z#kgpqegIS@zY1F<_tx!5whUV7chE^EBmF)Hhot>riyJUo24iaBLQLtm|0LdwUhRLJ
z>Sym(-!V`zA%f|*cuL7~*$>pTs{+T)DIz7y$^{jX`8D_r(TqmI@n38P@ic@&Dek9P
zC))G@QF_eWh-Ne}6Uf(gC84#kq}m{(8Z*v8P46W$F0eAJ_|C&1v(P@vVA@1CZv2Kw
z0PmCpADaNH9a;0DfSJPg9y})v4r6F3q#YN)=DfBq#&<r}2bsx8AIqQlLBmhj#jMgi
zhwI_m&9CocRB!6`JL3p3;klAuM}XeZOFo~xDh_l4bzDa4S{pfu`YS{>mzsT8jz@4L
zGAdK35~*iU1n6rbrW<ciJfuzG&W}{4Ch8Z%!<ohgEU$Y1=fv?r1=3YeI$z6rt@zHI
z%PfOFP0z&~kRZqNGN?lpZUF33+LD>ZZ)f(umGg78lg+gwfTfGN@kU1ysp2HqxUm5Q
zXhf&TF`QagNyBp<l8Ksi2AcAi&f!)t!ug1rwl(=HD>(Eo=0Furw3gVJOnk0^3RFSX
zs!+_}xHGlnv44d$cdcwyEa&gdqFsWF^|Vo6syc#NB2c|4MUXFMO6m4ZU3fGG<%-g{
z*|9%CuF(P+j{z*@!4U8OiSK%!4Chq}G`LvSf1&Vo{EbG|gFItq0?BZ40}QQhfYu|K
zY{QG^p#rdfo)cU#Ll0B~SG%oXnm1g^8UBHjnB49eSrB253<GJG&5vs$y57FiE8WF_
zRI$xV)CCIkd*zys0OGEkUZY5=a6^{R|EY8K9Bkt5pwHZ5)qA)H7E}G_NY)BX>I)5b
zI_p!rLC;p=5yl=fBx$-zaWv?fMdVp#{3;(vh|y;Ei4?`RUk?scWj2FI@kx*iXU;uZ
z9;-v;uv5;g`Hd#dEqil{#TGd}JvPOGm%-GfmnM{E4YQo+r7^)wx169!*~HZNpgaCK
zgO%hW*P3<H-YCaR5yMCxhlu{m@28DMPhm%s7xN{g*MVnqQSPhvvH0EZb~oS^kEL~6
zCs0|GPb#)uHdgVFN<vCAs11d&6sCY!4bZECDDe;zLqzX-Ct59Nyg2<?FaUwcjqtNm
zZeejdgDK46GM1X0Pft5Tp@i*?JpOMbTi^5E9tp+Gntj?V7kE56j74m7kNC0n>?Bjs
zf^BE^Z{s69f&*M(ybO@98h%z2n(o5oLMJChZ`f<M;|dnZ?<SV*(%OZvfgW~SExC;e
zSnu*wa+M^8*)b_ZNS177wt8EF(B}E%vUvFfIJn`0Lbm^dK;%jn%TbXSB$|xhFlYDp
zR%cZn@49W@Syr6^`qx(0al7g9$r5+ons-1aWOIr6Ow4yxXil}X1i!6I6U9*~E<h?N
ze;`;V+{ui~i1DsPRV+}bff`Hi=ejG5d|I$1aLeN68h(y!27j)w9zXr<_&}H89!_7U
zeORL0SOL{3N91mjny$!@i4Und74mmM{|g%4@lVDfl&QRtci!+cT<1^s^UmSV#6sM@
z$2>X@-wuQ9zjhl8-DhDwX<|V7ym=x4HErm)B~k-ktq}PZ{`@T4U^XIgBCo2v%oNQ*
z0;%}a<I&NuXK+s1dRvd?IF*x8oYLpQ{@N?0>IG~ef{%>pP~Ds<Q%_*;5c_uu>Rn~Z
z525@2Ez9w)W=o)Ux}q-Lvas5v@8_Jj<XK>j2wU5tP(aMl$1>&=P47Q9RU3-`K9!}r
z>I}fCURT5T%=S`^S_h)P_ULbw`owYpc$A$ps0$IsZ+W$17u`g{Oa%|#CH`%QGf`fe
zQ6B!n9jdqM6$e$|)7%^sG(8jQZ?g8PD5SI~Lg>Cdt4h&fhT^|AC~7vBmCOP`mccc=
zLhr<D5S`hItR9D7G#IHE76sk0qInI>6_10;^pnC{i?YowmkJU7m;fD-x3lS1TY{)$
zM{;-zRhN-mDO{6ui+zfI-U$7%0E?!vP_u9_kT8&3wbsTkub^oe+p~^ITpNaW>0^sy
zz-t*4UTa?u8Dr)}9tarvXP`Juluc}oQP*-$K<cC*Krqh3juNb<lByKrlEq_x%&(>%
zo{8;+sGKuaA#B0i57qqsC2CSWDk0|b$@XSrzQXLP(>YmXx#mISVroBSc}XvmM1bdg
zG3F;t9g8^4^xf`2@1QDSAI<>QE%MJIS;0shwasOO!~-z~Y|jc9J-8m}De0Qz`(RC|
z*tGk4G_lZrL}AB4c{>@;X1;w?f00*T*C5R`kp7~;p!<(<Lgp6#j{f+Mr33@NL3b*N
z#ZIqLAMv*+nk0oT!m$>cI~A8^%~dv3C<~N*$A?!4cTi+IxR1+1snTG?XBQ#W4;De{
z#J5Gnmjc`P0jx1aoJm3G4V(I%!S1-#p@(LLrC#=Q!huVOY+On*o=z9^-M#StDWCyD
zS`;A!PgR>5-65<slmxQ}Hx%)7st;Sb4rj8A(E&+5SLh~^9FDhw4f3FO_Vn~M(vA^b
zb}38QbXq|@J@KFG0%ta*!L4rb?LF^T);XV(1-A<UV8LlM#qT8~Z(WWLZbWD&4f_E7
zB{|OQ#!q>1a9N5s^1lhLEZc292J4X^X@jAFK{qP+oya>73piZwx8)V~xN_Xlw+2|O
zvm5B6&>hu-H^HD6NZUsFCg@r7r(X!>^zK{l;7LfZGchBqF=5>4AEF_*J|@Qx(yTAl
zGJ+1cb2kLDT#w<%Pv^SqNH;4{q3SvE{k&opl&D7W9)aeU4-Lxs%fs4G2J|?|i7$k2
zB9xfa8gEQaCl@Qn7e-=j$@$JvJ21^c6(5iiFOus$0ajfo9soE&Pn<lK7fe92i9E6A
zXvEBsn9yQCS*<>Ss3MSdd;%E0ZTZ2cG4m><%9K5$%lRn3rk3D1!{o&xe_Pp`Fe_&%
zDCO0Nr31k|^|6EbuAps62(`_A;bV8L?iPQe>@R8+E1iSCOOzc$v?QV?u-cno_d>Dl
zq1>_D>As~l7m--F%@@Pi&ax<(^xfl$2ku!o&$&VI5Jx_;3DpV9;jO@q@gnUk`54={
zs`SQ%kTfp`LlL$r<!r)6*cH}<O_I3CrHrNoNUutWm0r|DqOeoUQuKva|H!Z>kwmbi
zFTdR}WZ!P>E@g8Zv}4ZfQ^*dWtYd^POnz*=u!*yZYROhN;I0bRd}pv~325Ombi0Jw
zxf+@~N|*M6wRUdn$maL%aWCcm@_tmea<C*qA;+c|ZB^Qw&cWJf$l)9$^jZmXdFJ(Z
zuP~)JYR6k)qD}RWc)&8^G<H7kyd*HK;A-(n|8=oY7c*-7ul3q`z=#dlEcsDTaHpqR
z;fxO5!lQT?`Y!<t`kWC^NQ_DSgvm3ltj}K+hGK%t6pmSE7*sCB3%~s3;;i;xEEf<9
ztr2>DL^rLTN7nnsdX1Zz7mQVSWGH?WX(i?zV@ZH*#YnY<rH$$b+29khY_!cnv{lhB
z5-KH*iK{Wa6eF>%Cz8;&^{>z(XrA#&fl^?9&JOR#V}vUAmkY~^KR8yziVPpVEF5x|
z^$in<O6-jVckGX~&%JFg^gQP?{;kO5?efdLpv<`Hi)7iebkk#em`159X3c%b3@-&J
zakwX17zOD~={<(tijW^Nz9k&}cNzc)(ZsM+=)_xQlm&SJn*?Ew7)KxMcGZCCqeB#*
zUlxUHlDR($V0so&TH?w)Sql44cX5FDO5~mt6q(i*XN_Op0iGSWX8z>E5!c?k(I;)^
zjw77+?3P^xrSmg@YM;1L3|T4PbGBXP1`Gq}=%RQIZd{)CfJ$xM0p)icyaq-j=LZQN
zg(+gY246OWr9&<b`(E2owEY#V*T71P_eZNxA6hHzPy3~Xd~-=DA%ma>rAWM59#pH0
z@#9h0z6XAY;1z2l>;iB^i1~%O^(BE|{KIDyv1@2n|I`GfhN6|6j6?UZF=;dVxDAwH
z1IiyOwIh>VHG_Qkt}FgI$tUk-(&Ea6RNak{#;h+^#hu~r=r~>kDX%wkn^ah*On#c?
zoTI8CQJf(Bg<IWhn3<Xoz+N}xxvc2~e*xyi(o6HX7-zQe_fMOs1?J{LyBcx_4vOpv
zL&XhVwgoiQVquVwYSzw*vBkRJUAh4+H&2H1Iw~|$FPW{~X*l=m^-8I(54Jn*u*Uhr
zsA_D94R?IPPA6M!6}K!Q6L}f%C%mfXk5Sm!DWVAl?}Ak1k~0dOi{i*jZ38|VkMX*g
zo-vl<;jLjKCtTM*)g>abp}8?d=_ASMNeK33X;UqOycO+?LBM72mVxIea`>lKvTU=7
z;u<-{#a0243@%Wo@~rbH`bzv(l6;B%n`VlEJA;^uFK`oLkdJWOf;iNnt`#RxPdd`3
zjmCYZygzL#1yIxc14p85ONW}UK5;r*^ileIN);DKiOPVb(~T@*EWcaJ6r=k>E8fzn
ze@si5`Tq#G)aDOK%zr7l66QMGoox6EN$!{%ufZms0(I-rPRK#$g98Y?hGE~@ElY$O
zNHXP_H=Yg35+p1{PV7ML#Hm|fPOjP9qq<L?dd%3Cz!npoX2zOKdmvK#QV)y?@`EOh
z>cIK!0hy%P>0h?9!>l(b@mBo=8=M1DOCwu1*I#@-TsXUkocA?QHTiYIUwSRa{I0J3
zl2dnqCCZ=eFcO0!*?~uIFk?(XA^iarJjUBPziX8;ZPs6v`?A$?s!|qQdEqK-q+QcH
zgZ5e4DQO;;BTRzI^gOCv81w7BFPtF9Da4-W^T(n@bbKis=LA0aal+^^jQG-wHEBY?
zw((rH4o%X0uo4PgoltV%yl4a`{g64|yJ?HLb5j_T*B+=c3Tn?EYEkL!DvN5KCpe=v
z<qPv=#Xd6n?;b##`^*o66DM>X?dF$>jCbq*ntfRI)tH$+)n?8u^Kc!f@mO+da=lz1
z^XUd$T;bqQjK^CtBTu!q_9@RWI9LR-HtO7ku!blq`Fm|{_2N2Im}cC>H#3C(Ls6gy
zU8Rt4B1k6xFdQ#8ziaHaX`nW9w$L{4@EOD-UMD&FM3iqB0k@ZLW$s|{A#klwHrZi7
zfu{aANG-)H3?X9PlOt6t3`mbQM5u?)uBL3Evi9E(KS#TIV%9|w);>l1OQ1)}vrK;B
zja0N={2G%<fF&V4(XJ_bYFhr4e^yqtjM0XDDchI&WG%S2CC<sNrrjeyVj;PY=m-RQ
z4jr9ZnS;;SwwAps;rvUB0hs>3-2p57T(n}so+hz}KA9UKc}RW9UT`Q&_L%UD?~cGM
zQx5|DUDPtG#V~2c4!dxiVZl<ghiz$W>2&YTQyI2$j}}_Lxu{MnV}o4%>v4mPVfJzo
z-AU3TYCMtou%cG>i1rJH+Vn1@tFP;XK8#KK%dDo&Tsy#hrK`|HfSM$fJ3+*LzOj^A
zfnIs<MiyNE*eYukNvMwb%AbOKmm4Qt4&xH9=dTN6j|+rVE2FlvA;-ebJ&O|>kF*_;
z$nV3sVE4yQmvE=`O#h%0(i{bc?H=f{GxZiO9{Rvqbo(d7{YAm_i5)vLeOyMWDeC{q
z$|0KV0ST-{9m2=xc511pU)m~eC8sWgz-b<*KY*K|zzZ}H%$Z7Ws58o+jqTiAKpi3o
z9g}k13@VFS2o;6wI|xmG%}1$C=a^wgq*D_TErwI2ftKuGLm9+F^chNnktKG!C1nT?
zv<<3nMeEl6Dgk=?oN?9f$RTQTPP7dHkZt{&YIg5@C$3CBe#gQSCkL*#<?ecIL&Xf^
zjD9jn;sX8!GEh`@sl@QJ3OF@a6J8!4nsCkGj6pa3-79={&)^P1l!%DZd2QR-{1u4C
z-OOvH32$La`aG%?Q?EL6@la@J)$~r}u%^}UhhnjGw_V3jmeMtB@%&q$DaLCN+V2)t
z0^WFhAh3aZ(`AmfC@tobFKrB6>CU05Hg{*uHpKqke#(^jLX!jl-=y7k4;JkXF1H&k
z&-wtp?$$c5wq2CLNcSvKFQd^y*c#W&?CX*)6iiEx+hR$4wj^q!n8}~ta=Jr+i1VS`
z#9_fi!4bcj3iPbc)lJS4;fHFW#^T_i?Gg{v5A6_`A$iRg!XSuD=@nblapu&xLS}dM
zp6vmTvXDwE`G*Z>lvB)|Z?CV4*T>d1X-c@7b8n1sIx457FB?*-_JIXQxwqY^nDtq6
z-4@$zgcki?_HsolC064C<*=dwY-#)zFyTM^esoA>!^Tix&|d8HUDG05@j;LOI+Gbw
zYLgFM7KoJLVqb$0qGS||8w#e7N?}sLNYM0Z!;lpFjRHHi4$T&s7?2JW4yP3QQ4QsA
z|Hbbr83+E*fVr@AJryW@3*LnPHk}~d9m;$TleyJ#WGqO^Q>;W(B&nrV$qO_sm5UG?
ze&7sqJ8PJuxOa_q(a#=2X0szytXu3^mzu1^$WkRfz#j5&K7m4v9KAGBa2fBDZ14$b
z#k;SCP<k&Blb?6YoEn9c8c--B%??`dllBr~7U5iH29~Y!b$ji66C9MpH>MpiWVVU#
zr+I;+h!h+2RUulpmx9zqtlWd(RgbOe=68$Ohs0>17ydrD;g^F1ZuXp{<u#a>QmEyn
zTL^^#+bz5mmCgzC<cg-m4vW3RW7Q#Cnc&Vm$+qPgb;R2EyUy%yp_&6Yb~z!(I<$fu
zyXZWwWAEpLGVwv>fWIyA`SUeNqx0F~nPGT8o9D5N`W$x7jF?*3)?dfX2WU{0MJ#eg
z$ih{Jh++Q|PYGz4m8QG5_;DhZs=?Fe#;-cna#d?Lff2)U!lr#;;VRylHZ4{1or0+g
zhAp^wg#3IazAj*;<ikWF@@PIWl4PLu+6nTBLp}!?p47c?&}9aWIV;uYjZB+W!M4Fx
zB^xitO2(to0)E(?qvp?AHpu`D@XhhQQ%yuA@3baHL~{bln)f|=EQTwUf-G&rlGs?y
zd*9u_YnsidZW49g*n;na=_mw>io=)&_EzgLx7du)LqA&X=Gqx2#hxz~>@704B8<=#
zy;9m#Z;TZ$ZqoMQP&X^HQmi_?*@Cn9dmId><w-M=FS!l?kJ&6jB*-JQ^`0zi>|rok
zR?8<(Q?sP6pIF136{D#$NqWX97^)y^JC$t0n00***L^(@EEaWvSkCw5L?9N|C2Q+X
zCp`7$i-EVZClx+ov2vYdPHhw-0t!MP+giSsW4la7dG6Z}t7%X(YNC}t4hMKxZ(N=d
zw8UcUd&b>FDz$gcXMriNH}+H6cG;Ski6q7?Equ{fc8~Kls-=vptFwxJ*RoR<s~6Xy
zbRoW>_Lz|CP|9ZU`FK9=REIA@vo=}^gfg}j)K@mejoy)$Q>q5%@q}1GU@`YKWTm!!
zmGK464dH1-;q|MptXjtP1g!a{;~GL9A^=-Lb`3xKU@R6)e-Hsg<`TQ0lN9cj0N!dW
z#Os$cTl$NJ`*a`zW}ACUztdiiI0;>fa?lj93-}Wu_=S9))B)aFNj(PU0Q|Z1741vf
z+_a9ow-1039S0W;`ott_gcc)NE(2)a<jXA>g8X$~jkUWm3M?3`(+f#YkZRR)>9@f?
z?Kwocp^l@4>9F_1QU?~)x`9`p;tuO>XZ}*)L{JK<oB_NdkwN?i4+mY92&IG%G<D)x
CRpFNa

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_1geth.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_1geth.v
new file mode 100644
index 0000000000000000000000000000000000000000..89a300db52ff29571ed795818ad5f1f68491c96c
GIT binary patch
literal 31984
zcmV(tK<vMZ6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btl#%?B(cGx%gW=WD+0z!h0-tAPV<
z&Waf?I__6j{Po^>aoD*Zld61Gw<%cpG*<WIh$9liNU)@8Y{ceh3#<6}+6;rA7n;<+
zv4TR*jc`JgFGVr|F7WPf5TN$LSEHs>vAp3Pg;waQHq3GKa^)B7qSc#7C4uBbKr7Lv
zTAI>#;IB(XRN{p<R{%ytr$FM*<gPD3tBIB3t>^|=E4*L3Aqf}LmN^o&)oElU$Wy}s
zGTn^iS~8^3;Rf5~XXB{BC`MR#4-*tawsD7%Qicv&1w3+;<SQA_F7^@_Mbl7M<az86
zJpcfHS`wMzuLsuJYZ`#PH`EAag^BYk>?KG5(`-Vn%?=>_FST=uSk*_}%zA8oX_?aU
z7ti2uPpbWRXx?F9Wt`3+542285G40oA{EV^@5L5uV%mL3GI$huuZraN6GfD_v?Z7u
zBZ!$-OwsN0;~;wV7lenGKGQ4DGXG~v;&>zbKx6-)TSEQ!>sy0K9rE_qX5v3?a~>=L
zr+W?FN-Ovj>W(Ig15v59zzWaRjwZN`umy4u98mMq{uyNg9uwM7Sl1K-jr-%!ZVUmH
z@Nx|)FexjVynReZ_a$heJ(SPsb|^DzmhagoV8qeP0g8#{*Yx${D6>!<uF1KL3R{o_
zT0Vdtpk^#N2(^wl1b>Toj<(r=O!<4$iT_o=nWkc&xvg^^Bt+zcuRzrx)K1}~bJ^|3
z1zR1s6k=cIjA9iYZFjq%iYcOn;+XWqM~b&nY}d!_L@%(se`zT%_Yp@D>^Ey45f;<x
zmy4<b-|F>o(!pk`o0w-$*(8G<=(^2p!2^6z0eTca<amRclz+t}nH)Cl>2X<~<cIAd
z10UuT+D%SIA0T88=KHof0ps{m@&Sm2BMF9~N{iWGJMaho%K8zN$u<JPo01fMS!RS>
zuZ(}HoM%~<@t}R)W0(2_ZGS)*G)(BT2yPZTi{{!dR!Lub;SVg>wev?>%TrMJ+U?P%
z3^5geZlawoE8osS+4_L^I}Bz<1NCQQB6yx0A$%?Lf2$&gV4=4MMuqidr$MF5dx7ZZ
zkkgv#Jkck;7GK|V2!szb&XQVV586`wbx64R;&{UD*SappW+6u0IshqjSg1)OnHqZI
zj_)<K#6sLcu2udDZPGg%8%;;o{$eg}Gp>Jak{+16YVIPOwTLZy24~{gi=tW%MPWV-
z76%v?bc%w)=|U$^ajg-!hUNR~8OViW7m6J2bB-zmX(i~*mxB)U+wj$wsyJ|c&5^7N
zeM_nnQ-dy<1i2?mzDu(j-QngdiwgiOKh{GG+hCZbGJUtE{)ziF&g3c2gv$VZ2px%p
z-QDD9sU3Wx>@$};6XJMrke3O`nDSeixB@#m!n5@5NIw-f?ssdfn>URf;t7@gnx`xo
zG-R}mA`PcpVcmA>+}A-!=S?S}699m+_kW^eaq4Iuwn6Q*Ez54(+*-<5-~{L&$K_~<
z-hHFsM;l8`<-FEZzUjp}F4MQn%zpQ38JUDQ5d`h6FXny?PP1Era+;~xOk__JNKX{d
zR7%~A*N2#kEG!A{?+$4#%{Bz1GU02A;dtf6#H`vSV*bv6Lvxun74MxY7-MC@KhBu_
zo<)AD2|86U^&34pxV#-a$~?l+I-dnv(}7;Y`UDduBQ;)iV9(URxvS(<Hw)c6qhQ?k
z!58wdeB~)?V*)P{eWuCMVRk85n5-JdXoJCB_&>eA9E8mA<Q9B?<bKqhLrqHai7k)`
zU3$F)SP>GlGv}VO|GT--YL!-5A!!@s6D=h$!uFx7X@UAW$=S8&0o5hb3S0msg#IK1
z-sbH2ZH35{2%6AbEtT6Pw|dPoL3kFbA(Q@gyhKarar$YG)BUL@G&B3(t${L{IbuNy
zthR4vTn2hsNZIrLnK0Z@s}vGc6_I`cP5e9NgW5OL{Ex>V4=P5ehQ+YzBZ}Ct&8hA?
z%ZV&`_zouX3XZ8O9CDq}C7v4QYbQKoQZG&zJHzwHlJg5DKzTFss<d|XrMcrLws@Jz
zr1U!scOquVA)ONXlWwnTg<3co*?Y{g(y<833u->{{V_XAUY!_2JB`6=QllD-fcP*;
z9ng%FL66rPWg}YmWAoZ!{9U%qOx#%LD;YX7{Ztw@!!X)`xbo|!h(SjZqq?a!T7JNi
zC4eRR@?D=a=i04{#Ed{080DUNxeuD!F|4Y4$X@u`H9j>;?s8<0(JU>$0Afv7ARb~h
z)he6RSsQhYL5z=BNr28wT_oWC5j`b*=&^XM=3(oEBs)_Q{<Lo;hS|Abxk#`JawO@1
zJuR)Q^^&K9$Rcy}6v|maA@f;%qj4hNa5~vO10J66#am=y@d&=~Lmuw|sC;&!Mamg}
z0xmy3jP*Pra_@Xh0Yn8L1wr1@`~C!j|Fv9u`H3vn?HUXxSu&@IB+ptmHwtuP=?9%g
zzAeEV#b6c3A>?s8t{|=~NwS!<&&czeCN1IT92DicwMgU`U@XjhyB}P)bQ4PbGnKhL
z6IBcVg=TXK*@8gIGjIw)#)s-(RRB2j==p&d0VzSLHV8E9+^X+z%|l&J^i2SM043<<
zu&&d{Nj9loN06(L@cbea#Z@QQ51`F`^q+RdV>(JQtLq9Wir@6pTyIuj22cDyZcUce
z@wdkWxQw;Gy(N_PI=x<x`ADilL!_|LVoRKxMtBU|y6Is%X^Vsrl=U_}`Gk4^t(;--
zn^BH&4UeZy$AAVO01LLJ;zXi6M!zaA$eo(W6g*cV*=Tm4R}!7^XD-!9>1mW~^KDb*
zb2tFd#sfxtON%aF7#gr*lKE-bt^K-&Q%r^#CRbK3KXwr5*h~#-%vw+f<AkFja8;=>
zBE3HLT1w`0eELt4%7fB(rBBy$ADywt>vQ17$GUC%iLub73j%L-q_QOu&DXCq5*su_
zW}(n+=FuJq+vs^<70XE|aGMepQB^n~XX?a0StNFgjum<+kj_VmXVMQT5%lZ|gUyH&
zU3AU3!64pFOYn#5K7-PEZR=?rZ%hujh`9Pc5B&Ci<)M+j08Oh{=;LWjK1w?JMH#QG
z;EK*3Tv*}kX;?+0H99#2ZU|!C#b@;|3v~JgK3n(v%;%1u?8YLNOD=ad$4ldtMnE2e
z_yubLC)Do_T&|M#|BsFQc2?FXI8+03oC*a2f`SUW3`p0)D-d?rwUyc<+Zf0s&(TC6
z5gSV)S;@-+I=L22EL+hN4q&?;lz&N0Z{yQDOTIUJc&hesht7>7XrUa_S0o&S8Hkyx
zMNL->`+=J>U|~3k=YbQO=>C#$*h#y7pHAV`sC(%MYKd;hl~IlO^hpexs#`>_x6#N+
z48Jl7a)(~0o9|SF>8n;XkuRJPKHS^t0m1$*Ce4~XP>)+a_~u3K3@fUQZTA=%r%Q7;
zgD>#nkBu%HUr4kK9B=f{81pRl)Rx0Yx>?%T3!!B&t97;2>6ZieP!px*ZUZU#O{41a
zv&M)UZz&U8)2G%%nXmai&i?}Stjf5B9k_PqpbD9ZKH^63j<<!rps8;Et2$OVLkh0c
z9aT;RZitt0YMojRF9mQy!C(&Th!fKxL7F%z4t<e%H}E8_5Hd1k$tndmnuxFa!+l4e
z(M0;>fp<Ri$&908ZACjr@}2Bi$4?HrhSOGq&us)cdYEPSv;Revll$S+6Rh0B?z=1y
zQtUR*7pcHn$_Q1LdF++o|M(;S@m~6YL&@)W*Iwa)23T*x);l5v9SO=4t&sraPulH%
zcsu}{u&9k}#EdGD4wL9`B*bbn=K8N4N-L;!E6gNQwSG~AI{*q#;NeR!YDpjxx%)5L
z$tyTd6jdq1)vt|lqZ@sXG?i1?)ozQ{DiI6%uKf_mdp7}3svw?+7A<%(4X$1p_<%vv
z*eaiWa7?^mr=Kz%-c0zBU?W!*4H(*zdtt$H(_Laf)3h|aY>CAr4Th2ZFNWHElIz;E
z0HEE6=gKFOiDcwftVJ(kI^5NxWu;4Ah$hF$tXJ_3{jqIEK+j{aL3?!NWq=!>OnICQ
z&1UmZqm`%!E0Nm^e>b_fIg7?G)u>f~-;jLy)DpGAisxVEUnOji$Hxl>?$e42`psz*
zsZn<F4EyokG3El$Ht@WO1gR~@`k!x!ltDNV1i7bhb!TO131Ze=yD%Lw4%I;)LyV>Z
z^%7dqw5FWdMScRw=%-P2BV&4ek{l;Z)u8-`wH9f4xvVz%)HT9U)OeM6u9H_P#k_@H
z-*R|V38ixcWNJv6!9wBf6Odb}1*A#CcZ8L$Df2ag(_15x7`432JbwSjL{}@gFsznQ
zplMva4mImaT^GabC!1TQ1t>?z$daL~hys8(kp!<6e(oPVvG+W&1YC7&`^TO>Q<&u|
zL*PUr2Lr%yKyv~a@x2E_0-*GNE6V`6zyrw?)qQ;@=h)}+7Ya$pt>Y{swxT$gFm0+;
z{x53f_{64^@P5zobhZ2n38_aky9qeigWJ|3__|iVdJqc-na4>PESbU4GtS{f<rPX&
z)-{_`K!iQz(<AQSZzfP3+>p?O8u|K(!z&%h5$s7(LD0yO2$lLeL}YrdLGI@(PwG?x
zodXifrquG!{pbM=`N1(L7n!m55saR*-Ca;dZpRc0jjDp)r`Nz)T|mo0%IEfIlPCAz
zkXd6f`*h`16#U!6o~T_bX5IWBf^8EsdA@DCfjZyY+ae+gw7GtAAiJ-|^wu7a>*GT<
zNJ{^*Ic}I9D+JIOx11vdF{lJi()iS~^)Dhff!ZvJF`}e3msa>OC&0eX5)}}91pn;`
z{0o2(AlYWIG1e$xvk|67M%@pC0P;SV95BL1bT`3U>%Dt`;#!N|i~@cV7Kp_}5A}90
z^ICm9s29+mraH!Qj<GW)6D*-F9j*GM2r=e53|`Ugsw#~W7&DY6-1foIyC^*;ANw(Z
z@J$ENm|(T+JnMotlxUU8CML-P%}_r|5yH`4vRK-$q&ijeFO&BTDnp3(Nrqh>B=TXu
ziIcz~{d)zi)2j$1bvV$%ov@HEfo0G>NMevcQ`2YZu|jH@i>TiyihLhLQU9f8CJ0i?
za|QJEXB`mRBUUjqb;~)<Znb@>onN=i8R`9>-(VwWw~8VY;p9{tVW$0fKI5p`y2z3|
zCce+=Dlm3Hbu?={<}P_G2&N7Zo_N>3l#{TMlG!Yt>oRf3`-{3S6{63~E+Ifv$e%3k
zY=Et?`@QrX<Ps0)1kg88w&)6hhVB%gR60{XaG-;%l*Z;v<H277mNF`hnS?o|`k+g0
z$p+@C0Cu*gL*zXeny5M`xBdcCDsP5Yp9K6C|8s#Sx+@RIoGk@<Z~obIoY&oZg=3}O
za}4@43!Jhn8+cR8*xCrTVPm`Ov$f|qOYq(jMc7a2#}^vJ&>@_@zV~hUWwG-wiCFiv
z^A}gZ!=PW+_=q`<nrddwnM{fCCW9|A24cZHR=CKDT|ius?J+CEsb};_SHx_oLrd$r
zqo2@ZmyqSU0Cct*|7~ioLn!EBpt93vff`X?oA?tU>n9#e!wMem5B=A1C=}r{3J`We
zOlNP5b0GtRBbRZMy2>0xyzfjs0g*Z}t4bCm`j_0EZ!8P{EV|8R6`Tu@3}R4BK`HV>
zf9<1VE=o6VV>_ASxVYq!c(qtuyE};s%rWnO<LGjz(Z68IDKJXu`PdX<!W#&}$&+ff
zNp0WW8#1PsKMTkjec@w~O<qd$-|ZY26gfL>0weM%o4B4iKDqmsT_2Ss=|Q;v<zv;0
zio1T39+CxxPq@FbPWRq=NlMlw)Qa)cXe1)nj7NwK-bP$o6e>~3+tnRRX(x<U(ti<z
zdQQJVpIulwY^|xo%#M&FjOi&dvx4kj@v$`xXUIb}(X(KCHVf)D8e=EIn~yP*I`QEb
z#nHvMbW2YjUH8;Goh$Oc9^iS(G*`zEJ{!8^5I#aJ*V9lmU5626dPtuK^o1wF=a&`P
z&utJ8TazEXep=~SRbtX*Z#z;vq`L;bS370*0aQ%c`Z+1q`N*s85rsuf$%D6hVi}*L
z^uv_wsIvC)mZy!BQTizbEo=$BYxz?pdbe=5Ty?#*gaS~zFGtOMokhVOsml>IN6r`=
zU3DZBa&JvP0i&VAaG(8g9D|O`pnYUmQ0DX(6nbB}n+34CbF{(Qk*TMXT>Y*r!~vzm
zRUEXcjcFCDkLjS*kvPX=7(Q}T`wmg+5>%=FFilZ+HZQE|iQV&ODyLRQlcZ2tQLpi<
z9h}w&ii(q{-z#UO3z8FFMVN6wfdblF1?O^?-x}PHCtrFT$`y-jn7%5`^XjDhM$Edl
z7lAaYj{kP!k+8lGUU3w%y=34{19EoL(Ag&XGTl@n4f?CnarH<dB#CoHM}$!3PkRH-
z_Bw1{?>{cplFAeNbSPu;ypi5iR_wsvhb*S!OD461WVk@~ybBD=Qr~Z^fGLr}$fNV0
z7})m4%kMj`D&Z@Vyw!&O=P2W>rM<T!b&TI<H!HDI-d_yFsr57w&TA|lVCjn9w+sgy
zp5H5E<GRvF9mH{a5m?&}=CX_N3CTqr{bG>_lXXz8<Wq6_Ew`ms83}WL4=r*f>g78W
zelL#V+R3Rn?aJvex_J0Z>|Ct6Hh3ofE+;D@kE&f^Zi37}CoXnDExU>gx`DP8s#QG+
z;kFK;$Nj*8nX|w)SFBsZ-YghW<2lDet@m4G;?{5zt6TVsoXR~y>g9}Tp7&O9{PtAU
zF#5rNIo}6+4r5fi@dwSe+YGYd04ApLBpkDo5jP0FDAzx6ayaU3_oG;!c1`(az!HjK
za<X#NIaI9$(SpA5Pu;n4m36qaYxI|zvI}==C&9MBsW=c9YP4){gQD34^C|nFm@@K{
z0q0tS4)$~&24^c>Ugk7ErW*(&4*ks5p_!vyu-mswn?>iFWkLd8p-q0hB2nX_&AwVG
ztidP-U{@XPClE-lB7y+sWvO#QqweVqx|G2aXQ+bEFyIZe(s#!*U-6FIk|Goj<y=cb
zC3VT^58`=lE)erl>?Tp0>0UKXfeQSX#JVe(<kDLh{I2bcR>H5=bsK7#gm+aLiR|<w
znNT)&?ctEwV0N{V0prhY3V03)qH~IZH8W&b5S9jO1a-z3g&h^%1q{MVC9iQ&Hw}^P
zntr-P(H=xU_fz~+i!+PNA=xRsf(rfdtPTLm1)~$8UnfI0lv8o@lFc9len)vbaIk?(
zn(%V08=l<oZT|0eQCQ$StCX1dWOj`sh&Q;;KL4A%)~bA6^ZC-mG5D(wJ+${G^cw^J
zSKn3pH!Ues80>HGoKK^F4gN;cfdZnL2~^lASP2XEVp)*I*<Is~Q&b%CB916?r*Jep
zq9vZ1V#w*b)K*@SbQts9n@SbPe<qY+qVSe*vLc&p%Y|NXdS~rnbjmfGf)R<uVba6b
z7ukm3HM*-fY5hruL{6Qx{^^Gae+jxc1MZ6ZUkc~$%Sxv3<&*QiQEw5yYW)jo-H_fF
zwv4A8!Q7{^dMmA6peVra@sZB(@xapq)l%C`%4$Vn1(sLwga|Aq&Z>}Snf?Wb#r?Om
zRH=o1jx6_w(Irt7y2X$DyAd7suDNZa3BMZhIHC%oMazlFom>z-$idSLHqxiKlbpHe
zkTRBhlZ)!&ei<@6Y!{iPk?G1+#0OwV)ZkWWPqVt39L1XcewWSVIry`nbs?!VlnF^g
z>LMd=SiCeab<4~+NN|)@iOSa#?Q)7fk3Y_NOD@}*4fHs_;H&Yaz<@KY?E3)?Nv-35
zG=#rBg=FdUCZ1-P%j*R)Wx;UkQIMT&Qez3Oda_2ut+VmIeUR|L6^pH8QQcO|DrtJp
z#SSEY7SFAJlfps(VVwwe!<uSKY=|kNun(mUA|>MqV=w?7x!sfU<Q$0dxkBST$m0{d
zTDCt?ItvhzVT%pOM9x1l|5v5I051JeOh|j>PICAA=ip^agjSowls_kv*zt)vGPlOI
z3x;=?-~d0RTPJZoc7vnLS9+zsCK5vS7ywO}8N%>*bX=P3)5Wc`9rynGRJJS+<_I=E
z3PTsPb}Y;glU%Fd$mSETBlq02AiCrfUMef#grx|HNJH>2LJn2_?IML?e$S;bxolq3
zv<z4g%dw5~<}8DQbQ1Pvfeud6DjRR`Ma--`8+7{jG=pyiD$dg-@MsPiE{i_-SED9-
z+i#uK@($)Idv99%ijYVbm(4d5ho7yzsUNSH2@Tv2ct0(8Iz_i<pZrV0wObUX=M;&S
zEdWEyaJ})Rv7novlC)NoX?>M#um?tBRaPelLRgvi{w0+&58Gm1p46X)CvrU(UP!J^
zu`V82krDpIt0=}dm3ehPe3LC~;G!G;pm>dF|H2}}a<|auX+s6=sHc!)>}TO$c)<+7
zYXxR`X}1%H-rkpr^ec0gyB0yA3cYH%PirN5gn=!XC!K{cHXWcnjltl7cRVux{+LL}
zBM%-o4~6(0l94T;+E1F4uO_+_#4XurYYh11Tg`-!WYdN-vq)KaVm(T1avn2wPU&Pp
zAM8#KHQRr2y~<~=y?EI<rHQG+akLP!rH#(rxo=%s$}~4Tse^QMh_AKK<++AcIgz%@
z7K&k=j6N&(7H2(>_urFUGNs?~SN;P{i^pTYYt@gRcK|V+X83xLWtCQS*o$wC$36ou
zu*mo7rxiU2JbqKLY>fsfjsCt;MB|Leq5tmYmZL>8tN6Qt!GFXi+!gS~`(X|KY?4o#
zC^BJT8-_8l@9T9MB5-o0Sb9yjYTd1ye7GZC#4Jr?r5PJu6#vs^?;^*+fJVeXYMicW
zo<6acQ{8*Fct@;zrw#lnLhi)e6i3>y9OMo1!LO@=QeD5(Kto2iL3E)G#Z=EKd!#lQ
zp6D)ieK*r?)lz2CxHPl@kx|E6UsBM<!o5){Qe@qz=G)s*<}Q=LR>Nedwsx1)^~prq
z^^js(b^xjb2M(hu2!Wq(<XV!}ZL{V3<8G~of(M4M#@QEWx5Mb{{P|w`a-R-{EL9*S
za1stxnMoj+7^5@%%gUBCEL7yZi3x44ppT8Meg0lu^8l&!Y_$vZSM*N5%VBTXb^D<d
zNNgMWeFXLU`tbyhzH5xJSt6CJvrsV{A)j+4c>cm0r-*{{sR*Qq!(4REf(nNmZ7_8o
zCmJ@r++)_>Xpq5Tdve~)U=q7Bx<TA%zb?DahN#*#ZgIsEMPExC)r3(Z+f6HW=@>4k
z^e!Ce{lS7pI?3N$nNsC}uW3`YMNJFhUdGHT`okDN;2}K1d7IMSd^0isQ~iiA?gb6d
z!0seww$g<cAz`}}=t1|8?$((ZAsXk_VPnv9R~ph4Av_fJ$JmjF<Y9SlndxlX7933x
z4dJ}2imjIkHO=2f7uM6tXXBxjS0}4=7CDS7ul9%1brS+~4)^{0Xku2SvJwB6(0PPI
z#kO9YB0Dobd~4&->&F*mp*VSk3)Ae?MZ|1`WD7~sGT3mOLM;!gpoFg}3ZF<pd`3@1
z2r4ctnkBj8O%|h7`a<X&SCnozrp%KQ(L3My0|&wR)AKYu@a|y8M-#3&)IwT|mQfJ<
z1LQ#H0)4;}v{f4$!R2u5`MsXlM(7gha~3BcAa_yVZ3hcvfOei+|4|bty?l4k&aE+0
z@N@Yg*|!iok9?thsvp9|@Q<VG;CSNa30jAYoc<{4Jx7&{Z2@|X^cpEFECEYaLOOH^
zMq&HSrc0Iq7k+N(4xoqQVc*Vyb>)krWWtwPTl#|PP5&6czc60ko`Y!C_7009bn;}g
zrW?VwDVM{F^GknH0Odoce(C^UzB!;wkRvUPwh<oIXD?X=yAllLtN`X8zz}KUB;$L<
ziq!PPv_Ieg3^)e3NCVlpbelGq@JgBmAd8_8dH}fTEu_vW5S~ii5GkI>JsH2GmXRiC
zL%rR3#{@$2C*~HIukvNdoNw}4=cJF`and$@$~r@bahZL-WQk!?l%5{6O7^rFs7el2
ztSBeuB5ZHyKmB$D!-`O2yS)GpZe6jWnQwPlr#q8W!b!cCa)@WwcI=lv%)%)m$gJ=}
z<Jg8Or**X(EXxq|v|r?nNwYCu=?1KBl1GYhf}@-O!LnqE*n__wOTm_wm8St^7Y54`
zmmISX8k>`7j!n(!zW0wbDa&dPefo^^coPz?vFz$hHOKP5Af+_nr*_2>?Ywk3S{gUA
z%pj{qh@}+Clrh8?(iWSkVXkWAgjWtXHJVF4^$g{wv-f;=mup49*jzZ)1z8+2OK5bO
zKIMsv$Z7(L1wU!sBHRnsZ(Q*42}9<Bj{~B{0I_9FQdP?Nfy`v-jYiwNOm+~#DFhLa
z3+wJlV}7ho6Z7f8FnGft@K}H@HYFm@+GUP3Az-HwGrC#`GE1U_jp^vJwu3-=6$l5l
zH;K{NHePN4qRLz6XVP~{lLp}zty{7{Uy~9z@aw0A1Sn`Y*Osv6{k$3Rs!_NKy<8XE
zWbuqy{(<f{IW11nrHQfitlKt-1+MkV`zW=L(-Gvep0>28&hi3qrY32@an17|0FLB{
zwx3i^ogdXKH?-DS^(?_@WhOkoRuWei+J*B|qd601tmQ9CIE5)MAoY@LA&+>frzSrv
zyj{_~(CiPWa_>m(72?~xwk*Yvh|NNIe-K{bVcox&NNCK65BQe3VflKpvBhSt`)`3_
zr5b^F%r#j5+CfIPA8{i9Eb&sRGSowaYUWopx?DZiK{v2ND*P_OZ~Yt;rHPELu!j-;
z2(4A{!9=f60i{VISy(-jE3p&+O|2;@P%ho7VrSt?wUbAP$WxK|k+4?bl8cL;%C%OJ
z!gd!SUY;V+u3FKDTc}_k{27a65>5TzlPzIhg9nTz!_wvT*2Ng_#(GNkV+B{x@QKug
zY4`sfttMKqEkrd#wZelw=he*KdO>50o9y4JbAr9oR*Ukau3Fi-Bt+Qake1{+eHqxM
zDdprH-Z?sx+ui!ly7$Q>i#x-h8K*?)@c4ms-uF>o4%JMvImyO67?54M0*#Iyg86j+
z!u=U{aW!@P_x#M36D}oVCYO^KK2nhPS4l$>?YZL*sRVOUlJ;3Ny9q8_iSDua%x;mB
zEs&EE1h3t~UTk&trPZa~GVgy+J`;5sy7~B1U?otgcup}STYlVnftbAmca~-{O9K4g
zZu5;bVGP>|Hh|FZ-iLe;I27pjoQKn9v({<@NgWC%Mn-qxs9P@Y=bTWNt0%)FST#<K
zx#@f@g+$!tP`k(b7UZ&MXS}w(kkaW?pt}`HP(H*7@^I2Ovb`2uKNHJB;@{GQ9oI>K
zm2R`7`B4dkiI8#}!a>;ZLaQuX8O^3G&V-A$13l~$dSS8vS_gowJ=6@j9A`vNFMG<#
zOeHS_Fkb!}?Y0;3_F$}9)8C~vRk9jKJ_2XXZKXDJN<Qnli>Omv7-$6lPpJU3fOKR)
zeg`eRcoIqyLwd#IRZsvkl&nzS1|OHTT>7to#dTDnhG+MVUP5=_v3ei4$W(!Y)lB^t
zd2uaFSgZA2;RN6eID;ffhkCQNeo8vnwN7)p?qx`Ru5V+%W<qncey+;(<s(FGXq#uU
zl*TkC)`gs_0y@hu1SzoxJsvyGysW38*iP0zZ~V^je~7vrwogaOD5$ZR=!tE`X*@uH
zpj)8Z80WL3)!iPIC4k5^gRE}71e0gYp<QL?vdM=@85<GBji|L^$0BXNs*5`Ds-nFq
zvcintyNPV?HZo^TKxys2!&tEvZSnzj{wKKT^gKD}136jrzMjH?h+1MZX@p{&8=|b}
zhN?O_>c*9sq<RWKFY0{g1{2IC1`U<dpzn+a`303kYl=3}?h^8ZnqY$=WU@7&d%Jj$
z#d!~r(L>K`j2|RrznWFidJ+RA!R<8~AO(~0ZMuRZ<4}=~AOY7$U3b9+!_fvJhu{b-
zZ+8E~U_>xs1~{!D3ZeprYx-LsPdJW5>}qA|J&3~V=vGA*t(i}e_<0?#J}97$YXwOe
zs~us`rS?2=wlVy;psje9j6dr_t+-Xi(Z2$bXn}eV=Ud&#fP1(&OUQ$*taN584nl(l
zMBCua9!P*DrsF<Cm`^>LY<f^_y9u*GFIz17i}uX7Csl$Eh4`tyW)MwsBoV|u*HpGS
zPmJ>!K0mAcx#GRjM9}saV#XeeE|j@L*oo<SR>0#k*0!A^Uz&1%>l|ZGG7}|UmOEzP
zxAOQv<aCMxGw4Y`p=ZxT+u3lq=Sw0+n+j>sP&qu$!bd<Nm4v2NZi51DE6ba_VV`=s
zhgDyi*3Po7$c!PdUs?%%gF|&V#Fk;ZB7ADexQ0pL0-32~rGWH^o37Mk9TVF%yRC5%
z>iSdnqk)Pc5r!VtJ5L&+1s<WbrmkerHb1ZYkMOe|>i~N6<CYSBC6ku_<cS>-W1=QX
z+boq&1kk04o#ogpdaLhiW`O5uyFx(+J~qm%>V}A5EpsqzbU>LDfZx^ASiXw^<XJaa
z+;#_<1XkolH@fcrxbr=D5NOY1^gg!Y^?;+>jeS^>>l(`>s-JL-A%05!Z3q~=ipY_P
zo}SQ4$xL!D9G~U=eJ3uL>~Pq-j8HILvOfyg(#b=(sga|o0-GCY#Z9Izv-`p_e-Y5b
z;(RI7l_RUK+}m?`gE2VW)47-NF+6^;{QC3o(G|hyG0DADbWT4Lq%@+cTnO`-EcG%`
z#YsK+lu@s0HvpaCw3E$E{kk=05L0$8vu#P$h;y|P99%l^DU32#6@xxe5uuy%-jtp|
z5Aa{t#KnkqmEm~Q#WzAzMGE3CgSw%WL^5}?vh;wX0x_&OSmPQu`scIH%)~+<Tl@!Y
z39Brs<R2m?{_Wf>Q)CQai(^8(fSW|p64u4Kl~cJDrq(IhVpK|T-UXyq&<eE`{hJF+
z-=wY*_c(i2>|EE>*d5ai-K{c?+_qMC9a&%BR|lGycdwk%33XRk3h`I4yAo~uC}QCc
zpY6CLQ`u=21Qn(}zQ2%;N!Gys_p30D9~rr+0fQW{Qe{2^j9~>k4f{U=NOHlmsO0?f
zHZFzFA0dszQ;2+o9&tHG_4br}g3L92m#;gHnp#C0KL2k$O0)UKn^har%xK>jIAw}d
zCtLidd0=z}2dp6P?NHXd-so^nc9$SgGw|L0XAlixY;%YPQ+q&<->{nFwyi<7S;{_P
z(Fj2Tvi@s%P4|}$nYR$)KY<BAShnYC;Ly|n<jN%x3u3~f7TP98X!1k`HO19*MKYJ+
zO|b|#ytIH;VZokCypJUhhbT$|XUPssGF~@q$(|%iH&su&jVRo#c>wizU4Mlg+X&ep
z!1Qtk`5!owap5}Ub8y>6;bljx)~3eAgC9IPafpFvEkv8$EDLrZUZ0KOUrE0X;luPR
ztsu)XS-S;9_=x+bk_;FHwLSC(J|wpELj<3Ij>Z1wdz<P?iVIq=MC4i+15KA`f-<va
zUOJDz)-jJtEPFoBN9qsxHNljiTAYBJ4YhziyRzZIT~TV)FqxoDS&6aCv5km|bT=&!
zs6)1<#6?bx0KjQ$6!u(9#X@gO3SiZ>XeBWv+J0Lpt?=Id!fGV0goRFb_s`?>L53Ru
zz{1m+!&;Rv9TrHP0ma(oH}8lJJ5l&3kxh{bdzoGvut%8QKIgPM<K;QT>41o#$<oF7
zoh7c1fqah0uF94IfF>C|CqS;8G)~KQ8R#NQggdUTeE$lpW5xz8iL!T3)v&+RNDO|N
zXo;Hnb+Qh6Vk&-8B49lwtMgjyDq$A9&wGy1b;FH{@zDBcm!*}XI{_j-r|F)2Xi+a@
zJ2DxdW)$=~EOi04vs>jwE6UvI@lf}D4o>bK2MB%hAFiYJrJSU-NnY~ie70Adj7z?i
zuv-PLl}KOYjLH>%v4%7nlZ8GFr97n>e>Rfit<oYH@UO<3;VGg$%kN*|yXopF8Y9~W
z^7p0%#;3-DTFEMMu1Mj%WN-0($oBQM(H)@9QVE8<spqcS^x;tch(}`NEF5nBX$WYH
z@ZdLQQ-wvpN&;*^JIt(u+~1QU$#$jIoinoUx%Ex*UUz{YAP%W9RGSVFIrD6~R4v8B
za&}FQ0@5s1wn>EZQU(ofQcD`ji`dQw`PFBX5+8!>f=bZVucCIkFG$#=*QnM|QyV4$
zs(Dp!WC%*=kV7@H(xya$`=qC6AEDm_hd$r#T^=t`#dUh--5x#Q8xVdlxa`5I!BYnT
z@Z6Rt?^+x5XXYR~c_{ydbf1@GsqYn^s$F<YLC<I-Ble90W{MNtgbtyUETBLeGcfKI
zzERXLc%#eD3=a&%bWnXk9}i&>N9{o`*nAQlKQXkYN0{M8odW}06Ue`>B<r5Hnk6tj
zuBk(%3ttbV+L58r0+flT<Pjv+X{1T5TeQl4@i8zNUd1sYOQz4{O63%4$UPeTI2hJt
z@Mvv7>Jt8Z5yYvewY&_^6ttl^vwpe;o$|qJ3tn8iz_woL1s$F(EDHUzN%zhyieD~M
z9?BNkm>GJI5&GEbbMN`KA$8MTE2Njzyt4n@cGyPI;YQdU<ks*Z6#(()G0-&+K7M<$
zksUdYE2D^+5`uk=f3Hj{dKzYZi(1tZA5dB@e~HwHt<WJTK!BmyEoG`faXeBGi&L%%
z3{DUySCC$3PB1IlCrH?9zz>0Xd@^B_Qs{j=^Z<tX_dG52MEgnuFYB#_*!csuT&ns1
zPwIe{H{T<xJKHkwIA&{q?(Q(qwci^7vCYi1VufJHTtzqQwLxb5$Oo4=_<i_BvR&QY
z((R{@i(2qBAi}t8)7x&D-w}3Jiwx}xS81Yx6l(ItV=Q-B*=#KLD3^tbuh+2z4Q~GU
zmZDSb{4RN`rcXV^Ab#XaQvRNSkYbNd8thaiC2^_TWicvpVYOp0FLXvCzHJ13cPZ;V
z&?MUF!`2n2aBc`X!vz^%smVz1;RNKm^PQTJNf}OIoK``w;C^G3UE5|~h4_z#$o76D
z)hSx(4&@ISnbhWcn<2O(&sO-3wfF!Jx|7U&Pmfk~FpcPh5`^#z-s4@7w)Y4S>0pW=
zjPLY@wqMB^@;gK9$jf=mV^>U$bXkEO?edD3LRj8ZDJxQ7{5sYK6~13Y<)t5AwR8|n
zlyUc`K{0Zhty!*V)qeB^FmE#{@D&(w(@@93f7G3{;m=f_!=A7l)<xHN2xY-AG;YWT
zbp>7~9;$c#%3iOt1huT1oF!E(Dg7;ucghPN1nYQnx;wi_5aGZm$AqtXZTjS9DP;&!
zeNAx;<<7b{5c!0Nvb2RDCW`eTTvb=b@XJ26FjrJd8IS&WTd+F&YIa3tSD<Un9SDt{
z_ef<{LN_R)%o}Si<%Id)c5Dr2HftBV-$V_DRgt&`EgswuFZM?v{B`@ls|@C+=vZz{
zAW@10LSADZhZDM9kZrTc%RX3ZtGak?hX-<l6l~6X`43~?;xty+ZsX5NcHF-Sa_>g>
zsCpzLc)L%BJRQ~}k~iO?i3>$2BLeDn6Y&qeYG?bbzDdpvj&d8G+o%Vuw*MZnA?o)$
zotJEAB?`Tu<fPg7X<iJmgcf70s?y&a#+$mzTdRz{?^lV9g@zCX>;*l&gap<l<k(9G
zV&*rVCXh&S8<01J)Ja(qh9p?F{m5{LfTvR4bCr2<i@&LTW?e}%<i;`2@n`t;qtUCo
zg}*!@R3Ewk;Q^QhhuKPvA0KIC?n;$zIUkm9!O;@9&?vFUxXm&^EaQJCSXWYqHB*j$
z|F63nY@+z3<z0f!alj7X7Zuv+8Q25*xay0+ss-F$@8e3EzqK#(D}8ABuWSyMf9=}J
z9xM=F<vDM*)ZTQLqI&FjoxOcla{al}I0Y4;ff>?5rUv6~NW0_5>`fT+^+(jZR`VX%
zO5J`RJ8K~Cn;#p8rVW9E6J<gR;BxT)QD&czq4o}2T@`mhD>eKjpNwv*>(ECXR)Ak6
zddI@|^0-<GwE}-J*?Z!sCv+75w-=j}RWB<QHAJ1Q!68VNaGPU!CZ1aT4{8g&z%VoV
zk9QElf19+K5ow<H*0ds-s|~{mlUrhHs{NFc1+)k!4$P6SN2`{92yBy;Ah>JOPMt~M
zT9;Xr*coA;(=ti*S26XWGFS<4c~#U{Q=Z3icQgG=Gpyr%&}|##KRHvGlh`_>k&p3_
zo>waF%;N-nvA^JNEB!G^TzOEi1&$jSe}J0kx4sek)nRtT-?GY=?M&~!ld368yXNax
zAp*YSbAThwSm;)78BJOKbANmlV2KQQ_})`|^R5FghmA+<+X8bBF(N3$4Ef)gv0035
zusU6uYv(=!=|udqHJYQC?q^M~#dL{Zn8Zs4O)-bQU`38b3{r;0Nxb}{Y-VXp52>Y2
zA}zpn6{1O6ZsGK~adA7!qa{(VV+`s$K5c6IdOu3H$Lf@*aK|;rsJs1)hd7B3Sf%SP
z$|D}be!3R;s5gKoXQ6ntQP6`AH$2Ma9HYCjds8_NAO1=3rAE?NaGB1(-WYE8Vxq&w
zFJT@APZzAL4dXxc4Y<F8qPx^7Tu*{ume5nAZuS_k<6{Q(Ye0K7nrNL!0FTDe1wDlU
zS<NY5TZ`$2QM;23x^uJ|!F|ivSkk7#!+MN%`i#^Ipks*okw62B0@ZHP67X4@ZKq2%
zg1X~MT@3er5E$}7W)y%^{f1w|84d5lN6shPy!H#yj3igwU*cN6|M=8rpJsDJE(2co
zMwV)X7GBwtbFJ*h53Ct(8S-zo{I|AqyP9#rBM4Vh7;~{mTP?Ae{L%fkeUV3GP<nvv
zAkNZ89>4wbI-ZHC0o4V>-_@lf)ka>p+>{W$K0t5CoeAUzx<R)ul--7y&FV}WixeX7
za$2ZGjLF4yFZ#&}5t$W;D-e8ua;emow5Oe*t{}!;Bj!_--lM<ec-eJo!feZjyJx$V
zLDqX!ctcB`s~?l=FeAw-qD&x1E%Q(fmhG*9h4s;Y641g^h*u==rCmyy<yU-(9*MZ6
zK<5*^-yE=g;8VDRL(7rVLF$>)e5B@2o`VdPL++H8<`(yf7_LI>mkER_#D2J$Be@01
z519$Ip9Je=hR%w|20;qh+uRDRDL1K&>CtV6Y=L_OD_Ul&xRciS{BSC%3Mys0f?MEY
zfSrVQ66ND`ti!rW!0GZLr|;f~{EknHZu0Mpty@)F@bQD<t$n0*0F6q@PzQlS=A$ox
zWx;+=)am;3y923SW?vjM;y@?X5V)%Dc5Wb~B04O<*?Z+|9EGS+7odb$ZvW2Pz383)
z=TX5x>HY4yJUv@3&HT5}W*3ZkqysS7yzo+^M78rpo_QcCp4D+pEbS<m!@Jq+>*>@a
zcM2a5Em`3RBai7eMy{<Y@fy5lz!hv{dJeVu>s>^8;*QiSbbu5S8$9PxDfU*k0{7>5
z<wD1}U`1DUeRA>?H4YCHC@qh6j5o!xeIWVjI7iE*T}9Vi0y|Tbcnh!ak+#jfgnyOn
zSC?M<lamZU`t@{6ktV1a^5w{Hd35{j5U|_dUNW#`D9^Ur6uy>}o9IASopg=Q$e<N!
z$4+7QxUxa^dc)9eQ1|PJvPW<Y8Q_;)%jCKDpV2}v13-=hn1yx0?<o2Lq4Y=ZqqlZU
z=PY_As-(3UiwhPWvB_~kBqBq%P$-jK14mnE!Mo~Evm>%{c<L1hEv9?LD=rYOh~9D%
zkM32gaGLNI6d)nTGx!9^rdgmQuueI3y(ne&)ed13vwm`8_#qn*dy<Q^|1Q8%@8voj
zc@FbV#_^_N0&)N8Ws}%G;YqqSd4`G2Mnl0L%)@2XB)~ihgiqppShF<U^<B35r_;J9
z&WgnIyr4s;)zs*d@z0&0X6{^^YxHFBXlGMZw^?RcB=`<DntWi<u_c7ARM<b$Dc8}^
z`LvwFBAN#OTA3q_Ey*bw*7#T<2Zr;T9vnPN$W6ZhdKBS{{R+IlrU9T=`4K{<+GJD@
z3&4^SFC_n@a(gO6=iEt{y1qRYNC~tl+Yadp><mO%p&Z%ooysR2*U!j~F$IV&IlL9D
z0=HQr=oqo|jJeq2cSVy21F-X#tJb2q+7HM;QES|*1qfow8pC*D-42q_*0v*|fHbFi
z5U_}4T3X-jS|5lSPz~|Qym@;C9=tC7i-9X&cic3sl=!R$&Nn8rbO@8L)iA5q+wD5w
zOu{oC+F3>x@RcIy<HS*^M)`()yPoIWjPF>+Yg|S04T(B_1iDK879CDiej>jNCcoq`
zgZRqnI;jxX0~5WEWVZK+CQ}||czfWBgW}XMiYA7Ur?e;*-*Y(R;G2DS)-Auf3j7H+
zQtz=pyT^ZhR9RNY+%$2c!ABCPf=rAIE&9ld#b$KB{dS&I#TcV13Mv3`qG?Np$)GYY
zmc`*%jVIC{vK4G<p3lGu2rZhra%ubx^*}i=+Gt*mb;&yeP$huQ{dTFV#lY4fnd2U*
zTPTJmV2wVP;m=@zSG&sCYorz^=UczV@)T<4=*?A@freZ&I*A?!j<0kc>O8LGYgfBU
z3ds?(Qm)f9Ffdfp{+D`61V_JVtr0AaT>Ys{4r4+Le9e>t${13Eai*M19&P}O++L8@
zxg^<;ehe;%fjQ-!zR~JxcMsceFCFTe4VyRr9=$Ap(T4^%vR3Qn2sTF4geZ*%L(zl@
z9hwP!JZ7t$ARQeM#?5v<f{Pw|AzZ&bPuGT_$X!9zFvL;9Kw8`TXi)1gz0JY(h4n}$
zXp`0NZLH|B3afB0aMXV`Nj0l!#06bWAPS#IYD=`b<hdOl#hCH1w6}Y7Cc(Pt@Dgr-
z8(Nc=<H*;>g^km_W!`jjk?b7HB}sB>##$*Tj4NU}cg@2tZ~U3g_~?Iw$NgNAq6C{H
zs)-|sY{)EDQ8I0Al!$JI*upvzc5S2!#>Z&s>0>KdeD`=JXIT3JP$S09BRF-Bv@+gR
zdiEMqYB>%{c6M6O0lG<+d(mIkd-4`s!6iQ6xB{V66b;Q^!Mu8Jcn9o4G|YBoyF_j4
zsxiR3r=r23xw|#{i{Z3qJD+!*=;3?$OHiM{)sp0SX?-02T?u%`QO$@Iahlwph#P3w
z3q%9%#NBcxP!IOCG8TONutYHoDM$GMpE+&bSEl{rqa&qOLeaB35yCOP983Fh5beVA
zAO;vBUd|k#9x_Q?P33wPKMOs6RcSE?dKibryy5;rh_U{<`7q1LFYYM_v5>W0bap>L
z0%G!&tc#A0SEr+jqIs{oTsmFY-i1u`5yk$wg>E31Rbv?!T9o%;(%$R-L})HLTjv_s
zy+-ipDwD>f2~sWD1s5Lw{tX=Tg0-2fzDG2-A>E6Y6<QHVU#NNChHd*Yhpq#G+g4t@
z?c57toxB8B6;LLir*mqlMCTNSOp62&Iz;s8nFpPBPEg%{e$@O0hx1>bR^221@9g(4
zi$S0o*PZa|egS@y&^_o=Ec4!SVi3+-B)1|-uB0BgL)$jZtkaew$P_WlSNU`t><e~r
zAv2ErJU;<161~@cY-SWs1E;rTH!(XpL(N90OG1hGMfcc1b-ucm*uq#TOy^lwfMsCT
z#+dPvbjmYCCK1pG?n)!CUjbOEj8wlrqHj(hZ|6rcFR(-l&;MfR3Kwc{Q5eVaxzcG~
zlTDZUq=CV&5@K~0pG47~?OACbx@;q#&qfztarGp7rc4Jb2jkR#DNl$;{kltWE?t5(
zDdDB`)Di=?hqJ4~?TnEV)BHBIX{>fle^uRt0_<;(;xKu#$GNSv+6d2yrOb<ek^-fZ
zm@t)9V`_4-HKp*=$o)eEk2-b$TkoIoV~8S3T}d{Vke!e(T>DBz&iQK|#@{0Ey_c`5
zyi0S3q1jJGZ3jX$LbiBqznJ|j{&#sb4+vt{v_?2)`_EzL4TvM7>YUaKWlZ#Vb;SIu
ziLj1u67@592_WJ!Qo%lXh$XYal_Rz5yNPAis*V;EIsPU4*xy3)hV;P2C!hrpb1=?W
zV1Dw~SiPMPB4rYjclz=rg4FCkJHyJkxy)bbN^2%zjuo^?SSPf9wOqaBm_g(ZDvtp!
zldr70XP|}f?{kou80o@zdAZU@L(O>X<~*ULzyc7{Chzg8e1Ok`aS3T{o6@UCUjunP
z8#j{zKX8hvf_c)I9c8pB*cJB~hahEH?N@4)I%o_y!h<Cw(!Yj-vQNe)4Lvdgk?zM)
zrbe6Vwyso9a3e+88drMErZx5KtC75Lpa(&g;j@dLAM~}vtKF)?KYae3Ev@~a*P9X9
zHQa!QhjuSqtf-d^J{1yHebjG!PFnTw%sZki6%qm6JR-xeGyJ5-azFF6^l>7cE1d~@
z#*-l3{#l=u{m8TATaXN!a$ZIkL=VJ8M!K2-5i>pTakr_1@g`6NhtFZU%yR=Xc?$fa
z^ULF26yb-ztjcps?I*UJ>j^}^J=F?ca-BDkfxO6@L&rHSz1ggybT|2zU0(&SAL=EB
zXKlvsRH^|aO1L*xP)`((fV{f=1jH!O@ES?trsM&^M<7h1iU|3166(a=SM$k5nnpK9
zz!=<grF@LLb7WWFR`6=UXR9#q;OXPljRN_ghN4kb)T*%fSf^_}njm}+sg5+Vp`v&L
zE7ux&k60$7ra~!6&6=yjd^45?YYj_xK>}0Xn$`ciV-<zh{UV4`t3kCaDpAvFklC71
z)yu?w8MUxJ;1W(4Ba?_iOkU1K=L?50W`~jn`cm;$uS=kM550ic7s((m?@(u~OProY
z42j=Z`ii^Y@d&6>`nUO++OAwP@`il4wiZ%}m&gMGjNu<eZWg`TU?PQ4lY^PdqD(Z<
zU5K6UAI}`W<2NcekUfZP#!3o{HN*4p+t^mTh<4eFf5%(#w?_(U0#`_6E*n?dJF~+?
z?}#Vs$;nn{ftTVs@Eg0O`<RP>{Z^gS>hHDY>KElhYrDiNvHoDQ<lVN7iIoWUp#T$P
z9;0~UvB}pXzxy>%Rt4<mkLwkw6!&@dqrnN0Ym;+{TLw;FBgHWDt87;zTO1uv)*P#v
zXLa6eK%US)yCLoEkQthdOZUg>vL6?g-~qQR-)*c!#g%r_Zuf6W+e1tST@)iVX)@y?
zT=s@+oLw|z2P@l|N;-pVZs5ONgXeF*bgxbay)|FgIqfj+593#~As~IEw+~NStzC||
zld`YkMC_)0t!3YtoX0kQt169GAG8(Ag3Bc1BO=OpPSN3EX<<sXZ<J5L$Umku54wP3
z^h0<-;GsX^Wuv$l<p)yy9RHQOq8!aV27r0gZ2(>>MySv)VdMznb#maDA6cX6V?fe=
ztaBaXs@RxA#T>>CkEI3a6BFg>*(`-M_k8#H!$}54l9>B(!q|ErBtiULF{t(x54{+2
z{RV^p+Y}dA0p_;nSeb?LIK3_<?u*?uC3qWgcMyJhe_nXHuMLnDj)VwyVMjXK<>2e}
zz?%{YWeC$_ds005){+Bns5b-T+puwVBLK$P1M9CUJnJ}4KM!D0{1w3gaTIm6Y#gt#
zq+n7h#d_Z(*S|BELpC-=$c}Sn8zQx4D50c<DKzWvhb;xT7EW5IuNBuV33cR$5&)*o
z4do+TO@1_%l%&AL4$8mD%RRWi{SvC?Ubz~?q*Kuex-hMx*f7>lc;5co+r`ECkwF$)
zcg`qN-!)S$I@8<B-zbFFaYJI`ln#~<W&D<dd1}z!$+ASo-}^@Cd}lJ+2}a39xGw}4
z|J}(G*v?D*Wf<t|dCti)pjB&Dwk||0agdH_WGU#p`{Lvvz@Vxre3QJ#szDWs%K_U%
z`?y)2-XKZwiOFRZivXh`2&}66yA9@|G!2m<8%;Bs6UWw;uBI#p{d_8v0H@%%#J7iW
z_F4Pn*Syl?*+uF*SVhoiJnbz)NUA_G-?!^Ni6rJA?VHrBJ}7bJr!dP`js9g;^=PUK
zN2gd;So(#uP9N)Ms*VEPB5t6-3Bgg<25F1Iyf{wM&YYMza1&3etW+1yTj=>xn7O9*
zR>x6VRejkG`(%A(KwxCFjtSUaXS>S7X)*<&d_$iPMt0^nLDRR9t^^}7Rx^!pVtXt!
ze9U_`>XWVHNe$bCh8DEYMG&{81VrAAn|`J_^~)9OI?Q)RZn#cDh)RwDg&&#$@>N43
zRaXHyVKWI<;Ibtse}VA7?rkLG?F|Uvq)4b#2m16@CM5a>pp?2iubdo{P4{j{%)8#0
zO0XN~D$`plb4UE~>S7MkEeoMDRS56YE6uqm4sOEdlIKr{m+AWugCabT2DI~Q7NBM0
zLqR^UHl)-NbmqD8H3eTBF;Ap-*bXlVaj+)bEon*6<#&A%(?d6UGm6w4DkV-!dMC+C
zb<^eb12A+vC-^|(hI9aajy3ZV+R6zzvce`evRubObXK6Y&i>hsgBS|e`Z7Z!ssv6W
zfmji<xPuw5Jsx`7nc(XR=u_3xJ|y8TG`~j1YweS1-Uhtk_TPU+vf<G75pZ@{XK^o#
zlHOlA14%&!<%<ZQKI}%ji}1o0R(A=Yphky)*O0+D=TaSC^9`y%$uCMcuUlVDiYtsF
zXjb@HXPUQfY*YCY8@Q79QNC2BCi?R$v*eSF*uc(oj7cjy0x+uGE=BQinxh1}EJRD*
z*$MK-JhHf8Vmmc33+;ORE@6FHqNdbcud?9V4nB@i8V28#+$>VYEfCK0oCDsXer+J&
zWMN{Y)lFHlW)s(N>eCSat3^OGIFig|=!v-*k~ZFHIly13!i_qa@4(KaE@@4a&k{Yx
zr*!-ZVEE=cNv?zZ=FEhkNeXN?zg?eq&Xa5;X_GWM8XY`33d)VlXE*9yQD*=l8w<=B
z7S1xV1w)!_vGOx`>#k3|9Tx@Ft=q$qYv*u=9&^B7J~N!trT~O1(C(r_5K<iEd|+6O
z_m<2(B(T0MpZ>02q~J<Vo72q0cmAj_qjvk~&$@!rlZ!||8sU7^{QG!H+PGwd-n|sF
zJ8MxE-a4TVpybk`DmzCfv^**~;mZ|@K}|h|u1S;>@QCbfZAV^d>m=vPTaKko_uHxw
z?GVB@VHcp2_f=BKUQMM0lG#S)v~)&(e6W`vk&J^V7XHxKFZcE2H?l*R#eSiLmZEX$
z;v5iXm}J948*!u5rMa{|R+{8~>dyWxJ@{umJjdz~)rs%3pm6)OQS%nS8N|~(Rb8XV
z2t%;F1D*vm48xkP4O(sZ$V~fnG@KKMdOXf3`u{#SU+GqZbNQX*pg*@o$03<|PGs*X
zDj{`V?Zq|ZSwzsyChG@lx0fRYz>m$B;k5#>mg8?H9W#fU!G+0t?J+RTz3->0e6m@l
z%0N`dsC1qn+5L6Wy_?{;$yd|n8WFza&W4B+&MqURpyezXEFb8=_=Y`LX9Pbt?Cn*h
z{+5R>bGB?8=SDcIf5Ge}5gfT+`apruN?Mw!|GqgHR1BO~qcmd=u*;t)Y|P_X^4FKb
z+lt@+l3_H@&!4+otSZ>I<tw5X<}gjBGdvV)m}%O~k#M(H@$P${IayfgCEu`gcbm2v
zgk`ZiG&39TvZdiaFUSff_3t1Hr(YQvS!gO5qAJS$r8`BrN;~Cr$SYe>v$<Z6DCG8(
zr&s*6FWw2-C8@g=xXOO&e+cf+&jtc5?oGm#kkC3-H_wAK0a#vMY;Vl6;uW~w{p5QC
z72&nAd-~zQqzPC-;N91uf`F~$n;%LW`)oXDxSXv?wuUvgB#y8hf;_9Serp%4>N=I8
zAfNw<S-}sVZXM!f!fZ(A_ZN)NXZso=k$^^nceszvh;?moRY#!%j8Y87L3w&?!c&9|
zlsAZ*o~D>K;u)!6=)g5#nP*!xq5rKW%m?yxT{oxjke}c=%5b2%m;%AX1H|X85bB;9
z9I0oR4GO4H7+B~=C{(EG50ip|6)9`05Z?IZ(OXH$b*KKOEY7XPb>w(=Qu1G<v&zj~
zJxPxLa8wtT<Q}(M%UU6+E6YQ;GzBWMyzNY`BTm~OYWt6EAfM`vbnjpCVYbYGd!V<#
znYB0NA3!&_C1OLDhV3OczIxQwQgR-|Eyj=ur=7m=_dzG!T$Py~T^yD3<=npDicc=Y
zn&%$d;JSYo$v0z%{|RYYweqFOzcXar@RG8ULh}_xr@F7QL(VIQnm>?P&J}2P`w7B@
z{5H0y4wTyDku#B#eUq^F=|+JxZzYo$TcPNvEk{-z@G<e&V=2=iMVD`tkica|r824J
z8zxfLTur~drNssf1nnY}7Pmj#QeqKBW$g#&(Al7-LhTV;{HR^2>FeF?W0B0UvK5|)
z*_C}wAzT!qTS72}nCp|+Z2JAhEJpbMiTUA&Ksw^;GDna=f9o3seN*}xDIgSIK;%oe
z>tv4T1bn45ri+)s?z=9Ciuc$D_$7dFYv#U<bCItatf6Yr^F&Ao6f40}#q_QW-_%Yq
zb>et<Lm|N>bpz@OT-JTW8HFiOXix&)cQ#b$K>Kiw`Yx-$F}pDZu0v<Su-RUE5Z&?H
z*YH=dQeM<2KKS{F$*EyyVT3kuEpE)nd?cG!cj4KLW=mT_HCUx2Je%AhU3lpzF9n@(
zv*KQ&m_h6_G^)azIF?J~5fKHx8&6<8tX8|OEyxSB^moFt|GOrvfDXHw$FGvob=kRm
zYfvKZ(+lb*s4f+Ky)PJ?CP;4aE$wamZS!CRe$Ro#{kGXYSVuMV?)!1&5FH;o!2ZNq
zuDNkAt6Q9mKoS)E-mPa(mx}<;7Xd^G1~ZJTZCS`J+;To*R5=9>9vyDtkQ^kpMb^}3
zMWi}9oUN6PCmljkNM%!3D_^pEDLcVs7$E9$7bxTMUvk>gSgmGD4|=TaNP>|hujgOf
zk<-zR*!ur`#sntRlSBLB9<GZOg`~M#UE>}my6H@#Y@0W?)QvM)YC=$km?TR&6SkFi
zpJQHfe*j~E7QCnT#)6$e3JflL*4weQ1kLnKN(D2X1tEUc>xH@qkr>wzxjied_s41~
zDv%P(1!R8*SW#-m)~xifuv|;`>U7RLGfCy}=e^aNI3eyBp+wpdZ%UaKI5+<#+9<PK
z@i+Rj*!Y5;uv2hJfu;`6d{Lk@b#cy*!s7Zi@!fb};Mh2-&^OnCf@B&-Fs*W6hTorC
zD>v<wTGBJ~jB#O?`80H;#Q>4YnAoEm|H1`ndc{e6<;c7j?A=2S=<Iw2wYK<w>~$^;
z_}uc%h;CKq>#yT^!BzG<5{QBpsD#tB0L=*4@Jk_w3Q+=v4K72VKdQ_#QtF^3g6YDq
zY?m1(Bj8C8qP}y#SuqJL6E};U4JqDKeiJ{E@K=B^qFGslKePz!G^u36n`tH4B(8ii
zwQ`hotN`StX<`=69CDpij7IoU=Hl@5yd?D$!!ZjamWoJO9~e8wC2E*aX}uwgxRH?j
z#%QT7J_AV8iz&lfiVyWSh~z(f<Ud&MCS0SXhfA0s+({2^9=oWaGW=GU8$5?M@Sa|-
z@y!*ef0<))T+IB)+Ja5UU8r&x-#e@+2bzH#>P7c_2k^dJurv0apSQ_M7mw%Ao)4GI
z4!=)P-ECb~SdGj?udipd^x{>@#`=#|P=o-zpIyUFO*4Zh;0f`w;f5HhC-9;*#ij&=
z=HlnL-lO(HZ2sL9erfnS@GlMTHYSsr@w+V15ql$G14~3NaS|BF)CCD)dc#~o>~eHq
z*9>SyeSR<#QOqr!M&crHPJ^*cw(>d2LY=?Nx6NGi{TE^I4c2X|j8n^-K1ow5{Z=K+
zsdak<XpK^>+OKyAI<KX41EhEH@8ICKPTV+pay00Hg`?F;*P3&7-;*m6H;a~f#)ihR
z!!eEZgYc5m5uF&reOq0`)8S^n1A@>f3NJrRK$yc)^$wOzs?)xk2&qtjzuI4@0;@vw
zp4A8lA~%4}@vq^KB9vW9MR~G#A}pf6^~Vwew;kTL?%+u4Axt-i#;()#%U;@jWdVK1
z8&k-v<z$@z0FV0auKXSo%iE6NblEuOo6<8^A+@?Fc@8fuQKJ<HGvpU9m(8~A<KT`$
zq1G%JvS4sIA$Qs3)I4p?j}l1`PbrEPY%ODU{T$`WbRM&q)R=zU((k3Y3zQDwc{&N?
zgBf4GKv<AY_(#TyrjZL!47Mn7hq$In8(cV2;qwjB1DHsA;g*7q_2M(4#$F5s)DiR0
zP1P?_4m^+8Y8Ceu;^Mwd*?9HvPQi^(vvQ8^$}P9&{dW;+s_bq2SCDjgQ~~6Ym`w6d
zP7+AejLCJY;_gZKvF=ltTAv!JAp08lfc2eWZNV`!qxZbFH!uhm7-uOa45lx;yd9Ct
zj6szg2j$)fPKl0orewVoKm`7~n`$e4PbSI*uEc}l5Audg5<LxL$j49zpcQowG5mIA
z<9Z)BcnVKMC*FqyQ+}4x$>n&J%tb?~(F{=emzJ@DK4ty-m3$*LC1=H|uIqsMoVzaJ
zvsFW)5~Gntn4QdD5P8PgpLr1qhUT&yyaU|31n+gDLk7*)KF88CL}n$I!*Z;mWEu}=
zg6%dbtN559TC~v6m^@%iKsVg6kCGeFObx&#gQBp16Be-kP3aMY)97F7xEur)92?{}
zo-LwR@1x&@JW!{*lAnWTi#C9=2Ew$HSi32PWWv8h5qE298e~PKdi62kjjB>oF(m}}
zvd8mZ<-leWjT<ZkSvWarI&0B6Q!GfAUsgeWV$lox#<X%sZR+@+$+@mZwWs+)?}$bt
zKa1VZ{cUR<jxB!l{<0bxSwHI0y)@%fS%S$hLe*80Wo+WQ*xAwb)`Er-(o~vaxY!}P
z{-3%!Yl>LyBsOJy+W@C1@tW8nEBd~RS{fbXWs`+mq_=XsP5<Kjb_XJr?Ss7&#wV(M
zmH35x>wm&8Oqn`tih^S}ee$2@QXEpK^U;A-!m(Q&jf6qCHA!5?ZOxuD#mgs0NjQ+z
zFpN#C+xI?00uH+%Wi&K8T*ISDX<exgQf~{Kv?ghc-sen+lv-}xGHcGVht=PyE62Ej
z`FgU6kDch<S13L)Buv_<u1%R$QKVvF*4h8AwCh4Uw`3J>`}6s@I@>km{KMxr!-3F&
ziU&Q;dLdGz55}9llOD=LQ;YQJZF{G!a)L<}-TQ8Gfz8r0TE+0Ntd}h-_FE+pH4Av#
zt8lgN3|lEY47(~UfWQ^#sJ{3!z>5$^;jC%Tdet()3bRK{ZtSU-#&?)yH*NUkM{{Cf
zS|m%<&k=pmNkPHFjzBkav?^BjQ3gie|MGH#1Og}a9RBga_`EJ*dgC|XzUYE63S+!Q
zV_j^QIt2E#{G+L&!!9|NR_x4M%kDpULo><N?ljuuwoW^w-A&}3+I^xGQZ98)jbs`k
z7q<N!0{&PDf^iR?Q9Tq5RGf4_bv^HPr1UMc3LTC*^x-SJzPO0+V6D96ns()4sbr8@
zMpBG6ba5^FPvwS%=jdCbH>w@#a3*22UMrH^#tpD<f*_&~(ItY0KWi944!t}9%ETbi
z|9Y(gt(uXl{6QnSRc<h_J2_@Z9(a2lO<AN@FG~)8r|2{iJxJb}Zdw@RA}5>7JA{p>
zzkFDuSDp9$f3%!vCM9igid)}*Vl2S1yi2}@FdsV;M#N={Q&dT1A0!=xHYnS9?uB`G
zvhJX_64eiW!V+_O<e~{-@r2$Id~2H-+UwhY!0nt4jOIR5Ssb{{%G=tjruqT+3j4N=
z#R!#OosurxJ$vJ8giQ{PD~Ss|G{}qGph52h)nkRho^;7EEj-g)M7(Z+L$n86l}RH=
zc_QEKq|2`jaFa${OPLZa{S{L7m8)x%@04>2YZe(vO1UYdr37=IUtV-q5y5FsR~&hj
zDST~clOR@}^IGTcoLk)lS{3xd>?SD+X}LSHJMjkU5XlX|?1e50#JWUhxigR@3>uGh
zq80U6e3b(Oz88M;wGDXJA_vCjf&eOF;2$x`0JURq?Lq70@Tnj0fpPNb(nMi>vuTxU
zzaX+I-CVnN>c$m25~$pO$4Wb+AGkwG9&I2OJdaNbG0v3@JI8L}1JKQ|>^s*xLVE1}
z*ST6V%H-EvQ$_~v4cew->vf>?MbV)x!@U2?UGv#Z8S46Cr`N-#p9Nv~uOukb!UOP-
zjoTlsK>#)t+tNtHfAc*`eo0gHG&s0tY8&p=7G#Uly0OOaC^XR-L+^FBJ~E{ow*{Vg
z(1o?Cpj-l19G_g{i^T7zXE-@&Ojp>rk;_}Ki}%KaZ-q!iF`0IQ&N+8iI}1HDxyCqI
z>MJ*JZa!C19b%EK$d(HIQ%=k{=YshrftuJ)4+rr4<ifgj2iEPB%2$g;73FlmN`4i0
zP(2E|gja0E!AD3BIjH90Incc2q`D~9((nF9HrQ@Gn1VLh7mVCFs~;d)DMkG7^h};g
zs|0eCRjr}BY~Rk%z|cqVtt!~qb1jJSMZH|^;fVccn4Kke;S($uH*`LLWQ{!;T$ly6
zLL><n>GK%|-6WAUb*O8_7qDy2{j4YFTY^C%EV1mhWAp!GR{hT6&p=o7*Al*R5vQ$0
zj5)X<KfPKPlTW_>bp#ZQ{=|mATgrb2@6W1zk?5%`!F*{e<p<87_aTJSDt!e+uc-FU
z{U`@HBjeA?9D*?&Y2t^M)dXTz5SKuwc>JAOJ14NYsrI@2jIc*L^_1oPis6b`jMTst
zN-T#ICn3bgDU(gvSbMJYO3QFp-0E$fYY7)v@Me)ke9Iec`>@wl@m_dhEIw{VP%>?~
z>l|6MbZ4Y;oG+zBWcbbEwBQ364g^A1?s*otAZXwekYVFfdt(dbv+_!)(Vz>G8=t}-
zIw7(UvPn|3G1>y=##&6GG13F_CZ@#I03LH7j0hN9V7Q4Jba0gq9&9|FPKVGV(3A=q
ziV`t@s~qoqgXUZtmSq7;NbCeqQt2m*DXGu04wGg`66@vp3qTkGsVXun5bao4xCTH_
z?aLq`9kKBV@ODQ{gE|kQJv765PF`ncq-}KXJ8+A_$=XS=aIXJ&V)y2KATFbBe9?P{
zr9o?;GY(Ya9{1FLx(~(*@%jS;P~+OX-QvIAn$)ON%r>DprX-++9E!*DFzK3QR%kw2
z4dIczrN^aYK4RH9c~DfEux#JYyD)D;_M_!cGmz|6E}_vtFL2%6Gg6bf*3LfZg=bAl
zBFar4!~@{NPev$&6=9~1ydKJtwcIu3m}FIgTL~1|9}g7EV;k5)A!W>YtbyHI%-?r&
zKO`DuN(r`cAYIW}zk@6LkNa~j<g16ryf+5b>sbrQpUX=dQXMMVhq6u!1x@hNf$cjo
zKb><VJu}DSGd`rscngWJ-V39+W4T+-M-$F4v30r@(zXZ5fq$8+K70MEu_M7(R}crO
z><@z{(J8t!`P7;<+V<h{M8OX5-o~q8`E4L{v`<m!Es#zylEj&*;YfiS${+r@6pq;F
zwX;_Uwzg9*_1VO(K854r(4X&cg&H>i=5OH$h@iV^m%+?xyVsn!x@#ywq6~~{BMY4q
zxZfI17Y)3;8-6r`>XU5E)v;48L3Ezjqp@3W^V^|?c)UcLWkiwLR%kRI%}9OnnYOld
zZRppgW9EH`&dyE+Ej(J6#p6YOt~1CKoX6-m*@2aY_vAEGVdaK_?(WXi?&?RfDoWEK
zvOHZ*1#it#K72Hu6W_syv`w*!kYFfH`~w%(2MrK$N-qepC@A!D7bT0G7mlNnK&c#C
zQbAP752Jc^TDs%IK+&oy&91Gg{grE>pi&OgV|zz{UDx;*zf8XMDUT@=If;<xU?#BE
zv8wJ?)_!3BB09h*`Tjy8X~@>EDeT%u-M`zU=-W}K5l(mBrt@taU2jJ)=BPO`*A`fI
zf*J>0`&yOd7=~l{$K;?1>)S)apmT_^P&K#o$p;A3%hlz45gvx2VpQA?okavx4xO^;
zCB#(3dd<JXj;w}x*WV#Fbmy-7m8X)pMytUStrCtb;(QA{<qsEF4!8UCUq1z4wi-UA
ziWatNpT>nXX$Wf%6b-!t`(L_in&V<?V(6!;Ps&)@64?Sp<#D>%gfx;B!jIhs)WYvd
z2W<JTb_Z0Bq{+qqsC4*1)*b+$vQb5Muf3tLRn1LUZ}l_g$2cj}W)UDc(;F17NOGf<
z_)d#t?qU8S!_s!~0DKGPZf>yNJY90~Vq=^1E<Jg17@8Ce7{`#o>2TR47r{>apDV+d
zhL%5~LX^tg17C{bXHNY5m9q3}UntLg$@py>whD6cf=2}14_7;FlQ5^zawojnjUhpf
zAZ}w|+6+&;^xEo~TAe^9DQQf1^*kQ%!0b|ACJXO9P$4XWhV_7Co3EA-FZND(pw>}=
zrBYu@eb%2$JTU%L{bbFteURMf@npl4SK6I5Vzy2$8q1GMh$8n4Q*vu;z(E`Z7J2>g
zXmVSPUI+v&^^ZFtgoMF9K-V2PWBn_QGusdTdI(p@Swo6>(_pPo?7smiS<;B-Gq9AZ
z$H^>bJd=0U%%h2Ou>?7N)?y4GrT{}2sTwZ*^&fytG~wh!0a2FdTAFDzy5G|29lYYu
z3bc9n>IS-|8F3w42<dT<@XRoB6aJQst`VG=6QjEv1Oe&iJ08aa?|rj3G3wXmS?pOT
zz|fjUjh^Yn4sK~k-0qxhU~@(*E&+-?*K5Q5^VunATd=haT=ZP4Ok>53y8NwXLhCbb
zYl#t1B2eFEgn-)`9BU44FnM41>);HG$6p=n7yTOLyBeVH7TS<@&H`2NLy*g{GwL~9
zMAcfqg|=c`hw7`>pLaE?F5$g~VO{$wCO4uWrHgH>EFm<#6I4#<cs3vK6jvWRxdbgi
zAq8*?8n#bfh#ny#zNM0Jrh0AdT5*~Svmd0wU!v-CYi*dS8L2_~M_KF>eW_(z42Mi7
zN(oo;E<+X$3so^?|7M}3N|OXocDVDrGEj6NPwY|k)atcX>9KD5TI`c9za{J)MQBa|
z4E8(|vjt-+J6f9R98`w0v_xb~N7~j6l9@DnqiH`QOWh;)>RuirGnpfSHiKVwsnw$n
zkW{Q_Tt>xB1p>3K5|073a++F8ZkzBIVukScEA3T;<5tv-<#yvm9~d4y`AOY1G$J9r
z(`}hutO2CrW1L}d+FXD2#LN-!ohJkdl3ax(gm-Ia_wo#jS-Y_c_#)ndp%xVlH1FL^
zsjv9C0pb=_fm8ipcQC?cs&8?ixo6=+ek$}A9zizG0rq4V?3<FLqYB{^j1Iv|=UPui
zgq=c}3H@KRAijX)q`$^B!s=8O_ypCZ*)0~W5@QB6AfQ-(xzA^dkm`BqK!f3JblbD~
z`v{_`EAN;5#Qs%l_fNk99m+QwV7_em6ob_HwKsM;U&@gs0scGESlLM)&kKTc4c5!3
z3O^n3*6+ynnD6fgW_AMZS_pfSNq~+&zeXN(@|<NRh_I6NI|lsvN_jvyYUXVAj7fXA
zR<gMtMe8}3i-AW`53QyPP=dm;1psP4QY9Zn^jpez$wV_Um#xY83vY&V4qV>%s)!u~
zU)M|(CoMMnK6*vDrxEVP=_<=OLLa74+?n*J20GPZoPT((4|fXf&$WYs58B)r=oq?*
z(8uxd6wXFZzn85sd|qkj!#XVA&=39OjehE7s6T=cGW3SoTz0xlP~UP{CN*G2u&Yyj
z*4Yg_`^_6`G~RCa9AaZ4r_zGe8|fo(QJeU-G^YUJufvZ%dAsLtb**D*pM3uqC|n$x
z9`TEB4Zxw)F&58|+-dMdmZ+^R%fK&@)lC|>mAinu<lfs%e!1leSt9#K9kMW?LUmEk
zi9CC04AINmHSmQQ&H=}nUSx{)WoqqP+!kez1~%vr!`bQJc;&emb3(kS@$(cKpeB!%
zJhw~NreO7{HZ5Rj7hRM^SV&ut<vh&>K)0v6s>)wG<Prw-;$6zhgMK)|w53k4@R`JY
zvnhRAvbl;1;hJ<*=3;ZskB<zZXUy1?JKiO+$y9tY#*T>if&yw!>V1&_*Hn(_9GywF
z*3y~nxTZrMRYPh(bcWz!Ai?Tu$XJuifhw&=*AblmO){HoR&$6n#tj7^t;$aG5l<VF
zRwXs)PxU4J(x_DY8~}K<i5uT<EMH@y+++MZ!sBgRImmH=#YLdW-W1P=ar_AT6LMT}
zkjvaZp5OOPveD;{D_9P+8|*Y#y8EiG1Ra=frmw4Cv##kZ_4*qHzzkv`zsS`v(Nu)Z
zN7{ut`i!+$-PK-!__n|fL87iz2f|e$M?LCMdwSsYTHiCxfzg9herB30)CKUyq9~|k
zfxx`<Li#DnR(d~NV1_(eU*vrLdk|_pwDIqYj%td%Rf?@qF3`ijl%2rIoTL}<TS`nm
ze}U|0fYiUgwqwvLgIc3#Hcs^Sq<YfT4|;7USku!}*ny<~eOlqskbqU`mN2_fLi|cG
znIwyZ%JK>X(Hy0h;p(b^^c8!^j`*Ms9h0K_Gr@~n1-AIIoy1^BS1wV8x^hn_i{D%u
zur+%Y*}e{p;;9tf(>xs~D*eKGl1IOZAdW4?$7{PjZ(?GtUvVpn>U<DSv*+OB?ngh>
z1z*g06dfy9z1~8$Oyy$3qx)7sZ_4($Rvg{YK9EY@KX>Vr7)8?4EekOw>trASm1Y<Y
zHITyE`^^+vMAD%{koa|5XI~k=YwH`Jdgq?KxmAt>w)GrBr(N8UqSC>43bjMkI{Fba
z2{vtNXxYb+O5iU-G2;8BkKI{CQ}T`ECo7=i$(Hx-?y@ZtB%kbpULlTa_Y4pfvbb@2
zq<}-8RRyzq&ZcM_Qop?HS1f2g)kYgr$LHk@dVnA1=Z_?c;ix@J_U}cKl_o+5?D!Xy
zz;uIHu#*C~@XA$}8T(-N7LLm^v+`(H2M#S8Y!~lF>{IJUxq;=!poPT?BMgo;$7TU2
zh+27jRlrMG$q4LyXFcp@{!>g9Lu}IKM`7xH1C$sKL_`=^!&&XRcu+@a^yC+jvv6t~
zFW<yRI7GST!!$UWf*a3cm$83H7gnm%tqqSColch<ne5Q|EG~Y~uvq0+VF|0`udrcK
z`gm!<SQ43{p|+pCQ(F-g7?Jg6C9)$P0mv_3Vhy=8M3M{2ix&BldM`~k$nV`u-cjC8
zw54nvjHp-S7;$(&_sG0gVMe5vG*a%YD+c`mekdwtcAvDIYz2vPZmhM%?H|7waK`>l
zkkg~Dns}dlx@TAT?wW~|4i9FWVVAQ>RiBRr%xGv*p2VXuR<oB=;X{<d@#3TzvP51C
zjh`&oBMI_<mU>c_pF}N%v}Zu9FQY|8F@(S<;VoWSVzTc33y{B>h8!k9N)&P;U_2p@
zEr-aSNKx%RTb!}+Zh+ij^x}6(m9x(sAni|mF9(}Bz+YfcQ&>COahdjzFEEVWbdT12
z{lK&>D-)5?u~CJcypKi&%~{H{H|X`e!rk%r)+R$+<Z~Bm3y^B0cFY(&2#AY2Iy_U@
z+iYfaZ!igB_X+#7!qw==lrEHQ@SJlhU}!3pfjF<uP%rFYnhliV6EHf}%z_jK<~_^i
zqR^p^G$&U&g<XNlFp^NMjhbY1mkfAhJf^El{iQTQ5fKZ1Llq8Hd?)oiH@?>x8eMac
zla>Qt7TuQ^ModFOc%4^5^&oo?h3jxT!_}eN5{2n^U>aCUfU-2;9@{KL(`S;{F&q5?
ziyn}tXxj~7V3ThGON-4wel;YmsqRrKkApDJ?D=%pf%_&_S=Bn!$dw>geg6Z6Mu;2e
zM(h3on)N}*HH1F0?F$iu+%yN6ddI$?_u#^Bd4avvyzRVp^S?NYGg8Yid1CgR+U(*Z
zM7UbJlZ5jIK>pTk7qM9{I$T-Xly(v(UoS>qHGtd&33vdjch-!7bZU=VT^&$w7^_~h
zh5j=Q2};#-Lz_STWqkWyM)Wl=$Gd<_=vWL1pb=kDV{Th8-*F=NV+2pbJpXd>Q}8Ih
zWdnWLSfSGk0r*kmm?Gk``yC$&1YTh~z<^q~7dnTNDdzr-JX^bN3*jY8YL-x68VyWD
z19D7WGgA|vYikFIfP`!*c7-22WMZ&geJ87I&^a-wmj1rxW4#+DFqTQ?xL9Q*%?WVV
zC81i_PxDa9J+<>#<L(D+nRc=s!@XkkqZF*(?8-T(Dc=DSyYq(E5OxgPaTB{Hv{>1N
z64H1k%`b$HQ*<FaeJ=z0O|cq#SrcRB%wp5aZe?iBCa>o+h2W=^{+vI%a`A;YOG}>A
zTDn%gOWhM4s!4c(5??JMBe}<cXPa=r?(4)Mr43#Nv?73(jrqn}C$SyHdL)>Gh8GOj
zH5=C&XD`D}vVsX&U=g|RjH%bweIC<CrwiH9S)3f@LLGh#!AF=0!X>j(F8X_|JCA@4
z$iChdb{F4kP;a-$-;hyoGdZ_N$GTl6Md@F}Z|-!#LX{IHQ%{^C@_w5+I}1|Lh)Lfy
zq)h*tA!-1D1F5EDhH<bbX6$83DIR3^=G4`R{ILG@*fMaQKOcer@qX9i)YEf6^+`c?
z1B7!EnGd6<ElS$2!`AMB>9A_F{HC>jo&JJ8z%VRwGdyYq@p@=&#k8#cZ5-1$CnZff
zm25QP#!wp@7hty*I=j|o^D4}&{b34$8!S+p#D%F9N9LcD`T4YKI2N6evbd=oF8P5P
zKZn=?kBka^iHx4?=96makjd)z+VRp8=6HquC@U9|S$!DWiL;2XR4-Rg*EEIl=>lE)
zT{u37W;yC}WsReNlSaFwGYfk~YEc|g*zI_?wDk>z>79ogoL%<m_-(SN^ggy2;k(SY
zn_J{OU-DV3Bw8X;)75yx?)|Ppgej8oYL}3BCh#XkJy8Z6LTfFtX&IyxY0r5f(eVPA
zUW#x2*O=rbO`1Z*kQe?wXE^nJ)yi61;Y3~%IyCQ*E!o=Xv$V^zhV$t1vo4<^GaMJ|
z!|?*_n=}LjuabySb$}>P%z)i+nBGnefM9!Yj1QyF%`2!x)sXS{NYrKkw1F&ohu{Ds
zo0BUIfreQgCgv4e;sYpOmemApp`@pCs1V9Gn>qdiKY<>&EU0cX*uD5Z`*D5cQofCk
zyv`__Qwkz#UeN0H0(s#pn~M?QFc}m&*=@vC<C;3RR@{~+B`V-Mts&<wF;>$qlV!9}
zeD0+X$Up&#x6OEJ<4kjZI(vEgphTI+=d$e=K8&Af_;KY2(P-VQlqXRVx9_mLym~VI
zfSs*Yy+g)6#Sg*>jJAtbQ4houyTTE2g`fs!X$dO3&4C3l09kSFWn^7i*MLUtk$|c*
zop{6}KU2|^dV4Vlf=?+)Q@Z03w=Yrvdiu*_hGDNJHSvvzPX}iX0F8CzEQueFq&eHY
zC>pLx%)~k7uL2JP=i|BUH0nKdo%rXxI(BA;&Bm@k2r@LlJPO%A_+ZfLghXzUwWOJa
zl>u*YZ1Lnl!Zws;KL~a(P!MV!*9vyq5!_L0`kg4M>iQmjy!s-NGA-1|4MeIz!2cK(
z@F~aqWm`gq5r4!If{ZT4TEdoAC$vue0B0Z7an3`b<&KB5No2pi5=1muywCZ(Qof?q
z4|Ox;*|&{dFQ1jF(K|#)s3!MSSJXr(Oh{p{+&FO;bddq=yjzf_3F@PNHv((r$<oqe
zCM$PV2pv$7;5}`PE3{SMONE?C3!u>_@YV|9DW5OIwbm`wZp}pIfQ3ywN_@9Ecfmps
zGspq<dvO|6h?Mqju%dZCMpzkgz|KJ5-)cGM>!gk60v(o=yA)>=@M|OY^qEr<PdBF}
zd}4!B;F&yFrs0hAHvUfQ*o4M~)j3iA863p<@M8VPx_Fn%eHu6;dlLfpEoQYw*To4+
zO*Y#}HiyOFhlQp9Q*dJF+Ej&NriB*)Z^b4-9z01F^>$#z1#&OGhBGhPX)SnV<E%oC
z+qnD|f1@O}{T*EU7chqs94tT_8mj^c5%Eb_0C7qK3DhMqpKJ0plf01*iw9B@azaL<
zw{XfY@M`~8<y?(4NdMxp(a<#$5Q|^EYlgqXkqJVm*PMfvmaedoG~(CD381#2Mv?#U
z-c(T_RbS(A{Es=tPvdhd0v6_-s&;$E;i2CSOh!NJlkXxQaRJPthdR;uY8RKHs;MF$
zw9;it{1fM+c^rtfHFpiPOKy-z&Tv?|1qN(;=}_W0L?*?d`Mva63fB#>^&YD+5TQJz
zTj=xUg!8kpMS3j_%TBU_qYW|47etQo<1#^ZzF7>26KMG+u60RrE|oNkg?QM_N?yIJ
z(qI4*EOFr(t46<LfF|wFbi1~|t4^jwVjAdB4#n?KB^7WGhx%1;xVTbY<R-4b!e}44
zVF{)(3}Kv{o+>Ki9)WF=HvkQumu*&d+h+D695@6;4~}n%L_f+i4=!tMH$tT!8byuP
zq!En7CL2>Zl)Cl5G;6B9+H5L8TPZdrZjy3^VqcJYciLRMqZLkY;iP%z!6rn%?2Y&o
zteG<Rzk*iFcu~t5ytQy26Ois55%K<SE^6yATFJwG#kCXQjI8V!FctXk@mT~?db);u
zM~Ltzb(#6|K1<?EJ92|d2aFcbMFO5#XIJHJ-1n1ac=hl*b>4c({Q{-%Uj`irn|9rT
zjP7`1U(B5Mf^(!Bbd}Zs8s{*|Hcw3H5#f!~{U1YRMSKDhm8#o04!SQyOfL@OjX$eN
zz`ktH-hA)O7O?iY*hDIGBZP=@aj`H5s&N*+1Xj5p=%j^%%Y*X~6-FNsfo{0N+1<R0
zy%*nRynMS(YaoQ6z}VrcH<&S`68T5)qU>fpnv@~Fhhj;5#qJlje6>@mR6Nx;`cQ>o
z=tGo)uk)hWR^(%Mu#thfxd>D#Zi5;me+Aj;5IaL`{|rO9ZkBRc_)MahuN0g;kC=b;
zY4+vLtdXA*f;H-hC`<LT*Pg9YZHGXGN{Dv_v)BWocu*%N)<CL-Ml;vAUSL3nguE(~
zsc8U<q3L^Od_5zpA$kXIn%53|`w|5_6TWlr<HvAkf6j`g2S1i1*qGP2q_7w&2%+eM
z2)1}#KW?W-$EU+ZdeVqCPpv(Eha-%cUpvBC{`Q}286f|5^i>DIwzOL)w}}+fdrpJ@
zI#diGT7p`Bt_i5C|4(XPquPsiKC#@(CUAXrqiR#%i+QdwZkjsGjZRqv@qp}}7gy$@
zX-xxXeOFM%{~|flYY!+_M)%g;DI$Hnck=<#ykwVkNLCGr2H?aiH(c6RcA)AT6@8i-
zeL{uBX`mp-ni^$|Z;$JuJ>nOUU!b}N7!u(Y!o@`LUuvT7H~B-t{dP>BsJlYD1$+x5
znGX)-Cr)m9j>pJ#%ybsaoOiuQKlC0dpzlPNJIVIOCJ@at1EKLryV)6uG0gwqNW6be
zxroCr0wu&{7dE`K<Rm@KISQjdY{ILTT5i&8#%aGj3Y;7H?>%92EVOhn^+|ts*Kba1
zP`o4_Ez&%{nNal%97Y(H71|EzZ~Cnpar)KWWmN~UR;l^VgDeU;nLZnAft0$aB1504
zj?1Nu!Q*YL)3WuE4wa302J6+*y1l9S*7#$pq~y|}kjJ1C$ueLIn@||TFdId8Efimy
zB>k`LgsJJbejn-_m01i_rHy&GhMLYJF}&11s$OYfO6w>l(X19GlxI@s?60xNuh##M
z_AT-!t&`6lhawyvXqO4aqE9^rXXl{j+e==)d^u3!dGWpCst5}I*z;5OnfbL!9^?7N
z@#*BlW*dq_T9(yZ)7ZW=DbLEFVki+05ei$`&j~PghQh{;x*KZtav<y#{2;10wuHR*
zzVQhNotWhKI^A%creg)AQ|$`O24%yV*JxR7bW7T1WEU7=MWH8&ugvp6G^+iwr5Vl(
zLDC&}Y~*9T+F*-pfgsLO83Gy{hVeH<?s}~y#2J?8r}1bNZ0h|m?SDqfnek=Z<r5{Z
zbjZL&35<e|zj3tc%SD2WhJ-v@H=1!NIt=!%!Useu_?@I@J0}dp5{cJk1GeF?&j7@I
z>&_o3?q2ovWCuPHxA@&R)7ubP2*|@;X}YUDqaP9vz3FS9vptDGoh2#{`jSL6g=y?i
zA9Mskn$GDPFp{%sSVk5qdLq_HpB$LOJ@_MQ#*_R%^|U{o4Yw6deL(*&>I0fasj0&S
zvmNYjrJ@$^e#USn=}&QVKy8(E7E~P5+5tEOEl$Up9CBPr*0n7E?5$J|MBLL)YzN5+
z5LL^Ma72PH<&|0nb)m(>*TlYCu-*nTAg_hrJh!@^mTie=Ur>Ss?Y1t>0^`FAk%pz`
z#wAD3N*EVTrrg9Oo^vVm^^Lpi?QeyAo|&ss!yl90F@9o~TS0ET4WS*`HsFaKLOIPv
z5T4(gHywkg^aybYq2Cy4l?qF@RI6g}VU*RuGF`vxLPEYUfR#@YjnEI$u-EcEfvyuY
zWMx!Gub2`&o6MH-J)WnzM(<XWKcrAL@-i<fm7yttx{;bih19mu4z%tEs1Q5IN?y(+
zq>&coFCORyPdVPz<^Y%&do(%*B5Ou0pu(Vlj$||axSgtBLMvXY2Fzo|4DdQPiQ2;%
z5QX<c=4HdC@Z_u=hlc&^`?8OZh47<(?W&l=ZeI9vH9;2ZG0hd*FynB!4!a|icPtvH
z`$|2VUj9H!P0m*#XAcq(Ja{U_*CTB`%E!CD^#(MH^Lef)!+gvpt=PJ%G~Pr^6Yy;O
zGsg6Y8K3S9h(Mw6^iRrLPne0rzrx!U3|@NPFEj2G7ugvIMqS5jM&)E$<>GG$%8?G4
zfUV{vIp0j5*uyYoD`u1(wppwB2>xG=sl&#zA2FqX?|7TA{|l5G2zJ;sb)MU+>UETx
zyf{=(P{4~N+aM2%B!`hjstrGHj_y<$abSj1onN=|v)lCA6TK974F4En+PQx6d{jJD
zowY_0vSc!qV-lz}wvp=HmcYqA%;$N46&6x9Ck-nghUP9Pm0WCy3wmg0L10(~jgbJ|
z(5Sb=tpBh@MOsGYo?*V2Z*~+M!6}@j^_7AUhgUg8BHD}cZz5rg#_#)f5QR8C$)44S
z!X{Z&&d~&^lUJwnn^fJJdfUG5gcSCZF4T5+ZR(}2#z057W;(VP%l!y7N^9pfUNSQY
z>`e&xrv*QKCh>m#eOf*A=tCKw9GbZ9*>B%J=a*f#zfP0g!?ocR3*47KPVNKZTbH?1
zLED1QO~=_&gIw2PT_dOXmlD>F-+OSYo7wzex`uP~sc3Pg<^dLOGkVE4IUn!7d2`R$
z*k;<sqnQDDR;;?Bf9GP*J^@vEdRQ62h@0}XbfpCtq@&KLN-sSew1hgoa_S{{FrKfO
zDsS!Bn}h1~!26Uk3&B{n@B=K=JI=-IZ&3()VWoWAde3mpXlI4T0M!u6QC}P%7D!KV
z3!qqoL%a9LM_X8plzhDEoFFB>mFB-V`z{fA2MYAmCxmestM7xuK0?}QLNGMgQUyw;
zAFCwgkyl)y5lF-*VFWhy=PNLxfsD;C!~HC^!IDn`_u5NZ&ilRG&be!`gM=aLTQPnR
zz*FJpJ$O}Ehgck^P_UTPEd#2aEU=AjO#BSmyYb3|pLnfBYtT*M6%HF9^SyNa<y1SQ
zLp$Yw)puJis-0EKipFm5ex9lkHd|v7uI(-0ee603F^S`kZ8m*;Xefj$&e6y5zoj~X
z%5DQM6+Lz2GWJ)~bA>7$1Z*QG$p-=lQl`J5wZ4nGL9h6Uzo_~BgUzfLoD=cS)9P89
z3C>ArBabDEv6lz6-118ii+k%Z()4PkH~Z}}2PMu8wCXJNF&R;bAxKx|st@_xLt3Tz
zH?n_KDN4s4FXk|vVy)!x+p~jmBps*dLx4bE4W7D05Vdx%S_r+7shBTf8v7qn$;M^G
zhap$GH7kX3+OE4W2mr2xSDupgEyE7}*OQkNorVe5%Oo0RS(WCwXR_8s*0SZ-9U9-~
z>~JFXK=}-_9q&c<pEg?Z4U)}2GSRKLBXQVoL8{gR9s^|hW3=;M!UZWhV9a%29;fmI
z0K>5$vNzdwfD<HmI{etH0OC2XD-^Xj1rm2mUK(r7Oku$%w?<m%<y-k|R7`&caWHm9
zddD2xy??ivkMgo+FRC-cCeH;Rz8c7?XUIxUx+xnlFUZhBI6je6_*!HE{b~ZU3=DrN
zY6+Ngi+V4XpF`=Hg70Dv{`pZ5yNd>vr27DQv~*925R@0jKB+W#U(IeZpbix2;uNF|
zJ~lDOD}*0(_#_e;*5URNTy=uohu*tt5068sX%N7KD9jLv?G*etE3nJ+`;#oE6=?MK
z_6x_m5=QoHO)X!-aDJb#wY3FIU+~JTsa;LER4hRa1joz;lZDOUhN?=EKPACaGsA;i
zHY4T1R!#&aPP6Sh{|He`4i~CKKzI@mfE|?^UU77{h;y4xiwnfIa^+`$BC{6@q@RN(
z>a)mQxJAQh_L0~Y2_YT}Y{JfwBGCNWMXAbvqhA8OdPH=ax8>Ts+U=Q(oTxjE5IBzQ
zbUf7kWFz!2S(7joFA)Q}Q?R8+<NEjtzsu5J5}w`0$8~di9y#5%O%2&f!&e(4N^Oeu
zr9e+ow2D1ZneGaqu$4Co$T;G>_&Sn`oXHh(vH!mMcK2Ure^Spp6z}4}r^ZXP<)T=B
zpmZL4oLMJOlaL>&76IJK^Z(<c^n4#&%lOw2&LiLWzww24!v+`f-X3KXr#DO(R}uRf
zAZf3M@U=NUH_!uyEhuaX7Y|&F7QV$H?kWdwuD4RzdW=gP`yKNr7;uP2hkXUno|I+a
zWFNa`W!{D$r(V=lFbK~T(5Wx}nl?B6GQk4fg)@<vvw=!!{M;oE1x6`A5At35t@@sM
zi;Wz8x`-MN#&Od1;BCe;=3dmws#@$}AQKw53mF7#e^|D<Xh8SfruRw(qBNM?+0L6*
zhcst=i-Pmk(f5@8QQAbNx*sSSj<EFGCs=CQL1^FYh7=WX4igI0vD+;R%&>KsXWn{v
zO2afk-^Q7f6t+S__3p)zfyrk(v`=qSwNxhv$*NAZDtKW^>sS$EK`GQw9xG8QC{Jo9
z2B#bh5sAI-o=+AT`Q-;9_v!9$<O(Y5)C*gz;(iGD^gLa(^)iTV+UfSn(ccLosJXew
T9^#MxG^Rp#;3aTB)1+J^hdvjI

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_fifoless_1geth.v
new file mode 100644
index 0000000000000000000000000000000000000000..e3179b7129a631b4ee269cd3074800f3099928b9
GIT binary patch
literal 33736
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT-+L&|Uw
zKgX?N5|gtzu4<={RuE2Se~^XJTw8G?v5I$_ZWyxYW3T*X&`BsR$kLF+st-h*s3R07
zJMr_=luzVYu@nS$xtA48;u5kaTZQvGhgzU#r>%4@zQN%ryhokQg9bC))b21T!<{Y$
z<`DA#1|Z)Akz<z$wG%#a^Ji)EPshpe<MU+hLls+$98b)~>|?AdJ|z9~n?~??I8l+8
zBuaJ_vG#1j6M*g=FB_I%FLig&0WUDX*gXz$q>Pe)BhNZWCFg_TzotmDB12Z1IAk8=
z<)!_oFG1$i3=5DxNcI-B{_ZPi^&F(H>rcQ!3LQ9J?+#nq8dxZYqvtQzKIG<Vp`}n#
z;{)83u`r4vthZ&@kSBPBcch}&5<?gG{mvG(q<WT(liYUWO<4Ra)W<yc?>2~S8Sk?N
zMh6J0sK>?e`jseK28`SmP`XonYSXR`B^iig><u#eusk8H^NRMK^a3F5z1E-unlgqR
z#_FT`Y9S@OdbqUIcjQQ9bEw+BW!XR00aXb?P+T?X{^b<+dl8j2sl=*#@UUn@sL{I8
zTr15kkd7J0foX*ezFeB4B-EhdD*}s!I$dgEv-A!HwD*oixWZ3X)EddrtR5pz67tUh
zkS-6k0q?zins}$V&h;#l7RBZQN{Ofw1;vW%uhP0LQ73lYWM?yla8~JuXM&d>t$MRB
zpL9rM9(re-9QH`0xn)x`n}SRB3?JF_lzxJ5dgJ)(#Se(r$&cPP{?#O>enzj%wFLN(
zHlBnM{Ul8EB_%x%G4?W*N60fzSv%#Wii%900OTgCj<Jr3ga!j1S-Gq)25oAKytJ52
zPmu4M6CAl|=gXlkAMKUN`ovC6d)?hfMHh8TJi-foGP`^QFc#NFm=0owBVffrsn)Dx
z;GFf?j-D{u7EC9cRh0j4$7jA;Yrmi})CF(Tw1>`#w1$PD)M!iXSrM6Khh`A600LeD
zqOnd<cv9?EU?$@??T6*4W~l}HzqC?5=<}};*q0Taw{r@hXbM0Konb(i(mibx3xcwP
zLBPUtbo{x7fvfGNp6gf|uOUKD+B*hAK~1J40}?1p?wwwG!2O}}WnZ@F=1(<1lDVcs
zzD=K#8`TvSXUMZ;81>27Oj__heo2@a^1scPbPiI$CzO+Ri!WFhSPln=fF*rx^Ti7g
zQi$y}-(<>&7U7&QR<O^5^vi>gHqDJ?HBXYG>KDLM^iHgZF|wx1+H8dlM&4gHw!m7A
z7m#e+?LusQm|beh6#($Z*Xv;={wDCMf2EtGrL-Vz1WM9z_y0>23k*lJ9^9NKod)WU
z+m+tr3|9SYO_zcly_?~8V4ktmkKM#qdy8kUb30gxl$r)n?tX46sqS<qB5$Xv(vgs_
zusxN6?#~|&eoZcb&~(j?FQ-Cgb{3<NgnL?0BV(U|d{0e$(XDTvTDIEtM}pPrQXT;2
zAwMERs&YjQGcgLXQL}eBT1hcp?)7)rL&(kctH*bjL)Vj#*0%12k&Q~St3I*LtPru^
z<SW|RJVa>2d?`i6K1R?1-BfnQ`wPcjPR%`##)64Q;(tdkDprPkf~q5Pn4Sv?L+5Uk
z4Tv)fga?D)Z~iC8>Kb>>nc$)^fYVeFLwXTfw-PXk+?acy>I0RL{yfjq@sYaX_ENpH
zc}M{sXC(QiZ-E!#&{|*HtleD=s$(O()lyJ$G8Y~Lldcz$0E8rOpI-hBCfLIrH!)2g
zTDFkt#ls)ZD^*wevpSghxw9bxtC}l}Ar7v+_v6KEQGfyX;>^z|09ccBb9thvuLmgF
zmE>J2Z+-&_(ARhT*ZvVH(<h%kpXym|4Q9=rX)(t$z`xJ&r1zpF_oW??9M9pTP_bZ)
z1$vc?5PpX~njJ|4i>07Kg&tjw?S0GG-cX)9J|_X>MvcPw7}$OH|AHue|0)uTpi`Zg
z?-JzF41k@!dI;f&<U<CvZNKNCgr{K7x_XfsT1l~WVN*?Ig7e%Rn%@5O*82QO4$C&=
zHy7JJIFPD(Ba5#G@ej51)BxoRI0zJ}=*7S(y2>q40rj`2ln$3106z=dY+VAfxah3m
za9)o`N!l5lNUbF?nq(>qpOn!<qpFh|bxz&;Vg(#9GU6@m`G{Ti(a(4K6@OG$G6ZsM
z1k*PtR@`s{W^6@VQcDvTU+#NCyA~+^Qgn{&=H*rkG!=X981A1(4A_E>_+>tZ_lS^1
zWsRNPSOMUt`4H&2axit3OQ~d`EO&blQ6IC9U!#1lQ5rCal+AOP<T+J#-J7i%iQc0a
zJy!di^LDkJ{L5)u_BVV)Ws2^~4HxLUVBvOB$dSQN&55Owz>ogs8o_h*Uz%Hg)H13|
zK0F42!8CXhSb`^xFR`)0K*-PE!AchT*?_r@RI=rVRyUp|`=OErJ(w3zKY17}01k`3
zeu~EFnO&jnpghJCQ9-R1xojAdBr9<xvVq->eN%vR($(RIN#r*!F#=l(>@KZzxwpFW
z(@4yz`_>LSPc=~zoR;0LU@~9P%+x-!7zX6HZjgR=!hm!H9(*)%GbJmPHw^YSTa#~P
z08I|GTI?&97QWW|vRC!K&2BX9%QJiL=!kn7FR!{p4J$fP+7t6SKj|Y+{T-FRjQ-)T
zaPuLcMt*?4<99-|+xCbzR=g^5v#D=~kc+LIQUD~8Rj5H!!^XNs+)d(AEn9o@z!M`~
z(yvj)tjG+d9ZJq$r+sj65X%x|zBHr+9r3)RaCPv<L2}=43$g`6eL;41!srd)7o)Zu
z{Ov|Noc;Rn6s)kpDYDaM|B8Oo+3~RHG5T_(_Pw`#2I)aar=l=$ehzx*S)bQN%SGuZ
z|3Vf{q9>`Q35M=lGR*2SyHZj7;ZvEBY}Jw`@`o+T(WJ`lMN)15-Zkj?sX@^B;5Ku&
zic@7%aPf`tOsz<Aa*wo1tvry5w<erE9okuth3Tc%6#P?EQ;xHjcEfoaCpX~L&f~QO
ztZH>FPhbLV`ny0~G-(*+O2|rA7TvukaXdLovO*%le1g=DYZkU|0G%&Rr^&?cu*3oQ
z`uPhY?>1^0CDAsP+#v@^1vdo2LKxW=$$u3G&3QxIp_i3H))pm!Z*mJ8TC<aLMUfTp
z{iaZmpsiQUCT2LwKVY)0t)$zzzCESPTRSl2hF1ycwZ090L3grv(Wg^I+_I^f647wF
zwO8LzVg;PM+_VxG_@bzFs8UTM#3gA=_%FYK#g1bdUnZav+IneO5%Aw}tp=-h>jY_+
z?nk9?sKj{2Xl@c`8Y#y2+uAqESLj;#kU_KlM&q_l>#*+~li)?24jM9fDS#vlL3B`%
zJLcC(HRU3=h7AnkU{F2M1=ljtI3X94=0i+#u<P2~fuT#8Sd4OwM+gVsDqw^ybA(Q@
zmziaUv;RZ{I>akw58Ux@V!|S{^NQ{myTqT0j*Dg6=xuy4_B*0txU8;$X^$6%J@M6v
zKQ3oM0zlIG#Vevhs0k3pGb#1Vj}Fd4PY6qp_pzea__Z1O!8u2pj9kqsoW9SPHg0SD
zmxx1uqR^=gr6jod<J{SCEs+y9CcZvwKQj)-D$HIn+p>j!XJ-Q&cWDl`sq1YtEnn%l
zbsnqbCow?JyU56b4fU$Z{a@EXM^@?GLq81=C_=0s5~N<yiCcHrK{*lz9aw;tx<n#7
zNyd3?KAz!r3DGR31}uPMCBlx*GP|26kz@A?qMoD3iO##BD6(mlyOlz<fUg<CTAo^K
z9-h4hj&C~{{g#_r;hgGY$b!BG0XOlLn~0ke3237BQ+5p^b*jkjM-|zd&<!3kANxJc
z4=~P?v1V~Gizclp@sn6P;!jaJ)*#^V1ahZ`%EJc#DZt=VonmX@kn}le&E%MvcxV=E
z4oiL9Z1AatXklsb+dcXx(6p*<iUF+cj7c_o^yvPrQOfikGM7}!L4)^b9js)`lhB!j
z<glu9i|HbV*6)g!9cPqZs}rXqiCZ;%ZsE<^H=!U@U&0gzjAAKm;}?43AQQ|K(y^z~
zwmgI2>Ki7k<+Xt7id&Ska(J2<3eB5dhO6@D5s(D<Xw}UJ?jfQCKXpNNGbWE-ta|Sy
zCeL;2b}-39)I+@eBayW?;1T4G?f_;_j|<>uK9+0H;m4V8G~-!GQtfB8v+y+D<IZ={
zYVC!`Ycp-Q$HLmm-KU1Ya;cpKh#pYtUGJ!ty$|mCw+@Y+{1x6eyoqpQUdawv`-xvz
z@nW0!?BVwPRQ8Gk{MmXMiq!T~vexjBLNFd|TX;3DL!#FO|KaAr@(YtbAktmFZEiC<
z<+53cQ$8HZ*)7M7_d<Q$dF)u5=MZ`<<PJ^BA0I}-m9m4kd0E71(XOzoU(t4=v!@f}
z<&a}YpiD0E3?`lYh<Ha!vTBX#3Z_>Lsof4SIJdLiF~jFTUdwrgykja`1)!2iQm5B;
zDz_JCzD3V6OsuRn9`Xn@kv(@{_+#VT^c_mHMc$Ag&-g@i!|=dawMu*Fz~S=gp1DcZ
zbu|m!;Zy0d>B_TctCATfLbEbp)i5>RDh38uM#eLeW)Yw{H!9g^#7@?X$A>q~bc{+6
z*SBuO@>)?KD0}fQ`M1v=e(PnIMe7!g5J7RYn%dqy08KTrmv`u4n!tBU;o?*ndd)tJ
zf=?nOJ3_>wGHe0qd77&q<AUk1GFGP~isQ08t$#%%oezL<q;<14haNK`N6a?y&ABOD
z*n%^C$n$~;Tr~V{fO!Vym=n(xA^prvV_4b`qi`tou@F5e?5sWbP^lRMP(hBqf^aSJ
z!I7&C@<$jKH>{r-z{~)}fm&+c*swl@$BWMNDt7oDaeRbwPWZO_fQb{s6Jg$|`O2`&
z==Lj_gGec+9TZtdN89h61-Hly#DDT6=)s$6e+Mv<O&ru5nZ1TYd$o4S-OqN>CNic@
zg1$@?^w<u)w3{S8{TL%>AH@*6Auuy4tGo-6OcuB%0p+;7!GwPYdT&%m>L8MvD!~JQ
z5-W#X7DC{kWTKms3P0S2+WVur5G1(^hs1C6OC!VF5VA$97RLPGqxXCcZ7B<hZ8u+P
zRFo@?GXm7BJyjpsP-l_0bV0<A4aUQE8q{bk%bcc}<T5kuXsnY_IK_7@BA(bj%#AJ4
zyo`5_MM1X4Ix_*Z>3Tz4MG>0`wFMHOsNIsmjbhII0fLHWGVZOwce6WwyFGlYpX+kR
zBSo<~G9yJ_)zhlkUZhbHX1ECzA3U^<4}+&vsjW_8Y@o~E#UiG>jfXV+=Npj63mV>a
za4tm>puJZUWd)MbIT5*yslFOkKLERM-m*>pWTQ2A;VL79M`m_QGQ7xUA#0d$f+F6r
zz>(IpR=o?Ea>e)^F@SZXq$vJv`LDLqQ$m(Sx4C7u{N2iV7rsI}uy}#B3E?mh#&l+-
zk3twt5F;E%46{feqP`hF*L%Ko==ga3h&R?*jSWck|J?GArc2F?&{6jPwJkE4jQdPV
z4sR+!;P+QZwJ8VQ8R|*v=CIxT3z>N<rH9WYBwXF$cQB^StLp>he8(Z6p=`@{i$3s=
z)6uH0z@{8LXEL*qY(<zvl_&2e=q&PD9(Ys7Q0u5vDm06!j>D~F$M+yym|hl5mWpt-
zfbHa3bGQ{Wm-s_Vl1CiPLq)~cBy|c~{h8a`m{)Y-QWanah&=bRC^!BX*v&}pyaI{4
zU1eryafbpnxx!)R>sH=bX`J&m=18G@c}Jlcdu$ttyoCY1HJKlARJ&b*KYNjrsyh+x
zbpafzi7L>KESreU|1CtRn)h==MTqp7qc7+;TsiipVqs&+a60B2ebRQX3f3dH)FW)&
zIj$((V#QxHv;J&qG^J;Wg6rHFPB@Ff2xYok4`YQnCqln;(ncB`34zk@4XlM~$9pwR
zD&HQwpx&XJPAWf8z<k+{s9%uUmf9}Y;=-e*&M7_jH!*7vVKVRU?M@52s558YA4-Pk
zYOj`%>bhr>eC1=R>o%R4wjk+iqqt1x6PnZ<>F3n+*bEY0Sd}9^@L?wu;aft|Lr2BB
z%psZ~4zD#*bzoH5H$RLIua3%v-UrY&II(3552`6Q6xx&I)xx!F1EHRHGW&Gu>iz4q
zpuq)~d~LfLD~_yV=3g7$8<5Gf^yADPPW`G|g}(?nNZ$+T5v46}a6g7ih=^5>5ZfrR
zxO!D(t}BsLPaf66ct9&^>fH*UG#)=xam_Zp?wX$QQmKNgnz7NP5uwG0+IaE87;nc+
z#5|?-Lo6nmhA^1OV;HN)7pqq23%Vq3qB_oaWldhi>)~}JHc)S+E={*z_ISF%=dMkZ
zTWbY!wJ7Vb|3`Sb!op{g9mv`HT7pX&^%<Yr=Y-YM8;5z&wQ?c&FJKDRSghDCeZw+B
zXe!ET4hY#Gw9C?j@<QK=eQ|PEg4>nkSNCX%2Bu@+*d!@_`u<iO%3QzRd*g8khB!43
z+BEJ*o;~~xS;Z`a7>J>x^x*6*#CMk7e|w{iNKMWeUE6WhT3HTbDa(+RPtA;LKSt75
zPDikV<8h+#fu;h-d&49AQUpJO_7LiC$n<~0?vVF05&gMfhf%a}rO`IH5S9k?S5Qd2
z+jNb1PLU5xe<p(W({5>aK^lMMDdi&iNXSfK4p8x>^vh7OY+_v2vYZ3QvzhhgkUr4C
zzR>h99kgv_(*3~5$O@P_y#}rmn$5p&w9xX7&^eTmDu>!Ls}ZwtHGAb*EG(GY7!G+d
zc%^}31>$PN4>}{`nv48;(W|anr)N>nlZIKzg6*l8{@}irR`<R0OA}-ZulVSpJC_($
z0frz-khSi^ytPEg+xYrK*gA6|I2)7GW!ZhqV*Z)E(xnoyK1=o)&a7{)Aw310!xYoJ
zi<>4k8k}Vlju2t<QRIA@mxg1AOPAO;@ETt?1YhSH-k^!>#1g<9IME0YV)XS3TX=3o
zj8uZo98Wmo9v_san~;jb8#5HL$I$(nt7>0)7j48(PNeyE7iuGhl=(>i!jeBhn~Pgx
zHS7JeMcsW;D?c|6lYUUZAr$Y2y+tsNr?ynHe2_gq)KPdC&wm<7%N3`|s!{{?=y^3z
z%!h9ZGiw3TAq+1&!rLcWUQDBo#$vGfNq-&li;LiLsf@;o1^FkC)56zj+$W%{$V!vT
zzWyMiS7!XHT<nhfy*cug7NHEpK%gUV;P@_JrZI{3B(QEa1n5}SQ?udRh7%^NAT{RM
z6n!(5n;@iU`D#)LDuweQxk3q#%<;^xa*IKpfNzTm)sp$p0!06POTM&<cfrKxW)Sv;
zsLH4Syc8S@L9hSOjiYC(!pP_p#@`o)XMV^kv&4~PO^{tewm748`3+gZCsa+l-I`@q
zE4X8xW-QN=-+eYJ>ff926XH)9acb1egqc7g%C3esT%APhG*uR`@!XcG2jz+@6V5lh
zy!58Ta<RKKrw=<v)>i3Y(@KuSv%ffb8?I<Wx!l6N#oLn67&#@iun%L26Ko9w#+|yU
zzlg9M?E(^+THbUE3^5!;{R2Qy2i!jxgEjI4_E_Z_Qp9k%1gKbsRTpVp?v(nG<Yjb9
za#X?-IICwCP=l|DCij|QR=3F*u(p9f?Vxnda1-~nSDA(}OL6B0U$qPmG;aBQ!uNSZ
zuY5SFB@<9*`mV){peNkqYkp?zy2g==y#cgT3gyGbwRwK$*Y!r&<{<>&4<wG?$WMY=
zbAk1HJ?lAx+EZsH0zG`SPp)NHD4`;CIC?Rx#$PwwzHW71)1E6(<Sn{qcB(I0sck;5
z*&*sE!Ov(nUbRL1zqJF$(z<{AfMs}w2<42<+)N(IR;r7XYvfQ^=3=PH8ryyKuW1EQ
z64?a5-)f17D8jcmKoAl{@Wzg5rm323rg^(*gxA>3kF8T$0UVCQWgFkt-3mf-bJUW)
z2(svvDrdoWK4|Oz)Vga=JXO9OnDpM)S;u$rP&$~aQIy&GvJ4nZt=mw}q2tU&;e7cA
zx9zW?3Q1b+VMbv$+|;y*xy6XZm})Y5u*dF{uxv9hJdaDN=}<F)cL#Q<ba<Nsad~mS
zSm<(potVCyFz}ez>PAfhX5ks#F{P6(7RHW)sY8LAL<K3c&s{wCG7r}OpYfDpf$E3N
zN&trpWGsf_a)HMPyVP_%Ze>&!qeuX8mNY|>Ka}U(3B=QRYZS<LfIP4eFv2&X{e<@B
zR5nPknZU97(HBC=Vk`U+*vyp4cjqiu-UQOq{h+r*jzN3CmH+MR&(<)M>=Px(4#tRB
zI&I99eES})(0zzLR%o6J(dGZ7{rX4h<D5gw?cRs<Ho5O2Eb)A(Az@F*XGDP4JOq~r
z$!qaKP~c~?GH<)rG#{7^$xz3t3Ym8!{d$E17fOU_(_6vA5ca=H_vb9Diitm*;_z`-
zuM}s0t39CT0$DigM<Q|4+OuXmH;-C%i{eBk-Mr39;hSw-*^WZZOetHZWnR->CX_(?
zN+-0dqG|wX?Gs!*tT}&_t2KZ2BIvQLAu>dyG=m>ol$IXDwWPuP3tA=NVBELMoxTt9
zfFh<)lFZq^a|n~Yzk2~Xr%^(k|8ivrE$Cl=Ayyl9BUYFEb>gFk0!FRNMm`JaT`Q-i
zNH%MSaS%}QHX(K2MJV{v=i*HC=&M=D$k|4(>}B(lT`y-EE_{u%E}|)~Vei{iJKa1(
zL1@G`1AAbOn-OfVI$ew<q?dNp6SVi!&_dNEE70Xxckvse)rO!a2;RU7{}v-8RzbH|
ztBMOhu0%<tAKz9dEqsBmbsl;!$c6v`nJT(3zSMXaJW~t1&r6ur#a!A+N_Nn4G?ZBB
zz!NDwxG4whnfWmQ&NW-&BYw$t22K?u*2J*R&!r-9`cZB*Ks`zaJX7WYMXTU2<L!!P
zq9n13zD(P~j`x$`4UYhlcT~IAp)E`V)CwLxP+JzV#17XSv;lHukO@r=9xD$V_5e6#
z3D|!+GIE!NMvB%B2Eh^)uO?@`9$ZIYoXp?w84Wbw8K1AXQUr)UkbMQPx_WprnePoZ
zxLXCx0xuH+!aw3Huj9GLbJ@=YFV~w-GIE|W_z8tW7st`h*#mYkOh(i3z%bPlGX8<3
z(2G#gMK*ti+^j9C=<jB0&30d|OB|L*I$t%5;_gQ1^_b(eiHB(7d7QRqi9%`zVDbw;
z#viZ%od7m(plyd9!%vk)JQ;2_5?q8C;4nsVtH?2D3SZ1kXP<Ocq1UW16=sSl%UYLf
zO?+|b5Baw|Df35rtY=piXfUpS%j?pE8M9eF!FJ!_HSfFjESH{QlTq>rkJZ~sVoh26
zr=uawpT-+vGb>+9RbH~8Z+pn0<0VSr63XE+ZRkjvt+TEBAH+YoYiVB8sHAS7b<D_0
zNgPp$D0IS?LGZT)|8(nc%hus(Xj9rctMU~jBZ9dQA>x>KXoBec*Yr%SO8r762wwQ@
zPz|YifeVOzN@V2KwdcWSWG(yrRo4g8i1dI%Twhmk{a$QMR=_Yi6+Dxf=q>~Kpd_N+
zX9}dKT_+`XDqe!9f^?e2(n?)&iYg3#Ee$@%02f<>Hm^aw%(jJ$*Pg}cg}_HL9*F0p
z6j1Y7DE#oUl)wjvj<Fa|fq=`>k8Ggv|8wx8D8unW=9##P6w#LPNDeer&v<39)8QOX
z$By4>&DgY1B_DQaC#X@wi>n@E!T|6GO$pbPo%5P$>+IM{G7K&G?!&NLZyL4%EKWJ)
z&50fj$=T^JW(&&|UN_Jp+L*9~aw?Aa_Zr4=bJEm7GVpTPPG(ueLs{jAOnpBRbODk(
zVUyZhVde$mkN@&&6K;TBZt_i)job9{rQ6w4BI;HD1f>A0GQG+7XQPa>8aRh;ESlD!
zHDD=2U%jF_yhb3K`M+rjv@cPwya}jq_Rzl}9Cvke=gd!r)nQz`Q)8y1-p4}cAC7>>
zZXygeKi2!PGfd(ES$LAlYYn-3TILGYl&t#h6CBWiY9nFX-Mj=YheBTn4gPEQe$HI=
zF{ko$Wy4f#hgHFz{1tx@^7rcUg}Q>%Z285Pt}p)FEze5ibNXy8pfwH?X(zZc*@bA9
zF)er>bK|TlUF|}(PD5NtAS%mRq=O`<3(XNuEkL+?cEbfK*H1UcvT8_x+=x~+X##|q
z;v-07`&=5}xu3a1&17DTyo-Q*@4abOa%r4q0LoY?p6Q&Wj0-Y$(oM{W${EGFYMcj*
zuhxFfI&99P!39D}*LjOBwZFEcXdiCTaCb6i3Kff=E_eE=*^0Ggv3EPYD~CJgx}JPq
z&6_}~S*=G^poPGLgf6FVF|9uS%naxLsEgC>J`N?N2^TX)i6Eyqo)v&CXdQ-~)sQjL
zBjwo}pACF<Q)S9-I2eY0qb5qHf8b5{hV7w6bst0D_z>LRw~o2Z0H_XQF9G7x$0}Cn
z-U+;XCk~uIL`W1q3A@841E<#jX#t;%+VR>7ncs)W*F89`Ly^#}yK>18S+=D&Ez#SI
zJal?w-PNmI;hhyB!t3X~B2ZWN!z^;byFM)V2>9YnR>*JFKm`;a8e0hK8XvEj4Kg2V
z-Zc_FM+d_zti5v3^OEYD@_!~-Z&?7<Ifa`|k}1l!xpWfPd5VG{t`E672FXKE4~eaI
zl0Y<J<O)6HtNY3U{^{A?dxD~OaXtQn4C9Nd#lPBzyDeFC?}=m5Nm0KvZo|BSgp;#F
zPFQ3q+*GCWx0saGJOmzGLXW$Rl<T}7U?hx`=^l`kPjzLTtfgy0Nh<(3E}Z7eh}TFA
z1Cp0KG(iUUN6&|bjSJD>&WvB69L{o1tiM13VwSFcJ=Nuzez&%&I$F|s$$RULvyZyI
zr=vv%{ZZ6d=|)XFt<Z=uifej0CCV)xis~cmE;%26YF*Oun_U|k1(Yu7$)!-sR0##_
z(YwNicr)H59aGc6M`o(sG4UBtuCXV{18+vjQj^MOyv51Nemmb!AK>3@G%{AR%p3N$
z#aY)R1dwH|yK*{U2G!13tl?^bj+POm+95G?9q;Szrz}dfgApTp{r-cOW@T>5X3MCq
zYZzkZ$&+u#(3L5t4s^;(MJIRn0aXXbz&d0R;>|mSGH0~2A2H3nO&&iPmZ#lyW`5u0
zOU*21Dt<eMR0x5x_mImyT1tNQHq<?<no$HO()@%)!S;_7_4*Jg)nnsi5Fky8I1sF$
zwyC0y$Q-2sH#rRw)p5VVdRwwo;{ymbTY8>JQjp$K2hs(!-x@WZ%BP7}Z=}Y$Hp#NJ
zk*&3C@HaQHs~loX*;8a&zv_MFJ7}JLJ4BjXhzoHtQm+3U8odsk^yy>LfG!B+gz%gK
zfFKL_Uvhyh9S#}fLiqqDo+ae!KSr8r93h*HSJX!p53}b~(#qYu+5F$B&d54mhbd6J
z2F8CpQZinQB1E}{`+!1oDz?FXa!FS=40lgL@TL*D)3tYSM17oYKAyUoiW2ce?V@Hy
z!hbVy;Xa1M1(*Z$HH0(A{hHAn-=?Hi$=nXM7dpD@tz=+AhY#<0x|8U+%sSs|aUGsv
zl3s3SFhbA~5Yk8Gn+R<zV6~}V4$<q*er_fN^bY!yIhau8QPVOAkOJdIg%%(SLyqw5
ze6Y;O!R{Dv?Og^QbgJk5ln+ubk9I&IXMKLu6To>|ov(dCLCmoUPi_2@=1lMkfK`$a
z%fhLzkCR=iGyo8aBUNTls5Bncaj5oJJ6>%+&*8~^P3njYGR~TPZ$r|HD3egoo~pE8
zKK0iB=Rcc3uDM3f-q3s~)0-s>SC7x*H;_iSW=%WN;t5OE9E6I#+b$!yW$}LzO14xE
zc)KI3<n}VxYtbwryAGf4f!K3mzf(O=6si^ZEW=f9@DZ*chZV*0)5&iUNTCL=Kh!oH
zLV7RP1Xu~$;4M8qC`u1=dgk@zijQ8(H4CfvlAT^0j`G5T1Xbj$xj*|!U&=jZ1Ocqg
zHP}c~ZhMVk2LLzoNr8USqQi>HvU0e}3b%iGVD#a&6j52`PHHeNT>0KmOat7_6?DhV
zij9bSzZl3C>upE_bGIpI4S;HA@Uz8mk6^6W>)D?3@gelk&FPO2<mDI9I%Pq(Fm2zf
za_0w!2+m*JwB(2XAG3hv+z_odhR?JOLeWY!O?^pNm^)QDI6+gW!$-%mG)>x_A>~T1
z!~aV$^m`IB^fZs3ex<<@p=TzZkp<*B96vR=q>QE+t@kB1-GhL*xtZlNWebBiVnO_6
z?w~U_&VH;QpZtqROq7&=N#%_nbiI=8nI@oD{=Q>Puc$(HbV=dHpGa5XaM!PDJ2)fa
z=cbi<2Kee{db0iZiJ_wW!<#M3eBBJ!j<CUN#YyTbU$EF*gltLD3YFvx2#|gj1>s%m
z(zK)KZeq0*ch#WT3|I6j6+>jrIb3yT$}?4;uKHw8r!?_iEq1G{XeAl2g6rP4a$0pK
zP&;%qBR_n)np-YyWpzb5;|hq(N^!N2j-d$5jg{TzjgU;z7G~Q!)wLNQbKK{yM%oyI
z7EsL-DBflGxl?~1C=jFS@3Dc@b2Pr0xeArR;9}SMz$`uy1{%ri*n1(eH`W3Er$yZS
zAjsUrd#)P+C(F0@U08}zdwQ!-wya<8iJO)rB9ibv5bsv$W^ZhbXJV-GN>!bUHS!b!
zA`a4e-vjc8YI~%Xko{$pJ`Q)fT*Zf=E{n=0z#c<`mm~`nuQ@l6YoJ(V%4<RT5v73R
z>WzBvAC-A2{R@lk{{vYhf>pad67ffAyAfhbF(YperO^~IxgA1KG5r5}M?bxklswhe
z(J80${M51}d`?$@4`?YZ1m8!L{q)GD65K(h_H>(jp*GIDo$*{vpCY|)E1P*S20Zlj
zgP4!$bAxUfZ|dW1uY^X=our(9aaY}YN)N(GBlXjC^GhME*!WPbLmZd_CW?QSQ>!(A
zrgY9Ig9Cbx1?S3y8`kPa0unL!F<gWL;iW_UBs(}FkLhsY(;Jmsp!WedKGMx?(t`Rg
zy*m7#oXKGSP2G_1Z5Ws&Cb8iINrWgD-v1b#h@p2Q`$gYmfHv<y0-ZRx#7@_GaLmjd
zN#KzpS2*=Laee<sF-F4w>S`GfCeEgf`j5W!g4dHi88?FZAg210;;Fv?706owJ!cO8
z{o~c9L5f*ElX%7|{4SCeQrgW+G$JA@N;S3#w(#>|RoD^kwJPSQVPrG6a1|ebzDPL<
z7t9{|+S;ek{EePx&A(LzGWoWmjR`3Hp%-M8u}tnPhtiqS#R};8K;(YYIE)a9sJ-Fl
zl~?0qDou0ga>RIx=*#qAR_C<&Bfro3#x5^6Th8KYk)M|*t}2yG6DY8JjGJEuZ5I+?
zv&;{rDxcJ~JV&E%!4H7X<Fqxm7%K?bxLF(-#hhP=-VZRD3WZrVjq<XhiE5M_W0o96
zM$`dNmX6bOVIJ_5t{RFS#QUvD5flLbZL!yT5?o<z#US|m$?^>XW2zP8B{Rn%6wFRQ
zyd$^QA4(A*o$o<VJeN?6&vSl}GhB9O2IC$$aS`>zNSBSt`pVFL%;ov+6?FV5($J->
z70}fn=?gVNj#apd&*k&T)=cpc2QOdRCT7M1JMQ=`*uYDSbZ%&EOkSoamICek<@n{S
zJ{%t*zSevyI!4))E!;RT4v6i_^Fmh)t6st}X5(`+bi>f^Ra4w9rz-=F_Lrt(P>h#~
z@mnTKgpAusXFB<Ens8Trfa@Wy{_9hRQu$1oXQqX)YHp)D2Kg-**D$x?j5?s>d!Xo6
z0+(on8v+4iiRM`#WAYFoc0{0{b82Cbw*%??m3YfW)6^5mYO6{r@Z0xU9T#s${LJ#5
zWwOBayF0KGymR#L^6;B|Z2a_n-Km;vAX$7RgLvNpRanE8wI*FtI#MI({(-$BzqLCg
z%z*Bx;i=qe%yN{8BDRY~>W~DE6=XM#5r)4z8%bQ*?8nF$6K)osPF@wnNG*lmX%3GW
z;^F#X#kgpk0tT&<%BGu|fM~_lIvl?+2dO?}zdaJxwc_J2uN}1v1N<_JE*d)XP2`)_
z`_pmh?lS!l2l=Rt@JW(o<p>|M6^o9$>pR&(?h)0+!Whs~*;%9lP?3bE8*JK(EC1;p
z2n75i8W7~Y3v!ysKg8B}b7;8h7ENXLNhyIVc<BlyTYaBh>nh_ad9N-l(~US7e<*b!
ziHT&j{fn@n{T<zmLq-G921RwzZYZpfRZU(mfm{j%$lxrA1gj`3@9;Mwkc8|p)oMUK
zR-H$etR~b6A0-wKJnvkZ2M4`x9_bv-d2C6Z<`75vN4elMSb1Pgox?IR{qi&0hfX21
z%pH?A>+u+PH;U4|)i=gL?b8B@@Jzpd5vJ@*(tdM{&U$3P6{tlRK^kMh@<<v0-=x#o
z*ak?v<|`HgiZ_L{*pIAH{ute@G{$M}5ciq0U5KBE_3VvMy*cO*syc=yGX;GXpi;(T
z_1h`OJL-(A0E=@u^g3cMuZTPjk%}z0wSu8t0x5e1%%B7Vu0k<Bkvi?pqe?qP#6(1A
zoD#_Qub`|~HGO4eVa<y-s}}2ZUYmq+*a($Isz`G-`2NNv<+gy?_BsWFaR+yIYQ8ZI
zQIcUGnN>FcICu1CjgJ5eVCK7TWmD895@;>iN_V#>yk?~%9?fG!Ot+7|&XEmNrzbQ*
z_nn!%Cj=GQj`Xehv})w6ze-{DSD;yUKD-Ga6sLIOX@=wOa8VuA3&*Vl=gC9jRK}X$
z0?WBw^yit7-xPzZ(1-7V8>}N`G<x$934Ui+56Y{Rxnp$-Kge(VD)W6T$bx<`KXOft
zqcZ)^?HojTV<Df#`z%50P08vF1pf!<Oq*h=)oknDnJ-~wEJkAf;I}!`bzs)93a}ar
znL=LuM>askZuGjeNSljKUz_fkni;^RilH#;Vi~h5-Pm!>DoazqUkcSa_R{ze2sdp8
z^r~!^;_aj5>qM6J(zd{ZpKRxQ4@c^uNoCFL76+ToPC4fJVD}Wo)V#{;ZYG$npn2xp
znqmM_f{H+N4?Nn#AU%=%c*eX+&EtR;hZKkv0=C4^0(cy4I*<p1gEBU^xdQ|oA^RIp
zYHKe>cwz0NVux1)tB(wt9@c?i-`#4F`aJ9R=98`Bs+m%F5Wc7v626@KXT=qC2t6>t
z&__RyISeGy!TEmi=N8mzSk#wI`+%94Qb9UFG=^g`{Ta7m`-lHFtS?yhFcAHnKfkRy
z3H?Sh>Ym-Fp|`q`zGWUwI~e98c426^-k#1Eh;o@qp>-<f2IZJ){nZu(giGYIsBWmU
z+a(-O))hidjBsx0qOX~bt3X%vlno{@Z?p7Q)+?-9SBoG9FkdOU7)}Pu)!%%NOhBh8
z<{~Gs)n9K17%Hw-zV$%vc6pfY6r<m)9DVuDe^H;LMeaJ?^qel~-m=uP{l$%hUjq-O
z+Deo@{bIOW6uB;pF`-iw(8Zkq;RY>Fl=)bXHBgDX2x+NPWKC;+?Af+g`T3}TSLNf_
zqbL{>tvQn@;Xkvj(=14ddeKAZPN)b<%j$DhR*!f}8)*?OPYB)k-FHhMej@=joL#Xz
zT>P~NI5dbc8E*5I<2;Ivj38Y)N@>j#Hc*BofzhEw30un=a3Si?)3<agtx8WSjd~q?
zLy3=@gwqkhFay`aw5G-sj5Y>uL9{28+~x|Yh~rVkj9(*?vVom<vaBUuiF9pn>n=Jr
z<J|dZ&E0t(!C$+@qbO59st4#zrm16~G}rT^S7o1(q^K@8bgwg&1}@m8IIR{G8d33d
z57&*DE|DkNYE0LpL4iz#crXgfr+*qT;#62Mt6ro(P$6^)U|HOWS>y|wGYS-rZE%V;
zvT9?kL#YC8v{HG!c)^{#F^k}J;q5>hHbqM*48K`WVuU(32}5G~0&3hqI^}bT0u71N
z^SNl&WRI*6T+)9%2w;de(`HgY#x^B~xe;!O(9kQ-U-FjxF2>Wk1qy)GK%}BigcVHZ
zjWOU^V$1@oxFKx%g0{85H6}rCNw93Xr%;VO=#f4~%g?Dr(vD&eUj->Laxs*0=r?rf
zH3$84Eh+1iO5*8)X=}C-L1)+{*?U%whgm>QxP%S1I;6xMnP@xaZm+POSpx0~905(R
zXFSfaXxUGHP`+UX!hp5z>DClc*e1nW@8;vFae20Aoczd!iPsM4A$#s*T_ZQ_u?76P
zM8@A^6<ok;0Bp>Q$CDl|G#SLrRXAsj`Up3O#?n`rBY}rDS|OB!0)nJvC9?X=Q_*uI
zhh*Jb4jm+T65n`hS}cq(#sUPK312=@Hh!amgNl6brUy27@FMsC!+LP>`kg6FOW!No
zWawJM<{mDl;c{C^8S$gUTZPnKJO%}ssCmx3Iri)_?`Wh*Qx{ir_ULqG9Puh?%?Br#
zeGlQdR%a@Yj^)RunPRqAc93MrT`<o+`4Ws4Cx%?ual1=oc_k^S%E`8zxFOdlf?={B
za|o|cva+`?U<hQ@0CW~>AYg6618hRA=d2~}4R61k`bwiaw1Z4E6&e#L)4lAAjvG$}
z94#bGH-oqG!v<tN!x%sQam4VaRaA@adx$@7GlDBxd;x7hZXd6H>{&l+l+Gqwp_(Jx
z2n6CRU^UZ#=87pnF7S-PWGVG3DwU3Jq&KK(YC^z~k>A^7gtdalWmXF%8UN<){4Q4k
zD#3&g{sxLw`ZjiHsvlBgJ_*_uuDC*G!3__Pq<_vsCh`aZJHCq)Rza&e1uSuUEw|Yb
z0c0{qVkyOl;s9vW)t`<Qp~ulBw!BXev48pFM~yUiFgSaGM5zi-7~<P~1dyGi{+abL
zLe*f58ks6lBb;f!$v0CBBj3G~LL|68WZ*i#F}z1&D?5m}Xx1L`y-|_PZ*S?I%)Qp%
zFoGr*l5w%fHH0lxK>0*$=LIlbyF20I6@$uc7K|~`(FWppqKCueU)BT>FJfFk9%D#!
zkQU%vUKHL=-cxt)vW6cqueHN#aJ=U)agC^cRa7n*<1*$iT1)w{4U_$){@3%%K09ta
zIc?O%{3vbRF<zP`BcMLhxLu>5=GU{OA?J%TX1`zmqP#3T&jF`6+~i8v*V9`9u~DQd
zGQ2yTTAc1D?gi?}7*~>Dy;90+2xe}(6L^BR1kQMdZy!Va*9jbw<*rQ&bu{FWb|r<s
zeB#PPWp=0swVvtaOOlp|+czH?l9$DgwWZ9fqnE+0^ad~2<nXJk8O|YtGP>1vU$W-h
zXkHTkJ?*%`=KWEZ{7bB(=>hvAq&v!tp+5^bjZO(txb*|YFX#D$foKfLD?PU!P03Bd
zAQXBzH`)|GGOC$nTfOsj@?PX%?Y*apm`9fzu+;{u2G+NyhU>8pDUDeNxLsj6j-<>^
z$>H5DyR6B`<v9LJuhzksITNRed-1L%272Wh;r+OL6E?#3oRF2==hbwx&y1pEJra0s
zCriZ_8nr@h`mRUAB+}%v05E=9UJ*}{GSO34_B_{tyD|nMg?Tb-f7qXMAvem)U$tZ9
zg!HbZqQ%zLnlp!fs-Uz(0+^2-9RB2urKJNP-?McPDM_UZYFNhiQuY9{8O!BRnw=r3
z$6)<!(}vn;hm}n$e1x`>1^rxkdt_ay7$15`@L*MU_YfSGx52Sj_v(~aYaHeg*Ynxy
zZ7hM?nyOCtrtcI(Qv7LaMXiGBDry@aF_%k7M@#%wjsv)rwN9K)n-Vm*887ew)Ff!W
zhg0rYv<aXK9Aa$bg-v@*H+MpEVNRM2>g9nWrz3ifefWF4;5<c4NDca5Y+>J@nqhnC
zA-!b`G@2$=4H)4T*t;IB=sJ0}pem7$%78SV>bglQ-SLjzwx4ybcy>WAAt7+4E(zL6
z0r3>$iR34xugUNcF}1-+6+%cNHl<Atf}lb6y**@!Ml3mLYQWx{YPxNI#zEWANCjsE
z|0?eh#Cv?bZ}V?~Avys3d=RIog>MgjLV#B$Xz8!FhvVtta5!TYlF{&n({M!6CQQ_C
zPRaa^lk@0QXYm{_v^Fw;PGb>cHBvb;mu1cqxGbNxbH9pTRWc=*=Ib0G%3P<i=E7n!
zN*|OsKa?GU*2+(t=Pj|jIJYA_=Z)L8J&JZqK@Ekuen=M6B+}U*;k@|{6!M5cOc<A9
z*WVSr8GjpW*ZF1j3YegEqq;2RaqeQr)DgOOMHyf*R}mhpM}3#b>a^yesx0Z*#UwuC
zG^EI8U7#$j>(I;jIQsOd60=+hXY>TrO1Ks7eztn^FUs&u9`p2mo6}pEZg-OkZpIz-
zZrM@*YmbeULPn^TApO6nJu0h5k|mGz)AVV%_EhB9dA(eA@6$4j?y-)6LDS1>y_1)X
z4bXW-7OL$yi6!8#Lcs?wo{<wuF_8cd9r6voT8}y%Qa(Jf7ua5(v-N3itbqjRbAkWr
zOigE3Z<z4{-Pf3f1$%`!)NRxBgWa@EVFu3mFIjjF4d45@@^gme?;FGr1y6JdC>-}@
z!W)8Jg2)|&3lp8c8Nw!#?zmpd5>SnE`@g1AW_wPTfF9~+aJ?6elH~=YlrZUG{HQ}k
zY(MfwmLAeUK3`e@aW#K0S?R6i$JOqeI3nInRobyy>^xbDa<63uP&Bl*cdl9XA(m8;
zrna}mT)AORSJpp)1zv$HIGKGPe8vHM-rn&IsQULxJN9N!JK~^5-Z`C!D{_p<I_+|8
zG`6FE?V{kVF&{xwEa~6pe!(fJApvy_y`k{$lNPUtQ@>{b?_4xa4}w5Y6hm~!*k>3`
z<Qs!|WO)p;jmWhLf)5<L$B^o!YJT4lZ*>u{5*RYr9-EgSKaeMiG;-h~-zZ)0jKS}j
zl?KOh`Qu>Q+4ovAOXEY7O8nBo4)#FwOD`l=s8tVVe&3p?v3ZV$L&sfn=_y){nlZOn
zQs!HG?Cm|<uM*$?JarE&XV~xt!c2Z_#Or|(kFZ9_i51O&W5*7^x{YkO3|rh5W$Xq#
zkC!W2)c5*3*UsiaX<eFZVS+;!?*bc0J!lb-&aar&rOd}y6QxV-j$rn_K1+mNmsE0`
z+iAcJkpkJQ+q6pDP#uBr!m;#B8apk4pe1QIp~Y$Nccx59>r|LD?>#>9=>XQ>XCVe+
zpnVkPx5EPQMA3*B-+7l^4GFx;YdQG|cX&;cWj?tisy@R)oe3BxruGd!wJ6^%;erTg
zufkx5D<M`*UQ-qVWpkDVR^!<|b3n)!I+1&F#mk8}hF^-5O3NNCFAN<e;9JKDrA1i2
zY2lAb;yQ0&u@a7FhCI%Ot$^0>eWkk-p|BK{4srRldguN~#RKiRCH3tzs6!K|pe%pM
z?k5$fN}M1u8!5*?g9npa-PUFzxon+snt~b+m{A$7WS0yHt&;V{FO4bt?;%z1K~%JN
zVrJ*_dtlxS@&tcR96!Lth(_680*}It0i+)@E;nXewPMRqG8MEquYr63E<*@qzB)59
zr;ql^$d2o1%RPqlD5`|?-R_f_)DK#i;;&8f>ivujh`;7(#nC}a&$vybE---y<MUpS
zVExs*tDF+{T*#kC%DPY*F^N;Zbs6Xoc0S^hPv41<qPC=8erEiWIp!*iXjI}~sqK>x
zM;Ni4N(tpZ-@3$QVL7xdLHy+lX@5VbI#R&(6_Ab`VMpdBqN8EjAs~6x-Z%OCd(Qz6
zGMkLd@3Pa7%~8YKd+1tX;29NMDp=d!`pafIu;jQVal@nP%jTm9Oa`nQQi6@HWx7j&
zs{|at|8TdsewC)xy#hK*`t)S#B>K}ovVT4!w&)F$3pvJaD9HUb=kO(M|HloWHZGP7
zX#BwKB>_do?AeBb*IEv~XMipIh7T@oe;t?t9|HFGM{tVaU9i*5Q2P;WXUyzrvJ81O
z*ZXQiq9bW2x~)M5K44N2V2zOMi2nVW;hD4;Kqb9R#7jvcs^T5^6b1B#e6tPXFj1o}
z3Wn?A-N0|EE~K(WCV-N(i-!=LymUL;*B(E|uhvLVsS$C%PXNH2wyYw-FrA9-)t5wf
zj!HN%nDe(-{j){xR*&NfHJ|q7#Z|l7RIoe||7=quVXSMkBzhu}B!ynPM?CBEe&~FF
z!jzQ6{H4||!?D1NChj3|wZtu`5RgqDQcg&%O6uz4ddn&%n8Q<S3}+5Pv}zGHfX|C0
zSgWKQdkt*JnxR&$NP+tYaHVPI|NrS8RTJ@g{%D<_jnS_(O-7YP1(mJfZGI*|(U7c@
ztOCQ*J08yz;9F$!vMz_mcBUv(fauK;X$ff`W@{K&3)V-h(te)6eCdd48U~Mr_9Gm&
zL4gd=lR|MiK87UYgMXG%X@Ez9;;SzG$Zh~CK-IrOVlST^sCx_~pUeUSdWx@l9nJoD
z@svQ(#74p(o=3fFPnEG9jT{YnM*iB?W#|dBfE4;}-3a*YkEmgG<I_Mhz%~cup})s$
zv0j5rGMWWS{XoP3iVprk!(10|W*E%$xWqiE?nC~2-6B#6rZ};lhwqpPyLTVi4Z+W>
z8`V(~E_d26M1r<;Q2AAX>xr|@2$UW2XNaOO@s6r(IAzNa4v!nXr{V-XjB+Y{^8u-0
z%`24pHkwT>hv-0h5d~)7`&=E9@;uf8i}5h^+L)MvztiH*wn-ZLOg`)ZgY^N)X~BnF
z`LW@NpVoDHCqhMXuA$||DTBw7gP`8WydL(7x>%+7_Rt)lKM<vn7{F=KWo2UYJPn2@
zILcYey#}aLAgYc0VMn&(!J0uLL8dr)hjv6#d3KC)nr9lC)3!cFvlZuXrPrhsnU&GJ
z279M#p=8Oxjow0X>wQWWd0^|JSF1_dJ3U-kLe2_WRNfe9^cb>e*k>4d7i}$SD{i39
z6HW@qsb%hT@Kh?922yy*`2YkkS^4Q^mHdT+I;HOK%~MRxcv?3#(TuEM@Kd40?EcYC
zq(mI%2J`THl{KapLU=_P*R@4z*c66>1fvg;h07!3mD8rrwmH^>*^RANqoh+iWFbeH
zwD>@uYjrV;e9#yN?&?;%$YZyvs#%^S>|Us9=A+qr413-!tvWRjz7gP?^*f-+uSwyC
zMf6g`Fr-Oh_!QwgtgU2{1oP@+IKn?^CT+Qgph1whD+W>as3OZ)0#PnEF8?7=PMuQ&
zp8GWddiR9@TrJ~0yw8kmW|RYk1?0aR@t>IuRJYTT`Esn+p%)$D-Qiz(b!0GuoLQaz
zD7R47GG53|-u{YHoKxQXNlx&6htxhl!S^jgP6*zQ^S5^)Uqz?kS8NePB6j~&71}lM
z1=miDck20f&oh9MlkzHsDu3AVgywh9aB-XNnVZ$k1l*GRSFHABAlX)Uku@cEqVQoR
zr+fhfnt9A#-#H<002AE%1f7#_G!<~(Wyz-rB_tAOFCVW0U7`(5ax9_uqit$7_mt;G
z1!T=eSaU8*LQr=|8y7ikF{a^|F~Shg#otWASGXRbS{LzPkAu*4w)%vMH}s(wOhr1q
zVdnjf8B&0=;k5C%kmEOtx$Qs*tuUT(n@|PqB{&x$YjZ11-{A%+)b>ZZ+!&6zq&Zvd
zz1y$0QqUl4vx{?yPT%$(XsO@uYLo8o*#4d|r`X0Ek@DA)C3iN*=HjzjX|_)X$<+u*
zZJP@tnU4_g90?QQumT-%k~{JGA6o5#r9d}4Blsv`zxQ|r>JTE38P&LxGaZbf7?CSJ
zbf8KogfjD?VU!pP!gz<?oiMr?=`wglkAUKf4N|XFs#za45%jVM(m^1BcXGxx2X6eD
z(I|{WqTJ>#hPrQ9uzI#^b}pq&WU4^*hk^=G-mNVVHwMrqW*1ZoV?`kM6|nCk_*pwf
z#-}e=>g)BpAlP`nWNFy|=GnuR%F){A6eUlAN$;Q^*iXHo=&d5Rx3<RN5@8P(Lxn{p
zf|75}hOrS{5);Meoe(c@Su>0HM(Jzqva-)j*u_F;gau@5)|?=eVod3E(EkQ%JDTWT
zVvB$-IOzCESLk>Bm88*M?zQU_g9pkCXiURUd!r)Db`!e}!*~QdX+yKBpsDkdkiH~{
z;>vm@6HVcWkaqcq0{Z83?p5%O()E_l&{9@yYQp}rQ0da1Yew01gNzEwnZbfjrK6KF
z;rt>16Z!&Z0J^W*my5lE>ryDw3Kvan(c(_wJh~Yfq>?u7cm@I1P9hHH4>t(G%-X8u
zrX!e&TK8}-5yRxm41Q;YfL%8Kqces2#H!VR;n2~FMA_XUk5MwuY@?!@Ym|PG$<KQX
zFtNrZ(UO#n`WKDX*#buJbJGa!|LYI#!`jy(0%KC(26&4KugxEuF_+^6G#(f34aBz)
zyV*$qj}+VDLAf8G?|NqqDsAnIaNbO$>RS)vlK%UlLztUs|KF9%HBLAqsVKa%0Jq3w
zH`t{|<NsM7jL!kR{<f^obWMD>wabfv0vY;yd7qNH4a?O7h>3vGXlV!*PJnqvX{o@&
z6iT^>f@WZxas(cVJHP#pTNk~6Rq)C~_Mll@vVSlWx-H+`>@a#`jey96qSu9kvEKc#
zQocM`yAsERR+w;k26MxHp^Znnt}`EPlfAG5`pfkeq8Iu+=`exs3gkwAR#51?iB2+T
z*0wK7dsxpCMau1oRuv8rmMV<);b3lm{54cO^v6J>mPQyT5%(aBtWtj7Qfge{!s`o)
zn}9BvBbBlSg!Tn{+~s`Wc75f*X8FWwq<j?i7*mPXtp~_DO=5?<W4mWpD?LiSP<K{P
z0c)!QZ*wLCHUz{$Xb=`Gv->?xSZ*fsV3&kvtHeFkj_S;<#uxS}7b;iY5p@vRJJ1Ky
zB2Eab+$IhSr^<%@nshG?TG}gc5G4dIC7dw5`b5Y3v8r1*f78!8jao!scGj`hU-y`S
zv-VS11Dy5kjADIH=X%1np_Rb7H7bn^JJ32hgi%XFtw;z>A#Cj#&<%9Le}`^<c4)mR
z`i8-(N8E^d>Rp9?*tOnA3YxIn?b!_!(fLbu*j9~0bt(eNFpfr6F+P=9BDJWLQfAQn
z3Rh*PXaaZ4T*P1Vkpbnl7TS~UBO7qN^|cd1y9o-vDobsT;@2C2ddT$q;-*+s;5W<7
zIKk`<5WyO@H!n8A2?$DtoRi_3A4wKM1oF}{IRS9i-e`{8S&m#|gFe2>+O4M26`Y0K
z*egQ=RekSp26g+73W+k`;0=-=Wg5gIvmMXUg)ZPR8+Pd}$l-)aOECpqe;O{D_59;2
zk`_7R`(@S;C>T4|k5z^L>&^<8I>53nl}oIE1=1#4bRU!+@6vW>GDGvXj#(_Mrz(Zp
zQNtX@xgh||>!MjI2<J(c-Lq@u8Ds2)vh!#`Ku--Ry^(KlQuRF5QAwg^jpZ?lVi9~j
zl6dPqX4YM}**O&G9)(Izcnh#$A4S!15!Vp6TW!sEm4D1{h|#vg<3D>K+M%(Q7H164
zizV0*g*{r2p|Hv%phyA{$ybK-O1;N^q)|9j6OjHYT;pa4;J=Rjk0Pa~`^ZvHvtt4s
zhA+?xU`^s{WAJ_`iqh$8PWJta2dcB!gs{&nRF2wq7k3O}(w;@~%wk5Mx)JrqvGl>3
z4G`urdkA895|5<~i43(~^}<U|VKfr9+(JtE$`#_V0!C}@rUL4xI?<xmT%gdT`jT_g
zaz@`o2_9T_nVO`g+OfDN<n_DeNE5~7wpLJnEJ;cUcu+t}$3kIJId_0+Gk*%xwB-js
z{U~ZFZ0wzYcN=79;VRZY*T&Hq7}Y+Z9e<b!iFJHFP`&5Y8bgq@_*&x-V;o#T1U|m{
zr>-zrcH*iV2wcZ!{B${Ze_T-hb@ZPRKHW2o2${NLa`MC0;G{_0EVNPPIg_d|(1#ZC
zz;Fb=)z2oj4(wCnFL|Hm)@#r#QNa@aP`S6t$kk}V8=vPkZfvjy=IBvGScU(MG{)K9
znBPH*g!hnqx2)H};8<+^gsJYY=WfzEJ&%69p9`jVf%Hw?lvG=ycuk;9%nL?DR@ixs
z<BX=n_yMX>=oVhIn$KkO22)QJD_OF??xvUB#8B1Kko}t&ZQC>qpRvp2xi3G1p6627
zCs*;(C(^=8lbE7Hf2{wW)t9toX2+UAflX8><M{Eo*~*&e+UuiiQpuWZysd9^STj1O
zK4j_Vw@fvF4XKcPQC@(}aL<P_Ba<CJ_l*AJeZ_$7#5SG!Os;KyG!8RHOZj!~0<=cx
z0k~G!gk!VOB*QOh1Q4;{omS}?$cksVWgge{`O>^Jr^vbj#9Z;5a2gzY-wz`l&mX@P
zX^x6o1D@x4bzkBdh?*@^Y=!#oRO-P|Ix)ky>S&uTGtIV_F*~95myjReqfiQ}WJntN
z#S+%fIGNCXUc1&1hY!Nq;cntaH$zf2550$k`1~NM0;wa{BYUssQPn7<?(rjny`v*L
zc<>V+<;q-dBKUjVNq1V7E0<$k$*-YDGAvUeKPT&j7aa6?eqX&VJ`u1r)UCn%V93k3
z_TO)ab+Zi|9G@BH*s$IkfWN^NmLNX~EFwzuegh1wYgknsXz;mVV)${UmVQ=SqLaL}
z?cJt<L;v%%AMM@WHs*iP3g<nr5c6PN(67>x>y^9r^0HSo0jwTPN67KUVuBhiCVeNH
zSj3|dyLej7OK}XW{0C(Ye5-fiVoJM^#xvIDN|d&A8%dU|oqmI|bpyN>o*$T^XZ65x
z0<4M(`TsZ9s1$S%B%_d@zVNBczX}|lU3W71W5|-iA-bBSKQ^X6>MMiR*ARP_Yb58|
zXaj=)w1XL11zatE1rAbCTJs*QD7guj8O*`Cl@mDBRL3`6zs(Hzl<(VC)wCGhik<!}
zIZdwK(Lq%4Xaa*WrBW5JrLB^1-&av{8w;sEk2?9YuNwiyG@qq(&t;O3_OqwGcv9_Z
zwh<1{Yhi{Xi&}Ysshd~3fkNBoX^V<92X&d-9gr@6W>Pdp1QFj`*rBhn@YzcsQ~a$|
zM#MDal=XK(ULS6ag#sO7tif%bsb84U&$rS|e@XZxcDPYero@bi+1~PW(@K(9kC<8#
zrTYgnrI#-5;z+aL<ToIG>Kc&5mrTtB2x+m<9fUaB_r&@TdZ@S*!KLwTcE$jBbR%78
zs1V(~ZcA(1(%^z3%xw7&9-92><@NJr9=~=PW@SNox<_2j<c&Fduc09qhfE}P^@cw3
z6WAm>>Ol3L*zmGaM?p!M%i(Arql<B4PtQUIkwbKGo=@T6&9T8fcM03W;<!Fy=l%$K
zDDh$$7>#+Zs`Ha08365V*@x*P)`M1D_bL{w0cu3Mk*M-t?~e%<Ymr4e+V-)}VGA6c
zm7FR%y)Wf=T@W51XErTH(z0`4*#Ghw`ibUCj-`%KjFkRb{ouxzfCAf5+1k$LpVM{q
z%8De|hJ;JNgSSFxZ}kL7V6iWC8#c`^c+feaUs(Au$kde}+2s9V2w!uxi03a!!Mp)>
z$`Xp6IWTyVUaJThl6gzT@39WU(k!WED8V;52=&VMG#xzVw{`WRv20CcJ>h)`CJ!DV
z5Hn2$NbMi1F5l3rpMbG{ejL$s2f2$rDI}Mz;Ji7_RJdtc9@|G@=m2D$QHFo(Pw)$=
z=z>ogh}LeTUH0&3MJc8~+M9H`LajKeI3B-%Y;BQ~A4R&Ww$;XD790|U0Hh&~a4OK%
z7BgYb^4UJ_p4Ub?2f5W^%vKoB<LzGEar5y7VXW8Hjz<n(#t(2pu6t+Yo!+z+%xWt{
z0eK@TEHdjX42A4y+X};tFoV=1(eY}4@z2!Qn3DTfz(}gkHfX{|y5<vj?pO=Pa5zw~
zzZVE9nGb(KNIy0qV9scgh45P~#AE{lS?!)q3bJ^@(5+e0Q^fT>+MmmQz;Gnk%yEdH
zx)v$7p5W8$Kz2l`^HfgF`yM#Uoow0#tqmM644O-^35ygj6%P+t>Mza-l#MkB>z4b}
zHB-`G{03$?6ty|)zu-RCWK-foouT<i!QOC8K^1@LgOmhDRYtXbW(vH%BqS<>_+=qD
zAC=QRzR^lw$+t$c0<F!%gI`<HRK(fP7_>6<-;tdui@|tdU0v0>KTuu<cQV(dm5g8R
zbV3ED3h%XoiC%EGr5fh1aJXiERQm3NvoNzoixx6+!rUP$OTbdo5)#?O(csK|P##w!
zOqz2r41=dj+ygo~YFy4jlr|-U-|YiXHa=63(>q5$Y4l|Py5kUeb(a(B{M24pb-TRG
z7sA9lkOdjMhyT3;kEjKL?AgdcP6x-ZL45%YnLS1HllCZd<QNm8{_c!6R0iJ%=h2Uh
zA>>q4Wyn#85QZs>AHLCqb(O^+qu-&ivP9TfeQa0`r=MAq3h6B%u>@%ZnBngBGyHpz
zr_?xtrzmQ|-BR>c#bcA4I2<(b;o3S+7AMbN)ra?n>xMY+pX!vf$bo#J<YPVj!>s!N
zfA>b$4}Wo&LA59f+fx0_;+4k2dJ!icPmdM3h&o_+ZLg_sXjvY;e@LewR|&|~18Plx
z?L2F9HQqf}(P^3w-Hn}sv4t;4H*V~05i8o`Ovu}Uz95(f%-fuzJmfgA0z(FmMGee+
zs}#g*@)|oZ&WGiA4`YBG6gNH0XR>=+NyM-bx)~geM%{l)DTBdcm=(Q4&g}3dbe>wi
zfzx)#2LlW*`8(5QPd!=Jj<^s(DU|E<-9dhCCpFF*YzPnu`zHlDsUm93AQ9I?!PrHm
zxxFz^aCCH7^F#Ghxw>)b;hGynX6zfdiggE5LR~5}P*6iru_<lRJC2Rcz+~LAr*>Rf
z%wgbsUyy2VrQpY+LboP(R3HO#F#jfXYl2noLAu9QKpHq3;=AH#+0I${I+F2fC1(&E
zkaivr(36E9?Qu`{+u`+e)Q37RiLYnNdRHmQGpC8SNRmyeL-WgXfvS!sk%1djJ4DRc
z6rm(8si*>`%iyU#9)v(KpiE;qbNJ1J7T`XnmGUL+nSVx!R!hf&<oMwQo90DGyjn9D
zo%(R?BtT)XpW!n4@+cZjd%5nC`#t2jJ9pL^zH7O|9Cf?B2KqzfP@@6=KisojOoGY7
z)q#L%MHP8!9dE-4vER7!YxZ-&{v&nSa2Mr7+b0`*ar2axBR5zxbY9hJ%kn6I3_0WP
z9%fyGkFbs{g1b59KgGU;<@h;efJ~_&HFKs01+}4J&&Kfhm$rYy540czlj0a%R0tOZ
zN}+&5ex003BF@Ksz0L}9EsdxjNiE#;LaY>J@I83rgPX=YadC?RnYO*vLyOL>v(`%s
zb5tz|pSE_H^qLmA_zuI}*kgT?Hc!!chA%1eBoqFt!=AIc=#8%WN5KA?Lj!QXE2!#i
zqpqobit%LvP47~~>jOP|0uAna7TyDhe6dX3{lo#^C}QKa#5VsRkL>zq%&Y5WK}^5M
zC-&ZAJhWM&06Xg$oC~GAR8HG9no9k%Y@-y6ryRf3LG12uFqwa&q%@rd5YqGg&0#9q
zXHL}E5aaS6l084&*wzFnU|cJ=GSUbQHn1ijgXsz+fV+zAyC*>D3-aryevQ;!y$m-R
zdK~(-F~r#_N*x2J>$)<B6|KXWDCA+OCR=W7_R5P91g>6IfuqZK=^Sa?(h(;}uP+jZ
z&b)=2Dm0J2nk<JOrCxD+Q%u?QT?`KvSI#<<?}NL~Id}U<eDT~B^hW;S{E;6S?rekY
z1si>%JZ^&|74}6E1se`*KtB5`8cc13YhPxT!-XU4R^uBrH!nd98r10CL<nx>Qb_^L
z`Gn{jvfkW2VDv_AHUZ&<NI4r<2QDn{C`EHAalShZJgR4p;;R?QsMm%S(^}`13i8M{
z!D!On#0S=NH9Zdv){Rv|B5_)@;!EjkYwIO?A&F%*8D#yW2#rB3rAjAg0+VClgxD99
zDSbIm8R2Bq#4BM>q7$eO%W4A^pq*#K7GZgYNcPQrhug&18fQqB?%Y4(XAHmZHwC^S
zt8}v0%@MC!6%nbRtm)dId3<9i>F#QIsTgP&t9|J+G$ORIaP9EE>|SK}0bweFyj1vd
zf*R^lidYxzhzSFF`o&bN*L!pf+;q6_G^=7dkZE&pRI3*`qiRSNW=uK?;$r*oC?4R)
zD!7n8yEcj5n<#ph5Y>>ld^U3EnlS$JC?XS{poBJN8{C@QvFx9zC(*)B<y!VMn*ZdI
zF}p}ay;2Vfre8$>NDW*OXYs^^V32*aI`D0Rv8JCgXi`iap<$KmMeXieg4HSP2eOR{
zS%DmhTTx>W8;oQ3#d~oTHQgHINMK3{V%yh`=01Drz|^MqP~Mpn{+xOfxz+ZACVJA6
z$Pr{0rhnQR6)X?KKv^1FhmQd;@ekaLqu_ys?aj>FCq{&NgGd+)7ZlzMZ#f;c;6{?j
z!X}EaEP;a>(@vl+&7Bw*ukciJ*L9ut<yy(4PJ}Ils7ScmA7D9F7D+y#nJbv$=&9FI
z^oEa^!`jfO7O<wmY;AzXfw$md<wnb328nsPt?5p~m$k&<=(cN;fq!Cjz<*#TXr~LN
zM8Hv2#A(KYRvtOTgKFp{>qExfgRUwg*peh<D8|ENy<}398@Tt;hOQ*=h%v<}-LRpW
zYD?jzP7{ZMSBY*|Of*6a<ZM7ueB{cv{=1S15__c_y^sG<UM&yP&gQ{GYZ_VWAvopz
z!<d2VXz>ukZ|O)ihIGwCv?JSV;r)51SYT-`RX>H4CWH$H-KV*Kp<_jxFf7iiDb=Sk
zb#e%HpME<$W5|72ZAJUUEd7&_$V3AAPeVyP(z5kh&YgkHM+{Owk9!k3`P(R2l@#5O
zsw&e7Dy&}oPl)L0$KHkaB5vO1fRlKw6Hy8U+rT9zj_l?5Oa?7YUska7^1g2VU~*AS
zSOP{KDZVRjR+(htffMkw{!<b00_DmgsR1im;)!{W)fVPReL!wXyYD`5skFfiYqzJx
zj$!9*d4zhTl2I-VDe6!$Cxw&bE>WF`jKVJ2X$#iMe{4x=X=5Lib;1C0ozE*0cRHR9
zxM#AtOxrbiHxgNS`8g;H^z<Qs?ba`Wkg4Qq`ZjaG-gjSxkL&#5kaZAr{bKDDk7BzY
zbYMkz3&kaXk0zgz$tRn!7s3?<AU=|o@lLEwKG=n6N$Zfx>#tTsE?h2aKQsN?F?RWx
zD{p~O^Za^BFQ%`(pOSc2z;cERfYR_STJEJw$5$CAnv3jhv<LRNK+OS`Zjd&|r-Th!
z*~}ReeiEM|$PtvGg)jtd(mJoXJrjn^?NS?5*x4AO8*BbjV-}d#g^}(lZuo0unIIk1
z$)-2|_zN1>No=K0h<C*f9$P$vyb9znrmz4^8ojC}Bzh45bC2!K?Pl81rbu2(AfN=Z
z#;uN`RDg3>)qF*4sC;0uvW|%Eo^?sM2%k=yoml7$J1MLe&iX=_Z!RAOT5hC2QzaU9
zU#z=&*l!-0zegCpGUi}7-Sx1td*32Ak+}9&VS--SLP%EsjmogYG?*rA*=wz;uq#D$
zGMpAvXPH=M!gV&FkvOq`^_iUR^_usfl_@pb8p@f~N{UcQC7}<kld~OKi8o9Pa=EEk
zX~Uwv;-uGPG3fTOZ@xAB7A5D@Na&~FbqgW>_Q=XYo3WlX*l6NzySa3OwS(MDj~JLw
zoy*f4L575&t?)OJe8?7tfJdXWQUYc9M%qdFA30Q&eKI!R1{W!})iweS#jjSDTex?Q
z!FS>~_P^rz8l;ER&MEo%r3rMN^z76Rkhn-d@U}CFZD%9;s0tXS-1S<qhpzo5Zt{QY
zgSNNxK-=UD49{VWuz}!z@4JWl8a1apI_*Ya#IKALfD=l!C!o8Z=J*%jeWs;LtOAGV
z!)AqNJA5m~4eu8V7c#3>a}0?5T)LN#xn&WY&q1)xu|%i3!|6ha33MU+wnH)ccQmx0
zCTBd|?}eQZy*CuD3mDZrP^QcI?o62!h0mC%98I=M=f8iH(OOI_CUZ`L=~TTNNt*d_
zS8`r81U{G1wHZi8Wt7b5?0u~7imuudO9Ts4ZbTDHC-`|h`*+(<K-l0`ppr3OUi7h)
zOP&DsJ1Y@%;?uqC--JZ@h^0?gpWfeCxr_uMl`upDHn6Vc4{a);ER?(0nB0t<9$Ch7
zsrFZ+$A}U-Am9#H>ay#J*4-td#*iG@ExCE~u2B&@aKwa~bFs%h#IL%aSfkvnd1o`Z
z{tY{o{QS|K7p^l$J34ILi1<J`E6Wzw_XOS9E|0|0i9te9r?GC~lPlb$h6yK5V)j9t
zAOI`Do!8?-E8u9VR_cXM*nho7VM>wJphcO?<ew23Bp&Y$#-p&}>$@Lo0LY;ge+e{M
z8{VB(!XQq1LgT2$O2DO`Z~MrD54||tcnHN}vqKx$o6yY6;@FB8SL;i{>?7$ZCkl~4
zP*NV!gN3z#O9NA=?I<To4)er^PK!MG$?@pq>!WJ~SH<b>l0$hJzc|5UlN+^_MeaBa
zD|BQ=)N$O%k=Z)r#t-f>%KS1C{T1*N<D}SBi4pOvvh{~E7Y<13Q|zIAzlf+T29Q$l
zh8-2ngWPyCDZ5?i`ZP1a2{eaCHTpCBn(@Iv_WUK+)XBx3R9HeP1-qOvMB~hBh%YJ%
zkh_+h41%Qz{nz47hHBvBlw;yIo%v8^mPcHmIJoGtc=wRkyRN8u$jc0QoT!mak`0GM
zS38CpXP5kw$*=7WcSyuvNh??<pDvVf2@xFa%Fg*|f@gS;N11(~J>4Ki(xUr+`f|^A
z$q$HZY)0_#FYc724#P=u(8qMRPZ4U9xf!e@{V!In9!_lJk^Ao%R`RPk87+fydcH(2
z*di2*u;b;#tW~p5GZygc{4vZcs8A{kl0}5M)d3dnmaOk>tQ6-TxIsRx^hJ<XAe*@W
zX;Kp!hR|)Ph1K+D9{HtyPKdyOoBWFnl5jigWUkyj##H*n-}ub2h+2o7C9D2VyMH=)
z<TtyKA0D_6^!(00+$6NFPut6Z-Pq;8Xcg#wfH2S&1EVxM#XU~A)t{D=Jvyxo%sPOq
zt*Uq(E+RgdI~`B<K>K-kkgvC+V?PaGzV9vl(Ex)6|7*s`;1=3kC>ygWaEEdIC@`C-
zpWXH=T{U;dS+x9xpso=eDM`gUjfyad&$1BjB?8UQ@J*V3<x0{JyYl}kb9KD6_bFjA
ztI$2Rfl^gF#>o`a%3gEUuuGR#S>@vf21-5t27d2+ywA>W`^#-bi$DSd9cV(eA8Gmp
zrRI3ALq{NwOPSNUJ2LFD523hTaQq3Lh6zP?w8BtOB$?rMEH9{mOoLz}%20Bwk9D%Z
z4yDxYYEsPI(Fk(mu>On`1!rvdR2X*T*nZj92-teRvLWzRo2VirJ<FWF%;aEb9Qf+>
zz;ff5o~pEA-8S!1r`jsX7Vq-fzdzxN#Y9Q0abRS}$fsk#p`a7t5|rJlt%UT;&v89L
ztG-W&Lmy`ma#&Q^yWf(q%KMM2h>o;Iz$Yvl(NP9V7?F9dtD{a1(gBNSJXTNJ3>-GF
zpJPc`<Z3!MbY+6ZI@6F_Gr2w#OJtpxJNo-A8qEv%vz56dAhe*EVmn%Jj(RS&Xwf-Y
z<hsteF6czQwk(OEti`!XAe1X7ck&p7{#ZLv{4kX1{%s=R_JeW)1)AYZ8@Gr(*PvuG
zj?`+Ex3fGGAw0o$gcvg0yjF)7Hcp{j4$%V>UC-t+mJ;VAD|5jRa*IMSGTmNUR<%*R
z@?F`(^Sbu+<-SXPh8-7pFu+C`H8M2x(2n}CpvRFY%{8huXy6J2mlX?>K(mW-u7)!U
zs15+KP5J=vv}UI|aASuD!IF!^z@jbie`o#wZ3AsZ=7`b8L^dx3p8mEWV#Nd?j>&aS
z-6bIU$HUH-2Uoh};nA~ba`G4FI82Zew-SDIr%9tYO6P>g5_jeEi9un+CNirh_Ou@K
z`uODtZ-R)y*MeCk!cSv~gmV;0;FZuaNF6YZiYjKQLJ{3|RgSK;xO2a#m`G~jiNee?
zzBq0uXFPu2x9H48lMj7@DkYW>G)_S4l~15{HwlMmB*jgo!8c{ihY@_beie^dxMFX?
z_n$=h<GT1<Cu-@lFrJ&MHgf9;1`uy&L>|bwGu&(o2r%tq!L~BRs*QXs#RKNp<`QWL
zK;-B+Frr4!-gcr56qd|Rl-0ymPWeS;M?KdVrQI^7v9P*%3*m^|6FpSZSfI_dM2=;B
z&ZIoppzA&bymB4?a1BdGvfI;+dG^CwhGEOO1H;^vH@}09=9%d;yp+}OGUB_gs15>L
z|9OYd%OACIu7a^=`QWG$x|eepCtU$4CNP4pFqKelcDmpWvZTZPw8Zs97Y>zub*|^?
z)Pej*HcCUNo&~+Y#OqPR#^x7Bo5k;im^G|Jv0U{`xdDxU!iQZ)jb75(07~NeXfCAw
zznhUg5!T+9u%DK5Xq32gd<no22;pmkM<QP76~vQEeoAy?CxSqRK@@>|F$^aKcEnZ1
zZ+~1;oUB4EqgD2S$RxS)cuRYoAVv@Zqzanoprksmc4adhvP-Urv~<gp6f?@T4^Zto
zxWq-vWogv6ptK1xG}*bF0tbX)Lb6B&#3<v_DAH1(=oZDtu-v~du=bNqtr;R<$Wzr8
z*VTramUm7800;jnnI}>6p#8x}tWy|LQSNJ3OqUIgb$>%u0&oPwhOfP34vcQ1k3DM<
zV1k2nyW_W(%I>8<$vp}G!EIgr+|JfkWe0#qipZT?v9Mi{Q*4F<-NJ4Y>1zUh`&VXH
z&CdTw03**%n;2Lz8B?qemGQ5d7N?6dl^Avto*SlB76O2HRF0Zu-{Nv}TM^{$Z*|aY
zIAi5Qn|;XTq@w|8%zTQw-QSnAWLv3mVfQbc(86jbVpcyo35%$*fes%j>t>rI0Yfx#
z$uqte@Zs<r7LUa!ywCLN&t05%RW-6Qf3koF-Me);VYNY3<@G9IGvekRd`@qoFweNI
zCje+B6a#JLS+lL_w<ZogRJof@nPKW;BLx!CWYGIfgZnqSEx4L4ym(O98~C!<>lyN!
z;(5vE$}Keaj6B|Kyj_2ONUEYQLe>ooDR?$&1CrIFHm;||h1AIsJQS`~iauf1h!zH+
zH+;R&mPq-P_^9Uc0|nsCCb_9GeEr|VEtRg?4knbtc)XZYtM-+7PY9(*Pf$u)5IZ@k
zlAHoigt<n<ay@PHi8@WCHryrJP6p@<{KEp9jvPvcu6x4Eh!EH6xY>S{L1t{-S3Rl0
z@+PSmBbKcEwy4`+BcHEaQ|6e8XG{G4JhDx&tCWoW-P^vT46%%7l4Sf^>5bE|`Aod{
z3roy#JcIMLQP1YAN3qC6ol_nc%zA}rzC(=qM%gjo<8+1vVQREprFS$&OF!mEQ5Ydq
zmX=qfXQ)Jo=bpeb(rjOZ<1Z`6!c$OI^pviB&;tF7V87Eg{BLqtntb(Y(_lIc-XK0A
z31xb&c1U_@5Syr><5@!@EB01NZ~+@r``<GV%kC~-pM?J(+2yl>4h1ry`4N?Cl92wP
zg_0E9V1XQ^q1`XiLuO+M#jYia?D$CkCGKH_%Dal&V4*QraUWQc&pSLb8QMX|RlR^h
za-mB_a7QmyU%3ZO&<_*c%9#YPojKoXtp%&cPpY@jeDmF`2LT36ekxU6+?D5aH;Y9$
zX4WdBVYX#`J~#^P)1l9^%413w)^G5CFqBk&Fjgb03l`(H8lYY8hxxqmlH|SE5p9@o
zWgal$utBj;Jl`gsUH>q~jnA;-_nRHRgb8<B5ovg%zKT|3T=O1bxlfKTZKnuphpiQI
zFjCY-5oT;S!gE_B8HA>E4Z1ykn9)ji0@l6a!5<6psOSA5!8<!q5%@q{Xy$w*1xYqT
z!S@js)9$j)VmkdzNI%(nWU&dx`BB?X+tos$RUp;Jgy;W6131gFL4o`5=H%ba1NlRk
zB(>bC)tV+<s3!Cb6}F?K)6<V$9~riYX`2KvZfn9eKcN@=y|tb-!bvY(8|gf_g^rzb
zYQ2|39Hj(bmR1q(-^_+pQ2OA(lTv1GcccxFe8rayV7@m_#G^-6cl1c-VVVD(?5Q+t
z$Wn{PyU|}%o}$0drhq~KL4Q}z(>Ylf_9aM6rIv}R$ov`Caw&I9Gl{kAQ7Q(pMah{7
z?}HK+d}O(=RB6dg@;eKckaaj<jR<|%6j*`K^l$SP7TZwL-x*#BIUUBe0<?ke9}-oN
zYrizHWSmD4%){19P@b!lEeDX<2Np}!8!pLA*=~<u*=irZx^F&krZCL*A6(*D6(<Kj
zvj<UJDB6U1y6j+zrA85;vei2M;6`mVg%JD!0l(v6c|wEU6I-<Cb5igL-{7C`JbYB?
zns#1K@^#l*bDTe%XJaVBNoIhtWfWX1f`sSri$q`;^m7S{73?YB^@=1pXxTe#`Jw-p
z&HOdF)6dK#?sYcIvEgnWJPd1=WOdT@)2ildMxV~uW8Q(1Cpm`5;%ReKp`d`JV%)F(
zRerPdf5}(B06Gt~9AuV--J3w8^Kx|HOCqa-YZ8u4UQUa+q31JUSZ}GG+-oq8wXyex
zrS}9lUJT&nq6=B^rJ}g+ukY$dz-?Q9MDP|dkL57yrZVadRqpb3FOy=yLzBdiC38aM
zhz*J-Ga&g?A812x4l=c9;?h*7JiBD?rr-}*VCOoL{Kf)4eL|u6!A8dhcIjF!){1Vj
z`(}3yTCK=+u}e@7?n4@2JZ88gTMO_E@;p=KDq3)ywAmvK`*X_9z<H8dc)B70D#r!f
zlNCZKcSi#9vVep2!^W_INyKbsi|iOcpNvvHr6pA?eoJ;1lR#HIr`a8K!JXmkv-PH<
zJmSQ8BzO4#lGPx(<uIGe6<(xBA42iztOY!M3S~kq6q-;rgJzM}ZTKz0SPmBuh8Z2X
zXT$IN5PyDX!<(y<6xQ#N2&gmS`H29WiynW6;SO6J9S=zOqK&p@v1*sh{g`{t&Ewq*
z755I2$_`fG?}EQ{d)G`XK@n8Q8}4NapFnJ~Mb^kI+Rp(E(hBi^Jj7BET9lj?TsYEh
zXf?%~2fCoWJTY_?mTo2b+2PNSrJ6E-A>epnxX($`1_4Y47Oz+VG){RqaVE2V<3jDJ
z^b{9HntM787~<@&Fw~5H8w3GrfFv&6bap}UH>{TN=_Qa;e1&Dr0mh0~El{0T=dny^
zRWYp${;8wP#z28MAX)Pw^9LGaGK<g3%?NK)c>#pkG49#uHCoODYO9lyOY#7oCE#^W
zvC4%zT6jFyG1BG-`^xWDWHgdB6L58beY#yRnXRb##nnNCtH4Uy9?UHt9s%|SqL!bA
z_$hmVm)>Kb$%I9CyYGl1jzjH5<5k`gvaJA$JcFL?f0u<)J1g>Z_jxk<xG3EMR~eoA
z*Wrkjp??q2AbI8#x(@todHuT%jl2*Eo~h5hZdbeutkYg_9%8FwEnN~nc&<yS6;L;+
zvt$-p(95et7y00r{l26M=WG5R)s*5`9>(fIq*wiO6%fn{qb_+R&9S*UirRIm^=kI`
zJ_S{^zHSUEl|Bn++uGhXn!<LLea(j^`%&Bf0b-O`KOmlg{Er@2h+nlA2q^pwFMr+p
z!Ec8U|HI)>P|+Lr+Gl@i@zwm>);j-)Vqz?zyV%JmRQ`eCR-ZPcYDe*oT%Pwx00i-A
zo2JmBQRoZ>mnMf!m-;7A#*rUV$QWtgxzO}yk&@tp9|+;3X&4yR^^e3lY4iPM6g?~s
zvTHTKAm19KVzA}be(}+6kGGeXvYQgvbA0-MuE-^6@7lFWPyq+=Q5g&JamXO5LOEzb
z)!N~Ok<J>}1cKeZ54`b+Kk{Ugr1^Ie8#F?|bXXOPHMi2?%?|wb7`g5fCiQThyT`C&
zdN>3$kmeWZnSF^hFNN@B2jDX7sciPE$oSb!at720eCasUp9Nv3!|T!it9q1eZarJV
zLJYj=Mnwrjh!hG7GoE5>;=N2TVvN*>T6`z+og$3vmHgA&w_paTG$B(93OP7M!C|f?
zl{<a5GYonlqmI%GNMefpk3(b?dj%+}qPRsv^nu6Ty=2F;j5e2bT1D}l*JY>dEH&hG
zgHkvL`06cC9qwVZvEcQqa%sV01ealf`2-V~j|;Kj!n|JcE%PdI$v(Ca;@=Oft{Q%{
zBQL3^WGE+c!X@%!h}EGQ7Iv0ZRGnff?-J<$O35%WJ4AtB$OhX~kf375h2A5l{IfE)
z!Evor$-5yhJtfOYx;M+bFABlM9X)AD%voP6Mdfj;V}ToP#A)>bCGL~Iwn76VQqBnD
zQW5Pns+q8JpQ2HyrgMoa;e?-oDZZDW*6mue7s)wUNB<tOGRJ(DHrwYw<gdFRGD3wn
z(a5OT+gj*{M41Ptg}g36HXELnSx;9^a=~%!a-=BcM}2FssnzcH+aK5eET~<N_tGyW
z*6g<&hUawJu1^z`Hk35&-hAbzHIkd%{Ki5Ixe0|HUvGQN;g37{h=i&{8C?-lMN7!w
z{a}8|ESCeCKULDy5yrFOU=gVkgG)9wG?NClAdXSI0~lxC5aT$xqLo4Y7kZ{-6YyA{
zX>@(&>Rljcn<)mNc;-)(p5LZx%Rp6H0cploxr5v=W*A}ptrkrzB+3VeaO?1>C3if)
zHtXO*brkjeMMJcYusIs{%L6yJWy5^>BL@dny6^5sJy*8OZEk+kS%eVHW9kF{fc|X;
zPB>hQADw$DhfYsMKk@h#OWYQaN{NYW)|Dh)w(pQQ!1w{7<Ib>G;U0rF5~(ztaG$=&
z?8AT}D_UU}x5RPr7eKA0$rEJ#rRDGNQE!N?G3%-JvtNd+I)`z0WM;X!LHHN}<Hhlj
z9SI?>NdBZE?L0H;?u%#Z3kf|V<xxg>boN!1Towz~@DS(WhokSEofH$VI47iGx{n)i
z$(1h}y<R;7Cx`~qOK<*0Oe7;0&NF0V5sO8GN^vb(364dinSc$y2rM#wRF)|ec_KK6
z+K&~S`}@dpAmy(-3mxjZo3Bq>om_9qn+$0%{K5K-%fVi1oEhH-gvX2w)f6skaCSlS
zx|^zlB_pD+fsvU&^b%fvl-nm&wYr$*@Rgrlp@rM$ADBu52ZdFd8H9Rj5tb^9l!z5l
zHFN2(=<+XL4`mo~Wwa3f)gV;MC1|1`^&~ynHX7vr&#20xuviks=fuj3G$avwrjRLP
z*Y^&A`1;lfYN&ThD!ZUxsdfu@+|F?VN9toFv(3pRM$Ft3eBLz`i?K<mBf(~y^YCeN
zEbCge5joHaLQ$O}%C>KPMRz-?H?luXL25=+J!wB`aM}k4O{&`xo&#&s#lkW*2wadi
z=jm){)JFX7awF-I=1s^i$Tnm4DHqp6!MM(PlOB13w|!bAptLW^l*h^O??}ZZuZH5!
zwXUYyx3YgrE<R{U+cJJ{plQgM+xe+;AeA!o)zS1A&tOWUu}0*ho_SZu=KaHb?3uLb
zLLjDmV2c?qi4)Y(Jq*+@ubQCIYjfCntorrhh>!oc=7GUuXo##KG<1eL<V#8@*-pqk
z96eA>6~Ci-c%=@mj)Xu0g*>4M$81kS=@nCT{yTk+$7(<#u_xf-DhuaT{oomFnpJkq
z%ooV9P1%iAXvw*8z+q9A8=2)KqSvCuGW%Se7)p+W1>Qw-36<u0q6Lr7ows`Sj){#Y
zEQojTL)|ic$r1k|e9LSkf`#m{+V+hA(2fKKHEm@Yn~Hzq-mAM$r~29d0hv(QVz|$S
zDMS2BDu~4hgLHrdBseV>&vb@sHp@X?`H>UA#|H<TAyWT<>SxT~R(IM5sIRFW)onm%
z3vlSy`5LXVqi-{gEGT2PT>ZXp5>+yk2_m1J@7zwTApfGk6r&Dp!kgQ8ae%V+6HDkl
zCMV(Z#bnWZohD{->dYRCcGVr7*MV@EgLNC0aK1mBt$o$7&W{46{S<arZGT{RNPS)=
zg63!36JU|-F%nLK4W8n@xf_>fCxjt*C%s!X*I=dDa#~c_a?A3(>6P*}ew#{)M$TAZ
zN^{LtwYJ#T&Xx#5!TzIRpE4FaDa=UGgU!}EXwqmxv*Dj!JW)^pxh+Gto*@dK+7jJk
z)%^2X1OmlC>H`+)Iyr6bzo&Si8Tan_)U{XD8aXpzkBD%wa;J-Ydy8@X)vZ;KAPGWk
zhsH=qhB@g<4)LKE(9k`be4;Kr*ga>_i~#S*a#Da36e#v>=*?h3Chy+2;&6wi7GD>%
zxpWsT=14VR6`D0W@G*m8kD%|YMNp8{E+NtDSlNw1(7!UB;mR4edCFO`{a}l06uk5d
z>GTe6t;FbqnQ*K7N+^k0QiSj!UrOkuHs`ZfSHDW?AQMgNR3vk4aa_~MONUcvz`^1f
z_RvKMMvoS)?vD+?&wB_$zeux@<abl46pSQw5%)80-tM<1Rc>625pkk?L|9NTV}f^d
z-qG0$>#uUmY)Jw)tk1;ZmFJO51tQ{+)yXZSI2Uo+m9*1UHG53DMn~QzP9i!MIJB=q
zE<r%q!=<~DT3v8|1K?)j?(GFD`~bqnU<3ghWRwG_hrUyePtzJ$zWX%OP83povfDpD
z+=T4|3@(AVp8(Yy^0klcAOLsP`ZZ<6ISy>zb!CLZ7hbkzp+E04=>x@yq%|-4^cIJ*
zIb_zHw<4<!_I!VEaBsz6lu8xV?SB5P>J=<-hZ6wrIKry#v0o5<RBNYu)LY(0c*PkJ
zo5H7h@`IT8#^}cSw_Ps@Xi;<c4wfwsY|;j4F0$R4YIxBMBWmSCb0@=qGB)kGhzH2Z
z{Zp>bOkv7gs6wE>I8#XKRN?5G=&#zlJzHaFMKhBpoB(wO0ulmQA+&&vD7y2cFkStb
zFfiT&d#KBrWoW#$1w$uGUnoXlHn118KUa_(k|N^JLCNuSZ~Ws!$9fe;06EW}qUABB
zyj7OM3a<~V&uQ}!)7M6+C^m$G5&Q}ycwXOFsz)EXD8s}=$r&dJa7Cn722wUVi74wY
zP)KeII6$xBllnM>I6T#9N9W`XdSSTzzp309&Osnd#mWpvDAbp{LzC=ieV76tL@`Ca
zVqwxNE!f&65_5Y-AV)x}d|<vpDg?<S&7zbXCaqvjuK(sC?$qyixtrSQR=*NkPZFfE
zh-tBw%CtmT>UB9x%;l#o_t>EC?EqZjBQ(aaO}uju_j86Lw|*9H)17~}@9mY63FImJ
zy^LIV*Iu>#kglpbM%+u}$w+5&T;g6{bP#rW3d`F42RinCSFAyiqG4CKvXZD4P1If!
zDo+>hNw;!^5#S*_AA_=vdSrftoLZ`+9YMM>{g1^Db{MNo{)5gp9l)G%uBeJ9X+Udn
zs_#PAB})A1mnA#UM4T>`YoD<!y)lbuxRtY7Igg4VeOC_^>z}Ybh%K9s5~<qTi8#+-
zg6o-fLo*Sk*Wx>z38(3Cz|#wu!)w2UXgqe@Q0{MA+q**a<}53)O~9F|Li;b(qrui4
zF!qp9p5Kn#J<Vr%4C4X8KqWvj1Bo%F#us4z8%N#yTYa3j_w|d3eYN-rk2*oOGX3pR
zfIb%3gc`hxY7so;=sO!-gnVI&(i+&-L^xjbFIXY&8Xs}AVC2B)sdkBvXR(`rF@4FO
zsjp5NS0^)7hlWIvl6mJ5MtJU*Y_LH#j8<<ze`KtJhS(TuIdw>_g?Zma|JsDbZ{w1?
zz$T)?WhmO1P^n=qHns?qTdc*atB88tLT(OJ4&7WF5zLo+8i)DJ1qQhhg04se;gP#J
zqp5%9dMO2MIHG}F?-pgyL!zg8f9C(0L1{Wy;imM`69!e+?wds!&~Hz@*G^fcLtSRW
zCVfycFs=-#@x^*2zOJyishU1KYeLZ*gn)udt>OrgeWkZc1Oeil#cnmOLNr3wR|>=l
zc0!zXKudUOWlC_!5@A~Bc55}uD8TlHFcp}yPFz3lm9(+m{nyDaQ7V!nG$I*bj}YfD
z)EECD<;wt1WNeN*O<1-bNn-+6p%Xq2Z7Tosz~p;&BFn2#4}DeDu!mN-DfK>VNk|SY
z&c9q0%p;F3G6OH%&4xriMF}=bL^YmufJ=dgw>9Ti`{Ffcs`)5TyyyQ)S<*HbIE|+E
zwbHW&VQZ7Q(9yCZ(MH+E>MNB#!p>_#-hsrqAazM4`}URZvd834M8|oi-Mjmm5^9{8
z4jOuBslprgm1ZSr2w-u*9-;i_9|Fq2$$^cbCG&reO*tS3Jyz&a4-8Z@reA_XeaVM#
zs2@HaJc(73REZ#*bfn_p6!eq*tna$VZY19cZNBu9u9jc*-<H6p8+~!xVqiQcJ^jK2
z!fr~}dP{r22Dh}gwV*QsAH#2BHsoBZfXL^N;&JgdI<q@*#Gy)e#XjFi18FT2-9aD>
zsuBuKI1-O3g>a9TXobPyO7s@??Ia5dDf+7>p@$CzeiyiEnlE_um+ZD_u;Jgfdzt9+
zQBY0aDA3HbkG`KkIattN9NQFgod=QXY*K}$PLv77HUvg3IjP^*SizK_ARAx9tU+xk
zT$vm730A`GG%(bsYLpT09%&IMx$=Um?QkZ!K%AXugzDWE<ypV9VSoDjpk7?YpXz#X
z1;r<JBkH9NWQ7G+-is~L%B~F#r9aIaEo0aQrefw<D?)9bQq^RmQ^YI!=x90j3ATSN
z8{iArvRc5kfCoc4@MXe38#1&f0Fs6a0A~%MH=F3g<Nf}_bBk4_59;3k9#K-P52~AX
z$RNAsZOF-YZu{7ff+TnfvEQlID+Caj=uCO&D+ebce}HIEq6;j<8Y4#m(y=PS3l0H`
z)qGDXgomMH!k~6gP}O&Zw4`d-|1JCzz5BFjnV_crh237}_LeLz_krW3tSzx$)^n6d
zG9y!y#@<rQS*mPsG;~w?zoxzIquT!-@9s<?4hcrqU%iJs!YYdP9g<mEBXViNmHvXG
zDgiz|J{<p4&m((tdLl&HgCU?L_bK<R-m*o~CSh<n_mWrD70jS=eD@r#_j)>g!@dS(
z-zMJe;mz^QH$Exj6`x^5pG$U-65CRGcGJO%SFlk~5_O|96rzOQYlB2#*AF|wRYd#x
zW)&zOYhwVvI2%+%&Tx?%c!Iva6P^xJ-^b&Jiur<1x#8^dTknt69CDS^YP1u%-A?it
z^`(GF&qv$C&9ZOD5Cv4pyi+`bLf~I7V}<LSJX3bLzIE#8vDFYvMTf#_o<>enM?!Qe
ztb6+#9<qOB3HGjSz8ARv2%Bw9PH>D}#G~9S5UM+2i4D8QQ26}w#9}R~+u^d=l)BfN
zw3Xy%5GFfPla$W;^ilmeUzNqzA@zdMugVw}%qn|e*6TTPJuG3OnI1&EcjYUL5#^Vn
zQiPm7E~pm`$_h6GO#0NgN%wKR{vKMM%<zMtZ2pT&Ia4%rK+1Hh>m7gwE1!TpP1pU7
zHu)3pYMv~#v``sX#&iAE|0iq+?t!uB*%y7VfT{Q?Gz45q2Rl>lRXY=Oy7W|kBuP(2
zPlM}yTJ5s-g&nz!3>-=u8}Ed5-ao>HVUI4<D1@<0ysh4CqMyzomZAQ_vIl0HkAu24
z;LB(pss}6}Ix@)7fCs*a1ExBwlrDhhF95gx{^%XKLtrF?m=A(F8lY4HgrsB&z%uuU
z-k>$W`8YZTg?|SJH5yVLcgkGt8P>2H6ANfr8t{#L9Gob5JaF>=MR@F1_a))Xh!XVB
zu)#5FjYBDA!^cOpif#5}U?oW;N9Lc<+DR1yxQug24EsIqL}LD+X@!m(8zjV_H3*md
zEQB;90M4^4Y|WvQA5-j0GLd+4%16MiO)V!IB19=uFekvfI1wi6#*E*EE+}|{1F0oL
zkPc6S)9A6w@!~#=q*hF41L;^1n2j`!0xM=Cz7q%obP$eMELCXXv;gFvVz%O|IS8ZC
zODqPJ`;*f|K(-~O_6n%A-k)*&1H+bjbVWFEdJ0(8(3-EAR)ey)HslOh*7TLae%2L0
zTw50O1_vU>JUnxOmSd@WQ;cP{V98?B3n{##?=lHFFk7EIGpt8Jl$l2&6}60#p(wS^
zj7-19#dQFJ&TH~pDIagZwn|EcWYk=d-}DGf8a$H4lYX3rH!vFqDYVl5uq-w@uSFdv
zOiM)+ZC{}aTT{Nkj)SCLg}+|aK#o`GrkiDJ`tOOy-8KeMXH$HUKVd?-Rc5m#yUu@@
z*0t1i8sBRKuVIahs6^i0(*Em*W{!HF-_qSp&HQw`PwBPV56yTi>_Md+39Zvg&CBo3
zuFAUzO#5d#JFWhWS+#Gu;jrl>?OGDhQvr_yaQtudIsG_;e(L>rt$)3SdU{<(Ee7`h
znxJW_V~u|$dlK5)NVWTii8r|ALpnX9N?ZeN<!YUJ;V2;h4mhSF!fQScun1yU6CbbJ
zn)x!8E4S}%(N~93lg@?CM?vw4Lki;xMx(6O8rzw*g>BCKd-8<|h<ZS8LWlHaNft=&
z<UF{V;PlK954=5U=)-Lj?Wq@JavIfnTl0f60|WOL0TN%AfmOsHP=<#XrErJCEqSU0
z@aL;}^xu>cNW80~&K(X%96;Fvv;P0f1Nh)V2liO9;<s8pSshFU?Z1ri?^{+WZvogs
zNts+=b4vR|qzNx30=lueW=UlZb8HOHX*h(SrfkW?W()~znbu<sb6}9Q>FRoDNxGM{
z3}~i**&QyO-OkTzy^LK$>H)X!U5-wbqxJHwiNi?UD-Ny`I8BNpBSHh9V4<WG7m5Z7
zX{n<8&eq4K-iL;QwxwLAf&>bc0{JuZus7<$LS~8fEY~nvgZ)Qj4|^T8Egu7VW<Uf@
zkXkNF?ldo9NxLP+HtPM{<Coh*i?S>GR+#nQW*`1j@{NW3Hk&sVVsxZ+>ViSyJi4_`
zhf5q7$YbKrZlv}xYEPD<t}*@JYJ@C|IJd3|8rn`xh^8bCo;2wp8^t#^;=5nkVZA&J
z1)Yybg)fefwx2tgCuh7;w!*qs11~cgee$kSCZd5)N3fDE2W>y+hUSnDSt^tl@9s&%
zrb6mQmFvALbcGmQ>S%36H%R31g_S!C5p_uZ(N`Z~YmKF#_<9b6`BIJPQc}z5+k4)v
z%Fy1Z`UEcz4ekSzNAk&uQD$({1xOurs3EG$Ib0p`JC+e}<;MiagD^^yCm7ar<`G@x
z%I)7myy4hwYIEgU!Zxvffv>aO#XLGfPEn`6tS;OaJRQg>03(@XKo+WPxtUK>_W5rQ
z_eXfDf?NmSUn2cqI~fIpS&B@^7)nC?g^lgfOiqZps!viHoA%V{eAVOW3SoR3D`mG8
z#`#NP`RU)XD`dYPH5?l9(}Z6fi4X%9h?4FdW)=4UODfj_?~VAsC_@}@#C@Yw|5~Xx
z>;xRsSbV#Ep=Y7TTJLL6R`SfTUvftv;P0U`y!`)=_4*$;Bn`DE{)UWjhXyw#6{Nz6
z3PdUapj<D7dsoM4PwK!gM9h^k`?u$Q#~_TLd+4AIe2$KG(O)jo#QmLQQ0S^shD^-g
IwJV6U8yWSXmH+?%

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_gen_host.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_gen_host.v
new file mode 100644
index 0000000000000000000000000000000000000000..1318818ac700931cc702ac974c71d67504ef6e9f
GIT binary patch
literal 66696
zcmV(jK=!|j6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWd=m<P1(q-Ht(Ri(NRjp{xJ!<%r*kI>#RM(89vF>2K!^<%%<Zc#)NdDqb
z%LbPZnsvH**TiDPVtC1I^1qkqYW;wOYv`>2hnov$><H2`8e{&lg}`(PB-UZtp*KL<
zp#d6zIA9b%3vEGssiXD3yCGB!G3WsL8)^LLg3ExL%hN0=SIZtqrBT-?;L{@T@RdFy
zy3j^#(6cYW-gA$t6&)5wpXxoM3CMmFTT9T0(B{02ZW-I;2x<c$YWY6^KWfj%-E0VQ
z!SwYl*3#M(wTpEIORH_U-;I%&!0Jp5VTSM)!TZyB!!k>n?^&S`&roi7EIZ$cng@1R
zT^X%+u*Pd2!xcFyA4~#G(<LFfSyxt5Yu$WAkzORmeEf=6B!JAa$?Hlc?|cP|VMH=k
zJ?Ei1vsRZ%<Ypr9HMxk+ftlvta~K-8Rf8cpStEG<V4@XvvwRan=(4FRk`UMf$j!%M
zVdeTD%DQr}Nn7yA-Zm{aD_t$+j-;Vl1mQz0zEfGo_(5!p0D@bHUJ4AU%w!xNEJUd{
zZfd~{^nK#4TL&zgvXC6|b7OoRV*|XF4>k@vSGU+$!I?!K{}VHyssD<E9LFq28EhHv
zA|JcqWC(__y}FR`r!w$5Ad6|Wv|W*#jjbZuo=Wt_SipQylT-t|*T!GzV28mbFFozg
zG}%8Caan+F%MEw)GqUPh0p3syVWN{~3Z~_l*6m8lB;nML`yMDa4e@q>UmR7WhVNkN
zZ`Z0&Ki~t>C!Ud&$wP~;dQPct4tMGy2@R1aIPn#3^&<vAN(PlV)jC#Yjg1BGiwjc5
zEzAA<JxdCZuH}BVK&nI1qHAM9a${g~It~_U-4i!bw9!hVU}j&WA{&V*9j*W+I4u)O
zm0QB~)7MJQ{)Lx_xTes8ssQpf(>Y5CuOzJ5Gj-dFF8AdI1;VfL@&x_V={9q^-}^Wl
zUHOB=dUF%iV`SlU@ONxbqg*$*U7$Qed8h=Jj5K<6l`TuwC#{E0Dzi!=*bNCaZ!F4%
zkpL~|sKl%Com5n^J}e1hBL)iCL*L5u1Zao7SXH!jB3eZ6uIN)~Y_)ncsW;;sqUAEf
z1NN?%e)`3v&6B1_ncdB&*zH>gFlf?+ni3yq`d=J_&j6w1pp@%hy6}B5hL25%=Msy<
zM*=m+bq$UI=;g*9N0P`*XIYG=L?z2{bW^vzMFw+R;iHwd*P+Jty|B2F7u&lA?{Pas
zN9_^`!LnoYmM#MQdu;cTuac@-P&$PdEVS&cpOpfm!1cVIC#wz-wP@MBi&I?zA9p*?
z*Lxm29!T$<0t8eKeCNF!>&gY21NegdO`e$eDJgmYHhBREl$7TtTChHXsTew2_55z3
zJN^;v3cw%NQhiR9SC(gfbpfX2lGtGF*~(Lrp>KK%dJj~z+6C&N;t#ah6nVD97FN;7
zPzdw8uoe-;k-A(FFyB~26mF>Xk%*jTB<EH(QleTpii(w!E!<k$WZ5THG=0;sVNk)_
zvzIe{*O|-fDw17YRgvDeVa4vWi63g*tvq{J3rXeDV{`wu0Wdaq+C(ssm&Ji{dS+H1
z)xbXl08{w&EDc9+5cIn83tAilLuJy(aa^zj`=j_J_K`MuAyBCD-+Syjqv`v2HV{4i
zKmf_N$mNhCcV9ZkyFyZ$YLj;D-XiaulgVb!0VL9K&mMfR35SqQ&?c9|;&M0z2y-B9
zX>IB-jSaycbOEiLSLd7vVgmAGCYGv<cEyZiddj5?ugwHrCL@caDFH}VjwQM*X)lSt
zABH``?QIjU*)*cZ9wPln(LXg_ugn7wuEg7xE2fE|QuTCZvno`>Ab`NJWX~A*?z3(l
z;$E%WL-_9--S7kjvWhoQ|D7hiSc#8=`^cw&3UbHsI68_nF%tT7sJJGU3aMrGAJoCk
zu=^F9s<3J)+rlYpBi9-u??u>@GU&qA)OH>Vru{Is!Ez^+B3#tS=)obZzw8(<IN-`h
z)kIN!Pv2U~RWC1V11B2I%TEZ-16+&86RP!W2z5t^4DWoHpyPtD8O!O#+K)|HW1$Ap
zM!@#Cl{F5<IWURo7e>vq5^wCl)Rv_Ht<e6Yw^w1xMIhySd(Hpyjh8v+Vv$exScc-5
zklBLbk_?`P($`VWUIDXXFDrdjH&$tuVd1=iR5GA+8Je`8NZ;)`BSX@!&QmMcIw0dx
z;9epRA9!E1{_%z_%W4O%O92iFX_IuBBkS&e$LTjypn6dJyaU<^*iHG;jLPM2D8OXq
zE*Ml<yM(H1?BfaASXQmPE1L+b!d$b;<u<}LX;lOpL4=98JaoX343n;i|IQ6vLA>x5
zWLP~4UpR+sOP_m9w-kQ#(`MmHSquz(7xXCuqO@==NMH-DeA`irSadwl8<o@s!h`Ng
zCDR^D{2_q&e&<Dv*z53%(ak>9O4#Q^v)re$c?@y%7y#T;+w^Tirtb1yWgG$jn?zG{
zv@qEP=LVfr4QRz}-uE-jCiuOW-^PR-hCCMAzBH`^`9cOM&N56vJCg^66awzIA?8-`
z62ei!Ut<+P?9U2IZ5kWfN;p6?XfG55tKoU?wF~Fro-2$Vm1cB+6ZxA|Z<X$*h9mD=
zR0wJ?Hm1MeR9nFXEWwJx=Q<b_VC%Fk@*~hF6yJNGLH$P@O9YMIv`hhouyhiilcY+x
zmZR*UH};kO4<@04_G3I+o^YaRoRX7k&*e>z$)3jWudv4)z>O^_jqUGSKv^Af1=ej)
z*N>8K8VFAX-CUc&b!(ZqyQW_gT7$5}#)PYd?a`6IjqHw9YO$imrXk1WqQb3b1THlU
z_mBrbRpA{1%G08u=+e-Q%c-qX-DO#0w|UT`c=u~0#Ith3LayM!w%ZVY1hV+Hdz4IE
z!r^wZblJdV8TDLteH$ZY=H`SdswR)G`4*0*Tb2e9eq|mNiOX-gCpN<<f}f6iROcSX
z)<h@c>-guniDXkAHtuoK->GfqbZ$hHS+MgW9h87qEz7EJZANpMUr>T|%(0hnJOTDO
z1cMx+Y`ePMq0<=2O5kpwIPLlxU!24jrUtK0_09%MjmbwaWnX5U`%tRokZbUX%1bQ!
zM`-&oJALN?&w0tUsaFO_&MAo}$(qnKeyD<ErbN)(IhDwI)ea~LnaQe-x8g2P|Im6O
zUoe9;z>?7wCr#V)Ph(}7?oD0FC<h-HS8@kh(l-DW+n8=B7YbOU#1ef5Sny3PCZOiI
zX}60sFdU(}`|<KIn$s%oU`ury_tuzA+(p+dY&*2;kN<Rmfr<dKkOGyRFy#<qh}+1m
zgsU0^BLlpu37aPgp~(iT$GnCoXsS};(t(_NK@dG9V1yn$4DuBz61q#kSMI8o_h_j&
ztj+4BvbhxsrgW8t!W`*q+$y?98^pr5ZEuOV-+HX4C)l&Eaq5k#T|W?!dTN3U${tcU
zRXmVp|CnkxH@a>sMnb#bDE?@UdA@wgH%UBjspCl5eJ!y{bNn$SntF|8U<9#oD2Z01
z|6{`{@b6P5A!-!=6-OE3E#x{L7RmzgUQ+f)Gr7)vc?iQmZ`L@>+hxNJHqXN=3iFT#
zUbojy4ib?)V5oPY3%WZtP)FR`r&(ksECLM(rMVmWEpgJ9_9#`9FWl^UAs~Yupj$ul
zt*~*=WN@YxI6(X^FM~F!2NPy%VPym~*-yxA5^nh}x`%?ll0__BI}ER3!U;FP<8sw@
z^?*|$_+UKp(q%u)>QUH-=ewB_(RF{&<}uZ}@fXGN+~1+4Uwzni09Xvx*0QAD{R;vX
zA-UzTi2B&a{B5F__TnFXfS_|4>1q6Hpc;v(+|~oML#Z9yd>f!lCgx#qG^@Ueirq~v
zF_EK%wSgwUunYBykeTskloY!O;jA(x<}35Vd8A=j2xXffXFb!5C#v|7t9@44gY@#W
z*<nG?1@m|=^L51C04F|D1!wE3p$wGCabPwkdWR99`=hL(7*$=!?TOs-Bq*}22M(1*
z?1W|5p|;h5i^VIS2v><iosT%fNlkCIS|(v56H_MuxfENbVYplGBGEiquh%JRY?wZr
zh$X0FAO%Qa6xbB2Gx0JR(t6n#6T*!KDNEtx(xuKQD*Hu$IT!-RC7i7;Xl@_n)E;j5
ziDTHATwXQV-d3_3UXzI92>FDL3WT<{FlU6z`1mkuquC{cxk)D>2a)gOE(3ZT4}RQ2
z9eb>xlNTVBgJF6S6G;A{Sg&fiIJ&8=6W=!TJrb9;-$DUi^Q4U&k2)#K!<nmF`9}IJ
zGfOjV=0SZ-POxINheI#cXqAPsi=1dL{pzv>OnVQvLdnLcrKf>!_zN1S)BO)pluC$}
zTPc0sK;%fe-dD6YlN>{EP_DA&KgeK%V2R%n24O9`nZ6Pqee4|dq(d*OkQSxWrI|#k
z3w;t#5J3$sul~&$NeQX$x>DIz8X%$zwjHjK+>)6`uNxLX=Sg>s(Z~r!9BE(ap&Qr#
z2l|8iOVfffc;pqY!gWDsUsD*%umr~R6+P!tkb?E!*n9^x=M(d-oNk2l7o=aY2tX-o
z#)j-P;%@hPmPSW%(C1i1yCSS6$=Q3)cIa8P1buSVLks>TmB$3S#p!&ckFNvrcH?_G
z4jHk2;BlCl*?*{bc;!OD#UP`anOeM{q%xNcw~k>&=ui>4VQu~Xq|VLz?MP@t{$~jh
zz)bY|10v)yOWr6acm>=WH*d22k>)RLM!(``rr9dexh<ghU|wX2XnN=_Kgq{Ylh~7`
z2aRd0&KLSz2vsCeDs%sZh-+OzY=AZxq3>!8G{3N3a|98cs(qZ;QrJbK#MZgb0U>d^
zQ0T#J!?1?wOgV_a6v5D`qi`;e-sh0(O&^u-IyVISP9bc_n7GovRT0Uz>0}6UEDlEp
zOc8N_!IXxaY#gAFz(jqCG%`oPMD33}u-qdL@?>E9wph*vnBudIKb*#I^}1M|rj=Pg
zpZ5@|!zfBba@zFqw*Xn*2f8s_ieA%}3>vpcijW?0)UN>!Pyu2kctJHU#6t;C7$+6b
zP?1obY7WRJJXm$=JrW7FhG6@GoLTD;`k1W1Y+{Mp`$%cq*RVSfv04MTveOj+LxK}U
zD}=7K^4Iqr@8_zQHb>EUKUPGNM?XFZF2ov+c>Tv_7(MV(f@n!Y#N9)Hsg~;YU62NX
zx&eV@_vNYb4p(ZHwy<dwj*qk&HPY6v6V(&b#xg8%_V^{`FSBdy%+3aG_-7j1zlc=-
zGxZo}VAWodt5$6L#gBduTk^hKxD(nr5nG~q+<A3dwSpU%GO}H?B#&#u7r}ZNN3Omq
zXEBS^)7x(68$62amxDk+y*rILy8Gcfo#RCo{qNu2kz&>HK+;CS+%sv8&WfT(|H|>L
z>^BMd%>D~u$!Z*C#C{40`dr4v*<@x>PMP{LoSE0sPi2#Fho}LCkS<_by}=qICoqjg
zA5+7+h+V_vn7k=6tnHtfIPXx*NN68MjD}6ik1YAZF$Nm$6#aUxl^q!#JeUK?mKEM)
zIC`xeV@ceGDfS5gUAd;T0u+OrGyFLEto3oL({N!=>T7GEmD_uem7%H5VL(ZrL@Jxj
zV08j&e{g}hQIn-<XbY?*)_dWE#(aNHHgrl3!dI^LR9#bUANmlELv;TkJ5C?aklwI2
z&p7+~Z@Z14-*4^8|GIxo&?^o@DR{OB7H80|u-6Kg5Bu0Ytg90%dPSh&5fqGH$(a3H
z{ZkY1X?hgW#^IK&I2died?TaCE}lLd;VS!Og3+K9hrIL`lvgtd2!J*N1;4AoQl>R3
zeOKyEg^EVYU782&jX{I~=D2I9wf;g80URr2Fr*$TPm&%R(()CxD{(QLZw|y_vYy7q
zv?>*uB;tepnE(4rjT98#Z#1q5>x1is84*#v*KiT#+j?5Acs;@cUwE>~>ZT;<Kd<BR
zG7D7=mw=jsp>BA2BtLbRSL;=GHIkk^8b>`fvj2%YlbD{Xn)hl?!Z%=jPp8E7<g$Tr
z&Fwid_Zs<!(@oD088lS1QpKvu#K@y($iC%_=JCq({(HEI+5EDNJRF5!s$k94$Ou>#
zAHGLm&QEvk-9eFt>RqxD%KSGcA@}$wlH#CX;##Hoq;eb8^HbZswN-H9=$(URei6(O
zSX>{3$<ZS05pqY@bDi5B*a<y{6L)JbouvB@L7#l++T#8VaiYqa<Hw3kxk}c3jL<(Q
z679)n&>P>!m_x_+-zn#&(EicE?p>qpErA|_><{doXxZ-Vzx2bUQodg{ryV^n5<@Ql
zkPqzd)Cqj1`-Xr?7jx>7a=BK8Me@6d)ef;wmjJaD;3<&uD^gWz1bGGS<3Jtv7y$|h
zc#BJaWtmYWCs#!wsIgapXPBrri12Tt<#ty%OXzlFMBZ`z*>BtL3OQ}p?rI=zFT&`o
z{NLUg8Bku|V72y8O8}Y#J+_^kF@I7|FNNfPL#u08HL}<gr~JwRY%U_|af`!`==ZCy
zZYX%j84EgG74Xsgf`5a`+%AJbcU+^3N-VoFE*U!7>hj{)U$7<J4`_$3FM^mTu3+m)
zOfd!{Y8QlTv;PcFsEy`#wr;yR`^KGiLc8o+ilscDcTeGRVK}8DQGrFRvvC8kXnc4N
zavp_lgc@;Fe#Z|~i^WT{=8P0KcTe2~b|41W1dbFT5bAu@+?F_r57*Dq^~Z*LPwWXU
zN2H;0ozq?kf!hsaRS#aSH_Y9V$;lTCy#a33Uu)|3wgz*6SDH@3lXX?QE55rA{kWR%
z4)j+lCG8SoM=-(J5PwubAb%s?^d~jbnTiNGDwhn#v7{5dNJ?OpC#7yCNG3+R=NJ)A
zyk@!yICL+O)3>JJ#XRO;MyyfEe0hTN^$agy%UAzUIyp&-E4dWH=%ac`6O)rnI%kBw
zTs=e)2M>uxlQJmKJ0r<WgTQfvp6k56?(V-CM_fT8nhYnRTy*Y+clkUyF-lc&Pk7{3
zoiEU^$N`<}D#$jC1U3l&JSZiwHjy`Dqiy%1`GJRK!tUWiZp(GXcq@paVY%sSZ4d@y
z>6;uhxgOv$l<eMF^BdP~0$OcL?4AzmN{3H+5CRETTEW7j5$+lG&yO!H!)4TkwsM%{
zW>$AMx61Z}UThS7An9&Xz6O@r)yvPe&ZZ3i`#E3JfE;J*LXy7({>a_zliWZ%`l}z{
zhTvMy>ML76mfa`)@|2s9co&mc@C;;p{#hwDDU#u}g114DtaIBwP1zKrUYHfqGZuu7
zp+^yXdF?1JKbIXx9WwNcpwWzs=a-v5B9zR>i$f$?19TBk#UtqS@z`hKJtqd7X|BeC
z&wy{VETUJ|IzRcfs<^b#gt2uP$JwuU(JQ>f?v8&?VTI6PXcO|DJ$M{R?vK2kVkOVD
zt*+Xj!-sv7smh^GyeyzcznbU9`51=E+Y>B7AdhccsDgFCChUtAeN(%#L}fNY(44Gz
zHtIhshm4Wt&0m~B#IlM~w)}Xj_42pY2$!+FWYf1=f-$flZ?S7}E!PoQ-$~Ql4nRsY
zTkmG?rHhpIQil3Z=napzL$!^Ai08zk3AWn=YUOY@iJzH>Fa80l$pu0;)y`I0;DL$$
z=~fq-&~AlojWGaY1}DbUe{nII(R=LE*&5SMR9_T0)c8k7XRM<*E)B$_i>tBbiWvdd
z3C#!$!Adls-1mMc%)epKRkxwP7y0~ot84bRE2!s5Spomx$^|{7MdTJw$SPTz0o}WJ
z63(*?=6UWct}iz4%xE$3h+jq8?moQlRHk9k{fp-kGd5bl=Qvp8qwFQ0hqK>(fK)jO
zAFqm#Gh#&}Jxs@fOU@Y9fr|jhDXU%9vC-{@iK?UKu{#fBRkE1Jgn_4G*@iS10V{$T
z?y|_z>H>aQC1kVGe1Iy)JH$LtrFfpPa=pzgCA{w>gd7YRM>O{YfN0dM!9D7FD<fI~
zd$I#faZ~7=<1+7zwX^iGSw8J7Rsfv&QXbl8tU^0hm7?&id8p*IWz41a0a@SuArjtP
zW~K&w<i~9>$GZOkBNmfhP-TZH|K-e@;>#4{^w(`9Ay-GK;|5bR173hM_z*DPc*qaY
zq6Gdix0n=f!WM~7cMf9Ljc{H7p2ca^u!g*1yJY{IhilX(^(7AXKlnWdG-VmDwBM#a
zv0FfhRQO(3?nQ{@eAYn=tG7i<pGrwT?P<uA@tje_GVM<yyCmL`(E+?8%RGfb<BMAn
zkCN>IBM!r!``uZ_uQ&%?1haZbn{IFjCiB*rZ}{rt)iGYfb(x=A(4nD{38Gbx`WEO3
zlHsu?X}4nY$!#mBm%`At;xf%_GVWsYnC&eD4Nqn&X+96-r>Jk9VeVC_5U*DK5vXg%
zGGp;zw-ZuDvR;WI7^}$Fl9HH%jFG6d0|zX0o94%+v(y#>rrUdL@2D%<{V?i`PZG9$
zNTJ7wpFeAWpv{b4Ma`tDHN<?%yKB${>oAr0*ZWP{(&8w*_N>hY3Ot`eJuZ5eW0=mp
za@6eE#q9`PH5#cX26cr=H*!TM{mQ<|@ux0278j$;;P|R?gro^$m@fw4LFzt*e{L^b
zvaI)$#-+_&|8pe$ZmC+@5gHt?U7Jdo!YEAsxcvngeezj=5?~DSGW(s7r4_}|KWv!6
zaN`>~hxQJIba+i~GBLs=NVn{LVXt-8pW|}J;DMZ4>9kmeWn~Fwq2`)FeU{j$yhWGn
z$Aa)=k6{e^q<;*~b#nc8_S$d<P|bP*uH+j1caR{&mHkoyqCT1iadW}d2$%>J#Y~;+
zOq_JTtR+pUUPNs}WfPFv7wa@$3{&?yomZgnlm0`ejfLDJ`wP<O;(E*3Q5Qx>)Bx11
z(535w8fU9v1w0C&nF6V*kS9W&UFg_UpAH$j8uce{mOOXWe82YZ5$#HPY5oAEAFh;+
zZfv*Hv!(7@9m~;opFiQ}lopta?{laX^=5?IO}k)=rCpiRrU^CO!{Oa8(_P%RVjBQ+
z?;UoBP6w%#V+qu)=GnsOaN#u9w0fkM1E|aN9`o)8r|tHzQYysEH=%cWKx;3lsc1;l
zc4e|$t_t$dxV*RHYe>1iXWk@h0mG4yWbcK_(wvw%8$AiZuCoE*-Vwh72)$cdz!}A~
z=b~k}CMTWkCIL{r9tdaDx|&e}lO}F#u8^NHJa;_YIyR4hBW4Yts<;AzHW-*SXE*10
zF6_3`Ie5T!s@M%vx^&IWT+dj85>8R(5^VqRkAG%=$TZ}OldAF)w;`7B0s6<HsG;Bb
zVQ2+b8ah{k`B_Temu=S4vu&lKi0t+}w@|mAb^hh=2Wr|ZJ88X9_yCciUs@^Py?{Mx
z)EeKX=#hBNE2)aRLkL=th~NEo{lmq{6hPbaCYAI#T9BS!NfD_w7{+;BIt-d_N;#3g
zt8KqqERE~aqyE-=pPNWt=tx*v47Bs_X64Fddt2_XBFn4EwKl{;*Ik^d8NPYvjh!3K
zM(~CC=-C{i#rb9Z@ZAnkXqaR;N1=;R-|AOa@2VZfM7s{r%N(FGS>nbSn5gUo_WH+)
zHT2{VUC6E6vA~Wl40u%ew!yMc_}r)T(;|Kf@Y%4k*E{bxuFH;2^P3TBuC$lAftlY}
zpx_lT>ZQ}KEzu+;^+6$7?wYxuH~irR_ap`jux8H;kVhP<WF7RRQeCAtjAUFbc+4n@
zc%G^6F%!@O6OHk4Wayf=yy>N~N}KKk4FGmdlTa${u147MMWapph`s87Mrn<t72^@y
zIVY>>o{WF$3m^gvsKEp7Rl4REu1FIi+B%n~xB%<<?9%PvI-OP#aD33osvXa6r=ZeU
z7HiemwH-p`Km--~z$v+jkLQ{s`96%%&}vzfz~B%UUZ8W6?pICH6D}lnC)2^b$Q-1C
z-lr@<w+FRd)nJRJ-yEiMT#aKno*1=Vsy;p0So7px#Vl_FBbg!EezAvt8Q%rJ0uHb`
z_GL;vP`o(Tn8$bIqpWie6LSI0U`ZU(OFyc6@Gb?QP!`VtFmX?2&$$qES)p!=u>SwC
za(cLvMD;un9q{vAuX*&z?X+drt5|;?qS|@KdYV#0<OqbDzT*$k98fT~VlI02A(uPK
z3(k3lse3v**}*Ax{SyLY%@>>YMLp>_XeMyN^rO4cLhy=CrhQ>NC@pS$ljSAnsd{Ni
zo}rTyh1|CW3Yzv?)nj9q_V(oxe}DC+tK>kjh+NjA<OyMNOo6gcg%s_w)5KZ77cJ^<
zd|k}(CZFN|JErX}pQYY0UG9|6Xvbc-as$MKqOcBi#*E^T)=~<a4H_Q8Zs9Iqpq1wB
zJiy(rCfJVoJw~j(ciBJ5oipGl`8g?H2o-U84aYg?HevN27ybZ|jTA>$U{69=Q_Y2g
zQ}khG|AC4FRtvm|0bnt}0n&;h)Ah5=$bzS3S_)QAP8D<C)b<Sj?RJ1))>powQ|vM-
zULa;iQaH~Cq+DTn&wJsW=|&UJka#zAT!D`r7N%jhkj3(HrHy}siuz0$oYw^01<xK5
z?Xq7^W<aa3-QysG$lP{vPw>o;I|dE~sZqpC@$1?kdR&CxuPp7%#M0*Yfs9qyezb|#
zQzZS5ykfJWg6F4woW!h+7VkDtsTUeJJJg>2CCiKs=;y(v_4d=|qrTdrDmB4b=EL1|
zVM+o7?Ga@ap--tf&bUk+gk3K$LRv03@jjS%t@3K%P0@gJp!3g&oUdwW83GW)+ssR7
zSbXc>m$U$k(s_RAcH9@3ReT2qrPc+NSs^K49t$_bkPTn|{cs?O2}Yr9>qadQiFiQR
zc3Xe&>IvbDF`>%vf$sqLOH+B@Ym9^45%8`ve6Aug@;1t$K^Z{w8PX8=+6R`Ot_S!M
zE_#Zdh>7EyY-$F=j_;?z4}n2bj)r>epMkDFwIpTRM1b&^ofb@RQwuR6$OH5FsMrH4
z9E#2LmT_kh#<@T-KTz8z0b>t$yxth!u?H0d^NSjM0#c*qe%9p~4si6RkA7p?FP07S
zWhHt_c(O6fcAv3|v6=(G17xUTUxVE*w|;}HpdZOpP;dR3=h@gP?wnikCLjhklp(!|
zkKzb&2^`0Nx`g6JUVN>9d&|}$z7<=|W6aWz7eWd+$cJI9P5VIU%wLqOz%QfCJ@J?2
zXZFlboNJ9DCp!ue=fa7Yf@ed{!F27@5(?x;sOv0h)Q=B}sg}&|wRZ&O3*?+7vm6}^
z8Eb4UCKBKaN~ifof3BupMpbtBbTM)hl+)El)<#NRuT{)t<4OPPOH7=;qo!m#!SAxd
z9R>b)aZ6$PitX94{!ec}v{8}o2~@FfLT^T*%e+_A-8jUJsXL^xKner?mV?H!u+g{3
z8NnIWY}V>U?wqiMzlL#RPV=9il&W3?w{7SE30fM5){zh_npYWo({)p}CaW%G)zD5z
zV>d=G5`$CIXQ#6SDjtQZCdQfj4!{)B@fzy06SC?B7v5;3@G7`izesZL6By<=6oR6W
z0EKXFu17W+h^3fvCjD>b7Nne)5T|`3ii&odl%TzluZ@O*%Afe#8L>%=6TwMj%Thji
zOFvrp!^OC<tXWnXkKg_pSU1V<Tq5mcR=x{#Lmo|<IKU9w8<*{Q+Ao$eAXh^Yv!}HH
z%2z@^qdQ&C!(SDYj^=T}&qYd?TL#|bb{)-F(vnQcwp{FVpoh+h^Me26l`jhiVZ3vF
zBrlKav+kLk(ivd36lUU_?9kf{F?a}#26O`(nP;8Y!(z<tKIx<oK5*6*opI6DI4`iH
zR6K-Ly8U3&dX)SwfX~r<)PAe?i;Jo(X{Z2FdroXouy)aBPaS9a9c`fB^FWk<;0(-}
z@c<rZg*!Z_=>YM;nJ}@8Yr$+!?dZ|x=!9*#GV**u$;qv#F@&31IYM)sEw5+)`XbDS
z7zcH7%K>=ST!X@6Y;;9Rr>kZzqJqZOk1)4QDi+B{pk9Nf0<^1<L<H3Ztct0_M{S#b
z;f_iCmch!(Pv<4;Q9M3a@U1gZ8TJs|pIM3MsPKmFLWw`3>?X<xh!@kyZ#rJ)s2RqP
z`KHs}bSyjkb!T+;dOz2C?f~)<-D#_ci&&-$-KaKcBw7HsuXI^ODE1T#cUdoew&!9Y
z1V#?HXeP{{E@^<hh^P$HF1j<@Q|B_>WMhkGlH)Qt`LHT2g3-tuiB{4-iX2M<+QiuS
zodnbBs4eRF|2JU;cTjedjlkm$_eA}EZ9v!tG65%lo>pMx(9UKGhV?g*l6Pdt;?W!`
zyl^Ij<QgjwK{5s7`4_J&zhEe^i$;zK9(&I-Jc!0&`^1J^h-gcxP>5CN>Fkw)LF}AH
z5xYSP{?qi`QBtCS&KPzvQAT*0A&&<6jL1O-`2aO+_K1#s@&dO@iC@nwCUu!%9=7gq
z24Wp+(-hM+G<~%n#Njf8IqmI`hZO*0o{IALK2B}-!?rFbIdp><L&f#j+g+87iNg_h
z6}eupGf#TsX9Pa+ckR3WPlATiMW)=1mw`bU5_8-JmIgr=vU@hF`kf!E+c1Fh=RA4r
zryS^!={+&5fecA4{4AldnWh|7cv3#n$tWUvm4aBpJeZA50LbJve7&TD`lp(ZrZp!8
zl&vFRtvCRER2j#yRNLRQ^SusPEQ};Q7SXYDKR{EPp&1w4n5ylw8W#CIM-Bp{pa><w
z2vX!oi%&sYtrTr+_Az70aEG=NOlQu&0|@c-(|C++(SE|?Jtb%v^qMcv8W^K^kklO<
zYc_-2is`ysHV+ZkZ3U9$YeSkN!ZwL$r}wc7-e1imt9&rPRKfS-*9nHBHhal}zlkz3
zY?3=VvC*lxLn(Cve;IfwpF0CQ1m2;72&MP<nVeV00p~%MU;d8$@JP4$emkqbV<<Se
z>JHlQU~&vc<x)`@3T~1%K!xrrHfbjPKAa$Qj)VcA=LNzBB+?4lDZ*X_V;`Bu+HbCn
zx-NsGl2uI~W+VpQbhpkPia<zJke6k|da5KF&zVOG1|@4cIf{HXgXMS0$#^H#2m+oI
zw<zn8_eDm{i{XGx7wymJi|Up)F@HJYfMOw02WE(&ts6q}r(5#-ect}{Yn9wtMD{5C
zl9l;v{qI|yQz{=EJ!lu8M4uUI*hIDGW6h2{4Eo!sC#-OBuLjtsG()=dd=`2Q$_|7Q
zvP6~NsIhGCv$lnET_Qni@o`AJ3V(KUrTdSU#tL45ER%UJjRchvWBYX3*vNONDUSdX
zsVxXzG3rK&06E#51@t6ELn_V0VPQJG3b25K_>oLIt=~egYaf(Gp}I$_I54jXhP4t<
z%~Ib_>Y?@L%M<<Wu56Gn?r|}yuFnzYdQ=>75-H29MPM6SG65TD!9hSQNzk%`f%)4A
zjjD1Z*<*dL^kLaDz9-?24%T6(1b-mZ;eN0)C9dJd-}ud5Gj=V^N4mDy;#AdLpVD@s
z1{Eg-VNW;%nI2y|M%Ii=Hs76zj20-TI?@XA0z6^KH(B&#dz*=7=hlZKYD&e%CsdMx
zx5-zc*O!oA^(J#6yA{byu6S2d<Ur#?mSccevo3s7^mK#0$=P32Gu>L;;rSJ*6f2Em
zC3fkqEa&Xi+T^&3hK9gqsE(q#l5OWEAU0iu+Vs=*)-9?Pzeoo)0R}VY#A&*Ejnp)C
znn8X+!}mIz=LdDazKS3}GUcIT6jA6GEO~Zsmr4RMwA$)2^4(m`O886?XtRSeXBr1-
zPAEbGR_EKm2eZ2U<zxifvOJvVp;9za-vIRj!&*x~(u!k^b#PGHG^(bY)I+|5e2?=Z
z%;*6eCYLsOQdqd|$*>oL)55dl1qkj!VfOBkRHql0+8hHw+=i<FxuxxwlBfw*y<YnG
zJPcCmyNfQmhd?TZ^4e?k3oz^v+quhgy-!-K?5Ij4APq=v>sdSsE=qc}L`<c!X!&b|
z6dS7Kz(B~l$49WGhtVU!FH3Ml&b_}T;y!wF_H(X&hL?|t&5DK0GU?y8Lro(xJKgAk
z&-2-X%v%+xPWz|u_GHNKLOQYk3T*`yIuqenM7EB_2kE0VrtXg@!936ny^bAT<p|Jg
zkuz+rZa*Q~*tast=4Dahl(mLN0M2Gp2aBLw%L*JJRNtGI#sLH?<~toNN^%ME_M#X#
zha;?&3llz5!NdSQ)u<Bw|G8M0NSqoB6&ocOy>fVBE;Y_Y$Im=AfU$!zO2QH-8Vk}h
zmw?ZT>P!8mg&@gf;$w!|uhu@|WqPEV>Ujt~2PxJTAUdw1YA=^ydJU#Y=|0G0-sbT%
z<@Vwm(3vYF2#TNnueh`i^rEh^eCujV6a#aGaqG%$XIeE0wKuZ-%e98Y2^+Oe>ygnd
z$W!QbWU(zQp1zuknXe_40j0V4y=81MT?UBO=1)82%STzL4fTia3OV-w`8xr&<tFHt
z;b%M79inY_`O3F~Y9$DS)jdy6M8Wm-j|I8PKp{AXZFzlfyGmmuj^D86Wy~dzTAVIe
zRxo!Op{cXe7Ddc@)lgC2%Q}_8#swM3!eqN!C%nw6v>+lQxuN}W56H3Cn)&iQ=LQ@%
zTAQlH=H9HMhUYb}LUmL_7!$ODmorW0yvC{7{Vb$QX;DqC{yme9uMfYT#sBCLP&8vN
z(TBTXhs=-#!;7MiXbK&JBRBlccPm%IEjoA4P<{v)-Km28$6No!U+Xs0V9uVsRrmgX
z9GzRlI<a?|T4mIA<iT`8&(mmBrvF7!9|-)q_eKTX2ptnI)6Xz+_TC?LJBMzIM=05I
znQPLpw{V-okr(UY9?t?q2e4<F66#W#e|`Ulz6!=J&TU^j{FdQ2P?-|Qo6q6FU1BHp
zDG>*Mi-LjoGQLrXnVGzB%b<qG>npxQ@YZxZ*B?Ik>gAZHr9ua9P-<0Y$AOqJDq+I*
zyh=?1cxdIz5uMag0|{7#`z_xM(jJ<>#sPAo2(S}DY%?GweIZ$w$m@Sjtu4*vKeJJY
z$Q2+t2=B_Zlr9d%^K0`pGiTWQT%mv>?M8!Cl&3<8mX@#M-h=~!erGvEr@*>h{Fjx-
z=}|qAjJ+oC_n<cwy5(ppoaBcMyRW8T60+N$BJBqul+Vv2xtrRNAflt^+2oiDhfP`)
zPu3+=#2lVovrvKjB1Qhcdrt(;dxNhq(M9XEt&>nD1FlLaG(+_Nrg_JcV>699_m~%>
zuq!J|_J4^-!Tm{fLO_PrFH=^kN-4ka3oXo|Uc8zd=28Pg?3Wq{CArj{8CN)6h6^CZ
z)UC7&5CYJvz93eJj$A8wUWU6(*=R&yAeed8P2QXl<xy^e!OObhx8Y4pRsM+V2DFQ@
z%A%wYAv<{ceO|Os=UY(k8#Q_n8G6Wr#n+M1bF=E?GO2rw4j+@64N5^^lOwZoENyAF
zS`aWVL^*2VQ-%tn#IO-O^bzYTag>A2C@z;hL6>N5vsAk>4)l=lifP;x6!JsM*|eq1
zR9Yrv{LxSeI3b2?oy37x1J1t!hVGHoIR~snqA%;&A-2XDfB*gvw4C~`N7lJww;zRx
z=cV_fuQoPCVjazi8PuB70!cmF6yX3KRUsxXTEiVj*wX-Q=R>}LSoG-hl~{3o<i^4%
zCaz1kc0CrNt3tAk%_s5xvnQ*>^AQyk;Ih`r@D}t6e_d7PDd9JsZne?Wsf0)^&hu%3
z?lL=Mk^cME^a3z?2AVfnv+}^endX~BgO5cxf%bc)d#<YCNDWEZFV*I8ufu@{wEi=V
zfb6Xb(w^8pqgIS6$Md<OMmvLBttSDedYqmDX@nYg`Ylk$5pAJ(!pR(WNf*R_!hk^@
zOYHXZ?%OuD2bZ5Dajx(=ed38w0qiDIkpkz>gKZZP-BA(imcf9Nqm*kv3E@wUmk@D-
zeA553C!&dD__i{v&P7sw=htK1U+{57&Z%5x+GAsgmy?9A%O)aFJv~gvx%KGzjBXU4
z5+13#1*xwHrA3NgJ4ng9I_DAkK?_;DklQD(KuwCN?fik;lNknK5O}n>uQG#BR_TZv
zR=8ZJA1<oK8V<V;!QzY)0KS~=J0n686C+m1Y#_ZHSw9W+<&lScXyuC$I!U(1h7;|c
z9nZa70Mdso*A$t+^5^wLWThg)<GL$X=lAT6^vLYy>6sj=$sE2tT)|NQ(KJ{DTF#jn
z6hTn1VR<NGvU}Dol&wQ9mhW)ca3{I#yjW~ZONgLnG%nrlN#J-tg~T=&n^iZ%ZCk5;
zf+?CtNBCzXZ=X_lXcktAivp}`%{p!8JBYR*1je!n^;^!RjNiabw)3=;Cf{%Lm!2VR
zS!j#8x{HzbR;%2NlOqL7Ly%CzM3oV1*t=XNts_!uNo)W*tbTvCIxygO!m>@JoM)zj
zzJ!?92sV@^uwAgZNGd$}rSMl-@12Gs-?QXsc8QnUz)+!j6pL<QYMxZj52a88H?25R
z={i+M8)k(gR~p3@l(H>nk%=^@5?4#`A8VsL%+;^o2w-et1b<?&-qWm0{@qIU7{uzZ
zyVKi4`}>gJG6A<jQ)mp-bM?>3ZomC%)j17C7f^yXlY|BZ8U~eLdC1HGlm9QGgcC1s
z@eAbK0Ak2G;AyrI#St`OQ2xXi$=eqQ94cJyirsrP1HdqPWhn_SL^D7s!5#lJ><E*g
z2Q7Pexq{(&_nwtaH(#+@z~#Hs$ZqTJ?`L$au(*3Bb^lO~Xb5C+f6~rM*hS3?0BU#w
z+;6}(Tv)_ZuMGhy`L{&Vce~ZwHE#nAi3Qy|aBB6xu*Z^=D+YZH6+f;2!-Q+Y5Tadk
z5^^t~7(FX%>i*WvE(%d*b(+nR0F*Fc87>{lQKC4dRF?dtr^4y8*4T9bv74mt(L!$t
z-@O(Ce17g_mVs+BP(P{1Ti!leV3u~J9WT+G-Rx2r(Pl_&!U<Whgn=CKDKU9Q?0@1c
z`lBq%jmeLqIs75(nKTFCtRV+ims)U^(xLV2yk4_D4sj-wW*jCZ*jXOHWq+6bEmp}W
z*uVv-$1H3rJAh*+0acb4OHyJ}G9!?$B(Cv4GEpyQa=NBH{f$7dzRC1S8B1$&OA*61
zP0DJ};H}V(DrKvk^m&x5xC7xF_i!$o?!?~>V<`|5l@#iW%+(G*4hl`b<r;%D;?k)K
zG}`!Ilq5MZ_PpV|8K5>V;W;7RBCCG@QpFP`f^%Q738GMGwlrR$1WTyS!>i^o1?U8W
zt=Rn|=&}u67;X8=(ZyX<)@t=I<xA)q-oFsw7UM9`As`Qe7MVz<`YSN3h{AIA8?{Ql
zQRNY5=LT9WC(QY%5v>RqMajmd$(b7c<8G$Iaxi%($!;kFDJ5(KwgE%V87tpIphY`e
z40XYO>F;f42)_e~r=CWSe*DZ?Y$KJL7-0VrqJ8*b_!v4UK4rnnr&J>{O#6#`HxU5#
zvuT<ViU3rjkB~83xNqD8C|SC2g;*+E9x2ZB8~I*%$9atG;~J5>&xe%_l#mZ-lp8CE
z02x^jT<_!cYqe5gbnC<3AEsg#-cUO}%zUV2YjqL^YTZF6EP*8(#kZ4-WW}}cs;3G+
zUwCX^Qm`8I6_9=)Qz_^3uA7R6(TAy-UNWyel`~xJn4L(laQnltsfk(b`>OiX;}8`(
zdqg6Ar;8l9ytJWd1efwUx391|3BalcU?k{=&b=}@uU!ni{7r=c?H2e(ap7o9OQk@9
z8ab5P%gf#0=9iBGw_Dx&+H6W%Nj_{zl%w&u9rwK`WD9I}K^W(5*{+3-TZg$GX4`Sd
ze?{lWXfov>+BQSSzx`;;&4Wl%QBIS)wBJ!8pNj-GESrb;Z812@HnGrk^tq%2tA}+Q
z?b=ujUxlgD^Mvq92Y*b+S*BzfH(*>@co%8Qdx&fr8iw=`aQ%%twK>IP-jQQ%#Qs%^
zsPJ3lYW#_1v3FDNgve8VFO<_*>lzQlI>z{5@B!VG-w_w;Si<EQuh4I`sQ0rncV5rG
zMS=B{XJLb>0B2}<0UuG+vE6j1>99Ojs%0#Fis5s&4XlGU?_qzlPEW@DtMMIAjQ6nC
z56^D-#Ei>s*k#3tst57st=(=cM0NTgmtQ{bqFG)&Y;&rk;1gKXIeceZO5LxtzOL)&
zc^E~DAB;^KXd30n=l6MUKK3JVzXA%(^^Qe0s{H%lV8UqatqBd*zhY(L?XJIW0Ppk|
z^t0s}E1l_B*G;-=mY}S7l&j?$7G0?keKoJERyS&*cpo&{f-dyy$TjGG=X_Do+8GpI
zEpIMWHjFiN!NFh7jRix}*48UL1z98}TvX$06v21}B0{Pn8E!(4HzLAun|#?Fp2|mD
zA$(>Nf*_zr%IsJ&&mA)*&Y;x~%FKc%kA3_Ysf>F|TK|P^_Z?2{M#go?w-3WF8N(dm
z;blkRI{MB(m&vV?YzUlfoh#tyh5O2L#U>nqSf;HTBH%l}!WEEKmS<J{1H5rdbq2v)
z6}gdrmA;MPL)L0;SxZ|iU60!84jUw^SViZyP`&P0J!G<C@*UA$@fV4s?5D`cfgcA3
z(kPQ}L{!|{Jsyy&;~&jS_lJ;KRnQM^45WRCmn|e;Ebe7oWS2I%U*Ncu4m!tE0(B&W
zYE14B8HrF4MFk7ilzbf;GNHV0^u}KA0ugPQR4LiSr(vHb;VF6*>)oDNeGNbSj0P1&
z?d9$YMIf(iT5QMmB`<bgZ<LB3c|d)0iG{)>Y~N$HY*Ls&e^@C7JJ?sp<xDk28>KE_
zViB8@2dhQlEqS8Av#bXT3qzT3WPvI+oLvN!{}$nP4)>0IqLZzrhkstNaFfCrW4kAK
z%}hB<@nioI7>+tjOH7J(J#BTPoQeYfLlN3+rEzm*oD8;o+}1E>A=0N0RV-3PFdHBP
z9XEWq(xua~ci|ve%L40)h9f%DD|`ul13^$g?Sx}{s|f||xG%mw3)k02^;cPg8vD{s
zDBs~Trk$~f%gHIgLFauW0ik;$K1THV91jb#2=qx@t|&!qy)oTU958;GzHL<jf;gWr
z#=X#($K>~Z67!Nzt}?8ROmbshdPP4&NeT=`Bl!Ii<GZA7En_Xk%*)woeRURPcxI05
z9X1>#1(&Y_<bElNOH5GrdH>3A`8^mG5lUbRlE4FaW!1~OYC|mxkeXIRXUf@Retl3n
zG9Zm0E!H;hA2wy*o=5Fj4^r3t|Lr}xRe$?lRg!GxS+YKvz$yTtoysM*GMD$XC|Nu>
z*2iDc;!DP3Uu^AbKp1mWi)V^rI-4j5Q`9Y}NE{f+9XS>TtT`6XX8MG8B~0cN<b5SQ
zUI{@jS3vQx*?N*L(fN0G`ISwe$V9MS=Pq`0$Z_0R#`B-IfmgpnpJTF3JaU^+3Xdx%
zo3DL%*0#%IGva|h7*{`IU!74UYIdn|TsuHb37mN5RZs*?0;@Tr`-oxDNjp2>KW<XI
zFoeGv{#6DA`6s+c{3W4jJ)*ERTB@dT%xpN(lp5=mW$2ma$-6sJoq>f$pb$LG8#R*I
zk{;i@!hyjDyshqD#kvh5<o<CD<|9s#_mqY=JS$U9hF*@^7<6K=G9ex}=g<V$k;hSe
z_-@i$%II!V(uGKej>$v9(z)U|kLu;!2IQg><pZl;O7uP1?dWn*v1xT3A#xbeq{H@b
znycOAz&@Bh5FIfbp<9jATY6YKLq3Wo!DRhNP4C<;LIOIZw}K?ov=9VZH`aBwvI(EQ
zg?%slLEsZV<---j%HDw?s`ldak}Hqks;-J^d;5v70Zm)xr>(r;RvblzZ;ftOC80jB
zQzmHjD)-<S2h3EQkV3$I!}s0)dya1yh^FwbBS1;(U<}LPUEZ?U%p~S8a+h7spI&p`
z<|#~OZa<a)+JTY@2jdXTUu8~C$)bGZX@37W3zj8A#Vilh?WumhZTT8Vq)W;1DGf<B
zy0U;3Z7NyB?1>{)``xU$OM_Km3v2&hU{^A{dF-0RVl(^n{eQhKnJ+zSX%W}-=2TUL
zLrFEEBdAWhpx$!(mE<s{0B!mGfjMd%v}wHZwmVfc!zlG-Xml;XrNqk_N-8PGF83=p
z>36)~;_TkPj6J;~0Lzq4vn4NYP?F3c0}detQ%=!d+r9j81IcGC`AoEbkAeotYph!M
z;J(B1oREIUh0mgH*##TYe3R$&BfeLWu!G*6viYxC;Qi@K-4Ls5WLzuo-cI`jFcGY?
zO6Y1hi>!|sCk((vW4hN7Q3x}5EP#Eek*cF$3FLnQ)M7sCL}1&vF}p}XCi*hT3_m3v
z#*Z-ggmvDlo9rE?Mk3ZJd~QP%^b9~cT?V=6M=3^eg@C@5$b+bx`}k{l+<W)upE3Tz
znnvDTsbS`Pz_la_v|cMg#bSS3>|&vC6>ln<0aJkd2tV~O?ncrEuB=KSV?%ID(E@)x
z^7q`SXE_g4d}X#m(-s7F{@V=}NCIPf_UT;c+hzWs5V<`u??ju1qjyFN0RQhjRFk!M
zVZR0ShXG~`vuR3%kHqH(<N8!P04qS$zZ&7Q&Jc%kOuWIh<5V{NLDU+6T6=vbZmY`N
zOv?h~FiF60UX;KmQ8PMNiMY1MXnGtsPL8e8#EDPXB5pGGtxTFB#h6<Tu~V`{51$`W
z=h9+s=dHUwX~sS&FP~aE$cE36nLS@cK6_V*)^v4>gP?_kAy)?Yi=~VXc;1Z<rt)lG
zB~lZm+4H-w5(73SvWjfdB6k42NJxnAzFAqQQD2F^$cq(?^2VJieF&g>Ky=ENe(rH^
z1RRgfHSclIlMSV?BxPaBqHnJ#%6pH>2*~zBOL{#3NjTHjP%Va?rtGo?s8jV*W(#4M
zgcb|E3T1bh1l!{CIauVTiIbq9RvTGTcmJy=%rI_&sRMU)9ytV7!hL|7XN>BT-ns?~
zW*6XG!~eq=xi6c5L9`!dbUn&n0V&+<yoLb-$7j@W!dWfb+c^a!pB-z`c{%G$noDmc
zJAe;Tfd&t%YAUb1q;_@f>V^pto{U9TE2ygm!5C=Bmd;(^aR}8G#e26#)V3{uu&^E_
zeKn`HwZ+Vy1qJQ^%Qtklrtf;$z2PJGQe>_&ITba&d0rCaF~H-fz^#?Ha5i6^k^VQr
zBoNH6*g~rY=Ew2_?T)nykK0jaoVTLshhz_f>BD=aQM@+`s%VQ|7uq=(J%5f|Vx}I@
z?4v{ci_?5<!(v%si#pk}`cXNEAP>(Y^3NAB7AlJK;N7lFo94iAk04RBkI8#=Y-i}|
zt+U`(b-9XxlNWVwH$Mx>FhkA`T|E^`2g(53e;t=f`@XO3SG*c32VXDKkl`hiZ8xN+
zec7Y;3@AQ8LXGOQp$mYf2>W+Xyh7UrtY+4`5;`h3^elSlEV?NpJ_b=c>T$TA=BNg3
zrgM^47J`H<iy(KA8oW`E#ld{8$!nJD&<$MQJZugz*8lHg?Ufu(xXY8Wt{rQ9jBoJ1
zGlnX_^hSx|t1X+AcuV|owSu-ToKnICv=)9)x}^E|i!;B9oS=SnfH_EFThBjZ_b&ys
z9sAHus~}xL_z**X_s6X=ZyIh`Q5q2_gsZ!0t9(+!C~VNMbxNJ)w`8U9S(@lBQ|T2E
z*!D)!weroMl_%?TC2?5v>IcKB<(ounGeLqq_{DA37J?4dy4?BPyV$B+(#`QO8Jm$E
zg6#b&a71w0@nc9iHJmZNt*2zUD#~6hU@we-)o*VOZutn#UlYqHwEy9-cU0>`^=Ex|
z!)lNnIk5N|%7N>_Pn(E^*l<)MAN}-PQ(RNE(uZA7;dsWIAcLU9soCppNq+zEPcUN1
z#=cG62i&PQs>RVJ1y4bVFgVM{IS5M?E9U_G#-4oTK8@N;czlg~%JNl1@*I1rWrA#3
zn6rV_Obl&~@1QytXpnN2EI1{5!sznCaObx@O8kmdynIF6)};v{WK66d`lgX*7~#{6
zu6=6M+sy&wo?%bJd6WpV0;EE?y;vUzYAv=7flU6`J!8y5{CtE`2ZCoHX%FH<<3cRC
z>%9a<5Ir3Jb8=*gp2m>b`-QLlO#m9OBlJQ8!u^#xlmud(lEnugU|)DmTr%wjn>U!r
z_(#)Sy6pq+Is&EOI+g+bvGB>ZDRa3oY<ZUI;ZZppimvFX1K?M@YfG64j->K-7|6u$
zPX<b#?GTETTYE?#RMGieL?eR!L-=4e0%DFQe@D~GNSK>G-lUmoFA9&vawT~(sdY_y
z@IBJ*i9+!`$ihoqoD#>PZ-YdlxWW1NuqDI0ZUJ~wl^CYZSTIL^A0hHfi_`jM<pIXI
zlC6d|<u&<{DRu@sv1HJSw@}^2{JwsK=i|`iCql(kWR7wSEP$WlJDDQ0_A1sT4&Z@T
zbex_%5!sBX91lV&i7`B}Sb=>iirIjt)U=6^fv}Z}el>ZNGwOQ><o=Qs{dq?%VLg@}
zs3_G^SWSe#^oAMM6lq#h*W@CmY^jL}hax)~{&yd`DHXm#<GRe<W3>aU(=lE8@A=m!
zy`iF~mAO^I<DzZmCerzyE1Mp8SPansi)7MA0h?-{FGBe)Sia{|#2TSU<&T)~-Y`94
z0zl%H#|lZylW5AXN+UF_r=JRs)OEWg;JuH_tWXc?HNJ@0G}9B;ZCgQS19z<Jd0SVp
zRtuFRdoo~sY8C_j{nZ%j0(&**t7B>!#f|83Z-VoRvYp%;)%NO8^3?^)a%E*JT#4OA
zV&ILpq%q4y?0><beu98efD9!1Z_(gOW)`y9W^!M$DQl|sS>alYhDR+`RQ&Mf+toO3
z+b!Eei0w=yrqW0|h}hdtwj8h%hv|qcynvl!`p5B^Q)X!o5n4z5LKqU6MIF<|^n2LB
z7wL)itU9!AV6b8ybJV*-NPuP|0tp^{@{l~22p!Fk&r>MM%Ghs&na#hQM9}x1%{!w_
zL-dbt2+{lJmQRm0O+An*nf+h~L$y<MFewVw-4z=HyicpK({wzIxXO*w<1xc#h7--s
zL4KX*Lbz*5R)j@PHTDEo{0SokaVs{wX}lJwR@$I!{9+%)lxInlQS-?cz087P3}<B)
zC*yKMBGQ{`^xt=S*sDpoxuuJt|1j2tFonF?rS@cdD>XtGVzTPT^VINsFQFanP|foD
zOSf1qj6$+y4@bTg3U~oy-wVHyHU+e_G0Bo(F{-M6T^u_>G%!Np3AN6QXrUXZj{h62
zc-^>vUBEmbBE(OdrNy+KVb3dH;*Do>Q6q%P$y`I@jUPif)3~2TjX2h9lFyZ|Fp_eh
zyD2T4P`j+W5Zz|*xm}q^gkVUNUG*#SU-@-z<=lI}IVtJ&n_s=PL_g_7VS)M6N0nf8
zyTaDLm_(+|_lm|P0!9Q3d!w2FbI%~?UYRbyoAXWL@aV>BrshiID0%yeLc0c+TBoq#
zM-d*es(>aYBHMkz^=~cyk<mzCtYcz#Q;reAXxUWUR%}F04c$-l-huxm4S~+J<vG#I
z2d!BxRnS#-Z(-y$(ESrqhC<kBh^#{mo}}X%Y<KGC@oqz+B*wOnPA@{r{Ldc`sW9Vk
z#$`RD(Mvlv=<nL<BY00v1k*0@oQcvoTl{vlKn{QT8GukMPfjF{sfFFY7l9!`@4RV;
z2Wt=Tg!EU#*^UN{<$``DIP&`YLHoSi>6F{}^|&eo2+6e%z*ai;_*c0X4p>^B44LTs
zU#Dcl_v^YNcX9ER5ZhrEsY(se{Un6DQfAJ$kl?C%7=0%0(D3?fJ*@z!%yKvm)Hbgk
ziY-=JAm8inM=T5*0GsLsM09pT;fp19C0hH7PdN`pr4-N3v+j1@{l|`xPo9#uyFyXU
z8LN_}L=>Qs?zZ8^4Uj-3)YuzLSYq}(OlY|nFx%66b2KC@K}|Dlkfq-T_wY>gzc*+Q
zT2nvIEg7|uav!$LW|FkOu6BSL-!&-P`d<vE$Dt&jf2Hmi3?wVB5hcC~uGW{zXvXqp
z;$i96%@6T5g>q&yY5l6g-5g^JOSq38bLBZDLs2BL=MGb-`-v5v)Mc=4jJEQLwSm#f
zZ#f5|UnU}w>;mqtV6q?aPryV16(?Bd?4PaQ*4mCGplN>LYhWrDpb)|kDJ=4+e$?ui
zk~1SES25tse$_r5(Lmmy>S|dGudM}~q?t)`>@i(&TK5!N$?>WP5BibG`%2cse(7+!
zyNyRJaLj!qW0b0@3YeI2KkXXi2FaBcrTx#pOp$SWLilr(G3Vs!=a)0>WnVQkZt?Rf
zNxkl7&^@)hI660Dht;E9^&|hS<#5tA`Ib%jRnAK@V56}dE?so&wemT`ihxu(RD+@5
z?7b&e8_)0p4uLh$RSt2*tHd+`i-a7SO5%cBinoZMrVB?)eQnX%_gD+np*KIeqS)f2
zA>kHKYB&uJZTE35iWBCtHU$KWqk?(t%3>eaNsKt)WJgN&Gdbtn06q~k8dG~T+}ZD}
zLB)z6$T#q}-wOr*D?jS#`>SGi%}dan!jY}K5J^utnBeCQI*o24a91M6Wl=C|x%wpO
zKPb%;U=)gD(dt%HsBpYvQQh2=vX22OL)|{!(;L<3GD^ojOM8RG2T##UM1<b%K4-JZ
zm46wrM=pgY`CgaTWaieS!i*hwPL~s3ugb#uqyORWoDa4VP*6*vis~}xCgeykPD(C2
zhFQ4G3$R&DSX)nCJZ5v&(ENQ!5&6HywguIK1pm@Y+6E9HsPxEd<-qBHET**C$350A
zMw!Kuk0Q-*Pb^Op6<RGE8x6G!Rt)-v-=<V-iV#?pD6<!}kWr@bo<|#9!}1Iq!T>@x
zua-DMzv2YuFv;kSiorAe9_0^XuoDW1TAL#67RkT)@VMO=4#pFa1q~?&>K|Qd_C40O
zp}gJC4<N3)sAHOLaBn#rGtrK%I#={m+M+mOxMAE*9Vj#(LDeq0+vVYP(5Q`U-GfUU
znVv2!meJH8Z+RsA+l7HgN8`b=BklBh=6~M;S`Jb}?RnW`^u1zjR89V?p0~=M-+C9(
zxF!2QD1lE)!O+9LZb>q)D{9e4Ow>Pl(+fDLKy(eSRHWYLyEOjOXycy&KqT1)d{^fl
zAxh6UIW3A7+f#6r%xSG6YQbTs)s_*xUs=a*x)@UNb=g7MproJoNBgH9gM9t|c?b##
z+n{O%Oy0x2gn9f3H`9=M=g{n00P9mAJL;8nASN4}h-qJv_`GZ8#oe%FIk%=|7>s;j
zLtq6?mN!91=#VXkQ4?QW=iW4z1mfD&)?19Gu(l!Jl!JZaFFQ}tSs=912$>r1!FNNA
zIX}W1!l=J0d_{%^8UoFzJNetp^A=VesE`)X*P5)8Ru-{m8Be;0Bs;M%QIGVXI{4=S
zuy_ubZQ3U*j1eZ|!y#Jbw6{loGb(*#k)<TCzxd29zJG^^Gp<vwE`y@*ZFO~hJu3p`
zK;?K}<@ms3zCR&f2)@2hvg#2_AshGh9$!77I&B96ei}*LGM3pPD7$Hvm&^njTePjR
zXc3tXbt?%4%AImwyp)D{li|_`azY2ipnjz2L={De1EwGv<;(nz(m;Y8>a+Hx*-HGT
z@+LjlwJzXPM^Qkkn-se#F8c_Awf+mbo~y(U59%OhLA}BCz25i9_3E*9&kJOlx(y^_
z#7t06o9o)4B5&>1dKiOQQ$yt2&zkQqvvB(cceoF_ej~U`sv4)8a@?SMl@z-V>R%Gn
z^R5GQz^8B8!$n1i&pZ=DMS?vc)2sg3-np(oyi>Dw(>PVBCin}nR+%kHkFx~(0bG|h
z+DeLI!}ODqk$bom(@@!^%$k)$i$NreA2=u5?UUh%XS>5Y=|^M3k1ugxHhsU@1ea#;
z_R+Q9+D#7Qp_UR$c=Exx$f{Mw*L-g!edT}@5BqiA@1Kh6+qNOwd1^GMFKlsgv42+(
z=-u#{LaB0hzFOuSev3^|NvXEUHytjxSznCVOTCJRQl5=<&Qg$H%{YIfQ<pYJ+%6Hd
zi(G>9!S>jf1cC~w>;8fBm4d2V&kx&Wiw+s<rRY=(3c1TEkv)geVj~#=>1n~yTy9OW
zAGz253OjRp@W*x)=au7g>iP&$N2#nskhg`3+Ep?y+?Ko&tT>XxNWT8}J`)V7)8ZM^
z3}3bzZ|Yu8gnf?A%*5L1GbV5P&|f>B+YlvOgnJnV7q%|<!)QZ+PEWDxwmj$cRFxLq
zZ{Tg4D!9IW&Rz_VF!Nf?sp2+Gte)@F)u_@%sNi00_zp*-hY_{)@0^h?3J|=S4BN_h
zzI?ub8%FnU;fzX4M}8ZIdgoO(yGM@go|3SIkv+X()JfEA&^@ic?1apAinpIwq?`B8
zA-QVbLWAh*U*~WX6yRGN!^1&CeMqr!hECB+^WKsgS;T_vYM(y%FUM41f;G2l(r|P(
zuod=kkqW7B5;vJ@0*=XnwzN%*eRm367vt^zUsN?w;;#uwg;wGwIdI8r&=ivb&2KjO
zVcSw-dO$-Rko|4qtA!Iv=;2lN*yC#FJU1*);k=tG$?{}VMr_w>9escsb6&W)vCWQE
z-VSu)yTo?PKeWsfpB16+3GH*N=CUEx)LNa;Joub)-*Tq!rjGQ_?bNDEabg)P>lozZ
ze{OMn2WUYt@gFfVXP+wi8*4htP<NqMWvgaZjl-x_<KHOTI2oWq{oL(n%D~|Gn4(Le
zUNNSGLhB=d{fQ0y@!UqiBP@l>!M$gTdHjz9teZd>g*3vJL1&{4|MfwXT_Fbmb#(dH
z2n>t)xKFCB2;RCaKF@sG#3jxuZ*Y$6_~)F$>O)a3f)TmR@EOiy#70x)6!5=_W0zPK
znIGi#hv%DG*Gb!xPeO{zb`R_F0;k~R^4aPc^!t1oogQtYNRlzI(zxz6s05T-({^y-
z;cXk~ygOlwwIt9#2tV~&k}=%1;-cIdLV<?RJlxa`%z-2Aqn|ZD*Z2WcViz|$Ree$;
zULxz-5Fl+9wjlD@JBfA33bO=-UhfkR3Qc?h{7JBLX+hZKT`v7C=LoKmZ|=#O`IV<g
zKL^Ovp2rw(qyHA#=04*~T?RWB0c`g^NuV1fpE^%Uc6E&)FiFkR#!Ej_C&<D)*idP(
zwNrvxXmP*1kMb3P$Cl0gy2{KOS2&b83u0C!f%bB+aq90=A6v#Wh2F88UwH?c>&7q$
zWzE1DxY2GNvZf)K`+Z~X;w4b`H6uDwT=JtPwv$qn=Dtk@#ZolF!Z0RNG!Bk4wF^-#
zTyH-3(Iyp%IcUb)k($ZVFDkubxUQi)W6WI#9WZYJfYx9;84)nAt%*F2gFh8#Sw-aG
z=Rxg<1hk8E>WP}GBY4Vk$4pP<>H+TTUn$o+R%>KVpa@i~bGZTB!o0r92HzJZyjT3n
z$^H0AzL3=24TuZ&tP=&`UsFGIT+;40II-y*QgHVlBrPMip%^d)l1$l1-|S?+ju`)a
zwM?bx@+Y-p2(g(zr|fppKnz|53P;0AAP*GVwsb?Z#VL0#14Az@Hka^Fp#O5ZmF+ap
zSYn7yUaC{-ker^cVc7@x=PcsbtI=3GEdtM%&II_FlNi~hX;V|~rfr5pW;xWaQbJ^G
zU)A}_i8lKPf0LqwRtrCKDRE^D$I8>8+umjwf!(g1!<`HRa~Ti*gTBZ7V)oy|%-7s$
zcP(GF&Jq2#m(S{NSXEA;bM;~#UQ^C3{H1y3GSJd@`aJTP<Y|ZI_A_gjh9$PgXR1#L
zx}H=&yoR=cpBYrjPnxzV8RUlmF_soQel^D`L+${de&<NJIBZ`pK_KeocIao5t`EN#
z({2w=E9VTnkjR~3eQBlrTTj!K^UNz`SSE*Wv`Bf`fi&99sYGwHx1lZB;nmW&(vf_j
z3jX-WF80P#?2!ss3~dZXMQ>8y${w{|bFjHq_3QSI0@eU<9F2n)l&@;ZPwGV$UBvgV
zUES{^Bm)JSUPH@r!y-O$7}k-!@exYA9yZrd?^F}n*}Q94=&*Dm2xbC&RYUu?oQ7Yd
z)#KE<02(F#mThd6uKxz~#o=?IgKA{c<D(P+%C;6hU*IGs&aFXp@=x6D)A~7$ap(>X
zusO<$8OiUUQ>+OlxNV-qeE{W5_#Wrs>Id1r;6n=!$;=o0v}zMpvyxfDlavmy$e42^
zWV=;37M#meN0Qo_8IZE*<G&rSfjuBN@)_}?ZLWEJfnVZ|9>@e{L3Cu*p9yB{iDA^y
z%q^;Oa_Ibs6TMi)JUQbk82Uh}Q^q$Wk9}}(CW=4V|B<!uGFFjlG=<?6*&jxps@)OE
z?n90ZoM7JlfjCT!+*efz@yx;L4R3C+Mhs(1>B3@z3CJ8b5{2uHVVjF#(yn^BON+1V
z{4i@ri;I(AVSZbRE`JW;QE+M2m}JTsog=imV8Hu+o?s8ledP7n4FLwNdlqGhQqA;1
zzYZcXnc&~=;UKj>R1yxoWTRg|)-eh*Qq8vqSzmH)5Yf<6Nu=gPTu4P?z$d#3`w7|Z
zZ0D9|K)P~@V03-NvI?Eeg_k9j*@QrOTW>X>f2@r5jFRr7N<LGz;a$8wi;J!Tf%-={
z1mF!<By!PzR=LMK@ePrm6<}Q$>dTjzIdKr*n+k%hf!U4pGzHq&GP<wtbrpRahDcho
z<~pV*>RK#A#*^`ZIBaB*x!ta_!e%RFKAg`TsUXx2FJ|DU9mi1W7##}f9-hGNePMit
zc1@`nO>$14FG;JB7i6oNNn_&QK0zEm4IlhET1jn3wjWFH?XiH#PWtJnCCTp_(W<b4
zuYxX&|BmpJnST=7ywx}Zm#nH7y8Q(JP*PzLLYy?S6|3%ahX^`<LH@8bl`?^>kCrKn
zNhAhOhdRs^<7?j+s2{z{KwdKTX@2!5c|wNM2oxBgk&#MXpOw5G=71p0>|?w9#`mxO
z3#X0or+oCf*5<Q$E4)>Yp<d@bpxwo+=;j%Zmt9-XdGjdDCkd@@JXV1tp&xxG+2J}4
z9_d2WE^KNvlIY&i!wtvV@_zzIz)kqSyG4%Vsha)<9u*~+j>bUFW^zeaaU;#3i;G7p
z9;oPA34BcW{$f91M|96Hc&WTiv0{!hOpz<bwE!8|X}=$|{^sZ(Mn0*XC(o??U!SV0
zFI9FXlq*#&qu_gDpXh-O7R-jU$LsQ-;VLVMN6#IWKNucpCZ{c?GvL*{pp;{YGd~6M
z#fMYLOSBmUsodGt@S{Q(nswEQyR#eUX^=4bmPBea|GN#YQu9&7ipM<*aVsy6FFU(-
zHmRq?6v7%M^&lX!mL})vnfYCi@{&p#`!2oIbQ7{XuT^<BProi8e1iz+^ECysA(0>+
zFD^t}unaS0X;C!Gq_96>8>|=9xJ*Y!A0*p-Tu7f9AWbKoBMdBW+?|-4m9<CL4mCbL
zj+bCfMyp^9R?B&MIednx9NMTiXaN^WB%f=-GPK=0n?QQsT3YQ7FXz2)aO+hqFeQ$}
zbQU@LnJ>shAeA`we$nbGrwIh<|KHd7>I$qvP70j5!)CllTD0U#mzP5Lw=t{|n=#0`
z?>R!E^hkzpvt$11u`zp?YyuSfT#4BNF+m)ZO-86|@1y-;M=AkT0B3;VAEHJ&@o5{t
z2AfFGom)#T<1CC0rPT7Dm%fR8pO?#1pQA(vPFG)kKCic2vfr49<!X38Qgd`cSKH1W
za*D?NkP@NqL~noZC*aG>fvxc28-vsVJ03czzLcx#_z-yGnJ5))77)Ojn8n}ey^jzg
z>`}yesksBYDQ+Q0NLxh**6n$$YLw-SF(IgNskM=O>yjU{iUzw-@#wQC{{^jshq&vX
zz427VVR#~gnSI}h<%-Xr(&mr>4(8He5E*t)|L^%YA?@n39vsw%A(%u+&<tCR*X!EI
z<?X?9FJ<3GuK_v*L^CocYoY~q2QWn|Tq_lP*7&;&Z72I*$a&q+WVoRH<IAT6d-Si}
zbFFS*$pMc2!qQ(9hFhjvCpYogJ<-QqBslAMI#<JBk@>};zFl)krj3HXH``DK8mV?L
zeodfiB|rH!OdD8#80l=uN^q(NR+<%dPdF@d9+@fivq$!AHfGs7#Wfd#wOwmkyf`oD
zUH@NfOSz$WpCXm*!J2BS1*V4r@Rn(!eu0%IA$KLZpv!F48&<J#0I=|Y?*!lXSR0U<
zw?VqFF?f{(9K{Q1SShXBeXew4Md`z^^-6$V_-<(}q(<F-6{#dOfR)@XTAF5wvDZ_T
zWu5(mOSxC#7p36fH4~!={#17Uo5T8vKiUDxthT;N*1KNH>=XWVJ57_0N${m%157T#
z^g9wbP;VR4qoKvzuvk0l>DuD=QE^rr%1&+&=P``V{G_Z@kd;q#X_aj;Imx?n<VV2_
zim>=_<naIk9BQA<T+W0SoY#SVd<&|woAi{=I}3o}QyZT3FY*jhJty<q3cl0(rD!P`
zeXe=(a~{Df{r3Xl6Aqz(z!b;5O66xpc~s}&7+inHq15PRbTZ&9A}o35zQmpEc8r<}
zM@{et^-3(A;>aF2+H|mKmu(PJHd2hNhV>6@E^mJc+4B-)-U)yOh#`S*RhN4SzAYrD
zQ%f$$qEb=c<6NQ?i_3mi%KDmA+C)>-Z3nvc)|o4jfoD5q(R~uz<vWUi5qOZ~ePIru
z4!*|UZUc%W@uJ3rN#olR4n#~7=7)ItZ{j&A$&GYb3|+CQPM$VDsbst61nDrt<Krd@
z-FEOwN^JN?nhH>DER``Up(RPVp_2#&!2U##N@6Y+t5eP}YNG!#+5+-DT)%L6p71bv
z5uGj|pRE;#%JLz|;Gx(U9nL1SOr6Q-`?z3yu?%i7JKxg0w824PEn&EQs|sqSZ31(^
z{tKcr&`rV!a1I%B0oC3=ZeVPAm(~J>@gJlFmT{(Htwj4<uWoXfL7<9(1j&4T0f{bL
z&ZLfBc!v)E0||sG&Bz6nW=;DbppVL|otkxHSIDa&BMMw4%2cWwh727f9$N~7rml(>
zIRi@)gT$yo53Z;SXUXO4%E5xP;DA10F<MaMlswq8T<J?Aua^V(j*^eg^!b{2#098z
zm#fG+Wd&TxT>+w2NQ~V4a_E@^VEs=ySTw@|#EPMj2S4&$elh70povQ^fk?X;L4@u;
zxhl(luS^zG?Y?xJn;07rjp#QrM#5g45Ii~EsW()Uda;1`abukO7fz8_PGzfXa%>KI
z@(9!OtV*Py1ef4K#q?U2-R7@%*hZm=37cLRsvH_s?)xbdn3(s7-Srk30cPw9>DZLO
zH9g2~XkU`4IYHu|-sv`oxoy{=sIM&r@c<%%?=BIpItxB&km>Q9G!{x3F>?MuYA<I~
z^uzdA+qyKu{v=R4@KNC(c!<&JH#h8Ro3l`6PhQc=gXe-nfNuE#{;EpUoS0XjYM&O{
z_XTTjvUc=T@FUk9lN~k}J#Lo(hm-$!FQZ9!JD!}W!FTQ~wr|%3ksDWj`XSs&SS;u@
zQCfKJeVy7pBP26eaLz`~{yE}gH{dhZTb4VuM**}QBLm<U+JaNcYK+P|O&R^64MEFe
zQasw0tF0;gzI@C~5oG`oLA~QC2zvlhW5Ytf<xZw@XaTT7`-(!BfT}6!L-XTkMAb?8
zvo|90D2e+SUZVLQCgU&SVOx}y6wW+#ydoPLHcR)N;ueffWr*=jiL5^VJkMbQ&!=sf
zRu(fb^%7${NY%WOa}}3YYl6#k-D7JEhwoKTcF966<_`YJk@1{fQ~88;V6xbTE<QfH
zjGG9+`ZGtP@<E7a7W4`c8YJQxY3WVG<OLD+AijnbbXoZa<h!o2eW2><(T2Lxus*RZ
zq`DKvLmi^h=)dX=lOyu!+gykO`y^T2lGle^b(!8n;GlNQ&ZE3RRgiPg$^1V-Vby9J
z*}^R3u&4H*&T8~n*{73^AujJdVk!7Sl%((%T}CDcIa&Fe5B`hJ7bU@M)zh3RD#SwU
zJ}^ld)8y@7S6T3@#nldN)K-E=*g|W3<RunlePFXssLm}cd@{k)ofbwuU|fzbI9__#
zi~K4fmH|q<)I{u{pe=>6GJ@vbcrCauZDI$Ra-&mP?3?OmT8OSu6F)R9ut$5)NPBr@
zce4YdAAi~rOS~4od85|0!+v*$qwgR{LWkJAFW6tMAhlHcVcQs>9{U8&KBCGXf=vW`
ztZi<@QC&`NCsWc5%W~9o6;M749tHO<+(O#?xvj-V<%J0mA_K0VZImV`L;mRDUN8u1
zcjC67b!-b%G}BU4ayPKoeH}vJxwAM8M6T`zZD?A+#<p=FTJKg7<pF1m8LOG#x)Fex
z2vq5b@d%}g+edWg!l2iHzzS}E7M#L=bGDEu*JMTUzYu$xXYb*i{5hsH9axNfKtPw0
zLN}_%8*|WmC<Bj*Rl@+vJR;3W>)13_Qh;btS)R}F+ozViLBjyd=)(k89R1>ZuG$^u
zGr|ixgOQ1_bI7>5D!5$2_cd15$PYf;{5<)Y?4!s$)37U&8-+7zsObVBItbxGi?N<)
zJvdV6aiX=f&7=zB-t5D2^s|m+v12e9Nv@eih`1OY=~SHVL$2NMdZo(<iEkytoR<2w
z<6n!=5uys8tcPxfxz9WW08oM$ety-rPVnUb7!{U1?ZB8Fdwh~8T5QS%cSE<WRzLbe
z8NNb;kP4jJR!)$3VWnuY$66+;2VRRy((mCD8&ba*;MU^Vg7!mRV)V#RZuX~1bV*7J
zyy$=J>Rli<`72jd1A>dfiH0`e<kZ_08=kqB8Ar9&3Tr=R!=bTQ&y$)Na8@5@4dZ|_
z1F<KEATmt*(&k3cteNq%^lbsUx5Md!5F~bTo1|KA(t=>q`Eb4ych!y2vn+)liw+>M
zEx0DPYvCT2z`Vbce5G_rW0^V(30AMaz`}(&$^R;iYqxgZc1f_;Wj3$I)<J2cl)Sw5
z{h+HYVF(&s?8+eIAQ_xv$nMZ|3=hS03B-o-N*hNrT=YsckaoHPU>%gfcd@bil>vi%
z)h#i*Hkz9)ek5Is!0~(+++kuZ9s!6H)IQ`t$z#L(%A#gw+z%)aO$77s0W0^rOW7dI
zeCEHWkM=>4^Z~CQ^jkf1(`#<OE+*UKc^&1PN7iRyJEe7Xr1UsHmiynmJ|z%L@Tk1W
zsVnLrQbZ4VATM+tG(~Y)tvzi?UKPbn-&!wS1}Wttve)9*TNhI~<Cql+C;R)uck0;g
z52(bM*3J8#EQ!yL9$MJ`uO0*60*!<EA^otf9MJ60>oGP(Xx&dot}#a_*!IbP<fr7}
z_J!2ZtUX0U#JNUZ3<T12$Wq~2C?}NRss}H-8k`L7tV|k+a;-{yx+GM_4@-+9vNv;k
zdWysMq)6wZq<;13!$vZ^PzGmGwp|AJtym6y9|=_qLMiXo>wL>leNHAWRB@U@gei58
zb$U@<jEpB^bbZJkXnM!gopaHm+OPm#mPB2!i<tH9O6h|xm3(p)Ydym2UnX8CrdDW2
zetP5-N1TY8p68ZZwSIl-x$>gdcfe`Fz|#&0_>iwbUX2*|1l2TYT|`DPE#k{F5<ijT
ze{h=j(7an&p}cUgE~mIkFSxcf;&2+*)Qj}!9oT`oh|3aJZedH@XA!@S=ys00l)Sb`
zC3(E>8x-l(3_Nn)nEdkne^YVX&o{Y&ApC7mkj38i8^`6;8f}ReU5f1Vm03X-Q$@tc
zUTAy<5VZ)hjxS=9dY9<D|M}W3DMnC75)mr3*=-H9rkOC<>*0O4!@Q<()~ChTD62FS
z0U*vf5hJg*-IUWAfJz$Nh_Uc_&8D>QpP3x5q(qp)GIWjgPtQ&YRNq>n<1QFNgSsg}
z+r-<O8*-0`ZHI6#{pPEuilM2!S&?f`XQEoG>9y7|`j0HU5AwzFp}?5+ZL#82t;3VA
ze)YMYi2H+bcX~JWzLkoeg<7<_ni7(2-HAYNXK-e5zU+%pFJ$q6JpL6*YHZD5qx>k_
zjSX?Dy8WkY<E3u=dFj%<4NA3>@&Gyd_4k?ny3se!f-at7u)<0XRrv!5Y?bUq7R7!}
z1F{m`ngpAP?eafbf}Jbc1ml~kEq+fz%PWECw$B?tj%i3066<<#rS_r7tb6GlJF6Cf
zOcgrgCl#>(GI$RYM_&Ba+vF1^YniU&Yy23EmE?QWjzllRwSnym#HE?hSf3unEO|+2
zM$I(K$WMB6MZeq2&6^A#;&_qIMbzld%5MZFEH?;i201)*+i4*m&fCSIt+C$%51)X=
zq`QHLf{u{7qlcpDbKm;x*to^E6;$MuH|K@<H_-3-wzZixkiHcI#X2j``750({_P*I
z$v(2!Nsx7LS4O`H`yyHn6M)2|4BtB(d4gi%zOc7~b`0y}IT8?E+ss0=EYew9ks8?M
zMv0Rr+}S<K`iT;6sq`f6X}bA`Qx-RQrK{Eo`@uMQ2~+9B9RvHK!mSZUCVu?I@u@~#
zl1?yafxZ2P$BlMZu3LU(Gm&-MxRM~BGC7^*Wf39iX3487{U1sQKFiXqZFNS@>eN;n
z_tUc^Q~>n|(}t?bYsDi5LhOK|K)BUVu8t%?b1a3>eZe+K3O@LZJTq1D6VqhI_h<@U
z$N`oRzKr7-8SC{<J!t-8=0o0bns_=WIwB5KMWcfh-gc@O34%?=I@DyoNgigl)RXLF
z^zO&C<Jw%_4n+)r+m))LmJxBjRZW~5=Dlbse0pSI(KJ~#W)2gz$J|TM*21$B)yCBg
zIQqF54jY}ATV!?%+cby4Qo%Wgo4XHI&F{R12dE8;a2^4k>l*%fA_2vsEEH}Mnz<Wu
z3EMmMU>_;1lAad#bvAO@3xge}9&>erDWueh?@mzBj7_FjhJZt`%{$+$Xr#<SLb{*&
zNXFw*89}LKcC^CqF%KNa4z`Cy%UH%OpBvxejmiPq$YC%U-I6P=3vnSF0GIXjFCm`f
zr%mogT)M|KnaJygYWWPmwuFXE27w=@mCm{(3z|S1yW%_w?87IvM@U;ZUwPMgxz%bn
zm#eA3`Ns;R2bQHGu3zwdlLg_I_gFm)i(e%<ZXtzWC0bQ(l*r%CeT-M2trseG+{p8M
z9*sAmwolOdqp~~z0H{az!8zykz|}keUi}u?(cXlmtQ<b=#&oLi3MidDUV5Jz>n6be
zxiti2Hy`GczY*}4HhurJ0(cyeCgbN=H5uUg54f85)l_?dXU)@Vb9<`Eu>l`sY1-q@
zZl(IcU2)I=Gkw@gI_BIP1t1F_fSs$i#hmEp7Cx-Jf5$2;FkrC2YDp2?$)G#pKX9#n
zi_%D&UJDd|H$_9_%bT7=Tva<WlOz0nhg=j>0s`;XMwckBJkj6Zfdb%BYg*&57_lGP
z!rjCAiZ~vxcN4>Hd+~jCZKgs9)6IkQwtGl!X<t0ZS3Hil8a8IWrN&=%HkfiWW-50`
zr=au$Q*}unCd9P+4x2)F^|92>h!9PVxX<0x(KCm?o+U9X!o|Zij}k2yMVNFE26p%R
zkL-yr0_E)Rfz5GOzQA96)!4MN#bJsfZ79ZE(<^-OPLs0KIuTbX3Y89w&F$$SD9_Ay
zRCMt7x&Dk(`@py+MJ~8$adW{O_fAyIp?sRNk4QOT@YY^m=|u&i;F87=lbvk<Qxc&l
zp2AOKTdW<#E|mV~xJ`GgIDi=+y6tTgZG(fOI1i{An=HGmUFIE_E<cwFTct_EPk-pO
z3$;PYs=I0N@abkTTk{P+s>9^MF{49;77lp-iNYN0<Qzct8a51d_ChBxJoIm6?y1T4
zwIZ>2#-h!ts#>=+*!x6UioIGH4;W7{%=Pxkh<S+Ef9a*Jw$o2LOboK@5^OpedlkUP
zJG7?B#7G=^>QL($LKRc2Sh29G&wWq~ldO9tqeB-HKO7m-)F^fma+o^3h9m)RY`4<<
zRBgN}3qKdLs&^K5$eD^>?o&d1+MDc3+9({H#8GR#LV-Mh@s<&J^iD_R4gpabI+wV6
zT1AcEVy%vyQ9wchZn=wA%UQLn(iuWb->{!N17OK3CRWZmNu}JkSrQ=mEzR$8<Vt&~
znJhxHw$FOBif-`1AgeScRZbi~elOBiKblbf$%b|z<mE3C(I8{~l;$Yu?I{k0zO+b)
ze5G-LWOc{WrCRFE3yN4JMxqc}?-JLNlvOqaRCbad<jln+Ly%qI2=3#GHtUW077iJ4
zz42^64A9;B+9odCxv_ZU@A=zF)@j$$;$9ns4u>3Yv}tPx%D_Nmap)>tY*037qG}4h
z9D9MzY3z}z<_!D?%hLRaFVLaFoJ|?)%2Ph-?%|>+JqOnLl2u0!r6{Cqpe?PvLalmD
zF{M0}Ncvc-R9{yEBA5?<o}kB)z0SFVlnE=~R<1v)I&@>gK9`f8-Xp8yKeRC09aMs;
z(Xc_Kg_MlXMu$c4rA!ZudaEWp(}dLZ=%w{#k0c*UL(3dpt?m^Z><;ZOf@|Sg{5{_X
z1i-!^3C0Jn&@I`{>6l7>dy<Xoh02FdtGySlcO{AXS&{8Na>47GoV%Q{%f{Hc?@Ztr
z#p=zyy56Cz`Q@2w=c_&8b_)@K#)$;liL(p8y^o1vRKN!OHA?%a4t*BV^<lK4h9_Iy
z?@G`HaTL_Lw<W60-&z63@~pv9p0spSH5&Dx<V(Qwc(vIQ8$bPPq42$71%N|8o7G$^
zatvWm?nxXLJK)x)>+VMW;LkE&cf+)6>DA|ITqZMUq3|jjrabvYp=M%yo67R@Mb?ag
z?BC0S4qKeU;udSA;XYROeL)z~^Biovipt}E6(P58Z=%e*-*#A$iGn#Ckp_LQQ0kP-
z4Kj*OPBS@_;TJ#Y0xuYkActGV3+6;DyLivk{>88gO5@fA#=1@Lv1$GFV3($&uL91!
zP(1db_=J`aZ`h0>iN?<st%(8}3}Hn>Q$u;CIn?H?Qm%AfLP{v$xeBp4`Wk8)$D2+H
zU?P)S`5cHR2@8r-B;iv0FIBUp==ZNdYG_?GKGQ=gAY8lo8?tyBRol^Aui(-jpR4vY
zN%^Pv2o%-b<HQez4lPtL`3c!=y#*|-FpPh|-5c}hD*GG=N7U%7o%WN94hVKF0S+jd
z@U@s&BNn!4{E28{chQztvwy;83$qsh2^dWV?A!qwET^aH<hmE>)4o74%l&0L8%=p9
z{XDhy;*twI7K6N4C`Xa2qkT``SK?e~-2i~{oTwj}LMUm;9-4&-AfyU)g#A(V90ky$
zI;Ht1lha}lJVmyXAshwhuy#mzvD^c-p|f04gc--*rWm~7ibMuelvCaScfi&bZyw!y
z6o+<aXJ`yc<TQ;)@Mq~4x`jhGi~1k%>EwmP@FP%w?{0=;wos5vMuk8HU%zA19YD(r
zrX=Sb($yC<?;`t2RBXx{_{fGdZID0oU<Ankh(2b2@xjlcqrZ(7oV0g1$~v&D74_k+
z>c%AnHBv2gcoq@w#66jfzVq+$yz_cun1cSWT#<jgX9KEN!$L?dHFo1$LMeCEm`qQn
zIZQGZJADz^0DDTrF4vbGbb<+zKBQ>!2Lz=URsa<9X%MSg{*kP~=(U>{i{@#O0dT&>
zQEBh%S8Kh@Q~YGA>WJlGgB0y2RYNi}`AxO7k_G6l_>#YvB&?#{!P@kgzT>G>BI!v}
z4^qC1d46fDz$KNL=Iyb|fu1~HRj36V+p$6S@7otP?&@!Ye{HhW4*vdR3`4Bd6hp@C
z!zf5%ZbLy;`77@3%#2VXOjsPG5fwdC^eyUg*bmmBGT45t)u&RTP=A3S9S)3~-Z~Xk
zQOvTQ&t3UD)C%HAr_8Nf7&S-pmx1yZs>J=E9NAwWN69h;q@D^TyfZV>({8R0|4Ic0
zw})Pn95D@ADAPOzA*IOrFzdqi?98ui?5W#DL`x%YP-aDHItE^Ex{&RX=g7ERR#mx@
zr|-n~vX@afsz_2G74K7)EW;_@7IAWwpqv1C7lBx4bIw2pgTFSuQrH(JbAuwT-t{6h
zicE|kLTS)aWZ}3)-y+#st?&)TJ%iBkwtd(kw8d9<lzK-cW;<TW7F4xYD$4Apt6Nbw
zy1*i4y7V#o3n8end5jxeUzzS%9w_9XJ_z{Z5l2f52y)G(vSz@|n^*?}7HfoDm8PQK
z3tFf1On020q^?kuNZw)-C24)XwX=N9^V{;peQSm27f`+`Z^q)QJ#kJpc-Y}xi&Z$M
z0-ENMOx-~kl3m;%1rska?!w^xoq3+v^z@K4Gv?U6NV#MP;sYQN)gaA&5#pskJgnDy
zAnE*}Drbxxz_C__Yf=h#gSQsuha~~sf&a!4oZlFkx}wKkgk9lrFA>L@#q|E`nqt<0
zVE6Tm(p|NmtEv^_e*AyHzO0`$Ipe0653v(~zqddXKYWxn2NRnJx+-ok(e7Ka9x#f6
zCnl;W$~B0*aboLLpcDq=oLXGDyX8+#1C|FNt{gJ7O^4<HWAXN=>uAzF0XXEgV&^a&
z;anq&&RXQ0)2c?g6wN_Fw}Bq`*!;xUFvnJMw_PUtx*8d@?Te+vfcw$Nng3_^kio(2
z#5MjV^zo!uFLT65>9_?BXpG9k7JxbPr)p&5{VS_ZY+uOp+%XB1_vUNh*J9?qwJ<_H
zg|x@DJ%MqjgU8UE8IvW$)v0<EOWpTac|B}rAJ~KYlVX$d0*aWW&&6e=1H8vFY%LN$
zd=%BQ=ENc@?g^Vx5-gN#G6|zFKv|l~w&z}cU}!C_IY_jBp?MMtl@wSb(H080ep>E?
zx3Np~pg24hFr8~1)j537n6h@vMfHRE(uIDkt4xYfHZ7+Ygfld;Py|d4wJj}-Z8#Np
zInRVa+eJWYx~nq%Pk~o-ROe@T@hv<|odzWS7!S}Ewu9EE^bNzobNezmgX>Mw2VQS=
zP}lOHqX1&Gowo1y&=EZ!AjD0mQsH9^x|MfdB-C;*_ea4B{)k2W2S0{##kWdQ+4T2P
zqFb^|B|=_Nea$-|p}9-Ub4Q6!N0IBf5>m63@TwXL{OLJ%Qm+a?&y*q-pLbq@O191t
z0GBJRyBnJYR1_S+`PC1jjXxH#XOv0-Vdp*lr>8AKa+`+uvGkP(#lOy@=GA8Gg6fM0
z<nHpbuCWA=6kDCOjKF0JSJ?#b9zI2=&-UD`@X@A;HFvjoyaUt87aHY@8=B_R0u0na
z7A8AoQR5x#4%-Uy=JH^U*FUcyl_lgIg}LX&-&DpRZGx!aSli3%ls->1G$tQ^6Fk}6
z{>Htw`7oDP0pzA9wfCQr+%(D(-1nDXGEs_IU6j&kzIIaV;tBvkmZRsJ`{!qq|7PVX
zTn_TU>OmR8Gc|Z(rw>zDQJoyH0i;2oeSqQxC698<S?|@7-I7lOiHtBp;ez8V4sp9Q
zbju40XbY|+X1T_5*cA*4*`9#=_n=|)0FhaBr?YW8<45EQ_la{1Jw`B(XSr;GeSY)$
zwcKSgot>&;3j(3>hBf{xF}D%&mhT);(d*9jYg!mF4l1tK^Mic7w9H^zo~LBA$kwSi
zDy031V5RFe%3NA=+^clOv63aQwbs|bOrCu>)7rNBl!Y&cFom9-rRAHP&$%Q2z2?+V
zt-)mXl%s=GC11*cGO6tq=+b7;2z%cmR#;OAqlIhGpkh@Ftne&1dklu(;a*P|+9fMW
z=9(#NoDW)_evpoH;RBTr12v!J-_SNH;L}sC0!#=}oc$wtR*cc1hsAw(N04W#je5bu
z5E`FI>+sCAEi2{&{_<WHhW#DnzgU8qiIMIMiVFBo>x!c2U+|xvf7XDMpL?FVb$wO9
zFe_OtYK<zcvL-ecRi`6=VfwZQ&}wiizx}qbzar{>e{qHtuy+knP27F`BAkoP)1YK?
zpA2<iwtn>K0m0OeoQ%q7U^?#0Ukd|hRwGfcrm@hoV(Yx-qY|^K;5vRaNa#h<adYoM
zLR3^6L&7&LkFNqN#mC-MWPg8gn53YmmpPu3BFNsXfE&E5=(Oes4<V>TDO3QFv;c{O
zySox^TW06&3D7O0>mDNM$T?6zVkWDT3vxL<q0PpZO0^UNzI6fDpco>R8-mY9ThFG;
zGac}A?F99$84*7+i(Ed~jJsKtYS^Xf-40BbcRNE;kR@xk-{98CHX*4=ewzd_o^!`I
zjGs5RXn*o`rKj{F*u8yCi)jehhM(9u7y1?bc1mwT*yYNdHM+GIi=ZeE&~yePt2O{N
zK-V=4iD5%un!k9k%Q36l*VSkmmzh{*qTJao5lrB(@v>fP^lM%pJi83bG|g{9zgzuP
z1nHq3Y-9?!aU&daZTxBVvz<=oRVDipmI*tbiXJais|Br(vVT|KiD0FOPO-)DcwfI)
zOn$9X_j?%c(S@WtI~KYVtLM<qKD=ZMQbWOuiA;&^&{#%a*@mZPug@$33x&E28YmJ2
ze$%bu<Wh*>qG&HWt7hXm41>jC_D>s4Gb&3zX)Zweh>1#<k4JQXg77ItX1g`eA}iBW
zJJ!M7UQOAH*g-V*picfb`iUS2+b>E9NK{YDuY~v@?1Z8&=cD-e0Zlb@E$?E4ND5e&
zQk9*W@Z~>#0ovW=6ePJY`6_<*tG#9Y#(@BWrF{<H3849+=GK|o>)qAKCcn0$6@u5O
z?oso$3{>JF1Hea0M5~#mK|9>VFZ2pUmS_$5r^KHxs>J{-rv%L0`%7SBgh|}<6$n2C
zNq0JZ2=u=t2cP<hxc8seqny?nQAKJ=l$X0oIe)`6bgi0@_MCzReXAro2VgP#!)`sk
zS{A(v*1QBqT41_aLC3F5=c~ydWk&9FEq{a+<ll0o=IvsrOy^@u9pNFV)r8~t=TNeP
zj}(Hc|GOZzK_XVSni4T%N>X_=zB8cjd%b5$f9NxDL(Q0$w_N?1$LYp1lR<iHxv~T=
z8ax*FCX2(T`@*9_NC@&k6^iQLQOXahLaV#pl&>kB*YpzOXUHj`(A<q(d=bw0IUqd7
zYd?`pH(`T3&+=Upy>uWtZor4u_#To)CQIksGf@8+!ejmh4vHM=qz{mVtmfc}zaNhZ
zc|zT@gRQJDc34{Y1tMWG_VH7hR)0gp{ICPKXi&i3B2Y7^C5(%(x{76HTG}5<3RnR?
zj*evTb2GFb_m8cb8t&~a!JJCiT^zGMP$ac29bP8#>UkYSCm%1P4CTeG$Fu9QrDFjH
z@ZvYc?T=WhsWvAO$=x!xh~cU5>eU}4zl>0rT057NS#><m1FrI&K6&|#)ynxJ+`=aI
zz@mGICJTJ<>)l?R9%dyw;hNJ0$uEevB31feNkmcc*Ugq!f>fcLe|SCZ$-KobX<d7&
zI9UCtv!`D!#4064tW@K6mB>~$9M>QYv)dU;RK9g;2!|oO9@_s3IHgOg%~~dFMyE0=
zBJy&?=);m7b<rNnK1|uzS(E(H?h87V7~WS_6G~P2S~*>PM8dk9Gn^WMf^=y)#+wIh
z7I%0^2bc9Xq=Y{xrw&Q2Seh(F;a6)?oHDobALsHY^9UWD$_DZ~|DKHDCs@nnE)sR-
zP_aVjJ}I~NUo_jGZmOB-f-gdLgxtn2`huy!=F*OHRS+ssS>InwSc8f*u~fpgN($ft
zpms`Pl>4Gpc3n|Z)f;+O!j0l0Nj%VB5vR{0B|7($N%T5(mUci2-ZaNi(xFj(%6OnS
zE_tRe(v&xXd|ZNlx6=+aNyP9W-!ycg0oJP4`7e=c$tXU#%?TM6PYQ1m!EaQ%rzY=0
z{2FSeU%Soti^b6=i@rthFkXV}JTsYLzlx3~6HpJY;^2qw@Kkp*NhksVUWi6bAFsLD
zMe6Qli?JqdgB_tRB+RigLC?lJvfe^bQO3K3T#_}7<+(Qu9>Q%-&~B<O#h&k`ZR@(g
z`6Yw|5Kan#qD{`|Xum|AV9sgqP9wfgG`2GxL|fdPNz3s!Sg#+g7s27Ut;I4VKBsM`
z9x8vA1-_>>2Ic?cu;r_^%Vf5_+*dw11vl=><;<fo6#jO>mGA*RPmbs1snQ5M{uWBD
zF^x=9<RNFw#F$ltP+&tp5&NqRn|w(WN^Fm>u_;4eWQ*H%8~=<TYJDu>u!*H+t%{Jq
zj@gZ00fdIIhDn>n0u(~VWPmUil%&c?RgNv~TunXBIdqzZwau38wLPdb_>n&tmL<WT
zxEkr!0>-$XK6&FMWBco$-qKM3{bRlTKO-J9&$ZiL?Lnp$KbC=T!oG{z{EVroCXwnQ
z+$Ro1U_xJvYGNdN?6vGKH>}XJ)9c{8&;P=)m)JJhCf%|$zMu!Pd8r7;vZ+gx_a5@J
z-2tPB%)UpOFst`Lu(k-;Z?MMPlcj-_%qrSQ*P03fTD-?miFkr<79LwP-BV1;`!Qt;
zBhS;^bfZTD&L2KDwL3nS9O-R4OemgsRzB#2w2@;0hq)=z0@ZdqHMaTbN>6Q3EVdix
z<L>?mfv1}==UfBgnXvB%ad~xa09Zh$zrqTg?BcqW@{Xr^e_+_-2XTwV<a<%Pfu(L|
z+@3a(-|(F8`eG9!n4+^0@C3O=Mh*oqS*%M0A1D$0HQbpYNrBl^6lHz1r@pS}J=gBB
zm#s774WL1Z{E5)G!gB7^W1@)a&8K1N#5pTYfxH~3`}%l5h8aE19xUo|9W0rehDKe6
zbmKWJ^3DLFQU-F?9$4IwOHjuj2<idTiZo2zF+y0R!%We?j$GU25c4CthGCqAYeXI_
zFlKnLmF+c%mqQKDpe|yI1g$lVqOi<07PjAi&~4DYuy!l*qF+3N*n_=T`#c*@Ki8NC
z<d!${czXona?a-x`nWfiTM9<P_T}f_j^O0K@hca9zM6~?QX?gd=uvXTSvCjVW7jVe
z5Rfen|7jqgRkA&Nc?2}Klu%qGHt{`T;U*-GK1?TD`HYDpVzRp|^IS-HL+$>qL+uuq
zd3(KWCd??h+GxzpOkZBdmbm)OQeU&7(~g3}rJZVNZaIo6Qatql4yP)Y+aIvHy;Psd
z>oUVHFeVQksWxwpH(ET0*kVo8*;K>l{RC+(yD&^D=EK=%Y5##Bx<$fD_p8EFj}B1+
zJg~3Ge~U9~ON|!kYR~{PxQ$1wlr%aKPDzLZozXx9De$Q~$ozGYP0ZCwFjt|f2W@!@
zJvyh)I{+xR>w_0P_huw`+>BDii1(yyWVna!ZXp@=JLPI;P>Rq?s~w*n6jf<`WKB?L
z{}2pncX_y_mHA#&kw)zv49R~`<4fs13A0q<vDz<z-1TUQ@lK9zkAD8)WDfpQIeYr{
zA6K{aRmt5#Moth?v9t(ZA7~aW!=5~nIcD%yE9CBP0HeJXRbJx*;l29b7a7S~U4myY
z>n7TnZj2Nwl(rx9QwISOi6!;kZR@XKHZ%hbYxcOqT%~qFmz-&?+i!X!$0<a^ra{?L
zM?c;U3W5s41_PLlMKIWm*AfRhS1k_KvK{jBXt2D{{aq{@101vC1L3+wSC`$+7K#*;
zX%u1RB0*ttcB`$PYvkgEgva;ZUryh%N<1&)qTC`5tuj>Qy&&uNq9Di0*A0`&n6M}B
zm*```*uI>`Pi9q^n*c^=ta*{yL@fOub{|OSZV8=iQ9#4Kst#5Ib_sdC#(Q%ElQs=>
zz!^nDVcSEW-bd;AxZb|1a_6~lxXO;oLES0<aP0LD*WZ*V`>jb^LgT*k1d^Rpsoi?f
z)1x5H{Z462>cklcZd$>#3>@+5W3!7Lj-iblTRq2GC^m8K;%_Si0921qUKGy#Cj@BA
z{whXgu6kcmi<d8e3RG)9D8{7X*}Y_8`Pytq<A5R5l&4Rb(?w}tn(@?et)U1mvZml{
zR|0d&qmlh+dFzF!C<e@Ik4`ue6HQ1ykk0NBicm!}PMQd^#|B77CTR;PtVtTwe~Y{*
z7x{rKfC=O)mk*rqfaEejcu&W`pD6YgHEpDLR4{z5wCgjiVYQXVptCrDm+rF+;d;vR
z4kmhKLLrTH43O^ehf2kVEiW8-_ixZ!lUlQ8&74F+@ARVFX!Xf^rlUO#7QV|<51=2z
zC6Nc<^c%!MB5Ze~$EaT&f~{8V-t3d|xmZ_HJ{Dz!lK~v74u_C8vK*TN1bL1W=~SC1
zRuh$qGT8A9By!yf*jRa+0XNm>O-%YCG+rYy^0*p=ll<1MyS(K&<;=CTa5`x#sAC83
zXjng0jLyf8jUx?l%YsEr3h80$g~%KizKO5?J%r6AdH=-oVz0GtutXss%X$lPZKq{b
z1&f6s0ZnKcJ>d%0X$?fcYZP`Ax~!RA4FF}eC@DiDL?Y0DL&cA~@OVH4#SNL=i2HWC
z;xK9^chE1&P2wzH{^hJq30YN5AU916Dix4%)L|Z`c*WX(!{%*X(3Qw2evi6Fz->hj
zTJKE>Z5@SqFv5YvMIgaw=8U@05$aI&*C>8#w%s(K7UAziS1<>$)w`<akG>@DIPDQh
z9rvoWaO{Jsw2SG(Io|PlLTKI|o^MzF<n;&_h+TOdXGU>&y)S*;?N;T@BoQ?bz!#st
zRCexaDOw{sURT4?j!rJ~dn^SP+^b)UHjLfC?*wG3-{1@0D>Cs$lUjuO%_uW(RST&2
zDa9@IZba(OSqCG_#3L@bdx{D+De7^F9I)YI)03P%DGna)kkLxXKHA?_VD;24rH7}N
z^Iew;*?Z=&J%%;_2(2--85x(gzcT&V43?D*TY_C$sVGsVK0HhmD8&JOS-6R8SrJ+>
zJz_1H_g%+$G;d@BAjP8uR+$IVAz$McQWN5idwGW2%puGLk>9!72aAs%`@KGmPK+L$
zSFTeLb$SSB^F81OtRVBujQCKsZ(VqT`(&gR*s_u)3sJCu2-V}k#1z$}j&fp(^E(n^
z9eLdpAodT80A%*K>_p3_3+Nkooxmm23NU37?q8Wnwv`}2>hVV9(ck`~8$L7&=H2)v
zSEpU51?EF98w&5N2*~f3HO@7eu*j&mbmhcm^mnb48u9{R^sl=dz}s^QOVOc6YQ$Fd
zz2Vt(_p5)c9&}wKtSPX+6Ngi9K%iu+MemJT9u8QKR1u-+lgyo?EQrxFuuqX`GLE0a
zyXJ90Dr(=KJ|3NVknnBGj=|xMs9Q)3Zpb!&auaqvBnne0;Wb+^nH7J|6v3&Zo#P`6
znq$M|k(CyP^LfH8WHss__T#n8l(!0NM@Smy9DH<-I)X~kxLrAu2xy8zR+aJ8PHtNv
z%n!n1<SY3Oqf1a7t=D>Jsy1=Z^goIFtLWVVH6pgaR9L;UzkC`uU*)phAuXYCvCfuF
zmZrchJKu=6h1I<UuIZ9Wz;rV7azf~d1kjiAR+n9m@Y)aC#{-idm1Q4LY9#nx(kA*2
z>HPGwt1N%!Ye@HLU~#HqRc&(_40XVU4DJK13kATf;hZe%{Oh#2-qq3sJP$1XTTJZv
zr93sE0x^)}-GQ^RzCSR$Bv?yFb`jpBqU}w2U0BVo|3v(8cb*yUiDQwl53#lJVI8n$
zG|t4tSXdmQ)M5`yBb}TeLgU84l5H_m1TiE~!=#b18BtOXHd8ybfn8My5i}v`ax4gF
z8>SXW4!qslvuOg0_5h{BTaLOW^7erwnNZNc#RDw8+Au`L&-~edJ{Oj;eQj@5{xs##
ztwH~${~0>{@^*wh*jUuJZiDlZTX0)yI_sL<8z;OpG(eK<bnQXU>11tR-<Hul#X5iF
zbf_VY;?4Q#<mna|j1&_ndq0~|*I3G2q>k8qWA(?+EB&zLc2|GMvR?|9XDVnW2vmQS
z33Kt6VbOKadT4a3Q+ny2Q(5Fs_)eL+l*_m+8F0KWyD~|3izp8Y9C^3T%=#dQK%Brg
z1~9^?9kctojv*omyzC0z=;METP+&0rkq@?qo85p<C??}=CNv?C7Kywlx(<Ys0qu}Y
zOOk-Gg*xBZu$ZMhs_x`XqR1W^Sq8!IyjYbg9}xeY*etl&I1cay1eM85vib+7JGgrk
zv$n<xD%iY;`k;|+4Lpk8lMttf>BY&5QvwzS%>=?F<l{NGQS023ULi#rKW!tPjK%Me
z+XR64>BS}TU0rJ80*%sA$7NpbyEy(y^LoV|w6rLPJ(Ls5C#q}0SXZs+tF9LioAhYL
zrrzTf!+UIq;6OLc8N;>2YfG*P#+{ev4W5Eeese{2_-nF!IPMzB_IRS3n_C;KY}Qw6
ziHIC37XR0C#dFY*8~Kt<^=f;7?n>MSN~k0(vo+&6=v_o@oasv5hcb9We20K1w?$BB
z$3#jX`uXpYg*h)>v|zQwatqBm1fv#Iy6W=)?90c^OR0p;r`=H_GeFhW9jg2uqHe(H
z;`dxoz?O(O*`1^~2zE)NIhgQBj9k=c&}y13{E&Joq3y8=Cr^S}N%aCfw9q8n=3Q)X
zz3CwXYALCO6)H*|R`aRu^=vArl?Bq?Nm9kWyC!93R1EG2@kXs0n=I#S6OU}k8c8vc
z<a*4z49yFtVfLBzo6j-|c6YdgtFYCUR{bPaN<2w^En{%P1ipNu-|R6RDSMUBf-mf#
zr{O8&;mFX{8~8pB{k@Ek?`}MT$JLaCqgFW}xj~}MF)H=(5m^$D!#O6GjB`96peum`
zA?BFbws&G%XK`iRZ*p#B9gpXLMWzLBflQj$;Ngj><*YeaW`o}7hJ*bVHrS6vS`y)j
zgv!!b_N?rzJa;EO_d}Pj^2m8S;3cnH&{18BBzA{fa}4PQ9%3`hKXnb<Pgx4ND}NV`
z3YVT+P)8(02}1hLv^+q0QK(mlZO%?(mxqs`u>|^tIhMzRedi>3_Ng^h9gb2vu_^vd
zjMEdP>dN+@gt=A}7LWTWUXZazw=Oi(5hCjP{piZFc*DMk_~8o5iKNRx)(2XNOR7PD
zvAqOx<0T~SJ@xf5gZ@oOK$VB-XkyP3Nb}KsOL&h5SrN~x`;VDE5wC=kk`uaSa$Hnc
z10rk0Y9C`0U`&CHMbT|3h2Ip*wa_a26Mvr>Lp&K$Yoj;NyegK{Fy8X#CXfaPc&IYI
znX5*8g_L3)d@+^zf77w10@Y4Rm`7C4oq9hAlN-|{dLi?9YV6>JI-HvGzZ}lwoiu$K
zultgKKe_M0god_=MG&TI&6T<fb<gM9<ruBzgG8Yv1+W#3!Y4pLwmv76kU5isg$Rrr
zZ;yaE`nnfyvbJft?I9-W4^;H;7?h!KGsrfmdfOrWZ9Y4sW0Eb&H`{hG4(4>gn1lw#
zyPYmu3(vqhWUu<zZ+%R9p0x}e*9|Y3e-;g)<aV)N(_;aa&Kr6JF>rJFTc|0wO_ZhI
zmlRK9r;%T;3D<#~JoluX_?H+77PvzqO^4zkMnjt`cn0O_8$SDno*%A|i_R+RId6D4
zl;fp?&Wkc9Ao<6oCD2St%>`3&L88rC(Ot^2y|nEEH_owRepXN!SukJFh9YS9&x_*U
zpFj05R`yfyi|uE@;l7c*H=7-k0FlQaQc9XtNoIw*_cyI~_=%Gi^UUvWi()X;bF+uM
zkI0x6Qn~(_i<Rx%$%IB_%k4CSvd)MONi^x2T^Yge*)VVu<H9mun;x!g;Q|P1Z-D|?
zHCwBj-ufiLQ$i74KY$<md9iSW-YG(ye1PJssinkQbx&d0vFZQB*<s`?@x87!v|Aa@
zrYtCcg$j?F@PMMjZZE&OPvPG%346D!ShxNYb5qUMaPeTIj3<Wtyi)b}Nmyf7QMbZI
z6sbWB7C5vRv%dTFU?3yLToR~YF4zI;`gg<rML##ohJzh=%XdQsdj%JsW~91|2AP~5
z>PPa7@;}M(zLFIC;Cf83Ldw0ZX^1+O6C*1ZM>}!~;Ki5BLb=o4T#x2zDXRikpx%|F
z2<*ynSKB&efk{IQ_hrlg1aDD@anG5SvQ@30XzLw%j+r>x-I&9Lt>5AsCWSh&s#COD
zMPUj753n#0x@_CRGX9F1n=jqtB)yoD0Rv<UT$tUTm~(uTvC_7ixBA=d_p@C;(m2wc
z@#ox}_P26Ou1f$prqfvc0c@Ak8tY*e?Hd3uV8SuTvhh>VVuU)>-yS8{8;!BR{I38e
z<{qb{0t6RBu+4DaQ7#~jAT@al<E$<cH4R3To%qdNTuK|;>V%sDd@G<fD2i>54!Lw{
zHZZ@BGhRs;AGw|_guF&L^VI7i_+L_mMOV|y#ss&H8_$C|EYD-NBlMo3aqP!uDTL%#
zxPVqk_<acLa>ql5*Vg6L5Gutpo5Wc<+$+6X7J*8fh-A9{RdRIxYSl!k-6QEK*g4r1
z8S!e&XDh0$ndKn-I8k$o^y4D%!3+Cyix#fT1GtS%hXK#uZs&|@T%IVasN7+B%h_AW
zyx?}EiZSn63K${Uo+{f=F+vC6i=^bo@S2KNCLA4$<06N_tEg-dsBm!H#)^xo><p9f
zyQ;SXye9fVV|pmR`%rK+{u|BI4-!wd(kM7!;|yYGcC_g&?=mzZRd_eZhme!wPgb)p
z)LB3Oelb*zd#LLl(WNW)EsjrM=p?qagz~bZ8v%SH8iK8IvH5Ae_{H*2c3iOZr|#OD
z1O<^UWKA~(o(A__8I)@JmtXhA(gb(uH^jQEU}=n~D<SR*m;61!x>4gdJ10;a&ve7=
z;UpIWu{fr9)s)q6F6_8$UdVhdk;e)y(or#cno4S{cHlS8UK6iz(i&Kd4E<i^s5PeB
zRz|}nySuS#&Xb)!F?xvao&yzYbHx-g;chF%nxuE@C@w%4g%qG8fYjKx+n=2x&}oJw
zWOPTgxFL`Cx3E(>^?g1P()g5g%(pbOq*ydWQ%>%MGsaIi|7`{qo}{wc?d0kKLuI5`
z7edsM1uv(xHPPpPpLbJa=)R>A(*7zm=J}84w+BBaZuYJ{e%hv4!W>07T54Zy3W%@c
z?p`?1Q1#Jd;N_dBpJLmhcgNV5WzhTWEfqc7$~i<QQj*NtCjHyA0vbOg<Umi}{42B3
zpBpNgv+eo~e`k0{(H>@`9XRV0kTRskQE!9}j^rF8&bxvESr&h;ZB2t(!znvSoPbg5
zgQ-(^SB!`n-#PQYTk43VrsVxqE8h>ztc*0{h#aZ!XexAH^bv@=d1c^s8?QZ`ri|Vd
zxPB|S&zV5!e8Ygp*-!0Yi5p|A=*C78_Ery=j)bO~#0dtSDffg;0xKuC_`XlTV?IHT
z9}X8{JD|j4g9oaS&5CY}dhy`!SzKt(f$;|rdR#!vi%QE6uNf1pHzY=+5Lu@O$v=ia
z%5i)LlM#xvl?n7+bJ)+fg6iXJ<h@}E8N`o*!GXG-^>jE--4<bs?#MvS5w3VBeW7b^
z24=jbu7g6Z1C7}NAmnD65%mA|A}rV}-i2{g>rD_<mh<KVgcaTIdD9ZsB14}#ZHL*n
z?#g-hK-&y|WdIg<SejL-XOG<xR<l@(mj)d}4(}*IQo;^zrUsth)0`&K8g|hMhlbbz
z;bC0I;jGit2GIz&`xHuo)c!sr_1E#-amJmcY>G%laeeeGvsyP&`~=)jO$Rr!_9H6I
z)RSAu{E;m2yux)!Ed^Y(_-6r~MLBg99WVq=9{f(|6plJ05VmQq;9VzPyhllxDwhkC
zsswAcaPItDAK{=PGzIBJ77Z<}l_?Y=55i=ueHVm=V-N3N%_{b+OQWrz*duH09~n+8
z;SC_}K4z&6$<ZYrh|&#~;k@|AknuW=K41CrW*@PHE%ajz1VgRFY=2>RpayF=(2{MW
zE_+x-%>_932&_<zg{kHs(eW&>;83xJs3f6AWZOZOj_6nA{aGsR>G#BuDezj2y>B6J
zI*1Kr`#bOK`Y^OjpMYV0!b2}ig@%<Kdo51@F+3m+x)MS&WJb&x<y|K^6!iI(@q4bQ
zC&vTRxAs<Ox>FFyK@rYI=>HxumYM`x0*J}$jq$c7yI^6nS&AK*Q`mngX{VSL%A4Xi
z9tTnM-$$YDslc)SSuSl)5?X+ME^pUrgVkjAD|Q^=V#7Xh8xpGQ5BobLK>7%NA1_=U
z*B7ch!%NJvlwhCK3}fVon#1&`t3JxSWqUaeNBk}qz#qhbd$_EbWanEh{zzI}?(NY^
zBq>_qE6on!M5Z$zE_b!3hr^AHs_=r=qK@oGxuRnt$nlg;`ooaXeIMH|AY)7e{ASGI
zaH;Mt6Z7Q^NmQHbslUe3A=A^LQW@wiiZX;Nna-8p(p17GQRA~)<AkH^G-_NYiv%|X
z8UHg)vOqyxz!@%JSFB|JK_3Lcf_J&}(z|;ROFG8Njz)=T81?RAc<enVbZ2pjYTUV1
zdaq+ajnhm7J8}^^55xpmC)dWs=G({!S#Ja_(Mzz1^jZ?7+4x%~<kD(kVM!vYnhPy+
za291hDUgVNR6tMEpf}wQ#wxQDMWSGR=R#HOzdJm|-mU8`q|?Lx=2;7I4IbcX(4vlm
zmq|{KwRU`Ny64eQ^LTdX9ZT?X#8*rpZmu_-B5Q-(Sv*mA=gYY<j3$$54==dadP<+`
zx-rvUwk^9Ea*wuI5W^!~1PD~2UvNC>`net%nB<=u&%Z6w<A0C*!(y1EbmwJ+HZeB2
zgw?-bHF{QvAXAv#P*7XyU@Ld8^bi1d;9yY6EaS__!F*jtWW3Fv^>@oyNHBR5@4E)k
z_h|)u^DGJT7g#s&y{ey)!IAXU(;|@9HMDXL1`R;|BfyPH2gw6MGfN3oY+XCQ8zn9y
zlfONk_0dkx+JGjD%Nr->uEb2Z$=JJgO>%19@hSnU;2Mc@Z<<ohTW}I{*uG;ET-}l>
zzjD!?zW9J?`Z&MVH=k3wAHPjCj7179^V(3h#r9P}PCD=Bd|wv|_Ht@my_;xfm1dtl
zf|Dz{YNqud)28unA<xB*J)s3w8dh7(>xVhjefiF31Nra$tLB`OL2`OE;lNZWK%|%i
zB@<*y7Bz1`g~#i{G(7^KJz)hN+44=J)>*xLh!wCpdM95RcEDc3VZ~%ExS6`(VvH`G
zG`zy;6w{^tkl8YUUbl#s`;6DpYqiwj@<TGJ_S$Gc$nLi>KFanPp2d!uy2-NOruq2l
zP_nO$MP*U*31}pzy25ZMxIh=|VqnndJ|6I=4H*>802l9uF`LS{qxYb;FQNpW{Apj-
z&wn3c8Fr?ISM{JO;2v}?q+{_KzNH50)fr+YmOkFI^w4<=_)^;kNax1N0UZig;brqn
zPxWQJr+-C9@#xcJLP+>3&ojAadBk0*@-hF*lEO^jH@c42?NAT79%|llFqB#0ID|>u
zL5u1Mwe$l=T|6J7-!3PE{mU-BHYcp%su6#;L*HKmJjMEQd|j&wmwv4Fw4|W#NneUY
zYVt}_iT~!FC1fzF1<>-H+YiXA8nbJr2!9*6-uTnWD6vTulsC5xvqEQVi?fjoIc67>
zASV&(%d_DZL<0yi`wPLfMs8Dz1gs^~`C3@)bT{6VcON-dc*JrIB<P^WR1h*bPzhr(
z;{N-i^VP6X2P8q41iuD?ef0Ocg;=1I4sjoSje8RV0u{c}%A!w7)>8`4kNA@B2}r<`
z!;at^vF<a;qY{}zo>MwQk5OVyyS>H$Z<0v9Jo*W`ARNP{M$*vww0I5x{UxS1=x)M9
z9g@U%%{LsT`-LUP0l>$clM+Swcu-M8c4R3uV-p+caMK*#_YX7Dj9eVR^!O&<a7oZP
z@tLaGtv4DBtCZ2|K1}T%p~_Y+Y;9o|Ao{@0ya+HFgMUFOfzY^b-|`kny9fp2&Nmo5
zVQ0V|fq4Z<4F9_*TVI&rjbGGeWS^{F*nbgBE$llhX{8Xu7FB{9xuvYI06VJGGm>X4
zOM)aFZ{G7j{9U37P;wpuzh7`sXq!|SyjmcME>~Hk#Yh(s(}r8qsB7_*iWGahWx`My
zG~j4Xm!Ot8qV{v9+cUxc-$YNrVoML+;5zLv8s(oT_T*-*NJ7$eUqgyHi?|G*Exq(g
z3V_L2Moz7&W9?UD{<KJC*5JMjFVX(HHe2C+&AsL?e6W&nWOC?KmrG|pgOn4hF7>T@
z)wr1LPi6nIebFOYQ7VyX(b4-Jm5udY3ytD=5bZ&lKA~%~JV+i;3ovj_lJpu;i%Vc^
z$qw$aux5T?A|!khi6=)Tga#O*ljEMrH0c|UEtqQP9X?vymUHslTz^j^EbJ2pt?Ndt
z10`Ofa#<Y_H9|wmAgZSrLKlzb#c@nTy1mEod?r&DSJ-^#6|o+cYT+@}UV#{rva|N<
zH9+149_E*wH2#}C7>vU~;W)SfM-Z+2c$2aL^8_(3#)+u?wVh`>^ChGHaG%EOW_N-T
zuQ*djOGV_AoiJl=_hH;ay&h&NB;5D1-O7^q%^bPs;;T^I^n+6-$vz4oy7#*N{U8Js
zYjx;#?d?qyHaVF609rcV%+Q2_6NSIxyR<4S6~BJkzsF@XU2kDC8!@Z>eyvTB&}U>=
zR-4=Z>a)>1yS>{zjRobuxh0UY`1x(S#ZJLNe?toQz4wBXCf5ala+hF#WQ1NynVE^I
zzQsV}Pxs$jmR}jm_?+w*L;vJIvd{Y)ju|>R!6H-!KQE(0B!dcP2OeMV;FlZsOPSA&
zr)RkP!p_(czzvj^dW)b=M?&Is<rfLvD^eoBm|=2nb~MbFY`Mfa!bli7UB{#aGGu+X
zp`2LMPVvHVzSl(wt<{hQvsGl789Z%v&M!yAjz(pz_gwqKOp18(SkVf}gkivt4LAS?
zXgQ$m$WhL0$)rBWi~n+Ff~~m^aBWB1@D#}W$#jJCclfCKdQCkKxzm_{67nU^u*~YB
zQvw(FuiTcKG@WSAC!YZng;^Q*?=o{}mupDGhKkf+HXk(gs_~oJ<C;J`1W`sHSvmUE
z@ZSYtNN0Uw5D~|c%Sv>5$=EmCPds59hXj}qUBE?e*yy>(kgxLOGY0+*%E7}w{<UU8
z{NOh6N%!AB22L*b!wGJ#SOo;$TI>+!wihZ6eXa}#9VRh~T_`C60A`|~fv>ba?b^Es
zXV)6N1Lt^}`1C4SL(f!EK`_Hnd>FNvP(_^;lwKjFx3yt4NlB0AJvx9@?&2iE&X80S
zCTUi(%_Piz-DloHE6I%I2A)f+L`z~GmtSvyqWZ$nge3Lrp58F16{7qEtcDZKYtr4@
zFUq8`Os2(x#wXGWwwE+KTb7?r1CZkd59sU_u~>KsPz&}AoKG%O5%u*@L%U0q`Fvt}
zfIj?v$BZc|$bW$sG;q^eZPN3jibnWAFBjqoSj*bi3O;H1YJeMDE<ny9e|H(`g-L_F
zIcneTa^fS=j*JLZ$*C>ec}NaR`T8e`Z;sRDiiu;9wzBQigF=t~Xlcc|&67YARb_gs
zPp-!^*i3iWBObny)9z_rejZQ=u^`nX)6TUPKz4(U$rVv|JODb|LMTM5wyjk9dKhOU
zA!+RgPcjLZecJB4UOH}UeM(+)<BgO61uZCzucK9MkZVT(2`(rH+IOPJSq!*3W1%2c
z7}1*g3iR{{=w`$(5kAQn@@~Vq9(+;5IPd^rOq+Rq`Zc<|f|kKS4ySUvKK1R(Kb3vi
zfZvIfcIOd!aI1dPEddxY**h6PC>HhP$F$?x=uy8S&GzJP5@A>Tl&XdC6fii>z`vt>
z`s1hXB_x&q&tm=@opRK;05=xnS&chgCd$%NV-E=bq5Lx%EO<GNGxl4=DZ2-^qBR#$
z86fRmMXPH~2ojLTp`+2oUbe+6CRf07%Ok)YN!Z^IVzUWz(vQxpIt7}LDst9a;Z$9F
zuw3U5fB2@gI?DS6eDUO3KtmqlJC_x^Yy=_{`R6W$E(%Y=K4pviZ`s*OridySY+4te
z6tU!g)d+ZaQm2>2e&qT(DHDESZ&gc0iR3j@MV5>=M&EisTiZl^@rYz*L<6xj_a<w|
z`(UxPOpX=yl?1hppTssvm1oP7DjVFQoIQd!DX+U+L=JnR561qTNGU4<4LzWJ1IGJm
z5F^AsyBIrV+b87}7}wSfxeu_O$k${+H}$>Kl7&YGATi?-b|i9Xm1Od9kl>Pf^KJIx
zcwFL+8VK5SZ%uNcs!f3F%iyt-a5l}Nv84}<uZ1u+2h^GU1vonqS@7abV`L7lF}$9W
z0yN`PTPcd<pGLpS&1;|asCYA61y$Ek9}T+h)(dSY|H4LW`F7W5pV6@*55-9DQ)COk
zN{ZDubieE1(65Q?1c-As!iEQR{%70yFZC2zQPYOk&gK7guT@7xvrm>iKea!dAz95(
z;wkhUWUSywa*j~jnda?07gR5u&ZCV2vjO=_SMSA>(puV_6^g~sKx#@#tW8DC5=@i2
z5_aA))GW3oXR+)C<CE|qSmbRtCl3BdxM^udT`#*O+wR0b?kxEz2w*xqlCK)WFP6g^
z197!%7GbjOxz2uY9rDr*8A5jjkzeH;ev5R1+M+uA2==`>pZyy0ByMML<h&+LL`V}Y
zF0-fhd<xv4i3LL0ew(<0&CMT>uM7!AB}DSK_AB2!pp)5A<Apc(qJWlD#W~GHs5BJ_
zTrlTtk!UAc6J&*+^B+3<!Dnh$-`h$$HWF>9v~t`E$@4pWWnZ`ThXL6_f;nE&KcI-v
zp##Tmgx2p_QfOrehrPfx(RXJzJis=j&HCY3r3hD&;R-nkAU$pN>7ED0KEj`yK61)j
z>PNjvL5!BAWQXnM=9DHjX^H1*r~Wt(*1z7d49co^D*4AIuoOTl4~rnsC`+EY4n#z&
z^|9o--gcnliPsU+bjI-uqQmi|s#q)ZVAG5%0K%*z3CTYER(+4p$?0$bff2=b3@?MG
zpq6gEI4939&eS|*5p4sPq-mz|j9$~OR4LCpAtk~JOH};r%|kz?mrEBIPP(bfI315_
zU#22J=<+oRKPyT}yB_jC4lsV)qV=#NkJdm%et^m1Eq3m;Nb6CC^h$(0S(Bx)z!EJ0
zU7VHjjmF&WNwz^WtL=P=N#SM5Yh#gq`4YY!4NEmFgERo$Nu5CDfT5T`YKF?OmXb$^
zu(SYQQW`YNHKvC@Z~m26D0({>bAXGHV@Giap`72n>F27(r#Vm&-rIHyR|U^pj=_K_
z*+fG*;I$bNMs||&=@{^TSsN$gcT1jCr(*g10oYJ05o+-R)xR}l8^e;<bHbfPif+@>
z^10WTrKb;J?ENyzKGp#LJZ6jKbhp_!E92Ps>~?kJZruP;&{D$$9InS7Q7s@|mNJDE
zQR-950_rMupt?h1reY6}NP#G)(MNr2la--k6zu9WyBcsyf+N&5GABd3P&}=;D&SAS
z&!V`LaVN4i_Jx{m1XuMLUsDl{byE2kOCBNCODR8wXx0?8-|CSH<oy>AS5Oi+8}=P8
zUqGwo1eCPpk^3oVgd*P<b)g4Zm}3rtW$BXHjV0Zn608Sa1)eMMU;@KrQLhUVLaYPK
zF-#2c1R|Tot8o4C->%7JGOO6RBU+<sah{3i(UIl)a_zUL)v%7kDE;AfUR3XkDW)Kp
zzF<&m9uaA6f6}18`X<MP<D!v##&qrR%Y(PN#=NM<;imCt0UwG+`&pP7tmV6haui01
zpkbOmq>J2ombsz(-KXtkUe*1kML?1?qkNaey(*;WgU-7n`xtArQDP>CgXIzx-?`{0
zB(LooQ7@EQF%>2r0t|9CS;9nFy&w(-HaVhm@7m(6!@I^-qvc2YlbI;m815EF@<2(R
z8>cQ{9?3P+52!_K`v%#qdIPnKiZU*-lx#$dhpRQNrpDVP^;K;#9mY|}3Cyh+Jn7_>
zOG1;8EahjbpB1X0uj`6>DJlXv+RyqkqK=s`2>amivxQ7iYeSsCH+EF`ex*r+k<s(k
zp6bYhal*W62q6IxJ8H19DF|0bVCQYf8$h;3ub$D0y@2MJ2+Bf~58IT8#M)$F<ew$D
z>6<}e04Kbq`73+&J^@|~fQkIbI!xC=OS0HMqNg`ZceF-6;D>*V7T<mWY3`#tjA@3H
zpd}H|tc}9~Cr-YF7<MT#@Hl}`y4-%ggK&sGn|p^uAMAscER}{an`)3Eq!CU2zr%mz
zVezbzM(3R!5BX{9vh;R<bL8K;QN6#*;cyL=Io~G2ykZ{Z`tkppJd@}G^m=%pfkz1}
zFHv)zmsxQS5BFncKdt>kYw%di6Xp1$@+c7{1hN|8d*Jn@u$LD#WNlcCdnhsl&8w5s
zKLhdR`8wn+^2&e;jJ@Dk*}S&E8{P#lKoB8RIeINcIqq-#WaZ1Ygq-dVgA;us0<6DY
z8~k8Sf{deeC}$(r^wwa+s3}(nmU;9b-%5YA9GyhdI0@pmC;BD$EIiD!?79oZqjefl
zaWj+U1^(gnxrR{~2^hYIMbqO}1$&FVh%gVzkXVJUz%b6<Jfgr-q!*AlSELJ=*w(;Y
zfFlfGl;6;206_~&5d&CR+vdzXv$@aD<)_&c+@`!89d_+I_aJ~jIG6e@nTTT}mlJgC
z{oqNe6`iwFE*qY?QJ3heahdveY(PR8NYGtpJC%cBMcKdjluPCxb}A>~qQz4v+p`gX
zCW@G^kL&BJqF+?!99<Fswe-ePMLj-d9YZ%E2C|So+Z5fJF4aB|VtpY8(m`Zo8Wv@d
z$WZ$9mfF&G$dAicw2&M$;NiENrDezk!8oxFJiU<8#B@!6Q03p5iKMU}UMA&Es(e%#
zqCEw1-?9s$Vcu^c&b-^@Mw*}*{Z!2tRuGdC<%6V85A?H;aVE(FtD2h^*5f$dm~{qY
zO?nh$5ME{~iFpSt$glTLUf#1$>0XQa);s))h<g5}?kPo!ua^@{_}=}s)>^PRz)GU7
z?EW?n=@^Y_-D!;i*^Rgj6k;)M58e$|XweX0tskLYw+a&_#3qe&ciiNW6z}d9`@@dw
zbd7-qQ-JhMD;e~yG~;V7xK#{(X_aR$>`9OutJp@1&gA`WDi&W`<__?;Y%<ET21fg?
zvNZ`q0Doa_wotc~Oo1g6wIekFAr!6X5~uYllx_$ibDldB-SKEyg4CgnPLS<0dN<u9
z<t{X|Db|=+Y<;bK7;~BNynP{)I6tp+j%MXc5w>7vCOn`<0L`>IA;3{UpCrjI%eHH<
zq&{*J(Iw5C^p=96bk~Q(L^c6YNK|;&%bNuDWMUeACyEqbcJ3)=vLXQ9vUcvcdrYUB
z3Eu@7fo_xu=EQ@yh;0#wMAu@8@3F*sRdRtLB5<qcVlf<u-HcIuvO*XN`>rMx{dT0z
zkAC(gVZA3JMGxM*bWqoqKeir#A@LM2fFGF=U3XU4Ab=m=Bb2XuyHx?24=!py5ss}s
zas^)TJ&JGMjv~8}fUI&VkRkDe77*Y6Zbjryl%+RopQC`iRLTM5pO>GJEgEa`A3@X&
zbG-$vIY=1c4^1L*F9CfwCKL)}{!mPD$$;SLp`p{cDYlSlr&0#QY0dq|dqcyBB<7(g
z>SqqqyoNp0{}|S6FK|J<J5MMp{RiL<3P!U-D{$vr*Xf#B6-$K9<x|Ca8%t0;ygWZN
ziIQT508TN|*6ahr*M3pN{-8f73T%dVEDGoXL}!*uT>Sy#a!vCr6i_O6Vi}kq`c*BX
zOF}R#5v<upgsl2LXn#b6Mq*}!CfZkQrHw<CrTTKSL^`?5<>Tw#k)NGDf-TW(ULu^`
zLH#xN2YNZq@5SFDqg_KO58_$JS+nsl+e9MCkHeJS=XpP)fyOk_^a{*RirW8A-eFp#
zOX^384?plhBr{EX;=RI=QGPf3j;C#*qQb#u$BMnwCz55mv7v@hepdasylD4)wL?z~
zmNf*{*QSSCs>`hl_IBpCW=r`a+tk2}dm{h3JxlbE6Poj&s==vJp4atSe7y<0&jVSg
zVdfB=E+uN7^07H5$R=p@BoFw}sjbiZ9VP0}fH}p|7`g=#C)hxJx}t>?!Bt`%w^Fo5
z%+S&MNXis4kx8-Lx6-D}11~#NKRLW|r$;`&SpdmuZ2T#1*ifq(_6+fX=wL?0e~l4z
zHGBE^P-L16ztnS_XAZe`6>iONv>CLwDW9bgvGc7nWo(s$M2p|C1IJlYf*JWS#bB^R
zP+w}9LnD9+S!prRgT#UGP-)D5Brgw!Y@sRsLaC$qQ~3tLx$>;YHAKWda5Kq@(Vck8
z3DSVq96%vPit7}vVf@h=Sxnd#H>GQ8U4B7Jcw7Lp{j46ZVzo+|HjyBugSF@_ziD0a
zJKzaT@T|2+SbE=M*>$X4;^>>E(7fSyCQq52*TJWE9%W{W4*L~YQjhxzVj?)6;?65+
z)U+AdJ+2am9n4p9mmj!MEva<+-daG=CAi*LZyn;H7n(wW26_%;uHQN}buJv%DD^+S
zLl(#`&YJK$qmyf$OrC!E<}Gv;-pFn0^nUE(hms2yY8eKu73GgIj_tF){%2H9GR$qg
zE1NJrQ^X4nV|L}_xx%3tk^(ioH54W&FdE?}FJX_@xSDb2RGGcPUPow~F?tZu7>I`L
z*RDSR7Hg~p-w1G3NI4Lb5F-P2xzrE8iDMq_&{_IROWQu>4rNjy(pgGbO*LE)+tS_+
zD&va(?(Yu{%P<BPUx9-XPJQj``N4rhda$bm7mv?6O^Z_k{du7(bR4`NK{Q2b^z?`&
zMMBjNcO6^2h$^Q!%|LmHZz3S(|8OknSeVqSEC26xxZ;cr=^GtKSM(OS3^sYP>NHG6
zcV?C630rF7DQR|T<9+rGY&};moY)J-_8m-e0*iwYc@J{xmBCkC=R{mcx#q(M>PEI?
z57M0n8aac_iPwv{@?6Z{Oc)^4*}e9DgDHC*o76Q=swzN0p7faO)p8tyE&{I^x$KB>
zC7%uUFN_>i+L(54uI-m;HF>O_)7&EXv!B?@qGA-)bUGZ5U<TQi*(5c2XO8CH<16=u
zsX-81lV@f61oN`Cr^>ourj?(t>n}_txZ}lWv{&8Oeu<pKGgdY^M6hx(Y{`n_I!*-E
zVR#LBB)m3uv6XNtP=r_1U6Aekl`*wP&@W%5wc-g!w#{-K5E^I(%YrQATjcFqwn<qY
zK}s;pYrKSIe)??!w|jjD^{PGSqY1-Ia)!jb_6UN(%ALJKyCF7(!r~2Am=Vyt;?93`
zg-xlhZVmI1`?{1HxlI=(>N$f#`}{i5sO2vG|IHPhBPLpg(=*qyHS7Gskvp+prWY$M
zT8<Xx=NET;OEXkNAs797F}nNY4i*El^S~0InBThU1Qdoz(jj@;1YG{^v;uME{Hpj3
zvelkc33=&SU2@{9%$AMX$^~ClXu4%CdKrqcMBC@bC1}16kITf_LRYUy=i(?=)aQg<
zVbI;f^+livgP*Nhh(lT_#Gzt$jwl8aLYA#=ZQ!Kp&*{(TH)lMtvGkV}H}ob$Ka+$Z
z7`wS{CzW`*poOno07BBZ^+wiQF4-m3ABj@jwR~)WKNQy`lko=N@I+GAIZYkOJu8WS
z*@KGDx;;q<4N75lL=iLmU5<eVTAuM^e4cw>A<iMsziP#^xibpoyc6XmPl@Qfx)&aj
zFgp&G(UjcE{U#Nli!fqw@MHG)3Q38(4b&@#<vr+rUe`o_yzsFO+Y4Wp(E}7#P{7Id
zc%p{T!8`Px^gNxFE!eaOiPiU)IwlJS8J;&2p4Y@3@YH%sFqy_fnj>7b(0ZDg)q_^`
z^*_M4o-!MW#Mpv)q+b~0EbJ|Z*1*4inT~nH(ici1*rk41SM=J_QU@tXj0RE?f0xA+
zf;$6c=0zIT=zWbg43cS_pHDxIPrb8*M+4>0-Lx+1N*0**NaicqM13@;M=e|;8&4wU
z(3q+`vj00Fz(*jtOiQ!=gV%u*1;>EkK$CbQOiE2i=4(VsUd$UQo2l4Xf38moDt^!?
zG<YTpcYRz$HY>!jnqt3m{)Ya~*sd$SSEg5%m^Zl$f75D)8H>ZL+YKNok`Ve&t|wpP
zo5Y(M0#wBav<^!c3%3I1um9RdS0|yol1F{@c*gZ1m#)t6(%jx~)9Mj}{ptP9HQJj<
z+<!<>P)>FGN|(5+jcYHfb)u4s%ulz(@sC!4nV>^D5&)aEh_ZL4q!-K+&G+*b4C|)7
zDM?{CkXju5p|9#n#<~~Zx=ML^v&&bVnm2^T(|{N|NVLJFQFD~mvhIo1m?D`;Gc)iD
zPkbb)Pp5|7AG~=_${mLmVu}fr*Wbq@!NprHz5ziQJ2mcm7Lt}Z&qMC4cOuq9xv*(0
z8p>kq{$R!P9<uPJH$J17L9}v2M+lYE0VCPw%*k`E4L>KozN@GP&zm9UN?h^a^4R5+
zt5*X*<E#ooA1piAVl-#Qlp$F_!v+ll%RH9TEjH}JS#$7ie0B>duS?wgg8?Z%n32o3
zpp{F7u*xge1acAUv07Z#GIoL*ATLo}<c5+_jJ}IXHnb6kZXFqzEa)Doezi8}3JS(U
z8p(yK)38yLl4yNZs}?V)8J4xd%Qnssiq$599azw@6C6*|y6i@zde1-bKU4-8WCn66
zK!KtBM}>OGytla-KEKiMGz1~OyEkKvMW0LQchD1^cr_fstgyx}01#eIO+@!GDSZh{
zi-)~{7|2zom<r```Rfl7v6g_-V^IeGKY<q(F%#IE*PPX!oipc3{*I+(&9SyewiajU
zA-U1Xo&<P(?P5(Fj|SJh5716-Z=7itW5NK5*W=b0$U<m}x7nXin!fO7iW;((?rXwF
z-OB$f**P_9`1W7f?$pUunSgoU`yo#lalRVCHI>AfppVPF&UuHj5v4HAE~z1!o}s<g
zr19SFt801X)`7d|$-L3;gw%9;_AB^<5%y&j+Wq6G`M*n|fowLxg}94CFW04Ne`eoP
zuV5t9de}_2nJTY1Nxa^cJZ-g+gwG8S{EYQft^H3DAtXzA{R4Nm%zgv5FXuxcVTOO*
zO1iKD3b2F!h>jc4ArZON0!H@~sn6}gsGUDdI?ejcpJG-9c%Phzg?pMzhevB_HqzZX
z01Le8ga-jLE$CPF5+ZIsOnf>lhakvwj82{1RHK9gVq~pM{dU4MY)SY^ffxrA4O<~d
ztqGVKc#EO<21;oNMqIp3mP`9gmkyjyqEDrJC9E!0tezM=adj%*9ThrC4Jc*X!q|I&
zI>J<lENp+r16<uFdy05+(;^Cu=}UDl@10)5G<!_TWresT0HV6A%zoZ-S)u=RduHKO
zvYnyxFhJBK%a1k=010$eVx)`%G*ezay&S;#xBc3K%C$jxjUhQp{VLR!oL3cCM+9_O
z<-GXk+e5xv)k`J6(291eQSk?Kpch-AtssSZ&Ba&$c+i?5(afRn8{ycZ&!(ix@F6?E
zFEx{E`C#j;JJgbGC++_N`9J$(?XB{p|GQm->X?@vt7UMd%R_st?~x&r;X5>#*i9d5
zui;^?MQmlDDY`AQI;eeXXRHu_>AyoH^yhen&J{ce2DY-Bp&wBGU5Anyp~tBaa@ql@
z>i}-R4%w!${=@&ZJ-5_-Cqi2L$$D3(=hfBKTRgB%>x%D+7E#vjbndiHDWy?NGnS-B
zkv!>U|Lh4&>s+UxFVC5X^7s$Zm`a8tZ}tHHVG@1-GYqOBZlUc;oKFcM?z4c?7ztGM
zC)49r_<5O`Hd6~3f6wBw+^7=RgjnYSN&40njs`o~Let1(<CZHm-;^4-XoA`XyZVvH
zrMF9lL+oRyd;jqX4necLM<=E|9P8cQxZN6rLYDW`mbBeDZhtdf`}ghHI~e+86E3z{
z2usWT8+@;oKR_3AmHiY)b9LpcQo=YnCUc0iV(HKj*PZ?tVzjl-7OhFr_><qW?N|QP
zint_J86}bO@-%IJTIUYv(2t=e4I4Yo;=jAGEdN35bsQvCx8muI<l<C{VJq5P72R`o
zjtkIbta~-g;^|PZc2$0)er6uoUV{2{LEXvpTaz(uXw+$&;~G^!yzMJEgL$NG9Ae!h
z`6!zePuP=vF@hmLXWbm<wcJ2J`sDMGh+8KuE`@2NY(jK@W!ObUU3gOw5EwNRGM%kf
zKYH?z%cy5Idf~@CU4{(RH@(D8b83UDdo7@qz8EcpGXVokvs18#D0_ku1a#fyh+gvb
zrXT|P42{to9UC-I?f9z)fbgUq>UWmQjemcLx!_;sc5GFi4?bSvW`VZXvOF!327*_C
zG~HrMvk9u7KzwIn<u7XgfR?`0l>~|7OShC78jfz$XLM}$*!8@US`2#KiwwA9Uv`Aw
zlWo@Z68f?@5WR@d+S+nu-7D35e{zf^E5o?IqO9-r*@q#h-5jOW<se^Y3oNdxcrG>P
zo0Ic`*X1l}M4@3tdbDX1bL}>~=QsdxH5NCg2;GPf#;s`OaEONO9caFVm%+uHDr=9+
zKS8yP>@4!A+;KwAd^`V%c$d5xgog5z2(S7hYTv2p{eU9AY%wvV5$t02MY388l%6{`
z0M+=ZZ7WRvwp%~*n2`}bQL$GB_EbxyUZ4Yd78*GQ<H(*!0%+^t1&V!$guj(_ZfKgS
zWW5WjI0`Mb--gQ*dQY}VVTrc7S{{>lSwx~k2)5n2w&uGHsY(?1%Qo8NPM+nwXNnXZ
zCx$Lk(DWydIFA8K{F={_q^$NtMTo574z>WZqxB|XL76&N3WW!sEPq0vK+SosJu+<l
z^)#E`k$ubQs6M+z$N6tko+TW2thwub6Aq^8IlG`OPl~?I_Db>XGme+c(bwYSyQ>>x
z8YGeIcD97AIr2tlDG{&RSI2XE0HS}>Q+nnf=`H`iwuMoq4-_JnXd$lw?j+1p%v_r;
zpm)f94?dJOX~9%%I<6J1dpfoW4yB9@%pItWgaxl=&#eIY$oNr1Hx(Y@Rt^P}^j^FZ
zhXS~JTJ(H{sTW(7Lm2NdDjuH@T?2aCRkn~(mEYmo-dk%Vp@a(Rf2KA6b--9M=tOeX
zH1OC7mev}Wrkv5ibxf~UM~|IfwM7elxUYAqpw}@sp5`Q!5Y_z;+h*Ahx{0)Hh&+^7
zoq$f;9U7E|*bS8pKx77Y8z^cJZseMf)qZOD4>`(o!i#kOFOPW~iMlpwrK#5<@9n=i
z_>2l$+KWjl1|gsUOJF{0t2x0op1^hza|p~M4h4xCOX=CWuZ(*>RE*|TD_M_oSPuJe
zPl4t*?;6QY^Zcw`3Bd=KIvyKl<Ww1<439<R6_W&j)V;X}JFcqF=`n%z4IK%Su~YN*
zLtVlh43jS+D#<yybJTxgg@5%q%3$VrvnOHk4WGf^q}Gf41QSQE;38-9HhZT!qFK48
z#y3=29M`u$(W|$`1~Bl0w(`iX8$wWU7%gStPr4<pX23+-hMTmMK~Wb18fH)vI&7$$
zD|K(5XQTIpc1r}9YOU&(Q~yK=XBHvqUHkbP<bq~V`Pfph+BDCAUgla4F`J3JWHuN+
z|JCa*=fwUcf>6BAkpxxeJwtW6AH{*ftJ+CFVH<bliY`|FI#{2NN%LzSA`>5%mY+M7
zp>as{JgeRjg#t<{ugZw*9=(yyv5b^3Z}LkQiJ(#Xj%JrBenN+)YS@uqUmCEpPx|H|
zkSXD!ft2<G$q$7jsVmY_XX*4k7BlT|Kd}(3p$(@sHr8Y=uRnH8t|OJ9HECSfO*ILi
zX|X@AtiFg~{rgGbMlthdt#=nrK0mE~{X04J|I-g#pa9A&OO>C6S7<JWK~_p~%{mvL
z%$`-Z7KhG+-!v<WU9_C&<A3JYpN4<K5^Di<JL=oC28FmWosI_U11O<Vxz)dG0dMg-
zs^@L?>K5~0U@?FsdM?kFb;ko(t%>MGKM*ezE!5UAujB$h+g^qZJSK78BGhy^n7?5X
zOxFgZKk=);^fzwqGlmU}PibLLXG|D0tyohEV7axj4p1KLE=Ga5DdhLFtQ1ET{}hS*
z?L7~snxYMCP8Arw-9dff{gDZMvr;9EObG}~@?Aa_2`|voPeQ&ft*Uvl^;zgRp`E;m
zE1$!lb#jFvq!`PC=?-fze;;c(!N>YP+}!`PvE)>hZwU1JK{^^Nx_v>vRIMcdeec#T
z{J86Ad%sf?(Q4@QqMpuiRh*dbMzjVj``0P|Ts>_d`43Q9(h9GeOiV{(NI!`KDI{&?
zdXB`QnjGQ|&+cwSx$y+NA-xvMs4({b`AE()MN<e@s*7PYrR(ZWs+`zF9Z4feU{Z{}
zEdZ0=Nu9?$#M{vVgOjJ>oRbSS5h%^N+a50vTsmBGhO{UqA0^Eq4`!D%f(&~b_o~2n
zUz=o-EcuE_@aBv9mg|_l2kusE_Z`ag!7uKoUv#p_USR)fvk<t@s%VGbzlVNwHCadE
z>Yb7(=v<wvBZ0B!53|7dtf=&Lpo#x7L@GURi&^%90Ux48ASdWZ^gVkbJg^%33a)4G
z0KS4Wlj3?2E@ddMb>CJ+iQ1sWQbq}R{`BB2o`c7KO4#9GWx$HK%rr%6)N5orWZx(7
z*@_J*QfYG60A`Mt#{fY<zQ3*Zud$uasCPx&OjYzwRt+<Bm6^Z#cJRZ$qTvZ8YpTAr
z0siVb;ssK~wDYUjykQe<$&l-)DV*ndy=%yUN7H&nDOO~p;qffecf74ltHc-LzpY%a
zBm?btqpFn5Zw%a_VZ98g`2?U7Gjh8;?Spi8&YB@hf%~F>A?q2osl?fhX2<q}S5Lq&
zC!R44*htU{Xac~j_Mr8>d?<{TRk=N+^oY4?WqSf<){gy|Aw-+9$~aW=(A@v0M(IJM
zAa(p~ABQ0Mg~|&thMCUT1a+;N5Bt06)?QaFC8zR)hFcQGPyF~_-+PPXj`+!>X$^JI
zhjdSosTYc6nt^QR^RpzM7O1x2uW1+?O&I|1XG2yCo1jpx;sV;WW?)RB?kCbAK`i~8
zt<G3kKh6$DGZ`Z~X%&79-lnp{i1*BR3mv0ryz<Ekfek&(igLBvQV6GP*lnM8yVOO^
zDu{c`M_mKS=TSc5s!J^4IT2R$M=Bw(rCCs@@WYh`{b)630s*>BrGF8QlS?7^Dsy~m
zrK%+dgZk1yx=dGOz1$EeYyMINYt~nA(?FPxO%tWX82S(FzK>?t6!l5>0Ed3tEiSxL
zCEtoSe>(I*Hb0_VqzIYy<xbEn2W+^=BUUgL%DSj#5-BkGA_Q3@qb7yrC%&+8h#DNR
zDO%O>6b6oBdWT!za(`^6ZU**TtIuxaj`XS@tuis60ci_JRcO5)$tLGTO<r6O(Gd*B
zEN>0}1ybM5iA$~=trpCWoj(2q>FM!>l@j_M`u99RLrTC%Gv+=po+%oZm_Tojjq>V$
z1e>#HeGaY&G59$7`v%z)??wKG4gm1|bm-B;=&9|<=zeK~esAQUc=WO0_U5fGf}+hT
zRS<5exOK9~Xp{!o-5ze@`Q(6g&y8v*#zCLKKal&jKtM9R%gMSsm0$Ouih(~RZo}Fj
z+1!u-=xIrH=lZq_YSe<8kzy&^_Y2Olz`FCZ!G$$Qxa@YNX3ISwnJF0vqN%^m)FKf`
za`@Q6W%j8-TE!IZ2WTEFt$!v(g#wd#3VkO;vPTMlzMel>>3>U(mg%SCm@q_Vl{<9G
z2&?v)UWgevN%oOn?IJ8l`dVznx|brNR*z~<%2qa(Y$7(7Z)oeI*`q(Q#<2bF=z2=7
zYcN<4yB#mfo!SXxyOb>^pTJu3%eCaQ8OW0i<>l$XR>gtq<%z?TRx{5FJ~;WO=Jyvo
zBKGO`Bx(YZ!wAZ(V~i@7PvW%fwS(dpHRvVbm-pVWOJ8R8RcyTvEVA~w=O6vN`kG(5
z91=Jk96&##KuaZ?tdWNuAuBV76aQDNy?zuE`~D|20lSP7+_IwDL}CY`^q$8VihJ57
zAj|LKfwl3DLQD|9q?lmJbE$X5beRfqdHCpYu~w{e0_z4aN2;k9QsL_yI=K4@f9Pi3
zQBdEuO^oPEY0|vzGOJVx4c~iZNU3u2D`w;FV;J8Gs(?W<()mJhg|2B79d?z7C6yn?
zg8IAq5WXnHP-QKPuTtwL2kp(-v0fP^05tJ*JOO7}(^=*~sh~X~ThHY5SOk)Xw$&9A
z_!+%tU5@+u9F|&95@_gpH0hOq{w*x8AnztznJNSez^EdOI}E{7a&-k4S)ELFQbZO7
zARPb=sDrM{vvS{Qp!m{-r6BfINClR(VGv#>XVfM-rh}e=Ln+-jO}c27%{l`eLlyEC
zB$o}#%?{W9K&RRy^+9ZFrbfZ>MXWAgv#vc9Wn<=*^@h;I(9H$imL((>3HOEWkR&vO
z0YVQAHwET)8(VZzNj)_=5jY<0c@=$%T+4WoKf#M;x$4?0j!7E6brDo$)Z7h=mZisD
zTshBbmz746+sV!do9xx#FHt(?+yx9}#q^xP8DY;DIwa3Ni8hmYxWAQ6o3RU{nW#TA
z%e;P|vv?m+1vE$wyA}CqzClB&)D8BIE5=Z`Y1$y%9Gr`jyEVs_SZ>&>(Qe-oo5O2T
zhzuz*5i16zaTWLOSEz_Y#&WKRSeEC)y_0n&BT>?T)lV1OuiC54JX{(HTsE)B4t7&U
z<YV!|;q5@H$G5pz>#A1*E2q9s^q$tcncG%has-u<F8gW@a&yDC;stykbNOe0!hGc7
zk5UDNGL7%`-4IuDYyNW$XZ<i&VA01Ph#pXfP^``1c3Lj|oK`GtGzl@L!d^V~bpNMg
z(ZhX7X=PieGD1qLa!XMM;*}4noJUJn3gV6Gh76YP9uau2;91yW<}D~35Q_RhR9~{g
zfwW9gkwq@v9|!I+KDz~{BYXZ{6{{6=!ir6iWg(+pn9)oMWwPggpZ$wT#4s>FDQkd9
zxW9Hp<N@#X^J=nDt-0*h&_Sj(AhNd$y0&B~fE?bmCLPF)E)DcGTu4cEc|z8vG6i3{
z^2?Zx^>2(1Wt9tQO4%hvSCiXPoCWk8bJA>31o7t_cxL9E7ip-n_n{za-^oWi^hRO8
z9$cM|qEym>bTEATo>bEA7h_gVEYNZ?aocZf<QtjKUrFFzdkUsmRA?=7Rn|($QJq!B
zHfZ2N<QGd8;OrFsWr`L?{8zV*g?^^Sr-wwz5ed0Y9s6tm0QS-(753=x5wBjyiB#SH
zC=(=mkA?WBCWRd*5U`}D$jAQ8A2Y_%Ymq*=;JA6WGH;$ia-Gt)+k;pVn`tDFAmgtE
znnEcZ(UCe)rh-YJ>a5+0cj&+8An34`oOfllt=%PiB8$<lBYRexfCvMdmSu%n7&qwe
z0;Ywo`#_mEbb;ialtu-ebF5v?62;VPN#6$~KV|aN<hF<ZCPVq7IN7%Fr39A=SP{&v
zw(iDl!Tpm=Jd1<R{F1~CFPek2YKon3++)`O<KM@{k6K@z2Y761dMGEQ6wC9NIMi5Z
zKFNRuh|&`i!qph7EgM~*)QX~>$&jm@B3UbQB<dtK#)G=_(((*hq<ss6a&tyVIi3+t
zlXl21fKmQBvvnXlqY7fBVC{*eVE5wP8J@2OAZ>Z?)#WZ|F|@HkJ*6|5sWx7?A;Evu
zJhUR%KJp**Ibg3|4M0Ew0My&-nyhH`1UyZB-Qdy>?mbL!O({|Y<Ew)`y^$`%t-++5
z?E&!Jzbr<9u=zOp-0Q#K;ioDEZf=z@8<dTQkc{k#CBoMG^AS3&zFU~n>V@y@Bag(c
zFgqa8s{TX?1N4se;<O*g?Ct=8K~ee%^XBFJ(6lmh+kK$a!Cg#K^?(if;cZpP(3t}C
zK2o(5{kZ536&icc=%y>sr0S=K&8e=Mh>r^cS-H7mP5roa$r&pfJ_T7-#@kuClQTRq
z`t)~R^0Jv><az#TginDGqI<F%!+P|ef$)sOG}{694KD#ud1_;O_=g}CD~xfq?b(u}
zFy+p6DJdwX1KO4|>bUcdfM*RRe;p<S{Yc)wqbez1_@fq0JRa!bYxt0uQ9(Byjy1oP
zGT8$V9Ux7*3{3D=DXH5?cI4J}&QhldEt*ExGW*C>vY!Y)y|5Yj?tQR#jTfX}&oe&i
z1J73eQ#$abka9+`shRydv$K#VKA<KKD-D;;+=8%e20qRo#9mIa`C460;XVBYHu%zZ
zp=kw(u~X2?^1=xhCoYBct>S$RJaxG44p+!_aCVqyN4Ch74DL6=RCFIe9Eof6e*INB
z^58HKAJc4|l^TlzO?_PVf>&7s;=zWpb((^UJz(dK3vI(7vo^5LHI1QSk}+8BYOm(0
zW$F+={3n8sFL9g##s`sAlEG0>o6_H>jFvYAUPD15!Y%s#*5%<Wy%H%b6ezvrh*jWG
zxH|=PhIt%z$$Sv$vy7>wnk10O!6paIQ;jA4f#n~N_IZJqD&1&PX>l|hX1WY<FfrFn
z>3!B@0Y%dYro21fL}6Y?NDFfbd^Z8k4ymh05s`_Uzkm9O>MdRt?Ve^+z?_JMx}*Z)
z2F2-3EpzUL+s2@*K)Fvb?Obo)e-wM;f{=nOOxo#cjm|UmJjT*A3OQi)D^|mu19V4@
z)j+iZJ~mIJXTcSZTg-e8GN*u#G_Y^vvxdW+=MWpP*@uCXkjCF*`%ew7(2*22wUY*<
zAZ6{-GC7=nDCFrY6B_TmCrq`iD%DIlHVwzpTay2mQo-#0P6i`p21bI-G&!ktJU)2B
zZ)gz-W2dXG5ZV}fVxflQ4bG&9M}SsWqA=foRmEs?Vs4M>XV8G3)5n!7_6`^Ku#_h-
zf(C%GPkP?<v-8YvI8GV(Zs?LXpsjCZ?Mgx9d#`^l{f?7-Xd|eJMlqM<eVvxWUXH)5
zC~jadLh^U5enF6uIIl=AQ_dmWn)?_|vpGzTo<`H$x}V;uLa+7EKX59(X$YgvcG%K3
z)PX})6+CYB-Lc@KtW><TD0l}C@vzk26ILB6j|=yeUxTip17T)7xYu%YLEDE=i4>eO
z6>OZHCW!A8WhkzPP?O0eu>OVqB4J`vsw7{&HJ)8m#w6ZJV5r=p<wJSPt{FF3IhPMl
zFZeMij>@jWF4-@`%93wHs#UPWtfErsR`#O*h`}361WNH*h?;X)qnBu_1*H{r85Fs{
zG5<d+L?L=XXcPqY=l?&P+FNl3Vr%ws))7TOpr9MkS)~h2R5k)hOFzu*lJC5oP>zCW
z3XShSDA@l!hxFMU2cMcoOP#+&y_{2dk6nt3a!G$WCs(y_b8*}MpE)D{?9AfbsrIL%
zWmZ0GKTNMzlwShf7w;Yx)sKs&UzV~i^^@a|)+;kv>=d7Yu{c)HzdT|WDg+c8ZW%L)
zF>YXPh8QFShQ%5(w-VSmKRrJvV*PXy(9kcIZvK6jNj4Wi{U@CZV*_?K5d{H@IC+X8
zfr%Y^9&v6gk$iaX9F`m%^F?a19aV)l1lfq3pNCS=@-~N4_vXzn8H)h0uNlJ$Z@vbn
zK^&fFEQ`}izehz1R}B?Ss&hE`f^adMBA6Gvy;p_`CK$xart2CWQ;R;467~;aCIHkc
zoCy9Ct|fI9YE(%3RPHoYh{l69C$9AC^t{a+(YcMaE6Z8lteVFjH0j-Y%M*rm0Lz6W
zhGvr*PBeOU02n=olVrl(Sp=6Q()YR6j}C1K<KG|+aH=P|fg}j8KnlcMDtJh-+N*bp
zR($47<=ZThf~AA8bt<3E;Yi9&e7wdH*N|wbK9Mw^XH67VTd`2-UuICz2?@G2ld*W&
z*VW;Cg`Bldh9p%BL^{a|Lhr|<{yrY5BVx`SuzzEFG*GRTGj#)ULJSzQ@8siv5j!ZL
zQ`$xtvPP0FDb-<fDse`DT3q^t10A$g&!2SRz(%1A+P|TCF9*R<y;&Z)lesE*Xu&Jy
zt&2ZLwk0K3^DqP@I=Y?F!!;671-pS~@ay;CN4p;z%}38{-JxuGUl3(DK<W<lW2A6c
zd%?|>o+9c(jTe8Rckf=lt6tqz?Q{2aIH{qqg+AxR2H53M1ioS_%SCVx7F1C+4s=86
z<jw{(w+^SeH)Sh3y^{F=$6s~btuar*tbIIC9B|DJONZWet=j48+f>8*aP*vzI{=rX
z?)iPi7*6gp0-$r2paIBG7r_04(TzO~8ddARHa>xF(q6uQhM%@Um??STgU!Q}wx`b|
z(5opj#|`%ujAr^!8S4_d4p#Gh4^}(S6O<>oGvO-;Bj`Q<;~n!w>4L+l65(D1wlcsX
z*iOLrX?=s#zFMZZkdWbOLCtFdSVVY;z|nFM1SGRB&`|G(8AmfrGH@4$SDq;JdoBxP
z@f+ir1l1o%S;XApvmE1UU<&*MZXe0?YpQsh<+L5mupSo;PDik5z!i-&U=Lu9X~K9{
zA&m8Kppy@U;G#{!Mj|hnY4qB#=oz;i{&eSu?TalPcl6RpNu~G0tDP7orJ<(d)fJW-
z=Or0y2t3TI`#R>dd5~!(bQ=Lo6xml3V^^3zkJG5=J<g;`!A?^8DL1YhE@#f(l9#Jz
ztOp2TJ!sB1$GOYY?wR!Wn~5O*9jdJJ@}_oOW1nN|u#o$Hka~ofMQeDa)iOmG<jyQ6
z2m}+PQ{I?o;qJ|J919Gui$?k34BG(=X1ib>S2#T~Ojs3d?Nr*3wX?Xo^hZ@2|H6bk
z*L~0t?N~^y5>T400#quX$5e@3NJYxuhFE8Icq?rXa+MOmpC66E`Ra?D2$5$3I}G1Z
zXU&^)t@&vF+qTi^LwDKPS6_lq)F*EAzxLy&rH_-MREJjqY;zO=2qw~E5%Yf&=F?v;
z5OJzg8G-*2;UVZ~;J*Y(P~yF+AU5hswFpf9;?RxH!ZJPp0MStbo2a-zmq(+DAui6|
z+rr#H@%N}MWn_266eYmMu&0zwPJfy7@+^(88~RfNQaEqVM)OKP@qp{wnwXit#6`ND
zaaYA{j`fk+LfRtNg~R4eLO6M1w$tKCgoHK8+lM}y?Yi_1IVQ|8FK|)Vu!9OfO0F6a
z#9TO;>Sqif@`OktQ&YVIG1p4Ul>9P|uCM^{@RpA;WNSGZh+7h?WlUmXn=CAW^}t4r
z5Jq7%g_AfxA05@195#LtpfUX=41CAh>s>s3eUIYHt-aULrSy2_3Ahc4x?a<lct%w0
z{ff)TXuXsGg<!Z660hQ2CRykciyiKY^i}zUf8S_N4IH{XL)r692)?+%vR)JI?uw!v
zh$mlz$dEutJ%DBf9zU`GL5-V4-=Ub@eU)iQ1iI2Phw$ORf_kB)Z%93_DNczy5Ss^R
zSOzI>Dr^IUd-%E9sh``v8hkM-o1S2&IES=vR^qdz5@}6##KNljDR2~95MLzxf7rJr
zvJ|Z3zEC?sNz4LUr0Fig^66p))`^`mc}!hfu94*wU1kK~GrfQ|()+Jn4Qk7O-bGM?
z5>FEt;W!LHfQC>Su_PiXbT@eXS&GqM=kz=hA7l7cF5DOkIy2m+Q1x!<98>xuvDAq(
zRMwS%*8c{j5HYp+uVvR1Xpl=n#mJew7@ReAjUHzxgD(FdRX-$du%oTh;HGK^HAdlu
z>0RQ=b=F-U5OT8zxq67lb<Ow<gvaA;z`EM~J0iL}Ve>kq(^qbraqm89NLX(}sRp*N
zuNkH>EsAHXq$H_+(5J_VWZj&hX{>8K&v!8#r8aA$4e8y16y6(INLh*TXO2h-K!OW>
zPYD*lB}773dnqsthdLYA(Ad|NEry+7pn4&7{F;QhA~XR5@u#|HE&WwrF|r<UXuLdp
zDR%hYNGFr$81_fgE{+jMHy;fv&0J)LVsM8I#aI%<1>S=fuql)4wUh=6@z$l>D4$HG
zZ(oqd4dj~Gc9%5sIEPH<@ZcM64p#tbP&&IxhSiYudwl9(tUC-0B|l1LwQ~lc@2WHo
zZ=@r|4S5pl`ezG?`H!9fiSvFEXBbnb1~EzQ*#eY6{S#1+fC)s{cR#bm#YCV_#{O{g
zzv0AGy22GB3ls;3l2|CYBndQOn`t?#g;NYJbV>48Mf2Qh?za>M*HtqxIM*u2h=#48
zi4N}5P`BhKe0PFc(?iFnUea!(JSfAg4{ChSVe)|foDB|MnYa@oQsS4q*!M>OdfQ*d
zeAR)im}PizJyuNSps}2n4v4neT-_SXe2x4E7WetWX2!DcnF7H*{GZD0LOe7g`WH`6
zTx%)NydPa5`btjGA0^uzKPz_B%4>N|#q(1n=BD71Qmfu!Ec+tNo-5j_H+I<;4E=}?
zvvw4v%dxZ_YJGE3SQVeCU<$2={6o7e$F_iJO@rguR9utlO<y<jzX_g0l#uNCR(j>>
z91LC?nLDFsY#q3VhheG9nVp+LMrf3Dq4|n0_%~r^j*<RWau9<0zdU8hz3b9FR+BP0
zhl5%`3s(#CE>Vg_D>-|Dn-fP>Vfesi-G88qa-)Z{*Cw71w%?Bz-EmZadm<3L2nbU5
z*iK`00i+_nwl;I<xqYj+HID|)kjK1b!w@-M+xvWSAMnV_==k#I0&GcZl-PK361#cC
zQvQvXvT3Dv_QeHKp!s782~co-(BrCD1GnI*N;NJU%Iphp&KQ1Xqj=C7g!*ic6iGBH
zZUkHzR%I+j-eZ^;eCJCAlUd3Tq*{Hw48)>KAmCL8^c`U%0_RMKi}88yeVz9)G&|MC
zF0&R~7v7V*#9)J!YoHI=e;}`S9Axc{swrbLWeO5&y+!RyPg8p%!?0mcPKfCe{}n$r
ziH}c_+F-zD)0hRTJ)>R0uJRf8ph{jjH71?Wb&JK)>*0JnXt2h~U$i1Ks&>7lTOZ7=
zUn~2F4Ac2k|HA4{T0Blm0l})c4Fe#7*8wOTCl1oT;2;@q+9q+fm&y<}ufvS(7V966
zbwIN0_s=dvylU{*!stQR@<xu!i-cia6qtA55eX|jn9q^HcX#gS<(}qJ;Zbb;ZLQOR
z5krIK_ScdF(IYm<XV-<Z0S{|v(zayweqRtr1%Om={Q?dkVkXjo*D}Yy!cpQf#YwPm
zKDUyyc?5H#8!Nxs_tU~VK8nww0Ib(pFtY#Gch#6?d2JjaE%@vU1}Jou!K;UX1t?t{
z16{4quX@g@R<}US^_e6iWM*=0ngU4BUAAxz-du?Zac*(*SQ)vgP({j#5Dq=aQ9_Yn
zmeu`*#3Jm^!`3#U527PV%-75thv(Btqx(Eo4}45ue59PVCHyX9a2SlyCU&R>9wdxp
zGHSk74IhM$4XkmPnkaugEOglE<bCmV#2x*&;(Y+6gCX1wWMq~TwpyQD6W<AOWCaz&
zPQB`CJf{H1)K7so?>^vW))rXoR!OZE?+O9X`?9e~YuduWYuLM<cn0t7EvAkXk@~1D
zE}gczng<M0)wiVlpBMfk)4NRhrk(Cumoy-6yalMqG)&A3<#tQGL~T?hnMYf*P$oL{
z?g*V?q*~YlAkw9=$?*m)(}h0&8TsgnHJm6)EWF=$!)g5tk%Ckl180t&5jgIbh=(*{
zsdsiVT`E=zPLK4rkB<}H32^g%W3nRp1_e%NA<`yuV03*BN(*Tx#9v#B)Hm^~%o6a}
z**ZShJLhOa$=RsEPZAn~CR@Jriw^q}luQn+!1@_yD1*UtQ?e$n7vokxUDYo|2MPRJ
zS*Bzz(Y$J;Rp$cMX4egVC*ocPqpHec4r}mW?~{b;Um6&bR0+j5Tieoj-H{G4FIvWy
zKVy=cSO`Oay8NPmv1v@g#28AI;J^L$+{YTVgx2rn@Ig1XG4kKL(38Zuj-_Wh@m})K
zH8H5(Qcrg<sYRB-L(JS?R!6!Pe*ons3e|(k(t;;PWuY*E9C|>1gb4BJVz%-eaM;78
zxysJ_HUi5CzhdzVm|cK(<FN+bS4+;dI&xr^Hs23NhcQ-&vg5uDTZ0l7aja?c`Fl%7
zCP=b1n87WM7-@jq<7~z#3j%x-9t+@pGCQ%$?vO=!HO8BR`^C<3l-;$kJyXXE^AHf`
zHZ#)7DXL__%7_0g6$XQ2(4p?#5<8W?+$zXe_qUbo=9TJOwt{mz>)pZlQ@@1Hgt#85
zm5AityPthhA656UgCjS|rn6fo)ZmbuFQg0XwWz)gEif=q{}bCEdq7eq9(X%%4Hd0O
zSg$v6mI1p4u}I;|TPjn&sYA{)&}q4B$l9I-M7Ex7F6%07DWDJ2a+J=|ytsCUg^LqL
z5eX83E5E>QGPPvH2SxiFu@lbiDr6^sL}=KV*3?6+u>~AGgtx-rqC;`Crl{b4mti9D
zj}LV+;bUyenZCmU>0noR<-S8Wo~pE?6uj@oU8M<@jq4KaU)8>-j5uKH+%_B`5+J;L
zuz6_kB8#^yDO^;w#d((rCDfUX;zkSCavITe%=bi%XtG-J<&*)>Hx{^Be}Z!*1hxJ=
z@Kfi&fZDqqGxc%2+Xp|Mxi{XP5FX2)>WxJ4dWYK``rPSaqUCYV#-URZsSuX}<QxZ^
z?da~^fP$;30|BK@cP;(dY=Y#cYrpOm?UZQXzA85tm9ott1hC4OTX2z+Tu@gN^}09c
zs^nusBiEcAyJKTfiB)r`IZ`Ori8{@aGD}X#Xwl03cRF|<h{kA|P^`ZQ*Bt_8N06ou
zj<%JPZr=)h%>xAqk~n{--8mBanpYlf*-D5K2LNgpjvQ3<=tOpFFG86iU7a8^;AE(y
zgC|`cJH|RAQkIAt_vuQ8ybgVO?V;bVWz}n)P%kPyxn8OjRXpVFbw9-)3Oqzjt?o)t
zuv~RI1Tw58)emmBW@$rmo`TA3aK*QEl!j1yt*q>h5B-bqH~)8i>er3iGVE@{N@Ue#
zxt!-Mg%Drr5$E2g1byy`LPLPqc1R9<8gzTU`H17jiPrjii@J5(*Hn{4WfOvCX5H@v
zof@dA6>HR=24JVj^$i(rWkN)wzE@lv%OzJH;nKOirVgCZx0Q_7vjv?9TR#jWcQ)RT
zkDaclzDSL{bftRG(|w8J_QRXj29B@FtV83^f5(uL<b)IEv}Bo&V%Ac%vS2Z}48JGu
zp2){43pn%U=@kR$z+G9=es@}dS0J(y1wY$s_3!rd?|g0^uZgb9{p%nab1B<6rn5rO
z0Fyp5@Zx{=4^vl&I*6`4@w#>iUbC%i#-U1<zgCN?HI2RI2C3?0#6>53CCX<TXXr?q
z+<u>aGRlYL=JNm;z`g4g8;7*_zh(pO6tTocF>me3)8sECBN;c7<R_P=B@e&9MWvlK
z*X*>(icrYPwU}I^YR4(&vpGj-*Eh4V<sFKIIs!}zy^?T0K?|sh>Le(E-`Qz$mOXO0
zFamNqykh3)Dr;ngQg<Ug6`x)4P4rt5!OE~@EHPpCYxfc-T#RZRuaC11JYE5zd?9M0
zjXtJyADl>qP#?D8FR$JSr)MiSvP}SRY-oU@PdM5xWYMjic~BzVryP{zUc7o)=D!9L
zuYjJKH`@2mFVBM&5eUy9CMuB(Q|CNL4ivIu+A@CHBQXso$<5*=|94>gS{7+&Y~j6A
zJ<v>MnJXn!Gw*~&U2W4_VMmOmNDb9pe#Delt*SyeCvHF~QTnulxog7sqp^dA`|mfG
zrZtl6@7h+V+0CG)1y6`FW-~w+UPZaa=?lya2+Gz%K4r)<7#`Xriqd3eqn;Rz@8;Iz
zUOLlY9}l*XHVFzjQ)!N6X0+6A46y}wDJ_-Cn?xDkDhW(RMik4&!Ffx2p|D$q+t{I1
z$fS=!d3gUHahb@SL24T;H^RhfH6X4^Sa8W~;E}UOcSr!iMAljB8M}p96Mw`A<uVtU
z=wS>4;iwT02XZr6A4#_5dxSsU5IA5n=6wIRbR&^Kk^T=fi&$5(BV61YEyT|b=E%zP
zqHOC*njJ%FlKNsE1(IrHd#?x;QNFP7S5+?`vYwEy;9MC5AST!$$nT3!TfQCoFiTo!
z>z_={r0?JmN?DU2%4^z(34b4!zsbNfl>v)}$E!;I^1QIEy>NbHj5#t{FH2fU)M@!&
z-o?lM>%3->i!Kb8EIKh<H(e&Gj$>}H4-K1ve<FrYsOM9)MJihz_~@8Iae3ih;ww4o
zg-bfu#2e|P(AK6mwz%wCEDp!@4iFS5-DIk`Dh>=aF+NM|WN)y9alsy;wT<harS+Cv
z{weMRClp_E$&mUhOQ4FtHZ!+}aP&L~LLJ`{j9e1tCi)@C<924%XNMhMrSml9(5&ET
zO5W%tEF314Urv?ytruK~42LS$Hi5r;frA8rl2zdX*13`gn!K9h95@3NIrI1QM*WV+
zr%E>2X4>;s=EL)EbjjyVR?f|pat$%RwQhHNucG`iTkpJk*7C`IL9i+lYOt(7ZJbeh
zAqKK2AfSh8UZt_gJGwZJ71EuRwj2MxF|9nZ8%+(yHG#D@IXg95yk4_~NK2MfiB^*t
znHZ!|9XL#0#c0JVhLj+l7a>{{mz36^s&cCA)~|Q+Og|hN4%KEWKGu7m&OFc&%MQ&K
zUm}V?4P~NTTJ^7=nWv`PSpO7&aB`y&wucwYRqQ2goR6r$Ye6-UAwL20$AY=1wQi7Y
zFK(xXVi+U@wdZY4BoKadm0@>JVZL@I$FNuXwnDxGo)!EfxkyuiVVE);_k0irR_@^w
zH}hp92ERW8(wl10^S$FaLXk)QjmP>27^X1e$+M4CW}SnDbgMnbL!wzr-)8NQ^Bm0b
zSLA|8k_niY>)L}Y$p`Mm89@za9U-JYoRuE@AE=o3GXE?GaE3>mejPv$gnYNu7Xc~<
z1Cm;XDW8G$28Cr(^iE#Esfj0MG;?9)wV5!EHH$gYSAYtMn9m=uMk&}?`^z2kw(AZf
zWwpVs-GG?Ut9y(DSh~%)TJ;EW&G*OzO93}yM{@bG#Z<u&AC4&6=#2auUQaQTh1}ot
zihC821cY_arn(<YE^H%rY&(*qlURTKPFu3y;g!zJU$R|f!8kDA%1z`b!g9ba5+g$(
zww4GIw_7#UUXS#_7*lCF?~(w3eaEp&ve7<%GGvAX_=wi!j^pq2C9GDU6xFk{x33B*
zbxm9;rdRw=o9N4%rxvz(#7@vxR?t@F?(-%DEyA_{0$%3G|LO|<j&uJoKp^L~P|&oR
zt|K}GNF({iM!PIc+o>b-xgcLdCQ|1VyaZ?SEyL;G%(x8LUQ@91P1ww^@+s;|mg#XV
z)e*A6YAn62;;duD43ng$Q?DO@#*~Zk8cg(FRg~Act8^MwD+Ov>C~eHzH$gLwre5T~
zmNIZ|9~Y7UUCJE>GF**(fM)|ZLC_MX#sQ1GOO%zIJOx0EDVZc!>+v$`LD|fyo(Z34
zw+a?*Y^)EC^kJ~J0Wf$1C_7e3hEDa*RqXzQ2oST&U4Xg@8xZ9Va8(0wxfv1!WSQuM
z9G%2ECZ&ET3CPGYgb}|DvXbWzMqX+M@j0y6=z~_of)st6azU&<Xe4;qjiX9HqMS>U
z&p4fZ`&6Gw2%-TDl3M^o$?Le;!R`BJgwzIZmt&D~bOqidY*gGsgA9IPP?n4b5>?BO
zU-;d>^fIHd-@oQV2?o9sU)5=2*#b{D%P|j$8im`fq>|d)j<qt!;bINPI!L*VhBH1!
z7V*vRsp1s~hkn;lcpuqLOVCHGYVKAy?oi%w`ZMGtL(c`mPG?w;^qs%)^!tn>TK;Oa
zF=8?2BfRgf094Dk<-p(=BZAk%=M|U0(?oa&R2Li3Mqv(;`ToAd(<jfD_gx$hH~Ocp
zL=v1jg9qMd31GUI6Swdh6N@01nq5Fz*Ht&r%wd(MNjN@9=rqgv@C&G0Zc4kq_A?Qj
z8tJ8{^Sf#W)(J76n-)K;ACg*Q^t;16@^MoN#IFs|T1QuyokRbWzm$5m6W_xs!P-t3
zb&bbn;sko877S)){#u%U)_ubF&5xiP82&!EexaKQECspL>F3`F0fZ1F%HnPUJ6-rW
zqkh(bT)aE85?pltk48Grv^n|x&ZWQ@PzSdHXyH+DeEB*NjOw0++BUVRsCA;ZIU+)Y
zSn<(hTpHd?e6t>d0^2o-RD^Tt=?`y^JkrL~V6vYO&Nfnb3Hi&j9#%Jqe7kCLRt^1y
z+o@l<k0c5=Pb1wfNt}98=E$0y*=mkZ*MSM~H~Q7om9?m(+gVqfp@Hf=n|@+~0#Qx@
z4?E_4+0OBxJv~ihs6ApoCEN^K_}3Ov2$_YXZ-xt3o3?C@Te9_6==85d(l35zbFGM<
zl+4nrLLrk~q%6Krar_J{RmAw(hfJZ5<`-y0-rmv|d7<~(J!bx-k@z8vdD=%^ZeN~u
zV>F1lV7%O2ePE4%89zE*6ed{LrM}ne-aj`Gx;^Voi4Cj$pF;bNycV0qv=Stms+O2b
z4yRZ`SKbzLPy4QRz7JL-M!V-&GADWBXP$dv?w};bRo%}>ZQhb@!J99T?J<po2lt>o
zQxwv?>NNs?zulI2D#Y|Ws_+u_X8`i7KIv2)bgu8c7FjL_Ydn|XT{YI^ub=rjExlyh
z3%)^f7FEZcaIooP0M+|+3+CSt;4ux$p%wOyl|Edi7-rXpZ|87)%hM_Ll%T)ePW}ud
zo0qU{n1wb3cREoQr=jcrK0F-bEXfSAOc;~}CvWv`nx9<}LjGHeb<XK1w(vI<+h*j{
z`P9*zH)<gMyEIQbj-cjr3da%2m*t8{G=C+-@}%Hfk@LD`w%ayZKB5F<N&U7n_5c$u
zok>8YMDBP?%Z|HwfBnlITxTzCn$$JYu#e7Zm>>KUrf-X~EUOgFFt<5Q0Mx+5J^#=&
z#>WMu`7J?^dqf3SJp2I7Aj#$+JT9DTweX@yOFFq)6oI+YQewtKN`z3@XOize2zZr|
z-ofM&PkBek`vhi&cT)>tvdOyo&ts;@0?s|WGkHXJ!W9+(0_k<2dmHmsLkAL}^LbD6
zdN?uCC};7wl$QfN{ofe5>9r77UZ^EOg6eG|eY^Tg@#&BkZYHWZy62TH4T!s*R|aKk
zY3mM_oQkBHsXxs0(ye+bS+E&+oasl`A;nnR@zl}E@n*Z!0mhJWMtfC<y*jAyU55F>
zej!=b9WaMO2@NxM{g+Pwi|{exa_pj&rJ(n4E>GC_po}IW@Eyh0gRcv>b0el?YB4J1
zW6~@1F{PeJNEJ7Rb=+@{LKR}2a{yN;x2$o@Bk;{oSc-iD@?%@7Yj{2N-3$Kfq}o|7
z0eruZYpWceK$?@xdIQ%PDsKto2vt{-%-C~MuX&A+IQ-6&I4AxFaU1vcXp33K@ts@l
zFeX^m`rF&hDe<;I5qZIO5$ku*v^-VH?b@lteCw>t9axrnp<aDnUCMB#wSp8U=DeH^
z&~WiBC;qdq80RRrNea@D`f%+!4lFW<6{F*C-|{Jo6*oGwpIP%{=m~<6mFlulcYC#t
zS%}1a)$c`6tzYoLI`%6AUc(JuPpxtZ()7aC(3){J32a^l-1R^%G4_g0K^`BYAc7@O
zz9EVjm%?-)L29Jq<_zL93BJE5i?vA>2jFGA+l~r=_dP=ByVdpKvkVjci2<E5LbZTJ
zT|Za|yDkHKt=DpY!ff!GYQ+SZ{e0|u@&fw?wEJb}ClSa0|5QN<=~}c*%&2ejq>!Fv
z17L{RMjL?`@%WxVT)Wuv8d}&@SQ1IwCum?CNOpu8ndb_3i+Cp@7vx>fCQ|Z9fm}ys
zRXU4O8-&_r$TPdy2B&0#Qt$b7(+~jHecXTY3Qs1^+OpFFkB@;}LFk~8J1N#Te%!{8
zyk}mt{H8MBzraxXfR=e5_yNgEry<Rk5tQdk?UU$|06bid*0D;UaT+s(esg|?lU^aP
zle;$PW9oG#eu7Y5g`NE5p-517*;`f6eM~**Q59j23CqqJx-It8nyorJC>Eizcd3cW
zavH>Cda#1<et9qDau6f%Z3Z~E>y#AjC|d)ELvN5E=F3Zz_XsxM2>8Fb`2E;G$`0oz
zhCY6^?<L32+g5PHmdQ&Jo-rJv!C5aV5jPe{SUK0=mZ5_QW-!siKsnL66r!M|s*DT!
z9*`1)^@4$?k~e_<poCx&p^rnq1(aOvt68bB%y(p!eaT}=WRWNj1wru1N*?9k=*!Sg
z{UW2oHMhyFR^oipSfQG*D_y=mCyqX`l#579V;nm7|L@$F3*=`5ZkR~g;Dpv=VX(O>
z0rywKJGUOxr%Kd+TQ(G{29pgn#q2my?SpfTm<ku79g<4LFVp%F24`cD{$JY`Ge9MG
z&Qj`Oj-U-4ns^jQnop^AehqwdN7dd~bEV@dUOfz*rxR%@5#A)YBf13m$73m=OKi$O
zdZs%A(L@kG;|`{rtJ#I3Vs&JoI0ZQv<A2E{Te$KUT@IS^WbRl9X~FKk``$)2B(zuW
zrF?8x>CoHIMv+3!B(|PL>?2hNR{#GE=EJ_JE7a2GfotvHE`($>egq(IFj;%W%72J-
zqc5R^>u|9^3j?$I%0|A)`6~@<fT%hrAOYVgz7E#ukK<#Oc5vn8VV4_)QUJ2!l1G~}
zrEY$2NF;V}`X}YVG)*U~y!<1>yuof+t29SyZbDY&Qm)m7HJHC$blTv)<XbkwOj#-5
z5L9WmcvLd23cG?a%U~VKIiiaETG;5dbIr?VOp@oTrpG{?-G8Ft&u1=u)LJ^Hn6SA2
zV57=5`F&?&Od$Ski%4{HBj?94Pnwb!MO4SxvI@0t@_8xTH*HJ#e?xryNz4*dYw-Pk
zNX3;bjM38w#n+)XwRvplAK(ftONT{K8P={;Uo#QvPcp!kCo`F|r2t{__+ST^Lz);f
zq;J}jc-j88AnjR<IDgHt*}h)tI4_8DJvbny(Jd)4591(>NT_||_le#pn##&MYY*j?
zyr~E@1r4A!df&sKEiX+LK%oNRgE$_af<sAJu;@d9rp&^oxa;pRF~*4Ng^aY-DlTD#
zqMp!)RmZmplZCu><e5VCGEASYqESioayW#D#%K$)4z}N+-^n(gfA+86(u%4jssc~W
z7@t3+&lawZI(=Xxcwe)dOBH-Tt`Iz`TXSxo+-G)hP7CZ=pAL+zU-(`2%it-|t#}h+
zzO#po*DMnYGT?4RBWGy-jz?<u=6Xdu<|5$?zKhV;lzQ;-gQzgI+ebI6ggvTo7vQ^z
zJ~vvp`om15!IUjfonfp)7F#D~HxH+RNM6e-5)2IaAcMweqyt!-hY^(ai{DKSzo`yM
zHLTy~x2#>yyguu1QM$(#xvLH|#h8iK7<!W`zwXE~OxpcdI=vHIl*@f4E*H-7Ab{%C
zeiq#yAAp!)V&36QnK~WbxkdAW2ord0I)plJuA4sjt9RCto<_mE+^|vdiot^;J+h-8
z3fsQdXRo6A1YttUe3Zkx^rdD=D&hAu2tsluHBT4`_T>oE8S~ps=OejG?!zb37UR(e
z{}dd?2+VPq;7z*vfR}iH1{V3JKiNU6FdJG?STgyYybX9(%-&-|DQBlu3B<PM{G}(3
zFcU5e8&}8zlD?-;3&qW>M8mpx3$$Tr7{WvuznW&esu>23*9o^3%qRW_n|L7ZQv!-c
zH;3H;C=qvYA8?h|J-+MhL*lS5H|_=3E3m2P#R7+Eq5HX+vT{iS6&U<)NG?CQ!jFO$
zk|&^rT@f5^pBHN3hquyUF~kQ?06qEyI(JL`zp{WDE(rju;U|t#k8Dtz9pBLtE~Hki
zq?5fQ(w;?;zBQ{})g`R!#LLAXO|8Kvr^dTeS`1l8$E8YA50R_INs!~ZtNr$(o}C8M
zCKrC3)pBan9k}_mNl8D;hJ~LpNq`*zEQ7)<WZeK$CrbNRk11-@*UBBk@aZ>ehbNi(
zJZ~}8RQor=l#}N!0w!J!hl112z)FRwa|&Hsjla9cNd||1Et*dh4Die+eHDu+)Hg2V
zlyB!QoS<&mS>R&lmeq?ZP0cIJjtTOdS0Ri}Ks_iKwlt^t0pT{flL%VzZWpnHt(hi;
z6ZogQJq%}Hnd!&3*YEXsPmJ?*Sf{7#QEUT6W`IW<bC`uLD4Kz8%REVhi^pP^etGCT
zo38ZuAfC{WqUweA=xAzr7O{MuxRdL#l;n1RjWN|3nAuJ)KS?SR8HJWKIavUCn(c~2
z<zMWy=DxZc9jiH^4{sq=7Sz0qwMN^Dc*%c+?NQD4N^*-Ll>h<_+&g3)OZyi1+I%(D
zJ4-5e0(FM``izs14_?#x$#&6FmFtHR6%}&?ItkyCQbT|4>YaKq=Ym!VLVe#PJsb85
zkS~H#Nl6f}xa|rm=jYC_gLE#9>|#K7)#^JSMI5CLQKEqo*jZX^?!<TL(hl&%ksRzQ
z&h0Ptw&&8$!swZ75vdOEliDF2r<M~diS>Q!xj(w;VZm9U<?1{(q-`DWc;gDBsU%6E
zY>m!jUph1v`Xd;Pg!$3EZEemt5%l5bm15e$Hm*sQSS#iyI&(V&qS?8y@)D8=lmG49
z%x=zRh8Kdiv$lX!#P;fHsb%4<dSL(YH|S7ylfI3@@y4JJWO+id#vl0QG3Y~ia(Y{0
zUA=y|99#fG)%~L(>4p2b_0DYfSH_4Vhz>U9NLm(HVzJTGsqhyQTLAOc|I$Syh7%$L
zoCC<LtfPRBhIC3UGWTm;P`iK*g)ChFT8yUKb=d_U(2v=m`?Sy>>RKwerH=)!<fM+)
zuRG<@%vqqaoo;ChZ?wYkg+QGZ?+Klq>EeD^7L7gP8<D1?HwHW&5^v!_T{VP<Zi`KH
zO(K)X$DO;cI?J?dKU8e+WO~_ng=39Sr9CRonjoR&nMiY%meF#A<%ms})6vIn=aGVO
zFXpX}c~sLoKQqcHgxc>|oZ!zxRgPUCVH0k)jPOX4m-ph--LSQ~VR?f$<aG4F>pLy1
zdq@rjb777x{4|>S8}QhPh<EZ-J6;HwE4r(>)|zik)h|vXSCUr;-y9xjzLP3^O=Yu#
zik`m#0B{@t_l_<?%y+N#ybBpD8G)JGrDz?XL*4Eq{Q-bv`L>PCV_FV&<<nvaIYV;@
z+k+Z6+Uy;fB~#&o{F6o;f3H(UE>1wJ`)H<pF$OR`5Evt51CA9oJg3>4zq1C-*k1qF
zNw#ey22dM|VZ!{`_A6QP-;e6Cf*aX<)Njg<nzK5Lid&D@-Dh1`dZEYSSD!?bb}5p6
z=oR1_H34!kF}l4(3Yl%rS0`3`OSR3h=jD=NpDLon3^}L@St*8{#$F>HE+^|#AcL%#
zR^pKhUE70bKlIBm%PzUC*kF$plHmF2I5<8~#9>gtM1w<|h;Q^(1$&5Tn8>aU2qgkx
zc9Y4Re!c_cKsp`-=h9yVeckjcFay^!G0Kec?i1K#2Jm*5aIkz{<nvn?-PO5O6><Gw
zRQ2-RcZcEDbRCMf&i=fw`G-Bdw)#ktRmh;gNe2;HvXe@%ZX9|axItyVtRpdLE7`e5
zrsNvh(i5*gf~pQ{HNhWukm@)+o%9KJ9Z<?`b!&Bv8C^U-ZCWp|@K5w1BY-sgniwHe
z?j7j3_W+7jNbe{T<s?7I*3Ci3qD3T)H(4t71MhF*f{8?Ql>eStfj7N|+H=+!9@u)z
zm3W00r3n5g&Fm{E;Pk6VjVQ@uH>l(^n(Gj7>a#4|WxcCpPyI26&OXl+1kCBG9ia6{
z6ga4$J+{1`sz5R^-l2!yE80e<SprK<?*hZ81RRh!g#Y!k3o^eeC!MfaUvneeXkXR$
zHo#zGw5yW>b-BErS`&{Fnk_J7I!XpadJf2qxpU3MO6^>@(NUuRm$DvRE+T8boI?s)
z#$M|+9T_*HZP-dD)1n1~XoyP@P!BX08LM^sPK(r-2Puc+<J~u#jhzoX);gFLTNWV6
z6Bc8V5koU!i&W(21QAw-cJ<7qz+oKWd!aMO*AX2?u9PL`I3Fgv&~7mEEywiE`hUZe
z^i+hn7)S@wzmA6F@O9;7_I25e0nww^#5%!z>YRmbylw<5x>NF9p#Y?<E&O*D-f}v`
z9?q6=T11ZSo#sF1OL6NwX<Pt3eRN*D^0ObDflvLFrQz*gYXyIazl@PdxC($#w@`n@
z;o7WXR^8i6;U>k5GM%eYbhP3AK|b0C#>0Et-sL+{n%zJ2^5p;5i}}kg$llpNa|_8z
zZ|Qr?@(OB+adVRxe*fB)c@o7xE3AsYFhFpr75^dxSOEz4ZuD%BDxq;Z3<a*c*q#v^
zYO3yIAMq)et`XR)D%{7G2%JW@wijm81-$`s44q{fmEB}x*^|^a(B@f8N;(c)_a7G3
zG>|1QZ)w6Wr?@ld^4rBekj(z~cVBD~HhaL2&uE)$DDyWS*`q049MY}_U_n`mEWo$;
z20OpGf?%rWW6*4vaMIOz$aL?qabM<z;s<DL10!@Y&e3-d8(XZeQk|*B_IV|}P=~cF
zU6nG_qH2`kknoZN5p)E(jQDCZ8oHz9s6x~@#_kbiJGw@Fdko!kbnWJ$9bTKVhL6#i
zuv$Xy*LP`)s-@28Ie%*<*9J7p69Gj*@2*y3j`a`&6^i}2^-mOF-(>?yeVCO2E&3cA
zLl#+T3jRzXL+Z?`-~5<wcP{utb3>6UAP9%W(0F{@6b7LqcAV)H_lh(ol<;58LADKT
zi?i$tG*EZ&B?DS1y4LGevlzSoIdMMDKVK2lk@9xd4@!S~!WHDdYZ;J<8)3D)X|I}9
zX@YOdXE#9=7=!jrGgs#6z3aSSw#_2dD$=fg;-2UVN#kn1H?m;!MICa6b?zNFX(so$
zCw>xdt}KS3B3O)u5`+R0nl%bw$P{rS&T7SS;sQVhT1jZSK$9eHj=w*w)A$o{D7sR)
z#C)9=*AgtbwKZ`vJMI<)LR)g?vbXrNImB3$`G_7lj{MK)T9m8y=X&G5RKR=I{eR5l
zIJb9W9WL4MFQdY=-o@JE30iv$v{eH_SMxznl9q=Rob?5Ku7ld$5uj$a=N)hYnvK@B
z4o%QwZzIW=L~~|_|IWduyk~)R6E4z-<$k6$DuTmF?&U#;XCIq#HM4$vce62zIh=IH
zq&EQlx)pF%{C#~{AX3elSe=a0jSa~Zb3HpAPQ3sA^6u>K=(U4-T3UZ@2=eJ_(R}$9
z_rllDDF<7W#5I3D)M^%c!Q6wkYtEb+kc(Xi%mPpF*(KxGE03@s>GcES8yJFtkP;q!
zb`mvBDFo*+n90ZF9mu&)`8Jpzt8An<38B~&KKZQ>86~2w$cG#gbYA?#hSW7jtADrQ
zxV{cc#qLFqEN>dP$V^(&W}H`eK`OM0?i&Kwi*bp_Z6|+`zqp{o)1bFH8}eYD#McQ7
zJ>*WswNzqo|C4?pdV+zZPS{&E%1OAoeQP}&cMis3XN8uh`_{8wo`!?y(RP@uYSrqk
z@rrN;pOftz;^v%Xpn9emD?{5fD2)V2m^jvRknoWhR$s|QYRu@S)EQ@vYJLz$@TK6R
z6(+5zMRYq@UOGqX*M!<=jxig<_EJSFj4`+*OR$hSvoCB3XbB`YFNz2HYa?sua3soP
zGx8Gec`8w%VWvUUxwRi#8)wcrCuTkBJ4C~CR~ckZ)8_2a2o?5V_=wUYal`Xs6M*6B
z>c=S!S8HKkm1wt4{%N)Or9u8c{#QyL5+vJwF35tf&T?QqGTEgcfkG6@{>A81cBXth
z8=X;*Dwi#HbNR({-eYyec+XpiU?!4f4oeFvKL1p&Uet)Lk#z;)*~249nZ`DF;JREA
z+~PwB6}H$sVn1J_Tw{zW3J=0Q05ltwx1e<Y^c~hCUVU_bf|x`bbX(Bun#A8WDl7^Q
z4s!}Af#O$c9i>L?<m!5%gOjl}bO^-TbR$3)n;KY@sT35g+<n_7Egy6jTFDdoa;P4u
z%l>@II<tEWq~1eKSer=DBJVpU7$zE}00sv#m7{$N#Uw^r+{EN46f@j>$p<T|t;zSV
zSZtf7CiQqLx?&HkBlMKj3G)GpxZyu)3GT3;{^uOfOa|;1ygp*Tr!Qz*k<kiyNCI^Y
z!$}wW7?IJKiOi+`D6%RMTboq6a_Uk4K6WUr;pNE*Ml-73xug?BX+8Nr9!WT>%S=(n
ze5Q_Mf&QvUGB=ov)ZF`wo<Y>FifBS)5^bhNBl*4X@I8ZgX>SsohTC)Z>9J!%7CpM@
zaQjS!ppSC3g@Yr8^%s`>osAyzK`<^ISU}R8nxWO?s)#2b4^8p7V<j9`r@Eo4G$)k{
z6M3{e25AQz;WK#YpkaQ|c_K)`WrizuTc6XQ7B2A0o+2Y7+BJt-i4|ZJJPWdP??h2t
za^Lxt0w}Hx{AIg8RYD8~iwHsbO)-Nq{KCKD=LJyljP<|F`g~>1pJJSQ8{mIDNO*)6
zKeN`oOFsqK*UZ*ikOKg-mbCe^0Vu{Ds*T2rgwq`<jl}cRXUnNyV66LaZiyOnU6(r&
z@~nZ+hqJ1_gon5ta_Db(IWSWUBt>|SY?sL<-xIzYWvks73muVixRfD>{$yhq?##}>
z%|4>i{X*^9@l-qeJ<%Mr<+)!ZI62l_Z7Vw59qD2l`55^Dy8}f0O2inTWh#*Ae?w>>
z@&cBP9V0SRb7@06+>8LFnsK!M68G-hrPpV?+VTa3co-*p!(*;WtP;f1JYwTQP89j+
z&##NS0YK|^t?dl`5K2!`sv@G8*L@vN;rnJQ<#D`A(`#~_s8$@L!7O30@%$SNdSNF5
z;o_Yd$T<a&t?oX(WCXW6h)~89cro1tG+^H_1b@OKTYvh}XE88IT|($k)R|(39fB>2
zKx<B(n=X%{wx+Arn1;EI*0_Lz=8M)+23QuBblpKuoF8%cN{0XS=H+SJ9h{4-bZHTy
zR1;u-gg@OfN$-;%tHqUI3?gyZ4jZXZHmP}WVYmkXQpO|asn&{HBj(&{Ly<=<>k`jP
zEFouIA7zU%zC}nsjJ=0%Z5^$x&%&?(ZcfXjI=4IK<6VN?=ShH)c6M}snDTKk8Jakl
z-?gJv?+d^^d<#mffC>6TpynIjL%=IAu_<X9>%D9~Dtrlb0ABy2S$2`Gbjy`jZ&hnI
zZ$Lol&t;n+KWFh}tGAl_1VU6XaGubDVrs8ge|UhG07WS1O~bS11jbmppc3KEa5j9x
zXK5TfB!&u)yO4s`*PO}Zyg{lC-R!2rVyh?x!FzQAO9xJ#K$Dw50+ZPyu{Y{|<zi4)
z2fsVp_P)&TXdnkI$iP8_m?PI27gEwje-S86Xl&hLGTEV-J^+nf!dMBdstN@f-Nl@W
z$G0G&E?KK;1Xh8yEOMUi;Du>=&Djh9r)2T4tFL(Qzgv_5D=V%$VkDFiTLCKG@G>5B
zq6NZ2f24x3&?3_N-R%<`RlB+1aXJ_m+YK=RLnq`*O#!YnR;9gG7n9AUc;5rN1keMf
z|I9x(d~TDEX|;KM-~-{aXn>3;9IYiEhW%M*+mdr+ySa>F0*_Rw^X&*t1#JYaU&5|=
z0Aewu23LQ>OKhJEL-d6Xr0g=mi~uV8D5O6ELq*So3m~C6P|19g5Tw}r4?Lmhms*ra
zD1D=zV#w`1QZ4HV+DDCO&>gyY&{-gv((aU9O@d#l%(H&9Q~Kr`*=HVPT2;t#Gb*^G
z$KvhYCK2EZIeJfZY3scpF}`kmO@hLmta(i9XN=9GNTdy^Yogqu&^@IJwW(Y)dySl#
zcvZ<x6tjjU6%O<l@F_k%?!JUl-q@4fyUw0V%Ntu8&%UV38GZMiN;>ciAb=U?gLLYc
zCU0@40y6y%%#5_9B@8T|oCwHx`*Ng1vwNI8hHuBRgS)`^+Z>AZQv&bsOUbGp+KDhj
K(7?r)D^U&jzn5qL

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_mdio.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_mdio.v
new file mode 100644
index 0000000000000000000000000000000000000000..d87576900be01cc6148ab7c08af0afd2547cbebf
GIT binary patch
literal 7496
zcmV-O9k=3(6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btl#%?B(cGx%if%(y-R(C1x!vF&D9
zNY>ujh%O@4GkhBRT*B%E-Pn)~?I5OOC0aj))ZYEtzF4pI0L8;wHF(En!k%Je2TC@c
zcjUH~?^uf*Ku8JO5!bq%6EF3*P2Ty8+0+zDjhAY58C$gMv7^Op+Y<`gSa6{hvT?7H
zxqS(2!bWV+U(h8vMFh8`Y4dZdVN#crjdxMTT_Lud&%e1>b1D6KX7nV*f!5TNA{XNa
z0`Yr>*dJ0rR>XR6BO5C&pcunkbZtKC3Sdju*7StQkh$+tJF{ihF3f!(fE9C_dMYO5
zUT+F|Qot{VjfRveL63ZqXEtD2EwB)N&O~ABKZJf$s;(Q79-qc%fhyXYtIa&}o+iLz
zXn;CaN-H3KyDBO=40m;swi7XXjt^<=RD~U6ocpi)%#W&Yu4j|51{x_rVQ<fa_)Ixv
z@n=k(2(rzLy1!FcsH<@ZXHg-UOmw=ceydD(-lTXsa+e5IXGwp5<?PR9Bax<@qB4%L
z7H-hn1%()x{Hs4BK0N!gboFloVu;RgV6(zs&e2~l2}jad(^boPvR{fVUh5VTDXK2;
zNHSYgBd;1`bsmpcaXgS1oxk&(0J-l@l&aq75A?n=94!X+*f18>|6i2II;v)#y89=Y
zEikxJNn7raj1;~}O*3D1Wc)!TLgUt}i#YLHu+r_93F8})`%z42>Q_xv#W235>&V&;
z@nI&{w;P6uUJ=RVvH{Ajx|Xo1<Sri-z=Pe4?y)98da13F^%7Bii3qUyFFuPUTzj_e
zg7b#l;f|AsX2WJT9FW78&lwzZlgZ+_eI*J2AnY!0fQV)3yFM>sKkZ-a76~0pji%5i
z{<QVFPts2eoo6GyYD<mBQ16C9PA2lI0eaHOzL@AWH&(`VmjY|J6tX6DtU*0D1f#b=
zla0iqu6zW(IJMN&{8vaW<rxU`SQ>?RDk0bFos0W>Sy3pA@F`_-Yy*xzUuN7^uTO}4
z)%!_3D$hl4I^kFpX(36&{1{}QB>5*p;*KUA_k(A}b&b0=DB@K2XUfX1q6>^X1A}Fx
zM|b}LsZUtjKYUbH>zogB|7w)tE(G+Y%9q5J<QHe(dd?;qj*C5JQY^MO;;=kdy$}SQ
zBC;dXjp9HkrDaLFXn>LRVHv9VXXi1m%y`SsXnHLpz}TtK6+5-znxs@J3gyNwr9*xW
zrmPzAT)JWCyfxKne(tBLbj9um#s;Nd9HYbSJw6uMHCIug*7fe^?88CMB(B#S>wuwi
znJrbuXaWM4*7+N<;R2e^@C)lZ^0vvm$}hS}iImu3$yBl8rrLGW33LD2=DzbbnynR!
zEFpB$bwz-$|GjP0RvU%gHvWQt`^Ru|b+pzJ^+j%c6t*mXuh4-;B)L2i&&q^Sv2_wR
zaL4q^JmOC0vxs(q3pu_fn0<-yFpABZnAfdajxdJN4btvej<0&uM%TFt*{=ZYWWGFx
z5ymIF3<vh>lVv1*EUckw$j0R$293q4<~JKRt{_yGZhfM=UiLy|$TH3$rjM(+D|((4
zJP((MJQj$gQ&>~%`MpHu*3#w*yO+JcPe{{z5psW65s2L}G!!zT;|JfhPOm$Zg3z~;
z4*KC8dC&PJTA!yj5xyj1RhLcp<&ngre1sT^?jqibnuoyx6OJA4clN9-H|Joq;7Imn
ze+@Y@lk2M^Mu2~vn*%MXHdrK3H>exbFG^qbm=v8u&5Np#+PaB#deZ;b_YT>k1+~OQ
zaK&_(i5b|;#Mr#XK(;k>p19QG1kQ?0h4qBDdJ<@%HrsbkN2a6ShsL#;ai3BI*qr^c
zbIztYoulrdT$O-#luRs;ZQ|n}1u%}>L1j8|&LaVq;Y{4!cQbUe=a-IqeX&9w!LqWc
zA9eR;sUm`8m`luKDrAO=gft3F@6c`|$|NoVprKMvezNFM?-lZ|j?ccNyg7(id651^
zQsm0tU|=8UC;n1x7PR_z=72IPkG(pBt6+t)XhhLuTA_Z+6woI=aOrW|UToB*uLK0>
zb}l~9V#8(Ti)i<pl8`M)i5+DVj$h~kfQEbZl-Tm$aBx9LGa*i>lMLE<*zQnLiB>Uo
zv^pXqwSSJI{c(R~hvEd<=i~Bc!0;<YWT<^$V!-WMcCm031(*V)ln+R0$)A0f@T$(g
z_2aSk!xwvwgA+6vz%l*8Ra%pG@SnTkf{=F7kTg3MJD!e68`IMZd!o{cZ7XzTYSNYa
z&-pySv!(5N`Ylq=PPoI>vFB$-E>_w1ne)|DK5i=Gn3|-9xTUf5O|&VhyGQhHCG%<k
zfrP=T{u4snK_yvhtr-8lt`=Hw;Wa)+%b<0FvP4JWmu_KV*JKfC2$O#oS&Go?$*YUA
z^d+E^)s%EpE44R%F?Y{xg5BGF0eI|+LQ^|UIo!fm`kqboX3g%>;Og-4j9R1LOefIW
zvOvI-3L`d)xKQWG3Hv|7bb)Xae2E2k*ZC;dro1p9DdBu#1C}=-nH?RlLT9#=-A>==
z=opL=8_WLwU)eB?P5%%^H#eaTyO2^!%he#Y_+*&*$C><1oOHU{R<<v@;O0uGO7m49
zdY<in<(4~?wT4Opk`it7(@6`?=ZyZ*Pz>4+`6u%!+k*jJ!)irz6$+CdqE9eU_}s+S
zw;5ig{cZ(%PxX{?!LVO3-379-lA2C_)0pb79<iU@O+K|Vh=rQRZ5RYxwK&QSGZ&p1
zV-zSdkhcr$rzmNtMB;eEWuk*hGTI$-!J`$P2JFg$(aA&{7mFYpr2rs&Rpzs-zC5Z=
z!%+`1W+Y~cLPCO~Wz6-VE4@our#R5r^AEEDK#qcEk{vT*`!JzpAp185^ToQvg^ODv
zBq3t4D0^iCfmdQkf`@xU%xSI7_-aVbnZAL+#v{+6$J(w8Ajw9s1xA@yE5)}&pn~o$
zfD}88Uu5o74dz6EsBJDOmM{!w#asHe^l`)bcqU~V*Xm&EU)BjP&Hm!Wh%+~qYke9M
z!PD;&i_HfMo>$@;Bk>gzOzNy5eW>M}F8`FA`X^Y4=iaj~aU`-I5T$O;j_`OQ?*EWZ
zwJJpcLDjXWTs%h)2i~=^yGEF#3ZxnAq|^TL_`l<kFQl|b)r~}7fulA~zho~>M)lAu
zAnopg?+JVWoIy+R{I2vl^Td8Ol3)x>C$FnrX{Hn$kLVhL(Pib@^eE!ev@T^oIrHEt
zceiJOCD`U0W$tY-6MIMw&IP&DPB40nhqXZ2H{R?!u<L^KOVB2)ky>zNt!EosCEW*h
z2rc*3F$@P10b2oomq=cS%G6DN(mj-_tfe7~W7SZk{4XW)3G5T^wQ^YO6bY4hYZYuS
z>;B~`o@0f3tmnoKeXenQHBs;|KkcbW@QfL&SAN5qmM{PE^zr}GpWf3_vX}IFv5G+o
zB1cr5{1S7wTbE4A2OC2d`}qA@bBD0^^R9;P{8C>Q+aQm%6c7ppV_lazc1A?`$#Wt%
zzqi&i7s75fHJ&O2sQBzM>V9Yt{_jkZ@1~LS2(ceAjXkwhN{4<DPmu|VoHRtg=lBYi
zv1|5$>_BnOmIkT?U*3&$<HgGz>Yg@UHdia6E<^ah;%u8~rE?+RFloYpM?7{Zm-7Ou
zjK7x0r<Vtm7N;@XW9H<?gwV6rH=Wj}(oVSla;rDg|4om=RkWy%nnY{Let2BYKB3&m
zLdhJ4A2ks~T3GW5r$pKwnbY6?FxIbXD|ygej+@JChKM>^3<igsTjLzCkuvg??UN9b
z@MUcuLN*ZHMt)_^_z0;2Jfn=Bd^1a1S0{shPI!^I?F|`Qw&)F;#!d3l9KN1`G~~qq
zx*1OR%zifO7A;<JV=<wisyYN;hT@>lhB1ROy3Xu6H&HuKO-4m2znF#qIP%S-1B;Uz
zYB2JaRG=Z}8kQ5qu&m+WwKI+S6V)8caqSZ@4$+LiKTbASfomKRS(G%&lk@!b)g`0&
zWo_lJPfj{{h6cHamHLhXiSq>a^>xSEN1s)o&nR5XBpVy2zHMRp4l4;LSe*9u0n!AZ
zE&-N{`}04E&}Ndj9-#!}8l(@4i=cm~B9bOPEuDZFnnVF?qYE!qJ2Nw|RHY`aBHr=T
zz!$xEDb3I($w6`HBV5B#z<E5dEs2Z~@A*uL=8ImTS6x#`lM5oYZdKM&qY4l-MZ+Y}
z1YBj+?Zh93ks$-CWtF*ob9$yIWq8bS`Ue1~7TBe3r@>%+VU4-(t|ISK(499ZI43TO
zbHoCHbClQu{sk*D(UuAEZEF2)yynzG5tkA6lbfNdj`G$7|M90CUIn__xrfwRvi<Dw
ztwaot33aHw9r~8Gl3(+a+udr}^)7;ciE>ao?xlQ4DWzylW=&wE5&X?UZ}AX7Zx;`X
zCLF!uT_Xkt7&`_sT~dCt&w$xAJz70?9ENw7X|**MtLr!?#OT-38v|O@f1ELEjR|X{
z6xH$4y95<%%n>a&7uvGd6cFSPX82+2+!$MVb{{=Q!SPY}lJyV|7{<9DQMD)?Tolh6
zSp@gA(Z${*ew+idl_+3k$VRNeo=gpw9>^ZZ5*@K+RsLud^j|2SFNkYT|Iwn#?K*<9
zK}~D?$1x~>{_O00je$V<W~*uA&uRhXi2lsrJW42bWdILo-M_2oC6`_Oy{|8M`My|9
zVQsGjSFoZcU_`S{pyELUU5rM-I+YHD2pUo8_>tE&y>IL#W_TnD()E^@4w0J!lEdjO
zGI&R+!;ExWbYFJL$J@V?>E;V|PREUPn5On464){NIt5*_Q8TXkVo~^v|FvJ$WpVWk
z2E7A}2gI|j47k^uUG8=7f5FsA8Aj#ohxo68LHqCO5GX2gXqbOW=dcFG=daF4!vzma
zAux-Att-{1YeDVEIb%*aCAxFV-3wbc&6nfmsAd2|R%b%|i36<U#LxAz;HZRq=l%GW
zIYtXG-i3X7&Adk-0a=cF{S!Ob^N$FwuePxW5AqPtwZ^_^LH6&GlqB`NPxua_N!C(D
zCYwXWE`{{L&|Ls(J?y9Z<#+uljzHZ>#BOf8M0!oDxQeLN$o)U=J6G!gBur&8e>*qt
zU-)C{56q;IRl(~-uUBJv-_P@jtX_Gtq^EOywe?)*ERBxefO#q`<=h!1u-zJDx4k&v
zdD3(eAiE&PYEd-}j@(;w01(Jrf^|tM>}wu-ZG?g!oECc|gX9b#O^fR^pOq3SAEoW7
z1HyYcl*h|D@w>KXhOy|_CFeOu1=$F&2(M3UTJwSk!s#yqf@fYhQ7r7>GYC$wcd1-V
z6a@AkDpd?ng*V8r9W~_6mW6yI_2UoXrlJrG&BEV8bfK9H4ud@CH$_KDPsv)Sch&N^
zKE0MYEJP|K*oqjW5eTeLMXtP#x65bM{$hsu1orjm4mzh65oCkh$JH9gxZTD3_o2tG
z^ew`p!(&t%qL==O#z3@hs;D`o$Qz!#$`wp<<*<RjC`37!#AgGGD;a~hgOnY4I_^?K
zYFkVUZ#)o&<N-LA(`L1&0A@?!{q*Am2r8Hme3qhmsnW{X{*4)GKwlrY>~i>bBDK2>
zUdr{ei>~jjcK#~8nae;3-Q-dRLkH>mdLQgyENW$!m?9`**aq^8PUbQ{JiT@M^^{_4
zkoGoAM#)|O?&A{7@%@@31j<wE%Vf$xtlCw%!8r3bO#4!mS0q!{1Vq<~A@l)b<@<0K
zQCrmMiFxd+y}DlD-JguGDEWtYd#D2QzNe?KRW3j<#=7{ROOvQUbyFvgE?F@-dliDi
zJ6A07ZUGxUuo|}f6(k-YWSToP;Xl#Hcs~&=T^z6sd7IO;PugSxz>+DgvAagX&Zn3x
z<GgkRUG?;Ukm0U}y*1z%+BO$?%|`vqs~E&TxKp0dWO~Df!ikg8I<arH1rI0!+Lz+b
z{pq%7h<7;h$6MKw0Ui;TA4t>i5drE$b6{~mH9xZh{~M;!%w_pkab-!z26jL_b{|a+
z#i40K@*Mc~J3E%>moiz%co(4s{<<buV}O~q2*bl^?|9`T&J@JP8=>rYXPL!3jL_5C
z(!A$cQbcxlpAO5JpVkaS(qo{}GNN8+zGn`6P1NeJN_^6`v_2>Ovy(#Rwz%-1zt^iM
zv?fSbH^p6w@G3*NG%nA$RB!;Ol&Z<>=jNv|qQ~}<n3+24KTAu<b{7yU5k*Fi3Yb=d
zA9kUGguZiw)UmE#po{HEc?&GlI3WAG`R1gS9q#WbR~wI>I2=g)eCK{SW_3{&Nu|S3
zA!zCc*<*EYr+IEV=~Qfvg;b;!Pu}cnV4ntGC5KWymbX>{lMz2ei9@%b<9x$V8@&jF
zWkY3L)@ZAE$Lxt}EOnv;u7?3NUArjz94KQX>t5=$YP!f<)?arZ1hWP9l~k{st(c8o
zh2b5NYpR=61rT%`PSON!iv81A0svZc*VqOZK_!hZviY~{fwt>+dKZ{VfE8;9CHqQ!
zgv4qtxf#Ctqlm)1QhO7;BwZcMn3$_&zdOmC1_kyh;M4uwIOEAbxQRc6xwP;aqA-sI
z=|JiBB6p`H=~M}|L*A4{ObE$XSXj@u-;(UAFS%KP@)q_oF)6P5vXZ&DPnz-B08lBg
z@kWSYD>}0uEiG-~1BV^k&65A4sIVpB436m}^%LL+JcGKV6Jt@*@cIwRxf<+WLfT1e
znmEa=(T8xU`WAOI4qg~VdNup`78yJ9-%-k+#&8~OgJGhRbzXBBTaY_$p}|kI>X2fU
zJww!f__^0dW+RTD$O$d?W?-BiUt4<{k7&d<ZV}FUo1M#Lf337bHg5_F@@)4N!`U|=
zS@>(T0nTustC%aEni-4_Ze5{dXS%VouRu=2SdbZ<p&8MR#@8^8J3VDnuSkFh>F99e
zA#Ys0j7d7_Z2a!|N(J#;NDWI^BX=qg_Ij*^bNEqzeOjYAurlkmZ$?8@XkUp*H8e!p
zAor7b3@5W!O{Rr{e#Ccwm`s+(z8ZBD63FDKUKe`YJ&LuG)R$!+rDI4!Og_0@kFx7q
z?<*Ynp05BcN2U*FCDIPgBK%BetqKJyI0;hF?g0!38GQ(iqr>aI3hUs1JtR@k6OK@y
zvma95bCz_g2MVgdxt*;d9)ppd4m?CEE6|#rHqXunin^4;+j^{sqf)lqyhkKp*ou3S
z12@@i13tkg;xdK`Gl+fV`X@|=<!F56YSBJ%NJe;G1j6X<dM`jf1iy&K*E<&sgIn9x
zzi38KLj{QUsP1aVN{MBU99l?73ra<!iQml^E48#2;V;h8eJ=)xqHB$_V0=xdQt0H4
z6iM%NRJ78Zbff;JYa%#Pug)?V?IsmUa%MUAB^8`|JpND(Xz6#E(JHC_ea+;2k;8Qg
zqt#`ORC0UdaNgp$k4yZdRqS~=%$3V5jTVCMEOz%4yw&b@?W;w*mT-o9;h<ysbmUfz
zoA2Sf<q+g(+ElAGk?m}Oa=*k7C8V|ST00Z&$#y1AYqO0^rCP>ITpf1CQs!O<F};h%
zf8K_HA`QA~(}0c$-}+iRD1<1IAWEHQ%H#movgo_EV!|hi$)dJ|O|?2+#P_Y>t020w
zj!ba{>fvhp1&5GZz)^2xV*GGCe%0$yp-;o=3$Q%6r}dy1M!ON0naj@0a6%wbVff_)
z(vF#tL^2f0j+@Yj8?{`L2olUScOwqn;j|yC%scuZuJk}_R4gw$%kF~V!0;U8H_UlL
zrN`X`*bPc~;rz%px&h&1Ueh_*WD93K$lrHUlkaA5>-bmyUGiltpyBs@<s@hJFGq<X
zFmr|ISb&WBVh0%P&rl!FL)C*tHv!^j$y}0<>0<Ls*SRD}syn5a^(z1J^wXmdvI+Pl
zsfHBpl}^9lF!R+g1ZLM&Rs2CGSd%Q65|J*Mx)oc=+6v<nl+vXObmS;0bD@@y5l2`X
zXICf!I^=jt9H>U;n%8u|rJOaB(dR1e#+KBws@OcB`vktaoU06^BT94n3)3QU?FRF|
z2yS!9qX;g&8@g(%;1W?0Hm~vCrz@u~VN8mc!mm|ZZ2*hM(^FsMFT4p7OJVBB&W8fw
z7-gb;<!twz%|zXUU8sUmg-aqQ=A>i$!!Ynj+!rWt%S?nwE(AuZkl8=C!PbEWG_v={
zAYHJ>x&@Dtmv)2HD3+pZetv@C4&G1p%mA>oD@qOx?SBu>kO>L7$61y7-e$zmB>W{t
zw?cGcarq}Ga-Te8@Rd0#7|n(8I)3a`EDWLxFmS}nV`B%L@z+)+kRTdfmTcb~VAMf6
zcarZ7i-7Nihj>iBk#sq4x~n13XjocTp3bnM`2x_c3IOOV8#EQ}a3)uR)L+5<F$>k}
zG8qx(D#I)5E}jX}WERbLonV{7QvDtM@i6F$HG7+AqIXCuCQGxQxg}<=Q!p^L{!HK2
S__HW65!gmrluYFh5L0h4F{CX3

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..e76fa668e0ae72746c9a013bce505c2cd744e09c
GIT binary patch
literal 51568
zcmV(zK<2-T6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+lp=)9_
zPHYv#d!a=C)+B`?_APf)8AdEf6nVuUG;ExI54t4-B-`>Gkk*+<gtevE^=jXtT6Nf`
zX=5BRqbV<qTWTS@v6kK*m_vkVLZ-j;m<vzM#sb$GG0|Y3-+aW$3&+lEhOU;+XSSkN
zDNEImNFV~2AnBCu_iM)jPxXe3arNa=J*m6P<9B2eUmI+Iy&dyP%B$Jm({P<azM-hL
z5{&7ydu&{2L-xBgGxj?r_Tl{iq^zqp<Ojql(;N}^w#cc^FR-j|`aI^Z&6o=w1lXJr
zaL&H9-k>u7VZ~v|t71DtugtMb=Q0eLluD$P>@bt;;_Ie={$|fP%f^DMj{<|3s#3tU
zTk%`~U(DGV)H{YhL#rDG;Cm7l`+VPlkAdea$$Md&-EsB=RRT;(b*L)_92}0RP7zWl
zhY^n>wqF~q!E4^&pN6k&-uOnVYe&nA?%IW2QnclM8IXxGbu>H0EMBHFP2uq4DA8lM
ziX()xT0bNQ1wRP2hDEMZo?>ttZ0K!%`)#wV@v}nZXza9pQ|A?KwMu*?v*&m$$?Bx=
z@!`1|yDS=>jubeN{bFMCVuWjYnk&ugDVZLg!t$KXL>@$z3xSWM`Gi#!p|d0YH=db2
zO79ZmS7$#EC;Z(#=!M;iq`d|Oc>*)ggl=63^rj{d{bnq&a!83aH}=%Tafa=E`-bIq
z2J~evKdghjoRz)eDm@(Bab;6%t}P-2H5;$0b=@bC!k=of57#`K2lSK*;6SMQkO{u}
zKjAI7Ru8^Tpiym<BREOzSNVGgsSS^^I?aTJ1`#lm9+SVfLRU(pQuK@asGq~-`|1wM
z^GKQQih6p~dh!+@fkqYj20*UFg<l=?!g=6~;R#qAe1WywAzKK;FMrC~qk~|)7Dj)w
zAi_>>rvlh-Y0X(4$I2M?j0(#f!k8nyI@JUGeanv`lBpm$yv5e;`4}8Zu*Rg=(3=ig
z@7<$Q<7kke`<$(vHsxr#r6Uf;D)983{Qe;j$BZ2Q&SCmKN>k;~Yu3bi@ENdqp7l`y
z`eM9qOC=f1Nel)<2=w)*d+<sHxkpNE%1e80cOL)`wPsJOPj(qM3@kkTFkcxr2+1#B
z#9@H$MK(-9u|WcbcG~L`kId|5GYd&bczeCEOG>Ioi8S$L=EYpK+G@kw`U~?LP1?8x
zk@leHR6KFBG?=%;M$Ccn%|s73Eqn3uV<x~oPh&#sNBJ1o(wq>mGI)lLKAM%l|8Fy1
z{?u<>3>w!v+Vwfs@()^*Cojg~>Bw^VBnL#!#`@WieQf6s2kG8xXeCD3D`Cr~vT;vU
zrl^mDUFegQdR=L}y;cuj_6)0eRTe3oeDIj#=Iv6_nGs+Fat!*<5AzJ4@{L~y2{UKF
z$XVg0fl|2j=*7?l>uP*ZI#Am61e}{qU&?d*RpZ&=*@7t2Tlz9M!?#z8^Fb#m5<CP&
zP&8(#V!uO&ll4E7&3az@sJhbWlEsRA<>>yrx{jQEAM6~c-8Is)!+FFP>A9@L;|fUl
zY6*6DP-3=Nr{sB<+7-u_eX~P1RtvlB+O9#(&?@LD6df7dxU35jR2bX0zo*2&!?ZFH
z3)E0~5A`q@j0++STfGI=?}E7J#|p2|V4u@aM|X{G?@6uAul=ryUFVFP4P$Sgnd{m8
zWS3tsTiQO+fPlTk#O%DxuWT?6ea10w03izz|Mi;b{Qb(1{GKJ3#F$NSbB|EKSCDVg
z#alC+By<*?GlLceYwW5TwYwM5=?FBCZ38sk0}i}I?-2%{OOS*i)ApaXAt$?svqJpO
zgU<Z{J#)Y?)3bls;)f3>T#G<l@(tCHbz*bss?yKf<=ETo`>CiT*=$a%tm&h@?^i*&
za8Lv$$p!ZsArY{Mos*FX8{<>0grI$wr=h3cvdVDIGTVbvv^Z+S+Br2WYWR{nO87rv
ze_-D1@feZ_Mg#E8_-EoP7V8Bt0Qxl4c3p{(<HSTi6sNPxSeYGhm$>Gl)XY^le1M}+
zo47es9|T&X5dOKd`?y5<7E$*OCf=hpgT^nWZQLb{e{*}~o-|!_;#jY$M#^I@Cxi~O
z=k1odE+LaVm|*j5&I^dZn-L`IhA^vpUWKqho;M|BZ<GVvqV3`L5&PT+eNl6Sr*~@h
zjOZ!i*)tPx{G++DaEqHLl1fFD6d}=zy<0C6GXP^|<X91<L*$5{XS^%am79#n`XO|g
z(76A|iQWK6>#L1Fs94YtjO{C!K*B%#q=J$d32w@HKkRQG0ew98b8Jht^_OZ`Wq9gs
zcx^D0@X6<9L97llRJlQ!Ij9Fk*ez0S|CEpsk~rrdOTMDBQ%n79BuI-#6QMIu0Ql8f
zUY-bV`3-HI%vo%na&NC*;C$xo92CiO0a40Qr?RNo8ZfOI9Eh=bm!1(DO+~;`cx<4g
z4Xk0np~P^(bLpo!S;*O$(FLmz5hbQoqtqlH&knnZqS6vCqtq1QN7iYo{*H(4&QuiE
zAOQ!HlU_5u!SFel6`9VVaemz49#8G-yq8&iIUn=sQXoL$yhfQycAl4T!mi7;fkg(|
zy~~r%Qv$F2B7p3z@eW80vg(F~7H3jQ3dJ70D46EB#+1q8?ukTxo-wy+!Ap;i6TDB=
zUiPPbQV|EDhpW&{pHrc>03wX{5N!}^T+ATDzxP-0u=4i2AVy;#i5-|hDn|bHA^suV
zxX=@CW48e|V6ya`G<4{C9`ukE!v!_JR_n;UJ?i%e8m!pb%F{zq=)gZwBa-oLEKfLx
zGj_t(H_Bbtcz_N}*$Be@CMX3#PuPv?I$7wtl=AK9M{|J=(J*gz5fmb3w(A>c2-}eO
z*n>%bt=>CnIhr8eBrA2u;nvET^-hksG?V1LWmjVfoIoK$NtYc90bmgNdG%lV=UPTo
zsLbl_qbG@IOz*yACmR7`1~Vv??Y-N$kqh%AWff59jcbA?bp)TE+8a2rqPX{b285T`
zb}TL-^0=kgvS(gH!4U(Xhm7}5bTtYA;w`8$ua)!Aqy#4s#-tFE8HfHN*mVE`PDb7K
zp}cNg1=$1#3ConC#HXf?d$HAqpeSzjJdVr3ha%y+X9B*Tx?<4Hymgz^3q7MM$s#o0
z*22XkmeS3c>+N)I5h9`KKCwne3NhaIOb0rHz}v&F3i8^8t<tGl;L|zeXszz;?w6)v
z(0)kdHG`H18U-`HJ`}UDgQ4qx+sqRgF5@dPuy8zrmOkq1)Jmhj^>bp`;3ruRTI_&y
zLd-U&f?fRZd$CU&t}+e3i_`cKFdaPjm?1qOkKrfyzqM@}c~l><*$5T*zeM+8*RnOF
zC7&#%c68VnU_`MduKax9QZX;nC<&Ay%Gi6iysugOHMIc-ou;zF`D*BUA*vQ*i+^BE
zCZzu?_lYl$<GGc}=QI3inku=urU0^F*%JD1Ffk_ni$blp)2F^j@yicM-vCS`*j`lB
zS!3K9lC_;V{$&-%1st?nlvlxUSN<P|DKgawm#vSrUx1pmMxj7k{F7T^ILj5GFzsMl
zm(<*;0uZ$awfD~gK<+w=#(U6byP%_~KgdhbOriDrbaF@knj(Sm&R0gl#!|(9sx$mm
zf9^>r7;s}8G91>%&@FO>EL+zP-b@{vbql66CPq&E2?Sie!bx=R%ZL$cP4WP#u~yKU
z*s4O;Ug<oDGb%4Yo9^|cYcm4!=>aTJtwp~@a;GaD2oHXR@aW&gp?Ox$oJcn&uq#k{
zz}!?$Nu>5gR~M9bP7G<qGoFvPlQ;=|!MOB!#^HUG?uSn46#n%fZH);_SK`se$OFh-
zsv4~ks9tvD?MH8rEj!X-;<_w%w<hCrLfVe5zNBxTEHI4~V;OV?P!EeV`7CM3h|0g)
z#a+7MknFEj$Y;hdPR@9xx)J_QklE%1=QpxO2^mOVy6EE=Mocyz-h;Kaj;<wJ`G=B^
zD1<;eNG`j629d(&KitA8z>0!c)rpXHhT{9JJd?tn0f$6ga!!(AdDBE!E)F1wvsElQ
z1BwbQdg`@e(cT3Q(`JcdP@s4yj^Q!9iHNYa9pNqrxdSKYCr>Tp78-2>Y}*aeZ0Dq@
z>xc$!epC|J^FXb1^3SAg{8!VvpzyHKR|EY`WB#{Ku7iDlR22m3sch?F!m!|9zydw{
z5Uu%J`N%~BoVX~6>j_M|Wj`&?HkyjLGuq)Bz_XOG(e^&~uBRIO7crOcyBN+mUqmq{
zmeCkMVU|EADGnkFq8JR1FGrOa1xM!%i8O8%K=qZkkAVsJe>pyKZm7o3&YAQqmZd;s
zhN-yWv#lY&5e=@2kGg1bknAvrIzHwi{-!CjyWz8iEo@cNAySZCwgHnVAUM17=SM<D
z(kat|z!|(WaPWeQ_pqE%(F@`kP!XQkLNNqvi$qr3)t%y(XvR6l{+9~Uq>gB0_Y@G`
zoSQ-t?)~52Wt44h)k_z4G*r)0Hr$`9XkFRFgPg@*!6emyaRf$SIdbG;y5mgt&DEww
ziGDIjg^qR(vk-P9^7%aBi~OHrE_kH~vHyjjhNva56(;lwM8k&;nIE?M%dH{iK=dJ7
zC#;m_q*0e#A*x0+Cna>VzT|`UPaRtGxUY7{Ez2VyR87Kq)W)IM=%jv%t9+#Y7p?hs
zMZFk#gvfb;xz2k=A1)%AN!l3cSGwLx^K!QoBVN2=0{kP9Kbni}{%1X}(rjLafe?Pv
zeC%a@g@n@|#50i{Y6FOim8o43>isPhDDN~qQ$0KO9z}?qgjE0WyeCV4aIr;)XGK^Z
zhn@cL1aV<Kh9qvX&7pwh8kmsEAsO)}yTqfxCqU+hS59EdSJ4xzUcNdG$3}VBYDTr0
zz8q@TX!Ue=)ry(=09}Dhm$ESCK_u--lDp0a?~&5LQ3PGV_mP>OL2)1tzH)}2H5E9a
z*h?BDRyg%5_-%3-YZH8Hz!&fqi?}f9GJF$)Rp{5fOWWn&2toa_A>oxE@rf<0;!6Qv
z@n?NhtHLSG)9wNw?jy<z(FK)Mx-m3c^-*|Fdn;Y-Tv1yzb-_4-0$dI*C*`4U6FlS-
z8aD7q!5rrRk1JyD%E`!at9pciPjXr*yIhN7eKbZ~T-E<B;8~I2IlMBhyBDMx4<FTI
zBWHGI*Nw~Wp*ok+iD$^sA@JHq^G=MFbm6TJvBmS8R0w_co*9&B*RUF~{B8z(T>a~D
zoaSv2df<icz{$3%!p5*d;z(O@c6C8f*%)I1*UEv3b0Gi=R!ghEPzi7G>x6^(eXw+x
zKHL-H$vLOI$%-EG9Vu~+x~W^K^VJI-Km);&;8JcoqTC&?07Ll~NoYBE`#K&Mg?-^|
zJ$)1$Kl}Zx+C<`}ViHdKYO5~OSJ4>tI2zO3TAtA*I&gQ<*5CE7H==uYrSAkwE)C8(
z(G$`brXDJ+Ubg8TcpN4%HbtaCe;;k~fL=%E;&h7JQ!n-vrH-*g)*>$@Tp34aPYT45
zI<F5&PI>FTSMXkj!n$j`7G%jcl+-_j6?58nVkRC+7EHl?5xGKwX6!^ol$KWnGTaNY
z)tXQ@UY`1eU@^>9!0df=7O3f{YT)x*cAy93L+P08<Q|m6L-LT{9YR^V&?Bm%4+d>t
z>F6xgZLFUcqxS-Ij-TviUct~N4I=rJW%=hGDGTF4Wk7oMO?>$X@8lANc2e$*VJ`AI
zOcyYMWRs`V)T?;jGa;zmbwxMxeDRXH1#GGEW)wsyfUtKL&@iq*d=c4)>2`&r*Ex6D
z`lSV{Jv>o+?O>6yZ_!?j-@EPoAeo&M`1wk&WL6(=V1^7Bem*cgU;b#UKIxog{w<Wi
zvA$RXpfEFF7EWt7ia{}jD-KId2U!W4R<_e-(WeW+J;b(FOfp&t5kZEb#sQScCzbS?
zNQ}gPfUQm((^hscsWK;8%)P?N$i5=Gznh7er8Z#ypR?&g&GfI;$*D^Je^33dRw;Q^
z=Z_Q|)%N@KxI9R=N@sl5&r0*w1WB!2>63qyoth{_el2t*GCo^BD*B#mOPak^ZCQUJ
z--uz}rIBiXJ$#P8euop`7=(;F25`SR6U9WG+VK_`Mfb#xbHG9XwC3}!<rK(Z2X;eL
zc{aMSH<xnmr`kb_tbUHqBjpTia|F24F}jN!aZEl?py%<qs|GYCF6j@*`uLyhFsE@+
zfF^-A9zgK@;g?mHyKRrE^$%zJo9;8MPK1@H(!qxcVm*`R7l@ncGNHXuEHFRvVgmhd
z7w|u;UP6w2H(^^d76=vew;irH&YP-PRpI9;I=K#Lzl)_Lo0Hq=AyUrg7iU~TP^iGC
z=zr3n%1OKJJPvbWcNwsIAwun8CB{Lr;W4K%*32$ZE*9-Qk~U`F@I=L179&Xdwa(N|
z*-4O({@ov5i+RQo@lQ`Ivyv6EF=dkra;dj?+yj^t!DDw}jtIK{$M$~xs0S;TQ`OOH
z@0$XtPK<=NeohQHVi(8ylOe{yC$U9b9tD`jM8hqS>bRb2`TyG9DNQaQoLOcLxC#m)
zI)BgRw(u#xRa98}t#!C_NyLC__)5(=z8iz^bq%A6^Z|ewHxAG*yzNN^ABdz@bh0k=
zliSUMua_!6<K5hj!sh&<-pAsV3HNfr))uT=Ywd5TBO>gnKN^ypzZZJeuml*RI1{vL
z)ytnMDF{i&m5Q^$G>D8n)kLyLB|Z2F<sa9^IZ<Lv)0(Xw8Qtr{gUceV2j<4ti_3#0
z;1aT^@bQ)K(di<AJ;f-1w=0kgehXNG3TP=GYZr8hs<*H|C=RI(!pENIH1Swq_dOs%
znX0(>^qlP^_vxTFZD?*P(bX&2+#xP^wi;lurp1(zMaqeC<g)QRWMjHlXZ&Kj!|JVc
zo94g!PDbRii<;-umU+n}ER<K7{qFcIN8LDEkNap`jJvQ-b|%PXSl%%V^X;BRjkIJ~
zg1dog4HbpgcZ?<cvbCw;8?tq|#G}uH3Z!2z?gOD>^S-`eSXcl>^gO@tBd0wAX<?Yt
z1M7%1UjUVPxbE!clOGHT=lxu>Z1vahm<_cGvWa-fbzyc4zsEUxJb3Q6PhQ*6-E%H?
z0yhl$ycX*SMz&%)wlX6koC-KkQBOQ37vBOQHU&Jjk>Ub@Xgc+^MxBkkO6<j3wfppH
zTaur-?wvtU1N*`6ORsZGUk~+4GEdg!Qo+b98fmN?C}tC;DNT>x4${rK@6&>~&3Uc9
zV#KJOx|n{#+hPX^%!g~FAG+ICXhSHBj0A()Lg4mW5MhjUTd;j9$E!OSe*YiIcNcnc
zIch#Lt#WIxe-9=f?WGk98f+}NJ^Nc*3hkKdN%wNrtguwGh!?>8!gsmY&(ye<l7QFS
z`R7zittKU|5`Vl;D)qij%YO3rBzzC3B;(*!j+p3cdndrX&m+(!W6}+TZ|iE%>v(D+
z_157_MPh?DJP+N!h;H#vuE4?SH(n1t%Emvy0fL2UO|Ai<`T-4QH|o;1iRrE>w8_tQ
z$Lz{!Nz90_!~KRHxmr0`N`>3MO2n($w}4NXuFtU9BfV_e$%TTD(3=Cm4&_|PHZ|Y|
zk^iQW$gijb<I~Py)o-^K8D*;0+xUwt_Y<isYQ^phE!GCM3=J|Mgk;T+E)KhUl*F99
z9|BrB`3#ATrp$iBvQfQ0weUJzR+mt>|Mnfdbif7T^q*szbt{!LXHLUe*!%LScT0UL
z!3V^>aJI9U`U%41oVNOcIov*xhaKp`PT|XGQ3d-%#)2Mn)oAV$+Y=BbQ2gP38cW~=
z7^d_^#NoHVfbal=DAd2^!0|iTR`95HmH1E>?t4|K@EIz&J1Vf!Dp*}MTx-Sb=rf{L
zF#v#RUU)tpDIih8)Pn_KSd&<Ik43F$0EOl?BxTlbgJxkVEAhh$pzMLsRh((7{FwA(
zN=ySv3tO17F9FGGc5!adaOk0KoWBj1XI&%h8kpJT+1XxS|5419)<-YvyB&v<cwzy%
z%hl`bku=v1x=A7v7>Xo1tF^f<rVDldzNTlgg9Al(&6JyMSzZ<-dc|R6xQ=SqlG=hV
zI*m;5F4{i{7#7D=y>iVv_Fg;rj%{bA0QWNPnuL>Zn=qk$vWrg1IvH=yGK7$nV0jD)
zi##sNpZL^@-yA!jq_BbyZw#OB)&oS-r(2vt2zsqxB3jOvI;Y|)UR%T{uT@rH$&5ii
z%8n)DrqtP~GPheOz+`7b!}H#rYA99(+>>R;C*9N{Vqd@Rd_TBh{NsQTPg33BzF@WX
ziW9x0`Aiwvm4>q+hb8++b$kx9+stb+f&@vtufPb-QNX<bt23^?l+$ZWu?9EH%P(Cy
z3)R-TbhW9O!v$D@vkhWv0_x@*NF@mZ_o!iZG%4eYrGpn?U~s53)3ChTxV_ML!`adW
zNeoNYOZEQuP;iQ19?s<YHxFmIf(bWhne}1A9o;@>x@2ckTSN3|wtpVoJh-_%GX5B2
z;Nxe#^52yoo^1DU!JP2Udje7Ytx*3b`+`o=UDj@8nT^?8#06`ty|;nM;)wgpYqJoE
z_-ncs`9@^ly$2PVX?|qpQV(`D#e{h<KI*O132f!P{CDjMRhNNY%L!lMK~EQQDAhrZ
zEBmQH8$@E~_ZMLX@R*Y`R!arOfHG{3LW0FdY|Hhj>9NN4n~xpz!A*arM_a-z*;Cae
zQr*@y{7C#24qR~02eyuBYmZ5aB~^mTF?g!p0@WqOh3+3&O!DwXodTnDoS7*d7av&m
z5a$7*Fs*OV>LZlUF}F8}x{@QA%K#5o_{034lc#(n7K84T=v>iOJbNun$Ga&s-<t9j
zHklN<5e*Fs^9zx9{s=Y$c~mbLkVtAuxsQdF+-FucZ$54S5!9Nt`L|YVv#Ob@vv~&{
zKgTnb#ERMApTn~NdTA%Z%Z;c$zETU3tV|a37Ku1oc~rBl9ON0Uo@k&VubPthP4~l6
z+EJ#`6ofnfeRZto)Lo^gFy3({c2Fab#Pv4tCm0Z*IT4Xc`{wNF^D|JZe68S4K+>0J
zj|+Bn?%;?aTj9E1yW)<O()BI|^rO_z`?aTr_tHR04gsHef(Nh|@UL5K)Kg{1=JZ~8
zO?l04vV;1r7}N4j&AD1DTykuOMM*6;!bKEZyCCiiWP0Y=pdKGe*QrQ+C?)2h)c^b)
zJACmeU70V>Fq69Y+ax3_2&bM=ec@%R5Y0kjS9^Im!`22p(4}UT&h)hYq+kwR^UsDK
zm>$S87Bl1wqP@?Qd~jgb1lCPB1NyyrIl$s4oDq#=WfuKs(K~H89iUJ2pT_J^P=3A1
zDB+~y<D+^*fN7^IpDjSP^(Fd9!UY%dXA$zbEO#)bgU+>~h<C%Hf)D?=R?-FM7Mepp
z1}&NxTfTCSpDVNTgyu=OEV|xJ?qnN&XsPIXdmAMK9X=6tI2php=%t^>8>tzn5J76(
zKEP)k;(0xuckSHC6I4;TQs{cX2X=%F<yqyIqn(PFR-8cY`KvLx1|@Gwu`2=9uWm03
zwZ6<R^adI6Ds2wy+Vn39?7zQoHA*@)|8@Z@tU;wZ0IoduUfp#*SB@T{a=X%?`RTSh
z#;2F9(TV9(((8u9bb=_4=2nuT^_&?&g1(<;;wcK|-6vvuw*6~5cr^8+u#ozySxhD4
z*r#*FFMJ$m9PHk^RkliD5`R7(bmd`TCHx|^cB$CEWkMhZh}~PX2&n6*`zLbv&EG8o
zET2-<n(AR0nPM(NDohx<SiKFUrYVKU2D?!4RP6nEi!XlDE&swyE9Qz`zi7bm+y(fv
z%jj;P;&Q!&8GRS&DOcHEd$L3LN$*tv=7&^BBsyg|9Y-!%37empdh(#VAq4CO`%Ixz
z%md2lqBHg4CXTzUdDOnh`o!TK<AV+1kuv6ss_liXO2ljz+`A(;w)X@VXgPS|i{$Qh
zcLlW>B{l`d|J<W@A<IT)H%V0sRQ|VOkH3bXQZ)&6u5%<Leoe&K3OI`Kzc2F%i_l9u
zDX4HEo1=0OtY5qMCvr080mp4(3OyvXOLs~<Xb|bmuSXv`DGz-NnB7I(roS4IQ9l;x
z@s;UPUnf;1o^`|4x}Be5aFB1!{ZoaK0KPep;+q&_=eDhu{YV=6ba28~MkOd`o7<AL
z6C`)hn&(u3AUERL*VcOKc~;Y=bXk9;&2uX<<%PGTOJ+Sy4x4oFCb^MVCpXTta@7m;
z6YWbxXMBs5rL4HV;*gZ(?}eg>4A4AVcD3^Uf2TKX({Py|N=L1|M*@zhv?12h8n;CN
zS2lo_(35__&w4JB$+`ELw>H{2Wm^e?ws^7;rS6wz#9W!)^vVtV9k-hx!PiLJNetS7
zj&h7XgG}otu;oM&tK=Jc^fbC`o~K1<C`lJ#^zYZ~@0$!7*X5ZUY+s@X%qVM-7@-@p
z5eBsMBa>`5g3i(Ng^Ikl!%&XCQqEHQSq}Gzx((gRouVi8biTmIvfwOWW~BI<-;<PJ
zz*7!I%Kn?eMX>t1^27!WS6QLJSZTb2W7&V0NYk65Qm{~Nq%LnuUatcEn8(axk8MoH
zPI?oDnL{GYhh2B86xf3Oji4uoR(DAQE^@FEJ`XN}sLOEHu#--~3~1Ixf6lbGNi;9S
zFcVbmTMc^t*6ScE<ewnbkSf#@l|GQ;Gq|;{d%tR22Wd!zZ2&mN_VJlhx+kFmnfh>r
zCY!jtK{unbwul4V+IYcXPren7@Acs`#qIKQ1N>g7{Kz{0jZrKcsfSl^Q+W%AP<<~T
zH*$1b1~ro{FSnx}#@1&>0Q8bkq^1(+c(k<LadHSSgbmkk0@XK|Mv9;CmP<4Re+IwL
z_%kcH-)G>1M}GXz59>Ghgj0}8D%LOyrb3Qcx9yS`+L=C`vfZ$Z*@Aa?lPEM7=cXj<
z;L#({qhIj>y`(Z&c&tCE7|HjaA?}Y6y8qt%zh?_5`c!epg#ukJ!Gl<)F4@0oc#Wf=
zjQj&z3VFG3R3H2M9mdPD#5X{?uQ7`l{LxwS95S61k0PXzG9@k9FiO6YWKJ0YoNf~I
z@;~yG^@CD}$94b>z~A;i$sIm>VXGeg(EfWML>cu^`k)P~9X5lt3ee?t4tO6j$w>tz
zD?>e$n}C{1+jsqQ<XzATwun;M#Rgn33j<C~4V!fdgsm~*!KeOKkKam6$hux)Xg$@I
z=8-UY|GDhK`IGTaEB7niHUIjL43T7wX>9&Qaw<938iX&NR+@9huKUdl&gS9NhPrK7
zcAHrboF)SEC#O_w1N3a}Oq9f$VKgeP^jM$eJI(!s>dHQ!^!!a&?n?VPYTQIqW<|!t
zBGz~Jz5I?@>!1EIyGdMSi(WH+m5HU)>)QklI&xwsF4TlGAhO))Zo-|=k;4!=tlmj@
zN3y-M7>IYDS!LXh2)r#mV1Q~z57mSJT$r-?MCtlWs3APL+?|~pTyiGo>2o<av>;@!
zMO2Xt#Ka+|6C3<?t6aho36r*+N=-5t=;PNIx+O|8_;olgW^*8n(>pT%F`ISkZah&R
zeXyuZxDdvg*;gEs0kGs}ey)AXv6cS_Xh}xU5~rxo8FQ@nqQswRahs!r4pahKj*Tx0
z&t4g+eT0Woa3)}NW?HEs_QRCu4+ciqRhkG*B+b*4Zt|HnNp|uhJ%-uC^Dl+QH5f4+
zh*}~BdTzLcyzCI{7Qxe|UBU@d%n-YJ4d}9R9EBx;MvB`f1q~otvw>ZX1A{sV>s``N
z47$S5ur`nQx;$n`a7oNh9K~Y=_@C1h>>9&<Daj_a$NKsX>V~s?$h87j#-ruY)*Hay
zpqx1H(@mO@DG{ul_w5B+F<rB)$|i~f2awOw1gW`pT4=Hbl`OS~v87hWIc`!0i9A1x
za;k;>>2y%aa41-}1<dEz823AIVde*Ei6I2OY_hgVD%CPGBAMG#ix_NpY<{3Qa1*vY
zXt&ji7`Vw^yc5z&pyd;X9)!Se94Eqxyutv`ra|$Fv^`FvAGj#;)D((4$+wI}?Sb8E
zBm2o*pP5AZoMuT&(B1F2YY+YLH%?%5{19(o@Iw+xqin#|QP$Q_e2~vF(8r#CoFS8Q
zcB#f2dKs{lR~;7&$xi!ITw-a|`$oqT9)3)Xfm2CeRE{^t!V9Fl)*GA!u{+9iUb?F=
z)+b#z()t&S!idT}<3j_0+{hS`^A(9i4(ucyM<0O6x1r`#&GiiY=&0pn5HBvH!we}l
zm!ZsTEX^8^o}^9CmaR{ACp-1pC##~jAT9M}6<6B#rOhpGF=eZSRAHsRegS263l9OJ
z3A^3(aeH~!JH*n({S^FfnD6h$I91G0#lFz`Dr+U|Fy1CXmS87ZS&HJT6M_Hr>)rp^
zXG&5^&(0^Uy%nEM3W*MZTu?O)1+%XL+@|`T3zv^0Xv94Z^OBrcpSPk971C>>bltl>
zN`+nja5^wnz-Po9je9WDeBBw;qE-yRmF|B9K}NeXInFh;2*+MCQ850*&#Brz+k(yx
z1}*pW%ukmVCmF}7IZozUFdssA)9Nwohf@7I6HASrtcYBc9f1iExsTC;A180iO#M60
zfy~lJ))hL^#lv1r&krh)f8irU5*(f_duhzubKTJ{u+`^FN7#bI0);3J+?O;F4pX=8
z0h+oMEp+=G7#fN6_L6)eu~ZP^tWV3*%M35OCgUS;IvgZre<tKC0BsIr*G#x~YCk(n
zX3DqRdmZzARmhQr=1C@&&^_Fy=Pv>MaO}dgD^m&022A6d7TT7}73?MX_n65SjVGvl
zS!WZQ2%XB?SwL6Z4PnHSgg9;dT=eXyHjQztnhhfps&7+8Mb0wIj;CxeCKEulWf7Sq
zy3yRMnV8dUXYFE{J~AAEva5>iA2P!y8?+DHf@B7@qE^OM!#fbfY}R;@@ocM>vO24}
z=)Bvi6;s<K03scdv#JZT8=CiuZCNQA)C?BMBRvR*!rkXG11IYR9H!K0U-Wf@VUQFd
z0xWE{#`*&>HKcitQ+yh6|4k58gmLx_SEk7(kpsam6GOfkM6)r_K#FO!Ie-4sF)wXU
zgi9}zL(g7mKveOrks+!42T0!7x7`Ya#+K4^PcDPqeFEMlZR+*4vg%S}e?VE8v~4zX
zv;Gh3dL0`G)u`!*|7aQ{0jHNq7nWkDay3M)?OX|6c9Ek+S+Lh~O-G{LEOAYkY%40=
z-f<>1e&YqX+uubcBn?Mtoo!*cMd)T%YvXVPES1Of-Zgp8M+8+MI6Yud7m9}9-s#Zc
zd0#{mv%`I6njAt!`Y_pxn<TH65RR>fpcJu=S=sz5P}nnd9zU(t_k$5|{%>x6_bC#$
zWUlY2??ow=9J*-Bvh@n&cgur@%?en!oUq*uYT}(m@&y3_V)OP&KGwvWe@>m1d?`UH
zq5$Nk0|5nCUH+yiGDXZDVlJs%LZKA(60Ke&S)!Pk4C#eNq|5mFvt2HcCfXx}vPwNv
zYnU2@{WQj>=aIqkecds_#&}3-L&f3^p8tVvV>wkQ2TU1K035rkHFLMK_%L0uOXM$R
zs+@t|{|0HmzouV25c*5JFTwq#lX92+^=Ga7|AY!h4diC8j}2y(sLBxvh`_|ZOIB{9
zZkzDX$O3>D_Ch{b!B<%JORgRatq+eOGmh=j9=4%^qr1HQfEswEiB>m_Av|jSPW9ky
z5*3snS1`D@Ul@k)hMq0U{4B;4vew}T66q?iO;HQna8FiF)X~DCPY&}!Pb;p7mfTa|
z0<rM$&d=@w$C8jnstv$Rh(ue~;giTchWL@%Pi5XnPL`a+0!i$;iY7DnGKWY_q{&wA
zV+|%7&BGM|i|w1VhDLuVClZsX;EROr!VzAI{5xNgMJ3D0AT{Td%iZCy^mFqZYn5Ab
zm4BaBuVp!eqng>r(3nWr;VKqu&V#if<{JeILx6OT$f|wUN&1s`B(cQHZvqa@%giXu
zo2=C?h#Z`&StfkESNf+sDQP8fXQTk6EHlCt$|I74ufDj1x(dD<!(lN&xMD2F2fG1f
z#N3*UYoa?QJBk3Qd8q{-OK6uBl<;+WPEqlE=ye85Nb?9a*~Pd7gUwdN;uL8UeF;*`
z;^fkpK0z%0BS4tFO$uL0uh6P)tGy;-nD8Tg(GJ~g-rA;;`HV{d0w??+TFm#ip<Zr{
zZSfCB(N<dUtSaQD+`JIAfFT=O&N#}nG}MznE&0JuxgCZO9qAl6Od^i{kFY~j00$5O
z{4j@6*aodNdK#URc8i7LTM3U)OoZta?sywrt#K1R*ZH0O4Q4laqO8s<;<tWBRqc+D
zg(1ukytD*_v;0{bZpyGSU%pcI2u}NCpE4UurHfM_j53f|z2R_(=l#gR2`S$_vgdLQ
z<L+#~_4fzdi_U(;qQXgyL9+g+i%X9Q_kmK@^0*Qh9T&f<*ed5&Be4}?<qT3TcH4AL
z!-yq^5Zf>{mkgZNBbbW4g%>AdV6z(MOAlVYhM;R=zt8FgUL1JE=So2pri-R&5l0&B
zF5dU}nAS~Ay^c_&bL~9spl04uVqDd7!?NwCnb-)FTJuZ!8kSm`2-+^uLywP=WK6D8
zQhL`tRMrq_uA-R;!!Fi?M4v4765thpB3pA~0Z=Efz{g*zj}(uoF5fcWNOVo$&K>RI
z_TE8^ScV%r30(w5wKMl1EFlb2iq&AZ?N%Ik0Eh&5O$*68d;P04C3+4-;`JnxC}a4?
zUxOp1bv%0}c}x~NWCTQz!A2QF4ZFt1?^5c}&3N@SXl9n(-%$f=ggSJ1l&8g5k{&9z
z*%T9JPqbqr2P_~N)t=sbnt{7r0Kcy$8cyDMiU}S!iUm207L_V8L3R3{9Lg)RQLdEI
zpgEEF_ublkx|)~>jzv1U!<gdIBJmB0HM~H`4wg|M9Gs7+2-hBdU*_7$NyKWJ8kYj*
zCV_0LUqiUjT4{amoh<bDy!~L~()u9Lsj4&7?jNA&bY~c#{UHd0LItY|*GCEJ?v-g;
zGJnzRT(?mOn%dGuss1Gl%--cN<7y4-Sjm&TphHIik>d-L*m1I*($$WY<OBpZ<8Urx
zZEefOqS$`A)FU_{@AAZ&x1LwO+I^gxFnifdGTy)1a97~$h%nlyP03>SHieBw_aW#I
zo&78@^+bpotI5NwM4+i=c!=U%^z)}q4Fue|B~i6>A3x2!cpL_qcfT${+-2uaK^vA0
zLlv!qVJxr5`RR~~23uQM$Z9riE6M{ABOCtJ1)AnUHe_7<>YtCPB@-HqlyB3t=RYYW
z^cHtYQxg+8r&%;g+$D$om5zcEQ@ma#+yS_)PRvD()35}OcSXAe9#7D=U$RN+T>fq{
zIr4leMTUBh%gS>>TNcXP3U&%L*>jz4xzJ^ducTxy3jCX5M9|jU>m@XufNjU-*HszA
zDV`pkcn0LdWHS9;+8}iQ&=^<^lZuR53+k2kL)MY4MbUE5%y9s}c`R4Dv3PJcvt9l1
z46s7Y$2x7!3pWMD(t>Vkv(;vdzjvckaT33P%O8uu^!8+a)=0s|?{$c7sD6tJBKu=_
zr#=hHwKt_yS8RADVV{ExaSZn2y^tC6a<`<?DLd<k7_=|J`}!bXK|XPvhHIVqCX=|~
zB!My(btG;h)7Pa$n6<2Bvp(r#OiC{B)*@IPjihd1YDVi@p+`e|eawC4Ncg}gI1xo@
z1J~eZ`*01;Ich_3kAOvpd=*|D=V@m1_-MxeNHK`j8IuaSU9{`7lr!Z4S$RwRlKXWO
z1>F+ed1TuF%8fGm6@Ki^cq|hA3Mse)XrF}GO77UY8IP>oPp~gi@`^2Ee4S(D7KR~>
z!2vUJn#{c^9!aXhdh5LuqFp>O3w@;I$0U2I)kmH4So5l$a8HNM%LDz5gF8Q#9w+H@
z!P`!;0qRn-wA<itx^Q;5SF$&F{T4z09w$WI?r^7QceyP)Utl3xokPJ<Su>7{D&FxG
zRNzZk9!%Vi@#AA{j%98##b-dsJx9C411q*W4(oQmtJPO^OMCXxV=kvsx1f;RM{ICl
zdb%`pTV2eSJemS%(g0KA6E7owaCjsi@552v^$)yG_H=kfFo_>fRkS)`aOK<UYpR@w
zqhPFnzNqN)Y%PrQGz55+?1=CTvndg;$vB^U)iyt&KDw4ce0B2V>G?hSSs`nY6NMTc
zEKA51bln_SswQ?so_vs$5pe<i)=$A^+CIauHmKjK@J9IT?ikS&XXhy;#a_{<SLvGh
z$U;_3RTPxMupJ`$yt5a`giMA{9Lg>xxWAAOZTTf(|Afrn5Y3G}taGwdF`^RS-mIbY
zr%(}H6SLKwyN9L9Amez-Vn@tuw7b?*BUTA1J6llxlHFDTh|;vUclQVvZ$Vs<IbtXp
zrU4X;MIecamw&29#YM?&SM)w#-Ew105w8LyZ~T%EoOa1BtoIB_{jJJ|$n-izy-tin
ze!0CG|Jd}3h5icIpO!s7b#ZD4Yg%{9xM*a~ObCdi8-V@yxeJ_47v=JKF#;1|F2INZ
z^e%PHZ3c=PN2hEnM#Y)$);#}E73IYR9$GW4LzmsAjPNoRm6B}0o=AnDBC)nZ$TRDz
z3@2ozZN}Y<;x0^T-`u>le`$yB+qouMA<it+z!`(71ub)-s&9Fn3EEK(U{0inBKYj6
zd=at~Ze1>Y&9G|C1OL<M8>T2K|K3G{-xr34alHME*8+8h)uk9{rnPR=AlB)Q=U<fE
z237^P+HQSfqcJ&d9<J6xr2rcXiGH6bpa**qLn4(JI+Om_dz3(SS=QCb!w4EiFM51K
z^l7VD;Giq#-SEA#I#)M}El)V0{feE-m?T@uB{Yv?5uaCu1y@v>R8IKfPv+Ls(E|tq
zlF)q=ty+G$3g;VtDHbQ&WFKa^&+-2R2hOnGZEQgaA=P7&9Dff2=9T673xi2$*dWfC
zOv<FhX_+dyyy<s9s%(qNI)l=_XHXpP&KHV^D8k=#wQ=G(Z>CK=+Wn0Z)Ve`<H13_x
zgT;GMg6r?0*wI#g<MY8ArCeiAo6G1@7<-?MlI`8xO$rhJlP@kIECYEmW=KS-a*se+
zG`e%`)WG%UBTf9?y)Ox?ksF3%2UvOv(~%Xbt4QyB<Id)9Pw$a{Z(Ohm#=}C0*LOr8
z435qf^Lx=6PD$8u#l}Txg-7XN{+r|5nM|OBk_Tu*`)p0%@ODv|?1_y^(ed<RK7x_S
zJRx3-36C$5pyo<|*{M!pZ`HuwJ56eU=K*Ia@ivjW#xC{r%FMBoMr*o}`$_U3I+b=+
zdtwIn!YZBUk&R=DoP;Rdu`o<>H0hGyn5XmV%G8PGXY@k4Ue3zmq44L!k5b%a;$GIP
z#$GkhX0&t+DKG==q6f!R<4~owgS9AZh;~Dl#h~auQTs(!JVWihGCY15<cA;KUgPOC
zla49K9+dah_rb?3O><bWK%%UOqp$s@2ezKjnK1ys2)y)y%88V!2Rt5=pszg~QdxQ)
zhu(+~`cc4b!&(L-zopXF4+fwRu5LhP5BR%trNLZn$P>$idcnR7P}C5vYGWb6uqL%8
zjX>cni`?kXILep><t19T2x{BOPu11&awlLPx7=!7HVz@ctJ_G0-bFLRxkCYH20bgD
z$~8CtYTo$BSYeqD;mwy)$4rXWkHFv2?t1MR-VA{k7?LAr^g#%-uE_b1wV*++c*5s2
z7}*Lt3vz)_HM#Xez&KwdnQ#J#o<;vp$}N&M<)=FvT5}i(1}4BK|1Cn@fndrnhmjLA
zsCyM3{lNz|x`lVZrt7>@&=*{1%0<rOj8nf<tl>+MX5Ljp{XOQTkzAaWZ#P|x7@_;}
zduj6|V{m;v4ve5PsSEE2+ZaCaMDzl3j?a;X?{;kOj@gC#M3KsQIM>O0>_Cdz3EGQi
zOc&uIt?S9xST^P+dfh~xOZfsBbqE2Ts8mchVFxM;O582D?A>u<ZM>!Na(&iNYnv6Q
z?{wKoK?@-i?Pn3=Aq<nbbNzb4@oVBExcwn~f3kZCEL^6tF$bE8TFE3-6|OvxmPE|+
zrqoEnj<=McO^r%TED^}>XT=$u<wIa^w*@@e`n|5+hj-*v+wT9#9$bY_Xv9IV*9!EP
z^@A%|)sM&;Vp-8f2Sq!&ZiI<N38%$nlgyWH6ewaDs#U#ox-54RJvq8pyNS#!%NvTD
zslp4S5`?edpscl_2@uZs_@ho?TQ!9cytO@~ky!yevK&Y`i&hDb5}$#iOS!MJDWwjy
z#4?O{uIBq6E&PQ*kJDI?Htng2ZAUTJ0lC_wLgkxaGfZHqpQV7544lEYVT)NMB(c^s
z-#b`}%-g^5-#vwWDwQp`9@{czyP|IDa3af2kp_a6;Yd?_Eh|sL2!F6f=kD(GBP6qK
zr&PUwQ_nStsi+$1_X95P3na0r7#0~x2vc6&6E^l5sHP^WlPy-mlmGs#Zw^{zL|zQN
z5VlKeL!=nH7Hd3`kmCwZHRVgEemA$*yVbEk>7~}bs4h5okW)nJL0u0zI?=Pio0zhk
z;To)nr~R<t;iX;TMX;X+z>F?tizFRCC<@_q7tsX~Qa*_cTLnAQ+ZcYslF*X6x99D9
zz{)v(4A~kAhcta-&7aVCX?tYh*&+u(0x*|vwa>&$YF2Mw9D-=N&<rRou%Ecz-!K!d
za74d&qXRpTpfeVT(aC74RqQf${gZ+zl=S_Qb;*YSm6K54=G^ijk^Lu}<|`6`1ZZuf
z-^fmE9@a9rIaupr5Jm1va)_AX$mqW?<cH_Q%dV;l?L30^pnkPxJlYO?Vmj+y7SZ-{
z8KMyZ(43fg0h&w)L1KPH6f->cATp%7F%S%|zK~xojF&zw-t0kNB_bc^!*w<6&^L4=
zPhqF7%}9Q6U#8*J*5SQ8{*@~S=HHLoBr^(m1k27sbAf(?&wXiiKJR5}R-QXDzXv1&
z5{ki=I6_3nD^ISMnGm>_?e5)6qB@k_4T9C%eQ>J@HA=d&{GK;^Y{W7riA^2=VNA;_
zqaozBJ~=b`aSZ74zGpLuiF9z$?D1Ehqcefz9>bE3q#rn{e}W%MnqPk>U&9?#xj3yA
zatkxRx}s}7yd2X>_I1m6n!x?dwg_IyJzwnzfIgL!n+wQTSU7;K5RW(%*URAbi-LB+
z>#6YH^*Wn6P2$JWxrB&I3q|m=+6!HOHMvi*?2^tbSgvM6{pn|p{MQ%p_a-~0!DRa5
zJr;u$2cKFJ-70i^4yk5uJLhoNChD5D^kLa^goA`ZCQs~s+E%Ti^9b0(p&OCt4Qh$y
zte@C&uDDpjVp1VpubT<GOIT<4L#?eMm}mP4$52Q1y>yI+Xw}=OzT*t!loj-w*cS<=
zE>O5-rrdYEnOr$kG{lM6i=X(XDuw3xrj(3PkuX<}l32?O!81H3CHiu!P)yQNG2=uR
z$t-ZQ`49`#a+l!^4%$|XotW{Olt(Mu;Dr3`B-Glq3;_cad@imKb+)I$^Fef*rh-yt
zu=f7C3-|<Br)qwvX}PYSY=UBhkyIlQA)wx+lYYu?_7{3KhHFoxr%P0$M%?&@GKV0_
z9<JE}zE@T(Pjp~~-)}=&&_(L4#)F_4F<RcFWAM!ka6|_+=c!0@so;8j85<?Kt_d%y
zR1M-<hLmAkZjY(ywDp$2d|!!z9q;nVjv}A=)=g9idweVg1m+t+jy!pw?YbL+%NtYw
zU>&)=9FG%E^0iIjCwWWakE>@MQP$E~cY?Z1Ltbk6s*Td!N^yaDmfO;%`!houO@FnJ
zB=_Z0#%mi;%lI_O&{fA>TnR~$Y4BZjpZ+)u+Q(|C1bD}N(zon5B~*}2W<)3g7_)1N
z)SwRnd$&Y`hE@FzVRbQ%?5?-!7&8#nF!=846Y~4XfCLhh&CR^X!9pk3ZZbgOh>Z6(
z_Oez18g_ar(UE1yJB-HK3mXP$WA};}Aw}@gde1*gB4Ede%ET~Wo;T@(>!@o5%f?%d
z<Rh^q$;xvGT9UE`)?SPrj%&1o>Le;EMxj=HJ)`=i9aD95taUbn=0<m|HiZIs4pXd@
zp_o!q$!#>E8WJI@tmhKlr#D4lxeSbkD$Em9{wy3dV`tj;Rrt)6VNC5q@5{S2M)(N#
zzDsm5ZK;S&shBtd){4E9iYcAi0^=MR*6JFXYKz@OEzb0>CPBg?fiZzn=;tDDUAsCK
z$i`WN=I~I&$IEQF-@hjXx6?1>Uf1C4H#0w}mlHf~NX?%5PU2QecpLL~Z=14Tj$`&D
z`&n-JGtHRYsK(30Wa{;c+M6Gt<_2}<85-c6t$eR7DNI4+05w3$zeyF;W~^SX);iA#
zq(vxIVwh^*2k?2|b1?p2Pv~O-K+NYTgspH2j{P%|t^hBmG1L~l#Q0MB&#60k4$vA&
z5DuM-wqP=>y8(bCU=EwLp{=v5i4GRRs5EjPvM85rfc=4{U?<#vS!kBR*e>w!rIZAb
zf}#vWsza_|MIiry$a1_GO*An1Bz;t0L~QdY0Bd(0a@7E^dFGgc+m6&Ua$9Zn`u`x5
zCcPRIJ^_f|B4iY;?N$hx4pUt-FH%{WM}`9=YgR?j(Wad&@PQr_hHJ(rEPI@Q0>`RZ
zTq89qDLP2(toZdn_vB}0*QLf`&X2F_4<zfBD2Z}7l><U?4id`76XXdkds1oNTs%Ii
z?`&reuUqZ#q{o%_!~)J*uPqBA^S_*8&RvjiHGvSPeN53230+kC{=2x`I7u5|%~5T{
z`3p|-r@|5t?ZQKByGMXJY`qWMCcd!Dtl*>i9NV7Hr|kd)_#c#?d}D`6F6piG`-rY_
z9uk}ydYbVp78_dlE66eXs+VU>-x1)S0~f~raH!+{GtXT3JNWbC&fHX6*Z)oetpc{E
z*~*AaTs3Rg9qtYuC|m&rK;s}@GhbN2j=5+{!|y}aNHK6mTzhKUx$T6Vl3V>6Jwgsq
z2ct*@^GMxVqQgv<X~-zxkG8UyWn}RVmzof}C61SZyH*44XQzPppFhbKwp#u1t<0Jl
zFc7Mi*;@^4l!!py8=pIN%8<CH+eM8~g{tmP#_B(VJdMI3p;M}ifU-a0{2Gu#t*#IR
zH=aAYpqj)$xUwEV4XQPV>|qaK$RSl060;Ly#4fl5typ8*6iJT6C?4_&?b%1=8m&qa
zfsw&l2_G{QXI)=+dcO#}Fk2!}-D0o#$B)J3<IiKbyZQoSfl2$1k}nlT=&)V8z6nR(
zRS(-rPi4{(`CxYJ5swp_1NGCc#sPhc*={t*5Fr5srZuRP-||ArUl#PRcixbl!^L#R
z-Oeq!tJgzuN;(l@X?zLja9+E3g9)cAvGHafLfg<W_Y(T1JuxQH@nSX!LPWsdRh>J;
z5l(Z2{cXEZrUnZ{tgcij00fqnJ+PFgxBIy4d==iK`b}eIer}cmfh?|gXE6|SqV;}7
zL5|w__Nd==7zL}Qao6_xd#BuA6CT9YQ#nN^z3QUKQp_Sl;5#e?!xXTzd-xkZ9u73a
zORmsEsRDqmxc!Ae6%M$bYZWNS8e@01*5h4(ottk7+BAjB5#N9jzn_r5#0ur}FPR8J
zHy7J?<`w?`Ndyu*kS6_^)xJ^jr+$KL137f7YoC{`ghAJ9z?v%ZeQn1!W$UW(dSw+p
z{k=9xa;VHFPS^~!op2ln7#?t|tKxh|9-(0>5Io{H(0$#_ZR<e9_?|UO4F){H^h+Y`
zpHza0!hN}+%)QgCT0G=$;mmFZJ9?%n1J<ck388<&Kl#YW){mtXzVqI|*;;T)b2@y5
zENYl>dr)RP>ttg`SBl^sk{G<!%7Z}5%9SR4h@Z@I)A7q~zu@OB0&!Ij`fVfBEhtN!
zE5`tSv*K&~aC~UPWGRr&FrObUWe__VKEiY>z56IYX0(j>SZovw7X5w75}x;PVYi5b
zk5EE(E#_;YQF#Naj`ly|OEGXCd_x+*fS%H@8=%>$7R$6O^AiUj{=VHE*7{vUte_rZ
zjd<(%iHaC}?zYgcd!U<%q@-cH`a>N4?_eww2g=9-J13Os#P8hMX?n?o3OJcfZog^8
zmn4+mheaQS>J-_h76&7r{h3T){}aS4bUOH+O6U<9UWUQ30P}HAwQTekGVe^r-&eB-
zcZA1s=hpP*LzrcL{(j8i=Hq=QOu0SOR~FM(*&gs%{}-H*_TBuuzS>kUTh<SpJ@?Jl
ziUW7vfW6o@iqIipfTOdl#>0swIDW`OD~i*@F_;JF+cFbH6$=++l=qCy-^~miD^7(W
z$$B*wM(w~%|K310kzOyM?__Ah<<$coat}9DMYRuvvVG$1jJ3oyaCZS)Tpo6m(90^$
zLAwj<Rr4VHb~Pr(<GTD(1)(<JcCyd_!Ql|z7gH~*%&-i&Y<(djqDK7=8=4{GD2tM4
ztfw*F*dK`&Y0wC5Ib<M0Sot6Ps_1GuC$l`DU4EoGfSLjxK?J(rYMfh4(=DZxo4iA;
zGkzN0L`oF@6!Gk{z5Z{DwXo*~!=o%AHZZo^4S+o>P)(K=P`!dZuxDt6P{3g87&|Fp
z{xq4H-<DNvY*>$4sMPk!rhIXZH6uT%0eld!&9SXNn4&IWX6Av^Om2v8&gs*?rakwo
z6I{z%U?$|}BcxAZA}J)_y<UP8JDI>W&<U}Sdd}dRD0Bj5$O|jrI!|j+7>d=@Ocs@A
zp(TZ2r&1%bOLN5p)l+Pc#UJw*d=N(pz*o`i6F6GOLgMy_OD<9SxI)}%flp4z8_g0Q
z9>BbQl(?9vfYHIPfAu%zga9dzS+Gtd_Y}w;UDP0k46l%Bt9V#wQFc&051LS`r7^5`
zZZQ)0s6ogG2wdqq_+9LXOulM2Cr{rC!sADulW(TSnN%0Fpr3(f5;`Q>LWQc4TMI9U
zeN#zpMZC)WGK3aNtuEQs_&+I5&6p$-c(`ZR-L?#wFh&7{s8`@Nqk|%?l_cBX=mV}G
z-f%3yef8iAHFPz`amU*k)Hp8iDP3uygDD31yY(s&Xbv$t(2~>tM(a-z@dP*@Al^YR
zkSY|5iR%ruK_-MPydPRp1bS%!9^=X3?uLRK_f^8fT#(1}l+!z5w>_zsvm*OiFaE_D
z7duk%O5?65SxCzojiytBB=<qw=nLk=Ld20hP0f-k3m`YI>25#2!mFC9&+%G4p@JRI
zaq2<&BSY3+r6?51KSva?P_h<tGhNvP4duBUElR#xA2SU8SdvLGEu#Htqa`Khe?Y~a
zh>pEZuhRoILG;+tYCu3fa~zB(sGYwmmza^{i8n*mNKby5U!vdGPET`Q$$>!fq(6be
zD2J&FTU7?nNO<lyveRN$O;j_>yV9DfSvjtot!uYs%GKf6!*Vo)$wDAw809Jt&_;uL
zh{*xT8NeVB<OXT6)_rhX_3twd(0z_-TOq)Ax<nN;F7x>dBTO6Gcyb_hulit*0_hkE
zpl<Cs*%gf)z5<K$W2w4=?xK<x`JKzaHd?AUfKp3~sJ#hbFe=P<3hp2BM&mbMilsG0
z*XaDAYj9+h{w0dd=G!MY)!&xSyg-8cXKOfidG!ps8n>6Y>&UJ!8wkBZ-+|bu4!6Zc
zy&TVWzO%dn1dU2{)uS1?`cDJ3GMFsLfe(bn;fljdcT)<&1hCLKTYb0!AlIiVQQ_{#
z4diOq=E03mUEi(oyCVL84c9KQ9`HeX0!__~A7j48fWvhtBlfj1TS<#Vo07kmtoRb-
z@4!ufm%wxXN|F&&1TvWI-M_B@b4Z(yDghTLrz7w~H&q7*%qZ*P8H+C1gCNrTlgH|_
zDtb-7voqGf$MPe|@PQPK)o<N}+_cg6ybSD~!?4I0dN<R?TJ))3X_%!6?U=NkGOiz4
zB9XQ|`4L&j#kHJu0ed8%Tn{C2LJ=<Y^-R#Z&VT45?rhA7slVIW6mq=I%HX*RL2(sg
z&&E<nWp);xHL{ly6Lg-UpaL9+)Y<pp?%Ba0Cyf)U!K`TlApFq>Lo;0b?@*i6nwCT0
zFef{Ko@(XTg)QXt*iR3D7LgtynZ#H-7N+ALYn*_M0V}A7vaEKEhOG14|MR)Ym}3xW
z<lN~Uy+4)o>gaeSzbU2KJO!c=|JCxjpQcL@E+&9ze&I+D?3E=53J88u?hC4u7+f=`
z^vTY4^x29vM7{m<-LBs_IE<)MLZu8bovO8=YbF!imNA~Ai@4sNjS;t+sfkw2IjypQ
zt|gd;rqjo8j~MN85oNtHDNiQhGP_~H(QF;4`hTaq^J3sGulqY%3~H#G3?BD}UnwY{
z=Qol3>8yn6tO!pOdmu#dT(<K#6VUd;gA%vjh;2>0L>}1?UU)lyK<O@lee?`Sm|&k9
zrs`pEbDK2UUnRtjxqDxDPE~Fppwl4G;{O*3hEuqV81}Bd!Ir+6iX!ayX+hMNfgJs8
zebWo(PgxC-giIDy*~?pyx!lLL4S$jTY>*L$Zgfao-Y+Q&ElM@ivX7e`@I5?JXl-da
zdmKz+SdA8qw@7a~e^3Ui!t3CQ0;$OYNAbE5x4Qp_k|PSDT67JCCk9fC`?@?!$mg0x
zo?e=f!SCz8`5@LJ9D~<=XOqr~vKS!bailv!YiN{ss^W%ZHRM8Wu?4*`+8Skwa;gpO
zka(a+O9xo5s*P3^%M=bsPSzU+H(g0W(X%hWwI6n7cV{;kq)=U1UQr~L!ar-D`HwP#
zZ|*e(pO)5EHREt1^<K>Qp9?&^(<rM&;0*qQcpXFDHpVkG3|O_-?(u^P7=06x$B&tQ
z`i>l}<*1qE3snH+&J&<KMkvnnx^a#=Vr~9W=db%!yv*jaD6-d*T-tFp_gM;h*OG>w
zjm^g2y89wa-C&eu!Q)GzAnpW7V|Eq*;pZ9bMIE0p9>W-NC!yXUQhNyAScBGV%DYW+
zuwfuE9J2Cs!6dEH<0MzuO3Il*0FcX5#lJC$olthjRSC7FhQ|$pxWX|8C5@>)GEX}>
z7_@<02ZnbItmK`HkDMLAL{pRnv=rddW9XnEb3a`1G-(1utZj0`%<U0Agdv`@Pp1No
zc@6Ca6P{^mdEM1#&SGfy_2a~!GAAsWozcdV)w9yBfx!i}+>HkO^x0SjaH7IrT2>fz
z_~`JHve3Yum@0El&<wNP4njsdj7|y|QjcVdHy8perW|=QQJ8^Ub)N@RT&8Ve%EwJr
z*)fx_g{b-j`NZSk6SM}Yu@~Eqx?R6SQ^Sl=|FM$0LInl1MD1ti#vXAmdGOcU)m=yw
z>A%G<23R-nIv#+zharKu!)Lbv6g3&PQ~1@FX0I9(nUG~z!^i=b&!TCI%5POF`Ys^2
z4QO1*7{wQ}!NzrCBrzAO02})2?)!Van)8$}E-uohBg>op873{@8-hk=*H*9rd8WuL
zf*4+sGHRuU^XMi=J9gG^-6pC6{u(KghVJu*atc9QpFKUryl0(ji9!V?w`<~!#xK%`
z21NqgSL~{EC{dPA*2y&`h<HR#FY}0`ZSj@*oDA?CjjQU6J%B61-AeK2eC$=U3mHS-
zyuYT9Aiw7^Q>Q7-gB1t8C~#uM{3;$jEnwSWi5@RvQsm>JBH|FVkP`Oy;>FZ>Rxx~0
z+TQ9-?GUd}o)c&FAIvITLFZ%v$%7VxVrg2IDMZN*qPw4c#wCuGxs-9XJt@NHskRgw
zc4<dn{o5Pv374iv{hd_2r8CuO$K`{*n)%hSC_pQBfIo(ln2E9B&}OU~Ntp<XF1Hd9
z`SW(5VfD`K(aU3Ofs~l>rhY=c>_&$6pB-O!_JqzWc8kyq8d9-}_s!Uo`)RDD!z=z_
zxxqRVB<H+^q0j6`U~91CM*@U`@6e~K>G=k<jYj@as{TSF>=w8-R6veDQ=-=If|&qX
zRlLk}B>SbDW@emj;{rcbxnQHA6zv?|Ij2_W`p9iuXy7e^F3CR+uu=W`=6}pr7{Vaz
z71zsc1@~XqDF^*AvY1k;7g=kg$AH47lfE+eA?=Xl?GIpFUe!vCJ_{WvV%^vQ&>d7C
za%z3Al+>s3DYbc)`mP!Ul?q{%q7W9nBdK}s_CY=iE{_B(-rWHLKiTHc67<3*Trd#?
zuT8}jWstoC@0-JY+M%-42v?$CDYhkp<gkpxib0sXrf5@ZSfz%?g!wKN<|n%Col}B$
z<a3W=y4B_g2jtE5ZgIM2$g4-Wr!UCTt(sq2Vh!yw8_TC{(!Jwy%GIb5Or-d9A`IfU
zCNz7lSppjWrmuk77y!S<?3AmD;C&zz1JX0b${kR?%U6U%`#z(Mgl*%2)(sACop9Md
zTJ>8PF#rVhf`-nT^Cv;SamQ#w!ex+hbX~*k%oqmD+8fkLLO8u-On-H_dY$}tYZ*XX
zi|o8h3w_aKPOX>5!M6kw`bc3wFy}{SBS(1mIQ9lb#*y)4$-(vVb-~@{*q-668N(G$
zb_&5qF5$ytVhdEIlj|`=BA}0riPjq`C-3v+*gT-R&@Fy_(NkSg%&V6q0F}o0;1R`X
zj0&XK>ZIP<SFv~q8e8ch{FO$&KUopkAj|`XiGHfVCmwDO4IsXQK7w4EYiynI%X)Lj
z1ajz6NG9U1Kh;EtmDMntS4p-UyC@PLq7efQvXGU}`uQhNcxe!;g?>vp*WX+)=(M`o
zO^f>NO9qEeUZ7ZCWVqq~QnIheq;e5;gDJ!0>qTJU*TtVJ{%D&htk=_<sz5IC;i0SR
z#iaL!ZAV-RN)AI@?iC=79azJ|(FwpzwuAr;MrRgE`*;nZZ#vchm*h^^-h~h@K2DY%
zNE)5cTy|Dpj~_z@s!_QUQ+ij^mX~@5lz#Nv?F$--AB{E!tEJ@A;9@ls!T!#eN}84?
zx}j1n-qP9gA}e<(vIfmUwBMVtXVKQc1Rwc#e6C;A)@h+oG?@b*aP@E_sn(umLVEU_
zC3TO35$=Ax+Jm8h5`5Q52#LLS9HHG_lXNY1(TE1?#oiTPPAGihyn@#x&MOqxYM~Li
zgxS?=w+{1u^*zmIQ^JgLfRz=;Ur9p<Sqdd2-!RWl`gn954O8+Q7Ol!PLp$ooD}tmU
zh>W!}qUsYdYPv!Hk-y~y%7BLywQ10I5wP#PoVg10@FZeN4vEy&Jx%Qp|8Ga)+}=-3
z4#t?O&Gl(EJvL1ZEbr)+=wtHO;fq8d0MFvz(+=VLd}D@Ivtl=fx@V{IfH;VD&Rgk{
z$Je3b!){_uW4`HzvuTcD#wxH`Iy=$`rBI2`gph6~DGSA5Zh`Wt<C~C3YCrW)^l<<}
zS`7?EO!857wtWu$K%w^IVAT%87Qx@YgSL>FL}u&Q+~?c$>%3)Jr(j)4$XJ?fKKKqb
z8|^{1h+GajVp6(~1O;3BT&CR_(;dc?>6*dWY|#Wk_x!UPm8Ltj0``SZMtJ<`cWe`p
zVRL+%BaG{h!VDX-=EAi>UCeO<-@O`&La^hTI6)2&Br5SpWXn|?lFtTDrUVw`vP}i{
zfNK?x`U-p&MOyQ<U6KF&G^1+~4mkFXkTN&!CY!|q860{~r}_iVm$V@|DoTE;QH2{a
zJx2rPNHAg4AP8j?J?p8ao&=@8Koqv>UWiJT*20Oi7uopSG=B6h4)74Z)sJ-dSS;5C
zygpckk>^$_CL7tL_Z_#hjVLD&tB3&>#+T3-i-AHmvFOO%5gw;d=c0J5%Sb=$>i?Ve
zPZ8L2WRz=qKMz;)j=+L6=}G{QKJ|V&e$U+-<RhQDnXX(%JEGWl?H12%n1swNu>uDx
zO~?_zTuQ2?oi$LsB#L=1*ZI~E;^E0Az6RR4=2=k0izJh`TGtb05z{qp)H_c`jVg9I
zq-h54jUAKj&z5+|E{yjIS1+6`Po;`oMXFv<&F-7*@|FIMNOOV498+FrS@uMvA^zy!
zIH=J}ft`V4s<KZ^P(Cjmn#2r-*O+A%pz{3XQMy{Z=^umTFuQ8>0%^rOH6+l|XIy#Y
z_X^f+A6q2J@&7N{tqUU7KQaA034vNw88?QQM3KvUK@mr{*aGv+zy97c0pWZGrWDc1
zn)DcePYA$)_a$qiYKn6=2SC1?tmLT87#rlAHu+%!6ulJNFJRXf@VtYRNZq}>*Ay?&
zBf#^{9|5tIafd*N#tRAz-Q8x;<Xa)M3B!u;9o7bJG<)KBS;6X&n4ixlH9FfMzv=A?
z@G+fF;)EjaF`rC<#Si)P@z1J-WL<zC4dB`rH$mg~_$H>2(K_#i3SGZd_`ZX=oodlR
zL!}L?T+4{s@G1p5wzaN=tJ7Jm>Te#{hqKzAZFP4>mkCpgq4jtU8V^WVfR3&~Xc=t3
zJs|T`3b0`Xi28c$?(GNv&qc}Yx#zA+NPh27WpM&g>I!y~#!Oy(5fl_qy_~0$(i-O6
zfMJ2vl(W2o%qVC9eE}_2psc);*cAupQRD!vC`9nMbth87`vL6#vUV~C;XS}saZcpr
z8#bbDL?*iG%MLai2-lLM>jFFA(}VwauDb1FonD8g7V0q$|D`ApYfZSgrn@%2xD!Sf
zg#B%{_o4qN1`kNPDka~5MdQ$}V~q$EKNDEGUMAg;IM}OtZ#SKa(g;#qo~Jgykk`U>
znFg$bAn?BB6jxyU9hgPG`p(l@52d6U@)N?K9;z!XLV6nM%;8wK3-VU2c?!B~>7Ep_
zV%;s5VbC8fsGB5+Xnr-C*~K#6`lLsSAg`TgS~2J6As6x9@Xu&t9|M$5yFU&-|Cy%{
z;x^bMYl6-@MjDAmYF|6tmgGv3M1Y!`B^L0i<y^FVXoQX2Q|=nkAR2HV#59IhK0&20
z0kMdoagN4&RX__>;|=Q*Ypq};g_%WMb*CEd;2~l=vvgAY;l#u6oBKOTCe}$~yI@7*
zk2SlY6>b98WzlP8s9kxxv*PGC_D#l)rv0;cJ5jT}EC=JO$kmv0LTHV{a=sb`UuO|l
zr>Z5tU2p7GRaFleCN|xFAy#VZzmLC4yrx9RFP|YGc97XnNv!O5)ZOwcI#+8A@}*BK
z<&OY!yYno#jEN;dgy$)O0hGSftBkTWm}%#&A<P&%G=DAy-e7b@PX&o2;H%R%I*#S9
zS96ME<fi3q;-Pq5BdPfmSH(9#8r_r+*S`1gJC>tNu{M{Jt7YEl0CwM-iM-UZn=qiI
zW(>?@k3)|AP8%Au{-p3hGw<nP_1Ppni#kVTQ_VxbpHIM(#FFj)j~ceMTe3!HL4;gC
zrsjPumF_Xld~e(#T{Hu0At1|8Gilc217hP|;a221U&>zJp0lx*ig%kKoM`D#jd;5X
z(1Ect!GNT-578TL#|TrNRO*%Ts2nMxbaV?yZW6Dn4YZCTqO)GUxUkTp1HwbnE>x$$
zFA*BMlLfySgHYjB0t|#V`lkAR$q}EQsOQ`7n$|iyWwh7`lC-Gm)-Z?zyigtbr93aT
z{|;>D&A;ilF=u4T7qKJL4-I5Z;KS^!kbKX5XoabHp)S64uvVw-Y~trrhCmXtwb2wt
zFHyOI^t6xSFyFg(kG)_FOAt^#di230n*|dLo9azk_elL}4k^yI6pMQwRwzbCl9YU;
z3LAZ@Ds3jn!0K%9DU_C=&|yTJF_Sb9T33x(bYX_hUN+)s@RnrwYv7yS>p$%9`?_rD
z2#y*a6=oL!(5bj@7$rsMK@XoaLVXnrrdm(^rqdMT!QD*%xXWhcM~K7|G^2tx8zAp#
zF<3ZTn3rSHNf+#qaYQOzo>wfBn6zPU-Kr%!y$tEdT6Be$yWbKX{M(vPry(($pAb60
zcS3t&Jb}0EnXZ}KgOCj2?#&K?fW{OMwtqc4h9J|`hSqkl*ce#7VfofcSd!j+=ya$f
z8(h7pI)GIlw`LVkvR0SfF;r@nBt+9-p8<b3)%V1|9|D67aPZ*Puz4bh!0{(Ls}*-E
z`Ffa?aNTu#;c0qp%5R?5?sKH84y8hsjxdnXj3^|1j(z-M8voDz&Z!SL9nwV$MK6$M
zEN9Y+t4LXFC&yH!Q-gv{#nV*t&^dpD4O|uR9K^pUMmuXBK`QZa(64%bf`!msAUK0q
z)rbsoD5U<jcpt5N<imk_I(|-!Q{uc_sCh#&MZTj~COE1wOU#kzlLeXU{tNLwIu3%7
z{8*X>E*J`GHaW<&OzK$JSi`%<i#|VR0axOAiX@%LUsnJ+b$_`gQjRNM>{=6X*{TGh
z#?V>P3pWMMT|To$PygHQc`5<;w1(=#!K%GK<wjD0v@dE3<m{MTbYG-Uj8oUd6cB8k
z1;W0^?jozFBV#F+{V${<@ue6)o85fe)G~P3D!3U=@+@M%lT7MqN{3{#1X$VxVl7<Q
z{zbb};;A-Z84JJx4^0+3sn*596bJ~jS$W72<D96{m7KKtcab|c1t-)im>SD7ZL<*b
zM?bFE7-`+U>4M6XCmD7j`$lpa+e&t;nwpo6w>5P+jJ1MQQ}AQ9Ts)|0Ns+Awdnm`c
z!G@Y|FbdGuZ#NnI4>(3jb18Qay!(cdwCSfB1~K8|c3U;aO3R{rA9dc(B9^f!=F;fY
zga_2}!cpC3xTZ18zSp{RhWs`$7=b%bz0#({n+&<RyHvw{NO9nnsC`UYgKk9gk9GNt
zmEiYff-+LoHMet$o0Bh@7%LS|S9C7u{_#Mda3s-dF2J-WaPMeF4_%*I)nXmAJ&<;H
z+<Pnpp?t}0CKv8dMFM^*awr{p<JElBwR`1`R?UBf3r<ABKgK4h*u3nt6TJ&lZ$6?Q
zJwxCANa`*eH7}M7a*Q5HGrJejv5?Mzr<w|l*q=;1PY~di4}`Y{Z&*8fC*F;>IK{81
zise+{1+830dC&Qjawp9elN&yFLsH7AWkvaOZmwpSEm0rbMil_rVT5E`ooS-Mr*=C$
zQYr5U%4*J|A~ug<jE<RZH%ueo+}Ywe4ha1USVzuERj=^{bcqP?87l)L-9oe?e}vvy
z&x&28<maO9;Lx5waZFNoPm?nt<bqxl>Tm~s;jv~xx&vUBD1fAgibH!y(9njZ*bW89
z{bI$&u6e->m=+4Bb{BLnYJn&{u6-Q1B@?LAkg!4b^=c8Am{8?IS|R<p2=Cri@#n(q
zx@oC~9$E41B!Q1?-Zoj?0v7hhrsewVL=qsaP3nk(&z{w;V}>wv!N>zK3y`U1z{=hZ
zni3Yv2O-~&Uhy+8s5_OCv4V(TqP=<UnioZDNHgDKP-h_*U)<O#^>GvhC#jo%vQP(|
zq$`SS2M>97smHr#8A;((?_&=OVlfTEe71J>?YTG}#zHsB>6qxt2OASb-#nPb@vb44
zh{MVS%ad^;RU=E#D9giP)T+oUDzB&YBn$hvY6~}m&;ItQeFSQ7245K*<&L+BE}y=Z
z^to#arn?cYFG?rE1ucL+pE6w`x#7G0)B>q2H1v*_Y1bMenzX%i#*Y}*=(NuoeNG`l
ziy)XZx-?+l8OJM7O3Hw@n!jvVw*_=s^I{}z_}Ty9(Raze9OC=>+YDD^u_>Dizv4;!
z)Mk+^*2|R6F%25LYLsg(Zf8<JksvYzR8{FHCBaOa8@smtZ4OrY*q!tAQU;)Ez@U@J
z;6Uy5;_(#>^-0~*$yNcfX!*yn*yg+92b!n!>?(Of*vs<;Tgd!5*bc>LLXYiTx9@;_
zg&ne%<Vt5%r@fbbN4^vM?h$nrTnUS{Yy5|TZFRQ*zYR-B9xW<`xfFZp=vrn`y}dW{
zdc6^Vug5;jU~```6T-y=GQk6|F9QOlNxe2G6P%gxiwp8x4x=90H^VG6!QQqFr9o>b
zhlbJ}i6=I>U-+q+I;-!;cTCNWtPED76PxzQ!6Pmyo5Jp?klSfavC3`sDKxSnKDe5I
zhL-6|>+<RE)=%O`paoI%xCF9b?V~+2FRt}+I2RMy+@4b~IBavK^RMEP&oOh7@Z0t8
zC~W(cR!KORizG~GJ~W=Ub1Fdc<=Uh%2NSj1lM|M<<gnuxw5KthawjBiuIMza%)S5y
zx-*$4Z2)`F4+;$)61`NwVLWGCMm0>&i3cQ!Rmpd?=$GvVi3Ctf;-<0Y3IvZ03S7nH
zi!UP;PhDM|&Ki19!x9M;V)rKX$MnkZL<LnK_3+cwU%>k=ST0zwLvDd|0a68j1T(f@
z%UH=#q_PPSRyheaa2WRtCj-$VE9Rd4LwSE(p!Y+6Q8)olHu4VM&w3EC+w3jIcav6i
zU>h$WZzSl0iP};j@kiQivGD?5@zmI&a!1ha9ZnyIOL@WT?V}=mOS$f#pk~`{016+T
z1nJbR(|<wk-@^mk|8DK7QSIYH9@ROpv+SeVUCe^2go^W*>K8TFW%iMYGpU+ObC#Bc
z#{K;jntY_AmG|N`6+~c_M&9w5duT_F&_N-)BA9SpYJoz#Du6QJjcA1TF`xR6+mIbR
zLCvF><GE99b2l(ve$0PG>h545P@OLg|KpT4Iy=_oPTw{x?@1_$arIY1izstYxX*<1
zYG~x#O!UiG0Zpi+wZv2X4eo^Ryqw!qudvq)b!jgs=sGN;@5fam*@8nxG}AJAUC@&<
z<t0^=3-DVBOYL?<$k<`%rn877oDmk@L7X6YusXJt0aPi>6mUDQYey-`=`Q02CrsfJ
zgw#&Ef)!VJ65ed4Na12rS5|Po$b)Zd`f87dT+R8QA_d5%EDkLUwvawu(K^EW$+VQ3
zox-Y9ayBM}h9})FV71)ZyE871i!hCyEp*rwxee1M>eBX$ByWRpO3^*-u*fbj)uQ?L
z;T(fgOG5|XWI6o}63D*dVr-yOc_A$ph=3@}f*Wv?$vlm7Z3$OA9?wYQsg|-5<_k(c
zNHBkTJm=#UBxh+`PxBK$2_NtFng-R&nhHlZYWD(O9FT%c9P`mGwJnmnd*rSlBHjbc
zbNMAzT@iX&=P1V130$;4Y9)<MN^EBD?c5)4#<BlRPA>4WuNQ<ewH%}5+D|DhU-c=L
z9@u?KtvIVaimhQDvq{Xne36~6{qF2a%k`q@wOSv#$<+x<J9Jlnl>P)kx0b}9NPz~^
zFx4hG!qyM0+FUbfsjX)yT7>m*$vX%yX#zqOdM-yxd@b*N=CrEdV*J(wt5}8|>Yh54
zC!;7bkvY&iN0@5-zFP`Pg}&79795>+L;T~iTywJ1_C?>%Iu~VU_w?{r+P_E!QvUn+
zlkKT8>+jnzoWRx}8a+W10Rt$`Ou%gn>t*YHGu;18{zt1OwhqO9)kgJyk~Caw7k`ax
zlLys}-l}!FT(PAAgRMziR4xMA1d0c1jcalmhZxoKpM0~M#>AU#4nwJhXQ61ba4UWS
zmI#69+)FS1`RY{t(n0e+AgN<D7OTXDxNWbmXdMp)F!En$>G4u^uqJlJE+3)A#_Khr
z!n}k9vpARQ<sJkoeyng-$M2`sa%rMSr_c}uRVdanv3c4~*ts4Hb;`XO=+cSvG*i(d
ze{l6!Yl5=~7eVRQHLq;-;>g{sM(1dBmwc95rUG;+hYYi_TreW8m7)DRy)8DR(P@5t
ze_K;Wt+5~gbpD=p4Pkh7OuOsTi&$DtcGntW$Ks51sC}VKji<62#xTc%@L$Z@x^o3@
z_nc#Z>IqRw*+Pp0yTK--^OG)e4kr*nf3?`GEteT94Y>OK+5YkKDdAG-=urp0JieBq
z!6XqXC7jiPH(7~Kub%2ob?Q`zzIy;}FuN1UpPpaaW)f|d<?c%DbPr*pRnD9y_v_rJ
zig?$l^wkMxK&8sOZBZ|@cN!%RP=v<t`ZvvrH$-verzhb`-4MlS-nN&!S{me9mmZ-*
z?2-AJj3mh%+}P6Tq5Tbt;1TwqQ;m(3ZqVzaOka*GR)|3(+3iU7P8iHFmO^+YZh(hQ
z%0JDuF6$Zzm?vCt5k4TLPq!$9NbSx_TP!}I+yz8(l^iUJ1ZueSB3h0#^=d~KcvfCb
zZ!V+ujfOULM<JAnj=xYMdp<Y@#a4^5+~p;$pDWod1+QyW(47@cbmd~sl3KOVg>lv1
z$MqwUv`lE=^+BBKLxzCQKoK5BcrDFHhk-1Yj+Zr8{khtY@br5Xgve5_+;h`?>(nD^
zxb%*yi4bkrvQmRVyV&A&OI|OCokQ1DrB_|O_#W2O=3{|{C38e}?qhc?#+U(ELRbO#
zZtWF3!)Qp*Ye<`HS?&Z6s3<GXJLe%38g5M5#Zj<bGPJQ72^t5?cSuH@NWGd(enzlo
z1)>R5Lz1P#F+Q(Di8Jn*Mp7;XSELe>kWNOC*DT^Z9<-l0OpPAScQ!FMV@hLGn<p)d
zl$PemjiXPXE!}%cQ}@7Uq<<1>Xyw+)Nt+_O(o*Xl3Bq#+Aed$3xbPEKF%675EWHe$
zvZ;v7+t9&gS+{5|P;@lTm}ZWJtol;_FsABgGkX~XDfY^IGl1cx6RsPRfxRh<<~YxI
zRoYV6Z`7CsYB<W$-adgCYjQVwTB9ItP5CP?G`cBPi;JF?Dv<cJvwb&7ME8|RklL~Q
z0Q-UZn#72H$C`T<gnpp8UP=#W?ElbHpNdr`t*T}&Ei<tOSGU%SUM^r8{0DbpB_#1?
z&)qZDju&SCX4ArZ>;}H~h9iU4bA0N}!;%&20V-;C8pML_p;;zfJA*Tpt2aPcw0djQ
zw&tPt8{5Z?wo6mmQU`^d!_)VZWp+*!k>q>VS)r`QF?!h}TfF_(6|1>{zntLoXIZ7~
zrTgCRS9`^W>Tn(R-*~>VOwA>L#zdcI7QiurO=Q0q5m`WL_r&>YcbaZ9&s)es<1m}i
zE$PA0VB>*A`X>|68Id$XXgQe+dH%>y0uPMbvH}v10yn$>9+xU3RDuMGvBzhb(w_zL
zejfbJ|9diuI3h)*9$fdRf~<lX!v;;l*Gp2bz$XlM_5aqy2}vgyn^*ne^=&0Q_qYLX
z*j}_FypxWcz;d*XTA&0@(iHGOqyUg#=4av>AbsISF!~_cHt^mwZ$z&D2&+X8;)}rW
zn&>Eafzw!WeOwZpQWApNs5oI|DFwB;iLP8gb2cKYP+3n>hYFcf_GR<sBL1Hpg0Tgz
zIY)i<g|yJxN!Glby`wlk<j|c_G8sIj7+TPFlo$1-?p1bA27#Bq4c}hZ@ga>CtAK|=
z$0~`D<JX+nsb3cQlyAni{n85|;!V%Qz48k>q#2rV^p|2LX9)#6ACp~;V+(*bLY^Cr
zZ$&Ujrt`_Lt?Jj-$}h0#bL3S}9qF>*(RIp`q8eQ-q{K`P0#sAucChGItm^V0jL3sD
zR?pGVgyn5m<hW50MQUMl+%N&`lmDU$A&ch>U`PX;aa0b+W4;i6Fv!|r80e%gjc&ea
zY1ROf=qF?Xpz)bW;ZiJ%TXQMZFmmWgrm6Kk7~_y&tNtV3Es(%q%LR;@KU-w`RnZbZ
zl6;Mu%A_kzdajl_LZR2jvaQ2gSUx0~LB1k^^Fv7vT4%+DDu<OI$<MLAw8S3-ge%LP
zms#=rg$xXkM83?5SBa>@eWB!5Si?-Pq7{D=_~NRm^|>p59Sl9)XF+gbq732j)z*te
zfqkLHRyM_(i2Hrt<X^nDR0=HCOcsFZ`LTm_0zQv)bwLYF%<|3|K2Inc;9BWxIi!t4
zujTTiQU`;z{gVW}`6Zu#jP8?L9TZg8JO<|-%n3NRKQ5>0#Fjrqq#sVp!APbmlg_xq
zRs;SH{9$IW2C|LG_8-B&_#c&9=@JR6U}O^%Y<>;j%cwmL*RFs5n0DCARUQk|bHYoC
z7;@dNPkNXAu<782ynjL1dZwz*oXcW19HlXBS%a(KSB|p2*eT0e+Jm9iC|psL&KDoT
z&`jjpMbHhJ!wE@~0uL`z-mOjTMoKEFI&GiUeZrd;g~$evGVf7eTtiu+s}2p1Imlv&
z>e|keL`$?wW3m8nX-9uN80p5j6L@8YLS)HUF?6H$k=vbzzi(6*@qKcDP+)$MeNfDx
zORL-sL1#`{4DDA=A@l*>KnF6Vbj4wM@%*j)6m$0ZOMr=hnVX)D@OHalfiLyITnqAQ
zwDI=mDquxiP2_;{?)jpCP=WCCiF`2VixhCtt|5Cuh<PgdF0XcP_}!icA>#@(ki5S6
z*4~EYyKg?b#JgU01&JrCiLA06)Jz-QFvb1c3q2v2PexO$5<hgd7v_1P`z<ST?)0j{
zpKV?YejVYjo&2!P_bY<FSNR7GsL!PM0{wNuQe(gcYnDB3GM}bqpl&|LE9|+-#x3Fl
zOt<j=*6ZRM=^56wPQH2GQ=A;{_s&pdev=zu`|`Rt9Rg#nO4_-jB6jymEXVGHI<Hoi
zWT&JdWEcD-+ylH~5@+!mZH`{sk<RaQXAOoF(o_cx+R^^1@9hH@bQ}=X)^Ghf`;qLN
zN<s_9Yy7jO3zYu}qigD7ZeLYDqGRqDK6^SL3>8;tg;6U)t=n&Vl|2W^KL(l0PUf%j
z#i0w}S6snoY$N0=P=nrW*H)%OziM+)cQ&UD+xH#cqA<@RMS$3ok<VBdcEi+QqX7tE
zn|u3PN!yL*S6N=m;sGjj88|_&=}z65#0(aK9)twaE|||jvMwYI>C;a7?Fr<??ZD>d
zox4UjaejokfFuSt{sgKiM)?fOy`%2xo`Z9u5w5R$+%zF=Gafo5dK?ftfq9>|H?m05
z$1$DCqvHU28fgzFiAkLfoR{A-&%LKL9`usa#(bCvoZ)m1&N|jMk4avxk%aXndKkYi
zMC8j7NICf9049%SPQks8-#m*OGq;%^MgOySoUmru917<NYj@uB_!`~>YP>3`7piPl
zM>5>##I9?wQQdM;67JbwRz$jkbj6(*Uch&q`-(cfD3U^AQUN7nmMzPa%&%UtIca=b
zh`m5FbKxQb#;sKJr<aSFVUB*Hy*}P1x%*2_ED!WFpY8<`Ps%eb8~+bB0*g6*lMv-E
zmi5CA$FzqrDG1Ml0P-SAezH$)Tf>6$)3q7N&hq={FSqhx{YbJc&3FF`%`(uL%>+xD
z14SXtNx2HxLh)#ua)u{i6?z-9smP-Cc~9v;`x+%|L3U~4c&Y?^F|M3O8t>04>LQc0
zNe(wlIr|VJJ-)LN4*ic|&n4-fp=im;IY>xq^vmJ<F{`oz_Uu7)ID@|W)ep;4u{JbB
z7eG=OLxOU}!ztcoHGVO{!X7OEUq+-_KrnNx>B3>y)c-Ld;3D)KWORziY5RnHLo_6(
z^Zz3RikU(`$E%Yy1Pi%+?r;ty6((WUaG@W>SVgK4F*i^&K1=H&NErnq_oHLIo|wR1
zBSwFoOw9r7**Ma;Z-O!49eeu19GBVs*wctOA&7Tf8mZs<RQ&HJ;UG3`aJ-wAiYI?b
zN7;iILJ{?n)x$o`_a+RuK0Tazr^G9u5ffI}pR<LY3e{J99>mt(%t`x940xs^-snz+
zHoHjoj8u;VyK&>BESNuO|00e!a^L6%lCiX_&GO|h!*;bIiGIvXA;$*3j;?)=^4KKy
z2l_nK{I>u5O{8$bd5)qDxG0Q^d9uze#r5BS6~e{4taT?7ETd8&n9=89445X<!wXw&
z^bE~tO=bJz@)5b=8FQi*Pfe&;|7~puSJ~m7DRIdyYkXbu;$`Zn%G<3G|8WHwQ##C&
z;)P#in}Z?f46+uQih3A(4GJj?Kh{k3O<H*n3@)|p7m9yu4vv#>{emphZ;?-T{)L1&
znZzHQ#k>cBfw_L5_+yO@(S%U(Fh89D)@8#8!j6{lA&hpny(i&WkyIr{@0h|uSkeMc
zd*4!o%|fx)2uEg^@I)dxR~Juc_rlywmq^W61Ywd^)2#{JPnhG)sZa6Rjy`sFrnJ^v
z#lB5;5ClQWHlJ$1FoFB@laEX=)#OuOEvIg^hw|jxN>G-h5{SdBAS+m#DsP(<Zc1gv
z3-p-UdAKbo`*jy~-fpDO6nh$6dLbEsPwPfO2yfJ|N(`zMPsiV!L2%w;cCr)4aZF9=
zIYm3X_i7MQvJQ)9Yw=OSjba}^P!z;YG#+3Jilj6OWmQqljb3H@rjmFP1Rcx|@jl?o
zzpKVetv_crCUWy4iil=t9VI{hXA}Wp$(;$=H-&6v%F8F4&eN(47#>ZBGjG@lvA{*T
z`SBX+NbweJ1oujYE3kKu1o?Zv@h=r*aCg(Lck#P|@0}p!;c|B6uti?Zstl#5`L!J}
z_ggd<6^vZV^IAZHiA<n5S4|8N`6GdPK1(!@`ezUf64#a26!*cSF`b-(i>8ahp`t8!
z0d^fdX|t#Mtl+*X_e}|Gt*YwBKtSdv<t=#!m0{r_YhjmU6?rjbN}$OzAzN?jm<8(F
zLEur{u-{tua$U^|T?6#=tGV+8`Ie{hNZlrI=D1P9>k8QNwtT^ttS<n;#8gU|MG`B;
z$z&JPlHs;X#YV5Jue2GCv=p-*mFpS)KQRT9VMdEnTBP*(^8ZHsL!rv21OvsS#4`tm
z3V94V6Ql|N*mtr?J%dYUhd%3&QZr?9n8`m%-_)}OaZ2TcMsi|!J(wQ!U_ZhAGIEWa
zom^eb;Wf>a+XoDF;j}Ad>7rwk$sodC^*Pk*0K|{F+yQQMO#oBwc|d9cdEo_-U4f!K
z_YJ}0u4=Q{biFl`n&)iOQEJr{XQD60>*8fgz(cf9^&BSiTrq$QY5N89<*Qv2BxE)*
za>x16$qGSsH`}?YfY!7b7P1P0<S?bw80P8ETg*l3L-S8ihU2^d@u-b`9|sIOZfJ(f
zXbwLuEpZhExb4fAg!x<$P-J(pXhPRpzD5Apr?c}NT{@OpPYOry(ayEjKni7=LAmpb
zRwIJ<Ss)i<&HqA}U-Cz3LODTiOqKg@Cst^OP{)@08}QR|NfQN6(5-!~*KZ-bBumy5
znU4hbPw5vu#DfrS|LaB=t;W$NL=+93H2sO|VrvarAzp(}!aznDtHh2`yr_Q-0hjh6
zwoKe{-sa3n-Y89kl!^|v+uMh;p0l!4n;oT*caSQ_@ULn~<el9f8cjIUX(h|dg2@5y
zh2cl*n+1w;mN;;ZS2GlB?7V#U()VFvqUEbl-8HA-nv6o@bK*8Goi38hIjVMJ^CuRC
zDH%DfZGwdK3#qUAh1PW=gGY8d%kVbi{`e`!X~IZgZ`Tz!#NuS<eZFzeE4cM9i<U0L
zL49mM=}TN<4eBLopD6sLlR#|N)tFmZ-(JK(<Ux6TqF{~erozTT?|UOwg$zSkMsX=A
zt0^I+GM{~NLtG;m)s@`X4;hm;CY`L0go|-r+UaBHZ%9l!h`rtf&|V1Ug|{8k(tx$p
zpP2rlmzMK3G!(nMwhb)MF-$bL0cjgsq{5oeuRgjt%TcibEJ>dc8K^s=T4b9viy{y$
zbiIu|&+=ayKJq|;+P2KxRkxUL#r~iP+R@)z1<am1A3YhM#!Nikx~Nq{V2hWeE(nDD
zjBK?|qQY*<n=T<&kg(t#;!v0$7NGGu5r@pPX0=WI)9>s$FA|$|*?kSe2+c2BVIygQ
zy?FHrmhgq3yq`}+?G&#FZBiZOXd>$1H(v`l=k3d8=(TjIqP#8xAnD0n+XUuQumt6S
zJ!G&AoIfr1rHism#e6Z=2m%ueo+?GO6G~m-sN&XpJ`o8&OBakAP;h;UL+wE<F~7zo
z-67-na#Vg#qPH3l)=_nqf0B?<iLLdMDpBZ1^p}qwM4j*c0=F<K*Kmxp2W?JP`;{_0
z=Eb^dXF@Lmg@hFbz@$ad?+#JX{ewkqDQ$!hk926e!~LnfZs9t0rA7MQ#5<<Whd(W3
zwWNk3!|~q9r(qAM9k)HNte1iK;LRLwLk(53-toGiDAZa|u%2%Q*l741;Xy4@^5=Og
zQnff(LXdyJTK#(*0F!i>>3wd$>1AikR~V~$wI?*dT->FqJnG4(Ks4BjR*P4^EK9Ia
z-Cf$gOW{7V^2FYtX+L2@mql0un99U2kSn**&gHJ&O<JtsELQMh$G)je<yXz_Wq7fE
z5_Rj4gwC$B57`O(SSuAGF;}K;tiQh6SnjSIq2@Q3w*vv`187@6({1~Q%#Q2#H}R(3
z22@!r4%>-aryHoB?s(Yh7{gwdUeid<;n}*orZ=8-u%G?=^k<p@G-~ON5lmyuRb9R{
z&?rwdYP!CCrK7#VI&t(<!>rv;4LG@fhLJ{m{I7eyIGhMxaLJG>>nkqX@~_Ppb0|1$
z#D5EUO|0x>NG@ZsHgm1thAr=ozwloF`+=rADTeqoG#OxZQv3jRDf%3@=N8ZmwB8U0
zX()!H2GKOm6b#TYIVcO{$WyrNspY-HLEtC<QV~6cBuC(tYsL3rSa36CyC=Dccg;@k
z*QeDP&lj><TEzM47Ct@wq}KySYN#mjaQgpZk*+fA)O;gJvIrhci9ffd2HfQfTk^KY
z#4`u5wew4gkmQEoMf6-_Lj{C9xb@ObID8k>a>l_M2%5t{wkF&{thiFj31f9Bo3P9~
zPAzN%b4pTydC$vTU^oD|0?rsi@H;5$6h{PiU$r`*iYv(mjk=dDcv<w4nh{csC8EX9
zF*NP3IU`x$!8p6CW%%{dpMo*Yflaf#J<d8yN_RgraboG)PNcx39&Kmm@WF2ZY{xOu
zUExvJs!PQMRph5TMI=fc!*I=g$Y0DIs^Grg#GUKSxjaytP5*!$?;%f5vHgO35t^o2
zI`9*RQkpg)tN9Lxd8u#I)z!v>%I}F5@4)?u2F8QiL%SiOb6}M)d0;ij0^5<rZJ7c#
zHFfZ2@8RL}L$+pafJ~<h)~xzsC{H9Z$CaIYL^o(pEzg~%5t!07acf<tEX~&pynHYq
z1z9y0!}Hrqm%*9RPo36-A6(!^w3rI?`GkibG3^F2L%jtH2k6Nf9+o}pRJ!GB2Vm9X
zCTDsNO=RR-2|QjBb^C2jYuX{nEWQdVOnd~FgTOv5z?oH*b}IB;dtpW9$b$5R$I_qI
zqpB%zRquW#q>-a7iq}1`(@;J&E%9ifY$%&X-pi?{R0p97E_o~@dexscOBU#p&6ECg
zuz1WEp<$yHQ9eb|r8E1fo*v!kR{7WTJ;YAGAq4mDf3?<bw=cu6!LseH0Nd)`Zte@#
zt8M9mQLwZ_9{m_$ri6zfD|6uA>fExB_<?`&|E-ctSK-==1Pw&}J+8))6b&U|cE$F6
zPEH)~E4^CvKuz*m68U)Y4;)xEZBUZCFhX{5f2PtpYfF&32IMD*e71r3wGw?n-@f;5
zQl20>G|R5@&17f=kI}JbqIh3(g9)@pVRYh=gKHSqL$P|{GDalKwK-QDdwH2tNRoyo
z^8OZm+g2OHP8Zq+acm|ybp8ED91ggiAk0r`z5B|$R3yj^j<D9T%q%*GZchEOhAl;!
z+Vp@DZaQ1L=~L&B_8eDPj@@$r7?#M3$dt=?937AySBb_hf8?VByU=`6PNJo=H9xm0
zBg{`n)ySJ}-FsH7MH2U9qU;#O&@R%dI!Ip+>29<LE0}dQoDcS68RmEYv9QH-jSXP-
z+tnQr0+kBf$oeYeh_&Z%%Z$--6ZI!GUM}+zGH{VLXdN6Otp7MSc^u<-?tu1B@ZKO&
zkclNE?CEF+CBNd^R=G|Bj35J{zxqGtx#A=7dAB8r^1HK2=3!~m8$Zqu4D)kZ4sB>1
zZ`25u5a|TRgkuM!emhl9`B$q8My#M|j7y1J+2!+kl8k7$dO+BYCUsUM#@hf)F^+VL
zhJIm;2bTso$L<w^)_CPr#abJM$%wkO<u}U|I(vAyr*g0)uH=tMx)*}Yp2J_p<0O^I
z0iy<bh0eOi%sw=Od^2xCkJAMhk#sL_Rg~SZrDe2nue^S@$65AATOqXQy2vJ-?^@cE
zYsE9BZWnMJ#A@!VlAV9P=NZARBI;-jW3=3=b+b8d#xQr+N?>&<wL=sbV#NlQh&sGO
zzk+WjklQHT_9=K$geiQ_xV>mBxO48jrtFT5U!MLL<UVjb%;-HE2i7}V4o-$e+1+~c
z*B$@dX`45A=^ruh#kfg~v<iO)5hmI9DKFeKnT-+%^|2Q;Mh8wFL!70>6$vNtLZ<+g
zUrfdf-VlX%8q4A5c?B#8=FBO6iie3fiD<NE^hxj5_qF}jm$YspsiZ_XWOw8kGZCJk
z1;S}xW}nZlh^C3PNQyXtVF@TuAYmdHj(%iRpA8^P`oueYaVu3%BulGLHyP`P#fB}f
zsNo7>O;~JvzK`P{A(dI>rvI5%26g9i`1s5{`F6nS52dIx@KjMgYnI%)(|iCqK*qns
z5iGiW2Gj{yky|GYDxS1F;yVODJG>8%8m&W$rR*Wu`FL`nFhtB?RMXOZN>rMGQXb>r
z)1aNggWD9=?&Bu=P(3xgpg<<&sG@EEquZrB*lR~!=5%y9YFnw^$_N2$QLOV)@&#-N
z6cbX=rA#ajTjS#Hj#4PzKAl8{!hTR%5HTb@#$cjCKK*-$;;2dwx9C=9Hxa^6(Y|K)
zEXo74X3SHC&f-_lclYL`i?YgF5cB&_b3n$E=$C2O#JpTWr;c2Nx18bWt%+9Nr=9Er
zBr<{9S<`EC8--36<8N)$DQ!W~#Ai%)CitR|ps|BIrh-A(g7xRcxe=`W@c=r1QrCBy
zEEXRqH##-*sW>+FkqI6TBdlc8O0drb=xaGqwVh{_oQEgYO=$;OeQ3C`fUB@lau2!X
zP1mTU*AuF4yq&NHUIP?YtkB>Lw9ajs)xH^*I-*CpjjqLB&HI47&~3_LcBF#VgxEJH
z4H|Bp)3BgzI_zVkL@E{Z824oVapcE-WW>^XA&_Ith}0C%dHIt%wG*@X=U8S|Mxi`P
zlqX+0L1=uJ=?8~Zsouhz()5T4Dwi*1j~qOO51hj^o3Ss4HJJ7dn?oL#KTW3;U;Blo
zLIvk<;PWA8S0*A@sVWiM*iJc&-{Ov<$C)@dbnO#BsoFfzJu&Iwa|q5{#yao1MY}=K
z7Nqa{2Zw{LpG82+p8iHDkgI4=h<6qu%dbJ3dI~!@JUpD(E=IyV(8?SU6i?By@4IgQ
zpboc+Gm-UwCxhNz+E30|Nu~z5xXMUF!{XBFkHJnf)x%+GoCvhT)|Xx_odSDD`fQu8
ztinl>?w93EkF%T_sjQR{5Vl?QdL&|EyY%Zvj{Pg8&~PhFv`^2_C574v>J3;N<<1&S
zQZx(TThy>N_K`3OwdVO`dDUn-nT$TtcZ({h!!d`r8k4?#s<Dk$C|guT!}x#ETq0~)
zk=uy&Ve_LM6u1~RVfnG5^VOL=>8ENlk;kPwT5ab?dj`IvWbyEy9U{Y?W}$qFQJufo
zKYd9lAt_J7w%fii8vN~ZtDnt6LvVhiDY_ZdgNe+gE9PeD?Emt=!aK?CeN!=iC1SbX
z^i=-FJmmZzLOt3Ox6_N_wK<>@Mm?x^r!aq@?2JdpsG;JlvpU1~m@}YPb4@69G$wPb
z4a-{v{^;s7zrwRI4HMry<+r7|<t5mjXkMx29s6nK5|cIh_Fq%eE>LlAE`WG3xls`9
z0aA>EbSeKBDI7>1igxLT0clrPVQkWJZWPf+d4r~Z!by>*L_~2t61}_*MozJI_k3G4
zMORgRO}S@?G`9HIH9|$iUxk|NGEl5!LpfnU#^S4yR}Vbj>QOGDz+$k#gg+coQ;Lh6
zrn0wp!*5j^%CJfEH887yj6N~MPwp<B`OqRsyr|6xT9b>*J1lk`+86dE!Utp3I84nD
zPehz_apP{tzppCIH`05gI)>$Bv#*NJuN_JTUSURR$}GO*aAzcomygJ+5-<b(jx$WT
z33biO+G+1g5lXw4$z>ao8-D-A>0*^Yf%!n!%e^W5<`(Q%$o$TN^AK@^$Sw>$F(Reo
z48;Tjm-~J$7&l&lJ8aAfl+g?!rhjv~{Ak&EdLD~9^1Dny%0@;<vL81nYw4o62*3_S
zsT^EGXA^}57H35<K&Y?(6mi1v)t{GVFaL2TFmT6caIc?$6OYJq0w@15gs>0DL6bQ3
zXTP088VJ36qt<-z=aD1UdA>OB<T`9A`d?Geq{HD;kx}zfh3f*X7M&}p1T*@G?EZ@#
zJzOfr2i<pa(_?pED^f&UJsRS7JC#y=JMzw=&7#WlX`w<byqJ9w*u|o2;j2GWGt`4A
zNVh9GT68~<7@<vFN)7v7n2hq%iOw@xFV!n#&thmMp-4FI)C1Kjs>xslvc39A(n*FY
zuVfmXh0~#)LEejgzgnmu@xF<LOB08&90+T0xeMhtqY3n<t0lj&cLuK4&!#4kNEvrD
zc)m{#vc>rzRBR>%bH&MeI0E7F7Daz^?3B;EBz2oG77R@=y<JWrwjYOscP+L(ZKqKI
zO%tA==iAMrE|Vh9`1U#&#hO|m>iw>Cr%bH$<kMmHO$B4{`dv^NaLU2VLz4f@P(O=6
z%!KMVb+l179YMNs#j8z~wo?IGX0#jO6U78oK+c=6XiuT%P!-EoH7Ro8S^sR-g=@7y
zmd2W#w8A{qCFa!ZG-wl^_wVtIs<LTx85dx)kNs?iHIxmHmdeVrL^|QR10xomn+%fB
z4+ZYqc`N?iVF)fqT_#7x9X0ZroWKMZa(UMXxvX@X{_td(zY7k!MpV}jLiwdoh=Um^
z1NA~kHJOU6lgf8~eTD6waG+?+mp)IUg3+-0vppU>=d-0d*`0on<V__P3aeOCn3z==
zu9L&QhlbP=l}h|Fm1)mY>|FV>;*UmLYtn${vbeLRxSF#Fm5m~#Y9%z|Ho|*W;a#c9
z$;68lC`BgL&rOoTZ*az(fGz+N69k24yui7*_U!%b5m?kX+o=eG;v>NX_ugslyR=@-
z{_b*J%<%vfA+_Az;?=Q666?WTzeqIfvnR&{2qMHXu|rv=B2STk&v>wG!yC`w_AP|t
z!5Q<*av*7Z+)c7e_@$OjGiGG!xF?Er*2`a=OTmg7AE-ct)S&}rEzh7RV_h-J>ot&+
z#R#Btcw+;i19)Km_BjyH5@%s2Hvz$n&~lWew~}&)=4JLiCOv)&C8VsYy-*<m8`>1u
ztOanTURCzCa~t<)5xKP~-r=Gmp%#7*S-P^Je!{FAhN}poz82iqvNLpXV!#MzAgDEb
z>g3Hvz}E`%Df0KE?a>2qg|ei)U)gqDEm}}J^&-l8=){4`qy&K@J#pl*o<@C2$WeuU
z?~CLPwGe&I#-ZK8WwY4fBCe@C@k5lgl*7T5`;M;C76UxX0w+AgO}D03d_C>mc0RjP
zl2gIAlX4LGyx)|<>BFK~E2MhO1YB)TQ>V_)tz%8~Zx}uHzhm0pDOVzFG7_M$pYMIZ
zbk1W6`BSeuK;uh|(p`%R?IwRjO*aM7nzKM?ttYQ@f~4|EDyQip7J+<Y?4>V0WwLGd
zvxyiDei(+x*h!NPQG757n1&zDIja>3s)oKcmJ3-?YneuBlG+E15aJWQd{50X?e$0q
znX+=MA1Ki?v5py@+MUPy4F4X;n<5?Jh~(EC`R{pO=!qS))QlfZJsXveVCyW|iyEVY
zoFK2Y;3us28;U3uzPW&K$g7zjT&!I;6lYN%`If?7v<ktP_Xh@l|4a3@i^5sy$lfa-
zobSK4GJK~vcM?;um^ww3JF!SuhU%C&`2??>>woK%Y`nJ?p*89?OiJUy(Sqo~IFUDv
ziGRatDYMcjnjI+Q&>U<`V5I=J$=0p#^dZ@gI#>-|Zp0OL*($k0^|KUOHq`9;zy~#)
zvsa5N-lgQ{vU!vkv^L=Vxl-pD5rs2Prx*xS`60hn2)Hd1O>RMNY%wS~>IPi0C15%c
zb@AaG5T^@+60FLk_Rao?jwXq*b&>&{zp=<WwSmmN_F+=Y_=g{?2<<A^qON4!1??iy
z{8$YPCZ`r6v4j0w%ax@Mk=)oqv(omirj{hCX5YA9PZhoxcw*xQ<A}!88`er7(9kgD
z4)7K<axhchb1YZU(=H@_<|5o&%`g_4iS@A8#hCiU(xTU5KHHb}1?+pgOPx$6=x7{m
zJAH(ScnPhq{+!OCYp4V=j=z{(8(W|)!$mM@F=b+Wu|Y1#%gH}BgUQ#>H;A;k_txN>
zK>+$L6-fdnV1zl?GyD+ySu&^ji={YvLg*P7Pb7qElW^`T14W7h93G~Ye**;{R^bQw
z@zy`hqS=8*(+_Ga+0Z4*QPddhw$Kby8Rawx+XhZrhu1vTyG?trfpSDLZriGKv>7R0
z*ajmW&X@(y*~XYVficAkohQ6oZHiPo%H?EY>#Mg>8q(Rp=2V+0+RilQQMkOHUaP{r
ztu&P#N{BpZ`_DuL5}QY(mzMCtuK;emeriTBrIKlPYfDw5bzR3GOr^+k4*dlO@{e23
zxc`hb=o1_p8=kP~1QZ)~Iwy~U90_1=o%M3P^JVKox)5UV5R!_gWgOv}3NV=mFKcE$
zeg~VlNZpNTl!ND4S4S8xRvwt<-9=4WiJf=~0%gcD1pFqrV6!WghWjfv=8E~ubTtcR
zBuuiLN<pZ%G5QY$@2b<0B{NIc2}F|VT#H`|3bOW(6^zfIHTz-K`L$kt@fZ>y_YeD`
z%*4D!t&&0c;Cq4Rp6q9G&V&6x?K&0ZxJazWv+HieJmYynN9;EQ8{6IP+Bt$KuNP?J
zn+@g>kjoHreid7{LUpfDikp_vOOL7zT@H0Lk+<UV@}WYuS$EbGF|4^bb?(AZl{hT~
z1+yP!;*k>wx+vh&n4*iV@c;mW&5s)SA6nhBcNZ_@j8G(-X#n?>TL=uxTp;qKuR8V2
zXC(*mq$n6D$T+&jSFPtD;6nKZs$o{w<Wm))ZU3dda4NGyVYcJ%KCq4sTha9AnkxhI
zwtC%4jOrXimg^yYWEYgssZFTpw7H((bT+i!XnFm3Xy2!i21*xE+D<Ii)#SD5489KK
zmRD~d%biHQttl*}m*}k>n(i8_e>}DEhl}`?o9yHy_E=^E-)H_*4ynhBN#1#3>5*j=
zMgppY${-AwvzgT_wHOUaL%U<UK+z3;AJ;${f2+pQCYc~W-yr-*C<wn+e~&L6A@F)4
zO3o7>QZOV=2oDpTfg8&7=6NE~Lfok*(vgnmVBNJezWL``&A8BX`C%7!i2+BC|0|Es
zjO`mV*N_Pr3{N_2jAM>-4tC|R9G3h;buj5F7VsapPXExO0DAJ6;LC9Fb~UMs54<gg
z71jG2<(E^I%`%5;Csff(OGUnc?GTVoVq><vHXTMKv*_;_q6zyvca<V>O_)WF^4=gH
ztcw86thiSJaI<Sq9AiMR07WZw@oM51d(3k{J7t2ZsR(>D$!ut%dFX>~zpUJV6M9EC
z8Xcc<)hI;1d(3b7b&{cA^E-~(8>{yGKEyAnh3!dRQ+)Z^#iJ0cT?AJnI;QDo$LY3s
z-xo@-Hp1>d$|d0RPnL()n;1~t^gj=krB>|dJj#LHd>Z5}3${`(=y^q=^V38`$4o8p
zd|PNnYF{=zp6SknI9p4d;LmhM;=)al2d^*#tabWd+Z{M#Z5tnM*7AJ_+NH&oJ-#_r
zlZJT|#<;LSc78tIFiOr;3&}G#jV7`q4Tmj$N$Lhz$`{8p9L*TY>W|b@?9@%#Ns=Rs
zYsXRj5Oc?zGfgcaPwpCh<~yzGo<AF7F#>l)b`@X)v_*=f<7UA#D^;f}2;t*~?__+w
zq+<-$pnj%W)id_fxrAQiywMjpd-b0;Me-}*VIxR&vy4?^A#p*c(SGrS6CUKU=ijI0
z<b~9gz=i64Bg-NDP5q6mjhQ1D4u_LiQizjtQUfJ3(vReB(r^hi<)kVpw6yg&0xinA
zK*&9L$}52mt&{e~?4#7)1SWjnmM1bD$}qd&jt=lEPsj?j7;pP0ziGJW2Tw{q^ni+|
zRLu%6>Uo0Tt-D_>mTw=J-+nNQG}0?XdQI6S0(3!Mm*GVImVn%y^(Cm;#dp!fPacGT
z<CtnFtoJe8aJBM?5yf^<>2y*k5hYt=ln^H~k)+f)D09OhceH<$j-k(mK@*~cr&$jj
z4TMU6vZtGB2DOg6Rc@rr>nWH2h2NpHt2Lmw&U?aE&#yt`L)p}XCI~fnsM`)0L45U`
zu_2HkrM0<?{N7wjF7bm!Yesv7*&|s4y>`xS1`df95;HS++Hp%9370#@^7$e#Xy*2~
zwdT}TdoH8xA<u3#c(PXD&t(gHd2dJj1$<!IUjMU7f=<=tbA*sn@DdGPxDTCrTl!I)
z_`8v;H`NXLF{cCMAda;OYNCvpZ#x1YC?E2O#ZWAaiJ9y5p0h3UfzwdI+WpJo_sUgf
zBEX)Ga>LjpkB{*UC4gY)rvT;}Ap{RerRGBLovy)r-`f>`4GQQc!u|04+(l(wKuo<^
zrFlmWjBW~}cy1u*EtzfN*zVMGuI6h+U9YeXWq8|)%b(-n5&hW|^5Sl%l$KVW#(Z!R
z_C@G()?r^~iK=p-xwKzROKV7YX>*C<;?clwp<n)^byNesc}!%^{n4<6&71knrm0@`
zhR_Y4&D~#tTotKtQy>9`+_=PPnG4q0HBMg!`cL2oVB-R|hF|B*-Bh4u?qOnKkD0F6
zPUYR)i+ddExKS;6(it(wr6}?qyk*{soEy0RSXcN@oU!1wIXR0}H5UI+YUp0lQ2jJ7
z%!U3qrttFFGbLw-SD|KZd=%;2;XpYyTAByU+XbN-L9rJ*M9)a?gDOM;*<S7VcX{uN
zn&s=MuKXw{b?49wM(d6_X!vlTR*I$rk|xzUE$&Ljh$0z1D2Qy;zFb^Ac{ku<BSgS7
zT$$CUuFIZKNTuT8^pi}-xaGYrqSG`BysJQ<?*aGY<8VBc64oK`WQu9)p;*Cbha?Gj
ziyjCt#$%eppSCchU_`}X&dgnRNBWZH@o%;3)4TOm$^(8eLRFa5Qjh_VzhG<b(zD(7
z4ABKzfjN+aU3E=s1zQo6>OVc@Lya)SNc`ydftmj9TYyV_up^dHz+1u&fCR1jW+RM3
zdlZc~B`t)ObzETm)o2&!2&gOdluwCU`@slx3)Z&6O_G8c+$b;78E8ep<1|oRg)@r}
zGc4F|_T3FpYLy_b;Xj0THj_Gn)K7C7oaDzP$JlO~N!rg9eP)_aaxdbS{7%C%8O6@i
zeS?G09{hsa&BJlDa+%roOQ8-jOYsY%_J(ice8mrO=RwOR_`L^$0-w;<cnmeGUr`IR
zO{(!?01=biLUaoG92^D>kZtXR!p|Z>+^9~(Bz?|4f*}xW^B89~k}atmZf1kon`zF(
zoDNgx668#Jug}xc6&tyh%=$q#Xf|q-vt4I`Gf5)?iBb8ZgbJQqVlGMLaG2e8b)0;b
z)Q?MdZ>3vp<Ji2n_?u5+MIJeSMlTJ4ZQBl@6^aZUCm|o%J&6ftb|ZEDjuk)I6*E^A
z1+ezT(VqrN@w;J&p>vMEx}5*5>wN|##M3@6DY9tN*{Qv+dc7wbsBq*kG8EBPqLM?j
zKGVOWP<3i~tru(Eyc@W=`v*!08h~_1)GGlew=^wg9YbN;uh3TZVQXS2Dnii0gmob#
z$jo0-oMDF*ywM>ZxQl^EHF*fCpF5_t={%_qy^OF8`jCZkV9Q*R@A6N>th4oE@E*p!
z$@PF=F*5H#sVeyG>ioC7Pvp=%-wqUB9l|r{a4=*RYiv?4f`<om7Y!M>M2Z2>w$bBa
zr>SAsz!`kYkN}}sZCHQxYSXxA*f)1}`-1*7W8vqQ*6_|NjEORwFPxbP9lc$49mc%d
zP=`v_`ZhAPIzInY|6bB}hC5k=8tUSRY`V=9*Vdtqy|EJ`-DL)4mau@yTlOil4fE}n
zte0t`PPh$fZGQ%Sx?0csTR5Pf6l@(F{J6w53b(gAzTEZqmM7k;By%;RwV(;Q0_RR<
zjf)FF8K-&pQrnh5v-%UOB<g+9e7p|AYEFU98CS&S_EBUfj&^!aXDT4`>jEnFo=mHZ
zE9~)uy-~~ry65CIr?3XA1>hj03z;#`>gEnSkD>=^Rt|rW`rJd3;cc}vjhF1%-Wg}W
z6B%#+Ge-u#keBGDuOFcoLt+q1n5`9dng@S2S%CfVB}KzK-(ceyUt%Ffd7awa99DqK
z8Z+$By<^Q{79*Z@z;X5XAM+KCMNhuc!B3LSY<NA>o9dhzxn%=rR<;Btt!UJDIgx<5
z!qQ$)JEq5epHzE=!#JNt#c3L(W~wgf2_;i7TcTC2+QEORtC1d7hK;3iTM#pbki_`7
zte(FAa%35s)M`fh{kasEquFBcQ3WIPSi-`6q1<p$ZnxAZe9#g-hEBKKXK4e+kD8~7
z;X2+2U>(;R$Oa)?60nLO>nbD~Lfu@Kh7S|OAGxAGUgtMo4NNgV14!&e=wD<}4HuKe
zcB>Pc$gm}Xr5U!kn0Q|OH^WV7JOlYvM29-~9ezkBcs7Rtx0ws))axP6Z1HP?t!b%j
z>LB<X<4D!I4N8=iKK-dWt8a4n<SiM0)4CSACxbJ+T=DrkzHz~)P!3Ei&DZ^~I#)pB
z<@in-1P6r_N>AYwmGwP`bIuc|K+~eis;chKjeU>>qG9?(pSoN(Z%IhR1!wJ{rIBoO
zj@7@oIfB^=804Bgx@+)?(lfq`h1B|HOBu{sfsxf?;%@O7N#5+_M6l|thd5QGw_-oo
z1Y%=5FfS8Z+>lJP=Vbh^9}X<QH#^Vr4KabGMf3yKYhKgY3b|Y|5|~7E)RHRY{)P5C
zVj?B$^;XmeV~C*wK(p&5+T6Fo?;Iaqm`;jD<+5hCFGWh(-rIO=0n*d^{B$c4dmwM8
zrHcM`suR&bRu7F0TuPF}?Q9CJ>_1tV?2Q;6U`JZ&0O7G>V=3|ZEAZ=V%DErx0-Mpx
zxr^(-2Y}@Zot1YE1stp03f^u1PUjDs1s@?HbFfCkUS5|6tBhSu{2t&?@Z`$J&!oxn
z6jjUAQkT&SC`-a3zm0e&xwGsS5_d&3u$o4$HKYhXQ3<>`eJF$zr1~nPE*8%4Mi^mc
zQCOXxig}jDbAj32N2(2?)OuFtiQX8{0R1vSc(A-m7a{=kizC&__6S`{Wpgag^gjQ^
zhTndhADiz<Jm<%g;wFKUgel*}(Vat9drRWLg#oh7f5CG#LtzJ{{X9ILVX&bHvspI*
z()&@@gmwhha@YM3P0pY1m}FF4%w39q4;LFHVYaEf%VRf4XvA!X!%q}mpwq{E>+!VZ
z5TUFbHn3#$5Kk_ha>PlPg}7|^B}2HW-?+hGugAcC;a;FwH?!^6sae$<2&EDv91N|>
z((BSSeaE!2r$<cV;S&X(QIk6<JVGk9X?DO+g#q-^_Cwi9rmh!<k2~j=phw6*xZ9?S
zT0qDt0SlaT9N<9E?G|O9LA;O`0lqd;-2fhWjk1>+kY*90v*E+xNH!Caixw_LuOPf5
z=Dw^naj-}jkillFMy^gS+V)}+N6xyP@Qj!n>Q^FJ?<Y1@d`RALdR^F&6#&@k(Bl5s
zSO^Ugi}4Wpj*G@abT2T7{JK;BEs1R0VL1lZLwG@9wRqqur+53Cwer@Vqg6RoY|bls
zoYz7)9Y+Wc*Ww<!bSvo)!~a#;Zy-a@61F_XI_IN5rjS^=UlAX)p0+jgjf<`Xam_gd
zR-c(_C=QOH0DNqnz$zhyBaTk|vIh@Ze`&t@>F$ii<KDejRCuoh9x6e{O*--l=1p>?
z=*?gRF?4ykR=}TZ>D8udG-}E-*-I-f>3gZSd&ZIx0Hz!+JTEd%lIt_yd}ckq3Q9J9
zFfGmX|8xwxio{=j4h?Zr!kcfLIPY>1O?m#5G)i4;#UVEv!ELc|T`*i+zqyvNMzf>R
z(1&m`XiKpg4pQ*4sRLH-3Mhe`g1Wi~K~^8{jsslrFTb`NWuVsVHvpaey@A(~<tC$Q
zjG?D$4_%QcCuW;UeSpDt$fSf)!<mYtEd*hN@UtD2k7Nv1_(LaTns2i5V};5$0ete=
zSmjQa%*!!60AYFHzz-L!L@HwT!MGST&n;>Ag5N6Zyqg(iPpA;qeI`AHPcG8{L(E0V
zS~gIpuVwo$%K~5D;`Fj-hCmAsfKV9&N?a=s!H{O;M4dmIu%OcJaQym0b%RGoUe~f|
zIYBb?{QmPI<%|@t(50I4S9*9u)IIl(SyXuw|K>Qk%^;HqM+n!}ens)*F&JF{&B-JA
zz?RdnK+J!>KK<1vb*c_wb@=_G#sc&q8&$^T8`}|_y5i;*@ZzqCQ`F5*^j{I3T!+RQ
z7Q!{C=A9vC=4(huDPXs@IZ=`oNONAlH<f2rx*KaVU#N-VlOgttb()I;c)|Cs;R}RP
zQ7H=mmQGyQzIxVY-98aoVAr(pwAGe@o>cO0SkqE`{Jj~xq0pY}x<2LPMqhi<&NOQZ
z)ANmWvLmjw5Z*Yp7Su9(7{2RvVOOy|C>#G&B*XaN@BQ(vG>3-cdc4P!`+pQeW`S(-
zVgN(pl%8=EhPNyr2s4~F$i$Se8Zi$xNpAubzMz6ze9m`5VLXQaJOl{d#Hr#INp<c@
zl`8B#nf~l9hH#t0oxo?<3(n@^tD=VtJ(6{PUxP|GF$P>*aB<ja8{SY+XB-aJA93^b
zz548?D-T;v-#YJUt1IxBkl+3m{q`q*R0uy^JzfM_&-<834g2@h6d$V;xl+C81Qdap
z;>O=-^tVOU>jV}2C}+Nd*-ZoTxZ4miZ9f@4@@c46!g*rDORZL`xGLl^m@#{i@0nSr
zo6@1nc5+V@p7WdSt-(}RZ>PnRPE|+aM`K)P$C1V<HE^)lUGu)&Wv%?mPq;UZI}y5)
zkCTaGqPFl!CmHy5z=sz-^FbDY2W$P&GQk5Gv~T_h6X2gMVkQ?gRN<m$M$$B}+tU`V
z84Px-T4qa&D0V`<gLT6f)$cDzsw}gauEP&1o(lW#;hv_GmkC|%t1}?D+-fYNj_rm$
zhF-OBpESdJZk%=y4kpx{VSEo^mHh~<d5f6JZE$a^W8g6cEE|->mu-zH%+<by)PUE<
zz~cbzGNtmK2N`S8O29AAoV*;BU&_Z^1B5R1krvtUYsgC@@u>k3uWknnj}>oZW^J{2
zQ!U{uZdo~Nw=-vz)fvwV@Ts-+&iGMn#dNf<31?M#ECA7oj@B_8v<{7qM_6z+pScCX
zbTm9Ku#%k@E3U^|Ll?2|%QidFhrND(`mA989XX#a8ah+4gWQDvp||2cV|&&swUfm6
z<pcwgqUmbn+eE?C|G#O{ZB1zVAx{p=bqxENCW22v6iY?s7Y)E0uihqy>F6ta+lqT&
z&<(sRbS`mFDB@{fg%m3ew3_Jmn)a+vLYK>i1%+c&n({W8g~QW4odp-6&-+3hBS>UB
zQCHHtffDxAz`#HIv&zppKWYyhw1mb0oD#WByF!oRtyFKgeSOGm$qpsJc_uJU!g!wU
z-77Pc1g=fB<5FJK?~b$sr5COkw#?=iGs%(XRcB9*s~znEn*`{3AEyA$(Vcw;3QQJ2
zpW{|CBuGowI9DJS8dO{Bt#eKBUe@Eo+w4y9<OaFHpa-L2SkHEGVZCaG|H(0Obd>h7
zUld1B#=O}_^7>Cct*5C>>&Fp8*rjwf(YL#7Lp^GHYrAddyytr+fGVda><rUAe#9oV
zChuiGk$wP0=;vR;TZ(3P!}W&lJCBc`M;xcEmZ7yegcY%JV|=OHxoR)~fiq&5fCZuC
zzN{*n!$-qqjKG(?#9R%J($cI!<OX?k*^`K#fWe0@7#VeaA>G>0c6cInAc^~MIIvZp
zJ@rSy^=&v>)=|fNyG0l9bJg?9t2hY>SArVhmT>2Xot{Ba-Du1}N2gTX1#;0<kBO-4
ze`P|?7Gwv1XtfN6@&r%}9cb`BHK|ih&Dz&QmYgnk0EYiV`nsBso-te!oqzIPMcRl=
z=dvw4Vh?4_b%k^N^PqVPl`Ze?7-dep4iytybpUTW16+x-nvb;23YWe-l(nFO>koX2
zZV6!`&4K5YH(|AfPpnecU}9WCW?xt7E7$lmvAFkXQ}>uQRx9)v99G^Himu$WwILfX
z)y41H6a+0sFq-YTuB*j?O*gkHgL`>a`MZ&S{4HF)dPmQx?CIy1T$K57Lxm?Fxgren
zX&z^b%p>VnJCb3HqTpr{#4T{i%Uk-G2BVg&h!21K#-5!WrgTK^j6SZZ!~2sFP76uo
zzCW*<nC4Z<!$P#F8)xv{%Qtjw=(GIdIEEz=TO(WeAlwEXU*owri@{O;*NPBC%z!+E
zB9K()w>8OT^I1kVbsMtU*;5~%YwKs|>_?kSSKaTNfMQaUDkpB^qj_h%Z@b;SKR_vI
zY>+$@$~=v(LA#HjWED!XpY;f|EDHmv=V!IwaBkG$&#D)awXLSVCrvyfKQgC8U(7MP
z=-cc(&C<<{5Ow5Mv_Ls;0xbf`yk603)7tP@K@C;BBWzs8cMN~IQh4CR+a2y%d=|s+
z?2s^hv&~PYTnRq$`g}idL)2ZoeaH{-EJhPbyxM~+PzLLhutxWwVeki;CxOcI=o^63
zITd!fFhDO^FXpFi0z}<DZ|ef&$-Fd3Y?c_t=j<y{Tu7JIE|jEAl)KCQ8efX^u$bii
ztf{b`&ea%_<%y|*o}-L!VCJsR#Fj<V6ZXL~z<N@sOK4S6D`76hxY-f#^+f4+otOnt
zS-YJDhc?b0&D8O;A0s4NnJr2CeT3Pmm(|H-|M(}%?y)gRv^JY<XO#sEhv27V?9L^w
z%ap$c0YcHG2{PssIFl&O-~D#4CxGR&y=!H*ab(8X50#>#vEw-6|B9Rdmt+#Xk3Z|$
zxHM|g@`A1}NTo}t8#g^2o1HFf-k+usoEIw<0ej+$LFtn6zxc6VU}H6ZYjG{|;5wl@
zWApHYwTn+l%hE;Cx8}gDF>Mkg({V}<Y7!yeb;M*9$E}L^RHN;LFI6K}(bW#Me--hH
zpy_V`Bc=TfHNjhW-K?+5kG>IN3|zDz8E*(1F_fQ_KHA#cbY_SXgX5FGIc1*o1n+Sh
zc=Q~v+`@F0iIYb-`g8e*7N7N|Hx&_(OoRwA2Sc-=qH9w>!9Jhheo~r7u#SamXoaGz
zdjowB;!r7g4n2v3vb<-}vb?Px&3^OKA_b{Y;O2wE6fSv8zru4oc>AD=f=gQ5o$3QK
z-HNNST%4>ovk3kcB~s0AJ`BZ%*v+{aD^0vqt2i4c_e~{&AB2)ZhM7le+~RPixy!)<
z)9Xt7uXID^e<}RZ>k%~uyMrWay$OA_QJAJpw%9@?7|gSewUKYS7~2CThvR9zn~{EW
zTBOlSrYPT3EqOF?lOmqF>uAoR3krIYv1U6SPE%XjvaT^5Zj7lj&!&`YA%L%~w)V|J
zxh(8O>Pt^ACIr#f2%UaB2X#ss#jd2%LVNhhdUE21h1i=>CEyKZ@cSsj*coR>6GtA7
zl0Zr@kJY0`rZTk&P3iU9PUKjg6Yfp9a-8dSKehN<$sQYHu*%uW7(lt$KhB9?wys=7
z${{D<Wj5e}0HGi{q%Y(0@KKRq1w{f=#8YP`?}E1+=WUqN;8B-o(vk75ny4MV^X1E~
zHoXb~0otsp#T-`+5*%OktXL}m(&z`*LY?1#{y^ZUIa#PM<TMXCcl!7~9PaleTeiZM
ztl4Y+++Sp-JLXPm@hyY>@zrj!j};RJ`32s@Fo4f=3;74-FvaXsZ7Xv9jz9;r{2Y93
z%+af2*qbcdo8RZ!wlm`T@0{mXn*hl7+Txc+A&rb(2+(_BU(cl1;qYy7MdIAAnnE($
zv);bjv!vgh+iWFsv%29Dg=C(HZDFv5%_{u9Cp6*9+d~qrJOHHoLZn+ViqyPh>|2*D
zZrYXR<33L1h(7+cxMOuy69u+)n*ih15SDqFnzFyCIHmmm>Xd<TJ`h!X$+<;p|NeJ7
z+Xb{eM<~}KvE*?unc5pf6TF?N)HZpgm)edGkx0_?CQBg3lfALi(jPt+>e;(9{kVe6
zpi_JLgHEn4rx27j=amS>wCd6u6gE{;hT>h6=eM3lsC||>TC^ls=tp$ixZIPaz4q4g
z>!jd|;FI)dBW}Vz_^o&-u<jP`zn*W#nO8sdMsH^Hp+s^QFH(@7jqh=IBY6Z>-VGdH
z0AsK-qi@&!JHl|(N4h4=+~dORBXQh|oM19|WCYGL^GHcUgJysQOz`HJ_E>7x$0Qq5
zLEofdm@F1kVNLoWs0t@)%{JN6pr0Tc96Z%m)({GCbZZ6?2eG|Bax!uvh%)#TWdh{0
zpbdX7yr4Kb33*!Fv~17a7{|he90$&bZs=y1)gv9pxA3sTY;j!o`2jrJkOJX`!Trig
z);#+|xvNgIzf~t1b;?@2D*w?=XheCnCJp<zoL@e>wKEw|&oEdD?=o+8zh&6`>#mVL
zO6}9_O<GaN|JQcef#~8HLjA4!WUWZrIdX^*MERjfnlo+ngWbOtsgU7i`W&jN;rm6@
z-c!8=OD(8oa7I_nje@K5siiZi=if&*oH*laAwb$#n>@MKO!)Mv*M*QBac@JBBnaPJ
z5UP}A&GRIH)1~NLI^Kdljlvzxq?}QWQZKiG8FyB0=Z|vyF+W^w+r<t&Xon7tL0=U;
zoX}CRvK3NV<yMU=Suw^p5H?<%MmzUmyvR~alq4$oFdo&EZFAOiF)#gqW3!W0{@7ad
zEf@Omg+FhpcDnbV11m|zvVKw|-4r&yUTv{K65XJO+r97gTO(euFcN*e{4{8Tl7qm%
zL3`k<r!QkScExo~=x0e}HqWv(#K}XlXWK;XpL_!ZaQ_k8DuHPCsqR1HHwE_5eSbki
zt}D{m<PB-D^*UDLt<$I9M}0<-IE7};-+@X_pPM|}^Rnq(k#7|s{o$k`v3%krG|G71
zB!iQlTwE4XRTX6KuZul=ent6x%Sco*w>2l}WagT-X1Nm6(*d5%lgfZs^Uf8cHER=U
zHJHamTE2NNZR0Pe{bEQ3+#PW-u>2Yir%FK(7BIWc(@f>U;+wP_bNs}xopBi~vCrYn
zVh#x!JshC#J}&J&BURMCb<}?MIXVFN@&<Ww>)Etgks}JY$wkh;u$P;3AOPhi#Jm~i
zacDMA>mU8#gFqvu+5u6KY1e8d8i7z&<_M09R?D5h=-%DZQza8P74RYlO|8olXx!UU
zS<Dm>W)QFdwtG%yJgZmZx!`A-lQ0Ao{8ENlJdR{*9a{uzd2>Q=+C7D)?H!j-%=d+Q
zwlhr+-RbOtuGHvV9jJ_ExKcFeL+9U|LTh-Uo}wlg`pH@EdZf~$_yfX=I)Xh4TVBvl
zIhc{(QkQL(>WilGBGF+GO12jl$M<o@ZWC@BnFM3HbI899e3N=pR~^-lU3p7{JUsUW
z36`oe1;<Y(kcohoLo!nHq45ajDOe^ssjLO*LI#-NU$7vV?1IqD<h^qs`**dgdYwt#
z^^Dm@xUS*4HFt|pyCYUlCCbl14Ey!VzjD-7m+Q!7X~>0cswVz0_tSXyi;ow#=PT+g
z7(Qy3!Mn%)g8s$CN*YY$8JODtChM?4o5BCfeS$j3t)j-DNA4h{slLvB@N<Z-k?y{8
zMA@XAt#m4mbjF<7Fqu2y<#K@9c|j7ym=hOOz!h`8;s9eue2W}9y{vW}v+l8hQq*oV
zu!;W*!{u>(_E=~mdvc~P@wk;{ECj1R-ta{(6iBZ8B)=EbNqmk`Fbx;>vmepS+!=-J
zYu|F!%h7Y|Sz5f6DrR_>(i1dCO{e`pcAMLQUYP|UOQFMidnoPvVu<HLrI8upFc`VM
z^qY+Zv#4jje*w7O>Pv`V-Fr7mFSx`ZP-<PEdlWGHpsVD2kBZ7^I5eY=!PpqiESUm%
ziuU1&$z{1C*<0l`8^F<}OWX1DlrAEWd%;s>?3S5TTSgB;U5`BmhN?fBJ;Iy(j<H;#
zaf6VjC`q5HT(5BJBm&GJ+)09%q~!+H<;!X$_d@wO;aej-mj5QzVM-W*K7;pV<lgcv
zJ+e%);EOg3s2T@y@rj44NU|$YqeKV#dxzP!&I(j689LIK*u)G-Lm|BP5&sZosD+PD
zdij5X#zR<whfguAAnYW9$U3b>HiJ<VRK~Y;Ez#gA7}gEQ`GmUE7f`4BfkbS3xI?^O
z5-oC$jsYiktMR6ukb2FOvDXGY7aX>r>L|Mf-;fu52BqO@?{|DgZ(X%_M!p`SNCI;o
z(y0qZLY{cd(w<b+XSXFc*%+?|0k%;JrmZ|+jq1G6ETZ?p90-z{G>x{o&!gY^Jx&mE
z)fi-u&SZN0lh)$<2GJpR)>8?;?!VFQfx+c#v?&MMpj4aNHHI_9S2JOE2gCTf@A9?I
zQc?whhkFDMR@cFbU~AzEQSMHROF)H4PO@389Y9>P{Ccn1-o}>_VFl-N^Kld8Bo6z>
zYNV;dRvIq1B_4W2nA5O>Efi)=o2=AS`UvXibY<n8-jV}GYUSISjnnb2dDt%y{D$yC
zM{x4heLIHNx2C0jQjBA!uyU{=mVqoK7%0{S`Z@-0Whl|2ln!#;O<L>&iCFyKC$>a_
zF5M|Nv=s12z!*e*nDNy?5)|8-qzwwzAA}bgI-7Q&CGy4Mk`OdvptrI|Cd;2$`($Z7
z-ss@330}bhHs*)A_L0m??IcO|#*Nf*4ZJew-(oUGc%JSH=D#w>3{|^%^(>=8@gD6A
zJ1x?3nK=rNr?c{MnXLExaVuD%qD)1|L<;F3TCY{I2PQy7dG>cq*o@CFGvOO#SX>wX
zQn)Q~NX@|LGP|eFz?r|>Y?E#TZOT<$PxbsllDJ0P!GtN*vnFOf`G%@&j5tfvvrTsw
zfZpoz$QLPm)~~?@GA=XVk!=d)<bVK)N!!U)wXMvt2HA{y7XgAEO|F{ag6Y}68Jjn8
zj?KG#dZufTd?ZsRl?`-|a(ON(OiqDlROxbkjVC`7`10idF#zje-7sS8ZGlz&%(0$F
zR`S7cAg`{LTwvoMId2<;-+F9_%D&qV?!=Ax(VW)GHX`5_x*N5(;VjEqi#G{!e8TmF
zD~)&pfb|5*abf}ep(OOFuY?{5!~`H)se?7{k@Lk^LMBP}Q+tBbad?^(Ic;|?|B-g4
zn}6W@w7jh0&Y_J{5;rXUt=H*9A-rr9j=86c@3R{%@8jNq7BGYA#X-{xxQ2l(x$nSW
z<R<LS__)B{tbtMwo?L06O_kz>el53SUj(~<ck{tqNf$tsl_z25as(sj-m`NmAiZ8q
zo8XV#I>=Y$T_I${u`GE?ilk|!hTeXEl?xx8gQ9h5E6wJ~47&51gp;0NvhSX6v9d#R
zGdQ)H$SYYEep1C)53?jg?6VT_nV#>{d9E^;h<ue!k_N47=a1KhpJyzvJ>KJNh;7P7
zes&_;`8aJ}5T_pn?GS|GcU1mf;lJ2|9$mD4xzMu&3KHK|xX>?;9@{OIs}hK=$lWU2
zWi&K~^%@v-qGl?XurWzq)<T@4GK5l{4=uUgnmit-S|ukjA!UNTUHyDkA=DBLORuIx
zUJ`j|Y7r1rf==a^HyJ83{Zyl3Hkwk`j=lHODV|SZeH!2An0oFNAkfFv_Rk9;#EJUm
zMula1y0PVi++xPrr#vKOAkr{0ve=`sSN;X`a@!rFc4%ae12+6XNH;?N62Wz!M{Sql
zP+R`PdK{V(M>5Ay{Zx@V!u|fZws~GCE=swY9UbeK&iEb&$_LAV=RQLa#%4mOu=A1g
z$<-(rjjyUK3W3))nrs?B24Y*9)=+O6umrc0>RDm-Kt$?P3_(%w-$YUaS1OxAWRyjI
zFi?+%FOu+5>$pD9ERsmuYu|GGX>!i0;pMXRftB6>_1JCQuVbF9@Qd5KuD`4_0#~dW
zWlYIACHwMk6@<_Q=m%<p)LwTw8Y2>0FtJSkmo4t>4kvR5&d`!iFmgcGQ)E}UJs0RT
zXr#mSx4yRiIz=RJ<NG5vMDHl!Z~l<gSvQ!C*{))yrNXsmrzvaIsv>NEbmFE@6>aQ>
zY731YOW-FgN0(#62Ll$GmnW|GX7@FW<^?Gu@QbP*h~<1821fg96xB9R+0FNpH(bC1
z5@4w9TImY<xaWdD7fAD~S)5se!M9W4({9-vt41P<-&~?#lbaPlv3~CoAg9r}sly0=
z2#t}ir&vn=N|d9;LXs#d*I(Wa-U-sGj&eRP?(l7(!bdJ%|Kxl1J?qP1XOV<KTr^Eq
z`!DFzU6`_W<)Zdv?vKidTuC5ltsBzvcctBoi2?Fc01Y_wDUf2F#aXI>t!IfPfjPtp
zxL-(pn0xliyb?jV0qZe?kEZ}%jexej7#xKl@%s?~_-fwZB=`2p63$5+3gqyx2N<{S
zX<aCC+Y$V9x)In=PsdNQyxSLg!%#+qrNGZ)=pw4IP_xto?OCvO@djj2P|jdUW-V~=
zhm9iLhPK8^8q;LkBX;dU`Cz1Yf^dwbAuAO~3&R1*ShuwBfGNPOX(nNZ`8j6>1#EhK
zDX=H1E=i{B0sBS$Dh@+m!5E-}LU<MOXR{KnkHD&>G_Zdr->b)fO!L|P)Y6uaFx{gI
zkPX-ODtXm*_lI<sIf~RowsZfxf(Kr=5aXb?@vvU{N9>Fa%YI{saKWM?-1G7s0}&lw
zL^##}wW*e#yc71&L0U@&O<or|r}^!jAvUOe<E$xQ&S_e{+SfdBCr8YmpTs$4j~O?s
z8?0=+En+2(kc{{Jw0=SktBOeV`PBAIv2hfy3nv(kxCzS7Rlbi9ic*6kOBOF8CGK-Z
zQFuQ)LA#ok?nqgrRnjs;L4#`Z0DA5TCu;d`ybH<^d`0FCCd*Z|5-R|sE&+d~9JJuT
z@ZydUUl^Ug&T|hcM=NM_Q57|d{tm{(EG$eytti)EVcEE~x4mxyB&C1r3HtP_O;)c}
zP3*?^ksDMZ;}~mV<$;8Mnb%I3>sW=Y)u2PBo2vHVl=b<Gj#rD%E40RcU3F+!H=r=%
zWJ+O97tC^MJSc%xlWTg~ml(UEsX)=MPl!ka&+2lQrgL_lqK0&Nq@1VX@-yE*j)p>s
z_lJ?J7dmEpI!A+VFy~08>PzhtM<<B6R|)Mx5}9k8nhR!&in>fn<K$+u;v-nR-m>}y
z1eV90^$az7WNxeT=7+Am6ze!w--lN8l;8+wk}c9*A#Tw<m@U679}1>6S(_BW?QBX&
zP4)fz1b8w;zy1XFLBKuA4`m|;-3*LY&q1hv+Nus}LQdY5w8{X%{YIG%L_lSkHr2a%
zBfve9$yp*^^89w_d}7f?)0>$D&NYvU);%r+KeC(BJR<1qCiQ*=`_7=X7XPADJ+^Nf
zaNbe9As=_U?m1jhhdzSy-+v<#e_y<Tp+0Uj*b&6VR5vDqdpdm3Bdea@?aEKzA6H2S
zp&(t={k|o(eb_GulXTi&_&jvv#*Rp4&-J!4tW^mTc*d#rA@GwVVZR#NKyI*E<)(+;
zby&dBKoR$bc?ZKr6w>NvUCjv+ZTC{~2c*~rseJzGIFA@uuQ5^$=aq1~8;FZ;%1H{!
z;S{<6bbIV#n<pqC{+sPU%<Dtkw(Qwel+d_a#hId6$}OM$$H0eTgDNfj^I_ENjI%)t
zMguk-Fz^qNtY~f02C%dFolx=WCi_J#Ne(NC<JD!dTusqZx11b?BtDDzWx}{2`#j~r
ze$`++F3S2+CSE>;N2GJa<<62QLgbe9a0!`7Li-s!L~+K16J=o2CPAM7!CGV<Z|wpM
zk(*b|mXVUiQ?%qpC5`J{|CXG<njrbhM$t9-vFzMkPJvjSXz=&Ri<6Cv_4d+YF(XG>
zO1!z*4+p9D`mU%b0o)ZSrKfxq0$2Y)S8yZ^Dgi;_$Y2kvC+hiL%f25ha8JT8ty1^v
zY#sq&086j(Piw3%$Johx*?tRx=rC;*cci16jN6F>(;4s;eL?7f$o{E4gj|ok@#q)(
zZ`4w6XztR(U;3~LrTlLgI868Za)Sl&-5mSo)O`_s#CIZTEh;8nNQnqXgEuw|ujxWA
z7geKNj!j*(nedqIVCzr8!x#m|Yvj<YOkrWymOpC)|KV)p6`@H`8!L5&vN161rSP5S
zqSv&cXb;{V*a_j<&T~<7wFzT6k_zC}{gBS#H;)=+w$9rfT1@VHi-`UWgGZ;!31l`p
zCF4AX_afM##T`(%7W`N>h4(_qZ6-N?U$ag4u|;Zo2(8)T5Xg#Qe9Vc^xB^R_mrKe<
zZfHT>FgfweKU2kY!n7;pz1*acI>VJZA#m&3SOAR6BEX-quWEy-X4Ib1aYp_p$JNSe
za$0xD1#6g~AR^}Z?zzT~e)cbzV6Q5>k}`_q{__8)3k?TGah2;<Kgp33H^v0y=f9{A
z`)RXHq`24L9ErO@Q(@<G-(_5n2G;Y~84WPOp^Mu4txsLxA&v`7F=tTNPIurN@MFW4
z?Q79o6*ujnuCy%}M8NoD+Y8KMZM?K9tK&-ippqMHaAJ^;XjlT$2*+=1cr$TMKsR{{
zI~~;z%>3fWXhIq?J^SG&>PReg2#)5c7Rwrby=G&*{?9pKF;-tHw{s%1W|aRPFr#JJ
z=5*=MSm&@rGJkw_2I8_e_S{kmZ;DB}A&@*!EP?d3@p;{xN;Z#!r}h*}NI=*Hl?<WN
zkQeJax`ut_Q5<eQ7Y4=9*wfv3D}(_hU@E|1(RqzRKMtT|Oqj$GU)E61(ABUyC#1jk
zSt+S|UW!fU)=>mJ`1CRALr}p4@IL$#)eqkA!i;{p&TDh089c#u^~}B?bWCXDWa&`d
zHFB?z&fuVL&IRXo3B>{7Gka*OtDL#^|LBjZZ~j7$LoYm8j(jf=rPY|uJv6_qzgxu<
z1@y!`GkSLJe)@?O+Ads8e5Ly+lC|YH;yoa8^Hy?OuJL^2pa7RdJC>wSDj`*qh9!%e
z><v_=EpUZ$Y~)jMa4XVUCqC~k#cf<s*de7_jwD64A2%HB{_vuVYL_(1BxVfX#*cKg
z)f>PP(zpn|r~`aLqc#do1P37Ck7rwID)TJQn@1ELD16Pmu)u1OuY^rb?l}68zw7e#
z5GFfpYrvJdq1@nU8!V%9b5EBL(oDwbq$-&hkAl>op4z$#enXJpT}HJ^|BSC+WBQo3
zeXqGuMp(9gyJ^6$vp_eG1G(IN;CQw37r--gpyE(9(Zsb-`b)yFe4WXTr^D!yOci7S
zQdo4-G*-bw)lXQTSN^$X1f>C;c-s-D=QX-W(HdtTN{qe%`^raX>+$XtE{o;{+q97{
z1ju5zS+#|2<}PA7&+(oyamLCVthB7$fG&J(=<w-q6-v*ib8E-0W5-bNbObUOG5*Dz
zC!v)cP2P8eC_iD?Myk0iYGR|;xOUDHJ%hSz?Be1e>L?|#O$&|LgO;z=y?vN)z5^j!
zOjnBr0`B|##j{!1hQa?Fon;GEL<Yeyf<s~q!&xmDB0+5va5EMHQG{St+@7F!52Bfj
z{<1ZB=50)9=B`)1`PI5P(2fzUjptG)HV+i$C8Q_fPIs?AYPaO}d~pFp?Zozz^h@lN
zIr)xI6t$D=?{AgDumWB&41#^63mi)AXzd=e5!h;=SR}#5Ag;Oz1W&xT!#aX1*y>l*
zz+j(#o>}DaVZ|oGIF&{jHVx-rK_-7roU+D5(lUn21Igrh)G6SkuOet|_xqX>iXRT#
z*XB1s#OgZGj`MLJsB@0`C}!FLG8;bxQYaeEq}}7x1mHlU!F7sLLTE2OWbpp*z9FIt
z<do=K+5AJ-Ez%0sL!J)V*^Q5biOAf)8c}995L6ZpN9cf0!}j(Cchlvi5{9Y9S;$s_
z5?;e+!Gue(o^h&i)IKh+`2eCC@?S||tOz;b$E$7y67}lblahl?KYsFntTh4B8`&0I
z;l!?^DzsOl!TGiZfyt?R%k~3TDC@=4C~?Dj9X8l$uoumrK>rn~i^<LwpC}F*ozFHA
zp^OT)*XXZG!xATVzQlPJopWYCFMW(Or&a+!2$yW7+SdX=kV~?PWit|i_%V^t0)Pq5
z4E!Eg3D>Q=26j5wqX}27{Pp7fGHyqb)d6RgDWC$MelF5be`t%(6r*kWKeW6yZTQ*i
zivm_G*?xh)hK`Zent;Dfrn1W2LHi<Q)N7)e%A;9U6VCkj1UZl_FcNu$E^EBkruSqE
zKT5|O&1*Hn0qF=9_b$9=G5_T^9!co{IH)qPV`3-FY?j)UwU%ujbB76`mh^nL6z)_}
z#e5>MN65zsmgGk7K$nV691$g<Lhoj`g}-(W@N^q;LG!hz`H_qB#oq?+tTBYbQ$^*X
zaNVk7QbyyI&vD=*DLUZSXx)hd(K13>y^&*YkgDwM9c3<FbZp1W>WTJ~zfCZ*Q7Xxq
z&QQQeXQp^9w6=vxdCY=i7jr11_&B4A16^OA2s1$J<H*}Y>T)+R?*DW9*^KkS*ne8F
z4RcJSd)){h8(>!zp|vrb_VLi-$7$`p%-8GIVUp8swrG6`&}r3{T9tT&n#ziuu%r1*
z=vG#0H8Udh0e0_E&XgTNu&Eys^+i)%DjY%VV*7fp28SRU#0f-H=>o^&3MzmdjT)Ed
z#&CVoYlM-PzNMHEp~+RG?h}s`L5x#fYaC0-;#+hoOu2jL7re^T>l%(}TycaFrW0EF
zJjLj39P1?TkR+vB;KHyarxHbpf+e)CG^qq6U9}TQ<r)`%B|`uq62r9J%f>fc&>l8c
z`y|OTiYnuGYzMav41D`6xI_c0T=4zI3#}5WDnHSSdN8V22VyQu{94EB47p!sud{yM
z6wA=S<sJQw$ltQ#i`Z^7Xxw_{^O3bqU1hk5h;R(^RsaX60DBzQ9tiov0XI|4Uk|)I
zuz|<-#+6S~cL3<ehUOd<CC)5qQSb-qMG1Cz5ie3F_6fj!l!&5q{*z<dJkeXKF@wA0
zg|+%R-7<r!8aZ)MH)Mh7loCEhmNp_Q!II8zJ^G5i<d8vneeT$D^@##w{biToGiBb-
zniP6B0S6dDF2C^~xWYzdgo2EFa&=S&_q&!MyrM9<ZsCi>V=$>C6{Zv0W_0_GaG~p>
zr7Hqar--!&p!a3{wO2gp9%I4~kzRJgRBT0A*}tw~Ib5-BA|pJUMQUw!u4eg#8fa6i
zcN^bPh2XxCE%&yEIlWNlO(tso8QtA@s+X*#p4^g#dv8N$%~{qz>>%jRMOn&dV`V`O
zjH%|f>JM+3|8=je6IK>>GpVv#?w;m*>ab?6aDo1R<3M~9(d5@uDfU+~c^=Bf)JeE&
z_`!_XQM`7sN)>;fq3<%NYfUY@U6r0~`r?)Jn7lGsmh%0$SDSfXa0JPB!n9XlV5rUZ
z>cqRn^W=e;eQ*(O3Mr`*k--RhDc-``Py5c6t*%J@9b&*BCCNIt7vKc_WzmyH0{EXZ
zRych@erT5I&D=fPtXcn{wC#upF7G%v);rC#f-d2$4Enp4%jY2pDr3mcL_jz*NJvE3
z9_r+(JOhK(-D=NFG}_wA$f@7Ep`emq8dXJ>II%F<TZt`M?Gtnz?)GpS6ORB#f5czV
z#6bV(Ebi$8(4KkBSMsR7o<#>+b3vXWnw_B%B69`@!j}h`vT|}mqMSaC3JrB`2ZY?I
z2Vwld@s4_xo@er-S^Mmp4)@_Cy`_wh)1Hy>l!*Qg39-QdX8o)_2g#p8PH<Rv>MtHw
zO4RaA_x@iBP(S2QyIP-{uTxZ2<_>10o!GsFx776RA(DG$1q&(VZG7%1vA6=U2V_A4
z3^R1duS&irUQM#8htY(E;Mlg9=Mm`I_?QCa7_2rVyrs%Ga_V1;6s6=2Gw!rr(OZ<~
z3SgOJeV>q~1?_TM<2&J=vLs9s9^Hplh^~(3-tVqHVqu!4qq9;IWL!;djF3;62i<ds
z_fch@Dnd%r5Q(4$0Q#?tvPk#9U)=^QUF1xW?gJB_BGo}Z*A~B(Vvi_>9G5iZwxN2|
zy?I?kTCW_oEAHFoKi5%D9!W?lKy~d#^mZzGtx~xGq-)|6N?l!AU(>7Gnz0CH%A;10
zE;sdtMcbDJuA*)m3&!J73R7K<1fY4rb_cE^+nPL<N5M}E1@Nzi@?SN??Sq(8iT$<G
z&cY4ni{o{hm?bCWUtlV9IOc#9;DH^u<=3d05K!|`@k?DfCBfv(oNoUPcB|}O;b#Gw
z0x$(Jqc~VwoqdhSUvQ?>_^MNe!w?kos%jP&>6w`k*D7P0^TtTuVt?J^lXXGA6NBEf
z-W^s2Na-@Ow4KAoa-svz+L)Vy^^9j=GG62l0jI(0LqD>TwcWViKqH&-vxOs#3?D({
z)VP3+&FS?QXS&Pqe`*g8-VO+WGiPC19b>Zo(VLuNf)xg$zJ;36a#N6}J#F=JoYI;o
z4GR7fGvb-%SGy)QkkvE3?n-^tImg{-RaGm7+9++ahf6mjdUnD8D&H&3!P^6*6|xW#
zMx<~Y^ChOFj2e6b4-L^!{-hAA`?sJTa`yU)uZ*pbu~q!_%E(v@kVc3peB|z#ZdQl=
z_7-g`Z0IBEV{%67pE)bu7wfWe!GS|eSH0*`9Qk$~776or18x7_`e2PHJ#WGE!C)_U
zdYDP0yPYqC2#?V}#FGuv=@?_Wh6ZhHNypV3jbdhE+YZnr*V;^;e*nZ%E$}J2+2To^
z>NC;J4x>?4#A`WYi`sggZCGFV+*$pO9Dh!zt*Ri<>k=#c&pB&=>A5ciGg4uc+ulPP
z*2WV++ecV9KcpKK2O*w#ks7$1V6H!3FJrY(EJS>y<P<>U{C-ew^PRd0TfD!&4}lA2
zmMm}j;Qj^qO_bONr0>|!4ru;xf1+rK+FAD`gpRIKN8c8c3_QXYfUp$~%DB+}q^wYK
z?ET9y7t1#koC8+5KS^M9(m%%b|B=W_sH+;?%5f|ID3$_aZ1Rb-&~fZ4X_zC!`$#cE
z=5a(m<|z$5^$(Fn0ybx{3Ds&7wK2?4Xc<(M*c3c~D}PR!QVi4<#B--+tEXN2hk&rD
zt~B4@A)sQOewB3>^Xo@J;|E0PW&DOQy11r{zfK#wfkDMx1@peazK$c;;W?V$R%Hr9
z)k<(zmu}m-v&dnN9Sy_qcioxU5G+nd;d+B#%I&^+LIDvdmNh*_-wis0@(|`zTdRu3
z>aYW}HiHTGCUAnEL|+bT-iEIpXiOe>^IkG=uchL$OXxY<r0Q1@dPrqE1Cqmo_Bs$j
J6sBfHvC;PK<@x{s

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..a0f410d776861457b81aa58e1bf2f963410881c5
GIT binary patch
literal 1616
zcmV-W2Cw;x6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSHti^eqrA1vw$!f3}E-M;|>
z+hok8v_xrP$FQrJy<VCIS@@&ZPtkZO=2&+h%btJqIem>HqdH#Wy>J($9n+az5+T3G
zBOOdTgrrvzaZO=$fzj&3e{s%ha(v^NgH&|{>69tyL7n{l6Zh-nwkmPd*9SGr|NSl}
zMuU*rNtFti@wc};RbGza>=f`NMu~_F0%LZ4>jmuQ;zfltOuwGuhDYPUu|@B=dD7CP
z{>n?wzUVXS!~^F#9A=|IhNgKppcCp>*sMGPY~ORRD%_BEZ|S}sW1XCz#}(+bm?k)j
zSLNoWKRH>mAL_t7N_`4#`_HlOs?-5~t;?!C*Tk<h=<OI$!e;>15rA|6-FZMTNp}i?
zPjv(@a$7X6rM1WDIMfAzaSjEAU|4&orf5HEvGkksC=(L^Lb=1l%-><)t%tqHcT%x~
z`02W=5baUnI;yS&Dw=lpBh|r(CsR^^ssLr|aU=94(g5Oi$O?6BQQYO@!;@|>c$~98
zXksytz>esaxce?l;)Lh#krB~v=K38+xB~OFEWo5wg$*JQKDV;i`xDhQ%4mF75)?P6
z^AhZvg=l=&fTKyF-K}G{+gQ!D+#P7+F16MF`@G5VwdQzz%O!bBd@cqXcib>w9Qq*Z
zgCEk>u-cGCd`CMQ5ueCR=MOu}!hVVCq)_6JB`iimJ4D5aQR`)EHDWblQYVeQmAm~G
z{ZWW*4x(q|g{x@ygf3AYUhD7EPSus6#|ygT^T#ay5g=w`6*`geh;#Q|hnqjFH()hC
zap{zh4*iu|rO_+MbtDm;C?vJm&CA8&X+?f9lHQs%8dP3QKB@;4TFszKG9?<%m$_td
z=OufG$g0SW5SsH>!+aMj97gtzt|dhR5~6%c+Aq}M!}V}&9W!X@`dMl~|8vBBSoAsF
zz=yU53<CVR@`6&W#tp3K5`0^=^ic=_KlpA-k-oYsLGJK0v^rhyMrD!8Cw2LqJTJ<!
zva76DMsj20fc-NW`8)b-n?gY)0<M5sS{5f@Swv9!J1FDY;&<sd+ss}y5Tg%NExRlW
zU=|@jEmcZFB18kc8IsI2ATS?(BB`vA^?=a-V9*VUSQ&-yhUsX;#gU)P--*Enbt&`J
zLhtfq>#4>8_k+^2;!WQBTz&CxuIHFug`cDbxyM+>=zR8ctx^~wdMSyL37EK5x5APj
zsE1W8?eL(V!uEDPQ$G4(oQkp3UatAyf~KGvpL-+x_3HwArTzdnya1HFC(=>=Ixvw*
zr>!XTm#w!!Yx#gGwD1px&V1{VI&veBI?-n4vcM${x2`pz`LEOyLzIN|G#l)05v#}Y
zda&$4%cs}40&s}$<Krsg;&FQv_P>r)&gpk-mf_Sv>E-(i3ro}eu;stloi-0SH1hQ%
z4nz1z6^TB^(@5FNdg<r6wg52OSBt4S&vbFNO5yZJ)-)sKcGiBy4H`TKY%6oNi-lJ6
zHmVzKH924kr%!u{g#+|z1JP%r;f_KQNtdgoaL-0feQvxP8_}fgd<agT_dJO4u7Iw7
zg7uUzj!kBykLty5{w>+A{bTR5HRY=J$`fs7?^{)I#2~*)P(?dL;Q8w#)VDHEkIAmZ
zM@waq0u_UfjB$Uo${;L0>1}?Q#ZSV^pp$f$nCP7?l)u0(*;%j37zl5AXY|(WnP=aC
z^pj|xHK#0)r_aq2rd8CSSMz2DG#89FwcyMk!-{z8R(&z>s`>bn3$`%HRV!=GoE)5w
zgho0esk8n*(NHj_x%?wHb6@jVjbtw19OL205FD+IA{koH=}tkZ7-%7&Z0@J9x{*(e
zMrRH>1f~*ms$OXHeZWwDgl6$ru2}ekux^eM;lo7~Z`#8ys>@s%lywOA2<rPKQvlg9
OyTA~L_s4f`N-s8xIW_74

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v
new file mode 100644
index 0000000000000000000000000000000000000000..1bf9f59d51056ec28f5d948c7830169c0935bff5
GIT binary patch
literal 49032
zcmV(vK<dAX6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+lp=)9_
zPHYudbdYZoH=J09U|<19#}ca#>I926eW-7+l%_#-^zCw-Yf<eYO~<?c3|;Ll8P%ha
zm_TkZ(VaQJISvwC!NOnXuin1Vy2R&O%m#lP{t5VZ{~z;YAB_HMUI7Sx0JYx|D931S
zOrkr<0+wLwLsjEw;VI)IlRArN!p-%}c?0^^$cnh<Bb(=y2F~F|dX^g9nO2fA5Uy6A
z5L>7dJhH80zaePJeud0~hmnoFOt**n<?ZawkC*WJ<6~qZ8zagbBt1ksn<D8Jtr%@(
zxO%kQ)%_5uK#Qf08{ez!$AH@ShIc1=c6p|CoIAGa3|F%n<EqPA2=SSj3~>-eR|N}X
zR3fCm2Bu_gj2CO1q>R^X8Np31GAtRt1#JYxmArFs@7WIQ6W^W7k~bjxJ}+8u@cXY_
zp2mmEG~|k+Eii|&F5n=y8v?7z&0V=|!aW+?7N~N+ZHd*p);`9c&wR<DTU%h6Yh<I^
zxlC++F{Ce-JdfX^6M>Su2Wjhn$4wbnSIR(|xFU<BLmos3V%E<z;*B=8Gx!e`9QA2G
zghSP{AT{5-)tY$~>&9ECRh|-Dq!aFxig3g;Cz-F%=t6|V;Myp`pZ&msJJ?-~FL^Yj
zUUi)1VRXTI-S>b!z3C`OhBH6MHVICVh8#~_@S0iWv{R8gsW+g`u!oi%7!?NB)s6>D
zu;T-cRv8a5GR*`T(SXp95oRro(FPtO_dG-`uLrqN2^TCWwm2o902#t{6LhGq9+2at
zCzC@Uz{BB!3e+?$HW>bv-2*!3)p@(7UX#1ugvnUq-hEN@)t(&$yf22j#Y1MC;YVj@
za&>Br&b0lZ17Q>qUosPzPMVgax`=no*u8l0a)V@sUE3pjk6Ej*Y)$7(up1~;HXW1}
z-RO^J3}?BO$9_e{x+W^pMMJN$Xk3REUc4*S{!tf|W1a54UQX+%pp=0Ci&s3a$O&21
z_DDmJqbpNvyyYb9!^!&J*QN~?B}~QGh6j=!3JT0+RLN}Y^m*|6)g&=7TR9ZS`{^L9
zyY(ak^^?i+ByXA(*KWnM)E=B}>kcZ@DXA%f2pL<C=fa}t8USn#DrrI*VEpfZ<%);Z
z4IH$fr`@k`lhK$Ktylbt>HX|OJKw{p&Dfv2C&ci^&>6gvJs0WImN<`7Zt#D=IgO9x
z>7<3+@16Bjqg^5U@CH#hytF!n7BrSA+c0my=eCyq>vFOmNsI!Iy!uPrihA|>33HA4
zU2@CP8XNF7T}!u)>XP<1Ftn9$s^RmE!x>!>Z5A#i^rD9};jnHNx(9zcynO+wabP1^
z)fkoO&^h(5J-WOesRrg<sZa=F&x~!7fI)nRFur@|7q9hz<|#rsO`A-##3bzf@(8`Y
zxcbAr2Xh%rLksuo7gt4)3FbVDnc`C-ZBtuo7G%*eI~O}}V`d_7t<_MPxqm!q5BD>W
zyt;NPE30liK$2zfr#^^05F1&kTA>)sKGFJQIx(7>2)OB3>}o7?b`Kw5AcXmBS@o>0
z0OL64C#26g^6*#S4(0b?*l|y<<B;yur9sSnY)ANZHvti-;5`7JeHbKpz&Y-qGcMH`
zq#~#mr4qkqT#X@2v%8!ziF{cdr7Z7XBA<2$1Lib4S}9KSLm1+>85Sl9o_2QY#+j8_
zTiOGz^vL5;Er=F~X~YJX*76-7_xLREC%~Pb2}}DQY<e?yvLtMOn7YZM19IU5Etn%a
zf%@HGRXyQNYj<d6%|Dzd(G+(k(-urCQ(Xfl>qXAEjZ$%M9ywZ2PJ1_(N&R>D+@C8k
zO&MZsSGJgdA{@Czdu>jug0obd3d1YPXqH<{*kHsjZG>C%)e;X$j<ZNyOp*WB^-Bd!
z)};pKz**xuIo?J6(>}K?Y9nOymM8Q+<$U5K>I*#*j~Se%-`RM$-${sNLnJ+h-B&54
zO|#nXukK9qmpT25Dm=|rd^Y}&O>=F?Y)#p5V1c9$tlVXhi$dc^_XtE-O2^k^?WMKZ
z>gcMi3h2}d#}ss^x~)mK9lovx8X@{VW9K%LNkP=Cc4e#f2wI7;0;I(Vh?Z$m*nlMq
zCJqxv`RGA02~^i|jCxTT$o$M3fl%hk#L?)a>R)S>S;OEl-MA6&+iIt4H;k)zH9|Fi
zRvY3J&ISp6P>zvRbc5z=f^3@%?h&j0xO&i0`U!;NIG=1`tN{S1lr~;*2g>&l_x;~#
z50jgP+wQ0!Okdg-(kK*w!}SPd)`@{>x@1xy4b@aI4QDEM4p&eBo99eZzWM%8+!JxZ
z*2&^{a@_74S^+0O<?Vlg>`l^+C_Bj9VM#0Fl##(eSVLwjS=3`&V`|c>DsS}wr}B9X
zFO7&9Wl~woLC7jpNy$)m&aB1yFT~5GSy;+=m$hx=8s?NteA6TX4x*DW5adr?-1gj`
z@`l*?i^@^4i(rTKw2YlhI!OeQF9<xkT)x^ja{U&vQ7g+n1tNb@V{0>iT>r@ATg-KQ
zf@rM~AHt-U$xXQ0Q6w|2i(5@R{`-(<9tyr?1}Z&QsG`>JpV_|(pBFg(E06RUeMM-a
zG~2QTsHrBb+q?qDft}K6I<~S40*k0lr<nbaMYtxa!&QG8&KXsOf(afqu=nUOClcY`
zTdbhXr0<`}4f2ZMm1k+j@*Q;e<_^yunna~ID_cyHPYN4D4mkU0x}WVt3?O{*x(#SG
zhb!6Gh*#lf@o$z{@F%FFa|)L*4VedQXS_xy5!HbV6U9Ago28CXZj(s3lTXqjO{q%>
zC^t&9{QR!}yf<ioEmle81GLz3Pn^EiRDu;>byfBEAMAOcBYK+v0Sw3WXK*>LnG@3p
zZ2_*E6!d!>aX66P73bi6h;JO%6w3KVC6k|x=L9<>LBVd+#H5k7(3J(gz*_P}^~R5>
z<#U50femZd;5<Ni7H?qoC>Xzw<q19yxo)$&Ov31ZiG=Z*`8WOuCyjpKmQSGoVct45
zuCAP^b7P@c*%se7XM61MT&=osO%Q)!-=!d$*Oj(r1SsVAqRjs`B=fwUZ><#>Ei2-V
z4!2)9B70S(7zgGwfW_?R6p72Y1UMA{B{y>hFNC7G?W+oubkb)7-oN$CuxiPjvgkB;
z;SxIQ_->NdO-wBqEC{mprw4xz0~H>B&jOwU;r}y+6vx=Won&#f#)i68Fy8s4-wWa0
z@Q*;XI`vKX>$&vpCDsQ0@uxfLjC?xh>{_CY7j;wj_d|k#15>STo0c!yCSg7q$-fY3
z9YLF0$4zWv|F4}Bqo%3!ic+f1gAxCCbn~~0>uYI$@tX#tllMt#`Uogjm7J5o4uv)f
z04=$lWSYtbU)4~FoowJ@%wBD~wO^>Pd#}&s1da2meSr0K{o8?w1p{nL#oT%zNaPWz
z&)x2$20$tBk(kb#Z}2aR+y?MHQQy-!1SMi4CU3JNBFk;ldl3Y{;v(RNJyTg##G1_!
z#I?-KT(^dO>j=KoUo|0EzTvPy|MALoa&S&@f>or?DUUiJK`hP%2+r*Ab!ciIWNWMA
zDu4YGDgkDH2fEOsE>gyMqX3oY|1UYes)#~J%Uet`BvfDN4Tj>7YbDUo>Ei@xOlnqM
zVC_5I0n3a{C)(e9a!dl(N%}P`e9j)RN>v6gp7&T9H_4HV(Iuc6!=Q=P3UVJF^;hA|
zRMWbm4^+7U6ni>47hZ_2tivdLp|Qdj`fr~AvLcZ>K*8%s)xOpyD1d)az=Nd4OXZ?}
z7l&7Ppvgj47jQao3s~yoi?w!6kZI8%_g@X5=3n>4EbsY)5*iD@4azyaC9hFUxZYdz
z!rJwgz53}ub)_jr9PT}~2}x*~o_uGb9=uZO>J-ID21nS)!?tM8HAue0FH0DLf<6at
z-i?Tjsgh|34YwFwWRbLW1*d!Ro-bvb>VtaRd~(h%enQl7WZ^gDuYmM52|EO@#AT0`
zQOnwOdWcl!?b!u)o)`>T&ujPc>)f&Rr|G_sL6DkgY^=B_FpXqzt}V#%SLuL=2z0@P
zuZ^>sY}yn+(q)r?T$Eb2I!(p;{u6Ip%!zK*Q}Ib5qX>B(g`U{$;WKu)ix4p+wF})b
z*$~E5@DXRYq#9BEz2Sh#LYBo{fXp^%qr4PT*7`L2oWAFvt5^)k1pTtO!FVjyVn&o5
z2%3U!trvLSPlRiikc2M}hd1m6?Zc@_H-<HRHSvAyN5xByJsLAw%+#I+8=0wM)9pXa
zR{jRobC<f%*;T*t`{neJM&HADPV|0@2JD$YMT8?lOu5oC&XoB-@0$8I0w%De=Y>;O
zn60;aBFR*Al}VG3U(;R=z?l~g4I5d3`4;sPbG$X~KM=XkRf6hD930f%fduBiBXYMW
zkZ0nnE%%0&>+kjLUv<MX%>)^+@iR%&cDw)FpMic9D7g7zDJws{9Tu305?b`7m#3rB
zjJpS-BC7e8&^Hfx#f8y}f+gJxT3a4`m7>yCM+*59wR2B%HQU6bR{dqicu;vvpP+VD
zaBvyn)})49z0P^)&;&3*IjlV`R3k7lniCgGvvLJpg@?cFj?td~Z8W7pFn8$5{eNW;
zJGfMxjaJ2$z<_%YwKjX2EwTGaYt>9xnKvx*x}=W}^5><<Mq79bAEHvhk#^41gF@@;
zuQ(t``D2~orP28&mf~m5+mQ@oUh+3&1<U2&qxlY?`^O=#fFM^1038iH`wq*Aekqpa
z!W1;lnyb0-dke>mS7cuR67Xbar_&=C-{VdZcn#U5Yy)rMIAlByh^po=7ru!#bC&>|
ztEI|PTn#bCsk8hIoU|}S=)I(NV5kvEbShumEjC1d6PED)wZZApB+sp4uy<_p9(jP?
zKT}344mv)TMCus<0ye~DCidTw#_oTl_jLChH)Bb(KvE>#+~ybH8CSU~N$mY_%XT?8
z%@@D>Jbh~-_zF6JZFo=9(ZkBJ@4DostZcVm_rFR{m80}pZ1~SR+5&(pWohM1w$q3d
zmW7F&GjdYchhACshZmpe4_Y}TcvA6zcn_*rm5rG`x+%h4IsGB!<Xi~)+;1kO*Mrb|
z=}Jo8@&(lCKo&L2DS5vht69qI)igkLmX6?<NNHGZDtj7>m*d8va!2d*#opxA>!Seb
zRs8$5veD9Xjx~$?FlPWfFY{{jBZ@c`4&99DGi`@p7IT)82Nd5{O<rrkS^-dNWG=bg
zpSIv*-^Ai<wB|0rFna#>$qi=Fg=~kKqtb?+3LVL%<M{Gj=gP|sgaTPJnb*^Pg|N|=
z_F|8{a)dS%W$7vAPh3l}bxh1lLfL8Y09=7j9W@2z{_%h_oiT`$bAR!VX+u$#;<M>^
zp4H!!<-k-`oUXQ(G~BUPafDB#^zpn497Y!oMWylx7|Qb4SGdbGWF^1gbgB$QAWA2W
zSYgvzEA?6==4#cvExN;^C71#8$i{$4?L{MG#X_AVm$7M=^fdgyDY|%6PjQBH%O9!@
zPV~4t{(G5u7%t!PCH{fcC|1w2>@c=JV&GBm(rCYkEIhJKo_D{)L%4r-$0D;o#t=wt
ztC-4nEtTHJ@T$8js1;HOThccK+2vyuI2I>W%#$$%mag*iQQ5%GoVau_%dgGsVQKp@
z+aD20)&|hmT!giYt)<x~e$>+lM4_Pl4*6;{O(14j@&T@{ytFYRmaaD<!}<x)C5x$w
zKpqa%W3E^4SvPtM{q953lRa`dF}pK3?Y{C23FhTObqu(;SHq&(-&iDh_}=P%J9XyO
zEMhFk8R9w3TY;I$lxG?1{xIp_O8$8#mdl(ZO@-jD=Zk_bWtRr)qzBt@D1f4$=!rKI
z;f#NFTF?vHl-$?Cf--9d)Gf=`0}l+jq`!ZirMuXhxzOPrhjlU4i>`+A;w1y%Rn5c`
z_xi^;IS-z>xY_Y_?{DVPvSVqEw>e@n*ofHh_yMBYXbYDhOw+1d?(3|bahM42dpkJ>
zw(2dgs++(!goi7rw$_%2NV7H1ZNdhuDx7e7ic3_X;hqpm=j>P5Ha{K|nfGqV#JgI^
z7C%exbA12>2?tgPrd@MSuL{cDi#fb(@Q7JYyzWf4)zlN|!#z9U3g!@4nUV?`=SkpB
z&~NS`)W7QFT3!z81p@raZ05MVO-C5~DToeBm|x1Hl~knaZ>xR$I#o`l;h#PAF?9qx
z3I495|8YiBCH_6@P<=8tyDVDnQa-D&RQ640Fq`umb_>ymtR8500t^0S>jb9dEl4%)
zK77iw9DY=8V3tT=<hfGnJtHKbe-#2R@4(!Hg$G3y`TG{Ux>C`!yiXCRj^Q1Z)OZN8
z!1c+=3bV2>&v1DN(5aAi44xZNh(CnyI-K|&Vq{YT(;^Ss_nKK)8S)*Fm2M7EeZd$F
zN0@i4p=Aj}R(#J)_4dm2rMcv=F3v4#<GIQ)J1;~TrzPs(kYZ6uwhet<9#pcdD=T<o
z0g&a(!pRk@eEMUb+W0*3<)RyfagjfGrfaW>nv%O@TaYS6gtWW|G6-<K#navvjQ|u{
z+pn_J5Q5qwy1Y8LuZ4BS2I+fxy4jdrP;&5B`A2h_XXbdp18%D?)nr@cFoeuCWjk3W
zj#o#OjRI0sE&&@hB$8T6hKx&3PYG2?iL{k(H3wg=Krfg}99yQW)T))y6Ou1D9<Enz
zj`!pv*enoCV}6;2ZZalb%undWv)I58PM6{WEQfD7edxO`o+a2SQN$uR!0X{CbkXWg
z<ZtDhA1Kt9$G~f=i5_Q4^`wK&rLSWxXPxA4i)fHGzDT}`PZ%ofu9v%5(*PdB1JNng
zi*I7m8tcxG&{&{by{tv={O<aK{nas}ZHn1=-EL08+6@2@{hZmGZ}tkQ`kISNW3NPl
zEu#hwR0xORP3==d;~vwH$YpiGSo1W`6*2l-j{J%{UK`M6Eso)ic1dD0IzIK3hMoA4
zp=~Tw7Q~7%zBRA}K+Wft!-?>*4I;ODnR3hIS6h*H!81q+wWPJ{cLoYmTSfnuFkxwT
z|282{qB=&l{9zB!Ucg3I9d#5c?D?l(!OR7xLHhX}uEl;a62ND_bkI@`W;le=o6sxA
zpVLk}pak}E3i^_di33T!n`;zpz;yg+6iaq8zHH6+F0d6wkgwgNrFi9A$egpwn?-Gh
zX<)=tz>}?;>IQUx_N0z=kM3E2e<=x2ARH_wkLr*9I~n!yMXl-{fWWaSE+&V{CgNT|
zZYS(|aQ3cBDF*jLUw*zJkqZNf&DUe4STe5iVLlH<%FJ^hx?<x#j%y(|iKsg-E57oY
zo`-#$W@O$~uUguSZZ!P82CFhxH|LY8IUoSKAR<iX6zc3DF_^h$!bbS`FB-+|#?I!?
zQfF+ViU~SgY2oMkV25tJ<8t%gJ8x{ciuyfx{s*AP#y<fMP?W7rpnggo4t*=ApEbF5
zfebpREA&iN?0%0L$W!F9QMeM2=Lj6tlE6aLNxifK)DASvMogikES1Ez<|1QmZTkmH
z)XJlg#^D}mMs8Qa1Oq*RGW7udT14*7yAFgxXjBCZNv?xpGQY^X;j4{g6p25ynyy;q
z=90tO9j4t3I67{=VAy|+5r2DdDz&XQOb70d6h2p}t}D0)7ZyROO*!G;*TT8*=jqD7
zA``-gNYdr6n`#^*?><r8fyho7x|m5RPK!=lCt6Qktz2e!yRPkQHP?<)9<mA_DDi+(
z3;+4i)mso}lF34FW5JVT_B^<Pm-E*8&-y|$sK2tItAKN<&mRqn;j<Bv#wz2&>o37g
zSy}9<VDX!=hg#Cuv8ITZrz@Kbk@DD66`6tA_1OXFsm=ZxcVgc10(IU+u5R894*bq*
z-~HX2*>#COd;)Z$i0PNV2ISWZ6$aY%v%>JfGt-7-w^U*AY-9^EzYCai-?+N$hkqwn
ztGltEw#~S3yA-iCm;bE?Fc0Z-_CLTSGca*2TYr#zI8Am`#z;lc8gg(ugBp4J@1M1{
z$$QH#4sl$1gcdyt2zf3b)mtN&pu2`Q5b$E4e&fq%x%>Vcjl99z@7?KR68M1Y>Gz!g
z&#3kDlyajQe{MP%S;sI66+rsc?e2MDe^cE5z7icUg(K>dP<rY-kuamCx2U!typgl}
zK8#6ZPa{hvZF$Gmr68IPz@*&+EBf`qM@%UD77a`~_Z><cMBrsMe`88rv8#6ZEls`Z
z^KW38OuyTJoo0aOgtHu5-0dB?1_PFubw5j3<zybnwxSvhnJ{1i2l9yd{i*KGDhmgu
z2nwk~-)#+m0keWjozffVB0+v^nwNPQg^@{YepGfp3V53c?#j&<FuN#jjYl$#M2n!x
zvN`rxG;ck`qTCx+Ciu?zPz8;BLIxY|gO;VD0EaZ%Uxlz|<0<S+H~<bSzXq&PFjm8$
zZmEfFYxJ{6u1TZxQm!QI=)a~f`zfDvxKP(bKd+j1`Ul5aBgPhhT*zPKGu?VO5r7w?
z4HjI1R$5&PzagvtwAI93X?|aAuZIk2gW;t>O)Ct?UF%=jXd_9-!+-V>`&9_g2G1V6
zWRG4iDBR_ln7+}e%iBD(r0@L=I37p8+Fv|=C1*n_4N3cY*h6K4WjY_L#l?WJ)Gv>K
z=&uQMwp*BTExS{ZcKEPiR_WkqWl%H^K2)z$q`Nkrj4bz;vfw=J$=rN68EA0yG4J0s
zb`Mb#1@D{jMJ1E&Ko7Iv-jGA~Ifl3)duQ$nFkx)PGOWy7BtrcUY?_W-Zy4ckk|j&C
z2FR|mow9kn`+f??Oo0$*y+>#&QHJ2>LYQm9qf)tKZ^D0**^245m;1ZJdTZous)-f;
zQsGIHH`Zi}bgUGF0h@t(UIc9(vQlB*D#b(7V@bl1+RV{PTzBfIKZ+tdkyth!6~YXS
z(PxU))^$-wA#MB6!+8l-)xWT^(d6i8gkrD*8ko}(1Dom+AwfvB@QqB~g37;_miDi;
zH9S>MP9Q@c>kgu9@g_$boVYD6v9W;!F;HON13@VJL)$^3>O`f>74>kU@2~d+FYL;`
zSZYmb2{A}f>l%}NbgetXg^=#d&HhXwyS(}*%&tvqm&K8B-iX0q5^FCT#nm5f{x5pn
z*vjf=6X4(oWf^$2H^l%ApK`0&sIsSacdTimB*g-_qd(``T~!4o4V(aQ#}JL#hY7nL
zxS5H(?gl*Fu-ps@SVbnG=uZLraYXHyglPoVbbajijr*eiskU5yAg!rdg)2EOYgNn1
z-ytv0Whr_9>@f?&5x*l_VmV4ymYYmo6}uQ`3#X0osM=1rh1hZ$8i(nGRppwnYQs;r
zB`+v9ikl8Z*Pa}!FJE^)d_)(z*Du<Ws4l$!zBZ6cTsmQD_m+*`yr2e!DXsJ35{a<K
zAocz*^z;;rvio^0`__ekjpS#>j*?mo&|2Yol;{-GCLD75w*OKK6^>l-Yu*L>r{y5n
z`NZijh7+q-g%%ZtNAy-$s6`KjRh+&+bjX{r21T$GLFQAzB*__vN9gr#N^o5Qe&;pf
z)D+}7;K6f5<N7k}6HZ^oPXu;qMAIjhINQf?06ue8br4Wp6id7$0VaeJ$1VRyD8%*8
z7B6Q#D7;}IU{MM&D&h)!PJzK{*gHbV$(~*q2<(jjuz9YcIzVa)x60{1iGxlyP)2ux
zLajf*U(ts}-d$&ZbBm^tlp#eZte93sHs{^uMUdfA<d48sg}fiYjv;;BIN?pZU7*=R
zy!1qj%oBm%>ml3nxy=}%EHUSLT}w+!3LUJShH*>e#gwxPKWj6L7@BigYr2tr0oW)!
zcKkb=m0Z(Dlm$_C^z;=)lKG4mUh3tMAsLAc(vrN1uwglQJuZe$J_M#M=8FktAVf2>
zavf+l@kF|m+ROg`rx~GrGl7cPuVZs};Bz2L{u3DT0?GTJ$EDSVa3B9)pJe_F28O-`
zX?G*tiA_}rLO||SP-{7^yzK>^?OU=z>TKZMRlUQ6xx#Q|(|TTE?T)#$ZXgFOXpiQZ
zlh$q9M$PWCpPo(eWR34X1+Yn@f06KabBKr~U4hk&0XnugS%E2zh0wNrcXv@~T8`k-
zfbV`e!Vq!_5vGoJJjfG81kZHdICZ6aoU`UWd@XFxEQyhY{`OPw1fs+fxn5}zKw=T2
zz(~?qG$9N|MAVhMU1^Ul_B>!`U^lBE(!OPV`B52i(NE#r_cb$_6LGSG1fTXIKLTUu
z7QDSi=CP@Tw-)5^0S#ovIiEtK8Ss9mYp6TV1w~wd(uLcrxB!NNN6;?en{b#Z^e?Jt
zY`-rQW!AIcHUwYs|8=-!0pzR@rqKUh->5ZO%VC5aT{z|3Lo*2{P-o^+kcs&Rq##ic
zp<JbL7J<6_tK0edR>eZ?u|)UbRossOmDmP3Q1WmFjp{BY(*C3;SeG61iTXhBn=ie7
zusyv$fK4>RVLBd9&+8F$=E1rA?u|73eHM)mmN(3K9dBCfzERdT*W_7U<1Zy~BK@Ob
zzY1L<1IoF8gKjTN4b;u4pUIo>d0fE)AWw9oy~;(NF7lyXJB6#xG7wN2&m2nK;k`K9
zg34yJ2jtB*7C*t6LiGU*$fz3rPcwt7s6}{&vp_jN`r$}Xe7GzvdDAd!b&E{qJ{tI7
z&3dQlWWt|E1cnZ){8X2`LD)hMh8wxuE5fe<A$6JQ;Zgty_mg;bqH$CF3?q3E_bnUm
zNOF=s%oi_vEK@|zYe&idKzKA_kwdkH8eskBsD-j?3Vzx<;(7mY3C<sp7#4pe7n7{a
zK6yIE^ZCw``C1bBSQ~<|+y~EDw{K77FH(jYMLppvY>Q4Ge|`AUpsPs%m7zfBAV8YS
zde^m60<vc!Frn<KP=hxtPwvmU{{WLC&9S-@v7O+?Xz7YBUO>&Srb%?J;Q$o2d^yw+
zWa9?%6SravCVCuCUIOAp1_so{U6?8^5!%)>ea&Pfi^;+QbWni7CFkd1LRWUcTyrir
z7!qaTZX!?j(cf+*wY$`?p90%q5d!3tz8~1^j?GW~!X96^fUZj8Djw5@lw1YNkNvpi
zGx7rxI@p4I=VmDvz~2i7A$%J{4GR6e`z<SMXSN8H$y+si@2JQ9E#;Upz#!-Qi{Peh
zzG&wZMTJa_r}cI4(5$>}Ux>M@hf3H#uwqCB4tx6xqEIR%@U-He!mxi)WH+dX$@65%
zBTrcQob)_K(udG8-u}MHV;*E>{kKveOgux&L!X2!mJX%rRM&RU=WjZX7Co`zN=7xq
zFq(467KyxP<32@;*QO2HJ~2nFu*;&+d7DTdLbW6c2vDxbvOh3DD1qPffe>MqA)k`L
zn!rG?%yDywYnKKZ?y_rm+I7Att(A@F^g0KvzK*YAaOo>Z6*h#>mA5)58j#hSW*%aT
zZ-|{xO!!LGL@|PAol}~jIbUpX5Y7kteDz%?NIO|BPEGI)S0`IX?{?vANwb<RINVF?
zK$fos7Em@VOJj%rzm0X%Wr-c$NboVrk?83_=V9;U@nAO1i+|unH3iMBh=Oq(b#>X;
zA3<v4>8ugH-9lLnw5~e6D!e_atA-me?)TJ2q`J=fAU`7DS~^O@-3eWBVN;xE7N#)&
zf(#o%Vg(C9!gmJgKye4JJtfxajzFnf0Ag-5J&CDCZ`4kdfwYaBeDExTCd<9UiUk?O
zNYQVY8vsX7)MLB6k7(^$PIL;fw~K9NKRa7ii^E=jWz_~nT>{}afQ_Z_8R-ix46Ql;
zHODLePwX_cR`{t&ltf64sBXGacoY`AwS57l7pqo2(&QD($1YSvkV`*wNX2y(I@76~
zw|B&BH**8*e(O&bGe;|UlNVkKni*9ag!Mx%rw?$!_)0;m(bB!Bc_dc7ay=58dr+s{
zQF5Ox1kV~QceA1i6zqEE^J6(u9s0Fg0{uv+O#<c6GKOSo3_S->(qJ7nHo0Ei<NP|P
za2n&{%!meoO@J|;1BA|KT826<+wkv#O-63B;{}m>T%0R>&dM<BJ9zLf*uHv+#hi}Y
z?OooO3B<tmWZ!o6973C7BHGZVbcIQ>l`R0r>kMM1Fx=p~aOJ1`5RYMp3w?PZ<FAe#
z9OCn`H%yZA!56o0-GZPUGgnq=$82tgvn;p}Xr`fQx2~C5s)6m+<hZ84?CL+jy_O*+
zjYPj$0djO^WC)0@z?W6>E}Ca~m(7>7b);(v+CF9y&==0F8}UtU{^GOI%0ZHQqWU44
zzr}cy{#j@6&gA(El^)@G{=K*7!2>PROLU+j%!1onW`?lTmiO=xt_*uUJv-K#Th!l(
zsewh6hmwm<?f%lSjkwQcTOE6r-UazVGzL(KK_P6jk6?`#<n4JHogfy{6tp!8kx&2_
zW~xbtG9ZYtZO649@VnI3v5!!{=p9fds%1)zBA<*kLn50iZ!O9w@-tI#n<rf=cac=q
zWUDMhUD-4&h4%&6Zf>5@1F0`bXMvbvp5tGB(kY$xyoqs3#*5%TYk$RndpiE-0R})f
zQMID7HYvfDEoWJ|G?$0mohF?0)npNuH|Df&#Pv6vOgrBMOB0so4Q&H`J{u{|e1*F{
zvmB~VXk8ODfQe}Fn)*RuTSacW1Qsx*?u(&XZvbhD>BNW>RgfR~Qf=pO+|s>POiXP?
zYlL^)_b{1z(IYB$H%6Z?aX>mc%J7pkVa%0_h^rNIS2)X03ihfRUL*{6dE9~J|D*h)
z+z7>VTNgGAp%e@ql^f0!D!@GqZ&X%62F(J73z)!P+aX1DH1l8Fq}hLzFeH3#!sMW9
zF6fBVbtP?6K5L|G_AL5R4+3(~E)?aX{uL4-zSL93Us($rMpW*aOy^Y6BCkshvHl=c
z#kn;TE+DL@FAh0d`i0XE7(bUrm^cVKWf9cLnKo<LM>l`|S*ei%W=RV9)!Eqhe40;e
z^>I`j{6-HYi~y?Zf=Yl-*vn$6-v^1%<PQ)L(F^2|XJm}t9)N+fQ3EIZsTcvN(>^H~
zkE^AGB_4oLun0m#M`z<m)y*XsZpQ<^bno~v?vA3abk|trqUJ-_*CPD+o~rd77Te6L
zHk2P!eLp{ha=2)mLHE-$55)Q>BjNza$%Ic56YIzwZyvbJFWaM=UL!r=3>mCS6mRY*
zaTSO@I&<wHY3RjIr;)tYNE3@vkkqK~?9{OFSOXwi5vDoL{w&DBFx^Q7qGih#b@yO3
zL-Ki8cAa~tiYvPJH4VZ;^tC4E9M?$nh}L1MXofR%QC_siyl#wMXo2YPX5E8pNYuM_
z(DYd{-<c|0$N&U3MlfCjA6LNK)w^u?GJADNxO?takHP-mjkSYgtg<+k?))C87UF(%
z<FJifwQ=mr9uBMRuCMq4o0?JzA*k~0qt!0^GAlJTq)mqn?>vv-Z|!OhJDKIdH?Wq*
z!fDa$aw|D-jJE567N)M^I}D;dLAbuF89-0R3c9fyu2=wP_v5&lth-c2N~2lirBScg
zqIXLddw^!d&0J|cEc7|QoL#s+7j76j+r}xM4yU^2J9y@f_3X@<WDMy=)a&G+KAyF%
z6?@D+`on^JmiOAe2FDJNUd{?1Sv%F6b^?WH#WU6l<@xz$!e?$PioIMCg~ExacAu2+
z8BvQK*g<Y$+`fyQ?dWZ8V1!*4w#sP#H!X3PN&lUN?*$w~bT>LnA&Uif-7Q*TW$a=?
zk{7!FNG)uMaaued(tpvCb9ifaaZWl|CvX6kn&#ELtL@X`04*_RoD&8ZP%3DABYal{
z8*YxWsK((6ZC~w4;ejF6?dt1&#gN&BUvJE?LlkkDOAl4D0@&+HL5YJF{8zv{L$6sQ
z1bTXgJWhunO(KpqZlnmm^tT-e(mZP*ttB*k)a#&I&jYlK@A=Wkg!50_ElUk^aOOZJ
z{RXv@tEy5}psl)z=PjSoiBB{hCf<N=D&$ybIJ5;E7tBd6qB<HAknz6IckR*!N>t}7
zbu4s`iU38{3%^@=^L6O-WI{^3`WXk9>Vy?75b*+4A@u`hd|@opT*N3znhukFfq6Vk
za)O&WF{1Z8@3E{?7mp00ts*DctQ<r42_<_>QD&=d68jaa_J3#K%z>+*>jfzMpnH2-
z0ul6eZk2st<sJ2xDQdH+m^$#J0C7!C?d4-!jTjNLj#o_#4x8sC?Ow<U;%=PkRTjlI
zFO?Q|FMBrb)3=w7pMW5l%CjCgskuK3rQ)~g$3ReTO9N8`M;`N%!)*1GELPlLiIY$%
z{S`nMPRXd3__WDg)<!8hOcX%ZR|?>B{{zH!lfXzO5~bx7N{+-p_U_bwEoe@Su&d$l
z1DQcfpzPPUDW-Io8b?2qw&<0y?Fu}Wq}!4*nq)6%L0i850;;QlKBY^eqO2HoFwgsb
z8~`nQtqy!k?kMU1nn>*evTQ8^s%I9b{;rlgcb^df8cWNC$DH{V%|pbN{FsiCh@RB>
zY>`J3n=GT)KP`_cU2Wy~h?=?1QpqPO9B;@k__1N>xX+)5|1Iaz>cH0AA+ev$JnJqK
zc&NS>Dx<Sr6NeIEl<%~sKT}jpF=0$hRz&~B0m8?I8qMZp*XlE)-UL}g((fc2YM3gn
zX6pl41U1wG6A~gRt7;xkV*eRPG`Yf|jU+Ry;A$&`6d@<K<o`e+FwuY|hX}cfM|K3h
zXfv%hnvY_>d5fudlLs%OJ}@^g8pw)0uj2|ar+Ip^89%>mro*^ho)x7~3hP$mo!|r>
z9V(Yl{tt$vDC5y%2wzFS)0^Mxg3ZD>(ACba4*R=b8g#H4Z^1HDubWlACh{!`A#nyS
z6_~}JHDD^3tzg<tqkQbcHv3h?F}Ok^Lu&F?s@?IvcGC}8e9}Q!nn*uhja~?GM3%*)
zVPaApbjN|lS&<%`ZmEShF~cl2cg@@Hyy9uFO(!wvUFUTz_T382-k2?N->Gz%Np@ii
zb-&xCt9=nA@4B3my~4#B$tWomoF2Z7R<nv1p6;swYo?5%{Vu-;UqP^hbxj?Oh`1k3
z=*`>RoSLI*F(>ORv(m3m*4nRCDy;~7CP^YI!_K1(*lB3B=w2P1b>$0)>#SQuZ6RZK
ztA8hA-rxpd@fghvOjW4Ywri*)ebH+HLHho+P_bnZ`vJ<5>(%xfw<}UBW2A0JT9nL!
z*i=t@jo93cu|9q<UOs<9mkTI`vqcO7kFj4xuANedz~`6o5d0GC9h{XqvA{?ZFe2T3
zLP^@P@-AW5=13HDZ_`_H1=J9cYfRzkXqy=k=r_^pgiy+x7}+xinIO5GjJ?RO!>Js*
z0#+9fgoi2=sUpPtd}v|UoSd@3ytH^Dq`&O)kQA|hz&lv<;Zsj7OG7C&n4)x6zU-_V
zyLRl95&W7lKn(1MH0C`<TL4FZbwfU-H5sAn??%Ttl{nMwC(@iowNNyR#UC0Q6x~_0
zEXu!>S_US7o$~7hp^{{Xyum9-e?I-+W?h<Jg`kg`Ib`DR&TE)0s#W`plZG7LXz7ew
z%q48{8r3s;5vFawiW8QU$#*!l_IS$s`#Jwqu7_A3>5QY^(q<M0uP`i~B%}Br3*rfm
zX0ou#A?m_H0=$Bj`y4l+jO~8SMAG%ySX!Z%#RYAvV>r7fMostl-dDqJXigbuNlF(O
zctJoKQk5E)HVE_qp4E5=BM@PmQd&0UNIX5M;LW})?=E*>xh{#ReJcAveivCeTyR$5
z-X95gjA07#Tt50|Wc_I<SGm7Af$Y4D>YlrXujJs{P1MZ?ODy>~yKlcjcZf%$0B+jE
zC`1W%VsEcJr{@xKk4k_O+HugV03M%xGZ+6b3&nRYrj~lSU>rQdQIF!S&gBh}bgype
zy@0LJ;jO_RCx?sjIZKpNe2waH!ALX>76i41u?JuVI0IV*u*P8<#`t))z3kq9&cL3&
zVcvUP5HZ(~lS*(-Gz3!R9My*&a1-0Re%vQoI6Tq^beN|vC%f{T1eQGzB}ae+zBzaR
zV&(w~!Un;+5p(}0MT~0niRYX`bAIVI#)Wl<uX%du7+Q9X#xsaHY)1Gf-TKy2P!6l@
zl~iF1dRI^^rBT|3-~Ej1WYW_X#PbS5*q}kzCXxKP`am>(vj0YbK*|R?Y~mq}F%;XQ
zBT%4&!K-$5hX4}!22XACB)g%*mo>b!gKyZ^Q|?^plQr{=35%$v5$v<87%bD#ODC#m
z2=lg*!2hGtgrd`p>=hxZxH@P(_?kvklYp}Iijj9l-Ni{wG0c35svvVjTwl-jPFdF)
z<1SwXV^H63)WD}Ul0rLhCY*%flck|W3=LepTo3579u+l6NR5jI<E2*r_W1Ft)iFje
z3K?U?y8l&^^Kwnbm@#n=&cO%s&5S3EPCXe4L8KwVP#41p1^_O*{AG5umO8pgu;A;;
zM3m$XAJ1s{X?Qa-=A;aPJQ|y|ktJLwZPEOHU`)Wm)@6F=k?z@yo6<@Mct>n4#EXvG
zFcaF+c*nN2Y8Hui8KJIqNIatIu`lwPh*-j}7ylrLFeMK={=x(FaesU>GKs@i7Rs9=
zYa_#`vBh>b|6i^7OzK&HObOytnkvlK6L~=gi~$Y$QIG139wZ#`*ck_QLLgK3-hH+j
zhczKp-s7?R3DU<gCNB>8x;S7Mw^8XVJ%clS;X{0NJ%D!7tZjLrQL#BDElGzHbreBu
zD<3UUbqQK@r;(qB-?l>0lyOr-+Mq?(v5goKDCGW2ki;yWMf54qnaQdiHyoaIq63{v
zT!I7<>|UHHHt1@8dzt=#vyn%W49FDf?SMU~hZM&pwU645Nd#5P@MN@RRO?jCg_Gb~
zvpcjHh(SwIU#m=(FAP-ohx`8N?C8VKThU!3A5xOp1!?rC9Xr&hh_dQ^rBwzKTWLQj
zm$AFp_j5Z2j^={y>|28MI_Ky0txp+*8azSNAG@^1n1M7lAm7_kgY2<d&^SLXdZ9Ib
zmK-TltR_*!$HMC@79uXI@kp0s&Vx#VL=4E~9{@RO3CTi`3+<xLiGAAa#S1L|cY>t{
z0<3Fs=#+~9#!UkUlS!*L^P*6s%U}a}>DbbmT7c$VMHm?fk!srsrwh1YRNCI_mYf<u
zF4*bzYSq(?*VCf({?1M>;>D-W<$6c6P-s-q)6E@6kubM5@BeS9aSYQv)Vu}(0vSn;
z6iDFD2tLlXAI>rwo<k`%hY|}$(9NX290JBa?efe3taeyx?4Be!F-};7PrI!EIFj-#
z1V6EPi;l5{Hl4XarN;>MF4mV|5YXRH*r;K#f#hV?jq4`w<d3r#GkDc)l4PqYyN77s
zy4l?ICuMbr&016cPC5juY;Zzi-CT=9*CC4W9g`MjZBa)4AOdrqI^Snohu3<p``dEI
zI4phCrIU%N!J2ftE=@PvvqjcImpJMPS^Y$Wpv@(Pw3GqhyrzxS8&s4SSxXE7<(u67
zem{cUr|i6<(^=0Xb=i|oIL0VGZ*bge+}3UU4K&x-CU8sB`)(9K4Gk2wytcmHj};KP
z5@|;om$4*z4yww#V^|Y}Tek&l!2xn$I9Ks`z#p`cVv{8-h(a`r$FUEM*7x28GnF5f
zPhWul<wb!Jgd2NRfoy*S8<C=oM@S0mXnn(7QLPqT`9IF|<;kyg?^<NbakqH2zzEX^
zM*B!dV<&>a3i<|tgABl!`qywg(ftsWgU&cf!FW7VifNv`4+z#^_8M2p=@mjBda2~Q
z_4vp;;9NrM!|v<a9OiP*{d%_{9iAb(a0e(cZ*9R}YCoV2P8bY;(s4m4`TuY_s+b9r
z*m7<${?j`bE<A(BWJcAZ(28+5%&7X`dP~%iVB<WbJ-`Z}tX`I6Z!6x@C3(RfZj*!J
zxMxav<Osxo_H@`e-F$zZ<aatg^e$g3li`OUtjPId);AG^<|a;jT6~KGAbRv1tSLAU
zfXS(_;kg&Vi|9D8^i~ug@GC_LKTM<qQ4@5f1szOz#s;5X3fK3sTLtEWfL*C5e5nTs
zT0J5YK`YTTst0T^D6U9L54t^tPd=-7gc%!%ldUw_^j+L(pTFVJD!dd3*57?0_ux_$
z-?08~(Z&UEQ_fN<m-gd!V&=y+^6=&hUZ2g1e(x(|h@cVUx;GUUY@ReAMTmM!SY#o+
zx*Kp#KEAGJx732##ZM^nLvp+Z3x#-42z|Zj`3pjzE#3)4LvOYugX6j_Hfe&mzS;&6
z&6g!!*z|-&cpugnyTGA;vHURY$IcW&_9kY(5<-tJ5#f7wM6F2+<zO}2Oyt2LnfU6^
zOsqYhdUM*~7cFit&uC=_vd^nJe7f@nV$7DXIt0%?;=XpVR5BOD*(SW~H8BGImVT3w
zo|=G<%mk3X8n&MCNdUN4!f|Uah`jK|1~=e!5FWU;_k(GK>sWv*rbg~DZ2}nVY#56Z
zNJ7F5dq`@<acO7eVL<$CP=!(1mCb6U-D8(M4dmTVTRq4oL5q5OV*zEnLRJ1$Vq{hi
z^9IQp!Q=(tI-B#iMnV3^&OCGVoqopQM&+ne8--XND??|S^!wuA4kg~m5s#2dZM2<h
z-IU|^&a;x1<QMs1P^xyd*XN-Epk)|+7jBX4^_q{wYimWsXlrZ#OCp0N)}Wz$+Xp9O
zY&PMrY;7Yimb4<DUkpus(Md(A0%DlZ>dS^tDvCeSLEcR|6-kr$&7O`lu?7c9wbf71
zc<z;L6)dZV3WM()jp<kYfYeJGeg_2|sx#nI+8IzGBTu0cO%7uj)BAcSwHK}H3V|p$
zBz>lD<S3YY-)Yz%D&Ciwrmf;ommSF4iO7;WA8xzB)jzc4lDfPpu-0YH1p+EWF7yxA
zdvU(i47>-%e|iNfCp00l;W6w@35l{WMr5)hQQok|hGWZyA4Eo35Ds`#6kf{D*~97#
zm$#QzIZ?NPEY8cJkFyx;yIy}dl$+9S7A~V&%Gs=(X5dhswn6uqm3#W=DehiDPfg>#
zOFTe<MfL#MF+1pSSnB87c{9|iCy)z(w@i0)PHxOnpUFJFqk-Lq#yqe6kZ)9Z#VuUD
zU1CfNrI$O*3{*A$0qzDW8d}|oUeDydK4VlOcieFh@?9ys-*B@Z%x<#u&YF9Hx>s^^
zI*FPcK8b2U+pL>*+#)59g+q63d008_aZlZhO`hYgd4FDp(Bg%7L6szp%^^S|8P1KD
z9g$jxqh%3uF*jXXI>lcvh`u!;xfMn;;zDl((+p9O*stPsA%%oioM3A3t~k6rNzu_U
zYL>lnVjDv5cnU(o)z!%Vxeg5`!nn*(PIvF1yTIrUm5#IrlaYx@H%5UB5HJd6kfFZU
zVL#VjCcZW_thcM`l~wLbY8|b?farW3ADcfA{|K2py5#;yuy3j>j*@vvte!*VS)3eK
zM-?3-Klg1a3_i#5kaE^^E!Ll7?z)P5q&h`l`OXR!-DYfc_y{;r?UX~XwgokdcB>LP
z=8FlXY!7KWC02k;Nzb$~r3bYCsF0Lk6m)M9ge9ybMvYMdz5cKsevc?8_*wz<f*cV6
zWEj7g<17CwGJxl@2-v2}PcV+|mEx%p;_(}3RVumq)~W^HV>yBbowZWuUTpNa0qi3P
z%MWq9xI*#2QhIx|S;p%I(Us(oMk$kkwJr;+jf#L7Vqu-OMhJyCIc=dOByFW1kT$)l
zrCf!2$<lWELKC;W6w^e6&6-q$_!RYz2w)NuX(}VBT`6N1^63iWbo9__JDYA&;Nwc$
zM$oVOy(;)tP7v5_rf*{B6(`uIYvwI4)Urex8q+aI6nk=xm8ajqEm{ZGKr-{pNYZnX
zO$3g|mXVusu~;8K6Ah>evJ7Yyrpa@rPSW}K)0X5Jg|4f3JX8L$WmyQE#qR4gifdtF
zK4JP7<`c8*?~NgJIXl0MV(Q|w@;$f$2p}gxRlZj_E#0L@gg|y_)1RI{!+79OBZ8-M
zO52A3_19l3c05r8EI-E<tk?1TaTtkVTmA9X+bGmb=$V32B&m+K@Ni~ln{o9hW5q{}
zT_0b%Kb8Vt=A)dmDTH9qoVcuo)EB1TJjR#g`U|a@o-SjpkV<m1YKp$c)}-`K#&bK7
zMSUTQmFy%Ah+>JcF4lJsK)9lA%{dKb(2zl`<e=)ap1gyW^Li@whBqs+%Ew8+RyIgc
zF8*;N*ieJ&H;;L0m|4kB?mfgB7_;E;%{3h)_Y8;v`W8_Rfv}-P1vwzHo8Rwq9gxb#
zP!4l6+{%0NnH-8)^toQpfx#6U6kK(Y^8|vvfW$n3V_|E?=glGSSIycAm#rV$%!_*O
z>x)C5Z2H)(F|mTHe-A+?4b1Kz6aEdw+DbY2Y2|Fg05w3$zij^(wJj@RO|KhP;!@j+
zB+d~0wXGv1hcv$j>e+2GnsU+V2<FisEdI#0(+0cn+Vk*R&q32vM2Rl)c8K3d0m9=?
zezke1!`eTs3O4+fyWjDi%;tKoBlL~MeHv|ei=mw@^p_&`RFRsEUrzF?!~07IYp(c+
zW<~fH<YY0ha~b0dZ81<e=hQfaH!n>k9U%H2)NcHoJ9UU1tF<gG)CT=0)(Y*ldW1%p
z<2_Pcb}33dCx)>|mqm7c6<c*R<v9RiMrjLT7NXl8EjAtEvlFabNmuJ`RMA++gbi&@
z`hkBdiY95)1$&upDMzI;h5@HleHqe0Tu^UDXgJH^G3Q@Ssf)-2_)buyWW}M<Qtzy!
zhtxK+DRs>~hi((KoCT9BfajBTO>>baNP$sY+b#^jmRB1*a<(M9@+c|_3{K6>10JCM
zIYQkE(!Rd@O1KH%oBT`Bf3N3#&|HOdu^f-xS$-obP8rtk9aOD}Xn)@*;Y?oB>D|1C
z_$23a+3nwthp8<)RK!v;PGr;g6t=RaOJLzBT@IU34Jc-{eKz(TvtCdZm&?3@!iV)u
z-!3&TkBuEz)5KkEmF9pwSjLue2d0@?$J=LVNlE?C;)r2o?Z~^hQW9B6s|8<p(ikA-
z^o3!(i-oVtS8u6TWJRYrdy&U<2hiU!>e&Nf3}zI8Vr8-j<IU-^r*##W`wI@H)%=P}
z_f9&}SHi~d34#k&E5~dE#uiGe^P5?`F5`Nyb){KMl#g)j(rG}}(b#3_&NTj@O)yoC
z!$Disb&n66?&1GQYnClw+RICDr-P_@LB#s_nb#CfYNbC5nfUa83RYff;PvX~LQSBw
z<W31YhC;3CZN0bC3&~Cb*{BMCiK=8oOCtc_n+iX5SU@Ph)__abVin^U$L>F0aKayy
zNV-`5&9bAKK7Dl@e(Pz6KlJsnPiKnT%t_QyKKIFaOob8!>O;1Ta>l$KW~d-N@yc)L
zD@6Sn9Zos~XK%jjZ3KK>>qm?Tp?|qQGa^@($l1utR?Qy3?A5kYpjGhuTY}eFF+cZ6
zAlU`#0>Ap)^BE$kAY)BN)v1B8|A+z;1JY!_)31f#>v;_30@}pE39yMWjuhOXYkRPo
z`&QXxzld`m#c|ohYS(##D?wqK5QK|WDvNoWDe7|+4cZEXVhDJ##oFSnL>DR$cT?qk
zLGo{bPWaWeSkJJux`zPrN93E8HvwUpd8T___s4#8hEyDrP)IDq_W$rur|q87{h!FP
zSg#<B_EH!O-s*%92?3&f8w6J7oO9wdmB;R&WRE?_A^l6fNEonTiJimQq{w=a3*-oL
zQ)K^XSj_M**~n?<&s3-QnP#H|oYwTm0K$=pdp&uS@*KItT@~#u&%n5bUndKf#US}?
z;L>ZF`q51;xbxvZ37S&Z0E!T|lRhKL-Abj#x(A0s-M{>&31WGoVAfNf;8Ta=4Sena
zQpVI~HQiDnK?O$5^LK15{Yo$~mBpM|@gQXrDLHOWRyh6**AYgCa95WTBu8>)!%xet
z>d2+*kz}p-Q%EOVy@wt%dec{kM9Vgg?x{wVRr`*2IdqIQ$Go6non)J<)L1ww>tmHx
zt{&=Q6t7$W4lwp5`!2}sGZ_Wg&i|?fbA-64hL)&pJsJz-iaAhdT3lo1_H8kxL76(`
z^YkfiBAEv#&e);*-k{x#?o%I_gDr2$uCP_jj2|^fEeVenu5#AD56=B9mDkCd<arYF
z-zdn)=h-9;Y5i&GFMvMHYmORwy6;pQ(49ncVkJh-NNX|Va(l>={?Qz6{6dx=+B0XT
z^dco)%w9c)#{G$p1E~J+r>KK!lptC3Yl{J<f=?b|i3PICWNE|xW=D~<>$|COSF2qd
zACTVN^6m#yu0!6fWR8KUHvb>JMwk#BYY`_^)W_h6-B`#lAu`@KPtl|YKdhJfD~e)I
zsKBkYuWr&1nuD&pR6lCZS^*mFY`ZOAF|B-9$}`WBV?SFjhTbhZ6|yoDb$_hVRor7C
zvt%XyiK|QAAD$0w&Wr)o)}C^%4mlVq1xw_N@j|`#7-Ve3QlGC35`9xU$a1xttzXtM
z1$TOn_Xj%CZfX4Z4DF_2w7UlJ5Vrh)4O*%9KTEJ#?eHg(_6i5W;oB@|d7C|;RWa^J
zQ%)j{E->7$;<0DexT7Z(%P*4#y{v)JN%`5lWMARH9LcS|{f*+Zlfy9ZH-QVk9!yaF
z4jYS-egzAaZ~^km!I<LioTW2LsJjzw<6AmnX$`NMuOhI;kfrOKqQSRtx5mMDTUj=f
zeyFVo;g!Z+c(VvU43Hk#@)*E^S^*i7KrLi0%4T;~%y_+@rh}ozzpQhwHvTVLcO2ab
zvj2ZCJ$v?C{Az9(L;&K=q1Yw<w}Lt1G!-Xp!AE>`{#pBH(7d0K%I{Pf2KW+%L>PX|
z;M&4fY#hnmL%Oi!1TMcsqr6WuSGUJ|)OAZ`MFhwb8lAxSqqN%cC{K@Eoh|T3fbHeh
zk(y6qE!gXGauKA+_I<X`_$fWM4~WE{7_uhm7CeR6*av7$-x2ibD(d~dW2hH`TRyWJ
z@t<*!s;L(E-Cs>+F12%Bdo!`RE0kCQm_3u#m~QDpn6!vKSFewz;>=ZLI(H>7Oqe@=
zof>J$tu=SSKgf--nK+UzA^R$uJB^)M6iC1dXN!FUcq7@_o&UHrcow|STWMoBU7FED
z0l+2mKZ`U(fw@vH^>jP@!rq@A5Da=1Y#^gKIS$vdaGmHN?aN-?C+iAoh}DpfaXeF>
zCmGBQtQGD|3d8d$@`*Gy^f$@=yx9ea*8Ez~sQ`%Czk7`9w2Y{@@WXpb+O52c_ee^q
zW4%GWIocpS+)pX%nX-vThiB14DF(U%+|y0R`#-4NicLb7plPY+wTpdlp2V(WQ>{Dc
z#|P>LA{T)XhV@7h)5c4A90K@m3FaoxX}bg&N6HHOpUq1JP3Lo6Ju-VrVAhICuotlh
zc^44{c6Z#Aj@^Tpmt`=v6s``QEw*L^HL-a#u(EZ4gZFNMaUanz3nM?n&A|MDBqryi
z(d1@Dv;FlV^RG3MO0>M<`<6g07rr-NgoeNW?ckl}CVZNhd-~NHszgXbv=4T(W=U@K
zyos{<G5bb%UismqPq@ZsI8k+`D}P&#|3O~uxkko1(z-zO2>rU2W*zxD=nv3n6z~TD
zutda!w`@J^zBqZEg3srYy;7K5F&J0qq3GOIr9um~e<hgn?NDP<*>+RUC1i5oS!M{M
zXhHuYUpPq>aj_{l*hd+I7U%eW$d6wI_l1Dpk!PXQCDd%B&gUz-(AhST;FC3&_{~Y+
zu3=9y?xTyI1EzEj*n(501+X*z!0~Wwa*_kQLn=2}#=>M-J>14%nb@QEOhu!V&HYDu
zHa$Mw{si!D)3*JMb!^gvntSks*UEHLSVz3e)MqXg*}MM)(9w5G-sn~Uloywy%l4-h
zRwJQ<92M2sa_-CYATXLN9y0R8QT}y-v#cZJ5W6rb?KV^0Yulm365BN`W40{#w*DoM
zOH$=QrHXXDCd3uNlUf>EtcV4vo(LAYGjk!0V}SbQt6=C07ulWFZVmT|oRmLzV>@Eu
z8iRJS2fM>LVh09Y>#htaDlp}^As@5{P6RB)jW2t{($q!<SLabj3!*JI>6ENl=CsuQ
zeyHa(tk!ZND@Xklvy-)SivYwts}Nq~G;8(abG@h_Ro1JVchbU~7{s*Sv@`xkqGu=l
ztP?7Eiv_%r`Wa_cf$LW&x(&J^t$~nOi3e)RxUcsDwN{<5&sVM5W#m690QtWD=<v=F
z801@CF2G%;&zLu^#J%_WEn@4~S!-cg*!+E;<Y-}dbOBRB>`ac{^e{DcFiLU<NWvl$
zQ<}o)tzDC0U@MTO$soXM?zl#bh+A561}8o$SYpY|+Q`T`y0`r%OVG}Hb1<F0J>hjp
zoTDTL9qLAv#)so*(qlj^0j63KR8e}A>GQ;Ah+U!!{w(3z3MXpRx&wafDfSlNu<VBm
z!6By6pfb1KY8XRMM1lV|56gEed&X^@)1Zm*Lw<IG#ZFv!7oP3Cer3R5MmyQgiRfYB
z#3HLu#ShzwKg#}mVe3(|<B>mXc6A)8ZSc<P!+C`b;|oUn@e$B=;Z3^`f)zoO<!Hg3
z>N&cYQ1;1whs{vGKSf-5`^Z5YC4Ed$C*)m4TnZ5sEuTgL#y0Q_-q>t2Tk>+!RG`jH
zdNyd1_s^fK4MYmGxqWkbrygmwW56fY;R8P~_rZG>Sza?1nkzpsqg}RwFP>Qz=cXL7
z8LNi=j=Qlvf#=E>>TFpxc>GZ77I8^@tX?#ewocw|bQJ8{9`wq|UN=AGw5(vTs`Oyz
z=?|^2s8|V!DKNqg#@l6O|64sDM~+inn1WI$i=33BI6`EdH2QvDVd?>;w<};|JGvqx
zZzv{rKu6RQG3kv`I1Bc-{fOkplq}QcjWE+e`|-i7>j8AH6(G9c<2*th%0Pu|iWMs$
zX`2RQDmSC#M%OP0g?&dzk;Z`Z#L`Pl=2~}z<JvcX;t!YqHhFpFQuGSIhY;%GAfTXD
zY7H0jQ(q>fP9G~Z#~cQiEJZ_WH4uAzQP=|DU$ktJtap|F0ke6$<Ko+8OE7N^302y6
zwT)Ny#i-bdM>vWpR}X*(L&h?b>zYZaU(!0GJNw@M#BJ3v;-OTS2lWJ0>n*iQ-Z^PJ
zqGuZ$<JCLd5@KJ2OWv;y(*$p2-3%NQJ<l%&pmWmw)^@_~zL*2fpi+o5zp<GhUIlJA
zbqoQ#OA`fl{`U=Ba(QD;pM0tK4T8N7p$~*|j%bxX!Yy13xJMMEg9$ru%c_2^5x$~$
zMw|#jpnaIIOKVk7+?V^`m#&?5i`tGqfR`pE5KnE9cvuA)d$cnn<|wxLETUp=+Mn$3
z2Uz>FD}wg*juazx%*z<#u4wp07@$5(Z0z(Fj+)FNGT7Kuz)AWc)yI<oG^_TbgPt=<
zJ=mR-APSE9sKM4gi`)(cR}?3vAa6-%>|GB^tMpNgF<D#wgil9isQCQ)8U!WLMU!A$
z@S*NSjl>W=`Ra#)wio>B+}ZP~jqN=%Cvkai+OyhYRb@VlXbgNzcrTHw{?%4v!7cwC
z{0-DQy#T$KJMi=@n96mSZq@tfE_NsbF7XXDxz6dJ3v8DiJT%6Sv_jernjVsCtP_)F
zym)+3)mFyUXP?~sr<K@p$IbN01A%5m(w%l3!@jFO3#JYcPL@)QEzd1h%oq5e?>8ic
zJ>u|g1tcYL$!AT7-oN(RVP<7FH_awVm4-<tOokA-y>pecEO0+tdOo{v*+w=ejIqMM
zs=4e&h3m@Ojd_h<3N)FDls_i0I&~{pXeyhl3Y!c*;?_8rB`M*u0OvMPI3wLc_1MKR
ztBVpoM^sY7YzQgkEWqR0a103)D#iyB1X`uYFHG0^14iMjdb_g~05e)XsLp1ACmi{P
zb@Zgu+PkSbeGndhAe&f#^(!I0gX;4#*zeRShXzW{7-GHQn}%vzXYZf#Y~89--*}I1
zkD@_5{YWE`qYM*W@Na)`1E4OAz$S*9cP!ntj_>5k8^sCNE_8@MAN5GE;1rumI(Diy
zY;B5cfw!rTa&Hvdst?a7V<nVzSTb&U@1Ta7>-TC@y)s(=Lec&B9^OYJaw6i`Hl+*!
z2R4YtYK&UHWDw<JIVGCgjUZzCu$Blh+EO(V2bTzQpdZ67SkkDR2$aXO2Bz2Iv2Wwr
z`dEHBcFq#J|GLYD7!Se4^<}18Qc?W!8}_0j5W`kE8gczuH0u-KG6umSpWcB)Q8B*Q
zRnq&D)kP%N!Ed~jIpEjC_;x`_Glv3*hTS%(zi`Sn4wpb&4++4+6~{>~!-f@{^92{?
z#tjiWi1bzzi~HdhInm0aaFPO-W}C3pUSq2-=+moQ4Yhnju-;np6%A|FORuovsoTQz
zh}R+#P2Ct1@JJTHIoQiL=jsIBXokpysKZfa9L)pfMZf88UNBqUFHU4mxsBc&mPIT2
zw3lu64j}N43d9h=(Vay!;<7vnY9#MpBD*;A44G_`6fGR$XdU&4h#SpqL(0ux$NVql
z&0{qsxEKBDO6)CU20Sc%%Ld#8qj2;P7_~~$q;klQ-&u^6Uxu#E@(}ctRzm@(CPr@W
z_KB-t5d4+sr)4AMU^Z@2ndW1ZpZ$TckkEqU&BXdTtVil5EL5l*H#2&I4Z3-kvZ{gC
zBp1I3TP^w0kvN3YGZPyP0tpwm_Fyy&Y%_L=p*VW%l&oH@1dp~oc3gblY%DXEadcqF
z{WHHejI<~0B>iyRQ}iWKLs6dGl6ThgbK2H9ea9#b7#esN1rp%$7>(tflNDExN2S$e
z>mFNTUc!q5-0pBwPb7dMC@HC@NUUIvI*He&lm#*(12sr^1FtVF{Pew%JyNET%<|T*
z-2dVYfjtvbeXWHz_|A-kJA^h=+vMszI%;H~Dad^Rm3$sMnR2kXP^k9f7eq3g2O*Hv
zq1auaA^BkN0fpnZ&~@l9Uza<!;F)>qR;-)yb&T%M+vZhNDstZS=2sb<aT?Rn;~3F6
z^w>_{Z>KerVv4FmyjGH259MO-!4!}e5nL-GbRxWx6o~B(uBzMCFS?zSJ6HvU4lgWE
z$=b+}#-#wSY?8;1|8;h$6<hwaWd{oyulg<RI&A{r#PsU|rlBY--I$|Dy-e9VTp2N<
zY5DR2yocKgAdU;nPR<Gy(=e<g+GwPRguLJx5MXralY$*U>qMEy6N68OPj_f2so*M6
z^ilG;V2eVNZE>~2cO_eS2(!PG<_-*>Jb8h%fiKh!v+XdUWl}-2af}tP_Ny73U!#p=
zbmE6c&W%}jEm8m<FsMS_WK;tCVYeUZGSNQrZj|4Os8;I3onDofa={5Z!@G*aShgE$
zX0Q__O&dwet%PnQqK6xQ+do61q$1)oZ$;(ht?C%J-xjcozy}`eFK%eZkM@3A?|UEU
zIxM_$!r}cb7w0JgK`_hY0>D2O@Oza;U}tiBIBKwWd}gOclg4N-Erqm$Ln>Lz%xLCB
z*VbZ{^x@&w&L)ro?L>1Z$E&r?9ZVjHF>Ktbs8fFIBQSMc_^1{nl{EF1u%1Wi!!bAE
zBrAy(D1#Mf%vG$sml}yx|8_6(3zW)1C$irS<N`693(Eov%Yd6q`ZPpgfrAaHi!8H%
z6?`mhtF;9fq(;u+mc{|K79+2W^+;gEs*;?882@7#;;X<+1nnI@9ARJ_<8{LqV)+ry
z5WWKQOa;N4GL7EP2LUm|i>tw{MmWd%-QmMe9@-PWB~~|$hl|l{kQ}ZzzG~oAW{vny
z*GLB+A$h6!+<|Mlk`E}bC@R10k8n0j9~}7DE-8(H`rnhuZO!rpDA!?l(>>VqJvhA}
zI(1Y_avvlJ53~NG#hazhl?b_9`RLPt+(Af5JSyK^ANU<9`P$~gX392WKQS|MqxT0K
z2Kg+JgB_ehw*r~k!*U0YzT&v0FqMVn{Pt7Y?CFp3CrY%?*Wez33m!&Ty+G|x6QOb5
zS1jER@WuvgMrcvB_HHFbsHYF(e`<vi2F|fyLZjg%gtlo~drQigrn<glV?Q8QmAd`;
zZm~pz!eLM~#x1Lu9H+~yNt^D7@NGS9+H)6|HE29eZyNZdh#5=|X_u{P*uNXgm1dE^
z*N#)(WK++rP-GuUP8_%;3^;gf@#}%v9Fd8qmoimc4BFDkl5)VJXJl`J-8IAklX~QN
zhCqXKklqHFpsqWRVA13nlJp#m2K-Drkq|dX5;pdgBxftF^VH!iky;$3kdo;{tz)#H
zl4ZtHxnLHDp=Bzs$5~QbZvRvPJALY`P)JRZW>~h@e1GazGPAxZu^YJFp?u--HF-t4
ztHPR&9Vw>5DJ+)=S+l`Mx)1mbQ*YP2c0k*A0SRTiBXp{Y?yd;%9R}<`la)P1`h4=Q
z(&b?Q4L{fH$KU6YNN}f44~K>{_o*`|MD*F*of=wgqU|+W|9Sk5SHhdZZ7nCP0nA;d
z#d|QIgSt7I>x{yd_ksc#7er_Jv}V@bhS;h*B7)w15{7HU47F;Mj=X1M7RR91^|Sfm
z+=OJ?AHwB{C{@Ob)d6s_h|xl~KLHKRBq2|LT@ZAu9Lgta;pk|8OJGZrd;D%Vl)13=
zJ*SI$nl~uiDB7dRz#+=%m9|~G|5{i7I)6#c(N2eix2b?k(o8u%sPKh?688(N`JQ9i
zEd<fCpZ79=kH53fz(IET8t_RbmE(fP{QGY9($s!xDTiLQJeJD~dTR6mb0{}i)fgib
zLcCjagEe69$@+<hpk06(TQc{S%CaG8Wa|jW83@|hKvCvRuwLOET1e<H1kW~q;afTQ
z2ao@Vn!f>CrL;F~Y?3>C!X66_-goQE<`D|zW4jiG;Cyt9Gc#HslFFp6wYA*q{rv#d
zR&CFa_Kj*jgmT?UN*NC!bnipj`;z0AqwKeA`A>zWZlE0&d@P{!ay24662MsAS#e_?
zuBW$Jh8@pOR!isiYM{MXg?sq#Md{fbG8Yk!(DVBZtsucLOXlclKx@w}*Y~OXfQ7K>
zQ_py;k^m~UB|F{;hx)4qoFq;b%Ar3QqiVtWnR1`4y2&1FQy{(X^n-v1W|X0PT-_ua
z^>Oca?j(0U(ijnC4IpVCSg_F)$s{s@apEeJ^d0#6Y;r03VuLbc6b_sU%7<CME<AM!
zXDY;@7nXHa%JxLEJ|Ujw?I!}}3MHd95Y_DkVZz`Fqvo>-yEe`CQq4CGNzRz^POH!L
zvrI{MC9fHQxi!+Y$q%+k&|M7tIl{YzqSD2uQ;sS*e6rZm#u1;FIMlXdmY>Klhl!Sm
zej)poRn^-xtb8QDtEJ7^_Trx(Qp^O>8^u!7qa&=R3VFh#q5`t**!ER{OS7Gt1fLjf
zGmA>irXIu}@pzRR0p-iTi)xtW5e*Z#dT7H6%miA;@2p^9D5gucSiLB0709%$ShK1m
z;w2kQs~AnlzON%{OkOLtk7ZDIPqz(SS1bJE;@YH^61|?M#*w(6nx`&_;1(Tvo*rrL
zMPox;33;!9nrFfAwkdIx<F+KFxu&C{#~5UTptx&u{5&e+sa>orjnb!+**d^{SJonx
z*Mxi6P>@WlegQIfxDbQZLVm;Z5Msr%sy>~*otl;R(!)hq*f8ErCLRpHdhpY+oIv-@
z5B?zqEydC_eSpZ2_M>5=wdy(fYL&;jGKPw68zSj50dgFw;N>joEgLtmm=6;+s=-LI
zl#cF8JMZ9eqVRj@dJddzF*92*Ch}@b(3r@vk;E{@IrzRp8q$y>^NN9&jOKT@AvXM&
z5t>I$i~-tih~TkH+IsJ}-e-$-dT-DvK=<0jdxVM)-*Ms2R*R7!)Df~ok<k`lOla|R
zzW0aAs!rBs{JgN9b`U(BNC4D)QYMb3CsX$VQ>*Hk-S0?@$8-YeUP<fd(Pad5>+e;f
z7%lRyRg}Zaeix{?hG^;Mx~X(Vuyz7a<FN0p^==EofFl?~+YsFtTn3EIk==#KHblZv
z14sp4{k!=UF%Rli9#a9V8}lW>e2;Vt@>$<b`D_Yv`3>D%Y<MboC&v@}dF!s{fW~Z=
zt7Vn;bgZu|mcjI~O1xPEt#d+EFdIENVD-9oRG&)@Y=@jG(7iw)c5!kn#|s0mghfD^
z8fP+w1vSQ$fIQYr-|GOr6mFu3??gArYK^P@%?}GktZ|}-NDp}S_4ttZfWfSG>JQvJ
zfo<1B9`NsbKLn$22*rcSlRXAZ2oKeCcI~SvVtqTxB5o9sEP2Vq(1lPJt*=X7|8MxH
zTmfpTyJiZ!8CK&*N6Wp}`+`6J_&qZkCb*pcXLt~yfEnfLK5A#7B!TaT)TRFG9qP^P
zf|~t3WNi_ESLm{7VK;1N;Z?GdLPhSYzKcfMbil`Nk#+P5-&gs{ixqe)9ul;tGoT^8
z^vCfBs4Xw%M`OZbXK4oF-@#qo;bfv}<98NY#t>oh@a$9xYoyojJ1aFAX+cI1_Mny#
zWyk@Kac)|_#)Z4ANLy!%^hgO~bMe{?LW8M)muAHY;XQv@a-bP9WjSj_PfnlGHLzfG
zr0)`0ZGdeTZ0Q<3R)i>wx!aqbNJ!wcR#qMUwl-IFh%EHt7%4IL9m+9Qn89ut)T<kL
zXQa0SrM}(<cWO&>ltPfZ;AO;|WuOkqQPL{4rdJNe95D~dkiKUG9|DfM7PRl@&FUiY
z*pZwX&*=bX)HEUUhNJn$EsPqAl9c0U_C$YDSva%QZAc&k_>AWsYj+&$pa}^d6-u3+
z<3NOp&wOFJMWg@zDM<j=Cp(yq&iv@VuN~Dr;t6cNp|KIJ1)W%=9{&#D)+dw_&VLAq
zrsug#Xu*91b_F=a#VOL3x~lk1{@IS*f!^yJp_Axcw*mZUPSw+ItP0%gJmi7udCom9
zUifLaW`=fR!ew2AOTyWp1O5Oe1AK~YZ+^JCm!@Qc*-(psMpg)7FTx+86wyezqbUmU
zPJjQ>C<!9Xm~3*{SO}4OMPP@b&Do^%r3Mlt?PY<_>Wpt&XY~0vR_a5hxtN{g`DhjP
z6icg=@ge|0obGAnf#&-jXStLhF9B`kvXYAxEaY;cWJY%13l<IcHD@K(T6-q6`uEV5
zDQ3Hv?^O7`b)xs3q%&FGNv_u0#gb$=^1G%qQZ5)5bs;wrhOVN4?v8mS6jc|J^tp*a
zyZ_Jkk6YMHh~sllWh<bEq&)Q&`sUx00_$oCeCGY#oUdH#%r9w*8pqK;&izl_%eD_r
zj^~GX7p<Ri)vqVPsNkcTd8;UF_@Kc9*P*Tlnl5ow>lgX~HE=;UON&f~Z(Ehf3-ge3
za<|u5WlJKuZC_RLYq!{v5g9nN10aV#`!c{5nGu-7=rZ45Ms*yQk>`CMt#+~_bd$uV
zG{2mOuKc^6@H4`wv`1>xL@`Oc5;$@#F+4k`h<QaEl$aN$O_qX{xuf7(UX6VHI8MM&
zMKaty<o8vz&VL#t@XkTz6lvoSZgLn~kD}f;sOd%Wg_&@azO{-C<q-CHiNHH*9M0U`
zH+{6iX{j>7MEf;3%}Pd`r~J%H??ipyQP^AzCN6O?O+4N5L?uC^%+#ETLSQtwdjt|h
z{zhZ+mjld?c&*917;RNX?Y*Ubg21Wk!wHfUVT5KSJ0~go=$RK`W~^bLpCUBahskJ%
z*NYT5YKFnt4S*u6q9olknrH>&QUnG4F8WZv9_f*5Wm5|Pxc~hjYX~dvK3rdU_^)Bx
z^pYo+aZ%3{<gxc6OvtRHYOj-rQVRUcQw5qaOq!Oe;u%h<b)vc!{Kl-2V2OmnK0#1j
zuEx5yg%4QAj1RR=ge`MA?YfeU9L)6C{<Jw!6O1yD^c!PMPW^cA+GBK1v8?R7-^Aw3
z(X9{t_Em7+81C1s3~$RMynFU`T0zrIhyfen6_q+jSE=Vz-F|;7O743B6mTWvNyr09
zCygNIeO&p=0k$HLeH(&n0oafy%6-e<P~3p4KHvHx9K!g>$(qZ-vY0gHa5pR&2wXEE
z`B77|NQ9%O;P|no1OLi5XImJa?py$t8qga7ujS#{=#Ft@A32T_Mj=^6siZO7Ruy!5
z(lXZJNdARa&-aef8DZPm9sCYaV7-~}L)XM8_OVupX1eX76SnB=a=WQLgS42c*}Uew
z_?Fx5KC+xi>gIoX&ZEVn@XB>Cey&Ox`X}kT!}Gz>caBPdiBaRdc)o7RO$PsfI>1f)
z*XTyrj#5~rFSVtLW0OJ9v6;bAIxPA?Zf=06@KB?iOz=6(y4$>hIQP4%mHE5kVFlss
zegGxbYf7>%EE{x^KN2z<o;`B7x*p0$hq;;gvNc7IQiZq18kxG=@c1k^)~F$T!Hj63
z@j!kc1u<YO;W8q-W8_Z%eMk5xE61Z}(j+MT=^#H}s=d+kl)gn3k#Wq@v`JTN_G)Gc
zi^q4=ZuR7ze@QO@9QV}?jh}`GaW1ElTIaCw$9%G?$f+4L29qdP61WMDK~RJ;Smd|+
z;xQkRP^o1jP&;ePM~QOMyY%Y6F?tSzl^gab&K^3CjtGGNN{X3)a%>35#k#-NX?OS)
zeH#`*S4|ZW`nQeGs5biWEu=q5vkZMQp)%FeNEI#3h17q8U;%z@g1Kj7q-!g1bz!5c
zIrJGkYowl`UgjioJ8@sQZTPyuWnJ{noaOX%+|;@Owtk<s%ClWs>SNn;6~N?qB$69&
zcAQmOW_*!!0JxM?_U*6JQk^_4a_lb*%5z?#k~cu;-(=z71ww-hAs?a#$G0BV>veJ=
zC0537MXk^wIIfIfL06E^H<X;i08}dL=li1qaC{8gMqGS#%ftdGu{{(=v4334EQQOm
zyD1FHxR}PjujxT$S4!r&b@bSWx#)i7S!eqH_Yh)^x8+9U>xGM4$eAg%E>!M)((aJ`
zd!V)N=7DWQGWjn5H@7mx4ppu1{B|mE*r(})w%o+RV-um-qgjK&G`Gnh;9cmb>M<cg
z(HgYMBddc~m{oGHa*1epT%|4Sp_QM5v=W!C`dO<p&gMlAAIEza`H{k=<1Jh{*)An&
zO!5EhSL=8}E&c8&)=)tufLf}1);vGVz>qNtEdtUOXN;92Zq<Yzp!Q*x%=25fM3{!9
zgJzk<8Zd&sG3)wKYoMteJZL)xPG<U)wKp6+)5&o^;g`5Svru1Ck|Hs^Lx@dcT?Liy
zpNG%RE;2C{ASU|V*oqnMS^3$yR(zH=%ZK{u4@qEOD0SM~RIPbnbx+hj@(usN@e`7W
zB1DrmtAMS-c-oHZq`AOYcJCZmNSd^rv;f_Ec85_z;05X5=J4#^4=_rKKGcH(3mS@#
z($E3ptxKogUadbr$?*gU1CbFK8sFB0Qn8^1hD;IgP7*1zP;H(LN6s)_<t+03I=vSt
zgn%oeTz~i`k+|GN4a?TnW-@&KYGP;{ZU)h|*dlwspT#&UkOINCd1@Gaxxg2tsNkw!
zqZzzD8i!R95gg3DY}$)RQR)cch+l~3GvTVd^v38gY9B`3f&q%?k*=Ejco@C%5HPRq
zR1`&Nt$riib88K8`Fsr2MH3p1L^`R*?V{Y)%@hNn-ar+HE0VzEyzj~YQcSs(1nAu6
zPQFLWD^3Gp%teh5Xb2JzQcW4cn_JXq?d#=>D@8=Prcd=>#{h1{RQW>|_Y;Adg|9{g
zN|Hv*;AhjBZ+~E)CeCm%=&L4?M|RBI!~J<tQ9{-T_Hr;}%xY5C38FHhP+d1kAIhSz
z3cVeR*Hvv)|9zLee&>x@5lwC4*DC3H4kqJUsM`T@^e0pqgO!<%o-HZLu<b#n=bSXc
z23n2!c*e28t86-h&ozIwM?vL1l+MAS5$FJo{?Y8l$1XIePMQ&p&$EUhf?^eamECx)
z$<1%nK~w>vMLOtgLHnQ!2)BX;w-eZ{nYX(g7b^(Fe`)jXUZ<PwOq;n31Qx<VYlXF^
zGug)U=)I7AkvL}8x)cqf2u_@PO-a^VUgfJt5U1M)ELB}^-K|iUW~wE^{6hP3izp?u
zYB=9Ql!O?599AzjS5(Q!{2AgL97MB)&y$Z3Ui(&~9UY7tul->sY3lHN)nbYV3VSr7
zPjCm1Mast31N@MT2zVdo2vhy(HN5*!Q}Xn1%$lN8q!8iBvRsY^W-gV%lV@|aB7pJ7
zyo8hD6-KdKy0lPfXfe74i0>n}bFWJZ`RH5ci#TGgOeS9YQOEKz2knWR9h$J3nbl`?
z+C7>1XD`bG0*tFa&p;L+>K<V~(S1=ncBgCG;wY16>vIKdOuAIFewsrxi#mY6Z)Uhe
zA@=)p$_6J6dm|@mSQQ(Q<u@D*xCk1`I!QcMJ*XKSq>Gv|TfGsUN1A{i1^2`B!s4S{
zA<K%tl^z@MSEQTRtON~-tg*8}Q+jDUq$?YFriUms<?tO|wH(wx<-+R5ADZL)A8Sh}
z6tm0~O6l=7aiOry4swC5#9pxM@+?r%eE2v!3p2kKB_KyLB2WBUB)E5;Y*p9`-+_?p
zTtxPHR1wJF{sQYfV9BN$#>wwv)JW}LbK-t6@Rh;6P1>eotpZLSE|aFGHkRpwA94?+
zE}&1TM8_La-Tu@|<$J5U$DVqeFGp~FLOp$`5df8@6!uni6qK2>n5J|CM)y|Y<L(U+
zZ{E-sv_o6obJsca!v^XqLQzazjT(@}lysWKB>8O9C{y}gau{@Htr!MnU|=JAT`0%$
z6Rv09_9M;Kr7~0lOBeJCms`U7uF;SB_OoU|`IM9Ptu{ZH+7Uq=>Jlm4FXyc|VjR7G
zGD;++!PPKUCd?}pu8=e1l-bTLi%m4rk0IwJdF*KiUOu>(tF5OCo*+2yYg*E&h@1hy
zNT+*?T3&WW87sB`b+6jkUSPe+*%ysGD7b`T4(PV7OQFdM>!q=@<ZEkY`h;{G`3xI=
zE!LJi)_Q2~K?%R-<4H*}jk$YKwrW!^u0j*`_w3Uwza!fRue0P09nd19Y_Tw3CqR;l
zr`72R47}mRRF8|LGI#LmZ%hvMtvu9x`7nDm%JZ8~hl%GXHvbs$J35;{Z}OI6Hc`C0
z8v%B@{6L_%)fy#~pnUW)ze?x;E%J)Y;&Hp@#sdOf;j2wOjE;-PcOrKd>sCD7$FqC(
zdG;tuYEF}6Zzf$XZ5N7R+&(`WPM@D`m&0+hJp2)H-1v@{(*1_Tx62|fkH&}9Q0V7v
zz%bo#qXV{p*N&{kzr}hh0_62mSzEs-qrnhFzFh1l_7XxyMgFu`H2+!d&-8?O56o3Z
zqUHk#n$*<iE=v-sb`wv@@ka>OW8z1jqR&W|*8YTYM%8Z4$Cwhd<`UO{Y8dDOYhfFu
z1kn@Y^bj$PxRNfBZ+#Ld_@65`W(&%+L>7vlrJ*~+y9L$vDUyCk>t!?$G!W&ZHJ<GV
zMe`3-?zD~6D`_NO7Y5;JL%OlQ&37!OO_bos;kTSlVn8d=DaSR@+tkM#T4Rm|(hEh0
zRj8xZbpkhWl6|D5ibM}uGsox-y~@tCGL}+GOnDl(-SIY?0YO^E-`)uwRVP_qX5D=}
zs6<b3I?odVu*LInQ9>+kE*crxa2}drbe}D2^zk*#Sh)V#C_!{}&D^zTt+gD*${HtD
ziUPw#|Ms|tsFFt^34;i=>1_8-_4LRtonE(pYvmo<XwYEva8?xV-^zh6+06P|-j{8w
z^t)Ndz}f1)FY=uUxr}lDAZjP)DBoxJlKdqle3dDi5oeoYS6mkCc)tm|qoivt6+a4-
z7l;Pk-Qo_kXO^F$z8UG?mFrRw)uPej5_Ho!t8Xw{Z#qH$f<hMcbZJ^xqFo^dg>Yx;
zH=e(uVan4eS@dZ{Gqpv_#+;RC8ydV4NG%IzD+yI5c@7Q$9H^?B#uu1)B6BW818&V<
zGxVC6#?0@wt-{fRD9<$A9F?b>V~fczLD|ptDD4XQzC{izxGk&48pu`#=o}<CH<esA
zM6Hp-hX_)$kp<qZZmQrls)wkA!(z+5MPv9}XGApW=`vsX=Q*M>UswWWoNlRnw3sEX
z*@a}STR|^NQ~kJgPLd7@QgY8}t5F<Ec>~AnO{ta(seaU)@X+=ko&CYvy9S3_%Bt^F
zqw=OXQx`2T5F-9F+)c}rEJsJve%j*nG9mJ<gLws%nFK{X!2vTWK;~Q`JKj^tJff3}
zKm|VEgBrDx@(zWD1vi2C1)tyMI;>@$sL!iTUa!tQ{W;DR#54@7z74;A4c1E~i*m_=
zMEW;ATXTyBm~4mbOVfifc~H%hI@p`$d=cwkTK*@n0YiF{I|r+V7=cT!oNncA!4m4e
zEPT6Ga5p;@Fqn@E=awxnT1w+wCU{*f!bf<E%<k?32Zc50p^ZnL>{K|^BbUo5XIX{z
zUizqh9B&E{!vd*HsO4Eje)j`D^hVFt2Akx_mw%QT9>Xi6vvh_l-L9Lld@Q!qYfKRq
z<Y4gOYDEzr(<rU|kD>ZYbg3xK0WUO%Bj`az;ZwH8j3i&P(W$NyH5NzYUwkI}n2(P{
z-K+%tjN))$Qs6<;-eyLb=?{m3!93<8yV`P|`Aj=F1vrrm0eH_L+v72MvMpgQ(qn_5
zVv>OTniK!_vn4Ofg#lEvEYRq4kDKh>h4XG6)OuPgj#+-Vfj?3gz!3!T?6^$faxrd=
zcAzI9ox*L8<0I`X+vLH#Kr;MS)btFe@dx=Z571*jM_;VdZ78uSWl8=vf--A)OS_Tz
zo&geyvsxYVbX{0wh+-{f(|}P1C?T}FG>5Njd8br*A`AJ)uo?1&<QKt!6gfPyWFMZ=
zBZspH>&p)j8x+$jl-O(I!O)Cfk;<FlHVntGvqoNGMF=y4?h@h*0EX{4N_PC-WkNr`
z;mZ5o5`m@P?xfJa5ha-Z)qQ-vG%|nNhT2g0Df?QC4y&jM^65uCq1p<u9LQiC_hRK<
zId#EfhV`ax^EMx!BjSj+lC}&wbIoFUiB=6!rR8clC2YUeb0S;;K&ILv<n;Jz&_*@>
z2}BuR2!6V+md17hKESG;LH&rmA%^vx*k-}Hv)oLROsUg{q}v(K^MF1mDHr6HB-4V?
z?v(Hy<L|J72Hk#>86{1FH-F5(M;YGK(clw!y(UEGz3P$H3HNQk@lt)^#7dzG)(}Ye
z`r6&{S6y`<T*sG)BU`F{Rg$m`8t@>Rp37{J+J}ogj3bbpveGG*ukKhc+>7dt2r?4c
z!7!$=Ezd!8y94$xw2n?Ou!qZ^Goq7S;r=PyqaNmz6U&LNY-C5X>fHkKcJY`KZ${ef
z<Y3f0OtcS1@hC!_>Z8usBUUvVy9B&b*6VcPy9QF!_D9H=0d}W=B5NdGXqaqNKBesl
z@NmW*QJ4XJ&SfMf97eEE)pj?Hw!=+P=RdkVK(nJ%+AuQUN>PsfUR!mdcZ|mab>-#-
z3;S`_0cI6_XCA1rCNnhKJZ)3(+B^6Ni_N(rQ;%_a!p8v5$KxS}0#U7bjm8X3#0dC-
zTe@rhIIKHTctBw)T{rZUU6Av?($-7TAx<3ivLJ@o7PF2!gP+00WV!Ss?+Z$3=clZN
zdU#++_+<AN<xDmrM61ZS<F|v>1f-d9SR(Fn&9BT=ULX_-N1iwgs=0ceWkkyh`b{8<
z|DOS8-xCc`cGB(pK5OQWrYgT73XQn>;VXziU|?9RIuRjnpsyDI1R$166y7_B$!SO!
z7toVM_Z_S32t99lt`TeYAJwycla66J)0uEnaR6Rd$!46+#^a!-98(10rnGooND=h`
zB%a1}QH<?mjFaT;gJ`PMDkoQ{jDqm)v~1kWpbd#^1Nt2H>|%=kp!`I^A98PTZQgaC
zWgtNI@BU7)TpZ2Hip4u4!r3=PSl83cxbI!@Cg+4w%HkTH^Y*LvCd`{>y-gP&{5L&l
zqhmStg)*r(h=F-WC)daD2t)^sGcVLw2~iK@W6Dh_Dr&Oqd8~PdZ!m?MJ<Pq0xx}`s
zqQhGW$s0B&*cydDXU8e#q3_@lg$PdQwM>lXq-sWa%hhvac;MHYYc483?AiPZzqc)`
z90U^5WG~^U)9s{m{vuCGH9tT@xH9!P+<(FA*DMZAFx$K$K|e+Q34Cud#NZ#iY<~U@
zzVvJXq1SutyNw^|!Pb$p=}iQpF2%Lh=8Ds-zzdQjP0M9A-pk_S#B<Bh&+-@m{|F>K
z45DXcWT`J)4mt8owm_1jv3e!yn>wU<rDm|PLLX<?F5HP}u+olSj>l?h`>ZelaVPA+
zlbmEECJz8B4@ObrbJ+wltIgqIQ$(A|KUfU<n0>z}S)r5iEDdCZq_hlg^c=@ns?C<h
zR7qn{k0Ro`$eraj1oAN|aQ@MtEk<y7rEr$*Efy%F?jTEhI~bXKC0E%RV_9dg;GaR3
zX1yIe*XpmMZCD}JZtW<q@RJ*r#Fly9S}p=;*|--re8~{*#y??_yR0|KMx?7D;W)gq
z$y~V^xJGKxKlQtVC_$IQQF#YYXl|K>QC(FU7xuAuz|(|oB8Vz2DhMiTs1I5`3$6I(
zx_A)AX-Xa3>7fiGk-GlsW8elvBPE2DtR2aUvIuqN8ce*>GNG2>l3@;G3beqtEhM=j
zTo!*8E_1EuyzDjh<cAMOEs^#7fG}*EsH5-Uuq!0H*mFA!;Pd0EW)*g;h<PEJql=s1
zDuPD|r|m@rA}o*R$Be$vf0={WI*1Lba<MzbCpm@4Qr4Pd)1xQUrkl_ilMOF;kA?Tr
z-UucR{i<4U9kDS{tPA^*)6@OzkQB>vES1FRDifrS&yzUMF)|B@1-OBDDQ9m2pSMI(
zRB6F3Zk#pqOXC;x_NghW!LWRNTH7uu7>{e~+Hj=jO{NF~veA59PvPh{7b{!_Fbv9r
zL8>6dfVtu!bzkgm;g&xJ?mddNv6}ef^G;_GS7;9%j0OtGJntuj3@hboZb~oa5oo5D
z<_8P7ntqmewEd-2{SJHHXwu(j<*kLl!gdf>6-}7bZ8JRLKll&PKD8&v-BP>qgjg8h
zI`EbyM{}VnZy6Bk=l+j@1v|K>G$7-0pP5tepqaAw{oYK55swQ}J(Y^v0)^;#Q8R8G
z-kM2koj>NuC6%YMlMs4Pzil((qu;hEA3`=<DoP|-)1EZGkO~6a&%P?C>WpSM^Uf*|
zK45{;2(%^c8LOmO$Zm?3@dFrqOklv;A?^djCNeh<%v0$MyF{H3N14VNWEpprSuMaS
z(WRP+-S81N>VZCOK~v3*c^(0O-!R#7=Gc`1lp|!!AjIEt8IuBN=qoQ%G<oIm?J&tu
zj>Cs+jY@z475@``?Mr1hcnEhxxk<FSJ*QX73=Kh-Rx;&MAO`jjbWYTut+KF~paDIO
zFAhy;AIu8b=3{r`6vHFRAQfe^AeIOrLmzr3Xg%zBj7CuMh)3SMR*wHUaB}|J@h#R6
z=F|%zPeu%q!?PD19@MIF!1iJ33Hjx`_;TPkc4ap_t4paD6DH1`liO2)(n4`U)GrU;
zxU&#wOZXU`*;>n%q2RlrqI6H%HmGO%Qf@fe^_h{lW5<e@3@FXYsn$g;NGq8SIA8Dz
zp+vnYg;JMgiYkt>0)65Z2RR9u(IQ!zV<xqO!G-R&EfILKs}DoPM7Ek2?34|Q@O{A+
zR5EYeoR}suqv8hh3AWcVie`#5A8<IF>FiuonB$xA*i^{d$0eJ^X?E;U_2R~_ny+Dj
zZ+j%|u5BjvZ@34xCh2N3s9DqbNEji&B4AfYM3o|T2WOdxda`2im5~Ou(bp{E-3@>z
z7Ps$tlmmB{M3qA+(9m>quCpP2pU*PWq<PX%zGnc<<D_G+%5AK>;4hVWgO8|o?sM{_
zSh=BOTq6OhJeu{8@(^c_Jc(YQ)?tyE+Igqx2;@c{BC%+)`YE2DN7fT$`rTw&^*e*f
zHYi_nw#2_uabJe!69C*J4N{0uy1!{{O%QzZr2MrN>0@03<V<T%pb5S4C7pZ!BK#l<
zb|<AFxltl66kyAXMX%KPbVp~4F9EjUJ99PB&~{Z;g5GW6bFE522cZ+`5;$5kU_QuK
zpf0do9reg!6*n9$mrSD7m653=&?a)M>$%?62+oO1llq^5pYw5IOH^<GHgbjJlqD;p
zm@K6%v@!&${OOMl?XA!h_q|ZQu0khR`~(XtfZx8(2CBVCdFE~8!Q`ebjSk$9ym0Iy
zwJrV(SlF?gL|^g+|Lq#s4CED^;n0`E;^lL}Bu<tn@ZSl9&^3I3D}lfip~gW2R<|ol
z^Q-)PS01F`a>xLv{U?U37UM_$IKf+jP5k5Ll1^xaNB}f+)H(PeVGO{E)Z*WA8k^0^
z%H}pWp1e~v4Rwx~xVT)bN2%^o(apSZO*?(jv@KLqwXPIXa{Ggd*8-5<#11}P=#JUA
zQ2@P=a4POV=2#B0s$}mjf%jhKu%A%AAzvLE|La^()^k5Cs}}tx>Kxk~JSBC-Pa2B?
zX~HF0j7DLgS&NB~8CoZaJk8P<>SU)a--CsN=0=gCpg_)n3Mmm9;vBbIj<7HK3id4F
ze+Y?)A`USP<FOU*R*H;(`sJV+1<uWXUDJs}2FJHS7l+dw>IlVRcvp3HPR(w{p&+&C
z>ktGgY+($~<@a)`gX$!(>#fJR@BKZbY>~Lobd`t+=5@h;?B=e%yp49carteVi+)qu
zR;iB@uidE6el4sjjoU&=Q5RGNUe!Gfo2qQRR$!0cR_XpKv3V@2o?v0}fezi;;-Xiv
zQo2e+cN<EqI_c&X&ggDeH6xkI3eVvW0Idr5l@fJ9As)CCT0R&whct5ott{?EavYOU
zivtUgx;tmXN?qAhb%Y-?@v&1ZWltrLkY{4XT>i7GD{m`jqqYRI`7VMbEXS(1K@9Bh
z@r)}=bbG$Nl-qknuW4gBn?qQB)cX8eVk1mW*_~+;;5?bOXYVumk7a3ffW&7;vRjKH
zMy$kr&870-O=GuRS7yBYdx6)CGGn?i@MdNI*5oMWlg`kQw>FML$ahDORe#{9eFkR5
zL~BODH5M3o_}_VTzhKF@ws|hzi|<3Fc{~a8D}kTFm)fn2{(XhygroPhJg%~CDvE1w
zp)d!2!b1GFrY7b>1Mz-;IcPUwvHZ-ja@$U&u-C1LxHLfP&|gr~{(xG&isaOEjU`{l
z5*zVuUagnK!G`o-L1ced1QR<qsGU^U&@jIr=UhpHRepjN)=@$k5NPFHUX7lh5Z-Fd
zHw>hl4AK`tDR`F->k2~Z82q?OoIln66<b7|FpQjWr3fbpF&mQ-_}I1@faC|ezpnwz
z*qQyx^iz$ssGu@ZUULE?;v>`a%y9>Vd-;w+GPQFJ%X0E#-R$Xxs5NzKh2ML9(fB(S
z!|SRrEU*+enugYHg`I^fD?5k-s0c$EK5P@g_4<(7a#c~VOC73gfGJ=}usPAt)56-y
z9GXIYog_o5CNKS<RP;}o?bmRi)C6()iOAA)g*)#>pQpDrV<=6`2APG-I8f94?|>wA
z|Cs1`9Gv8N-HPpcW)Nj8dB_WU#!MfhR`(U(U33U*e|2FaE(~k|AYL5E@gCZtJlWt0
z8l+1|$};|B<C<63Nc2EIV^fNC@l{gOe-|XhOeQ2GXNL^cNHhBQ#lz(*3FK;w;MJP4
z!K6J=({3nJb5T+xORqZx25{4BkLyk}SCwqpbTfshS}}mZ9ZkXTP{@;ph1HZc{(fsg
zzkz_<-*~-vcSs@y+t!p$xQ;D*?rsm>R`ATc6ApOW6*u6~gQOx@EH5Y^(p~JW_c2oe
zLmNWJu|PQ?vy#+jv)JvbTa%AaboYhY<hhIyQ{m-Fyw=>3d<|^oavYZE+cR&?Uh#WP
z1`!SAlB87Dl_WTB#TC2WSzW#{3c>54)uqb_P{%N49?Zo%`MJR%M1M#J1UHe4dK08q
zfje-&u%Jl4&%%s1+MyIPkBq}L`^b{%{0vxWXd|EdJzn5P6FfusVeh?_riQ7Ub{}D0
z8lc*YH-=|yYHe4sES<Uv$lKmpJAGlCi(iLQV`HfFWMMIPJ<YfhOWNTZ64MvUe8>Bu
z=UByx{?=ume+l^N9l*vA@Y?0$&!7tbo*hoG>`>9@viOwXj=N9S=4QDoXXX9yZM0Wi
zyYuTaP6_!}4+8Z~3=n1tqrR==PI@W-w`?!tsheH?c8`FeR267^rGjJRe`bJ%g3PM<
z67*(`i7o5HhC9g^umsFDf0+Bni)C$C*Lo#KFbA|V)<R?0dyX^GbVf~`d>Gk8x^?&A
z3+U}>;(JEnqty|+HyK+S-M`3Fm2^2JVXgel*z7+X;Ki)2IZbVJ9`yk}Kf%EH4z@#5
zvc?9reWk$*ldS9F0#BefKRtst);gEd(OY5Hl#V9AQy;&UI7*|%6tmX#sZ?_Q+CvVY
z{99D(gQiJ?lI4^k?5*<ephz#DAu5T==Kguc=NM68_c_6|=}DWhMln@MQbQzJjYq&3
zs3K&QMHnHQjdi93=L>0OM68eP%_i?8op=+ji|+E6e-*Wnp=sEiVq+3oEVYOZ9?)l<
z*;P`ULY||8#aQ%GogjOQ{SVrmGo@1{Qf2JGzwg#(?Oda1Zojv&mE~WGhK@`L*ze1?
zH@=rMT@sx(j~Y6kFNMihe4jqM)jxLa5F=0PiFjBhthpcL1h%fcu6MPQ#&QdT0i@(w
zfJ-{Z4ZwfS8*;j@8|5^uwWK4yN+?=nw%&EfTjvHGAHYkjw_|nLEX?k%+i$tmDTuIl
z#0K(pA2|O0nHZ7O7oRh}O@nf6wdS8bJwOVO{$Q>SZ{gInB=X1~61{Nc9+5cxCYB?a
zDa0jo>Z(0UXT)YB(~<k`-<~2}h6{2r82xA{L}EsFglwF^vG)!s*^e?jcD$_pUK*bV
z<h+!LjrdC}ePGYnGOEzxXJK@zIK0d+q*K(=J*`f-HDhA6ssTuR>*EoFGtU!H<UmZQ
zolLiZ<FkmXrGUh35SuBIU95@!(l%-{(iX`k0bA6(ZVIz|n#>=P9xcn_Np8P+TA@V>
z*_zc((>50ar$AU|A-{MtCh>UJN@%<OGy+3|NTHp(lE2dq?e#T3_wk&}1O-^Lnd&u(
zmv+e2CvM;soN9&Dh2rxy!CD^rG8^b%)xl^4DFpvof3?8J@DlQOD}8C30}Ycpkalxe
zQiZh0n+rN*z({Q-p_&E71I`QUdV`tTcrqd7PrO&}nv6>}N3AG|BIz(-4L#duHhhfZ
zrO!IOKElta8q0GCFqaWl-eA+q3`LWpDyW-75zB-y`u0!HGx-wOiY24n_-{2ier+Xz
z1$hgg&O3zr#np#RMm>5<+2{{RMT-@5glNA^O0r$yKaq;|pD!vTiy#rFL8Ic0gULaa
zrDSBR2ySEviiPK$XkEB%>dA?*M)E_%ft0su9a&m<R5;dUw@q*i3-0-Dh^pElEs0c~
zk05hLytC9z1!{X^qW~Rr0k!&#{le)6trtRG0Okzod;tSd6rLJEvcypHPBu96t_B6D
z!2{2<P)x)gE~`Id(TrF7LLBZYBONbZspBKoW>Qs^P)Hst$s+J!YW8t2Zta1~<I7aW
z>0p;Y)K1>0sbrfP=O9=Pr|i0Vcr9r9Q?vX{uD=@T5)%hE%7M(&+U_n=0oD6?Ew#M%
z{^nLpFHG_s<=WF{@C*~yQN_sxq<%H5=?^Uan(2iNd(gWJp0+WP2rP&OEV}P-KEr!*
zV+N6ca0X1L$UqKwP17TCSMei#j|!$ZhABd|{KTm}n;=R$z9QDMj(o|s_yqf`Ba_~M
z_C@G^(wlA8%PVRSKXD3Z((C_TUB&nJ&W})>whXPAeiWzQLitf)01FC{w<+C0_?#d6
zf#@%s^UiHr^)JSULRNYiHlV#B_<lFANB_8N9c{ZgKJDS_S88c<3*hMJ^sC4BiNIE_
z1}mF`sX0o8X;_Zrg=Oz9GjosOey%{kjCl}ncw99x?wrw3(}kh7n|q?y%VHl4Q`~7_
zes>=EFz|U6lUy^DIIX_9l3T9G+QtC!)o`%R7#}77g0R>~8HuZ1EojUxELB|4Y?1s)
z4Va+m#o8F9xB;WAc^RQ90bd_uF-S(^xKQ|pD|A;G0A4oQl@aS(Di;ih35fY;WIo5q
z_(NcIb2g_b!Vh6yL;BDs84!hUMVj3-xs77kMS*3MXRy=y3R7^;XO6<T>NPKoQA~#|
z4Zse&oc>Q#W3IJh9V*;kG*wDP2*^~{io~NWez!wDtoH132@!+-e)dCPP$&9A@4`_C
zT^G2gA`n3<H!~Dmd;&<^ga9-9R2o(~-^N3?`W6tn`EPQ$PytLfvLQt^YUf)hV)s!U
zN;Y<JN2u}_LEr$hzi;@Qv9SQ8cRiJFj)`_M$VP`$>yK+4<1$UCPP72or}S65Dxo_D
zzBWckoz%UoUtAOfE)QP}t|w{3f$zs@?d;-?yfElT720<yM)2EVewEv00{+Xyfw7k>
ziSI~vhKf5yutL?o3o4yUABN}g=(&IZ)bR>)Ev<@4uxgZHaD!-gL2*YhbPU@=x0cV&
zj#=JCQs1XfchJyY1s_+fA9Hkpp@ak4Ij0T*xFlQOr`i73zsiKp2lmYXAbfW~${Qyl
zvO_{>_;N%Cx!(dk?F#kDYBN$iz#$}T6s3ojZ0Gp5<&epli7+aI_;7@98z)15>4^Sq
z?D$`u_K9W!=(Sz#G0B^8Cec%1Je%B=BzeG-Y%eeu0E}rnj{^C^wqd524G%4=4?3$v
zZDyXdWfQ&ctAuGI5k_6g(TK#hUlt=Nq!$;kRJsWb?tFsX5KJ^)O97`!5NshgoaES4
z*Z*ztGf+)uWO<uH#N~~6Gf^8IELP(05XorlZNwl(i0EEqMD92k56$q-Koj%fZ%{w0
zECUt$t(iBcRuHct<7RD=V1#M4L%L(3tD0mXZQQiYteA-DrnoaT>OUIs+u1a(`{=Ey
zKf+Cgp`j=$AUs=VwC_w4Jz>{|c4h+f!3M6<WN4pr!km&GEH@SP`?1w@jWi}Wgn++c
zT3}#X`U_DiZR5Ppncz$;^1$6Oq{trOs{dEeY&WDmAM6mWNzMKs*QY%qwKmpf&=k`w
z!1@xki!kYG8o#eZ7d?_iDkIJ<dj9Hhb7tHr9MmL8bapuI=ku7CIH1Q92`XQAB4cRB
zAbUUFvO9u&+#^N$3?p)3b^5sN(`jf<jFgPJ=S7}mw({%a08fUl;X9?C+{}WxOp+N=
zI6pVOxB!D{nytYymR7>yHscH8c0YB9d);hw!=Vc(iW#wwi!;dyyEY2RNmd?&wIvMu
z)0)aj6+@bNv9HIrzhWI?H-m7$l}Xx|myBLS-VwXvs4NJ*s%OZeQNu*LA<^gp1blY5
zO8W+y?%0YQydl`Em%ID%crJU`E5tNGv^6HqdI_79;0l5W-Dswx1z&EhOYv!LF`06I
z{s$mr^lUyqUhs*y;!=~&y@5v#%44ezI@gqK7Fbc>oNUI`w0?GvUBxEYi1Peh9$0hB
ziHPU6qY8D{3)R!@Y0tJBOnY2CPOab^1QpvJ%|58wvlEiF3v&e>jZ^Pz*-~+jx&5@o
zL)_w79+VX20psvH4L_%TR_#%9#$`a&mTBa^*%Sygy|drUnE|Mm@>aeZ`(@Z@c?>nQ
zgtNHO9?^Chxqr8g+{!2wCgi3w2=@VoOX-%W%WYLlCbF1fG=`k-rjGq!G?tIpvG!=#
zgdWZ@Q$BFY4w6`Tiiard#%YfK%K2Zu&QT_H;2TOlWKAD}h_RYiXhZ}z=NwVTzu7Ux
z{S-^c<clS_?;d5^RP<REKn)IJ_U?;Mm10Pc`d#Fw2A<uoZ3g7~z+$5RTyQw1yO<<v
zIR{MnxJhi#jMzDFgBH8Nx``tpu3J4&RE2uRAL&u(B*aILjl5Z!YBv6*7}T<4qA2)O
zDb?wWM%jHT{5mnrZOVvxti1L3qwqoTlo{DGE!^G+1}vB&=`2mD26yN#V?HibXD462
z6ukjA+Fqxt-8-`EeY#Ig^!VJ4o@_LZSW!B}7P+^h47xF#A8H#}u^|z~B^GHk5}=_7
zrqRi|khCQ7OuU6w{Qz^tfdqtu+d}wQyyfLVF79<7XUO>^Ln67}Xy!$GIZ%BGqS}R-
z4PvoxIOHwRQ>`3#tvubD2af*hj^Yi7Q4$feKJ18}4Z7Wj>8wzd$N0d7*rl!qLZUNn
zWdys_%5_;#w$8fda)InU38O(b^EPUbf)P<-`$$i8;d(DjyUxBgqm6@H20KBo(j?(*
zqp<rsNJ4iiP<E-IH2TocYe>mCup?vM4~@7R&-ICpU`7d<?2?z!HXh&(8`ryaYC+$F
zrN3CAjmeKj|0|?OF9F{IL*x;q&r!w&V~Lr(F##>8&q{e0gSO#_u}%0~D9u@<x=l!=
z%Ep#{Nv(x2<svZfFy%wRi2grDn#%L1RLlF3)9-ga9@-F}HT0cSa|yM7;}>t2@p$=b
zshYPl=K6WwpexygrtqMMK?J|{i)Jpq>9JNLW2^xLHP~3@Z|nFVFBFKzpUhpU^mq+v
zjoh$yJK*!_1-AL&0{8%dB%uX&q0?5R>3u;GXF$|L_L2qe0pq*b^QOB$e~3}O8fL<w
zW=W7D>_?RXD^CgNW#_|roOA4yH7Aa*5Fw1P(^t+en>yf(wbdo1{!-H8KA`#qybMoa
z?=p#oe@ZeH(1<pd(gwdV_d&g$g0IWZTWZWlH^J8bWtE6I@P%9=uCOMdJfy+iLN}iJ
z*LcvjJ!T)1!5C*Ce>~u-`5jKH?RTuE&2fr0nu=hTnnIg8mcw$NoyHfv47cJ&nS-N*
zV?oDkpMIyR7VyNUh>y@7ns3LikaMj8aawA!$fn!dpU}hkSZ^-<%#QZvJ>5>wAtg<i
zfS+|RQJb`4Q$H-$Y~}tOlp<(43=`mvF+33CO8ZXUzU5BiEI`AcZS_ZsqrD*;i>G47
z4trsY?9KG-*Ioa9#*j&cWf!wRV1x<t2d(!!LB=ddm~u^a9=oFEKWY9WvBpzdL30E?
z-Gou_AyssUn7F)!jKK1q>i$8q=sm10Z84_zl7d&6Z;~l>FxIKE_$&=y`Jsm^ezqvK
zy)95n+EoQlqVu1TpptwD>IXE)3v(w$@aKUA<{;KbaK>f8#orDSaaio<w!iLQhZI|O
z)`j9y1&a(!M=ui-Hg5CH-YP91kxa;(6Ltxs9*YmaDDwC??4R_*(K#!W6^zg@*e&x<
zp*p)k@t02tZKd?VU)N;97)1;@$hJR&c3cV6{5QWHM}`ewc4OZ~i#F`*odjYNw+$y;
z@H_0&=#cNgJ)2c^OAb|_1_2q(PkV~in~l5i$^!BgKBt#^c<+c2bZ+3)8l=R-xN=_C
za}n9*<;Z@u;SjIPX2$jTZnnK^ORK83!t<b>X#J{I`=?pWxhVixBa0DeRoR`sktyb<
z@{GTDgu!S0RdKcZEo>oDg1`kBZ|_NUWHwTGv@Dx7dr-4wj)g*!&<X>?@~;hW4WB!+
zj@K`ywgNL@qo%WOd3`fiiOzP;+esbu4fM04aRn*0{{`{XJYNEv74{z>tO*?>J6B!Y
zL0sF;EQPx!jN(J)NhTkZSt1<=0a_tefhHx{m?y-}qwsh61Q0nZ8FB`f^@{eUMTVrk
z$7uL8zFC!ISod$Sp%#wSmK2X3xHPy^j2h`&A>gi~AgM+0;qYYT*orpx@}*F#`&>u(
z!5)a_F$K>qyo_j?mf4B7UF6mT$<<x$H5*i7^~O3xch|a=<43N5s(QIOWJ*!pYY<0c
zorZT-^CU9xZjdy?8h!g#7VT2&ZzUG#JiL8SDzO3F_^ZRlA{Ce8j|1{3-s2;p&ZR#z
zwJ~ORPZ8&X+m82qpDV*UvG@vRwLmwBU3=}EL*OGQr_OUR(ERz?Waes^*~kdQ#*MfH
z$A2=gsmcnn|8&ik6$Ji+6>mW+=jE`C13=B+Bz|Rsxks1ALlj$5l{G4Z8F!fmt*1Gz
zNN)c!risWR4%I=`5EQj{m*#r+SV<q=Z{N*WC9^Q3;}|2u1W>N)53a2dpl1k_?pU80
z>cOkMDnU-G>748{y6;h2nG8O%>)kI&mtS%Alw_pSgz%6FG2)0`@4c3$Qvl=v#yX{v
z6FGN0=BQ^{G9-AcJCnrEBL+kce(VkUPVzyAo$ZS}rAH;<-m|Zg6tluvslh!v4=hH{
z=+n?NiMay(YF1HKW#9067BrsVw);Rb+ePota@%`hRiq|qC&Y1rE*RWeRpRXA?>seI
z6Z)wh199J;CeLHRciKwUExxBsYE1f$)U(DPN9$|(my%Xppbu~<T&#)0Hw@@!LCi^n
z;bDj&XV7Lv9#<D6lo?eG_{M?rrIQQMIs;5tJ6l)Xh{9a*2RO(XG)p}-TjvKKh~{Q8
zq;Va8z^zPNY=vtRx{G~FkIebn@0XWV$+LBadpVKH--vBar%v`;+QZ%<SVN35{)8z-
z>My+uls6gc^E@?R4;388mXaw?Qo^6c?XlC;E@cl_C`u!7Ke(71!diZ<ts(ir1^|r{
z;6u-lt-pD3RxkuFq^CvA^{gNog%d`i%OT9V*v$!{_AqGh^`zngYIZR0{EE&3w4g1l
zqA}M%xWZhh?0t8?Hol?UUVS;L!ij_FL?2ga-)ZMMZN={gJhDY;(+q~4{pnTeod<st
zv=nLmCbVFX{2Vz<lzt9ciC?qJ6DKd&qFUO+^#n%=<oP-L0TVDoSD+B2{2rXZClmW9
zhop*n-hDbd3P<1Z@28pO%lA~3)6#FJqkDpR)0eyIe6q9(76N*f0P=c=zKik9EbKaf
zE6_(;(i?lW<sXI^9f|R4^jhT+Ng8K=0mBUe#N*%<<J~zrJ?I^OP&rXyX`wBE@WhB=
zXdikua$`{#>TBi<+2Qb0^*q`Z?B#3R9r2K>=EmB*<1+iiM?iflg4uX19hJ<65~lTw
zud#uwks^2=jVGiJF2IdU;&7pO#KOiNO5bALlZOJ#JwpKUCvRlY-g!QzC2A{S{L3g|
zgbdIY%;7%lyPxeiuW&CFq@=JIvQntC!X{XIKX+wQ3PI-mh4UA-#VVpdb+Q;(aHFo?
z<O`!`N`g&4*x!!i$+x|afW$P%%c&qpeF>3X60ESu->EBh5R0B5AvpfD7TOKmU<sa}
zL{gpW2ELA}N`?s7N8XncOAQOCo^QqNu9HpY0U0(GSDeDB3iCR9x1bufHQ9-oOB=!S
z+TWGB!%9S6^=}(E8l((+9WnTVs9UWGxF5dK{peE5w%Pzly8Qyji6pQiqz&HpW6Hh-
zt+nR|1e?IZV%aoDIO{;3LEdpt!ILj8B@&|daw@6%l%AtrE4@9#W5)G}vDU2!7nu>O
zB;NVRh%J*sSV9t&>%WTZQwKtOF6ounWHasCOID1S#>fqn#c-!9IC8*!&Y{AvLV^<X
z$y^dc4iu(v!L4;(BE8Rex`JLlnR2=-{8GWVT!*swn=UBmNVA0-iWIiJ&cwQgE;PDP
zZi8D~qaBl@HTA;;5ti+}p$9fqh6nEVF%~97(VK=Jg|Hu@+Dj&+K97lUsAZg|Dp95q
zazIItwS@(Rh@JB(V_3$X?H_<+_}Ow)0z<s_p8NgY4klG#eu>zwU<aSZ`JyLYcuI_C
zwT##6%rshs>};ejxsth6x3;uarG}!gFjw7i|87zFP{@xsYG_~(M#r+WKM@Q$2)&x|
zPFm?2=IH)-ay?1B0`JAMwu3nOhn1DiB$>y8@oq56;RNx|!p>|U)M7elMUbb0yy2N*
zDW6AJTvH%%D+{(8@D)66uyb4hYFh#PQh_<pPtN%V%Y=F(zrQv)2XJ)G2m?(3ZpYpS
z+2oE3<P%mTl`X2MG7b;1R`8jYk*dYzY~;{2krnON=c#vevoX1lZ+g@Rg&Dl1Qp|CH
z+|RcpnVeUOg19-%A%<760DI2uw`QH*F6#|*L`iA@sY>oSeluG=l}YaV5gU_bWelwH
z?%)yH{OpGB2x^i@tWtefJR8L7b(fB`HGJlm@VuHBrsC@{U5{5Igmv*4dV6b~8KUFI
zqA(td9+#k6*y~1}BHHPtuvWg~g#*S)U4){1&N$0mIch&V$Y8d<Pn(r$2H%G~7sj}q
zvn-tRJj6mREVEKeMih*W!MJ%O!nv30S}vxWJh)Ek7S}t1rv8;xBS{p{O4x|W0()h5
zsNrsC><$6S$jrE=f(z&MwZ(8?Ig$EGxW6J0UpV?1ZyJLcMGF&-HQ|U{)Lh9!nw=t6
zpXa^wW>3=l07o+DDG5r)g<Sr;LyEO>Y|@dBjr*V&m2sIsH#M-T^OeUjV_*tOnw2Or
zFntxNZFdLIv$LvO-et7<uRxx;W<Yi4)its4Ah&N+G&S*0dRNXh-RcOKX(4j?BP0d-
zv{xfd=dXFXo6WhXg?xqHIC2@69!r=Cj1zF&wp;-{!MsfWdqm4Buq`=ImfAtSrS+`1
z!lEnKi9VghRHw*k)p2TrO9HZo*U7VRxxH~!Q340$;an6r!cwj%f+hnAUOL4T#T0;E
zyn&(lqeq>R4_?YiLp|?UzfHbTTu$u}hJG@BvBwIT#p?T^GWiV%MH4bl@Eg8h7S^1p
z&*rizb4kad649R!sd+&eC!DB2m@YS7e)Tl>IAzixqmL^AP+=_xAjfo$9fC_N!aE;2
z;sZ|ascKDVkz!|PgUHfEN7uCt3wSp+@jJUD0b3DB#a=gXT)nq%w`S5dW4JE?Z(b5v
zVi}p=z>`OEn~s9^G56Ph#}guan?uS#H1D+SF<E2&(Gm_1y@(}97|isBx7k#Rrfp<@
zNMm(yU}-Zf@%(@TCGjPG2)Kqa-a#+8%{D7mG}QLPVNm~LrZuLQrYbDQQ~&LMRdEjm
zu~u~&!SaB~42V?N*;_JMr>0QPb;*}ecAc(Tb0hfv4ZVz64eY;4MeM5X^v1+7R$Zu-
zgH#0@Yuz<_iSz;Ds*@*pK9%x-W?_0G?MRFnJgB_A<XHpF<bxclO|a|nge2OL)x;sA
zMjJ_4bOg|?zrXCMA)#MG^_Ato6Bl0u19fO-)a+57J6-!fNVg1wP7D`FBN%6rp}`SX
z?Y-;bEJ;eqo+azNDiFl@{H=++1x5P~84Ki7UTz47I0~n#-E=rh_F%Odv5i-^$0tmR
zMs&Kt!NCkA76Sr9hVZ@)82IVrRI}8tHavPBI3{91#4E#Bn^mLtVnf=C9-l;^2M(g!
zsX!~!6W>G#hUXcj10i#;I(wGMIdk{Mr;v(g6N2Rt&@VkZ7WHFYH(2l>B2!q&e#ZJ;
zgvy<a<izu!<JK&&-${vH#R8VHY=3N{Dqgpf#UFS}y9Bgg%AUC{OXH$(m@X_J?fXU|
zGr;@l!l1VE1WhkI#f_;Qo7&1%b;LoVC}Lh*Ny@`cz_};sZZL0@po_gLSRQ8coD;!P
z-H8^#uDWRE+>~Xs9E84u+g>ePsJk?XZNj@XsJ+C)NvUJ#ODmeQ!`d4We|+ZYuR7+S
z_t#|7Uo*2S`jzJ|(k3d5&L5)arcHEN{I!u95COa=wk)?L<ZKFgtvfk_fY^8LKrm!C
zq_di6(qKeqaiX-29ZFKYzM#sl+k_K>#@i|O+{GY=f)c2&OlKM|*+=o{udh<=yR%%S
zyvx6rx)_lQUBCEDNJ&JMgQ5B*O-o=Vzs=!{kmXSRxq`dTT>`eux%}&$!~1{H9-ju)
z5l6&&i`ee*2`8eJ*W?^0YZ(P2dM8xEA4r<2z~#SoA4m775S@iOziB%<i912cr-ZJm
z1%f-_{YA6FuC6~oG}#Og3G_|u1mMuMi&m&8O)7{6&HgKk2UJj!1HI5*u*DUk+@EkX
z+%@~@a?zr!%`A@hc*Z{tscG*8+(s}X%h&_WI~sb6UuPWA3u%VH;-Mm|E31g3XOSB)
z7lY5nX`X>bncPlNpaDj4$Z$ekN{iP)GKF4&(?5T4yd}6!5NWIqBMOc+<Ua#)7(s(z
z^qCKgQsDdxdRw(<SwzmSAr}=TM=@Y6D;m2Fa-|!G8}hNiTb+3?&0IWsb|^LuwkVnL
zUJ$ZK#?$YuvzyPv-vnoEZJ3Jpsa<9vzCh*3qN&XLfGm>?l84MS?1!bg^7t9xk{M=N
z729<<H_)|ADoEHzwK$>tLbl8RcKs~Jk|>MfI-5RISDffB!kjVq0##^ewbOzFAJ8a<
zMKik0Zyklv&{Ph{CiKx&m+Is@n44sO3W$MrluG2SIR%LlMhy&6pv$qPHCXC)uFhTT
z`#@G~dmL50(WN4H(7Tz2S#R0Com`fX8feA0H@riy`_!A?D{v(QRkB97R73S)X5Mj1
zc-uYsUAhvhj9Yvu^+;a`N)(UP(9&R%T-2A;FFC80?OzN53RNr{4e4}>ToQo=FM;?+
zx~B{4_moJ2c_L7Ms1;}Ph+b-?(<}u0{EHmR-#WWOi?zVJcz01d=12*V2ILzb`s^-T
z4(<55SnO@o6~D1s@BHb0rce3euJ%Qp1a5lFyt&(*C?ExMW^FAqS_%R=-1EY~#lQu4
zb_ML7)a6?CwvQ`2tt!N&faGPRxAev*soYA0S`mbzzDXi`P{XD99@wdWo0ITV^3N|g
zIgO%W&*wnI$3?5PYA`N`9FW8#D43l~*qprz1FMCjTf`bk=qr>3X?KLOfxm`ZQZt$w
zj}2%G2W$Qj2xuO)$vIShwmy?UVK+8?$+XUX(x^%Cz7Y&CwjbN`21hQXTsDc&vZBOq
zwy-D(C+^zre|RLAJwmY1ag~-?J3IfdME)hl4Rgv;&iHB8@0ghD8<d_X@WOsSHM^Q-
z&W61pf@lP1$=4K7o21lV+vt+<rhT(9^ncg2KE2NafSem`jLkfikiD()nqj)NXA3~P
zdW%=q_kj5dV&72gS)+kI=Hl>aBG9AYbx1V=akMnLNj@sFEelLY>57LVj_7zy<ieQ+
zGN8Ji{LONWc-n97Gx?MnwzmNvO{>Cnw7U~KRmb0j79_Y#edy4dUO%kF7GohXbbNMK
z2I88l;lsmtTIA`-WYfNNo%xdIVfH%$^B*Ti%0t-)`DD_%t3uZ%9-RG^nR@@4Nyt&}
z&%xLB6{9Ov|GL6Tocp_HuFtGsN0R!d;p9zU79Lx!aHN-0mgVasVTZsoOr7TgiJ$9*
zBweRoVhYqwF4cdH@Q;<^R{jIyL7zGY!cm6H^7!?P;RFU{PjcPT_@Ub16Xpi8Oy6#v
zi-L`9O(XvPH{!s58e3f52?D6%mCzX+a}lMKFO=N%OkUxQrX*-dv~A7FK4qPJcS~!e
zL3x>751iceWIbT<YH=KNnY@>pFMS}o#3N<Eh<o}6-(8s{`P@!n8#E(aR=yDAKD1Oo
z3y8nkjpd|ZXi+s>;TXO0{USwa%M~M*fP+RSU~iMu`)|yb$Zb&l<OXUZgzU*;_Z59I
z3}{<rrzz{tPT%Rbk;Y`M`$h@s?-4fOj=Me7_Ga=f#d(>Cp*g)!J0Gs`0nlbAC#M7i
zOvUG_eB=8pn=}T;WF7G*tokKh1_uSom+_RHfBK!fi7cJ3<@;q7<vLy1CxEf2@#9+E
zny4XY{y-<90nSZHr%+-{1RZf+l1Ff6r7#H&Nn>BVxO0xl1*9Ec_K-it_l4qBGWgpe
zIX{O%W3pnY;Iy=eN&oj_D7fgXR$)oQNnUp!<7rStX-=VKb#T8ta=@{RoYnBGPZ=DG
zw8TzbDc`uSd^P@Gb>V+G4%CU{fVhpYA?rj+X@3r;O~UBT>y~*M^+%eD3r}4Qu6AA^
z#|+k-3_*oIACmZnG~HEE{ls+Mm^_63z&iQIe7A1%J$(AfI%&Q0cO|iDq_K50rj`Ze
z`7$txXOTAJRO!EhQWCA<y-rliQPDL_b1QoaWyR?$rOZmmq5i{bb2Y$M8GNt}UOgWG
z6gk)&o$N1);Gj?pZO_WD7)RS3jL>sj-7%ybA<AXRmMK7k+1d_g#_|=7L8U<bA;Zjq
zX=qd%y+(w0Gi`%Z8X*Qzi}d_XQyd&NB)RzjC20u`7r6F)F0|Lh@gk7ysyHXQ+c8u;
z9U+z=Wk)oRArKP_2oO@J+L5vd0u?TygjX#L9b6Xs9h<8VI9fA^2L~2pw8^j&DcAaC
z4RGWa^j`ZvHC4$n7f2jwUCxi9az1Y{MP26j3|-OW^n<u_(p)rnt4nnb6|MfZCgWq(
zGW!2V$f=xnc|Oez`MthDYCfN}NQ&&{JjRYE<6e<byWP)e7|X+EFMEUZO>p{BwJ@?1
z<t^-V)6o2z3gd7Jz@}OW0}G}?Q@Fj|7~hE5IOOX+{musB^iiOZG30dp9GQhLdjmh|
z=z}p)7ft-v#fjJrpC{&*$s<9E2sgUGhnV{bvpF$%DBOc-HNTM_7y@5Qy743Vr9i8V
z_^^b1!XDM`0Qm>W%Mr6l8tafOo^h9WZAaKMZMDdpT)?Vv$2rFMV*@Q&%bVY+>8in!
zy?%3JJ?Tr9xAi=$nCD_W36r*39ReASW)tKbF=m%X5^LdDem@WB2x(zHqv^=A8YMS?
z(C2(G*7d8-JI791;CXcDODPkWXGdm|4C~ada=;jI=y+U@<^G%lK5P!kZ^#j6C#IMO
zHcxLI=tl6PcfWAj^0PY}Yd35JeLqDO9Hz7mOuN2F6S)}4T#hyg24G)7h#sVbx}~N$
zt_~GIL8tl;#3QU2vkCFWZH+F6y~K<Sajz5&+H(TLdy(cU);r?mxfV_)ce{I3EHv0G
zQXtm?9hz245jYa)SHTa@sChaypmiMYigWTZ4mK^!(U*sdeRR0lZXum9+&#M2Bcxb}
zUt&x$JAK#}ta`%ibAT2HM|69Bspkf_U3hsZPM{1Hsr9w`Nu>@2dobTvIE-M>58_S)
zw3JU!UA9^LX$^`cW&i{c(W6`lE6Z+OH#2#BJb<?wgC&A<=-}cM24qd@pYGd5&IW}5
zS);{29PGV{{iyQ?3eJw|T0*x^EX^E(_v4jaJ2a-nvIA0H-vnpSuuT5c^E9KyrTyTU
zAN*WN^nFMaIbF4XhB#&1`pmWnzK`MzP3jH{f4Xe;+)U5UlO3`^>G}d0X=PEYHvL^1
zATJ+6Mc8*_3j^fX(1t4~dt4y*!Ef&HUaTh!q({H1mocArL<B3Iac(3QYjAGCQDbwA
zDpHy~U&oySOxOTrRGP{t4~euw=3o6byAr-2i>QV;80INr0eMM{r>+S#0B~25>n}70
z@vFua`lEj#9P9=-dyqhLB7ztfBE4?%#R=7`gx`CJZv{pmildM8xTs4rtAoBZ*bW2g
zm#e){8Yb&wEk|#Ci5uVJK1R9bHi^?F(#|?5l4MhsS)J?x-6pn#q|?eC^S}F4=yRef
z#}74SoFCyGv_f2en?SF!7SF<M#W2Ax9VcZ?MN)~tBY|K)7&wcR11ed5+=;B4LuOC{
z#qtor_7)2}HiJ;>SzjR&%8M&b59(c!#}Q=MKb||HHCs%J={uC6LfZFO`b~qn{bd@j
zlh32hik@#P?yrQ7a0d$}^cy1d5%#Y+f|3+>%HcQ}xMwnw(1d&Nmv`ed7g7!T;vzp?
zRW?L&W7ul^ixvfIGHZ=n$`i1Ab<wo&nZq{a=k})l<Vs&Hm3laZY|opVS+#_#TLWPn
zKyDCKI@~?hD31YzvL%q;2#{FA`OhAhn2DKmuQbeCYBI5t-ejKf-tc&GXK8$f<WP-M
zyqn~%md=GG7Q_MGesru)Y3Ckds_A`t(DT74Vf9u}j`ode{*y%b|IFH$?E{Cm@4fkG
z9=Y9a!jd4qLb75}fwX2{{e#EfL{K*oLv2rP$%da_eBoiT4+jNi0^-A|yn3>mu{Su2
zpP9LtE%m37t5a*3eI~GR^CW_{hwriS*odaU+XDK%Kq}2T>h&;VM$Ws9*bI?|0OmPI
zn2`Q#2v&C(>C?nQT*mJ=-2Vq!>oN>MO(JvU>4o~^&2fzKL}{;Yy)OgPa~<dO;;pC5
z;uV+cfjqf$i1sa_uo4TRDr-~FD|-dWJaoHzDMifov!xV#nZ>!6EN7s%k-IxApV3rt
z3mZl%BF`|uY+<C;6IE6R_#o%ZZuX$^8HSIm0jf$jix;F7Huc|{DQZxUf2F*i-ZWxP
z1hVybd;AJT!ad-A)ZFm@%`R&OMSFFRD?D7HZysVr@~z3<lN4~=aW71d`nyPqs?Gcf
znI-0W)RaWx52anuf`d)TED6$fw9r2Z6?K+innGmK!F?<;-3-3l&g_t#qS&Gp*8CSt
z$oJ20^ks)#z#dK}bj}Cd-Vftp#C;hU8#m=`_EX~JmM8x^)qoAS`#%|a^uuKetBP8-
z1ux>S4l}LK7a1Y_qqbm~wJ6<1<|ZKg&0lhu!gHD@%QLgOJv#9o+^>&`WB#vJVsaln
zx%^rJj;_hrHQC!z84i9U@qg8!Lwb+p04cu)0srYKBS?~t&c~N&v@XkYBkKBf1a>c7
z!gOvX%>7%FL76?IP&qbqP>dlA3Tm=O{d<dX-I>Td&%5(f_iZhq^0W#9yV$O&H`9Z`
ztTClK`ZMS)P9wQkq&>~dPOaezADfA7Id(|uGP)avuHuqxCX{gw)prk>w}FzN1}I`Z
z-4h1WK;rC8dV(10uoVnHXiL((&=jn4FZRzbDNQ`#CtmrF6Bciw1$CQtE^VvQg;W0t
z)Y&gmkw<dHG%wh$%0tL|u23r8$b-5QW=O9NcsTp$=*n$2QMO6~<Rod)>&3<&k7GtW
zflRq2&|Gq2&fh&3b~y&s9{c1X|DL=WPmkzIs0*Iwz;my=>Wtd9BDT6O>%|p)s(;do
z!6qFYv~e2t%eG?CUB9NiCFt;R4EvIsUt_a5m!=axHYexPt1>}>AvnR~8jIuh#Wb+l
zJt)m0A1vht*roXnz@4X>%;;sYhQ;*e)@&(-yt6_T0WBGT(z+I{dyn|J{Xk!(kiI!U
z^Rb_*oDe*u0bL-JzdYWwJ|)?FW_!8f8+uM8)!sM?4O7fx#=Ut`|2&_r|J5#L^1gIq
z;Y7FJ5Z;HFhuf|_=~v!hagOzqa|*be_;C<WpQs$IqOte4hOH`%pplJ{X97kLv;3KW
zE8XD7*y6mF78ihekJsQJb(mxv9`N^<?Do@0$T#^=Yfu_~uRQorO??s%Tb)*hOAzm{
ztVJO|5>&O7MX_l<Wqi&Q?T<mhQRe+SC&ELl1X8C;6f<Eol^D0KqJ0Qh;c9PtWj;5g
zPw)U<EE?ooKWsloZ_m=KUU!eUJoOUmmdgc>6zV-jvW8M5!ah->Q+mo=5}zlfWjTxe
zyMBq<KUhduj#!30e$5yUHWITLF5aoOBaSZk`iDXdPD6ACxrhhVfcy%&E2LjnhYr3l
zu|LtifM<BCm8)#;yrouqB|$LWQkw@GCY}yu2sI)4(=~q~E1nu7JG_z65i8tSwYLHM
zOWIh`i!w{!Hp)8QrYZs!WCCP_*rRYh-P3qI#pSlB9}{@~Dl1R=r5)d8Kp$~@)&~6a
ze0Ojc*@@Kp7Upzu<9VCw1%#{BddIDPWN2<fwlC(4Y8N^`F;SD4(HQ0q;s!z)LB?Zq
zPw^@eTWLU^WjIX;n2fisq%GA>!XhjhD6MPbRw;*^WmkrcQD9nGdFf9*CQ^^ibIa*O
za|yC37o7Y`jiV!%p@0x%29kg_6Rr78^o4~iWFr7EX2|EyU!9=k7M=d%EM_&12HEP|
z-r8;Vv-ot}_@yUU-UuqCGB+ISbwTl4P|{U6Ao#MrHY~f=09A3a$jbOZlsg2VD=B6G
z;hzCfUC7TjN6(HZknj21%cWjia9%y%6K$7j51tx@6q{LP&)&0Cr*kr24-hmG%nh+q
z2XM*Sf*FEz3X_kT2TX@(*^cguJh#U0&L<JDo-huAW)KF7F?-t}ph-eT1jFK67I}P*
zX67p9V<fq-#t?~a4-?)vBt!Ug1$B|K6AO1IHIQN&yPAZDM;k9yT~A`3twTY>Vtu~&
zo0rI3Rp3N^pO{{`XN|DB&`D%DIR0z~wjd+;X5RRLT{vs*&>UhSz{BAkT8|R!^=zNg
zvbZ-)mE%kV0P5Rj^&4Ioi|;jGTC|T*IXpo$0)GDQ=d{t5!#pUt*YL%iRZFN#B;ydv
zLA(O>O&#yO#r1_+G4ZkB6G^N#a;uBtNtex|pNR$+bi9nOoK6>v2!aBwdco*Mjm4&Z
za+%Wsm8;S~B%(p4Dul_$tIs0{RhW+1a*2d2k*Lk4i6v&3^r)plkd~+wgAcxTHh;_B
zKlX#VO$6_H@?Ad7$rqHBS7>ThYXcyc+p-dIABLZx@<WiB!>TdlesaHHbGsp61t!;W
zG%*=$oP(=1o{4r*+R@e=acFfR9bgkWt8EkD(95Js7h?f*+T5Le+@U(#6`lqCwV4t8
zVC9jP6nWCSD^PIy35dZ4@ra)yD9D3!9E&gkc>C!|?*5fDo<I7dt&@NI_{q!ZBLm_i
zALBX*7C6&XTZV#NL^fW2U_&Og6;d43Vs<;q=Jd%GmqOalddOTe5$paa8Ye^Fw$y3=
zVF4p0B(D6sHP&ae+GS}6UNtJt>hT@sXX1|J*O)IivH&*ZtSYUybfVfHxTMfhUAN+y
z%Vjv^WV~lq`1@o@tWPT`&iF4X=yZ2_eaR+=dkQ&wai0kL0ZCd-iMjnf1bTecsT63W
z4=nneMJhg}f_Op_`$&$fs5&qsZ7K*{w8x|?i|2MkNGwq~(X_VR!}W2Pn-6V=Jz;A;
z`tBm=t3mk8<zHkJ6oL=>K^m>Wz*YpVEBF*=j)m7EN1v}Sd7+QocIqvSfD?>jL(!xa
zse(!7{M~m-gxFM~z{SyGEDco00H(b?OF;qYC*l9^2G%&%9ds2VlVjmP#*|;|Vs~fv
zng@qm+m6JbEnRrP!(eS=f(GS@HT0=4zFK!p&mRo<fCBYbVkiCv2Q4&`SyVM2vVy;Z
zIcy#qg8Gg?K1;#@bD#|u^}s5o0cMf6SJ@_^rHEy{3O|-2<|ni=qQfoBxZ@qPyR8(Z
z^FJDONVD>{0Sj$S99#wUjz&Y&H#hP`9B9<pE`ykTboQ(TM4i(Y@J1rI$N*5#Oyf;;
zc+Y`m0eHfsZ{1;wMA0rE_(a9=7dSH0Lp44$yyydVjoRkBc^|I}he82E4~XQJLp?xT
zd$8rfZ5F8R0|^fYrKR|Sr!GWYNi*f$*Mqe@=|*Rw`d|+XUkL4WM#skiR-`(J5d7Mb
zx=aEcx|cBy16b4gU|x<D^=p<v@3Pr1Tc75?1%FrVoJ<4L2bF?!31Xq#KK^2N2%6RU
zv>F=;CUvI7e|0;3Rl}K8C*L;JMZ+H|sb~DrB>@+PXEOR7^TLwX&aViv2a8<<(|L9g
zA|$bX@SoyMG6bhH^##0c3@MZl9KU?!C0DjW6Ff)xv!ZaHzt;>oU7+wiHR{a*?at%#
zn1@QL6=3%%3U}+0srfwvr>x$NbLH|EHl0#AJPhaxo=&gg<{g|(2a!_>Uwv9BfYX@(
z2G<R=bKC1bk#|u)#Tf!?gI8OSVeuCwIwOx3WLm&#;*^DE1&BTWM%ClOAJ#IF)EjI?
z)#$kwfKfB1B|NjNH+-}=)T4*)tnsxTB6#Wc4(F<2k;>V>NfRPx4AGE==egGk^RJB(
z4T=(*mP|&9@IUIQV|-dP;dHB|yy4tEz3~3ya0QoL%c)heX2OM@W_j7Hz2A%04U`?K
z4HjkK{vra}Odi;zgQX`cfvSC6`L(Z481%qGtYkXib>wx*{}Z<Q!n1wnhJUsnC%eXd
z+>+?fJ%{#D*5Gn;Zk8q71B9j){hO6R>S9chr)8oV@LZ(at!#kKb6M}N5|Vx!X|hl2
z8p#E*ypB#3C)X0_O6O|(;#`}Ku?eI@(nusj;Tl<((qB;<zngZQK4<+2-6jX$Fxse=
zQ4D5`12Cq&|1k{Q1-4QhyvEk7dT;-bX1doNBk>oVSrEMx44V@bC|*wP^aIV1op-ci
z+C1w(xGt>P<n*%@JJ)-W?O{^~$tpCc?P1#u8r?-%N1<F|aqzs|Ji*`yCC0Y_VXhyo
zY-NL52>Dd&L&%EpIe<E~$k3filx*uBuH?0pQ3(4!GhzIKc^?F>H5ax9dwKtmY#^Cd
zF0+mePJ#I!00wP3_LvlUpxhe|?S&J4QgC-(`h5SmQ$*y(g<^~yCoeSWt&tqjt0PkK
zaG0MV$c;46I8UY+1sO?j3j00=2IU6zBf1#uSWCr5Rf$u3#R}@bGhks9rp?_uyUnEo
z-Qw1++V@c-j@&~_m|-stoO)`|R%C3?|HM#{*v^8NMB>slxldWC*6zEVtI);fV7fgW
z1u6T?4diMpF3$-9>w!8SfbgpIZj3g3w4C%A{U>60ib%g$A0ylxULsjJ@rbZ4qp%4F
z(bX{5V0F>AQN;3266IiM!9D#eYzZGwe}XcR4}KxH&6XQdh0{a$EH;~#XzdC8Kqhv7
za^mZ=-^revV5<!RkiG=58+!86Kr3?a(8W`ja~YKA1wZ}VLhHVV(<(8^g=WZvluE)g
zO2)C}m+;YaTNh1*sPx^S9c$SfrE`Dy=`qayu&kyC_0({`t&<%HY_zL1lP*pdzxW&7
z!zhUf6t`S#YL8uM09cUH?D*eO-2N)3{uhCCth138xH0acv%^S=9uHl;diTT2bl;b$
zUZ&i$X6*b&he)4_+6z(tAMxAJbqa{Ps|k4Y5PHF65Cw51ML868Yeta93{LPlI`4zE
z8!$V@7598g=^5Z!(<C=QqY>9aNk~R43uF&Q16dFw3dN$%;5$_1CmMr(+Dk@lmMXqP
z5U$54!>pmN9b+V9aXBDXs`qT5TD|_v2gG$kKym&pj|Q%h;@6yPy;)WfvXYf-+8^TT
z75}Kt!W2|kw>fy(+gnTK=elo^e#YMF@KrY@`H|6)ctzlA>U!w^1w4QihOlKLfhU{o
z;s##wMBqf3a2BzMth}CXW60;3`=n(By02D#MG){cU3jDYFLA@PYI<BfTAhCn_qI>x
zoD#?`oTNN=9Ja0jR+hnJJe>^A9js6Ipo+?}OfY=kuPLD!hk3_q3dAKXQ0?4+T^y$d
zS!7ie0^p-CzNY}GE^JCoC?}yJofu**x#RsZmH!k8Am{-2#O98Rp$J;<{T!AsC>_>%
zZ`Jze%54Xr-*9Ke$YQ2OL;OdEI>@sdcugVjj+Ym9Wq2K<r1P_pSTj)(xyieF;0o~V
z^-sM~l&&)oeY?;G;|-5AMhNVszB<#Ty%4a|#>g{9l@&Vb#AxNl%|Iug>T4)@Qv}K2
z@Qw;0(4zb$^;%?!we|VW0%hQ=@YUaY4H@z5=8gd_J1ejaZxt}+wnD~|miqrru%G(d
zOBFC*gD4c(Eowi6Wmy`qd+8m}s^5omZ_uYlwrWQ3_dC(G0ENi6!4TqwOhPP%hwdd9
zVs}PyiY#<TM`&~UTQ~eq#!u4i5h;c-FdFeblGh`&BfD#$B@>=h&wGm^VP<(npH)HO
zLIc_XF?lro7=KBcP>t2lsrev;{t4Ba<E8Z9<+<UfW~evYjX!r=A38pWQRj)Pcw$JE
zzf9I18Rnc*Vzs)>sPM})SYQ!j-;Wo@xgE3H;7S!u-w?{po@{20`fsyP+xsYelu30B
zLAd9o7~s?LUtDS(1i~M^Ms<;ZDamn5oY0sgfJO=KoROJ5*+yA!mAVPj4q<Ni*A-Sp
z<o|l@4~8Nqr5kMMbJv=bNpn|Wsv)RpfvlSJG?^a5Xw~fG7LUbE#qLbN*6*Q{-?j9;
z{$dNi>cKc^As=oTLY=FzIy@NbsQWLy#szqBRGBTnaN`1`aURsCAy@X!_Gdc8T#tE0
ztsRc4B@~$N@n%S^U?URzsplaZnOeCOHE}}`{oP;zR;-^}6WWyjYu6$>J0Q*M#Hgcq
z-qJrI|H@!KHFgqAcdQuOV`y=!9t@S}CB-;n+)~}NOABR&bJ1FYrkXt=6z3|fDETsD
zW3J1YIk&M*%M<sLj$n_RmjpADc2TC1M|BL9da&>f_kea(^q&bnfQ|@K0T~6BHwcIH
zc4%WRYAJf;UWMTdu#6eMF7(RuiLbsBY9=&wEjqMsDe3bZ%G_0f-N26CiGUyzMFe#4
zTVSIz_ha1tSheE1QoeKOB_792{J{rwr8uBqs19Fh%#lHBks5w6<UA`*%H4TFaL&3_
zcy08mW5fb1h{9V*|1g1ZGTRwVr7!E9!Q4n#*6zlsUNk0{ny#ashduRheaU>Ky;OdK
z#9?@2{-W|!h?T91qEeCdTNy<6in|r!?Dbg}M!n6oX<{Mz#Ic&i;o2(idQ-=`?`u}W
zR}iFyayZ9a-ULIqkr>gqYxusux5P)LO9oCuv)r|r#Up+Q)=}#&eBq!C<L!%>FG<ya
zEyI39SOJcllGJ`N&=Iqc*<sc(Nz=n^v&pbwMV-(vxgBt{&>@aXkIw_`mL`;@gat~k
zvNW^2T?>i3KEYdY^C(2;ysCULzrKGq4Ot!zc<IE+!E4H!2t&4|YUAPc_+lu3oYwM_
zHtTt{Fr7lv+pA6~n7AN{Fn~4ie`86f14zoTniZOj+s9REQAdTWV8{(w?k1nx;IwaG
z%y$WJcc%o@%+ae|`&AFNL#I1w<;SqF2`1asEbWy%ZY27TcCPoo%yrjd@;U{<D5q+I
z;Ggo{#j~I4{1|-7=gFL$bttt9n5ey;v58?Fs<XK~X2q01Yq|?-aDnGAyI;$x8cf2=
z9%%=sM{xM>%yM1XFG_s(=P(-0+pUuE^qMXvhSE074zi|fO}qMOeBn<V2^+SJIm3Ht
z;#oXPG?q3^&rtK<jZ)-A8E%&)G7-eQ_1@mC*v=v+`B>NpM`bS#A?8ZEg`0v|G+@2=
zXeX&hakynaf|g!3HSjUfhx!du5%bQDf9UhvnopUl5<kRwvA}9gcT)Wn+}pi4b$<^|
zE?&59L^VG{iH0EX(yH&j7PiB@9g9TKitL2uBI{SGcrk5p1zeb?2}5%MTgE6(yWOgw
z+XFDHpA;OwPS!>Do%<agprpV|?tlmGyKpKlYkRs<6Lc2OmD|}OKVxz@A7VJOJJwet
zCqal9Ew0+raq{2IJpGU6BI{Rk$pG#Z{l2(cc!%J8{Kq3*`-!uhq$}xY>03C<nLd9T
zMTzPP=T5UZLH!?WG#DDhekiYNwF~*JGxp!VrG@vaPAKoqw39;9hDk<ks8GJnSqfWf
zIEjEjo{+SR2!dLXPlk5HWXwx2<h?^O`;^3@cL3MO%${80g|`3HY+p2KKH?Y2(I{@p
z`S+i*19KzRxLu)TGyp2CM7)N|urjFDnWM=Sn<A+@wWl}rE}Hv70y#o^H498ko9S2`
z&FMYKu^@SPV|VQuy*uCIZ{|*88j>xNZ<4ZsrC9tDR5sU_Tj41G+tkUgmM;JC0TsYE
z&x$^v6d`tMCbU*@>xPWLfZY(nW{cY`m*<s4e~N$S)~n7@`xFsj!!{j*cdN;;z!utW
z;$9Fp5-Gs-S2F8iTXg8s^zHTeR17IeHg0TW(n*WfkKTgMsKq%zIr+>;dmN%BVdy>G
znyY@5tDt(JI23z^ZkTm(tYe1L(^p+>f`=ZyTs^eT^4>9uG#CWtK{W!onH8;Y4<?qp
z?gt^Nw}rB8X{78rmND+H=t}Oyu6y8Dai8E;bwr9NDR5ms;g>5;t%<C`J{}zDj}~Tn
zT9Le?#d#TJ+o0+-MK?NzNK5aCyq_4TF#7N%SB0<)&q!}4ki8o5;mmA7M_A8u^Ze@J
QU?mDQpj&a&5WTuJ6kc_4Q2+n{

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..d049a46b11fc1253d4979119f5f5ae098d243fc3
GIT binary patch
literal 52976
zcmV(nK=Qwf6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+lp=)9_
zPHYv#d!a=C)+B`?_APf)8AdEf6nVuUG;ExI54t4-B-`>Gkk*+<gtevE^=jXtT6Nf`
zX=5BRqbV<qTWTS@v6kK*m_vkVLZ-j;m<vzM#sb$GG0|Y3-+aW$3&+lEhOU;+XSSkN
zDNEImNFV~2AnBCu_iM)jPxXe3arNa=J*m6P<9B2eUmI+Iy&dyP%B$Jm({P<azM-hL
z5{&7ydu&{2L-xBgGxj?r_Tl{iq^zqp<Ojql(;N}^w#cc^FR-j|`aI^Z&6o=w1lXJr
zaL&H9-k>u7VZ~v|t71DtugtMb=Q0eLluD$P>@bt;;_Ie={$|fP%f^DMj{<|3s#3tU
zTk%`~U(DGV)H{YhL#rDG;Cm7l`+VPlkAdea$$Md&-EsB=RRT;(b*L)_92}0RP7zWl
zhY^n>wqF~q!E4^&pN6k&-uOnVYe&nA?%IW2QnclM8IXxGbu>H0EMBHFP2uq4DA8lM
ziX()xT0bNQ1wRP2hDEMZo?>ttZ0K!%`)#wV@v}nZXza9pQ|A?KwMu*?v*&m$$?Bx=
z@!`1|yDS=>jubeN{bFMCVuWjYnk&ugDVZLg!t$KXL>@$z3xSWM`Gi#!p|d0YH=db2
zO79ZmS7$#EC;Z(#=!M;iq`d|Oc>*)ggl=63^rj{d{bnq&a!83aH}=%Tafa=E`-bIq
z2J~evKdghjoRz)eDm@(Bab;6%t}P-2H5;$0b=@bC!k=of57#`K2lSK*;6SMQkO{u}
zKjAI7Ru8^Tpiym<BREOzSNVGgsSS^^I?aTJ1`#lm9+SVfLRU(pQuK@asGq~-`|1wM
z^GKQQih6p~dh!+@fkqYj20*UFg<l=?!g=6~;R#qAe1WywAzKK;FMrC~qk~|)7Dj(W
zr6%o)mV6>w`kipF5>H#qWB~P8!_PYtldXiMI{T!FnN%9XV}u>Xqq7yS+FmM@xsO(Q
z{QmuYakYhwVsk5j)`O>-fWvT}-KJ|&7abp55dl_mcMd+QFXPHBnS*QZ{k;5(`56qx
z`w0#pDU3!C{c;7#;`&OyA1(B<9|6!z144U>3hXEwy(qZur9Z0FJf-!ASHd8mKs?F;
zl30L6^SZq<ZzSlNv>*~BT}gb+EKywlAI<O&VjY-E2ao5=-1#eSSs2Ne5wF0czI1h<
zkp(;$pW-4WWKVUPDhkR$1Us$~Myr>xwDBC;!!mg->|mCUdd=NtwoJ<2t+YwylY>gB
zy)OX{fs{v@J}-y-MZ_Q4pm{{TjR@9#2BAkn94MeCN6P)<)cJs!JCGs$y~OKJk}o9)
zxK;Au{V8IdY_ze<dfaU>y7)RG`u&>ESXOZ6ZYwbwJ?-8V!z=5(Mn4T;V;C-@ro<g*
zJ}2GRR?24Fn((EL^M}Nz*Bhro<%Ug?526breyUo@Gkb|~zDwg#fYP`{Wx%PIdXV$k
z`!}0DPbzjjE~Wf^DP&Y3o*lTL$kH|jEMDXV7GdK$$MPwEtm1UvkWPbl+VR@&H<+o-
zhia+rjhdT6n=clB-AC47dPQo6melf;87g76wjF(x9x{NBacx1OSTksCDlM>_5CZ+K
z{*qa~)-st*7VfH|j+j@v$oTpI)2yK50dmj!Ov6jn1Z)A7?7qQWmQAvkNi?Z4&xFv|
zYt43VC3v;q!yd`Y!Nop7kS`I|jzPT!vo7Q21EENnCSEz0N)FG>n*guxA;_-#V+?xT
zAhwQs&Fa1Hmj34R0(dvhVSQndJ|0Y9lwb}$9ezh&rds%7@^zo7ymo-R`gFlz%>SEh
zo(7Z3bQP#-+9VOW1TH>k7EMC{E*v@W0C)0UqhL-*_tswNv*~bBl<a-}t+!#jIWqEC
zN(Nku8RmAcedvR$5d{oTJId%Hu?$E$G()TQJoD(qS)0L>$=Y;8!!UfH1t4?<lmJ72
zMAl#TWUv~);H2#znry~1KQ9N1%tfolXwXW0*RD-eCWq&Ba4bmQnqGA;VhtPj5>m!}
zWwaLRD)v^7#d;|EUu+l|K_of>CsvOGV(WOO7fUeNz4Jpu!?zfV;V0no8OWSQ5^+7%
zIu9XI#x1xjJQ7j3Nl8i3Q^UrI;A{4kw<m33nWZ7pa>@$tXu>i*fxu<|2lZc=a>DF~
z1*h+#Cy@kg)}XfGM2d4u0fl|F?Senqw93ZT&i*!ofcuH{c^NYoGGVAMv&&f+y?lz2
zv9Vm6e1*#lb5a93CT-ewU7uA@_}sKe3^6@;)-Oq*O10egLl-HWc>R!k>Uvi{@L!!O
z_XK4t*pvDI1Mc+2pSzn|M;9uAu1|pu;9Pz^K%D;wW*bK(2-hPdZ677gAd(E)E6JH?
zo7b@Rln*ioAva&SwV>9!W~!^6LqBgoBnizG*d9kjeJ%#XpPK{@etiHM>7x9*vVmte
zQe>9{{EIt)s1GxTKyjkL3{<lB7)tLqsaZcTlq_D+c*^ArX(L0SnG@2SX_ddOC}X%9
z`TUHO+nwj4_bT65p|W?Y8EZKDIaR(ob*FZKzyQE&9IE2W5@eZ<wBYZNzFIW1-*qRu
zg&f#r8L{kB_^DsJ`WvU2zgK(m9%SO)c7uOw|MU};W=Tfj@98!y)W6<(OENOhXgpyU
z5}Vr_@yn}DgQ65N%|ahJK%(NT>17wF3sz$hjtfunMahvnj%!anK2A)rkO_H>n}zy6
zGr;JD&`<EYU<~E<mRvWS*tf5`J?uVGLpKKy8u#(ZvX+Td;zp$Rqrz6PIO&+U%u10V
zKm`w3na%6vL45L|$quRG1Shlc%Pg&aBBNGb=K1a>gAjg_1!u;9y2a`uZcr8<KS%(I
zVp~Oa5D7{xGI(R04R-7JJv07D`8<AoGx}b80#rjPjYaY0p11aUV1aTR--7XGt)*#p
zjb{?+1j7t_`O!`x?6D@DL&WHm1#N8n^tT!VURF0%x%M2lJwR@B6DV{Q+gW7|J;J1a
zVg+3_d`!5aYdWYXstyD+Pq(WFs7Inpa(Eyjz9_Yn2fQYzOI3iZFE6!cK%3Q2DZ3e&
z>3EI61Kzz6^Zvk!LVf~czJ4`f3fQLE>kcAI$5yWJ>(-`SZa93sg&c?ygxrxS;}?JF
z{#Pnc>QTo~MkHf^8UPx2p}vTw2Mi~3hrWRuXx6;F*P=qjlmF9mcB1)&)!Lju77Mz>
z!=We3HyQ#Z2nC~+h2D?ZxpKCdCs2`k>>88pVDH+tS5WyX<`0l;5HF5Zq~|!IW{`hG
zrm;TRKe$sd;R^x2M8^5!@urpuMf8Od9_w^q=X+Q766T<b*}(mXFv=KSe_a|#@oY<V
z)iA=pX{y_S29g?nxrC3^hNYJV+EeO-CROkK+wEXN7+_b0{cgkkI{FTN(ea9UPJEo}
zwm61aM3ebN9`^sXJe=dgO0Ka`w`#pUMEI3oRemMoEj9xnZhrjoJ0JtcaM1fy*uR;K
zW0HGWsTayKX<Uj_B>{|?;JEb_FDM$RJ^2Qg<ku;@YtEj&OwgG!Xz^f!Fth_0c->{S
z2EUGbJWn6S&IxbJlEn7<d~KZjywx!iT}!6ka)TQ@h-VH<ieCl`m+~4kCNNt^Ke|}1
zY;ZCXoW>g^VGU2SlCdGz);T}FW?8rkv^FSY$cOoezCW1HP-t5R&OKOqWUA?6dAlhm
z8@`Wgh^t^({)MhkJe)U&_t%EQ58TAE!t%qv@t7^DEuY0H3dcPJc$qkWl-0(`qP;^2
z&6RrV<st3Q*2d1Cgfb%t2lipWVcfr9bA0{_i^x-{5`)|Fx;=kU>oFzt0MWAVZj}e;
z(ee%NKCAt#y$Dw;V05Ei(pg+{#OQYB4Tr6E^n+UDTC1A>=~JYO6Tc<-!NcR4Zn452
zL57u*@`JH4h+h5L<i$umQp?Y})gQQD)9~qZ1Z#Z9I6_#u&AT|OuKSJZozpEapUy&Z
zY0I&(({T;%Ya#|5Pc1id=OOfg-s|6J2<Jh?ra3&`M<x7kH<gNI@3yJD4SwZryoaSc
zTF}%x$3`H4<+OD>#W?<Wtd#XgB@?Air<+-UdL1CF9{N%Oyps=yk+^Os#L5R<*Lj6Y
zPAkIz(wvg44sI|8^cuHM4wp^+RsS}d-P!Yfawf@OFC!vq;mIteddnfE*fa}1RPOFl
z4$7=J@AB4xR0Co`H81VVMC#~1Fd|ZX%2#hCVsqkrAcE-v(Pf#p_Lw-rk+ovz4vd2u
z06O;%CA@-5%h&`_?mEzxUVjVzZT6M6%RD$8)kkA|P}ochW1mLd1c_&Ca4gDGgfA58
zD4M#`t59t|5;@U;vp@`XWOcl&Y)rkTxlfAJ<0xE-2nH&9|6`{_i#~jiL057@B3+I)
zF65~FQ44iw5#~{YwQ0)N{G#dItc<Uga$3@8rV>!rjaq2<Gr9DLBHa0&KMreQ$if{)
z2R~rJM4H8_HbpbtW8*gbjv)5#$w8icio1Qd+e+AnSK6+s17lJN@|vH#9tdB3F24t*
zxn=5+gQu5m$LE!8$>mO90xc#V!m2l-&|F=B?Y%5Q=1^UflNjxRzt)Oc_Ncp=e$WJ0
z+HxQMIxNzNc?6EXV2!DrQfD4ERXCyabd8%CyCnjp`y9b-FhaSuVUa%S!vVLfghcM{
z0!R{NF4mBDw=`VGV|+HS&Tn5obx|Dz2}`0Jk?6a-SZIYBD|X%fh|m<aqeu}MwF779
zdrB-@s{L|KJASId^zfeMU6bV#h5;OGZdOj%pQ4LmAK>9Zt>oPx{v-TQZ1EO8R93ke
za&eF*d3msKYDB+SH5s=Lw?3*_CN_hDIL*7kRD@+4&P}3aNnxGdm^0(LCv=5NU#hL5
z*r5FIVno?TVeUF5w~Cm}J+-73@U@Qwt{>}_BN(vt&&*cCljT#ubeL?svJo<XhmPuo
zj57^}ip|amr23ETi^Q6P)MiY5Q?cw55mM6@<8MESCnV~e*D^d!95TNgr8J)!%xxr(
zc4-xnmgt{lg!$xjKk{-CY%xzPptR`yJSXfZG0(?@=q<QHQ!3o<dEKD-BW`03dQi9=
z7~tgFu?kf+;aF{~#J?m~B>0!cYINB8B3K#~V_-*NO$-Fsto>I&*WL4WcXh%8zIG<N
z31zc(j#+s_)hqrlFK}X)Qaab1TqA<<!q21=8BQk8{z&MeB-tVea-;;XY8)_%ap7Vi
zpjtv1NI>8rtKy9s1=>ugC+z*!f-7Mu>dWbasl&&I@^)msr#k9P4-k0jej9kOEFJHq
z7nnuFbR2TZO4NRxb+8yx-Ba*zmUJ`BJ76ZThI1##!|MAL#(k|@fXUGNB9iN+)h*p}
z#WK&lpPVV)-GhSwo}{`F_AC4l7<Z(Jofa_hMMdXq*V&YUi;DHLt7k7BeW7`Xk+(nO
zY&ZX5OO*55i^B6?hm~H)fT}(mQ~8?AoQC#TY4hP>UXmSz;H#tpI^)c_WAYaTF~q+Y
z8o(~navf%ToP^5N-P3`O>%4h@lJq|7Y>rZ@|15HS3NqzM13a^2Dvj%*&SHTmK?t<Q
z_~N3l?WE&=Uhon&RJ1NB72B0Et5L3XMp)Fne95Z-f85oxq_B0wF}|a1l_y9e_Ig}-
z64M?jVro_GtA-~%r#P{b{N!O%nR)_5Im6Wkr%Mjlwu?mZbrX=KkEE(o;Wv*Cr!&qd
zFdQaUNV$Yfg(llc;g7P!{B61L4b{W|-PxqIOt~3ao7L|$HVzf*45tt_^i#vMIy67M
zJVfz1MEZcz$oNSdS4n-A2gGQv@EO-+(Hs4pp6atIf*m9>9agJP0~;<s;cHe6QBatW
zhgq};KXJVWzeZReEsyPYJ50ezAKPBTju9n6)#S2JQSIw9Bma`>Ez}LH5ScLqhA5cZ
ze{smeepzivEX%Om$uY%Dh45?)fM`V6O?}tpt#hZpq@B^n(lD;(<upYrC=tU?!)=kR
z#AvzFTZe@Uon%*7w6)Ys_Uvc==03kR$C$@XP!3>pVA&8>s0SFmO8o?_-pY?00On1c
zXi}nmq`;KqFg;^oV=5PA7X`%U+mqCkq^S&9MUb4JY^MDlnvGeFSugI}o{(22pi%gp
z%hvnEgi<-EP9^ppk$1nvq&*7M7>sy$?T5$Tr?bNE*-K0o#01?W>Pya%(v3na!YROU
zas{%qbB0UG=WbOoFx^pUQfXlTLS5k6qDik}ecNflGXFXU5uiGP+FW<GD8A|4otdKd
z+{xK6A+X}LJEK1zexFo{*LnZ8MSi5oEN>w=w*Zi<br@>|L&Nu$E0+G=7!}ApCE=FM
z{W8Ob``Rw?hk-aBp9p+avqP~|13%Z@=!PVRh7-T=2*wWgDTN^8st?DCN}Y|1H}fq(
zu3xLXk*`*BM~kNe(sWZ~hjBNk+KEHgN`pCzTs)6pe^eHCpOqnbOZh%QtGR?FQxwrR
zZv<^czMfj+{k@MsSFyA;bz%6b(3^1Ve22R53@ZwhPqp3wq5>-TNX}giU$=mrG;vA^
z%THNv^1H7EXg#!oDV4F`(&gGoV&ad-vccMqP-%9eG>>?jxq*UuH&>qooq|e58S|Fj
z2-~ELyaSPD0Tc~%CiR^YGW}XKXYAgqUA&br58Ud$w}DaT@+0!seYjcS9@(Qr<3|VC
z!WElz$Jgkb(gq%%JP-_vwIxC63B?`7^J5QpFjfLxQss#6<!J;6*B{`FLbudbY{mGC
zS;cR&PfgT>s?m)BMz)@&2)u(Hx0Pi7l5i%Y{!7g9J7{QZBltH^?-26aNNaQPN!Kzh
zfZ<%N+TgDeK9uTVPu9=dLjb9Itfk*Jazb~lVt}smD$t88Jbk_A$3)}gF$SI@g7{l+
zD!@Y=<@9le7Ig`X$alV?RyMLDV9ui@fZwZDE6BJfOh%G*tJfcRsmk#bxrBU$y$QGV
zVOA9u2kXUy@q%-p>6!xY&*YQu`b>>1NA|klsAoWPYbeC&ut^Le`UI4pRH2+rEp;mX
zHgpq={q-Wzt*^)@JvdT~6f+JuDQ!E&0Fbf1PV_XNgyfM!q@S#1l*sTBJ5#I|Nw3PJ
zjeeLA)j>bCs_csC3CP&DPN}QrHA8)CG>hb=Z<!s>{Q5Z+D`JZ;g-Ve=^6TBVTw0f5
zxyR?@7Er-PLtZ(Fn_nFKv(A$oUa!fXxrS^10~JAx-KxyuS$sKNPz}~O!aAoj{`#=y
zfG3c3bXfb43Q^|ql0obCTP<hv2WM>sOfs42F6NS%6f|Py2kO1BLR~;W1{QGFo!j}D
z4!zYcD#F@1y6VTo9RA=!Z(r7F9g6g=im^7iYPvz3>;m4q?qnM`?JD&{fP330DW)aQ
zsi2m{QEj_ppJ$Q@%&nYNDl*!aY_-kRz1*^k;r7}o41Cb{jpo$O!rlqK5fx-qmgL=b
zuy$2EOek!S=pj3Qn3aAVMCVp#*TO;RJV7ICi1ZlE)Q*?bD)qi76pYdQsqO6M-Vx{(
zC4;*TIeW}0t}bWjkP@|oUW_=<g;<`5(DeU_QjUSqldUMIpG6(TV&f*23wBA63EL=R
zqV)f&-3!k!)BGM<#(jM^-k)mYZ@k6|!n`$!AiEy*#V}UCda3ZZ09sXpP}M)@{x^qM
ztK292ogdQQT9Sf7c}#>Zv*z)%VUdd?e#eWJ6Rlg!2!1;gyQWQxqTCmJ5j{e?pOp#`
zSeu&gsGzt}&@O1B>r7|=#7QNyj?Q-dnokb3kMn@_8SR8i$r=2clR?j*k9G434u#J{
zkn4POhKQacOOmi%XS9(80;shw!5$W632bf1Zb~c`%w;fOjF=5XHtG%kmuYuXS{dhd
zruNxFuG+Ql3~-hSs38a^3C&U8YPixI4<OL;dpK&Q7<s9?d{{a=x=O?w_D0xOhvPr0
zW-z(*X)Q0#XW@7*&|c<Q)RRWUstN*v>{TS06s@ZRUv)bg2JD@!TuM_dfs@!g#QONZ
zV18}f8>lV4LAblxsUvEvwtP8prP*_*XW4gEuyUvstIWDJTb_FBP$G0?6Mk0CA`CNN
z%14>*Pw2H8o-LwKG>K6P9k$VAyQanUY^*dpO|6=`AW$Xv9ZquT`{d_ld46i`*q6Iq
z5fU0L3+>Zj^0ObNnJa(ZiON;+TRriKw7E=1OeQrR;uY6ws}z&!e@58(G@C^S6b&oO
z!q<7xkbvA)KPy-wezn&(^qTa6*~8dB;{U~j!3Dl<c7;H{n$!q&-qs(Zv);0azh=OL
zTC$-%0k+WKn0KIFr+4*jo~b6oHR0U_wtTF1i<44V$}H|Rd2de&qBLZeg-<BHY_ce-
zpqif@j<$rmlj<+uYE)wzXj&P|O@Q;N@eDRAM9O&pVtp|mz!{tV!rl^Y*d4|<ex3@Y
z0XcgbQJ>`P!*lVg<$Cr0XULIfcHL&r+VXr~zU6L@_zN=zQ&HC)8+hqt%DBJT9_z9C
zm%AK~044=Ekgz&Gn6qc^>m|2((D+-Ns+LG1>B)oS9>)vGY6JXL2gCiZwoKkQ>R0F<
z+()lt*Lxxy5(`(&MRR5zWg>j4%&jl{FvyHr_@pYm9m};Y3r$HREIFAhj_Yw7+J;VM
z;QgMp*ByEf4~+zU&ce9{zGod`KHky*hopn6$^?qiHu21X6Fo09yUl(NjU(fLuyd=E
zk%gbxG3pYlXtdj+Qr*6O9J-FD^Xx|UPs@I)ua_Jp{~93k7iq{*u^hlX`~CJ472#cA
zV819^hb`PcBol5NTWc}JhuU?wkpj<2@@Q1F6eWIv`etM`<}YjQ`g5CU^+)Odca(Ow
z6w_)3bzf4EfOthS1Q1^ptc#neF|3rZjtBS)rKKtU!bxX1^Fu@~4%wZ+cS|SxgDY~~
zk5KK8qV0>}R4q5HuOcF7gWaUG1s4J{YpOX~H+$Xy8B&kM_8X?;CvTeS-FkxhHe(d9
zP!(NM#S3EyZ$Um*+t#?_?tG4sUXARO1rOO0W=;hy7WwMypu~fC8$&!&T#mvm-sdb@
z9^50a#ISmZ`OZ`g(I|qdVb1M6Zj(UfL8>JUZ3+&___NsUS?Oblzi0nj=1(C}8#Eqp
zST1b*kAGq`C2OB_azLOKRT}|=u3f;gch>*FZ)}!gG>>C*HOycoHm2xY=V*9T>$NiG
zUMl&{E{n1!se#@zhKRkaUkzHL*8;W_y(|)7HVi%&K>-bXm}n1#e0dAVoQ7LKHfMz8
zc$Q=`Mx!5&`qoO0@4fhf`)kteRvD=(brWz2XQvtx5{A08PamN^U$KM1#Dew&P(a^?
z!L=s3yrXl!VX{2&RTHN)m;Hh>QvVwswxSZVs2M3*+(n?m<tA>d;05#M#80!En~$(8
z6U+JYtjCq<#yXR@ih2^Z$nb@95A<R@w7bMF7U8>rK!mjo`)P@ST@SeFrVtM5ah^m6
zw+=w@(Hn8-H2Tx%9rAfUZ8pGSpPQ-tzlD<qZ%l@vNnDp`Wl&x2kgNdBTgaO~=bjz-
zIx?e8VGCdDgy;oE5!%uUoz(6vxLTYhm$T-he>ylcm@5fkn&Nr&-hrlcGno4kj~U;D
zi?z(@h+*gL{R_#es^u+1Sh`ncM0i;9<$yK$;kKF>(seXc_?p-N;tCxOe71$KwX4Zg
zXbkNyQgrB>P_PCirvuyshB+1n8lqjQZ$ZTz$i)%8p^iT5ILe6#^2-QNt2UFjBWVtu
zJ4%EaUQYg9TPM3s{$dA2X#;9EEoL%Yno^a^GE^(sggOG`M1&30@wT8~Zx2@9MT<Oy
zPwFp=<2SkTnX2tXTEvJe?xcBxbitZ5PU*}%sg(otA%}N|_D@yt=F^5tK_0OU`Bx;%
z@1-eWp5^qP$=ir2JCVWm%kD~^a-Hw9p~Z=(OpeEzTi}~SCyE7Gw?iLZ%gkz|#TiLG
z8EpQVV>siziLC!?*`Y&QH~LJg##7AFuO6#Sli}`6gazmZ5qBW4Q1UXD!0E+m-l!)+
zA7{CSS_cD*vrAM)IDl#v9<q7*#_EW@{;a=s#d&AI0otIm|H%V%0b5w(z90|RVv1Kg
z+o(7%QgcwXr^EL$w#$v`4<l9cZW#_c++uPmDZ2=NOEqB}*@Tr0)7}WJsbS8cyUXUC
zw1Be8J9Tz0CtfA)3>KU+13X<alp2gZpe{`kXk<d8B4Vo*3hx$|8KbGXA!{Oqc6IAS
za&>zq`cn@&1kL;Du1s$eeqhZxmQn9ko&$K139o|}HU7z<IChj~^~0m^Kqyg~(4U3J
zvr20|vM2a*ua;mqT^Kg_oosYCX{%Xgm&IU_U3K1_Bk0cj02mv{G*J;m3yUn4gL&Q2
z^BmaqS<x=YbIDX`ALEzf@VDpvS>gW<3{{lt0qj_oljq!2tRi}i;VJy0GUlmo0kN<d
zF?Z4upFBlQfkz+K|6haDuq!_jN~(=;fWUweV0SP6MGJP0?OQkInqC*UgPo=Yej}T3
zH3b9n<x_I+=$m3hrvrGXFhe9&mbA#i#6V1h&vhDUAaUlbjiZj~;~p;IiVaxc6}oy|
zha`Bb@CwKGWGmmYh)7|r(^*J8XuqW1n=Phq;BYFe?h(knU`NTP`vk(S+=@Z(`l;d>
z4ok7t=$c)jBVKCCChS3U<cb>lOpgJc06f>5*zGj}cA^ArD@f&t)5z(ShRZ$rR&)4M
zN(%^`p9Cv#p6&1%G*+Kp=Rb=*KEOCRWq>|l#*f(1HBabJ8Ng`V!vf_rR3Hjx6tNC|
z&!PnubAmPMfjq+3*_uIq#8Oex30M2ilohZ9qo5?W;*}l7-sgL>7Ec+p<~6@p$~T<a
zE}XkU-i_oG{^Wd3dK_^x=@oL?`{SkTT(oxRpkEV>x(~y7u4JCI)~5+};MWvrqUt9w
z&iJ67GSRHn6IGj~E7dDL^Y$B3lQq2S`>O7yo<Z)$Zx}qGf34FHChoH>_UDSix+$0e
z?fcz1lej}Yk?`E#yHM>ql{1NmvVq{NoqrMPQ1j*ftIJTbdEO=F#rqft6*A*awN$R;
z`f<rgYoV~xxzRfoF0#%TqOc~4pt}`A3?0T#qVbIzTE3j@ys_IB*Aw_z1ajy<f}082
zjIF*ppR)%G9p2P{7-2sAUt^qfmD>R6NQnVK#s&tJ?AfY~UR+bQ-8(MGtQ7`)<S;_F
ztg~O+fgu?A$TKXp0-1jWku!T%HsyIi8&R0ps(l)&Jq|LGHng76k$Nx9j3K=2wuhW{
z+Mdxu+yjopx>307GQyh<61-2{aH8ToIZ)BBs+9Y(VMYBf-iV=%>QxLTb`wu5SCW?%
z_H=}iwiy5_ScHO+_QIGWH16$EV#7~+{oa93YFk6D_1)L4^P1XXh*yr9dI*VqBow60
zU5)W-AuI7n_-lFhr<VibHmVAa8y~MxuJe{9p~aL+q4CBY<G@s~fj!;5^UygbdNDAm
ze^ZqwDl~46qb-uF51^Nm&cG-LGo;)O*CLH2@GUlJ<yf5Z;QcQlJ_N~&9TU4;^_!DS
zx<VS<*JZ6{10DrXNljLu+csx>ZJ_kj89x53p#w9hfxZwlW2Hz6>Wt#v$_xLiUnE;N
z;-VQm5a!UH>pF1*k$<9CrQM+}EB_5}kA(!6u6kINsR@?~C`C-QFTlU%I}Jp%Aj0WH
zUY`h_Eswae4B`H}*X&#V_NW<CBUMqN_K{Ut3;Duj5;>bv5nEa0=w^}pd*ubt2nfzS
zDlG;kDRxv7k|;zT+?bHqvMqoEca(^8@>kEmTgar^(phKbPq9XcJPqP{_tpJx>U8r)
z!77LAPO3z#D9xJcxnA*>P-!|CnLI#09>=tL!v3Q+Hp4(nz9&xIjr*IYp@#iXE>X;j
zuSo0UmQ@Vp=Io#1sRs1H*#q`PL-zOW%`oSCscox~qib1ocKI*pz~^n3%T^g&?n7S=
zyh~U&KbugOiIGWUq4W+6W9N)bG2#(6{_XU5pS)6nbDTt;HAMc)&NI>)Z4-2hMXRAK
z6a5%Z&6*6n`qinaYOo3l!=NZ@lo+W?IQLX2leUj2lza@ih|QD`8Y#&pHC=sKh51-3
z#IL<9Jp<n@W-J{5hRgo0i(Fbj2ugtw4g)IJ)W<@D?Xx`X<!zYbR4nkox@Bv=S#|I1
zN!8bLnTZrBzdhgoRis=^O!u7qjxw<~*PPI-Rdm5oc(bo})Xxn&@ubp80mdc>O+xiU
zr@rALL_+mD)JfQ&HAAaH<N!;Hdku)H(<24=jz{Xb{8ZV0(WWWPbk??j?q0-8gOJ?V
z$d0%7oOSj(J<N#1GhuJ^uPF`FO#flL=1on+u)SjqW!z@u4-|D^dXX}K%;S{qiU%Vs
zDx%I<l1i86`R6C!F_~_m&6ly`PP1}n8Ruf$KP(Ix&XM1-z`k&Phw|16I{83!s(_}K
zn8{D9bc5vI3A`4=H2}yZTFXj72wC=M{1;&AW!(yX2KyGcQP-N!&09itn-@o*AN0#U
zU!4l!fz_}ZxV-G4CB+8U;FNRyZXgS(PeSa&T9;~kX6e01nYmM!aMCb*XY_iYedU)1
ziq#nH19+}-bZed@X%HA3Rme1xYBw^;fjc&RR@Fw%Z_cV4<-lvQ#>Ht&MTe}Y6fUy~
zx)U46VA};I<o2r9v{f+0Tby6LGW>Ge{u5<YYWk+GS>Di9k|Y=`9Y5~6)CMdm|0bqK
z-TC^=K)vesr_2dEc4Rax7(o2CUd}QgiVYlbd_GM>o3xhhFxgReNH3k}cmrHWKNOvI
zygoCTc#4N7mR;E7Z*aNoBi4CZiSl&&JQ`Mr@cCXw$Bo{%mhI*|<Ppn>&Lb8%BuVCM
zKl{IlJ~IIjEhWgM=xH!3dEDrpq;4v98Sl0i3|q{R>Na9+!Iz9pYFaoz+-3?l?Xks%
z>Q3B#;^|AW?mg@?WNcnDX$x9*!{_cWv|v}3^tEBi5_5J%wgFK~x9lk4GGHI#(B^M}
zJFN+kjYiO**w}GMFM`1Y@iqWnMAc7cSh*ejz~I0Z(B&y-6j1l+PM;+*IlX*wlj~7r
zX`^$6djDU`CIqC6UMn;jIQh?Wdcm5LaOI*-8MO{g8))VqH{Pr7MuHskhnzaiLs_ra
zliwm?B3@fYf_WpBYb1SuUi3oe=vWq<GY$H9+$T*RHLD*VoG{!eX;;Z|rRBHz;&~7r
zHkRWSPUj!eQ9t)mk1ov?qxc_8_7*pvk$zlKAWdP*`LTVr*?7O2Y7UY<G>8`&#P^$u
zzyi&Rw=;ikB%AC<J0=lJc`+q|0r=*4>E&@d#E3%1{_UV5pH60({<8wb_C<q~^kPv;
zGP}!=6ap4?hOQLTZfRLW&q1}Nyks}3y`n>;wCRXu1|x|Mh_h1Q6jDqNeW3DTi*}=5
z0i>*Q1-je;?K7>S{(C+0z@ew#hN8D!VBw1uh?S)R{mw5P`aEXXennbtZ9qK*tFEBW
z#k>)uc;A=WbUQOmlb!|>#mh+HFuAi}+H$v`O1NiAqNr9ATj6p2C})EIS*Q9EwXsK^
zb{kZ+5EU7h+a+Kc)0YQv0*A(%dM?gTgLZopY@1;8BU5K5x%TOXIype>mR=@8&*D)4
zc<^LdEnD-?A;!~_@^v$lYe7;#brgtzQ%}7QQt6|_0fjKcHu)Fa5_sU&y=w)I*~|qM
zdj$nFx<%0?bbV!891S%11mBhqR>r%CzWru8?Od6mTcl)0KT76mz@lag<hwkDRVLEl
zQpp)@xBrCkMLAPOS0~pUxoegAd43Z+wG|A6*<3>@1uZJFSER!pQ4hytYwu4<lMHx+
zhmzn};&`Yt2Xk`BKBX`X^A#mWvkMqGcux5(&-<X!Q|>N!Op}~VSLwSU-WoF)-qkow
zZ-6-YqsFX|s2hfV=p@a4e;6m+V6CFwxa=h|jABQ{B<L%Z)92lE)V3Q;Ajz4*qY9+A
zf_aHf;Gss6FYSx5X&q@X#r1eC`COY&_h1RE(?YvATpxfdd&jh=v?S%Utz@RKy-)Pw
zt$PG;DPz3-)3wUc+-}2~az2kaL~RTvA7enOGAEU;^A2`_jk88K_?h9iKiX^gRFbLn
zZuR7-B^F+|6_65yz-p0}%$h0$;q})qtu}u;jNM*T*tXYdH)HX#$56<`2j=Ujm)x^M
z2yEWhe?T=!gzb%6tj$wTf#+?v=snT9C;%h^3)sdgk5P7bbt)o<d)6GjaRXFSO=y#^
zKb*be=1!I-Z&Fx2F5zlu!O}eyvW%7wg>RuPmIWR{iQzQ6Ad<*cXn0Vm!p~ILRLYu}
z1DHvli7{qzYbtsKx<UFB@<W@Dt9=DCr+?EICP-DjR_PhP+3oIMrO5lOme}KG5Rh+O
zBg>BKpMZ6$euElw@zimW7K3d*OBZXe{LM@jA|A_VmV?L$rUl2FP-!t<%ml)Ikxd%H
z<mIWFG9!^6;2EGIRL&lWM5$H@giR20uIbIh+AmT<CbXrSW!3yBEYIJm0GYtooT^JY
zV!Sv~Kr_!etCQ7^;GDbU{`px~oJ9dlt{h&A^gLiaK>i#1k<|Nnalce+4CfzJ4!LR!
z-o|s(i8_i20Y)!UJQ?y#CxlQfUbVJpH3OGP$mw@Fdx;W1&OO(o$JlgxLo$Q8#?x3H
z%uavoG+%j~y2>+>X>2p(G{^2FR4On(4|gh?-fNW^D^{$Zsp+{r<>EV_kzm9e0awRi
ziisnPg^Tu2-t^XNky$w;=rVztWNmf-pa%Q;`+|uW6T5%g9A{0=*;C=$8e&v^0$rNW
zuhx`Md!<VAIbqZ`3}i`h`{^nc94T|I0|-h&sA$hLy+HTmRr3C6iKj)!((5u=eTT3B
z@yNOX40PJ6DxhK$;_9_|Hk36(hl%CGTkR&D(NtcK$<0{m)&vm-#M_Od_FxQ!f=w(G
z%;j3Sg%&4>AP+`&U49%Or%cXmbHO#%^M81ThahasYSU4}pk*?x_A^N18csC?9Z^eq
zV7FpU2_`+Q$J=H}_P-1Q%UngKLSAI>gPqWI-$n*991i`V<IvTzk`q|v&eXAp`MQO6
z7d5);PRYQ{p;T7GpQ{*EnlMt=Ht*T{UN!-(3AnVAKQG{cp#G|nf?s`Gg6vi%M-+#5
zE}9r{Z)(O_TG#;6O`1u$tC=qeo$NB&wZ6HVFb8zyU_fRT^(-p`Rm!rE0bv2z+z?LP
zO&DBtZN4PAjI?Mr%KCX79P+L+jfV)rHX0+IXO25{Ki`<tmE%aa?h##ZggbCcQ#uqm
zdTAKFSq*@JVrTfsO-ZnkS2Wy<MbhJ9r()R1wjt2Xx0_<zI_fvC7VBO51yx?fS9nnb
zCJU(|sm18n98I6AB@5|dlYNN68(thVV-dLMY%)Y8l%l_tDh-*(r$K>sg(TgLT4<R{
z#M{C;nNU*0FKligC(xsJP|~{lC5JF|vfvy>>Nj3x{JuZuh)ViR$3ELfS3Vkuxl_Z}
znk?J^J=H0V$N)@_q=5h~7HqRNDTb@(2Wa94e#&FAzVmYYFz6pB4(Mo=a*_TRI%Jy;
z%Z&g*cC<}j%nEKp(gTg0Fb>jQ3=_ZU*2zvOfYm&a*A|Dlz}AUenQ?p!(tSEisQwy;
z6Ae_G68YTn36ecUE8>Ln|Ga~TbSaF^GNu&P$IX90QvvdT(cB!pZe_i2CrUJ1dvJdR
z!s}x~HA0qpiz<p3n+>D0OdR!bC>7C(=Cp+rg(UA!zJV=?`QM#8!7v_<0v=8&!)wA+
zVRQ|D9kAAXak#lyh@_y`0rZd*&*eT#A3|TpTIV*hO~Sa8I&aI;L?)9s4TbJ%?W$EF
zvz}fmjC|@2u<W8~Q=J-_P{YBSc4$*f8=-oFNx-a2A~uCHnfjPJ^Veh-{(AM`tBPde
zCUCbzn<T`|51QeHDYGQ6K<wSYgx3csS2d{x|N3oH;oQeS$}XM1B1I8}gGR-B^+|e2
zg8FHHP|zNOn@_x`a@#@*!o^balb}-_-r<GC$fMD_xJ<?$lKx%qgS+vMT9JX+g%dfI
zpej+ax;p2;aPgR2(0wUi3a2K``z8{(2WJel3vAW)oEuxuQr(vied4T$4azwAW~_K+
zEW+q(A1~J%onQ#1wpVV@eZ^X6ht2%AlHtbBDAgG!y*dY?MIwM?A58`oYfHJvws{M0
zFFtHsWJpR{(`QW4r`I^24b%DEBIWQxSH5(i+GTevKV|!rr^{zDrZv9ASYpEpdB@|I
z`UF4X!RV3i|AFsT9BsA9DsXW-n(7Un%CuEkj|E@92XIJnw~)`L1UMIFf099_b(ae^
z=}OSS$sfczH<7{|xW8knmcZA$DeI2kBi;njYIHEioPG^g@uMHP&CfheAD-J+KQGi|
z1TtBEL{zY+gasuBr*nmt<G1H6%Psq7L$)X@^Hi@X>;)XrjU90hDe4iunzNs5iSf}<
zR0FK9ek+^QKp2y+xA0j}4S#QMG-ts|Ztj26`4ugEt=S}zCIZ#EJ*4s6z;v&K7Yb9A
zySwZRo&=S}*9J%u6EL0?fhXg|WAHmWoay++R$Z!*_L3;uQ%pu6Fh_rmH=~lxXc?<;
zQm~=*fd!7y?0-P`5tw5!3p+c~hegPvjfvCfZ-N$cGl4$H{C-mOKCh|TC!?Wp8nLQC
z#mz`|S|H$zqaPvO=0_}&;<0D-%?nPV+$p+e+I{Kx-&<vZ%ryP4Jf`1Te60MCIjkdO
z%AqCGL|ii}(8{7-fZXCzfsxxL_d5IWU1*JZDsnsc6TpFVds|u0w59fZ&9aiY!5vVz
zC*`4yA+%7IAk|=V*pH=4!ctll^9h~e9j5$%sHi|}1l|~{HkE<yzGo(@+0KiLrN5ZD
z>78V1W+fV|Y$~|!(JAn;*d5=Nmel0v&uf9ECkP1df;UKshL^N_huJS1eWJK9+Ix#<
zz|8(YQdDg{BcAc<!syrI12fPcG+x*C0Rl=$D)_^31uEoGn*|Oxh&b7DG;A=+B?7l+
zi*)gY;^=TfBa7E)T(Ber2+A%ecq~B=neQWjs%Yl<M812(FXh<xn%_B{LX=jcBQ~B6
zr;6j0rzHT%M{L#*X_K{gFdJwf>O=1G-)Kh3S1{#aEo)b9gon8;a5)&0GjDRqsWUd;
z$8W>Kc@knh)6Kw3$+GIKCJgYXRnFAATXBUsD<y?=wyTiylYk-4L?@FHHJS@Qc-xI`
zhV1sO8Oz-r<8DPGg80mVNjBq7UBq|A6!0(Wbh9j_2j0#|f0+sk`_RxM`6mH9e3Nt@
zhO4HnAx)PbsN$&4(kS7%d@S}G9VmF*jQ9Pdwt3vETH<fSUm-ZcLcH<B6H9%A*s+hW
z=VN&Kfyh=GKR$p!%E`(Iu`L21p0sW}9YYKUNH!yHBcRRNizfNj)zGP07KYp!*l5mE
zaj+^&!XYe}4^I(heVAdercVL6@zr;I0n%xqqZ41mN96-xOg`jwSuq9~#=MiFo3%)5
zL3g1m`cLFDmwm3rkXbm&HM%w8ukEk@xerN)8>??6pW3Q^;@`oV+SE1seeT>Vh*DLe
zoQmuaLz=0sm##($BA?O9=D2R6K9Gv}db}iLc9e}&DNRr6g{;C(lSDI5KRp&m9X#=$
z-FNfUh{VfNP;mOndeH-5z!a4ZF@~(1>4yk7n%&4fU_@;7W3;eh;z5-9Zy*Lxp({4}
z>UxRJLyE9<3^=Ye9*uzS6O%dJEx1mTJFF~ZpTp@AnutW(jeV-&$wP=0_)}@$SPWi6
z=jWz$5M7e(pbX>PY6)5Kz;fCME^Zwby2vXF0Td<b#`AYfNP!PmL8Iv}ME|~Osb59v
z`;dTSb8b^~?(=$eTl*Q`@<@&GB-*C<8<__&0Mv!qjf1Pg`<gc)--cgM(k~|U2C%%v
z1D$Yi)CkM8I&e3{P<kic`o58rx+0}_#UE_=@kVgX@8)b(!K$IN^Ln41;|V~LS>e+i
zoWY9x?SN^x?P#}RM!tr#7!m#a+3o3Tb_XRsdE6`p)!@@Ar-e-DIh{Z_5KB76eF&!4
z)!ilDLXBd6!i&()uk%X05`mXojca*;!mpbioviq)qQ-CO1#Yl<Jj9Gkm1L7uP-t5d
z^bsJ+?`=*L?fR5VgSkt>eRrTcIZDJ_GsJ`&ps@L<Yei)p8X3NwBLlrB0zsaCHfD>d
z`SLDBkY3^KlHOyrO0|Q;tvbd!DKSHpX&J68t5f&(dSr{-_Ycc?W`$4O-9Ienkmoq{
zp)k?!x1K+3cAjY)ccUgcw5B|8*P{CUZIMr0{u_njEMzsZjysRNp^O$y)2Wd0;zsOT
z<%;*EE4IR?>*m5ym!#Lu&dtk2NKB3k_wTZ;u^(wnIT=vy@fWcmdS61V0kROi{{Kj^
z4k`=|hV#8eni{?1?9e%yoyS=l<E0z4>`T#F4k;-c>*5aV-p*>ju1NWnsxMhk5crvL
zfvZ+Ag0nhIaIS+q<wcln(jqkTS5Yom{Pf<XOcq4c%#d8=A<ZMHF=Z|0WE+JwuzJOt
zp<8z(9;O|KS>4S^mRdK~-w}0xNkewTB!d3Ka@`=e6Lr%Sf((L=J2RY!Y&BM+NHTb`
z(dTd@p?f_He_I-hg^k&xTrm21Zxn1#EEK8Xvik_(51HGktzrs0aho{P>@=7?{f-3v
z-oQm_MyqH9QsC!dmA`}`w3%X<bc_**?MC&AXT_6W2LPYwOXv9slh4oQYQ70rnm8P`
z?Ji4-ZX4nk=G`{y)^xjx$=0<#aek)ifG-gsT!mUlbG=}>88zImtTt7lsK4M99UM3W
zlN@}Ugz1RWW1jrPG4DRz3^T--_k)i_0v2};K3(#2C`bO&p}((%Vs2WO1q-jV8s+SR
zTUYXhV!vht2FaNSpk%*G%0TCQ8VF`=6?=JJesxyYPTE^E;JfpC$$y-y;hV%eTf0He
z0s{^h@m^MC&H}m?&{0TcX0tVKTa(QrSs754$f>!-mk#6+0aPLKUIY~2p&GOM%#4x~
z;^)k;$k7^3j^n^Unn<npRr@np8Qj|-nUXWSR0~?-*dPpfILg*UJdWh{w|zoT$FPJ-
z`={^F9&<LKdX)r0x!iV8Dc?Yt1biyrg3VGF06+#{sfnY|h)U~A{M1dDOX7UE(ocl2
z8jY<8N<<}9-Tglbf#k>IFlR}6Glag)vZ(G-pgaaUEm@0v#c_GBxowu<BW-gXM)rqZ
zveB7@$0sWz5mnrPF$LIa&~w|WL;3sW)y5l)M?~cpW)w{x#GW;I@rvKOURZ=Gh_*E-
zLGpAnh!ey7T9Cz)e}?X6JGWVwOI`-3r{Kb-55S=J=s`>ng>N#Wx~_ru?<V$>s%y?K
zI9Smu{}0PWrkq2F&`oQmLxv=opF)=)Jv=+*E+%XP8u{~t)76}ctrNhKN|yT>QGebg
z$Ds(nUxX68_<^`*7pDgRX6J@sTOftRgN4lEy#|oT(LcwBl(sV^>MlSdi6wl3Z~TP(
zsczJ7$Att@euuh9YvaM_z%**)qMF$IMze45g<aoTfrt(#r_1~bY7TH;X`M;|(%R5I
z0&#rg>PZc`mF=pdGTBaFjOY^xQBb9vdae#eGUvlZr}~}yhIP(29@@%mg;(kM$Q02o
zde{4`FiGnF^0w_1D({vwsr?BlR*&`#^$Cw1%1EcdQ+JW|J!`jeeKoo<w#NTh7|!4t
z+*rK6$V~6MuA?}WN_gsNN0_w@&1-sp;|;T~R5$rVgul$~FI)oehFajF3BX3fW!&@-
zzCNYM<T~!m6qNjVwUEXIk6;^Y&+C|MPvIbCiD}ci1bU2%qP%%KE8=AE{kLe|??Us^
z;0t0>3iS*RjK0n30?wtXtt|;1qLMj#jN{T7cVCOl^g3L=OP%nH;KO?I(%%<v$E44a
zzNDM<IE2$Vg~<h)TY0Ug&PAwZJ+#N>Nz5t~7~jj`IH;t)mox_{Rp*t47j8Awg?g7>
z6y53zzchq_FTInqwivALgZ)m6cbh|2fhu@jvU{7awEN68!5}j!-zF}Z90sk0284_8
zTSWOwHaruDp~SsEDF<l-CYkVK&IIBeH7n3(97}M*T$Hq+y7%qCzw1mx;qJ0Dm{0?k
zFpHqArHU0T2*`FC1(ln9$cvZ1$reEeQIy@W`nBDzAxES%b(1}X?f;XC-q`OEw(o8&
z0;eUvAOb{;R!op&ez=9k_EHk>i6VR<_iP=LQsNc8UBD#dL(Omg8t3!OLLNgW>@r$a
zU_bj9CI<BQR+4)WgIEY~x6rV)ZW+lV03kr$zuOOTR5*O^Q2I)eb{;wBd2F(Bm98gu
z97LxCUVi@mL4(vGzq~nLQt|RU9-Nxf_1&Jay0$DmAUtbx6M5W<DRK{%VRV<fIBd)r
z-odCtbHvXUf|VI~B)0+eSi7lDA^b?(al@UAn^;%{;4MS3)T3W#`QK(qcMIhf<odQ#
zj?@u8dD8a2npVkIH*t4BTkQ!c2b^0~szp?KdCx8+r>GN-rmq<?vz8{xU|dl0p`@_Y
z--+NyHk?yrRZx35o0?$@QW{GKLmwr`6g$rJ`p3u@b;v4tk<t&b3V@AdAh?-eWD;Qp
z?^DI-rsj~kk}RG@SaFSBJ+Gt0?FZ(}yjJWgY&KTmNH4=>#Q{nneirCs+K^9oJ0w=`
z%#OZF4g)?M%`MY>LqU?*EM@+@=xjl~45jJ=mV1;sJnwj)Y<F-{Ed@q+4WiZ~>211I
zKK_Vcd;M(|OuvXn;tqNx1oxZ$+P7!poT@Q#ww}xlTh|CLb#H7$tGMQFP(WTYyWc$5
zUP?cW(y1IlMZMdL;O8J0iqf16dxsYX8{5D`1^o~|%d6IO?*Wf1u5a$ld*+P~2$FKr
zN|{I!!wsesBaXVW7SgO)IsO(tCzU!imk@`Fo%n450CbpEVcaMM+D*%)=18>048x#U
zjm3>gV%yuEF+6AJckv=qr!sHDdbMkgifMmkGK?{&sp1C?BVNGJ*@k{Dzj|%2$ofOl
ziwQvaI^#I?IdfEw5m!=7;_Gh}CK9j$5!`c}v;do9A$n>a$6FCJnE^fYFMHMy7!uO$
zxwQ^p9idRH*N#=J>)MNf6Fz#P&M*v^M-FvtF@GS6)Tl-V>*W(|dZgr+Or+Vdf^GJ9
z?jkH@EIQ+iMe9Z~i%Z)a*U=so+KI)uCqlwYw#M)KB!((LoQt#0+19yQ7apeAE0l5A
z?1H-<8n71zR9%2dHFy5XhHe;=EqNj`Mqt-M(^0%w^rDIBAneG&W`>32(O$&^5jJ7k
zN5IvRx|SpO6wa)%PMIJ~(KhP!pa`*qQkKRJi4=td<{s{nhpTJo2g3eeY<C2?D4~=!
zy->|G|Fb6>X(Fr#I}{2csDQbUM@6(#a-p&;AXZMm6P~k#BBFLvZcYFc=T>=xZQioh
z@rLXL_sJ&i;E!y@>W~oi8!?f1#eG5}u<H*tk`baa5Ld|Fzn{nL>hGS?`eYvBkM{Em
z>4+1j!Mh9`&G*)Frfb}{|HG~ta;E0VQd2z690A(rFPrqlsQO?H(n4)4X%8QF&pT>X
zaqwIgQqI~Yn-ufVS;K!Tu}(ox;;{=qKxsP7w(jSJdx)2T2&C~hq!{d?6U2Z|5Cy;x
zwB5mAX)so(57)rd_;Ela>HDi6&q-2fCmo^UTqCIlj8eb0g%glhNp+t$eKaNuz;5ha
zPuOjX?jrAzf!HD6HzmN2w)u4)2jnDrfLa)!80{b$je22#R`E+Y9K?mYGVK7U!L``%
zM!3w{+%FIC*<+o~gl5$0wpp3AQH{D`iwaPice_G^_VBXheFoROKTGq+?LXgT-}!%O
zF^AH4Vwbd9)dfH8g&z%!pbb`7YY#0TkJN=NlzStvzpiR^hs<lD38-dOoyKewJQ(Yn
z?Z?C39FRFkqgWyWPJ`cljY=2T|IZ<avWS4{_X@){BhjHIVgoI0!>nCtO^pRGkd<{3
z6t$R`Q+IlNGmtKKlehzi)@6fsk}U$owat%=zTp+;*+|5le(7kw5C`H*Kn1A=Siz#1
z$|8exHmV)wZJ6Iu6aAQwke3)55r<PuwooNU?zM0HiJ*<WI+Q4V3OM;7*$Vw+yNz^d
zi9E&9v!^rvkd7kHOKGeM!?gx|!rs|$(6B6e2WNNdw7`C+@*LCRV3b>roiK|82Sgk$
zIP7bp+o%T;;hD>J7<D5}uP1PQE;;CeaRsx*25k*u<+;T^>Pin^xweU0A5-&IH><}9
zUx+S;NX%8Z!01(Ck{s-i1V7;S6W&e>nPDEqYNs!Yy;-xRP}FYMXw3XuElzLy+Uu@q
zxc%!@J4j+Yqv6tB9*sujCGEt`ZZfz2+IYlL&muH}2A62j#z0^uqtI#F4l(r1GgHRh
zTR(NtvrDDEt5~p;89?n)7*5r;8{*L>gyJPX2(zJ#`HeK@!yn^WzBhU-{`TzR089bk
zrD<-<2lt01A8uuz>g+I1b#J0|s#@e1qVTa>hqgEpQHtR7XfO>Uakya&BKP9<Y9&}p
z?5{KMQh$(F@T~cb(`@m5i_@EM02qr}o=ScWD>p1Qr)Q4xrKT#5W+obi(bifgpd{@v
zoozpon+;___Th_W+n11Zd|*W4Av#V0<HGCAP*`|xN2*`Mhf=JWH35ELWUmp8>htyz
zZYC@;lk0E2Xzm$6Si|<q`ppD|l28*0yDb<P(}Qh4Z&g<k(tiw>pIsr_P{|Cp{5OdD
z=n-gCv}s4N?oa7^?nP;5p2L`=q(ZoI5z>Ju+q6lcen5_lsHO~wNI|Qgq$r>09WUMQ
z!og~nxCiQ}lysGpgI=(Q3;SP9?nW&vspS7&rA*%Dgq~L0&&rT?{$l6>sZFyv_~Vl;
z(xt+Rlg*87&WYCspr?o=C*6iKB~9dhrouVar;sWZh^#x_(vk(eGoVJd^Af#K565uy
zB<ruamm;n?#Q$kx7bp`BZ;AQ5L5%4Dy|XnI9slMOm1!4Wq0tiU>`BuDBL@$u7iq!$
zt*44R#mlnG$DMOnW3U~qBbW1`BXQJN?PDb!;#F>cc35Ejf>3jOBuN$TpjCvoLvd0T
zoT~v8PdLjoG9{qVN?QFkZaA`yi+C8Y_Rh%E0HCMHZw_WGxJ74<ZlVD8vVT5zDei|P
zlBm8dvPRtADFZ0>PB;Si^@rUt_?k35j7$3$yp8IodLZpK1s-1;VHp_&LownJJ3KO3
z!}%wr4E&Q9PKS**In52tO8sInF@&=n_`+hN;|;nRKjJ@UT~ylVjVYC)rmyNFM0=yf
zm7Z9O%b5F~Iz}Yb@HYp9EAq~+AWUNDpe*$cutVvo^2u>t3`8cU3vJ*M<^II{r*Kd3
zz3+My5wZ6&s>t?otn?0#IEbKJczls)7)}+0CBh-5lVH#yopF^Ku=Ni{SNnNgfzTj+
zO$Gt~^_v0(7!+y|)A$tA28x?JzW_!Wx7~dXp$n$!Y>&zB2LLdEVDj<1xq{!mMvN@y
z0?LJW_tQEBP|ee99;{7tB>7`&H?TXoLm=DzV8edca5{-6T1zDPI9`yCKXy=SCSWu!
zGmV6wG{s36+YRP>HvxrcT=+E!JzI%vy=9N<m826*%S4<y)e<J@{h)rQ<BIg@PEsnC
zID4k~C+}dhwi?J^0cYz0WcrF@h?Akry@QtQtD`(X><vl`20c1r&asnwRu=A*AxW7p
z$8@O-iK=vB!V5-E`f(}{^R76iBE7b9Y)Dg$8d)wUc&ONQ=rn%ajdVg=E6cI%w_4Q6
zI`)V(LSPX!XTI(MeQnDoQEk2hL4(myeLHPaMaX_oSjkgflhY-K;!BZ#!S<HJjQpV&
zHFoGf#+Ev!yeLbKvlaAfrQ3NL6V5UelI?ozW#+^mp(VyVvD7Ta8kdgjsiZ?!uWSw$
zWPZOU47B3F?WlpDt2x9>txX-=%a5i{5AQ0(R!ZmK;12hckT*yF$;?Y7!-a{N47Dtp
zyTi^Yznai8d`A%?zbFhg*!!~fkxPdQWZ!qIs`o`ufJ(ZklqX>uz%FCFtX$Mw6L7PZ
zuR96PryI#sktXi7MS|>48|axGlLF(ha=Ua9ge-9qMe|^vBEM0G^e$K{7L+t__DoiY
zS3h*gncKje+oMB4i_mlkRx^letl)hHTZB&Y8z6r_3&FItr_W2KEIUUQLP&tl3GqB1
zHijG9lzFSkP=avWxiBpPFxP^y?xOQ5Y<x5XmWjz3WTf_FivegZ|3tepl0r@oC0t}e
zpKq)<@}=0D#-n1CSNfeYZ$g3m&3`GDu@LOxZmF<@x3dj4ECu<yb2U^iRRsx!v&|Q0
z(3BV!#{a!h9&2H0T34r5)<D|qEzSgSNy<fE?<JT!UZzXZjE2{PVPFVtWEpJ{DZ8eZ
zn>4<ug~DtB&n1E9^-(^{WIjF9)q`?*&1KZ2p39%!UTz`u=<*CTxGp#a2IIi7SjDlf
zd!zC?JS`Qu0yKCrv2s=@khh$CCt9=xnUl;crP$^ew(yHla)v>r$IEA|dXwC>jn%4G
z6H6dAh$?)TU4h_ucF{7a*O8aj20H_ex5-Yzf0SDoFBV@~ED*NOTaJvS?|EhTYa%vs
zny6N*GN-K?CoTd_YE+dha#T#T-MDo;FiS5{bNypuZrFVWu#Oe=^<E_)VibYIydFU_
zmb^q3%X>Qr=5>;IShK|ohgkBGmWVQjikT3i=jv;Q(@8?5xpwU&3L=;dJ8e8KFzB|!
zf=$!Zau;~O`&SulWGEGgk^~bZyhDcXU?pj|5tx_clcBo_=WtPV3Z&m2Mn|}gdrnGz
z>eWfx?B>AB04g6uhme}Sij&m0KpPKdj*f}`tl;xDtF~y191g@Qg4et)GD!s|eo<hE
z^k+mH7T+q6&6CFCTMH7N6i78TUk#FQ!P{b*wQJ4=kRJHQGE2+igS?&vFkJfsGTBcy
zjVki$a>NG_q<cTRsrR|F?4f#jsbIGnbBbULHme?Y5k%NetMJ?Y<1U1~uY0-W@TWHb
zZ(PTe*_TNKoj}Dg>FljFv~i3tmuP_tK&DvEsn}YSL9w_%Pu?V?_X5I|JJr}I4eYvI
zh3hASg?xMP{Mh%WI|#^h0F{B0lL75v)KZk>&84i>8XJ=zO}g0oK?hg3ff2Zw%a7GD
z3%V6+gBmW_!B+?p$P1-T%7>&D^eiGd$~VzYt!LYmhvl>SX;apyKM%c*Msf0H)2A^?
zJek?qJ5T`8EUZBI0nZ2`B>>GlZ@YLZFAe}cE^1Aq0fRsL<4Sa5B?J4}kuV^0y8|nV
zB~#vlCs1VYYGe~HQ}7=!BuD;`%%C1m(Em_4Ni0b{BIqlGZ3(i<lUojQDYbAjzGF+y
zk^LL+XfO;)@1t;Rk3)YBBmt7-gxxusCWvs0lYUfsoAzx`|2%<zXmU2Z?<xLvBNLNc
z-|+1BeE%CJl9;`LLiu;q)RA5MA}EI%nmMjFZ2uRicnGVRRvP?U0m}(s(NZ>Sd67Cx
z%1}L_{PHI^2fDd1AqmHaUJ8-hRp2<X16c}nglq)ho8h&XHpq6c^?<ImMBzhBTd56L
z$B*X$1HLZw$o`WJQvs)Cq9A2Wd1OiK@#UpoXifA80jKRr?(X;9PM_Lb7P|SKy@9MJ
z2^QnWCua%x!c3BQX;FocUMBok2&t|bb3ppHKfo^T{ya$hI9ZdO!yl;rAdz^5WHCM8
z7%^id*|Rins2>>kSnwEe81(0BX|=m8J~1`P#*qNhKK8~}^JcM?p}M9ODnSVbNH%PG
zhW703gyP+oj2}&OjbaycI!SbsDXos$+~E>~+;FjGaS%U(GQHF@{&XPtvf1AOs;z9@
zoON@`ewegVVr20{&{)6et#M1GH-mNx{tDA%P>EFxqTPra_hgwLH7v`)WM?QI1qanI
zw(*~U>Yr*%&nhu16s2A-TgMu49ouOff>PU{6Y2Dz<`qe?+WV50{YLVomVzR=)@$g)
z-nL<yQR)9rQ({&|R5?J6Niq?A-|&o2rIDVi`HvmqpYA$Js^_oEUXB0e?WCTZA*Z*7
zw;j7TMeurSh*fIdPTe;HYyj_fE$SuZC^1k$K!k50eq`1hu@K`>zSC9T!609z2?GL5
z$_%)nlkdk<*xlm;Gb13YweZSjSiK6-h^pF3Hv}~?{;)IUU}?8t(pIDr5mkcr!c(t`
zeMSLbXN{%bbX2{o4CYcJAgqeIe=XTG7_hB(+It~@!dh1bHHSMeJ#GlJ^#yp+4o;Af
zNSCLQA;@Y!pon+WK|Xb3<;O^kNgUh_aB2BdJ?_&rcUFp>8dSqAZ*o{Lcpsz=OgPmb
zK3MbpylVl{PWl8x8$p~!n+z(4h2Ba26dg4Zlji)_4D5q9-WSxWKnHq&f)OzxV9FHI
zL^t(mj7V!g8oou5^6i8UHY7E?)pUK=IL?}E56na)6-~A=SeQ!jgM7ZoA*yqJLtRi1
z%GFYvw?++c`o|>v+F2AKVZeUl(`S`}-{yG+>$Cw%WjE)KX49yvy=+@~D`sn`@87!w
zwt(CPbA8XFn%!hYg#r#0aU+*wDw>c3tP?1m>~_?Y>5{vw4sE;8elFE-R4#`9&%JxV
z#27$|;q?n8fnCedJ(b(f&$8zEki(6CCZ-Uq6ArFE3h~l0(1?c&i8yalS8&wb!G2hm
ztOj0r1FvjXFvP@*3u`u7BfyUbe+OUZ<`dupwNFWr1{j5sNMo9TUB_i6nY!6>M^<=P
zacSx8x$@5kaZS*${^5n0&#vNWD20oUholA+YorBh12+luzQJkWCyIKX1T5$8ElU?B
z+uiy?5q^~v#}wtBez!7*M79zJ?HwJ(vD<?tWB9E|>N#Vu4SqIdkp($W8Kh&ws*{?!
z!0gL@+XsjJ2Y-ZFrK_CkNB1f#c97@aWn(;ODO@q(ND2NkTv5!KO%19ila5Ja9}=b(
zH`Y25f$yq4702Y`6nI*ujl%Bkb>bhm7o9R_M()O4JbeE40*E|?S#s7-f?8jjzV7k@
zW#3nBt@^+S%TQ09tmET`l~a~ZneCV!dxCDS%-Ot;@4^ySDG8q@hp>jh&zhRgWzyhi
z8r+iXlW45Os%4)KbPC}2H5H((n_B<SwSJGVO@_<KM}-s8DdFl&qfm53H8q|B5r4ui
zdxqtb{R%d0P?s*TysY()W;<J1LlJFYRO}oY4fTCfkfg1ohDwEO*SmZeQkfh+_!Z?+
zaIa^63YwfG5lHb!f=481>Ac#?YEpu#x5=NjO9;dqfV$jf@X|R9uf42eY^txKviJWL
zk{4HK1{b7q-kU&&=UTxLOcJa%8Hg?Mmr)Tv!q!a5;ETN>;M$-1UKZm5TKTXWvuX8r
zVqQv?dlL_=jDil^2}|nGpM^<Oh&v4MYPm_0dPlW-?<P|2w}Rq_4J<}b*CW8=fwPrC
z<7mzRPnv_x1AWdBxh6rj_mjp^;f=2mp&`hg?gZ@83)K0bTv^boePTL>ioTHMl?C`V
zL;oG_ie5l{<UJ0jAX(`0tJ`qUXl<8XkIkkJ{zF74dOy00aSt!s<b*dGbb)r<I#Uc5
zNq9y+C6s-YPx7ivXGSbC?7C74q1w3ZJPOa5A(DP~IMGebvm?;^YsWT%aO%_h02AMX
zLB7++1ugaN#!MYuz;B6pSe8cBVl-r*skWWFqT=ls+=TyCP5!AwU1juZaF_wcym2n!
zZ#XyS9GsNPD+?k<pkT-PUmAq;b!Kz=ir0@O*Nejzy}0FlRtGE&ebrV2&Y+cmgpi$S
z>&}kNB2b+GWVM{vQldD=sICGdEom||f)Hyr;2(z7DOH$l&PS64pe(q3<2VOZ0bhHo
zG?WI~fJTb(r(y}&_M=DpVA@>Jm10Exp!+UOq)<fF_fyKuwtcI8X!x)@V=aX0pyRG6
zC9v#Gj%cI8{8`P;o4fVe(VDT6+YL5h7hsr}|Bl{Nhv()TgqIj)2P{p|)z8mF@(iA>
z53Ko1iH$YGozai^6?_3DG>6*iO)|PCKITmGFNgJo6@9sTsdq#V(rfOJDjLrSJ4O#B
zQ8^1lBtqd7?qd^+Fz62wK0cM0v!Sn&C#xX-y=_p8IDQ4ru(77yEJQ|E_Tc`UBZzvz
zob`a{;F%PSaC>n>5g$j@4wv-AdCk2cn<?GFuP?IU&(EvDW~t(p7$x&mCUwIrDZs3a
zaIr}?)R~!MU9^Rty_bpu7q?bq`4IGAk-*54J(FsouA*;6YsY{>qNrZ;JKs=w$dXc}
zl$YH~%wB=uCa8kra5W4IBb`*?q~zN;&8%M%X4Cu=evq6!v-)U$KoOeumDhz^?Vg$<
zmP^j2zuD;}<!Y<_eb7<^>QUGw^_$o-Ctq9({gHJ0Tf&6{kMWbWby(6&cxM<{qyUPF
zG3J07Uqs5bG8JcPZ8?E=!Rhd1*Db<?>RuUKxTWHfYb!*UHBe4o1{rQNyxyS6-veF-
z9!6XAtT@;8Bc@H7?+I?Y!!L9<5K6JXwBX_^4*4NKG7n3onOL;x+(Z3Cno_}}Dyj`H
zZhsRgA@LQJ(8i7qWgDpN?kFmq7m6pm{1pW?#7Lx|<3!NyHzBxAqH3gPdRF4lcS|9-
zl0zL$1kcEOFa9b_fynm&4ZLfM=_bSxwTZgq(m=9?7}u=aG9jT`P4WFgJxbl9v>^s>
z5gj8d7rIB`Eb-+>xRgcw`W%CyRhouKw$F~7e-*vG_nBC4mC?Zl`M%ew)UfM=i|E+^
zTqq+~uGtito3q1FkTxb8D12drXoX}?Ou&hDkbuv2+q%rF6G%8R5Qs?#u;o4L1s*X4
zlj#H4mU_gmw8Grcn*~8g;EqyL{7n^#1p=2!Ko%_ZgBt8U5hgBTG&ELL{e=9x8#79P
zeSBUUf8OXdh@P%xbJ1?x9yVHnBl2aVaDG*nxC3$JXPH;Ml&XNQa{mkxEGJlt&Daw?
zodA+V&9?OLacCyt!_%{$wq15vK*kyP;6NP^<W&+dqzNh)12CsdAP@`nbM?-l{SN8u
zgu&@XI*dz9G-z!uhV$evy`+A3f`%&22-LwBVMTa-<FJ}b@U>|fwg=5@q-B$G*Tzv9
zAs-h+L>x;dWXSA!_w(dZqJO9>3-&ek`;rAN&g(;Y{!(eyAZW24VhSkFZ~4Ac^Xr9_
z`a~G^gm)-2A6t`w&_L1%8R9x*FPIReqzzE{IqCO7n-_*IE1<qgBx@o5QK8-P&=a47
zp&n%!SnBX&1EDl&R29W=DIdl&+}@ENKwLb&IdT7==hk=4)-{Ixa?#lDSW(JGHRts*
z8^Ah>(Ct@3jcyj?l7#bi_t4&D(d9UbwetvHNR*hL9{bmBSdwFPL!xe_ox8EP^t<Lm
zr8Qh_C?L>3eVijN0+;(By&hu&%SSS_d1A72$(<P~^4y`4zSE5AZS59pxmBQj1x_%4
z@#<4@@;7^&p4<AvN#ucd-L-7*-*X$tEw5S)<9+=()>fREWG4&l;142vM>&P>_RM@9
z7Qrj0OLyjT+O{Vb8qhe;l1<0Hod_0Svco`DTUJ+)CQIb`Ci$1kI?cn}u-RGI{0J@q
z#?EMxh-zVa8)AQsAsMlyYj~94<B;?xwk^xE=RHD`8!{mNi-;=^j=V#%{A8J~VT>lm
zYTV2$E?aYXBlZ~y%84;Ga(v`)0?U?e<cZL$Una#suT@`%SR%@K`HtXf7!Uiw7s#QN
z82pYpb*e$$(sI%H&O3W!hKqvzFkx<dbpNx?xzFwMDiE5i8d$_muhgbkSFl)m6RLu#
zWd8-oNx?nSqBipQuZm>^ue3O3BooSL#gMMY0zU|%@P9o9K|UGZvqc^3jF2M6o=}iQ
zqp*_mjK8omzk*W2s`krg5viHF$HFoE`1zh)d*s8y(QiKt&F<x%yLr~p=KLmspKhX$
zgCZ2X<pQ2O_DExH!o9VlWUO}V`jFkQ+o+NSh|@z|nj(ZE{V~R#v2dDL^)V35*A-)>
zr2;c2pm|$TH=Iksw)SU?QR%Wx^%z}AGEklWtsz3YGvVt9__4gEpMR1G6@IduDAw{r
z$5~Si&^K;{v~D!dLtTT@)(QJlDPV{i0ed~aU+}bsLlC~4g-{Yz-139*?J1jJelaso
zuHI2KgWU=@zdqW}OZU@DcaN~IF$^%dTGg-m<qW!4?3~vE<lNQL-iu;hI)Y}G<qXW2
zzs_W!$6xiqoF-Hq3fVj;Jed%I^-)~c4B#&y$xs|hq9Pwiqq#ZZ1x+aDqC{A7!|O?p
z_m%39RYLavZBZ%2JS7yuQNe{Xxh87OY=nn90Ud;j%oTU?@`8zo9SC_7As8imwE5rc
zPc}H9FRam4F&?n>5GM@C#ZIvq|06ZAA&}miUI$cbbHk4uKU2KEXcJWHD9FOV?!!SV
z8Dn6=OY(p~9B;Q16n-qm7)#(18gZmJM=-i^B2yX|6K@uK$PFqC6S?tqEgUoS_*Civ
ziVODNnr%D7DsN!01E&#4GfS`$>|jxdRa3t7!GKL?d-&G#-XowD0c->!L+jlKRKa%e
zcx41XZfXO=E((NmRUa*s`A1b`q_Au<*f&t;*bd=Hx5>S7<$)@t)~;MFz7u6QfXtq>
z)DsSy%x(NT7WTL~W<hPGqir#=a8}>`JlShG0z!aXVZhDFzg>LE3}z#*3Q~mf%Q0a|
z1<A5u!kuI|j;o&3_}tGS{N<P|u1QSHFLV&~Jrb|XVvw${q@Y*_AR>$OC{DXdx9KaF
zyk04R-iO#2o5XRRRp<<@Rgs&EW?8%@VSOz~3f9F7xlA>Vwo*sEve$TCu4~#3QbHic
zzFBX@e}uoh{hP->^ugWL{q{~AsHPxBs8c#2G)l0Ap=Z@w8Q3A5m^`53I&@sC5Gr?x
z)sYU6-cwxOlxVbSmlI2N2l|X^o2#?!Oc_JcRNcX4(!a+2)LxNk$rBL;xgG##ub0St
z`25ouD*4sgC>hXoPY%+bdpWS0O|2R`UCZC(#*1mH&4oL?jhwTp*Hy>=0T2q84pm!c
zCqrNVMXIB+;x7YYlB-=62}f+zi$sJ>{|qOSBkfblH7<5|n3%G3KoZw$Cl7^P)YZ^D
z-69Z;A|JVS`@~CjPhft-=CpQ0KO|4jf>ZB3RbkVJSA)Z;LsZ~7J&L#>dK@O8USjwD
z4!F)tYVT#vAL?My9p=j_aY=gFeuL81)_sY+*(xs91$OvS0MYnEGOd%us4=SpDHw&J
zH!LxfiP={-kLoU*77ZKao*~DVE-YW%+C??PX75mtzGRB$3dosYBvuMIm{Y9}nY)oM
zwg2AbS)dPl^Ly1;1gFC)<aey-L&=OD4dc0R;t*fAqNPwR--iPI1xz~n!|UT?^PU9E
zq5&n?>wTwsxP1#6*fRtDsAlb>MAix{4-<1Ig9!$6W5!5thQr}dLk?Oem@ga~%jzz=
z2b17`k)iP^Jw-j0%igW2H$LuiZaME?1DHQaO4C>;^cUY#$6L=_3ruj@@*)J!Hf!lV
zTB-yc5vpu(qI0p1LSCDMoZ!{JGYMf2W(J3=?MW4w)Kv1mRyg)ahV)4_2>W4$6#<y2
zY%a6J?15xw39-UYc-l2ZnmtiGq%aWBEfu7y32lK0pJD5Q<~FS&6!Fvp;e4*25mm7E
zDVZSy!nnENGx|LIg1(!na3aUJo)(w0{d{h?%H-nm_HBD*>?3Kj6MQRg>7fEdoyRFf
zSC%D<8%+pR>VlaP<)S0dFYm*v1oDpNzLUaV5W9@@p&h8MD1K<*h{q>rLXZO6^5$T2
zU*&4`uVt9!h#=kMUBqU#RzdWwC6wdzgn>WNq=2{+o%AF1$kiblGhV5QtF~4H=wPTs
z9)0*~hIqS!<G=dA$GrjCz$>~Wr%Yt)0KAgGmo^(S$MVlmi(5iak^$<e0-=@g*>Fz?
zv^i{ExW5!2eK^8rz*UEzdB;bLIPqOP^50{!GO}ar&jOw1fEBpv@;?vXx!vRg%;MZ$
ziRyw)lLs~|O6!<;@86&4%_20vj&oyb)=UCARI%)FfcJumZvcqkU3Pk<-<`7ynE&k$
zS0Q~v3k#p_S^ol3wW-4O-bj(`dVA^r_To95G}Ve0W<m~>*4>Lbd)l~WnKy?2P?m6(
zAd!VvY!q6VQX8@dOv%v>0Bv@IgFud+m2~ODA(ehcBg!WC*6Z)8mv>$Ro!HO9_pwHQ
zEhR$46(!7ziN#VgVl&G_s2bUkC%v?{1ne{KGFHw!DnOU$?sIlX3Aq_hFKB^v4Lhuz
zJxQz`*<q>w%#{_Bg4DU;Zl1-6Xpiu=gK|5u4wx%G>ouy!mWQFVZEUd+vi>0o7dG}2
zy!&6pYUf6Hgq<8>04qLgH~XAZ(HrUI#)%pe)|+G`$0Wj87@N)df6U512Y0>Esz`U1
zNu1UkNpC^QiwH7olPJydBX$kDQ!n*nfiaMZ+P{LzVSEq2;Mi|gnPqKZvSv<X7Vp3&
zPxPc_Q&8;urh430yunsgWxsijdr7|B&tpnNg^Qi(BIAO+LPP;+BwuzCENc+~;)N9S
zC6-&hrnIyeLRK`eg<83&hr{8L78yd*LRFs<$V|Em;a?`nb>HW}7^G%+D4{^<^g0xD
z_27vzIzSyu69jDMmZ0c!R#>w(ofB^?ja&z79`kpt5n%{z(P8`<F}BS6r9MV_Vs)Cl
ziUg}I8=D*Z$h3#o)z^ffru4x4>+l;cHPZcV`fQp?R4j6;x>6G}tOl$}mIKyA2oBwm
zEhl{)Sn)t!E({O<pn=0GlMJ4y;bGe7Va1)#YPuIsTeMEXI`Pz_fJ)Qa<AIviRVDW`
zV}W-Y-JfHZlZi7p2<vsigSsST`95OZ0|38Tl{7lSG}v~j+RfH-pk2fOHU=ldnQ`<Z
z;<|&X{*yQDx92c0`4se~Ug>r8oJi=nDMrEj2(x+ZNIoRfCyd;mdwmMrtul3ZS~p+!
z)O=x_x3e{z`xhGhP_1$^=A|VmFZ51Z^{JTHCr&){@4N~!ygr)|VOU#M)KOG^q(f~G
zJ!0qeD!NTT<ji3>1~|E2r!+x%wk93`fWT11F2rarNi}3VPi3>H;EA4pN46B3%;*n}
zt?#LLag{ww)Z{62#yKj~jd?&L+E~*6S*ZhqH11@R(vF+*`0;vqZG>tK3moZLM672j
z_IU$QX*VXt`nVROyR+t!ZHcPCAK)C2JRKh?x#0fWzOk&YZ8Sz8_~GDpaJlEHz;BT8
zS3~Hd&hx_@rhe!lBcbfK>paj6f*%Mz!K(N=L1Z@?CTm#>tXo~123I0YO8#>1C<6kC
zkkV5rZ1Yp-xbkBz_3trCrqwU$G(15b4;r6DB73~|^DUMU@x~A^8&zq);?vQ#eIhm&
zA^+x1m=$4+@)nO~HMdNk9&rp3Q10FNB)%pjWa;~N&!&uy|9ME%vSL~Q)Y(TI!#y_J
zTgf{!gKX(Jq`tL5{xwlqizB1XqXDc^X$j|h2@mZNQ)F#b`WdVV6zo)Ywc4czFh$qs
z$mVN@>{MimQS^g?Xl_EhS)lTT0GNQEo?+i4>|5rp2Q-?cUWo#;{IWdyZ{!d>ptM&@
z`4RL)v@*14YP^}lY&|H+lC+P5QxVp_$s4#TvSy}mluT%ZGG}U}mQ%G`8LLRgD%X-n
z|K3;B53U;;EksYnLl-u$qe>vs9DoqL^}(`B+7!4k=LCckx^$RP-ggB;Y#z?X<=&Fh
z-P8B2vlUH#Vqn8Qcj`pvj=pLQ9LHSb+0qTfIt;E*o6mrNX|~P0I-;g>a|N6anFFtr
z{z#&E%eXFR#!yo&$hqQ(fD>eyIuKIi^>SdvbyViII^C`}f^$&AjFz#l`J%HCl6M&b
zoaU;pYn{;((3O9~z+&&>0f{Pj@Gi~UCk#>BL;`Fy>)_>c-Zw>3Ejn@mZqwQces<p9
z!0S9!!3Fy(%%}&>{on6H`yUWiAQUSa1<aZ|Kh_ne(ms+co-969(EFruEH})-BOBGM
z0!Y^}X1B(UKp>mIr-Bmc2k&v}bkn1&cf(%S-t+?&G8dz?6|$NbFPo9bV~k4??eo?_
z+Cfm9O~`F&m64T^@pUpHokXB%rE=cNP6H%fpHI^XZVbRHRF*x5GX*sn(BXIq|NNzF
z@{i)6%*_?>t;&g7r7^+F-9`|!H_@;VAHE*~B&Ei{XMgYYcB;QF!x_}B;aU(bl6!>n
znMm5=^KzE!61(ia(?dGbjYULGIWk$C1-x7#>BJL9w7DuS-+Uc-4gsHO`h8<t09>3Z
zxrJ4PN%raTj+Va=ZCZl1({ullXBXzTkJnAo{%s$1LbL|i^a1f_p+k#J0vaW<cJ4gU
z&`wm^4vF8bkMeFcoi&f?A8hzca2xg!$RjcX*7Wwz-aPj)ZNgsw6Z^|~BGR-znXi!Y
zEre4=pX?KJFH#xW<(3H6u2_(xhbFh(uM~W%P_Ck)FIe$hy-r|hf(h^m^KV>7@Ya6D
zNxaB(+6LAXz<Yj&9IJ-mI8V8I8DPC;=G>viiDdof`$!nu$&UuQp<-reYgN|8d6lo&
z&dJkHINJ#{jH(t>0QDk!&H6M}qSH*>IE2NmT;a0a4JBgoKG$lC00U7!{?-&C)3Jw>
zWRQ1@XcP8xkFe635_rmtaPhB&-uWfSR8)x>!No~W0>Shm6BOK5oK^Sf-Ze5IVzTQZ
zOn~EDT{cWy4e%O6QYs{uf;h*)kHK4qro8}KtiIAybMa!_Ld}nz(A1Itox2l2wXniG
z?JMSr;xIryFC$JsS@3;h@D5Rkwi)BincFS#miH@kVMpJPp?fS@mZl^XPj1$9$piV8
zmJ$~1?($GHh_z3LUW1SMZl8J7eUNJPW9wCcNYtO|W~Tb^t{;Y!sx#>V(%ko5=Pv=g
z%Qu+S!qC2w4l^Ab3yC%-ewt^1r#Qli4>|_{Q$8}%Gr+Jy^Ea2gDmf^0eovG=GBSp_
zA+~IxJ%D)a+1RS0sjMOqrs|@W^~>H|JcQaCW6sq3@IeFw97a-wYKzWNvOQO}E}#?D
zkMW<O$rGKpq;hcmxO(7uzyjI&+V!w}M!Ekq_Gdnk6TH8@#Kb3C=%IT;-Fy54snmmL
z&%q1I&XiiV@`1HY{-GY;U5_+->88q)sHx^e(@Q%RVW0f6F>dI0D-kKE)J$0WlDWqI
z(c1@OMu)r-3w3`+P~FVtCXmFFsVC}@&N<l9GsRxdSl*6I_T&&xeM*?l;p=lu2bcW&
z5NYXG{ffUXo#jhrM1a~&{`FPMHg+1gz!hR^k$@xUWP!iV={KGcT^~VN$Yz;dWoiDs
zHMkcT*nq85bsvqoSt7|zpV?gV!DryxUD~gx;KHXa&);XOlRk*1a|lkl?_{fU$9QcD
z1ux-<?Ijaabn1^a!@w&F>M=3YUkLqD#-Z^$c&}vH+-rJysr1e>(3<wo7Z<eo;|Z|+
zZsv6*6uN|7naTXm8j?WxCI@Gyz;h-uGDtDBBflO``{*MSSK=`X0piGFklhbPR^OFm
z4Spb`4c_qQ0Z_mj%1JSqDx*S25J63n9hezwVXJ1g>~!|CmF+n30p%2kRPu=MI?K|W
z9gq7coyZ`6v;x8sU%Z{rFa0fn0|ZVYBHyH?Rm-t9hX;*%s~dEDzNB#(jGMyyGS1dX
zRGC%K)v&<r=hL_6KjE6=rgE<s1Suik+%<Mu0vGW1^H`eR!fs~|^kBhyYqQP=*UUb^
zPHyp|mV50VKD^=r$Scu}#zyVtKjhM4^Y#43q|ilDlp(Q7<!q21n>5F%iWQCWpp2W0
zyBKp}^2!5l84dfrEUaA2m$x?H8&}_QV<O)Ng7zl`MoJu)-Gz_)rXs=yGVY_|EcS%3
zFelCxT*bq5#9-iC$87|+td2DMmgHDJPKtR&lcDD)I!eI<mRsg7BF_BQqEv)35=s@(
zum$*1pXJY(v%JkWi{w$P8<&9uHjgeOr>dD`eE7e_`^phcB(k3fS;;VD_UP{J7qtEH
zd~nqIPhhk}XmDr~@;G1m3K49N^-9er_^Y&Y6V&sdq72u&B;Jao`*x7ebml=Za;4AG
z3Xm%EeD)66ORJHON)1=4P^LZ3%haH1uVqX9dhme)kN;hbxx-M41wtpPRQHV-$r(iT
zg+C|?Q~ftRiRl2)D#kZOXjpb_;_pnoC`W2K2|<-hFoTh=pvO=6*A)63I2D@u%8V8m
z*W>RatO#!<Nv+L9C<r9>(q7~`ia^W9+I}5N)wMXqpu^TI9Hyu~*yai~ru<7zj<;q*
zMtXMo2=ze4z^wtA$-P7(dlZ*;5*C3|Y>7i)i9GYxqofz@yWMspj1)CqE+`$cgA4F*
zKp{sX{z9rq<tkLA?v`v(YF{#&sMjIWkRp-^!>lWS3rwpf&>%;$^lNkG?uH_kTOH~5
z=2<i_&%JFbR+P*&7j6CumB%1V>I<&%E5?rNvJDFn0RZ1KPZ^Ncr{Q`MZbnN6QR7)$
zsE?(+5Ii4Q%k$JwsaO!8$}SX&;$8-W{sMv|>@L(h5Z8T@&JQ^uYYf$+%Btz}h3~d-
zoj`L}JBsKTp8iHfBQ#LM0-`y<GFeCx&H_nYs{toMCouhik(}0E+)VS@n2*imBkpN6
zwPLCdMX(NsreMn%fa6BCSx!>boTh_At^g-JLS=pk3<g$HX-_0CWbtIeMt}8N?8NB!
z$X2{67i;eu*~C1f?OPnFnm?3@?jl<Mi$<-8T7(%tMcZZTgv~O|v`WR2AUp1SOB9NS
zXTc!wskY}B2_CfM0jerAo!F;m|3utdbJJYTV^t=R0+qL0lbbqWIaxo1W7W0chd8uN
zJSl=J3~u87=|oAN2MT{ns!Lf!^Fj&-gdvcY2MBM`kEBa|Hd{s2;rb2~*iG!f>@=89
z`DI>tc^)Bz$uASE&SN71Q+oFD9>o!C$J){@;<my9s|4`&^{rDSA4P~+?BuUVQz<vN
zoH215rR-81`iJuTPsrv6@Ip}IJjz;@lMZVuj<y;jl6C9xcr?z=4?<LSt;eK5lo)A&
z2m1blJ$Fe}{jG>(Bq9JZ^|6H5LSUREakfT|DfkUCSlV$gke^NCSB@k@q3Lk<f?<go
z-iFXcMCn9OA{=642NUXEGjj61G`*7MFri(fJp1A?*5Ja)S#N$ESf)>4eEJ_U5}0U|
zt8bR6h<)3m^gKZ>85$(EFU$4-78o7uTiwwss?b?tRp+I@(Z};QFfGE0Z=M*JpGF4_
zXDF%hLY;}1X-NZCql?97pX$kkv|d|LLL$khGteiTEP}~~EoMN2$y6q^DlS`QZiTV1
zZOUWg)NdC7$|1dj*cR3Gp>=r+&cuh?AK{yKP`ovbdbEE-B$w~{QSXUVkT7stllgmn
z+dic@X|ZF-R!o?40xaRz^ikBhz692czST1V2PML1=m^{!-ygK>EFid_F;LwGIRX%A
zkS!#s<w67q(vcVo=V{T*H9rXDU5Y=uGzXG7l`fC{e+iT%Q*Ey<s$WMx<)RI!ax+|6
zd$7<y)K%O2#iJnv84tljySO(X*FXl+vH28K_#rgwSgo?GdydqYb+SDt7U7{!c&J$p
z#U0;wPCj`z5VV@m`C;bXQ^O^bWmDHs^%B<VA5$3p;uRFh!`9$+Y0biBi};A#fjpX2
zl~nptp(?XvD|q!l^%cV7R%Vtv<`^aYdYjQJ#A?X-G0WtecItF0%cBj?y%lzIlEolc
z926JQmm}J|MOj93pa@V@+U0)F_GqTSJ}P1eIT7qlJynh|3fRs5b~&y14$HF2q4g7#
z1u;?(Jl{3;KRj_aB$jokx7*k0m|d^A#N^?;AP#RHMjljFjUx>Y986|0x03$57euCG
zQJS(|H;b<_Mu6!afvl3QaD)Q>A2S~KJ#o776!G4~(;DWjElc3dMhwIz8jTLmE^zvf
z^~)*T)f3MXZH+|7+5nK3SyVKU-!rLJJ>!1nEU8^ZuS#5_xERmb*@ZX@G}Tik*Dahv
ztBdL=Fzh>w>xkx;q#+0zX?e8uUWj#pwQ!|n)I>~V^BrJZ*jO}xP#y*MDtp8`z=xDe
zQqcnXaNM?K)uyV-WhXAx|IWQl#{mhdueUVLAG3XGJKGjYKT0@uavapmQU2PoIyr1|
zJh=KX!QC;n!=FDjSZ2D}R2;<vACHiL5URtf^?$*M_GK(I`9;2*@o1K5naPy5F>?^Q
z{}2#TE}{OZeK~X6m$MzjH<anG;dO$F2i1g;M2g<qZ^L>K%AbkBa<~p<Eh3MT2ZnmH
zEORb=q|g}9jI~Tv8_XKRjI&Uf<S=p=n?}8O{xGF_RyIr+4EwtE#R6Z|E1Xz7x`Qdn
zwGD7`+<KgspRz{4odd)YmDB#(<|DYReLXDz%d8A3Ed=Q3d6}iKb0NZ##YF%|??Myi
zDU7aGPDY&pOvx^UhRMwrZd*K-GBt#62twP-vhH}Gc-V{3Fgc?prK*-ZT_H~=Wia(l
z7mo~IZnSwV4xIqDtA*o9cWrG-A3U+3o!zKP<p#rz@-f^mZvwMju4h8yOPjfczCx!U
zN9WG583}lVVizMF$pPs~eC!*wzu{A@R`Y<CH|8D+x`x}EpIs<4`;a8{|4z?&Jcg=}
zHY7&#eVddO)%eApb!Afu&Zb*2n61nNzsw?hVq)Nq2w%d^)u<TU``2|Us)W3F)E^X$
z8-(JgB{z2dvMq=JCGIvBEW3U}V{wy_Y^y1J-TE}<8FqAMx6s&gfLCu}lOc~o`_Vgr
zQbQ5S-{&1sIao|(gB+`8@YYBvXFO$drb7F6HH|wUEWhkj{Bhum%{!1_3X1LeM~4CB
zE2Ap5!=ZZ5C%<bDklWH=1txyxpJASIkGd^-V^Vo|XnpL1h7d8R*Etbsb8iHaNG}9k
z7N#mqer$<%g`?yBVbMEh>h>S%4PdHf+9=?TOFXVXC)etRw`^%m*>D+QW!6*J@?>{b
z?6q{rfQJ;>#lwgf-lC4qk{Za_Q7-t@fCp+9%$`$rt>jnX>FYo2eJrpB%O<P2$JLxD
zO_XpO(5_#|Iz6@e5Tje2X&#eBA+t`q1Y&fZRkMS@;*3oz`Q>$KTC2C*+u_bn#nynM
z7K>duD8OVse?`!YBdxTf_MWt;;KvOuO}td8Gy_866(=nJpOctV*Q~ay`&QS=@Ymfa
z6F)-))z_e5bs23RW{z~M|2q;pKDq+&$Q+qEbHN@Jvc+~r8^UAk2g6Lfbfjy{Ko2(2
zX=u=z*rC~1It*r1;k_-m1h0Wsw%n7^zQrou_^E%plV1|Q7@D3V!){*`Z>cKWW{N;4
zz9s8O<Rqp)eor{uZTpA)PSZi{;9D;C?H!PBSI6y2E*w<IC$=VFw<=^zv$6tJ87I2o
zh0pibqq6<v{)K(GSNNrpNwktW^XztKtN;VSyg)oVK{ZQrT6X{4@2Bz}@%Qnx5Vvu4
zh8S@T0A?$O1_FYAMoR}sM(QiQSP3CfU;@iO;b0NVT{V|N=0=Z%M+#%KqATr2E^{5q
z!<(3PnkR)Sk<tCpiliv0?k;=lLtwRv%cp3OT_$~_0qw`HljMLx;dc}^hnEse#(Yn_
z_a`*1JSh2mKbBtjE&X2;+uOEJ@l6y(Gb1c!f0jGSU0Qq_X95g!M~rqEEV3dyMq_Hi
z&G91H>8GSs|Lhb_se92m#FcG{ht8Y=$S2fFP_ugck?pVYHhHl6Zx`w+{>^`UMQYbp
zEQ`n2Kx;~>2EptnA0zNmuht&?_GSx87)5-~d`U+6aW&zpwxYjx)*15fIv|mGx$<U8
zDHzv~t0{-C7AmaA64ZPj|1|H=Ib_6RQz>)Kjz^gKJ-0`;1*_34E`T&W(13jJuA<}E
zh#xM>dpc+9IZmn!LK2_hIt0EzN{@1UW3`FJ_q?<RjqeM}95Zz9Ak}DN>dnB-m?P$W
zK4h$1MGGcW50wuJAM>b+K_H1aFqAEgsy*=OqXma^I={GM2RQXWiihAA@7D|ZhOZDI
z4PeD2yWSHC7o1rYimpm@<WI0|kbd?M{t6weOauLJ52$OkT74ju*(X<jjsJlhg&Qtf
zM$O^NIgtbWIkb~`TEGn0Vy%0I6D*iW7{xsJi$c<(%K(mf?$l!(${ccMG82xjk9QRH
zeb_G7AWs@u#OuJxLp;ABIxEz*`a_Mjr5Oi_fmo=d0h~7vbGu-605GS8rgXMCMRxBa
zbN`_+9vRV@5VjRPY@`szh~I{Fgi3@p3T5XJ^KXNr$lvzvY9^$&#Prs{^eVrEA}cm%
zf(1gyBl*aER>H?M7UgV3Bo|ea`4;9pH+OZKFCNm~>l82-&FumWQJ#ZF*PTe_q?{-Z
zBODbjE9!p!nk1Nt&t66OL?5(>nX0pV0_H->@e^D%1(pqin>lJrm*ZJJ1%wJvJfiTi
z%@_+Kt_S^4S#5ZL%w?(B`ce%!hD&g0^te^Rz?Ne@=17<TEZ13Sr4#c8o{~c~ZLh8L
z4eW02^tsjc;EMwC%XY(KV#OidV7=FU_;De;R_@2r6%Ww2vToEeFryS&@b`Pk7fGSZ
z1OkOglYy>aN9(SeWVI_joyx5-E7MkWo;5w-vEYs*5X}<XeQv@tQY{<Eu^7)e_Ja$u
z9s*$JWKmg)lXLWkl^XkB+V$#T(|bPFlEJfE2p-@U{oU1IMH}y|Ykit~ENh4sq@0w<
zvgN<f8YqEpFusaZKkr?b0Q1q9j&sD!tJ{{CB6&$YbnV&YuvGjNH1n7OCD)@=L!u<H
zrNdu|18$^&%(Zzx5NQ9PK4kJHiZjnnyH`cD@voN&E{S&(RR1CGbtoM}53SUMsm3Kq
z$i+OC^vW=%)0wVrHnBWEQJ9pJ#xOjkf>SLLd7R3kNGC|JEh7TW_I;+og^=S$FoQ${
zM`|HgjmmA=WY)n+>|?Nfjez1>*N{$;NGcJF{KmuOPXQ_En(@zhVl9h~j5*>9-$|tv
zi!+E69ozM8+2tU9*5wAQuLgw}ad9$H>%#J94?VaOfuDHheKw2XAbS5xq^Zv;wBnH#
z#Dan~(Jo+vPYdZ)7m2`~&Tn}?bDLuJfGu_k%n;F1hFTC28*bwYKcxAPGkqHdhY=y!
za>d!7p~)L@)f1H(9`uxEl9!yk!5`lwBrKSOG*lu79%kjMcQRPnc0l+QM48Me6QlPc
z#3tb7L)D>gboivhy~xoH;y$Dl8up@L1q>Ux6{2ddjsKt~c%lJ;y&S?jbWD4@Og;Y%
zo}L|!e@+BLZ@YTCp6u$gtTOTdO-9^qzP%?q8J@F957S`rh`+FkgFXHk99t~S;m{9)
zcPR&`#qPo5Q5{sh_`@W>caz?Da@xb*F#V(=CnT8RmSFcR$Q4!kJZYhOaj$Uciqws0
z;B{=KT8t%|o1iTf3@)dl<MT6GdM<^7<gWRO3cIG}Y}-n%<t!EHBJ}%rU?J{be~=kG
zvPilJte!j?=#M1=y)BZynK9MPJas~Pi<OtClTE)-NCM5p4t_}G3DohNm>FK1uIsgR
zy$19QDT4PHS9q?sP6v-duLp19SPfd5>2>Qyt_mK#=aswtw4j<EU{2UvMYk?7K=S&d
zjOOxFe4&48>1ee3eoE>hO?HMlB0u$L>f^8VO$<MO_$Zo6hbd1af?(NvMf-<tPp)Be
zueNCEWo;Swg=Y$u!Qf2CB6G>)oS7!q-X2O^X<cw5p}|*mcvFeEA2NzfF6W7|Tm=4c
zEJm@_gy&hd9UmeD)JC3z#c5hl`76nL5RCL4nKzrS>)@qvd>!2Kei<@4Whv*Y(>u;t
zv%8`9%pjKkd~o~XN*1rHv6GQCmZ*`aF1H_j3N;$~ym^NX?xWfP48=ZNyV%H8g~`zz
z9;fA<NNQ(E%({&SGUt1R=`muo+wz_VzK2xdR`u7mNvh3d|5PNT<Gbmg6<7s(-IP!H
zu0Ek7_MIYXkNi4fhYr05Tjjbs_i$##C|X58=vjxW<Rz6+>#1}!)EN`@O?;-^tKl;e
zA+Om0sDl`ClcGbQMI>djprG#+;#4b(tXA~smN)rrZ|IVtQD&2{dN^A7wUsA+15=IR
zv)HsTTsd3+WE3))F_Qo@K+L~*UsPy&6i-GhLj@pOjEEQBLS_u?^`gL^#!^de<|3~Z
z9aIfCM~yj!BlS;ridBG3Bb1ojz@jy4F|b%Qc4<wo_f7m2hS3lUX-Cb0h0n}3eC(a>
zU?C7e{_f;?8zK5D1|qaGRXo{fD$1fX7hX{faOzWON~2Ssb^k+^?rDOy`Z`M~;{jN2
zH_AxE0Fa{ouDmBor#Qy+PrVM`w=n<j%149J=CyZIQ~~i81i9M-ll_erk8LGB?_+1^
z%-EC(8p`;X6^-V#Ix25#FO&2a)n1^RjqxR!tNrjcCw!d1Wx$LjEjw*Q(weLX;v5eV
z6(sSAqW0j}o_F}`!g|4t547s_BzROKknqYf0bOABX@N2WmNf8IVDf)v#2k=v^Vwe{
z{7vRuib2$Joo(E|0}Ghy?GiK`K#=;00wH*2?#yosXQ!PnKY)O$zF>n9737B5istXD
z#}p#M){*<$VugfE5ByPO;*Us%htt<1RjMDP<Ia0x35ZX={;~~nAIlUFp|?Oua0BQm
zl5&%I@sC2cpP>L%HpSF{(o;t-Qxc5h_{1-LVAuBh0lxe8!#Ey;m8gJR^F5zCBsYI}
zF5Sp-Mol5Yy(US`Vd398-FJr{dxM<E#h{v}RV9to4b0YnoU}zy7tdXOzEdN;dG^^&
zh-HV*>Fwyaw*#yULYQxF<V~_%;8WKEX2Q$S9g2-m$8(@d3MH(sT^9Z<`!XWh@?(Vz
zk-ITzE{63uSqT!x8|BzE(mI1S0ioq72;dW(*vlhpKjBCeN<F(UsxD-yhl*HdD`^8g
zmj(p<uzVOqfh+2{efgQ>s_m@xFNf>Cs!A}zK72u)Mo@Yq3xWZy=>_rQ#S&{y<UK6#
zqu4@u^T4^gKSg<Ou1l!wC|gycYRLa*@U!|fEXmE?XRlkAbONoNkZxE@E-aw<wv<FL
zOVE*~>S&NScu#6)=>2dbtndGWiQAMhDPmy`=IqANJ-)?aoh?#F1|2;a;&PL(O1hz1
zr;I6+@Zp>Jh(6SsTzMPfBv86Mm%tfkj&&8g=b?ZBf6SX=GTX#XQ9Zu;TyTFGjU=kh
z;8&^Qazj}M&DCyRuolksW>$<;`E(FD%KojV7_B@(&=hYH7}|gxO&JhCM&!zvoaQfQ
z{bpS&rgnm%K9$^Aq?J%ex2_3&hFpO)_}l5KBF)i-yE>XiG-kAAEt6g`{qJn`672J2
zH4a>{l|<266Oi6Dk?$emJ}j&-sxk+2RBkgn8BI+*QMKF8O_5N`_4>=!K(=ttIQ;hu
zmu-I3qAEj>T+p7M?Z^E-q%c2~E=B%Jy?(tm*@WK+(JU$o|2H|ADrX#ipZqMvZ}ojs
zsE&&_-Laak{)(M2{pZx(AHfA?10FRr%h)+c#1byf)1FT#rrScm@*{kMy^n)5K;4%#
za`-s)d;P{cNNMlWvwVu~OI?d|mua8jb36>yHu$2aS*)sKOo}~I8zb8m2<>UYDD{i*
z0TEoFhvX~(Rcd<E<zuElfykjm$r}S7&A^l6^u^hP^)cLpSgCj)rzBa(wv8O08MUq}
zJ%EGU8En%}51K>oicEMJy2Xs1>$(=pu{#wuo%)%iq{<~**Mj%^zWjgx$6<s&lr%_I
z3z||2d_sSC;^_JQhg}U;;NfKA)-Rn(=lShAo~~uMhzEv2=cqxuanWu5yksXC`h`~Y
zWKroU`)B|n+i>G6;X@?pP3ghdq{64rQ_JSk&w*86z8L<bOPQorb62izG|@S9MWFCE
zXVc;y&tGiZy!ajiwa7zhTWP}ta9sdL2hJk3u;Y593=@gvc}$@oAwrWR2@@C7BT?yP
zwUPb*0DLCGqB@HmA(8uTe>~{WxX#>eKL7V!6gC@b{m`8QkKRbuL<%Ms@o~oY<ZZnQ
zxEE0|inKXWPCPz!`}gGgPJ!R|q=b@cZ4$Vi&{+*MZ48OOIhE6UV<ye~1qjz0K6oXc
zeXu`Rl`%xoQVp8Y(n$RnQ%*ixYNSsjEBuFGjaCx8lp3`|leeI1q&P~lSYv^n-2#bQ
zUZH)_j5tM{3ci1Kt4o0i!3-GRwdD0D(?5P*K1*KKE@fT^lIiXd=5B&&t;g7@vOF$>
z-R&5ulQ(Z1I+7>_mt;v5kUz&9mxaGppCa@e7dPba359%ECI2+YEmTu<>gs88W(FAC
zk&{D;L3lwJH&(V`gzd7GvK=Vu_ENNWB;B51_Jyezpq!mpY|NZf6HpoWwjR+E+pC(8
zW9gVl?#c(+EA$&$#Yeh8%Z{8y69CxHyqk=|JwB#>gMcP?3A@G~Wq`DK_~J*R%9PY%
zD7dMK+Ly!p4g$rVqVbYKJXaM_Vd7+fJJnOOx=oBhE>Y*u2qclMJor9lWf!&|X&l$}
z{KeoSe3$b3Uy;V8FUP#kP@xd5RI;F^>2C6z5Y!e=NUU}zFmi7*+c;D~achs_p3_^D
z`n>96@g)#p5$Y|{DU8!kMj$|i7lN?~UqtoZ-d)0KUvF+sJ^WxGa0=fY4(;s=MWagC
zudQib76V(8S6&*^eZXeStG^x@gonjv!Z{}>bDpSx!Ju=>TUENg!!E%D8y)X7`&e!&
zA|pH?Dhi#SKBjs3&R^&!g~|g80`>zgS@*MeD@Er7tixqym!(qisRASl7zR=%up5|@
z^+C&3u2v9Y`;7|d#jR%{hXB$Go#~ifN({7p$D#jWnQBg)?jeWy;7Q{G+stR!US4^S
zg@EPEsUO4z1Wpz}73&Ew6}(_qJ!_ylG3QRgmZd+esYV8=HSEo9AHiir`mypkN$b1d
zcl`a#cO_pp5?>7c4xDmXuRI$Bg%{o=w5e{2{!?ylVSg(;`kJyM7Vc%BZ`B#v&>0JZ
zL2tgNf$dHm>F2_FwB*BVVk&wqcVr(*F&HVx`ruge#N}3;l<#=~UhyzG+ECAX^9o90
z%ma{Cx~&@O^)~vZVdD^|)ae6rk~Xf=BhOsmV55h;r{?2-^rr(BlI9ew3%+yjN%(h5
znN_%roYAdLuC;eb*@ylc$EgCf=Y~w)(1lL_`}g1x!}ypw+FDRwN5a_dL2;0{kyz3s
zc?muFC6;v|e5N_VMX5-ec)gJ=1OT=tw7=ZffZYo(COdB?_Y!T}DyOLi<pC{_)ytvp
z=;=W19b@vUKk1{VK9*~JcpA`UNy5qUHoh2O<BCih!KZ*GVZWUc9(K*?q5ihl{;xk|
zwGG>|U`MyBw4oU_13wa67WfptUSEQumawLU@17gd+DXK6Xb1|@KzJWOp_suGeJs|E
z^2zrD;UQ7!&jp#3+H#u@pF)$g>+4M44o&U>d8fff{grps%z~2zABbt+2B|>B{Jfcy
zi4O!{i9=KoM+OID_Y@^WtRC{1Ya+I(9(fJ~;7&Od>9m@^R*pKzM$13aL%S>;A2lgB
zOM^*SeIEbc9pa#`=OM*dA0)u4ZBbhjUwENH+f-&KXmhB^^RxvjsU=a@DVN?<Mq;vi
zSqOiUk(emtWRUgaCV|x8+@kd>DN4WNALBa7;bh%Q@kr8}!4WWjv^yPcpdj-meCUCB
zf1d&Eu<r?c8a7fBd^X+?TKP*=`E9%a6#$F`N%qD32<?d3f@>LNazrD?EHG6|IuKCT
zW>$2crIYgBkbSQqrqUXUI9gq5|9rSrW_^oJjkxQvwrETIz@}Zxq@bMaE3Vf@+5Vyp
z7KDeQowOS{&1Jpz&cN5G^8xrlN{{${E^IZm{YPGOC|tV8$%;|_pZ-PJ8E<aymJPl1
zHU#%Uvs8}aYDc!S_~{$;oi(95_hbI~(UZE)j8u_sACg<@(S(P(>f8D5Akr7B{!1=>
zEv`{NbWp+E{TUj~zGS8TrkX~^!7RR^(lcBtm*srh>Kt0|$Fh9PM+~2%e)DA<*kLlB
zM`KJ+2@vt6@qw2|SpRoUyr0lc2);IwjR`o(fd#I(BScU1%<JFVSdpnpXj`Suv?db0
zb{U>~ss+1_p~lZV+ZxY`j_7rKdT-r%f=;Cd{C#TB5;t}ylly;G*!;SSjwBBJQp9-b
zt2zU}$Smwhy0?iGxeb$g1oTT)8aLZr%$~)B#=cJ@8)f~>myMR^WxgeAjZ=bfd_jK-
z_(<u-g%e!tO0422Q!$^vIvd`sG=?iOY~l#G<!rBAx9L`ig|H-NHj48#>4Hdw%Vq9h
zPXBx6V=$QaZu;UP!1N@HwYnqy{DYh@IG+V?sxc5gC$)?$t1S$l?X}oPcQXd81Z@wI
zwP+HlmdE_bl2=3vj;hb(oRUDl$o}a8VTk6NYtm!LQ1U8;Ft%QZy|wRx68{dh^k~g(
zks=NWd2Yrr8-$Ld%cCQB+NT#!UPyjJ9xvvRUeCynvQxl>JC@mr63)Tv=^M!-U8&ds
zE5d`sVvpBWVdN9E=~e+#nQg!$M#AVD8CXcAOSQTgciJ?nk-rMY3r2_|)(lt6iNC4d
z5=U;hgdrE=iCTmgs3~-SNTIbr<^l@9)pU8E?bqu%3SrM~bjH9M{X;jFX{&fb!CSot
zHB)iz#fIC)Ks6w4@rP?$i=*Ss0lG|@?Ag9DLOELWy2Vwg7-^1sQaKL-N0TItlO?1s
zc`9$$1M63_28w=)xzc{yH$6mDrGq4maR!kW2PasmTLdYEJQ}h#G5=zxF|J3L$f)AQ
z^be`8z#U(CboS$gWT#6ZM<V)+BEl}7ltKmjn+7=|A<1^IY-!Q~o~2T3IpG5e)nl>i
zrzy7YlWqHK58AcUASJ=5ex*`}HoVEfhHTc2+UZiWP&Gt#mbaFXVJ61481+%qqiv!N
z!D$>zANd!rJ1s*95)uvcIIKVCpH#L&zu=fqC@C%wA)vFB8{?Itjc-3uWU9*t;r;K@
zGHpklE2cNg-suUvMc?kcbKc!j&9<c2|A>Isrrny>)E7)dtNUy}H`CJf?Uni?c>6a@
z*Hc3!T>;$?oOz;4so<5?O6Q&6PLL3DkBp6MpZELy@P+dS^h(}LrXR9?+?*EUbSBEZ
z*~*M&)a3}9l!wIuAKvDwZHU#mjP^@|atMPAddthGL52fAHZ#}!w`r#FE0%UYbmjEJ
zdzaCA9HY_#cQX&<9K8t{nw-yM&o%0oG~;K9B&2+D&tB6yPlhp0!HKAf&PYX47XY*h
zE^ygk@Dhp(Cl0csP&=-*uW^?GvRmU%8J^o_7CCu9^Z!$^$^V1CQW1Y#e;^2P*7|a&
zFUw+EMnuAaa{nm#39KbIe2I8&0i50gE3E&W&7eWfsg<m%yp_vW55k~K;@-V-?Q_Fq
zt_!9jG8r`+8%cKFMH0`)eYBvC!KPcE<@WbpikrE4*eX%KQ$M^}x@Z~Z$vt3>UXbU_
zFS2<=2mUWkKvF!roz!6lPF-Lm&$Q7Lrf4Eu70?P?^pbRK&{R1a7d$O32mDggSHl=!
zmDsD=D9e3#b^kcu5go@c`uDS(jTqoqknUO0@(F9TcYjjA#w5t<XTxIKo#IT;Ih>zx
z_)mK;wCrV@%6!9cMtaqWqHoFTicul%1D^;+8Cv}@YchM#GNb#UmkDg$f9v+Jww9t!
z2g#vS#!x;vS#>7X*$p&HPdOx57>_Jzr+Il<Z~gF}DSDbTT=$EqC13}sx2Nr&k?`Uj
zEdjL#i(RuW-4>HzC|#G5n)LDBnUzSR|1%d2qyRD;=?Ij~se1nGV%2}}*6_8Y4|OG-
zoOvGo5xQ*Y`YU4y2YBj%@KR?~!`$p+VMPmm)w^AiXJ!@elE;D#bq0?`2`JQ*6_2W?
zfW^!OtFifcsE|6_c@nAoBp;Y9?IR8Rosios?yA~G17HCeMq;HzR8mcCkyMPC`RhNt
z7dLj(cK3iXG<LcdE{0EI;z4cu6L3$+w*GF0!CC*B#C5gBiz{<Y>YHjsGAx7gSy7KD
zEmHnIgaWPzSioHZ_QrmKr0D_aIIVbb{_>`rV`1W3dLX&W|444eZ()IGznpKGa>#=K
zx}dqyY5yk+iV4Htzz5U%C%l4ae-ry2NO*@H*ZamgeF?s(o*TNfR+D!go+{*q$*DH|
zkdDwlZt*qn>ez)6R}|cvgAX(OXX9_Ii5q@YXE6Aa9@u9U5eAs5zMUALh@W6r6YP4=
z>3X*6Y`wlx!8(e)Xm=2)A#eyDzm~xV|A<;`-od>Uh*`*YFd;(0m0`al$@@pR5vrN_
zUR)X2<*7~D`X+T2z)54Bgo#KDP)a<`rnY8O*;mM`v@Z)-3I%smXd1#64bJVubf~Zi
zDCsJg*m<L$EBo~!1I$*Jud!i*@HfN`vshss)@sntwhUPnYwhra+h0xI(OtVqPt5y0
z-(M$UOfa*y!!ZHETu(arsznO@@8Rdrhc9B#z0#k0A$`QVleIkkB<A2wO9yQy#bo7;
zsuE&@n*JaKa*~Ji`jXtxFLC;fOGi5z8`y!V^yZZzoE8t+uw@knL?hbPDl{7_KzjUF
zJj7x(q!kZ><OA!xo*EZ@g=8SGPlAyX+kjRq?`*_;$*md8*-9PdFDV;)di#QSV&5o+
zMdis#Tl>VKTI)UI5e!LF2098N9>BSDDk`IFK8hUt*-bNMwxJGK`Gyg=LzB;jqCF9*
zg+Rpzz>}||wAzi(V_#e3J{>q!5-Hr3?E{3$SiHH-S0w%|?z(?(@xu~J{?K(jwn(X(
zWlq|G8K+naR36yCcukD;H-;JW|8sbM+eVf;0O@I(1t!U%#_0&VcW(thuYJ0bW2P<y
zetKdk!+gfv(3lcL9GB>ZV>5oi=+6!%=w_GqB{PKH-bK{6Q3V-_f&$?Rp=0UKNgGbZ
zDDWT?@|*~$+;|()d4>Ew>|?x`tvG5)-cf*aR5bnHmhEH24n*f}w$lS8gQ@hto{V;g
zVBcVi*H|eW?DQzGo*?#n`04wb`NotPac7qI?CK1)i>REC3;F92w|Y0VEa_iWzjtkO
zzPUH@KxcZ&CJzZ+^rDgZ<>2&%s+<rTm3#|67|jYU4I=|ES3FuJlxAtVz%`Fa-TC=)
z)XxH@Wg>m^i8to;%<>A#umg;eO>=8tfU#!uZU#Juy~Dp9A)c(2s7+=4bBhtHNTXl^
zD4xGTnaEN6wnN2A5w*ACl<W<5K+qLwBDmq(CWN`P=*3`l%7KvCrUA%6KQ8>0G1!gm
ztceYA&`dp_P155+pa@TYrvT>;wR*9??n>hQhx@r$tZj}(LL!KqkG-?s#56B@!sDS>
zUu;S{d2dVG{qukI<bSD>9}A(L#AcVk_FL3#0x8rhTBKGFZlAW{F3dVk-oDXBhOFyU
z;PHdLUf84X-quE2E=FlmhjK@hbe)@qA&x7U++o#}n*l`;wea8DR082?^2CN&?7>jj
z#|tVtlg}s2WQFX~);*B^XZ2ovWa4vLl+~A}cv8Q$5yaC{uO%?Y7VL8~HiCiknW<x?
zkRoZG35fXU%G#TNm)2lPtih8{%QS-1FrUQP0WRO*;`!AqZ^#)1f^a{~t0rh^qr4-T
z5>XdX*&kiuO7Z5$&nGM|mpudJ!C(*s1%AJgT*D{PWP5U`4|R^U#Pyoi9U&rSvfC8-
z-RoM;5~4BQ+OViHdT(<6opf}|&Sbqs8b~7f$BUh2RsM2gVAvFUru%%iQ}A+sb?Psr
z*u~MSH;R~4tK<hMO{iWXS|I{)M&l7uBi)OI)y;g2<<yvs{6oF{w^_q7;Bz0HVBP>k
z=CGS$gg1LcI$k~n`aKR^sJkj9D->8%RCx;{X~lOix8I|GHfiH(meq{`0Wi0S((%r7
zG&R#Z$x(TE#qDFTfHzn-vIaT&Ths_I`A()EbVCzT%kxuXcVNdJ-JiDj#X#a~#_xLf
zRE|`oqH`F@vDN<DV?7fZ{g7|*$4dxl=;k(G^2~PZpqs+R9_zH<>tY@yBAS+}jEQI$
z#LJ;|Hdi)CB7a6}q}X)D-NG{xCFu-pXNZ#@hFa9_-zq(>@Kuu#GhG;TN8snoHpIN_
zwv0&U*egXg?UR$?JhR<6KPFcY0NBk|k=oAE^$^^$d|TyjnIP-Yx6S={EyVUCj~t}f
z=msR7*vLP!tJT{Gl=DOmt%5FoNV-7kHkh{G7KZa#ExJLu4+e&zVY%^;?l1pLu*0ly
zCSPp+l(gafI1PiM5`^-oPgGP*Jzuxxvmjyk4q{)A;R~3{Wql#QoBY_rSR6dqEAVBE
z6q<3eYq+9vODZ5n^tElqbct_s!`=XkQaiZseDc0m_XjFsgZ7~z0%R_tc$Iaag5HzP
z<)X5R6W6v#I`Q7!ABG2tQf_%FK!=|{+#bvL|IXR30f+&38y@DRp<)-Feq=X65wn?N
z#C>%(i{USCchXHXb&gK*0|wjp-uVO~_ComEtO+a)RxL%!ayE`*MTL5dqb{F<l5r;%
zry#>cU7lKZ_7SUd<jSb!7-(hpjP@12F)WPL?BVH7pv<dsYBf`UE=iRgvXH+lKk%m(
z)R4CvU={fYC97iTm~t1?1QJSZ0^YJfX2*~-v>;HGXXbOkrx!gu_zPb+!;s*ToQg}F
za-GYqBn_~Wuk!tP9$m58gDeKv+Vbp}xha|!-@=#|S$F!GLWCf%`8_vXd*HdgIai5&
zGzYi>Htz@S9Yxeq8Mb?k$6QhOQ_nOJ@=0*vpdW=j?kSUsk9S(wRzzjjn0eg`3eD%|
z8QtBe>uQ9(b6IzDs1^v+P=6NW>d#Y!+b1)bm#vVTb>^AYqPJRW1+QE$I`8$2g5ePa
zpWv0UC~HF2p+|T1Xh|(ztCV!k1!_+c)=<2R4}$?p=F%8`ykhz52rqRyt%O#W3@;gM
zCb;g{;>HuJ5fRb1<Bmm!6zGWhth#1OTT3PQR9YMAR@ZjSp=<sTF@y|%rX@ksm--Ed
z96R1h^F=>tik%qo!Zj3CBP{HBCe}?|uvvYLQJ-&-v%IVQQnALuzSj!1;0I&{<6In#
z+b2`o88|*laN`fa0u=%50#`NG2lr&gc&CB>;LWh<e~jiU4_P9R)FYZC@(0_1aTKHL
z?hq%)t7hdEvk<JM^!9I=3AJ0mj}={uo}e9ItpVKojf5a|B$#x+n8nR#ySc5XymN`&
z#GsRmgp#O{L|B)#)c1Ng=NamQU+ydVshmFWP(FV#157D$dgR+{3pX%jGFFgz*Xdd_
zG<wlP!6-wnynM)Wsi|l<5IhIjnX50Xq|}LqFijlA2Y-6#_CDsHx2D+5niHIN`{!qY
z=F~z=pLCHWXs;ZPbba|#4tRBzhM*oKX6|D47~no`qh89Ic==>DUu8e+{HPy8_bj#|
z3l@>drJr*y>?^E>vK<CbK%9Yt=!2pdN_G|H9#X!=f3I5n02cLoTAoo12s&aQ*~VPP
zUP{SpIMZyhVtcX}ohxp}lPr@h%{VOCNC7J2-pKque^xK{YZ#XJPga6I0GKI1zm2LX
z+`E^`7^+soI|_3*oH+ZjP2rDXZd)JBVG}f*dKJ@rxM4vs?B2q1QfyPWiLSk}S{k=c
zgs9UfmLC%D%tty7z5PuNX(de-q}OB3xrDxyq^7O_7G&&1SL}~=A^kHlA+&Ta{qFht
zC=ObA*SPhV??KzT7&>w5_&*}U0C24?qh8VJ+kn711v2A>>wXkj^nDOCtW6X#e|30j
z5@lyKc-s~_bz?^Iv8??2Lf_3%Ack=15twc$`6eo55d`*%TGfU~92kJKxuC3$QVbuY
zT&ahwDG5+=^UE#hj&_6K+cGA3_zwE?Vsal^Y4H!%?Uq=}wbJf^JfQGD=YG&;t)I88
z4UYDZJTkso;f)lL2ya>*7-{vjfBufY@e=qK_5bI%K;jL%v#Baq!+x(8T{4WYyD*V{
z1e?^2K9VC+Hdz8~pa6eUZ-M^D1$nTo2tq}|_IeNqe@A|U^Tl~aid(SgC!IOaPy(<g
z&0q;XQS_KHpUFo!mlnqppk>e>Rz$a7CvacpoDhdr49=mL#JmiIC{q_*cw{hm>6_1|
zB$%Qz+ZVi$9#%+ZXnF4<w%Rox(y*Mbm`Z(GvSPq?f^>nto}upD<9xZ%qycoCwR^DW
zw|?Z&0eXLJvUFC+uza)<4>9pfIa}PAO_Y8nMKWzwJ|aNJvC!}M?}kKUAgR~kM0-?%
zIN68wfd%Oz+(#}4>v(UH34uZ9CfmfCo_=sy&rgwNK`rA+ok4Q5FTzLOAC%f(a1b(o
zvK)RJ!S-~FA&J?k^eJIAOwi0AUqPfKM58H{Lh=PBP$EtJa8a6!`8Rzt3o^l7<yA6;
z`uhL=1)m;FNXd^x|0P6Pt}Pb`tJmlj(F`|X5aiXqHKw-xTUTI1brDA!S7!`W#-t)N
z)*$ikYxTVZSm&{4O2AEF22k^8GzMktqC|{It+kvkr^(5`BUFVyD$^3uwQ3g|Pr*g^
zAid513%xSuiCl<ZmJ1f0uNir*8`ttpHI$kXCBKE<OSRVfg%?vXr41eyPG|k}8QksS
zNPd^FC4_ILG=OMWM=&BM40Qyy8D~O(1bMlx0O>HizP#+ivObekH>nkYewjE5D0Otb
zhg8_DfcXCi*bMuI300eVXOz*y6}XS&RE{SwCTIgSw~urpjivx>)Zh)ihu+pOFEK?2
zExI!x=D_oLs)v#`@@0dN+^-X;QBac#PEoH`?=UX;vIGAh<T~rVXUY<7+z$z`mcq{-
zs*TlopH`xATH}779gI)+Fz<cy5V$;q_x2YYzl@VA566{(jxHr~dRKae$~Oq7?8>l`
zMf;DaQ=j|;DQ~D)vS^`gpdj0D7i_{Wbhb&PcFcjUL1cEzqUb`Y+;Ic$6vor!z~iXU
z1{QavTKNJ-ti1vO#Lr$@`3!x;NeOQ3H4LesvjS5;L#+}7S!f^Z<61u6Gp<Vao(M`%
z63gNwixCAR>j5(lI)~QQw)Mc1q54Hslk#BTZ>PuQJH-(QAs?v%i!blZ2?G~4P(6=k
z*Q<mXq0XFM2jKrKQVhwBoqL0h-}v=JPtx&0B0WkZES6u?Vx{v(w!DRYoJ9OYY7vY-
zKDv*6x5OL@cPH(uL22N3`nN(8KZyLOGtnD7$-{tWFnj>oNEzO;NS@d{rZ4-T1=2i@
z?DuH-=KUNQ-{=)dS^OA<Dc0-S=+TuFTh}+kvFZL7xDHc1$NDSBdQPufBlZ)vb=&CX
zRK1~}Of8I=LLh$Yn>lvGw|;UzA7G-iWj0;2zt~MWCJE@uKtZ#pIKtbNrkp4Qpl`vK
z-({63>aKRY*{IxU#q*WReRt=pyAyzseIabbLD(Be3$!Vm9BxxO;F+7wRY!-3r<SUS
z!W)Z9-UY#i0>3|n{2DH+4Zn<p$`<ts(1pdD&3JIBnqS&9mOr{pWi~+t$e!vPUq23y
zn8f!AuW@$fV0r14Y+&ZO*V$4lQH7L6b;J?5n9;50RRnvs+8i1t$v#_Le6E>kEM=_o
z{eyVk=m7$tUo^6vq;C9<zqFfGz*mJlcCwLKP@e;`LW8ppEJXe+2*zYKkT75E4q^P6
zs>4L;1uUqaUL^O5NhqjR)wH5576&&p`j-UXat$({D%O8ONLux`;s4GK8aKoDO`m-R
z0ck!#gwSy@7o%6Kp*9H!WZ16>OPz<i!%D?3l|f)7`!AiH1T`ig?R2|SYp+YZfHNAx
z@fxcZ<2UQoXt(i*hp2zh7sdNKlp!FiG3&@$_BH1+NdJgkhm-Z2wl%JKGzX{^;VxTn
zTffMLgUpcbi%Y4RE{JB9W<(}Ne$}hFgJw1sJW;XBUL?_eH=EHt#0L3;W||pw!n~7S
z{l8X5vxn4$2SJJn9Ldq&yh9Vax!^mak&H$VY?Pn=6SP&Qh+%3ch?<u%W^*l^Q9EGU
zmhL4Ln4bUj?2G)IFsF(<B7J%g4#LLE+9<-UbDF>2ZaIc?GK!j$lBOF78MXg83CD`P
zk?C1H{14ShZquy$=`^&A&ok`1nZoAo;zQ)5aVg&y=8Ud<o<rUjxeOzo0tSklm<d57
z{VXM<L)YYYZ~E1!Z@!{9>^9185oOUb1R%I|dLP3-Pjh<XJx6wjxjSOdU{($u;i}`%
zdfVSOr&!DR61uD0ozXA(5Pm0>_Jt*2#U@HP@u6dxB5QDYkTwV>B}>Buj_azOBlYz@
z*(}*Z3FE!VLCQ^vx%6qIDmqq724BQiQeJ}MRWv&+X><2yOJ6K)ObCaP)ZAVJh0h*B
zsjxDCqNzRUFVpT%RIQ&xA}iW*K#N4>I`i#=lz%FKviH+vkk_sR3EDz9JY3M`W4BpG
z8*&4y=k8DTR?oBRF2CZP*Rd%Ctpzm<_h=BTd@rIg*xwp7e7kkw`Zft1-*5{6Vv`yp
z3UZ@djf|)ae+eOA4j`7)tPa-)8<X*>agL_gTb1gU`2WKRX#;%R$xOr6LNm|%Y66#Q
zIsI>?E)Kchd;j5)^{sV1!1+%EXypF#1I-2&Xv*a4yv&R<>hSL6@vb{EsFOKpR1V+q
zz{NF}Y540c+>^xvWwHkUk6JL92Ou3AWWb)M9zjQ>vOrMrIu_E7r_4MG#}eXeZwhi$
zD=aj?lU3ijpwfbQ*zdG;l9Z-;p$Kw<4(iDt)t_~~7Y<LyI?HPxc$Q9H<sh&u#I{0N
zo)>97+c&|ULYl0-(2zk_-b`_>wJMuJe#Hfpp0^F-XSZ=DtStkHhYChEsA~jFFlD-G
z-%=&%Vb+!hE|!|^EaP{OY4bK;g3iy!EdvEJOU3zup@VFo3MkmNZ>F269}ACHMFoYe
z-gaX3Xk7>9OreS+cEk@amsnI(u<y7Ma!FSHI^ltz5d!^{#kJ{G<5}8lfQT2M0<Xzy
z4F89fuO*_KeGR89RvPq<U6~TxVl4$su{`w1hsHCzhsF$CY=t+{SB=qD-x@SOP}p6|
z59~oOZ@`N#F)#gFImPJ4ZCa9JM(6;X4LSdAxurcr+Q5$TdckV{N#EIUDOjrn!Ll9&
zgA!8&Cbv?P<@&<>0t5y4N3^l25e+%Tu)pOlvT>4uMl8y$XRqo^{!n_GkjU>jQx$K&
z%gpaw`@keW_28Q#nS0=9TGRp2!O6%SozI|LpRgYbh=Bfm?G4W{O5cUS4zP6U(yD38
z-sP9|bqXWVAo~&la|VQDHdOrt1Ys!HTq<%u>Pjda-JN$WcSksB6cYQ&nSMa7G7)14
z;+acstRAntn>@gds1k5gOxWVi=?K;;w4M`NloVYq>i2&^lNGtt1C_OJKW&X5-lpL+
ztDW>GOAmrlfW;><0PIu^Zh&6M-rH_Y<P&kH?KL0|loD)s>b)Gdyh7RJgIr;Y>_LVg
z;p-D;dT|B?A|f@HidQ$SC8Mo+f8QRhSfW}3c-lvof@j6pe%&__MV*eZl8CErQrfJ+
z!<0#A`?*&``HK%!Ng4(J4gAr-hMEJ+vVHsHnibSEWq*h4_avm9&ME`@B{5TKR9u>Y
zj6IT~V&{I*Zf76o@RKm&ukhMjdeCd3ZzLeWqM5OK`MOvwTa4ZQC74a@q(6tIJ52FM
z$BY-$Ao#@ZN#ZE^=Cyahr&X!VbvBlgL$xmEy8!_T(r{5iEUUY6qm{C&{#Ni^3~OiH
zmW3&rYvKjtM~s`^^f((_?O{8-8Xie)+aT8CYNX7)41$;x4HB<79LkR%_usAbAY&``
zJrbg)<%4j*8Xs(&4r^Ibb5<+1v-6U_83Yx&U_|7j4i*mP4W#)!z3qFDP$T0!E}S6c
z8@Wct-`*@BOiqwt?(v`NIx#?`-M?wbEkEH;C{G=A0O0!AgrTs%DH%9Tiz8Z6ZVJh7
z>NbnfMSJsLlkoAp^a=^hqEm{ee&<w&-AY_!(3HmIplwQQv9nUjnmnovD$o*JXA=h=
zL+-Hcami3PgO#FarYEla+v;@bqR{^3*nWFlQc23M5R^Mp9N`UK+VlA}jja}`hEftk
z?UW&JTe#S_w}4BL=?hyuS-<kwzB1#rrnctwP_OchYa>!91D_U!CXGIE*Xv4FE9Cf2
zl+v4~1Ox)a7SIp3HBR(yy6_mGPn4n{<=x|&uobOc_sGcW_$<I1|9+fVg*bZCSx;xQ
zL_?%&PWJ>?TUOiYgMV~Bk4Ib|AWhT4TS+JbD!5E<@v59Tzrz|0B<wUWCFCnHxmO8a
z=HLEd#pXmKY~R9tBkDMN34nuf!}%h)ZM%XA9dsyjx5<w(%D;-vj3-zmMYSB&GYKFR
ze#Uo21@Fw;eaoM_)%#TYFJalooJL~6o`D?T=ju0fWZSbMiw2A9=XiX#LeFMr>7F<i
zoDU9a#IF<sO?sq=cJqwp0FyIU1MciPPGk4ALOImOu6{CfYSp+eY+wC@w^T=2n8V-`
zMiocg5hi}86zu?{Pq+7N!m9J=_PV<EaQ1-)eavhOqOm>O3z<)f*^0z|#&cTOUE)SU
zahtAE7bP5#E+~+0IU1B#OfWAX<fGp&p$I)Bwk*WgpM|upYfmFkhpeGWf{*`~TYI5%
zY_Sa^w)i_;`XN_ZaR^zIOBl<m^k=3AgJaWrIN8nj<cRK5;(#bmhAIegUH3BEaHzbm
z+`Fa;SbJFWsH$=HK+&5=cpyxjfbj2&1Z=!;9fA;m<6uHX&**8py$vF)7NnWWiKIFB
z))a3JeG~TkpOjUnW=8!qF*%EBQO}G&-{l6LvDxd}GdaN{_n1m_)0adM$!GA%0}y1#
z?k@nEMbp_IP+W^-D$k4|<*!|l<6*y3p$&rVor0zGK1V}VSX7s_afbp@_9#I>4zzx1
zKQ+H1P)!a#FE8bwx4cv&x#L8mmWI~@plJ6bJp{P+K!NlYH3+PU@yZ+dEu-fP*l0Cb
zvk=-qs8>tn_92ZCY81nXXg8WOc!Sy6{n7!LmQ(;SOKREuChnn0&XS{ddWFXtQ9;!o
z0xrG)YuX)0nPi8RYmg(p!{nBI`PGVZ9(gPit&*KJI~EY~n1G<Qbrc-h0V<?z-Df;+
zk7!$tyM_+F@srW>Dzm5+Wa1>@zjqHG9^wr}*lCEzix+rn%N<~CvNtlmjH(yWu4zgR
zj$;~f+4>c;rUw>f`QN?rKN5D_IEI-Ebu8c<;G%gO2yRl@K%4q$(%<y(mWs`n&dD$B
zHQRX+B%xxfyzn!kAW7LAwE0L#;7ZGi)KwZT8eb;Bg71!_el~ogR|>-3Zak;)i1t>C
ziy0Rh!j@WmZ#w?&oAjBD5oOyhPm)TlMjdmeDvKZ=G|31LvY7z+&RaYaV)wPOibGRs
zvvJW6+0zVoqYm{7n(S}Hp9{3{yC4Z4Kpj6O+&t6if3Nf$cohPM>WAxjG^Ydm8o~>f
zelA)1V^GL6MI?z{+K+kix77%b6k-BZ>LC&t#B;=Y$^5+3kkEnfyV5?ShQQ7QCPrnj
zi>5Tvsl)Kf;(X;Fr;2%U=70AgVgKwPt#?H-Zz3l7&On{LZI!?;pC^;b8c_&80+GL#
zZUFXIp={qm)is7Xxz(lHImv;QXfess44ks^+=&>0s)H%X>2PomJR>0hYMMs^M7WF}
zt4@M!Lo%?3I$7?B&UBc}9+eYMBE{;zTktgmXwR$1&C;n#_wq5Ra|)7kxj%orKLb~W
zVw0K|kw!vZ79Tz>|M*0O#s6;IuhPV#K76cttR^_^?$A}`-GbF1FICGuVFc~thob4v
zInRRwrJ}Ft($HXtNK{&zWfRb~6lIPQVz34}6(idkO)>|f3t?!S%&Q3(qY<LP3+UB5
zS8?GrF0FC_NB@5k*emc!%#u-XX!qyGN?3gNy0$CWO1-Cd48wChH_U&B9yMOA3F&N4
z8@ANmr!o9pr#x&6LbE!Na&b_tM^;sBpzeDvJ}^kAL%SHFGmR~X$FZCa{>yaqgHB<(
z5B%&Eaz6kaIQfX_Yo!%{no|3RQkG8Sav69Vf%}<m+4tl|44dawc3@w+M56bJWz<U&
zW7wRS*$cyE715omP5ps|hylh#xyf$Vj(D?j4lTf~UQ;l_VR8V_{}L1C<JYWHI&G?g
zn@>&j&Oh?R$dA?wqwxDg@_|hN;OSOV3RZ=X=3c;Hw4+=mrW)G2_;7Rx#4G7#{-4jn
zt=Ww~LG)W|V7AoOksDFA$ZtE^I5@{b6u?QT5*jErr3=}g9gD+eTt&V|x2<(~#QU>5
z0Q%%eBXN0+SaJqB-9%f@$5ev!4)?C{tVSix&m{iD#q#Z@cAz9%;8usyV6W>6;$77R
z%zQ8)q41l)vHsDm!94?OeCaQmvF}!HpFiru^mht?>R0@tbdQ*2!%hSki3$!Hrd#nZ
zGK<dvQ`)Y0y-$Xw;+!OFXodUZ^M<{{(5NwINm%qpT$rs0#_v#tyXiXV7Fh4&cYQO&
zsJ}RA6p$Qjy2;#jRF9So>{?jk$3P(Y2gD=ywhuE0VzyN&{qj-|<1Kwi5<kxJ1F?FC
zadJTe`%g8bp%ug!*);8Q`9QrjG*u_!94zmYUW^Vjg~j!KkQF9f1rK(_zF(!U+vDS6
zGAMTqjbRI@|L%qCMc2DqUxEGW%$N6XTB2^u@H-6>`e#vrcuw_d9q%P-Ea6+*U+WQk
za2yttJ+yMR3_JHLVc~kwJEotYhv!f@OXO<mh_;fSE)4^@`o@Z;UT%%CI^B2@w%fA+
ztm0hp!Kk7zQs6u}_6(ZuabfZ4ELGgBHnCk!0>lF}9;i7(%nNStjG+Z5N>Sac$;FHt
zYV?AOy~5;s2?!(tm4sobSZ2iQ@nT$8FR0F*J~*DO*LB707~#K@FXd(dQfq4QO9{B=
z%L@fc?V`e1ZfT$Oe<a)NQJ_&Lg{SJ;Vei7Z(p<z9SKl$^QU5>!#YomlkpqzbkFg&+
zCu$dV-=9Z*r!n42{;P><K+uN~v}7)BQdwtY<K7$TvEG+L4$1Ru7^p@Uq}z99N2@>4
zl8Ba;{hvFtnf==hXWkT;cXdU`pqV~oHPJ*^Zr0Tnq=?|PqVCf|I`9_O{=rHzBoNO{
zpz@Dbzh1;E{i4j&t6$ck7~(-e=_as9LE+a>-(~xa-@<Ths&Lx`(Ku;$$DU7`Le~)J
z41H*R_X6b9ouuFV>b1<MQMqT=iXee+{pGzubPi*!IN*HpFUFsDIKC&`ABOw2u~(yr
zhAaA4yIa>SX1G}gUCR8uI~Z<>15)Og=x*&EBgMjwb5{7x7FKM5#f0m-&XCGy_or`$
zDo~xq^$f{H0<P{sfrGSZ1N+?At?AmW;`MwbkdoiSRfb>&#LF09DwCvT={dKSwV!d4
z_S|6J&1F#l!f)fYF_KclQMYN>);;%|BlFumSrSmTDWBEIkz&RMV*(9<o3A<Hs3GUr
zt6LF|97<=v*jKSLI<7{OR`%X=sbQ(f8%PC{?NPdVs0NexuW6<lp+XsVmS=hv5hOt^
zpM@?GdC?+Du1uh8v4qlUD*_E9tC?(JI~oy-h+blIDlc<?`0M6-n-tjP23qBolp4V2
zn<{jJ+VGYm>>KBKCLI5-)DtSdct-S679~*T!esjX)K0<0V{89H5<C9q0rh*E?M+=O
zg=|=leAXX%-3Y?cC1Dsl*+$xa)Ar8IsD|18aBJ&L468tIb_AqE=-dnL>{m9D!~god
zD)V_i?0VtERqi-uH6EDVv}~##k2y@#<sEObXu?}^<hp=y41KIKvE?rPG@)Cf!AtaS
zTzhark^>KJSFEJ+6JEUY(WhD6GLLD_4kLRImKpGNQgK2|(0OKg8trwIIQH952Kin%
ziGy^&Q^I?!ap`}TVG%nAR0ri2x2CXWGdr5FUMRy;NAxw&nQ-f5s0>2*tw|_<KH%}_
z5I5C0aOb#wckv5vRc$-fN!NxW`&NOE+a|cL*1)R<m;ZW+a(zgVm5hm0<-{<9Zj*7c
zf=^7L=jV9p=s=rvEDL796O_NsSIsJs^8?5|Vkcz33<UyW8+%|j=Jli1yA2jPsQ|D!
zVZf99?;oHZ<H3Kuic3(^{bTfXrus<|nBlXvtAN>;zJ;y<9enhQ74XRUx9}r6ZWXtV
z^Z4!$j{GLWwqdI$a6*+vVA@1MP67{e9cX1G`h^yNa<x;`GJxv0Rilp_35SfTSK;?f
z7{<?g4px(<tA!nrcj0F+h8<T*3Ye29cCA}5bcJ!N2Dl$sD)HoTy}M;MOH=$tqaJ=R
z(s&C4@tWj-R`_Y$FIkHTxg>)f{t-4ZGZ7HZK)T=_bwyp+@$CV=#*?x><!Xs0nj;rx
z^#~a1?v%~4`&q>ETHB)f=0j4aEbPsVh)tr^s7DqbbHL)KNz-`ESd79{?Kq=a&KX$X
zU8cbanTr=EO@ynXxXYu$xIxv$YJ)|DWiekW=`W<ul3THbJmbznjvWoUD-x?6XjPWd
zWct>Mcx;V5r@eF9`rF9#Y0{WBwXE+}HRd_fi24}NebB*>=?MVle-gPaPRGapo?$<;
z!w0shYH4*0&6}KPeTfe`ZLz+L_~iR{9%q~^%CQiF`IuMAN+LZr4$i;9B_fVq?m}*2
zABQ<)p@*3bVPdMwJ4o7B*fB+rF$U=ufXmfGBmJpiHl+|Woz?*<CU#a~N6|S6`SY&1
zp2(HqOtSAeZB$Lue~6elDtfEPl-s*3PMxTXy9im%u7uH8jUPY{i^oYliy3z>cO~35
zpPPb(VF<|C!kcWeSivX8B17O7tgEz{WN3POO3S=uW7O6_F(J393cvGBDuZ1YUJ?Gi
ziy(T3QEywvC1+Q-;18Gazr<miKL0ilIghB*onmo4X#M_KTo7<j077}*U8qx(l0L#S
zf)GC^2(gPUuW>Kg;IgCc5)%MggGQxN?W-%RG1>^ZYH2xoB)B)vCm?6f#h>SV>68&Y
z6IX!tycNu_#fMfgG!V)>#vJMH`>H%8=ht)6VhW}YSm_p*e_bsqmIf%HqZnffQ`~n4
z8qQ#6kDD~|vm*XRA;vy!Q61{{(KlTxRK-$j#NWoygdKgv8Smq1M{!YO3<Sg{wRVg#
z%Q=`%0jdF8o|RXyAxM*ieN5dBP!R~M$~_qS>%re!4V6R}=|dhtzb<dUq&yZM-PK22
zX8x@RBQO{s>()+|?72Z?@`F-JS|Y)NY9saP(ntziG45ECk|gTJ2Pm!IWrmN>^Pj&Q
zr^Yc*;aA``ep#)WRkLx;#!RN|2)9ug6fdc9!}s5p3ITq$R1R4_Vyue4sk7c6)b1Ob
zX-rKh$E>%L4}-V^8sAp0i{dh@M4_g!rd3W>wWhx;BZ-ht;TX(iqt(3Z4{}lxho(`a
zYAU(nrmipy82NA0z(`K~RxC^cQU%SF2*-n0#nm{;+V)-W*NTWN_<h*%wx+<j^<vDY
zK3sO}ufEHiplS8*WY!%fAldb@y9>&%f1?wi|7&eJtU29-LIp6$R^YpOkR%Iax!{u$
z(DvAU(qhnx^9<bS!rk-xLTzcnlL*Q=l97Z89bX1SBd(*TJldo9H{~PB8t3gy$EpeA
zmaWk+cEx(%S*%CYNh2eC6C0;cA;)0Cmb{t?=9z^vMJ{Lrr_doHDThdhNu)t8eqIXR
z#lE3EPFO#~Q-*myo~bTaw~N6OkWOj#Q^@m4(FR`TgRX6j7nViZF!Hfz$|?&#l|;);
zwsB5G1pqe+6b_v=i{F{?Qd8=T0}a0kfcGx9UIpJwvXbL-6{e96c0)Y>QfBstnBMkq
zOarh-=fb4AiV9_-(dy{{nKOlAh+vcT(G_`39CDPS%v0v7azun$se=E7_ySXF|2fd{
znYtj!(DCygI^9ycZl_!-0S(Xo>ALJQw+|e^Va2<o8nBF7A6}vS{vX0#pqfTpiR@8=
zxf-a#Lf2%p{;((&Dlg#FJvI>HP?E8uC|{mDC4-aj-Low_IiTkQ5++TymA~ew3x=u3
zk4sGH2~x>e?sNJ%uVcKGc^-Z?u;%J#r$U(FI-8Pb3f%INFn+;^B;P($Uph3PWSKV5
z>ih&NIz`EpeJwpfRmOWDG3&cU>0c7oZsa~<>Km2p@VAYAeoP)DQ+^>qIZjWX&;4!%
z?TAe;h$dML{|&{vwZ1uk;Ci};hQ){AqZ~7LJ<LNz{vB)efknJt1-IQyuC`8xJGZDz
zaf30wU`}m{$`l<YV4YH|8_-F(pj=jqOcjKp%M^t&v?mfjo`V;g|FNkTHtFLcRlO8c
z#2SSIX$`tXrpWF8KY%9@L$%ACC8xi|_uWrHSmI5!m5*sAHvFM9DMkp7?2~cv?U<}8
z3Ebm0c3=<L)y`}~4rC#Am9~~+tgk4P0?dH%wzu>FX_KTUBlyLNuZYk|rhID7vIlF8
z?jm>Lkij&1Kx&@}f_>vufxR4bAqD;p-Zw?EiNb<D%x#8XJOG?1QZCdfP3s7lf0}^=
za!Xeor@WLyqDJ&mPK1Vsx@8{|Ud*8-136+AIRLxRSTpZK8WQ83Qqo$p-Z;!vv_Yg|
zFRtFcc)+X|S5jz;lBu?uSr9mwVTfC6(z@jVBc>~W*4~z3J&fk=-%sB9|4^ZUF>K_Q
zUN)4sgRrBYcfD<71o*Ya_$Pj8AtZ@c>fVS6;})SuAk(=ienFS$Lc=<O1IV%lGHt;{
zO>Efs%*}l-blI<*@ht_jd*TU|udx4-Q3^o2C_;G85*>g%x_F%wBN90&b+nO^E53-Z
z&;I$-XT%LRed1;W3^w{%9~>bcN>LkS5+W$_g8sR9IzO{IT4i*s*|@{C2=RgDH^!$R
zR=R%0`j)~LqM-@bh?kPMAG&&(B{s1cdEO<;uYuk_(+s$#p;>w*B5PbFo&bwuvY=X%
zn8v^eLVWs|M0bO<NmpHJ`O?=X3R~_t?1Evl=Sz)zMw51q{6HQ*H4K!?(NMuzgz9A)
ztaHvv8_S+hyO_Le4xW`FXAd}PY^f$a!kyOv+`eeK&gKJ%MQ$`TG8K=SFs}?`=)BiO
z3B`&p9ENDlPD>Oy9BTnZmOHe*^w?Cgx(sPPTt2N3IDiYBzVQ$*W1y4=`^iW}S5zeQ
z_;FA?Yh>&ovCY~H+u64x%2(KZq<e>}+-voiBVpiQce$z)Clo1@_b=ntTTRcUd4DA^
zj1JYT#$i9&+09~xNK{9{P!5Qdym1O9wBv&Tq<tKvLaHT}jNm46s-#C>4a5GTd<b{h
z^%G#8eQQig)YotvdP07QS~v2uv5?>+S>)SP`=o7)wk`Kg@D6Y&q$CAsyQ`Y*B{_0c
zKg&#irG7NVb*2{Z{qIq}u{9@FQ~NR_K|G}Mm6CWEDlwGWEH;sU4k@gT$vk%}M)XeU
z-o{s*Du4*Dc$r+zU@VIsmzC-4ZMsGKW8Uw@#|hVgZRq{|TKnL!+*}cI6L`|Y(5}va
zSfeq^=V47u69YB+f-)H03kBo5r=Wiy$HtApz$I@)+|TSmDHgy5Nku4m$T7~y*llk|
zLzXIAes-!3CQ7Xzq$gVybCq1_&$ewTHBKWb{WsNnu(oZo^t<ct2c5^@84s&YN32)`
zw{PFxMdm1x)yqpXv2FV!_rXt}hVa$wb=(kfp%pz+JCrkOBRL3iv2;TTSrCm=F~Jcg
z^uPR$9>P22h{qHsb3pAa1`X0V8vy$)qmmtx_ymE0zZF4xYqQ{>_N#39m#tK1_gkaK
zPv!ryu?)g+9ZXTtjYvZFMKH&%as)*wN0{@T*HXr<s%+chV1T|0zyLqNUJ<Xcqj^k>
zDdI!v90s9|3PTI*-f?#w*C&4atANSCHQ=}~C!5-25%Bg0wnQ|8pyBK#9*i}MBj*AE
zB=p>(w8)<OVOA-pL`L@f{#?yLIDPEA1P%k|3TfjB9g+fpV0E+O`wE=YKI$e4S-kDY
z3kr-KwT$lc7<0Lgr?d^0f)T=ML!JST4sh|e<vmF0$SPjdbyPv-Am^!<RY!TZ{e)_M
z<-saILIR1XT*AMSdN+U7sqp01_Jcdhmyjft1xRbWve<4Kj8mbXP_IfoC$3?b{lwgT
z6=^Kj!%Z`&uZ}!mY~sUH|1d;(rR{G>z##f){zK8x--0Ta!EQTX;<h$46#d5qSjq;r
zlsoNc>osp=3sl;0mCit~=%D${YzF+Vr21VR<GdDQfi03Rdm*CfDu%`tH^lRfRRB%4
zVag!%+DK7MBA!*4L7o~NXX0Zy*Se^CV>8*DX~K!Ri8Yc=I9Hae55cObGri@Y`<Lwr
z50-3kBSB!vhm&SKubxg*P!Eb`Fk(Q;ld8<cf&t53M_L1efJ?+tg7(q^6iqRmqfh`*
z;8WieeLz=9$U3YjM;UA^IvuqeoB+7n50qKSkI<+y{kEt^bv7@^Wd-303&^CrWJjL9
z^ZmDI0P<075<BK_qLBhFH-N0MV|vF>Ig3qL0`J4a)k)d+zaq<|n7pw|tc0Z2Gs?c<
z@=Bu9BZFK>TN<PEjuJw_2-i5Hx*VwySTs+ppileefs7u_V*+QimDb!37(xt$uCjg)
z+xlaO(h?1)bIZ`kl%ae!bM}@vv(gmiRXQb@sll-PP_>^6Bb<$hWILTsaY;-J&VIv2
zy<e!KFEhYLPYztBffYv&_33_`z{1FrP*`$gCeF<;kP@OJcD+y@uznd(VDv1P6v934
zzQW}xcVGS8&&mL_rSq%c+**DC`@5}u@75UE?d8rn1`_7I&$c1vo+syhNlHjGXl^B&
zRRxpj#<1q^VAvTn0R3?d&&EC316eXg>z&Q7z{k)lpHwvOM}q&~v~+;Vca1=blqO4*
z0vs#SA>f|5>mLkGftfm9h_{t$G1vPL@{7bQ2N*e&0>iss^?aUs@kVpzQ3mYpLryGo
zlw&}G6Rp#FyMqqzdmPFL#K&XS#!h(VeCAy_ned{Z$R0!a!h5z+I0mi{!cG@I%Bd0H
zA&#Upf6H2!vDpQswv}yFn!|M|v9r?bhG<@(>Q4RG35$TL5u;!P@+UyQ(r#lP`k2YY
z=2(z8y11x2pRT@R@;)5{KpVS5O024`GQ%cbZ7>u|^j(>Zn;4RaYnTJPt!eSI`zAzh
zeHRr73Xi)*_eMxNfZ39ycgWQS%-2P(1P(r!21Vd^M5O!_g<@Be`OeE(5<BvLx&v2~
zqW9r#=h#sqOMmtdT%*8AL9nq_z~o$76%2OVZxg;mT6Z*=iEaPbBtYiI*TX4<RX`o^
z7HXcD{(f}{OWj1W8~SCvV4#QEsCA}0s{h22Vm;j&zlM9uIx6-Gl7WsdeR{SIXsiJo
zwsb4d__A7Hnw#v{9F5<aDT*=2Pb&<KoSBt%{?0#tX{Pc}F@bwBvW&0eV*|AjjPUy&
z@m7wnjImzLyiBK}W)%+H!l{;O-F1Q}yAKYu0#B@>>OYctUS#Ww?H}rCk2FiIExc)+
zQa@gSuNMXIc38Gd6oH6mL$PUX4*3~{RFc6)s|TE9<<qT<4V#j6lZOmBCYe?3O9QTr
zlOwGaZ(K~4VF-ISi6gWk<w!d|>fZH3_@ox(JB`j>c-8S7OrW*oz_TOi+{}7lREQd*
z{n9Y^UIj5sU5x|gQARW9I=@f<s%490H5rvI149om?Tginb!6x<HRi&p!a=Lep(|uc
zueeLe-;j3Qk0<Kt+%uokh||1+a@9<5wZJr$fz<H8!y-PdK)5c8nJZO%FQxb0bPc(?
zJAldP43tGbP9SuR#5zX0pj2CinR4m_3e0rb_E=69El;f$een|DKc`yxIhmxD-v)5`
zwFfbZiJd}jCE2z-EVcab$oCXd^gVRin0?K03E*{%86_W&n5NqqdBeC+!nBDdrP$J}
zUd0Imvbpvj+VA<Q29sA7f~Wc+v+uK17(0f-pe~o@Me5_j1l2Hp$L<%Uo7@miC&wrC
z0e`oBA;J{d6)6*#4`Zw_NNWogllB0wt>c(>^-WYHqO;dHfK4C5Z-<Z9Yq!&m%L07K
z;Eclj&FWNSpnp>~W+_t65@lv)3p|anYU$HSOm?Se#R8N=hF?R#^y<XMA=)0K`C{|=
zEt|eG>hzOaI{oo9_+-!*`|WH$NY=sJ**nySv+(h1xQ3Hh&_%0l^E=N|O*3t^FRp>p
zs6^eWrzd@PVl7r?x_PE{t5TtJvhd>e#wJKYZ258Rk+l}T4BooX`gQG-g945xkR^$z
zi<O_aXEqqqa2PQnTHbE?vS`y()_?lbE)2f=oXwDhGPsq~&+pBpP-65$E{qHvPhkRg
z*^SqcBe`<EIbU~z__eXu&1xnQ{<r|NpJw)E!TsXvf3E|FK1@Li`V<8O^TNvpnk7>C
zb3nLU@@1DlKv4JB<odd9vXc=thqmMco8!iP`Gho%|Ac|2`*(-Rkre0#29{Sa`A1-^
z{YcDi{Hw32IPfD&!~(x|FlgOG(NbXobm<Pu&<)xHQF>vADc!W!oCr-`^l&ukKFtkw
zD54iCL;ES=pb>&}%g!lMaB)g{%DjJdIUS|rqWsR=CQpaX$F0^t1ueg$m9*PTbp8y2
ztX|vyUwCv1cHfw(1v3;HYm}l-*zi!mkDHQQ*xoC_wg<)T4A1_nGUt|b{~1vseV48f
z!lx|GBMXIj*>G<SP9HWBM19atfm2D$!}6av*IR)vGRmWnErf8d)O?nG;&@XeSn5Jf
zdEt8D#z%re5;ExfD;w*FzUKpNSai6wXES3VI;hD~eZ9sty5iLOkIoY&!C?Agy-$1h
z2M$^vl$DD)QUzZQeJm>^vDf@!Y1>-D=6Ndr8dxS#4Gcu^id@|@3shI7tzx9Fu%h2Y
z+xsF<@U6wAm`sOL6opF7m%So!ww-)F_galxh?wY6PNcw^%lB_U0MW4^2)R`HZEzjM
zCn-7eN!wwB5J#tQ)_M4fUaRvQl8`{x_@&)!9m43~#0pFQ<DXG<I%T`mgCX~Qibc47
zLYz`~JCgJH(S8RxOz~cn|B5jFa}C1PxAN&T6Hb06+6m<bn=x~1n@3Ew?^%UL+Vk0-
zj}KdFSh<X2>X4o)Qa;uzU!H%}{GsmnWu!J3Qp~iPtYliv9{i{v!&e1q&+Pgs{SZ&&
z38#gqz8sfcSzL+x?{fjwYETP)eBoZ<Hx*qfA14$K4sAqTshr1;Xx?uJv||@YHn$OW
z;7}3~OPp0`SMQd2?hmh!#2KuvN+US*!#>S}+f^PZbdi{Na<%fMztW^yOWv+Ogd0h}
zov`WcAmf3mqe{z-+<b#uiQ4CHk|n-NDBop1hPusAOR}AYb**rvJpp_bH54Fjn86QD
zZ7e+K)?Wt~x*I{z_B5DV5QxA#g~mCgJS{ov>}f^eIVU1G(y2=M8qsUKjsa#*AQX3C
zUPQmAuu_Kd5X2K5CnVa7eL7oPcjvy-n_5O>NSW?6smvZwLPdH<pG^`3&JY5q?XnR=
z2L}^fGIO(*qMnj{C9WuOFEal5#*8OmzA2y>b%RMR0A<G)1h34>7!;pEjvTkna&ITN
zuAq2jr(HQ6rto7Zg!ka>tk%X8ARRCSgzkZBstwnO^{>*+=?eOvN*j-9&?u(r?n^uA
z{Fggin>*6p?1Vr?cgGNe1lYkFp)@S47PbboU5{-i>wU^+cYet-iLmiM{)o#5k~RR0
zK1f29(ZrnOYRMEeb_aa6Vz6e(ZaXVq=cm${DGdt-Mt7I;_^aJw;(a#b!=XV#dje`+
z<f!*Ac|7p>5MqPR+mO=`!KK5T$93XhfRq_`nmVG?&N(TbpT-07tDM}E^fppu+I^6B
z{~6&wZ1l)_#zN-coB_&f&y_#{Y>LjUAW_zt{e!FPb<w$|e-$=+XljZMLewGDt!jK+
z$$r;w)?b@B2)-eI+OaV3s{aB=ZkM22L(-qx^EO`fw~7k={f@#5ufS8B2Y#feK3suw
zIJnZ%E9j0X%#AH)jf$Cg=gePT2z-|P=0`V%N18bDf#okiPul$vvx9Rl-SeA4+m#+c
zQ|Rf@@93Za79)BrW}DkH?{wD>bVm&YZGWXw!9NXU-der!?++KQsq@BUHNX$~g-A)X
zBk`ED^7U}uOATDVhZl*fl7%}R-$6KvLU^V4eEr4xk*^_85}Sv-%>qUBs>Fz}B!j%4
z+wdfyZyMNdR$l>p6bcj}{V51XrRf(4itlVF`K~dg7Oprrs-b(Rq~EDFgf;0{p$Aok
zi;)$Rw0VloX6jDB2MXY?pO}FqVsJT%5ijox*T*LVEip1!yOL-78;kqZZ3sOQ+A3CG
zs3`+xY{x>gYc+Y;9WJ1%Z*I1~O%11(3Z6R3wxs~l3Mg!HRKQAU2zSGDA3QFS^;iuk
zhXdC|kmtU9BC@uRm|RZ(Dd9Vw=DY_>4AXMhxAX&=eUzfK(oPlY#Y$Ypi3s)Gyt<K3
zh=`^mNlXS;63sNqS$JI*{heKxPbTPV=a%PnlEW+KqF9TsPw_!ZwpImA_#&%vw%N>%
z{*d_jFBP+j8!kJwoXBCp@7%2HcWQ~Z*VmMlun_eLMWZhMH8p1xTESCIfXqH4{`)e3
zH&|5iHT}dumF#r>EmMLUE%$G_e~$KD9Nh6Xn;@8Ar@^{Ov1^S5%ZqaaZ4aCE7>awX
zSq?i;R--n{0T{U;;PZ?(49D|b`y*=`d)LwbN1=Kc4m<nmq}d)&O;~}=<<0^R$w9xG
zh4Ip0y*NBp`qHErWh1RvKn3;P{Dr-)&CnL+!k5f{hQuoKd^JVRR+0k#Bb&GpfZS&^
zvqHvju4UTEZ5qa)kUmvU8k=I$^<>H?Sfv&J-yz6|I4yqdqX>8S-t|xo-E|)O4^X=U
z(cx=T?{5LiA9fbz1rI>j)G@y@MG_o&`g9i^Uvt<6f-<1U(VNd{j+a@S&NSC}?ls$*
Nlkbp>OF5QWU>P2hQ#Jqq

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..9563fd15c126c5539b9d133529a0058594331112
GIT binary patch
literal 1744
zcmV;>1~2)G6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSHti^eqrA1vw$!f3}E-M;|>
z+hok8v_xrP$FQrJy<VCIS@@&ZPtkZO=2&+h%btJqIem>HqdH!0-?K7t{+1A$a==AI
zjGSc_;>EY!sthYMDY7I}?}ZptFv#4mAW`OJ#vdN-{%&0u6u1&pJx5FGc5Z0y6Cw><
zcapv!yHhHQa7_WH>gi+ne?F`lxdTa9b+}^+1>1FyL_AAzCARcP@EA)*g&P1s9>+d-
zA4=LjNrNyH2jMB9JoQ@Q;2n_m(+DA5S3hVPRpsctlTB5~EIj*Ff?Azn&DLZkI80|V
z7)%t!SR}3>&qdpQ`aK!S|DKuBVZF&`jfo&o*~1qg!I2PkFIyiBZdwh6tK|euSo+>a
zg;!-o;Yg_UOuW5)D<9wU2&o#2bByNuBpw9J2<5vT`@K&x+^#;->wycBYhWs~_K2L!
zec*BsOaCB~&Zfh|YTsaWbb0meI}uGVbj+44r{?Mj{@k||)~{nGyDiIQM(#?SHaik7
zx^LmKKLIA^VDfW-!Nm6;a69DHChDR8wiwVtAJo(|^@JnD<ARCCrbvVJzbnFp3Aa*u
z1Q^q(@mRtthO<Ra%RQ#kxD<YUSacNj^Kd9kVKq5$qkzM;5WWXsnZjOdH)VO&Iqhux
z+LW1Z0T*)hQ=ID}%(g;36)AWMOYt@}U2-B-KH2DB`{`w;vc~2IZ>M=JKV59zyD#4|
z8;kMu(55`D^3mNqtn9aZrHsNt1~!-x7~lv=z%r595St^uP5{{AS^gD)quPsGM_>8C
ztQ)ri$RnL7ICaew=Km&h(|ZmWt~Te2pHdqRLogu9qlp>mHH}#yTv9t9tMITw44L+B
z7fMa}wTO1ML*odk&sRb-yDkyS(g2!f`j5btnkg{kYYQ;*dvFEQ@_-E#L*#Q_a095P
z35zxIg&srWQ?nGGf4ase7iJRX^_v9V(=~5`U6RZ*pXV!(Dd-efmED_oSHco1OilG2
zqCIvEPCAp?LLyRy+Q^M>?-+M0{*TNX`b|{(P`o_A74QSUMjz3vUeu9~Ya!$**sSD3
zl?c%GhC?(!x$G7tz?KRJw^1gKTFSm!_tPSc9{^E_Y^r@b34+iJ3F(yFdm}9ail^}h
z^xNoyu9jj`y<`1vlq6mlG!NZ>p&p48Mw@^FF%CoB_CjzbpZonyTf~WPB^c?@fJ2D3
zM2w$_aDxWLJI44QJV^PglB$EN_VDf<Z(a@l#8n!tuc1WuuoLL4kjK!i73adOgFzLA
zlC4pZsQXM9C3l8bDzkVU_G`oREr(hJxxSHzyL~x3Ln?akW5;n#$mu+Zrd?|NH5*=(
z0A8N_ke{!X7wB)k^~y-?G2n-hzPtGucj=0@TjR>bht}mthRLQUtsaNK9i1|XsvSMG
z>gci+^x#IZycADa*0LT5R<w^t#yYGs)Bt?D62Y2`Fz9EncD~yf>!slB{pU34wdT>B
zL5{RE-K{&WD7qyR+eoX{&I3hjnyU7T(&tQuN{!|BsihshQ7S@ESZf-y;QVa(6_P1u
zkO*qq40mB+XhIOo9XRT|g0A$&=};M=QSAp>V)J^;Pv-p~PkYOf{~!$<kdy+}6O3s?
z9(B=ALg6_&c5iB~fLc739zviM`K#`FU`@Y8?^sR{Ws^})d`8u&2ccUciL517viKQN
zwwd#}V(|cw77dtTNwnSxM~CkDa#}<f(;1y{o<``wtJ_rbKv~0$-Ggg(6B2xMEaO$C
z4Vn*?@r;0yMu<#kxIDl{)zQry9XZnmFrTZO|L*!KB<zIJAC|gj;s(6he@?HxE|*|!
zy(~Jl;ri^Aoply!Y24U;$eYl$9TTr0srD?X8pVR~#C*kH9{Ktw3mmdD=xOUwJ}?&O
ztge|6rmqmWf8+duSda=jlLwFIhvMs^4j#bVIFAf?0crXi;NlE{?oC_4{SZGyGnAiX
zy+#<VOiSY_B|_)1L+B`dJve>1jWB1(=z$kA>X;?9G2Ffk(Z$^h$`qw@S{Tb3`Cl_#
mnXiAK7J%|=&=2YC(j8d^jcl<VOj`fb{`%D~tg0NqJMFynnpeO8

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v
new file mode 100644
index 0000000000000000000000000000000000000000..858f0d90c01ba3cd83e944022ae5b10464de50d0
GIT binary patch
literal 54768
zcmV(vK<dAX6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+lp=)9_
zPHYudbdYZoH=J09U|<19#}ca#>I926eW-7+l%_#-^zCw-Yf<eYO~<?c3|;Ll8P%ha
zm_TkZ(VaQJISvwC!NOnXuin1Vy2R&O%m#lP{t5VZ{~z;YAB_HMUI7Sx0JYx|D931S
zOrkr<0+wLwLsjEw;VI)IlRArN!p-%}c?0^^$cnh<Bb(=y2F~F|dX^g9nO2fA5Uy6A
z5L>7dJhH80zaePJeud0~hmnoFOt**n<?ZawkC*WJ<6~qZ8zagbBt1ksn<D8Jtr%@(
zxO%kQ)%_5uK#Qf08{ez!$AH@ShIc1=c6p|CoIAGa3|F%n<EqPA2=SSj3~>-eR|N}X
zR3fCm2Bu_gj2CO1q>R^X8Np31GAtRt1#JYxmArFs@7WIQ6W^W7k~bjxJ}+8u@cXY_
zp2mmEG~|k+Eii|&F5n=y8v?7z&0V=|!aW+?7N~N+ZHd*p);`9c&wR<DTU%h6Yh<I^
zxlC++F{Ce-JdfX^6M>Su2Wjhn$4wbnSIR(|xFU<BLmos3V%E<z;*B=8Gx!e`9QA2G
zghSP{AT{5-)tY$~>&9ECRh|-Dq!aFxig3g;Cz-F%=t6|V;Myp`pZ&msJJ?-~FL^Yj
zUUi)1VRXTI-S>b!z3C`OhBH6MHVICVh8#~_@S0iWv{R8gsW+g`u!oi%7!?NB)s6>D
zu;T-cRv8a5GR*`T(SXp95oRro(FPtO_dG-`uLrqN2^TCWwm2o902#t{6LhGq9+2at
zCzC@Uz{BB!3e+?$HW>bv-2*!3)p@(7UX#1ugvnUq-hEN@)t(&$yf22j#Y1MC;YVj@
za&>Br&b0lZ17Q>qUosPzPMVgax`=no*u8l0a)V@sUE3pjk6Ej*Y)$7(up1~;HXW1}
z-RO^J3}?BO$9_e{x+W^pMMJN$Xk3REUc4*S{!tf|W1a54UQX+%pp=0Ci&s42z9z@J
zR1lPu-q;xln=nT;%}O>2qX6&1rQ$iwcSG<W+U$;AO0#rQ<>ht9m><a^l{yacK}M5}
zXNfx%TPbBY8PeR!cP;7m%Jxm;dOs_O@m(%v|FQpxydVUtfZrSKG1uBX6Ium9Ouv5N
zlqE9L0}Ov%GoWeq8hMgCh9fC25R}+jae)O#1!*G?MCZYU;^ezx`ZVU*Rz;q2c`9ho
zv>i5SYgeS3cGy>Gh5S*~jah_9TN}`l#QC0$Qc*jH`*%?n{E#pglg^FawS`KQY#3Au
zBd>>rYFHfhOGr||^te>~$p{_Hk`d(N_+0c~o`jRq<kFgHC^-IXOZ({F4=PZuwt8d3
zLL)YRrs1mZ7lhtp36;u$c4V7FN@#(4lPp-HA|BydGS>tl(cs=ScyD-OH{l{)=C=TG
zQAdry4~~bcERl)XYzrbcA>aCVfsUKOHkwGapjZ%ap`ucJzUbg%)nX3uXk}vYUaJBU
zEWNdcaoZtPk;F*}YjG&kLQ9=n)Na*?KsFdKWiCChK~dBo>nq45(Ed`1Zs9sdMsa|L
zou?<&w5N#@h!&$s#T^vf#Aak<SfVR#+|haS4FuM3&lS*eL&)gEk5oIW-N{eZM!iN9
z=+MYnGzlLTEL*3wbpp4uUe$ABP8k#j9GiMGM4?_3zDeRiJ{7xGx4(z;>tm;BzIG%m
z@fIR%|LJ%cg*_G9dMpdi_=kk2|CAh)%z1Sq->TU2`|%Et3MkpBooW5RirOlxIR(p<
zDdIB*kORzN!mA7!QOyaAOVA#@XpVY8idW2_Ctn|(i}$QZh5wG(gp+WJ4KA;oGu4G=
zz8`6(BD@^>sb$ZpLu)Y*xz)h*`Y8!+ieZ+YJn%7Q9bfYo$QKI|T_smyAN|?c)K%;P
zEZRI&>N=IgY$3D0Ov1iB^X`_a@A@S1<i7p8AWhMX2kl><A11|=lT%AnX1gxwO|vU#
z0rY4%JvjFZ6%`ZTf3|YSY_={U;n6LwAi%yPFG!lZs?><{a$oh3v-+>N9&>=PVGdsc
zB=>J$!9foaKLWZ0&gXH+8E?x0G9<Y@&3~9Dj(QdFbza*{gSc8zb-jhrFrGU=djnTK
z5VQ0ZepK+X4AygA^+Do3^2&Te1hk*gMPL3vY#qkNyJBWeISDN~HHGrJKFEDsCP`<6
zpsLzk*?R8RbbIrIWh7Z#o8=6GWFNk4sO+}QVe9#_8%E_YPXfS5f=Ou2_U9L|j1B4^
zEwBaUsJtRxMOzIIBY|=N%6heT=q()<0_Q#eXP7VwnO0;Elcje7ovOx_5|aPG5We7>
z#nT2lu@oahjd1C!?8jVIc$xp5<VnEP`j8ForK42N!$r+Oj=&&0MJ{GV>zy@D7nzxb
z)%AMpRx|en5_aXlLIzDk%+$^I&7&k4!>DTFj5ZSIbH%*C6PU_MozVonk{}y0(Y!3i
zb(<1?T@cp`j;TQwyiw4+JkG9MdYhY)Fp*b6hsMtb-B!2!8K!?h%P#|v8+Cq2`JZNq
zQ9ZTW;vMy5M^{phzi4SYY-+3bc-xKHp7U@_ryPJ;Wss<#bD@S~Foaw!b3`J3z;GB%
z^xD5*mfcuKfz@0Moz0H=K$A10Cdf|0q?RU%^6n%%&Lzo<F{Gf~4#M>)18ZQP*5zMS
z#-VGw()7UW59@H3`X=(KtEy%Ujw6R0x^i3{mv+V~*<AU`j&mHnLq_Gn`QZn_Z6e8s
znX(j$@U;CTT82d})!^=Sc<HUbHS3_Vga8EBZR(i@U!i+!iDHFVIfb8kss^|)kKSY@
z_)f$n+h=?7|J}~=;b*s0poit$bh*YbOAH*}=I+L98QvXA62!dHfAOrd)`_EQ|3*&~
zim2(ucd<C+rCmd!sDiGuGYDj_kZ*m^AO;*tRPnzOa4KFs|JAV==C#$z21y_}{6@M9
zH#*GKksq|_*spuo2>6B1Hx>g-(g1xkg^e!%40R8Te(K||1L%kCBnSSWDrC^QFR;0K
zV8Rkxmg!iv4fqx7%~Yp6&W^6VQ;iw>PteY2iymRh3H)#!P;(A4?fukKY1*}pO)roD
z&d?SFY%xHc1F>g@lg$OhkYM*Tp@Fv^8FA=nV6s%s)=WS~>PXM@e1m=KMCu&{+0Nft
zcb}VY+-lHz069@lW4!h?j&gc)o?JUA^?~V|3!2ctg52}165sP?Osi}R310yvAj-`K
zNcqH-BX+8da13lQptcejCUpz&mRJUNLcJZ@`Z2mR_<m!|0Ap))m!fgS4IexWohPa;
zpVl+p^5EIFzUq9qQHv<2LkLVFyOh>xOT|>tlk}zSH-=)VU=$ydisqC-bHai1;jGSb
z`8jyuIn^$LF<W4P+n%d+NFx?O5A~{Zo)xP5feW~mj_36p1Q&sTlhNA>L&vl4C@uXE
zM%RYJ1$h{DuZ|B%_=<M!OY@A;0Hx`ec!5LpG6yk~`$s)O9tOW4)jq^ad!HX&G8cKV
zc^&EdR<B5fHjc;r^vQ#P6=t*p@3YbhCL0d(BvAEM*S(X74~c%x)PTc*c0u?i+LN|M
zR)`6xEnN#?b;g!!61SHf$h?BAua!ze&f5|L<Fli{O9u0sv{MRcN9=WKH_1kk4q`Vg
zD1tliZE?yC;*%3FE_c?>G)<MzMKT5I_(zMjd@H*E-^)IOt4(}plXbfi5Z7<5-}lfe
zUow)+NNsWBP6P3??u;S?_!rt2tNqVot7NVzSfNae2@MEN<DHm_%T5I=xC+PcykvmG
z71)#2dZ#Y&CJKh3?d~I@_tES@>V_$jzh@Zbj4=roVRb>^Lo^eIJFDV(l7-=ykcgl6
zPIO+6Q`OA!2s%vY^(6h+sw%ok^ZRC#Bnj?9<ybGF^htgq4Xz>y6xz2!8G9>3J6C(3
z^Mo$vPw+e3A?d_cm>k46`%5V;D~GKnsg@-;Lrpb6e`3u6sRmFjZbv%=KIeD*R|i`?
zXb2YP1Tu3Vho*_Pf{bNG>R>~%EdRpF7>0Z2h~Z1Fw1BpI){9|~V1>*bsDPNfhs7N+
z1=0I@CtJ*a`%Y?7g=X0UabRbP9N;iGyPhr=#_nQva#<gM_(AcGI3hVlcFi&~|8jRl
zc1eAgT@;9m>SP>%hZuK_Zb)>sUW{9F6Xn<`<z|{H(Q@@fh+aR3K54krDXk^9I_Z?4
zv%4A;gjmwhcC5yvc*QtI_q~aH#csM01_fFJtJtw-F$4jumRH@AHk6<4BOa`4v><C=
zFenvxpMAbz@Wg<Z{=8JJU%}+65__!{^=syRuFj*uI8n$f-!c~XzxGwr=v2TtK-LGt
zjL$2&|2XzTcSg&1v47s3a)}g7rE^J()QQyVTwQ;$JA$fx-4x%y86^;?*;TW^zu_EH
z$sufsoxU?_7tDXJ4##kCnp{;Lh>4OeB^;~(suACrswVQ0FI4T^Q(Vyx#3*EJMIaeC
zH4n8;t~^H<M&$RH+Q5&N3a+n(?hIt?t%p5)4s}7*o3GM4PJifzbHQQTnC9D|Fu~ol
z(NJ1xJPjhD4L1T3FYrBkr=D=)*8W_yN#RxP&OI!u9sVL)m^n`b;NO=%-G7LCom8wx
zW`IfdJ8Osw<(MyEy$U?is1_vF_4wOyn9c?^kx%IS1)OMfU(>?CBANKfjc@70po%Z!
zj<BaovS)13)v@<6<S}^gSK+QTAeU*ymc@Zz+EdS8G1qn@bi}8Fg`7lFo29rGE?$IB
zGUa!m!yUo`Gn+DAIdhQ@+qB(iJUcEE5HFFE9Z@Xn!LG;a(e$!vQt^;!u6<M*uFL2&
zWB{zn2=-Sp8BtaCj|>+e_k_(Q8!I^WV49QLr8H+F8kB>tR;+5vD+>7f<;*}yyML9a
z6)aeB{bm)wXKz94Nly4g{<v4~pcH~cEeAlo7Ic?=XzxE%NMwkitgI(7(x%5MTF<!x
z`HX8S;rZ+{-D<47{7XLGys(bB3_!4A94~o0Lpkd!-~T|nql8TW_n|~1@DZ5Y?(KkA
z(6R1ij>Ztxjqw)pNG@|c2Cb_UR|TG;HNLMn9WjLbwO$*Pv&_oWuT6`L2_Rj~u$zWx
zpddx~M#jQ2dxU1sr%7w0r|RzZ{ap3%H6Cdc-b)1q2B>@>>1d2$ymXIUH$gdKfS*+p
z!i5&TaRS(h^ulpDNdnxHkW(V{(0R%!6=j8;5Sy1c(hHPYkPeQ;!$^J`4ffd4@t#$h
z#)9dm_NK7Mii_mv5m6#$#*Cf7Etn%(#?F<FG2JjPsl)<i<|Z3@V<nlzRC5TE=Pk7z
zR1}4eUB<33O5o+xc@&)P_6^-pHqGOwH(YR~gXrPJu<vo@fV_hX)m?bjY?niSt5mXt
z(b!5T!e4k}8%0zjsk-()f44`6)W<BtNR@+eylg!Rfl*om*g~!1^A)kQgwC543Sg9j
zp?PDvoB=qZkQL>pf0=g{Uz;Q~vc=^;**clRbl>x(EV=o>j;{*E@n91ZupR$MFj*kk
zbKR?c0_3;ZldyUwe01xhy#j5BBZb6qoqgRPyU7KOT3E*(nVKt-6gW{>$TTQK?+{UT
zGC1MBPj!^H7E*YkH(Q2rexKf}wkRm>K<Lx72$=HJ4hr6AT_D2rTKuf$VslUiN*o}M
z&g^H?5(&N5OViOq$)GAd+yYiN;WdH@7)WqMR_uf&t4DTt%0Al6a4A<1<!Rl%Y3JBd
z@UxR`fyMQax5XxbT;V^(p*X6HQt{S)QIx0u$v0!IGp(ONvV%RA8r|#Z>RU$49z7%6
zfL{~&?XV{i4Tm)c#<_K0)4XFpQ}SN<*{y1|%8mn!GnLLktzX}s;>n;qn~(x>FY0C1
zEmod0e$iWK?I8(_O1UdDmzms+J!^T#!d6|<nXDY0{x0POC%gC4wG27^5*T?r?%?9C
znck4#VC&RCgpMKCa}ung>V5sQrXyWVHG)zzy<>c41|cr==$><|*F9UFK$&L}Zt0uZ
zVh?@#@*Z|}{!!8gMS#_Ur?QwK9~=BuQaQGJ8NA(nBL?|m90J>-?$9mV260D@23&pN
zj7e4wez6+}%ds*6-fITh!7Pv_PAPtjg(DXcW)k0LXWIDD1@y(8iT;HObNpuxq4*gV
z5O9h9NjGOqi8~j$C$@`K@<BP;K@L9Fr?Jb<YktP_KANjB3y;p5c^3Q;79B|_qDu&|
zjScPl-;C+<t$8XjoPxhOMUNhXf^y?St|1t=0Fn$~vO+}O4ippKHAdYsTYrl}iR`iK
z{g7b|W3>7DMYE=9(Y`DsKwlGu`v%wt9=<g@?eiN^?5qN?1&6qL%4_gd|DT^)aL0sG
z5iv$}vZs3bGfd>*6AkRQ>*E#p3qNP;NE4vGXi{!HgFcGXQq)iFh=U~oRuZZ}>192o
zqNv=*VRCJBZEyg4Dpr>Y+K>d2|8%fhL`V(s(W>=8y+Y~uFp;neVo1u$8RBnsC6Pe{
z&aujqV)>SH;&jm3v;Fy0r1(yg+a!zvoXL}DpiHxTq}#Xb?{)QsxC#Hh>Kle@JQS?j
zr*0K$)8d&8lmurwtTY1=@M73e)2j;r^+4oIT1`;WbY$fvhM&dCO*YnV7l*Xn?j=j4
zdw^Ici4c@&63wBx9q?<zyzJmnB1R}QS)N>gOc4}~`cZG}pRbnBC?Y<uI%br%1DA7(
zv01y#4zpT$YKSB=hXx#=g@g&;z*t7(g{N^Zh+RS}G;=74OQQzk94iPtn)v{EE1LeQ
z|AJCV2RphHbFv+#OxQ=_FzxMhaLtp}B9h>x0;$*Frlt)Q5aXdI^Z?zIG&Q1;6cCtr
zHXu28$5<$bXN++zq23PCkMC?`B^8G0#Fn?epJxsAu-I$|iLDEAJUriWfG6YYljcE@
zx&U#W$SHarow3W0gW>|wA{7e7^-RV6MxHy+G$k#2l7TVMjLk&F*rJU1TyP^BC{j<=
z2Ky6|sCFBpgoOzTD2nV>%z&z#rI3{hb9^z*I`h_r$+S3jc>^BEML6hZKCzA5ofW%$
z)6dG0L&KguVrz|lq|suAN)#{Bb67uUaCZoWFCBVJVVa%z7xTnwRrr&1R#A0_`_ZCJ
zhi%a?yGh~xpIUaWDI1{FNMazw>W@thazc)?v9+Y}dx4T`%phLAr`mS?GaM0Eob~aB
z+x>HopUxbTU{lN?++!RgKV90+S<mOdG^TH@rPfe^M8kls<06~emT7QM>VclCr~9K3
zy-1a?3%X^3zzYO1^b_sOAoT?iLv9`$DF4(aYy|O&)z3$$Zh^%VsLgDD-y=H>d}1Ti
zmhQa7UE0xC6sL*P(LxT9xa?AlK<~2RXSE5~6A|AC{${Yco|ZK#;jpAE`vJD_i0O5U
zwc%+p(vSc>*dOFim*%CiX0S`f7edfXzQ3i4Sf6|ZT!USy@6IRgfq|6AO00j}qACHB
zBeoCiA&%=K6M$(?mnO5Aof{}_2$p)vo3tYf7KEr~a^Hhg0%!+D;j{!t9oR!8^w-o#
zrM?{iuxv5YWswVj(Z*jU(Gw6rUS3%OwWOAFG_~>+k2=!W+n3Q!kQMNDABh%$C9k+x
zeO3M!nnSs|c-OqE;s#B&xG18yS;`+S3SWRef;|DQ=9OlZXW4hcR<+^=HRu4Bq}<%+
z-uAg&wKPjXt58^)kMy-T@C0i3iwiyO;%0e@n^(KhMT=~;KZtWEro8|Zp6VP#`Mw*O
z=v3#d`Zo&(sUaF{&ROGx!ZJf34#7N1l>EJ@R}JFRM`{uZ=|>({?=>cx@Yfc|{~R$4
zJcbOg0l~&*r6#lTEYi|pz52hgIZlm<>&{~)+F1q~*d;MNcWPgdJS8a;O3?CWz^khs
zZEeQ^=`yHG^K6J?KTT%U{5^o^IsRNarxU>|10|=XS!kagy|0jo<6L5{bXF;GOs=Gf
zehwMJr3fJ?V@_25FpH$twOm|c!0=Pi3AZ?d4ITqQ`f(16gsvXM+FGtRB@zd!4F}9#
zhtP!~2WR|uq7y+|Cy!lgOXO^q>CP4`hgLEpc|vgqNX8f23h;`zuc3AU;N}kt!*l|s
zJtfzBk2E|HpeUPLs=U1qH^zrNbf>_Nv%Y)$5$m^ug&Gw;T=dJ%HGiJkzv?PAGk~Ce
zYR~4H<MRMc4W>@etSRt34_<aUxq`m5kGUK}0pF6Usp2_m?#muZm3YG1_eVb{+aOz1
zm_atEy0+q*6NgNwyt!+4iQ=8f>WQ2+1^@`^2alBM;ZUQ=Y-~FrkfUP2qat({t|GzY
zU}pVC`tD4CZ)Eh`s{!#-WoAE#Ykl8n>1FQAvy=p!NCR-F`f`02`dqz`4de|fbHw$|
zRHsY9a{B?e)K9e{mleEXt4xfi**UNCpsz3+x-!PRL~BTH%ebo#ath!h*EREn`K|xP
z@VjF$JB?_eA2sTkuq)>qr^BRTGQbMzOI*2b))<R9Lm)CG?v+j>T{Ek>d}e_e6Ns>)
zk^29eQuqpEi7CSBQ9AU_CwK{MHqiao`fw|VttDFc+HSHhdx+NCIyfVwG#d+<a7GyJ
ziFo{SV?<q5<3&ppzkI7E*_9u!<wsM5NW5AcDU%5OL=C5$>R47#L=VzBUQFj-?J|&S
zPJxh#crEb|bR2M1f&PReAaPZMDLI`<ThVIynVtID^9oy7pcE8X!2?wH!i2G`ylxS$
zH|I&DPtQRlWDKhB$!(2;fxdXaG_@>+-30sW6U&nWud2};E>!O`?`+-9P{afY@sfqq
zjrzVCgC1suviB5EUmbNR1dk;gIF&_!0>AHd{T*YrTR3YLXz%*AM)<vqKg_1;zFhwT
zB_UO@x3{`2G&4}vp>2msMJith+jUCrk3eAY8}t2kdu`D~8vf8$Emd2vownHzEu54o
z8<x#6enYC0W3+itJJ>FDHOqPmxGrxVo-&x?){8n+2Y*6dC~NIyL8$yBF)-uW0RAsQ
zf1eOSzy2i2vIG=Iy13Hk$ssvDZ64Nbco}kSCL-3Q&z0btZ8sY!?lCf0)s;4c3#Ib+
zX-Gn~ziuR6FE}7e<5)~Vu%@5Ab{?K^7ww-mq<^!W_-+7yr=hMG-Eyrqh2B=SF}`A5
zI9e((9s8yYsU~bT3+>|0{R4^!p1b>m95o0dw#k{x)VA&_qnH&&w2#v%+&TX7i>P0m
zL92*NLHrhv;!z2)X(51T4H#8y*!0<18Kb-RoAN!Sd^+@GDj|zsIP4#Kyp75)W4=Bp
z0LH)MuxL-U|CgnQq4#48n06$0i~6=gW$G$22@tJ6Zu{L52dG#kaJI`$H(|C+L4%s=
zuVC%}>=02Bu96p6jV8j_Mu4_|4FiPJ(hTi3#*xP$E&<7)`C$TZ-_pG6tTf&eF`)v`
zGNwRGuU&W7{w;?9gwPbr8hQPNwi7nU`vg_snFC7vA8HYv_TUo}-7Xoq!G0b|Lcacp
zP0E7T#5DIdunx7r;%hs~KGc{VYh|QqDKplcMkgF{!`d}RE5_NV*>IM5RSL>lVyg15
zr{KCZ${_1gxj?ro%yS#Cr;+=Xac*cxjJ%V>d-FZB!Ujk?6K1)_SQX2;JQ9hxhQIE@
zN}(YcAMPwY7BBB<!au*NSS$|q%J0sDFHfEq3Cg;QspyJB#H9C}Q(GBNlq5Q|-Ao+}
z5Q(F#_CdilDT%vEdjg(u(H5A|%Wd)iP8NQzzA8Kk1_71O1T~zsw<4u3hsZxgqBj``
zKwEE?kEsp?Pr1KNrCz9@7T0%cc3s#|+DvVfprV?D4JAX{R29t5*KAP{y3Q)2T&(9q
z6yDi@30GB>sD3D+AwcwCu-oEmrYF?U7wk$dvk^kprJLh;DC@zAz#tN~9%I95FkdNz
zDPj}|uh$bc$jf=-HjQBL75aen=roZC%m`gHos{;ua?tfor^*+gKlFiG#UCyf{WH~F
zb-bp=owG(pT8RflDWU8_;lxoq{4=<cH<x^|ehC`&2l@Z#E-Nctr%lk$D)yK$dH0f+
zoj_`8Z={<3=O25LaVqU5uYXXT8jxmfp$?&IR!86U%bQk}_3|0wip^xE9akB^C(I7a
z(><_@uPS+@a84fjQ5WB|8;J#d>dGhU*!GlOaeU!>Au@DJd9h<846!6*$(LR+Y4SF%
zfZm<WZ4vd5Y#L~(F@k!1tzgj%?fUKL#wU!P=~42m0;ur}IWZbdc(@~(Tl#;2_WIX-
zrjrMBXNBF>GO>?fvK7o*u<G!V3?o;VanQGc-b+$`1aq7e_-Hz<)`aI0GN|9~L`E$x
z4PEZ@_ZS^SY|#VQ_8JaPl|o1E_MiA%1;+p!@pTN!a=fB^6-0@_e2I4iYMmlpkeD}H
zA@g2={REjHm_i9oY8roz!CWNIx+%%CefP$^Q$nUxcWdr4yq(PzjB)g-b?q@0w9PJ;
zvq5Xm3M(|<CC0YjWptIOOQMvz?HnH**Lmn^KH$58X(se3S2a5IF|}t7!-C=?X68(j
z=ZJjZ5iH5*e?ejju{s9<ibpjcP6ZOF7*muA)d6oitoMxegfka#ZP$}dt2SzFEhB?M
zq12L#Ug^TY-dt{QlzT&@86c#GlF#l<u1+itL``Bc=Jdd(hvN1SmO3!pX|iTdZ_gU?
z56;U2&mc?t!4^!$)|K>`5``xrFupbDCeFq7jk8y+-JxA;q<9~$@*MTgFRiF8PSPoT
zr=ONkQuq~IkV1!RZ-qBaN%sqY<~nh&YE^+M(+6e3O<E1>mfF6bq`t}i#*O|*pVPj+
zh77A5e*b*WhwKCf4sj8iAsEe5FKBhrii>4-J1iA{*$7+FvK{Krg9*Xqn{mOYzUQOO
zidxrxzUqO!ExlJuFyG7qPhp6^R+H$V-F@Fauo-P{)OSb}vcmVz8hs|g)JCw-yztvt
z{vN9s7F5f)x_uVEr^z948A-~P^H^%94f%fxmh?&~eEM<r>O9M5kF{Is+ZdD{vVdz}
z=*x5L_zx`k4DEyWCc`q5D%AFjwLYJeB?l_)k5AAG+-a6VI5qoREQP-I1Tr%|{zxgt
zKySLH&PMQ~V2St))2)FS#Zj<nuKu`Y)JZ;F5tpt=AlmnldN13)iyOAH)Y%h42ME9-
zQmY4|eZP0&2qHA?o@PZURisFz&TF!lS>`NKTKk!5<EFo%%gx{A#~h2)U&3KctK6F<
zn6OpNaSk0$F3dQbi+^CtBC&%Z4UxW~r!qo3f-LT)+#42V^nIFySb*D=pHQunFxJU0
zc{YfUd_}BC_D8`~GuIQ79AB}k!b^2^;s?Qw4J+ei`8Ue?Fr;v_Eo=Dz$~nqsTNS&7
zp3q1i4&HvVg~(ZSGAUO;0XyvB=F?~KWegyxWwf87YA_+2q_pstdpV+((b1Fb&}%xb
z7q!cGE%7cm%C!u;pjlV})Lbz!H1q9d1N}054TIi3k_?L71UpcXg}eJKX^4{hAQR_}
z?;(Ad#S+baVLIRQG&)+}3Wdtz!~v}ftVMyv`8}AWQ)HDj8+feTg1XA#T(jmO8{loF
zq?fWvMA>z#i8|pUe(k;e>=eb(u8)uHjT2N@%TxF{r8SuE2(LPQo}XT=N<@1@VV|$b
z`dnX1siiK_Sow@g;V)pw;jJenQkj%0KE#Diq$VPCw~4kYObBRdH{MIQ6Q##EbheiB
zN|c);>S13qfTAJ2m7*&JYFPqmpzZuar7;1zNox8nf`{ahKBw9(l>I=$qi0Q3?5L=x
z#=A5+!y+}60--qhWW}TFr<KiHkNP7a4LIt1R*hAw6ifq^+Xn%;zMZtM%7;+7pOx0x
z#^3wP4}XgOMg(7nWbX+1@BhUS0>G{Sh@e@@)^Cx=S-nS+RKxVmR_c17NX7g-EXIa*
zJEsyHYUd1?{IA}<q~~GY;uFTS&=BE&z&Z*5#zg^oBNV)nw%A83E?ZdLPLLXhZ<p4W
zTZpF{(zfWPW9<{8ecVWTUC8R*^=ig=P+aud3txqI4})_EHkHGoFKRSod&}b3H;EZm
z)>iKd_W`PLfvBZyK42u5kjrCwv)=xV9_f9|bO*j0Ungrg4EZOk!+_wd3*WZ^6iz;{
zBm0v2>J6pwyaEU>Y}ygIeEbB+trRqky1qqRF#f5VQbtYW4K~oX-6?x{DrU#$Jg?dV
z=h8*M@`jw`*jPS`Ll};*Y6$f~KZFi1Xg->=V!A`|4<UnS1)pgxmGNY`k}n^eXxhui
zxCgt^h>@frE56F_v<_MWSQC!lp>#S?etd+x&apeu^|%TEZwLauuBR`;D&*u1sMa*b
z^wIy%=7hawnDmH)#OlsqL$(w;e82)QVm;L|-W}S(tFx^svlg~VLy%3pY@nVS@CIal
z;#&|C)xP}d_WV=DxZ2P`yf%!>gOvxJB|z`bf2fH7)ck|#GyhHH;UBw`txEDthaO-F
zni9?94ne)MM6^>m=zh(rxRMKlKCkL?3jdm%Tg&;nW2aI`It*Tas->t}u%i1#MQAGs
zWp`Eu)lj)Q`3E`WE&>LW6hX_AaN7D}um17MzL!;cKXIb(Ve5w}nXsAwt`#diBn==q
z`CqME@ISC=xY>Z(e$>F(k1$H2Ybj0L@74TIo+USV+jvu%s+X>$Vm#&ZuY*<+bk2WV
zP3Td!UbI1Pw}R5K@KgBGR|@H((PY!Aewpb0AGoqKi^T920s)#&N_l$^juEJXREwcg
zjW-EQoA65;B$}`T=6h}2ZMHCuB%tV>-L)^9CeG46Ak}`$iij7Cxc~xlru7N!C)4YY
z<6{Z+CI=ipxiAuZxM~mrxIe@J1?BUBR0Lm<sx<Rfdj@A}0XxdcP!rDY_whOfCr%*x
zB%w};%90i+GR(f?q}Cz_AP#(4qlrA4mph@y10M&rugz^0Czp+@f3H54F00e8SsN6`
zH{3N+Allb!V;?*-GlXnf=9=r(5cz+UIQcPOCBADO@JJy0rI*rnK+iOHi5e_HW7$+O
zB`^p&!FUgE5_qdof6z56YL>+HcX3t2MfM+qXO#fTf8t<dJw!wy_Gx0fmj5du-Kfu>
zjpk!H(N39df)l`HT7*gTc9irP(I(n>e{icdf<*NgE&z@1>dAr(BP;ow4?<Pw<v8x9
z^7B`JMdT8S1&F*YMk4#}{-0ezM<EHi03<NSZh?*7Z`bVtm$^P}R*xl-^izULMn6ZX
ztxFD?jTYhl4%WnNu^37q=(6Oe|A_KaRJ86OByr&X;I!C|l|Wt?b^mxcs*Y39v#F+W
z?dtxOL<chHs32lc>N_&W8tlY3##ql@q@v`Um|B=^r;%)lA4hK%6!jgpmSXB2^4VcT
zT449#oP4+JH}b-sfYoMQ<6^e%{6077(rggVo>*hozv2dsxWpzcOUDwks&gqth?30d
zQ_#(Lg+3w&HY_5p3dob?2QJu_LXKV@C7`1e;v8h&r>PtIy}@(VY)-q-S^XO|kI9zu
zq{|s=;LmaoM=hWns3bhh;mIga#cn}_KeJ(LuKVkGGZ=4+y$p08?@%zVWi%lQ7lV_#
z?ZL{|oNJ<NF;V$V(1LLcA1Np9<I<CrBl<+}y=#ui)}b#p*fvGV1#F$zA84?mwd|=l
z=ro$8PAdz?os@9K_dkv{0gtqSSjGDYjV*l;=)oMK05K!AZR0{0lRnX}jsRMySyH6Y
zzQ2c~fkWf8jG;s!-<mVd#s0QaD6)=H`#sI_o}TG&z(wP=s78I7X`f)Zh84_6nT78C
z_Yhj`Z6I%EmDEg3FF7!s@`Gw?p}lSu(eVu`d{uUI%p^0-G>s~`Ehu^SlnKHtl?zWV
zY6XQ%bT=LDl@-yj{`J0<WT~#Wn$1h&T7<|Ui^_lYiV~Cg9tF3+b)0A36zT!~{&z{D
zkP_JZz$|39+(?zN0kkf$u4;k!t?5DHPEIA5*1R^^1x?g?vGrIj$gct&ia*iF2kJa<
zuXp|^?E<)amTf>t(_yHhbALb>{hIGF;hw=fs=!5p?PwntJc7Elu809WLXNcsub*jl
zxys5+dfIOL$xmydx~8CF7nsHy?9`V)_3kaCTN<NU!EmJk1OosRlLalo7T+9q7u8{x
zNWQ%I$K1N;5KJgYHO5<=rP{pVDMY#e66Po8-ezN#l+%wG(->Wy$5U3)q~C884>c+C
z>kD17eB5E&QT*T?0h=Y$UpgXNZeslTX@FX!rH*Z#*=JS`nc_WGNN7N~TYVOG7BT4k
z_qto3|C-}|A&Wj;&qfm@0;5DTk@8{!aJ(kv?Ea8$q$N4@t%7Yn&BlWy-{olQ1e@b0
zgM_SE7IXNj*s#uJem#wLef1Pef^kV~V;Oi3%OHz&nAjeBWRxaoG%Va_eR~Iw?Avw!
zx{#J&uBRD3F{r-1{sThH0h&d~Q&4SNczxE!W1a2Ir{><=yCdTjmFbS4KWj&W){QjE
z*b3x!!#W7uB>q8uW8I)-&9m|17+=C?+lMq0!2Ef4U88*2a$3BcEe%MnG^$+>Kp@~I
zBT2(fYL8zwu3D$r>c+<5OlVWZfC=p%q`BoO+OKI^hOpxxh(_NNq}~n*{+Nbc>8eaQ
zO&gcm=fAGiTHOqK37q5Kd!ld|+*-Gl3L;M{fM_QEz(>zFDY=hW?`I$6YW>gY)D>u)
z%_SZ<78rb_C`eUPNrmHc^&JezbyZ!ZXF0?aghc*mbVFbzGhFR4p^);`@Be@rHpekK
zw&>#<Pjs?%Bx>crz00?H0Z6$|;td`>`c(rh8g)s{`^kWUltS!5PGqB`tgU~bs$rC7
zt$iPCTn##YLjpKcYMs>!#W%*qiCD<4N)S)#fCGYxbsCA()8W*c6X^B!pb0_qmfH)h
zK@U-GMVNhi{xyEqC(!85f5x@;Y21|7)=#E}BYMNk1XFCi<CXnGraRcnRKFNiaCf0B
z&1m3+ru85x<u`Fu9_pzj+t8%Zzx#Gjs4uHhkQ`cmxu*CDM_v5lB+jRFb>_1*<WQ<o
zq~h1nSSLsY7>!O1xcw%?+AQL5dLd62Iiux*=dCmLzB2tD3V6Qjo69J*C^b-NQbmg=
zWA>M}!&PUde8e;Jt`Te(l@m`8ujY7deym{ddxxFX)q<L+Ip*YEIqN(z327HjdfcpS
zCiwtH*u_(qJiVLCYm&LdLrm|y{RwMZF{?*Gr&&}N8Oo;5qn*S+H@=ww>j`33&TZ!S
z;*{G(zs=QbiG_}d8L+Rv>UtrvqvU}=%Vn0JTZdX=6x6lVG>HM4neleB&%GMxAkDcl
zU+C>tsx%(m-lzN7X9<xi1VkT-Rc@zM5WR=_&Tz))53GG_Xi0?4z9-3H;o(t%Lub4@
zX>0^z5rb`H2ZZFxjQCuVs@0&YW62ZUaO{(7Sk&;tK6U2PbK7q#S&f{`ZCsl8`J5+B
z6jE?=SDCRLml<7bz(0pj*nWvruXrT~<X=wTYqZ#Y@GcNi)Ws}CGfVy?3X(>fJ)|Bp
zBr8^0UydKztaGapii;y&nveXwVLoK%FKe_4EF@lf$_0Ef0;`iVyuw0ybR*oc%nPSp
zwnPs&HzYQQ-)vtS6PF??GGM>QDTMm3g(zb|=cF5}tW!a1u)P0*_6IhhvVYCk$H}^)
zl*Hd0t9MQV+qr%s>DL>JYO9)#fs2RE{Y4Xq;fvvcf?t=xzQNWBQ%kCiQJLqZw_`F~
zjxT%05YOj?nazM<PiUj-tRKppNBlZNY%+J@Z*%DG*&hw|Fp7fpW8!s_%#d*P-~;e4
za%qrd5Le#j=Skr{tYNVRxzOiyxIP5_wl${gG7~ocu2DfzcuNBXdQ))p$JB0w^z=ES
zMV*w~%<zwsm1;xBA<T>@T!;WbLRhxVs`6^!Sk>v`@1qzXS&S@tN@Zt#JfSA3^?hT6
zE$Ztrgq(~an{y;Uc9ye7r`0a<Qmk(19s58NStF`>$~IOip1q+4a^i&xw~XUU-_icF
z>wgK12>{y{cIR1-b!t|fS7Xw15TSN7x&qJ;zuh@yA`Q;>*TEc=rn3NgLN1)9WesfM
zLcFBv?bEVAOy>#NNWAYYBEO2Ryz^`SU&eIay2WE4qpgeYmW;E<*DpCKEB7tkacB1=
zn>BE<q>7xodmn17=*Cm;c^hg8aKxCIrU{$$>T0Q6l(#kH>8uW`?i3$GwyiuUd-@>1
zuXaA`$T)I#`kYd?1co=(H}%aObI)GA{JjZ}i;4Qnsqcm)+?OaCeI-I0@voaFk#$3j
z_Gom>x+$a<Iiv5^FJR1@^#Qb%Hkk<<(5+nnBoMa$X*Hj5b|c@KJ{}JDI<A(Ccek6S
z8&wf$7G%8wpFvb1@(*(2eXX>L6{=2(Oq<Q={~31P1B}C+wxf4F;HyI!EDqCTX)w}O
z>_{$`2UR1!&5#*P#(xEoigo2d3$iL<MH4Br36uZ1EM~k&NN`kUJy`ABhW@|S)R4N<
zEJS|%#IYr9dz+Q~m>OwD7bFxGikrl0b6a5FLZSeZj6zlI`3=}apTWH5R7ZM8eQ8<6
zzo61FY1?#S2gd%Gk|y6%-=l$3@NV9T_agI0ISd5nVdV#`|Kh3JPf)|h<x{yjsI2ML
zw#QWPRCw4V#Pqf~!L^9kI7XZHIWqr)O&3h))u)Nmwq;)sSe}=`9kl>6x3r6(Sc(M{
zoaE@>aFEaPBK!$S+wIK?kG#eUp(lq=LuP)?)W1}Md<^d?L7CRNS%N^c_{LNos)|pW
z0zS%^0Qg*FkOAd^<YFnRydXr=yf-sjjF!gJfBGrp%f$nt-p@B?h96rHW0-k&35~X@
z4{H@gB9YX!y^0f|Bs(iDL15Z17tmQzSL%CD{|=6^Ow|6x+P#)6R!mS$uqW>ziah2o
z-F2uT{B&#4z>LA@B_YKG3;BT>ET4Wvtgs%tLCkAkM^YD69kvj=WZ2(uFJ{sKh;Qzg
zeYch3bthX(pEh-pmslzE={Mm<8#UuOjc&qxN^(y?%Rq0qVAE2`RfZWa+n2y@^oK9+
z`YJTqBeqq2lY3cFQocaxQ7CKxoLFk&hp#ks%K1rLB<afvXU&$q>BRrpK;ryq&1ZwY
z;8obaN;BzryR`*W!CNTEXSc?B*en(riT%o66>ZUvk+Q>#`!?fG`(ANBcg7+(@Y7aW
zy&Nrl@~kkUQQwE4rH#vX<*vp^NCy$p`FpRl5Fz%RO85SPVY-^b6H=NaM=hkJKA64K
zQ(?~c>Zo@T<z&B!I`wE3l8OKgT?O_%Unm&a>v9+?hd%2kkyC}k0z<=CJ-8H^+klUy
z_OOUVth-DsIh!2u#cB&)c;yKAZ^Nor#CPkE+a$Khm1DjRKS5Kq0kAREtk_Pk;t<lb
zSPV|)9KIvH*X4mQ19AT<eQtPNj%@sRdbcCNto!x!xPpiNfa^|cSJ!^$`{(r`8%Cyx
z$dA4Ym-!;Ep$q`}zTk9;g;{iKQ>1*y#?;3Db(6;#PaI`>f3Nw`AEppu0R9u7I}8x`
zIq2fnfKZ=X^|MZdk;QqwtquN48_e;_u=X|CT@Mz094u<L3+o1Aje&`_9*<A@iHgk8
zBl|nsBR7Ovs(*nOMVPS3k^std<!nVjCcDTS8ia)JHHRLt8oMAwp)8Wpsv=R5U5r>t
zY<`;RB`~?IUHB<deJIrrR&uNiwa9u*Na6Gp8?EX-jbSbqK<Aa$Z+b7cqlc<?!2)tR
z$%WYwKzb6^&9cccblS%pD-|(ocX^FlqL=g*h`KbBAA4bBKu|5chfh~qdVfHkH#{iI
z%JQ!`WQJ<Z#47Buu(myS`NQmLPZ(V9_57!*BO1cJv=ada9wIXQ+XePJ$CD~NChU`R
zH8GT<E%eFPPJ^+89>tD-GD=U-a5b&A7H5cv<-XlIL?!U%G6YTk$H?$e4NR7v*Ct0H
zFP6O<>O>wiNiK!6Z{~5*Z!covemISz0oV=r-!l^VHH)e*)Vf>1XI}MOX(|6yco`!w
zH>0p3$*MZIIEg&aUk!uW-nM1>D$CAFH%yrKhyAV<e)lL;{X?w6S+V@vO<rXjxXUFI
z{N9V<!p;O8*Gww{nY<Yc`U=EQald29>H$nzDlL?jMHs~g;>uD2jMS(uEha35ji2BK
zMo(mon=QOQ&h|dJ%)eeR0)23*v)`XWmNn*`*~|ssVc{l6wsPj3j|Q`p`SC195MG<V
zUo}Abp??Dv7#w*FRkcel&HD{?!J4V8TE*0F&Br>5Su%de#Jca349xOX*xI}~BU#s=
z8hW+B9zu1%2_DM8iq<@@3S>lxmvpQH%r_fY_gSbk#<4~*zE|#T4{=W@+|$VC7lQ&t
z_J;T&$B_|!&+hLbg{f(3An-M#892@06$(_i<D3L|p8+Jg%jHI77>;%SUB3rEjoR_O
z8@ZN^6(npnaQ4uX%Y3T#gz5?8|GsF%u`%h~(>33AozXIkuL}?vyFXdiugBeWd$2fn
zG{yF77f@TwS*hkwA&&7<cZ-&NvCG)UbCtchYQlMUtJ)p=QvJj71}ghu9r;DBMaG7^
zK99|rWtThDMT7TeUp~n2f-Ps7UqaShPq@mZU^7F`m-^x4h*e}ms}1f*!&J7U?$c|!
zrvPFC$ye-7#kRlia@yy1&LyE`tm5=X14>ADqX|$FNw$?VWFI0Q+kxISRK<^}4$1&S
zD3PiA4=~ZH<{z+ojgNfp=u>5E3bta3lkM9g7=2!Vsc&P&#68wdCkjuVnR_Hkd@Jju
zBg7VVoT>Qd!yob(hwA|V7e?|W>sj8{p0W}&oAc-M-F4VHxi*alUPnLkOWi_8m)&)n
z(754mpaWWKczPBnEdp&DPIBJ%4NL3>dDP4KGCvxCr?w6xLm|05D+}99qcD<wSLX<$
z#<1ip!01T79Csn6lHd@y)Y~-gs*JaU^pD84c4zn@iXujs)y)somWuJL7>QxSe2@I=
zBXL|;<7-3e3?yGq2XGV(D59sgp`oJUkeoSOqn-Wb3El^;lRsNrzv`h}hG8O8nd~8p
zoSu5%AY7OOCc9UVO23N~z&SWuZZl+yYUE24RuteH90yucBT$wG$xn<gKyDMq1f8D)
z2kHcL8#N-0NCjwMhI#FZkm~a-{Xeu*0g~nIXkLM|))S<4FW*U}PAc4P<rHQpU1n#P
zlqI&s=`W26|2bL_IQII=XVPB<>Pm<+K%9^1@Yqdr{t!xzA%m8K^?dEo=o;$P_8C7i
zvyFl!%e_!vNTkNQ2?<Yd$t$BI@z<gneaAC%#seiUz!x!0KdmoE3F@z#&B}<6zz`g}
z^Q<LWw_gHO<xohlpibb2mKCQ_tuH>H@O&_nNjj_HBJ1CdX!y#<4aro+M`8^)h#k^h
zg`Yf5+F{C1o|!(;w3OOCKUmsaNsB@ZR8+fD5UCVE6uNgm88iC9Hsf4h<@kn+ype7u
z$>68P`NKV<>^KRDdWOtrDDG;$LY;ZDFjVwYSAVMC{X4lT=58GYWplnFSW_En*RTR-
zJw5EtkPXKb=A&Qps$KG505V(2ZZCMIJw%#*r;MD%aoE}VwnsviC>z#|w5eeTH2e0f
z;sNXqri0&ERZ?1G!ak%O&tF4Fb|+<pH}j>$CJeN^x5NaH(w?L>TdpS3<MNmiNoYCq
zRNgPLnkBD)j$^Ay2x!~d)6Y(=In{461T#0q^e2J5m>GZBa$~;`xHwIrF^Mh`9rT^F
z;_QE(sALJP7eH@n)vyg^^4-XRf8j@^%`7^ORQBxE3`{Y0Id(>8P_0$^wrY`+V|ak#
zt#qnl+Q7)cETMdEQSRdB2f(yfWh6={pgjg-zg^X5`k5>EH^#8tF5_M$sO=>$o=*?$
zWTBdmEQa?_IYU1QHdlrSpoF35*6LGnT32sLEp_1MI78pe;ctKgZhN*slmhMEQzprB
zejLzxA~NyS^U}mVL%}}UufHWutG?^j3N>l3`eXLW1=CIoRtHTHlw&Yc#p{BMqZO^a
zZYR<Zz<Fm#rSJM~2m~5>mz#Dhvx2#JDQ_%->&8jq-GDVKhHOmy$C2ok*f9SxL2+RK
z=ok}(sVyn6D7k(i@gqTQcJWe=TE%U}L7@N!>0TCFr^JTu)c_O=z`f`sP6$wS_le}n
zF^vjD?BGrt0B<WfNCk4wP!RY6-~FtcA)22rF5&NOyIg*CQO^-yu>YBYUPUCe$lWg|
z!HeU7T)sk1hRW0PCh}&irVQMXu*LA~p^Q|$8YPI%c>{fo>rag|4%}3Q`c`@aahx11
z_KTloikD{pO*Opp<b=yQqK9Vh<M{hc$r&#pXb`eF053q$zx`afN;>#AeB`*Mhsl#x
z<z<2*ja}vf-ZnI_TSB5KFZE@*V9<<OMjh8mwh^5-oG5igoyeflH17T=jbp1|4MUir
z%{Wz_fsoE%AbWYnAqG;mXyRLV9So$>hviU~7fT;9K_IE{%TR4^vzX=-uCX!M<h7P5
zRT6W)sRQ}zit^@vOuxbvEl5YPgT%hr!f9OqLAeH2l<qVM28gcA<-@Y0LYOfP6%bZ^
z!uff7uc?!fx0I3j=Wa34dE(Djm!SNw+I*V9oB8nd6jltWMV0<_F1ruQmiLd5@`8Jd
z^FmAMfa_ZE8lyC`9_<dWPOX=pjahdzvyos!k(9_<sCVAp$9_fV^31U@JrzsYsJS4}
zU1~=6;OIAB*v+O`P`9>95FNJ!jyH}!t5xMw|B|HT`S%O_c1ZRFz;*f5H)kmh)JuGl
zm}fio(X7iAv02jV*zh~x!TF|Frz9%?UIpeyO-v8#;{T6Iw_cS0W=W|+u~Wt)$NzNP
z-0eE#ca;2mLeNKqlZ_Juv`lBke$wX?P|4$3x-?yxV`l1ofZ5vTf!rPiU~*oHUTVRx
zweG!{h5)NB$!hH;{KtBuUw|awzVS#pP9;auD7f0N&yAwq8NlnGP0Djr9W2>^_9ZTd
zakCNg{Ho50|A6vH9CX#fZM}aG9I$UQlG9a?sAWWlGVLw-_I`EdyN*q8%0+EIcXRt4
znY#vz9;MVm%af8C>m#^#d?|Xc*2COy!si4X8k<gQ?;5Ycj=7vBU&+j2ju1e7$ty6~
zsy)~8#7RQ+Kbqe$I~&m&T1m;2^lkdMFgx=LPj4fz^4(3v-G>?MlQTSfZ!PZMWRb~o
z$P|Co{uJPC7UjnBD0>7+9v%DO3^X{3dwk&pnV<6uIp!m=RzJ;&OJjeN?mPS~M{ASL
zbl4L`h(>!fz{-utr=W!RtDl*bT@JsgGRF^5AObl4;w1)HD%Ie#%l?6;+ENE;4aUyc
zr>7z1#aa<FT?Kg`1bQW+bO}nf2rnF@J>>s{0-<D>BNb)>Z<dCM2mn;-WaOXDYKv^3
zmKztZ4i)yT&~OX}W4C@XL+e2rxv{qDRL<D3v+kH;v<?70W!&32*Yf?03W^0xSc7Oc
zDOJxy8d>&O{?s_m%I*L3NI8T{NL2(AW3b*?t4AI%-^6ShVJSa87-bV4-{OCPCUcVw
z)fd=mRoNOOeJv62R4vi$E}M256G5NL&rYuX?n3YqOvM+n$1pKLTt9|O)4lOB-qHtq
zsd$IvT`R*S<vT3K=;OA8nh3-)pY<2}QR)U?%?Lfdu=tb98!RnXqhn^aSFfx}Ow2%`
z`7_kijZ${y3w!f6HvIdH`g0<1N<UsH=)6IK66gvnqfAO;!Hw^G>xBhP6C`T%y<(A(
z<b9+q0~NM4oB#xNnm5+g{lKK@6pha`u3ij({0lS=NXNnA^B+=7k59>CCdS6W1yG|5
z^<m^PP@DdrlLL+K+cRnKe)f`}jEV=0>f|RAsCt)WC~{_+S*5^bFy-aJp#dUlHp-m=
zQ^%i*T6AvWQ)j}I4S$8wwgN&y)JE==G_^TAuM);M#RX?6&PYw<B~PyVLt!4=gl)z4
zJ1|^Q2IERT<U%zUUYISP?wK-Ex9}=GYra?~zvrS8+Rjjztxpg6xcEg{q-!_>k3O*=
z;cMa51L^S)6-8ovR3ZDPpG=ja6NVlKEyPbTcOP$Nuf-chju2*G!zGoh;!{qpxe1sq
z<w~M``FC~>vT#KdI7B3;2vN-eOSx~mR!dz4Vnm>!;p@`C?vbh385A(VC9-aDe4EaE
z$<KndFY6d5X6uJZw;13P7R{w}D<`Eq#!waCUk8T4efkz(rZ+N>^4NbHzugZ5q~Q(N
z;GJ!F6WKEKVEiqJT)M>)?L6ILo)$z&X1Qt_o_l(}p3OTyokoM4%c{bWe(d3#okNG_
zM;f9>h+{p7LhxT!Frl(D2Yr+1jHk^OAH&cdIgC(lLHi4VB{WK*az(9zC|FV@UyVoF
z#b3TCfc34d1}gmBy$2YG6;dN3OLpHD_(*HwWS5g={BSI6Elw4y8{>!(y8*d>ZM%7?
zWK+qP8-Ne1rFrV<fVhpgbr@m)vR|GiPho>%gaN7BVP;!@GOT+S?ENZkB6b5LC~#3-
zX{gwPf@4$)wL;Kjmf=iBIFFa2k!TFa5{rq`<)bN=)F^x?e*PUa9u_f~8w5@OO!G{x
zVpgtn6P@cj0|=x7!HAR+4m5Js&w$A_81JkUOqzi$rbBZjJ9&1untnx7s2+Nmcd}i%
zKzpMlIzX(SI5W4?s@aWOM&u)E(DsSya@6l>!NBFWOY+i+n~WAe-#ddkZHMdaZQrH=
z!lU1oS;7E&&^erH-M@#axr&L9aq1aHx%&onWw#dVoCS?CU_i3jfx+iD4KTY=DX4<c
zAzB_xgtrZY79Crp`XBbB)YObFFtXq-#-+94ba!g7oO6khM*nK|FPP=j=TrwS`O#ia
zhVusgI%o@Z`@F95&={|>d(A{rVQ_;g<nS>w*xf{hJfFPD$T8Fdz-K_D)lisiJ0ZLT
zU#}fSxqmP$GFT5l1$KHx*})-iQ!damAe+Ck$K3B`8$(#B2bFV6`dvLeyiBIISh}m6
z`ueM!1V0`~ro}~F*}Ze#XEZ&!!C5d@a~75#rBUx0DfT6vDIXvnB++p!Eoo~9+Mc1~
zjER}r=cIZ8XOserlA<N6xndt164O$?^r)UMhPYL#+uv^k_JH6u;6EntutQJXu)0y@
zADH&?63qJVGJ-U5{}U|@K<_M}=mUaTgQU!5h;LsS1exRJHo#DpqT5DYZQU|@%kTRq
z>83f(Ts*sNIugN(9gN8~nHn}+=!*0#IbN^i&!`Kd!;4+9=H(QR?$l#&ll+s+3fbJ_
z-Y(N)z3Q@cWf}?1;5jREs~I(5I9<ma#D-FY$#cTs;^h^;pZwsrlD8>^88k#5u|5Yv
zsXJX3gw+!*hZJZrW5OQ{Gw|&ON@5(ir{AqG7^4la!YWXewuGjssEmBnI=`{mu})s=
zT9`gYd8N>vqGtzhIYTUzJ6+eqa(SNC9v2Qy5xbEz+pjY0vrhIop+LzfzI|@}{R`im
z%NEScs{Y4pVs-QlrI7hS63ooOEqdPtl6k@;)i-s%`JVmgS*ixHWQHd7P`t`kEu7d>
z9G#1v&c}2B?K(zudzpcJJmv-8KVH2=k6-nIL#W0qN4XPzBpL~ZJU0UA2beAYTIReA
zz^1b<@I!I$e^Jt2rJDq2rG{$6`xkH;x({vp5NUR^a<2q=F&Xffdk_ObX3Lt#8qO(m
zO^<=_rIfHK-IXt2B<m0*2+!n1GH`(85*wT&D~f%Y^fJtWz*BWeL5~*p6SN!4y=BA2
zxr3y%pg3vk0GeElr(`g(t*we#i#+6$Roc}T=}|5XhD~SwqE~rSD}c_?dzJb4Y*_<t
z6r{UmfEWFhml;1kpUBlU1bhvKIFHGNm0TAhx>$;Dr631`XoZ&}h->hI9s`GJ+=oy3
z#~Yz+D;u=e0{z#l8t0bwxX~w@fvAAFP?bA`2fV`Ap%o|^Imvx58I*Q!yxI@Zd9D@}
zoiCOP2Vqs{43ah#Yz(&K=Od~(i2LAPbkh3Hj$r^S0^3R})+!97M#=Y9(~W#D9k>CS
z+qB;J{&0qpX6m3%x~8jzj2QQhbg@jNzH%PwpX{@_p@SjNkMdBa;JXwq!&iF0Y*o_s
zK+5+uT(pT5kF}Ww>g1VDsJn?n8gg4z3DP;q#q<nMfpy#-lAizEO&{v)*<}t=yby$`
zZYtR?RkLOXsf}(~pj0%sgfmiZ97okf7P+Iu$z7}J_SDP15Dr~ZkvuxXjt!S0V(F8U
z@-+8|fSOgzmYXAhfs581|5TNBW0Nbl>^oKNva|>~PwyJ-LlttA#rV~nvM~P4oxdVK
z>RoaDRZ&Ccgl;nwmYW%(lHvpneB)mgL1YKk%H7C!P6~mh8e_nufM1nnLgZUxY*S>Y
zyXY7tpJXsj=|trF-A0Mh5v#gNTf~nFr-e5RVbO4HM>wVQR4>#UtUl!WLttwip`Dyq
z=cl5nZG^PfN66XSpT+w7Vr$zts)bQg^V=Whad&~p^NHQZG=4o|rF(WHod{CQI;B`p
zMTA*a6=Xl>eqphf=Xg*WkV>B$*&WNI;)sVr-}S5We5i*slPYtg3W{`=KT#)rc7e)#
z#Uh-~fOpd!J0d4iPPR)=H)%tO@+$odL(D)pLl-!UKZ>V*_&aL=E7gXEmongT8C9;0
z#UYNpL>rGTZ*j%Y12tkM34~&GvT^7%ZSVeJ67qQ?v=4pQ%*q1PNu!j~d9Cg!FPI%-
ztq>PS$;A#HgqjkQ^_kB+FK>)?iyvPiULvs6JR?|qpeo9lmqa%jxWg>5j%?l*TF#`!
z-VT>?Jp2cdq?XDz$pW&nQC@3!&xf*&A~Fr^j*QYx_JrW2`*4~X*NL^Jx^A)xY?W|v
zUw_w?T%luTR_V;%7@TR$bt{pNmGS>n7+DH?BBuN)dO+<=F+HWB4|VvjUUw*B0Ou<+
zmAcaKAPb;(oz6Sm+mtJDdH}f!0tno{46r8aCq8RwkleZJk&1a&ljc_{#sr^VJ7#>x
zBzRu$4(+`9x}^89F&}wQg;GvCmj8}csJW$y?74#UVxbXYx%c?uZ;8hkq9IvPu@AAn
za_2$G0*x$7WTHDn__Z-jEd%{Vcea>2JfDZ?X=r(F^w%8!RH2-j29>;?+X9RMG5-UO
zq9KcJ(v|g^1JNx~@eL{&0KDd1+Q%iL`(f)UvL-nhHsN^ehb&64>0|c9NIU&99pRMw
zHfbwT9j~1?AOaR^Lx`CJ^>7U$H2mgiexP&#uvYWBs6zlS7<ab%h(6p0F54coa}Ldd
zkphiumDsPNqALZ5;M{Na*Ut=aBK)0>k8&u7&dPN_fcH8A4U;dR5v`(QpQbV4^@9sg
zM;92b;7<f!wOQo76jIQIb?Y<reg^yFu~qiHuSUmAb49UaVn<5Ewi0;>(G0Z+l1h!T
z_aEG*`2WAygl%+)*ZNfJ2$_AOb-Mhs7ZRm9PCGRnrpg}!(@=tpaT7~BKxb9rtfUeT
zleY5J5pHwA{}OG&@-znHk&>^CLFm7+OO`u?6!Yo_%kb=@b&p#`l3QmVuNDlbutm5C
zuuOXWPeB1rCuSIs63#e!nuHqC(Sc>Cx~tjPtzSpusM#*V%RN#40SR~?tSj&&im0WF
zbN<hSb>5C<#?DPGoGj{&2L1b}b}-tL+fVWJJ3*G$;*F4c)BRNl89!o>?I3>@rCIoU
z;oJ#zol;;nbaxl#o?V>fy^-VBI(!a##Q8Ir9S0X3>Bv`_s}YmQcl+`CDxb}Q=_Y?u
zrzdNua1V|5?XsJ-kv(q}ehNg@y-f@YZnnK8^gdPkc+kEJ@w@HiqXh3f-1`*D*#+g?
zc`S+;>4YAsrdeE(Ta(~k*LRPdw$A-_R1M<io7O%bs=TK%nkDY>Ea_!#1<=Bt^_F5z
zDT7Tq2|$@$;P&xTps@ox(?4VsK)u#Eg5_w$B$3!`kiZ))7d&}A=FI|f;c%l{2vPSg
zV5m$|ubltCIvKN3OLNI?&)X#MBA#!{ZDb)@<wQ51dJapWhj^jGPcRj*tOPr=<+0`h
zTKC2-X3h1{Jsu;SOva)skcqXa6FrvEL42?zGUsB)I+Lq6Pa7XgrdwTHr8_`*Gf!Je
zjgP_)<h-@#{7h~OSyGZW)pmWbU%t2=6j+o>2q-R3@w=9;-2-(eldTLM2Req_;N@+}
z20)0R>d<xWo~mFpHMjR7Gs`BU@pfuhieef);l`(y=cdd=_v&DRs%)&kruN=SCM9Yy
zV~*lqr%ih%=x|a$z>3rdTYIWj#5zlKx!0TO?G<9lnM4i#^zAA+Vrt0ly(;s80n6B)
z<UByIwL;2u;b}A<T3^*pub7eT0=vmUszj22q7Z}Hw4B+Ari=7}AW?7S<?zhVfuIbv
zgNkxW()1xc7HtEsAkx$AtlC8kJ=Gt1xfeO#TMSARzPD9fR27GSzP{_^eJRLySVhY;
zTMQS~0tw!Nais%qeU#*GhjDj~Z(klc?DxKcUU`nt3zy<U9*T2$Qj%Fsl2-Ns>V3Z`
zjN--`pK2)4lUq$!5B+phi;Y`^+Uj}-^!NW*$yXV@yAS<P<{3JNaR@%eXnKAr%{m_4
z;BoM|yC?>&yi8NL4K7?i0f1PQB%_1Jt~<SYYJlcXpXy}70{+(S;FK10@7y_|Xt&G;
zF&}$i@OXGLhv7(K%HDU5)O|NMJ|Z;rHr~T)L0GK@SS8e%j~%<OC(+jZWH5Mz>Bq}1
zIZX@(G{DGvI_%Y@F>$cYS7&lgv5iaUdxQZI%@Lo}h~9*!9)bcEeMdble|NF>*8plC
z!)Y6he8=)i_0+vMT$k?)!U7yG?HtKxGevA-M`Ao$)J=b$zj`LrVf7Q`D!=|6X8+I1
zq$1ZJ#PTYzv6t1*tuBlv!Va>+KZfWr`V*stqWfmIN}PR?`81my5CI-FekDna_gO(b
z@}Ukj=A}Gt$^F2tWbbSF8*t?;xh5f!y07hatnsn<HI@Gi%}~o$AkL^PVoO3I8pt)k
zg|j`51gtdmlU*&lwY7a0dHDsUK#AMe(<M+Xux3_uQvmvIf;6K&(9vM-fs8^bFLpAH
zEp1|Bv$7CbOGVu%VXv=Cr>T~dzD^tl8g{E@H?LK?x}}DbjSSC}SF&2KJ<;Ex&!|el
zt52mBvU)#M48N3$!Jjy(R_gSmZB5F)VRj@wCRMWu4WG#DS+u7P^Q8qgJRo5q)8>}P
zo!wCNlsfPKu554}W-4`^*yj5CCqk3*Lop5@Nk<a*e!kD9XyDnj(Bytu_HK)cj6qTk
z4b+9bxw$ORTL)MisGRRx@8mQ-#A0~rTRE#<SQ=y9@)G@uz_Xl{fBG}7$Nm7a>Vsm>
zMjq7ti(?0>)#E2Mjb~A}7YV#PwTRCf=1>5jwIUaRGmGG2*NNb3S6&pX;8;Z<#0ygP
zGe=uZ@|pNX%Q|R5rQceXQ&|XfTn|MILUG>YGC5(LngBQ+#*1YNDxr#xg@)}sdMd5>
zjDXGne`2)g*>eJDC54-6YT#5;wLi9M`bGwF+v06$n-qxg;4s%%E}WJQ4OmU0=sl`i
z$Xt^=2Qg_SzbN8NC#51u%1~h*ZFuFnP&V~zCUP%AwrC0$H&y+bVYfU;pjxr+*ZxE&
zyuC4Dt=g3bWW0QWGK~E?LB}&_AZKux@3n!H(-Ls5ViiFm0K~jcFbF>mSRNdn6?Hoh
zxESfKKF}AC^}Mpoa40<Z=U*mVWK9JD8Vp7;FCGO<J6lFQ(Q$*b0CNnut52Vu-cjPi
z*~+g_o6*YG<<Dq4N7f|B1%{@rz{Z^&%b`vJX-O`P0IR2tO&<9lM>;gdTbdK9CM&jD
zO!dgM%s;Tm=8zOI2l+;vxL=A#zxvlB)0*{Se<1HF3MWrgJc%<#)*C_VC6J<bSJQnP
zReyj0i2acmXU2LxX46w^>_ui0X*{Dma5KyDL#!`rT3;UhFX!VL@H#ubtwxwZj>-6~
zlCyp{DP<+=6?EvF;*vHggvtbuH6m>1GBh+Hmo`r7A~h=at{Jt9fInJ-o=X~X^MA?4
zR@vtFFm1A}R=4)iqFE*|mL?z!4|Z}xyojT-P@v#XROzDBphOvUvM;_`f6SbaHzAe*
z$RDuYfR7}W&|@Q&uQ0S@`ciPJ>GQ`SogL|Gvll@E`Qxl_p+r9jvv}t(DR7y8X6K(P
z5EZ=f6uYP0NkX*f23S0dnQQI0wn?vx+qC!z6;VS&x%SFBR)ivwUgUU%G(esT^chx*
zY<IpW1C|efiKQK`Kx4*s-J%1VE*39&t;=|=oaD4+2@P?z;V<8@@x0IqgA(eYs=Zy0
z$`8rL)lHe{L&X4x_5ruNOyFJ)n%O+p-on8T>g*k&4A%1tTjR%L@V3X}lo$+5xZefL
zbXF2W030s#EYP&!I9v#U)~9X<Oba!s`U_Zi4OI=UEdrgUuYI(dUb?_<HDk)O4(e)p
z4TI&SGxJN{VufOJ<y)Kr%!}j$%N#UNyWGe^T+h>~5=kZMr_}$nDm>9|DR!(5G(wAy
zCv}WflQrw9LkiYgbgbV5|2MC0aRf2`&VOf=vvYw2<cmFqCuK|D{5F5o?ce~`P9rhM
zuyi|Z*fHzEkCzwTS2K4m%xg_lo(;plPk&iu%LPOn)<?4){WoNzki}oQ!l)0cK~Z(z
zP$AsTUhPW3$1B?hwFQp2KXs(opw5tyVk#oPmEzX7Vjfk+#+*2;Dl$}LWGUnn!Rr`5
zgCMcuzb2~tc3j<x+MBW{)}Qj?5ReW&mZ+GS|DbStA~dJbVRJahokXmydWlNn5pilz
z2~bMAq;C>+s3bJ=BE1*+KGWE+Q@ywgJyaNCch>0OHbj=pfr%x#qD2{)Tg%0#{it+^
z{f8frvNUxdpSc$#X?7$U-c(Gjdk$E%e@2~V1gN9w@mMLdDhfP@BB2z)7T=n63d$LR
zgs{7cQZP9vr5|#Wa+M-Yr0eQ8<%B@Ow{+sDAPHe6#)HeBX$~sMoIYi*(i!Edxd3`?
z;P_VCHrCui`%CN%M&|A@88vyVE8R%z2iOP09?Ok7!H%2xb2P3m;GcGjhe4|TreGj;
z1AP;JE`LzXu?!M?V<DD+p9qHR2Yb#|Czwj$r~%3d`IJ!%bzp*%%TA-H<2Iq~*oEr9
z7N`gKX-cxGYYanpYyedy4!xaJi;8Zk53wA&fmL`j&nt>9m*)~$B^7;Uw3+Z?>QfX=
z5Ny>fI_ojh8X%C*qCgtdA6)qjBi%aElApuM6~|HfY4&&mCz0Kw*1}6aV*caB%EO_{
z{lhR2oT1RK3hwCev|WK!bTp{><2rYelC~`P5QmVnm94wgGz1A&;sHK@kJqea@5aQv
z8w+|`{J}(6JYg9>*<`=z>W5?vT3Z+W?rEs#o89-Il%%3K7h!SHxpL&P>2Dl21$a(u
z=0F&2ZjMANg;bcZRodV^JP*D)LBzzuX#9{p;P%VXsO}DhX#TfUGK+$MMRTSt7=QAp
zN}PI3m$!+{&G$MUj?P!Kl-goYWJ84(rItHfu5M8u@y^>kZR>|8^I>lA!hx#{ZBk8x
z*tSVp&svxh*;(kMdf_pC^Kgo~zIkC9X8tJ5bYfV<>*EEu17ig@3ly*l>+vulF{tQA
zg@=;z^pTWmpZCy2=&!~3j+A^OGbcDS7m^{dLlS=U!DL(DE+H_qy%1L}Vz~_t(C9_{
z9?3L~e6y^q!r@UwFH~O(H`a^n$tuxII_VT-#CF9)oxtm05^2XA{efeX14}(o4T~uH
zmTsb%d)phu8^oQVjA*9hE|5xkr$SWHiOu}~cPUyptCsTLxhR?4Kgdi)0R^O)Wdu=%
z?Ezl7X5ezoUI&K)MNy5BuV#ks_SPR3#gxi~e$2cmJ3!4K_oXZLb2s%~yK;d)KWtoi
z72?`Q$FocG4*~B|eE3D_kL@>+jN@7G8GZ&w2%|{Uc5s5>Lyo<KW>&{cGYSzzZ+JrH
z6NznztY-I>Xypj~o&Q#j!{ZY`x)$&$Ihyh*(!Ch~Q-v>{V1!{wwA#TqZYC@b?OW;Z
zOX^2|bWqhTr76+Q@mb=^PYG9BW@JlqB-zG%POZX{dcG(;*dWoil;=4Xe}rNdc(qIt
z&I&8u^on9xW&F%$*Y-Euh}IWOMaCh^oD20h;WT~QeSB8=?yB+SlIIJ3puSVeD{QE;
zDN{H=^+75hZ4t~4%7+M;{ed;{1B(=LW2D*0<Z;m1S0-F0@CnY240QUQmDkRPvv{KO
zN-_48c;@3A9V*Y7ZSm@15fZ$Wc9~rI4ODcS6F%|J8_>9hysP5Hf~Ym`$w{S|x9-s=
zLpW3qFfwQ26CI2>T6SrO7MRcx=S-q)w8^3xcZg<+l~_>J{0agGvB^naTVSK;#e)(~
zr69eubzw!ZqX6>|lrZ*a=fn%5IDEaR2)TV2#EK`gEGy%Ot$_2IjB%R^S?zBq%(!hH
zYxX26$4?K6C>|ZSLH(82|4KLbs=-A}UcCAGqg8f-eH7=8t-qA47Q&g7zT`Z0@&xbD
zC=`F1+P=o27ub=%EnW1*)P4+w58BZ1i!f3$$xq4u*b`=tcu~tQ7~yNtUFiW6m;${f
zYQs^z<B)(0Nb-%N`eUa7R4cOqM#IG%U`%WZtbNNVYXvmHDM>L}F-Hr65A@6^!J1!<
zF}B8zKt`Jv$VN+Wzs2{sqOr%}r3z4mFIllZuq8QvAs0SELFihphPAOHA~$qyOz2YS
z=3^M~wv4y2@A%(KTP&v_g=7-HG)-;%Oz3qtfs(GQ>nV>3?Q}E8uy^Ww#l7hDQ>Hm-
zFV)nMh@mv*&*8QfkoCv?kHVNX%)>{M=3!PHpC<pywI``jWJxA>=wW;IhbYf;UWzu<
zw;f-?cN$#ag(PiC4KFgUKF?oISx>}iIA?ts&$gJ$<u*SL>_T9wH1+Vt<j}r{eY{O+
z2)TX~-WyD2q23U|q9YhqA+QIH<~*O@CyR1=QJIg(=D3jpp#;Ak+J@fNw|Ap(7RJQX
zNPCw48JTx~vs4`2;S&W)c_xWslr>HGwXce?s+F(eb{>azb)tl?sUtN2f%YqPI4C7O
z2!<Es0K+8e(g6u0_W+uH(Yofp7voqh2GcW9g-n7%`aZv7;E}n=;lWKTc7CvlxVio<
za_L#9Lm)R4bW{Ol#Ed)<(4M0*ON90A`G(MXO~^H^{97(L(N`Y7Z4xGh^1#DKXh3mw
z?A?mjFxAFTKZ{JMS#{^g#4%rFGtfWR&tHY(a|EZfnnJjm`olda2`7In74v8%pxyu@
zc~5?Oh_d0q59eM@RFm>g0i+OYEU_9^SuPp}g3H{!OP=ASTi8`tjFvi`;hd`E!UW~^
zg9NokNlfkOA&wSZ_y&`iJ883oFYXUbZg~g+E+}ihj=vt6%yvV~H@IUl>p(yx4`qkO
z2W;YOuQZNKvgMSh9N{npA~@NQrJinV>kcnBJ3;mA*EiYq9*$`A$pu<F?wI@A0l|5a
zDKnvkOER(EBeJO-?m#2^e3c~tbu{i<(Q^BqdR|VuxqF1;gYaq>o@G)~2Zj$w&tbx$
z7H41O6{`+w6;%WUDB1{a$O(F5?Z|{{*kmD&XqKtrt=myYkwiZNNt6s(stEt7q!<_6
zZ~U%)f7@(=hW*$^cb-7ZhEt79vr_mqzx@Uo;&q<jZG;&S__?T6`~DF$w4%!4gIvf;
zMs(Cmxf%Nb;~#1rruRFm$3sIvZ%}<#uZ=dPjww7oO4{QH&5b~*#en7pYE9w-M7fjr
z*-brMs)>oPPbd1@Et7sCedl1iGaO<%g^lR;lK}Iyy}L}f;VDDcyvw6ku$n(3?+#w3
zZ?o|}d3Rf@`2IcXof-f)qjfi?K{8X2J92+~h5|+!+<^j5Qka3y=A;J@BxMP4`lV+I
zj`Z{g-_KALa<MaBvKN;ssZ%_;v6?C>An~)#EeiiM=wSmZyL;agUn?-7h(bPhX_bU<
zD&8pBu3ARIC8okGHyg=8Y;<<i=Xq{4FX0`ACo+PoPi2*T(W47T>=siE$kmqu=8E6u
zo#XZxpLHOdkZw2>sS6N={?+Wwx#f>b&)6)Fc>@a%wqszU6D59Lz^3_iIJgHVwf!Je
z%6Z6GdP*(?USF?@r>U;;L*%(xn(uQA^8=u9Qnqk_J2Gcj$;FdiC}1C=tjZ|yDeYkQ
zg9u!h;=q;#EQMn4Zb)st^D;h-x0O67@p%Z^%QmY_J1P3sE>NiUH!illv!|?#d*^vU
zrSGrTl2Dd6+l^tnd!7?WVQFtquCbj=RxB!!bz;eMLlvvt16;3oqyd4A?{g48o()Lq
zDhj{23JG$7o3&L*o?$y><hb)uIWNq+Ij$fDaTxTH*5=x=)U1vSGhF8VKWmZ)dUG6(
zDiE!&^`x(P4y-cmUGwuV<as<lt%y+{vYb3JCW2ekfPub(LYL9Ah6k*38nhx%6v(U;
zwzd&w)%Ku*zR*StU>W09jPP4|FXd~+GxuhZOij2>t#Z+f5Uq;fX1E0Y{ckuK(_!7|
zXFNJJlKpSiN>Bz#>B^sIGV*QybMRR5sz(^A^IL$Nj@Ar)@&O{(rBp?w7U{Wu$&ki3
z9)6PJTfZBGT9!&MP1j45H>H{*l0GpGqLj-EQ$M{`{KbO|VA#u=Aas0V;JHfwuhyoD
zihP-&SHEJgJ4|Bh^xwwmX&@AAF1o~WOvcUA)`W5vcX4RGir%dD36`}qbuVIxm_`LL
znM%J^&yxh^hi+#&_JZ42mR1Aq%(MJmg+!mCpK06c+PH`xWLuX5mW$k72G%-Pl%BkU
z5QywdUvWXCL%eMya^H7cG*RRsolxtX@1k+DnGv0TtQasoG)Oad?0@FzM?8{Pj;-)D
zbXAB1!6L1v99HN{h}Rz9CD%i$8i)+$)9)n6mLaHRUa{s^F92F?2D5a^pXo54E#isS
zoY`Hwe8q$_i_W%>z<loN;5NengmUI&G!6KWNtufev<Pnv)()i{Oilvh?iJ5<UWLQt
zfr7x4PWFtbt6+mLMZI;~+xfjf#!eY3EZIXj11%|~C)V_oKKrqGZpxe&sS(-+Vu}1t
zyoc>Zc}=K3$7MS$ne|dDHNWoM#j6V=Mk?R}mpJw2Rmqz{!&A1aL092Rri#F2YNtMK
zAm`4+I95~VotI@d_8VM6*YcffzxjyOT%A2gY7pvuH1YA~JHR9xu<vDZjKNZe)_Gl$
z0g4f2OqNTulve<?&H(x{gZwWF_pJT}AErccIpoG2^~vK+TRcz-R58rAo&wm7XBQzL
zp>fQxd`kb5ItM`8=NdLe>g8QXvu7mKl><eos9wehr1C|R-#C@lN<6<RaD{56IGU&P
z2N(CsT8f4k^ZlIgyOgC=Mwc+vH16C2n~s&*waX!x&!x8YZ~x~H{opNINV?XU!hA?}
zw)dZ!#2Ts#i3`6@*GHsXO;<R^K1S|40ZFo<VzJKv{sZux49wY$wZ7rijWgo4aV0B`
zE0cn3jrjUw0phdY_g;^y_#LM(3(O;JMcZVM(2gmdOY-{+SC(d}dZCcnO(h*dQ&6Pu
z5UU6Fc+0(?WC!-ddT0tfPE9aK%5)UVF^35=!GJh>41!?_E4PTx=@dqe&U758H#<AQ
z*69+J*c}J<2gbOnI8vaLZRSD5?zFDCcZEnZv=91=yYlJ}|BCcp4uc*&H{k8I@Y^8l
zx&_LHJ7s*+8pH!nPW}jY2@{fhKXZ`TuISs+$X2{&)}Igwp$7(}@g<W(E*8V}E^RF|
zHA`Aq(OgtCMQd3er_)qiAoI_Cd2dkUi2%;20|fMu<t`NNwx1uF92_r>6~X)~)i5N!
zkR_366nKf4G_Yu3I<F_sTO$q;BmM`*3=fT5YW~H++|8k#s_~j8aA;%Ub{fd2zaFU0
z(IdIi4)JayO>oG#C*<-4z=#h(=@mRUpFlMJoXuPsKAd-ooYkA1DRYBw<A8VvmUq7N
z0Ma<K1)wkyC;}fj@<!;a%nqxpL{@ZGBZ~j{s(x=lv4&qJw%ZO9cl^!j%(-{X^v(U5
zCuo7zeV6I281!}TPD!!x0E*gkXX$IAz(6t1$B%Pr7?B$rUTpXy^W)5u!0W0R+u!ut
z1zj9x!&G&{3h7~FjJDKFr)5t9E5~d|0g{_ttd<u)-Z+yKk4?N^b*m;HoQiXcnQSfJ
zWG%p$RP!DqMoTD_*!=&6Jyq4g9bGhmr2-~BH=%MpC1<E#bF!l~TBt(HH?b4mPpHMS
zoR;So=OUXaAVeyg6+@2w`<!fjqZdmMxfyXA^!a@gm9Q<pLA*RXG+j88kwN;hZAfiw
zK-{G|ZUt25^_{ceAaHTjSp*W(5883C`}+Nj8~5+JjEepei4j)t>l9Z7sIT>Qlhvoq
zwx;bOy0O1&eNU!%+m=4i%v&;IGuaa@Nweac={iy6Nhq)T&D0BOFUIu+q3g;8%URbm
zGbDM593qxjGwzGL@tKI59CZAAt*Ca9cyr5GFmt%n=fk)bswG5oAw0QGay>i=>eS2Y
zLG7xhgWNK1s$1yy!Dafy?n(FnA4J8+Xn_@LIlN=zqDJ2?av)yMz|)V5d1HMb(Nm@I
z%jOPmeunHnK#&;K@;_?!a$o;lxpcUQ6d1+DQymM+C^Tv)u>qFV!MmObd6_14cKfNX
zU05l%BAEEgVhiW3*PW{K`US>`_le<7SC(%I`n36P0eZLpN@9(=Nu=nRr=7$s3cNRR
zf=`z@VLZbsX@ii!&Fk5qF1=I?f~a5P5IFXw0Jqhm)rpl?Hx$i=#z%L<5eE|F+^;(f
zlg_asB1QaP1meA`_~_e`c{2S==b1Xi($7wUxZ(7=5Qq9ar0^pv0gP*H;)o=#n`Be<
z6PFcKq-qO65b2!PUOsfx1`JR~z05jus;VRKx7HNaYCmZQDlAljRHMMfE(7@b3kguh
z9*h71A?T!XFMxkNzVrw-i?PC~xiEukNSNTQo!=h1-d(xL!(bn)7fTAUFg#;ArT5|w
z1AV@+ADq&_>+41%ODq5y6grV~0vQG)e+NXIv`O>o^_Jxwx>C79l}QqcXkq2_WQ^g)
z?LnbjCqA&N7+GML^XwHlnI(nB%d1;hN`AECsN>c;T~S|`s)G)P4?|x$?s*A2<Z$s@
zB;=|C3l%7=u7#QrfJFS0w2*VK4zX6l=rNPL&1LbLjAnNjdxjq&YBK%QKadOtqgVPa
z{~qA-j}IpgsweLq%>#W~_FzP!Ef^j#pw}+nr;f3WlZ+Cp_=&I5e2~=h8`3zfUaxl%
zo8{rxmb9fKFSx`b$1xiVI?_||8BH)g2>^a^Rc7Qg;iNCzy=;Gniw8g%3yodUw-flE
zLQkRDN2r#e$;qxj<Xp&J-&bC_q}{p|?Vt>VBh(8@LbOhFzak*qxn&BlN7|2$g*HBt
zzZ=M~ORxbqq9_IzGEWcMVzCSl>-vf_hN*sKh}-OzJ$bPD05c8)EuYoYXAQ!iD}8)|
zA3AV9cb>*~?`8DoiGB7XI)1V?6^W$rcE<CUGH$xk3>YlKF|chZ;w|AfwoLaPiC_Yb
z+v}P(O=1A#6#*-+>KEZ5Vn<n~N$xSxcIiYd=vs8pgmu*juDkh=CrY52Mh5(GAUvXC
z2Ai?RGEusq@jz-+?K(l-KubQN<83-)V>2pRZ=#uHl~+1{i*b$G#gaC_pI71zrQ+jA
zRYXi!?yiHCb;X%vaC(BXn_C^Ed52BEJsl-5+O6BSo-+SY-&&KP)Fd$o)zbSxBFcn9
zE7P|zTIgihqHxFdC7*QCp&eu<%o@sJ473^cp;%13`9t#2wNshg%s85&BHrCcE-za=
z2Sl5DY8h?wKO>A^)s!S}77JoD^~@QMUVcnL0zn=o0OstT)}stV?!c+U;^BIDrb)OX
zJ(`}tK1buEHE!GS^KeY%J58NeBX4>QQWfjW*e$x3Ts1xvIO}L(#>U}RFa-%}Ir|`Y
z>d9<^u(JLE$*h#9+g?HLyb)bnX~qM%&173=aN}H29coqn|NM8_04ij|P@m|7oFEnQ
zy(+Of)D|7fr=$hN8G9tv45eB?IFiF(5OfkmrmJyhiqcmq{`3D4Le4*rQ^iFv68$D&
z`Ln0HZ_h2(U%JDPRkd38)%qX=+Lto7mzYwU`kj4YTJBWz8q#g|qax+wMP*a2?Il(=
zMt{8Lhr>7y+4BzbSUBfcxy5s#{x%V~FN@?yV4LtGbj6ZjAP!Vb4#&4oz64N2SIjm#
zqovY@8(+OWIC%iYD#$yd2P914V?S=;)c*B`{o4^C5)IdGP-EMB9wfM(4|DiPRHucB
z4fE@a(y%s&SGx!^5s?T0bZD7Hm%_%jq;g#nrdD3=o?c@cY%b2oLyw7vcC8*W<9!_o
z!%og$%j?+Jp}O~1fE8Iob#LjGat5zJVc_){06T^`F(H6&7!lzNdoJ`zK?0%WYO#8N
zbd0f0I1|bQ^`6w?QP%9j!d~ZykU0MJiC)#_AhX-`!0DwOcWXz`gR`mCcEr89v&>k2
z^TqWbqml-%J$LJ>0SqHd*~YO*SP;8uEY5DIbsxJnk2?n^DhS>o>L?R^=ZUq*wmNN)
zkI_LK`PM^mFHeX)@l#qO=~<rLQ@`@4XK$cWrp|?NghFcStP9S4T^vPtdvZ=ty|m}i
zq&OjiWjJ;NRIA0EExYLYE~fTu^r2UKi^UF_+rE6B$0A@<oEh3bH&w!3&yQoHcTpN3
zTrt8W4MpFkz1rnunPvW0zcPkIk(^+6;7Gq9X3W;|%Dl5t;NO<)BLJ6~w1;m7T1@1t
z4Izy!@*Ra-zR=AAV#|=fDgy~zoJ4xrA`0bbsNQT_M3-H~3r*^$i+-H-N$ZgV<ybUW
zzu=kkNcdfadJgmbX6HEoK`s&D%avY&1igweZGG4M;L+nrsR>1&&VDyhPq|A8(N>7Z
zW50@&K@r7|63}H<+1i&l`0!lH*}4#gCN8<?@<@(JD_k2KK*Lk9H!y-Z_txOTHk1PG
z?&T!3q7|R_WA~&g1^>?vc#X(Tfn9_n-*nzh78Yyvuxr*dsqXQvt5e;}1-+oGLF&Ax
zH%0k+jNl>X!K}r+hOL28zIDF6{dsK^gnbTZ?*?jW23;OWYDbDa%|yxZX@C;zY3PbW
zsX_bo<5z6jJF&<(nVB_?+YbJ`^?3<GPO?@>{<(cE{A}OloeHN;`7N02a8mEuvK#L}
zza|Dl>yCDfw$X`-RD01F%KXCI{!Gv&5lt$ZWrU1UcgnEnR$5kVLRwSYL)$;bY={N)
zi<6;h^O<%{Zg1#(@yI~jY1!~weCI@V`_1*e-digm%(`@;Bf=x9R<tP&hBWNfN(erK
zl~3MisIA}3;)lg3zw7(TQD>`~=@237;-gvzZ+k*V_`nue=46%?FbwkO-5%NqxZ_y~
zJua{H)C7-!?O7MpKV~NAy<Z#N!?3mi>yJe6VO(0d+sK@;0OjbP&)730E*9_^+mwU)
z{lLvHe!?5eqV}H!y(h1qY(v<;`G?^^Z2=yj#pYy(jB2=JW1CX<V!87P2_}kqP2F*!
zz>s&qXp96LjcD@U=w8F7*>eOZP@8Y?i}?O!cu&woQ`6WHCO~+zUI09VS8xlbx+uqR
zxiUi9TktTH3V7w}*`?N8p_M<T=1ZwDeAnu>3_ji#G{2iBB+|rqfJDAI6c-VH(oewT
z<?^o8uRl;^(tdQBaRz0euomxkIo}q@v8}qayT0lCp4@|IY-yN2TGX2x7Z2Gtdy6Mj
zZWQ($b~#aV1nnC_p8vPKmsA>(<L(^rcKO^%_5Yq>)ocl6|L3_C7=*2|eWM%QI4>`V
z^HNX;f+eD%WC=a{?$NGT7(RJ#+-FG<Wr)Z%YLAV<CWU<b2DFXQfiol19!@Ob<Cz}+
zG_k08m}0Vo&&??v+-yt~`jd%6%#E!u`ky%OfZPolp$sET9G?PWGJjXHn0fS^>q`~s
zq@KSkckEqxE5$4cMaL{KJ!LXI$y7z^^g)UA9*ZB|`q;!*uP$Z)+9(`i6V=g;OSLEs
z+M%Rx0#i!q1lCRL=UDh^x{kkUT&nGrHzhAfIw8}L(Xljlp5znVf%#C=L|tO)=YjKF
z^GQ@S)onS$7pL8^OOxty91%RW_Uc@>r?Juhdqt@_(LoubltGf>)-}H=!(Xd0Soicb
z&=(KwP){}UV~<=uEq@^Q0lOULp^{??i(lMwTgowSYMmrKBjJVCdv+>dx{%HarDT12
zQ^K=Y#C_lYw^nOnlXrWpC7Q?o{mMUm{;Uchl201kv<D0SKKz_mCy}KgO*@K&EHK(7
z(R&sw&4}PfVH3<T8L~Uvbo))FADdSDHPGwrOz%FRV>#lOD;$qM*G44NDkA<vCYpSI
z&>^b?<$3!O^IX#DIUBW;I_jN^_e{bp_$IEu7N^$cYr*aa5nh6gIl8-Dao2nYi-Ck8
z`XrocECXq!jnQu_<-`D`-#QhQ1n!4tC2xCicCs~qha;Uxn4>Js|4B?L`nraqA1VGc
zer*G3&~zb4y$0x={(z}Qr&RXwl9C+>G%|^6vN4t#?!HtOnW;cJHhws|y-cu+8VNHU
z=V3qFWcAsWWfeEg^3<S7?(D(LSf+EtkH)s2Cizig`Fu+L3i9xtHWSxIhT~|2QkSn@
zmJ9B7FH_N+=@Xx!EL!LACh5J7{DI}q<({$qFPKof^kQ<B;W<~wkk|x+zbHG(Rl)&C
zq9b1t*F5k$Z+7f4mfeqE!djfE6j0?nS?0BE72zmxS)TZIkzGE>=4n>}R-otbxo}#f
z5r7xv4Ya^ALobEJ!YZxrkA_mC)^O6PSyU#dR+aIlbfC(w4u*X|03-^NAP1A*4l!Co
z&w=Ll1dD>ajy4AiE2?hWyWy9EU)P@6^R&GR^Nv0yHxysNr!pFVu*z_t^KzNfrt5^$
z&(tM#Mgd6Ekwfy1mtq_>gc?ix;ju;qSYGR~MjP)M>y7GSt7xDu+5cT|66rjXNRPb3
zoErgxE7v7)5uC_J_)jx#X4S;R4yd2#;fbRogBb0)?Nr?8h`s2UpS<w8nNenr|BoY0
z-i?-%-M=;fQI0IsGIrCcc@nh8OI%tG$eaGErVt97=7@hCRFwxm#-(G}%L>h*69UZX
z9CyzV^>Ma5#IBA9H6oe2mEA$Rs&CKfIT3LMwRoZCjpB8BzTx_@R<z&OF`(T)`5q;w
zg}=mQUyMms7steq{#qe^JEe&DSSy5xsNsV!epZclXmve;;TB^+P^6m6rm;aZ@HOi!
z{jU47&GO4XC*S9g+n36-ZB|7sG>1}~AB%v@ej5;Zf!UdJoW)+QZL+L+3`c@M<*lv%
zRDLcXWAF*_;?Q+uV`Vjc3w5<<;WHJxoR3eL;Rs_tLGG>9n3F}jySOrzpygajk6|?u
zQ{0)pFR@z~Di;~VK>h{K5|cy+@vTf(lSFrj$XIKUU{n>(oomikej?qtA=_9+9TtBA
zEDq0S3VRC4q2D1Z&#t)0ZUmc7brc&(%6kH2BPsdX2~IpmO#0gAq&&o5;yL1ki_cHp
zJHW$Tn(}-+cnd709jj2#)9~|l*KJGe6p{LD@(CGd|H@ZR@7_jOW+^R4Pl=j%{``vM
z8h^<yFoefz_V2Ye)#wtE_xFzh<;puxr*Y}&aNL&&TjiGh&rs12N&8no*ZF(8wzXdK
z^*%st_mFu&EpN2FYH$rZt)nh};RRX;GD(TRSqeaW+&T8#F)3D~$lxi_#{MsNXm&%^
zH5l|<wgO+carrc(PR^d^7iTnVnja+iG^HYNeZtebKLYD0G|V3`CQ2C$aN%#k;9{5A
zL)BS~t>xWwfbyi>WQO)~yn|r{R}cyi3C^9C*QiKE+rSExKw3y!3a$WkDYV0Jii1eK
z94$7XP+~eZ)b@)B7F9@n`k29>svr?zGTf9$pRE;&{i0Rh#YpYxbNlYs(wHsMECDr$
z)`N`Le8Y@xgk7-;FCl`}K)-dtdbJ34G>Mnsw8q0T!Qaj(uk(wXg^qk@!gmh`a^<?%
zQuAFXDcFz`LW!P!@j|E2>Oq=j>uoC1hAoVg>>kw@JPVhWYZ;pi?Lm{-u9g5wkD8o%
zf9lJ4NrR~{kJe-`-Nz~cF#>Tu{lCj>T#P_AYeQmnN_01nNCg!_d>c*AshB}mrZ7a1
zzB!mmdq})VO;Mqb9x6j7PQ4y-Yn)7E)*?+e+jw0Uo*1zrDxejaH0X=_Zg=mGA?C&i
zDG~zVyEdR20&<&w0z1rb3%e*hR>{tC%gv<}iC`9RTs{gpOcd6P4>Pb?N)~zI338)@
zLM>Nfdx)St;M<Oi3P-?4juJTIH#1v*L{ma4{>ABGEqhs(SF6>?>4hv?OWJd)hU<1~
zOWDR=X4^%e=dl3jM=YN-vbz{xdtBV1;D(~cl1c9~J0Zxt#dNe7^uy>o+tmSBza>XW
z^i6(JMm)IvspJ`cnGfI1j1&?qPgi-1S7x0szYMG<3zSp++U_&5FwP>UH?A!S)7LiP
z9N~NrJvaxXy3`w=(olMF+!-Ttlnl`WwohujQ{Nd(w%Oadn$B9aQ}MQmcx$Hb$tQit
zmRg|QGbWjFhz}Ta(cJ&9CRUjbhBY_HX7iBjlVz04vf6;2PFr9DjG#o(8nipSx97m;
z9nXYp?B6+W3J@7Ks|8pX^_>L@O22RN@Ro(v+Lm10Ea0x(XPf($pcX0pH!2|TjGO5Y
zp}o${1_$E4Ge;4dHvxb%G+;d4*9CS>^&7N=vcy))gTy>tGlM=b3<8(5=`1eud_kcj
zN1t%ql1T0YFj4qg`cJ1#47J%`nJqucRzgX&ko8_!F2EzY^8jI*1(x<%qs-xqs8k+Q
z##jZ0CQ}-2!~@TA@j?<z>NPaj&%p!fvmR2@_gLA{)+`-vys!3k+wygO-K#jk$Wo0^
zEZYD8AGWKkb)3kWHApP3L56D-J9A^{)BB;Hq|ac(s%vs(fU#cd_?{CzK|hErHcHrx
z#Az2G`PLkpXtNo+RfJG?Bn?gBajXw7gEQ=I4KXMSvfBIjbJWD?*G@RRd!KG8wpyF<
zUbH7<K)Ipke(%JC;N*AIPm5`pSpqRpn2Kqo#EX3L#NtuM+Hj<GbQ|NCBk8|5+sjue
zPsHYy`+aTxKs*Z8JT<~;f__^E`S&Z-(#PA-i&Bw<9QoLfHC%SzI_Rzu0A>eB;9#i_
z?D)KF3y30*mSUx@#M`>Gjq4Od$}OVnKp}}H5$z1$11Phac<0Jua(Rc_84ew-7PSG$
znxP*Le%$++emtkoMQgw=f5>hB!jDq;LBQ4dd%7ST<AZDkBpvvZPon=ygTWnk-K&Li
zb@^T6Cp(mkS|N@b4gVozEgITN@oDY*tJ>jA7Qdk`1zaQ#WB%Ha*@?K6C3)k*{J<eV
zvw989A)~lGOqvyUktiSGnZfTI9>luz84b#odLzLiXRaS1!Cih)4ePuLsm_N0%y6jK
zTpBPuJC>4@K6sQS5#b`sk|KDU0|@^DrWWufMfvpBn{s#$ZutPa#vv^)pvNUp8Lq@y
z%Nf>d6Y665JSsC%Gvy}QsXhn$K3Xe)_7A<h0%{3hk$%ROdo9;EQxQDkF)dU_KmVM0
zsS>p$`OR@l-0`nYJvM?SYoa!7bX3IwcCv6_c_OeqBf=E_%sQ~_aV9*la{=!zWL1;v
z3kPPzT|~2$J2JeJCx6L(l^)jQ{2FP1%BcIl2U2%ox}qTGm+C&zawV$HDy=QKORk%Y
z&6}KVl8?AH>qW7Rvmp2G<YCWcF;eF81>$ON@NtMKWMXA#8CSwi1N<Sz7#EOZDLzUa
z`2imkXkQD5oE2~aBToR?y%dDSOEjC%yqr!wHzUq6SBAk<-nZ1Z4r)c6Ox+wvKU_N)
zF9rDpLTM+1ad&*D!h}{;D(TR*p8o{@8-R8kR(l^?N+rTtt6qAskj??~#!D(r0}G+j
zjG`OTolVqqt=s5pgbyr8?3}h<W>za@ds-PXlVI_BJpME4r!2e8wpE@@jbe`5JYm%V
z$Tw+(9<p2d<tT}D`V3DjzchIyf5T@Fe|P$^bj-@%eH3TM-vRG}oSgNezu#rLii5H~
zIN?lkn;^>K%$U^h+A)VKflq92Sj`3Y^=ZMwqMN;xU4iAe06Rd$zhH-pMIYBG?vL9$
zw0P&K?*up?Uw)fD{M*Ph3gzj%;dy6$O-jsgO`?$|HPzjSV(ygTu#V<UK7o;}f<!b@
z@uiF@j`uy=hm6I7L(c5LrUdB@jEdQMLpm>DY=mkVkvi@puFX5Ax7qh3DjpsUNQoo1
zoq%(;SHeyc5%ksUzM6+4q+&C$LLk3-0J~$fgp^t}&vdg)6nMkF>4&l`YELK%tQQZ(
zR68$RjT<BHw6`DM(&RktBbM4ND^otZ1&>HZbrvGX4Ih`tVR23Slp8k7C>!9Ki5)^2
zrBS3VAxkRq-}=naX+G(EFJMcni}0tEX(M>jBTSPAlFC}W|HDq^`$xj#-Igx5wB^Lm
z^AoR}7u#})MkaU8;__At;cyejV%fU_H{J;aP1tn#?rJDX%v5oWY4m%mjh;^>rQ~T^
z5L31)hcP_&g-+TtsCd%m)$PLH-PFQ@G~%j=-cQdEo+k2e4PJRZx9|oS&)l7>H*wsB
zM4R3aOAer7ULFi%A|d&6Tsy$_rL2AK<t?<3!Gi3gc^F433Fz$88?sz1q@x%S1J6b3
zezSY>koC0lK}-3Ci1<&YQOYc@1{IJM=<iDx&b+96At3^oc%$~%&&l+=rgMvU0E+9X
ze3gRpxXRZfyL#k=(z66SMr(Xf;I<cQgyVGCKIcyCuoY*Cxv<pR3hC+#L$E?p#Gfuk
zSY^t2`Re2I&#fxF<R5e$T_)Xo0SWeEA{$YnIoUYq?riDI658rfIxCFS5e5Ee{I9G5
z=&!{OQcZ`I-p0gflyKZT`Rn}6%TV*)X`tVayLac|Rv_PUQ7V=bB`KU&C9yZ&>tX_T
zDs_GEMb5sv{Q2U_oHSxCZLvFjK%~#ZnTJvUfp+2qg6)CmCF`}aBTPoDtl`LQUCD0i
zjTE0kwOh7LujeWO4H<IB@&69@i>62d>nx4cK;+&Jv}Qa*p%HJ!*NpP@q-+l?hXR6n
zl6-;QIjtum{gWQHND~c|VMJjV#U1(7bZLl!c+gs_ip;q(CMf(kP5Usg3p3n{I#*wP
zy=Q+gZya_2iTBONs!pnV0mLr^(#I-jpo3?BzOSzn?qxG4G&Oj^Fvf{}{gm_+7H~p;
z^xLjS6TLXQ<_m3<$9V#B;qRZA-jlYY%g}jvoIF9hC&cD_PD7*cT4-MKYJpFgcN5?*
zg1uWR6qz!0zDO3sad@v=3V9`rlF8jfQy(pZPW9J5N69h~PS@yPfMF~nwL_vW9#|+3
z<y!mA(98yP0F;+2pEdX`agrlSliqE@QuuWMn=H87|KhP`OtHD#&h=tt??i?WR+*^(
z3L}R$JrAgS=2U@I;cbhxhlUjvr`ME0kqF@O(A7eX3+I!a;35=W&94kp`2u9ri6_lQ
z!TAMn;(tfYR8M>`UjKD{ne`O_dF_iU;mHuUbI9=Up!7-CeiTyT3<0uZ0r~iKcPny@
zce_Ao$NXk8Y&WBuO1q0KY5cWLa$kFA{gPtt@(q&`V4>IIFS4f-gOYWtcXS%k-?MQd
z5%9@<1H+1fQvG9W&icXk8^4*y_!SmG8DNLuDJlRIPM2s@`vsEKZ<=4n7-J}bk)v;b
z7vY>T)IKIpvU>VL<6x|Z_tsz-DgxESgefRMUUOA<RPC77Qo}l`DL-sbQkQ9Q$j5Yu
zOQGiniKnS3t*~GE23n3gEUdnHr3UEx&0S})zKT%O(PdiaAr5Bvp{8R_!n3(NOMM~d
zftK@!J~^t3q5Tzq=kUO(d1Y5pavWjRCmV0w?V~ReD>prwD3S_qS;qFQNk=L6j+q#i
zmH#4U4ah3-^pN-Lnc~ZK)grBN5LS7b@zPYM`0mqTKmyPiQl6Vrx?#Hj9&PMroH3z|
zETb#V)eYdIM=WZa0)cJe;2XNUrGH?#&ES=Y86Dl~wBz&yWS6@$+(A{V9(Nr^L^9Q+
zQcv9te_w0rC5XQ@!T`e<xophG=aSls7x`v3YiYj5nOVHR-L)}rw`C&tMw1UszDvTI
zooU>Dd{H({ru}N;^^NXAWUs~Ew<e0)4J{&`<nf{6mAVof{W%I32T>hbZ4VgCmY?@a
z=^sOv`oef~TP&phKPlU(bZb>0u#1;virts!LEe?4W}V7YWdx<kX^z$Jo@8~=Zy5TT
zy};eBE+YG)zTI@JiU-rwNT0=qoe2L<Susnvdu$oka>ge6{5edDd%<7<ObDp@Cj-MJ
zzjqZGoh%Sv95+abkx%gJ1xqK^GwN}9Qm-&A)sGkdSSr#1zG2&Ydjm^Rb{}8OmTDPE
zqu160utsmxA(t~jaK{j6`~}E%wIPX8DdY_58S&pO%PWy)<a=Mwp8tB}ae`QdPJHg@
z=uDUjZ!`VoH$6?&{C|mGN|K|+8KwF!zxf|9)>Jcq_q!(VynAD~o57nud-8a)eFrxO
zl?`g5lEdAj&W<_<-60HLgidQOnj^w{B$MtlL9Y{RJbM;}OzT0Prk@H1(NPVix$Re4
zim{7eM`*UgKWmSTP7YF}R>lIR+z?pr(VFeOyoK4;W1`L##*joQ&D~-Q^j`}-r~{}(
zSJ5#NfwJs{_OMU-Y`EgCvJN7riaOU^O=W8Wj<$a`%vee;H!$lIUBtH)LY>8`>G0c)
zXYPnoVdNq18f!dT^@)#VNC68Fmr|U%xW8F&(PuvpVp9~FC3{q(#JT0iy9Y(Fbmf;C
zBE!#N8Qy?$CDh5TcottAfD0X$%k)K$-V)Wysf5Jbld4D6Bg1_^DP8Dv+?ATp@D}bK
zP*o2eqRG}#onO?WJ9O2U!DI(zExRg2bC?6Tm0^NDK?E6vBOH5}u7w;4FwT+j=vwJg
zE8MOT2=S38>Obhcj}v)^dhT6A%E04HnI(`fZYgg;GP;_93t>5u<dK*suz%}Wx1i9)
zO5wKUjT=j@b$?v^UZn~FZfC`-1~!0tI&MtkQ{vbMrCL@p9m{`Kz|RPmy*(L&P1+x>
z84_NZH1e31sw*h3;BIwxFO{BM5TZpvVr3o-sr$qymDkIW;s#9;;b=<7gt|fe4Szp*
zC*~VV0-|#{!T+5uPg$V33H{Oo2?(P30mW)>V9dFiqKaCE7Y3-kb#uf}nJ=&72;W^%
zIN0+@vsmZ%sJz=~={Y`u_K&<h@b1Mxb!WrW$Ck7l$B|KY3Ie7FfYl0o=?$PqKZ$yu
z`Gb*+S+5up60Li*if<sW-_M%^&)_oZyh=4gkSBw?{OqZoIoRI831@WTN6p<;PcD|a
zo2K|07He||V!vm%_S7$fS1?6#C=u9IDEs1*MH`S0cKm0|0=JIYjt0cYuJO($#>tn3
zkcCsN>@lvYsAMWNGmvRrUWrzS9gY^j0+3shSfwEO=&(c!b49n1la6Ee-?%Q)u1p%8
zNz;Je=0`mMTj#N6id^zy6V$9l{qi85ljdqP(4u22jOExd!LPg;s$^iNQG6mP5;N}h
zC=37Z{b>cJ{}@M<&pa5|(h5kuJb6wT9fWU$mtDhNYlU9ZC&R~n%`4gfV*Uxq(cSOm
zwryZ4p7jdoGtyYL+IbG0<q5}~!|?O*6Mr=K*K-;-t`xbBY1mwy$SSMnW??qcZ%J<$
z8X)HMTmkGCsA)lil=VGDYao$<_AXv+Tf_6GM&N58_F%{c*?ryMI8b$H2&#7d74ad-
zBTTnvyBhXZ4nvA#Je|T4BxpfLelwNp>!CTLTy{1ww`J~8>U;Jx9^qhpTX7wG6MQzl
zT-qBj;%>e)S>L3^u@)eB>KQhaNL5*p3JTE<t~9NTftGkMOcKi(hjLhooy+!DZ#fA}
zWoDDp-Lz@*ACLW;n=>G!>kP_FEDR^AG_pYAFL42UeO;qklNMeuQXPP3=pIoWGPzTS
z5e%Z*VJQVAjU_#-W&us`onDL305U=!z^2mn6WUNk+~HKkV>i*QkC6-%@{`qV1Av?b
z??L`&Y>1i0`E!in<kVq7;@;J98DkzyU*8pKlXgV)<_nbXKI`L2_po@1K>`e13ifa@
zh#VghKAeFUOL_ELKB~^au%@ahmuU;KRpv=8Y|(#EzxcM#&2#2xx>P}`MY5rAHVV<0
zpfS=RACG`;+z>k_l(g1U=iC6JU{9|t3rxnWubd5yjY!PrF%i_D-><$DluaHkYvztY
z80yG->N(2!3~T=e?oU>QYW3NJvwQ<tsN5YK4&E!q4HV%_9BB-4cc?&;&-#lK5F&cI
z;)1TaeQg`yIdaHtPA{3<GVy<od=H=<;UEm;a({jypp&vvwZh>}9fZ8TLM2+(H0IK@
zQ>-3um{@>+(-(<pY=F4_J8E!bCQTt?6D_tgYVMLP1VB@qCezxgps47^btbbm>=;^I
znf5S(MiMXIZ4hbM35a8dj86`@3gbTS+KiGNk{uJuz>SijDKuw$9?Hzg-za##J8`|Q
zHq6+?QR5S7JQ29VC8w<?`>n$D<ww>>xuEqUodym|$08fm6|H7E1S<(;yINx;hI;a6
zrSBpruY@U_o}@rl3ke*&4w6BxRcmLIjl#NOx`%(Alxo5_I{j5vSns;)j`nd^g)oP;
zi}Rtrg5bjtB<(?VJv(QWgqIFz_c?;s3;UsFy7Nyh)wNfkc-IW%PduWXwSV6nRPWq!
z<CW@{Oi|+({v#s_GYj~5f`r{5U+P^$FIzR}NJIZ)J^(HIu5HX#`OA#KZL8olXdq=<
zZt7Qny6QP}=<|(kgZ0L<?C>nE0Cs^XE``pjPf`=83??=F1<s-_5e)_Dh0N%r=A~!9
z66Zx%cBQ?Yrw>4cc3c!bwLZA{uEL8ESc-;(#I3t=FBfJVa7*CRrz%wg>Uwf_Zj2wH
zLYwfO<~u17B4o=HlkqGtWLzxO&bucVcIS%$_zdU?^o*^-4oGCBC?Eo@B!D*RRT6g6
z`Pfa3pm1S$)&4)BbD>G2u*~Q0sWf9VvELB-#9Z)w%Sd4q&fw^GRh-G5TI=JLYp?-?
zduuCx2`Hou&McWwMjaafrlKm{TC}Ta>eQ<^LLO8&&}Vf?Wy3t<%qRLB2x`+!CIRf5
z=6i+%BB%)-z}7;JkuV{{XZhpbNc=r^jCPHv97PvR7#ln~9V|WVMbUL|Xy{(EpbH_6
zz4vK@fsBrNxAr6;)7QyoH+>O96pnYC&f@lZSC*lnjsgnVUW*Z8;5Wto_9*tE$+qoq
z)sDXECBzP=9<oW_QPJFrMrM6v=i%aRXyuPSb<%5Cx2_{zS2^xGSgqrk3dL)jeI51-
zBB)D2T9y4Xl+EsB3vxgB^Q~=G+l6SHcYo(6LnEYWS3aG@eOGueYyWf^jm;ozd=5s#
z-$z0DJef3J*^F+1r|LfUByxRsQWE;{vwH^9;4+2h>%Z=00>jhdQlIi^aR!DIE*aTs
z#xu5Btta3?CIH9cpzP6R`-YakT7GQM7A|SVxmy@Mwq}sPd7jY3;XwefFABUlJ(I*_
zAp2W4lz?0piUFk)JaZR(Gu=h$8&}$dx}SQEqBP;}FbOY>{Yc~OA*o2n4Qkeby!idR
zwAx~b8Ry%SZc`)&pr_1CfQK}GqrvO&#|~N>)^X#GS8sDy8|Vj_o{fD>iF<pZNUD-)
zk$6cg-*{OmtkE4!Z{j?yu^AhR`;O3l91I3*&Ptl<BIEDVGbCF7Ff!KqGCL(R!Z;l2
z^7&A<V}c<iVO3KDaVhd__y3*3|B&?8j)~ehv~D{+FB6I6U4ioVY(GQ-xB-Hu(B~LT
zFJik^KNW3m%Zm3+b%^M6pY5VQ$;|YOEMFlqBq$(&)VlXIon61w9T1X&&<TWh-XBMt
z{{;sM47o(j=+T{$K|0P5K}}@=fGe9FIiojqkz2Y>#@ps=GcLpm9AIIlgQd2V^L3cZ
zcR8E!$R<A#;&Q)k<8p$2T*3=6CK)-|glcgQjy;i|Xv{Zeay56@_7<!cHk}*DYxn-D
zg~4pB28R3s|Hhd8H?EGmAI_vCzpCFK!abx178Ea&Ga~%2uV6kO&IY|XI<7`_nXnO?
z)dZ`v2qI9K4s!zD{UhiBNxXtNXc^=_Y4i3^+lkOg;w=nc4C0O8EX-~wh7fl3gI8WT
zLsDw_PrleVj<4g{^lrkAU!+9P?7WzUh!vRRlO-;Wt*9iL^CT@0Uv^>=1^GFV>hGAI
z!RsPN!>zEwba{{PR6y>u8m5xJ%2f{Y57Hqj8LUcf)7z$0B9c>P=wktjuOd$<H%wME
z`su@lbo50+REkSJbf`xxG(s{J57tOXu40j`jB&&p3CQ{0$q_oym9kY{=Ux3IVn59?
zC1p2ujLKA-sHD>8S<-*w4rU$>xE0QEld)jEj;CW8^1UaS>1yCapx_Ah3!f?VLH{&>
z<cJqU#`zomD=W=#Z`W-x^^O*@qPzm>oK?Od3&$&sxR(1<xsT&%)Llakz@FZ?fv3l3
zwAEePs(QtvyVLeSz9*uz_tCYl9SlLj4};{KctGUH&b{h*`hUOPSL`ZjaSdMbF_`%R
z!JRdG*suj>#a$Ym-Of*`iqz9E(wC$umpS%ozZc@3*Fz}!6Y$+GIN);6p8|FOv;*q(
z_8Kuozh!2SMT02m*0G7Y=p4zg;&k~)e}-NNin|{9Z9>%Z@JwqL1$($U{cxUH>{`y@
z_=WOP1Wdao3Ze}JCYeCj!K0hm??mR?{iS{C+ImNx4_wH;i`G^-qzkp^rlGuAhj;Ui
zSZ``~AwoP9OEYFvM)Ao^zOFs;<r2X_f<)?aR84}e#bx8GJR0C4)Qs%jP&`{+QO>AF
z%sPGd6=>pPn`3)KbS7n022~#QVf{zaLorbj=>*F5`BVnBm1nQx7rU(TR~AZ;CDmtj
z#NVg`Qn~U^nA0lSrKHX)a+?_4iK%&~>!Y@G{XVlr?lix0%k$jCZC1Ow6CxX|7IN&R
z=o;ggc#dUP7I}usb%l20`FF=xo`PN+M&ojI8QfQS=<L2US5@%(EWFg7e;TY3{lv87
zQ4PF{$v<!3n#x0yvh8BbCLPD34)jyQMz$O+x)5zX7i)Z%)T|kQr_yAc*UDjzjnw@2
z3-Lb0(HrI$)XD|?p_jhX2Y4<4LVpflJ=%1#%<)+w(@QuN6Kbw*6{nMGfwYO>+z6W9
zTaNaL$Cv59)3q|rAQq=Pi}be;f6WK|LfAg}<yqHq1;tH7w4o>bN5-VMCIU7MO?Xy0
zV9`8Lh5fKA_M;L_T<+8`f`=0$fT8m$puR-Uw;XP>Q%kVuS#|a!NM+W{UTeymq{iPP
zCAM|Zy<)u>?59n$^&jnx9DJK6e_0GyR2QV*g+&Zw&##5G*DTQ$dPZJYluYstK#H~X
z+EICX=-r=A*$l?N`w_CHknOyA0lIbteQXYO4oJFw#Q2I`vC<(EkyCDP{iNI(ma(B$
z$h|yvKkcp?&|9#M7%mF)ss<iVX~@vn7L}O7^U<7n(z5>1DmxIM5gqs{!0TC#65^Q>
zDr-r6^Sa}Cuuw>L@86d0v{8djkTv)jc8N^V`xwV0xqS?ySd+<_@IJD)#eKTaL57iz
zqQ>|69D|F)O+K@L7x*dr7h1VN|84@0Nq^(yTr!_{K6ItxXvQnDw=9l)6LD^)LuYD;
zzu2Yf<);EOh-tPF_n%M5T&<9QN7KW-M-1CHgP)>X!3vjdLg4gM1D(fj!ix;$>C1kC
zkmAyXf^^$SViJfBSASu*!gI8!M0+xyQ*(`7iFn6Hf}WCf&ieOHu7*kW8_x`9kjq((
z=9~Z`#E2`EO^#F<^T_&%DyNMHMey<vu%nPurn54@W_@;clTEdwAp~kr;$cndIfK%u
z#Jp^jBQ~)@2yx6`lNe~N4bX`%qULd@93|%G7tm+W!hu)FkZ5`J-+B7qzS=BWm37eY
z;uOv>5u@t6R9MnN^g*CqN$c5RI|fNLeg*G~SMUI>wmhoDRBD4%o*GpLqbNYbe0<d#
ztf6_#-J4j>cl9lICzc7b6^Twz?U@do_~a-;T3Nmz79)EN(8e!9F@zQgM=Vop4!uCn
z*{f~YTZ7rkXE`cofi#4&-e=(QmkcBX=@QC7{WMaxZM*aDaPDDaD>&Wsegr9WqLzz*
zUW$Fegf|py-xFZ`&f{bBuK4Dr5XB{X`L2nq+ZsaOK{j#A_73qWQQtX{7tv{=mq<kQ
zy4&yFAi+1KWQa<qB0%K?hx+wDZ_UT}l7<-b4TYn1bmu#X-KzphFT7jtp??=KLUW@L
z$eMB4_ieUz*Weg@1qFq{;;RV!t>K1kT`7~NdHeGMy_+ZR%~Z-J<)bp&Ai#Eb%URpi
zF)QK>pcVJK^gPxO$91JJJ{HS>YIN9oT)3y;XGp);*E~%~Wq<Z>GvAx@&s(*;N@Q<j
zXCfAoluP8c69|hDITD<okr{U>TBW3-I*&xW>ptT6T+w4S`0Yx?(P%B^df~4+Mgvwa
zH_Vhb)uo_0(O9Fk`Y~N#{?sL>taFL6PfXz}UxB$sA2qWcvAoky6I{k089Tt+Y^!>6
z_jA`~mXLVim1UtXL4AUt67!Yg3O<hmi6KyDu{LGYIn-mFm<kuG!)ic2;!%*l8R{NJ
zW*MSo@Tl{0wpYB)kFU&J<yjzS=u({S1@5s0vz7qv5nlowEv1=K1t>`jIZldQ_RE*8
z3ZoEmh2)Cgq*h}y7j%zl=`gTwYpAKg_^z>8F`qiP(VyFgty9zioks~w!V>&~aL;{P
zU2CuK5%PgpQ1**nDV>pkNn+Si2HQU;?%gdWZjX}N!`r8k($$jq+~Z+^00oYtI!l?x
z?1FBrQUXsJ`(>ic;L2fHTK_K9P{iOzAW|>Lmwm#Y&UX`8e5tKtQy}w`hgX1pr-<e(
zHDY!7>HfSG;C&a?5J#%CJ!?YD6fEwWy<i#f<}2|+B|phr#P=2@q3c!ac%IY{5n1y(
z4(N6HfSTW4Dgjz`N8LyVRA@>MObV;ETVsulqUAlEoHSOqk?eWpt_)Fyhs7^>=KME+
z;9XMgclhdcmY{SP^nRsfiO;>uLAfBj)32}GxLegJc%^&q%h-|n8064~yIa`xZ&CRv
zr`P7WI6dUdoNa0VWvjoWjza$kWj?fXz0P@nI3<n{(9rfV)?TEh*OSm;#Fm`Ndg!kC
z_Si*+O67GO7DAKv=N4$m;=dE{eH!3zE{dU6(TnvGU-P{jj1n_T=G5<@?^~6PZ63B)
zwbjw+666A8nGi<gSiHp`KvhM|`nX-z-tfSptXzPj?b^PpZIHp_-~s^ui~Q-UOgvc%
zTSi<a5?&wuEZ}q8_#J>Y`-L+*YI_A`l)7|PcFrs{*5)4^S)~dQ2FOF+z9sRzRp=sR
zQuEyW@0g`4*#wrwgFxxykb#}r18>sPGhDrvrUotZ+SUql@bSwp7XPavYwR|m=H2M(
z7AFO)xtCrJV7_ZoawG|qjJJc}6(K?~d6GPUByD0ni2M(dc>myVcrWOxLG5aIe-E|_
zK#hL^T!v(5mt+H2J8cbbQeFba2SY79MQq&5HZhRo3GfOq9;WbaGhtZZwr$Re-B~O6
zvi>k_CG%dkFqbliFlG4lP|fPrUcxX#4p*SDNmll^x-N4BMAN!CW-`x$M_%^#BU9q_
zxH9^aGg`<&M1_v{zUJ<2hIwQ+>!3)4)3;rbNRaR-6#H+$Fw$Oa8`sF2L=~6tOJ$lc
zTDF$`TpV=_NRCqzT0^qAPE5E`MD2-GK2Kis*GQvc*>+U{?Lv@EJjLY)!!sann2*@N
z><o>bPaO5_N+|*xB7k~sob!k`9#YxM@fqFi9lI25mXF?Wa~-8%{qS+ESI5LIIX9L`
za<z}s$C-!VI+?#L(HSQJ01%!qBj`_ajgA==qBYhK$QoFY$29TZZ%WjyOq|;I6EoIw
zN6FM&T144>ct-p&E^)s4WayLEX5jgP`AaE>_%{qbZXQ6;$&J%W{`LA6j(BEGbJV1F
z_ev=_FBAB@RNa33*j(sm6;_260YGiBchOyIUNMYebB28HKLZW!z6ah!uez4I;47N;
z9Uc8;`Akql8W_C@2s%aqOBW=6L;k9kna_!-MI~PekjiYss$WxGhnf@5!cNSt>F0G>
zPJCQvjc=XN{Y@2El3n$<NJ~>0X)FXAD1qTOUOr%e+#y}H0~qxqV?l(N7dKCax2m7Y
z9_5Log<}<grdX0Arm!`h<$aeW3}-D!nu5H?#IpC<5Vq34wH5Asxa3(pTNIzMZ;Adb
z2*;7yYI|^)aMkkpFeN+v+Dbs29;8Est!Deo&)Of+U;l@9Y<gEDUY#gt=MpaE1-dQT
zc45I`c`l||xNILL5iI^>W%3mecL+53eAZj<PK>!kYK30Nlx~!_XOx3sv2Vc826%rN
zP;u*ZHFtsueai2~J+IbSE38^d2+~eu;gQG;o^zx$OJ2{Ouy%Fqd5HY}+d>{uUa{td
z(Y~Yq4UKHu^blAFG0NMhIP3hRO!>LlCIT+?7BrXOD)`{f$|NH=2}Pz%bRQ#TphJkT
z@};TOz~BO$UGD-W|Ei*g_DJ|jXh}P7#Tn9wWbp0=7dY7(n4Zt8Z3oc1uEy&__r_h}
z#-ZI+&#}+fZC2w(ZygIU$5szEp_esf9n2T3A^B|#1WVD9E?=5ZjMXPeR?d~!L;?6t
zv3HrzJJ>=wH9D3gth|ZyC=dN1O^YfBB*UHjDrbA6P;$U6c24HmFdyjrmXaZx0;%1(
z_qamleV<bCClMvc_X6Tqv&u=M^A5#Cy^d?D?es~xz`5e`6Y+w26{&N{%sk{?G+&g~
zNhK)-krV30OUZiKE1Za0kYp@<Js?R^;-}d7gk2#fN4+MS^d;ZDJ(S+9G?c+XJ2Y{m
z@2x9Xtbm0h7pmv24<0k6H_9?fCgJ{7upzR};n?JpKB}{<Oabsc!wMsEl@@mZg4|1E
z{OcbHv54p*G<4GF!e#sN=F$mz!OZdR?8cO^*7lWE<Q^}Rd`*1p!I9)AK?1BR?9WI@
z5(ewGt93KzuX>({RkT}xG7IHZHkoMelxQjtvG8Qpz2D}K5OW6!=kXWya^r+(cX#BI
zzfMZ|Xm?Q(TLX3)`~QyRt^!=MD4U?VpOQG=3xHsP2b4ajEa7)*$kPdN>u{6wJc(L6
zlBvMH8j-imyMe|h>|wCq_35k7?}wC{6CsEiV|y_>@7{e+?eY+Mw?;&?Y3C#7A}{Wf
z1sQuK`LLC8G=$=&NQK$rZ)e89eY}fBDnt^vaYxDw;-jlHYmmw<kD-Q71U1$WMoQhI
zw)|BLl{PW}h#6&F$I4KezxNM!<P`+<AO0t$Ay3wH2O+ZC>eDW2$o=QNY;5LekWIXs
zz3p$9ByV+8vG3x)Vg%q4a(`Ar=DE`-<4QvkqDs>>Rvc#HuW9&vWNVP>$3Jyj#U{sa
z)08=9D73ua?O#`R$AKwfHe)4Rr`TEJWPZ8q7C*AjSJL=y1OVpZNF_o!+BpJ$v0Eth
z;a3#`zWzd_omlXmvmOitx@h5mQEUNKrhy_@ol1=Ed?F=UnvgD6*ECZsOP4gWK5p#y
zEOshq_HPvy8l_U@0-A0nvlRPxo|M3$+5fetq`}x2DLJtS^Pbkup+=E2+<PcJBUJWY
zc0^m=0AQOZvGATK)7tWz)Sfs#DH=fh(o(@k-YPHqgC91vK&q)V2>U;|w&0yBID;+L
za)aUc4`T5dr9EZbbn|S=foA6!i(S+s!X+H?7xoFk;k&;)mmCGzTWveUAnD4dP8n^3
z31Kx@RFTb@lkJAqkryb^wKDO?z`K9-n!mLvI`D2a1t_;difW=ICjVCsF<&Bx4oGp`
z*`ZiolC0k(YQ<a)i+Kz7s4%NuzY9`;NrD)tIxu(2-OwH4C`m_P2%P8emgy{clCD3B
zYCLc67eB{M(?zmE+=_`5^2Jhb8#K5oOsYc5dvgM9eKY|=SyXG9jI&dR3!o$Jj>tBh
zBR@dJbN+iLCiF^gWY?bi9rPv(Uj4wcIQyWrIGh|65Ngy^xg2c60!rDIIG_v8t1lBD
zYw0|^m_J4N^UsD^q2Hfhr&V`YE4F`98_gh4`J0QoD6*%qS<VA3L6onS(IbJaRecu6
zox%CP)CyQj3{EUVxHa#&_?8Kb=nbPn!h}UX06KixHLIOt!T)f5%vx`#Gr6nJVDUki
zGv(1iC(-fE8kf@;ftO|le=Z77@dGo`2$^cjFjLI)_4kg|F+eF`N?AZhicTZsQmFr`
zUK(BT>kExb^qP8WJwZ?5ER-iiy~9^@T=J~!C6=---AS+Sh!y=}<n=w64>`R<gBm@m
z`|Q5_O|kud9VDz(BDyS3f46IsF+^`fi)Me2kMNtD0If-FL&qwE?;*1W4FqS%60}xK
zoRsA%NvayRA_xF%`M-PH^R`goGH}bC_<%5l-;On(XBGZE=^pf8F?q4w4~NrLSNHi(
zh!`4z1bKM4*SlwGK-<aCzsu+R1xdW+lW)|Dkcop-$I_yYytVPdT74FLsBJTcTRWex
zdzOB@k=}G|w{2QStk{M`7@3B=+omwABGvB;W+oMFm_NF)d%V{yf5IQI+*)=v^_O;;
zN`bCdY?*-cvHNi55K-yq=f^GjXa0pUtS&q*y!T0azNMg`C%~Xu0mc#=Vi!Kr8)pJN
z6+eS8>{&yGgbk$++*ycLattl32lgg*$um>ISqKsix8f}X9<woZ{?3r$B&&v^&1v=t
zHQUIbze5Y#nV~c>1KQ3``g5?*cqaj)=s#8La$C0sfkkhckIh3Dp+v0@e3fD=YU|!0
z8Wo)0vO+D26<(z620v-?v1Eg%%pnv;L~+W*sN3zi-j2~V+7z;1YQh;|y;o1r@pq`3
z{oYIjkNyz-WvEi2dXxq4=Me<w<p@yDDFU5T`D1CQh4Z3#=}pX{`<&;6S3J+>NB#aW
z9w%j0ndh;y-Ol2C%C%lTD7}dV)csGno<gFu`kSps)NKZBAPfX=nfcnq-rz1!fw!-G
z&?_j(Gc{ivm*$?^1rJ`u)oFC68%1@c4ZXDIa{I>!E8c938|i5S3|TU5VKg^X^mG#y
z3Mq)eTVZUO<WTMrk3(0%26|q>D>cE7Qg$`dGH3-7lz&n47rw3(v6-nLJ#{vu`teQ0
z9FF%78+}0BzEZ*eBtNsB;2Jw{_ayskspdst4JRhT2N}7pXxuo6+e+T!&84;gZIxKp
zuS+Q>em}!n6J_*W39(bv77RI1Fs6#Ae#-vX8mQ01+bMGO%L_4ICSEa}hBBG!iWJG1
zgCA35)1tx<J?o6N*3`@mFw+|>^c!nQeX(z&ZW(NNaQ7gOL&A(%>#8sSDe7cH6{W7`
zuUlz+8Y>A1(XPEUhXu2;W4Dn)H{gXzMpH~7eG@QxI+tjDmcd2i7%$WGo#=NrMreHr
zMVg#|n*Jg01hPXT-~cBfV@~l#Wf#r9wMAYOrZSx|wFBX5wkN-$<zLjPHG0_Oo(awr
z38>ZV+)Add!8llpT(Gj~8Ylmckdpi~Hy}UL(}jXv@MU?BGR{G$xsZ{Zp$>~bn1dGb
zov_Y0;uBpz_iQ3K!A4S0;E?cx%E;{X`qfXx4q;VQ%j{>?n;DU3$rf_(_nSnpV`DyQ
z|EYb3xVmVv*KqwGVQ#M$b3tZ7p>r%9F{7G;<I-1Kf2$qwsC{%3s&{w89Y@2^mA6bA
zjG$rp=18vnQ&cC9Er;i9Lv_IbZE4b3adk9eXl_42quwG5fwg!`i+I#8@Qqq=)aLAB
zgbkFdayi;6di!P%)e!sX87$_`k&Chx`qqk)BQx2)UED%sK)^k4NO`74ah<pjwMlqZ
zsFYA=RMfM|i@@?H3=rnHz^yXx(_`ml{a!BK%nj4Y$9YSDFeJRO|0Ujb{@_|qSi294
zL%7QHTP=4d3+$6qS4s^0D6b7{gccuqT62G?CAt#d7LEgmEw`$#5f5}J;jle^E-M`z
zcfYkzWfr1=V?#4X51BJ-L&sO2uJnqqEtl3xT-M$=ghrUk!Q(qBQPm6JUiRL-L?6uM
zr?Wu?rmS}RStHG{vH;Z2ahq$y0#3@h9-FkCF#@)M={7}mn2fd=$Eodz06UYizAk!;
z+^fKffAuT$ZoG2Wk6&bErk-k0#?wvytkR5*@P#(~P!qtUeeIzSGpVld%mo|ev}Wg$
z6YUBhGj>>Ju)me1LXNbL$;+jwPKCc%t6n#4^oD{XNTJ|HFLh|1ftysLGG=aB1^w*H
zT9<2S`6aOYO4(P>qvc<Ad$ihx&Mj^I9~=n~$U0V$$c3<Rb>bgP0k98oe!JPKJ@*x5
zCK?PKsEY)U^N6Gp64!K3z&oRxGQGALxU%QNw0o6&v6nu*l6GQmDfT;mZC;CjZ=ry4
z3s;}{CYU(6dgUn3EUBTnB;99W#T<&zP1=oVdhX(_;N|&pL+0N?@;L?1ys!HkcaBMw
zuM~ukjs)-3$iOoIO=wg-upVQluEcvUZUdR+9pnR>jLxG(k=qMXK8qIe?@Rab-c`YA
z8Y9u;GR)%07eP%YCeL>bnv!QSbNW^EYf#<Ay~2@}x(qJvClg_#N?qz?u~<J-eX(uz
z>v@>m*n)uQW6+4RdN&VM)i6^nm_f7AlIqAh*YhwNF@Au3Qg1o2xe<E-;vNkM`kQ2q
zX7UYf){TnVntj^g=nEY`9`^6?H~UXp))u|@Ctt<x&PuwI6|56(kiezAyp!`FQtEXt
zn;QT50~F5}CWI6atm~t|P3Lmp;K@_sjwe+2*sc`3H^{1^(wGoT`{%ajZa;8-ff?;@
zW?+jeg3gyh-@DrT+9Wu}Lb|0$q80gf3)Wm^GRon!C+on#qmuZf5!T5Eu3|QR)R}3j
z7*10G^H}JEtB*pUcZ|e?BA4+|Umy#Qk0v(T{_4Z*i6&9vB0~B07r{~<iyNE~ye}M;
zx8Dp9oroxyL=0muO}MR{%)RBUJq=+9$sagQ=g2K?;irAaT5}<Z6*2#qbrd~re2#5K
z(ka&w_DSx%lhpl3Lw=Bs&|~?jcGA~QwSWx`$oC?k&h$Vl<5C6VqgZqAqJDiL4-aVl
zkh8WX+i2C=vh9g{LYRzH_~4)`hUHW+pEnCjqOtl#4UJS$|LN6=oZgIPtpS!%EEA^E
z?{Q`$C&oS*+0Pp6x|r!!AxVePbKYZfM}TFn;xGYcn3#iab5n?uXOs?HPuZno!VWYQ
z$rS!3@v9qN=7TcLdcpSze3hff4*WB@@$_CXn4^kTw++?G%%H((lv<nMh(c)&<Ebs$
z1Z!FlzX|xfoGm!bvK9{br@0ijnA_fsTcAzB42`SFM)+eMjR;pf>#SfMHyVgy1e3E|
zOM!AK6TnZUZs341T6?AX5tnu_jTYMd)JItjyP^_1upozN=#)GhlnUK^QIPz8qIpSA
zeRVHSUyJ-1dPCIRU8gi33HI^f_aiswK7l~v(f675McE?S;5?4PED-St=sEr=9uYaC
zg9Bkf^>12FVU2VxMMMsQ8eOzf<Gvip9LvG~JiMhM32#q(EF0oCk&yq0MqO5Fs-ehy
zrnaohv{zX;z(8{@7@QMHWi>-HfVtPdr!anksur92I5w@A&_y59_F$a?c$5U9d<ZS4
z$rr8(pAUmb_O(Ws%YFhQr0B$Dm$qq6>UizYYo4lJg?j!X0i;T%lvKH)!Bi09SAgli
zpCop9*6MonZq(Av^v1vK`qkLc|KK;2e<r=@ovcyA!43_V;Cy=frUs*tzSxwKlksBi
z#>WaT@5wgib3W>ssxu_x+--T=ZY#|yx8+MG=h$NN4jU6536(SV^d0<s<n382l~Wnj
zBRuBV+9@Ff%+k1@`hy6(#zU>SLl@2*e+GCc0#p`tLG5Ycr+<&VI!yJJYprkeezL^2
z!f*0opfabt%=wh-)45QwXhKQ(KLyM>x3b1N<{Qh-Y<Ecy_xk}_j~G68j+eg~M)D&3
zsH<`in*W}(@3^O_pIQ(7>TXYdP)mq`^^R=RtlqsK#bN(VyX-7Z%C=6Up45~^)19dK
zF@Na|gI$i&oBHgANl7z)7J*6XSr~Fhj{HPXsymM0gpD66uV-Qkwoe2ZyD1kSD2zn!
zrFrQ!uQ}lp#*M|pbh0GaxRYro{ZkS*je1kwIP7RS%Pn**-#JV(tJ<m|_}fhmz1?;?
zD~=ya-`zm(^osQ7!d<lUYHDs7I|Zqd&)}?QXhS!r%YDYdj0WW#Pq`fXY{mxtbeJ%t
zb~%plRoh@`^)v4L;v{p^93qi+ivXg*S^-@z0Sju`AiS2797#q%^xbbmq`~*PLt{f6
zhqH{I$N0Vzn=|k`LpDx9+TiMhFm^#U9m45H=AYaT@mTD&0h~6&TL(#i&8^a`4H=$f
z?|$9mCt=J^Dl{L^v`#YZ?XGI{VeVU11v)`HrzM4OksePQ(seJ2K20S<WjgeqsHj3E
zGk-(!3r{*KY)zf@3A$N;&%-{0XW9IYtg>hbePE>Zqr(#;1ZkGYe78deoT5m+gvDMT
zqQlEg6Luy}=m8s}6$sS6+$=t)Xb?&*B*-%?p9miV&*RqX*J77*K0W;}s%_19Sphx7
z*L>=&;8)V)(6#Q1OYff*fy~NF#7L*n>1F~gk{dig8{(8JR4+{0mR@ukM18$9yu+gc
z^E%i%JLw>)welAi9%pm@L(Xkjc(MB7^=u;l-KKa!cP=Nct)%DXP9vDP*N_2y!#A0c
zk!8NXAVQ+@h5Nrox3HgPUsFDKNf*Mj@&MKHC~kOIE~s>%z}Ncz?*hv1e07&kA`kfc
z5bN-8f_~;ytBFJl)nP}b9pQ)d6fmzaT39u3vh?TflXM|N%7AcBjoWTuE*@go7o%=3
zI{}L2w-F=xmw0jAGAQDfhtBxO4iy`!BXjCG&5f0WnLKx115uyTd3e6U+Ybf#^L&bE
ztHB_nlxL;GUIr%SFegD(8IqrKri9lX7x7yE^i}Mwa+rZnKrT-7?&%=88;5n1*eu5s
z53T!saMV8`!o3jUWWXgYtA#j0d=<4{sq=XM;3nqZpDcLkA*`BjJ+f7mDk$oWn~0gW
zL5YdS>Vshf*76Q?Q_TT{8_%_?(=TH4z;<IXS%F9-;XwI$v&qvToGU;K$2$)v(1?>Z
zZ$Gue;S+#q-qa7gorhF;lQhD-RRYEB?mb?BG)Sm=pTD9~qXvF*Am}U9H0pBegJAhN
zAU~*axP5#;_al5`{`ii8;_gaY@N$6<5dgWs$;Btdo2tkz-K{eW(wPX1hQJwx5({s6
zJQ=le)`du3yf3d+Fm@y6_Tx5%iIs9X2g0opW%yFG0be_rh)e^USp9chf@w(L#WE~z
z<-X-Vi-VnS@~CD<j=Fsm>7B93CvGilGCx&ea)6b-V3(ZQ<%?XT!(1%3PBC9(mXX1Q
zSazi`L_Hjr8-!H)F8h#)m>)X}2y`f?Xh0Eh%o=f2xx8+?>f}5M7VrN`3uD#v4C=y*
za{b9GL4A*?jXu`_L)rBfi)~29xDAEf2O){!^KzT!1JRmcg+3ql(%u6r@?)*mdL1gV
z$cA(IT%Zm2Jc*4LI{sAI^9etUVbJDP&O~J<#BFY_J-mP>N`t7RE;6E`RR76v?Mta;
z$dz5KF>#Z&{>A*zMhh5%S%krqQ-3->#Xjh1g3cu9nVGG5Hq*=*4IR_oJLu8|^nLT?
zFMSCF+N;+q0+j+OB_?Vq{geme!E1gp-gj9iZqdfVE-%Ig7fotKWMlp5i%GL?T>nZ-
zpJ1`gU3xGr9Yvg>qMGllJYC_(!xuORD>`RB&32dH(^AXYWRG|gQaNc(a#5vCz2Ctv
zYrKpdv6SWZtJwdc=2BNlSgvxWugp5ctn}H{%9u^taOx8$y_|ad%N7BZMce@sWszZI
zcsS%;MHg_r7VOL(^)I_Lvy(5xx4t6Ud;toZg|Ja@K>|VRYhqjPMEQ<pnFzz#ghQgl
zuUYG<OGqp)pxc9^x<`Gve9m_pWp<84uGz*h%{kD8L9(gI6)>70({;*BA1C<Ec@6^*
z|4Xm(7yNfmbGl(!3w)lN_+J;t)M2736$;5LiJ!cBpa06<FFniK^ve<1_d0vbnxrwN
z5AtU4R!i@~RF|w*$F^-=Q{LQzV}o=+Jcy}CVJ9?mEz(UmcVH%mT}YCn<5QLH|Nn&^
z%s|^Bj)pF`X`DI77vL-J#5`NY=zDf>cR@E{Dxd5h!A_bJg_++SH`!{(e|U)mZ<O6t
z`;T4`;Los+9}2fHz={fHyt!2Lgq9WCdy?YyDr=R`wmv;y^HV`DE|d@o=>BrN*6|tT
zBZZNeQ;>Ug!#y|?^#dmSWVGbZPBveJ%Ta3^9F%;gXFLtW>U#eK1IW?xivg&i-W&a2
zD8e1vJH$N<(m53qJM;!hZ3HOda-Zk7ubYB7v)J|}`3xT88aq#VghttsEjX#Ju~-@Q
zRH0n__7d%DN+sY<`jGeD`sgEUQej2ORjlAjJrgk|YP?^Znmheb%c>@GF&%9?OMNSh
zTkg_ITzH4I1DI7|rUO;_0?$%QTD%!(n3y9!y2FF$RE1}toG`-p#f}54djy|%9X_ah
z$fCS%CT3{8$y*aW|0J{tM`o=tC>@-9bmbMngW=QMF$(Oz#?)lycGAZ~U2|grO8F-_
zj29y32T8uF<FYVm+V-h%`z|%mv?<V4ySsgxUR3Qy+-=>d=8%nro>BE{$%EdeLtqi|
zaS>yUeb}E^2?5)4Eve)IZShU)2L1pi1D>`K-$?<}^!l4#K~MLp2a%rlFTeYMeh2@o
z4FwKzor5xDB>bT(rUr$-P|SVGZL7iulY8kt8_*=xAT-js7qwNiJ&Mn^8_FkJ@7R$t
z(!%;^<87wm9#2ko*KN3;MXUwLak*(>q3dnO24-Af4^fvx&MQB%(CT-QCHf!9t{I7I
zRq)4Uxfa&|2@q1jy<77wCS_uBDP(TM7F4bUZLQ`*c|$+7y9yWpRmacaP^N##oT^DR
z@MiAwly=ZV444=~TJly3<O1%`A`vxu|E2<X5yGXa3bA@hue0kdn+jS)gLH4WkiCz!
zewVKt3)`N~xIhzEpX|Ej`&q7q9H^y(p}~F$(ygTtTBwC(&8(uF4i(e!J4zn6asn0%
zbrFsMVKcs1Oy}w4Sp?$#@l$^h`AN}gF_GbOhuuneosRcixOIi(l>rKg!IryXP33wq
zJNani#dKkS<yE?|rJ^-q6<ynN^!Qj=w!s`}4^g#_Q_9#CW3A()_yKf0I})}<?tD`d
zC5m8YL4of?ep)KZRyuID+}WF$SbUJtKprdT<Z{8DuZhH4psH|j3QrR$%5g~5_+i<f
zrGppbm{Ys3V&6i^A&eFo@}zlCU^4sppT^-R_xCLX+PpVlYGY#2<3s~~$(FJ7R^8Ul
z0JEC8-U&v4*gN=0KYvFGTsAe2c>qD{VrkBc1TJsp-JYJG4{1+mb?dNeEsRC2M9fSE
z&VbhNaqs~m6i^|n1GDGtsw4rj@99XgKD2cu)~4!7brailSMO*4N`No=lobuaxBcmB
z1_cAXSAHVcd$(w)=w0;wOw1cqAD_U6)nE{C`==vfO54SaO@tP4ZyO4}hJ#OGMYi=N
z(m*b({yNcmvwv%PHLub8q7quDgf<(-BrE@|7dqj;1ku$XU*FXB+djM;4%yEp2jhQ`
z@S`T2D|Yg}|DKpv{3zSntmbRx4O_01wE+v}!c9q)OlPR0q(zJNGNdVoqtFUV(o3Mx
zT3>vRLLHU1In<T#MKPOA<vWM+#BT-OXh~Mgk^RP^bVOe1sgyt6NcS+m|2Q6lCSvly
zCruiy_s{<$W^6Hx@eTq^d+6ptp-^~9+#XGb!w^1`wga0K>+;s7!6ZAuNK5u;mYJRR
zFjG|1Bnx1F)KO>kLKwa=u%-m?VKTe!QkeeIxL|8oI80X2AqB)pk@kau0rKYQ+-+)7
z$u~Lgnj&k4q@P!ZI*ExJsPWk=wM_Y=RMe)ij!iTcAQ?5(y*&?=O6<}#cG1I7qbHJK
z(?b8W@M5UWqO~{Nfx0dKw1MIGeh-LrIEAK|-;7V<!GH2Ed=xT2Zfi34obsM66&q^V
zJ{MJC?vFi99kpTapCD0Z%|@q{fpNiLbwHB&$}Ruxr`omK9%E;<3W$w9aZJG6NX^nd
zKC(x4E#mDpe&du3jw)yU$Wf1MhdR^Ec;zk*YMZJ0d_CK3$C_)$=1EzeUuAr(2h4kU
z6oLdxeiqvmoavArT}@;<oq+t*tkwo8uOP;!?*5`0R2@;8tar68>5YQXi-(;dtnM;%
znbZ!kO@EbF=hluc!{lz-UJzMu)D#N;t)B8NYWVz)<fNE9>PlHP6CFQry?2(V?)byp
zXpBzx;8U7v+BsDsAeg{6G1~Ym#p}s4A9whdw}lA;SK27g+XSaiO3`NVyu=V0Z(znn
zc6i8yAm`k8NbFXzj$<p~(xP6d>ZM>3^ME)}E95Ac)WP~LVO7YtcY)oQ$>)C4uWLr>
z>D=o9Yg@Ttz%a%F!U`79U8?{J?&~Nk&z8i45=fPrMM0ky7iG0l>9WI%=DR~Qm)KvH
zZ};Hd1-HIb=&|^U6MA>-yBUa(ys7FS+>MxS;9AJrhF6}WBmr?^Ya>-y?*GZ+P47#d
zdPM|xqL-al+G&ve4s-Hq)@e^0M>BqLr5yD+Um}sZ4T#xkss8ucr7jrn?A~yFd9eSE
zPnzdwI%<2P5DhFIU&h%`&_g1TGJ^INrDAFSf1t>NPPhd7TW8F1>g-4CXxYe+FRUOP
zGKu+Q{~;D#Y?)K^Yn7!P^B5=nK{J!CW|8Qwz`qJW5oFpSa|tc>6!fHiLvTz?q*dX=
z&^z5YoexO@Q_t16`j(HcPTspxroO9-5M^7BFw>JE=HzCSKibBDVX@a#ef_Db^0r?g
z4C(3c!*L&uO)(UbB*5On!uhn!Gu(S`Qw&`<orMI<+Al&}bL{&^(Rx|*Z6N)SA1f)I
z@W}kdpfm^9{km@wx-;PtWuoFD{UXC0vw_hl!h<?~=4iciEn^#G&L%0WsDQZWIJf^@
zl4|V#P3|vH()-H@^wz<kVkHk2Tq;fzjFS}qh^gI5h>_d=8;-e#b+lCgSSCH+<?adN
zrQ<O0KB*iS)U@I9Of7(a(owWjdd?{<&|96$-TW6H-@YjHeMC4wjt6>;`t#!Gn602a
zufN&nw*eA_CV%}q{&SgqqWh!6A1$6FLu1Yb{AEC{y>zE(OZa+Af~=6Fod8!c8%+td
zGJ_aaI)bej!{N^b9JgL@D3f~hb>&R81yDj%a9PBZ=d3Lcjj_5^G6NyC2!NkyEDnCv
znK6-bD1}P1DNkv|!Y&P4)u13bP@k3FBIVqolTsvEX=LN?PyseV!QTlMH7kjU4OD(;
z7yaN{WOdnVIrwM{HNy-GTa4UF6*PAauR_OFA^gOLPnKgUE~>aDf<vi^CV4!b)sy_I
z2}4AH`7!**545G?`uT6M=@ryH%9Q&R#Em4p1q+5!;yg*DH7QNTb}2i8Og9Y<kXfmy
z#Jbhs6p_MT#$%+_f?L(-n=AUE#UkoIFsxW^W}!;PCCoERwH4*mixk+?S%I?$2`%O1
zEdTi}Yl~M4e!}M-zG)-P^D!6c)B6mLQyJ0r@Q*6w%-P;u&1D&oh3);Zb(#S1Jh&b5
zbjOLb!kE++aJW0*iF4IR)omPwk2;l&__u1CBSebtMLe@fwcp{L`Gz1`%%S#gsbyFm
zh|wp{8#aNElcn?jN@**|o`BVwxbdB?r*&Z@Ov_3^sQhQtA|uK5fDe-WzZm>xwQKD1
z0dW<M>SYO7WwS{n<KpZpn@I&HK|a0{FOm?TQaW{nO9_Y$J;xejr&GzURA;p4bsd+*
ziuvp>Zi$Ip+mvG*PV}$ZvNWxNIHj#-rJ#5a|C?UFN)+ev4an&}8eePs_^`vz&#8#f
z$}+?}Eqg=O+>S2~Hw#v~q8<;C2>VIo!c^q8@o6emN>wRS`Q5Olbxu0s%Z6Jss_P8~
zizEC|1xMQG5?2ktWSnGS-aDV0G&NjjtL~v|J|UmH&^@gEmqoN5PK2lF1x%V*AAm;{
zcGhST=68xwD!C%Gb=q#JH$CE#qv|*Gvr_Jv&@i_J<A$u`9*+%2>rB>0Pzyvr-kt+%
zcIku0k_+Rq?evo3TU7c3M8><BKg<!|Xeg53Ph951YVvf*HH)3lGf@2?%KD7@hJpND
zl<*iZls~D)XpOny&b!D5XrS2%Sy5L<Q7!ew#MjI+l@vob@21zj=3Q~HugE_yqXql4
zSDWH~9QFJmlmT2aTQ>AWWmUqK$8J;!YtV<G`~@F8*N_reYyTJDnt8rK0oQln*#NTq
zL6>t2ERcqN>~JxEc;PhzGO~->o<FV0s~ZM|2pEiHLVLFKmlxYW7MC=g{}I2lZtjWc
z<P55m_RpIH>;VPw?=TD2ohxA;@0X7GsKXEAi*DF=n<!C^n>I5vdb{r}tp^HV;RDVh
z^!=EmKpA)ts%w2Bubd|2zfZle`sH2wE92sph^|4xsTC9BSG)%c)*2nv`T*X8H-Dt?
z5H0mCkiGJ|;UR4@T2krfBTU`HaaA<LPEaG^#FloQCfObi1tgV7btcvjjWYG@x0bK8
z+FHW`bMXM6PXW@EVscCTb|7L-(QqWONP_Sg>g7DM<lk`SyC*{Tfn^*k0b3jo;vdcz
zH2ZJiCvX~UXrxMNgUlHU-0RzTZqU~JwBrOyBblPr=GnKfQ?trAF?#%w$&l?7I-+^n
zXq3m*qRy^JqJq7%Nd~iSYi~MX@si8_(2?dXVoG-)fn{bUVS-xLd#5VmoYb$(X&;}i
zNpE(83m>ww2lh<B52U|1TyZ~ECg1nnr-W>_CeYhyprv`^J5tk{ZLz9@g^8XEYeE@?
zs_1Id69|VpIbj%1`%fLwncV!5%0A(zE~Q_7jwRJe;IFyMg77qL3D8vC4k;<wkcP;3
zVI!oS$2wT8oF_|7@yr{%0g^f^NB4t@kfY=ETR7)O73)sUA6r$OKw7EVLOdSp?}7&%
zS`qR@17>?~=8?K}NZCcr3m`CXyI%@G?F<YM$Jw#{WUzTc=pR`MVP9XS;ma-(_q$JL
z!N&uH`k)T_7w!gPE%6%a*rJa8olBR;hk&ovR|W=dxlUIna8DQUx-2CQpB9V`&Ge}E
zYX=x?Q-I*ls)ltgOe^p@WP}H+jpj8n3Nb2t1Coi5F(-0qq<@?gVi`C_$gh_rX+;2%
z7jb1;L%7#*ywn*qV5dq<yGrS0jquCq=8l;fB?QXACFF|xN0pz!@{I4WFZ!lLHLM;}
z8J5eI&)!CslR@-Yj9oH-;L*&|^-xM`NPl|*EYUbhEk<r*u!OsD09kiKgnh$WeD}#K
zdV1vRkssmrKUnRsNp=a7#+|=wHH`+LPEaB(tiiAdSkmUT3f8x>*aV-ASaTWWxoKsq
zpDGk%2pgnJDoLsOon+?vm@Pc9$lT++*qlqY82Ghocek-(GqRvVJ%~O7-9+^cL~kvW
zC1KHjVh*%1jP_KU>EQAHPzjaczg%BBx3MQrbYu6;O(d(W=6M>gxdm86iaHrEE&4W6
z<U$KDUTyn+Nrp%8dR{8<#D3jVaeJ`^FUsVGD2==Su~-!3!T`5m(k&m#brfZ-=W#0a
zP0M}pWjj0#+c5G?;0f{Z93yb$<tVf_0JT?Xi|slcg#_ig>LTOLLYKFFBBBqDFWW@j
zb1BkOea!=A&K`YvKx^B2_G^Hr?Vp~jN!Uhnu`ZginW4ivx49$K&8c7~heDGeboz>E
z(%V#x#Jl#Kg*mad{8Ne5br%%sIx>^yTf{kNlQ6qWb1|v>Eh@o3piLRr(an0{225A*
zs<jiZkHvR7RF~8e@bwFVL3{g<)yLeS#O827G63a1f~_T%a9C3*f?+Ge%AU(ug$ASx
zc_h>MTeemxFOi8QNGLIA``kxcS^x+CQg=9mpH19d9HH{bX<^W%tUlxdQ7TsI97f{=
z-hO5zsQAkoW33D>9%01Y)^!6PUve@4SC~IO{Wsxq68G;?CZvs81wp+@jwft#{=iMH
z@(l4E?MzE9`K>x9O*;->@+%z@vR?QKhv*Qgqo-^CT!>Q5i{A}ECZlkdiufH-tm599
zb_E6b=yc$SxIWME5SUa`_kID@{a*Jy+-USOS6l$+Bu0qm)unvsaB0)9<!$l$@)4Pm
zSIe$yg%B`*DpSaO`7-0g%V6YOurUzHw1K41WsE+7z*isWkTYcj#fFa627{X`i;~G^
zMtMqU1)`pCOMx}NWTp6{uU~)XaF<Kd3o)me1dQ=kI+SD#d;Gmkibe8+QU(JwL9)LO
zQs3BkPhZa%;gdHLL2}nkoJJzw!4C_!_pJUhgvtVphL!^un0Lvd?ztY$j$TBgyz2KC
zUUAm&0sxe)`91aObp#s~0!JjBtw`n0vW)TN7~M}Xz0Ab-EVh0(UgD>x^$wH;-E{ww
z4r65RI)O&eBz9Ks9@nq#KDuKlujQ}D;~3J9W4;5*FE7%IU0<}YOM(AuR3d&eT#uI!
zW+NNN1;3nA$T{)~HBL1~Dh9Yx{an5}Sq*K={?C)A4qzTcAdlNi;4RFL&12|X#^K<P
zz5S%=reREm>6KD$5-w<^ay)jmcm7U*R=6NiUVg(w&wp-cN#5QV8o$Nm{P}MEi-2u<
zQB|ydP<=B2Co)g4ec}Tv#2$taWE@pX?Gi{Ptn~;sX71*LhbS_sH3k=+JSa*Y=6``{
zEN=-V^?p<+FGBXhT&oL_4TmN8S<=J$gp<baf5W{qO_TCT0{FIw+l!-J1GV)xM&h|*
zx^I}ZN7T)fbZjYt-M|xJ=;jvAj{*?^ry8rnXjsXjNQm1ql%}laeE%TpKMs)8NRYZ5
zzp!O3nOK?f>^{6*l7sdp0(FB6362ts$YDwybyI1Yr7bK^|Bse}pGWWbF;!y6V4Wv5
z_>gibo>P6fc^cM<k}wL|i(7xG3VY{1Er|iu9j9BK40w4VIV=r~8eD>>=yD~49$70I
z1%?^W-J;+0gA?ap5pd}6-Zr?~;xgFB>yV=EVA9t?8ceR_i==MOci}NQ{g{VPD;q&G
z!ePa~R)ISVTl+fI`+j2Yb9z2os!ZY!PJ>m$k{I#fu@0KZ%GQEfr&c{d<g+F9HgYjw
z^^8pzbeEgN@@W3|q})I{y7xG$JvP8+RXqql?dKU;V5YakkDPst0DgGUt##?9`wNHZ
z;iN|YzqFWlre#K$jfb8ds7Gg~#24CX(E>!>`p$8h(lhIhRz4RuxC!w_+!u~{r|^nc
z{z+BgLn|eN!*124$hg6mN8M{HT<#qZ;(|bVu|!Y(?4Lk?KQxLv8(<Ad$TGb8bUUrt
z^Qou_zMo1=&3?gj6D_H~s$?W0UTZdtsT|G!{sND<{b{rWqU@D+K?<}J_?hiXY1oKE
zFyuBAk$V?t*I|jgs=uY}71S<16CA=vRrG@{1ok}NbznBssA>Pw0e14?zPdZC^fpJ0
zh^9(HM2pE$XxSU52@0?zR>p`RH*GsWHRXDV(0ok<JsNbTCt?dV{8_TlGs~V2FTLNB
zy}~nPZ!9xP1&*pxR&|b<z}Z=ZWL2GNgOnla<`_Zmr3h>6HU(~+Fd@H*8$F@p{bx;9
zPv+Ib0RE&pP+Wp?vfq5mcsf}5NmE|p!p9oa$Oz1}Q%2Ip&Ya-L055xA5gbCs)$?ED
zf!BKMLp*9y&zGpmd=F3NYj8+9+^)R#+IAvwj!7W6fs%EXda}^Bv5#aG#&<bj8lBAN
zY<}_L-kDBq)2hVAOQB_jAxE+bKdotq^*4+pm@G#Pk?&}fb#xZrwYgNMk~#4(yajMr
z8;kPdTD^Q>Ml>qxP+lF&v5YvO8xtS_3?^R#IFLEkg!t3%%?;f@Yb4ltpi_l|A$i#6
z@c=vU-^Wv6PkLtT1@?kDARy<I{Cy80B+T~Yv+ut;rlCi6$;ATqz2(u*{i{1=^1)bn
zCU|QjL#M)QAh03N5Zhw}+$t2V3mgxaWA>Ew@eq6~88|XEJ_q_+HM9SS-#TUM_<S8-
zb$~kB4H*F5T2A4x6E;&u1~NS8y<+^DlMeiuwtiSLdLGpy@ZRB<AaF6%^S5cu+r`05
zU<LOWgP%Tu5{P2%O;sf#g5>4@0>SfNmRIq!RH*Ka%oH-0-c_!csaJ!atqcjUUv=e!
zPkK9R2eO-IAnQRG2G0aLpiPJa;tmDGek$|>F!{%RePBR^&2?h)8|2ok8^Z0W7k9?}
zlli$?*!Yu43=qE_y5KOU6leMk;)<jSW#5PKd@TB-XVRN}b{>gDACv->^}MBq3E!{R
z<~+UxfLwlluXSdXyJYQ*@I10LLV-0&p(<yi6#Y?nk_$J;Yyf1xQ?o5F0cVenL2NCW
z;jwXkznL*B%-QpLb~Kfy|7Lze9Ikr57Gr!;)HGa`zcb>I)l_ffXWU=0y1Y+F-QX<U
zhJ5Rlsh%#MZ!j0M<22S;e-QGi;D8CNVqbxAEi{>VeNc)|%&HwLQ?zKD4gc8s4f;?#
z@)H2{ult@r<!T`IwM&l_TR)4wVS|OmY^+ZP8MiB*5gIBRhdB?G|N6|0Vb!0y4k_<H
zzHqT*%@7WN#xHGkD*TrM8f*3h{|ow&h_0fxxXm>MdKIPIL;0NEW9k<7AU=m8nA4ha
zf7t?qH>Y8K?GP$4!ANNG?Jx`&;a%H`@|<`<Rt2=Qbh6A`vC2bmSAP|J#kko3q)AH;
zf`%0wa2hKO7Fk+Pbfh_j248`U|1tX%a`4(Y;_@xmRMMIp1+kfc#wpGxN?h_&KHt8H
zMJtPzo0WR?$rj$<W&GtIx5IIBVzJ+0Y><TrRFFP+J#RlBGwCl<w@PRrh@ZrU{H}!u
zOyCm(;&VLPQyc%wHdrrVMJqiWXEF2;Sqii1I9OaCufxSVThE~YP}$?e`+>MIb7}ve
zLYQv&pz3A}5ln+O0gA4AVRlun>z)~{{-{H};tT7J_n@}L8qk#Km0Rm1Lxt52>V~d<
ze*4hmn5Av$xyLOAXqJ;`$|Lq}OC>#xQTf%W<QIAx_z~Kdk=^V8_@ZQ_zItCr4+sVq
z$I%RP8%Nn5_kO+}U-_GkyUC$2U*P!5r{rxua?26SaCqd17%%~tzz>{>8rVA!tcy&R
zy?nWRc@q+s{^xvLXAy*rrO`|}m(q8K!AYHIz>GvM3B0=5ih;^x$zn3dPLCr8^N|SB
zWSfDow2QYhVZG{{jG+Y#%~{EWX8J#{NFF_h#b>|~w=kYoE_!%g`nVg6TzYyRgn$aj
zabycvB{jmK5*IS0HC)JBYw1m$9@MOCfZdpjZ9QW4;y$T*QUI0(Rg|}4DFZW9JSml`
z9O?L{wWnW^@wx<Ru<sW@?tz8-;z3ku2JFX)tTDsvrEMKBc|2*h<eJY=5R05Czf~-E
zaDSI)Vpm2tSsFmKu`y!P{m&T=R5tj)&o?zME%GOF153_@wWx-G2ml4q=H92!RdgAF
zBTqP?{TRcuIf011oXWI1LGyaaWVVZ#GoOw&lJJ_HEy5UNNho0~-&`|{fm$ehVw}Xg
z`xlPNA7p{h&>JJ25pJn%g38e%VXxmO%CG=^y!fx{Xb$M_$s7?^n#A-&`$*6@l$uPh
zmWwD~t)v3yist$%xrhQ6{bBHFCOz)krTr+4Am!P9jkrBOqyP8cgLiC9K5-3^nk>-?
zbx=}j`dJul&o<9&RFAhcf=#Q;tDtOEXYX*yq|7}87Nf8awS_ngNgw0NcO_r$_h$eK
z%y!+Z7eWWdR0bI61}l8W+;cv73n=9wXfnVFuyaO;2~W~EtG1C@LnjovA1Nho&NN5(
z=r0I~5Jurbet#5UYlJ3os{e}-wn3O;JB*!&vV@b`*B`hX^*p!9v?TP`<7yJP<-ZBl
zB#>jpIPCLvBWIxT!Vv~<g27iTJ<ls|jsJkmE!X1YPG8Ss^2Md@rfvw9r_#GSx$`nq
zItg|*TBpb8ZfKO7WFK9^9&K0CcpJR4847@%0yu3^&}NsK$5(=DVR<!4cKdPI6EtA}
ziB-Jd-{K5<SQ)RAu<&hxDX3l^WDi-DkC4CvH~206L7vN5P(xl*(i+}i9FOEZtMM0R
zK=v&p&`$}^#|F8Rz}zH$e=~y6$Rr+93#6CASI*L9r9HuWf*_yY+rvYxg`JatgFi!c
zLQQDgTPeA**#_jm($%<~vGXF7YeUd+QVM`eT_Dh})!i&NuQ!?9t7Gv*0i<d0=a$;(
z8U+Fxj;fbne6lS2<{iEAkZ)48(?<qq0ams*k4*MBQf8Bnox7gv6tbw{lq6u1e*L`i
z7g5p<=Xph^)oa0?W?muz_!Tqd!7`B@9N8^m!0GdC_D4MJm#6K*L2?U^uL)ncBGXCV
zz597(CDxfGv&s?zhQSWr^nBA4@meo}Ns}d7Z;i>3G}Lisl(B%$zkH)GY6H=)kwj|_
zUv<ePNeKh0y!3NUqcRkTmQTWBaW7oSwoU03xXcf3a*Vm{A<t?$ePutxR~b1AW9}E)
zD8!IaJVkff-DS5Ktr}(!YaA4~_0*@$)Sd50v{7IiYeoFhvy}yOt_4Sgg_c^Hk}60&
zf`eg+({SMC2+fdp(?b=oLUv2T{{q$d9EWa?3ms7rbW<mx^M!21h8FFb+@CK!G9*s)
z3KcYZIYO)2Yh-Ba3Hw0+<}D;W54C|0SN*;z7BE6ymtS9dpjIp^fh2A!*&cHilT6tN
z`(O&j6Jkq+5sUPm=yh5@zc`JJ!4u|Kk<k~k#q>2F$l5hxn(gdmNd}mXU%DZU#Zvg}
zr7l%P6SCnKz1DkLkBsX5Tsb0i9O@TgNUHr;4MtPobb;ITG@Fs?g2mV7!m{GBE{QO^
z><z!iev7<ZP&k)YNyX@E1cuVoJjX1u80_8t8Z7|$7Dad{`H(owXaX=Qu3X{xjbcyo
z(!ENQ>tuTZ&>_l0B=bPvdE&H8o-CVh%1!HjzFxECx!*vcI*-K1>#Ub){yz1d(s~_U
l)+eFXb(zMy_9<82QlB(<9SkrL_UlYak}vj#usKRjQ7Yy^=&Jw#

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..814a55277422d93ad366a6ae4b23e8b5f99f8e4d
GIT binary patch
literal 24312
zcmV(lK=i+h6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+{lq8tR
z_-An@&$PpbBP&~}@Ir}D1LciPYJQYkg<&M8U)&y5%Ubj2&-A;8*hA2VL-&&8ZgIkp
zfoM;RrEN8=oLuNwS9{N6S>bTl(4BO<xU4&xDnq-g+)qD~RS<GAz*S*0zVVR_VfP@^
zgmFi;2X#I2Vkd_$q^)THMqDQIVIA4`$yO<XM(689t~f@kEbz-`55t6$&IFfCFY_j(
zjy{tIU&20YCe#N~<)}h9N?}Zr6(IOf54woOBE+`%iXsEJPr%0WviS&aOiD)o;0%>U
z(>%?}Lp?9UR)9Zyw3wm_&8A0IDW|z(jf85S{TPSb&3HqUEU#MU2io)r51Vila8lLf
z_<<Y*sOxP<Q(`H`h(+p_O{~=%WwllP;NVh6N7m8@*;Vn9A>EGgklMA>dpHQOL|^!N
z7gESRMYr;v`5yCnt8`k#3>RQ(?}3$JE7pM~RlPd7%!-RL_INwH0wa<lH_1u&yg~RX
z4758@V;9>{T^=d8{Q@8}ZdUt%l84F>8A=mJLz}IOq2d{cVO0#Si=bH+qFz|D>*!Bp
zCz}o4fnn0_z75qTz?+5pT%vga(bLRL$LZZO!r+f^8By0HGt<*nJUE}BMW*gsHaE$O
zIgnWVXqD~Yz-I2aS7&d1W3n0{t`B>t1m52uQ??gv$1d=%8xRcmMw)^yA&%8XZj^4R
z5m$7$W>OzAX6>94>0qZ@rGG-b#&+O%O1MU{V$?a+w1&vZ5@R`4$=9!^!qCwtTaVlH
z&Xh_MFrSDd3)EU|e(>?uULFAto;lu%G5LD3$Ky_x^gPM9X{r4X)>-8vt$${CYse__
zo`}ayX;#Sp*mQH(xk6zRj6~{&GT87#w#=4<>O&MZBKo^^wN%Y<<WfWE)<5)~s0B#K
zl$~UMI70loLD?|OD7pwc^|%vA<wklUlRKrd?blxN?zNjB5N#9Tm!8bX`=_GotEgNz
z$xTK31PXGJ_Wj-H1a*QG?kA|W`pKW_>N|H~PF#On*C6`8K@kzj0Dv}F-IXnWj%wbI
zQ8R;0m@5)_3D{c@>YkBD8t$>%W5o8gPG~flu5&~q{()fYVI9)FoVf@SDN>%FMi-9$
zgB{Kg$Sf}C5#G?Qt-{)<UMIzI@Bv+?b(Fs~90jz?G_t6Yw7R{8#@j1jU2vnLoBFr(
z`b&8^e#q3pWKKQMD8Ey2b!HKgfBEI9Y|@rEvQrR*5g?|xAf`voUG`Mh0Qhj=(aP$q
z=(JYyZRiBDs^EE}1(h03k`;I0)kSSr&8s`ZaPx=LUO9(?NI@37fefI*i`yVFSTDI4
z;-!qG{(JP?lkFm^{91R7Sx){Berzb1WuZx3I21eT@&$H%cSF+9C_qSPBSX(hKA6M0
zT!4hf%)xFWSf1}Psf?F0ZU!weZt#yn-nP%Uj;82P5#lN2J1&*%)uH+7C6JhP6(*6g
zH_1fmn%$vRQo>!3)W#eJ(ZdtzbA>Km2GIJrsi7A{j+3@0hUMkWTn9kYw*0e30T7yd
z*G3%D6HhsH=nZ!zDKu;Ih(dEyJQ7(lIG@T3<B;CodX6q(uDPR8>A*-veHWxhOJ26+
zi)9D#vhh}LxorF&6?(W&ZFKtw!7I-IUVz{Qx(N`DuGsLQOcd?h;6v3w!js8l!{zCL
zy&Wm6LQ?K}oOGBwDZu+v8GpK<a+Fl(=XFM{?Y7R7TEc0(9iJ!i+Jom1?73;sKm6BH
zmcpU`u@>t|4Hug)#SiBIB#zhrIdMvv+alH{>zC>Y=KDN-CCGB?36yDjO?=~$Uqj&<
z3zrlL^v6#WxIx?_?UDE}nC*AUDPL5e#+g)_Oe$}fRqk@r;}EtE|3?4S@ts;nMlYMF
zu)+T5-FcD0JChU<&o3&;HpiXfjrWDVEy4yG8IYGTH!27RYZ6gyW!vNF1q4f!Ul#c@
z{RfkXESkiMiZtXs#!^zR)eSV$a2n*k+^1u@wse00F?;A;Qr*iC>~fMzEsCtt=(}Cc
z2`lw2BMmiA21HDx%Q%Kj^+TSZu%0=0h7cUv8MpTB+yT1BGw-k32X%f_b*vdsqc0xo
zidoYLVw<k$y7nfY?0s0Kj4<1tOS_JN--hmQ1e}pcYD&~`fBua+c?14?1|=2Q_UZdx
zqA>tw|8$Q-g(2<`$P}dfv6PNowgN`Z>_R|ZR~$CJ1{&HuUx?^9D4iEg`^g+y%KB_`
zFE1q4lceQ}L}nf-eFXTTyt*Sx`0&Fe5pRDhz5it4!%EnQX8;rgQ|uUtmicZO6%yKn
zV|Ta(c0@WUbczFm8SfJmb|Fyg$284%j#nLb!D#1?2<-NsH{#HDBx4D+LvArt$jb|I
zyB#5}D=*h;A(ti|GyTFI?oyEdpO_om0`^2GNvdu8(14CTxX|HhUZv@~sdik55~xm6
zmUYr0F<fS><n{<>kC=6KhsR8ggPSnQ2eLbz{GEi^E3!c2j~y8jXHiMB+zw3XL`0=O
zq}L;xkh=uIc;9!Cxu{>XxF)5dxnV4W9uKL6?eV4AGUteIdb_!}-$!!(6ZZ31tP(K)
za%dC0lQboM%K0a8Jf)m}iJWXJ_2u?Xx`G}zTL7SB3S;L>mqx<Fv~RpSsJe}GtRqn7
zZ>?T~n0Y$R8MU)R@HxXA_f83g{BL7ilNJeT0oAC#*=TxyAf6q-`hGhavfP&U3tWb?
z%v?GGGp2n`r{6(p>yL|Tu8xm(dD_=tz$X!A<InD(S!Kl|-$1(#<S_Pal6s%>=XyA>
z5M{&|{xeuOX*T8<EpL>J*)i_)OYx;fMU0=DGGKSMmZH@B)E|pus8M4fyfFqHkFc}@
zLC<uCd68E08f7)lZ1BD?tl52<gR|sTG<~z;=j$|7lXek$&EiupHo{lt`~z}H+*Jok
zFPrGae2JJj)6k3KsT*r{r_#X(=WdoWfXp_W!NmMhtyybewgBVB@w6p5+C*oOY6|el
zqX@6|c~$)(5+1fSPe!1CokRms`)$8umVLX&8jQwy>TcTg^YXB+o(maa;FccfV9pZ_
z*59I?hNIr%bBR_QRvV{6`dw*O=TB&?8KGva!nf=MDTv{l4|b(g^1LtEv@k#mpzwGA
z%KGmmV9+IM1kJLm#H1w8u7X1p%id??OvwpKDk7jVLMeZRXL8>w2jDnS*aj2QJbp*i
zHW{s?0pCP&obkDwLr^3QevT;~*~<$gTWfXoF|)6gXz_EA9^juL^v&2xc^=jaeq%>S
zMDbouLFNYlRQ-fTNC{9HzhrPvyxSK8CNIvzb^ewV{=!$(E!eL#!cC#5O4AVW7$T}6
z3!|d}V^OTO71A-v?St%j0t!rKAP=j?nwva3W+K(G35O0>$ZEi{z}2XbYlGnEOWD|O
zXfW3A_MA+OD61qhvF#<yz9uEbe%G#meb~QPDuen~`O#i%>YbD7M)y+@Rb57j#>~8j
z6NW*2rv8K6!{o!oMiO2}87Qt*>?9=uvrZ7m0Err9CN{az^@0%a{w7-6<=HxajG2Nb
z-A7L_Q_5)-LwPb_&YB2@p888pLJN2ZJ4oz3+eB9+t1$MwC7^JNb71Oct%z!xP8%ny
zS)0Cdg!GEa6U?X=j#SqIPU1CQ4Gy}W>9)(-OoFamAYH_YlDWY<)$e?{PaMed^u<Ju
zvj3*okvQwOm22sAjEn`6BuA;<0@B3I@CU6C2`1SH|9C)7krNx35EpvsQ1tfpa^^}4
z6{dx*8jOS%$20DPI!v!KGg;VxYh$|e6hhN`bH0+BVsE{0LJKD>3}<7`e!N+W*jP-i
zccl)RiWhxl`75X`0O5z*j&;nE+{y4~QG|wR8+8%##6IfO%=of3S;4aSY+OM!ZgB-0
zX`ciSpDT6(3g9R(!!#%9IazU2412-}MarmVQcTafI5qO|cQ{bVBK4233_Fd-0>|7i
z2XGr;ups)Q$HaP0b^x-Dobs<{KzgE($-#D|pZ=&m#EmG{0rckKZ0A|v=86QQ*&K|&
zzf?Mff%Gjc8fS}C#mc`}dZZ-o2N51*^PhzL0lG5U(WxG|+e@GXKgeh5k;8vJXC%Or
zmU`9ObN4l{rWEyv%MQ1qGlwwWv8(=-2Wl%PEkwgqN1_ikkc;s)v}4Y=CE2Kqz<m?^
zP+`9e>)xfg1C}c{TXhAuQv)+y;fq2L{oqGU;rk!lM^moy?i+UQ!mGZ`=;lt<QM0!1
zFiwG0(yo|fN$`h0zIOr)%1W?n!Wonu=NxZ~F}FL0YA2F}z%CY9AG#==Bt?X|qbd9g
zScP7^EI2|8o<cU(W(zmFE^p@t0g7a4*Cm}z{Cg~D4@hD!c_<YM<}Y_*F@2B}j4qEW
z`k`!BG5Q#B?4!jm(-(B^5bPMFrd!Ed^2=8ahBrF@Z91@ZIWKETQDTP%Zoa@1Ta@UA
ze;tmIkLL8ha*njC;&rry-qV8zBfJ600;SNnq<9epKAM%`6!4P<#+?9}^mk59^RdBn
z?|aGU*RQnc{n9nCgmK3elRhVZ<P1vd#1#(w-DUy)2}ulPCd=R9`OEm_3>rlAI(|5<
zdi%oZL}ZHEbF83RUvRe#A~`7?W#JIC^!y@7>9|W5YOp>=*TvF~2KG+*FZe*T%(}-F
zDTXJunA-%lRwQ8v13wZg2A=u>i*Kpf+lar=DI$R5y*d+<+5T&0e|nVBlfRN>`V;f$
zUAEgDT`D|7m1ftpsE(|Dw*w%V;nT#S?i!=F>YETqSgHsj_Fd+1pKuCEzg3MqS$ti@
zWAHE2-Lea8Hs`I<wnZh%U?Kr+ILN>JJOasGsM_*<yu~$LO`oBFZ;Xki<2OLOI#wgC
z_4ct>v>IjAe9cKCzem<0QIX9NW|fjc9&Yo)OXZG=XFa!QlLY~K@%*<6PsRUH<0XPl
z&~UrPFaAop*bPgNJ><Qk94Hp^zl}0aN&6s+Ik}9cMxjS{)iZv3CkK`2d1f#OPSwb&
zB7VO#FL)TWh~VG6h%;xzzX{T5{w%b0xY-$)SQhC&A0Y<%PJ{XjZi{kwm3jcdba|ul
zBFWRcN_Cv?euvffRmq_GlkWxw%FIA)lDi?!l_l*Z&XBJREQeJjo94%{LZNu*UDo7J
zH#G6Tm)%!hyG~xmrOw&0s$rG&*U1OoOBa}LBIrPdvWXHV0u@<jikCC+3QN6->jNWY
z%&qR8F>6;rVN7;F9^TFOZaFmyhDR}YE7@n62s;q<552NQ1$>2TQh|Q4xqTx<HZxe)
ze+B7U0fpMUI?y>-^t*>D^nnd|I+zRPl`6Hi#4gl%zkB^ORHw(YDVh~W?<*a-gX)aA
z3BY^|P)c99c+^Gq;1XOGzMh$yTe`BCKfKAe4Jt~(70F|pTmo`Gv9sN4)U*F!RV^n4
z>l9X47D1Rn7bX+ib42I>uJ&Eg=s}ancqU#3Rpoh%r}+*bAI=LP4~HU5hsUlaTYKJ>
z+ckV7mO)u)N}a{ijJe@(wW;kV_+Bv)?V^(kUOodCs@-ItHA4_E?6@MCDs3(hsR^Pt
z7c!`j)CZf(1_3un{@DF~0$y{LT;J>(0k$?KSq|U`kbdZMX{-+sTx)UBWkT%VW$Ghd
z9|@w4g=EXSbFNptL3v&!umaJ791~>Rt$ah;sdwwPmt!+YK_71EMIfJ?P#Teg(T{R-
zN0L$ZPPOijo2~)SLaCtb$ONqJm)<x}2irrIg7g2{(-VX@eKn}qFLhRSC;^$1$c|8;
z6OZAK(bQ8nBB8oS@PAsv&#D|RslijjN-;d#rV{FG&|+F7D=*kLZ*a7^_5lJfXe3>3
z6}m)<Kb0dAK6bhhTUsYwe1k>!NATCwpf;JLb{>SJ1^m|6DR>aAiEjkP8D=usArTW1
zm2XCGs~s$(gZf}h8j6oJE@)ryO%+}uu8+6U2U{(@X!0IMy*baNjt>rz$mRZtH0y8*
z<C-$kxSyx1pKlTLrx-CBUmC)H%`jD{uj1w}O@>@P!!**qiEy)7Aqp{d<d@`QWSZwN
zld0mBP%5vJE>nPxLxv$Y9Yq=VZHN|A+X1xaTe0G<g9>=@zPFsvNI~eUDyyg}CL!Qg
zAEPeC#PlSgoH2`{K?!E$DEsX_OVrbLtK@xgI1C;~*@Ro>7>8Wd!BBgGsRn@;ELY)o
zi==Prd`{5fZQN_D{r$ZE9my7*O3!<@mz^Hm_WDUN>^n<2Z+bd+QPxV)2Iw@cBvft$
z&K5|{8BO;|8AB+#pb;!cUouRvIkoSrc(c4$5i$106|sc4!&Plu?huo9rC6c7@=IME
z+O%L4%4CBz6$oPlJt`5SpzbfZDHSw-E090Z;7kfrrklt|;4T+6+QW<{o{+9AF{h``
zBiD(gG-Ui19v1&bB_;`c@~Jbw<DOK`kYIRg7oM!_mc9dy>T@$mP#Z9+Lda19HJ7oI
z%vff`cMWHuT~sR*b+i7lBRbC%H~1^>!e6_<qD{oZBe(t|s@QYOR7l}7{D&zVA3~S)
z+mLF`7`hy;+kOxAJnh|YbTUVNeY*I1_+aOT?#>ov75EnWpj6*!utoldFkr&&IP|CR
z6pZo1Wg~9<iZkX&whNmX&L;SCHE9_eTeLePgi;QpabF~C>rp{gat)T}$93;XSozHl
zO@$j{>wh1~?G5|AiXrJ{T8wyiqRJmyKV+!$(<bfJ%9_)Vur}j&?tu_sT%g@Hjuwe9
zv1OaDV7&CA)Ae1mDgOqv!blYB@!H@`v>_S4kB)B%5fP^E@xZ!^;6_k}p&*RXV4sB^
zPS_B@gTpMQOTr;chz^tM7H!T$O~{Z$M$~L)zGpAYtdFx7c5nxeXV>TqtC&4x>NHQ(
ze9%R73>Xqu5px}%=7^&ZNCR4e?HJc4P2|txDeub8s8g?K@XIc67VV?n)yet!lVu>=
ztF~DQe^Q%QAv|RM(}v6%!=Z+NvZNe96oVqI3Ta|(<r^xQ(`V@_LGtCytow-oHWdhP
zUpRDT8Rm$T>R2z8pQ9c=y>HyfSjU6E&kpVwV`8Y59%IM*5vo0&8ih)Fe<?d;*wWKE
zk77e3+*B_{d^ko8z4;LZpBu?gCQ1q!PoOZ}hLY8O1w4f2*2?)G%UmaQ6^ZNWD+cp(
zp6qg5&fqeA5{Y+}Jpp8<zb9qt_plkUworG^vqhIASVEX!?6h-EL=KZ%VB3J++m3zP
z!o##mTmmTE)-(@IBewPllKs+HUzEQ`PJgEB`fohS9{Z($(&KTZQ4NF9<Hn#~dQexf
zHhh(7ogy&JUdr{-7<<e3%f3++x}va$5B6bS<$e_B&yNr0!2nVZ)bnl#xE;(Q+?SXE
z*jMU<pZiF|IT@|qS%6b8XXrk>2j)avkpCTuqC~p|VWaWPoaLEL<*uFh{0NVOm;MNy
z5WBo$n3<?kN9tocuyiZQCkhjB6RE`ob6QV<tQTOHc5iyqGgvbz=JdSvd$>dVb_=$!
z9Fo%l;g#?c|A?lsB3aV}@VaN1$ZY0;<lfEZ@S9^If+;;NdmQ9oLcXzLgc9eRd+N-1
zSFP)fv5lU+sEEA&Km;HwL45+R6jPSd`<>Lvif>)l*gQn!&QkBNML+7Wo!e`sB0a>7
zqcD*xDMq^+*exlYtVm0=Eqmx+oUwX1CHC(+@=EWx-z>lm9o*d}Pf*~&D63*#)gmgq
z=*Uu$9(4DNGf&(fJ%smG4EIWQdq5S%PYT?13<{i_$y8h-zbRV{56*58yhG$aJ@pvj
zq)!G%(9?4Q(?}txEx}!InAN=J14aSW4vGX(^B@+p4gQl5S6R&x+grZ#%u$pVVtxBd
zp!1uc-AIkQ!bE1hBbfHuiIo9s3iWYoR*f*2*7xY?gDZtZ5lY!CT;y$cK=uIknJ$%0
zvj|j!$ahN0V?*=joIn>h1hKU5;|@H1#sX9ZHIUjv3m91^#a}S-%~sIlcc=v)WWNjC
zEFr-F{`@a}G;Ni+-0^xp9xAL#+3XgtgB*IDKCgO!&8)ZtTdk{xamrEb@P<lCj<5ZZ
zo7#PDv18&cGWANTs7F_xka4F(A_vH|5*VBP`uc)M7rYdzQG9hg=l%WdCseS+rBS_!
z)vphu|BZ?}^QhiL0dL*tN;#)1bTJX*@69E1gyK-(NwihxCNj|P_8|=a9Jcqt(#G(~
z9F-?{*6gY|I@IR98>X%Dz#P{=(FWc^Dvjqfv}Vx~W+xCH`0%)av`2~J;hz|yqJGOI
zW?-LUd;HK{bLG_4O|LtmP|Qpw5c4aqUADiALd;(-K^|8XA9njWP&|wAf7)j<MM>pd
zxd~lUD2y;gCSPPrm?{91L)xa)45W(xnvTq{HpdFh{NWA5q9cML7k3NQ0gD7M+NT_5
zQ|&igToUymvU}E;qvTrfS@-!C9OMJy3d2c1FXq3Z#47Wnc7{ckI;GG_*wz0yZ7-6y
zP96V_5GDDjS3_dAfJ}}ZE%chiP)<xlO?<oA5VID(jRCwAbX{c@vkW#u<K7;)KqChf
zuLVOSF6k{)29_e6^`2eGrtJ=Ft>UHUgoRlX#gg<&oY*XAqC!AXsX_TJV~G-j-0Ow(
zUUY}Wx#3~zlx{ylgE;;|3IQ4+LWh@tRg0?D7WMnPwl7V`D8|Wht?pQ%U2?nFw5R@q
z<QY~9YHIe<K8~x9<LkaoE^W6HFHV@Vmq$##|EX|@D7AXmMqg_eDLQhCY4fk(CL`g{
zFT7_H%aoFYsP)YdGpId`GrnEi4=Og(<X8dwG~*o_Iz<dR@cycNUF`IlXk(e)vEeUz
z#2UaU@oF-_aS!bk5Y`~j7^m@e@6c8K7;H!O-lw-RSw%psOqm!Vo0g(f<9K4T#p(f6
zD-mybnCj`CzTfpacsWPCn&m*p?ZD9!y@YVN9a;q+I?S8hn%`G0fx@k<|4sf)>@@g4
z@PM%c)!+k)@_(26Z`p(A1CIZVVBPB<3!fUWMBhqFwvME(`Rr_>KBRo6K506)+^t_q
zLi2@+_>NwI7&XfeHH{q1#~0;}?1~9|d!l!}gsl9R?7%tHfp`YnL7)DQi%rMF5AWL`
z;^T|PL9cyq6YJDZLjz`v7tr5QwVFn7;huk6^ss@lS4DB3kjjk4M0O_??9_ugMdlv4
zr-!??F~^7^gwGtP6X>j{#rvUfR8!9|+6v}Y^^AkeotKukru*wc7b%H-++n;%Rz$Zk
zg?UYK>m*D1N9vt=JcbT~YMkv1aZDS(fS5zQXdzKm4$J#3RuF(;yJ3$$jB4R)j;Qq?
zp9E?w0|q&Hj;n6$%Bm#Ix;~Q3tEO*!J{-`I00h_LXKO0nhj8fut-{XCxa{Jo1`x^P
zMT!wccZz$r$T>_=Zl!%a8-v@Hew4vgtucb`ZMrU14W|!Nms5VA!C!8SX$pAC(wkyB
z@~1}Uty#FX&C%5_hm5)*R+)7du~wN<tpAFP&k{5D5stKDIeVmF;IXDXxG`!ZjuL;A
z$3#38ZF%CaMhMv}$V$5+V1O=eIod+q))eIbmcoppB#e#IN}$){HAc6s=Dte(L_;-n
zK0|7Zkja#10%$R|+G(HIeYQ=Nu49R!@p1HlUdmZU*Ro<vrZ9T=9EW|>LiaWKdmAfX
zsVF3erAwf|;lF86+APW0S1U!Plw&1s_#r<p?>-B=#08X$U5f<h(_p8H@<qHn34i}a
zElST?VBP|~1wcuOfua2`7tgsoMb+H?FfR!Zjw3xSjQxr%vNvxEeIr|Uzgx-^p`!a(
zYP|iXC@`atQyW$uxRqy`u=7IyD<yNr(8~-iKr>mjx;Z#>O|&@(<FZI}DE%EP>60Ou
z;kD`?dMkVy>>*I`yZddPck6c;F*^t82INcU<qf<~ZW1wtUo00GnB26c=HxqSkw{c-
zLIY~<z${kjqx36>QLA5Ho~m-Yk1s2sbF2IAqXnLYD^ByXCG_N5YHmdY-T3-Y=jTq{
zITMREu|mYejDXi{!aMSfibcbGgpMUzhe2wz!W@8!$2{D_{<mO6_$nF}7>*XCRR>t;
zLrY0rlS#yylhWDAUb(H|MxU)ws?eF_p<!PbTFDD?$=#T8A6?Cl=JCO;z{z?sY(!$3
zem6MWxoVFNMIUtbDfAP`9RP1H_07kaH8lc@3<b9*G*sf7c@q`FXpHNMGB1Cwy6tjm
z;WkcYv0Jb5$42vqo4fn>ZxpH8a*SgaBDy>CJoVC(H`?U`e<GcoN=nH$V)^EBw<QBZ
z%06qfyYb%LVb4{sEy-qA58Fgdp^M^#r~!9@v?jWw(&({6YT<rjV;MvhE||(3vhQ=6
zaz#*c0}BW;jkx7PB_<o?|IOPM`In*}d6tZ?tg?y(26jW4@GWSda{E-AfQaZe9wDg(
zI!FZc*DC93+fi+?%82PzuI6mV$=%RZVs#on)H@jsVG&4iTVNv_gTd|Oe+^f0T7g`B
zW_0yTkkN+Gw+VA6)Q?4kDxArl(zaBWswDWLw<@ug*Gpy+P|F`&3{a7{Vm9}hYPkk|
z<(_*{sjG2bQ9ug#(Zb|S9oy$)SA6mq#!=&u=JUm;S08h{>#_p0f_`^;6$F=NVa%J6
z>?HHuULg~yb5xcqf5F2$ibr#euL+qrF`4&uh8`n>gO~f4Y{D5K%|k1AZK!_i3l<a<
zLb$Wiq}5QNce_+d6=bd>J*A=8UBrYKCBIxJ%6<R|bU9odL2O)IzaH+sL)~#78OVUZ
zI)DsDNK$%A;RQ=cBbh&n%p@Cl2Mk3i%Lb9v>w$IOH*4D#hceh<%u9`=%s<Ni4{9ii
zNeGBk0Gqv%y34(V=S@>zQF}vmr)f-|`wj-@i?~Z5JtCyO>PSmB^*G({RiehA`aHUb
zuWGYTiZ=OTK^8%lB?ac<YlZ+DWx4;WU9mfq=VnO~oP4}HL3jjA!3>0+kfpvy>-j4C
z%1Z_9Vy{n}qxYqk$!J%JQbpIgHHrI&u3^yGutcavp#*Lg*F4p|8vAeUAX=3QzAx$5
z(qpZ1J4246%z9qUBu1NMT&%gDJ#Wq;Yeq51NPF3R0?@4dJ#60b9UV_G=X#jeNhCuS
zK$FNE>@<1POfm4@4xt7!sKwQmkq%2C>1WFH0GyFT@&K3uKT0$${rkg0ThB*1xkg|A
zK5;MV@q|8}EnfXOHRaomVO~=B3^(+Z%&fX@Hiidnw8!fpC~gf^@`zq>><fcQ8@put
z1;V^>|H~2wAhF2J({5H1ddgnH$Ex2<mn!}v%Ez3Adn3&FG|pw~l`LW6-!z+v?n(Y3
zNZ7bDkftdE*D-Hj^L~j9kx->pHtL?`HQotFYhEq9Rv6rLO%~`UznPu^e-ahos1rxx
zxHMt~4h?t=v8{(-0E1`a3k%OAjCfuP^IETo=ouL8It4%dTZITX@$Jd?=e=;^Exy|u
zlj5u-1o>-O?l}fZ=aI~7GN0E4#x7CdK>#Q8)xh%|1SlZ2fAL6n5R1aQ-DHPcKzXXv
zS@P2X>~jR+Bw;%)L|_k~Fr~s9&^RMNump8-(-7C`@I(oSkFZ$tI+Ne^WZ|3WyzJ#k
z`n>y8g!8)*j6CGUaC}d3#ZE+ch)O)+mdrflV_nuc&^FLGj0nSj_6k)%aY+r4lIF!<
zpI`DbqQ>Eiz(k_IX!MN98nT-T7?j2AqD;P=!b!ybbBS@+Z7hph^_J2c9YhD<G;Fx!
zbz_Bs@t>_;l;TO!NE9h5dt`rj5X()5;frS3b-E7hQK1hTXc{q8BpS;@7{5w1DDDb4
z4ZA>Krj}4G!hypdRS>`w0h#@>IetYWvl2sSNdTsBBJ5WWRs|0jU?v==j$xa8y2(23
zAAIqLa1KN}kzu;f=&LL6N`aavj&71NSrPQ`4e|9IC4(TuVweG>hblzr7~?HS1+53p
z=;0K3ZZ2)v;;9N<tX@idSpGrbOQ<BO0OECWP;R<Gpb<A-&2{5RiXB-qgezZm3JC@Z
zL;%Wya%pV&m;2=gkAp}nZNO2?TrDSq94`NkcQO1k!9LW69TpP%O(4V5WkOkv;VgqI
z!1BWD5tE<poan9l)(vP)A!kAoV?aevzQXMLh6w~$3}_qk7=2G+qrJ|r00zF<D`B%O
zmfCZsex?b2)DO_9l|qCdsHY+l`FF?;k+cFb2G0^Z<OqofWDG3-ILarqV5o9g3rtg0
zWSvFXBW(`o;4gNy=^$I|)apw9k*<TbD*Bgy(KH8=DIZmeq;vASi<O^2=|dQbXtlPg
z#bD*Q^AZ|x-@bq=_9kS%a{<kgg_(8&q)&LU)*Qy;-uO#N(^bKkwj2L-hH_2Z>Q6XL
zw37i`0`|Rn=9%EQ?q}kWjnoe=*k7BNNva$3jp&KyGLCWb3Skz!oKef0AtU~>j9T!y
zr3K_HkRg(pkR>&b$@t>W@#O!7r^o<87Rd2vVe=VMj_VoS9jCL$tQ<4FgXu;C&X)1}
zZ1m6!*R6=#qH{Ma5nHBsC+I=o@j}d*B}SMRw#@tU%9^v0FIt(cG3qwW)N+f{o-~(p
z#*r02LE{>@RmTfI6_(M$^lV(1^%_=?pJVcV&F$=Y4|*&ofDS0wVl{umXU;dmgNEb=
zMxeBwZL?AtYnkpqLrD4r!^S?fhIeD}8#J-AZE|Mq*719T#Z2KG1THXRI&X;OUWnfv
z(Yn;REO?xY6lgG`2HD2KZ&{kt#y*=tbAw|-`oml5x;rk4&yGMr$q-^tRd&qQ!hxx3
zyb5muzO!)bk+Nn(|N05xSw{#36*DFx5a-65*NehLYj|I=_FjdrJ??Qpi!|DU)+^W}
z0r*|D`L3BAot}?*>;oTmPBW2H)Q=1ye1t7Gwt3`mIklvG0h1yRA+^=K5b1)xa==r`
zk~C!GXQ-{EuD*}2)DUzz9HiZ1Z7_oVUF^e}Z%!d_Rz+eGmOz3_p8J$m%V~IuXC4+-
z=l{CkEVlz&B5z9YKBk+^qp@SAZEDXfGIpp>%wcFotM19*7IE1rta8Q!UTe~*B2207
zcCS)q^#%r8Kad(}^d^%!*T3ckrdcZM-t{0j9_z_@iS`tlRJs<$WO##B&Yjgt_Gy*0
zN#m43gl1eY)tZrU$6u=?s_rv<Q|`YjD2px$PVoyJbGB%$Y@0!Zs)n<ly{7-vU!Yd5
zfX_D1-jaTMHi#f$I<WwZ13>{;eB^WD=j~D}G7aT{t8@q)aC^Bo1)EnG(R*6eUk3+=
z!{?4eirHDZiT<)Q+BGOCcEE-yqKg6<Ek`(zd8UBFEFaXPm)?SJPCrtb57PJm8S*PB
z?k3<ZcrrdE4Au1aC5qjrDYj&qGx#GTVgAJ11OMXY?6p$Ra52aamE6uNX>Av$Y?`}x
zPZLgUz$EUa+;1u_Bnlf6HN>(h!U6Iq`+LG5oHL0sNzEpablhx6&SjuoncKd3m(FXZ
zMdJz(uLpoNR3!2VJG7kwRL5_8fWh@5w5*e3!e*p!J^cFkv?ham8w5?%mUy3t`1F%A
zbFQNHET)AiJLf`OI{O**ynVava5a@YXh3b=LsXHXDc?U90??SMCpHE5u56rY%B!>a
z6&CTd8w`7`Ln*0d@DALu+2VOQu@54H3+N6xC;s+%Vti8U%2D?*LZOAA+0;m`<J8$A
zN`CyPm3k=?9{W#j3zm`_T(i=EU}*s#w^j^f;EJ??Z=+kI?ZykI>u%tt_R>ZUJ_u1r
z*t4^Um@ZK-)Hs|%DZ)`tF!CFuhy`m|QbW}Yi!XuZz}zIy5YLAZR+@exurpkDATB9-
z5O-B24L^~{%jiwIRVq_JTkltoY9%f0-EsCP5x3F{@jO9?>V&nm06axf5We&Km>Hg2
zJ%PlMN$N&HW)MO*>o$|GlA@kEz~oTSiolt}fC<c~)Ex;+hb6}Iwp>&H(CgOxVQlY$
zT!Zmr4$@W(SXf@KEy?c`D4#obFH3$I;$;*%o}7J9d?ch|*%d3?vx}rRQ)D?ZR>Lgi
zaZHQ&Z-MvhTRCdB|NXN%{<i(Il@|r+Gw+ZoKQ`1eFJBA2`!4fLJ~p{6onIekSbzh}
zhhJhY|80!T5cLD=@9?rJ1-xY|kk@uSJlJ|-H|nw7JH+a6c94&2L(C4lZW-ew#Ms~F
zXaE2z{}~)4#9<5=ai#|wsZ}U7tJ1$T+(hbN0kmi51Ezhr{+**8dA>&K8Lyd@6GuC9
zTNVAOASqy}VYvu*VR9H@MYQJGHRzm>0sAuU<U4`T|7`n4SB793Q8Io^IzxQDpQhLP
z5I8#+NNe+s@80%be~aq;nv<JJQy79fZM5OK_+kK!3Xf(7r{@e6A;f`ez1pn|xsP$N
z$RN_2(tveP)al>1`stMlu~S5aW@AmNpJ@ekb~{Oa4tV!ju7e{{;)iq@(s2VbA8|HU
z$&FK%88kpi+dH)GOX~s8qSBVu{(g1WZk+%}eNsi`(v-}FH=TgugI6SQ;gc$InCLPD
zfM#52%UfT6(*am;WTBKg*|o95*QWhJvTVsqim-e0J6im27SugQ`TH6*_KL131V^i}
zX;y6P9#V8LK{2$78n}2MRnKX)#X1&OX}k&6BM!@Z(vk`GCnlV-L+%+HM97YBO=bl(
z5c{k>$zV@gu};eUh=zYNQfEu`&k4Om=BRF%)Be5oSeG!+qtS0~MjTahseP2G2)%xc
zr}wIu_Nn=ku{OlfVI?slZBlu98r%aZ0-^UZE7ZsW%~K^+O6rVAwVdLM_o6g{@aU14
zsK*u@xJAvclCYD9g#z)m`l6TE)}h4N=%sXFmcMN`@b;UefK(b2U%FD9Iq@h?wjz&p
z-wiaOET6vHR&%+ApVrhsYd-ZSK;S>7QHT9^5_TF`y|R(^h+%GfC*tZqx&+~eF>Q3E
zBo0))K^nry!psR5l~Z$<8-UF3VeoJ7Oz-S1z2np_`-_cK&MiRzoA7EA;#ZiGOh9J0
zn>eA=4TJF}KdN%hq5Z09no|V1Og#miczf8JNm<kX&kgH)+6Qu9K`L)1jxBYRM9b)j
ze94T4S24ZDhXaEiR-27Zp-5TlH0MT-u>-SWx>0_Kvt=**bh=b4m#3X#Ik{jv;E}O<
zFCI#Q^;x2_kbP%4n@hsJG}F+xV!tO10<~$S0bybaz-;mk+CA?L_OyLik4^ay;nap8
zbDS`z9n%^RkmA8aFo)p_fbooW^bF%Xms;~QaNIPHI!kDZ=QAcPPcdDt@QZx(Z+Id$
zhMruTy?LxJ9ggCEVkI=4evZ%KnJ19v6xF35E-TaS7NpE-EcT~=yeVH%UT!bD5||~x
z>&?jU6%Q1y<}3;i95K8_FuwI`|AVo!a%+bzGTyUtzEi&)SzY#I2~_rW^n}}!Phrt{
zrfO>i(C_%w=Vj}dMohZnwqw^jtmOJP2L)r1!gJhFAUj37+@S)a^KGvYq`tRobZ+L~
z<|?nh*iYXY<ER-15QHTFNd*9j=jr{vbdG1vc?m9tH(1ag`rdrra|B7_eX(DAg<#-K
z^L1<{`i*Gp{3kvPXj{>zT+vYocMJk5L>QFY-->A8n*;(3=2u_V!obm2i=WdSrV`v=
zx!AnO&MxTu9K!kr8H)>YKn$|mBh`)d>@@e16zUGX5vyMbbm4b9fKEe~2rGe~-FEYV
zF4MEalRYw1vy*c@1MWKT19rVP`z*Gb5sExBk&PC!)bbW^24DbNBGG>y00?xYa9x&W
zS!?-2p0}fP11ohtQE?Bh^vy@G<m1#`B*N2NdP4K03+bs|7gf{Gjn10vi8vQf{XiRb
z>u<(->zP|J`#_t$M^!OVn^MfU)H1pv9i*QGEsYT;xRD)7D#&?<?)+^gBx@Z^dteuc
z(8a!a3K@aPY<jGlvn1Np=d9~0(!&emVDFg&cZ;Z*=2`5fLS!76yGY-S5~vO+;>y%i
zP)5Zpx_umK0F=rT<+J>Q<9s~a#xfxnPe-|}>rs2Z4t0sm2Bafh;JoQkl{tz!TE=#s
z2gWa?lro31e1^-XfsR(+1j>LrGw~90Z=8<4O}o+$+6y5=?Z>(PrllFd>cPRLC)sQh
zwSY3|wl#vXeJlm@6#S~%<nI5h1^2lNLPYLf!3n+?lK1Sv1)kpX;BSKk{Bb_(%tl_#
zb7j_OdMQD6TbuOG9Mi?M0-Q$2vjAdc>$ymm%=_9>?{ea(nkrgi<K2$?A8R~xruMQV
zgYy5kJcLXLgwd0gbq<Hf!q{;vbBLF@2Q4rJK@PPzWdCO9e<n!k0}$TJ_2O$RyQTIQ
z4UB%+!)|T-KZ*eCH6D~qs*P0@Zim0-65)#ro{%G|Lm4D#ZNgfZshH+Z>K?CP(RwH5
zh2fUtE_x!jB@U9%PU_B~CP8eh%FT&uAf)Wt8oY@4*mHDj)bCyOWmOOV<r4dZdzQ2B
zsF|7SNE=FH+|U(x_i(8EV7^Ii<0eqMwZj7%&(3jIq%*eGn~INKDb0vPpQx5HDp9SO
zVKTYCmR{?*DI6S`ABnHW;;9wzcRN(Os_eX=2&Bv+5hfie`?rN*G&r6@JZ&~lxT-!+
zO}r{Pd<Q`Q3H8Q+@14EYQQrc<JuWWKEQdPg-qI1-HkDzxbRB$1g|to^sP0Sphv4WE
zaKfUTRD<xYNvHP-?AcGBFWXG&7cFx+z_6^#<*n1Myvpo1Xf!ABEPBWwBgo1EQ<0IZ
zF5E~bBby_+2_ktrD#c`)>Qt?|YBXiVEv#tP_yQC#CP~RKka72_P?olbfeT#a{OCYM
ziv=(;ol*xt=q$W#@gS5p3}<wKI<(MXVtaOMC$V*CZ*UIMru4G{UdE9e2Yl#p#H*3(
z3}wvt?7)S<c`D)cnmAid6A6}6V$t(d>J<(;9LFL3y=2pd8eK2#b?%RVfRiq<Rif@o
zUnM(JgHG9?RgAdb8mT6mQ!T3_7Mk~SDPMbyp_Q%LAS4Wg-B{#JOcjJz=<Lfl{ogvX
zJR_Gh#*o3D{yWF(8QZocOXISJT3=zM51!&sJU`&~2&gY`QVqB&T$QgjNHAk=8OQ@9
zB0u&pB_Qml<SK>JMeUGBXgFT0N&a~n^+7Mu-}?z1Z0+~QeW!uQx1wB$d6;yr;`zxG
zwNTYcI|7MVT2tD-aill_`9cz^wq)=TN28J&o8KTFvqj!-ReW(vQkMM^+B1PCBH}WA
z68TI;&QL|H<%RcxiZ>vCbDrA69~AjUhmy_Yub+EJ<g&f$rSwpQ*_)DE2(I07--1BX
z1x$wfc^+v4FT9iJ?<?`l61tkYN8vQZwk^+sq%rz!Gm4W1*rRojvOCpC3RP$-4V!-(
zWlHC)w_TiUmGJrtGmh5gc8>0E=qo=NYm`k+9?5H)>pA5i(#ddkBcf^nx|M18o&6w4
z<Z1P$zd^lfzRg8B!gP13BIqT6{DhD{%`Q?75uth(a`J&1qrEZ^<P_3DnvUWZ$ADbb
z363rnSU=SSS`+utu=o!3z*FYTm70isKa!FSVy<-pAzL13cD7i~7p~oX&2TwcBQwSX
zNUTh!4!wss9JN<lZy;QVgaIX+Hpv2Y>N0+cDpco#cxe2z(_7sOzJZ63Q>O?tCQBIr
zoJ^JoKFF)T&%no9U^rc?wM<dVz~@j>g~&>bpm^OnDPt<6cnENr$4Vh0pMDw||2ZaI
ztsJm)3q2Gc+huFYyfxUzTF44$ZLW}0WRUZ~2oC9egL9k0{CQ#SIpWq|U9r)mOnF~-
zZ%j1zF?8gHI5Q-GGZuwsPaK?5pdh%8+eB_dGozG}%bv@-03!w6Z~;$jb!_{e>NWVJ
zX5iQEuz$U7O{oud8U{yhIc8I475p}U_K~L0q7`3>7FY7}=q_(Z1aUVzv6xMK2)R>X
zc<IL2cc0)K)_fac85}Fku&`0~8-NC<Fh_AHdE-5tESWw5Sp*GuzrEUCioQOYR!Si<
zg{#K3V?2&59=>ZvspTaD8jlo~RDKLZyLRv5NEzvLRf6Zz)T8KU0oY6}4@F^gV6oHg
zR=|mt2n7XX(jItBuK&RFMXivye`wP&M4Dy5LoP>qv)wxgX(IisyDKvXLkoulS?@2&
ziim@d=g!AAwQz$B6eYSpRBY>eLvDQJ2x}6*=$oCk{o|=&^u@eGa?oU9w7=`BO}R6L
zizq~F!}p<Heo!aVB@9BCAig&##95r>;31Zp5hPE9j&9yJK{Cv5YD5JZ(^J~;QiuQc
zhssWWXFt{6c!hl8RF5#^#z?%`NS&UJj&11IJiisx#(6vkt!D<2iQriF{{_J6_2%OK
zKKomUPYG*<_PJbdks(778vqB}eZ1?|b!pHiTESUWp#TDCzmKRIt6MDF_0GjIZ}@Sx
z&{Cmn(^C$6K*e3PHGG#=?z34!$H+p02UcjajtHuT5iAzV8H^}P6^|5pel&NsCB3MZ
z6&s4(2<@-aSh94=q91F&;hZm<C&U2?2SonjEl@yYI`c9@g-YGZ0{dSjGoF4@dJL%2
zj>Xu5v2R3wi{dMpAcZDK;-8y*NC;NAh`Xep$Ne7=cR$<|;$Mwke}0jI%n&O#4bPsX
z<$q)nhImwe7K9!j!|(L;(|wvQR|xRL5S~}K0s(J<>eN8`9ZdMaK-09_zKqRUTUFhx
zTkL5LEtdRUR3Sb$R770RtCC>OoN`<U5-iGWpO5$4|9t6#y;M6TIEF3xBds`s4D`F-
zqNo=^Rt<3;Cs~~$?gm<Nl+bPYVM&@q)sM#Yno6D}A1X61ZnrN$WQ;lQV9Ps(g8PqN
z^U4P%-|L!zfI2qxQtw|%5*K#3y8%8mj68c){LLbfzT4cULHI}k74=0Ewa(l&P97b%
z<XAP+{FfHQPH3?<rjJ{kb*H)Bpf)_A51Up&-DyHmv97UDozb0{gCXDs8Oytt{K`UE
z*$&b>{J9ck3q?%Q6AtuHP*mTaKfKi$kpOlz-GWqZd%&Q&ZaRu*T!wY9JX~T*+PeBc
z!gl1TYx8*Fyycx9_r@6O)EaPvzLN3_xN!LDr*PqI6{9I<j$wmA(vc8eJjYLjed}4j
zxa(ByQ;A-0cpI^G;zZUqI=&baKPS*QLv+VwazZnm6}RA|fB+3c&!Gi;jqc9}a{@kv
zX?Zym$|dx92E#B6M7ad5BkWWoRJ1E-0E7&I!9Ru_hnyc{{t=Y%Ra{)7><KT0sm!YU
zC11atO_$K96|4S4B2RFw_mHJ~FEj|BtFg_*$7hqt2S$&P6dB={C#~BcIxhpUl^e~o
zkIeMEPzvM|R0Xpus=0ojb$lG7gN&r+WFy7bxRgPqDfQcM(1>ay5B<R+z(XJx@kmB2
z0lSqAxBGsRYIkY^Zxj@yL>#$&2&tVUdKXe{KlZL~D)fJREa3C!{nMt`!A;8pj2eCj
ze0^U?4pDwL1}yZv2(@WS3LgkXk@=`7OdWnIQHgJ02r$#5YI2wHJFEQ3cUplDaULuj
zzI9p|d6(6=px<#7(GloRrCclHr4givpZl)b%;;6TWO}je=~*#ep>nP)T{;u*D-v~}
z_kg!w(;91jiJBB2O&~)r91Np*54*YM(dx-%Jmm#t_5RW6<oj9g5f~$sVZJz0ps8vX
zVHRg62!#P&##?N1V=%;qK$~e|x{PD{)$fhMs3)*t#!o+deqg>)(H*OCjzVg1e&Lze
z&=<Bq&n3mkw`yV`BBt})kEXwdcSALmjo58q_VLY0*d}x(={`gQF_C%b*d$leAklU|
z+V#QEf)5=5#k@QL*MvpUm08v=t!?_vV^;mwxsDmZ%|G>fn9ntDB)ap#UkFWR8H(>9
zsB-?%Ni-Ev(Y{J?{P10DFw<^vw#TGVrmJbn)V|j6DlkSZjKPdh!e*jvZBdp}ShC-0
z6z40HX?)>CKSQWt!^>G30Zt}QrP6uoQP4ihL(U${r>2af8R+r*y9LS#g+twNh;$Z@
z;l&zf$cx$Qt%&_~<G!N%wO9Du9qx6fVr=wjP|{7w-d<A@y0g{X{|kZJ^!vy7m?=94
zGH8`9a1Rw9r-+{bHo2$!ClL?nW72^SIg{UXp0V&~OBs$NbM?j^#V@+!Hib7l7|?18
z+|<jN1))Z7?H>KMJea7qyrsYSmHA8X1_ZFmeq8UUH7(>0n%fvskjmj>Y8K!h=AA{L
zwQ`y)vHb^G`#W|;5mc@I;13pXFQt{nSbMi*RF6BUuMYO-wE%oTfEpCYWDpF*$a~X5
zKzOnamcXjMFS=)3%t72Lciup6ruYHv9uncGo-xY36q-4|8=9N<iTp&!D3@6DG)h)Y
zps1kXiR0lHDSYUHaB9vqdGzp=eT@!Rl_&7N<fi&x8J-A3eivgn$LOb~0yFz`ps+~g
zmFk^kVk0I0L|cJJ1EYQ%6c^yx+NfJL483lW26a$AkgIeQvHANsZ^kvN9fW2dquN{l
zMgC)nb(Cl3wMHaV-a1{>6k5XxOC0+1Juau5>s*sI0QoJE7#fB&dy_DkpYf9iaK@Qi
zVb?y!(w{B6vd*(rxn2?g9=YU^8$g0gU|^LK1m|HX61jK%mU1dQy{ME?rgKE$J!%=f
zsEFjFfWk<LZg%F*-68B;3^xq#XO5M8)lTF}u0Mnxdw8!jZ4cPeSW$}ddA^GFmI!TP
zvob~$IIxC??4NdVT=2`eRB}s)7$6fv!I<Qwe1qp0vRQ`OcCD20<4vR)HKqo9AOsl{
z7I!*LEBVhY5a!hNLo%EX{C07%;pi2BrGYH5TTp-(SURB@R~qlzh70iNT8a}X?Lre*
z^)TC7Q({U{V_qc$^JQULdS=BHm!vI|z`Sz9HUE8SXR=cKbpX_(PI+d=|C+n)<S2(G
zC>#YObL)}y;1pbPV!tIJDWaFK#yKWHzH+YYY`^gMEOSBcp2*QdRc+DcO^=faHNzZS
z!zjP@kZYSV8hkF;u30(6Lq=zxriiU0JYChM;YE*&hL7J>clQ3ryU%G3pOgjJ(@ti#
z(3Xxy(4RZ|AUMmBBn_-`KG0Y+6048G&~~${4+t*AV({<udyayqgL9&)q_C8(!njBa
z;>#Lk10*Hw5F&tVa6`0fR0hoeN$AD811H|{J)eb*>-mkMZ#b&y1fzh8wA5XSBOik0
zmf({393j{%F&m_CU{hE~Vj5eg)V!(r4eRm)t#_C!Ebjn*P$HT6QAka5{{-^9x50R3
zK*6<HP%fL-OJG{j?N(m-A}zuVCtMxjJb`^Cd(JPTs?ycZy|Z(jde%<wFP|02D-B&?
z_oc*;o#+alXZ1bz8I7_5es34It}+NZZ{XRM;cf=%W?*7N-y!k+__nS$VKH{AZ?naB
zlJX~XAb72~?~jc>F-h;QaF}Q)TOBI4gPUA8$GQE-+b6DEw44*CpoWgwXvTXnNel-V
zAF$Z@|2XBcSb`)j2TT+RYiWGJHX7|JDIdT8>1`P*m`kDNt+~Ec4UsNaD<r_QPe~?p
z{VcdH8xp6tK2m3-?TFWmwyl4g$sl$1{rq>H91lFw2wct%c$;MGSeK4ckWbAHcl<KH
z4<_$c{PaP0O23Ik{AB5z8kpTiYCDFM^%_vAGo=XGF?^zVuF*l&h&K^GS!yBTQou}x
z`p?;)h0%83rYBHB`o0F9sj;{}Rd4+XiM%tv8>wJ;CiMwS9=Y-9TAnFP=7u~VO-oY}
zHM)?;*V`6xTSJt<<}|x@at^p9GDZ|lqjadl(EX*?jp^_cNmz*5IjCFx`W#90Sp6Rg
z6+u6)@#hxQ<7?TP)b5Ad>Zvo-R5ZBFpsV|n;H49O$u{rhWL?7phP~`-vQE`_x{VeR
zF%64|37$c!D=d;zdVjSs($GsZ_FZ@=0XC{z0CByiVPyLw->ia_Je?vD+n?WT)_x$0
zS;O!!ZHDE#d3SAB`>9gnSI`z}mA6_Sqc?o;q%NWVRm@wE-<P#aqgd9WB(y03WGOsz
zIQ^}|flsnyBn2-my%&B%5v20hReCthYA7e3CK&X!(iy&8AWd(qs{n=Nwj`l?*tQcR
zSr`3RdzX;WVPVh@23O!i((n7)ssYPCO;FX<X6Z@5l&U++0i5<gErE(f?4S))F*m|{
zR(!oyo(I-0?T}+>J-gGYN^br>In9p3(01u(E!yEE5wd^xePo(FrU#Pu8P*po&h?a4
zVM{HRn|)Grpj^TF6ptTVipIozEP%znHi^dDu?R8IZm(hZvmxw#?ys>*c#Mm(gQE{&
z?xVYnA~?2A_xu7rarR5N8g~g7sH&?A0RA~8dWPxxjU{ufK{NuIFo&Wyhu}y1#$o7)
znzpkrFa5ZQB<3vq;lpDtuOL-_lw7L&*yRV&ke%#5QMp-6S_vh@@Wwsid`X?_;7?B<
z9#ff6I1bL%W{0MuwLR*i-nY%e$Rh1!Ni=uc6~2z7#<!390B<>03u19`<dMT#ix%Vs
zvf;dhllO~f=1Gj~V&rg#uORXEuh@A&+XAlDL`sxxa7WIBc;%=?4?KpZPCccjy0u<e
zVSQ@K-17{WDxKSU4PcI=JKmo{->7uYb5Is)FizS9fet31o-*$mw*|mr>?V441BMm$
zf=E;>=Hnhe8+RJg^WQElwBD8QbXl7kC<#`U5#JgY9&1Fq1+im~U8Ez4OAz4Gmb|aY
z%@4eZMAM21#xkQ;7|g~P^G3fu6DQ{_op@|R<OTkPJN8*=9~6BjIaw}$z!7>@Ku0rg
z1ocZ8)-;wymRWGG_{@l>;{X?<re>6E!<0y#yABoC_cqj){nYs{aCU{ER;O*t-;jg2
zX7+a*zo*F7PHIv_tR=E*`GFce1b8fGS3`gub5*z@6ey5;^|Fwxu0*<{PxWOD6CV8u
zB19z0V!+-!kQ}zlW!4IcgBzsSVxYTNs*jXwchy)!hjt_n{(@E4S4zuVh)d6l#L9=u
zjdC#DyD(1>vp~U)jil6n40HLaDQGSQ8;lD$VR2HQIhNQNAfe{xF;Ik!)PfDDKfcIO
z3PaL4@mk{cplvlP#13z*XNe*@q6##U!(2r=1RNyf7<_s4alkx=tbpb(XvX~02`eg3
z;tZPT{q?^;@dKzJv$Ytzm>i7OVBZYqGTcdCm5v))AP)i?zQvu<e&niPUkILkR0y7n
zU${)gkOEtsyku-&o&mocb+L)4lRss-sS?oG7RN30UL*6|nS(1Y>k}r_P+bvW9rXcE
z))bdoktl)br6O@Ueet6|End5IT9Qpl6mfFR_7xn!k}N3Bt;ND)GOF0+)>D7xJJ~sq
zKelLs#5#E0w8{nkw0?H>%7ycC(qv*=_BTn%iwKfYcE=4;#wu|E_4kZK&S2Ds%fsWd
z*1yG6AMbq`l>n~3-ai}6{+ZS`6UE-!X)mx3BpJ_CJxUHB{Xr?#y~oY^XVunW|4Qoz
znR@wi4S)V|&Z7Q0EK7Q@@JU6==jgl_zEyC@<xQ3!LvRD?E0gBHk&=3y2*S@FSFsBB
z3p$7!<+_GqxZoEIqdgQ3rYOU^U$nYdVoo-{p?vzEITF0)%$p?h@7PDhXs87#?ZcIx
zBVb<Um@Oru$qXI-CVKu5K|K+rG8_PvwF*skd`Au9fhqBvPr~(Or{CpBdAjv@iKMur
z6L6sVF~PxWk@s-ShiKXS*-Gj-U!hYpi4kBzF^O>`fK+8ssEr}ScT+F>)MIyW6R;Aj
z%?E&^ztjc!ZhrVPwfJIV+{Mz>er%!0*h-IL4&30<=z46q!ilz0!0C<Z+CEz-a?IK?
z$<Yi-W=O03G62fRIGpj}`4Lk2(=C?hnT62twA)dWbR-E0hPI>#;fM+9==@0}(VL?z
zBZll3vyK8l|NT$?e2wRIQ_KkNh#6#Gi-;PyM~=nMbLk2i4hyKSo-i6!;(rM7b9e;H
zvISI-LIkxsmY!Sz>$0Q8z+(&TKv9UkBq7c#lA?e^5aw03a3#lu0`^VBY8Y_Yk+xza
zS1Cd9O=+psY=X^aDV&DkfY;m@qH=tq?w$(3sCi%TzpIX{qAPo@LL@EZ@A^p_H55gn
zGALAXRyyxCz2b60Gw(>MH!5hsD1r{xPs75oI%u%M{s<qAaZom)8wQ`4JJO|yewYo!
z#Eg<afG~hHs%~e5zO4yuj*;(1(-(h4p~n#KzmlGxhmKr6ayTC0Gp*;nwdz_Y$TiJd
z4-3HHuIHz4RGU=E=OT0O<t(67>%TdJWoIvog<b{YL&!{xKKSuRPUYdKthTr;Wt<&C
z+;M<R8D^`XelAYz66nwy4#pL#pS3(>PplY2QHM=5{mDS9yz<{TnMt@L0RQ%D3co}n
z^XsZMOlPI--EtK3JP27A?r&Egg-<vLz2&?xhx)xn&=tAJ$&DMIz3@O`b0}EWt}FAk
z<j5Jyjrj7+RixBU1;~X(YJN`rEd@Ud@1<k5|JVRvbLdY<BIRpt>a`fXvy1O#X`8p+
zx(P?T@I(F;i}a+?&|g>wAG~TiD>jF+4f28IU5$eWllVPvHoCi`KS*-&OYnVa&&g4m
zqgpp$(sC`MA(fxMNFz~k!Z7zS&({y1BiT)h@()jQ4_RZO=C2A8&0+D0Y!T?Uu&v_j
zH0v~8$$Iyk!c8s7gD}cooU`anh$~~3peTQe)2S01!h<SEUz~Z&Y&o#P{b-OBifvXW
zvL(lnwYNN%%Qq@v{(FFc>j3ncJ|;V(6vWsNd>jdK`FN_}3sJq;#n8JoP<6q#yo-hU
z%aYHuT5yn(lv2-6DTc&9n`*jju!z+U?P+aOVy|(dwB6NKBSe--<9W+Y!m6(k+tP!I
zSwV=evKh_4QkLfj!9YziVc9}#$gBIfgnat&JuEl<w<C<`+pX083kcE>e~QYg1_lqS
zj?~TLSrYfSooFy5l>I9*s5Ox5+LcM$9!c^hsxWvC1_t+I_j&5-m0yBl(s68&27X1L
z%}T=5W<d1HEOT_Fop5x>Izs^gM#T;oG)(N<#HDjyY#uXhO-3ZSg_ITfk-VpMD%jtp
ztWJ*jA6Bc~`BEVxia~*ZD;|wRwCGZXp{b<Q(J|01$d%jVR(=MQK|)u_<BtFR8FbmU
z)Fqsha<$t8t}pZxqAr1lBUP5lH8N=4B5|o}M_T5-xPM0PJ7%vHP?(8gA0$h()>n*t
z9llUUz$EOHdpsH_Q?HBn6aES+8H&BO7?nND2o|Y039mY);YU3LS|VLN?+9Q4foh?D
zDx;EaOvj!q=eX2{3WNyi`DvoV&>G4xHND)kU*d|I{~37~oxG$qmGew&d5IJxL1pjC
zBZ9{u_8X}`LupzOSl0MY?BM@-V^8JbvgWU?fN}e9!>IgT3Ti&IM^%=J=?l>Jj4*Er
zQ$k1gca8r;{KO{m^tI_1g9P*g&m=J)Y7%pcrJ-f@hbs<XA4bCTeS#nHhq+~vWReaA
ziNjSC@_p!>`}mP0A-b*`6KPc-vo}eM#u$yBID;Kmu|{bqen5WPVCP(ugh_M(V#{OY
z0Y=HQ(R20De}~@wCx69x=@(#ux98p{;57ft7!%>IXv@bppWS1~R5-cb%i}0K#tlO?
znb&;3v*{kFG#;kRdCyPk#*Z0$!<xIJnYF9(Kj>8eL&#AF^1@P^`0jP<GmMLiZ|V&U
z->^IpU!If$pL3MJMS}wC)@Mk4!h7=P0yZnpq@ntx%)hvIDI6?*)nk33N0fC3>B7B5
z_HVk1dU+%qGmx!$Ah^DP*{lGj1h`E-VPf^C^o+nL0vSCCfo!GPfT=qZsIq<;wri%q
zHe!Rl{NZa7&k%%92C&hCfrT97hUW;<-jHn56&WU!khewhlSlJ{3gD$x_pr7$t@Q?I
zriSl5n6<fp0!<K<>y!2GXwmfeNN<ng!k|?&@7hpy;t)!lFr;f@y9G!6!use~<`0>Z
zu7bV8!#Um-GzKS6Z@Ot+R;4W2Dp^}biXU^Jn*?VgoHpzMXjrUA^g6+n=HLHqQDZDM
z7#s3C6g?MgOZvrA8rj`^Vcn(!q9+f@6U5N2W9x*XJ8U!Clrt?@CTb9XKy|bh6z|CQ
z$Xj_-JERzIA_8iswGN!#jx)Mx608^l1^_)(L3tS7hheMsmRzkCASIFJQdvEpw(vF8
zc|hP?2cp>e@5Ny4@1zpNPPpq9EB6Z=sQD#b#1#Sk6F_(+%=o7SRWD+omXU>MMFvuq
zXkPD3w)1a6%)C4aDe~`c3XgU6&7YujI6tq0Kk(hU33k-_?)C&s_#Fg<%_Q*fbXz9Z
zJoIOUHb=`#Xn{V6MdgoF@mxl>PWD6lIzkbqg(Ei!fglQN548K9QlvEVe5a*dj~S2g
z@hw{n+7aT0Y^9bFtTg{oc~TMSF(Ng0!Bll}&v+Yz!e6#i0JS2#@b?s0MOK*{^Nr8I
zYT%)ZNhesk8k;TKOp7w$vWU2`^d;7gzOmZ>`jN|3$x9O)1GWUXTucRdfGj7JXl{Kd
zZ{+26;6d4A-+J{Sd2V)f!~F$)9w+XecgDaVAcp~g>=Uo$5KX<C{lL{hphBbRzDc<(
zjB;4E_W1PPQ<o*<mVeQr6+r7}E<A3VUdWr@w`53{CtX<{un^t?#hG(VJJB&d6&J9~
zfw4-@;OEg9)sApW$`0Hi#fybvHyZTy<(h&O%Vgq}iL!So=Yt#I`ok>QA7n{HP1Qz2
z<<M}LCQ{#;A(Q@8gIE;#PzPB|`OP8fh@7Nbpg|KW&B8vkGy!^IcE2PFXkr}gf@r?1
zV(eS7E#{plYr(IZO3}Xi>1GZCMt|~nQmK{u9j@!}IV2Y0sGo*!B*uRUC=zl#oqhHT
zC{CgU6TqvB64YHtNcMSvm$Y}vY#A4yHE6C52S}wjgGSk458Ur-Cc&KVM_%4nO`JoR
zSQWV=Y5=1PvqkoKQGR`Qw#okG2&Bck4q<IKsAoXwvO2CBFKZwk(_b0haE_6LiOHuo
zj+4|I^dub45?&Ty<zwkT$p6t10y=NKv3_-vXY`T4wmK|WikICei4HUOKI21syXhe@
zyY<#&kD2b()N2ZE%;D<<yp4L=SN8x0eEkuAeh0vCZIsrBS2@X&hsq})h3V*EqhG7M
z{CWt`om^&iRctYT#ZePx{UAL)I@mDNKBK*YiGp{2PPy5B5wDk|lQ?%t8~UuVxg>tz
zgCPOj?lD5C8-nPAfA{HEbiN)kvO2xl?EL%m6Zj<<)Bzwvc@GL0G1GO&?a+9l-gW?t
z@PlK#ct>W2+`SZcteOjl0Ab7`P<=fOM#~R7uj~d@r*5|QD*y>x<J`tWXXkGt_4GEw
zHMS<sdh4*=isa<;iR+C%1(+WDaD3c7s;XIQrEl(m*TQJPjZ)kFzv4sRYS0q%-<T6f
zIf)F-6dxsd$f-H(J0c6OKJ`TS+AYB*n=}J$+I!+IA(`)F)kvWIbREKS$yDk?(5o-x
zJ|JvkgMMDtwuX;+Mu)f7S3-7;L|2KO{tqy2L$m*`7$zJ)kx$6VHJhYP<Oz6JYD%aS
zt7iq6>t=YyOk7h*qoHK&M)9v2Hs+bME$DJR>tYHd%vn*GQ5*g*FDKxmK<{#Kb@UWX
z{l5JB7+4y2r$Sb5NJ$;_&vTE@)>P~a^jah_vKVN{xtDgNq{eQ-2*D90Qzpq>aQvK<
z&G5wqjQ?kU9vj(q89QqU;uxWRjZf|;aaZ+JPSJ^)bHI;N)NaDYqWAR;LO{mzmM%{W
zk0pN@_k@)AV&wz>Uy3C6W;-nhZM#$9iYnQm#z~eaZ7n>|L^KC}>8+aZSHrD|`yjDu
zD(sbg57@eMRxE#%@P~QG(eu-^b+sE|HeF0=BG9ka;Ie072AoQ`q|aiI;(r~w7(Ow*
ztfUXcnKvR+IySUFjdKh)2d<NomX6h&3wuhd%=?V4ZW~dD;3utO#_Fd^UI%b}8h(he
z=)N-^zXDcM!l#N>KX&ICf9XCs-*-1p;Hf0A#nJYdRPf+ZdK1v7@4T;Bn_{X|AS5I7
z;miuO?7nLO#c^_rhe@34!O-Y=$0yVfTs&F`946;ccj$<LR?DwnqD&a;<zAt_rXkh8
zX66dWrb*Ij+^XlUr(2v}KGUB{${{{q1Y9vL%^}D$I^hQ9nm)A)^f)H=RcHW>elvZL
zdse(_%<c>?fhKI(3EqhY(9Tfqg<*&GJYBoWe4i+p4n(F}X0@kh7QoJr%-{3l5HRX=
z<XAu!ONu}!-16@yernVF)xpe&%kB=EU(D7nxwk%@$qqXKYhxhtwmqK?4grVtOwe+<
zq6-*Nukp<zQA>x@R?L5D*(AKcXVQ^L-a;E5+F?wi9F>tY)z=hrt(b?oO4=|GLTmk~
zJjAPMT9Kq8FSC9P>Ej|V<(@MS_Qd>rdJJ?cH=X{E=R%q~-#R3pD+K18#19*+E%Hlr
zxw3!mpUlFl=B6o)6c-rR`GANba?KBa-tcUz6lx>zYkjh2H4avs0rKv|C!L-j*xJG*
zAGiS(S{^li4t-{}ENw_IXz{^WauiEW0MO7qS#+NpP%R`rzcH6lxzUKj6?KM7SKEBF
zO~Om-aU@>dHXZnU3Drml%;refq9U!+L;5uqttPY3Uto=MDi-ewiSrz!!h+qSG+VT8
zKYH*>dV7ATM3uV+9j+=k5Jl@2K}=vl1ZLY;!W8+x#^$d>t=dhLD<V7G*fYuxH~NJO
z`nhN5*KKT2bl`{K(44MQEOlrGN<(ESt$Jf(e?b3~pWbG)$r^`n(gmiVfOQp5YbvEI
zI^fYRds1<u#kZWb@&9@dI6Lfaox>(f+bl`RRdp*?q8N^CH8N6lMViARQ4o50JXu#j
z)f29D9rDlfJbBxCTL11lO(p=T$3kaW+tm2B{8HppR`3vxzt!O6K7)Tm94P-kMq#dV
z=@Omv0JgU;egJQe-Ipqmj?*#g+H=J_4lpTH)E!v@r;M^nuz`n?z#^f*aq9-{Kk#&B
zk+dq}VF%l>fPvu=IwlWV3W!s%MrDlVv_CRRlj|qrl5$2=&L}>3te7jwNs}No=zEb0
z@J^3KNs46{lNAMwjxp?5dJlxD_TK04eTSgb$p<sQMm9Et$YNE67XlHrUA(NEOdSh_
zW{ta_bW-?0jol;(-akh)10dn~eF{b^4Oep6&eK&fE_Bf=@}q-%k<o4~HQijAC2Fsk
z?O9D=0X|q+Jy{em$M1Os(~W64CwflokC$M{(A1)MR6SUH`A#Nv%7$7hrCa<#SyFF5
zyrb@l-f)&fzh_ejPl_8e^_Ot72MtS=rr^AteVMez&yYF-C9bY7Z9gr?L$sWmx$p$O
ziN8(P3mT||^^}|%U!NVw^0<dlfCXc7%iEs)cs1<36Gu|aPH=L+%r-81*Ieq^O~s<q
z4?m%ma7A44Ag@ch-QfdJVg~F~@?$2}Yxjlrn-U-#mhdj`@pf#UGMmIu&*fRf1SHaw
z#a-FtMFW49#%~UNG^>gw6|}Y~OrGXgXuE}6;dBD0HGaf4DkRt+bhc6tPZk!6Tf)P&
z4kMTY@NEo`?l!78{mMNaF&*1o4>mrCmP!WQKVYr!RhnZ*X1J*_e>8D4O7!+buxS~}
zea&aRcE8trPdS4flH~~QXtR$sNz&3@GkE^Tj8TjjBL#006hqCm?rcPkY{vcK)~B&D
zXA4KdwQN{b{~X1wN3sJmsaJvde!pvq;Y4Az+#3P3)`@kDOyiL4AadxgxFH5^lSbU>
zgw3XJTNW9)n>QouuXtdiu>%y}rm|80Z@b7y>6G|7)wtdRYZz6mc<#S56etzb$OGy>
zcUQr{LZ<LEZTv`*fjP~nY{Q^#x3;xWN}x(4WKfiL?DaaW$cvf*eZ;C4UT-*OAFqVT
z<n`S~`3A4IK-@O~D}=LB?L>gQoFYd~S~1tgt6ob3#}2k!M;6v;^-5j(%J8;mNXK9n
z!&vIIL51lXt+ZHmCKt>7XtKQX6ozw<oP2fqAfvw@;^8u$qT8~ZhC`}%iiYJKkhJGV
zBv27Nn5}s*%*+#=qA4iwD}C2iRE#uze-=fZa*F6XT;*fgAdC-Im}jq8OwoBeFCcnY
z$3PxY@)Rg_KPI5kt)iI6lE^l%l@WMAa0=WS8g<D3YbbRqJCU2u!aqy2nx2*t-=L6)
ztmPeq!ZMlryKX*?#NUUZN}-w~?lZH|7%vu9oOhoI?s#vWFW6}D<eMY49v59xO-UV!
zeCkp!XmrvlvE4qZu7VG_N$1iP&?^(Iy`6xF{g@M2MnA+TvH28pnN9Q9=l4nE0ldtu
z$AWH4+H-L;iF)IC7ZYGzdq#ZB5&TcMc1kMxPK|CJ${B&;Y#pe&<JlN1t^pfJyGu1A
zvt#Ql&rq6mX%Z06H|0E6JeE8sMUwUW$3%N+TR+1wvZK!2(xgFodDpa%cKA4RFf{fd
z<LGTT8^Hu?{UdULVyG=E(2z(t6W>xyXO|GV@b=5Qj(u6!UV@V8qo3UP_PZ(9u~lbO
zKMf+WVUez&7o%!Ne!sFw6;cI~9li`z_fyKslggi<HjN@%IB*4NCeD)kj?+SDaADqa
z0ETz}lRX55w`qfyw!v?)=gsAmW=do}TBOfDwWDcW0X|KN9;l;UsEP5*l0OyB5&P)`
z%_C_cfAE>Mw(V=*$`t6D%oM2747j$0?kmGDGx^Y={ABqOe6=71XjUUZ{1U5uo6%v{
z^2<T;CViR;8yT|Y(F3EdU{H`ZghRLFLKhM5AH?k9IN5sZN$xhAl#hXSsZjPlXklup
r<@q5YU;07*@k~k<VpXk8W3#Qfd;-?%PgvGP|NXWjaKmhwTvYk%P**i!

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..e020a369be3b28951295e75f0482e6cf803451ff
GIT binary patch
literal 44064
zcmV(vK<dAX6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWEUJ7g+O@c^}cptF>U
z0va)I^|bix8~q_FYvLrp2|``f(cb;2Wig6>9hAlmDKh5OWxU#girIGdmwHE=!<yGd
z8I!ZlngtB=4tJ#eD@BnDB&JM=jCZbn=w_9rruc#7-ifAaNu6{WxLp|(l&;H}Sw~o6
zY$vSMt%yYG@#fTs#Hcx93W+->9z+p)nCfb-Ps?hf_>W$Efj{)^td2Kf9~kebX%@K{
zt|&aN(Yo;9g;f%gV@>U~brVSLf&Q6Vs&i}g8Yj)rSS8C=HM{BpsN9_#!7ZZB(}U8(
z=rN;SAYJMCB_UYJ7^jI?WfGp*&^VxT7D}T!Fp-U5E5FkppUX=UkMgwiQigNsyFYtX
zv`m#x8V`=WQ(YveL}r9$iCWJ8tgehWghzFuheb-`l6yxXIk?xy*RB;kH%NAr#PrHG
z0=Dg(0rSU%!o8==(G|OaZhwdj{6sO;NRiGuswAeu0*I`e&FNhdP<a*FqKk@?SK!yy
z1k7{K+hT<(--`45OoZ2F$5qLK(X5P`jbOHb?UEH;(qvM8t-rMk?hxR$EK~huZzB*8
zrit_V^=)~=M~}O|fqf*9z?8cv@}43vyN*SOMFsOpG!gSW|519o{zgwiv*N{}3k%;q
zS)=UDKDy5cg|Ili{#O>7sn#o<BCJ-U5lw$MZ#A|C?QDq(?HoOaUSd;1X(la7y(4S&
zfP2<yv~6UKg$_bGCDmRrX63BCYjm3|b;KLkK9Bx@KXH12W>M|0x!2?$1jt^iqo97}
zI6h!nwvsiE4xgzl-ZP(RO3F|e8V?x$fm*#(b5o{GlA^af7a9C{Yq>h92GlVy?9+_W
zp%))9LiEqmHo1sHZnCIRfH~$~8%$mQRY~PRrG-6cL^1ON!_g>_8c=9`@FWW2#RH^X
zM6#ASBR9n+a`z%!!0TP8>(QIOw&<Y>V>EF%&R4`DG1`#5Ssk$whFvbc8Nx}Etm_Tx
z$EVN77Uo#CAJ;Za|Cf2E;wsRr?{bF+#Uv&<5ni;Dva$bR^n#R4l6MIqW+kSs4_Dtd
zMv+|e+(BG7LHle)nJbGwVi(C~_fJaOmixVHq_*ztj~-w233CWT-s@*FGVe5I|05{L
zqe>KYy;m+felF{^`?F!B9;q}3#b;@t&$nWBVLYw?%JH4M?bx7Dr`Al4#6@cJ9pP@U
z&O&1Q=-nyvFF<*UCxhE%URZSk6{5!&hkX0)8)Lj9y;H`#EHy#gNmqaW>-?E5!EiU)
z@IsASzujTtrm|l2lEHWrVu^5K_)i&i0v7qA20WNrk-x48l#|K4M-^sm>bOK0qxCw+
z88@3=)-2mg4hsX*P2LT!R|z*t^n3Sj%)Fsp0XLD*P2!=wA^CLBI_R5p<jEkg&E)(F
z;&m`y-giIF_e&qDwj8<Z{0IntnzR*-W?Rgmde^#514<&1&}qJVzR0PrUi7X7#svT+
zOumZEJ)0|OAc$2iZ4G@k@6<a;pusb@mYqh>FeWv(hadJ}-V~h;Ne#h24Y~JD>Dn^%
zi2|#D|5P2d(iz@OH5C!lcFDDP7~?E{4iZ8H1eUwkJ5pr!U@znWeqJ65nVJs$p{J7X
z)Mw4(aY;Y9XUX02Nx*XfPzaEyuDSECFaxos!3BT4Gtg$3vwq&+9Z(<9!y^1?i~}bf
z@eO>n>%XVoj9g0P5&?OPU?4&fqSHmQ`{Zi490Ka*4b5m^{<8A+`U_mKD8lL)0M&KE
zBrOG7`Z2iz3sQCJf9>!rl8*D~5{>d!-mPg=Kf+~SAufIh6kNP_kc|h2|F7&P!5>h|
zs(<4bSjy6-bvrjlL@mg@;7un)n%MTS6$kzeU*9i~1s=|^DT29mtg^F5WEHPI9hAyh
zbRCMbuz~nsa$4izw)LyY$8Cy28xAwio+55_4>K6##Qq&h6?TR{z?MftWF96C;;Vsj
zPmCvt0FegJao+Z{;)RY2U-QbH(Al_$G|Bk0+TrRbs2Msqu6+VNIR=YXU9pp$U0%#+
zY(J$RPgchNHqbs>M)kiXc^+kH@wbA@Q+h<+ekl5q`-7)kB6|$F>6y+?@pyyS&)SLM
z2T7Tsc<bS!poBs1GQv`i@-LWnAsutCP#QqdoDKlzR7JaFFS2xJ4KEGQp|i~0-jh__
zg_PV>!SeKzJ=PAAlg%Wz?t`Fj%ear$URxuMqSJWF5*txXLE{-<od+yQXkc2K8X)GR
zk8(mz36Q+8Ss(oOVWEU0h2=u&V>J?bp&~#IEXK9mn<yCaolaz#Ap<aI5NdM{_4EKy
zbYhIoA9#yGVWGGQ(@gNLy`}y+d6wW`>{BYzqLxCa&~Z}ASD?D990t6-eovm54$l@b
zBtOSmh*b8+R@NeWq{a}wsEW&eP8Uepq79G9Y}CI<?DIA3yiIRPSj4M^(>b28gPX+9
zF12{AQ}2vxRi$x#BS?DGJ+IXq%Q8UsMr(q?6Kn`MZcmqFo$Xntq51p`uL1LUY$)x8
zUfn0veekfY5rOq)G*U?U=u2G1RlQR?e`vxsFD+4Sp2Hl0wKz26E%vv_QS4g#)ko}S
zbL2g=KznoG#SiPOu&d$kXmBl(OA9>4!0(0mC^xJ|V_szh+LnJy6U=Z3Hp&Yt&tk61
z6x3uzYp7Ti_Xp8dXJf&}dgEBqcB3=`LEyD{`cn|o7n8UHhc$zftgi$OCk@0sD)dE8
z2sEI^)41(yv3viPYu*|v&FTSY5G#u5x^Y1-Yf|CSPr_{FVh-EoJE<+LDA1bk;wh$N
z<2)MLQJuEnywtzpXftiHKT@jiq=;;~7~Hvsy3s;stVTgeS#ANY_(VAge$v`*@94y<
z^|__(v@=cFo8+CJ+%owwiI`v!tO5i1j@EBBs4!u`3=rMVKKc+u-bz~{{W${Vr8Ta)
zfrZboFV>K}D?{r%{y)H9DPIM)bAE*)v46qWE4X~O6_-kT_x@EN-9^Q8AKajRN!5Cp
z4}rfec^7zUXY<Goo>0&I5z|92I&fQ5v=9j(vURBAg~|e10K?exW>uiTS3e)%*CgMU
zjj$VwcmwZ^;?Tt7a?dx`tfK(;%(7E%oeejuB7X#@0gsI{+^^h)JEQZxwUel6Ce}Ub
zS1EFE8m|OqV)iuPANMu)H<u)5H=f=^>ee~$sgs}lhmOgAcgRLW@kOXHfFqmhNAjtc
zTe)OW>n6+q33C~GTuS9&tPL3Gmi}Xo1~37Yg|d-#z_T#?r)aX|enub8uKkQ&T`bt=
zGWRBr);0VglXOeZ&>j~y2BP&Ok%TQ&9z6p^6G+)GDB8*zlM!lAMu^@E1+2G|ktq)S
z;-hHB^4vOwNTg!RER{|2%6!6g%ybA?8J~kh^MF2O>w<idX8@A8^ZSd$?y!Y%#X;yB
z8L@T9hVym@PR1o01f$LiM6r3_6YIoe7vTuVPQWaU8CMD4T!=Sq17eyYN(kiFq$SRS
z+Jvv9{bU&8*e}t2@XnA}!rZvf+nbFlmEPv*RZzoxBQ&x82B|y0o@(bOV2{l0rA1=M
zhzu$?w0n=CM;ZEE!I9R~y(y1Zy?Vn6uPLDgt7;Z6E1V9mvmJ<HZtA=H&*y#`u1)r|
z_%oG-S+81O)M()BMA0E(@isuRVE0uoekD>V=FKX0Sj&EuVTFT+F{NTt4aA7(XLm7;
z0t*TnJGA-z?S$`ZLt9*$6c0W}C|9Fg7RCQ7Z`}8;OP~Lwk~Ou40JzGG3LNS6Pz)85
zb2YfXNCTg--R?Tva8Pe+FlB_a6jI?wuuHOX%+Y8`%`Vb(DsKoR4sXy|;s&g0TBhAt
zhR$PsNf7#NoZ^sD3_!yEPD5Gs+xqA<MAn-+DVKC}%^nQ%N$g8sVT46lgKF{b6Cn;0
z#;%&;Wjrkl=fg)^|FD*0*pzguBiBkBj-x={kczW_kGx+fC<BKTi=}$~ylb-3jRc@Z
z{G5q#Z08-I$^lAbp!Q#y1hDGFb{uFR+jc~y!{rf395Zc<t^5AYkI(9i#9@2l%M9^(
z@0eJGka=CnM)5A5tbIjX)e#;N0o^BS^;k-m7i9l-9%rq>QwlH0@$(x8DX|xz9C(0n
zM5I=@w=Zr|uMS2<pQVcEwv4zoL+D^AUAfxKV3d-oJ|({HzSfh^n~R*-cas;dF&B12
z4bn+?9tLOH^ez1U`PV_2%g%~sQCL;=6&<L2pkw7lxtrV=?6B|Pt-q@Xj-zc%a6Bj0
zvraSa1{WQ3(w=!=s<i;Vq{S0wG_Y2G&)gZshG24iNU+2Sh)q}2Lh<r4VNwMLtwE>S
zhuW`uqE;A%HQmwH*v(etZc-SY+T2ggdd_#Ea?#u7uk1d8cG)bMr~UQF8<PPPD9s~N
zOyo7SA_S>1Ec9)$)^b8Z;lVG+tR+F+2G&BjI8|WWtY0ardsNbIxz2e2-qgTdzUsQ$
zS31q1O|WY%CS{(|_O$xEbVUnQ`}o1GjW=PRRU^%X+$jshkkdMhj@&tmfHzK-rzG~V
zE)@N%$50ZALe?T^Aq=XAnpsqxq&?@4x-lv038;nm{g{<%uZAZAWr#Uj7Rn8!1qJNL
zaK~m6U5<_WUv_GK4GOinY@NgZ{@ics-pT#%i9K`6mt;YO8_kYseynPTy0hMYng2Ia
zxIfNwr|HGP0qD$vV-S4Tvp`@Y;kIJTpsScD{H|l5T4K{WQO@kmv^Wi~uy$fu2TDDA
z{Nh>p<ueWM{}S^p!l$m@$${`v6+4iy9R6=!I7gn{mk7Dx#$MhO@oc|>4QFQQOZ|Q{
zrm`GcbTCF(kyly%H)ycRVjH&e=4m^4Pg9kYO;tS(wxo)lFv77}iLvX{`%PVBr7SN;
zvc@w$JoLvgJDFiXueEQX!@uM=ygfj}QaguTt*2^<<*0+}i!?Rrk!Pj{y@)cbZE-{R
z%nWA*CJ2oB{YS6Q%99`C!nP}frLIkL=KO)UVFPfAQOC}S#=lVP@Be1=AksE0^&Z)e
zfMJusv&BXqahC6hsK@{5*;OdrqShF)#1pnV(ZGJT2F@bO2p_4(-AY<6KXhInQRFlX
z<OEIojgKW20}!EXr^ha4+Zj2-Hz%*I*RkQ%tl#hkI93+%Pg@2q%f`Uwzh82DUFKl9
zSO_|*FU->L4__=?2vDW4Mkl}>>Q}NlxWK6O{_z6FG7OTny%#O8S_(0<Zc+HE#%?fk
z=>5@DfO~;2sDJPG-l=nS)q|zW_Z1GQxC#&k^`dv`)}N}c`!~J|8CLDFxoN;N7CC6~
zCWf8OKBy#)=PG9KP1Xc@aZhiT#^=8;+Q&NWTaA_@01biq6uF8*`M1x7{Ye+Aw1l{@
zy%kI8BOurb;UWf_!Bg!V`5?HCoM=7aN_eUPP#Zf7A=#8=KiQyQs}?(6t|yg$+Dpcd
zbsCv88<1ZK(U>sr_*gx&c1k-DgmO)!hUs{`H>E-4NX-=4d4I2;JZLOjxy!KZRe!Ms
zADg59g*yGEzS2#0>4r3KCbmj=+jy@Xxw89!6ch7c%rByEQlc7I`*~#2*zWCJ1HCU=
z;hPXL=kTnBby{g<p$w}~%@MNWsf&04)br(>+hHGkDn3nIi9J7iX*N1my5wxG9D-XZ
z!`0BZto*_nSZI3obG)iTKaykil$eOHMY$w8S`T84S)wiKH+AL*cmjwC#``GTT;+Q-
z^$?FhA>F{r#fA0Ec%h69IF*`FyfolH>&Iw`z5zB;eo*SVGsKGvEU;C`m?TM(u^W&8
zN4C&MbW$3RBG#4(U5aZQ$&Ey(t~d0z)jv9UGpnZ~=^K5i#r=;$xY?=+NpI9SAI_B}
zfHWZ`i{@k#SNk$#d3oCIyFVq4_vV2+lB^BvAT97Ta9Q=~l*ZuoIlJf=v5}&Dqy)%k
zoGuMM;ViMy+P@y-xrVQ%GMClwRQNV7{t=Q`%RS-<J!umnT05kKDTiBdakVSHg@dJ8
z_G>lYNA4hJiiW}kj<8qrjRtopWGsJ=9JOuzvhFkKYF9A_(pE9%xGmQL?D^gT`gkY@
zjFCf|@4wX$|0b2qk>w2uB1qW&eD@e0MA`vhYx^lxx5mjH!ab>=MIU@Reo79EuK0|C
zPUacFybF&&A>bvv7du@9S^g0(37``dk2{R?B;gU@dU=C@doLvg4Z0f#Yv<|=wcQv@
zfNzr`938c%Mz~L;qW`-!XVB#xL*an4ydEQAyZp$CE3{vcgn{bF9l7|=<AU+6xbU&F
zElO07Am4+?$Zfc@M-yqQyK^QqLh#{F?hOh9{3-Z>0*4G!e0L<F>yDxYQqc&a`4IuR
zYvkSSgv=jhtL6~$8d`-jsk)H<#cXM&Hd>l~^zZ;5tTP`_Xhk(iQWzna{8c9G{$D)9
zHk*jVt0$~A`g5l~0K>ro7h;ZLiM^Y;Rp(9^|Lc#sG-R*4_J!$I)n&1Nhf#?JoXX>1
zT89jn{O^WhcQzaqTmbW^n(UZuQocS7&;^1~2$q4Ih-czFh6b?~+I}0MQzIhLV|d2}
zbLkT<;sS~}1d4*WVtN{V;r=5-uA~uS-#^mjPqfEP@#}0sJ_Bv`d6~uo>$lWaqhsbl
zFV=>M1(Zl%_Dsr|g+L{jW&vv)!G60L5Ko&SjC@knt|p>hj1x(Rul`6p)(gWM+ORGT
zsAsK)Vn`|0*V!jM#rfIb<4@s=eDF1O#eUltbLs*QX|B&VRV=Jqr{lN=hoh|MZlRsA
zhJssS5I=8OIlChFB96IL(KiI1{WR*Nv1m#^Ek)c0<&)03HtmpbH!t>u9#_CqX#`zm
z3>}Lq&GUcfXN3F{i#_(<r_#pk>FO!1^R<9|(Y48Mf3zNtEbF<iOO_~_!$mOg`u6%R
zfBkH%it7USZq-;>)*h*~K{%Wy@dT9AO#3WZXB&P{gvR(}G*z!CG@XxzNmD9wE_r_M
zEt&s+;MZz6a)9R#y6Ri@`YJqp0tp-2T|3j@^^-oG(;fOf(%1}`X#wb<l3Lrf-*TQ*
zNq87_>(0I&WGPEp#8keQ^Tjtp3Pq~rN7GAH|L)bORr)~sRH!$>l16F!k0Oq~;6>kt
z(e)O+Ovph9(J(1Rv_~<!<VDD$$K?R89JPG=k~Ok&em&8&b+!6M=@%r$d3H36>mTds
zy#O|4QyS0!^q*JFso<0cvSNhXl$gM1ly=G*4%1?6vWuZ!$~wF((GK|bPt^gf1f8v<
zk19QMk)d7o>ki4w6&Xa~YOXg2DmFv9PDq75oCp;FXQxO#zDQ%`1uW}|ThrgP{c#|@
z{Jim-be9)`D$qN;U;YWp>MWr*E^(s^whqP~r>FD0F4;U1BAle37Zpyb+oR8ttOfL1
zH3*i)@wsO1yuva5DM^gk0T*zYD^x(N&!HBw7q`VmnodK6!8RUVY&d8&%f6?B7Jg>t
zwL=_S>Yj}YT-?qJcq0zb#5ei76N0%fsgPW4pp2)yK3#@g=<nC=n|4k2d6y43oY9$0
zRoN~Zxbg6XrXh)Cvlg;?eHJ&Y0Ea;QVb|wxZpE2$V=^!cLC>QeyFu*Thy>uM%!Gsr
z2uO6G6c*OWAi;UH{U-8SqI`^#1lA+|m7%0}&M-+eBbO0v#H+w#RuxS~bz}AlG4e+W
zeo2_oX<PIVA)we7)wa}QKysSaH@d6>WMHo+<xDT^j|8T<6&-BwBLpcX8c-I~ak!yR
zf{4BVuF`za@_`u#DDwTlfRqsk+?YiO?O=|k+O54!>MDN%;Ka1%jfA@Em3HYXCCc?4
zZT@vy_fo1BY?4l5Yc%`OZ%ptoojv;HGm#oNsET_LQZPPE#VwQSa0O<T{PEKka2%MO
zWozF}*%elDC3T4x)Ue!HPe{3&+75u0G8b$APd%$~7#GFk<$TR#W<65G`DZ+>TFBkp
zoy4d~H=5^jL#Q0JeY?~6A&~VB4IFHNhMHB59KzL$Cg}X~mGGsONs=J~9DD>|!9NUT
zi^92meSKti7gT3Tc;xMS9x)T)#)$k+9f-ZBC<lS$8dQ$(JSXon8<>+PlE^kf+X)kT
zq)g>__D-AZtJD?SquJdwCi+YRQk)n`dO-}@Oh|fd3gIZ47rHXbw4=X7A2_%?x$b5{
zcW-~<JI3ahgbS54G7`qipn`uRCkIVW&jQ3~?~0(JR>cC=U1DwXXJ>d}EM_`Ik<4qD
zh2KC$$m%S)d<j`$V!zQn;vrKhR}NlxHkbZTD&Qd4P8-YKnLbMY3Y@fN&zKC8Bk135
zD|lq{Y<C~(T2FNE>P;0`?B1|unWy(5kYJ)X4DRfH(2hp&uY=Vhgb_elUyT~+V)AXj
zmrKYVA%&!jgh8i~%kft(OW9DI<XuhwzudhY%QYCULMXl7FdGrt5?bOt66iGHc+i1m
zv;A<I;P{3o!aL{q+gJlV8?x+iJaaC8)O<ZniYif*wPTOUODpuU*U@>8*ItMkVzT_(
zQtZ9eyjv;rxsp<|<8%M4eA={?RX6wyBky~9n>G;dQIJ|LK$SPXGIc825%(^`28F;*
zp5*SVzt{4U9-HOc#cn_tlD4Jy%A|F5$%)e1wa!NPm*h-05F$-@GGgAh9l$tgl!r;y
zgZ^9OiTUdR9~4{;OU-nNVt>1G)*P8@*ybk-JLKMIaW<3ce`TM1%XxS_&{p}$`@PkZ
z;1;8!VR_6y4xh=YA-K#d2b~>lubAU+q2#w0J32*z9q*OpA4^06>$39M4W(p+QfW=i
z&U~S%RDBb@jyQ$<dfs0#QYe5*iyjn|oh<6V)?u;Ra&}uoqV#S@c@-ejceJ!H!Q99t
z3a+=FmZ|+vo9^F6^UjjgvlVi0e*cv~ep*%at3}7K(}>^=(SFr8heS;drS1YH=q*1_
zTMW}<Et=6#Jg@plBT-o*y$E4*t#)DWjFTy=A-m(uNvZT$%h?krJggUQXdi_NqNG8S
z!e|p2>v12Rh;!B=7&FH5Wp_|D^QY-mVs$DZk65vbKePN$b=j3D?mOd9CiwT>2Rwa1
z;EwbOf@?GCuE<%VCq)Da0Sz=@H|oEF!Xt(oEDO{ay)wKi?cjqvt%m`At5;PpjulA8
zauJHAud(;5E9)Om7!~i8Adn`132p>7x5lj(TSH#iD<8`T;GQ4<q+z``FR-TS<1c#p
zCihX3T0mw)&^b4>!Q`mWheoJsQWYrq66QLHz;ZDQc%Z@mgOa(bqFJCgHYio@yz0Zf
zH$-JZxu*&Zp~W&=ksV&bz;L1%&c=Y#LZ?cGAM19(YK}&x$8-`$)DW<bOt12Cj!Eqb
z*#YGb`f}s^-=}q?v>TyUkx2-7`f7j|oA^g~vM^6WJ)t|~q|6S&XyzF(DE6<JEq_Ev
z8+UHC%#g?GtPX<AL)Lhf`;lBUxQpEa13wTf<@AfAI<UVHqb9z@Ix#9L^lTEr^k^~7
zuV3fCs)9aZ>ZTZe)ZJf~l<#(mc#YB!qHf~!|4*#P&+E6zUOt&iHg4=oMCGT(7A2Pc
zl?S;3azZPhDoFttXIQn4%1;gom?-ny$;ucb7Z!>u-eCyE<h1UfE#m8bc)SuHf|?bV
zUv<ySLT*Ex-=k84R%;mT<erdR@%J2`QA8$~cJ{B>WV`b;AG+vBhv4RLn=i2SGa(;t
zu*o4>z-j(oFq9Qdf=&W<G+zhpc5!fwV=vZwN#BXDa;cg|RPug6G4NTNj;+P6-p3yi
z2Jd-Hb7NkwpuabSsK_XShQ)59U64;HlB8I9r_*bmbs5Dnk7C~VbeSN)5Zo%RWLpk>
zWTYNahZ;Igt@fq+;H7^yW+f1g?wgrCdt*w}%bZd@$Ws=4d(c3>UsCuxgGI4gm7?;|
zy`Z>ga$X+pTlJ)W?t(D3Y7dwWU&N6Lqws=e^6OmdOWXpzOrp`*No9%!J3WK~d+LPa
z#%vhBz+_?gppWJSzENvgc0TCHbg`Sxww9ZIA-l$l3s9uea1OqGYeZFuOKKv1AFkNB
zZj-&_9J$8W!F*<i&Eek^EwHg_gApbosOR$!D+4A3bT>GjMXMdH(i)od!~!%SZjHZw
zAyAtUj15Ik7kKhk5pIfC;cB!USsV*})_7kluZGWshxfy*i;2}P@j<)J{U1$RFn`h7
zDqK|v0T7&e47Q3tz_`}#X*x1aiA?~O(Nn6hk4uM=u`_7!X9Ts|-752CniNF-HmyW|
z;r2u-bNUtb?0+k6UWi&VY5F}A>9lXfpdru|7A-W2!5Vii+1#wc0d#B}lb|y1gZ=)$
z|FdMeQi}MsA%pF^bTIfT8F=mS6HcM1`Ny|#WzTE?+Lrx|!UnoVrBJ>g$S+0tA0Iam
zS+$SrQr3XtHk&r0g#=dPX`}4f4Ik#<@Q-=48RJ7DWGDoRuki_T&((XX`m)I*G<9Qi
zfnp~b!q*r4j`%ut8G1tJj2y^NM8&RqMwI@Pa@t_f_tn?;ni1LZE%-$%#qsMo?up)|
zTY%Im?d|?p;rtf!)3$N8EQd?^bbfW<$#8MYmT#vqm*YWH?j(Z!l*he|YsGwIQ-$g_
zy4|sg8C(>>xgaA9JU6ksqKswbs|=}we-|SkW~E(|8Q`eg|MHoQGuRU@tO#`EYJnMR
zEOk(4Fsuu+DY(Fj9=)q$^z1(V*}kC}0*#&Z@<>{PcR7wGTo2jX`euZk??MD+wMdND
zX&ZKi*94Xd?e*s~>n-3n^L9hrGviNQcoh+HdyX{WGV>Xb#?Z)yX;H(3aPHKZwBrEu
zHYz|GJf5~*&AKCl+CaI<P<U63mPgqXjtUM-uST(QP{QPziM;e9f;)QWq}JrA*wRet
z1i5HOi!VBYiQGBtESzkHGaKGkr~Ka(6=^p%{obb_e^wK^ZW@l0o5FW#(XA^~8^Y{(
z?~O(&BD^g0A3NgB5<U7C9*j{B4Ecv+<{KWbLCapK^q%eh4F7qH5k9)d58;=)R}(HU
zgvm*@ClXx7>O`HK*WnFo;)Z#?f~`BJ`=qQAkDgYl!v1G;g42!l_(|D1^(0tYGi@CJ
zFeqKVBLw>CX?WUgb)5U(cj9G8AYHN>9C%uR74HT3H$GVV_v(i?aQPZ{qUz;=+A(8S
zOw)qWWbftFJ(ganv$6Q}l%=s)&9LGCyK!<PWiVcJZCd?Bwh%WUAHoc006<c5@*tFB
zqA+e$eIQ*Vr0_cwvUY?DQ+|~}<_7wZYBztrW}%JEdWP~U<AxhWHCgTTGCezC%SPeV
zAx}Ig^Gd|_!oUN{=qvzV#{?04_M&(l+XRaDr7FzxDOGjo=LPgpHFqVOdz%6wZz8g6
zwb(K*GB5n6+>Eh8Bw<NYHhS;J@}SaONvI)sk`^UdQFCqI<77=%PiC8PL~))tg&wxk
zU<^0(H&kFaz1Ise6}aDU;VxJ2gPvft>1~5}o>_tS?rUyq!5lwD0JZ6PZU(hlJ2fye
zCD!mWX2#r92t)+8pZ<DfQ*Xs!clj=pSeSQSVB~vrON4^jqlT9G*ovUL%>#^HYSSJG
z`7fZAQXu@(oxJs81~Fgcmt>XmRfq)~&|T&)%JChfXy&EP=uc=#lPL^W<%{2?qZ0zJ
z%&?^$=+Bu{I3^#3;pDtH&#oA4gZAJtFHmAyk0vjDtQP7{O`Oam^F*%TzxNlbv6*vB
zp{5q5hbljd$hGNETcc;!fLV`YNrv3jG~52<4I&;TXgt#iLkS27V%us?G>c(G)?*Z|
zCt?{T(nJejkeLnc)e-`_p1*+8b-d??^g{C(su^~csE4X*=?mlJ(g9gqS$>fK@`)^T
zbGoc!l{h;J$Gku&XvCRPjxV8LyMtN?$?T3}M)m5R85NRu(osiXXJpVN{o#=ZxxN^B
zV8p=Sq;A)^vmRkmu8Wu_{t<-j=?(Lz3P_<#vqNh*1jms|-hvKx0)9&cK(KF{x)BUF
zL&OYga5Wxg#I!dk`x;WHi<b;&Osn-uaOv^8$qA$*u2?KD^*au)as6U<H}J;Mp}aS%
zR>s^wSC+nFPDWRGyF>{qM3$)mS|u=5^EHd#EGGs1k2qM4<0<#~Jj6Mf;1^71*BkEO
z1yn~YVK5C2!fq%QF?Oc8rmdsrvuak@A!RF7J0k^UT0I^488o%Aa;-X8E{veL<}3+Q
zGWogr=)xo86s|Cd@;fa8Wtq9h!-|@&`pABA>jmc5R(i$NR>B;N#=?VIN{Es<gr5Ti
za-%NvjYb5vsR`-`T@k|1h$I~9XqFgcOW$zt;Y3aalHvo)oO4(G2bgUqlI)r5+jWa!
zu-tZ}e`>HBd~JaHG}1HmCVx%*Q8ckUb{3;m;FRWJ1VmFe>x9xPQbiS;tTb;ykAhcN
zt~Jfm4a{b^9a7k`bp*I(ff6@LhQ>AuN}?qSbO_0)_7tYuU(^$NTj3m~S_jk(sfHB`
zaz`m>t^GN5oz1|6!7|?$Im!PcnE*3b+m~bd(01)A5V<wh!C9U^QC-@T2e}*25tCwr
z%T~TS##%T>VHbA}49+3!HBYSrf~^`?TUut;xsc%=9O*0>Y+;m4ciwQo_jbY9nr6{(
zMv?cUGQ+z`39n~Z)-liktk<?@0=s?ulzeOWDdD)zTGvCsA0XLnrIRm`ke|(@Cm==x
z9J17sUu!Jcd|PrIoCR=J9@bb5*wcl4pu}Gk`5ohAHPmG9<FyL$%a5Q)^@?_t)V6Kp
zCj~_N_+f)81($y@k(H0>!qjV@x>$#tTuf;I6Tb1=t?XzrZ@;SEF4-pB+iN-FQntN|
zw6Q9nWdlAPJ7xrLqWiJFmcDbjIo~|rpHFl^;xs^MY)!q}I=vw72xI+gR!QM&;Dt{+
z15&Rac40I$8Ppr(UY?Fe92H#d#{zz0KYC7O^xAa`%MR<&FABb~jENb9h&|Ue1cK!o
zESG?ykp^=gkg#Uo6a6S|;C9s)f&Fc8m4+~aJiyN+iTZ-aw}?Ysz_8)M#t7Yn*Ezx-
z@h&AUQxZvC&D%+4PAH>S!3U31$ZGWZ?&%K@%n)mFA$0xv-XaooP=gFl*_CE_q}XJe
zmr>6_<?W#T@$8$hR1O0nmD$>Rl)_!UHK%AMwu!{m=haUTz({DWXcVT#cnv9H7}}`o
z<=;;-d6_PwrN>Ck+s<DKHTgbmqUCKg2kt+J3YP5H23Bu_kgmL9XyuvmKFzb>EBIQ1
zVit=TZQrSGEa50U(V_Jh!7bNg(428T2x^2*iaf_U>wdDt3IzeWzw0j5R&jg=BN=?~
z=^`r<2#(D?yWq!O!2aK0l>7Q5A3qSCWUvOoN?l83GK{yJBY_&&aw7A#fSn=8V&n=@
zE~4lA=irT}lEO>Q6|jOlBw1F0;4DWlulF<rK<1Ts=n_S!QZUzyW?D4f=^jN6mMNw$
zOR-^H9p%rZ*T0kwck+Y5Ur#%hFuzRgC3(D@s9o>hKOYTSC+oOK*hXNMJif@3Yrs^I
z3Gk)8)5^$2jlQ}3QTB2Hbe!**6FJ=IWO4@cR&^D}dBeYxwb0!<Ll*id)>%MU1i)hg
zTDdEgG10CgxHO%QJFVlB>tt)j-&zsALzgtmS{-)Z?}r)D?Ipb#JUTj%T?6JkN02<8
zV#BQ%=(ZY}F^lzxQ1H4MmZhQ74|rZk);UaeNzzlcvoJUjRX#1QfiQyl-~jR$Tz_aX
zWGyH%-2$S3Ens8oniVyTO^!A+ozOM6os+<<cH0^}>ODsOP^?9_L&I*Z4BniXk1rXD
zIR}nresxegtfMT>>O2+)apRWLXow3ad{e0&qpblgU;sfp``aN|@KybEiP6fg8=yTR
z@=y)U@VR}56hO6uGiutwKa$|3oc&>1xfkN`AOR#`M4HI2H{WPqJXJt-C+0|AVi8An
z*=<UH32+F)f&hcIJ!dLF1Wt?g6V9o72_tZ`CVWmq%+6;BwWwS2bpT-VOYQr@m<Czg
zy`Nbn@n%W^_hw?YyM~cT?u|VjuFfFPM(@r<Wl^8T&=o?#F{n!gjClN#8Gf95s6JM8
zi6@gI_V`)a;XGtdIE}TR2Dr12)^Eyj`!6vMamHy2IWjxq5T7R2`V9(#;woN=9}ipY
z<89$weA}Lo7F2ueKSO>?=C*V-5*V5uH(z6d(!9Tz&3Hro1QOY^ytwhax{g$PQ4YbS
zt{tw#vAu-Zx$Oed`Gs}Xywp>1abY;E{1AJRn_O8k%f86@2O8pInuD#EBQU|ztI$n<
zNFRcgB-`k-*+QoxgYo6#bKVc;KMQU*%?*=_Wq{r_@8#^i4vr@4QL*MO1@)B`R$7Sm
zNBCb)Ki{oQl=_Ao>M59`Nt%HzghGA`^j4(vr>#<X);&kmmr{qfXX8d>gu)jVNGg%E
zr-gniY_J&zjM(>3#XBQAbVfYI!=YqcXPnZyuN|_WFJ$8-?#r4SJoUJ~y9Tqd0VRXk
zyFJ@o^maH^$T^Np=DaEmVc1W+T0%ou95cFKT;hLKk54v9D2$#s*$)9q4!js=%eI+?
zGtQk%J(zd*_s&U*_m93H8&WgVypgx6cM57nz0Rekql)*+?fip~nIuVSoPu$lXs|Z-
ztiaDs`dsv;FTdT}!zpcV)tO%gg?<qgB|liLtnz>f2$mB#XvlM0B!2j-Y@+s0kqqRx
z`L0jZm1{Z>sFd;RB7K_bEkjS%9F;7ffZ<AF^Pnw48*)Jk!W2VoG*}LHS^0OrP*wv~
ze`RG5R&j7NIJ$SUak{_nOX0VLv$2n*{0sYPCsqj#390I_Cm%ep#ja8=w%Y}ktBh%t
z73Pk+<m%bTy-7-@J^2{7a^6U;orlpO>+b(cYE8eR>Ih~DGd!HYetf~%>jhj$v*Dl8
z@6JeIdWH<n7_%nsb6WO@92=@5*vAvb^j+g@Pz5ow(+mjSP);ia^hDYHCRUCG){s@U
z(0`D)79$L~h$L0Y&7`csDvCV`p1Q)!62fOYm5b|up0=Y8!`OV(#dNUR*wlSq%UsHd
z7AMBid?|trCG0zie=S3YM}PxACgTS@Aa1U`+Al5g4<=v#<k8rk2E!X8*kr9I(N$dA
zICQt22z6#Wbx}DD%OK4Dp-&VN$o_Y!b_yn6OzD+c@8>1yso6HTc8;_#R5Pe%ZR<wL
zi;^E=`Y&VKzs{-y9N&};3KlF;JjLb)t`?a|;t#ZuVq9;vCE<Q;IDb2Y3TKU2X&^$|
zcI=J~K<%q_=Ia3WT9U7)rLm}a%FLXS*G^U!kVg3A`hmT><}P_)P_J<UM5`7D!4D7T
z3|umsx!cKF>l4uinjs@J^``k{o>(+Zbiz_gHT&%_hb3_=OF9ZyM0rxR57=6Vf}Mzj
z6Av*ug_P2%&=Op-PuB_hP_J=@+Sl<aFAg1j3Um8wt_R6$p@fZ57UNQyB(!%t?_i&+
z06PKwf|J_oF>`eKE9~2`Tc|Nscn-wsp6EN|otC3>Jh0#IDeo(wzBn_kZ1C`WtLv<=
z7-#mYpf|Ac_;Yd#_Yr8dYD2**Z<j9y==q0T60!+`CXrWHs9yKgt)Fs?w@Y)kj7G(H
z4p4iWqSEr7&7`Hu#X}UsD~G^jIDj7<K7lfe&v47Jj80-qRxlXqP)^97<@YYs4qI%0
zN;`qytV6<|c$uTwCmm58lsn<CQpg=8<{X)Oq#SztYopR;G3t0J05e0}#l)J>LHPK&
zweXW`1OGuT^>L8$I0D#X_WlRwg+Fw>l=nVtldJG>AVwYOY_=_iG@w|;V{()|8)CM3
z2{Iu~82p+d^@Q`%hta-t4)!mq9uH#96CDZf7-`_|L%5xFwD<|#L63(B<5t>2@#@F*
zQ1n0_N%(t#mov<HLHkLV!eC>D{U?vR*kf~oT#}NncJj~vpH0>omoJspHX!|(E3Lvm
zQPW?37?eNB&2^;y2V*@V*d>aP6BLP<bp2PtV4+41+AY&_$5zXH!S19ZA?CQ*s%0$M
z+o~n_PaJOaPrZtr>i2>N!BN#R(6U9^*j>jXVt;$^BU;ax`*|&*y=R}7dQ(P6bT_5G
z83F$_cRp7b{_=upVRk(LSFTUAJ}^W_*@|EPZzjY(tN2=H%Nk0wUFZE?Z}GMRF{kae
z<y(|BTYC=-BOf-0CE!VoCa9(}Rn$f35}RUiz$1m5@nLsR&gnR5KuuN(_3=aVB)s=a
z%!qJv0M`b4DoIOF3{*sHk@I3>nbfw4b$&_SIj3vk@)an6?K87?-Kd`voET{+lG7mD
zKDbfYWI1;2U1;Ap0Zz&z$s9Mf%JHIOP^9;tR8X?oX&xuzi70y#X{+>(yOVVTQcOYF
zv^m7_3g9#0gddSEqA$d{81^?V`;0f1(MZ|)6{~X)4s*Jo0(2?kbFzhnZu7F-42h0S
zbnc)aj4PSy2TDD}wA%p4%N7X%`^F&_xzbDB5{?BjM)u-160T$fLO`T#9OSX~Y6C>Y
zpte;@tAdvp=&Z8<Ho0+yM7!c|vvwF<sIQQQ;o(RP%eH0>_m-ARB>d6+r*2)Zz!rV5
zhs7BZ{!fCPOXyY40no{ggXN_la>jgA60VOUgL@pfNfOv(K=1j)Fkl{oL%QM_L&Y5N
zpJWebnmi_Fwk8D{rhG6cy@Fl;FjAM+V1SidsDL0_vs4-)>VV>n_5CC}kHfek$Fd5@
zxPf0Z5%3dqA+xayPVRRV*H;?EpK<cs@G(s{VlLR)_6pk-tGK?V2bBiIRQ?utq9~s%
zS^e$>&{=_~wVPmq{(Ud|$;WAoY8q<p;Fr~DpJh+>cU_49yGQ8$V(VkNQ&$v2t+<G5
zHxJ#n`uT>n*m6CO(a569m`a-Iw8XRkR33yot=8N<_=sVkXKs<4Qai0T7y0yaE{#hh
zc?*iwcZ*}qGz9|_nI4~g8XpZ3Iy#?9hP$Qhxtn}Deqovl?qfk9VerTsR&aW<P)bD}
zvFoIb@r_83F+FX)0uyQd@6mbnaWoiB;&ScZEwi%<T#1(b#|eo~pW}rh-_#UjhPL-!
zBb*(>@n4EjdFI_S_OV*|%*y&E_&*pwN(250m?&XY2GZ{2U)-z%?2y;ip7Q%U+O&D_
zr^RoW6r|hr$H~DxF#hdz)#UOPQZdDHII@CEyRzaO4E^csaZX?NXZbw<Pp~$+JsG=m
zeUot>F0`Us`aF|l0V!abxBxRIlsy(SybKI@lF~hFM9Acr#F&fDs-02HBt?@x^2|>~
zkoby<*zzXZJbH`M)_-&}EZA_sC95MMxW*C@1(3HIcA5%Mf!&&69n_H9!e6H~FU16G
zo#?~l$lm|+^uQ*Y-g#eG0JqsrtZ=-fZaw>-FjNYPQn_n{+1iB-0?vBf2a!Q%d5=M%
zol%rnG2^AX@|)e&67B`v&Uh@`9)sh}k+`qzCRLnSJRqxZ>$)h{qiW6;br+U#wynk)
zn-*&`qq_t0ATzF`*rz_#Y~gl2ts2jkV||++6>WmNWIxxRkfr@t9N|G*lrGcf#_7r4
zx&5uskC$p`MZYCq=1qM&9%_#TBDpdI+5ewCmLE^1FXTYXwt@8E-_2kS=1}3_ZKkwD
zFO$HpwH4M7KVpP%69&thXMKeO$)IU6jcvLmnuZ_T`2!I;_WmyQQ^TMNWA4tJG23FX
zX^~wHoMt9aFUugn#QouN>D9XMmJ*9gLbTp)1&)#OEq3^&SYhq?x8jOXq<l1R*J(IB
zL+h0xb50R=<!8YqawGIZh6G*HldF$#i3zS$+Qz|N#17smaSVyS_s<djoTyjHn;*t1
z6g_ASxw^y#ecDG3(#uxM6IVoT+?r$A5cW8}Dni272wgq{v}_~I3u*mV{u{^*cqB-@
zInTsgcFyYy&7(n=xeGcRMHU}&os)GZPTLktn#Qp>@(`HpmKd@d-=1?qAA92nl5AfP
zjYYddlu^jne(G-KJK1E^?6R0G@OqYY{UNsIO#UJpIui)kj{6EU!6cCVf&M!mH=ug9
zYTW4aRoW6*7`9TuVFk(v$NR-u$%X1zR*8+ZIwRCvVjOCQaGamyOm0>6jz@pcxPNac
z?s77ku6`oTHnzm%6l!f&&Ie%GOLc>ZHh4J8c)?3S)|a(J@1#-?CH(uoOEn_Z1VBK<
z5twq15(40G#gPm6<Y$TsYHuM}QF>}sc5(izOAwr48FeU4cz_SuBmG1A&C6aBm}$T_
zDT$~4SGN!(V}c8*AqI)c1KM=-xTP+I1GbOi4;Sk^@Q!OFjX@Th9dE6qHWkrn*i7~4
zm^yN~+1~)uh(#wxO@S)ZUEz4~TeD4kc1L=V&phQ}RUNpzHvfnk;>bgTY=>~Nx^?47
z6i$s<jH9f)*7U1mnC#Rts~9c(b?%!}=(8s}yhd{k2e;A2Y(yJUW`MslW0A3#ZNg%h
zjg+*|Tzfx8BY3v9vFlz?SnDlugCV^5R(Tk;p9g`K2_b<)I4@ERbEx-M+mq@ts8f1o
z8jMya0y@-WTZ8!-YSB(N3U{~FsEr+h0jeGqe%_~h^BXr-=|m@`3A8H#$2hQ3X>pSo
zlyq%>MwHD8!vwAb1olH=z<=AKA+9LnizNK4(aHN6THA$Ls9NVOcX-%$$S(j{YYmp?
zRT&7M{-j*d?-0UTaa0)lKtHoQ#cG|Yk!%>`;4sjP*L8K=E=8p|!6daT%ZxYSn9_~u
z?j~rrIx91X4K59~PUgvTHCEX~8D<LDyrSF)hq0lzlWL~3UfP2KSE|fA(V1_Q=);hT
zSjs988i@^v7`UxPFYX(1&0vn)7D)RZ$YCWW*UFi4!^5n*z|j063hX7DN38NT2&4rH
zc1g2F!_!#gl4AQs0^n^m)}Fx?MMhS6$ifiKArTP)hLrnUir?7D4$WGcoWVgZIC-g+
zApdUBp7m4qDsTyAzQ_A~FoPKVoOK!JQepx7Se&()Q|9kFVs!5p{KGB~W)+pLO;3Mr
zwKyT_y!YzS4&Yo>#=*%Z!49dx&ulv*C@zvfpS(@hyvUZY*8rE>)4<Z9^xD}{*WqOf
zqsD;Zk&>7%Z@I<et;h{=9zw6jZuZn0C7OdOgo=hKsz^8ua6H>Uv5$9dUvPGGCj%0Z
zI$;n3@EkIq+2Pqg=1jpDx{w9gbIztJakBzsRM43Iix5;p!mn>Nzq0X9!m&W>Wds3V
zr}jP0lWk4QX%nMgC;d0?B(Idf5JJuM|0J2`2PN$kZr|C<8BDI21>r(q6h1;3{`!dt
zM*X_Rn@$r4QP(SlQe*>@E_2G(u_QYTMk)Rr4k)Z-Y%lQ0w9n2UvYot@_b^`#B!^RZ
zY{d8t3jt(XAN96YFQWtzlfN1m!VZZlcW#gwORm_H9|=+TjXh*KpNk<)8!M6xkfI1C
zxT!u|BB%l~{+>(}kO%n&{Ipn$Ugen&#4w?scp-)p!)M=)FV9$N)eX~aQ*z6JE)T09
zCmML!mBn*9r3Jf<C2OI1c$u7>NVit<rt<H9bGD?HU2Qp(=p;xGEVA=fPTD9+JNgLQ
zSk*Vhvl(Lw3}dfQNnbS63HIbm$l71BwC>|<qn&kO#_QZix(|SBgL-9leoMFXpzzQ;
z#nBol5m)o+ga(KKPSK^gQ@hfGHDNA^j2VxDSv<%S(AFzNzpc|e^X@>=QKOXT)sQT5
zMNNa?*W%AS#?Pj4DIuktRnNe|$%(OWy0D{TcR|~q5jqap-vHH?NN9ffe_ZTvfvqnR
z*?S&wYrocNHV67mtc+r%W!ys<?%FZA23PJ>So1l-3pN2oF@L~CYhHzN)SPT`@){e%
zTzgg-H>s-`eOdf{mK*;qn&p;9{DPG&#ko|BPvfzpmORlDBICl68QSh(odyd-(qR4#
z#9+To&d-7VH-)N`wZL8@S=~EJ^;LxCAjU=W_t4^nuu%g%+jE3RnU0U*I8stpGQ_9W
z>acRwL&rMtPBC%Dcng;4t{0e#KI=Y*;rcGMVRS4{B12!8#2_M2PX!go>Cct#qr)z^
zSc3nhP9M~9KgO-zMw1xeX})nU<(5EOHzK!*C`C>&Roh#ema^8&&yr-JLRf*1?SjnG
zaN%sK)s1}2Q+e$&G|xoqEc82z#ioLxM?BuU)k=X)gqP8uEh$TiVjsRm?cj#O^{HS`
zZWeg?YF@n(PS^e0*Ox2*l=p%wPdYlJRI?^m7}FrJ0u;}L%=lTQ*dx3klUVRk-o|^Q
z8h0+h*$3gel8<0L#|U+0J>?mF!}ge_G_L6vDv|yy^LEC-v8^8mf?*RL;N>^Q$+9_<
zaP=vV;>GW|n>c4+@%`0_Te@Q|pq@RM(0C-G!=M6a05?F$zv?x&bg?^))`(#+EW38H
zlwZ0a3!!5?qpIXz_-MbCL||Ower}nrR$DxE=pT`)TCF+o>lqCjpwYSmIDhvrTr8mb
z6=*-*x!%KqI>3cwybCNc7AaotJYMlZHSSP@alPjP;}>%G2#34Pkm7Z4>*T?`-j%{9
zMV|RAupB`*p>E#6_wK;Lj-ZQpK2M;8I01r5{k1C<tBz~C$V^&??O}-zQ1UUzQwF_Z
zHOu@Z<4d|GD@@V<gbl6aOrUPYKg!i#(!e`Q2cV$EpUNoNuhY8>GV{m&b99dGxL-ip
zUz}7+rUDoH)kLnrD!Sun#}Un@9p-|^3r_x}6bi~FO>IjUfU0uZtiqpTl<pH~0+6zB
z|0)mG6fg0YVEZk^ME-1e9L)d%87+BMz}b$xYmBkykC`N{{%&@ee^xQ4AP;v-g$DFG
zsez5%#72lpxl~dAj<UGoKL{9j32vvJ*=6NGeXDHZtUiUiE1A~|3Vc@e)b#K(;HVjt
z*s=Fa25u+O>kyulL1|c>vzZcoT&R=?J0AXXhMARqE~bYhh##t8&+0WtXPw{tcoXGH
z3C^%1cQ|qL{*S)cOXEZ0t5*ucB=TA?_+R*`lF_unO+XaK9lYgzw(#Aoq@}yTLt-rY
zZutL2ihW%vYIV^=a6U5QNf!;El)f7uf%s|q0yq0R&l3up9T5EJzmbJ#WXP-X-$MSm
zC}LC&&8bc`x@Kj`v&UCszhjR-O<J-jW|G1wW==g?hug!8TfQ_c0kbE%FknbkN}tJe
zVvfzCL)$x8J8$up#dm<G^#EBdMAo6IpsP(0=W85)=ZB3f@(*;;fm0jeON{Ds?2V*%
zxmAG!#$OLn3Hu@Vdd*P`HS~#;DtDMy?{(6GrHCT}*x-ro3(iXQ9EgzGQ|X9|Jc%2l
z)4q!Yjm?~8@0n#xg&Z2Nlqnbn0a`=kiXeZvFxu(H)LthfhvizWYg-t$jj%R(0@e0d
zD=ajuBda-UXi#e`4J_-Y4}nsMQP90!{mK^(hj*{CUQ+q7nb@8Wfy#H*7|iA81WkW9
z7aptp3JtJHtn=&luQRa`mBzUN?d153IzjXgi64n`X&@+tytEfDC}nr<Q=hgh%7Mk2
z(x)HvdL|-$@OzG0)gDc*e-#Hj&uRW^F`)MB+Hpb%Z~S*}Eqrr1RjII8>yu<Eoiwh|
zt6e2~+%<EP-V66wOwaBB^TMN^DwwiSY*=rsrk-bY<dkFd@PB(Th;|Os#cfJ{1*eRh
z<^vU$;!O(cW`vg%nu@>DaNvSY-l%sEN$sNxD(c$>aNik!k-r@lb7<$1h=m@?X--vX
zK>u^c#eV-!#@CC4<dZQ5iTFISJ97&@g@m68COZ_BG#@Mne^9FfWHKh2lmg3S=Z}1q
zX~yAzfH{lbAy&v&@XA=FP1R{ANcvDdRzs#tsT2P3*O!czvW?@QRQG_g@can;1Ny;b
z+k{4Z17f${m)^75?86D_|Jg<uCZVulKO8Oo+A8Hiup!IHvZx2T(18x2p{@)2b(Tk^
zcojfM)`h~6luLR3Xa!*!B>0`;`JUjz4jXp&kvH{-1x$v&z|x33%kBVmTvc^%=-KP&
zQ#Jveok?DyU;Gjmh6|9tT0+B>qTzd`U2Nx{U+jcmG<gXd7>zsapnWu(;VY_!p85>!
zUXul?Kg@+X?zgR4&A12S>sH>kaMHwKZKO;m*IlJ+=Rnc6B!yrwV{dXFDmEYBpLSW}
zVN2Hw|GyB26jA?>Xq{I3S(CDugdyPu9H0`eglmJJ$)_V5A~k66fB3$epiT)U!E*Px
zv=CGtNwcmY<%%Q=ECBdC8oeV`4H=ZalrG>EspXN_jCYq2v+@#-MOt;ZUB~+<`}Db|
z0TAlyGZ>qSXs07Dd^FBLX8m-}2adgK^~Q>88FdQu9;J7!*MuQNIJuzKlifEHj0+#j
zHURa+tJy-=^<Tp+k9y-Q#>fiV(0w%qmCClWiqFvh!tYqbbGH2u2qrI5+A4(Gyv1?I
z7KoNv4dmns@-CAnogLt!&u;V-CZL9$2^{7d5#f~9j^#w=uuh;m%eQy;{yWzsDLUkm
zv5t1IA30V(GKCmQ@3f5IC_lpL{ULS93t3Rb(3*v4?yD@fqZm;tPexQlJNZ9#1g$U)
zDJhE$t-sbFUy>}*8tL@Ltx!x4<Aib=VFSf=*jVIGTC>ylPDimAnfLPfFYY;FLU;2o
zZHkn;$vbn$yE{Lr#FQ#fP8*)dI{&S|>Qr<P-#A(=UKVoj|8rT?^EL7mSn@!+Pq!Pm
zddsRB?4aQ=Y&z2n2LbqM1WK)9E*qJWCIx7NecpR~f}>EH(>D64qa%5(<^2t+LovBu
zH(@2+L4)H0PokvCsgdo#Wp>=+FP^%=$KPiCd%)^IraD}edfL_88HrE33$<M8Irze9
zaKTc)ew9#MX(eZVnE@3_mZK2;9PJp(v^z!DEF{hv5xQnTO!)C$TI{i!Y}i2EF|?mR
zshy64UR|P*KXwsSgCuk6u#yQ;!H`?+9tQhH<bJ?!fkM_Gr2WSQ>9Y&L+l^&MGgQGo
zdx0X&S_xdWI~f<Zh_8CHfhS-V7)&bm3+&BWp0!{%?_gw9kSd2Ft(fhPrH=0!$}Ope
z`JxQ|S^0>mwAsAqa8X7~MT0Q<*y()bzB=M(Yi*M+oj?kl>L;{rq)Az3MOPcSCpqQi
zQ=YKGKt?qbVd0h_5>{w40-ic*EH@tP3PWoXtyZ;fJ-^?W4<^WecwL7WRwcL8EKC$v
z%;Xgoc>O_;-Jfs?;|0SqPyXrR&&eKzSU-{1q`UqW<Q;B<Q?_db7o|1JbNI9Fm1L?~
zd4~nPzB|m0Sk9d};5PbyIuQSHAT<GSw|V|i<MSg-*P3~WIE6QkeNOBjnCep|tPx_K
zP+95NxL^;wz5MN;a|Eky^~AKsu|&1COfM7RnI5O*>N*Yyn>;o}>jwX75^a0QR1^xI
z@e)VpZ1=zI6Sh0w=kD3yp+{nRa)tj`+ibGk@#)FNPap4!m!Ji5{ZhlMv-K;LZ?t)J
zu!?W4dtim6RAN@9rR#h2n@hb#H+kCbCbr3Jk!(6A(qa4+8f2iMTXl(X;i6l(bcx99
zP>KH))j9l&85K+QImg@ISnrxP<NWVOot@rz5dVjpZA86i?l72gjB2x+cOA@Id=3T=
z0qHO%lFhkH#}83`5|GLj2Dy(;$d+iKy)jdqDTg-7)o=+#D(om~HT@+ipZ)7+Fdz0_
z&ixY+K-DhdaVcxjBb=vEeM;G(Fd1f?ynn%cXp^QnZ}*E_9r?&ZV`UOLR5^}v!EhG7
zgXf-_n!X`8kxN1uu0r_LIHp?-*y#7eJ;t<~%Lw9tC3>GTp|+8>&|Wq>x`6wfcZQzV
z7LFwaOSza0=#5oCiM~q?zkGy^O^eOUL+bb+1l*lpY}gEn|9fwp0>R!oF;vCpCh2JD
z+$k}dwnMC49p;12=o!e0DWtz+nKpi?x2&WDp|)$o_h@nX(_~`|ms$rP|Gro?{#jcU
zZI?`S&m8VrAWIsO-}wWf7c3URguCTL_UVXXH-rf@l$5*&U@qr^39YNAYm>O7=$p7d
z&&oT0aliG40Vc&Ej9IreGcv=7Ww{g926Q)}X5f9o8JS$_wK4V+j+pN)xbI8ni|w(o
zd7}}XJF2^6geXM!{UpioO_P}M`x4^9qZnUA@VTbo!cjPuOoI(5YbQgtSmWn;7#ANt
zCNQSaEpndYb4<WtsCI0^Eiq*|(hI)+@r}4gD<%-2Y{X-hI(~9kp7j#UZFIrpEt(PV
zrASR7nW)Hbbrq8(orJS`V@(T_UtvP^C@H`2RlTVl&ii;fIUGn?uZI({3!V06Rs>7?
zD1wYYe!t74f648lEdqA-f{%4uSE9pIcHVAE?qoqMD~ZR5BDL%-c?gknmQ6nK<I=e1
zbU0Ct4|*(*?`5kK(lBJreWnC?A=KGXEsQpRK##zG%vyed56;rY)6dK*AZb7-^g4U{
zwGDFK0_f$@9?{GaR?)|SpF(`$(_hBCYKDbdPN&D+<67hLpS0zH0$6g{%gBl8bhFB>
z49{@=n!2b35FnG{D0$o3#ump98SiVp)wmBSCu9=zBiUt$^_H<{n|GX<YWep;h2Rh#
z?CA6unO6gAQ#3(Y{J69?dy&bn#>cS-5+=EQZ*5~>-2>A(RsnuDM;O38m8iU|mA~s=
ziNiOGq|pj%cX+$FOg7FIQX`WLh28_0&y}GGV}jjNf*{NDC(pvd$sUGF2==r%POvdb
z;a?pXt7|8z3Hrjot9LdlFHGNR|D#<NwEp#ejv`fMqk$mD;e*o?UTik9+th5*EdM1d
zDbgZ#=lWDrVo&BuM`7{bqtkFVv0;2I`9ls>5c=rR0k*zM!T?2;srMV=O0+Rk-XIcA
zE>IlVWJ7dc5yWs-{`}y7^#k}g)J<shN3X1^(*{Up4dK*$WJkp$-qjd8`&~m8*hw=T
z>;T4S2l(zFV%uN}8pPdp5_xGQnZfFbMA7+aT%N`3*&=nR^D3U1n4#h?Ek9a;V+{1-
zdca=!X5-MU2JP68qcpedzVOE?9Vc_-mK$l>mZTZY1NF_UTFw%|kXRx40i%*?L^G=x
z=^18KM9V(J!gEjFvAiEAg)jH$sdOIttdsqORy}Cs40DryV_FysWTzTzPz2oFU5Gi|
zJ{sn;yRJ@+`~c5!%ehw=wvCU9A{nCTWtESz^i0kSjn1%)dmEgwX;AK~mh!$`Z;x^(
z&9Qf{iSE6}^U*Fg`R`Yp0+WN=ImHXq?YELprZPQXMzK&SZje`)*RPfKUC$JeGr~6{
zF~ySe@b}8CGEGgCx1A0dXqk|LP`?<pY%@TD=KeDX+uqKuP8DNy(r@V#mwE#`ZMC_=
z1hB{r7&(w>c$DScvEwk~c^W-bn)Sq?;yqauT@+H4)@l_$RXPC?4}c762}=#sL-^$C
zZc)u}Y9GUoHtZ&}Xyn|8aTE>}{(9*lGCAu*Bjrk&DBEwVu2{8UM-TQIpsa)8FXS0D
zisx!`u?=&>Fl?d(?q?yJ%r}6j;Ir1e0Jt#fTKFHx%DQqdFtu!l=WB<6=#0JcX9;cn
z)|W~mC)*x<IK0|Q`yKa7x)_3gP@yfXZxcE6#1l9L4E0&6;00|IRk`3@l7Gm(iSO8|
zSONF<4xgfU{NPh!^j0dBN{Z=H2iR~~+Z@^N0nH<Yh3MGgdzR@F;%y*j%ovNGZ)%Z*
zD@^fA3{D1?!k({A1~%`lpPp#pazRa63xQ(T@-Bbf?39S0GV%Iip(*zJLw-J*T}!kC
z&|3R<@DNjE-5n8H2jZwNR_M_wx`o(@lJ=gvdy0`9fi8r&GHW{?s-z?UKIN{Cg<?-7
zWLB;?YnaXrvb)>Q7%Zo(9Hej9z8Zr6LUvA#_<zJh6@aIQ@;T%DMzZe%b?MY)gdKTm
zgyJOl<=lEwR!UjaMSerm6d*cvMqVV5q|Ha6|L6}PCx(gVBfxVjoY_zlbtwvX#@MZA
zG&alhu#YOs!!S41d2?JVsZfTx3MnHccHh|zV5AF`h)fjoMipKi9nY0kH4{U){!wEW
zfr(e&TnQ;85SU#Ee-?6kM%%M}pavhaLcgCcPgtBaOM9e+Zk*FmOUF)^TK|%!RY_yQ
z90g9#RZNcXGhH&xWzz1Nl80MWub)>g6La7y1U)taFI9}xQk(4+XDF-{wtg~ObHdIh
z+_X=M^-&tB6a6ki|MTyu#Zt-%x<`bS<?7P0T7uw>Z)gWoR?}Pp)&hU7RJDg1q0Xv@
zby63ioOh=pArsy_n<B@6pcB6Q$MKgisnA8zR(-FZ_d?sMDv}f$r+m9~=$tH%B;o-x
zUtN@J=p|Ez&ZnW!VKq^7DB{Hl*{=`KM?o5V%6?h~*_;c<Y#%ks@y@l5iN6dVBbvKe
zMCl5_A4xdO>4Nvna^AX|>49NZ9<%3qg4KglMQ#ObiL*?X_W(u-j8%yE#NNd4B1)%9
zJ9@Oz6V%i*BcYnhBiJhm7(nv1(2aLr#ibHx1D_m!VHJ9hN)zZ$vYf1|?DW^Rs`ifh
z4K$4^##GRtqbun(<KY)ny^9`}4fo>N5V|zSXSMT^eN52hO1Q<)aD?hS#+Q?-_pg9T
z4D8AKF|M*yecNMjeiDA28?ZQsFr~8qb4&9cvmmAq@p%rh#YslY-v9io)(d6;g>mZ8
zbfR1H%deHH0oKtPWeyh+-dA<DKoQ&U%N@H3O@e@O+52;N-N13l55_%#_?JkC|Afoh
zC9@UXP)Aw7J+fJZIC7)y$+ac&x*`ML+cT|EgCmAgw7_Sz%s&8;1}X%M4F4;#x)2Gx
zc$~E+Y4XUO*~5?_794T{%(P9%rE)l?;}g7Is3XHbssf86`SwT95EG!}(KQ#L@k2-3
z$2YH3lR*xbOl13zt*mtbawlRjRmWN+HsS1rvdoaN<EJksGg`NJKY$0GS*>}z;5^=3
zv<YbYhuEbbcMEZKors7_p)UBaS@OuX_CnG8dB*L;SQ$P{%*7&oIU*doj+S_$9By(o
zKHKs#e6$tpm(2GWN`+~vGup-dk&B-^`w)!s@mbZ<8yML^K00oIg9m;LE8O9PK)g<9
zGM$*~0JBK(KpC}4N8!tynOM(=*b6+XCsRB&m0~|tSC&t~y(oCj;~MBWPObNvr^{iN
z(cg(f_^mqT-{iyRHx{qk1K4Ly=-O!*#>xP<7|+%@xSo5}Y}E*sqX~4sai~ZCRdx>2
zcN|$sC#3+!<Kdk*5QK~<amsA@V*z9C^M~|nUyTUwG?`ip9v#Z!mDF|9^_vRl2D>tr
zrQ%-%h98#K4f(o5JMPz*9FM{~zbb4WCEx1!rEC<U%GXg+j&@@(7hNu^44(FkcdHUd
zzXw}hgpIWwYY<4!2%*Gm%M0tC^Xp!BiE`!f5hd!s!KKh?{3rda((r^=q)g#mH_O1I
zYNyvkt`~v&u*yzoAWy5zTRbV`I)1vZnSdG!u(ynqlYz(Xas{pxngL*&Az9P0(kC0%
z%7)7FKcbJ(SZ=>GM|{lF1lotl8n;xAw%a#DhUKV@r9=hf%{FRWb@EPFuObx>dl-&D
zcStD{&@M*RAOn}QVP9g`?_%sIJ=Y-Ep=FNEa)4onteCXW`ZOQzueJ<uPWjn(1b>Ig
zWrHcVB()Z5)zv>p$RW0b8-Cn5WIz2KQxx}J3QDvIk5LdP3k<*AJ?vGRYc(fvw)um8
zjsUvb@g)wyX{=x!WQhB<E^@V(;CeRhK}0=F-!+WzAhJ0&{cQIUf~TkXPdi+N^5ph$
z&(9iHc$cqeOu`_U?uB3N_y^r003VZ$<4v~c!bT7?QP~Onn~wGT-O^(^@!BFP#(Ud*
zLtN8+AvucvuJUE7v37qd6?A#xYVk>37JuR}-3*PDn_0G_4=zXQW8b(if`_OS2U!Z(
zZ_7A5)p@8b-aoOmzvwFOln5M0cW$pDqM83d@AgKeAyN=4qKiu7xxo<k3)@3V6<oh!
zni23wN7%-hrEh;f7>G&t`hXT#CdaW^(YR0>kZdw$Fo0N}0h>D9$Y#jEO7_a~q1@9i
zS>|*I5VN}-c+yX8bI<AvUfc8VzT^4F=Vd?Y1!fh|gDvNq_)pODc2qL)egy1)(@E(I
zwGKZ2FxI3|Y4Frcg6G=f`(wiNx@l&P+xUqBhfK<{8p)5n*_VZ7NY{{jdK<R@eHj$w
z#d4*ul$PBF`EXWP!NPLq+lBq$aAW?`r{4cbH{HadrV4dpD9&p*tlyKr44}?ddq1w0
zT0E|RBW=7673g0$excOcIQ1W^*O~KXJzF!qwJ741O;^wMpaX@Q0O^hZCxJQLrKdmA
z93iR;<|_84u%<IDUY6}GN<!+n848M(k;nCyWS7W;ut)fjQNwwe3#y`{O!^hjZC7;R
zTo@?HJW}Os*n1z}3kj#S!^#K-nsj?ef91?0`&=mj7QnZ47ei->`QVW>qk>NQMPI{;
z-${$JXMJrP1a-z@p=`ce$@fpGOOmilUbGDpY_oe-X-Y*h;701N+LsT1TSv{ht)8xe
zQ-VAV&#Efe0o_RistTuv4o|Nv80nV#zTs88Z#i?Zq|;KTttWnaHw5F%6}lj867uqY
z%fgFui63w#g3fnj+<^!w^o_Zqh&-y94`VKiv7D0~O*bmk9Eo)V0W5e8(yWR)P`X(W
zg+9~4;Ds}o=5Wh<I~XlcRuf-9Dggg764fjgaLFY-fQF0Q>D-b41i8w+u`zId+1T|)
zU5;%GX(oz6d-V#ucnI4Gcj=JVJ1@VtfZU0b2dFyzjJkL<T3KUw>sNX`%U69iD*~iz
zNYDEIRjf8}U*Xvp!1k;a_M2ERryj#lxhs$q_A45m<PI5#IEWKuHXXlU8Io9+eMpS!
zg(VlKt%tDu2Wcj=!z!03<`f$vx-=gXIJ{@(6QGSi?~5dVs0<cU&AYTHX;>oD<hUqI
zhTODcgBB5~j84Y7*DaTsX|nG*`k&tXLirVC+TsP}sb6&<$gC&a4Oc|^IPbp@6#rjt
zzp)9d6(-+XPzDMGVy<VN5BSaI0|+5In|jr06&xT?lEF0nN%A~EM1<lx!i%W1O0kQu
z;!?%SH%hob59`nS0NYh3S}Rx|tuPeB)i(8=DL>E{(i6RIiGI+%eT?jmC{PP)3M2pD
z%~zw~)#1Jt@D_e$P4;`p;OJ?=+b6dXJXq4#c-qCTaR)C*|KZJ1^)>cVkJqmYT#7F;
zUPp2H6WuoTWD7rUZWM|B=gKi~+xoa`jV-G<TK*vwAR)x5m;2?>^mI*{L0OYBld(Y)
zQC-b@;<o_BrH5>#`C4VgrNvnkQ@iQ_63-uJ^e#3s1Y1Wo`2d}VMdbLmgAysk+%4-+
zrKJkMf|-j{b#stWAh~qdSa3x2_=d)J+HaVIqgTt0EG+y1kJVXSLk53RNa<V2HC483
zxYnhkH%in}=$LhU8~}?F34ZOL8?c~Ka5yMfophEViX{&vank#WMOHbnEblAlbvoJ3
zF}qBvNiwR($7jK`;?jazG5J_}`k~UO&?DifP}tlPEO-Iu?e<x7*B1v~eevL+4r^s(
zZ-($;YKT4WEgMgW-h)Ow5m6wf)(A3QX+(SD_gLPf(gZM;wm24m;YXC70=($N>ilNF
z+?drpjmYikR4R-*Z4DM<K1SuIRBUn8`d(V^$m-`>sEF@O-&18zp++R%jXLt&MNwjS
zXQA@H#=4)TA5zjAMeRU9#$<n06xY!xYw7=w&w|;ql2-M`(Y9RcQ@(>vc5k!Ff<~2M
zlrF73RSKxH<y0b>^x^53JtJ(;PQ4zA$)@1V3-24BBNmg0XbO4aWOU26I<)F25`X4L
zSgGq6?i827f(xx&ntmw)l+#$>@x<JqAY%tdM@=HZuJ}&aO_ydAWpsYpVgvoqOfrg_
zo-!P2XAj`x;{Y_4WNBm!!CqvzO`~2rn0|QAM*?MH`*gtlPRa?J?bd=gZX<nw#j5w+
zMlsB$t=20#j0Q1hRbTN_*?jhQG*Do^zn#%nw#-IM`zLY5*Sd^uKd0#cA59-KCVL3r
zHp@Y_)O<|fnRk!?UCME!hx(P5^We$z&TCvx4QSE=Fk9`dyrY~|h>97wZgr##>wg?}
zx$dJ}XC>8vl)XUehb!s_MlpU}c~W5oQCN$z3$W=8JVqr|=0^IWDXD~Th!}NDpy4TP
zun+!^W`xsLXuC84DDr+i*{8@rDB%oi)RwT$rsygUqhPd(K{{b6){NZ0?(1`;RE7*T
znmCe%xKkW<VC2i7AeTAJF2O58brS_-dePnQ{d-(eVGkzHD7{n>KMa<~{<f(I4`=mq
zzs>GQ(7DJL^`IP-N<a#ZNJuMG@O7UlXTm_qFTOPnvR08SoK^%fZG>{x!3);wJ6i?`
z|NC85flwC@mRSN`hGcEQgF-T-)UWBQUCn;D+*^zys5rtpuPGY8OL(eb#i^I#%7p<N
z#OX{#1i^95Yny%fGZZhKafX%Uw2tbP0)K#?D0nGI`6ZJN!_}sXwE(vvwPuFQx0o2y
zLc4#iyi^58<fv0V?jr%y*0#zQkiCtWynPyjUri_*ys7cgDu1;9gHh3UCznMi<&puR
zMz$JI!O0g6%Szrk!2my1A#$z%5nV_lzq+glPqN3dXee>7fF0bvJx}HVr=Bt%mM<K3
z0sHiey?wv(5g)vF$0nW+K$BOgL(>LjS{@*wTFh?dM}9iy`x>9kkmM+aXB>0tu$V72
z!K{1aGjw6!-|-(;nU@u>&3v~RAW;&YhWpx_roPjgy1KKH*kpH*H8~dAlFGSNgfnYl
zdtwDQfnCPQgsop{r1BbJfOp<Fo1jUPPV5Bn=Ef@7czO~F8+a)G;f%xrX#c79pea#*
zslN{I2<x!jdks}1f(yBigL`6zmSelv(eUsj+Q}UvE?M16F)FL%VMAsr@?d&|E+F|J
zik%e@(g<Ry&785tPMFi+Cfycy%F-7n{T+nZ(GDQFHlsewiDpq<pnu8dgg4V_cEuie
z*3KHoHRRMhMO7n#7`z)rAY%)>^AC3wStYbe#cZ!<h^@QC{rt8UQ)%MNgLG}V0B5bd
z<D)d4Qgh$nE!Xsz7aGO9pY|>AzP(yVz4$p#9r@Dij3GPR8b?|YQcAcT_~XgwZ)P8v
z6fNkml9PG5xRwD(37;B92$6ii{QEPH*l)l_L^>9b+^5(U!z>Dk6Mj$rE3d7tNE}7G
zcV9V&ux*hnYWhT5@gy#QE%2atGz|T!EA}xmS<&r_7po`VfRZ=1`!Ws<eQ-qPbp#yI
zGV%JAQCr~$j+Fo|tPoYDxe{8nt?wFP?F;zTN!wPqRd5bWmU0v~O%eUw<zvm3%;n`F
ztVj;^EeAmHES|=63d}Z))En_E-|%$>)Fl&oNdqE@v`tyr)n}C8TGDesh^otCQi@IQ
z$J($hU~Belod%OzOzyvw!qRMEKv+h}(N%~%hkiE@r~Jq=Z1s1>tL%kE%p|cByk;ff
zY53o0kzamoIZ*8Gg<`|f?X0{1m#&B*J_iU#(sp~^05RayiHuHXVzHfTaD<92a%mP^
zWesVS-j0=)QEbzFGQYo@A2-4ZPULAvl}&rMqiQSsz=LkILUlk9C?_$nSb%@o4pRR6
z)AsXqn$Q$!xIfraX9)57Cq@5w)8pU3wMBm0!p=gPz7lN%VT_>IdvR~dgwfYJh2kd3
zQh&2Hyepkc-^cmh;6oTl6a=H9MU6iWk{8!m$zO3Ae?%4j*duM@N??Qd4~oyo2=jBi
zYTk_#+LXkkvi;b62wGFt@~zVoH;!`NN_oj9gTwZBIBCMp(mxgkF(9<^C4L|Cvo)yo
zi676gl{AO#?=+<nVPa}*4Uo<}vhL2^BdrXx71i97L9)GMtcZ9)N8J}TD|((}=9T&q
z!^(*d*5{ueK)N`0gwckMEHBF8$NxLHv2PEf%?f#P@`!U%OZ`M$o57TV>S50820Wf-
z@J+GdFW-#4=eba@z8k7DX=K&%`vNHvhK|kRVlt9|$x-}WHZLERp~ATG6W*9<1Krtw
zx-TE^$~e}tx<*FR2GZ;@eSKkc196wS_$Q}ho^lYO<*bF_Bf$R(HJ3F_uAk$an{k<w
zEl-_n4jjm-o{#0)8|KkgSVT`FJzNA2LE&hGHLpK{gR-+m@i9n(Ff(1{8?4qw9->B^
zvw(+J55vz|sx0F?n<8teU+II?TR#DQwS-q6iL?;Sof&365d?#f*|H3~)qW`9GhCh9
z7rVRv(KN6#qMSNXuA_bLo3}HHSVTrCIIwTEnI&^9A%!^}GJPirJVVG$hXgw9uY!|*
z6m(-T@H3Sw$EqR;ml{e2a%;2GnHJ?oIX7k-Ww?Cl&IWrJ+*T6?^cr<jv4~~mv`yXI
z4PW8iRmRNCUOUx9tIt^-@^=U>pmPQ1Y814L;Hk;njJoO3B4J#KQmr+rF>Nb4DfpT@
zbjE~-+c0@<uDgs?6Lu#9({mzHSw9zLFSjpQT;^}GRXlJl&Kgw>5f}*)4SWrdnOIJ)
z&tV?LS=64i$=ZdF#vNJ32*xUvfY`AX75kPFzbEo+Z{snFYyQzE>QmlgbXW6>QA?z|
zm*cgF^@A@Ncpecu1oI$ypFzYK5OnR;N(&u^Y@uWZ#1MP?f6@}pelg>vK5yu1w|M3J
z>Gr+kYv38K58X6$)#8u@cFDAtP}##v6G-zy{`?eT)E0qXDny)Cv+$S%6fbT$oIj8S
z?CaP0O?1FCmb=+Ky`@_(4EhW*+qFZ{al8?Adj5PsVT1&yf+(PvP_IsgZ-LBqrbZg<
z{g<XCPlKG`EDwCeU6XoHu{=3DKQv0LOfTW*m*z19@ln@-zIQmOGex~0TK1ETN1!fC
z;(<}*Y`r~sbaUtLv1q=|Ep(PAu{WDec8TQmh4oxV%oI#>5$NDoZde^ex2~92s2t#K
zrL>9Zgszh)fnp^G`8H^N-!j+adT3r5vZ3Lz2;8kO5k=awoD|6%Lmv$N&G*RSu_J(F
zO-o=QAt$KOFxK)4jkG<IPE4Q{OMakxd&v>R^^}_7E&~jIhP#FZ0vcdnXqY}>Gm|n2
z$d5%%MJ0=d<1slS(`no+=nO(?vt9uOc|s@1d|KuXi_q_U#PeDmEYT<VbBy!T)>hiK
zk2|tdIb^AyZ)9p<i67&4@~xg_!uZ*8Oh4ES-n_L>3>RHEeEtMEC^aT{SdMkU<$c)$
zfkuyKOvU(?JNghOgCo-Pe)EAM=W0V|t-9393Hm<t|K-fu6cqZ&8MHiXNUBEH{e+)4
zDX^QC!PXPxr@=EMz}F9VCn6QnHCHB1b*F0}vX13K5Oe8HF7W{*?d1ozMND1=JzNma
zIY7kocMkMMZX$!*8?aXI*v<Dkj!gHytf}wiG->kWm@a8Zv@VK^c++9bfiI}VQaFFX
z_rcust19aiwD<f!1_VM39s{5LEj@i9rl>>{1vXsq5C65=viw8P2X|RhLFkv!%HL8U
zYipuo6GJ>@S-1`gWntbz^+s7hAXUC!;Uoc#!&E9`97$BJ3oM`&TvR#LgGF9I*$F`t
zUm4#?%1|eg(KuU2MD1B{k-mmg2kq;-X8BE(WQaXQ^!b5=AD+vENC;HL2oU=@Wy&)l
z_Q6Yaizwjs7VOSEvk5R`+U9b#dlC`|d_#aQR330M*X%}A*dREqh!SZKFbVn@SaMfp
zWC#LH*?Sg37~ry?Y=T_{V^fbmS{`~zA>VkL)mvhx!goCkA#a#neJ`vBD%-;W`C?z~
zm-E~icn2zba8{*rrwN)waq?Th7dpv}jKxx?nUM#UEj(~zzMYs?ugGgw$lLgsIf_H+
zLeDZ*O7cxTvllceRAOfYc1#`)k=9c596*obJH1Kc=G7anN;DLbg=q&kRtqlpCJZ|d
z6CyOyH$)O7&^IrxDSiT!Vo%Fcrm8V?a}nm$huDu(!&-lNXf*}<ph!j;9t)f>0@XPf
z{#e4J9%fF&gG$Qm&k{>DCcEv=Q@5FDi!wAvJo094d*_ASGD`vd(3u1=p8nec*y~95
zOTX$65l>#fr|F|;N?At8bt-!Rmn)<sc^`=uX2G8aO4lsD76j!;*gIJ_=?ag|4p-U8
zs^#Tuw01%ya$xLM4~m%jyx2u~jAENpr0-S0xrs!1=brfC8z9`M6*tjJ(q-BO>sT3|
zQT1H?;JEf34}9o3nM-NCYMJfUe||3-QFejlXrQkD?^Tt_GEQ?PSZ+Ule`5(q`c5M6
zV<r$cm_gttB@&H5?tGK@5fipUayF_@&LdaQg{wTa?d{-Tve5wA{ePJtwwj*UHj=<M
z8%P`s*R^qF5O2`yqU_Sv8E(+QE39t5zr50JQa${Ff?2h;{iw}t%M*gbffraP;kv#(
zYgzz~OLiB|XT)4=8hS?(P_xA&&8><BRQC_dhK=7VE|8{;+y0a8U!p*3TXNG*a#Y1u
zz<2ky!`rEp{9vHM*4;Sh#Ys(3^<QizXF_ZK*%Wz|dJ==_3HJTb*a>%Y?bLWCF_!XC
z->hv|tME~eL~#%FhYqN$Z;5YUCr9G`p&rQu72l=OFLgQ5_$<jG0xq$x%%sM4EACdj
zG@sctGuW)~>P)r4kL*(Ri|MuLW}IQ01oZML;VeE#bfKG<rr&cf$*`DUhK|JPVCtC`
z%=yM0o$gawz}i-3QfKc);v7iRW^Z&~QL<CN+iG##7zn!Bja+@j_9B4|1y>eh>T^5^
zXKe!LPt+E|Rk!9#%v6pF_fBO5{N8?RqU6I^`Jo15SZA-Ti2@G;GS9F-IxgydHZR5A
zr_Y0HsU)?~6O3I~%!C=X#r@=JoFj`slcz@%6E0deI{xuuFq(>16bCGy`k}*3hyys0
zHu~~i!oX}m3Dt0<%7crY{+2prR+pn|kMa2s2-5n;^bRl8Fdq+9^JQLan@!LK0?|tk
zgivHNstjGnm*qIfs9Lv3r7eOo`a9K2IFqs)+Y+xKbGAfE`&8JN4M3MY3jM`es7WWn
zlm4FS)jFrqhZZ?Gt7T>nsK8ag5>Gtx{xZos?iR4sBHYOCK1%W&idYq(Z6@;mxXK-W
z8}+Ty)LNdX3hRSVtrAbiJv<!&5w@887c(zs9L+^<65WP%|L5J&Jr!n>qN62b%bJ3f
z#1k4@;{PN-`TA%-ItFf>zO;6{CRW?6t3MzP16s9%mNEU8MJZ7J<wixHYv4j$j{^ET
zoC&~zV>Fg7^6BP!yBoFlR$VV~-buQc--IK{EQh#iIf59vLA;*0(Wo?`rT=LPR&u5s
z&^Qnw3?b7qX!-KM+c^!t@`O+T%12c7t38USkNpP>MB9^b$@2`~SRXKc{^$j`2EwGX
ze4$1LrN4flqUfN2hnq_4`qeZS@4+mea!$J(a&vw>glu8*)Ow5{j>-xWq%eX$s?V5|
z5JQow`F6cM<wA;K;*#=d)bUZ(#QjA8#MS`GL%})53?Edw{U-xwbmRBifEh&#x%8^+
zR9raT-&L_MTJl0#kPg&z4wefqu91D>`IfHb%p(x~FgjqUYIK9FKn|BuNiqF4fePwA
zqwb&tNZr~^JL^AQ`(~5aK*-}WL8h^QyA;Q1m}S31UR?~14X}Wv){P_eYQ%@NZC0hq
zH%(%f7I3e2(B<Zfj_kGsua$XS&gafrX$6it3MLwG$W1aQofk0Z03+?Z;y^aZhXq*-
zh(uU?yPMG(z`uqhomO-w;Xo^3o@2T?o<F<LOi|UJ^-ZHj$%Fj$MmA$yTSxhsgDhTL
zlL~KO+xG5zs@(I)J)MHmFyR8w6yG8Q{9W{<PRr;<I8mb0su5%UY)^*1y-WVU$5`^6
zfU2j*MH~n_E?BM%fa?-mUi-GKa=vZYb@IIqKQ=G~0~?Zf=e9yhK*@?vT=IqJGRs!w
z^T#ubI_;K@<Och}1bfgtGU?pN#sUN1@3m@cd}4+Nm9qH6jqRl>EWk~#L4?Uk2yZa~
zVh-QPfOfW%$o=cRZQnAd;9f7U^s3!Y_l+HlIRkZy&3m$t{+JGfPOTv8v~YpU0CrM6
z*5IE22Tp2iEa)&X^K@92z^iTvMZG8uLN&C8<vwT=1C2754E^e{H6x2MzMbzCOOpR+
z{R}So?cv_}gU7&P(Od?tt{~9NO%86)<{jgc38_~kS-5=JeZj$F3~%dok{OIxLuikn
zE!LZ(JtP`OXG*e(`lx2FbdeZR!xzYP|0_johE3s`3dORqLEbe*3=fZ^2Kq@$z>GRW
zDXs`Zv`=$>{=O*%=mauCq)C$;lL08jjK8!@2n;0(u6sPvkPtSe*Q+{L*Wgg=e28Sr
zC9$YQhyv4TK%rH{Tt)1wV`;6z1O>J8{AUzl9#e}+ODN1#@~WBoQi=!HQI@19*+(cX
z$Jc&H*Wr-GZ7*Q<EKByTodeKIQ>jv6H%Oho^>wxy`mfH0F_&-ekalZws)wg<21_6g
z0kbHZZSpAilgC5osXTX`C0=aXty)fa-dDe%elrb<<MCn`kG0aTD%9rLQ*!tdb$PwX
z4i#2@+ke27d0M2r^9=Z$n&1pC?fDY#n(^-OzphM!9#@%45RRkAvVq><PlDYunStip
z7fn{f#NF&6WX?bx1u`Ydx2oTt(-cgsykVNbFZe2;c76<x;GiG*kE~XTmIXgKD<=1G
zXJRSFP_FsU12rtaRT(Y2^yI7r^l|g!Y?cW_0cJQDH=72@id-PXqJl;(96|^x`<OUr
zCfYkHK9^Efex;wS0&m%OYDuwz;Y$oi4Kq+`u0a*A%TI=r?T%$_K^&K!X*F`8C88{|
zgV9SUBu<JKJQx3UFzQ~e;TD@kffy_tc3A$Q9iwbWCrrdx1bG}`B!o&lY^xzjBECtE
zzAV9Oq2&H+AKk|re-+th0(O`HI^EU|Q(P><(BiP`aHU|*FW>wv`{Ac2+w}kdy}$qq
zoE+wN7Q&G)g%~HljVe%olT@;PGo93;ZkM!PX^;l$C18r#nHEA2R{l7H1xIc=K0JSL
zY+wqkoC#!fgsh5<=os9Pi=FggN<kCLj1FBPY)EY0Ir6OF5faP)YbWfz9Nqk0R3^f^
zQ;`_@LS+cQ*4pWe1ha11EJ@bbJS-bF>)XJ3+g9fGA9N?6jE~5b#r8$^J8rnGS#h-?
zp{l-_ZIUB8>QUTr_Rg)-(D|-#vSh+KiFJ+7`<VcfOV9uuYNHGQ*@i@Z$Bq}`b9x>U
z#B31z-RE{kr3aX>eEb8=cOUCdcG()K!@M+eI$>OoXDqIpyw7rEo&$AJ>x;LwH96CP
zEr*;Y6$i)3a<_0RT~MNeVE7r{@D+(3jt*D$x%|OxowiG(Z|SYZVI7*uTK6FI$rzrj
z(!7|M?Lr4%l*qHc^*Q-*q&ACJ7qDDJFUKkiVOqK8KXnqPS`A&MHrOSNl)Qu7;j)1%
zk9hqZTC6=ciWCa<|GRpR5<6}zznd+4VM85WX(_hi^EQr2OCyki<0!^$_B-6vBS(;g
z0If=VW&Xe2^J%P7#|QbA`GX4op{zxhyDgt<8GJIdY9X!sFi=vs9yS1_AdRWzd$6{*
z3FokR4)qDyL6i8W@TUPFI!uwEFXnpPTqN!h>oF|saa*%sKx%5royC`HrUk&?Lfl?8
zqblxt!Jb7<)9}AER(C5x$eFN}TVazJoht=!oKZbEqc$=hQ_HtglHJ*os8x5}Op8EU
z-KlfNba8VUYgqI{Y6+XL^po@3oTfHr6sA%ie7?fYMK;&}>N$YARU3X%#XVX6B%#$M
zu#~s%{4F_Ea*$C3GN+-c<La93-ORw&)-x47$7-JS7)cW!f#$`B4wdgp!Ov*t{s%mF
zPKqv34YTzVE6bBzVcLwR{pCkqz(Oh2OqIZ(tHvn|HIV@@5`x=jq$(KMNUduqHnO<s
zmAyclSTq)naj#hM`|3gV<I7OFii5}1pw=qCaT}zZG=<dBScdnG*8at(a51@rdU;yQ
z>4@ndzyI2rOP{VYhKf_K;7&x&`qbN|?wO)I!9_bp<nZg-Q17XG`{qREmtec5YpwO=
zShY#}_91yF%Q60O7i{2O`hKd4RGSFvIz7t(NY8T!YtGIh=`yqYequfi$Vyo9QI_Ap
z=FF%&-fVD)nzY?>%R_W#N`>q4oL$Kqjl%zj;}PLk#KeJY=4l)|w`-~)M)r(>Cu`Eg
z&8k+K$@gUOKslB-I52r#48aSW{7hI6-wzQZB_=K^a8fJIZ42~y=sDHE10SBmzP5UL
z`MgfS{`p6J#{F7SZuLm}TYKQ;6(<UUyWK~NIHS`(Jw?;nl6N@&Ob%2^G_+zu!#Y`%
z#Ek`0nE~$lq6Jk$1j=BH6MpReFZBM(H07I=kDEnV9zW_(tR>tP>ipGFP+ef>JR&TO
zvhv*PcDYO<Tm-TR)9)4`AshP*1lOpzx<Sx~S@LG<V+&*7cs0GYcJHSw(Hm-?T_<K9
zFwvU)rbp74D5E~U5ExNCgJx_RnI;g!s+JzK`P+fyfQaSMgz%VJMw-f69e(apBJ%+S
z^IbSqL`nH$=bbVl8PES}bBI4hh5>|}t;6}*aU9>sieA;=*(pB?S;VC=<Ge^BEYz5?
zc9bRj+DdGeIdNeK6$@fZ1za3SO6U`E^C1gDp61SoJQbP5s0Xw<MXi970Xzrqz6yJs
zhue!eK;ImK_wvW|tDo#KN`^X<)k1bLx}8Y-p8us9tiqI~np~RIzTp15wY<MnQ|(1T
z>=&39%T#;F=`g0okQEPty02pXNRN67v>SF@=jn_zVW8-IH=Qz;E%Tg^ItN>a)DYg9
zlZv42>S)p-dFYyqL5PB{mMe6w;G;CkH*AtRzE-EYmqdUr>t`ouJ8BsOB{&~=$-WuO
zN@|HAM8(v|^DQg+ExL5#kxNo&I)$0maiN<G<&lC3I$$6UT|S&@<g%FVY`&ossju0e
zU9Ke@=%0A=19Rp`Ogkhhomz{EcEvh^P2;-sc>N{Wd%z!3^tZ{i@Z)$#Uj7t@z!^eP
zZ<sEA<o@!oazODSZ;C!@RQyY(=uYz-;AC=vv1Ww5V<HETE25)GsBov|a%A?St%pJu
zC8Y=(Y*@|9ni4LLGnELaQDLoE_k+`zL+c3EcrUi<)2(_5>q5R${3Ys?rn>>DCn!9-
zVV;%*N<p}fQH=?I@N6dckw~(<ANZkQzPcJeoQdy~p+(=~$9W(cfh?E;+DebOLt`Bi
zCSZX;7@nnT6q};B1sUoy)dj+iljE4l>*#9W(sR}S#dY9eHlS|~krL)pH+Hos`3EMA
zd@=w6Xu96n2Hty~<#689=c7BrzCSl=d6%j`3<_w}daO9DralyDH;qmLZH4K`2Y+uP
ztTF;Am-aLuA;fe36Ymwq48pZ~k0;*ng6d~K5ghTYPV?d;0|v_shf#IKbRP-~h9@Wq
zieInod8}h*K=RqdOw`IPIySIOM&f+RUW%y*`GAAf2oAv0-N7#@4T*iJG{odcd)pw_
z5`rgiGhKG2w`3bGR;YUPCQ-kf{*kc8+E&wWmM*pKsrXU{cf6|QPc`D8T{r}fllemv
z;<*<O2$Ky$Gz@*hrT5XGyEyc(-1?3RIyXw^I*b|Kuzl_n>{CKvlpwLTPB?B<1=tWq
zWR(V#cL7!B8#yMbNQ<Eu!gEeR%cdi_E1Tj`opeN@TqV6p=ffMe43xr7Kv|h6AFHB5
zG<Lbn51}XwzYTO}CaZ8euJvak<3ZIr?AzHB0$aD+(o0Cyqwcxc?+gWOo6QR@3^*;K
zTYNgmxfFSMcje$OtqU0VEi-nqT35R%47Mq!K*wlq1Icv?l{_vmPI7Xi5N_yo9-V(w
z^O6bCs0>}Ps4*VGm*ei3;MO$qAMk0fkc>OcZ~1#oliV#338D;lgDI>Q1@=oIk7_tS
zD1BLYja)uSVMlh_O&~a5@}ze6<551gP6XmP1%b1J;=5#E-n5q~H*`^Xgy7CIv64QF
z-m72sH{6>O5;&UnM2VLil;ILUI9G~{s7h|~RUatVu(n-wWkB!rS&G{?(+Uiw9Lsfg
zD<dV5Vg`1^4mb}9Lwa6ZZ#>|mZ<&+C?obG?CPi?U)sHIy=-z#XH+1@J#P0iwDx*uS
z<D`b;2c?lff&%kz_>{<??GWwgmHK$o(asWip>7)c-vH*5pYOM>F6QfJJqE~*c<GDy
zOs2EpC00Dq{BCVHG;Z>hQ>Ix1y$rQw{EqoSqM)}~@?rM{v$4h9wa_A<g!5VMqlt%+
z1i=Hl5aqD;`V|B<aphPG;CkWp*r2ujgD8PrRDU<U)B{^vO+&5{M1Hn<pBWpE%(=4r
zi1V-@qfbsE^6KnW{i^2ZRLHdc8AiG2&ZwHJ#-2=U^T8R`48@}DYkP?oClIT-!3H?2
z;&P1Zq8=>uG|>&xYt50tjiC?(ZYN;J3x%Sk?j4HLS~Z-Bk?$NO=hQGez|9!aJGnCS
z&Q*DY%J^p;b|^QH8CX3us?1-&$8X4&Gcm)GY_z74Vj=}lhI_SHW}%T0%NrmcHEtmM
zK;wXo6!D>G$w=zGOiP-Jq}!M=HmM|5I{J6Rk7@epG-r?PxvYM+-G*-{jUTy10lVtm
z6O-4m4Hb%UY}2hJZ43BT!8nW$&5sLZEE6to#otNIxe|y(s`L@Hi~oeeHf3eLL=H(+
z2~fvfvlFVX6outrF4k7JNlm&$w8H_4yC&JkrFs)Q4G_;o+ZwJ*3l;t{jI{3d>I|yK
zhIVgbcoS{wDcgRBU~31^;ulV?t#g9@%5I!c(|zY3T%+E%Rhe)SGl<XCCjYZ^6~|YE
zhzCKmbj_rXt5FvyRG0JL66E5W_&ev5`z*d@b4Powtr}vM3)t0?gd&e<e-@CxrqjR0
z?_yLQE8(h#-{aVZ)MeY8@(IBG=|T5tJf_93MLPZ7RCdChl2t}^(#ehVEmpt-kmIGR
z@}@b~qLI2kOc8@Vd=b%t6yoP7F_BHN`XJC)NXbZ{WODfIT~T})&vM-nZ`un^-j-8^
zp5DOxAQJr+usNEtm5VxxV(&upD<fj$?reE|doZ3KW=TL9aX^$^=&(IvQ&o|O_06iI
z3z+JN?9a}G)-5^gejb^Z+1@U6-i<j2PRv;Xugo+mxk<Dd6f^7QLSEK>5?4VFUux@9
zn5b~AQ6RI+!X%U-U<g4btW9_@@46q{)?I|=0Z?JfA(m>pT9bNmzMY5MeGZr>z$gud
z4R9ff#Rv@NQT!z8IYUI3umAZP;+Loz3mQ-#0W;{-i-50=1o<+p@6&-eajVhebdrMb
zNvf#d$lPVKv*Yn)GwY3V5%;=S&raK&@ROD#mMIdKOBYm!&=yOLz~XsE>8;6pT2{a9
zV-cP8R#^(qoc=Psv3d{sW#2mYoJous?m`IjGHi9kW0Z)zA)Bu~Fs&+RtngkKB9WDL
zzE0G0o7G~A!~-)k5@=rtPA^Tj{;ebCAjl=}^s4<a?4^o_&PV6^Sb_MA5Ca0pM+ycU
zFI+|<5q;lBrHGw$1tPd%UVGuBz0X~fi+TVqHX`MIEeXP>jUvq11WgZ;?=vEApXBm_
z*g^_sSU7B5sg;ZxX0aek3__bax{>Y_q<gWFV&n;AIiG-nNJCyCSt>pcaWooK3^Z2R
zCbKP9!K*Za0@hJrP^Otgv+7l&6s(K09ge58!60)q?=SCKb{IVP)RD<gWK5t(?mr!?
zs90>+?G54Aad7U}^u)HYCe^ZRF*o1eDU9Es!m{I|Q?**aqXqN(ofnAL9(b2$^$#6v
z8gG@&qIvXt^!Z&O0;jkcD^_SrxjpScyEkI-e+%BT50q8NS0z#mx-JgC?Zmgzsa~^%
zoo50uzAY>TJOdB=x}!N9GVB7~*3vnw^;Zc#mIANLLVs-vGw&+GQ&nbNGAn-})N*dH
z^-37hY)jPwIBybl6alHO13e)VT_eU4h~)W^K!h`EX|?<oNT)7kugq_84Rs>mA<0pD
zja2Ban3Z#&VCccbgT#%clT*(?2eB8&k#rY`Jgls4<L|9H*muIf#t9}6OAMaR<%0)y
z>(61?|1Iv~XT~q~90hk;9vO(hcA=)PHZ0>w%bu)n$N@tX1#+j8I3MnpNwoW8{v}y`
z7VkD1aEXr+43zT0hNv557snTSwqmxHvPfD`--~J!kZj;#3+yPLxAD)b0boLR0pgM$
zwUMq*f_Kd0Md}=F(}GUTm~o;u!plXoY5MngST@mfX2-YG_j>7AyMy;q0n{ri)Os#b
z$x9eZM>iybZK{{k4&4|~B}jEt7=j}=UmdXklx#|pnkU&#PDHq=!{*;#q>uhM{#tNg
zwH0Q&Y0;AzVLsUX!IQ;7X|UDUKcU8I{m8Dm=vw?nonR-b*`|Ek=U~Q|`ji!E!ube*
zc@X#GfWuFwRVivPKng15EX*mG-a~KRiUew%_`QUXw->n!f4;8ZQ34SkItAZchvtHz
z0exO-7vv3z?cm+`J0Yd%ja-6*GGvqqLRBH-fqUoHLe`@>dJfkMR*zUU5hyD#6RDu%
zqVS7`>?OC9UAA&PfHeSkaSqfz0l3_5!DNH_Oxtl?vT8_b0-_hN1we1*y=A0Z7n0A`
zi>e0l<-&U<-veB{0IB|%f>YgHNI}Ym6Q{U?4)w?3g<0d4)5Jm|_~35S(u{#FobHB@
z)asZ&IKA^QY&5r(O<!e!z$T+&ZqgQwvkEKFxwXW^s)(--LuQ~gNA8C1ukTUp<O+7=
zF5{pn&{v29iB!D8wMLbVviRA<#MM(7=~GD<ly%!zCJOe+@L#o_$e=ySjUt__eT~02
zcIVzlJ1QN#M!9y?eQT`Ze<>{=rOjkc{rmyu(x!*`g9^GH@?Wb2;#1&l$WJLQq9#*v
zIGx&He~)9H8+FH0{8Zk(84`GU>oZTWL<lcqcgdv-J!v#lOO(5F2WNFxB>sfTR@(hO
z!^vIq5)cl_86G7jID$UnBqDs$+(xu1?()9>9>k|gs2TXoo)=tCi^^a~^gZ2Go#Nn3
zPpoZGeiw57NxU?gcS31F8x$(|V2Zi{vQ#u9+ol)DFrQNE^;@9Ozvs##IU%_a1qUXH
zm{Z7X0^{fKS~LLxM-J$%s^ehvlC)AB$5%n4{Y!=CCHCuBjciQOpPL1-RT{rf>n+I#
zqj&Z60;P8~yfg~DLtltwyo{)5plFWS#!|cQ2)RF2#|ZX8tLi9Fio$Ir$oB1h?Uk+@
zP4!d2Xvvb)rm**WLh#iF;^(fDF;Gwl$Iull>+(h{&ZAcGTys_J{;_6#7Z;BPH|>%-
z!&QpsL-d-P0?V_P?p7FtV&Y4~)o36T&<DsJl)CtxBf^JlynCeS^c<^otkf8@jm1%u
ziu@{X$w}w`Q7I#~8H97MV|%7nO;?9hmxuF!4)o!r7oA?gd5zan%yn%2<+-IZuRfU1
zg2D07znmSjTpFJTwcCyv05D%Rw6Zm{#Jwby7X<w+a6JU-MFpkM)i=mq-&qfps~Ytu
zAxwNww_A67==Q*J2n+b9%418Y=p!|T>-!^=<|{o<1grbGj9cpEfJBp@dm)-7K4)X-
z5i*EE^{W+9ckxQ&_9W2a3<eb-FPlM=Qu4>WzT#XL4Q&UeP{70i?bqu0qZ+2G%g0fL
zRptr~wZqoQ9}l-|OoR-MLX&BUkeEfdmBKq|b0?rQ-}b4jH-7k>F|1K{Iax+tH49j4
zswVtB0_m^=;ScJeT)g6DLI)d$!f2<Sfrk`I7_-C$=Uz){CV3<gjbrVZo|#^&pjQcd
z-S}j3N@g5OdYq`o!a@reve+6UY}(e5lip^GMBkN<Erp5gI!l#Rq7N%9l~b-@81a+~
zPeYp~dh^*VXcPjn)Fem3ENN&R$>_sY)?HXj<O&HQDJSGMc!vybZF9GC6tejp)Y*`B
zFyiVpG1vqmu#2R3(W%Q`e!~yM2<-d-KR9C-V&=kCAC67DcS%j@(sJu<w%U+j6VbA@
z8;YjUpwM#K4(h|}5H0{=qI(+%l>X`}j;=_sF>8GouNDL?BEEPcFhmfy$8}3;W=E(t
zhzIkxm*lak%|9WgDGXto<NgdD5S;iJt<YH9v>?%N(m`c8R{cf~OeochP@LkMfAdiv
zZQ3p&?jy#9IVD;xyrBWzwTQ7+69N9G;z%sAk>U2wqWI9=C+Wmg8-D7=D2!?S!3pr>
zePc5_XZ};D{g#5)whLl=;$LU09dYQXiFdW=+RDD(<#M=`zua<{y@(~Pv-Pxb>u)z&
zhBc<ZLQNm+h%5j?^%nx=s<s`$J8&?v=P!-OUyuf27@6n#eZ!S%bTT_LSenh$G^LK2
ztYBc|aJ#g>TlY(^jG0ULvB#e(9<#$hGi(zp^3)X7uoT=*efuLtUhne%4Er1gL^BFS
z0*^QI+bjZh6%%zb?Dc=riLe%c^SYHu>3Fo_&b`YF9^-P{>f_;!Z4yt?DOJApa0`>`
zQn?F<D!~AA-)9r*%G|S~!X1LbBWAT_V7d9ZUr4u<*RflP)Ic4rZ(<LA$Q(-ES4<pL
zX<78l)Tp0h3A!54o2tk!xSUXC?||%U0Rcy{O=1&?qL_9KHi2RDV<^rTF-TT_n-3?!
zCx+wW)z9gJP`No%pm>rI3Ha^^XOUIzA8RA%A14?YN!rTkr694IrGDKD0(yyyoiVi|
z889Vgfh?Nm>12&y8iMDqs0FAiHx*nYcD6Z|P=lWZg7Jx`mriW==UM@m2P=<xwlXUN
z_-oSw{B0;z5!k>~gF~D+=4~*~#A50f{dNTTQ%KS-49L0$+``M?DhHCA2DzZK#Je+)
zY<2+M8tvKQz)|~-q_L|+CiWgFK_$x#rWD_}Iw>i;^+Ds8=ZJwR(TnJHC^s0RIb{f~
zb$}Y?4%DEVwZ_+^et%UP)`zjJMs!CV-Ff$~DaXBT86w5?q8^VIUHT+lc(zvm<<ktT
zc3Yog=(ix;`-j>V1%?ZkUf56+>^cilJ8gmJyrWLc3oa#K43u%M0_Z{4vVtoEe`C}#
zyQJXK7*G$f<&uro{H;d*N{UtPqt%yv8@pKJTRsWK^NmJbaAqG{NL?Z+Yb9@H{3sCA
za^^$}hC)|txk==73}v4_-zF=kssVF|yy(=)a59-UhQ%J?&@)hdjRb44{^EQ6t!44e
z*PBnok`?g^IVs2IsAY~Cq;Ak`sEGH5tMBPz(s4xsop`Cu8;iNA%`e3wfC3AD<s>q&
z?}^ESKfkBe?h6CXBH&$UMj^|Gxfc@XK54HAX43{l>u*SK`N=N;0TZmYmm_?v3|O+*
zTh6y7B8O(f{V{b*etE+yyor7)bvF@@#o{tpyC;z2L1Nu9Aqk@#XO+@t=8;w98Rx2u
zeR+56{P>g5`2I+)MO1F|%!QgTYQFkM=%{sz<t=!Rk-t%HFocR;tf*;69j3Z)hxfi;
z>o9&iHVhvMH3}dW;=(GD)fo((H})eN{DqMlJ)o-5Ig7X2@-RsUaC;~2l{6*XystyE
zlq(1Qq`MA`LwEqlWyc`HigQsxc~%+_gcSZY^b=Eou{x#7r!R{BRV_-4VPpL&fhcs&
z?9V3S715-viGI!#AaK&=s<PvL_MkP)5S+e>_oPgb@{PBptQkQbEh`&cmZQu7bv;?a
z`q}+zLLo)4)|aeD1W%lo;aN~$InF3W%BR#7GWdR>ob}p??(-8<9UO^C+E^><Go^73
zJsoJrVMQ;ffI;WC8e_s+>#sM(A^_}x!U>{0lb1{|ahw`Bq>Pj)w1`knsL)un%)K<-
zG=HD@O1=tKU{`t62l>u)D4TF|6_JFZL-gA(U0PzTK~Zj8lWzZ#e8-hG0}uottn9(`
z&06PdQi}hgqudhYNR-aU)#E8#cXjRw?kP4v>mpTd><Q3V*{`+Tv+BnX7swlE(B4mP
z+iekcooAOY264JpVK)i^!HA~13o$TnBpKB>LHfu$wob5!TS3f2pJ?~27|OyO>9<d&
zimEll$Q*yh8fCgMXUG|UtPdpE_cN?AUc{Io*{Ud*XZ@qB=%Rb;X3|Z;q!|A0|GtLe
zO-<_ZfL5b&D}3c@2&pcf2R)cR_s>E(#H}P6QsM$TdTLsMiMIgrnc^YTmATrt0Y3Q_
zbS@?Oy;;9!zB1WD&H1d^2_$J^2Ksal%kj{dq?zUGSYuTSLpb%Fx}HFn%asnQMajpP
z0w&&ZIr>?S!MYfu+TDBcEw3=Fk=;;OZyVs8C+_>3Up8!gEu}yV|NB?#rz{(SpZM9J
zL^N^CMi3@uM`YxU!A8Y*u3vRK;tnSmJbO@l3i~2$;ZT$jGl#h-)tex@6KI}pe|(tK
zjdw_@J<!1t2t8H_F?-NQo~)MBF7JKaS(lCESq6`EC@aHP=qu4r86BweGdKx?kXgzM
zt9PjE*icuazwVS)L<SZK9Tp#sB8&=h!gLAvYM|1MeEDtEPiFD#SvCzCk}7G}yJ58@
zae%D$L_-F+1O-|IzM1mT;#TKLXF4pf@|&VoV4sv>F!XM!JmX-N4Oh(cY)kHF&(E(Y
z^Qnj4&?zG+aeRl#4$A1>FxgN&F%W*Jjx&3hPcL2EqxjSlSY2!u-U+3?DQD`#cR0k;
ztamJr=Lm{+10qd2{~E0{>0=p@C^Su7F4+OlhJIbH1uZ;QiFj8uoPurZbksvq=G9r4
zTP^JD$95VIAN6b<yf5o7!C+I^fzevbh_6FoX{rc=cab;#)naasUOFVs#@orGrGi%>
zpXAW6ipxz(v?PEJz7%^KF4PXolr{sQ&J(NPmr*D<qW?TRu$`(dBy>prRd!S=8~84o
z<~w{W#sLy!z!4jxRzx8n1M4x*i>)PPrU+^q5@_g|H-{QR+gP}Zem0&wjO7<GPtr9z
zht68^Eu|OncCH{>Yo)WpRATjO@}3td_kK)DXVW@k4<l@$FjDh^hCu*%_e^>ilrk@s
zdwO{2i)`xVGCD}_eBBH?N$P_;uvi#N#8FRublAW4Z(1Kd(4E0g4B8^<{7s)rD-BnV
zzQH@ZI5}M1O+V)6riKevGYQ9D;{Tl<L73lOQ9bTC!%htP)CAr+d~k`vpzgbMQgc8x
ziP-Z_!sFj!dL*o{HkxSw$)I#remO~J^N+~EtpB-;!xNiVa-(K$ow(N?;#FC|0{|Al
zl(e0nMtFu~;ud1e@dmmjA@5S!1!dN`iUooW5(yPk9*@ch0?b>QsB*X5jR=<nWz^fw
z5Tg#rWE^S}__i;nhY!{Dy|mE3${t54Jl8gq!5liFNr%Q5uFh?ZdR<Me*HMmu?r1@&
zNXkDM<^Cd*3(N~}vdNze)JbF$xt^Rdj={0tQ9<t1Tp0cVZT^0O=)%nv<=+Htfd&w+
zxPc|NhN#!Hi4VW6U&lVnVR3cdUFc62Y0%Y?<VHn=BI{-$Qc|GJ+d4_uUn^8)TYRm5
zMt%_)#`UcYet|iM*nBktuSuK5#|tlP(`HxVU{1LVm*C)Bv~s7TX+zFYc}JAVeW155
za9<J<y@nnHy>zgPM!{eM3LL8mqt|_Yy%DzrTib&9E>mFVDevNPlxQq@jNU4Uy`I$g
zSAOTx&{)Y%WT9pJ_seF4k$fTb%FBom-{)N@rqe4JQn9E6xus^?QfysCZ8d{xK>^s<
zIL?#h$HguP{4(++uO-%YT?q>fFZpRd%>z1fEQs4_lk5yuwm$!{mzcdsG0Y$#C=gI#
z1TR$e8L*)4`l0RViA4zb-bQx3Z?n4BC;#JB${H$vUyfvG*Rhm1O3Y{HGIT<SwNcqF
zvOv{_T4?Q+-5LD&%@UT0TT|HfZdF>!i?U2J(R#I`86RJJ<1;EkpJj><<$&h<+XkP+
z_7AMxMFqNJ=y<`w!Nwxyr=3n|s;2i1o_HsfhrNQ<VSHpGjH!c|>GfWb=+>ki9-p3(
zuvr_S!Nuf;-DM5k8-f6QiY}WieAEvbZUx}6Jv|69&z41Y)VW&Fl(soYnWRcCO~ujy
zFhKqt=+d;otlShVy~;2y-ybpvch$*!%0}~Dd?Z<}zT+Hw7H(j})6-14{ogHpJTyo5
zVyZo#`xKBvE)CaLc>Enu-(u`u@nzV!4#6rDkUa25Na)pw@g|(=a&?h?5VvvyqAR^M
z)-}4QFo?-%xBP&73pdxo<OD@~a#q&SROE(DW*-AAUgm!(>A1}+eKd!E0V${}l5rR{
zQ!sMuf+jOLQ-KscG4%_p%M2`HsUn*oP$rkJJ>qe@aAOlN*AeK2Ki%zj*~jLdB*%Ky
z0-4fOQt)f1dEeGj?Z5v(;}<w@YHMN8|E(5_%78*_KxUKhEdaZpH513|axykHD?nY1
z`}@1&gNCdL4L`_orEz#1u+<S_GtmGZ?-lf}SD45!lDaSy^Er^Y;$kWobG}4gWH2k5
z9oRjqqkrI`H~iUZ5ac`wpA6{+V4!x2Ykd*_LL>G8A9zrcnY05YcbWk-Z~^OE<O(@(
z`mBy?7nI|-b^@<(9dxmO1R#;OT_!Hd(UpsJTA~)A8|r6<I*2KJFTJ#oo>v9`FG8jf
zvf!kA;$nI`0#G8jY!Kl^tdu?VP}{<iWn?pCg<ugYl98_$5-m`HBRb*`0&$wtojyGw
z9(}O_D_0c+z&$0DB;f>0!&RY+8Mr0%Icdc|uw|&cjq_3%41f^}URE`uSJ)OR_zyVZ
zAgx7+3t=|^YN*`b3;p7w@L~j+5Nr)-OWfDT4&%rqbRhcIkjzMQS49!WWXPj?!^G<F
z<eq2f*M=JY*gND6dKC(L_tLh&PoUjUIfaKY7Lsa$3d$b^Zx?C-9zmO|SJf*WqPlnC
zvdRoYrqNdCYG^lHVw%wg0T~|)z}{=oNhilu0J#4qhv6!<<Ip-F1#iFC2&l4x<Q<yh
z_lg05?)^j@nUUseSf(}1HPDDVxjq%@Dp30jS=EDe(a_Jl4du)1mIsh(&zs{kyD=*{
zr}<W~=JEe#qfiJ?olwk)Q&;-}+q(U{zG~g{!pRzUMZemJ;Zmnqy{U4@OJnz4bEp4e
zdOc52MtLGCWGA}()-Bl^@zK2&#`{7Cn5dm^wWP2Mo%6zGCiZk7qqa#Hye>G{o*PcO
zv3B24%s2(I2|4l!T-!^UMLXy;03k7~wLHeB-Jb9Lj9^M=(;%rHyEa5p4hAjFRKqBo
zt8il~m)Yl31S=%=1$f~=t*&jT3@-xSY-WX(*?4H4H5;{=(nzs#P8-g7SzzoZfafj_
z;nkUU_M%w<W9hv5wp!J-;Db+Vfw*)0IyAYj96%D<spTOFb0+dZo}O&&ww?Ik)S*_6
zTKUKf9I%w}p6+!Xdy*1oe@|*eo?oVtZpMeaeVx)nl@W&)+$3)cncaJ~FHyWbGk4Y+
zu)Ze1r|s!mzTMoo>(GR(12yCPhdT0cjH~2c7Dr}U_gg;#{OT-YBBe<<R040iM?noO
ze&y1ziA2nqz%KzN;{Xoi<vkHTo8z+rCr!#N-#^Z2vJ&GX=9gh<WkRARU2lm;<EaHH
zzirs<AMn&LZT=??W)E8{wTLj1$!EwB<3J;xp1{_=Qh8ximh9R!xX^B%;73S0g%wVL
zNoD*gqU@8JVW(|pPRXdIU2RFKh__M!BSp-QQc}`gy!qH=&bDVxqJDmq5U>~EV>n1*
zd!G!Z<oAGuOGL#drBZ$tovMaM+1Qgy{ogZ4ZMbhcF26VQ$?$^P4`YnOerJE3O}1S8
zKs^SlLaksB`EP}DHFV?)_iBv0=^Thc*t3Zc+>X@JxL=yvO_*BOE2RDsV}p!D+hw&@
z0lRH3$m~^6CLrW^`)7*!jqfvhE=5Ii4}Y|XLZT;!=LP%nVq?tb7zpU?u!ZyoM^dng
zg%5Iw&lq~}%>tR#X!J*|%24b%>i=XH`T2yf;=MSR`MFSRcLw^%Q41y#1GvSIDrlp=
zFjHBye*L_vfjq~VgAX1cFPNJzAbUn1gdb||g~gmRCQnEr@`1p-b!8yV&*TA_8^1z-
zt>ptnG|#J4X`>O<&{=*>VLnlAv#8M8i4S*woH~#`(jYi5*!i8U8=;%@Xzk$G$ETey
zx_>x)>_fknm*&DihXb@$kB{o1kt7hJN(+Zm59{;aem@|G58xu#MVzK*r9N>f$Y6lB
z$Uxnf%?3(F0pW`A>t~K@Pk33|j#Q1qkxfXFrL;p+J=w8gJfe(r1#8cFIn6It^@~*P
z@1$dmHIweZ`^&tdAI$2~*K*!#-eOy1KN#Uj(!8Wi3(m2Xzm_VsMstLTw5~ZBn_cf(
zFrH3~XB4g#`OVZnv}lYu`6mf#^<_cxZEAy`01+~WPyd8-<%7$7f$sv>7ZnFrT3zvu
z@?;8K1Ry6VKYKJrDK`*Ksf!;u)<Y)&g%#T`XQR-kCIhZ2!Kde(&)!Mzg_&%N31_<W
z1ZaGff%Eq7*!7U^;Q}QE{F-<Q6$BBe+E=V}kM;k8CarV#8Z?Y)-`irfv5L_5o74!Z
zsUKSZ=fBbO!1QP{S|m=*a?ExAu~L8|i|hi$yxRFk1=XlP<X*S)*bbBgaQvAQ#xw3w
z1lc^V6g%rX`xL=t7?FZ@2RdqZ<K)=FXlKI5%4ZB{3rwl+W?*ra2m7>Iv7)&WZ9JNQ
zGp{m?dtctCXi0z(Xwuw!wb1Px+suIEV6KE_y6)n8((XCN+j~U%BNG*&oknU9dhs5T
zCD{eZGs8l)ImAQ!<I7ygaO(y~Hi`%!Suu1I@uMN-qZak(VG_e6>Qc-s0-AvrsXw76
z@x>9cCcPZ=Y?mJY=YIx#9_FElLOgYq?aTr1;W)AV*JxVf{<}0T){ITNrG#Yf3<0F%
zF<AiSbX*c)IjYj%rg`nbqDJGTX_P3D89pvV^wfK-<yoKcg?jOy<USj#UwzShcJXUs
zTRqBu9C243fN<~Tjd{ic@tT-6>K%2SJ|fF!Fj6nBWNh^825r^dP{C2w)lyBYV=Coe
z6?3@;Fv;tGr1%SHBu~v`Or2$}uhhlLy5_^b)enPDlcB#?V3Rc&u;E%*ZgriI@O9uN
zzbw~)i(UruwJrx0v`Cuy5P!Ouhl#NsJ$pPljm}>6f7jt|?KL45=0vhb+&rphh-*_#
z3(6hsY)|x9zLQ)CnRS6#56uILX(#Lp0@b(vUB7v<yiBotQ2!Dx>kkHjs3I&~^)_rD
z7dx-ppSGYeC!qR>AGkG<Mi2YGg|x{gkaBoMm67n+GKv4ot&s4A4XL||!WLsmW88HU
z3mZ8=pi+Q;_hD$HCN=W@KZn7Q^*N4Lqy^Ng6)`b!Qm7k;?~F1UvZwMi7CigvO#4w%
z?*3!5`j}wGCBcGR?dQ=qLrf}B%=7@Irx{KxfHc;x6cSZ?AGkrcRfm<y*pxnk3`h7q
z^F^7sVsx<if#~pSJR<KDjDteNc%_J>PdqMXS|LT$U1QnhI{QELEb`C_U<SGwWGO3A
zWk5)rhJ6F%KOA`1b^aM-;3KlROuIh!6&ATwdJCuR{jLFqVZg@Hu=>^FS0-l)ZXs6P
zB~qW{ujW$5@`cL;`E{AH@_C*lb&dj%t0@QnlpOse&{x4#!5~8QLUEg^sT}(fL_jU}
zl(QWeC{-kVI%34%u40^6Fi+t2C%CT?#zVHI_kqO_g$`W9tk#_NnLB8_Mqjt>HL3&<
z^v}A7L{6FH<i96_v}b~tr77Hhr5G9n*PI$kYqC=ZqPvA^C?$n64UXfH7a_uf!knr)
z--k<OKhx(hP!g6yi_TKI<>PzSdr)mxDzc4VS$TvR_GBqDeJ~@dhZc=Um<(M;TjH|V
z1Okqto-VD3Q#t3-3*DvRj=%MN;jbx~d0sE#Gt+3cm?_^d4^MM%asYbi!$U>(Lw*{?
z4Hiz@aujd)t=mb>;qV--imDxIWtf$!A~+sD{`KfYKi7YvAoLB50k)F?Lre}JaGbj5
zLmrB8OmmU%eG)$oTr#r&#6^x-B!WnBgG-J;SSl<&nqaDalsNa&rn03JYss{N&Y1jc
z5lubWa4?$h$(2qlGYxiH10hUon_i0;0H#v6FreAgUDzKsLXYC{zMJ&hK+S#VtMv7{
z56KCts|+#zU_&)v*eoOb#=KFI^4}Hz-s=DY3rqQ&y|&>YK#jHN*uF5u54=Coa|3E0
z?pSx<LP%SCBb=E*)p(hJPC>_u9syHt9O4v^r1oSf9xzpBWe*-|EP2fgk!_dka()WJ
zqg!w4cD?yzDp!eM^ysH6b%CMwYK5TJH$hJ@SyZ+cjfrW1jJIOeB&b7%0w#EzYX#O9
zRen{Mua!Auq!TQvTqGS7mJQRPrDl0$Z5T+f#(V(7%i|0gEDNc?{f(yK;s7fGzLJ)X
zWE(wy_xWd{3v!#S1h271i7XX~I6F^@nXW9~<g;n-uO;^OXO0B!*?;EpKyDj}Hxv4X
zK9DQ&IQ$T-5Ld{M6Io%PBp+JB0@LxINzpv%gWvD(Wz<N|naH`KAk4Z;+4V=%8<?Zk
z<Qvymv<+AeAX)sn6LvX1qSc*F*k~lF$~Stp?MP!TM7>QkHn;x4Bb~xplpiH;#E0T;
zCzIa*lc7MX{NG(8vp@JfigUtJS1Gett0u4kFnoc=qL;KEADX`m^6mjw?kJk(sWP>W
zO40D&L^ACQjIPahqSl_teu}j(!jDe5DDX~w{;xQvuF;UEEJFVy$^~)xGCbo%Do4bt
z_r|=w#8xRST=X932w_Mv2P?uqFi<2M6yvndLT>9;p15=erc-8}z8BjL2y>~Cl(LgI
z@#?XJ_^*{+yI%2pz%I~!)|CiVS~^#kZQrUi@I)9!#{S)=iCVAcwG>lX5sgX5YL%{_
z1;$D%a&=;VHGt-bCXAaG95~xqCVmf;hHR$jgFf8i1X1>p$qZ?fLV-wSWDGA4F!Rwi
zDL?o*hES}~^CR(<D^K#d99egVu*>&+JIqkt1U6YST<Bo%txQ4x13Atc1R2gRf!cSL
zgt4R%dAfSE!^`;-<wiFXLE%=6P;x(NI55BbP(G}%v!o8P(bbd?6bFt`?lq85=OAcV
zsc7CcMDl&)#}j+bO*hFp#E5fG(P2Y+x0@L$|7itbFZF}p<C>v<4mYX&IdNm3n82d)
z?qc~-bNl*d%Ny6*8F&GMuz~&{J8J8(*%wZuU5jCltjCXJVEQMNUqpCX0O7-k=Wp7K
zZg^6O(S1TUHP2`5xk>n6**{D-$`|G$Wk&j^lwef_V_rGCEvkFjEHRhEVR=o!EhcnW
z|Ah8o7wS6A7kEu=cc;`xL`)qs2gX89DTkx6dC{g-)ofH1nWAhN*CLjgguBRqwv5L0
zS7f7wi3zF5NHJ9uBNMiYvqU_d1epABmS0<jj#K9|NpC$H;p*{h+|!|x<n|-48y|fW
zw6sd5sZjyZOafp`wHC5D|2Nqox1EEU4Rf)m#zX2?p5?dO6_KqR)D|{w0Odqx4YKEY
z=Gkhn*fgGZB#|EL5*7st;^<v?Q*NIUim{?69n1;2#^6gltIk5Isx&k5j2K<sT8ORY
z^dbDLyUfaTc`sEMGe=$KNPUnXV%fvNuHThcLFMP~Kc4|60aJRtl=slPKMHyvU>Q!&
zA77h8N^H`rv1nj#24B!mo*aA3EmiVey`3Z=+5zf|TN;`|C8G{ONE##>Pt^T`U_#al
zjZ23%JH$l=&>e}cAiC3^qWw5T#<*i3HD$LKPmy}Qqa5@sCUt&^Bj;!{|NQT4yfe^=
z_zykH0O2JZvV$Zn3D2~dzgHdQ0Nc!eeQj5<#TB0dFgFYHsAxNYF1y(NO`&R#J}-cr
zpnX(psW0_IDZ5GMz!SRA7PfkMFJmBk)|VL1D?!*RYO=)Wy!qJY*!G){H&0PLXw(qZ
zJ}19jw;|F9tb<(T>^;DS5u0!A9%u}?c&CgkHcfvDo_hsBIP$9`GH9JjsIB<&!`xTi
zX5>+ob73<85CZNn5g%tA(6K*yU<~{bD8yn8H;x3FDsZDF4RS@dNfv-q<<VH@X$x#q
z^$uRt1nO%xrZ5u0K}qgMG@K}^*E1w{16ao?astt{hyVtCksCqY{iSjV-clU44op1;
zYJqNEB5Dh+sLw2CGfa>9>qZ03&nBG%Uy}zvm|YR~-7&smf@F-~VTsEeS~sY2R41>f
z)e6_-IRPC-0rkaTk4Vs1Q}RjJgYYjff%z304~U276u|d*hMC6j3mRw=Hv{-2T*t}j
zQQ+qztqMruUKT>Tr)lg2&bA~y!!Zg=$(U9k-#nA5*zm>g@+I6mNpO$9kGIt)B(b}d
zOY7p>e{Ci_{jwj1Q*_CH+@72$p~i>$V&D%bW-$eeO8>hcg!A3ToL%`=-PM|?tMgu>
zgqxpXfDy72a%^5Nr668STH&Pnm<BZg#M_R+qTeV$6aX-HZ#YW!Pa+52^QB1Nn-R{T
zM4FzryMV70gP#Z-l(*|dGC)G1mf2cXi803_aGh1^)usVB0M?j)`;Nx%=N6GJS0~xz
zH=%d{uF}0Y&G0n8=u+C-)h~2Gb=^!-sz?4LodujOpCNJ++K=C!M$Ci<2-z2i`97z9
zNB1&^%i1)_krNG2g?&C5)RZXS`XF~^wR02DH0O8#Miakg<SD&;hV?qpRX%K6pkjJ6
zseY*eAm&ym;p!y_KTwo1l4r+=jxLH)a!o4WU@>e>uJl*6s$1jNNoj_>C$MQbQE#Zt
zf^|h1Ag>ia22<nRl%6s%-U>3-5B-oc|Kws|Gxs^aMCgR6flLrJva2ei$-Ow>2VvjC
zdi4)vsq82-iH<U<yK@n<*ZQ$`!Af4T5xX6Y#yRZu@Q0%|%TmmdbW7+c&pYjVjF9?+
zNQoV)d-rHbv25<j$2-<@WCO^MnzoT%O4egj&Wi#L6o&etsRq@<p1aNr$@wI_E&Gk|
z>qv!0)6WOSdZ<ykP10PYcnGXX3$$O*eYnpu*P^d-cs4KWr|s3b_?Lj{@2)gE8p!zP
zyi^qbu5?q5kLTcu(UP2q27qh|EuIWkA_b)O#<daPnBk3p!0fI0mBxmt)2x9kYNulV
zc<MGPtW~eV2**<MMw4nCf%hUF6Y!wt$wudDlrQ}1;F^`MNp}eO(lPbx`9+9~j4N*O
zHBo<hg1@Eo$G}S6fo$jz#UL~4jx~H{(HE=)!{Eiz%`x2to3rO%Wpzk^D3~<tsD_(S
z6uj1=cX-H{^8xjPY%D-BZc+dWAyyTW$_Q+~?W3J*mqJ{bnFShrO)IHG-V${mJ~lv(
z{iGdTeEl1^r`{GCxZ0z+vL^zB>|L!Lf-v)M^Cx;Kz2u88;Cg&iaQ``5uAL-viRT9S
zNyqk?`z}>-tDqg0mgpE1_7dPMJ23SS)$H<C_C~aA09V(870FZ?)TCjX;FC$iA6g$1
zj4r+EHLYS~1}7ql<F32zqtVv-x00)TaKrv71vEYZs-OiLMsZgpCaxxk1tfT%9O`Kb
zIx+q4%R&sR_v9fll(VLnt}@Du`|OwA?YH4Yx=7v^YcJg8sJeH29H4s1DWPIZdgX_I
zi@{B7Gg}<-Q3}`ntSn0P)U6IYGmmI2a;He$u(6ld-2sof@m{H|m`JB2nfsVI*b}u?
zt^g?Xfy{ogAw@Sky{HKQ-q@w5VMJn<FFx9UA`@AJlM^1X`J;KS4mKvahQzH>bdvhp
zO&H4_iD`<#QqSGqNe{q%17Hhr%%Z2zvuSO>1@96Fk095`;JWFKIV>>u3reTqv@kjc
zkz~Y^LDNYn+dKlZG_ldmJX);7GFUa?{fJYZ56AVq$5MB;^53`mu_z9K5I(%Ar%vpB
zuVcrm3}JUg5$j#(N~iV6hUt;=)%ngdiiQiXbQ~#J;W1DJ4~uocH{eI>UT+>*gMTZ9
z=zaJXy*a2kN77`8fno5Djl;_2iG&=ut{ZCz0FvowENhCqL?N{r-A9rS8vONf<65n)
zV#dK8%k$%|Xr7K^mJz<Qh$Dq)*qj$<`BuZUNslH!FC089xK^xcf&|x5InEwMwS7#~
zNWn~DEVHlC8*IL~!7l+sh%G;>p6LY9g$%_?25fX41x$tACuP0)B?H^`^D=HC9RFAh
zi;qdJahE*s-A5TV6b{?4cN)ptC_BxBgIiydc=YP0O<UeR{V5;ysl|g%fv!|lP$RG3
z9RYUPVZSi&RRnvJ!RM`lcOL6KgFp~*dPROt=V9o6tG6c!K?;p-hr)q|?lPpYf;_96
zaF~900UAp;x(>hizNup;^k^}~!nqt}gcg?s@&o-@uaSpBAoI?BXC2;FFuy@LO-SxY
zWSc3DQCic3yKl@qny9QEf;uy&&z|xViOYKM1@6wCdJUj~poWSiL1eLxo~Yz%`vH0h
zxnudw<qV>0`;Zr%24#ac@vXl2uU{JnlDNaj#nXx@dPN)o?+L|RP#*FBzzD_qrEbT3
z%x3Zxxaz2H(O-+e0zB4C_nZ7ruBVK}6uL}SB5rPCp{!1Upia3alI|%q1HRWErO4R5
zowH^$m%(G~E(f^)mI0lffi6ywDZuRrGT^s@i8b>eFysD%pU`8r$=B1)m88oRar1Q(
z2eKpDb|@<l?lI?%QD|>t|BORlU~9s)l-pr*1kTNdoh2$gq;+5zzBOM^tI7~K5|<p?
zro)^vsoHIz2YNSoT5!bq;)fhyYk|M?8ZEP6X4AfVvH-HLVI^O@Czs&TEApl%!fHO=
z<!MNNW?1&8Vlz#)@!28WMh0l$yR%LL$bRDrzO9Y$BQ*>M!>Q2qju@Iuc|Da8f5~RA
zOdu38S$GC7*)h1?=1FF~so!y#SY<pw>gC`@c}EEzN*nMZLqb&Nh7cz%eTYYmxnMNf
zC%hB?75izKmRWU0=k2wu@{dkzK68%`FE$nQW}rm*Q8`hp{40+1T*OA9ZGZGK6KF-#
zfIq~`HS;iaTf~2>0lisBfaya5HL@7Da3Pnuz5ln_b=C(Agqz5gNKdIR7jkTr>^WZJ
zVJd0#criNp6rz5m&nual+T0=$zuemU04tp*<Q>0brl_-h?N`V%zs7tGWFb*lJN((C
zMqPf;Id8DhhkFG{>hcpGdiqMBPR}7X_+_SGoZqB4A8{@CD|c=8%MC6yYTt<c5LdTS
oa=4sni${s2S?5d6PqWz@5usTAf(Whf!>v>2*tz!G0L)MKungtIR{#J2

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..1978ac1b03af495ab810303552b4ea90518d25dd
GIT binary patch
literal 10472
zcmV<EC>Pg@6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWEi7X6Ux_2rlWuntR#
z*F5b+Qm)F%(;`A~&C4n}q9)bI?Z40Sb~a#D5w5$_&5^6GDIVv)WC=db_G7KKje-jm
zrHp5t?p7ROj3$bA|D_qx!nC^?^5*q#W0c;<+w2ec`eJu$GtaE)k%=+Z`c@>-HRp{Y
zEMLVU$?O6eZoC`dv7j!QN+Jhn$v5wrC5dyo72YPAF!fhFk^*+#4SG5jGLPe<ox!3A
zvzOV0iG&=l*#6I|SB_sezvL~f8V=#4y(poh=(X%8%-Nx1e<W%Z{zdxd`do<vo7k}7
zb8skm*_cIdW2qmdH&{v-p<cNJUsNMrScED6bhzVqUi3p{PMP|iEXq`sWmU9>PHM-A
zMVNY)C#c?H|Np`^sY~cVcD~%h!R|t&;~9n3QHjk;wURGPlS~&fB9T@Zee|#(vWg*&
z4ww#^l-$&@ZpB}whrGJ-0e^=T`1FD^G)k}E-jd%BGrX#k&c(J2!0oH~T%k)>6zY>a
z8u~`0<d~^15>#;zs?SX@vY<Df0u%yI4p^l?-n{py%A){UA`laeLpBbf2cL#fSKB6~
zx3r3G)QK#8J5{6b2-;pg2(;H91UH|K#+N5b8~6cl!q$GIWvWWRYCr`A#EO&sI2X1d
z9`s(-`TZ0nCCxJ&Bf2{H8kZ06`6U!h3Tmfil2T3{LM|VjXj<5ZZm(v7&io%=s&qI|
z<k0=T)eqE<tje?q#^xnUCooY_MSerQ2$IM(6uoN^t7c_{MbtzTeoVH!`IbM(R#AX!
zfdQdR9O@QEQAhr}<?7zNi6gL`BuTK@2Fi`T4J;H@|6I-@9Vp_^@^i(aou-j58%d~p
zfiz(sM6CX?+wrFBwkVhc@S_q3jF3R1dgaXlBS}fO*vf>?7J9we>!%prbdb%_xg&>P
z6woc|?&I=HJq1(W2mhiTq)-#U?O0c!SfE<UL;m!4rRBsS5yYSRr>of=HC+MJ@Le5%
zmM~i4lNUegkSk#!)A~=wb$oF#hDP^_7v2GH!SFyf`OVn9JoZ;;j3)wcEEPJIKu_Yn
z2@oVWZ^I=Vs-noIvf-0JE7FM<<6JE9Z4S|A8QbJt+rqHbkWoSDb!Cw7r?m1Mr4N&T
z{@gPVJhtyHvb}^uotjaNkEY_zEqF?#)1gE8HyIp;HTM|Zk^|-aG^e<I!pIv=`tiS%
zcNP4H!pL$0bV_Pp+MGh*@gJFZ1Dti)dIO(N*RWEMCCv6Y><7Fatxr3`tbp|Nt8c^7
zHWsN`1Bv2%4QWN##9mpzL62$!!KvO(8C#|WZdxOwjUy-BL;;xp^X4E}AK9e@rhRez
z-3wS;m02TaCU%Sz7GEXYbim1R3ezU)ZRQ=Wi6i`0?2iCfFifw6V@Rb(NfK^EjXdq}
zGkr(2exVb@Y45XWmMCvUZu^2cEf&eF<rT10S1DH9-f}iI3d%0Lf;!TN4Q0f4auHrj
zM@Jy6J7)bBJMkIxkW#VU9KGj%Q6L1pP`0}GF!cBat0p*Z8Or>Td759)l&(ZC1twRQ
zE+^!!#t{sG1%O$L584W46F4}CcgX<%Z-d?1Hc6EAgUcD4F%c|0J7bH#%*tV8>*S6j
z=SB<;4CENm2wvU4hQB#RXYv1fOvJ%H%==)bw?`MrQgRDb0^a=uP|t;j?WWpVSk@=)
zjz%U2a`^w#ttgwHS;?|a36ZRA?_lgiYVzD|^j3bgC)4xN7oS8)(xLo%8t#i3h1I6(
z0CalB^A19s^!7S!OI?s}kBSqZ4`CV6q4=YHVep(b0N@e__o}ClU4*!7%M1^`%{>}D
z-~w_agWPpx`S32$n*Xo_!E)A|p17&%HY{6rK@3Dp)c?5v$%kAIzRlGXkqy!%bZLpN
zA;t4lZvfuCr0VwkXQHByM7AceOS4DT|HtD)VMwEEqyd_#4k?tZBdLZA8Z@Pv5tANa
zZoX&}7u*0}05htc6co^}3BCAiZN6uK+ID#iJucUf^><vi*4ml>06X$xHfX_RGC<tJ
z$9kdn$NUj6q{1L(TIoSs2hDOlRLnd{oIIvK0w}BsH{Uunwx5tp`Tsi3nb3ZO{bHM#
zY))IIxl0aTerbCvD)${1Y87-`nj1fBByF~#@lc3ga{FpCi!(5~U^EX3;E%}396==@
zK!RW+-!3i%Op)r02*0&WLerLN6g3?GFI#Em$1>&c-He2iO$@DM??Q6dd{9&DG5R(b
za0T6ZEAh6FiVSI?-Ow&c)&aC}&se&)TeG8Ou~)`z)zZp$h;%Q4)7#yo7Qw*ukEeiR
zxa;{J!~22^X5DIK`v-HSM`>9=;pPi++4#su&o#iN>X;E5Z*%UV5shf<b=;DCTObX_
zPjC}r3xq2Tt%9Q$kQvl^L-1e(?T0IHRQR4Z)q$n*O2gw+D~B!X4r?NEJyDGf?Ls&Y
zw0^`*c#yqvLIaQmqAu_`NGWF1WKcYPNbyHRC{`$!h^6#fIDJJJ_tZ*g0H4|^fxc-4
z)v+*#H-3ir9r`^K`Hz-oxR<;%8RpWVR9X;hMrl~#9W+7JaQtyrJ^8#Rm^&q5Fg!PT
z`++#05qaxA57q?$DZ)3c$8f`57p+#aJ&h{8WubM7lN1{?YOoA<(~9o+y|GJ%B4P4t
zzKX5*SPqkrx|2$;-of;s?UZSpR&1>_gL)PWJFv=Ynr#URVji3HtJM@Bauuwg@M{j;
zG2Sl7Gq&`oh)~rzAJJ*`y>nKG8a0=MZRNAjhSAt|u88%h|7^ojkUbD=6&T-KcWPz)
zP77&0JH+vT<UeR0E2lo`w-7-)vpIVIFb^C=CF&gP_b$fu&~$LtZ^8JMsFUmF4TR@B
zm|wZFuhT{5(8W`dn*}$0kUq%p<T;!YGx03<M-`ldYxzlM?GM5V?gil6b|Awpi_SOl
zKB^&Nw%%rTSXKPHp#cI9&mkz9a{{@p@It(Wug+GOI?s@Ao*&yD*Bm;jRV#K)y=)4c
z>sx;GTrcXW5Bkhd>;SzBP|u1kIq8Ah*P+M+Qt!w)K=rbDjdCzSM!tR}H(~ZNuZ-t8
z|Hpo*JpK7Dvf0I868?rHzg<450gMqXEt!a816hb5COy>1BD_2uu`Jis3oIDOpLQBf
z>j}HrRSE?TS^dWc`AR$gCO|I92A4wdLyXVC{;KX>t`oeG<ex^2idUakFNL6-5cxQ`
zGAI@_OFi%R|6y|!sqnw8gTQXYOTs+D14T~iQbEqn{6$n`3GK>IfJ7$yYHP(1LK@F*
zAPRxXYL?U~z6p+i^@IwmqbJNi1frukUWzo=D|GjhM{gP(Z+ct<W+=Y$E;KI~og--a
zuO@#ievb&E7;1uA+urF1FHBSx!nqFVpv8K1*#LOqQdA?*`&mBCTk*Ks^`2U`^k3N`
zx&a7xBO8F5E&vZ$+*s9~X}x<kA>!E-q2U&uqT(=&yMuM5z>0bzeaP*bZ+pPi(-;!A
zM2RtZokZ&e4e6&FBZc;pQ1}|2DDQF(7}ke-|MEU*)Mm!?J6fj+$7BtXLdjePylDR8
z{b?NtzO%kQzptUcb|;A^)o;(`>X=7RKK(Mj>*02j;An~(3S8E$2`8h=nNl9!5Lz}%
zPR|{x9T;h=?Mynb*N;X93mxj3ish**C_#fRY7d$?aAON&=TG@KupoI?7W2AnE5Z9s
z9O<7hRbrOADJ~u>S^32u{!$+#jqQJ`0J#^X%RqGbTYw2kB$rqjEc#5%7nFEFj1<J;
z(%50+QXkB~BzhTN57C>2moj1V@4)Y>cLkqfAtvMRXL^mT5}p2~M%lqs0Fh4NbA&r~
zb~n&6&*8apxK`5nFYG{V7>Zuc%OVGMnD<##;)~j*J{fLLM`R-VP!izg97p+M-`s>D
zf7Id#kl~#suYYz=FQEeoscF)@Bxwyv__33`_8}v?+y>S&Z)hRcKKC3;gt5rWk67X;
zi{CTzs#*5D7%>iA$X}|ZSGzHQw&w#WFoO{2+pT4D1T9zG<agwxi8xtzlfCzbuMHYb
zVMl@H|4QcvI`plbeo%)Ncgc(dLB##%;=gbLPwTwS9zt#W<#7urn2=>>8i|)9vrY>g
zpG9aO=7O2$69gu=I>O2UPL8jlt_U(t2lYHF*br$D1WfskV#^5Ybnsy_37nPV=AlY-
z;%}|JGaKh&wMsX$nDIhk&6Zmm>zL$zkvBIQ+WkZH0biuDc77&K^GAgrh2+Ux>%&CJ
zD=Pj&Iu1A6*ybSv-QtF#ANGsWTRSmX4i46&wYAk@Acr<C&v`o(3`{DZEqludX9=)5
z578+^8M%a95x$~jIxTFtaC5qJ&M{`w15vnFQAnM7gM8;AzMB5eg*(<BFHgzL7+qf6
zL@_Epdyzwn-5+x1W*ZK~xtaG|6l|A8VYhh<XRILY8@jTt07=VJBzy$2V+d40mAR^A
zD@^Gro6~wct#_$1q7!%cg!^dzKq|xP6}i*qT|t1QBb63}1+Mrw=q5N@J)ycHYZXIe
zPia@(Pf>rT8<U;e^K4R{_fi36FPP<tnv0M(G4=3PA!e(o3i>DMU$bQ{+(<xcI#XbE
zwh2In8gMbG4UQYXbzE8s`5Dq^Qj`aeBsZeupj>76xrUfC-BTltd$bh_)oztD_3h~m
z7dY0iAEQ2v)(3KJYkWSE`bm=dd8ds5K82{>3K_q=hQn#k$``7GDi(I^!gA|)zqz|R
z5Ik-kqiEwXA~xLeRA!Y*FGnE@&IhX~!8n=AYz(c459aNKB(GHqOaG6Nc{2i7eeR+}
z=pqEHGZv<%IGmdZUSLH?as);r_W3`er}`%{GnA*xvWdCyFL%89DMw6OFy8juZNU)&
z5tHVT<xTsE+Z|erUdK5he*kA)fc^H~ft_STs~``h1#Ba9P>5y+7Pq%T#^Sp{Q$Z`=
zH!Aoy4x9=SrWL%iHPdYXiDkX=YVZav9{d=#Qq%>fiKVB}L<&d#lXP+t6~#K?B>PkU
z_;r*Z9QCa%8KI|9z@kGGr6Mj4^#6Bi-<4VpseSw&F8vU9@-b&t$^Ox#LSv(E*Eh$(
zZp=4!fduOKpNUmlG`1Q}TZwhcEhvnOny)&XHcEjULo}$o+^jW56sXn}iOl6SNxTqN
z&@jv(M4yhU^Bvj0KBc3he5hcjkCP6)6}FMCo}eXa=nA5`7OUt8*R5s^uvD*~YKv+?
zmU1n*=>1$hFo;F7b53b@xv`z}Nk+8S>y52X!!<+hU*$`)mlT%mi)yE!od@N!)GJ1l
zo-Zp0!l@vlSC|-O;R=uO<nD>-!=nKKnfw~^LX|m&=}JTgG2*Y`XtnbaK^{e33Vb(>
z{ieAtXz=99J2JV9|JEldadbsR`&}>K(B6LI=C#qu`rv$OE`DO4XrV`6Wm^oapiN2D
zkmI=cE({B%c<WZ-^P>ySzD{F*Ib7Qn`g1#5Z)m5p8O>p7ahFexA2(S9sZO4IGB&Hg
ztGYEM-Qx!eIz{Zuk;TE5#4k=4iqVh%Oi7&+o(p&ryiIpqm3)oFRT+4ee+qXFZuR81
zOOnOxy?jBg_tn5tc>3i;IpB*jx^_v;#U=0b6a5y%G5ob}|1S<9<3qr%4iL}6JurjZ
znGF!I!@n#?U34ROi^A(++4}vKGk+Q3^4a0H@W_v`3P*1?p`!B*w`W@nwq@F!pU?WP
zq~lxz=47y5hyvOE*$8wX9mKl@&{SxIfI9G1T&@QE@LwyTbQ~_N_8jxIH^mD<ZO9!}
zy{SR(k=ledn;0MG1ale#;^a36H;uvNpg}bu#kb|rVe}+JI;lFg5d4~INlRd_EUPfv
z;})t6bK{QwRU8(5q!-yGA;N)431zyoGYwl(ZX~7-yP;~XA!}D%K#+f5O2*I4uz-G8
zs2pVQ9#~(=(38_>-j@|_IU8>rHV8(lUZ&0_vE#7CE}s0<V&UVxw4Dh$h+6g9uiPeP
zI87`TKy^B2u5_Qz18scbiMjHo03g$N?RR;=RND!wx@5~qYaXf@uYf$^DuNYlawdiB
zN5DBOx<@4OYnt+&v?p?=E;1J(4ZBg25&u<X8ahMtt3F|-{^eLsmWv3$^=)q=>jNP3
zpzR+RqaL?=w%&qI8B!r3uk^QG<Q)6J25!90)%-W-kv9n3bOesws`#`v5|FEnjgY|H
zyG1a4`*E#_Mr`j=Zy}o<+dULNwQ6zDDu*?YP3j726mA-d!Bo;fm{i|$uKV@>E!aOC
zY8+BcZ;Saf%);mh`|+VcH-pl*<Pm?TFR2O;a%h!t=VjrR7<X&uP?Z|r`I8oW>xMM#
z$=&>PF#_|$$@v7?Mv{m#eY(OaU_k=<Ir0AK^xR^<y`06%*Q>k6`91LcfR_4azui3z
z{Xi}h?t4vvG_68-w?(^bblIy3k`E6Y1xGjj3F{fo0YJGQ&G2@*`Su=xEVD04f&fOU
zSeSy4#lrXijpBp11*P_ENrf^IZPe$7^cFwyiAkcRGi>{|H){R>*9)<UczLK6volb{
z?hdh`#b{V^zEmaVR*`%X-F%t_#v6QGz3LC1{~%TCw1D7`;|IeGE8GlYl100|Y=a6H
zi_o=yOjv^cltY7(snt1f@qwFOfYU<y8H5yf56>j_)&RJpyR>Iw7HGA-mL#V}ywv+c
zMyF~A0rYY#HpvzXEf-UU?WcVqZv^vib?}j#P7Ea1sbh180?R|*5=9s88rBp95QB<)
zLHzsJ#bL<J?tp83+&8?-7Hx<FMc=Wb>(R#o>5ai_>C*$T7}?$EJ6w!Uja6a$wPP2i
z<at9RIIYPUw-c9dVIJ0Y#_NpIW~=q8NduW^V;}{;(-flI*z&x6gaeA&v$kAu$RUQ%
z$PDB4J*ouV!8c1YmE+mAkFgTM?>n<;W_cq?OjQB-vAS?fkk7KlK5EG<W`C@SBISt4
zD-llo?>IO7;auEqEZiq4X1^S_!0o#NwZV~oUu_rxhL@A+jWwx$<zh)Vm<D51u@e5X
z$vogXT>*$P%%zegEPU?2pW^U9+)&lV(`@iQz1j-g81X3f36mJ97V##A^!8$D&AR$q
z<JH;P+*o29F2eVtq(@)r!Y`bj;7z1+^4?dRP~+@H)KFkQV8tEZ;Z&Tx4mi5yFe>&A
z4O!FlQJ8b;0{xVvaTt-wY~$ufsKEus{Wf60gHrUuxsBxidXLaJEu$pZj(RV#_&Ty_
z7y3^|pym_FtNeU%$StisX2!q^qcT6v+3=PXw;TVn0WQmiP(pIHcw}*y)Sqd5MNlq2
z?i(T|yBANBF9mO@#nFO9u<(#m+k%-u%;0rr&|rn~wie_f&0FAwIJ)-dsLo^U38;76
zop?u~uU#|`)f^^^0`lHcEH+9A;jUNS9JbaMxlB1nu#xqg_0OHPvzwATmP^yIb@jw*
z=21RF@xafYGal1kEB-h>Mc;xyt5l=oNoi+vUSRI!nPcHnuN&p`MF3*GfdnKP>iZhv
zl<R6bO`0m@rFC9;7Yjtf{19ugY9P)2g8%uVnJ9W<Uh&Y=A%MyB#@i4v<E!?xat36y
zHUsAQwYXolRK$02xP}11;inDW<7<(1<?%(9D3T7%ri1{?;HOa~r2F|tuWR*3>YK*G
z_NI6fV0FpJ{LU+v6%G(R#<G0etj{0MDrrrJtR{K}>jhlU*j8WcZF<nNRtglJ=l4&I
za4Nd@D%XFm*}ZIUd*a#vpYw#O;6^~70~;^AzQCV%vvRnTqA?&)b+}((N12XG7b#Cw
z?5I*fJ)@VK%Ob{uLPrcVBZ25h4R9O}t-Oy}=5}FFok*fbU3qxlOMx-jKU*7a@A^~u
z?_Vp5LCJXU;Bc``147hmFV@mfp>o1FN*O|I1wBEXg?@Gd5y;($Dr4FcYIB4W&1%AV
zpxF*}O{vWZt*&HZhY1tv86!_mZRVp`h2Zy_wy2N?OSnBlprV5jE!h4iW#2Q@hY7QS
zpbY^??_vrCj&kxts}}w!JcOz^n)BE(lxV{?NU_a?(1pCbC<)&N=kTl_WdHL;5YOkv
zODzi}Q;^3K-lMX@wvT4fR)ha9+qCW0UTE8}XDfsqtoV@@a4_vd|Ja}pLjO75pgWBP
z4rRv;Pa~{(Xbzh+A<37#O8c=gM;gsg$dg_Fw7mlKZ9ZE_AP>5BK(Z6L$-Z0R^&W^~
z*0@0;NeZvP$P?$v>9}E|-)Bf9r}<JqHV{9PP1rDS9;M);V@b6=c<=E`Vv(t!Yh^hw
zb_zh5pJwN;^+IrBW>;3)i$ul(1s7VYI2qzNgQ$8@;?v5-eChsv;sZUp!LW96Cot{I
zv$?924(~Dn#M-r;C+C`U<&}M)F%}OxeMbh5+aYD`XPToVER0}|?WpN(Ct1$>l8q}F
z%^b<V#nTSK`%Ba!IN65}%FoT9NduwKW3+f+tUQ`<*Uf;dc8hTXRpaIWVXRK7D8~2=
zBiVR!lH>4#Es@2e^gOpXxZexb7e`iVDn)TaPERou*qEfp#pB@&56XYHs167(F6tC}
z5-_Vl4eKq(xm8f?f<06x>3;UP!bu5JOJ6qq#&^0m9Nw1Of8$^;Rn54QuX?tIOl@v>
ziODN%4-a#V$A5OLOFrn?UA+^}+Zfyaf)@c|x^ruTI4FrKtR#f2oRgZm&^2drFsWV3
zt;t8YU(T?wp7`-ErNgTN*EDxXM#=@t+qR_*^HmNIf?iXT0<ZpQn7Oam_DkEwE5lVj
z8XyRy(jF1=5;DK(ljZd9H@s^GbZ0#}aQS=7P(WvPHvbx9;r!5+QHW}N?KOiwZ_+s2
zCO5uw5?VT9!;Cnko2rFrB4d~UjU?rhU^gsTi!<S-KG|Wo)6H5E>a_{em{nax?q03P
z+A>#o6qgz9iXu;U$8Z$v%W$1)Bc#cekYWgzl9|y?N@V<Ogt<>@>z&)`pEt;-h7<Ec
z@hj>TpD{)0Yv4G>(6AXmqz&B5>r&AQuFM6PNYy@Ja#%hcZ@82W3I^ne{Kf0Ji(nKs
zMo<LLt!*~1`Q>F+l{Tj}S98)`?C0gTAC)f1m~H28HRcM(y<Kon)?0G(6LdX6Q6(G4
ziN!Akm-B%eLWKQLXSIyaAo54OY99f0-hAut_S~D@I-p|-hPi74d|S?ly@(#3fWDU*
zceam!2w!5{UWVCY4z>q@o{02NpSfU}jzgAk-tmcKoHNeQP!aJ?NM;*UCy~1Ja6c>1
zDx~cB2Ix%4t=V6iwtY3ng@d%zV*t}ipOrkxCI>x9mB<wlc$8&NFp4zTWHjH_0!NMh
zA>1oNOLJ2sc;f;~mT)HFSvY-1eP+86DAwfgF@&=nSXJ`SVl)^O4xfS=;Dg9!W(HQI
z=`=gcKx6@f?X0~(%!}j%`3!Bg+{T4p9Zy=SRG>w&&js6j+9ulqSDm_%Us0*IcVh8`
za6hB=wmRp`)GN~uQ<Sb?D|mo0-kD0&B-g2RFX5m!qtGUw`rc=G!2Bq8@11Ogo{I*y
zh8lofNN04zDqJrmfE4$9M>i<#XaQ$(0fZF^#g`P~ewnfO2zdd&`w(h)fe%3FZ)%8b
zZylD~E-_MLAJ;V;1Spf(9KpdE4X1~s+6uDBNKR-NDq=3I$3Gq=GY@LqPj}@3mp9hx
zR~d<Q(WAhrz|0cj`Rhye>+g3pHv`jO)CpJtH523mU5{SK6CIOBW{dga<dTBsk)-%|
z?p#-fh5v>+^Y<Rk{yViaze!IgZZ4h#5<}mRU|8Q-NsYo2k77o>(&}y)Iy`KyxiJl2
zEle23%UqgzpLoRH^7CmVxKx{s^D+NO6gCl?DSooY%=%U6_3o(g$%iT(DUOoGveI}d
zo{&cVlDR%+$|}`x0{=9T?sgQ}fB1F=>}&H3`<LYK?RiS_nY=-~p9B1BrDUg$*T|X~
zT+S7fz+sKb&76afH9A@us5b1<eLzBn{m!3@-A_Spio^6I?`=w!wcq|oPXBM&{*S*N
z(XP9Fs<lAC*3_!&y#p{SItjHIV`@ZwQLl<BZ&f>n0Q&Wzm@|&QPfMu%-^Y_;IX#Ag
z3H@XK!wKRX1Rwg$b@vIl<9LPe4?bj`Trc~>Wo4MU63Jxgjv`;N4N6t0lz)Tm^A*G$
zS{W-V<s>$%?ewq(E4;2hu5gm~r#3vM$)ZGl&NUvCsBDBaw9n$+C9V156L|Qve)DSH
z^X1r&o%q8u(C=bIY&N0>g9i=u+axCg<GzGm_Z)E}VBsM!RP%;-OF6}v;tpb}(E_!p
z#AzqruuDElFCw{aOCxss!(};Pz%*=v8Jy$^i8XAxEY9Il{pw2VpDz*XRHpv<QDYLs
zC$jTp79UJ#dbnP@ZCyV`e}4VMCiKz!_o1B<qx9RPxQ=^bc7=+5n4I(JTOS<pd6HrW
z3v}nG#6?Owbiuaf4;}^t$L^Foi-1k2yh6eNm{UoylLK&ffgGQHKv7c|6QWAnRFz!G
zxdjT$Dv_*XgQgQ@teRXEIB;srF$|n!>P<g{mK8wELszvRcO25fSmnJDh!cL)rT4cR
zg!kQvqXPt$Tqj4nc_!Z+G?4?_TcJ%P7`ZqXFE(wHiJn*O@ev*uI+(sZS%)(iMH>B?
z5eFuJ1l#a*wV#HAVLW3=DFZ9so2H92h&m3X)e-L~%%O+SO=^t7xKy5DB^vFF^SbtB
zKi$q4&z#KrVxW=9;X%q2vtD_Jlg?4+VyHEEC$SK{k>ZY`owR|L2P)<g#Kf0t^=qP_
zsF=01tFchA_tLl$xo$zd+|e9=j+Yn46V{tM+l9B+KZcv&)hZfK^P{7zGz1EQYxRhY
zn8I>c*`r%rt>ufSGQaZqChF%%)k^Gm+L_X+#H$_k+QX;|oT($I@#F(4@TLRpCb!X;
z%~#QTZ3}oQ<D_q{G};VV=p|U@*qUDIj0zq`1N0e&))i9dGEn8p3Ow(PSe-mXv5d%Q
z>n^!hQ@slE40(Ru8*{ZxU`+N^G{NJm?E&>&tcS9N#F0_frs5)3{<yVXtHsqzhs72_
zGpyt06H5*dE5gfH+3c#1)fg4+&#*%UfZ?fWOZHd@x~_T8)Lb=A%u`oOkx6T`{dZD6
za6+SUq~Xdv-$T8I%QnSwf1f*c-<eRIHK}3~ZZR7rkG~Q&jq#WRHX0mk0k4p)EsY;5
z*1r4RhIYZqI^u&D=-+Yf71Qu{Bvej_N<U#KbqRyT!QO3X)S=r})Lw(bDKu9OK~k;K
z2-ouSh!H*7F@~x0eXvcw9iSZuD@Th^0yW4CdA80-Dndy_1?aJ8nFYfZ_o_`7Z$o@#
z+j)ik9%mu4YNKUKMb#G_du<22kB(<s6f?;N{kv7*l^}TjuFey?<9k$CG+s)wGK!(=
zD##v~UwUb!afV>seVgXmD&+xf{o&T`=x!+atzN2&F4G%Zj|e4h0O8vpifh6FFo@Do
zk<Cox;u?$Od!XlxggqN^hUf1tYKHT9)zKO0bs1x(ixj2&hZ1{ev1};nzzm>5Gx;fw
z+}AANcbd;}8ufUfKPrUS>+B*roR>rhRRI>DIEd=kDD)*g!Lt-q_ZkHhpkVvC5H*_j
zt`FA3>T%DpB+<8=ivtkFeAzRS?Q`l(zZ-Anwtmj?P_{+|T1r-E$+=)Ckfa50NE$A^
zkvwuJjK71+1%%|ezpR-0#xH2O6Vld~NunIF1jlznXC%+(ZV#dgC+b!hDh&(yQ+3^B
z#Svxx5;>_7`dryqn~Gmh#dA9LW8<Qzok6br)(1Ko3FdINS}Sd(Iuo*KP*<(yVvf$@
z>)n*l7dKlt<;^DMN->n$Gt8ARRzsuh<f_N$?k*~=C?72$tw|*fxV{4tHV=b4pIdBQ
z6S3gulB<4B=CX({B@G_QOI9;5%LL=%q`-WtzdREHKukP=r9YP*U!2w^D^V$Y@?!J|
zt|VjxuAJwZuRvaq+6H5ABRU!GB*K<E!6r=vP@(H`#Zi793vbUs;(Wn=A5pJZU}-ao
zF-0hGSQCGy|2QS4?UQ2?$AL$Wh!*DEV;#0vn54|Oz2CCUyx)d7Z(%&D5U|sfILa!g
ztn@v=<{Nyw=1R6e4|){jSv_BLzHQr$9t(rApaM-gz5i*ROcSHVAU{>;`-q9HQonQQ
zOO{4_DpD)=>8(1P0;ldgtCHICRjDalCdx1^V49DmscA?N#S=G*eq$Rl?K2z5@)*1o
zMq48o&c^%3#JNj5Lq;8xsWs7G8=SHkVPgB;hb<W?ioZa^IYDY-56rRh7xUA|07idI
zy|3X<(!qmbsHS;BUBcb!w}r>qx>+urT@iDf4y0ixE%ZKaUMuj!j7PhMHhJ!MNh4<%
eQ6FjDA7pLmd;N#?V8CKyFY>wab(VS<Gr}1BK27WZ

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v
new file mode 100644
index 0000000000000000000000000000000000000000..08b1512515b456774397ddc1a546a4c5f69e3fa9
GIT binary patch
literal 12256
zcmV<6FCWm06Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWEUk8-L|ap<yp`mPr<
zQE5<6Sn?%<57DQCZ;fVDU)6(Ns*3B_ND;ufQ)^8NK=^(o`}yd%Fc%2s9P(^43Uh1f
zN;2oEX9K9v^yneZu|HCgV&uM-`26<1irx%>om(#uNU?y|!O*+1*aPj*5NYJ(hwmj@
z86LgK!`%+I0J|%0g7=4q$w;8m{k0Xr>q_{j;R+W^H_7V7aHg8(rwm+oe`J&XZ0j9T
zmxdf{rzC9|fpo@|Sm6|0UA8Th^Yo+%n^6j2c|t<bGl47Bg=M6=pL6Bl0z*wZg$fY$
z#H0_)*<OL+7@UY*gBl5g1u(~7rz`Yir1rO9Ma)R?*(B|Y$cW2qvG42M1!$23@I>W}
z(K>ea_u-lr*Y}D81Smn@I80{Pp9SXjBLiUpfv7ZRY&C-w;W~?PBUE?SfOS*01`{iA
zIv>aBVng^Y+lnYhcBh?25DwL>bD~Rj`JdU|Z>#P6sAxk~_}0PjzI?sh0N0e&NDj*X
z=Mobnba1c5>j3?rOta6^!bdx4$!cT}UkN#o*&Ix?8C3E~RL(#VL=@)aZd|#dyc}7Z
z7xQ7@A4jRHVUjCL;;8^#S$>A0y|?pC{>v=XFs4p5);m^qAulssu@ve%`bc@SA5U`@
z@+dT80Psr<gw0&u_s(LlQ*(}=%~GW9Le5jJj{HGsVtqE6Q@hN5F$O8t*?^;QZ7U$N
zX~jr=b>h6Z;Szj)`u5Eo02s$|qhY78`LGoy@pSo4YgaH`RM%gjDfUg5k&RNWQ(%P+
z^Pn?G52LP5w9khww<N|ZodJFRD*14A`>Fz7Obv9wP5dxd9y>AKlI3888klEa4mS|#
zDz+GBh~Tpb8vwa>M>KK$r4smV;wXeLz#9+J1;6g!>bm=6IzDr*fpkSr@v=8{lLGAz
z**HEyY6+H3BSxAr7!BTNhkTbc@TUBMw;2aEyw%$z@>T6xgopuyhc7$G?W52l02Qnw
z{BUvwnYsEbSNXNl#MJWdYySm3LO8ME%s2O~d|#n_qRNx?Zs7a*cg_8``It=?Wn(JO
zH<y)+%w<3j@-(OiMDl1ZiiRTSDA@1<9<QkL<d#V&9&iT)7a~Ra&K8&SXwHd@Gp}bg
z<6<<6m`%at;)EYPT>TbbkRJLi?1F^~KP153N=@CQwPd>Ass;Mfx=~2ji^0M+y08|<
zGa!;3%RjVKDq%eEhPEcrw^(yu7*?q4SBrOF24rCm?QW~{v7E6+vGgec41Qt5;zj>)
zdt}yabJ}a$(ZYc(jcm>fTUaul9pcb&usbK!xOErTS2dLqnOH-a=A!^5@(P3du%*|e
z@mYHgDzml55)&ux6oJy&?49B$t$_ea`|nC@Mu;KGKnj&Df;hPaE)b|MldI4+K5Tlp
zTFgwtc{9132{jtq?<=ai>5i;klDPe4qU)0JVJg&WpMQ><(?qCZaqxul;^!h56kM{$
zwIy^b96#J7$9%^5^cNN`WJMh1U{RcHi-l!%%8^`HM^yR~MRP6=EDEu~A4~|QO$L|}
znWsGy#zZbr6Qh(PCS_3Ndz^0~;ioeWo?&(;O}3g(&m3q_F3K$Lxx)HVED}<_sghJ5
zIs@9Tt;t?w+KO23kW;cwM$gao36m{5u%287A00&QbVs!wBROiZ4mepqYT^p3#};OF
zG~NCrDM6si;%NjX>N^xQjv3h4hq_5ChMfAj%;-xe`otPc*#Y4ayPZl7yXq1|lmsOO
z0C&@a9&1|#(M;|>^!<*qgJX(f=UGHh3I9YLpI~`j@J{qxvFBDX_h<&z*JsGZ_(D~1
z#UmjVca;4C2LA8E`<KFm?ruL|BNZ#D#l?9qZ>u-lC-kG4M0j>MZ$U{O`C9iVE5?<f
zrfz|xQ1xnG8_lq5physbkHi?g|Gjrz1(>&I9l@s8wN?f*$PGiYnicEfmy!+Zzs40H
z-<5(>$+N602k=K8u;Wyx`{L-)I(b5+P`j9;Zjt5e`n5pRK?PhgF9B!KF}3s8e;`E;
z$6o~eXJ5jCe-Trzs21t6+{C6!`Aq4f#?<zw{&u&QFG}uSU6FnhB&_;_IBB28DFE&X
zX|vGU7dNW<X5s?EiZtNe5F*WbITTpT)pYeRg&%4^m^&dY<yL;yQd`vB@T~YXyRvbS
zj}Zpsa+iv|R)lm<Jq1B2kiuXL-oXghmvcQ%oS>L>EFsxfx1;U<+)>o8Jg8>%8rK=j
zqNgN`X)A;4*<Gt83ZEd#qd?o%Fv#!6($AE4khr`DFKI;wVQu2PqYNI{*tig)KxCtg
z{|_E|nuA)?aYZp|Fj@>ej1$gL7!T=kCAAw6$63mh{M)eOAR+x7n&5mn>i3f!L4}pe
zOL7#OQiE!^B!M%i<u(YYzs7>7qR$zzSk+G+4!AC<9uk%=Av8b>it)jMP_ci5O1ytU
zf3asxP1vnxy^_f$g~V~+;&%yCL6$5_`kmc0=vQpj%zk}%I-TI##)!t)zSq^fVi?im
zMUX0x-|fjJjj<i7SVtDO+L!>kBLyu#EtgH%#W?Vlp2yiumvYonI+C3e(TDI;BV$Pg
z^{zY#@!OlKCuaqpvYg;KGo^>Et4Hqfm4Iva?fz(`{y}&)l?-osJmOIlWOU8FBRAnZ
zEcBgnsuoHEz2hMl1ZBCd>);S2Pzx~+N9iuA9b8Mc(l-YsK)PBPr+z(`P2Ez&N3R+V
z;T~*f;k+<<{u5e~qN7x1(D)ce;?I*NN|Wi{%)7?Op(HT=gu;;$Fw-(%@qU-EGL>TR
z4H-YLl)$T^Dfto&=CK6-<2_`pNAo*{f03h3N*!-?t>0ht`MZJgfdYY5!xuT&xGm0V
zjKlCgh4Tyl{{wco0zQya4~7b+y*+$qBsJS^G>wP8r*munR*#<!sXYFXwBkN>Mq--i
zPr+apvh2fip1&!*Q~%1q@=^9A{4pjP-Ea(gN|}@{yW27;UY|=g$_b<NJ;tdUibh~&
z7#{s5FoVS#oLfoTnkFq~ad>Jp;bp}Kzn91|U&#i!y_uZ7-dm^Tr5~jUKFFHXw;bLi
zQVVUbbz@eV4ckX;e_Sxv5J~K=J?qe`xr^#ax>su9CKWgow7p1_5}8h?Sx;M=`rz1(
zQim(YBwL+`*N<L9#^bH7H|54m8mZ2Mhcz`bc)x!G3z*8&D0!JfYwqS@pWPXVY5@YF
zwbo>~jQX-p2M&j_=PQqYO0TB9(Fe?aF+8;Zc6ulL04;Ia{IYy*KVx(a0qZ$e?qX+k
zLtCf;xYkPPMcIy%9NLTydi;M#rz7W-QuWZQ@$j8{@tA|rTtjp70E%;@=p4MIr1u7j
zP$s#!Vb2<#T=A_v<NX0)SJxqOZT&1Rsc7<PP<nH{+yEKB?Dr9xMqd)<;BRA7A1Q<u
zD!Hu%$84_M#A1^VbfS|L4q5{g5$KgSBrvQG-xL<h4L3AiPAQ~thzZ}Xoq~MeoL2d1
z|3|L2d^^O#mQ<`#e+?>b!sY?6jQe4XI!}x?49lt&gv;{*N_0`@G00w;&V2ZjraroB
z85-<_BU?XGNPc=1U9N!9xfC5pwbRD0Zhu+jd{7d=ADrp2P&-D{Bm3xi9f9+_ZyIFM
zw0<!;0D<<=HH3!V5lzgQa8TjSbOGuBJj8jo3{%-Hv_~29MmPO^fk_m9W5FIH?@EDd
z8&aMO@2uFOwCPpT7{5zJ(!R(;IKRT#phdF{kGS`ZtFKINpCqH6I|oxt7OE8Djx1{s
zz+Gf+txOIanar^oQdR$+5EUh$8jdugogS(EgiFkws}`=~KUqfk+Gp@o6oYK}$J)#8
z*I^-8Tp~(*$sQr#P{AY8_HHJc-Mq&%?VLSXU4u{rC`_k)7m*$_&;lrPKcsv&cFFaf
z=|Inpl~&7Cu?0x2E(a|IT*5WGVizxo-c0JOoK?1q+fSs}NmzIDPe2&A&sa{r+v3wr
zw=)9Rr$1J`Oh6;qL)=#$Nd-=NoM@)JRsRFsPIXM9&g>$_aBx0z&|oj1i8Ro&Fw7K<
zsdDQvG0L&v3BI+Bbk0~q;b!&0799)Zlg^&)=ywzqq)?-M2Ulm$MN%uAHt*={j`_9?
zna$30!F@|-!kDL{UyljZrE+mFvkFhVGNq2|(S|}c&zX4z$}1J8?-WbB(-#sNdRMEZ
zA)akb0yAQJ(yzVl=7!K?+7p9FJ)Fc>O}}1$+5Gz$*zDHkJ7Jdf{dj`GuCq(3O_Ctz
zdF%fJIjaN<d4difrpm~Nc~>V{IB=4BPJLiYxFW&KLdDhr8G;tBj}8?528vnCUM6XE
z43jI`QE8R3b1nU%YnjGuhiCjrqWT&%k(%%E&6c;?+6d><QRZAf6+p&ZxS#=wkaqs3
z^rv$V1axbmacD35JP2-LV;RiLX7-v*lU+kp#B==RQ8|7F0;!?z4pKzxx&Ha*QCz@E
zy=UM+37rzZ%>j;ll*X1thB>*&Gx$ZP7nzoByYH!1O-k-71T3M^heK*A7$>Ip5dcZp
zjnQM6y~$x%uzb0RAnA`1F-&L3DtcMU70808xF2u!{9KQ&Kq;GZW&E5oA7I%GE4!AE
zrE`HE82~F4Et|Yk`RvglPc*$hNY^+nnGp;Mu6@ia>L*W1hW)Q?H8L<>!H4TUw}iRm
z5xI&8wO}<TXK;lX%@D&lJ`x)7@#Y3dHbr*J{J0L$8G2TRK+kd$k76sy&j+!t)Sfe!
zI`RF#V;D#3o0E?Ia$!6t1tzJTW;Y#pm^oUO!&nZ2xc2J3>v9JNPj#Pny>(8<Sij?J
zkBNZ6GqdDJ2GQ=F_o;>+yq)?0?co^Wy3Hjhu>>pui{2}Bd#|P@M;cpCWfVWSUZPW?
zo@*<0^Fz&yS>}rHoYSa`fPXz<+TaFIdghHSowPVq&bL!QJ8EY6tqB!(z5EW)C!CkC
zkG2Us$}Hja+9pr@r^E8IN<0M69A!f2)qQS%B@B$DnIq>U{NLRo8I{~*+zQ^RmzaQu
zTS4HR{7I)0v4Yv$*I;0tR()uTxfGBU$nnp@c`We5DawM&Eo17u70Z3+7^^aZ&(#U7
z;N}Vo3=Q}&XO4}-eK|%n5_tpp>$+mnLecsenmEL%NJ&`Qt2O3SOtgaC{zw{ZuYZI3
z6a)2i&vOq)LAn+*&YX~?|2IB`7r65bRBh97LQN)=7@y<HW$)qkC7N2PTIE|efJX4F
zaGc*V+(SGE=XZYnf9lV%e!3(=S9+JK#b``Qk6|eoYuj<(#p-|l)auG-NJxO?^L_xO
z`3$5w&So+3f7G(2us~h-hI)Gz59o)^*g=-H#tJ~AUVdrV=M_ma(oGEoyZT6OVL3Sy
z4}#P+glQ9{kewg02Z-VOnzJ4N)EZ%RYQZeMlY~j7b-y+6k)ifJ7uOAO$DR;>LZhAB
zD1rtLzo?qa4srQBWW;6%RwnXxx|Qh<W;i^`5pzM1unf8Af<%8Av{rnph`Eg^ma^Dn
z6>_KF4b-p9a3G@y+-D@|IPjUBd!+q2bwTM*7la;d2^xH$l0{|l5!)NSJeysjT07w8
zdJAnCJf%uN+H|JuNxTewEhOxh=wp!^VqdpZ<*Nhjn0Fy71N;m7%l4G6NXSC~3}b+{
zQ|s6zIaA<DB6WwQOrqTbR&!k;3ONbY(9^EG7wz5iEl45xK?$AH{-8)|tg$k+yUWTE
zrHRGVvjC?S=GeA-8)*s=Gmm*#x=<d<AXQ{%Bh!&QJ{;cGH=9<+BXr`PYrY3F7Jxr^
zBs=5K$H4Zqpx!_5xMLxFr+__{0u%FB@j-iZGG&eQR4gs_H+yqp*d`{hd<^ePF~ZZ5
z6hOI7ABMU4rUG0kD#oTAS<!72$#a{CWo1f?A|Q^1%ZyA{P)7%`NKn^_ng!OV$|^AO
z!)V|Ve0x5qntG2r*-uWl{vqG$9XC2P9lOHoYk!~~Z9lWK!$4rQ*jSKbWA0FsTx1Pm
z$9yBpfThvX*iR8t$FX7rEq();wTJE)jJ%FUnY~lRyTgdvk`X_ID2-1yf8XsvW*_~*
z?uF?10cxxRLa1F-Bg#C)+Rv8}(X;6w5MLb5wf~$A!poG(_=lo5gslSx{);FGxwa=#
zikM*qQc3eG2Xcxu(D#EFqotodLqg5h>Z_F=fwYV{vnsJU4F)3XeEb1j*dP15j{7f6
z(DJfV$C)STW*d`OQw^Bf-Fg_v!$?sLB;^tk88igocxULPs1{RSYd2gA;O@5X;F1bO
z&CMv)>O+la83;EnEFCIsprMN<f=(+rVxhp?Vcp3JmyRIbHY|gM3l&nIXw&s{XZ4`k
zPjaIsO^qY3wZ>qu6EgN8KDnE-A4y=HHyo7h6~{yGf5%4gxn-v&-;>PArDD-BunX%K
zO-;6$bpJ5XhHcj#EHJuo%0xFNduVnx1vwcow%%z(D^hj7OtF^B`Ax&s(=uc0zeZ;B
zxWqY^^%@B=G*at^4P${9M^Rz7Y7YvzOns%++~-M&YQ2J$Ov9A@6JsX2{{0~^i#Jf7
zmq>A1&N=Ps0b_LLSme_(<BO1GD*8X$LwxQ0R9hF?v#5qaqx#y08HRa}?+9${PhfU`
zAZP$(dr>HF(Xud=^zKQ&jFl;t(r>B2+X^=i;dS(~39Tle0f-r^Uw?i#D;{TLCXfEV
zM;#eZ3)Yo1Lr$+1*sKTD2bKA{Qr#4um${TG_%erX>U@$VDiN6CBe>pdTdSbJt}hVt
zeW~k|5qRzve|It=j6VJ%lqkTl(=rvQ#?vlwPt`2X7X0EDy&Lm`=is%KET_7yi$k!`
z-wxk?5_T^b*w>E#CSl(Q1yCj%if#6;;hj;F@ks`KXb#`^$h7NhHLapu<bxd)wTjDA
z=&Fq}qOtSwIo~!@P7Iv$e?tnoHsLwsR}VzVmtUVz<?dx7m@&?SQ34Ky1H4{>I~+dm
zRWs}u3587-b?k+VfnR`)ZGcdhOofaL5hgFlV@rsu<8$_tPCWdD|Dhro|1a~N`H&)2
z?noxcHGc!dx?3Mz*p(+JPCvG<jd~cv4YtU|wN*lPK|t<Y$%HQgi9P9=W_*_MNH}l2
z!`YFn!;RJfn1k`dA>XO6TQF(Rt-P^%`<6IJ6^Zcjz1oS>GqBQcn64RK7cUT?vy*~q
zIXaBcpG-gd{ohq}iifgxdBKvm$(8Ac#flhFA~Gj4%a)xTZTxLEYeo=H+EIjb>=?-1
ztTg`_uO#{`V-MxKH)@YZeIxS`KTrs^n32tZ+2l7^eh^KU&##k0Hwa=)|2DRHV{;7+
zW6jHPh4!~XVisSBQIUm$?P{3a1`j32fWKDDUT>X%)1BBn9}-iHKQ?f9zoz#VJJr&0
zJHusCYn<P%7EYp&-hVeh8lf!~FDd70W8H=r$yv#!yBM*QRyFRhEztjk<aH=iNCiHI
zb%rbL!-&V<DH!o866zRK*S$?=Pz9*DQJ}r%Zg9@}ZtLHA4|CK=A7<&l9@bZzNKg2p
zw*DKbGbkD$iJ;*&-VT<zO9rknv^q2^-Q9jYqrpK_cr(Y#xF$&}H9t$fYwtXurA<_;
z9EYe|SiCgna2Cto54Y|nH)V?FNKKAYKDm}x(n4D8UbW+*7`D6C==C{KP%A2<oBx?1
z&4U?l*vPMpl>mYv&b?$#P324*Oo+*WOKV!`eBsHQe3PpS6bL=Jh@`nt8&O%Va+|Tz
zM;9QAQhZj=a>;|{_YA{&yMARpl`zL4$%#qD{%;HHBeZcf(pS`@ugFuo9!Xm%rb*Eu
zH78Q+Y-VU~3Udz;0qX8GkDj~6qg*sHV91O5M<4;JaZDJ?kT_&)w6WoY+vVGR3-j)p
z%d`m#Sh+HKg_v<Js+(b1QQfXUFTb#qqel!1l`8{GkL?=1*snky<M$?-pxq*0w>Acw
z1z4@q%lvZ^C>><maMWnfSKDD6^&LNQ>Dqu{3H@u%u725)&(R7dZ16LBH95FxqLg3!
zWa?M@SR2Z)gFl48Wy0y)uLD#(nb92`=v*@fiw&UF>WT$vQyen$TS21LuLw3wIdI$2
zJVn7ZG+u4hnQv(SjG*?7>7ONjy>65*99(^&odgzlKzAwb!J(fd_{{hxSjWglz+HJ1
z2(8gaej6(@r9d{vcDa0g@Gm<VnH^F(XuztPJZWJN<~gDYSwr;Hn^L;#Kk8QxaH$xP
zPx1BVhHdScE9?kv@~u*o+>-3BI(G%>sp{V}aU4)^Bg%kTPd9lM{AJpUsdit5^3R9S
z&B|mT9fLJ;6j@lGm}XO*aO|-=%tn`Vyf5}r%hudRE>y6p_|y9&F~ci?WjVCC%q;za
z&CAvVZ6Z77<G|~b0C+nP1;W0eFj#gUPlg!_&RKjJ(gX*(IVLY1qzQF$bg851cA!Ld
zVX9q;?GZYl$LJNL2PAVqPzN!i;>?T+>5zU7+2!D`vOk6SnHXQk|GuI#{Y3c1*zq8b
z^(<>ZfI3qAeYKuXYIt|Y5Np~S#=Wlgsgwz6l*awA(<Y=XkDdY{4G)OMpVgJ@#J4AI
z;|XDm%MC1`V!&fS_|~;YfoWX=>sCm&d^QZXRA)^bHXCC@>ofe9A%f{<7Op{HVm81P
zeMw#mUeNaO2Ob}F@<yo$RU;+rKC?RlDsn6%xy9EipO@>3wlLXwDvkpLNP`%AI4Ppp
zmGJI-0l$;zK9&gHY4nOX`hgNDKG>;H`r~H$gw1VXdE)EU>Rln;|5rE9(*;WA=J{JD
zAWdbde$ex=Z#vz<z!7)(2RyT}75&5<OTCd~pCRTs{KDeJFFo3d>ZxLiw2WK1)jrN|
z>B*LeX6n<9{a&B~d8e1UvQ->|m4Uyp1ASP@+6Fh?WS(}IKb<DT;nL4MtK2mGIQB@3
z#pW2PSwjuY3MnyBrJ**4Z(w(;+M9bly_kY!+^QG}qi>H0L7Oqo0bEGLUVm_vY>S>b
z)B{Z~j4h>N6No(az?kCT1K(Y~^8YTwR=bspm#`#iWnMB>Uu_>SC=u~vbu?z*HvT7f
z#;*LhX(3*AN}AbT>{zr}_|-_lw+NQPE55@vCZBm#Zz$3fNt(So5lEFe{oo0$Q+JEu
z0d}EzPRbus_aHo_!A6&<V2W^8xdbG9vQEKP9j_0P>d;B^JF%IE2(uz)ibsh$aYq2b
zYM){3tz##|yqMm7NOS(qQEaWVKSeH|WLAZWlIz(-WQw<^Nxh$cTP<*hwPUt~=7Qgy
z#;y;)^K1EIl^rJ#v@l~dr8RXvz7%((AEiXfsI3#=YSl4xE2QUXOcr)iZ}n}apkz`s
zClS5ZB4<m}QrhxJlz4x50xsp0kK`+fK?kraym(fLS>qRgmb~JOoU8rYg(+CnDk6R0
zK{>D_57ufrl9W7raG~`T)ie7GJbu5h;5hlwN>n;*vY8+|zG$P{f=>3e<Q2P8<j~<e
z5~5#3;V21)b*0~Ju=i$cQ_yXzq+vtSr29`5$AO{YDVkiC1-q)Lu0_Y?Nrz*=*j1~k
zha3CG*L47LpNx-?f+LI$jQm8vax#YqiuZkP#*e`q4;o1bG-}dSkJQ!SU>8X<zwlI#
zaOZ9**tXmXu`zlZ@eqH+y}xal*_YPJflXKocZQWP9A?<RR><Lsg>)Kv#fzDi8v6+E
z_@^@QNJE~VHiF2ozG*nwp54<X`-zZ`OA|JV9IN^^nUGvp)8atS8F2|>Q0!3Bh}lJ|
z9YxG(A#a=IUrj>9t&>@Jy6FB+3t5@U1=>U4EM?=rN}{Lo^EuZMpZtv%=89-xn@^u)
zJ??@IBzTArFW+kCfqemW%0cgX-<)Tu+_5%<y&@D+hLIAdZTlF;s`AEyZ|{p{A5PjD
z&-?%_A|4P4T}Lnu+WlNbHDKl!8Fu8<vw_QK3?)bFJ|$D}DsP|8C?PEGV}!Z$4|+14
zPHktmWKFhhP?jx#!)xs>k)h^w*xzy2$yD~D=wBk@7<<(^u`_u|!dv8DF`T&Y0I{6O
za54}jVzBN*HPflfC6^kyUgKNsr)k<*V>J@tp?ife@F}tRVU{x$zN9c0!BYhx=k8kr
zXh;Xf6=g{RFQV2}uDpvpEi=4BTh5xlJb0hscyP^`FRtw81D6Ue*079-B8D>eXhT!<
z_(hUI4X>HsiPok<snsfozw}amN$t@0M{^hr2e6lF%(~aI=J6QV<A5DL242^IgWg&E
zc@8401I=4X4Xc-M<{y2%?pisXEGHu{_2Nfja*6cSVj85nLqFPnj}Y2G1-V-fvC%kr
z6=Ox?+QNz*ezDy?aN8<nW#iL)j=4~<?QySD#qMaRUeV0(q@Dm8X9LXkdT52%ua6}u
z7Hz{#Ss+j*@@pMxm@uw!e$b`J;RDB^Y&wg=q4r+x9mVWpE>lT27D4|t07&6Bm9xO{
zKRTW**JY9-ExF?QW9{2-MDnCZc{13L381DBnUh&{@U^8K{5Zs*pnk9Hab&+Pqs^Un
zv!Sk^>>r$r1ux43nY|mTp4V<9+uG`0$qq>{fXQ(|CdP@Gh2Ev0S)%sCnQxwZh(s|>
z_i{LEff=LAxou1Qw2azdn=zmPeuQJ@ptuj&`K^)7ODpeBg{JHZJS@HJv-unARMR(n
zRjoiekAo}HmiIHVY$a4&>SiH*?3ybY0$-D*Z0p1BpApo4XU$j>+r+OgiIKnqK|&3}
z*-S9bzOOwPBm1xJS_r=gd6flhebH+s^7-fiCabonTE(53XF~-2+V6J4SMYhlvx&Re
z1e;yvDGJu~z?+OZ5p>2f1D5_irFq?XyGJOys-T-wZji@}mJi<oQYMQUrCB79#_?MZ
zT&J4A-gkS<ioRy4$srK-$Ea&o3KGy+vwFMkp{~xGCo+|7w%^;9ux#=Uvn*ifmtI6b
z20|DZs}PW&>E`u9lju{$dFgv$hTou)MA&IRAKH|ch6pMe%Eu#_5YBwT33;DaJf;P|
zsg?7;lpqE)_b5Sy-0q(ZF}8;&xQ<TDH4CrdA3)(1G@|A($gM|8z4T%O%zfTHxOd;*
z+?Q31@?R=#mZfx^;<I^@jFew5ugyR<JwcW9ZAzfUror|~ymh|fC>!Z#*6WDq={9o6
z;H2i2FVImkpBVrSxK*#L@Z-PKQuXLO!gdsR$tLlu6CQvF<h^!AwJ#~hT+uA7Y};u%
zq@2|mo9XW?XHP@nv;)OBwvmAt7zDIBIN~tZ*b)Q}D+R2`%>@}cu|{>h8|rkn$Aq2f
zV)oP8jaNFE)&ZXBnF(s3nqj$heUPC2b|>G#T%G(*0@4|r3DCaG&t%Dh>1rjijf1)I
z;KY<T30`5>SOLD?NhEO3*w&E;4?)Y7l<+d%=SdPy*BD4Qhh_6CRd;in0aCs`k1d`|
zb6$DV_Gge`!l#8iWkzxRFPWOEXbO+RR@Dji!#Sr+(R0#yj~BQM_;Q_zDN#nBjG1mW
zVwFsu#O@C&AKJg3JqwJE^^%%aos4szzm43>#gl;v3Ghd8)?NLoE)VCsndr=ofh*IX
zMm54`WD*U$P4frsC@*79P42nBt>#}}2_jII9<7)`78Y-39Ss`wa3dXd45lc(P<&~*
zDhSMOoxJV{3ilq-v)JzH)<yaAeZaU{h27m97_5*W3$y7yscEb=(Bm_S$ATm0-KmUq
zy49zgX|JVdL#C0dY3Fg$@Qc@Pwp5r|;WI1EMQRk?8i!VLMuvEi%Gq3--d6$uGG_iV
zIbGegI4KL8_Vw5!4nuKFx{p2Qb>V{NIkpUwcr+$Nn-9$B<fx$RAieMr80)Z~3FhtR
zy#R68(DEoX!IVBpmrSEluze()1Wk>M(idJ5-GdVK6H|6WKk<|+WpB+|0<Z)08c~JT
zG&1v8SU&S=G-SSoTr(HoxMx$r0AYBgR1z5^^(CMi&>hsi8!<&%GX9Ze-J0p<>ervI
zrKAIJno)JG<O;!hLEB`aQDs&Lm*qH4P#3K}<3x?%<NM)*6#;`4#4zQUUMnkxppTW-
zlLGzS-+pLwIv0|iMleq_^KcAC&B3PJ18KwSLvf{w3;g8TITRqpsQCFJx{`mDUWcp}
zV~5;+`^Q!R5z1w&rWI_Aw#aN}-Gy8#IIju=yH$h~nzgc4{}a2?K6+CCM$((aTo2if
z^^1;|=iJyPqJA*uCo<{^qQ;nvE^2T%!W_T(9{#HkSeh4RK>kpKdX^DEo%e*lCYrXM
zr0^za5(=Io&NuhwXS<^&pE=H|Ost`~Tt%+^)5PFXQ~=ireW^v>^-OP%34hyJv)R7g
z()OBXs&M$I0Hcg%SbFcx^$0N=+T#f&3K1TDhb_9^`GNp=Izz0G?INF6E2nDbH#s23
z#%G50<08I)Pxue;x(U!U6?LX0-U%r`kNYsS%#4SjX8>K?rDO{hlpHScuFx$?SBN#e
zs9&ZMn1l53pY|SotAz`UO$RFv8D{|dIoZwb4K%L@ieFzzu}a7@gs*`?8X5HRB)j-k
z3aiYs(!?mHtX$N@06^-be97%AJ>I$#fXp2L8BOVDqcuSUk908%H4=e|)KKx-HJ6=y
z$03e-l_oRJZj=>Q2!%@y`rP+swiO}f6I0LS=hcW>nmVUI^>!V&W-_nrWM6F^q-P}u
zi0gY-@5*BI^$ns(&x*ZP>a|g^2yy?sOoVoSXi4bdv-ixBi33A7`qq!XCjkFEktn-@
z;{RLK*?x}<Aqb(sWT1jjiP3Mrx7mcB8qwnCcrTcJ`%FZj<h*_gIEy?tn<uYGvqP<Y
zY?9{n2YXxBQe>gAC*WM#z0xaU@t2of9!)P8c9q{TNUE%^6dSf7Kh#EFevf*x*y+xu
zR3*d^6JO-Qo?bZ!P~4srsO*@x(t<kgRf){958Fl-*LOrVMD`nTp*qHVF-Cbla}rB^
z!k8x<4NS3~l^$dFB!i#6M;PNs__1^k1rE)q05%swwZe|VP<AjGDCTi$c+vcIyw}0#
zsAXwNiz*Su!lG+0F`kYveWeL4mW8=`-@~aeFV=RiCiW<#nn7y&2w${LnJM&_VjfvQ
zJxj7=M*Gha_fa@=7BIIX!X2})l0vB@CH=FOrYGwzVXF+~*kJf|i#Du8WFrM0#b8ga
z&LZsA9G-;<DPHoh<j;t`dtMA$ws$S7e|=fGG`nB?hM!@!XzeN|`3Uonn;sS!v29A(
zBdAF6zGAKGj{&$56=lw_ol=2*C;*!KA-KNLC!2c?ojIh>a><f#PfC^HIa!2b1a<-)
zPIZRYpy*%xVg#GI57wN);w5B%>)J3Ziyo&8Lv3afuQNb^j*IaCI5=$3<DzvSeF-@)
zX`03<iMdX4IjSC#WZ-z>^+3q#fTZTI8#i`Die}^aN|rCqu$36I$3=5=v%fG}APwmH
zqtt<$UP#nc+z}`*(53(i4h;C~J>N<b3H;JkxkR*7G&t{*(5+nqaVZk>#OzeaI?1K+
zpGRv7!!z;UKn-51$w!sh+0)c`t<7~AnCh==EZQqhyDM%JCYrO7|EO30NmfSCZ({#B
zu+xx<{24n)7*jY`!?nLTA6z9&iX}Hugdyj{TRNu^nUmN@_xSHAX12SM{q{LsEO2eK
zf~c9Eq<})css58Gq~ONzuHdl_Q8(sw=2B@}IpXuG@Dcmcp01zN`tUilY%muC%Zlll
z9eAWAz8NrL-<7_&E4sv=VeRA?<dnCVH)dgzA?ORqjL*!f=H@aTfgP2Vl>0s$&xV$H
zx1hLNro1A_{#rR%3>$7_EaGFF#qao}&!&f>{I2medQ%AE;YA5l85vr^-%Wp918$SJ
z_iHZwqU=y`_LY0a%BjiC8LBlILhe&ZzA*!SV^}+!2}(Go;y{hT1|aZ#M*2Y;xjJ1a
z5uei&kTf@d|N0}1P}NoIoA}z!(!S(h{5K3GhNfs$N0!8Odt)Crf{O7<iOAa%+D-+y
zr*b>VJBysxG}W8Ai^o$BUjJ~sOC}k`O4$NJUUJjp32GOf9M^c%y^oAFp*{lM1n#7!
z7EEz;t;2<UXG}bMp14k)U9Bki^gLHv5{cYk87r_yuI322d}v=rQVJ>-Wi|Z0&>i@H
zI%+dDno)^6A8=;uUep(EEsA?5bx!i@b)M;RS{F}b53mjK%Z{NqlGq5^s0lt;#|9@&
zUmd2Pcad%9TsDIH+E3@C+9inn?@gnEI%W9R|E$KSz?O`)7N6$pM_1{;|M%)1<g*~y
zBq)boSIh$nuAmI`XsiBWP}&E-O@F1KU>RSWB3<RUq(G;w?Y`j+@<coua*^~5j)XPN
z8RFN6RYvpS*MYmQy;gnNa7D#ji7spDnWd^A=nrNaW?0g?86b7DVq!>5Zn$r10WKOb
z=^)@PR+<UG+=tLStV5G`kQz7KXky})2KHh%$eMS$*nk$3hd9h^SHU#n5t{0a*Su0V
zgdyDmy#z`?GBzFtq$>mqGNC75Fn<-L3W%2)Fx&2-(yxKoafA36{{|wzMBl1>8j<>r
zIkvvX;WBmi8Gs>=MmPlhYH&mr0*~{2-V(F`lPiAp_|pG|!*58#<nJAY(D=Y(d6}<E
zV8nWy?@v9Sj5xi~uR;uuMv(wWsCqNq1qY+-1eLd=cIXj9PiK#N{+2q|r##hOHt-!d
zZ}8u*1|OSzm3lNoIuaaBgnp0F(e0W@|MI*5ZFKYE;Yrb++siX%All9I(AgN&3xpn<
uKUwwJOUoeCw3}YSQh$#8@>fy8zP|C~GbkD-MqjYI=P>3;e+2!-HIo(PD$7;?

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v
new file mode 100644
index 0000000000000000000000000000000000000000..58f631881707b122f4798a20f18faaf4a31d2265
GIT binary patch
literal 16680
zcmV(tK<vMZ6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWEUk8-L|ap<y5s%z#(
zzOESivm`cY`FjR%cM~Z1Y|@c+*-KtZcQ28ttwQg(J<|}bX3amD!wKU(H*~oB8eh9*
z4$MG7K^cFrz)+&gDi>U$gl6f;BdBLf5Rv@uZ<r5UehiiF())I7wsV))iz84aN7N4k
zF;O11R#VRdRX1-k%9tE=t)KSO+9-9AP2A^?pn=i+&^RbmyI|5IO9KoSDJ9v)Bu;iR
zav6#B#;yAHr<`=?NkM3<e_qrlLcNKxIKkS9eoa@dqJddZV_yMM0||B}#lUi5zmZ)O
zMw%js)b3iK6Iy#Z1Mv&x8V#o^@jSzFe;4}#5Dk2lf9oI2hp32P+I^eWHl4h=!!|nS
zJqXc}ubfxngU$@Z*%WvrG1<1Cq%U3=FY4DVUi1AQ?C$#p(HXu%Z_XTELb7_zOy~c>
z*adfSnhIRZy5#G|I1~f_qXJ)~x$!0eFCg2B&fyF-RoT?Ck&QdGANJPL0T!-9+o<wh
zkwIszXoSp8RzZ=XFz7RrE#w6^LW$zJCi&U{!ZDRB6F3Tid*bj#SvI$aNK4buC{Q$v
z7k;pn^z11lj1b!PD*dEwHJSBgN>Jj(zM__;vC>Cbj~Lxc-QssQ@kkS9%$4e3mLC;H
zO)H?_k6r|X+$%Ep(-TAXlftXz7?)zT_Qqb@viR>6aq8a*ZCDBR{d-Xs8uBOoF}9;;
zGd=5hy(jB0vD4_}KWBSMiJj_QJjJ|>w~(2u+=+`}O+2?GaA=xqC|RD&#--+|8Y-7?
zj$*u2L=8_wEmcLXeXHf_8OsK!Q2O8d^dMW9+^74>(?{J0PTL6o=aKmbG8bO%-h#iU
zmX=Rrww}CIG@C^_3l|3fGdkY?G@qpo9tDp`6o=#rn5fh^2EMN)#d>LPw~ukQ*amtz
z+kMzRoDg5Feb;9VycQH8j|>+|gB2-WQ}~w*O4pMXvkdglZBsRX?A;%Kv;6}OK?T&Q
z-8ioV2dCJvh%vVEEhrwx?;F>tH?VPp+jn3-)bc6@{*j|_EUhL1>3P(%*QKgT(H-|g
z6jl&v>$hwJ(VT$xcI6;iQ%o09$68IfnONo3is1RjUG6_-1#YXTl(WWM+FwW1lug`)
zO-uZvhthb_;Wa{nYYR3GTs(d#$!(JyRsWZqmwWuLHd;HhgU26a4HT;%y~&6}=3cu%
zR+BYIQVB`<<hGT*^pb;X7MHcQ`mxQKMIPVBw(o1RwJ7d;7){P0@cIymrm)PAmi7d+
z3jB1C{L{{%;7~IB8%S`+OX$1xA0EKOzi*n?wIEFXpFUr%+wA)$QrQ@Io7ay&1@v9m
zC>g%Fp97w~*Dl*-oBWx_*!E8T0N^Dtu+}O%m_mRKX(bGguy@}8|Ayp5-_hMcRtR)I
zBmx2ag}7Y>TGXgFy?6X|XvPyWGzpZBJI+!JmJ|lM`0`O;3k<q&BCYgZTzBQE51w>F
z*p^#1G(*ohTSO=MK!~g|(zLIFw$3!wmmXE!e$>`RENDC4K`R0D9AqLeQ+X_B@nRK!
ziRN|G85#Sp#Gw|0Za^xcXksVf7Lk`lJ-=}H{X_UetNHD>Ez`&SDn+N1O4_LJYbLQG
z1FQw=nDVdW&p1r4Ix4r)cY1GI_HxWO$seqzK5?~FZ=t2mPxwk(<0I@KHGsz}N_%$d
zl;=L}sDh<6^W(}DQIj#WPBC}*HVB{f2jQBveDuKC{FR)#AoU}m@7x!}7g_9wBiOj>
zirV%GvKzG|+#5fl3zhk2qLlj#PaFSc*^<gYRFCC84$mF)(<CMHCp1qnr78;Ty1n0T
zIz(}KLx96XfwzSTVX9?^$_{ZtK1d3M%oLe<C9Y@l07GtTRjf#==V+6kHXFVw`huSa
zJi#Oi*gExcGc&oD#;?<<*(sf*!IF}Bj>rcfFz|f9^2qraD`roo4y4B|JbHH0=49u)
z6m#E$0#TqeRwu-1e`tGKO{3y;Yzi?_yJD54n^(Or!^y+lFl2J?eplCl2xOdh-l=Av
zvvk18Sw8iMWCn_7LPqZ*i;|vAc;Niz=6~dI={?Zx1r2_5<?vdOMy$wbW+?M>Nd^ZA
zRhb=z(Mo&bkN-vX#TItt7<va|l!;xg_01J`-0#Xh1u*M-Q=_aJ{XWbxV-%4KK=fHw
zoM#{!Mw*lDQx=Sdd17+u^%=@O^NL)+<4B0-=l%qzq~<ID#p1HbQXE=ovSfPB(RF!5
zUyMuMWNJ?E{vuJo?=UAqzG>(yUkii_wFMOE%-w}Y$k;b4E(*f0cxyaNr?9ahZuyj}
z{Kehe#|@F7%0&tJX;t>amMk_6orzap;`~<_jbEu5hZ{tQ-pvfw0PMY5re=Z4L@g}f
zwlOo2ar=JT3L;<}T58D(krZbLgIC-*)WJsMYN9&FFB`A34e-{Ew-nK@4*}Q?SV(Sc
zYy0IGrxu5cwu>$^ovYwn&>A4${e*rJKLAsWEmtCt$;|odF51+m;XpIaK@Q^*%!PZ#
zLrAMHzg&;KI>R}>3Ss!bT9wtQ#-=yTX!!$IbY3-9j5YDhErqWM@MSBZbtKd~vbv&W
z(HFf+AduNcIPY~AaGXpG2LY?v%z)+9O0T9gC@gr-19!e+E=}l}6|7Kzr{`Zosnmg^
zU|XDyKgbimU`3`1rZ#Yd>>t+h8h=hOfIgzyS&6DHZ8yQ7t@n_Ew~zv?COb3QvLapf
zg|&A^9~h$pCwO~HWYDL)HrkRl`Bo+Fa#Nfhc>aR)ZrC4dZ7{e>?#wPW#_J1ZMI&2k
zAb36uOXuPE9c6A>FtwomSiJnJ0kcSPF<}q4bbYIv6wJ}^=7RuEn+qRcPNs``AW~Nv
zaYC5_2(}>Z9@dXP_R9n>jQwcge~C>uJob%)SdiX-@I-)NO?{<X1N<7DpHX3M!g0eY
zuS#sJ-cv?kZj_*YlEcuS$jFyC(^z8qjqS<}8tl}@huNEZ<&2aI|FgDuv$C34(FxFp
z<YD}*$^E0WU7}_U#g-l1V%?lPpla8$(ldI85?%W_TFWsL1jBWU?@S?b+~GzjqFOA3
zB{2~|n(xolS$~aY`2Q`xKFK2ao>*%dX<D;d6fs)>*pm0na|{Zh>lPOEgDA5C(5;;p
z5@J_1;~<`fD+&Lf0qtm{?<b^l)cGToiOKOl<~^9#gjBDlYe{#fg$Z($T~YaO1khZG
z&iRx7$jK`Q@6BU4jWxV>gi}={*ky!m=VPOATS!kDFRAu9#~R!it!kIgd8kjCp9eLB
z7ds?xWC8G4#Sl;y`d)&>u^$7~)TfS55i4o#Ne-A)19LDF<rYL-%zzw6QY7K|$s0Hv
z?t5GWA5!(JC1B;HnQeo5@d<5cLDMvjl-kHgkj&v=R-FrceYApJqc(&EUE<SSZ0=uB
zOzMXDGTOEnsB2h@Gl{qR8N^Pg$G=!ds-ox1RN>$BkcaAOJ~L=suB4DKvu9b=KD9@q
zF-Aij{OYLQDye^yioSl>^Pw8~B>#fsLq4DJBeO6<Wl>{}1w83Nd{B8N0L>n1_(3GF
zc{4hdY&1fDceIO0DKX!!ds=fOwR_Y5xZ@_866kU=1{=87JSOaaCB~})2!DA-9Ef0B
z458!k5U%s137yu)VsEDIU3jvX!a|QQsS`Ygz>9>OzP%!Q$YT?ewq(IQ$}OPcbw0?8
zF-6*-+<UesXk{5J+l;BbhLc#>-wj%D@9Xq8g-c!xus}=nwEz-N35d0Z4M@gbN)QDF
zwL2C%`9V<7w-C4dnOb4|BQMZ#zJ&zG*6gC#LIbuZi)z01kCW!JT}~%K6eu3G6T#&i
zL~n~hvpOydt<5sV#2ru>|9@Y49Gq@F69;v66du9d4nHeh1V0#-CdC`Ngjw{rzk2oS
zJ|N`2IdFx!v6(f_t6>SYru@0@3N6(uA*AroLccF=*!s!itl>e00XK^622rY?Unml_
zt7Y~ZfDJ*@e`K(1ID7s!CM|Wu{L2?Mb|ld^<D~o*7~6rQ5BlhcXXw~xTPQ7P;_2JY
zoGz1$)+<(gDZ0L^g(8YH0SbB$+KxzR<2(!U<IP;?y-RZ&OY<-WJjGy4yd0j;O#oh)
zS1ljp8OOnw*0`kO`=mXB=X$pxZ(WDqq^;OA9T|TQcQ@8?X$VaG?I%WxY9}BF-dphb
z+$UJBSftQ2O@@SPYkpcy)mU?Hm%Kg;Rcp@WT{hQN$nDKEK+*WX0voGn&d6};;=nYk
z|2$V)-L&N6PNjt#%SLy2iVF_&q<!!g3Q!m3jpBd5b*MpriMK7v7ST<^A38XbvI<t!
zVT(318PDV(TC`4Jw^2Hu7f{o%6YYCrRG}PVcov^RV`z!ei?$`FEvC|3U0+NFBBe+k
zlqM}R`qf$%(}dz{LIHMajjXUe0{pLW7El5313|01RV$_Av%!2=7Ed`EdUZrTqvPEs
zdoyYmb{FHVr-32IALZ1FgSBO&U|9>g2-YsO^r&sV?S^!V$m&C(5M{(_;&FdV!*{Ga
zmQ6^BACAt+gwnnFS^kb@1%mZqWEq*<YB;wuO2uAPJ!yj4M@KVTAbFqTYg_15_~${>
z`hUQRm@QvNkOOwm+|}(J_DD8S4=6~)_nKmBJSN;8d?c)VZtjC1fhCIIMVlc**Tq>n
z2<gCs4#kt%l9=#(W>Ezgqvv)y-St2{Y93src@Cz-DBRTj>7nLKnjeop%_x|$l4N;(
zT`Jlhp$4bNZNEb|Skd+KySl76{9xJxMd)1Jvz5!J^p>k+7UntWpYp{3D4O|n223Sy
z4Yv$miE(uUmG`b#2u)&;)!nkt=2{~%Z1)m&Paz9uq2ev>L&dsSqXlk<tPCO*hBmDY
z-i}FII%J@kF3WL*_q%$88wN53`KZlvg5WySeTZ8jE%h#QEsY1OtV&t_pb#=cwdxJ}
z*bKr(7M1ryi}tJ>NyL@Tc}s44Lq#U*gVpBk&q>kO*^_88U6L$9A>l^J+~j=|LPLIR
z!DAoAl%0_=gewCdL%2B>ZS!a|-S<sMKyo?13*Fhr<m^RM8Ob{9$3~2e2Y${!9lW?E
z17TAsrFu5R3SKdt;v$sTk-f79R6CJ=1ezZ`Ck#sMJGS+&(KA7C_%DF{vlQK#^ARZG
z%Q<BnEV?HSSOBHi?wedr|GxDW<*W1+#$X>RzaOZf5DLvh@xYo>v$h17&MwKiSN6?G
z%O&jjH*a@Ek|p@l*AZGNNfc@qX8b{GPVc|p?Y^$^u-4|js84Mx5;2sjb`nA>2Si;{
zf&+l-4XFzvIi5+r;}FSto&nvxz&pNK2J#Z9i%H_X#zy)qLsFQRD$qT@JC78V`$`*b
z(YJIa`>=aZ!g(9QtM{&i;;A}BKeh$S9<4@**GqiMM+2YqZ=RrVmQe7Kj~iDrq<gi*
zQ+-aXgg(`1YtLk@Zufuq6}p{r=eLh~M)h^v6Y`&mwIwr_)lhRIao^y!#egTzXN@P?
zfN@2-&Lvj9-yPr(5Zs8vwVlai-aW0aPr(w8arA3}V5ms=;zAXnYBdIMtKGN}+NE*(
zT^1cnkXr{DMOL?nZ8`Ul9FYXV(1c-2OBdy)@eFNz{qD7!3EZsyepaDf7g{zdULZK#
zCx<t&h<=M<3GjS9g5<=znLHphjz}3z^}U7ru%>`a_Ck@)S~rp{?lo^7_57I+I%nLO
zp(goXE)NxHrT_tt8uD*O;vDLcT~VMa(==BsoA{U$a(y@%WN`Z@m#?@Rzhi^(^QUaM
z5IgQKn;VoM4{^$(vpGh>)5B$RQzXyK^aZ>U-8_g4TeX!EtBS?1u@B9oK1p7?%0H{Y
z5Nn$Bgl?RfmsMtZjcj)WlR4Q$3HgFxQbZ5T(CDqT|JFfTR5DQaFm6|vt5~!WgI%)_
zs879QJ)`33E<eowh+mS{OEYEbzjj9D$rpBI85|plI5AhuWg8Hg^s0@CBE@(gBn#Hy
z*90^lLZ+mAyaH=)g_i0kx}i=OMu=@OLLlZG2bW}KR_wyjF$#FpdsEd=$4D85?D}b?
zup07g;Fw`>G?8XhC60FY3G@J;pKuydy>}qtu)?=ub82cWY=gGEwWUqER2vI0;PR|M
z)G$^9m(fz@8WW?nBFV^D&zL@lJr_;~(0f#~1lO!o#f!{^Egf>3Hf{fqR!NuFQBpqX
zZlvPan4aNt2Y~5^us_{iNp3xh#s$)<a`>mI>#rQ1t~r98RVRz+Bf*??<pit1{*$HE
zwg7*=;ytW{t$GPOrMT#ZUV^}cPs@G=<?Z<wLjc&?oCZ=vy+vE9SsE(OA2XqIQY}EB
z8mo(kUkh~r|MXz;&*hq(`4<o?^@=*Lc>nD(M#4DvlE+SII;bc@guWM$6(+0sKqP4u
z_rf&Jt_**d#IOzHcH&3;lkm?-eBFVqKs1ITx0jDUZC;3Lm@<xQ)a~LmkP8`LL)$H^
z!4GD|Ai^=<^{(c&c>JlZ?9&=P`>o1SH$XlX@6Leo#@Z!ui#%&rMqfZNEz@R-C$|f*
zLDo1JPMsS7tT42)XoqQ=)<^-*h4Q<MHC8Z@jU6Z}?jO;Mg_N|4%mINioFKp9xug~p
zE>KHKK!>-k%v)Ko+xbvS$mZqfjQnb2Ri?YLtUKseCCnfn2H#35#eC=Mx1uA&Q}kRx
zT2x6>!rErg>@tHQ@6?m<P0aD<tL~Nj=S87Kl2iaE!Zl6?pT<VIXVyH^qwESQxUL61
z7nc&?Y0PYA`g`n^YyXuHSoGD6tEIj|l*A)<he5B29Fm>?F5`=84F7<5O&JIS9Thx6
zpGx;e?Y>MFB<0f&z)k+bI<u>qOTgoFJpSJ8U2;(r0nL<81Hy`_p8&{s`ZU9qh19p2
ztlWZ!3Z4Pogw;`}yqb({<Lca{qyG<pl<*sFuOO?7QBMAObev-YBy~tpK_5qpJV<CS
z?Ak}1KZVDz?DVK)g9%B=<Td{91rsF9%%j3qHN2)vcX4Xt62#h1Lm0akHu#MTI7Tbx
ze5`Tx20?m*<Y3%_Exo=|5!fM5hXf`Uy<6U@Bw`YRiAZ1nQ%E!ik#J=N_!*{Mxv<YL
z^KW=|aV9|FxyFb%mr(fb1DN`wDg?f&J{zL{kVacUW}|k6I!=2klN;He`eNLM$`^M-
zdj1+`$f#vcIh!k#gRJgRqd(G${!q_2?^pgYiF9ae8JG*%NwWEvF&hxQLQGrSnuzVC
z{faO31wdP2XmpIK1L{ywc7LCwe@@b|VexOb_7-qfXO~t`Yc~%O)S`rX+IVYbll>Z8
zIeEpyfmwsg^aG8R=^d6%!%CW*+^(G)=)rgLb#5$nBkbFwCr+anlwi>tz2mnNlsFb!
zu4*HCnaO`z2X*tJr2wh6OK(@ge=l#ZR=<-mfI_Z<t`r5YEwAIop&%p{RfaF^){C1!
zqJCJ|Q6~$u@l>D#+3Jmgeh8paiT_mIVxy3gWXm*xCDCX@73MCE*Tl)+x0EHLON0n_
zLpGVxm}va?YEq}yIn5w**Shw%`UCoB+VK{{+bJ+G9+5d=vzPo+CVhu9x5?{K?@cIw
z$Q&)*#0FYLHml?YG96DFc~4_iw}_5Bl{~sC9;r~^d@S$)al1fMyC^7q_L8pzkiNl>
zhY>aN&DD)hp45b7wStXs+QOV2YkCW&9Z=+c9-)`m%`2r#JeVARS#)_=d1(=dVp_;l
zYl>+qU7`o7={-e|DUkB2QYMr=9_N}UII<<Fxq;PmBK9}yCpYA3l_cxQ&Ud=8Y&wG#
zhn;VHS8S{R2hZ~e^wRrADzPmVbQXr`|JQ$slCWx!{K*<h<04tKWJ{r=f(zL;rlSm{
z30Y|MYK}$}nc;3eLlrSj_<5VxELM7pMHDl<o&$AS6neG%^kfGWV#7Ovg0|<iv>cdN
zH!`TmP|tTEPUp&gzNguUdO_^9puU+#hC@1>@>{+%u*^DwI5hk02nzfOzprupLuP~Z
zoMZ{g$IR3{O#^Z`N2tX`r5DtLYw)cW#P(_@>uklo>EzrnB>-bv-ZJJjZuR&>IrPp|
zJJMI3gmluqL%7OiRM7{Qu(Vm`*CD19(QwuDKj|6VK<KRQldls|;*Wy{yYpO_jYvxJ
zt7A8)jTr5T_FZP*x3P80s;R~sB&|6sjs&yJ4by*$!aH<0zK?*HyN#7et(^8Ct;s8<
zlCQ!>rEvlonsg)y-ku-@OC>Hc{j?)j1UuUoB@IE_QB6+JpQ)1B7YzcJ9fO56;Y4tR
zGQfDpsoD-FWl{YiV8`K~nNMq91pLE-N|x0bkw}FpWzUvU6m;5J1>Hy|JOaar3KX%R
z<?c%j^p_zJVXN$AiGtiacaW_S9a|=fK8NMF8ctg563~v!IC9dzx~VV9$Z}XAL4E<;
z_d+n8vCdZ*Mjl<+CML8L`vNOA;;&5#Q89lB4-;mCZXjj0ZOzk%dSa3f@7cSb{z$y9
zm0IIx(%Zl@O_I4F<QAb>d0IExc6s7nwvbQfa&zF~)iU9PS*d1;Y^i^3^Sbh!Xu)fD
zQYLTDFxlUGoOpT_!1lzY$FhS_wXUg+amoE)&g*~bo#kGX{*C&Vz3)*hy{~@`_L)t=
z2;WuM7hQ0Z%1l-|Aqx;fT7dzpUovu!Ny)Y0P2c3#5J11YL?7e`s=CK%@o-8R^a*D-
zd6`y^%Ph-K@nLt#-G40xnJ6SeD>X`#o4kPWw)(%-;|Fdn7(RWymvLwbuVTAWdK4ze
zGv+B3f<$l$Gm;KS@~2#eju{!Em74_PG0L1WTy-2`o2I-h?(?!fEt-`8dSInkq=MwE
zj-%)l<u@H6NyZq~K9ND|^cfPy810d=uV;fB(DOU~*mX&T#Gv=92R?F2J2AUYH^>vh
zRIZxg1QD{dwho)hPI)x_h8oz`z@kV8{QS$aYoC<OW>8uh>USqb9jA7Npa&}sFQjih
zzhM_o&Gb~X5snOuVW<DC^B5^R9xgERGOmuxt}dS22|tE$$gD<3Vr%^Go)WslO!Ghl
zvlXqte^~nyO-YByi;s!p!-!xN%kMz0&-kOWyIXY6+))hhiKt<anrg)WhgsPk_`-UL
zyr4rl$*sUgsD~{h>n=uo504CQ;2}4^gX_f(t2}%&TT7s*j0e~eF&Qb9ehLw(Jik#-
ze$A1(K!1PQ!HPekcml^TW;Q~$I%!pqb_)`$6BzxHmgLdgs*`P^&Cqt4SI1Qul@!^6
z)9?pR;EKmt8D8-Q(z?U|+S%21cqU$M#_e!YAas;>>mpG2VgJzv-XIsa48KdQpQQ%p
zhlw$$SE*PBB=vFB<%Kxyke%Dps84`qRx~`!?YNJEjF_}er;!!CTf?hHbit=19~{53
z&^;OwA^XNT(7yIZ>j0X`L^}{pRp<54R0-L(h3tu<s3Ih(Y&N9+RS3k&%rtz(8SH+h
z^Hl~cKENI@dXsUh(lLRZ&>l1!hm~v>Wt#;Lm3G55`yb+|{Qco^^S1m41--C=myR%H
zB3am^9_b6xMkCk~?Ffjs!(=74s1)f~tBRxrOMV^Yt)U*fx4f;O$qnplgG8f~h+3`J
zHymd@p&-w%!QmFXv<AT3C29c{+!?+|1JPa}e|vkzU(4aGv%~8l3SE%UF`>=h(&mH#
zTBb1_I$(@Kx@JiF+Bzoqj1PkYy?E`g82u)e4%#+&!_YFJSW}ZwZn^P29)zmM`HA)6
zQKn_xeJ0fbqIwG3^NCJ7MAI{us<Y#&`Fw`;xoKCwD6m&pxvf|S{q-GGqS2xrJ?D(y
zJYHdy6?fCtAVmM2@Bu;W0MV?-Ur#BU4n2=MiTxsm!<5gew>n%5&LpC^qxk7*uOwT*
z#^5ik#Y-CX)A#w)J2>bXamZ{QGNTrr@l1iq?6b81iOob-#<g1o2~^N3qrOUe9=2x}
z-NloSI<;^w7;!ALqjFG%QuahB_eqpB;+-Bfo%Fc7xIX{1QL6?+)LQ`Ev)2kde%#lS
zyiT!dB*E}~;#NbnaA0wZgPSy&<nzWu_030IJj1ODD->ZW$hl(XU;mON1o_Ue{u<2;
z-;LQ=q?+v_cx7gyO(ScfR#Tp8((_qVymw57*LgT-;5!M`*fU_esFEfLZ2~qZ{j4Rc
zH&L~u@ruwUGJ`^3w}ct`o8-thVO?msA5a!(fO-s;8#b8DRX0FpKUn!$q^-6k&}JcC
z;iB-l$)(x-13?7S=WE#nqp2sY1lcByYuE!QwCYc6){P~B9tBygC$`=>>>BZsMZo<`
zwt1y10j!VZu*K%T<9wSlVCIjt6j$&nb{As?6b~KeuIg>;tiG9z+{8NHi_xPC$Mr<l
z{Gj~`^(EN!Z!(=@u_Ib=dN<#@Ptm)#hmT{wE&`eR?!iB8Aa0{}990BmmniK(J`;WK
z-410YH+)zU_1lEIHdaRpyojwNn6TR<!PbW^NuomsoujyG&E>7zhv!a?ghmPBp7q_Q
zP4il7%Av1C0;A>YI_kAvH%{|PzK6I<(Qp?w-F=~`uSeWuy1ctTFxpLhLNvbq`9!fx
zT^@loD8~Ur;o1f@M#@Ky6mupjj>-Rl6`~9n@8Jh|%Fj}PS`;wO<M`@+IG*3{!#U<A
z6o}vRN9+R+a_Y9k%x^lRApBDZ2+1)k1TX2Rs0UBQ*HB3+apM@blcG#}m7L@0jul-(
z3AZ_dtBx3EU|hJ$DPLP;WdT!$=8npL#6Udj-uAi!emQ+i=384-^BAd@6C#n4hf?#V
zY*kQYy=h7SJ(B*|nArH7kKcW7$aXGRl$^Sh@{*=io8M1Gs$myQeG+ktdJ>E)w(BQE
z$UF2H{~}e@J9i^u@?M;`acfj}*szrLI%8wB6+RbF-SX<NY!<#|@7L*$PlRR(oH`al
z%tFp9hb~XszU$7(6jgN#O7*6E$pOFaCfd3i2*}mt<y6mCtF_-u2MqXBNO*SV7K$MZ
zeA8<lDl_`K5yn*R4l-!0lQYpOzhQMpAm929^TG%<w^Jf`4b*rvEI-nT32Cua(ou)o
za%D#7CT$LfXxKCNW^jhh<IF6B3XL+1hHKFn21pFul&F{=qM+7hi<2SpoCD-6eArbj
zD_OQ1ua~AY4_+%dc*G=LH>`$3ft41|80^yw8v(0_4@>YlxW|a>(`!evr#3jUB5Rt~
zMax7^0J$bmNbe6h(T2)chH0Mb^6j7{huc%}4&H^S;aaCG8AMU8SEkh5Q`K-25;CQb
zs~?32-|J!&NSMK9;s?658VwL>rh#$_OUF#2GIHIGSB3ks9;Dtk!YUKY6c`XaAbRpT
z@!szN#@r#M=@EOHo)qNNI=XsVy{~_Y+#kLXPP85CKw_xko`8FUSA3e^?Z@}w8sWA4
zDE<E!+hL{TU4$r!qGp5&dLK!j^~Uw1Bpso}c(gY@Iy2Jf4umUQa?QFwTAt;Dab1Mo
zPSH9BMCgc2j8<#)T-p3W2R%;SXJ&0<5suB#i{l*9MzSZ2Odb%psEGpQyDhFQ1dFpa
zx771{pJCfGM)j5%h_g0(9A9VK3o(`p(B`<IM(MIpS79z4XI(ZTT))kU<+T5CAaV}e
z0zAib(1<krMFi%<H(?PGVSVk96}N342*%`|fm3s0J!PU5uyx}hOQTqhTs(!jcySHq
zUOqHNNtxV881vC#ERP;P#3o_Yrgco?;D02kd0gPhe8n>%U_kAPO`&*vve5SphfYcC
zstw+;@9yoJ$DuVgg>2LtoNTMARihS}*S4Bsn*j4Og|EPDiK7RG*s(4{)jQ*oIdeOu
z&2yz6MchP?${EU2T<xl<-7|2g=nlTqD3X3hCb~-@mT??Mk1B3LQWLw$rwG|wu+M^f
zy;pu#21f`oD@Jr?a0$2HY*@Bi#6O&``2j&jKX%etqDF%rfKUR!<8GeF7)gik+W{=6
zMQFFpmr$b~TEnMPX@XgE;wL?8Fn3H@wu@u<5>U_{Q&YLAc5nuoFju!XfOM|106qQt
zl^)6$p|--O_P6#GhIOet8fVzw?y|)kjVap*?BV30R)yyt-qeQ|FxNM+d=_r_^_m0s
zQ9?eDqQLZ#vXUJYvl=}ePS4nD3v=$!Xxi}eeugo)jnY}qDO7+GgvmAgUIx8VIHLhQ
zoWb|et*wK4f!|l#MgM}H&j-<bE??<0N1Hv2M?MA00~zofFl6Epz;^egXj8>D(+8v)
zzD#Qm$$plxzdcxU92_s}eD~{j9{F#m>|Q$h!CJZGJ7%Zf1n@C#Py;C~d!Fug?5yU|
zBQ)NWwMKo@5Hyz`Q<u}ItO`<kT?IM*D{m)}rON)A*$9$Rc0x}-4fpgOnwSXo=RTlF
zfTCQ7b2U2M{dNTVK#?Pd1?g=>j0jtd(Ovm%IR~9r$vFl#=VxjLB1;$N??Z!*fC%pW
zjRg=0{I|(s90cn=WEZ%9i()w(<e$PZ?4cv>f|wlqp;aIlcJVHfJ67T(Q=e65(yZco
z)3y*{)wlo}_XX8B3$)RD!n3hvitOyX<l!Tk($;s3j4!ab4(?J5tNJSz`n(*ZhS4Y)
z*?@m!6WPE5(22Mx%MzEGlrSCf?O6o(TMu6Cxu60?dbm6zl1-#6ef&mEB~}DR5ehmZ
zd{%d8sq%8oT=h^alGT|olfY6OwBVLj;{U{^?N#;sOrNQ~mVetpNgTLwUOgklqU%N*
zUb>wXxgt+7p52jAcR5@{5y5=n5}83kmkdg=V&@YyZuJkM^={0}k?488_DXN(OVAW0
z2NhK((H6{}yG^bZ*6Rll0#p{?sozHtIi|w7G!kBIcD=XB_SoN{QyP4tZsck_>7@?_
zqf9UX?99T7q2s3ve*FYUlEEkQ8R^OIUVBjX<jipXnb{`5Wl3*mfdGJVWQ8jSi`nTO
zVUT_9Pf7!8J$|;F3-wF-!6LA*Sw%`{e>CYdX!J0N3{!ot+@-Wd2}yR!`N`=UTwhxD
zvMpH%0(bQY+cMs~gS2B@b6uuP@pF=fd&`K0{s2$xWZPL(nab*@A|wSh==<j7bjk-d
z7a$q1Sv*UP*VXW0k6j)Lb1gh%hW8Ggj@1IlN-7jSy}mSf5^Yevw)C9QK=V&(U@Y`;
z9))N$0OJdtC$+|fBbbIoTrCXPY5a(I@?rH9Wei{4DnQVB=U0@nlL`r=7qGug-1fuv
z((Ky~Q$SP>BPDf6GJ+z3L&{4e&1-SeE&tlzjYq&ZSOF>UzbyVcqEe<mEx^*oq>hqv
zdv9@<e|$rxL8;xoWg9emgWH}z2~bQ;6Z5q?df)(*X88isA&2dB8pK}bbhIYh^}t5q
zSdv?6Mpm=@@+l2i;mQu*L-ee%$Hq+)3YkO+T;8wYtJ_?fAeKv9L?pS>>z-yqoyx0_
z1QSwA%aF`!PWg|OJi^zprJo^N{6PFpp|`El!aftjbrPDkJQ&-u<gz^l`_LJq*2YSI
zn{U0+ayC8uCxSC9?QwiI_)Jk!Tq3yh$7;uRrawx>G>{69>$B!4OR+Q(rnemJ)d=OL
z9uJ;(cY1z|SVM~>D3c$oVFflP%Aei5Wn70J0lMgylo`RHl)Q8)%VSVp1mx++C0Q89
zW*rf$cXw;2V$L0^MqbOpUp_|-G9Nd)b#bpER!zwS4~bIKN#Z(+4oo|VfhfFM3vUM9
zV3dV_{-@$2&>Bwb_b+8_gR(ae>g;;rX{GQ823-@(V<@G+-|?oTW|Sc3v<q}I_{7sq
z?ZuH}O9Ou}LEwlEC~Gz5!fP4Gq#4KKcn7iI0bWDMpBJ};q782ZmME^vMHSH9e1E4V
zlotTs!DVyD$ikCs7mDMxN9D6zyou$4bs_dGYd%&sKWF{U&NXe#7zSJr{S`<{U5}qx
z+|~-*bB!*Sq6paMh9%TMe~^njoUWg&mm;-nJQHQrK$+n&ip8&U;zZ1RQ`a99b#A_C
zrp95oAWfHp0?^F%mO7<vbo8PkyL&;;mFFE7XSRflojoJ}F}g<qjDK&q^pt2ltRszq
z){LH@{523Fi2A`D;9+3v?`Lc0K+krz=i#xjqU}rsLDvSp7<`vI-rPe$QtInG`uN>U
zQKptTlWqu6QM6ZIc9iiNw7r?W@I<B#4Qox)#$2&y>y5UXI@}AE%UfB^0F8;kK;hZy
zkPkMB<ss4ExH}-eNwb>hH*=KrWe|J}#n0*YjQ!;eiLLGAKb|>9k@H@Gb&yD+T`m#O
zNX;<V$(>qSlMrr2R^-T!AsGlTYFJ1|4c`xUAg&}vFNT)_fGqVG2Nb~^bv@0utm;5~
zx^p#>+oI%$CclqlbF&1+Pqv`U6juWGZg*Y_aTmp_nR9X2`v`Q)pWc68%e8V=D3!2g
zf}GE7sCaMm)?&rINW6lH(@<4f`u5_%jMQ2ddn^}>ongwrrY=X4STS_7l<3|*|K#>4
zP%IF+(P$>W<w&B;ZJF1v*%ktw<Cik^6n7Ckxb^tnGUKohg-9O{V*v?J(2LM?!yTYh
z`wNub>F>t^<E`8Cl0>Vk1qV8(8kUIN%!TB=ZxE1;9BzF9aXe}vNG?0_nF0`+;W**C
zz3dp)&(BV0h1d~O=WxS6lR&2tJ!BhHSA~=nA=KVEh$ZfhzAPs`Z@Q^B68P!v-T6hV
zt@xv=a~j(3r+yjYVC=+21><*>My#)ffUty(8XxQf@tLAgqDDAz&P31$I08bWsTc9Y
z_kTKk`q3!|-%+F#dU((-10bGcXeiVeq&Yg2kb$?dw-5oqB$7JOh_<$x!pE5Dc>JE9
za&taWbYD#XS*A$J(>~F-;%yW2*0@h2JW?ikm2Wnq9^BU;b&GBC>yZvBe`O<jM*Azy
zP=2*x0+wg($#Hg4eRUhsWZV-5%RIFMv(GDSU6j~(=tJ4M+f=?*pl4c3(1$!vqdJeW
zMB79z@aBysu`gzD1Sc)!3R~%bUdTzZ>RCn8ypg>w-T*s{oHPA}z|7$^ZnVVl<{&si
z^i&w$O?ji<HGIdWY2d$Mw5q!2&NoJgymIb{_wfMEYU7EL%c-t%q6W=_*N9gb{fF6%
zIKb032c*x!a1?E<qHu9>0CuuJA|U1jr`f=KcF!JRIJeB2t-33<PxorV3?#_w_WcA?
zf$ZXm)v2EK58=X!t@EhJ>ZRE@fIak4Pu|Tjk!}9_kRQbf06s2WgO~Us&$rKl8qxhy
zO2zhV|J{9a5*s%BKY}=oW99-2T_mk(VTJ3VL{7gv?!IQ7bdKISuwg&=?z&{zU%T#~
z&2l63uSuP*qRnrpMG-F<0oMjbWMTeeND9=SUSj(SThO0(4-%^7X?`fI{QzI_8V)rw
z3}Yo^5`l1E;I^B8W<!JpLz3AdL`0GF3W01X0}T`4P`3oQE<fM3gIxh+IsXwcqqR>D
zfXzasbjHEh@y~fOMgDO&Ay6s(1P~RfKPCaID)>)W)xBV|g~38mjyuI9=*c5|naK%o
z9f<T&AG4;V5rw&b1XUGhRHoZ9Z}w9q$&<+aAlpv@z6kvDMj&kMB$+N)D*#xz0x16j
zmK{m+(J>qOmJwQIPlTi;_2v=Y;aLQm!y}g7YiTGc%^WMzlB9H7d6O=hq^xP3%=)oV
zl5MjaRJ@4Vp{WL1It{EhDP{asX^ww||8LSx<WqhlF-iVp3sMj~m6spN)d971m4RuY
zd{tve=uk1W(5c}z%_D`bpGDe3CGSR?4=46bN9UzYY$ojrGf4UD%Yd_BsfeJJvFvN|
zSt(0|EpITvWq&fhp}X3V!;F%$o|3nkvdegS3E>d?Cd0<SPU%B80p=@T^pbd{+IJbC
z$*H&_^sZ55>TF32I+EyHaz!jH@v?XwqKOE=o;3aL3l?q?YEY*T`-4~zjjLI8Wky<%
zJ4vdAzV!#)B2@S>CmUKv)NcCM*L|Hr;9>LHXj<)vSsli82B9hG`5sImv70-sV?&N7
zK;x060-KR$c@-s<Rwg}UUD))>fX1IRsvCG>yklBeS0sTgg(Hodtk+ZW#7`itla{3J
zyH>wf9r_JUz&l+L64oPaZp{|qhdr}&BtE*)r>%14H(F2F;y=i$zgLhzyOD)0eg(TW
z+ko2;dyV3jAI``SH>uBNuN3P_$4tbd9%hf_7%=)&Pa0p2kdAvW94_VR48XTRv=j7l
za0>2@lJ=k5yRp|(i7U-mq5|*wX~g|%7^Nw`hI~*$lP8(oJU(y&W1}Aq;&&{wN2eR{
zK?)>y;O3;^FYyCb8|~m!*KA(5r1uZ{T6d%YxN^Z+m-H>&*G_kJNHO7}+fvj?$bTn2
zxM4T5j1$E^?cStZojHoKC47u!7hcY5>jBX|fH_RwW(a9B@taKvN?mwPh)M^o04bK^
z>b!wA7q3%WAO$bv(M*w<A=P3MB*$+ZtMGOf6L7i`y*Qsr>W^{ag0q`X%WK%Hpn$gu
zAnXyIMI(fdcO`JKy=Jjr=4Fkc6*0wI10N*ua>$UPW0m-ckY*S-=;289#otk3%;k&n
zg}CxXY&49yUfj?jcj45uu=qq&_SH^WdNj4sYf{*nUn^D=98ZY*uIlV&JSdc%T;lSm
zQ8ajGs%hlwr)=i6uT9iZVYPHcjWv{po9^-?1h#uz@$U&qSmxlm8gk_<?|{?cVBX4n
z`V&bU(__!~jmZ3fX{;6ZUS1tR*2tkK#<<EK={6+K)LurSYQ%Eu%=3O|O-jpyxg$vj
z7z(c&Dx3FQSKXK{?NmqioO5sHulJ9Ei`<F^W$}Mkq}`;#JIv+@?#SgT%>3%|V}}vp
zN(wZbGrwJ-7t|DS7M=zN9#*KkqO`8ug&ASi=<b6*9#5;H(KAgo1XwKs^7eanNTBra
znSo3Q__qZZfp5a^HwKrhPRhX%xi#zXAtJxL<f<fTkOa~r7QjqzK#bN2z_wCp=84wu
zT8UwrvAz~xMJL5CMqmLCHhN<Et{?STbfm%I8&r4x!0Rq(N`&tHQyV|*aJKgdb$G%c
z_zb18clzsoPh`N2Eb()MbON%C#F4oQ%nT#a+qK&jtLHpyF1(LjY{pLqvsznEVFn=k
zmrIQL0oGXGZQTrn&|xw*wCP<K_OS7-%rKW#L_e~dpG%sGysNK#t+}ieA%5D#P^(<M
z*)WBpKp=Vc7}+<qry4ItELz-Eqh-O!b&6fu9hWN^7AEWsC;;leUw&4DbcOD~gvTM?
z3#A!&6WH5P`<SK!)X}hGg_gX?>*~-y2$>Cg#DE*Hu<VSB&E?dy6w&7@dj9{iXZ}8W
zKl%yH6U^UgN(T0x$ft)RMZ5aZshtb$K~IG2p-0z=LHCx}SFR$|f<Nk`#$~3^Yl(H%
z_!h%(-utiX>&xXlGN(=)j|fr{=8W|9V;!Z)+79T32+%~K{=gf!bsW#h=&NO}1&{<d
z&Ev}KBm6_75&OLWc12d^7$16WKMtK$DcHh&Q^CHFs>9dxnl-VZ(t3CM^Ks$Vmt{C5
zyI;gyEydVPY&?je)3Q|NUJ`Vp_9bn;XVWKB5y8r@6fMw$VI52WLRGN1g1%c6I0u1G
z$fW>b4pnN3GaNC`Ud(oYn#?zwKIoBH*2PiF5?*52ATTR6-6dnG;7^4DYSYBaNOh7q
zE+|x+{!L{fWuYaAT7Cvr<~-LAG<Exmh|Vn^7VT79c1UnKTaD%xn>Vk&YGz$iNp^36
z(Y`Dg;fx*N^f{d~PQJh#s4={(z#E><j3Y-0>&Jl;@S~Hra^|)2Jk5v<cx<#<)&y9_
zkD9DdibdDtBDp`+H<DcR)<k-F7G8CdJ!Vwqg&CdF5OIhDWCxDyW_)X5*fG{LGc!*q
zHoI*#NhGQs(^FJlC)p*{ZLgKH&8P4;1sMMYtKU!H=?ra>_yn_s&f%xNy?%^B#aI{v
zpCNN9<b2<6dLY9%p%WQQ2s0KV8;zHNM9<-@32XM=t8#Zn;_SZC>FT$62)~JYsJ&t#
z1$J-bEq7lCZz)7#s^*GH(1#Xf3lKn867W?PWlZz>>Iiq`ailz$21Rq(k#t>0XCRO7
z8j&3xgZiDy=aU->x}+v~oX;or$UYo7=*ANGNjIx07`t*fwb|^FW4VPmqzfm#<<Bn8
zQtS~UFwE#W;&NP1kC~ZiquYm3xS}FgxEF;T-9aSMjNe><{UGxiap3Ufqvz)nBDU+1
ziD_D_)~Z<Gi`XbI_zQ7aG}*2XjCd~~73$U#i%}vvmvCpaYePUFvZue3?IM^h6oIlz
z1{isjIlm$amLle?Y%O!yH$LIs<^A#3yh+w!QvUAtl7Fim)~GWU`TupO)1TfE6}6AR
z7dQlZBk6fP_blcoqWbF+F~zrYdl6qULLB{WUzbt3(|jaIx5$0XD|<$fV{xr3kMjGM
zW4?OoBEuu?{{MgOZ@0FZVdWOw1?gG67-1kMUD1RCP@3Qjv`^Spki0EmzGq`}olC$)
z*q(KH4^QK1%8le*I}|;aR-QV6RJ5vbVi>hB^`%$h?gg<O^tkm)g-ad?^0cM{lrw!)
zooNiRN)+2_MLBB+r*1Yo8%|_Y4D1uy?vh8jHz-yQKrAf(zX~-&cd#I57lUv$`-vPR
zJhffvwj@WjmIF~kwY~qs2C(6#xKxso3R#x<D2z_-ce<};?JV3cY2j!I1#!7np<mqd
z#J(vpeNQl{R%imA`IZ|}A@!a)VX&PDMy;4rFf4Hh|J!n>`4L$hxO<*qNoBA7@AE{W
z8(DcGTeR;^@mmko-^LKqDy%qcMsx~t;(jrZOqC9?;@^hGt9o+&Pd%Bzoq+XISarHT
zThKk$)U*EO0bfg5>;3SQs%~Z$pd6rQrVx)F1wtaNygof6sI?ASzcu%2oT%=mIug~z
z#GRx8`~Qh*Kghe?owj~bver6@)Z8=Zs+{7E#A=}XS|z<)_4i%;(`XeaK$&Ab-t~Nj
zgv6i1s;GD@gq_#XKi<x6Y}t0sx&y5xaa58PoydPI!C;|yu-vCJMvzaZvTE85(NT*O
zm++G6UaeCZ?_(Y_%Navr)*bBC@w4y_aC2P(#|Q3Vc|q9m9!X*HWAodL#SIEQ`@I>v
zKzB<F81HVGLUJU}lPgZZAyxO)K;XH<0NsPwV9orOyzz`oYgab^g<f|;&}v{<7Idc9
zL&yVv<>%3<otNKVkDUy`j-<@{jK(2{4D=;DTr_J9tjk%w1&=)CpCAlOpdu5sM7!B)
zmV<7;Zg!fdCljh9eXbH99r#oBs1I=>Jk1GrZYp$J0DDw60&bS1dJb$t7fncC#Yhb(
zq*O*D@<(AE)Fcz@@uCGQWM)wy-I!VW`OwrV4=={vMK|7to|dTC6f?zvLT6yU>#cT&
z9bx)ER6Q$a4RZII@QHyd#-|&M=w8Fet}ODaKi}+7__Gh8hrrTBy2%qvl}Wh*SKiu(
za?Fcp(0Y(qaM?F{OgdD>DBb>!2IOIRJAH{R`UD>k1i`uiKRNiL@{UTw)X-wH#%BeU
zo7)08tdSNK$>A+FS-q5a|1ljjEst98=_^XUoR;B67UzNNs#!<82E!59$yf8BtF_!{
z$8`=yb43m80TXI?gP9yXgny?LxL`OTUB%|olbqA`OASohhlPN76(N*lURJ7OGp7d4
z(u$oyfEk(BctYi6MUhbF&w}Tc&>`NafC=`Rkuu%*-)&w%wtMG$&C<|W?l~dVz4n{W
z@FT$-I~3Px=2R2<Q2s|c5?IrsXuVz$34T|hWu8s)loiVK8f%Ww4<;5R1RL5HJC+xO
zO=lPO$=4qUyH9!rDVsI`$Ta5XqrW1SUDc^9H&5eVqf`QUP6Emd6Otk#zhw;PdPhIH
zqQjMlSkY7}T9WTmy9<J-q?GdhNPi91{E?L@+;%!?5{wmEScs+x0(Rnve<L)jiNQMX
z>DZbJIdR>>XLSRdoeyE#poO-?Gx{17qRLV!Lhp1Rk4D7y7d?D2VU`|Zz98(?fxrit
zI+t_WTt7(%0IKce`5#v!!Z_q}HToWpNbKcaA~pdG6!He8Q%$nRRJZ?!Nz3_mhJB52
zsFrqk+=Ugq3eLBe9DZ$>EY%K{>=$&KLE9Ui&Rk|1>FvQybJ(BGR|%VZ?&=I^Y}dM4
z((9sZ&c9)O6KnY195UY$&Z5IR|62ciM0=0O?z_Do<Kh2_rr&YQ5e{EIq&hVBAT{wM
ziAAUIMz*|M!{;k84SrWBkMNnaX!LFqXK<4h_ndB>4I47Hl<7a<U2(3N`a>E!2=F^v
zsWN0WciJW_C+;|DvW($}vlP421fM6J6lU|w1YrRc0qXt|@=P0oX3YNvxitF<Hu6q8
z1#!YA@+HG&jUS~`2`CMhQ}?0XYX4_s&piA-)hzCyM6QXH`QX}O-qta@74F`Q-s~hV
z5qtK1(2IQbW0rWtEJ?J2nPuEJ+V}T<HP2X(eW!mU-4YX7T#n<w$P|6YebrRD`O_55
zSFZaoFy7;B>b{4AQ0nPHADsP=;~GIO!`f=ux@TqW?KP!=!kDfAQ1r*Mx<)5$eo1zr
zB}WwM!mAeIWfy?9g{mD%6!?Oq6GUs*IRJDpfqr(@LY2Azo+omj^FT9nvxs_qf}B4q
z0t)h5i;LjS887KP@aju^H$~&)2apLBvpxwDuZ+2a8H@C5;K|N#z9GA6`5WNSMRr(N
Dkw0ND

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_length.v
new file mode 100644
index 0000000000000000000000000000000000000000..5a61d5dd591b5a8c2bc6308652376c06bed25ee7
GIT binary patch
literal 3128
zcmV-849D|}6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWFH6Sh8ZmDA5WtD2W`
zFJCPT$hh;j+i1BqDqK=O;M$TfaFn|-t&ob&i23zs{OW6&J_@vlOd0FFM<C=kcn;zf
zk0VD*;Q>T@DS&s_d~7n@`}Ru`gH|kbQuYT#-2-pa#YuFg@%BbO(4g-p))lg0k9v!E
zOX3>NR+(Rh{y{PZmRCo^!#_c~oGd`}XpM~a<E6+}R^uYKpU*JvtNCuYuFJPvF4#LY
zjji3lqK82yx6<29r%Us$8cX$;+r#>3b;qZ(iR~qmMz!xBT>f6aED(;stO!JSfN4x*
zhoaBD5z4Bc3;p&lCI;okYG9VcqB?P=$APh6Bz1%|hTMsk(#T}&I7@D4Z_*)Ll+LM!
zcn5lDAXalcVe#%PPXY$0_{zQ;3~@9Yt-ZgXir3=#mG^B$PbTt~%br6i*LunnH>#MA
zI^RCXQ&3wgRF)GRTDrPw>qk#nPP!`B#cpz|vpe;;F?lz-rox$Jx{1+G-UN~VhbEp0
z%eJRsrCvQK3HbbHM~L^We8VV@dR!<jF;yS<DQx1z>6AvDL<s!KzTltnMi_AaiClu!
zTClT6xeysJ#v>&>u$WNd86-J)rjW88+#zVZrAW8yP3{SP+~!q4$}#$=MGpwZa_hEW
z=!peFr_Y2GjU?|7%D2g*Q~N5JWJ2b!2%2l9254=fUyZ#^9iF-aUh#0hk7Lc2#ah?K
zGFdFm4&K`Hs9-A(we9@;s2k;+QJ?>$@YgB4rlsT8CeXJpl3n*P^DD=4dL1?3)y_;~
z9*W4;u=x`WB+s6P9vamxy2X0McaL(j0N>!)1xS@%{H_sbbV}*Ox98bYRD=D-x5Si9
zH9X)avE>35yt;IUF+=@HbDSuTEqO0E3mIET%^RDBgHW~`JuFOjjJ|-TB8=t>%BW8f
zwsOCksQa>Ovbh?XVjh+S*YFp+-&D^tUf%{rgQ}JQ9VXT?E!s8=ouq~bbWwJ9K(e#{
zT6_@@@gsSEu371RXQ71Pf3|!m6-SndJS3DkI6WR*8h<h^4XqZFJ55CGg;Tf!=NamB
zS#G@{F`K*Yu2J(3q8z}v_WHJA4Ch^uagre{tr2<nx$9G6vMFQ~h{Brq<@D7ohQcdJ
z9g~vUgC46Y!s_K<Te|5(g(-FIyHjIt5mZT^a_^S4=merT=S<+I)YXA-in;J6*H}RA
zE*`G$yt1$n5S#>?NL2+{VI}gD$(LfXBo(NyFZRpz;f*<_Z?NqpvAv?ei!=Bz+=MWx
z*h6il1;k_Ecp*E@1oh^*{$#QnbhWesqc)Irg_o0^)729WpXzZ1i_p?ds|!O5&ywuR
zZ%`I5|0}H8!6-)h*z9`v25c5K{Dc4k;(u|aG^R{5<x3q9yE=zeR!AoT)iSyIX{N?k
z5$2_Y@+Ej}ogJv`)}T)=jcJ4bgj{&ainJ&NFKAD~d&#zTkR(lfeaK=!j~%<LgTcHw
zFG@RO8FTVqZM9iy@5B@lbM?sat?_U3?a^r^e8YY*PHAmc6CqPCeK;qWKSn-T&(X<~
zOIOfM`QnlfqZ9A_F*;t5#x~mjlOvP%aHNGs!K?gThbf4JAno_t_lqNIQo^zEBylS#
zrLiuO+-hKiyD`xGIc6~bC-0A{@X&WEneol6x*X_gg5(+p&;8)hR~D<IVLS0YyhnIz
ztP@wx(FY#YZyS6WNk^OWJI35SG!nK(XVe_mX)B!oT_xE<^<xPION3Mih9{qC)(N!e
z2d?||2hjnyfS{Sgw7S_xeV258*t9w%gLt}%9?5rlG-=92GKI-VEbx&e=c2OWLZtZq
zf(rUJJ@{XZG^EG<8PDNcmLr~9iVc=8K<J2I^}`8a@{z59a;YYc;tU=>mn!5-@VqEf
zvgSkXRnpG@K<B9pl_^C-dQI93vl>&TW<|Zvv~k!uM2K%g2As7JEWnjW6A7LOO<gch
zXVcxs(og>Mq^gTiaEJwSC`;de$g|vpz+*ili_ekO><<lT_onZ*Fz#}4U?HGXN5#b)
zc;e|mdZ0q6soCX`+9}7+;}R6<=`gj)ad_!nA!hj)=}2l0UrW{&e^!BWomo6-QDsj<
z!XJyrrx<vuTD{LReWIMCx|Fg~sBo$<vgd2kb_tETlmdEb^&o|-dHKBJSf1ex0b2aS
zQ(kILuW_CQqro5AB&%7DOY#!1_b1uTtL_X+#L$#;B&@RP#w{QkWO^Z0hHOS_h1fe#
zr?88r8iv;Aw?&WhKe^&vj<zdHS@+McyDha5_7BxvEBqB%XFIZ3Bo~%I1Hztb2?%{%
zd&^>Q?0od@g^a7-%2&(_g0Sjl8yk{h??4G-Fxk0>oW=rWR_gIuaAE{7z^Jcs(cnsy
zpu*lh%UK_U-&|BOS#IY7547W-<1xB>7MVQ6XQjO2ZgZp}nn9#AFsMVd)@q+bpGheg
zDA&tn3c=nek*;Hue~swvI+<c7(tgv0RFtR%BE&NhsE4}MriB%+DXhd$W3@`e#ma-`
zgK*edz|(uV=yePks88lB_+QTLvan=%s#$V$iRd$Qq<Z`n^JcBD^@GEiaTY*hb#y{X
SJ?X|578R<`=;~v%+8R<n@gnO0

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_ff_read_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..90f15e349e9abcbc5b39464e4ad8e62a408f602b
GIT binary patch
literal 9952
zcmV<6CLh_06Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|Btj@oSfe?>MWF@fd7?ze-QZhVr*kA
zs?P~}o*Vq}4%R1SRe_|}`LX}zfEbPF@9C#~Q0A~xG~3r<&HTcGQIv2sS{P{b0$L5p
zuvVsP>+CFpeJUF7C8^%f=}nU4!i=v^{&WqoS@dtcI<L2-5)^T%Hcb`WrN8XHhdpG1
zjFl$9%6Cf7;(u`k2(dH(%5`!sa{fXM81<fo0sBy~T<n(*TOxA{X`5lC3*jR?t!$hR
zTra3@vr0I}##Rw*mjL(#L+sPV!zcspz6^!7BNaYR;fFsK%2ZlW&ag{<tl)Zk*xI%+
zl+Re=Ph!;{^z8}@YC{TONcNb2fJ>K?c}u(>u}zhLcS-UO8!r`ju8yT2WY}y*X^a2>
zKx){XOR#%o$64yz7cGevl{e#XMY%NQ;VQ9d`<pWUEO!#9cJQo9kqn9L-%~YAL?H_l
zy>{dFdG7T~5-`Ie92NFn*E>e(W&j>4jv{kSJ$`C8*JP<)1XRgqRV=7BKy6Y2f1Tez
zP4ck##XSu?Xe1u-9f1VJiE_P&k}_VrJp(vClY2G}*RrCRm}moh_sMU$io`@Gf8=Nh
zLd(t#J`edlJ#~-#E`$3*1E3u3B5*c8!~$kI0ZA{n%IU(n=I4DD^p71U(mbuuMN=G+
z|44!pb-Q1{OSA2zJrQI&1*ivW7m{m>>wxCTR~vMoO@H%VzVF~IKqOk&fr#3V?p(8=
zst8YBF>vX~aDh9#76i$<h50H`zC8@xs<L6`;*7~ex%SJP1Y_bvsYU5$wfkpE45fhD
zkKXwS0^y_nJNT!qgcoE$0%LAazI-iJ1<b6;&FUfeiXjRM(ERiC4V+v5Ncm8)R=Rx;
zFcx9C8WAO>&#_#WH}@yDN`_+J+)oD+<l54QuZauKwM1#pK(~Xm`Gi?DM%2LK;O}FC
zPsTTh=SnA9U?&q81V%xm2W3Pk8O+bBW+D7Z%}vamKZu7#{T74k0c@|&5~&SOJ)tdG
zrm84$FDgbTj{1y+72?<~-zJRxbX|k9O!Oz2s?ZEc)ve%)W@Ex61q6L9Uf4>-s*zXh
zjzB~#)hP*3@yl7zi^31hGiIb<aGH`_*5-{Xq%}hB-oVqC-%%{YAsa#R+{L=dQYg@g
z7xO>R4N)loC*}BGJy>;uJLin!?|`AO^Sp0Nvj&m0V-8yY4Crd8uy})NJ_6qnVt_!K
z@CYZDP>zNaO(*Xmc<VqE{YD$j>@?q2=hE#i4)!tgW!t59j%J5heUrVI!#DC0+Rf6$
z`x!3OWJpi5(hDNRCkldQ5)Gj13PUU`IREFZkX4f8%!<OfN%f7(J<PpAod7n>yr)wU
z7GX1a7F%$+XdP}c6T|cK(0S6jr5DXM@-j$6niJQ+ZhUVZnKC~CcLZ*4;i^rFvOVc_
z9e=ZQYY`I%#>QWSBJT9c*<^9@X8|2PG?;=|CLl)QnByz~;=Tuu)g#-&gkKMT{s;yv
zcjZUkU-?GyPsO2M>v=o)s5Q=E6?t2iN9W8lq4}>d_LAP>jvJDJ{o(}}q7{Ysv-v84
zy6^S;+E2mYKEy0T`>`&5IUe&gHlcabELKgVW8TL|ZCq;NOkJJxCag!sBD7+BoYOU$
zDNmxaU4_@+v!ZV9tY{5+Plxd<f|8l`7`7b*jGFm>>#P^GISdEtYnQeG0UHdbA3Y$b
z*&cis*+@b3iaZ!@?F6$#0Gf$?q+)}v;=`YF8{QNYu<?sS&oXQ<v+rpaekj?N^2K?&
z_;3+Y0OT-wm%x8Bz}C1HoS=4k+|$BRfj_N?(Wy}JF><n%Ny;hVmfwP|%4cFkrAj=%
zE8XQe!`)=xvK~ocs~S+Jg?q%8Kj0X_Y1C+*`phTr?QY;E_R`0=Z48en2LO{F#10b+
z-PV)U`gj|TF(dq1hQ$qq*B?h4P}Tj_wq^E8PlvxaWMURu%tbkLf~DrP<3*T*z>nnl
zgiD&S8Ga3<-|L@|;j$<cWaOpW2tURjQL@c@(T&!$(eEzVmir)PXxw!cXt}PmmKldO
z@kUHiQ;@3=-V)h&GOZd-`Ie&N_W9)o2HDdY3_)<FBOg{vsLyJ=!<nMe$o8zOkwsz;
zi`r84?ma)#mD_QH<#y&|KAG4#Dpw4Q-cRC2i1<UE|IL!0YckV_-T^Y9_<%TX@@^4h
zvg^06+qD*pC?rJQ(za(d28fX##b3r?RvHz&j6=M~b!AwH>^1GmYgM^jY{#r5$WV**
z+3sjXZV=${`tJYo?3Y*&Wjl$^FNkCLo^bRsUjgXnQjScAoC~T&O!v`VWZ?SXtfy2R
z^<kEHXYl^iEAj}KfEJ45%(Rre>>W9(+u4<D<jx{~+YSF3w`%RZP8vc^q6VU_ME7DL
z&%$WivvQ&NH$3%*Z`Y@(CpKC)F1B~G)P&=S^&?W#+Fnm%_g&HQ>)FX;QYX~&SJywf
z_P#GnGjmM>`JR57il~lqv`aL}atqU(LXMEE*Hc`vEes1Jn46BSN>P*A0=8U5)4zV&
z;~=Ni*B&?47tEBl)G>b$Tdl*r=uh5AgX0gtQH@<El${S!P=3FqCte}P-o&NF?uH7~
zZ`Uk2)DhSA9t<eet17<2+e_tn7sS8ksJXIAEH;F6HUgW{ivc0Ye0bI|u~=42OX4wa
z4?d0zUXNumm64{x35JoOI5#Ol?xm$YcRn3pI&CxXl>ejV<hq&)6jN~*8FzWTvOTX+
zrQ{-?YS9G0@RfQ^Mtxb~%clR7@;)Vn%UG~`oDB~jPvn)ov{IwcFmYSlDH0Gh1BDaU
zd9>8A^L)aMFT4ynzk<ZpPTxVF1!KB*>)*pjg?NuZg}vqXY7}J$Z27s`c*F@p-*q>n
zq2Ye8lwr!h-_9u7j1BIeYxv4Dz?igw_`hsHhd3B(urs;nPcoHyjWVIv<K%G3g%@^S
z%?ru0=@!79%@Y<?^fP3htcx;BhLHeRTQ}3PNsJW5CLT|5z5S7t(CHQ?;?UMuxvsQr
zlcM2DfugXx-c6shu-VKKb{rSQchCmcGaSU+D}n!Jg%TMMt~O*WUbCb}2tny$!)IF*
zuzlnt+U)JUA15w;yD~di6-KwNPK8t0O5bX`+~muc-n@44Nl>w6m8D*(av=%9(<3nP
z{%hm^MwOdIAQSqZ!3b`2<%XUEMuyk21i(u;NB3dQ(RlVX&Mj-`<PDFnPTD!_?-ukF
z`sfz7;m>5UAHqmFy7y~fq{;;6!PsRdSS2RHXq$a5F|=`?^haQzpY2Hj#{=IAa+*Gp
z6|4&U-ceYHkZbRWvS>9pfdXto9>4_fSXWQNZ2OtJ^>f?L<5wqjw}eztGGwOS8{hA5
z@A)Bd;Q)<oURxDbR_LrLppz!pVo311ck<;hUs8bRWSrCr?9dA&mndDu6C2`n3W;vz
zI9|qRcPx$<5*X=ekZ$dNPeAtOk^a0mB#Vk2Lf}Bt#Dd+1?A1`+ErDZDL&&}J5f&gT
zM#?Z&y8|ZV)bf#aY?RJvb5wuq5j}XR2egYZOJ&M6Q`jSd(XOa#078f|(-B~1C)c{;
zOr-PMW=g2Fa|R2OkPljI7UMwKl0osK_FYZ3!b}L1+WkO1blA0k;Z;j3yTE_~;)<s9
zC)frlbf>gqJ=Mxb{pM~Y(@org&33P@X$xrbV=V$N5T|P`|Gg3Dq7lhp8mcxN&4(u7
zK>SBNh%b*IoXtkV{;T^KsTWZ<Yr)bX{9LG805t&QHK(u;zb&T45GaZ36SdWY@=mYZ
zDh<lK-g$n`JzF5EQBjHQdIWzd+n)nM10W>-pJ;lC?&WP@lrca4;dMIH?`^3$VfWe_
zfZu{si*Ff2N<Ik8Ua~-JyNSHhNu|a=phCb8=myw#3$1R=)57FHrFIZ^-YYQ2GT`Ks
z<!A+vp{n?N(DDz1WeX!mjV&m)gOQh`XZ|tAmyZO4CMN`Hr8j5BEX$!ov;=Z^*mn#t
zcY*9`(3q8$z8qK)KDd5~2(0A@kE6NN4WPfI1@ZT$Io%6(ct;V>D^cC2zXJTZEwY7h
z(X*YeVQ?UU?cqrc(8(%IRkPU5|FKUgDZ%zhI?Xf~$XsZZuJ()lS_Zl?eGuv}HXhV5
zW!X!wjB|Ls>y}fkFCrNnXlbN2PnfkSSxO+KcVWlXz91gv-<wAU%`Y7cnez#3DiR7t
z{{^nS7kv7<XVD-~bmTF9Nx@w6OHV4Gwj(B}z&Y|C^S_7ekhOIZ-R(ID3Cp3U-B1yf
zcTD_Ng{&-CU?1(e-*m5S&P6}v=+-mE(e-|}tFv7Go>p?}U^)zdcwm`A0w!@w<nEdS
zJ7EQ6a8FNdR5#)%W=IAhbKF4Xe!<a`0iz%C7puV)umj3Ff)m7=D;}@{S$|I6?TGzp
zOs^<ICEA1;J%&YrAr~c>ZB&X3DYUnj-*g)PLp_2n=Dmo-jdLK*;gB|O_3=9^mkqvs
zBOLX8gAK(dXg&FE@T97JJa)6fQ%L(Bnn)OlLueRpBfZtVht@|B)So$h$nya5P{$jH
z6JK^O%t67fQoaU#*n@eBTP!Fk!&``o2tEEF@a^!HfFhuQ_;$%c&oA}|_ix~Ya05R;
zT4q5N;Ebp;C*6d5zjeT067qH^Heh~JARTHD8U(xqCn-2k%uQPrqEoF103g&!$FBL|
z@J0q^abC2~%$xcP8+`rNTxU}<U(KAV$`s;mTrylS7Z}FOVZ8Ur4-CHXnmU0oj)>7V
z>_!I!o1_X<bWzmJIj(tdLzp7dGTGI@{}a4hc;xN!%S?CDjnSn#o$~Dc>?1E&XJQ!U
z7ul(#91^2t&z$&!^PvZ%v-334x7@k{utFxet$z6(vF*-*mwH`pe1em*h=a_<_yj9&
z%)6D#5NBuhisA^*qfr3iHb|t2fJUgrgI42&Hf)UGq`kMv@OpW0DuQa_uT_5BgT1A-
zM<T@HYVc}x)keE8u#h;haTjA5?db1JIW&5nicF*Sm@<=XDe<QCTm;bOer%C*e`*s)
zAd8bmDd9Gs6VvyH{?!~i@tQ+idw);0<{w&*0K&LUOCObzeo;T$3&c4eH*ETUo`r{e
zmTqFqbK_cN+DL*Re@yjwI3)TenAA<*J|+YG?Gm6_5%~450SX8xmM4FyJcgG%3aH*G
zs7MU1Yy-&hduRv0=_ryn(D7Dx5LnuT@i)J;>U9Xi^=Hkyno2L8>0t7Gle)-?Y?*-C
zO<LgV5N$T{keS!?mV97o^h!pi?QP_L1-k6_Pp3j%t?Fmz9-G^a@W~ADJR8mhWkpM&
ztyJn3i)#$`=UFoAK$F+LpN;i>7*K{5%6sFh(|{I}8NhhTdpCX<q)O2`9_SPGxd1DO
zdRon-NYi$NnGFPBfeB3<he3`7tp2}oLsPxuxpjA?91P^(!>BhI&>MUs10a4k1uZYl
zKLNCGH@}wggpr?j?gP-6w~J2{PmVkk#TrpSRjY#XpPduKbv1~|I|4olFpD0z$;6>?
z-l2{<mB72)ZrUijIHSqcXkBAKmuMcRE4tB&0EFGnou4YixS1!nLweMZXR!Y_*7&d^
z>hm*lxdZ6q>%S!Ji}4-9>OkY214YD^#&OG1N7<Eks?+$J_ziSV2Z5dbI*yevw;<t8
zkP=AMB~qusPI89VT7Fb3#0~-#O2Ux~R3l#k{Kf+YcNLp%`tIMaSu=Yz5Db#7`!t8<
z5&^7Bngdht3@IBbX)5>w+yN|~SE2+lllCR{UDaxt0Q-)2k7o~O`6lM#WsPjNU@?YK
z!BP_9rb=WQC!EhVzkf8y!GqmQ;yCry=>)(Xw_2!IvpYCtIz;LPRzwYoCeBoU{elF4
zi0-NX>b=OF8+-BB>huBLZ{Ozw+Q{J^t_wJV;Oik9G_14-*L4FtHVxX;!%Lb@;Cd3c
zE-E4eZQm&8u^<Lc3{UYc7sI@lG<ReCV7wAb)Nj64XTQ&&A9<CZW5^T?To1MUM4U{|
zL7-ca42K?J;%3Rki)3ad>fkHefQm+NU?f!2Q(N`|++>QxhJI!rd&R%B$}4-n<#C=y
zhwZ2>e(wJYUWKg^4G(;Q&)mJV<BnQS=Y&jHt-JplbiI4LHf|(eL`T&KKprEiv(qGU
zB`JdCc``nuG~N(?uulO^v8fX5n=tOI5s=`adAzmOiT>^!9W8p{M@R+Vkp`s;?!EU=
zMaOklGgnt6bONF?U(P}uBIu5?)-aVmNnx3Z4@Z=ODx1N8sq7jfvH$j+B%hVxrze@w
zk;8|Nx9-_knSX%)E7^3Z3<)x4KpJt1XjKfs(q5mYa!=t0vh~P(vO1am)6zb%AAG8u
zo#-n;E$1=NEU9_emh}&1%LRm~-@C7Q*ea<=(AZ?Qb)HK3!^KX!)@1Y|p3pq>Yj>I5
z@ZW2HIk;!pt-cO^w<yDVi^72IsYnM{iw6tA(vRUM4jk!z+7jz_c%m2tdR{d$=TA22
zEsdHm%*1$*8m`x|{^Gg48AKMz=EN$3#_FYyCFv!&y^->d&G?_CQC{@kJFQ(l1JJDF
zC9*;|w@Po6=-S3KMa4p;Bg$chDDG%N;%qCzd#KnOy9yOuLC_DhlxHWXP&iGgUOJ(>
z!dhct%$_y))JMSs8rjJV$v^0m)r5zT*|?U$LX#OUfH!c$=@onVgt(na!p@Fc)Vyt#
zK=ALQp(Rn+qv_|ti>AAt5MOt$rc4Kt(F#K7huBE{PKB)cu_^Ik&zTJ9%|t*PcLYAM
zxcDj0kDHp&Hn$+Won?4xPyX`xdhQaOi;qM^f0olT-b(MT_g{r`xw*Dkv6^q>=2ZzK
z4+^`}ey<qqCet@D!X#(_M}ulCl>AbPYQXgKk|uiJ&u#jW@ksW=(n!P24dGg2NFtQ?
zosRpqbwYcQHWcAXrAh6?ny_#X<;=No0Nl=iAt!8?8S!h1pl6BxJFag+LRtfwrG?lR
zk*LaIDD-RwrGKve7b0$m(4c}BBcj0oqZqtkXdv7;>Z~bXUiE5G-&x@Fy-R81=V`I&
z3woi2-!22hK$1OxmtNlPH($t08gUhb>&D$u&WD1tlo|Nu*Ciq7{#Sj;Q686)SkPkm
ztjG@G8}1Ph=EbCSRH7K#6BupLo$mY^m90sT(Oo#!GEpO>`i4Ugt}R?%V;|0V;e%r)
z<aAAy79}!}o8?6)kM6Ggk+D3x??qKVs2E2eqJt&Biehm}4|Hx&qmqjXL>w0-hxMC>
z<p!c5!*qZF>|=aeKrAa&p!85o$0STv`iZksbf4jpN5~JZHYKgF{6e8}ho^uC`iGNs
z7)8Ys;zvMd`6ho{frM5Tdy99!uoFuQvnZO+mK~Q^;IfGsvS($)xf-Ks*R;3~o1GrS
zcl{~L!6>0{!mfcYu>(gS03i@3t&zso&1lQcyhgnR{3xH@if<UQw)>Bh=~|_yN5?aZ
zaZa^e+OT@l`1y$w7W?p=7<CVj;YgL28=yjMQV~m1TBin0<D^Yhk!Iy?r?IwDAWqwr
zZngiwd3(m%`NJ$D3U?d&YPHO;2oX-5S1-?>MOr2Cd7CZT6x>D?J9SSt2Pa7rjf`y$
zt1Tdx&-Hv2>WE1I1oA0}!g(pO!FG7@S2wwyDq(=`K-@k8E;)I!`T?}@0#WC?3$mP>
z@GkK4Xk^nnDKxFez76+DP0Zcz^-1aWit9a%h-5u{LXowvn64cKcZw3VIrC={-7p-)
zf}ZsK6;K4(fWLJeS@-y#(WK%f|LcN3k+nhC-Qw#8TN-9H8^K14Tj_&$ts(_OoXxxf
z6f_67C3Z~v5mgdt{+A=FU!fA=q-|A4$iJXr+C*+EwESD?nRbf5f4>u;Tg&}zxj#RM
zJXzBJKLTqlaroPXW#WKM>A}H(LNaXXdZc}L;dM7%g(l4p<Z}q>U?pYae6p;1vg}9+
zy_jMQz5@vcAb(_V-7~{p1>uxM>U_*GLIMoO3s6;D!7uuOphDgAAuY);km}y5PKfz$
z68ZL~bT}XN!&ICsZPh-W0yqCvw1ts`n?;{nuOjkk`E3Q|8R`^-WXiYeEhQaawe-mO
zYy8dn3A^2;)C_Kp!9^DRbo(B3?kDdc9%(sCwoN0K)y^cUDZmyt(0IYdZ595--^PXe
zpKi^sd-Osk`-|$PhvwPTKL{xP3z>#}b@SX#y7VZmGM(hm{N(6fH#l%=ALwCjS$1y{
z!V`*?X#t;F#I|L}c$IQ1`ufu|V{D~|_ZpysEn>ix?&QfT>n)MdRX<SnhU$OVZGp1G
zk&l6umYPV9j0uIsMA=(sIE0?*CM1TS6xBO;A_zf@!FEo0_h)|<)k;ipXJ(&C&Vmxc
zJF`hE&|BAIE253G#CZG>W)|G<aJ~QE2Dg<!`f|~(g8}x-Z3(N<#QqXte)K)<tDvSu
z0lvK;b@JHxZGvRPq5p}Q&<?5sE7mVwLDn(F*}P<=wAVTWJxFLZeS5fHR#8Fa#13q!
zenCn!7>>~EYg4Ms(Vo6Z`fK=Ckt5^uh;pr>tCT9$bp8YM=V=l-bPr_U3&h=M${vzT
zXI^1{&%^O5T?3}jl>RW!e_?|YPqohzHNw#O^~B_nvU!qmo&cd>SO~aOgx?N-MKd9I
zFG%$Jpk0r_*KvKEmr+tCam1DFaT?9N7f9&oIC)iLbB5Tj^3T&Qe%=eTRo)T&P8!u4
z3Va}}c5pwwf|x=-^vqjad50Zw6bl(iZ4#rXT?)*eixTjKJQb|V=`dD7^`z&fT`(AN
zQ%E860zU3QaCImg1YOTXDaL*=P6SWg3~O=cHrA3@IvzCOmlhPkDy^<kuX7+oXIMj{
zmA;c!U}ZHs%vNF~+!8pX<Oo`rKPje)Y-C4U*^O?y@jo_6WoF8!F*jaCL^FLaV#1!O
z%x60F7OxoAvXqrYqKlnh)NxewkFXaMeScGg!n9=&7z$}4jNA!c)sp84LBajG)2g_y
z#4URP;25TM>PlUY*J#hT4l{;uvcnw%nYs`#Xqv&|#WJn;(nZW&K+7V&O<x31LV+#&
z?eV|`luNr9@OKj=H=D8rB@F&(hYLr_l)|7d_Ct~>*Is!vyONwrWgGsYPF|YFHXD5V
zeOu7DLf{!+*CW|>gj$$mU|<ITCp~VdWTLaN+Dma%CBv(!c0gr)Cl^W+%SSuOG;ojW
z3j#_fw8+r9y5@ZCws{borZnhJ+?vvraeS_0x5Q|!Tdt14YA*|g#f&p(Dc0%X@90aR
zVQ>;2--j7!?Y^t0t+rF9L`Cf;X-^9eL6i7{=^)$6PN${H5}^$KA0rbnxG@zBn7|PZ
zlt}|5Ce1XOj*}ED$;n+#WoHq^7NF{Fo@$wlMi-p&K4p0zsC=0loW$ss>K9dHUcYD_
z6Q2t&A!jndM#1CYFw^Q2Qj}{N!$18nfMk}JW2R(_O?ju|3pG%hqp9P=3QTeR4|Rm&
zR;jgja%A&h0yho@muwvODal%zYv@as9VBBZb@aygk4R=kt=$3xZWlPQZlkU)giDJn
zcLi69vO`staQb2f^I|gR*9I7Qi$5W$MxpH?=Zv+42^9^Vx4-BDb@bx^s9zV_<<)h3
z)8YL9bZypgT75^d)A327Zy6bds`-ZXqCZ56VmP6mo0iioQLfvSP+as3q!+BSzZw7h
zHPPfbcxRBG8JEGv`-T$c)SVUG>k>}UaN43;<?rR6_}1SlUBSK{<~{xIJ~7idk|_%+
z@IQf6N^-q;DE!ZH{`AU2%D59in=T@|m2j1kzUo>=cf#z~kzgp_2sgL8_Qo{rG*F?!
zI@tD#j0{FT@tjv3@%Cx%r`fjLNbG93z)U+gcw-rV2ec(Gm;QrbI`<!b<AMIpud5pT
zC(Q>Xdx8jiE&mmDLZThZw1;_;7|@#Ues>~oZOYwZQH1Rg=DzE6o(i>`#KDktZGvP2
z&@^)m;AN2#v+-I?kDA<=z`Yo`A9IUIS|*k8Qr?>$(P6wn)dtW0alRCbGG7imb9r=?
z@(u<AH2pbJA+Q1j;NWb53eOTeSu^R4vfPL5Hl}tFcs2j+i|F6I?NBq7T6lUuthH2b
zzP8Po5ke0aI;_5{vUE%^(540NYjs0t8QqISBeB~{W!EM<Q@Yo&lfhN}d46%etk{uw
zK@4HLRlR_^ZU|hzUr10PzR`70PfO><@*C*{8lHvzsGBAIyJ72HuTfJiSb(EQejydF
z{BF;b*}r7^CY_}x(4{MF{lci%ft;ee6R-qAE@}xqG2+Urji{PPfwCVak7lZ$eU+_~
zbZxCm+!`kl?^Hz;@NzF%79AKs<{?e4VR_u@0MI|%632%5FJvT&me*>a(3x=T4_i|y
z9$&BoLUNX$Q-L~l9b3^xw_v3aJr=M3q+9<}5ENEFIpV!URm(VQ1SBmd+^Te-@EAFO
zV!~8chObUbauiAl3VIORcAd;}lxo||YFSaurDJ5q-IzO;2mWi<g9T-Yz8K!2O&dth
zZS)G3a$KrxZMK=JXD|lVGu^mLjxunz#Tc+x|H-?*aQw7=qw3uaeiNsh^dW?j(x>w2
zB8l^-e4<toaB=Pe6=|?bJEShf@dwo`U_B5_=tf?XNl|ra7m;%r1s(PxWBztnFS=l1
zN^uz+@E9mGZKb<72HveJ2V*D2^{A3l!ZtBaI%T~*lI_|*zY|i)tr{ra=o#a*_`*o0
zvkyj@Lr$h+g^=rV#H++`FQV#lhCzY2S@1DL`6VBVJzTTIQ+04F9M8AoI$np6Q~<y9
zC!UN_awlHMdN=D@4zkcW++?w=h5!-_Xdb?w%k4OiKs(2!!e%+lCc-c66U~F~bGiL4
zjWTnZIgTV30<yl^Tye&5NrZkapCgaSQub5jGv@F-<!WUOd3gA_8LI3L2rbZ4_0W<C
zt%K0m_G;Dy|CBo5lZRzC)KH#-m<waeb)Ih{C4TKgpJjFr$ZTThG+&KLtlA{m>=<MQ
zL8>aM&Jv?BSv(;{4jk}Lsqq<=(P128GZl`$J<F@`RC*BNDn*!5*u9PYawxzbRhnqq
z?kE*$?Gm4;e~Q{d*^Q*Nu=V27*E4xBDoF3KEY=;SK$)t*8(zXwpy0(m-r2nn!*SEF
z8AjZp73i?J;ZkAyH5ryEK_g=?6Kaf@Lg#&`lD$puB>;AxIaNfOAYm;QZYRSlBhPx8
zK`X7VTvpj`^n*2Y%c#co@$<_$I)V_Xb$gTq@N|(c?!)>Vi|ey>FBZU0sZTr>@?h2G
zvIMCmgN&=QCT@(^9(BToTyL3U^q*Q40F1Y?Y6xgkF{qWkJMH#9D~%k#Uh@H7mu^w`
zu7Wd5<mzKY&i-H59@4=Nc8uSZ-gwk@<5P{;s6x*`E|1@FwqiHDkVc?aRGt5j@2+-P
z1B$r+^j2Re%xi#_1Fm8dQq?%W0CVmG*1A|2m2N&Z9cY7@Vrdl&R7Wg5_Evs8%7tlH
zP)F*HrYEkzI+z57J1tP<=9)0DPYjf`M&<N3^+jMy&sh|<0T)2z@UkmO(nXl{$sD>L
zoRmOo?T<i~h!3VoN(E+IHOIT(uO)EH%$EM`KH1}nHsDo##-2Fj)J<wEKQ2>Ry94f3
zsi!~Ki#3I_avWPibR|B)Tcl6oJIj>o_Lbg~SM9ZP#-MK@?JLbzuGfi!HxAtA%GUx$
e>Y}f_g<U9E!)z&t`MpYcyXW+O9U;r^X@5P1&u4l7

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_min_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..46199ea7b979362e9235708bf607c3a0cd3b8184
GIT binary patch
literal 40448
zcmV(pK=8kd6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+WN;r$O
zGny4NohprakRCN%4H2yFAGfEBjq@McD%kkpg=CUvEui=`@(^Vji6brobqDb|v<GpF
zDyoT`#Htig=~b|lyCfCr29jS|H{6YVNI}V&slY)QpKDvDk0`gfy59#ILhI(j7wvrW
z`e#lg2S<5*SIxW9oF9kdYnpr7^Pmkr^#)0Iht=o<sdzy@h<WyJCT*}Xg}L|CqFkPp
zOam@^CwT9Nn?6JXI)UPDQcgwZ2B?4bHTU@>>=`Yru>|#C5JQheR|x^U*Iu!$d0<$5
zNnRU>oeOON+f4ZE(?r=HWZ(A2uEsure8KG{Q-)y;nZ2_*W>jZ0i3u8h@_<$uD3nPU
z{#3TRyticuLH;cJfp^CuWVD13C(>CnVVf%|SK}$%R9qh$a?XQHaiMTYp5Dx9I^Wg$
za=TfkHB|TLV}4Hvxe{_10y(Csqu6(-O%G+qaL7PLqA`tfJ{|{&h%DF{q_a@raDMpb
zGi5~W@tELJ^0`kTB3E}F(P-h$VQ%t&VJ2aV^b{Qi-4%2<WFtVl87zxXz@Xk$x2iL<
z=p?>uOa+xfVJ9P}(KZhN0tDzbx9g@Gs6T0Jl18<@cC*%T2zXM{#cK(QyJ;=Va8`21
zVQ=we5Q-A!uwH>*txx)R*%cky0B3m;B5lZRziTN|>gTTJt9FI@p&$RV!Z7L<%jU2W
zr&owSUcF+;-H`fiZHGKsqL-gBuiZe#{E#WhYH80t?+?;jfQHhiUBc4uby<ldo8_<;
z`%jKF``eNNAbjJ9`YbGna04Mba!!q$)SFU+ffzVL%<vOc=D}>=w*@dQ71a+}cnG>~
z{D6US5PYYMU-@q2NC}`(`N^!Wo2kv<PF+IlHIomCpXgfvz~*HRzFd_TAL&*K=GH`Z
z4wwV9Aaw$5wLqR*801*#yf!*huc~oNTvd)~FTxpnn(k+}x*U1A3sc4sR12kUuy@mt
z?9}AB7ki0g2vjLR5{IP*U|~0(M6o(*>k?c9fr<P1DEvMT2F(Ueus7$<26I6fPok%)
zIj#YR&Z$ImF@{tc|CO#dzZ29MnA8@KeZ0{FuHIKd4WL0_Oko4^Oru?(2SIb<7$*ss
z1TOD$neFi+q?@xyENF@qxsBGbEkioZ&w>cgJBoP%c8|sq64FI*0ows&jOY`BSdQN@
zOTWb5e5S3q#iUPiBXW!y{F25X^aTLxMrXOx`0|0_)rUXJh1NIY0m3}*1GyNT{fy*f
zkTUBBcqwu&+Ht_{>KIgWUPvX4{RFF|cQArr6a?Y>Ddkj}HxNvzj6!L;BgMSOhI#lZ
z+?ZZXB^{-O3v~BFJmLgIk1Q*|KAz#9zJ{9W=LxgdU6V|uY5<Ot$%PuckE{q~H)hnF
zg+!1EUs5u#9nv$2@wKSln<SqE#Whz;{ug1op<YMfV;FgYO5_I?*LbMi{+<Vuq^kHc
zpOT;xB>F3%X=YTTIlk2s5-$f<JEA$9u(c(SaZ}_A0Ax65!ggX2jQPEv14k@I^r0{l
zQV$%%a-9d1LQMyz9voM+dEOvcYGsA`i&>pouKCnfKmMQqth*SCZMkuFR0BCfhSuib
zj5ao=4l%WGzZ=$t1-FQj{vx~y*rc<FHL@ffrvd5V__V!$)fPQd;FD-E32HXm8OzB?
z2J-ZH4p@2Mds&>PbB}{gh@c^-vDbUwzFkP5>jW>OkN*d%_n*fTmG#n$L5tWXy>Qj3
ztQoUF>3NGz^y(Lg>Do_&;3^pT1)LP|)gA3mw#{}(u_O&vSM#bBNebw7fm+Pljz(k+
zZkAwVMGKyqwvVVCJmKx}gxW=e5@$omWEq1OQnDzrIBE$dZPfco!D|Ci+~B^Ap8x_(
zX;9i5v)VN>Rjh~eQBilBLXlZxhs?!41gp9KhI}8@25wvT@|QZac!#59V*%=#@fM!)
zN`MKO2jo@{xH|X)6Vt587^pyO^X9kCcnkN1H$3h}tZL+s<wL*<yAs!6F$CG0<>(IW
zK1PRDkKCPR=W23ook4@>pqvtx#l~yaQEU)Ofef2Y9TY_v_oqC24RYuH>>Ef5|Jarz
zM{Z%0^tFdvI>{A;gP_ML9)9*QG{@1^-7{HX>POF5qf0!<Ax5)v#gl5bFIoDi_PHIq
z_)<fN*Nkh2R29gL$A{Kv1nCKwLAp!#6;pp`D(o8rWNe1%Ib|Z9@m6>f{$QSNBOFM2
z2mcmFIBL1y1=C_QclEeH+*7N&L&W>&soNt8%=6;c==AI`kI^~-)XH<l!fH5?Lxrd-
z0q@jnPyL;<2kB&Ymi_w4S|a!tkP1O5Abf&(m59085bBEl^eyAQnxwl=B4sds5~r!9
zlZ<wxjGm^NokL;fX!^RA?`c0^#!K=d!x#^;Iq9eR*tUn0!*$qT&w(?q(om5l;GBAF
z6w@wiu<c7%rd(Wg-V-0(H?<hu!F`(@=sY5Z-uH63es?}}I%A9XpnI~UynT@{GnZyL
zn4q+~{ib)c;1cLR%8^PX(pC3lM6-35MgBC#3Bvt2REO)II5$(ZwjE-~bD|-CK1SDX
z07f|}6!UekbPk*OVya6OCV^xOP(T}zzGbPMpuGGRM}7(go&QD}*koWHhthA|F4#(!
z<<zq3&Mo-!Nd?PRxIt`<bWOGjY*C<4;i|8+_qQv(od%!hLO=izoP>6cE%;_m3wd)|
zeQI9`m_(lCi0TzWg{&%{@N?(+m}i={6Az4k=oV~{&6T3I8RjS4-q~75GfN5Tj;2fd
z<u<v}<}W8I39>B%4E9j|Ailkk=zxZ5g5}0x=HfylQNolZjE(sSD|@}+o;xiw--?zo
zjZwlU3R&cEhCs6n&G=^nhQhw`7N}rEFXZCjHLKP<-xF@cy!PGx7;#etR0(V<C=8$)
zi25n(&Be^Hy{xK14?gE^WQ{cf6fhI3I!jdD%3WpOpwb(Ula>-YhK)&f4P?XUM`BAw
zE%MY_1GAM$5A$35wP7K3W{>|J<RpS<wL_nwXqff(*p^=bd`CEewP$ZuWB&i^R?~Pt
zDhMWRPHY8%ynRQ&`q(a{P|r&=skY<5ggevt=SJuBg{!fP94aFLUwXe3?&ytDGd4AC
zIlFSjq(Eiig}^UHRV;;9py{kN(Z4WXe^k|$eD>3z`*We;!;Z+Zr#-67kiU`LgegXh
zQ$D55S$<zK_V`FWQk7RHWs*){EFV#LdY)uA@c^5cao^^muk9o5yw5oV^t%kN^~<_3
z4kaj0-L_roh`zGeGMG(&<`W{Et;K_Uj*0`Y(ivB-fCAWh(bC{ug26I0Oq<Se-2X*I
zYkCDuZDzGJKSD6C$I6UmlIoJ}(kix{{an>XShpiT9AI$3!}2VDpRx<%LE<JBP0S(}
zf_v?}CqlqLMx~`MG;bS{@9^1zt$xwNW|P)V8fm`}z|xCKB>}I}3LURYgu;VwgFDy#
zz}320wyAhrUi*IevrU#oZmMc;qHtqCMscsIxqiZoVY_GV@f$+N5cra(WLx4L7qoKU
zFga$s;z0s3qb>D=1tU?gSuGvTL-jsKBF&t9+2uJ&B<dv(FbrdG>$_0T8FrQwGAlG0
z#CTW{I0(tvfsUlTc)NY-Dqexf_Rw&cv9?_fUjcYSb_Y6@nmb5(O6EP<aj>9NY_twk
zb@S(hzUD5r*4)hW<5|W>Zms+YeSaJi!8#5WL>o<1_DUi_xWh24Y{da}VUh9dGDq7Z
zBKO(YytO;LG&xDVmS-Z^W)FI#yo$h032ZdBJ{|-&$gARLZ)k%ncp4xlTiVzpRd+zd
zY!WI1qW+r=ZTvaFS14LE?GseZ@4RF*{U9p(7bZ~4%QxA&dYG{Vmf*Ya{oi1AdJ9Qh
zmIaB;O+yd?+j*QCln|hDpw$L=dRY(CF(QZP;Nor?-<E5o2;UD1ll}<?zBy8jh&90s
z7`{D1o~Cy$EQiZl?c0mljr@3G#n$9%+=$$24=PB~k$sGTucgIVFfz8c%ZA;Q%@1nP
z7(tXaFa~2B%DjW`1q0-Q6I}SX9A9d4jS%JWKU5yu`U0bWiil=cyx|NTeR(z7Gg!q;
zxt@q>ywuYrQepzjMLNUf?Mz1!W!0?BGxudAw353JA<9ydS($cw87GhLE^<`pHlw*L
zo8_jXr-3})!3=SktS@4Yp1u)#(z-{nat6HBJJ#7M2x}@i$ETc{)N6Z;9rD-Yxs?dO
zIRy)V7;r=Y&E+8iIwo8Nm!M?KI>^gwi7>9vQ61pQ@jiLo;8q9Ko~euK4%V;<r9~*1
zJcPo?Cdok#;3D85bAR6xKm87Hv<Qp&Yw;~A)F9=!sW9D9>Bu6C=~J^9i@aN`BM0@T
z(vlS{bF}AlZd%13?kt-Y?dGV5I17}KEb)WZX9yssA?yMkH8@$?!D+XxK?XRE_NK;&
zN6V*y+t+ydy^i}PI*?;o;R~|l{naNxD`SLCQOqrj{e1G;uu*_OSKDg)7+<GJ<P-CC
zh9d;@wLw2zohVQ!pkj-<P1Ip9T!C;xH0$r=Fi_?JYy*B--AE8P=ZFW-><V@Ad4?}A
ze=z>}aO;l2R8syzd>O=b@7CchSIPui@}{o<W(T6eHUp0Gz|*TRgudaN))3M-mvHOY
zg9fX4Wo-|&oS1=!jnoU0{ITXoVn@nAQlBJR#CmH_r|P=_@cYD$=w->U{icI7G;^kL
z4giSl9b?KqLC01UFN67RJ~Ab&1ye7?g2p$lX*kmNQj(~NU;4c%$RyOonN9u+H#=%i
zhTQYc5j6J(CW1sM8z72IeFl1}H^F`KeU=(PBwZ4jm!Xxep<5YFBCW0+9ufqal`FO!
zli*bL8}RDBc#@p0b=WXAV=Wn0CD4*twi#5eD=z6SNl464vT1J{ysa+d(V9jP&%pbn
z)|G;oV-;)~U$~^{#ZBd5zU0^BuW6X76~#C6h}(}tJ5tTZoaeSVc61$PYZ$}6Sj5y!
zG@EJhso}PV+jd$=ODX$ENXIk14F~%ctPu3TKW#k^@TydJ_L^)pEe$ylMU@+O)|kG{
zg@P<O`eZDsn64WIj=NW(&t5_$!ip<0nHgjaCl_Kg*xGWq^+*Pgd|l4X^+<ygW>ISd
z(-Axb-Xjcaa%Sd6xZt?!LfRVGT@%3K^~MUDv&14-uEdL?3kR5}_(Qz;3@6gB4wrX(
zI$OCqb(f*r1Eh_z_#WE3%Y%(q+r=?;_&G}^QfbGZaB<&_-IlujMpTK&O{N{(>R=pZ
zL^8etb!SG3=58u+)!y_ZFXAx+)!F;S@!+OyBEo+H8cQ1%R(x5~L2Ac1G`*k*T}nVG
z_*ed=ykIHj-DJU;UWds>wdi6-eKv`6si{rxrd2voZ?uZcg;{(fLK{$P(GIY+lnCEE
zF{SnbWg<)@MvhmCJS5K!7b^f7Nzy-_+U{qj4_`=<sc<O%kBL>8bWk&v-_7-Zw`v8q
z?R4&uw|?<7tLObLQ2vAs@MwCXS6$$-ZXR(FA=mKVx4dM8B(M8(E$1L{G&RN&MNYQ`
z1R6nkU~{oGDj5x2)l!mW^L3~CN;m3#5XL+rnE(KKRy#4k5VkY2iT<5TP2P`-%{)_o
z=jM{ogV{8HkgBm-0FxY+w^9u@|C-4~kAjs3|K11N_~HIlfDx;Gev<xG6w${J=Pb1D
z!`wt0VuFQ_%I&VW5mK6+ne|YQuT^frN}YIrt|`J3C0Dm3T&1YP&B*Ep`{sb`5fDve
zn9Ag1u#hIWl;RBEJ-#Jk6$N@#GA5Om&u0RX9ZGhAxzV5RCt2%=-EEEZ0lsM`T5nzo
zVE^y80PR%=`fyo;UIh*`>Y0oC#Ec=RQA*^>lGI5X*S{}OpPN|!smQz}7xkFTN+`A9
z^18sUM1K&@_KCr&#v)G0u&}Q%q;_jgf8)#mUPIbEDJgh`U0q7IUTnnDt5StG*n=c}
zb&wKK8>`qxXuVi`Yqpf{P(4$>2j?^nsU8BhLJFRj>S$;Ek`{_b2Q=B^I-<#W%tmA@
zv0@WpXbpp_?y|-`mXuHiO;TlqD0?B9g$@etbOFX|HzC^FH2q6ZC21Id-W8&eepcl5
z=WSu6f_Pvno)`2%!r5oXezKq)zVi37*aE)W`QM1mrlEX9gjzR&Rj*_XuCx|1@G+u{
z$Wi26STK(yV^afN(xrUxVmO+-!g!94_@Z=am7AUN&^U=Mr8<PSY{G5yp9-{OnwNlU
z{408LwH1qfI1ma^#auQqB9odNgHS4z8OsYsF6(6)>Z3FA*2|9tC@Ao=N?UmGlK6h&
z{P*7l$%in9^~7f%hzOau{H6s~#7>c77%o>~B5iDjzUdydiBHN0+QO}t+>B~s2#p<{
zx@Z7s6Tk=|ooo_<0|kstM$N$R85)v!{LmEUSZ#GOb8=r0`w>X$v15da7ce&|8jGce
z%i_qep>Zsn-TbW5_g90<jm8DC^GkD(Oi+6S8ZN)%)~^iv6Pbu|XO{yRBMiA=gcS57
zH>Jl3%Q<}4+}#PoSYo9j_#4^R5j5eR0nTE(_%gK|d_SoWaRlyr;0UGRGoVN0g6}o}
zl`kwkzF^Md`V?d+{#klz4Wik0WhFfz;H+g65S~O6n=faXujvlcMG0!O7pv}CS|2$;
z?5oLXry@0*t;bpENnA2?YIcXu-{X0~^xj)!tiQjvw^HscgUy@6)SNeuHvcp=hG1ds
zXL!p5Zv%g1;o}NI_&NsDi^l8ucB87{n=}UY?&ZtJKOvR*5>Mn`Z?1f=xilU*Goql3
z$Q8sRKh1G1XQZI^64Ll>J1B#(T$ZNYuY{=W7{oz#VgBo#iqt--NJt_ByTUJ#0r($q
zKwv%B5;}wSsC17)ew_fR$3HO*VC9+GB2l8(SZ_f4h1`rjivIHP+TeCA9zpnWCTTzt
zq%MH<PpiZ+Op^c5CuUIXC4eU(mXm@riT5r5yA|VxCh{{6PE(rLg7(xxP8kf7Sm_hj
zB1%5T$foojit08ih>$7RX6OK3iyi!+7^~M8HkBnlAoi`;pfgT7fqxI`2h|J_&tc&g
z!Kq*KCEjdm?VStN^=c@z`nFqOGEuquYpeVySljus%Ad^S`I)>=NNlmpf5E%;^g|l=
zKphiOf6N^IwBqEb%BCac656RP&ycZnZXtVH?1SoE;u`VkdMN|^v+|Q)->~p&04gzw
z%XaVJ5i9dHGeX4SFbB>mPe{J4eFQ9I9Zq0z9W*Ac+6r<<U+Y<XQ>(`lc=OJ?ndoRo
z^Vj_wwalbhK7DT~jg^0S`QvR{BQvn$AiSuh<(zDJM;oM;r{KNX)le{r(<5x=hy3EN
zRgg5;6K<|!)-<|W51BICP*Fzn{{Nxm0OYlaBYRS}c;VJ-0r*b+7xUFjvYWGxP7*@%
z7|9FiWW%||Tqv|8>gFAAbra)!|2+aJRi2_99zF`yz%O?GZCXtEUeVD{X+J_T`1Y&q
z^+Z|(!Sv3Jn`Xae#8Se$2&aFtB#thMif{nr`V8!zTMMjP?6hQw!j*%(C8;?zX2p>0
zw3hsGv&v175!PPqUdLEARf%M2a2~?g4UfQZs&W1UP_1P8m8-K(g7)|z(Zy|;j?DXO
zmU|nyvm#prr!b!?mh<?F`Nvca7gG4^nT`;vDW4>a8Iubbo2$v^iZ%k|f9DZW%<3Ng
zNkOPNys?jr9~B+tYk?N<wR?PhoM%5IN9sl`39iw2iL>$k)7g3s_oA*DkmY@nd=LJ$
zk{gQ)y1CsLd6o`YkkFjy^Ib50C4`B$5E!zv&~x~$9^9dG-CyT)`iTnr2qo?U614%$
zkAmh4tr8DJ`#WBabA_U>;Y}PMv?@0YFhl$eYwM&XAlJd=|9T4>;L}QrlUdn6@uOt1
zJVQ)m=V_6nxN7GC)XO8HPexcL$aD86E!g4TDd7BKUkP195|dK~Bujy~<Fx;8_D<`%
zYkN3mqV8<Y=rHj4DU`*91lw$PGJ~Cujr=0dm5S$Ar1>&-@*xd1o@Wh}C`?}4O<{H0
z;GM6Dm`mbTI#6g%o%1huKZCTJ-tpr#g*MBcnmZHA!r{Nk?F83(K)4(*39U85L5R6!
zgTvZc*pU&Br(a5%8zTCz6Iiu~S;8`hiY!nhS4317?o=OidCgQw!$zT>b80SQHGSWo
zu%@rbY-$?8Lp*_>H8Pb2<sw2)(~*w8HDjDklGl?OUED`VKZGve0O%hUt<jLJ$#-_d
zNF~=l5+X@T&ZC=%MEx_?Z(Hu0!CL00WW6Pl4WxvF-UFq){x$6oQ~ciP_4@!cxQ+xt
zz(If8DRaGG_Wxn~g3wwXgtkWYL%)f1isgj)7V57UW>RX|g_9IdJ-l)&qpw)-e4!?9
zCQl-{D|lu}4gx$XZS4;4Ws>j$hBUct*=uAZorhZl`uPOe`bD1WA4FgJUnnk1Ry|AZ
zp06Y4{ma&*pl_qS;E$P&SnZagg;07yzDQu9x<`SE^`nhdm~RSB7^d2T4!EfI&vfFp
z@z26Br;;w4YfuxF2NXe4q(G(@d5vQ^@D!FvfRS$MkG?-$c+#4Rn>FVp*7^BzsYUL2
z&YE*mIulTRH@J<T_A4EGzgf;hO;}8zg9n#i8uDec3?P=k0T80<$9jofK6^zsx#i&>
zKGwg<YRWv=cS*s}sV-w~gC0c~VD}JeN5o-4hn||wv)j<e-wrG5be=+dZw1JyvW)K&
ziwlh#m9mA{$VDUb`^?mL8MATbwn_`=u>x)~YDMDnK9Xc9(#KOdGqVzG3ahHr&j1*4
z{UI*~!Bj1BY)NGN8+b8-#Y5ayEHRx$zJs`6KozVC%Cnxr=3gLB{YLNX8ju)z++}kY
z`)}h3Kx0l9k!GI0t4#)P^=Ww%t`H61N@=JgtK0uzaO%z)ksdL<WSUbpe?!FMI)%|5
zsBHB3Ffl;IR(FjQ8jsyJ6T8#d6q6G>m6LoR)Xn4r*wy4RB;F!!UcjI8!)&TV7a+X;
zf!9mX4)Kc^kCw3gbzbu8=9RFi3ij{$Q3iD06K!X*@#CMT7@Ct$FMCatxd$|IWg33I
zG-o#cevkZ&xvwf7B7Va|k9U+;IcZ}k(8sm75x=~$y5T9m$c>|$f8^x2q)!4Mbb&j9
zC^y4w7tm`pwNlv#Mzg6@G8ahh;I4}$eU5YV@RJJ1DnXVxodoaTt^*jHk)8kB1BwMf
zme)I3lx)u$+u1F5ODM-5O@4?D)NZpYPqUKlKO#4R)&9tEJk&hw7atV5*Gc!sLUFm?
zG^%K;)PL~=Z5+9iKdylJokW#y8kG1RhIo|qA6BJvQckg6P||eyp$o+%7M3iZd&il2
zE|YI2?91<coUnA;Z<TxA+CHH<fCpHEDk-=QM<TL%&_NqL%Aa+9x!$Jtyg76A-yd(s
zx?RSoZX&UZUSaZDZbHV;mIfub`0~qX&br}Hv}7D)I0$cNRQw7j%!Q9KL*qjh$pqGa
zz4FzZ%z%lzicVezYilDS6`EE60*gOBI&xXeWU2v#W!rm1_9vq3HQyY*iT2$ZH%<^9
zGBYb#zP{Z$R`O7&o#AuCJ!9U=L-5gAMTYhNmjE2sYzTrqGIj!OWhgpg7lR|3NYffL
z=YWrVY(7TdtTyrtO{>NMDxsuf50i9f*5qhUmA)U>!vT;#N{hKh;lABWHkM_EJU7m3
ztkCdrlka_*Ui%bQmKrx|IHYXClfJjBaRS`y2}-#=&lfRy!HU0L_t)~NAWX{lV6v;e
z>F)TgD>pqxB2g5su>N=QkVBm0%+y$C?pTL=`)1CA%Kk)f=sSpvN>0RUNpy~efk`+?
zp0Uzv2d}o=DS3~&BHPRelT$YrxN@}MAmys<p@w#XSd?qaNL7OdoW_un<(J<3__inS
zFSjvGHjz!Bw-kKs6?D!(fxzH6X7td2+K)oDjJR&;6%L)QNh2h>o{0s_eu}HDPJ)X~
z8cFrro$T&^*)e+3OpW&;_|1t7N~vTS;C?Fx4SeFV?>2H!6a<&G{Yn|Ms)M*p@AX(c
zd)x8f8-RL)_`UVx2DtuR*qZshFvOAMV<k4GO|D<scJ21@LBg+~vFu$rRsr%CkmRN{
zz>x>CvLm2f4J^*GIY!m!1eAc4^<1HLE+GRV{6L<JZKyIu=*|r?3(B_6p0UFO2GBHH
z7F_&#a6#sB+aKl6@?41Ho3~v~+ZwvR)s>%mn_LRpx6kMT3P7Txq&l~`NgrYX>p%2!
zXGxj_jpb+gJtb!QpTat0j@=hlGD%CHoj}`T-AS}vzZ<p~k;cYn65q8?^F^DjIzuT;
zqmyTdIQawj3$gTXUnw%c*d7)NVB9neCXDz)3{kt4@$-X817X=Tky;h^N?dnVTS5T6
zLokN#v4g6RuZvO{gQ^7VP98V+Mi-P-kWB$vvh#J}TYX_bSf@G=K7}n<Es<kR1tw(w
z156xC?7wJ*@vpV=S(QDCeteNk>>IOy%TRZf@yMkNkAihsN7G|uPQ{QN4JiR^&ZU|k
zQ_^cRA?a11&;9A(hWj-&!Qk;imGN=@iYyKn9DPVq28COy*8;3FT>tbd=Y~FFYsMK>
zo0lb5qcM#fBmgxqkz*16sOeirsma$@W&Tl{4;0ZBe{(rR;5eD=h}hWjAoNG;W%D80
zNXg53G5rX}n>A`*neK(HxUmfr{z+<N`7=MTc#yh)9Tpq*V){jjbh&m=q2Z{W<PtZU
z|4=^;9JN*iTi{kl%iKuLR)aFG*9AgS6%hY+LVVY`J2l~-v9@55=IT*iA0N)B@!k0;
zy5R_xLCXZViGr2`xI_up0-wbZ3$YMu#{i#$-TGlj)(BzlawwUg(=d*7MECxb0=0BQ
zLNO6#ODFL3jKn<lgiXj<8H!^*#!rrm%I;;k%r1Am1RQiXhwDw%lgH*v(|of&bm<8P
zE8US^tP)5zy&E!!Ikyx6cMK!q_&}aA6JXNQ!K@wL8#5Kb=?)407VGo3D|$o;uZJ@x
zV^xum7*moeHlF!}$1Q~w`m-jWj;T4^?RVSV)1g(_iG;F50&|}I2_FrIY%m||=c4#C
zAj7=;>=>^KE0f;Z7sfyjYkp7TpRSmdm_=YV0?mVB8u24=_NeQ5oDF`mv(-(TY55A3
ztDBDMMR8j%!2;+wUhq+&ktP`wnEVAdq`kngzzs6t3V0*=2GSJgGyCPd43p(O&68f%
zRD#H3x9RK_M8eGQJh)6!LuUu$sh-FmR&{&JUs;FVgOB~WuhIMu75yDGUQSC5?=T^^
zL(+cQb6u26c+6D4(A;~@fLJEu)qw47)wXL|)oxq*lkGdg;h(ntcG`<);Eg@Uxe~fE
z4x_YAMwsnKSLc!GnL7D-whvMFkmm|_@x{K3Vo&qgvZB~WZ`7f=Xjg+7Mf{|i<aTOx
zM;FjML`gZfR^{~{8xUG(`{`8(z>XB&cb<hAb0W{l`MuHesQcAsW;s6fG9~S_c`h#e
zA92=gBtUkaIzhCEqAa9af|<WO`sH(ZCbNvEn#Jh>lofO1vp;%B^~T|+$QI2kBQ@=#
zo>rsj^?g5)9DTcNq9g*vZp-?mM1z?$gTC#R^OaetXWT|5jnwc=fWy<Y5<lZao#gFi
zR*R~kDAG&i#%A{%mZp~>Xl4B6h&c?xe8~dejTRkX&gq9*(hdIet(_t>Vs=1#ProP{
z1*PeXr+Q`-=I;{|&PY{rJ9(95N2H~p&5av+`PGP@yr||u)`mmuaeS>1LXKG~4Ce#&
zpL^~r7jDo0Mj>|jH+4Rs1>vChX8?^MWxNqo%uNRrhPqP>5@_HGkH}AVw@A`HUIJVd
z#49E|R+$1tvKtAbL(8~V+jHaGF`vw0)DavlwG7I1oNDWw-u~HDHb0NiZ>5*tz<6c#
zxZnwWqwc?1GeX2=7n<85JgO2stLn-ruXnASO@fT0IDPBax^*DCKoHpmFXCOTq~xqO
zc^Y1!rT64myLsE<nHw&z)`irA6m2;V%&Iy|zHKa;(WL2xxU*(q%?9v$srpIN6``}x
z5~!J(Z7?O_mDZUny?k}_p<jUU5|ywnpu;Zg5can!<IM4lij`#v+IVf5v+K=d4?@$a
zX^aW+*p0blrf+eJ3Q`6wtTO=8xr02YEV$jq@&4R$oRD{H`HQ*o4)1Em;Bo=b4h#8a
z1`H&4=*6(ocSu8~v$7G}4wH6aSx(sQS)k}A*yyf0*+r!p`f4(w<Qru4Ld}=S^QCNu
zazceACbkCmNe9RSsqc`+u@d~Ym?*xpZUVz4bv)I;RbF0|em>1@9<y53oImgEZhqFP
z-z&_XaB_mv-q{)3+69V4F#9VNWt;!Xhjn#~E1Oq)YQQqv3JP?RP2H1u`2CDga>DrJ
z3Ywr#eNLLYms2X{7+x~!e$)Z>{kj}r&^MDR@3Os6I`o0Xr8p7&J3XStI=ooSg3m6c
zgQvM!4T37mj)=T4IZyxz-`fs5;)~&%-RP8W=53qou#w2{zct&%Ogd7{t*A#5-ahG#
z9r>}y_8T#yGI#cS==_G_wYF0BQ3lunfV{~^6L?Mz_4GQwAp9`gqm^~XKeg)H!*!R^
zI&xg0Cg^u_DR>*^H7X~T`3WI7-!sv#Tu{0guCqx$opqIKJXM(lj3=52^{MiG^83_W
zI3CaABVMSyJHa~`OiyPU5?v3Z2MFwl*gCgK7;hr5vq_9d3?PY@b!n9F_^Br5W4D_N
zsk<R%^7YHGd&`CcQrs|JmhTbkVOR*F+DJw+KHS@Rtl4l>;`|yD)LDY!dji2p@<^_B
z73!2x1n|{GF84eJp=O_9GHTOHM#G#u>1rxpJcv(BTMR+9MA9v5y<U;10V}*TWl9cU
zPT-$G4n*j<f6wY2qU*1XjP#%{IB+;HUBf)#COJL@YPt2xDnxAaMD2;o-RI|J1ae+_
z{~o!bLzGq2Zjw0(&?(72%H}&4((l&kEPE|M+XQLSw|{Hd)-yG<ADDpsuogjbEud^}
z+PduG7h%BR?6WA!&YD4@hvIeNEshb5C58R>2u2e?5lW4J;LR7Ph8~#o4q4I<{o;fh
zFC&E0*+AD!O{G#*$OG6+yAGi7WcH;%MV{#VNK7GVrY8y|!BDr1M>Ld82oJEO&e26Y
z)H4vC%f|MW-lpR1FarEv=mp2{xC|z~B=d_k7$g>EEx=qH_0Mx);<f>yDk%0;c9^XO
zSHkLRKodAyj6E;&8LDO9cL6WXl;WEf8#sH<bSOv0*NfJskLvtcRGj25Fdft;$gDJe
z&;q_40eVs8D)srhuFjuYqZ%3Jew#Nh3=>zvvQ-+-6~kb5@c>)-I`emL$=hT@58ZiE
zTCP@rl(IKz+LDMMpqH-dQP-=28(*_15WWE9MgHah4BMAT-DP`agvlNSCm28Mg?wr-
zZ=#zm*c*2<1mmAsWd?jRf?PIHKU$nzjYHYS07^cv*JC+FRs+43GKxB)T0yQE=8p@N
zE;E!sH6p>d$~NEkPS+7toB08U2qds75|cjw7ydub_QaG#gPjk|Q<<Z&<-JS@`#P30
z0Z6~(sPqC(Bu`m(W@l2C+Vz`eEF{$@X|0PSFH&fGLFw@$1FG6D-WrWU<V_~!OFBL7
z()$Q@8O1-R-gmo+w(;O)CI9cOklV=r59e(&zs_2>*MBg5g>KNsZRaTe7=bP-g+~FQ
zK+=s=IMNGD<qPg;NEGI*ervZ93E??+j7r9BT^|Tr4j<rtsBUl%55wbJnOZ6wSGY6O
zapub(hZ8WVDc>t&LlbB4@!*=ED_=fmEJn*v%4zbT^ZN3g^g;8p;jw|QL05mHK8p(F
z_+3&xNgrRCEilfRxb-?wl5$T?-;5dNL);e_s8FQh?Pe7U&pKY2#x_s=_m-Y%rz`M)
zZ-I@G(C+P{@-3WOB^X_YBYw(;)2Hh6en%t@nCCRc?LxIDiLLAaCf^X^sD)e^(VBhs
zpQB@O0a^&ZZBw9HRM9))bhVRIX}Qm*>IIza1hT^~$9_bSE9hk>4@7rDv2g~*Dk@5_
z>^&Tr&4v5@?^F7v!+So2JfKL$MPboea2l~CZ#)y27*O@%M>G`M8#5uv=kcW=Widu*
z07Zm@fJM>2ph9{72+UPR2{tSeWAFNV{b*zs@J`<GFm2>_x|D{eDN{WOq`AjCm>k3U
za3M!n><w?c02f#jy2!j8Llc!WmjJtOUMXF0pvC=_l(j&?LH{r2pABKxVfO{qCHj|!
zokhsi{-p+6n5x}x8c*jBCcyaV^`3$GaO>0maXmzs0+-;yHzm_x=CMzTi{7W=qp2a^
zg_Gq=vv{4_9tH|$C_wHLNog+4EKWYaE`5f3;LIm|Z{5Y!dJKm6GpI0ozcoD$&Yy>#
zT4aXT@qaAqz8Z}>T00ECC3`hQ91pCmB?5pmgnTzhJ}H5FP@6y-OFcLce_St&HEvn(
zW#T|{+Ep035_pa@?iW_9S#c5516>8Z5uB7D9q2@HT$8t3XTikwLY8ay`|2GMXw}F6
zz~Cf5Q#pT-MJzvOaw;N?7ed1qQ5dCEHyZ^^igBrA9lq+{CNMNa5$s&#T`?s?a$JE9
zVd^{3oH;IvInM7rcEf`9ZzNF)&9%73BAR|Pld~%|TiOnX7Y1LTEa(oK*uf2I5M2j>
zusx~BF!tR<i`eQ4i8191_MYUbu8S4sOUSnpQZd6oyrW6tT2(-=opvvw^mlG82vHub
zD4~1mc}vnRc@c~YZaVK1ZZWV&_0dg^eK6LR2^JYA+q4!;`zkzT<^(Ggfr1GOQ^MQU
zk%p=ul&%w!2I<p#uubz@M=WS~HveA_#bnaDBq?B%;;R{`NYrYBckb&OdwiBO-!9LT
zm6&|^E>eFaa7b2evueNcZk#6PgboT3R*AzPM@!P?q<Loa=-lb(&sr|EJDN2>E~inF
zB3%GRR=FmSdb?_kE~&YpXUFE2Q8?m$$7Q8d@pfHajCfUSl|KcftsY=&KG(&vebv-L
zq!@BGWO#C?uOWngj4RVV<Ni0eo^FhTGkl^L|C|i%gCcutE%RpRUdi?J<kAHkNofq)
z`(K1LfA=L83Uq6nHS3kb2?2WQ&)>Tzn$cbWL|ZJ2oe1^yP9!R$aHqgJS3|xVe4V^k
zfVWyZ`X;U)3SNg|>x!lWzwk?&tU7Aom6X2?#x$?eug?En;Gp4_^~XgmhdtWrB$-vv
z;)xP{WEucMQ+P;IquH{`7-bP^&sVMNY>rS?@EXS!Qf?wjYg<y>95W^mh8z9=gQ|Zz
z72Jc-xtgD(yL@4L`rh(amh87q`@12b{arT8J1yE4n$tf@KG|3%+_MlxGMRBKu3ViZ
z)2Y`W*nP;E-rgf3Uwoh$RvFypV`o3V_+c{E=0*P8LWQgNczQI(kci%ie1=>9;d3CL
zumluXQ5m=HeyjWHYgT)dDy`{V_!)fCxe$Yk38c;7N8b*?)XlgNzrGu~Akq&oygr73
zF@#niUizo{lw2^|qIbxfF2MGFDbHOTNyCKwwBDHMHd?43?W>OcZfa~3iC|1)q7Q&)
z;VNc|XiVxu5F+fu&I)x)p*UTYZ<1xVsq{5)!#)@(D}7@MlTOF8d70z673_oOD&HUB
zmjIN_gK#=EFx}mD>K%=%vl|q0vWCOxYv6JeD%uC@eL15HkLI|n7X2>?*D+Ho)AdM?
zFF9V~sn#<|=c@0$#0i#>!d=o|526^nJn1Z*q{hh^_Hq}__2AG=iPlW(Kis&FQ@Fzj
zOSGDZi!2<d%j^bLvkGSBCP%x0es-ctYiUXbo_~4op<sztg@?`nHicS)qE3m{QM%4u
z*;h<m93bV$g*kdHOsw*&#X>#z4h-OVWkw~cA430(hujWKN`r=tT+DxU#d@Lh1ODRJ
z4ZWb^YW5|p=Lsi#hG{>UDn3N7Ek^J86t4E7@U3Z8>RUFsHh#Orm3R++y6EK`ii!ne
z3}g-Law-n!mKU#eZ#3r8SL@Ft_58{1EwD2Va=?+2VfC$!Q!PGL@yk$$lBWt_zsQG9
z^<0M&Vh=x5Zi;?=wC9rjS$kzBPA@fcD=dV>#Xh@uIPI}2x`{=HIrtxvh)3rq*I5#v
ziBsi4PXPcT#zyy<$B^55q&+Q$shg>&f@Q4PC6!Gr$2RG*mL7<3*|2k&R~Z%gHu4U7
zGe@-`?a4|H^9=b2pRL6z`PY<xn^q(;$D+OY#4l*dE6mRxqN8fEVbxaQT^g7PN6bc3
zz=Pm@W=Ckt!P-1L&pbPrIo!H%h(~qg1?09g`(2eco*0PBkKQ8}^W~ZNZ7im}Je??&
zzzW7_Z_?u;!0NWqG8*<SU?MK+?qesTi>fxK$`yk9xci~^wXE`)_}x_sku4?%X-0j=
z1^PzZ57sV+I=6@Nz`!z9*$yv7fDUakX&3RdN|IM^<b>R1B<eGWrnKn@<LQ?*R=j|G
zDpXf~Ojs8^fqs8lN07H+Uh<G_g^FLO1@cu)MN`RxCzbkh7myXExHqfm!C6Vy4>xo6
z_PYsL2#$gPtO&wC0Bee2W7hpmKo@`i9Ec>7&VH`Pzz)Rnq&Or=kSneqh_O2<#a%4?
ze+RR??HWl8G|}s#&JY3r18GT=4Iu8TC@uroKHuCIsC=&RKU`;oYMiqzll9#K@xl<b
zm$lz^Y(o>hol#U#(zTs#v_f8C9k>OWn{q#LpoN1+fu}tj$JK{ks^O^~Kg1D%Y)gv@
z+g=6H8c1<Bg-TbL((uuB>!^LR>z)P_ze|NQEvWn5rYM{>o{TJ0rUhGy9P>QJ9Ss$5
zdNcHxjID`x?4^WJjNI-%Ir9QkiWL5eeae8K`5<c76os!pj3VNLFOd?Ut@G$~q;iEP
zMl#FLFVQq@3#4+!FDU1*72dVNh5g<05`s#~+VmslMP{L&yo%}IOBUu%Tz<l;gZ90s
zylKsaLljRZO>oI^7bXLH(uA%+kFQD%GmWp(;rE6yl<To8d$=m@rwZ~TLNT>AFcRSh
z80k7zM#FbUniB@wBS2xqROJ{8AEoSqPQ^R9UiEWLURy0NU6&PLgSnTeC<?H*#MDPC
z$=fQi1y%x(Aq*copp;^ocJeKpT$OcUIYLnjNo^uwsDpB@#*zkCn?1Sj(!fd<))}p!
zCsv)wh=B*QfL?8-kJ%mE8oJd=_xevRm4^hZR#5m3qihA}wdFrxiL1W>X*8dbR_@|4
z9BY1C`Yy#_CBx})Q~<H!I{LBxVr4fRdXvs|UK98`oSFy%vme=;xGcX;^J=5y^d307
zA53skyC1Q9h}Oo6Pk!CmlWZ-4e7H|2$wg(KkkmD@mY~Q#*z#&**4yNz))0(CkF@-5
zOo2fM#bS(sg_!pH+;YP@>IuZlzx?a1r#MqBm1CzAjAoS+;fS#Jg~;34ZYrCW8j%(q
zup$B^O4}o`e{JE&OQQb*KBOFf_HR{!o)8gfsI?m;FDpON=t2`~wHS!Qp}sTCY!q0w
zZ8OKnCE-gL3C(Yf->#LDA$$89Ux>0^G>?<2H??f&g8H3Bl`N-Q9QwUma19kWO8M_+
zEP#sFH&1g$nmn5?ebU5IpvSD@`CbYe7B!df|MH4s22L#(En)CY<@O*O%DH^~>xZ=8
zH8BZPTpfQV6}s?G{?Hq1`EAxnPh}2h5QOy?r9GSnX_|+3qzfs98+!zb^K~$y-!-m8
z;JZH*q55#*^E0MrnguQ7p24I%v6lQq5!0u(bQ<0WyrmAgGO^eOB-H<fF<NxoGl3ny
z;YtgJh-$#u6I{bGpYi|jnY>DAZih>mX#$n$UPD7evN*7=1PcHx+XoZcG?>Pg*P67Y
ztVFYT5Al-rcn#pd1S`-&n6K|iyBKH+S-3*BG`G#xya<6yfGWtez5a#jV2ff)yH-lJ
z!9GWyJl70Fu4Y8Q+-2aV0zmFX{HAGF1hL5VJio<mv`9M1_u|ZWxS|(pu9p%c`!rG#
z^rv&8!)7{=5)d_}Ql7`r*^w=PNDLT}sv=08wPT-PmFIt-#c<Uf+{nL!G$USADT^&1
zMnBS4b?rco6oS_rS?_maV!TG>{gBx!uh`^Z*yr{VwIs(&>f}~h{}+M{dY0=<Pm!d(
zrRuot&#J8t<d9t)U!iKqCZf__o<N%<q&VYHG~eg|Myt~1FQi-s=^Fm>F0uf3@m^;X
zQs+d&PZ_72HYCwWur=jqDleZ<2%@-qG^BoU>#CzLXGsV~^=H#4d3=CUcc3J23ry<9
zp4b;kS`FB82ta{FA>;$LQ5v&Dar>-3_X0a-zaIEiA$1zyfrSgEO=Ta(E)-|T|6*W`
zn{x#f^S>)Ob@`)H2wj<6{|u+H(TJpzdpk@Lp%STH$PYJ@xc28tTw)#M{mY?_;MqI(
zM>yJpV^gJbBY3A@C*G9seONvI`g*$i7sopkEQz26@M?rk5VpxW)oX1td^6;N;r8aU
zl;>GSdp^87rRJ877hv;k&<JMyGS^9JUlh3rS_P+rD7`+8eh8bqH(z4NuC5&PqxOV^
z7qMe0DrcMB3PHboOhz>KIhM-ZAVqINRr~NlpoRRU++JJ1c2%KR(up+{4u^%5bC%JR
zP%@mD^u(!Z#=OSy1KU8erMy64_OSFj3s=uRQO9{#-tM-2HiNtd`|lx%s!dW!V$bbw
zczUz4;}v}gg%Ob?<*O!_a3Yi-Ik%FO0aynr3HB?G4m#%+nVnAYhIqa`uu#FuEwn;A
zd##BR==B+HvbojdXLr5aVm<S>wQ(V2t0f9JFUW2@g4~$a80h$VC8>mk-2goiy;z2)
z*{uzEaca!_deM<CZLf}U31FYEn+r|x-Ayp;`()wsKjU8kN2Wt8NdxRKdiVxP;VEcv
z<zY{xdAD)zV_l98kcw2VhhH04QrH|_@=QdH7~VgQh@l>X9DhPHZY~6QvD@<j9H1(>
zF-tbZ0+~}_RE@*u&*`ZZLmw}}FAkT)=TgU=b8bEaZH<_u*9a$O2q@gJs8|o&o;yR8
ztXx*tN*j_*#ZWsC<X3LxOqlWEVW*3wdvxUc&9VP~34*HDI#Rho3I2x>b%~LDQ;<MP
zg0`!=WF8sY5Iqx<$J8<KjktMQSrPOp>zEXyAmmrOuy$lJTgK02j++->-@td_<<|jP
zk#P6w!phMl^pxYs3$x(n#Sz<CN-XWR&s}X>K(%gvz&0qAOjWSORTMmeQVyd#DekE5
z+%N1NWeaXAYv-F5Q8qoSU5wO<(2v#!%RQhrv=ioZuVa6%@Yxis+KW+u(AaN)Dkn?d
z9lsjbxYM?e;g%u3VnHZ|2<1pTb0IsdpY-bV|0&b>itk}~=(A)=Dz*jA#l-Ic;-zz3
z4w~9>ky9xSim`(4r5H3kHcoRaXqE@nA7*+vEN2Yi%mpwDmDFk<f)EyGU;lH&#-R;O
zNJ|Oiol|6?GUjh`smyc_#RE0<Eo&~<hkL8&_lNnWCtm>p&?Zcui7FxLBM@AF=I2d7
z3~+YfWl2akvI{F8AB>ge3(|`pXHcfe#-Dl+ghM;do?k`@app$Rt&gK(xkTJJ-|M(1
zDiGw_l~0?AwtQN%Z+JHV#fx#GTkH}qsy9>jq34)=9IKM8E}w1p=!@`eE*<?&_LTqk
zKjNuCd@RLAz<=~#A?6)_D>`CIqiz6@U;FVyKT!Rzz&bWtw^MBMRac%ZEAOl^bk;aG
zZSt=B)9NZ+WobB0vZ3@4d}0rWzyyRuN?qR7WQGE_eqSopgl$S`gWeVk8~DAB1H*DG
znh)TfUc6a;+xM=MGnkww!6#E-iX?2jdKe7qHFIJBxP>4utDF8^$KXWA9dGc!w?zoB
zo>f`Wsgn<hXc^(C;$?-8S^D2M{s$|ArZr-J;SX&S0bfnRv61|bkKrVO*ngGSJ|>M(
z`D=ItS!SOa<6d%zbm76wOub_mr0Ir3#~##bQTUYoi^wyRQp11B^e{HJ#(lvBk;YDX
ztFE5p33EEln1NGNv!Ao$UU5>Q{l)xlA=EGnxF=d=R*4yDTVG)<0_VOEbmZE4&ZE~L
z`ddfkF{m?H-Elm+S^}&6fb`TgY|_v#C{Km0%^Lmb3)iXa;(-^<$+g7>t_2UX{N~N?
zP0?cAVH0o7AiMxp2hjv3Ai+BVgXEKI2_+sw&R;~V0QfOaOQ3kbw3WB?#U`Mb6drNY
z`FNVJt0AE+M;FGvgT%s>P4z;J-I<ewJk0<nK-j-Ec4LWIF#}6|5)>a0o3FH!ftG|R
zuP=odv9iCD#0>dT<Ts(Oeq?hxEOAjEoy3;^18#WlX=D18<E`+KsV=n}$=9XEA4e(L
z1UZ3T*wDR*uttv*v8f{;K$Vv)x&oVEwAm)!Pt{>la(Jn4W@2(ZJ-2+PuPFQ1q<y3`
zTuyk69(tX)$o>bf%E+Qa%Vn?zea(sY(?-f|ZFCqv1X(-4zLi+q;Tlu>)LxsbFNgt=
z-zfRMVtN}H+8kCj>*}tCnidpFyfErT#lgdj4ZT17{Yc8LVA%ywGuqs$T+`^s>L;NU
zZNUJZh2(3^m~`hYWyWn`({(sdFnlbaON!l7#a613A2xyJL5*9VA{mR~dB09vFc-M)
zu8+@Wm*cUeDtxbC0vKN20kx2aPkMrr^ogl7BI!uWycKgD(w-(TQT@!buD*}A)g-pd
zxJOQSu^hbg2Pc3(z|B=b{W&nexy4tMgzN*h3N`<gsx6ljorWN;b3eLT?;-|a4oM=V
z8In9Y<3H^DQ~0pPF#JNeJRoA-ODQtbCfEYmJUa%o!fD=vQPhJ$dkRu8LxOk^!`r)0
z-FOT`LL+)_ss_cMi;NadEP~vi1UASv)}Y!}lfdD1T&S73p^r+`CEO8Pl*zn2$K&d+
zt(-SO^_OeMd^}y3hyf_A=K>XnB6`j5LaM_z<>P=1f)10P3L>fCjlDSrkAK%W3LR6x
z$C|0aVICJz%$h`hWd71PkUi%-yN~%48Uh%<h?HVE)`C<A7lG0BU(}w2p+9cPdRa=^
zS@e^nPg0izx_qH$|HNzINxP}2cy7O2jE>9nGHPcva5|--${7s&&K0PepUkeL8uaTn
zox%Na>UoYgwR=rl*>5&Q4ewnDi!dm0L9ocI8}M^Xpz;gp^c0E!ipA<xGHM`tSlm;}
zz#^7%+w?i^jKav#yvE(wo*j4&TA;0=+s2J(mws@womQ;z=OLsGc+|(P_f?cBE)DEO
zj13)aBWiiGn#wfT)$(=$!8MFy0aST%;n7Z&xMJPmg|xpQSv@>#G&@vb<REaa=_U>;
zK=t!t-c{w9Kj#rnw|42b*rika3;gt8fU9;#1BR?xHp7RVQTqMXWU)l^<*UQQyeU&C
zUmg{Da2_5VN)vN&C{h&GwwSJoijo)Ah3hR{tq8h-EY}E#t*ZudrrQH5A7V%K{EPq)
z9Ae>%LBK(DaI9SdMx?lwWl(^Bux4~XvV<FBkGKFs#C#8oS+yr#_#E}vJ)9kXGPYU0
zDHpg}BFrrd`qo<fsNS8J>9!`7v=|9@=M!T+p%VcRjfNm}vf=9Hwez*%dZzA3#REq_
zdENAC38HRh{K}ZE&IO;#X(>2l)M!VcK9tc;a($O5w14Cz36cav?8W_tmY|Kq?zRT=
zmr{E^tn(zHAdRiqKVRz6pdK=`8i&qWj>(=B&P?9MH)CQ^m;4hn@Awv@>^;yA;Xw0l
z?YJTQOi&wh^ln?PL5ZuhNon=?r7J_L2q$>T8EvlM^%A34uzv=cu68`aZZq8?+IvMv
zv2pVL-QaQGtRA6@8aI{Oj0mI{QGVVgWu*8K)>k!TzxeZs{A_`CM89Jm;Xxh8`iTay
zlDLH>AsUg3Yi3uQ6GL*~pk!q9Z*8be%n0-KPqCLjL}2~o9@|Whv@o=O`!E;JXCM@Y
z&=#$CD^b%S6E?SHp%3g(ZC@6h%xnnq#HjoBIVA#!YGe5<0!twum-67)vYwe_4b8G;
zz@ak*_TK5RJwuqi#mP+W{hJDY=gIU6CsMt*kghMoj7XTl1s&Bg-ZA}*MFpX$eZsIF
z@T)ZX<%q*(&Zpl^*aG3A&HEwxVRla`i4}$Cd1|*%Es?{-e?0XJc@zXax~3gu<>e<d
z{jKw%Rfi<55M7Gu!*s{dSP<Ac7+Gkx_TlMd(!Go~C9cPD?*0O09rnWq|M@Lz!y$<a
zG^odTDlYZ#|E*OV;kV8rQBSB2_oV}TWyIH0QKm{{m&8_3xi7+ltAT9$)V2%kI)oN8
z^)~Q99opMY5Bv6>-<|GO#^?2>ZIbDZxfm2lp<M8FcR}x|S>ot!oNoye6@X{A$vHaf
z+V73pq)T##S+ThN6R>D`AirHfhBXCCWIaxX+4M#U9p5!P;VbLkJ0O=@I*r$gCxN-V
zKfLSEOp2SjlsrKC8H0sp9+T$({ncCT8wt?v8*IP}lq%2TQXWVoh!zsY$y#ga$hIsd
z$qM)Z=}DIuEGz1SP?OakDHwN)*)K=OFLbQWKC_nY87S#_g1Hp<)~V)s(nFfS3{D!h
zyKbiE5{`A=Ba#RK_zUz=Fg7pOzkz+CwXq4gB4+mj-07AWq15zTorPf`aOYY8X2}|u
z$T|23FbiGPu>=pAJ=e`_M8IXQNwrJKakp;XqK24sN3vgs-*5L?+lL6fV7@l2iM~0W
znSg+d7?g)BQ2oF5NKc&B#gR!I;I|RYsKr{@PAD=vbuQlHahWZ3nNUg#&#laaZgX<l
zt_(}Glp>Imt`o4Wn|i^o>Y96{lmQi2EMi|t(N@sDN`tikb``Rn!%?vLB;2hO;Sss>
zb?!hy83<x=?>xt?0kOgKiPsxk&vTkdNKqVC@FN|l6fn{32}8=JqAq)pFO+plb?oE-
zbin#LkeR;kWi~0W3VIT?HWYU}jd9BQ2x<!qn^6T%TFTvqfF=SqTqMh-69wX$-``pt
zHg+o`60l58hVP;lT!_HY$Y@X%WiwwB+L=P`>GEzl0rI1EWZ0^<AQA7zb4>L}W*CxJ
z3P_;D1$ga*0*z1iurX*I^zkELr96(Rs1M>;w9C$hMlRe9{(lH-M<l$a%MM6R_)>oS
z@){KYlwwU^Yoslx8(U5Kwv>@JPwzK|_bvWXB}UA+9-j(#(ANP<&abgd^Am|luEm?t
zifM)S=+?&9KItp^6v3CnW0aC7br=9H+RIMptb^ut;o#&sQ7kCf8&aq~l?RuEvT*U^
zQ<+uJP=|r;t|3|EY65h<VY&SvH5OM1i{Njtg_6;`)9{woiN<tuoJ(*W-;{JVOefK3
zC4oK_#UIv6?AM*E-7NZ==buV?_nEYemE%9JM&w+2T)-!^BwaTPIMeb*jdeH_b4mvW
zPwPsIN6nRJ!G7&X_okpyLGYL%Zact>`J}(5tQsa<E#R`rvVLNx|3?T&XW1}YNV>;>
z8w}uCtfZW;Z4(K`OsE)1i<G-6+U_$Cj?xpW-g38q27q`7mh~}uwNbEv4axvXJWFqI
zb*YEnU;w}<_PF##-#(KWT5Rwa9G*(r_@HPcih{AnY#_p<I0%Zmy80qShCG`qZC0T$
zSLc;e5;8s0#xr0gkbyhgU|<>GnGRz_a*`AKLx?)wRf9$T0vJ~}8w#PX!f;QwZ@L;g
zhPSbmkR1cTlg8y|?5)4EKwS8NoyM>bkaF4!5CJ#v@k+-bmKTT5dF+kmWAk$}o#`}^
zI@gfACWioI{Y9gg93;Y`L(tn{UkEhgrE;Ua-f2dt+ZromVeE2V2j|M<t83-VFYyQW
zp1kAZBtZkD^hS>UwoX{8qCOjrfd-NJUdsT}k1ya<WN>(pr~1C;7}9LT#5%JL@`Pmq
zvTf4lTic&qh^Lf%nFb=rFj*nVoZgwamTjtA4Sn>lvsz15(V*uOK&VyWcOl-}Arp3W
zcNJV9nR`klRZKvo_fa7V>VLdGyw5D^znH5X&^+-6K=@dG)C>#K6}(l~=)tz1$2=Ax
zc1Q**qV2fV==*V^)b_!x*IIGQQR#|SVOgiY0uP*PZ#Woq6-e;)reWepShl^Dml8R2
zpE{#&VPbnQ)3+$S*Ji7-%dd-t5C>#~`>#Fk*&FQNMTee&*c>3xIt+xCFEI3wDE`v9
zl(9|j;Wl$xM4Qs>xj^Tdmmqh)!1z@p^hNZn@@ICEDaz>&(vCMTRPfevBcv%&1Ir%a
z8{wYFfU-|;5mK;y@k!EAAz8Ui3EVJ<i9h;*2@r71+*16p93hi;lkKHGhD(DAREM}$
zs13@Q^b0~!hCi^{=I6r=m15QUY2Dy7Ty<5}wbV(l=1Yse);~-#HL~y(Y=FrDw#=I(
zH>nO`$13ec>F0jc+EKdi97;&&kYvm$>C5r8rrkmdIQQyjD6DBAzhYpSWwGlS^oXFe
zo+{GY=TIwku{JF_ew~e>S7BKpXs5;4O!4f`>m2(tTTl^^d$PG#q(PZahAI&JcdM&Y
z+uZU2!pv)OUw-@tD8JSK0%^<a5I`g9WW#8}Xei?ilJ^?Gjo+DxGRr1vmS5qim+q{X
z{Lr@ZxTLVqtJN#i^pr*5k;~s}IXKIhpHpq!Yxb(dLrT(#T}FY|WiVzP*4!ThPAuJi
zl>aE<N8$q13Ue9)W_lwly9J{&AZ3vue_znzWSDG#sdVup9GCQKvuIN5kV%W29kNgD
zX1B7A%mgQPdh|)x=|_C!w)dIqz8|z|4>nIY&LX2`edt7(HXLd+prYO|Ef-O_rfO5M
zlAU<AT-SD9w?XzH>2Rahw=%pe?_?Guy}CE5o&Mgji&$?;?TMd%6+9iY@u8^U9|9FU
zIw@5(A@L6BiNL;?AFJCx^08?pHffKLZ6N!bRso%{Y6CBcw9+U97TZ-k!6AeHeN$2`
zEPp7ne8{Xi=`ePif2Qx?N$-OKc=VpDp(`(I%_wH&He^q0(8+8JC+H!7!Y|M#Ixuel
z6mzv(IJs?M@I!#B*@Ii5Imj(Eq-rYlpQzfV{kS&M1a6e&J5FRV)8i2WcZw@`xcRp)
zrMS%7%u@RL63e^sZ^5)mpR~FnHQkUXniD{NnMyT-Igy%A-&S7LMB*QZ_LeZGmr(s2
zm)~%)iu1Oa^)(7jlQm?Wc;09#o^Spj+g1%cX4L^E&0$7pM_Lslvrfj_Mc}YCxEmzu
zl?MUk1BEoClPI>l`v_gZ&tzjD^Ao0=@vxBI4}k79AMmDxL3G0{jU%zd5_!;L6NLwT
zb*>(${TuWY*irr)lxC4~q9;Q~iO<S+1vXAMSW*<MFxFspf6O!?jsb2Dx?bDb{AYnZ
zSUDzV8fV_eAFOQ(^Xd!B=Vd9QY`wMV-B2-IthXCk7@t-*alVCe)8C4?7(5)r9Kg+Q
zf(Oi-bF-gDbJkep`=WFuA8z<n=J7B~e*Z~a!x57X`j3oSW6%LjS=sPQ@^!p#7G)Kp
zfM6j^KmV4^lnzB!V(dl;YdU9$d~@@`1IOO)K^8pLW;9od=KuzvH&7fz38}?)xVvz}
zK$!)|#7>qLsp|%Me$&|vupjnb*b@jRNKL?%cc!<*Y`3T|C)H`kerZi(=)N9!s*~{$
z`aB}jmjbSv6f87{<*InIe_>bYO3`F3!4_ylZA#n9EiHx!(xomfeoH%aXJit9ehh24
z#?%+WtEqW38TqAjc7wmntvUfwHL&ea#uf6r^Mf1WR;49nxbR)`i2r~rO~EZ;&|;i<
z^5{q<P2ghuC83BWy}&zdmCOmCtoso5A*;Dy)dINI??SANfk3-CCOh}80%5XLEbW3?
zM#?IoWD{J!?GLhbf=!4+WDbu-|KF{-&hNYx_@S90_``5xatD<z$)e}(&J#;cD)353
z_KC&PqpX?&y?oj{>P(WM;*i*}+)V7CN->(Gi20Epz3^fBGy2WUKX0U-J;t<B+;g11
zu;NkEJDWi_=!iRr-cx_pN&{e2t~m3{p7ROb>^jIqYb^v2zf*!6JQw6dg{nB4Zl`Jl
zfUA!v*VkwBk4dYKQN3NRse@{p+4+ES@_k~T3SH>CPVK28Ae~I?@Il-AESple^jL$u
z91D`s@-g>>j*W~q3p%ty)}BgHUjAY~dBt@#H-G)70JZuDm%TC>CT|g%M1QWco@r{^
zBofJ=Gmtp)7`&AM-y~Wg)+2pORm@#5o%mYC4sv#Kks|t^7g@yf5nOf?)GV{eE4r_+
z5!UtdAcMQM=IMh-799EL;)1+$uRjpEEbwS;Fhnv(_#%xbSF}@Ct$*zS{l2|r)PEhe
z3)Tw<N%U;dDm=OiS;g8Cc3C$YurneH#o>{AFl3*YcJ44UL0w`$X1#F!3jQRkitbOP
zn?y8ABqJ92;}WASr3CvkBwe(jxmHdIX6DC>6`oWfM&nYK(lHL$1GJf)J1-SHdf^Th
zzOkeG9ZTVzj<h!~K;u6o5TtgTEPz8R{hIV;s_U>o+Db*lXdDeF08ghY_3U)90TC+0
z^?g19mI{B6;bX)C&{7j%l%!5z(9Kzq>aY)Yu}RXD@9Ex`c%^J0Q_CtNv&=e<!&j3x
z{v=jl(yR?)f8~aeR_BaB3hmTdrZua+&)i{PW4+X%K@!oh&2v?#NzlbJ_4)d0MpB`=
zL_ZKxpeBHXE~)Bs$n2oc&cI@lvd`+;f{b5J_|p6@SRMl3Oc?do$%^_#1+OjQq;3X;
zXu;q@(IusbFK7$s(L7$8Y8G;!rBZ3I$y{!;0B_FecPz2DCp6MvkmM$}_mtO|wpLcb
zvfmt~GGv57?UDc%)f#<^F?7Dpz>9b7-xOQ@>{|~rF`B`do0kx3isk>LlUu04YhOy2
zPPU5fa?p6Y-CD>rF+V#zgh_m0;n5$7DB%#{vYEc`qOvPhT0WAeT9c3h4zG)w*;q?j
zW<v}*0J|WmT>`Z?QX~M#6wQ8Wtcmy);yhy2m!^(pO(Ri}@RxTEsQsA`x5toXjI(F1
z8ooRBSrgz4X6CR>o;&_b0sTgda8hBLrg{=;x0)apR;n^r2o-u`<e-`osNCd?JB<kt
zT?>yP?{3_?Ab1WFp%9Y@B@6gRyQ}_y4RKjRN+u~bape{EIu7diiGGsE)qz6f4+BFm
zV$1%8cK2yg<XMWJ8B4Ag$_`8RbiSf`X76K==U2q*iW;Cx^4RL?Sl>jq4Wbm_H(p#l
zdQOuCThpyZsweIpueo;V&WRMxO|Ba5XY9xmZiNNgWj}`_oc%U|L9ORs%W3|<U0QB0
z2*qNvjERr*0!tsir_M%nsubm{ik{K@5t}A`Jh8(;=8T2n;IjJy_XRO|wdZPDV&`y3
z(}F|46IHh~#9GYQV<|VLxm7tQx(%Int5}PY@0)EreN@stdQ}XCO4PU=Xc?HWIH+&6
z%ld%o)Mt}ia-NZa>2L#vB?L#T9h0aX%V}=i`5&qx{)34cg$9Z>Ayz>8AcyPwte{|>
z{@8Ryozg=Om0ZV*JvclTpc`Ljiw=xJ*~AI@nG(kY-SWGRduO{4@+DX|>0Waq^v7$P
zi3Cia``&&t%_w6)^a~BserUF(bgJeW0H%NP*pQUCj90!hoTHyZ%ycm=$t?X|lw}A2
z6X=E(GwotkVwaZWKs?^R@q&%gz!<+I#}Q5`kWpRnK@BX+f2Y!CM^*Hj%Zqc-tE}nM
z$u}nc(1$!u@bWOUG&Nao9Ro_h=7hzT0&;xa>+~`znE8{^FP0Yg9i;9&1@IY#_GOsh
zheqao+&jr@JX{iZe|mUJ#SacpggC1j6_Rw9$-xP&QV9_w*NUf!5TEVeRGB>bub{9x
zusdl~B&yEd-L8NLKy?mx5n%ym*^J^54G*TN9ADK*z1XaIRoUrd>^C%cxkzT?&jXg!
zBA)mczw=b(#iS{oeo?{M7KD?T?fnl_0=0G8hN(bE4=SwWxM^@(9f;H8eaZ-?z`G=h
zt%XI#%D(z|tG@wnsG;<Ndo4OE>C21y>0eC}Q3;m2al(TH8!#5$^M9{=J`R7Jch=T2
zFzDp^QN~)mjpjv$c;29f#H>!&?vZ{&d8^v8^60!b+y6b`;wr34AT%EE$ydnwlSP#I
zO8^OC=e0Jh3?V_C@M}9>#b(~SsT^p~+uatRfq8isfEN8Y4b)BJL-cBIl)X*?i?T0p
z8wXF#l|YD)y4t$4M#q9vB4N^nF&!`px0TFUR#?Kpx>u{B_gac&js*GH;jU&HGLQ~)
zF8b1^9epgpCaknEz8@;;6dB2wSTa8+C0b%^3L^MD%heB@?}EtU?$2X0r<MLM?Z&<N
z80qJDBmsAic7#b(aSJ<P>=d2L9{l>!13h-QWhTa)%kZwxJ~dQC^F25Qjq)h+jkS76
z_7j83Ag0AUB%{}pJzkSGJj4B0|7rHj3=j=``{4Q^SM2-cfsd9Yh^1jLLmS?rY|ZDJ
zP2+Xhgx7yt-z_?zhuW(>3&39DUiLV8PEl2%X_vn+<_5GRuM3y}0-iArE5p5P84fIe
zJEf1EdnD2?oi&$tUXocym^MmRdnz@D!e}49KSo399l#YNKEOp-RUNR`u_efUJO(5p
z@7xeWj48NV2^qkuKK^7J@;T=qw$8p8@18OA2R{r82!Ev}9^G>Ugy7j>t^DwR%)$9|
zKmguE(T0OA^*jLBWzO)TZ_VO6*OSm<4HsrQ!9<GUvBT<t%73grj<w!wEZ$jvaXxvJ
z<M^L{3e@qQ+j6@po6j;LAw8tZU)&j9fUuH{xIo*YOQ6+#At)e$zkhT|68&sGcwH^q
z{_5pUl`JwxB_^(snS(PMfLe#UBa!k-p)ySE<4^8)?l8rpq8>ON(l;i=X-#R7gv@UW
zp-Da><l&_5n0ZDCb$<KA=apTtP8T@Z*l!%)(t>^nAY94IfVW8uv5sY%_38JT$o`4z
z<b7Fv%j=LOc41fvd#ui6kf#JIF%=w5K=%ldjRF3f|B?*R#4Jx&$+U=ls)KXr8hTNj
zKwx!;!2n%{Z%(kD31#1r0hS5d0PY7|F_*XC_6}S=+b1fS)$xu4`4~e&Vt<oe`~pBh
zylsw{CVNMxfkoKdb^RH<P7!6-AsP+VVKTu$R>5>dKl>;7Wu=YOr!Bb>vW4qlnIiiX
zRi}zDaT3%t5j6~st{CN>Y2_cLqY}w5J8RIyS^^zF_G{7R@y)IeDDg^|hN}-caq=PO
zmxiJmD*lxv`wfDjY|wQGHY$~jI{wt%9~Ztr7`qIqn$I<8B?EN>e&;5<357}NyT6>$
z_0Q?Z%T9s9Ajt=b0xveZgM3RUkz|9h!}DK>S6A7~IpYV28fg<kIUp?X9*N4Wkoc9-
znb9X-Sf5lcZmYU5aH79?V(}8Sv6{G>Amc2l?xBX%z#{PMspX4dh}AA{iw#n3v@3ah
zhC>Hi{KF@o(L=FkLFcwi0q`o}WqdfkssSD9tJ|=ucMXHOr**->&65t{b4A;r$kLo=
zt%D)UNaZCWvGYnXpO<7-tYRb8IaLdjIGmv%Ug03MkT}-qd9S^$c*H1yk4O=FqR~3t
z^Cn(Jh8D~<cI^o5l3A!HCW}|z&mt1tFbYp`4IX!5z|t8jB2finH<JhZn?Tp4!(<{V
zJO<i2qRvRNOyVV6OaYgo0Z>`w4AOD<7argwmWZkB8n?66AE2gf+B{HFH9Hh}%oOG2
zJK*sEEqSOb90BM9R3_g{DktD?4~CA6H?cYw;Y6pCO;*ugCHxmq7CpCQ$0fiM7I=xS
z@W_doQzQA3ylCa{@B2T9he*RMidjv4UffNA0$X2drI%avOUtUxZa%loj$qAU*Q6Z%
zjjYo0T7_obJ?N8*WfMyKR%MmD0DM@_isCc2;Gi>UMYu<GxXWX>Js&f~jAx0H?#maN
zF?ug7>}7S$ZY+a9%*1Kbr2E50?#foWLL9}K0iIV!D0=%c@@*muo!_z{AcS>YaK6V<
zO8a41M{nw=X7r+(TgVV#QIXuYb95Z0*G0_+T~#wD7N%m@`e7)x81toSW2Io3Ql|{|
zG{GhS5Y0ib?(3UF3cGAk;=DGIl3{{gwh;RP3cXk26@r0-mSfo+<ziKCD_dR#hxljU
z*lWW0eN@%Re;;Y;Q_&W7-li<gnRgpR33Yt5nu#7xX~&YDG^#Q$WU>%;p=?(_i)X17
zMVKloSGSbWjPmd`8Elt?Zff1Xj{8Kvuj@z}#%EAvIr!r@C?L_fNGlN++ELa+@8zNX
z-G{N;=t$}b9}_*bOE=$L_uDA-a2<UJ5|DEW2$tquBI{qIZJ3E6CRsVsE1OQ2t?2->
zHt`CSN&{ZEOyQ|iaA=RPtTTD6Y%j#7e0Dor^%ZX&%k+-^D>?w`v)m1LU|1pL7hp+Y
z7thVcIVKJlM$aqE3`~){UPYk#&Uyx1Fe#D+VoD^F5Gh(Xg_6ZqLn+~$!Ip}dWdSQv
zXxFtW&RJA~=g)ZC8$Fi#!jNIHTNH&^9;zL3G(9&9J$^_vW;Oxaxv1fBU^y5B3X#s(
zZeGZg;TsFE=NueR6fL2F+{iR2wDp&xman$hl{L7S(Gu3z3_*#IFY4}8r!xpIY#WQ?
zEs;)5*JdqwQbR7Mk2s*;1z81VvYp;D$_=?G%uf|L2@;@1cAL8)WRYkVw&!2Uzm;SP
zhj{P28oLv@(C%EHP$s@8>5FoL`UIyz_f|FWcL3$Hh-*2$?(><lpAVt4*eTZ?!7gWu
zmmz#)8VmzEm^Dz96ZM`9^<mVY)&@1y4|pgQ?n2P&zd&yAZ-uVtp5>NFrQjxh@mOP)
zH3W)#4snd-31DZ7^=h!my9p{L(#tRiyWTlg)d$%H_8I!=y>eGQD1ZVes7^R(3N}8f
zrnZdhR0hjdtLs`f_xTOlNAo%B=S15oT+j`F%9U|}<+lW-1?8n*;Z;L+g6K;%5`1vP
z>bharAxKd9l$lqgr)}VqmR=Q&rlb;3jM;=;K%lF4+DYSmYdj@o4kE+%gCo*JhV+*?
zzIpLx$=$YlQKWCSN#W<=lyw&Us|>RU5+XTEE}B3zQW&m=0pAK}|4O`EJFq5ZMk}3b
zFgd+ya$C$-z?LJKe-f#OfnP25p0P32G8m&cTopgLxk~RB398<<*?F>R)3h(ofegUz
zd9o_~G*nmPeh<Tdr(g0^^Q|F0LFnV+dN!rx!+Qjn((?L(BCVGx1hhMs52>WI8xbJD
z1XQ3T;ut?(%^8Og|1Cr+C?TZ{=>kV%18wSORvHglr3_Va!wjd)8~UjL9BdD!D+X&k
zsRq?>DMyKUO7Yk+Q$JC?Vh8fGgd{K5bkLJf-tMaqK*C=!&Mvq(O%4(@0TN>PYA832
zJ!+?d2+o}r+u%(D?5ier#}yXNIW3VAFq$EC8=C1eX6|s{My{##c3Jd0bVCp}|FOp9
z&Nc*|VO<6GAlH@UnQzg#5U;$W_k5Z+JiT^*IyLy}m0kI$u({d*JqF+a-K;fAD?u%2
z)+<wbtE%UGvu}PkvkR>GC@_-G-R#-SfnwV--7|!?waW4ZvqUH#nb}BvXTTGg*8s^d
z;}AEJR0Ehqr7t0N_eQ?5wq1Bu^>s>&HB3G2AW0N3`WF|&v#^e(Hf=cyEFM&Rm9l%5
zn);Gr`}`Apsd_TQ_zs~~!J=KB6FAzrq2SqHdN)J9U7j#7ZpWUUG?|k(T~eF-U+TN?
zk+=Kh-x@k>qJ0V}Q5P*L-e39ijI7HdD(hiI2mI>jx^7yY^bOQU+zO^X(mJL_QH1yt
zN>L3U90}Yn-eFmsrdOJ*$o0|ENO#5F3qN0{s;u#Y%M!vpr@;lNuu}mTeMlpSV(rvG
z1uA(LEgj1*s1ifB;i}D-39lAcxDlLAZkLRmvoNwT`fV^Fc@f}Mo@jY#m>U47QJ&_*
zID=(iKi73syv>Rr*%1(=s(MQ0D6)yb4ry6LiTYGJ@QA-D{X-h%nhY6Z$<OsZH~_CH
zef>}>?UfW+5ekpD>sVTsM$OY6E;-$KmY*TD$in~4!8X#t326B#_Y8^;E?ZyY;wGvC
z&e*>?h=$<$9}%x{lj7q8wnQAd>aAB5pJgl|&gXXfhIU<eMDD`1gwd5?mKr(onW4&&
z%+Qcgj$ERyqczN6ojuNwf^O1P2$K$T><&(UFcvk8jJ-_8#6G9E<DX)*8;~F}^mh!b
z&&>Ud7^+;#9WpUy_FGFWWD|Qnz`@sq>=Vf$5-?W<UnK3erZ+Z((HVM+h7T<xW@hwo
z8f<G+Y$(a3yfsFaQr~ub>^gOXaOdZ$QTiCUSICdqQxt|c$&B5~7yIlCJ71lCgxucu
z9(u(m5KcgaS`Tz;e}&lB8qfgpLpMUqJnOuw>pZ`!!=j%O@zrP#%wnJ!h{hMGHRV)i
zTgsl!26p%VTMrw9&r=2b_hUKVr!e?hS!)nhh-5_<gwgu9r_1p_g9@X?71U%pdX3C0
zp}ZJBe{EtI5o!=y|I@xgCGaxtQkL4G`VN?bV~6+Z02Fcr4<{hXzqbK<1o|BXKNy*V
z=gxtzCE=q#a|J5|R4ro^L?mb^Z;<;JB@K}5kM-Cxd|B3cQ6K?a+noS~RO#|I%Z;Dj
zu?ORjSVDCp3ptVoj+H4t93_idmyiQRJ1GsC+_Qnq$fZY!DRb_Px+?u3QI)4L1pf55
zEO>Qe`lMpfE$SBUA>9SbX!uEcF-~x=ZQdM<=dgcLoW&~fBYZj9YBB?Q=Bbqc!GPRn
ztk)<}tRbN_iXD`1Kx6E~ej{OkP_LUK8~@Fg4mhve-Wm&twlUfmEx``>fd)M7s$haY
zEmfx%r*I5ZEN+9kg@l&A=ly?kKQX=VMXN9V-kj_An-{?DZAd4SAG0||17|>eCQIXS
z9i@#TUhIq4>8==aqbMLFeUEg(c#pnBDvp_I+sy?e?|<4CmnW(YeIb((o{%7892Ye>
zSKp~7AQKjFBO}Z`t16@iF^VKG#l>|<&A5DglId+_Y=?6m9&}>`6DPtPlIcF>OS76%
z?M*h;tc@-iEjqzK4joGg_GTUdrnmpWakVbo)Uajy5EUnGf$z=A0&c&?JWS1~;#2_V
z5uOKOO~$Y)$<*FRDDq_7_6DgY#pJa@tT|<csrcA7x+JBdh&5q5lj-AQWwn)yOR^u-
zyj<mYqKNE0TY8tAy#7A<@l);rT*Y{|*=g&ft!P}cL_9b20<;vfL+<QUNqx*Vi}Oo%
zvK{Du!H_MSAR>f;Le(-iv<N`zQ;Nutp-&MioJnOZV;W0>G-+(-!mijra>Avk0!g*^
zQrE+kTp$<iQ}sY&_+GgZNSRRujSFoK<frB+JGZbp9r}rOW+W`byYtNB&ijd|yfTml
z@dO>b*@YvQbz4r;$%ox=rMx)&9u$H%&SJ_vgKj-lX)#nsQTX4qh%y&uEWI<F$c<(3
zASP=Jf!R?f+4tl8ktl$Z0#5vs5yHC#==ymn@JPWQKYMj9wVh%b2NdG{4L1$}al<|m
z<>~5V#bXR?7Ndg<-^txnMio#ChC4Dvc~tOOtE_2Dp{!qJT`J@~66<=g7*9fLCXV|k
zBP|`GdsJ?=3NM+fhZFq*qZOPu;dwh@Cd3eV9v~%k6C;qeW@J3afW7C&3ZBxC`@s)R
z7LqtzZiu}%;>cL@WLZfig~-RapKuZ;a98t@gJEG07^lN{%##}YlxQz!{i{kx8W{Va
zPsM=~*M9batRx982GBT3^e6+=@~Bw@5TE<&Fr}In2r>{peOYS%$i~^gT>?WDd^JJB
z>DBckS^1p?m$gWAG@LJACgBR*M`E7(d8nYLJibz0j%FiIfh?%FhwV<71H5oQYbaD3
z`_6*(@VwqZFg@^7wr*};l()>JrYs7YIN7~5+rE_c+jK0nIrI<|R5L~*W|t=N0|6D>
z@E1YY-x>Q?J(e^mA#?l)qlJV2emS}1hQoe=5^={xNm$f6H~1Ch)5?G)*Iy0%4cOT&
zYq{wj%_&Fe0BRg?5l8*E+&P#;WcOTY9BkPSb_)rOD;pwrrL8d{%#FC89|^%ybZ6TJ
zZ{<P=wvg`OVxx4(E!@~S1!My0Vd)t<^j8`%CBt|98h@BSPy7ex+#=a+>)L6sOtJTE
z{i`Nm)~g14^IM8pL}=ENZJmBf9`K>~t?uy9n#jhzEc*#SJye_D2ZCxfHcfx8?W&by
z$<Sc!f6FT?b+RpT6g>65Ge@#YUX5w3lJ*$bhjUM85Dz~SA7(c)2ow)N3e0mLr^`e=
zB6MT9;D>iHB#II2RVKdcQZtT>|F!r&h%}ZB12xaDUUA0PNdXYa?=qea;K|Mvn%2A}
z665|*wgMObH`)vF_FUE&E|_e5?E;!~wHZe$!1qE{8qDP$DAF1PB0?!bBsY&VzXP-`
z+6WC>X~Uw&DNC+udQ0uT=|YaAy%IYZ0EYo@4#UD*aI7pwag2@i9JBAO+-&3cAt3N6
z@Mu`rKRuj!c*@BYcujQ3j$kY!Q(!O!Y#;yW4j07)q7<?j+3*)GOg?f~mK`Rp^1&P9
z<Z@azEZZqWD`T3lKPzB<36iPr+`IxR+|(J`Osa)zp9awvj6>?n?D-Du%@9v)VhZV2
zqg^Lhf=_X8;}vBPW*l1;sX$V!^?3B27T$pq#e20$MzV1|;5$Wb_pz`4S5ZsrcRer5
z9h!y&gFtf(2~D$xo~|Lbe$RZM?b1inHRanS9}p@4kcMK}SX>M}U6F9*1Vntyf>~IV
zVONw(q|YR+Go{vs<X12|^SJY!(Tn(hu85XL3)g|n6-NmfjCEwov#c-%3N^jETNO@Y
zoX<ZKY^irq6HBgdPUbvR&6b+=a97`^VZL@$rXp?vGAI_;%S3AY564Hj+Kgu}4o43U
zePx_Dj5YO<)$q$K{T+EUYt!vkT;8+Vk0e{Z5i$V<m|R}SFym$ze66aTVVZ!#!r97J
zka3RD511DQ#u|GrSHqDC$$cKy2f|x15eaFbZ#G^x@>k$8Fw^vjf7d8~w^1a$1S;93
zr}|00m#6kHMuTta4Azhubo9FMCD4SO=Tv!nzc<q`(z#oM9ZWAtVEPnK#}G}r&FHU%
zJCbQ|ZDjZ&lyws(gCT|pO2gH24AiR4i%I4%$9rA-oPe8(lQ{{PDt#nDF;Shpn&Mc?
zo4@zafDr*Vq0}=PoOsEUL+=))LI-=Ok^XxbIIHSx1RXDQwY1L&hI@&~O~#)zgZl<m
zLpBEdV2RR)oBO#3OZXjsk$-ScgrdX+ydFy{jtVXF4buMA{(VG_k0DOk@xJZ9?J<pc
z5+g4*aG`jxSc6Ch=U?*6(`4G@+(NX0Ugm5wiRCHCeEVk{HpJK10h%{OIv{IR<ebPk
zgCXFrZS07S*s2Sm#bN~f8Jtv7f~m>uTkTKY*yiu*ZawKmC3oxKkJYY<#cfvcAE3`P
zMB#3Hf+sDCT*5fyz9GVE4AK6sbF0#ob#dmC$Q_?ukS2ISu4k)yPQ%Y`#@TrLPldx|
z?kiIfRbgFA!wtA;bL5f<@vey^LBs@2?223NtLyY?rOXinpb35#_M!K61nm^lpeMEB
zLZr_Y0Rj=ZShp@4m_#W6M>(~z3W~dYGT%T|+a=csR2lV^{!QEObfVOOGXXRo3o}#`
z35XRr%-O8>QS_5r)A5@o3@D8>E{<U{Zw~g2bK|bQql;ZGv<FoPmDk{{ghS3!428wl
zQGtuSpNhvUbIxwyoQyQA`8ys`rxa{173V>WwkRjABGW6A;B6!dWl(VjAkDvfnK+AP
z<8m9XP2i7!N^+JARtQiY<rm~?G!r(61EP*nINPqZS-*b&`tH_TUmg3L0813t!-J_X
z1wzLHZ#^#D2Wy{T+}7Qty}w3j>V5iI8(u{{2>!^};fZi`gksi%?7e#e<{~~?VlMO`
znjWUElapMhG^uf=Sb#>oSb9!Qy(EeXC<QWC+YZn+6Kc1>cv!Lh+Ib5GK16INHoL9L
zG*Mj2wQ)W|{8?4f?SkZ(j2x+ykw&B@)fi%*OSmfXuj)Ea7I(Owq5!i<{FKkQ(kU*G
z5H>d>+DNgwE+m?^tM-qcT&IP|Keuj)Q)U<g7@-4A10e|Pjd-&np2ez6j~eewOO45L
z?=`%tT+ZSRSx1ZYoco3DaC%U=^bF>@&Etv-^n!pmRtiLzvTLdQ_o;#A*8)$C_V7xS
z^cBv2!R8P8-dtmZhHuXgQ;0kI+-T#=*@1S&35;axQoDh)&XFtK8La<kKKQzw3r8Ds
z>uf)?3@U1~S&|k{2f83qzf9%BF4pAy8{t3)Qz#&;Tdwtfwy)H)bLIU;SBw>n%k;t_
zFn!0S1aC6JlyGBY01AczX`OLecZDV%X+~(Dhu%5Yi0b)nP*pDR_?cVMsRiYWT&Sw)
z4CAwebw`-v{+Q$>Qzm9}fZVp8U9&^kwRA+Bqd+B?P<iJ4lEy1F!eF>MK5L-*$`w~e
z1JAqqPdsd{4r_tdOW?q;A4ty6Fw%9iM+)LvcQWC8OW43G?A9;Aegx-~&CG&kef@nC
zqY~?M`BNR;%Gbc->1oz~(Q4aOnvgP%Gj<KygM;)(Hk#%UU@pI7mZo)W8l7`|-ax)8
zP!7dP7J?pB$ro&p-;?R)>zNpMqCUu!oC6K$TlsXl1))T&7Yry8trLh}8{?9>&@QO%
z9T(B~0v7h+R}F#QcC$u3cX)b6Vg$$p?r`z!pj#Y_Om1Sm+pjS&^Bf7T?FAc~xG7Yc
z?zuXW9JpmhZ}$CSB!{dUN@xlBCg9x=9u=rq82ly88b7?jVa{#vWV)(81Fxk_D|Bci
z`qfgJp|Cs+;2Xumpq}P%7C^qx?PHYuIIM~x!n3q^T99yYTiHAVVrWOfnj>)oPYyA4
z2WI9rgONTEck^n{?82tS@LU#-w!$&&OHnPJykyNeD}Ibxbif3FZG^I4C*`d)`Q0M`
zZf|*9(?%)28a7QO^}H`WTCQ;Y+X6}ad5TVgnkwaC7_!h*DU~Jdp-E$sv3stT8c5PT
zsF`S3D`mWWYlxviU6kmqM|a|IHBc}FuPR$y6sQO+!a`5-lit8_{M2@GDVnD9vNHU`
z3`{n*Vg{J~cYSnHa(Pu#t>Eh-=bOy92b*fp-b>N1=JYKD@e#3L6v!-8^ZHN0Z!B$1
zr|ZXBRav57*L1vN!T~nyzg#sv9V<OkE11CwtK2hoJ{O6ad84dQ%nUCIliu|nTUDtx
z<?RY**R{5U#ip|PXlh?Txz4*=JE98&PF`8$t8)4UZnS39-LbL->Gd?>Z*CG#oZ<S-
zL=35A>I-=ikFj#(j;S`U_?F966@x$l8(R%9?T;hS&_6a&F~^>=D;VWZ1x=+4KvBI$
zASkA_C7+ZfYlA4`rD5{FshCfaNIK_}#7q~k`r!gLpZMZhO|aRP_ZXO97@C*-avgc@
zr;$bQXYL>|$@0Q)bL}p6{ZmY7MO+Dr>gIt)X`98#r1bGMIR#?WycB<2j{Y7PnL4`8
zSrWIXgfs)5daj`2_CkvazJQJTwv*q3JWv7s$#5QDQMW`pfJ--H2Edz|2tczUL7;IU
zQ`EZo417rh;MrX>5!L*Yw=Y717U)j(v-;snNioz8Te+|YjfdY=1LGVctqM-B*aEcS
zTBYu#>AmWg!sqr_OL{gxm<_kpSuvXI(Q!R~;vzoE`K|PYrVZ43nVG1CC3*-T5N!x#
zM&p8BzCSIHxb~yYdDN5-W2XaA-8Zsit`_2MD0DiVogd?<5aKWH-&U}#^7iCjQ?C(c
zSV$_gP(g%m<YYAZ$W=(Uh2M73`&A-_R|1s^=>Mdbe=RFpM74AcfXoJBQOt4jgln^p
z&`3!*Epk&T+BF7e`5MR!8#73-<4}A$f3eBBr3p0<Pzoc@XwunZ40d5>7LROabq;r)
zNnNzHuymO_>RYp;SfI%sOB?G1oiGyV8$nlPRgg`9hSb0OkylG(US<i@t<q_}Eegbx
z*j2sV@~7fNt+4e~5D|ufo}<&G(xcT@0wQihac8Kk{r7KMu&Fy@LPN-y%L#G7h}y(*
z4gyMEsqWAez*Jspo$(YNo?2}(91R?D@vwywf62b89zajplPE+dvP$$mX{8d^^Xek1
z*VbQDxr!s8MZ#J$%=2Fquj39c2(#!-M`xS^2|T;V0W?)dObhgJrX=cio5OeCsVs+&
zkScDEvS{UnCXJY9qc9gfmo^-YBo9)fe>dg*MY^*A3xu@KtRj9*vCG9WFI;LLnq=+P
z!XAPpO75Ps9azje8&neBdtu}83b#82KcHP@&2gJ5c!Tn!_REcoY5+WRM^_QX7VXm?
zV>=-!0(^=``p&I^3=St9TtRvEFzEPoiEthfxH2mwZAp_fjHK0_C)tfMUsBrYGCChV
z{$<|6r=@k_NhZvw)o8;C?|f&15PY0nLP$203O7>O&$tXnrfO)Fmao4mfY%Ozj1%3n
za{JGtKTFS4GXYd@0Q+Q}AdNnFdntx{5Gq#LUc^z%|H6+eM&5_yHSqCvQHZK{;P>D&
zxtagvJ#zK!u*HnIS>|(jUg|L^q#fT{w5PZP`WrFETKu+kgvQMEH9uQuY^(SkrC@F~
zifpZvbT&$JlUj__*Vfs+zA)Kw3&{`$iwKeFi9D{DuNTK89Z)}h3-fW&G@p1(MJK@A
zI7hEXST-mkuGe+br&R{aE3hF+Tm6|AWE?2b!Ww)X1gyrb=~AtKxu@@6H;<VyZHi^&
zWW+U@a7+vDz{mObzyEM!*+R?^H12Iz-sQP&N4{}vuI3|wJZgmK5ru)T`m>*cJ{V|X
zAsLi(VYmi-#36u#)#j0TDMOM_wcS%wck<R7OX3#9j574w8BFRkJdT0s9_tN3fx|+#
zJ65UV(AVu%^)b|9YeW8PvUj?9P8314m%geebRyrd$Z+T^))<&NqzEcYGO*o$s-%qg
zC)n>SUoY#Hz(P#2M;NW2!|&phlbG2{(M1f1D?KUO2)Tf+z{BYgz(vh9;yfxQ$DLyd
zkC&!%aIF&2JSTNu^*;h*X1~>({llE0*~2S@@9txhrWv7>9LV2~NCbMh(-Y&-Pzwd)
zowF<1royll;Bd9`u-=zTSfQl}|7hj1FC~!lw#ikvp$OZxty4-%zGTv|Nzb`L@9+3A
zBJp!{DJ`wItVA)GT=086>+4)f_i4A<2QG~8@doO7T{9bUyC-@-JtIU_l;+R?-R-ny
zl2`mR3H!}#NUE(-$G&)Yv5lFQ57pUFkC?JbJ^gWWI{&MC2T1pcEW8vcB~pK|ovd!?
zE#=xPB?lR+`P51*k@DzL7^|yfAivrpIpo#n&1Yuu&Yh-NSzliGOy3IBQHgZg)2zdc
zM{YVmz%^dMLxXXbyr2nQT&plG*1~afhv=xa&k4KQNDM(Y^bbc3+B=<@u2nP$3w!Wl
z*<19fKuCyW!ARk0bf|44KqOkYgQm<zFLxbWqTZ~;2IK|?j*8N|NQfNw4^5Ct?cq_u
zf*vT+C$rzKPxlYxEaA_f^6AQr>aL#3GZKpz#|%LTxX7`P&M5l!Nw~KBMx=$Cd4|4i
zF8{%*$?fFdD0M$mW(3$>mwhO0<=$D-SGYn2i)BDjK=F+%@04T=?pvn6wd@fc^2y@q
z6qWw=X*;cDYSbrgP5U1`&-HbgOS@D+F6X<e%d$x>MXt{fI>HMfjqpr(8-3p}3jip`
zK;M$45v#(3GDr}i(e}nlhsaw)Qga|1&lp*QARJ}5fpJ+bk*~r#n_lSb3`jz64U?y<
z*DCaYTM~#0(#HQ-D^uey^$O!|F7Y3vGuIxb0*-_qT3Qo9uc@yjsW0@E#>?p$?A#!o
zSl*N#i$_j_;!;O|WN0!w>tNi{{3mHWHk6$T+U&byv*yE(w(DoSa_V8svbHj><a~Wn
zxcxK>4qJFehvS2)Aypy|!i8jgZpib?p-8s|mCxRyTq3lm#Hq+$F^U7i;wJf&7ip|8
zh+!#Dua@|i2qzrLWDy6L7e}D}5@)wSa`u(PJQ!*=h*NqCehBcg|6O0&SJyBt%fhR1
zq0(!1AZ^`cHdD~+)!8h2x3SCIU&GXvgIw-}m_AJekiS1eXwQJRWrV1$)6!OT<r7`4
z?@T0BRukg|f-ZUMChwI;7ZoQM4*jS}JkF11P7jU_UM2LyVG$@v7f(nCy*x%0qF#}g
zs}Dl1W@Q+Oig*>P;9UtMttj)8@0In?;z$WPm=$*s^}2J>ya7&obU>f#yq~$z_nC9n
zC_6raP$rBh>!FkdIR^6G{$m+lehw+r(pg;BzQ%jGQ?VWSFqua7YXuqvD#YM1<mppW
z(IivBuLKZ#-(RYiku~sD7DZGoyAS67FtH(VDVbosGuW@%fdwqSt|a8e8w1`WxotCO
zi#0v}4hK6T?~-?u8`bg@w}LkW1=Z3Puysf{|0fbsI+Z=XW@8I+Y>VB-PMzGXbGAD#
zI)XBp1W^V-?6_w{*F4^hjFvqvFiFR_<E&sj{t8UszU0eV)J|{QqD|kjYDeLGW3_5j
zH*kTOquPqL^m_ICwhcq|eG5|tYA6hLzS976=8Abo1a|Ma(9RdJG6&w5LmmF#{eupg
zL*r=X$6)>!Zeyg!;=D&s=aFEQCX~o`b%!9@OV5*w+;7zj&&Q8J_fA3d3&JKPd05#3
zN`|Qgrro1l2)N?CMY;s-o76_|?o$VNdsqL&Qt*;o8aKm2c+mMctllzg@H=taYr6uc
zE;%_15wx>bi9k(h7GHX+_#ZH+MtQ6ca~G8?4PFO;uFJEEz7nd_Zp-Y^pE*Uvuu1Ha
zbPxnwd!+WeD-f(-Uy)u>^MFpdK099+geo>o<w+*38%R0<(RAhwLPmIGJyl%jL)1(%
zy6e=;@30QiPaW`a65cdV?(`STUx!w}i9hCcY-!+6;U#xbuJBT&xx8w&y&{F;>zd!w
zkVpY2f){<S>-45BuxdfKMzb4UhB?>F$3T*(x^1vQUV;q1*fNVSU}1ecIx+w|w&=m)
zLhRwZl*|;a=q#Pzh!FBgPf)_9XU`~oGO^75%<l&rfUxX!Trkd}>_<@MwAkD<T4uQS
z1qMFILJ-v{O`I2&8MJfXzYd%ynolwTN@{dk|G>H{Pt`|j$Q34P<{q>kSYv!8>+O{*
z<a8ahuo}vmzwrmg#Z+Y0X2{An8yU$GL2q0R73nyp;_#7jbWhT1p@D3P18@A*xZ&OI
z4Q>p<K1;o@W6=|%d93L+a-=_vE)1Dq8XzB;2$)0na^djEAyye4)=+X~&;vmZtRCqA
z^?6SRK6;|Yg*N|l-0}`3+Pj9=1QzoqZ_Y7Va~dg5e8;vo5<;WzG&+w_TVtAFA0m}I
z(BUuuey-=0(~b=pLJZ&O?Mpl26QR1<V$X|FuJyvQaL6sAvD3i<{Jopj_vRqt>*{9s
z!+Mci>)DZEsL|v6gI;F>Fg_h_rEp;f&^D8#X|nA^>)7C#-72g^!JA_m9yJh6f2OSH
zK|!>-Dyb<V0+Gg7u5_YSjtyWqCCju^E7Y%cH`_t=yxY*VKuE>7ANUh7b;G=q+AOz0
zkpOLG+-vZ@EG5$Kdv+F2e~O8;j^9*N(k@S1IbJ)OIM9Pl{OQzwO4uH{N*Z(C^--A1
z)|5wZzWx5TZJ3wAx$_4OtN;rsnan*uPQzfI!39RTBl-%lA0@v}mn~~+MK=)9c)R`+
zJ=I)m&s#M}qrZRd%tex3Zny<s!FMx?ev5=ef>FWT?cr1gw6xY<0kynVp0YjPaMSW4
zvuS=Wrh)Chw_@DY+RN1))@JW(-Z5_eA|9_0?W>NdO+)w0zx-j~x}5EY_KQDtA7W>-
zZ`RF_5lYGez2ao>Gi{6qS5iy0E0ga<8Pl*wD?x^mk&|E(OHXzXOeV+o)e}35WhnIu
zFiNvP#ba8<JhmW3%Y&Iwwc;@W{N#XH%(HH;i!WqS>@OqzHHQPncPnviDnN~p`RW_9
z6&^_Tf))C=vEWx__e0u*@0FJwA`OXvNGjBGLAA2HRLW_XX2(LQFkf?L(~v!@4E<Ch
z_uwyOimh|$bQ&HRn^SvjWDwTLv?T$`9W~-AJS;v7eK*!<U=V9LmcZY}9f#j^lj^#s
zC2xQjvD*xKO08s<V~wn^(|;5{<h>@|+3O6ZQ8-v%<4~G-F)_iqx>MBY%)Pa91$*u~
z$vxR!R)^&=j!wkAsn@lG-8ou!k7p;=s2#HjV2VPeYFeN%>d+M5_xFRdj^3^A@_QS5
zgnyNR_J>bVeM`P(^zY;oi-cSh?fdt%``=|LN+t-Z)3{)2s<ErveuL-n+ol_VW>EhA
zG#=Un-P@jA??gA>sX5W7V+^}xZ_jpQH4m0}`y_66b%A7loVyTh*HPPOWp$RP-=}M`
zR1DAU5vm&Gr_K-#J%|Cqv~J_fDHpqEa<s)Kjl{H*;=adCZS+yytHS>nyZNS+G1HIS
z^uL?~3>NUFd_i-l1BH%x*}mZ0uH7Mq4@mrH?roNBcHGM)OcaQEBuGT6j&}uiq(wo`
z>XTZ8wtH-T>q*$S;LPJX;B(CDum_V>m{ds-yp&!q>ai%8BALxudrm&1nzF4VM3=|h
z%aEPA3X;)W_FW6>)HL+s)Hq`TZB}4o%I+8%UYAKr!8QJmhHM8$7|<dVR2Hdr;Hh(2
z4G9VK?OLIY9QT(%-Ymn9w~!4PZi`H*@2pbh8gAH?U@?MwVo)%Vf5SeF)3)#);0&_(
znf!YzEg|jd$rSc3^QAV(8+-I#2<%W~vQ#?R@o2PyV5({D^iJ2_!A^_r=cibRyWn1K
zDjk&V3euexoV>{->)9W?=TOFkj1P`qbXfu)hg2_O=y?9%5!(Sw+E94ToVVk6Y{rrR
zes<Zb)f&=ac1WX-#78+Pd#nO@bJ+jqn<DkcaZ`ckK5<*RyC0N2WTbu$h;*Rd37U1e
z4SHh7$k?PxJx5{K;rId;QWu#v&ldJCvpGsP$~iT2*4Q4V`)cIrs+7{JYF~!3VMc7#
z?|pICCfQ=%ItWCFHYhEj1T=^%x{+bJat_o{iMP^V+et*C%Gu^F1lEyb0I-u1`J=4r
z5n!{a!ZBkkx@yw_e#h?pE^Q2gR=8EJ9php?&WVY`6h3^*oDiifivrUeUGog38*}V=
zd>r$s#xv{!A!c*{srj*DX5BoYO6G_9*X-THhYthEL%3(PJkUG#K<7RR7E%o;A@eqz
z#E5X38DjC_7^u9@xiGl?@>-v7nt1lseuQalT-Tt$hDU`zr_pjrei^~gr@s3f$T_C7
zDviJ9JV3$F;c0C0<)c^y#@xoQ8o5Bx8>f#n|9GT6BX{mWFZada)M#yGkrkzmL*HL~
z0EVA<CiKy8t@Nw47}y32evXbw&;mY_SlQz|>C!`)t=Y{~KZk}%%*FLfKt^+=izl-U
z<m2~Vih$P6{{NkaUu*bQ(AkkSVvGiq{R4uJVBR#L*d$-$4tYfN7V(4qpD74W@16aN
zy~NajG)t!DnsN#3-vS+{3QrmMpCL`T{YhADeOg-F#DB>Z+T)IN`k`8gFAJ&u`=cO>
zDocc4jrm^-Oxq7DacrAvXYxKo5W{&KyQCrESBn#3XyvMSK{<NSWbLPk>N1CCbrP}>
z{*pVi>^VI1pGX;+nlaYe#G90m9)=p*m$(LSgbE>l42%zE>^j@4B86PbJ>2A(MMG_3
zf2tcKlcbG4lOCq3E0&4B7LSDo_gBu|pPqZ;M%0$jke#5zt$QaH$jGmxh}S-<Scn@p
z;$X_mTZ9aHj^lERMD8XnVQuXI@n;9b&Igs}xnCjn!}LOJ`#vMh!XtdZK_NU%#0e~J
z4CD+dd5oMaA%N^Dc6<Re%BIlWBh~LG0!oQ~mivg3Ob`^p{*9S*J<OQJ3r0Y-s(c}k
zFv#HL=5u`}2U^?id<gCp@@gNzeW)?lI2zS(sT>yefilC_F4Iz%Z@N=H?vhP>cUI$n
z(!d!G^#&E)_Ri|B)~L$PL41U21Mj}?_CWV9&y9tRNlV0T&IkYg&Q)UNa7-Q)I$!8&
zyr>*SO}_HFq1R&Or&I`&HQ*T{!L=ICTLhtWHC#^{Ncw3L+zZ&iB}dKCm_RWdCrOj>
zaw4vg%Hz*O{4eF3AJf#J9{fy`^SE!G`O2i$OIaFX>BMomc%a0Ac-03Zk}Od-*~w9(
z3Yz=+QHNg8SZAoRNEDKe+C-&}0*(r_Dit~Jr*VrMPVX)>#{*8|A?-+=9z~x2@Xjw|
z^5RQ>zy=v!vCB6tzG{JDWZ=^!%-Ga@8{HxbLSJR78F6wW&I%bF9=V}z>-$$YUTl`&
z6>#Ea(jB}!REakYcTUJ;X?q4-YdTkH0`_dV2PtEbb<@L2PvK)D>}B){?v;T0;TEnU
z-$-)Z$>w~3pEK$cc>?vnQZ_^&kdS{w%g~PoW91%P3`psSf~rWCs_jU;X@Ox7V0E6_
z*nOqkrSuv(pdmg}^Hr%DiF$NJeq7G}ATEw@#j!*GeQPa9xf@)asMksn^e7!&yPHCF
zI#&5nIR@c^jCCV#MXM?urrN5cAZLaD>PI%={7^_Wel}!|AH1pwKZfI5=Y~W&brq&m
zP|NH6?UiJ8!=W+k_lC{6Jcg?oPuYRxU@G<*Qd~~79cC`I?9Slt$`JiMzjvuW0OtBc
zb3$wq$yzc>F=a2t-0Je7K+Gs9*?f;bxlb`9QJe_J06(YmtrF>!_V;TJ>2?5QXy#D4
zppU&G*%upCJc)&4i)m|n3RP4X_eWU`d?^l0uBeW_ycy`$CGLU$0c<6`5KxR#XXBIX
zsdmYpsa~UtNRxj)8sh&Pf1~jUCv?c6Wg-^<t7$27?$bcEmlL1rIcdQwGN%SAGqjCg
z&$3=nv)~OCh2!|M86Ld1&SVp4HG06jhjC}_R5@RGb}NZ^&5NSEd14RTR_RGKpURK9
z3k(Zjp?^-RqH7ioN@z7E;*u)x6`F%r^`F-dOXeMsICz!`uW4Kp#peib9mjMXG*(+y
zAsbcY1XL7re^Krt(8PhzB3*d49wYVJ!ALVex++d~S{}X&lxVZt<8)Svvtd%QA$BWG
zBM~D*zP>(|<~4|TW2s&wp2g4B`Jsn~Z!LLBC8y5FoH<G&NGaDbeyg5Oh_DXNrYJCu
z;_kZEZ0!!E^`uS-3hq|80A9+i97S*-#x;Fkp7fbPM|=bTIv;q*_MJ1gMWJ)1oV+zC
zYieOlPy{>DPAd6)M{^R&`?Ql`R0qu;G{nwPXhsj85>UBG?dGu|gtxFz|JYRU0s%9e
zGZs7h1d#Eg7(xApVV%fMGL%Fqjkp<Nj9{lZZ-E9KkJ2P{Ur>`CaKlAm^vD!O2A&M>
z@Jp{W$dYO5WVqv-Y2mN09$oz#WrYPPefFesKG|maLEaTBxwL2=Jr7yej(4^hdw)b=
z>Z*{uK-IpEz#dh!qz{@598@aw@CwG^^L9mm&*SOyp`IpqWaT9jT*47EwP#+?hvxv~
zfJN%LVT!_%zXY>rH54-!b@V9BvfWt+Znqp4V24(@B6pXl?ansm>}JHI3~v2>l+5fy
zxtovJn&OVmO3rIpJU7bT%H$M(C*k;Fc-S}fUu2L&!(6qLGD8rs)v0C@0SL-Y8ex2r
zEts)R&m)hWCist>SVo!~Zq#RnK;3mlW)|8cb`A~xb&9uDX^{D!l$a=f%*1KiPb4uz
zf-;!6PNj-YoA3Tfu*;j{Z=E1PPs`f-UpE2QtyuG#XV7rqv<f?u+dt{rorEM#<#XxK
zNZPG#C_B%~2`({YWTe(!RorMxXxHR=th$?gBX|Vh`5z#J=kUhB1}99)d^5t1!q3`5
zOd&}JKRqKc4%o}QMouiP`;TnIY+)BzRU-{ZW2Z20sFm$Q9QJ34MMx-7z=Sce?xh%e
z2G;v8YD^xQJM4TDODxy-n?OZdm*q|0!3|cH<8P$wWp;uPjVL26R<u(ESO1`pwQ41p
z@J1KVN^n$Pcq+3GKH(>*DJr0p{CxQZfnnEfzL@nd!E!?!@J=L8Wwo7U@I>4N{rv@3
zUU?B<r+&Da<EL8uOtVWI08q|J(#46F^PxUUVO~rSn<#q}8ZHj~<v`A2RGAJ2>KG;S
zLk$M^O+G!=oiilYKCT;Aj7S<=EPof)%7=PVMx87^3=NY5vv`R<eOZ=n;b9?xcI)}P
zXgNn|9COA09Uu{hmZ{*2B)zEqB>p|j)FZ%LH!7QIANxgEt#(G$xK>XW0Xf<*Vlq}C
zd(5wI%86-Kx|W9&cuOz@yxwA8hV#QYY7hvfUB5M0`+t?-YjAZ76Hy&F!sBpMtUP`F
z<2#gW=kCtewef^scmiZ62(?obu$vvOm@}ub1i(%_7AwKpLRU;A!R|U(nmc22d9h*~
zJngF}i9|g?``uCMN3$X#wVb3mXn~wAG@?F#sGQT2Hv$?!BlaahqKs;@e}_X^;_BmV
zxnyksGYq4+*6k{McTM8ki*a~m_|a!dT<Gdq_VO|e=DRpc3zTdr(H{$+%1&3Lr5|gj
z=l7Uz+wJaM(jjOh)Jl;E2A-&C-&;DW$DmQA#~k$sl?@xT*P^o&P;J;y6`65M^fi|v
zz>Dy15#wEG=1;8n5Dy<Om*mnxxr`qLRw#AOx&qCkZCmw*0`18pURD;%I_>L2;N>Ik
zwL7_r${`UJzDQy(ZRJVuDZo0nnxhc$mXfu4z!G_^=G02?LO_fW&)Sz@MF}jnJ*?sj
znFJ%So#Z2?(UfjKMG{9EqN^T^tvCUozBRXaPP}6b-JLSY$r`B5FVEa*BH&XAar@}}
z|1gGR`vttkN$E4@Di-p`TyOW8Z3><Ahi`Y8L!Otx{euyMs6pd}+FUxmG1|O(+EOu&
zhZ?{HjQ!Wa*Q|tL$IuHhe?sCcO5wcRi19&GjdW~(*Uhn6N3l5`nVOLzGDs%9=WYx2
zdnKEwu<HG~k~4NG5d~N$XLrYH=06_TBpjH@Hzl9L=K@Y>#q_|o=siku`|g70w~QG9
zZco;$S&TMIwqFslv8&Fa^8$LNt!8n^xkoQYq;w3Di#)Duf6t+ld)T0PGX{`dblOn{
zWS{~fqkbOA%A(NAr}iO8-h#dRsepjb$OWlge~$iC7(a7F2nyMSCRS~kFZ?`VJ|i|2
zN2z`P_Hm>8ImBUdk<azAFWvaQFHubT@#bi-!W{{hP#J091_-sEqCO3{>~G&*{2MjF
z3|9d9X#fwwaCASq3IeKaQo9fb2gjB>gi9GmI-$X_3LCGp_Qn7|u)X&T%sCQS3r$#_
zX3ZMmWYV=ygEW-CzHm*1QnZeaQbj*m!(>XVQcIgzZfNX4-;&sF3{`{i_A%m;)<*2P
zX#UVzP;Cxzy@T*VZrnf&RNvgpb4SpngWKDNB%0xt1;nsdK>;M%IB=OG%PK|k!yg|-
zGVTO^2WSWICKIaeNq7@t*h4=rKyNAL;1)5+aA`eVG;GQ(^|ISuT*C9F!2OEDB2*lO
zu;uACE0nBxins;5ktKMo+nY=uhAL3K_*wfS{ed7SYft*wPT57(AHsCcM{WtWzqHuM
z*3bZfE4at2c=$9!;#Oh^)~{%7Vj#(f{xklo$intla_!kKb38A}Sm(H!0Vm0?FDTnx
zv6s5CDGy38tj**!p@K0eNgo-y<+6T^sTey?%mqoW!yJr_9ttpI(hi~p%HXAqCNOCE
z)7ii7!V*OZ!z{Vr<r`R?Mm`ajCwa_4o|fC;B>@Hh;!V~wpEO$ADGKPfIbeH$%j3RF
z8+}E4Fd2}7p{n4n>TscNe=Bb|hSpHvQj6Y&fHo#%tUmZS-DjJzfRy(1FDVdI-YXtT
zqvJKyKh=YF@tm;zxmJ02(p7zM26!`MdwV-M@LWl_g9?&m%_2pjB+W9eS(NT&>n5CW
zpiJ%;eKwvX)M1c8SzTLMW<&P3ovkEA09;Sf-N(kvZ%E4)x}Wq4`Ig*42%E!V<{@)v
zC?%<=GBbYLiX2jq2DHCx5oWMjBlC&RayEpXd>IUNsyB~0AFHIzJ!k~{)rNHDZ&Tu?
zNgqh6)7%baA1z<}bD4-2Y6eu+2Sc_F^|n7gRX-aOANqdAA{r{0@pdiZdcMp7!$#=M
zS(D)z|Bn8IKl~gk@s*zv#Hx+;e=Xm`Vei7nXmPs{$^`Gf0v=ouOkK3;iZ_tFIDcv=
zU@LHbgG}xUZgLX(k+?UBp+Me0bWQ68kghNn_ow7x%RCK+G)k*~)C?5N+n{P<qk)u=
zeyg9DCWB9lm3XF(1xLL*Wm`C7Z5Cz1^`!0i7-0xPiBj?eV;kUS^1keY4|MAiRi^jV
zQ3X|>?|+9s_X-`cY;vnnKuTLEl53PEa7HT%0>&O<yU$~5kpbXC*R4>Yy|~H^8*KAl
zc9oli@6JMNwdX{?R+>H>ATc6aA)X2Y_VRxfP7-W~dZZ9x9sFg0wt6R%5exj4?jF6(
z1It1S`D7|(NCo!|A_r5ztqA@Am_tKC%ErXI>R2+l9qN~(I}|zs1G!8238b!tkJ)nO
zQgWGPhkZfZXOcz4by7SbfaGcCOy`NtSHECwScIohjxH+lJ5f3T$=*ZH?=fL?kUn~X
z7~{8cP-c<2e?Qp@l`(iazG*eU4FMITCqr%c2?#d3I*5<Kbi<zFhTs6$=j*gQ-5^KW
zp3I6uksLtfNU<INXV7Lyq8#_Z|M?;)J7H_{uh!;xt7hU{4gI8LL;rmFna(nRDUnAg
zF8%ECwig<l7N6p_kro)%a(A!3M=;|S6d1}M%sFAvFnf&Kx%euKbE;Pd{m^V-?{uB)
z*-ZcJqGe4uyx|D;jVEU7Vatd++h&SAnZF%UV#Hp?Qk)$sv&)@zL>?*&vq;LOb*}*0
z2#E+9hDtV@oUjz>fY&T5dFYBy4vf03WMKX8(GVvO!D*<5y$>$W;z-hUb!kq^a(v8W
zuI)!48uflOuJrLc4Jd@S77r*ndkiQ7usQ-;WQ8(1h8lkku<NjRh{t&)<$g?iaW6HZ
zIZy^<1~R&rT1+iIXKwO0U9BTPSk}iB^#gB9Msn_^(q?-%y~LlKD{!ZQ8jJdrf`n7$
zWGwJ_tT-T>4Gx!Oux_INGaoF_zPOAdpc9jHF9Y9iGIRPJ<(vJzrHHwL$WQyos@mg+
zUL}Wi4YF=EifkuFw2FkDpA>x;RWbnTjCZmB1BQ21&){VYAMzNxd!@amv;s~9lDH<=
zq5xGWe*Stkp2~=8zt{}F$g(@m#<uQ6G0V{grh;&DUSE64Z+fFz6_zeO<}@&H0v9`^
z!0h#9+TtPbjmiwxbnj4ldp=mJm%h~40*ssQR}93yuvpp?I!fd@-&3oFb_LScdtk40
zrJGZ1_DM9@$;`OS$@lJ>>iO5J%G_2xi`P#dTHWs52IS6n!vKWZXvr`?miTf`I(VND
zFxbceWQQ>${WUd<qMcT9i7S{mUwYa(6BH@LN;cPfeZGdWgNLw;QJwO-$IJG(w~G3(
zP{+5k{p=dCOgaIH=ayqT^0upqBhqlh^9K%<qcFAZdc9^(lmH+o_O@N~N(&Q<<mX9g
zwxADur}LElSTK&WsfpLNdx(U3!9*7%auFZiSL_&3@Yd)c7f+-f@&q`Q+;*$lNEc%y
zbTeHs;9mKsKY<?F9Iyz60_^GkComyXJ@-lx7N_S9FJ6(s0U(t!$69A}$EuomQ!>Ct
z&dB`|bYFEEj4>g1?)ry@d~sm5YUK$x=@%p&5~hPUj+DH%8eM^mX6|JhgJM$#Tj_+N
z|1!yRE~l;vG8x0C#rgxy_GO?0a8N$(BQ1B{0+n6!lgWwx5}a9vE|3`%#}dlYVey=0
z3h&-Y^Cgg+V2jw7^Phy~yC$ZHy4crmwWdRVC|tob6$?y=N&1)-Gi^*}(kyVU!XE%8
zXh=|ZXLDHdo0lvOnJ{njiQ7Ct&AL+qN_ih6rQT5(DTjdUJ6AB~P7Up41MK&_Q|bce
zhJ6QG@8)_Qis#Ds+Xv>NX5iOd4g2m}35Su+&xSJo{eUs|m1NAPzy=iV<)VMD{ODDu
zJK<D|&?QO5^tM+QS86*v4bM%K22P@k1aHCc;%=1lc0}n!x>QdkS-1mx0mH?!@-=1D
zz3H|lILs&KejgO{Dz&*<2grzmJxCVUmu8qdy{DZ7Oi3nLZAjsHni{Q1$NFO<cW7xJ
z%CpP-z9P>2AqdSm1f;j%di!rhd@jtS#<0nLXI^A2W&oA^aZjqrZ0%WCf5Shyixo!j
zPbB4DAmtc;+2a};REd}mG;0CqJdQZR`F;^}^b_}g-sM}nVKEPfDyn}|#!%@BBVVLG
zo+Fl&nxp~3QmoZEioY2qT#7wr64-wY2cG7{afHX@enF{Lcd909w3?+r7T1v)6&uQ8
z9KcN;9e(KAb0qQbRlQ`7T&_vIi_@ximf~hS;#5*1Ip8-|>8scv5Ykqtt;`Ecp@uEv
zG_m~{kW{P)N4oJpQK=tU9Bs`)Iy6`W#mCAa-V6E(&+K*R+e+;6tV4mXNdDOmlj!W_
ztsE;JxrkZ$*LJiVwWDC2qpLFeBkbyuZ+a@5v+&I(>gG7Q%`<gy6>DcjusgLq<74>y
zqMfp2;FpTdF~iQa*MO;l88oA2Fv)f7crEK;hG32#p#x(2wD*q9=QFGagT?}e;n5qH
z-@AtL`3YU0M<8ITo+^$I%NWX4C2=z_ob$cW<;u_4F?A1)?U>68Eg?CnPHjYd5~a?C
zM_M$d%siJdzG1~$g6#!F&P^B~MWk!s?OR_7j8(KtsEpze-jDho1tS}i@K^J2uWON2
zcw1u)m3z#kw0nI=l0H^R%fJ&C>*{P-g&Z5FUzYX7U;=dv_cYan!c3-Lci1#r(tuh+
zBk|rhN0<|D-D%lp=hmJ`kAWBj7D_6ytV`9jHN+j&a(rq*>NxR<<de!xs%mZ^o%WY8
zU)d(Q#!a(#xN+{!W;7v^#V9))oY)HbNf%Gx{QIK6=j&Wl+bpwhUn@EA64}x1SqWh5
z|C2~q?XUV)wh}hKk2Y7VZ{SF-7q?I<<Ng?}+&~rv*-EKI8Jgz(=xGXRoO9{12s#rl
zD7o8%pCH1%yYza32#lwP7>L2%5rKxQRY}0kv*1M+W0zXLKGk+SF-|j9GX%uY88prs
zKAq|I8oM~KgKSFO>3AAt2JN}vpf}B5+@}w2rG9sMC6c8r1d{4>iP<BX5#u?M1$Q?G
z%TorD^i}fRcl|Qv^Ku8qN>jLYH-EF($1GS<i8`D`m7}sd%re>3UMx!pfNa-owZJmu
z%vW}Nrg&=e7r`8s;TAJZk}*pI%Eo9bj#*x_xe$f9m5j|Y*?rA4rCeixGv+lV)zbIW
zLoJg$F8(odLChZi@===w=$IV7p?1CXH*Tpa(;)_hL`F?sl74Tv&-??{p-|<H?lJ>3
zjwmAM5O&Z+HlC36gKP`yVMFIMxGt5;OKN!7l#3<b?5-PyA4t*?&U=Q191>i=HaiRe
zOWeV_T(9mlpUOl0UT_?%zo3EV*2!F8FLF;O3`HmpU9c9{=v2Gs&;ion<Z(7iM@*Zs
zj_`2mOlSAii_<2GiEdoP39EUW2n6Zkvmb07Ykk0(T@2iC>;s&yZoCK;E7BE7uHj|0
z=W64H^JLGMvncsWmJ(9BQ-NXn3$uWBo{9OU%NP*5T3fA*NS=u3!A^E3V4&>`LE`tM
z#9FCr6s&N=m2g&$46>glIx>~oG%#t#JA^!~H$4yN0)q(3miS9!<ub(kto=G%q}07X
zCQoC|1ISZ`D0KHwsm$x8rbVP`Q(=YJy#3kkwXQ8Td|x&~2PHIu#WZ;Tk?dLwP2%x|
zTi~-GrgJlU0zS@1>ixRDncA&q>N&vAc6z0RzzheFn{#3xnrw1DE-0%QW?fMC1g*LZ
z0oU$We;^i3v^y2wIF<gwT5bPwIV!zgW{J}AcJ%R0F?8!OuotA_(-P}T#`%v;Yh2vl
z;X(Pt+da6@bte2dn{nvZ#xPOHCxDiPVr(Nmk4`n<?6|HL=rAVl%PWAX`5<>07Z*F!
z*Mxk%w4~Y;bQ()KYHP)dL2e!ZgDQiVlNa}civp(5=7}KF82zXmHvb`iUxZ7m=(eqi
zwNOFe`!+Iyts#LqvqZiLu1`Oq)cM26ivtixJOd)Ia{pi#q2$}qfluN1ABC+|jK`kS
MV_@QS6~--#dgQ`4CIA2c

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v b/FPGA_firmware/q_sys/synthesis/submodules/altera_tse_tx_stat_extract.v
new file mode 100644
index 0000000000000000000000000000000000000000..3f24f08fd0e4f69354e457c82909286ce8250e86
GIT binary patch
literal 15968
zcmV-mKA*vh6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2huuKQ{Xc>xdK#>Z<MAjE+
z+|lP7kkDI}96}@#y-qF3n<G*bAY5pN!Y?){=jd)quX-tGexOKNMb>zll6z7%wwUlO
z(-OLpa?1$P74-xu2X35pY{w7Dk}bU{MYI2RcQ`eS%fSG><N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQmHSl7141rI}?cLuKs
zgSfHq8tMX}>F{k7s|i&8*J0&tjx^-RI#5!Gwh|mKA7y*kyu&swn1Woi1-Wu%H#y61
z(V^lrFdDWcLFJw%hdGEfqsB9PV#b~ox!HLUK}TF-(}Zeu92nh!p*poGMoqtir}E+B
zQ?3-$UCW$oyzel^NJYIUiH!ctwk4ym$-3D}r}UBMo`(RFz!+(XVQE$<WBLwzK3#Ob
z_<AV<CPWj*+LU?|(2IISv5d$Cdg#7-*jyY;|BtkHMZ~ILvjxDDg=e0~JcT+Jhb&nL
zNJ=(WKyo?LZx!fAtZd7qkw;RMmv8R{vt=Du>@o_@ynqbpPX**?Zr$lc|13|o4B$vM
zWkpDcvSBr3TC!Z8w=dSx;XxqHP8_9#L>Fan3?^MPCoo#JXu4<H++6z<wNb1gm;cX<
zr_!tz^0ncw4Nj07g>fU6U)>Lw1ssR~8mJ|ojM_ENC1r4&xxm$>TCx3d<e=sJRFXVC
zvH!G2!N@<)qPnql@h4z#3IQ^WL)8#j_1UD#Ewp6`e*h5E!U>td2^1%f*58mMGdLxE
z!7k1F{-4=`1+eRw^LN}CrHPld=ng_f;0lt*xHu2{w!mopY_ldR3w)A{n*6mrMcqqV
zYi)#86wfR}9FYEq^qN{sTLI+m$fT5>Xnam3@=Yvh*<IPZOT1NcM0Pwa`o^r6s#&4(
zjobHn*P@ZDa|dEj!U&YwDnHhEvWN`bmi_;h=x(tiCL7?2m3EPzHLUCratODq0hC#G
z%CcSWo^?2Zh)eI#oj%&j?z7+y1{ykQb?&&k=X8Ux4q6oTtmij!jLs?pp02GD=j=7l
zGK6?@$Yy$-dO!(`Aif{EUnD|DP!qd>8~QGb4r~fK-reCDH9cntc*iadeX#Vh5Hu<A
zoVjAG*H_3C&2_}dtCsSiJZc6Nt-n|59P;ed)eWx&BxZxQyS5>NrW1n)g$|^hoqZAn
zG4*=r8Ti+^u@tAK$%$w1ewqfV>e6o(?0E7I^Hwzhz@f40PWc?Kx~J-4u(pfAV;H6%
zTOje4AMO(P*@Yg{UwT)0xTN#(lURB(2NPD4Rs;bd#wPp7GEYN<rP#_L22Wzj^kQXD
z<TQ&Pk8nr^(I!C96eC1!A*ZA@C=2;=?h8U`+ltXg{K~xIxNu%vN5$<EH4wnp>wAGZ
zr_etHf$wuM$sh%dxVBo}<SN%^>}2A{v7^a$buo#Pcm>i}(#a0|F+}Q{wc~>atghJ5
zf{MRjh1xw#L2Hf${3x`3Cq=D!<<8pY-<QD1G-CJGM=%LfF2JbB9U0xGoaunPDnJZt
z4gmt~;4GHWVwEkA9B_Ax(abtpGNb;$u6yW9$1q3%Z;?T~80*9TJS%`_a!P|}CbM_m
zU|LMp3Ed5l+=-X~lK9F)l}(v??SoxvbC7Rl6UVcB|Diyw23D&8@vR~eslkfBRRmug
z%6)62aP8bmvZlizgvar*u@)x}GLS1DJj(I$M{L2eN59eyuhX0s-rL!>#qHmbCx!co
z_7#m}=8{>=ue?zOP(syt?~U}SexUNr%;@BwQ+=eV-zNZ_&q|YLZwO<#CYy{67PM%{
zO{>7tYESNYt>|kc9O{5bPvc<;R&LmWw<QWh?->c|2?iYkUB{<#ls)|0L^$l_gR_P^
zWsPT3&~{qTN_x{+txudzc}JS2F+#_WG2Z-OQS(`P)r{M}jrr11spt4xXlPR8nPAk!
z(lircv+PI9>3%{*2+ff6cxnpPZIK}Ke%X!xR~4Clu^o-_fX}IgG{t7~(!wYeqN$IV
zRLM57h?swC2bD6yPY~O2H_Xn|B8TL;BVfG_EB+y=+3M}>&0@l*omchPU5_va`q-nP
z$j8%|0Y^Q;n*`qSUS({E=|oBmHu-gm?%niX19Yl2v#)zbR(W<r=B7SQPklj}LghF*
zbktV8pBABK;IHmk4vtn6FcE1m%3VC2Zz_JUkTKl??3KG1!^MUQV(`+i@nvH+Zk9mX
zON2C_$*eIH?C?`Y{kxK<tA1W39*zPIz$==RPH0)P+(v`b3?>_-3GYbtko~3>&)mFD
zy;d+p>;_H>XFc3Nv04~QCeIQ3ww^#I<Tj=JBQt7dDbao&x!)MKV3hJYs=#uUiR=>v
zL&-elSVur$=8l<*72ZA`23Z%)Z@qj-v~I6$S9Sg`LKRW24RvUI`*U*RxMag>^UCBt
z+KDj{=957>oVqsRVEBld{s%$>R&CPfq{}`OLC}3qKna6!9wxupZ^Dp{95#`a?A^+h
z^{S-p7uN1C0ZOxE?6ld~idQ}IchUE7IirbOA_`!eNksFCmKkf(U}&5%e;ccKYp8D=
z7vWriWB(>?c__phPt^G6*e`(^KLHr4{oIo;sKFAw7?4xS?YLlRdv1}G9Q{XVyFN`J
zc}?-4+OIL$i<xM!t&+=EPmBjkLrwA9Bpj4QPjr{>RW|HiXY9V@Ss@dV$o)8NbSsd<
z2O@x_1IH)JGkpBif{dUXGSjO4Sa~>_x$Wb%*NsBv)6kLE(Yifv*<|Q!97<y2>y%d^
zTm|iYz2h_t=56akTy{ssN^}3c=1b_&cC5!;y>gid^g}G|nY`PjYRNaDgn|GKRacT(
zwoN#063c^=-E3ptabk$G%+OinIz(z>I`OKX&EH#}e_7q9Jty-I2Cf{Vxvc9=Q0OA;
zvnO8I;}AwJ1`W=lyRm%u3vgk?+Y-+KRY!1dRJS4;NIaTZazp++a9TfS28Fc-^G{ET
z$nh*l!LjL2aI`tW&q^gF?l=~atI0yi_yBV@_O#J%rs0RW@-m6r_AIJ)JsDJ%W@Uvl
zhgu?&-0sicjeO(cd(Tdwk9ymXQ)Rum_;3?oIBpv{B2DE=Z+}@I@2V4s#nrF1;PCAL
zAXSqjR6a|=%M1jq`X&imC1B3WJ^lR4;^1#m(3ZOE>LJlPHALUe6Vgr_eaGUYVs{`i
z>Afa#a4{Op|6{gz*sOH!K-u?JwY2CD6=N~?a_NKl=&9X9!`jU6SH*CqTf=}dRA@J(
zTJ}5~8D>4=5op-2xrtP%iM9J;Cjs$h(!<5#ZYUyXW-knMGS4xm2kFe)qCfl7D&y=g
z94ZBqbA%eZM4fT{$QQbl`&!4%?#tAtZHV=ogYy0$>O`+O<(&mJsOmV*d>xX|4msJb
z@1BIb%EC>nUh;n^6`YaKBYxEG&VZyHugC1_QOvHI87pv#et(~4e05mMh8k~S5NmST
z<JuGVmZ6gV|5<@%V8-NMZXp(b_U<zh3y=cF^)5l9k(h$=_&GNn<7J#e!kan97`EsR
zL^Z0iioQ>c!HSlf$#*(Gd1&jZik>UPWhS+18XyjVl2>`EFbvr5FPX2b645P9Xb78n
zSUU1`_;Oh4uOk!oB{BbC+|}Cv4gP+(LQXov+N7<pnr51<`DVhn+km`DNFQhj#6F@{
z-bW^PzNui^;ikNPRn@~O6T~rssB4LvdBHXo&SzN#0TR}Fs=9R`1*nF{a0-O_qyf~j
z{u`1xS@X1%EopAw-(tO(gG(j+h6!SqB3Kb=WV{@axV({q43C1_-AdWjwJAexJg?Pq
zz91bcegvQj=B;QQi8~(S<hrJ|$|h+FS6WP;MQ!5vFh=c%+}2^Tyqu4kRKaE+?dWOZ
zKTF3QMs~m@uM;5wp4|K)79ro;dB#N3llZACD@P$+-kUrDyh5?>RPzl%z9fj>oG|!7
zq-DfW!q{s&nI+hk{=i+UQ83LnGEozu6fVD%i++mLS%^$R-fW_a@T*^Mu?+Wf=oe@R
z>C=Yw{-d(qV8`y05I6^eDYTD2v0MGk)4UPp56?1-rPL7!R=_Z{8U3@e=f8YKkbd`&
zu&zBG02|HmHP$!yFl9PhJ9`jY#-qd)AW8)qvfsR}!YbmQvWB#IlDr2Wu-{(sGk~1Z
z7*ZGT`>!BzcJ%D3wPV+uDW2a7Y-#%7G2bKdGinc{znhPG5uRl@M+4Ifw3FN4v8Vbf
zU>P|ivK3^(=cF_cpt?<5Ane8F-^8f&(ZBgKW+tX<l;$tCY=Rs5L_<^&Smla$Sru%n
zw+lXDZr=R`k3Op}G6nlVZ&9?yF=;BX)-eVhk<`;AT}U}68lRXvqX}=q2L#z(jwOEg
zAf_)kFJ(Hd7R=CCaM_N+^Pm?u<2{P9>6<3zH#4xfYwsniTJ2%gOf7l87?jT|CFkGA
z$ist(UTpRf8kys7QxOGDubl9+97W?kx}TJOgzLZ_LDU>lkN)T#56(QHfus%uiS+yb
z3%<BrvDs*Q%wlVcd2UcmS*^z-t}@w?Z;1e!KLpS;`S7HRdYPjwOX%7P2Y$Cj@Uo3>
z&eYvwcZ{5iWAeE)@hzlha31oO8EBXRAnyPXL`01x7|t-2Q86jL%S2K%M$Byv2=K$_
zVXR#o=i<{OOFCkQeCPZ<CKUlbMLTp*MRdoD_}Jz*RBl2b0petx4aC)*tq)wEmmccA
zkjBk?`aKZjG^m{+KVR%VBO(K4^7Eh3Tylf$o?Qms?!k!KLu!8$FpsAk!2iX!>df{s
zf3JEXQ%z9le9n3@b?3AZThc-(DN-cz$wTpOZGb-X3US8HBrXetbQU5G>`^U?r25cU
zKd0WIv6%X!aa$hKxrTK@w@?`prl&k@De~B~(0u#$%xGc?m_Zalg!t0ARkLjejfA`q
zvIgluGjFt<r1U4lcLSfOlNN23-`0daQMU|e32xXi6kjT`2Rl_`wsc#oMNqV@<TqVZ
zT#^2>@siC&PSyaoQA-!a&GZQIK^8Lejdy<@DFt$W8|&z*51^S9n3Jsn21*D%B&I!i
z4m>Aw5*g|aYhME46HUl{^R!kl_8sR69>Ya($RjJ}FJSS*OjM#N{TAdt3>lFHx0OeY
z)fd@<lfzbcK3k{>nq-k|qY^*km3SRPX>_;6pFMPEP!$R<HSVbF@CD`sqK03a_cHox
zdZYAPYLRWk15`(b9EWTRmudk;Mhgp56IqGqcYS$i&O9T(#TQOl>2KYQfh^D=ldi~4
z-Zhpx61A;U(*RA2X2sO7>;K0l%ZffBhGQ-vXXhllrq@D8Ek&%7>FEH(OL8qb&>M#m
zo-7lcN5@AP{7TewvXOi<JAx`%L#-+ST?^d!tNrET>0I_&C~H26M=s)q|BQ73V->1G
z=L;<d+7<1XOS*$p6PPQaRnXvkvm>9W#Z#2lb>E4i5N}e3;p-9+AD`q#G@*Lu?a|z(
z)wZcR`mmxFTmZj#Y2fsTeUP*i!}E;dbQ$+zM}?WTGHEVgI3)Imwrc>>?E;5!p}rMx
zviXO*VI2HkLII+`#N+f*Z6M|2phyMdG2#5WDywpbY{uu{b-Z}u_SH|k+S%Je!hmff
zz#Me)h241dM5txITq_W}MA{+GIq2fS)#1n-{pJ?PfZS^KhZ*Z}!!I(Qsyk_o5c2PQ
zyw30mPUFOE3IT)3C}f(bBq*K+8Y3dYBY4&`@6~~T;47f}kJ8yApC}ad!TQn2Hbzyl
zFEcfNTx~~F;EE%QBbz_9sh-@BJX?VfYb>8nM@Hyk+G9>c<nk}(mFUx7z;ArsRLgIl
z@1`N@E*?2)$;g}|z`7v0JT1l>dz4=Y-?jE|JyB^~RESLRONAE=<)cwuXrh?|HmbgN
zl1|G&t(E>Ed@>{>caUQkg;B>m#Y-I;fKfZJZB?g>EJ1>kJ7J`V8+(j3zN4*v8@nLK
z!EBb$BIanGJV)JBzr~O02!Z&#x_!e|ppuT&33N0$iqsmfdWi0p%F=u?{Mp0~k@!|%
zUDh2@1$Mg(govr|MB1SG1dI`hAFt*IzQc+Kealgy=8%63$>#6)QZIL(ZVx-9Ul^?e
zMox#TP$7~_`up_-%K@oBZ=BF$qt6_`fsoQ;dGzGAG^$63m1#95#1uM(D}LD9dj0(l
zySF8zYD9D;=L_byW<YVwF>}<!RTQ*<-cizx@x_E2xjf$K`;H(gQxc>anKL8QJvHCo
z&*)_2Jz?J$2Je^Rl;7#nicWHI<+L*)()rcgH*z_EwJ(U-uTF<pH@hy|UWZy&T*xhD
zD7r2-%3_-pnlg1V|IDduASCZ9bew+vy8LZudzAMhDUSTTbPfz&JP$cT{uC@_Swh4e
z!&e@|;mO%UCyOhUF@_Pxlipo5J>!6|IEt1naixglf*8nby_zAm+r2K`)}GafP;fw_
zX_WKL!Owd|i5o!Mp<44QTjmrf6SArTz()(1{De3S+cuiBJ{Iy!WAorRa(CC;PWSdd
za%O0pxHnz-I&G}>Sf5IrLK;zT-5u&VpMg-Mq}dw?u#x(^H+zR5AUAA-vLT4PS6h1Y
z>51I_G5{&{)M+P7W3%VFS^<J6|2Xr{f<0iI@c@cpp6L4lx(9(2zWSwr;O#PMEEMo3
zHDgkw%a@uo^AuW4vts3Coi8!H*vZXe_qtD3BzjDrY-UsN`pZOFwd5j;o6)+7@V@3f
ztd2BsKRJ%KFk?~D73YAW0{49Dny&~K!q}8`YajARtApnH2Yf34Lr4VGSTpjLJQMUc
zr3T!jZx}r3M^>{o^$2(dpSc=qWEl&DLu(m5mK3W|7by=@W2zV{q!8kT>HRE5y}kW>
zrzA3;$0aU79XvU?QrzPHzUmV?<dY^O7iYRbhA9JpN%-~&GCZU%x%@3ji`gg?@5#Tp
z5S)~Pxh*YOLA2|1ShKmWc;x}5QCqXA|He+2e(XG8rLbrcC2k|SFGZu+TQrH~-jfkN
z1`pQbpU%k1$Pm%JV6@EZTxDdeAiLsTRyS~Dy=N`TMJ@q>vnSfdJ(SNt6}`j0`n(D1
zaT`A&h#tr)E(w@83rr-oqniO{?Bj|SZE+pT(yW*GC+UgIVW?_+4U5lQO|3IRIeHzk
zJVSNe-0%;-H=24&O7qvm2cNueWWh~!CN?RYsB$a9WEmD-dhr3dbMV|7f2|K?^h1?C
zg30e#E~>T{PxYdRo$bChw-rX7dU;07fQ=&c_iuCG!Vud*cZ;>=tdk!T8{9U6(`8Yl
z11aj$!w)7IB`gR}MFyjR-fkJ3nzES87SLIfiiRsbLxD8nl`94qMDsbRv<~&*+KSLn
z*p=9ab5dDESmxArH-c1VC<nw`yL(u7#o_g3x2#<9Jor;P&V3u5I6FccM#yU_vV<pv
z?b=ka{cyyRvrdbg_?*s=TpOVerey&iZI2NK1v$rVdK5U=+U>IKqo&9p8UPSH!d@8+
zTe&LG%NRb}7IHMIc2F@266EQef(nO5jii0}hF|gQ2FrF*8LucbS86uV!{4=;*m%@-
z*8!W06|XXOxUDzB*-%7&UW~;9XZ^JHKa(|zu0WWClNZJlTOqjh4D9YZ>^~(JpaR^B
z=@yUrqevjn_W|W-U{+^2YEh#sY(mnOvD|%vf5IkcrUX-14e-#pv4fZgCZ-e2ZF_*T
z73+Do``p^s4D71N7E&6=ljCmx>_w`xt&pgj;Nvu~7}C$d3(;#X!e`n1dAEm$VM;rc
ztaXK~D;$A@gN)*%OXWAX7@derHiXb#zuLisn+H+^0b}hYN{S*=U}ogH$QhyD#za7e
z8xw?IzX#zjmqi73n<fZ4v7)y<r<mEDJ9uFMN9}&;{H_>2>SyGAG?zI(@x&^qF<kX9
z_2l991kVkXz0t>>eSuo_o}-^}8>2cv4Ob(wAAzY4GjF?7fmHAijqY*G5-Am^RvRU?
zH;~gv#LlXJ;3mcP<#e+^Z<h0WMy?nF$^uA<SPkKqUD|o4NFmG;v#T5a2fyOZQS(>2
z=M+wjf}-rHj~E)iyh-}@%xcluC|X$xr37&^uB9S=cOyCX8p@LmC22hUZd<tCp2NiK
z`X=FgyQ@2XI^irt&un8vdhJ5vs~)!X+if4;@MNOfp|{oaR4?%i=Wk4?j2vKz{8QR!
zQil<_zYyeK4;-n8g)8%s$IOwa<36w`B{CC)I%>kh7{YIvCJdDHqxZ>6=RE(aMJv+w
zOr(gk{3*wkrQI9ZFZv@aOyWgGT>^-so?DES#-IW14jO8u0xEzXiM_HE{u7`hIWs_}
z^Iy$g^-N|K*vylfdGr$(yE{M=W7HM>PEng<=tY|kULS|DPR=k15sjAQ0dU`3W*EXo
z{Ju_!q(vnUkVwYuP18CFN*83bJ4<F!waNF!fGMgY_F2~2Sa-_V6BIz~y-M}Myn=43
z!1F-cegO!)LFXSbL?Pj-u~O53J^E}Kl(0*<cY|?ZHoPa9a4N#H3UQk9ehM6B?fW^)
zfsvUD%WRJP%(+bVJzu*Mjz6-`bx^eArhDU=k$TANHGl9%RwaO3>LVHET)K{BW|*NZ
z2uQbsx3+iP3=8`mI{It#QzJZpB($0k0+)LB*HaOx?(g6%xc04h^}5FNCljM??hYgr
z=A7II?YRmY#^um?lTr0EziLR<6Y|K!p=GAE=&mo!wUu{R=_<%%zgOCb!!8@>=OGj4
zF*IyociEMsMypU=<iYB1`V8yZ%I^xFs-%bi(dbL59OaH4h%g(3B&Puhkk$FHr7o~v
zJtXbe@{6{R?p8A!x}*DN78~B8$|aas?Uf-~Bt<+1b5~O)$npr?t0$n#im}lfusB!}
z_6Je7_z+@!t3EC9h%GfCgsvvH-Y3$cR3HJ}vz8a1tHq{W{WE*+Dq_kAwtDL{TJs;*
z=U&QFkNWDrRl<@Is(W01(LOYNx{LkBqu%Yv3F-8)%}W@`kj6n!a&!>H8asBxhhHFQ
z-)&j>Sa|pp><par9Brr`c;!H&a*kn8SOo!;hjy6~!;xNDHImJ9W#*#xkpT;HvC=ZR
zgN+5aWcHLI>nw(U_l1cRMi%<d+J3vrV`8lbVdZO6R_2r6i`m5L1@#3^#_vb+J0|Bj
zuPZG#?>*0X$mDc8>KT6?@#kC+#1T>6DKF{`%o2@hWshjNL+9OmD;szzti4-SM)7B$
zjN9<(O~#v&K{5iy_dE3Pe_0wS1ABV#D=V)_)r6fmguceQgrIpH_3|n#>>aioK7L{<
zR=CMq$fG@M@$5KdA0M8b0M+~$TsBQ@?PUxoM<)#449UOws#NSgrP`K#vkws&csQM?
zEmkD}29RIN)Zes)fe-eg`;9plYR^NkqyJ7<U*+AOuSpbvo3Qo{qutf}x=|5+>Qqx!
z^RbvJU5fjSFdIHz6UMn6NDO;z%W~THf%39Ly-+ZXAq=s?quxCwrq4!oUh^~pKz(jv
zM?R^g@fa+!leLY}^qP?K96)Ru5>$bwFc#3=xd9ir1li70o;#x#rJ&w4|EQBiCYafR
zor)pow_E1StVFgkrJJDdmWW!7$-V%<S>ExosG9JF=p7RF24!;f22{fVosB^gz{}<*
z#+c;PWcVik!EzS9K$O%78VvmTZwu41T0b;VKbQU&1KU-D)7J5RK$_{EB9-<}v*)FP
z)Ww~6n|24C55Ov>XACJ^bFjEH6p0lIRfedu6^vx;=UH;DKx}iym%{bQpB7Qjz97S3
z^V?X?4du$ev~L$4<+b|O^(BDpMUGmTdwg$e(Z<dw-`$((ehK7u5?+gDjEaQ*nSRp2
z@*ceSJx};hUw<*awc?2=385TT>;^c%M%><TT^B@sLHKz2kj_qDRlFL3e(bMH>GP^E
zm%WgT#ke)K8)y7xIqBn)deVF|Ddp{&Dw_7e-$xh_!(wddg)$0JR|R3g^$qnf1VB|7
z!*Onv?%C{M)h)zK`>9+{KG$!h<d6L-qZdcfCrcI?i!ozm%Q5twRr{n@^Y2!Vsx#yu
zUISSw>GX6<V9@oO3fWr-xBiJiq)RXNO1h2|e~v(QEWLqf6q{?C;8o9&i*JVkkW-{a
z^c{uCdf%j?B&Am-(2e4-+H-pnlOxj6N3T9*lcy@XANns2f?o0Z(RmOYeah!y=b?i&
z{1cABZq_a4&=$;xdhWyr1dj`=XuE(nIuqS0jBs5MS-#36_n%{(tn?f1*wtWUuRjpu
zd=2ZS=2XP@&Mvc};RE!;ri~EUO{GHzvrJ@bU<Xm3RNSZQ`nn@ez!s66Qxh;ur8O^i
zYpL9=d9wxn;X&FQi8TZlw#}7$b(-MnS2h3Jm1#3z)lvDCFQ-3SY)GSWyJng58k-_1
zwd(X!KXbji7~SwL;+~s@qju)f;&>f=@s&BF?jElhJP~MlJr2+=dGntaA8=bx_&)1A
zbogFzL)<>DsJ$qD+SI@!YiRd5K&Qm^$^{Br2%;VoP0byz@h`{PB|nF~@9lIDzzg8l
z&B&lk(6_mX&+nIb86H=$v2QQ<8!=a~9c?s0;}V0m4waI#fNCT|pMWH<aI`lmpu5@_
z4OE`~vunM9K_CClFXU$31Q&q0)WyH~9rHQpR4*_|-Fb7f<&>g`fMH`is&-FrZnCMK
zj*crVunu@q;=hLksPOHuiDAlh#|&rNcz72kG8bqC2^&qSJvPHq?uf=bI)zZwZK<d)
zUkYlcPAG0SrDdV6mP}~Nd1iiQ{Ck-<Y@4MU{cM91zP>byl!{RR!%UVU1Djl!IXNW%
zR#mq!0`kkZFj^m3TBtY`dI(RQP)YWpQ2CEt5q>k?yZsJ$#?M5z@EpE>ngcB2=|v?O
zlCu}S=@%a463Km-W>2sj0tXH6`<DvRA+xr}lN*w;fZqlY{KwjGew!si<#?O00jykO
zpj01m_`bmITP)9AL0oU~{;OsC{9Si(`1ReST-sFbV~4>LdnI;>VrbW{O0gR=)lU7@
zQFjf~l{e>|MH-BkTcuOyU>g_ks_};FEef7+h8UukSZx0gMChz5eq(mrn8~gYWU#dJ
z;mf{(P|!r!!Pn_=Mofu?IPCTKCJP7<zH8Qdh~2k<zDF@d!buzo1dQ}+{5W&+x&CBt
z9VNOkBLB`R&o;j6oCtGo`nL@X2OvSzL89x&)k^CFfm_Y=Axy-5=`>3qG@RXUxxndA
zyoeDj5uOV?lvlCx4va7YjG^V}Rev@}`PfOQBHYN*S^}|pP^0+gA_Hs-I3ey2K~_n7
zB!nbo>q-kQwC2_5xE0J+u8PltM>hE1E(y&u)-qG!T4XsQT5~a12#E&e_Oni7Sm&sk
zP1wws`DSOox-o#Vl7VFcgauN1<Q6*iQM8b}(;|>YwqF`@<dQvjYauiLXRk4n1+13z
z)H2mmTb1~lvF{&TS1O7nLey4*x7z3Q+skjY(?F+Ys_jc}G^Dp>@_?%*4wCr&cm4m8
zC4M$?kLYc1&LSQZc&Ba;G{@dAk<0VLuy7xXK+rO}-Ay>-xH;<d$gSh|Sc^?5I|-wn
zUaMsx$#sz6`C)YcT|BrmnhR(Iv8yJ|514qTikLkO<45%MR@Qmi$?kOJ>fdt~3_2^u
z791XGsIfbf;l}l2_~c1)l0>aGtCV4(FP%rkkLv%}bgv~O14nA(djIKsWLlV7!@rLA
z)4A-!Gyxbjs7A~JLz@=!4w+!q8@^j8!`xDc!0dT~Z)Lhd^#g}vE<=z+CARQ$lU1Ts
zkb>W$Tsq~JI(9|wblN*oJy2#xJUDg?Zhr*hJ>qG2tfHP=)Ut0by9WW;EZqaUu!$fZ
z-GaYL7I1E5mCBq_Om5@m`a?oyro`!%`MS77BLYD{NgM)vMk{YsDoEvQ%)epabJTov
z1s4Bs-YZ={hcn&%6=_xVIaYJGNq0_@Z117N`2PWG{J;R%p5!yj!9$H=I<<Hw9nVg!
z2yeF6LCAAvsU9{^BOzYiYeS<ZEO!UU_aesU@iDxBmMVe&(4{ZrT(ryX>33CGuE6)|
zh;#^2JiA}%be8ewvp)=TOOUdnDD6v)cZDXsK1bm?zm(>W{VNy4r)b7tkAz_P4|y;L
zn#Uev*wD8(y-p;<fG^Yvq~dj6QR!&oTs@bpJo;;%b)mr%C4wiLmN+J-YWaHDgPYG&
z0#PyqYInxOVXdLSfIP0ogoiK42(x%Ce7E63w-SZfYZ_b<yPJ?rw*U?%;Ggaqal?2m
zFVx`Fa?cV?YE~IvB~Lz2K@yLqnO!sKt1yRGPkrr=@TS3-L))8Pb#Qkd_JJ26B!bA<
zE%y@`<y76LbJbV+sRjGu0n<%o3Pr0{g|K_g>+hTgLCaA$=Y{gx<aE4BRtEfDW-Jh^
z8bRSQ5NBsEq~ZNX><(BEnI>eD*nAJ65cLs3@r;dG%3+zz$G~V%8?cv$j4+JBLBHj{
zNZeWV<yRR|IJgVzv3wK`+FtPeUpmxAM{O|_*l7*jOQJEez`pmhKzge_rdxoS3o%Hj
zSA6240R%;a4h>ArbATL>dI4vPiZ>3jd4_>mx9?l!$4>ifF+Zv0EXzEdd<Y%oMtQ+r
zS(=nW8jQRY2hOqvVQsTz#F!4!sD>olI5Y2`{)7yDxhHPX-Hs5sNbM)kZQp-9oD)`|
zSev`p&jaCOCGtKde$M+7d--M*ZKK1Vvbdw5;-P9g`l~nQ#)Ob$xj%RZdG=*QH0Qmf
zm2B$$Sy{kMKEvRj3+B^exZ=g6TO@bqnW+`w#dSL&On3l>U2%9KwheA`*CWk(<J1}D
zDHJ2xp+`=FjSgo(atG~#aH(;eG3HBZbfJ?30$O0N+3%N{d_@6-?KQeiG)CY9o%Rft
z88kvLHQx?#IPSSBeJtD`mm&@4(wagr*2sGgU6ER!xc}LFft^0dr0Kvu7<4k%eyw>+
zxA9`kaq->ZF_}#foWQWGU6NM;MP<L+)27YB0O7Lrs;zd`k3IIN`dV*ZoeLSo&U#C8
zisWL+fT=PVaP^Nbvaqp}IBJ0|IS|N5eaQLQs9D%^_Q|_pydn(O93PIhu})mV7DJG1
zf=VbAi4C_s6NQGAZV(Jrs_Z+hI6%N%#=RaLBf(}IB!=0w>f{8Mbi~Q=--7MtnlNB+
zCDjmeg;dYKg6@yrXSJ;z&rAtYPRIkg)Q7KeN}nZzNAM*M5G|j@dzO*n<v9n_dzG!J
zIYOZKy<M&ajv+^9+T51G_q(8aPjI5e1kNY6WW#Co<TrG;Qx~Jaav0C^=Mcb%jc|q_
z3ja$<D2)dewRbAP)|F_BR{eIamS}aSP=w}s8nxM;0N1)h>Sw63E~Aj?7>+ne+$Qs6
z4K5i8-o2yv?B79u5cyn6hCfxdw<Ri(DBta)R$J`mCT<~`*74E~p8~+>M?;yC>{v(A
z)I89P%Cvar_^DA85DK_Q%|xCO3o5?|>%?_47dU+IWBfwVPzJXq+)A*b;PPqW(0A|9
zs|MS-9C+f!la_$rm<TP|lO(8YbxnnIz@{x9!nErLbY?p;x7&3N&1s0)D8!3-`A-Me
zgu!~}DDc!vNm_OQ_v%V^OiA{qt+=~hJ>e-1jVh%`A=E6=TPbatDtn)4jj7J$WZQuB
z?4O?n26-SUgt*aL_~%OXacHb!A9-YDkPpFX>qv?7%itRe14saU=uoUVClnsHiEhU1
zhp)XzoUI;{a_c8?LB%c?h~3iA7PgIBfF7LzzHHh;;i(Df!matLS83&4S9SK#N=qmS
zqlw7<!fe!z$=geXfZ|drmt89tY*_x@VL_0x`O$2{sy^O26f$|2v%`Se!EFBS9@ovZ
zcSD#Sy6BZt%PkcwGB|=<L@5hdXO^6nV-b+7m8`2zzIN-!Xp#EMy%&>gUY+KHROoEW
zGe{Q=+=b!*DQG1QQJdcAVh^ud-`Hz#99A8p_mymt*?-{;G547jxa`B&5UGnH&7|@E
zq&tT;VZ{3JE?R%{#Dr6S=9c6|Pi}5Fd${mKJerSQ`dE=tWbFsz5Tt{mX6ge=P$$)?
zT?iBa)Oubr1E>NAwug3|oya<&D^^vZ3-y0M!%Pe9Ao(n~W(_t3ut&PhG+91fv$hkI
zulfs&4AjKhiSka5r}c8LaBy0UyXMpJ+e<ub%K54Nu?Zm(#b%s<m31V%IA>Z2u|K0O
z!X=*UgG$NfK?_P=@5d`uhI2YQw%Lag;WRaq1uK3L*Vrr~rnRvW5oPKsBaD5fNX*cg
zaLQ=e8?czMiQR0Uc2T8xx!4cTcBJ=aLnkrwd=0$|8gQ{^GI#pTxMex&2t9ixsZUb2
zuA1Cxqcmf)SPuM7Jf=TOz4Oc>AQy$EoY)MH>caw|Q#$Qz@}vD|z=D)5>7WLF)w>^~
z!1+?GeIzN1dZsG>Ps2ojYGp;LCFfTF53YNaZ2|cTspp@5Pe%s#6||NQ2^%yiu+j@$
zkH-<LS=KhY$6Vm++>A!23+H)}Q$dNFVKQFH6n1K=@~3<ZVBI;f0;kF-DNOgX+P~74
zlXfcOYhxhMxA?Wxqr-E=74hNA@u_9k<iqWj=rBrSwxpXpH`;DWepHU|Kb@FA3%*SM
zfF+;t-y8kFBo0T%SY%e8E!yG7Okan?-OM$$9Q%GM3x!s>e}q8M{Pkimx!xCe#aaSv
z|HF{g_7z1Hw(VQVX#z5VL<~6MhAE^4&3s0GVRf8!%(aL0Y5%`7w%Hyg)x>y-UP@bT
z<gG~E1N<xGg;Rj$ES-hVoNA~dg7<u8xXDLEba8BuD2qjXajy5B4F$25sh{uSB1s5%
zUU-^IQUJ*Z;q=N6&q0lws;o2H9r_F3p=p5DPSU$TCf%#LQ(;~<gC986Dee+g_qe<!
zOsz7goOmql6jgLhmU_Wf2;O{2G9he|T>0L;!H_$h6_=^DQv$#)#OK-TLChw1U|Ke0
z;y;-|<l(^P(1SN6J2ji!+{*jWsU@TWs`KiHB8hjkE_zEWCjQNfM`Xil(!fIN#4QtV
zVLWp(@3hY3<KKcjGcH=P;ubB3>inW~rCpIt#eBTsL|=s{&knd}=21fPRS`fu<p^NC
z@z@cliGD=7JBLTNd6Bq&YUIe(iz^^d3R))DMqP3oOTQ{aT0sDA81Y-YT#mBm;^Vj5
zW>>-r{Z}$$yhsMdu%!nofX;+|yn?VGw%?ocPXq#z7Z(+Bm1`+TPlD0gk&tDJHOuH-
z90gO)nxc%j;~+bYIo({pF|gw%g}4(Kjy*|<3kFpa`Ke1>sQu<EJNtjwu>kvPDu{EA
zPkHKq^7jsszZGR{-6TQSR&DblztI_)1<%=SS^C^CrLgSyM-dQ+nQ=XOBwYGW2$GdM
zIwRAT76<(G!wMd>cO}uhRKP8?P~dEt%f2bHJJn<i24WE6z@wN0;OyAkrpzU{&j@@+
zb9A(>nPOTWe0TS;Lj|;6so)bXT21Y=e<PuoG)=9Y$j*)qs!Xbl1p<E~nh>5H0qX-(
zpN9)3NgnTQO}M0OLe3dY-8`}3_wp%W@I1J5%8L_~-&i3;D0!RG6r*6fgzk3}<i^Kt
z9n7x-v*3)sh(dE|vvt8vs2{TYsW@3gegbwcZ4VCqT7iw;m0pBZosUoFp*cI0amk$M
z#3xn{59#r`(SoN+`5lIo%L|&FXPK-=>PLp=CVrwrTH3<)tdU$<5Uj6`pfL-lx>`Jh
zgA7n0h<+tQyPmE%b-y*gk9&%uNQf$Tm)oW$uI3=a(zd)Y!pJ*LcAyFKVr6GrOz#N0
zurpcfI{rm!kG*r2p&bB3XyYUsSy%2BK%qse1MAatyXKa}r?ow+>IV}@thggd|3Y5;
z;K$84EuKGo^we|6_&CxtGr$=`V)&?m_*#4I!2N+n4~>-d!wG*N0tAt_u5k4+C})T^
z@nD+PLW-fCVuH2Z_3e!xCy{}xKhv%pR42h=)Z^R@$~WBd<XZ-1GQMqIUa0Q%o@FF;
z{hM=TgLbt~DbGrZS#Cn6C`|Kqh|WUo^NuIG>g8r5O~gHiXek3H%pB$6&Cx85PTanp
z0^LQp0hf$fqQBYRpPmg|<UJFX3Mlk1Cu7+2ppnz>_5AqIcJv6rTDAMTC<O>1@*@?q
z62h5bLoa&>org2XtDx|oCDDl9>n&xDjjG45>Ah*NlSk=~#5XlfBx=fkM6vTjq`3EO
zQ-^5bn7)z3yrsGEf0)$%O!|(B@{a-5<Ue-TUDEcdNr;7fZTm2kTo+W`q6#kL#^T3$
zH0Q5sP5Xt$Tj*Hd`p@tb`D7mbO=^uAP=<dm*hvkvA(kD|{8KBtNaOOKRYb#fTztGm
zS{yC4Lxm$E%KX|XJtD;$doLe<F@n=^&?f1xl7BXrJ=_@#6BS{JGW26#oE$u><GMym
zNf}Pz`Way?uERdi<$%yRq#LKXR*nn_s)Q@QDb=ck5sAoxW+wSAqxHT#;V9t-I!_-*
zbDBnVNT1M1SI|fG7W)vhnwU}w(8F&?a{#eNB5Pf$$RSwYvg!(&O}?F;4-Ru{?pJ0|
ztUB(z8K`X#a)Z3E$yx`t&+h<R3LIKlM#S@al=Y!3Hdt7y5A%EwtjDk<{xQU6(*Xu_
znSZL|!2i^!Se+{!9ImPALHWUE)Jnw0lgHY#wFo6C%_FN}aI}FKmfCMJxp_0P+-JW^
z&`u)GN$C;K!h#)4tZ^QEVGSM#L9~mu7wr}T9r+_F;Lf-ZJ;-Q>T{Zz}TTZ%}LEY^_
z)o;?<^kB{pW2CehvctWo6Qf{gn7czKwK}rnz%@w9xGe~H&S_#;YEp0l^4+!(@Z}_`
zmgBUMhsCuOffn7F;W<QscY#=dtf4bqr@%p8z-MQJ3mx&Ih&qAW{`d}GGV}_ieG;JD
z|8_62=0qB?1il^MvC%I+pXMra5?{z;G)TOu)k;rbNSyj~%ZzkP!B!B1_+q}o=3Gw}
z{*Z{<86(Y68tsc*tOa$lFx%~82(Hj4&NkKpHjTq7J(<JncCjnMPkd8p(E?m*LK$l&
zK)U$~J=F99Zy>6G6ca2U-+;S*No)N;Zm+t;>deY#O^PQ1iwpwhkg(u~4;iCwg3`je
z^>&-T(c!f$jY6~h;Zmpe(?(qPfe?`J2u$TWL0uqFn|gi`?}NsT#%N$L=6BCv`HKvV
zNEh-KzR&fj0uWHK)^1lrJTZsiV&C(WEz#D*B{*Wkf5;65N{o#GV>8YPoEGr@B%n@d
z9fvr--vLp<bS{=o|C%oLZ{O0Gvec*dGyF#=uh^Y-Xiku%B8+@I^C{4P5?uwI{t<j&
za4)}C+{XAtGGuyP4t%tR39X*6lY8@}FMoe~eLhoqgfF||!i!eJs?#y1mIE9aAjMwB
z9hsVbPkI*G1QBXT?b3*}z<i{Tpy4-i6Ua!tDpIQ1xIHUu<K^w7p5P9c$6B<!5x_zK
zIe>n%V%?f3ORk6lKq$mV=Lnu+fwN}gBKd#KcCPXPx76v?ncbc;PY4E+e*K24^!=K4
zSNul(fjjn@?-L+!;LVx?X;nM^w{ZU2xEd3nK5kmt`ivts7*2_Ucd0leN5V8qY7>Dp
z6ai_ywMv56cFtEpdf=o?qWN{ov?SgC0TE}_2KpRr9_9NCc84UJ&IA#Ou*rCBWZL`-
z2HwQD0jS{5m48!mIB)d7e&dCS;SN`5+^NgTPw51;9quqOWX_@(9TPbR=r9V)1th;w
zaJwG$303~O1>Mh`D0`K^klX;Mn^+rKN2F)_ZmK{~(V4fMf}Iez(dH8HP&E<GN3dUe
zH}+o|7nZEfQ@5j`yL`V1T%q7yZY`3i-aym7-rdSRgJ*qnKKu#(x?)HX0wIf{ue*np
zlE-ys<};YI+D;R+VYu}S^%{e6aYRqO@ss#dh=r79xUYPVkq_@50V~8wD1C-K*l0?O
zY*?~qE<^n&?J7$j<68dt4`a>zVIBum@VwAqJ-mo@CXtEgx#T7i1<Zxdc~=&kSPuU3
zj>{w5@U~FZp>!;-BZ9EBQz&^~8G~GXRvg11%Nb0b_3)=xoNxK$&HjT%#R;71^!=#4
zcp5PSH$iX#GXM@T@I3Y6Ocq}f>}y557A*WK>J^>av~ll59r{yjgeSBJceya*+fbd3
zo8}}sA!IK<RVQ5izw?2Sp+1CetglF}6OpQP*l#|bJTHI$hopbcMlzw<CwyGfJKinA
z6ls`pZQs=iwNa`A=g=AxciNZwkVp#vIS5($VKo1$LHVI0)6nlp4SMG<vc8(^sHBAu
z;uXF}q^9JUnf(9m5NCRVmPeo>{jBn>c2&W(n}&)U!=j>F)Kf5L(sC3~*UC-eP9@|q
zji|29f<HF2CB`Z;-N^?NE^~<mPObp)y65v!^b4b5j2R?FDl>sJQnzm00)1&ve-TvE
zzr&s=2;FY87PofiWQ{#3oyCX?`zz6k0wOSXY0_M8pX%ZRtpEdWO`@V&>3>q6$9qSk
zL155r!r03nEdo&l1eqY9AW?ly4!ZPC;#&&w(;;xjfd$;PbrD;TnVlHa<EObBw^53U
z;Xbm7ifR^4+A3+(wKy(NPh=%fS2#`+_aQz&L`*!$G-Tiz2Vn$UD?{Dc!x61}lGmHV
zET5zpRT;5ov8tDUH){K2sk;T@bZ=4(d3xagJ6i9$=!1W(1N{TA2TW*+&jzu(;ki~V
zmoN^NOQ8?^Y^i_(1>(0fxRPXxbLWGxSc}M@xr8cpfI}A|0tC_~TjKD~V%FD{ElUTQ
zAwC2tU3-(+lanFsZWQq!z+9~Ctnmq7${z|@recck@hqU{ih+GJr22#Na_PB%{lbbY
zG8_WqQ~l1<Y{Lw4`Fhn0B%wOYsr*Kh5^nOF@TqLrebRf!7jYZOc)sZoXWu|N?Id_<
zRP@#)Hj|#5)Wg%wlPkewu|$qr6Xma<?sc3lWG^qzz4o*5w#S_rZWdco{M$xlY2g?D
zv7}tX6C2kaP`qH>gsrB&^!-!#eq0t8=hf;G^;P`*o%6~=$>N1T|0PG!T(gyDgf#&f
z23S>f$A%C`7aoSqEaSZ^LE0=SqR01WFiiIQN-a{ebH*1h@I9}~6nmVje61GWclJ5j
zFC&3@N5`<$zN`aW)s%))M<r@#NEj#~KGA}c$>Z7{r*oTy8qfyZrO1VOpa&D)jyPL^
z56DeIN1dN9RXScC^k%F(=pWvqpWL_`V#Hi>k}Ca++ZZ;DY|7T3tS#qSbX+|L=L#7N
z?Y>WVBv<MDE0)uwF$DSK^E7LkDoda*vG@4YbD_G+Kn>bkv6~@8pjfNAn%}066c4N-
zE2=j(-~s`afo!tLKT88KNRmy+2B#xQim-sadU;cry-vwTNZ~hCiQmEZ>{|2vyX!US
zFtqMhj&-EGln;+yuvULGaCEk>qYF&4+qnh<Dvx4kEa6gicE+*fUZW#>wibeGbRopi
zY_oG3!&SP1dN|C5O<5P~>Yrsn@$&P8be(xde9&sze1)a#VINeQfIqI<{OC)EKOsLz
zSL)F!O2>y$jAl~MGAX%&<BlGP6HU+z&vNU*on^}o@6p;!)S1*`9qMdRL2jh8N4fp>
zptG>mlhgsyQS!;7B+j-9eMER=cs8OvoI^z4fXCV8(Nt%KChyY|ph6~dku`s<v!)rx
z1FWWmv_MuMjXgW31)rK15feS1pL0}(PiWQB-$oyG0e*hyA7u%S;5dDVR2cUP>f`&B
zv4lU1;kdVaD}N3;T=o^wFdbx3y6W%NVBdXQLWE3>D%D-&N1~TE6OU<5t0L5>bvmHG
z?re>i-T)gkjntVgzVrm#t@r$x<U$yMb8zgb*{+5`T$fWKeg|Mt#}mI<Y%JS1#WFge
z#AFU?9zOu?`7HtXLxw)z?X|VY&al-SnlI64)hGr-wZB~0Z?QFuv!1f%#xXSfVll_y
zD#9R}xEb;pp3rNMeuW;|9p0P!M#68o#K|-@itv2WSJ$q#Af<ER*X9(2si-h)NAr)F
zj=XVt&;4ArDL|mqG&?mB6u)?l7(lZJZM$ZgOFCprf*{B?=DtAhmTi5$Fof9ESCWI&
z=Ou!tQu}@6X7HQQ7-q6a%EN1r2ozCkw9NL38$WAQ5e!5P0NP3($%GvJ;c@*uBl@|@
OOMM$*rMt^|w{lDe=}pK0

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv b/FPGA_firmware/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv
new file mode 100644
index 0000000..1c0d086
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv
@@ -0,0 +1,335 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_burst_adapter/new_source/altera_wrap_burst_converter.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------------------
+// This component is specially for Wrapping Avalon slave.
+// It converts burst length of input packet
+// to match slave burst.
+// ------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_wrap_burst_converter
+#(
+  parameter
+    // ----------------------------------------
+    // Burst length Parameters
+    // (real burst length value, not bytecount)
+    // ----------------------------------------
+    MAX_IN_LEN              = 16,
+    MAX_OUT_LEN             = 4,
+    ADDR_WIDTH              = 12,
+    BNDRY_WIDTH             = 12,
+    NUM_SYMBOLS             = 4,
+    AXI_SLAVE               = 0,
+    OPTIMIZE_WRITE_BURST    = 0,
+    // ------------------
+    // Derived Parameters
+    // ------------------
+    LEN_WIDTH       = log2ceil(MAX_IN_LEN) + 1,
+    OUT_LEN_WIDTH   = log2ceil(MAX_OUT_LEN) + 1,
+    LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
+)
+(
+    input                           clk,
+    input                           reset,
+    input                           enable_write,
+    input                           enable_read,
+
+    input [LEN_WIDTH   - 1 : 0]     in_len,
+    input [LEN_WIDTH   - 1 : 0]     first_len,
+    input                           in_sop,
+
+    input [ADDR_WIDTH  - 1 : 0]     in_addr,
+    input [ADDR_WIDTH  - 1 : 0]     in_addr_reg,
+    input [BNDRY_WIDTH - 1 : 0]     in_boundary,
+    input [BNDRY_WIDTH - 1 : 0]     in_burstwrap,
+    input [BNDRY_WIDTH - 1 : 0]     in_burstwrap_reg,
+
+    // converted output length
+    // out_len         : compressed burst, read
+    // uncompressed_len: uncompressed, write
+    output reg [LEN_WIDTH - 1 : 0]  out_len,
+    output reg [LEN_WIDTH - 1 : 0]  uncompr_out_len,
+
+    // Compressed address output
+    output reg [ADDR_WIDTH - 1 : 0] out_addr,
+    output reg                      new_burst_export
+);
+
+    // ------------------------------
+    // Local parameters
+    // ------------------------------
+    localparam
+        OUT_BOUNDARY        = MAX_OUT_LEN * NUM_SYMBOLS,
+        ADDR_SEL            = log2ceil(OUT_BOUNDARY);
+
+    // ----------------------------------------
+    // Signals for wrapping support
+    // ----------------------------------------
+    reg [LEN_WIDTH - 1 : 0]        remaining_len;
+    reg [LEN_WIDTH - 1 : 0]        next_out_len;
+    reg [LEN_WIDTH - 1 : 0]        next_rem_len;
+    reg [LEN_WIDTH - 1 : 0]        uncompr_remaining_len;
+    reg                            new_burst;
+    reg                            uncompr_sub_burst;
+    reg [LEN_WIDTH - 1 : 0]        next_uncompr_out_len;
+    reg [LEN_WIDTH - 1 : 0]        next_uncompr_sub_len;
+
+    // Avoid QIS warning
+    wire [OUT_LEN_WIDTH - 1 : 0]   max_out_length;
+    assign max_out_length  = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
+
+    // ----------------------------------------
+    // Calculate aligned length for WRAP burst
+    // ----------------------------------------
+    reg [ADDR_WIDTH - 1 : 0]       extended_burstwrap;
+    reg [ADDR_WIDTH - 1 : 0]       extended_burstwrap_reg;
+
+    always_comb begin
+        extended_burstwrap      = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap[BNDRY_WIDTH - 1]}}, in_burstwrap};
+        extended_burstwrap_reg  = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap_reg[BNDRY_WIDTH - 1]}}, in_burstwrap_reg};
+        new_burst_export        = new_burst;
+    end
+
+    // -------------------------------------------
+    // length calculation
+    // -------------------------------------------
+    reg [LEN_WIDTH -1 : 0] next_uncompr_remaining_len;
+    always_comb begin
+        // Signals name
+        // *_uncompr_* --> uncompressed transaction
+        // -------------------------------------------
+        // Always use max_out_length as possible.
+        // Else use the remaining length.
+        // If in length smaller and not cross bndry or same, pass thru.
+
+        if (in_sop) begin
+            uncompr_remaining_len = in_len;
+        end
+        else begin
+            uncompr_remaining_len = next_uncompr_remaining_len;
+        end
+    end // always_comb
+
+    // compressed transactions
+    always_comb begin : proc_compressed_read
+        remaining_len  = in_len;
+        if (!new_burst)
+            remaining_len = next_rem_len;
+    end
+
+    always_comb begin
+        next_uncompr_out_len = first_len;
+        if (in_sop) begin
+            next_uncompr_out_len = first_len;
+        end
+        else begin
+            if (uncompr_sub_burst)
+                next_uncompr_out_len = next_uncompr_sub_len;
+            else begin
+                if (uncompr_remaining_len < max_out_length)
+                    next_uncompr_out_len = uncompr_remaining_len;
+                else
+                    next_uncompr_out_len = max_out_length;
+            end
+        end
+    end
+
+    // Compressed transaction: Always try to send MAX out_len then remaining length.
+    // Seperate it as the main difference is the first out len.
+    // For a WRAP burst, the first beat is the aligned length, then similar to INCR.
+    always_comb begin
+        if (new_burst) begin
+            next_out_len = first_len;
+        end
+        else begin
+            next_out_len = max_out_length;
+            if (remaining_len < max_out_length) begin
+                next_out_len = remaining_len;
+            end
+        end
+    end // always_comb
+
+    // --------------------------------------------------
+    // Length remaining calculation : Compressed
+    // --------------------------------------------------
+    // length remaining for compressed transaction
+    // for wrap, need special handling for first out length
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset)
+            next_rem_len  <= 0;
+        else if (enable_read) begin
+            if (new_burst)
+                next_rem_len <= in_len - first_len;
+            else
+                next_rem_len <= next_rem_len - max_out_length;
+        end
+    end // always_ff @
+
+    // --------------------------------------------------
+    // Length remaining calculation : Uncompressed
+    // --------------------------------------------------
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            next_uncompr_remaining_len  <= 0;
+        end
+        else if (enable_write) begin
+            if (in_sop)
+                next_uncompr_remaining_len  <= in_len - first_len;
+            else if (!uncompr_sub_burst)
+                next_uncompr_remaining_len  <= next_uncompr_remaining_len - max_out_length;
+        end
+    end // always_ff @
+
+    // length for each sub-burst if it needs to chop the burst
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            next_uncompr_sub_len  <= 0;
+        end
+        else if (enable_write) begin
+            next_uncompr_sub_len  <= next_uncompr_out_len - 1'b1; // in term of length, it just reduces 1
+        end
+    end
+
+    // the sub-burst still active
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            uncompr_sub_burst <= 0;
+        end
+        else if (enable_write) begin
+            uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
+        end
+    end
+
+    // --------------------------------------------------
+    // Control signals
+    // --------------------------------------------------
+    wire end_compressed_sub_burst;
+    assign end_compressed_sub_burst  = (remaining_len == next_out_len);
+
+    // new_burst:
+    //  the converter takes in_len for new caculation
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            new_burst   <= 1;
+        end
+        else if (enable_read) begin
+            new_burst   <= end_compressed_sub_burst;
+        end
+    end
+
+    // --------------------------------------------------
+    // Output length
+    // --------------------------------------------------
+    // register out_len for compressed trans
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            out_len <= 0;
+        end
+        else if (enable_read) begin
+            out_len <= next_out_len;
+        end
+    end
+    
+    // register uncompr_out_len for uncompressed trans
+    generate
+        if (OPTIMIZE_WRITE_BURST) begin : optimized_write_burst_len
+            always_ff @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    uncompr_out_len <= '0;
+                end
+                //else if (enable_write) begin
+                else if (enable_read) begin
+                    uncompr_out_len <= first_len;
+                end
+            end
+        end
+        else begin : unoptimized_write_burst_len
+            always_ff @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    uncompr_out_len <= '0;
+                end
+                else if (enable_write) begin
+                    uncompr_out_len <= next_uncompr_out_len;
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Address calculation
+    // --------------------------------------------------
+    reg [ADDR_WIDTH - 1 : 0]        addr_incr;
+    localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
+    assign addr_incr  = ADDR_INCR[ADDR_WIDTH - 1 : 0];
+
+    reg [ADDR_WIDTH - 1 : 0]    next_out_addr;
+    reg [ADDR_WIDTH - 1 : 0]    incremented_addr;
+
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            out_addr <= '0;
+        end
+        else begin
+            if (enable_read) begin
+                out_addr <=  (next_out_addr);
+            end
+        end
+    end // always_ff @
+
+    // use burstwrap/burstwrap_reg to calculate address incrementing
+    always_ff @(posedge clk, posedge reset) begin
+        if (reset) begin
+            incremented_addr <= '0;
+        end
+        else if (enable_read) begin
+            incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
+            if (new_burst) begin
+                incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap); //byte address
+            end
+        end
+    end // always_ff @
+
+    always_comb begin
+        next_out_addr  = in_addr;
+        if (!new_burst) begin
+            next_out_addr = in_addr_reg & ~extended_burstwrap_reg | incremented_addr;
+        end
+    end
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/bkg.sv b/FPGA_firmware/q_sys/synthesis/submodules/bkg.sv
new file mode 100644
index 0000000..79de502
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/bkg.sv
@@ -0,0 +1,106 @@
+
+/*
+The ram provides the background signal.
+when frameID is 1, reset ram content to 0
+frameID is 2~1+TOTAL_FRAME, sum the signal store in the ram
+when rameID is TOTAL_FRAME+2, output the background signal
+The TOTAL_FRAME has to be the power of 2, and it belongs to [2,65536]
+In general, TOTAL_FRAME = 8192
+*/
+
+module bkg_ram #(parameter TOTAL_FRAME = 4)
+(
+
+	input wire clk_clk,
+	input wire rst_reset,
+	
+	input wire[26:0] frameID,
+	input wire [7:0] address, 
+	input  wire [15:0] data_in_data,
+	output wire [15:0] bkg_signal,
+	output wire bkg_sub_status
+	); 
+
+	
+	wire wren_sig;
+	wire[31:0] q_sig;
+	wire[31:0] data_sig;
+	reg[7:0] wraddress_sig[3]; //delay address 3 clocks
+	reg[31:0] reg_sum;
+	reg[15:0] reg_data_in[2]; //delay data_in_data 2 clocks
+
+//	localparam TOTAL_FRAME = 8192; //2^13= 8192
+//	localparam SHIFG_BIT = 13; 
+	
+	//for fast simulation
+	//localparam TOTAL_FRAME = 4; //2^2= 4
+	localparam SHIFT_BIT = $clog2(TOTAL_FRAME); 
+	
+	ram4bkg ram4bkg_inst (
+    .data(data_sig),
+    .rdaddress(address),
+    .clock(clk_clk),
+    .wraddress(wraddress_sig[0]),
+    .wren(wren_sig),
+    .q(q_sig)
+  );
+
+  
+  reg[1:0] states;
+  localparam STATE_IDLE = 0;
+  localparam STATE_RAM_RST = 1;
+  localparam STATE_BKG_ADD = 3;
+  localparam STATE_BKG_OUT = 2;
+  
+  assign bkg_sub_status = (states==STATE_BKG_OUT)? 1'b1:1'b0;
+  
+  always @(posedge clk_clk or posedge rst_reset)
+  begin
+   if (rst_reset)
+		states <= STATE_IDLE;
+	else if (frameID <=27'd1)
+		states <= STATE_RAM_RST;
+	else if (frameID >TOTAL_FRAME+1)
+		states <= STATE_BKG_OUT;
+	else 
+		states <= STATE_BKG_ADD;
+	end
+		
+	assign bkg_signal = (states==STATE_BKG_OUT)?q_sig[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+   assign wren_sig = (states==STATE_RAM_RST || states==STATE_BKG_ADD)? 1'b1: 1'b0;
+	assign data_sig = (states==STATE_BKG_ADD)? reg_sum: 0;
+	
+	
+	always @(posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			reg_sum <= 0;
+			reg_data_in[1] <= 0;
+			wraddress_sig[0] <= 0;
+			wraddress_sig[1] <= 0;
+			wraddress_sig[2] <= 0;
+		end
+		else 
+			case(states)
+				STATE_IDLE:
+				begin
+					reg_sum <= 0;
+					reg_data_in[1] <= 0;
+				end
+				STATE_BKG_ADD:
+				begin
+					reg_data_in[1] <= data_in_data;
+					reg_data_in[0] <= reg_data_in[1];
+					reg_sum <= q_sig + reg_data_in[0];
+					wraddress_sig[2] <= address;
+					wraddress_sig[1] <= wraddress_sig[2];
+					wraddress_sig[0] <= wraddress_sig[1];
+				end
+				STATE_RAM_RST:
+					wraddress_sig[0] <= address;
+			endcase
+	end
+	
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/bkg_subtraction_pipe.v b/FPGA_firmware/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
new file mode 100644
index 0000000..cbc6521
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
@@ -0,0 +1,312 @@
+//background subtraction module
+
+//tested with algo_top_cl_cali_tb.v with bkg_subtraction_pipe
+//tested with bkg_subtraction_pipe_tb
+
+//okay... it is not really pipe.... has to read a ram after use the previous output of this ram 
+
+module bkg_subtraction_pipe #(parameter BKG_FRAME = 4)(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
+	output  wire [31:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket,  //         .startofpacket	
+	
+	output wire				bkg_sub_on,
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //3 headers 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it?  26.June. 2024
+);
+	localparam SHIFT_BIT = $clog2(BKG_FRAME); 
+	
+	wire rst_frame = data_in_startofpacket; 
+	
+	wire data_out_ready_for3header = to_udp_ready;
+	
+	/************************* Frame Counter***********************************/
+	/*
+	This is a frame counter; 
+	frameID +1 at the rising edge of data_in_startofpacket
+	if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
+	*/
+	reg [26:0] frameID;
+	reg data_in_startofpacket_last;
+	
+	always @(posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			data_in_startofpacket_last <= 1'b0;
+			frameID<= 27'b0;
+		end
+		else 
+		begin
+			data_in_startofpacket_last <= data_in_startofpacket;
+			if (~data_in_startofpacket_last && data_in_startofpacket)
+				frameID<= frameID + 1'b1; 
+		end
+	end
+	
+	//**********************bkg_subtraction or not *****************
+	
+  reg[1:0] state_bkg;
+  localparam STATE_BKG_IDLE = 0;
+  localparam STATE_RAM_RST = 1;
+  localparam STATE_BKG_ADD = 3;
+  localparam STATE_BKG_OUT = 2;
+  
+  assign bkg_sub_on = (state_bkg == STATE_BKG_OUT)? 1'b1:1'b0;
+  
+  always @(posedge clk or posedge rst)
+  begin
+   if (rst)
+		state_bkg <= STATE_BKG_IDLE;
+	else if (frameID <=27'd1)
+		state_bkg <= STATE_RAM_RST;
+	else if (frameID >BKG_FRAME+1)
+		state_bkg <= STATE_BKG_OUT;
+	else 
+		state_bkg <= STATE_BKG_ADD;
+	end
+	
+	
+	
+	/************** bkg RAM ****************************/
+	/*
+	for prepare the bkg signal by two RAM;
+	one for data_in_data[31:16]; the other for data_in_data[15:0]
+	the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
+	*/
+	
+	reg[8:0] rdaddress; //for read ram
+	reg[8:0] wraddress;
+	wire		wren;
+	
+	//data_in_data + ram0_q
+	reg[31:0] ram0_data;
+	reg[31:0] ram1_data;
+	
+	wire[31:0] ram0_q;
+	wire[31:0] ram1_q;
+	
+	
+	
+	ram4bkg ram4bkg0 (
+    .data(ram0_data), //32 bits
+    .rdaddress(rdaddress),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram0_q) //32 bits
+  );
+  
+  ram4bkg ram4bkg1 (
+    .data(ram1_data), //32 bits
+    .rdaddress(rdaddress),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram1_q) //32 bits
+  );
+	
+	wire[15:0] bkg0;
+	wire[15:0] bkg1;
+	
+	assign bkg0 = bkg_sub_on?ram0_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	assign bkg1 = bkg_sub_on?ram1_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	
+
+	
+	//data_in_data - bkg0
+	reg[16:0] data0_sub;
+	reg[16:0] data1_sub;
+	
+	//data_in_data
+	wire[15:0] data0_in_data;
+	wire[15:0] data1_in_data;
+	
+	//reverse the polarity of ADC signal for calculation => no for simulation
+	assign data0_in_data = ~data_in_data[31:16];
+	assign data1_in_data = ~data_in_data[15:0];
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[3:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 4'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 4'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 4'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 4'd3;	//sending third word :
+	localparam STATE_RDRAM0 = 4'd4; //wait to read the first channel of ram
+	localparam STATE_INPUT0 = 4'd5; //data_in_ready do sub and sum
+	localparam STATE_RDRAM1 = 4'd6; //data_in_data is ready to output, data_out_startofpacket is high; read next ram
+	localparam STATE_INPUT = 4'd7; //data_in_ready do sub and sum for next
+	localparam STATE_RDRAM = 4'd8;
+	localparam STATE_OUTPUT_LAST = 4'd9; //output last, data_out_endofpacket is high
+	localparam STATE_LOC	= 4'd10;	//
+
+	
+	wire state_bkg_valid;
+	wire state_data_valid;
+	// Check if state_bkg is either STATE_RAM_RST or STATE_BKG_ADD for write
+	assign state_bkg_valid = (state_bkg == STATE_RAM_RST) || (state_bkg == STATE_BKG_ADD);
+	// Check if state is STATE_DATA and both data_in_valid and data_out_ready are true
+	assign state_data_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST);
+
+	// Final wren assignment combining the conditions
+	assign wren = (state_bkg_valid && state_data_valid)? 1'b1 : 1'b0;
+
+	
+	
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					rdaddress <= 0;
+					wraddress <= 0; 
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+					end
+				end
+				STATE_WORD0:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD1;
+					end
+				end
+				STATE_WORD1:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD2;
+					end
+				end
+				STATE_WORD2:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_RDRAM0;
+						rdaddress <= 0;
+					end
+				end
+				STATE_RDRAM0:
+				begin
+					state <= STATE_INPUT0;
+				end
+				STATE_INPUT0:
+				begin
+					if (data_in_valid)
+					begin
+						state <= STATE_RDRAM1;
+						rdaddress <= rdaddress + 1'b1;
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+					end
+				end
+				STATE_RDRAM1:
+				begin
+				if (data_out_ready)
+					state <= STATE_INPUT;
+				end
+				STATE_INPUT:
+				begin
+					if (data_in_valid)
+					begin
+						if (data_in_endofpacket)
+							state <= STATE_OUTPUT_LAST;
+						else
+							state <= STATE_RDRAM;
+						rdaddress <= rdaddress + 1'b1;
+						wraddress <= wraddress + 1'b1;
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+					end
+				end
+				STATE_RDRAM:
+				begin
+					if (data_out_ready)
+						state <= STATE_INPUT;
+				end
+				STATE_OUTPUT_LAST:
+				begin
+					if (data_out_ready)
+						state <= STATE_LOC;
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+
+	//output 160 words
+	assign data_in_ready = ((state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) && data_out_ready_for3header) || (state == STATE_INPUT) ||(state == STATE_INPUT0); 
+	assign data_out_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0; 
+	assign data_out_data = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST)? (bkg_sub_on? {data0_sub[16:1],data1_sub[16:1]}: {data0_sub[15:0],data1_sub[15:0]}):0;
+	assign data_out_startofpacket = (state == STATE_RDRAM1)? 1'b1: 1'b0;
+	assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;
+   assign data_out_empty = 0;	
+
+	//output the 3 header to upd
+	assign to_udp_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:0;
+	assign to_udp_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_valid: 1'b0;
+	assign to_udp_empty = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_empty: 2'b0;
+	assign to_udp_startofpacket = data_in_startofpacket;
+	assign to_udp_endofpacket = (state == STATE_WORD2)?data_in_valid: 1'b0;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/byte_enable_generator.v b/FPGA_firmware/q_sys/synthesis/submodules/byte_enable_generator.v
new file mode 100644
index 0000000..2d5e2bf
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/byte_enable_generator.v
@@ -0,0 +1,838 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+
+  This logic recieves a potentially unsupported byte enable combination and
+  breaks it down into supported byte enable combinations to the fabric.
+  
+  For example if a 64-bit write master wants to write
+  to addresses 0x1 and beyond, this maps to address 0x0 with byte enables
+  "11111110" asserted.  This does not contain a power of two of neighbooring
+  asserted bits.  Instead this block will convert this into three writes
+  all of which are supported:  "00000010", "00001100", and "11110000".  When
+  this block breaks a transfer down it asserts stall so that the rest of the
+  master logic will keep the outputs constant.
+  
+  Revision History:
+  
+  1.0  Initial version - Used a word distance to calculate which lanes to enable.
+  
+  1.1  Re-encoded version - Uses byte enables directly to calculate which lanes
+                            to enable.  This allows byte enables in the middle
+                            of a word to be supported as well such as '0110'.
+
+  1.2  Bug fix to include the waitrequest for state transitions when the byte
+       enable width is greater than 2.
+
+  1.3  Added support for 64 and 128-bit byte enables (for 512/1024 bit data paths)
+
+*/
+
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+
+module byte_enable_generator (
+  clk,
+  reset,
+
+  // master side
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  // fabric side
+  byteenable_out,
+  waitrequest_in
+);
+
+  parameter BYTEENABLE_WIDTH = 4;   // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
+
+  input clk;
+  input reset;
+
+  input write_in;                              // will enable state machine logic
+  input [BYTEENABLE_WIDTH-1:0] byteenable_in;  // byteenables from master which contain unsupported groupings of byte lanes to be converted
+  output wire waitrequest_out;                 // used to stall the master when fabric asserts waitrequest or access needs to be broken down
+
+  output wire [BYTEENABLE_WIDTH-1:0] byteenable_out;   // supported byte enables to the fabric
+  input waitrequest_in;                                // waitrequest from the fabric
+
+
+generate
+  if (BYTEENABLE_WIDTH == 1)  // for completeness...
+  begin
+      assign byteenable_out = byteenable_in;
+      assign waitrequest_out = waitrequest_in;
+  end
+  else if (BYTEENABLE_WIDTH == 2)
+  begin
+      sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM (   // pass through for the most part like the 1 bit case, has it's own module since the 4 bit module uses it
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );  
+  end
+  else if (BYTEENABLE_WIDTH == 4)
+  begin
+      thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM(
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );  
+  end
+  else if (BYTEENABLE_WIDTH == 8)
+  begin
+      sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM(
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );  
+  end
+  else if (BYTEENABLE_WIDTH == 16)
+  begin
+      one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM(
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );  
+  end
+  else if (BYTEENABLE_WIDTH == 32)
+  begin
+      two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM(
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );
+  end
+  else if (BYTEENABLE_WIDTH == 64)
+  begin
+      five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );
+  end
+  else if (BYTEENABLE_WIDTH == 128)
+  begin
+      one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
+        .clk (clk),
+        .reset (reset),
+        .write_in (write_in),
+        .byteenable_in (byteenable_in),
+        .waitrequest_out (waitrequest_out),
+        .byteenable_out (byteenable_out),
+        .waitrequest_in (waitrequest_in)
+      );
+  end
+endgenerate
+
+endmodule
+
+
+
+
+
+module one_thousand_twenty_four_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+  input clk;
+  input reset;
+
+  input write_in;
+  input [127:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [127:0] byteenable_out; 
+  input waitrequest_in;
+
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[63:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF);
+  assign partial_upper_half_transfer = (byteenable_in[127:64] != 0);
+  assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[63:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[63:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[127:64]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[127:64]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+
+
+
+module five_hundred_twelve_bit_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+
+  input clk;
+  input reset;
+
+  input write_in;
+  input [63:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [63:0] byteenable_out; 
+  input waitrequest_in;
+
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[31:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF);
+  assign partial_upper_half_transfer = (byteenable_in[63:32] != 0);
+  assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[31:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[31:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[63:32]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[63:32]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+
+
+module two_hundred_fifty_six_bit_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+
+  input clk;
+  input reset;
+
+  input write_in;
+  input [31:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [31:0] byteenable_out; 
+  input waitrequest_in;
+
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
+  assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
+  assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[15:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[15:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[31:16]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[31:16]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+
+module one_hundred_twenty_eight_bit_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+
+  input clk;
+  input reset;
+
+  input write_in;
+  input [15:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [15:0] byteenable_out; 
+  input waitrequest_in;
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[7:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF);
+  assign partial_upper_half_transfer = (byteenable_in[15:8] != 0);
+  assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[7:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[7:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[15:8]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[15:8]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+
+module sixty_four_bit_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+
+  input clk;
+  input reset;
+  
+  input write_in;
+  input [7:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [7:0] byteenable_out; 
+  input waitrequest_in;
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[3:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF);
+  assign partial_upper_half_transfer = (byteenable_in[7:4] != 0);
+  assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[3:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[3:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM (
+    .clk (clk),
+    .reset (reset),
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[7:4]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[7:4]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+module thirty_two_bit_byteenable_FSM (
+  clk,
+  reset,
+
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+
+  input clk;
+  input reset;
+
+  input write_in;
+  input [3:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [3:0] byteenable_out; 
+  input waitrequest_in;
+
+
+  // internal statemachine signals
+  wire partial_lower_half_transfer;
+  wire full_lower_half_transfer;
+  wire partial_upper_half_transfer;
+  wire full_upper_half_transfer;
+  wire full_word_transfer;
+  reg state_bit;
+  wire transfer_done;
+  wire advance_to_next_state;
+  wire lower_enable;
+  wire upper_enable;
+  wire lower_stall;
+  wire upper_stall;
+  wire two_stage_transfer;
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      state_bit <= 0;
+    end
+    else
+    begin
+      if (transfer_done == 1)
+      begin
+        state_bit <= 0;
+      end
+      else if (advance_to_next_state == 1)
+      begin
+        state_bit <= 1;
+      end
+    end
+  end
+
+  assign partial_lower_half_transfer = (byteenable_in[1:0] != 0);
+  assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3);
+  assign partial_upper_half_transfer = (byteenable_in[3:2] != 0);
+  assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3);
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);  // partial lower half transfer completed and there are bytes in the upper half that need to go out still
+
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
+                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
+                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));  // partial upper and lower half transfers complete
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));  // partial lower half transfer (to be followed by an upper half transfer)
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |  // full word transfer
+                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
+                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));  // partial upper half transfer (after the lower half transfer)
+
+  sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM (
+    .write_in (lower_enable),
+    .byteenable_in (byteenable_in[1:0]),
+    .waitrequest_out (lower_stall),    
+    .byteenable_out (byteenable_out[1:0]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM (
+    .write_in (upper_enable),
+    .byteenable_in (byteenable_in[3:2]),
+    .waitrequest_out (upper_stall),    
+    .byteenable_out (byteenable_out[3:2]),
+    .waitrequest_in (waitrequest_in)
+  );
+
+  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+
+
+/**************************************************************************************************
+  Fundament byte enable state machine for which 32, 64, 128, 256, 512, and 1024 bit byte enable
+  statemachines will use to operate on groups of two byte enables.
+***************************************************************************************************/
+module sixteen_bit_byteenable_FSM (
+  write_in,
+  byteenable_in,
+  waitrequest_out,
+
+  byteenable_out,
+  waitrequest_in
+);
+
+ 
+  input write_in;
+  input [1:0] byteenable_in;
+  output wire waitrequest_out;
+
+  output wire [1:0] byteenable_out; 
+  input waitrequest_in;
+
+  assign byteenable_out = byteenable_in & {2{write_in}};          // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled
+  assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1);  // transfer always completes on the first cycle unless waitrequest is asserted
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/cali_ram_cali_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/cali_ram_cali_ram.v
new file mode 100644
index 0000000..c217881
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/cali_ram_cali_ram.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module cali_ram_cali_ram (
+                           // inputs:
+                            address,
+                            address2,
+                            byteenable,
+                            byteenable2,
+                            chipselect,
+                            chipselect2,
+                            clk,
+                            clk2,
+                            clken,
+                            clken2,
+                            freeze,
+                            reset,
+                            reset2,
+                            reset_req,
+                            reset_req2,
+                            write,
+                            write2,
+                            writedata,
+                            writedata2,
+
+                           // outputs:
+                            readdata,
+                            readdata2
+                         )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  8: 0] address;
+  input   [  8: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 320,
+           the_altsyncram.numwords_a = 320,
+           the_altsyncram.numwords_b = 320,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 9,
+           the_altsyncram.widthad_b = 9,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/calibration.v b/FPGA_firmware/q_sys/synthesis/submodules/calibration.v
new file mode 100644
index 0000000..568dfbc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/calibration.v
@@ -0,0 +1,233 @@
+//module calibration has two functions: calibration and merge 16-bit stream to 32-bit stream and then output
+//calibration output 16-bit data_caled
+//a better design is a design seperate these two functions
+//tested by calibration_tb 25.07.2024
+
+module calibration
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input  wire signed[15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	output wire [8:0] 	address,
+	output wire 			clken, //read
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest,
+	
+	//the interface for provide the calibrated data in a ram // one clock latency
+	input  wire [8:0]			data_caled_address,
+	output wire [15:0]		data_caled,
+	input  wire					data_caled_rd_enable, // to enable read
+	
+	output wire					data_in_last, //....
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 * 32 bits data  
+	// channel 0 [31:16] channel 1 [15:0]
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	localparam SHIFT_BIT = 13; //2^13 = 8192, the calibration factor 1 is represented by 8192 
+	
+	//for to_udp_data
+	reg [15:0] first_data_buffer;
+	
+	//for read calibration ram
+	reg [8:0]  	read_cali_address;
+	reg signed[16:0]   cali_fac_buffer;
+	wire read;
+	assign clken = read;
+	assign address = read_cali_address;
+	
+	//for write and read the calibrated data
+	reg signed[31:0]	data_caled_data_32bit;
+	wire 			data_caled_wren_a;
+	reg [8:0]	data_caled_address_a;
+	wire [8:0]	address_b;
+	assign		address_b = (data_caled_rd_enable)? data_caled_address: 9'd0;
+	wire[15:0]	data_caled_data_a;
+	assign data_caled_data_a = {data_caled_data_32bit[31],data_caled_data_32bit[14+SHIFT_BIT:SHIFT_BIT]};
+	
+	
+	data_caled_ram	data_caled_ram0 (
+		
+		.clock ( clk ),
+		
+		.address_a (data_caled_address_a),
+		.data_a (data_caled_data_a),
+		.wren_a (data_caled_wren_a),
+		.q_a ( ),
+
+		.address_b ( address_b ),
+		.data_b ( ),
+		.wren_b (1'b0),
+		.q_b ( data_caled)
+		);
+		
+	//the state machine for read calibration factor from ram
+	reg[3:0] state;
+	localparam STATE_IDLE = 4'd0; //waiting for startofpacket
+	localparam STATE_CAL0 = 4'd1; //get califactor for channel0
+	localparam STATE_INPUT0 = 4'd2; // stream in data for channel0;
+	localparam STATE_CAL1 = 4'd3; // get califactor for channel1
+	localparam STATE_INPUT1 = 4'd4; // stream in data for channel1;
+	localparam STATE_CAL2 = 4'd5; //get califactor for channel1; output the first 32-bit udp data [channel0, channel1]
+	localparam STATE_INPUT_EVEN = 4'd6; // stream in data for channel 2,4,6.....
+	localparam STATE_CAL_ODD = 4'd7; 
+	localparam STATE_INPUT_ODD = 4'd8;
+	localparam STATE_CAL_EVEN = 4'd9;
+	localparam STATE_OUTPUT_LAST = 4'd10; //outout the last 32-bit udp data 
+	
+
+	assign data_in_ready = (state == STATE_INPUT0 || state == STATE_INPUT1 || state == STATE_INPUT_EVEN || state == STATE_INPUT_ODD)?1'b1:1'b0;
+	assign data_caled_wren_a = (state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD || state == STATE_OUTPUT_LAST)?1'b1:1'b0;
+	assign read = (state == STATE_CAL0 ||state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD)?1'b1:1'b0;
+	
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			data_caled_address_a <= 0;
+			read_cali_address <= 0; 
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			data_caled_address_a <= 0;
+			read_cali_address <= 0; 
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_CAL0;
+			end
+		end
+		STATE_CAL0:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT0;
+			end
+		end
+		STATE_INPUT0:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= 16'd0;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				state <= STATE_CAL1;
+			end
+		end
+		STATE_CAL1:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT1;
+			end
+		end
+		STATE_INPUT1:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= data_caled_data_a;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				state <= STATE_CAL2;
+			end
+		end
+		STATE_CAL2:
+		begin
+			if (~waitrequest & to_udp_ready) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_EVEN;
+			end
+		end
+		STATE_INPUT_EVEN:
+		begin
+			if (data_in_valid) 
+			begin
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				first_data_buffer <= 16'd0;
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				if (data_in_endofpacket)
+					state <= STATE_OUTPUT_LAST;
+				else
+					state <= STATE_CAL_ODD;
+			end
+		end
+		STATE_CAL_ODD:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_ODD;
+			end
+		end
+		STATE_INPUT_ODD:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= data_caled_data_a;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				if (data_in_endofpacket)
+					state <= STATE_OUTPUT_LAST;
+				else
+					state <= STATE_CAL_EVEN;
+			end
+		end
+		STATE_CAL_EVEN:
+		begin
+			if (~waitrequest & to_udp_ready) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_EVEN;
+			end
+		end
+		STATE_OUTPUT_LAST: 
+		begin
+			if (to_udp_ready)
+				state <= STATE_IDLE;
+		end
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	//output the 160 32bit words to upd, first channel [31:16] , second channel [15:16]
+	//output  wire [31:0] to_udp_data,           //  st.data
+	assign to_udp_valid = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_CAL2 && (~waitrequest))? 1'b1:1'b0;
+	assign to_udp_endofpacket = (state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+	//reverse the polarity for output => no for simulation
+	assign to_udp_data = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST) ? {~first_data_buffer,~data_caled_data_a}: 32'b0; 
+	
+	
+	
+	
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/cluster_locate.sv b/FPGA_firmware/q_sys/synthesis/submodules/cluster_locate.sv
new file mode 100644
index 0000000..698db7a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/cluster_locate.sv
@@ -0,0 +1,186 @@
+/*
+CLUSTER LOCATE:
+if there is continuous [equal or more than SIZE]signals above THRESHOLD, there is cluster;
+The STATE_FIRST_CLUSTER find the left position of the Cluster; sig_ch_left
+if there is more than one cluster, the STATE_LAST_CLUSTER determine the right position of the Cluster; sig_ch_right
+When the address is 319, it goes to output state:
+the has_cluster, no_cluster, sig_ch_left and sig_ch_right keep for two clocks
+*/
+
+//the interface tested  by algo_top_cl_tb.v
+//the detailed math precise tested by cluster_locate_tb.v
+
+module cluster_locate // #(parameter THRESHOLD=54, SIZE=4)
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input logic signed [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+
+	input wire[15:0] THRESHOLD, //range 0~255
+	input wire[8:0] SIZE,	//range 0~255
+	
+	output wire[8:0] sig_ch_left,
+	output wire[8:0] sig_ch_right,
+	output wire has_cluster,
+	output wire no_cluster,
+	
+	output wire data_in_last //.... after this, there is has_cluster of no_cluster signal
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	localparam CHANNEL_NUM = 320;
+	reg signed[15:0] REG_THRESHOLD;
+	reg unsigned[8:0] REG_SIZE;
+	
+	reg[2:0] states;
+	localparam STATE_IDLE = 3'b000;
+	localparam STATE_REC = 3'b001;
+	localparam STATE_FIRST_CLUSTER = 3'b011;
+	localparam STATE_LAST_CLUSTER = 3'b010;
+	localparam STATE_HAS_CLUSTER = 3'b110;
+	localparam STATE_NO_CLUSTER = 3'b111;
+	localparam STATE_HAS_CLUSTER_KEEP = 3'b101;
+	localparam STATE_NO_CLUSTER_KEEP = 3'b100;
+	
+	reg unsigned[8:0] size_ctr; //the same as the channel
+	reg[8:0] ch_left;
+	reg[8:0] ch_right;
+	reg[8:0] address; 
+	
+	
+	assign sig_ch_left = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_left: 9'd0;
+	assign sig_ch_right = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_right: 9'd0;
+	assign has_cluster = (states==STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? 1'b1: 1'b0;
+	assign no_cluster = (states==STATE_NO_CLUSTER || states == STATE_NO_CLUSTER_KEEP)? 1'b1 : 1'b0;
+	
+	assign data_in_ready = (states == STATE_REC || states == STATE_FIRST_CLUSTER || states == STATE_LAST_CLUSTER)? 1'b1: 1'b0;
+	
+	wire data_over_th;  /* synthesis keep */
+	assign data_over_th = (data_in_data > REG_THRESHOLD)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			ch_left <= 0;
+			ch_right <= 0;
+			address <= 0; 
+			size_ctr <= 0;
+			states <= STATE_IDLE;
+			REG_THRESHOLD <= THRESHOLD;
+			REG_SIZE <= SIZE; 
+		end
+		else
+			case(states)
+				STATE_IDLE:
+				begin
+					ch_left <= 0;
+					ch_right <= 0;
+					address <= 0; 
+					size_ctr <= 0;
+					REG_THRESHOLD <= THRESHOLD;
+					REG_SIZE <= SIZE;
+					if (data_in_startofpacket)
+						states <= STATE_REC;
+				end
+				STATE_REC:
+				begin
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket) 
+							states <= STATE_NO_CLUSTER;
+						else if (data_over_th)
+						begin
+							size_ctr <= size_ctr + 1'b1;
+							states <= STATE_FIRST_CLUSTER;
+							ch_left <= address;
+						end
+					end	
+				end
+				STATE_FIRST_CLUSTER:
+				begin
+					if (data_in_valid) 
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+							if ((size_ctr + data_over_th) > REG_SIZE)
+							begin
+								states <= STATE_HAS_CLUSTER;
+								ch_right <= address;
+							end else
+								states <= STATE_NO_CLUSTER;
+						end
+						else if (data_over_th)
+							size_ctr <= size_ctr + 1'b1;
+						else   
+						begin
+							size_ctr <= 0;
+							if (size_ctr > REG_SIZE)
+							begin
+								states <= STATE_LAST_CLUSTER;
+								ch_right <= address -1'b1;
+							end else
+							begin
+								states <= STATE_REC;
+								ch_left <= 0; 
+							end
+						end
+					end
+				end
+				STATE_LAST_CLUSTER:
+				begin	
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+						states <= STATE_HAS_CLUSTER;
+						if ((size_ctr + data_over_th) > REG_SIZE)
+							ch_right <= address - ~data_over_th; //2024.09.30 ch_right <= address - ~data_over_th;
+						end	
+						else if (data_over_th)
+							size_ctr<= size_ctr + 1'b1;
+						else 
+						begin
+							if (size_ctr > REG_SIZE)
+								ch_right <= address-1'b1;
+							size_ctr <= 0;
+						end
+					end
+				end
+				STATE_HAS_CLUSTER:
+				begin
+					states <= STATE_HAS_CLUSTER_KEEP;
+				end
+				STATE_NO_CLUSTER:
+				begin
+					states <= STATE_NO_CLUSTER_KEEP;
+				end
+				STATE_HAS_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				STATE_NO_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				default:
+					states <= STATE_IDLE;
+			endcase		
+	end
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/csr_block.v b/FPGA_firmware/q_sys/synthesis/submodules/csr_block.v
new file mode 100644
index 0000000..be0cd55
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/csr_block.v
@@ -0,0 +1,414 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block is used to communicate information back and forth between the SGDMA
+  and the host.  When the response port is not set to streaming then this block
+  will be used to generate interrupts for the host.  The address span of this block
+  differs depending on whether the enhanced features are enabled.  The enhanced
+  features enables sequence number readback capabilties.  The address map is as follows:
+
+  Enhanced features off:
+
+  Bytes     Access Type     Description
+  -----     -----------     -----------
+  0-3       R               Status(1)
+  4-7       R/W             Control(2)
+  8-12      R               Descriptor Watermark (write watermark[15:0],read watermark [15:0])
+  13-15     R               Response Watermark
+  16-31     N/A             <Reserved>
+
+
+  Enhanced features on:
+
+  Bytes     Access Type     Description
+  -----     -----------     -----------
+  0-3       R               Status(1)
+  4-7       R/W             Control(2)
+  8-12      R               Descriptor Watermark (write watermark[15:0],read watermark [15:0])
+  13-15     R               Response Watermark
+  16-20     R               Sequence Number (write sequence[15:0],read sequence[15:0])
+  21-31     N/A             <Reserved>
+
+  (1)  Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
+  (2)  Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
+
+  Status Register:
+
+  Bits      Description
+  ----      -----------
+  0         Busy
+  1         Descriptor Buffer Empty
+  2         Descriptor Buffer Full
+  3         Response Buffer Empty
+  4         Response Buffer Full
+  5         Stop State
+  6         Reset State
+  7         Stopped on Error
+  8         Stopped on Early Termination
+  9         IRQ
+  10-31     <Reserved>
+
+  Control Register:
+
+  Bits      Description
+  ----      -----------
+  0         Stop (will also be set if a stop on error/early termination condition occurs)
+  1         Software Reset
+  2         Stop on Error
+  3         Stop on Early Termination
+  4         Global Interrupt Enable Mask
+  5         Stop descriptors (stops the dispatcher from issuing more read/write commands)
+  6-31      <Reserved>
+
+  
+  Author:  JCJB
+  Date:  08/18/2010
+
+  1.0 - Initial release
+  
+  1.1 - Removed delayed reset, added set and hold sw_reset
+  
+  1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
+        This will prevent the read or write masters from starting back up when reset while in the stop state.
+  
+  1.3 - Added the stop dispatcher bit (5) to the control register
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+
+module csr_block (
+  clk,
+  reset,
+  
+  csr_writedata,
+  csr_write,
+  csr_byteenable,
+  csr_readdata,
+  csr_read,
+  csr_address,
+  csr_irq,
+
+  done_strobe,
+  busy,
+  descriptor_buffer_empty,
+  descriptor_buffer_full,
+  stop_state,
+  stopped_on_error,
+  stopped_on_early_termination,
+  reset_stalled,
+  stop,
+  sw_reset,
+  stop_on_error,
+  stop_on_early_termination,
+  stop_descriptors,
+  sequence_number,
+  descriptor_watermark,
+  response_watermark,
+  response_buffer_empty,
+  response_buffer_full,
+  transfer_complete_IRQ_mask,
+  error_IRQ_mask,
+  early_termination_IRQ_mask,
+  error,
+  early_termination
+);
+
+  parameter ADDRESS_WIDTH = 3;
+  localparam CONTROL_REGISTER_ADDRESS = 3'b001;
+
+
+  input clk;
+  input reset;
+
+  input [31:0] csr_writedata;
+  input csr_write;
+  input [3:0] csr_byteenable;
+  output wire [31:0] csr_readdata;
+  input csr_read;
+  input [ADDRESS_WIDTH-1:0] csr_address;
+  output wire csr_irq;
+
+  input done_strobe;
+  input busy;
+  input descriptor_buffer_empty;
+  input descriptor_buffer_full;
+  input stop_state;      // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
+  input reset_stalled;   // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
+  output wire stop;
+  output reg stopped_on_error;
+  output reg stopped_on_early_termination;
+  output reg sw_reset;
+  output wire stop_on_error;
+  output wire stop_on_early_termination;
+  output wire stop_descriptors;
+  input [31:0] sequence_number;
+  input [31:0] descriptor_watermark;
+  input [15:0] response_watermark;
+  input response_buffer_empty;
+  input response_buffer_full;
+  input transfer_complete_IRQ_mask;
+  input [7:0] error_IRQ_mask;
+  input early_termination_IRQ_mask;
+  input [7:0] error;
+  input early_termination;
+
+  /* Internal wires and registers */
+  wire [31:0] status;
+  reg [31:0] control;
+  reg [31:0] readdata;
+  reg [31:0] readdata_d1;
+  reg irq;  // writing to the status register clears the irq bit
+  wire set_irq;
+  wire clear_irq;
+  wire set_stopped_on_error;
+  wire set_stopped_on_early_termination;
+  wire set_stop;
+  wire clear_stop;
+  wire global_interrupt_enable;
+  wire sw_reset_strobe;  // this strobe will be one cycle earlier than sw_reset
+  wire set_sw_reset;
+  wire clear_sw_reset;
+
+
+
+
+
+
+  /********************************************** Registers ***************************************************/
+  // read latency is 1 cycle
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      readdata_d1 <= 0;
+    end
+    else if (csr_read == 1)
+    begin
+      readdata_d1 <= readdata;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      control[31:1] <= 0;
+    end
+    else
+    begin
+      if (sw_reset_strobe == 1)  // reset strobe is a strobe due to this sync reset
+      begin
+        control[31:1] <= 0;
+      end
+      else
+      begin
+        if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
+        begin
+          control[7:1] <= csr_writedata[7:1];  // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
+        end
+        if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
+        begin
+          control[15:8] <= csr_writedata[15:8];
+        end
+        if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
+        begin
+          control[23:16] <= csr_writedata[23:16];
+        end
+        if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
+        begin
+          control[31:24] <= csr_writedata[31:24];
+        end
+      end
+    end
+  end
+
+  
+  // control bit 0 (stop) is set by different sources so handling it seperately
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      control[0] <= 0;
+    end
+    else
+    begin
+      if (sw_reset_strobe == 1)
+      begin
+        control[0] <= 0;
+      end
+      else
+      begin
+        case ({set_stop, clear_stop})
+          2'b00: control[0] <= control[0];
+          2'b01: control[0] <= 1'b0;
+          2'b10: control[0] <= 1'b1;
+          2'b11: control[0] <= 1'b1;  // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs 
+        endcase
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      sw_reset <= 0;
+    end
+    else
+    begin
+      if (set_sw_reset == 1)
+      begin
+        sw_reset <= 1;
+      end
+      else if (clear_sw_reset == 1)
+      begin
+        sw_reset <= 0;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      stopped_on_error <= 0;
+    end
+    else
+    begin
+      case ({set_stopped_on_error, clear_stop})
+        2'b00: stopped_on_error <= stopped_on_error;
+        2'b01: stopped_on_error <= 1'b0;
+        2'b10: stopped_on_error <= 1'b1;
+        2'b11: stopped_on_error <= 1'b0;
+      endcase
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      stopped_on_early_termination <= 0;
+    end
+    else
+    begin
+      case ({set_stopped_on_early_termination, clear_stop})
+        2'b00: stopped_on_early_termination <= stopped_on_early_termination;
+        2'b01: stopped_on_early_termination <= 1'b0;
+        2'b10: stopped_on_early_termination <= 1'b1;
+        2'b11: stopped_on_early_termination <= 1'b0;
+      endcase
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      irq <= 0;
+    end
+    else
+    begin
+      if (sw_reset_strobe == 1)
+      begin
+        irq <= 0;
+      end
+      else
+      begin
+        case ({clear_irq, set_irq})
+          2'b00: irq <= irq;
+          2'b01: irq <= 1'b1;
+          2'b10: irq <= 1'b0;
+          2'b11: irq <= 1'b1;  // setting will win over a clear
+        endcase
+      end
+    end
+  end
+  /******************************************** End Registers *************************************************/
+
+
+
+  /**************************************** Combinational Signals *********************************************/
+  generate
+    if (ADDRESS_WIDTH == 3)
+    begin  
+      always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
+      begin
+        case (csr_address)
+          3'b000: readdata = status;
+          3'b001: readdata = control;
+          3'b010: readdata = descriptor_watermark;
+          3'b011: readdata = response_watermark;
+          default: readdata = sequence_number;  // all other addresses will decode to the sequence number
+        endcase  
+      end
+    end
+    else
+    begin
+      always @ (csr_address or status or control or descriptor_watermark or response_watermark)
+      begin
+        case (csr_address)
+          3'b000: readdata = status;
+          3'b001: readdata = control;
+          3'b010: readdata = descriptor_watermark;
+          default: readdata = response_watermark;  // all other addresses will decode to the response watermark
+        endcase  
+      end
+    end
+  endgenerate
+
+
+  assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1);  // this is the IRQ bit
+  assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) &       // transfer ended and interrupts are enabled
+                   ((transfer_complete_IRQ_mask == 1) |                        // transfer ended and the transfer complete IRQ is enabled
+                    ((error & error_IRQ_mask) != 0) |                          // transfer ended with an error and this IRQ is enabled
+                    ((early_termination & early_termination_IRQ_mask) == 1));  // transfer ended early due to early termination and this IRQ is enabled
+  assign csr_irq = irq;
+
+  assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
+  assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0);  // when clear_stop is set then the stopped_on_error register will be cleared
+  assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1);  // when clear_stop is set then the stopped_on_early_termination register will be cleared
+  assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) |  // host set the stop bit
+                    (set_stopped_on_error == 1) |  // SGDMA setup to stop when an error occurs from the write master
+                    (set_stopped_on_early_termination == 1) ;  // SGDMA setup to stop when the write master overflows
+  assign stop = control[0];
+
+  assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
+  assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
+  
+  assign sw_reset_strobe = control[1];
+  assign stop_on_error = control[2];
+  assign stop_on_early_termination = control[3];
+  assign global_interrupt_enable = control[4];
+  assign stop_descriptors = control[5];
+
+  assign csr_readdata = readdata_d1;
+  assign status = {{22{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy};  // writing to the lower byte of the status register clears the irq bit
+  /**************************************** Combinational Signals *********************************************/
+  
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.qip b/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.qip
new file mode 100644
index 0000000..0276769
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "data_caled_ram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_bb.v"]
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.v
new file mode 100644
index 0000000..dc286ee
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/data_caled_ram.v
@@ -0,0 +1,243 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: data_caled_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module data_caled_ram (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[15:0]  data_a;
+	input	[15:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire [15:0] sub_wire1;
+	wire [15:0] q_a = sub_wire0[15:0];
+	wire [15:0] q_b = sub_wire1[15:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (data_a),
+				.data_b (data_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 16,
+		altsyncram_component.width_b = 16,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/data_interface.sv b/FPGA_firmware/q_sys/synthesis/submodules/data_interface.sv
new file mode 100644
index 0000000..b230d78
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/data_interface.sv
@@ -0,0 +1,320 @@
+/*
+This data_interface get the data from the sensor, and provide the data after background subtraction and cluster locating signal to next step
+
+The BKG_FRAME has to be the power of 2, and it belongs to [2,65536]
+CLU_THRESHOLD and CLU_SIZE are for cluster_locate; CLU_SIZE belongs to [0,319]
+
+*/
+
+
+`timescale 100 ps / 100 ps
+module data_interface #(parameter BKG_FRAME = 4, CLU_THRESHOLD = 54, CLU_SIZE = 4)
+(
+			//Clock/reset
+			input  wire        	clk_clk,                    //                     clk.clk
+			input  wire        	rst_reset,                  //                     connect to int_reset from sensor_interface, to reset frameID to 0;
+			//avalon ST sink
+			input  logic unsigned[31:0] data_in_data,           //  data_in.data
+			output wire        data_in_ready,          //         .ready
+			input  wire        data_in_valid,          //         .valid
+			input  wire [1:0]  data_in_empty,          //         .empty
+			input  wire        data_in_endofpacket,    //         .endofpacket
+			input  wire        data_in_startofpacket,  //         .startofpacket
+			//avalon ST source
+			output wire [31:0] data_out_data,          // data_out.data
+			output wire [1:0]  data_out_empty,         //         .empty
+			output wire        data_out_endofpacket,   //         .endofpacket
+			output wire        data_out_startofpacket, //         .startofpacket
+			input  wire        data_out_ready,         //         .ready  the UDP is ready
+			output wire        data_out_valid,          //         .valid
+
+			output wire[26:0]	 frameID, // for assign signal in tb simulation
+			output wire bkg_sub_on,
+			output wire rst_frame, // this is for after data_interface
+				 
+			//data for sig after bkg subtraction
+			input wire			   sig_rdclk,						//the read port for sig_ram
+			input wire[8:0]		sig_rdaddress,             //0~319 for data. 500~502 for the 3 words head
+			output wire[31:0]		sig_out,
+			output reg 			sig_ram_last,
+
+			//the output of cluster_locate
+			output wire[8:0]		sig_ch_left,
+			output wire[8:0]		sig_ch_right,
+			output wire				has_cluster,
+			output wire				no_cluster
+		
+			
+	);
+	/*******the reset logic********************************/
+		//the rst signal for every frame
+	wire rst_frame_after_sensor_interface;
+	assign rst_frame_after_sensor_interface = data_in_startofpacket || rst_reset;
+	
+	assign rst_frame = data_in_endofpacket || rst_reset;
+	
+	
+
+		/*
+		This is a frame counter; 
+		frameID +1 at the rising edge of data_in_startofpacket
+		wire[26:0] frameID;
+		if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
+		*/
+		frame_counter framectr(
+			.clk_clk(clk_clk),
+			.rst_reset(rst_reset),
+			.sig(data_in_startofpacket),
+			.frame_Num(frameID)
+		);
+		
+
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 5'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 5'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 5'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 5'd3;	//sending third word :				
+	localparam STATE_DATA_PRO	= 5'd4;	//blocking data do the calculation
+	localparam STATE_DATA_NEXT  = 5'd7;  //sending data
+	localparam STATE_LOC	= 5'd5;	//calculatebb
+	
+	
+		//Helper stuff
+	reg	[7:0]	tx_ctr;	//counter of sent data words range: 0~255
+	localparam WORDS_TO_SEND = 163;
+
+	//the number of clocks for STATE_DATA_PRO
+	reg [5:0] delay_ctr;
+	localparam DELAY_CLOCKS = 6'd3; 
+	
+	
+	/************** bkg RAM ****************************/
+	/*
+	for prepare the bkg signal by two RAM;
+	one for data_in_data[31:16]; the other for data_in_data[15:0]
+	the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
+	*/
+	wire[15:0] bkg_signal0;
+	wire[15:0] bkg_signal1;
+	wire[31:0] bkg_input_data;
+	
+	//signal after subtract background
+	//got the background signal at the third clock in STATE_DATA_PRO
+	//and subtract it to 16 bit by giving up the LSM, i.e. divide 2. 
+	reg [16:0] signal0_17bit;
+	reg [16:0] signal1_17bit;
+	wire[15:0] signal0;
+	wire[15:0] signal1;
+	
+	assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
+	assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
+	
+	bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_but0(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_reset),
+		.frameID(frameID[26:0]),
+		.address(tx_ctr), 
+		.data_in_data(bkg_input_data[31:16]),
+		.bkg_signal(bkg_signal0),
+		.bkg_sub_status(bkg_sub_on)
+	); 
+	
+	bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_but1(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_reset),
+		.frameID(frameID[26:0]),
+		.address(tx_ctr), 
+		.data_in_data(bkg_input_data[15:0]),
+		.bkg_signal(bkg_signal1)
+	); 
+	
+	assign bkg_input_data = (state==STATE_DATA_NEXT)?~data_in_data:15'b0;
+	
+	
+		//The state machine
+	always @(posedge clk_clk or posedge rst_reset)
+	begin 
+		if (rst_reset)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+						tx_ctr <= 0;
+					end
+				end
+				STATE_WORD0:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_WORD1;
+					tx_ctr <= tx_ctr+ 1'b1;
+					end
+				end
+				STATE_WORD1:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_WORD2;
+					tx_ctr <= tx_ctr +1'b1;
+					end
+				end
+				STATE_WORD2:
+				begin
+				if (data_out_ready)
+					begin
+					state <= STATE_DATA_PRO;
+					tx_ctr <= tx_ctr +1'b1;
+					delay_ctr <= DELAY_CLOCKS -1'b1;
+					end
+				end
+				STATE_DATA_PRO:
+				begin
+					delay_ctr <= delay_ctr -1'b1;
+					if (delay_ctr == 0)
+					begin
+						state <= STATE_DATA_NEXT;
+						delay_ctr <= DELAY_CLOCKS - 1'b1;
+						signal0_17bit <= {1'b0,~data_in_data[31:16]}-{1'b0,bkg_signal0};
+					   signal1_17bit <= {1'b0,~data_in_data[15:0]}-{1'b0,bkg_signal1};
+					end
+				end
+				STATE_DATA_NEXT:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1'b1;
+						if (tx_ctr == WORDS_TO_SEND -1)	//last word, size matches
+							state <= STATE_LOC;
+						else
+							state <= STATE_DATA_PRO;	
+					end
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+		
+	assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready; 
+	assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1'b1 : 1'b0; 
+	//the output data is be reversed....so during transfer without signal it's FFFFF, the software HIT-DAQ will reverse it again
+	assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
+									(state == STATE_DATA_NEXT)? {~signal0,~signal1}: 0;
+	assign data_out_startofpacket = data_in_startofpacket;	
+	assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;	
+	assign data_out_empty = 0;
+	
+	
+	
+	
+	/*********************Prepare the data to cluster_locate******************************************/
+	/*
+	it is built by the fact that regardless data_out_ready signal, the STATE_DATA_PRO will go to STATE_DATA_NEXT
+	so the signal after bkg sub will continue at least two clocks
+	*/
+	
+	//the signal indicate the signal after bkg sub is ready or not; it's ready on next clock
+	wire sub_bkg_signal_ready;
+	assign sub_bkg_signal_ready = (state == STATE_DATA_PRO && delay_ctr == 0)? 1'b1 :1'b0;
+
+	
+	reg[8:0] cl_address;
+	wire[15:0] cl_data_in_data;
+	wire cl_data_in_valid;
+	
+	cluster_locate #(.THRESHOLD(CLU_THRESHOLD), .SIZE(CLU_SIZE)) cl_but(
+		.clk_clk(clk_clk),
+		.rst_reset(rst_frame_after_sensor_interface),
+		.address(cl_address), 
+		.last_data(sig_ram_last),
+		.data_in_data(cl_data_in_data),
+		.data_in_valid(cl_data_in_valid),
+		.sig_ch_left(sig_ch_left),
+		.sig_ch_right(sig_ch_right),
+		.has_cluster(has_cluster),
+		.no_cluster(no_cluster)
+	); 
+
+	reg[2:0] state_clu;
+	localparam STATE_CLU_IDLE = 3'b1;
+	localparam STATE_CLU_FIRST = 3'b10;
+	localparam STATE_CLU_SECOND = 3'b100;
+	
+	assign cl_data_in_data = (state_clu == STATE_CLU_FIRST)? signal0:
+										(state_clu == STATE_CLU_SECOND)? signal1: 16'b0;
+	assign cl_data_in_valid = (bkg_sub_on && (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND))? 1'b1: 1'b0;
+	
+	always @ (posedge clk_clk or posedge rst_frame_after_sensor_interface)
+	begin
+		if (rst_frame_after_sensor_interface)
+		begin
+			state_clu <= STATE_CLU_IDLE;
+			cl_address <= 9'b0;
+		end
+		else case(state_clu)
+		STATE_CLU_IDLE:
+		begin
+			if (sub_bkg_signal_ready)
+				state_clu <= STATE_CLU_FIRST;
+		end
+		STATE_CLU_FIRST:
+		begin
+			state_clu <= STATE_CLU_SECOND;
+			cl_address <= cl_address + 1'b1;
+		end
+		STATE_CLU_SECOND:
+		begin
+			state_clu <= STATE_CLU_IDLE;
+			cl_address <= cl_address + 1'b1;
+		end
+		default:
+			state_clu <= STATE_CLU_IDLE;
+		endcase
+	end
+	
+	
+	/*********************ram for data after background subtraction**************************/
+	
+	/*when bkg_sub is not on, store the original data
+	store the signal after bkg_sub in ram
+	output the sig_ram_last signal
+	*/
+	
+	wire sig_ram_wren;
+	wire[31:0] sig_ram_data;
+	wire[8:0] sig_wraddress;
+	
+	
+	ram4sig sig_ram (
+	.data(sig_ram_data),
+	.rdaddress(sig_rdaddress),
+	.rdclock(clk_clk),
+	.wraddress(sig_wraddress),
+	.wrclock(clk_clk),
+	.wren(sig_ram_wren),
+	.q(sig_out)
+	);
+	
+	assign sig_ram_wren = (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND)? 1'b1: 1'b0;
+	assign sig_wraddress = cl_address;
+	assign sig_ram_data = {16'b0,cl_data_in_data};
+	assign sig_ram_last = (state == STATE_LOC)? 1'b1: 1'b0;
+	
+			
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/descriptor_buffers.v b/FPGA_firmware/q_sys/synthesis/submodules/descriptor_buffers.v
new file mode 100644
index 0000000..2752970
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/descriptor_buffers.v
@@ -0,0 +1,421 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block is responsible for accepting 128/256 bit descriptors and
+  buffering them in descriptor FIFOs.  Each bytelane of the descriptor
+  can be written to individually and writing ot the descriptor 'go' bit
+  commits the data into the FIFO.  Reading that data out of the FIFO
+  occurs two cycles after the read is asserted as the FIFOs do not support
+  lookahead mode.
+  
+  This block must keep local copies of per descriptor information like
+  the optional sequence number or interrupt masks.  When parked mode
+  is set in the descriptor the same will transfer multiple times when
+  the descriptor FIFO only contains one descriptor (and this descriptor
+  will not be popped).  Parked mode is useful for video frame buffering.
+
+
+
+  1.0 - The on-chip memory in the FIFOs are not inferred so there may
+        be some extra unused bits.  In a later Quartus II release the
+        on-chip memory will be replaced with inferred memory.
+
+  1.1 - Shifted all descriptor registers into this block (from the dispatcher
+        block).  Added breakout blocks responsible for re-packing the
+        information for use by each master.
+        
+  1.2 - Added the read_early_done_enable bit to the breakout (for debug)
+  
+  1.3 - Made the read_address and write_address widths 64-bit (for debug)
+*/
+
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module descriptor_buffers (
+  clk,
+  reset,
+
+  writedata,
+  write,
+  byteenable,
+  waitrequest,
+
+  read_command_valid,
+  read_command_ready,
+  read_command_data,
+  read_command_empty,
+  read_command_full,
+  read_command_used,
+
+  write_command_valid,
+  write_command_ready,
+  write_command_data,
+  write_command_empty,
+  write_command_full,
+  write_command_used,
+
+  stop_issuing_commands,
+  stop,
+  sw_reset,
+  sequence_number,
+  transfer_complete_IRQ_mask,
+  early_termination_IRQ_mask,
+  error_IRQ_mask
+);
+
+  parameter MODE = 0;
+  parameter DATA_WIDTH = 256;
+  parameter BYTE_ENABLE_WIDTH = 32;
+  parameter FIFO_DEPTH = 128;
+  parameter FIFO_DEPTH_LOG2 = 7;  // top level module can figure this out
+  
+  input clk;
+  input reset;
+
+  input [DATA_WIDTH-1:0] writedata;
+  input write;
+  input [BYTE_ENABLE_WIDTH-1:0] byteenable;
+  output wire waitrequest;
+
+  output wire read_command_valid;
+  input read_command_ready;
+  output wire [255:0] read_command_data;
+  output wire read_command_empty;
+  output wire read_command_full;
+  output wire [FIFO_DEPTH_LOG2:0] read_command_used;
+
+  output wire write_command_valid;
+  input write_command_ready;
+  output wire [255:0] write_command_data;
+  output wire write_command_empty;
+  output wire write_command_full;
+  output wire [FIFO_DEPTH_LOG2:0] write_command_used;
+
+  input stop_issuing_commands;
+  input stop;
+  input sw_reset;
+  output wire [31:0] sequence_number;
+  output wire transfer_complete_IRQ_mask;
+  output wire early_termination_IRQ_mask;
+  output wire [7:0] error_IRQ_mask;
+
+
+  /* Internal wires and registers */
+  reg write_command_empty_d1;
+  reg write_command_empty_d2;
+  reg read_command_empty_d1;
+  reg read_command_empty_d2;
+  wire push_write_fifo;
+  wire pop_write_fifo;
+  wire push_read_fifo;
+  wire pop_read_fifo;
+  wire go_bit;
+  wire read_park;
+  wire read_park_enable;  // park is enabled when read_park is enabled and the read FIFO is empty
+  wire write_park;
+  wire write_park_enable;  // park is enabled when write_park is enabled and the write FIFO is empty
+  wire [DATA_WIDTH-1:0] write_fifo_output;
+  wire [DATA_WIDTH-1:0] read_fifo_output;
+  wire [15:0] write_sequence_number;
+  reg [15:0] write_sequence_number_d1;
+  wire [15:0] read_sequence_number;
+  reg [15:0] read_sequence_number_d1;
+  wire read_transfer_complete_IRQ_mask;
+  reg read_transfer_complete_IRQ_mask_d1;
+  wire write_transfer_complete_IRQ_mask;
+  reg write_transfer_complete_IRQ_mask_d1;
+  wire write_early_termination_IRQ_mask;
+  reg write_early_termination_IRQ_mask_d1;
+  wire [7:0] write_error_IRQ_mask;
+  reg [7:0] write_error_IRQ_mask_d1;
+  wire issue_write_descriptor;  // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
+  wire issue_read_descriptor;   // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
+  wire write_en;   // Qualified fifo write with waitrequest to prevent fifo overflow when descriptor slave port is being back pressured 
+
+
+  /* Unused signals that are provided for debug convenience */
+  wire [63:0] read_address;
+  wire [31:0] read_length;
+  wire [7:0] read_transmit_channel;
+  wire read_generate_sop;
+  wire read_generate_eop;
+  wire [7:0] read_burst_count;
+  wire [15:0] read_stride;
+  wire [7:0] read_transmit_error;
+  wire read_early_done_enable;
+  wire [63:0] write_address;
+  wire [31:0] write_length;
+  wire write_end_on_eop;
+  wire [7:0] write_burst_count;
+  wire [15:0] write_stride;
+
+
+
+  /************************************************* Registers *******************************************************/
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      write_sequence_number_d1 <= 0;
+      write_transfer_complete_IRQ_mask_d1 <= 0;
+      write_early_termination_IRQ_mask_d1 <= 0;
+      write_error_IRQ_mask_d1 <= 0;
+    end
+    else if (issue_write_descriptor)  // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
+    begin
+      write_sequence_number_d1 <= write_sequence_number;
+      write_transfer_complete_IRQ_mask_d1 <= write_transfer_complete_IRQ_mask;
+      write_early_termination_IRQ_mask_d1 <= write_early_termination_IRQ_mask;
+      write_error_IRQ_mask_d1 <= write_error_IRQ_mask;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      read_sequence_number_d1 <= 0;
+      read_transfer_complete_IRQ_mask_d1 <= 0;
+    end
+    else if (issue_read_descriptor)  // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
+    begin
+      read_sequence_number_d1 <= read_sequence_number;
+      read_transfer_complete_IRQ_mask_d1 <= read_transfer_complete_IRQ_mask;
+    end
+  end
+
+
+  // need to use a delayed valid signal since the commmand buffers have two cycles of latency
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      write_command_empty_d1 <= 0;
+      write_command_empty_d2 <= 0;
+      read_command_empty_d1 <= 0;
+      read_command_empty_d2 <= 0;
+    end
+    else
+    begin
+      write_command_empty_d1 <= write_command_empty;
+      write_command_empty_d2 <= write_command_empty_d1;
+      read_command_empty_d1 <= read_command_empty;
+      read_command_empty_d2 <= read_command_empty_d1;
+    end
+  end
+  /*********************************************** End Registers *****************************************************/
+
+
+  /****************************************** Module Instantiations **************************************************/
+  /* the write_signal_break module simply takes the output of the descriptor buffer and reformats the data
+   * to be sent in the command format needed by the master command port.  If new features are added to the
+   * descriptor format then add it to this block.  This block also provides the descriptor information
+   * using a naming convention isn't of bit indexes in a 256 bit wide command signal.
+   */
+  write_signal_breakout the_write_signal_breakout (
+    .write_command_data_in (write_fifo_output),
+    .write_command_data_out (write_command_data),
+    .write_address (write_address),
+    .write_length (write_length),
+    .write_park (write_park),
+    .write_end_on_eop (write_end_on_eop),
+    .write_transfer_complete_IRQ_mask (write_transfer_complete_IRQ_mask),
+    .write_early_termination_IRQ_mask (write_early_termination_IRQ_mask),
+    .write_error_IRQ_mask (write_error_IRQ_mask),
+    .write_burst_count (write_burst_count),
+    .write_stride (write_stride),
+    .write_sequence_number (write_sequence_number),
+    .write_stop (stop),
+    .write_sw_reset (sw_reset)
+  );
+  defparam the_write_signal_breakout.DATA_WIDTH = DATA_WIDTH;
+
+
+  /* the read_signal_break module simply takes the output of the descriptor buffer and reformats the data
+   * to be sent in the command format needed by the master command port.  If new features are added to the
+   * descriptor format then add it to this block.  This block also provides the descriptor information
+   * using a naming convention isn't of bit indexes in a 256 bit wide command signal.
+   */
+  read_signal_breakout the_read_signal_breakout (
+    .read_command_data_in (read_fifo_output),
+    .read_command_data_out (read_command_data),
+    .read_address (read_address),
+    .read_length (read_length),
+    .read_transmit_channel (read_transmit_channel),
+    .read_generate_sop (read_generate_sop),
+    .read_generate_eop (read_generate_eop),
+    .read_park (read_park),
+    .read_transfer_complete_IRQ_mask (read_transfer_complete_IRQ_mask),
+    .read_burst_count (read_burst_count),
+    .read_stride (read_stride),
+    .read_sequence_number (read_sequence_number),
+    .read_transmit_error (read_transmit_error),
+    .read_early_done_enable (read_early_done_enable),
+    .read_stop (stop),
+    .read_sw_reset (sw_reset)
+  );
+  defparam the_read_signal_breakout.DATA_WIDTH = DATA_WIDTH;
+
+
+  // Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
+  // This differs from scfifo which commits the data any time the write signal is asserted.
+  fifo_with_byteenables the_read_command_FIFO (
+    .clk (clk),
+    .areset (reset),
+    .sreset (sw_reset),
+    .write_data (writedata),
+    .write_byteenables (byteenable),
+    .write (write_en),
+    .push (push_read_fifo),
+    .read_data (read_fifo_output),
+    .pop (pop_read_fifo),
+    .used (read_command_used),  // this is a 'true used' signal with the full bit accounted for
+    .full (read_command_full),
+    .empty (read_command_empty)
+  );
+  defparam the_read_command_FIFO.DATA_WIDTH = DATA_WIDTH;  // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
+  defparam the_read_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
+  defparam the_read_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
+  defparam the_read_command_FIFO.LATENCY = 2;
+
+
+  // Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
+  // This differs from scfifo which commits the data any time the write signal is asserted.
+  fifo_with_byteenables the_write_command_FIFO (
+    .clk (clk),
+    .areset (reset),
+    .sreset (sw_reset),
+    .write_data (writedata),
+    .write_byteenables (byteenable),
+    .write (write_en),
+    .push (push_write_fifo),
+    .read_data (write_fifo_output),
+    .pop (pop_write_fifo),
+    .used (write_command_used),  // this is a 'true used' signal with the full bit accounted for
+    .full (write_command_full),
+    .empty (write_command_empty)
+  );
+  defparam the_write_command_FIFO.DATA_WIDTH = DATA_WIDTH;  // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
+  defparam the_write_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
+  defparam the_write_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
+  defparam the_write_command_FIFO.LATENCY = 2; 
+  /**************************************** End Module Instantiations ************************************************/
+
+
+  /****************************************** Combinational Signals **************************************************/
+  generate  // all unnecessary signals and drivers will be optimized away
+    if (MODE == 0)  // MM-->MM
+    begin
+      assign waitrequest = (read_command_full == 1) | (write_command_full == 1) | (sw_reset == 1);
+
+      // information for the CSR or response blocks to use
+      assign sequence_number = {write_sequence_number_d1, read_sequence_number_d1};
+      assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
+      assign early_termination_IRQ_mask = 1'b0;
+      assign error_IRQ_mask = 8'h00; 
+
+      // read buffer flow control
+      assign push_read_fifo = go_bit;
+      assign read_park_enable = (read_park == 1) & (read_command_used == 1);  // we want to keep the descriptor in the FIFO when the park bit is set
+      assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
+                                  (read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0);  // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
+      assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
+      assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0);  // don't want to pop the fifo if we are in parked mode
+
+      // write buffer flow control
+      assign push_write_fifo = go_bit;
+      assign write_park_enable = (write_park == 1) & (write_command_used == 1);  // we want to keep the descriptor in the FIFO when the park bit is set
+      assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
+                                   (write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0);  // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
+      assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
+      assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0);  // don't want to pop the fifo if we are in parked mode
+    end
+    else if (MODE == 1)  // MM-->ST
+    begin
+      // information for the CSR or response blocks to use
+      assign sequence_number = {16'h0000, read_sequence_number_d1};
+      assign transfer_complete_IRQ_mask = read_transfer_complete_IRQ_mask_d1;
+      assign early_termination_IRQ_mask = 1'b0;
+      assign error_IRQ_mask = 8'h00;
+
+      assign waitrequest = (read_command_full == 1) | (sw_reset == 1);
+
+      // read buffer flow control
+      assign push_read_fifo = go_bit;
+      assign read_park_enable = (read_park == 1) & (read_command_used == 1);  // we want to keep the descriptor in the FIFO when the park bit is set
+      assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
+                                  (read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0);  // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
+      assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
+      assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0);  // don't want to pop the fifo if we are in parked mode
+
+      // write buffer flow control
+      assign push_write_fifo = 0;
+      assign write_park_enable = 0;
+      assign write_command_valid = 0;
+      assign issue_write_descriptor = 0;
+      assign pop_write_fifo = 0;
+    end
+    else  // ST-->MM
+    begin
+      // information for the CSR or response blocks to use
+      assign sequence_number = {write_sequence_number_d1, 16'h0000};
+      assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
+      assign early_termination_IRQ_mask = write_early_termination_IRQ_mask_d1; 
+      assign error_IRQ_mask = write_error_IRQ_mask_d1;
+
+      assign waitrequest = (write_command_full == 1) | (sw_reset == 1);
+
+      // read buffer flow control
+      assign push_read_fifo = 0;
+      assign read_park_enable = 0;
+      assign read_command_valid = 0;
+      assign issue_read_descriptor = 0;
+      assign pop_read_fifo = 0;
+
+      // write buffer flow control
+      assign push_write_fifo = go_bit;
+      assign write_park_enable = (write_park == 1) & (write_command_used == 1);  // we want to keep the descriptor in the FIFO when the park bit is set
+      assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
+                                   (write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0);  // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
+      assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
+      assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0);  // don't want to pop the fifo if we are in parked mode
+    end
+  endgenerate
+
+
+  generate  // go bit is in a different location depending on the width of the slave port
+    if (DATA_WIDTH == 256)
+    begin
+      assign go_bit = (writedata[255] == 1) & (write == 1) & (byteenable[31] == 1) & (waitrequest == 0);
+    end
+    else
+    begin
+      assign go_bit = (writedata[127] == 1) & (write == 1) & (byteenable[15] == 1) & (waitrequest == 0);
+    end
+  endgenerate
+
+  assign write_en = (write == 1) & (waitrequest == 0);
+  /**************************************** End Combinational Signals ************************************************/
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/dispatcher.v b/FPGA_firmware/q_sys/synthesis/submodules/dispatcher.v
new file mode 100644
index 0000000..2204d0c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/dispatcher.v
@@ -0,0 +1,430 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block is responsible for communicating with the host processor/
+  descriptor prefetching master block.  It uses FIFOs to buffer descriptors
+  to keep the read and write masters operating without intervention from a
+  host processor.  This block is comprised of three main blocks:
+
+  1)  Descriptor buffer
+  2)  CSR
+  3)  Response
+
+  The descriptor buffer recieves descriptors from a host/prefetcher and
+  registers the incoming byte lanes.  When the descriptor 'go' bit has been
+  written, the descriptor is committed to the read/write descriptor buffers.
+  From there the descriptors are exposed to the read and write masters without
+  intervention from the host.  The descriptor port is either 128 or 256 bits
+  wide depending on whether or not the enhanced features setting has been enabled.
+  Since the port is write only minimial logic will be created in the fabric
+  to adapt the byte enables for narrow masters connecting to this port.  This
+  port contains a single address so address bits are exposed to the fabric.
+
+  The CSR (control-status register) block is used to provide information
+  back to the host as well as allow the SGDMA to be controlled on a
+  non-descriptor basis.  The host driver should be written to mostly interact
+  with this port as interrupts and status information is accessible from this
+  block.
+
+  The optional response block is used to feed information on a per descriptor
+  basis back to the host or prefetching descriptor master.  In most cases the
+  port will be used for sharing infomation about ST->MM transfers.
+
+  Communication between this block and the masters is performed using pairs
+  of Avalon-ST port connections.  When the SGDMA is setup for MM->ST then the
+  write master port connections are removed and visa vera for ST->MM and the
+  read master.  For more detailed information refer to "SGDMA_dispatcher_ug.pdf"
+  for more details.
+
+  
+  Author:  JCJB
+  Date:  08/13/2010
+
+  
+  1.0 - Initial release
+  
+  1.1 - Changed the stopped and resetting logic to correctly reflect the state
+        of the hardware (this block and the masters).
+
+  1.2 - Added stop descriptors logic
+  
+  1.3 - Fixed the busy status so that it doesn't become ready too soon.
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+
+module dispatcher (
+  clk,
+  reset,
+
+  // 128/256 bit write only port for feeding the dispatcher descriptors, no address since it's only one word wide, blocking when too many descriptors are buffered
+  descriptor_writedata,
+  descriptor_byteenable,
+  descriptor_write,
+  descriptor_waitrequest,
+ 
+  // st interface for feeding the dispatcher descriptors. This interface is used if dispatcher descriptor interface is set to ST Source instead of Avalon MM Slave
+  snk_descriptor_data,
+  snk_descriptor_valid,
+  snk_descriptor_ready,
+
+  // control and status port, 32 bits wide with a read latency of 2 and non-blocking
+  csr_writedata,
+  csr_byteenable,
+  csr_write,
+  csr_readdata,
+  csr_read,
+  csr_address,  // 4 addresses when ENHANCED_FEATURES is off (zero) otherwise 8 addresses are available
+  csr_irq,  // only available if the response port is not an ST source (in that case the SGDMA pre-fetching block will issue interrupts)
+
+  // response slave port (when "RESPONSE_PORT" is set to 0), 32 bits wide, read only, and a read latency of 3 cycles
+  mm_response_readdata,
+  mm_response_read,
+  mm_response_address,  // only two addresses
+  mm_response_byteenable,  // last byte read pops the response FIFO
+  mm_response_waitrequest,
+
+  // response source port (when "RESPONSE_PORT" is set to 1), 
+  src_response_data,
+  src_response_valid,
+  src_response_ready,
+
+  // write master source port (sends commands to write master)
+  src_write_master_data,
+  src_write_master_valid,
+  src_write_master_ready,
+
+  // write master sink port (recieves response from write master)
+  snk_write_master_data,
+  snk_write_master_valid,
+  snk_write_master_ready,
+
+  // read master source port (sends commands to read master)
+  src_read_master_data,
+  src_read_master_valid,
+  src_read_master_ready,
+
+  // read master sink port (recieves response from the read master)
+  snk_read_master_data,
+  snk_read_master_valid,
+  snk_read_master_ready
+);
+
+  // y = log2(x)
+  function integer log2;
+    input integer x;
+  begin
+    x = x-1;
+    for(log2=0; x>0; log2=log2+1)
+      x = x>>1;
+  end
+  endfunction
+
+  parameter MODE = 0;                           // 0 for MM->MM, 1 for MM->ST, 2 for ST->MM
+  parameter RESPONSE_PORT = 0;                  // 0 for MM, 1 for ST, 2 for Disabled  // normally disabled for all but ST->MM transfers
+  parameter DESCRIPTOR_FIFO_DEPTH = 128;        // 16-1024 in powers of 2
+  parameter ENHANCED_FEATURES = 1;              // 1 for Enabled, 0 for Disabled
+  parameter DESCRIPTOR_WIDTH = 256;             // 256 when enhanced mode is on, 128 for off (needs to be controlled by callback since it influences data width)
+  parameter DESCRIPTOR_BYTEENABLE_WIDTH = 32;   // 32 when enhanced mode is on, 16 for off (needs to be controlled by callback since it influences byte enable width)
+  parameter CSR_ADDRESS_WIDTH = 3;              // always 3 bits wide
+  parameter DESCRIPTOR_INTERFACE = 0;           // 0: Avalon MM Slave, 1:Avalon ST Source
+  localparam RESPONSE_FIFO_DEPTH = 2 * DESCRIPTOR_FIFO_DEPTH;
+  localparam DESCRIPTOR_FIFO_DEPTH_LOG2 = log2(DESCRIPTOR_FIFO_DEPTH);
+  localparam RESPONSE_FIFO_DEPTH_LOG2 = log2(RESPONSE_FIFO_DEPTH);
+
+
+  input clk;
+  input reset;
+
+  input [DESCRIPTOR_WIDTH-1:0] descriptor_writedata;
+  input [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable;
+  input descriptor_write;
+  output wire descriptor_waitrequest;
+  
+  input [DESCRIPTOR_WIDTH-1:0] snk_descriptor_data;
+  input snk_descriptor_valid;
+  output wire snk_descriptor_ready;
+
+  input [31:0] csr_writedata;
+  input [3:0] csr_byteenable;
+  input csr_write;
+  output wire [31:0] csr_readdata;
+  input csr_read;
+  input [CSR_ADDRESS_WIDTH-1:0] csr_address;
+  output wire csr_irq;
+
+  // Used by a host with a master (like Nios II)
+  output wire [31:0] mm_response_readdata;
+  input mm_response_read;
+  input mm_response_address;
+  input [3:0] mm_response_byteenable;
+  output wire mm_response_waitrequest;
+
+  // Used by a pre-fetching master
+  output wire [255:0] src_response_data;      // making wide in case we need to jam more signals in here, unnecessary bits will be grounded/optimized away
+  output wire src_response_valid;
+  input src_response_ready;
+
+  output wire [255:0] src_write_master_data;  // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away 
+  output wire src_write_master_valid;
+  input src_write_master_ready;
+
+  input [255:0] snk_write_master_data;       // might need to jam more bits in......
+  input snk_write_master_valid;
+  output wire snk_write_master_ready;
+
+  output wire [255:0] src_read_master_data;  // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away 
+  output wire src_read_master_valid;
+  input src_read_master_ready;
+
+  input [255:0] snk_read_master_data;       // might need to jam more bits in......
+  input snk_read_master_valid;
+  output wire snk_read_master_ready;
+
+
+  /* Internal wires and registers */
+  // descriptor information
+  wire read_command_valid;
+  wire read_command_ready;
+  wire [255:0] read_command_data;
+  wire read_command_empty;
+  wire read_command_full;
+  wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] read_command_used;  // true used signal so extra MSB is included
+  wire write_command_valid;
+  wire write_command_ready;
+  wire [255:0] write_command_data;
+  wire write_command_empty;
+  wire write_command_full;
+  wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] write_command_used;  // true used signal so extra MSB is included
+  wire [31:0] sequence_number;
+  wire transfer_complete_IRQ_mask;
+  wire early_termination_IRQ_mask;
+  wire [7:0] error_IRQ_mask;
+  wire descriptor_buffer_empty;
+  wire descriptor_buffer_full;
+  wire [15:0] write_descriptor_watermark;
+  wire [15:0] read_descriptor_watermark;
+  wire [31:0] descriptor_watermark;
+
+
+  wire busy;
+  reg  all_transfers_done;
+  wire done_strobe;
+  wire stop_issuing_commands;
+  wire stop;
+  wire sw_reset;
+  wire stop_on_error;
+  wire stop_on_early_termination;
+  wire stop_descriptors;
+  wire reset_stalled;
+  wire master_stop_state;
+  wire descriptors_stop_state;
+  wire stop_state;
+  wire stopped_on_error;
+  wire stopped_on_early_termination;
+  wire response_fifo_full;
+  wire response_fifo_empty;
+  wire [15:0] response_watermark;
+  wire [7:0] response_error;
+  wire response_early_termination;
+  wire [31:0] response_actual_bytes_transferred;
+
+  wire [DESCRIPTOR_WIDTH-1:0] descriptor_writedata_int;
+  wire [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable_int;
+  wire descriptor_write_int;
+  wire descriptor_waitrequest_int;
+  
+  /************************************************ REGISTERS *******************************************************/
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      all_transfers_done <= 1;
+    end
+    else if (((done_strobe == 1) & (read_command_empty == 1) & (write_command_empty == 1)) | (sw_reset == 1))
+    begin
+      all_transfers_done <= 1;  // no more descriptors are buffered and the last transfer completed
+    end
+    else if ((read_command_empty == 0) | (write_command_empty == 0))
+    begin
+      all_transfers_done <= 0;  // at least one descriptor has been buffered, this will deassert two clock cycles after the first descriptor is written into the descriptor FIFO
+    end
+  end
+
+
+  /********************************************** END REGISTERS *****************************************************/
+
+
+  /******************************************* MODULE DECLERATIONS **************************************************/
+  // the descriptor buffers block instantiates the descriptor FIFOs and handshaking logic with the master command ports
+  descriptor_buffers the_descriptor_buffers (
+    .clk (clk),
+    .reset (reset),
+    .writedata (descriptor_writedata_int),
+    .write (descriptor_write_int),
+    .byteenable (descriptor_byteenable_int),
+    .waitrequest (descriptor_waitrequest_int),
+    .read_command_valid (read_command_valid),
+    .read_command_ready (read_command_ready),
+    .read_command_data (read_command_data),
+    .read_command_empty (read_command_empty),
+    .read_command_full (read_command_full),
+    .read_command_used (read_command_used),
+    .write_command_valid (write_command_valid),
+    .write_command_ready (write_command_ready),
+    .write_command_data (write_command_data),
+    .write_command_empty (write_command_empty),
+    .write_command_full (write_command_full),
+    .write_command_used (write_command_used),
+    .stop_issuing_commands (stop_issuing_commands),
+    .stop (stop),
+    .sw_reset (sw_reset),
+    .sequence_number (sequence_number),
+    .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
+    .early_termination_IRQ_mask (early_termination_IRQ_mask),
+    .error_IRQ_mask (error_IRQ_mask)
+  );
+  defparam the_descriptor_buffers.MODE = MODE;
+  defparam the_descriptor_buffers.DATA_WIDTH = DESCRIPTOR_WIDTH;
+  defparam the_descriptor_buffers.BYTE_ENABLE_WIDTH = DESCRIPTOR_WIDTH/8;
+  defparam the_descriptor_buffers.FIFO_DEPTH = DESCRIPTOR_FIFO_DEPTH;
+  defparam the_descriptor_buffers.FIFO_DEPTH_LOG2 = DESCRIPTOR_FIFO_DEPTH_LOG2;
+
+
+
+
+
+  // Control and status registers (and interrupts when a host connects directly to this block)
+  csr_block the_csr_block (
+    .clk (clk),
+    .reset (reset),
+    .csr_writedata (csr_writedata),
+    .csr_write (csr_write),
+    .csr_byteenable (csr_byteenable),
+    .csr_readdata (csr_readdata),
+    .csr_read (csr_read),
+    .csr_address (csr_address),
+    .csr_irq (csr_irq),
+    .done_strobe (done_strobe),
+    .busy (busy),
+    .descriptor_buffer_empty (descriptor_buffer_empty),
+    .descriptor_buffer_full (descriptor_buffer_full),
+    .stop_state (stop_state),
+    .stopped_on_error (stopped_on_error),
+    .stopped_on_early_termination (stopped_on_early_termination),
+    .stop_descriptors (stop_descriptors),
+    .reset_stalled (reset_stalled),    // from the master(s) to tell the CSR block that it's still resetting
+    .stop (stop),
+    .sw_reset (sw_reset),
+    .stop_on_error (stop_on_error),
+    .stop_on_early_termination (stop_on_early_termination),
+    .sequence_number (sequence_number),
+    .descriptor_watermark (descriptor_watermark),
+    .response_watermark (response_watermark),
+    .response_buffer_empty (response_fifo_empty),
+    .response_buffer_full (response_fifo_full),
+    .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
+    .error_IRQ_mask (error_IRQ_mask),
+    .early_termination_IRQ_mask (early_termination_IRQ_mask),
+    .error (response_error),
+    .early_termination (response_early_termination)
+  );
+  defparam the_csr_block.ADDRESS_WIDTH = CSR_ADDRESS_WIDTH;
+
+
+  // Optional response port.  When using a directly connected host it'll be a slave port and using a pre-fetching descriptor master it will be a streaming source port.
+  response_block the_response_block (
+    .clk (clk),
+    .reset (reset),
+    .mm_response_readdata (mm_response_readdata),
+    .mm_response_read (mm_response_read),
+    .mm_response_address (mm_response_address),
+    .mm_response_byteenable (mm_response_byteenable),
+    .mm_response_waitrequest (mm_response_waitrequest),
+    .src_response_data (src_response_data),
+    .src_response_valid (src_response_valid),
+    .src_response_ready (src_response_ready),
+    .sw_reset (sw_reset),
+    .response_watermark (response_watermark),
+    .response_fifo_full (response_fifo_full),
+    .response_fifo_empty (response_fifo_empty),
+    .done_strobe (done_strobe),
+    .actual_bytes_transferred (response_actual_bytes_transferred),
+    .error (response_error),
+    .early_termination (response_early_termination),
+    .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
+    .error_IRQ_mask (error_IRQ_mask),
+    .early_termination_IRQ_mask (early_termination_IRQ_mask),
+    .descriptor_buffer_full (descriptor_buffer_full)
+  );
+  defparam the_response_block.RESPONSE_PORT = RESPONSE_PORT;
+  defparam the_response_block.FIFO_DEPTH = RESPONSE_FIFO_DEPTH;
+  defparam the_response_block.FIFO_DEPTH_LOG2 = RESPONSE_FIFO_DEPTH_LOG2;
+  /***************************************** END MODULE DECLERATIONS ************************************************/
+
+
+  /****************************************** COMBINATIONAL SIGNALS *************************************************/
+  // this block issues the commands so it's always ready for a response.  The response FIFO fill level will be used to
+  // make sure additional ST-->MM commands are not issued if there is no room to catch the response.
+  assign snk_write_master_ready = 1'b1;
+  assign snk_read_master_ready = 1'b1;
+
+  // since the snk_read/write_master_valid is always high a completed response from the master should always be accepted in one clock cycle and so we generate the strobe based on that condition
+  assign done_strobe = (MODE == 1)? (snk_read_master_ready & snk_read_master_valid) : (snk_write_master_ready & snk_write_master_valid);
+
+  assign stop_issuing_commands = (response_fifo_full == 1) | (stop_descriptors == 1);
+  assign src_write_master_valid = write_command_valid;
+  assign write_command_ready = src_write_master_ready;
+  assign src_write_master_data = write_command_data;
+  assign src_read_master_valid = read_command_valid;
+  assign read_command_ready = src_read_master_ready;
+  assign src_read_master_data = read_command_data;
+  assign busy = (all_transfers_done == 0);  // transfers are still occuring
+
+  assign descriptor_buffer_empty = (read_command_empty == 1) & (write_command_empty == 1);
+  assign descriptor_buffer_full = (read_command_full == 1) | (write_command_full == 1);
+  assign write_descriptor_watermark = 16'h0000 | write_command_used;  // zero padding the upper unused bits
+  assign read_descriptor_watermark = 16'h0000 | read_command_used;  // zero padding the upper unused bits
+  assign descriptor_watermark = {write_descriptor_watermark, read_descriptor_watermark};
+
+  assign reset_stalled = snk_read_master_data[0] | snk_write_master_data[32];
+  assign master_stop_state = ((MODE == 0)? (snk_read_master_data[1] & snk_write_master_data[33]) :
+                              (MODE == 1)? snk_read_master_data[1] : snk_write_master_data[33]);
+  assign descriptors_stop_state = (stop_descriptors == 1) & ((MODE == 0)? ((src_read_master_ready == 1) & (src_write_master_ready == 1)) :
+                                                           (MODE == 1)? (src_read_master_ready == 1) : (src_write_master_ready == 1));
+  assign stop_state = (master_stop_state == 1) | (descriptors_stop_state == 1);
+
+  assign response_actual_bytes_transferred = snk_write_master_data[31:0];
+  assign response_error = snk_write_master_data[41:34];
+  assign response_early_termination = snk_write_master_data[42];
+
+  // descriptor interface muxes
+  assign descriptor_writedata_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_writedata : snk_descriptor_data;
+  assign descriptor_byteenable_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_byteenable : {DESCRIPTOR_BYTEENABLE_WIDTH{1'b1}};
+  assign descriptor_write_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_write : snk_descriptor_valid;
+  assign descriptor_waitrequest = (DESCRIPTOR_INTERFACE == 0) ? descriptor_waitrequest_int : 1'b1;
+  assign snk_descriptor_ready = (DESCRIPTOR_INTERFACE == 0) ? 1'b0 : ~descriptor_waitrequest_int;
+
+  /**************************************** END COMBINATIONAL SIGNALS ***********************************************/
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/div.qip b/FPGA_firmware/q_sys/synthesis/submodules/div.qip
new file mode 100644
index 0000000..4cb52ad
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/div.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_DIVIDE"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "div.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "div.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "div_inst.v"]
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/div.v b/FPGA_firmware/q_sys/synthesis/submodules/div.v
new file mode 100644
index 0000000..5d50d2d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/div.v
@@ -0,0 +1,116 @@
+// megafunction wizard: %LPM_DIVIDE%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_DIVIDE 
+
+// ============================================================
+// File Name: div.v
+// Megafunction Name(s):
+// 			LPM_DIVIDE
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module div (
+	clken,
+	clock,
+	denom,
+	numer,
+	quotient,
+	remain);
+
+	input	  clken;
+	input	  clock;
+	input	[29:0]  denom;
+	input	[39:0]  numer;
+	output	[39:0]  quotient;
+	output	[29:0]  remain;
+
+	wire [39:0] sub_wire0;
+	wire [29:0] sub_wire1;
+	wire [39:0] quotient = sub_wire0[39:0];
+	wire [29:0] remain = sub_wire1[29:0];
+
+	lpm_divide	LPM_DIVIDE_component (
+				.clken (clken),
+				.clock (clock),
+				.denom (denom),
+				.numer (numer),
+				.quotient (sub_wire0),
+				.remain (sub_wire1),
+				.aclr (1'b0));
+	defparam
+		LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
+		LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_pipeline = 26,
+		LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
+		LPM_DIVIDE_component.lpm_widthd = 30,
+		LPM_DIVIDE_component.lpm_widthn = 40;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
+// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
+// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "26"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
+// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "30"
+// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "40"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: denom 0 0 30 0 INPUT NODEFVAL "denom[29..0]"
+// Retrieval info: USED_PORT: numer 0 0 40 0 INPUT NODEFVAL "numer[39..0]"
+// Retrieval info: USED_PORT: quotient 0 0 40 0 OUTPUT NODEFVAL "quotient[39..0]"
+// Retrieval info: USED_PORT: remain 0 0 30 0 OUTPUT NODEFVAL "remain[29..0]"
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @denom 0 0 30 0 denom 0 0 30 0
+// Retrieval info: CONNECT: @numer 0 0 40 0 numer 0 0 40 0
+// Retrieval info: CONNECT: quotient 0 0 40 0 @quotient 0 0 40 0
+// Retrieval info: CONNECT: remain 0 0 30 0 @remain 0 0 30 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE
+// Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/fifo_with_byteenables.v b/FPGA_firmware/q_sys/synthesis/submodules/fifo_with_byteenables.v
new file mode 100644
index 0000000..73afb61
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/fifo_with_byteenables.v
@@ -0,0 +1,185 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This FIFO module behaves similar to scfifo in legacy mode.  It has an
+  output latency of 1 or 2 clock cycles and does not support look ahead
+  mode.  Unlike scfifo this FIFO allows you to write to any of the byte
+  lanes before committing the word.  This allows you to write the full
+  word in multiple clock cycles and then you assert the "push" signal to
+  commit the data.  To read data out of the FIFO assert "pop" and wait
+  1 or 2 clock cycles for valid data to arrive.
+  
+  Version 1.1
+  
+  1.0 - Uses 'altsyncram' which will not be optimized away if the
+        FIFO inputs are grounded.  This will need to be replaced
+        with inferred memory once Quartus II supports inferred
+        with byte enables (currently it instantiates multiple
+        seperate memories.
+
+  1.1 - Seperated the asynchronous reset into seperate async. and sync.
+        resets.
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module fifo_with_byteenables (
+  clk,
+  areset,
+  sreset,
+  write_data,
+  write_byteenables,
+  write,
+  push,
+  read_data,
+  pop,
+  used,
+  full,
+  empty
+);
+
+
+  parameter DATA_WIDTH = 32;
+  parameter FIFO_DEPTH = 128;
+  parameter FIFO_DEPTH_LOG2 = 7;  // this impacts the width of the used port so it can't be local
+  parameter LATENCY = 1;  // number of clock cycles after asserting 'pop' that valid data comes out
+
+
+
+  input clk;
+  input areset;
+  input sreset;
+  input [DATA_WIDTH-1:0] write_data;
+  input [(DATA_WIDTH/8)-1:0] write_byteenables;
+  input write;
+  input push;  // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
+  output wire [DATA_WIDTH-1:0] read_data;
+  input pop;   // use this to read a word out of the FIFO
+  output wire [FIFO_DEPTH_LOG2:0] used;
+  output wire full;
+  output wire empty;
+
+  reg [FIFO_DEPTH_LOG2-1:0] write_address;
+  reg [FIFO_DEPTH_LOG2-1:0] read_address;
+  reg [FIFO_DEPTH_LOG2:0] internal_used;
+  wire internal_full;
+  wire internal_empty;
+
+
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      write_address <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        write_address <= 0;
+      end
+      else if (push == 1)
+      begin
+        write_address <= write_address + 1'b1;
+      end
+    end
+  end
+
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      read_address <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        read_address <= 0;
+      end
+      else if (pop == 1)
+      begin
+        read_address <= read_address + 1'b1;
+      end
+    end
+  end
+
+
+  // TODO:  Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
+  altsyncram the_dp_ram (
+    .clock0 (clk),
+    .wren_a (write),
+    .byteena_a (write_byteenables),
+    .data_a (write_data),
+    .address_a (write_address),
+    .q_b (read_data),
+    .address_b (read_address)
+  );
+  defparam the_dp_ram.operation_mode = "DUAL_PORT";  // simple dual port (one read, one write port)
+  defparam the_dp_ram.lpm_type = "altsyncram";
+  defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
+  defparam the_dp_ram.power_up_uninitialized = "TRUE";
+  defparam the_dp_ram.byte_size = 8;
+  defparam the_dp_ram.width_a = DATA_WIDTH;
+  defparam the_dp_ram.width_b = DATA_WIDTH;
+  defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
+  defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
+  defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
+  defparam the_dp_ram.numwords_a = FIFO_DEPTH;
+  defparam the_dp_ram.numwords_b = FIFO_DEPTH;
+  defparam the_dp_ram.address_reg_b = "CLOCK0";
+  defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
+
+
+  
+  always @ (posedge clk or posedge areset)
+  begin
+    if (areset)
+    begin
+      internal_used <= 0;
+    end
+    else
+    begin
+      if (sreset)
+      begin
+        internal_used <= 0;
+      end
+      else
+      begin
+        case ({push, pop})
+          2'b01: internal_used <= internal_used - 1'b1;
+          2'b10: internal_used <= internal_used + 1'b1;
+          default: internal_used <= internal_used;
+        endcase
+      end
+    end
+  end
+
+
+  assign internal_empty = (read_address == write_address) & (internal_used == 0);
+  assign internal_full = (write_address == read_address) & (internal_used != 0);
+
+  assign used = internal_used;    // this signal reflects the number of words in the FIFO
+  assign empty = internal_empty;  // combinational so it'll glitch a little bit
+  assign full = internal_full;    // dito
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/frame_counter.v b/FPGA_firmware/q_sys/synthesis/submodules/frame_counter.v
new file mode 100644
index 0000000..2df7a6d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/frame_counter.v
@@ -0,0 +1,36 @@
+//the frame counter
+//count the frame number by the sensor_interface status_out[0] rising edge
+
+
+
+module frame_counter(
+	
+	input wire clk_clk,
+	input wire rst_reset, //this reset should connect to sensor_interface int_rst
+	
+	input wire sig,
+	input wire [31:0] data_in, //for connect in qsys only
+	input wire data_in_endofpacket, // for connect in qsys only
+	
+	output reg [26:0] frame_Num
+);
+
+
+	reg sig_last;
+	
+	always @(posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			sig_last <= 1'b0;
+			frame_Num <= 27'b0;
+		end
+		else 
+		begin
+			sig_last <= sig;
+			if (~sig_last&&sig)
+				frame_Num <= frame_Num + 1'b1; 
+		end
+	end
+			
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/max10emif_dcfifo.sv b/FPGA_firmware/q_sys/synthesis/submodules/max10emif_dcfifo.sv
new file mode 100644
index 0000000..6d28ca6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/max10emif_dcfifo.sv
@@ -0,0 +1,69 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module max10emif_dcfifo #
+    ( parameter
+        numwords = 8,
+        width = 24,
+        widthu = 3
+    )
+    (
+    data,
+    rdclk,
+    rdreq,
+    wrclk,
+    wrreq,
+    q,
+    aclr
+);
+
+    input   [width-1:0] data;
+    input   rdclk;
+    input   rdreq;
+    input   wrclk;
+    input   wrreq;
+    output  [width-1:0] q;
+    input   aclr;
+    
+    logic   [widthu-1:0] rdptr;
+    logic   [widthu-1:0] wrptr;
+    
+    
+    always_ff @ (posedge wrclk or posedge aclr)
+        begin
+            if (aclr)
+                wrptr    <=    0;
+            else
+                wrptr    <=    wrptr + wrreq;
+        end
+    
+    
+    always_ff @ (posedge rdclk or posedge aclr)
+        begin
+            if (aclr)
+                rdptr    <=    0;
+            else
+                rdptr    <=    rdptr + rdreq;
+        end
+    
+    
+    logic    [width-1:0]    fifo    [numwords-1:0];
+    
+    always_ff @ (posedge wrclk)
+        fifo [wrptr]    <=    data;
+    
+    assign    q = fifo[rdptr];
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_altpll_shift.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_altpll_shift.v
new file mode 100644
index 0000000..0143d03
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_altpll_shift.v
@@ -0,0 +1,335 @@
+//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 clk configupdate locked phasecounterselect phasedone phasestep phaseupdown read readdata reset scanclk scanclkena scandata write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="15000" clk2_divide_by=20 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
+//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_altiobuf_bidir 2019:09:22:08:02:34:SJ cbx_altiobuf_in 2019:09:22:08:02:34:SJ cbx_altiobuf_out 2019:09:22:08:02:34:SJ cbx_altpll 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_counter 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_lpm_shiftreg 2019:09:22:08:02:34:SJ cbx_max10_altpll_avalon 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+
+//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
+//VERSION_BEGIN 19.1 cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+
+//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 19.1 cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+//synthesis_resources = reg 3 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
+module  q_sys_altpll_shift_dffpipe_l2c
+	( 
+	clock,
+	clrn,
+	d,
+	q) /* synthesis synthesis_clearbox=1 */;
+	input   clock;
+	input   clrn;
+	input   [0:0]  d;
+	output   [0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   clock;
+	tri1   clrn;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	reg	[0:0]	dffe4a;
+	reg	[0:0]	dffe5a;
+	reg	[0:0]	dffe6a;
+	wire ena;
+	wire prn;
+	wire sclr;
+
+	// synopsys translate_off
+	initial
+		dffe4a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe4a <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a <= (d & (~ sclr));
+	// synopsys translate_off
+	initial
+		dffe5a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe5a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe5a <= 1'b0;
+		else if  (ena == 1'b1)   dffe5a <= (dffe4a & (~ sclr));
+	// synopsys translate_off
+	initial
+		dffe6a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe6a <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a <= (dffe5a & (~ sclr));
+	assign
+		ena = 1'b1,
+		prn = 1'b1,
+		q = dffe6a,
+		sclr = 1'b0;
+endmodule //q_sys_altpll_shift_dffpipe_l2c
+
+//synthesis_resources = reg 3 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_altpll_shift_stdsync_sv6
+	( 
+	clk,
+	din,
+	dout,
+	reset_n) /* synthesis synthesis_clearbox=1 */;
+	input   clk;
+	input   din;
+	output   dout;
+	input   reset_n;
+
+	wire  [0:0]   wire_dffpipe3_q;
+
+	q_sys_altpll_shift_dffpipe_l2c   dffpipe3
+	( 
+	.clock(clk),
+	.clrn(reset_n),
+	.d(din),
+	.q(wire_dffpipe3_q));
+	assign
+		dout = wire_dffpipe3_q;
+endmodule //q_sys_altpll_shift_stdsync_sv6
+
+
+//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="15000" clk2_divide_by=20 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
+//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_altiobuf_bidir 2019:09:22:08:02:34:SJ cbx_altiobuf_in 2019:09:22:08:02:34:SJ cbx_altiobuf_out 2019:09:22:08:02:34:SJ cbx_altpll 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_counter 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+//synthesis_resources = fiftyfivenm_pll 1 reg 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
+module  q_sys_altpll_shift_altpll_7ig2
+	( 
+	areset,
+	clk,
+	inclk,
+	locked) /* synthesis synthesis_clearbox=1 */;
+	input   areset;
+	output   [4:0]  clk;
+	input   [1:0]  inclk;
+	output   locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   areset;
+	tri0   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	reg	pll_lock_sync;
+	wire  [4:0]   wire_pll7_clk;
+	wire  wire_pll7_fbout;
+	wire  wire_pll7_locked;
+
+	// synopsys translate_off
+	initial
+		pll_lock_sync = 0;
+	// synopsys translate_on
+	always @ ( posedge wire_pll7_locked or  posedge areset)
+		if (areset == 1'b1) pll_lock_sync <= 1'b0;
+		else  pll_lock_sync <= 1'b1;
+	fiftyfivenm_pll   pll7
+	( 
+	.activeclock(),
+	.areset(areset),
+	.clk(wire_pll7_clk),
+	.clkbad(),
+	.fbin(wire_pll7_fbout),
+	.fbout(wire_pll7_fbout),
+	.inclk(inclk),
+	.locked(wire_pll7_locked),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.vcooverrange(),
+	.vcounderrange()
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.clkswitch(1'b0),
+	.configupdate(1'b0),
+	.pfdena(1'b1),
+	.phasecounterselect({3{1'b0}}),
+	.phasestep(1'b0),
+	.phaseupdown(1'b0),
+	.scanclk(1'b0),
+	.scanclkena(1'b1),
+	.scandata(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pll7.bandwidth_type = "auto",
+		pll7.clk0_divide_by = 1,
+		pll7.clk0_duty_cycle = 50,
+		pll7.clk0_multiply_by = 5,
+		pll7.clk0_phase_shift = "0",
+		pll7.clk1_divide_by = 2,
+		pll7.clk1_duty_cycle = 50,
+		pll7.clk1_multiply_by = 1,
+		pll7.clk1_phase_shift = "15000",
+		pll7.clk2_divide_by = 20,
+		pll7.clk2_duty_cycle = 50,
+		pll7.clk2_multiply_by = 1,
+		pll7.clk2_phase_shift = "0",
+		pll7.compensate_clock = "clk0",
+		pll7.inclk0_input_frequency = 20000,
+		pll7.operation_mode = "normal",
+		pll7.pll_type = "auto",
+		pll7.lpm_type = "fiftyfivenm_pll";
+	assign
+		clk = {wire_pll7_clk[4:0]},
+		locked = (wire_pll7_locked & pll_lock_sync);
+endmodule //q_sys_altpll_shift_altpll_7ig2
+
+//synthesis_resources = fiftyfivenm_pll 1 reg 6 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_altpll_shift
+	( 
+	address,
+	areset,
+	c0,
+	c1,
+	c2,
+	c3,
+	c4,
+	clk,
+	configupdate,
+	locked,
+	phasecounterselect,
+	phasedone,
+	phasestep,
+	phaseupdown,
+	read,
+	readdata,
+	reset,
+	scanclk,
+	scanclkena,
+	scandata,
+	scandataout,
+	scandone,
+	write,
+	writedata) /* synthesis synthesis_clearbox=1 */;
+	input   [1:0]  address;
+	input   areset;
+	output   c0;
+	output   c1;
+	output   c2;
+	output   c3;
+	output   c4;
+	input   clk;
+	input   configupdate;
+	output   locked;
+	input   [2:0]  phasecounterselect;
+	output   phasedone;
+	input   phasestep;
+	input   phaseupdown;
+	input   read;
+	output   [31:0]  readdata;
+	input   reset;
+	input   scanclk;
+	input   scanclkena;
+	input   scandata;
+	output   scandataout;
+	output   scandone;
+	input   write;
+	input   [31:0]  writedata;
+
+	wire  wire_stdsync2_dout;
+	wire  [4:0]   wire_sd1_clk;
+	wire  wire_sd1_locked;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+	reg	pfdena_reg;
+	wire	wire_pfdena_reg_ena;
+	reg	prev_reset;
+	wire  w_locked;
+	wire  w_pfdena;
+	wire  w_phasedone;
+	wire  w_pll_areset_in;
+	wire  w_reset;
+	wire  w_select_control;
+	wire  w_select_status;
+
+	q_sys_altpll_shift_stdsync_sv6   stdsync2
+	( 
+	.clk(clk),
+	.din(wire_sd1_locked),
+	.dout(wire_stdsync2_dout),
+	.reset_n((~ reset)));
+	q_sys_altpll_shift_altpll_7ig2   sd1
+	( 
+	.areset((w_pll_areset_in | areset)),
+	.clk(wire_sd1_clk),
+	.inclk({{1{1'b0}}, clk}),
+	.locked(wire_sd1_locked));
+	// synopsys translate_off
+	initial
+		pfdena_reg = {1{1'b1}};
+	// synopsys translate_on
+	always @ ( posedge clk or  posedge reset)
+		if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
+		else if  (wire_pfdena_reg_ena == 1'b1)   pfdena_reg <= writedata[1];
+	assign
+		wire_pfdena_reg_ena = (write & w_select_control);
+	// synopsys translate_off
+	initial
+		prev_reset = 0;
+	// synopsys translate_on
+	always @ ( posedge clk or  posedge reset)
+		if (reset == 1'b1) prev_reset <= 1'b0;
+		else  prev_reset <= w_reset;
+	assign
+		c0 = wire_sd1_clk[0],
+		c1 = wire_sd1_clk[1],
+		c2 = wire_sd1_clk[2],
+		c3 = wire_sd1_clk[3],
+		c4 = wire_sd1_clk[4],
+		locked = wire_sd1_locked,
+		phasedone = 1'b0,
+		readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
+		scandataout = 1'b0,
+		scandone = 1'b0,
+		w_locked = wire_stdsync2_dout,
+		w_pfdena = pfdena_reg,
+		w_phasedone = 1'b1,
+		w_pll_areset_in = prev_reset,
+		w_reset = ((write & w_select_control) & writedata[0]),
+		w_select_control = ((~ address[1]) & address[0]),
+		w_select_status = ((~ address[1]) & (~ address[0]));
+endmodule //q_sys_altpll_shift
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v
new file mode 100644
index 0000000..b23f8a0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v
@@ -0,0 +1,214 @@
+// q_sys_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 32,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 1,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		output wire [31:0] out_0_data,          //    out_0.data
+		output wire        out_0_valid,         //         .valid
+		input  wire        out_0_ready,         //         .ready
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket,   //         .endofpacket
+		output wire [1:0]  out_0_empty,         //         .empty
+		output wire [0:0]  out_0_error          //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk               (in_clk_0_clk),        //   clk.clk
+		.reset_n           (~in_rst_0_reset),     // reset.reset_n
+		.in_data           (in_0_data),           //    in.data
+		.in_valid          (in_0_valid),          //      .valid
+		.in_ready          (in_0_ready),          //      .ready
+		.in_startofpacket  (in_0_startofpacket),  //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),    //      .endofpacket
+		.in_empty          (in_0_empty),          //      .empty
+		.out_data          (out_0_data),          //   out.data
+		.out_valid         (out_0_valid),         //      .valid
+		.out_ready         (out_0_ready),         //      .ready
+		.out_startofpacket (out_0_startofpacket), //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket),   //      .endofpacket
+		.out_empty         (out_0_empty),         //      .empty
+		.out_error         (out_0_error)          //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v
new file mode 100644
index 0000000..56b2a3e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v
@@ -0,0 +1,216 @@
+// q_sys_avalon_st_adapter_001.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_avalon_st_adapter_001 #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 6,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 2,
+		parameter outDataWidth    = 32,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 6,
+		parameter outUseEmptyPort = 1,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		input  wire [5:0]  in_0_error,          //         .error
+		output wire [31:0] out_0_data,          //    out_0.data
+		output wire        out_0_valid,         //         .valid
+		input  wire        out_0_ready,         //         .ready
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket,   //         .endofpacket
+		output wire [1:0]  out_0_empty,         //         .empty
+		output wire [5:0]  out_0_error          //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 6)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 2)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 6)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_avalon_st_adapter_001_timing_adapter_0 timing_adapter_0 (
+		.clk               (in_clk_0_clk),        //   clk.clk
+		.reset_n           (~in_rst_0_reset),     // reset.reset_n
+		.in_data           (in_0_data),           //    in.data
+		.in_valid          (in_0_valid),          //      .valid
+		.in_ready          (in_0_ready),          //      .ready
+		.in_startofpacket  (in_0_startofpacket),  //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),    //      .endofpacket
+		.in_empty          (in_0_empty),          //      .empty
+		.in_error          (in_0_error),          //      .error
+		.out_data          (out_0_data),          //   out.data
+		.out_valid         (out_0_valid),         //      .valid
+		.out_ready         (out_0_ready),         //      .ready
+		.out_startofpacket (out_0_startofpacket), //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket),   //      .endofpacket
+		.out_empty         (out_0_empty),         //      .empty
+		.out_error         (out_0_error)          //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_error_adapter_0.sv
new file mode 100644
index 0000000..28ddc69
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_error_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_001_error_adapter_0
+//   use_ready:          true
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      0
+//   in_error_width:     1
+//   out_error_width:    6
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_avalon_st_adapter_001_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1: 0]     in_data,
+ input [0:0]		 in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1: 0]     in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg [6-1: 0] out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+      out_empty = in_empty;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv
new file mode 100644
index 0000000..fac40f3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv
@@ -0,0 +1,132 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_001_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      true
+//   in_use_valid:       true
+//   out_use_valid:      true
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        6
+//   in_ready_latency:   2
+//   out_ready_latency:  0
+//   in_payload_width:   42
+//   out_payload_width:  42
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket,in_empty,in_error
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket,out_empty,out_error
+// ------------------------------------------
+
+
+
+module q_sys_avalon_st_adapter_001_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input     [6-1: 0] in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input     [2-1: 0] in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg [6-1: 0] out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg  [42-1:0]   in_payload;
+   wire [42-1:0]   out_payload;
+   wire            in_ready_wire;
+   wire            out_valid_wire;
+   wire [4:0]      fifo_fill;
+   reg [1-1:0]   ready;   
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket,in_empty,in_error};
+     {out_data,out_startofpacket,out_endofpacket,out_empty,out_error} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| FIFO
+   // ---------------------------------------------------------------------                           
+   q_sys_avalon_st_adapter_001_timing_adapter_0_fifo q_sys_avalon_st_adapter_001_timing_adapter_0_fifo 
+     ( 
+       .clk        (clk),
+       .reset_n    (reset_n),
+       .in_ready   (),
+       .in_valid   (in_valid),      
+       .in_data    (in_payload),
+       .out_ready  (ready[0]),
+       .out_valid  (out_valid_wire),      
+       .out_data   (out_payload),
+       .fill_level (fifo_fill)
+       );
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always @* begin
+      in_ready = (fifo_fill < 5 );
+      out_valid = out_valid_wire;
+      ready[0] = out_ready;
+   end
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv
new file mode 100644
index 0000000..a13a0bd
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv
@@ -0,0 +1,163 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../simpleFifo.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner$
+
+//  --------------------------------------------------------------------------------
+// | simple_atlantic_fifo
+//  --------------------------------------------------------------------------------
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_001_timing_adapter_0_fifo
+//   depth:              16
+//   depthBits:          4
+//   data_width          42
+//   use_fill_level:     true
+//   in_use_ready:       true
+//   in_use_valid:       true
+//   out_use_ready:      true
+//   out_use_valid:      true
+//   out_ready_latency:  0
+//   in_ready_latency:   0
+// ------------------------------------------
+
+`timescale 1ns / 100ps
+
+module q_sys_avalon_st_adapter_001_timing_adapter_0_fifo (
+  output reg [4:0] fill_level,
+                     
+//Interface: in
+  output reg         in_ready,
+  input              in_valid,
+  input [42-1:0]      in_data,
+//Interface: out
+  input              out_ready,
+  output reg         out_valid,
+  output reg [42-1:0] out_data,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+/*AUTOARG*/);
+
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   parameter DEPTH = 16;
+   parameter DATA_WIDTH = 42;   
+   parameter ADDR_WIDTH = 4;
+             
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [ADDR_WIDTH-1:0] wr_addr;
+   reg [ADDR_WIDTH-1:0] rd_addr;
+   reg [ADDR_WIDTH-1:0] next_wr_addr;
+   reg [ADDR_WIDTH-1:0] next_rd_addr;
+   reg [ADDR_WIDTH-1:0] mem_rd_addr;
+   reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
+   reg                  empty;
+   reg                  full;
+
+   reg [0:0] out_ready_vector;
+   
+   // ---------------------------------------------------------------------
+   //| FIFO Status
+   // ---------------------------------------------------------------------
+   always @* begin
+//      out_valid = !empty;
+      out_ready_vector[0] = out_ready;
+      in_ready  = !full;
+      next_wr_addr = wr_addr + 1'b1;
+      next_rd_addr = rd_addr + 1'b1;
+      fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
+      fill_level[ADDR_WIDTH] = 0;
+      if (full)
+        fill_level = DEPTH[ADDR_WIDTH:0];
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Manage Pointers
+   // ---------------------------------------------------------------------
+   always @ (negedge reset_n, posedge clk) begin
+      if (!reset_n) begin
+       wr_addr   <= 0;
+       rd_addr   <= 0;
+       empty     <= 1;
+       rd_addr   <= 0;
+       full      <= 0;
+       out_valid <= 0;
+      end else begin
+       out_valid <= !empty;
+       if (in_ready && in_valid) begin
+        wr_addr <= next_wr_addr;
+        empty   <= 0;
+        if (next_wr_addr == rd_addr)
+         full <= 1;
+      end
+              
+      if (out_ready_vector[0] && out_valid) begin
+        rd_addr <= next_rd_addr;
+        full    <= 0;
+        if (next_rd_addr == wr_addr) begin
+          empty <= 1;
+          out_valid <= 0;
+        end
+      end
+                                               
+      if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
+        full  <= full;
+        empty <= empty;
+      end
+    end
+   end // always @ (negedge reset_n, posedge clk)
+   
+   always @* begin
+      mem_rd_addr = rd_addr;
+      if (out_ready && out_valid) begin
+        mem_rd_addr = next_rd_addr;
+      end
+   end
+   
+
+   // ---------------------------------------------------------------------
+   //| Infer Memory
+   // ---------------------------------------------------------------------
+   always @ (posedge clk) begin
+      if (in_ready && in_valid)
+        mem[wr_addr] <= in_data;
+      out_data <= mem[mem_rd_addr];
+   end
+   
+endmodule // simple_atlantic_fifo
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002.v
new file mode 100644
index 0000000..bd45b95
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002.v
@@ -0,0 +1,214 @@
+// q_sys_avalon_st_adapter_002.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_avalon_st_adapter_002 #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 1,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 32,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 0,
+		parameter outUseEmptyPort = 1,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		input  wire [0:0]  in_0_error,          //         .error
+		output wire [31:0] out_0_data,          //    out_0.data
+		output wire        out_0_valid,         //         .valid
+		input  wire        out_0_ready,         //         .ready
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket,   //         .endofpacket
+		output wire [1:0]  out_0_empty          //         .empty
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_avalon_st_adapter_002_error_adapter_0 error_adapter_0 (
+		.clk               (in_clk_0_clk),        //   clk.clk
+		.reset_n           (~in_rst_0_reset),     // reset.reset_n
+		.in_data           (in_0_data),           //    in.data
+		.in_valid          (in_0_valid),          //      .valid
+		.in_ready          (in_0_ready),          //      .ready
+		.in_startofpacket  (in_0_startofpacket),  //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),    //      .endofpacket
+		.in_empty          (in_0_empty),          //      .empty
+		.in_error          (in_0_error),          //      .error
+		.out_data          (out_0_data),          //   out.data
+		.out_valid         (out_0_valid),         //      .valid
+		.out_ready         (out_0_ready),         //      .ready
+		.out_startofpacket (out_0_startofpacket), //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket),   //      .endofpacket
+		.out_empty         (out_0_empty)          //      .empty
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002_error_adapter_0.sv
new file mode 100644
index 0000000..0a13b4a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_002_error_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_002_error_adapter_0
+//   use_ready:          true
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      0
+//   in_error_width:     1
+//   out_error_width:    0
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_avalon_st_adapter_002_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1: 0]     in_data,
+ input [0:0]		 in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1: 0]     in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg out_error; 
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+      out_empty = in_empty;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_channel_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_channel_adapter_0.sv
new file mode 100644
index 0000000..43cf8bc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_channel_adapter_0.sv
@@ -0,0 +1,106 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Channel Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_avalon_st_adapter_channel_adapter_0
+//   in_channel_width:    1
+//   in_max_channel:      1
+//   out_channel_width:   0
+//   out_max_channel:     0
+//   data_width:          32
+//   error_width:         1
+//   use_ready:           true
+//   use_packets:         true
+//   use_empty:           1
+//   empty_width:         2
+
+// ------------------------------------------
+
+
+module q_sys_avalon_st_adapter_channel_adapter_0 
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input     [32-1: 0] in_data,
+ input              in_channel,
+ input              in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1: 0] in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg          out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+ 
+ 
+);
+
+    reg out_channel;
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+      out_error = in_error;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+      out_empty = in_empty;
+
+      out_channel = in_channel; //TODO delete this to avoid Quartus warnings
+
+      // Suppress channels that are higher than the destination's max_channel.
+      if (in_channel > 0) begin
+         out_valid = 0;
+         // Simulation Message goes here.
+      end
+   end
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..7b41c4d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,116 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1: 0]     in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1: 0]     in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg [0:0]         out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+      out_empty = in_empty;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
new file mode 100644
index 0000000..168a093
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0.sv
@@ -0,0 +1,132 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      true
+//   in_use_valid:       true
+//   out_use_valid:      true
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        6
+//   in_ready_latency:   2
+//   out_ready_latency:  0
+//   in_payload_width:   42
+//   out_payload_width:  42
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket,in_empty,in_error
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket,out_empty,out_error
+// ------------------------------------------
+
+
+
+module q_sys_avalon_st_adapter_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input     [6-1: 0] in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input     [2-1: 0] in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg [6-1: 0] out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg  [42-1:0]   in_payload;
+   wire [42-1:0]   out_payload;
+   wire            in_ready_wire;
+   wire            out_valid_wire;
+   wire [4:0]      fifo_fill;
+   reg [1-1:0]   ready;   
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket,in_empty,in_error};
+     {out_data,out_startofpacket,out_endofpacket,out_empty,out_error} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| FIFO
+   // ---------------------------------------------------------------------                           
+   q_sys_avalon_st_adapter_timing_adapter_0_fifo q_sys_avalon_st_adapter_timing_adapter_0_fifo 
+     ( 
+       .clk        (clk),
+       .reset_n    (reset_n),
+       .in_ready   (),
+       .in_valid   (in_valid),      
+       .in_data    (in_payload),
+       .out_ready  (ready[0]),
+       .out_valid  (out_valid_wire),      
+       .out_data   (out_payload),
+       .fill_level (fifo_fill)
+       );
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always @* begin
+      in_ready = (fifo_fill < 5 );
+      out_valid = out_valid_wire;
+      ready[0] = out_ready;
+   end
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
new file mode 100644
index 0000000..a543c20
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_timing_adapter_0_fifo.sv
@@ -0,0 +1,163 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../simpleFifo.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner$
+
+//  --------------------------------------------------------------------------------
+// | simple_atlantic_fifo
+//  --------------------------------------------------------------------------------
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_avalon_st_adapter_timing_adapter_0_fifo
+//   depth:              16
+//   depthBits:          4
+//   data_width          42
+//   use_fill_level:     true
+//   in_use_ready:       true
+//   in_use_valid:       true
+//   out_use_ready:      true
+//   out_use_valid:      true
+//   out_ready_latency:  0
+//   in_ready_latency:   0
+// ------------------------------------------
+
+`timescale 1ns / 100ps
+
+module q_sys_avalon_st_adapter_timing_adapter_0_fifo (
+  output reg [4:0] fill_level,
+                     
+//Interface: in
+  output reg         in_ready,
+  input              in_valid,
+  input [42-1:0]      in_data,
+//Interface: out
+  input              out_ready,
+  output reg         out_valid,
+  output reg [42-1:0] out_data,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+/*AUTOARG*/);
+
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   parameter DEPTH = 16;
+   parameter DATA_WIDTH = 42;   
+   parameter ADDR_WIDTH = 4;
+             
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [ADDR_WIDTH-1:0] wr_addr;
+   reg [ADDR_WIDTH-1:0] rd_addr;
+   reg [ADDR_WIDTH-1:0] next_wr_addr;
+   reg [ADDR_WIDTH-1:0] next_rd_addr;
+   reg [ADDR_WIDTH-1:0] mem_rd_addr;
+   reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
+   reg                  empty;
+   reg                  full;
+
+   reg [0:0] out_ready_vector;
+   
+   // ---------------------------------------------------------------------
+   //| FIFO Status
+   // ---------------------------------------------------------------------
+   always @* begin
+//      out_valid = !empty;
+      out_ready_vector[0] = out_ready;
+      in_ready  = !full;
+      next_wr_addr = wr_addr + 1'b1;
+      next_rd_addr = rd_addr + 1'b1;
+      fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
+      fill_level[ADDR_WIDTH] = 0;
+      if (full)
+        fill_level = DEPTH[ADDR_WIDTH:0];
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Manage Pointers
+   // ---------------------------------------------------------------------
+   always @ (negedge reset_n, posedge clk) begin
+      if (!reset_n) begin
+       wr_addr   <= 0;
+       rd_addr   <= 0;
+       empty     <= 1;
+       rd_addr   <= 0;
+       full      <= 0;
+       out_valid <= 0;
+      end else begin
+       out_valid <= !empty;
+       if (in_ready && in_valid) begin
+        wr_addr <= next_wr_addr;
+        empty   <= 0;
+        if (next_wr_addr == rd_addr)
+         full <= 1;
+      end
+              
+      if (out_ready_vector[0] && out_valid) begin
+        rd_addr <= next_rd_addr;
+        full    <= 0;
+        if (next_rd_addr == wr_addr) begin
+          empty <= 1;
+          out_valid <= 0;
+        end
+      end
+                                               
+      if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
+        full  <= full;
+        empty <= empty;
+      end
+    end
+   end // always @ (negedge reset_n, posedge clk)
+   
+   always @* begin
+      mem_rd_addr = rd_addr;
+      if (out_ready && out_valid) begin
+        mem_rd_addr = next_rd_addr;
+      end
+   end
+   
+
+   // ---------------------------------------------------------------------
+   //| Infer Memory
+   // ---------------------------------------------------------------------
+   always @ (posedge clk) begin
+      if (in_ready && in_valid)
+        mem[wr_addr] <= in_data;
+      out_data <= mem[mem_rd_addr];
+   end
+   
+endmodule // simple_atlantic_fifo
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_button_pio.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_button_pio.v
new file mode 100644
index 0000000..cf32dd5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_button_pio.v
@@ -0,0 +1,59 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_button_pio (
+                          // inputs:
+                           address,
+                           clk,
+                           in_port,
+                           reset_n,
+
+                          // outputs:
+                           readdata
+                        )
+;
+
+  output  [ 31: 0] readdata;
+  input   [  1: 0] address;
+  input            clk;
+  input   [  8: 0] in_port;
+  input            reset_n;
+
+
+wire             clk_en;
+wire    [  8: 0] data_in;
+wire    [  8: 0] read_mux_out;
+reg     [ 31: 0] readdata;
+  assign clk_en = 1;
+  //s1, which is an e_avalon_slave
+  assign read_mux_out = {9 {(address == 0)}} & data_in;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          readdata <= 0;
+      else if (clk_en)
+          readdata <= {32'b0 | read_mux_out};
+    end
+
+
+  assign data_in = in_port;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cali_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cali_ram.v
new file mode 100644
index 0000000..4e79123
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cali_ram.v
@@ -0,0 +1,83 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cali_ram (
+                        // inputs:
+                         address,
+                         chipselect,
+                         clk,
+                         clken,
+                         freeze,
+                         reset,
+                         reset_req,
+                         write,
+                         writedata,
+
+                        // outputs:
+                         readdata
+                      )
+;
+
+  output  [  7: 0] readdata;
+  input   [  8: 0] address;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [  7: 0] writedata;
+
+
+wire             clocken0;
+wire    [  7: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=CALI",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 512,
+           the_altsyncram.numwords_a = 512,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 8,
+           the_altsyncram.widthad_a = 9;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_calibration_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_calibration_ram.v
new file mode 100644
index 0000000..c24fb89
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_calibration_ram.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_calibration_ram (
+                               // inputs:
+                                address,
+                                address2,
+                                byteenable,
+                                byteenable2,
+                                chipselect,
+                                chipselect2,
+                                clk,
+                                clk2,
+                                clken,
+                                clken2,
+                                freeze,
+                                reset,
+                                reset2,
+                                reset_req,
+                                reset_req2,
+                                write,
+                                write2,
+                                writedata,
+                                writedata2,
+
+                               // outputs:
+                                readdata,
+                                readdata2
+                             )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  8: 0] address;
+  input   [  8: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 320,
+           the_altsyncram.numwords_a = 320,
+           the_altsyncram.numwords_b = 320,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 9,
+           the_altsyncram.widthad_b = 9,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv
new file mode 100644
index 0000000..725685c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv
@@ -0,0 +1,101 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Channel Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_channel_adapter_0
+//   in_channel_width:    1
+//   in_max_channel:      1
+//   out_channel_width:   0
+//   out_max_channel:     1
+//   data_width:          32
+//   error_width:         1
+//   use_ready:           true
+//   use_packets:         true
+//   use_empty:           1
+//   empty_width:         2
+
+// ------------------------------------------
+
+
+module q_sys_channel_adapter_0 
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input     [32-1: 0] in_data,
+ input              in_channel,
+ input              in_error,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1: 0] in_empty,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [32-1: 0] out_data,
+ output reg          out_error,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+ output reg [2-1: 0] out_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+ 
+ 
+);
+
+    reg out_channel;
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+      out_error = in_error;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+      out_empty = in_empty;
+
+      out_channel = in_channel; //TODO delete this to avoid Quartus warnings
+
+   end
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu.v
new file mode 100644
index 0000000..2e2e21b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu.v
@@ -0,0 +1,71 @@
+// q_sys_cpu.v
+
+// This file was auto-generated from altera_nios2_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_cpu (
+		input  wire        clk,                                 //                       clk.clk
+		input  wire        reset_n,                             //                     reset.reset_n
+		input  wire        reset_req,                           //                          .reset_req
+		output wire [28:0] d_address,                           //               data_master.address
+		output wire [3:0]  d_byteenable,                        //                          .byteenable
+		output wire        d_read,                              //                          .read
+		input  wire [31:0] d_readdata,                          //                          .readdata
+		input  wire        d_waitrequest,                       //                          .waitrequest
+		output wire        d_write,                             //                          .write
+		output wire [31:0] d_writedata,                         //                          .writedata
+		input  wire        d_readdatavalid,                     //                          .readdatavalid
+		output wire        debug_mem_slave_debugaccess_to_roms, //                          .debugaccess
+		output wire [28:0] i_address,                           //        instruction_master.address
+		output wire        i_read,                              //                          .read
+		input  wire [31:0] i_readdata,                          //                          .readdata
+		input  wire        i_waitrequest,                       //                          .waitrequest
+		input  wire        i_readdatavalid,                     //                          .readdatavalid
+		input  wire [31:0] irq,                                 //                       irq.irq
+		output wire        debug_reset_request,                 //       debug_reset_request.reset
+		input  wire [8:0]  debug_mem_slave_address,             //           debug_mem_slave.address
+		input  wire [3:0]  debug_mem_slave_byteenable,          //                          .byteenable
+		input  wire        debug_mem_slave_debugaccess,         //                          .debugaccess
+		input  wire        debug_mem_slave_read,                //                          .read
+		output wire [31:0] debug_mem_slave_readdata,            //                          .readdata
+		output wire        debug_mem_slave_waitrequest,         //                          .waitrequest
+		input  wire        debug_mem_slave_write,               //                          .write
+		input  wire [31:0] debug_mem_slave_writedata,           //                          .writedata
+		output wire        dummy_ci_port                        // custom_instruction_master.readra
+	);
+
+	q_sys_cpu_cpu cpu (
+		.clk                                 (clk),                                 //                       clk.clk
+		.reset_n                             (reset_n),                             //                     reset.reset_n
+		.reset_req                           (reset_req),                           //                          .reset_req
+		.d_address                           (d_address),                           //               data_master.address
+		.d_byteenable                        (d_byteenable),                        //                          .byteenable
+		.d_read                              (d_read),                              //                          .read
+		.d_readdata                          (d_readdata),                          //                          .readdata
+		.d_waitrequest                       (d_waitrequest),                       //                          .waitrequest
+		.d_write                             (d_write),                             //                          .write
+		.d_writedata                         (d_writedata),                         //                          .writedata
+		.d_readdatavalid                     (d_readdatavalid),                     //                          .readdatavalid
+		.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), //                          .debugaccess
+		.i_address                           (i_address),                           //        instruction_master.address
+		.i_read                              (i_read),                              //                          .read
+		.i_readdata                          (i_readdata),                          //                          .readdata
+		.i_waitrequest                       (i_waitrequest),                       //                          .waitrequest
+		.i_readdatavalid                     (i_readdatavalid),                     //                          .readdatavalid
+		.irq                                 (irq),                                 //                       irq.irq
+		.debug_reset_request                 (debug_reset_request),                 //       debug_reset_request.reset
+		.debug_mem_slave_address             (debug_mem_slave_address),             //           debug_mem_slave.address
+		.debug_mem_slave_byteenable          (debug_mem_slave_byteenable),          //                          .byteenable
+		.debug_mem_slave_debugaccess         (debug_mem_slave_debugaccess),         //                          .debugaccess
+		.debug_mem_slave_read                (debug_mem_slave_read),                //                          .read
+		.debug_mem_slave_readdata            (debug_mem_slave_readdata),            //                          .readdata
+		.debug_mem_slave_waitrequest         (debug_mem_slave_waitrequest),         //                          .waitrequest
+		.debug_mem_slave_write               (debug_mem_slave_write),               //                          .write
+		.debug_mem_slave_writedata           (debug_mem_slave_writedata),           //                          .writedata
+		.dummy_ci_port                       (dummy_ci_port)                        // custom_instruction_master.readra
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.ocp b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..23e7aed9ee93b8934d4e0ae2ca0a2e0ce688fa7a
GIT binary patch
literal 848
zcmV-W1F!sx6Pzyv00aQyk63i=U?jDY<fX$IkWG0!1b%&*LE-5aH9#eLH<(692V9^q
zpzba10XYRlO?WCXxB+wG>fUy>97nsU?2v94egTsDr`IuKXA`t0Ms%td=o8Jo3>Da`
z6JzcgxK6lfTylhj@_CHF;6Y0UOJ3Z1nxa*ggjzb0JL~sLQ1C(^)%8w~wn6whk->|#
zZfD{|Q+F6$bzmDv(4b$P@JH?blstbnXo`Z}Q;+&<q*Im^pZ|7QdSC-K2jFn?(!=g#
z@HY8lN`bEcc`n4{*M1Puyx*O=Mbo@sKVB~qa*Z|`8{I=B$w(+Fn2=6cFnRHnu_6HA
zK`a<XHrHIrr$>2?u^ZzrE;A8*V!X1`X|@-n08iNq_W;<+#F2!+Gc7`)00GcyJo>Fe
zUB9z(uVrD??ho$tST7JJaCe1wQQK@}-I^IuC3!&)45_lqiKYAZK+S=D_+17O<x1OY
z>Y|;RVj+y3%NZURi>adrp37gqQV*67zwl)E@H>S#Nrc+>RkPkyBPj?+dGum#+kNc(
zR{J6`vvuqXGJ9fRjJ4`(mZ;=(d~Ntd%pf^Yh3qOsT9?B2<L-%DL$E%jG{Pr^3u{;o
zVw*SWvl3(yrQ4Y_YNu|C0N*7#X^_{P+2qW=Y!}tZRf5bB)gEg%rV?z(&@m;=HR4#>
z7_s53%YGol59Bb<XQwQHn_HgH*q5AygEDODoNI<(9LTDoU5d6;E&pOsXKq^#2v%{*
zN9ckp+=d?OW_KLT0h&44$))%D85vPD;7KPPQG(;GN6PD{L0*#W5iJa`G?NRJ8xe^s
zd{z&v`-){Z49B@=9CZ6`liUEh=bfvaM=ni^sR7HPV!}Jej_@TEqoGe??if&?(dt-x
z3^KbXWtNd*PsbvBUD0gZX=gs8wQaFd52S117kTRUMpyxOa@^3Vdsgr)>!Jor{RzKG
z7N6Z-d{vr*asC~~h~GMt3qV_CuUhWGf%8jmrErc_2K+v?eCCiZ|EHgVr7fMomCLR8
zZ`Q(G*>T0MBY`J?EFMgsK9Q;SKzSNy|2f}tOAH;v)xt%fpGZ@_0XX>aAFa&oU+Z;-
aFD8#K1S=mELUj^2dZ^6TUbR>-+5XbM6r9@t

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc
new file mode 100644
index 0000000..2e2b009
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc
@@ -0,0 +1,53 @@
+# Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+# use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any
+# output files any of the foregoing (including device programming or
+# simulation files), and any associated documentation or information are
+# expressly subject to the terms and conditions of the Altera Program
+# License Subscription Agreement or other applicable license agreement,
+# including, without limitation, that your use is for the sole purpose
+# of programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors.  Please refer to the applicable
+# agreement for further details.
+
+#**************************************************************
+# Timequest JTAG clock definition
+#   Uncommenting the following lines will define the JTAG
+#   clock in TimeQuest Timing Analyzer
+#**************************************************************
+
+#create_clock -period 10MHz {altera_reserved_tck}
+#set_clock_groups -asynchronous -group {altera_reserved_tck}
+
+#**************************************************************
+# Set TCL Path Variables 
+#**************************************************************
+
+set 	q_sys_cpu_cpu 	q_sys_cpu_cpu:*
+set 	q_sys_cpu_cpu_oci 	q_sys_cpu_cpu_nios2_oci:the_q_sys_cpu_cpu_nios2_oci
+set 	q_sys_cpu_cpu_oci_break 	q_sys_cpu_cpu_nios2_oci_break:the_q_sys_cpu_cpu_nios2_oci_break
+set 	q_sys_cpu_cpu_ocimem 	q_sys_cpu_cpu_nios2_ocimem:the_q_sys_cpu_cpu_nios2_ocimem
+set 	q_sys_cpu_cpu_oci_debug 	q_sys_cpu_cpu_nios2_oci_debug:the_q_sys_cpu_cpu_nios2_oci_debug
+set 	q_sys_cpu_cpu_wrapper 	q_sys_cpu_cpu_debug_slave_wrapper:the_q_sys_cpu_cpu_debug_slave_wrapper
+set 	q_sys_cpu_cpu_jtag_tck 	q_sys_cpu_cpu_debug_slave_tck:the_q_sys_cpu_cpu_debug_slave_tck
+set 	q_sys_cpu_cpu_jtag_sysclk 	q_sys_cpu_cpu_debug_slave_sysclk:the_q_sys_cpu_cpu_debug_slave_sysclk
+set 	q_sys_cpu_cpu_oci_path 	 [format "%s|%s" $q_sys_cpu_cpu $q_sys_cpu_cpu_oci]
+set 	q_sys_cpu_cpu_oci_break_path 	 [format "%s|%s" $q_sys_cpu_cpu_oci_path $q_sys_cpu_cpu_oci_break]
+set 	q_sys_cpu_cpu_ocimem_path 	 [format "%s|%s" $q_sys_cpu_cpu_oci_path $q_sys_cpu_cpu_ocimem]
+set 	q_sys_cpu_cpu_oci_debug_path 	 [format "%s|%s" $q_sys_cpu_cpu_oci_path $q_sys_cpu_cpu_oci_debug]
+set 	q_sys_cpu_cpu_jtag_tck_path 	 [format "%s|%s|%s" $q_sys_cpu_cpu_oci_path $q_sys_cpu_cpu_wrapper $q_sys_cpu_cpu_jtag_tck]
+set 	q_sys_cpu_cpu_jtag_sysclk_path 	 [format "%s|%s|%s" $q_sys_cpu_cpu_oci_path $q_sys_cpu_cpu_wrapper $q_sys_cpu_cpu_jtag_sysclk]
+set 	q_sys_cpu_cpu_jtag_sr 	 [format "%s|*sr" $q_sys_cpu_cpu_jtag_tck_path]
+
+#**************************************************************
+# Set False Paths
+#**************************************************************
+
+set_false_path -from [get_keepers *$q_sys_cpu_cpu_oci_break_path|break_readreg*] -to [get_keepers *$q_sys_cpu_cpu_jtag_sr*]
+set_false_path -from [get_keepers *$q_sys_cpu_cpu_oci_debug_path|*resetlatch]     -to [get_keepers *$q_sys_cpu_cpu_jtag_sr[33]]
+set_false_path -from [get_keepers *$q_sys_cpu_cpu_oci_debug_path|monitor_ready]  -to [get_keepers *$q_sys_cpu_cpu_jtag_sr[0]]
+set_false_path -from [get_keepers *$q_sys_cpu_cpu_oci_debug_path|monitor_error]  -to [get_keepers *$q_sys_cpu_cpu_jtag_sr[34]]
+set_false_path -from [get_keepers *$q_sys_cpu_cpu_ocimem_path|*MonDReg*] -to [get_keepers *$q_sys_cpu_cpu_jtag_sr*]
+set_false_path -from *$q_sys_cpu_cpu_jtag_sr*    -to *$q_sys_cpu_cpu_jtag_sysclk_path|*jdo*
+set_false_path -from sld_hub:*|irf_reg* -to *$q_sys_cpu_cpu_jtag_sysclk_path|ir*
+set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$q_sys_cpu_cpu_oci_debug_path|monitor_go
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.v
new file mode 100644
index 0000000..ef3591b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu.v
@@ -0,0 +1,14962 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_ic_data_module (
+                                      // inputs:
+                                       clock,
+                                       data,
+                                       rdaddress,
+                                       rden,
+                                       wraddress,
+                                       wren,
+
+                                      // outputs:
+                                       q
+                                    )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  8: 0] rdaddress;
+  input            rden;
+  input   [  8: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .rden_b (rden),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 512,
+           the_altsyncram.numwords_b = 512,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 9,
+           the_altsyncram.widthad_b = 9;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_ic_tag_module (
+                                     // inputs:
+                                      clock,
+                                      data,
+                                      rdaddress,
+                                      rden,
+                                      wraddress,
+                                      wren,
+
+                                     // outputs:
+                                      q
+                                   )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 25: 0] q;
+  input            clock;
+  input   [ 25: 0] data;
+  input   [  5: 0] rdaddress;
+  input            rden;
+  input   [  5: 0] wraddress;
+  input            wren;
+
+
+wire    [ 25: 0] q;
+wire    [ 25: 0] ram_data;
+wire    [ 25: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .rden_b (rden),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 64,
+           the_altsyncram.numwords_b = 64,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 26,
+           the_altsyncram.width_b = 26,
+           the_altsyncram.widthad_a = 6,
+           the_altsyncram.widthad_b = 6;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_bht_module (
+                                  // inputs:
+                                   clock,
+                                   data,
+                                   rdaddress,
+                                   rden,
+                                   wraddress,
+                                   wren,
+
+                                  // outputs:
+                                   q
+                                )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [  1: 0] q;
+  input            clock;
+  input   [  1: 0] data;
+  input   [  7: 0] rdaddress;
+  input            rden;
+  input   [  7: 0] wraddress;
+  input            wren;
+
+
+wire    [  1: 0] q;
+wire    [  1: 0] ram_data;
+wire    [  1: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .rden_b (rden),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 256,
+           the_altsyncram.numwords_b = 256,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 2,
+           the_altsyncram.width_b = 2,
+           the_altsyncram.widthad_a = 8,
+           the_altsyncram.widthad_b = 8;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_register_bank_a_module (
+                                              // inputs:
+                                               clock,
+                                               data,
+                                               rdaddress,
+                                               wraddress,
+                                               wren,
+
+                                              // outputs:
+                                               q
+                                            )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  4: 0] rdaddress;
+  input   [  4: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 32,
+           the_altsyncram.numwords_b = 32,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 5,
+           the_altsyncram.widthad_b = 5;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_register_bank_b_module (
+                                              // inputs:
+                                               clock,
+                                               data,
+                                               rdaddress,
+                                               wraddress,
+                                               wren,
+
+                                              // outputs:
+                                               q
+                                            )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  4: 0] rdaddress;
+  input   [  4: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 32,
+           the_altsyncram.numwords_b = 32,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 5,
+           the_altsyncram.widthad_b = 5;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_dc_tag_module (
+                                     // inputs:
+                                      clock,
+                                      data,
+                                      rdaddress,
+                                      wraddress,
+                                      wren,
+
+                                     // outputs:
+                                      q
+                                   )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 19: 0] q;
+  input            clock;
+  input   [ 19: 0] data;
+  input   [  5: 0] rdaddress;
+  input   [  5: 0] wraddress;
+  input            wren;
+
+
+wire    [ 19: 0] q;
+wire    [ 19: 0] ram_data;
+wire    [ 19: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 64,
+           the_altsyncram.numwords_b = 64,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 20,
+           the_altsyncram.width_b = 20,
+           the_altsyncram.widthad_a = 6,
+           the_altsyncram.widthad_b = 6;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_dc_data_module (
+                                      // inputs:
+                                       byteenable,
+                                       clock,
+                                       data,
+                                       rdaddress,
+                                       wraddress,
+                                       wren,
+
+                                      // outputs:
+                                       q
+                                    )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input   [  3: 0] byteenable;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  8: 0] rdaddress;
+  input   [  8: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .byteena_a (byteenable),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 512,
+           the_altsyncram.numwords_b = 512,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 9,
+           the_altsyncram.widthad_b = 9;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_dc_victim_module (
+                                        // inputs:
+                                         clock,
+                                         data,
+                                         rdaddress,
+                                         rden,
+                                         wraddress,
+                                         wren,
+
+                                        // outputs:
+                                         q
+                                      )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  2: 0] rdaddress;
+  input            rden;
+  input   [  2: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .rden_b (rden),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 8,
+           the_altsyncram.numwords_b = 8,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 3,
+           the_altsyncram.widthad_b = 3;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_debug (
+                                       // inputs:
+                                        clk,
+                                        dbrk_break,
+                                        debugreq,
+                                        hbreak_enabled,
+                                        jdo,
+                                        jrst_n,
+                                        ocireg_ers,
+                                        ocireg_mrs,
+                                        reset,
+                                        st_ready_test_idle,
+                                        take_action_ocimem_a,
+                                        take_action_ocireg,
+                                        xbrk_break,
+
+                                       // outputs:
+                                        E_oci_sync_hbreak_req,
+                                        debugack,
+                                        monitor_error,
+                                        monitor_go,
+                                        monitor_ready,
+                                        oci_async_hbreak_req,
+                                        resetlatch,
+                                        resetrequest
+                                     )
+;
+
+  output           E_oci_sync_hbreak_req;
+  output           debugack;
+  output           monitor_error;
+  output           monitor_go;
+  output           monitor_ready;
+  output           oci_async_hbreak_req;
+  output           resetlatch;
+  output           resetrequest;
+  input            clk;
+  input            dbrk_break;
+  input            debugreq;
+  input            hbreak_enabled;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            ocireg_ers;
+  input            ocireg_mrs;
+  input            reset;
+  input            st_ready_test_idle;
+  input            take_action_ocimem_a;
+  input            take_action_ocireg;
+  input            xbrk_break;
+
+
+wire             E_oci_sync_hbreak_req;
+reg              break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             debugack;
+reg              jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+reg              monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+reg              monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+wire             oci_async_hbreak_req;
+wire             reset_sync;
+reg              resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             unxcomplemented_resetxx0;
+  assign unxcomplemented_resetxx0 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer
+    (
+      .clk (clk),
+      .din (reset),
+      .dout (reset_sync),
+      .reset_n (unxcomplemented_resetxx0)
+    );
+
+  defparam the_altera_std_synchronizer.depth = 2;
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          resetrequest <= 1'b0;
+          break_on_reset <= 1'b0;
+          jtag_break <= 1'b0;
+        end
+      else if (take_action_ocimem_a)
+        begin
+          resetrequest <= jdo[22];
+          jtag_break <= jdo[21]     ? 1 
+                    : jdo[20]  ? 0 
+                    : jtag_break;
+
+          break_on_reset <= jdo[19]     ? 1
+                    : jdo[18]  ? 0
+                    :  break_on_reset;
+
+          resetlatch <= jdo[24] ? 0 : resetlatch;
+        end
+      else if (reset_sync)
+        begin
+          jtag_break <= break_on_reset;
+          resetlatch <= 1;
+        end
+      else if (debugreq & ~debugack & break_on_reset)
+          jtag_break <= 1'b1;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          monitor_ready <= 1'b0;
+          monitor_error <= 1'b0;
+          monitor_go <= 1'b0;
+        end
+      else 
+        begin
+          if (take_action_ocimem_a && jdo[25])
+              monitor_ready <= 1'b0;
+          else if (take_action_ocireg && ocireg_mrs)
+              monitor_ready <= 1'b1;
+          if (take_action_ocimem_a && jdo[25])
+              monitor_error <= 1'b0;
+          else if (take_action_ocireg && ocireg_ers)
+              monitor_error <= 1'b1;
+          if (take_action_ocimem_a && jdo[23])
+              monitor_go <= 1'b1;
+          else if (st_ready_test_idle)
+              monitor_go <= 1'b0;
+        end
+    end
+
+
+  assign oci_async_hbreak_req = jtag_break | dbrk_break | debugreq;
+  assign E_oci_sync_hbreak_req = xbrk_break;
+  assign debugack = ~hbreak_enabled;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_break (
+                                       // inputs:
+                                        clk,
+                                        dbrk_break,
+                                        dbrk_goto0,
+                                        dbrk_goto1,
+                                        jdo,
+                                        jrst_n,
+                                        take_action_break_a,
+                                        take_action_break_b,
+                                        take_action_break_c,
+                                        take_no_action_break_a,
+                                        take_no_action_break_b,
+                                        take_no_action_break_c,
+                                        xbrk_goto0,
+                                        xbrk_goto1,
+
+                                       // outputs:
+                                        break_readreg,
+                                        dbrk_hit0_latch,
+                                        dbrk_hit1_latch,
+                                        dbrk_hit2_latch,
+                                        dbrk_hit3_latch,
+                                        trigbrktype,
+                                        trigger_state_0,
+                                        trigger_state_1,
+                                        xbrk0,
+                                        xbrk1,
+                                        xbrk_ctrl0,
+                                        xbrk_ctrl1,
+                                        xbrk_ctrl2,
+                                        xbrk_ctrl3
+                                     )
+;
+
+  output  [ 31: 0] break_readreg;
+  output           dbrk_hit0_latch;
+  output           dbrk_hit1_latch;
+  output           dbrk_hit2_latch;
+  output           dbrk_hit3_latch;
+  output           trigbrktype;
+  output           trigger_state_0;
+  output           trigger_state_1;
+  output  [ 28: 0] xbrk0;
+  output  [ 28: 0] xbrk1;
+  output  [  7: 0] xbrk_ctrl0;
+  output  [  7: 0] xbrk_ctrl1;
+  output  [  7: 0] xbrk_ctrl2;
+  output  [  7: 0] xbrk_ctrl3;
+  input            clk;
+  input            dbrk_break;
+  input            dbrk_goto0;
+  input            dbrk_goto1;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            take_action_break_a;
+  input            take_action_break_b;
+  input            take_action_break_c;
+  input            take_no_action_break_a;
+  input            take_no_action_break_b;
+  input            take_no_action_break_c;
+  input            xbrk_goto0;
+  input            xbrk_goto1;
+
+
+wire    [  3: 0] break_a_wpr;
+wire    [  1: 0] break_a_wpr_high_bits;
+wire    [  1: 0] break_a_wpr_low_bits;
+wire    [  1: 0] break_b_rr;
+wire    [  1: 0] break_c_rr;
+reg     [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             dbrk0_high_value;
+wire             dbrk0_low_value;
+wire             dbrk1_high_value;
+wire             dbrk1_low_value;
+wire             dbrk2_high_value;
+wire             dbrk2_low_value;
+wire             dbrk3_high_value;
+wire             dbrk3_low_value;
+wire             dbrk_hit0_latch;
+wire             dbrk_hit1_latch;
+wire             dbrk_hit2_latch;
+wire             dbrk_hit3_latch;
+wire             take_action_any_break;
+reg              trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              trigger_state;
+wire             trigger_state_0;
+wire             trigger_state_1;
+reg     [ 28: 0] xbrk0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire    [ 31: 0] xbrk0_value;
+reg     [ 28: 0] xbrk1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire    [ 31: 0] xbrk1_value;
+wire    [ 31: 0] xbrk2_value;
+wire    [ 31: 0] xbrk3_value;
+reg     [  7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+  assign break_a_wpr = jdo[35 : 32];
+  assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
+  assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
+  assign break_b_rr = jdo[33 : 32];
+  assign break_c_rr = jdo[33 : 32];
+  assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          xbrk_ctrl0 <= 0;
+          xbrk_ctrl1 <= 0;
+          xbrk_ctrl2 <= 0;
+          xbrk_ctrl3 <= 0;
+          trigbrktype <= 0;
+        end
+      else 
+        begin
+          if (take_action_any_break)
+              trigbrktype <= 0;
+          else if (dbrk_break)
+              trigbrktype <= 1;
+          if (take_action_break_b)
+            begin
+              if ((break_b_rr == 2'b00) && (2 >= 1))
+                begin
+                  xbrk_ctrl0[0] <= jdo[27];
+                  xbrk_ctrl0[1] <= jdo[28];
+                  xbrk_ctrl0[2] <= jdo[29];
+                  xbrk_ctrl0[3] <= jdo[30];
+                  xbrk_ctrl0[4] <= jdo[21];
+                  xbrk_ctrl0[5] <= jdo[20];
+                  xbrk_ctrl0[6] <= jdo[19];
+                  xbrk_ctrl0[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b01) && (2 >= 2))
+                begin
+                  xbrk_ctrl1[0] <= jdo[27];
+                  xbrk_ctrl1[1] <= jdo[28];
+                  xbrk_ctrl1[2] <= jdo[29];
+                  xbrk_ctrl1[3] <= jdo[30];
+                  xbrk_ctrl1[4] <= jdo[21];
+                  xbrk_ctrl1[5] <= jdo[20];
+                  xbrk_ctrl1[6] <= jdo[19];
+                  xbrk_ctrl1[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b10) && (2 >= 3))
+                begin
+                  xbrk_ctrl2[0] <= jdo[27];
+                  xbrk_ctrl2[1] <= jdo[28];
+                  xbrk_ctrl2[2] <= jdo[29];
+                  xbrk_ctrl2[3] <= jdo[30];
+                  xbrk_ctrl2[4] <= jdo[21];
+                  xbrk_ctrl2[5] <= jdo[20];
+                  xbrk_ctrl2[6] <= jdo[19];
+                  xbrk_ctrl2[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b11) && (2 >= 4))
+                begin
+                  xbrk_ctrl3[0] <= jdo[27];
+                  xbrk_ctrl3[1] <= jdo[28];
+                  xbrk_ctrl3[2] <= jdo[29];
+                  xbrk_ctrl3[3] <= jdo[30];
+                  xbrk_ctrl3[4] <= jdo[21];
+                  xbrk_ctrl3[5] <= jdo[20];
+                  xbrk_ctrl3[6] <= jdo[19];
+                  xbrk_ctrl3[7] <= jdo[18];
+                end
+            end
+        end
+    end
+
+
+  assign dbrk_hit0_latch = 1'b0;
+  assign dbrk0_low_value = 0;
+  assign dbrk0_high_value = 0;
+  assign dbrk_hit1_latch = 1'b0;
+  assign dbrk1_low_value = 0;
+  assign dbrk1_high_value = 0;
+  assign dbrk_hit2_latch = 1'b0;
+  assign dbrk2_low_value = 0;
+  assign dbrk2_high_value = 0;
+  assign dbrk_hit3_latch = 1'b0;
+  assign dbrk3_low_value = 0;
+  assign dbrk3_high_value = 0;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          xbrk0 <= 0;
+      else if (take_action_break_a 
+                 && (break_a_wpr_high_bits == 0) 
+                 && (break_a_wpr_low_bits == 2'b00))
+          xbrk0[28 : 0] <= jdo[31 : 0];
+    end
+
+
+  assign xbrk0_value = xbrk0;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          xbrk1 <= 0;
+      else if (take_action_break_a 
+                 && (break_a_wpr_high_bits == 0) 
+                 && (break_a_wpr_low_bits == 2'b01))
+          xbrk1[28 : 0] <= jdo[31 : 0];
+    end
+
+
+  assign xbrk1_value = xbrk1;
+  assign xbrk2_value = 32'b0;
+  assign xbrk3_value = 32'b0;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          break_readreg <= 32'b0;
+      else if (take_action_any_break)
+          break_readreg <= jdo[31 : 0];
+      else if (take_no_action_break_a)
+          case (break_a_wpr_high_bits)
+          
+              2'd0: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= xbrk0_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= xbrk1_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= xbrk2_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= xbrk3_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd0 
+          
+              2'd1: begin
+                  break_readreg <= 32'b0;
+              end // 2'd1 
+          
+              2'd2: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= dbrk0_low_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= dbrk1_low_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= dbrk2_low_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= dbrk3_low_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd2 
+          
+              2'd3: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= dbrk0_high_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= dbrk1_high_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= dbrk2_high_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= dbrk3_high_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd3 
+          
+          endcase // break_a_wpr_high_bits
+      else if (take_no_action_break_b)
+          break_readreg <= jdo[31 : 0];
+      else if (take_no_action_break_c)
+          break_readreg <= jdo[31 : 0];
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          trigger_state <= 0;
+      else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
+          trigger_state <= 0;
+      else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
+          trigger_state <= -1;
+    end
+
+
+  assign trigger_state_0 = ~trigger_state;
+  assign trigger_state_1 = trigger_state;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_xbrk (
+                                      // inputs:
+                                       D_en,
+                                       E_en,
+                                       E_valid,
+                                       F_pc,
+                                       M_en,
+                                       clk,
+                                       reset_n,
+                                       trigger_state_0,
+                                       trigger_state_1,
+                                       xbrk0,
+                                       xbrk1,
+                                       xbrk_ctrl0,
+                                       xbrk_ctrl1,
+                                       xbrk_ctrl2,
+                                       xbrk_ctrl3,
+
+                                      // outputs:
+                                       xbrk_break,
+                                       xbrk_goto0,
+                                       xbrk_goto1,
+                                       xbrk_traceoff,
+                                       xbrk_traceon,
+                                       xbrk_trigout
+                                    )
+;
+
+  output           xbrk_break;
+  output           xbrk_goto0;
+  output           xbrk_goto1;
+  output           xbrk_traceoff;
+  output           xbrk_traceon;
+  output           xbrk_trigout;
+  input            D_en;
+  input            E_en;
+  input            E_valid;
+  input   [ 26: 0] F_pc;
+  input            M_en;
+  input            clk;
+  input            reset_n;
+  input            trigger_state_0;
+  input            trigger_state_1;
+  input   [ 28: 0] xbrk0;
+  input   [ 28: 0] xbrk1;
+  input   [  7: 0] xbrk_ctrl0;
+  input   [  7: 0] xbrk_ctrl1;
+  input   [  7: 0] xbrk_ctrl2;
+  input   [  7: 0] xbrk_ctrl3;
+
+
+wire             D_cpu_addr_en;
+wire             E_cpu_addr_en;
+reg              E_xbrk_goto0;
+reg              E_xbrk_goto1;
+reg              E_xbrk_traceoff;
+reg              E_xbrk_traceon;
+reg              E_xbrk_trigout;
+reg              M_xbrk_goto0;
+reg              M_xbrk_goto1;
+reg              M_xbrk_traceoff;
+reg              M_xbrk_traceon;
+reg              M_xbrk_trigout;
+wire    [ 28: 0] cpu_i_address;
+wire             xbrk0_armed;
+wire             xbrk0_break_hit;
+wire             xbrk0_goto0_hit;
+wire             xbrk0_goto1_hit;
+wire             xbrk0_toff_hit;
+wire             xbrk0_ton_hit;
+wire             xbrk0_tout_hit;
+wire             xbrk1_armed;
+wire             xbrk1_break_hit;
+wire             xbrk1_goto0_hit;
+wire             xbrk1_goto1_hit;
+wire             xbrk1_toff_hit;
+wire             xbrk1_ton_hit;
+wire             xbrk1_tout_hit;
+wire             xbrk2_armed;
+wire             xbrk2_break_hit;
+wire             xbrk2_goto0_hit;
+wire             xbrk2_goto1_hit;
+wire             xbrk2_toff_hit;
+wire             xbrk2_ton_hit;
+wire             xbrk2_tout_hit;
+wire             xbrk3_armed;
+wire             xbrk3_break_hit;
+wire             xbrk3_goto0_hit;
+wire             xbrk3_goto1_hit;
+wire             xbrk3_toff_hit;
+wire             xbrk3_ton_hit;
+wire             xbrk3_tout_hit;
+reg              xbrk_break;
+wire             xbrk_break_hit;
+wire             xbrk_goto0;
+wire             xbrk_goto0_hit;
+wire             xbrk_goto1;
+wire             xbrk_goto1_hit;
+reg              xbrk_hit0;
+reg              xbrk_hit1;
+wire             xbrk_toff_hit;
+wire             xbrk_ton_hit;
+wire             xbrk_tout_hit;
+wire             xbrk_traceoff;
+wire             xbrk_traceon;
+wire             xbrk_trigout;
+  assign cpu_i_address = {F_pc, 2'b00};
+  assign D_cpu_addr_en = D_en;
+  assign E_cpu_addr_en = E_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          xbrk_hit0 <= 0;
+      else if (D_cpu_addr_en)
+          xbrk_hit0 <= cpu_i_address == xbrk0[28 : 0];
+    end
+
+
+  assign xbrk0_break_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[0];
+  assign xbrk0_ton_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[3];
+  assign xbrk0_toff_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[2];
+  assign xbrk0_tout_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[1];
+  assign xbrk0_goto0_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[6];
+  assign xbrk0_goto1_hit = xbrk_hit0 & xbrk0_armed & xbrk_ctrl0[7];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          xbrk_hit1 <= 0;
+      else if (D_cpu_addr_en)
+          xbrk_hit1 <= cpu_i_address == xbrk1[28 : 0];
+    end
+
+
+  assign xbrk1_break_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[0];
+  assign xbrk1_ton_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[3];
+  assign xbrk1_toff_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[2];
+  assign xbrk1_tout_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[1];
+  assign xbrk1_goto0_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[6];
+  assign xbrk1_goto1_hit = xbrk_hit1 & xbrk1_armed & xbrk_ctrl1[7];
+  assign xbrk2_break_hit = 0;
+  assign xbrk2_ton_hit = 0;
+  assign xbrk2_toff_hit = 0;
+  assign xbrk2_tout_hit = 0;
+  assign xbrk2_goto0_hit = 0;
+  assign xbrk2_goto1_hit = 0;
+  assign xbrk3_break_hit = 0;
+  assign xbrk3_ton_hit = 0;
+  assign xbrk3_toff_hit = 0;
+  assign xbrk3_tout_hit = 0;
+  assign xbrk3_goto0_hit = 0;
+  assign xbrk3_goto1_hit = 0;
+  assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
+  assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
+  assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
+  assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
+  assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
+  assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          xbrk_break <= 0;
+      else if (E_cpu_addr_en)
+          xbrk_break <= xbrk_break_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_traceon <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_traceon <= xbrk_ton_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_traceoff <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_traceoff <= xbrk_toff_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_trigout <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_trigout <= xbrk_tout_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_goto0 <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_goto0 <= xbrk_goto0_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_goto1 <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_goto1 <= xbrk_goto1_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_xbrk_traceon <= 0;
+      else if (M_en)
+          M_xbrk_traceon <= E_xbrk_traceon & E_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_xbrk_traceoff <= 0;
+      else if (M_en)
+          M_xbrk_traceoff <= E_xbrk_traceoff & E_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_xbrk_trigout <= 0;
+      else if (M_en)
+          M_xbrk_trigout <= E_xbrk_trigout & E_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_xbrk_goto0 <= 0;
+      else if (M_en)
+          M_xbrk_goto0 <= E_xbrk_goto0 & E_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_xbrk_goto1 <= 0;
+      else if (M_en)
+          M_xbrk_goto1 <= E_xbrk_goto1 & E_valid;
+    end
+
+
+  assign xbrk_traceon = M_xbrk_traceon;
+  assign xbrk_traceoff = M_xbrk_traceoff;
+  assign xbrk_trigout = M_xbrk_trigout;
+  assign xbrk_goto0 = M_xbrk_goto0;
+  assign xbrk_goto1 = M_xbrk_goto1;
+  assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
+    (xbrk_ctrl0[5] & trigger_state_1);
+
+  assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
+    (xbrk_ctrl1[5] & trigger_state_1);
+
+  assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
+    (xbrk_ctrl2[5] & trigger_state_1);
+
+  assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
+    (xbrk_ctrl3[5] & trigger_state_1);
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_dbrk (
+                                      // inputs:
+                                       A_ctrl_ld,
+                                       A_ctrl_st,
+                                       A_en,
+                                       A_ld_data,
+                                       A_mem_baddr,
+                                       A_st_data,
+                                       A_valid,
+                                       clk,
+                                       debugack,
+                                       reset_n,
+
+                                      // outputs:
+                                       cpu_d_address,
+                                       cpu_d_read,
+                                       cpu_d_readdata,
+                                       cpu_d_wait,
+                                       cpu_d_write,
+                                       cpu_d_writedata,
+                                       dbrk_break,
+                                       dbrk_goto0,
+                                       dbrk_goto1,
+                                       dbrk_traceme,
+                                       dbrk_traceoff,
+                                       dbrk_traceon,
+                                       dbrk_trigout
+                                    )
+;
+
+  output  [ 28: 0] cpu_d_address;
+  output           cpu_d_read;
+  output  [ 31: 0] cpu_d_readdata;
+  output           cpu_d_wait;
+  output           cpu_d_write;
+  output  [ 31: 0] cpu_d_writedata;
+  output           dbrk_break;
+  output           dbrk_goto0;
+  output           dbrk_goto1;
+  output           dbrk_traceme;
+  output           dbrk_traceoff;
+  output           dbrk_traceon;
+  output           dbrk_trigout;
+  input            A_ctrl_ld;
+  input            A_ctrl_st;
+  input            A_en;
+  input   [ 31: 0] A_ld_data;
+  input   [ 28: 0] A_mem_baddr;
+  input   [ 31: 0] A_st_data;
+  input            A_valid;
+  input            clk;
+  input            debugack;
+  input            reset_n;
+
+
+wire    [ 28: 0] cpu_d_address;
+wire             cpu_d_read;
+wire    [ 31: 0] cpu_d_readdata;
+wire             cpu_d_wait;
+wire             cpu_d_write;
+wire    [ 31: 0] cpu_d_writedata;
+wire             dbrk0_armed;
+wire             dbrk0_break_pulse;
+wire             dbrk0_goto0;
+wire             dbrk0_goto1;
+wire             dbrk0_traceme;
+wire             dbrk0_traceoff;
+wire             dbrk0_traceon;
+wire             dbrk0_trigout;
+wire             dbrk1_armed;
+wire             dbrk1_break_pulse;
+wire             dbrk1_goto0;
+wire             dbrk1_goto1;
+wire             dbrk1_traceme;
+wire             dbrk1_traceoff;
+wire             dbrk1_traceon;
+wire             dbrk1_trigout;
+wire             dbrk2_armed;
+wire             dbrk2_break_pulse;
+wire             dbrk2_goto0;
+wire             dbrk2_goto1;
+wire             dbrk2_traceme;
+wire             dbrk2_traceoff;
+wire             dbrk2_traceon;
+wire             dbrk2_trigout;
+wire             dbrk3_armed;
+wire             dbrk3_break_pulse;
+wire             dbrk3_goto0;
+wire             dbrk3_goto1;
+wire             dbrk3_traceme;
+wire             dbrk3_traceoff;
+wire             dbrk3_traceon;
+wire             dbrk3_trigout;
+reg              dbrk_break;
+reg              dbrk_break_pulse;
+wire    [ 31: 0] dbrk_data;
+reg              dbrk_goto0;
+reg              dbrk_goto1;
+reg              dbrk_traceme;
+reg              dbrk_traceoff;
+reg              dbrk_traceon;
+reg              dbrk_trigout;
+  assign cpu_d_address = A_mem_baddr;
+  assign cpu_d_readdata = A_ld_data;
+  assign cpu_d_read = A_ctrl_ld & A_valid;
+  assign cpu_d_writedata = A_st_data;
+  assign cpu_d_write = A_ctrl_st & A_valid;
+  assign cpu_d_wait = ~A_en;
+  assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          dbrk_break <= 0;
+      else 
+        dbrk_break <= dbrk_break   ? ~debugack   
+                : dbrk_break_pulse;
+
+    end
+
+
+  assign dbrk0_armed = 1'b0;
+  assign dbrk0_trigout = 1'b0;
+  assign dbrk0_break_pulse = 1'b0;
+  assign dbrk0_traceoff = 1'b0;
+  assign dbrk0_traceon = 1'b0;
+  assign dbrk0_traceme = 1'b0;
+  assign dbrk0_goto0 = 1'b0;
+  assign dbrk0_goto1 = 1'b0;
+  assign dbrk1_armed = 1'b0;
+  assign dbrk1_trigout = 1'b0;
+  assign dbrk1_break_pulse = 1'b0;
+  assign dbrk1_traceoff = 1'b0;
+  assign dbrk1_traceon = 1'b0;
+  assign dbrk1_traceme = 1'b0;
+  assign dbrk1_goto0 = 1'b0;
+  assign dbrk1_goto1 = 1'b0;
+  assign dbrk2_armed = 1'b0;
+  assign dbrk2_trigout = 1'b0;
+  assign dbrk2_break_pulse = 1'b0;
+  assign dbrk2_traceoff = 1'b0;
+  assign dbrk2_traceon = 1'b0;
+  assign dbrk2_traceme = 1'b0;
+  assign dbrk2_goto0 = 1'b0;
+  assign dbrk2_goto1 = 1'b0;
+  assign dbrk3_armed = 1'b0;
+  assign dbrk3_trigout = 1'b0;
+  assign dbrk3_break_pulse = 1'b0;
+  assign dbrk3_traceoff = 1'b0;
+  assign dbrk3_traceon = 1'b0;
+  assign dbrk3_traceme = 1'b0;
+  assign dbrk3_goto0 = 1'b0;
+  assign dbrk3_goto1 = 1'b0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+          dbrk_trigout <= 0;
+          dbrk_break_pulse <= 0;
+          dbrk_traceoff <= 0;
+          dbrk_traceon <= 0;
+          dbrk_traceme <= 0;
+          dbrk_goto0 <= 0;
+          dbrk_goto1 <= 0;
+        end
+      else 
+        begin
+          dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
+          dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
+          dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
+          dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
+          dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
+          dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
+          dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
+        end
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_itrace (
+                                        // inputs:
+                                         A_cmp_result,
+                                         A_en,
+                                         A_exc_active_no_break_no_crst,
+                                         A_exc_active_no_crst,
+                                         A_exc_addr,
+                                         A_op_beq,
+                                         A_op_bge,
+                                         A_op_bgeu,
+                                         A_op_blt,
+                                         A_op_bltu,
+                                         A_op_bne,
+                                         A_op_br,
+                                         A_op_bret,
+                                         A_op_call,
+                                         A_op_callr,
+                                         A_op_eret,
+                                         A_op_jmp,
+                                         A_op_jmpi,
+                                         A_op_ret,
+                                         A_pcb,
+                                         A_valid,
+                                         clk,
+                                         dbrk_traceoff,
+                                         dbrk_traceon,
+                                         debugack,
+                                         jdo,
+                                         jrst_n,
+                                         take_action_tracectrl,
+                                         xbrk_traceoff,
+                                         xbrk_traceon,
+                                         xbrk_wrap_traceoff,
+
+                                        // outputs:
+                                         itm,
+                                         trc_ctrl,
+                                         trc_on
+                                      )
+;
+
+  output  [ 35: 0] itm;
+  output  [ 15: 0] trc_ctrl;
+  output           trc_on;
+  input            A_cmp_result;
+  input            A_en;
+  input            A_exc_active_no_break_no_crst;
+  input            A_exc_active_no_crst;
+  input   [ 31: 0] A_exc_addr;
+  input            A_op_beq;
+  input            A_op_bge;
+  input            A_op_bgeu;
+  input            A_op_blt;
+  input            A_op_bltu;
+  input            A_op_bne;
+  input            A_op_br;
+  input            A_op_bret;
+  input            A_op_call;
+  input            A_op_callr;
+  input            A_op_eret;
+  input            A_op_jmp;
+  input            A_op_jmpi;
+  input            A_op_ret;
+  input   [ 28: 0] A_pcb;
+  input            A_valid;
+  input            clk;
+  input            dbrk_traceoff;
+  input            dbrk_traceon;
+  input            debugack;
+  input   [ 15: 0] jdo;
+  input            jrst_n;
+  input            take_action_tracectrl;
+  input            xbrk_traceoff;
+  input            xbrk_traceon;
+  input            xbrk_wrap_traceoff;
+
+
+wire             advanced_exc_occured;
+wire             cond_dct_taken;
+wire             curr_pid;
+wire    [  1: 0] dct_code;
+wire             dct_is_taken;
+wire    [ 31: 0] eic_addr;
+wire    [ 31: 0] exc_addr;
+wire             instr_retired;
+wire             is_cond_dct;
+wire             is_dct;
+wire             is_exception_no_break;
+wire             is_external_interrupt;
+wire             is_fast_tlb_miss_exception;
+wire             is_idct;
+wire             is_uncond_dct;
+wire    [ 35: 0] itm;
+wire             not_in_debug_mode;
+wire             record_dct_outcome_in_sync;
+wire             record_itrace;
+wire    [ 31: 0] retired_pcb;
+wire    [  1: 0] sync_code;
+wire    [  6: 0] sync_interval;
+wire    [  6: 0] sync_timer;
+wire    [  6: 0] sync_timer_next;
+wire             sync_timer_reached_zero;
+wire    [ 15: 0] trc_ctrl;
+reg     [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             trc_on;
+  assign is_cond_dct = A_op_bge  | A_op_blt | A_op_bne | A_op_bgeu | 
+    A_op_bltu | A_op_beq;
+
+  assign is_uncond_dct = A_op_br | A_op_call | A_op_jmpi;
+  assign is_dct = is_cond_dct | is_uncond_dct;
+  assign cond_dct_taken = A_cmp_result;
+  assign dct_is_taken = is_uncond_dct | (is_cond_dct & cond_dct_taken);
+  assign is_idct = A_op_jmp | A_op_callr | A_op_ret | A_op_eret | A_op_bret;
+  assign retired_pcb = A_pcb;
+  assign not_in_debug_mode = ~debugack;
+  assign instr_retired = A_valid & A_en;
+  assign advanced_exc_occured = A_exc_active_no_crst;
+  assign is_exception_no_break = A_exc_active_no_break_no_crst;
+  assign is_external_interrupt = 1'b0;
+  assign is_fast_tlb_miss_exception = 1'b0;
+  assign curr_pid = 0;
+  assign exc_addr = A_exc_addr;
+  assign eic_addr = 0;
+  assign sync_code = trc_ctrl[3 : 2];
+  assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
+  assign sync_timer_reached_zero = sync_timer == 0;
+  assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
+  assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
+  assign record_itrace = trc_on & trc_ctrl[4];
+  assign dct_code = {is_cond_dct, dct_is_taken};
+  assign itm = 36'd0;
+  assign sync_timer = 7'd1;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          trc_ctrl_reg[0] <= 1'b0;
+          trc_ctrl_reg[1] <= 1'b0;
+          trc_ctrl_reg[3 : 2] <= 2'b00;
+          trc_ctrl_reg[4] <= 1'b0;
+          trc_ctrl_reg[7 : 5] <= 3'b000;
+          trc_ctrl_reg[8] <= 0;
+          trc_ctrl_reg[9] <= 1'b0;
+          trc_ctrl_reg[10] <= 1'b0;
+        end
+      else if (take_action_tracectrl)
+        begin
+          trc_ctrl_reg[0] <= jdo[5];
+          trc_ctrl_reg[1] <= jdo[6];
+          trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
+          trc_ctrl_reg[4] <= jdo[9];
+          trc_ctrl_reg[9] <= jdo[14];
+          trc_ctrl_reg[10] <= jdo[2];
+          trc_ctrl_reg[7 : 5] <= 3'b000;
+          trc_ctrl_reg[8] <= 1'b0;
+        end
+      else if (xbrk_wrap_traceoff)
+        begin
+          trc_ctrl_reg[1] <= 0;
+          trc_ctrl_reg[0] <= 0;
+        end
+      else if (dbrk_traceoff | xbrk_traceoff)
+          trc_ctrl_reg[1] <= 0;
+      else if (trc_ctrl_reg[0] & 
+                                  (dbrk_traceon | xbrk_traceon))
+          trc_ctrl_reg[1] <= 1;
+    end
+
+
+  assign trc_ctrl = 0;
+  assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_td_mode (
+                                         // inputs:
+                                          ctrl,
+
+                                         // outputs:
+                                          td_mode
+                                       )
+;
+
+  output  [  3: 0] td_mode;
+  input   [  8: 0] ctrl;
+
+
+wire    [  2: 0] ctrl_bits_for_mux;
+reg     [  3: 0] td_mode;
+  assign ctrl_bits_for_mux = ctrl[7 : 5];
+  always @(ctrl_bits_for_mux)
+    begin
+      case (ctrl_bits_for_mux)
+      
+          3'b000: begin
+              td_mode = 4'b0000;
+          end // 3'b000 
+      
+          3'b001: begin
+              td_mode = 4'b1000;
+          end // 3'b001 
+      
+          3'b010: begin
+              td_mode = 4'b0100;
+          end // 3'b010 
+      
+          3'b011: begin
+              td_mode = 4'b1100;
+          end // 3'b011 
+      
+          3'b100: begin
+              td_mode = 4'b0010;
+          end // 3'b100 
+      
+          3'b101: begin
+              td_mode = 4'b1010;
+          end // 3'b101 
+      
+          3'b110: begin
+              td_mode = 4'b0101;
+          end // 3'b110 
+      
+          3'b111: begin
+              td_mode = 4'b1111;
+          end // 3'b111 
+      
+      endcase // ctrl_bits_for_mux
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_dtrace (
+                                        // inputs:
+                                         clk,
+                                         cpu_d_address,
+                                         cpu_d_read,
+                                         cpu_d_readdata,
+                                         cpu_d_wait,
+                                         cpu_d_write,
+                                         cpu_d_writedata,
+                                         jrst_n,
+                                         trc_ctrl,
+
+                                        // outputs:
+                                         atm,
+                                         dtm
+                                      )
+;
+
+  output  [ 35: 0] atm;
+  output  [ 35: 0] dtm;
+  input            clk;
+  input   [ 28: 0] cpu_d_address;
+  input            cpu_d_read;
+  input   [ 31: 0] cpu_d_readdata;
+  input            cpu_d_wait;
+  input            cpu_d_write;
+  input   [ 31: 0] cpu_d_writedata;
+  input            jrst_n;
+  input   [ 15: 0] trc_ctrl;
+
+
+reg     [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 31: 0] cpu_d_address_0_padded;
+wire    [ 31: 0] cpu_d_readdata_0_padded;
+wire    [ 31: 0] cpu_d_writedata_0_padded;
+reg     [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire             dummy_tie_off;
+wire             record_load_addr;
+wire             record_load_data;
+wire             record_store_addr;
+wire             record_store_data;
+wire    [  3: 0] td_mode_trc_ctrl;
+  assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
+  assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
+  assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
+  //q_sys_cpu_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
+  q_sys_cpu_cpu_nios2_oci_td_mode q_sys_cpu_cpu_nios2_oci_trc_ctrl_td_mode
+    (
+      .ctrl    (trc_ctrl[8 : 0]),
+      .td_mode (td_mode_trc_ctrl)
+    );
+
+  assign {record_load_addr, record_store_addr,
+         record_load_data, record_store_data} = td_mode_trc_ctrl;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          atm <= 0;
+          dtm <= 0;
+        end
+      else 
+        begin
+          atm <= 0;
+          dtm <= 0;
+        end
+    end
+
+
+  assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_compute_input_tm_cnt (
+                                                      // inputs:
+                                                       atm_valid,
+                                                       dtm_valid,
+                                                       itm_valid,
+
+                                                      // outputs:
+                                                       compute_input_tm_cnt
+                                                    )
+;
+
+  output  [  1: 0] compute_input_tm_cnt;
+  input            atm_valid;
+  input            dtm_valid;
+  input            itm_valid;
+
+
+reg     [  1: 0] compute_input_tm_cnt;
+wire    [  2: 0] switch_for_mux;
+  assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
+  always @(switch_for_mux)
+    begin
+      case (switch_for_mux)
+      
+          3'b000: begin
+              compute_input_tm_cnt = 0;
+          end // 3'b000 
+      
+          3'b001: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b001 
+      
+          3'b010: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b010 
+      
+          3'b011: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b011 
+      
+          3'b100: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b100 
+      
+          3'b101: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b101 
+      
+          3'b110: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b110 
+      
+          3'b111: begin
+              compute_input_tm_cnt = 3;
+          end // 3'b111 
+      
+      endcase // switch_for_mux
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_fifo_wrptr_inc (
+                                                // inputs:
+                                                 ge2_free,
+                                                 ge3_free,
+                                                 input_tm_cnt,
+
+                                                // outputs:
+                                                 fifo_wrptr_inc
+                                              )
+;
+
+  output  [  3: 0] fifo_wrptr_inc;
+  input            ge2_free;
+  input            ge3_free;
+  input   [  1: 0] input_tm_cnt;
+
+
+reg     [  3: 0] fifo_wrptr_inc;
+  always @(ge2_free or ge3_free or input_tm_cnt)
+    begin
+      if (ge3_free & (input_tm_cnt == 3))
+          fifo_wrptr_inc = 3;
+      else if (ge2_free & (input_tm_cnt >= 2))
+          fifo_wrptr_inc = 2;
+      else if (input_tm_cnt >= 1)
+          fifo_wrptr_inc = 1;
+      else 
+        fifo_wrptr_inc = 0;
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_fifo_cnt_inc (
+                                              // inputs:
+                                               empty,
+                                               ge2_free,
+                                               ge3_free,
+                                               input_tm_cnt,
+
+                                              // outputs:
+                                               fifo_cnt_inc
+                                            )
+;
+
+  output  [  4: 0] fifo_cnt_inc;
+  input            empty;
+  input            ge2_free;
+  input            ge3_free;
+  input   [  1: 0] input_tm_cnt;
+
+
+reg     [  4: 0] fifo_cnt_inc;
+  always @(empty or ge2_free or ge3_free or input_tm_cnt)
+    begin
+      if (empty)
+          fifo_cnt_inc = input_tm_cnt[1 : 0];
+      else if (ge3_free & (input_tm_cnt == 3))
+          fifo_cnt_inc = 2;
+      else if (ge2_free & (input_tm_cnt >= 2))
+          fifo_cnt_inc = 1;
+      else if (input_tm_cnt >= 1)
+          fifo_cnt_inc = 0;
+      else 
+        fifo_cnt_inc = {5{1'b1}};
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_fifo (
+                                      // inputs:
+                                       atm,
+                                       clk,
+                                       dbrk_traceme,
+                                       dbrk_traceoff,
+                                       dbrk_traceon,
+                                       dtm,
+                                       itm,
+                                       jrst_n,
+                                       reset_n,
+                                       trc_on,
+
+                                      // outputs:
+                                       tw
+                                    )
+;
+
+  output  [ 35: 0] tw;
+  input   [ 35: 0] atm;
+  input            clk;
+  input            dbrk_traceme;
+  input            dbrk_traceoff;
+  input            dbrk_traceon;
+  input   [ 35: 0] dtm;
+  input   [ 35: 0] itm;
+  input            jrst_n;
+  input            reset_n;
+  input            trc_on;
+
+
+wire             atm_valid;
+wire    [  1: 0] compute_input_tm_cnt;
+wire             dtm_valid;
+wire             empty;
+reg     [ 35: 0] fifo_0;
+wire             fifo_0_enable;
+wire    [ 35: 0] fifo_0_mux;
+reg     [ 35: 0] fifo_1;
+reg     [ 35: 0] fifo_10;
+wire             fifo_10_enable;
+wire    [ 35: 0] fifo_10_mux;
+reg     [ 35: 0] fifo_11;
+wire             fifo_11_enable;
+wire    [ 35: 0] fifo_11_mux;
+reg     [ 35: 0] fifo_12;
+wire             fifo_12_enable;
+wire    [ 35: 0] fifo_12_mux;
+reg     [ 35: 0] fifo_13;
+wire             fifo_13_enable;
+wire    [ 35: 0] fifo_13_mux;
+reg     [ 35: 0] fifo_14;
+wire             fifo_14_enable;
+wire    [ 35: 0] fifo_14_mux;
+reg     [ 35: 0] fifo_15;
+wire             fifo_15_enable;
+wire    [ 35: 0] fifo_15_mux;
+wire             fifo_1_enable;
+wire    [ 35: 0] fifo_1_mux;
+reg     [ 35: 0] fifo_2;
+wire             fifo_2_enable;
+wire    [ 35: 0] fifo_2_mux;
+reg     [ 35: 0] fifo_3;
+wire             fifo_3_enable;
+wire    [ 35: 0] fifo_3_mux;
+reg     [ 35: 0] fifo_4;
+wire             fifo_4_enable;
+wire    [ 35: 0] fifo_4_mux;
+reg     [ 35: 0] fifo_5;
+wire             fifo_5_enable;
+wire    [ 35: 0] fifo_5_mux;
+reg     [ 35: 0] fifo_6;
+wire             fifo_6_enable;
+wire    [ 35: 0] fifo_6_mux;
+reg     [ 35: 0] fifo_7;
+wire             fifo_7_enable;
+wire    [ 35: 0] fifo_7_mux;
+reg     [ 35: 0] fifo_8;
+wire             fifo_8_enable;
+wire    [ 35: 0] fifo_8_mux;
+reg     [ 35: 0] fifo_9;
+wire             fifo_9_enable;
+wire    [ 35: 0] fifo_9_mux;
+reg     [  4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [  4: 0] fifo_cnt_inc;
+wire    [ 35: 0] fifo_head;
+reg     [  3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 35: 0] fifo_read_mux;
+reg     [  3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [  3: 0] fifo_wrptr_inc;
+wire    [  3: 0] fifo_wrptr_plus1;
+wire    [  3: 0] fifo_wrptr_plus2;
+wire             ge2_free;
+wire             ge3_free;
+wire             input_ge1;
+wire             input_ge2;
+wire             input_ge3;
+wire    [  1: 0] input_tm_cnt;
+wire             itm_valid;
+reg              overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 35: 0] overflow_pending_atm;
+wire    [ 35: 0] overflow_pending_dtm;
+wire             trc_this;
+wire    [ 35: 0] tw;
+  assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
+  assign itm_valid = |itm[35 : 32];
+  assign atm_valid = |atm[35 : 32] & trc_this;
+  assign dtm_valid = |dtm[35 : 32] & trc_this;
+  assign ge2_free = ~fifo_cnt[4];
+  assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
+  assign empty = ~|fifo_cnt;
+  assign fifo_wrptr_plus1 = fifo_wrptr + 1;
+  assign fifo_wrptr_plus2 = fifo_wrptr + 2;
+  q_sys_cpu_cpu_nios2_oci_compute_input_tm_cnt the_q_sys_cpu_cpu_nios2_oci_compute_input_tm_cnt
+    (
+      .atm_valid            (atm_valid),
+      .compute_input_tm_cnt (compute_input_tm_cnt),
+      .dtm_valid            (dtm_valid),
+      .itm_valid            (itm_valid)
+    );
+
+  assign input_tm_cnt = compute_input_tm_cnt;
+  q_sys_cpu_cpu_nios2_oci_fifo_wrptr_inc the_q_sys_cpu_cpu_nios2_oci_fifo_wrptr_inc
+    (
+      .fifo_wrptr_inc (fifo_wrptr_inc),
+      .ge2_free       (ge2_free),
+      .ge3_free       (ge3_free),
+      .input_tm_cnt   (input_tm_cnt)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_fifo_cnt_inc the_q_sys_cpu_cpu_nios2_oci_fifo_cnt_inc
+    (
+      .empty        (empty),
+      .fifo_cnt_inc (fifo_cnt_inc),
+      .ge2_free     (ge2_free),
+      .ge3_free     (ge3_free),
+      .input_tm_cnt (input_tm_cnt)
+    );
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          fifo_rdptr <= 0;
+          fifo_wrptr <= 0;
+          fifo_cnt <= 0;
+          overflow_pending <= 1;
+        end
+      else 
+        begin
+          fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
+          fifo_cnt <= fifo_cnt + fifo_cnt_inc;
+          if (~empty)
+              fifo_rdptr <= fifo_rdptr + 1;
+          if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
+              overflow_pending <= 1;
+          else if (atm_valid | dtm_valid)
+              overflow_pending <= 0;
+        end
+    end
+
+
+  assign fifo_head = fifo_read_mux;
+  assign tw = itm;
+  assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_0 <= 0;
+      else if (fifo_0_enable)
+          fifo_0 <= fifo_0_mux;
+    end
+
+
+  assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_1 <= 0;
+      else if (fifo_1_enable)
+          fifo_1 <= fifo_1_mux;
+    end
+
+
+  assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_2 <= 0;
+      else if (fifo_2_enable)
+          fifo_2 <= fifo_2_mux;
+    end
+
+
+  assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_3 <= 0;
+      else if (fifo_3_enable)
+          fifo_3 <= fifo_3_mux;
+    end
+
+
+  assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_4 <= 0;
+      else if (fifo_4_enable)
+          fifo_4 <= fifo_4_mux;
+    end
+
+
+  assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_5 <= 0;
+      else if (fifo_5_enable)
+          fifo_5 <= fifo_5_mux;
+    end
+
+
+  assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_6 <= 0;
+      else if (fifo_6_enable)
+          fifo_6 <= fifo_6_mux;
+    end
+
+
+  assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_7 <= 0;
+      else if (fifo_7_enable)
+          fifo_7 <= fifo_7_mux;
+    end
+
+
+  assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_8 <= 0;
+      else if (fifo_8_enable)
+          fifo_8 <= fifo_8_mux;
+    end
+
+
+  assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_9 <= 0;
+      else if (fifo_9_enable)
+          fifo_9 <= fifo_9_mux;
+    end
+
+
+  assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_10 <= 0;
+      else if (fifo_10_enable)
+          fifo_10 <= fifo_10_mux;
+    end
+
+
+  assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_11 <= 0;
+      else if (fifo_11_enable)
+          fifo_11 <= fifo_11_mux;
+    end
+
+
+  assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_12 <= 0;
+      else if (fifo_12_enable)
+          fifo_12 <= fifo_12_mux;
+    end
+
+
+  assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_13 <= 0;
+      else if (fifo_13_enable)
+          fifo_13 <= fifo_13_mux;
+    end
+
+
+  assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_14 <= 0;
+      else if (fifo_14_enable)
+          fifo_14 <= fifo_14_mux;
+    end
+
+
+  assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_15 <= 0;
+      else if (fifo_15_enable)
+          fifo_15 <= fifo_15_mux;
+    end
+
+
+  assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign input_ge1 = |input_tm_cnt;
+  assign input_ge2 = input_tm_cnt[1];
+  assign input_ge3 = &input_tm_cnt;
+  assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
+  assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
+  assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
+    (fifo_rdptr == 4'd1)? fifo_1 :
+    (fifo_rdptr == 4'd2)? fifo_2 :
+    (fifo_rdptr == 4'd3)? fifo_3 :
+    (fifo_rdptr == 4'd4)? fifo_4 :
+    (fifo_rdptr == 4'd5)? fifo_5 :
+    (fifo_rdptr == 4'd6)? fifo_6 :
+    (fifo_rdptr == 4'd7)? fifo_7 :
+    (fifo_rdptr == 4'd8)? fifo_8 :
+    (fifo_rdptr == 4'd9)? fifo_9 :
+    (fifo_rdptr == 4'd10)? fifo_10 :
+    (fifo_rdptr == 4'd11)? fifo_11 :
+    (fifo_rdptr == 4'd12)? fifo_12 :
+    (fifo_rdptr == 4'd13)? fifo_13 :
+    (fifo_rdptr == 4'd14)? fifo_14 :
+    fifo_15;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_pib (
+                                     // outputs:
+                                      tr_data
+                                   )
+;
+
+  output  [ 35: 0] tr_data;
+
+
+wire    [ 35: 0] tr_data;
+  assign tr_data = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci_im (
+                                    // inputs:
+                                     clk,
+                                     jrst_n,
+                                     trc_ctrl,
+                                     tw,
+
+                                    // outputs:
+                                     tracemem_on,
+                                     tracemem_trcdata,
+                                     tracemem_tw,
+                                     trc_im_addr,
+                                     trc_wrap,
+                                     xbrk_wrap_traceoff
+                                  )
+;
+
+  output           tracemem_on;
+  output  [ 35: 0] tracemem_trcdata;
+  output           tracemem_tw;
+  output  [  6: 0] trc_im_addr;
+  output           trc_wrap;
+  output           xbrk_wrap_traceoff;
+  input            clk;
+  input            jrst_n;
+  input   [ 15: 0] trc_ctrl;
+  input   [ 35: 0] tw;
+
+
+wire             tracemem_on;
+wire    [ 35: 0] tracemem_trcdata;
+wire             tracemem_tw;
+reg     [  6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [ 35: 0] trc_im_data;
+wire             trc_on_chip;
+reg              trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             tw_valid;
+wire             xbrk_wrap_traceoff;
+  assign trc_im_data = tw;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          trc_im_addr <= 0;
+          trc_wrap <= 0;
+        end
+      else 
+        begin
+          trc_im_addr <= 0;
+          trc_wrap <= 0;
+        end
+    end
+
+
+  assign trc_on_chip = ~trc_ctrl[8];
+  assign tw_valid = |trc_im_data[35 : 32];
+  assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
+  assign tracemem_trcdata = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_performance_monitors 
+;
+
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_avalon_reg (
+                                        // inputs:
+                                         address,
+                                         clk,
+                                         debugaccess,
+                                         monitor_error,
+                                         monitor_go,
+                                         monitor_ready,
+                                         reset_n,
+                                         write,
+                                         writedata,
+
+                                        // outputs:
+                                         oci_ienable,
+                                         oci_reg_readdata,
+                                         oci_single_step_mode,
+                                         ocireg_ers,
+                                         ocireg_mrs,
+                                         take_action_ocireg
+                                      )
+;
+
+  output  [ 31: 0] oci_ienable;
+  output  [ 31: 0] oci_reg_readdata;
+  output           oci_single_step_mode;
+  output           ocireg_ers;
+  output           ocireg_mrs;
+  output           take_action_ocireg;
+  input   [  8: 0] address;
+  input            clk;
+  input            debugaccess;
+  input            monitor_error;
+  input            monitor_go;
+  input            monitor_ready;
+  input            reset_n;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+reg     [ 31: 0] oci_ienable;
+wire             oci_reg_00_addressed;
+wire             oci_reg_01_addressed;
+wire    [ 31: 0] oci_reg_readdata;
+reg              oci_single_step_mode;
+wire             ocireg_ers;
+wire             ocireg_mrs;
+wire             ocireg_sstep;
+wire             take_action_oci_intr_mask_reg;
+wire             take_action_ocireg;
+wire             write_strobe;
+  assign oci_reg_00_addressed = address == 9'h100;
+  assign oci_reg_01_addressed = address == 9'h101;
+  assign write_strobe = write & debugaccess;
+  assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
+  assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
+  assign ocireg_ers = writedata[1];
+  assign ocireg_mrs = writedata[0];
+  assign ocireg_sstep = writedata[3];
+  assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
+    monitor_ready, monitor_error} : 
+    oci_reg_01_addressed ?  oci_ienable :   
+    32'b0;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          oci_single_step_mode <= 1'b0;
+      else if (take_action_ocireg)
+          oci_single_step_mode <= ocireg_sstep;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          oci_ienable <= 32'b00000000000000000000000000111101;
+      else if (take_action_oci_intr_mask_reg)
+          oci_ienable <= writedata | ~(32'b00000000000000000000000000111101);
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_ociram_sp_ram_module (
+                                            // inputs:
+                                             address,
+                                             byteenable,
+                                             clock,
+                                             data,
+                                             reset_req,
+                                             wren,
+
+                                            // outputs:
+                                             q
+                                          )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input   [  7: 0] address;
+  input   [  3: 0] byteenable;
+  input            clock;
+  input   [ 31: 0] data;
+  input            reset_req;
+  input            wren;
+
+
+wire             clocken;
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign clocken = ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clock),
+      .clocken0 (clocken),
+      .data_a (data),
+      .q_a (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 256,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 8;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_ocimem (
+                                    // inputs:
+                                     address,
+                                     byteenable,
+                                     clk,
+                                     debugaccess,
+                                     jdo,
+                                     jrst_n,
+                                     read,
+                                     reset_req,
+                                     take_action_ocimem_a,
+                                     take_action_ocimem_b,
+                                     take_no_action_ocimem_a,
+                                     write,
+                                     writedata,
+
+                                    // outputs:
+                                     MonDReg,
+                                     ociram_readdata,
+                                     waitrequest
+                                  )
+;
+
+  output  [ 31: 0] MonDReg;
+  output  [ 31: 0] ociram_readdata;
+  output           waitrequest;
+  input   [  8: 0] address;
+  input   [  3: 0] byteenable;
+  input            clk;
+  input            debugaccess;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            read;
+  input            reset_req;
+  input            take_action_ocimem_a;
+  input            take_action_ocimem_b;
+  input            take_no_action_ocimem_a;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+reg     [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [  8: 0] MonARegAddrInc;
+wire             MonARegAddrIncAccessingRAM;
+reg     [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             avalon_ram_wr;
+wire    [ 31: 0] cfgrom_readdata;
+reg              jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [  7: 0] ociram_addr;
+wire    [  3: 0] ociram_byteenable;
+wire    [ 31: 0] ociram_readdata;
+wire             ociram_reset_req;
+wire    [ 31: 0] ociram_wr_data;
+wire             ociram_wr_en;
+reg              waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          jtag_rd <= 1'b0;
+          jtag_rd_d1 <= 1'b0;
+          jtag_ram_wr <= 1'b0;
+          jtag_ram_rd <= 1'b0;
+          jtag_ram_rd_d1 <= 1'b0;
+          jtag_ram_access <= 1'b0;
+          MonAReg <= 0;
+          MonDReg <= 0;
+          waitrequest <= 1'b1;
+          avalon_ociram_readdata_ready <= 1'b0;
+        end
+      else 
+        begin
+          if (take_no_action_ocimem_a)
+            begin
+              MonAReg[10 : 2] <= MonARegAddrInc;
+              jtag_rd <= 1'b1;
+              jtag_ram_rd <= MonARegAddrIncAccessingRAM;
+              jtag_ram_access <= MonARegAddrIncAccessingRAM;
+            end
+          else if (take_action_ocimem_a)
+            begin
+              MonAReg[10 : 2] <= { jdo[17],
+                            jdo[33 : 26] };
+
+              jtag_rd <= 1'b1;
+              jtag_ram_rd <= ~jdo[17];
+              jtag_ram_access <= ~jdo[17];
+            end
+          else if (take_action_ocimem_b)
+            begin
+              MonAReg[10 : 2] <= MonARegAddrInc;
+              MonDReg <= jdo[34 : 3];
+              jtag_ram_wr <= MonARegAddrIncAccessingRAM;
+              jtag_ram_access <= MonARegAddrIncAccessingRAM;
+            end
+          else 
+            begin
+              jtag_rd <= 0;
+              jtag_ram_wr <= 0;
+              jtag_ram_rd <= 0;
+              jtag_ram_access <= 0;
+              if (jtag_rd_d1)
+                  MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
+            end
+          jtag_rd_d1 <= jtag_rd;
+          jtag_ram_rd_d1 <= jtag_ram_rd;
+          if (~waitrequest)
+            begin
+              waitrequest <= 1'b1;
+              avalon_ociram_readdata_ready <= 1'b0;
+            end
+          else if (write)
+              waitrequest <= ~address[8] & jtag_ram_access;
+          else if (read)
+            begin
+              avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
+              waitrequest <= ~avalon_ociram_readdata_ready;
+            end
+          else 
+            begin
+              waitrequest <= 1'b1;
+              avalon_ociram_readdata_ready <= 1'b0;
+            end
+        end
+    end
+
+
+  assign MonARegAddrInc = MonAReg[10 : 2]+1;
+  assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
+  assign avalon_ram_wr = write & ~address[8] & debugaccess;
+  assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
+  assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
+  assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
+  assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
+  assign ociram_reset_req = reset_req & ~jtag_ram_access;
+//q_sys_cpu_cpu_ociram_sp_ram, which is an nios_sp_ram
+q_sys_cpu_cpu_ociram_sp_ram_module q_sys_cpu_cpu_ociram_sp_ram
+  (
+    .address    (ociram_addr),
+    .byteenable (ociram_byteenable),
+    .clock      (clk),
+    .data       (ociram_wr_data),
+    .q          (ociram_readdata),
+    .reset_req  (ociram_reset_req),
+    .wren       (ociram_wr_en)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_ociram_sp_ram.lpm_file = "q_sys_cpu_cpu_ociram_default_contents.dat";
+`else
+defparam q_sys_cpu_cpu_ociram_sp_ram.lpm_file = "q_sys_cpu_cpu_ociram_default_contents.hex";
+`endif
+//synthesis translate_on
+  assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h08000120 :
+    (MonAReg[4 : 2] == 3'd1)? 32'h02001d1d :
+    (MonAReg[4 : 2] == 3'd2)? 32'h00440000 :
+    (MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
+    (MonAReg[4 : 2] == 3'd4)? 32'h20000b0b :
+    (MonAReg[4 : 2] == 3'd5)? 32'h14000000 :
+    (MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
+    32'h00000000;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_nios2_oci (
+                                 // inputs:
+                                  A_cmp_result,
+                                  A_ctrl_ld,
+                                  A_ctrl_st,
+                                  A_en,
+                                  A_exc_active_no_break_no_crst,
+                                  A_exc_active_no_crst,
+                                  A_exc_addr,
+                                  A_ld_data,
+                                  A_mem_baddr,
+                                  A_op_beq,
+                                  A_op_bge,
+                                  A_op_bgeu,
+                                  A_op_blt,
+                                  A_op_bltu,
+                                  A_op_bne,
+                                  A_op_br,
+                                  A_op_bret,
+                                  A_op_call,
+                                  A_op_callr,
+                                  A_op_eret,
+                                  A_op_jmp,
+                                  A_op_jmpi,
+                                  A_op_ret,
+                                  A_pcb,
+                                  A_st_data,
+                                  A_valid,
+                                  D_en,
+                                  E_en,
+                                  E_valid,
+                                  F_pc,
+                                  M_en,
+                                  address_nxt,
+                                  byteenable_nxt,
+                                  clk,
+                                  debugaccess_nxt,
+                                  hbreak_enabled,
+                                  read_nxt,
+                                  reset,
+                                  reset_n,
+                                  reset_req,
+                                  write_nxt,
+                                  writedata_nxt,
+
+                                 // outputs:
+                                  E_oci_sync_hbreak_req,
+                                  debug_mem_slave_debugaccess_to_roms,
+                                  oci_async_hbreak_req,
+                                  oci_ienable,
+                                  oci_single_step_mode,
+                                  readdata,
+                                  resetrequest,
+                                  waitrequest
+                               )
+;
+
+  output           E_oci_sync_hbreak_req;
+  output           debug_mem_slave_debugaccess_to_roms;
+  output           oci_async_hbreak_req;
+  output  [ 31: 0] oci_ienable;
+  output           oci_single_step_mode;
+  output  [ 31: 0] readdata;
+  output           resetrequest;
+  output           waitrequest;
+  input            A_cmp_result;
+  input            A_ctrl_ld;
+  input            A_ctrl_st;
+  input            A_en;
+  input            A_exc_active_no_break_no_crst;
+  input            A_exc_active_no_crst;
+  input   [ 31: 0] A_exc_addr;
+  input   [ 31: 0] A_ld_data;
+  input   [ 28: 0] A_mem_baddr;
+  input            A_op_beq;
+  input            A_op_bge;
+  input            A_op_bgeu;
+  input            A_op_blt;
+  input            A_op_bltu;
+  input            A_op_bne;
+  input            A_op_br;
+  input            A_op_bret;
+  input            A_op_call;
+  input            A_op_callr;
+  input            A_op_eret;
+  input            A_op_jmp;
+  input            A_op_jmpi;
+  input            A_op_ret;
+  input   [ 28: 0] A_pcb;
+  input   [ 31: 0] A_st_data;
+  input            A_valid;
+  input            D_en;
+  input            E_en;
+  input            E_valid;
+  input   [ 26: 0] F_pc;
+  input            M_en;
+  input   [  8: 0] address_nxt;
+  input   [  3: 0] byteenable_nxt;
+  input            clk;
+  input            debugaccess_nxt;
+  input            hbreak_enabled;
+  input            read_nxt;
+  input            reset;
+  input            reset_n;
+  input            reset_req;
+  input            write_nxt;
+  input   [ 31: 0] writedata_nxt;
+
+
+wire             E_oci_sync_hbreak_req;
+wire    [ 31: 0] MonDReg;
+reg     [  8: 0] address;
+wire    [ 35: 0] atm;
+wire    [ 31: 0] break_readreg;
+reg     [  3: 0] byteenable;
+wire    [ 28: 0] cpu_d_address;
+wire             cpu_d_read;
+wire    [ 31: 0] cpu_d_readdata;
+wire             cpu_d_wait;
+wire             cpu_d_write;
+wire    [ 31: 0] cpu_d_writedata;
+wire             dbrk_break;
+wire             dbrk_goto0;
+wire             dbrk_goto1;
+wire             dbrk_hit0_latch;
+wire             dbrk_hit1_latch;
+wire             dbrk_hit2_latch;
+wire             dbrk_hit3_latch;
+wire             dbrk_traceme;
+wire             dbrk_traceoff;
+wire             dbrk_traceon;
+wire             dbrk_trigout;
+wire             debug_mem_slave_debugaccess_to_roms;
+reg              debugaccess;
+wire             debugack;
+wire             debugreq;
+wire    [ 35: 0] dtm;
+wire             dummy_sink;
+wire    [ 35: 0] itm;
+wire    [ 37: 0] jdo;
+wire             jrst_n;
+wire             monitor_error;
+wire             monitor_go;
+wire             monitor_ready;
+wire             oci_async_hbreak_req;
+wire    [ 31: 0] oci_ienable;
+wire    [ 31: 0] oci_reg_readdata;
+wire             oci_single_step_mode;
+wire    [ 31: 0] ociram_readdata;
+wire             ocireg_ers;
+wire             ocireg_mrs;
+reg              read;
+reg     [ 31: 0] readdata;
+wire             resetlatch;
+wire             resetrequest;
+wire             st_ready_test_idle;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_ocireg;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire    [ 35: 0] tr_data;
+wire             tracemem_on;
+wire    [ 35: 0] tracemem_trcdata;
+wire             tracemem_tw;
+wire    [ 15: 0] trc_ctrl;
+wire    [  6: 0] trc_im_addr;
+wire             trc_on;
+wire             trc_wrap;
+wire             trigbrktype;
+wire             trigger_state_0;
+wire             trigger_state_1;
+wire             trigout;
+wire    [ 35: 0] tw;
+wire             waitrequest;
+reg              write;
+reg     [ 31: 0] writedata;
+wire    [ 28: 0] xbrk0;
+wire    [ 28: 0] xbrk1;
+wire             xbrk_break;
+wire    [  7: 0] xbrk_ctrl0;
+wire    [  7: 0] xbrk_ctrl1;
+wire    [  7: 0] xbrk_ctrl2;
+wire    [  7: 0] xbrk_ctrl3;
+wire             xbrk_goto0;
+wire             xbrk_goto1;
+wire             xbrk_traceoff;
+wire             xbrk_traceon;
+wire             xbrk_trigout;
+wire             xbrk_wrap_traceoff;
+  q_sys_cpu_cpu_nios2_oci_debug the_q_sys_cpu_cpu_nios2_oci_debug
+    (
+      .E_oci_sync_hbreak_req (E_oci_sync_hbreak_req),
+      .clk                   (clk),
+      .dbrk_break            (dbrk_break),
+      .debugack              (debugack),
+      .debugreq              (debugreq),
+      .hbreak_enabled        (hbreak_enabled),
+      .jdo                   (jdo),
+      .jrst_n                (jrst_n),
+      .monitor_error         (monitor_error),
+      .monitor_go            (monitor_go),
+      .monitor_ready         (monitor_ready),
+      .oci_async_hbreak_req  (oci_async_hbreak_req),
+      .ocireg_ers            (ocireg_ers),
+      .ocireg_mrs            (ocireg_mrs),
+      .reset                 (reset),
+      .resetlatch            (resetlatch),
+      .resetrequest          (resetrequest),
+      .st_ready_test_idle    (st_ready_test_idle),
+      .take_action_ocimem_a  (take_action_ocimem_a),
+      .take_action_ocireg    (take_action_ocireg),
+      .xbrk_break            (xbrk_break)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_break the_q_sys_cpu_cpu_nios2_oci_break
+    (
+      .break_readreg          (break_readreg),
+      .clk                    (clk),
+      .dbrk_break             (dbrk_break),
+      .dbrk_goto0             (dbrk_goto0),
+      .dbrk_goto1             (dbrk_goto1),
+      .dbrk_hit0_latch        (dbrk_hit0_latch),
+      .dbrk_hit1_latch        (dbrk_hit1_latch),
+      .dbrk_hit2_latch        (dbrk_hit2_latch),
+      .dbrk_hit3_latch        (dbrk_hit3_latch),
+      .jdo                    (jdo),
+      .jrst_n                 (jrst_n),
+      .take_action_break_a    (take_action_break_a),
+      .take_action_break_b    (take_action_break_b),
+      .take_action_break_c    (take_action_break_c),
+      .take_no_action_break_a (take_no_action_break_a),
+      .take_no_action_break_b (take_no_action_break_b),
+      .take_no_action_break_c (take_no_action_break_c),
+      .trigbrktype            (trigbrktype),
+      .trigger_state_0        (trigger_state_0),
+      .trigger_state_1        (trigger_state_1),
+      .xbrk0                  (xbrk0),
+      .xbrk1                  (xbrk1),
+      .xbrk_ctrl0             (xbrk_ctrl0),
+      .xbrk_ctrl1             (xbrk_ctrl1),
+      .xbrk_ctrl2             (xbrk_ctrl2),
+      .xbrk_ctrl3             (xbrk_ctrl3),
+      .xbrk_goto0             (xbrk_goto0),
+      .xbrk_goto1             (xbrk_goto1)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_xbrk the_q_sys_cpu_cpu_nios2_oci_xbrk
+    (
+      .D_en            (D_en),
+      .E_en            (E_en),
+      .E_valid         (E_valid),
+      .F_pc            (F_pc),
+      .M_en            (M_en),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .trigger_state_0 (trigger_state_0),
+      .trigger_state_1 (trigger_state_1),
+      .xbrk0           (xbrk0),
+      .xbrk1           (xbrk1),
+      .xbrk_break      (xbrk_break),
+      .xbrk_ctrl0      (xbrk_ctrl0),
+      .xbrk_ctrl1      (xbrk_ctrl1),
+      .xbrk_ctrl2      (xbrk_ctrl2),
+      .xbrk_ctrl3      (xbrk_ctrl3),
+      .xbrk_goto0      (xbrk_goto0),
+      .xbrk_goto1      (xbrk_goto1),
+      .xbrk_traceoff   (xbrk_traceoff),
+      .xbrk_traceon    (xbrk_traceon),
+      .xbrk_trigout    (xbrk_trigout)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_dbrk the_q_sys_cpu_cpu_nios2_oci_dbrk
+    (
+      .A_ctrl_ld       (A_ctrl_ld),
+      .A_ctrl_st       (A_ctrl_st),
+      .A_en            (A_en),
+      .A_ld_data       (A_ld_data),
+      .A_mem_baddr     (A_mem_baddr),
+      .A_st_data       (A_st_data),
+      .A_valid         (A_valid),
+      .clk             (clk),
+      .cpu_d_address   (cpu_d_address),
+      .cpu_d_read      (cpu_d_read),
+      .cpu_d_readdata  (cpu_d_readdata),
+      .cpu_d_wait      (cpu_d_wait),
+      .cpu_d_write     (cpu_d_write),
+      .cpu_d_writedata (cpu_d_writedata),
+      .dbrk_break      (dbrk_break),
+      .dbrk_goto0      (dbrk_goto0),
+      .dbrk_goto1      (dbrk_goto1),
+      .dbrk_traceme    (dbrk_traceme),
+      .dbrk_traceoff   (dbrk_traceoff),
+      .dbrk_traceon    (dbrk_traceon),
+      .dbrk_trigout    (dbrk_trigout),
+      .debugack        (debugack),
+      .reset_n         (reset_n)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_itrace the_q_sys_cpu_cpu_nios2_oci_itrace
+    (
+      .A_cmp_result                  (A_cmp_result),
+      .A_en                          (A_en),
+      .A_exc_active_no_break_no_crst (A_exc_active_no_break_no_crst),
+      .A_exc_active_no_crst          (A_exc_active_no_crst),
+      .A_exc_addr                    (A_exc_addr),
+      .A_op_beq                      (A_op_beq),
+      .A_op_bge                      (A_op_bge),
+      .A_op_bgeu                     (A_op_bgeu),
+      .A_op_blt                      (A_op_blt),
+      .A_op_bltu                     (A_op_bltu),
+      .A_op_bne                      (A_op_bne),
+      .A_op_br                       (A_op_br),
+      .A_op_bret                     (A_op_bret),
+      .A_op_call                     (A_op_call),
+      .A_op_callr                    (A_op_callr),
+      .A_op_eret                     (A_op_eret),
+      .A_op_jmp                      (A_op_jmp),
+      .A_op_jmpi                     (A_op_jmpi),
+      .A_op_ret                      (A_op_ret),
+      .A_pcb                         (A_pcb),
+      .A_valid                       (A_valid),
+      .clk                           (clk),
+      .dbrk_traceoff                 (dbrk_traceoff),
+      .dbrk_traceon                  (dbrk_traceon),
+      .debugack                      (debugack),
+      .itm                           (itm),
+      .jdo                           (jdo),
+      .jrst_n                        (jrst_n),
+      .take_action_tracectrl         (take_action_tracectrl),
+      .trc_ctrl                      (trc_ctrl),
+      .trc_on                        (trc_on),
+      .xbrk_traceoff                 (xbrk_traceoff),
+      .xbrk_traceon                  (xbrk_traceon),
+      .xbrk_wrap_traceoff            (xbrk_wrap_traceoff)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_dtrace the_q_sys_cpu_cpu_nios2_oci_dtrace
+    (
+      .atm             (atm),
+      .clk             (clk),
+      .cpu_d_address   (cpu_d_address),
+      .cpu_d_read      (cpu_d_read),
+      .cpu_d_readdata  (cpu_d_readdata),
+      .cpu_d_wait      (cpu_d_wait),
+      .cpu_d_write     (cpu_d_write),
+      .cpu_d_writedata (cpu_d_writedata),
+      .dtm             (dtm),
+      .jrst_n          (jrst_n),
+      .trc_ctrl        (trc_ctrl)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_fifo the_q_sys_cpu_cpu_nios2_oci_fifo
+    (
+      .atm           (atm),
+      .clk           (clk),
+      .dbrk_traceme  (dbrk_traceme),
+      .dbrk_traceoff (dbrk_traceoff),
+      .dbrk_traceon  (dbrk_traceon),
+      .dtm           (dtm),
+      .itm           (itm),
+      .jrst_n        (jrst_n),
+      .reset_n       (reset_n),
+      .trc_on        (trc_on),
+      .tw            (tw)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_pib the_q_sys_cpu_cpu_nios2_oci_pib
+    (
+      .tr_data (tr_data)
+    );
+
+  q_sys_cpu_cpu_nios2_oci_im the_q_sys_cpu_cpu_nios2_oci_im
+    (
+      .clk                (clk),
+      .jrst_n             (jrst_n),
+      .tracemem_on        (tracemem_on),
+      .tracemem_trcdata   (tracemem_trcdata),
+      .tracemem_tw        (tracemem_tw),
+      .trc_ctrl           (trc_ctrl),
+      .trc_im_addr        (trc_im_addr),
+      .trc_wrap           (trc_wrap),
+      .tw                 (tw),
+      .xbrk_wrap_traceoff (xbrk_wrap_traceoff)
+    );
+
+  q_sys_cpu_cpu_nios2_avalon_reg the_q_sys_cpu_cpu_nios2_avalon_reg
+    (
+      .address              (address),
+      .clk                  (clk),
+      .debugaccess          (debugaccess),
+      .monitor_error        (monitor_error),
+      .monitor_go           (monitor_go),
+      .monitor_ready        (monitor_ready),
+      .oci_ienable          (oci_ienable),
+      .oci_reg_readdata     (oci_reg_readdata),
+      .oci_single_step_mode (oci_single_step_mode),
+      .ocireg_ers           (ocireg_ers),
+      .ocireg_mrs           (ocireg_mrs),
+      .reset_n              (reset_n),
+      .take_action_ocireg   (take_action_ocireg),
+      .write                (write),
+      .writedata            (writedata)
+    );
+
+  q_sys_cpu_cpu_nios2_ocimem the_q_sys_cpu_cpu_nios2_ocimem
+    (
+      .MonDReg                 (MonDReg),
+      .address                 (address),
+      .byteenable              (byteenable),
+      .clk                     (clk),
+      .debugaccess             (debugaccess),
+      .jdo                     (jdo),
+      .jrst_n                  (jrst_n),
+      .ociram_readdata         (ociram_readdata),
+      .read                    (read),
+      .reset_req               (reset_req),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .waitrequest             (waitrequest),
+      .write                   (write),
+      .writedata               (writedata)
+    );
+
+  assign trigout = dbrk_trigout | xbrk_trigout;
+  assign debug_mem_slave_debugaccess_to_roms = debugack;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          address <= 0;
+      else 
+        address <= address_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          byteenable <= 0;
+      else 
+        byteenable <= byteenable_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          writedata <= 0;
+      else 
+        writedata <= writedata_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          debugaccess <= 0;
+      else 
+        debugaccess <= debugaccess_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          read <= 0;
+      else 
+        read <= read ? waitrequest : read_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          write <= 0;
+      else 
+        write <= write ? waitrequest : write_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          readdata <= 0;
+      else 
+        readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
+    end
+
+
+  q_sys_cpu_cpu_debug_slave_wrapper the_q_sys_cpu_cpu_debug_slave_wrapper
+    (
+      .MonDReg                 (MonDReg),
+      .break_readreg           (break_readreg),
+      .clk                     (clk),
+      .dbrk_hit0_latch         (dbrk_hit0_latch),
+      .dbrk_hit1_latch         (dbrk_hit1_latch),
+      .dbrk_hit2_latch         (dbrk_hit2_latch),
+      .dbrk_hit3_latch         (dbrk_hit3_latch),
+      .debugack                (debugack),
+      .jdo                     (jdo),
+      .jrst_n                  (jrst_n),
+      .monitor_error           (monitor_error),
+      .monitor_ready           (monitor_ready),
+      .reset_n                 (reset_n),
+      .resetlatch              (resetlatch),
+      .st_ready_test_idle      (st_ready_test_idle),
+      .take_action_break_a     (take_action_break_a),
+      .take_action_break_b     (take_action_break_b),
+      .take_action_break_c     (take_action_break_c),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_action_tracectrl   (take_action_tracectrl),
+      .take_no_action_break_a  (take_no_action_break_a),
+      .take_no_action_break_b  (take_no_action_break_b),
+      .take_no_action_break_c  (take_no_action_break_c),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .tracemem_on             (tracemem_on),
+      .tracemem_trcdata        (tracemem_trcdata),
+      .tracemem_tw             (tracemem_tw),
+      .trc_im_addr             (trc_im_addr),
+      .trc_on                  (trc_on),
+      .trc_wrap                (trc_wrap),
+      .trigbrktype             (trigbrktype),
+      .trigger_state_1         (trigger_state_1)
+    );
+
+  //dummy sink, which is an e_mux
+  assign dummy_sink = tr_data |
+    trigout |
+    debugack;
+
+  assign debugreq = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu (
+                       // inputs:
+                        clk,
+                        d_readdata,
+                        d_readdatavalid,
+                        d_waitrequest,
+                        debug_mem_slave_address,
+                        debug_mem_slave_byteenable,
+                        debug_mem_slave_debugaccess,
+                        debug_mem_slave_read,
+                        debug_mem_slave_write,
+                        debug_mem_slave_writedata,
+                        i_readdata,
+                        i_readdatavalid,
+                        i_waitrequest,
+                        irq,
+                        reset_n,
+                        reset_req,
+
+                       // outputs:
+                        d_address,
+                        d_byteenable,
+                        d_read,
+                        d_write,
+                        d_writedata,
+                        debug_mem_slave_debugaccess_to_roms,
+                        debug_mem_slave_readdata,
+                        debug_mem_slave_waitrequest,
+                        debug_reset_request,
+                        dummy_ci_port,
+                        i_address,
+                        i_read
+                     )
+;
+
+  output  [ 28: 0] d_address;
+  output  [  3: 0] d_byteenable;
+  output           d_read;
+  output           d_write;
+  output  [ 31: 0] d_writedata;
+  output           debug_mem_slave_debugaccess_to_roms;
+  output  [ 31: 0] debug_mem_slave_readdata;
+  output           debug_mem_slave_waitrequest;
+  output           debug_reset_request;
+  output           dummy_ci_port;
+  output  [ 28: 0] i_address;
+  output           i_read;
+  input            clk;
+  input   [ 31: 0] d_readdata;
+  input            d_readdatavalid;
+  input            d_waitrequest;
+  input   [  8: 0] debug_mem_slave_address;
+  input   [  3: 0] debug_mem_slave_byteenable;
+  input            debug_mem_slave_debugaccess;
+  input            debug_mem_slave_read;
+  input            debug_mem_slave_write;
+  input   [ 31: 0] debug_mem_slave_writedata;
+  input   [ 31: 0] i_readdata;
+  input            i_readdatavalid;
+  input            i_waitrequest;
+  input   [ 31: 0] irq;
+  input            reset_n;
+  input            reset_req;
+
+
+reg     [ 28: 0] A_br_jmp_target_pcb;
+wire    [ 28: 0] A_br_jmp_target_pcb_nxt;
+reg     [ 28: 0] A_br_taken_baddr;
+wire             A_cancel;
+reg              A_cmp_result;
+reg              A_ctrl_a_not_src;
+wire             A_ctrl_a_not_src_nxt;
+reg              A_ctrl_alu_force_and;
+wire             A_ctrl_alu_force_and_nxt;
+reg              A_ctrl_alu_force_xor;
+wire             A_ctrl_alu_force_xor_nxt;
+reg              A_ctrl_alu_signed_comparison;
+wire             A_ctrl_alu_signed_comparison_nxt;
+reg              A_ctrl_alu_subtract;
+wire             A_ctrl_alu_subtract_nxt;
+reg              A_ctrl_b_is_dst;
+wire             A_ctrl_b_is_dst_nxt;
+reg              A_ctrl_b_not_src;
+wire             A_ctrl_b_not_src_nxt;
+reg              A_ctrl_bmx;
+wire             A_ctrl_bmx_nxt;
+reg              A_ctrl_br;
+reg              A_ctrl_br_always_pred_taken;
+wire             A_ctrl_br_always_pred_taken_nxt;
+reg              A_ctrl_br_cond;
+wire             A_ctrl_br_cond_nxt;
+wire             A_ctrl_br_nxt;
+reg              A_ctrl_br_uncond;
+wire             A_ctrl_br_uncond_nxt;
+reg              A_ctrl_break;
+wire             A_ctrl_break_nxt;
+reg              A_ctrl_cmp;
+wire             A_ctrl_cmp_nxt;
+reg              A_ctrl_crst;
+wire             A_ctrl_crst_nxt;
+reg              A_ctrl_custom_combo;
+wire             A_ctrl_custom_combo_nxt;
+reg              A_ctrl_custom_multi;
+wire             A_ctrl_custom_multi_nxt;
+reg              A_ctrl_dc_addr_inv;
+wire             A_ctrl_dc_addr_inv_nxt;
+reg              A_ctrl_dc_addr_nowb_inv;
+wire             A_ctrl_dc_addr_nowb_inv_nxt;
+reg              A_ctrl_dc_addr_wb_inv;
+wire             A_ctrl_dc_addr_wb_inv_nxt;
+reg              A_ctrl_dc_index_inv;
+wire             A_ctrl_dc_index_inv_nxt;
+reg              A_ctrl_dc_index_nowb_inv;
+wire             A_ctrl_dc_index_nowb_inv_nxt;
+reg              A_ctrl_dc_index_wb_inv;
+wire             A_ctrl_dc_index_wb_inv_nxt;
+reg              A_ctrl_dc_nowb_inv;
+wire             A_ctrl_dc_nowb_inv_nxt;
+reg              A_ctrl_dcache_management;
+wire             A_ctrl_dcache_management_nxt;
+reg              A_ctrl_exception;
+wire             A_ctrl_exception_nxt;
+reg              A_ctrl_flush_pipe_always;
+wire             A_ctrl_flush_pipe_always_nxt;
+reg              A_ctrl_hi_imm16;
+wire             A_ctrl_hi_imm16_nxt;
+reg              A_ctrl_ignore_dst;
+wire             A_ctrl_ignore_dst_nxt;
+reg              A_ctrl_illegal;
+wire             A_ctrl_illegal_nxt;
+reg              A_ctrl_implicit_dst_eretaddr;
+wire             A_ctrl_implicit_dst_eretaddr_nxt;
+reg              A_ctrl_implicit_dst_retaddr;
+wire             A_ctrl_implicit_dst_retaddr_nxt;
+reg              A_ctrl_intr_inst;
+wire             A_ctrl_intr_inst_nxt;
+reg              A_ctrl_invalidate_i;
+wire             A_ctrl_invalidate_i_nxt;
+reg              A_ctrl_jmp_direct;
+wire             A_ctrl_jmp_direct_nxt;
+reg              A_ctrl_jmp_indirect;
+wire             A_ctrl_jmp_indirect_nxt;
+reg              A_ctrl_late_result;
+wire             A_ctrl_late_result_nxt;
+reg              A_ctrl_ld;
+reg              A_ctrl_ld16;
+wire             A_ctrl_ld16_nxt;
+reg              A_ctrl_ld32;
+wire             A_ctrl_ld32_nxt;
+reg              A_ctrl_ld8;
+reg              A_ctrl_ld8_ld16;
+wire             A_ctrl_ld8_ld16_nxt;
+wire             A_ctrl_ld8_nxt;
+reg              A_ctrl_ld_bypass;
+wire             A_ctrl_ld_bypass_nxt;
+reg              A_ctrl_ld_cache;
+wire             A_ctrl_ld_cache_nxt;
+reg              A_ctrl_ld_dcache_management;
+wire             A_ctrl_ld_dcache_management_nxt;
+reg              A_ctrl_ld_ex;
+wire             A_ctrl_ld_ex_nxt;
+reg              A_ctrl_ld_io;
+wire             A_ctrl_ld_io_nxt;
+reg              A_ctrl_ld_non_bypass;
+wire             A_ctrl_ld_non_bypass_nxt;
+reg              A_ctrl_ld_non_io;
+wire             A_ctrl_ld_non_io_nxt;
+wire             A_ctrl_ld_nxt;
+reg              A_ctrl_ld_signed;
+wire             A_ctrl_ld_signed_nxt;
+reg              A_ctrl_ld_st;
+reg              A_ctrl_ld_st_bypass;
+wire             A_ctrl_ld_st_bypass_nxt;
+reg              A_ctrl_ld_st_bypass_or_dcache_management;
+wire             A_ctrl_ld_st_bypass_or_dcache_management_nxt;
+reg              A_ctrl_ld_st_cache;
+wire             A_ctrl_ld_st_cache_nxt;
+reg              A_ctrl_ld_st_ex;
+wire             A_ctrl_ld_st_ex_nxt;
+reg              A_ctrl_ld_st_io;
+wire             A_ctrl_ld_st_io_nxt;
+reg              A_ctrl_ld_st_non_bypass;
+wire             A_ctrl_ld_st_non_bypass_nxt;
+reg              A_ctrl_ld_st_non_io;
+wire             A_ctrl_ld_st_non_io_nxt;
+wire             A_ctrl_ld_st_nxt;
+reg              A_ctrl_ld_stnon32_cache;
+wire             A_ctrl_ld_stnon32_cache_nxt;
+reg              A_ctrl_logic;
+wire             A_ctrl_logic_nxt;
+reg              A_ctrl_mem;
+reg              A_ctrl_mem16;
+wire             A_ctrl_mem16_nxt;
+reg              A_ctrl_mem32;
+wire             A_ctrl_mem32_nxt;
+reg              A_ctrl_mem8;
+wire             A_ctrl_mem8_nxt;
+reg              A_ctrl_mem_data_access;
+wire             A_ctrl_mem_data_access_nxt;
+reg              A_ctrl_mem_dc_data_rd;
+wire             A_ctrl_mem_dc_data_rd_nxt;
+reg              A_ctrl_mem_dc_tag_rd;
+wire             A_ctrl_mem_dc_tag_rd_nxt;
+wire             A_ctrl_mem_nxt;
+reg              A_ctrl_mul_lsw;
+wire             A_ctrl_mul_lsw_nxt;
+reg              A_ctrl_rd_ctl_reg;
+wire             A_ctrl_rd_ctl_reg_nxt;
+reg              A_ctrl_retaddr;
+wire             A_ctrl_retaddr_nxt;
+reg              A_ctrl_rot;
+wire             A_ctrl_rot_nxt;
+reg              A_ctrl_set_src2_rem_imm;
+wire             A_ctrl_set_src2_rem_imm_nxt;
+reg              A_ctrl_shift_right_arith;
+wire             A_ctrl_shift_right_arith_nxt;
+reg              A_ctrl_shift_rot;
+reg              A_ctrl_shift_rot_left;
+wire             A_ctrl_shift_rot_left_nxt;
+wire             A_ctrl_shift_rot_nxt;
+reg              A_ctrl_shift_rot_right;
+wire             A_ctrl_shift_rot_right_nxt;
+reg              A_ctrl_signed_imm12;
+wire             A_ctrl_signed_imm12_nxt;
+reg              A_ctrl_src2_choose_imm;
+wire             A_ctrl_src2_choose_imm_nxt;
+reg              A_ctrl_src_imm5_shift_rot;
+wire             A_ctrl_src_imm5_shift_rot_nxt;
+reg              A_ctrl_st;
+reg              A_ctrl_st16;
+wire             A_ctrl_st16_nxt;
+reg              A_ctrl_st8;
+wire             A_ctrl_st8_nxt;
+reg              A_ctrl_st_bypass;
+wire             A_ctrl_st_bypass_nxt;
+reg              A_ctrl_st_cache;
+wire             A_ctrl_st_cache_nxt;
+reg              A_ctrl_st_ex;
+wire             A_ctrl_st_ex_nxt;
+reg              A_ctrl_st_io;
+wire             A_ctrl_st_io_nxt;
+reg              A_ctrl_st_non32;
+wire             A_ctrl_st_non32_nxt;
+reg              A_ctrl_st_non_bypass;
+wire             A_ctrl_st_non_bypass_nxt;
+reg              A_ctrl_st_non_io;
+wire             A_ctrl_st_non_io_nxt;
+wire             A_ctrl_st_nxt;
+reg              A_ctrl_stnon32_cache;
+wire             A_ctrl_stnon32_cache_nxt;
+reg              A_ctrl_supervisor_only;
+wire             A_ctrl_supervisor_only_nxt;
+reg              A_ctrl_trap_inst;
+wire             A_ctrl_trap_inst_nxt;
+reg              A_ctrl_uncond_cti_non_br;
+wire             A_ctrl_uncond_cti_non_br_nxt;
+reg              A_ctrl_unimp_nop;
+wire             A_ctrl_unimp_nop_nxt;
+reg              A_ctrl_unimp_trap;
+wire             A_ctrl_unimp_trap_nxt;
+reg              A_ctrl_unsigned_lo_imm16;
+wire             A_ctrl_unsigned_lo_imm16_nxt;
+reg              A_ctrl_wrctl_inst;
+wire             A_ctrl_wrctl_inst_nxt;
+wire    [ 15: 0] A_data_ram_ld16_data;
+wire             A_data_ram_ld_align_fill_bit;
+reg              A_data_ram_ld_align_sign_bit;
+wire    [  7: 0] A_data_ram_ld_byte0_data;
+wire    [  7: 0] A_data_ram_ld_byte1_data;
+wire    [  7: 0] A_data_ram_ld_byte2_data;
+wire    [  7: 0] A_data_ram_ld_byte3_data;
+reg     [ 17: 0] A_dc_actual_tag;
+wire             A_dc_data_dcache_management_wr_en;
+wire             A_dc_data_st_wr_en;
+wire             A_dc_dc_addr_wb_inv_done_nxt;
+wire             A_dc_dc_addr_wb_inv_want_xfer;
+reg              A_dc_dcache_management_done;
+wire             A_dc_dcache_management_done_nxt;
+wire    [ 17: 0] A_dc_desired_tag;
+reg              A_dc_dirty;
+reg              A_dc_fill_active;
+wire             A_dc_fill_active_nxt;
+wire             A_dc_fill_done;
+reg     [  2: 0] A_dc_fill_dp_offset;
+wire             A_dc_fill_dp_offset_en;
+wire    [  2: 0] A_dc_fill_dp_offset_nxt;
+reg              A_dc_fill_has_started;
+wire             A_dc_fill_has_started_nxt;
+wire             A_dc_fill_miss_offset_is_next;
+reg              A_dc_fill_need_extra_stall;
+wire             A_dc_fill_need_extra_stall_nxt;
+wire    [ 31: 0] A_dc_fill_st_data_merged;
+wire             A_dc_fill_starting;
+reg              A_dc_fill_starting_d1;
+wire             A_dc_fill_want_dmaster;
+wire             A_dc_fill_want_xfer;
+wire    [ 31: 0] A_dc_fill_wr_data;
+reg              A_dc_hit;
+wire             A_dc_index_wb_inv_done_nxt;
+wire             A_dc_index_wb_inv_want_xfer;
+reg     [  3: 0] A_dc_rd_addr_cnt;
+wire    [  3: 0] A_dc_rd_addr_cnt_nxt;
+reg     [  3: 0] A_dc_rd_data_cnt;
+wire    [  3: 0] A_dc_rd_data_cnt_nxt;
+wire             A_dc_rd_last_driven;
+wire             A_dc_rd_last_transfer;
+reg              A_dc_rd_last_transfer_d1;
+reg     [ 31: 0] A_dc_st_data;
+wire             A_dc_tag_dcache_management_wr_en;
+wire             A_dc_tag_st_wr_en;
+wire             A_dc_valid_st_cache_hit;
+reg              A_dc_want_fill;
+wire             A_dc_want_xfer;
+reg              A_dc_wb_active;
+wire             A_dc_wb_active_nxt;
+reg     [  5: 0] A_dc_wb_line;
+reg     [  2: 0] A_dc_wb_rd_addr_offset;
+wire    [  2: 0] A_dc_wb_rd_addr_offset_nxt;
+reg              A_dc_wb_rd_addr_starting;
+wire    [ 31: 0] A_dc_wb_rd_data;
+reg              A_dc_wb_rd_data_first;
+wire             A_dc_wb_rd_data_first_nxt;
+reg              A_dc_wb_rd_data_starting;
+wire             A_dc_wb_rd_en;
+reg     [ 17: 0] A_dc_wb_tag;
+wire             A_dc_wb_update_av_writedata;
+reg              A_dc_wb_wr_active;
+wire             A_dc_wb_wr_active_nxt;
+wire             A_dc_wb_wr_starting;
+wire             A_dc_wb_wr_want_dmaster;
+reg     [  3: 0] A_dc_wr_data_cnt;
+wire    [  3: 0] A_dc_wr_data_cnt_nxt;
+wire             A_dc_wr_last_driven;
+wire             A_dc_wr_last_transfer;
+reg              A_dc_xfer_rd_addr_active;
+wire             A_dc_xfer_rd_addr_active_nxt;
+reg              A_dc_xfer_rd_addr_done;
+wire             A_dc_xfer_rd_addr_done_nxt;
+reg              A_dc_xfer_rd_addr_has_started;
+wire             A_dc_xfer_rd_addr_has_started_nxt;
+reg     [  2: 0] A_dc_xfer_rd_addr_offset;
+wire    [  2: 0] A_dc_xfer_rd_addr_offset_nxt;
+wire             A_dc_xfer_rd_addr_starting;
+reg              A_dc_xfer_rd_data_active;
+reg              A_dc_xfer_rd_data_starting;
+reg              A_dc_xfer_wr_active;
+reg     [ 31: 0] A_dc_xfer_wr_data;
+wire    [ 31: 0] A_dc_xfer_wr_data_nxt;
+reg     [  2: 0] A_dc_xfer_wr_offset;
+wire    [  2: 0] A_dc_xfer_wr_offset_nxt;
+wire             A_dc_xfer_wr_offset_starting;
+reg              A_dc_xfer_wr_starting;
+wire    [  4: 0] A_dst_regnum;
+reg     [  4: 0] A_dst_regnum_from_M;
+wire             A_dtcm_ld;
+wire             A_dtcm_st;
+wire             A_en;
+reg              A_en_d1;
+wire             A_eret_src;
+wire             A_exc_active_no_break;
+wire             A_exc_active_no_break_no_crst;
+wire             A_exc_active_no_crst;
+wire    [ 31: 0] A_exc_addr;
+reg              A_exc_allowed;
+reg              A_exc_any;
+wire             A_exc_any_active;
+reg              A_exc_break;
+wire             A_exc_break_active;
+reg              A_exc_break_inst_pri15;
+wire             A_exc_break_inst_pri15_nxt;
+reg              A_exc_crst;
+wire             A_exc_crst_active;
+reg              A_exc_ext_intr;
+wire             A_exc_ext_intr_active;
+reg              A_exc_hbreak_pri1;
+wire             A_exc_hbreak_pri1_nxt;
+wire    [ 28: 0] A_exc_highest_pri_baddr;
+wire    [  4: 0] A_exc_highest_pri_cause_code;
+wire    [ 31: 0] A_exc_highest_pri_exc_id;
+reg              A_exc_illegal_inst_pri15;
+wire             A_exc_illegal_inst_pri15_nxt;
+wire             A_exc_inst_fetch;
+reg              A_exc_norm_intr_pri5;
+wire             A_exc_norm_intr_pri5_nxt;
+wire             A_exc_record_baddr;
+wire             A_exc_shadow;
+wire             A_exc_shadow_active;
+reg              A_exc_trap_inst_pri15;
+wire             A_exc_trap_inst_pri15_nxt;
+reg              A_exc_unimp_inst_pri15;
+wire             A_exc_unimp_inst_pri15_nxt;
+wire             A_exc_wr_ea_ba;
+wire             A_exc_wr_sstatus;
+wire    [ 31: 0] A_fwd_reg_data;
+wire    [ 55: 0] A_inst;
+reg     [ 31: 0] A_inst_result;
+wire    [ 31: 0] A_inst_result_aligned;
+wire             A_is_opx_inst;
+reg     [ 31: 0] A_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire    [  4: 0] A_iw_a;
+wire    [  4: 0] A_iw_b;
+wire    [  4: 0] A_iw_c;
+wire    [  4: 0] A_iw_control_regnum;
+reg              A_iw_corrupt;
+wire    [  7: 0] A_iw_custom_n;
+wire             A_iw_custom_readra;
+wire             A_iw_custom_readrb;
+wire             A_iw_custom_writerc;
+wire    [ 15: 0] A_iw_imm16;
+wire    [ 25: 0] A_iw_imm26;
+wire    [  4: 0] A_iw_imm5;
+wire    [  1: 0] A_iw_memsz;
+wire    [  5: 0] A_iw_op;
+wire    [  5: 0] A_iw_opx;
+reg              A_ld_align_byte1_fill;
+reg              A_ld_align_byte2_byte3_fill;
+reg              A_ld_align_sh16;
+reg              A_ld_align_sh8;
+reg              A_ld_bypass_delayed;
+reg              A_ld_bypass_delayed_started;
+wire             A_ld_bypass_done;
+wire    [ 31: 0] A_ld_data;
+wire             A_mem16;
+wire             A_mem32;
+wire             A_mem8;
+reg     [ 28: 0] A_mem_baddr;
+wire    [  1: 0] A_mem_baddr_byte_field;
+wire    [  5: 0] A_mem_baddr_line_field;
+wire    [  8: 0] A_mem_baddr_line_offset_field;
+wire    [  2: 0] A_mem_baddr_offset_field;
+wire    [ 17: 0] A_mem_baddr_tag_field;
+wire             A_mem_bypass_pending;
+reg     [  3: 0] A_mem_byte_en;
+reg              A_mem_stall;
+wire             A_mem_stall_nxt;
+wire             A_mem_stall_start_nxt;
+wire             A_mem_stall_stop_nxt;
+wire    [ 26: 0] A_mem_waddr;
+wire    [ 26: 0] A_mem_waddr_phy;
+reg     [ 15: 0] A_mul_cell_p1;
+reg     [ 31: 0] A_mul_cell_p3;
+wire    [ 31: 0] A_mul_result;
+reg     [ 16: 0] A_mul_s1;
+wire    [ 17: 0] A_mul_s2;
+wire             A_one_post_bret_inst_n;
+wire             A_op_add;
+wire             A_op_addi;
+wire             A_op_and;
+wire             A_op_andhi;
+wire             A_op_andi;
+wire             A_op_beq;
+wire             A_op_bge;
+wire             A_op_bgeu;
+wire             A_op_blt;
+wire             A_op_bltu;
+wire             A_op_bne;
+wire             A_op_br;
+wire             A_op_break;
+wire             A_op_bret;
+wire             A_op_call;
+wire             A_op_callr;
+wire             A_op_cmpeq;
+wire             A_op_cmpeqi;
+wire             A_op_cmpge;
+wire             A_op_cmpgei;
+wire             A_op_cmpgeu;
+wire             A_op_cmpgeui;
+wire             A_op_cmplt;
+wire             A_op_cmplti;
+wire             A_op_cmpltu;
+wire             A_op_cmpltui;
+wire             A_op_cmpne;
+wire             A_op_cmpnei;
+wire             A_op_crst;
+wire             A_op_custom;
+wire             A_op_div;
+wire             A_op_divu;
+wire             A_op_eret;
+wire             A_op_flushd;
+wire             A_op_flushda;
+wire             A_op_flushi;
+wire             A_op_flushp;
+wire             A_op_hbreak;
+wire             A_op_initd;
+wire             A_op_initda;
+wire             A_op_initi;
+wire             A_op_intr;
+wire             A_op_jmp;
+wire             A_op_jmpi;
+wire             A_op_ldb;
+wire             A_op_ldbio;
+wire             A_op_ldbu;
+wire             A_op_ldbuio;
+wire             A_op_ldh;
+wire             A_op_ldhio;
+wire             A_op_ldhu;
+wire             A_op_ldhuio;
+wire             A_op_ldl;
+wire             A_op_ldw;
+wire             A_op_ldwio;
+wire             A_op_mul;
+wire             A_op_muli;
+wire             A_op_mulxss;
+wire             A_op_mulxsu;
+wire             A_op_mulxuu;
+wire             A_op_nextpc;
+wire             A_op_nor;
+wire             A_op_op_rsv02;
+wire             A_op_op_rsv09;
+wire             A_op_op_rsv10;
+wire             A_op_op_rsv17;
+wire             A_op_op_rsv18;
+wire             A_op_op_rsv25;
+wire             A_op_op_rsv26;
+wire             A_op_op_rsv33;
+wire             A_op_op_rsv34;
+wire             A_op_op_rsv41;
+wire             A_op_op_rsv42;
+wire             A_op_op_rsv49;
+wire             A_op_op_rsv57;
+wire             A_op_op_rsv61;
+wire             A_op_op_rsv62;
+wire             A_op_op_rsv63;
+wire             A_op_opx_rsv00;
+wire             A_op_opx_rsv10;
+wire             A_op_opx_rsv15;
+wire             A_op_opx_rsv17;
+wire             A_op_opx_rsv21;
+wire             A_op_opx_rsv25;
+wire             A_op_opx_rsv33;
+wire             A_op_opx_rsv34;
+wire             A_op_opx_rsv35;
+wire             A_op_opx_rsv42;
+wire             A_op_opx_rsv43;
+wire             A_op_opx_rsv44;
+wire             A_op_opx_rsv47;
+wire             A_op_opx_rsv50;
+wire             A_op_opx_rsv51;
+wire             A_op_opx_rsv55;
+wire             A_op_opx_rsv56;
+wire             A_op_opx_rsv60;
+wire             A_op_opx_rsv63;
+wire             A_op_or;
+wire             A_op_orhi;
+wire             A_op_ori;
+wire             A_op_rdctl;
+wire             A_op_rdprs;
+wire             A_op_ret;
+wire             A_op_rol;
+wire             A_op_roli;
+wire             A_op_ror;
+wire             A_op_sll;
+wire             A_op_slli;
+wire             A_op_sra;
+wire             A_op_srai;
+wire             A_op_srl;
+wire             A_op_srli;
+wire             A_op_stb;
+wire             A_op_stbio;
+wire             A_op_stc;
+wire             A_op_sth;
+wire             A_op_sthio;
+wire             A_op_stw;
+wire             A_op_stwio;
+wire             A_op_sub;
+wire             A_op_sync;
+wire             A_op_trap;
+wire             A_op_wrctl;
+wire             A_op_wrprs;
+wire             A_op_xor;
+wire             A_op_xorhi;
+wire             A_op_xori;
+reg     [ 26: 0] A_pc;
+reg     [ 28: 0] A_pcb /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+reg              A_pipe_flush;
+wire    [ 28: 0] A_pipe_flush_baddr;
+wire    [ 28: 0] A_pipe_flush_baddr_nxt;
+wire             A_pipe_flush_nxt;
+reg     [ 26: 0] A_pipe_flush_waddr;
+wire    [ 26: 0] A_pipe_flush_waddr_nxt;
+wire             A_refetch_required;
+reg              A_sel_data_master;
+wire             A_sel_dtcm;
+wire    [ 31: 0] A_shift_rot_bmx_result;
+reg     [ 31: 0] A_shift_rot_result;
+reg     [ 31: 0] A_slow_inst_result;
+wire             A_slow_inst_result_en;
+wire    [ 31: 0] A_slow_inst_result_nxt;
+reg              A_slow_inst_sel;
+wire             A_slow_inst_sel_nxt;
+wire    [ 31: 0] A_slow_ld_data_aligned_nxt;
+reg     [ 31: 0] A_src2;
+reg              A_st_bypass_delayed;
+reg              A_st_bypass_delayed_started;
+wire             A_st_bypass_done;
+reg     [ 31: 0] A_st_data;
+wire             A_st_writes_mem;
+wire             A_stall;
+wire             A_up_ex_mon_state_latest;
+wire             A_valid;
+reg              A_valid_from_M /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire             A_valid_st_writes_mem;
+wire    [ 71: 0] A_vinst;
+wire    [ 31: 0] A_wr_data_filtered;
+wire    [ 31: 0] A_wr_data_unfiltered;
+wire             A_wr_dst_reg;
+reg              A_wr_dst_reg_from_M;
+wire             A_wrctl_bstatus;
+wire             A_wrctl_cdsr;
+wire             A_wrctl_data_bstatus_reg_pie;
+wire    [ 31: 0] A_wrctl_data_cdsr_reg_status;
+wire             A_wrctl_data_estatus_reg_pie;
+wire             A_wrctl_data_ienable_reg_irq0;
+wire             A_wrctl_data_ienable_reg_irq2;
+wire             A_wrctl_data_ienable_reg_irq3;
+wire             A_wrctl_data_ienable_reg_irq4;
+wire             A_wrctl_data_ienable_reg_irq5;
+wire             A_wrctl_data_status_reg_pie;
+wire             A_wrctl_estatus;
+wire             A_wrctl_ienable;
+wire             A_wrctl_status;
+reg     [  1: 0] D_bht_data;
+reg     [  7: 0] D_bht_ptr;
+wire             D_br_cond_pred_taken;
+wire    [ 16: 0] D_br_offset_remaining;
+wire    [ 19: 0] D_br_offset_sex;
+wire             D_br_pred_not_taken;
+wire             D_br_pred_taken;
+wire    [ 28: 0] D_br_taken_baddr;
+wire    [ 26: 0] D_br_taken_waddr;
+reg     [ 10: 0] D_br_taken_waddr_partial;
+wire    [  1: 0] D_compare_op;
+wire    [ 31: 0] D_control_reg_rddata_muxed;
+reg              D_ctrl_a_not_src;
+wire             D_ctrl_a_not_src_nxt;
+wire             D_ctrl_alu_force_and;
+wire             D_ctrl_alu_force_xor;
+wire             D_ctrl_alu_signed_comparison;
+wire             D_ctrl_alu_subtract;
+reg              D_ctrl_b_is_dst;
+wire             D_ctrl_b_is_dst_nxt;
+reg              D_ctrl_b_not_src;
+wire             D_ctrl_b_not_src_nxt;
+wire             D_ctrl_bmx;
+reg              D_ctrl_br;
+wire             D_ctrl_br_always_pred_taken;
+wire             D_ctrl_br_cond;
+wire             D_ctrl_br_nxt;
+reg              D_ctrl_br_uncond;
+wire             D_ctrl_br_uncond_nxt;
+wire             D_ctrl_break;
+wire             D_ctrl_cmp;
+wire             D_ctrl_crst;
+wire             D_ctrl_custom_combo;
+wire             D_ctrl_custom_multi;
+wire             D_ctrl_exception;
+wire             D_ctrl_flush_pipe_always;
+reg              D_ctrl_hi_imm16;
+wire             D_ctrl_hi_imm16_nxt;
+reg              D_ctrl_ignore_dst;
+wire             D_ctrl_ignore_dst_nxt;
+wire             D_ctrl_illegal;
+reg              D_ctrl_implicit_dst_eretaddr;
+wire             D_ctrl_implicit_dst_eretaddr_nxt;
+reg              D_ctrl_implicit_dst_retaddr;
+wire             D_ctrl_implicit_dst_retaddr_nxt;
+wire             D_ctrl_intr_inst;
+reg              D_ctrl_jmp_direct;
+wire             D_ctrl_jmp_direct_nxt;
+wire             D_ctrl_jmp_indirect;
+wire             D_ctrl_late_result;
+wire             D_ctrl_ld;
+wire             D_ctrl_ld_ex;
+wire             D_ctrl_ld_st_ex;
+wire             D_ctrl_logic;
+wire             D_ctrl_mem16;
+wire             D_ctrl_mem32;
+wire             D_ctrl_mem8;
+wire             D_ctrl_mul_lsw;
+wire             D_ctrl_rdprs;
+wire             D_ctrl_retaddr;
+wire             D_ctrl_rot;
+wire             D_ctrl_set_src2_rem_imm;
+wire             D_ctrl_shift_right_arith;
+wire             D_ctrl_shift_rot;
+wire             D_ctrl_shift_rot_left;
+wire             D_ctrl_shift_rot_right;
+wire             D_ctrl_signed_imm12;
+reg              D_ctrl_src2_choose_imm;
+wire             D_ctrl_src2_choose_imm_nxt;
+wire             D_ctrl_src_imm5_shift_rot;
+wire             D_ctrl_st_ex;
+wire             D_ctrl_supervisor_only;
+wire             D_ctrl_trap_inst;
+wire             D_ctrl_uncond_cti_non_br;
+wire             D_ctrl_unimp_nop;
+wire             D_ctrl_unimp_trap;
+reg              D_ctrl_unsigned_lo_imm16;
+wire             D_ctrl_unsigned_lo_imm16_nxt;
+wire             D_data_depend;
+wire             D_dep_stall;
+wire    [  4: 0] D_dst_regnum;
+wire             D_en;
+wire             D_exc_inst_fetch;
+wire             D_exc_invalidates_inst_value;
+wire    [ 26: 0] D_extra_pc;
+wire    [ 28: 0] D_extra_pcb;
+wire             D_ic_fill_ignore;
+reg              D_ic_fill_same_tag_line;
+wire             D_ic_fill_starting;
+reg              D_ic_fill_starting_d1;
+wire             D_ic_want_fill;
+wire             D_ic_want_fill_unfiltered;
+wire             D_ic_want_fill_unfiltered_is_x;
+wire    [ 55: 0] D_inst;
+wire             D_is_opx_inst;
+reg              D_issue;
+wire             D_issue_rdprs;
+reg     [ 31: 0] D_iw;
+wire    [  4: 0] D_iw_a;
+wire    [  4: 0] D_iw_b;
+wire    [  4: 0] D_iw_c;
+wire    [  4: 0] D_iw_control_regnum;
+wire             D_iw_corrupt;
+wire    [  7: 0] D_iw_custom_n;
+wire             D_iw_custom_readra;
+wire             D_iw_custom_readrb;
+wire             D_iw_custom_writerc;
+wire    [ 15: 0] D_iw_imm16;
+wire    [ 25: 0] D_iw_imm26;
+wire    [  4: 0] D_iw_imm5;
+wire    [  1: 0] D_iw_memsz;
+wire    [  5: 0] D_iw_op;
+wire    [  5: 0] D_iw_opx;
+reg              D_iw_valid;
+wire    [ 28: 0] D_jmp_direct_target_baddr;
+wire    [ 26: 0] D_jmp_direct_target_waddr;
+reg              D_kill;
+wire    [  1: 0] D_logic_op;
+wire    [  1: 0] D_logic_op_raw;
+wire             D_mem16;
+wire             D_mem32;
+wire             D_mem8;
+wire             D_op_add;
+wire             D_op_addi;
+wire             D_op_and;
+wire             D_op_andhi;
+wire             D_op_andi;
+wire             D_op_beq;
+wire             D_op_bge;
+wire             D_op_bgeu;
+wire             D_op_blt;
+wire             D_op_bltu;
+wire             D_op_bne;
+wire             D_op_br;
+wire             D_op_break;
+wire             D_op_bret;
+wire             D_op_call;
+wire             D_op_callr;
+wire             D_op_cmpeq;
+wire             D_op_cmpeqi;
+wire             D_op_cmpge;
+wire             D_op_cmpgei;
+wire             D_op_cmpgeu;
+wire             D_op_cmpgeui;
+wire             D_op_cmplt;
+wire             D_op_cmplti;
+wire             D_op_cmpltu;
+wire             D_op_cmpltui;
+wire             D_op_cmpne;
+wire             D_op_cmpnei;
+wire             D_op_crst;
+wire             D_op_custom;
+wire             D_op_div;
+wire             D_op_divu;
+wire             D_op_eret;
+wire             D_op_flushd;
+wire             D_op_flushda;
+wire             D_op_flushi;
+wire             D_op_flushp;
+wire             D_op_hbreak;
+wire             D_op_initd;
+wire             D_op_initda;
+wire             D_op_initi;
+wire             D_op_intr;
+wire             D_op_jmp;
+wire             D_op_jmpi;
+wire             D_op_ldb;
+wire             D_op_ldbio;
+wire             D_op_ldbu;
+wire             D_op_ldbuio;
+wire             D_op_ldh;
+wire             D_op_ldhio;
+wire             D_op_ldhu;
+wire             D_op_ldhuio;
+wire             D_op_ldl;
+wire             D_op_ldw;
+wire             D_op_ldwio;
+wire             D_op_mul;
+wire             D_op_muli;
+wire             D_op_mulxss;
+wire             D_op_mulxsu;
+wire             D_op_mulxuu;
+wire             D_op_nextpc;
+wire             D_op_nor;
+wire             D_op_op_rsv02;
+wire             D_op_op_rsv09;
+wire             D_op_op_rsv10;
+wire             D_op_op_rsv17;
+wire             D_op_op_rsv18;
+wire             D_op_op_rsv25;
+wire             D_op_op_rsv26;
+wire             D_op_op_rsv33;
+wire             D_op_op_rsv34;
+wire             D_op_op_rsv41;
+wire             D_op_op_rsv42;
+wire             D_op_op_rsv49;
+wire             D_op_op_rsv57;
+wire             D_op_op_rsv61;
+wire             D_op_op_rsv62;
+wire             D_op_op_rsv63;
+wire             D_op_opx_rsv00;
+wire             D_op_opx_rsv10;
+wire             D_op_opx_rsv15;
+wire             D_op_opx_rsv17;
+wire             D_op_opx_rsv21;
+wire             D_op_opx_rsv25;
+wire             D_op_opx_rsv33;
+wire             D_op_opx_rsv34;
+wire             D_op_opx_rsv35;
+wire             D_op_opx_rsv42;
+wire             D_op_opx_rsv43;
+wire             D_op_opx_rsv44;
+wire             D_op_opx_rsv47;
+wire             D_op_opx_rsv50;
+wire             D_op_opx_rsv51;
+wire             D_op_opx_rsv55;
+wire             D_op_opx_rsv56;
+wire             D_op_opx_rsv60;
+wire             D_op_opx_rsv63;
+wire             D_op_or;
+wire             D_op_orhi;
+wire             D_op_ori;
+wire             D_op_rdctl;
+wire             D_op_rdprs;
+wire             D_op_ret;
+wire             D_op_rol;
+wire             D_op_roli;
+wire             D_op_ror;
+wire             D_op_sll;
+wire             D_op_slli;
+wire             D_op_sra;
+wire             D_op_srai;
+wire             D_op_srl;
+wire             D_op_srli;
+wire             D_op_stb;
+wire             D_op_stbio;
+wire             D_op_stc;
+wire             D_op_sth;
+wire             D_op_sthio;
+wire             D_op_stw;
+wire             D_op_stwio;
+wire             D_op_sub;
+wire             D_op_sync;
+wire             D_op_trap;
+wire             D_op_wrctl;
+wire             D_op_wrprs;
+wire             D_op_xor;
+wire             D_op_xorhi;
+wire             D_op_xori;
+reg     [ 26: 0] D_pc;
+wire    [  5: 0] D_pc_line_field;
+wire    [  2: 0] D_pc_offset_field;
+reg     [ 26: 0] D_pc_plus_one;
+wire    [ 17: 0] D_pc_tag_field;
+wire    [ 28: 0] D_pcb;
+wire             D_raw_refetch;
+wire             D_rdprs_stall;
+reg              D_rdprs_stall_done;
+wire             D_rdprs_stall_done_nxt;
+wire             D_rdprs_stall_unfiltered;
+wire             D_rdprs_stall_unfiltered_is_x;
+wire             D_refetch;
+wire    [ 31: 0] D_rf_a;
+wire    [ 31: 0] D_rf_b;
+wire    [ 31: 0] D_src1;
+wire             D_src1_choose_A;
+wire             D_src1_choose_E;
+wire             D_src1_choose_M;
+wire             D_src1_choose_W;
+wire    [ 31: 0] D_src1_reg;
+wire    [ 31: 0] D_src2;
+wire             D_src2_choose_A;
+wire             D_src2_choose_E;
+wire             D_src2_choose_M;
+wire             D_src2_choose_W;
+wire    [ 31: 0] D_src2_imm;
+wire    [ 31: 0] D_src2_imm16;
+wire    [  1: 0] D_src2_imm16_sel;
+wire             D_src2_imm5_sel;
+wire    [ 31: 0] D_src2_reg;
+wire             D_stall;
+wire             D_valid;
+wire    [ 71: 0] D_vinst;
+wire             D_wr_dst_reg;
+wire             E_add_br_to_taken_history_filtered;
+wire             E_add_br_to_taken_history_unfiltered;
+wire    [ 31: 0] E_alu_result;
+wire    [ 32: 0] E_arith_result;
+wire    [ 31: 0] E_arith_src1;
+wire    [ 31: 0] E_arith_src2;
+reg     [  1: 0] E_bht_data;
+reg     [  7: 0] E_bht_ptr;
+wire             E_br_actually_taken;
+wire             E_br_cond_pred_taken;
+wire    [  7: 0] E_br_cond_taken_history;
+wire             E_br_mispredict;
+wire             E_br_result;
+reg     [ 28: 0] E_br_taken_baddr;
+wire             E_cancel;
+wire             E_cmp_result;
+reg     [  1: 0] E_compare_op;
+reg     [ 31: 0] E_control_reg_rddata;
+wire    [ 31: 0] E_control_reg_rddata_muxed;
+wire             E_ctrl_a_is_src;
+reg              E_ctrl_a_not_src;
+wire             E_ctrl_a_not_src_nxt;
+reg              E_ctrl_alu_force_and;
+wire             E_ctrl_alu_force_and_nxt;
+reg              E_ctrl_alu_force_xor;
+wire             E_ctrl_alu_force_xor_nxt;
+reg              E_ctrl_alu_signed_comparison;
+wire             E_ctrl_alu_signed_comparison_nxt;
+reg              E_ctrl_alu_subtract;
+wire             E_ctrl_alu_subtract_nxt;
+reg              E_ctrl_b_is_dst;
+wire             E_ctrl_b_is_dst_nxt;
+wire             E_ctrl_b_is_src;
+reg              E_ctrl_b_not_src;
+wire             E_ctrl_b_not_src_nxt;
+reg              E_ctrl_bmx;
+wire             E_ctrl_bmx_nxt;
+reg              E_ctrl_br;
+reg              E_ctrl_br_always_pred_taken;
+wire             E_ctrl_br_always_pred_taken_nxt;
+reg              E_ctrl_br_cond;
+wire             E_ctrl_br_cond_nxt;
+wire             E_ctrl_br_nxt;
+reg              E_ctrl_br_uncond;
+wire             E_ctrl_br_uncond_nxt;
+reg              E_ctrl_break;
+wire             E_ctrl_break_nxt;
+reg              E_ctrl_cmp;
+wire             E_ctrl_cmp_nxt;
+reg              E_ctrl_crst;
+wire             E_ctrl_crst_nxt;
+reg              E_ctrl_custom_combo;
+wire             E_ctrl_custom_combo_nxt;
+reg              E_ctrl_custom_multi;
+wire             E_ctrl_custom_multi_nxt;
+wire             E_ctrl_dc_addr_inv;
+wire             E_ctrl_dc_addr_nowb_inv;
+wire             E_ctrl_dc_addr_wb_inv;
+wire             E_ctrl_dc_index_inv;
+wire             E_ctrl_dc_index_nowb_inv;
+wire             E_ctrl_dc_index_wb_inv;
+wire             E_ctrl_dc_nowb_inv;
+wire             E_ctrl_dcache_management;
+reg              E_ctrl_exception;
+wire             E_ctrl_exception_nxt;
+reg              E_ctrl_flush_pipe_always;
+wire             E_ctrl_flush_pipe_always_nxt;
+reg              E_ctrl_hi_imm16;
+wire             E_ctrl_hi_imm16_nxt;
+reg              E_ctrl_ignore_dst;
+wire             E_ctrl_ignore_dst_nxt;
+reg              E_ctrl_illegal;
+wire             E_ctrl_illegal_nxt;
+reg              E_ctrl_implicit_dst_eretaddr;
+wire             E_ctrl_implicit_dst_eretaddr_nxt;
+reg              E_ctrl_implicit_dst_retaddr;
+wire             E_ctrl_implicit_dst_retaddr_nxt;
+reg              E_ctrl_intr_inst;
+wire             E_ctrl_intr_inst_nxt;
+wire             E_ctrl_invalidate_i;
+reg              E_ctrl_jmp_direct;
+wire             E_ctrl_jmp_direct_nxt;
+reg              E_ctrl_jmp_indirect;
+wire             E_ctrl_jmp_indirect_nxt;
+reg              E_ctrl_late_result;
+wire             E_ctrl_late_result_nxt;
+reg              E_ctrl_ld;
+wire             E_ctrl_ld16;
+wire             E_ctrl_ld32;
+wire             E_ctrl_ld8;
+wire             E_ctrl_ld8_ld16;
+wire             E_ctrl_ld_bypass;
+wire             E_ctrl_ld_cache;
+wire             E_ctrl_ld_dcache_management;
+reg              E_ctrl_ld_ex;
+wire             E_ctrl_ld_ex_nxt;
+wire             E_ctrl_ld_io;
+wire             E_ctrl_ld_non_bypass;
+wire             E_ctrl_ld_non_io;
+wire             E_ctrl_ld_nxt;
+wire             E_ctrl_ld_signed;
+wire             E_ctrl_ld_st;
+wire             E_ctrl_ld_st_bypass;
+wire             E_ctrl_ld_st_bypass_or_dcache_management;
+wire             E_ctrl_ld_st_cache;
+reg              E_ctrl_ld_st_ex;
+wire             E_ctrl_ld_st_ex_nxt;
+wire             E_ctrl_ld_st_io;
+wire             E_ctrl_ld_st_non_bypass;
+wire             E_ctrl_ld_st_non_io;
+wire             E_ctrl_ld_stnon32_cache;
+reg              E_ctrl_logic;
+wire             E_ctrl_logic_nxt;
+wire             E_ctrl_mem;
+reg              E_ctrl_mem16;
+wire             E_ctrl_mem16_nxt;
+reg              E_ctrl_mem32;
+wire             E_ctrl_mem32_nxt;
+reg              E_ctrl_mem8;
+wire             E_ctrl_mem8_nxt;
+wire             E_ctrl_mem_data_access;
+wire             E_ctrl_mem_dc_data_rd;
+wire             E_ctrl_mem_dc_tag_rd;
+reg              E_ctrl_mul_lsw;
+wire             E_ctrl_mul_lsw_nxt;
+wire             E_ctrl_rd_ctl_reg;
+reg              E_ctrl_retaddr;
+wire             E_ctrl_retaddr_nxt;
+reg              E_ctrl_rot;
+wire             E_ctrl_rot_nxt;
+reg              E_ctrl_set_src2_rem_imm;
+wire             E_ctrl_set_src2_rem_imm_nxt;
+reg              E_ctrl_shift_right_arith;
+wire             E_ctrl_shift_right_arith_nxt;
+reg              E_ctrl_shift_rot;
+reg              E_ctrl_shift_rot_left;
+wire             E_ctrl_shift_rot_left_nxt;
+wire             E_ctrl_shift_rot_nxt;
+reg              E_ctrl_shift_rot_right;
+wire             E_ctrl_shift_rot_right_nxt;
+reg              E_ctrl_signed_imm12;
+wire             E_ctrl_signed_imm12_nxt;
+reg              E_ctrl_src2_choose_imm;
+wire             E_ctrl_src2_choose_imm_nxt;
+reg              E_ctrl_src_imm5_shift_rot;
+wire             E_ctrl_src_imm5_shift_rot_nxt;
+wire             E_ctrl_st;
+wire             E_ctrl_st16;
+wire             E_ctrl_st8;
+wire             E_ctrl_st_bypass;
+wire             E_ctrl_st_cache;
+reg              E_ctrl_st_ex;
+wire             E_ctrl_st_ex_nxt;
+wire             E_ctrl_st_io;
+wire             E_ctrl_st_non32;
+wire             E_ctrl_st_non_bypass;
+wire             E_ctrl_st_non_io;
+wire             E_ctrl_stnon32_cache;
+reg              E_ctrl_supervisor_only;
+wire             E_ctrl_supervisor_only_nxt;
+reg              E_ctrl_trap_inst;
+wire             E_ctrl_trap_inst_nxt;
+reg              E_ctrl_uncond_cti_non_br;
+wire             E_ctrl_uncond_cti_non_br_nxt;
+reg              E_ctrl_unimp_nop;
+wire             E_ctrl_unimp_nop_nxt;
+reg              E_ctrl_unimp_trap;
+wire             E_ctrl_unimp_trap_nxt;
+reg              E_ctrl_unsigned_lo_imm16;
+wire             E_ctrl_unsigned_lo_imm16_nxt;
+wire             E_ctrl_wrctl_inst;
+reg     [  4: 0] E_dst_regnum;
+wire             E_dtcm_ld;
+wire             E_dtcm_ld_st;
+wire             E_dtcm_st;
+wire             E_en;
+wire             E_eq;
+wire             E_exc_break_inst_pri15;
+wire             E_exc_illegal_inst_pri15;
+wire             E_exc_inst_fetch;
+wire             E_exc_trap_inst_pri15;
+wire             E_exc_unimp_inst_pri15;
+reg     [ 26: 0] E_extra_pc;
+wire    [ 28: 0] E_extra_pcb;
+wire    [ 31: 0] E_fwd_reg_data;
+wire    [ 55: 0] E_inst;
+wire             E_is_opx_inst;
+reg     [ 31: 0] E_iw;
+wire    [  4: 0] E_iw_a;
+wire    [  4: 0] E_iw_b;
+wire    [  4: 0] E_iw_c;
+wire    [  4: 0] E_iw_control_regnum;
+reg              E_iw_corrupt;
+wire    [  7: 0] E_iw_custom_n;
+wire             E_iw_custom_readra;
+wire             E_iw_custom_readrb;
+wire             E_iw_custom_writerc;
+wire    [ 15: 0] E_iw_imm16;
+wire    [ 25: 0] E_iw_imm26;
+wire    [  4: 0] E_iw_imm5;
+wire    [  1: 0] E_iw_memsz;
+wire    [  5: 0] E_iw_op;
+wire    [  5: 0] E_iw_opx;
+wire             E_ld_bus;
+wire             E_ld_cache;
+wire             E_ld_st_bus;
+wire             E_ld_st_cache;
+wire             E_ld_st_dcache_management_bus;
+wire             E_ld_stnon32_cache;
+reg     [  1: 0] E_logic_op;
+wire    [ 31: 0] E_logic_result;
+wire             E_lt;
+wire             E_mem16;
+wire             E_mem32;
+wire             E_mem8;
+wire    [ 28: 0] E_mem_baddr;
+wire    [  1: 0] E_mem_baddr_byte_field;
+wire             E_mem_baddr_corrupt;
+wire    [  5: 0] E_mem_baddr_line_field;
+wire    [  8: 0] E_mem_baddr_line_offset_field;
+wire    [  2: 0] E_mem_baddr_offset_field;
+wire    [ 17: 0] E_mem_baddr_tag_field;
+wire             E_mem_bypass_non_io;
+wire    [  3: 0] E_mem_byte_en;
+wire             E_oci_sync_hbreak_req;
+wire             E_op_add;
+wire             E_op_addi;
+wire             E_op_and;
+wire             E_op_andhi;
+wire             E_op_andi;
+wire             E_op_beq;
+wire             E_op_bge;
+wire             E_op_bgeu;
+wire             E_op_blt;
+wire             E_op_bltu;
+wire             E_op_bne;
+wire             E_op_br;
+wire             E_op_break;
+wire             E_op_bret;
+wire             E_op_call;
+wire             E_op_callr;
+wire             E_op_cmpeq;
+wire             E_op_cmpeqi;
+wire             E_op_cmpge;
+wire             E_op_cmpgei;
+wire             E_op_cmpgeu;
+wire             E_op_cmpgeui;
+wire             E_op_cmplt;
+wire             E_op_cmplti;
+wire             E_op_cmpltu;
+wire             E_op_cmpltui;
+wire             E_op_cmpne;
+wire             E_op_cmpnei;
+wire             E_op_crst;
+wire             E_op_custom;
+wire             E_op_div;
+wire             E_op_divu;
+wire             E_op_eret;
+wire             E_op_flushd;
+wire             E_op_flushda;
+wire             E_op_flushi;
+wire             E_op_flushp;
+wire             E_op_hbreak;
+wire             E_op_initd;
+wire             E_op_initda;
+wire             E_op_initi;
+wire             E_op_intr;
+wire             E_op_jmp;
+wire             E_op_jmpi;
+wire             E_op_ldb;
+wire             E_op_ldbio;
+wire             E_op_ldbu;
+wire             E_op_ldbuio;
+wire             E_op_ldh;
+wire             E_op_ldhio;
+wire             E_op_ldhu;
+wire             E_op_ldhuio;
+wire             E_op_ldl;
+wire             E_op_ldw;
+wire             E_op_ldwio;
+wire             E_op_mul;
+wire             E_op_muli;
+wire             E_op_mulxss;
+wire             E_op_mulxsu;
+wire             E_op_mulxuu;
+wire             E_op_nextpc;
+wire             E_op_nor;
+wire             E_op_op_rsv02;
+wire             E_op_op_rsv09;
+wire             E_op_op_rsv10;
+wire             E_op_op_rsv17;
+wire             E_op_op_rsv18;
+wire             E_op_op_rsv25;
+wire             E_op_op_rsv26;
+wire             E_op_op_rsv33;
+wire             E_op_op_rsv34;
+wire             E_op_op_rsv41;
+wire             E_op_op_rsv42;
+wire             E_op_op_rsv49;
+wire             E_op_op_rsv57;
+wire             E_op_op_rsv61;
+wire             E_op_op_rsv62;
+wire             E_op_op_rsv63;
+wire             E_op_opx_rsv00;
+wire             E_op_opx_rsv10;
+wire             E_op_opx_rsv15;
+wire             E_op_opx_rsv17;
+wire             E_op_opx_rsv21;
+wire             E_op_opx_rsv25;
+wire             E_op_opx_rsv33;
+wire             E_op_opx_rsv34;
+wire             E_op_opx_rsv35;
+wire             E_op_opx_rsv42;
+wire             E_op_opx_rsv43;
+wire             E_op_opx_rsv44;
+wire             E_op_opx_rsv47;
+wire             E_op_opx_rsv50;
+wire             E_op_opx_rsv51;
+wire             E_op_opx_rsv55;
+wire             E_op_opx_rsv56;
+wire             E_op_opx_rsv60;
+wire             E_op_opx_rsv63;
+wire             E_op_or;
+wire             E_op_orhi;
+wire             E_op_ori;
+wire             E_op_rdctl;
+wire             E_op_rdprs;
+wire             E_op_ret;
+wire             E_op_rol;
+wire             E_op_roli;
+wire             E_op_ror;
+wire             E_op_sll;
+wire             E_op_slli;
+wire             E_op_sra;
+wire             E_op_srai;
+wire             E_op_srl;
+wire             E_op_srli;
+wire             E_op_stb;
+wire             E_op_stbio;
+wire             E_op_stc;
+wire             E_op_sth;
+wire             E_op_sthio;
+wire             E_op_stw;
+wire             E_op_stwio;
+wire             E_op_sub;
+wire             E_op_sync;
+wire             E_op_trap;
+wire             E_op_wrctl;
+wire             E_op_wrprs;
+wire             E_op_xor;
+wire             E_op_xorhi;
+wire             E_op_xori;
+reg     [ 26: 0] E_pc;
+reg     [ 28: 0] E_pcb;
+wire             E_rot_fill_bit;
+wire    [  7: 0] E_rot_left_mask;
+wire    [  7: 0] E_rot_mask;
+wire    [  4: 0] E_rot_n;
+wire             E_rot_pass0;
+wire             E_rot_pass1;
+wire             E_rot_pass2;
+wire             E_rot_pass3;
+wire    [ 31: 0] E_rot_prestep1;
+wire    [  7: 0] E_rot_right_mask;
+wire    [  4: 0] E_rot_rn;
+wire             E_rot_sel_fill0;
+wire             E_rot_sel_fill1;
+wire             E_rot_sel_fill2;
+wire             E_rot_sel_fill3;
+wire    [ 31: 0] E_rot_step1;
+wire             E_sel_data_master;
+wire             E_sel_dtcm;
+reg     [ 31: 0] E_src1;
+wire             E_src1_corrupt;
+wire             E_src1_eq_src2;
+wire             E_src1_from_rf;
+reg     [ 31: 0] E_src2;
+wire             E_src2_corrupt;
+wire             E_src2_from_rf;
+reg     [ 31: 0] E_src2_reg;
+wire             E_st_bus;
+wire             E_st_cache;
+wire    [ 31: 0] E_st_data;
+wire             E_st_writes_mem;
+wire             E_stall;
+wire    [  7: 0] E_stb_data;
+wire    [ 15: 0] E_sth_data;
+wire             E_stnon32_cache;
+wire    [ 31: 0] E_stw_data;
+wire             E_up_ex_mon_state_latest;
+wire             E_valid;
+reg              E_valid_from_D;
+reg              E_valid_jmp_indirect;
+wire    [ 71: 0] E_vinst;
+wire             E_wr_dst_reg;
+reg              E_wr_dst_reg_from_D;
+wire    [  1: 0] F_bht_data;
+reg     [  7: 0] F_bht_ptr;
+wire    [  7: 0] F_bht_ptr_nxt;
+wire    [ 10: 0] F_br_taken_waddr_partial;
+wire             F_ctrl_a_not_src;
+wire             F_ctrl_b_is_dst;
+wire             F_ctrl_b_not_src;
+wire             F_ctrl_br;
+wire             F_ctrl_br_uncond;
+wire             F_ctrl_hi_imm16;
+wire             F_ctrl_ignore_dst;
+wire             F_ctrl_implicit_dst_eretaddr;
+wire             F_ctrl_implicit_dst_retaddr;
+wire             F_ctrl_jmp_direct;
+wire             F_ctrl_src2_choose_imm;
+wire             F_ctrl_unsigned_lo_imm16;
+wire             F_en;
+wire    [  8: 0] F_ic_data_rd_addr_nxt;
+wire    [ 17: 0] F_ic_desired_tag;
+wire             F_ic_fill_same_tag_line;
+wire             F_ic_hit;
+wire    [ 31: 0] F_ic_iw;
+wire    [ 17: 0] F_ic_tag_field;
+wire    [ 25: 0] F_ic_tag_rd;
+wire    [  5: 0] F_ic_tag_rd_addr_nxt;
+wire             F_ic_valid;
+wire    [  7: 0] F_ic_valid_bits;
+wire    [ 55: 0] F_inst;
+wire             F_is_opx_inst;
+wire             F_issue;
+wire    [ 31: 0] F_iw;
+wire    [  4: 0] F_iw_a;
+wire    [  4: 0] F_iw_a_rf;
+wire             F_iw_avail;
+wire    [  4: 0] F_iw_b;
+wire    [  4: 0] F_iw_b_rf;
+wire    [  4: 0] F_iw_c;
+wire    [  4: 0] F_iw_control_regnum;
+wire    [  7: 0] F_iw_custom_n;
+wire             F_iw_custom_readra;
+wire             F_iw_custom_readrb;
+wire             F_iw_custom_writerc;
+wire    [ 15: 0] F_iw_imm16;
+wire    [ 25: 0] F_iw_imm26;
+wire    [  4: 0] F_iw_imm5;
+wire    [  1: 0] F_iw_memsz;
+wire    [  5: 0] F_iw_op;
+wire    [  5: 0] F_iw_opx;
+wire             F_iw_valid;
+wire             F_kill;
+wire             F_mem16;
+wire             F_mem32;
+wire             F_mem8;
+wire             F_older_non_sequential;
+wire             F_op_add;
+wire             F_op_addi;
+wire             F_op_and;
+wire             F_op_andhi;
+wire             F_op_andi;
+wire             F_op_beq;
+wire             F_op_bge;
+wire             F_op_bgeu;
+wire             F_op_blt;
+wire             F_op_bltu;
+wire             F_op_bne;
+wire             F_op_br;
+wire             F_op_break;
+wire             F_op_bret;
+wire             F_op_call;
+wire             F_op_callr;
+wire             F_op_cmpeq;
+wire             F_op_cmpeqi;
+wire             F_op_cmpge;
+wire             F_op_cmpgei;
+wire             F_op_cmpgeu;
+wire             F_op_cmpgeui;
+wire             F_op_cmplt;
+wire             F_op_cmplti;
+wire             F_op_cmpltu;
+wire             F_op_cmpltui;
+wire             F_op_cmpne;
+wire             F_op_cmpnei;
+wire             F_op_crst;
+wire             F_op_custom;
+wire             F_op_div;
+wire             F_op_divu;
+wire             F_op_eret;
+wire             F_op_flushd;
+wire             F_op_flushda;
+wire             F_op_flushi;
+wire             F_op_flushp;
+wire             F_op_hbreak;
+wire             F_op_initd;
+wire             F_op_initda;
+wire             F_op_initi;
+wire             F_op_intr;
+wire             F_op_jmp;
+wire             F_op_jmpi;
+wire             F_op_ldb;
+wire             F_op_ldbio;
+wire             F_op_ldbu;
+wire             F_op_ldbuio;
+wire             F_op_ldh;
+wire             F_op_ldhio;
+wire             F_op_ldhu;
+wire             F_op_ldhuio;
+wire             F_op_ldl;
+wire             F_op_ldw;
+wire             F_op_ldwio;
+wire             F_op_mul;
+wire             F_op_muli;
+wire             F_op_mulxss;
+wire             F_op_mulxsu;
+wire             F_op_mulxuu;
+wire             F_op_nextpc;
+wire             F_op_nor;
+wire             F_op_op_rsv02;
+wire             F_op_op_rsv09;
+wire             F_op_op_rsv10;
+wire             F_op_op_rsv17;
+wire             F_op_op_rsv18;
+wire             F_op_op_rsv25;
+wire             F_op_op_rsv26;
+wire             F_op_op_rsv33;
+wire             F_op_op_rsv34;
+wire             F_op_op_rsv41;
+wire             F_op_op_rsv42;
+wire             F_op_op_rsv49;
+wire             F_op_op_rsv57;
+wire             F_op_op_rsv61;
+wire             F_op_op_rsv62;
+wire             F_op_op_rsv63;
+wire             F_op_opx_rsv00;
+wire             F_op_opx_rsv10;
+wire             F_op_opx_rsv15;
+wire             F_op_opx_rsv17;
+wire             F_op_opx_rsv21;
+wire             F_op_opx_rsv25;
+wire             F_op_opx_rsv33;
+wire             F_op_opx_rsv34;
+wire             F_op_opx_rsv35;
+wire             F_op_opx_rsv42;
+wire             F_op_opx_rsv43;
+wire             F_op_opx_rsv44;
+wire             F_op_opx_rsv47;
+wire             F_op_opx_rsv50;
+wire             F_op_opx_rsv51;
+wire             F_op_opx_rsv55;
+wire             F_op_opx_rsv56;
+wire             F_op_opx_rsv60;
+wire             F_op_opx_rsv63;
+wire             F_op_or;
+wire             F_op_orhi;
+wire             F_op_ori;
+wire             F_op_rdctl;
+wire             F_op_rdprs;
+wire             F_op_ret;
+wire             F_op_rol;
+wire             F_op_roli;
+wire             F_op_ror;
+wire             F_op_sll;
+wire             F_op_slli;
+wire             F_op_sra;
+wire             F_op_srai;
+wire             F_op_srl;
+wire             F_op_srli;
+wire             F_op_stb;
+wire             F_op_stbio;
+wire             F_op_stc;
+wire             F_op_sth;
+wire             F_op_sthio;
+wire             F_op_stw;
+wire             F_op_stwio;
+wire             F_op_sub;
+wire             F_op_sync;
+wire             F_op_trap;
+wire             F_op_wrctl;
+wire             F_op_wrprs;
+wire             F_op_xor;
+wire             F_op_xorhi;
+wire             F_op_xori;
+reg     [ 26: 0] F_pc;
+wire    [  5: 0] F_pc_line_field;
+wire    [ 26: 0] F_pc_nxt;
+wire    [ 26: 0] F_pc_plus_one;
+wire    [ 17: 0] F_pc_tag_field;
+wire    [ 28: 0] F_pcb;
+wire    [ 28: 0] F_pcb_nxt;
+wire    [  4: 0] F_rf_rd_addr_a;
+wire    [  4: 0] F_rf_rd_addr_b;
+wire             F_sel_instruction_master;
+wire             F_sel_itcm;
+wire             F_stall;
+wire    [ 71: 0] F_vinst;
+wire             M_A_dc_tag_line_addr_match;
+wire             M_A_dc_tag_ram_addr_match;
+wire             M_W_dc_tag_ram_addr_match;
+reg     [ 31: 0] M_alu_result;
+reg     [  1: 0] M_bht_data;
+wire    [  7: 0] M_bht_ptr_filtered;
+reg     [  7: 0] M_bht_ptr_unfiltered;
+wire    [  1: 0] M_bht_wr_data_filtered;
+wire    [  1: 0] M_bht_wr_data_unfiltered;
+wire             M_bht_wr_en_filtered;
+wire             M_bht_wr_en_unfiltered;
+reg              M_br_actually_taken;
+reg     [  7: 0] M_br_cond_taken_history;
+reg              M_br_mispredict;
+reg     [ 28: 0] M_br_taken_baddr;
+reg              M_cmp_result;
+reg     [ 31: 0] M_control_reg_rddata;
+reg              M_ctrl_a_not_src;
+wire             M_ctrl_a_not_src_nxt;
+reg              M_ctrl_alu_force_and;
+wire             M_ctrl_alu_force_and_nxt;
+reg              M_ctrl_alu_force_xor;
+wire             M_ctrl_alu_force_xor_nxt;
+reg              M_ctrl_alu_signed_comparison;
+wire             M_ctrl_alu_signed_comparison_nxt;
+reg              M_ctrl_alu_subtract;
+wire             M_ctrl_alu_subtract_nxt;
+reg              M_ctrl_b_is_dst;
+wire             M_ctrl_b_is_dst_nxt;
+reg              M_ctrl_b_not_src;
+wire             M_ctrl_b_not_src_nxt;
+reg              M_ctrl_bmx;
+wire             M_ctrl_bmx_nxt;
+reg              M_ctrl_br;
+reg              M_ctrl_br_always_pred_taken;
+wire             M_ctrl_br_always_pred_taken_nxt;
+reg              M_ctrl_br_cond;
+wire             M_ctrl_br_cond_nxt;
+wire             M_ctrl_br_nxt;
+reg              M_ctrl_br_uncond;
+wire             M_ctrl_br_uncond_nxt;
+reg              M_ctrl_break;
+wire             M_ctrl_break_nxt;
+reg              M_ctrl_cmp;
+wire             M_ctrl_cmp_nxt;
+reg              M_ctrl_crst;
+wire             M_ctrl_crst_nxt;
+reg              M_ctrl_custom_combo;
+wire             M_ctrl_custom_combo_nxt;
+reg              M_ctrl_custom_multi;
+wire             M_ctrl_custom_multi_nxt;
+reg              M_ctrl_dc_addr_inv;
+wire             M_ctrl_dc_addr_inv_nxt;
+reg              M_ctrl_dc_addr_nowb_inv;
+wire             M_ctrl_dc_addr_nowb_inv_nxt;
+reg              M_ctrl_dc_addr_wb_inv;
+wire             M_ctrl_dc_addr_wb_inv_nxt;
+reg              M_ctrl_dc_index_inv;
+wire             M_ctrl_dc_index_inv_nxt;
+reg              M_ctrl_dc_index_nowb_inv;
+wire             M_ctrl_dc_index_nowb_inv_nxt;
+reg              M_ctrl_dc_index_wb_inv;
+wire             M_ctrl_dc_index_wb_inv_nxt;
+reg              M_ctrl_dc_nowb_inv;
+wire             M_ctrl_dc_nowb_inv_nxt;
+reg              M_ctrl_dcache_management;
+wire             M_ctrl_dcache_management_nxt;
+reg              M_ctrl_exception;
+wire             M_ctrl_exception_nxt;
+reg              M_ctrl_flush_pipe_always;
+wire             M_ctrl_flush_pipe_always_nxt;
+reg              M_ctrl_hi_imm16;
+wire             M_ctrl_hi_imm16_nxt;
+reg              M_ctrl_ignore_dst;
+wire             M_ctrl_ignore_dst_nxt;
+reg              M_ctrl_illegal;
+wire             M_ctrl_illegal_nxt;
+reg              M_ctrl_implicit_dst_eretaddr;
+wire             M_ctrl_implicit_dst_eretaddr_nxt;
+reg              M_ctrl_implicit_dst_retaddr;
+wire             M_ctrl_implicit_dst_retaddr_nxt;
+reg              M_ctrl_intr_inst;
+wire             M_ctrl_intr_inst_nxt;
+reg              M_ctrl_invalidate_i;
+wire             M_ctrl_invalidate_i_nxt;
+reg              M_ctrl_jmp_direct;
+wire             M_ctrl_jmp_direct_nxt;
+reg              M_ctrl_jmp_indirect;
+wire             M_ctrl_jmp_indirect_nxt;
+reg              M_ctrl_late_result;
+wire             M_ctrl_late_result_nxt;
+reg              M_ctrl_ld;
+reg              M_ctrl_ld16;
+wire             M_ctrl_ld16_nxt;
+reg              M_ctrl_ld32;
+wire             M_ctrl_ld32_nxt;
+reg              M_ctrl_ld8;
+reg              M_ctrl_ld8_ld16;
+wire             M_ctrl_ld8_ld16_nxt;
+wire             M_ctrl_ld8_nxt;
+reg              M_ctrl_ld_bypass;
+wire             M_ctrl_ld_bypass_nxt;
+reg              M_ctrl_ld_cache;
+wire             M_ctrl_ld_cache_nxt;
+reg              M_ctrl_ld_dcache_management;
+wire             M_ctrl_ld_dcache_management_nxt;
+reg              M_ctrl_ld_ex;
+wire             M_ctrl_ld_ex_nxt;
+reg              M_ctrl_ld_io;
+wire             M_ctrl_ld_io_nxt;
+reg              M_ctrl_ld_non_bypass;
+wire             M_ctrl_ld_non_bypass_nxt;
+reg              M_ctrl_ld_non_io;
+wire             M_ctrl_ld_non_io_nxt;
+wire             M_ctrl_ld_nxt;
+reg              M_ctrl_ld_signed;
+wire             M_ctrl_ld_signed_nxt;
+reg              M_ctrl_ld_st;
+reg              M_ctrl_ld_st_bypass;
+wire             M_ctrl_ld_st_bypass_nxt;
+reg              M_ctrl_ld_st_bypass_or_dcache_management;
+wire             M_ctrl_ld_st_bypass_or_dcache_management_nxt;
+reg              M_ctrl_ld_st_cache;
+wire             M_ctrl_ld_st_cache_nxt;
+reg              M_ctrl_ld_st_ex;
+wire             M_ctrl_ld_st_ex_nxt;
+reg              M_ctrl_ld_st_io;
+wire             M_ctrl_ld_st_io_nxt;
+reg              M_ctrl_ld_st_non_bypass;
+wire             M_ctrl_ld_st_non_bypass_nxt;
+reg              M_ctrl_ld_st_non_io;
+wire             M_ctrl_ld_st_non_io_nxt;
+wire             M_ctrl_ld_st_nxt;
+reg              M_ctrl_ld_stnon32_cache;
+wire             M_ctrl_ld_stnon32_cache_nxt;
+reg              M_ctrl_logic;
+wire             M_ctrl_logic_nxt;
+reg              M_ctrl_mem;
+reg              M_ctrl_mem16;
+wire             M_ctrl_mem16_nxt;
+reg              M_ctrl_mem32;
+wire             M_ctrl_mem32_nxt;
+reg              M_ctrl_mem8;
+wire             M_ctrl_mem8_nxt;
+reg              M_ctrl_mem_data_access;
+wire             M_ctrl_mem_data_access_nxt;
+reg              M_ctrl_mem_dc_data_rd;
+wire             M_ctrl_mem_dc_data_rd_nxt;
+reg              M_ctrl_mem_dc_tag_rd;
+wire             M_ctrl_mem_dc_tag_rd_nxt;
+wire             M_ctrl_mem_nxt;
+reg              M_ctrl_mul_lsw;
+wire             M_ctrl_mul_lsw_nxt;
+reg              M_ctrl_rd_ctl_reg;
+wire             M_ctrl_rd_ctl_reg_nxt;
+reg              M_ctrl_retaddr;
+wire             M_ctrl_retaddr_nxt;
+reg              M_ctrl_rot;
+wire             M_ctrl_rot_nxt;
+reg              M_ctrl_set_src2_rem_imm;
+wire             M_ctrl_set_src2_rem_imm_nxt;
+reg              M_ctrl_shift_right_arith;
+wire             M_ctrl_shift_right_arith_nxt;
+reg              M_ctrl_shift_rot;
+reg              M_ctrl_shift_rot_left;
+wire             M_ctrl_shift_rot_left_nxt;
+wire             M_ctrl_shift_rot_nxt;
+reg              M_ctrl_shift_rot_right;
+wire             M_ctrl_shift_rot_right_nxt;
+reg              M_ctrl_signed_imm12;
+wire             M_ctrl_signed_imm12_nxt;
+reg              M_ctrl_src2_choose_imm;
+wire             M_ctrl_src2_choose_imm_nxt;
+reg              M_ctrl_src_imm5_shift_rot;
+wire             M_ctrl_src_imm5_shift_rot_nxt;
+reg              M_ctrl_st;
+reg              M_ctrl_st16;
+wire             M_ctrl_st16_nxt;
+reg              M_ctrl_st8;
+wire             M_ctrl_st8_nxt;
+reg              M_ctrl_st_bypass;
+wire             M_ctrl_st_bypass_nxt;
+reg              M_ctrl_st_cache;
+wire             M_ctrl_st_cache_nxt;
+reg              M_ctrl_st_ex;
+wire             M_ctrl_st_ex_nxt;
+reg              M_ctrl_st_io;
+wire             M_ctrl_st_io_nxt;
+reg              M_ctrl_st_non32;
+wire             M_ctrl_st_non32_nxt;
+reg              M_ctrl_st_non_bypass;
+wire             M_ctrl_st_non_bypass_nxt;
+reg              M_ctrl_st_non_io;
+wire             M_ctrl_st_non_io_nxt;
+wire             M_ctrl_st_nxt;
+reg              M_ctrl_stnon32_cache;
+wire             M_ctrl_stnon32_cache_nxt;
+reg              M_ctrl_supervisor_only;
+wire             M_ctrl_supervisor_only_nxt;
+reg              M_ctrl_trap_inst;
+wire             M_ctrl_trap_inst_nxt;
+reg              M_ctrl_uncond_cti_non_br;
+wire             M_ctrl_uncond_cti_non_br_nxt;
+reg              M_ctrl_unimp_nop;
+wire             M_ctrl_unimp_nop_nxt;
+reg              M_ctrl_unimp_trap;
+wire             M_ctrl_unimp_trap_nxt;
+reg              M_ctrl_unsigned_lo_imm16;
+wire             M_ctrl_unsigned_lo_imm16_nxt;
+reg              M_ctrl_wrctl_inst;
+wire             M_ctrl_wrctl_inst_nxt;
+wire             M_data_ram_ld_align_sign_bit;
+wire    [  1: 0] M_data_ram_ld_align_sign_bit_16;
+reg              M_data_ram_ld_align_sign_bit_16_hi;
+wire    [ 17: 0] M_dc_actual_tag;
+wire             M_dc_bypass_or_dcache_management;
+wire    [ 17: 0] M_dc_desired_tag;
+wire             M_dc_dirty;
+wire             M_dc_dirty_raw;
+wire             M_dc_hit;
+wire             M_dc_raw_hazard;
+wire    [ 31: 0] M_dc_rd_data;
+wire    [ 31: 0] M_dc_st_data;
+wire    [ 19: 0] M_dc_tag_entry;
+wire             M_dc_tag_match;
+wire             M_dc_valid;
+wire             M_dc_want_fill;
+reg     [  4: 0] M_dst_regnum;
+wire             M_dtcm_ld;
+wire             M_dtcm_st;
+wire             M_dtcm_st_non32;
+wire             M_en;
+wire             M_exc_allowed;
+wire             M_exc_any;
+wire             M_exc_break;
+reg              M_exc_break_inst_pri15;
+wire             M_exc_break_inst_pri15_nxt;
+wire             M_exc_crst;
+wire             M_exc_ext_intr;
+wire             M_exc_hbreak_pri1;
+wire             M_exc_higher_priority_than_tlb_data;
+reg              M_exc_illegal_inst_pri15;
+wire             M_exc_illegal_inst_pri15_nxt;
+wire             M_exc_inst_fetch;
+wire             M_exc_norm_intr_pri5;
+reg              M_exc_trap_inst_pri15;
+wire             M_exc_trap_inst_pri15_nxt;
+reg              M_exc_unimp_inst_pri15;
+wire             M_exc_unimp_inst_pri15_nxt;
+wire    [ 31: 0] M_fwd_reg_data;
+wire             M_hbreak_req;
+wire             M_ignore_exc;
+wire    [ 55: 0] M_inst;
+wire    [ 31: 0] M_inst_result;
+wire             M_is_opx_inst;
+reg     [ 31: 0] M_iw;
+wire    [  4: 0] M_iw_a;
+wire    [  4: 0] M_iw_b;
+wire    [  4: 0] M_iw_c;
+wire    [  4: 0] M_iw_control_regnum;
+reg              M_iw_corrupt;
+wire    [  7: 0] M_iw_custom_n;
+wire             M_iw_custom_readra;
+wire             M_iw_custom_readrb;
+wire             M_iw_custom_writerc;
+wire    [ 15: 0] M_iw_imm16;
+wire    [ 25: 0] M_iw_imm26;
+wire    [  4: 0] M_iw_imm5;
+wire    [  1: 0] M_iw_memsz;
+wire    [  5: 0] M_iw_op;
+wire    [  5: 0] M_iw_opx;
+wire             M_ld_align_byte1_fill;
+wire             M_ld_align_byte2_byte3_fill;
+wire             M_ld_align_sh16;
+wire             M_ld_align_sh8;
+wire             M_mem16;
+wire             M_mem32;
+wire             M_mem8;
+reg     [ 28: 0] M_mem_baddr;
+wire    [  1: 0] M_mem_baddr_byte_field;
+reg              M_mem_baddr_corrupt;
+wire    [  5: 0] M_mem_baddr_line_field;
+wire    [  8: 0] M_mem_baddr_line_offset_field;
+wire    [  2: 0] M_mem_baddr_offset_field;
+wire    [ 17: 0] M_mem_baddr_tag_field;
+reg     [  3: 0] M_mem_byte_en;
+wire    [ 26: 0] M_mem_waddr;
+wire    [ 26: 0] M_mem_waddr_phy;
+wire    [ 31: 0] M_mul_cell_p1;
+wire    [ 31: 0] M_mul_cell_p2;
+wire    [ 31: 0] M_mul_cell_p3;
+wire    [ 16: 0] M_mul_s1;
+wire             M_non_flushing_wrctl;
+reg              M_norm_intr_req;
+reg              M_oci_sync_hbreak_req;
+wire             M_op_add;
+wire             M_op_addi;
+wire             M_op_and;
+wire             M_op_andhi;
+wire             M_op_andi;
+wire             M_op_beq;
+wire             M_op_bge;
+wire             M_op_bgeu;
+wire             M_op_blt;
+wire             M_op_bltu;
+wire             M_op_bne;
+wire             M_op_br;
+wire             M_op_break;
+wire             M_op_bret;
+wire             M_op_call;
+wire             M_op_callr;
+wire             M_op_cmpeq;
+wire             M_op_cmpeqi;
+wire             M_op_cmpge;
+wire             M_op_cmpgei;
+wire             M_op_cmpgeu;
+wire             M_op_cmpgeui;
+wire             M_op_cmplt;
+wire             M_op_cmplti;
+wire             M_op_cmpltu;
+wire             M_op_cmpltui;
+wire             M_op_cmpne;
+wire             M_op_cmpnei;
+wire             M_op_crst;
+wire             M_op_custom;
+wire             M_op_div;
+wire             M_op_divu;
+wire             M_op_eret;
+wire             M_op_flushd;
+wire             M_op_flushda;
+wire             M_op_flushi;
+wire             M_op_flushp;
+wire             M_op_hbreak;
+wire             M_op_initd;
+wire             M_op_initda;
+wire             M_op_initi;
+wire             M_op_intr;
+wire             M_op_jmp;
+wire             M_op_jmpi;
+wire             M_op_ldb;
+wire             M_op_ldbio;
+wire             M_op_ldbu;
+wire             M_op_ldbuio;
+wire             M_op_ldh;
+wire             M_op_ldhio;
+wire             M_op_ldhu;
+wire             M_op_ldhuio;
+wire             M_op_ldl;
+wire             M_op_ldw;
+wire             M_op_ldwio;
+wire             M_op_mul;
+wire             M_op_muli;
+wire             M_op_mulxss;
+wire             M_op_mulxsu;
+wire             M_op_mulxuu;
+wire             M_op_nextpc;
+wire             M_op_nor;
+wire             M_op_op_rsv02;
+wire             M_op_op_rsv09;
+wire             M_op_op_rsv10;
+wire             M_op_op_rsv17;
+wire             M_op_op_rsv18;
+wire             M_op_op_rsv25;
+wire             M_op_op_rsv26;
+wire             M_op_op_rsv33;
+wire             M_op_op_rsv34;
+wire             M_op_op_rsv41;
+wire             M_op_op_rsv42;
+wire             M_op_op_rsv49;
+wire             M_op_op_rsv57;
+wire             M_op_op_rsv61;
+wire             M_op_op_rsv62;
+wire             M_op_op_rsv63;
+wire             M_op_opx_rsv00;
+wire             M_op_opx_rsv10;
+wire             M_op_opx_rsv15;
+wire             M_op_opx_rsv17;
+wire             M_op_opx_rsv21;
+wire             M_op_opx_rsv25;
+wire             M_op_opx_rsv33;
+wire             M_op_opx_rsv34;
+wire             M_op_opx_rsv35;
+wire             M_op_opx_rsv42;
+wire             M_op_opx_rsv43;
+wire             M_op_opx_rsv44;
+wire             M_op_opx_rsv47;
+wire             M_op_opx_rsv50;
+wire             M_op_opx_rsv51;
+wire             M_op_opx_rsv55;
+wire             M_op_opx_rsv56;
+wire             M_op_opx_rsv60;
+wire             M_op_opx_rsv63;
+wire             M_op_or;
+wire             M_op_orhi;
+wire             M_op_ori;
+wire             M_op_rdctl;
+wire             M_op_rdprs;
+wire             M_op_ret;
+wire             M_op_rol;
+wire             M_op_roli;
+wire             M_op_ror;
+wire             M_op_sll;
+wire             M_op_slli;
+wire             M_op_sra;
+wire             M_op_srai;
+wire             M_op_srl;
+wire             M_op_srli;
+wire             M_op_stb;
+wire             M_op_stbio;
+wire             M_op_stc;
+wire             M_op_sth;
+wire             M_op_sthio;
+wire             M_op_stw;
+wire             M_op_stwio;
+wire             M_op_sub;
+wire             M_op_sync;
+wire             M_op_trap;
+wire             M_op_wrctl;
+wire             M_op_wrprs;
+wire             M_op_xor;
+wire             M_op_xorhi;
+wire             M_op_xori;
+reg     [ 26: 0] M_pc;
+reg     [ 26: 0] M_pc_plus_one;
+reg     [ 28: 0] M_pcb;
+reg              M_pipe_flush;
+wire    [ 28: 0] M_pipe_flush_baddr;
+wire    [ 28: 0] M_pipe_flush_baddr_nxt;
+wire             M_pipe_flush_nxt;
+reg     [ 26: 0] M_pipe_flush_waddr;
+wire    [ 26: 0] M_pipe_flush_waddr_nxt;
+wire    [ 31: 0] M_ram_rd_data;
+wire    [ 31: 0] M_rdctl_data;
+wire    [ 31: 0] M_rdctl_data_inst_result;
+wire    [ 31: 0] M_rdctl_data_latest;
+wire             M_refetch;
+wire    [ 31: 0] M_rot;
+reg              M_rot_fill_bit;
+wire    [  7: 0] M_rot_lut0;
+wire    [  7: 0] M_rot_lut1;
+wire    [  7: 0] M_rot_lut2;
+wire    [  7: 0] M_rot_lut3;
+reg     [  7: 0] M_rot_mask;
+reg              M_rot_pass0;
+reg              M_rot_pass1;
+reg              M_rot_pass2;
+reg              M_rot_pass3;
+reg     [ 31: 0] M_rot_prestep2;
+reg     [  4: 0] M_rot_rn;
+reg              M_rot_sel_fill0;
+reg              M_rot_sel_fill1;
+reg              M_rot_sel_fill2;
+reg              M_rot_sel_fill3;
+wire    [ 31: 0] M_rot_step2;
+reg              M_sel_data_master;
+wire             M_sel_dtcm;
+reg     [ 31: 0] M_src1;
+reg              M_src1_corrupt;
+reg     [ 31: 0] M_src2;
+reg              M_src2_corrupt;
+reg     [ 31: 0] M_st_data;
+wire             M_st_writes_mem;
+wire             M_stall;
+reg     [ 28: 0] M_target_pcb;
+wire             M_udtlb_refetch;
+wire             M_up_ex_mon_state_latest;
+wire             M_valid;
+reg              M_valid_from_E;
+wire             M_valid_ignoring_refetch;
+wire    [ 71: 0] M_vinst;
+wire             M_wr_dst_reg;
+reg              M_wr_dst_reg_from_E;
+wire    [ 31: 0] W_badaddr_reg;
+reg     [ 28: 0] W_badaddr_reg_baddr;
+wire    [ 28: 0] W_badaddr_reg_baddr_nxt;
+wire             W_badaddr_reg_baddr_wr_en;
+reg     [ 28: 0] W_br_taken_baddr;
+wire    [ 31: 0] W_bstatus_reg;
+reg              W_bstatus_reg_pie;
+wire             W_bstatus_reg_pie_inst_nxt;
+wire             W_bstatus_reg_pie_nxt;
+wire             W_bstatus_reg_pie_wr_en;
+wire    [ 31: 0] W_cdsr_reg;
+reg     [ 31: 0] W_cdsr_reg_status;
+wire    [ 31: 0] W_cdsr_reg_status_nxt;
+wire             W_cdsr_reg_status_wr_en;
+wire    [ 31: 0] W_cpuid_reg;
+reg              W_ctrl_a_not_src;
+wire             W_ctrl_a_not_src_nxt;
+reg              W_ctrl_alu_force_and;
+wire             W_ctrl_alu_force_and_nxt;
+reg              W_ctrl_alu_force_xor;
+wire             W_ctrl_alu_force_xor_nxt;
+reg              W_ctrl_alu_signed_comparison;
+wire             W_ctrl_alu_signed_comparison_nxt;
+reg              W_ctrl_alu_subtract;
+wire             W_ctrl_alu_subtract_nxt;
+reg              W_ctrl_b_is_dst;
+wire             W_ctrl_b_is_dst_nxt;
+reg              W_ctrl_b_not_src;
+wire             W_ctrl_b_not_src_nxt;
+reg              W_ctrl_bmx;
+wire             W_ctrl_bmx_nxt;
+reg              W_ctrl_br;
+reg              W_ctrl_br_always_pred_taken;
+wire             W_ctrl_br_always_pred_taken_nxt;
+reg              W_ctrl_br_cond;
+wire             W_ctrl_br_cond_nxt;
+wire             W_ctrl_br_nxt;
+reg              W_ctrl_br_uncond;
+wire             W_ctrl_br_uncond_nxt;
+reg              W_ctrl_break;
+wire             W_ctrl_break_nxt;
+reg              W_ctrl_cmp;
+wire             W_ctrl_cmp_nxt;
+reg              W_ctrl_crst;
+wire             W_ctrl_crst_nxt;
+reg              W_ctrl_custom_combo;
+wire             W_ctrl_custom_combo_nxt;
+reg              W_ctrl_custom_multi;
+wire             W_ctrl_custom_multi_nxt;
+reg              W_ctrl_dc_addr_inv;
+wire             W_ctrl_dc_addr_inv_nxt;
+reg              W_ctrl_dc_addr_nowb_inv;
+wire             W_ctrl_dc_addr_nowb_inv_nxt;
+reg              W_ctrl_dc_addr_wb_inv;
+wire             W_ctrl_dc_addr_wb_inv_nxt;
+reg              W_ctrl_dc_index_inv;
+wire             W_ctrl_dc_index_inv_nxt;
+reg              W_ctrl_dc_index_nowb_inv;
+wire             W_ctrl_dc_index_nowb_inv_nxt;
+reg              W_ctrl_dc_index_wb_inv;
+wire             W_ctrl_dc_index_wb_inv_nxt;
+reg              W_ctrl_dc_nowb_inv;
+wire             W_ctrl_dc_nowb_inv_nxt;
+reg              W_ctrl_dcache_management;
+wire             W_ctrl_dcache_management_nxt;
+reg              W_ctrl_exception;
+wire             W_ctrl_exception_nxt;
+reg              W_ctrl_flush_pipe_always;
+wire             W_ctrl_flush_pipe_always_nxt;
+reg              W_ctrl_hi_imm16;
+wire             W_ctrl_hi_imm16_nxt;
+reg              W_ctrl_ignore_dst;
+wire             W_ctrl_ignore_dst_nxt;
+reg              W_ctrl_illegal;
+wire             W_ctrl_illegal_nxt;
+reg              W_ctrl_implicit_dst_eretaddr;
+wire             W_ctrl_implicit_dst_eretaddr_nxt;
+reg              W_ctrl_implicit_dst_retaddr;
+wire             W_ctrl_implicit_dst_retaddr_nxt;
+reg              W_ctrl_intr_inst;
+wire             W_ctrl_intr_inst_nxt;
+reg              W_ctrl_invalidate_i;
+wire             W_ctrl_invalidate_i_nxt;
+reg              W_ctrl_jmp_direct;
+wire             W_ctrl_jmp_direct_nxt;
+reg              W_ctrl_jmp_indirect;
+wire             W_ctrl_jmp_indirect_nxt;
+reg              W_ctrl_late_result;
+wire             W_ctrl_late_result_nxt;
+reg              W_ctrl_ld;
+reg              W_ctrl_ld16;
+wire             W_ctrl_ld16_nxt;
+reg              W_ctrl_ld32;
+wire             W_ctrl_ld32_nxt;
+reg              W_ctrl_ld8;
+reg              W_ctrl_ld8_ld16;
+wire             W_ctrl_ld8_ld16_nxt;
+wire             W_ctrl_ld8_nxt;
+reg              W_ctrl_ld_dcache_management;
+wire             W_ctrl_ld_dcache_management_nxt;
+reg              W_ctrl_ld_ex;
+wire             W_ctrl_ld_ex_nxt;
+reg              W_ctrl_ld_io;
+wire             W_ctrl_ld_io_nxt;
+reg              W_ctrl_ld_non_io;
+wire             W_ctrl_ld_non_io_nxt;
+wire             W_ctrl_ld_nxt;
+reg              W_ctrl_ld_signed;
+wire             W_ctrl_ld_signed_nxt;
+reg              W_ctrl_ld_st;
+reg              W_ctrl_ld_st_ex;
+wire             W_ctrl_ld_st_ex_nxt;
+reg              W_ctrl_ld_st_io;
+wire             W_ctrl_ld_st_io_nxt;
+reg              W_ctrl_ld_st_non_io;
+wire             W_ctrl_ld_st_non_io_nxt;
+wire             W_ctrl_ld_st_nxt;
+reg              W_ctrl_logic;
+wire             W_ctrl_logic_nxt;
+reg              W_ctrl_mem;
+reg              W_ctrl_mem16;
+wire             W_ctrl_mem16_nxt;
+reg              W_ctrl_mem32;
+wire             W_ctrl_mem32_nxt;
+reg              W_ctrl_mem8;
+wire             W_ctrl_mem8_nxt;
+reg              W_ctrl_mem_data_access;
+wire             W_ctrl_mem_data_access_nxt;
+wire             W_ctrl_mem_nxt;
+reg              W_ctrl_mul_lsw;
+wire             W_ctrl_mul_lsw_nxt;
+reg              W_ctrl_rd_ctl_reg;
+wire             W_ctrl_rd_ctl_reg_nxt;
+reg              W_ctrl_retaddr;
+wire             W_ctrl_retaddr_nxt;
+reg              W_ctrl_rot;
+wire             W_ctrl_rot_nxt;
+reg              W_ctrl_set_src2_rem_imm;
+wire             W_ctrl_set_src2_rem_imm_nxt;
+reg              W_ctrl_shift_right_arith;
+wire             W_ctrl_shift_right_arith_nxt;
+reg              W_ctrl_shift_rot;
+reg              W_ctrl_shift_rot_left;
+wire             W_ctrl_shift_rot_left_nxt;
+wire             W_ctrl_shift_rot_nxt;
+reg              W_ctrl_shift_rot_right;
+wire             W_ctrl_shift_rot_right_nxt;
+reg              W_ctrl_signed_imm12;
+wire             W_ctrl_signed_imm12_nxt;
+reg              W_ctrl_src2_choose_imm;
+wire             W_ctrl_src2_choose_imm_nxt;
+reg              W_ctrl_src_imm5_shift_rot;
+wire             W_ctrl_src_imm5_shift_rot_nxt;
+reg              W_ctrl_st;
+reg              W_ctrl_st16;
+wire             W_ctrl_st16_nxt;
+reg              W_ctrl_st8;
+wire             W_ctrl_st8_nxt;
+reg              W_ctrl_st_ex;
+wire             W_ctrl_st_ex_nxt;
+reg              W_ctrl_st_io;
+wire             W_ctrl_st_io_nxt;
+reg              W_ctrl_st_non32;
+wire             W_ctrl_st_non32_nxt;
+reg              W_ctrl_st_non_io;
+wire             W_ctrl_st_non_io_nxt;
+wire             W_ctrl_st_nxt;
+reg              W_ctrl_supervisor_only;
+wire             W_ctrl_supervisor_only_nxt;
+reg              W_ctrl_trap_inst;
+wire             W_ctrl_trap_inst_nxt;
+reg              W_ctrl_uncond_cti_non_br;
+wire             W_ctrl_uncond_cti_non_br_nxt;
+reg              W_ctrl_unimp_nop;
+wire             W_ctrl_unimp_nop_nxt;
+reg              W_ctrl_unimp_trap;
+wire             W_ctrl_unimp_trap_nxt;
+reg              W_ctrl_unsigned_lo_imm16;
+wire             W_ctrl_unsigned_lo_imm16_nxt;
+reg              W_ctrl_wrctl_inst;
+wire             W_ctrl_wrctl_inst_nxt;
+reg              W_dc_valid_st_cache_hit;
+reg              W_debug_mode;
+wire             W_debug_mode_nxt;
+reg     [  4: 0] W_dst_regnum;
+wire             W_en;
+wire    [ 31: 0] W_estatus_reg;
+reg              W_estatus_reg_pie;
+wire             W_estatus_reg_pie_inst_nxt;
+wire             W_estatus_reg_pie_nxt;
+wire             W_estatus_reg_pie_wr_en;
+reg              W_exc_break_inst_pri15;
+wire             W_exc_break_inst_pri15_nxt;
+reg              W_exc_crst_active;
+wire             W_exc_handler_mode;
+reg              W_exc_hbreak_pri1;
+wire             W_exc_hbreak_pri1_nxt;
+reg              W_exc_illegal_inst_pri15;
+wire             W_exc_illegal_inst_pri15_nxt;
+reg              W_exc_norm_intr_pri5;
+wire             W_exc_norm_intr_pri5_nxt;
+reg              W_exc_trap_inst_pri15;
+wire             W_exc_trap_inst_pri15_nxt;
+reg              W_exc_unimp_inst_pri15;
+wire             W_exc_unimp_inst_pri15_nxt;
+reg              W_exc_wr_sstatus;
+wire    [ 31: 0] W_exception_reg;
+reg     [  4: 0] W_exception_reg_cause;
+wire    [  4: 0] W_exception_reg_cause_nxt;
+wire             W_exception_reg_cause_wr_en;
+wire    [ 31: 0] W_ienable_reg;
+reg              W_ienable_reg_irq0;
+wire             W_ienable_reg_irq0_nxt;
+wire             W_ienable_reg_irq0_wr_en;
+reg              W_ienable_reg_irq2;
+wire             W_ienable_reg_irq2_nxt;
+wire             W_ienable_reg_irq2_wr_en;
+reg              W_ienable_reg_irq3;
+wire             W_ienable_reg_irq3_nxt;
+wire             W_ienable_reg_irq3_wr_en;
+reg              W_ienable_reg_irq4;
+wire             W_ienable_reg_irq4_nxt;
+wire             W_ienable_reg_irq4_wr_en;
+reg              W_ienable_reg_irq5;
+wire             W_ienable_reg_irq5_nxt;
+wire             W_ienable_reg_irq5_wr_en;
+wire    [ 55: 0] W_inst;
+wire    [ 31: 0] W_ipending_reg;
+reg              W_ipending_reg_irq0;
+wire             W_ipending_reg_irq0_nxt;
+wire             W_ipending_reg_irq0_wr_en;
+reg              W_ipending_reg_irq2;
+wire             W_ipending_reg_irq2_nxt;
+wire             W_ipending_reg_irq2_wr_en;
+reg              W_ipending_reg_irq3;
+wire             W_ipending_reg_irq3_nxt;
+wire             W_ipending_reg_irq3_wr_en;
+reg              W_ipending_reg_irq4;
+wire             W_ipending_reg_irq4_nxt;
+wire             W_ipending_reg_irq4_wr_en;
+reg              W_ipending_reg_irq5;
+wire             W_ipending_reg_irq5_nxt;
+wire             W_ipending_reg_irq5_wr_en;
+wire             W_is_opx_inst;
+reg     [ 31: 0] W_iw;
+wire    [  4: 0] W_iw_a;
+wire    [  4: 0] W_iw_b;
+wire    [  4: 0] W_iw_c;
+wire    [  4: 0] W_iw_control_regnum;
+wire    [  7: 0] W_iw_custom_n;
+wire             W_iw_custom_readra;
+wire             W_iw_custom_readrb;
+wire             W_iw_custom_writerc;
+wire    [ 15: 0] W_iw_imm16;
+wire    [ 25: 0] W_iw_imm26;
+wire    [  4: 0] W_iw_imm5;
+wire    [  1: 0] W_iw_memsz;
+wire    [  5: 0] W_iw_op;
+wire    [  5: 0] W_iw_opx;
+wire             W_mem16;
+wire             W_mem32;
+wire             W_mem8;
+reg     [ 28: 0] W_mem_baddr;
+wire    [  1: 0] W_mem_baddr_byte_field;
+wire    [  5: 0] W_mem_baddr_line_field;
+wire    [  8: 0] W_mem_baddr_line_offset_field;
+wire    [  2: 0] W_mem_baddr_offset_field;
+wire    [ 17: 0] W_mem_baddr_tag_field;
+reg     [  3: 0] W_mem_byte_en;
+wire    [ 26: 0] W_mem_waddr_phy;
+wire             W_op_add;
+wire             W_op_addi;
+wire             W_op_and;
+wire             W_op_andhi;
+wire             W_op_andi;
+wire             W_op_beq;
+wire             W_op_bge;
+wire             W_op_bgeu;
+wire             W_op_blt;
+wire             W_op_bltu;
+wire             W_op_bne;
+wire             W_op_br;
+wire             W_op_break;
+wire             W_op_bret;
+wire             W_op_call;
+wire             W_op_callr;
+wire             W_op_cmpeq;
+wire             W_op_cmpeqi;
+wire             W_op_cmpge;
+wire             W_op_cmpgei;
+wire             W_op_cmpgeu;
+wire             W_op_cmpgeui;
+wire             W_op_cmplt;
+wire             W_op_cmplti;
+wire             W_op_cmpltu;
+wire             W_op_cmpltui;
+wire             W_op_cmpne;
+wire             W_op_cmpnei;
+wire             W_op_crst;
+wire             W_op_custom;
+wire             W_op_div;
+wire             W_op_divu;
+wire             W_op_eret;
+wire             W_op_flushd;
+wire             W_op_flushda;
+wire             W_op_flushi;
+wire             W_op_flushp;
+wire             W_op_hbreak;
+wire             W_op_initd;
+wire             W_op_initda;
+wire             W_op_initi;
+wire             W_op_intr;
+wire             W_op_jmp;
+wire             W_op_jmpi;
+wire             W_op_ldb;
+wire             W_op_ldbio;
+wire             W_op_ldbu;
+wire             W_op_ldbuio;
+wire             W_op_ldh;
+wire             W_op_ldhio;
+wire             W_op_ldhu;
+wire             W_op_ldhuio;
+wire             W_op_ldl;
+wire             W_op_ldw;
+wire             W_op_ldwio;
+wire             W_op_mul;
+wire             W_op_muli;
+wire             W_op_mulxss;
+wire             W_op_mulxsu;
+wire             W_op_mulxuu;
+wire             W_op_nextpc;
+wire             W_op_nor;
+wire             W_op_op_rsv02;
+wire             W_op_op_rsv09;
+wire             W_op_op_rsv10;
+wire             W_op_op_rsv17;
+wire             W_op_op_rsv18;
+wire             W_op_op_rsv25;
+wire             W_op_op_rsv26;
+wire             W_op_op_rsv33;
+wire             W_op_op_rsv34;
+wire             W_op_op_rsv41;
+wire             W_op_op_rsv42;
+wire             W_op_op_rsv49;
+wire             W_op_op_rsv57;
+wire             W_op_op_rsv61;
+wire             W_op_op_rsv62;
+wire             W_op_op_rsv63;
+wire             W_op_opx_rsv00;
+wire             W_op_opx_rsv10;
+wire             W_op_opx_rsv15;
+wire             W_op_opx_rsv17;
+wire             W_op_opx_rsv21;
+wire             W_op_opx_rsv25;
+wire             W_op_opx_rsv33;
+wire             W_op_opx_rsv34;
+wire             W_op_opx_rsv35;
+wire             W_op_opx_rsv42;
+wire             W_op_opx_rsv43;
+wire             W_op_opx_rsv44;
+wire             W_op_opx_rsv47;
+wire             W_op_opx_rsv50;
+wire             W_op_opx_rsv51;
+wire             W_op_opx_rsv55;
+wire             W_op_opx_rsv56;
+wire             W_op_opx_rsv60;
+wire             W_op_opx_rsv63;
+wire             W_op_or;
+wire             W_op_orhi;
+wire             W_op_ori;
+wire             W_op_rdctl;
+wire             W_op_rdprs;
+wire             W_op_ret;
+wire             W_op_rol;
+wire             W_op_roli;
+wire             W_op_ror;
+wire             W_op_sll;
+wire             W_op_slli;
+wire             W_op_sra;
+wire             W_op_srai;
+wire             W_op_srl;
+wire             W_op_srli;
+wire             W_op_stb;
+wire             W_op_stbio;
+wire             W_op_stc;
+wire             W_op_sth;
+wire             W_op_sthio;
+wire             W_op_stw;
+wire             W_op_stwio;
+wire             W_op_sub;
+wire             W_op_sync;
+wire             W_op_trap;
+wire             W_op_wrctl;
+wire             W_op_wrprs;
+wire             W_op_xor;
+wire             W_op_xorhi;
+wire             W_op_xori;
+reg     [ 28: 0] W_pcb /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire    [ 31: 0] W_status_reg;
+wire             W_status_reg_crs;
+reg              W_status_reg_pie;
+wire             W_status_reg_pie_inst_nxt;
+wire             W_status_reg_pie_nxt;
+wire             W_status_reg_pie_wr_en;
+wire             W_status_reg_prs;
+reg              W_up_ex_mon_state;
+reg              W_valid;
+reg              W_valid_from_M;
+wire    [ 71: 0] W_vinst;
+reg     [ 31: 0] W_wr_data;
+reg              W_wr_dst_reg;
+wire             av_addr_accepted;
+wire             av_rd_addr_accepted;
+wire             av_wr_data_transfer;
+reg              clr_break_line;
+wire    [ 28: 0] d_address;
+reg     [  1: 0] d_address_byte_field;
+wire    [  1: 0] d_address_byte_field_nxt;
+reg     [  5: 0] d_address_line_field;
+wire    [  5: 0] d_address_line_field_nxt;
+reg     [  2: 0] d_address_offset_field;
+wire    [  2: 0] d_address_offset_field_nxt;
+reg     [ 17: 0] d_address_tag_field;
+wire    [ 17: 0] d_address_tag_field_nxt;
+reg     [  3: 0] d_byteenable;
+wire    [  3: 0] d_byteenable_nxt;
+reg              d_read;
+wire             d_read_nxt;
+reg     [ 31: 0] d_readdata_d1;
+reg              d_readdatavalid_d1;
+reg              d_write;
+wire             d_write_nxt;
+reg     [ 31: 0] d_writedata;
+wire    [ 31: 0] d_writedata_nxt;
+wire    [  8: 0] dc_data_rd_port_addr;
+wire    [ 31: 0] dc_data_rd_port_data;
+wire    [  5: 0] dc_data_rd_port_line_field;
+wire    [  2: 0] dc_data_rd_port_offset_field;
+wire    [  8: 0] dc_data_wr_port_addr;
+wire    [  3: 0] dc_data_wr_port_byte_en;
+wire    [ 31: 0] dc_data_wr_port_data;
+wire             dc_data_wr_port_en;
+wire             dc_line_dirty_off;
+wire             dc_line_dirty_on;
+wire             dc_line_valid_off;
+wire             dc_line_valid_on;
+wire    [  5: 0] dc_tag_rd_port_addr;
+wire    [ 19: 0] dc_tag_rd_port_data;
+wire    [  5: 0] dc_tag_wr_port_addr;
+wire    [ 19: 0] dc_tag_wr_port_data;
+wire             dc_tag_wr_port_en;
+wire    [ 31: 0] dc_wb_rd_data;
+wire    [  2: 0] dc_wb_rd_port_addr;
+wire             dc_wb_rd_port_en;
+wire    [  2: 0] dc_wb_wr_port_addr;
+wire    [ 31: 0] dc_wb_wr_port_data;
+wire             dc_wb_wr_port_en;
+wire             debug_mem_slave_clk;
+wire             debug_mem_slave_debugaccess_to_roms;
+wire    [ 31: 0] debug_mem_slave_readdata;
+wire             debug_mem_slave_reset;
+wire             debug_mem_slave_waitrequest;
+wire             debug_reset_request;
+wire             dummy_ci_port;
+wire             hbreak_enabled;
+wire             hbreak_req;
+wire    [ 28: 0] i_address;
+reg              i_read;
+wire             i_read_nxt;
+reg     [ 31: 0] i_readdata_d1;
+reg              i_readdatavalid_d1;
+wire             ic_data_rden;
+wire             ic_data_wren;
+reg              ic_fill_active;
+wire             ic_fill_active_nxt;
+reg     [  3: 0] ic_fill_ap_cnt;
+wire    [  3: 0] ic_fill_ap_cnt_nxt;
+wire             ic_fill_ap_last_word;
+reg     [  2: 0] ic_fill_ap_offset;
+wire    [  2: 0] ic_fill_ap_offset_nxt;
+wire             ic_fill_done;
+wire             ic_fill_dp_last_word;
+reg     [  2: 0] ic_fill_dp_offset;
+wire             ic_fill_dp_offset_en;
+wire    [  2: 0] ic_fill_dp_offset_nxt;
+reg     [  2: 0] ic_fill_initial_offset;
+reg     [  5: 0] ic_fill_line;
+reg              ic_fill_prevent_refill;
+wire             ic_fill_prevent_refill_nxt;
+wire             ic_fill_req_accepted;
+reg     [ 17: 0] ic_fill_tag;
+wire    [  7: 0] ic_fill_valid_bit_new;
+reg     [  7: 0] ic_fill_valid_bits;
+wire             ic_fill_valid_bits_en;
+wire    [  7: 0] ic_fill_valid_bits_nxt;
+reg              ic_tag_clr_valid_bits;
+wire             ic_tag_clr_valid_bits_nxt;
+wire             ic_tag_rden;
+reg     [  5: 0] ic_tag_wraddress;
+wire    [  5: 0] ic_tag_wraddress_nxt;
+wire    [ 25: 0] ic_tag_wrdata;
+wire             ic_tag_wren;
+reg              latched_oci_tb_hbreak_req;
+wire             latched_oci_tb_hbreak_req_next;
+wire             norm_intr_req;
+wire             oci_async_hbreak_req;
+wire    [ 31: 0] oci_ienable;
+wire             oci_single_step_mode;
+wire             oci_tb_hbreak_req;
+wire    [  4: 0] rf_a_rd_port_addr;
+wire    [ 31: 0] rf_a_rd_port_data;
+wire    [  4: 0] rf_b_rd_port_addr;
+wire    [ 31: 0] rf_b_rd_port_data;
+wire    [  4: 0] rf_wr_port_addr;
+wire    [ 31: 0] rf_wr_port_data;
+wire             rf_wr_port_en;
+wire             test_has_ended;
+reg              wait_for_one_post_bret_inst;
+  //the_q_sys_cpu_cpu_test_bench, which is an e_instance
+  q_sys_cpu_cpu_test_bench the_q_sys_cpu_cpu_test_bench
+    (
+      .A_cmp_result                         (A_cmp_result),
+      .A_ctrl_ld_non_bypass                 (A_ctrl_ld_non_bypass),
+      .A_en                                 (A_en),
+      .A_exc_active_no_break_no_crst        (A_exc_active_no_break_no_crst),
+      .A_exc_allowed                        (A_exc_allowed),
+      .A_exc_any_active                     (A_exc_any_active),
+      .A_exc_hbreak_pri1                    (A_exc_hbreak_pri1),
+      .A_exc_highest_pri_exc_id             (A_exc_highest_pri_exc_id),
+      .A_exc_inst_fetch                     (A_exc_inst_fetch),
+      .A_exc_norm_intr_pri5                 (A_exc_norm_intr_pri5),
+      .A_st_data                            (A_st_data),
+      .A_valid                              (A_valid),
+      .A_wr_data_filtered                   (A_wr_data_filtered),
+      .A_wr_data_unfiltered                 (A_wr_data_unfiltered),
+      .A_wr_dst_reg                         (A_wr_dst_reg),
+      .E_add_br_to_taken_history_filtered   (E_add_br_to_taken_history_filtered),
+      .E_add_br_to_taken_history_unfiltered (E_add_br_to_taken_history_unfiltered),
+      .M_bht_ptr_filtered                   (M_bht_ptr_filtered),
+      .M_bht_ptr_unfiltered                 (M_bht_ptr_unfiltered),
+      .M_bht_wr_data_filtered               (M_bht_wr_data_filtered),
+      .M_bht_wr_data_unfiltered             (M_bht_wr_data_unfiltered),
+      .M_bht_wr_en_filtered                 (M_bht_wr_en_filtered),
+      .M_bht_wr_en_unfiltered               (M_bht_wr_en_unfiltered),
+      .M_mem_baddr                          (M_mem_baddr),
+      .M_target_pcb                         (M_target_pcb),
+      .M_valid                              (M_valid),
+      .W_badaddr_reg                        (W_badaddr_reg),
+      .W_bstatus_reg                        (W_bstatus_reg),
+      .W_cdsr_reg                           (W_cdsr_reg),
+      .W_cpuid_reg                          (W_cpuid_reg),
+      .W_dst_regnum                         (W_dst_regnum),
+      .W_estatus_reg                        (W_estatus_reg),
+      .W_exception_reg                      (W_exception_reg),
+      .W_ienable_reg                        (W_ienable_reg),
+      .W_ipending_reg                       (W_ipending_reg),
+      .W_iw                                 (W_iw),
+      .W_iw_op                              (W_iw_op),
+      .W_iw_opx                             (W_iw_opx),
+      .W_mem_baddr                          (W_mem_baddr),
+      .W_mem_byte_en                        (W_mem_byte_en),
+      .W_pcb                                (W_pcb),
+      .W_status_reg                         (W_status_reg),
+      .W_valid                              (W_valid),
+      .W_vinst                              (W_vinst),
+      .W_wr_dst_reg                         (W_wr_dst_reg),
+      .clk                                  (clk),
+      .d_address                            (d_address),
+      .d_byteenable                         (d_byteenable),
+      .d_read                               (d_read),
+      .d_readdatavalid                      (d_readdatavalid),
+      .d_write                              (d_write),
+      .i_address                            (i_address),
+      .i_read                               (i_read),
+      .i_readdatavalid                      (i_readdatavalid),
+      .reset_n                              (reset_n),
+      .test_has_ended                       (test_has_ended)
+    );
+
+  assign F_iw_a = F_iw[31 : 27];
+  assign F_iw_b = F_iw[26 : 22];
+  assign F_iw_c = F_iw[21 : 17];
+  assign F_iw_custom_n = F_iw[13 : 6];
+  assign F_iw_custom_readra = F_iw[16];
+  assign F_iw_custom_readrb = F_iw[15];
+  assign F_iw_custom_writerc = F_iw[14];
+  assign F_iw_opx = F_iw[16 : 11];
+  assign F_iw_op = F_iw[5 : 0];
+  assign F_iw_imm5 = F_iw[10 : 6];
+  assign F_iw_imm16 = F_iw[21 : 6];
+  assign F_iw_imm26 = F_iw[31 : 6];
+  assign F_iw_memsz = F_iw[4 : 3];
+  assign F_iw_control_regnum = F_iw[10 : 6];
+  assign F_mem8 = F_iw_memsz == 2'b00;
+  assign F_mem16 = F_iw_memsz == 2'b01;
+  assign F_mem32 = F_iw_memsz[1] == 1'b1;
+  assign D_iw_a = D_iw[31 : 27];
+  assign D_iw_b = D_iw[26 : 22];
+  assign D_iw_c = D_iw[21 : 17];
+  assign D_iw_custom_n = D_iw[13 : 6];
+  assign D_iw_custom_readra = D_iw[16];
+  assign D_iw_custom_readrb = D_iw[15];
+  assign D_iw_custom_writerc = D_iw[14];
+  assign D_iw_opx = D_iw[16 : 11];
+  assign D_iw_op = D_iw[5 : 0];
+  assign D_iw_imm5 = D_iw[10 : 6];
+  assign D_iw_imm16 = D_iw[21 : 6];
+  assign D_iw_imm26 = D_iw[31 : 6];
+  assign D_iw_memsz = D_iw[4 : 3];
+  assign D_iw_control_regnum = D_iw[10 : 6];
+  assign D_mem8 = D_iw_memsz == 2'b00;
+  assign D_mem16 = D_iw_memsz == 2'b01;
+  assign D_mem32 = D_iw_memsz[1] == 1'b1;
+  assign E_iw_a = E_iw[31 : 27];
+  assign E_iw_b = E_iw[26 : 22];
+  assign E_iw_c = E_iw[21 : 17];
+  assign E_iw_custom_n = E_iw[13 : 6];
+  assign E_iw_custom_readra = E_iw[16];
+  assign E_iw_custom_readrb = E_iw[15];
+  assign E_iw_custom_writerc = E_iw[14];
+  assign E_iw_opx = E_iw[16 : 11];
+  assign E_iw_op = E_iw[5 : 0];
+  assign E_iw_imm5 = E_iw[10 : 6];
+  assign E_iw_imm16 = E_iw[21 : 6];
+  assign E_iw_imm26 = E_iw[31 : 6];
+  assign E_iw_memsz = E_iw[4 : 3];
+  assign E_iw_control_regnum = E_iw[10 : 6];
+  assign E_mem8 = E_iw_memsz == 2'b00;
+  assign E_mem16 = E_iw_memsz == 2'b01;
+  assign E_mem32 = E_iw_memsz[1] == 1'b1;
+  assign M_iw_a = M_iw[31 : 27];
+  assign M_iw_b = M_iw[26 : 22];
+  assign M_iw_c = M_iw[21 : 17];
+  assign M_iw_custom_n = M_iw[13 : 6];
+  assign M_iw_custom_readra = M_iw[16];
+  assign M_iw_custom_readrb = M_iw[15];
+  assign M_iw_custom_writerc = M_iw[14];
+  assign M_iw_opx = M_iw[16 : 11];
+  assign M_iw_op = M_iw[5 : 0];
+  assign M_iw_imm5 = M_iw[10 : 6];
+  assign M_iw_imm16 = M_iw[21 : 6];
+  assign M_iw_imm26 = M_iw[31 : 6];
+  assign M_iw_memsz = M_iw[4 : 3];
+  assign M_iw_control_regnum = M_iw[10 : 6];
+  assign M_mem8 = M_iw_memsz == 2'b00;
+  assign M_mem16 = M_iw_memsz == 2'b01;
+  assign M_mem32 = M_iw_memsz[1] == 1'b1;
+  assign A_iw_a = A_iw[31 : 27];
+  assign A_iw_b = A_iw[26 : 22];
+  assign A_iw_c = A_iw[21 : 17];
+  assign A_iw_custom_n = A_iw[13 : 6];
+  assign A_iw_custom_readra = A_iw[16];
+  assign A_iw_custom_readrb = A_iw[15];
+  assign A_iw_custom_writerc = A_iw[14];
+  assign A_iw_opx = A_iw[16 : 11];
+  assign A_iw_op = A_iw[5 : 0];
+  assign A_iw_imm5 = A_iw[10 : 6];
+  assign A_iw_imm16 = A_iw[21 : 6];
+  assign A_iw_imm26 = A_iw[31 : 6];
+  assign A_iw_memsz = A_iw[4 : 3];
+  assign A_iw_control_regnum = A_iw[10 : 6];
+  assign A_mem8 = A_iw_memsz == 2'b00;
+  assign A_mem16 = A_iw_memsz == 2'b01;
+  assign A_mem32 = A_iw_memsz[1] == 1'b1;
+  assign W_iw_a = W_iw[31 : 27];
+  assign W_iw_b = W_iw[26 : 22];
+  assign W_iw_c = W_iw[21 : 17];
+  assign W_iw_custom_n = W_iw[13 : 6];
+  assign W_iw_custom_readra = W_iw[16];
+  assign W_iw_custom_readrb = W_iw[15];
+  assign W_iw_custom_writerc = W_iw[14];
+  assign W_iw_opx = W_iw[16 : 11];
+  assign W_iw_op = W_iw[5 : 0];
+  assign W_iw_imm5 = W_iw[10 : 6];
+  assign W_iw_imm16 = W_iw[21 : 6];
+  assign W_iw_imm26 = W_iw[31 : 6];
+  assign W_iw_memsz = W_iw[4 : 3];
+  assign W_iw_control_regnum = W_iw[10 : 6];
+  assign W_mem8 = W_iw_memsz == 2'b00;
+  assign W_mem16 = W_iw_memsz == 2'b01;
+  assign W_mem32 = W_iw_memsz[1] == 1'b1;
+  assign F_op_call = F_iw_op == 0;
+  assign F_op_jmpi = F_iw_op == 1;
+  assign F_op_op_rsv02 = F_iw_op == 2;
+  assign F_op_ldbu = F_iw_op == 3;
+  assign F_op_addi = F_iw_op == 4;
+  assign F_op_stb = F_iw_op == 5;
+  assign F_op_br = F_iw_op == 6;
+  assign F_op_ldb = F_iw_op == 7;
+  assign F_op_cmpgei = F_iw_op == 8;
+  assign F_op_op_rsv09 = F_iw_op == 9;
+  assign F_op_op_rsv10 = F_iw_op == 10;
+  assign F_op_ldhu = F_iw_op == 11;
+  assign F_op_andi = F_iw_op == 12;
+  assign F_op_sth = F_iw_op == 13;
+  assign F_op_bge = F_iw_op == 14;
+  assign F_op_ldh = F_iw_op == 15;
+  assign F_op_cmplti = F_iw_op == 16;
+  assign F_op_op_rsv17 = F_iw_op == 17;
+  assign F_op_op_rsv18 = F_iw_op == 18;
+  assign F_op_initda = F_iw_op == 19;
+  assign F_op_ori = F_iw_op == 20;
+  assign F_op_stw = F_iw_op == 21;
+  assign F_op_blt = F_iw_op == 22;
+  assign F_op_ldw = F_iw_op == 23;
+  assign F_op_cmpnei = F_iw_op == 24;
+  assign F_op_op_rsv25 = F_iw_op == 25;
+  assign F_op_op_rsv26 = F_iw_op == 26;
+  assign F_op_flushda = F_iw_op == 27;
+  assign F_op_xori = F_iw_op == 28;
+  assign F_op_stc = F_iw_op == 29;
+  assign F_op_bne = F_iw_op == 30;
+  assign F_op_ldl = F_iw_op == 31;
+  assign F_op_cmpeqi = F_iw_op == 32;
+  assign F_op_op_rsv33 = F_iw_op == 33;
+  assign F_op_op_rsv34 = F_iw_op == 34;
+  assign F_op_ldbuio = F_iw_op == 35;
+  assign F_op_muli = F_iw_op == 36;
+  assign F_op_stbio = F_iw_op == 37;
+  assign F_op_beq = F_iw_op == 38;
+  assign F_op_ldbio = F_iw_op == 39;
+  assign F_op_cmpgeui = F_iw_op == 40;
+  assign F_op_op_rsv41 = F_iw_op == 41;
+  assign F_op_op_rsv42 = F_iw_op == 42;
+  assign F_op_ldhuio = F_iw_op == 43;
+  assign F_op_andhi = F_iw_op == 44;
+  assign F_op_sthio = F_iw_op == 45;
+  assign F_op_bgeu = F_iw_op == 46;
+  assign F_op_ldhio = F_iw_op == 47;
+  assign F_op_cmpltui = F_iw_op == 48;
+  assign F_op_op_rsv49 = F_iw_op == 49;
+  assign F_op_custom = F_iw_op == 50;
+  assign F_op_initd = F_iw_op == 51;
+  assign F_op_orhi = F_iw_op == 52;
+  assign F_op_stwio = F_iw_op == 53;
+  assign F_op_bltu = F_iw_op == 54;
+  assign F_op_ldwio = F_iw_op == 55;
+  assign F_op_rdprs = F_iw_op == 56;
+  assign F_op_op_rsv57 = F_iw_op == 57;
+  assign F_op_flushd = F_iw_op == 59;
+  assign F_op_xorhi = F_iw_op == 60;
+  assign F_op_op_rsv61 = F_iw_op == 61;
+  assign F_op_op_rsv62 = F_iw_op == 62;
+  assign F_op_op_rsv63 = F_iw_op == 63;
+  assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
+  assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
+  assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
+  assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
+  assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
+  assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
+  assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
+  assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
+  assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
+  assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
+  assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
+  assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
+  assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
+  assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
+  assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
+  assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
+  assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
+  assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
+  assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
+  assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
+  assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
+  assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
+  assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
+  assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
+  assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
+  assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
+  assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
+  assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
+  assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
+  assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
+  assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
+  assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
+  assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
+  assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
+  assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
+  assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
+  assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
+  assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
+  assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
+  assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
+  assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
+  assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
+  assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
+  assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
+  assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
+  assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
+  assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
+  assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
+  assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
+  assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
+  assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
+  assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
+  assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
+  assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
+  assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
+  assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
+  assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
+  assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
+  assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
+  assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
+  assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
+  assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
+  assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
+  assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
+  assign F_is_opx_inst = F_iw_op == 58;
+  assign D_op_call = D_iw_op == 0;
+  assign D_op_jmpi = D_iw_op == 1;
+  assign D_op_op_rsv02 = D_iw_op == 2;
+  assign D_op_ldbu = D_iw_op == 3;
+  assign D_op_addi = D_iw_op == 4;
+  assign D_op_stb = D_iw_op == 5;
+  assign D_op_br = D_iw_op == 6;
+  assign D_op_ldb = D_iw_op == 7;
+  assign D_op_cmpgei = D_iw_op == 8;
+  assign D_op_op_rsv09 = D_iw_op == 9;
+  assign D_op_op_rsv10 = D_iw_op == 10;
+  assign D_op_ldhu = D_iw_op == 11;
+  assign D_op_andi = D_iw_op == 12;
+  assign D_op_sth = D_iw_op == 13;
+  assign D_op_bge = D_iw_op == 14;
+  assign D_op_ldh = D_iw_op == 15;
+  assign D_op_cmplti = D_iw_op == 16;
+  assign D_op_op_rsv17 = D_iw_op == 17;
+  assign D_op_op_rsv18 = D_iw_op == 18;
+  assign D_op_initda = D_iw_op == 19;
+  assign D_op_ori = D_iw_op == 20;
+  assign D_op_stw = D_iw_op == 21;
+  assign D_op_blt = D_iw_op == 22;
+  assign D_op_ldw = D_iw_op == 23;
+  assign D_op_cmpnei = D_iw_op == 24;
+  assign D_op_op_rsv25 = D_iw_op == 25;
+  assign D_op_op_rsv26 = D_iw_op == 26;
+  assign D_op_flushda = D_iw_op == 27;
+  assign D_op_xori = D_iw_op == 28;
+  assign D_op_stc = D_iw_op == 29;
+  assign D_op_bne = D_iw_op == 30;
+  assign D_op_ldl = D_iw_op == 31;
+  assign D_op_cmpeqi = D_iw_op == 32;
+  assign D_op_op_rsv33 = D_iw_op == 33;
+  assign D_op_op_rsv34 = D_iw_op == 34;
+  assign D_op_ldbuio = D_iw_op == 35;
+  assign D_op_muli = D_iw_op == 36;
+  assign D_op_stbio = D_iw_op == 37;
+  assign D_op_beq = D_iw_op == 38;
+  assign D_op_ldbio = D_iw_op == 39;
+  assign D_op_cmpgeui = D_iw_op == 40;
+  assign D_op_op_rsv41 = D_iw_op == 41;
+  assign D_op_op_rsv42 = D_iw_op == 42;
+  assign D_op_ldhuio = D_iw_op == 43;
+  assign D_op_andhi = D_iw_op == 44;
+  assign D_op_sthio = D_iw_op == 45;
+  assign D_op_bgeu = D_iw_op == 46;
+  assign D_op_ldhio = D_iw_op == 47;
+  assign D_op_cmpltui = D_iw_op == 48;
+  assign D_op_op_rsv49 = D_iw_op == 49;
+  assign D_op_custom = D_iw_op == 50;
+  assign D_op_initd = D_iw_op == 51;
+  assign D_op_orhi = D_iw_op == 52;
+  assign D_op_stwio = D_iw_op == 53;
+  assign D_op_bltu = D_iw_op == 54;
+  assign D_op_ldwio = D_iw_op == 55;
+  assign D_op_rdprs = D_iw_op == 56;
+  assign D_op_op_rsv57 = D_iw_op == 57;
+  assign D_op_flushd = D_iw_op == 59;
+  assign D_op_xorhi = D_iw_op == 60;
+  assign D_op_op_rsv61 = D_iw_op == 61;
+  assign D_op_op_rsv62 = D_iw_op == 62;
+  assign D_op_op_rsv63 = D_iw_op == 63;
+  assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
+  assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
+  assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
+  assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
+  assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
+  assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
+  assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
+  assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
+  assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
+  assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
+  assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
+  assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
+  assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
+  assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
+  assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
+  assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
+  assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
+  assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
+  assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
+  assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
+  assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
+  assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
+  assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
+  assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
+  assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
+  assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
+  assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
+  assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
+  assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
+  assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
+  assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
+  assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
+  assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
+  assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
+  assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
+  assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
+  assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
+  assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
+  assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
+  assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
+  assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
+  assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
+  assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
+  assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
+  assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
+  assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
+  assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
+  assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
+  assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
+  assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
+  assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
+  assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
+  assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
+  assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
+  assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
+  assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
+  assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
+  assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
+  assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
+  assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
+  assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
+  assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
+  assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
+  assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
+  assign D_is_opx_inst = D_iw_op == 58;
+  assign E_op_call = E_iw_op == 0;
+  assign E_op_jmpi = E_iw_op == 1;
+  assign E_op_op_rsv02 = E_iw_op == 2;
+  assign E_op_ldbu = E_iw_op == 3;
+  assign E_op_addi = E_iw_op == 4;
+  assign E_op_stb = E_iw_op == 5;
+  assign E_op_br = E_iw_op == 6;
+  assign E_op_ldb = E_iw_op == 7;
+  assign E_op_cmpgei = E_iw_op == 8;
+  assign E_op_op_rsv09 = E_iw_op == 9;
+  assign E_op_op_rsv10 = E_iw_op == 10;
+  assign E_op_ldhu = E_iw_op == 11;
+  assign E_op_andi = E_iw_op == 12;
+  assign E_op_sth = E_iw_op == 13;
+  assign E_op_bge = E_iw_op == 14;
+  assign E_op_ldh = E_iw_op == 15;
+  assign E_op_cmplti = E_iw_op == 16;
+  assign E_op_op_rsv17 = E_iw_op == 17;
+  assign E_op_op_rsv18 = E_iw_op == 18;
+  assign E_op_initda = E_iw_op == 19;
+  assign E_op_ori = E_iw_op == 20;
+  assign E_op_stw = E_iw_op == 21;
+  assign E_op_blt = E_iw_op == 22;
+  assign E_op_ldw = E_iw_op == 23;
+  assign E_op_cmpnei = E_iw_op == 24;
+  assign E_op_op_rsv25 = E_iw_op == 25;
+  assign E_op_op_rsv26 = E_iw_op == 26;
+  assign E_op_flushda = E_iw_op == 27;
+  assign E_op_xori = E_iw_op == 28;
+  assign E_op_stc = E_iw_op == 29;
+  assign E_op_bne = E_iw_op == 30;
+  assign E_op_ldl = E_iw_op == 31;
+  assign E_op_cmpeqi = E_iw_op == 32;
+  assign E_op_op_rsv33 = E_iw_op == 33;
+  assign E_op_op_rsv34 = E_iw_op == 34;
+  assign E_op_ldbuio = E_iw_op == 35;
+  assign E_op_muli = E_iw_op == 36;
+  assign E_op_stbio = E_iw_op == 37;
+  assign E_op_beq = E_iw_op == 38;
+  assign E_op_ldbio = E_iw_op == 39;
+  assign E_op_cmpgeui = E_iw_op == 40;
+  assign E_op_op_rsv41 = E_iw_op == 41;
+  assign E_op_op_rsv42 = E_iw_op == 42;
+  assign E_op_ldhuio = E_iw_op == 43;
+  assign E_op_andhi = E_iw_op == 44;
+  assign E_op_sthio = E_iw_op == 45;
+  assign E_op_bgeu = E_iw_op == 46;
+  assign E_op_ldhio = E_iw_op == 47;
+  assign E_op_cmpltui = E_iw_op == 48;
+  assign E_op_op_rsv49 = E_iw_op == 49;
+  assign E_op_custom = E_iw_op == 50;
+  assign E_op_initd = E_iw_op == 51;
+  assign E_op_orhi = E_iw_op == 52;
+  assign E_op_stwio = E_iw_op == 53;
+  assign E_op_bltu = E_iw_op == 54;
+  assign E_op_ldwio = E_iw_op == 55;
+  assign E_op_rdprs = E_iw_op == 56;
+  assign E_op_op_rsv57 = E_iw_op == 57;
+  assign E_op_flushd = E_iw_op == 59;
+  assign E_op_xorhi = E_iw_op == 60;
+  assign E_op_op_rsv61 = E_iw_op == 61;
+  assign E_op_op_rsv62 = E_iw_op == 62;
+  assign E_op_op_rsv63 = E_iw_op == 63;
+  assign E_op_opx_rsv00 = (E_iw_opx == 0) & E_is_opx_inst;
+  assign E_op_eret = (E_iw_opx == 1) & E_is_opx_inst;
+  assign E_op_roli = (E_iw_opx == 2) & E_is_opx_inst;
+  assign E_op_rol = (E_iw_opx == 3) & E_is_opx_inst;
+  assign E_op_flushp = (E_iw_opx == 4) & E_is_opx_inst;
+  assign E_op_ret = (E_iw_opx == 5) & E_is_opx_inst;
+  assign E_op_nor = (E_iw_opx == 6) & E_is_opx_inst;
+  assign E_op_mulxuu = (E_iw_opx == 7) & E_is_opx_inst;
+  assign E_op_cmpge = (E_iw_opx == 8) & E_is_opx_inst;
+  assign E_op_bret = (E_iw_opx == 9) & E_is_opx_inst;
+  assign E_op_opx_rsv10 = (E_iw_opx == 10) & E_is_opx_inst;
+  assign E_op_ror = (E_iw_opx == 11) & E_is_opx_inst;
+  assign E_op_flushi = (E_iw_opx == 12) & E_is_opx_inst;
+  assign E_op_jmp = (E_iw_opx == 13) & E_is_opx_inst;
+  assign E_op_and = (E_iw_opx == 14) & E_is_opx_inst;
+  assign E_op_opx_rsv15 = (E_iw_opx == 15) & E_is_opx_inst;
+  assign E_op_cmplt = (E_iw_opx == 16) & E_is_opx_inst;
+  assign E_op_opx_rsv17 = (E_iw_opx == 17) & E_is_opx_inst;
+  assign E_op_slli = (E_iw_opx == 18) & E_is_opx_inst;
+  assign E_op_sll = (E_iw_opx == 19) & E_is_opx_inst;
+  assign E_op_wrprs = (E_iw_opx == 20) & E_is_opx_inst;
+  assign E_op_opx_rsv21 = (E_iw_opx == 21) & E_is_opx_inst;
+  assign E_op_or = (E_iw_opx == 22) & E_is_opx_inst;
+  assign E_op_mulxsu = (E_iw_opx == 23) & E_is_opx_inst;
+  assign E_op_cmpne = (E_iw_opx == 24) & E_is_opx_inst;
+  assign E_op_opx_rsv25 = (E_iw_opx == 25) & E_is_opx_inst;
+  assign E_op_srli = (E_iw_opx == 26) & E_is_opx_inst;
+  assign E_op_srl = (E_iw_opx == 27) & E_is_opx_inst;
+  assign E_op_nextpc = (E_iw_opx == 28) & E_is_opx_inst;
+  assign E_op_callr = (E_iw_opx == 29) & E_is_opx_inst;
+  assign E_op_xor = (E_iw_opx == 30) & E_is_opx_inst;
+  assign E_op_mulxss = (E_iw_opx == 31) & E_is_opx_inst;
+  assign E_op_cmpeq = (E_iw_opx == 32) & E_is_opx_inst;
+  assign E_op_opx_rsv33 = (E_iw_opx == 33) & E_is_opx_inst;
+  assign E_op_opx_rsv34 = (E_iw_opx == 34) & E_is_opx_inst;
+  assign E_op_opx_rsv35 = (E_iw_opx == 35) & E_is_opx_inst;
+  assign E_op_divu = (E_iw_opx == 36) & E_is_opx_inst;
+  assign E_op_div = (E_iw_opx == 37) & E_is_opx_inst;
+  assign E_op_rdctl = (E_iw_opx == 38) & E_is_opx_inst;
+  assign E_op_mul = (E_iw_opx == 39) & E_is_opx_inst;
+  assign E_op_cmpgeu = (E_iw_opx == 40) & E_is_opx_inst;
+  assign E_op_initi = (E_iw_opx == 41) & E_is_opx_inst;
+  assign E_op_opx_rsv42 = (E_iw_opx == 42) & E_is_opx_inst;
+  assign E_op_opx_rsv43 = (E_iw_opx == 43) & E_is_opx_inst;
+  assign E_op_opx_rsv44 = (E_iw_opx == 44) & E_is_opx_inst;
+  assign E_op_trap = (E_iw_opx == 45) & E_is_opx_inst;
+  assign E_op_wrctl = (E_iw_opx == 46) & E_is_opx_inst;
+  assign E_op_opx_rsv47 = (E_iw_opx == 47) & E_is_opx_inst;
+  assign E_op_cmpltu = (E_iw_opx == 48) & E_is_opx_inst;
+  assign E_op_add = (E_iw_opx == 49) & E_is_opx_inst;
+  assign E_op_opx_rsv50 = (E_iw_opx == 50) & E_is_opx_inst;
+  assign E_op_opx_rsv51 = (E_iw_opx == 51) & E_is_opx_inst;
+  assign E_op_break = (E_iw_opx == 52) & E_is_opx_inst;
+  assign E_op_hbreak = (E_iw_opx == 53) & E_is_opx_inst;
+  assign E_op_sync = (E_iw_opx == 54) & E_is_opx_inst;
+  assign E_op_opx_rsv55 = (E_iw_opx == 55) & E_is_opx_inst;
+  assign E_op_opx_rsv56 = (E_iw_opx == 56) & E_is_opx_inst;
+  assign E_op_sub = (E_iw_opx == 57) & E_is_opx_inst;
+  assign E_op_srai = (E_iw_opx == 58) & E_is_opx_inst;
+  assign E_op_sra = (E_iw_opx == 59) & E_is_opx_inst;
+  assign E_op_opx_rsv60 = (E_iw_opx == 60) & E_is_opx_inst;
+  assign E_op_intr = (E_iw_opx == 61) & E_is_opx_inst;
+  assign E_op_crst = (E_iw_opx == 62) & E_is_opx_inst;
+  assign E_op_opx_rsv63 = (E_iw_opx == 63) & E_is_opx_inst;
+  assign E_is_opx_inst = E_iw_op == 58;
+  assign M_op_call = M_iw_op == 0;
+  assign M_op_jmpi = M_iw_op == 1;
+  assign M_op_op_rsv02 = M_iw_op == 2;
+  assign M_op_ldbu = M_iw_op == 3;
+  assign M_op_addi = M_iw_op == 4;
+  assign M_op_stb = M_iw_op == 5;
+  assign M_op_br = M_iw_op == 6;
+  assign M_op_ldb = M_iw_op == 7;
+  assign M_op_cmpgei = M_iw_op == 8;
+  assign M_op_op_rsv09 = M_iw_op == 9;
+  assign M_op_op_rsv10 = M_iw_op == 10;
+  assign M_op_ldhu = M_iw_op == 11;
+  assign M_op_andi = M_iw_op == 12;
+  assign M_op_sth = M_iw_op == 13;
+  assign M_op_bge = M_iw_op == 14;
+  assign M_op_ldh = M_iw_op == 15;
+  assign M_op_cmplti = M_iw_op == 16;
+  assign M_op_op_rsv17 = M_iw_op == 17;
+  assign M_op_op_rsv18 = M_iw_op == 18;
+  assign M_op_initda = M_iw_op == 19;
+  assign M_op_ori = M_iw_op == 20;
+  assign M_op_stw = M_iw_op == 21;
+  assign M_op_blt = M_iw_op == 22;
+  assign M_op_ldw = M_iw_op == 23;
+  assign M_op_cmpnei = M_iw_op == 24;
+  assign M_op_op_rsv25 = M_iw_op == 25;
+  assign M_op_op_rsv26 = M_iw_op == 26;
+  assign M_op_flushda = M_iw_op == 27;
+  assign M_op_xori = M_iw_op == 28;
+  assign M_op_stc = M_iw_op == 29;
+  assign M_op_bne = M_iw_op == 30;
+  assign M_op_ldl = M_iw_op == 31;
+  assign M_op_cmpeqi = M_iw_op == 32;
+  assign M_op_op_rsv33 = M_iw_op == 33;
+  assign M_op_op_rsv34 = M_iw_op == 34;
+  assign M_op_ldbuio = M_iw_op == 35;
+  assign M_op_muli = M_iw_op == 36;
+  assign M_op_stbio = M_iw_op == 37;
+  assign M_op_beq = M_iw_op == 38;
+  assign M_op_ldbio = M_iw_op == 39;
+  assign M_op_cmpgeui = M_iw_op == 40;
+  assign M_op_op_rsv41 = M_iw_op == 41;
+  assign M_op_op_rsv42 = M_iw_op == 42;
+  assign M_op_ldhuio = M_iw_op == 43;
+  assign M_op_andhi = M_iw_op == 44;
+  assign M_op_sthio = M_iw_op == 45;
+  assign M_op_bgeu = M_iw_op == 46;
+  assign M_op_ldhio = M_iw_op == 47;
+  assign M_op_cmpltui = M_iw_op == 48;
+  assign M_op_op_rsv49 = M_iw_op == 49;
+  assign M_op_custom = M_iw_op == 50;
+  assign M_op_initd = M_iw_op == 51;
+  assign M_op_orhi = M_iw_op == 52;
+  assign M_op_stwio = M_iw_op == 53;
+  assign M_op_bltu = M_iw_op == 54;
+  assign M_op_ldwio = M_iw_op == 55;
+  assign M_op_rdprs = M_iw_op == 56;
+  assign M_op_op_rsv57 = M_iw_op == 57;
+  assign M_op_flushd = M_iw_op == 59;
+  assign M_op_xorhi = M_iw_op == 60;
+  assign M_op_op_rsv61 = M_iw_op == 61;
+  assign M_op_op_rsv62 = M_iw_op == 62;
+  assign M_op_op_rsv63 = M_iw_op == 63;
+  assign M_op_opx_rsv00 = (M_iw_opx == 0) & M_is_opx_inst;
+  assign M_op_eret = (M_iw_opx == 1) & M_is_opx_inst;
+  assign M_op_roli = (M_iw_opx == 2) & M_is_opx_inst;
+  assign M_op_rol = (M_iw_opx == 3) & M_is_opx_inst;
+  assign M_op_flushp = (M_iw_opx == 4) & M_is_opx_inst;
+  assign M_op_ret = (M_iw_opx == 5) & M_is_opx_inst;
+  assign M_op_nor = (M_iw_opx == 6) & M_is_opx_inst;
+  assign M_op_mulxuu = (M_iw_opx == 7) & M_is_opx_inst;
+  assign M_op_cmpge = (M_iw_opx == 8) & M_is_opx_inst;
+  assign M_op_bret = (M_iw_opx == 9) & M_is_opx_inst;
+  assign M_op_opx_rsv10 = (M_iw_opx == 10) & M_is_opx_inst;
+  assign M_op_ror = (M_iw_opx == 11) & M_is_opx_inst;
+  assign M_op_flushi = (M_iw_opx == 12) & M_is_opx_inst;
+  assign M_op_jmp = (M_iw_opx == 13) & M_is_opx_inst;
+  assign M_op_and = (M_iw_opx == 14) & M_is_opx_inst;
+  assign M_op_opx_rsv15 = (M_iw_opx == 15) & M_is_opx_inst;
+  assign M_op_cmplt = (M_iw_opx == 16) & M_is_opx_inst;
+  assign M_op_opx_rsv17 = (M_iw_opx == 17) & M_is_opx_inst;
+  assign M_op_slli = (M_iw_opx == 18) & M_is_opx_inst;
+  assign M_op_sll = (M_iw_opx == 19) & M_is_opx_inst;
+  assign M_op_wrprs = (M_iw_opx == 20) & M_is_opx_inst;
+  assign M_op_opx_rsv21 = (M_iw_opx == 21) & M_is_opx_inst;
+  assign M_op_or = (M_iw_opx == 22) & M_is_opx_inst;
+  assign M_op_mulxsu = (M_iw_opx == 23) & M_is_opx_inst;
+  assign M_op_cmpne = (M_iw_opx == 24) & M_is_opx_inst;
+  assign M_op_opx_rsv25 = (M_iw_opx == 25) & M_is_opx_inst;
+  assign M_op_srli = (M_iw_opx == 26) & M_is_opx_inst;
+  assign M_op_srl = (M_iw_opx == 27) & M_is_opx_inst;
+  assign M_op_nextpc = (M_iw_opx == 28) & M_is_opx_inst;
+  assign M_op_callr = (M_iw_opx == 29) & M_is_opx_inst;
+  assign M_op_xor = (M_iw_opx == 30) & M_is_opx_inst;
+  assign M_op_mulxss = (M_iw_opx == 31) & M_is_opx_inst;
+  assign M_op_cmpeq = (M_iw_opx == 32) & M_is_opx_inst;
+  assign M_op_opx_rsv33 = (M_iw_opx == 33) & M_is_opx_inst;
+  assign M_op_opx_rsv34 = (M_iw_opx == 34) & M_is_opx_inst;
+  assign M_op_opx_rsv35 = (M_iw_opx == 35) & M_is_opx_inst;
+  assign M_op_divu = (M_iw_opx == 36) & M_is_opx_inst;
+  assign M_op_div = (M_iw_opx == 37) & M_is_opx_inst;
+  assign M_op_rdctl = (M_iw_opx == 38) & M_is_opx_inst;
+  assign M_op_mul = (M_iw_opx == 39) & M_is_opx_inst;
+  assign M_op_cmpgeu = (M_iw_opx == 40) & M_is_opx_inst;
+  assign M_op_initi = (M_iw_opx == 41) & M_is_opx_inst;
+  assign M_op_opx_rsv42 = (M_iw_opx == 42) & M_is_opx_inst;
+  assign M_op_opx_rsv43 = (M_iw_opx == 43) & M_is_opx_inst;
+  assign M_op_opx_rsv44 = (M_iw_opx == 44) & M_is_opx_inst;
+  assign M_op_trap = (M_iw_opx == 45) & M_is_opx_inst;
+  assign M_op_wrctl = (M_iw_opx == 46) & M_is_opx_inst;
+  assign M_op_opx_rsv47 = (M_iw_opx == 47) & M_is_opx_inst;
+  assign M_op_cmpltu = (M_iw_opx == 48) & M_is_opx_inst;
+  assign M_op_add = (M_iw_opx == 49) & M_is_opx_inst;
+  assign M_op_opx_rsv50 = (M_iw_opx == 50) & M_is_opx_inst;
+  assign M_op_opx_rsv51 = (M_iw_opx == 51) & M_is_opx_inst;
+  assign M_op_break = (M_iw_opx == 52) & M_is_opx_inst;
+  assign M_op_hbreak = (M_iw_opx == 53) & M_is_opx_inst;
+  assign M_op_sync = (M_iw_opx == 54) & M_is_opx_inst;
+  assign M_op_opx_rsv55 = (M_iw_opx == 55) & M_is_opx_inst;
+  assign M_op_opx_rsv56 = (M_iw_opx == 56) & M_is_opx_inst;
+  assign M_op_sub = (M_iw_opx == 57) & M_is_opx_inst;
+  assign M_op_srai = (M_iw_opx == 58) & M_is_opx_inst;
+  assign M_op_sra = (M_iw_opx == 59) & M_is_opx_inst;
+  assign M_op_opx_rsv60 = (M_iw_opx == 60) & M_is_opx_inst;
+  assign M_op_intr = (M_iw_opx == 61) & M_is_opx_inst;
+  assign M_op_crst = (M_iw_opx == 62) & M_is_opx_inst;
+  assign M_op_opx_rsv63 = (M_iw_opx == 63) & M_is_opx_inst;
+  assign M_is_opx_inst = M_iw_op == 58;
+  assign A_op_call = A_iw_op == 0;
+  assign A_op_jmpi = A_iw_op == 1;
+  assign A_op_op_rsv02 = A_iw_op == 2;
+  assign A_op_ldbu = A_iw_op == 3;
+  assign A_op_addi = A_iw_op == 4;
+  assign A_op_stb = A_iw_op == 5;
+  assign A_op_br = A_iw_op == 6;
+  assign A_op_ldb = A_iw_op == 7;
+  assign A_op_cmpgei = A_iw_op == 8;
+  assign A_op_op_rsv09 = A_iw_op == 9;
+  assign A_op_op_rsv10 = A_iw_op == 10;
+  assign A_op_ldhu = A_iw_op == 11;
+  assign A_op_andi = A_iw_op == 12;
+  assign A_op_sth = A_iw_op == 13;
+  assign A_op_bge = A_iw_op == 14;
+  assign A_op_ldh = A_iw_op == 15;
+  assign A_op_cmplti = A_iw_op == 16;
+  assign A_op_op_rsv17 = A_iw_op == 17;
+  assign A_op_op_rsv18 = A_iw_op == 18;
+  assign A_op_initda = A_iw_op == 19;
+  assign A_op_ori = A_iw_op == 20;
+  assign A_op_stw = A_iw_op == 21;
+  assign A_op_blt = A_iw_op == 22;
+  assign A_op_ldw = A_iw_op == 23;
+  assign A_op_cmpnei = A_iw_op == 24;
+  assign A_op_op_rsv25 = A_iw_op == 25;
+  assign A_op_op_rsv26 = A_iw_op == 26;
+  assign A_op_flushda = A_iw_op == 27;
+  assign A_op_xori = A_iw_op == 28;
+  assign A_op_stc = A_iw_op == 29;
+  assign A_op_bne = A_iw_op == 30;
+  assign A_op_ldl = A_iw_op == 31;
+  assign A_op_cmpeqi = A_iw_op == 32;
+  assign A_op_op_rsv33 = A_iw_op == 33;
+  assign A_op_op_rsv34 = A_iw_op == 34;
+  assign A_op_ldbuio = A_iw_op == 35;
+  assign A_op_muli = A_iw_op == 36;
+  assign A_op_stbio = A_iw_op == 37;
+  assign A_op_beq = A_iw_op == 38;
+  assign A_op_ldbio = A_iw_op == 39;
+  assign A_op_cmpgeui = A_iw_op == 40;
+  assign A_op_op_rsv41 = A_iw_op == 41;
+  assign A_op_op_rsv42 = A_iw_op == 42;
+  assign A_op_ldhuio = A_iw_op == 43;
+  assign A_op_andhi = A_iw_op == 44;
+  assign A_op_sthio = A_iw_op == 45;
+  assign A_op_bgeu = A_iw_op == 46;
+  assign A_op_ldhio = A_iw_op == 47;
+  assign A_op_cmpltui = A_iw_op == 48;
+  assign A_op_op_rsv49 = A_iw_op == 49;
+  assign A_op_custom = A_iw_op == 50;
+  assign A_op_initd = A_iw_op == 51;
+  assign A_op_orhi = A_iw_op == 52;
+  assign A_op_stwio = A_iw_op == 53;
+  assign A_op_bltu = A_iw_op == 54;
+  assign A_op_ldwio = A_iw_op == 55;
+  assign A_op_rdprs = A_iw_op == 56;
+  assign A_op_op_rsv57 = A_iw_op == 57;
+  assign A_op_flushd = A_iw_op == 59;
+  assign A_op_xorhi = A_iw_op == 60;
+  assign A_op_op_rsv61 = A_iw_op == 61;
+  assign A_op_op_rsv62 = A_iw_op == 62;
+  assign A_op_op_rsv63 = A_iw_op == 63;
+  assign A_op_opx_rsv00 = (A_iw_opx == 0) & A_is_opx_inst;
+  assign A_op_eret = (A_iw_opx == 1) & A_is_opx_inst;
+  assign A_op_roli = (A_iw_opx == 2) & A_is_opx_inst;
+  assign A_op_rol = (A_iw_opx == 3) & A_is_opx_inst;
+  assign A_op_flushp = (A_iw_opx == 4) & A_is_opx_inst;
+  assign A_op_ret = (A_iw_opx == 5) & A_is_opx_inst;
+  assign A_op_nor = (A_iw_opx == 6) & A_is_opx_inst;
+  assign A_op_mulxuu = (A_iw_opx == 7) & A_is_opx_inst;
+  assign A_op_cmpge = (A_iw_opx == 8) & A_is_opx_inst;
+  assign A_op_bret = (A_iw_opx == 9) & A_is_opx_inst;
+  assign A_op_opx_rsv10 = (A_iw_opx == 10) & A_is_opx_inst;
+  assign A_op_ror = (A_iw_opx == 11) & A_is_opx_inst;
+  assign A_op_flushi = (A_iw_opx == 12) & A_is_opx_inst;
+  assign A_op_jmp = (A_iw_opx == 13) & A_is_opx_inst;
+  assign A_op_and = (A_iw_opx == 14) & A_is_opx_inst;
+  assign A_op_opx_rsv15 = (A_iw_opx == 15) & A_is_opx_inst;
+  assign A_op_cmplt = (A_iw_opx == 16) & A_is_opx_inst;
+  assign A_op_opx_rsv17 = (A_iw_opx == 17) & A_is_opx_inst;
+  assign A_op_slli = (A_iw_opx == 18) & A_is_opx_inst;
+  assign A_op_sll = (A_iw_opx == 19) & A_is_opx_inst;
+  assign A_op_wrprs = (A_iw_opx == 20) & A_is_opx_inst;
+  assign A_op_opx_rsv21 = (A_iw_opx == 21) & A_is_opx_inst;
+  assign A_op_or = (A_iw_opx == 22) & A_is_opx_inst;
+  assign A_op_mulxsu = (A_iw_opx == 23) & A_is_opx_inst;
+  assign A_op_cmpne = (A_iw_opx == 24) & A_is_opx_inst;
+  assign A_op_opx_rsv25 = (A_iw_opx == 25) & A_is_opx_inst;
+  assign A_op_srli = (A_iw_opx == 26) & A_is_opx_inst;
+  assign A_op_srl = (A_iw_opx == 27) & A_is_opx_inst;
+  assign A_op_nextpc = (A_iw_opx == 28) & A_is_opx_inst;
+  assign A_op_callr = (A_iw_opx == 29) & A_is_opx_inst;
+  assign A_op_xor = (A_iw_opx == 30) & A_is_opx_inst;
+  assign A_op_mulxss = (A_iw_opx == 31) & A_is_opx_inst;
+  assign A_op_cmpeq = (A_iw_opx == 32) & A_is_opx_inst;
+  assign A_op_opx_rsv33 = (A_iw_opx == 33) & A_is_opx_inst;
+  assign A_op_opx_rsv34 = (A_iw_opx == 34) & A_is_opx_inst;
+  assign A_op_opx_rsv35 = (A_iw_opx == 35) & A_is_opx_inst;
+  assign A_op_divu = (A_iw_opx == 36) & A_is_opx_inst;
+  assign A_op_div = (A_iw_opx == 37) & A_is_opx_inst;
+  assign A_op_rdctl = (A_iw_opx == 38) & A_is_opx_inst;
+  assign A_op_mul = (A_iw_opx == 39) & A_is_opx_inst;
+  assign A_op_cmpgeu = (A_iw_opx == 40) & A_is_opx_inst;
+  assign A_op_initi = (A_iw_opx == 41) & A_is_opx_inst;
+  assign A_op_opx_rsv42 = (A_iw_opx == 42) & A_is_opx_inst;
+  assign A_op_opx_rsv43 = (A_iw_opx == 43) & A_is_opx_inst;
+  assign A_op_opx_rsv44 = (A_iw_opx == 44) & A_is_opx_inst;
+  assign A_op_trap = (A_iw_opx == 45) & A_is_opx_inst;
+  assign A_op_wrctl = (A_iw_opx == 46) & A_is_opx_inst;
+  assign A_op_opx_rsv47 = (A_iw_opx == 47) & A_is_opx_inst;
+  assign A_op_cmpltu = (A_iw_opx == 48) & A_is_opx_inst;
+  assign A_op_add = (A_iw_opx == 49) & A_is_opx_inst;
+  assign A_op_opx_rsv50 = (A_iw_opx == 50) & A_is_opx_inst;
+  assign A_op_opx_rsv51 = (A_iw_opx == 51) & A_is_opx_inst;
+  assign A_op_break = (A_iw_opx == 52) & A_is_opx_inst;
+  assign A_op_hbreak = (A_iw_opx == 53) & A_is_opx_inst;
+  assign A_op_sync = (A_iw_opx == 54) & A_is_opx_inst;
+  assign A_op_opx_rsv55 = (A_iw_opx == 55) & A_is_opx_inst;
+  assign A_op_opx_rsv56 = (A_iw_opx == 56) & A_is_opx_inst;
+  assign A_op_sub = (A_iw_opx == 57) & A_is_opx_inst;
+  assign A_op_srai = (A_iw_opx == 58) & A_is_opx_inst;
+  assign A_op_sra = (A_iw_opx == 59) & A_is_opx_inst;
+  assign A_op_opx_rsv60 = (A_iw_opx == 60) & A_is_opx_inst;
+  assign A_op_intr = (A_iw_opx == 61) & A_is_opx_inst;
+  assign A_op_crst = (A_iw_opx == 62) & A_is_opx_inst;
+  assign A_op_opx_rsv63 = (A_iw_opx == 63) & A_is_opx_inst;
+  assign A_is_opx_inst = A_iw_op == 58;
+  assign W_op_call = W_iw_op == 0;
+  assign W_op_jmpi = W_iw_op == 1;
+  assign W_op_op_rsv02 = W_iw_op == 2;
+  assign W_op_ldbu = W_iw_op == 3;
+  assign W_op_addi = W_iw_op == 4;
+  assign W_op_stb = W_iw_op == 5;
+  assign W_op_br = W_iw_op == 6;
+  assign W_op_ldb = W_iw_op == 7;
+  assign W_op_cmpgei = W_iw_op == 8;
+  assign W_op_op_rsv09 = W_iw_op == 9;
+  assign W_op_op_rsv10 = W_iw_op == 10;
+  assign W_op_ldhu = W_iw_op == 11;
+  assign W_op_andi = W_iw_op == 12;
+  assign W_op_sth = W_iw_op == 13;
+  assign W_op_bge = W_iw_op == 14;
+  assign W_op_ldh = W_iw_op == 15;
+  assign W_op_cmplti = W_iw_op == 16;
+  assign W_op_op_rsv17 = W_iw_op == 17;
+  assign W_op_op_rsv18 = W_iw_op == 18;
+  assign W_op_initda = W_iw_op == 19;
+  assign W_op_ori = W_iw_op == 20;
+  assign W_op_stw = W_iw_op == 21;
+  assign W_op_blt = W_iw_op == 22;
+  assign W_op_ldw = W_iw_op == 23;
+  assign W_op_cmpnei = W_iw_op == 24;
+  assign W_op_op_rsv25 = W_iw_op == 25;
+  assign W_op_op_rsv26 = W_iw_op == 26;
+  assign W_op_flushda = W_iw_op == 27;
+  assign W_op_xori = W_iw_op == 28;
+  assign W_op_stc = W_iw_op == 29;
+  assign W_op_bne = W_iw_op == 30;
+  assign W_op_ldl = W_iw_op == 31;
+  assign W_op_cmpeqi = W_iw_op == 32;
+  assign W_op_op_rsv33 = W_iw_op == 33;
+  assign W_op_op_rsv34 = W_iw_op == 34;
+  assign W_op_ldbuio = W_iw_op == 35;
+  assign W_op_muli = W_iw_op == 36;
+  assign W_op_stbio = W_iw_op == 37;
+  assign W_op_beq = W_iw_op == 38;
+  assign W_op_ldbio = W_iw_op == 39;
+  assign W_op_cmpgeui = W_iw_op == 40;
+  assign W_op_op_rsv41 = W_iw_op == 41;
+  assign W_op_op_rsv42 = W_iw_op == 42;
+  assign W_op_ldhuio = W_iw_op == 43;
+  assign W_op_andhi = W_iw_op == 44;
+  assign W_op_sthio = W_iw_op == 45;
+  assign W_op_bgeu = W_iw_op == 46;
+  assign W_op_ldhio = W_iw_op == 47;
+  assign W_op_cmpltui = W_iw_op == 48;
+  assign W_op_op_rsv49 = W_iw_op == 49;
+  assign W_op_custom = W_iw_op == 50;
+  assign W_op_initd = W_iw_op == 51;
+  assign W_op_orhi = W_iw_op == 52;
+  assign W_op_stwio = W_iw_op == 53;
+  assign W_op_bltu = W_iw_op == 54;
+  assign W_op_ldwio = W_iw_op == 55;
+  assign W_op_rdprs = W_iw_op == 56;
+  assign W_op_op_rsv57 = W_iw_op == 57;
+  assign W_op_flushd = W_iw_op == 59;
+  assign W_op_xorhi = W_iw_op == 60;
+  assign W_op_op_rsv61 = W_iw_op == 61;
+  assign W_op_op_rsv62 = W_iw_op == 62;
+  assign W_op_op_rsv63 = W_iw_op == 63;
+  assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
+  assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
+  assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
+  assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
+  assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
+  assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
+  assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
+  assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
+  assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
+  assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
+  assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
+  assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
+  assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
+  assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
+  assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
+  assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
+  assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
+  assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
+  assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
+  assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
+  assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
+  assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
+  assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
+  assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
+  assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
+  assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
+  assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
+  assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
+  assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
+  assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
+  assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
+  assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
+  assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
+  assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
+  assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
+  assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
+  assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
+  assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
+  assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
+  assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
+  assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
+  assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
+  assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
+  assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
+  assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
+  assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
+  assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
+  assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
+  assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
+  assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
+  assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
+  assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
+  assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
+  assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
+  assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
+  assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
+  assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
+  assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
+  assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
+  assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
+  assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
+  assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
+  assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
+  assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
+  assign W_is_opx_inst = W_iw_op == 58;
+  assign F_pc_nxt = (A_pipe_flush)? A_pipe_flush_waddr :
+    (M_pipe_flush)? M_pipe_flush_waddr :
+    (E_valid_jmp_indirect)? E_src1[28 : 2] :
+    (D_raw_refetch)? D_pc :
+    ((D_br_pred_taken & D_issue))? D_br_taken_waddr :
+    ((D_ctrl_jmp_direct & D_issue))? D_jmp_direct_target_waddr :
+    F_pc_plus_one;
+
+  assign F_stall = D_stall;
+  assign F_en = ~F_stall;
+  assign F_sel_itcm = ~F_sel_instruction_master;
+  assign F_iw_avail = ~W_exc_crst_active & (F_sel_itcm | F_ic_hit);
+  assign F_older_non_sequential = (((D_br_pred_taken & D_issue) |
+    (D_ctrl_uncond_cti_non_br & D_issue)) & ~D_iw_corrupt) |
+    (E_valid_jmp_indirect & ~E_iw_corrupt) |
+    M_pipe_flush;
+
+  assign F_kill = D_refetch | F_older_non_sequential;
+  assign F_issue = F_iw_valid & ~F_kill;
+  assign F_iw_valid = F_iw_avail;
+  assign F_br_taken_waddr_partial = F_pc_plus_one[9 : 0] + 
+    F_iw_imm16[11 : 2];
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_iw_valid <= 0;
+      else if (D_en)
+          D_iw_valid <= F_iw_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_issue <= 0;
+      else if (D_en)
+          D_issue <= F_issue;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_kill <= 0;
+      else if (D_en)
+          D_kill <= F_kill;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_br_taken_waddr_partial <= 0;
+      else if (D_en)
+          D_br_taken_waddr_partial <= F_br_taken_waddr_partial;
+    end
+
+
+  assign D_raw_refetch = ~D_iw_valid & ~D_kill;
+  assign D_refetch = D_raw_refetch & ~(M_pipe_flush | E_valid_jmp_indirect);
+  assign D_br_offset_sex = {{16 {D_iw_imm16[15]}}, D_iw_imm16[15 : 12]};
+  assign D_br_offset_remaining = D_br_offset_sex[16 : 0];
+  assign D_br_taken_waddr = { D_pc_plus_one[26 : 10] +
+    D_br_offset_remaining + 
+    D_br_taken_waddr_partial[10],
+    D_br_taken_waddr_partial[9 : 0]};
+
+  assign D_br_taken_baddr = {D_br_taken_waddr, 2'b00};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_br_taken_baddr <= 0;
+      else if (E_en)
+          E_br_taken_baddr <= D_br_taken_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_br_taken_baddr <= 0;
+      else if (M_en)
+          M_br_taken_baddr <= E_br_taken_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_br_taken_baddr <= 0;
+      else if (A_en)
+          A_br_taken_baddr <= M_br_taken_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_br_taken_baddr <= 0;
+      else 
+        W_br_taken_baddr <= A_br_taken_baddr;
+    end
+
+
+  assign F_pcb_nxt = {F_pc_nxt, 2'b00};
+  assign F_pcb = {F_pc, 2'b00};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          F_pc <= 0;
+      else if (F_en)
+          F_pc <= F_pc_nxt;
+    end
+
+
+  assign F_pc_plus_one = F_pc + 1;
+  assign F_ic_data_rd_addr_nxt = F_pc_nxt[8 : 0];
+  assign ic_data_wren = i_readdatavalid_d1;
+  assign ic_data_rden = F_en;
+//q_sys_cpu_cpu_ic_data, which is an nios_sdp_ram
+q_sys_cpu_cpu_ic_data_module q_sys_cpu_cpu_ic_data
+  (
+    .clock     (clk),
+    .data      (i_readdata_d1),
+    .q         (F_ic_iw),
+    .rdaddress (F_ic_data_rd_addr_nxt),
+    .rden      (ic_data_rden),
+    .wraddress ({ic_fill_line, ic_fill_dp_offset}),
+    .wren      (ic_data_wren)
+  );
+
+  assign F_ic_tag_rd_addr_nxt = F_pc_nxt[8 : 3];
+  assign ic_tag_clr_valid_bits_nxt = ((A_ctrl_invalidate_i & A_valid) | A_exc_crst_active) | D_ic_fill_starting | clr_break_line;
+  assign ic_fill_valid_bits_nxt = ic_tag_clr_valid_bits_nxt ? 0 :
+    D_ic_fill_starting_d1     ? ic_fill_valid_bit_new : 
+    (ic_fill_valid_bits | ic_fill_valid_bit_new);
+
+  assign ic_fill_valid_bits_en = ic_tag_clr_valid_bits_nxt | D_ic_fill_starting_d1 | 
+    i_readdatavalid_d1;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          clr_break_line <= 1;
+      else 
+        clr_break_line <= 0;
+    end
+
+
+  assign ic_tag_wraddress_nxt = (clr_break_line)? 1 :
+    (A_exc_crst_active)? 0 :
+    ((((A_ctrl_invalidate_i & A_valid) | A_exc_crst_active)))? (A_inst_result[10 : 5]) :
+    (D_ic_fill_starting)? D_pc_line_field :
+    ic_fill_line;
+
+  assign ic_tag_wren = ic_tag_clr_valid_bits | i_readdatavalid_d1;
+  assign ic_tag_wrdata = {ic_fill_valid_bits,ic_fill_tag};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_tag_clr_valid_bits <= 1;
+      else 
+        ic_tag_clr_valid_bits <= ic_tag_clr_valid_bits_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_valid_bits <= 0;
+      else if (ic_fill_valid_bits_en)
+          ic_fill_valid_bits <= ic_fill_valid_bits_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_tag_wraddress <= 0;
+      else 
+        ic_tag_wraddress <= ic_tag_wraddress_nxt;
+    end
+
+
+  assign ic_tag_rden = F_en;
+//q_sys_cpu_cpu_ic_tag, which is an nios_sdp_ram
+q_sys_cpu_cpu_ic_tag_module q_sys_cpu_cpu_ic_tag
+  (
+    .clock     (clk),
+    .data      (ic_tag_wrdata),
+    .q         (F_ic_tag_rd),
+    .rdaddress (F_ic_tag_rd_addr_nxt),
+    .rden      (ic_tag_rden),
+    .wraddress (ic_tag_wraddress),
+    .wren      (ic_tag_wren)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_ic_tag.lpm_file = "q_sys_cpu_cpu_ic_tag_ram.dat";
+`else
+defparam q_sys_cpu_cpu_ic_tag.lpm_file = "q_sys_cpu_cpu_ic_tag_ram.hex";
+`endif
+//synthesis translate_on
+  assign F_ic_tag_field = F_ic_tag_rd[17 : 0];
+  assign F_ic_valid_bits = F_ic_tag_rd[25 : 18];
+  assign F_ic_desired_tag = F_pc[26 : 9];
+  assign F_ic_valid = (F_pc[2 : 0] == 3'd0)? F_ic_valid_bits[0] :
+    (F_pc[2 : 0] == 3'd1)? F_ic_valid_bits[1] :
+    (F_pc[2 : 0] == 3'd2)? F_ic_valid_bits[2] :
+    (F_pc[2 : 0] == 3'd3)? F_ic_valid_bits[3] :
+    (F_pc[2 : 0] == 3'd4)? F_ic_valid_bits[4] :
+    (F_pc[2 : 0] == 3'd5)? F_ic_valid_bits[5] :
+    (F_pc[2 : 0] == 3'd6)? F_ic_valid_bits[6] :
+    F_ic_valid_bits[7];
+
+  assign F_ic_hit = F_ic_valid & (F_ic_desired_tag == F_ic_tag_field);
+  assign F_pc_tag_field = F_pc[26 : 9];
+  assign F_pc_line_field = F_pc[8 : 3];
+  assign D_pc_tag_field = D_pc[26 : 9];
+  assign D_pc_line_field = D_pc[8 : 3];
+  assign D_pc_offset_field = D_pc[2 : 0];
+  assign D_ic_want_fill_unfiltered = D_refetch;
+  assign ic_fill_prevent_refill_nxt = D_ic_fill_starting | (ic_fill_prevent_refill & ~(((A_ctrl_invalidate_i & A_valid) | A_exc_crst_active) ));
+  assign F_ic_fill_same_tag_line = (F_pc_tag_field == ic_fill_tag) & (F_pc_line_field == ic_fill_line);
+  assign D_ic_fill_ignore = ic_fill_prevent_refill & D_ic_fill_same_tag_line;
+  assign D_ic_fill_starting = ~ic_fill_active & D_ic_want_fill & ~D_ic_fill_ignore;
+  assign ic_fill_done = ic_fill_dp_last_word & i_readdatavalid_d1;
+  assign ic_fill_active_nxt = D_ic_fill_starting | (ic_fill_active & ~ic_fill_done);
+  assign ic_fill_dp_last_word = ic_fill_dp_offset_nxt == ic_fill_initial_offset;
+  assign ic_fill_dp_offset_en = D_ic_fill_starting_d1 | i_readdatavalid_d1;
+  assign ic_fill_dp_offset_nxt = D_ic_fill_starting_d1 ? 
+    ic_fill_initial_offset : 
+    (ic_fill_dp_offset + 1);
+
+  assign ic_fill_ap_offset_nxt = ic_fill_req_accepted ? (ic_fill_ap_offset + 1) :
+    D_ic_fill_starting ?  D_pc_offset_field : ic_fill_ap_offset;
+
+  assign ic_fill_ap_cnt_nxt = ic_fill_req_accepted ? (ic_fill_ap_cnt + 1) :
+    D_ic_fill_starting   ? 1 :
+    ic_fill_ap_cnt;
+
+  assign ic_fill_ap_last_word = ic_fill_ap_cnt[3];
+  assign ic_fill_req_accepted = i_read & ~i_waitrequest;
+  assign i_read_nxt = D_ic_fill_starting | 
+    (i_read & (i_waitrequest | (~ic_fill_ap_last_word & ic_fill_active)));
+
+  assign i_address = {ic_fill_tag, 
+    ic_fill_line[5 : 0],
+    ic_fill_ap_offset, 
+    2'b00};
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_ap_offset <= 0;
+      else 
+        ic_fill_ap_offset <= ic_fill_ap_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_ap_cnt <= 0;
+      else 
+        ic_fill_ap_cnt <= ic_fill_ap_cnt_nxt;
+    end
+
+
+  assign ic_fill_valid_bit_new = (ic_fill_dp_offset_nxt == 3'd0)? 8'b00000001 :
+    (ic_fill_dp_offset_nxt == 3'd1)? 8'b00000010 :
+    (ic_fill_dp_offset_nxt == 3'd2)? 8'b00000100 :
+    (ic_fill_dp_offset_nxt == 3'd3)? 8'b00001000 :
+    (ic_fill_dp_offset_nxt == 3'd4)? 8'b00010000 :
+    (ic_fill_dp_offset_nxt == 3'd5)? 8'b00100000 :
+    (ic_fill_dp_offset_nxt == 3'd6)? 8'b01000000 :
+    8'b10000000;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ic_fill_starting_d1 <= 0;
+      else 
+        D_ic_fill_starting_d1 <= D_ic_fill_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ic_fill_same_tag_line <= 0;
+      else if (D_en)
+          D_ic_fill_same_tag_line <= F_ic_fill_same_tag_line;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_active <= 0;
+      else 
+        ic_fill_active <= ic_fill_active_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_prevent_refill <= 0;
+      else 
+        ic_fill_prevent_refill <= ic_fill_prevent_refill_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_tag <= 0;
+      else if (D_ic_fill_starting)
+          ic_fill_tag <= D_pc_tag_field;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_line <= 0;
+      else if (D_ic_fill_starting)
+          ic_fill_line <= D_pc_line_field;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_initial_offset <= 0;
+      else if (D_ic_fill_starting)
+          ic_fill_initial_offset <= D_pc_offset_field;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          ic_fill_dp_offset <= 0;
+      else if (ic_fill_dp_offset_en)
+          ic_fill_dp_offset <= ic_fill_dp_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          i_read <= 0;
+      else 
+        i_read <= i_read_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          i_readdata_d1 <= 0;
+      else 
+        i_readdata_d1 <= i_readdata;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          i_readdatavalid_d1 <= 0;
+      else 
+        i_readdatavalid_d1 <= i_readdatavalid;
+    end
+
+
+  assign F_sel_instruction_master = 1'b1;
+  assign F_iw = F_ic_iw;
+  assign F_bht_ptr_nxt = F_pc_nxt[7 : 0] ^ 
+    M_br_cond_taken_history[7 : 0];
+
+//q_sys_cpu_cpu_bht, which is an nios_sdp_ram
+q_sys_cpu_cpu_bht_module q_sys_cpu_cpu_bht
+  (
+    .clock     (clk),
+    .data      (M_bht_wr_data_filtered),
+    .q         (F_bht_data),
+    .rdaddress (F_bht_ptr_nxt),
+    .rden      (F_en),
+    .wraddress (M_bht_ptr_filtered),
+    .wren      (M_bht_wr_en_filtered)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_bht.lpm_file = "q_sys_cpu_cpu_bht_ram.dat";
+`else
+defparam q_sys_cpu_cpu_bht.lpm_file = "q_sys_cpu_cpu_bht_ram.hex";
+`endif
+//synthesis translate_on
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_bht_data <= 0;
+      else if (D_en)
+          D_bht_data <= F_bht_data;
+    end
+
+
+  assign D_br_cond_pred_taken = (D_bht_data[1] == 0) |
+    D_ctrl_br_always_pred_taken;
+
+  assign D_br_pred_taken = D_ctrl_br & (D_ctrl_br_uncond | D_br_cond_pred_taken);
+  assign D_br_pred_not_taken = D_ctrl_br_cond & !D_br_cond_pred_taken;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          F_bht_ptr <= 0;
+      else if (F_en)
+          F_bht_ptr <= F_bht_ptr_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_bht_ptr <= 0;
+      else if (D_en)
+          D_bht_ptr <= F_bht_ptr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_bht_data <= 0;
+      else if (E_en)
+          E_bht_data <= D_bht_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_bht_ptr <= 0;
+      else if (E_en)
+          E_bht_ptr <= D_bht_ptr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_bht_data <= 0;
+      else if (M_en)
+          M_bht_data <= E_bht_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_bht_ptr_unfiltered <= 0;
+      else if (M_en)
+          M_bht_ptr_unfiltered <= E_bht_ptr;
+    end
+
+
+  assign E_br_cond_pred_taken = (E_bht_data[1] == 0) | 
+    E_ctrl_br_always_pred_taken;
+
+  assign E_br_actually_taken = E_br_result;
+  assign E_br_mispredict = E_ctrl_br_cond & E_valid & (E_br_cond_pred_taken != E_br_actually_taken);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_br_actually_taken <= 0;
+      else if (M_en)
+          M_br_actually_taken <= E_br_actually_taken;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_br_mispredict <= 0;
+      else if (M_en)
+          M_br_mispredict <= E_br_mispredict;
+    end
+
+
+  assign E_br_cond_taken_history = E_add_br_to_taken_history_filtered ? 
+    { M_br_cond_taken_history[6 : 0], 
+    E_br_actually_taken } :
+    M_br_cond_taken_history;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_br_cond_taken_history <= 0;
+      else if (M_en)
+          M_br_cond_taken_history <= E_br_cond_taken_history;
+    end
+
+
+  assign M_bht_wr_data_unfiltered = ({M_bht_data, M_br_mispredict} == {2'd0, 1'b0})? 2'd1 :
+    ({M_bht_data, M_br_mispredict} == {2'd0, 1'b1})? 2'd2 :
+    ({M_bht_data, M_br_mispredict} == {2'd1, 1'b0})? 2'd1 :
+    ({M_bht_data, M_br_mispredict} == {2'd1, 1'b1})? 2'd0 :
+    ({M_bht_data, M_br_mispredict} == {2'd2, 1'b0})? 2'd3 :
+    ({M_bht_data, M_br_mispredict} == {2'd2, 1'b1})? 2'd0 :
+    ({M_bht_data, M_br_mispredict} == {2'd3, 1'b0})? 2'd3 :
+    2'd2;
+
+  assign M_bht_wr_en_unfiltered = M_ctrl_br_cond & ~M_ctrl_br_always_pred_taken & M_valid_from_E;
+  assign E_add_br_to_taken_history_unfiltered = E_ctrl_br_cond & E_valid;
+  assign D_pcb = {D_pc, 2'b00};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_pcb <= 0;
+      else if (E_en)
+          E_pcb <= D_pcb;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_pcb <= 0;
+      else if (M_en)
+          M_pcb <= E_pcb;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_pcb <= 0;
+      else if (A_en)
+          A_pcb <= M_pcb;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_pcb <= 0;
+      else 
+        W_pcb <= A_pcb;
+    end
+
+
+  assign D_stall = (D_dep_stall | D_rdprs_stall | E_stall) & ~M_pipe_flush;
+  assign D_en = ~D_stall;
+  assign D_dep_stall = D_data_depend & D_issue;
+  assign D_valid = D_issue & ~D_data_depend & ~D_rdprs_stall & ~M_pipe_flush;
+  assign D_issue_rdprs = 0;
+  assign D_rdprs_stall_unfiltered = D_issue_rdprs & ~D_rdprs_stall_done;
+  assign D_rdprs_stall_done_nxt = M_pipe_flush        ? 0 :
+    D_rdprs_stall_done  ? E_stall :
+    D_issue_rdprs;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_iw <= 0;
+      else if (D_en)
+          D_iw <= F_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_pc <= 0;
+      else if (D_en)
+          D_pc <= F_pc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_pc_plus_one <= 0;
+      else if (D_en)
+          D_pc_plus_one <= F_pc_plus_one;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_rdprs_stall_done <= 0;
+      else 
+        D_rdprs_stall_done <= D_rdprs_stall_done_nxt;
+    end
+
+
+  assign D_jmp_direct_target_waddr = {D_pc[26], D_iw[31 : 6]};
+  assign D_jmp_direct_target_baddr = {D_jmp_direct_target_waddr, 2'b00};
+  assign D_extra_pc = D_br_pred_not_taken ? D_br_taken_waddr : 
+    D_pc_plus_one;
+
+  assign D_extra_pcb = {D_extra_pc, 2'b00};
+  assign D_iw_corrupt = 0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_iw_corrupt <= 0;
+      else if (E_en)
+          E_iw_corrupt <= D_iw_corrupt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_iw_corrupt <= 0;
+      else if (M_en)
+          M_iw_corrupt <= E_iw_corrupt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_iw_corrupt <= 0;
+      else if (A_en)
+          A_iw_corrupt <= M_iw_corrupt;
+    end
+
+
+  assign E_stall = M_stall;
+  assign E_en = ~E_stall;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_valid_from_D <= 0;
+      else if (E_en)
+          E_valid_from_D <= D_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_iw <= 0;
+      else if (E_en)
+          E_iw <= D_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_dst_regnum <= 0;
+      else if (E_en)
+          E_dst_regnum <= D_dst_regnum;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_wr_dst_reg_from_D <= 0;
+      else if (E_en)
+          E_wr_dst_reg_from_D <= D_wr_dst_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_extra_pc <= 0;
+      else if (E_en)
+          E_extra_pc <= D_extra_pc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_pc <= 0;
+      else if (E_en)
+          E_pc <= D_pc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_valid_jmp_indirect <= 0;
+      else if (E_en)
+          E_valid_jmp_indirect <= D_ctrl_jmp_indirect & D_valid;
+    end
+
+
+  assign E_extra_pcb = {E_extra_pc, 2'b00};
+  assign E_valid = E_valid_from_D & ~E_cancel;
+  assign E_wr_dst_reg = E_wr_dst_reg_from_D & ~E_cancel;
+  assign E_cancel = M_pipe_flush;
+  assign M_pipe_flush_nxt = E_br_mispredict | A_pipe_flush_nxt;
+  assign M_pipe_flush_waddr_nxt = E_extra_pc;
+  assign M_pipe_flush_baddr_nxt = {M_pipe_flush_waddr_nxt, 2'b00};
+  assign E_sel_data_master = 1'b1;
+  assign E_sel_dtcm = ~E_sel_data_master;
+  assign E_dtcm_ld = E_ctrl_ld & E_sel_dtcm;
+  assign E_dtcm_st = E_ctrl_st & E_sel_dtcm & E_st_writes_mem;
+  assign E_dtcm_ld_st = E_ctrl_ld_st & E_sel_dtcm & E_st_writes_mem;
+  assign M_stall = A_stall;
+  assign M_en = ~M_stall;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_valid_from_E <= 0;
+      else if (M_en)
+          M_valid_from_E <= E_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_iw <= 0;
+      else if (M_en)
+          M_iw <= E_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_mem_byte_en <= 0;
+      else if (M_en)
+          M_mem_byte_en <= E_mem_byte_en;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_alu_result <= 0;
+      else if (M_en)
+          M_alu_result <= E_alu_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_st_data <= 0;
+      else if (M_en)
+          M_st_data <= E_st_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_dst_regnum <= 0;
+      else if (M_en)
+          M_dst_regnum <= E_dst_regnum;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_cmp_result <= 0;
+      else if (M_en)
+          M_cmp_result <= E_cmp_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_wr_dst_reg_from_E <= 0;
+      else if (M_en)
+          M_wr_dst_reg_from_E <= E_wr_dst_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_target_pcb <= 0;
+      else if (M_en)
+          M_target_pcb <= E_src1[28 : 0];
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_pipe_flush <= 1'b1;
+      else if (M_en)
+          M_pipe_flush <= M_pipe_flush_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_pipe_flush_waddr <= 83886080;
+      else if (M_en)
+          M_pipe_flush_waddr <= M_pipe_flush_waddr_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_sel_data_master <= 0;
+      else if (M_en)
+          M_sel_data_master <= E_sel_data_master;
+    end
+
+
+  assign M_sel_dtcm = ~M_sel_data_master;
+  assign M_dtcm_ld = M_ctrl_ld & M_sel_dtcm;
+  assign M_dtcm_st = M_ctrl_st & M_sel_dtcm & M_st_writes_mem;
+  assign M_dtcm_st_non32 = M_ctrl_st_non32 & M_sel_dtcm & M_st_writes_mem;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_pc <= 0;
+      else if (M_en)
+          M_pc <= E_pc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_pc_plus_one <= 0;
+      else if (M_en)
+          M_pc_plus_one <= E_pc + 1;
+    end
+
+
+  assign M_pipe_flush_baddr = {M_pipe_flush_waddr, 2'b00};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_mem_baddr <= 0;
+      else if (M_en)
+          M_mem_baddr <= E_mem_baddr;
+    end
+
+
+  assign M_mem_waddr = M_mem_baddr[28 : 2];
+  assign M_mem_waddr_phy = M_mem_baddr[28 : 2];
+  assign M_ram_rd_data = M_dc_rd_data;
+  assign M_fwd_reg_data = M_alu_result;
+  assign M_rdctl_data_latest = M_rdctl_data;
+  assign M_rdctl_data_inst_result = M_ctrl_intr_inst ? W_status_reg : M_rdctl_data_latest;
+  assign M_inst_result = (M_exc_any)? { M_pc_plus_one, 2'b00 } :
+    (M_ctrl_rd_ctl_reg)? M_rdctl_data_inst_result :
+    (M_ctrl_ld)? M_ram_rd_data :
+    M_alu_result;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_up_ex_mon_state <= 0;
+      else if (W_en)
+          W_up_ex_mon_state <= (A_ctrl_ld_ex & A_valid) ? 1'b1 :
+                    (((A_ctrl_st_ex & (~A_dc_want_fill | A_dc_fill_done)) | A_op_eret) & A_valid)? 1'b0 : 
+                    W_up_ex_mon_state;
+
+    end
+
+
+  assign E_up_ex_mon_state_latest = (M_ctrl_ld_st_ex & M_valid) ? M_ctrl_ld_ex :
+    (A_ctrl_ld_st_ex & A_valid) ? A_ctrl_ld_ex :
+    W_up_ex_mon_state;
+
+  assign E_st_writes_mem = ~E_ctrl_st_ex | E_up_ex_mon_state_latest;
+  assign M_up_ex_mon_state_latest = (A_ctrl_ld_st_ex & A_valid) ? A_ctrl_ld_ex :
+    W_up_ex_mon_state;
+
+  assign M_st_writes_mem = ~M_ctrl_st_ex | M_up_ex_mon_state_latest;
+  assign A_up_ex_mon_state_latest = W_up_ex_mon_state;
+  assign A_st_writes_mem = ~A_ctrl_st_ex | A_up_ex_mon_state_latest;
+  assign M_ld_align_sh16 = (M_ctrl_ld8 | M_ctrl_ld16) & M_mem_baddr[1] &
+    ~M_exc_any;
+
+  assign M_ld_align_sh8 = M_ctrl_ld8 & M_mem_baddr[0] &
+    ~M_exc_any;
+
+  assign M_ld_align_byte1_fill = M_ctrl_ld8 & ~M_exc_any;
+  assign M_ld_align_byte2_byte3_fill = M_ctrl_ld8_ld16 & ~M_exc_any;
+  assign M_exc_crst = 0;
+  assign M_exc_ext_intr = 0;
+  assign M_exc_break = A_exc_hbreak_pri1_nxt | A_exc_break_inst_pri15_nxt;
+  assign M_ignore_exc = A_pipe_flush | A_refetch_required | (M_udtlb_refetch & ~M_exc_higher_priority_than_tlb_data);
+  assign M_exc_allowed = M_valid_from_E & ~M_ignore_exc;
+  assign M_exc_higher_priority_than_tlb_data = 0;
+  assign M_udtlb_refetch = 0;
+  assign M_refetch = M_dc_raw_hazard;
+  assign M_non_flushing_wrctl = 0;
+  assign A_pipe_flush_nxt = (((M_ctrl_flush_pipe_always & ~M_non_flushing_wrctl) | M_refetch | M_exc_any) & 
+    M_valid_from_E & ~A_pipe_flush) | A_refetch_required;
+
+  assign A_pipe_flush_waddr_nxt = (A_refetch_required)? A_pc :
+    (M_exc_break)? 101714440 :
+    (M_exc_any)? 33554504 :
+    (M_refetch)? M_pc :
+    (M_ctrl_jmp_indirect)? M_target_pcb[28 : 2] :
+    M_pc_plus_one;
+
+  assign A_pipe_flush_baddr_nxt = {A_pipe_flush_waddr_nxt, 2'b00};
+  assign A_stall = A_mem_stall;
+  assign A_en = ~A_stall;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_pc <= 0;
+      else if (A_en)
+          A_pc <= M_pc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_valid_from_M <= 0;
+      else if (A_en)
+          A_valid_from_M <= M_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_iw <= 0;
+      else if (A_en)
+          A_iw <= M_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_inst_result <= 0;
+      else if (A_en)
+          A_inst_result <= M_inst_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mem_byte_en <= 0;
+      else if (A_en)
+          A_mem_byte_en <= M_mem_byte_en;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_st_data <= 0;
+      else if (A_en)
+          A_st_data <= M_st_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dst_regnum_from_M <= 0;
+      else if (A_en)
+          A_dst_regnum_from_M <= M_dst_regnum;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_align_sh16 <= 0;
+      else if (A_en)
+          A_ld_align_sh16 <= M_ld_align_sh16;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_align_sh8 <= 0;
+      else if (A_en)
+          A_ld_align_sh8 <= M_ld_align_sh8;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_align_byte1_fill <= 0;
+      else if (A_en)
+          A_ld_align_byte1_fill <= M_ld_align_byte1_fill;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_align_byte2_byte3_fill <= 0;
+      else if (A_en)
+          A_ld_align_byte2_byte3_fill <= M_ld_align_byte2_byte3_fill;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_cmp_result <= 0;
+      else if (A_en)
+          A_cmp_result <= M_cmp_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mem_baddr <= 0;
+      else if (A_en)
+          A_mem_baddr <= M_mem_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_wr_dst_reg_from_M <= 1'b1;
+      else if (A_en)
+          A_wr_dst_reg_from_M <= M_wr_dst_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_en_d1 <= 0;
+      else 
+        A_en_d1 <= A_en;
+    end
+
+
+  assign A_mem_waddr = A_mem_baddr[28 : 2];
+  assign A_mem_waddr_phy = A_mem_baddr[28 : 2];
+  assign A_br_jmp_target_pcb_nxt = M_ctrl_br ? 
+    ({M_pc_plus_one, 2'b00} + {{16 {M_iw_imm16[15]}}, M_iw_imm16}) :
+    M_target_pcb;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_sel_data_master <= 0;
+      else if (A_en)
+          A_sel_data_master <= M_sel_data_master;
+    end
+
+
+  assign A_sel_dtcm = ~A_sel_data_master;
+  assign A_dtcm_ld = A_ctrl_ld & A_sel_dtcm;
+  assign A_dtcm_st = A_ctrl_st & A_sel_dtcm & A_st_writes_mem;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_pipe_flush <= 0;
+      else if (A_en | A_refetch_required)
+          A_pipe_flush <= A_pipe_flush_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_pipe_flush_waddr <= 0;
+      else if (A_en | A_refetch_required)
+          A_pipe_flush_waddr <= A_pipe_flush_waddr_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_break <= 0;
+      else if (A_en)
+          A_exc_break <= M_exc_break;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_crst <= 0;
+      else if (A_en)
+          A_exc_crst <= M_exc_crst;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_ext_intr <= 0;
+      else if (A_en)
+          A_exc_ext_intr <= M_exc_ext_intr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_any <= 0;
+      else if (A_en)
+          A_exc_any <= M_exc_any;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_br_jmp_target_pcb <= 0;
+      else if (A_en)
+          A_br_jmp_target_pcb <= A_br_jmp_target_pcb_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_allowed <= 0;
+      else if (A_en)
+          A_exc_allowed <= M_exc_allowed;
+    end
+
+
+  assign A_pipe_flush_baddr = {A_pipe_flush_waddr, 2'b00};
+  assign A_slow_inst_result_en = (A_dc_fill_miss_offset_is_next | A_ctrl_ld_bypass) &
+    d_readdatavalid_d1;
+
+  assign A_slow_inst_result_nxt = A_slow_ld_data_aligned_nxt;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_slow_inst_result <= 0;
+      else if (A_slow_inst_result_en)
+          A_slow_inst_result <= A_slow_inst_result_nxt;
+    end
+
+
+  assign A_slow_inst_sel_nxt = A_en ? 0 : A_ctrl_ld_bypass|A_dc_want_fill;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_slow_inst_sel <= 0;
+      else 
+        A_slow_inst_sel <= A_slow_inst_sel_nxt;
+    end
+
+
+  assign A_exc_addr = A_inst_result;
+  assign A_shift_rot_bmx_result = A_shift_rot_result;
+  assign A_wr_data_unfiltered = (A_exc_any)? A_inst_result_aligned :
+    (A_ctrl_mul_lsw)? A_mul_result :
+    (A_ctrl_shift_rot)? A_shift_rot_bmx_result :
+    ((~A_slow_inst_sel | A_ctrl_st_ex))? A_inst_result_aligned :
+    A_slow_inst_result;
+
+  assign A_ld_data = ((~A_slow_inst_sel | A_ctrl_st_ex))? A_inst_result_aligned :
+    A_slow_inst_result;
+
+  assign A_fwd_reg_data = A_wr_data_filtered;
+  assign A_exc_any_active = A_exc_any & A_exc_allowed;
+  assign A_exc_break_active = A_exc_break & A_exc_allowed;
+  assign A_exc_crst_active = A_exc_crst & A_exc_allowed;
+  assign A_exc_ext_intr_active = A_exc_ext_intr & A_exc_allowed;
+  assign A_exc_shadow = 0;
+  assign A_exc_shadow_active = A_exc_shadow & A_exc_allowed;
+  assign A_exc_active_no_break = A_exc_any_active & ~A_exc_break;
+  assign A_exc_active_no_crst = A_exc_any_active & ~A_exc_crst;
+  assign A_exc_active_no_break_no_crst = A_exc_any_active & ~(A_exc_break | A_exc_crst);
+  assign A_exc_wr_ea_ba = A_exc_active_no_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_wr_sstatus <= 0;
+      else if (W_en)
+          W_exc_wr_sstatus <= A_exc_wr_sstatus;
+    end
+
+
+  assign A_refetch_required = 0;
+  assign A_cancel = A_refetch_required;
+  assign A_valid = A_valid_from_M & ~A_cancel;
+  assign W_en = 1'b1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_wr_data <= 0;
+      else 
+        W_wr_data <= A_wr_data_filtered;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_iw <= 0;
+      else 
+        W_iw <= A_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid <= 0;
+      else 
+        W_valid <= A_valid & A_en;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid_from_M <= 0;
+      else 
+        W_valid_from_M <= A_valid_from_M & A_en;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_wr_dst_reg <= 0;
+      else 
+        W_wr_dst_reg <= (A_wr_dst_reg & A_en) | A_exc_wr_ea_ba;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_dst_regnum <= 0;
+      else 
+        W_dst_regnum <= A_dst_regnum;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_mem_baddr <= 0;
+      else 
+        W_mem_baddr <= A_mem_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_mem_byte_en <= 0;
+      else 
+        W_mem_byte_en <= A_mem_byte_en;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_debug_mode <= 0;
+      else 
+        W_debug_mode <= W_debug_mode_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_crst_active <= 0;
+      else 
+        W_exc_crst_active <= A_exc_crst_active;
+    end
+
+
+  assign W_exc_handler_mode = 0;
+  assign W_mem_waddr_phy = W_mem_baddr[28 : 2];
+  assign F_iw_a_rf = D_en ? F_iw_a : D_iw_a;
+  assign F_iw_b_rf = D_en ? F_iw_b : D_iw_b;
+  assign F_rf_rd_addr_a = F_iw_a_rf;
+  assign F_rf_rd_addr_b = F_iw_b_rf;
+  assign E_src1_corrupt = 0;
+  assign E_src2_corrupt = 0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_src1_corrupt <= 0;
+      else if (M_en)
+          M_src1_corrupt <= E_src1_corrupt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_src2_corrupt <= 0;
+      else if (M_en)
+          M_src2_corrupt <= E_src2_corrupt;
+    end
+
+
+  assign rf_wr_port_addr = A_dst_regnum;
+  assign rf_a_rd_port_addr = F_rf_rd_addr_a;
+  assign rf_b_rd_port_addr = F_rf_rd_addr_b;
+  assign rf_wr_port_data = A_wr_data_filtered;
+  assign rf_wr_port_en = A_wr_dst_reg;
+  assign D_rf_a = rf_a_rd_port_data;
+  assign D_rf_b = rf_b_rd_port_data;
+//q_sys_cpu_cpu_register_bank_a, which is an nios_sdp_ram
+q_sys_cpu_cpu_register_bank_a_module q_sys_cpu_cpu_register_bank_a
+  (
+    .clock     (clk),
+    .data      (rf_wr_port_data),
+    .q         (rf_a_rd_port_data),
+    .rdaddress (rf_a_rd_port_addr),
+    .wraddress (rf_wr_port_addr),
+    .wren      (rf_wr_port_en)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_register_bank_a.lpm_file = "q_sys_cpu_cpu_rf_ram_a.dat";
+`else
+defparam q_sys_cpu_cpu_register_bank_a.lpm_file = "q_sys_cpu_cpu_rf_ram_a.hex";
+`endif
+//synthesis translate_on
+//q_sys_cpu_cpu_register_bank_b, which is an nios_sdp_ram
+q_sys_cpu_cpu_register_bank_b_module q_sys_cpu_cpu_register_bank_b
+  (
+    .clock     (clk),
+    .data      (rf_wr_port_data),
+    .q         (rf_b_rd_port_data),
+    .rdaddress (rf_b_rd_port_addr),
+    .wraddress (rf_wr_port_addr),
+    .wren      (rf_wr_port_en)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_register_bank_b.lpm_file = "q_sys_cpu_cpu_rf_ram_b.dat";
+`else
+defparam q_sys_cpu_cpu_register_bank_b.lpm_file = "q_sys_cpu_cpu_rf_ram_b.hex";
+`endif
+//synthesis translate_on
+  assign E_arith_src1 = { E_src1[31] ^ E_ctrl_alu_signed_comparison, 
+    E_src1[30 : 0]};
+
+  assign E_arith_src2 = { E_src2[31] ^ E_ctrl_alu_signed_comparison, 
+    E_src2[30 : 0]};
+
+  assign E_arith_result = E_ctrl_alu_subtract ?
+    E_arith_src1 - E_arith_src2 :
+    E_arith_src1 + E_arith_src2;
+
+  assign E_mem_baddr_corrupt = E_src1_corrupt;
+  assign E_mem_baddr = E_arith_result[28 : 0];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_mem_baddr_corrupt <= 0;
+      else if (M_en)
+          M_mem_baddr_corrupt <= E_mem_baddr_corrupt;
+    end
+
+
+  assign E_logic_result = (E_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
+    (E_logic_op == 2'b01)? (E_src1 & E_src2) :
+    (E_logic_op == 2'b10)? (E_src1 | E_src2) :
+    (E_src1 ^ E_src2);
+
+  assign E_eq = E_src1_eq_src2;
+  assign E_lt = E_arith_result[32];
+  assign E_cmp_result = (E_compare_op == 2'b00)? E_eq :
+    (E_compare_op == 2'b01)? ~E_lt :
+    (E_compare_op == 2'b10)? E_lt :
+    ~E_eq;
+
+  assign E_br_result = E_cmp_result;
+  assign E_alu_result = ({32 {E_ctrl_cmp}} & {31'b0, E_cmp_result}) |
+    ({32 {E_ctrl_logic}} & E_logic_result) |
+    ({32 {E_ctrl_retaddr}} & {{3{1'b0}},{E_extra_pc, 2'b00}}) |
+    ({32 {E_ctrl_st_ex}} & {31'b0, E_up_ex_mon_state_latest}) |
+    ({32 {(~(E_ctrl_cmp)) && (~(E_ctrl_logic)) && (~(E_ctrl_retaddr)) && (~(E_ctrl_st_ex))}} & E_arith_result[31 : 0]);
+
+  assign E_sth_data = E_src2_reg[15 : 0];
+  assign E_stw_data = E_src2_reg[31 : 0];
+  assign E_stb_data = E_src2_reg[7 : 0];
+  assign E_st_data = (E_ctrl_mem8)? {E_stb_data, E_stb_data, E_stb_data, E_stb_data} :
+    (E_ctrl_mem16)? {E_sth_data, E_sth_data} :
+    E_stw_data;
+
+  assign E_mem_byte_en = ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
+    ({E_ctrl_mem16, E_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
+    4'b1111;
+
+  assign hbreak_enabled = ~W_debug_mode;
+  assign oci_tb_hbreak_req = oci_async_hbreak_req;
+  assign hbreak_req = (oci_tb_hbreak_req | latched_oci_tb_hbreak_req) 
+    & hbreak_enabled
+    & (~wait_for_one_post_bret_inst | ~A_one_post_bret_inst_n);
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_oci_sync_hbreak_req <= 0;
+      else if (M_en)
+          M_oci_sync_hbreak_req <= E_oci_sync_hbreak_req;
+    end
+
+
+  assign M_hbreak_req = hbreak_req | M_oci_sync_hbreak_req;
+  assign latched_oci_tb_hbreak_req_next = latched_oci_tb_hbreak_req ? hbreak_enabled 
+    : (hbreak_req);
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          latched_oci_tb_hbreak_req <= 1'b0;
+      else 
+        latched_oci_tb_hbreak_req <= latched_oci_tb_hbreak_req_next;
+    end
+
+
+  assign A_one_post_bret_inst_n = oci_single_step_mode & 
+    (~hbreak_enabled | ~(A_valid | A_exc_any_active));
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          wait_for_one_post_bret_inst <= 1'b0;
+      else 
+        wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 
+                : ((~A_one_post_bret_inst_n) | 
+                (~oci_single_step_mode))             ? 1'b0 
+                : wait_for_one_post_bret_inst;
+
+    end
+
+
+  assign E_fwd_reg_data = E_alu_result;
+  assign D_src1_reg = ((D_iw_a == 0))? 32'b0 :
+    (D_src1_choose_E)? E_fwd_reg_data :
+    (D_src1_choose_M)? M_fwd_reg_data :
+    (D_src1_choose_A)? A_fwd_reg_data :
+    (D_src1_choose_W)? W_wr_data :
+    D_rf_a;
+
+  assign D_src1 = D_src1_reg;
+  assign D_src2_reg = ((D_iw_b == 0))? 32'b0 :
+    (D_src2_choose_E)? E_fwd_reg_data :
+    (D_src2_choose_M)? M_fwd_reg_data :
+    (D_src2_choose_A)? A_fwd_reg_data :
+    (D_src2_choose_W)? W_wr_data :
+    D_rf_b;
+
+  assign D_src2_imm16_sel = {D_ctrl_hi_imm16,D_ctrl_unsigned_lo_imm16};
+  assign D_src2_imm16 = (D_src2_imm16_sel == 2'b00)? {{16 {D_iw_imm16[15]}}         , D_iw_imm16                    } :
+    (D_src2_imm16_sel == 2'b01)? {{16 {D_ctrl_set_src2_rem_imm}}, D_iw_imm16                    } :
+    (D_src2_imm16_sel == 2'b10)? {D_iw_imm16                                        , {16 {D_ctrl_set_src2_rem_imm}}} :
+    {{16 {1'b0}}                   , 16'b0                         };
+
+  assign D_src2_imm5_sel = D_ctrl_src_imm5_shift_rot;
+  assign D_src2_imm = (D_src2_imm5_sel == 1'b1)? {{27 {1'b0}}, D_iw_imm5} :
+    D_src2_imm16;
+
+  assign D_src2 = D_ctrl_src2_choose_imm ? D_src2_imm : D_src2_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_src1 <= 0;
+      else if (E_en)
+          E_src1 <= D_src1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_src2 <= 0;
+      else if (E_en)
+          E_src2 <= D_src2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_src2_reg <= 0;
+      else if (E_en)
+          E_src2_reg <= D_src2_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_src1 <= 0;
+      else if (M_en)
+          M_src1 <= E_src1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_src2 <= 0;
+      else if (M_en)
+          M_src2 <= E_src2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_src2 <= 0;
+      else if (A_en)
+          A_src2 <= M_src2;
+    end
+
+
+  assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
+    D_iw_op[4 : 3];
+
+  assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : 
+    D_ctrl_alu_force_and ? 2'b01 :
+    D_logic_op_raw;
+
+  assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] : 
+    D_iw_op[4 : 3];
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_logic_op <= 0;
+      else if (E_en)
+          E_logic_op <= D_logic_op;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_compare_op <= 0;
+      else if (E_en)
+          E_compare_op <= D_compare_op;
+    end
+
+
+  assign norm_intr_req = W_status_reg_pie & (W_ipending_reg != 0);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_norm_intr_req <= 0;
+      else if (M_en)
+          M_norm_intr_req <= norm_intr_req;
+    end
+
+
+  assign E_rot_n = E_src2[4 : 0];
+  assign E_rot_rn = E_ctrl_shift_rot_right ? -E_rot_n : E_rot_n;
+  assign E_rot_fill_bit = E_ctrl_shift_right_arith ? E_src1[31] : 0;
+  assign E_rot_left_mask = (E_rot_n[2 : 0] == 3'b000)? 8'b00000000 :
+    (E_rot_n[2 : 0] == 3'b001)? 8'b00000001 :
+    (E_rot_n[2 : 0] == 3'b010)? 8'b00000011 :
+    (E_rot_n[2 : 0] == 3'b011)? 8'b00000111 :
+    (E_rot_n[2 : 0] == 3'b100)? 8'b00001111 :
+    (E_rot_n[2 : 0] == 3'b101)? 8'b00011111 :
+    (E_rot_n[2 : 0] == 3'b110)? 8'b00111111 :
+    8'b01111111;
+
+  assign E_rot_right_mask = (E_rot_n[2 : 0] == 3'b000)? 8'b00000000 :
+    (E_rot_n[2 : 0] == 3'b001)? 8'b10000000 :
+    (E_rot_n[2 : 0] == 3'b010)? 8'b11000000 :
+    (E_rot_n[2 : 0] == 3'b011)? 8'b11100000 :
+    (E_rot_n[2 : 0] == 3'b100)? 8'b11110000 :
+    (E_rot_n[2 : 0] == 3'b101)? 8'b11111000 :
+    (E_rot_n[2 : 0] == 3'b110)? 8'b11111100 :
+    8'b11111110;
+
+  assign E_rot_mask = E_ctrl_shift_rot_right ? E_rot_right_mask : E_rot_left_mask;
+  assign E_rot_pass0 = E_ctrl_rot ||                                              (E_ctrl_shift_rot_right && (E_rot_n < 24));
+  assign E_rot_pass1 = E_ctrl_rot || (E_ctrl_shift_rot_left && (E_rot_n <  8)) || (E_ctrl_shift_rot_right && (E_rot_n < 16));
+  assign E_rot_pass2 = E_ctrl_rot || (E_ctrl_shift_rot_left && (E_rot_n < 16)) || (E_ctrl_shift_rot_right && (E_rot_n <  8));
+  assign E_rot_pass3 = E_ctrl_rot || (E_ctrl_shift_rot_left && (E_rot_n < 24));
+  assign E_rot_sel_fill0 = E_ctrl_shift_rot_left && (E_rot_n >=  8);
+  assign E_rot_sel_fill1 = (E_ctrl_shift_rot_left && (E_rot_n >= 16)) || (E_ctrl_shift_rot_right && (E_rot_n >= 24));
+  assign E_rot_sel_fill2 = (E_ctrl_shift_rot_left && (E_rot_n >= 24)) || (E_ctrl_shift_rot_right && (E_rot_n >= 16));
+  assign E_rot_sel_fill3 = E_ctrl_shift_rot_right && (E_rot_n >=  8);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_fill_bit <= 0;
+      else if (M_en)
+          M_rot_fill_bit <= E_rot_fill_bit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_mask <= 0;
+      else if (M_en)
+          M_rot_mask <= E_rot_mask;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_pass0 <= 0;
+      else if (M_en)
+          M_rot_pass0 <= E_rot_pass0;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_pass1 <= 0;
+      else if (M_en)
+          M_rot_pass1 <= E_rot_pass1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_pass2 <= 0;
+      else if (M_en)
+          M_rot_pass2 <= E_rot_pass2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_pass3 <= 0;
+      else if (M_en)
+          M_rot_pass3 <= E_rot_pass3;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_sel_fill0 <= 0;
+      else if (M_en)
+          M_rot_sel_fill0 <= E_rot_sel_fill0;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_sel_fill1 <= 0;
+      else if (M_en)
+          M_rot_sel_fill1 <= E_rot_sel_fill1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_sel_fill2 <= 0;
+      else if (M_en)
+          M_rot_sel_fill2 <= E_rot_sel_fill2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_sel_fill3 <= 0;
+      else if (M_en)
+          M_rot_sel_fill3 <= E_rot_sel_fill3;
+    end
+
+
+  assign E_rot_prestep1 = E_rot_rn[0] ? {E_src1[30 : 0], E_src1[31]} : E_src1;
+  assign E_rot_step1 = E_rot_rn[1] ? {E_rot_prestep1[29 : 0], E_rot_prestep1[31 : 30]} : E_rot_prestep1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_prestep2 <= 0;
+      else if (M_en)
+          M_rot_prestep2 <= E_rot_rn[2] ? {E_rot_step1[27 : 0], E_rot_step1[31 : 28]} : E_rot_step1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_rot_rn <= 0;
+      else if (M_en)
+          M_rot_rn <= E_rot_rn;
+    end
+
+
+  assign M_rot_step2 = M_rot_rn[3] ? 
+    {M_rot_prestep2[23 : 0], M_rot_prestep2[31 : 24]} : 
+    M_rot_prestep2;
+
+  assign M_rot = M_rot_rn[4] ? 
+    {M_rot_step2[15 : 0], M_rot_step2[31 : 16]} : 
+    M_rot_step2;
+
+  assign M_rot_lut0 = {8{M_rot_sel_fill0 & M_rot_fill_bit}} | (M_rot_fill_bit ? ({8{~M_rot_sel_fill0}} & (M_rot[7 : 0] | M_rot_mask)) : ({8{~M_rot_sel_fill0}} & M_rot[7 : 0] & ~M_rot_mask));
+  assign M_rot_lut1 = {8{M_rot_sel_fill1 & M_rot_fill_bit}} | (M_rot_fill_bit ? ({8{~M_rot_sel_fill1}} & (M_rot[15 : 8] | M_rot_mask)) : ({8{~M_rot_sel_fill1}} & M_rot[15 : 8] & ~M_rot_mask));
+  assign M_rot_lut2 = {8{M_rot_sel_fill2 & M_rot_fill_bit}} | (M_rot_fill_bit ? ({8{~M_rot_sel_fill2}} & (M_rot[23 : 16] | M_rot_mask)) : ({8{~M_rot_sel_fill2}} & M_rot[23 : 16] & ~M_rot_mask));
+  assign M_rot_lut3 = {8{M_rot_sel_fill3 & M_rot_fill_bit}} | (M_rot_fill_bit ? ({8{~M_rot_sel_fill3}} & (M_rot[31 : 24] | M_rot_mask)) : ({8{~M_rot_sel_fill3}} & M_rot[31 : 24] & ~M_rot_mask));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_shift_rot_result[7 : 0] <= 0;
+      else if (A_en)
+          A_shift_rot_result[7 : 0] <= M_rot_pass0 ? M_rot[7 : 0] : M_rot_lut0;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_shift_rot_result[15 : 8] <= 0;
+      else if (A_en)
+          A_shift_rot_result[15 : 8] <= M_rot_pass1 ? M_rot[15 : 8] : M_rot_lut1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_shift_rot_result[23 : 16] <= 0;
+      else if (A_en)
+          A_shift_rot_result[23 : 16] <= M_rot_pass2 ? M_rot[23 : 16] : M_rot_lut2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_shift_rot_result[31 : 24] <= 0;
+      else if (A_en)
+          A_shift_rot_result[31 : 24] <= M_rot_pass3 ? M_rot[31 : 24] : M_rot_lut3;
+    end
+
+
+  assign M_mul_s1 = M_mul_cell_p2[15 : 0] + M_mul_cell_p1[31 : 16];
+  assign A_mul_s2 = A_mul_cell_p3[15 : 0] + A_mul_s1;
+  assign A_mul_result = {A_mul_s2[15 : 0], A_mul_cell_p1[15 : 0]};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mul_cell_p1 <= 0;
+      else if (A_en)
+          A_mul_cell_p1 <= M_mul_cell_p1[15 : 0];
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mul_cell_p3 <= 0;
+      else if (A_en)
+          A_mul_cell_p3 <= M_mul_cell_p3;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mul_s1 <= 0;
+      else if (A_en)
+          A_mul_s1 <= M_mul_s1;
+    end
+
+
+  q_sys_cpu_cpu_mult_cell the_q_sys_cpu_cpu_mult_cell
+    (
+      .E_src1        (E_src1),
+      .E_src2        (E_src2),
+      .M_en          (M_en),
+      .M_mul_cell_p1 (M_mul_cell_p1),
+      .M_mul_cell_p2 (M_mul_cell_p2),
+      .M_mul_cell_p3 (M_mul_cell_p3),
+      .clk           (clk),
+      .reset_n       (reset_n)
+    );
+
+  assign E_mem_bypass_non_io = E_arith_result[31];
+  assign A_valid_st_writes_mem = A_ctrl_st & A_valid & A_st_writes_mem;
+  assign E_ld_cache = E_sel_data_master &
+    E_ctrl_ld_non_io & ~E_mem_bypass_non_io;
+
+  assign E_st_cache = E_sel_data_master &
+    E_ctrl_st_non_io & ~E_mem_bypass_non_io & E_st_writes_mem;
+
+  assign E_ld_st_cache = E_sel_data_master &
+    E_ctrl_ld_st_non_io & ~E_mem_bypass_non_io & E_st_writes_mem;
+
+  assign E_stnon32_cache = E_sel_data_master &
+    E_ctrl_st_non32 & ~E_mem_bypass_non_io & E_st_writes_mem;
+
+  assign E_ld_stnon32_cache = E_sel_data_master &
+    (E_ctrl_ld_non_io | E_ctrl_st_non32) &
+    ~E_mem_bypass_non_io & E_st_writes_mem;
+
+  assign E_ld_bus = E_sel_data_master &
+    (E_ctrl_ld_io | (E_ctrl_ld_non_io & E_mem_bypass_non_io));
+
+  assign E_st_bus = E_sel_data_master &
+    (E_ctrl_st_io | 
+    (E_ctrl_st_non_io & E_mem_bypass_non_io & E_st_writes_mem));
+
+  assign E_ld_st_bus = E_sel_data_master &
+    (E_ctrl_ld_st_io | 
+    (E_ctrl_ld_st_non_io & E_mem_bypass_non_io & E_st_writes_mem));
+
+  assign E_ld_st_dcache_management_bus = E_ld_st_bus | E_ctrl_dcache_management;
+  assign E_ctrl_ld_cache = E_ld_cache;
+  assign M_ctrl_ld_cache_nxt = E_ctrl_ld_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_cache <= 0;
+      else if (M_en)
+          M_ctrl_ld_cache <= M_ctrl_ld_cache_nxt;
+    end
+
+
+  assign A_ctrl_ld_cache_nxt = M_ctrl_ld_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_cache <= 0;
+      else if (A_en)
+          A_ctrl_ld_cache <= A_ctrl_ld_cache_nxt;
+    end
+
+
+  assign E_ctrl_st_cache = E_st_cache;
+  assign M_ctrl_st_cache_nxt = E_ctrl_st_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_cache <= 0;
+      else if (M_en)
+          M_ctrl_st_cache <= M_ctrl_st_cache_nxt;
+    end
+
+
+  assign A_ctrl_st_cache_nxt = M_ctrl_st_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_cache <= 0;
+      else if (A_en)
+          A_ctrl_st_cache <= A_ctrl_st_cache_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_cache = E_ld_st_cache;
+  assign M_ctrl_ld_st_cache_nxt = E_ctrl_ld_st_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_cache <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_cache <= M_ctrl_ld_st_cache_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_cache_nxt = M_ctrl_ld_st_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_cache <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_cache <= A_ctrl_ld_st_cache_nxt;
+    end
+
+
+  assign E_ctrl_stnon32_cache = E_stnon32_cache;
+  assign M_ctrl_stnon32_cache_nxt = E_ctrl_stnon32_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_stnon32_cache <= 0;
+      else if (M_en)
+          M_ctrl_stnon32_cache <= M_ctrl_stnon32_cache_nxt;
+    end
+
+
+  assign A_ctrl_stnon32_cache_nxt = M_ctrl_stnon32_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_stnon32_cache <= 0;
+      else if (A_en)
+          A_ctrl_stnon32_cache <= A_ctrl_stnon32_cache_nxt;
+    end
+
+
+  assign E_ctrl_ld_stnon32_cache = E_ld_stnon32_cache;
+  assign M_ctrl_ld_stnon32_cache_nxt = E_ctrl_ld_stnon32_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_stnon32_cache <= 0;
+      else if (M_en)
+          M_ctrl_ld_stnon32_cache <= M_ctrl_ld_stnon32_cache_nxt;
+    end
+
+
+  assign A_ctrl_ld_stnon32_cache_nxt = M_ctrl_ld_stnon32_cache;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_stnon32_cache <= 0;
+      else if (A_en)
+          A_ctrl_ld_stnon32_cache <= A_ctrl_ld_stnon32_cache_nxt;
+    end
+
+
+  assign E_ctrl_ld_bypass = E_ld_bus;
+  assign M_ctrl_ld_bypass_nxt = E_ctrl_ld_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_bypass <= 0;
+      else if (M_en)
+          M_ctrl_ld_bypass <= M_ctrl_ld_bypass_nxt;
+    end
+
+
+  assign A_ctrl_ld_bypass_nxt = M_ctrl_ld_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_bypass <= 0;
+      else if (A_en)
+          A_ctrl_ld_bypass <= A_ctrl_ld_bypass_nxt;
+    end
+
+
+  assign E_ctrl_st_bypass = E_st_bus;
+  assign M_ctrl_st_bypass_nxt = E_ctrl_st_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_bypass <= 0;
+      else if (M_en)
+          M_ctrl_st_bypass <= M_ctrl_st_bypass_nxt;
+    end
+
+
+  assign A_ctrl_st_bypass_nxt = M_ctrl_st_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_bypass <= 0;
+      else if (A_en)
+          A_ctrl_st_bypass <= A_ctrl_st_bypass_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_bypass = E_ld_st_bus;
+  assign M_ctrl_ld_st_bypass_nxt = E_ctrl_ld_st_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_bypass <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_bypass <= M_ctrl_ld_st_bypass_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_bypass_nxt = M_ctrl_ld_st_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_bypass <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_bypass <= A_ctrl_ld_st_bypass_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_bypass_or_dcache_management = E_ld_st_dcache_management_bus;
+  assign M_ctrl_ld_st_bypass_or_dcache_management_nxt = E_ctrl_ld_st_bypass_or_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_bypass_or_dcache_management <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_bypass_or_dcache_management <= M_ctrl_ld_st_bypass_or_dcache_management_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_bypass_or_dcache_management_nxt = M_ctrl_ld_st_bypass_or_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_bypass_or_dcache_management <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_bypass_or_dcache_management <= A_ctrl_ld_st_bypass_or_dcache_management_nxt;
+    end
+
+
+  assign E_ctrl_ld_non_bypass = E_ld_cache | E_dtcm_ld;
+  assign M_ctrl_ld_non_bypass_nxt = E_ctrl_ld_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_non_bypass <= 0;
+      else if (M_en)
+          M_ctrl_ld_non_bypass <= M_ctrl_ld_non_bypass_nxt;
+    end
+
+
+  assign A_ctrl_ld_non_bypass_nxt = M_ctrl_ld_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_non_bypass <= 0;
+      else if (A_en)
+          A_ctrl_ld_non_bypass <= A_ctrl_ld_non_bypass_nxt;
+    end
+
+
+  assign E_ctrl_st_non_bypass = E_st_cache | E_dtcm_st;
+  assign M_ctrl_st_non_bypass_nxt = E_ctrl_st_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_non_bypass <= 0;
+      else if (M_en)
+          M_ctrl_st_non_bypass <= M_ctrl_st_non_bypass_nxt;
+    end
+
+
+  assign A_ctrl_st_non_bypass_nxt = M_ctrl_st_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_non_bypass <= 0;
+      else if (A_en)
+          A_ctrl_st_non_bypass <= A_ctrl_st_non_bypass_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_non_bypass = E_ld_st_cache | E_dtcm_ld_st;
+  assign M_ctrl_ld_st_non_bypass_nxt = E_ctrl_ld_st_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_non_bypass <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_non_bypass <= M_ctrl_ld_st_non_bypass_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_non_bypass_nxt = M_ctrl_ld_st_non_bypass;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_non_bypass <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_non_bypass <= A_ctrl_ld_st_non_bypass_nxt;
+    end
+
+
+  assign E_ctrl_mem_dc_tag_rd = E_ld_st_cache | 
+    E_ctrl_dc_index_wb_inv |
+    E_ctrl_dc_addr_wb_inv |
+    E_ctrl_dc_addr_nowb_inv;
+
+  assign M_ctrl_mem_dc_tag_rd_nxt = E_ctrl_mem_dc_tag_rd;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem_dc_tag_rd <= 0;
+      else if (M_en)
+          M_ctrl_mem_dc_tag_rd <= M_ctrl_mem_dc_tag_rd_nxt;
+    end
+
+
+  assign A_ctrl_mem_dc_tag_rd_nxt = M_ctrl_mem_dc_tag_rd;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem_dc_tag_rd <= 0;
+      else if (A_en)
+          A_ctrl_mem_dc_tag_rd <= A_ctrl_mem_dc_tag_rd_nxt;
+    end
+
+
+  assign E_ctrl_mem_dc_data_rd = E_ld_stnon32_cache;
+  assign M_ctrl_mem_dc_data_rd_nxt = E_ctrl_mem_dc_data_rd;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem_dc_data_rd <= 0;
+      else if (M_en)
+          M_ctrl_mem_dc_data_rd <= M_ctrl_mem_dc_data_rd_nxt;
+    end
+
+
+  assign A_ctrl_mem_dc_data_rd_nxt = M_ctrl_mem_dc_data_rd;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem_dc_data_rd <= 0;
+      else if (A_en)
+          A_ctrl_mem_dc_data_rd <= A_ctrl_mem_dc_data_rd_nxt;
+    end
+
+
+  assign M_A_dc_tag_ram_addr_match = M_mem_baddr_line_field == A_mem_baddr_line_field;
+  assign M_W_dc_tag_ram_addr_match = M_mem_baddr_line_field == W_mem_baddr_line_field;
+  assign M_A_dc_tag_line_addr_match = (M_mem_baddr_tag_field == A_mem_baddr_tag_field) & 
+    (M_mem_baddr_line_field == A_mem_baddr_line_field);
+
+  assign A_dc_valid_st_cache_hit = A_ctrl_st_cache & A_valid & A_dc_hit;
+  assign M_dc_dirty = M_dc_dirty_raw | 
+    (M_A_dc_tag_ram_addr_match & A_dc_valid_st_cache_hit) |
+    (M_W_dc_tag_ram_addr_match & W_dc_valid_st_cache_hit);
+
+  assign M_dc_raw_hazard = M_valid_ignoring_refetch & 
+    (
+    (
+    A_dc_valid_st_cache_hit & (M_mem_waddr_phy == A_mem_waddr_phy) &
+    (
+    (M_ctrl_ld_cache & (0 | ((M_mem_byte_en & A_mem_byte_en) != 0))) |
+    (M_ctrl_stnon32_cache & 0)
+    )
+    ) |
+    (
+    W_dc_valid_st_cache_hit & (M_mem_waddr_phy == W_mem_waddr_phy) &
+    (
+    (M_ctrl_ld_cache & (0 | ((M_mem_byte_en & W_mem_byte_en) != 0))) |
+    (M_ctrl_stnon32_cache & 0)
+    )
+    )
+    );
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_dirty <= 0;
+      else if (A_en)
+          A_dc_dirty <= M_dc_dirty;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_dc_valid_st_cache_hit <= 0;
+      else if (W_en)
+          W_dc_valid_st_cache_hit <= A_dc_valid_st_cache_hit;
+    end
+
+
+  assign E_mem_baddr_tag_field = E_mem_baddr[28 : 11];
+  assign E_mem_baddr_line_field = E_mem_baddr[10 : 5];
+  assign E_mem_baddr_offset_field = E_mem_baddr[4 : 2];
+  assign E_mem_baddr_line_offset_field = E_mem_baddr[10 : 2];
+  assign E_mem_baddr_byte_field = E_mem_baddr[1 : 0];
+  assign M_mem_baddr_tag_field = M_mem_baddr[28 : 11];
+  assign M_mem_baddr_line_field = M_mem_baddr[10 : 5];
+  assign M_mem_baddr_offset_field = M_mem_baddr[4 : 2];
+  assign M_mem_baddr_line_offset_field = M_mem_baddr[10 : 2];
+  assign M_mem_baddr_byte_field = M_mem_baddr[1 : 0];
+  assign A_mem_baddr_tag_field = A_mem_baddr[28 : 11];
+  assign A_mem_baddr_line_field = A_mem_baddr[10 : 5];
+  assign A_mem_baddr_offset_field = A_mem_baddr[4 : 2];
+  assign A_mem_baddr_line_offset_field = A_mem_baddr[10 : 2];
+  assign A_mem_baddr_byte_field = A_mem_baddr[1 : 0];
+  assign W_mem_baddr_tag_field = W_mem_baddr[28 : 11];
+  assign W_mem_baddr_line_field = W_mem_baddr[10 : 5];
+  assign W_mem_baddr_offset_field = W_mem_baddr[4 : 2];
+  assign W_mem_baddr_line_offset_field = W_mem_baddr[10 : 2];
+  assign W_mem_baddr_byte_field = W_mem_baddr[1 : 0];
+  assign dc_tag_wr_port_data = (A_dc_fill_starting_d1)? {A_valid_st_writes_mem, dc_line_valid_on, A_dc_desired_tag} :
+    (A_dc_tag_dcache_management_wr_en)? {dc_line_dirty_off, dc_line_valid_off, A_dc_desired_tag} :
+    {dc_line_dirty_on,  dc_line_valid_on,  A_dc_desired_tag};
+
+  assign A_dc_tag_st_wr_en = A_dc_valid_st_cache_hit & !A_dc_dirty & A_en_d1;
+  assign A_dc_tag_dcache_management_wr_en = (A_ctrl_dc_index_inv | (A_ctrl_dc_addr_inv & A_dc_hit)) & A_valid & A_en_d1;
+  assign dc_tag_wr_port_en = A_dc_tag_st_wr_en|A_dc_tag_dcache_management_wr_en|A_dc_fill_starting_d1;
+  assign dc_tag_wr_port_addr = A_mem_baddr_line_field;
+  assign dc_line_dirty_on = 1'b1;
+  assign dc_line_dirty_off = 1'b0;
+  assign dc_line_valid_on = 1'b1;
+  assign dc_line_valid_off = 1'b0;
+  assign M_dc_tag_entry = dc_tag_rd_port_data;
+  assign M_dc_dirty_raw = M_dc_tag_entry[19];
+  assign M_dc_valid = M_dc_tag_entry[18];
+  assign M_dc_actual_tag = M_dc_tag_entry[17 : 0];
+  assign dc_tag_rd_port_addr = M_en ? E_mem_baddr_line_field : M_mem_baddr_line_field;
+//q_sys_cpu_cpu_dc_tag, which is an nios_sdp_ram
+q_sys_cpu_cpu_dc_tag_module q_sys_cpu_cpu_dc_tag
+  (
+    .clock     (clk),
+    .data      (dc_tag_wr_port_data),
+    .q         (dc_tag_rd_port_data),
+    .rdaddress (dc_tag_rd_port_addr),
+    .wraddress (dc_tag_wr_port_addr),
+    .wren      (dc_tag_wr_port_en)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam q_sys_cpu_cpu_dc_tag.lpm_file = "q_sys_cpu_cpu_dc_tag_ram.dat";
+`else
+defparam q_sys_cpu_cpu_dc_tag.lpm_file = "q_sys_cpu_cpu_dc_tag_ram.hex";
+`endif
+//synthesis translate_on
+  assign M_dc_desired_tag = M_mem_baddr[28 : 11];
+  assign M_dc_tag_match = M_dc_desired_tag == M_dc_actual_tag;
+  assign A_dc_desired_tag = A_mem_baddr[28 : 11];
+  assign M_dc_hit = M_dc_tag_match & M_dc_valid;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_hit <= 0;
+      else if (A_en)
+          A_dc_hit <= M_dc_hit;
+    end
+
+
+  assign dc_data_rd_port_line_field = M_en                     ? E_mem_baddr_line_field : 
+    A_dc_xfer_rd_addr_active ? A_mem_baddr_line_field :
+    M_mem_baddr_line_field;
+
+  assign dc_data_rd_port_offset_field = M_en                      ? E_mem_baddr_offset_field : 
+    A_dc_xfer_rd_addr_active  ? A_dc_xfer_rd_addr_offset :
+    M_mem_baddr_offset_field;
+
+  assign dc_data_rd_port_addr = {dc_data_rd_port_line_field, dc_data_rd_port_offset_field};
+  assign M_dc_rd_data = dc_data_rd_port_data;
+  assign M_dc_st_data = M_ctrl_dc_index_nowb_inv ? 32'b0 : M_st_data;
+  assign A_dc_data_st_wr_en = A_dc_valid_st_cache_hit & A_en_d1;
+  assign A_dc_data_dcache_management_wr_en = A_ctrl_dc_index_nowb_inv & A_valid & A_en_d1;
+  assign dc_data_wr_port_data = A_dc_fill_active                  ? A_dc_fill_wr_data : 
+    A_dc_st_data;
+
+  assign dc_data_wr_port_addr = A_dc_fill_active                  ? { A_mem_baddr_line_field, A_dc_fill_dp_offset } : 
+    A_mem_baddr_line_offset_field;
+
+  assign dc_data_wr_port_en = (A_dc_fill_active ? d_readdatavalid_d1 : A_dc_data_st_wr_en) |
+    A_dc_data_dcache_management_wr_en;
+
+  assign dc_data_wr_port_byte_en = A_dc_fill_active               ? {4{1'b1}} : 
+    A_mem_byte_en;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_st_data <= 0;
+      else if (A_en)
+          A_dc_st_data <= M_dc_st_data;
+    end
+
+
+//q_sys_cpu_cpu_dc_data, which is an nios_sdp_ram
+q_sys_cpu_cpu_dc_data_module q_sys_cpu_cpu_dc_data
+  (
+    .byteenable (dc_data_wr_port_byte_en),
+    .clock      (clk),
+    .data       (dc_data_wr_port_data),
+    .q          (dc_data_rd_port_data),
+    .rdaddress  (dc_data_rd_port_addr),
+    .wraddress  (dc_data_wr_port_addr),
+    .wren       (dc_data_wr_port_en)
+  );
+
+  assign M_dc_want_fill = M_ctrl_ld_st_cache & M_valid & ~M_dc_hit;
+  assign A_dc_fill_starting = A_dc_want_fill & ~A_cancel & ~A_dc_fill_has_started & ~A_dc_wb_active;
+  assign A_dc_fill_has_started_nxt = A_en ? 1'b0 : (A_dc_fill_starting | A_dc_fill_has_started);
+  assign A_dc_fill_need_extra_stall_nxt = M_ctrl_ld_stnon32_cache & M_valid & M_A_dc_tag_line_addr_match & 
+    (M_mem_baddr_offset_field == 7);
+
+  assign A_dc_fill_done = A_dc_fill_need_extra_stall ? A_dc_rd_last_transfer_d1 : A_dc_rd_last_transfer;
+  assign A_dc_fill_active_nxt = A_dc_fill_active ? ~A_dc_fill_done : A_dc_fill_starting;
+  assign A_dc_fill_want_dmaster = A_dc_fill_starting | A_dc_fill_active;
+  assign A_dc_fill_dp_offset_nxt = A_dc_fill_starting ? 0 : (A_dc_fill_dp_offset + 1);
+  assign A_dc_fill_dp_offset_en = A_dc_fill_starting | d_readdatavalid_d1;
+  assign A_dc_fill_miss_offset_is_next = A_dc_fill_active & (A_dc_fill_dp_offset == A_mem_baddr_offset_field);
+  assign A_dc_fill_wr_data = (A_ctrl_st & A_st_writes_mem & A_dc_fill_miss_offset_is_next) ?
+    A_dc_fill_st_data_merged : 
+    d_readdata_d1;
+
+  assign A_dc_fill_st_data_merged = { A_mem_byte_en[3] ? A_st_data[31 : 24] : d_readdata_d1[31 : 24],
+    A_mem_byte_en[2] ? A_st_data[23 : 16] : d_readdata_d1[23 : 16],
+    A_mem_byte_en[1] ? A_st_data[15 : 8]  : d_readdata_d1[15 : 8],
+    A_mem_byte_en[0] ? A_st_data[7 : 0]   : d_readdata_d1[7 : 0] };
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_want_fill <= 0;
+      else if (A_en)
+          A_dc_want_fill <= M_dc_want_fill;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_fill_has_started <= 0;
+      else 
+        A_dc_fill_has_started <= A_dc_fill_has_started_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_fill_active <= 0;
+      else 
+        A_dc_fill_active <= A_dc_fill_active_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_fill_dp_offset <= 0;
+      else if (A_dc_fill_dp_offset_en)
+          A_dc_fill_dp_offset <= A_dc_fill_dp_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_fill_starting_d1 <= 0;
+      else 
+        A_dc_fill_starting_d1 <= A_dc_fill_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_fill_need_extra_stall <= 0;
+      else 
+        A_dc_fill_need_extra_stall <= A_dc_fill_need_extra_stall_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_rd_last_transfer_d1 <= 0;
+      else 
+        A_dc_rd_last_transfer_d1 <= A_dc_rd_last_transfer;
+    end
+
+
+  assign A_dc_wb_active_nxt = A_dc_wb_active ? ~A_dc_wr_last_transfer : A_dc_xfer_rd_addr_starting;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_active <= 0;
+      else 
+        A_dc_wb_active <= A_dc_wb_active_nxt;
+    end
+
+
+  assign dc_wb_wr_port_data = A_dc_xfer_wr_data;
+  assign dc_wb_wr_port_en = A_dc_xfer_wr_active;
+  assign dc_wb_wr_port_addr = A_dc_xfer_wr_offset;
+  assign dc_wb_rd_port_en = A_dc_wb_rd_en;
+  assign dc_wb_rd_port_addr = A_dc_wb_rd_addr_offset;
+  assign A_dc_wb_rd_data = dc_wb_rd_data;
+//q_sys_cpu_cpu_dc_victim, which is an nios_sdp_ram
+q_sys_cpu_cpu_dc_victim_module q_sys_cpu_cpu_dc_victim
+  (
+    .clock     (clk),
+    .data      (dc_wb_wr_port_data),
+    .q         (dc_wb_rd_data),
+    .rdaddress (dc_wb_rd_port_addr),
+    .rden      (dc_wb_rd_port_en),
+    .wraddress (dc_wb_wr_port_addr),
+    .wren      (dc_wb_wr_port_en)
+  );
+
+  assign A_dc_fill_want_xfer = A_dc_want_fill & A_valid & A_dc_dirty;
+  assign A_dc_index_wb_inv_want_xfer = A_ctrl_dc_index_wb_inv & A_valid & A_dc_dirty;
+  assign A_dc_dc_addr_wb_inv_want_xfer = A_ctrl_dc_addr_wb_inv & A_valid & A_dc_dirty & A_dc_hit;
+  assign A_dc_want_xfer = A_dc_fill_want_xfer | A_dc_index_wb_inv_want_xfer | A_dc_dc_addr_wb_inv_want_xfer;
+  assign A_dc_xfer_rd_addr_starting = A_dc_want_xfer & ~A_dc_xfer_rd_addr_has_started & ~A_dc_wb_active;
+  assign A_dc_xfer_rd_addr_has_started_nxt = A_en ? 1'b0 : (A_dc_xfer_rd_addr_starting | A_dc_xfer_rd_addr_has_started);
+  assign A_dc_xfer_rd_addr_done_nxt = A_dc_xfer_rd_addr_active & (A_dc_xfer_rd_addr_offset == (7 - 1));
+  assign A_dc_xfer_rd_addr_active_nxt = A_dc_xfer_rd_addr_active ? ~A_dc_xfer_rd_addr_done : A_dc_xfer_rd_addr_starting;
+  assign A_dc_xfer_rd_addr_offset_nxt = A_dc_xfer_rd_addr_starting ? 0 : (A_dc_xfer_rd_addr_offset + 1);
+  assign A_dc_xfer_wr_offset_starting = A_dc_xfer_wr_starting;
+  assign A_dc_xfer_wr_offset_nxt = A_dc_xfer_wr_offset_starting          ? 0 : (A_dc_xfer_wr_offset + 1);
+  assign A_dc_xfer_wr_data_nxt = dc_data_rd_port_data;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_addr_has_started <= 0;
+      else 
+        A_dc_xfer_rd_addr_has_started <= A_dc_xfer_rd_addr_has_started_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_addr_active <= 0;
+      else 
+        A_dc_xfer_rd_addr_active <= A_dc_xfer_rd_addr_active_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_addr_done <= 0;
+      else 
+        A_dc_xfer_rd_addr_done <= A_dc_xfer_rd_addr_done_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_addr_offset <= 0;
+      else 
+        A_dc_xfer_rd_addr_offset <= A_dc_xfer_rd_addr_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_data_starting <= 0;
+      else 
+        A_dc_xfer_rd_data_starting <= A_dc_xfer_rd_addr_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_rd_data_active <= 0;
+      else 
+        A_dc_xfer_rd_data_active <= A_dc_xfer_rd_addr_active;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_wr_starting <= 0;
+      else 
+        A_dc_xfer_wr_starting <= A_dc_xfer_rd_data_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_wr_active <= 0;
+      else 
+        A_dc_xfer_wr_active <= A_dc_xfer_rd_data_active;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_wr_offset <= 0;
+      else 
+        A_dc_xfer_wr_offset <= A_dc_xfer_wr_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_xfer_wr_data <= 0;
+      else 
+        A_dc_xfer_wr_data <= A_dc_xfer_wr_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_actual_tag <= 0;
+      else if (A_en)
+          A_dc_actual_tag <= M_dc_actual_tag;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_tag <= 0;
+      else if (A_dc_xfer_rd_data_starting)
+          A_dc_wb_tag <= A_dc_actual_tag;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_line <= 0;
+      else if (A_dc_xfer_rd_data_starting)
+          A_dc_wb_line <= A_mem_baddr_line_field;
+    end
+
+
+  assign A_dc_wb_rd_en = A_dc_wb_rd_addr_starting | A_dc_wb_rd_data_starting | A_dc_wb_wr_starting | 
+    av_wr_data_transfer;
+
+  assign A_dc_wb_wr_starting = A_dc_wb_rd_data_first & ~d_read;
+  assign A_dc_wb_wr_active_nxt = A_dc_wb_wr_active ? ~A_dc_wr_last_transfer : A_dc_wb_wr_starting;
+  assign A_dc_wb_wr_want_dmaster = A_dc_wb_wr_starting | A_dc_wb_wr_active;
+  assign A_dc_wb_rd_data_first_nxt = A_dc_wb_rd_data_first ? ~A_dc_wb_wr_starting : A_dc_wb_rd_data_starting;
+  assign A_dc_wb_update_av_writedata = A_dc_wb_wr_starting | 
+    (A_dc_wb_wr_active & ~A_dc_wr_last_driven & ~d_waitrequest);
+
+  assign A_dc_wb_rd_addr_offset_nxt = A_dc_wb_rd_addr_starting ? 0 : (A_dc_wb_rd_addr_offset + 1);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_rd_addr_starting <= 0;
+      else 
+        A_dc_wb_rd_addr_starting <= A_dc_xfer_wr_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_rd_addr_offset <= 0;
+      else if (A_dc_wb_rd_en)
+          A_dc_wb_rd_addr_offset <= A_dc_wb_rd_addr_offset_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_rd_data_starting <= 0;
+      else 
+        A_dc_wb_rd_data_starting <= A_dc_wb_rd_addr_starting;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_wr_active <= 0;
+      else 
+        A_dc_wb_wr_active <= A_dc_wb_wr_active_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wb_rd_data_first <= 0;
+      else 
+        A_dc_wb_rd_data_first <= A_dc_wb_rd_data_first_nxt;
+    end
+
+
+  assign A_dc_index_wb_inv_done_nxt = ~A_dc_dirty | A_dc_xfer_rd_addr_done;
+  assign A_dc_dc_addr_wb_inv_done_nxt = ~A_dc_dirty | A_dc_xfer_rd_addr_done | ~A_dc_hit;
+  assign A_dc_dcache_management_done_nxt = A_valid & ~A_en &
+    (A_ctrl_dc_nowb_inv |
+    (A_ctrl_dc_index_wb_inv & A_dc_index_wb_inv_done_nxt) |
+    ((A_ctrl_dc_addr_wb_inv ) & A_dc_dc_addr_wb_inv_done_nxt));
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_dcache_management_done <= 0;
+      else 
+        A_dc_dcache_management_done <= A_dc_dcache_management_done_nxt;
+    end
+
+
+  assign M_dc_bypass_or_dcache_management = M_ctrl_ld_st_bypass_or_dcache_management & M_valid;
+  assign A_ld_bypass_done = A_dc_rd_last_transfer;
+  assign A_st_bypass_done = A_dc_wr_last_transfer & ~A_dc_wb_active;
+  assign A_mem_bypass_pending = A_ctrl_ld_st_bypass & A_valid & ~A_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_bypass_delayed <= 0;
+      else if (A_en)
+          A_ld_bypass_delayed <= M_ctrl_ld_bypass & M_valid & A_dc_wb_active;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_st_bypass_delayed <= 0;
+      else if (A_en)
+          A_st_bypass_delayed <= M_ctrl_st_bypass & M_valid & A_dc_wb_active;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ld_bypass_delayed_started <= 0;
+      else 
+        A_ld_bypass_delayed_started <= A_en ? 0 : 
+                ((A_ld_bypass_delayed & ~A_dc_wb_active) | 
+                A_ld_bypass_delayed_started);
+
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_st_bypass_delayed_started <= 0;
+      else 
+        A_st_bypass_delayed_started <= A_en ? 0 : 
+                ((A_st_bypass_delayed & ~A_dc_wb_active) | 
+                A_st_bypass_delayed_started);
+
+    end
+
+
+  assign d_address_tag_field_nxt = A_dc_wb_wr_want_dmaster                         ? A_dc_wb_tag : 
+    (A_dc_fill_want_dmaster | A_mem_bypass_pending) ? A_dc_desired_tag :
+    M_dc_desired_tag;
+
+  assign d_address_line_field_nxt = A_dc_wb_wr_want_dmaster                         ? 
+    A_dc_wb_line : 
+    (A_dc_fill_want_dmaster | A_mem_bypass_pending) ? 
+    A_mem_baddr_line_field :
+    M_mem_baddr_line_field;
+
+  assign d_address_byte_field_nxt = (A_dc_wb_wr_want_dmaster | A_dc_fill_want_dmaster) ? 0 : 
+    A_mem_bypass_pending                      ? A_mem_baddr_byte_field :
+    M_mem_baddr_byte_field;
+
+  assign d_byteenable_nxt = (A_dc_wb_wr_want_dmaster | A_dc_fill_want_dmaster) ? {4{1'b1}} : 
+    A_mem_bypass_pending                               ? A_mem_byte_en :
+    M_mem_byte_en;
+
+  assign d_writedata_nxt = A_dc_wb_update_av_writedata                 ? A_dc_wb_rd_data : 
+    A_dc_wb_wr_active                           ? d_writedata :
+    A_mem_bypass_pending                        ? A_st_data :
+    M_st_data;
+
+  assign d_write_nxt = A_dc_wb_wr_starting |
+    (M_ctrl_st_bypass & M_valid & A_en & ~A_dc_wb_active) | 
+    (A_st_bypass_delayed & ~A_st_bypass_delayed_started & ~A_dc_wb_active & ~A_refetch_required) |
+    (d_write & (d_waitrequest | ~A_dc_wr_last_driven));
+
+  assign d_address = {d_address_tag_field, 
+    d_address_line_field[5 : 0],
+    d_address_offset_field,
+    d_address_byte_field};
+
+  assign A_dc_rd_data_cnt_nxt = d_readdatavalid_d1 ? (A_dc_rd_data_cnt + 1) :
+    A_dc_fill_starting ? 1 :
+    A_dc_fill_active   ? A_dc_rd_data_cnt :
+    8;
+
+  assign A_dc_rd_last_transfer = A_dc_rd_data_cnt[3] & d_readdatavalid_d1;
+  assign av_wr_data_transfer = d_write & ~d_waitrequest;
+  assign A_dc_wr_data_cnt_nxt = av_wr_data_transfer ? (A_dc_wr_data_cnt + 1) :
+    A_dc_wb_wr_starting ? 1 :
+    A_dc_wb_wr_active   ? A_dc_wr_data_cnt :
+    8;
+
+  assign A_dc_wr_last_driven = A_dc_wr_data_cnt[3];
+  assign A_dc_wr_last_transfer = A_dc_wr_last_driven & d_write & ~d_waitrequest;
+  assign av_addr_accepted = (d_read | d_write) & ~d_waitrequest;
+  assign d_address_offset_field_nxt = av_addr_accepted ? (d_address_offset_field + 1) :
+    (A_dc_wb_wr_starting | A_dc_fill_starting) ? 0 :
+    (A_dc_wb_wr_active | A_dc_fill_active) ? d_address_offset_field :
+    A_mem_bypass_pending                ? A_mem_baddr_offset_field :
+    M_mem_baddr_offset_field;
+
+  assign d_read_nxt = A_dc_fill_starting |
+    (M_ctrl_ld_bypass & M_valid & A_en & ~A_dc_wb_active) | 
+    (A_ld_bypass_delayed & ~A_ld_bypass_delayed_started & 
+    ~A_dc_wb_active) |
+    (d_read & (d_waitrequest | ~A_dc_rd_last_driven));
+
+  assign av_rd_addr_accepted = d_read & ~d_waitrequest;
+  assign A_dc_rd_addr_cnt_nxt = av_rd_addr_accepted ? (A_dc_rd_addr_cnt + 1) :
+    A_dc_fill_starting  ? 1 :
+    A_dc_fill_active    ? A_dc_rd_addr_cnt :
+    8;
+
+  assign A_dc_rd_last_driven = A_dc_rd_addr_cnt[3];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_rd_addr_cnt <= 0;
+      else 
+        A_dc_rd_addr_cnt <= A_dc_rd_addr_cnt_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_address_tag_field <= 0;
+      else 
+        d_address_tag_field <= d_address_tag_field_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_address_line_field <= 0;
+      else 
+        d_address_line_field <= d_address_line_field_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_address_offset_field <= 0;
+      else 
+        d_address_offset_field <= d_address_offset_field_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_address_byte_field <= 0;
+      else 
+        d_address_byte_field <= d_address_byte_field_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_byteenable <= 0;
+      else 
+        d_byteenable <= d_byteenable_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_writedata <= 0;
+      else 
+        d_writedata <= d_writedata_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_rd_data_cnt <= 0;
+      else 
+        A_dc_rd_data_cnt <= A_dc_rd_data_cnt_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_dc_wr_data_cnt <= 0;
+      else 
+        A_dc_wr_data_cnt <= A_dc_wr_data_cnt_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_read <= 0;
+      else 
+        d_read <= d_read_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_write <= 0;
+      else 
+        d_write <= d_write_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_readdata_d1 <= 0;
+      else 
+        d_readdata_d1 <= d_readdata;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_readdatavalid_d1 <= 0;
+      else 
+        d_readdatavalid_d1 <= d_readdatavalid;
+    end
+
+
+  assign A_mem_stall_start_nxt = A_en & (M_dc_want_fill|M_dc_bypass_or_dcache_management);
+  assign A_mem_stall_stop_nxt = (A_dc_fill_active & A_dc_fill_done)|A_dc_dcache_management_done|(A_ctrl_ld_bypass & A_ld_bypass_done)|(A_ctrl_st_bypass & A_st_bypass_done);
+  assign A_mem_stall_nxt = A_mem_stall ? ~A_mem_stall_stop_nxt : A_mem_stall_start_nxt;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mem_stall <= 0;
+      else 
+        A_mem_stall <= A_mem_stall_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_data_ram_ld_align_sign_bit_16_hi <= 0;
+      else if (M_en)
+          M_data_ram_ld_align_sign_bit_16_hi <= (E_mem_baddr[0]) | E_ctrl_ld16;
+    end
+
+
+  assign M_data_ram_ld_align_sign_bit_16 = M_mem_baddr[1] ? 
+    {M_ram_rd_data[31], M_ram_rd_data[23]} : 
+    {M_ram_rd_data[15], M_ram_rd_data[7]};
+
+  assign M_data_ram_ld_align_sign_bit = M_data_ram_ld_align_sign_bit_16_hi ?
+    M_data_ram_ld_align_sign_bit_16[1] : 
+    M_data_ram_ld_align_sign_bit_16[0];
+
+  assign A_data_ram_ld_align_fill_bit = A_data_ram_ld_align_sign_bit & A_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_data_ram_ld_align_sign_bit <= 0;
+      else if (A_en)
+          A_data_ram_ld_align_sign_bit <= M_data_ram_ld_align_sign_bit;
+    end
+
+
+  assign A_data_ram_ld16_data = A_ld_align_sh16 ? 
+    A_inst_result[31 : 16] :
+    A_inst_result[15 : 0];
+
+  assign A_data_ram_ld_byte0_data = A_ld_align_sh8 ? 
+    A_data_ram_ld16_data[15 : 8] :
+    A_data_ram_ld16_data[7 : 0];
+
+  assign A_data_ram_ld_byte1_data = A_ld_align_byte1_fill ? 
+    {8 {A_data_ram_ld_align_fill_bit}} : 
+    A_data_ram_ld16_data[15 : 8];
+
+  assign A_data_ram_ld_byte2_data = A_ld_align_byte2_byte3_fill ? 
+    {8 {A_data_ram_ld_align_fill_bit}} : 
+    A_inst_result[23 : 16];
+
+  assign A_data_ram_ld_byte3_data = A_ld_align_byte2_byte3_fill ? 
+    {8 {A_data_ram_ld_align_fill_bit}} : 
+    A_inst_result[31 : 24];
+
+  assign A_inst_result_aligned = {A_data_ram_ld_byte3_data, A_data_ram_ld_byte2_data, 
+    A_data_ram_ld_byte1_data, A_data_ram_ld_byte0_data};
+
+  assign W_status_reg_crs = 1'b0;
+  assign W_status_reg_prs = 1'b0;
+  assign D_ctrl_rdprs = 1'b0;
+  altera_nios2_gen2_rtl_module the_nios2_rtl
+    (
+      .A_cancel (A_cancel),
+      .A_ctrl_ld16 (A_ctrl_ld16),
+      .A_ctrl_ld32 (A_ctrl_ld32),
+      .A_ctrl_ld8 (A_ctrl_ld8),
+      .A_ctrl_ld_signed (A_ctrl_ld_signed),
+      .A_dst_regnum (A_dst_regnum),
+      .A_dst_regnum_from_M (A_dst_regnum_from_M),
+      .A_en (A_en),
+      .A_exc_any (A_exc_any),
+      .A_exc_break (A_exc_break),
+      .A_exc_break_active (A_exc_break_active),
+      .A_exc_shadow_active (A_exc_shadow_active),
+      .A_exc_wr_ea_ba (A_exc_wr_ea_ba),
+      .A_exc_wr_sstatus (A_exc_wr_sstatus),
+      .A_ld_align_byte1_fill (A_ld_align_byte1_fill),
+      .A_ld_align_byte2_byte3_fill (A_ld_align_byte2_byte3_fill),
+      .A_ld_align_sh16 (A_ld_align_sh16),
+      .A_ld_align_sh8 (A_ld_align_sh8),
+      .A_mem_baddr (A_mem_baddr[1 : 0]),
+      .A_op_bret (A_op_bret),
+      .A_pipe_flush (A_pipe_flush),
+      .A_refetch_required (A_refetch_required),
+      .A_slow_ld_data_aligned_nxt (A_slow_ld_data_aligned_nxt),
+      .A_valid (A_valid),
+      .A_wr_dst_reg (A_wr_dst_reg),
+      .A_wr_dst_reg_from_M (A_wr_dst_reg_from_M),
+      .D_ctrl_a_not_src (D_ctrl_a_not_src),
+      .D_ctrl_b_is_dst (D_ctrl_b_is_dst),
+      .D_ctrl_b_not_src (D_ctrl_b_not_src),
+      .D_ctrl_ignore_dst (D_ctrl_ignore_dst),
+      .D_ctrl_implicit_dst_eretaddr (D_ctrl_implicit_dst_eretaddr),
+      .D_ctrl_implicit_dst_retaddr (D_ctrl_implicit_dst_retaddr),
+      .D_ctrl_rdprs (D_ctrl_rdprs),
+      .D_data_depend (D_data_depend),
+      .D_dst_regnum (D_dst_regnum),
+      .D_en (D_en),
+      .D_iw_b (D_iw_b),
+      .D_iw_c (D_iw_c),
+      .D_src1_choose_A (D_src1_choose_A),
+      .D_src1_choose_E (D_src1_choose_E),
+      .D_src1_choose_M (D_src1_choose_M),
+      .D_src1_choose_W (D_src1_choose_W),
+      .D_src2_choose_A (D_src2_choose_A),
+      .D_src2_choose_E (D_src2_choose_E),
+      .D_src2_choose_M (D_src2_choose_M),
+      .D_src2_choose_W (D_src2_choose_W),
+      .D_valid (D_valid),
+      .D_wr_dst_reg (D_wr_dst_reg),
+      .E_ctrl_a_is_src (E_ctrl_a_is_src),
+      .E_ctrl_a_not_src (E_ctrl_a_not_src),
+      .E_ctrl_b_is_src (E_ctrl_b_is_src),
+      .E_ctrl_b_not_src (E_ctrl_b_not_src),
+      .E_ctrl_late_result (E_ctrl_late_result),
+      .E_dst_regnum (E_dst_regnum),
+      .E_en (E_en),
+      .E_src1_from_rf (E_src1_from_rf),
+      .E_src2_from_rf (E_src2_from_rf),
+      .E_wr_dst_reg (E_wr_dst_reg),
+      .F_iw_a (F_iw_a),
+      .F_iw_b (F_iw_b),
+      .M_ctrl_late_result (M_ctrl_late_result),
+      .M_dst_regnum (M_dst_regnum),
+      .M_en (M_en),
+      .M_exc_any (M_exc_any),
+      .M_refetch (M_refetch),
+      .M_valid (M_valid),
+      .M_valid_from_E (M_valid_from_E),
+      .M_valid_ignoring_refetch (M_valid_ignoring_refetch),
+      .M_wr_dst_reg (M_wr_dst_reg),
+      .M_wr_dst_reg_from_E (M_wr_dst_reg_from_E),
+      .W_debug_mode (W_debug_mode),
+      .W_debug_mode_nxt (W_debug_mode_nxt),
+      .W_exc_handler_mode (W_exc_handler_mode),
+      .W_exc_wr_sstatus (W_exc_wr_sstatus),
+      .W_status_reg_crs (W_status_reg_crs),
+      .W_status_reg_prs (W_status_reg_prs),
+      .clk (clk),
+      .d_readdata_d1 (d_readdata_d1),
+      .reset_n (reset_n)
+    );
+
+  defparam the_nios2_rtl.SHADOW_PRESENT = 0,
+           the_nios2_rtl.SHADOW_REGISTER_SET_SIZE = 1;
+
+  //custom_instruction_master, which is an e_custom_instruction_master
+  assign dummy_ci_port = 1'b0;
+  assign E_src1_eq_src2 = E_logic_result == 0;
+  assign A_eret_src = W_estatus_reg[0];
+  assign W_status_reg_pie_inst_nxt = A_op_eret         ? A_eret_src :
+    A_op_bret         ? W_bstatus_reg[0] :
+    A_wrctl_status    ? A_wrctl_data_status_reg_pie :
+    W_status_reg_pie;
+
+  assign W_estatus_reg_pie_inst_nxt = A_wrctl_estatus ? A_wrctl_data_estatus_reg_pie:
+    W_estatus_reg_pie;
+
+  assign W_bstatus_reg_pie_inst_nxt = A_wrctl_bstatus ? A_wrctl_data_bstatus_reg_pie:
+    W_bstatus_reg_pie;
+
+  assign A_wrctl_status = A_ctrl_wrctl_inst & (A_iw_control_regnum == 0);
+  assign A_wrctl_estatus = A_ctrl_wrctl_inst & (A_iw_control_regnum == 1);
+  assign A_wrctl_bstatus = A_ctrl_wrctl_inst & (A_iw_control_regnum == 2);
+  assign A_wrctl_ienable = A_ctrl_wrctl_inst & (A_iw_control_regnum == 3);
+  assign A_wrctl_cdsr = A_ctrl_wrctl_inst & (A_iw_control_regnum == 31);
+  assign A_wrctl_data_status_reg_pie = A_inst_result[0];
+  assign A_wrctl_data_estatus_reg_pie = A_inst_result[0];
+  assign A_wrctl_data_bstatus_reg_pie = A_inst_result[0];
+  assign A_wrctl_data_ienable_reg_irq0 = A_inst_result[0];
+  assign A_wrctl_data_ienable_reg_irq2 = A_inst_result[2];
+  assign A_wrctl_data_ienable_reg_irq3 = A_inst_result[3];
+  assign A_wrctl_data_ienable_reg_irq4 = A_inst_result[4];
+  assign A_wrctl_data_ienable_reg_irq5 = A_inst_result[5];
+  assign A_wrctl_data_cdsr_reg_status = A_inst_result[31 : 0];
+  assign W_status_reg_pie_nxt = A_exc_any_active  ? 1'b0 :
+    A_valid           ? W_status_reg_pie_inst_nxt : 
+    W_status_reg_pie;
+
+  assign W_status_reg_pie_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_status_reg_pie <= 0;
+      else if (W_status_reg_pie_wr_en)
+          W_status_reg_pie <= W_status_reg_pie_nxt;
+    end
+
+
+  assign W_estatus_reg_pie_nxt = A_exc_crst_active ? 0 :
+    (A_exc_active_no_break & ~A_exc_shadow &
+    ~W_exc_handler_mode) ? W_status_reg_pie :
+    A_valid           ? W_estatus_reg_pie_inst_nxt : 
+    W_estatus_reg_pie;
+
+  assign W_estatus_reg_pie_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_estatus_reg_pie <= 0;
+      else if (W_estatus_reg_pie_wr_en)
+          W_estatus_reg_pie <= W_estatus_reg_pie_nxt;
+    end
+
+
+  assign W_bstatus_reg_pie_nxt = A_exc_break_active ? W_status_reg_pie :
+    A_valid            ? W_bstatus_reg_pie_inst_nxt :
+    W_bstatus_reg_pie;
+
+  assign W_bstatus_reg_pie_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_bstatus_reg_pie <= 0;
+      else if (W_bstatus_reg_pie_wr_en)
+          W_bstatus_reg_pie <= W_bstatus_reg_pie_nxt;
+    end
+
+
+  assign W_ienable_reg_irq0_nxt = (A_wrctl_ienable & A_valid) ? 
+    A_wrctl_data_ienable_reg_irq0 :
+    W_ienable_reg_irq0;
+
+  assign W_ienable_reg_irq0_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg_irq0 <= 0;
+      else if (W_ienable_reg_irq0_wr_en)
+          W_ienable_reg_irq0 <= W_ienable_reg_irq0_nxt;
+    end
+
+
+  assign W_ienable_reg_irq2_nxt = (A_wrctl_ienable & A_valid) ? 
+    A_wrctl_data_ienable_reg_irq2 :
+    W_ienable_reg_irq2;
+
+  assign W_ienable_reg_irq2_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg_irq2 <= 0;
+      else if (W_ienable_reg_irq2_wr_en)
+          W_ienable_reg_irq2 <= W_ienable_reg_irq2_nxt;
+    end
+
+
+  assign W_ienable_reg_irq3_nxt = (A_wrctl_ienable & A_valid) ? 
+    A_wrctl_data_ienable_reg_irq3 :
+    W_ienable_reg_irq3;
+
+  assign W_ienable_reg_irq3_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg_irq3 <= 0;
+      else if (W_ienable_reg_irq3_wr_en)
+          W_ienable_reg_irq3 <= W_ienable_reg_irq3_nxt;
+    end
+
+
+  assign W_ienable_reg_irq4_nxt = (A_wrctl_ienable & A_valid) ? 
+    A_wrctl_data_ienable_reg_irq4 :
+    W_ienable_reg_irq4;
+
+  assign W_ienable_reg_irq4_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg_irq4 <= 0;
+      else if (W_ienable_reg_irq4_wr_en)
+          W_ienable_reg_irq4 <= W_ienable_reg_irq4_nxt;
+    end
+
+
+  assign W_ienable_reg_irq5_nxt = (A_wrctl_ienable & A_valid) ? 
+    A_wrctl_data_ienable_reg_irq5 :
+    W_ienable_reg_irq5;
+
+  assign W_ienable_reg_irq5_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg_irq5 <= 0;
+      else if (W_ienable_reg_irq5_wr_en)
+          W_ienable_reg_irq5 <= W_ienable_reg_irq5_nxt;
+    end
+
+
+  assign W_ipending_reg_irq0_nxt = irq[0] & W_ienable_reg_irq0 & oci_ienable[0];
+  assign W_ipending_reg_irq0_wr_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg_irq0 <= 0;
+      else if (W_ipending_reg_irq0_wr_en)
+          W_ipending_reg_irq0 <= W_ipending_reg_irq0_nxt;
+    end
+
+
+  assign W_ipending_reg_irq2_nxt = irq[2] & W_ienable_reg_irq2 & oci_ienable[2];
+  assign W_ipending_reg_irq2_wr_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg_irq2 <= 0;
+      else if (W_ipending_reg_irq2_wr_en)
+          W_ipending_reg_irq2 <= W_ipending_reg_irq2_nxt;
+    end
+
+
+  assign W_ipending_reg_irq3_nxt = irq[3] & W_ienable_reg_irq3 & oci_ienable[3];
+  assign W_ipending_reg_irq3_wr_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg_irq3 <= 0;
+      else if (W_ipending_reg_irq3_wr_en)
+          W_ipending_reg_irq3 <= W_ipending_reg_irq3_nxt;
+    end
+
+
+  assign W_ipending_reg_irq4_nxt = irq[4] & W_ienable_reg_irq4 & oci_ienable[4];
+  assign W_ipending_reg_irq4_wr_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg_irq4 <= 0;
+      else if (W_ipending_reg_irq4_wr_en)
+          W_ipending_reg_irq4 <= W_ipending_reg_irq4_nxt;
+    end
+
+
+  assign W_ipending_reg_irq5_nxt = irq[5] & W_ienable_reg_irq5 & oci_ienable[5];
+  assign W_ipending_reg_irq5_wr_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg_irq5 <= 0;
+      else if (W_ipending_reg_irq5_wr_en)
+          W_ipending_reg_irq5 <= W_ipending_reg_irq5_nxt;
+    end
+
+
+  assign W_exception_reg_cause_nxt = (A_exc_active_no_break & 
+    ~A_exc_ext_intr_active) ? 
+    A_exc_highest_pri_cause_code :
+    W_exception_reg_cause;
+
+  assign W_exception_reg_cause_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exception_reg_cause <= 0;
+      else if (W_exception_reg_cause_wr_en)
+          W_exception_reg_cause <= W_exception_reg_cause_nxt;
+    end
+
+
+  assign W_badaddr_reg_baddr_nxt = A_exc_crst_active  ? 0 :
+    A_exc_record_baddr ? A_exc_highest_pri_baddr :
+    W_badaddr_reg_baddr;
+
+  assign W_badaddr_reg_baddr_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_badaddr_reg_baddr <= 0;
+      else if (W_badaddr_reg_baddr_wr_en)
+          W_badaddr_reg_baddr <= W_badaddr_reg_baddr_nxt;
+    end
+
+
+  assign W_cdsr_reg_status_nxt = 0;
+  assign W_cdsr_reg_status_wr_en = W_en;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_cdsr_reg_status <= 0;
+      else if (W_cdsr_reg_status_wr_en)
+          W_cdsr_reg_status <= W_cdsr_reg_status_nxt;
+    end
+
+
+  assign W_status_reg = { 31'd0, W_status_reg_pie };
+  assign W_estatus_reg = { 31'd0, W_estatus_reg_pie };
+  assign W_bstatus_reg = { 31'd0, W_bstatus_reg_pie };
+  assign W_ienable_reg = { 26'd0, W_ienable_reg_irq5, W_ienable_reg_irq4, W_ienable_reg_irq3, W_ienable_reg_irq2, 1'd0, W_ienable_reg_irq0 };
+  assign W_ipending_reg = { 26'd0, W_ipending_reg_irq5, W_ipending_reg_irq4, W_ipending_reg_irq3, W_ipending_reg_irq2, 1'd0, W_ipending_reg_irq0 };
+  assign W_cpuid_reg = { 31'd0, 1'd0 };
+  assign W_exception_reg = { 25'd0, W_exception_reg_cause, 2'd0 };
+  assign W_badaddr_reg = { 3'd0, W_badaddr_reg_baddr };
+  assign W_cdsr_reg = { W_cdsr_reg_status };
+  assign D_control_reg_rddata_muxed = (D_iw_control_regnum == 5'd0)? W_status_reg :
+    (D_iw_control_regnum == 5'd1)? W_estatus_reg :
+    (D_iw_control_regnum == 5'd2)? W_bstatus_reg :
+    (D_iw_control_regnum == 5'd3)? W_ienable_reg :
+    (D_iw_control_regnum == 5'd4)? W_ipending_reg :
+    (D_iw_control_regnum == 5'd5)? W_cpuid_reg :
+    W_cdsr_reg;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_control_reg_rddata <= 0;
+      else if (E_en)
+          E_control_reg_rddata <= D_control_reg_rddata_muxed;
+    end
+
+
+  assign E_control_reg_rddata_muxed = (E_iw_control_regnum == 5'd7)? W_exception_reg :
+    (E_iw_control_regnum == 5'd12)? W_badaddr_reg :
+    E_control_reg_rddata;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_control_reg_rddata <= 0;
+      else if (M_en)
+          M_control_reg_rddata <= E_control_reg_rddata_muxed;
+    end
+
+
+  assign M_rdctl_data = M_control_reg_rddata;
+  q_sys_cpu_cpu_nios2_oci the_q_sys_cpu_cpu_nios2_oci
+    (
+      .A_cmp_result                        (A_cmp_result),
+      .A_ctrl_ld                           (A_ctrl_ld),
+      .A_ctrl_st                           (A_ctrl_st),
+      .A_en                                (A_en),
+      .A_exc_active_no_break_no_crst       (A_exc_active_no_break_no_crst),
+      .A_exc_active_no_crst                (A_exc_active_no_crst),
+      .A_exc_addr                          (A_exc_addr),
+      .A_ld_data                           (A_ld_data),
+      .A_mem_baddr                         (A_mem_baddr),
+      .A_op_beq                            (A_op_beq),
+      .A_op_bge                            (A_op_bge),
+      .A_op_bgeu                           (A_op_bgeu),
+      .A_op_blt                            (A_op_blt),
+      .A_op_bltu                           (A_op_bltu),
+      .A_op_bne                            (A_op_bne),
+      .A_op_br                             (A_op_br),
+      .A_op_bret                           (A_op_bret),
+      .A_op_call                           (A_op_call),
+      .A_op_callr                          (A_op_callr),
+      .A_op_eret                           (A_op_eret),
+      .A_op_jmp                            (A_op_jmp),
+      .A_op_jmpi                           (A_op_jmpi),
+      .A_op_ret                            (A_op_ret),
+      .A_pcb                               (A_pcb),
+      .A_st_data                           (A_st_data),
+      .A_valid                             (A_valid),
+      .D_en                                (D_en),
+      .E_en                                (E_en),
+      .E_oci_sync_hbreak_req               (E_oci_sync_hbreak_req),
+      .E_valid                             (E_valid),
+      .F_pc                                (F_pc),
+      .M_en                                (M_en),
+      .address_nxt                         (debug_mem_slave_address),
+      .byteenable_nxt                      (debug_mem_slave_byteenable),
+      .clk                                 (debug_mem_slave_clk),
+      .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
+      .debugaccess_nxt                     (debug_mem_slave_debugaccess),
+      .hbreak_enabled                      (hbreak_enabled),
+      .oci_async_hbreak_req                (oci_async_hbreak_req),
+      .oci_ienable                         (oci_ienable),
+      .oci_single_step_mode                (oci_single_step_mode),
+      .read_nxt                            (debug_mem_slave_read),
+      .readdata                            (debug_mem_slave_readdata),
+      .reset                               (debug_mem_slave_reset),
+      .reset_n                             (reset_n),
+      .reset_req                           (reset_req),
+      .resetrequest                        (debug_reset_request),
+      .waitrequest                         (debug_mem_slave_waitrequest),
+      .write_nxt                           (debug_mem_slave_write),
+      .writedata_nxt                       (debug_mem_slave_writedata)
+    );
+
+  //debug_mem_slave, which is an e_avalon_slave
+  assign debug_mem_slave_clk = clk;
+  assign debug_mem_slave_reset = ~reset_n;
+  assign D_ctrl_unimp_trap = D_op_div|D_op_divu|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
+  assign E_ctrl_unimp_trap_nxt = D_ctrl_unimp_trap;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_unimp_trap <= 0;
+      else if (E_en)
+          E_ctrl_unimp_trap <= E_ctrl_unimp_trap_nxt;
+    end
+
+
+  assign M_ctrl_unimp_trap_nxt = E_ctrl_unimp_trap;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_unimp_trap <= 0;
+      else if (M_en)
+          M_ctrl_unimp_trap <= M_ctrl_unimp_trap_nxt;
+    end
+
+
+  assign A_ctrl_unimp_trap_nxt = M_ctrl_unimp_trap;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_unimp_trap <= 0;
+      else if (A_en)
+          A_ctrl_unimp_trap <= A_ctrl_unimp_trap_nxt;
+    end
+
+
+  assign W_ctrl_unimp_trap_nxt = A_ctrl_unimp_trap;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_unimp_trap <= 0;
+      else if (W_en)
+          W_ctrl_unimp_trap <= W_ctrl_unimp_trap_nxt;
+    end
+
+
+  assign D_ctrl_unimp_nop = 1'b0;
+  assign E_ctrl_unimp_nop_nxt = D_ctrl_unimp_nop;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_unimp_nop <= 0;
+      else if (E_en)
+          E_ctrl_unimp_nop <= E_ctrl_unimp_nop_nxt;
+    end
+
+
+  assign M_ctrl_unimp_nop_nxt = E_ctrl_unimp_nop;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_unimp_nop <= 0;
+      else if (M_en)
+          M_ctrl_unimp_nop <= M_ctrl_unimp_nop_nxt;
+    end
+
+
+  assign A_ctrl_unimp_nop_nxt = M_ctrl_unimp_nop;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_unimp_nop <= 0;
+      else if (A_en)
+          A_ctrl_unimp_nop <= A_ctrl_unimp_nop_nxt;
+    end
+
+
+  assign W_ctrl_unimp_nop_nxt = A_ctrl_unimp_nop;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_unimp_nop <= 0;
+      else if (W_en)
+          W_ctrl_unimp_nop <= W_ctrl_unimp_nop_nxt;
+    end
+
+
+  assign D_ctrl_illegal = D_op_crst|
+    D_op_hbreak|
+    D_op_intr|
+    D_op_ldl|
+    D_op_op_rsv02|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv44|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs;
+
+  assign E_ctrl_illegal_nxt = D_ctrl_illegal;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_illegal <= 0;
+      else if (E_en)
+          E_ctrl_illegal <= E_ctrl_illegal_nxt;
+    end
+
+
+  assign M_ctrl_illegal_nxt = E_ctrl_illegal;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_illegal <= 0;
+      else if (M_en)
+          M_ctrl_illegal <= M_ctrl_illegal_nxt;
+    end
+
+
+  assign A_ctrl_illegal_nxt = M_ctrl_illegal;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_illegal <= 0;
+      else if (A_en)
+          A_ctrl_illegal <= A_ctrl_illegal_nxt;
+    end
+
+
+  assign W_ctrl_illegal_nxt = A_ctrl_illegal;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_illegal <= 0;
+      else if (W_en)
+          W_ctrl_illegal <= W_ctrl_illegal_nxt;
+    end
+
+
+  assign D_ctrl_trap_inst = D_op_trap;
+  assign E_ctrl_trap_inst_nxt = D_ctrl_trap_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_trap_inst <= 0;
+      else if (E_en)
+          E_ctrl_trap_inst <= E_ctrl_trap_inst_nxt;
+    end
+
+
+  assign M_ctrl_trap_inst_nxt = E_ctrl_trap_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_trap_inst <= 0;
+      else if (M_en)
+          M_ctrl_trap_inst <= M_ctrl_trap_inst_nxt;
+    end
+
+
+  assign A_ctrl_trap_inst_nxt = M_ctrl_trap_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_trap_inst <= 0;
+      else if (A_en)
+          A_ctrl_trap_inst <= A_ctrl_trap_inst_nxt;
+    end
+
+
+  assign W_ctrl_trap_inst_nxt = A_ctrl_trap_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_trap_inst <= 0;
+      else if (W_en)
+          W_ctrl_trap_inst <= W_ctrl_trap_inst_nxt;
+    end
+
+
+  assign D_ctrl_custom_combo = 1'b0;
+  assign E_ctrl_custom_combo_nxt = D_ctrl_custom_combo;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_custom_combo <= 0;
+      else if (E_en)
+          E_ctrl_custom_combo <= E_ctrl_custom_combo_nxt;
+    end
+
+
+  assign M_ctrl_custom_combo_nxt = E_ctrl_custom_combo;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_custom_combo <= 0;
+      else if (M_en)
+          M_ctrl_custom_combo <= M_ctrl_custom_combo_nxt;
+    end
+
+
+  assign A_ctrl_custom_combo_nxt = M_ctrl_custom_combo;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_custom_combo <= 0;
+      else if (A_en)
+          A_ctrl_custom_combo <= A_ctrl_custom_combo_nxt;
+    end
+
+
+  assign W_ctrl_custom_combo_nxt = A_ctrl_custom_combo;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_custom_combo <= 0;
+      else if (W_en)
+          W_ctrl_custom_combo <= W_ctrl_custom_combo_nxt;
+    end
+
+
+  assign D_ctrl_custom_multi = 1'b0;
+  assign E_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_custom_multi <= 0;
+      else if (E_en)
+          E_ctrl_custom_multi <= E_ctrl_custom_multi_nxt;
+    end
+
+
+  assign M_ctrl_custom_multi_nxt = E_ctrl_custom_multi;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_custom_multi <= 0;
+      else if (M_en)
+          M_ctrl_custom_multi <= M_ctrl_custom_multi_nxt;
+    end
+
+
+  assign A_ctrl_custom_multi_nxt = M_ctrl_custom_multi;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_custom_multi <= 0;
+      else if (A_en)
+          A_ctrl_custom_multi <= A_ctrl_custom_multi_nxt;
+    end
+
+
+  assign W_ctrl_custom_multi_nxt = A_ctrl_custom_multi;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_custom_multi <= 0;
+      else if (W_en)
+          W_ctrl_custom_multi <= W_ctrl_custom_multi_nxt;
+    end
+
+
+  assign D_ctrl_supervisor_only = D_op_initi|D_op_initd|D_op_eret|D_op_bret|D_op_wrctl|D_op_rdctl;
+  assign E_ctrl_supervisor_only_nxt = D_ctrl_supervisor_only;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_supervisor_only <= 0;
+      else if (E_en)
+          E_ctrl_supervisor_only <= E_ctrl_supervisor_only_nxt;
+    end
+
+
+  assign M_ctrl_supervisor_only_nxt = E_ctrl_supervisor_only;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_supervisor_only <= 0;
+      else if (M_en)
+          M_ctrl_supervisor_only <= M_ctrl_supervisor_only_nxt;
+    end
+
+
+  assign A_ctrl_supervisor_only_nxt = M_ctrl_supervisor_only;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_supervisor_only <= 0;
+      else if (A_en)
+          A_ctrl_supervisor_only <= A_ctrl_supervisor_only_nxt;
+    end
+
+
+  assign W_ctrl_supervisor_only_nxt = A_ctrl_supervisor_only;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_supervisor_only <= 0;
+      else if (W_en)
+          W_ctrl_supervisor_only <= W_ctrl_supervisor_only_nxt;
+    end
+
+
+  assign E_ctrl_invalidate_i = E_op_initi|E_op_flushi|E_op_crst|E_op_opx_rsv63;
+  assign M_ctrl_invalidate_i_nxt = E_ctrl_invalidate_i;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_invalidate_i <= 0;
+      else if (M_en)
+          M_ctrl_invalidate_i <= M_ctrl_invalidate_i_nxt;
+    end
+
+
+  assign A_ctrl_invalidate_i_nxt = M_ctrl_invalidate_i;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_invalidate_i <= 0;
+      else if (A_en)
+          A_ctrl_invalidate_i <= A_ctrl_invalidate_i_nxt;
+    end
+
+
+  assign W_ctrl_invalidate_i_nxt = A_ctrl_invalidate_i;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_invalidate_i <= 0;
+      else if (W_en)
+          W_ctrl_invalidate_i <= W_ctrl_invalidate_i_nxt;
+    end
+
+
+  assign D_ctrl_jmp_indirect = D_op_eret|
+    D_op_bret|
+    D_op_opx_rsv17|
+    D_op_opx_rsv25|
+    D_op_ret|
+    D_op_jmp|
+    D_op_opx_rsv21|
+    D_op_callr;
+
+  assign E_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_jmp_indirect <= 0;
+      else if (E_en)
+          E_ctrl_jmp_indirect <= E_ctrl_jmp_indirect_nxt;
+    end
+
+
+  assign M_ctrl_jmp_indirect_nxt = E_ctrl_jmp_indirect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_jmp_indirect <= 0;
+      else if (M_en)
+          M_ctrl_jmp_indirect <= M_ctrl_jmp_indirect_nxt;
+    end
+
+
+  assign A_ctrl_jmp_indirect_nxt = M_ctrl_jmp_indirect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_jmp_indirect <= 0;
+      else if (A_en)
+          A_ctrl_jmp_indirect <= A_ctrl_jmp_indirect_nxt;
+    end
+
+
+  assign W_ctrl_jmp_indirect_nxt = A_ctrl_jmp_indirect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_jmp_indirect <= 0;
+      else if (W_en)
+          W_ctrl_jmp_indirect <= W_ctrl_jmp_indirect_nxt;
+    end
+
+
+  assign F_ctrl_jmp_direct = F_op_call|F_op_jmpi;
+  assign D_ctrl_jmp_direct_nxt = F_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_jmp_direct <= 0;
+      else if (D_en)
+          D_ctrl_jmp_direct <= D_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign E_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_jmp_direct <= 0;
+      else if (E_en)
+          E_ctrl_jmp_direct <= E_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign M_ctrl_jmp_direct_nxt = E_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_jmp_direct <= 0;
+      else if (M_en)
+          M_ctrl_jmp_direct <= M_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign A_ctrl_jmp_direct_nxt = M_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_jmp_direct <= 0;
+      else if (A_en)
+          A_ctrl_jmp_direct <= A_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign W_ctrl_jmp_direct_nxt = A_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_jmp_direct <= 0;
+      else if (W_en)
+          W_ctrl_jmp_direct <= W_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign D_ctrl_mul_lsw = D_op_muli|D_op_mul|D_op_opx_rsv47|D_op_opx_rsv55|D_op_opx_rsv63;
+  assign E_ctrl_mul_lsw_nxt = D_ctrl_mul_lsw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_mul_lsw <= 0;
+      else if (E_en)
+          E_ctrl_mul_lsw <= E_ctrl_mul_lsw_nxt;
+    end
+
+
+  assign M_ctrl_mul_lsw_nxt = E_ctrl_mul_lsw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mul_lsw <= 0;
+      else if (M_en)
+          M_ctrl_mul_lsw <= M_ctrl_mul_lsw_nxt;
+    end
+
+
+  assign A_ctrl_mul_lsw_nxt = M_ctrl_mul_lsw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mul_lsw <= 0;
+      else if (A_en)
+          A_ctrl_mul_lsw <= A_ctrl_mul_lsw_nxt;
+    end
+
+
+  assign W_ctrl_mul_lsw_nxt = A_ctrl_mul_lsw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mul_lsw <= 0;
+      else if (W_en)
+          W_ctrl_mul_lsw <= W_ctrl_mul_lsw_nxt;
+    end
+
+
+  assign F_ctrl_implicit_dst_retaddr = F_op_call|F_op_op_rsv02;
+  assign D_ctrl_implicit_dst_retaddr_nxt = F_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_implicit_dst_retaddr <= 0;
+      else if (D_en)
+          D_ctrl_implicit_dst_retaddr <= D_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign E_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_implicit_dst_retaddr <= 0;
+      else if (E_en)
+          E_ctrl_implicit_dst_retaddr <= E_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign M_ctrl_implicit_dst_retaddr_nxt = E_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_implicit_dst_retaddr <= 0;
+      else if (M_en)
+          M_ctrl_implicit_dst_retaddr <= M_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign A_ctrl_implicit_dst_retaddr_nxt = M_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_implicit_dst_retaddr <= 0;
+      else if (A_en)
+          A_ctrl_implicit_dst_retaddr <= A_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign W_ctrl_implicit_dst_retaddr_nxt = A_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_implicit_dst_retaddr <= 0;
+      else if (W_en)
+          W_ctrl_implicit_dst_retaddr <= W_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign F_ctrl_implicit_dst_eretaddr = F_op_div|
+    F_op_divu|
+    F_op_mulxss|
+    F_op_mulxsu|
+    F_op_mulxuu|
+    F_op_crst|
+    F_op_hbreak|
+    F_op_intr|
+    F_op_ldl|
+    F_op_op_rsv02|
+    F_op_op_rsv09|
+    F_op_op_rsv10|
+    F_op_op_rsv17|
+    F_op_op_rsv18|
+    F_op_op_rsv25|
+    F_op_op_rsv26|
+    F_op_op_rsv33|
+    F_op_op_rsv34|
+    F_op_op_rsv41|
+    F_op_op_rsv42|
+    F_op_op_rsv49|
+    F_op_op_rsv57|
+    F_op_op_rsv61|
+    F_op_op_rsv62|
+    F_op_op_rsv63|
+    F_op_opx_rsv00|
+    F_op_opx_rsv10|
+    F_op_opx_rsv15|
+    F_op_opx_rsv17|
+    F_op_opx_rsv21|
+    F_op_opx_rsv25|
+    F_op_opx_rsv33|
+    F_op_opx_rsv34|
+    F_op_opx_rsv35|
+    F_op_opx_rsv42|
+    F_op_opx_rsv43|
+    F_op_opx_rsv44|
+    F_op_opx_rsv47|
+    F_op_opx_rsv50|
+    F_op_opx_rsv51|
+    F_op_opx_rsv55|
+    F_op_opx_rsv56|
+    F_op_opx_rsv60|
+    F_op_opx_rsv63|
+    F_op_rdprs|
+    F_op_stc|
+    F_op_wrprs;
+
+  assign D_ctrl_implicit_dst_eretaddr_nxt = F_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_implicit_dst_eretaddr <= 0;
+      else if (D_en)
+          D_ctrl_implicit_dst_eretaddr <= D_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign E_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_implicit_dst_eretaddr <= 0;
+      else if (E_en)
+          E_ctrl_implicit_dst_eretaddr <= E_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign M_ctrl_implicit_dst_eretaddr_nxt = E_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_implicit_dst_eretaddr <= 0;
+      else if (M_en)
+          M_ctrl_implicit_dst_eretaddr <= M_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign A_ctrl_implicit_dst_eretaddr_nxt = M_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_implicit_dst_eretaddr <= 0;
+      else if (A_en)
+          A_ctrl_implicit_dst_eretaddr <= A_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign W_ctrl_implicit_dst_eretaddr_nxt = A_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_implicit_dst_eretaddr <= 0;
+      else if (W_en)
+          W_ctrl_implicit_dst_eretaddr <= W_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign D_ctrl_exception = D_op_trap|
+    D_op_opx_rsv44|
+    D_op_div|
+    D_op_divu|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_hbreak|
+    D_op_intr|
+    D_op_ldl|
+    D_op_op_rsv02|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs;
+
+  assign E_ctrl_exception_nxt = D_ctrl_exception;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_exception <= 0;
+      else if (E_en)
+          E_ctrl_exception <= E_ctrl_exception_nxt;
+    end
+
+
+  assign M_ctrl_exception_nxt = E_ctrl_exception;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_exception <= 0;
+      else if (M_en)
+          M_ctrl_exception <= M_ctrl_exception_nxt;
+    end
+
+
+  assign A_ctrl_exception_nxt = M_ctrl_exception;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_exception <= 0;
+      else if (A_en)
+          A_ctrl_exception <= A_ctrl_exception_nxt;
+    end
+
+
+  assign W_ctrl_exception_nxt = A_ctrl_exception;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_exception <= 0;
+      else if (W_en)
+          W_ctrl_exception <= W_ctrl_exception_nxt;
+    end
+
+
+  assign D_ctrl_break = D_op_break|D_op_hbreak;
+  assign E_ctrl_break_nxt = D_ctrl_break;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_break <= 0;
+      else if (E_en)
+          E_ctrl_break <= E_ctrl_break_nxt;
+    end
+
+
+  assign M_ctrl_break_nxt = E_ctrl_break;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_break <= 0;
+      else if (M_en)
+          M_ctrl_break <= M_ctrl_break_nxt;
+    end
+
+
+  assign A_ctrl_break_nxt = M_ctrl_break;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_break <= 0;
+      else if (A_en)
+          A_ctrl_break <= A_ctrl_break_nxt;
+    end
+
+
+  assign W_ctrl_break_nxt = A_ctrl_break;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_break <= 0;
+      else if (W_en)
+          W_ctrl_break <= W_ctrl_break_nxt;
+    end
+
+
+  assign D_ctrl_crst = D_op_crst|D_op_opx_rsv63;
+  assign E_ctrl_crst_nxt = D_ctrl_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_crst <= 0;
+      else if (E_en)
+          E_ctrl_crst <= E_ctrl_crst_nxt;
+    end
+
+
+  assign M_ctrl_crst_nxt = E_ctrl_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_crst <= 0;
+      else if (M_en)
+          M_ctrl_crst <= M_ctrl_crst_nxt;
+    end
+
+
+  assign A_ctrl_crst_nxt = M_ctrl_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_crst <= 0;
+      else if (A_en)
+          A_ctrl_crst <= A_ctrl_crst_nxt;
+    end
+
+
+  assign W_ctrl_crst_nxt = A_ctrl_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_crst <= 0;
+      else if (W_en)
+          W_ctrl_crst <= W_ctrl_crst_nxt;
+    end
+
+
+  assign E_ctrl_rd_ctl_reg = E_op_rdctl;
+  assign M_ctrl_rd_ctl_reg_nxt = E_ctrl_rd_ctl_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_rd_ctl_reg <= 0;
+      else if (M_en)
+          M_ctrl_rd_ctl_reg <= M_ctrl_rd_ctl_reg_nxt;
+    end
+
+
+  assign A_ctrl_rd_ctl_reg_nxt = M_ctrl_rd_ctl_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_rd_ctl_reg <= 0;
+      else if (A_en)
+          A_ctrl_rd_ctl_reg <= A_ctrl_rd_ctl_reg_nxt;
+    end
+
+
+  assign W_ctrl_rd_ctl_reg_nxt = A_ctrl_rd_ctl_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_rd_ctl_reg <= 0;
+      else if (W_en)
+          W_ctrl_rd_ctl_reg <= W_ctrl_rd_ctl_reg_nxt;
+    end
+
+
+  assign D_ctrl_uncond_cti_non_br = D_op_call|
+    D_op_jmpi|
+    D_op_eret|
+    D_op_bret|
+    D_op_opx_rsv17|
+    D_op_opx_rsv25|
+    D_op_ret|
+    D_op_jmp|
+    D_op_opx_rsv21|
+    D_op_callr;
+
+  assign E_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_uncond_cti_non_br <= 0;
+      else if (E_en)
+          E_ctrl_uncond_cti_non_br <= E_ctrl_uncond_cti_non_br_nxt;
+    end
+
+
+  assign M_ctrl_uncond_cti_non_br_nxt = E_ctrl_uncond_cti_non_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_uncond_cti_non_br <= 0;
+      else if (M_en)
+          M_ctrl_uncond_cti_non_br <= M_ctrl_uncond_cti_non_br_nxt;
+    end
+
+
+  assign A_ctrl_uncond_cti_non_br_nxt = M_ctrl_uncond_cti_non_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_uncond_cti_non_br <= 0;
+      else if (A_en)
+          A_ctrl_uncond_cti_non_br <= A_ctrl_uncond_cti_non_br_nxt;
+    end
+
+
+  assign W_ctrl_uncond_cti_non_br_nxt = A_ctrl_uncond_cti_non_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_uncond_cti_non_br <= 0;
+      else if (W_en)
+          W_ctrl_uncond_cti_non_br <= W_ctrl_uncond_cti_non_br_nxt;
+    end
+
+
+  assign D_ctrl_retaddr = D_op_call|
+    D_op_op_rsv02|
+    D_op_nextpc|
+    D_op_callr|
+    D_op_trap|
+    D_op_opx_rsv44|
+    D_op_div|
+    D_op_divu|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_hbreak|
+    D_op_intr|
+    D_op_ldl|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs|
+    D_op_break;
+
+  assign E_ctrl_retaddr_nxt = D_ctrl_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_retaddr <= 0;
+      else if (E_en)
+          E_ctrl_retaddr <= E_ctrl_retaddr_nxt;
+    end
+
+
+  assign M_ctrl_retaddr_nxt = E_ctrl_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_retaddr <= 0;
+      else if (M_en)
+          M_ctrl_retaddr <= M_ctrl_retaddr_nxt;
+    end
+
+
+  assign A_ctrl_retaddr_nxt = M_ctrl_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_retaddr <= 0;
+      else if (A_en)
+          A_ctrl_retaddr <= A_ctrl_retaddr_nxt;
+    end
+
+
+  assign W_ctrl_retaddr_nxt = A_ctrl_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_retaddr <= 0;
+      else if (W_en)
+          W_ctrl_retaddr <= W_ctrl_retaddr_nxt;
+    end
+
+
+  assign D_ctrl_shift_rot_left = D_op_slli|
+    D_op_opx_rsv50|
+    D_op_sll|
+    D_op_opx_rsv51|
+    D_op_roli|
+    D_op_opx_rsv34|
+    D_op_rol|
+    D_op_opx_rsv35;
+
+  assign E_ctrl_shift_rot_left_nxt = D_ctrl_shift_rot_left;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_shift_rot_left <= 0;
+      else if (E_en)
+          E_ctrl_shift_rot_left <= E_ctrl_shift_rot_left_nxt;
+    end
+
+
+  assign M_ctrl_shift_rot_left_nxt = E_ctrl_shift_rot_left;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_shift_rot_left <= 0;
+      else if (M_en)
+          M_ctrl_shift_rot_left <= M_ctrl_shift_rot_left_nxt;
+    end
+
+
+  assign A_ctrl_shift_rot_left_nxt = M_ctrl_shift_rot_left;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_shift_rot_left <= 0;
+      else if (A_en)
+          A_ctrl_shift_rot_left <= A_ctrl_shift_rot_left_nxt;
+    end
+
+
+  assign W_ctrl_shift_rot_left_nxt = A_ctrl_shift_rot_left;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_shift_rot_left <= 0;
+      else if (W_en)
+          W_ctrl_shift_rot_left <= W_ctrl_shift_rot_left_nxt;
+    end
+
+
+  assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
+  assign E_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_shift_right_arith <= 0;
+      else if (E_en)
+          E_ctrl_shift_right_arith <= E_ctrl_shift_right_arith_nxt;
+    end
+
+
+  assign M_ctrl_shift_right_arith_nxt = E_ctrl_shift_right_arith;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_shift_right_arith <= 0;
+      else if (M_en)
+          M_ctrl_shift_right_arith <= M_ctrl_shift_right_arith_nxt;
+    end
+
+
+  assign A_ctrl_shift_right_arith_nxt = M_ctrl_shift_right_arith;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_shift_right_arith <= 0;
+      else if (A_en)
+          A_ctrl_shift_right_arith <= A_ctrl_shift_right_arith_nxt;
+    end
+
+
+  assign W_ctrl_shift_right_arith_nxt = A_ctrl_shift_right_arith;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_shift_right_arith <= 0;
+      else if (W_en)
+          W_ctrl_shift_right_arith <= W_ctrl_shift_right_arith_nxt;
+    end
+
+
+  assign D_ctrl_shift_rot_right = D_op_srli|
+    D_op_srl|
+    D_op_srai|
+    D_op_sra|
+    D_op_opx_rsv10|
+    D_op_ror|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43;
+
+  assign E_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_shift_rot_right <= 0;
+      else if (E_en)
+          E_ctrl_shift_rot_right <= E_ctrl_shift_rot_right_nxt;
+    end
+
+
+  assign M_ctrl_shift_rot_right_nxt = E_ctrl_shift_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_shift_rot_right <= 0;
+      else if (M_en)
+          M_ctrl_shift_rot_right <= M_ctrl_shift_rot_right_nxt;
+    end
+
+
+  assign A_ctrl_shift_rot_right_nxt = M_ctrl_shift_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_shift_rot_right <= 0;
+      else if (A_en)
+          A_ctrl_shift_rot_right <= A_ctrl_shift_rot_right_nxt;
+    end
+
+
+  assign W_ctrl_shift_rot_right_nxt = A_ctrl_shift_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_shift_rot_right <= 0;
+      else if (W_en)
+          W_ctrl_shift_rot_right <= W_ctrl_shift_rot_right_nxt;
+    end
+
+
+  assign D_ctrl_shift_rot = D_op_slli|
+    D_op_opx_rsv50|
+    D_op_sll|
+    D_op_opx_rsv51|
+    D_op_roli|
+    D_op_opx_rsv34|
+    D_op_rol|
+    D_op_opx_rsv35|
+    D_op_srli|
+    D_op_srl|
+    D_op_srai|
+    D_op_sra|
+    D_op_opx_rsv10|
+    D_op_ror|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43;
+
+  assign E_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_shift_rot <= 0;
+      else if (E_en)
+          E_ctrl_shift_rot <= E_ctrl_shift_rot_nxt;
+    end
+
+
+  assign M_ctrl_shift_rot_nxt = E_ctrl_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_shift_rot <= 0;
+      else if (M_en)
+          M_ctrl_shift_rot <= M_ctrl_shift_rot_nxt;
+    end
+
+
+  assign A_ctrl_shift_rot_nxt = M_ctrl_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_shift_rot <= 0;
+      else if (A_en)
+          A_ctrl_shift_rot <= A_ctrl_shift_rot_nxt;
+    end
+
+
+  assign W_ctrl_shift_rot_nxt = A_ctrl_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_shift_rot <= 0;
+      else if (W_en)
+          W_ctrl_shift_rot <= W_ctrl_shift_rot_nxt;
+    end
+
+
+  assign D_ctrl_rot = D_op_roli|
+    D_op_opx_rsv34|
+    D_op_rol|
+    D_op_opx_rsv35|
+    D_op_opx_rsv10|
+    D_op_ror|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43;
+
+  assign E_ctrl_rot_nxt = D_ctrl_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_rot <= 0;
+      else if (E_en)
+          E_ctrl_rot <= E_ctrl_rot_nxt;
+    end
+
+
+  assign M_ctrl_rot_nxt = E_ctrl_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_rot <= 0;
+      else if (M_en)
+          M_ctrl_rot <= M_ctrl_rot_nxt;
+    end
+
+
+  assign A_ctrl_rot_nxt = M_ctrl_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_rot <= 0;
+      else if (A_en)
+          A_ctrl_rot <= A_ctrl_rot_nxt;
+    end
+
+
+  assign W_ctrl_rot_nxt = A_ctrl_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_rot <= 0;
+      else if (W_en)
+          W_ctrl_rot <= W_ctrl_rot_nxt;
+    end
+
+
+  assign D_ctrl_logic = D_op_and|
+    D_op_or|
+    D_op_xor|
+    D_op_nor|
+    D_op_andhi|
+    D_op_orhi|
+    D_op_xorhi|
+    D_op_andi|
+    D_op_ori|
+    D_op_xori;
+
+  assign E_ctrl_logic_nxt = D_ctrl_logic;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_logic <= 0;
+      else if (E_en)
+          E_ctrl_logic <= E_ctrl_logic_nxt;
+    end
+
+
+  assign M_ctrl_logic_nxt = E_ctrl_logic;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_logic <= 0;
+      else if (M_en)
+          M_ctrl_logic <= M_ctrl_logic_nxt;
+    end
+
+
+  assign A_ctrl_logic_nxt = M_ctrl_logic;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_logic <= 0;
+      else if (A_en)
+          A_ctrl_logic <= A_ctrl_logic_nxt;
+    end
+
+
+  assign W_ctrl_logic_nxt = A_ctrl_logic;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_logic <= 0;
+      else if (W_en)
+          W_ctrl_logic <= W_ctrl_logic_nxt;
+    end
+
+
+  assign F_ctrl_hi_imm16 = F_op_andhi|F_op_orhi|F_op_xorhi;
+  assign D_ctrl_hi_imm16_nxt = F_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_hi_imm16 <= 0;
+      else if (D_en)
+          D_ctrl_hi_imm16 <= D_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign E_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_hi_imm16 <= 0;
+      else if (E_en)
+          E_ctrl_hi_imm16 <= E_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign M_ctrl_hi_imm16_nxt = E_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_hi_imm16 <= 0;
+      else if (M_en)
+          M_ctrl_hi_imm16 <= M_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign A_ctrl_hi_imm16_nxt = M_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_hi_imm16 <= 0;
+      else if (A_en)
+          A_ctrl_hi_imm16 <= A_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign W_ctrl_hi_imm16_nxt = A_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_hi_imm16 <= 0;
+      else if (W_en)
+          W_ctrl_hi_imm16 <= W_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign D_ctrl_set_src2_rem_imm = 1'b0;
+  assign E_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_set_src2_rem_imm <= 0;
+      else if (E_en)
+          E_ctrl_set_src2_rem_imm <= E_ctrl_set_src2_rem_imm_nxt;
+    end
+
+
+  assign M_ctrl_set_src2_rem_imm_nxt = E_ctrl_set_src2_rem_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_set_src2_rem_imm <= 0;
+      else if (M_en)
+          M_ctrl_set_src2_rem_imm <= M_ctrl_set_src2_rem_imm_nxt;
+    end
+
+
+  assign A_ctrl_set_src2_rem_imm_nxt = M_ctrl_set_src2_rem_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_set_src2_rem_imm <= 0;
+      else if (A_en)
+          A_ctrl_set_src2_rem_imm <= A_ctrl_set_src2_rem_imm_nxt;
+    end
+
+
+  assign W_ctrl_set_src2_rem_imm_nxt = A_ctrl_set_src2_rem_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_set_src2_rem_imm <= 0;
+      else if (W_en)
+          W_ctrl_set_src2_rem_imm <= W_ctrl_set_src2_rem_imm_nxt;
+    end
+
+
+  assign F_ctrl_unsigned_lo_imm16 = F_op_cmpgeui|
+    F_op_cmpltui|
+    F_op_andi|
+    F_op_ori|
+    F_op_xori|
+    F_op_roli|
+    F_op_opx_rsv10|
+    F_op_slli|
+    F_op_srli|
+    F_op_opx_rsv34|
+    F_op_opx_rsv42|
+    F_op_opx_rsv50|
+    F_op_srai;
+
+  assign D_ctrl_unsigned_lo_imm16_nxt = F_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_unsigned_lo_imm16 <= 0;
+      else if (D_en)
+          D_ctrl_unsigned_lo_imm16 <= D_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign E_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_unsigned_lo_imm16 <= 0;
+      else if (E_en)
+          E_ctrl_unsigned_lo_imm16 <= E_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign M_ctrl_unsigned_lo_imm16_nxt = E_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_unsigned_lo_imm16 <= 0;
+      else if (M_en)
+          M_ctrl_unsigned_lo_imm16 <= M_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign A_ctrl_unsigned_lo_imm16_nxt = M_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_unsigned_lo_imm16 <= 0;
+      else if (A_en)
+          A_ctrl_unsigned_lo_imm16 <= A_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign W_ctrl_unsigned_lo_imm16_nxt = A_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_unsigned_lo_imm16 <= 0;
+      else if (W_en)
+          W_ctrl_unsigned_lo_imm16 <= W_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign D_ctrl_signed_imm12 = 1'b0;
+  assign E_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_signed_imm12 <= 0;
+      else if (E_en)
+          E_ctrl_signed_imm12 <= E_ctrl_signed_imm12_nxt;
+    end
+
+
+  assign M_ctrl_signed_imm12_nxt = E_ctrl_signed_imm12;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_signed_imm12 <= 0;
+      else if (M_en)
+          M_ctrl_signed_imm12 <= M_ctrl_signed_imm12_nxt;
+    end
+
+
+  assign A_ctrl_signed_imm12_nxt = M_ctrl_signed_imm12;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_signed_imm12 <= 0;
+      else if (A_en)
+          A_ctrl_signed_imm12 <= A_ctrl_signed_imm12_nxt;
+    end
+
+
+  assign W_ctrl_signed_imm12_nxt = A_ctrl_signed_imm12;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_signed_imm12 <= 0;
+      else if (W_en)
+          W_ctrl_signed_imm12 <= W_ctrl_signed_imm12_nxt;
+    end
+
+
+  assign D_ctrl_src_imm5_shift_rot = D_op_roli|
+    D_op_opx_rsv10|
+    D_op_slli|
+    D_op_srli|
+    D_op_opx_rsv34|
+    D_op_opx_rsv42|
+    D_op_opx_rsv50|
+    D_op_srai;
+
+  assign E_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_src_imm5_shift_rot <= 0;
+      else if (E_en)
+          E_ctrl_src_imm5_shift_rot <= E_ctrl_src_imm5_shift_rot_nxt;
+    end
+
+
+  assign M_ctrl_src_imm5_shift_rot_nxt = E_ctrl_src_imm5_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_src_imm5_shift_rot <= 0;
+      else if (M_en)
+          M_ctrl_src_imm5_shift_rot <= M_ctrl_src_imm5_shift_rot_nxt;
+    end
+
+
+  assign A_ctrl_src_imm5_shift_rot_nxt = M_ctrl_src_imm5_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_src_imm5_shift_rot <= 0;
+      else if (A_en)
+          A_ctrl_src_imm5_shift_rot <= A_ctrl_src_imm5_shift_rot_nxt;
+    end
+
+
+  assign W_ctrl_src_imm5_shift_rot_nxt = A_ctrl_src_imm5_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_src_imm5_shift_rot <= 0;
+      else if (W_en)
+          W_ctrl_src_imm5_shift_rot <= W_ctrl_src_imm5_shift_rot_nxt;
+    end
+
+
+  assign D_ctrl_cmp = D_op_cmpgei|
+    D_op_cmplti|
+    D_op_cmpnei|
+    D_op_cmpgeui|
+    D_op_cmpltui|
+    D_op_cmpeqi|
+    D_op_opx_rsv00|
+    D_op_cmpge|
+    D_op_cmplt|
+    D_op_cmpne|
+    D_op_cmpgeu|
+    D_op_cmpltu|
+    D_op_cmpeq|
+    D_op_opx_rsv56;
+
+  assign E_ctrl_cmp_nxt = D_ctrl_cmp;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_cmp <= 0;
+      else if (E_en)
+          E_ctrl_cmp <= E_ctrl_cmp_nxt;
+    end
+
+
+  assign M_ctrl_cmp_nxt = E_ctrl_cmp;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_cmp <= 0;
+      else if (M_en)
+          M_ctrl_cmp <= M_ctrl_cmp_nxt;
+    end
+
+
+  assign A_ctrl_cmp_nxt = M_ctrl_cmp;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_cmp <= 0;
+      else if (A_en)
+          A_ctrl_cmp <= A_ctrl_cmp_nxt;
+    end
+
+
+  assign W_ctrl_cmp_nxt = A_ctrl_cmp;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_cmp <= 0;
+      else if (W_en)
+          W_ctrl_cmp <= W_ctrl_cmp_nxt;
+    end
+
+
+  assign D_ctrl_br_cond = D_op_bge|
+    D_op_op_rsv10|
+    D_op_blt|
+    D_op_bne|
+    D_op_op_rsv62|
+    D_op_bgeu|
+    D_op_op_rsv42|
+    D_op_bltu|
+    D_op_beq|
+    D_op_op_rsv34;
+
+  assign E_ctrl_br_cond_nxt = D_ctrl_br_cond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_br_cond <= 0;
+      else if (E_en)
+          E_ctrl_br_cond <= E_ctrl_br_cond_nxt;
+    end
+
+
+  assign M_ctrl_br_cond_nxt = E_ctrl_br_cond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_br_cond <= 0;
+      else if (M_en)
+          M_ctrl_br_cond <= M_ctrl_br_cond_nxt;
+    end
+
+
+  assign A_ctrl_br_cond_nxt = M_ctrl_br_cond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_br_cond <= 0;
+      else if (A_en)
+          A_ctrl_br_cond <= A_ctrl_br_cond_nxt;
+    end
+
+
+  assign W_ctrl_br_cond_nxt = A_ctrl_br_cond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_br_cond <= 0;
+      else if (W_en)
+          W_ctrl_br_cond <= W_ctrl_br_cond_nxt;
+    end
+
+
+  assign F_ctrl_br_uncond = F_op_br|F_op_op_rsv02;
+  assign D_ctrl_br_uncond_nxt = F_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_br_uncond <= 0;
+      else if (D_en)
+          D_ctrl_br_uncond <= D_ctrl_br_uncond_nxt;
+    end
+
+
+  assign E_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_br_uncond <= 0;
+      else if (E_en)
+          E_ctrl_br_uncond <= E_ctrl_br_uncond_nxt;
+    end
+
+
+  assign M_ctrl_br_uncond_nxt = E_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_br_uncond <= 0;
+      else if (M_en)
+          M_ctrl_br_uncond <= M_ctrl_br_uncond_nxt;
+    end
+
+
+  assign A_ctrl_br_uncond_nxt = M_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_br_uncond <= 0;
+      else if (A_en)
+          A_ctrl_br_uncond <= A_ctrl_br_uncond_nxt;
+    end
+
+
+  assign W_ctrl_br_uncond_nxt = A_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_br_uncond <= 0;
+      else if (W_en)
+          W_ctrl_br_uncond <= W_ctrl_br_uncond_nxt;
+    end
+
+
+  assign D_ctrl_br_always_pred_taken = 1'b0;
+  assign E_ctrl_br_always_pred_taken_nxt = D_ctrl_br_always_pred_taken;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_br_always_pred_taken <= 0;
+      else if (E_en)
+          E_ctrl_br_always_pred_taken <= E_ctrl_br_always_pred_taken_nxt;
+    end
+
+
+  assign M_ctrl_br_always_pred_taken_nxt = E_ctrl_br_always_pred_taken;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_br_always_pred_taken <= 0;
+      else if (M_en)
+          M_ctrl_br_always_pred_taken <= M_ctrl_br_always_pred_taken_nxt;
+    end
+
+
+  assign A_ctrl_br_always_pred_taken_nxt = M_ctrl_br_always_pred_taken;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_br_always_pred_taken <= 0;
+      else if (A_en)
+          A_ctrl_br_always_pred_taken <= A_ctrl_br_always_pred_taken_nxt;
+    end
+
+
+  assign W_ctrl_br_always_pred_taken_nxt = A_ctrl_br_always_pred_taken;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_br_always_pred_taken <= 0;
+      else if (W_en)
+          W_ctrl_br_always_pred_taken <= W_ctrl_br_always_pred_taken_nxt;
+    end
+
+
+  assign F_ctrl_br = F_op_br|
+    F_op_bge|
+    F_op_blt|
+    F_op_bne|
+    F_op_beq|
+    F_op_bgeu|
+    F_op_bltu|
+    F_op_op_rsv62;
+
+  assign D_ctrl_br_nxt = F_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_br <= 0;
+      else if (D_en)
+          D_ctrl_br <= D_ctrl_br_nxt;
+    end
+
+
+  assign E_ctrl_br_nxt = D_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_br <= 0;
+      else if (E_en)
+          E_ctrl_br <= E_ctrl_br_nxt;
+    end
+
+
+  assign M_ctrl_br_nxt = E_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_br <= 0;
+      else if (M_en)
+          M_ctrl_br <= M_ctrl_br_nxt;
+    end
+
+
+  assign A_ctrl_br_nxt = M_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_br <= 0;
+      else if (A_en)
+          A_ctrl_br <= A_ctrl_br_nxt;
+    end
+
+
+  assign W_ctrl_br_nxt = A_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_br <= 0;
+      else if (W_en)
+          W_ctrl_br <= W_ctrl_br_nxt;
+    end
+
+
+  assign D_ctrl_alu_subtract = D_op_sub|
+    D_op_opx_rsv25|
+    D_op_cmplti|
+    D_op_cmpltui|
+    D_op_cmplt|
+    D_op_cmpltu|
+    D_op_blt|
+    D_op_bltu|
+    D_op_cmpgei|
+    D_op_cmpgeui|
+    D_op_cmpge|
+    D_op_cmpgeu|
+    D_op_bge|
+    D_op_op_rsv10|
+    D_op_bgeu|
+    D_op_op_rsv42;
+
+  assign E_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_alu_subtract <= 0;
+      else if (E_en)
+          E_ctrl_alu_subtract <= E_ctrl_alu_subtract_nxt;
+    end
+
+
+  assign M_ctrl_alu_subtract_nxt = E_ctrl_alu_subtract;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_alu_subtract <= 0;
+      else if (M_en)
+          M_ctrl_alu_subtract <= M_ctrl_alu_subtract_nxt;
+    end
+
+
+  assign A_ctrl_alu_subtract_nxt = M_ctrl_alu_subtract;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_alu_subtract <= 0;
+      else if (A_en)
+          A_ctrl_alu_subtract <= A_ctrl_alu_subtract_nxt;
+    end
+
+
+  assign W_ctrl_alu_subtract_nxt = A_ctrl_alu_subtract;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_alu_subtract <= 0;
+      else if (W_en)
+          W_ctrl_alu_subtract <= W_ctrl_alu_subtract_nxt;
+    end
+
+
+  assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
+  assign E_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_alu_signed_comparison <= 0;
+      else if (E_en)
+          E_ctrl_alu_signed_comparison <= E_ctrl_alu_signed_comparison_nxt;
+    end
+
+
+  assign M_ctrl_alu_signed_comparison_nxt = E_ctrl_alu_signed_comparison;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_alu_signed_comparison <= 0;
+      else if (M_en)
+          M_ctrl_alu_signed_comparison <= M_ctrl_alu_signed_comparison_nxt;
+    end
+
+
+  assign A_ctrl_alu_signed_comparison_nxt = M_ctrl_alu_signed_comparison;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_alu_signed_comparison <= 0;
+      else if (A_en)
+          A_ctrl_alu_signed_comparison <= A_ctrl_alu_signed_comparison_nxt;
+    end
+
+
+  assign W_ctrl_alu_signed_comparison_nxt = A_ctrl_alu_signed_comparison;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_alu_signed_comparison <= 0;
+      else if (W_en)
+          W_ctrl_alu_signed_comparison <= W_ctrl_alu_signed_comparison_nxt;
+    end
+
+
+  assign E_ctrl_ld8 = E_op_ldb|E_op_ldbu|E_op_ldbio|E_op_ldbuio;
+  assign M_ctrl_ld8_nxt = E_ctrl_ld8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld8 <= 0;
+      else if (M_en)
+          M_ctrl_ld8 <= M_ctrl_ld8_nxt;
+    end
+
+
+  assign A_ctrl_ld8_nxt = M_ctrl_ld8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld8 <= 0;
+      else if (A_en)
+          A_ctrl_ld8 <= A_ctrl_ld8_nxt;
+    end
+
+
+  assign W_ctrl_ld8_nxt = A_ctrl_ld8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld8 <= 0;
+      else if (W_en)
+          W_ctrl_ld8 <= W_ctrl_ld8_nxt;
+    end
+
+
+  assign E_ctrl_ld16 = E_op_ldhu|E_op_ldh|E_op_ldhio|E_op_ldhuio;
+  assign M_ctrl_ld16_nxt = E_ctrl_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld16 <= 0;
+      else if (M_en)
+          M_ctrl_ld16 <= M_ctrl_ld16_nxt;
+    end
+
+
+  assign A_ctrl_ld16_nxt = M_ctrl_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld16 <= 0;
+      else if (A_en)
+          A_ctrl_ld16 <= A_ctrl_ld16_nxt;
+    end
+
+
+  assign W_ctrl_ld16_nxt = A_ctrl_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld16 <= 0;
+      else if (W_en)
+          W_ctrl_ld16 <= W_ctrl_ld16_nxt;
+    end
+
+
+  assign E_ctrl_ld8_ld16 = E_op_ldb|
+    E_op_ldbu|
+    E_op_ldbio|
+    E_op_ldbuio|
+    E_op_ldhu|
+    E_op_ldh|
+    E_op_ldhio|
+    E_op_ldhuio;
+
+  assign M_ctrl_ld8_ld16_nxt = E_ctrl_ld8_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld8_ld16 <= 0;
+      else if (M_en)
+          M_ctrl_ld8_ld16 <= M_ctrl_ld8_ld16_nxt;
+    end
+
+
+  assign A_ctrl_ld8_ld16_nxt = M_ctrl_ld8_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld8_ld16 <= 0;
+      else if (A_en)
+          A_ctrl_ld8_ld16 <= A_ctrl_ld8_ld16_nxt;
+    end
+
+
+  assign W_ctrl_ld8_ld16_nxt = A_ctrl_ld8_ld16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld8_ld16 <= 0;
+      else if (W_en)
+          W_ctrl_ld8_ld16 <= W_ctrl_ld8_ld16_nxt;
+    end
+
+
+  assign E_ctrl_ld32 = E_op_ldw|E_op_ldl|E_op_ldwio|E_op_op_rsv63;
+  assign M_ctrl_ld32_nxt = E_ctrl_ld32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld32 <= 0;
+      else if (M_en)
+          M_ctrl_ld32 <= M_ctrl_ld32_nxt;
+    end
+
+
+  assign A_ctrl_ld32_nxt = M_ctrl_ld32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld32 <= 0;
+      else if (A_en)
+          A_ctrl_ld32 <= A_ctrl_ld32_nxt;
+    end
+
+
+  assign W_ctrl_ld32_nxt = A_ctrl_ld32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld32 <= 0;
+      else if (W_en)
+          W_ctrl_ld32 <= W_ctrl_ld32_nxt;
+    end
+
+
+  assign E_ctrl_ld_signed = E_op_ldb|
+    E_op_ldh|
+    E_op_ldl|
+    E_op_ldw|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63;
+
+  assign M_ctrl_ld_signed_nxt = E_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_signed <= 0;
+      else if (M_en)
+          M_ctrl_ld_signed <= M_ctrl_ld_signed_nxt;
+    end
+
+
+  assign A_ctrl_ld_signed_nxt = M_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_signed <= 0;
+      else if (A_en)
+          A_ctrl_ld_signed <= A_ctrl_ld_signed_nxt;
+    end
+
+
+  assign W_ctrl_ld_signed_nxt = A_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_signed <= 0;
+      else if (W_en)
+          W_ctrl_ld_signed <= W_ctrl_ld_signed_nxt;
+    end
+
+
+  assign D_ctrl_ld = D_op_ldb|
+    D_op_ldh|
+    D_op_ldl|
+    D_op_ldw|
+    D_op_ldbio|
+    D_op_ldhio|
+    D_op_ldwio|
+    D_op_op_rsv63|
+    D_op_ldbu|
+    D_op_ldhu|
+    D_op_ldbuio|
+    D_op_ldhuio;
+
+  assign E_ctrl_ld_nxt = D_ctrl_ld;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_ld <= 0;
+      else if (E_en)
+          E_ctrl_ld <= E_ctrl_ld_nxt;
+    end
+
+
+  assign M_ctrl_ld_nxt = E_ctrl_ld;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld <= 0;
+      else if (M_en)
+          M_ctrl_ld <= M_ctrl_ld_nxt;
+    end
+
+
+  assign A_ctrl_ld_nxt = M_ctrl_ld;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld <= 0;
+      else if (A_en)
+          A_ctrl_ld <= A_ctrl_ld_nxt;
+    end
+
+
+  assign W_ctrl_ld_nxt = A_ctrl_ld;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld <= 0;
+      else if (W_en)
+          W_ctrl_ld <= W_ctrl_ld_nxt;
+    end
+
+
+  assign D_ctrl_ld_ex = 1'b0;
+  assign E_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_ld_ex <= 0;
+      else if (E_en)
+          E_ctrl_ld_ex <= E_ctrl_ld_ex_nxt;
+    end
+
+
+  assign M_ctrl_ld_ex_nxt = E_ctrl_ld_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_ex <= 0;
+      else if (M_en)
+          M_ctrl_ld_ex <= M_ctrl_ld_ex_nxt;
+    end
+
+
+  assign A_ctrl_ld_ex_nxt = M_ctrl_ld_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_ex <= 0;
+      else if (A_en)
+          A_ctrl_ld_ex <= A_ctrl_ld_ex_nxt;
+    end
+
+
+  assign W_ctrl_ld_ex_nxt = A_ctrl_ld_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_ex <= 0;
+      else if (W_en)
+          W_ctrl_ld_ex <= W_ctrl_ld_ex_nxt;
+    end
+
+
+  assign E_ctrl_ld_dcache_management = E_op_initd|
+    E_op_initda|
+    E_op_flushd|
+    E_op_flushda|
+    E_op_ldb|
+    E_op_ldh|
+    E_op_ldl|
+    E_op_ldw|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63|
+    E_op_ldbu|
+    E_op_ldhu|
+    E_op_ldbuio|
+    E_op_ldhuio;
+
+  assign M_ctrl_ld_dcache_management_nxt = E_ctrl_ld_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_dcache_management <= 0;
+      else if (M_en)
+          M_ctrl_ld_dcache_management <= M_ctrl_ld_dcache_management_nxt;
+    end
+
+
+  assign A_ctrl_ld_dcache_management_nxt = M_ctrl_ld_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_dcache_management <= 0;
+      else if (A_en)
+          A_ctrl_ld_dcache_management <= A_ctrl_ld_dcache_management_nxt;
+    end
+
+
+  assign W_ctrl_ld_dcache_management_nxt = A_ctrl_ld_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_dcache_management <= 0;
+      else if (W_en)
+          W_ctrl_ld_dcache_management <= W_ctrl_ld_dcache_management_nxt;
+    end
+
+
+  assign E_ctrl_ld_non_io = E_op_ldbu|E_op_ldhu|E_op_ldb|E_op_ldh|E_op_ldw|E_op_ldl;
+  assign M_ctrl_ld_non_io_nxt = E_ctrl_ld_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_non_io <= 0;
+      else if (M_en)
+          M_ctrl_ld_non_io <= M_ctrl_ld_non_io_nxt;
+    end
+
+
+  assign A_ctrl_ld_non_io_nxt = M_ctrl_ld_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_non_io <= 0;
+      else if (A_en)
+          A_ctrl_ld_non_io <= A_ctrl_ld_non_io_nxt;
+    end
+
+
+  assign W_ctrl_ld_non_io_nxt = A_ctrl_ld_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_non_io <= 0;
+      else if (W_en)
+          W_ctrl_ld_non_io <= W_ctrl_ld_non_io_nxt;
+    end
+
+
+  assign E_ctrl_st8 = E_op_stb|E_op_stbio;
+  assign M_ctrl_st8_nxt = E_ctrl_st8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st8 <= 0;
+      else if (M_en)
+          M_ctrl_st8 <= M_ctrl_st8_nxt;
+    end
+
+
+  assign A_ctrl_st8_nxt = M_ctrl_st8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st8 <= 0;
+      else if (A_en)
+          A_ctrl_st8 <= A_ctrl_st8_nxt;
+    end
+
+
+  assign W_ctrl_st8_nxt = A_ctrl_st8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st8 <= 0;
+      else if (W_en)
+          W_ctrl_st8 <= W_ctrl_st8_nxt;
+    end
+
+
+  assign E_ctrl_st16 = E_op_sth|E_op_op_rsv09|E_op_sthio|E_op_op_rsv41;
+  assign M_ctrl_st16_nxt = E_ctrl_st16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st16 <= 0;
+      else if (M_en)
+          M_ctrl_st16 <= M_ctrl_st16_nxt;
+    end
+
+
+  assign A_ctrl_st16_nxt = M_ctrl_st16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st16 <= 0;
+      else if (A_en)
+          A_ctrl_st16 <= A_ctrl_st16_nxt;
+    end
+
+
+  assign W_ctrl_st16_nxt = A_ctrl_st16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st16 <= 0;
+      else if (W_en)
+          W_ctrl_st16 <= W_ctrl_st16_nxt;
+    end
+
+
+  assign E_ctrl_st_non32 = E_op_stb|E_op_stbio|E_op_sth|E_op_sthio;
+  assign M_ctrl_st_non32_nxt = E_ctrl_st_non32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_non32 <= 0;
+      else if (M_en)
+          M_ctrl_st_non32 <= M_ctrl_st_non32_nxt;
+    end
+
+
+  assign A_ctrl_st_non32_nxt = M_ctrl_st_non32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_non32 <= 0;
+      else if (A_en)
+          A_ctrl_st_non32 <= A_ctrl_st_non32_nxt;
+    end
+
+
+  assign W_ctrl_st_non32_nxt = A_ctrl_st_non32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st_non32 <= 0;
+      else if (W_en)
+          W_ctrl_st_non32 <= W_ctrl_st_non32_nxt;
+    end
+
+
+  assign D_ctrl_st_ex = 1'b0;
+  assign E_ctrl_st_ex_nxt = D_ctrl_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_st_ex <= 0;
+      else if (E_en)
+          E_ctrl_st_ex <= E_ctrl_st_ex_nxt;
+    end
+
+
+  assign M_ctrl_st_ex_nxt = E_ctrl_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_ex <= 0;
+      else if (M_en)
+          M_ctrl_st_ex <= M_ctrl_st_ex_nxt;
+    end
+
+
+  assign A_ctrl_st_ex_nxt = M_ctrl_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_ex <= 0;
+      else if (A_en)
+          A_ctrl_st_ex <= A_ctrl_st_ex_nxt;
+    end
+
+
+  assign W_ctrl_st_ex_nxt = A_ctrl_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st_ex <= 0;
+      else if (W_en)
+          W_ctrl_st_ex <= W_ctrl_st_ex_nxt;
+    end
+
+
+  assign E_ctrl_st = E_op_stb|
+    E_op_sth|
+    E_op_stw|
+    E_op_stc|
+    E_op_stbio|
+    E_op_sthio|
+    E_op_stwio|
+    E_op_op_rsv61;
+
+  assign M_ctrl_st_nxt = E_ctrl_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st <= 0;
+      else if (M_en)
+          M_ctrl_st <= M_ctrl_st_nxt;
+    end
+
+
+  assign A_ctrl_st_nxt = M_ctrl_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st <= 0;
+      else if (A_en)
+          A_ctrl_st <= A_ctrl_st_nxt;
+    end
+
+
+  assign W_ctrl_st_nxt = A_ctrl_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st <= 0;
+      else if (W_en)
+          W_ctrl_st <= W_ctrl_st_nxt;
+    end
+
+
+  assign E_ctrl_st_non_io = E_op_stb|E_op_sth|E_op_stw|E_op_stc;
+  assign M_ctrl_st_non_io_nxt = E_ctrl_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_non_io <= 0;
+      else if (M_en)
+          M_ctrl_st_non_io <= M_ctrl_st_non_io_nxt;
+    end
+
+
+  assign A_ctrl_st_non_io_nxt = M_ctrl_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_non_io <= 0;
+      else if (A_en)
+          A_ctrl_st_non_io <= A_ctrl_st_non_io_nxt;
+    end
+
+
+  assign W_ctrl_st_non_io_nxt = A_ctrl_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st_non_io <= 0;
+      else if (W_en)
+          W_ctrl_st_non_io <= W_ctrl_st_non_io_nxt;
+    end
+
+
+  assign E_ctrl_ld_st = E_op_ldb|
+    E_op_ldh|
+    E_op_ldl|
+    E_op_ldw|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63|
+    E_op_ldbu|
+    E_op_ldhu|
+    E_op_ldbuio|
+    E_op_ldhuio|
+    E_op_stb|
+    E_op_sth|
+    E_op_stw|
+    E_op_stc|
+    E_op_stbio|
+    E_op_sthio|
+    E_op_stwio|
+    E_op_op_rsv61;
+
+  assign M_ctrl_ld_st_nxt = E_ctrl_ld_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st <= 0;
+      else if (M_en)
+          M_ctrl_ld_st <= M_ctrl_ld_st_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_nxt = M_ctrl_ld_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st <= 0;
+      else if (A_en)
+          A_ctrl_ld_st <= A_ctrl_ld_st_nxt;
+    end
+
+
+  assign W_ctrl_ld_st_nxt = A_ctrl_ld_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_st <= 0;
+      else if (W_en)
+          W_ctrl_ld_st <= W_ctrl_ld_st_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_io = E_op_ldbuio|
+    E_op_ldhuio|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63|
+    E_op_stbio|
+    E_op_op_rsv33|
+    E_op_sthio|
+    E_op_op_rsv41|
+    E_op_stwio|
+    E_op_op_rsv49|
+    E_op_op_rsv61|
+    E_op_op_rsv57;
+
+  assign M_ctrl_ld_st_io_nxt = E_ctrl_ld_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_io <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_io <= M_ctrl_ld_st_io_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_io_nxt = M_ctrl_ld_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_io <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_io <= A_ctrl_ld_st_io_nxt;
+    end
+
+
+  assign W_ctrl_ld_st_io_nxt = A_ctrl_ld_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_st_io <= 0;
+      else if (W_en)
+          W_ctrl_ld_st_io <= W_ctrl_ld_st_io_nxt;
+    end
+
+
+  assign E_ctrl_ld_st_non_io = E_op_ldbu|
+    E_op_ldhu|
+    E_op_ldb|
+    E_op_ldh|
+    E_op_ldw|
+    E_op_ldl|
+    E_op_stb|
+    E_op_sth|
+    E_op_stw|
+    E_op_stc;
+
+  assign M_ctrl_ld_st_non_io_nxt = E_ctrl_ld_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_non_io <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_non_io <= M_ctrl_ld_st_non_io_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_non_io_nxt = M_ctrl_ld_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_non_io <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_non_io <= A_ctrl_ld_st_non_io_nxt;
+    end
+
+
+  assign W_ctrl_ld_st_non_io_nxt = A_ctrl_ld_st_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_st_non_io <= 0;
+      else if (W_en)
+          W_ctrl_ld_st_non_io <= W_ctrl_ld_st_non_io_nxt;
+    end
+
+
+  assign D_ctrl_ld_st_ex = 1'b0;
+  assign E_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_ld_st_ex <= 0;
+      else if (E_en)
+          E_ctrl_ld_st_ex <= E_ctrl_ld_st_ex_nxt;
+    end
+
+
+  assign M_ctrl_ld_st_ex_nxt = E_ctrl_ld_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_st_ex <= 0;
+      else if (M_en)
+          M_ctrl_ld_st_ex <= M_ctrl_ld_st_ex_nxt;
+    end
+
+
+  assign A_ctrl_ld_st_ex_nxt = M_ctrl_ld_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_st_ex <= 0;
+      else if (A_en)
+          A_ctrl_ld_st_ex <= A_ctrl_ld_st_ex_nxt;
+    end
+
+
+  assign W_ctrl_ld_st_ex_nxt = A_ctrl_ld_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_st_ex <= 0;
+      else if (W_en)
+          W_ctrl_ld_st_ex <= W_ctrl_ld_st_ex_nxt;
+    end
+
+
+  assign E_ctrl_mem = E_op_initd|
+    E_op_initda|
+    E_op_flushd|
+    E_op_flushda|
+    E_op_ldb|
+    E_op_ldh|
+    E_op_ldl|
+    E_op_ldw|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63|
+    E_op_ldbu|
+    E_op_ldhu|
+    E_op_ldbuio|
+    E_op_ldhuio|
+    E_op_stb|
+    E_op_sth|
+    E_op_stw|
+    E_op_stc|
+    E_op_stbio|
+    E_op_sthio|
+    E_op_stwio|
+    E_op_op_rsv61;
+
+  assign M_ctrl_mem_nxt = E_ctrl_mem;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem <= 0;
+      else if (M_en)
+          M_ctrl_mem <= M_ctrl_mem_nxt;
+    end
+
+
+  assign A_ctrl_mem_nxt = M_ctrl_mem;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem <= 0;
+      else if (A_en)
+          A_ctrl_mem <= A_ctrl_mem_nxt;
+    end
+
+
+  assign W_ctrl_mem_nxt = A_ctrl_mem;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mem <= 0;
+      else if (W_en)
+          W_ctrl_mem <= W_ctrl_mem_nxt;
+    end
+
+
+  assign E_ctrl_mem_data_access = E_op_flushda|
+    E_op_initda|
+    E_op_ldb|
+    E_op_ldh|
+    E_op_ldl|
+    E_op_ldw|
+    E_op_ldbio|
+    E_op_ldhio|
+    E_op_ldwio|
+    E_op_op_rsv63|
+    E_op_ldbu|
+    E_op_ldhu|
+    E_op_ldbuio|
+    E_op_ldhuio|
+    E_op_stb|
+    E_op_sth|
+    E_op_stw|
+    E_op_stc|
+    E_op_stbio|
+    E_op_sthio|
+    E_op_stwio|
+    E_op_op_rsv61;
+
+  assign M_ctrl_mem_data_access_nxt = E_ctrl_mem_data_access;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem_data_access <= 0;
+      else if (M_en)
+          M_ctrl_mem_data_access <= M_ctrl_mem_data_access_nxt;
+    end
+
+
+  assign A_ctrl_mem_data_access_nxt = M_ctrl_mem_data_access;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem_data_access <= 0;
+      else if (A_en)
+          A_ctrl_mem_data_access <= A_ctrl_mem_data_access_nxt;
+    end
+
+
+  assign W_ctrl_mem_data_access_nxt = A_ctrl_mem_data_access;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mem_data_access <= 0;
+      else if (W_en)
+          W_ctrl_mem_data_access <= W_ctrl_mem_data_access_nxt;
+    end
+
+
+  assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
+  assign E_ctrl_mem8_nxt = D_ctrl_mem8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_mem8 <= 0;
+      else if (E_en)
+          E_ctrl_mem8 <= E_ctrl_mem8_nxt;
+    end
+
+
+  assign M_ctrl_mem8_nxt = E_ctrl_mem8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem8 <= 0;
+      else if (M_en)
+          M_ctrl_mem8 <= M_ctrl_mem8_nxt;
+    end
+
+
+  assign A_ctrl_mem8_nxt = M_ctrl_mem8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem8 <= 0;
+      else if (A_en)
+          A_ctrl_mem8 <= A_ctrl_mem8_nxt;
+    end
+
+
+  assign W_ctrl_mem8_nxt = A_ctrl_mem8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mem8 <= 0;
+      else if (W_en)
+          W_ctrl_mem8 <= W_ctrl_mem8_nxt;
+    end
+
+
+  assign D_ctrl_mem16 = D_op_ldhu|
+    D_op_ldh|
+    D_op_ldhio|
+    D_op_ldhuio|
+    D_op_sth|
+    D_op_op_rsv09|
+    D_op_sthio|
+    D_op_op_rsv41;
+
+  assign E_ctrl_mem16_nxt = D_ctrl_mem16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_mem16 <= 0;
+      else if (E_en)
+          E_ctrl_mem16 <= E_ctrl_mem16_nxt;
+    end
+
+
+  assign M_ctrl_mem16_nxt = E_ctrl_mem16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem16 <= 0;
+      else if (M_en)
+          M_ctrl_mem16 <= M_ctrl_mem16_nxt;
+    end
+
+
+  assign A_ctrl_mem16_nxt = M_ctrl_mem16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem16 <= 0;
+      else if (A_en)
+          A_ctrl_mem16 <= A_ctrl_mem16_nxt;
+    end
+
+
+  assign W_ctrl_mem16_nxt = A_ctrl_mem16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mem16 <= 0;
+      else if (W_en)
+          W_ctrl_mem16 <= W_ctrl_mem16_nxt;
+    end
+
+
+  assign D_ctrl_mem32 = D_op_ldw|
+    D_op_ldl|
+    D_op_ldwio|
+    D_op_op_rsv63|
+    D_op_stw|
+    D_op_op_rsv17|
+    D_op_stc|
+    D_op_op_rsv25|
+    D_op_stwio|
+    D_op_op_rsv49|
+    D_op_op_rsv61|
+    D_op_op_rsv57;
+
+  assign E_ctrl_mem32_nxt = D_ctrl_mem32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_mem32 <= 0;
+      else if (E_en)
+          E_ctrl_mem32 <= E_ctrl_mem32_nxt;
+    end
+
+
+  assign M_ctrl_mem32_nxt = E_ctrl_mem32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_mem32 <= 0;
+      else if (M_en)
+          M_ctrl_mem32 <= M_ctrl_mem32_nxt;
+    end
+
+
+  assign A_ctrl_mem32_nxt = M_ctrl_mem32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_mem32 <= 0;
+      else if (A_en)
+          A_ctrl_mem32 <= A_ctrl_mem32_nxt;
+    end
+
+
+  assign W_ctrl_mem32_nxt = A_ctrl_mem32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_mem32 <= 0;
+      else if (W_en)
+          W_ctrl_mem32 <= W_ctrl_mem32_nxt;
+    end
+
+
+  assign E_ctrl_dc_index_nowb_inv = E_op_initd|E_op_op_rsv49;
+  assign M_ctrl_dc_index_nowb_inv_nxt = E_ctrl_dc_index_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_index_nowb_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_index_nowb_inv <= M_ctrl_dc_index_nowb_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_index_nowb_inv_nxt = M_ctrl_dc_index_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_index_nowb_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_index_nowb_inv <= A_ctrl_dc_index_nowb_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_index_nowb_inv_nxt = A_ctrl_dc_index_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_index_nowb_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_index_nowb_inv <= W_ctrl_dc_index_nowb_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_addr_nowb_inv = E_op_initda|E_op_op_rsv17;
+  assign M_ctrl_dc_addr_nowb_inv_nxt = E_ctrl_dc_addr_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_addr_nowb_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_addr_nowb_inv <= M_ctrl_dc_addr_nowb_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_addr_nowb_inv_nxt = M_ctrl_dc_addr_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_addr_nowb_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_addr_nowb_inv <= A_ctrl_dc_addr_nowb_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_addr_nowb_inv_nxt = A_ctrl_dc_addr_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_addr_nowb_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_addr_nowb_inv <= W_ctrl_dc_addr_nowb_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_index_wb_inv = E_op_flushd|E_op_op_rsv57;
+  assign M_ctrl_dc_index_wb_inv_nxt = E_ctrl_dc_index_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_index_wb_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_index_wb_inv <= M_ctrl_dc_index_wb_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_index_wb_inv_nxt = M_ctrl_dc_index_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_index_wb_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_index_wb_inv <= A_ctrl_dc_index_wb_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_index_wb_inv_nxt = A_ctrl_dc_index_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_index_wb_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_index_wb_inv <= W_ctrl_dc_index_wb_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_addr_wb_inv = E_op_flushda|E_op_op_rsv25;
+  assign M_ctrl_dc_addr_wb_inv_nxt = E_ctrl_dc_addr_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_addr_wb_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_addr_wb_inv <= M_ctrl_dc_addr_wb_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_addr_wb_inv_nxt = M_ctrl_dc_addr_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_addr_wb_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_addr_wb_inv <= A_ctrl_dc_addr_wb_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_addr_wb_inv_nxt = A_ctrl_dc_addr_wb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_addr_wb_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_addr_wb_inv <= W_ctrl_dc_addr_wb_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_index_inv = E_op_initd|E_op_op_rsv49|E_op_flushd|E_op_op_rsv57;
+  assign M_ctrl_dc_index_inv_nxt = E_ctrl_dc_index_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_index_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_index_inv <= M_ctrl_dc_index_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_index_inv_nxt = M_ctrl_dc_index_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_index_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_index_inv <= A_ctrl_dc_index_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_index_inv_nxt = A_ctrl_dc_index_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_index_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_index_inv <= W_ctrl_dc_index_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_addr_inv = E_op_initda|E_op_op_rsv17|E_op_flushda|E_op_op_rsv25;
+  assign M_ctrl_dc_addr_inv_nxt = E_ctrl_dc_addr_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_addr_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_addr_inv <= M_ctrl_dc_addr_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_addr_inv_nxt = M_ctrl_dc_addr_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_addr_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_addr_inv <= A_ctrl_dc_addr_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_addr_inv_nxt = A_ctrl_dc_addr_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_addr_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_addr_inv <= W_ctrl_dc_addr_inv_nxt;
+    end
+
+
+  assign E_ctrl_dc_nowb_inv = E_op_initd|E_op_op_rsv49|E_op_initda|E_op_op_rsv17;
+  assign M_ctrl_dc_nowb_inv_nxt = E_ctrl_dc_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dc_nowb_inv <= 0;
+      else if (M_en)
+          M_ctrl_dc_nowb_inv <= M_ctrl_dc_nowb_inv_nxt;
+    end
+
+
+  assign A_ctrl_dc_nowb_inv_nxt = M_ctrl_dc_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dc_nowb_inv <= 0;
+      else if (A_en)
+          A_ctrl_dc_nowb_inv <= A_ctrl_dc_nowb_inv_nxt;
+    end
+
+
+  assign W_ctrl_dc_nowb_inv_nxt = A_ctrl_dc_nowb_inv;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dc_nowb_inv <= 0;
+      else if (W_en)
+          W_ctrl_dc_nowb_inv <= W_ctrl_dc_nowb_inv_nxt;
+    end
+
+
+  assign E_ctrl_dcache_management = E_op_initd|
+    E_op_op_rsv49|
+    E_op_flushd|
+    E_op_op_rsv57|
+    E_op_initda|
+    E_op_op_rsv17|
+    E_op_flushda|
+    E_op_op_rsv25;
+
+  assign M_ctrl_dcache_management_nxt = E_ctrl_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_dcache_management <= 0;
+      else if (M_en)
+          M_ctrl_dcache_management <= M_ctrl_dcache_management_nxt;
+    end
+
+
+  assign A_ctrl_dcache_management_nxt = M_ctrl_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_dcache_management <= 0;
+      else if (A_en)
+          A_ctrl_dcache_management <= A_ctrl_dcache_management_nxt;
+    end
+
+
+  assign W_ctrl_dcache_management_nxt = A_ctrl_dcache_management;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_dcache_management <= 0;
+      else if (W_en)
+          W_ctrl_dcache_management <= W_ctrl_dcache_management_nxt;
+    end
+
+
+  assign E_ctrl_ld_io = E_op_ldbuio|E_op_ldhuio|E_op_ldbio|E_op_ldhio|E_op_ldwio|E_op_op_rsv63;
+  assign M_ctrl_ld_io_nxt = E_ctrl_ld_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ld_io <= 0;
+      else if (M_en)
+          M_ctrl_ld_io <= M_ctrl_ld_io_nxt;
+    end
+
+
+  assign A_ctrl_ld_io_nxt = M_ctrl_ld_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ld_io <= 0;
+      else if (A_en)
+          A_ctrl_ld_io <= A_ctrl_ld_io_nxt;
+    end
+
+
+  assign W_ctrl_ld_io_nxt = A_ctrl_ld_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ld_io <= 0;
+      else if (W_en)
+          W_ctrl_ld_io <= W_ctrl_ld_io_nxt;
+    end
+
+
+  assign E_ctrl_st_io = E_op_stbio|
+    E_op_op_rsv33|
+    E_op_sthio|
+    E_op_op_rsv41|
+    E_op_stwio|
+    E_op_op_rsv49|
+    E_op_op_rsv61|
+    E_op_op_rsv57;
+
+  assign M_ctrl_st_io_nxt = E_ctrl_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_st_io <= 0;
+      else if (M_en)
+          M_ctrl_st_io <= M_ctrl_st_io_nxt;
+    end
+
+
+  assign A_ctrl_st_io_nxt = M_ctrl_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_st_io <= 0;
+      else if (A_en)
+          A_ctrl_st_io <= A_ctrl_st_io_nxt;
+    end
+
+
+  assign W_ctrl_st_io_nxt = A_ctrl_st_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_st_io <= 0;
+      else if (W_en)
+          W_ctrl_st_io <= W_ctrl_st_io_nxt;
+    end
+
+
+  assign F_ctrl_a_not_src = F_op_call|F_op_jmpi;
+  assign D_ctrl_a_not_src_nxt = F_ctrl_a_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_a_not_src <= 0;
+      else if (D_en)
+          D_ctrl_a_not_src <= D_ctrl_a_not_src_nxt;
+    end
+
+
+  assign E_ctrl_a_not_src_nxt = D_ctrl_a_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_a_not_src <= 0;
+      else if (E_en)
+          E_ctrl_a_not_src <= E_ctrl_a_not_src_nxt;
+    end
+
+
+  assign M_ctrl_a_not_src_nxt = E_ctrl_a_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_a_not_src <= 0;
+      else if (M_en)
+          M_ctrl_a_not_src <= M_ctrl_a_not_src_nxt;
+    end
+
+
+  assign A_ctrl_a_not_src_nxt = M_ctrl_a_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_a_not_src <= 0;
+      else if (A_en)
+          A_ctrl_a_not_src <= A_ctrl_a_not_src_nxt;
+    end
+
+
+  assign W_ctrl_a_not_src_nxt = A_ctrl_a_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_a_not_src <= 0;
+      else if (W_en)
+          W_ctrl_a_not_src <= W_ctrl_a_not_src_nxt;
+    end
+
+
+  assign F_ctrl_b_not_src = F_op_addi|
+    F_op_muli|
+    F_op_andhi|
+    F_op_orhi|
+    F_op_xorhi|
+    F_op_andi|
+    F_op_ori|
+    F_op_xori|
+    F_op_call|
+    F_op_rdprs|
+    F_op_cmpgei|
+    F_op_cmplti|
+    F_op_cmpnei|
+    F_op_cmpgeui|
+    F_op_cmpltui|
+    F_op_cmpeqi|
+    F_op_jmpi|
+    F_op_op_rsv09|
+    F_op_op_rsv17|
+    F_op_op_rsv25|
+    F_op_op_rsv33|
+    F_op_op_rsv41|
+    F_op_op_rsv49|
+    F_op_op_rsv57|
+    F_op_ldb|
+    F_op_ldh|
+    F_op_ldl|
+    F_op_ldw|
+    F_op_ldbio|
+    F_op_ldhio|
+    F_op_ldwio|
+    F_op_op_rsv63|
+    F_op_ldbu|
+    F_op_ldhu|
+    F_op_ldbuio|
+    F_op_ldhuio|
+    F_op_initd|
+    F_op_initda|
+    F_op_flushd|
+    F_op_flushda;
+
+  assign D_ctrl_b_not_src_nxt = F_ctrl_b_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_b_not_src <= 0;
+      else if (D_en)
+          D_ctrl_b_not_src <= D_ctrl_b_not_src_nxt;
+    end
+
+
+  assign E_ctrl_b_not_src_nxt = D_ctrl_b_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_b_not_src <= 0;
+      else if (E_en)
+          E_ctrl_b_not_src <= E_ctrl_b_not_src_nxt;
+    end
+
+
+  assign M_ctrl_b_not_src_nxt = E_ctrl_b_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_b_not_src <= 0;
+      else if (M_en)
+          M_ctrl_b_not_src <= M_ctrl_b_not_src_nxt;
+    end
+
+
+  assign A_ctrl_b_not_src_nxt = M_ctrl_b_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_b_not_src <= 0;
+      else if (A_en)
+          A_ctrl_b_not_src <= A_ctrl_b_not_src_nxt;
+    end
+
+
+  assign W_ctrl_b_not_src_nxt = A_ctrl_b_not_src;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_b_not_src <= 0;
+      else if (W_en)
+          W_ctrl_b_not_src <= W_ctrl_b_not_src_nxt;
+    end
+
+
+  assign F_ctrl_b_is_dst = F_op_addi|
+    F_op_muli|
+    F_op_andhi|
+    F_op_orhi|
+    F_op_xorhi|
+    F_op_andi|
+    F_op_ori|
+    F_op_xori|
+    F_op_call|
+    F_op_rdprs|
+    F_op_cmpgei|
+    F_op_cmplti|
+    F_op_cmpnei|
+    F_op_cmpgeui|
+    F_op_cmpltui|
+    F_op_cmpeqi|
+    F_op_jmpi|
+    F_op_op_rsv09|
+    F_op_op_rsv17|
+    F_op_op_rsv25|
+    F_op_op_rsv33|
+    F_op_op_rsv41|
+    F_op_op_rsv49|
+    F_op_op_rsv57|
+    F_op_ldb|
+    F_op_ldh|
+    F_op_ldl|
+    F_op_ldw|
+    F_op_ldbio|
+    F_op_ldhio|
+    F_op_ldwio|
+    F_op_op_rsv63|
+    F_op_ldbu|
+    F_op_ldhu|
+    F_op_ldbuio|
+    F_op_ldhuio|
+    F_op_initd|
+    F_op_initda|
+    F_op_flushd|
+    F_op_flushda;
+
+  assign D_ctrl_b_is_dst_nxt = F_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_b_is_dst <= 0;
+      else if (D_en)
+          D_ctrl_b_is_dst <= D_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign E_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_b_is_dst <= 0;
+      else if (E_en)
+          E_ctrl_b_is_dst <= E_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign M_ctrl_b_is_dst_nxt = E_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_b_is_dst <= 0;
+      else if (M_en)
+          M_ctrl_b_is_dst <= M_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign A_ctrl_b_is_dst_nxt = M_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_b_is_dst <= 0;
+      else if (A_en)
+          A_ctrl_b_is_dst <= A_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign W_ctrl_b_is_dst_nxt = A_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_b_is_dst <= 0;
+      else if (W_en)
+          W_ctrl_b_is_dst <= W_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign F_ctrl_ignore_dst = F_op_br|
+    F_op_bge|
+    F_op_blt|
+    F_op_bne|
+    F_op_beq|
+    F_op_bgeu|
+    F_op_bltu|
+    F_op_op_rsv62|
+    F_op_stb|
+    F_op_sth|
+    F_op_stw|
+    F_op_stc|
+    F_op_stbio|
+    F_op_sthio|
+    F_op_stwio|
+    F_op_op_rsv61|
+    F_op_jmpi|
+    F_op_op_rsv09|
+    F_op_op_rsv17|
+    F_op_op_rsv25|
+    F_op_op_rsv33|
+    F_op_op_rsv41|
+    F_op_op_rsv49|
+    F_op_op_rsv57;
+
+  assign D_ctrl_ignore_dst_nxt = F_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_ignore_dst <= 0;
+      else if (D_en)
+          D_ctrl_ignore_dst <= D_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign E_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_ignore_dst <= 0;
+      else if (E_en)
+          E_ctrl_ignore_dst <= E_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign M_ctrl_ignore_dst_nxt = E_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_ignore_dst <= 0;
+      else if (M_en)
+          M_ctrl_ignore_dst <= M_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign A_ctrl_ignore_dst_nxt = M_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_ignore_dst <= 0;
+      else if (A_en)
+          A_ctrl_ignore_dst <= A_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign W_ctrl_ignore_dst_nxt = A_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_ignore_dst <= 0;
+      else if (W_en)
+          W_ctrl_ignore_dst <= W_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign F_ctrl_src2_choose_imm = F_op_addi|
+    F_op_muli|
+    F_op_andhi|
+    F_op_orhi|
+    F_op_xorhi|
+    F_op_andi|
+    F_op_ori|
+    F_op_xori|
+    F_op_call|
+    F_op_rdprs|
+    F_op_cmpgei|
+    F_op_cmplti|
+    F_op_cmpnei|
+    F_op_cmpgeui|
+    F_op_cmpltui|
+    F_op_cmpeqi|
+    F_op_jmpi|
+    F_op_op_rsv09|
+    F_op_op_rsv17|
+    F_op_op_rsv25|
+    F_op_op_rsv33|
+    F_op_op_rsv41|
+    F_op_op_rsv49|
+    F_op_op_rsv57|
+    F_op_ldb|
+    F_op_ldh|
+    F_op_ldl|
+    F_op_ldw|
+    F_op_ldbio|
+    F_op_ldhio|
+    F_op_ldwio|
+    F_op_op_rsv63|
+    F_op_ldbu|
+    F_op_ldhu|
+    F_op_ldbuio|
+    F_op_ldhuio|
+    F_op_initd|
+    F_op_initda|
+    F_op_flushd|
+    F_op_flushda|
+    F_op_stb|
+    F_op_sth|
+    F_op_stw|
+    F_op_stc|
+    F_op_stbio|
+    F_op_sthio|
+    F_op_stwio|
+    F_op_op_rsv61|
+    F_op_roli|
+    F_op_opx_rsv10|
+    F_op_slli|
+    F_op_srli|
+    F_op_opx_rsv34|
+    F_op_opx_rsv42|
+    F_op_opx_rsv50|
+    F_op_srai;
+
+  assign D_ctrl_src2_choose_imm_nxt = F_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_ctrl_src2_choose_imm <= 0;
+      else if (D_en)
+          D_ctrl_src2_choose_imm <= D_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign E_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_src2_choose_imm <= 0;
+      else if (E_en)
+          E_ctrl_src2_choose_imm <= E_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign M_ctrl_src2_choose_imm_nxt = E_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_src2_choose_imm <= 0;
+      else if (M_en)
+          M_ctrl_src2_choose_imm <= M_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign A_ctrl_src2_choose_imm_nxt = M_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_src2_choose_imm <= 0;
+      else if (A_en)
+          A_ctrl_src2_choose_imm <= A_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign W_ctrl_src2_choose_imm_nxt = A_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_src2_choose_imm <= 0;
+      else if (W_en)
+          W_ctrl_src2_choose_imm <= W_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign E_ctrl_wrctl_inst = E_op_wrctl;
+  assign M_ctrl_wrctl_inst_nxt = E_ctrl_wrctl_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_wrctl_inst <= 0;
+      else if (M_en)
+          M_ctrl_wrctl_inst <= M_ctrl_wrctl_inst_nxt;
+    end
+
+
+  assign A_ctrl_wrctl_inst_nxt = M_ctrl_wrctl_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_wrctl_inst <= 0;
+      else if (A_en)
+          A_ctrl_wrctl_inst <= A_ctrl_wrctl_inst_nxt;
+    end
+
+
+  assign W_ctrl_wrctl_inst_nxt = A_ctrl_wrctl_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_wrctl_inst <= 0;
+      else if (W_en)
+          W_ctrl_wrctl_inst <= W_ctrl_wrctl_inst_nxt;
+    end
+
+
+  assign D_ctrl_intr_inst = 1'b0;
+  assign E_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_intr_inst <= 0;
+      else if (E_en)
+          E_ctrl_intr_inst <= E_ctrl_intr_inst_nxt;
+    end
+
+
+  assign M_ctrl_intr_inst_nxt = E_ctrl_intr_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_intr_inst <= 0;
+      else if (M_en)
+          M_ctrl_intr_inst <= M_ctrl_intr_inst_nxt;
+    end
+
+
+  assign A_ctrl_intr_inst_nxt = M_ctrl_intr_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_intr_inst <= 0;
+      else if (A_en)
+          A_ctrl_intr_inst <= A_ctrl_intr_inst_nxt;
+    end
+
+
+  assign W_ctrl_intr_inst_nxt = A_ctrl_intr_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_intr_inst <= 0;
+      else if (W_en)
+          W_ctrl_intr_inst <= W_ctrl_intr_inst_nxt;
+    end
+
+
+  assign D_ctrl_bmx = 1'b0;
+  assign E_ctrl_bmx_nxt = D_ctrl_bmx;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_bmx <= 0;
+      else if (E_en)
+          E_ctrl_bmx <= E_ctrl_bmx_nxt;
+    end
+
+
+  assign M_ctrl_bmx_nxt = E_ctrl_bmx;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_bmx <= 0;
+      else if (M_en)
+          M_ctrl_bmx <= M_ctrl_bmx_nxt;
+    end
+
+
+  assign A_ctrl_bmx_nxt = M_ctrl_bmx;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_bmx <= 0;
+      else if (A_en)
+          A_ctrl_bmx <= A_ctrl_bmx_nxt;
+    end
+
+
+  assign W_ctrl_bmx_nxt = A_ctrl_bmx;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_bmx <= 0;
+      else if (W_en)
+          W_ctrl_bmx <= W_ctrl_bmx_nxt;
+    end
+
+
+  assign D_ctrl_flush_pipe_always = D_op_flushp|
+    D_op_bret|
+    D_op_wrprs|
+    D_op_initi|
+    D_op_flushi|
+    D_op_wrctl|
+    D_op_eret|
+    D_op_trap|
+    D_op_opx_rsv44|
+    D_op_div|
+    D_op_divu|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_hbreak|
+    D_op_intr|
+    D_op_ldl|
+    D_op_op_rsv02|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_break;
+
+  assign E_ctrl_flush_pipe_always_nxt = D_ctrl_flush_pipe_always;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_flush_pipe_always <= 0;
+      else if (E_en)
+          E_ctrl_flush_pipe_always <= E_ctrl_flush_pipe_always_nxt;
+    end
+
+
+  assign M_ctrl_flush_pipe_always_nxt = E_ctrl_flush_pipe_always;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_flush_pipe_always <= 0;
+      else if (M_en)
+          M_ctrl_flush_pipe_always <= M_ctrl_flush_pipe_always_nxt;
+    end
+
+
+  assign A_ctrl_flush_pipe_always_nxt = M_ctrl_flush_pipe_always;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_flush_pipe_always <= 0;
+      else if (A_en)
+          A_ctrl_flush_pipe_always <= A_ctrl_flush_pipe_always_nxt;
+    end
+
+
+  assign W_ctrl_flush_pipe_always_nxt = A_ctrl_flush_pipe_always;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_flush_pipe_always <= 0;
+      else if (W_en)
+          W_ctrl_flush_pipe_always <= W_ctrl_flush_pipe_always_nxt;
+    end
+
+
+  assign D_ctrl_alu_force_xor = D_op_cmpgei|
+    D_op_cmpgeui|
+    D_op_cmpeqi|
+    D_op_cmpge|
+    D_op_cmpgeu|
+    D_op_cmpeq|
+    D_op_cmpnei|
+    D_op_cmpne|
+    D_op_bge|
+    D_op_op_rsv10|
+    D_op_bgeu|
+    D_op_op_rsv42|
+    D_op_beq|
+    D_op_op_rsv34|
+    D_op_bne|
+    D_op_op_rsv62;
+
+  assign E_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_alu_force_xor <= 0;
+      else if (E_en)
+          E_ctrl_alu_force_xor <= E_ctrl_alu_force_xor_nxt;
+    end
+
+
+  assign M_ctrl_alu_force_xor_nxt = E_ctrl_alu_force_xor;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_alu_force_xor <= 0;
+      else if (M_en)
+          M_ctrl_alu_force_xor <= M_ctrl_alu_force_xor_nxt;
+    end
+
+
+  assign A_ctrl_alu_force_xor_nxt = M_ctrl_alu_force_xor;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_alu_force_xor <= 0;
+      else if (A_en)
+          A_ctrl_alu_force_xor <= A_ctrl_alu_force_xor_nxt;
+    end
+
+
+  assign W_ctrl_alu_force_xor_nxt = A_ctrl_alu_force_xor;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_alu_force_xor <= 0;
+      else if (W_en)
+          W_ctrl_alu_force_xor <= W_ctrl_alu_force_xor_nxt;
+    end
+
+
+  assign D_ctrl_alu_force_and = 1'b0;
+  assign E_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_alu_force_and <= 0;
+      else if (E_en)
+          E_ctrl_alu_force_and <= E_ctrl_alu_force_and_nxt;
+    end
+
+
+  assign M_ctrl_alu_force_and_nxt = E_ctrl_alu_force_and;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_alu_force_and <= 0;
+      else if (M_en)
+          M_ctrl_alu_force_and <= M_ctrl_alu_force_and_nxt;
+    end
+
+
+  assign A_ctrl_alu_force_and_nxt = M_ctrl_alu_force_and;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_alu_force_and <= 0;
+      else if (A_en)
+          A_ctrl_alu_force_and <= A_ctrl_alu_force_and_nxt;
+    end
+
+
+  assign W_ctrl_alu_force_and_nxt = A_ctrl_alu_force_and;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_alu_force_and <= 0;
+      else if (W_en)
+          W_ctrl_alu_force_and <= W_ctrl_alu_force_and_nxt;
+    end
+
+
+  assign D_ctrl_late_result = D_op_ldb|
+    D_op_ldh|
+    D_op_ldl|
+    D_op_ldw|
+    D_op_ldbio|
+    D_op_ldhio|
+    D_op_ldwio|
+    D_op_op_rsv63|
+    D_op_ldbu|
+    D_op_ldhu|
+    D_op_ldbuio|
+    D_op_ldhuio|
+    D_op_slli|
+    D_op_opx_rsv50|
+    D_op_sll|
+    D_op_opx_rsv51|
+    D_op_roli|
+    D_op_opx_rsv34|
+    D_op_rol|
+    D_op_opx_rsv35|
+    D_op_srli|
+    D_op_srl|
+    D_op_srai|
+    D_op_sra|
+    D_op_opx_rsv10|
+    D_op_ror|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_rdctl|
+    D_op_muli|
+    D_op_mul|
+    D_op_opx_rsv47|
+    D_op_opx_rsv55|
+    D_op_opx_rsv63;
+
+  assign E_ctrl_late_result_nxt = D_ctrl_late_result;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_ctrl_late_result <= 0;
+      else if (E_en)
+          E_ctrl_late_result <= E_ctrl_late_result_nxt;
+    end
+
+
+  assign M_ctrl_late_result_nxt = E_ctrl_late_result;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_ctrl_late_result <= 0;
+      else if (M_en)
+          M_ctrl_late_result <= M_ctrl_late_result_nxt;
+    end
+
+
+  assign A_ctrl_late_result_nxt = M_ctrl_late_result;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_ctrl_late_result <= 0;
+      else if (A_en)
+          A_ctrl_late_result <= A_ctrl_late_result_nxt;
+    end
+
+
+  assign W_ctrl_late_result_nxt = A_ctrl_late_result;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ctrl_late_result <= 0;
+      else if (W_en)
+          W_ctrl_late_result <= W_ctrl_late_result_nxt;
+    end
+
+
+  assign D_exc_inst_fetch = 1'b0;
+  assign D_exc_invalidates_inst_value = 1'b0;
+  assign E_exc_trap_inst_pri15 = E_ctrl_trap_inst & !E_iw_corrupt;
+  assign M_exc_trap_inst_pri15_nxt = E_exc_trap_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_exc_trap_inst_pri15 <= 0;
+      else if (M_en)
+          M_exc_trap_inst_pri15 <= M_exc_trap_inst_pri15_nxt;
+    end
+
+
+  assign A_exc_trap_inst_pri15_nxt = (M_exc_trap_inst_pri15) & (~(M_exc_hbreak_pri1|M_exc_norm_intr_pri5));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_trap_inst_pri15 <= 0;
+      else if (A_en)
+          A_exc_trap_inst_pri15 <= A_exc_trap_inst_pri15_nxt;
+    end
+
+
+  assign W_exc_trap_inst_pri15_nxt = A_exc_trap_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_trap_inst_pri15 <= 0;
+      else if (W_en)
+          W_exc_trap_inst_pri15 <= W_exc_trap_inst_pri15_nxt;
+    end
+
+
+  assign E_exc_unimp_inst_pri15 = E_ctrl_unimp_trap & !E_iw_corrupt;
+  assign M_exc_unimp_inst_pri15_nxt = E_exc_unimp_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_exc_unimp_inst_pri15 <= 0;
+      else if (M_en)
+          M_exc_unimp_inst_pri15 <= M_exc_unimp_inst_pri15_nxt;
+    end
+
+
+  assign A_exc_unimp_inst_pri15_nxt = (M_exc_unimp_inst_pri15) & (~(M_exc_hbreak_pri1|M_exc_norm_intr_pri5));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_unimp_inst_pri15 <= 0;
+      else if (A_en)
+          A_exc_unimp_inst_pri15 <= A_exc_unimp_inst_pri15_nxt;
+    end
+
+
+  assign W_exc_unimp_inst_pri15_nxt = A_exc_unimp_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_unimp_inst_pri15 <= 0;
+      else if (W_en)
+          W_exc_unimp_inst_pri15 <= W_exc_unimp_inst_pri15_nxt;
+    end
+
+
+  assign E_exc_break_inst_pri15 = E_op_break & !E_iw_corrupt;
+  assign M_exc_break_inst_pri15_nxt = E_exc_break_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_exc_break_inst_pri15 <= 0;
+      else if (M_en)
+          M_exc_break_inst_pri15 <= M_exc_break_inst_pri15_nxt;
+    end
+
+
+  assign A_exc_break_inst_pri15_nxt = (M_exc_break_inst_pri15) & (~(M_exc_hbreak_pri1|M_exc_norm_intr_pri5));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_break_inst_pri15 <= 0;
+      else if (A_en)
+          A_exc_break_inst_pri15 <= A_exc_break_inst_pri15_nxt;
+    end
+
+
+  assign W_exc_break_inst_pri15_nxt = A_exc_break_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_break_inst_pri15 <= 0;
+      else if (W_en)
+          W_exc_break_inst_pri15 <= W_exc_break_inst_pri15_nxt;
+    end
+
+
+  assign E_exc_illegal_inst_pri15 = E_ctrl_illegal & !E_iw_corrupt;
+  assign M_exc_illegal_inst_pri15_nxt = E_exc_illegal_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          M_exc_illegal_inst_pri15 <= 0;
+      else if (M_en)
+          M_exc_illegal_inst_pri15 <= M_exc_illegal_inst_pri15_nxt;
+    end
+
+
+  assign A_exc_illegal_inst_pri15_nxt = (M_exc_illegal_inst_pri15) & (~(M_exc_hbreak_pri1|M_exc_norm_intr_pri5));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_illegal_inst_pri15 <= 0;
+      else if (A_en)
+          A_exc_illegal_inst_pri15 <= A_exc_illegal_inst_pri15_nxt;
+    end
+
+
+  assign W_exc_illegal_inst_pri15_nxt = A_exc_illegal_inst_pri15;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_illegal_inst_pri15 <= 0;
+      else if (W_en)
+          W_exc_illegal_inst_pri15 <= W_exc_illegal_inst_pri15_nxt;
+    end
+
+
+  assign E_exc_inst_fetch = 1'b0;
+  assign M_exc_hbreak_pri1 = M_hbreak_req;
+  assign A_exc_hbreak_pri1_nxt = M_exc_hbreak_pri1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_hbreak_pri1 <= 0;
+      else if (A_en)
+          A_exc_hbreak_pri1 <= A_exc_hbreak_pri1_nxt;
+    end
+
+
+  assign W_exc_hbreak_pri1_nxt = A_exc_hbreak_pri1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_hbreak_pri1 <= 0;
+      else if (W_en)
+          W_exc_hbreak_pri1 <= W_exc_hbreak_pri1_nxt;
+    end
+
+
+  assign M_exc_norm_intr_pri5 = (M_norm_intr_req) & (~(M_exc_hbreak_pri1));
+  assign A_exc_norm_intr_pri5_nxt = M_exc_norm_intr_pri5;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_exc_norm_intr_pri5 <= 0;
+      else if (A_en)
+          A_exc_norm_intr_pri5 <= A_exc_norm_intr_pri5_nxt;
+    end
+
+
+  assign W_exc_norm_intr_pri5_nxt = A_exc_norm_intr_pri5;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_norm_intr_pri5 <= 0;
+      else if (W_en)
+          W_exc_norm_intr_pri5 <= W_exc_norm_intr_pri5_nxt;
+    end
+
+
+  assign M_exc_inst_fetch = 1'b0;
+  assign M_exc_any = M_exc_trap_inst_pri15|M_exc_unimp_inst_pri15|M_exc_break_inst_pri15|M_exc_illegal_inst_pri15|M_exc_hbreak_pri1|M_exc_norm_intr_pri5;
+  assign A_exc_inst_fetch = 1'b0;
+  assign A_exc_highest_pri_cause_code = (A_exc_norm_intr_pri5)? 2 :
+    (A_exc_trap_inst_pri15)? 3 :
+    (A_exc_illegal_inst_pri15)? 5 :
+    4;
+
+  assign A_exc_highest_pri_exc_id = (A_exc_hbreak_pri1)? 2 :
+    (A_exc_norm_intr_pri5)? 4 :
+    (A_exc_trap_inst_pri15)? 5 :
+    (A_exc_illegal_inst_pri15)? 7 :
+    (A_exc_unimp_inst_pri15)? 6 :
+    8;
+
+  assign A_exc_highest_pri_baddr = 0;
+  assign A_exc_record_baddr = 0;
+  //data_master, which is an e_avalon_master
+  //instruction_master, which is an e_avalon_master
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign F_inst = (F_op_call)? 56'h20202063616c6c :
+    (F_op_jmpi)? 56'h2020206a6d7069 :
+    (F_op_ldbu)? 56'h2020206c646275 :
+    (F_op_addi)? 56'h20202061646469 :
+    (F_op_stb)? 56'h20202020737462 :
+    (F_op_br)? 56'h20202020206272 :
+    (F_op_ldb)? 56'h202020206c6462 :
+    (F_op_cmpgei)? 56'h20636d70676569 :
+    (F_op_ldhu)? 56'h2020206c646875 :
+    (F_op_andi)? 56'h202020616e6469 :
+    (F_op_sth)? 56'h20202020737468 :
+    (F_op_bge)? 56'h20202020626765 :
+    (F_op_ldh)? 56'h202020206c6468 :
+    (F_op_cmplti)? 56'h20636d706c7469 :
+    (F_op_initda)? 56'h20696e69746461 :
+    (F_op_ori)? 56'h202020206f7269 :
+    (F_op_stw)? 56'h20202020737477 :
+    (F_op_blt)? 56'h20202020626c74 :
+    (F_op_ldw)? 56'h202020206c6477 :
+    (F_op_cmpnei)? 56'h20636d706e6569 :
+    (F_op_flushda)? 56'h666c7573686461 :
+    (F_op_xori)? 56'h202020786f7269 :
+    (F_op_bne)? 56'h20202020626e65 :
+    (F_op_cmpeqi)? 56'h20636d70657169 :
+    (F_op_ldbuio)? 56'h206c646275696f :
+    (F_op_muli)? 56'h2020206d756c69 :
+    (F_op_stbio)? 56'h2020737462696f :
+    (F_op_beq)? 56'h20202020626571 :
+    (F_op_ldbio)? 56'h20206c6462696f :
+    (F_op_cmpgeui)? 56'h636d7067657569 :
+    (F_op_ldhuio)? 56'h206c646875696f :
+    (F_op_andhi)? 56'h2020616e646869 :
+    (F_op_sthio)? 56'h2020737468696f :
+    (F_op_bgeu)? 56'h20202062676575 :
+    (F_op_ldhio)? 56'h20206c6468696f :
+    (F_op_cmpltui)? 56'h636d706c747569 :
+    (F_op_custom)? 56'h20637573746f6d :
+    (F_op_initd)? 56'h2020696e697464 :
+    (F_op_orhi)? 56'h2020206f726869 :
+    (F_op_stwio)? 56'h2020737477696f :
+    (F_op_bltu)? 56'h202020626c7475 :
+    (F_op_ldwio)? 56'h20206c6477696f :
+    (F_op_flushd)? 56'h20666c75736864 :
+    (F_op_xorhi)? 56'h2020786f726869 :
+    (F_op_eret)? 56'h20202065726574 :
+    (F_op_roli)? 56'h202020726f6c69 :
+    (F_op_rol)? 56'h20202020726f6c :
+    (F_op_flushp)? 56'h20666c75736870 :
+    (F_op_ret)? 56'h20202020726574 :
+    (F_op_nor)? 56'h202020206e6f72 :
+    (F_op_mulxuu)? 56'h206d756c787575 :
+    (F_op_cmpge)? 56'h2020636d706765 :
+    (F_op_bret)? 56'h20202062726574 :
+    (F_op_ror)? 56'h20202020726f72 :
+    (F_op_flushi)? 56'h20666c75736869 :
+    (F_op_jmp)? 56'h202020206a6d70 :
+    (F_op_and)? 56'h20202020616e64 :
+    (F_op_cmplt)? 56'h2020636d706c74 :
+    (F_op_slli)? 56'h202020736c6c69 :
+    (F_op_sll)? 56'h20202020736c6c :
+    (F_op_or)? 56'h20202020206f72 :
+    (F_op_mulxsu)? 56'h206d756c787375 :
+    (F_op_cmpne)? 56'h2020636d706e65 :
+    (F_op_srli)? 56'h20202073726c69 :
+    (F_op_srl)? 56'h2020202073726c :
+    (F_op_nextpc)? 56'h206e6578747063 :
+    (F_op_callr)? 56'h202063616c6c72 :
+    (F_op_xor)? 56'h20202020786f72 :
+    (F_op_mulxss)? 56'h206d756c787373 :
+    (F_op_cmpeq)? 56'h2020636d706571 :
+    (F_op_divu)? 56'h20202064697675 :
+    (F_op_div)? 56'h20202020646976 :
+    (F_op_rdctl)? 56'h2020726463746c :
+    (F_op_mul)? 56'h202020206d756c :
+    (F_op_cmpgeu)? 56'h20636d70676575 :
+    (F_op_initi)? 56'h2020696e697469 :
+    (F_op_trap)? 56'h20202074726170 :
+    (F_op_wrctl)? 56'h2020777263746c :
+    (F_op_cmpltu)? 56'h20636d706c7475 :
+    (F_op_add)? 56'h20202020616464 :
+    (F_op_break)? 56'h2020627265616b :
+    (F_op_sync)? 56'h20202073796e63 :
+    (F_op_sub)? 56'h20202020737562 :
+    (F_op_srai)? 56'h20202073726169 :
+    (F_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign D_inst = (D_op_call)? 56'h20202063616c6c :
+    (D_op_jmpi)? 56'h2020206a6d7069 :
+    (D_op_ldbu)? 56'h2020206c646275 :
+    (D_op_addi)? 56'h20202061646469 :
+    (D_op_stb)? 56'h20202020737462 :
+    (D_op_br)? 56'h20202020206272 :
+    (D_op_ldb)? 56'h202020206c6462 :
+    (D_op_cmpgei)? 56'h20636d70676569 :
+    (D_op_ldhu)? 56'h2020206c646875 :
+    (D_op_andi)? 56'h202020616e6469 :
+    (D_op_sth)? 56'h20202020737468 :
+    (D_op_bge)? 56'h20202020626765 :
+    (D_op_ldh)? 56'h202020206c6468 :
+    (D_op_cmplti)? 56'h20636d706c7469 :
+    (D_op_initda)? 56'h20696e69746461 :
+    (D_op_ori)? 56'h202020206f7269 :
+    (D_op_stw)? 56'h20202020737477 :
+    (D_op_blt)? 56'h20202020626c74 :
+    (D_op_ldw)? 56'h202020206c6477 :
+    (D_op_cmpnei)? 56'h20636d706e6569 :
+    (D_op_flushda)? 56'h666c7573686461 :
+    (D_op_xori)? 56'h202020786f7269 :
+    (D_op_bne)? 56'h20202020626e65 :
+    (D_op_cmpeqi)? 56'h20636d70657169 :
+    (D_op_ldbuio)? 56'h206c646275696f :
+    (D_op_muli)? 56'h2020206d756c69 :
+    (D_op_stbio)? 56'h2020737462696f :
+    (D_op_beq)? 56'h20202020626571 :
+    (D_op_ldbio)? 56'h20206c6462696f :
+    (D_op_cmpgeui)? 56'h636d7067657569 :
+    (D_op_ldhuio)? 56'h206c646875696f :
+    (D_op_andhi)? 56'h2020616e646869 :
+    (D_op_sthio)? 56'h2020737468696f :
+    (D_op_bgeu)? 56'h20202062676575 :
+    (D_op_ldhio)? 56'h20206c6468696f :
+    (D_op_cmpltui)? 56'h636d706c747569 :
+    (D_op_custom)? 56'h20637573746f6d :
+    (D_op_initd)? 56'h2020696e697464 :
+    (D_op_orhi)? 56'h2020206f726869 :
+    (D_op_stwio)? 56'h2020737477696f :
+    (D_op_bltu)? 56'h202020626c7475 :
+    (D_op_ldwio)? 56'h20206c6477696f :
+    (D_op_flushd)? 56'h20666c75736864 :
+    (D_op_xorhi)? 56'h2020786f726869 :
+    (D_op_eret)? 56'h20202065726574 :
+    (D_op_roli)? 56'h202020726f6c69 :
+    (D_op_rol)? 56'h20202020726f6c :
+    (D_op_flushp)? 56'h20666c75736870 :
+    (D_op_ret)? 56'h20202020726574 :
+    (D_op_nor)? 56'h202020206e6f72 :
+    (D_op_mulxuu)? 56'h206d756c787575 :
+    (D_op_cmpge)? 56'h2020636d706765 :
+    (D_op_bret)? 56'h20202062726574 :
+    (D_op_ror)? 56'h20202020726f72 :
+    (D_op_flushi)? 56'h20666c75736869 :
+    (D_op_jmp)? 56'h202020206a6d70 :
+    (D_op_and)? 56'h20202020616e64 :
+    (D_op_cmplt)? 56'h2020636d706c74 :
+    (D_op_slli)? 56'h202020736c6c69 :
+    (D_op_sll)? 56'h20202020736c6c :
+    (D_op_or)? 56'h20202020206f72 :
+    (D_op_mulxsu)? 56'h206d756c787375 :
+    (D_op_cmpne)? 56'h2020636d706e65 :
+    (D_op_srli)? 56'h20202073726c69 :
+    (D_op_srl)? 56'h2020202073726c :
+    (D_op_nextpc)? 56'h206e6578747063 :
+    (D_op_callr)? 56'h202063616c6c72 :
+    (D_op_xor)? 56'h20202020786f72 :
+    (D_op_mulxss)? 56'h206d756c787373 :
+    (D_op_cmpeq)? 56'h2020636d706571 :
+    (D_op_divu)? 56'h20202064697675 :
+    (D_op_div)? 56'h20202020646976 :
+    (D_op_rdctl)? 56'h2020726463746c :
+    (D_op_mul)? 56'h202020206d756c :
+    (D_op_cmpgeu)? 56'h20636d70676575 :
+    (D_op_initi)? 56'h2020696e697469 :
+    (D_op_trap)? 56'h20202074726170 :
+    (D_op_wrctl)? 56'h2020777263746c :
+    (D_op_cmpltu)? 56'h20636d706c7475 :
+    (D_op_add)? 56'h20202020616464 :
+    (D_op_break)? 56'h2020627265616b :
+    (D_op_sync)? 56'h20202073796e63 :
+    (D_op_sub)? 56'h20202020737562 :
+    (D_op_srai)? 56'h20202073726169 :
+    (D_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign E_inst = (E_op_call)? 56'h20202063616c6c :
+    (E_op_jmpi)? 56'h2020206a6d7069 :
+    (E_op_ldbu)? 56'h2020206c646275 :
+    (E_op_addi)? 56'h20202061646469 :
+    (E_op_stb)? 56'h20202020737462 :
+    (E_op_br)? 56'h20202020206272 :
+    (E_op_ldb)? 56'h202020206c6462 :
+    (E_op_cmpgei)? 56'h20636d70676569 :
+    (E_op_ldhu)? 56'h2020206c646875 :
+    (E_op_andi)? 56'h202020616e6469 :
+    (E_op_sth)? 56'h20202020737468 :
+    (E_op_bge)? 56'h20202020626765 :
+    (E_op_ldh)? 56'h202020206c6468 :
+    (E_op_cmplti)? 56'h20636d706c7469 :
+    (E_op_initda)? 56'h20696e69746461 :
+    (E_op_ori)? 56'h202020206f7269 :
+    (E_op_stw)? 56'h20202020737477 :
+    (E_op_blt)? 56'h20202020626c74 :
+    (E_op_ldw)? 56'h202020206c6477 :
+    (E_op_cmpnei)? 56'h20636d706e6569 :
+    (E_op_flushda)? 56'h666c7573686461 :
+    (E_op_xori)? 56'h202020786f7269 :
+    (E_op_bne)? 56'h20202020626e65 :
+    (E_op_cmpeqi)? 56'h20636d70657169 :
+    (E_op_ldbuio)? 56'h206c646275696f :
+    (E_op_muli)? 56'h2020206d756c69 :
+    (E_op_stbio)? 56'h2020737462696f :
+    (E_op_beq)? 56'h20202020626571 :
+    (E_op_ldbio)? 56'h20206c6462696f :
+    (E_op_cmpgeui)? 56'h636d7067657569 :
+    (E_op_ldhuio)? 56'h206c646875696f :
+    (E_op_andhi)? 56'h2020616e646869 :
+    (E_op_sthio)? 56'h2020737468696f :
+    (E_op_bgeu)? 56'h20202062676575 :
+    (E_op_ldhio)? 56'h20206c6468696f :
+    (E_op_cmpltui)? 56'h636d706c747569 :
+    (E_op_custom)? 56'h20637573746f6d :
+    (E_op_initd)? 56'h2020696e697464 :
+    (E_op_orhi)? 56'h2020206f726869 :
+    (E_op_stwio)? 56'h2020737477696f :
+    (E_op_bltu)? 56'h202020626c7475 :
+    (E_op_ldwio)? 56'h20206c6477696f :
+    (E_op_flushd)? 56'h20666c75736864 :
+    (E_op_xorhi)? 56'h2020786f726869 :
+    (E_op_eret)? 56'h20202065726574 :
+    (E_op_roli)? 56'h202020726f6c69 :
+    (E_op_rol)? 56'h20202020726f6c :
+    (E_op_flushp)? 56'h20666c75736870 :
+    (E_op_ret)? 56'h20202020726574 :
+    (E_op_nor)? 56'h202020206e6f72 :
+    (E_op_mulxuu)? 56'h206d756c787575 :
+    (E_op_cmpge)? 56'h2020636d706765 :
+    (E_op_bret)? 56'h20202062726574 :
+    (E_op_ror)? 56'h20202020726f72 :
+    (E_op_flushi)? 56'h20666c75736869 :
+    (E_op_jmp)? 56'h202020206a6d70 :
+    (E_op_and)? 56'h20202020616e64 :
+    (E_op_cmplt)? 56'h2020636d706c74 :
+    (E_op_slli)? 56'h202020736c6c69 :
+    (E_op_sll)? 56'h20202020736c6c :
+    (E_op_or)? 56'h20202020206f72 :
+    (E_op_mulxsu)? 56'h206d756c787375 :
+    (E_op_cmpne)? 56'h2020636d706e65 :
+    (E_op_srli)? 56'h20202073726c69 :
+    (E_op_srl)? 56'h2020202073726c :
+    (E_op_nextpc)? 56'h206e6578747063 :
+    (E_op_callr)? 56'h202063616c6c72 :
+    (E_op_xor)? 56'h20202020786f72 :
+    (E_op_mulxss)? 56'h206d756c787373 :
+    (E_op_cmpeq)? 56'h2020636d706571 :
+    (E_op_divu)? 56'h20202064697675 :
+    (E_op_div)? 56'h20202020646976 :
+    (E_op_rdctl)? 56'h2020726463746c :
+    (E_op_mul)? 56'h202020206d756c :
+    (E_op_cmpgeu)? 56'h20636d70676575 :
+    (E_op_initi)? 56'h2020696e697469 :
+    (E_op_trap)? 56'h20202074726170 :
+    (E_op_wrctl)? 56'h2020777263746c :
+    (E_op_cmpltu)? 56'h20636d706c7475 :
+    (E_op_add)? 56'h20202020616464 :
+    (E_op_break)? 56'h2020627265616b :
+    (E_op_sync)? 56'h20202073796e63 :
+    (E_op_sub)? 56'h20202020737562 :
+    (E_op_srai)? 56'h20202073726169 :
+    (E_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign M_inst = (M_op_call)? 56'h20202063616c6c :
+    (M_op_jmpi)? 56'h2020206a6d7069 :
+    (M_op_ldbu)? 56'h2020206c646275 :
+    (M_op_addi)? 56'h20202061646469 :
+    (M_op_stb)? 56'h20202020737462 :
+    (M_op_br)? 56'h20202020206272 :
+    (M_op_ldb)? 56'h202020206c6462 :
+    (M_op_cmpgei)? 56'h20636d70676569 :
+    (M_op_ldhu)? 56'h2020206c646875 :
+    (M_op_andi)? 56'h202020616e6469 :
+    (M_op_sth)? 56'h20202020737468 :
+    (M_op_bge)? 56'h20202020626765 :
+    (M_op_ldh)? 56'h202020206c6468 :
+    (M_op_cmplti)? 56'h20636d706c7469 :
+    (M_op_initda)? 56'h20696e69746461 :
+    (M_op_ori)? 56'h202020206f7269 :
+    (M_op_stw)? 56'h20202020737477 :
+    (M_op_blt)? 56'h20202020626c74 :
+    (M_op_ldw)? 56'h202020206c6477 :
+    (M_op_cmpnei)? 56'h20636d706e6569 :
+    (M_op_flushda)? 56'h666c7573686461 :
+    (M_op_xori)? 56'h202020786f7269 :
+    (M_op_bne)? 56'h20202020626e65 :
+    (M_op_cmpeqi)? 56'h20636d70657169 :
+    (M_op_ldbuio)? 56'h206c646275696f :
+    (M_op_muli)? 56'h2020206d756c69 :
+    (M_op_stbio)? 56'h2020737462696f :
+    (M_op_beq)? 56'h20202020626571 :
+    (M_op_ldbio)? 56'h20206c6462696f :
+    (M_op_cmpgeui)? 56'h636d7067657569 :
+    (M_op_ldhuio)? 56'h206c646875696f :
+    (M_op_andhi)? 56'h2020616e646869 :
+    (M_op_sthio)? 56'h2020737468696f :
+    (M_op_bgeu)? 56'h20202062676575 :
+    (M_op_ldhio)? 56'h20206c6468696f :
+    (M_op_cmpltui)? 56'h636d706c747569 :
+    (M_op_custom)? 56'h20637573746f6d :
+    (M_op_initd)? 56'h2020696e697464 :
+    (M_op_orhi)? 56'h2020206f726869 :
+    (M_op_stwio)? 56'h2020737477696f :
+    (M_op_bltu)? 56'h202020626c7475 :
+    (M_op_ldwio)? 56'h20206c6477696f :
+    (M_op_flushd)? 56'h20666c75736864 :
+    (M_op_xorhi)? 56'h2020786f726869 :
+    (M_op_eret)? 56'h20202065726574 :
+    (M_op_roli)? 56'h202020726f6c69 :
+    (M_op_rol)? 56'h20202020726f6c :
+    (M_op_flushp)? 56'h20666c75736870 :
+    (M_op_ret)? 56'h20202020726574 :
+    (M_op_nor)? 56'h202020206e6f72 :
+    (M_op_mulxuu)? 56'h206d756c787575 :
+    (M_op_cmpge)? 56'h2020636d706765 :
+    (M_op_bret)? 56'h20202062726574 :
+    (M_op_ror)? 56'h20202020726f72 :
+    (M_op_flushi)? 56'h20666c75736869 :
+    (M_op_jmp)? 56'h202020206a6d70 :
+    (M_op_and)? 56'h20202020616e64 :
+    (M_op_cmplt)? 56'h2020636d706c74 :
+    (M_op_slli)? 56'h202020736c6c69 :
+    (M_op_sll)? 56'h20202020736c6c :
+    (M_op_or)? 56'h20202020206f72 :
+    (M_op_mulxsu)? 56'h206d756c787375 :
+    (M_op_cmpne)? 56'h2020636d706e65 :
+    (M_op_srli)? 56'h20202073726c69 :
+    (M_op_srl)? 56'h2020202073726c :
+    (M_op_nextpc)? 56'h206e6578747063 :
+    (M_op_callr)? 56'h202063616c6c72 :
+    (M_op_xor)? 56'h20202020786f72 :
+    (M_op_mulxss)? 56'h206d756c787373 :
+    (M_op_cmpeq)? 56'h2020636d706571 :
+    (M_op_divu)? 56'h20202064697675 :
+    (M_op_div)? 56'h20202020646976 :
+    (M_op_rdctl)? 56'h2020726463746c :
+    (M_op_mul)? 56'h202020206d756c :
+    (M_op_cmpgeu)? 56'h20636d70676575 :
+    (M_op_initi)? 56'h2020696e697469 :
+    (M_op_trap)? 56'h20202074726170 :
+    (M_op_wrctl)? 56'h2020777263746c :
+    (M_op_cmpltu)? 56'h20636d706c7475 :
+    (M_op_add)? 56'h20202020616464 :
+    (M_op_break)? 56'h2020627265616b :
+    (M_op_sync)? 56'h20202073796e63 :
+    (M_op_sub)? 56'h20202020737562 :
+    (M_op_srai)? 56'h20202073726169 :
+    (M_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign A_inst = (A_op_call)? 56'h20202063616c6c :
+    (A_op_jmpi)? 56'h2020206a6d7069 :
+    (A_op_ldbu)? 56'h2020206c646275 :
+    (A_op_addi)? 56'h20202061646469 :
+    (A_op_stb)? 56'h20202020737462 :
+    (A_op_br)? 56'h20202020206272 :
+    (A_op_ldb)? 56'h202020206c6462 :
+    (A_op_cmpgei)? 56'h20636d70676569 :
+    (A_op_ldhu)? 56'h2020206c646875 :
+    (A_op_andi)? 56'h202020616e6469 :
+    (A_op_sth)? 56'h20202020737468 :
+    (A_op_bge)? 56'h20202020626765 :
+    (A_op_ldh)? 56'h202020206c6468 :
+    (A_op_cmplti)? 56'h20636d706c7469 :
+    (A_op_initda)? 56'h20696e69746461 :
+    (A_op_ori)? 56'h202020206f7269 :
+    (A_op_stw)? 56'h20202020737477 :
+    (A_op_blt)? 56'h20202020626c74 :
+    (A_op_ldw)? 56'h202020206c6477 :
+    (A_op_cmpnei)? 56'h20636d706e6569 :
+    (A_op_flushda)? 56'h666c7573686461 :
+    (A_op_xori)? 56'h202020786f7269 :
+    (A_op_bne)? 56'h20202020626e65 :
+    (A_op_cmpeqi)? 56'h20636d70657169 :
+    (A_op_ldbuio)? 56'h206c646275696f :
+    (A_op_muli)? 56'h2020206d756c69 :
+    (A_op_stbio)? 56'h2020737462696f :
+    (A_op_beq)? 56'h20202020626571 :
+    (A_op_ldbio)? 56'h20206c6462696f :
+    (A_op_cmpgeui)? 56'h636d7067657569 :
+    (A_op_ldhuio)? 56'h206c646875696f :
+    (A_op_andhi)? 56'h2020616e646869 :
+    (A_op_sthio)? 56'h2020737468696f :
+    (A_op_bgeu)? 56'h20202062676575 :
+    (A_op_ldhio)? 56'h20206c6468696f :
+    (A_op_cmpltui)? 56'h636d706c747569 :
+    (A_op_custom)? 56'h20637573746f6d :
+    (A_op_initd)? 56'h2020696e697464 :
+    (A_op_orhi)? 56'h2020206f726869 :
+    (A_op_stwio)? 56'h2020737477696f :
+    (A_op_bltu)? 56'h202020626c7475 :
+    (A_op_ldwio)? 56'h20206c6477696f :
+    (A_op_flushd)? 56'h20666c75736864 :
+    (A_op_xorhi)? 56'h2020786f726869 :
+    (A_op_eret)? 56'h20202065726574 :
+    (A_op_roli)? 56'h202020726f6c69 :
+    (A_op_rol)? 56'h20202020726f6c :
+    (A_op_flushp)? 56'h20666c75736870 :
+    (A_op_ret)? 56'h20202020726574 :
+    (A_op_nor)? 56'h202020206e6f72 :
+    (A_op_mulxuu)? 56'h206d756c787575 :
+    (A_op_cmpge)? 56'h2020636d706765 :
+    (A_op_bret)? 56'h20202062726574 :
+    (A_op_ror)? 56'h20202020726f72 :
+    (A_op_flushi)? 56'h20666c75736869 :
+    (A_op_jmp)? 56'h202020206a6d70 :
+    (A_op_and)? 56'h20202020616e64 :
+    (A_op_cmplt)? 56'h2020636d706c74 :
+    (A_op_slli)? 56'h202020736c6c69 :
+    (A_op_sll)? 56'h20202020736c6c :
+    (A_op_or)? 56'h20202020206f72 :
+    (A_op_mulxsu)? 56'h206d756c787375 :
+    (A_op_cmpne)? 56'h2020636d706e65 :
+    (A_op_srli)? 56'h20202073726c69 :
+    (A_op_srl)? 56'h2020202073726c :
+    (A_op_nextpc)? 56'h206e6578747063 :
+    (A_op_callr)? 56'h202063616c6c72 :
+    (A_op_xor)? 56'h20202020786f72 :
+    (A_op_mulxss)? 56'h206d756c787373 :
+    (A_op_cmpeq)? 56'h2020636d706571 :
+    (A_op_divu)? 56'h20202064697675 :
+    (A_op_div)? 56'h20202020646976 :
+    (A_op_rdctl)? 56'h2020726463746c :
+    (A_op_mul)? 56'h202020206d756c :
+    (A_op_cmpgeu)? 56'h20636d70676575 :
+    (A_op_initi)? 56'h2020696e697469 :
+    (A_op_trap)? 56'h20202074726170 :
+    (A_op_wrctl)? 56'h2020777263746c :
+    (A_op_cmpltu)? 56'h20636d706c7475 :
+    (A_op_add)? 56'h20202020616464 :
+    (A_op_break)? 56'h2020627265616b :
+    (A_op_sync)? 56'h20202073796e63 :
+    (A_op_sub)? 56'h20202020737562 :
+    (A_op_srai)? 56'h20202073726169 :
+    (A_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign W_inst = (W_op_call)? 56'h20202063616c6c :
+    (W_op_jmpi)? 56'h2020206a6d7069 :
+    (W_op_ldbu)? 56'h2020206c646275 :
+    (W_op_addi)? 56'h20202061646469 :
+    (W_op_stb)? 56'h20202020737462 :
+    (W_op_br)? 56'h20202020206272 :
+    (W_op_ldb)? 56'h202020206c6462 :
+    (W_op_cmpgei)? 56'h20636d70676569 :
+    (W_op_ldhu)? 56'h2020206c646875 :
+    (W_op_andi)? 56'h202020616e6469 :
+    (W_op_sth)? 56'h20202020737468 :
+    (W_op_bge)? 56'h20202020626765 :
+    (W_op_ldh)? 56'h202020206c6468 :
+    (W_op_cmplti)? 56'h20636d706c7469 :
+    (W_op_initda)? 56'h20696e69746461 :
+    (W_op_ori)? 56'h202020206f7269 :
+    (W_op_stw)? 56'h20202020737477 :
+    (W_op_blt)? 56'h20202020626c74 :
+    (W_op_ldw)? 56'h202020206c6477 :
+    (W_op_cmpnei)? 56'h20636d706e6569 :
+    (W_op_flushda)? 56'h666c7573686461 :
+    (W_op_xori)? 56'h202020786f7269 :
+    (W_op_bne)? 56'h20202020626e65 :
+    (W_op_cmpeqi)? 56'h20636d70657169 :
+    (W_op_ldbuio)? 56'h206c646275696f :
+    (W_op_muli)? 56'h2020206d756c69 :
+    (W_op_stbio)? 56'h2020737462696f :
+    (W_op_beq)? 56'h20202020626571 :
+    (W_op_ldbio)? 56'h20206c6462696f :
+    (W_op_cmpgeui)? 56'h636d7067657569 :
+    (W_op_ldhuio)? 56'h206c646875696f :
+    (W_op_andhi)? 56'h2020616e646869 :
+    (W_op_sthio)? 56'h2020737468696f :
+    (W_op_bgeu)? 56'h20202062676575 :
+    (W_op_ldhio)? 56'h20206c6468696f :
+    (W_op_cmpltui)? 56'h636d706c747569 :
+    (W_op_custom)? 56'h20637573746f6d :
+    (W_op_initd)? 56'h2020696e697464 :
+    (W_op_orhi)? 56'h2020206f726869 :
+    (W_op_stwio)? 56'h2020737477696f :
+    (W_op_bltu)? 56'h202020626c7475 :
+    (W_op_ldwio)? 56'h20206c6477696f :
+    (W_op_flushd)? 56'h20666c75736864 :
+    (W_op_xorhi)? 56'h2020786f726869 :
+    (W_op_eret)? 56'h20202065726574 :
+    (W_op_roli)? 56'h202020726f6c69 :
+    (W_op_rol)? 56'h20202020726f6c :
+    (W_op_flushp)? 56'h20666c75736870 :
+    (W_op_ret)? 56'h20202020726574 :
+    (W_op_nor)? 56'h202020206e6f72 :
+    (W_op_mulxuu)? 56'h206d756c787575 :
+    (W_op_cmpge)? 56'h2020636d706765 :
+    (W_op_bret)? 56'h20202062726574 :
+    (W_op_ror)? 56'h20202020726f72 :
+    (W_op_flushi)? 56'h20666c75736869 :
+    (W_op_jmp)? 56'h202020206a6d70 :
+    (W_op_and)? 56'h20202020616e64 :
+    (W_op_cmplt)? 56'h2020636d706c74 :
+    (W_op_slli)? 56'h202020736c6c69 :
+    (W_op_sll)? 56'h20202020736c6c :
+    (W_op_or)? 56'h20202020206f72 :
+    (W_op_mulxsu)? 56'h206d756c787375 :
+    (W_op_cmpne)? 56'h2020636d706e65 :
+    (W_op_srli)? 56'h20202073726c69 :
+    (W_op_srl)? 56'h2020202073726c :
+    (W_op_nextpc)? 56'h206e6578747063 :
+    (W_op_callr)? 56'h202063616c6c72 :
+    (W_op_xor)? 56'h20202020786f72 :
+    (W_op_mulxss)? 56'h206d756c787373 :
+    (W_op_cmpeq)? 56'h2020636d706571 :
+    (W_op_divu)? 56'h20202064697675 :
+    (W_op_div)? 56'h20202020646976 :
+    (W_op_rdctl)? 56'h2020726463746c :
+    (W_op_mul)? 56'h202020206d756c :
+    (W_op_cmpgeu)? 56'h20636d70676575 :
+    (W_op_initi)? 56'h2020696e697469 :
+    (W_op_trap)? 56'h20202074726170 :
+    (W_op_wrctl)? 56'h2020777263746c :
+    (W_op_cmpltu)? 56'h20636d706c7475 :
+    (W_op_add)? 56'h20202020616464 :
+    (W_op_break)? 56'h2020627265616b :
+    (W_op_sync)? 56'h20202073796e63 :
+    (W_op_sub)? 56'h20202020737562 :
+    (W_op_srai)? 56'h20202073726169 :
+    (W_op_sra)? 56'h20202020737261 :
+    56'h20202020424144;
+
+  assign F_vinst = F_iw_valid ? F_inst : {9{8'h2d}};
+  assign D_vinst = D_issue ? D_inst : {9{8'h2d}};
+  assign E_vinst = E_valid ? E_inst : {9{8'h2d}};
+  assign M_vinst = M_valid ? M_inst : {9{8'h2d}};
+  assign A_vinst = A_valid ? A_inst : {9{8'h2d}};
+  assign W_vinst = W_valid ? W_inst : {9{8'h2d}};
+  //Clearing 'X' data bits
+  assign D_ic_want_fill_unfiltered_is_x = ^(D_ic_want_fill_unfiltered) === 1'bx;
+
+  assign D_ic_want_fill = D_ic_want_fill_unfiltered_is_x ? 1'b0 : D_ic_want_fill_unfiltered;
+  //Clearing 'X' data bits
+  assign D_rdprs_stall_unfiltered_is_x = ^(D_rdprs_stall_unfiltered) === 1'bx;
+
+  assign D_rdprs_stall = (D_rdprs_stall_unfiltered_is_x & (D_exc_invalidates_inst_value)) ? 1'b0 : D_rdprs_stall_unfiltered;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  
+//  assign D_ic_want_fill = D_ic_want_fill_unfiltered;
+//
+//  
+//  assign D_rdprs_stall = D_rdprs_stall_unfiltered;
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif
new file mode 100644
index 0000000..2701855
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif
@@ -0,0 +1,267 @@
+-- Contents are randomly generated during RTL generation.
+WIDTH=2;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : 3;
+01 : 3;
+02 : 0;
+03 : 1;
+04 : 1;
+05 : 3;
+06 : 1;
+07 : 2;
+08 : 3;
+09 : 0;
+0a : 2;
+0b : 1;
+0c : 0;
+0d : 2;
+0e : 2;
+0f : 0;
+10 : 2;
+11 : 3;
+12 : 3;
+13 : 3;
+14 : 0;
+15 : 3;
+16 : 2;
+17 : 2;
+18 : 0;
+19 : 0;
+1a : 2;
+1b : 0;
+1c : 3;
+1d : 3;
+1e : 3;
+1f : 0;
+20 : 0;
+21 : 0;
+22 : 3;
+23 : 1;
+24 : 3;
+25 : 1;
+26 : 0;
+27 : 1;
+28 : 3;
+29 : 0;
+2a : 3;
+2b : 1;
+2c : 2;
+2d : 2;
+2e : 2;
+2f : 0;
+30 : 2;
+31 : 0;
+32 : 1;
+33 : 2;
+34 : 3;
+35 : 0;
+36 : 1;
+37 : 0;
+38 : 3;
+39 : 0;
+3a : 3;
+3b : 0;
+3c : 2;
+3d : 0;
+3e : 1;
+3f : 1;
+40 : 2;
+41 : 1;
+42 : 1;
+43 : 3;
+44 : 0;
+45 : 3;
+46 : 3;
+47 : 0;
+48 : 3;
+49 : 2;
+4a : 2;
+4b : 1;
+4c : 0;
+4d : 3;
+4e : 2;
+4f : 1;
+50 : 0;
+51 : 1;
+52 : 2;
+53 : 2;
+54 : 0;
+55 : 3;
+56 : 2;
+57 : 1;
+58 : 3;
+59 : 2;
+5a : 3;
+5b : 1;
+5c : 2;
+5d : 2;
+5e : 0;
+5f : 0;
+60 : 2;
+61 : 0;
+62 : 2;
+63 : 2;
+64 : 3;
+65 : 0;
+66 : 2;
+67 : 2;
+68 : 0;
+69 : 2;
+6a : 3;
+6b : 1;
+6c : 3;
+6d : 1;
+6e : 1;
+6f : 3;
+70 : 0;
+71 : 2;
+72 : 3;
+73 : 0;
+74 : 0;
+75 : 3;
+76 : 3;
+77 : 3;
+78 : 2;
+79 : 0;
+7a : 3;
+7b : 0;
+7c : 3;
+7d : 3;
+7e : 1;
+7f : 3;
+80 : 1;
+81 : 2;
+82 : 0;
+83 : 2;
+84 : 2;
+85 : 1;
+86 : 3;
+87 : 1;
+88 : 2;
+89 : 2;
+8a : 2;
+8b : 0;
+8c : 0;
+8d : 3;
+8e : 3;
+8f : 1;
+90 : 1;
+91 : 0;
+92 : 2;
+93 : 0;
+94 : 1;
+95 : 3;
+96 : 2;
+97 : 2;
+98 : 0;
+99 : 2;
+9a : 1;
+9b : 2;
+9c : 2;
+9d : 3;
+9e : 1;
+9f : 0;
+a0 : 1;
+a1 : 0;
+a2 : 2;
+a3 : 3;
+a4 : 2;
+a5 : 1;
+a6 : 3;
+a7 : 1;
+a8 : 1;
+a9 : 1;
+aa : 3;
+ab : 0;
+ac : 2;
+ad : 3;
+ae : 3;
+af : 0;
+b0 : 2;
+b1 : 0;
+b2 : 2;
+b3 : 2;
+b4 : 1;
+b5 : 0;
+b6 : 1;
+b7 : 2;
+b8 : 1;
+b9 : 1;
+ba : 0;
+bb : 0;
+bc : 1;
+bd : 0;
+be : 0;
+bf : 2;
+c0 : 1;
+c1 : 1;
+c2 : 0;
+c3 : 2;
+c4 : 1;
+c5 : 3;
+c6 : 0;
+c7 : 1;
+c8 : 3;
+c9 : 1;
+ca : 3;
+cb : 1;
+cc : 1;
+cd : 1;
+ce : 0;
+cf : 3;
+d0 : 2;
+d1 : 1;
+d2 : 1;
+d3 : 3;
+d4 : 1;
+d5 : 0;
+d6 : 1;
+d7 : 3;
+d8 : 3;
+d9 : 0;
+da : 3;
+db : 1;
+dc : 2;
+dd : 1;
+de : 2;
+df : 2;
+e0 : 3;
+e1 : 0;
+e2 : 3;
+e3 : 2;
+e4 : 3;
+e5 : 0;
+e6 : 3;
+e7 : 1;
+e8 : 0;
+e9 : 1;
+ea : 1;
+eb : 3;
+ec : 3;
+ed : 1;
+ee : 1;
+ef : 2;
+f0 : 1;
+f1 : 2;
+f2 : 0;
+f3 : 1;
+f4 : 1;
+f5 : 0;
+f6 : 3;
+f7 : 2;
+f8 : 1;
+f9 : 2;
+fa : 3;
+fb : 0;
+fc : 3;
+fd : 3;
+fe : 2;
+ff : 1;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
new file mode 100644
index 0000000..70390fb
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif
@@ -0,0 +1,75 @@
+-- Contents are randomly generated during RTL generation.
+WIDTH=20;
+DEPTH=64;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : e8932;
+01 : f5925;
+02 : 9d108;
+03 : abb57;
+04 : a7f84;
+05 : 825e3;
+06 : bc52c;
+07 : f4522;
+08 : 79e43;
+09 : 16b8c;
+0a : 0d600;
+0b : 4a754;
+0c : e1184;
+0d : e281c;
+0e : a2fbb;
+0f : c819a;
+10 : 4aee7;
+11 : 6407d;
+12 : 333e6;
+13 : 3b15a;
+14 : aa9c4;
+15 : f43ec;
+16 : 261ec;
+17 : 71c75;
+18 : 8836d;
+19 : 7ff03;
+1a : bf315;
+1b : 964fe;
+1c : 92e39;
+1d : 67a03;
+1e : 6152d;
+1f : 392c1;
+20 : ed91c;
+21 : b8957;
+22 : 6cc97;
+23 : b6b3f;
+24 : fb6a3;
+25 : 5d248;
+26 : a1f90;
+27 : 45e40;
+28 : 67ec2;
+29 : a14c6;
+2a : a8d3b;
+2b : 4215b;
+2c : fb86c;
+2d : 69c1f;
+2e : 66424;
+2f : 4d56d;
+30 : 1b392;
+31 : 8f373;
+32 : 1a223;
+33 : 638d7;
+34 : 8b270;
+35 : 59c92;
+36 : 485f8;
+37 : 7a44a;
+38 : aba5e;
+39 : d2ec0;
+3a : 52405;
+3b : 9980a;
+3c : bb727;
+3d : 437c9;
+3e : f57ec;
+3f : eac74;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
new file mode 100644
index 0000000..4009a1b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v
@@ -0,0 +1,162 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_debug_slave_sysclk (
+                                          // inputs:
+                                           clk,
+                                           ir_in,
+                                           sr,
+                                           vs_udr,
+                                           vs_uir,
+
+                                          // outputs:
+                                           jdo,
+                                           take_action_break_a,
+                                           take_action_break_b,
+                                           take_action_break_c,
+                                           take_action_ocimem_a,
+                                           take_action_ocimem_b,
+                                           take_action_tracectrl,
+                                           take_no_action_break_a,
+                                           take_no_action_break_b,
+                                           take_no_action_break_c,
+                                           take_no_action_ocimem_a
+                                        )
+;
+
+  output  [ 37: 0] jdo;
+  output           take_action_break_a;
+  output           take_action_break_b;
+  output           take_action_break_c;
+  output           take_action_ocimem_a;
+  output           take_action_ocimem_b;
+  output           take_action_tracectrl;
+  output           take_no_action_break_a;
+  output           take_no_action_break_b;
+  output           take_no_action_break_c;
+  output           take_no_action_ocimem_a;
+  input            clk;
+  input   [  1: 0] ir_in;
+  input   [ 37: 0] sr;
+  input            vs_udr;
+  input            vs_uir;
+
+
+reg              enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg     [  1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg              sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg              sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+wire             sync_udr;
+wire             sync_uir;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire             unxunused_resetxx3;
+wire             unxunused_resetxx4;
+reg              update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+  assign unxunused_resetxx3 = 1'b1;
+  altera_std_synchronizer the_altera_std_synchronizer3
+    (
+      .clk (clk),
+      .din (vs_udr),
+      .dout (sync_udr),
+      .reset_n (unxunused_resetxx3)
+    );
+
+  defparam the_altera_std_synchronizer3.depth = 2;
+
+  assign unxunused_resetxx4 = 1'b1;
+  altera_std_synchronizer the_altera_std_synchronizer4
+    (
+      .clk (clk),
+      .din (vs_uir),
+      .dout (sync_uir),
+      .reset_n (unxunused_resetxx4)
+    );
+
+  defparam the_altera_std_synchronizer4.depth = 2;
+
+  always @(posedge clk)
+    begin
+      sync2_udr <= sync_udr;
+      update_jdo_strobe <= sync_udr & ~sync2_udr;
+      enable_action_strobe <= update_jdo_strobe;
+      sync2_uir <= sync_uir;
+      jxuir <= sync_uir & ~sync2_uir;
+    end
+
+
+  assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && 
+    ~jdo[35] && jdo[34];
+
+  assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && 
+    ~jdo[35] && ~jdo[34];
+
+  assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && 
+    jdo[35];
+
+  assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && 
+    ~jdo[36] && 
+    jdo[37];
+
+  assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && 
+    ~jdo[36] && 
+    ~jdo[37];
+
+  assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] && ~jdo[35] &&
+    jdo[37];
+
+  assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] && ~jdo[35] &&
+    ~jdo[37];
+
+  assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] &&  jdo[35] &&
+    jdo[37];
+
+  assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] &&  jdo[35] &&
+    ~jdo[37];
+
+  assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&  
+    jdo[15];
+
+  always @(posedge clk)
+    begin
+      if (jxuir)
+          ir <= ir_in;
+      if (update_jdo_strobe)
+          jdo <= sr;
+    end
+
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v
new file mode 100644
index 0000000..86189ec
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v
@@ -0,0 +1,239 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_debug_slave_tck (
+                                       // inputs:
+                                        MonDReg,
+                                        break_readreg,
+                                        dbrk_hit0_latch,
+                                        dbrk_hit1_latch,
+                                        dbrk_hit2_latch,
+                                        dbrk_hit3_latch,
+                                        debugack,
+                                        ir_in,
+                                        jtag_state_rti,
+                                        monitor_error,
+                                        monitor_ready,
+                                        reset_n,
+                                        resetlatch,
+                                        tck,
+                                        tdi,
+                                        tracemem_on,
+                                        tracemem_trcdata,
+                                        tracemem_tw,
+                                        trc_im_addr,
+                                        trc_on,
+                                        trc_wrap,
+                                        trigbrktype,
+                                        trigger_state_1,
+                                        vs_cdr,
+                                        vs_sdr,
+                                        vs_uir,
+
+                                       // outputs:
+                                        ir_out,
+                                        jrst_n,
+                                        sr,
+                                        st_ready_test_idle,
+                                        tdo
+                                     )
+;
+
+  output  [  1: 0] ir_out;
+  output           jrst_n;
+  output  [ 37: 0] sr;
+  output           st_ready_test_idle;
+  output           tdo;
+  input   [ 31: 0] MonDReg;
+  input   [ 31: 0] break_readreg;
+  input            dbrk_hit0_latch;
+  input            dbrk_hit1_latch;
+  input            dbrk_hit2_latch;
+  input            dbrk_hit3_latch;
+  input            debugack;
+  input   [  1: 0] ir_in;
+  input            jtag_state_rti;
+  input            monitor_error;
+  input            monitor_ready;
+  input            reset_n;
+  input            resetlatch;
+  input            tck;
+  input            tdi;
+  input            tracemem_on;
+  input   [ 35: 0] tracemem_trcdata;
+  input            tracemem_tw;
+  input   [  6: 0] trc_im_addr;
+  input            trc_on;
+  input            trc_wrap;
+  input            trigbrktype;
+  input            trigger_state_1;
+  input            vs_cdr;
+  input            vs_sdr;
+  input            vs_uir;
+
+
+reg     [  2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             debugack_sync;
+reg     [  1: 0] ir_out;
+wire             jrst_n;
+wire             monitor_ready_sync;
+reg     [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             st_ready_test_idle;
+wire             tdo;
+wire             unxcomplemented_resetxx1;
+wire             unxcomplemented_resetxx2;
+  always @(posedge tck)
+    begin
+      if (vs_cdr)
+          case (ir_in)
+          
+              2'b00: begin
+                  sr[35] <= debugack_sync;
+                  sr[34] <= monitor_error;
+                  sr[33] <= resetlatch;
+                  sr[32 : 1] <= MonDReg;
+                  sr[0] <= monitor_ready_sync;
+              end // 2'b00 
+          
+              2'b01: begin
+                  sr[35 : 0] <= tracemem_trcdata;
+                  sr[37] <= tracemem_tw;
+                  sr[36] <= tracemem_on;
+              end // 2'b01 
+          
+              2'b10: begin
+                  sr[37] <= trigger_state_1;
+                  sr[36] <= dbrk_hit3_latch;
+                  sr[35] <= dbrk_hit2_latch;
+                  sr[34] <= dbrk_hit1_latch;
+                  sr[33] <= dbrk_hit0_latch;
+                  sr[32 : 1] <= break_readreg;
+                  sr[0] <= trigbrktype;
+              end // 2'b10 
+          
+              2'b11: begin
+                  sr[15 : 2] <= trc_im_addr;
+                  sr[1] <= trc_wrap;
+                  sr[0] <= trc_on;
+              end // 2'b11 
+          
+          endcase // ir_in
+      if (vs_sdr)
+          case (DRsize)
+          
+              3'b000: begin
+                  sr <= {tdi, sr[37 : 2], tdi};
+              end // 3'b000 
+          
+              3'b001: begin
+                  sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
+              end // 3'b001 
+          
+              3'b010: begin
+                  sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
+              end // 3'b010 
+          
+              3'b011: begin
+                  sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
+              end // 3'b011 
+          
+              3'b100: begin
+                  sr <= {tdi, sr[37],         tdi, sr[35 : 1]};
+              end // 3'b100 
+          
+              3'b101: begin
+                  sr <= {tdi, sr[37 : 1]};
+              end // 3'b101 
+          
+              default: begin
+                  sr <= {tdi, sr[37 : 2], tdi};
+              end // default
+          
+          endcase // DRsize
+      if (vs_uir)
+          case (ir_in)
+          
+              2'b00: begin
+                  DRsize <= 3'b100;
+              end // 2'b00 
+          
+              2'b01: begin
+                  DRsize <= 3'b101;
+              end // 2'b01 
+          
+              2'b10: begin
+                  DRsize <= 3'b101;
+              end // 2'b10 
+          
+              2'b11: begin
+                  DRsize <= 3'b010;
+              end // 2'b11 
+          
+          endcase // ir_in
+    end
+
+
+  assign tdo = sr[0];
+  assign st_ready_test_idle = jtag_state_rti;
+  assign unxcomplemented_resetxx1 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer1
+    (
+      .clk (tck),
+      .din (debugack),
+      .dout (debugack_sync),
+      .reset_n (unxcomplemented_resetxx1)
+    );
+
+  defparam the_altera_std_synchronizer1.depth = 2;
+
+  assign unxcomplemented_resetxx2 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer2
+    (
+      .clk (tck),
+      .din (monitor_ready),
+      .dout (monitor_ready_sync),
+      .reset_n (unxcomplemented_resetxx2)
+    );
+
+  defparam the_altera_std_synchronizer2.depth = 2;
+
+  always @(posedge tck or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          ir_out <= 2'b0;
+      else 
+        ir_out <= {debugack_sync, monitor_ready_sync};
+    end
+
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign jrst_n = reset_n;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  assign jrst_n = 1;
+//synthesis read_comments_as_HDL off
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
new file mode 100644
index 0000000..e9edf29
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v
@@ -0,0 +1,222 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_debug_slave_wrapper (
+                                           // inputs:
+                                            MonDReg,
+                                            break_readreg,
+                                            clk,
+                                            dbrk_hit0_latch,
+                                            dbrk_hit1_latch,
+                                            dbrk_hit2_latch,
+                                            dbrk_hit3_latch,
+                                            debugack,
+                                            monitor_error,
+                                            monitor_ready,
+                                            reset_n,
+                                            resetlatch,
+                                            tracemem_on,
+                                            tracemem_trcdata,
+                                            tracemem_tw,
+                                            trc_im_addr,
+                                            trc_on,
+                                            trc_wrap,
+                                            trigbrktype,
+                                            trigger_state_1,
+
+                                           // outputs:
+                                            jdo,
+                                            jrst_n,
+                                            st_ready_test_idle,
+                                            take_action_break_a,
+                                            take_action_break_b,
+                                            take_action_break_c,
+                                            take_action_ocimem_a,
+                                            take_action_ocimem_b,
+                                            take_action_tracectrl,
+                                            take_no_action_break_a,
+                                            take_no_action_break_b,
+                                            take_no_action_break_c,
+                                            take_no_action_ocimem_a
+                                         )
+;
+
+  output  [ 37: 0] jdo;
+  output           jrst_n;
+  output           st_ready_test_idle;
+  output           take_action_break_a;
+  output           take_action_break_b;
+  output           take_action_break_c;
+  output           take_action_ocimem_a;
+  output           take_action_ocimem_b;
+  output           take_action_tracectrl;
+  output           take_no_action_break_a;
+  output           take_no_action_break_b;
+  output           take_no_action_break_c;
+  output           take_no_action_ocimem_a;
+  input   [ 31: 0] MonDReg;
+  input   [ 31: 0] break_readreg;
+  input            clk;
+  input            dbrk_hit0_latch;
+  input            dbrk_hit1_latch;
+  input            dbrk_hit2_latch;
+  input            dbrk_hit3_latch;
+  input            debugack;
+  input            monitor_error;
+  input            monitor_ready;
+  input            reset_n;
+  input            resetlatch;
+  input            tracemem_on;
+  input   [ 35: 0] tracemem_trcdata;
+  input            tracemem_tw;
+  input   [  6: 0] trc_im_addr;
+  input            trc_on;
+  input            trc_wrap;
+  input            trigbrktype;
+  input            trigger_state_1;
+
+
+wire    [ 37: 0] jdo;
+wire             jrst_n;
+wire    [ 37: 0] sr;
+wire             st_ready_test_idle;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire             vji_cdr;
+wire    [  1: 0] vji_ir_in;
+wire    [  1: 0] vji_ir_out;
+wire             vji_rti;
+wire             vji_sdr;
+wire             vji_tck;
+wire             vji_tdi;
+wire             vji_tdo;
+wire             vji_udr;
+wire             vji_uir;
+  //Change the sld_virtual_jtag_basic's defparams to
+  //switch between a regular Nios II or an internally embedded Nios II.
+  //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
+  //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
+  q_sys_cpu_cpu_debug_slave_tck the_q_sys_cpu_cpu_debug_slave_tck
+    (
+      .MonDReg            (MonDReg),
+      .break_readreg      (break_readreg),
+      .dbrk_hit0_latch    (dbrk_hit0_latch),
+      .dbrk_hit1_latch    (dbrk_hit1_latch),
+      .dbrk_hit2_latch    (dbrk_hit2_latch),
+      .dbrk_hit3_latch    (dbrk_hit3_latch),
+      .debugack           (debugack),
+      .ir_in              (vji_ir_in),
+      .ir_out             (vji_ir_out),
+      .jrst_n             (jrst_n),
+      .jtag_state_rti     (vji_rti),
+      .monitor_error      (monitor_error),
+      .monitor_ready      (monitor_ready),
+      .reset_n            (reset_n),
+      .resetlatch         (resetlatch),
+      .sr                 (sr),
+      .st_ready_test_idle (st_ready_test_idle),
+      .tck                (vji_tck),
+      .tdi                (vji_tdi),
+      .tdo                (vji_tdo),
+      .tracemem_on        (tracemem_on),
+      .tracemem_trcdata   (tracemem_trcdata),
+      .tracemem_tw        (tracemem_tw),
+      .trc_im_addr        (trc_im_addr),
+      .trc_on             (trc_on),
+      .trc_wrap           (trc_wrap),
+      .trigbrktype        (trigbrktype),
+      .trigger_state_1    (trigger_state_1),
+      .vs_cdr             (vji_cdr),
+      .vs_sdr             (vji_sdr),
+      .vs_uir             (vji_uir)
+    );
+
+  q_sys_cpu_cpu_debug_slave_sysclk the_q_sys_cpu_cpu_debug_slave_sysclk
+    (
+      .clk                     (clk),
+      .ir_in                   (vji_ir_in),
+      .jdo                     (jdo),
+      .sr                      (sr),
+      .take_action_break_a     (take_action_break_a),
+      .take_action_break_b     (take_action_break_b),
+      .take_action_break_c     (take_action_break_c),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_action_tracectrl   (take_action_tracectrl),
+      .take_no_action_break_a  (take_no_action_break_a),
+      .take_no_action_break_b  (take_no_action_break_b),
+      .take_no_action_break_c  (take_no_action_break_c),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .vs_udr                  (vji_udr),
+      .vs_uir                  (vji_uir)
+    );
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign vji_tck = 1'b0;
+  assign vji_tdi = 1'b0;
+  assign vji_sdr = 1'b0;
+  assign vji_cdr = 1'b0;
+  assign vji_rti = 1'b0;
+  assign vji_uir = 1'b0;
+  assign vji_udr = 1'b0;
+  assign vji_ir_in = 2'b0;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  sld_virtual_jtag_basic q_sys_cpu_cpu_debug_slave_phy
+//    (
+//      .ir_in (vji_ir_in),
+//      .ir_out (vji_ir_out),
+//      .jtag_state_rti (vji_rti),
+//      .tck (vji_tck),
+//      .tdi (vji_tdi),
+//      .tdo (vji_tdo),
+//      .virtual_state_cdr (vji_cdr),
+//      .virtual_state_sdr (vji_sdr),
+//      .virtual_state_udr (vji_udr),
+//      .virtual_state_uir (vji_uir)
+//    );
+//
+//  defparam q_sys_cpu_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
+//           q_sys_cpu_cpu_debug_slave_phy.sld_instance_index = 0,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_ir_width = 2,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_mfg_id = 70,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_sim_action = "",
+//           q_sys_cpu_cpu_debug_slave_phy.sld_sim_n_scan = 0,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_sim_total_length = 0,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_type_id = 34,
+//           q_sys_cpu_cpu_debug_slave_phy.sld_version = 3;
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
new file mode 100644
index 0000000..356144f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif
@@ -0,0 +1,75 @@
+-- Contents are randomly generated during RTL generation.
+WIDTH=26;
+DEPTH=64;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : 1870e85;
+01 : 0c7a32b;
+02 : 0d6f82d;
+03 : 2fd40bb;
+04 : 081903c;
+05 : 0b4738f;
+06 : 06cf30d;
+07 : 108360b;
+08 : 280f36d;
+09 : 3d1a275;
+0a : 305944e;
+0b : 053c131;
+0c : 0a534cb;
+0d : 0c55952;
+0e : 2cd2091;
+0f : 3d6d1c2;
+10 : 0fe378c;
+11 : 2aa1b9a;
+12 : 3831d37;
+13 : 1f0be61;
+14 : 3c442c7;
+15 : 2104326;
+16 : 11125e0;
+17 : 346e1e9;
+18 : 2860f4c;
+19 : 0d9980c;
+1a : 1585005;
+1b : 2e5b156;
+1c : 39cb8a5;
+1d : 021c3b6;
+1e : 03ed2b2;
+1f : 21eb3a0;
+20 : 34b7b88;
+21 : 2a1ce69;
+22 : 1f469d3;
+23 : 2112185;
+24 : 040ba74;
+25 : 1eb3e3d;
+26 : 0ce9c9e;
+27 : 1f87c64;
+28 : 1e473b6;
+29 : 1f25af5;
+2a : 365bf0b;
+2b : 25cd9f7;
+2c : 23eea54;
+2d : 0032429;
+2e : 2d0d25e;
+2f : 10402c3;
+30 : 2713267;
+31 : 2bcd989;
+32 : 1b82a03;
+33 : 2f5201c;
+34 : 2f45fe6;
+35 : 3e958c3;
+36 : 18dfdf6;
+37 : 23f8ef7;
+38 : 23368a0;
+39 : 065976a;
+3a : 1a821cf;
+3b : 2bf20bd;
+3c : 38df60d;
+3d : 2795273;
+3e : 2196286;
+3f : 14070d1;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v
new file mode 100644
index 0000000..22e9703
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v
@@ -0,0 +1,174 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_mult_cell (
+                                 // inputs:
+                                  E_src1,
+                                  E_src2,
+                                  M_en,
+                                  clk,
+                                  reset_n,
+
+                                 // outputs:
+                                  M_mul_cell_p1,
+                                  M_mul_cell_p2,
+                                  M_mul_cell_p3
+                               )
+;
+
+  output  [ 31: 0] M_mul_cell_p1;
+  output  [ 31: 0] M_mul_cell_p2;
+  output  [ 31: 0] M_mul_cell_p3;
+  input   [ 31: 0] E_src1;
+  input   [ 31: 0] E_src2;
+  input            M_en;
+  input            clk;
+  input            reset_n;
+
+
+wire    [ 31: 0] M_mul_cell_p1;
+wire    [ 31: 0] M_mul_cell_p2;
+wire    [ 31: 0] M_mul_cell_p3;
+wire             mul_clr;
+wire    [ 31: 0] mul_src1;
+wire    [ 31: 0] mul_src2;
+  assign mul_clr = ~reset_n;
+  assign mul_src1 = E_src1;
+  assign mul_src2 = E_src2;
+  altera_mult_add the_altmult_add_p1
+    (
+      .aclr0 (mul_clr),
+      .clock0 (clk),
+      .dataa (mul_src1[15 : 0]),
+      .datab (mul_src2[15 : 0]),
+      .ena0 (M_en),
+      .result (M_mul_cell_p1)
+    );
+
+  defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
+           the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
+           the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
+           the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
+           the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
+           the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
+           the_altmult_add_p1.input_source_a0 = "DATAA",
+           the_altmult_add_p1.input_source_b0 = "DATAB",
+           the_altmult_add_p1.lpm_type = "altera_mult_add",
+           the_altmult_add_p1.multiplier1_direction = "ADD",
+           the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
+           the_altmult_add_p1.multiplier_register0 = "CLOCK0",
+           the_altmult_add_p1.number_of_multipliers = 1,
+           the_altmult_add_p1.output_register = "UNREGISTERED",
+           the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
+           the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
+           the_altmult_add_p1.representation_a = "UNSIGNED",
+           the_altmult_add_p1.representation_b = "UNSIGNED",
+           the_altmult_add_p1.selected_device_family = "MAX10",
+           the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
+           the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
+           the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
+           the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
+           the_altmult_add_p1.signed_register_a = "UNREGISTERED",
+           the_altmult_add_p1.signed_register_b = "UNREGISTERED",
+           the_altmult_add_p1.width_a = 16,
+           the_altmult_add_p1.width_b = 16,
+           the_altmult_add_p1.width_result = 32;
+
+  altera_mult_add the_altmult_add_p2
+    (
+      .aclr0 (mul_clr),
+      .clock0 (clk),
+      .dataa (mul_src1[15 : 0]),
+      .datab (mul_src2[31 : 16]),
+      .ena0 (M_en),
+      .result (M_mul_cell_p2)
+    );
+
+  defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
+           the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
+           the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
+           the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
+           the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
+           the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
+           the_altmult_add_p2.input_source_a0 = "DATAA",
+           the_altmult_add_p2.input_source_b0 = "DATAB",
+           the_altmult_add_p2.lpm_type = "altera_mult_add",
+           the_altmult_add_p2.multiplier1_direction = "ADD",
+           the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
+           the_altmult_add_p2.multiplier_register0 = "CLOCK0",
+           the_altmult_add_p2.number_of_multipliers = 1,
+           the_altmult_add_p2.output_register = "UNREGISTERED",
+           the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
+           the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
+           the_altmult_add_p2.representation_a = "UNSIGNED",
+           the_altmult_add_p2.representation_b = "UNSIGNED",
+           the_altmult_add_p2.selected_device_family = "MAX10",
+           the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
+           the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
+           the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
+           the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
+           the_altmult_add_p2.signed_register_a = "UNREGISTERED",
+           the_altmult_add_p2.signed_register_b = "UNREGISTERED",
+           the_altmult_add_p2.width_a = 16,
+           the_altmult_add_p2.width_b = 16,
+           the_altmult_add_p2.width_result = 32;
+
+  altera_mult_add the_altmult_add_p3
+    (
+      .aclr0 (mul_clr),
+      .clock0 (clk),
+      .dataa (mul_src1[31 : 16]),
+      .datab (mul_src2[15 : 0]),
+      .ena0 (M_en),
+      .result (M_mul_cell_p3)
+    );
+
+  defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
+           the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
+           the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
+           the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
+           the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
+           the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
+           the_altmult_add_p3.input_source_a0 = "DATAA",
+           the_altmult_add_p3.input_source_b0 = "DATAB",
+           the_altmult_add_p3.lpm_type = "altera_mult_add",
+           the_altmult_add_p3.multiplier1_direction = "ADD",
+           the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
+           the_altmult_add_p3.multiplier_register0 = "CLOCK0",
+           the_altmult_add_p3.number_of_multipliers = 1,
+           the_altmult_add_p3.output_register = "UNREGISTERED",
+           the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
+           the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
+           the_altmult_add_p3.representation_a = "UNSIGNED",
+           the_altmult_add_p3.representation_b = "UNSIGNED",
+           the_altmult_add_p3.selected_device_family = "MAX10",
+           the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
+           the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
+           the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
+           the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
+           the_altmult_add_p3.signed_register_a = "UNREGISTERED",
+           the_altmult_add_p3.signed_register_b = "UNREGISTERED",
+           the_altmult_add_p3.width_a = 16,
+           the_altmult_add_p3.width_b = 16,
+           the_altmult_add_p3.width_result = 32;
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
new file mode 100644
index 0000000..d8d89e7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif
@@ -0,0 +1,267 @@
+-- Contents are randomly generated during RTL generation.
+WIDTH=32;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : e459de2d;
+01 : 70371382;
+02 : 9e5c9169;
+03 : e019ec71;
+04 : 8a8a254a;
+05 : 5d6b1e75;
+06 : b69a1826;
+07 : 1895f4fa;
+08 : f357cacf;
+09 : d52486ab;
+0a : 1e598442;
+0b : d8d4c72d;
+0c : f8973f5f;
+0d : 7df07844;
+0e : 603c0386;
+0f : 5fa48cd0;
+10 : 7dad0b4e;
+11 : d8063146;
+12 : dd06b1d5;
+13 : a42cea93;
+14 : 937d88ca;
+15 : 0c6e9a23;
+16 : b81bdfa3;
+17 : 28077cf0;
+18 : 9aab97aa;
+19 : b6597e34;
+1a : 436fcd2b;
+1b : be8fe3e1;
+1c : dae80c2f;
+1d : e95b81e6;
+1e : 767f7b1b;
+1f : 23d2190d;
+20 : dbd13b92;
+21 : ba04bced;
+22 : c59ab4a9;
+23 : d18cd97a;
+24 : fdc9eef9;
+25 : e5d3431b;
+26 : 36145dba;
+27 : 381901fd;
+28 : 2b84a31d;
+29 : 56d3b835;
+2a : 82d83a4f;
+2b : 521d2b9a;
+2c : 0224591a;
+2d : 80d7ea50;
+2e : 49815eac;
+2f : 9c8177e2;
+30 : d83c171d;
+31 : 82d4e894;
+32 : 2da7a2cf;
+33 : ae082f05;
+34 : ea847ea7;
+35 : c53a36ee;
+36 : 9044fe8d;
+37 : dadb18f9;
+38 : 3631522b;
+39 : 2bae3746;
+3a : 02d78d99;
+3b : 8e0e2771;
+3c : 2ed189db;
+3d : 63aa82eb;
+3e : 754229af;
+3f : a11062b5;
+40 : e28618e1;
+41 : fcaf3400;
+42 : c8a7faac;
+43 : be56d9b0;
+44 : 7c3f3063;
+45 : 4d331f3f;
+46 : 8cceb16d;
+47 : 2d352b5d;
+48 : 0db6cd22;
+49 : 745ff58e;
+4a : e450c6d2;
+4b : 5567ae51;
+4c : ec2ac609;
+4d : fcced128;
+4e : 193f8e92;
+4f : 5719a6cc;
+50 : 065cddb6;
+51 : 04f4e1f9;
+52 : a95d8a1e;
+53 : d516bf8e;
+54 : e30d671e;
+55 : ebeeb2fe;
+56 : b48fdd0f;
+57 : f4b75c46;
+58 : 4d9c9650;
+59 : f2df58d8;
+5a : 67ace373;
+5b : 7ccace3c;
+5c : f4f3f5d5;
+5d : 2be9f598;
+5e : f7889908;
+5f : f67c2f07;
+60 : 880a8491;
+61 : 9c3967d0;
+62 : d89b44d2;
+63 : 7c21987c;
+64 : 495e0377;
+65 : 1c88706d;
+66 : bf0b4325;
+67 : 79fcc944;
+68 : fd8c1d81;
+69 : f4f168ae;
+6a : cf67e751;
+6b : 75907b16;
+6c : d859c7c1;
+6d : 05ef2e02;
+6e : 1f5802c9;
+6f : 8cb4928b;
+70 : 19e65b5f;
+71 : 9c3b7bab;
+72 : 22bc8d7d;
+73 : 03aa0e5f;
+74 : 7d35f4ff;
+75 : e5208a6e;
+76 : 44fdd477;
+77 : 74a81f1c;
+78 : 6936d4f1;
+79 : 375fc2a2;
+7a : 22a07f26;
+7b : 701c1a4d;
+7c : af4d2557;
+7d : bac85a82;
+7e : 29cff602;
+7f : 3e17ccab;
+80 : 98b6a18b;
+81 : af30f039;
+82 : 79aa79a1;
+83 : 0c6c6328;
+84 : f344e139;
+85 : d1a23597;
+86 : aff9d82b;
+87 : 0ab8d355;
+88 : 0fbf06a8;
+89 : ceb95c63;
+8a : 592f5478;
+8b : 34acb1a3;
+8c : 4f3fbe92;
+8d : 88e863bc;
+8e : b50bf58a;
+8f : b5843c0b;
+90 : 1949e308;
+91 : 8e362c2d;
+92 : 38096a2e;
+93 : 2590b613;
+94 : ed4f1bc7;
+95 : 1a9dde4b;
+96 : 020e5d70;
+97 : 7ba782ee;
+98 : 5c50a842;
+99 : d4ec5b1a;
+9a : 057d94d1;
+9b : dbd94e93;
+9c : 2df44dca;
+9d : b408a804;
+9e : d9eebfab;
+9f : 9a2625ef;
+a0 : 890d9a69;
+a1 : 4ed6c078;
+a2 : 975f5842;
+a3 : d9678916;
+a4 : 0bab32d2;
+a5 : 2bc29415;
+a6 : 1184a161;
+a7 : 2c7798e7;
+a8 : e91740c8;
+a9 : e35b48d1;
+aa : 622b21fb;
+ab : e397793d;
+ac : 290cf107;
+ad : 49af21ac;
+ae : 658940ca;
+af : f141502f;
+b0 : e20fc11c;
+b1 : bac0182e;
+b2 : 462d22a4;
+b3 : 7af0c133;
+b4 : 426fabd0;
+b5 : f932436d;
+b6 : 1e7bb164;
+b7 : a3da743c;
+b8 : 04cb28f8;
+b9 : 44a491e9;
+ba : 01d01813;
+bb : 5377cacc;
+bc : 8881ed2c;
+bd : 211920b7;
+be : aba37912;
+bf : 675a2662;
+c0 : 013a8a6c;
+c1 : 43bf84d0;
+c2 : 664255e1;
+c3 : 1c65eeba;
+c4 : 3f75ffe1;
+c5 : 70308174;
+c6 : c582652e;
+c7 : 677bec19;
+c8 : 11c8d31c;
+c9 : 8860f1c7;
+ca : 156959c6;
+cb : 21a40051;
+cc : c4bb9d10;
+cd : c4929ac5;
+ce : 12f38649;
+cf : ed7e4f86;
+d0 : 864863d1;
+d1 : 89a9d795;
+d2 : 7ac0220c;
+d3 : 633c7064;
+d4 : 40cb08f1;
+d5 : f0c35f7a;
+d6 : 2a5f3bdb;
+d7 : a713a1e7;
+d8 : d5e272b6;
+d9 : bad2c556;
+da : fd3d9459;
+db : 5527cf67;
+dc : 95b92db7;
+dd : 458a7949;
+de : a7152dfa;
+df : f849dd47;
+e0 : 9252c934;
+e1 : 8bfff345;
+e2 : 4e431d80;
+e3 : b359488e;
+e4 : 5f52ee08;
+e5 : 98756db8;
+e6 : 6386634d;
+e7 : 9f99c691;
+e8 : e1c31956;
+e9 : f7396d29;
+ea : 564934e0;
+eb : 2d099bb3;
+ec : b119ee59;
+ed : 3d8600b2;
+ee : 8bc829af;
+ef : f85308ea;
+f0 : fe722da9;
+f1 : 7eac949a;
+f2 : dc1d47af;
+f3 : a63f312a;
+f4 : 139fa1fd;
+f5 : 96c2a006;
+f6 : 1707634b;
+f7 : f951f3ce;
+f8 : 30c16fe1;
+f9 : fb0ed148;
+fa : d1313194;
+fb : 757ccab5;
+fc : f584858b;
+fd : a7ab8295;
+fe : ea01d817;
+ff : b9f579f3;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif
new file mode 100644
index 0000000..644013a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif
@@ -0,0 +1,42 @@
+WIDTH=32;
+DEPTH=32;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : deadbeef;
+01 : deadbeef;
+02 : deadbeef;
+03 : deadbeef;
+04 : deadbeef;
+05 : deadbeef;
+06 : deadbeef;
+07 : deadbeef;
+08 : deadbeef;
+09 : deadbeef;
+0a : deadbeef;
+0b : deadbeef;
+0c : deadbeef;
+0d : deadbeef;
+0e : deadbeef;
+0f : deadbeef;
+10 : deadbeef;
+11 : deadbeef;
+12 : deadbeef;
+13 : deadbeef;
+14 : deadbeef;
+15 : deadbeef;
+16 : deadbeef;
+17 : deadbeef;
+18 : deadbeef;
+19 : deadbeef;
+1a : deadbeef;
+1b : deadbeef;
+1c : deadbeef;
+1d : deadbeef;
+1e : deadbeef;
+1f : deadbeef;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif
new file mode 100644
index 0000000..644013a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif
@@ -0,0 +1,42 @@
+WIDTH=32;
+DEPTH=32;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+
+00 : deadbeef;
+01 : deadbeef;
+02 : deadbeef;
+03 : deadbeef;
+04 : deadbeef;
+05 : deadbeef;
+06 : deadbeef;
+07 : deadbeef;
+08 : deadbeef;
+09 : deadbeef;
+0a : deadbeef;
+0b : deadbeef;
+0c : deadbeef;
+0d : deadbeef;
+0e : deadbeef;
+0f : deadbeef;
+10 : deadbeef;
+11 : deadbeef;
+12 : deadbeef;
+13 : deadbeef;
+14 : deadbeef;
+15 : deadbeef;
+16 : deadbeef;
+17 : deadbeef;
+18 : deadbeef;
+19 : deadbeef;
+1a : deadbeef;
+1b : deadbeef;
+1c : deadbeef;
+1d : deadbeef;
+1e : deadbeef;
+1f : deadbeef;
+
+END;
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v
new file mode 100644
index 0000000..7e6bb91
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v
@@ -0,0 +1,1063 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_cpu_cpu_test_bench (
+                                  // inputs:
+                                   A_cmp_result,
+                                   A_ctrl_ld_non_bypass,
+                                   A_en,
+                                   A_exc_active_no_break_no_crst,
+                                   A_exc_allowed,
+                                   A_exc_any_active,
+                                   A_exc_hbreak_pri1,
+                                   A_exc_highest_pri_exc_id,
+                                   A_exc_inst_fetch,
+                                   A_exc_norm_intr_pri5,
+                                   A_st_data,
+                                   A_valid,
+                                   A_wr_data_unfiltered,
+                                   A_wr_dst_reg,
+                                   E_add_br_to_taken_history_unfiltered,
+                                   M_bht_ptr_unfiltered,
+                                   M_bht_wr_data_unfiltered,
+                                   M_bht_wr_en_unfiltered,
+                                   M_mem_baddr,
+                                   M_target_pcb,
+                                   M_valid,
+                                   W_badaddr_reg,
+                                   W_bstatus_reg,
+                                   W_cdsr_reg,
+                                   W_cpuid_reg,
+                                   W_dst_regnum,
+                                   W_estatus_reg,
+                                   W_exception_reg,
+                                   W_ienable_reg,
+                                   W_ipending_reg,
+                                   W_iw,
+                                   W_iw_op,
+                                   W_iw_opx,
+                                   W_mem_baddr,
+                                   W_mem_byte_en,
+                                   W_pcb,
+                                   W_status_reg,
+                                   W_valid,
+                                   W_vinst,
+                                   W_wr_dst_reg,
+                                   clk,
+                                   d_address,
+                                   d_byteenable,
+                                   d_read,
+                                   d_readdatavalid,
+                                   d_write,
+                                   i_address,
+                                   i_read,
+                                   i_readdatavalid,
+                                   reset_n,
+
+                                  // outputs:
+                                   A_wr_data_filtered,
+                                   E_add_br_to_taken_history_filtered,
+                                   M_bht_ptr_filtered,
+                                   M_bht_wr_data_filtered,
+                                   M_bht_wr_en_filtered,
+                                   test_has_ended
+                                )
+;
+
+  output  [ 31: 0] A_wr_data_filtered;
+  output           E_add_br_to_taken_history_filtered;
+  output  [  7: 0] M_bht_ptr_filtered;
+  output  [  1: 0] M_bht_wr_data_filtered;
+  output           M_bht_wr_en_filtered;
+  output           test_has_ended;
+  input            A_cmp_result;
+  input            A_ctrl_ld_non_bypass;
+  input            A_en;
+  input            A_exc_active_no_break_no_crst;
+  input            A_exc_allowed;
+  input            A_exc_any_active;
+  input            A_exc_hbreak_pri1;
+  input   [ 31: 0] A_exc_highest_pri_exc_id;
+  input            A_exc_inst_fetch;
+  input            A_exc_norm_intr_pri5;
+  input   [ 31: 0] A_st_data;
+  input            A_valid;
+  input   [ 31: 0] A_wr_data_unfiltered;
+  input            A_wr_dst_reg;
+  input            E_add_br_to_taken_history_unfiltered;
+  input   [  7: 0] M_bht_ptr_unfiltered;
+  input   [  1: 0] M_bht_wr_data_unfiltered;
+  input            M_bht_wr_en_unfiltered;
+  input   [ 28: 0] M_mem_baddr;
+  input   [ 28: 0] M_target_pcb;
+  input            M_valid;
+  input   [ 31: 0] W_badaddr_reg;
+  input   [ 31: 0] W_bstatus_reg;
+  input   [ 31: 0] W_cdsr_reg;
+  input   [ 31: 0] W_cpuid_reg;
+  input   [  4: 0] W_dst_regnum;
+  input   [ 31: 0] W_estatus_reg;
+  input   [ 31: 0] W_exception_reg;
+  input   [ 31: 0] W_ienable_reg;
+  input   [ 31: 0] W_ipending_reg;
+  input   [ 31: 0] W_iw;
+  input   [  5: 0] W_iw_op;
+  input   [  5: 0] W_iw_opx;
+  input   [ 28: 0] W_mem_baddr;
+  input   [  3: 0] W_mem_byte_en;
+  input   [ 28: 0] W_pcb;
+  input   [ 31: 0] W_status_reg;
+  input            W_valid;
+  input   [ 71: 0] W_vinst;
+  input            W_wr_dst_reg;
+  input            clk;
+  input   [ 28: 0] d_address;
+  input   [  3: 0] d_byteenable;
+  input            d_read;
+  input            d_readdatavalid;
+  input            d_write;
+  input   [ 28: 0] i_address;
+  input            i_read;
+  input            i_readdatavalid;
+  input            reset_n;
+
+
+wire             A_iw_invalid;
+reg     [ 28: 0] A_mem_baddr;
+reg     [ 28: 0] A_target_pcb;
+wire    [ 31: 0] A_wr_data_filtered;
+wire             A_wr_data_unfiltered_0_is_x;
+wire             A_wr_data_unfiltered_10_is_x;
+wire             A_wr_data_unfiltered_11_is_x;
+wire             A_wr_data_unfiltered_12_is_x;
+wire             A_wr_data_unfiltered_13_is_x;
+wire             A_wr_data_unfiltered_14_is_x;
+wire             A_wr_data_unfiltered_15_is_x;
+wire             A_wr_data_unfiltered_16_is_x;
+wire             A_wr_data_unfiltered_17_is_x;
+wire             A_wr_data_unfiltered_18_is_x;
+wire             A_wr_data_unfiltered_19_is_x;
+wire             A_wr_data_unfiltered_1_is_x;
+wire             A_wr_data_unfiltered_20_is_x;
+wire             A_wr_data_unfiltered_21_is_x;
+wire             A_wr_data_unfiltered_22_is_x;
+wire             A_wr_data_unfiltered_23_is_x;
+wire             A_wr_data_unfiltered_24_is_x;
+wire             A_wr_data_unfiltered_25_is_x;
+wire             A_wr_data_unfiltered_26_is_x;
+wire             A_wr_data_unfiltered_27_is_x;
+wire             A_wr_data_unfiltered_28_is_x;
+wire             A_wr_data_unfiltered_29_is_x;
+wire             A_wr_data_unfiltered_2_is_x;
+wire             A_wr_data_unfiltered_30_is_x;
+wire             A_wr_data_unfiltered_31_is_x;
+wire             A_wr_data_unfiltered_3_is_x;
+wire             A_wr_data_unfiltered_4_is_x;
+wire             A_wr_data_unfiltered_5_is_x;
+wire             A_wr_data_unfiltered_6_is_x;
+wire             A_wr_data_unfiltered_7_is_x;
+wire             A_wr_data_unfiltered_8_is_x;
+wire             A_wr_data_unfiltered_9_is_x;
+wire             E_add_br_to_taken_history_filtered;
+wire             E_add_br_to_taken_history_unfiltered_is_x;
+wire    [  7: 0] M_bht_ptr_filtered;
+wire             M_bht_ptr_unfiltered_0_is_x;
+wire             M_bht_ptr_unfiltered_1_is_x;
+wire             M_bht_ptr_unfiltered_2_is_x;
+wire             M_bht_ptr_unfiltered_3_is_x;
+wire             M_bht_ptr_unfiltered_4_is_x;
+wire             M_bht_ptr_unfiltered_5_is_x;
+wire             M_bht_ptr_unfiltered_6_is_x;
+wire             M_bht_ptr_unfiltered_7_is_x;
+wire    [  1: 0] M_bht_wr_data_filtered;
+wire             M_bht_wr_data_unfiltered_0_is_x;
+wire             M_bht_wr_data_unfiltered_1_is_x;
+wire             M_bht_wr_en_filtered;
+wire             M_bht_wr_en_unfiltered_is_x;
+reg     [ 31: 0] W_badaddr_reg_prev;
+wire             W_badaddr_reg_prev_is_x;
+reg     [ 31: 0] W_bstatus_reg_prev;
+wire             W_bstatus_reg_prev_is_x;
+reg     [ 31: 0] W_cdsr_reg_prev;
+wire             W_cdsr_reg_prev_is_x;
+reg              W_cmp_result;
+reg     [ 31: 0] W_cpuid_reg_prev;
+wire             W_cpuid_reg_prev_is_x;
+reg     [ 31: 0] W_estatus_reg_prev;
+wire             W_estatus_reg_prev_is_x;
+reg              W_exc_any_active;
+reg     [ 31: 0] W_exc_highest_pri_exc_id;
+reg     [ 31: 0] W_exception_reg_prev;
+wire             W_exception_reg_prev_is_x;
+reg     [ 31: 0] W_ienable_reg_prev;
+wire             W_ienable_reg_prev_is_x;
+reg     [ 31: 0] W_ipending_reg_prev;
+wire             W_ipending_reg_prev_is_x;
+wire             W_is_opx_inst;
+reg              W_iw_invalid;
+wire             W_op_add;
+wire             W_op_addi;
+wire             W_op_and;
+wire             W_op_andhi;
+wire             W_op_andi;
+wire             W_op_beq;
+wire             W_op_bge;
+wire             W_op_bgeu;
+wire             W_op_blt;
+wire             W_op_bltu;
+wire             W_op_bne;
+wire             W_op_br;
+wire             W_op_break;
+wire             W_op_bret;
+wire             W_op_call;
+wire             W_op_callr;
+wire             W_op_cmpeq;
+wire             W_op_cmpeqi;
+wire             W_op_cmpge;
+wire             W_op_cmpgei;
+wire             W_op_cmpgeu;
+wire             W_op_cmpgeui;
+wire             W_op_cmplt;
+wire             W_op_cmplti;
+wire             W_op_cmpltu;
+wire             W_op_cmpltui;
+wire             W_op_cmpne;
+wire             W_op_cmpnei;
+wire             W_op_crst;
+wire             W_op_custom;
+wire             W_op_div;
+wire             W_op_divu;
+wire             W_op_eret;
+wire             W_op_flushd;
+wire             W_op_flushda;
+wire             W_op_flushi;
+wire             W_op_flushp;
+wire             W_op_hbreak;
+wire             W_op_initd;
+wire             W_op_initda;
+wire             W_op_initi;
+wire             W_op_intr;
+wire             W_op_jmp;
+wire             W_op_jmpi;
+wire             W_op_ldb;
+wire             W_op_ldbio;
+wire             W_op_ldbu;
+wire             W_op_ldbuio;
+wire             W_op_ldh;
+wire             W_op_ldhio;
+wire             W_op_ldhu;
+wire             W_op_ldhuio;
+wire             W_op_ldl;
+wire             W_op_ldw;
+wire             W_op_ldwio;
+wire             W_op_mul;
+wire             W_op_muli;
+wire             W_op_mulxss;
+wire             W_op_mulxsu;
+wire             W_op_mulxuu;
+wire             W_op_nextpc;
+wire             W_op_nor;
+wire             W_op_op_rsv02;
+wire             W_op_op_rsv09;
+wire             W_op_op_rsv10;
+wire             W_op_op_rsv17;
+wire             W_op_op_rsv18;
+wire             W_op_op_rsv25;
+wire             W_op_op_rsv26;
+wire             W_op_op_rsv33;
+wire             W_op_op_rsv34;
+wire             W_op_op_rsv41;
+wire             W_op_op_rsv42;
+wire             W_op_op_rsv49;
+wire             W_op_op_rsv57;
+wire             W_op_op_rsv61;
+wire             W_op_op_rsv62;
+wire             W_op_op_rsv63;
+wire             W_op_opx_rsv00;
+wire             W_op_opx_rsv10;
+wire             W_op_opx_rsv15;
+wire             W_op_opx_rsv17;
+wire             W_op_opx_rsv21;
+wire             W_op_opx_rsv25;
+wire             W_op_opx_rsv33;
+wire             W_op_opx_rsv34;
+wire             W_op_opx_rsv35;
+wire             W_op_opx_rsv42;
+wire             W_op_opx_rsv43;
+wire             W_op_opx_rsv44;
+wire             W_op_opx_rsv47;
+wire             W_op_opx_rsv50;
+wire             W_op_opx_rsv51;
+wire             W_op_opx_rsv55;
+wire             W_op_opx_rsv56;
+wire             W_op_opx_rsv60;
+wire             W_op_opx_rsv63;
+wire             W_op_or;
+wire             W_op_orhi;
+wire             W_op_ori;
+wire             W_op_rdctl;
+wire             W_op_rdprs;
+wire             W_op_ret;
+wire             W_op_rol;
+wire             W_op_roli;
+wire             W_op_ror;
+wire             W_op_sll;
+wire             W_op_slli;
+wire             W_op_sra;
+wire             W_op_srai;
+wire             W_op_srl;
+wire             W_op_srli;
+wire             W_op_stb;
+wire             W_op_stbio;
+wire             W_op_stc;
+wire             W_op_sth;
+wire             W_op_sthio;
+wire             W_op_stw;
+wire             W_op_stwio;
+wire             W_op_sub;
+wire             W_op_sync;
+wire             W_op_trap;
+wire             W_op_wrctl;
+wire             W_op_wrprs;
+wire             W_op_xor;
+wire             W_op_xorhi;
+wire             W_op_xori;
+reg     [ 31: 0] W_st_data;
+reg     [ 31: 0] W_status_reg_prev;
+wire             W_status_reg_prev_is_x;
+reg     [ 28: 0] W_target_pcb;
+reg              W_valid_crst;
+reg              W_valid_hbreak;
+reg              W_valid_intr;
+reg     [ 31: 0] W_wr_data_filtered;
+wire             test_has_ended;
+  assign W_op_call = W_iw_op == 0;
+  assign W_op_jmpi = W_iw_op == 1;
+  assign W_op_op_rsv02 = W_iw_op == 2;
+  assign W_op_ldbu = W_iw_op == 3;
+  assign W_op_addi = W_iw_op == 4;
+  assign W_op_stb = W_iw_op == 5;
+  assign W_op_br = W_iw_op == 6;
+  assign W_op_ldb = W_iw_op == 7;
+  assign W_op_cmpgei = W_iw_op == 8;
+  assign W_op_op_rsv09 = W_iw_op == 9;
+  assign W_op_op_rsv10 = W_iw_op == 10;
+  assign W_op_ldhu = W_iw_op == 11;
+  assign W_op_andi = W_iw_op == 12;
+  assign W_op_sth = W_iw_op == 13;
+  assign W_op_bge = W_iw_op == 14;
+  assign W_op_ldh = W_iw_op == 15;
+  assign W_op_cmplti = W_iw_op == 16;
+  assign W_op_op_rsv17 = W_iw_op == 17;
+  assign W_op_op_rsv18 = W_iw_op == 18;
+  assign W_op_initda = W_iw_op == 19;
+  assign W_op_ori = W_iw_op == 20;
+  assign W_op_stw = W_iw_op == 21;
+  assign W_op_blt = W_iw_op == 22;
+  assign W_op_ldw = W_iw_op == 23;
+  assign W_op_cmpnei = W_iw_op == 24;
+  assign W_op_op_rsv25 = W_iw_op == 25;
+  assign W_op_op_rsv26 = W_iw_op == 26;
+  assign W_op_flushda = W_iw_op == 27;
+  assign W_op_xori = W_iw_op == 28;
+  assign W_op_stc = W_iw_op == 29;
+  assign W_op_bne = W_iw_op == 30;
+  assign W_op_ldl = W_iw_op == 31;
+  assign W_op_cmpeqi = W_iw_op == 32;
+  assign W_op_op_rsv33 = W_iw_op == 33;
+  assign W_op_op_rsv34 = W_iw_op == 34;
+  assign W_op_ldbuio = W_iw_op == 35;
+  assign W_op_muli = W_iw_op == 36;
+  assign W_op_stbio = W_iw_op == 37;
+  assign W_op_beq = W_iw_op == 38;
+  assign W_op_ldbio = W_iw_op == 39;
+  assign W_op_cmpgeui = W_iw_op == 40;
+  assign W_op_op_rsv41 = W_iw_op == 41;
+  assign W_op_op_rsv42 = W_iw_op == 42;
+  assign W_op_ldhuio = W_iw_op == 43;
+  assign W_op_andhi = W_iw_op == 44;
+  assign W_op_sthio = W_iw_op == 45;
+  assign W_op_bgeu = W_iw_op == 46;
+  assign W_op_ldhio = W_iw_op == 47;
+  assign W_op_cmpltui = W_iw_op == 48;
+  assign W_op_op_rsv49 = W_iw_op == 49;
+  assign W_op_custom = W_iw_op == 50;
+  assign W_op_initd = W_iw_op == 51;
+  assign W_op_orhi = W_iw_op == 52;
+  assign W_op_stwio = W_iw_op == 53;
+  assign W_op_bltu = W_iw_op == 54;
+  assign W_op_ldwio = W_iw_op == 55;
+  assign W_op_rdprs = W_iw_op == 56;
+  assign W_op_op_rsv57 = W_iw_op == 57;
+  assign W_op_flushd = W_iw_op == 59;
+  assign W_op_xorhi = W_iw_op == 60;
+  assign W_op_op_rsv61 = W_iw_op == 61;
+  assign W_op_op_rsv62 = W_iw_op == 62;
+  assign W_op_op_rsv63 = W_iw_op == 63;
+  assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
+  assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
+  assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
+  assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
+  assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
+  assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
+  assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
+  assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
+  assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
+  assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
+  assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
+  assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
+  assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
+  assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
+  assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
+  assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
+  assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
+  assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
+  assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
+  assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
+  assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
+  assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
+  assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
+  assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
+  assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
+  assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
+  assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
+  assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
+  assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
+  assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
+  assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
+  assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
+  assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
+  assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
+  assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
+  assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
+  assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
+  assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
+  assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
+  assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
+  assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
+  assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
+  assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
+  assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
+  assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
+  assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
+  assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
+  assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
+  assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
+  assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
+  assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
+  assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
+  assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
+  assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
+  assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
+  assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
+  assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
+  assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
+  assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
+  assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
+  assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
+  assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
+  assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
+  assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
+  assign W_is_opx_inst = W_iw_op == 58;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_target_pcb <= 0;
+      else if (A_en)
+          A_target_pcb <= M_target_pcb;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_mem_baddr <= 0;
+      else if (A_en)
+          A_mem_baddr <= M_mem_baddr;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_wr_data_filtered <= 0;
+      else 
+        W_wr_data_filtered <= A_wr_data_filtered;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_st_data <= 0;
+      else 
+        W_st_data <= A_st_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_cmp_result <= 0;
+      else 
+        W_cmp_result <= A_cmp_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_target_pcb <= 0;
+      else 
+        W_target_pcb <= A_target_pcb;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid_hbreak <= 0;
+      else 
+        W_valid_hbreak <= A_exc_allowed & A_exc_hbreak_pri1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid_crst <= 0;
+      else 
+        W_valid_crst <= A_exc_allowed & 0;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid_intr <= 0;
+      else 
+        W_valid_intr <= A_exc_allowed & A_exc_norm_intr_pri5;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_any_active <= 0;
+      else 
+        W_exc_any_active <= A_exc_any_active;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_exc_highest_pri_exc_id <= 0;
+      else 
+        W_exc_highest_pri_exc_id <= A_exc_highest_pri_exc_id;
+    end
+
+
+  assign A_iw_invalid = A_exc_inst_fetch & A_exc_active_no_break_no_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_iw_invalid <= 0;
+      else 
+        W_iw_invalid <= A_iw_invalid;
+    end
+
+
+  assign test_has_ended = 1'b0;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  //Clearing 'X' data bits
+  assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
+
+  assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
+  assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
+  assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
+  assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
+  assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
+  assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
+  assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
+  assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
+  assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
+  assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
+  assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
+  assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
+  assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
+  assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
+  assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
+  assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
+  assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
+  assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
+  assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
+  assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
+  assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
+  assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
+  assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
+  assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
+  assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
+  assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
+  assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
+  assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
+  assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
+  assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
+  assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
+  assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
+  assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
+  assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
+  assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
+  assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
+  assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
+  assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
+  assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
+  assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
+  assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
+  assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
+  assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
+  assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
+  assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
+  assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
+  assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
+  assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
+  assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
+  assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
+  assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
+  assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
+  assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
+  assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
+  assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
+  assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
+  assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
+  assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
+  assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
+  assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
+  assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
+  assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
+  assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
+  //Clearing 'X' data bits
+  assign E_add_br_to_taken_history_unfiltered_is_x = ^(E_add_br_to_taken_history_unfiltered) === 1'bx;
+
+  assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered_is_x ? 1'b0 : E_add_br_to_taken_history_unfiltered;
+  //Clearing 'X' data bits
+  assign M_bht_wr_en_unfiltered_is_x = ^(M_bht_wr_en_unfiltered) === 1'bx;
+
+  assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered_is_x ? 1'b0 : M_bht_wr_en_unfiltered;
+  //Clearing 'X' data bits
+  assign M_bht_wr_data_unfiltered_0_is_x = ^(M_bht_wr_data_unfiltered[0]) === 1'bx;
+
+  assign M_bht_wr_data_filtered[0] = M_bht_wr_data_unfiltered_0_is_x ? 1'b0 : M_bht_wr_data_unfiltered[0];
+  assign M_bht_wr_data_unfiltered_1_is_x = ^(M_bht_wr_data_unfiltered[1]) === 1'bx;
+  assign M_bht_wr_data_filtered[1] = M_bht_wr_data_unfiltered_1_is_x ? 1'b0 : M_bht_wr_data_unfiltered[1];
+  //Clearing 'X' data bits
+  assign M_bht_ptr_unfiltered_0_is_x = ^(M_bht_ptr_unfiltered[0]) === 1'bx;
+
+  assign M_bht_ptr_filtered[0] = M_bht_ptr_unfiltered_0_is_x ? 1'b0 : M_bht_ptr_unfiltered[0];
+  assign M_bht_ptr_unfiltered_1_is_x = ^(M_bht_ptr_unfiltered[1]) === 1'bx;
+  assign M_bht_ptr_filtered[1] = M_bht_ptr_unfiltered_1_is_x ? 1'b0 : M_bht_ptr_unfiltered[1];
+  assign M_bht_ptr_unfiltered_2_is_x = ^(M_bht_ptr_unfiltered[2]) === 1'bx;
+  assign M_bht_ptr_filtered[2] = M_bht_ptr_unfiltered_2_is_x ? 1'b0 : M_bht_ptr_unfiltered[2];
+  assign M_bht_ptr_unfiltered_3_is_x = ^(M_bht_ptr_unfiltered[3]) === 1'bx;
+  assign M_bht_ptr_filtered[3] = M_bht_ptr_unfiltered_3_is_x ? 1'b0 : M_bht_ptr_unfiltered[3];
+  assign M_bht_ptr_unfiltered_4_is_x = ^(M_bht_ptr_unfiltered[4]) === 1'bx;
+  assign M_bht_ptr_filtered[4] = M_bht_ptr_unfiltered_4_is_x ? 1'b0 : M_bht_ptr_unfiltered[4];
+  assign M_bht_ptr_unfiltered_5_is_x = ^(M_bht_ptr_unfiltered[5]) === 1'bx;
+  assign M_bht_ptr_filtered[5] = M_bht_ptr_unfiltered_5_is_x ? 1'b0 : M_bht_ptr_unfiltered[5];
+  assign M_bht_ptr_unfiltered_6_is_x = ^(M_bht_ptr_unfiltered[6]) === 1'bx;
+  assign M_bht_ptr_filtered[6] = M_bht_ptr_unfiltered_6_is_x ? 1'b0 : M_bht_ptr_unfiltered[6];
+  assign M_bht_ptr_unfiltered_7_is_x = ^(M_bht_ptr_unfiltered[7]) === 1'bx;
+  assign M_bht_ptr_filtered[7] = M_bht_ptr_unfiltered_7_is_x ? 1'b0 : M_bht_ptr_unfiltered[7];
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_wr_dst_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_wr_dst_reg)
+          if (^(W_dst_regnum) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_dst_regnum is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid)
+          if (^(W_pcb) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_pcb is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid)
+          if (^(W_iw) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_iw is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(A_en) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/A_en is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(M_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/M_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(A_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/A_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (A_valid & A_en & A_wr_dst_reg)
+          if (^(A_wr_data_unfiltered) === 1'bx)
+            begin
+              $write("%0d ns: WARNING: q_sys_cpu_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_status_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_status_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_estatus_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_estatus_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_bstatus_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_bstatus_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_exception_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_exception_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_badaddr_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/W_badaddr_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(A_exc_any_active) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/A_exc_any_active is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(i_read) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/i_read is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (i_read)
+          if (^(i_address) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/i_address is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(d_write) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/d_write is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (d_write)
+          if (^(d_byteenable) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/d_byteenable is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (d_write | d_read)
+          if (^(d_address) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/d_address is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(d_read) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/d_read is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(i_readdatavalid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/i_readdatavalid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(d_readdatavalid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: q_sys_cpu_cpu_test_bench/d_readdatavalid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  
+  reg [31:0] trace_handle; // for $fopen
+  initial  
+  begin
+    trace_handle = $fopen("q_sys_cpu_cpu.tr");
+    $fwrite(trace_handle, "HeaderStart\nVersion 0\nCpuCoreName NiosII/f2\nCpuInstanceName q_sys_cpu_cpu\nCpuArchName Nios2\nCpuArchRev R1\nCtrlRegPresent 0\nCtrlRegPresent 1\nCtrlRegPresent 2\nCtrlRegPresent 3\nCtrlRegPresent 4\nCtrlRegPresent 5\nCtrlRegPresent 7\nCtrlRegPresent c\nCtrlRegPresent 1f\nExcContainsId 1\nHeaderEnd\n");
+  end
+  assign W_status_reg_prev_is_x = ^(W_status_reg_prev) === 1'bx;
+  assign W_estatus_reg_prev_is_x = ^(W_estatus_reg_prev) === 1'bx;
+  assign W_bstatus_reg_prev_is_x = ^(W_bstatus_reg_prev) === 1'bx;
+  assign W_ienable_reg_prev_is_x = ^(W_ienable_reg_prev) === 1'bx;
+  assign W_ipending_reg_prev_is_x = ^(W_ipending_reg_prev) === 1'bx;
+  assign W_cpuid_reg_prev_is_x = ^(W_cpuid_reg_prev) === 1'bx;
+  assign W_exception_reg_prev_is_x = ^(W_exception_reg_prev) === 1'bx;
+  assign W_badaddr_reg_prev_is_x = ^(W_badaddr_reg_prev) === 1'bx;
+  assign W_cdsr_reg_prev_is_x = ^(W_cdsr_reg_prev) === 1'bx;
+  always @(posedge clk)
+    begin
+      if (~test_has_ended)
+        begin
+          if ((W_status_reg != W_status_reg_prev) || W_status_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 0, W_status_reg);
+              W_status_reg_prev <= W_status_reg;
+            end
+          if ((W_estatus_reg != W_estatus_reg_prev) || W_estatus_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 1, W_estatus_reg);
+              W_estatus_reg_prev <= W_estatus_reg;
+            end
+          if ((W_bstatus_reg != W_bstatus_reg_prev) || W_bstatus_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 2, W_bstatus_reg);
+              W_bstatus_reg_prev <= W_bstatus_reg;
+            end
+          if ((W_ienable_reg != W_ienable_reg_prev) || W_ienable_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 3, W_ienable_reg);
+              W_ienable_reg_prev <= W_ienable_reg;
+            end
+          if ((W_ipending_reg != W_ipending_reg_prev) || W_ipending_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 4, W_ipending_reg);
+              W_ipending_reg_prev <= W_ipending_reg;
+            end
+          if ((W_cpuid_reg != W_cpuid_reg_prev) || W_cpuid_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 5, W_cpuid_reg);
+              W_cpuid_reg_prev <= W_cpuid_reg;
+            end
+          if ((W_exception_reg != W_exception_reg_prev) || W_exception_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 7, W_exception_reg);
+              W_exception_reg_prev <= W_exception_reg;
+            end
+          if ((W_badaddr_reg != W_badaddr_reg_prev) || W_badaddr_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 12, W_badaddr_reg);
+              W_badaddr_reg_prev <= W_badaddr_reg;
+            end
+          if ((W_cdsr_reg != W_cdsr_reg_prev) || W_cdsr_reg_prev_is_x)
+            begin
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h\n", $time, 4, 31, W_cdsr_reg);
+              W_cdsr_reg_prev <= W_cdsr_reg;
+            end
+          if (~reset_n)
+              $fwrite(trace_handle, "%0d ns: %0h,%0h\n", $time, 0, 0);
+          else if (W_valid_hbreak)
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h\n", $time, 1, W_pcb, W_wr_dst_reg, W_dst_regnum, W_wr_data_filtered);
+          else if (W_valid_intr)
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h\n", $time, 2, W_pcb, W_wr_dst_reg, W_dst_regnum, W_wr_data_filtered);
+          else if (W_valid || W_exc_any_active)
+              $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, 3, W_exc_any_active ? W_exc_highest_pri_exc_id : 0, W_pcb, ~W_iw_invalid, W_iw, W_wr_dst_reg, W_dst_regnum, W_wr_data_filtered, W_mem_baddr, W_st_data, W_mem_byte_en, W_cmp_result, W_target_pcb);
+        end
+    end
+
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  
+//  assign A_wr_data_filtered = A_wr_data_unfiltered;
+//
+//  
+//  assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
+//
+//  
+//  assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
+//
+//  
+//  assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
+//
+//  
+//  assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram.v
new file mode 100644
index 0000000..cc30273
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram.v
@@ -0,0 +1,412 @@
+// q_sys_ddr3_ram.v
+
+// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ddr3_ram (
+		input  wire        pll_ref_clk,        //      pll_ref_clk.clk
+		input  wire        global_reset_n,     //     global_reset.reset_n
+		input  wire        soft_reset_n,       //       soft_reset.reset_n
+		output wire        afi_clk,            //          afi_clk.clk
+		output wire        afi_half_clk,       //     afi_half_clk.clk
+		output wire        afi_reset_n,        //        afi_reset.reset_n
+		output wire        afi_reset_export_n, // afi_reset_export.reset_n
+		output wire [13:0] mem_a,              //           memory.mem_a
+		output wire [2:0]  mem_ba,             //                 .mem_ba
+		inout  wire [0:0]  mem_ck,             //                 .mem_ck
+		inout  wire [0:0]  mem_ck_n,           //                 .mem_ck_n
+		output wire [0:0]  mem_cke,            //                 .mem_cke
+		output wire [0:0]  mem_cs_n,           //                 .mem_cs_n
+		output wire [0:0]  mem_dm,             //                 .mem_dm
+		output wire [0:0]  mem_ras_n,          //                 .mem_ras_n
+		output wire [0:0]  mem_cas_n,          //                 .mem_cas_n
+		output wire [0:0]  mem_we_n,           //                 .mem_we_n
+		output wire        mem_reset_n,        //                 .mem_reset_n
+		inout  wire [7:0]  mem_dq,             //                 .mem_dq
+		inout  wire [0:0]  mem_dqs,            //                 .mem_dqs
+		inout  wire [0:0]  mem_dqs_n,          //                 .mem_dqs_n
+		output wire [0:0]  mem_odt,            //                 .mem_odt
+		output wire        avl_ready,          //              avl.waitrequest_n
+		input  wire        avl_burstbegin,     //                 .beginbursttransfer
+		input  wire [24:0] avl_addr,           //                 .address
+		output wire        avl_rdata_valid,    //                 .readdatavalid
+		output wire [31:0] avl_rdata,          //                 .readdata
+		input  wire [31:0] avl_wdata,          //                 .writedata
+		input  wire [3:0]  avl_be,             //                 .byteenable
+		input  wire        avl_read_req,       //                 .read
+		input  wire        avl_write_req,      //                 .write
+		input  wire [2:0]  avl_size,           //                 .burstcount
+		output wire        local_init_done,    //           status.local_init_done
+		output wire        local_cal_success,  //                 .local_cal_success
+		output wire        local_cal_fail,     //                 .local_cal_fail
+		output wire        pll_mem_clk,        //      pll_sharing.pll_mem_clk
+		output wire        pll_write_clk,      //                 .pll_write_clk
+		output wire        pll_locked,         //                 .pll_locked
+		output wire        pll_capture0_clk,   //                 .pll_capture0_clk
+		output wire        pll_capture1_clk    //                 .pll_capture1_clk
+	);
+
+	wire   [1:0] m0_phy_mux_afi_rdata_en_full;       // m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
+	wire   [5:0] p0_afi_afi_rlat;                    // p0:afi_rlat -> m0:phy_mux_rlat
+	wire         p0_afi_afi_cal_success;             // p0:afi_cal_success -> m0:phy_mux_cal_success
+	wire   [1:0] m0_phy_mux_afi_wdata_valid;         // m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
+	wire  [31:0] p0_afi_afi_rdata;                   // p0:afi_rdata -> m0:phy_mux_rdata
+	wire  [31:0] m0_phy_mux_afi_wdata;               // m0:phy_mux_wdata -> p0:afi_wdata
+	wire   [1:0] m0_phy_mux_afi_rst_n;               // m0:phy_mux_rst_n -> p0:afi_rst_n
+	wire   [1:0] m0_phy_mux_afi_dqs_burst;           // m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
+	wire  [27:0] m0_phy_mux_afi_addr;                // m0:phy_mux_addr -> p0:afi_addr
+	wire   [5:0] m0_phy_mux_afi_ba;                  // m0:phy_mux_ba -> p0:afi_ba
+	wire   [5:0] p0_afi_afi_wlat;                    // p0:afi_wlat -> m0:phy_mux_wlat
+	wire   [3:0] m0_phy_mux_afi_dm;                  // m0:phy_mux_dm -> p0:afi_dm
+	wire         p0_afi_afi_cal_fail;                // p0:afi_cal_fail -> m0:phy_mux_cal_fail
+	wire   [1:0] p0_afi_afi_rdata_valid;             // p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
+	wire   [1:0] m0_phy_mux_afi_we_n;                // m0:phy_mux_we_n -> p0:afi_we_n
+	wire   [1:0] m0_phy_mux_afi_cas_n;               // m0:phy_mux_cas_n -> p0:afi_cas_n
+	wire   [1:0] m0_phy_mux_afi_cs_n;                // m0:phy_mux_cs_n -> p0:afi_cs_n
+	wire   [1:0] m0_phy_mux_afi_rdata_en;            // m0:phy_mux_rdata_en -> p0:afi_rdata_en
+	wire   [1:0] m0_phy_mux_afi_odt;                 // m0:phy_mux_odt -> p0:afi_odt
+	wire   [1:0] m0_phy_mux_afi_ras_n;               // m0:phy_mux_ras_n -> p0:afi_ras_n
+	wire   [1:0] m0_phy_mux_afi_cke;                 // m0:phy_mux_cke -> p0:afi_cke
+	wire   [5:0] m0_afi_afi_rlat;                    // m0:afi_rlat -> c0:afi_rlat
+	wire         m0_afi_afi_cal_success;             // m0:afi_cal_success -> c0:afi_cal_success
+	wire  [31:0] m0_afi_afi_rdata;                   // m0:afi_rdata -> c0:afi_rdata
+	wire   [5:0] m0_afi_afi_wlat;                    // m0:afi_wlat -> c0:afi_wlat
+	wire         m0_afi_afi_cal_fail;                // m0:afi_cal_fail -> c0:afi_cal_fail
+	wire   [1:0] m0_afi_afi_rdata_valid;             // m0:afi_rdata_valid -> c0:afi_rdata_valid
+	wire         p0_avl_clk_clk;                     // p0:avl_clk -> s0:avl_clk
+	wire         p0_avl_reset_reset;                 // p0:avl_reset_n -> s0:avl_reset_n
+	wire         s0_pll_reconfig_scanclk;            // s0:scanclk -> pll0:scanclk
+	wire         s0_pll_reconfig_phaseupdown;        // s0:phaseupdown -> pll0:phaseupdown
+	wire   [2:0] s0_pll_reconfig_phasecounterselect; // s0:phasecounterselect -> pll0:phasecounterselect
+	wire         s0_pll_reconfig_phasestep;          // s0:phasestep -> pll0:phasestep
+	wire         pll0_pll_reconfig_phasedone;        // pll0:phasedone -> s0:phasedone
+	wire         s0_phase_detector_pd_ack;           // s0:pd_ack -> p0:pd_ack
+	wire         s0_phase_detector_pd_reset_n;       // s0:pd_reset_n -> p0:pd_reset_n
+	wire         p0_phase_detector_pd_down;          // p0:pd_down -> s0:pd_down
+	wire         p0_phase_detector_pd_up;            // p0:pd_up -> s0:pd_up
+	wire   [1:0] s0_afi_afi_rdata_en_full;           // s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
+	wire   [1:0] s0_afi_afi_wdata_valid;             // s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
+	wire  [31:0] m0_seq_mux_afi_rdata;               // m0:seq_mux_rdata -> s0:afi_rdata
+	wire  [31:0] s0_afi_afi_wdata;                   // s0:afi_wdata -> m0:seq_mux_wdata
+	wire   [1:0] s0_afi_afi_rst_n;                   // s0:afi_rst_n -> m0:seq_mux_rst_n
+	wire   [1:0] s0_afi_afi_dqs_burst;               // s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
+	wire  [27:0] s0_afi_afi_addr;                    // s0:afi_addr -> m0:seq_mux_addr
+	wire   [5:0] s0_afi_afi_ba;                      // s0:afi_ba -> m0:seq_mux_ba
+	wire   [3:0] s0_afi_afi_dm;                      // s0:afi_dm -> m0:seq_mux_dm
+	wire   [1:0] m0_seq_mux_afi_rdata_valid;         // m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
+	wire   [1:0] s0_afi_afi_we_n;                    // s0:afi_we_n -> m0:seq_mux_we_n
+	wire   [1:0] s0_afi_afi_cas_n;                   // s0:afi_cas_n -> m0:seq_mux_cas_n
+	wire   [1:0] s0_afi_afi_cs_n;                    // s0:afi_cs_n -> m0:seq_mux_cs_n
+	wire   [1:0] s0_afi_afi_rdata_en;                // s0:afi_rdata_en -> m0:seq_mux_rdata_en
+	wire   [1:0] s0_afi_afi_odt;                     // s0:afi_odt -> m0:seq_mux_odt
+	wire   [1:0] s0_afi_afi_ras_n;                   // s0:afi_ras_n -> m0:seq_mux_ras_n
+	wire   [1:0] s0_afi_afi_cke;                     // s0:afi_cke -> m0:seq_mux_cke
+	wire         s0_mux_sel_mux_sel;                 // s0:phy_mux_sel -> m0:mux_sel
+	wire   [5:0] s0_phy_phy_afi_rlat;                // s0:phy_afi_rlat -> p0:phy_afi_rlat
+	wire         p0_phy_phy_clk;                     // p0:phy_clk -> s0:phy_clk
+	wire   [4:0] s0_phy_phy_read_latency_counter;    // s0:phy_read_latency_counter -> p0:phy_read_latency_counter
+	wire   [5:0] s0_phy_phy_afi_wlat;                // s0:phy_afi_wlat -> p0:phy_afi_wlat
+	wire         s0_phy_phy_reset_mem_stable;        // s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_qr; // s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
+	wire   [0:0] s0_phy_phy_vfifo_rd_en_override;    // s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
+	wire   [0:0] s0_phy_phy_read_fifo_reset;         // s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
+	wire   [1:0] s0_phy_phy_write_fr_cycle_shifts;   // s0:phy_write_fr_cycle_shifts -> p0:phy_write_fr_cycle_shifts
+	wire         s0_phy_phy_cal_fail;                // s0:phy_cal_fail -> p0:phy_cal_fail
+	wire         s0_phy_phy_cal_success;             // s0:phy_cal_success -> p0:phy_cal_success
+	wire         p0_phy_phy_reset_n;                 // p0:phy_reset_n -> s0:phy_reset_n
+	wire  [31:0] s0_phy_phy_cal_debug_info;          // s0:phy_cal_debug_info -> p0:phy_cal_debug_info
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_hr; // s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_fr; // s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
+	wire  [31:0] p0_phy_phy_read_fifo_q;             // p0:phy_read_fifo_q -> s0:phy_read_fifo_q
+	wire   [7:0] p0_calib_calib_skip_steps;          // p0:calib_skip_steps -> s0:calib_skip_steps
+	wire   [1:0] c0_afi_afi_rdata_en_full;           // c0:afi_rdata_en_full -> m0:afi_rdata_en_full
+	wire   [1:0] c0_afi_afi_wdata_valid;             // c0:afi_wdata_valid -> m0:afi_wdata_valid
+	wire  [31:0] c0_afi_afi_wdata;                   // c0:afi_wdata -> m0:afi_wdata
+	wire   [1:0] c0_afi_afi_rst_n;                   // c0:afi_rst_n -> m0:afi_rst_n
+	wire         c0_afi_afi_cal_req;                 // c0:afi_cal_req -> s0:afi_cal_req
+	wire   [1:0] c0_afi_afi_dqs_burst;               // c0:afi_dqs_burst -> m0:afi_dqs_burst
+	wire  [27:0] c0_afi_afi_addr;                    // c0:afi_addr -> m0:afi_addr
+	wire   [5:0] c0_afi_afi_ba;                      // c0:afi_ba -> m0:afi_ba
+	wire   [3:0] c0_afi_afi_dm;                      // c0:afi_dm -> m0:afi_dm
+	wire   [0:0] c0_afi_afi_mem_clk_disable;         // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
+	wire         c0_afi_afi_init_req;                // c0:afi_init_req -> s0:afi_init_req
+	wire   [1:0] c0_afi_afi_we_n;                    // c0:afi_we_n -> m0:afi_we_n
+	wire   [1:0] c0_afi_afi_cas_n;                   // c0:afi_cas_n -> m0:afi_cas_n
+	wire   [1:0] c0_afi_afi_cs_n;                    // c0:afi_cs_n -> m0:afi_cs_n
+	wire   [1:0] c0_afi_afi_rdata_en;                // c0:afi_rdata_en -> m0:afi_rdata_en
+	wire   [1:0] c0_afi_afi_odt;                     // c0:afi_odt -> m0:afi_odt
+	wire   [1:0] c0_afi_afi_ras_n;                   // c0:afi_ras_n -> m0:afi_ras_n
+	wire   [1:0] c0_afi_afi_cke;                     // c0:afi_cke -> m0:afi_cke
+
+	q_sys_ddr3_ram_pll0 pll0 (
+		.global_reset_n     (global_reset_n),                     // global_reset.reset_n
+		.afi_clk            (afi_clk),                            //      afi_clk.clk
+		.afi_half_clk       (afi_half_clk),                       // afi_half_clk.clk
+		.pll_ref_clk        (pll_ref_clk),                        //  pll_ref_clk.clk
+		.pll_mem_clk        (pll_mem_clk),                        //  pll_sharing.pll_mem_clk
+		.pll_write_clk      (pll_write_clk),                      //             .pll_write_clk
+		.pll_locked         (pll_locked),                         //             .pll_locked
+		.pll_capture0_clk   (pll_capture0_clk),                   //             .pll_capture0_clk
+		.pll_capture1_clk   (pll_capture1_clk),                   //             .pll_capture1_clk
+		.phasecounterselect (s0_pll_reconfig_phasecounterselect), // pll_reconfig.phasecounterselect
+		.phasestep          (s0_pll_reconfig_phasestep),          //             .phasestep
+		.phaseupdown        (s0_pll_reconfig_phaseupdown),        //             .phaseupdown
+		.scanclk            (s0_pll_reconfig_scanclk),            //             .scanclk
+		.phasedone          (pll0_pll_reconfig_phasedone)         //             .phasedone
+	);
+
+	q_sys_ddr3_ram_p0 p0 (
+		.global_reset_n              (global_reset_n),                     //        global_reset.reset_n
+		.soft_reset_n                (soft_reset_n),                       //          soft_reset.reset_n
+		.afi_reset_n                 (afi_reset_n),                        //           afi_reset.reset_n
+		.afi_reset_export_n          (afi_reset_export_n),                 //    afi_reset_export.reset_n
+		.afi_clk                     (afi_clk),                            //             afi_clk.clk
+		.afi_half_clk                (afi_half_clk),                       //        afi_half_clk.clk
+		.avl_clk                     (p0_avl_clk_clk),                     //             avl_clk.clk
+		.avl_reset_n                 (p0_avl_reset_reset),                 //           avl_reset.reset_n
+		.afi_addr                    (m0_phy_mux_afi_addr),                //                 afi.afi_addr
+		.afi_ba                      (m0_phy_mux_afi_ba),                  //                    .afi_ba
+		.afi_ras_n                   (m0_phy_mux_afi_ras_n),               //                    .afi_ras_n
+		.afi_we_n                    (m0_phy_mux_afi_we_n),                //                    .afi_we_n
+		.afi_cas_n                   (m0_phy_mux_afi_cas_n),               //                    .afi_cas_n
+		.afi_odt                     (m0_phy_mux_afi_odt),                 //                    .afi_odt
+		.afi_cke                     (m0_phy_mux_afi_cke),                 //                    .afi_cke
+		.afi_cs_n                    (m0_phy_mux_afi_cs_n),                //                    .afi_cs_n
+		.afi_dqs_burst               (m0_phy_mux_afi_dqs_burst),           //                    .afi_dqs_burst
+		.afi_wdata_valid             (m0_phy_mux_afi_wdata_valid),         //                    .afi_wdata_valid
+		.afi_wdata                   (m0_phy_mux_afi_wdata),               //                    .afi_wdata
+		.afi_dm                      (m0_phy_mux_afi_dm),                  //                    .afi_dm
+		.afi_rdata                   (p0_afi_afi_rdata),                   //                    .afi_rdata
+		.afi_rst_n                   (m0_phy_mux_afi_rst_n),               //                    .afi_rst_n
+		.afi_rdata_en                (m0_phy_mux_afi_rdata_en),            //                    .afi_rdata_en
+		.afi_rdata_en_full           (m0_phy_mux_afi_rdata_en_full),       //                    .afi_rdata_en_full
+		.afi_rdata_valid             (p0_afi_afi_rdata_valid),             //                    .afi_rdata_valid
+		.afi_cal_success             (p0_afi_afi_cal_success),             //                    .afi_cal_success
+		.afi_cal_fail                (p0_afi_afi_cal_fail),                //                    .afi_cal_fail
+		.afi_wlat                    (p0_afi_afi_wlat),                    //                    .afi_wlat
+		.afi_rlat                    (p0_afi_afi_rlat),                    //                    .afi_rlat
+		.phy_clk                     (p0_phy_phy_clk),                     //                 phy.phy_clk
+		.phy_reset_n                 (p0_phy_phy_reset_n),                 //                    .phy_reset_n
+		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),    //                    .phy_read_latency_counter
+		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                //                    .phy_afi_wlat
+		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                //                    .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), //                    .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), //                    .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), //                    .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),        //                    .phy_reset_mem_stable
+		.phy_cal_success             (s0_phy_phy_cal_success),             //                    .phy_cal_success
+		.phy_cal_fail                (s0_phy_phy_cal_fail),                //                    .phy_cal_fail
+		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),          //                    .phy_cal_debug_info
+		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),         //                    .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),    //                    .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),             //                    .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (s0_phy_phy_write_fr_cycle_shifts),   //                    .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (p0_calib_calib_skip_steps),          //               calib.calib_skip_steps
+		.pd_reset_n                  (s0_phase_detector_pd_reset_n),       //      phase_detector.pd_reset_n
+		.pd_ack                      (s0_phase_detector_pd_ack),           //                    .pd_ack
+		.pd_up                       (p0_phase_detector_pd_up),            //                    .pd_up
+		.pd_down                     (p0_phase_detector_pd_down),          //                    .pd_down
+		.afi_mem_clk_disable         (c0_afi_afi_mem_clk_disable),         // afi_mem_clk_disable.afi_mem_clk_disable
+		.pll_mem_clk                 (pll_mem_clk),                        //         pll_sharing.pll_mem_clk
+		.pll_write_clk               (pll_write_clk),                      //                    .pll_write_clk
+		.pll_locked                  (pll_locked),                         //                    .pll_locked
+		.pll_capture0_clk            (pll_capture0_clk),                   //                    .pll_capture0_clk
+		.pll_capture1_clk            (pll_capture1_clk),                   //                    .pll_capture1_clk
+		.mem_a                       (mem_a),                              //              memory.mem_a
+		.mem_ba                      (mem_ba),                             //                    .mem_ba
+		.mem_ck                      (mem_ck),                             //                    .mem_ck
+		.mem_ck_n                    (mem_ck_n),                           //                    .mem_ck_n
+		.mem_cke                     (mem_cke),                            //                    .mem_cke
+		.mem_cs_n                    (mem_cs_n),                           //                    .mem_cs_n
+		.mem_dm                      (mem_dm),                             //                    .mem_dm
+		.mem_ras_n                   (mem_ras_n),                          //                    .mem_ras_n
+		.mem_cas_n                   (mem_cas_n),                          //                    .mem_cas_n
+		.mem_we_n                    (mem_we_n),                           //                    .mem_we_n
+		.mem_reset_n                 (mem_reset_n),                        //                    .mem_reset_n
+		.mem_dq                      (mem_dq),                             //                    .mem_dq
+		.mem_dqs                     (mem_dqs),                            //                    .mem_dqs
+		.mem_dqs_n                   (mem_dqs_n),                          //                    .mem_dqs_n
+		.mem_odt                     (mem_odt),                            //                    .mem_odt
+		.csr_soft_reset_req          (1'b0)                                //         (terminated)
+	);
+
+	afi_mux_ddr3_ddrx #(
+		.AFI_RATE_RATIO            (2),
+		.AFI_ADDR_WIDTH            (28),
+		.AFI_BANKADDR_WIDTH        (6),
+		.AFI_CONTROL_WIDTH         (2),
+		.AFI_CS_WIDTH              (2),
+		.AFI_CLK_EN_WIDTH          (2),
+		.AFI_DM_WIDTH              (4),
+		.AFI_DQ_WIDTH              (32),
+		.AFI_ODT_WIDTH             (2),
+		.AFI_WRITE_DQS_WIDTH       (2),
+		.AFI_RLAT_WIDTH            (6),
+		.AFI_WLAT_WIDTH            (6),
+		.AFI_RRANK_WIDTH           (2),
+		.AFI_WRANK_WIDTH           (2),
+		.MRS_MIRROR_PING_PONG_ATSO (0)
+	) m0 (
+		.clk                   (afi_clk),                      //     clk.clk
+		.afi_addr              (c0_afi_afi_addr),              //     afi.afi_addr
+		.afi_ba                (c0_afi_afi_ba),                //        .afi_ba
+		.afi_ras_n             (c0_afi_afi_ras_n),             //        .afi_ras_n
+		.afi_we_n              (c0_afi_afi_we_n),              //        .afi_we_n
+		.afi_cas_n             (c0_afi_afi_cas_n),             //        .afi_cas_n
+		.afi_odt               (c0_afi_afi_odt),               //        .afi_odt
+		.afi_cke               (c0_afi_afi_cke),               //        .afi_cke
+		.afi_cs_n              (c0_afi_afi_cs_n),              //        .afi_cs_n
+		.afi_dqs_burst         (c0_afi_afi_dqs_burst),         //        .afi_dqs_burst
+		.afi_wdata_valid       (c0_afi_afi_wdata_valid),       //        .afi_wdata_valid
+		.afi_wdata             (c0_afi_afi_wdata),             //        .afi_wdata
+		.afi_dm                (c0_afi_afi_dm),                //        .afi_dm
+		.afi_rdata             (m0_afi_afi_rdata),             //        .afi_rdata
+		.afi_rst_n             (c0_afi_afi_rst_n),             //        .afi_rst_n
+		.afi_rdata_en          (c0_afi_afi_rdata_en),          //        .afi_rdata_en
+		.afi_rdata_en_full     (c0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
+		.afi_rdata_valid       (m0_afi_afi_rdata_valid),       //        .afi_rdata_valid
+		.afi_cal_success       (m0_afi_afi_cal_success),       //        .afi_cal_success
+		.afi_cal_fail          (m0_afi_afi_cal_fail),          //        .afi_cal_fail
+		.afi_wlat              (m0_afi_afi_wlat),              //        .afi_wlat
+		.afi_rlat              (m0_afi_afi_rlat),              //        .afi_rlat
+		.phy_mux_addr          (m0_phy_mux_afi_addr),          // phy_mux.afi_addr
+		.phy_mux_ba            (m0_phy_mux_afi_ba),            //        .afi_ba
+		.phy_mux_ras_n         (m0_phy_mux_afi_ras_n),         //        .afi_ras_n
+		.phy_mux_we_n          (m0_phy_mux_afi_we_n),          //        .afi_we_n
+		.phy_mux_cas_n         (m0_phy_mux_afi_cas_n),         //        .afi_cas_n
+		.phy_mux_odt           (m0_phy_mux_afi_odt),           //        .afi_odt
+		.phy_mux_cke           (m0_phy_mux_afi_cke),           //        .afi_cke
+		.phy_mux_cs_n          (m0_phy_mux_afi_cs_n),          //        .afi_cs_n
+		.phy_mux_dqs_burst     (m0_phy_mux_afi_dqs_burst),     //        .afi_dqs_burst
+		.phy_mux_wdata_valid   (m0_phy_mux_afi_wdata_valid),   //        .afi_wdata_valid
+		.phy_mux_wdata         (m0_phy_mux_afi_wdata),         //        .afi_wdata
+		.phy_mux_dm            (m0_phy_mux_afi_dm),            //        .afi_dm
+		.phy_mux_rdata         (p0_afi_afi_rdata),             //        .afi_rdata
+		.phy_mux_rst_n         (m0_phy_mux_afi_rst_n),         //        .afi_rst_n
+		.phy_mux_rdata_en      (m0_phy_mux_afi_rdata_en),      //        .afi_rdata_en
+		.phy_mux_rdata_en_full (m0_phy_mux_afi_rdata_en_full), //        .afi_rdata_en_full
+		.phy_mux_rdata_valid   (p0_afi_afi_rdata_valid),       //        .afi_rdata_valid
+		.phy_mux_cal_success   (p0_afi_afi_cal_success),       //        .afi_cal_success
+		.phy_mux_cal_fail      (p0_afi_afi_cal_fail),          //        .afi_cal_fail
+		.phy_mux_wlat          (p0_afi_afi_wlat),              //        .afi_wlat
+		.phy_mux_rlat          (p0_afi_afi_rlat),              //        .afi_rlat
+		.seq_mux_addr          (s0_afi_afi_addr),              // seq_mux.afi_addr
+		.seq_mux_ba            (s0_afi_afi_ba),                //        .afi_ba
+		.seq_mux_ras_n         (s0_afi_afi_ras_n),             //        .afi_ras_n
+		.seq_mux_we_n          (s0_afi_afi_we_n),              //        .afi_we_n
+		.seq_mux_cas_n         (s0_afi_afi_cas_n),             //        .afi_cas_n
+		.seq_mux_odt           (s0_afi_afi_odt),               //        .afi_odt
+		.seq_mux_cke           (s0_afi_afi_cke),               //        .afi_cke
+		.seq_mux_cs_n          (s0_afi_afi_cs_n),              //        .afi_cs_n
+		.seq_mux_dqs_burst     (s0_afi_afi_dqs_burst),         //        .afi_dqs_burst
+		.seq_mux_wdata_valid   (s0_afi_afi_wdata_valid),       //        .afi_wdata_valid
+		.seq_mux_wdata         (s0_afi_afi_wdata),             //        .afi_wdata
+		.seq_mux_dm            (s0_afi_afi_dm),                //        .afi_dm
+		.seq_mux_rdata         (m0_seq_mux_afi_rdata),         //        .afi_rdata
+		.seq_mux_rst_n         (s0_afi_afi_rst_n),             //        .afi_rst_n
+		.seq_mux_rdata_en      (s0_afi_afi_rdata_en),          //        .afi_rdata_en
+		.seq_mux_rdata_en_full (s0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
+		.seq_mux_rdata_valid   (m0_seq_mux_afi_rdata_valid),   //        .afi_rdata_valid
+		.mux_sel               (s0_mux_sel_mux_sel)            // mux_sel.mux_sel
+	);
+
+	q_sys_ddr3_ram_s0 s0 (
+		.avl_clk                     (p0_avl_clk_clk),                     //          avl_clk.clk
+		.avl_reset_n                 (p0_avl_reset_reset),                 //        avl_reset.reset_n
+		.phasecounterselect          (s0_pll_reconfig_phasecounterselect), //     pll_reconfig.phasecounterselect
+		.phasestep                   (s0_pll_reconfig_phasestep),          //                 .phasestep
+		.phaseupdown                 (s0_pll_reconfig_phaseupdown),        //                 .phaseupdown
+		.scanclk                     (s0_pll_reconfig_scanclk),            //                 .scanclk
+		.phasedone                   (pll0_pll_reconfig_phasedone),        //                 .phasedone
+		.afi_init_req                (c0_afi_afi_init_req),                // afi_init_cal_req.afi_init_req
+		.afi_cal_req                 (c0_afi_afi_cal_req),                 //                 .afi_cal_req
+		.pd_reset_n                  (s0_phase_detector_pd_reset_n),       //   phase_detector.pd_reset_n
+		.pd_ack                      (s0_phase_detector_pd_ack),           //                 .pd_ack
+		.pd_up                       (p0_phase_detector_pd_up),            //                 .pd_up
+		.pd_down                     (p0_phase_detector_pd_down),          //                 .pd_down
+		.phy_clk                     (p0_phy_phy_clk),                     //              phy.phy_clk
+		.phy_reset_n                 (p0_phy_phy_reset_n),                 //                 .phy_reset_n
+		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),    //                 .phy_read_latency_counter
+		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                //                 .phy_afi_wlat
+		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                //                 .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), //                 .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), //                 .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), //                 .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),        //                 .phy_reset_mem_stable
+		.phy_cal_success             (s0_phy_phy_cal_success),             //                 .phy_cal_success
+		.phy_cal_fail                (s0_phy_phy_cal_fail),                //                 .phy_cal_fail
+		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),          //                 .phy_cal_debug_info
+		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),         //                 .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),    //                 .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),             //                 .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (s0_phy_phy_write_fr_cycle_shifts),   //                 .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (p0_calib_calib_skip_steps),          //            calib.calib_skip_steps
+		.phy_mux_sel                 (s0_mux_sel_mux_sel),                 //          mux_sel.mux_sel
+		.afi_clk                     (afi_clk),                            //          afi_clk.clk
+		.afi_reset_n                 (afi_reset_n),                        //        afi_reset.reset_n
+		.afi_addr                    (s0_afi_afi_addr),                    //              afi.afi_addr
+		.afi_ba                      (s0_afi_afi_ba),                      //                 .afi_ba
+		.afi_ras_n                   (s0_afi_afi_ras_n),                   //                 .afi_ras_n
+		.afi_we_n                    (s0_afi_afi_we_n),                    //                 .afi_we_n
+		.afi_cas_n                   (s0_afi_afi_cas_n),                   //                 .afi_cas_n
+		.afi_odt                     (s0_afi_afi_odt),                     //                 .afi_odt
+		.afi_cke                     (s0_afi_afi_cke),                     //                 .afi_cke
+		.afi_cs_n                    (s0_afi_afi_cs_n),                    //                 .afi_cs_n
+		.afi_dqs_burst               (s0_afi_afi_dqs_burst),               //                 .afi_dqs_burst
+		.afi_wdata_valid             (s0_afi_afi_wdata_valid),             //                 .afi_wdata_valid
+		.afi_wdata                   (s0_afi_afi_wdata),                   //                 .afi_wdata
+		.afi_dm                      (s0_afi_afi_dm),                      //                 .afi_dm
+		.afi_rdata                   (m0_seq_mux_afi_rdata),               //                 .afi_rdata
+		.afi_rst_n                   (s0_afi_afi_rst_n),                   //                 .afi_rst_n
+		.afi_rdata_en                (s0_afi_afi_rdata_en),                //                 .afi_rdata_en
+		.afi_rdata_en_full           (s0_afi_afi_rdata_en_full),           //                 .afi_rdata_en_full
+		.afi_rdata_valid             (m0_seq_mux_afi_rdata_valid)          //                 .afi_rdata_valid
+	);
+
+	q_sys_ddr3_ram_c0 c0 (
+		.afi_reset_n         (afi_reset_n),                //    afi_reset.reset_n
+		.afi_clk             (afi_clk),                    //      afi_clk.clk
+		.afi_half_clk        (afi_half_clk),               // afi_half_clk.clk
+		.local_init_done     (local_init_done),            //       status.local_init_done
+		.local_cal_success   (local_cal_success),          //             .local_cal_success
+		.local_cal_fail      (local_cal_fail),             //             .local_cal_fail
+		.afi_addr            (c0_afi_afi_addr),            //          afi.afi_addr
+		.afi_ba              (c0_afi_afi_ba),              //             .afi_ba
+		.afi_ras_n           (c0_afi_afi_ras_n),           //             .afi_ras_n
+		.afi_we_n            (c0_afi_afi_we_n),            //             .afi_we_n
+		.afi_cas_n           (c0_afi_afi_cas_n),           //             .afi_cas_n
+		.afi_odt             (c0_afi_afi_odt),             //             .afi_odt
+		.afi_cke             (c0_afi_afi_cke),             //             .afi_cke
+		.afi_cs_n            (c0_afi_afi_cs_n),            //             .afi_cs_n
+		.afi_dqs_burst       (c0_afi_afi_dqs_burst),       //             .afi_dqs_burst
+		.afi_wdata_valid     (c0_afi_afi_wdata_valid),     //             .afi_wdata_valid
+		.afi_wdata           (c0_afi_afi_wdata),           //             .afi_wdata
+		.afi_dm              (c0_afi_afi_dm),              //             .afi_dm
+		.afi_rdata           (m0_afi_afi_rdata),           //             .afi_rdata
+		.afi_rst_n           (c0_afi_afi_rst_n),           //             .afi_rst_n
+		.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), //             .afi_mem_clk_disable
+		.afi_init_req        (c0_afi_afi_init_req),        //             .afi_init_req
+		.afi_cal_req         (c0_afi_afi_cal_req),         //             .afi_cal_req
+		.afi_rdata_en        (c0_afi_afi_rdata_en),        //             .afi_rdata_en
+		.afi_rdata_en_full   (c0_afi_afi_rdata_en_full),   //             .afi_rdata_en_full
+		.afi_rdata_valid     (m0_afi_afi_rdata_valid),     //             .afi_rdata_valid
+		.afi_cal_success     (m0_afi_afi_cal_success),     //             .afi_cal_success
+		.afi_cal_fail        (m0_afi_afi_cal_fail),        //             .afi_cal_fail
+		.afi_wlat            (m0_afi_afi_wlat),            //             .afi_wlat
+		.afi_rlat            (m0_afi_afi_rlat),            //             .afi_rlat
+		.avl_ready           (avl_ready),                  //          avl.waitrequest_n
+		.avl_burstbegin      (avl_burstbegin),             //             .beginbursttransfer
+		.avl_addr            (avl_addr),                   //             .address
+		.avl_rdata_valid     (avl_rdata_valid),            //             .readdatavalid
+		.avl_rdata           (avl_rdata),                  //             .readdata
+		.avl_wdata           (avl_wdata),                  //             .writedata
+		.avl_be              (avl_be),                     //             .byteenable
+		.avl_read_req        (avl_read_req),               //             .read
+		.avl_write_req       (avl_write_req),              //             .write
+		.avl_size            (avl_size)                    //             .burstcount
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v
new file mode 100644
index 0000000..ed72f0a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v
@@ -0,0 +1,309 @@
+// q_sys_ddr3_ram_c0.v
+
+// This file was auto-generated from alt_mem_if_nextgen_ddr3_controller_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ddr3_ram_c0 (
+		input  wire        afi_reset_n,         //    afi_reset.reset_n
+		input  wire        afi_clk,             //      afi_clk.clk
+		input  wire        afi_half_clk,        // afi_half_clk.clk
+		output wire        local_init_done,     //       status.local_init_done
+		output wire        local_cal_success,   //             .local_cal_success
+		output wire        local_cal_fail,      //             .local_cal_fail
+		output wire [27:0] afi_addr,            //          afi.afi_addr
+		output wire [5:0]  afi_ba,              //             .afi_ba
+		output wire [1:0]  afi_ras_n,           //             .afi_ras_n
+		output wire [1:0]  afi_we_n,            //             .afi_we_n
+		output wire [1:0]  afi_cas_n,           //             .afi_cas_n
+		output wire [1:0]  afi_odt,             //             .afi_odt
+		output wire [1:0]  afi_cke,             //             .afi_cke
+		output wire [1:0]  afi_cs_n,            //             .afi_cs_n
+		output wire [1:0]  afi_dqs_burst,       //             .afi_dqs_burst
+		output wire [1:0]  afi_wdata_valid,     //             .afi_wdata_valid
+		output wire [31:0] afi_wdata,           //             .afi_wdata
+		output wire [3:0]  afi_dm,              //             .afi_dm
+		input  wire [31:0] afi_rdata,           //             .afi_rdata
+		output wire [1:0]  afi_rst_n,           //             .afi_rst_n
+		output wire [0:0]  afi_mem_clk_disable, //             .afi_mem_clk_disable
+		output wire        afi_init_req,        //             .afi_init_req
+		output wire        afi_cal_req,         //             .afi_cal_req
+		output wire [1:0]  afi_rdata_en,        //             .afi_rdata_en
+		output wire [1:0]  afi_rdata_en_full,   //             .afi_rdata_en_full
+		input  wire [1:0]  afi_rdata_valid,     //             .afi_rdata_valid
+		input  wire        afi_cal_success,     //             .afi_cal_success
+		input  wire        afi_cal_fail,        //             .afi_cal_fail
+		input  wire [5:0]  afi_wlat,            //             .afi_wlat
+		input  wire [5:0]  afi_rlat,            //             .afi_rlat
+		output wire        avl_ready,           //          avl.waitrequest_n
+		input  wire        avl_burstbegin,      //             .beginbursttransfer
+		input  wire [24:0] avl_addr,            //             .address
+		output wire        avl_rdata_valid,     //             .readdatavalid
+		output wire [31:0] avl_rdata,           //             .readdata
+		input  wire [31:0] avl_wdata,           //             .writedata
+		input  wire [3:0]  avl_be,              //             .byteenable
+		input  wire        avl_read_req,        //             .read
+		input  wire        avl_write_req,       //             .write
+		input  wire [2:0]  avl_size             //             .burstcount
+	);
+
+	wire         a0_native_st_itf_wr_data_begin;     // a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
+	wire         ng0_native_st_itf_rd_data_last;     // ng0:itf_rd_data_last -> a0:itf_rd_data_last
+	wire         a0_native_st_itf_cmd_autopercharge; // a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
+	wire         ng0_native_st_itf_rd_data_error;    // ng0:itf_rd_data_error -> a0:itf_rd_data_error
+	wire         a0_native_st_itf_cmd_priority;      // a0:itf_cmd_priority -> ng0:itf_cmd_priority
+	wire   [3:0] a0_native_st_itf_wr_data_byte_en;   // a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
+	wire   [7:0] ng0_native_st_itf_rd_data_id;       // ng0:itf_rd_data_id -> a0:itf_rd_data_id
+	wire  [31:0] a0_native_st_itf_wr_data;           // a0:itf_wr_data -> ng0:itf_wr_data
+	wire         a0_native_st_itf_wr_data_valid;     // a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
+	wire   [7:0] a0_native_st_itf_cmd_id;            // a0:itf_cmd_id -> ng0:itf_cmd_id
+	wire  [31:0] ng0_native_st_itf_rd_data;          // ng0:itf_rd_data -> a0:itf_rd_data
+	wire         ng0_native_st_itf_cmd_ready;        // ng0:itf_cmd_ready -> a0:itf_cmd_ready
+	wire         ng0_native_st_itf_rd_data_begin;    // ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
+	wire         a0_native_st_itf_cmd_multicast;     // a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
+	wire         a0_native_st_itf_wr_data_last;      // a0:itf_wr_data_last -> ng0:itf_wr_data_last
+	wire         ng0_native_st_itf_rd_data_valid;    // ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
+	wire         a0_native_st_itf_cmd_valid;         // a0:itf_cmd_valid -> ng0:itf_cmd_valid
+	wire         ng0_native_st_itf_wr_data_ready;    // ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
+	wire         a0_native_st_itf_rd_data_ready;     // a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
+	wire   [2:0] a0_native_st_itf_cmd_burstlen;      // a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
+	wire         a0_native_st_itf_cmd;               // a0:itf_cmd -> ng0:itf_cmd
+	wire  [24:0] a0_native_st_itf_cmd_address;       // a0:itf_cmd_address -> ng0:itf_cmd_address
+	wire   [7:0] a0_native_st_itf_wr_data_id;        // a0:itf_wr_data_id -> ng0:itf_wr_data_id
+
+	alt_mem_if_nextgen_ddr3_controller_core #(
+		.MEM_IF_ADDR_WIDTH                (14),
+		.MEM_IF_ROW_ADDR_WIDTH            (14),
+		.MEM_IF_COL_ADDR_WIDTH            (10),
+		.MEM_IF_DM_WIDTH                  (1),
+		.MEM_IF_DQS_WIDTH                 (1),
+		.MEM_IF_CS_WIDTH                  (1),
+		.MEM_IF_CHIP_BITS                 (1),
+		.MEM_IF_BANKADDR_WIDTH            (3),
+		.MEM_IF_DQ_WIDTH                  (8),
+		.MEM_IF_CLK_EN_WIDTH              (1),
+		.MEM_IF_CLK_PAIR_COUNT            (1),
+		.MEM_TRC                          (15),
+		.MEM_TRAS                         (11),
+		.MEM_TRCD                         (5),
+		.MEM_TRP                          (5),
+		.MEM_TREFI                        (2341),
+		.MEM_TRFC                         (34),
+		.MEM_TWR                          (5),
+		.MEM_TFAW                         (10),
+		.MEM_TRRD                         (2),
+		.MEM_TRTP                         (3),
+		.MEM_IF_ODT_WIDTH                 (1),
+		.MEM_WTCL_INT                     (5),
+		.MEM_IF_RD_TO_WR_TURNAROUND_OCT   (2),
+		.MEM_IF_WR_TO_RD_TURNAROUND_OCT   (3),
+		.CTL_RD_TO_PCH_EXTRA_CLK          (0),
+		.CTL_RD_TO_RD_EXTRA_CLK           (0),
+		.CTL_WR_TO_WR_EXTRA_CLK           (0),
+		.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK (1),
+		.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK (1),
+		.MEM_TCL                          (5),
+		.MEM_TMRD_CK                      (4),
+		.MEM_TWTR                         (6),
+		.CSR_ADDR_WIDTH                   (8),
+		.CSR_DATA_WIDTH                   (32),
+		.CSR_BE_WIDTH                     (4),
+		.CTL_CS_WIDTH                     (1),
+		.AVL_ADDR_WIDTH                   (25),
+		.AVL_BE_WIDTH                     (4),
+		.AVL_DATA_WIDTH                   (32),
+		.AVL_SIZE_WIDTH                   (3),
+		.DWIDTH_RATIO                     (4),
+		.CTL_ODT_ENABLED                  (0),
+		.CTL_OUTPUT_REGD                  (0),
+		.CTL_ECC_MULTIPLES_16_24_40_72    (1),
+		.CTL_REGDIMM_ENABLED              (0),
+		.CTL_TBP_NUM                      (4),
+		.CTL_USR_REFRESH                  (0),
+		.CFG_TYPE                         (2),
+		.CFG_INTERFACE_WIDTH              (8),
+		.CFG_BURST_LENGTH                 (8),
+		.CFG_ADDR_ORDER                   (0),
+		.CFG_PDN_EXIT_CYCLES              (10),
+		.CFG_POWER_SAVING_EXIT_CYCLES     (5),
+		.CFG_MEM_CLK_ENTRY_CYCLES         (20),
+		.CFG_SELF_RFSH_EXIT_CYCLES        (512),
+		.CFG_PORT_WIDTH_WRITE_ODT_CHIP    (1),
+		.CFG_PORT_WIDTH_READ_ODT_CHIP     (1),
+		.CFG_WRITE_ODT_CHIP               (1),
+		.CFG_READ_ODT_CHIP                (0),
+		.LOCAL_CS_WIDTH                   (0),
+		.CFG_CLR_INTR                     (0),
+		.CFG_ENABLE_NO_DM                 (0),
+		.MEM_ADD_LAT                      (0),
+		.CTL_ENABLE_BURST_INTERRUPT_INT   (0),
+		.CTL_ENABLE_BURST_TERMINATE_INT   (0),
+		.CFG_ERRCMD_FIFO_REG              (0),
+		.CFG_ECC_DECODER_REG              (0),
+		.CTL_ENABLE_WDATA_PATH_LATENCY    (0),
+		.CFG_STARVE_LIMIT                 (10),
+		.MEM_AUTO_PD_CYCLES               (0),
+		.CONTINUE_AFTER_CAL_FAIL          (0),
+		.MAX10_CFG                        (1),
+		.CFG_REORDER_DATA                 (1),
+		.CTL_CSR_ENABLED                  (0),
+		.CTL_ECC_ENABLED                  (0),
+		.CTL_ECC_AUTO_CORRECTION_ENABLED  (0),
+		.ENABLE_BURST_MERGE               (0),
+		.LOCAL_ID_WIDTH                   (8),
+		.RDBUFFER_ADDR_WIDTH              (7),
+		.WRBUFFER_ADDR_WIDTH              (6),
+		.MAX_PENDING_WR_CMD               (16),
+		.MAX_PENDING_RD_CMD               (32),
+		.CFG_DATA_REORDERING_TYPE         ("INTER_BANK"),
+		.USE_DQS_TRACKING                 (0),
+		.USE_SHADOW_REGS                  (0),
+		.AFI_RATE_RATIO                   (2),
+		.AFI_ADDR_WIDTH                   (28),
+		.AFI_BANKADDR_WIDTH               (6),
+		.AFI_CONTROL_WIDTH                (2),
+		.AFI_CS_WIDTH                     (2),
+		.AFI_CLK_EN_WIDTH                 (2),
+		.AFI_DM_WIDTH                     (4),
+		.AFI_DQ_WIDTH                     (32),
+		.AFI_ODT_WIDTH                    (2),
+		.AFI_WRITE_DQS_WIDTH              (2),
+		.AFI_RLAT_WIDTH                   (6),
+		.AFI_WLAT_WIDTH                   (6),
+		.AFI_RRANK_WIDTH                  (2),
+		.AFI_WRANK_WIDTH                  (2)
+	) ng0 (
+		.afi_reset_n             (afi_reset_n),                          //    afi_reset.reset_n
+		.afi_half_clk            (afi_half_clk),                         // afi_half_clk.clk
+		.afi_clk                 (afi_clk),                              //      afi_clk.clk
+		.local_init_done         (local_init_done),                      //       status.local_init_done
+		.local_cal_success       (local_cal_success),                    //             .local_cal_success
+		.local_cal_fail          (local_cal_fail),                       //             .local_cal_fail
+		.itf_cmd_ready           (ng0_native_st_itf_cmd_ready),          //    native_st.itf_cmd_ready
+		.itf_cmd_valid           (a0_native_st_itf_cmd_valid),           //             .itf_cmd_valid
+		.itf_cmd                 (a0_native_st_itf_cmd),                 //             .itf_cmd
+		.itf_cmd_address         (a0_native_st_itf_cmd_address),         //             .itf_cmd_address
+		.itf_cmd_burstlen        (a0_native_st_itf_cmd_burstlen),        //             .itf_cmd_burstlen
+		.itf_cmd_id              (a0_native_st_itf_cmd_id),              //             .itf_cmd_id
+		.itf_cmd_priority        (a0_native_st_itf_cmd_priority),        //             .itf_cmd_priority
+		.itf_cmd_autopercharge   (a0_native_st_itf_cmd_autopercharge),   //             .itf_cmd_autopercharge
+		.itf_cmd_multicast       (a0_native_st_itf_cmd_multicast),       //             .itf_cmd_multicast
+		.itf_wr_data_ready       (ng0_native_st_itf_wr_data_ready),      //             .itf_wr_data_ready
+		.itf_wr_data_valid       (a0_native_st_itf_wr_data_valid),       //             .itf_wr_data_valid
+		.itf_wr_data             (a0_native_st_itf_wr_data),             //             .itf_wr_data
+		.itf_wr_data_byte_en     (a0_native_st_itf_wr_data_byte_en),     //             .itf_wr_data_byte_en
+		.itf_wr_data_begin       (a0_native_st_itf_wr_data_begin),       //             .itf_wr_data_begin
+		.itf_wr_data_last        (a0_native_st_itf_wr_data_last),        //             .itf_wr_data_last
+		.itf_wr_data_id          (a0_native_st_itf_wr_data_id),          //             .itf_wr_data_id
+		.itf_rd_data_ready       (a0_native_st_itf_rd_data_ready),       //             .itf_rd_data_ready
+		.itf_rd_data_valid       (ng0_native_st_itf_rd_data_valid),      //             .itf_rd_data_valid
+		.itf_rd_data             (ng0_native_st_itf_rd_data),            //             .itf_rd_data
+		.itf_rd_data_error       (ng0_native_st_itf_rd_data_error),      //             .itf_rd_data_error
+		.itf_rd_data_begin       (ng0_native_st_itf_rd_data_begin),      //             .itf_rd_data_begin
+		.itf_rd_data_last        (ng0_native_st_itf_rd_data_last),       //             .itf_rd_data_last
+		.itf_rd_data_id          (ng0_native_st_itf_rd_data_id),         //             .itf_rd_data_id
+		.afi_addr                (afi_addr),                             //          afi.afi_addr
+		.afi_ba                  (afi_ba),                               //             .afi_ba
+		.afi_ras_n               (afi_ras_n),                            //             .afi_ras_n
+		.afi_we_n                (afi_we_n),                             //             .afi_we_n
+		.afi_cas_n               (afi_cas_n),                            //             .afi_cas_n
+		.afi_odt                 (afi_odt),                              //             .afi_odt
+		.afi_cke                 (afi_cke),                              //             .afi_cke
+		.afi_cs_n                (afi_cs_n),                             //             .afi_cs_n
+		.afi_dqs_burst           (afi_dqs_burst),                        //             .afi_dqs_burst
+		.afi_wdata_valid         (afi_wdata_valid),                      //             .afi_wdata_valid
+		.afi_wdata               (afi_wdata),                            //             .afi_wdata
+		.afi_dm                  (afi_dm),                               //             .afi_dm
+		.afi_rdata               (afi_rdata),                            //             .afi_rdata
+		.afi_rst_n               (afi_rst_n),                            //             .afi_rst_n
+		.afi_mem_clk_disable     (afi_mem_clk_disable),                  //             .afi_mem_clk_disable
+		.afi_init_req            (afi_init_req),                         //             .afi_init_req
+		.afi_cal_req             (afi_cal_req),                          //             .afi_cal_req
+		.afi_rdata_en            (afi_rdata_en),                         //             .afi_rdata_en
+		.afi_rdata_en_full       (afi_rdata_en_full),                    //             .afi_rdata_en_full
+		.afi_rdata_valid         (afi_rdata_valid),                      //             .afi_rdata_valid
+		.afi_cal_success         (afi_cal_success),                      //             .afi_cal_success
+		.afi_cal_fail            (afi_cal_fail),                         //             .afi_cal_fail
+		.afi_wlat                (afi_wlat),                             //             .afi_wlat
+		.afi_rlat                (afi_rlat),                             //             .afi_rlat
+		.csr_write_req           (1'b0),                                 //  (terminated)
+		.csr_read_req            (1'b0),                                 //  (terminated)
+		.csr_waitrequest         (),                                     //  (terminated)
+		.csr_addr                (8'b00000000),                          //  (terminated)
+		.csr_be                  (4'b0000),                              //  (terminated)
+		.csr_wdata               (32'b00000000000000000000000000000000), //  (terminated)
+		.csr_rdata               (),                                     //  (terminated)
+		.csr_rdata_valid         (),                                     //  (terminated)
+		.afi_seq_busy            (1'b0),                                 //  (terminated)
+		.afi_ctl_refresh_done    (),                                     //  (terminated)
+		.afi_ctl_long_idle       (),                                     //  (terminated)
+		.afi_rrank               (),                                     //  (terminated)
+		.afi_wrank               (),                                     //  (terminated)
+		.local_multicast         (1'b0),                                 //  (terminated)
+		.local_refresh_req       (1'b0),                                 //  (terminated)
+		.local_refresh_chip      (1'b0),                                 //  (terminated)
+		.local_refresh_ack       (),                                     //  (terminated)
+		.local_self_rfsh_req     (1'b0),                                 //  (terminated)
+		.local_self_rfsh_chip    (1'b0),                                 //  (terminated)
+		.local_self_rfsh_ack     (),                                     //  (terminated)
+		.local_deep_powerdn_req  (1'b0),                                 //  (terminated)
+		.local_deep_powerdn_chip (1'b0),                                 //  (terminated)
+		.local_deep_powerdn_ack  (),                                     //  (terminated)
+		.local_powerdn_ack       (),                                     //  (terminated)
+		.local_priority          (1'b0),                                 //  (terminated)
+		.local_zqcal_req         (1'b0),                                 //  (terminated)
+		.local_zqcal_chip        (1'b0)                                  //  (terminated)
+	);
+
+	alt_mem_ddrx_mm_st_converter #(
+		.AVL_SIZE_WIDTH   (3),
+		.AVL_ADDR_WIDTH   (25),
+		.AVL_DATA_WIDTH   (32),
+		.LOCAL_ID_WIDTH   (8),
+		.CFG_DWIDTH_RATIO (4)
+	) a0 (
+		.ctl_clk               (afi_clk),                            //        afi_clk.clk
+		.ctl_reset_n           (afi_reset_n),                        //      afi_reset.reset_n
+		.ctl_half_clk          (afi_half_clk),                       //   afi_half_clk.clk
+		.ctl_half_clk_reset_n  (afi_reset_n),                        // afi_half_reset.reset_n
+		.avl_ready             (avl_ready),                          //            avl.waitrequest_n
+		.avl_burstbegin        (avl_burstbegin),                     //               .beginbursttransfer
+		.avl_addr              (avl_addr),                           //               .address
+		.avl_rdata_valid       (avl_rdata_valid),                    //               .readdatavalid
+		.avl_rdata             (avl_rdata),                          //               .readdata
+		.avl_wdata             (avl_wdata),                          //               .writedata
+		.avl_be                (avl_be),                             //               .byteenable
+		.avl_read_req          (avl_read_req),                       //               .read
+		.avl_write_req         (avl_write_req),                      //               .write
+		.avl_size              (avl_size),                           //               .burstcount
+		.itf_cmd_ready         (ng0_native_st_itf_cmd_ready),        //      native_st.itf_cmd_ready
+		.itf_cmd_valid         (a0_native_st_itf_cmd_valid),         //               .itf_cmd_valid
+		.itf_cmd               (a0_native_st_itf_cmd),               //               .itf_cmd
+		.itf_cmd_address       (a0_native_st_itf_cmd_address),       //               .itf_cmd_address
+		.itf_cmd_burstlen      (a0_native_st_itf_cmd_burstlen),      //               .itf_cmd_burstlen
+		.itf_cmd_id            (a0_native_st_itf_cmd_id),            //               .itf_cmd_id
+		.itf_cmd_priority      (a0_native_st_itf_cmd_priority),      //               .itf_cmd_priority
+		.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), //               .itf_cmd_autopercharge
+		.itf_cmd_multicast     (a0_native_st_itf_cmd_multicast),     //               .itf_cmd_multicast
+		.itf_wr_data_ready     (ng0_native_st_itf_wr_data_ready),    //               .itf_wr_data_ready
+		.itf_wr_data_valid     (a0_native_st_itf_wr_data_valid),     //               .itf_wr_data_valid
+		.itf_wr_data           (a0_native_st_itf_wr_data),           //               .itf_wr_data
+		.itf_wr_data_byte_en   (a0_native_st_itf_wr_data_byte_en),   //               .itf_wr_data_byte_en
+		.itf_wr_data_begin     (a0_native_st_itf_wr_data_begin),     //               .itf_wr_data_begin
+		.itf_wr_data_last      (a0_native_st_itf_wr_data_last),      //               .itf_wr_data_last
+		.itf_wr_data_id        (a0_native_st_itf_wr_data_id),        //               .itf_wr_data_id
+		.itf_rd_data_ready     (a0_native_st_itf_rd_data_ready),     //               .itf_rd_data_ready
+		.itf_rd_data_valid     (ng0_native_st_itf_rd_data_valid),    //               .itf_rd_data_valid
+		.itf_rd_data           (ng0_native_st_itf_rd_data),          //               .itf_rd_data
+		.itf_rd_data_error     (ng0_native_st_itf_rd_data_error),    //               .itf_rd_data_error
+		.itf_rd_data_begin     (ng0_native_st_itf_rd_data_begin),    //               .itf_rd_data_begin
+		.itf_rd_data_last      (ng0_native_st_itf_rd_data_last),     //               .itf_rd_data_last
+		.itf_rd_data_id        (ng0_native_st_itf_rd_data_id),       //               .itf_rd_data_id
+		.local_multicast       (1'b0),                               //    (terminated)
+		.local_autopch_req     (1'b0),                               //    (terminated)
+		.local_priority        (1'b0)                                //    (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf
new file mode 100644
index 0000000..7e63dbf
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan variation_name="q_sys_ddr3_ram_p0" megafunction_name="altera_mem_if_ddr3_phy_core" specifies="all_ports">
+   <global>
+      <pin name="global_reset_n" direction="input" scope="internal" />
+      <pin name="soft_reset_n" direction="input" scope="internal" />
+      <pin name="csr_soft_reset_req" direction="input" scope="internal" />
+      <pin name="afi_reset_n" direction="output" scope="internal" />
+      <pin name="afi_reset_export_n" direction="output" scope="internal" />
+      <pin name="afi_clk" direction="input" scope="internal" />
+      <pin name="afi_half_clk" direction="input" scope="internal" />
+      <pin name="avl_clk" direction="output" scope="internal" />
+      <pin name="avl_reset_n" direction="output" scope="internal" />
+      <pin name="afi_addr[27..0]" direction="input" scope="internal" />
+      <pin name="afi_addr[0]" direction="input" scope="internal" />
+      <pin name="afi_addr[1]" direction="input" scope="internal" />
+      <pin name="afi_addr[2]" direction="input" scope="internal" />
+      <pin name="afi_addr[3]" direction="input" scope="internal" />
+      <pin name="afi_addr[4]" direction="input" scope="internal" />
+      <pin name="afi_addr[5]" direction="input" scope="internal" />
+      <pin name="afi_addr[6]" direction="input" scope="internal" />
+      <pin name="afi_addr[7]" direction="input" scope="internal" />
+      <pin name="afi_addr[8]" direction="input" scope="internal" />
+      <pin name="afi_addr[9]" direction="input" scope="internal" />
+      <pin name="afi_addr[10]" direction="input" scope="internal" />
+      <pin name="afi_addr[11]" direction="input" scope="internal" />
+      <pin name="afi_addr[12]" direction="input" scope="internal" />
+      <pin name="afi_addr[13]" direction="input" scope="internal" />
+      <pin name="afi_addr[14]" direction="input" scope="internal" />
+      <pin name="afi_addr[15]" direction="input" scope="internal" />
+      <pin name="afi_addr[16]" direction="input" scope="internal" />
+      <pin name="afi_addr[17]" direction="input" scope="internal" />
+      <pin name="afi_addr[18]" direction="input" scope="internal" />
+      <pin name="afi_addr[19]" direction="input" scope="internal" />
+      <pin name="afi_addr[20]" direction="input" scope="internal" />
+      <pin name="afi_addr[21]" direction="input" scope="internal" />
+      <pin name="afi_addr[22]" direction="input" scope="internal" />
+      <pin name="afi_addr[23]" direction="input" scope="internal" />
+      <pin name="afi_addr[24]" direction="input" scope="internal" />
+      <pin name="afi_addr[25]" direction="input" scope="internal" />
+      <pin name="afi_addr[26]" direction="input" scope="internal" />
+      <pin name="afi_addr[27]" direction="input" scope="internal" />
+      <pin name="afi_ba[5..0]" direction="input" scope="internal" />
+      <pin name="afi_ba[0]" direction="input" scope="internal" />
+      <pin name="afi_ba[1]" direction="input" scope="internal" />
+      <pin name="afi_ba[2]" direction="input" scope="internal" />
+      <pin name="afi_ba[3]" direction="input" scope="internal" />
+      <pin name="afi_ba[4]" direction="input" scope="internal" />
+      <pin name="afi_ba[5]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[0]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[1]" direction="input" scope="internal" />
+      <pin name="afi_we_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_we_n[0]" direction="input" scope="internal" />
+      <pin name="afi_we_n[1]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[0]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[1]" direction="input" scope="internal" />
+      <pin name="afi_odt[1..0]" direction="input" scope="internal" />
+      <pin name="afi_odt[0]" direction="input" scope="internal" />
+      <pin name="afi_odt[1]" direction="input" scope="internal" />
+      <pin name="afi_cke[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cke[0]" direction="input" scope="internal" />
+      <pin name="afi_cke[1]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[0]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[1]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[1..0]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[0]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[1..0]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[0]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata[31..0]" direction="input" scope="internal" />
+      <pin name="afi_wdata[0]" direction="input" scope="internal" />
+      <pin name="afi_wdata[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata[2]" direction="input" scope="internal" />
+      <pin name="afi_wdata[3]" direction="input" scope="internal" />
+      <pin name="afi_wdata[4]" direction="input" scope="internal" />
+      <pin name="afi_wdata[5]" direction="input" scope="internal" />
+      <pin name="afi_wdata[6]" direction="input" scope="internal" />
+      <pin name="afi_wdata[7]" direction="input" scope="internal" />
+      <pin name="afi_wdata[8]" direction="input" scope="internal" />
+      <pin name="afi_wdata[9]" direction="input" scope="internal" />
+      <pin name="afi_wdata[10]" direction="input" scope="internal" />
+      <pin name="afi_wdata[11]" direction="input" scope="internal" />
+      <pin name="afi_wdata[12]" direction="input" scope="internal" />
+      <pin name="afi_wdata[13]" direction="input" scope="internal" />
+      <pin name="afi_wdata[14]" direction="input" scope="internal" />
+      <pin name="afi_wdata[15]" direction="input" scope="internal" />
+      <pin name="afi_wdata[16]" direction="input" scope="internal" />
+      <pin name="afi_wdata[17]" direction="input" scope="internal" />
+      <pin name="afi_wdata[18]" direction="input" scope="internal" />
+      <pin name="afi_wdata[19]" direction="input" scope="internal" />
+      <pin name="afi_wdata[20]" direction="input" scope="internal" />
+      <pin name="afi_wdata[21]" direction="input" scope="internal" />
+      <pin name="afi_wdata[22]" direction="input" scope="internal" />
+      <pin name="afi_wdata[23]" direction="input" scope="internal" />
+      <pin name="afi_wdata[24]" direction="input" scope="internal" />
+      <pin name="afi_wdata[25]" direction="input" scope="internal" />
+      <pin name="afi_wdata[26]" direction="input" scope="internal" />
+      <pin name="afi_wdata[27]" direction="input" scope="internal" />
+      <pin name="afi_wdata[28]" direction="input" scope="internal" />
+      <pin name="afi_wdata[29]" direction="input" scope="internal" />
+      <pin name="afi_wdata[30]" direction="input" scope="internal" />
+      <pin name="afi_wdata[31]" direction="input" scope="internal" />
+      <pin name="afi_dm[3..0]" direction="input" scope="internal" />
+      <pin name="afi_dm[0]" direction="input" scope="internal" />
+      <pin name="afi_dm[1]" direction="input" scope="internal" />
+      <pin name="afi_dm[2]" direction="input" scope="internal" />
+      <pin name="afi_dm[3]" direction="input" scope="internal" />
+      <pin name="afi_rdata[31..0]" direction="output" scope="internal" />
+      <pin name="afi_rdata[0]" direction="output" scope="internal" />
+      <pin name="afi_rdata[1]" direction="output" scope="internal" />
+      <pin name="afi_rdata[2]" direction="output" scope="internal" />
+      <pin name="afi_rdata[3]" direction="output" scope="internal" />
+      <pin name="afi_rdata[4]" direction="output" scope="internal" />
+      <pin name="afi_rdata[5]" direction="output" scope="internal" />
+      <pin name="afi_rdata[6]" direction="output" scope="internal" />
+      <pin name="afi_rdata[7]" direction="output" scope="internal" />
+      <pin name="afi_rdata[8]" direction="output" scope="internal" />
+      <pin name="afi_rdata[9]" direction="output" scope="internal" />
+      <pin name="afi_rdata[10]" direction="output" scope="internal" />
+      <pin name="afi_rdata[11]" direction="output" scope="internal" />
+      <pin name="afi_rdata[12]" direction="output" scope="internal" />
+      <pin name="afi_rdata[13]" direction="output" scope="internal" />
+      <pin name="afi_rdata[14]" direction="output" scope="internal" />
+      <pin name="afi_rdata[15]" direction="output" scope="internal" />
+      <pin name="afi_rdata[16]" direction="output" scope="internal" />
+      <pin name="afi_rdata[17]" direction="output" scope="internal" />
+      <pin name="afi_rdata[18]" direction="output" scope="internal" />
+      <pin name="afi_rdata[19]" direction="output" scope="internal" />
+      <pin name="afi_rdata[20]" direction="output" scope="internal" />
+      <pin name="afi_rdata[21]" direction="output" scope="internal" />
+      <pin name="afi_rdata[22]" direction="output" scope="internal" />
+      <pin name="afi_rdata[23]" direction="output" scope="internal" />
+      <pin name="afi_rdata[24]" direction="output" scope="internal" />
+      <pin name="afi_rdata[25]" direction="output" scope="internal" />
+      <pin name="afi_rdata[26]" direction="output" scope="internal" />
+      <pin name="afi_rdata[27]" direction="output" scope="internal" />
+      <pin name="afi_rdata[28]" direction="output" scope="internal" />
+      <pin name="afi_rdata[29]" direction="output" scope="internal" />
+      <pin name="afi_rdata[30]" direction="output" scope="internal" />
+      <pin name="afi_rdata[31]" direction="output" scope="internal" />
+      <pin name="afi_rst_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rst_n[0]" direction="input" scope="internal" />
+      <pin name="afi_rst_n[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_valid[1..0]" direction="output" scope="internal" />
+      <pin name="afi_rdata_valid[0]" direction="output" scope="internal" />
+      <pin name="afi_rdata_valid[1]" direction="output" scope="internal" />
+      <pin name="afi_cal_success" direction="output" scope="internal" />
+      <pin name="afi_cal_fail" direction="output" scope="internal" />
+      <pin name="afi_wlat[5..0]" direction="output" scope="internal" />
+      <pin name="afi_wlat[0]" direction="output" scope="internal" />
+      <pin name="afi_wlat[1]" direction="output" scope="internal" />
+      <pin name="afi_wlat[2]" direction="output" scope="internal" />
+      <pin name="afi_wlat[3]" direction="output" scope="internal" />
+      <pin name="afi_wlat[4]" direction="output" scope="internal" />
+      <pin name="afi_wlat[5]" direction="output" scope="internal" />
+      <pin name="afi_rlat[5..0]" direction="output" scope="internal" />
+      <pin name="afi_rlat[0]" direction="output" scope="internal" />
+      <pin name="afi_rlat[1]" direction="output" scope="internal" />
+      <pin name="afi_rlat[2]" direction="output" scope="internal" />
+      <pin name="afi_rlat[3]" direction="output" scope="internal" />
+      <pin name="afi_rlat[4]" direction="output" scope="internal" />
+      <pin name="afi_rlat[5]" direction="output" scope="internal" />
+      <pin name="phy_clk" direction="output" scope="internal" />
+      <pin name="phy_reset_n" direction="output" scope="internal" />
+      <pin name="phy_read_latency_counter[4..0]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[0]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[1]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[2]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[3]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[5..0]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[0]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[1]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[2]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[3]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[5]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[5..0]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[0]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[1]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[2]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[3]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[5]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_fr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_fr[0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_hr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_hr[0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_qr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_qr[0]" direction="input" scope="internal" />
+      <pin name="phy_reset_mem_stable" direction="input" scope="internal" />
+      <pin name="phy_cal_success" direction="input" scope="internal" />
+      <pin name="phy_cal_fail" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[31..0]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[0]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[1]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[2]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[3]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[4]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[5]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[6]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[7]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[8]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[9]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[10]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[11]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[12]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[13]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[14]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[15]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[16]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[17]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[18]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[19]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[20]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[21]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[22]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[23]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[24]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[25]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[26]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[27]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[28]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[29]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[30]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[31]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_reset[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_reset[0]" direction="input" scope="internal" />
+      <pin name="phy_vfifo_rd_en_override[0..0]" direction="input" scope="internal" />
+      <pin name="phy_vfifo_rd_en_override[0]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_q[31..0]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[0]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[1]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[2]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[3]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[4]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[5]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[6]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[7]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[8]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[9]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[10]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[11]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[12]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[13]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[14]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[15]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[16]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[17]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[18]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[19]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[20]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[21]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[22]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[23]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[24]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[25]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[26]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[27]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[28]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[29]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[30]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[31]" direction="output" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[1..0]" direction="input" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[0]" direction="input" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[1]" direction="input" scope="internal" />
+      <pin name="calib_skip_steps[7..0]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[0]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[1]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[2]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[3]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[4]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[5]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[6]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[7]" direction="output" scope="internal" />
+      <pin name="pd_reset_n" direction="input" scope="internal" />
+      <pin name="pd_ack" direction="input" scope="internal" />
+      <pin name="pd_up" direction="output" scope="internal" />
+      <pin name="pd_down" direction="output" scope="internal" />
+      <pin name="afi_mem_clk_disable[0..0]" direction="input" scope="internal" />
+      <pin name="afi_mem_clk_disable[0]" direction="input" scope="internal" />
+      <pin name="pll_mem_clk" direction="input" scope="internal" />
+      <pin name="pll_write_clk" direction="input" scope="internal" />
+      <pin name="pll_locked" direction="input" scope="internal" />
+      <pin name="pll_capture0_clk" direction="input" scope="internal" />
+      <pin name="pll_capture1_clk" direction="input" scope="internal" />
+      <pin name="mem_a[13..0]" direction="output" scope="external" />
+      <pin name="mem_a[0]" direction="output" scope="external" />
+      <pin name="mem_a[1]" direction="output" scope="external" />
+      <pin name="mem_a[2]" direction="output" scope="external" />
+      <pin name="mem_a[3]" direction="output" scope="external" />
+      <pin name="mem_a[4]" direction="output" scope="external" />
+      <pin name="mem_a[5]" direction="output" scope="external" />
+      <pin name="mem_a[6]" direction="output" scope="external" />
+      <pin name="mem_a[7]" direction="output" scope="external" />
+      <pin name="mem_a[8]" direction="output" scope="external" />
+      <pin name="mem_a[9]" direction="output" scope="external" />
+      <pin name="mem_a[10]" direction="output" scope="external" />
+      <pin name="mem_a[11]" direction="output" scope="external" />
+      <pin name="mem_a[12]" direction="output" scope="external" />
+      <pin name="mem_a[13]" direction="output" scope="external" />
+      <pin name="mem_ba[2..0]" direction="output" scope="external" />
+      <pin name="mem_ba[0]" direction="output" scope="external" />
+      <pin name="mem_ba[1]" direction="output" scope="external" />
+      <pin name="mem_ba[2]" direction="output" scope="external" />
+      <pin name="mem_ck[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_ck[0]" direction="bidir" scope="external" />
+      <pin name="mem_ck_n[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_ck_n[0]" direction="bidir" scope="external" />
+      <pin name="mem_cke[0..0]" direction="output" scope="external" />
+      <pin name="mem_cke[0]" direction="output" scope="external" />
+      <pin name="mem_cs_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_cs_n[0]" direction="output" scope="external" />
+      <pin name="mem_dm[0..0]" direction="output" scope="external" />
+      <pin name="mem_dm[0]" direction="output" scope="external" />
+      <pin name="mem_ras_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_ras_n[0]" direction="output" scope="external" />
+      <pin name="mem_cas_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_cas_n[0]" direction="output" scope="external" />
+      <pin name="mem_we_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_we_n[0]" direction="output" scope="external" />
+      <pin name="mem_reset_n" direction="output" scope="external" />
+      <pin name="mem_dq[7..0]" direction="bidir" scope="external" />
+      <pin name="mem_dq[0]" direction="bidir" scope="external" />
+      <pin name="mem_dq[1]" direction="bidir" scope="external" />
+      <pin name="mem_dq[2]" direction="bidir" scope="external" />
+      <pin name="mem_dq[3]" direction="bidir" scope="external" />
+      <pin name="mem_dq[4]" direction="bidir" scope="external" />
+      <pin name="mem_dq[5]" direction="bidir" scope="external" />
+      <pin name="mem_dq[6]" direction="bidir" scope="external" />
+      <pin name="mem_dq[7]" direction="bidir" scope="external" />
+      <pin name="mem_dqs[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs[0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs_n[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs_n[0]" direction="bidir" scope="external" />
+      <pin name="mem_odt[0..0]" direction="output" scope="external" />
+      <pin name="mem_odt[0]" direction="output" scope="external" />
+   </global>
+</pinplan>
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc
new file mode 100644
index 0000000..a61a169
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc
@@ -0,0 +1,480 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+#####################################################################
+#
+# THIS IS AN AUTO-GENERATED FILE!
+# -------------------------------
+# If you modify this files, all your changes will be lost if you
+# regenerate the core!
+#
+# FILE DESCRIPTION
+# ----------------
+# This file contains the timing constraints for the UniPHY memory
+# interface.
+#    * The timing parameters used by this file are assigned
+#      in the q_sys_ddr3_ram_p0_timing.tcl script.
+#    * The helper routines are defined in q_sys_ddr3_ram_p0_pin_map.tcl
+#
+# NOTE
+# ----
+
+set script_dir [file dirname [info script]]
+
+source "$script_dir/q_sys_ddr3_ram_p0_parameters.tcl"
+source "$script_dir/q_sys_ddr3_ram_p0_timing.tcl"
+source "$script_dir/q_sys_ddr3_ram_p0_pin_map.tcl"
+
+load_package ddr_timing_model
+
+set synthesis_flow 0
+set sta_flow 0
+set fit_flow 0
+if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" } {
+	set synthesis_flow 1
+} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } {
+	set sta_flow 1
+} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_fit" } {
+	set fit_flow 1
+}
+
+set is_es 0
+if { [string match -nocase "*es" $::TimeQuestInfo(part)] } {
+	set is_es 1
+}
+
+####################
+#                  #
+# GENERAL SETTINGS #
+#                  #
+####################
+
+# This is a global setting and will apply to the whole design.
+# This setting is required for the memory interface to be
+# properly constrained.
+derive_clock_uncertainty
+
+# Debug switch. Change to 1 to get more run-time debug information
+set debug 0
+
+# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision
+set_time_format -unit ns -decimal_places 3
+
+# Determine if entity names are on
+set entity_names_on [ q_sys_ddr3_ram_p0_are_entity_names_on ]
+
+##################
+#                #
+# QUERIED TIMING #
+#                #
+##################
+
+set io_standard "$::GLOBAL_q_sys_ddr3_ram_p0_io_standard CLASS I"
+
+
+set outputDQSpathjitter 0.060
+set outputDQSpathjitter_setup_prop 0.25
+set tJITper 0.253 
+
+##################
+#                #
+# DERIVED TIMING #
+#                #
+##################
+
+# These parameters are used to make constraints more readeable
+
+# Half of memory clock cycle
+set half_period [ q_sys_ddr3_ram_p0_round_3dp [ expr $t(CK) / 2.0 ] ]
+
+# Half of reference clock
+set ref_half_period [ q_sys_ddr3_ram_p0_round_3dp [ expr $t(refCK) / 2.0 ] ]
+
+# AFI cycle
+set tCK_AFI [ expr $t(CK) * 2.0 ]
+
+# Minimum delay on data output pins
+set t(wru_output_min_delay_external) [expr $t(DH) + $board(intra_DQS_group_skew)/2 + $ISI(DQ)/2 + $ISI(DQS)/2 - $board(DQ_DQS_skew)]
+set t(wru_output_min_delay_internal) [expr $outputDQSpathjitter*(1.0-$outputDQSpathjitter_setup_prop) + $SSN(rel_pullin_o)]
+set data_output_min_delay [ q_sys_ddr3_ram_p0_round_3dp [ expr - $t(wru_output_min_delay_external) - $t(wru_output_min_delay_internal)]]
+
+# Maximum delay on data output pins
+set t(wru_output_max_delay_external) [expr $t(DS) + $board(intra_DQS_group_skew)/2 + $ISI(DQ)/2 + $ISI(DQS)/2 + $board(DQ_DQS_skew)]
+set t(wru_output_max_delay_internal) [expr $outputDQSpathjitter*$outputDQSpathjitter_setup_prop + $SSN(rel_pushout_o)]
+set data_output_max_delay [ q_sys_ddr3_ram_p0_round_3dp [ expr $t(wru_output_max_delay_external) + $t(wru_output_max_delay_internal)]]
+
+# Minimum delay on address and command paths
+set t(ac_output_min_delay_external) [expr $t(IH) + $board(intra_addr_ctrl_skew) + $ISI(addresscmd_hold) - $board(addresscmd_CK_skew)]
+set t(ac_output_min_delay_internal) [expr $outputDQSpathjitter*(1.0-$outputDQSpathjitter_setup_prop) + $SSN(rel_pullin_o)]
+set ac_min_delay [ q_sys_ddr3_ram_p0_round_3dp [ expr - $t(ac_output_min_delay_external) - $t(ac_output_min_delay_internal)]]
+
+# Maximum delay on address and command paths
+set t(ac_output_max_delay_external) [expr $t(IS) + $board(intra_addr_ctrl_skew) + $ISI(addresscmd_setup) + $board(addresscmd_CK_skew)]
+set t(ac_output_max_delay_internal) [expr $outputDQSpathjitter*$outputDQSpathjitter_setup_prop + $SSN(rel_pushout_o)]
+set ac_max_delay [ q_sys_ddr3_ram_p0_round_3dp [ expr $t(ac_output_max_delay_external) + $t(ac_output_max_delay_internal)]]
+
+if { $debug } {
+	post_message -type info "SDC: Computed Parameters:"
+	post_message -type info "SDC: --------------------"
+	post_message -type info "SDC: half_period: $half_period"
+	post_message -type info "SDC: data_output_min_delay: $data_output_min_delay"
+	post_message -type info "SDC: data_output_max_delay: $data_output_max_delay"
+	post_message -type info "SDC: data_input_min_delay: $data_input_min_delay"
+	post_message -type info "SDC: data_input_max_delay: $data_input_max_delay"
+	post_message -type info "SDC: ac_min_delay: $ac_min_delay"
+	post_message -type info "SDC: ac_max_delay: $ac_max_delay"
+	post_message -type info "SDC: Using Timing Models: Micro"
+}
+
+# This is the main call to the netlist traversal routines
+# that will automatically find all pins and registers required
+# to apply timing constraints.
+# During the fitter, the routines will be called only once
+# and cached data will be used in all subsequent calls.
+if { ! [ info exists q_sys_ddr3_ram_p0_sdc_cache ] } {
+	set q_sys_ddr3_ram_p0_sdc_cache 1
+	q_sys_ddr3_ram_p0_initialize_ddr_db q_sys_ddr3_ram_p0_ddr_db
+} else {
+	if { $debug } {
+		post_message -type info "SDC: reusing cached DDR DB"
+	}
+}
+
+# If multiple instances of this core are present in the
+# design they will all be constrained through the
+# following loop
+set instances [ array names q_sys_ddr3_ram_p0_ddr_db ]
+foreach { inst } $instances {
+	if { [ info exists pins ] } {
+		# Clean-up stale content
+		unset pins
+	}
+	array set pins $q_sys_ddr3_ram_p0_ddr_db($inst)
+
+	set prefix $inst
+	if { $entity_names_on } {
+		set prefix [ string map "| |*:" $inst ]
+		set prefix "*:$prefix"
+	}
+
+	#####################################################
+	#                                                   #
+	# Transfer the pin names to more readable variables #
+	#                                                   #
+	#####################################################
+
+	set dqs_pins $pins(dqs_pins)
+	set dqsn_pins $pins(dqsn_pins)
+	set q_groups [ list ]
+	foreach { q_group } $pins(q_groups) {
+		set q_group $q_group
+		lappend q_groups $q_group
+	}
+	set all_dq_pins [ join [ join $q_groups ] ]
+
+	set ck_pins $pins(ck_pins)
+	set ckn_pins $pins(ckn_pins)
+	set add_pins $pins(add_pins)
+	set ba_pins $pins(ba_pins)
+	set cmd_pins $pins(cmd_pins)
+	set reset_pins $pins(reset_pins)
+	set ac_pins [ concat $add_pins $ba_pins $cmd_pins ]
+	set dm_pins $pins(dm_pins)
+	set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ]
+
+	set pll_ref_clock $pins(pll_ref_clock)
+	set pll_afi_clock $pins(pll_afi_clock)
+	set pll_dq_write_clock $pins(pll_dq_write_clock)
+	set pll_write_clock $pins(pll_write_clock)
+
+	set dqs_in_clocks $pins(dqs_in_clocks)
+	set dqs_out_clocks $pins(dqs_out_clocks)
+	set dqsn_out_clocks $pins(dqsn_out_clocks)
+
+	set afi_reset_reg $pins(afi_reset_reg)
+	set seq_reset_reg $pins(seq_reset_reg)
+	set sync_reg $pins(sync_reg)
+	set read_capture_ddio $pins(read_capture_ddio)
+	set fifo_wraddress_reg $pins(fifo_wraddress_reg)
+	set fifo_rdaddress_reg $pins(fifo_rdaddress_reg)
+	set fifo_wrload_reg $pins(fifo_wrload_reg)
+	set fifo_rdload_reg $pins(fifo_rdload_reg)
+	set fifo_wrdata_reg $pins(fifo_wrdata_reg)
+	set fifo_rddata_reg $pins(fifo_rddata_reg)
+
+	# ----------------------- #
+	# -                     - #
+	# --- REFERENCE CLOCK --- #
+	# -                     - #
+	# ----------------------- #
+
+	# This is the reference clock used by the PLL to derive any other clock in the core
+	if { [get_collection_size [get_clocks -nowarn $pll_ref_clock]] > 0 } { remove_clock $pll_ref_clock }
+	create_clock -period $t(refCK) -waveform [ list 0 $ref_half_period ] $pll_ref_clock
+
+	# ------------------ #
+	# -                - #
+	# --- PLL CLOCKS --- #
+	# -                - #
+	# ------------------ #
+	
+	# AFI clock
+	set local_pll_afi_clk [ q_sys_ddr3_ram_p0_get_or_add_clock_vseries \
+		-target $pll_afi_clock \
+		-suffix "afi_clk" \
+		-source $pll_ref_clock \
+		-multiply_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_mult(PLL_AFI_CLK) \
+		-divide_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_div(PLL_AFI_CLK) \
+		-phase $::GLOBAL_q_sys_ddr3_ram_p0_pll_phase(PLL_AFI_CLK) ]
+	
+	# DQ write clock
+	set local_pll_dq_write_clk [ q_sys_ddr3_ram_p0_get_or_add_clock_vseries \
+		-target $pll_dq_write_clock \
+		-suffix "dq_write_clk" \
+		-source $pll_ref_clock \
+		-multiply_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_mult(PLL_WRITE_CLK) \
+		-divide_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_div(PLL_WRITE_CLK) \
+		-phase $::GLOBAL_q_sys_ddr3_ram_p0_pll_phase(PLL_WRITE_CLK) ]
+
+    	# DQS write clock
+  	set local_pll_write_clk [ q_sys_ddr3_ram_p0_get_or_add_clock_vseries \
+  		-target $pll_write_clock \
+  		-suffix "write_clk" \
+  		-source $pll_ref_clock \
+  		-multiply_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_mult(PLL_MEM_CLK) \
+  		-divide_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_div(PLL_MEM_CLK) \
+  		-phase $::GLOBAL_q_sys_ddr3_ram_p0_pll_phase(PLL_MEM_CLK) ]
+  
+ 	# -------------------- #
+	# -                  - #
+	# --- SYSTEM CLOCK --- #
+	# -                  - #
+	# -------------------- #
+
+	# This is the CK clock
+	foreach { ck_pin } $ck_pins {
+		create_generated_clock -multiply_by 1 -source $pll_write_clock -master_clock "$local_pll_write_clk" $ck_pin -name $ck_pin
+		set_clock_uncertainty -to [get_clocks $ck_pin] 0.025
+	}
+
+	# This is the CK#clock
+	foreach { ckn_pin } $ckn_pins {
+		create_generated_clock -multiply_by 1 -invert -source $pll_write_clock -master_clock "$local_pll_write_clk" $ckn_pin -name $ckn_pin
+		set_clock_uncertainty -to [get_clocks $ckn_pin] 0.025
+	}
+
+        # ------------------- #
+        # -                 - #
+        # --- READ CLOCKS --- #
+        # -                 - #
+        # ------------------- #
+        
+        foreach dqs_in_clock_struct $dqs_in_clocks {
+        	array set dqs_in_clock $dqs_in_clock_struct
+        	# This is the DQS clock for Read Capture analysis (micro model)
+        	create_clock -period $t(CK) -waveform [ list 0 $half_period ] $dqs_in_clock(dqs_pin) -name $dqs_in_clock(dqs_pin)_IN -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -from [ get_clocks $dqs_in_clock(dqs_pin)_IN ] 0
+        }
+        
+        	set resync_clock ${inst}|pll0|upll_memphy|auto_generated|pll1|clk\[2\]
+          	
+                set local_resync_clk [ q_sys_ddr3_ram_p0_get_or_add_clock_vseries \
+          		-target $resync_clock \
+          		-suffix "resync_clk" \
+          		-source $pll_ref_clock \
+          		-multiply_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_mult(PLL_ADDR_CMD_CLK) \
+          		-divide_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_div(PLL_ADDR_CMD_CLK) \
+          		-phase $::GLOBAL_q_sys_ddr3_ram_p0_pll_phase(PLL_ADDR_CMD_CLK) ]
+        
+        
+        	set tracking_clock ${inst}|pll0|upll_memphy|auto_generated|pll1|clk\[3\]
+          	
+                set local_tracking_clk [ q_sys_ddr3_ram_p0_get_or_add_clock_vseries \
+          		-target $tracking_clock \
+          		-suffix "tracking_clk" \
+          		-source $pll_ref_clock \
+          		-multiply_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_mult(PLL_AFI_HALF_CLK) \
+          		-divide_by $::GLOBAL_q_sys_ddr3_ram_p0_pll_div(PLL_AFI_HALF_CLK) \
+          		-phase $::GLOBAL_q_sys_ddr3_ram_p0_pll_phase(PLL_AFI_HALF_CLK) ]
+        
+        
+        
+        for { set i 0 } { $i < $::GLOBAL_q_sys_ddr3_ram_p0_number_of_dqs_groups } { incr i } {
+            set resync_x2_capture_clockname "${inst}_resync_x2_capture_${i}"
+            create_generated_clock -name $resync_x2_capture_clockname -source [get_pins ${inst}|p0|umemphy|dq_ddio\[$i\].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clk] -divide_by 2 [get_pins ${inst}|p0|umemphy|dq_ddio\[$i\].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clkout] -add
+        }
+        
+        # -------------------- #
+        # -                  - #
+        # --- WRITE CLOCKS --- #
+        # -                  - #
+        # -------------------- #
+        
+        # This is the DQS clock for Data Write analysis (micro model)
+        foreach dqs_out_clock_struct $dqs_out_clocks {
+        	array set dqs_out_clock $dqs_out_clock_struct
+        	create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqs_out_clock(dst) -name $dqs_out_clock(dst)_OUT -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -to [ get_clocks $dqs_out_clock(dst)_OUT ] 0
+        }
+        
+        # This is the DQS#clock for Data Write analysis (micro model)
+        foreach dqsn_out_clock_struct $dqsn_out_clocks {
+        	array set dqsn_out_clock $dqsn_out_clock_struct
+        	create_generated_clock -multiply_by 1 -invert -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqsn_out_clock(dst) -name $dqsn_out_clock(dst)_OUT -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -to [ get_clocks $dqsn_out_clock(dst)_OUT ] 0
+        }
+	
+        ##################
+        #                #
+        # READ DATA PATH #
+        #                #
+        ##################
+
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		set_max_skew -from [get_ports $dq_pin] 0.1
+        	}
+        }
+        
+        ###################
+        #                 #
+        # WRITE DATA PATH #
+        #                 #
+        ###################
+        
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		# Specifies the minimum delay difference between the DQS pin and the DQ pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS pin and the DQ pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        	}
+        }
+        
+        foreach { dqsn_pin } $dqsn_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		# Specifies the minimum delay difference between the DQS#pin and the DQ pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS#pin and the DQ pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        	}
+        }
+        
+        foreach dqs_out_clock_struct $dqs_out_clocks {
+        	array set dqs_out_clock $dqs_out_clock_struct
+        
+        	if { [string length $dqs_out_clock(dm_pin)] > 0 } {
+        		# Specifies the minimum delay difference between the DQS and the DM pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS and the DM pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
+        	}
+        }
+        
+        foreach dqsn_out_clock_struct $dqsn_out_clocks {
+        	array set dqsn_out_clock $dqsn_out_clock_struct
+        
+        	if { [string length $dqsn_out_clock(dm_pin)] > 0 } {
+        		# Specifies the minimum delay difference between the DQS and the DM pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS and the DM pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
+        	}
+        }
+        
+        ###################
+        ###
+        ##DQS vs CK PATH #
+        ###
+        ###################
+        
+        foreach { ck_pin } $ck_pins { 
+        	set_output_delay -add_delay -clock [get_clocks $ck_pin] -max [q_sys_ddr3_ram_p0_round_3dp [expr $t(CK) - $t(DQSS)*$t(CK) - $board(minCK_DQS_skew) ]] $dqs_pins
+        	set_output_delay -add_delay -clock [get_clocks $ck_pin] -min [q_sys_ddr3_ram_p0_round_3dp [expr $t(DQSS)*$t(CK) - $board(maxCK_DQS_skew) ]] $dqs_pins
+        	set_false_path -fall_from [get_clocks $local_pll_write_clk ] -to [get_ports $dqs_pins]
+        }
+        
+        ############
+        #          #
+        # A/C PATH #
+        #          #
+        ############
+        
+        foreach { ck_pin } $ck_pins {
+        	# ac_pins can contain input ports such as mem_err_out_n
+        	# Loop through each ac pin to make sure we only apply set_output_delay to output ports
+        	foreach { ac_pin } $ac_pins {
+        		set ac_port [ get_ports $ac_pin ]
+        		if {[get_collection_size $ac_port] > 0} {
+        			if [ get_port_info -is_output_port $ac_port ] {
+        				# Specifies the minimum delay difference between the DQS pin and the address/control pins:
+        				set_output_delay -min $ac_min_delay -clock [get_clocks $ck_pin] $ac_port -add_delay
+        
+        				# Specifies the maximum delay difference between the DQS pin and the address/control pins:
+        				set_output_delay -max $ac_max_delay -clock [get_clocks $ck_pin] $ac_port -add_delay
+        			}
+        		}
+        	}
+        }
+        
+#########################
+#                       #
+#  FALSE PATH           #
+#                       #
+#########################
+
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		        set_false_path -from [get_registers *dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*] -to [get_ports $dq_pin]
+        	}
+        }
+        
+        set_false_path -rise_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ]
+
+        foreach { pin } [concat $dqs_pins $dqsn_pins $ck_pins $ckn_pins $reset_pins] {
+        	set_max_skew -to [get_ports $pin] 0.1
+        }
+
+#########################
+#                       #
+# FITTER OVERCONSTRAINT #
+#                       #
+#########################
+
+        if ($fit_flow) {
+        set_max_delay -from [get_registers *hr_to_fr*] -to [get_registers *out_path_enhanced_ddr*] 2.8
+        set_max_delay -from [get_registers *hr_to_fr*] -to [get_registers *oe_path_enhanced_ddr*] 3.3
+
+        set_min_delay -from [get_registers *input*] -to [get_registers *dq_r*] 0.1
+        }
+
+}
+
+######################
+#                    #
+# REPORT DDR COMMAND #
+#                    #
+######################
+
+add_ddr_report_command "source [list [file join [file dirname [info script]] ${::GLOBAL_q_sys_ddr3_ram_p0_corename}_report_timing.tcl]]"
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv
new file mode 100644
index 0000000..ef87247
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv
@@ -0,0 +1,448 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_ddr3_phy_core; -name IP_TOOL_VERSION 19.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *)
+module q_sys_ddr3_ram_p0 (
+    global_reset_n,
+    soft_reset_n,
+	csr_soft_reset_req,
+	pll_mem_clk,
+	pll_write_clk,
+	pll_capture0_clk,
+	pll_capture1_clk,
+	pll_locked,
+	afi_reset_n,
+	afi_reset_export_n,
+	afi_clk,
+	afi_half_clk,
+	afi_addr,
+	afi_ba,
+	afi_cke,
+	afi_cs_n,
+	afi_ras_n,
+	afi_we_n,
+	afi_cas_n,
+	afi_rst_n,
+	afi_odt,
+	afi_dqs_burst,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_dm,
+	afi_rdata,
+	afi_rdata_en,
+	afi_rdata_en_full,
+	afi_rdata_valid,
+	afi_cal_success,
+	afi_cal_fail,
+	afi_wlat,
+	afi_rlat,
+	afi_mem_clk_disable,
+	mem_a,
+	mem_ba,
+	mem_ck,
+	mem_ck_n,
+	mem_cke,
+	mem_cs_n,
+	mem_dm,
+	mem_ras_n,
+	mem_cas_n,
+	mem_we_n,
+	mem_dq,
+	mem_dqs,
+	mem_dqs_n,
+	mem_reset_n,
+	mem_odt,
+	avl_clk,
+	avl_reset_n,
+	pd_reset_n,
+	pd_ack,
+	pd_up,
+	pd_down,
+	phy_clk,
+	phy_reset_n,
+	phy_read_latency_counter,
+	phy_afi_wlat,
+	phy_afi_rlat,
+	phy_read_increment_vfifo_fr,
+	phy_read_increment_vfifo_hr,
+	phy_read_increment_vfifo_qr,
+	phy_reset_mem_stable,
+	phy_write_fr_cycle_shifts,
+	phy_cal_debug_info,
+	phy_read_fifo_reset,
+	phy_vfifo_rd_en_override,
+	phy_cal_success,
+	phy_cal_fail,
+	phy_read_fifo_q,
+	calib_skip_steps
+);
+
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver. 
+parameter DEVICE_FAMILY = "MAX 10";
+
+// choose between abstract (fast) and regular model
+`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL
+  `define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0
+`endif
+
+parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
+
+localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
+
+
+// On-chip termination
+parameter OCT_TERM_CONTROL_WIDTH   = 14;
+
+// PHY-Memory Interface
+// Memory device specific parameters, they are set according to the memory spec.
+parameter MEM_IF_ADDR_WIDTH			= 14;
+parameter MEM_IF_BANKADDR_WIDTH     = 3;
+parameter MEM_IF_CK_WIDTH			= 1;
+parameter MEM_IF_CLK_EN_WIDTH		= 1;
+parameter MEM_IF_CS_WIDTH			= 1;
+parameter MEM_IF_DM_WIDTH         	= 1;
+parameter MEM_IF_CONTROL_WIDTH    	= 1; 
+parameter MEM_IF_DQ_WIDTH         	= 8;
+parameter MEM_IF_DQS_WIDTH         	= 1;
+parameter MEM_IF_READ_DQS_WIDTH    	= 1;
+parameter MEM_IF_WRITE_DQS_WIDTH   	= 1;
+parameter MEM_IF_ODT_WIDTH         	= 1;
+parameter MEM_IF_NUMBER_OF_RANKS	= 1;
+
+// PHY-Controller (AFI) Interface
+// The AFI interface widths are derived from the memory interface widths based on full/half rate operations.
+// The calculations are done on higher level wrapper.
+parameter AFI_ADDR_WIDTH 	        = 28; 
+parameter AFI_DM_WIDTH 	        	= 4; 
+parameter AFI_BANKADDR_WIDTH        = 6; 
+parameter AFI_CS_WIDTH				= 2;
+parameter AFI_CLK_EN_WIDTH          = 2;
+parameter AFI_CONTROL_WIDTH         = 2; 
+parameter AFI_ODT_WIDTH             = 2; 
+parameter AFI_DQ_WIDTH				= 32; 
+parameter AFI_WRITE_DQS_WIDTH		= 2;
+parameter AFI_RATE_RATIO			= 2;
+parameter AFI_WLAT_WIDTH			= 6;
+parameter AFI_RLAT_WIDTH			= 6;
+parameter AFI_RRANK_WIDTH           = 2;
+parameter AFI_WRANK_WIDTH           = 2;
+
+// DLL Interface
+parameter DLL_DELAY_CTRL_WIDTH	= 6;
+
+parameter SCC_DATA_WIDTH            = 1;
+
+parameter NUM_SUBGROUP_PER_READ_DQS        = 1;
+parameter QVLD_EXTRA_FLOP_STAGES		   = 0;
+parameter QVLD_WR_ADDRESS_OFFSET		   = 4;
+	
+// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture.
+// Read valid prediction FIFO
+parameter READ_VALID_FIFO_SIZE             = 16;
+
+// Data resynchronization FIFO
+parameter READ_FIFO_SIZE                   = 8;
+
+// Latency calibration parameters
+parameter MAX_LATENCY_COUNT_WIDTH		   = 5; // calibration finds the best latency by reducing the maximum latency
+localparam MAX_READ_LATENCY				   = 2**MAX_LATENCY_COUNT_WIDTH; 
+
+// Write Datapath
+// The sequencer uses this value to control write latency during calibration
+parameter MAX_WRITE_LATENCY_COUNT_WIDTH = 4;
+parameter NUM_WRITE_PATH_FLOP_STAGES    = 1;
+parameter NUM_WRITE_FR_CYCLE_SHIFTS = 1;
+
+// Add additional FF stage between core and periphery
+parameter REGISTER_C2P = "false";
+
+// Address/Command Datapath
+parameter NUM_AC_FR_CYCLE_SHIFTS = 0;
+
+parameter MR1_ODS								= 0;
+parameter MR1_RTT								= 0;
+parameter MR2_RTT_WR							= 0;
+parameter MEM_T_WL								= 5;
+
+localparam MEM_T_RL								= 5;
+
+// The sequencer issues back-to-back reads during calibration, NOPs may need to be inserted depending on the burst length
+parameter SEQ_BURST_COUNT_WIDTH = 1;
+
+// The DLL offset control width
+parameter DLL_OFFSET_CTRL_WIDTH = 6;
+
+parameter MEM_CLK_FREQ = 300.0;
+parameter DELAY_BUFFER_MODE = "HIGH";
+parameter DQS_DELAY_CHAIN_PHASE_SETTING = 2;
+parameter DQS_PHASE_SHIFT = 9000;
+parameter DELAYED_CLOCK_PHASE_SETTING = 2;
+parameter AFI_DEBUG_INFO_WIDTH = 32;
+
+parameter CALIB_REG_WIDTH = 8;
+
+
+parameter TB_PROTOCOL       = "DDR3";
+parameter TB_MEM_CLK_FREQ   = "300.0";
+parameter TB_RATE           = "HALF";
+parameter TB_MEM_DQ_WIDTH   = "8";
+parameter TB_MEM_DQS_WIDTH  = "1";
+parameter TB_PLL_DLL_MASTER = "true";
+
+parameter FAST_SIM_CALIBRATION = "false";
+
+
+parameter EXTRA_VFIFO_SHIFT = 0;
+
+localparam SIM_FILESET = ("false" == "true");
+
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+
+// ******************************************************************************************************************************** 
+// BEGIN PORT SECTION
+
+
+// When the PHY is selected to be a PLL/DLL SLAVE, the PLL and DLL are instantied at the top level of the example design
+input	pll_mem_clk;	
+input	pll_write_clk;
+input	pll_capture0_clk;
+input	pll_capture1_clk;
+input	pll_locked;
+
+
+
+
+
+
+// Reset Interface, AFI 2.0
+input   global_reset_n;		// Resets (active-low) the whole system (all PHY logic + PLL)
+input	soft_reset_n;		// Resets (active-low) PHY logic only, PLL is NOT reset
+output	afi_reset_export_n;	// Asynchronously asserted and synchronously de-asserted on afi_clk domain
+output	afi_reset_n;		// Asynchronously asserted and synchronously de-asserted on afi_clk domain
+							// should be used to reset system level afi_clk domain logic
+input csr_soft_reset_req;  // Reset request (active_high) being driven by external debug master
+
+// OCT termination control signals
+
+// PHY-Controller Interface, AFI 2.0
+// Control Interface
+input   [AFI_ADDR_WIDTH-1:0]        afi_addr;		// address
+input   [AFI_BANKADDR_WIDTH-1:0]    afi_ba;			// bank
+input   [AFI_CLK_EN_WIDTH-1:0]      afi_cke;		// clock enable
+input   [AFI_CS_WIDTH-1:0]          afi_cs_n;		// chip select
+input   [AFI_CONTROL_WIDTH-1:0]     afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_cas_n;
+input   [AFI_ODT_WIDTH-1:0]         afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_rst_n;
+
+
+// Write data interface
+input   [AFI_WRITE_DQS_WIDTH-1:0]   afi_dqs_burst;
+input   [AFI_DQ_WIDTH-1:0]          afi_wdata;			// write data
+input	[AFI_WRITE_DQS_WIDTH-1:0]	afi_wdata_valid;	// write data valid, used to maintain write latency required by protocol spec
+input   [AFI_DM_WIDTH-1:0]          afi_dm;				// write data mask
+
+// Read data interface
+output  [AFI_DQ_WIDTH-1:0]    afi_rdata;           // read data				
+input   [AFI_RATE_RATIO-1:0]  afi_rdata_en;        // read enable, used to maintain the read latency calibrated by PHY
+input   [AFI_RATE_RATIO-1:0]  afi_rdata_en_full;   // read enable full burst, used to create DQS enable
+output  [AFI_RATE_RATIO-1:0]  afi_rdata_valid;     // read data valid
+
+
+// Status interface
+output  afi_cal_success;	// calibration success
+output  afi_cal_fail;		// calibration failure
+
+output [AFI_WLAT_WIDTH-1:0]			afi_wlat;
+output [AFI_RLAT_WIDTH-1:0]			afi_rlat;
+input  [MEM_IF_CK_WIDTH-1:0] afi_mem_clk_disable;
+
+
+// Ping Pong PHY signals
+
+// PHY-Memory Interface
+
+output  [MEM_IF_ADDR_WIDTH-1:0]       mem_a;        // address
+output  [MEM_IF_BANKADDR_WIDTH-1:0]   mem_ba;       // bank
+inout   [MEM_IF_CK_WIDTH-1:0]         mem_ck;       // differential address and command clock
+inout   [MEM_IF_CK_WIDTH-1:0]         mem_ck_n;
+output  [MEM_IF_CLK_EN_WIDTH-1:0]     mem_cke;      // clock enable
+output  [MEM_IF_CS_WIDTH-1:0]         mem_cs_n;     // chip select
+output  [MEM_IF_DM_WIDTH-1:0]         mem_dm;       // data mask
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_ras_n;		
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_cas_n;		
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_we_n;		
+inout	[MEM_IF_DQ_WIDTH-1:0]         mem_dq;       // bidirectional data bus
+inout	[MEM_IF_DQS_WIDTH-1:0]        mem_dqs;      // bidirectional data strobe
+inout	[MEM_IF_DQS_WIDTH-1:0]        mem_dqs_n;    // differential bidirectional data strobe
+output  [MEM_IF_ODT_WIDTH-1:0]        mem_odt;
+output	                              mem_reset_n;
+
+// PLL Interface
+input	afi_clk;
+input	afi_half_clk;
+
+
+
+
+output  avl_clk;
+output  avl_reset_n;
+input  pd_reset_n;
+input  pd_ack;
+output pd_up;
+output pd_down;
+
+output  phy_clk;
+output  phy_reset_n;
+
+input  [MAX_LATENCY_COUNT_WIDTH-1:0]  phy_read_latency_counter;
+input           [AFI_WLAT_WIDTH-1:0]  phy_afi_wlat;
+input           [AFI_RLAT_WIDTH-1:0]  phy_afi_rlat;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_fr;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_hr;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_qr;
+input                                 phy_reset_mem_stable;
+input	[MEM_IF_WRITE_DQS_WIDTH*2-1:0] phy_write_fr_cycle_shifts;
+input   [AFI_DEBUG_INFO_WIDTH - 1:0]  phy_cal_debug_info;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_fifo_reset;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_vfifo_rd_en_override;
+input                                 phy_cal_success;	// calibration success
+input                                 phy_cal_fail;		// calibration failure
+output            [AFI_DQ_WIDTH-1:0]  phy_read_fifo_q; 
+
+output         [CALIB_REG_WIDTH-1:0]  calib_skip_steps;
+
+
+// END PORT SECTION
+
+
+initial $display("Using %0s core emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular");
+
+
+assign afi_cal_success = phy_cal_success;
+assign afi_cal_fail = phy_cal_fail;
+
+assign avl_clk = afi_clk;
+assign avl_reset_n = afi_reset_n; 
+
+
+integer MEM_T_WL_int = (MEM_T_WL/2);
+assign afi_wlat = MEM_T_WL_int[AFI_WLAT_WIDTH-1:0];
+
+
+// Exporting read latency is currently not supported
+assign afi_rlat = 0;
+
+
+q_sys_ddr3_ram_p0_memphy_m10 #(
+	.DEVICE_FAMILY(DEVICE_FAMILY),
+	.MEM_ADDRESS_WIDTH(MEM_IF_ADDR_WIDTH),
+	.MEM_BANK_WIDTH(MEM_IF_BANKADDR_WIDTH),
+	.MEM_CLK_EN_WIDTH(MEM_IF_CLK_EN_WIDTH),
+	.MEM_CK_WIDTH(MEM_IF_CK_WIDTH),
+	.MEM_ODT_WIDTH(MEM_IF_ODT_WIDTH),
+	.MEM_DQS_WIDTH(MEM_IF_DQS_WIDTH),
+	.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
+	.MEM_DM_WIDTH(MEM_IF_DM_WIDTH),
+	.MEM_CONTROL_WIDTH(MEM_IF_CONTROL_WIDTH),
+	.MEM_DQ_WIDTH(MEM_IF_DQ_WIDTH),
+	.MEM_READ_DQS_WIDTH(MEM_IF_READ_DQS_WIDTH),
+	.MEM_WRITE_DQS_WIDTH(MEM_IF_WRITE_DQS_WIDTH),
+	.AFI_ADDRESS_WIDTH(AFI_ADDR_WIDTH),
+	.AFI_BANK_WIDTH(AFI_BANKADDR_WIDTH),
+	.AFI_CHIP_SELECT_WIDTH(AFI_CS_WIDTH),
+	.AFI_CLK_EN_WIDTH(AFI_CLK_EN_WIDTH),
+	.AFI_ODT_WIDTH(AFI_ODT_WIDTH),
+	.AFI_DATA_MASK_WIDTH(AFI_DM_WIDTH),
+	.AFI_DQS_WIDTH(AFI_WRITE_DQS_WIDTH),
+	.AFI_CONTROL_WIDTH(AFI_CONTROL_WIDTH),
+	.AFI_DATA_WIDTH(AFI_DQ_WIDTH),
+	.AFI_RATE_RATIO(AFI_RATE_RATIO),
+	.MEM_T_RL(MEM_T_RL),
+	.MAX_LATENCY_COUNT_WIDTH(MAX_LATENCY_COUNT_WIDTH),
+	.NUM_WRITE_PATH_FLOP_STAGES(NUM_WRITE_PATH_FLOP_STAGES),
+	.NUM_WRITE_FR_CYCLE_SHIFTS(NUM_WRITE_FR_CYCLE_SHIFTS),
+	.NUM_AC_FR_CYCLE_SHIFTS(NUM_AC_FR_CYCLE_SHIFTS),
+	.CALIB_REG_WIDTH(CALIB_REG_WIDTH),
+	.AFI_DEBUG_INFO_WIDTH(AFI_DEBUG_INFO_WIDTH)
+) umemphy (
+	.global_reset_n(global_reset_n),
+	.soft_reset_n(soft_reset_n & ~csr_soft_reset_req),
+	.ctl_reset_n(afi_reset_n),
+	.ctl_reset_export_n(afi_reset_export_n),
+	.pll_locked(pll_locked),
+	.afi_addr(afi_addr),
+	.afi_ba(afi_ba),
+	.afi_cke(afi_cke),
+	.afi_cs_n(afi_cs_n),
+	.afi_ras_n(afi_ras_n),
+	.afi_we_n(afi_we_n),
+	.afi_cas_n(afi_cas_n),
+	.afi_rst_n(afi_rst_n),
+	.afi_mem_clk_disable(afi_mem_clk_disable),
+	.afi_odt(afi_odt),
+	.afi_dqs_burst(afi_dqs_burst),
+	.afi_wdata(afi_wdata),
+	.afi_wdata_valid(afi_wdata_valid),
+	.afi_dm(afi_dm),
+	.afi_rdata(afi_rdata),
+	.afi_rdata_en(afi_rdata_en),
+	.afi_rdata_valid(afi_rdata_valid),
+	.afi_cal_success(afi_cal_success),
+	.afi_cal_fail(afi_cal_fail),
+	.mem_a(mem_a),
+	.mem_ba(mem_ba),
+	.mem_ck(mem_ck),
+	.mem_ck_n(mem_ck_n),
+	.mem_cke(mem_cke),
+	.mem_cs_n(mem_cs_n),
+	.mem_dm(mem_dm),
+	.mem_ras_n(mem_ras_n),
+	.mem_cas_n(mem_cas_n),
+	.mem_we_n(mem_we_n),
+	.mem_reset_n(mem_reset_n),
+	.mem_dq(mem_dq),
+	.mem_dqs(mem_dqs),
+	.mem_dqs_n(mem_dqs_n),
+	.mem_odt(mem_odt),
+	.pll_afi_clk(afi_clk),
+	.pll_mem_clk(pll_mem_clk),
+	.pll_write_clk(pll_write_clk),
+	.pll_capture0_clk(pll_capture0_clk),
+	.pll_capture1_clk(pll_capture1_clk),
+	.phy_read_latency_counter(phy_read_latency_counter),
+	.phy_read_increment_vfifo_hr(phy_read_increment_vfifo_hr),
+	.phy_cal_debug_info(phy_cal_debug_info),
+	.phy_read_fifo_reset(phy_read_fifo_reset),
+	.phy_vfifo_rd_en_override(phy_vfifo_rd_en_override),
+	.calib_skip_steps(calib_skip_steps),
+	.phy_clk(phy_clk),
+	.phy_reset_n(phy_reset_n),
+	.pd_reset_n(pd_reset_n),
+	.pd_ack(pd_ack),
+	.pd_up(pd_up),
+	.pd_down(pd_down)
+);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v
new file mode 100644
index 0000000..b9ec269
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_addr_cmd_datapath(
+	clk,
+	reset_n,
+	afi_address,
+	afi_bank,
+	afi_cs_n,
+	afi_cke,
+	afi_odt,
+	afi_ras_n,
+	afi_cas_n,
+	afi_we_n,
+	afi_rst_n,
+	phy_ddio_address,
+	phy_ddio_bank,
+	phy_ddio_cs_n,
+	phy_ddio_cke,
+	phy_ddio_we_n,
+	phy_ddio_ras_n,
+	phy_ddio_cas_n,
+	phy_ddio_reset_n,
+	phy_ddio_odt
+);
+
+
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_BANK_WIDTH        = "";
+parameter MEM_CHIP_SELECT_WIDTH = "";
+parameter MEM_CLK_EN_WIDTH 		= "";
+parameter MEM_ODT_WIDTH 		= "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+parameter AFI_ADDRESS_WIDTH         = "";
+parameter AFI_BANK_WIDTH            = "";
+parameter AFI_CHIP_SELECT_WIDTH     = "";
+parameter AFI_CLK_EN_WIDTH     		= "";
+parameter AFI_ODT_WIDTH     		= "";
+parameter AFI_DATA_MASK_WIDTH       = "";
+parameter AFI_CONTROL_WIDTH         = "";
+parameter AFI_DATA_WIDTH            = "";
+
+parameter NUM_AC_FR_CYCLE_SHIFTS    = "";
+
+localparam RATE_MULT = 2;
+
+
+input	reset_n;
+input	clk;
+input	[AFI_ADDRESS_WIDTH-1:0]	afi_address;
+input   [AFI_BANK_WIDTH-1:0] afi_bank;
+input   [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
+input   [AFI_CLK_EN_WIDTH-1:0] afi_cke;
+input   [AFI_ODT_WIDTH-1:0] afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
+
+output	[AFI_ADDRESS_WIDTH-1:0]	phy_ddio_address;
+output	[AFI_BANK_WIDTH-1:0] phy_ddio_bank;
+output	[AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
+output	[AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
+output	[AFI_ODT_WIDTH-1:0] phy_ddio_odt;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
+
+	// some bits of afi_address are tied low during calibration (only a few addresses are used for calibration)
+	// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
+	// sclr pin is very slow and causes timing failures
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_ADDRESS_WIDTH-1:0] afi_address_r;
+	reg [AFI_BANK_WIDTH-1:0] afi_bank_r;
+	reg [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r;
+	reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
+	reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r;
+
+	always @(posedge clk)
+	begin
+		afi_address_r <= afi_address;
+		afi_bank_r <= afi_bank;
+		afi_cs_n_r <= afi_cs_n;
+		afi_cke_r <= afi_cke;
+		afi_odt_r <= afi_odt;
+		afi_ras_n_r <= afi_ras_n;
+		afi_cas_n_r <= afi_cas_n;
+		afi_we_n_r <= afi_we_n;
+		afi_rst_n_r <= afi_rst_n;
+	end
+
+
+	wire [1:0] shift_fr_cycle =
+		(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 	2'b00 : (
+		(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 	2'b01 : (
+		(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 	2'b10 : (
+											2'b11 )));
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_address(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_address_r),
+		.dataout (phy_ddio_address)
+	);
+	defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
+	defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
+
+
+
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_bank_r),
+		.dataout (phy_ddio_bank)
+	);
+	defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
+	defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cke_r),
+		.dataout (phy_ddio_cke)
+	);
+	defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
+	defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cs_n_r),
+		.dataout (phy_ddio_cs_n)
+	);
+	defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
+	defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_odt_r),
+		.dataout (phy_ddio_odt)
+	);
+	defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
+	defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_ras_n_r),
+		.dataout (phy_ddio_ras_n)
+	);
+	defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cas_n_r),
+		.dataout (phy_ddio_cas_n)
+	);
+	defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_we_n_r),
+		.dataout (phy_ddio_we_n)
+	);
+	defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter uaddr_cmd_shift_rst_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_rst_n_r),
+		.dataout (phy_ddio_reset_n)
+	);
+	defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "false";
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v
new file mode 100644
index 0000000..3e8fc96
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v
@@ -0,0 +1,513 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_addr_cmd_pads_m10(
+    reset_n,
+    pll_afi_clk,
+    pll_mem_clk,
+    pll_mem_clk_ddio,
+    pll_write_clk,
+    enable_mem_clk,
+    phy_ddio_address,
+    phy_ddio_cke,
+    phy_ddio_cs_n,
+    phy_ddio_bank,
+    phy_ddio_odt,
+    phy_ddio_we_n,
+    phy_ddio_ras_n,
+    phy_ddio_cas_n,
+    phy_mem_bank,
+    phy_mem_odt,
+    phy_mem_we_n,
+    phy_mem_ras_n,
+    phy_mem_cas_n,
+    phy_ddio_reset_n,
+    phy_mem_reset_n,
+    phy_mem_address,
+    phy_mem_cs_n,
+    phy_mem_cke,
+    phy_mem_ck,
+    phy_mem_ck_n,
+    mimic_clock
+);
+
+// *****************************************************************
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in 
+// from higher level wrapper with the controller and driver
+//Global parameters
+parameter DEVICE_FAMILY = "";
+
+// Width of the addr/cmd signals going out to the external memory
+parameter MEM_ADDRESS_WIDTH     = ""; 
+parameter MEM_CONTROL_WIDTH     = ""; 
+parameter INVERT_OUTPUT_CLOCK   = "";
+parameter MEM_CHIP_SELECT_WIDTH = ""; 
+parameter MEM_CLK_EN_WIDTH      = ""; 
+
+parameter MEM_BANK_WIDTH        = ""; 
+parameter MEM_CK_WIDTH          = ""; 
+parameter MEM_ODT_WIDTH         = ""; 
+
+// Width of the addr/cmd signals coming in from the AFI
+parameter AFI_ADDRESS_WIDTH         = ""; 
+parameter AFI_CONTROL_WIDTH         = ""; 
+parameter AFI_CHIP_SELECT_WIDTH     = ""; 
+parameter AFI_CLK_EN_WIDTH          = ""; 
+
+parameter AFI_BANK_WIDTH            = ""; 
+parameter AFI_ODT_WIDTH             = ""; 
+
+// *****************************************************************
+// BEGIN PORT SECTION
+
+input   reset_n;
+input   pll_afi_clk;
+input   pll_mem_clk;
+input   pll_mem_clk_ddio;
+input   pll_write_clk;
+input   [MEM_CK_WIDTH-1:0]              enable_mem_clk;
+input   [AFI_ADDRESS_WIDTH-1:0]         phy_ddio_address;
+input   [AFI_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n;
+input   [AFI_CLK_EN_WIDTH-1:0]          phy_ddio_cke;
+
+output  [MEM_ADDRESS_WIDTH-1:0]         phy_mem_address;
+output  [MEM_CHIP_SELECT_WIDTH-1:0]     phy_mem_cs_n;
+output  [MEM_CLK_EN_WIDTH-1:0]          phy_mem_cke;
+inout   [MEM_CK_WIDTH-1:0]              phy_mem_ck;
+inout   [MEM_CK_WIDTH-1:0]              phy_mem_ck_n;
+output  mimic_clock;
+input   [AFI_BANK_WIDTH-1:0]            phy_ddio_bank;
+input   [AFI_ODT_WIDTH-1:0]             phy_ddio_odt;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_we_n;
+
+output  [MEM_BANK_WIDTH-1:0]            phy_mem_bank;
+output  [MEM_ODT_WIDTH-1:0]             phy_mem_odt;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_we_n;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_ras_n;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_reset_n;
+output                                  phy_mem_reset_n;
+
+// The rest of this file performs HR->FR conversion for HR interfaces, and
+// FR-SDR->FR-DDR for protocols that require it.
+
+wire    [MEM_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n_l;
+wire    [MEM_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n_h;
+wire    [MEM_CLK_EN_WIDTH-1:0]          phy_ddio_cke_l;
+wire    [MEM_CLK_EN_WIDTH-1:0]          phy_ddio_cke_h;
+
+wire    [MEM_ADDRESS_WIDTH-1:0]         phy_ddio_address_l;
+wire    [MEM_ADDRESS_WIDTH-1:0]         phy_ddio_address_h;
+wire    [MEM_BANK_WIDTH-1:0]            phy_ddio_bank_l;
+wire    [MEM_BANK_WIDTH-1:0]            phy_ddio_bank_h;
+wire    [MEM_ODT_WIDTH-1:0]             phy_ddio_odt_l;
+wire    [MEM_ODT_WIDTH-1:0]             phy_ddio_odt_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_ras_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_ras_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_cas_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_cas_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_we_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_we_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_reset_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_reset_n_h;
+
+// each signal has a high and a low portion,
+// connecting to the high and low inputs of the DDIO_OUT,
+// for the purpose of creating double data rate
+    assign phy_ddio_cke_l           = phy_ddio_cke[MEM_CLK_EN_WIDTH-1:0];
+    assign phy_ddio_cs_n_l          = phy_ddio_cs_n[MEM_CHIP_SELECT_WIDTH-1:0];
+    assign phy_ddio_address_l       = phy_ddio_address[MEM_ADDRESS_WIDTH-1:0];
+    assign phy_ddio_bank_l          = phy_ddio_bank[MEM_BANK_WIDTH-1:0];
+    assign phy_ddio_odt_l           = phy_ddio_odt[MEM_ODT_WIDTH-1:0];
+    assign phy_ddio_we_n_l          = phy_ddio_we_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_ras_n_l         = phy_ddio_ras_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_cas_n_l         = phy_ddio_cas_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_reset_n_l       = phy_ddio_reset_n[MEM_CONTROL_WIDTH-1:0];
+
+    assign phy_ddio_cke_h           = phy_ddio_cke[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
+    assign phy_ddio_cs_n_h          = phy_ddio_cs_n[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
+    assign phy_ddio_address_h       = phy_ddio_address[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
+    assign phy_ddio_bank_h          = phy_ddio_bank[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
+    assign phy_ddio_odt_h           = phy_ddio_odt[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
+    assign phy_ddio_we_n_h          = phy_ddio_we_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_ras_n_h         = phy_ddio_ras_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_cas_n_h         = phy_ddio_cas_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_reset_n_h       = phy_ddio_reset_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+
+// Generate MUXSEL for ADC 
+
+reg gen_muxsel_r1;
+reg gen_muxsel_r2;
+reg muxsel;
+
+always @ (posedge pll_mem_clk)
+begin
+    gen_muxsel_r1 <= reset_n;
+    gen_muxsel_r2 <= gen_muxsel_r1;
+end
+
+generate
+begin: gen_adc_sel
+    always @ (posedge pll_mem_clk)
+        begin
+            if (gen_muxsel_r1 & ~gen_muxsel_r2)
+                muxsel <= 1'b0;
+            else
+                muxsel <= ~muxsel;
+        end
+end
+endgenerate
+
+//if "half_rate_mode = true" in a DDIO_OUT, datain_l is sent out first and datain_h is sent out next
+//if "half_rate_mode = false" in a DDIO_OUT, datain_h is sent out first and datain_l is sent out next
+//in this file (addr_cmd_pads.v), all the address and command pads are instantiated using altddio_out (i.e. half_rate_mode = false)
+//inside io_pads (altdqdqs is used), the output signals to be the memory are sent using 2 layers of DDIO_OUT,
+//first layer with half_rate_mode = true and second layer with half_rate_mode = false
+//so for all the memory write interface signals, datain_l will be sent out first
+//in order to be consistent, address and commands should also follow the same order (i.e. datain_l is sent out first)
+//therefore, phy_ddio_*_h is mapped to datain_l and phy_ddio_*_l is mapped to datain_h for all the altddio_out in this file
+
+    genvar i;
+    generate
+    for (i = 0; i < MEM_ADDRESS_WIDTH; i = i + 1)
+    begin :address_gen
+        addr_cmd_pad_m10 uaddress_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_address_h[i], phy_ddio_address_l[i]}),
+            .datain_lo          ({phy_ddio_address_h[i], phy_ddio_address_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_address[i])
+        );
+        defparam uaddress_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+    generate
+    for (i = 0; i < MEM_CHIP_SELECT_WIDTH; i = i + 1)
+    begin :cs_n_gen
+        addr_cmd_pad_m10 ucs_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cs_n_h[i], phy_ddio_cs_n_l[i]}),
+            .datain_lo          ({phy_ddio_cs_n_h[i], phy_ddio_cs_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_cs_n[i])
+        );
+        defparam ucs_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+    generate
+    for (i = 0; i < MEM_CLK_EN_WIDTH; i = i + 1)
+    begin :cke_gen
+        addr_cmd_pad_m10 ucke_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cke_h[i], phy_ddio_cke_l[i]}),
+            .datain_lo          ({phy_ddio_cke_h[i], phy_ddio_cke_l[i]}),
+            .enable             (1'b1),
+            .pad                (phy_mem_cke[i])
+        );
+        defparam ucke_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+
+    generate
+    for (i = 0; i < MEM_BANK_WIDTH; i = i + 1)
+    begin :bank_gen
+        addr_cmd_pad_m10 ubank_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_bank_h[i], phy_ddio_bank_l[i]}),
+            .datain_lo          ({phy_ddio_bank_h[i], phy_ddio_bank_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_bank[i])
+        );
+        defparam ubank_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+        generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :odt_gen
+        addr_cmd_pad_m10 uodt_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_odt_h[i], phy_ddio_odt_l[i]}),
+            .datain_lo          ({phy_ddio_odt_h[i], phy_ddio_odt_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_odt[i])
+        );
+        defparam uodt_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :we_n_gen
+        addr_cmd_pad_m10 uwe_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_we_n_h[i], phy_ddio_we_n_l[i]}),
+            .datain_lo          ({phy_ddio_we_n_h[i], phy_ddio_we_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_we_n[i])
+        );
+        defparam uwe_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :ras_n_gen
+        addr_cmd_pad_m10 uras_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_ras_n_h[i], phy_ddio_ras_n_l[i]}),
+            .datain_lo          ({phy_ddio_ras_n_h[i], phy_ddio_ras_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_ras_n[i])
+        );
+        defparam uras_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :cas_n_gen
+        addr_cmd_pad_m10 ucas_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cas_n_h[i], phy_ddio_cas_n_l[i]}),
+            .datain_lo          ({phy_ddio_cas_n_h[i], phy_ddio_cas_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_cas_n[i])
+        );
+        defparam ucas_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :reset_n_gen
+        addr_cmd_pad_m10 ureset_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_reset_n_h[i], phy_ddio_reset_n_l[i]}),
+            .datain_lo          ({phy_ddio_reset_n_h[i], phy_ddio_reset_n_l[i]}),
+            .enable             (1'b1),
+            .pad                (phy_mem_reset_n)
+        );
+        defparam ureset_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+
+  wire    [MEM_CK_WIDTH-1:0] mem_ck;
+
+
+//An address/cmd CPS was used to generate mem_ck clock. However, this would only work as 
+//long as the mem_ck clock has same phase as an address/command clock. If they require 
+//different phase setttings (e.g., LPDDR), the fitter cannot merge them and mem_ck cannot 
+//be placed in the same DQSLB as the addr/cmd pins. A DQS CPS is now used for mem_ck to 
+//make its placement flexible (case:31912). Setting the following parameter to 'true' 
+//will turn on the legacy behavior.
+localparam USE_ADDR_CMD_CPS_FOR_MEM_CK = "true";
+
+
+generate
+genvar clock_width;
+        for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
+        begin: clock_gen
+
+        altera_gpio_lite #(
+            .PIN_TYPE                  ("bidir"),
+            .SIZE                      (1),
+            .REGISTER_MODE             ("ddr"),
+            .BUFFER_TYPE               ("pseudo_differential"),
+            .ASYNC_MODE                ("none"),
+            .SYNC_MODE                 ("none"),
+            .BUS_HOLD                  ("false"),
+            .OPEN_DRAIN_OUTPUT         ("false"),
+            .SET_REGISTER_OUTPUTS_HIGH ("false"),
+            .INVERT_OUTPUT             ("false"),
+            .INVERT_INPUT_CLOCK        ("false"),
+            .INVERT_OUTPUT_CLOCK       ("false"),
+            .INVERT_OE_INCLOCK         ("false"),
+            .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+            .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+            .USE_ADVANCED_DDR_FEATURES ("false"),
+            .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+            .ENABLE_HR_CLOCK           ("false"),
+            .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+            .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+            .ENABLE_PHASE_DETECTOR_FOR_CK  ("true")
+
+        ) umem_ck_pad (
+            .sclr                      (1'b0),
+            .outclock                  (pll_mem_clk_ddio),
+            .din                       ({1'b0, enable_mem_clk[clock_width]}),
+            .outclocken                (1'b1),     
+            .inclock                   (1'b0),     
+            .inclocken                 (1'b0),     
+            .fr_clock                  (),         
+            .hr_clock                  (),         
+            .invert_hr_clock           (1'b0),     
+            .phy_mem_clock             (pll_mem_clk_ddio),
+            .dout                      (),         
+            .pad_io                    (phy_mem_ck[clock_width]),
+            .pad_io_b                  (phy_mem_ck_n[clock_width]),
+            .pad_in                    (1'b0),     
+            .pad_in_b                  (1'b0),     
+            .aset                      (1'b0),     
+            .aclr                      (1'b0),     
+            .oe                        (1'b1),     
+            .mimic_clock               (mimic_clock)
+        );
+
+    end
+endgenerate
+
+endmodule
+
+module addr_cmd_pad_m10 (
+        pll_afi_clk,
+        pll_mem_clk,
+        pll_mem_clk_ddio,
+        pll_write_clk,
+        muxsel,
+        datain_hi,
+        datain_lo,
+        enable,
+        pad
+);
+
+parameter INVERT_OUTPUT_CLOCK = "";
+
+input           muxsel;
+input            pll_afi_clk;
+input            pll_mem_clk;
+input            pll_mem_clk_ddio;
+input            pll_write_clk;
+input [1:0]     datain_hi;
+input [1:0]     datain_lo;
+input           enable;
+output          pad;
+
+wire datain_h;
+wire datain_l;
+
+        q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH (1)
+        ) hr_to_fr_lo (
+            .hr_clk         (pll_afi_clk),
+            .fr_clk         (pll_mem_clk),
+            .datain_rise    (datain_hi[1]),
+            .datain_fall    (datain_hi[0]),
+            .muxsel         (muxsel),
+            .dataout        (datain_l)
+        );
+
+        q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH (1)
+        ) hr_to_fr_hi (
+            .hr_clk         (pll_afi_clk),
+            .fr_clk         (pll_mem_clk),
+            .datain_rise    (datain_lo[1]),
+            .datain_fall    (datain_lo[0]),
+            .muxsel         (muxsel),
+            .dataout        (datain_h)
+        );
+
+        altera_gpio_lite #(
+            .PIN_TYPE                  ("output"),
+            .SIZE                      (1),
+            .REGISTER_MODE             ("ddr"),
+            .BUFFER_TYPE               ("single-ended"),
+            .ASYNC_MODE                ("none"),
+            .SYNC_MODE                 ("none"),
+            .BUS_HOLD                  ("false"),
+            .OPEN_DRAIN_OUTPUT         ("false"),
+            .SET_REGISTER_OUTPUTS_HIGH ("false"),
+            .INVERT_OUTPUT             ("false"),
+            .INVERT_INPUT_CLOCK        ("false"),
+            .INVERT_OUTPUT_CLOCK       (INVERT_OUTPUT_CLOCK),
+            .INVERT_OE_INCLOCK         ("false"),
+            .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+            .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+            .USE_ADVANCED_DDR_FEATURES ("true"),
+            .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+            .ENABLE_HR_CLOCK           ("false"),
+            .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+            .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+            .ENABLE_OE_PORT            ("true")
+        ) uadc_pad (
+            .sclr                      (1'b0),
+            .outclock                  (pll_write_clk),
+            .phy_mem_clock             (pll_mem_clk_ddio),
+            .din                       ({datain_h, datain_l}),
+            .pad_out                   (pad),
+            .aclr                      (1'b0),          
+            .outclocken                (1'b1),          
+            .inclock                   (1'b0),          
+            .inclocken                 (1'b0),          
+            .fr_clock                  (),              
+            .hr_clock                  (),              
+            .invert_hr_clock           (1'b0),          
+            .dout                      (),              
+            .pad_io                    (),              
+            .pad_io_b                  (),              
+            .pad_in                    (1'b0),          
+            .pad_in_b                  (1'b0),          
+            .pad_out_b                 (),              
+            .aset                      (1'b0),          
+            .oe                        (enable)
+        );
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v
new file mode 100644
index 0000000..0e4615f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v
@@ -0,0 +1,102 @@
+//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="MAX 10" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
+//VERSION_BEGIN 19.1 cbx_altiobuf_out 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = fiftyfivenm_io_obuf 2 fiftyfivenm_pseudo_diff_out 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_ddr3_ram_p0_clock_pair_generator
+	( 
+	datain,
+	dataout,
+	dataout_b) /* synthesis synthesis_clearbox=1 */;
+	input   [0:0]  datain;
+	output   [0:0]  dataout;
+	output   [0:0]  dataout_b;
+
+	wire  [0:0]   wire_obuf_ba_o;
+	wire  [0:0]   wire_obufa_o;
+	wire  [0:0]   wire_pseudo_diffa_o;
+	wire  [0:0]   wire_pseudo_diffa_obar;
+	wire [0:0]  oe_b;
+	wire  [0:0]  oe_w;
+
+	fiftyfivenm_io_obuf   obuf_ba_0
+	( 
+	.i(wire_pseudo_diffa_obar),
+	.o(wire_obuf_ba_o[0:0]),
+	.obar(),
+	.oe(oe_b)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.seriesterminationcontrol({16{1'b0}})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devoe(1'b1)
+	// synopsys translate_on
+	);
+	defparam
+		obuf_ba_0.bus_hold = "false",
+		obuf_ba_0.open_drain_output = "false",
+		obuf_ba_0.lpm_type = "fiftyfivenm_io_obuf";
+	fiftyfivenm_io_obuf   obufa_0
+	( 
+	.i(wire_pseudo_diffa_o),
+	.o(wire_obufa_o[0:0]),
+	.obar(),
+	.oe(oe_w)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.seriesterminationcontrol({16{1'b0}})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devoe(1'b1)
+	// synopsys translate_on
+	);
+	defparam
+		obufa_0.bus_hold = "false",
+		obufa_0.open_drain_output = "false",
+		obufa_0.lpm_type = "fiftyfivenm_io_obuf";
+	fiftyfivenm_pseudo_diff_out   pseudo_diffa_0
+	( 
+	.i(datain),
+	.o(wire_pseudo_diffa_o[0:0]),
+	.obar(wire_pseudo_diffa_obar[0:0]));
+	assign
+		dataout = wire_obufa_o,
+		dataout_b = wire_obuf_ba_o,
+		oe_b = 1'b1,
+		oe_w = 1'b1;
+endmodule //q_sys_ddr3_ram_p0_clock_pair_generator
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv
new file mode 100644
index 0000000..f13f364
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv
@@ -0,0 +1,414 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_dqdqs_pads_m10 (
+        reset_n_afi_clk,
+        pll_afi_clk,            // PLL AFI clock, 150 MHz, 0 phase        
+        pll_mem_clk_ddio,       // Memory clock, 300MHz, 0 phase, PHYCLK network
+        pll_mem_clk,            // Memory clock, 300MHz, 0 phase, GCLK network
+        pll_write_clk,          // Write and AC clock, 300MHz, -90 phase
+        enable_mem_clk,
+        dq_capture_clk,        // Calibrated Read capture clock, 200MHz
+        read_capture_clk_hr_dq, // Div2 HR dropback clock 
+        invert_hr_clock,
+
+        mem_dqs_n,              // memory DQS#
+
+        rdata_hr,               // FR read data out 
+        write_oe_in,            // write output enable
+        write_data_in,          // write input data
+        output_strobe_ena,      // DQS output enable
+
+        extra_write_data_in,    
+        extra_write_data_out,
+
+        phy_mem_dq,             // memory DQ
+        mem_dqs                // memory DQS
+);
+
+parameter       PIN_WIDTH = 8;
+parameter       EXTRA_OUTPUT_WIDTH = 1;
+parameter       REVERSE_READ_WORDS = "false";
+parameter       MEM_CK_WIDTH = "";
+
+localparam      rate_mult_out =  4 ;
+localparam      WRITE_OE_WIDTH = PIN_WIDTH * rate_mult_out / 2;
+localparam      WRITE_OUPUT_FR_WIDTH = PIN_WIDTH * rate_mult_out / 2;
+localparam      fpga_width_out = PIN_WIDTH * rate_mult_out;
+localparam      extra_fpga_width_out = EXTRA_OUTPUT_WIDTH * rate_mult_out;
+localparam      EXTRA_OUTPUT_FR_WIDTH = EXTRA_OUTPUT_WIDTH * rate_mult_out/2;
+
+localparam      rate_mult_in = 2;
+localparam      READ_PHY_DQ_WIDTH = PIN_WIDTH * rate_mult_in;
+
+input                           reset_n_afi_clk;
+input                           pll_afi_clk;
+input                           pll_mem_clk_ddio;
+input                           pll_mem_clk;
+input                           pll_write_clk;
+input   [MEM_CK_WIDTH-1:0]      enable_mem_clk;
+input                           dq_capture_clk;
+output                          read_capture_clk_hr_dq;
+input                           invert_hr_clock;
+
+inout [PIN_WIDTH-1:0]           phy_mem_dq;
+inout                           mem_dqs;
+inout                           mem_dqs_n;
+output logic [fpga_width_out-1:0]     rdata_hr;
+
+input [WRITE_OE_WIDTH-1:0]      write_oe_in;
+input [fpga_width_out-1:0]      write_data_in;
+input [1:0]                     output_strobe_ena;
+
+input [extra_fpga_width_out-1:0] extra_write_data_in;
+output [EXTRA_OUTPUT_WIDTH-1:0]  extra_write_data_out;
+
+wire [EXTRA_OUTPUT_WIDTH-1:0]   extra_wr_fr_data_hi;
+wire [EXTRA_OUTPUT_WIDTH-1:0]   extra_wr_fr_data_lo;
+
+wire [PIN_WIDTH-1:0]            rd_fr_data_hi;
+wire [PIN_WIDTH-1:0]            rd_fr_data_lo;
+wire [PIN_WIDTH-1:0]            wr_fr_data_hi;
+wire [PIN_WIDTH-1:0]            wr_fr_data_lo;
+wire [PIN_WIDTH-1:0]            fr_oe;
+
+wire                            fr_os_hi;
+wire                            fr_os_lo;
+wire                            fr_os_oe;
+reg                             fr_os_oe_r;
+
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq;
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq_r;
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq_r1;
+logic [PIN_WIDTH-1:0]           read_capture_clk_fr_dq;
+
+reg wrdata_valid_r1;
+reg wrdata_valid_r2;
+reg wrdata_muxsel;
+
+reg wr_dqs_ena_r1;
+reg wr_dqs_ena_r2;
+reg dqs_ena_muxsel;
+
+//############################################
+// Generate the muxsel signal for DQ and DQS
+// these muxsel signal generated in memclk domain
+//############################################
+
+always_ff @ (posedge pll_mem_clk)
+begin
+        wrdata_valid_r1 <= |write_oe_in;
+        wrdata_valid_r2 <= wrdata_valid_r1;
+        wr_dqs_ena_r1 <= |output_strobe_ena;
+        wr_dqs_ena_r2 <= wr_dqs_ena_r1;
+
+end
+
+generate
+begin: gen_wdata_sel
+    always_ff @ (posedge pll_mem_clk)
+        begin
+            if (wrdata_valid_r1 & ~wrdata_valid_r2)
+                wrdata_muxsel <= 1'b1;
+            else
+                wrdata_muxsel <= ~wrdata_muxsel;
+        end
+end
+endgenerate
+
+generate
+begin: gen_dqs_ena_sel
+    always_ff @ (posedge pll_mem_clk)
+        begin
+            if (wr_dqs_ena_r1 & ~wr_dqs_ena_r2)
+                dqs_ena_muxsel <= 1'b1;
+            else
+                dqs_ena_muxsel <= ~dqs_ena_muxsel;
+        end
+end
+endgenerate
+
+generate
+    genvar opin_num;
+    for (opin_num = 0; opin_num < PIN_WIDTH; opin_num = opin_num + 1)
+    begin :output_path_gen
+                wire hr_data_t0 = write_data_in [opin_num + 0*PIN_WIDTH];
+                wire hr_data_t1 = write_data_in [opin_num + 1*PIN_WIDTH];
+                wire hr_data_t2 = write_data_in [opin_num + 2*PIN_WIDTH];
+                wire hr_data_t3 = write_data_in [opin_num + 3*PIN_WIDTH];
+        
+                q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_lo (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t2),
+                    .datain_fall   (hr_data_t0),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (wr_fr_data_lo[opin_num])
+                );
+        
+                q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_hi (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t3),
+                    .datain_fall   (hr_data_t1),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (wr_fr_data_hi[opin_num])
+                );
+        
+                q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_oe (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (write_oe_in [opin_num + PIN_WIDTH]),
+                    .datain_fall   (write_oe_in [opin_num + 0]),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (fr_oe[opin_num])
+                );
+
+                // FR capture
+                always_ff @ (posedge read_capture_clk_fr_dq[opin_num])
+                    begin
+                        ddio_phy_dq_r[opin_num]                 <= ddio_phy_dq[opin_num];
+                        ddio_phy_dq_r[opin_num + PIN_WIDTH]     <= ddio_phy_dq[opin_num + PIN_WIDTH];
+                        ddio_phy_dq_r1[opin_num]                 <= ddio_phy_dq_r[opin_num];
+                        ddio_phy_dq_r1[opin_num + PIN_WIDTH]     <= ddio_phy_dq_r[opin_num + PIN_WIDTH];
+                    end
+                
+        end
+endgenerate
+
+                altera_gpio_lite #(
+                    .PIN_TYPE                  ("bidir"),
+                    .SIZE                      (PIN_WIDTH),
+                    .REGISTER_MODE             ("ddr"),
+                    .BUFFER_TYPE               ("single-ended"),
+                    .ASYNC_MODE                ("none"),
+                    .SYNC_MODE                 ("none"),
+                    .BUS_HOLD                  ("false"),
+                    .OPEN_DRAIN_OUTPUT         ("false"),
+                    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+                    .INVERT_OUTPUT             ("false"),
+                    .INVERT_INPUT_CLOCK        ("true"),
+                    .INVERT_OUTPUT_CLOCK       ("false"),
+                    .INVERT_OE_INCLOCK         ("false"),
+                    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+                    .USE_DDIO_REG_TO_DRIVE_OE  ("true"),
+                    .USE_ADVANCED_DDR_FEATURES ("true"),
+                    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+                    .ENABLE_HR_CLOCK           ("true"),
+                    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+                    .ENABLE_PHASE_INVERT_CTRL_PORT ("true"),
+                    .ENABLE_NSLEEP_PORT        ("true")
+                ) dq_ddio_io (
+                    .sclr                      (1'b0),
+                    .inclock                   (dq_capture_clk),
+                    .fr_clock                  (read_capture_clk_fr_dq),
+                    .hr_clock                  (read_capture_clk_hr_dq),
+                    .invert_hr_clock           (invert_hr_clock), 
+                    .outclock                  (pll_write_clk),
+                    .phy_mem_clock             (pll_mem_clk_ddio),
+                    .dout                      ({rd_fr_data_hi, rd_fr_data_lo}),
+                    .din                       ({wr_fr_data_hi, wr_fr_data_lo}),
+                    .pad_io                    (phy_mem_dq),
+                    .oe                        (fr_oe),
+                    .inclocken                 (1'b1),            
+                    .outclocken                (1'b1),            
+                    .pad_io_b                  (),                
+                    .pad_in                    (8'b0000),         
+                    .pad_in_b                  (8'b0000),         
+                    .pad_out                   (),                
+                    .pad_out_b                 (),                
+                    .aset                      (1'b0),            
+                    .aclr                      (1'b0),            
+                    .nsleep                    ({8{|enable_mem_clk}})
+                    );
+
+generate
+if (REVERSE_READ_WORDS == "true")
+begin
+    assign ddio_phy_dq [PIN_WIDTH -1 : 0] = rd_fr_data_hi;
+    assign ddio_phy_dq [READ_PHY_DQ_WIDTH-1 :PIN_WIDTH] = rd_fr_data_lo;
+end
+else
+begin
+    assign ddio_phy_dq [PIN_WIDTH -1 : 0] = rd_fr_data_lo;
+    assign ddio_phy_dq [READ_PHY_DQ_WIDTH-1 :PIN_WIDTH] = rd_fr_data_hi;
+end
+endgenerate
+
+// FR to HR conversion
+
+always_ff @ (posedge read_capture_clk_hr_dq) rdata_hr <= {ddio_phy_dq_r,ddio_phy_dq_r1};
+
+
+always_ff @ (posedge pll_mem_clk) fr_os_oe_r <= fr_os_oe;
+
+//######################################
+// Instantiate DQS group
+//######################################
+generate
+begin: dqs_en 
+        q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH    (1)
+        ) hr_to_fr_os_oe (
+            .hr_clk        (pll_afi_clk),
+            .fr_clk        (pll_mem_clk),
+            .datain_rise   (output_strobe_ena[1]),
+            .datain_fall   (output_strobe_ena[0]),
+            .muxsel        (dqs_ena_muxsel),
+            .dataout       (fr_os_oe)
+        );
+end
+endgenerate
+
+altera_gpio_lite #(
+    .PIN_TYPE                  ("bidir"),
+    .SIZE                      (1),
+    .REGISTER_MODE             ("ddr"),
+    .BUFFER_TYPE               ("pseudo_differential"),
+    .ASYNC_MODE                ("none"),
+    .SYNC_MODE                 ("none"),
+    .BUS_HOLD                  ("false"),
+    .OPEN_DRAIN_OUTPUT         ("false"),
+    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+    .INVERT_OUTPUT             ("false"),
+    .INVERT_INPUT_CLOCK        ("false"),
+    .INVERT_OUTPUT_CLOCK       ("false"),
+    .INVERT_OE_INCLOCK         ("false"),
+    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+    .USE_DDIO_REG_TO_DRIVE_OE  ("true"),
+    .USE_ADVANCED_DDR_FEATURES ("false"),
+    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+    .ENABLE_HR_CLOCK           ("false"),
+    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+    .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+    .ENABLE_OE_PORT            ("true"),
+    .ENABLE_NSLEEP_PORT        ("true")
+) dqs_ddio_io (
+    .inclock                   (1'b0),
+    .fr_clock                  (),
+    .hr_clock                  (),
+    .invert_hr_clock           (1'b0),
+    .dout                      (),
+    .pad_io                   (mem_dqs),         
+    .pad_io_b                 (mem_dqs_n),       
+    .pad_out                    (),
+    .pad_out_b                  (),
+    .sclr                      (1'b0),
+    .outclock                  (pll_mem_clk_ddio),
+    .phy_mem_clock             (pll_mem_clk_ddio),
+    .din                       (2'b01),
+
+    .oe                        (fr_os_oe_r),
+    .inclocken                 (1'b1),            
+    .outclocken                (1'b1),            
+    .pad_in                    (1'b1),            
+    .pad_in_b                  (1'b1),            
+    .aset                      (1'b0),            
+    .aclr                      (1'b0),            
+    .nsleep                    (|enable_mem_clk)
+    );
+
+
+//######################################
+// Instantiate extra output pins
+//######################################
+generate
+    genvar epin_num;
+    for (epin_num = 0; epin_num < EXTRA_OUTPUT_WIDTH; epin_num = epin_num + 1)
+    begin :extra_output_pad_gen
+            wire hr_data_t0 = extra_write_data_in [epin_num + 0*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t1 = extra_write_data_in [epin_num + 1*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t2 = extra_write_data_in [epin_num + 2*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t3 = extra_write_data_in [epin_num + 3*EXTRA_OUTPUT_WIDTH];
+
+                q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_lo (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t2),
+                    .datain_fall   (hr_data_t0),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (extra_wr_fr_data_lo[epin_num])
+                );
+
+                q_sys_ddr3_ram_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_hi (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t3),
+                    .datain_fall   (hr_data_t1),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (extra_wr_fr_data_hi[epin_num])
+                );
+
+        end
+endgenerate
+                altera_gpio_lite #(
+                    .PIN_TYPE                  ("output"),
+                    .SIZE                      (1),
+                    .REGISTER_MODE             ("ddr"),
+                    .BUFFER_TYPE               ("single-ended"),
+                    .ASYNC_MODE                ("none"),
+                    .SYNC_MODE                 ("none"),
+                    .BUS_HOLD                  ("false"),
+                    .OPEN_DRAIN_OUTPUT         ("false"),
+                    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+                    .INVERT_OUTPUT             ("false"),
+                    .INVERT_INPUT_CLOCK        ("false"),
+                    .INVERT_OUTPUT_CLOCK       ("false"),
+                    .INVERT_OE_INCLOCK         ("false"),
+                    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+                    .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+                    .USE_ADVANCED_DDR_FEATURES ("true"),
+                    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+                    .ENABLE_HR_CLOCK           ("false"),
+                    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+                    .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+                    .ENABLE_OE_PORT            ("true")
+                ) extra_ddio_out (
+                    .sclr                      (1'b0),
+                    .outclock                  (pll_write_clk),                  
+                    .phy_mem_clock             (pll_mem_clk_ddio),             
+                    .din                       ({extra_wr_fr_data_hi, extra_wr_fr_data_lo}),                       
+                    .pad_out                   (extra_write_data_out),                       
+                    .oe                        (|enable_mem_clk),                   
+                    .outclocken                (1'b1),          
+                    .inclock                   (1'b0),          
+                    .inclocken                 (1'b0),          
+                    .fr_clock                  (),              
+                    .hr_clock                  (),              
+                    .invert_hr_clock           (1'b0),          
+                    .dout                      (),              
+                    .pad_io                    (),              
+                    .pad_io_b                  (),              
+                    .pad_in                    (1'b1),          
+                    .pad_in_b                  (1'b1),          
+                    .pad_out_b                 (),              
+                    .aset                      (1'b0),          
+                    .aclr                      (1'b0)           
+                    );
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v
new file mode 100644
index 0000000..e0208c9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v
@@ -0,0 +1,109 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
+module q_sys_ddr3_ram_p0_flop_mem(
+	wr_reset_n,
+	wr_clk,
+	wr_en,
+	wr_addr,
+	wr_data,
+	rd_reset_n,
+	rd_clk,
+	rd_en,
+	rd_addr,
+	rd_data
+);
+
+parameter WRITE_MEM_DEPTH	= "";
+parameter WRITE_ADDR_WIDTH	= "";
+parameter WRITE_DATA_WIDTH	= "";
+parameter READ_MEM_DEPTH	= "";
+parameter READ_ADDR_WIDTH	= "";		 
+parameter READ_DATA_WIDTH	= "";
+
+
+input	wr_reset_n;
+input	wr_clk;
+input	wr_en;
+input	[WRITE_ADDR_WIDTH-1:0] wr_addr;
+input	[WRITE_DATA_WIDTH-1:0] wr_data;
+input	rd_reset_n;
+input	rd_clk;
+input	rd_en;
+input	[READ_ADDR_WIDTH-1:0] rd_addr;
+output	[READ_DATA_WIDTH-1:0] rd_data;
+
+
+
+wire	[WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
+wire	[READ_DATA_WIDTH-1:0] mux_data_out;
+
+
+
+// declare a memory with WRITE_MEM_DEPTH entries
+// each entry contains a data size of WRITE_DATA_WIDTH
+reg	[WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
+reg	[READ_DATA_WIDTH-1:0] rd_data;
+
+generate
+genvar entry;
+	for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
+	begin: mem_location
+		assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry]; 
+		
+		always @(posedge wr_clk or negedge wr_reset_n)
+		begin
+			if (~wr_reset_n) begin
+				data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
+			end else begin
+				if (wr_en) begin
+					if (entry == wr_addr) begin
+						data_stored[entry] <= wr_data;
+					end
+				end
+			end
+		end		
+	end
+endgenerate
+
+// mux to select the correct output data based on read address
+lpm_mux	uread_mux(
+	.sel (rd_addr),
+	.data (all_data),
+	.result (mux_data_out)
+	// synopsys translate_off
+	,
+	.aclr (),
+	.clken (),
+	.clock ()
+	// synopsys translate_on
+	);
+ defparam uread_mux.lpm_size = READ_MEM_DEPTH;
+ defparam uread_mux.lpm_type = "LPM_MUX";
+ defparam uread_mux.lpm_width = READ_DATA_WIDTH;
+ defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
+
+always @(posedge rd_clk or negedge rd_reset_n)	
+begin
+	if (~rd_reset_n) begin
+		rd_data <= {READ_DATA_WIDTH{1'b0}};
+	end else begin
+		rd_data <= mux_data_out;
+	end
+end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v
new file mode 100644
index 0000000..40ee56f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v
@@ -0,0 +1,88 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: fr_cycle_shifter.v
+//
+// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
+// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
+// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
+// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
+// "__" means don't-care.
+//
+// shift_by          dataout in current cycle            dataout in next clock cycle 
+//    00                {T3, T2, T1, T0}                    {__, __, __, __}
+//    01                {T2, T1, T0, __}                    {__, __, __, T3}
+//    10                {T1, T0, __, __}                    {__, __, T3, T2}
+//    11                {T0, __, __, __}                    {__, T3, T2, T1}
+// 
+// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
+// (i.e. you can only shift by 0 or 1 fr-cycle).
+// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
+//
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_fr_cycle_shifter(
+	clk,
+	reset_n,
+	shift_by,
+	datain,
+	dataout
+);
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver 
+
+parameter DATA_WIDTH = ""; 
+parameter REG_POST_RESET_HIGH = "false";
+
+localparam RATE_MULT = 2;
+localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+input	clk;
+input	reset_n;
+input	[1:0] shift_by; 
+input	[FULL_DATA_WIDTH-1:0] datain;
+output	[FULL_DATA_WIDTH-1:0] dataout;
+
+
+reg [FULL_DATA_WIDTH-1:0] datain_r;
+always @(posedge clk or negedge reset_n)
+begin
+	if (~reset_n) begin
+		if (REG_POST_RESET_HIGH == "true")
+			datain_r <= {FULL_DATA_WIDTH{1'b1}};
+		else
+			datain_r <= {FULL_DATA_WIDTH{1'b0}};
+	end else begin
+		datain_r <= datain;
+	end
+end
+
+wire [FULL_DATA_WIDTH-1:0] dataout_pre;
+
+
+wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
+wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
+wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
+
+assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
+	
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v
new file mode 100644
index 0000000..c502117
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v
@@ -0,0 +1,60 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_iss_probe (
+	probe_input
+);
+parameter WIDTH = 1;
+parameter ID_NAME = "PROB";
+
+input [WIDTH-1:0] probe_input;
+
+	
+altsource_probe	iss_probe_inst (
+				.probe (probe_input),
+				.source ()
+				// synopsys translate_off
+				,
+				.clr (),
+				.ena (),
+				.ir_in (),
+				.ir_out (),
+				.jtag_state_cdr (),
+				.jtag_state_cir (),
+				.jtag_state_e1dr (),
+				.jtag_state_sdr (),
+				.jtag_state_tlr (),
+				.jtag_state_udr (),
+				.jtag_state_uir (),
+				.raw_tck (),
+				.source_clk (),
+				.source_ena (),
+				.tdi (),
+				.tdo (),
+				.usr1 ()
+				// synopsys translate_on
+				);
+	defparam
+		iss_probe_inst.enable_metastability = "NO",
+		iss_probe_inst.instance_id = ID_NAME,
+		iss_probe_inst.probe_width = WIDTH,
+		iss_probe_inst.sld_auto_instance_index = "YES",
+		iss_probe_inst.sld_instance_index = 0,
+		iss_probe_inst.source_initial_value = "0",
+		iss_probe_inst.source_width = 0;
+		
+		
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv
new file mode 100644
index 0000000..a7eb65a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv
@@ -0,0 +1,580 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: memphy.v
+// This file instantiates all the main components of the PHY. 
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_memphy_m10(
+    global_reset_n,
+    soft_reset_n,
+    ctl_reset_n,
+    ctl_reset_export_n,
+    pll_locked,
+    afi_addr,
+    afi_cke,
+    afi_cs_n,
+    afi_ba,
+    afi_ras_n,
+    afi_cas_n,
+    afi_we_n,
+    afi_odt,
+    afi_rst_n,
+    afi_mem_clk_disable,
+    afi_dqs_burst,
+    afi_wdata,
+    afi_wdata_valid,
+    afi_dm,
+    afi_rdata,
+    afi_rdata_en,
+    afi_rdata_valid,
+    afi_cal_debug_info,
+    afi_cal_success,
+    afi_cal_fail,
+
+    mem_a,
+    mem_ba,
+    mem_odt,
+    mem_ras_n,
+    mem_cas_n,
+    mem_we_n,
+    mem_reset_n,
+    mem_ck,
+    mem_ck_n,
+    mem_cke,
+    mem_cs_n,
+    mem_dm,
+    mem_dq,
+    mem_dqs,
+    mem_dqs_n,
+    phy_read_latency_counter,
+    phy_read_increment_vfifo_hr,
+    phy_cal_debug_info,
+    phy_read_fifo_reset,
+    phy_vfifo_rd_en_override,
+    calib_skip_steps,
+    pll_afi_clk,
+    pll_mem_clk,
+    pll_write_clk,
+    pll_capture0_clk,
+    pll_capture1_clk,
+    phy_clk,
+    phy_reset_n,
+    
+    pd_reset_n,
+    pd_ack,
+    pd_up,
+    pd_down
+);
+
+//  ******************************************************************************************************************************** 
+//  BEGIN PARAMETER SECTION
+//  All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver 
+parameter DEVICE_FAMILY                         = "";
+
+// PHY-Memory Interface
+// Memory device specific parameters, they are set according to the memory spec
+parameter MEM_ADDRESS_WIDTH                     = ""; 
+parameter MEM_BANK_WIDTH                        = "";
+parameter MEM_CLK_EN_WIDTH                      = ""; 
+parameter MEM_CK_WIDTH                          = ""; 
+parameter MEM_ODT_WIDTH                         = ""; 
+parameter MEM_DQS_WIDTH                         = "";
+parameter MEM_CHIP_SELECT_WIDTH                 = ""; 
+parameter MEM_CONTROL_WIDTH                     = ""; 
+parameter MEM_DM_WIDTH                          = ""; 
+parameter MEM_DQ_WIDTH                          = ""; 
+parameter MEM_READ_DQS_WIDTH                    = ""; 
+parameter MEM_WRITE_DQS_WIDTH                   = "";
+
+//  PHY-Controller (AFI) Interface
+//  The AFI interface widths are derived from the memory interface widths based on full/half rate operations
+//  The calculations are done on higher level wrapper
+parameter AFI_ADDRESS_WIDTH                     = ""; 
+parameter AFI_DEBUG_INFO_WIDTH                  = "";
+parameter AFI_BANK_WIDTH                        = "";
+parameter AFI_CHIP_SELECT_WIDTH                 = "";
+parameter AFI_CLK_EN_WIDTH                      = "";
+parameter AFI_ODT_WIDTH                         = "";
+parameter AFI_DATA_MASK_WIDTH                   = "";
+parameter AFI_CONTROL_WIDTH                     = "";
+parameter AFI_DATA_WIDTH                        = "";
+parameter AFI_DQS_WIDTH                         = "";
+parameter AFI_RATE_RATIO                        = "";
+
+// Write Datapath
+//The sequencer uses this value to control write latency during calibration
+parameter NUM_WRITE_PATH_FLOP_STAGES            = "";
+parameter NUM_WRITE_FR_CYCLE_SHIFTS             = "";
+
+parameter NUM_AC_FR_CYCLE_SHIFTS                = "";
+
+parameter CALIB_REG_WIDTH                       = "";
+
+//  The number of AFI Resets to generate
+localparam NUM_AFI_RESET = 4;
+
+//  Read Datapath parameters
+parameter MEM_T_RL                              = "";
+parameter MAX_LATENCY_COUNT_WIDTH               = "";
+localparam MAX_READ_LATENCY                     = MEM_T_RL/2 + 12; 
+localparam INVERT_HR_CLOCK                      = MEM_T_RL % 2;
+
+//  END PARAMETER SECTION
+//  ******************************************************************************************************************************** 
+
+//  ******************************************************************************************************************************** 
+//  BEGIN PORT SECTION
+
+//   Reset Interface
+input                                            global_reset_n;        //Resets (active-low) the whole system (all PHY logic + PLL)
+input                                            soft_reset_n;        
+input                                            pll_locked;        
+output                                           ctl_reset_export_n;    
+output                                           ctl_reset_n;        
+
+//  PHY-Controller Interface, AFI 2.0
+//  Control Interface
+input   [AFI_ADDRESS_WIDTH-1:0]                 afi_addr;               
+input   [AFI_CLK_EN_WIDTH-1:0]                  afi_cke;
+input   [AFI_CHIP_SELECT_WIDTH-1:0]             afi_cs_n;
+
+input   [AFI_BANK_WIDTH-1:0]                    afi_ba;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_cas_n;
+input   [AFI_ODT_WIDTH-1:0]                     afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_rst_n;
+
+input   [MEM_CK_WIDTH-1:0]                      afi_mem_clk_disable;
+input   [AFI_DQS_WIDTH-1:0]                     afi_dqs_burst;
+
+//  Write data interface
+input   [AFI_DATA_WIDTH-1:0]                    afi_wdata;              //write data
+input   [AFI_DQS_WIDTH-1:0]                     afi_wdata_valid;        
+
+input   [AFI_DATA_MASK_WIDTH-1:0]               afi_dm;                 
+
+//  Read data interface
+output  [AFI_DATA_WIDTH-1:0]                    afi_rdata;              //read data                
+input   [AFI_RATE_RATIO-1:0]                    afi_rdata_en;           
+output  [AFI_RATE_RATIO-1:0]                    afi_rdata_valid;        
+
+//  Status interface
+input                                           afi_cal_success;        //calibration success
+input                                           afi_cal_fail;           
+output  [AFI_DEBUG_INFO_WIDTH - 1:0]            afi_cal_debug_info;
+
+
+//  PHY-Memory Interface
+output  [MEM_ADDRESS_WIDTH-1:0]                 mem_a;
+output  [MEM_BANK_WIDTH-1:0]                    mem_ba;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_ras_n;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_cas_n;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_we_n;
+output  [MEM_ODT_WIDTH-1:0]                     mem_odt;
+output                                          mem_reset_n;
+inout   [MEM_CK_WIDTH-1:0]                      mem_ck;
+inout   [MEM_CK_WIDTH-1:0]                      mem_ck_n;
+output  [MEM_CLK_EN_WIDTH-1:0]                  mem_cke;
+output  [MEM_CHIP_SELECT_WIDTH-1:0]             mem_cs_n;
+output  [MEM_DM_WIDTH-1:0]                      mem_dm;
+inout   [MEM_DQ_WIDTH-1:0]                      mem_dq;
+inout   [MEM_DQS_WIDTH-1:0]                     mem_dqs;
+inout   [MEM_DQS_WIDTH-1:0]                     mem_dqs_n;
+
+input   [MAX_LATENCY_COUNT_WIDTH-1:0]           phy_read_latency_counter;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_read_increment_vfifo_hr;
+input   [AFI_DEBUG_INFO_WIDTH - 1:0]            phy_cal_debug_info;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_read_fifo_reset;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_vfifo_rd_en_override;
+
+output  [CALIB_REG_WIDTH-1:0]                   calib_skip_steps;
+
+//  PLL Interface
+input                                           pll_afi_clk;        //clocks AFI interface logic
+input                                           pll_mem_clk;        
+input                                           pll_write_clk;        
+input                                           pll_capture0_clk;
+input                                           pll_capture1_clk;
+
+//  output to sequencer
+output                                          phy_clk;
+output                                          phy_reset_n;
+
+input                                           pd_reset_n;
+input                                           pd_ack;
+output                                          pd_up;
+output                                          pd_down;
+
+//  END PORT SECTION
+//  ******************************************************************************************************************************** 
+
+// PHY clock tree buffered clock driving to DDIO
+wire                                            pll_mem_clk_ddio;           
+wire                                            pll_write_clk_ddio;      
+wire                                            pll_capture0_clk_ddio;
+wire                                            pll_capture1_clk_ddio;
+
+wire    [AFI_ADDRESS_WIDTH-1:0]                 phy_ddio_address;
+wire    [AFI_BANK_WIDTH-1:0]                    phy_ddio_bank;
+wire    [AFI_CHIP_SELECT_WIDTH-1:0]             phy_ddio_cs_n;
+wire    [AFI_CLK_EN_WIDTH-1:0]                  phy_ddio_cke;
+wire    [AFI_ODT_WIDTH-1:0]                     phy_ddio_odt;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_ras_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_cas_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_we_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_reset_n;
+wire    [AFI_DATA_WIDTH-1:0]                    phy_ddio_dq;
+wire    [AFI_DQS_WIDTH-1:0]                     phy_ddio_dqs_en;
+wire    [AFI_DQS_WIDTH-1:0]                     phy_ddio_wrdata_en;
+wire    [AFI_DATA_MASK_WIDTH-1:0]               phy_ddio_wrdata_mask;
+wire    [AFI_DATA_WIDTH-1:0]                    ddio_phy_dq;
+wire    [MEM_READ_DQS_WIDTH-1:0]                read_capture_clk_hr_dq;
+
+
+wire    [NUM_AFI_RESET-1:0]                     reset_n_afi_clk;
+wire                                            reset_n_resync_clk;
+wire                                            invert_hr_clock;
+
+localparam SKIP_CALIBRATION_STEPS       = 7'b1111111;
+localparam CALIBRATION_STEPS            = SKIP_CALIBRATION_STEPS;
+localparam SKIP_MEM_INIT                = 1'b1;
+localparam SEQ_CALIB_INIT               = {CALIBRATION_STEPS, SKIP_MEM_INIT};
+
+localparam NUM_OF_DQDQS                 = MEM_WRITE_DQS_WIDTH;
+localparam DQDQS_DATA_WIDTH             = MEM_DQ_WIDTH / NUM_OF_DQDQS;
+localparam DQDQS_DM_WIDTH               = MEM_DM_WIDTH / NUM_OF_DQDQS;
+localparam DQDQS_DDIO_PHY_DQ_WIDTH      = AFI_DATA_WIDTH / NUM_OF_DQDQS;
+
+reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
+
+//  Initialization of the sequencer status register. This register
+//  is preserved in the netlist so that it can be forced during simulation
+always @(posedge pll_afi_clk)
+    `ifndef SYNTH_FOR_SIM
+    `endif
+    seq_calib_init_reg <= SEQ_CALIB_INIT;
+    `ifndef SYNTH_FOR_SIM
+    `endif
+    `ifndef SYNTH_FOR_SIM
+    `endif
+
+//  ******************************************************************************************************************************** 
+//  Instantiate PHYCLK buffer for fitter 
+//  ******************************************************************************************************************************** 
+        fiftyfivenm_phy_clkbuf uphy_clkbuf(
+                .inclk ({pll_capture1_clk, pll_capture0_clk, pll_write_clk, pll_mem_clk}),
+                .outclk ({pll_capture1_clk_ddio, pll_capture0_clk_ddio, pll_write_clk_ddio, pll_mem_clk_ddio})
+        );
+
+//  ******************************************************************************************************************************** 
+//  The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
+//  The reset block has 2 main functionalities:
+//  1. Keep all the PHY logic in reset state until after the PLL is locked
+//  2. Synchronize the reset to each clock domain 
+//  ******************************************************************************************************************************** 
+
+
+    q_sys_ddr3_ram_p0_reset_m10    ureset(
+        .pll_afi_clk            (pll_afi_clk),
+        .pll_write_clk          (pll_write_clk),
+        .pll_locked             (pll_locked),
+        .global_reset_n         (global_reset_n),
+        .soft_reset_n           (soft_reset_n),
+        .ctl_reset_export_n     (ctl_reset_export_n),
+        .ctl_reset_n            (ctl_reset_n),
+        .reset_n_afi_clk        (reset_n_afi_clk),
+        .reset_n_resync_clk     (reset_n_resync_clk)
+    );
+
+    defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
+    defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
+
+assign calib_skip_steps = seq_calib_init_reg;
+assign afi_cal_debug_info = phy_cal_debug_info;
+
+assign phy_clk = pll_afi_clk;
+assign phy_reset_n = reset_n_afi_clk[0];
+
+
+//  ******************************************************************************************************************************** 
+//  The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
+//  interface and the output DDIOs.
+//  ******************************************************************************************************************************** 
+
+    q_sys_ddr3_ram_p0_addr_cmd_datapath    uaddr_cmd_datapath(
+        .clk                (pll_afi_clk), 
+        .reset_n            (reset_n_afi_clk[1]), 
+        .afi_address        (afi_addr),
+        .afi_cke            (afi_cke),
+        .afi_cs_n           (afi_cs_n),
+        .afi_bank           (afi_ba),
+        .afi_odt            (afi_odt),
+        .afi_ras_n          (afi_ras_n),
+        .afi_cas_n          (afi_cas_n),
+        .afi_we_n           (afi_we_n),
+        .phy_ddio_odt       (phy_ddio_odt),
+        .phy_ddio_bank      (phy_ddio_bank),
+        .phy_ddio_we_n      (phy_ddio_we_n),
+        .phy_ddio_ras_n     (phy_ddio_ras_n),
+        .phy_ddio_cas_n     (phy_ddio_cas_n),
+        .afi_rst_n          (afi_rst_n),
+        .phy_ddio_reset_n   (phy_ddio_reset_n),
+        .phy_ddio_address   (phy_ddio_address),
+        .phy_ddio_cke       (phy_ddio_cke),
+        .phy_ddio_cs_n      (phy_ddio_cs_n)
+    );
+        defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH                  = MEM_ADDRESS_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_BANK_WIDTH                     = MEM_BANK_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH              = MEM_CHIP_SELECT_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH                   = MEM_CLK_EN_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_ODT_WIDTH                      = MEM_ODT_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_DM_WIDTH                       = MEM_DM_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH                  = MEM_CONTROL_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_DQ_WIDTH                       = MEM_DQ_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH                 = MEM_READ_DQS_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH                = MEM_WRITE_DQS_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH                  = AFI_ADDRESS_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_BANK_WIDTH                     = AFI_BANK_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH              = AFI_CHIP_SELECT_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH                   = AFI_CLK_EN_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_ODT_WIDTH                      = AFI_ODT_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH                = AFI_DATA_MASK_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH                  = AFI_CONTROL_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_DATA_WIDTH                     = AFI_DATA_WIDTH;
+        defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS             = NUM_AC_FR_CYCLE_SHIFTS;    
+
+
+
+//  ******************************************************************************************************************************** 
+//  The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface 
+//  and the output DDIOs.
+//  ******************************************************************************************************************************** 
+
+    q_sys_ddr3_ram_p0_write_datapath_m10    uwrite_datapath(
+        .pll_afi_clk                   (pll_afi_clk),
+        .reset_n                       (reset_n_afi_clk[2]),
+        .afi_dqs_en                    (afi_dqs_burst),
+        .afi_wdata                     (afi_wdata),
+        .afi_wdata_valid               (afi_wdata_valid),
+        .afi_dm                        (afi_dm),
+        .phy_ddio_dq                   (phy_ddio_dq),
+        .phy_ddio_dqs_en               (phy_ddio_dqs_en),
+        .phy_ddio_wrdata_en            (phy_ddio_wrdata_en),
+        .phy_ddio_wrdata_mask          (phy_ddio_wrdata_mask)
+    );
+        defparam uwrite_datapath.MEM_ADDRESS_WIDTH                  = MEM_ADDRESS_WIDTH;
+        defparam uwrite_datapath.MEM_DM_WIDTH                       = MEM_DM_WIDTH;
+        defparam uwrite_datapath.MEM_CONTROL_WIDTH                  = MEM_CONTROL_WIDTH;
+        defparam uwrite_datapath.MEM_DQ_WIDTH                       = MEM_DQ_WIDTH;
+        defparam uwrite_datapath.MEM_READ_DQS_WIDTH                 = MEM_READ_DQS_WIDTH;
+        defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH                = MEM_WRITE_DQS_WIDTH;
+        defparam uwrite_datapath.AFI_ADDRESS_WIDTH                  = AFI_ADDRESS_WIDTH;
+        defparam uwrite_datapath.AFI_DATA_MASK_WIDTH                = AFI_DATA_MASK_WIDTH;
+        defparam uwrite_datapath.AFI_CONTROL_WIDTH                  = AFI_CONTROL_WIDTH;
+        defparam uwrite_datapath.AFI_DATA_WIDTH                     = AFI_DATA_WIDTH;
+        defparam uwrite_datapath.AFI_DQS_WIDTH                      = AFI_DQS_WIDTH;
+        defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES         = NUM_WRITE_PATH_FLOP_STAGES;
+        defparam uwrite_datapath.NUM_WRITE_FR_CYCLE_SHIFTS          = NUM_WRITE_FR_CYCLE_SHIFTS;
+
+     
+//  ******************************************************************************************************************************** 
+//  The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
+//  It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
+//  ******************************************************************************************************************************** 
+
+    q_sys_ddr3_ram_p0_read_datapath_m10    uread_datapath(
+        .reset_n_afi_clk            (reset_n_afi_clk[3]),
+        .pll_afi_clk                (pll_afi_clk),
+        .read_capture_clk_hr_dq     (read_capture_clk_hr_dq),
+        .rdata_hr                   (ddio_phy_dq),
+        .seq_read_increment_vfifo   (phy_read_increment_vfifo_hr),
+        .seq_read_fifo_reset        (phy_read_fifo_reset),
+        .seq_read_latency_counter   (phy_read_latency_counter),
+        .afi_rdata_en               (afi_rdata_en),
+        .afi_rdata                  (afi_rdata),
+        .afi_rdata_valid            (afi_rdata_valid)
+    );
+    defparam uread_datapath.DEVICE_FAMILY                          = DEVICE_FAMILY;
+    defparam uread_datapath.MEM_ADDRESS_WIDTH                      = MEM_ADDRESS_WIDTH; 
+    defparam uread_datapath.MEM_DM_WIDTH                           = MEM_DM_WIDTH; 
+    defparam uread_datapath.MEM_CONTROL_WIDTH                      = MEM_CONTROL_WIDTH; 
+    defparam uread_datapath.MEM_DQ_WIDTH                           = MEM_DQ_WIDTH; 
+    defparam uread_datapath.MEM_READ_DQS_WIDTH                     = MEM_READ_DQS_WIDTH; 
+    defparam uread_datapath.MEM_WRITE_DQS_WIDTH                    = MEM_WRITE_DQS_WIDTH; 
+    defparam uread_datapath.AFI_ADDRESS_WIDTH                      = AFI_ADDRESS_WIDTH; 
+    defparam uread_datapath.AFI_DATA_MASK_WIDTH                    = AFI_DATA_MASK_WIDTH; 
+    defparam uread_datapath.AFI_CONTROL_WIDTH                      = AFI_CONTROL_WIDTH; 
+    defparam uread_datapath.AFI_DATA_WIDTH                         = AFI_DATA_WIDTH; 
+    defparam uread_datapath.AFI_DQS_WIDTH                          = AFI_DQS_WIDTH;
+    defparam uread_datapath.AFI_RATE_RATIO                         = AFI_RATE_RATIO;
+    defparam uread_datapath.NUM_OF_DQDQS                           = NUM_OF_DQDQS;
+    defparam uread_datapath.DQDQS_DATA_WIDTH                       = DQDQS_DATA_WIDTH;
+    defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH                = MAX_LATENCY_COUNT_WIDTH;
+    defparam uread_datapath.MAX_READ_LATENCY                       = MAX_READ_LATENCY;
+    defparam uread_datapath.MEM_T_RL                               = MEM_T_RL;
+
+//  ******************************************************************************************************************************** 
+//  The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
+//  ******************************************************************************************************************************** 
+
+wire addr_cmd_clk;
+wire mimic_clock;
+
+        assign addr_cmd_clk = pll_mem_clk_ddio;
+        localparam INVERT_OUTPUT_CLOCK = "true";
+
+    q_sys_ddr3_ram_p0_addr_cmd_pads_m10 uaddr_cmd_pads(
+        .reset_n            (reset_n_afi_clk[3]),
+        .pll_afi_clk        (pll_afi_clk),
+        .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+        .pll_mem_clk        (pll_mem_clk),
+        .pll_write_clk      (addr_cmd_clk),
+        .enable_mem_clk     (~afi_mem_clk_disable),
+        .phy_ddio_address   (phy_ddio_address),
+        .phy_ddio_cs_n      (phy_ddio_cs_n),
+        .phy_ddio_cke       (phy_ddio_cke),
+        .phy_ddio_bank      (phy_ddio_bank),
+        .phy_ddio_odt       (phy_ddio_odt),
+        .phy_ddio_we_n      (phy_ddio_we_n),    
+        .phy_ddio_ras_n     (phy_ddio_ras_n),
+        .phy_ddio_cas_n     (phy_ddio_cas_n),
+        .phy_ddio_reset_n   (phy_ddio_reset_n),
+
+        .phy_mem_cs_n       (mem_cs_n),
+        .phy_mem_cke        (mem_cke),
+        .phy_mem_address    (mem_a),
+        .phy_mem_bank       (mem_ba),
+        .phy_mem_odt        (mem_odt),
+        .phy_mem_we_n       (mem_we_n),
+        .phy_mem_ras_n      (mem_ras_n),
+        .phy_mem_cas_n      (mem_cas_n),
+        .phy_mem_reset_n    (mem_reset_n),
+        .phy_mem_ck         (mem_ck),
+        .phy_mem_ck_n       (mem_ck_n),
+        .mimic_clock        (mimic_clock)
+    );
+    defparam uaddr_cmd_pads.DEVICE_FAMILY           = DEVICE_FAMILY;
+    defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH       = MEM_ADDRESS_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH   = MEM_CHIP_SELECT_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH        = MEM_CLK_EN_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH       = MEM_CONTROL_WIDTH;
+    defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH       = AFI_ADDRESS_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH   = AFI_CHIP_SELECT_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH        = AFI_CLK_EN_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH       = AFI_CONTROL_WIDTH; 
+    defparam uaddr_cmd_pads.INVERT_OUTPUT_CLOCK     = INVERT_OUTPUT_CLOCK;
+
+    defparam uaddr_cmd_pads.MEM_BANK_WIDTH          = MEM_BANK_WIDTH;
+    defparam uaddr_cmd_pads.MEM_ODT_WIDTH           = MEM_ODT_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CK_WIDTH            = MEM_CK_WIDTH;
+    defparam uaddr_cmd_pads.AFI_BANK_WIDTH          = AFI_BANK_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_ODT_WIDTH           = AFI_ODT_WIDTH; 
+
+        generate
+        if (INVERT_HR_CLOCK == 1)
+                assign invert_hr_clock = 1'b1;
+        else
+                assign invert_hr_clock = 1'b0;
+        endgenerate
+
+        generate
+    genvar i;
+    for (i=0; i<NUM_OF_DQDQS; i=i+1)
+    begin: dq_ddio
+        wire dqs_busout;
+
+        //  The phy_ddio_dq bus is the write data for all DQS groups in one
+        //  AFI cycle. The bus is ordered by time slot and subordered by DQS group:
+        // 
+        // FR: D1_T1, D0_T1, D1_T0, D0_T0
+        // HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
+        //
+        // Extract the write data targeting the current DQS group
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
+
+        // Extract the OE signal targeting the current DQS group
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t0 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i]}};
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t1 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i+NUM_OF_DQDQS]}};
+
+        // Extract the write data mask signal targeting the current DQS group
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
+        assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS)];
+
+        wire pll_capture_clk;
+        assign  pll_capture_clk = pll_capture0_clk_ddio;
+
+        q_sys_ddr3_ram_p0_dqdqs_pads_m10 ubidir_dq_dqs (
+            .reset_n_afi_clk        (reset_n_afi_clk[3]),
+            .pll_afi_clk            (pll_afi_clk),
+            .pll_mem_clk_ddio       (pll_mem_clk_ddio),
+            .pll_mem_clk            (pll_mem_clk),
+            .pll_write_clk          (pll_write_clk_ddio),
+            .enable_mem_clk         (~afi_mem_clk_disable),
+            .dq_capture_clk         (pll_capture_clk), // calibrated capture clock
+            .read_capture_clk_hr_dq (read_capture_clk_hr_dq[i]), // to read datapath
+            .invert_hr_clock        (invert_hr_clock),
+
+            .phy_mem_dq (mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
+            .mem_dqs                (mem_dqs[i]),
+            .mem_dqs_n              (mem_dqs_n[i]),
+
+            .extra_write_data_in    ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
+            .extra_write_data_out   (mem_dm[i]),
+
+            .rdata_hr               (ddio_phy_dq[(DQDQS_DDIO_PHY_DQ_WIDTH*(i+1)-1) : DQDQS_DDIO_PHY_DQ_WIDTH*i]),
+            .write_oe_in            ({phy_ddio_wrdata_en_t1, phy_ddio_wrdata_en_t0}),
+            .write_data_in          ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
+            .output_strobe_ena      ({phy_ddio_dqs_en[i+NUM_OF_DQDQS], phy_ddio_dqs_en[i]})
+        );
+        defparam ubidir_dq_dqs.MEM_CK_WIDTH            = MEM_CK_WIDTH;
+        
+    end
+    endgenerate
+    
+//  ******************************************************************************************************************************** 
+//  Instantiate phase detector
+//  ******************************************************************************************************************************** 
+    fiftyfivenm_phase_detector phase_detector_inst
+    (
+        .reset      (~pd_reset_n),
+        .phasedone  (pd_ack),
+        .clk        ({mimic_clock,pll_capture1_clk,pll_afi_clk}),
+        .up         (pd_up),
+        .down       (pd_down)
+    );
+
+// Calculate the ceiling of log_2 of the input value
+function integer ceil_log2;
+    input integer value;
+    begin
+        value = value - 1;
+        for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
+            value = value >> 1;
+    end
+endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv
new file mode 100644
index 0000000..631c98b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv
@@ -0,0 +1,187 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: read_datapath.sv
+// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
+// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+// altera message_off 10036 10030 10858
+module q_sys_ddr3_ram_p0_read_datapath_m10(
+    pll_afi_clk,
+    reset_n_afi_clk,
+    read_capture_clk_hr_dq,
+    rdata_hr,
+    afi_rdata_en,
+    afi_rdata,
+    afi_rdata_valid,
+    seq_read_fifo_reset,
+    seq_read_latency_counter,
+    seq_read_increment_vfifo
+);
+
+// ********************************************************************************************************************************
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
+
+parameter DEVICE_FAMILY = "";
+
+// PHY-Memory Interface
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+// PHY-Controller (AFI) Interface
+parameter AFI_ADDRESS_WIDTH         = "";
+parameter AFI_DATA_MASK_WIDTH       = "";
+parameter AFI_CONTROL_WIDTH         = "";
+parameter AFI_DATA_WIDTH            = "";
+parameter AFI_DQS_WIDTH             = "";
+parameter AFI_RATE_RATIO            = "";
+parameter NUM_OF_DQDQS              = "";
+parameter DQDQS_DATA_WIDTH          = "";
+parameter MAX_READ_LATENCY          = "";
+parameter MAX_LATENCY_COUNT_WIDTH   = "";
+parameter DEVICE_WIDTH              = 1;
+parameter MEM_T_RL                  = "";
+
+// Local parameters
+localparam DDIO_PHY_DQ_WIDTH = AFI_DATA_WIDTH/NUM_OF_DQDQS;
+
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+input                                       reset_n_afi_clk;
+input                                       pll_afi_clk;
+input           [AFI_DATA_WIDTH-1:0]        rdata_hr;
+
+input           [MEM_READ_DQS_WIDTH-1:0]    seq_read_fifo_reset; // reset from sequencer to read and write pointers of the data resynchronization FIFO
+input           [MEM_READ_DQS_WIDTH-1:0]    seq_read_increment_vfifo;
+input           [MAX_LATENCY_COUNT_WIDTH-1:0] seq_read_latency_counter;
+input           [MEM_READ_DQS_WIDTH-1:0]    read_capture_clk_hr_dq;
+
+
+input           [AFI_RATE_RATIO-1:0]        afi_rdata_en;
+
+output          [AFI_DATA_WIDTH-1:0]        afi_rdata;
+output          [AFI_RATE_RATIO-1:0]        afi_rdata_valid;
+
+logic           [AFI_DATA_WIDTH-1:0]        rdata_reorder;
+logic           [NUM_OF_DQDQS-1 : 0]        vfifo_output;
+
+reg             [MEM_READ_DQS_WIDTH-1:0]    read_enable_from_lfifo;
+wire            [MEM_READ_DQS_WIDTH-1:0]    rdata_fifo_full;
+wire            [MEM_READ_DQS_WIDTH-1:0]    lfifo_full;
+
+// VFIFO read increment per capture clock
+
+// VFIFO pointer
+
+logic [MAX_READ_LATENCY-1:0] vfifo;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_shifter
+        if (!reset_n_afi_clk)
+            vfifo <= 0;
+        else
+            vfifo <= {vfifo[MAX_READ_LATENCY-2:0], afi_rdata_en[0]};
+    end
+
+logic [2:0] vfifo_pointer;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_pointer_gen
+        if (!reset_n_afi_clk)
+            vfifo_pointer <= 0;
+        else if (seq_read_increment_vfifo[0])
+            vfifo_pointer <= vfifo_pointer + 1'b1;
+    end
+
+localparam VFIFO_OFFSET = MAX_READ_LATENCY - 8;
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_rden
+        if (!reset_n_afi_clk)
+            vfifo_output <= 0;
+        else
+            vfifo_output <= vfifo[vfifo_pointer+VFIFO_OFFSET];
+    end
+
+logic [3:0] reset_counter;
+logic	write_req;
+logic	read_req;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin
+        if (!reset_n_afi_clk)
+			begin
+				write_req	<=	0;
+				read_req		<=	0;
+				reset_counter	<=	'0;
+			end
+		else
+			begin
+				if (!(&reset_counter))
+					reset_counter	<=	reset_counter + 1'b1;
+				
+				if (reset_counter > 5)
+					write_req	<=	1;
+				
+				if (reset_counter > 9)
+					read_req		<=	1;
+			end
+	end
+
+// HR rdata clock cross into afi_clk domain
+
+wire [DDIO_PHY_DQ_WIDTH-1:0] read_fifo_output_per_dqs;
+
+    max10emif_dcfifo    rdata_fifo (
+                .data (rdata_hr),
+                .rdclk (pll_afi_clk),
+                .rdreq (read_req),
+                .wrclk (read_capture_clk_hr_dq[0]),
+                .wrreq (write_req),
+                .q (rdata_reorder),
+                .aclr (~reset_n_afi_clk));
+    defparam
+        rdata_fifo.numwords = 8,
+        rdata_fifo.width = AFI_DATA_WIDTH,
+        rdata_fifo.widthu = 3;
+
+// Read data reorder
+generate
+genvar i;
+for (i=0; i<NUM_OF_DQDQS; i=i+1)
+begin: rdata_per_dq_group
+
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+1)-1 : DQDQS_DATA_WIDTH*(i*4+0)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+2)-1 : DQDQS_DATA_WIDTH*(i*4+1)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+3)-1 : DQDQS_DATA_WIDTH*(i*4+2)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+4)-1 : DQDQS_DATA_WIDTH*(i*4+3)];
+
+end
+endgenerate
+
+assign afi_rdata_valid = {2{vfifo_output}};
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v
new file mode 100644
index 0000000..5c59132
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v
@@ -0,0 +1,89 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_read_valid_selector(
+	reset_n,
+	pll_afi_clk,
+	latency_shifter,
+	latency_counter,
+	read_enable,
+	read_valid
+);
+
+parameter MAX_LATENCY_COUNT_WIDTH	= "";
+
+localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
+
+input	reset_n;
+input	pll_afi_clk;
+input	[LATENCY_NUM-1:0] latency_shifter;
+input	[MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
+output	read_enable;
+output	read_valid;
+
+wire	[LATENCY_NUM-1:0] selector;
+reg [LATENCY_NUM-1:0] selector_reg;
+reg	read_enable;
+reg reading_data;
+reg	read_valid;
+
+wire	[LATENCY_NUM-1:0] valid_select;
+
+
+	lpm_decode	uvalid_select(
+        .data (latency_counter),
+        .eq (selector)
+        // synopsys translate_off
+        ,
+        .aclr (),
+        .clken (),
+        .clock (),
+        .enable ()
+        // synopsys translate_on
+	);
+
+	defparam uvalid_select.lpm_decodes = LATENCY_NUM;
+	defparam uvalid_select.lpm_type = "LPM_DECODE";
+	defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
+
+
+	always @(posedge pll_afi_clk or negedge reset_n)
+	begin
+		if (~reset_n)
+			selector_reg <= {LATENCY_NUM{1'b0}};
+		else
+			selector_reg <= selector;
+	end
+
+	assign valid_select = selector_reg & latency_shifter;
+
+
+    always @(posedge pll_afi_clk or negedge reset_n)
+    begin
+        if (~reset_n)
+        begin
+            read_enable <= 1'b0;
+            read_valid <= 1'b0;
+        end
+        else
+        begin
+            read_enable <= |valid_select;
+	
+            read_valid <= |valid_select;
+        end
+    end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v
new file mode 100644
index 0000000..0d05cc1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v
@@ -0,0 +1,82 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
+module q_sys_ddr3_ram_p0_reset_m10(
+	pll_afi_clk,
+	pll_write_clk,
+	pll_locked,
+	global_reset_n,
+	soft_reset_n,
+	ctl_reset_n,
+	ctl_reset_export_n,
+	reset_n_afi_clk,
+	reset_n_resync_clk
+);
+
+
+parameter MEM_READ_DQS_WIDTH = ""; 
+
+parameter NUM_AFI_RESET = 1;
+
+
+
+input	pll_afi_clk;
+input	pll_write_clk;
+input	pll_locked;
+input	global_reset_n;
+input	soft_reset_n;
+output	ctl_reset_n;
+output  ctl_reset_export_n;
+output	[NUM_AFI_RESET-1:0] reset_n_afi_clk;
+output	reset_n_resync_clk;
+// Apply the synthesis keep attribute on the synchronized reset wires
+// so that these names can be constrained using QSF settings to keep
+// the resets on local routing.
+wire	phy_reset_n /* synthesis keep = 1 */;
+wire	phy_reset_mem_stable_n /* synthesis keep = 1*/;
+
+wire	[MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
+
+        assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
+
+	q_sys_ddr3_ram_p0_reset_sync	ureset_afi_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_afi_clk),
+		.reset_n_sync	(reset_n_afi_clk)
+	);
+	defparam ureset_afi_clk.RESET_SYNC_STAGES = 15; 
+	defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
+
+	q_sys_ddr3_ram_p0_reset_sync	ureset_ctl_reset_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_afi_clk),
+		.reset_n_sync	({ctl_reset_n, ctl_reset_export_n})
+	);
+	defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
+	defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
+
+
+	q_sys_ddr3_ram_p0_reset_sync	ureset_resync_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_write_clk),
+		.reset_n_sync	(reset_n_resync_clk)
+	);
+	defparam ureset_resync_clk.RESET_SYNC_STAGES = 15; 
+	defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v
new file mode 100644
index 0000000..d37a5c7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v
@@ -0,0 +1,62 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_reset_sync(
+	reset_n,
+	clk,
+	reset_n_sync
+);
+
+parameter RESET_SYNC_STAGES = 4;
+parameter NUM_RESET_OUTPUT = 1;
+
+input	reset_n;
+input	clk;
+output	[NUM_RESET_OUTPUT-1:0] reset_n_sync;
+
+
+
+
+// identify the synchronizer chain so that Quartus can analyze metastability.
+// Since these resets are localized to the PHY alone, make them routed locally
+// to avoid using global networks.
+(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg	[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
+
+generate
+genvar i;
+	for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
+	begin: reset_stage
+		always @(posedge clk or negedge reset_n)
+		begin
+			if (~reset_n)
+				reset_reg[i] <= 1'b0;
+			else
+			begin
+				if (i==0)
+					reset_reg[i] <= 1'b1;
+				else if (i < RESET_SYNC_STAGES)
+					reset_reg[i] <= reset_reg[i-1];
+				else
+					reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
+				
+			end
+		end
+	end
+endgenerate
+
+	assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv
new file mode 100644
index 0000000..7d9bdf8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv
@@ -0,0 +1,94 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// *****************************************************************
+// File name: simple_ddio_out_m10.sv
+//
+// This module can be used to double the data rate of the datain*
+// bus. Outputs at the dataout. 
+//
+// Example 1:
+//
+// datain_rise = T1 at clk cycle x of hr_clk, where each Ty is a data item
+// datain_fall = T0 at clk cycle x of hr_clk, where each Ty is a data item
+// with width DATA_WIDTH
+//
+//
+// dataout = {T0} at positive phase of clk cycle x clocked by fr_clk
+// dataout = {T1} at negative phase of clk cycle x clocked by fr_clk
+//
+// *****************************************************************
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_ddr3_ram_p0_simple_ddio_out_m10(
+	hr_clk,
+	fr_clk,
+	datain_rise,
+        datain_fall,
+        muxsel,
+	dataout
+);
+
+// *****************************************************************
+// BEGIN PARAMETER SECTION
+
+parameter DATA_WIDTH = ""; 
+
+// END PARAMETER SECTION
+// *****************************************************************
+
+input	hr_clk;
+input   fr_clk;
+input	[DATA_WIDTH-1:0] datain_rise;
+input   [DATA_WIDTH-1:0] datain_fall;
+input   muxsel;
+output	[DATA_WIDTH-1:0] dataout;
+
+generate
+genvar i, j;
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [DATA_WIDTH-1:0] datain_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [DATA_WIDTH-1:0] datain_f /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+
+
+        always_ff @ (posedge hr_clk )
+	begin
+		datain_r <= datain_rise;
+	end
+
+        always_ff @ (negedge hr_clk)
+        begin
+                datain_f <= datain_fall;
+        end
+
+
+	reg [DATA_WIDTH-1:0] dataout_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+	for (i=0; i<DATA_WIDTH; i=i+1)
+	begin: ddio_group
+
+                always_ff @ (posedge fr_clk)
+                begin
+                        if (muxsel)
+                        begin
+			        dataout_r[i] <= datain_f;
+                        end else begin
+                                dataout_r[i] <= datain_r;
+                        end
+		end
+	end
+	
+	assign dataout = dataout_r;
+	
+endgenerate
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v
new file mode 100644
index 0000000..094eac1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v
@@ -0,0 +1,195 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ***************************************************************************
+// File name: write_datapath.v
+// ***************************************************************************
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+module q_sys_ddr3_ram_p0_write_datapath_m10(
+	pll_afi_clk,
+	reset_n,
+	afi_dqs_en,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_dm,
+	phy_ddio_dq,
+	phy_ddio_dqs_en,
+	phy_ddio_wrdata_en,
+	phy_ddio_wrdata_mask
+);
+
+
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+parameter AFI_ADDRESS_WIDTH     = "";
+parameter AFI_DATA_MASK_WIDTH   = "";
+parameter AFI_CONTROL_WIDTH     = "";
+parameter AFI_DATA_WIDTH        = "";
+parameter AFI_DQS_WIDTH	        = "";
+
+parameter NUM_WRITE_PATH_FLOP_STAGES = "";
+parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
+
+localparam RATE_MULT = 2;
+localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
+
+localparam DM_GROUP_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
+
+
+input	pll_afi_clk;
+input	reset_n;
+input	[AFI_DQS_WIDTH-1:0] afi_dqs_en;
+input	[AFI_DATA_WIDTH-1:0] afi_wdata;
+input	[AFI_DQS_WIDTH-1:0] afi_wdata_valid;
+input	[AFI_DATA_MASK_WIDTH-1:0] afi_dm;
+output	[AFI_DATA_WIDTH-1:0] phy_ddio_dq;
+output	[AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
+output	[AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
+output	[AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
+
+wire	[AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
+wire	[AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
+wire	[AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
+wire	[AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
+
+generate
+genvar stage;
+if (NUM_WRITE_PATH_FLOP_STAGES == 0)
+begin
+	assign phy_ddio_dq_pre_shift = afi_wdata;
+	assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
+	assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
+        assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
+end
+else
+begin
+        reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
+        reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        
+        // phy_ddio_wrdata_mask is tied low during calibration
+        // the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
+        // sclr pin is very slow and causes timing failures
+        (* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        
+        for (stage = 0; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
+        begin : stage_gen
+        	always @(posedge pll_afi_clk)
+        	begin
+        		afi_wdata_r[stage]       <= (stage == 0) ? afi_wdata       : afi_wdata_r[stage-1];
+        		afi_wdata_valid_r[stage] <= (stage == 0) ? afi_wdata_valid : afi_wdata_valid_r[stage-1];
+        		afi_dm_r[stage]          <= (stage == 0) ? afi_dm          : afi_dm_r[stage-1];
+        		afi_dqs_en_r[stage]      <= (stage == 0) ? afi_dqs_en      : afi_dqs_en_r[stage-1];
+        	end
+        end
+        
+        assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+end
+endgenerate
+
+generate
+genvar i, t;
+for (i=0; i<MEM_WRITE_DQS_WIDTH; i=i+1)
+begin: bs_wr_grp
+	
+	wire [1:0] shift_fr_cycle = 
+		(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 	2'b00 : 2'b01;
+											
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en_pre_shift;
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en;
+	
+	wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq_pre_shift;
+	wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq;
+	
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en_pre_shift;
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en;
+
+	wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask_pre_shift;
+	wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask;
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter dq_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_dq_pre_shift),
+		.dataout (grp_dq)	
+	);
+	defparam dq_shifter.DATA_WIDTH = (DQ_GROUP_WIDTH * 2);
+	
+	q_sys_ddr3_ram_p0_fr_cycle_shifter wrdata_mask_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_wrdata_mask_pre_shift),
+		.dataout (grp_wrdata_mask)
+	);
+	defparam wrdata_mask_shifter.DATA_WIDTH = (DM_GROUP_WIDTH * 2);
+	
+	q_sys_ddr3_ram_p0_fr_cycle_shifter wrdata_en_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_wrdata_en_pre_shift),
+		.dataout (grp_wrdata_en)
+	);
+	defparam wrdata_en_shifter.DATA_WIDTH = 1;
+
+	q_sys_ddr3_ram_p0_fr_cycle_shifter dqs_en_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_dqs_en_pre_shift),
+		.dataout (grp_dqs_en)
+	);
+	defparam dqs_en_shifter.DATA_WIDTH = 1;
+
+	for (t=0; t<RATE_MULT*2; t=t+1)
+	begin: extract_ddr_grp
+		wire [DQ_GROUP_WIDTH-1:0] dq_t_pre_shift = phy_ddio_dq_pre_shift[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t];
+		assign grp_dq_pre_shift[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH] = dq_t_pre_shift;
+		
+		wire [DQ_GROUP_WIDTH-1:0] dq_t = grp_dq[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH];
+		assign phy_ddio_dq[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t] = dq_t;
+
+		wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t_pre_shift = phy_ddio_wrdata_mask_pre_shift[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t];
+		assign grp_wrdata_mask_pre_shift[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH] = wrdata_mask_t_pre_shift;
+		
+		wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t = grp_wrdata_mask[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH];
+		assign phy_ddio_wrdata_mask[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t] = wrdata_mask_t;		
+	end
+	
+	for (t=0; t<RATE_MULT; t=t+1)
+	begin: extract_sdr_grp
+		assign grp_dqs_en_pre_shift[t] = phy_ddio_dqs_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
+		assign phy_ddio_dqs_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_dqs_en[t];
+		
+		assign grp_wrdata_en_pre_shift[t] = phy_ddio_wrdata_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
+		assign phy_ddio_wrdata_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_wrdata_en[t];
+		
+	end
+end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv
new file mode 100644
index 0000000..2dedb43
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv
@@ -0,0 +1,223 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// This file instantiates the PLL.
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name IP_TOOL_NAME common; -name IP_TOOL_VERSION 19.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+module q_sys_ddr3_ram_pll0 (
+	global_reset_n,
+	pll_ref_clk,
+	pll_locked,
+	
+	afi_clk,
+	afi_half_clk,
+	pll_mem_clk,
+	pll_write_clk,
+	pll_capture0_clk,
+	pll_capture1_clk,
+	
+	scanclk,
+	phasecounterselect,
+	phasestep,
+	phaseupdown,
+	phasedone
+);
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver. 
+parameter DEVICE_FAMILY = "MAX 10";
+
+// Clock settings
+parameter REF_CLK_PERIOD_PS = 10000;
+
+parameter PLL_AFI_CLK_DIV           = 2;
+parameter PLL_MEM_CLK_DIV           = 1;
+parameter PLL_WRITE_CLK_DIV         = 1;
+parameter PLL_CAP0_CLK_DIV          = 1;
+parameter PLL_CAP1_CLK_DIV          = 1;
+
+parameter PLL_AFI_CLK_MULT          = 3;
+parameter PLL_MEM_CLK_MULT          = 3;
+parameter PLL_WRITE_CLK_MULT        = 3;
+parameter PLL_CAP0_CLK_MULT         = 3;
+parameter PLL_CAP1_CLK_MULT         = 3;
+
+parameter PLL_AFI_CLK_PHASE_PS      = "0";
+parameter PLL_MEM_CLK_PHASE_PS      = "0";
+parameter PLL_WRITE_CLK_PHASE_PS    = "2500";
+parameter PLL_CAP0_CLK_PHASE_PS     = "0";
+parameter PLL_CAP1_CLK_PHASE_PS     = "2500";
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+// ******************************************************************************************************************************** 
+// BEGIN PORT SECTION
+
+input   global_reset_n;		// Resets (active-low) the whole system (all PHY logic + PLL)
+input	pll_ref_clk;		// PLL reference clock
+output	pll_locked;    // When 0, PLL is out of lock
+
+// When the PHY is selected to be a PLL/DLL MASTER, the PLL and DLL are instantied on this top level
+output  afi_clk;		// See pll_memphy instantiation below for detailed description of each clock
+output  afi_half_clk; 
+output	pll_mem_clk;
+output	pll_write_clk;
+output	pll_capture0_clk;
+output	pll_capture1_clk;
+
+input	[2:0] phasecounterselect;
+input	phasestep;
+input	phaseupdown;
+output	phasedone;
+input	scanclk;
+
+assign afi_half_clk = 1'b0;
+
+// END PORT SECTION
+// ******************************************************************************************************************************** 
+
+    wire [4:0] sub_wire;
+	wire  afi_clk         = sub_wire[4];
+	wire  pll_mem_clk         = sub_wire[0];
+	wire  pll_write_clk       = sub_wire[1];
+	wire  pll_capture0_clk    = sub_wire[2];
+	wire  pll_capture1_clk    = sub_wire[3];
+
+	altpll	upll_memphy (
+				.areset (~global_reset_n),
+				.inclk ({1'h0, pll_ref_clk}),
+				.phasecounterselect (phasecounterselect),
+				.phasestep (phasestep),
+				.scanclk (scanclk),
+				.phaseupdown (phaseupdown),
+				.clk (sub_wire),
+				.locked (pll_locked),
+				.phasedone (phasedone),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		upll_memphy.bandwidth_type = "AUTO",
+		
+		upll_memphy.clk4_divide_by = PLL_AFI_CLK_DIV,
+		upll_memphy.clk4_duty_cycle = 50,
+		upll_memphy.clk4_multiply_by = PLL_AFI_CLK_MULT,
+		upll_memphy.clk4_phase_shift = PLL_AFI_CLK_PHASE_PS,
+		
+		upll_memphy.clk0_divide_by = PLL_MEM_CLK_DIV,
+		upll_memphy.clk0_duty_cycle = 50,
+		upll_memphy.clk0_multiply_by = PLL_MEM_CLK_MULT,
+		upll_memphy.clk0_phase_shift = PLL_MEM_CLK_PHASE_PS,
+		
+		upll_memphy.clk1_divide_by = PLL_WRITE_CLK_DIV,
+		upll_memphy.clk1_duty_cycle = 50,
+		upll_memphy.clk1_multiply_by = PLL_WRITE_CLK_MULT,
+		upll_memphy.clk1_phase_shift = PLL_WRITE_CLK_PHASE_PS,
+		
+		upll_memphy.clk2_divide_by = PLL_CAP0_CLK_DIV,
+		upll_memphy.clk2_duty_cycle = 50,
+		upll_memphy.clk2_multiply_by = PLL_CAP0_CLK_MULT,
+		upll_memphy.clk2_phase_shift = PLL_CAP0_CLK_PHASE_PS,
+		
+		upll_memphy.clk3_divide_by = PLL_CAP1_CLK_DIV,
+		upll_memphy.clk3_duty_cycle = 50,
+		upll_memphy.clk3_multiply_by = PLL_CAP1_CLK_MULT,
+		upll_memphy.clk3_phase_shift = PLL_CAP1_CLK_PHASE_PS,
+		
+		upll_memphy.compensate_clock = "CLK1",
+		upll_memphy.inclk0_input_frequency = REF_CLK_PERIOD_PS,
+		upll_memphy.intended_device_family = DEVICE_FAMILY,
+		upll_memphy.lpm_type = "altpll",
+		upll_memphy.operation_mode = "NORMAL",
+		upll_memphy.pll_type = "AUTO",
+		upll_memphy.port_activeclock = "PORT_UNUSED",
+		upll_memphy.port_areset = "PORT_USED",
+		upll_memphy.port_clkbad0 = "PORT_UNUSED",
+		upll_memphy.port_clkbad1 = "PORT_UNUSED",
+		upll_memphy.port_clkloss = "PORT_UNUSED",
+		upll_memphy.port_clkswitch = "PORT_UNUSED",
+		upll_memphy.port_configupdate = "PORT_UNUSED",
+		upll_memphy.port_fbin = "PORT_UNUSED",
+		upll_memphy.port_inclk0 = "PORT_USED",
+		upll_memphy.port_inclk1 = "PORT_UNUSED",
+		upll_memphy.port_locked = "PORT_USED",
+		upll_memphy.port_pfdena = "PORT_UNUSED",
+		upll_memphy.port_phasecounterselect = "PORT_USED",
+		upll_memphy.port_phasedone = "PORT_USED",
+		upll_memphy.port_phasestep = "PORT_USED",
+		upll_memphy.port_phaseupdown = "PORT_USED",
+		upll_memphy.port_pllena = "PORT_UNUSED",
+		upll_memphy.port_scanaclr = "PORT_UNUSED",
+		upll_memphy.port_scanclk = "PORT_USED",
+		upll_memphy.port_scanclkena = "PORT_UNUSED",
+		upll_memphy.port_scandata = "PORT_UNUSED",
+		upll_memphy.port_scandataout = "PORT_UNUSED",
+		upll_memphy.port_scandone = "PORT_UNUSED",
+		upll_memphy.port_scanread = "PORT_UNUSED",
+		upll_memphy.port_scanwrite = "PORT_UNUSED",
+		upll_memphy.port_clk0 = "PORT_USED",
+		upll_memphy.port_clk1 = "PORT_USED",
+		upll_memphy.port_clk2 = "PORT_USED",
+		upll_memphy.port_clk3 = "PORT_USED",
+		upll_memphy.port_clk4 = "PORT_USED",
+		upll_memphy.port_clk5 = "PORT_UNUSED",
+		upll_memphy.port_clkena0 = "PORT_UNUSED",
+		upll_memphy.port_clkena1 = "PORT_UNUSED",
+		upll_memphy.port_clkena2 = "PORT_UNUSED",
+		upll_memphy.port_clkena3 = "PORT_UNUSED",
+		upll_memphy.port_clkena4 = "PORT_UNUSED",
+		upll_memphy.port_clkena5 = "PORT_UNUSED",
+		upll_memphy.port_extclk0 = "PORT_UNUSED",
+		upll_memphy.port_extclk1 = "PORT_UNUSED",
+		upll_memphy.port_extclk2 = "PORT_UNUSED",
+		upll_memphy.port_extclk3 = "PORT_UNUSED",
+		upll_memphy.self_reset_on_loss_lock = "OFF",
+		upll_memphy.vco_frequency_control = "MANUAL_PHASE",
+		upll_memphy.vco_phase_shift_step = 104,
+		upll_memphy.width_clock = 5,
+		upll_memphy.width_phasecounterselect = 3;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v
new file mode 100644
index 0000000..b1b6a6b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0.v
@@ -0,0 +1,289 @@
+// q_sys_ddr3_ram_s0.v
+
+// This file was auto-generated from qsys_sequencer_110_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ddr3_ram_s0 (
+		input  wire        avl_clk,                     //          avl_clk.clk
+		input  wire        avl_reset_n,                 //    sequencer_rst.reset
+		output wire        pd_reset_n,                  //   phase_detector.pd_reset_n
+		output wire        pd_ack,                      //                 .pd_ack
+		input  wire        pd_up,                       //                 .pd_up
+		input  wire        pd_down,                     //                 .pd_down
+		output wire [2:0]  phasecounterselect,          //     pll_reconfig.phasecounterselect
+		output wire        phasestep,                   //                 .phasestep
+		output wire        phaseupdown,                 //                 .phaseupdown
+		output wire        scanclk,                     //                 .scanclk
+		input  wire        phasedone,                   //                 .phasedone
+		input  wire        phy_clk,                     //              phy.phy_clk
+		input  wire        phy_reset_n,                 //                 .phy_reset_n
+		output wire [4:0]  phy_read_latency_counter,    //                 .phy_read_latency_counter
+		output wire [5:0]  phy_afi_wlat,                //                 .phy_afi_wlat
+		output wire [5:0]  phy_afi_rlat,                //                 .phy_afi_rlat
+		output wire [0:0]  phy_read_increment_vfifo_fr, //                 .phy_read_increment_vfifo_fr
+		output wire [0:0]  phy_read_increment_vfifo_hr, //                 .phy_read_increment_vfifo_hr
+		output wire [0:0]  phy_read_increment_vfifo_qr, //                 .phy_read_increment_vfifo_qr
+		output wire        phy_reset_mem_stable,        //                 .phy_reset_mem_stable
+		output wire        phy_cal_success,             //                 .phy_cal_success
+		output wire        phy_cal_fail,                //                 .phy_cal_fail
+		output wire [31:0] phy_cal_debug_info,          //                 .phy_cal_debug_info
+		output wire [0:0]  phy_read_fifo_reset,         //                 .phy_read_fifo_reset
+		output wire [0:0]  phy_vfifo_rd_en_override,    //                 .phy_vfifo_rd_en_override
+		input  wire [31:0] phy_read_fifo_q,             //                 .phy_read_fifo_q
+		output wire [1:0]  phy_write_fr_cycle_shifts,   //                 .phy_write_fr_cycle_shifts
+		output wire        phy_mux_sel,                 //          mux_sel.mux_sel
+		input  wire [7:0]  calib_skip_steps,            //            calib.calib_skip_steps
+		input  wire        afi_clk,                     //          afi_clk.clk
+		input  wire        afi_reset_n,                 //        afi_reset.reset_n
+		output wire [27:0] afi_addr,                    //              afi.afi_addr
+		output wire [5:0]  afi_ba,                      //                 .afi_ba
+		output wire [1:0]  afi_cs_n,                    //                 .afi_cs_n
+		output wire [1:0]  afi_cke,                     //                 .afi_cke
+		output wire [1:0]  afi_odt,                     //                 .afi_odt
+		output wire [1:0]  afi_ras_n,                   //                 .afi_ras_n
+		output wire [1:0]  afi_cas_n,                   //                 .afi_cas_n
+		output wire [1:0]  afi_we_n,                    //                 .afi_we_n
+		output wire [1:0]  afi_dqs_burst,               //                 .afi_dqs_burst
+		output wire [1:0]  afi_rst_n,                   //                 .afi_rst_n
+		output wire [31:0] afi_wdata,                   //                 .afi_wdata
+		output wire [1:0]  afi_wdata_valid,             //                 .afi_wdata_valid
+		output wire [3:0]  afi_dm,                      //                 .afi_dm
+		output wire [1:0]  afi_rdata_en,                //                 .afi_rdata_en
+		output wire [1:0]  afi_rdata_en_full,           //                 .afi_rdata_en_full
+		input  wire [31:0] afi_rdata,                   //                 .afi_rdata
+		input  wire [1:0]  afi_rdata_valid,             //                 .afi_rdata_valid
+		input  wire        afi_init_req,                // afi_init_cal_req.afi_init_req
+		input  wire        afi_cal_req                  //                 .afi_cal_req
+	);
+
+	wire         sequencer_rst_reset_out_reset;                            // sequencer_rst:reset_out -> [cpu_inst:reset_n, mm_interconnect_0:cpu_inst_reset_n_reset_bridge_in_reset_reset, mm_interconnect_0:sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_pll_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst:avl_reset_n]
+	wire  [31:0] cpu_inst_data_master_readdata;                            // mm_interconnect_0:cpu_inst_data_master_readdata -> cpu_inst:readdata
+	wire         cpu_inst_data_master_waitrequest;                         // mm_interconnect_0:cpu_inst_data_master_waitrequest -> cpu_inst:waitrequest
+	wire  [19:0] cpu_inst_data_master_address;                             // cpu_inst:address -> mm_interconnect_0:cpu_inst_data_master_address
+	wire         cpu_inst_data_master_read;                                // cpu_inst:read -> mm_interconnect_0:cpu_inst_data_master_read
+	wire         cpu_inst_data_master_write;                               // cpu_inst:write -> mm_interconnect_0:cpu_inst_data_master_write
+	wire  [31:0] cpu_inst_data_master_writedata;                           // cpu_inst:writedata -> mm_interconnect_0:cpu_inst_data_master_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata;    // sequencer_phy_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_address;     // mm_interconnect_0:sequencer_phy_mgr_inst_avl_address -> sequencer_phy_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_read;        // mm_interconnect_0:sequencer_phy_mgr_inst_avl_read -> sequencer_phy_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_write;       // mm_interconnect_0:sequencer_phy_mgr_inst_avl_write -> sequencer_phy_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata;   // mm_interconnect_0:sequencer_phy_mgr_inst_avl_writedata -> sequencer_phy_mgr_inst:avl_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata;     // sequencer_rw_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest;  // sequencer_rw_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_address;      // mm_interconnect_0:sequencer_rw_mgr_inst_avl_address -> sequencer_rw_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_read;         // mm_interconnect_0:sequencer_rw_mgr_inst_avl_read -> sequencer_rw_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_write;        // mm_interconnect_0:sequencer_rw_mgr_inst_avl_write -> sequencer_rw_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata;    // mm_interconnect_0:sequencer_rw_mgr_inst_avl_writedata -> sequencer_rw_mgr_inst:avl_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata;    // sequencer_pll_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest; // sequencer_pll_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_address;     // mm_interconnect_0:sequencer_pll_mgr_inst_avl_address -> sequencer_pll_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_read;        // mm_interconnect_0:sequencer_pll_mgr_inst_avl_read -> sequencer_pll_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_write;       // mm_interconnect_0:sequencer_pll_mgr_inst_avl_write -> sequencer_pll_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata;   // mm_interconnect_0:sequencer_pll_mgr_inst_avl_writedata -> sequencer_pll_mgr_inst:avl_writedata
+
+	altera_mem_if_sequencer_rst #(
+		.DEPTH            (10),
+		.CLKEN_LAGS_RESET (0)
+	) sequencer_rst (
+		.clk       (avl_clk),                       //       clk.clk
+		.rst       (avl_reset_n),                   //       rst.reset
+		.reset_out (sequencer_rst_reset_out_reset), // reset_out.reset
+		.clken_out ()                               // clken_out.clken
+	);
+
+	sequencer_m10 #(
+		.AVL_DATA_WIDTH       (32),
+		.AVL_ADDR_WIDTH       (20),
+		.READ_VALID_FIFO_SIZE (16),
+		.HPS_PROTOCOL         ("DDR3"),
+		.PHY_MGR_BASE         (294912),
+		.RW_MGR_BASE          (327680),
+		.PLL_MGR_BASE         (360448),
+		.MEM_DQ_WIDTH         (8)
+	) cpu_inst (
+		.clk         (avl_clk),                          //            clk.clk
+		.reset_n     (~sequencer_rst_reset_out_reset),   //        reset_n.reset_n
+		.address     (cpu_inst_data_master_address),     //    data_master.address
+		.write       (cpu_inst_data_master_write),       //               .write
+		.writedata   (cpu_inst_data_master_writedata),   //               .writedata
+		.read        (cpu_inst_data_master_read),        //               .read
+		.readdata    (cpu_inst_data_master_readdata),    //               .readdata
+		.waitrequest (cpu_inst_data_master_waitrequest), //               .waitrequest
+		.pd_reset_n  (pd_reset_n),                       // phase_detector.pd_reset_n
+		.pd_ack      (pd_ack),                           //               .pd_ack
+		.pd_up       (pd_up),                            //               .pd_up
+		.pd_down     (pd_down)                           //               .pd_down
+	);
+
+	sequencer_pll_mgr #(
+		.AVL_DATA_WIDTH (32),
+		.AVL_ADDR_WIDTH (13)
+	) sequencer_pll_mgr_inst (
+		.avl_clk            (avl_clk),                                                  //          avl_clk.clk
+		.avl_reset_n        (~sequencer_rst_reset_out_reset),                           //        avl_reset.reset_n
+		.avl_address        (mm_interconnect_0_sequencer_pll_mgr_inst_avl_address),     //              avl.address
+		.avl_write          (mm_interconnect_0_sequencer_pll_mgr_inst_avl_write),       //                 .write
+		.avl_writedata      (mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata),   //                 .writedata
+		.avl_read           (mm_interconnect_0_sequencer_pll_mgr_inst_avl_read),        //                 .read
+		.avl_readdata       (mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata),    //                 .readdata
+		.avl_waitrequest    (mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest), //                 .waitrequest
+		.phasecounterselect (phasecounterselect),                                       //     pll_reconfig.phasecounterselect
+		.phasestep          (phasestep),                                                //                 .phasestep
+		.phaseupdown        (phaseupdown),                                              //                 .phaseupdown
+		.scanclk            (scanclk),                                                  //                 .scanclk
+		.phasedone          (phasedone),                                                //                 .phasedone
+		.afi_init_req       (afi_init_req),                                             // afi_init_cal_req.afi_init_req
+		.afi_cal_req        (afi_cal_req)                                               //                 .afi_cal_req
+	);
+
+	sequencer_phy_mgr #(
+		.AVL_DATA_WIDTH                    (32),
+		.AVL_ADDR_WIDTH                    (13),
+		.MAX_LATENCY_COUNT_WIDTH           (5),
+		.MEM_IF_READ_DQS_WIDTH             (1),
+		.MEM_IF_WRITE_DQS_WIDTH            (1),
+		.AFI_DQ_WIDTH                      (32),
+		.AFI_DEBUG_INFO_WIDTH              (32),
+		.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
+		.AFI_MAX_READ_LATENCY_COUNT_WIDTH  (6),
+		.CALIB_VFIFO_OFFSET                (12),
+		.CALIB_LFIFO_OFFSET                (4),
+		.CALIB_REG_WIDTH                   (8),
+		.READ_VALID_FIFO_SIZE              (16),
+		.MEM_T_WL                          (5),
+		.MEM_T_RL                          (5),
+		.CTL_REGDIMM_ENABLED               (0),
+		.NUM_WRITE_FR_CYCLE_SHIFTS         (1),
+		.VFIFO_CONTROL_WIDTH_PER_DQS       (1),
+		.DEVICE_FAMILY                     ("MAX10")
+	) sequencer_phy_mgr_inst (
+		.avl_clk                     (avl_clk),                                                  //   avl_clk.clk
+		.avl_reset_n                 (~sequencer_rst_reset_out_reset),                           // avl_reset.reset_n
+		.avl_address                 (mm_interconnect_0_sequencer_phy_mgr_inst_avl_address),     //       avl.address
+		.avl_write                   (mm_interconnect_0_sequencer_phy_mgr_inst_avl_write),       //          .write
+		.avl_writedata               (mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata),   //          .writedata
+		.avl_read                    (mm_interconnect_0_sequencer_phy_mgr_inst_avl_read),        //          .read
+		.avl_readdata                (mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata),    //          .readdata
+		.avl_waitrequest             (mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest), //          .waitrequest
+		.phy_clk                     (phy_clk),                                                  //       phy.phy_clk
+		.phy_reset_n                 (phy_reset_n),                                              //          .phy_reset_n
+		.phy_read_latency_counter    (phy_read_latency_counter),                                 //          .phy_read_latency_counter
+		.phy_afi_wlat                (phy_afi_wlat),                                             //          .phy_afi_wlat
+		.phy_afi_rlat                (phy_afi_rlat),                                             //          .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr),                              //          .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr),                              //          .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr),                              //          .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (phy_reset_mem_stable),                                     //          .phy_reset_mem_stable
+		.phy_cal_success             (phy_cal_success),                                          //          .phy_cal_success
+		.phy_cal_fail                (phy_cal_fail),                                             //          .phy_cal_fail
+		.phy_cal_debug_info          (phy_cal_debug_info),                                       //          .phy_cal_debug_info
+		.phy_read_fifo_reset         (phy_read_fifo_reset),                                      //          .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (phy_vfifo_rd_en_override),                                 //          .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (phy_read_fifo_q),                                          //          .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (phy_write_fr_cycle_shifts),                                //          .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (calib_skip_steps),                                         //     calib.calib_skip_steps
+		.phy_mux_sel                 (phy_mux_sel)                                               //   mux_sel.mux_sel
+	);
+
+	rw_manager_ddr3 #(
+		.RATE                                 ("Half"),
+		.AVL_DATA_WIDTH                       (32),
+		.AVL_ADDR_WIDTH                       (13),
+		.MEM_ADDRESS_WIDTH                    (14),
+		.MEM_CONTROL_WIDTH                    (1),
+		.MEM_DQ_WIDTH                         (8),
+		.MEM_DM_WIDTH                         (1),
+		.MEM_NUMBER_OF_RANKS                  (1),
+		.MEM_CLK_EN_WIDTH                     (1),
+		.MEM_BANK_WIDTH                       (3),
+		.MEM_ODT_WIDTH                        (1),
+		.MEM_CHIP_SELECT_WIDTH                (1),
+		.MEM_READ_DQS_WIDTH                   (1),
+		.MEM_WRITE_DQS_WIDTH                  (1),
+		.AFI_RATIO                            (2),
+		.AC_BUS_WIDTH                         (27),
+		.HCX_COMPAT_MODE                      (0),
+		.DEVICE_FAMILY                        ("MAX10"),
+		.AC_ROM_INIT_FILE_NAME                ("q_sys_ddr3_ram_s0_AC_ROM.hex"),
+		.INST_ROM_INIT_FILE_NAME              ("q_sys_ddr3_ram_s0_inst_ROM.hex"),
+		.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT (0),
+		.DEBUG_WRITE_TO_READ_RATIO            (1),
+		.MAX_DI_BUFFER_WORDS_LOG_2            (2),
+		.AP_MODE_EN                           (2'b00),
+		.AVL_CLK_PS                           (6667),
+		.AFI_CLK_PS                           (6667),
+		.ENABLE_NON_DES_CAL                   (0),
+		.TREFI                                (35100),
+		.REFRESH_INTERVAL                     (15000),
+		.TRFC                                 (350)
+	) sequencer_rw_mgr_inst (
+		.avl_clk           (avl_clk),                                                 //   avl_clk.clk
+		.avl_reset_n       (~sequencer_rst_reset_out_reset),                          // avl_reset.reset_n
+		.avl_address       (mm_interconnect_0_sequencer_rw_mgr_inst_avl_address),     //       avl.address
+		.avl_write         (mm_interconnect_0_sequencer_rw_mgr_inst_avl_write),       //          .write
+		.avl_writedata     (mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata),   //          .writedata
+		.avl_read          (mm_interconnect_0_sequencer_rw_mgr_inst_avl_read),        //          .read
+		.avl_readdata      (mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata),    //          .readdata
+		.avl_waitrequest   (mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest), //          .waitrequest
+		.afi_clk           (afi_clk),                                                 //   afi_clk.clk
+		.afi_reset_n       (afi_reset_n),                                             // afi_reset.reset_n
+		.afi_addr          (afi_addr),                                                //       afi.afi_addr
+		.afi_ba            (afi_ba),                                                  //          .afi_ba
+		.afi_cs_n          (afi_cs_n),                                                //          .afi_cs_n
+		.afi_cke           (afi_cke),                                                 //          .afi_cke
+		.afi_odt           (afi_odt),                                                 //          .afi_odt
+		.afi_ras_n         (afi_ras_n),                                               //          .afi_ras_n
+		.afi_cas_n         (afi_cas_n),                                               //          .afi_cas_n
+		.afi_we_n          (afi_we_n),                                                //          .afi_we_n
+		.afi_dqs_burst     (afi_dqs_burst),                                           //          .afi_dqs_burst
+		.afi_rst_n         (afi_rst_n),                                               //          .afi_rst_n
+		.afi_wdata         (afi_wdata),                                               //          .afi_wdata
+		.afi_wdata_valid   (afi_wdata_valid),                                         //          .afi_wdata_valid
+		.afi_dm            (afi_dm),                                                  //          .afi_dm
+		.afi_rdata_en      (afi_rdata_en),                                            //          .afi_rdata_en
+		.afi_rdata_en_full (afi_rdata_en_full),                                       //          .afi_rdata_en_full
+		.afi_rdata         (afi_rdata),                                               //          .afi_rdata
+		.afi_rdata_valid   (afi_rdata_valid),                                         //          .afi_rdata_valid
+		.csr_clk           (),                                                        //       csr.csr_clk
+		.csr_ena           (),                                                        //          .csr_ena
+		.csr_dout_phy      (),                                                        //          .csr_dout_phy
+		.csr_dout          (),                                                        //          .csr_dout
+		.afi_rrank         (),                                                        // (terminated)
+		.afi_wrank         ()                                                         // (terminated)
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0 mm_interconnect_0 (
+		.avl_clk_out_clk_clk                                          (avl_clk),                                                  //                                        avl_clk_out_clk.clk
+		.cpu_inst_reset_n_reset_bridge_in_reset_reset                 (sequencer_rst_reset_out_reset),                            //                 cpu_inst_reset_n_reset_bridge_in_reset.reset
+		.sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset),                            // sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
+		.cpu_inst_data_master_address                                 (cpu_inst_data_master_address),                             //                                   cpu_inst_data_master.address
+		.cpu_inst_data_master_waitrequest                             (cpu_inst_data_master_waitrequest),                         //                                                       .waitrequest
+		.cpu_inst_data_master_read                                    (cpu_inst_data_master_read),                                //                                                       .read
+		.cpu_inst_data_master_readdata                                (cpu_inst_data_master_readdata),                            //                                                       .readdata
+		.cpu_inst_data_master_write                                   (cpu_inst_data_master_write),                               //                                                       .write
+		.cpu_inst_data_master_writedata                               (cpu_inst_data_master_writedata),                           //                                                       .writedata
+		.sequencer_phy_mgr_inst_avl_address                           (mm_interconnect_0_sequencer_phy_mgr_inst_avl_address),     //                             sequencer_phy_mgr_inst_avl.address
+		.sequencer_phy_mgr_inst_avl_write                             (mm_interconnect_0_sequencer_phy_mgr_inst_avl_write),       //                                                       .write
+		.sequencer_phy_mgr_inst_avl_read                              (mm_interconnect_0_sequencer_phy_mgr_inst_avl_read),        //                                                       .read
+		.sequencer_phy_mgr_inst_avl_readdata                          (mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata),    //                                                       .readdata
+		.sequencer_phy_mgr_inst_avl_writedata                         (mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata),   //                                                       .writedata
+		.sequencer_phy_mgr_inst_avl_waitrequest                       (mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest), //                                                       .waitrequest
+		.sequencer_pll_mgr_inst_avl_address                           (mm_interconnect_0_sequencer_pll_mgr_inst_avl_address),     //                             sequencer_pll_mgr_inst_avl.address
+		.sequencer_pll_mgr_inst_avl_write                             (mm_interconnect_0_sequencer_pll_mgr_inst_avl_write),       //                                                       .write
+		.sequencer_pll_mgr_inst_avl_read                              (mm_interconnect_0_sequencer_pll_mgr_inst_avl_read),        //                                                       .read
+		.sequencer_pll_mgr_inst_avl_readdata                          (mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata),    //                                                       .readdata
+		.sequencer_pll_mgr_inst_avl_writedata                         (mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata),   //                                                       .writedata
+		.sequencer_pll_mgr_inst_avl_waitrequest                       (mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest), //                                                       .waitrequest
+		.sequencer_rw_mgr_inst_avl_address                            (mm_interconnect_0_sequencer_rw_mgr_inst_avl_address),      //                              sequencer_rw_mgr_inst_avl.address
+		.sequencer_rw_mgr_inst_avl_write                              (mm_interconnect_0_sequencer_rw_mgr_inst_avl_write),        //                                                       .write
+		.sequencer_rw_mgr_inst_avl_read                               (mm_interconnect_0_sequencer_rw_mgr_inst_avl_read),         //                                                       .read
+		.sequencer_rw_mgr_inst_avl_readdata                           (mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata),     //                                                       .readdata
+		.sequencer_rw_mgr_inst_avl_writedata                          (mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata),    //                                                       .writedata
+		.sequencer_rw_mgr_inst_avl_waitrequest                        (mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest)   //                                                       .waitrequest
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex
new file mode 100644
index 0000000..0c6be75
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_AC_ROM.hex
@@ -0,0 +1,41 @@
+:04000000180E0000D6
+:04000100180F0000D4
+:040002000C010211DA
+:040003000C010310D9
+:040004000C012000CB
+:040005000C014000AA
+:040006000C01600089
+:040007000C070400DE
+:040008000C010209DC
+:040009000C0102885C
+:04000A000C014000A5
+:04000B000C012000C4
+:04000C000C01600083
+:04000D001C0F0000C4
+:04000E001E0F0000C1
+:04000F001C0F0000C2
+:040010000C0D0000D3
+:040011000C0D600072
+:040012000C050400D5
+:040013000C090000D4
+:040014000F330000A6
+:040015000F33600045
+:040016000F3300089C
+:040017000F3360083B
+:040018001E2F000097
+:040019001F3F000085
+:04001A001E0F0000B5
+:04001B000E030000D0
+:04001C000E230000AF
+:04001D000CCB000008
+:04001E000CCB6000A7
+:04001F000CCB0008FE
+:040020000CCB60089D
+:040021001CCF0000F0
+:040022000C0B0008BB
+:040023000C0F0000BE
+:0400240000000000D8
+:0400250000000000D7
+:0400260000000000D6
+:0400270000000000D5
+:00000001FF
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex
new file mode 100644
index 0000000..3b53998
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_inst_ROM.hex
@@ -0,0 +1,129 @@
+:03000000080000F5
+:0300010000078075
+:030002000806806D
+:0300030000018079
+:030004000806806B
+:03000500000200F6
+:0300060008068069
+:0300070000028074
+:0300080008068067
+:03000900000300F1
+:03000A0008068065
+:03000B000003806F
+:03000C0008068063
+:03000D00000100EF
+:03000E0008068061
+:03000F00000800E6
+:03001000008680E7
+:0300110000088064
+:0300120000A680C5
+:030013000806805C
+:03001400000900E0
+:030015000806805A
+:030016000009805E
+:03001700008680E0
+:0300180008068057
+:03001900000B6871
+:03001A0000CCE82F
+:03001B00000AE8F0
+:03001C00008CE86D
+:03001D00000B884D
+:03001E0000EC886B
+:03001F00000A08CC
+:0300200000AC88A9
+:030021000806804E
+:0300220000CE000D
+:0300230000CD808D
+:0300240000E700F2
+:03002500000C00CC
+:03002600020CE0E9
+:03002700020CE0E8
+:03002800000D00C8
+:030029000006804E
+:03002A000006804D
+:03002B00060E803E
+:03002C000610803B
+:03002D0000A680AA
+:03002E00008680C9
+:03002F0008068040
+:0300300000CE00FF
+:0300310000CD807F
+:0300320000E700E4
+:03003300000C00BE
+:03003400030CE0DA
+:03003500030CE0D9
+:03003600000D00BA
+:0300370000068040
+:030038000006803F
+:03003900070E802F
+:03003A000710802C
+:03003B0000A6809C
+:03003C00008680BB
+:03003D0008068032
+:03003E0000115856
+:03003F000006D8E0
+:030040000806802F
+:03004100040E8822
+:030042000410881F
+:03004300040F683F
+:030044000410E8BD
+:0300450000A68092
+:03004600040FE8BC
+:030047000410E8BA
+:0300480004100899
+:0300490004108818
+:03004A00001100A2
+:03004B0000C6806C
+:03004C00008680AB
+:03004D0000E6804A
+:03004E0008068021
+:03004F00000000AE
+:03005000000000AD
+:0300510000A0000C
+:030052000080002B
+:03005300080000A2
+:0300540000008029
+:0300550000008028
+:0300560000008027
+:0300570000008026
+:0300580000A08085
+:03005900008080A4
+:03005A000800801B
+:03005B000086809C
+:03005C0000A6807B
+:03005D0008068012
+:03005E00040F0884
+:03005F0008068010
+:030060000000009D
+:030061000000009C
+:030062000000009B
+:030063000000009A
+:0300640000000099
+:0300650000000098
+:0300660000000097
+:0300670000000096
+:0300680000000095
+:0300690000000094
+:03006A0000000093
+:03006B0000000092
+:03006C0000000091
+:03006D0000000090
+:03006E000000008F
+:03006F000000008E
+:030070000000008D
+:030071000000008C
+:030072000000008B
+:030073000000008A
+:0300740000000089
+:0300750000000088
+:0300760000000087
+:0300770000000086
+:0300780000000085
+:0300790000000084
+:03007A0000000083
+:03007B0000000082
+:03007C0000000081
+:03007D0000000080
+:03007E000000007F
+:03007F000000007E
+:00000001FF
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v
new file mode 100644
index 0000000..aa1a3cc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0.v
@@ -0,0 +1,1258 @@
+// q_sys_ddr3_ram_s0_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ddr3_ram_s0_mm_interconnect_0 (
+		input  wire        avl_clk_out_clk_clk,                                          //                                        avl_clk_out_clk.clk
+		input  wire        cpu_inst_reset_n_reset_bridge_in_reset_reset,                 //                 cpu_inst_reset_n_reset_bridge_in_reset.reset
+		input  wire        sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, // sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
+		input  wire [19:0] cpu_inst_data_master_address,                                 //                                   cpu_inst_data_master.address
+		output wire        cpu_inst_data_master_waitrequest,                             //                                                       .waitrequest
+		input  wire        cpu_inst_data_master_read,                                    //                                                       .read
+		output wire [31:0] cpu_inst_data_master_readdata,                                //                                                       .readdata
+		input  wire        cpu_inst_data_master_write,                                   //                                                       .write
+		input  wire [31:0] cpu_inst_data_master_writedata,                               //                                                       .writedata
+		output wire [12:0] sequencer_phy_mgr_inst_avl_address,                           //                             sequencer_phy_mgr_inst_avl.address
+		output wire        sequencer_phy_mgr_inst_avl_write,                             //                                                       .write
+		output wire        sequencer_phy_mgr_inst_avl_read,                              //                                                       .read
+		input  wire [31:0] sequencer_phy_mgr_inst_avl_readdata,                          //                                                       .readdata
+		output wire [31:0] sequencer_phy_mgr_inst_avl_writedata,                         //                                                       .writedata
+		input  wire        sequencer_phy_mgr_inst_avl_waitrequest,                       //                                                       .waitrequest
+		output wire [12:0] sequencer_pll_mgr_inst_avl_address,                           //                             sequencer_pll_mgr_inst_avl.address
+		output wire        sequencer_pll_mgr_inst_avl_write,                             //                                                       .write
+		output wire        sequencer_pll_mgr_inst_avl_read,                              //                                                       .read
+		input  wire [31:0] sequencer_pll_mgr_inst_avl_readdata,                          //                                                       .readdata
+		output wire [31:0] sequencer_pll_mgr_inst_avl_writedata,                         //                                                       .writedata
+		input  wire        sequencer_pll_mgr_inst_avl_waitrequest,                       //                                                       .waitrequest
+		output wire [12:0] sequencer_rw_mgr_inst_avl_address,                            //                              sequencer_rw_mgr_inst_avl.address
+		output wire        sequencer_rw_mgr_inst_avl_write,                              //                                                       .write
+		output wire        sequencer_rw_mgr_inst_avl_read,                               //                                                       .read
+		input  wire [31:0] sequencer_rw_mgr_inst_avl_readdata,                           //                                                       .readdata
+		output wire [31:0] sequencer_rw_mgr_inst_avl_writedata,                          //                                                       .writedata
+		input  wire        sequencer_rw_mgr_inst_avl_waitrequest                         //                                                       .waitrequest
+	);
+
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest;   // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
+	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata;      // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess;   // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
+	wire  [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address;       // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_read;          // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
+	wire   [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable;    // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_lock;          // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_write;         // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
+	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata;     // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
+	wire   [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount;    // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
+	wire         rsp_mux_src_valid;                                                       // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
+	wire  [91:0] rsp_mux_src_data;                                                        // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
+	wire         rsp_mux_src_ready;                                                       // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
+	wire   [2:0] rsp_mux_src_channel;                                                     // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
+	wire         rsp_mux_src_startofpacket;                                               // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
+	wire         rsp_mux_src_endofpacket;                                                 // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
+	wire  [31:0] sequencer_phy_mgr_inst_avl_agent_m0_readdata;                            // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_waitrequest;                         // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_debugaccess;                         // sequencer_phy_mgr_inst_avl_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_phy_mgr_inst_avl_agent_m0_address;                             // sequencer_phy_mgr_inst_avl_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_phy_mgr_inst_avl_agent_m0_byteenable;                          // sequencer_phy_mgr_inst_avl_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_read;                                // sequencer_phy_mgr_inst_avl_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid;                       // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_lock;                                // sequencer_phy_mgr_inst_avl_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_phy_mgr_inst_avl_agent_m0_writedata;                           // sequencer_phy_mgr_inst_avl_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_write;                               // sequencer_phy_mgr_inst_avl_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_phy_mgr_inst_avl_agent_m0_burstcount;                          // sequencer_phy_mgr_inst_avl_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_valid;                        // sequencer_phy_mgr_inst_avl_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_phy_mgr_inst_avl_agent_rf_source_data;                         // sequencer_phy_mgr_inst_avl_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_ready;                        // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket;                // sequencer_phy_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket;                  // sequencer_phy_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid;                     // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data;                      // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready;                     // sequencer_phy_mgr_inst_avl_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;             // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;               // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_src_valid;                                                       // cmd_mux:src_valid -> sequencer_phy_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_src_data;                                                        // cmd_mux:src_data -> sequencer_phy_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_src_ready;                                                       // sequencer_phy_mgr_inst_avl_agent:cp_ready -> cmd_mux:src_ready
+	wire   [2:0] cmd_mux_src_channel;                                                     // cmd_mux:src_channel -> sequencer_phy_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_src_startofpacket;                                               // cmd_mux:src_startofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_src_endofpacket;                                                 // cmd_mux:src_endofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_endofpacket
+	wire  [31:0] sequencer_rw_mgr_inst_avl_agent_m0_readdata;                             // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_waitrequest;                          // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_debugaccess;                          // sequencer_rw_mgr_inst_avl_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_rw_mgr_inst_avl_agent_m0_address;                              // sequencer_rw_mgr_inst_avl_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_rw_mgr_inst_avl_agent_m0_byteenable;                           // sequencer_rw_mgr_inst_avl_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_read;                                 // sequencer_rw_mgr_inst_avl_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid;                        // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_lock;                                 // sequencer_rw_mgr_inst_avl_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_rw_mgr_inst_avl_agent_m0_writedata;                            // sequencer_rw_mgr_inst_avl_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_write;                                // sequencer_rw_mgr_inst_avl_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_rw_mgr_inst_avl_agent_m0_burstcount;                           // sequencer_rw_mgr_inst_avl_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_valid;                         // sequencer_rw_mgr_inst_avl_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_rw_mgr_inst_avl_agent_rf_source_data;                          // sequencer_rw_mgr_inst_avl_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_ready;                         // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket;                 // sequencer_rw_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket;                   // sequencer_rw_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid;                      // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data;                       // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready;                      // sequencer_rw_mgr_inst_avl_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;              // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;                // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_001_src_valid;                                                   // cmd_mux_001:src_valid -> sequencer_rw_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_001_src_data;                                                    // cmd_mux_001:src_data -> sequencer_rw_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_001_src_ready;                                                   // sequencer_rw_mgr_inst_avl_agent:cp_ready -> cmd_mux_001:src_ready
+	wire   [2:0] cmd_mux_001_src_channel;                                                 // cmd_mux_001:src_channel -> sequencer_rw_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_001_src_startofpacket;                                           // cmd_mux_001:src_startofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_001_src_endofpacket;                                             // cmd_mux_001:src_endofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_endofpacket
+	wire  [31:0] sequencer_pll_mgr_inst_avl_agent_m0_readdata;                            // sequencer_pll_mgr_inst_avl_translator:uav_readdata -> sequencer_pll_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_waitrequest;                         // sequencer_pll_mgr_inst_avl_translator:uav_waitrequest -> sequencer_pll_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_debugaccess;                         // sequencer_pll_mgr_inst_avl_agent:m0_debugaccess -> sequencer_pll_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_pll_mgr_inst_avl_agent_m0_address;                             // sequencer_pll_mgr_inst_avl_agent:m0_address -> sequencer_pll_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_pll_mgr_inst_avl_agent_m0_byteenable;                          // sequencer_pll_mgr_inst_avl_agent:m0_byteenable -> sequencer_pll_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_read;                                // sequencer_pll_mgr_inst_avl_agent:m0_read -> sequencer_pll_mgr_inst_avl_translator:uav_read
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid;                       // sequencer_pll_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_pll_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_lock;                                // sequencer_pll_mgr_inst_avl_agent:m0_lock -> sequencer_pll_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_pll_mgr_inst_avl_agent_m0_writedata;                           // sequencer_pll_mgr_inst_avl_agent:m0_writedata -> sequencer_pll_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_write;                               // sequencer_pll_mgr_inst_avl_agent:m0_write -> sequencer_pll_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_pll_mgr_inst_avl_agent_m0_burstcount;                          // sequencer_pll_mgr_inst_avl_agent:m0_burstcount -> sequencer_pll_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_valid;                        // sequencer_pll_mgr_inst_avl_agent:rf_source_valid -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_pll_mgr_inst_avl_agent_rf_source_data;                         // sequencer_pll_mgr_inst_avl_agent:rf_source_data -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_ready;                        // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_pll_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket;                // sequencer_pll_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket;                  // sequencer_pll_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid;                     // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_pll_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data;                      // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_pll_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready;                     // sequencer_pll_mgr_inst_avl_agent:rf_sink_ready -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;             // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;               // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_002_src_valid;                                                   // cmd_mux_002:src_valid -> sequencer_pll_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_002_src_data;                                                    // cmd_mux_002:src_data -> sequencer_pll_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_002_src_ready;                                                   // sequencer_pll_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready
+	wire   [2:0] cmd_mux_002_src_channel;                                                 // cmd_mux_002:src_channel -> sequencer_pll_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_002_src_startofpacket;                                           // cmd_mux_002:src_startofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_002_src_endofpacket;                                             // cmd_mux_002:src_endofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_endofpacket
+	wire         cpu_inst_data_master_agent_cp_valid;                                     // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
+	wire  [91:0] cpu_inst_data_master_agent_cp_data;                                      // cpu_inst_data_master_agent:cp_data -> router:sink_data
+	wire         cpu_inst_data_master_agent_cp_ready;                                     // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
+	wire         cpu_inst_data_master_agent_cp_startofpacket;                             // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
+	wire         cpu_inst_data_master_agent_cp_endofpacket;                               // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
+	wire         router_src_valid;                                                        // router:src_valid -> cmd_demux:sink_valid
+	wire  [91:0] router_src_data;                                                         // router:src_data -> cmd_demux:sink_data
+	wire         router_src_ready;                                                        // cmd_demux:sink_ready -> router:src_ready
+	wire   [2:0] router_src_channel;                                                      // router:src_channel -> cmd_demux:sink_channel
+	wire         router_src_startofpacket;                                                // router:src_startofpacket -> cmd_demux:sink_startofpacket
+	wire         router_src_endofpacket;                                                  // router:src_endofpacket -> cmd_demux:sink_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_valid;                               // sequencer_phy_mgr_inst_avl_agent:rp_valid -> router_001:sink_valid
+	wire  [91:0] sequencer_phy_mgr_inst_avl_agent_rp_data;                                // sequencer_phy_mgr_inst_avl_agent:rp_data -> router_001:sink_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_ready;                               // router_001:sink_ready -> sequencer_phy_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_startofpacket;                       // sequencer_phy_mgr_inst_avl_agent:rp_startofpacket -> router_001:sink_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_endofpacket;                         // sequencer_phy_mgr_inst_avl_agent:rp_endofpacket -> router_001:sink_endofpacket
+	wire         router_001_src_valid;                                                    // router_001:src_valid -> rsp_demux:sink_valid
+	wire  [91:0] router_001_src_data;                                                     // router_001:src_data -> rsp_demux:sink_data
+	wire         router_001_src_ready;                                                    // rsp_demux:sink_ready -> router_001:src_ready
+	wire   [2:0] router_001_src_channel;                                                  // router_001:src_channel -> rsp_demux:sink_channel
+	wire         router_001_src_startofpacket;                                            // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
+	wire         router_001_src_endofpacket;                                              // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_valid;                                // sequencer_rw_mgr_inst_avl_agent:rp_valid -> router_002:sink_valid
+	wire  [91:0] sequencer_rw_mgr_inst_avl_agent_rp_data;                                 // sequencer_rw_mgr_inst_avl_agent:rp_data -> router_002:sink_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_ready;                                // router_002:sink_ready -> sequencer_rw_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_startofpacket;                        // sequencer_rw_mgr_inst_avl_agent:rp_startofpacket -> router_002:sink_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_endofpacket;                          // sequencer_rw_mgr_inst_avl_agent:rp_endofpacket -> router_002:sink_endofpacket
+	wire         router_002_src_valid;                                                    // router_002:src_valid -> rsp_demux_001:sink_valid
+	wire  [91:0] router_002_src_data;                                                     // router_002:src_data -> rsp_demux_001:sink_data
+	wire         router_002_src_ready;                                                    // rsp_demux_001:sink_ready -> router_002:src_ready
+	wire   [2:0] router_002_src_channel;                                                  // router_002:src_channel -> rsp_demux_001:sink_channel
+	wire         router_002_src_startofpacket;                                            // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
+	wire         router_002_src_endofpacket;                                              // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_valid;                               // sequencer_pll_mgr_inst_avl_agent:rp_valid -> router_003:sink_valid
+	wire  [91:0] sequencer_pll_mgr_inst_avl_agent_rp_data;                                // sequencer_pll_mgr_inst_avl_agent:rp_data -> router_003:sink_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_ready;                               // router_003:sink_ready -> sequencer_pll_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_startofpacket;                       // sequencer_pll_mgr_inst_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_endofpacket;                         // sequencer_pll_mgr_inst_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
+	wire         router_003_src_valid;                                                    // router_003:src_valid -> rsp_demux_002:sink_valid
+	wire  [91:0] router_003_src_data;                                                     // router_003:src_data -> rsp_demux_002:sink_data
+	wire         router_003_src_ready;                                                    // rsp_demux_002:sink_ready -> router_003:src_ready
+	wire   [2:0] router_003_src_channel;                                                  // router_003:src_channel -> rsp_demux_002:sink_channel
+	wire         router_003_src_startofpacket;                                            // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
+	wire         router_003_src_endofpacket;                                              // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
+	wire         cmd_demux_src0_valid;                                                    // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+	wire  [91:0] cmd_demux_src0_data;                                                     // cmd_demux:src0_data -> cmd_mux:sink0_data
+	wire         cmd_demux_src0_ready;                                                    // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+	wire   [2:0] cmd_demux_src0_channel;                                                  // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+	wire         cmd_demux_src0_startofpacket;                                            // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+	wire         cmd_demux_src0_endofpacket;                                              // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+	wire         cmd_demux_src1_valid;                                                    // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
+	wire  [91:0] cmd_demux_src1_data;                                                     // cmd_demux:src1_data -> cmd_mux_001:sink0_data
+	wire         cmd_demux_src1_ready;                                                    // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
+	wire   [2:0] cmd_demux_src1_channel;                                                  // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
+	wire         cmd_demux_src1_startofpacket;                                            // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
+	wire         cmd_demux_src1_endofpacket;                                              // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
+	wire         cmd_demux_src2_valid;                                                    // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
+	wire  [91:0] cmd_demux_src2_data;                                                     // cmd_demux:src2_data -> cmd_mux_002:sink0_data
+	wire         cmd_demux_src2_ready;                                                    // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
+	wire   [2:0] cmd_demux_src2_channel;                                                  // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
+	wire         cmd_demux_src2_startofpacket;                                            // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
+	wire         cmd_demux_src2_endofpacket;                                              // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
+	wire         rsp_demux_src0_valid;                                                    // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+	wire  [91:0] rsp_demux_src0_data;                                                     // rsp_demux:src0_data -> rsp_mux:sink0_data
+	wire         rsp_demux_src0_ready;                                                    // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+	wire   [2:0] rsp_demux_src0_channel;                                                  // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+	wire         rsp_demux_src0_startofpacket;                                            // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+	wire         rsp_demux_src0_endofpacket;                                              // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+	wire         rsp_demux_001_src0_valid;                                                // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
+	wire  [91:0] rsp_demux_001_src0_data;                                                 // rsp_demux_001:src0_data -> rsp_mux:sink1_data
+	wire         rsp_demux_001_src0_ready;                                                // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
+	wire   [2:0] rsp_demux_001_src0_channel;                                              // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
+	wire         rsp_demux_001_src0_startofpacket;                                        // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
+	wire         rsp_demux_001_src0_endofpacket;                                          // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
+	wire         rsp_demux_002_src0_valid;                                                // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
+	wire  [91:0] rsp_demux_002_src0_data;                                                 // rsp_demux_002:src0_data -> rsp_mux:sink2_data
+	wire         rsp_demux_002_src0_ready;                                                // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
+	wire   [2:0] rsp_demux_002_src0_channel;                                              // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
+	wire         rsp_demux_002_src0_startofpacket;                                        // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
+	wire         rsp_demux_002_src0_endofpacket;                                          // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid;                   // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
+	wire  [33:0] sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data;                    // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready;                   // avalon_st_adapter:in_0_ready -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_out_0_valid;                                           // avalon_st_adapter:out_0_valid -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_out_0_data;                                            // avalon_st_adapter:out_0_data -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_out_0_ready;                                           // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+	wire   [0:0] avalon_st_adapter_out_0_error;                                           // avalon_st_adapter:out_0_error -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_error
+	wire         sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid;                    // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
+	wire  [33:0] sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data;                     // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready;                    // avalon_st_adapter_001:in_0_ready -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_001_out_0_valid;                                       // avalon_st_adapter_001:out_0_valid -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_001_out_0_data;                                        // avalon_st_adapter_001:out_0_data -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_001_out_0_ready;                                       // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire   [0:0] avalon_st_adapter_001_out_0_error;                                       // avalon_st_adapter_001:out_0_error -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_error
+	wire         sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid;                   // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
+	wire  [33:0] sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data;                    // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready;                   // avalon_st_adapter_002:in_0_ready -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_002_out_0_valid;                                       // avalon_st_adapter_002:out_0_valid -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_002_out_0_data;                                        // avalon_st_adapter_002:out_0_data -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_002_out_0_ready;                                       // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
+	wire   [0:0] avalon_st_adapter_002_out_0_error;                                       // avalon_st_adapter_002:out_0_error -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_error
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (20),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (20),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) cpu_inst_data_master_translator (
+		.clk                    (avl_clk_out_clk_clk),                                                     //                       clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset),            //                     reset.reset
+		.uav_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (cpu_inst_data_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (cpu_inst_data_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (cpu_inst_data_master_read),                                               //                          .read
+		.av_readdata            (cpu_inst_data_master_readdata),                                           //                          .readdata
+		.av_write               (cpu_inst_data_master_write),                                              //                          .write
+		.av_writedata           (cpu_inst_data_master_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                    //               (terminated)
+		.av_byteenable          (4'b1111),                                                                 //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                    //               (terminated)
+		.av_begintransfer       (1'b0),                                                                    //               (terminated)
+		.av_chipselect          (1'b0),                                                                    //               (terminated)
+		.av_readdatavalid       (),                                                                        //               (terminated)
+		.av_lock                (1'b0),                                                                    //               (terminated)
+		.av_debugaccess         (1'b0),                                                                    //               (terminated)
+		.uav_clken              (),                                                                        //               (terminated)
+		.av_clken               (1'b1),                                                                    //               (terminated)
+		.uav_response           (2'b00),                                                                   //               (terminated)
+		.av_response            (),                                                                        //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                    //               (terminated)
+		.av_writeresponsevalid  ()                                                                         //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_phy_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_phy_mgr_inst_avl_agent_m0_address),                  // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_phy_mgr_inst_avl_agent_m0_burstcount),               //                         .burstcount
+		.uav_read               (sequencer_phy_mgr_inst_avl_agent_m0_read),                     //                         .read
+		.uav_write              (sequencer_phy_mgr_inst_avl_agent_m0_write),                    //                         .write
+		.uav_waitrequest        (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest),              //                         .waitrequest
+		.uav_readdatavalid      (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid),            //                         .readdatavalid
+		.uav_byteenable         (sequencer_phy_mgr_inst_avl_agent_m0_byteenable),               //                         .byteenable
+		.uav_readdata           (sequencer_phy_mgr_inst_avl_agent_m0_readdata),                 //                         .readdata
+		.uav_writedata          (sequencer_phy_mgr_inst_avl_agent_m0_writedata),                //                         .writedata
+		.uav_lock               (sequencer_phy_mgr_inst_avl_agent_m0_lock),                     //                         .lock
+		.uav_debugaccess        (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess),              //                         .debugaccess
+		.av_address             (sequencer_phy_mgr_inst_avl_address),                           //      avalon_anti_slave_0.address
+		.av_write               (sequencer_phy_mgr_inst_avl_write),                             //                         .write
+		.av_read                (sequencer_phy_mgr_inst_avl_read),                              //                         .read
+		.av_readdata            (sequencer_phy_mgr_inst_avl_readdata),                          //                         .readdata
+		.av_writedata           (sequencer_phy_mgr_inst_avl_writedata),                         //                         .writedata
+		.av_waitrequest         (sequencer_phy_mgr_inst_avl_waitrequest),                       //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_rw_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_rw_mgr_inst_avl_agent_m0_address),                   // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_rw_mgr_inst_avl_agent_m0_burstcount),                //                         .burstcount
+		.uav_read               (sequencer_rw_mgr_inst_avl_agent_m0_read),                      //                         .read
+		.uav_write              (sequencer_rw_mgr_inst_avl_agent_m0_write),                     //                         .write
+		.uav_waitrequest        (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest),               //                         .waitrequest
+		.uav_readdatavalid      (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid),             //                         .readdatavalid
+		.uav_byteenable         (sequencer_rw_mgr_inst_avl_agent_m0_byteenable),                //                         .byteenable
+		.uav_readdata           (sequencer_rw_mgr_inst_avl_agent_m0_readdata),                  //                         .readdata
+		.uav_writedata          (sequencer_rw_mgr_inst_avl_agent_m0_writedata),                 //                         .writedata
+		.uav_lock               (sequencer_rw_mgr_inst_avl_agent_m0_lock),                      //                         .lock
+		.uav_debugaccess        (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess),               //                         .debugaccess
+		.av_address             (sequencer_rw_mgr_inst_avl_address),                            //      avalon_anti_slave_0.address
+		.av_write               (sequencer_rw_mgr_inst_avl_write),                              //                         .write
+		.av_read                (sequencer_rw_mgr_inst_avl_read),                               //                         .read
+		.av_readdata            (sequencer_rw_mgr_inst_avl_readdata),                           //                         .readdata
+		.av_writedata           (sequencer_rw_mgr_inst_avl_writedata),                          //                         .writedata
+		.av_waitrequest         (sequencer_rw_mgr_inst_avl_waitrequest),                        //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_pll_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_pll_mgr_inst_avl_agent_m0_address),                  // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_pll_mgr_inst_avl_agent_m0_burstcount),               //                         .burstcount
+		.uav_read               (sequencer_pll_mgr_inst_avl_agent_m0_read),                     //                         .read
+		.uav_write              (sequencer_pll_mgr_inst_avl_agent_m0_write),                    //                         .write
+		.uav_waitrequest        (sequencer_pll_mgr_inst_avl_agent_m0_waitrequest),              //                         .waitrequest
+		.uav_readdatavalid      (sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid),            //                         .readdatavalid
+		.uav_byteenable         (sequencer_pll_mgr_inst_avl_agent_m0_byteenable),               //                         .byteenable
+		.uav_readdata           (sequencer_pll_mgr_inst_avl_agent_m0_readdata),                 //                         .readdata
+		.uav_writedata          (sequencer_pll_mgr_inst_avl_agent_m0_writedata),                //                         .writedata
+		.uav_lock               (sequencer_pll_mgr_inst_avl_agent_m0_lock),                     //                         .lock
+		.uav_debugaccess        (sequencer_pll_mgr_inst_avl_agent_m0_debugaccess),              //                         .debugaccess
+		.av_address             (sequencer_pll_mgr_inst_avl_address),                           //      avalon_anti_slave_0.address
+		.av_write               (sequencer_pll_mgr_inst_avl_write),                             //                         .write
+		.av_read                (sequencer_pll_mgr_inst_avl_read),                              //                         .read
+		.av_readdata            (sequencer_pll_mgr_inst_avl_readdata),                          //                         .readdata
+		.av_writedata           (sequencer_pll_mgr_inst_avl_writedata),                         //                         .writedata
+		.av_waitrequest         (sequencer_pll_mgr_inst_avl_waitrequest),                       //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_QOS_H                 (74),
+		.PKT_QOS_L                 (74),
+		.PKT_DATA_SIDEBAND_H       (72),
+		.PKT_DATA_SIDEBAND_L       (72),
+		.PKT_ADDR_SIDEBAND_H       (71),
+		.PKT_ADDR_SIDEBAND_L       (71),
+		.PKT_BURST_TYPE_H          (70),
+		.PKT_BURST_TYPE_L          (69),
+		.PKT_CACHE_H               (86),
+		.PKT_CACHE_L               (83),
+		.PKT_THREAD_ID_H           (79),
+		.PKT_THREAD_ID_L           (79),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_EXCLUSIVE       (61),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.ST_DATA_W                 (92),
+		.ST_CHANNEL_W              (3),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (0),
+		.BURSTWRAP_VALUE           (1),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) cpu_inst_data_master_agent (
+		.clk                   (avl_clk_out_clk_clk),                                                     //       clk.clk
+		.reset                 (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
+		.av_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (cpu_inst_data_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (cpu_inst_data_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (cpu_inst_data_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (cpu_inst_data_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (cpu_inst_data_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_src_valid),                                                       //        rp.valid
+		.rp_data               (rsp_mux_src_data),                                                        //          .data
+		.rp_channel            (rsp_mux_src_channel),                                                     //          .channel
+		.rp_startofpacket      (rsp_mux_src_startofpacket),                                               //          .startofpacket
+		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                 //          .endofpacket
+		.rp_ready              (rsp_mux_src_ready),                                                       //          .ready
+		.av_response           (),                                                                        // (terminated)
+		.av_writeresponsevalid ()                                                                         // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_phy_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_phy_mgr_inst_avl_agent_m0_address),                  //              m0.address
+		.m0_burstcount           (sequencer_phy_mgr_inst_avl_agent_m0_burstcount),               //                .burstcount
+		.m0_byteenable           (sequencer_phy_mgr_inst_avl_agent_m0_byteenable),               //                .byteenable
+		.m0_debugaccess          (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess),              //                .debugaccess
+		.m0_lock                 (sequencer_phy_mgr_inst_avl_agent_m0_lock),                     //                .lock
+		.m0_readdata             (sequencer_phy_mgr_inst_avl_agent_m0_readdata),                 //                .readdata
+		.m0_readdatavalid        (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid),            //                .readdatavalid
+		.m0_read                 (sequencer_phy_mgr_inst_avl_agent_m0_read),                     //                .read
+		.m0_waitrequest          (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest),              //                .waitrequest
+		.m0_writedata            (sequencer_phy_mgr_inst_avl_agent_m0_writedata),                //                .writedata
+		.m0_write                (sequencer_phy_mgr_inst_avl_agent_m0_write),                    //                .write
+		.rp_endofpacket          (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket),              //              rp.endofpacket
+		.rp_ready                (sequencer_phy_mgr_inst_avl_agent_rp_ready),                    //                .ready
+		.rp_valid                (sequencer_phy_mgr_inst_avl_agent_rp_valid),                    //                .valid
+		.rp_data                 (sequencer_phy_mgr_inst_avl_agent_rp_data),                     //                .data
+		.rp_startofpacket        (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket),            //                .startofpacket
+		.cp_ready                (cmd_mux_src_ready),                                            //              cp.ready
+		.cp_valid                (cmd_mux_src_valid),                                            //                .valid
+		.cp_data                 (cmd_mux_src_data),                                             //                .data
+		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //                .startofpacket
+		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //                .endofpacket
+		.cp_channel              (cmd_mux_src_channel),                                          //                .channel
+		.rf_sink_ready           (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready),          //         rf_sink.ready
+		.rf_sink_valid           (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid),          //                .valid
+		.rf_sink_startofpacket   (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //                .endofpacket
+		.rf_sink_data            (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data),           //                .data
+		.rf_source_ready         (sequencer_phy_mgr_inst_avl_agent_rf_source_ready),             //       rf_source.ready
+		.rf_source_valid         (sequencer_phy_mgr_inst_avl_agent_rf_source_valid),             //                .valid
+		.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket),     //                .startofpacket
+		.rf_source_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket),       //                .endofpacket
+		.rf_source_data          (sequencer_phy_mgr_inst_avl_agent_rf_source_data),              //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                 //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                //                .error
+		.rdata_fifo_src_ready    (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready),        //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid),        //                .valid
+		.rdata_fifo_src_data     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data),         //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_phy_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_phy_mgr_inst_avl_agent_rf_source_data),              //        in.data
+		.in_valid          (sequencer_phy_mgr_inst_avl_agent_rf_source_valid),             //          .valid
+		.in_ready          (sequencer_phy_mgr_inst_avl_agent_rf_source_ready),             //          .ready
+		.in_startofpacket  (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket),     //          .startofpacket
+		.in_endofpacket    (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket),       //          .endofpacket
+		.out_data          (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data),           //       out.data
+		.out_valid         (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid),          //          .valid
+		.out_ready         (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready),          //          .ready
+		.out_startofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
+		.out_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_rw_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_rw_mgr_inst_avl_agent_m0_address),                   //              m0.address
+		.m0_burstcount           (sequencer_rw_mgr_inst_avl_agent_m0_burstcount),                //                .burstcount
+		.m0_byteenable           (sequencer_rw_mgr_inst_avl_agent_m0_byteenable),                //                .byteenable
+		.m0_debugaccess          (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess),               //                .debugaccess
+		.m0_lock                 (sequencer_rw_mgr_inst_avl_agent_m0_lock),                      //                .lock
+		.m0_readdata             (sequencer_rw_mgr_inst_avl_agent_m0_readdata),                  //                .readdata
+		.m0_readdatavalid        (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid),             //                .readdatavalid
+		.m0_read                 (sequencer_rw_mgr_inst_avl_agent_m0_read),                      //                .read
+		.m0_waitrequest          (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest),               //                .waitrequest
+		.m0_writedata            (sequencer_rw_mgr_inst_avl_agent_m0_writedata),                 //                .writedata
+		.m0_write                (sequencer_rw_mgr_inst_avl_agent_m0_write),                     //                .write
+		.rp_endofpacket          (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket),               //              rp.endofpacket
+		.rp_ready                (sequencer_rw_mgr_inst_avl_agent_rp_ready),                     //                .ready
+		.rp_valid                (sequencer_rw_mgr_inst_avl_agent_rp_valid),                     //                .valid
+		.rp_data                 (sequencer_rw_mgr_inst_avl_agent_rp_data),                      //                .data
+		.rp_startofpacket        (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket),             //                .startofpacket
+		.cp_ready                (cmd_mux_001_src_ready),                                        //              cp.ready
+		.cp_valid                (cmd_mux_001_src_valid),                                        //                .valid
+		.cp_data                 (cmd_mux_001_src_data),                                         //                .data
+		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                                //                .startofpacket
+		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                                  //                .endofpacket
+		.cp_channel              (cmd_mux_001_src_channel),                                      //                .channel
+		.rf_sink_ready           (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready),           //         rf_sink.ready
+		.rf_sink_valid           (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid),           //                .valid
+		.rf_sink_startofpacket   (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
+		.rf_sink_data            (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data),            //                .data
+		.rf_source_ready         (sequencer_rw_mgr_inst_avl_agent_rf_source_ready),              //       rf_source.ready
+		.rf_source_valid         (sequencer_rw_mgr_inst_avl_agent_rf_source_valid),              //                .valid
+		.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket),      //                .startofpacket
+		.rf_source_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket),        //                .endofpacket
+		.rf_source_data          (sequencer_rw_mgr_inst_avl_agent_rf_source_data),               //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                            // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                            //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                             //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                            //                .error
+		.rdata_fifo_src_ready    (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid),         //                .valid
+		.rdata_fifo_src_data     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data),          //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_rw_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_rw_mgr_inst_avl_agent_rf_source_data),               //        in.data
+		.in_valid          (sequencer_rw_mgr_inst_avl_agent_rf_source_valid),              //          .valid
+		.in_ready          (sequencer_rw_mgr_inst_avl_agent_rf_source_ready),              //          .ready
+		.in_startofpacket  (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket),      //          .startofpacket
+		.in_endofpacket    (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket),        //          .endofpacket
+		.out_data          (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data),            //       out.data
+		.out_valid         (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid),           //          .valid
+		.out_ready         (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready),           //          .ready
+		.out_startofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
+		.out_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_pll_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_pll_mgr_inst_avl_agent_m0_address),                  //              m0.address
+		.m0_burstcount           (sequencer_pll_mgr_inst_avl_agent_m0_burstcount),               //                .burstcount
+		.m0_byteenable           (sequencer_pll_mgr_inst_avl_agent_m0_byteenable),               //                .byteenable
+		.m0_debugaccess          (sequencer_pll_mgr_inst_avl_agent_m0_debugaccess),              //                .debugaccess
+		.m0_lock                 (sequencer_pll_mgr_inst_avl_agent_m0_lock),                     //                .lock
+		.m0_readdata             (sequencer_pll_mgr_inst_avl_agent_m0_readdata),                 //                .readdata
+		.m0_readdatavalid        (sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid),            //                .readdatavalid
+		.m0_read                 (sequencer_pll_mgr_inst_avl_agent_m0_read),                     //                .read
+		.m0_waitrequest          (sequencer_pll_mgr_inst_avl_agent_m0_waitrequest),              //                .waitrequest
+		.m0_writedata            (sequencer_pll_mgr_inst_avl_agent_m0_writedata),                //                .writedata
+		.m0_write                (sequencer_pll_mgr_inst_avl_agent_m0_write),                    //                .write
+		.rp_endofpacket          (sequencer_pll_mgr_inst_avl_agent_rp_endofpacket),              //              rp.endofpacket
+		.rp_ready                (sequencer_pll_mgr_inst_avl_agent_rp_ready),                    //                .ready
+		.rp_valid                (sequencer_pll_mgr_inst_avl_agent_rp_valid),                    //                .valid
+		.rp_data                 (sequencer_pll_mgr_inst_avl_agent_rp_data),                     //                .data
+		.rp_startofpacket        (sequencer_pll_mgr_inst_avl_agent_rp_startofpacket),            //                .startofpacket
+		.cp_ready                (cmd_mux_002_src_ready),                                        //              cp.ready
+		.cp_valid                (cmd_mux_002_src_valid),                                        //                .valid
+		.cp_data                 (cmd_mux_002_src_data),                                         //                .data
+		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                                //                .startofpacket
+		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                                  //                .endofpacket
+		.cp_channel              (cmd_mux_002_src_channel),                                      //                .channel
+		.rf_sink_ready           (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready),          //         rf_sink.ready
+		.rf_sink_valid           (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid),          //                .valid
+		.rf_sink_startofpacket   (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //                .endofpacket
+		.rf_sink_data            (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data),           //                .data
+		.rf_source_ready         (sequencer_pll_mgr_inst_avl_agent_rf_source_ready),             //       rf_source.ready
+		.rf_source_valid         (sequencer_pll_mgr_inst_avl_agent_rf_source_valid),             //                .valid
+		.rf_source_startofpacket (sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket),     //                .startofpacket
+		.rf_source_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket),       //                .endofpacket
+		.rf_source_data          (sequencer_pll_mgr_inst_avl_agent_rf_source_data),              //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),                            // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),                            //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                             //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),                            //                .error
+		.rdata_fifo_src_ready    (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready),        //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid),        //                .valid
+		.rdata_fifo_src_data     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data),         //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_pll_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_pll_mgr_inst_avl_agent_rf_source_data),              //        in.data
+		.in_valid          (sequencer_pll_mgr_inst_avl_agent_rf_source_valid),             //          .valid
+		.in_ready          (sequencer_pll_mgr_inst_avl_agent_rf_source_ready),             //          .ready
+		.in_startofpacket  (sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket),     //          .startofpacket
+		.in_endofpacket    (sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket),       //          .endofpacket
+		.out_data          (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data),           //       out.data
+		.out_valid         (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid),          //          .valid
+		.out_ready         (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready),          //          .ready
+		.out_startofpacket (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
+		.out_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_router router (
+		.sink_ready         (cpu_inst_data_master_agent_cp_ready),                          //      sink.ready
+		.sink_valid         (cpu_inst_data_master_agent_cp_valid),                          //          .valid
+		.sink_data          (cpu_inst_data_master_agent_cp_data),                           //          .data
+		.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket),                  //          .startofpacket
+		.sink_endofpacket   (cpu_inst_data_master_agent_cp_endofpacket),                    //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_src_ready),                                             //       src.ready
+		.src_valid          (router_src_valid),                                             //          .valid
+		.src_data           (router_src_data),                                              //          .data
+		.src_channel        (router_src_channel),                                           //          .channel
+		.src_startofpacket  (router_src_startofpacket),                                     //          .startofpacket
+		.src_endofpacket    (router_src_endofpacket)                                        //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_router_001 router_001 (
+		.sink_ready         (sequencer_phy_mgr_inst_avl_agent_rp_ready),                    //      sink.ready
+		.sink_valid         (sequencer_phy_mgr_inst_avl_agent_rp_valid),                    //          .valid
+		.sink_data          (sequencer_phy_mgr_inst_avl_agent_rp_data),                     //          .data
+		.sink_startofpacket (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket),              //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_001_src_ready),                                         //       src.ready
+		.src_valid          (router_001_src_valid),                                         //          .valid
+		.src_data           (router_001_src_data),                                          //          .data
+		.src_channel        (router_001_src_channel),                                       //          .channel
+		.src_startofpacket  (router_001_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_001_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_router_001 router_002 (
+		.sink_ready         (sequencer_rw_mgr_inst_avl_agent_rp_ready),                     //      sink.ready
+		.sink_valid         (sequencer_rw_mgr_inst_avl_agent_rp_valid),                     //          .valid
+		.sink_data          (sequencer_rw_mgr_inst_avl_agent_rp_data),                      //          .data
+		.sink_startofpacket (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket),             //          .startofpacket
+		.sink_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket),               //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_002_src_ready),                                         //       src.ready
+		.src_valid          (router_002_src_valid),                                         //          .valid
+		.src_data           (router_002_src_data),                                          //          .data
+		.src_channel        (router_002_src_channel),                                       //          .channel
+		.src_startofpacket  (router_002_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_002_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_router_001 router_003 (
+		.sink_ready         (sequencer_pll_mgr_inst_avl_agent_rp_ready),                    //      sink.ready
+		.sink_valid         (sequencer_pll_mgr_inst_avl_agent_rp_valid),                    //          .valid
+		.sink_data          (sequencer_pll_mgr_inst_avl_agent_rp_data),                     //          .data
+		.sink_startofpacket (sequencer_pll_mgr_inst_avl_agent_rp_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rp_endofpacket),              //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_003_src_ready),                                         //       src.ready
+		.src_valid          (router_003_src_valid),                                         //          .valid
+		.src_data           (router_003_src_data),                                          //          .data
+		.src_channel        (router_003_src_channel),                                       //          .channel
+		.src_startofpacket  (router_003_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_003_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux cmd_demux (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_src_ready),                                             //      sink.ready
+		.sink_channel       (router_src_channel),                                           //          .channel
+		.sink_data          (router_src_data),                                              //          .data
+		.sink_startofpacket (router_src_startofpacket),                                     //          .startofpacket
+		.sink_endofpacket   (router_src_endofpacket),                                       //          .endofpacket
+		.sink_valid         (router_src_valid),                                             //          .valid
+		.src0_ready         (cmd_demux_src0_ready),                                         //      src0.ready
+		.src0_valid         (cmd_demux_src0_valid),                                         //          .valid
+		.src0_data          (cmd_demux_src0_data),                                          //          .data
+		.src0_channel       (cmd_demux_src0_channel),                                       //          .channel
+		.src0_startofpacket (cmd_demux_src0_startofpacket),                                 //          .startofpacket
+		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                   //          .endofpacket
+		.src1_ready         (cmd_demux_src1_ready),                                         //      src1.ready
+		.src1_valid         (cmd_demux_src1_valid),                                         //          .valid
+		.src1_data          (cmd_demux_src1_data),                                          //          .data
+		.src1_channel       (cmd_demux_src1_channel),                                       //          .channel
+		.src1_startofpacket (cmd_demux_src1_startofpacket),                                 //          .startofpacket
+		.src1_endofpacket   (cmd_demux_src1_endofpacket),                                   //          .endofpacket
+		.src2_ready         (cmd_demux_src2_ready),                                         //      src2.ready
+		.src2_valid         (cmd_demux_src2_valid),                                         //          .valid
+		.src2_data          (cmd_demux_src2_data),                                          //          .data
+		.src2_channel       (cmd_demux_src2_channel),                                       //          .channel
+		.src2_startofpacket (cmd_demux_src2_startofpacket),                                 //          .startofpacket
+		.src2_endofpacket   (cmd_demux_src2_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux cmd_mux (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_src_ready),                                            //       src.ready
+		.src_valid           (cmd_mux_src_valid),                                            //          .valid
+		.src_data            (cmd_mux_src_data),                                             //          .data
+		.src_channel         (cmd_mux_src_channel),                                          //          .channel
+		.src_startofpacket   (cmd_mux_src_startofpacket),                                    //          .startofpacket
+		.src_endofpacket     (cmd_mux_src_endofpacket),                                      //          .endofpacket
+		.sink0_ready         (cmd_demux_src0_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src0_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src0_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src0_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux cmd_mux_001 (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_001_src_ready),                                        //       src.ready
+		.src_valid           (cmd_mux_001_src_valid),                                        //          .valid
+		.src_data            (cmd_mux_001_src_data),                                         //          .data
+		.src_channel         (cmd_mux_001_src_channel),                                      //          .channel
+		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                //          .startofpacket
+		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                  //          .endofpacket
+		.sink0_ready         (cmd_demux_src1_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src1_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src1_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src1_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src1_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux cmd_mux_002 (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_002_src_ready),                                        //       src.ready
+		.src_valid           (cmd_mux_002_src_valid),                                        //          .valid
+		.src_data            (cmd_mux_002_src_data),                                         //          .data
+		.src_channel         (cmd_mux_002_src_channel),                                      //          .channel
+		.src_startofpacket   (cmd_mux_002_src_startofpacket),                                //          .startofpacket
+		.src_endofpacket     (cmd_mux_002_src_endofpacket),                                  //          .endofpacket
+		.sink0_ready         (cmd_demux_src2_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src2_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src2_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src2_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src2_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux rsp_demux (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_001_src_ready),                                         //      sink.ready
+		.sink_channel       (router_001_src_channel),                                       //          .channel
+		.sink_data          (router_001_src_data),                                          //          .data
+		.sink_startofpacket (router_001_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_001_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_001_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_src0_ready),                                         //      src0.ready
+		.src0_valid         (rsp_demux_src0_valid),                                         //          .valid
+		.src0_data          (rsp_demux_src0_data),                                          //          .data
+		.src0_channel       (rsp_demux_src0_channel),                                       //          .channel
+		.src0_startofpacket (rsp_demux_src0_startofpacket),                                 //          .startofpacket
+		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux rsp_demux_001 (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_002_src_ready),                                         //      sink.ready
+		.sink_channel       (router_002_src_channel),                                       //          .channel
+		.sink_data          (router_002_src_data),                                          //          .data
+		.sink_startofpacket (router_002_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_002_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_002_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_001_src0_ready),                                     //      src0.ready
+		.src0_valid         (rsp_demux_001_src0_valid),                                     //          .valid
+		.src0_data          (rsp_demux_001_src0_data),                                      //          .data
+		.src0_channel       (rsp_demux_001_src0_channel),                                   //          .channel
+		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                             //          .startofpacket
+		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux rsp_demux_002 (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_003_src_ready),                                         //      sink.ready
+		.sink_channel       (router_003_src_channel),                                       //          .channel
+		.sink_data          (router_003_src_data),                                          //          .data
+		.sink_startofpacket (router_003_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_003_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_003_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_002_src0_ready),                                     //      src0.ready
+		.src0_valid         (rsp_demux_002_src0_valid),                                     //          .valid
+		.src0_data          (rsp_demux_002_src0_data),                                      //          .data
+		.src0_channel       (rsp_demux_002_src0_channel),                                   //          .channel
+		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                             //          .startofpacket
+		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux rsp_mux (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_src_ready),                                            //       src.ready
+		.src_valid           (rsp_mux_src_valid),                                            //          .valid
+		.src_data            (rsp_mux_src_data),                                             //          .data
+		.src_channel         (rsp_mux_src_channel),                                          //          .channel
+		.src_startofpacket   (rsp_mux_src_startofpacket),                                    //          .startofpacket
+		.src_endofpacket     (rsp_mux_src_endofpacket),                                      //          .endofpacket
+		.sink0_ready         (rsp_demux_src0_ready),                                         //     sink0.ready
+		.sink0_valid         (rsp_demux_src0_valid),                                         //          .valid
+		.sink0_channel       (rsp_demux_src0_channel),                                       //          .channel
+		.sink0_data          (rsp_demux_src0_data),                                          //          .data
+		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                                   //          .endofpacket
+		.sink1_ready         (rsp_demux_001_src0_ready),                                     //     sink1.ready
+		.sink1_valid         (rsp_demux_001_src0_valid),                                     //          .valid
+		.sink1_channel       (rsp_demux_001_src0_channel),                                   //          .channel
+		.sink1_data          (rsp_demux_001_src0_data),                                      //          .data
+		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                             //          .startofpacket
+		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                               //          .endofpacket
+		.sink2_ready         (rsp_demux_002_src0_ready),                                     //     sink2.ready
+		.sink2_valid         (rsp_demux_002_src0_valid),                                     //          .valid
+		.sink2_channel       (rsp_demux_002_src0_channel),                                   //          .channel
+		.sink2_data          (rsp_demux_002_src0_data),                                      //          .data
+		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                             //          .startofpacket
+		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data),         //     in_0.data
+		.in_0_valid     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid),        //         .valid
+		.in_0_ready     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready),        //         .ready
+		.out_0_data     (avalon_st_adapter_out_0_data),                                 //    out_0.data
+		.out_0_valid    (avalon_st_adapter_out_0_valid),                                //         .valid
+		.out_0_ready    (avalon_st_adapter_out_0_ready),                                //         .ready
+		.out_0_error    (avalon_st_adapter_out_0_error)                                 //         .error
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data),          //     in_0.data
+		.in_0_valid     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid),         //         .valid
+		.in_0_ready     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready),         //         .ready
+		.out_0_data     (avalon_st_adapter_001_out_0_data),                             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                            //         .valid
+		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                            //         .ready
+		.out_0_error    (avalon_st_adapter_001_out_0_error)                             //         .error
+	);
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_002 (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data),         //     in_0.data
+		.in_0_valid     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid),        //         .valid
+		.in_0_ready     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready),        //         .ready
+		.out_0_data     (avalon_st_adapter_002_out_0_data),                             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_002_out_0_valid),                            //         .valid
+		.out_0_ready    (avalon_st_adapter_002_out_0_ready),                            //         .ready
+		.out_0_error    (avalon_st_adapter_002_out_0_error)                             //         .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v
new file mode 100644
index 0000000..95e1c83
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v
@@ -0,0 +1,202 @@
+// q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..5b08052
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv
new file mode 100644
index 0000000..18315ff
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux.sv
@@ -0,0 +1,130 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+//   NUM_OUTPUTS:         3
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
+    input  [3-1 : 0]   sink_channel, // ST_CHANNEL_W=3
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src0_channel, // ST_CHANNEL_W=3
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [92-1    : 0] src1_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src1_channel, // ST_CHANNEL_W=3
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [92-1    : 0] src2_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src2_channel, // ST_CHANNEL_W=3
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 3;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv
new file mode 100644
index 0000000..8596069
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+// ------------------------------------------
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [92-1   : 0]  sink0_data,
+    input [3-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [92-1    : 0] src_data,
+    output [3-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 92 + 3 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 92;
+    localparam ST_CHANNEL_W     = 3;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv
new file mode 100644
index 0000000..bca6179
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router.sv
@@ -0,0 +1,234 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [78 - 77 : 0] default_destination_id,
+   output [3-1 : 0] default_wr_channel,
+   output [3-1 : 0] default_rd_channel,
+   output [3-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[78 - 77 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 3'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 3'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 3'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [92-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [92-1    : 0] src_data,
+    output reg [3-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 78;
+    localparam PKT_DEST_ID_L = 77;
+    localparam PKT_PROTECTION_H = 82;
+    localparam PKT_PROTECTION_L = 80;
+    localparam ST_DATA_W = 92;
+    localparam ST_CHANNEL_W = 3;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h50000 - 64'h48000); 
+    localparam PAD1 = log2ceil(64'h58000 - 64'h50000); 
+    localparam PAD2 = log2ceil(64'h60000 - 64'h58000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h60000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [3-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_ddr3_ram_s0_mm_interconnect_0_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x48000 .. 0x50000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h48000   ) begin
+            src_channel = 3'b001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+    // ( 0x50000 .. 0x58000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h50000   ) begin
+            src_channel = 3'b010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x58000 .. 0x60000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h58000   ) begin
+            src_channel = 3'b100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv
new file mode 100644
index 0000000..0a86a22
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_router_001.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_router_001_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [78 - 77 : 0] default_destination_id,
+   output [3-1 : 0] default_wr_channel,
+   output [3-1 : 0] default_rd_channel,
+   output [3-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[78 - 77 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 3'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 3'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 3'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_router_001
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [92-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [92-1    : 0] src_data,
+    output reg [3-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 78;
+    localparam PKT_DEST_ID_L = 77;
+    localparam PKT_PROTECTION_H = 82;
+    localparam PKT_PROTECTION_L = 80;
+    localparam ST_DATA_W = 92;
+    localparam ST_CHANNEL_W = 3;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [3-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_ddr3_ram_s0_mm_interconnect_0_router_001_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 3'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv
new file mode 100644
index 0000000..dd6214b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
+    input  [3-1 : 0]   sink_channel, // ST_CHANNEL_W=3
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src0_channel, // ST_CHANNEL_W=3
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv
new file mode 100644
index 0000000..204e963
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux.sv
@@ -0,0 +1,365 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux
+//   NUM_INPUTS:          3
+//   ARBITRATION_SHARES:  1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+// ------------------------------------------
+
+module q_sys_ddr3_ram_s0_mm_interconnect_0_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [92-1   : 0]  sink0_data,
+    input [3-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [92-1   : 0]  sink1_data,
+    input [3-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [92-1   : 0]  sink2_data,
+    input [3-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [92-1    : 0] src_data,
+    output [3-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 92 + 3 + 2;
+    localparam NUM_INPUTS       = 3;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 92;
+    localparam ST_CHANNEL_W     = 3;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[60];
+      lock[1] = sink1_data[60];
+      lock[2] = sink2_data[60];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h
new file mode 100644
index 0000000..a82e720
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_defines.h
@@ -0,0 +1,164 @@
+/*
+Copyright (C) 2016 Intel Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000000000
+#define AC_ROM_MR1_OCD_ENABLE 
+#define AC_ROM_MR2_MIRR 0000000000000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB 
+#define AC_ROM_MR0_DLL_RESET_MIRR 0001010001000
+#define AC_ROM_MR0_DLL_RESET 0001100010000
+#define AC_ROM_MR0_MIRR 0001000001001
+#define AC_ROM_MR0 0001000010001
+#define AC_ROM_MR1 0000000000000
+#define AC_ROM_MR2 0000000000000
+#define AC_ROM_MR3 0000000000000
+#define AC_ROM_USER_ADD_0 0_0000_0000_0000
+#define AC_ROM_USER_ADD_1 0_0000_0000_1000
+#define AFI_CLK_FREQ 151
+#define AFI_RATE_RATIO 2
+#define AP_MODE 0
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 1
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 4
+#define CALIB_VFIFO_OFFSET 12
+#define CYCLONEV 0
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DELAY_CHAIN_WRITE 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 0
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_NON_DES_CAL_TEST 0
+#define ENABLE_NON_DES_CAL 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FAKE_CAL_FAIL 0
+#define FIX_READ_LATENCY 8
+#define FULL_RATE 0
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 1
+#define HARD_PHY 0
+#define HARD_VFIFO 0
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 0
+#define HPS_HW 0
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 50
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 50
+#define IO_DELAY_PER_OPA_TAP 416
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 14
+#define IO_DQS_EN_DELAY_MAX 7
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 15
+#define IO_DQS_IN_RESERVE 3
+#define IO_DQS_OUT_RESERVE 3
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 15
+#define IO_IO_OUT1_DELAY_MAX 15
+#define IO_IO_OUT2_DELAY_MAX 7
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MRS_MIRROR_PING_PONG_ATSO 0
+#define NON_DES_CAL 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 0
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 14
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 1
+#define RW_MGR_MEM_DATA_WIDTH 8
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 1
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 1
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 1
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SET_FIX_READ_LATENCY_ENABLE 0
+#define SKEW_CALIBRATION 0
+#define SKIP_PTAP_0_DQS_EN_CAL 0
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 36
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 36
+#define USE_DQS_TRACKING 0
+#define USE_SHADOW_REGS 0
+#define USE_USER_RDIMM_VALUE 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c
new file mode 100644
index 0000000..63a9745
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.c
@@ -0,0 +1,720 @@
+
+#include "sequencer_defines.h"
+
+#include "alt_types.h"
+#include "system.h"
+#include "io.h"
+#include "sequencer_m10.h"
+#include "sequencer_auto.h"
+
+// Just to make the debugging code more uniform
+#ifndef RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 0
+#endif
+
+// To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
+// instead of static, we use boolean logic to select between
+// non-skip and skip values
+//
+// The mask is set to include all bits when not-skipping, but is
+// zero when skipping
+
+gbl_t *gbl = 0;
+param_t *param = 0;
+
+void initialize(void)
+{
+	alt_u32 i;
+	
+	// Initial LFIFO is max
+	
+	IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, 0xf);
+
+	//USER calibration has control over path to memory 
+
+	IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 1);
+
+	//USER memory clock is not stable we begin initialization 
+
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 0);
+
+	//USER calibration status all set to zero 
+
+	IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, 0);
+
+	param->read_correct_mask_vg  = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+	param->write_correct_mask_vg = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+	param->read_correct_mask     = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
+	param->write_correct_mask    = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+	param->dm_correct_mask       = ((t_btfld)1 << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH)) - 1;
+}
+
+void set_rank_and_odt_mask(alt_u32 rank)
+{
+	alt_u32 odt_mask_0 = 0;
+	alt_u32 odt_mask_1 = 0;
+	alt_u32 cs_and_odt_mask;
+	
+	odt_mask_0 = 0x0;
+	odt_mask_1 = 0x0;
+
+	cs_and_odt_mask = 
+		(0xFF & ~(1 << rank)) |
+		((0xFF & odt_mask_0) << 8) |
+		((0xFF & odt_mask_1) << 16);
+
+	IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask);
+}
+
+// should always use constants as argument to ensure all computations are performed at compile time
+static inline void delay_for_n_mem_clocks(const alt_u32 clocks)
+{
+	alt_u32 afi_clocks;
+	alt_u8 inner;
+	alt_u8 outer;
+	alt_u16 c_loop;
+
+	afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO; /* scale (rounding up) to get afi clocks */
+
+	// Note, we don't bother accounting for being off a little bit because of a few extra instructions in outer loops
+	// Note, the loops have a test at the end, and do the test before the decrement, and so always perform the loop
+	// 1 time more than the counter value
+	if (afi_clocks == 0) {
+		inner = outer = c_loop = 0;
+	} else if (afi_clocks <= 0x100) {
+		inner = afi_clocks-1;
+		outer = 0;
+		c_loop = 0;
+	} else if (afi_clocks <= 0x10000) {
+		inner = 0xff;
+		outer = (afi_clocks-1) >> 8;
+		c_loop = 0;
+	} else {
+		inner = 0xff;
+		outer = 0xff;
+		c_loop = (afi_clocks-1) >> 16;
+	}
+
+	// rom instructions are structured as follows:
+	//
+	//    IDLE_LOOP2: jnz cntr0, TARGET_A
+	//    IDLE_LOOP1: jnz cntr1, TARGET_B
+	//                return
+	//
+	// so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and TARGET_B is
+	// set to IDLE_LOOP2 as well
+	//
+	// if we have no outer loop, though, then we can use IDLE_LOOP1 only, and set
+	// TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
+	//
+	// a little confusing, but it helps save precious space in the inst_rom and sequencer rom
+	// and keeps the delays more accurate and reduces overhead
+	if (afi_clocks <= 0x100) {
+
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, inner);
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP1);
+		IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP1);
+
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, inner);
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, outer);
+	
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_IDLE_LOOP2);
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP2);
+
+		// hack to get around compiler not being smart enough
+		if (afi_clocks <= 0x10000) {
+			// only need to run once
+			IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
+		} else {
+			do {
+				IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
+			} while (c_loop-- != 0);
+		}
+	}
+
+}
+
+// should always use constants as argument to ensure all computations are performed at compile time
+static inline void delay_for_n_ns(const alt_u32 nanoseconds)
+{
+	delay_for_n_mem_clocks((1000*nanoseconds) / (1000000/AFI_CLK_FREQ) * AFI_RATE_RATIO);
+}
+
+#if DDR3
+void rw_mgr_mem_initialize (void)
+{
+	//USER The reset / cke part of initialization is broadcasted to all ranks
+	IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL);
+
+	//USER start with memory RESET activated
+	//USER tINIT = 200us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0xFF
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0x6A
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_0_CKE_0_inloop);
+
+	//USER Execute count instruction
+	//USER IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0);
+
+	//USER indicate that memory is stable
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER transition the RESET to high 
+	//USER Wait for 500us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0x83
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0xFF
+
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0_inloop_1);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0);
+
+	//USER bring up clock enable 
+
+	//USER tXRP < 250 ck cycles
+	delay_for_n_mem_clocks(250);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET);
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ZQCL);
+    
+	//USER tZQinit = tDLLK = 512 ck cycles
+	delay_for_n_mem_clocks(512);
+
+}
+#endif // DDR3
+
+#if DDR2
+void rw_mgr_mem_initialize (void)
+{
+	//USER start with CKE low 
+	//USER tINIT = 200us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0xFF
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0x76
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0_inloop);
+
+	//USER Execute count instruction
+	//USER IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER indicate that memory is stable 
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER Bring up CKE 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_NOP);
+
+	//USER *** STAGE (4)
+
+	//USER Wait for 400ns 
+	delay_for_n_ns(400);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER *** STAGE (5)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2);
+    
+	//USER *** STAGE (6)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3);
+    
+	//USER *** STAGE (7)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+    
+	//USER *** STAGE (8)
+	//USER DLL reset
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_DLL_RESET);
+    
+	//USER *** STAGE (9)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER *** STAGE (10)
+    
+	//USER Issue 2 refresh commands spaced by tREF 
+    
+	//USER First REFRESH
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH);
+    
+	//USER tREF = 200ns
+	delay_for_n_ns(200);
+    
+	//USER Second REFRESH
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH);
+    
+	//USER Second idle loop
+	delay_for_n_ns(200);
+    
+	//USER *** STAGE (11)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_CALIB);
+    
+	//USER *** STAGE (12)
+	//USER OCD defaults
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR_OCD_ENABLE);
+    
+	//USER *** STAGE (13)
+	//USER OCD exit
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+    
+	//USER *** STAGE (14)
+    
+	//USER The memory is now initialized. Before being able to use it, we must still
+	//USER wait for the DLL to lock, 200 clock cycles after it was reset @ STAGE (8).
+	//USER Since we cannot keep track of time in any other way, let's start counting from now
+	delay_for_n_mem_clocks(200);
+}
+#endif // DDR2 
+
+#if LPDDR2
+void rw_mgr_mem_initialize (void)
+{
+	//USER start with CKE low 
+	//USER tINIT1 = 100ns
+
+	//USER Load counter
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x10);
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER Execute count instruction
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER tINIT3 = 200us
+	delay_for_n_ns(200000);
+
+	//USER indicate that memory is stable 
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER MRW RESET
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR63_RESET);
+
+	//USER tINIT5 = 10us
+	delay_for_n_ns(10000);
+
+	//USER MRW ZQC
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR10_ZQC);
+    
+	//USER tZQINIT = 1us
+	delay_for_n_ns(1000);
+    
+	//USER MRW MR1
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_CALIB);
+    
+	//USER MRW MR2
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2);
+    
+	//USER MRW MR3
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3);
+}
+#endif // LPDDR2 
+
+//USER  At the end of calibration we have to program the user settings in, and
+//USER  hand off the memory to the user.
+
+#if DDR3
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks ... 
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER load up MR settings specified by user 
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER);
+}
+#endif // DDR3
+
+#if DDR2
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks ... 
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+
+	//USER load up MR settings specified by user 
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_USER);
+}
+#endif //USER DDR2
+
+#if LPDDR2
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks...
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+
+	//USER load up MR settings specified by user
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_USER);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3);
+}
+#endif //USER LPDDR2
+
+//USER load up the patterns we are going to use during a read test 
+void rw_mgr_mem_calibrate_read_load_patterns ()
+{
+	//USER Load up a constant bursts
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x02);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_WAIT2);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x02);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_WAIT3);
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE);
+}
+
+//USER  try a read and see if it returns correct data back. has dummy reads inserted into the mix
+//USER  used to align dqs enable. has more thorough checks than the regular read test.
+alt_u32 rw_mgr_mem_calibrate_read_test (alt_u32 group, alt_u32 num_tries, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_groups)
+{
+	alt_u32 vg;
+	t_btfld correct_mask_vg;
+	t_btfld tmp_bit_chk;
+
+	*bit_chk = param->read_correct_mask;
+	correct_mask_vg = param->read_correct_mask_vg;
+	
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x10);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1);
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x10);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2);
+	
+	if (all_groups) {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x06);
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x32);
+	}
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B);
+	if(all_groups) {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1);
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0);
+	}
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B);
+	
+	tmp_bit_chk = 0;
+	for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--)
+	{
+		//USER reset the fifos to get pointers to known state 
+
+		IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0);
+		IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0);	
+
+		tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
+
+		IOWR_32DIRECT (all_groups ? RW_MGR_RUN_ALL_GROUPS : RW_MGR_RUN_SINGLE_GROUP, ((group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS+vg) << 2), __RW_MGR_READ_B2B);
+		tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0)));
+
+		if (vg == 0) {
+			break;
+		}
+	}
+	*bit_chk &= tmp_bit_chk;
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE);
+	
+	if (all_correct)
+	{
+		return (*bit_chk == param->read_correct_mask);
+	}
+	else
+	{
+		return (*bit_chk != 0x00);
+	}
+}
+
+//USER find a good dqs enable to use 
+alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp)
+{
+	alt_u32 v;
+	alt_u32 p;
+	t_btfld bit_chk;
+	alt_u32 found_vfifo;
+	alt_u32 vfifo_not_found;
+	alt_u32 counter;
+	alt_u32 test_status;
+	alt_u32 fail_to_fail_phase;
+	alt_u32 capture_clk;
+	
+	if (grp == 2) {
+	    capture_clk = 1;
+	} else {
+	    capture_clk = grp;
+	}
+
+	//USER ********************************************************
+	//USER * step 2: find working VFIFO
+	found_vfifo = 0;
+	vfifo_not_found = 0;
+	counter = 0;
+	while (1) {
+	    for (v = 0; v < RTL_VFIFO_SIZE; v++) {
+		    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ALL_BITS, &bit_chk, 0);
+		    
+		    if (test_status) {
+				found_vfifo = 1;
+				break;
+			}
+			
+			IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, grp);
+		}
+		
+		if (found_vfifo) {
+			break;
+		}
+		
+		PLL_INCR(capture_clk << 2);
+		
+		#if LPDDR2
+		PLL_INCR(capture_clk+0x4);
+		#endif
+		
+		// 600 steps of 10ps is one full clock at 167Mhz
+		// 10ps is the PLL phase step resolution
+		// trying this value for now, we know that sometimes we need to sweep two clock due to reset condition of div 2 register
+		counter++;
+		if (counter == 600) {
+		    vfifo_not_found = 1;
+		    break;
+		}
+	}
+	
+	//USER ********************************************************
+	//USER * step 3: decrement phase until read fails
+	
+	while (1) {
+	    if (vfifo_not_found) {
+	        break;
+	    }
+	    
+	    // decrement first because the current phase would work
+	    PLL_DECR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_DECR(capture_clk+0x4);
+        #endif
+	    
+	    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
+	    
+	    if (!test_status) {
+	        break;
+	    }
+	}
+	
+	//USER ********************************************************
+	//USER * step 4: increment phase until read fails to determine window
+	fail_to_fail_phase = 0;
+	while (1) {
+	    if (vfifo_not_found) {
+	        break;
+	    }
+	    
+	    // increment first since the current phase wouldnt work
+	    PLL_INCR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_INCR(capture_clk+0x4);
+        #endif
+	    
+	    fail_to_fail_phase++;
+	    
+	    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
+	    
+	    if (!test_status) {
+	        break;
+	    }
+	}
+	
+	//back by half to get best margin
+	for (p = 0; p < (fail_to_fail_phase/2); p++) {
+	    PLL_DECR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_DECR(capture_clk+0x4);
+        #endif
+	}
+	
+	if (found_vfifo) {
+		return 1;
+	} else {
+	    return 0;
+	}
+}
+
+//USER VFIFO Calibration -- Full Calibration
+alt_u32 rw_mgr_mem_calibrate_vfifo ()
+{
+	rw_mgr_mem_calibrate_read_load_patterns ();
+	
+	int group0=0;
+	int group1=0;
+	
+	#if M10_DQ_WIDTH_8
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=1;
+	#endif
+	
+	#if M10_DQ_WIDTH_16
+	    #if TW0_CAPTURE_CLOCKS
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(1);
+	    #else
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=1;
+	    #endif
+	#endif
+	
+	#if M10_DQ_WIDTH_24
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(2);
+	#endif
+	
+	if (group0 && group1) {
+		return 1;
+	} else {
+	    return 0;
+	}
+}
+
+//USER precharge all banks and activate row 0 in bank "000..." and bank "111..." 
+void mem_precharge_and_activate (void)
+{
+	//USER precharge all banks ... 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0F);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT1);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0F);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2);
+    
+	//USER activate rows 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1);
+}
+
+//USER Configure various memory related parameters.
+void mem_config (void)
+{
+	alt_u32 wlat;
+
+	//USER read in write and read latency 
+
+	wlat = IORD_32DIRECT (MEM_T_WL_ADD, 0);
+	
+	//USER write latency 
+	wlat = (wlat - 1) / 2 + 1;
+
+	//USER advertise write latency 
+	gbl->curr_write_lat = wlat;
+	IOWR_32DIRECT (PHY_MGR_AFI_WLAT, 0, wlat - 1);
+	
+	mem_precharge_and_activate ();
+}
+
+//USER Memory calibration entry point
+ 
+alt_u32 mem_calibrate (void)
+{
+	// Initialize the data settings
+
+	gbl->error_substage = CAL_SUBSTAGE_NIL;
+	gbl->error_stage = CAL_STAGE_NIL;
+	gbl->error_group = 0xff;
+
+	mem_config ();
+	
+	//USER Calibrate the VFIFO
+	
+	if (!rw_mgr_mem_calibrate_vfifo ()) {
+	    return 0;
+	} else {
+	    return 1;
+	}
+}
+
+alt_u32 run_mem_calibrate(void) {
+	alt_u32 pass;
+
+    initialize();
+	
+    set_rank_and_odt_mask(0);
+    
+	rw_mgr_mem_initialize ();
+
+	pass = mem_calibrate ();
+
+	mem_precharge_and_activate ();
+	
+	IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0);
+
+	//USER Handoff
+
+	rw_mgr_mem_handoff ();
+
+	IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0);
+
+	if (pass) {
+
+		IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_SUCCESS);
+
+	} else {
+		
+		IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL);
+	}
+
+	return pass;
+}
+
+int main(void)
+{
+	param_t my_param;
+	gbl_t my_gbl;
+	alt_u32 pass;
+
+	param = &my_param;
+	gbl = &my_gbl;
+
+	IOWR_32DIRECT (RW_MGR_SOFT_RESET, 0, 0);
+
+	pass = run_mem_calibrate ();
+
+	while (1) {
+	}
+
+	return pass;
+}
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h
new file mode 100644
index 0000000..d8efb04
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ddr3_ram_s0_software/sequencer_m10.h
@@ -0,0 +1,345 @@
+#ifndef _SEQUENCER_H_
+#define _SEQUENCER_H_
+
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if ENABLE_ASSERT
+#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s"
+
+extern void err_report_internal_error (const char* description, const char* module, const char* file, int line);
+
+#define ALTERA_INTERNAL_ERROR(string) {err_report_internal_error(string, "SEQ", __FILE__, __LINE__); exit(-1);}
+
+#define ALTERA_ASSERT(condition) \
+    if (!(condition)) { ALTERA_INTERNAL_ERROR(#condition); }
+#define ALTERA_INFO_ASSERT(condition,text) \
+    if (!(condition)) { ALTERA_INTERNAL_ERROR(text); }
+
+#else
+
+#define ALTERA_ASSERT(condition)
+#define ALTERA_INFO_ASSERT(condition,text)
+
+#endif
+
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
+
+#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR
+#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400
+
+#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0010)
+
+#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
+#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
+#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808
+#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C
+
+#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00
+#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04
+#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08
+#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C
+
+#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000
+#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000
+
+#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400
+#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400
+
+#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200
+
+#define RW_MGR_RANK_NONE 0xFF
+#define RW_MGR_RANK_ALL 0x00
+
+#define RW_MGR_ODT_MODE_OFF 0
+#define RW_MGR_ODT_MODE_READ_WRITE 1
+
+#define NUM_CALIB_REPEAT	1
+
+#define NUM_READ_TESTS			7
+#define NUM_READ_PB_TESTS		7
+#define NUM_WRITE_TESTS			15
+#define NUM_WRITE_PB_TESTS		31
+
+#define PASS_ALL_BITS			1
+#define PASS_ONE_BIT			0
+
+/* calibration stages */
+
+#define CAL_STAGE_NIL			0
+#define CAL_STAGE_VFIFO			1
+#define CAL_STAGE_WLEVEL		2
+#define CAL_STAGE_LFIFO			3
+#define CAL_STAGE_WRITES		4
+#define CAL_STAGE_FULLTEST		5
+#define CAL_STAGE_REFRESH		6
+#define CAL_STAGE_CAL_SKIPPED		7
+#define CAL_STAGE_CAL_ABORTED		8
+#define CAL_STAGE_VFIFO_AFTER_WRITES	9
+
+/* calibration substages */
+
+#define CAL_SUBSTAGE_NIL		0
+#define CAL_SUBSTAGE_GUARANTEED_READ	1
+#define CAL_SUBSTAGE_DQS_EN_PHASE	2
+#define CAL_SUBSTAGE_VFIFO_CENTER	3
+#define CAL_SUBSTAGE_WORKING_DELAY	1
+#define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
+#define CAL_SUBSTAGE_WLEVEL_COPY	3
+#define CAL_SUBSTAGE_WRITES_CENTER	1
+#define CAL_SUBSTAGE_READ_LATENCY	1
+#define CAL_SUBSTAGE_REFRESH		1
+
+#define MAX_RANKS			(RW_MGR_MEM_NUMBER_OF_RANKS)
+#define MAX_DQS				(RW_MGR_MEM_IF_WRITE_DQS_WIDTH > RW_MGR_MEM_IF_READ_DQS_WIDTH ? RW_MGR_MEM_IF_WRITE_DQS_WIDTH : RW_MGR_MEM_IF_READ_DQS_WIDTH)
+#define MAX_DQ				(RW_MGR_MEM_DATA_WIDTH)
+#define MAX_DM				(RW_MGR_MEM_DATA_MASK_WIDTH)
+
+/* length of VFIFO, from SW_MACROS */
+#define VFIFO_SIZE			(READ_VALID_FIFO_SIZE)
+
+/* Memory for data transfer between TCL scripts and NIOS.
+ *
+ * - First word is a command request.
+ * - The remaining words are part of the transfer.
+ */
+
+/* Define the base address of each manager. */
+
+/* MarkW: how should these base addresses be done for A-V? */
+#define BASE_PTR_MGR 					SEQUENCER_PTR_MGR_INST_BASE
+#define BASE_PHY_MGR 					SEQUENCER_PHY_MGR_INST_BASE
+#define BASE_RW_MGR  					SEQUENCER_RW_MGR_INST_BASE
+#define BASE_DATA_MGR					SEQUENCER_DATA_MGR_INST_BASE
+#define BASE_PLL_MGR					0x00058000 /* Aidil - todo */
+#define BASE_REG_FILE					SEQUENCER_REG_FILE_INST_BASE
+#define BASE_TIMER					SEQUENCER_TIMER_INST_BASE
+#define BASE_MMR                                        (0x000C0000)
+#define BASE_TRK_MGR					(0x000D0000)
+
+/* Register file addresses. */
+#define REG_FILE_SIGNATURE				(BASE_REG_FILE + 0x0000)
+#define REG_FILE_DEBUG_DATA_ADDR		(BASE_REG_FILE + 0x0004)
+#define REG_FILE_CUR_STAGE              (BASE_REG_FILE + 0x0008)
+#define REG_FILE_FOM                    (BASE_REG_FILE + 0x000C)
+#define REG_FILE_FAILING_STAGE          (BASE_REG_FILE + 0x0010)
+#define REG_FILE_DEBUG1                 (BASE_REG_FILE + 0x0014)
+#define REG_FILE_DEBUG2                 (BASE_REG_FILE + 0x0018)
+
+#if TRACKING_WATCH_TEST || TRACKING_ERROR_TEST
+#define REG_FILE_TRK_SAMPLE_CHECK	(BASE_REG_FILE + 0x003C)
+#elif MARGIN_VARIATION_TEST
+#define IO_DQS_EN_DELAY_OFFSET		(IORD_32DIRECT(BASE_REG_FILE + 0x003C, 0))
+#endif
+
+/* Tracking slave addresses. */
+#define TRK_DTAPS_PER_PTAP     (BASE_TRK_MGR + 0x0000)
+#define TRK_SAMPLE_COUNT       (BASE_TRK_MGR + 0x0004)
+#define TRK_LONGIDLE           (BASE_TRK_MGR + 0x0008)
+#define TRK_DELAYS             (BASE_TRK_MGR + 0x000C)
+#define TRK_RW_MGR_ADDR        (BASE_TRK_MGR + 0x0010)
+#define TRK_READ_DQS_WIDTH     (BASE_TRK_MGR + 0x0014)
+#define TRK_RFSH               (BASE_TRK_MGR + 0x0018)
+#define TRK_STALL              (BASE_TRK_MGR + 0x001C)
+#define TRK_V_POINTER          (BASE_TRK_MGR + 0x0020)
+
+#define TRK_STALL_REQ_VAL      (0x1)
+#define TRK_STALL_ACKED_VAL    (0x80000000 | TRK_STALL_REQ_VAL)
+
+/* PHY manager configuration registers. */
+
+#define PHY_MGR_PHY_RLAT				(BASE_PHY_MGR + 0x4000)
+#define PHY_MGR_RESET_MEM_STBL			(BASE_PHY_MGR + 0x4004)
+#define PHY_MGR_MUX_SEL					(BASE_PHY_MGR + 0x4008)
+#define PHY_MGR_CAL_STATUS				(BASE_PHY_MGR + 0x400c)
+#define PHY_MGR_CAL_DEBUG_INFO			(BASE_PHY_MGR + 0x4010)
+#define PHY_MGR_VFIFO_RD_EN_OVRD		(BASE_PHY_MGR + 0x4014)
+#if CALIBRATE_BIT_SLIPS
+#define PHY_MGR_FR_SHIFT				(BASE_PHY_MGR + 0x4020)
+#define PHY_MGR_AFI_WLAT				(BASE_PHY_MGR + 0x4018)
+#else
+#define PHY_MGR_AFI_WLAT				(BASE_PHY_MGR + 0x4018)
+#endif
+#define PHY_MGR_AFI_RLAT				(BASE_PHY_MGR + 0x401c)
+
+#define PHY_MGR_CAL_SUCCESS				(1)
+#define PHY_MGR_CAL_FAIL				(2)
+
+/* PHY manager command addresses. */
+
+#define PHY_MGR_CMD_INC_VFIFO_FR		(BASE_PHY_MGR + 0x0000)
+#define PHY_MGR_CMD_INC_VFIFO_HR		(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY	(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_CMD_FIFO_RESET			(BASE_PHY_MGR + 0x0008)
+#define PHY_MGR_CMD_INC_VFIFO_FR_HR		(BASE_PHY_MGR + 0x000C)
+#define PHY_MGR_CMD_INC_VFIFO_QR		(BASE_PHY_MGR + 0x0010)
+
+/* PHY manager parameters. */
+
+#define PHY_MGR_MAX_RLAT_WIDTH			(BASE_PHY_MGR + 0x0000)
+#define PHY_MGR_MAX_AFI_WLAT_WIDTH 		(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_MAX_AFI_RLAT_WIDTH 		(BASE_PHY_MGR + 0x0008)
+#define PHY_MGR_CALIB_SKIP_STEPS		(BASE_PHY_MGR + 0x000c)
+#define PHY_MGR_CALIB_VFIFO_OFFSET		(BASE_PHY_MGR + 0x0010)
+#define PHY_MGR_CALIB_LFIFO_OFFSET		(BASE_PHY_MGR + 0x0014)
+#define PHY_MGR_RDIMM					(BASE_PHY_MGR + 0x0018)
+#define PHY_MGR_MEM_T_WL				(BASE_PHY_MGR + 0x001c)
+#define PHY_MGR_MEM_T_RL				(BASE_PHY_MGR + 0x0020)
+
+/* Data Manager */
+#define DATA_MGR_DRAM_CFG				(BASE_DATA_MGR + 0x0000)
+#define DATA_MGR_MEM_T_WL				(BASE_DATA_MGR + 0x0004)
+#define DATA_MGR_MEM_T_ADD				(BASE_DATA_MGR + 0x0008)
+#define DATA_MGR_MEM_T_RL				(BASE_DATA_MGR + 0x000C)
+#define DATA_MGR_MEM_T_RFC				(BASE_DATA_MGR + 0x0010)
+#define DATA_MGR_MEM_T_REFI				(BASE_DATA_MGR + 0x0014)
+#define DATA_MGR_MEM_T_WR				(BASE_DATA_MGR + 0x0018)
+#define DATA_MGR_MEM_T_MRD				(BASE_DATA_MGR + 0x001C)
+#define DATA_MGR_COL_WIDTH				(BASE_DATA_MGR + 0x0020)
+#define DATA_MGR_ROW_WIDTH				(BASE_DATA_MGR + 0x0024)
+#define DATA_MGR_BANK_WIDTH				(BASE_DATA_MGR + 0x0028)
+#define DATA_MGR_CS_WIDTH				(BASE_DATA_MGR + 0x002C)
+#define DATA_MGR_ITF_WIDTH				(BASE_DATA_MGR + 0x0030)
+#define DATA_MGR_DVC_WIDTH				(BASE_DATA_MGR + 0x0034)
+
+#define MEM_T_WL_ADD PHY_MGR_MEM_T_WL
+#define MEM_T_RL_ADD PHY_MGR_MEM_T_RL
+
+#define CALIB_SKIP_DELAY_LOOPS			(1 << 0)
+#define CALIB_SKIP_ALL_BITS_CHK			(1 << 1)
+#define CALIB_SKIP_DELAY_SWEEPS			(1 << 2)
+#define CALIB_SKIP_VFIFO				(1 << 3)
+#define CALIB_SKIP_LFIFO				(1 << 4)
+#define CALIB_SKIP_WLEVEL				(1 << 5)
+#define CALIB_SKIP_WRITES				(1 << 6)
+#define CALIB_SKIP_FULL_TEST			(1 << 7)
+#define CALIB_SKIP_ALL					(CALIB_SKIP_VFIFO | CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
+#define CALIB_IN_RTL_SIM				(1 << 8)
+
+// PHY Debug mode flag constants
+#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
+#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
+#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
+#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
+#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
+#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
+
+/* PLL manager command addresses */
+
+#define PLL_INCR(group)	IOWR_32DIRECT(BASE_PLL_MGR, group, 0x1)
+#define PLL_DECR(group)	IOWR_32DIRECT(BASE_PLL_MGR, group, 0x0)
+#define RTL_VFIFO_SIZE  8
+
+/* Bitfield type changes depending on protocol */
+typedef alt_u32 t_btfld;
+
+#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
+#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
+
+extern const alt_u32 inst_rom_init_size;
+extern const alt_u32 inst_rom_init[];
+extern const alt_u32 ac_rom_init_size;
+extern const alt_u32 ac_rom_init[];
+
+
+
+/* parameter variable holder */
+
+typedef struct param_type {
+	t_btfld dm_correct_mask;
+	t_btfld read_correct_mask;
+	t_btfld read_correct_mask_vg;
+	t_btfld write_correct_mask;
+	t_btfld write_correct_mask_vg;	
+
+	/* set a particular entry to 1 if we need to skip a particular rank */
+
+	alt_u32 skip_ranks[MAX_RANKS];
+
+	/* set a particular entry to 1 if we need to skip a particular group */
+
+	alt_u32 skip_groups;
+	
+	/* set a particular entry to 1 if the shadow register (which represents a set of ranks) needs to be skipped */
+	
+	alt_u32 skip_shadow_regs[NUM_SHADOW_REGS];
+
+} param_t;
+
+
+/* global variable holder */
+
+typedef struct gbl_type {
+
+	alt_u32 phy_debug_mode_flags;
+
+	/* current read latency */
+
+	alt_u32 curr_read_lat;
+	
+	/* current write latency */
+	
+	alt_u32 curr_write_lat;
+
+	/* error code */
+
+	alt_u32 error_substage;
+	alt_u32 error_stage;
+	alt_u32 error_group;
+
+	/* figure-of-merit in, figure-of-merit out */
+
+	alt_u32 fom_in;
+	alt_u32 fom_out;
+
+	//USER Number of RW Mgr NOP cycles between write command and write data
+#if MULTIPLE_AFI_WLAT
+	alt_u32 rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
+#endif
+	alt_u32 rw_wl_nop_cycles;
+} gbl_t;
+
+// External global variables
+extern gbl_t *gbl;
+extern param_t *param;
+
+// External functions
+alt_u32 rw_mgr_mem_calibrate_full_test (alt_u32 min_correct, t_btfld *bit_chk, alt_u32 test_dm);
+extern alt_u32 run_mem_calibrate (void);
+extern void rw_mgr_mem_calibrate_eye_diag_aid (void);
+extern void rw_mgr_load_mrs_calib (void);
+extern void rw_mgr_load_mrs_exec (void);
+extern void rw_mgr_mem_initialize (void);
+extern void rw_mgr_mem_dll_lock_wait(void);
+#if HPS_HW
+extern int sdram_calibration(void);
+#endif
+#endif
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_debug_uart.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_debug_uart.v
new file mode 100644
index 0000000..9806f9b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_debug_uart.v
@@ -0,0 +1,921 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_debug_uart_tx (
+                             // inputs:
+                              baud_divisor,
+                              begintransfer,
+                              clk,
+                              clk_en,
+                              do_force_break,
+                              reset_n,
+                              status_wr_strobe,
+                              tx_data,
+                              tx_wr_strobe,
+
+                             // outputs:
+                              tx_overrun,
+                              tx_ready,
+                              tx_shift_empty,
+                              txd
+                           )
+;
+
+  output           tx_overrun;
+  output           tx_ready;
+  output           tx_shift_empty;
+  output           txd;
+  input   [  8: 0] baud_divisor;
+  input            begintransfer;
+  input            clk;
+  input            clk_en;
+  input            do_force_break;
+  input            reset_n;
+  input            status_wr_strobe;
+  input   [  7: 0] tx_data;
+  input            tx_wr_strobe;
+
+
+reg              baud_clk_en;
+reg     [  8: 0] baud_rate_counter;
+wire             baud_rate_counter_is_zero;
+reg              do_load_shifter;
+wire             do_shift;
+reg              pre_txd;
+wire             shift_done;
+wire    [  9: 0] tx_load_val;
+reg              tx_overrun;
+reg              tx_ready;
+reg              tx_shift_empty;
+wire             tx_shift_reg_out;
+wire    [  9: 0] tx_shift_register_contents;
+wire             tx_wr_strobe_onset;
+reg              txd;
+wire    [  9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
+reg     [  9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
+  assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
+  assign tx_load_val = {{1 {1'b1}},
+    tx_data,
+    1'b0};
+
+  assign shift_done = ~(|tx_shift_register_contents);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_load_shifter <= 0;
+      else if (clk_en)
+          do_load_shifter <= (~tx_ready) && shift_done;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          tx_ready <= 1'b1;
+      else if (clk_en)
+          if (tx_wr_strobe_onset)
+              tx_ready <= 0;
+          else if (do_load_shifter)
+              tx_ready <= -1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          tx_overrun <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              tx_overrun <= 0;
+          else if (~tx_ready && tx_wr_strobe_onset)
+              tx_overrun <= -1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          tx_shift_empty <= 1'b1;
+      else if (clk_en)
+          tx_shift_empty <= tx_ready && shift_done;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          baud_rate_counter <= 0;
+      else if (clk_en)
+          if (baud_rate_counter_is_zero || do_load_shifter)
+              baud_rate_counter <= baud_divisor;
+          else 
+            baud_rate_counter <= baud_rate_counter - 1;
+    end
+
+
+  assign baud_rate_counter_is_zero = baud_rate_counter == 0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          baud_clk_en <= 0;
+      else if (clk_en)
+          baud_clk_en <= baud_rate_counter_is_zero;
+    end
+
+
+  assign do_shift = baud_clk_en  && 
+    (~shift_done) && 
+    (~do_load_shifter);
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          pre_txd <= 1;
+      else if (~shift_done)
+          pre_txd <= tx_shift_reg_out;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          txd <= 1;
+      else if (clk_en)
+          txd <= pre_txd & ~do_force_break;
+    end
+
+
+  //_reg, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= 0;
+      else if (clk_en)
+          unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
+    end
+
+
+  assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in = (do_load_shifter)? tx_load_val :
+    (do_shift)? {1'b0,
+    unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9 : 1]} :
+    unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
+
+  assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
+  assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0];
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_debug_uart_rx_stimulus_source (
+                                             // inputs:
+                                              baud_divisor,
+                                              clk,
+                                              clk_en,
+                                              reset_n,
+                                              rx_char_ready,
+                                              rxd,
+
+                                             // outputs:
+                                              source_rxd
+                                           )
+;
+
+  output           source_rxd;
+  input   [  8: 0] baud_divisor;
+  input            clk;
+  input            clk_en;
+  input            reset_n;
+  input            rx_char_ready;
+  input            rxd;
+
+
+reg     [  7: 0] d1_stim_data;
+reg              delayed_unxrx_char_readyxx0;
+wire             do_send_stim_data;
+wire             pickup_pulse;
+wire             source_rxd;
+wire    [  7: 0] stim_data;
+wire             unused_empty;
+wire             unused_overrun;
+wire             unused_ready;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  //stimulus_transmitter, which is an e_instance
+  q_sys_debug_uart_tx stimulus_transmitter
+    (
+      .baud_divisor     (baud_divisor),
+      .begintransfer    (do_send_stim_data),
+      .clk              (clk),
+      .clk_en           (clk_en),
+      .do_force_break   (1'b0),
+      .reset_n          (reset_n),
+      .status_wr_strobe (1'b0),
+      .tx_data          (d1_stim_data),
+      .tx_overrun       (unused_overrun),
+      .tx_ready         (unused_ready),
+      .tx_shift_empty   (unused_empty),
+      .tx_wr_strobe     (1'b1),
+      .txd              (source_rxd)
+    );
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d1_stim_data <= 0;
+      else if (do_send_stim_data)
+          d1_stim_data <= stim_data;
+    end
+
+
+  assign stim_data = 8'b0;
+  //delayed_unxrx_char_readyxx0, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxrx_char_readyxx0 <= 0;
+      else if (clk_en)
+          delayed_unxrx_char_readyxx0 <= rx_char_ready;
+    end
+
+
+  assign pickup_pulse = ~(rx_char_ready) &  (delayed_unxrx_char_readyxx0);
+  assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  assign source_rxd = rxd;
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_debug_uart_rx (
+                             // inputs:
+                              baud_divisor,
+                              begintransfer,
+                              clk,
+                              clk_en,
+                              reset_n,
+                              rx_rd_strobe,
+                              rxd,
+                              status_wr_strobe,
+
+                             // outputs:
+                              break_detect,
+                              framing_error,
+                              parity_error,
+                              rx_char_ready,
+                              rx_data,
+                              rx_overrun
+                           )
+;
+
+  output           break_detect;
+  output           framing_error;
+  output           parity_error;
+  output           rx_char_ready;
+  output  [  7: 0] rx_data;
+  output           rx_overrun;
+  input   [  8: 0] baud_divisor;
+  input            begintransfer;
+  input            clk;
+  input            clk_en;
+  input            reset_n;
+  input            rx_rd_strobe;
+  input            rxd;
+  input            status_wr_strobe;
+
+
+reg              baud_clk_en;
+wire    [  8: 0] baud_load_value;
+reg     [  8: 0] baud_rate_counter;
+wire             baud_rate_counter_is_zero;
+reg              break_detect;
+reg              delayed_unxrx_in_processxx3;
+reg              delayed_unxsync_rxdxx1;
+reg              delayed_unxsync_rxdxx2;
+reg              do_start_rx;
+reg              framing_error;
+wire             got_new_char;
+wire    [  7: 0] half_bit_cell_divisor;
+wire             is_break;
+wire             is_framing_error;
+wire             parity_error;
+wire    [  7: 0] raw_data_in;
+reg              rx_char_ready;
+reg     [  7: 0] rx_data;
+wire             rx_in_process;
+reg              rx_overrun;
+wire             rx_rd_strobe_onset;
+wire             rxd_edge;
+wire             rxd_falling;
+wire    [  9: 0] rxd_shift_reg;
+wire             sample_enable;
+wire             shift_reg_start_bit_n;
+wire             source_rxd;
+wire             stop_bit;
+wire             sync_rxd;
+wire             unused_start_bit;
+wire    [  9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
+reg     [  9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
+  q_sys_debug_uart_rx_stimulus_source the_q_sys_debug_uart_rx_stimulus_source
+    (
+      .baud_divisor  (baud_divisor),
+      .clk           (clk),
+      .clk_en        (clk_en),
+      .reset_n       (reset_n),
+      .rx_char_ready (rx_char_ready),
+      .rxd           (rxd),
+      .source_rxd    (source_rxd)
+    );
+
+  altera_std_synchronizer the_altera_std_synchronizer
+    (
+      .clk (clk),
+      .din (source_rxd),
+      .dout (sync_rxd),
+      .reset_n (reset_n)
+    );
+
+  defparam the_altera_std_synchronizer.depth = 2;
+
+  //delayed_unxsync_rxdxx1, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxsync_rxdxx1 <= 0;
+      else if (clk_en)
+          delayed_unxsync_rxdxx1 <= sync_rxd;
+    end
+
+
+  assign rxd_falling = ~(sync_rxd) &  (delayed_unxsync_rxdxx1);
+  //delayed_unxsync_rxdxx2, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxsync_rxdxx2 <= 0;
+      else if (clk_en)
+          delayed_unxsync_rxdxx2 <= sync_rxd;
+    end
+
+
+  assign rxd_edge = (sync_rxd) ^  (delayed_unxsync_rxdxx2);
+  assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
+  assign half_bit_cell_divisor = baud_divisor[8 : 1];
+  assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
+    baud_divisor;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          baud_rate_counter <= 0;
+      else if (clk_en)
+          if (baud_rate_counter_is_zero || rxd_edge)
+              baud_rate_counter <= baud_load_value;
+          else 
+            baud_rate_counter <= baud_rate_counter - 1;
+    end
+
+
+  assign baud_rate_counter_is_zero = baud_rate_counter == 0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          baud_clk_en <= 0;
+      else if (clk_en)
+          if (rxd_edge)
+              baud_clk_en <= 0;
+          else 
+            baud_clk_en <= baud_rate_counter_is_zero;
+    end
+
+
+  assign sample_enable = baud_clk_en && rx_in_process;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_start_rx <= 0;
+      else if (clk_en)
+          if (~rx_in_process && rxd_falling)
+              do_start_rx <= 1;
+          else 
+            do_start_rx <= 0;
+    end
+
+
+  assign rx_in_process = shift_reg_start_bit_n;
+  assign {stop_bit,
+raw_data_in,
+unused_start_bit} = rxd_shift_reg;
+  assign is_break = ~(|rxd_shift_reg);
+  assign is_framing_error = ~stop_bit && ~is_break;
+  //delayed_unxrx_in_processxx3, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxrx_in_processxx3 <= 0;
+      else if (clk_en)
+          delayed_unxrx_in_processxx3 <= rx_in_process;
+    end
+
+
+  assign got_new_char = ~(rx_in_process) &  (delayed_unxrx_in_processxx3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          rx_data <= 0;
+      else if (got_new_char)
+          rx_data <= raw_data_in;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          framing_error <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              framing_error <= 0;
+          else if (got_new_char && is_framing_error)
+              framing_error <= -1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          break_detect <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              break_detect <= 0;
+          else if (got_new_char && is_break)
+              break_detect <= -1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          rx_overrun <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              rx_overrun <= 0;
+          else if (got_new_char && rx_char_ready)
+              rx_overrun <= -1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          rx_char_ready <= 0;
+      else if (clk_en)
+          if (rx_rd_strobe_onset)
+              rx_char_ready <= 0;
+          else if (got_new_char)
+              rx_char_ready <= -1;
+    end
+
+
+  assign parity_error = 0;
+  //_reg, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0;
+      else if (clk_en)
+          unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
+    end
+
+
+  assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {10{1'b1}} :
+    (sample_enable)? {sync_rxd,
+    unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9 : 1]} :
+    unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
+
+  assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
+  assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_debug_uart_regs (
+                               // inputs:
+                                address,
+                                break_detect,
+                                chipselect,
+                                clk,
+                                clk_en,
+                                framing_error,
+                                parity_error,
+                                read_n,
+                                reset_n,
+                                rx_char_ready,
+                                rx_data,
+                                rx_overrun,
+                                tx_overrun,
+                                tx_ready,
+                                tx_shift_empty,
+                                write_n,
+                                writedata,
+
+                               // outputs:
+                                baud_divisor,
+                                dataavailable,
+                                do_force_break,
+                                irq,
+                                readdata,
+                                readyfordata,
+                                rx_rd_strobe,
+                                status_wr_strobe,
+                                tx_data,
+                                tx_wr_strobe
+                             )
+;
+
+  output  [  8: 0] baud_divisor;
+  output           dataavailable;
+  output           do_force_break;
+  output           irq;
+  output  [ 15: 0] readdata;
+  output           readyfordata;
+  output           rx_rd_strobe;
+  output           status_wr_strobe;
+  output  [  7: 0] tx_data;
+  output           tx_wr_strobe;
+  input   [  2: 0] address;
+  input            break_detect;
+  input            chipselect;
+  input            clk;
+  input            clk_en;
+  input            framing_error;
+  input            parity_error;
+  input            read_n;
+  input            reset_n;
+  input            rx_char_ready;
+  input   [  7: 0] rx_data;
+  input            rx_overrun;
+  input            tx_overrun;
+  input            tx_ready;
+  input            tx_shift_empty;
+  input            write_n;
+  input   [ 15: 0] writedata;
+
+
+wire             any_error;
+wire    [  8: 0] baud_divisor;
+reg     [  9: 0] control_reg;
+wire             control_wr_strobe;
+wire             cts_status_bit;
+reg              d1_rx_char_ready;
+reg              d1_tx_ready;
+wire             dataavailable;
+wire             dcts_status_bit;
+reg              delayed_unxtx_readyxx4;
+wire    [  8: 0] divisor_constant;
+wire             do_force_break;
+wire             do_write_char;
+wire             eop_status_bit;
+wire             ie_any_error;
+wire             ie_break_detect;
+wire             ie_framing_error;
+wire             ie_parity_error;
+wire             ie_rx_char_ready;
+wire             ie_rx_overrun;
+wire             ie_tx_overrun;
+wire             ie_tx_ready;
+wire             ie_tx_shift_empty;
+reg              irq;
+wire             qualified_irq;
+reg     [ 15: 0] readdata;
+wire             readyfordata;
+wire             rx_rd_strobe;
+wire    [ 15: 0] selected_read_data;
+wire    [ 12: 0] status_reg;
+wire             status_wr_strobe;
+reg     [  7: 0] tx_data;
+wire             tx_wr_strobe;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          readdata <= 0;
+      else if (clk_en)
+          readdata <= selected_read_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          irq <= 0;
+      else if (clk_en)
+          irq <= qualified_irq;
+    end
+
+
+  assign rx_rd_strobe = chipselect && ~read_n  && (address == 3'd0);
+  assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
+  assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
+  assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          tx_data <= 0;
+      else if (tx_wr_strobe)
+          tx_data <= writedata[7 : 0];
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          control_reg <= 0;
+      else if (control_wr_strobe)
+          control_reg <= writedata[9 : 0];
+    end
+
+
+  assign baud_divisor = divisor_constant;
+  assign cts_status_bit = 0;
+  assign dcts_status_bit = 0;
+  assign {do_force_break,
+ie_any_error,
+ie_rx_char_ready,
+ie_tx_ready,
+ie_tx_shift_empty,
+ie_tx_overrun,
+ie_rx_overrun,
+ie_break_detect,
+ie_framing_error,
+ie_parity_error} = control_reg;
+  assign any_error = tx_overrun ||
+    rx_overrun ||
+    parity_error ||
+    framing_error ||
+    break_detect;
+
+  assign status_reg = {eop_status_bit,
+    cts_status_bit,
+    dcts_status_bit,
+    1'b0,
+    any_error,
+    rx_char_ready,
+    tx_ready,
+    tx_shift_empty,
+    tx_overrun,
+    rx_overrun,
+    break_detect,
+    framing_error,
+    parity_error};
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d1_rx_char_ready <= 0;
+      else if (clk_en)
+          d1_rx_char_ready <= rx_char_ready;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d1_tx_ready <= 0;
+      else if (clk_en)
+          d1_tx_ready <= tx_ready;
+    end
+
+
+  assign dataavailable = d1_rx_char_ready;
+  assign readyfordata = d1_tx_ready;
+  assign eop_status_bit = 1'b0;
+  assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
+    ({16 {(address == 3'd1)}} & tx_data) |
+    ({16 {(address == 3'd2)}} & status_reg) |
+    ({16 {(address == 3'd3)}} & control_reg);
+
+  assign qualified_irq = (ie_any_error      && any_error      ) ||
+    (ie_tx_shift_empty && tx_shift_empty ) ||
+    (ie_tx_overrun     && tx_overrun     ) ||
+    (ie_rx_overrun     && rx_overrun     ) ||
+    (ie_break_detect   && break_detect   ) ||
+    (ie_framing_error  && framing_error  ) ||
+    (ie_parity_error   && parity_error   ) ||
+    (ie_rx_char_ready  && rx_char_ready  ) ||
+    (ie_tx_ready       && tx_ready       );
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  //delayed_unxtx_readyxx4, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxtx_readyxx4 <= 0;
+      else if (clk_en)
+          delayed_unxtx_readyxx4 <= tx_ready;
+    end
+
+
+  assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
+  always @(posedge clk)
+    begin
+      if (do_write_char)
+          $write("%c", tx_data);
+    end
+
+
+  assign divisor_constant = 4;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  assign divisor_constant = 434;
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_debug_uart (
+                          // inputs:
+                           address,
+                           begintransfer,
+                           chipselect,
+                           clk,
+                           read_n,
+                           reset_n,
+                           rxd,
+                           write_n,
+                           writedata,
+
+                          // outputs:
+                           dataavailable,
+                           irq,
+                           readdata,
+                           readyfordata,
+                           txd
+                        )
+  /* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
+
+  output           dataavailable;
+  output           irq;
+  output  [ 15: 0] readdata;
+  output           readyfordata;
+  output           txd;
+  input   [  2: 0] address;
+  input            begintransfer;
+  input            chipselect;
+  input            clk;
+  input            read_n;
+  input            reset_n;
+  input            rxd;
+  input            write_n;
+  input   [ 15: 0] writedata;
+
+
+wire    [  8: 0] baud_divisor;
+wire             break_detect;
+wire             clk_en;
+wire             dataavailable;
+wire             do_force_break;
+wire             framing_error;
+wire             irq;
+wire             parity_error;
+wire    [ 15: 0] readdata;
+wire             readyfordata;
+wire             rx_char_ready;
+wire    [  7: 0] rx_data;
+wire             rx_overrun;
+wire             rx_rd_strobe;
+wire             status_wr_strobe;
+wire    [  7: 0] tx_data;
+wire             tx_overrun;
+wire             tx_ready;
+wire             tx_shift_empty;
+wire             tx_wr_strobe;
+wire             txd;
+  assign clk_en = 1;
+  q_sys_debug_uart_tx the_q_sys_debug_uart_tx
+    (
+      .baud_divisor     (baud_divisor),
+      .begintransfer    (begintransfer),
+      .clk              (clk),
+      .clk_en           (clk_en),
+      .do_force_break   (do_force_break),
+      .reset_n          (reset_n),
+      .status_wr_strobe (status_wr_strobe),
+      .tx_data          (tx_data),
+      .tx_overrun       (tx_overrun),
+      .tx_ready         (tx_ready),
+      .tx_shift_empty   (tx_shift_empty),
+      .tx_wr_strobe     (tx_wr_strobe),
+      .txd              (txd)
+    );
+
+  q_sys_debug_uart_rx the_q_sys_debug_uart_rx
+    (
+      .baud_divisor     (baud_divisor),
+      .begintransfer    (begintransfer),
+      .break_detect     (break_detect),
+      .clk              (clk),
+      .clk_en           (clk_en),
+      .framing_error    (framing_error),
+      .parity_error     (parity_error),
+      .reset_n          (reset_n),
+      .rx_char_ready    (rx_char_ready),
+      .rx_data          (rx_data),
+      .rx_overrun       (rx_overrun),
+      .rx_rd_strobe     (rx_rd_strobe),
+      .rxd              (rxd),
+      .status_wr_strobe (status_wr_strobe)
+    );
+
+  q_sys_debug_uart_regs the_q_sys_debug_uart_regs
+    (
+      .address          (address),
+      .baud_divisor     (baud_divisor),
+      .break_detect     (break_detect),
+      .chipselect       (chipselect),
+      .clk              (clk),
+      .clk_en           (clk_en),
+      .dataavailable    (dataavailable),
+      .do_force_break   (do_force_break),
+      .framing_error    (framing_error),
+      .irq              (irq),
+      .parity_error     (parity_error),
+      .read_n           (read_n),
+      .readdata         (readdata),
+      .readyfordata     (readyfordata),
+      .reset_n          (reset_n),
+      .rx_char_ready    (rx_char_ready),
+      .rx_data          (rx_data),
+      .rx_overrun       (rx_overrun),
+      .rx_rd_strobe     (rx_rd_strobe),
+      .status_wr_strobe (status_wr_strobe),
+      .tx_data          (tx_data),
+      .tx_overrun       (tx_overrun),
+      .tx_ready         (tx_ready),
+      .tx_shift_empty   (tx_shift_empty),
+      .tx_wr_strobe     (tx_wr_strobe),
+      .write_n          (write_n),
+      .writedata        (writedata)
+    );
+
+  //s1, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_descriptor_memory.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_descriptor_memory.v
new file mode 100644
index 0000000..342ade5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_descriptor_memory.v
@@ -0,0 +1,86 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_descriptor_memory (
+                                 // inputs:
+                                  address,
+                                  byteenable,
+                                  chipselect,
+                                  clk,
+                                  clken,
+                                  freeze,
+                                  reset,
+                                  reset_req,
+                                  write,
+                                  writedata,
+
+                                 // outputs:
+                                  readdata
+                               )
+;
+
+  output  [ 31: 0] readdata;
+  input   [ 10: 0] address;
+  input   [  3: 0] byteenable;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+wire             clocken0;
+wire    [ 31: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 2048,
+           the_altsyncram.numwords_a = 2048,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 11;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_enet_pll.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_enet_pll.v
new file mode 100644
index 0000000..9779235
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_enet_pll.v
@@ -0,0 +1,343 @@
+//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 c4 clk configupdate locked phasecounterselect phasedone phasestep phaseupdown read readdata reset scanclk scanclkena scandata write writedata bandwidth_type="AUTO" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" clk2_divide_by=20 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=5 clk3_phase_shift="-3000" clk4_divide_by=2 clk4_duty_cycle=50 clk4_multiply_by=1 clk4_phase_shift="-10000" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="no_compensation" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_USED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
+//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_altiobuf_bidir 2019:09:22:08:02:34:SJ cbx_altiobuf_in 2019:09:22:08:02:34:SJ cbx_altiobuf_out 2019:09:22:08:02:34:SJ cbx_altpll 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_counter 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_lpm_shiftreg 2019:09:22:08:02:34:SJ cbx_max10_altpll_avalon 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+
+//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
+//VERSION_BEGIN 19.1 cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+
+//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 19.1 cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+//synthesis_resources = reg 3 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
+module  q_sys_enet_pll_dffpipe_l2c
+	( 
+	clock,
+	clrn,
+	d,
+	q) /* synthesis synthesis_clearbox=1 */;
+	input   clock;
+	input   clrn;
+	input   [0:0]  d;
+	output   [0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   clock;
+	tri1   clrn;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	reg	[0:0]	dffe4a;
+	reg	[0:0]	dffe5a;
+	reg	[0:0]	dffe6a;
+	wire ena;
+	wire prn;
+	wire sclr;
+
+	// synopsys translate_off
+	initial
+		dffe4a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe4a <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a <= (d & (~ sclr));
+	// synopsys translate_off
+	initial
+		dffe5a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe5a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe5a <= 1'b0;
+		else if  (ena == 1'b1)   dffe5a <= (dffe4a & (~ sclr));
+	// synopsys translate_off
+	initial
+		dffe6a = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a <= {1{1'b1}};
+		else if (clrn == 1'b0) dffe6a <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a <= (dffe5a & (~ sclr));
+	assign
+		ena = 1'b1,
+		prn = 1'b1,
+		q = dffe6a,
+		sclr = 1'b0;
+endmodule //q_sys_enet_pll_dffpipe_l2c
+
+//synthesis_resources = reg 3 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_enet_pll_stdsync_sv6
+	( 
+	clk,
+	din,
+	dout,
+	reset_n) /* synthesis synthesis_clearbox=1 */;
+	input   clk;
+	input   din;
+	output   dout;
+	input   reset_n;
+
+	wire  [0:0]   wire_dffpipe3_q;
+
+	q_sys_enet_pll_dffpipe_l2c   dffpipe3
+	( 
+	.clock(clk),
+	.clrn(reset_n),
+	.d(din),
+	.q(wire_dffpipe3_q));
+	assign
+		dout = wire_dffpipe3_q;
+endmodule //q_sys_enet_pll_stdsync_sv6
+
+
+//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" clk2_divide_by=20 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=5 clk3_phase_shift="-3000" clk4_divide_by=2 clk4_duty_cycle=50 clk4_multiply_by=1 clk4_phase_shift="-10000" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="no_compensation" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_USED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
+//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_altiobuf_bidir 2019:09:22:08:02:34:SJ cbx_altiobuf_in 2019:09:22:08:02:34:SJ cbx_altiobuf_out 2019:09:22:08:02:34:SJ cbx_altpll 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_counter 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+
+//synthesis_resources = fiftyfivenm_pll 1 reg 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
+module  q_sys_enet_pll_altpll_7cu2
+	( 
+	areset,
+	clk,
+	inclk,
+	locked) /* synthesis synthesis_clearbox=1 */;
+	input   areset;
+	output   [4:0]  clk;
+	input   [1:0]  inclk;
+	output   locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   areset;
+	tri0   [1:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	reg	pll_lock_sync;
+	wire  [4:0]   wire_pll7_clk;
+	wire  wire_pll7_fbout;
+	wire  wire_pll7_locked;
+
+	// synopsys translate_off
+	initial
+		pll_lock_sync = 0;
+	// synopsys translate_on
+	always @ ( posedge wire_pll7_locked or  posedge areset)
+		if (areset == 1'b1) pll_lock_sync <= 1'b0;
+		else  pll_lock_sync <= 1'b1;
+	fiftyfivenm_pll   pll7
+	( 
+	.activeclock(),
+	.areset(areset),
+	.clk(wire_pll7_clk),
+	.clkbad(),
+	.fbin(wire_pll7_fbout),
+	.fbout(wire_pll7_fbout),
+	.inclk(inclk),
+	.locked(wire_pll7_locked),
+	.phasedone(),
+	.scandataout(),
+	.scandone(),
+	.vcooverrange(),
+	.vcounderrange()
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.clkswitch(1'b0),
+	.configupdate(1'b0),
+	.pfdena(1'b1),
+	.phasecounterselect({3{1'b0}}),
+	.phasestep(1'b0),
+	.phaseupdown(1'b0),
+	.scanclk(1'b0),
+	.scanclkena(1'b1),
+	.scandata(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pll7.bandwidth_type = "auto",
+		pll7.clk0_divide_by = 2,
+		pll7.clk0_duty_cycle = 50,
+		pll7.clk0_multiply_by = 5,
+		pll7.clk0_phase_shift = "0",
+		pll7.clk1_divide_by = 2,
+		pll7.clk1_duty_cycle = 50,
+		pll7.clk1_multiply_by = 1,
+		pll7.clk1_phase_shift = "0",
+		pll7.clk2_divide_by = 20,
+		pll7.clk2_duty_cycle = 50,
+		pll7.clk2_multiply_by = 1,
+		pll7.clk2_phase_shift = "0",
+		pll7.clk3_divide_by = 2,
+		pll7.clk3_duty_cycle = 50,
+		pll7.clk3_multiply_by = 5,
+		pll7.clk3_phase_shift = "-3000",
+		pll7.clk4_divide_by = 2,
+		pll7.clk4_duty_cycle = 50,
+		pll7.clk4_multiply_by = 1,
+		pll7.clk4_phase_shift = "-10000",
+		pll7.compensate_clock = "clk0",
+		pll7.inclk0_input_frequency = 20000,
+		pll7.operation_mode = "no_compensation",
+		pll7.pll_type = "auto",
+		pll7.lpm_type = "fiftyfivenm_pll";
+	assign
+		clk = {wire_pll7_clk[4:0]},
+		locked = (wire_pll7_locked & pll_lock_sync);
+endmodule //q_sys_enet_pll_altpll_7cu2
+
+//synthesis_resources = fiftyfivenm_pll 1 reg 6 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_enet_pll
+	( 
+	address,
+	areset,
+	c0,
+	c1,
+	c2,
+	c3,
+	c4,
+	clk,
+	configupdate,
+	locked,
+	phasecounterselect,
+	phasedone,
+	phasestep,
+	phaseupdown,
+	read,
+	readdata,
+	reset,
+	scanclk,
+	scanclkena,
+	scandata,
+	scandataout,
+	scandone,
+	write,
+	writedata) /* synthesis synthesis_clearbox=1 */;
+	input   [1:0]  address;
+	input   areset;
+	output   c0;
+	output   c1;
+	output   c2;
+	output   c3;
+	output   c4;
+	input   clk;
+	input   configupdate;
+	output   locked;
+	input   [2:0]  phasecounterselect;
+	output   phasedone;
+	input   phasestep;
+	input   phaseupdown;
+	input   read;
+	output   [31:0]  readdata;
+	input   reset;
+	input   scanclk;
+	input   scanclkena;
+	input   scandata;
+	output   scandataout;
+	output   scandone;
+	input   write;
+	input   [31:0]  writedata;
+
+	wire  wire_stdsync2_dout;
+	wire  [4:0]   wire_sd1_clk;
+	wire  wire_sd1_locked;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+	reg	pfdena_reg;
+	wire	wire_pfdena_reg_ena;
+	reg	prev_reset;
+	wire  w_locked;
+	wire  w_pfdena;
+	wire  w_phasedone;
+	wire  w_pll_areset_in;
+	wire  w_reset;
+	wire  w_select_control;
+	wire  w_select_status;
+
+	q_sys_enet_pll_stdsync_sv6   stdsync2
+	( 
+	.clk(clk),
+	.din(wire_sd1_locked),
+	.dout(wire_stdsync2_dout),
+	.reset_n((~ reset)));
+	q_sys_enet_pll_altpll_7cu2   sd1
+	( 
+	.areset((w_pll_areset_in | areset)),
+	.clk(wire_sd1_clk),
+	.inclk({{1{1'b0}}, clk}),
+	.locked(wire_sd1_locked));
+	// synopsys translate_off
+	initial
+		pfdena_reg = {1{1'b1}};
+	// synopsys translate_on
+	always @ ( posedge clk or  posedge reset)
+		if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
+		else if  (wire_pfdena_reg_ena == 1'b1)   pfdena_reg <= writedata[1];
+	assign
+		wire_pfdena_reg_ena = (write & w_select_control);
+	// synopsys translate_off
+	initial
+		prev_reset = 0;
+	// synopsys translate_on
+	always @ ( posedge clk or  posedge reset)
+		if (reset == 1'b1) prev_reset <= 1'b0;
+		else  prev_reset <= w_reset;
+	assign
+		c0 = wire_sd1_clk[0],
+		c1 = wire_sd1_clk[1],
+		c2 = wire_sd1_clk[2],
+		c3 = wire_sd1_clk[3],
+		c4 = wire_sd1_clk[4],
+		locked = wire_sd1_locked,
+		phasedone = 1'b0,
+		readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
+		scandataout = 1'b0,
+		scandone = 1'b0,
+		w_locked = wire_stdsync2_dout,
+		w_pfdena = pfdena_reg,
+		w_phasedone = 1'b1,
+		w_pll_areset_in = prev_reset,
+		w_reset = ((write & w_select_control) & writedata[0]),
+		w_select_control = ((~ address[1]) & address[0]),
+		w_select_status = ((~ address[1]) & (~ address[0]));
+endmodule //q_sys_enet_pll
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_eth_tse.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_eth_tse.v
new file mode 100644
index 0000000..401f352
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_eth_tse.v
@@ -0,0 +1,406 @@
+// q_sys_eth_tse.v
+
+// This file was auto-generated from altera_eth_tse_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_eth_tse (
+		input  wire        clk,           // control_port_clock_connection.clk
+		input  wire        reset,         //              reset_connection.reset
+		input  wire [7:0]  reg_addr,      //                  control_port.address
+		output wire [31:0] reg_data_out,  //                              .readdata
+		input  wire        reg_rd,        //                              .read
+		input  wire [31:0] reg_data_in,   //                              .writedata
+		input  wire        reg_wr,        //                              .write
+		output wire        reg_busy,      //                              .waitrequest
+		input  wire        tx_clk,        //   pcs_mac_tx_clock_connection.clk
+		input  wire        rx_clk,        //   pcs_mac_rx_clock_connection.clk
+		input  wire        set_10,        //         mac_status_connection.set_10
+		input  wire        set_1000,      //                              .set_1000
+		output wire        eth_mode,      //                              .eth_mode
+		output wire        ena_10,        //                              .ena_10
+		input  wire [3:0]  rgmii_in,      //          mac_rgmii_connection.rgmii_in
+		output wire [3:0]  rgmii_out,     //                              .rgmii_out
+		input  wire        rx_control,    //                              .rx_control
+		output wire        tx_control,    //                              .tx_control
+		input  wire        ff_rx_clk,     //      receive_clock_connection.clk
+		input  wire        ff_tx_clk,     //     transmit_clock_connection.clk
+		output wire [31:0] ff_rx_data,    //                       receive.data
+		output wire        ff_rx_eop,     //                              .endofpacket
+		output wire [5:0]  rx_err,        //                              .error
+		output wire [1:0]  ff_rx_mod,     //                              .empty
+		input  wire        ff_rx_rdy,     //                              .ready
+		output wire        ff_rx_sop,     //                              .startofpacket
+		output wire        ff_rx_dval,    //                              .valid
+		input  wire [31:0] ff_tx_data,    //                      transmit.data
+		input  wire        ff_tx_eop,     //                              .endofpacket
+		input  wire        ff_tx_err,     //                              .error
+		input  wire [1:0]  ff_tx_mod,     //                              .empty
+		output wire        ff_tx_rdy,     //                              .ready
+		input  wire        ff_tx_sop,     //                              .startofpacket
+		input  wire        ff_tx_wren,    //                              .valid
+		output wire        mdc,           //           mac_mdio_connection.mdc
+		input  wire        mdio_in,       //                              .mdio_in
+		output wire        mdio_out,      //                              .mdio_out
+		output wire        mdio_oen,      //                              .mdio_oen
+		output wire        magic_wakeup,  //           mac_misc_connection.magic_wakeup
+		input  wire        magic_sleep_n, //                              .magic_sleep_n
+		input  wire        ff_tx_crc_fwd, //                              .ff_tx_crc_fwd
+		output wire        ff_tx_septy,   //                              .ff_tx_septy
+		output wire        tx_ff_uflow,   //                              .tx_ff_uflow
+		output wire        ff_tx_a_full,  //                              .ff_tx_a_full
+		output wire        ff_tx_a_empty, //                              .ff_tx_a_empty
+		output wire [17:0] rx_err_stat,   //                              .rx_err_stat
+		output wire [3:0]  rx_frm_type,   //                              .rx_frm_type
+		output wire        ff_rx_dsav,    //                              .ff_rx_dsav
+		output wire        ff_rx_a_full,  //                              .ff_rx_a_full
+		output wire        ff_rx_a_empty  //                              .ff_rx_a_empty
+	);
+
+	wire  [3:0] i_tse_mac_rgmii_in4_pad_export;   // i_tse_mac:rgmii_in4_pad -> rgmii_in4_0:pad_in
+	wire  [7:0] rgmii_in4_0_dout_export;          // rgmii_in4_0:dout -> i_tse_mac:rgmii_in4_dout
+	wire        i_tse_mac_rgmii_in4_ck_export;    // i_tse_mac:rgmii_in4_ck -> rgmii_in4_0:inclock
+	wire        i_tse_mac_rgmii_in1_pad_export;   // i_tse_mac:rgmii_in1_pad -> rgmii_in1_0:pad_in
+	wire  [1:0] rgmii_in1_0_dout_export;          // rgmii_in1_0:dout -> i_tse_mac:rgmii_in1_dout
+	wire        i_tse_mac_rgmii_in1_ck_export;    // i_tse_mac:rgmii_in1_ck -> rgmii_in1_0:inclock
+	wire  [3:0] rgmii_out4_0_pad_out_export;      // rgmii_out4_0:pad_out -> i_tse_mac:rgmii_out4_pad
+	wire  [7:0] i_tse_mac_rgmii_out4_din_export;  // i_tse_mac:rgmii_out4_din -> rgmii_out4_0:din
+	wire        i_tse_mac_rgmii_out4_ck_export;   // i_tse_mac:rgmii_out4_ck -> rgmii_out4_0:outclock
+	wire        i_tse_mac_rgmii_out4_aclr_export; // i_tse_mac:rgmii_out4_aclr -> rgmii_out4_0:aclr
+	wire  [0:0] rgmii_out1_0_pad_out_export;      // rgmii_out1_0:pad_out -> i_tse_mac:rgmii_out1_pad
+	wire  [1:0] i_tse_mac_rgmii_out1_din_export;  // i_tse_mac:rgmii_out1_din -> rgmii_out1_0:din
+	wire        i_tse_mac_rgmii_out1_ck_export;   // i_tse_mac:rgmii_out1_ck -> rgmii_out1_0:outclock
+	wire        i_tse_mac_rgmii_out1_aclr_export; // i_tse_mac:rgmii_out1_aclr -> rgmii_out1_0:aclr
+
+	altera_eth_tse_mac #(
+		.ING_ADDR                 (11),
+		.ENABLE_MAC_RX_VLAN       (0),
+		.ENABLE_SUP_ADDR          (0),
+		.DEVICE_FAMILY            ("MAX10"),
+		.INSERT_TA                (0),
+		.ING_FIFO                 (2048),
+		.ENABLE_ECC               (0),
+		.CRC32DWIDTH              (8),
+		.ENABLE_ENA               (32),
+		.SYNCHRONIZER_DEPTH       (3),
+		.ENABLE_MAC_TX_VLAN       (0),
+		.RESET_LEVEL              (1),
+		.STAT_CNT_ENA             (1),
+		.CUST_VERSION             (0),
+		.CRC32S1L2_EXTERN         (0),
+		.MBIT_ONLY                (1),
+		.EG_ADDR                  (11),
+		.CORE_VERSION             (4865),
+		.CRC32GENDELAY            (6),
+		.EG_FIFO                  (2048),
+		.REDUCED_INTERFACE_ENA    (1),
+		.ENABLE_MAGIC_DETECT      (1),
+		.ENABLE_MDIO              (1),
+		.ENABLE_MAC_TXADDR_SET    (1),
+		.RAM_TYPE                 ("AUTO"),
+		.CRC32CHECK16BIT          (0),
+		.ENABLE_LGTH_CHECK        (1),
+		.ENABLE_MAC_FLOW_CTRL     (0),
+		.ENABLE_SHIFT16           (1),
+		.USE_SYNC_RESET           (1),
+		.REDUCED_CONTROL          (0),
+		.MDIO_CLK_DIV             (40),
+		.ENABLE_PADDING           (1),
+		.ENABLE_GMII_LOOPBACK     (1),
+		.GBIT_ONLY                (1),
+		.ENA_HASH                 (0),
+		.ENABLE_EXTENDED_STAT_REG (0),
+		.ENABLE_HD_LOGIC          (1)
+	) i_tse_mac (
+		.clk             (clk),                              // control_port_clock_connection.clk
+		.reset           (reset),                            //              reset_connection.reset
+		.reg_addr        (reg_addr),                         //                  control_port.address
+		.reg_data_out    (reg_data_out),                     //                              .readdata
+		.reg_rd          (reg_rd),                           //                              .read
+		.reg_data_in     (reg_data_in),                      //                              .writedata
+		.reg_wr          (reg_wr),                           //                              .write
+		.reg_busy        (reg_busy),                         //                              .waitrequest
+		.ff_tx_clk       (ff_tx_clk),                        //     transmit_clock_connection.clk
+		.ff_rx_clk       (ff_rx_clk),                        //      receive_clock_connection.clk
+		.ff_rx_data      (ff_rx_data),                       //                       receive.data
+		.ff_rx_eop       (ff_rx_eop),                        //                              .endofpacket
+		.rx_err          (rx_err),                           //                              .error
+		.ff_rx_mod       (ff_rx_mod),                        //                              .empty
+		.ff_rx_rdy       (ff_rx_rdy),                        //                              .ready
+		.ff_rx_sop       (ff_rx_sop),                        //                              .startofpacket
+		.ff_rx_dval      (ff_rx_dval),                       //                              .valid
+		.ff_tx_data      (ff_tx_data),                       //                      transmit.data
+		.ff_tx_eop       (ff_tx_eop),                        //                              .endofpacket
+		.ff_tx_err       (ff_tx_err),                        //                              .error
+		.ff_tx_mod       (ff_tx_mod),                        //                              .empty
+		.ff_tx_rdy       (ff_tx_rdy),                        //                              .ready
+		.ff_tx_sop       (ff_tx_sop),                        //                              .startofpacket
+		.ff_tx_wren      (ff_tx_wren),                       //                              .valid
+		.magic_wakeup    (magic_wakeup),                     //           mac_misc_connection.export
+		.magic_sleep_n   (magic_sleep_n),                    //                              .export
+		.ff_tx_crc_fwd   (ff_tx_crc_fwd),                    //                              .export
+		.ff_tx_septy     (ff_tx_septy),                      //                              .export
+		.tx_ff_uflow     (tx_ff_uflow),                      //                              .export
+		.ff_tx_a_full    (ff_tx_a_full),                     //                              .export
+		.ff_tx_a_empty   (ff_tx_a_empty),                    //                              .export
+		.rx_err_stat     (rx_err_stat),                      //                              .export
+		.rx_frm_type     (rx_frm_type),                      //                              .export
+		.ff_rx_dsav      (ff_rx_dsav),                       //                              .export
+		.ff_rx_a_full    (ff_rx_a_full),                     //                              .export
+		.ff_rx_a_empty   (ff_rx_a_empty),                    //                              .export
+		.mdc             (mdc),                              //           mac_mdio_connection.mdc
+		.mdio_in         (mdio_in),                          //                              .mdio_in
+		.mdio_out        (mdio_out),                         //                              .mdio_out
+		.mdio_oen        (mdio_oen),                         //                              .mdio_oen
+		.rgmii_out1_aclr (i_tse_mac_rgmii_out1_aclr_export), //               rgmii_out1_aclr.export
+		.rgmii_out1_din  (i_tse_mac_rgmii_out1_din_export),  //                rgmii_out1_din.export
+		.rgmii_in1_dout  (rgmii_in1_0_dout_export),          //                rgmii_in1_dout.export
+		.rgmii_in1_ck    (i_tse_mac_rgmii_in1_ck_export),    //                  rgmii_in1_ck.export
+		.rgmii_out4_din  (i_tse_mac_rgmii_out4_din_export),  //                rgmii_out4_din.export
+		.rgmii_out4_ck   (i_tse_mac_rgmii_out4_ck_export),   //                 rgmii_out4_ck.export
+		.rgmii_in1_pad   (i_tse_mac_rgmii_in1_pad_export),   //                 rgmii_in1_pad.export
+		.rgmii_out4_aclr (i_tse_mac_rgmii_out4_aclr_export), //               rgmii_out4_aclr.export
+		.rgmii_out1_pad  (rgmii_out1_0_pad_out_export),      //                rgmii_out1_pad.export
+		.rgmii_out1_ck   (i_tse_mac_rgmii_out1_ck_export),   //                 rgmii_out1_ck.export
+		.rgmii_in4_dout  (rgmii_in4_0_dout_export),          //                rgmii_in4_dout.export
+		.rgmii_in4_pad   (i_tse_mac_rgmii_in4_pad_export),   //                 rgmii_in4_pad.export
+		.rgmii_out4_pad  (rgmii_out4_0_pad_out_export),      //                rgmii_out4_pad.export
+		.rgmii_in4_ck    (i_tse_mac_rgmii_in4_ck_export),    //                  rgmii_in4_ck.export
+		.rgmii_in        (rgmii_in),                         //          mac_rgmii_connection.rgmii_in
+		.rgmii_out       (rgmii_out),                        //                              .rgmii_out
+		.rx_control      (rx_control),                       //                              .rx_control
+		.tx_control      (tx_control),                       //                              .tx_control
+		.set_10          (set_10),                           //         mac_status_connection.set_10
+		.set_1000        (set_1000),                         //                              .set_1000
+		.eth_mode        (eth_mode),                         //                              .eth_mode
+		.ena_10          (ena_10),                           //                              .ena_10
+		.tx_clk          (tx_clk),                           //   pcs_mac_tx_clock_connection.clk
+		.rx_clk          (rx_clk),                           //   pcs_mac_rx_clock_connection.clk
+		.rx_clkena       (1'b1),                             //                   (terminated)
+		.tx_clkena       (1'b1),                             //                   (terminated)
+		.xon_gen         (1'b0),                             //                   (terminated)
+		.xoff_gen        (1'b0),                             //                   (terminated)
+		.mac_eccstatus   (),                                 //                   (terminated)
+		.gm_rx_d         (8'b00000000),                      //                   (terminated)
+		.gm_rx_dv        (1'b0),                             //                   (terminated)
+		.gm_rx_err       (1'b0),                             //                   (terminated)
+		.gm_tx_d         (),                                 //                   (terminated)
+		.gm_tx_en        (),                                 //                   (terminated)
+		.gm_tx_err       (),                                 //                   (terminated)
+		.m_rx_d          (4'b0000),                          //                   (terminated)
+		.m_rx_en         (1'b0),                             //                   (terminated)
+		.m_rx_err        (1'b0),                             //                   (terminated)
+		.m_tx_d          (),                                 //                   (terminated)
+		.m_tx_en         (),                                 //                   (terminated)
+		.m_tx_err        (),                                 //                   (terminated)
+		.m_rx_crs        (1'b0),                             //                   (terminated)
+		.m_rx_col        (1'b0)                              //                   (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("input"),
+		.SIZE                                     (4),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("none"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_in4_0 (
+		.inclock         (i_tse_mac_rgmii_in4_ck_export),  // inclock.export
+		.dout            (rgmii_in4_0_dout_export),        //    dout.export
+		.pad_in          (i_tse_mac_rgmii_in4_pad_export), //  pad_in.export
+		.inclocken       (1'b1),                           // (terminated)
+		.fr_clock        (),                               // (terminated)
+		.hr_clock        (),                               // (terminated)
+		.invert_hr_clock (1'b0),                           // (terminated)
+		.outclock        (1'b0),                           // (terminated)
+		.outclocken      (1'b0),                           // (terminated)
+		.phy_mem_clock   (1'b0),                           // (terminated)
+		.mimic_clock     (),                               // (terminated)
+		.din             (8'b00000000),                    // (terminated)
+		.pad_io          (),                               // (terminated)
+		.pad_io_b        (),                               // (terminated)
+		.pad_in_b        (4'b0000),                        // (terminated)
+		.pad_out         (),                               // (terminated)
+		.pad_out_b       (),                               // (terminated)
+		.aset            (1'b0),                           // (terminated)
+		.aclr            (1'b0),                           // (terminated)
+		.sclr            (1'b0),                           // (terminated)
+		.nsleep          (4'b0000),                        // (terminated)
+		.oe              (4'b0000)                         // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("input"),
+		.SIZE                                     (1),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("none"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_in1_0 (
+		.inclock         (i_tse_mac_rgmii_in1_ck_export),  // inclock.export
+		.dout            (rgmii_in1_0_dout_export),        //    dout.export
+		.pad_in          (i_tse_mac_rgmii_in1_pad_export), //  pad_in.export
+		.inclocken       (1'b1),                           // (terminated)
+		.fr_clock        (),                               // (terminated)
+		.hr_clock        (),                               // (terminated)
+		.invert_hr_clock (1'b0),                           // (terminated)
+		.outclock        (1'b0),                           // (terminated)
+		.outclocken      (1'b0),                           // (terminated)
+		.phy_mem_clock   (1'b0),                           // (terminated)
+		.mimic_clock     (),                               // (terminated)
+		.din             (2'b00),                          // (terminated)
+		.pad_io          (),                               // (terminated)
+		.pad_io_b        (),                               // (terminated)
+		.pad_in_b        (1'b0),                           // (terminated)
+		.pad_out         (),                               // (terminated)
+		.pad_out_b       (),                               // (terminated)
+		.aset            (1'b0),                           // (terminated)
+		.aclr            (1'b0),                           // (terminated)
+		.sclr            (1'b0),                           // (terminated)
+		.nsleep          (1'b0),                           // (terminated)
+		.oe              (1'b0)                            // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("output"),
+		.SIZE                                     (4),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("clear"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_out4_0 (
+		.outclock        (i_tse_mac_rgmii_out4_ck_export),   // outclock.export
+		.din             (i_tse_mac_rgmii_out4_din_export),  //      din.export
+		.pad_out         (rgmii_out4_0_pad_out_export),      //  pad_out.export
+		.aclr            (i_tse_mac_rgmii_out4_aclr_export), //     aclr.export
+		.outclocken      (1'b1),                             // (terminated)
+		.inclock         (1'b0),                             // (terminated)
+		.inclocken       (1'b0),                             // (terminated)
+		.fr_clock        (),                                 // (terminated)
+		.hr_clock        (),                                 // (terminated)
+		.invert_hr_clock (1'b0),                             // (terminated)
+		.phy_mem_clock   (1'b0),                             // (terminated)
+		.mimic_clock     (),                                 // (terminated)
+		.dout            (),                                 // (terminated)
+		.pad_io          (),                                 // (terminated)
+		.pad_io_b        (),                                 // (terminated)
+		.pad_in          (4'b0000),                          // (terminated)
+		.pad_in_b        (4'b0000),                          // (terminated)
+		.pad_out_b       (),                                 // (terminated)
+		.aset            (1'b0),                             // (terminated)
+		.sclr            (1'b0),                             // (terminated)
+		.nsleep          (4'b0000),                          // (terminated)
+		.oe              (4'b0000)                           // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("output"),
+		.SIZE                                     (1),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("clear"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_out1_0 (
+		.outclock        (i_tse_mac_rgmii_out1_ck_export),   // outclock.export
+		.din             (i_tse_mac_rgmii_out1_din_export),  //      din.export
+		.pad_out         (rgmii_out1_0_pad_out_export),      //  pad_out.export
+		.aclr            (i_tse_mac_rgmii_out1_aclr_export), //     aclr.export
+		.outclocken      (1'b1),                             // (terminated)
+		.inclock         (1'b0),                             // (terminated)
+		.inclocken       (1'b0),                             // (terminated)
+		.fr_clock        (),                                 // (terminated)
+		.hr_clock        (),                                 // (terminated)
+		.invert_hr_clock (1'b0),                             // (terminated)
+		.phy_mem_clock   (1'b0),                             // (terminated)
+		.mimic_clock     (),                                 // (terminated)
+		.dout            (),                                 // (terminated)
+		.pad_io          (),                                 // (terminated)
+		.pad_io_b        (),                                 // (terminated)
+		.pad_in          (1'b0),                             // (terminated)
+		.pad_in_b        (1'b0),                             // (terminated)
+		.pad_out_b       (),                                 // (terminated)
+		.aset            (1'b0),                             // (terminated)
+		.sclr            (1'b0),                             // (terminated)
+		.nsleep          (1'b0),                             // (terminated)
+		.oe              (1'b0)                              // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash.sv
new file mode 100644
index 0000000..ebc281f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash.sv
@@ -0,0 +1,212 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+`timescale 1ps / 1ps
+
+module q_sys_ext_flash #(
+	parameter CS_WIDTH		= 1,
+	parameter IO_MODE		= "STANDARD",
+	parameter DEVICE_FAMILY         = "Arria V",
+	parameter ASI_WIDTH		= 4,
+	parameter ADDR_WIDTH	        = 24,
+	parameter ENABLE_4BYTE_ADDR     = 1,
+	parameter ASMI_ADDR_WIDTH       = 22,
+	parameter CHIP_SELS             = 1
+)(
+	input   wire                                    clk,
+	input   wire                                    reset_n,
+	                                                	
+	// ports to access csr                          		
+	input   wire                                    avl_csr_write,
+	input   wire                                    avl_csr_read,
+	input   wire    [2:0]                           avl_csr_addr,
+	input   wire    [31:0]                          avl_csr_wrdata,
+	output  wire    [31:0]                          avl_csr_rddata,
+	output  wire                                    avl_csr_rddata_valid,
+	output  wire                                    avl_csr_waitrequest,
+	                                                	
+	// ports to access memory                       
+	input   wire                                    avl_mem_write,
+	input   wire                                    avl_mem_read,
+	input   wire    [ADDR_WIDTH-1:0]                avl_mem_addr,			
+	input   wire    [31:0]                          avl_mem_wrdata,
+	input   wire    [6:0]                           avl_mem_burstcount,
+	input   wire    [3:0]                           avl_mem_byteenable,
+	output  wire    [31:0]                          avl_mem_rddata,
+	output  wire                                    avl_mem_rddata_valid,
+	output  wire                                    avl_mem_waitrequest,
+                                                    
+	// ports connecting to memory                   
+	inout	wire    [3:0]                           flash_dataout,
+	output  wire                                    flash_dclk_out,
+	output  wire    [CS_WIDTH-1:0]                  flash_ncs,
+                                                    
+	// interrupt signal                             
+	output	reg                                     irq
+);
+
+    wire                                            epcq_dclk;    
+    wire    [CS_WIDTH-1:0]                          epcq_scein;   
+    wire    [3:0]                                   epcq_sdoin;   
+    wire    [3:0]                                   epcq_dataoe;  
+    wire    [3:0]                                   ddasi_dataoe;
+    wire    [3:0]                                   ddasi_dataout;
+    wire                                            ddasi_dclk;
+    wire    [CS_WIDTH-1:0]                          ddasi_scein;
+    wire    [3:0]                                   ddasi_sdoin;
+    wire                                            asmi_busy;
+    wire                                            asmi_data_valid;
+    wire    [7:0]                                   asmi_dataout;
+    wire                                            asmi_clkin;
+    wire                                            asmi_reset;
+    wire    [ASMI_ADDR_WIDTH-1:0]                   asmi_addr;
+    wire    [7:0]                                   asmi_datain;
+    wire                                            asmi_fast_read;
+    wire                                            asmi_rden;
+    wire                                            asmi_shift_bytes;
+    wire                                            asmi_wren;
+    wire                                            asmi_write;
+                                                       
+    wire                                            asmi_illegal_erase;
+    wire                                            asmi_illegal_write;
+    wire    [7:0]                                   asmi_rdid_out;
+    wire    [7:0]                                   asmi_status_out;
+    wire                                            asmi_read_rdid;
+    wire                                            asmi_read_status;
+    wire                                            asmi_read_sid;
+    wire                                            asmi_en4b_addr;
+    wire                                            asmi_sector_erase;
+    wire                                            asmi_sector_protect;
+
+	q_sys_ext_flash_soft_asmiblock_instance_name #(
+		.IO_MODE			(IO_MODE),
+		.CS_WIDTH			(CS_WIDTH)
+	) soft_asmiblock_core_inst (
+		.dclk	            (epcq_dclk),
+		.sce	            (epcq_scein),
+		.dataout            (epcq_sdoin),
+		.dataoe	            (epcq_dataoe),
+		.datain	            (flash_dataout),
+		.dclk_out           (flash_dclk_out),
+		.ncs	            (flash_ncs)
+	);
+
+	q_sys_ext_flash_epcq_controller_instance_name	#(
+		.DEVICE_FAMILY        (DEVICE_FAMILY),
+		.ADDR_WIDTH           (ADDR_WIDTH),
+		.ASMI_ADDR_WIDTH      (ASMI_ADDR_WIDTH),
+		.CS_WIDTH             (CS_WIDTH),
+		.ASI_WIDTH            (ASI_WIDTH),
+		.ENABLE_4BYTE_ADDR    (ENABLE_4BYTE_ADDR),
+		.CHIP_SELS            (CHIP_SELS)
+	) epcq_controller_inst (
+		.clk                    (clk		            ),
+		.reset_n                (reset_n                ),
+		.avl_csr_write          (avl_csr_write          ),
+		.avl_csr_read           (avl_csr_read           ),
+		.avl_csr_addr           (avl_csr_addr           ),
+		.avl_csr_wrdata         (avl_csr_wrdata         ),
+		.avl_csr_rddata         (avl_csr_rddata         ),
+		.avl_csr_rddata_valid   (avl_csr_rddata_valid   ),
+		.avl_csr_waitrequest    (avl_csr_waitrequest    ),
+		.avl_mem_write          (avl_mem_write          ),
+		.avl_mem_read           (avl_mem_read           ),
+		.avl_mem_addr           (avl_mem_addr	        ),					
+		.avl_mem_wrdata         (avl_mem_wrdata         ),
+		.avl_mem_burstcount     (avl_mem_burstcount     ),
+		.avl_mem_byteenable     (avl_mem_byteenable     ),
+		.avl_mem_rddata         (avl_mem_rddata         ),
+		.avl_mem_rddata_valid   (avl_mem_rddata_valid   ),
+		.avl_mem_waitrequest    (avl_mem_waitrequest    ),
+		.irq                    (irq                    ),
+		.epcq_dataout           (flash_dataout          ),
+		.epcq_dclk              (epcq_dclk              ),
+		.epcq_scein             (epcq_scein             ),
+		.epcq_sdoin             (epcq_sdoin             ),
+		.epcq_dataoe            (epcq_dataoe            ),
+		.ddasi_dataoe           (ddasi_dataoe           ),
+		.ddasi_dataout          (ddasi_dataout          ),
+		.ddasi_dclk             (ddasi_dclk             ),
+		.ddasi_scein            (ddasi_scein            ),
+		.ddasi_sdoin            (ddasi_sdoin            ),
+		.asmi_busy              (asmi_busy              ),
+		.asmi_data_valid        (asmi_data_valid        ),
+		.asmi_dataout           (asmi_dataout           ),
+		.asmi_clkin             (asmi_clkin             ),
+		.asmi_reset             (asmi_reset             ),
+		.asmi_sce               (						),
+		.asmi_addr              (asmi_addr              ),
+		.asmi_datain            (asmi_datain            ),
+		.asmi_fast_read         (asmi_fast_read         ),
+		.asmi_rden              (asmi_rden              ),
+		.asmi_shift_bytes       (asmi_shift_bytes       ),
+		.asmi_wren              (asmi_wren              ),
+		.asmi_write             (asmi_write             ),
+		.asmi_illegal_erase     (asmi_illegal_erase     ),
+		.asmi_illegal_write     (asmi_illegal_write     ),
+		.asmi_rdid_out          (asmi_rdid_out          ),
+		.asmi_status_out        (asmi_status_out        ),
+		.asmi_epcs_id           ({8{1'b0}}			 	 ),
+		.asmi_read_sid          (						 ),
+		.asmi_read_rdid         (asmi_read_rdid         ),
+		.asmi_read_status       (asmi_read_status       ),
+		.asmi_en4b_addr         (asmi_en4b_addr         ),
+		.asmi_bulk_erase        (				        ),
+		.asmi_sector_erase      (asmi_sector_erase      ),
+		.asmi_sector_protect    (asmi_sector_protect    )
+	);
+	
+	q_sys_ext_flash_asmi_parallel_instance_name asmi_parallel_inst (
+		.busy                   (asmi_busy              ),
+		.data_valid             (asmi_data_valid        ),
+		.dataout                (asmi_dataout           ),
+		.clkin                  (asmi_clkin             ),
+		.reset                  (asmi_reset             ),
+		.addr                   (asmi_addr				),
+		.datain                 (asmi_datain            ),
+		.fast_read              (asmi_fast_read         ),
+		.rden                   (asmi_rden              ),
+		.shift_bytes            (asmi_shift_bytes       ),
+		.wren                   (asmi_wren              ),
+		.write                  (asmi_write             ),
+		.illegal_erase          (asmi_illegal_erase     ),
+		.illegal_write          (asmi_illegal_write     ),
+		.rdid_out               (asmi_rdid_out          ),
+		.status_out             (asmi_status_out        ),
+		.read_dummyclk          (1'b0),
+		.read_rdid              (asmi_read_rdid         ),
+		.read_status            (asmi_read_status       ),
+		.en4b_addr              (asmi_en4b_addr         ),
+		.asmi_dataoe            (ddasi_dataoe           ),   
+		.asmi_dataout           (ddasi_dataout          ),   
+		.asmi_dclk              (ddasi_dclk             ),   
+		.asmi_scein             (ddasi_scein            ),   
+		.asmi_sdoin             (ddasi_sdoin            ),      
+		.sector_erase           (asmi_sector_erase      ),
+		.sector_protect         (asmi_sector_protect    )
+	);
+	
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v
new file mode 100644
index 0000000..467fba8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v
@@ -0,0 +1,66 @@
+// q_sys_ext_flash_asmi_parallel_instance_name.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ext_flash_asmi_parallel_instance_name (
+		input  wire        clkin,          //          clkin.clk
+		input  wire        fast_read,      //      fast_read.fast_read
+		input  wire        rden,           //           rden.rden
+		input  wire [31:0] addr,           //           addr.addr
+		input  wire        read_status,    //    read_status.read_status
+		input  wire        write,          //          write.write
+		input  wire [7:0]  datain,         //         datain.datain
+		input  wire        shift_bytes,    //    shift_bytes.shift_bytes
+		input  wire        sector_protect, // sector_protect.sector_protect
+		input  wire        sector_erase,   //   sector_erase.sector_erase
+		input  wire        wren,           //           wren.wren
+		input  wire        read_rdid,      //      read_rdid.read_rdid
+		input  wire        en4b_addr,      //      en4b_addr.en4b_addr
+		input  wire        reset,          //          reset.reset
+		input  wire        read_dummyclk,  //  read_dummyclk.read_dummyclk
+		input  wire [3:0]  asmi_dataout,   //   asmi_dataout.asmi_dataout
+		output wire [7:0]  dataout,        //        dataout.dataout
+		output wire        busy,           //           busy.busy
+		output wire        data_valid,     //     data_valid.data_valid
+		output wire [7:0]  status_out,     //     status_out.status_out
+		output wire        illegal_write,  //  illegal_write.illegal_write
+		output wire        illegal_erase,  //  illegal_erase.illegal_erase
+		output wire [7:0]  rdid_out,       //       rdid_out.rdid_out
+		output wire        asmi_dclk,      //      asmi_dclk.asmi_dclk
+		output wire        asmi_scein,     //     asmi_scein.asmi_scein
+		output wire [3:0]  asmi_sdoin,     //     asmi_sdoin.asmi_sdoin
+		output wire [3:0]  asmi_dataoe     //    asmi_dataoe.asmi_dataoe
+	);
+
+	q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name asmi_parallel_instance_name (
+		.clkin          (clkin),          //          clkin.clk
+		.fast_read      (fast_read),      //      fast_read.fast_read
+		.rden           (rden),           //           rden.rden
+		.addr           (addr),           //           addr.addr
+		.read_status    (read_status),    //    read_status.read_status
+		.write          (write),          //          write.write
+		.datain         (datain),         //         datain.datain
+		.shift_bytes    (shift_bytes),    //    shift_bytes.shift_bytes
+		.sector_protect (sector_protect), // sector_protect.sector_protect
+		.sector_erase   (sector_erase),   //   sector_erase.sector_erase
+		.wren           (wren),           //           wren.wren
+		.read_rdid      (read_rdid),      //      read_rdid.read_rdid
+		.en4b_addr      (en4b_addr),      //      en4b_addr.en4b_addr
+		.reset          (reset),          //          reset.reset
+		.read_dummyclk  (read_dummyclk),  //  read_dummyclk.read_dummyclk
+		.asmi_dataout   (asmi_dataout),   //   asmi_dataout.asmi_dataout
+		.dataout        (dataout),        //        dataout.dataout
+		.busy           (busy),           //           busy.busy
+		.data_valid     (data_valid),     //     data_valid.data_valid
+		.status_out     (status_out),     //     status_out.status_out
+		.illegal_write  (illegal_write),  //  illegal_write.illegal_write
+		.illegal_erase  (illegal_erase),  //  illegal_erase.illegal_erase
+		.rdid_out       (rdid_out),       //       rdid_out.rdid_out
+		.asmi_dclk      (asmi_dclk),      //      asmi_dclk.asmi_dclk
+		.asmi_scein     (asmi_scein),     //     asmi_scein.asmi_scein
+		.asmi_sdoin     (asmi_sdoin),     //     asmi_sdoin.asmi_sdoin
+		.asmi_dataoe    (asmi_dataoe)     //    asmi_dataoe.asmi_dataoe
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v
new file mode 100644
index 0000000..f7d24a9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v
@@ -0,0 +1,2872 @@
+//altasmi_parallel CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DATA_WIDTH="QUAD" DEVICE_FAMILY="Arria V" ENABLE_SIM="TRUE" EPCS_TYPE="EPCQL512" FLASH_RSTPIN="TRUE" PAGE_SIZE=256 PORT_BULK_ERASE="PORT_UNUSED" PORT_DIE_ERASE="PORT_UNUSED" PORT_EN4B_ADDR="PORT_USED" PORT_EX4B_ADDR="PORT_UNUSED" PORT_FAST_READ="PORT_USED" PORT_ILLEGAL_ERASE="PORT_USED" PORT_ILLEGAL_WRITE="PORT_USED" PORT_RDID_OUT="PORT_USED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_DUMMYCLK="PORT_USED" PORT_READ_RDID="PORT_USED" PORT_READ_SID="PORT_UNUSED" PORT_READ_STATUS="PORT_USED" PORT_SECTOR_ERASE="PORT_USED" PORT_SECTOR_PROTECT="PORT_USED" PORT_SHIFT_BYTES="PORT_USED" PORT_WREN="PORT_USED" PORT_WRITE="PORT_USED" USE_ASMIBLOCK="OFF" USE_EAB="ON" WRITE_DUMMY_CLK=0 addr asmi_dataoe asmi_dataout asmi_dclk asmi_scein asmi_sdoin busy clkin data_valid datain dataout en4b_addr fast_read illegal_erase illegal_write rden rdid_out read_dummyclk read_rdid read_status reset sector_erase sector_protect shift_bytes status_out wren write INTENDED_DEVICE_FAMILY=""" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
+//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:08:02:34:SJ cbx_a_graycounter 2019:09:22:08:02:34:SJ cbx_altasmi_parallel 2019:09:22:08:02:34:SJ cbx_altdpram 2019:09:22:08:02:34:SJ cbx_altera_counter 2019:09:22:08:02:34:SJ cbx_altera_syncram 2019:09:22:08:02:34:SJ cbx_altera_syncram_nd_impl 2019:09:22:08:02:34:SJ cbx_altsyncram 2019:09:22:08:02:34:SJ cbx_arriav 2019:09:22:08:02:34:SJ cbx_cyclone 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_fifo_common 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_counter 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_nightfury 2019:09:22:08:02:34:SJ cbx_scfifo 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ cbx_zippleback 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = a_graycounter 6 lpm_compare 3 lpm_counter 4 lut 29 mux21 19 reg 254 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
+module  q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name
+	( 
+	addr,
+	asmi_dataoe,
+	asmi_dataout,
+	asmi_dclk,
+	asmi_scein,
+	asmi_sdoin,
+	busy,
+	clkin,
+	data_valid,
+	datain,
+	dataout,
+	en4b_addr,
+	fast_read,
+	illegal_erase,
+	illegal_write,
+	rden,
+	rdid_out,
+	read_dummyclk,
+	read_rdid,
+	read_status,
+	reset,
+	sector_erase,
+	sector_protect,
+	shift_bytes,
+	status_out,
+	wren,
+	write) /* synthesis synthesis_clearbox=1 */;
+	input   [31:0]  addr;
+	output   [3:0]  asmi_dataoe;
+	input   [3:0]  asmi_dataout;
+	output   asmi_dclk;
+	output   asmi_scein;
+	output   [3:0]  asmi_sdoin;
+	output   busy;
+	input   clkin;
+	output   data_valid;
+	input   [7:0]  datain;
+	output   [7:0]  dataout;
+	input   en4b_addr;
+	input   fast_read;
+	output   illegal_erase;
+	output   illegal_write;
+	input   rden;
+	output   [7:0]  rdid_out;
+	input   read_dummyclk;
+	input   read_rdid;
+	input   read_status;
+	input   reset;
+	input   sector_erase;
+	input   sector_protect;
+	input   shift_bytes;
+	output   [7:0]  status_out;
+	input   wren;
+	input   write;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [3:0]  asmi_dataout;
+	tri0   [7:0]  datain;
+	tri0   en4b_addr;
+	tri0   fast_read;
+	tri0   read_dummyclk;
+	tri0   read_rdid;
+	tri0   read_status;
+	tri0   reset;
+	tri0   sector_erase;
+	tri0   sector_protect;
+	tri0   shift_bytes;
+	tri1   wren;
+	tri0   write;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [3:0]   wire_addbyte_cntr_q;
+	wire  [2:0]   wire_gen_cntr_q;
+	wire  [2:0]   wire_read_flag_status_cntr_q;
+	wire  [1:0]   wire_spstage_cntr_q;
+	wire  [1:0]   wire_stage_cntr_q;
+	wire  [1:0]   wire_wrstage_cntr_q;
+	wire	[3:0]	wire_add_msb_quad_reg_d;
+	reg	[3:0]	add_msb_quad_reg;
+	wire	[3:0]	wire_add_msb_quad_reg_ena;
+	reg	add_msb_reg;
+	wire	wire_add_msb_reg_ena;
+	reg	add_rollover_reg;
+	reg	addr_die_diff_reg;
+	wire	wire_addr_die_diff_reg_ena;
+	wire	wire_addr_die_diff_reg_sclr;
+	reg	addr_overdie_delay_reg;
+	reg	addr_overdie_reg;
+	wire	wire_addr_overdie_reg_ena;
+	wire	wire_addr_overdie_reg_sclr;
+	wire	[31:0]	wire_addr_reg_d;
+	reg	[31:0]	addr_reg;
+	wire	[31:0]	wire_addr_reg_ena;
+	wire	[7:0]	wire_asmi_opcode_reg_d;
+	reg	[7:0]	asmi_opcode_reg;
+	wire	[7:0]	wire_asmi_opcode_reg_ena;
+	reg	buf_empty_reg;
+	reg	busy_delay_reg;
+	reg	busy_det_reg;
+	reg	clr_rdid_reg;
+	reg	clr_read_reg;
+	reg	clr_read_reg2;
+	reg	clr_rstat_reg;
+	reg	clr_secprot_reg;
+	reg	clr_secprot_reg1;
+	reg	clr_write_reg;
+	reg	clr_write_reg2;
+	reg	cnt_bfend_reg;
+	reg	do_wrmemadd_reg;
+	reg	[3:0]	dummyclk_reg;
+	reg	dvalid_reg;
+	wire	wire_dvalid_reg_ena;
+	wire	wire_dvalid_reg_sclr;
+	reg	dvalid_reg2;
+	reg	end1_cyc_reg;
+	reg	end1_cyc_reg2;
+	reg	end_op_hdlyreg;
+	reg	end_op_reg;
+	reg	end_pgwrop_reg;
+	wire	wire_end_pgwrop_reg_ena;
+	reg	end_rbyte_reg;
+	wire	wire_end_rbyte_reg_ena;
+	wire	wire_end_rbyte_reg_sclr;
+	reg	end_read_reg;
+	reg	fast_read_reg;
+	wire	wire_fast_read_reg_ena;
+	reg	ill_erase_reg;
+	reg	ill_write_reg;
+	reg	illegal_erase_dly_reg;
+	reg	illegal_write_dly_reg;
+	reg	illegal_write_prot_reg;
+	reg	max_cnt_reg;
+	reg	maxcnt_shift_reg;
+	reg	maxcnt_shift_reg2;
+	reg	ncs_reg;
+	wire	wire_ncs_reg_sclr;
+	wire	[7:0]	wire_pgwrbuf_dataout_d;
+	reg	[7:0]	pgwrbuf_dataout;
+	wire	[7:0]	wire_pgwrbuf_dataout_ena;
+	wire	[7:0]	wire_pgwrbuf_quad_dataout_d;
+	reg	[7:0]	pgwrbuf_quad_dataout;
+	wire	[7:0]	wire_pgwrbuf_quad_dataout_ena;
+	reg	power_up_reg;
+	wire	[31:0]	wire_quad_addr_reg_d;
+	reg	[31:0]	quad_addr_reg;
+	wire	[31:0]	wire_quad_addr_reg_ena;
+	reg	[7:0]	rdid_out_reg;
+	wire	[31:0]	wire_read_add_reg_d;
+	reg	[31:0]	read_add_reg;
+	wire	[31:0]	wire_read_add_reg_ena;
+	reg	read_bufdly_reg;
+	wire	[7:0]	wire_read_data_reg_d;
+	reg	[7:0]	read_data_reg;
+	wire	[7:0]	wire_read_data_reg_ena;
+	wire	[7:0]	wire_read_dout_quad_reg_d;
+	reg	[7:0]	read_dout_quad_reg;
+	wire	[7:0]	wire_read_dout_quad_reg_ena;
+	wire	[7:0]	wire_read_dout_reg_d;
+	reg	[7:0]	read_dout_reg;
+	wire	[7:0]	wire_read_dout_reg_ena;
+	reg	read_dummyclk_reg;
+	wire	wire_read_dummyclk_reg_ena;
+	reg	read_nonvdummyclk_reg;
+	wire	wire_read_nonvdummyclk_reg_ena;
+	reg	read_rdid_reg;
+	wire	wire_read_rdid_reg_ena;
+	reg	read_status_reg;
+	wire	wire_read_status_reg_ena;
+	reg	reset_addren_reg;
+	wire	wire_reset_addren_reg_ena;
+	reg	sec_erase_reg;
+	wire	wire_sec_erase_reg_ena;
+	reg	sec_prot_reg;
+	wire	wire_sec_prot_reg_ena;
+	reg	shftpgwr_data_reg;
+	reg	shift_op_reg;
+	reg	sprot_rstat_reg;
+	reg	stage2_reg;
+	reg	stage3_dly_reg;
+	reg	stage3_reg;
+	reg	stage4_reg;
+	reg	start_dummyclk_reg;
+	wire	wire_start_dummyclk_reg_ena;
+	wire	wire_start_dummyclk_reg_sclr;
+	reg	start_sppoll_reg;
+	wire	wire_start_sppoll_reg_ena;
+	reg	start_sppoll_reg2;
+	reg	start_wrpoll_reg;
+	wire	wire_start_wrpoll_reg_ena;
+	reg	start_wrpoll_reg2;
+	wire	[7:0]	wire_statreg_int_d;
+	reg	[7:0]	statreg_int;
+	wire	[7:0]	wire_statreg_int_ena;
+	wire	[7:0]	wire_statreg_out_d;
+	reg	[7:0]	statreg_out;
+	wire	[7:0]	wire_statreg_out_ena;
+	reg	streg_datain_reg;
+	wire	wire_streg_datain_reg_ena;
+	wire	[7:0]	wire_volatile_reg_d;
+	reg	[7:0]	volatile_reg;
+	wire	[7:0]	wire_volatile_reg_ena;
+	reg	write_prot_reg;
+	wire	wire_write_prot_reg_ena;
+	reg	write_reg;
+	wire	wire_write_reg_ena;
+	reg	write_rstat_reg;
+	wire	[7:0]	wire_wrstat_dreg_d;
+	reg	[7:0]	wrstat_dreg;
+	wire	[7:0]	wire_wrstat_dreg_ena;
+	wire  wire_cmpr14_aeb;
+	wire  wire_cmpr15_aeb;
+	wire  wire_cmpr8_aeb;
+	wire  [3:0]   wire_dummyclk_cntr_q;
+	wire  [8:0]   wire_pgwr_data_cntr_q;
+	wire  [8:0]   wire_pgwr_read_cntr_q;
+	wire  [32:0]   wire_read_add_cntr_q;
+	wire	wire_mux211_dataout;
+	wire	wire_mux2110_dataout;
+	wire	wire_mux2111_dataout;
+	wire	wire_mux2112_dataout;
+	wire	wire_mux2116_dataout;
+	wire	wire_mux212_dataout;
+	wire	wire_mux213_dataout;
+	wire	[3:0]wire_mux214a_dataout;
+	wire	[7:0]wire_mux219a_dataout;
+	wire  [7:0]   wire_scfifo13_q;
+	wire  add_rollover;
+	wire  addr_die_diff;
+	wire  addr_overdie;
+	wire  addr_overdie_pos;
+	wire  [31:0]  addr_reg_overdie;
+	wire  [7:0]  b4addr_opcode;
+	wire  be_write_prot;
+	wire  [7:0]  berase_opcode;
+	wire  bp0_wire;
+	wire  bp1_wire;
+	wire  bp2_wire;
+	wire  bp3_wire;
+	wire  buf_empty;
+	wire  bulk_erase_wire;
+	wire  busy_wire;
+	wire  clkin_wire;
+	wire  clr_addmsb_wire;
+	wire  clr_endrbyte_wire;
+	wire  clr_freadepcq_wire;
+	wire  clr_rdid_wire;
+	wire  clr_read_wire;
+	wire  clr_read_wire2;
+	wire  clr_rstat_wire;
+	wire  clr_secprot_wire;
+	wire  clr_secprot_wire1;
+	wire  clr_sid_wire;
+	wire  clr_write_wire;
+	wire  clr_write_wire2;
+	wire  cnt_bfend_wire_in;
+	wire  data0out_wire;
+	wire  data_valid_wire;
+	wire  [3:0]  datain_wire;
+	wire  [3:0]  dataoe_wire;
+	wire  [3:0]  dataout_wire;
+	wire  [7:0]  derase_opcode;
+	wire  die_erase_wire;
+	wire  do_4baddr;
+	wire  do_addr_overdie;
+	wire  do_bulk_erase;
+	wire  do_die_erase;
+	wire  do_ex4baddr;
+	wire  do_fast_read;
+	wire  do_fread_epcq;
+	wire  do_freadwrv_polling;
+	wire  do_memadd;
+	wire  do_polling;
+	wire  do_read;
+	wire  do_read_nonvolatile;
+	wire  do_read_rdid;
+	wire  do_read_sid;
+	wire  do_read_stat;
+	wire  do_read_volatile;
+	wire  do_sec_erase;
+	wire  do_sec_prot;
+	wire  do_secprot_wren;
+	wire  do_sprot_polling;
+	wire  do_sprot_rstat;
+	wire  do_wait_dummyclk;
+	wire  do_wren;
+	wire  do_write;
+	wire  do_write_polling;
+	wire  do_write_rstat;
+	wire  do_write_volatile;
+	wire  do_write_volatile_rstat;
+	wire  do_write_volatile_wren;
+	wire  do_write_wren;
+	wire  dummy_read_buf;
+	wire  end1_cyc_dlyncs_in_wire;
+	wire  end1_cyc_gen_cntr_wire;
+	wire  end1_cyc_normal_in_wire;
+	wire  end1_cyc_reg_in_wire;
+	wire  end_add_cycle;
+	wire  end_add_cycle_mux_datab_wire;
+	wire  end_fast_read;
+	wire  end_one_cyc_pos;
+	wire  end_one_cycle;
+	wire  end_op_wire;
+	wire  end_operation;
+	wire  end_ophdly;
+	wire  end_pgwr_data;
+	wire  end_read;
+	wire  end_read_byte;
+	wire  end_read_flag_status;
+	wire  end_wrstage;
+	wire  ex4b_addr_wire;
+	wire  [7:0]  exb4addr_opcode;
+	wire  [7:0]  fast_read_opcode;
+	wire  fast_read_wire;
+	wire  freadwrv_sdoin;
+	wire  ill_erase_wire;
+	wire  ill_write_wire;
+	wire  illegal_erase_b4out_wire;
+	wire  illegal_write_b4out_wire;
+	wire  in_operation;
+	wire  [2:0]  inout_wire;
+	wire  load_opcode;
+	wire  [9:0]  mask_prot;
+	wire  [9:0]  mask_prot_add;
+	wire  [9:0]  mask_prot_check;
+	wire  [9:0]  mask_prot_comp_ntb;
+	wire  [9:0]  mask_prot_comp_tb;
+	wire  [3:0]  memadd_datain;
+	wire  ncs_reg_ena_wire;
+	wire  not_busy;
+	wire  [8:0]  page_size_wire;
+	wire  [8:0]  pagewr_buf_not_empty;
+	wire  [15:0]  prot_wire;
+	wire  rden_wire;
+	wire  rdid_load;
+	wire  [7:0]  rdid_opcode;
+	wire  [7:0]  rdummyclk_opcode;
+	wire  reach_max_cnt;
+	wire  read_buf;
+	wire  read_bufdly;
+	wire  [7:0]  read_data_reg_in_wire;
+	wire  read_dummyclk_wire;
+	wire  read_nonvolatile;
+	wire  [7:0]  read_opcode;
+	wire  read_rdid_wire;
+	wire  read_sid_wire;
+	wire  read_status_wire;
+	wire  read_wire;
+	wire  reset_addren_wire;
+	wire  [7:0]  rflagstat_opcode;
+	wire  [7:0]  rnvdummyclk_opcode;
+	wire  [7:0]  rsid_opcode;
+	wire  rsid_sdoin;
+	wire  [7:0]  rstat_opcode;
+	wire  scein_wire;
+	wire  sec_erase_wire;
+	wire  sec_protect_wire;
+	wire  [7:0]  secprot_opcode;
+	wire  secprot_sdoin;
+	wire  [7:0]  serase_opcode;
+	wire  shift_bytes_wire;
+	wire  shift_opcode;
+	wire  shift_opdata;
+	wire  shift_pgwr_data;
+	wire  st_busy_wire;
+	wire  stage2_wire;
+	wire  stage3_wire;
+	wire  stage4_wire;
+	wire  start_frpoll;
+	wire  start_poll;
+	wire  start_sppoll;
+	wire  start_wrpoll;
+	wire  tb_wire;
+	wire  volatile_default_wire;
+	wire  volatile_empty_wire;
+	wire  [7:0]  wren_opcode;
+	wire  wren_wire;
+	wire  [3:0]  write_datain;
+	wire  [7:0]  write_opcode;
+	wire  write_prot_true;
+	wire  write_wire;
+	wire  [7:0]  wrvolatile_opcode;
+
+	a_graycounter   addbyte_cntr
+	( 
+	.aclr(reset),
+	.clk_en((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cyc_pos) & (((((((do_read_sid | do_write) | do_sec_erase) | do_die_erase) | do_read_rdid) | do_read) | do_fast_read) | do_read_nonvolatile)) | addr_overdie) | end_operation)),
+	.clock((~ clkin_wire)),
+	.q(wire_addbyte_cntr_q),
+	.qbin(),
+	.sclr((end_operation | addr_overdie))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		addbyte_cntr.width = 4,
+		addbyte_cntr.lpm_type = "a_graycounter";
+	a_graycounter   gen_cntr
+	( 
+	.aclr(reset),
+	.clk_en((((((in_operation & (~ end_ophdly)) & (~ clr_rstat_wire)) & (~ clr_sid_wire)) | do_wait_dummyclk) | addr_overdie)),
+	.clock(clkin_wire),
+	.q(wire_gen_cntr_q),
+	.qbin(),
+	.sclr(((end1_cyc_reg_in_wire | addr_overdie) | do_wait_dummyclk))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		gen_cntr.width = 3,
+		gen_cntr.lpm_type = "a_graycounter";
+	a_graycounter   read_flag_status_cntr
+	( 
+	.aclr(reset),
+	.clk_en(((((start_sppoll & end_operation) & (~ end_read_flag_status)) & (~ st_busy_wire)) | (clr_secprot_wire1 | ((start_sppoll & st_busy_wire) & stage3_wire)))),
+	.clock(clkin_wire),
+	.q(wire_read_flag_status_cntr_q),
+	.qbin(),
+	.sclr((clr_secprot_wire1 | ((start_sppoll & st_busy_wire) & stage3_wire)))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		read_flag_status_cntr.width = 3,
+		read_flag_status_cntr.lpm_type = "a_graycounter";
+	a_graycounter   spstage_cntr
+	( 
+	.aclr(reset),
+	.clk_en(((((do_sec_prot & end_operation) & (~ do_sprot_polling)) | (((do_sec_prot & end_operation) & do_sprot_polling) & end_read_flag_status)) | clr_secprot_wire1)),
+	.clock((~ clkin_wire)),
+	.q(wire_spstage_cntr_q),
+	.qbin(),
+	.sclr(clr_secprot_wire1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		spstage_cntr.width = 2,
+		spstage_cntr.lpm_type = "a_graycounter";
+	a_graycounter   stage_cntr
+	( 
+	.aclr(reset),
+	.clk_en(((((((((((((((in_operation & end_one_cycle) & (~ (stage3_wire & (~ end_add_cycle)))) & (~ (stage4_wire & (~ end_read)))) & (~ (stage4_wire & (~ end_fast_read)))) & (~ ((((do_write | do_sec_erase) | do_die_erase) | do_bulk_erase) & write_prot_true))) & (~ (do_write & (~ pagewr_buf_not_empty[8])))) & (~ (stage3_wire & st_busy_wire))) & (~ ((do_write & shift_pgwr_data) & (~ end_pgwr_data)))) & (~ (stage2_wire & do_wren))) & (~ ((((stage3_wire & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & (~ do_read_rdid)))) & (~ (stage3_wire & ((do_write_volatile | do_read_volatile) | do_read_nonvolatile)))) | ((stage3_wire & do_fast_read) & do_wait_dummyclk)) | addr_overdie) | end_ophdly)),
+	.clock(clkin_wire),
+	.q(wire_stage_cntr_q),
+	.qbin(),
+	.sclr((end_operation | addr_overdie))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		stage_cntr.width = 2,
+		stage_cntr.lpm_type = "a_graycounter";
+	a_graycounter   wrstage_cntr
+	( 
+	.aclr(reset),
+	.clk_en((((((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & (~ write_prot_true)) | do_4baddr) | do_ex4baddr) & end_wrstage) & (~ st_busy_wire)) | clr_write_wire2)),
+	.clock((~ clkin_wire)),
+	.q(wire_wrstage_cntr_q),
+	.qbin(),
+	.sclr(clr_write_wire2)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.cnt_en(1'b1),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		wrstage_cntr.width = 2,
+		wrstage_cntr.lpm_type = "a_graycounter";
+	// synopsys translate_off
+	initial
+		add_msb_quad_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_msb_quad_reg[0:0] <= 1'b0;
+		else if  (wire_add_msb_quad_reg_ena[0:0] == 1'b1) 
+			if (clr_addmsb_wire == 1'b1) add_msb_quad_reg[0:0] <= 1'b0;
+			else  add_msb_quad_reg[0:0] <= wire_add_msb_quad_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		add_msb_quad_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_msb_quad_reg[1:1] <= 1'b0;
+		else if  (wire_add_msb_quad_reg_ena[1:1] == 1'b1) 
+			if (clr_addmsb_wire == 1'b1) add_msb_quad_reg[1:1] <= 1'b0;
+			else  add_msb_quad_reg[1:1] <= wire_add_msb_quad_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		add_msb_quad_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_msb_quad_reg[2:2] <= 1'b0;
+		else if  (wire_add_msb_quad_reg_ena[2:2] == 1'b1) 
+			if (clr_addmsb_wire == 1'b1) add_msb_quad_reg[2:2] <= 1'b0;
+			else  add_msb_quad_reg[2:2] <= wire_add_msb_quad_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		add_msb_quad_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_msb_quad_reg[3:3] <= 1'b0;
+		else if  (wire_add_msb_quad_reg_ena[3:3] == 1'b1) 
+			if (clr_addmsb_wire == 1'b1) add_msb_quad_reg[3:3] <= 1'b0;
+			else  add_msb_quad_reg[3:3] <= wire_add_msb_quad_reg_d[3:3];
+	assign
+		wire_add_msb_quad_reg_d = {quad_addr_reg[31:28]};
+	assign
+		wire_add_msb_quad_reg_ena = {4{(((((do_fast_read | do_write) & (~ (do_write & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) | clr_addmsb_wire)}};
+	// synopsys translate_off
+	initial
+		add_msb_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_msb_reg <= 1'b0;
+		else if  (wire_add_msb_reg_ena == 1'b1) 
+			if (clr_addmsb_wire == 1'b1) add_msb_reg <= 1'b0;
+			else  add_msb_reg <= addr_reg[31];
+	assign
+		wire_add_msb_reg_ena = ((((((((do_read | do_fast_read) | do_write) | do_sec_erase) | do_die_erase) & (~ (((do_write | do_sec_erase) | do_die_erase) & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) | clr_addmsb_wire);
+	// synopsys translate_off
+	initial
+		add_rollover_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) add_rollover_reg <= 1'b0;
+		else  add_rollover_reg <= (wire_read_add_cntr_q[26] | clr_read_wire2);
+	// synopsys translate_off
+	initial
+		addr_die_diff_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_die_diff_reg <= 1'b0;
+		else if  (wire_addr_die_diff_reg_ena == 1'b1) 
+			if (wire_addr_die_diff_reg_sclr == 1'b1) addr_die_diff_reg <= 1'b0;
+			else  addr_die_diff_reg <= addr[25];
+	assign
+		wire_addr_die_diff_reg_ena = ((not_busy | clr_read_wire2) | add_rollover),
+		wire_addr_die_diff_reg_sclr = (clr_read_wire2 | add_rollover);
+	// synopsys translate_off
+	initial
+		addr_overdie_delay_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_overdie_delay_reg <= 1'b0;
+		else  addr_overdie_delay_reg <= addr_overdie;
+	// synopsys translate_off
+	initial
+		addr_overdie_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_overdie_reg <= 1'b0;
+		else if  (wire_addr_overdie_reg_ena == 1'b1) 
+			if (wire_addr_overdie_reg_sclr == 1'b1) addr_overdie_reg <= 1'b0;
+			else  addr_overdie_reg <= addr_overdie_pos;
+	assign
+		wire_addr_overdie_reg_ena = (((~ do_addr_overdie) | add_rollover) | clr_read_wire2),
+		wire_addr_overdie_reg_sclr = (add_rollover | clr_read_wire2);
+	// synopsys translate_off
+	initial
+		addr_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[0:0] <= 1'b0;
+		else if  (wire_addr_reg_ena[0:0] == 1'b1)   addr_reg[0:0] <= wire_addr_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		addr_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[1:1] <= 1'b0;
+		else if  (wire_addr_reg_ena[1:1] == 1'b1)   addr_reg[1:1] <= wire_addr_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		addr_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[2:2] <= 1'b0;
+		else if  (wire_addr_reg_ena[2:2] == 1'b1)   addr_reg[2:2] <= wire_addr_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		addr_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[3:3] <= 1'b0;
+		else if  (wire_addr_reg_ena[3:3] == 1'b1)   addr_reg[3:3] <= wire_addr_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		addr_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[4:4] <= 1'b0;
+		else if  (wire_addr_reg_ena[4:4] == 1'b1)   addr_reg[4:4] <= wire_addr_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		addr_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[5:5] <= 1'b0;
+		else if  (wire_addr_reg_ena[5:5] == 1'b1)   addr_reg[5:5] <= wire_addr_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		addr_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[6:6] <= 1'b0;
+		else if  (wire_addr_reg_ena[6:6] == 1'b1)   addr_reg[6:6] <= wire_addr_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		addr_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[7:7] <= 1'b0;
+		else if  (wire_addr_reg_ena[7:7] == 1'b1)   addr_reg[7:7] <= wire_addr_reg_d[7:7];
+	// synopsys translate_off
+	initial
+		addr_reg[8:8] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[8:8] <= 1'b0;
+		else if  (wire_addr_reg_ena[8:8] == 1'b1)   addr_reg[8:8] <= wire_addr_reg_d[8:8];
+	// synopsys translate_off
+	initial
+		addr_reg[9:9] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[9:9] <= 1'b0;
+		else if  (wire_addr_reg_ena[9:9] == 1'b1)   addr_reg[9:9] <= wire_addr_reg_d[9:9];
+	// synopsys translate_off
+	initial
+		addr_reg[10:10] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[10:10] <= 1'b0;
+		else if  (wire_addr_reg_ena[10:10] == 1'b1)   addr_reg[10:10] <= wire_addr_reg_d[10:10];
+	// synopsys translate_off
+	initial
+		addr_reg[11:11] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[11:11] <= 1'b0;
+		else if  (wire_addr_reg_ena[11:11] == 1'b1)   addr_reg[11:11] <= wire_addr_reg_d[11:11];
+	// synopsys translate_off
+	initial
+		addr_reg[12:12] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[12:12] <= 1'b0;
+		else if  (wire_addr_reg_ena[12:12] == 1'b1)   addr_reg[12:12] <= wire_addr_reg_d[12:12];
+	// synopsys translate_off
+	initial
+		addr_reg[13:13] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[13:13] <= 1'b0;
+		else if  (wire_addr_reg_ena[13:13] == 1'b1)   addr_reg[13:13] <= wire_addr_reg_d[13:13];
+	// synopsys translate_off
+	initial
+		addr_reg[14:14] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[14:14] <= 1'b0;
+		else if  (wire_addr_reg_ena[14:14] == 1'b1)   addr_reg[14:14] <= wire_addr_reg_d[14:14];
+	// synopsys translate_off
+	initial
+		addr_reg[15:15] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[15:15] <= 1'b0;
+		else if  (wire_addr_reg_ena[15:15] == 1'b1)   addr_reg[15:15] <= wire_addr_reg_d[15:15];
+	// synopsys translate_off
+	initial
+		addr_reg[16:16] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[16:16] <= 1'b0;
+		else if  (wire_addr_reg_ena[16:16] == 1'b1)   addr_reg[16:16] <= wire_addr_reg_d[16:16];
+	// synopsys translate_off
+	initial
+		addr_reg[17:17] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[17:17] <= 1'b0;
+		else if  (wire_addr_reg_ena[17:17] == 1'b1)   addr_reg[17:17] <= wire_addr_reg_d[17:17];
+	// synopsys translate_off
+	initial
+		addr_reg[18:18] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[18:18] <= 1'b0;
+		else if  (wire_addr_reg_ena[18:18] == 1'b1)   addr_reg[18:18] <= wire_addr_reg_d[18:18];
+	// synopsys translate_off
+	initial
+		addr_reg[19:19] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[19:19] <= 1'b0;
+		else if  (wire_addr_reg_ena[19:19] == 1'b1)   addr_reg[19:19] <= wire_addr_reg_d[19:19];
+	// synopsys translate_off
+	initial
+		addr_reg[20:20] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[20:20] <= 1'b0;
+		else if  (wire_addr_reg_ena[20:20] == 1'b1)   addr_reg[20:20] <= wire_addr_reg_d[20:20];
+	// synopsys translate_off
+	initial
+		addr_reg[21:21] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[21:21] <= 1'b0;
+		else if  (wire_addr_reg_ena[21:21] == 1'b1)   addr_reg[21:21] <= wire_addr_reg_d[21:21];
+	// synopsys translate_off
+	initial
+		addr_reg[22:22] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[22:22] <= 1'b0;
+		else if  (wire_addr_reg_ena[22:22] == 1'b1)   addr_reg[22:22] <= wire_addr_reg_d[22:22];
+	// synopsys translate_off
+	initial
+		addr_reg[23:23] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[23:23] <= 1'b0;
+		else if  (wire_addr_reg_ena[23:23] == 1'b1)   addr_reg[23:23] <= wire_addr_reg_d[23:23];
+	// synopsys translate_off
+	initial
+		addr_reg[24:24] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[24:24] <= 1'b0;
+		else if  (wire_addr_reg_ena[24:24] == 1'b1)   addr_reg[24:24] <= wire_addr_reg_d[24:24];
+	// synopsys translate_off
+	initial
+		addr_reg[25:25] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[25:25] <= 1'b0;
+		else if  (wire_addr_reg_ena[25:25] == 1'b1)   addr_reg[25:25] <= wire_addr_reg_d[25:25];
+	// synopsys translate_off
+	initial
+		addr_reg[26:26] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[26:26] <= 1'b0;
+		else if  (wire_addr_reg_ena[26:26] == 1'b1)   addr_reg[26:26] <= wire_addr_reg_d[26:26];
+	// synopsys translate_off
+	initial
+		addr_reg[27:27] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[27:27] <= 1'b0;
+		else if  (wire_addr_reg_ena[27:27] == 1'b1)   addr_reg[27:27] <= wire_addr_reg_d[27:27];
+	// synopsys translate_off
+	initial
+		addr_reg[28:28] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[28:28] <= 1'b0;
+		else if  (wire_addr_reg_ena[28:28] == 1'b1)   addr_reg[28:28] <= wire_addr_reg_d[28:28];
+	// synopsys translate_off
+	initial
+		addr_reg[29:29] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[29:29] <= 1'b0;
+		else if  (wire_addr_reg_ena[29:29] == 1'b1)   addr_reg[29:29] <= wire_addr_reg_d[29:29];
+	// synopsys translate_off
+	initial
+		addr_reg[30:30] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[30:30] <= 1'b0;
+		else if  (wire_addr_reg_ena[30:30] == 1'b1)   addr_reg[30:30] <= wire_addr_reg_d[30:30];
+	// synopsys translate_off
+	initial
+		addr_reg[31:31] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) addr_reg[31:31] <= 1'b0;
+		else if  (wire_addr_reg_ena[31:31] == 1'b1)   addr_reg[31:31] <= wire_addr_reg_d[31:31];
+	assign
+		wire_addr_reg_d = {((({31{not_busy}} & addr[31:1]) | ({31{stage3_wire}} & addr_reg[30:0])) | ({31{addr_overdie}} & addr_reg_overdie[31:1])), ((not_busy & addr[0]) | (addr_overdie & addr_reg_overdie[0]))};
+	assign
+		wire_addr_reg_ena = {32{((((rden_wire | wren_wire) & not_busy) | (stage4_wire & addr_overdie)) | (stage3_wire & ((((do_write | do_sec_erase) | do_die_erase) & do_memadd) | (do_fast_read & (~ end_ophdly)))))}};
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[0:0] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[0:0] == 1'b1)   asmi_opcode_reg[0:0] <= wire_asmi_opcode_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[1:1] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[1:1] == 1'b1)   asmi_opcode_reg[1:1] <= wire_asmi_opcode_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[2:2] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[2:2] == 1'b1)   asmi_opcode_reg[2:2] <= wire_asmi_opcode_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[3:3] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[3:3] == 1'b1)   asmi_opcode_reg[3:3] <= wire_asmi_opcode_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[4:4] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[4:4] == 1'b1)   asmi_opcode_reg[4:4] <= wire_asmi_opcode_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[5:5] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[5:5] == 1'b1)   asmi_opcode_reg[5:5] <= wire_asmi_opcode_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[6:6] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[6:6] == 1'b1)   asmi_opcode_reg[6:6] <= wire_asmi_opcode_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		asmi_opcode_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) asmi_opcode_reg[7:7] <= 1'b0;
+		else if  (wire_asmi_opcode_reg_ena[7:7] == 1'b1)   asmi_opcode_reg[7:7] <= wire_asmi_opcode_reg_d[7:7];
+	assign
+		wire_asmi_opcode_reg_d = {(((((((((((((((((({7{(load_opcode & do_read_sid)}} & rsid_opcode[7:1]) | ({7{(load_opcode & do_read_rdid)}} & rdid_opcode[7:1])) | ({7{(((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat))}} & secprot_opcode[7:1])) | ({7{(load_opcode & do_read)}} & read_opcode[7:1])) | ({7{(load_opcode & do_fast_read)}} & fast_read_opcode[7:1])) | ({7{((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & rdummyclk_opcode[7:1])) | ({7{((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & wrvolatile_opcode[7:1])) | ({7{(load_opcode & do_read_nonvolatile)}} & rnvdummyclk_opcode[7:1])) | ({7{(load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren)))}} & write_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & (~ do_polling))}} & rstat_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & do_polling)}} & rflagstat_opcode[7:1])) | ({7{(((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat))}} & serase_opcode[7:1])) | ({7{(((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat))}} & derase_opcode[7:1])) | ({7{(((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat))}} & berase_opcode[7:1])) | ({7{(load_opcode & do_wren)}} & wren_opcode[7:1])) | ({7{(load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren)))}} & b4addr_opcode[7:1])) | ({7{(load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren)))}} & exb4addr_opcode[7:1])) | ({7{shift_opcode}} & asmi_opcode_reg[6:0])), ((((((((((((((((((load_opcode & do_read_sid) & rsid_opcode[0]) | ((load_opcode & do_read_rdid) & rdid_opcode[0])) | ((((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & secprot_opcode[0])) | ((load_opcode & do_read) & read_opcode[0])) | ((load_opcode & do_fast_read) & fast_read_opcode[0])) | (((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat)) & rdummyclk_opcode[0])) | (((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat
+)) & wrvolatile_opcode[0])) | ((load_opcode & do_read_nonvolatile) & rnvdummyclk_opcode[0])) | ((load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren))) & write_opcode[0])) | (((load_opcode & do_read_stat) & (~ do_polling)) & rstat_opcode[0])) | (((load_opcode & do_read_stat) & do_polling) & rflagstat_opcode[0])) | ((((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & serase_opcode[0])) | ((((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & derase_opcode[0])) | ((((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat)) & berase_opcode[0])) | ((load_opcode & do_wren) & wren_opcode[0])) | ((load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren))) & b4addr_opcode[0])) | ((load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren))) & exb4addr_opcode[0]))};
+	assign
+		wire_asmi_opcode_reg_ena = {8{(load_opcode | shift_opcode)}};
+	// synopsys translate_off
+	initial
+		buf_empty_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) buf_empty_reg <= 1'b0;
+		else  buf_empty_reg <= wire_cmpr15_aeb;
+	// synopsys translate_off
+	initial
+		busy_delay_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) busy_delay_reg <= 1'b0;
+		else if  (power_up_reg == 1'b1)   busy_delay_reg <= busy_wire;
+	// synopsys translate_off
+	initial
+		busy_det_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) busy_det_reg <= 1'b0;
+		else  busy_det_reg <= (~ busy_wire);
+	// synopsys translate_off
+	initial
+		clr_rdid_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_rdid_reg <= 1'b0;
+		else  clr_rdid_reg <= end_operation;
+	// synopsys translate_off
+	initial
+		clr_read_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_read_reg <= 1'b0;
+		else  clr_read_reg <= ((do_read_sid | do_sec_prot) | (end_operation & (do_read | do_fast_read)));
+	// synopsys translate_off
+	initial
+		clr_read_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_read_reg2 <= 1'b0;
+		else  clr_read_reg2 <= clr_read_reg;
+	// synopsys translate_off
+	initial
+		clr_rstat_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_rstat_reg <= 1'b0;
+		else  clr_rstat_reg <= end_operation;
+	// synopsys translate_off
+	initial
+		clr_secprot_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_secprot_reg <= 1'b0;
+		else  clr_secprot_reg <= (((wire_spstage_cntr_q[1] & wire_spstage_cntr_q[0]) & end_read_flag_status) | do_read_sid);
+	// synopsys translate_off
+	initial
+		clr_secprot_reg1 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_secprot_reg1 <= 1'b0;
+		else  clr_secprot_reg1 <= clr_secprot_reg;
+	// synopsys translate_off
+	initial
+		clr_write_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_write_reg <= 1'b0;
+		else  clr_write_reg <= (((((((((((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) & end_operation) | write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))) | (((((((~ do_write) & (~ do_sec_erase)) & (~ do_bulk_erase)) & (~ do_die_erase)) & (~ do_4baddr)) & (~ do_ex4baddr)) & end_operation)) | do_read_sid) | do_sec_prot) | do_read) | do_fast_read);
+	// synopsys translate_off
+	initial
+		clr_write_reg2 = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) clr_write_reg2 <= 1'b0;
+		else  clr_write_reg2 <= clr_write_reg;
+	// synopsys translate_off
+	initial
+		cnt_bfend_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) cnt_bfend_reg <= 1'b0;
+		else  cnt_bfend_reg <= cnt_bfend_wire_in;
+	// synopsys translate_off
+	initial
+		do_wrmemadd_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) do_wrmemadd_reg <= 1'b0;
+		else  do_wrmemadd_reg <= (wire_wrstage_cntr_q[1] & wire_wrstage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		dummyclk_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) dummyclk_reg <= 4'b0;
+		else  dummyclk_reg <= {volatile_reg[7], (volatile_reg[6] & (~ volatile_default_wire)), ((volatile_reg[5] & (~ volatile_default_wire)) | volatile_default_wire), (volatile_reg[4] & (~ volatile_default_wire))};
+	// synopsys translate_off
+	initial
+		dvalid_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) dvalid_reg <= 1'b0;
+		else if  (wire_dvalid_reg_ena == 1'b1) 
+			if (wire_dvalid_reg_sclr == 1'b1) dvalid_reg <= 1'b0;
+			else  dvalid_reg <= (end_read_byte & end_one_cyc_pos);
+	assign
+		wire_dvalid_reg_ena = (do_read | do_fast_read),
+		wire_dvalid_reg_sclr = (end_op_wire | end_operation);
+	// synopsys translate_off
+	initial
+		dvalid_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) dvalid_reg2 <= 1'b0;
+		else  dvalid_reg2 <= dvalid_reg;
+	// synopsys translate_off
+	initial
+		end1_cyc_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end1_cyc_reg <= 1'b0;
+		else  end1_cyc_reg <= end1_cyc_reg_in_wire;
+	// synopsys translate_off
+	initial
+		end1_cyc_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end1_cyc_reg2 <= 1'b0;
+		else  end1_cyc_reg2 <= end_one_cycle;
+	// synopsys translate_off
+	initial
+		end_op_hdlyreg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end_op_hdlyreg <= 1'b0;
+		else  end_op_hdlyreg <= end_operation;
+	// synopsys translate_off
+	initial
+		end_op_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end_op_reg <= 1'b0;
+		else  end_op_reg <= end_op_wire;
+	// synopsys translate_off
+	initial
+		end_pgwrop_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end_pgwrop_reg <= 1'b0;
+		else if  (wire_end_pgwrop_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) end_pgwrop_reg <= 1'b0;
+			else  end_pgwrop_reg <= buf_empty;
+	assign
+		wire_end_pgwrop_reg_ena = (((cnt_bfend_reg & do_write) & shift_pgwr_data) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		end_rbyte_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end_rbyte_reg <= 1'b0;
+		else if  (wire_end_rbyte_reg_ena == 1'b1) 
+			if (wire_end_rbyte_reg_sclr == 1'b1) end_rbyte_reg <= 1'b0;
+			else  end_rbyte_reg <= (((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0]));
+	assign
+		wire_end_rbyte_reg_ena = ((wire_mux2112_dataout | clr_endrbyte_wire) | addr_overdie),
+		wire_end_rbyte_reg_sclr = (clr_endrbyte_wire | addr_overdie);
+	// synopsys translate_off
+	initial
+		end_read_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) end_read_reg <= 1'b0;
+		else  end_read_reg <= ((((~ rden_wire) & (do_read | do_fast_read)) & data_valid_wire) & end_read_byte);
+	// synopsys translate_off
+	initial
+		fast_read_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) fast_read_reg <= 1'b0;
+		else if  (wire_fast_read_reg_ena == 1'b1) 
+			if (clr_read_wire == 1'b1) fast_read_reg <= 1'b0;
+			else  fast_read_reg <= fast_read;
+	assign
+		wire_fast_read_reg_ena = (((~ busy_wire) & rden_wire) | clr_read_wire);
+	// synopsys translate_off
+	initial
+		ill_erase_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) ill_erase_reg <= 1'b0;
+		else  ill_erase_reg <= (illegal_erase_dly_reg | illegal_erase_b4out_wire);
+	// synopsys translate_off
+	initial
+		ill_write_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) ill_write_reg <= 1'b0;
+		else  ill_write_reg <= (illegal_write_dly_reg | illegal_write_b4out_wire);
+	// synopsys translate_off
+	initial
+		illegal_erase_dly_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) illegal_erase_dly_reg <= 1'b0;
+		else if  (power_up_reg == 1'b1)   illegal_erase_dly_reg <= illegal_erase_b4out_wire;
+	// synopsys translate_off
+	initial
+		illegal_write_dly_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) illegal_write_dly_reg <= 1'b0;
+		else if  (power_up_reg == 1'b1)   illegal_write_dly_reg <= illegal_write_b4out_wire;
+	// synopsys translate_off
+	initial
+		illegal_write_prot_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) illegal_write_prot_reg <= 1'b0;
+		else  illegal_write_prot_reg <= do_write;
+	// synopsys translate_off
+	initial
+		max_cnt_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) max_cnt_reg <= 1'b0;
+		else  max_cnt_reg <= wire_cmpr14_aeb;
+	// synopsys translate_off
+	initial
+		maxcnt_shift_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) maxcnt_shift_reg <= 1'b0;
+		else  maxcnt_shift_reg <= (((reach_max_cnt & shift_bytes_wire) & wren_wire) & (~ do_write));
+	// synopsys translate_off
+	initial
+		maxcnt_shift_reg2 = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) maxcnt_shift_reg2 <= 1'b0;
+		else  maxcnt_shift_reg2 <= maxcnt_shift_reg;
+	// synopsys translate_off
+	initial
+		ncs_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) ncs_reg <= 1'b0;
+		else if  (ncs_reg_ena_wire == 1'b1) 
+			if (wire_ncs_reg_sclr == 1'b1) ncs_reg <= 1'b0;
+			else  ncs_reg <= 1'b1;
+	assign
+		wire_ncs_reg_sclr = (end_operation | addr_overdie_pos);
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[0:0] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[0:0] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[0:0] <= 1'b0;
+			else  pgwrbuf_dataout[0:0] <= wire_pgwrbuf_dataout_d[0:0];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[1:1] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[1:1] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[1:1] <= 1'b0;
+			else  pgwrbuf_dataout[1:1] <= wire_pgwrbuf_dataout_d[1:1];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[2:2] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[2:2] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[2:2] <= 1'b0;
+			else  pgwrbuf_dataout[2:2] <= wire_pgwrbuf_dataout_d[2:2];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[3:3] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[3:3] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[3:3] <= 1'b0;
+			else  pgwrbuf_dataout[3:3] <= wire_pgwrbuf_dataout_d[3:3];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[4:4] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[4:4] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[4:4] <= 1'b0;
+			else  pgwrbuf_dataout[4:4] <= wire_pgwrbuf_dataout_d[4:4];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[5:5] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[5:5] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[5:5] <= 1'b0;
+			else  pgwrbuf_dataout[5:5] <= wire_pgwrbuf_dataout_d[5:5];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[6:6] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[6:6] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[6:6] <= 1'b0;
+			else  pgwrbuf_dataout[6:6] <= wire_pgwrbuf_dataout_d[6:6];
+	// synopsys translate_off
+	initial
+		pgwrbuf_dataout[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_dataout[7:7] <= 1'b0;
+		else if  (wire_pgwrbuf_dataout_ena[7:7] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_dataout[7:7] <= 1'b0;
+			else  pgwrbuf_dataout[7:7] <= wire_pgwrbuf_dataout_d[7:7];
+	assign
+		wire_pgwrbuf_dataout_d = {(({7{read_bufdly}} & wire_scfifo13_q[7:1]) | ({7{(~ read_bufdly)}} & pgwrbuf_dataout[6:0])), (read_bufdly & wire_scfifo13_q[0])};
+	assign
+		wire_pgwrbuf_dataout_ena = {8{((read_bufdly | shift_pgwr_data) | clr_write_wire)}};
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[0:0] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[0:0] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[0:0] <= 1'b0;
+			else  pgwrbuf_quad_dataout[0:0] <= wire_pgwrbuf_quad_dataout_d[0:0];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[1:1] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[1:1] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[1:1] <= 1'b0;
+			else  pgwrbuf_quad_dataout[1:1] <= wire_pgwrbuf_quad_dataout_d[1:1];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[2:2] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[2:2] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[2:2] <= 1'b0;
+			else  pgwrbuf_quad_dataout[2:2] <= wire_pgwrbuf_quad_dataout_d[2:2];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[3:3] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[3:3] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[3:3] <= 1'b0;
+			else  pgwrbuf_quad_dataout[3:3] <= wire_pgwrbuf_quad_dataout_d[3:3];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[4:4] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[4:4] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[4:4] <= 1'b0;
+			else  pgwrbuf_quad_dataout[4:4] <= wire_pgwrbuf_quad_dataout_d[4:4];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[5:5] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[5:5] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[5:5] <= 1'b0;
+			else  pgwrbuf_quad_dataout[5:5] <= wire_pgwrbuf_quad_dataout_d[5:5];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[6:6] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[6:6] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[6:6] <= 1'b0;
+			else  pgwrbuf_quad_dataout[6:6] <= wire_pgwrbuf_quad_dataout_d[6:6];
+	// synopsys translate_off
+	initial
+		pgwrbuf_quad_dataout[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) pgwrbuf_quad_dataout[7:7] <= 1'b0;
+		else if  (wire_pgwrbuf_quad_dataout_ena[7:7] == 1'b1) 
+			if (clr_write_wire == 1'b1) pgwrbuf_quad_dataout[7:7] <= 1'b0;
+			else  pgwrbuf_quad_dataout[7:7] <= wire_pgwrbuf_quad_dataout_d[7:7];
+	assign
+		wire_pgwrbuf_quad_dataout_d = {(({4{read_bufdly}} & wire_scfifo13_q[7:4]) | ({4{(~ read_bufdly)}} & pgwrbuf_quad_dataout[3:0])), ({4{read_bufdly}} & wire_scfifo13_q[3:0])};
+	assign
+		wire_pgwrbuf_quad_dataout_ena = {8{((read_bufdly | shift_pgwr_data) | clr_write_wire)}};
+	// synopsys translate_off
+	initial
+		power_up_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) power_up_reg <= 1'b0;
+		else  power_up_reg <= (busy_wire | busy_delay_reg);
+	// synopsys translate_off
+	initial
+		quad_addr_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[0:0] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[0:0] == 1'b1)   quad_addr_reg[0:0] <= wire_quad_addr_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[1:1] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[1:1] == 1'b1)   quad_addr_reg[1:1] <= wire_quad_addr_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[2:2] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[2:2] == 1'b1)   quad_addr_reg[2:2] <= wire_quad_addr_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[3:3] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[3:3] == 1'b1)   quad_addr_reg[3:3] <= wire_quad_addr_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[4:4] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[4:4] == 1'b1)   quad_addr_reg[4:4] <= wire_quad_addr_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[5:5] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[5:5] == 1'b1)   quad_addr_reg[5:5] <= wire_quad_addr_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[6:6] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[6:6] == 1'b1)   quad_addr_reg[6:6] <= wire_quad_addr_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[7:7] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[7:7] == 1'b1)   quad_addr_reg[7:7] <= wire_quad_addr_reg_d[7:7];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[8:8] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[8:8] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[8:8] == 1'b1)   quad_addr_reg[8:8] <= wire_quad_addr_reg_d[8:8];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[9:9] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[9:9] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[9:9] == 1'b1)   quad_addr_reg[9:9] <= wire_quad_addr_reg_d[9:9];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[10:10] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[10:10] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[10:10] == 1'b1)   quad_addr_reg[10:10] <= wire_quad_addr_reg_d[10:10];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[11:11] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[11:11] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[11:11] == 1'b1)   quad_addr_reg[11:11] <= wire_quad_addr_reg_d[11:11];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[12:12] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[12:12] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[12:12] == 1'b1)   quad_addr_reg[12:12] <= wire_quad_addr_reg_d[12:12];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[13:13] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[13:13] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[13:13] == 1'b1)   quad_addr_reg[13:13] <= wire_quad_addr_reg_d[13:13];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[14:14] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[14:14] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[14:14] == 1'b1)   quad_addr_reg[14:14] <= wire_quad_addr_reg_d[14:14];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[15:15] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[15:15] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[15:15] == 1'b1)   quad_addr_reg[15:15] <= wire_quad_addr_reg_d[15:15];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[16:16] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[16:16] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[16:16] == 1'b1)   quad_addr_reg[16:16] <= wire_quad_addr_reg_d[16:16];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[17:17] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[17:17] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[17:17] == 1'b1)   quad_addr_reg[17:17] <= wire_quad_addr_reg_d[17:17];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[18:18] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[18:18] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[18:18] == 1'b1)   quad_addr_reg[18:18] <= wire_quad_addr_reg_d[18:18];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[19:19] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[19:19] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[19:19] == 1'b1)   quad_addr_reg[19:19] <= wire_quad_addr_reg_d[19:19];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[20:20] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[20:20] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[20:20] == 1'b1)   quad_addr_reg[20:20] <= wire_quad_addr_reg_d[20:20];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[21:21] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[21:21] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[21:21] == 1'b1)   quad_addr_reg[21:21] <= wire_quad_addr_reg_d[21:21];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[22:22] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[22:22] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[22:22] == 1'b1)   quad_addr_reg[22:22] <= wire_quad_addr_reg_d[22:22];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[23:23] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[23:23] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[23:23] == 1'b1)   quad_addr_reg[23:23] <= wire_quad_addr_reg_d[23:23];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[24:24] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[24:24] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[24:24] == 1'b1)   quad_addr_reg[24:24] <= wire_quad_addr_reg_d[24:24];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[25:25] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[25:25] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[25:25] == 1'b1)   quad_addr_reg[25:25] <= wire_quad_addr_reg_d[25:25];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[26:26] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[26:26] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[26:26] == 1'b1)   quad_addr_reg[26:26] <= wire_quad_addr_reg_d[26:26];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[27:27] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[27:27] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[27:27] == 1'b1)   quad_addr_reg[27:27] <= wire_quad_addr_reg_d[27:27];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[28:28] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[28:28] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[28:28] == 1'b1)   quad_addr_reg[28:28] <= wire_quad_addr_reg_d[28:28];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[29:29] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[29:29] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[29:29] == 1'b1)   quad_addr_reg[29:29] <= wire_quad_addr_reg_d[29:29];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[30:30] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[30:30] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[30:30] == 1'b1)   quad_addr_reg[30:30] <= wire_quad_addr_reg_d[30:30];
+	// synopsys translate_off
+	initial
+		quad_addr_reg[31:31] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) quad_addr_reg[31:31] <= 1'b0;
+		else if  (wire_quad_addr_reg_ena[31:31] == 1'b1)   quad_addr_reg[31:31] <= wire_quad_addr_reg_d[31:31];
+	assign
+		wire_quad_addr_reg_d = {(((not_busy & addr[31]) | (stage3_wire & quad_addr_reg[27])) | (addr_overdie & addr_reg_overdie[31])), (((not_busy & addr[30]) | (stage3_wire & quad_addr_reg[26])) | (addr_overdie & addr_reg_overdie[30])), (((not_busy & addr[29]) | (stage3_wire & quad_addr_reg[25])) | (addr_overdie & addr_reg_overdie[29])), (((not_busy & addr[28]) | (stage3_wire & quad_addr_reg[24])) | (addr_overdie & addr_reg_overdie[28])), (((not_busy & addr[27]) | (stage3_wire & quad_addr_reg[23])) | (addr_overdie & addr_reg_overdie[27])), (((not_busy & addr[26]) | (stage3_wire & quad_addr_reg[22])) | (addr_overdie & addr_reg_overdie[26])), (((not_busy & addr[25]) | (stage3_wire & quad_addr_reg[21])) | (addr_overdie & addr_reg_overdie[25])), (((not_busy & addr[24]) | (stage3_wire & quad_addr_reg[20])) | (addr_overdie & addr_reg_overdie[24])), (((not_busy & addr[23]) | (stage3_wire & quad_addr_reg[19])) | (addr_overdie & addr_reg_overdie[23])), (((not_busy & addr[22]) | (stage3_wire & quad_addr_reg[18])) | (addr_overdie & addr_reg_overdie[22])), (((not_busy & addr[21]) | (stage3_wire & quad_addr_reg[17])) | (addr_overdie & addr_reg_overdie[21])), (((not_busy & addr[20]) | (stage3_wire & quad_addr_reg[16])) | (addr_overdie & addr_reg_overdie[20])), (((not_busy & addr[19]) | (stage3_wire & quad_addr_reg[15])) | (addr_overdie & addr_reg_overdie[19])), (((not_busy & addr[18]) | (stage3_wire & quad_addr_reg[14])) | (addr_overdie & addr_reg_overdie[18])), (((not_busy & addr[17]) | (stage3_wire & quad_addr_reg[13])) | (addr_overdie & addr_reg_overdie[17])), (((not_busy & addr[16]) | (stage3_wire & quad_addr_reg[12])) | (addr_overdie & addr_reg_overdie[16])), (((not_busy & addr[15]) | (stage3_wire & quad_addr_reg[11])) | (addr_overdie & addr_reg_overdie[15])), (((not_busy & addr[14]) | (stage3_wire & quad_addr_reg[10])) | (addr_overdie & addr_reg_overdie[14])), (((not_busy & addr[13]) | (stage3_wire & quad_addr_reg[9])) | (addr_overdie & addr_reg_overdie[13])), (((not_busy & addr[12]) | (stage3_wire & quad_addr_reg[8])) | (addr_overdie
+ & addr_reg_overdie[12])), (((not_busy & addr[11]) | (stage3_wire & quad_addr_reg[7])) | (addr_overdie & addr_reg_overdie[11])), (((not_busy & addr[10]) | (stage3_wire & quad_addr_reg[6])) | (addr_overdie & addr_reg_overdie[10])), (((not_busy & addr[9]) | (stage3_wire & quad_addr_reg[5])) | (addr_overdie & addr_reg_overdie[9])), (((not_busy & addr[8]) | (stage3_wire & quad_addr_reg[4])) | (addr_overdie & addr_reg_overdie[8])), (((not_busy & addr[7]) | (stage3_wire & quad_addr_reg[3])) | (addr_overdie & addr_reg_overdie[7])), (((not_busy & addr[6]) | (stage3_wire & quad_addr_reg[2])) | (addr_overdie & addr_reg_overdie[6])), (((not_busy & addr[5]) | (stage3_wire & quad_addr_reg[1])) | (addr_overdie & addr_reg_overdie[5])), (((not_busy & addr[4]) | (stage3_wire & quad_addr_reg[0])) | (addr_overdie & addr_reg_overdie[4])), ((({2{not_busy}} & addr[3:2]) | {2{stage3_wire}}) | ({2{addr_overdie}} & addr_reg_overdie[3:2])), (({2{not_busy}} & addr[1:0]) | ({2{addr_overdie}} & addr_reg_overdie[1:0]))};
+	assign
+		wire_quad_addr_reg_ena = {32{((((rden_wire | wren_wire) & not_busy) | (stage4_wire & addr_overdie)) | (stage3_wire & ((do_write & do_memadd) | (do_fast_read & (~ end_ophdly)))))}};
+	// synopsys translate_off
+	initial
+		rdid_out_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) rdid_out_reg <= 8'b0;
+		else if  (rdid_load == 1'b1)   rdid_out_reg <= {read_dout_reg[7:0]};
+	// synopsys translate_off
+	initial
+		read_add_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[0:0] <= 1'b0;
+		else if  (wire_read_add_reg_ena[0:0] == 1'b1)   read_add_reg[0:0] <= wire_read_add_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		read_add_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[1:1] <= 1'b0;
+		else if  (wire_read_add_reg_ena[1:1] == 1'b1)   read_add_reg[1:1] <= wire_read_add_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		read_add_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[2:2] <= 1'b0;
+		else if  (wire_read_add_reg_ena[2:2] == 1'b1)   read_add_reg[2:2] <= wire_read_add_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		read_add_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[3:3] <= 1'b0;
+		else if  (wire_read_add_reg_ena[3:3] == 1'b1)   read_add_reg[3:3] <= wire_read_add_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		read_add_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[4:4] <= 1'b0;
+		else if  (wire_read_add_reg_ena[4:4] == 1'b1)   read_add_reg[4:4] <= wire_read_add_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		read_add_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[5:5] <= 1'b0;
+		else if  (wire_read_add_reg_ena[5:5] == 1'b1)   read_add_reg[5:5] <= wire_read_add_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		read_add_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[6:6] <= 1'b0;
+		else if  (wire_read_add_reg_ena[6:6] == 1'b1)   read_add_reg[6:6] <= wire_read_add_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		read_add_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[7:7] <= 1'b0;
+		else if  (wire_read_add_reg_ena[7:7] == 1'b1)   read_add_reg[7:7] <= wire_read_add_reg_d[7:7];
+	// synopsys translate_off
+	initial
+		read_add_reg[8:8] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[8:8] <= 1'b0;
+		else if  (wire_read_add_reg_ena[8:8] == 1'b1)   read_add_reg[8:8] <= wire_read_add_reg_d[8:8];
+	// synopsys translate_off
+	initial
+		read_add_reg[9:9] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[9:9] <= 1'b0;
+		else if  (wire_read_add_reg_ena[9:9] == 1'b1)   read_add_reg[9:9] <= wire_read_add_reg_d[9:9];
+	// synopsys translate_off
+	initial
+		read_add_reg[10:10] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[10:10] <= 1'b0;
+		else if  (wire_read_add_reg_ena[10:10] == 1'b1)   read_add_reg[10:10] <= wire_read_add_reg_d[10:10];
+	// synopsys translate_off
+	initial
+		read_add_reg[11:11] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[11:11] <= 1'b0;
+		else if  (wire_read_add_reg_ena[11:11] == 1'b1)   read_add_reg[11:11] <= wire_read_add_reg_d[11:11];
+	// synopsys translate_off
+	initial
+		read_add_reg[12:12] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[12:12] <= 1'b0;
+		else if  (wire_read_add_reg_ena[12:12] == 1'b1)   read_add_reg[12:12] <= wire_read_add_reg_d[12:12];
+	// synopsys translate_off
+	initial
+		read_add_reg[13:13] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[13:13] <= 1'b0;
+		else if  (wire_read_add_reg_ena[13:13] == 1'b1)   read_add_reg[13:13] <= wire_read_add_reg_d[13:13];
+	// synopsys translate_off
+	initial
+		read_add_reg[14:14] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[14:14] <= 1'b0;
+		else if  (wire_read_add_reg_ena[14:14] == 1'b1)   read_add_reg[14:14] <= wire_read_add_reg_d[14:14];
+	// synopsys translate_off
+	initial
+		read_add_reg[15:15] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[15:15] <= 1'b0;
+		else if  (wire_read_add_reg_ena[15:15] == 1'b1)   read_add_reg[15:15] <= wire_read_add_reg_d[15:15];
+	// synopsys translate_off
+	initial
+		read_add_reg[16:16] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[16:16] <= 1'b0;
+		else if  (wire_read_add_reg_ena[16:16] == 1'b1)   read_add_reg[16:16] <= wire_read_add_reg_d[16:16];
+	// synopsys translate_off
+	initial
+		read_add_reg[17:17] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[17:17] <= 1'b0;
+		else if  (wire_read_add_reg_ena[17:17] == 1'b1)   read_add_reg[17:17] <= wire_read_add_reg_d[17:17];
+	// synopsys translate_off
+	initial
+		read_add_reg[18:18] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[18:18] <= 1'b0;
+		else if  (wire_read_add_reg_ena[18:18] == 1'b1)   read_add_reg[18:18] <= wire_read_add_reg_d[18:18];
+	// synopsys translate_off
+	initial
+		read_add_reg[19:19] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[19:19] <= 1'b0;
+		else if  (wire_read_add_reg_ena[19:19] == 1'b1)   read_add_reg[19:19] <= wire_read_add_reg_d[19:19];
+	// synopsys translate_off
+	initial
+		read_add_reg[20:20] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[20:20] <= 1'b0;
+		else if  (wire_read_add_reg_ena[20:20] == 1'b1)   read_add_reg[20:20] <= wire_read_add_reg_d[20:20];
+	// synopsys translate_off
+	initial
+		read_add_reg[21:21] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[21:21] <= 1'b0;
+		else if  (wire_read_add_reg_ena[21:21] == 1'b1)   read_add_reg[21:21] <= wire_read_add_reg_d[21:21];
+	// synopsys translate_off
+	initial
+		read_add_reg[22:22] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[22:22] <= 1'b0;
+		else if  (wire_read_add_reg_ena[22:22] == 1'b1)   read_add_reg[22:22] <= wire_read_add_reg_d[22:22];
+	// synopsys translate_off
+	initial
+		read_add_reg[23:23] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[23:23] <= 1'b0;
+		else if  (wire_read_add_reg_ena[23:23] == 1'b1)   read_add_reg[23:23] <= wire_read_add_reg_d[23:23];
+	// synopsys translate_off
+	initial
+		read_add_reg[24:24] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[24:24] <= 1'b0;
+		else if  (wire_read_add_reg_ena[24:24] == 1'b1)   read_add_reg[24:24] <= wire_read_add_reg_d[24:24];
+	// synopsys translate_off
+	initial
+		read_add_reg[25:25] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[25:25] <= 1'b0;
+		else if  (wire_read_add_reg_ena[25:25] == 1'b1)   read_add_reg[25:25] <= wire_read_add_reg_d[25:25];
+	// synopsys translate_off
+	initial
+		read_add_reg[26:26] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[26:26] <= 1'b0;
+		else if  (wire_read_add_reg_ena[26:26] == 1'b1)   read_add_reg[26:26] <= wire_read_add_reg_d[26:26];
+	// synopsys translate_off
+	initial
+		read_add_reg[27:27] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[27:27] <= 1'b0;
+		else if  (wire_read_add_reg_ena[27:27] == 1'b1)   read_add_reg[27:27] <= wire_read_add_reg_d[27:27];
+	// synopsys translate_off
+	initial
+		read_add_reg[28:28] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[28:28] <= 1'b0;
+		else if  (wire_read_add_reg_ena[28:28] == 1'b1)   read_add_reg[28:28] <= wire_read_add_reg_d[28:28];
+	// synopsys translate_off
+	initial
+		read_add_reg[29:29] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[29:29] <= 1'b0;
+		else if  (wire_read_add_reg_ena[29:29] == 1'b1)   read_add_reg[29:29] <= wire_read_add_reg_d[29:29];
+	// synopsys translate_off
+	initial
+		read_add_reg[30:30] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[30:30] <= 1'b0;
+		else if  (wire_read_add_reg_ena[30:30] == 1'b1)   read_add_reg[30:30] <= wire_read_add_reg_d[30:30];
+	// synopsys translate_off
+	initial
+		read_add_reg[31:31] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_add_reg[31:31] <= 1'b0;
+		else if  (wire_read_add_reg_ena[31:31] == 1'b1)   read_add_reg[31:31] <= wire_read_add_reg_d[31:31];
+	assign
+		wire_read_add_reg_d = {wire_read_add_cntr_q[31:0]};
+	assign
+		wire_read_add_reg_ena = {32{((end_read_byte & end_one_cyc_pos) & (~ end_operation))}};
+	// synopsys translate_off
+	initial
+		read_bufdly_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_bufdly_reg <= 1'b0;
+		else  read_bufdly_reg <= read_buf;
+	// synopsys translate_off
+	initial
+		read_data_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[0:0] <= 1'b0;
+		else if  (wire_read_data_reg_ena[0:0] == 1'b1)   read_data_reg[0:0] <= wire_read_data_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		read_data_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[1:1] <= 1'b0;
+		else if  (wire_read_data_reg_ena[1:1] == 1'b1)   read_data_reg[1:1] <= wire_read_data_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		read_data_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[2:2] <= 1'b0;
+		else if  (wire_read_data_reg_ena[2:2] == 1'b1)   read_data_reg[2:2] <= wire_read_data_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		read_data_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[3:3] <= 1'b0;
+		else if  (wire_read_data_reg_ena[3:3] == 1'b1)   read_data_reg[3:3] <= wire_read_data_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		read_data_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[4:4] <= 1'b0;
+		else if  (wire_read_data_reg_ena[4:4] == 1'b1)   read_data_reg[4:4] <= wire_read_data_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		read_data_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[5:5] <= 1'b0;
+		else if  (wire_read_data_reg_ena[5:5] == 1'b1)   read_data_reg[5:5] <= wire_read_data_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		read_data_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[6:6] <= 1'b0;
+		else if  (wire_read_data_reg_ena[6:6] == 1'b1)   read_data_reg[6:6] <= wire_read_data_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		read_data_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_data_reg[7:7] <= 1'b0;
+		else if  (wire_read_data_reg_ena[7:7] == 1'b1)   read_data_reg[7:7] <= wire_read_data_reg_d[7:7];
+	assign
+		wire_read_data_reg_d = {read_data_reg_in_wire[7:0]};
+	assign
+		wire_read_data_reg_ena = {8{(((((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & end_one_cyc_pos) & end_read_byte)}};
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[0:0] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[0:0] == 1'b1)   read_dout_quad_reg[0:0] <= wire_read_dout_quad_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[1:1] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[1:1] == 1'b1)   read_dout_quad_reg[1:1] <= wire_read_dout_quad_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[2:2] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[2:2] == 1'b1)   read_dout_quad_reg[2:2] <= wire_read_dout_quad_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[3:3] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[3:3] == 1'b1)   read_dout_quad_reg[3:3] <= wire_read_dout_quad_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[4:4] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[4:4] == 1'b1)   read_dout_quad_reg[4:4] <= wire_read_dout_quad_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[5:5] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[5:5] == 1'b1)   read_dout_quad_reg[5:5] <= wire_read_dout_quad_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[6:6] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[6:6] == 1'b1)   read_dout_quad_reg[6:6] <= wire_read_dout_quad_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		read_dout_quad_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_quad_reg[7:7] <= 1'b0;
+		else if  (wire_read_dout_quad_reg_ena[7:7] == 1'b1)   read_dout_quad_reg[7:7] <= wire_read_dout_quad_reg_d[7:7];
+	assign
+		wire_read_dout_quad_reg_d = {read_dout_quad_reg[3:0], dataout_wire[3:0]};
+	assign
+		wire_read_dout_quad_reg_ena = {8{(stage4_wire & do_fast_read)}};
+	// synopsys translate_off
+	initial
+		read_dout_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[0:0] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[0:0] == 1'b1)   read_dout_reg[0:0] <= wire_read_dout_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		read_dout_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[1:1] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[1:1] == 1'b1)   read_dout_reg[1:1] <= wire_read_dout_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		read_dout_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[2:2] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[2:2] == 1'b1)   read_dout_reg[2:2] <= wire_read_dout_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		read_dout_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[3:3] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[3:3] == 1'b1)   read_dout_reg[3:3] <= wire_read_dout_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		read_dout_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[4:4] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[4:4] == 1'b1)   read_dout_reg[4:4] <= wire_read_dout_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		read_dout_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[5:5] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[5:5] == 1'b1)   read_dout_reg[5:5] <= wire_read_dout_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		read_dout_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[6:6] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[6:6] == 1'b1)   read_dout_reg[6:6] <= wire_read_dout_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		read_dout_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dout_reg[7:7] <= 1'b0;
+		else if  (wire_read_dout_reg_ena[7:7] == 1'b1)   read_dout_reg[7:7] <= wire_read_dout_reg_d[7:7];
+	assign
+		wire_read_dout_reg_d = {read_dout_reg[6:0], (data0out_wire | dataout_wire[1])};
+	assign
+		wire_read_dout_reg_ena = {8{((stage4_wire & ((do_read | do_fast_read) | do_read_sid)) | (stage3_wire & (((do_read_stat | do_read_rdid) | do_read_volatile) | do_read_nonvolatile)))}};
+	// synopsys translate_off
+	initial
+		read_dummyclk_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_dummyclk_reg <= 1'b0;
+		else if  (wire_read_dummyclk_reg_ena == 1'b1) 
+			if (clr_freadepcq_wire == 1'b1) read_dummyclk_reg <= 1'b0;
+			else  read_dummyclk_reg <= read_dummyclk;
+	assign
+		wire_read_dummyclk_reg_ena = ((~ busy_wire) | clr_freadepcq_wire);
+	// synopsys translate_off
+	initial
+		read_nonvdummyclk_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_nonvdummyclk_reg <= 1'b0;
+		else if  (wire_read_nonvdummyclk_reg_ena == 1'b1) 
+			if (clr_freadepcq_wire == 1'b1) read_nonvdummyclk_reg <= 1'b0;
+			else  read_nonvdummyclk_reg <= ((~ read_dummyclk_wire) & volatile_empty_wire);
+	assign
+		wire_read_nonvdummyclk_reg_ena = ((~ busy_wire) | clr_freadepcq_wire);
+	// synopsys translate_off
+	initial
+		read_rdid_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_rdid_reg <= 1'b0;
+		else if  (wire_read_rdid_reg_ena == 1'b1) 
+			if (clr_rdid_wire == 1'b1) read_rdid_reg <= 1'b0;
+			else  read_rdid_reg <= read_rdid;
+	assign
+		wire_read_rdid_reg_ena = ((~ busy_wire) | clr_rdid_wire);
+	// synopsys translate_off
+	initial
+		read_status_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) read_status_reg <= 1'b0;
+		else if  (wire_read_status_reg_ena == 1'b1) 
+			if (clr_rstat_wire == 1'b1) read_status_reg <= 1'b0;
+			else  read_status_reg <= read_status;
+	assign
+		wire_read_status_reg_ena = ((~ busy_wire) | clr_rstat_wire);
+	// synopsys translate_off
+	initial
+		reset_addren_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) reset_addren_reg <= 1'b0;
+		else if  (wire_reset_addren_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) reset_addren_reg <= 1'b0;
+			else  reset_addren_reg <= en4b_addr;
+	assign
+		wire_reset_addren_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		sec_erase_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) sec_erase_reg <= 1'b0;
+		else if  (wire_sec_erase_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) sec_erase_reg <= 1'b0;
+			else  sec_erase_reg <= sector_erase;
+	assign
+		wire_sec_erase_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		sec_prot_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) sec_prot_reg <= 1'b0;
+		else if  (wire_sec_prot_reg_ena == 1'b1) 
+			if (clr_secprot_wire == 1'b1) sec_prot_reg <= 1'b0;
+			else  sec_prot_reg <= sector_protect;
+	assign
+		wire_sec_prot_reg_ena = (((~ busy_wire) & wren_wire) | clr_secprot_wire);
+	// synopsys translate_off
+	initial
+		shftpgwr_data_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) shftpgwr_data_reg <= 1'b0;
+		else
+			if (end_operation == 1'b1) shftpgwr_data_reg <= 1'b0;
+			else  shftpgwr_data_reg <= (((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		shift_op_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) shift_op_reg <= 1'b0;
+		else  shift_op_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		sprot_rstat_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) sprot_rstat_reg <= 1'b0;
+		else
+			if (clr_secprot_wire == 1'b1) sprot_rstat_reg <= 1'b0;
+			else  sprot_rstat_reg <= ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		stage2_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) stage2_reg <= 1'b0;
+		else  stage2_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		stage3_dly_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) stage3_dly_reg <= 1'b0;
+		else  stage3_dly_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		stage3_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) stage3_reg <= 1'b0;
+		else  stage3_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
+	// synopsys translate_off
+	initial
+		stage4_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) stage4_reg <= 1'b0;
+		else  stage4_reg <= (wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0]));
+	// synopsys translate_off
+	initial
+		start_dummyclk_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) start_dummyclk_reg <= 1'b0;
+		else if  (wire_start_dummyclk_reg_ena == 1'b1) 
+			if (wire_start_dummyclk_reg_sclr == 1'b1) start_dummyclk_reg <= 1'b0;
+			else  start_dummyclk_reg <= (do_read | do_fast_read);
+	assign
+		wire_start_dummyclk_reg_ena = ((((end_one_cycle & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0])) | (clr_read_wire | addr_overdie)),
+		wire_start_dummyclk_reg_sclr = (clr_read_wire | addr_overdie);
+	// synopsys translate_off
+	initial
+		start_sppoll_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) start_sppoll_reg <= 1'b0;
+		else if  (wire_start_sppoll_reg_ena == 1'b1) 
+			if (clr_secprot_wire == 1'b1) start_sppoll_reg <= 1'b0;
+			else  start_sppoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
+	assign
+		wire_start_sppoll_reg_ena = (((do_sprot_rstat & do_polling) & end_one_cycle) | clr_secprot_wire);
+	// synopsys translate_off
+	initial
+		start_sppoll_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) start_sppoll_reg2 <= 1'b0;
+		else
+			if (clr_secprot_wire == 1'b1) start_sppoll_reg2 <= 1'b0;
+			else  start_sppoll_reg2 <= start_sppoll_reg;
+	// synopsys translate_off
+	initial
+		start_wrpoll_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) start_wrpoll_reg <= 1'b0;
+		else if  (wire_start_wrpoll_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) start_wrpoll_reg <= 1'b0;
+			else  start_wrpoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
+	assign
+		wire_start_wrpoll_reg_ena = (((do_write_rstat & do_polling) & end_one_cycle) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		start_wrpoll_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) start_wrpoll_reg2 <= 1'b0;
+		else
+			if (clr_write_wire == 1'b1) start_wrpoll_reg2 <= 1'b0;
+			else  start_wrpoll_reg2 <= start_wrpoll_reg;
+	// synopsys translate_off
+	initial
+		statreg_int[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[0:0] <= 1'b0;
+		else if  (wire_statreg_int_ena[0:0] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[0:0] <= 1'b0;
+			else  statreg_int[0:0] <= wire_statreg_int_d[0:0];
+	// synopsys translate_off
+	initial
+		statreg_int[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[1:1] <= 1'b0;
+		else if  (wire_statreg_int_ena[1:1] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[1:1] <= 1'b0;
+			else  statreg_int[1:1] <= wire_statreg_int_d[1:1];
+	// synopsys translate_off
+	initial
+		statreg_int[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[2:2] <= 1'b0;
+		else if  (wire_statreg_int_ena[2:2] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[2:2] <= 1'b0;
+			else  statreg_int[2:2] <= wire_statreg_int_d[2:2];
+	// synopsys translate_off
+	initial
+		statreg_int[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[3:3] <= 1'b0;
+		else if  (wire_statreg_int_ena[3:3] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[3:3] <= 1'b0;
+			else  statreg_int[3:3] <= wire_statreg_int_d[3:3];
+	// synopsys translate_off
+	initial
+		statreg_int[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[4:4] <= 1'b0;
+		else if  (wire_statreg_int_ena[4:4] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[4:4] <= 1'b0;
+			else  statreg_int[4:4] <= wire_statreg_int_d[4:4];
+	// synopsys translate_off
+	initial
+		statreg_int[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[5:5] <= 1'b0;
+		else if  (wire_statreg_int_ena[5:5] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[5:5] <= 1'b0;
+			else  statreg_int[5:5] <= wire_statreg_int_d[5:5];
+	// synopsys translate_off
+	initial
+		statreg_int[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[6:6] <= 1'b0;
+		else if  (wire_statreg_int_ena[6:6] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[6:6] <= 1'b0;
+			else  statreg_int[6:6] <= wire_statreg_int_d[6:6];
+	// synopsys translate_off
+	initial
+		statreg_int[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_int[7:7] <= 1'b0;
+		else if  (wire_statreg_int_ena[7:7] == 1'b1) 
+			if (clr_rstat_wire == 1'b1) statreg_int[7:7] <= 1'b0;
+			else  statreg_int[7:7] <= wire_statreg_int_d[7:7];
+	assign
+		wire_statreg_int_d = {read_dout_reg[7:0]};
+	assign
+		wire_statreg_int_ena = {8{(((end_operation | ((do_polling & end_one_cyc_pos) & stage3_dly_reg)) & do_read_stat) | clr_rstat_wire)}};
+	// synopsys translate_off
+	initial
+		statreg_out[0:0] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[0:0] <= 1'b0;
+		else if  (wire_statreg_out_ena[0:0] == 1'b1)   statreg_out[0:0] <= wire_statreg_out_d[0:0];
+	// synopsys translate_off
+	initial
+		statreg_out[1:1] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[1:1] <= 1'b0;
+		else if  (wire_statreg_out_ena[1:1] == 1'b1)   statreg_out[1:1] <= wire_statreg_out_d[1:1];
+	// synopsys translate_off
+	initial
+		statreg_out[2:2] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[2:2] <= 1'b0;
+		else if  (wire_statreg_out_ena[2:2] == 1'b1)   statreg_out[2:2] <= wire_statreg_out_d[2:2];
+	// synopsys translate_off
+	initial
+		statreg_out[3:3] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[3:3] <= 1'b0;
+		else if  (wire_statreg_out_ena[3:3] == 1'b1)   statreg_out[3:3] <= wire_statreg_out_d[3:3];
+	// synopsys translate_off
+	initial
+		statreg_out[4:4] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[4:4] <= 1'b0;
+		else if  (wire_statreg_out_ena[4:4] == 1'b1)   statreg_out[4:4] <= wire_statreg_out_d[4:4];
+	// synopsys translate_off
+	initial
+		statreg_out[5:5] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[5:5] <= 1'b0;
+		else if  (wire_statreg_out_ena[5:5] == 1'b1)   statreg_out[5:5] <= wire_statreg_out_d[5:5];
+	// synopsys translate_off
+	initial
+		statreg_out[6:6] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[6:6] <= 1'b0;
+		else if  (wire_statreg_out_ena[6:6] == 1'b1)   statreg_out[6:6] <= wire_statreg_out_d[6:6];
+	// synopsys translate_off
+	initial
+		statreg_out[7:7] = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) statreg_out[7:7] <= 1'b0;
+		else if  (wire_statreg_out_ena[7:7] == 1'b1)   statreg_out[7:7] <= wire_statreg_out_d[7:7];
+	assign
+		wire_statreg_out_d = {read_dout_reg[7:0]};
+	assign
+		wire_statreg_out_ena = {8{((((((((end_ophdly & do_read_stat) & (~ do_write)) & (~ do_sec_erase)) & (~ do_die_erase)) & (~ do_bulk_erase)) & (~ do_sec_prot)) & (~ do_4baddr)) & (~ do_ex4baddr))}};
+	// synopsys translate_off
+	initial
+		streg_datain_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) streg_datain_reg <= 1'b0;
+		else if  (wire_streg_datain_reg_ena == 1'b1) 
+			if (end_operation == 1'b1) streg_datain_reg <= 1'b0;
+			else  streg_datain_reg <= wrstat_dreg[7];
+	assign
+		wire_streg_datain_reg_ena = (((do_sec_prot & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0]) | end_operation);
+	// synopsys translate_off
+	initial
+		volatile_reg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[0:0] <= 1'b0;
+		else if  (wire_volatile_reg_ena[0:0] == 1'b1)   volatile_reg[0:0] <= wire_volatile_reg_d[0:0];
+	// synopsys translate_off
+	initial
+		volatile_reg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[1:1] <= 1'b0;
+		else if  (wire_volatile_reg_ena[1:1] == 1'b1)   volatile_reg[1:1] <= wire_volatile_reg_d[1:1];
+	// synopsys translate_off
+	initial
+		volatile_reg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[2:2] <= 1'b0;
+		else if  (wire_volatile_reg_ena[2:2] == 1'b1)   volatile_reg[2:2] <= wire_volatile_reg_d[2:2];
+	// synopsys translate_off
+	initial
+		volatile_reg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[3:3] <= 1'b0;
+		else if  (wire_volatile_reg_ena[3:3] == 1'b1)   volatile_reg[3:3] <= wire_volatile_reg_d[3:3];
+	// synopsys translate_off
+	initial
+		volatile_reg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[4:4] <= 1'b0;
+		else if  (wire_volatile_reg_ena[4:4] == 1'b1)   volatile_reg[4:4] <= wire_volatile_reg_d[4:4];
+	// synopsys translate_off
+	initial
+		volatile_reg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[5:5] <= 1'b0;
+		else if  (wire_volatile_reg_ena[5:5] == 1'b1)   volatile_reg[5:5] <= wire_volatile_reg_d[5:5];
+	// synopsys translate_off
+	initial
+		volatile_reg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[6:6] <= 1'b0;
+		else if  (wire_volatile_reg_ena[6:6] == 1'b1)   volatile_reg[6:6] <= wire_volatile_reg_d[6:6];
+	// synopsys translate_off
+	initial
+		volatile_reg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) volatile_reg[7:7] <= 1'b0;
+		else if  (wire_volatile_reg_ena[7:7] == 1'b1)   volatile_reg[7:7] <= wire_volatile_reg_d[7:7];
+	assign
+		wire_volatile_reg_d = {({8{(do_read_volatile | do_read_nonvolatile)}} & read_dout_reg[7:0])};
+	assign
+		wire_volatile_reg_ena = {8{(((do_read_volatile | do_read_nonvolatile) & stage3_dly_reg) & (~ do_addr_overdie))}};
+	// synopsys translate_off
+	initial
+		write_prot_reg = 0;
+	// synopsys translate_on
+	always @ ( negedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) write_prot_reg <= 1'b0;
+		else if  (wire_write_prot_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) write_prot_reg <= 1'b0;
+			else  write_prot_reg <= ((((do_write | do_sec_erase) & (~ prot_wire[0])) & (((~ mask_prot_comp_ntb[9]) & (~ tb_wire)) | ((~ mask_prot_comp_tb[9]) & tb_wire))) | be_write_prot);
+	assign
+		wire_write_prot_reg_ena = (((((((do_sec_erase | do_write) | do_bulk_erase) | do_die_erase) & (~ wire_wrstage_cntr_q[1])) & wire_wrstage_cntr_q[0]) & end_ophdly) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		write_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) write_reg <= 1'b0;
+		else if  (wire_write_reg_ena == 1'b1) 
+			if (clr_write_wire == 1'b1) write_reg <= 1'b0;
+			else  write_reg <= write;
+	assign
+		wire_write_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
+	// synopsys translate_off
+	initial
+		write_rstat_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) write_rstat_reg <= 1'b0;
+		else
+			if (clr_write_wire == 1'b1) write_rstat_reg <= 1'b0;
+			else  write_rstat_reg <= ((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & (((~ wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) | (wire_wrstage_cntr_q[1] & (~ wire_wrstage_cntr_q[0]))));
+	// synopsys translate_off
+	initial
+		wrstat_dreg[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[0:0] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[0:0] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[0:0] <= 1'b0;
+			else  wrstat_dreg[0:0] <= wire_wrstat_dreg_d[0:0];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[1:1] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[1:1] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[1:1] <= 1'b0;
+			else  wrstat_dreg[1:1] <= wire_wrstat_dreg_d[1:1];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[2:2] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[2:2] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[2:2] <= 1'b0;
+			else  wrstat_dreg[2:2] <= wire_wrstat_dreg_d[2:2];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[3:3] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[3:3] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[3:3] <= 1'b0;
+			else  wrstat_dreg[3:3] <= wire_wrstat_dreg_d[3:3];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[4:4] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[4:4] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[4:4] <= 1'b0;
+			else  wrstat_dreg[4:4] <= wire_wrstat_dreg_d[4:4];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[5:5] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[5:5] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[5:5] <= 1'b0;
+			else  wrstat_dreg[5:5] <= wire_wrstat_dreg_d[5:5];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[6:6] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[6:6] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[6:6] <= 1'b0;
+			else  wrstat_dreg[6:6] <= wire_wrstat_dreg_d[6:6];
+	// synopsys translate_off
+	initial
+		wrstat_dreg[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clkin_wire or  posedge reset)
+		if (reset == 1'b1) wrstat_dreg[7:7] <= 1'b0;
+		else if  (wire_wrstat_dreg_ena[7:7] == 1'b1) 
+			if (clr_secprot_wire == 1'b1) wrstat_dreg[7:7] <= 1'b0;
+			else  wrstat_dreg[7:7] <= wire_wrstat_dreg_d[7:7];
+	assign
+		wire_wrstat_dreg_d = {(({7{not_busy}} & datain[7:1]) | ({7{stage3_wire}} & wrstat_dreg[6:0])), (not_busy & datain[0])};
+	assign
+		wire_wrstat_dreg_ena = {8{(((wren_wire & not_busy) | (((do_sec_prot & stage3_wire) & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0])) | clr_secprot_wire)}};
+	lpm_compare   cmpr14
+	( 
+	.aeb(wire_cmpr14_aeb),
+	.agb(),
+	.ageb(),
+	.alb(),
+	.aleb(),
+	.aneb(),
+	.dataa({page_size_wire[8:0]}),
+	.datab({wire_pgwr_data_cntr_q[8:0]})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.clken(1'b1),
+	.clock(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cmpr14.lpm_width = 9,
+		cmpr14.lpm_type = "lpm_compare";
+	lpm_compare   cmpr15
+	( 
+	.aeb(wire_cmpr15_aeb),
+	.agb(),
+	.ageb(),
+	.alb(),
+	.aleb(),
+	.aneb(),
+	.dataa({wire_pgwr_data_cntr_q[8:0]}),
+	.datab({wire_pgwr_read_cntr_q[8:0]})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.clken(1'b1),
+	.clock(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cmpr15.lpm_width = 9,
+		cmpr15.lpm_type = "lpm_compare";
+	lpm_compare   cmpr8
+	( 
+	.aeb(wire_cmpr8_aeb),
+	.agb(),
+	.ageb(),
+	.alb(),
+	.aleb(),
+	.aneb(),
+	.dataa({wire_dummyclk_cntr_q}),
+	.datab({dummyclk_reg[3:0]})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.clken(1'b1),
+	.clock(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cmpr8.lpm_width = 4,
+		cmpr8.lpm_type = "lpm_compare";
+	lpm_counter   dummyclk_cntr
+	( 
+	.aclr(reset),
+	.clk_en(((do_fast_read & start_dummyclk_reg) | (clr_read_wire | addr_overdie))),
+	.clock((~ clkin_wire)),
+	.cout(),
+	.eq(),
+	.q(wire_dummyclk_cntr_q),
+	.sclr((clr_read_wire | addr_overdie))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.cnt_en(1'b1),
+	.data({4{1'b0}}),
+	.sload(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		dummyclk_cntr.lpm_direction = "UP",
+		dummyclk_cntr.lpm_port_updown = "PORT_UNUSED",
+		dummyclk_cntr.lpm_width = 4,
+		dummyclk_cntr.lpm_type = "lpm_counter";
+	lpm_counter   pgwr_data_cntr
+	( 
+	.aclr(reset),
+	.clk_en(((((shift_bytes_wire & wren_wire) & (~ reach_max_cnt)) & (~ do_write)) | clr_write_wire2)),
+	.clock(clkin_wire),
+	.cout(),
+	.eq(),
+	.q(wire_pgwr_data_cntr_q),
+	.sclr(clr_write_wire2)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.cnt_en(1'b1),
+	.data({9{1'b0}}),
+	.sload(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pgwr_data_cntr.lpm_direction = "UP",
+		pgwr_data_cntr.lpm_port_updown = "PORT_UNUSED",
+		pgwr_data_cntr.lpm_width = 9,
+		pgwr_data_cntr.lpm_type = "lpm_counter";
+	lpm_counter   pgwr_read_cntr
+	( 
+	.aclr(reset),
+	.clk_en((read_buf | clr_write_wire2)),
+	.clock(clkin_wire),
+	.cout(),
+	.eq(),
+	.q(wire_pgwr_read_cntr_q),
+	.sclr(clr_write_wire2)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.cnt_en(1'b1),
+	.data({9{1'b0}}),
+	.sload(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		pgwr_read_cntr.lpm_direction = "UP",
+		pgwr_read_cntr.lpm_port_updown = "PORT_UNUSED",
+		pgwr_read_cntr.lpm_width = 9,
+		pgwr_read_cntr.lpm_type = "lpm_counter";
+	lpm_counter   read_add_cntr
+	( 
+	.aclr(reset),
+	.clk_en((((rden_wire & not_busy) | data_valid_wire) | add_rollover)),
+	.clock(clkin_wire),
+	.cout(),
+	.data({{1{1'b0}}, addr[31:0]}),
+	.eq(),
+	.q(wire_read_add_cntr_q),
+	.sclr(add_rollover),
+	.sload((rden_wire & not_busy))
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.cnt_en(1'b1),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		read_add_cntr.lpm_direction = "UP",
+		read_add_cntr.lpm_port_updown = "PORT_UNUSED",
+		read_add_cntr.lpm_width = 33,
+		read_add_cntr.lpm_type = "lpm_counter";
+	assign		wire_mux211_dataout = (((wire_stage_cntr_q[1] & (do_write | do_fast_read)) & (~ do_read_stat)) === 1'b1) ? (((~ wire_gen_cntr_q[2]) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]) : ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0]));
+	assign		wire_mux2110_dataout = (do_fast_read === 1'b1) ? dvalid_reg : dvalid_reg2;
+	assign		wire_mux2111_dataout = (do_fast_read === 1'b1) ? (((((do_fast_read & end_fast_read) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])) | clr_read_wire2) : (((((do_read | do_fast_read) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | clr_read_wire2);
+	assign		wire_mux2112_dataout = (do_fast_read === 1'b1) ? (((~ wire_gen_cntr_q[2]) & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])) : ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]);
+	assign		wire_mux2116_dataout = (do_write === 1'b1) ? (((~ wire_gen_cntr_q[2]) & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])) : ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]);
+	assign		wire_mux212_dataout = (((((do_write | do_sec_prot) | do_sec_erase) | do_bulk_erase) | do_die_erase) === 1'b1) ? end1_cyc_dlyncs_in_wire : end1_cyc_normal_in_wire;
+	assign		wire_mux213_dataout = (do_fast_read === 1'b1) ? end_add_cycle_mux_datab_wire : ((wire_addbyte_cntr_q[2] & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0]));
+	assign		wire_mux214a_dataout = ((stage3_wire & ((do_write & do_memadd) | do_fast_read)) === 1'b1) ? {add_msb_quad_reg[3:0]} : {3'b110, add_msb_reg};
+	assign		wire_mux219a_dataout = (do_fast_read === 1'b1) ? {read_dout_quad_reg[7:0]} : {read_dout_reg[7:0]};
+	scfifo   scfifo13
+	( 
+	.aclr(reset),
+	.almost_empty(),
+	.almost_full(),
+	.clock(clkin_wire),
+	.data({datain[7:0]}),
+	.eccstatus(),
+	.empty(),
+	.full(),
+	.q(wire_scfifo13_q),
+	.rdreq((read_buf | dummy_read_buf)),
+	.sclr(clr_write_wire2),
+	.usedw(),
+	.wrreq(((shift_bytes_wire & wren_wire) & (~ do_write))));
+	defparam
+		scfifo13.lpm_numwords = 258,
+		scfifo13.lpm_width = 8,
+		scfifo13.lpm_widthu = 9,
+		scfifo13.use_eab = "ON",
+		scfifo13.lpm_type = "scfifo";
+	assign
+		add_rollover = add_rollover_reg,
+		addr_die_diff = (~ (wire_read_add_cntr_q[25] & addr_die_diff_reg)),
+		addr_overdie = ((((rden_wire & (do_read | do_fast_read)) & ((addr_die_diff & wire_read_add_cntr_q[25]) | wire_read_add_cntr_q[26])) & stage4_wire) & (~ do_addr_overdie)),
+		addr_overdie_pos = addr_overdie_delay_reg,
+		addr_reg_overdie = wire_read_add_cntr_q[31:0],
+		asmi_dataoe = {dataoe_wire[3:0]},
+		asmi_dclk = clkin_wire,
+		asmi_scein = scein_wire,
+		asmi_sdoin = {datain_wire[3:0]},
+		b4addr_opcode = 8'b10110111,
+		be_write_prot = ((do_bulk_erase | do_die_erase) & (((bp3_wire | bp2_wire) | bp1_wire) | bp0_wire)),
+		berase_opcode = {8{1'b0}},
+		bp0_wire = (statreg_int[2] & (~ do_polling)),
+		bp1_wire = (statreg_int[3] & (~ do_polling)),
+		bp2_wire = (statreg_int[4] & (~ do_polling)),
+		bp3_wire = (statreg_int[6] & (~ do_polling)),
+		buf_empty = buf_empty_reg,
+		bulk_erase_wire = 1'b0,
+		busy = (busy_wire | busy_delay_reg),
+		busy_wire = ((((((((((((((do_read_rdid | do_read_sid) | do_read) | do_fast_read) | do_write) | do_sec_prot) | do_read_stat) | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_read_volatile) | do_fread_epcq) | do_read_nonvolatile) | do_ex4baddr),
+		clkin_wire = clkin,
+		clr_addmsb_wire = (((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & end_add_cycle) & end_one_cyc_pos) | (((~ do_read) & (~ do_fast_read)) & clr_write_wire2)) | ((((do_sec_erase | do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & end_operation)),
+		clr_endrbyte_wire = wire_mux2111_dataout,
+		clr_freadepcq_wire = end_operation,
+		clr_rdid_wire = clr_rdid_reg,
+		clr_read_wire = clr_read_reg,
+		clr_read_wire2 = clr_read_reg2,
+		clr_rstat_wire = clr_rstat_reg,
+		clr_secprot_wire = clr_secprot_reg,
+		clr_secprot_wire1 = clr_secprot_reg1,
+		clr_sid_wire = 1'b0,
+		clr_write_wire = clr_write_reg,
+		clr_write_wire2 = clr_write_reg2,
+		cnt_bfend_wire_in = wire_mux2116_dataout,
+		data0out_wire = 1'b0,
+		data_valid = data_valid_wire,
+		data_valid_wire = wire_mux2110_dataout,
+		datain_wire = {((memadd_datain[3] & write_datain[3]) & (~ ((((do_fast_read & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & (~ (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0])))))), ((memadd_datain[2] & write_datain[2]) & (~ ((((do_fast_read & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & (~ (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0])))))), (memadd_datain[1] | write_datain[1]), ((((((shift_opdata & asmi_opcode_reg[7]) | rsid_sdoin) | memadd_datain[0]) | write_datain[0]) | secprot_sdoin) | freadwrv_sdoin)},
+		dataoe_wire = {inout_wire[2], inout_wire[2:0]},
+		dataout = {read_data_reg[7:0]},
+		dataout_wire = {asmi_dataout[3:0]},
+		derase_opcode = {8{1'b0}},
+		die_erase_wire = 1'b0,
+		do_4baddr = ((((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & (~ sec_erase_wire)) & (~ (bulk_erase_wire | die_erase_wire))) & reset_addren_wire),
+		do_addr_overdie = addr_overdie_reg,
+		do_bulk_erase = 1'b0,
+		do_die_erase = 1'b0,
+		do_ex4baddr = 1'b0,
+		do_fast_read = (((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & fast_read_wire),
+		do_fread_epcq = 1'b0,
+		do_freadwrv_polling = 1'b0,
+		do_memadd = do_wrmemadd_reg,
+		do_polling = ((do_write_polling | do_sprot_polling) | do_freadwrv_polling),
+		do_read = 1'b0,
+		do_read_nonvolatile = read_nonvolatile,
+		do_read_rdid = ((~ do_read_nonvolatile) & read_rdid_wire),
+		do_read_sid = 1'b0,
+		do_read_stat = ((((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & read_status_wire) | do_write_rstat) | do_sprot_rstat) | do_write_volatile_rstat),
+		do_read_volatile = ((((((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & (~ sec_erase_wire)) & (~ (bulk_erase_wire | die_erase_wire))) & (~ reset_addren_wire)) & (~ ex4b_addr_wire)) & read_dummyclk_wire),
+		do_sec_erase = ((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & sec_erase_wire),
+		do_sec_prot = ((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & sec_protect_wire),
+		do_secprot_wren = ((do_sec_prot & (~ wire_spstage_cntr_q[1])) & (~ wire_spstage_cntr_q[0])),
+		do_sprot_polling = ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]),
+		do_sprot_rstat = sprot_rstat_reg,
+		do_wait_dummyclk = (do_fast_read & wire_cmpr8_aeb),
+		do_wren = ((do_write_wren | do_secprot_wren) | do_write_volatile_wren),
+		do_write = ((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & write_wire),
+		do_write_polling = (((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])),
+		do_write_rstat = write_rstat_reg,
+		do_write_volatile = 1'b0,
+		do_write_volatile_rstat = 1'b0,
+		do_write_volatile_wren = 1'b0,
+		do_write_wren = ((~ wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]),
+		dummy_read_buf = maxcnt_shift_reg2,
+		end1_cyc_dlyncs_in_wire = (((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & (~ wire_gen_cntr_q[0])) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))),
+		end1_cyc_gen_cntr_wire = wire_mux211_dataout,
+		end1_cyc_normal_in_wire = ((((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))) | (do_read_rdid & end_op_wire)),
+		end1_cyc_reg_in_wire = wire_mux212_dataout,
+		end_add_cycle = wire_mux213_dataout,
+		end_add_cycle_mux_datab_wire = do_wait_dummyclk,
+		end_fast_read = end_read_reg,
+		end_one_cyc_pos = end1_cyc_reg2,
+		end_one_cycle = end1_cyc_reg,
+		end_op_wire = ((((((((((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & ((((((~ do_read) & (~ do_fast_read)) & (~ (do_write & shift_pgwr_data))) & end_one_cycle) | (do_read & end_read)) | (do_fast_read & end_fast_read))) | ((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_stat) & end_one_cycle) & (~ do_polling))) | ((((((do_read_rdid & end_one_cyc_pos) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0]))) | (((start_poll & do_read_stat) & do_polling) & (~ st_busy_wire))) | ((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & (do_wren | (do_4baddr | (do_ex4baddr | (do_bulk_erase & (~ do_read_stat)))))) & end_one_cycle)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | ((do_write & shift_pgwr_data) & end_pgwr_data)) | (do_write & (~ pagewr_buf_not_empty[8]))) | (((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & end_one_cycle)) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & end_add_cycle) & end_one_cycle)) | (((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cycle) & ((do_write_volatile | do_read_volatile) | (do_read_nonvolatile & wire_addbyte_cntr_q[1])))),
+		end_operation = end_op_reg,
+		end_ophdly = end_op_hdlyreg,
+		end_pgwr_data = end_pgwrop_reg,
+		end_read = end_read_reg,
+		end_read_byte = (end_rbyte_reg & (~ addr_overdie)),
+		end_read_flag_status = wire_read_flag_status_cntr_q[1],
+		end_wrstage = end_operation,
+		ex4b_addr_wire = 1'b0,
+		exb4addr_opcode = {8{1'b0}},
+		fast_read_opcode = 8'b11101011,
+		fast_read_wire = fast_read_reg,
+		freadwrv_sdoin = 1'b0,
+		ill_erase_wire = ill_erase_reg,
+		ill_write_wire = ill_write_reg,
+		illegal_erase = ill_erase_wire,
+		illegal_erase_b4out_wire = (((do_sec_erase | do_bulk_erase) | do_die_erase) & write_prot_true),
+		illegal_write = ill_write_wire,
+		illegal_write_b4out_wire = ((do_write & write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))),
+		in_operation = busy_wire,
+		inout_wire = {(~ (stage4_wire & do_fast_read)), (~ ((do_read_stat | (stage4_wire & (do_read | do_fast_read))) | (stage3_wire & (((do_read_stat | do_read_rdid) | do_read_nonvolatile) | do_read_volatile)))), (do_read_stat | (~ ((stage4_wire & (do_read | do_fast_read)) | (stage3_wire & ((do_read_rdid | do_read_nonvolatile) | do_read_volatile)))))},
+		load_opcode = (((((~ wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
+		mask_prot = {(((((((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]) | prot_wire[6]) | prot_wire[7]) | prot_wire[8]) | prot_wire[9]) | prot_wire[10]), ((((((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]) | prot_wire[6]) | prot_wire[7]) | prot_wire[8]) | prot_wire[9]), (((((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]) | prot_wire[6]) | prot_wire[7]) | prot_wire[8]), ((((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]) | prot_wire[6]) | prot_wire[7]), (((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]) | prot_wire[6]), ((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]), (((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]), ((prot_wire[1] | prot_wire[2]) | prot_wire[3]), (prot_wire[1] | prot_wire[2]), prot_wire[1]},
+		mask_prot_add = {(mask_prot[9] & addr_reg[25]), (mask_prot[8] & addr_reg[24]), (mask_prot[7] & addr_reg[23]), (mask_prot[6] & addr_reg[22]), (mask_prot[5] & addr_reg[21]), (mask_prot[4] & addr_reg[20]), (mask_prot[3] & addr_reg[19]), (mask_prot[2] & addr_reg[18]), (mask_prot[1] & addr_reg[17]), (mask_prot[0] & addr_reg[16])},
+		mask_prot_check = {(mask_prot[9] ^ mask_prot_add[9]), (mask_prot[8] ^ mask_prot_add[8]), (mask_prot[7] ^ mask_prot_add[7]), (mask_prot[6] ^ mask_prot_add[6]), (mask_prot[5] ^ mask_prot_add[5]), (mask_prot[4] ^ mask_prot_add[4]), (mask_prot[3] ^ mask_prot_add[3]), (mask_prot[2] ^ mask_prot_add[2]), (mask_prot[1] ^ mask_prot_add[1]), (mask_prot[0] ^ mask_prot_add[0])},
+		mask_prot_comp_ntb = {(mask_prot_check[9] | mask_prot_comp_ntb[8]), (mask_prot_check[8] | mask_prot_comp_ntb[7]), (mask_prot_check[7] | mask_prot_comp_ntb[6]), (mask_prot_check[6] | mask_prot_comp_ntb[5]), (mask_prot_check[5] | mask_prot_comp_ntb[4]), (mask_prot_check[4] | mask_prot_comp_ntb[3]), (mask_prot_check[3] | mask_prot_comp_ntb[2]), (mask_prot_check[2] | mask_prot_comp_ntb[1]), (mask_prot_check[1] | mask_prot_comp_ntb[0]), mask_prot_check[0]},
+		mask_prot_comp_tb = {(mask_prot_add[9] | mask_prot_comp_tb[8]), (mask_prot_add[8] | mask_prot_comp_tb[7]), (mask_prot_add[7] | mask_prot_comp_tb[6]), (mask_prot_add[6] | mask_prot_comp_tb[5]), (mask_prot_add[5] | mask_prot_comp_tb[4]), (mask_prot_add[4] | mask_prot_comp_tb[3]), (mask_prot_add[3] | mask_prot_comp_tb[2]), (mask_prot_add[2] | mask_prot_comp_tb[1]), (mask_prot_add[1] | mask_prot_comp_tb[0]), mask_prot_add[0]},
+		memadd_datain = {wire_mux214a_dataout[3:0]},
+		ncs_reg_ena_wire = (((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & end_one_cyc_pos) | addr_overdie_pos) | end_operation),
+		not_busy = busy_det_reg,
+		page_size_wire = 9'b100000000,
+		pagewr_buf_not_empty = {(pagewr_buf_not_empty[7] | wire_pgwr_data_cntr_q[8]), (pagewr_buf_not_empty[6] | wire_pgwr_data_cntr_q[7]), (pagewr_buf_not_empty[5] | wire_pgwr_data_cntr_q[6]), (pagewr_buf_not_empty[4] | wire_pgwr_data_cntr_q[5]), (pagewr_buf_not_empty[3] | wire_pgwr_data_cntr_q[4]), (pagewr_buf_not_empty[2] | wire_pgwr_data_cntr_q[3]), (pagewr_buf_not_empty[1] | wire_pgwr_data_cntr_q[2]), (pagewr_buf_not_empty[0] | wire_pgwr_data_cntr_q[1]), wire_pgwr_data_cntr_q[0]},
+		prot_wire = {(((bp3_wire & bp2_wire) & bp1_wire) & bp0_wire), (((bp3_wire & bp2_wire) & bp1_wire) & (~ bp0_wire)), (((bp3_wire & bp2_wire) & (~ bp1_wire)) & bp0_wire), (((bp3_wire & bp2_wire) & (~ bp1_wire)) & (~ bp0_wire)), (((bp3_wire & (~ bp2_wire)) & bp1_wire) & bp0_wire), (((bp3_wire & (~ bp2_wire)) & bp1_wire) & (~ bp0_wire)), (((bp3_wire & (~ bp2_wire)) & (~ bp1_wire)) & bp0_wire), (((bp3_wire & (~ bp2_wire)) & (~ bp1_wire)) & (~ bp0_wire)), ((((~ bp3_wire) & bp2_wire) & bp1_wire) & bp0_wire), ((((~ bp3_wire) & bp2_wire) & bp1_wire) & (~ bp0_wire)), ((((~ bp3_wire) & bp2_wire) & (~ bp1_wire)) & bp0_wire), ((((~ bp3_wire) & bp2_wire) & (~ bp1_wire)) & (~ bp0_wire)), ((((~ bp3_wire) & (~ bp2_wire)) & bp1_wire) & bp0_wire), ((((~ bp3_wire) & (~ bp2_wire)) & bp1_wire) & (~ bp0_wire)), ((((~ bp3_wire) & (~ bp2_wire)) & (~ bp1_wire)) & bp0_wire), ((((~ bp3_wire) & (~ bp2_wire)) & (~ bp1_wire)) & (~ bp0_wire))},
+		rden_wire = rden,
+		rdid_load = (end_operation & do_read_rdid),
+		rdid_opcode = 8'b10011111,
+		rdid_out = {rdid_out_reg[7:0]},
+		rdummyclk_opcode = 8'b10000101,
+		reach_max_cnt = max_cnt_reg,
+		read_buf = (((((end_one_cycle & do_write) & (~ do_read_stat)) & (~ do_wren)) & ((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) | (wire_addbyte_cntr_q[2] & (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0]))))) & (~ buf_empty)),
+		read_bufdly = read_bufdly_reg,
+		read_data_reg_in_wire = {wire_mux219a_dataout[7:0]},
+		read_dummyclk_wire = read_dummyclk_reg,
+		read_nonvolatile = read_nonvdummyclk_reg,
+		read_opcode = {8{1'b0}},
+		read_rdid_wire = read_rdid_reg,
+		read_sid_wire = 1'b0,
+		read_status_wire = read_status_reg,
+		read_wire = 1'b0,
+		reset_addren_wire = reset_addren_reg,
+		rflagstat_opcode = 8'b01110000,
+		rnvdummyclk_opcode = 8'b10110101,
+		rsid_opcode = {8{1'b0}},
+		rsid_sdoin = 1'b0,
+		rstat_opcode = 8'b00000101,
+		scein_wire = (~ ncs_reg),
+		sec_erase_wire = sec_erase_reg,
+		sec_protect_wire = sec_prot_reg,
+		secprot_opcode = 8'b00000001,
+		secprot_sdoin = (stage3_wire & streg_datain_reg),
+		serase_opcode = 8'b11011000,
+		shift_bytes_wire = shift_bytes,
+		shift_opcode = shift_op_reg,
+		shift_opdata = stage2_wire,
+		shift_pgwr_data = shftpgwr_data_reg,
+		st_busy_wire = ((statreg_int[0] & (((~ do_polling) | do_4baddr) | do_ex4baddr)) | ((~ statreg_int[7]) & do_polling)),
+		stage2_wire = stage2_reg,
+		stage3_wire = stage3_reg,
+		stage4_wire = stage4_reg,
+		start_frpoll = 1'b0,
+		start_poll = ((start_wrpoll | start_sppoll) | start_frpoll),
+		start_sppoll = start_sppoll_reg2,
+		start_wrpoll = start_wrpoll_reg2,
+		status_out = {statreg_out[7:0]},
+		tb_wire = (statreg_int[5] & (~ do_polling)),
+		volatile_default_wire = (((volatile_reg[7] & volatile_reg[6]) & volatile_reg[5]) & volatile_reg[4]),
+		volatile_empty_wire = ((((~ volatile_reg[7]) & (~ volatile_reg[6])) & (~ volatile_reg[5])) & (~ volatile_reg[4])),
+		wren_opcode = 8'b00000110,
+		wren_wire = wren,
+		write_datain = {(({2{(((do_write & stage4_wire) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0])}} & pgwrbuf_quad_dataout[7:6]) | {2{(~ (((do_write & stage4_wire) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]))}}), ({2{(((do_write & stage4_wire) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0])}} & pgwrbuf_quad_dataout[5:4])},
+		write_opcode = 8'b00111000,
+		write_prot_true = write_prot_reg,
+		write_wire = write_reg,
+		wrvolatile_opcode = {8{1'b0}};
+endmodule //q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v
new file mode 100644
index 0000000..8b4802f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v
@@ -0,0 +1,207 @@
+// q_sys_ext_flash_epcq_controller_instance_name.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ext_flash_epcq_controller_instance_name #(
+		parameter DEVICE_FAMILY     = "MAX 10",
+		parameter ADDR_WIDTH        = 24,
+		parameter ASMI_ADDR_WIDTH   = 32,
+		parameter ASI_WIDTH         = 4,
+		parameter CS_WIDTH          = 1,
+		parameter CHIP_SELS         = 1,
+		parameter ENABLE_4BYTE_ADDR = 1
+	) (
+		input  wire        clk,                  //          clock_sink.clk
+		input  wire        reset_n,              //               reset.reset_n
+		input  wire        avl_csr_read,         //             avl_csr.read
+		output wire        avl_csr_waitrequest,  //                    .waitrequest
+		input  wire        avl_csr_write,        //                    .write
+		input  wire [2:0]  avl_csr_addr,         //                    .address
+		input  wire [31:0] avl_csr_wrdata,       //                    .writedata
+		output wire [31:0] avl_csr_rddata,       //                    .readdata
+		output wire        avl_csr_rddata_valid, //                    .readdatavalid
+		input  wire        avl_mem_write,        //             avl_mem.write
+		input  wire [6:0]  avl_mem_burstcount,   //                    .burstcount
+		output wire        avl_mem_waitrequest,  //                    .waitrequest
+		input  wire        avl_mem_read,         //                    .read
+		input  wire [23:0] avl_mem_addr,         //                    .address
+		input  wire [31:0] avl_mem_wrdata,       //                    .writedata
+		output wire [31:0] avl_mem_rddata,       //                    .readdata
+		output wire        avl_mem_rddata_valid, //                    .readdatavalid
+		input  wire [3:0]  avl_mem_byteenable,   //                    .byteenable
+		input  wire [7:0]  asmi_status_out,      //     asmi_status_out.conduit_status_out
+		input  wire [7:0]  asmi_epcs_id,         //        asmi_epcs_id.conduit_epcs_id
+		input  wire        asmi_illegal_erase,   //  asmi_illegal_erase.conduit_illegal_erase
+		input  wire        asmi_illegal_write,   //  asmi_illegal_write.conduit_illegal_write
+		input  wire [3:0]  ddasi_dataoe,         //        ddasi_dataoe.conduit_ddasi_dataoe
+		input  wire        ddasi_dclk,           //          ddasi_dclk.conduit_ddasi_dclk
+		input  wire [0:0]  ddasi_scein,          //         ddasi_scein.conduit_ddasi_scein
+		input  wire [3:0]  ddasi_sdoin,          //         ddasi_sdoin.conduit_ddasi_sdoin
+		input  wire        asmi_busy,            //           asmi_busy.conduit_busy
+		input  wire        asmi_data_valid,      //     asmi_data_valid.conduit_data_valid
+		input  wire [7:0]  asmi_dataout,         //        asmi_dataout.conduit_dataout
+		input  wire [3:0]  epcq_dataout,         //        epcq_dataout.conduit_epcq_dataout
+		output wire [3:0]  ddasi_dataout,        //       ddasi_dataout.conduit_ddasi_dataout
+		output wire        asmi_read_rdid,       //      asmi_read_rdid.conduit_read_rdid
+		output wire        asmi_read_status,     //    asmi_read_status.conduit_read_status
+		output wire        asmi_read_sid,        //       asmi_read_sid.conduit_read_sid
+		output wire        asmi_bulk_erase,      //     asmi_bulk_erase.conduit_bulk_erase
+		output wire        asmi_sector_erase,    //   asmi_sector_erase.conduit_sector_erase
+		output wire        asmi_sector_protect,  // asmi_sector_protect.conduit_sector_protect
+		output wire        epcq_dclk,            //           epcq_dclk.conduit_epcq_dclk
+		output wire [0:0]  epcq_scein,           //          epcq_scein.conduit_epcq_scein
+		output wire [3:0]  epcq_sdoin,           //          epcq_sdoin.conduit_epcq_sdoin
+		output wire [3:0]  epcq_dataoe,          //         epcq_dataoe.conduit_epcq_dataoe
+		output wire        asmi_clkin,           //          asmi_clkin.conduit_clkin
+		output wire        asmi_reset,           //          asmi_reset.conduit_reset
+		output wire [0:0]  asmi_sce,             //            asmi_sce.conduit_asmi_sce
+		output wire [31:0] asmi_addr,            //           asmi_addr.conduit_addr
+		output wire [7:0]  asmi_datain,          //         asmi_datain.conduit_datain
+		output wire        asmi_fast_read,       //      asmi_fast_read.conduit_fast_read
+		output wire        asmi_rden,            //           asmi_rden.conduit_rden
+		output wire        asmi_shift_bytes,     //    asmi_shift_bytes.conduit_shift_bytes
+		output wire        asmi_wren,            //           asmi_wren.conduit_wren
+		output wire        asmi_write,           //          asmi_write.conduit_write
+		input  wire [7:0]  asmi_rdid_out,        //       asmi_rdid_out.conduit_rdid_out
+		output wire        asmi_en4b_addr,       //      asmi_en4b_addr.conduit_en4b_addr
+		output wire        irq                   //    interrupt_sender.irq
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (DEVICE_FAMILY != "MAX 10")
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					device_family_check ( .error(1'b1) );
+		end
+		if (ADDR_WIDTH != 24)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					addr_width_check ( .error(1'b1) );
+		end
+		if (ASMI_ADDR_WIDTH != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					asmi_addr_width_check ( .error(1'b1) );
+		end
+		if (ASI_WIDTH != 4)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					asi_width_check ( .error(1'b1) );
+		end
+		if (CS_WIDTH != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					cs_width_check ( .error(1'b1) );
+		end
+		if (CHIP_SELS != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					chip_sels_check ( .error(1'b1) );
+		end
+		if (ENABLE_4BYTE_ADDR != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					enable_4byte_addr_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	altera_epcq_controller_arb #(
+		.DEVICE_FAMILY     ("MAX 10"),
+		.ADDR_WIDTH        (24),
+		.ASMI_ADDR_WIDTH   (32),
+		.ASI_WIDTH         (4),
+		.CS_WIDTH          (1),
+		.CHIP_SELS         (1),
+		.ENABLE_4BYTE_ADDR (1)
+	) epcq_controller_instance_name (
+		.clk                  (clk),                  //          clock_sink.clk
+		.reset_n              (reset_n),              //               reset.reset_n
+		.avl_csr_read         (avl_csr_read),         //             avl_csr.read
+		.avl_csr_waitrequest  (avl_csr_waitrequest),  //                    .waitrequest
+		.avl_csr_write        (avl_csr_write),        //                    .write
+		.avl_csr_addr         (avl_csr_addr),         //                    .address
+		.avl_csr_wrdata       (avl_csr_wrdata),       //                    .writedata
+		.avl_csr_rddata       (avl_csr_rddata),       //                    .readdata
+		.avl_csr_rddata_valid (avl_csr_rddata_valid), //                    .readdatavalid
+		.avl_mem_write        (avl_mem_write),        //             avl_mem.write
+		.avl_mem_burstcount   (avl_mem_burstcount),   //                    .burstcount
+		.avl_mem_waitrequest  (avl_mem_waitrequest),  //                    .waitrequest
+		.avl_mem_read         (avl_mem_read),         //                    .read
+		.avl_mem_addr         (avl_mem_addr),         //                    .address
+		.avl_mem_wrdata       (avl_mem_wrdata),       //                    .writedata
+		.avl_mem_rddata       (avl_mem_rddata),       //                    .readdata
+		.avl_mem_rddata_valid (avl_mem_rddata_valid), //                    .readdatavalid
+		.avl_mem_byteenable   (avl_mem_byteenable),   //                    .byteenable
+		.asmi_status_out      (asmi_status_out),      //     asmi_status_out.conduit_status_out
+		.asmi_epcs_id         (asmi_epcs_id),         //        asmi_epcs_id.conduit_epcs_id
+		.asmi_illegal_erase   (asmi_illegal_erase),   //  asmi_illegal_erase.conduit_illegal_erase
+		.asmi_illegal_write   (asmi_illegal_write),   //  asmi_illegal_write.conduit_illegal_write
+		.ddasi_dataoe         (ddasi_dataoe),         //        ddasi_dataoe.conduit_ddasi_dataoe
+		.ddasi_dclk           (ddasi_dclk),           //          ddasi_dclk.conduit_ddasi_dclk
+		.ddasi_scein          (ddasi_scein),          //         ddasi_scein.conduit_ddasi_scein
+		.ddasi_sdoin          (ddasi_sdoin),          //         ddasi_sdoin.conduit_ddasi_sdoin
+		.asmi_busy            (asmi_busy),            //           asmi_busy.conduit_busy
+		.asmi_data_valid      (asmi_data_valid),      //     asmi_data_valid.conduit_data_valid
+		.asmi_dataout         (asmi_dataout),         //        asmi_dataout.conduit_dataout
+		.epcq_dataout         (epcq_dataout),         //        epcq_dataout.conduit_epcq_dataout
+		.ddasi_dataout        (ddasi_dataout),        //       ddasi_dataout.conduit_ddasi_dataout
+		.asmi_read_rdid       (asmi_read_rdid),       //      asmi_read_rdid.conduit_read_rdid
+		.asmi_read_status     (asmi_read_status),     //    asmi_read_status.conduit_read_status
+		.asmi_read_sid        (asmi_read_sid),        //       asmi_read_sid.conduit_read_sid
+		.asmi_bulk_erase      (asmi_bulk_erase),      //     asmi_bulk_erase.conduit_bulk_erase
+		.asmi_sector_erase    (asmi_sector_erase),    //   asmi_sector_erase.conduit_sector_erase
+		.asmi_sector_protect  (asmi_sector_protect),  // asmi_sector_protect.conduit_sector_protect
+		.epcq_dclk            (epcq_dclk),            //           epcq_dclk.conduit_epcq_dclk
+		.epcq_scein           (epcq_scein),           //          epcq_scein.conduit_epcq_scein
+		.epcq_sdoin           (epcq_sdoin),           //          epcq_sdoin.conduit_epcq_sdoin
+		.epcq_dataoe          (epcq_dataoe),          //         epcq_dataoe.conduit_epcq_dataoe
+		.asmi_clkin           (asmi_clkin),           //          asmi_clkin.conduit_clkin
+		.asmi_reset           (asmi_reset),           //          asmi_reset.conduit_reset
+		.asmi_sce             (asmi_sce),             //            asmi_sce.conduit_asmi_sce
+		.asmi_addr            (asmi_addr),            //           asmi_addr.conduit_addr
+		.asmi_datain          (asmi_datain),          //         asmi_datain.conduit_datain
+		.asmi_fast_read       (asmi_fast_read),       //      asmi_fast_read.conduit_fast_read
+		.asmi_rden            (asmi_rden),            //           asmi_rden.conduit_rden
+		.asmi_shift_bytes     (asmi_shift_bytes),     //    asmi_shift_bytes.conduit_shift_bytes
+		.asmi_wren            (asmi_wren),            //           asmi_wren.conduit_wren
+		.asmi_write           (asmi_write),           //          asmi_write.conduit_write
+		.asmi_rdid_out        (asmi_rdid_out),        //       asmi_rdid_out.conduit_rdid_out
+		.asmi_en4b_addr       (asmi_en4b_addr),       //      asmi_en4b_addr.conduit_en4b_addr
+		.irq                  (irq)                   //    interrupt_sender.irq
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v
new file mode 100644
index 0000000..1138596
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v
@@ -0,0 +1,58 @@
+// q_sys_ext_flash_soft_asmiblock_instance_name.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_ext_flash_soft_asmiblock_instance_name #(
+		parameter IO_MODE  = "QUAD",
+		parameter CS_WIDTH = 1
+	) (
+		input  wire       dclk,     //     dclk.conduit_dclk
+		input  wire [0:0] sce,      //      sce.conduit_scein
+		input  wire [3:0] dataout,  //  dataout.conduit_sdoin
+		input  wire [3:0] dataoe,   //   dataoe.conduit_dataoe
+		output wire [3:0] datain,   //   datain.conduit_dataout
+		output wire       dclk_out, // dclk_out.conduit_dclk_out
+		output wire [0:0] ncs       //      ncs.conduit_ncs
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (IO_MODE != "QUAD")
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					io_mode_check ( .error(1'b1) );
+		end
+		if (CS_WIDTH != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					cs_width_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	soft_asmiblock #(
+		.IO_MODE  ("QUAD"),
+		.CS_WIDTH (1)
+	) soft_asmiblock_instance_name (
+		.dclk     (dclk),     //     dclk.conduit_dclk
+		.sce      (sce),      //      sce.conduit_scein
+		.dataout  (dataout),  //  dataout.conduit_sdoin
+		.dataoe   (dataoe),   //   dataoe.conduit_dataoe
+		.datain   (datain),   //   datain.conduit_dataout
+		.dclk_out (dclk_out), // dclk_out.conduit_dclk_out
+		.ncs      (ncs)       //      ncs.conduit_ncs
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_frame_timer.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_frame_timer.v
new file mode 100644
index 0000000..29cc9c0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_frame_timer.v
@@ -0,0 +1,203 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_frame_timer (
+                           // inputs:
+                            address,
+                            chipselect,
+                            clk,
+                            reset_n,
+                            write_n,
+                            writedata,
+
+                           // outputs:
+                            irq,
+                            readdata,
+                            timeout_pulse
+                         )
+;
+
+  output           irq;
+  output  [ 15: 0] readdata;
+  output           timeout_pulse;
+  input   [  2: 0] address;
+  input            chipselect;
+  input            clk;
+  input            reset_n;
+  input            write_n;
+  input   [ 15: 0] writedata;
+
+
+wire             clk_en;
+wire             control_continuous;
+wire             control_interrupt_enable;
+reg     [  3: 0] control_register;
+wire             control_wr_strobe;
+reg              counter_is_running;
+wire             counter_is_zero;
+wire    [ 31: 0] counter_load_value;
+reg              delayed_unxcounter_is_zeroxx0;
+wire             do_start_counter;
+wire             do_stop_counter;
+reg              force_reload;
+reg     [ 31: 0] internal_counter;
+wire             irq;
+reg     [ 15: 0] period_h_register;
+wire             period_h_wr_strobe;
+reg     [ 15: 0] period_l_register;
+wire             period_l_wr_strobe;
+wire    [ 15: 0] read_mux_out;
+reg     [ 15: 0] readdata;
+wire             start_strobe;
+wire             status_wr_strobe;
+wire             stop_strobe;
+wire             timeout_event;
+reg              timeout_occurred;
+reg              timeout_pulse;
+  assign clk_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          internal_counter <= 32'h1387;
+      else if (counter_is_running || force_reload)
+          if (counter_is_zero    || force_reload)
+              internal_counter <= counter_load_value;
+          else 
+            internal_counter <= internal_counter - 1;
+    end
+
+
+  assign counter_is_zero = internal_counter == 0;
+  assign counter_load_value = {period_h_register,
+    period_l_register};
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          force_reload <= 0;
+      else if (clk_en)
+          force_reload <= period_h_wr_strobe || period_l_wr_strobe;
+    end
+
+
+  assign do_start_counter = start_strobe;
+  assign do_stop_counter = (stop_strobe                            ) ||
+    (force_reload                           ) ||
+    (counter_is_zero && ~control_continuous );
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          counter_is_running <= 1'b0;
+      else if (clk_en)
+          if (do_start_counter)
+              counter_is_running <= -1;
+          else if (do_stop_counter)
+              counter_is_running <= 0;
+    end
+
+
+  //delayed_unxcounter_is_zeroxx0, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxcounter_is_zeroxx0 <= 0;
+      else if (clk_en)
+          delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
+    end
+
+
+  assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          timeout_occurred <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              timeout_occurred <= 0;
+          else if (timeout_event)
+              timeout_occurred <= -1;
+    end
+
+
+  assign irq = timeout_occurred && control_interrupt_enable;
+  //s1, which is an e_avalon_slave
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          timeout_pulse <= 0;
+      else if (clk_en)
+          timeout_pulse <= timeout_event;
+    end
+
+
+  assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
+    ({16 {(address == 3)}} & period_h_register) |
+    ({16 {(address == 1)}} & control_register) |
+    ({16 {(address == 0)}} & {counter_is_running,
+    timeout_occurred});
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          readdata <= 0;
+      else if (clk_en)
+          readdata <= read_mux_out;
+    end
+
+
+  assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
+  assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          period_l_register <= 4999;
+      else if (period_l_wr_strobe)
+          period_l_register <= writedata;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          period_h_register <= 0;
+      else if (period_h_wr_strobe)
+          period_h_register <= writedata;
+    end
+
+
+  assign control_wr_strobe = chipselect && ~write_n && (address == 1);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          control_register <= 0;
+      else if (control_wr_strobe)
+          control_register <= writedata[3 : 0];
+    end
+
+
+  assign stop_strobe = writedata[3] && control_wr_strobe;
+  assign start_strobe = writedata[2] && control_wr_strobe;
+  assign control_continuous = control_register[1];
+  assign control_interrupt_enable = control_register[0];
+  assign status_wr_strobe = chipselect && ~write_n && (address == 0);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_glad.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_glad.v
new file mode 100644
index 0000000..803ff52
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_glad.v
@@ -0,0 +1,87 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_glad (
+                    // inputs:
+                     address,
+                     byteenable,
+                     chipselect,
+                     clk,
+                     clken,
+                     freeze,
+                     reset,
+                     reset_req,
+                     write,
+                     writedata,
+
+                    // outputs:
+                     readdata
+                  )
+;
+
+  output  [ 15: 0] readdata;
+  input   [  8: 0] address;
+  input   [  1: 0] byteenable;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [ 15: 0] writedata;
+
+
+wire             clocken0;
+wire    [ 15: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=glad",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 320,
+           the_altsyncram.numwords_a = 320,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.widthad_a = 9;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_irq_mapper.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_irq_mapper.sv
new file mode 100644
index 0000000..d29733e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_irq_mapper.sv
@@ -0,0 +1,66 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Altera IRQ Mapper
+//
+// Parameters
+//   NUM_RCVRS        : 5
+//   SENDER_IRW_WIDTH : 32
+//   IRQ_MAP          : 0:2,1:3,2:5,3:0,4:4
+//
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_irq_mapper
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // IRQ Receivers
+    // -------------------
+    input                receiver0_irq,
+    input                receiver1_irq,
+    input                receiver2_irq,
+    input                receiver3_irq,
+    input                receiver4_irq,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg [31 : 0] sender_irq
+);
+
+
+    always @* begin
+	sender_irq = 0;
+
+        sender_irq[2] = receiver0_irq;
+        sender_irq[3] = receiver1_irq;
+        sender_irq[5] = receiver2_irq;
+        sender_irq[0] = receiver3_irq;
+        sender_irq[4] = receiver4_irq;
+    end
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_jtag_uart.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_jtag_uart.v
new file mode 100644
index 0000000..c05a590
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_jtag_uart.v
@@ -0,0 +1,588 @@
+//Legal Notice: (C)2019 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_jtag_uart_sim_scfifo_w (
+                                      // inputs:
+                                       clk,
+                                       fifo_wdata,
+                                       fifo_wr,
+
+                                      // outputs:
+                                       fifo_FF,
+                                       r_dat,
+                                       wfifo_empty,
+                                       wfifo_used
+                                    )
+;
+
+  output           fifo_FF;
+  output  [  7: 0] r_dat;
+  output           wfifo_empty;
+  output  [  5: 0] wfifo_used;
+  input            clk;
+  input   [  7: 0] fifo_wdata;
+  input            fifo_wr;
+
+
+wire             fifo_FF;
+wire    [  7: 0] r_dat;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  always @(posedge clk)
+    begin
+      if (fifo_wr)
+          $write("%c", fifo_wdata);
+    end
+
+
+  assign wfifo_used = {6{1'b0}};
+  assign r_dat = {8{1'b0}};
+  assign fifo_FF = 1'b0;
+  assign wfifo_empty = 1'b1;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_jtag_uart_scfifo_w (
+                                  // inputs:
+                                   clk,
+                                   fifo_clear,
+                                   fifo_wdata,
+                                   fifo_wr,
+                                   rd_wfifo,
+
+                                  // outputs:
+                                   fifo_FF,
+                                   r_dat,
+                                   wfifo_empty,
+                                   wfifo_used
+                                )
+;
+
+  output           fifo_FF;
+  output  [  7: 0] r_dat;
+  output           wfifo_empty;
+  output  [  5: 0] wfifo_used;
+  input            clk;
+  input            fifo_clear;
+  input   [  7: 0] fifo_wdata;
+  input            fifo_wr;
+  input            rd_wfifo;
+
+
+wire             fifo_FF;
+wire    [  7: 0] r_dat;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  q_sys_jtag_uart_sim_scfifo_w the_q_sys_jtag_uart_sim_scfifo_w
+    (
+      .clk         (clk),
+      .fifo_FF     (fifo_FF),
+      .fifo_wdata  (fifo_wdata),
+      .fifo_wr     (fifo_wr),
+      .r_dat       (r_dat),
+      .wfifo_empty (wfifo_empty),
+      .wfifo_used  (wfifo_used)
+    );
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  scfifo wfifo
+//    (
+//      .aclr (fifo_clear),
+//      .clock (clk),
+//      .data (fifo_wdata),
+//      .empty (wfifo_empty),
+//      .full (fifo_FF),
+//      .q (r_dat),
+//      .rdreq (rd_wfifo),
+//      .usedw (wfifo_used),
+//      .wrreq (fifo_wr)
+//    );
+//
+//  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
+//           wfifo.lpm_numwords = 64,
+//           wfifo.lpm_showahead = "OFF",
+//           wfifo.lpm_type = "scfifo",
+//           wfifo.lpm_width = 8,
+//           wfifo.lpm_widthu = 6,
+//           wfifo.overflow_checking = "OFF",
+//           wfifo.underflow_checking = "OFF",
+//           wfifo.use_eab = "ON";
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_jtag_uart_sim_scfifo_r (
+                                      // inputs:
+                                       clk,
+                                       fifo_rd,
+                                       rst_n,
+
+                                      // outputs:
+                                       fifo_EF,
+                                       fifo_rdata,
+                                       rfifo_full,
+                                       rfifo_used
+                                    )
+;
+
+  output           fifo_EF;
+  output  [  7: 0] fifo_rdata;
+  output           rfifo_full;
+  output  [  5: 0] rfifo_used;
+  input            clk;
+  input            fifo_rd;
+  input            rst_n;
+
+
+reg     [ 31: 0] bytes_left;
+wire             fifo_EF;
+reg              fifo_rd_d;
+wire    [  7: 0] fifo_rdata;
+wire             new_rom;
+wire    [ 31: 0] num_bytes;
+wire    [  6: 0] rfifo_entries;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  // Generate rfifo_entries for simulation
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          bytes_left <= 32'h0;
+          fifo_rd_d <= 1'b0;
+        end
+      else 
+        begin
+          fifo_rd_d <= fifo_rd;
+          // decrement on read
+          if (fifo_rd_d)
+              bytes_left <= bytes_left - 1'b1;
+          // catch new contents
+          if (new_rom)
+              bytes_left <= num_bytes;
+        end
+    end
+
+
+  assign fifo_EF = bytes_left == 32'b0;
+  assign rfifo_full = bytes_left > 7'h40;
+  assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
+  assign rfifo_used = rfifo_entries[5 : 0];
+  assign new_rom = 1'b0;
+  assign num_bytes = 32'b0;
+  assign fifo_rdata = 8'b0;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_jtag_uart_scfifo_r (
+                                  // inputs:
+                                   clk,
+                                   fifo_clear,
+                                   fifo_rd,
+                                   rst_n,
+                                   t_dat,
+                                   wr_rfifo,
+
+                                  // outputs:
+                                   fifo_EF,
+                                   fifo_rdata,
+                                   rfifo_full,
+                                   rfifo_used
+                                )
+;
+
+  output           fifo_EF;
+  output  [  7: 0] fifo_rdata;
+  output           rfifo_full;
+  output  [  5: 0] rfifo_used;
+  input            clk;
+  input            fifo_clear;
+  input            fifo_rd;
+  input            rst_n;
+  input   [  7: 0] t_dat;
+  input            wr_rfifo;
+
+
+wire             fifo_EF;
+wire    [  7: 0] fifo_rdata;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  q_sys_jtag_uart_sim_scfifo_r the_q_sys_jtag_uart_sim_scfifo_r
+    (
+      .clk        (clk),
+      .fifo_EF    (fifo_EF),
+      .fifo_rd    (fifo_rd),
+      .fifo_rdata (fifo_rdata),
+      .rfifo_full (rfifo_full),
+      .rfifo_used (rfifo_used),
+      .rst_n      (rst_n)
+    );
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  scfifo rfifo
+//    (
+//      .aclr (fifo_clear),
+//      .clock (clk),
+//      .data (t_dat),
+//      .empty (fifo_EF),
+//      .full (rfifo_full),
+//      .q (fifo_rdata),
+//      .rdreq (fifo_rd),
+//      .usedw (rfifo_used),
+//      .wrreq (wr_rfifo)
+//    );
+//
+//  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
+//           rfifo.lpm_numwords = 64,
+//           rfifo.lpm_showahead = "OFF",
+//           rfifo.lpm_type = "scfifo",
+//           rfifo.lpm_width = 8,
+//           rfifo.lpm_widthu = 6,
+//           rfifo.overflow_checking = "OFF",
+//           rfifo.underflow_checking = "OFF",
+//           rfifo.use_eab = "ON";
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_jtag_uart (
+                         // inputs:
+                          av_address,
+                          av_chipselect,
+                          av_read_n,
+                          av_write_n,
+                          av_writedata,
+                          clk,
+                          rst_n,
+
+                         // outputs:
+                          av_irq,
+                          av_readdata,
+                          av_waitrequest,
+                          dataavailable,
+                          readyfordata
+                       )
+  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
+
+  output           av_irq;
+  output  [ 31: 0] av_readdata;
+  output           av_waitrequest;
+  output           dataavailable;
+  output           readyfordata;
+  input            av_address;
+  input            av_chipselect;
+  input            av_read_n;
+  input            av_write_n;
+  input   [ 31: 0] av_writedata;
+  input            clk;
+  input            rst_n;
+
+
+reg              ac;
+wire             activity;
+wire             av_irq;
+wire    [ 31: 0] av_readdata;
+reg              av_waitrequest;
+reg              dataavailable;
+reg              fifo_AE;
+reg              fifo_AF;
+wire             fifo_EF;
+wire             fifo_FF;
+wire             fifo_clear;
+wire             fifo_rd;
+wire    [  7: 0] fifo_rdata;
+wire    [  7: 0] fifo_wdata;
+reg              fifo_wr;
+reg              ien_AE;
+reg              ien_AF;
+wire             ipen_AE;
+wire             ipen_AF;
+reg              pause_irq;
+wire    [  7: 0] r_dat;
+wire             r_ena;
+reg              r_val;
+wire             rd_wfifo;
+reg              read_0;
+reg              readyfordata;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+reg              rvalid;
+reg              sim_r_ena;
+reg              sim_t_dat;
+reg              sim_t_ena;
+reg              sim_t_pause;
+wire    [  7: 0] t_dat;
+reg              t_dav;
+wire             t_ena;
+wire             t_pause;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+reg              woverflow;
+wire             wr_rfifo;
+  //avalon_jtag_slave, which is an e_avalon_slave
+  assign rd_wfifo = r_ena & ~wfifo_empty;
+  assign wr_rfifo = t_ena & ~rfifo_full;
+  assign fifo_clear = ~rst_n;
+  q_sys_jtag_uart_scfifo_w the_q_sys_jtag_uart_scfifo_w
+    (
+      .clk         (clk),
+      .fifo_FF     (fifo_FF),
+      .fifo_clear  (fifo_clear),
+      .fifo_wdata  (fifo_wdata),
+      .fifo_wr     (fifo_wr),
+      .r_dat       (r_dat),
+      .rd_wfifo    (rd_wfifo),
+      .wfifo_empty (wfifo_empty),
+      .wfifo_used  (wfifo_used)
+    );
+
+  q_sys_jtag_uart_scfifo_r the_q_sys_jtag_uart_scfifo_r
+    (
+      .clk        (clk),
+      .fifo_EF    (fifo_EF),
+      .fifo_clear (fifo_clear),
+      .fifo_rd    (fifo_rd),
+      .fifo_rdata (fifo_rdata),
+      .rfifo_full (rfifo_full),
+      .rfifo_used (rfifo_used),
+      .rst_n      (rst_n),
+      .t_dat      (t_dat),
+      .wr_rfifo   (wr_rfifo)
+    );
+
+  assign ipen_AE = ien_AE & fifo_AE;
+  assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
+  assign av_irq = ipen_AE | ipen_AF;
+  assign activity = t_pause | t_ena;
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+          pause_irq <= 1'b0;
+      else // only if fifo is not empty...
+      if (t_pause & ~fifo_EF)
+          pause_irq <= 1'b1;
+      else if (read_0)
+          pause_irq <= 1'b0;
+    end
+
+
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          r_val <= 1'b0;
+          t_dav <= 1'b1;
+        end
+      else 
+        begin
+          r_val <= r_ena & ~wfifo_empty;
+          t_dav <= ~rfifo_full;
+        end
+    end
+
+
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          fifo_AE <= 1'b0;
+          fifo_AF <= 1'b0;
+          fifo_wr <= 1'b0;
+          rvalid <= 1'b0;
+          read_0 <= 1'b0;
+          ien_AE <= 1'b0;
+          ien_AF <= 1'b0;
+          ac <= 1'b0;
+          woverflow <= 1'b0;
+          av_waitrequest <= 1'b1;
+        end
+      else 
+        begin
+          fifo_AE <= {fifo_FF,wfifo_used} <= 8;
+          fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
+          fifo_wr <= 1'b0;
+          read_0 <= 1'b0;
+          av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
+          if (activity)
+              ac <= 1'b1;
+          // write
+          if (av_chipselect & ~av_write_n & av_waitrequest)
+              // addr 1 is control; addr 0 is data
+              if (av_address)
+                begin
+                  ien_AF <= av_writedata[0];
+                  ien_AE <= av_writedata[1];
+                  if (av_writedata[10] & ~activity)
+                      ac <= 1'b0;
+                end
+              else 
+                begin
+                  fifo_wr <= ~fifo_FF;
+                  woverflow <= fifo_FF;
+                end
+          // read
+          if (av_chipselect & ~av_read_n & av_waitrequest)
+            begin
+              // addr 1 is interrupt; addr 0 is data
+              if (~av_address)
+                  rvalid <= ~fifo_EF;
+              read_0 <= ~av_address;
+            end
+        end
+    end
+
+
+  assign fifo_wdata = av_writedata[7 : 0];
+  assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
+  assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+          readyfordata <= 0;
+      else 
+        readyfordata <= ~fifo_FF;
+    end
+
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  // Tie off Atlantic Interface signals not used for simulation
+  always @(posedge clk)
+    begin
+      sim_t_pause <= 1'b0;
+      sim_t_ena <= 1'b0;
+      sim_t_dat <= t_dav ? r_dat : {8{r_val}};
+      sim_r_ena <= 1'b0;
+    end
+
+
+  assign r_ena = sim_r_ena;
+  assign t_ena = sim_t_ena;
+  assign t_dat = sim_t_dat;
+  assign t_pause = sim_t_pause;
+  always @(fifo_EF)
+    begin
+      dataavailable = ~fifo_EF;
+    end
+
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  alt_jtag_atlantic q_sys_jtag_uart_alt_jtag_atlantic
+//    (
+//      .clk (clk),
+//      .r_dat (r_dat),
+//      .r_ena (r_ena),
+//      .r_val (r_val),
+//      .rst_n (rst_n),
+//      .t_dat (t_dat),
+//      .t_dav (t_dav),
+//      .t_ena (t_ena),
+//      .t_pause (t_pause)
+//    );
+//
+//  defparam q_sys_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
+//           q_sys_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
+//           q_sys_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
+//           q_sys_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
+//
+//  always @(posedge clk or negedge rst_n)
+//    begin
+//      if (rst_n == 0)
+//          dataavailable <= 0;
+//      else 
+//        dataavailable <= ~fifo_EF;
+//    end
+//
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_led_pio.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_led_pio.v
new file mode 100644
index 0000000..ea884b2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_led_pio.v
@@ -0,0 +1,70 @@
+//Legal Notice: (C)2019 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_led_pio (
+                       // inputs:
+                        address,
+                        chipselect,
+                        clk,
+                        reset_n,
+                        write_n,
+                        writedata,
+
+                       // outputs:
+                        out_port,
+                        readdata
+                     )
+;
+
+  output  [  7: 0] out_port;
+  output  [ 31: 0] readdata;
+  input   [  2: 0] address;
+  input            chipselect;
+  input            clk;
+  input            reset_n;
+  input            write_n;
+  input   [ 31: 0] writedata;
+
+
+wire             clk_en;
+reg     [  7: 0] data_out;
+wire    [  7: 0] out_port;
+wire    [  7: 0] read_mux_out;
+wire    [ 31: 0] readdata;
+wire             wr_strobe;
+  assign clk_en = 1;
+  //s1, which is an e_avalon_slave
+  assign read_mux_out = {8 {(address == 0)}} & data_out;
+  assign wr_strobe = chipselect && ~write_n;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          data_out <= 0;
+      else if (clk_en)
+          if (wr_strobe)
+              data_out <= (address == 5)? data_out & ~writedata[7 : 0]: (address == 4)? data_out | writedata[7 : 0]: (address == 0)? writedata[7 : 0]: data_out;
+    end
+
+
+  assign readdata = {32'b0 | read_mux_out};
+  assign out_port = data_out;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.hex b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.hex
new file mode 100644
index 0000000..a74ec33
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.hex
@@ -0,0 +1,32764 @@
+:020000000000FE
+:020001000000FD
+:020002000000FC
+:020003000000FB
+:020004000000FA
+:020005000000F9
+:020006000000F8
+:020007000000F7
+:020008000000F6
+:020009000000F5
+:02000A000000F4
+:02000B000000F3
+:02000C000000F2
+:02000D000000F1
+:02000E000000F0
+:02000F000000EF
+:020010000000EE
+:020011000000ED
+:020012000000EC
+:020013000000EB
+:020014000000EA
+:020015000000E9
+:020016000000E8
+:020017000000E7
+:020018000000E6
+:020019000000E5
+:02001A000000E4
+:02001B000000E3
+:02001C000000E2
+:02001D000000E1
+:02001E000000E0
+:02001F000000DF
+:020020000000DE
+:020021000000DD
+:020022000000DC
+:020023000000DB
+:020024000000DA
+:020025000000D9
+:020026000000D8
+:020027000000D7
+:020028000000D6
+:020029000000D5
+:02002A000000D4
+:02002B000000D3
+:02002C000000D2
+:02002D000000D1
+:02002E000000D0
+:02002F000000CF
+:020030000000CE
+:020031000000CD
+:020032000000CC
+:020033000000CB
+:020034000000CA
+:020035000000C9
+:020036000000C8
+:020037000000C7
+:020038000000C6
+:020039000000C5
+:02003A000000C4
+:02003B000000C3
+:02003C000000C2
+:02003D000000C1
+:02003E000000C0
+:02003F000000BF
+:020040000000BE
+:020041000000BD
+:020042000000BC
+:020043000000BB
+:020044000000BA
+:020045000000B9
+:020046000000B8
+:020047000000B7
+:020048000000B6
+:020049000000B5
+:02004A000000B4
+:02004B000000B3
+:02004C000000B2
+:02004D000000B1
+:02004E000000B0
+:02004F000000AF
+:020050000000AE
+:020051000000AD
+:020052000000AC
+:020053000000AB
+:020054000000AA
+:020055000000A9
+:020056000000A8
+:020057000000A7
+:020058000000A6
+:020059000000A5
+:02005A000000A4
+:02005B000000A3
+:02005C000000A2
+:02005D000000A1
+:02005E000000A0
+:02005F0000009F
+:0200600000009E
+:0200610000009D
+:0200620000009C
+:0200630000009B
+:0200640000009A
+:02006500000099
+:02006600000098
+:02006700000097
+:02006800000096
+:02006900000095
+:02006A00000094
+:02006B00000093
+:02006C00000092
+:02006D00000091
+:02006E00000090
+:02006F0000008F
+:0200700000008E
+:0200710000008D
+:0200720000008C
+:0200730000008B
+:0200740000008A
+:02007500000089
+:02007600000088
+:02007700000087
+:02007800000086
+:02007900000085
+:02007A00000084
+:02007B00000083
+:02007C00000082
+:02007D00000081
+:02007E00000080
+:02007F0000007F
+:0200800000007E
+:0200810000007D
+:0200820000007C
+:0200830000007B
+:0200840000007A
+:02008500000079
+:02008600000078
+:02008700000077
+:02008800000076
+:02008900000075
+:02008A00000074
+:02008B00000073
+:02008C00000072
+:02008D00000071
+:02008E00000070
+:02008F0000006F
+:0200900000006E
+:0200910000006D
+:0200920000006C
+:0200930000006B
+:0200940000006A
+:02009500000069
+:02009600000068
+:02009700000067
+:02009800000066
+:02009900000065
+:02009A00000064
+:02009B00000063
+:02009C00000062
+:02009D00000061
+:02009E00000060
+:02009F0000005F
+:0200A00000005E
+:0200A10000005D
+:0200A20000005C
+:0200A30000005B
+:0200A40000005A
+:0200A500000059
+:0200A600000058
+:0200A700000057
+:0200A800000056
+:0200A900000055
+:0200AA00000054
+:0200AB00000053
+:0200AC00000052
+:0200AD00000051
+:0200AE00000050
+:0200AF0000004F
+:0200B00000004E
+:0200B10000004D
+:0200B20000004C
+:0200B30000004B
+:0200B40000004A
+:0200B500000049
+:0200B600000048
+:0200B700000047
+:0200B800000046
+:0200B900000045
+:0200BA00000044
+:0200BB00000043
+:0200BC00000042
+:0200BD00000041
+:0200BE00000040
+:0200BF0000003F
+:0200C00000003E
+:0200C10000003D
+:0200C20000003C
+:0200C30000003B
+:0200C40000003A
+:0200C500000039
+:0200C600000038
+:0200C700000037
+:0200C800000036
+:0200C900000035
+:0200CA00000034
+:0200CB00000033
+:0200CC00000032
+:0200CD00000031
+:0200CE00000030
+:0200CF0000002F
+:0200D00000002E
+:0200D10000002D
+:0200D20000002C
+:0200D30000002B
+:0200D40000002A
+:0200D500000029
+:0200D600000028
+:0200D700000027
+:0200D800000026
+:0200D900000025
+:0200DA00000024
+:0200DB00000023
+:0200DC00000022
+:0200DD00000021
+:0200DE00000020
+:0200DF0000001F
+:0200E00000001E
+:0200E10000001D
+:0200E20000001C
+:0200E30000001B
+:0200E40000001A
+:0200E500000019
+:0200E600000018
+:0200E700000017
+:0200E800000016
+:0200E900000015
+:0200EA00000014
+:0200EB00000013
+:0200EC00000012
+:0200ED00000011
+:0200EE00000010
+:0200EF0000000F
+:0200F00000000E
+:0200F10000000D
+:0200F20000000C
+:0200F30000000B
+:0200F40000000A
+:0200F500000009
+:0200F600000008
+:0200F700000007
+:0200F800000006
+:0200F900000005
+:0200FA00000004
+:0200FB00000003
+:0200FC00000002
+:0200FD00000001
+:0200FE00000000
+:0200FF000000FF
+:020100000000FD
+:020101000000FC
+:020102000000FB
+:020103000000FA
+:020104000000F9
+:020105000000F8
+:020106000000F7
+:020107000000F6
+:020108000000F5
+:020109000000F4
+:02010A000000F3
+:02010B000000F2
+:02010C000000F1
+:02010D000000F0
+:02010E000000EF
+:02010F000000EE
+:020110000000ED
+:020111000000EC
+:020112000000EB
+:020113000000EA
+:020114000000E9
+:020115000000E8
+:020116000000E7
+:020117000000E6
+:020118000000E5
+:020119000000E4
+:02011A000000E3
+:02011B000000E2
+:02011C000000E1
+:02011D000000E0
+:02011E000000DF
+:02011F000000DE
+:020120000000DD
+:020121000000DC
+:020122000000DB
+:020123000000DA
+:020124000000D9
+:020125000000D8
+:020126000000D7
+:020127000000D6
+:020128000000D5
+:020129000000D4
+:02012A000000D3
+:02012B000000D2
+:02012C000000D1
+:02012D000000D0
+:02012E000000CF
+:02012F000000CE
+:020130000000CD
+:020131000000CC
+:020132000000CB
+:020133000000CA
+:020134000000C9
+:020135000000C8
+:020136000000C7
+:020137000000C6
+:020138000000C5
+:020139000000C4
+:02013A000000C3
+:02013B000000C2
+:02013C000000C1
+:02013D000000C0
+:02013E000000BF
+:02013F000000BE
+:020140000000BD
+:020141000000BC
+:020142000000BB
+:020143000000BA
+:020144000000B9
+:020145000000B8
+:020146000000B7
+:020147000000B6
+:020148000000B5
+:020149000000B4
+:02014A000000B3
+:02014B000000B2
+:02014C000000B1
+:02014D000000B0
+:02014E000000AF
+:02014F000000AE
+:020150000000AD
+:020151000000AC
+:020152000000AB
+:020153000000AA
+:020154000000A9
+:020155000000A8
+:020156000000A7
+:020157000000A6
+:020158000000A5
+:020159000000A4
+:02015A000000A3
+:02015B000000A2
+:02015C000000A1
+:02015D000000A0
+:02015E0000009F
+:02015F0000009E
+:0201600000009D
+:0201610000009C
+:0201620000009B
+:0201630000009A
+:02016400000099
+:02016500000098
+:02016600000097
+:02016700000096
+:02016800000095
+:02016900000094
+:02016A00000093
+:02016B00000092
+:02016C00000091
+:02016D00000090
+:02016E0000008F
+:02016F0000008E
+:0201700000008D
+:0201710000008C
+:0201720000008B
+:0201730000008A
+:02017400000089
+:02017500000088
+:02017600000087
+:02017700000086
+:02017800000085
+:02017900000084
+:02017A00000083
+:02017B00000082
+:02017C00000081
+:02017D00000080
+:02017E0000007F
+:02017F0000007E
+:0201800000007D
+:0201810000007C
+:0201820000007B
+:0201830000007A
+:02018400000079
+:02018500000078
+:02018600000077
+:02018700000076
+:02018800000075
+:02018900000074
+:02018A00000073
+:02018B00000072
+:02018C00000071
+:02018D00000070
+:02018E0000006F
+:02018F0000006E
+:0201900000006D
+:0201910000006C
+:0201920000006B
+:0201930000006A
+:02019400000069
+:02019500000068
+:02019600000067
+:02019700000066
+:02019800000065
+:02019900000064
+:02019A00000063
+:02019B00000062
+:02019C00000061
+:02019D00000060
+:02019E0000005F
+:02019F0000005E
+:0201A00000005D
+:0201A10000005C
+:0201A20000005B
+:0201A30000005A
+:0201A400000059
+:0201A500000058
+:0201A600000057
+:0201A700000056
+:0201A800000055
+:0201A900000054
+:0201AA00000053
+:0201AB00000052
+:0201AC00000051
+:0201AD00000050
+:0201AE0000004F
+:0201AF0000004E
+:0201B00000004D
+:0201B10000004C
+:0201B20000004B
+:0201B30000004A
+:0201B400000049
+:0201B500000048
+:0201B600000047
+:0201B700000046
+:0201B800000045
+:0201B900000044
+:0201BA00000043
+:0201BB00000042
+:0201BC00000041
+:0201BD00000040
+:0201BE0000003F
+:0201BF0000003E
+:0201C00000003D
+:0201C10000003C
+:0201C20000003B
+:0201C30000003A
+:0201C400000039
+:0201C500000038
+:0201C600000037
+:0201C700000036
+:0201C800000035
+:0201C900000034
+:0201CA00000033
+:0201CB00000032
+:0201CC00000031
+:0201CD00000030
+:0201CE0000002F
+:0201CF0000002E
+:0201D00000002D
+:0201D10000002C
+:0201D20000002B
+:0201D30000002A
+:0201D400000029
+:0201D500000028
+:0201D600000027
+:0201D700000026
+:0201D800000025
+:0201D900000024
+:0201DA00000023
+:0201DB00000022
+:0201DC00000021
+:0201DD00000020
+:0201DE0000001F
+:0201DF0000001E
+:0201E00000001D
+:0201E10000001C
+:0201E20000001B
+:0201E30000001A
+:0201E400000019
+:0201E500000018
+:0201E600000017
+:0201E700000016
+:0201E800000015
+:0201E900000014
+:0201EA00000013
+:0201EB00000012
+:0201EC00000011
+:0201ED00000010
+:0201EE0000000F
+:0201EF0000000E
+:0201F00000000D
+:0201F10000000C
+:0201F20000000B
+:0201F30000000A
+:0201F400000009
+:0201F500000008
+:0201F600000007
+:0201F700000006
+:0201F800000005
+:0201F900000004
+:0201FA00000003
+:0201FB00000002
+:0201FC00000001
+:0201FD00000000
+:0201FE000000FF
+:0201FF000000FE
+:020200000000FC
+:020201000000FB
+:020202000000FA
+:020203000000F9
+:020204000000F8
+:020205000000F7
+:020206000000F6
+:020207000000F5
+:020208000000F4
+:020209000000F3
+:02020A000000F2
+:02020B000000F1
+:02020C000000F0
+:02020D000000EF
+:02020E000000EE
+:02020F000000ED
+:020210000000EC
+:020211000000EB
+:020212000000EA
+:020213000000E9
+:020214000000E8
+:020215000000E7
+:020216000000E6
+:020217000000E5
+:020218000000E4
+:020219000000E3
+:02021A000000E2
+:02021B000000E1
+:02021C000000E0
+:02021D000000DF
+:02021E000000DE
+:02021F000000DD
+:020220000000DC
+:020221000000DB
+:020222000000DA
+:020223000000D9
+:020224000000D8
+:020225000000D7
+:020226000000D6
+:020227000000D5
+:020228000000D4
+:020229000000D3
+:02022A000000D2
+:02022B000000D1
+:02022C000000D0
+:02022D000000CF
+:02022E000000CE
+:02022F000000CD
+:020230000000CC
+:020231000000CB
+:020232000000CA
+:020233000000C9
+:020234000000C8
+:020235000000C7
+:020236000000C6
+:020237000000C5
+:020238000000C4
+:020239000000C3
+:02023A000000C2
+:02023B000000C1
+:02023C000000C0
+:02023D000000BF
+:02023E000000BE
+:02023F000000BD
+:020240000000BC
+:020241000000BB
+:020242000000BA
+:020243000000B9
+:020244000000B8
+:020245000000B7
+:020246000000B6
+:020247000000B5
+:020248000000B4
+:020249000000B3
+:02024A000000B2
+:02024B000000B1
+:02024C000000B0
+:02024D000000AF
+:02024E000000AE
+:02024F000000AD
+:020250000000AC
+:020251000000AB
+:020252000000AA
+:020253000000A9
+:020254000000A8
+:020255000000A7
+:020256000000A6
+:020257000000A5
+:020258000000A4
+:020259000000A3
+:02025A000000A2
+:02025B000000A1
+:02025C000000A0
+:02025D0000009F
+:02025E0000009E
+:02025F0000009D
+:0202600000009C
+:0202610000009B
+:0202620000009A
+:02026300000099
+:02026400000098
+:02026500000097
+:02026600000096
+:02026700000095
+:02026800000094
+:02026900000093
+:02026A00000092
+:02026B00000091
+:02026C00000090
+:02026D0000008F
+:02026E0000008E
+:02026F0000008D
+:0202700000008C
+:0202710000008B
+:0202720000008A
+:02027300000089
+:02027400000088
+:02027500000087
+:02027600000086
+:02027700000085
+:02027800000084
+:02027900000083
+:02027A00000082
+:02027B00000081
+:02027C00000080
+:02027D0000007F
+:02027E0000007E
+:02027F0000007D
+:0202800000007C
+:0202810000007B
+:0202820000007A
+:02028300000079
+:02028400000078
+:02028500000077
+:02028600000076
+:02028700000075
+:02028800000074
+:02028900000073
+:02028A00000072
+:02028B00000071
+:02028C00000070
+:02028D0000006F
+:02028E0000006E
+:02028F0000006D
+:0202900000006C
+:0202910000006B
+:0202920000006A
+:02029300000069
+:02029400000068
+:02029500000067
+:02029600000066
+:02029700000065
+:02029800000064
+:02029900000063
+:02029A00000062
+:02029B00000061
+:02029C00000060
+:02029D0000005F
+:02029E0000005E
+:02029F0000005D
+:0202A00000005C
+:0202A10000005B
+:0202A20000005A
+:0202A300000059
+:0202A400000058
+:0202A500000057
+:0202A600000056
+:0202A700000055
+:0202A800000054
+:0202A900000053
+:0202AA00000052
+:0202AB00000051
+:0202AC00000050
+:0202AD0000004F
+:0202AE0000004E
+:0202AF0000004D
+:0202B00000004C
+:0202B10000004B
+:0202B20000004A
+:0202B300000049
+:0202B400000048
+:0202B500000047
+:0202B600000046
+:0202B700000045
+:0202B800000044
+:0202B900000043
+:0202BA00000042
+:0202BB00000041
+:0202BC00000040
+:0202BD0000003F
+:0202BE0000003E
+:0202BF0000003D
+:0202C00000003C
+:0202C10000003B
+:0202C20000003A
+:0202C300000039
+:0202C400000038
+:0202C500000037
+:0202C600000036
+:0202C700000035
+:0202C800000034
+:0202C900000033
+:0202CA00000032
+:0202CB00000031
+:0202CC00000030
+:0202CD0000002F
+:0202CE0000002E
+:0202CF0000002D
+:0202D00000002C
+:0202D10000002B
+:0202D20000002A
+:0202D300000029
+:0202D400000028
+:0202D500000027
+:0202D600000026
+:0202D700000025
+:0202D800000024
+:0202D900000023
+:0202DA00000022
+:0202DB00000021
+:0202DC00000020
+:0202DD0000001F
+:0202DE0000001E
+:0202DF0000001D
+:0202E00000001C
+:0202E10000001B
+:0202E20000001A
+:0202E300000019
+:0202E400000018
+:0202E500000017
+:0202E600000016
+:0202E700000015
+:0202E800000014
+:0202E900000013
+:0202EA00000012
+:0202EB00000011
+:0202EC00000010
+:0202ED0000000F
+:0202EE0000000E
+:0202EF0000000D
+:0202F00000000C
+:0202F10000000B
+:0202F20000000A
+:0202F300000009
+:0202F400000008
+:0202F500000007
+:0202F600000006
+:0202F700000005
+:0202F800000004
+:0202F900000003
+:0202FA00000002
+:0202FB00000001
+:0202FC00000000
+:0202FD000000FF
+:0202FE000000FE
+:0202FF000000FD
+:020300000000FB
+:020301000000FA
+:020302000000F9
+:020303000000F8
+:020304000000F7
+:020305000000F6
+:020306000000F5
+:020307000000F4
+:020308000000F3
+:020309000000F2
+:02030A000000F1
+:02030B000000F0
+:02030C000000EF
+:02030D000000EE
+:02030E000000ED
+:02030F000000EC
+:020310000000EB
+:020311000000EA
+:020312000000E9
+:020313000000E8
+:020314000000E7
+:020315000000E6
+:020316000000E5
+:020317000000E4
+:020318000000E3
+:020319000000E2
+:02031A000000E1
+:02031B000000E0
+:02031C000000DF
+:02031D000000DE
+:02031E000000DD
+:02031F000000DC
+:020320000000DB
+:020321000000DA
+:020322000000D9
+:020323000000D8
+:020324000000D7
+:020325000000D6
+:020326000000D5
+:020327000000D4
+:020328000000D3
+:020329000000D2
+:02032A000000D1
+:02032B000000D0
+:02032C000000CF
+:02032D000000CE
+:02032E000000CD
+:02032F000000CC
+:020330000000CB
+:020331000000CA
+:020332000000C9
+:020333000000C8
+:020334000000C7
+:020335000000C6
+:020336000000C5
+:020337000000C4
+:020338000000C3
+:020339000000C2
+:02033A000000C1
+:02033B000000C0
+:02033C000000BF
+:02033D000000BE
+:02033E000000BD
+:02033F000000BC
+:020340000000BB
+:020341000000BA
+:020342000000B9
+:020343000000B8
+:020344000000B7
+:020345000000B6
+:020346000000B5
+:020347000000B4
+:020348000000B3
+:020349000000B2
+:02034A000000B1
+:02034B000000B0
+:02034C000000AF
+:02034D000000AE
+:02034E000000AD
+:02034F000000AC
+:020350000000AB
+:020351000000AA
+:020352000000A9
+:020353000000A8
+:020354000000A7
+:020355000000A6
+:020356000000A5
+:020357000000A4
+:020358000000A3
+:020359000000A2
+:02035A000000A1
+:02035B000000A0
+:02035C0000009F
+:02035D0000009E
+:02035E0000009D
+:02035F0000009C
+:0203600000009B
+:0203610000009A
+:02036200000099
+:02036300000098
+:02036400000097
+:02036500000096
+:02036600000095
+:02036700000094
+:02036800000093
+:02036900000092
+:02036A00000091
+:02036B00000090
+:02036C0000008F
+:02036D0000008E
+:02036E0000008D
+:02036F0000008C
+:0203700000008B
+:0203710000008A
+:02037200000089
+:02037300000088
+:02037400000087
+:02037500000086
+:02037600000085
+:02037700000084
+:02037800000083
+:02037900000082
+:02037A00000081
+:02037B00000080
+:02037C0000007F
+:02037D0000007E
+:02037E0000007D
+:02037F0000007C
+:0203800000007B
+:0203810000007A
+:02038200000079
+:02038300000078
+:02038400000077
+:02038500000076
+:02038600000075
+:02038700000074
+:02038800000073
+:02038900000072
+:02038A00000071
+:02038B00000070
+:02038C0000006F
+:02038D0000006E
+:02038E0000006D
+:02038F0000006C
+:0203900000006B
+:0203910000006A
+:02039200000069
+:02039300000068
+:02039400000067
+:02039500000066
+:02039600000065
+:02039700000064
+:02039800000063
+:02039900000062
+:02039A00000061
+:02039B00000060
+:02039C0000005F
+:02039D0000005E
+:02039E0000005D
+:02039F0000005C
+:0203A00000005B
+:0203A10000005A
+:0203A200000059
+:0203A300000058
+:0203A400000057
+:0203A500000056
+:0203A600000055
+:0203A700000054
+:0203A800000053
+:0203A900000052
+:0203AA00000051
+:0203AB00000050
+:0203AC0000004F
+:0203AD0000004E
+:0203AE0000004D
+:0203AF0000004C
+:0203B00000004B
+:0203B10000004A
+:0203B200000049
+:0203B300000048
+:0203B400000047
+:0203B500000046
+:0203B600000045
+:0203B700000044
+:0203B800000043
+:0203B900000042
+:0203BA00000041
+:0203BB00000040
+:0203BC0000003F
+:0203BD0000003E
+:0203BE0000003D
+:0203BF0000003C
+:0203C00000003B
+:0203C10000003A
+:0203C200000039
+:0203C300000038
+:0203C400000037
+:0203C500000036
+:0203C600000035
+:0203C700000034
+:0203C800000033
+:0203C900000032
+:0203CA00000031
+:0203CB00000030
+:0203CC0000002F
+:0203CD0000002E
+:0203CE0000002D
+:0203CF0000002C
+:0203D00000002B
+:0203D10000002A
+:0203D200000029
+:0203D300000028
+:0203D400000027
+:0203D500000026
+:0203D600000025
+:0203D700000024
+:0203D800000023
+:0203D900000022
+:0203DA00000021
+:0203DB00000020
+:0203DC0000001F
+:0203DD0000001E
+:0203DE0000001D
+:0203DF0000001C
+:0203E00000001B
+:0203E10000001A
+:0203E200000019
+:0203E300000018
+:0203E400000017
+:0203E500000016
+:0203E600000015
+:0203E700000014
+:0203E800000013
+:0203E900000012
+:0203EA00000011
+:0203EB00000010
+:0203EC0000000F
+:0203ED0000000E
+:0203EE0000000D
+:0203EF0000000C
+:0203F00000000B
+:0203F10000000A
+:0203F200000009
+:0203F300000008
+:0203F400000007
+:0203F500000006
+:0203F600000005
+:0203F700000004
+:0203F800000003
+:0203F900000002
+:0203FA00000001
+:0203FB00000000
+:0203FC000000FF
+:0203FD000000FE
+:0203FE000000FD
+:0203FF000000FC
+:020400000000FA
+:020401000000F9
+:020402000000F8
+:020403000000F7
+:020404000000F6
+:020405000000F5
+:020406000000F4
+:020407000000F3
+:020408000000F2
+:020409000000F1
+:02040A000000F0
+:02040B000000EF
+:02040C000000EE
+:02040D000000ED
+:02040E000000EC
+:02040F000000EB
+:020410000000EA
+:020411000000E9
+:020412000000E8
+:020413000000E7
+:020414000000E6
+:020415000000E5
+:020416000000E4
+:020417000000E3
+:020418000000E2
+:020419000000E1
+:02041A000000E0
+:02041B000000DF
+:02041C000000DE
+:02041D000000DD
+:02041E000000DC
+:02041F000000DB
+:020420000000DA
+:020421000000D9
+:020422000000D8
+:020423000000D7
+:020424000000D6
+:020425000000D5
+:020426000000D4
+:020427000000D3
+:020428000000D2
+:020429000000D1
+:02042A000000D0
+:02042B000000CF
+:02042C000000CE
+:02042D000000CD
+:02042E000000CC
+:02042F000000CB
+:020430000000CA
+:020431000000C9
+:020432000000C8
+:020433000000C7
+:020434000000C6
+:020435000000C5
+:020436000000C4
+:020437000000C3
+:020438000000C2
+:020439000000C1
+:02043A000000C0
+:02043B000000BF
+:02043C000000BE
+:02043D000000BD
+:02043E000000BC
+:02043F000000BB
+:020440000000BA
+:020441000000B9
+:020442000000B8
+:020443000000B7
+:020444000000B6
+:020445000000B5
+:020446000000B4
+:020447000000B3
+:020448000000B2
+:020449000000B1
+:02044A000000B0
+:02044B000000AF
+:02044C000000AE
+:02044D000000AD
+:02044E000000AC
+:02044F000000AB
+:020450000000AA
+:020451000000A9
+:020452000000A8
+:020453000000A7
+:020454000000A6
+:020455000000A5
+:020456000000A4
+:020457000000A3
+:020458000000A2
+:020459000000A1
+:02045A000000A0
+:02045B0000009F
+:02045C0000009E
+:02045D0000009D
+:02045E0000009C
+:02045F0000009B
+:0204600000009A
+:02046100000099
+:02046200000098
+:02046300000097
+:02046400000096
+:02046500000095
+:02046600000094
+:02046700000093
+:02046800000092
+:02046900000091
+:02046A00000090
+:02046B0000008F
+:02046C0000008E
+:02046D0000008D
+:02046E0000008C
+:02046F0000008B
+:0204700000008A
+:02047100000089
+:02047200000088
+:02047300000087
+:02047400000086
+:02047500000085
+:02047600000084
+:02047700000083
+:02047800000082
+:02047900000081
+:02047A00000080
+:02047B0000007F
+:02047C0000007E
+:02047D0000007D
+:02047E0000007C
+:02047F0000007B
+:0204800000007A
+:02048100000079
+:02048200000078
+:02048300000077
+:02048400000076
+:02048500000075
+:02048600000074
+:02048700000073
+:02048800000072
+:02048900000071
+:02048A00000070
+:02048B0000006F
+:02048C0000006E
+:02048D0000006D
+:02048E0000006C
+:02048F0000006B
+:0204900000006A
+:02049100000069
+:02049200000068
+:02049300000067
+:02049400000066
+:02049500000065
+:02049600000064
+:02049700000063
+:02049800000062
+:02049900000061
+:02049A00000060
+:02049B0000005F
+:02049C0000005E
+:02049D0000005D
+:02049E0000005C
+:02049F0000005B
+:0204A00000005A
+:0204A100000059
+:0204A200000058
+:0204A300000057
+:0204A400000056
+:0204A500000055
+:0204A600000054
+:0204A700000053
+:0204A800000052
+:0204A900000051
+:0204AA00000050
+:0204AB0000004F
+:0204AC0000004E
+:0204AD0000004D
+:0204AE0000004C
+:0204AF0000004B
+:0204B00000004A
+:0204B100000049
+:0204B200000048
+:0204B300000047
+:0204B400000046
+:0204B500000045
+:0204B600000044
+:0204B700000043
+:0204B800000042
+:0204B900000041
+:0204BA00000040
+:0204BB0000003F
+:0204BC0000003E
+:0204BD0000003D
+:0204BE0000003C
+:0204BF0000003B
+:0204C00000003A
+:0204C100000039
+:0204C200000038
+:0204C300000037
+:0204C400000036
+:0204C500000035
+:0204C600000034
+:0204C700000033
+:0204C800000032
+:0204C900000031
+:0204CA00000030
+:0204CB0000002F
+:0204CC0000002E
+:0204CD0000002D
+:0204CE0000002C
+:0204CF0000002B
+:0204D00000002A
+:0204D100000029
+:0204D200000028
+:0204D300000027
+:0204D400000026
+:0204D500000025
+:0204D600000024
+:0204D700000023
+:0204D800000022
+:0204D900000021
+:0204DA00000020
+:0204DB0000001F
+:0204DC0000001E
+:0204DD0000001D
+:0204DE0000001C
+:0204DF0000001B
+:0204E00000001A
+:0204E100000019
+:0204E200000018
+:0204E300000017
+:0204E400000016
+:0204E500000015
+:0204E600000014
+:0204E700000013
+:0204E800000012
+:0204E900000011
+:0204EA00000010
+:0204EB0000000F
+:0204EC0000000E
+:0204ED0000000D
+:0204EE0000000C
+:0204EF0000000B
+:0204F00000000A
+:0204F100000009
+:0204F200000008
+:0204F300000007
+:0204F400000006
+:0204F500000005
+:0204F600000004
+:0204F700000003
+:0204F800000002
+:0204F900000001
+:0204FA00000000
+:0204FB000000FF
+:0204FC000000FE
+:0204FD000000FD
+:0204FE000000FC
+:0204FF000000FB
+:020500000000F9
+:020501000000F8
+:020502000000F7
+:020503000000F6
+:020504000000F5
+:020505000000F4
+:020506000000F3
+:020507000000F2
+:020508000000F1
+:020509000000F0
+:02050A000000EF
+:02050B000000EE
+:02050C000000ED
+:02050D000000EC
+:02050E000000EB
+:02050F000000EA
+:020510000000E9
+:020511000000E8
+:020512000000E7
+:020513000000E6
+:020514000000E5
+:020515000000E4
+:020516000000E3
+:020517000000E2
+:020518000000E1
+:020519000000E0
+:02051A000000DF
+:02051B000000DE
+:02051C000000DD
+:02051D000000DC
+:02051E000000DB
+:02051F000000DA
+:020520000000D9
+:020521000000D8
+:020522000000D7
+:020523000000D6
+:020524000000D5
+:020525000000D4
+:020526000000D3
+:020527000000D2
+:020528000000D1
+:020529000000D0
+:02052A000000CF
+:02052B000000CE
+:02052C000000CD
+:02052D000000CC
+:02052E000000CB
+:02052F000000CA
+:020530000000C9
+:020531000000C8
+:020532000000C7
+:020533000000C6
+:020534000000C5
+:020535000000C4
+:020536000000C3
+:020537000000C2
+:020538000000C1
+:020539000000C0
+:02053A000000BF
+:02053B000000BE
+:02053C000000BD
+:02053D000000BC
+:02053E000000BB
+:02053F000000BA
+:020540000000B9
+:020541000000B8
+:020542000000B7
+:020543000000B6
+:020544000000B5
+:020545000000B4
+:020546000000B3
+:020547000000B2
+:020548000000B1
+:020549000000B0
+:02054A000000AF
+:02054B000000AE
+:02054C000000AD
+:02054D000000AC
+:02054E000000AB
+:02054F000000AA
+:020550000000A9
+:020551000000A8
+:020552000000A7
+:020553000000A6
+:020554000000A5
+:020555000000A4
+:020556000000A3
+:020557000000A2
+:020558000000A1
+:020559000000A0
+:02055A0000009F
+:02055B0000009E
+:02055C0000009D
+:02055D0000009C
+:02055E0000009B
+:02055F0000009A
+:02056000000099
+:02056100000098
+:02056200000097
+:02056300000096
+:02056400000095
+:02056500000094
+:02056600000093
+:02056700000092
+:02056800000091
+:02056900000090
+:02056A0000008F
+:02056B0000008E
+:02056C0000008D
+:02056D0000008C
+:02056E0000008B
+:02056F0000008A
+:02057000000089
+:02057100000088
+:02057200000087
+:02057300000086
+:02057400000085
+:02057500000084
+:02057600000083
+:02057700000082
+:02057800000081
+:02057900000080
+:02057A0000007F
+:02057B0000007E
+:02057C0000007D
+:02057D0000007C
+:02057E0000007B
+:02057F0000007A
+:02058000000079
+:02058100000078
+:02058200000077
+:02058300000076
+:02058400000075
+:02058500000074
+:02058600000073
+:02058700000072
+:02058800000071
+:02058900000070
+:02058A0000006F
+:02058B0000006E
+:02058C0000006D
+:02058D0000006C
+:02058E0000006B
+:02058F0000006A
+:02059000000069
+:02059100000068
+:02059200000067
+:02059300000066
+:02059400000065
+:02059500000064
+:02059600000063
+:02059700000062
+:02059800000061
+:02059900000060
+:02059A0000005F
+:02059B0000005E
+:02059C0000005D
+:02059D0000005C
+:02059E0000005B
+:02059F0000005A
+:0205A000000059
+:0205A100000058
+:0205A200000057
+:0205A300000056
+:0205A400000055
+:0205A500000054
+:0205A600000053
+:0205A700000052
+:0205A800000051
+:0205A900000050
+:0205AA0000004F
+:0205AB0000004E
+:0205AC0000004D
+:0205AD0000004C
+:0205AE0000004B
+:0205AF0000004A
+:0205B000000049
+:0205B100000048
+:0205B200000047
+:0205B300000046
+:0205B400000045
+:0205B500000044
+:0205B600000043
+:0205B700000042
+:0205B800000041
+:0205B900000040
+:0205BA0000003F
+:0205BB0000003E
+:0205BC0000003D
+:0205BD0000003C
+:0205BE0000003B
+:0205BF0000003A
+:0205C000000039
+:0205C100000038
+:0205C200000037
+:0205C300000036
+:0205C400000035
+:0205C500000034
+:0205C600000033
+:0205C700000032
+:0205C800000031
+:0205C900000030
+:0205CA0000002F
+:0205CB0000002E
+:0205CC0000002D
+:0205CD0000002C
+:0205CE0000002B
+:0205CF0000002A
+:0205D000000029
+:0205D100000028
+:0205D200000027
+:0205D300000026
+:0205D400000025
+:0205D500000024
+:0205D600000023
+:0205D700000022
+:0205D800000021
+:0205D900000020
+:0205DA0000001F
+:0205DB0000001E
+:0205DC0000001D
+:0205DD0000001C
+:0205DE0000001B
+:0205DF0000001A
+:0205E000000019
+:0205E100000018
+:0205E200000017
+:0205E300000016
+:0205E400000015
+:0205E500000014
+:0205E600000013
+:0205E700000012
+:0205E800000011
+:0205E900000010
+:0205EA0000000F
+:0205EB0000000E
+:0205EC0000000D
+:0205ED0000000C
+:0205EE0000000B
+:0205EF0000000A
+:0205F000000009
+:0205F100000008
+:0205F200000007
+:0205F300000006
+:0205F400000005
+:0205F500000004
+:0205F600000003
+:0205F700000002
+:0205F800000001
+:0205F900000000
+:0205FA000000FF
+:0205FB000000FE
+:0205FC000000FD
+:0205FD000000FC
+:0205FE000000FB
+:0205FF000000FA
+:020600000000F8
+:020601000000F7
+:020602000000F6
+:020603000000F5
+:020604000000F4
+:020605000000F3
+:020606000000F2
+:020607000000F1
+:020608000000F0
+:020609000000EF
+:02060A000000EE
+:02060B000000ED
+:02060C000000EC
+:02060D000000EB
+:02060E000000EA
+:02060F000000E9
+:020610000000E8
+:020611000000E7
+:020612000000E6
+:020613000000E5
+:020614000000E4
+:020615000000E3
+:020616000000E2
+:020617000000E1
+:020618000000E0
+:020619000000DF
+:02061A000000DE
+:02061B000000DD
+:02061C000000DC
+:02061D000000DB
+:02061E000000DA
+:02061F000000D9
+:020620000000D8
+:020621000000D7
+:020622000000D6
+:020623000000D5
+:020624000000D4
+:020625000000D3
+:020626000000D2
+:020627000000D1
+:020628000000D0
+:020629000000CF
+:02062A000000CE
+:02062B000000CD
+:02062C000000CC
+:02062D000000CB
+:02062E000000CA
+:02062F000000C9
+:020630000000C8
+:020631000000C7
+:020632000000C6
+:020633000000C5
+:020634000000C4
+:020635000000C3
+:020636000000C2
+:020637000000C1
+:020638000000C0
+:020639000000BF
+:02063A000000BE
+:02063B000000BD
+:02063C000000BC
+:02063D000000BB
+:02063E000000BA
+:02063F000000B9
+:020640000000B8
+:020641000000B7
+:020642000000B6
+:020643000000B5
+:020644000000B4
+:020645000000B3
+:020646000000B2
+:020647000000B1
+:020648000000B0
+:020649000000AF
+:02064A000000AE
+:02064B000000AD
+:02064C000000AC
+:02064D000000AB
+:02064E000000AA
+:02064F000000A9
+:020650000000A8
+:020651000000A7
+:020652000000A6
+:020653000000A5
+:020654000000A4
+:020655000000A3
+:020656000000A2
+:020657000000A1
+:020658000000A0
+:0206590000009F
+:02065A0000009E
+:02065B0000009D
+:02065C0000009C
+:02065D0000009B
+:02065E0000009A
+:02065F00000099
+:02066000000098
+:02066100000097
+:02066200000096
+:02066300000095
+:02066400000094
+:02066500000093
+:02066600000092
+:02066700000091
+:02066800000090
+:0206690000008F
+:02066A0000008E
+:02066B0000008D
+:02066C0000008C
+:02066D0000008B
+:02066E0000008A
+:02066F00000089
+:02067000000088
+:02067100000087
+:02067200000086
+:02067300000085
+:02067400000084
+:02067500000083
+:02067600000082
+:02067700000081
+:02067800000080
+:0206790000007F
+:02067A0000007E
+:02067B0000007D
+:02067C0000007C
+:02067D0000007B
+:02067E0000007A
+:02067F00000079
+:02068000000078
+:02068100000077
+:02068200000076
+:02068300000075
+:02068400000074
+:02068500000073
+:02068600000072
+:02068700000071
+:02068800000070
+:0206890000006F
+:02068A0000006E
+:02068B0000006D
+:02068C0000006C
+:02068D0000006B
+:02068E0000006A
+:02068F00000069
+:02069000000068
+:02069100000067
+:02069200000066
+:02069300000065
+:02069400000064
+:02069500000063
+:02069600000062
+:02069700000061
+:02069800000060
+:0206990000005F
+:02069A0000005E
+:02069B0000005D
+:02069C0000005C
+:02069D0000005B
+:02069E0000005A
+:02069F00000059
+:0206A000000058
+:0206A100000057
+:0206A200000056
+:0206A300000055
+:0206A400000054
+:0206A500000053
+:0206A600000052
+:0206A700000051
+:0206A800000050
+:0206A90000004F
+:0206AA0000004E
+:0206AB0000004D
+:0206AC0000004C
+:0206AD0000004B
+:0206AE0000004A
+:0206AF00000049
+:0206B000000048
+:0206B100000047
+:0206B200000046
+:0206B300000045
+:0206B400000044
+:0206B500000043
+:0206B600000042
+:0206B700000041
+:0206B800000040
+:0206B90000003F
+:0206BA0000003E
+:0206BB0000003D
+:0206BC0000003C
+:0206BD0000003B
+:0206BE0000003A
+:0206BF00000039
+:0206C000000038
+:0206C100000037
+:0206C200000036
+:0206C300000035
+:0206C400000034
+:0206C500000033
+:0206C600000032
+:0206C700000031
+:0206C800000030
+:0206C90000002F
+:0206CA0000002E
+:0206CB0000002D
+:0206CC0000002C
+:0206CD0000002B
+:0206CE0000002A
+:0206CF00000029
+:0206D000000028
+:0206D100000027
+:0206D200000026
+:0206D300000025
+:0206D400000024
+:0206D500000023
+:0206D600000022
+:0206D700000021
+:0206D800000020
+:0206D90000001F
+:0206DA0000001E
+:0206DB0000001D
+:0206DC0000001C
+:0206DD0000001B
+:0206DE0000001A
+:0206DF00000019
+:0206E000000018
+:0206E100000017
+:0206E200000016
+:0206E300000015
+:0206E400000014
+:0206E500000013
+:0206E600000012
+:0206E700000011
+:0206E800000010
+:0206E90000000F
+:0206EA0000000E
+:0206EB0000000D
+:0206EC0000000C
+:0206ED0000000B
+:0206EE0000000A
+:0206EF00000009
+:0206F000000008
+:0206F100000007
+:0206F200000006
+:0206F300000005
+:0206F400000004
+:0206F500000003
+:0206F600000002
+:0206F700000001
+:0206F800000000
+:0206F9000000FF
+:0206FA000000FE
+:0206FB000000FD
+:0206FC000000FC
+:0206FD000000FB
+:0206FE000000FA
+:0206FF000000F9
+:020700000000F7
+:020701000000F6
+:020702000000F5
+:020703000000F4
+:020704000000F3
+:020705000000F2
+:020706000000F1
+:020707000000F0
+:020708000000EF
+:020709000000EE
+:02070A000000ED
+:02070B000000EC
+:02070C000000EB
+:02070D000000EA
+:02070E000000E9
+:02070F000000E8
+:020710000000E7
+:020711000000E6
+:020712000000E5
+:020713000000E4
+:020714000000E3
+:020715000000E2
+:020716000000E1
+:020717000000E0
+:020718000000DF
+:020719000000DE
+:02071A000000DD
+:02071B000000DC
+:02071C000000DB
+:02071D000000DA
+:02071E000000D9
+:02071F000000D8
+:020720000000D7
+:020721000000D6
+:020722000000D5
+:020723000000D4
+:020724000000D3
+:020725000000D2
+:020726000000D1
+:020727000000D0
+:020728000000CF
+:020729000000CE
+:02072A000000CD
+:02072B000000CC
+:02072C000000CB
+:02072D000000CA
+:02072E000000C9
+:02072F000000C8
+:020730000000C7
+:020731000000C6
+:020732000000C5
+:020733000000C4
+:020734000000C3
+:020735000000C2
+:020736000000C1
+:020737000000C0
+:020738000000BF
+:020739000000BE
+:02073A000000BD
+:02073B000000BC
+:02073C000000BB
+:02073D000000BA
+:02073E000000B9
+:02073F000000B8
+:020740000000B7
+:020741000000B6
+:020742000000B5
+:020743000000B4
+:020744000000B3
+:020745000000B2
+:020746000000B1
+:020747000000B0
+:020748000000AF
+:020749000000AE
+:02074A000000AD
+:02074B000000AC
+:02074C000000AB
+:02074D000000AA
+:02074E000000A9
+:02074F000000A8
+:020750000000A7
+:020751000000A6
+:020752000000A5
+:020753000000A4
+:020754000000A3
+:020755000000A2
+:020756000000A1
+:020757000000A0
+:0207580000009F
+:0207590000009E
+:02075A0000009D
+:02075B0000009C
+:02075C0000009B
+:02075D0000009A
+:02075E00000099
+:02075F00000098
+:02076000000097
+:02076100000096
+:02076200000095
+:02076300000094
+:02076400000093
+:02076500000092
+:02076600000091
+:02076700000090
+:0207680000008F
+:0207690000008E
+:02076A0000008D
+:02076B0000008C
+:02076C0000008B
+:02076D0000008A
+:02076E00000089
+:02076F00000088
+:02077000000087
+:02077100000086
+:02077200000085
+:02077300000084
+:02077400000083
+:02077500000082
+:02077600000081
+:02077700000080
+:0207780000007F
+:0207790000007E
+:02077A0000007D
+:02077B0000007C
+:02077C0000007B
+:02077D0000007A
+:02077E00000079
+:02077F00000078
+:02078000000077
+:02078100000076
+:02078200000075
+:02078300000074
+:02078400000073
+:02078500000072
+:02078600000071
+:02078700000070
+:0207880000006F
+:0207890000006E
+:02078A0000006D
+:02078B0000006C
+:02078C0000006B
+:02078D0000006A
+:02078E00000069
+:02078F00000068
+:02079000000067
+:02079100000066
+:02079200000065
+:02079300000064
+:02079400000063
+:02079500000062
+:02079600000061
+:02079700000060
+:0207980000005F
+:0207990000005E
+:02079A0000005D
+:02079B0000005C
+:02079C0000005B
+:02079D0000005A
+:02079E00000059
+:02079F00000058
+:0207A000000057
+:0207A100000056
+:0207A200000055
+:0207A300000054
+:0207A400000053
+:0207A500000052
+:0207A600000051
+:0207A700000050
+:0207A80000004F
+:0207A90000004E
+:0207AA0000004D
+:0207AB0000004C
+:0207AC0000004B
+:0207AD0000004A
+:0207AE00000049
+:0207AF00000048
+:0207B000000047
+:0207B100000046
+:0207B200000045
+:0207B300000044
+:0207B400000043
+:0207B500000042
+:0207B600000041
+:0207B700000040
+:0207B80000003F
+:0207B90000003E
+:0207BA0000003D
+:0207BB0000003C
+:0207BC0000003B
+:0207BD0000003A
+:0207BE00000039
+:0207BF00000038
+:0207C000000037
+:0207C100000036
+:0207C200000035
+:0207C300000034
+:0207C400000033
+:0207C500000032
+:0207C600000031
+:0207C700000030
+:0207C80000002F
+:0207C90000002E
+:0207CA0000002D
+:0207CB0000002C
+:0207CC0000002B
+:0207CD0000002A
+:0207CE00000029
+:0207CF00000028
+:0207D000000027
+:0207D100000026
+:0207D200000025
+:0207D300000024
+:0207D400000023
+:0207D500000022
+:0207D600000021
+:0207D700000020
+:0207D80000001F
+:0207D90000001E
+:0207DA0000001D
+:0207DB0000001C
+:0207DC0000001B
+:0207DD0000001A
+:0207DE00000019
+:0207DF00000018
+:0207E000000017
+:0207E100000016
+:0207E200000015
+:0207E300000014
+:0207E400000013
+:0207E500000012
+:0207E600000011
+:0207E700000010
+:0207E80000000F
+:0207E90000000E
+:0207EA0000000D
+:0207EB0000000C
+:0207EC0000000B
+:0207ED0000000A
+:0207EE00000009
+:0207EF00000008
+:0207F000000007
+:0207F100000006
+:0207F200000005
+:0207F300000004
+:0207F400000003
+:0207F500000002
+:0207F600000001
+:0207F700000000
+:0207F8000000FF
+:0207F9000000FE
+:0207FA000000FD
+:0207FB000000FC
+:0207FC000000FB
+:0207FD000000FA
+:0207FE000000F9
+:0207FF000000F8
+:020800000000F6
+:020801000000F5
+:020802000000F4
+:020803000000F3
+:020804000000F2
+:020805000000F1
+:020806000000F0
+:020807000000EF
+:020808000000EE
+:020809000000ED
+:02080A000000EC
+:02080B000000EB
+:02080C000000EA
+:02080D000000E9
+:02080E000000E8
+:02080F000000E7
+:020810000000E6
+:020811000000E5
+:020812000000E4
+:020813000000E3
+:020814000000E2
+:020815000000E1
+:020816000000E0
+:020817000000DF
+:020818000000DE
+:020819000000DD
+:02081A000000DC
+:02081B000000DB
+:02081C000000DA
+:02081D000000D9
+:02081E000000D8
+:02081F000000D7
+:020820000000D6
+:020821000000D5
+:020822000000D4
+:020823000000D3
+:020824000000D2
+:020825000000D1
+:020826000000D0
+:020827000000CF
+:020828000000CE
+:020829000000CD
+:02082A000000CC
+:02082B000000CB
+:02082C000000CA
+:02082D000000C9
+:02082E000000C8
+:02082F000000C7
+:020830000000C6
+:020831000000C5
+:020832000000C4
+:020833000000C3
+:020834000000C2
+:020835000000C1
+:020836000000C0
+:020837000000BF
+:020838000000BE
+:020839000000BD
+:02083A000000BC
+:02083B000000BB
+:02083C000000BA
+:02083D000000B9
+:02083E000000B8
+:02083F000000B7
+:020840000000B6
+:020841000000B5
+:020842000000B4
+:020843000000B3
+:020844000000B2
+:020845000000B1
+:020846000000B0
+:020847000000AF
+:020848000000AE
+:020849000000AD
+:02084A000000AC
+:02084B000000AB
+:02084C000000AA
+:02084D000000A9
+:02084E000000A8
+:02084F000000A7
+:020850000000A6
+:020851000000A5
+:020852000000A4
+:020853000000A3
+:020854000000A2
+:020855000000A1
+:020856000000A0
+:0208570000009F
+:0208580000009E
+:0208590000009D
+:02085A0000009C
+:02085B0000009B
+:02085C0000009A
+:02085D00000099
+:02085E00000098
+:02085F00000097
+:02086000000096
+:02086100000095
+:02086200000094
+:02086300000093
+:02086400000092
+:02086500000091
+:02086600000090
+:0208670000008F
+:0208680000008E
+:0208690000008D
+:02086A0000008C
+:02086B0000008B
+:02086C0000008A
+:02086D00000089
+:02086E00000088
+:02086F00000087
+:02087000000086
+:02087100000085
+:02087200000084
+:02087300000083
+:02087400000082
+:02087500000081
+:02087600000080
+:0208770000007F
+:0208780000007E
+:0208790000007D
+:02087A0000007C
+:02087B0000007B
+:02087C0000007A
+:02087D00000079
+:02087E00000078
+:02087F00000077
+:02088000000076
+:02088100000075
+:02088200000074
+:02088300000073
+:02088400000072
+:02088500000071
+:02088600000070
+:0208870000006F
+:0208880000006E
+:0208890000006D
+:02088A0000006C
+:02088B0000006B
+:02088C0000006A
+:02088D00000069
+:02088E00000068
+:02088F00000067
+:02089000000066
+:02089100000065
+:02089200000064
+:02089300000063
+:02089400000062
+:02089500000061
+:02089600000060
+:0208970000005F
+:0208980000005E
+:0208990000005D
+:02089A0000005C
+:02089B0000005B
+:02089C0000005A
+:02089D00000059
+:02089E00000058
+:02089F00000057
+:0208A000000056
+:0208A100000055
+:0208A200000054
+:0208A300000053
+:0208A400000052
+:0208A500000051
+:0208A600000050
+:0208A70000004F
+:0208A80000004E
+:0208A90000004D
+:0208AA0000004C
+:0208AB0000004B
+:0208AC0000004A
+:0208AD00000049
+:0208AE00000048
+:0208AF00000047
+:0208B000000046
+:0208B100000045
+:0208B200000044
+:0208B300000043
+:0208B400000042
+:0208B500000041
+:0208B600000040
+:0208B70000003F
+:0208B80000003E
+:0208B90000003D
+:0208BA0000003C
+:0208BB0000003B
+:0208BC0000003A
+:0208BD00000039
+:0208BE00000038
+:0208BF00000037
+:0208C000000036
+:0208C100000035
+:0208C200000034
+:0208C300000033
+:0208C400000032
+:0208C500000031
+:0208C600000030
+:0208C70000002F
+:0208C80000002E
+:0208C90000002D
+:0208CA0000002C
+:0208CB0000002B
+:0208CC0000002A
+:0208CD00000029
+:0208CE00000028
+:0208CF00000027
+:0208D000000026
+:0208D100000025
+:0208D200000024
+:0208D300000023
+:0208D400000022
+:0208D500000021
+:0208D600000020
+:0208D70000001F
+:0208D80000001E
+:0208D90000001D
+:0208DA0000001C
+:0208DB0000001B
+:0208DC0000001A
+:0208DD00000019
+:0208DE00000018
+:0208DF00000017
+:0208E000000016
+:0208E100000015
+:0208E200000014
+:0208E300000013
+:0208E400000012
+:0208E500000011
+:0208E600000010
+:0208E70000000F
+:0208E80000000E
+:0208E90000000D
+:0208EA0000000C
+:0208EB0000000B
+:0208EC0000000A
+:0208ED00000009
+:0208EE00000008
+:0208EF00000007
+:0208F000000006
+:0208F100000005
+:0208F200000004
+:0208F300000003
+:0208F400000002
+:0208F500000001
+:0208F600000000
+:0208F7000000FF
+:0208F8000000FE
+:0208F9000000FD
+:0208FA000000FC
+:0208FB000000FB
+:0208FC000000FA
+:0208FD000000F9
+:0208FE000000F8
+:0208FF000000F7
+:020900000000F5
+:020901000000F4
+:020902000000F3
+:020903000000F2
+:020904000000F1
+:020905000000F0
+:020906000000EF
+:020907000000EE
+:020908000000ED
+:020909000000EC
+:02090A000000EB
+:02090B000000EA
+:02090C000000E9
+:02090D000000E8
+:02090E000000E7
+:02090F000000E6
+:020910000000E5
+:020911000000E4
+:020912000000E3
+:020913000000E2
+:020914000000E1
+:020915000000E0
+:020916000000DF
+:020917000000DE
+:020918000000DD
+:020919000000DC
+:02091A000000DB
+:02091B000000DA
+:02091C000000D9
+:02091D000000D8
+:02091E000000D7
+:02091F000000D6
+:020920000000D5
+:020921000000D4
+:020922000000D3
+:020923000000D2
+:020924000000D1
+:020925000000D0
+:020926000000CF
+:020927000000CE
+:020928000000CD
+:020929000000CC
+:02092A000000CB
+:02092B000000CA
+:02092C000000C9
+:02092D000000C8
+:02092E000000C7
+:02092F000000C6
+:020930000000C5
+:020931000000C4
+:020932000000C3
+:020933000000C2
+:020934000000C1
+:020935000000C0
+:020936000000BF
+:020937000000BE
+:020938000000BD
+:020939000000BC
+:02093A000000BB
+:02093B000000BA
+:02093C000000B9
+:02093D000000B8
+:02093E000000B7
+:02093F000000B6
+:020940000000B5
+:020941000000B4
+:020942000000B3
+:020943000000B2
+:020944000000B1
+:020945000000B0
+:020946000000AF
+:020947000000AE
+:020948000000AD
+:020949000000AC
+:02094A000000AB
+:02094B000000AA
+:02094C000000A9
+:02094D000000A8
+:02094E000000A7
+:02094F000000A6
+:020950000000A5
+:020951000000A4
+:020952000000A3
+:020953000000A2
+:020954000000A1
+:020955000000A0
+:0209560000009F
+:0209570000009E
+:0209580000009D
+:0209590000009C
+:02095A0000009B
+:02095B0000009A
+:02095C00000099
+:02095D00000098
+:02095E00000097
+:02095F00000096
+:02096000000095
+:02096100000094
+:02096200000093
+:02096300000092
+:02096400000091
+:02096500000090
+:0209660000008F
+:0209670000008E
+:0209680000008D
+:0209690000008C
+:02096A0000008B
+:02096B0000008A
+:02096C00000089
+:02096D00000088
+:02096E00000087
+:02096F00000086
+:02097000000085
+:02097100000084
+:02097200000083
+:02097300000082
+:02097400000081
+:02097500000080
+:0209760000007F
+:0209770000007E
+:0209780000007D
+:0209790000007C
+:02097A0000007B
+:02097B0000007A
+:02097C00000079
+:02097D00000078
+:02097E00000077
+:02097F00000076
+:02098000000075
+:02098100000074
+:02098200000073
+:02098300000072
+:02098400000071
+:02098500000070
+:0209860000006F
+:0209870000006E
+:0209880000006D
+:0209890000006C
+:02098A0000006B
+:02098B0000006A
+:02098C00000069
+:02098D00000068
+:02098E00000067
+:02098F00000066
+:02099000000065
+:02099100000064
+:02099200000063
+:02099300000062
+:02099400000061
+:02099500000060
+:0209960000005F
+:0209970000005E
+:0209980000005D
+:0209990000005C
+:02099A0000005B
+:02099B0000005A
+:02099C00000059
+:02099D00000058
+:02099E00000057
+:02099F00000056
+:0209A000000055
+:0209A100000054
+:0209A200000053
+:0209A300000052
+:0209A400000051
+:0209A500000050
+:0209A60000004F
+:0209A70000004E
+:0209A80000004D
+:0209A90000004C
+:0209AA0000004B
+:0209AB0000004A
+:0209AC00000049
+:0209AD00000048
+:0209AE00000047
+:0209AF00000046
+:0209B000000045
+:0209B100000044
+:0209B200000043
+:0209B300000042
+:0209B400000041
+:0209B500000040
+:0209B60000003F
+:0209B70000003E
+:0209B80000003D
+:0209B90000003C
+:0209BA0000003B
+:0209BB0000003A
+:0209BC00000039
+:0209BD00000038
+:0209BE00000037
+:0209BF00000036
+:0209C000000035
+:0209C100000034
+:0209C200000033
+:0209C300000032
+:0209C400000031
+:0209C500000030
+:0209C60000002F
+:0209C70000002E
+:0209C80000002D
+:0209C90000002C
+:0209CA0000002B
+:0209CB0000002A
+:0209CC00000029
+:0209CD00000028
+:0209CE00000027
+:0209CF00000026
+:0209D000000025
+:0209D100000024
+:0209D200000023
+:0209D300000022
+:0209D400000021
+:0209D500000020
+:0209D60000001F
+:0209D70000001E
+:0209D80000001D
+:0209D90000001C
+:0209DA0000001B
+:0209DB0000001A
+:0209DC00000019
+:0209DD00000018
+:0209DE00000017
+:0209DF00000016
+:0209E000000015
+:0209E100000014
+:0209E200000013
+:0209E300000012
+:0209E400000011
+:0209E500000010
+:0209E60000000F
+:0209E70000000E
+:0209E80000000D
+:0209E90000000C
+:0209EA0000000B
+:0209EB0000000A
+:0209EC00000009
+:0209ED00000008
+:0209EE00000007
+:0209EF00000006
+:0209F000000005
+:0209F100000004
+:0209F200000003
+:0209F300000002
+:0209F400000001
+:0209F500000000
+:0209F6000000FF
+:0209F7000000FE
+:0209F8000000FD
+:0209F9000000FC
+:0209FA000000FB
+:0209FB000000FA
+:0209FC000000F9
+:0209FD000000F8
+:0209FE000000F7
+:0209FF000000F6
+:020A00000000F4
+:020A01000000F3
+:020A02000000F2
+:020A03000000F1
+:020A04000000F0
+:020A05000000EF
+:020A06000000EE
+:020A07000000ED
+:020A08000000EC
+:020A09000000EB
+:020A0A000000EA
+:020A0B000000E9
+:020A0C000000E8
+:020A0D000000E7
+:020A0E000000E6
+:020A0F000000E5
+:020A10000000E4
+:020A11000000E3
+:020A12000000E2
+:020A13000000E1
+:020A14000000E0
+:020A15000000DF
+:020A16000000DE
+:020A17000000DD
+:020A18000000DC
+:020A19000000DB
+:020A1A000000DA
+:020A1B000000D9
+:020A1C000000D8
+:020A1D000000D7
+:020A1E000000D6
+:020A1F000000D5
+:020A20000000D4
+:020A21000000D3
+:020A22000000D2
+:020A23000000D1
+:020A24000000D0
+:020A25000000CF
+:020A26000000CE
+:020A27000000CD
+:020A28000000CC
+:020A29000000CB
+:020A2A000000CA
+:020A2B000000C9
+:020A2C000000C8
+:020A2D000000C7
+:020A2E000000C6
+:020A2F000000C5
+:020A30000000C4
+:020A31000000C3
+:020A32000000C2
+:020A33000000C1
+:020A34000000C0
+:020A35000000BF
+:020A36000000BE
+:020A37000000BD
+:020A38000000BC
+:020A39000000BB
+:020A3A000000BA
+:020A3B000000B9
+:020A3C000000B8
+:020A3D000000B7
+:020A3E000000B6
+:020A3F000000B5
+:020A40000000B4
+:020A41000000B3
+:020A42000000B2
+:020A43000000B1
+:020A44000000B0
+:020A45000000AF
+:020A46000000AE
+:020A47000000AD
+:020A48000000AC
+:020A49000000AB
+:020A4A000000AA
+:020A4B000000A9
+:020A4C000000A8
+:020A4D000000A7
+:020A4E000000A6
+:020A4F000000A5
+:020A50000000A4
+:020A51000000A3
+:020A52000000A2
+:020A53000000A1
+:020A54000000A0
+:020A550000009F
+:020A560000009E
+:020A570000009D
+:020A580000009C
+:020A590000009B
+:020A5A0000009A
+:020A5B00000099
+:020A5C00000098
+:020A5D00000097
+:020A5E00000096
+:020A5F00000095
+:020A6000000094
+:020A6100000093
+:020A6200000092
+:020A6300000091
+:020A6400000090
+:020A650000008F
+:020A660000008E
+:020A670000008D
+:020A680000008C
+:020A690000008B
+:020A6A0000008A
+:020A6B00000089
+:020A6C00000088
+:020A6D00000087
+:020A6E00000086
+:020A6F00000085
+:020A7000000084
+:020A7100000083
+:020A7200000082
+:020A7300000081
+:020A7400000080
+:020A750000007F
+:020A760000007E
+:020A770000007D
+:020A780000007C
+:020A790000007B
+:020A7A0000007A
+:020A7B00000079
+:020A7C00000078
+:020A7D00000077
+:020A7E00000076
+:020A7F00000075
+:020A8000000074
+:020A8100000073
+:020A8200000072
+:020A8300000071
+:020A8400000070
+:020A850000006F
+:020A860000006E
+:020A870000006D
+:020A880000006C
+:020A890000006B
+:020A8A0000006A
+:020A8B00000069
+:020A8C00000068
+:020A8D00000067
+:020A8E00000066
+:020A8F00000065
+:020A9000000064
+:020A9100000063
+:020A9200000062
+:020A9300000061
+:020A9400000060
+:020A950000005F
+:020A960000005E
+:020A970000005D
+:020A980000005C
+:020A990000005B
+:020A9A0000005A
+:020A9B00000059
+:020A9C00000058
+:020A9D00000057
+:020A9E00000056
+:020A9F00000055
+:020AA000000054
+:020AA100000053
+:020AA200000052
+:020AA300000051
+:020AA400000050
+:020AA50000004F
+:020AA60000004E
+:020AA70000004D
+:020AA80000004C
+:020AA90000004B
+:020AAA0000004A
+:020AAB00000049
+:020AAC00000048
+:020AAD00000047
+:020AAE00000046
+:020AAF00000045
+:020AB000000044
+:020AB100000043
+:020AB200000042
+:020AB300000041
+:020AB400000040
+:020AB50000003F
+:020AB60000003E
+:020AB70000003D
+:020AB80000003C
+:020AB90000003B
+:020ABA0000003A
+:020ABB00000039
+:020ABC00000038
+:020ABD00000037
+:020ABE00000036
+:020ABF00000035
+:020AC000000034
+:020AC100000033
+:020AC200000032
+:020AC300000031
+:020AC400000030
+:020AC50000002F
+:020AC60000002E
+:020AC70000002D
+:020AC80000002C
+:020AC90000002B
+:020ACA0000002A
+:020ACB00000029
+:020ACC00000028
+:020ACD00000027
+:020ACE00000026
+:020ACF00000025
+:020AD000000024
+:020AD100000023
+:020AD200000022
+:020AD300000021
+:020AD400000020
+:020AD50000001F
+:020AD60000001E
+:020AD70000001D
+:020AD80000001C
+:020AD90000001B
+:020ADA0000001A
+:020ADB00000019
+:020ADC00000018
+:020ADD00000017
+:020ADE00000016
+:020ADF00000015
+:020AE000000014
+:020AE100000013
+:020AE200000012
+:020AE300000011
+:020AE400000010
+:020AE50000000F
+:020AE60000000E
+:020AE70000000D
+:020AE80000000C
+:020AE90000000B
+:020AEA0000000A
+:020AEB00000009
+:020AEC00000008
+:020AED00000007
+:020AEE00000006
+:020AEF00000005
+:020AF000000004
+:020AF100000003
+:020AF200000002
+:020AF300000001
+:020AF400000000
+:020AF5000000FF
+:020AF6000000FE
+:020AF7000000FD
+:020AF8000000FC
+:020AF9000000FB
+:020AFA000000FA
+:020AFB000000F9
+:020AFC000000F8
+:020AFD000000F7
+:020AFE000000F6
+:020AFF000000F5
+:020B00000000F3
+:020B01000000F2
+:020B02000000F1
+:020B03000000F0
+:020B04000000EF
+:020B05000000EE
+:020B06000000ED
+:020B07000000EC
+:020B08000000EB
+:020B09000000EA
+:020B0A000000E9
+:020B0B000000E8
+:020B0C000000E7
+:020B0D000000E6
+:020B0E000000E5
+:020B0F000000E4
+:020B10000000E3
+:020B11000000E2
+:020B12000000E1
+:020B13000000E0
+:020B14000000DF
+:020B15000000DE
+:020B16000000DD
+:020B17000000DC
+:020B18000000DB
+:020B19000000DA
+:020B1A000000D9
+:020B1B000000D8
+:020B1C000000D7
+:020B1D000000D6
+:020B1E000000D5
+:020B1F000000D4
+:020B20000000D3
+:020B21000000D2
+:020B22000000D1
+:020B23000000D0
+:020B24000000CF
+:020B25000000CE
+:020B26000000CD
+:020B27000000CC
+:020B28000000CB
+:020B29000000CA
+:020B2A000000C9
+:020B2B000000C8
+:020B2C000000C7
+:020B2D000000C6
+:020B2E000000C5
+:020B2F000000C4
+:020B30000000C3
+:020B31000000C2
+:020B32000000C1
+:020B33000000C0
+:020B34000000BF
+:020B35000000BE
+:020B36000000BD
+:020B37000000BC
+:020B38000000BB
+:020B39000000BA
+:020B3A000000B9
+:020B3B000000B8
+:020B3C000000B7
+:020B3D000000B6
+:020B3E000000B5
+:020B3F000000B4
+:020B40000000B3
+:020B41000000B2
+:020B42000000B1
+:020B43000000B0
+:020B44000000AF
+:020B45000000AE
+:020B46000000AD
+:020B47000000AC
+:020B48000000AB
+:020B49000000AA
+:020B4A000000A9
+:020B4B000000A8
+:020B4C000000A7
+:020B4D000000A6
+:020B4E000000A5
+:020B4F000000A4
+:020B50000000A3
+:020B51000000A2
+:020B52000000A1
+:020B53000000A0
+:020B540000009F
+:020B550000009E
+:020B560000009D
+:020B570000009C
+:020B580000009B
+:020B590000009A
+:020B5A00000099
+:020B5B00000098
+:020B5C00000097
+:020B5D00000096
+:020B5E00000095
+:020B5F00000094
+:020B6000000093
+:020B6100000092
+:020B6200000091
+:020B6300000090
+:020B640000008F
+:020B650000008E
+:020B660000008D
+:020B670000008C
+:020B680000008B
+:020B690000008A
+:020B6A00000089
+:020B6B00000088
+:020B6C00000087
+:020B6D00000086
+:020B6E00000085
+:020B6F00000084
+:020B7000000083
+:020B7100000082
+:020B7200000081
+:020B7300000080
+:020B740000007F
+:020B750000007E
+:020B760000007D
+:020B770000007C
+:020B780000007B
+:020B790000007A
+:020B7A00000079
+:020B7B00000078
+:020B7C00000077
+:020B7D00000076
+:020B7E00000075
+:020B7F00000074
+:020B8000000073
+:020B8100000072
+:020B8200000071
+:020B8300000070
+:020B840000006F
+:020B850000006E
+:020B860000006D
+:020B870000006C
+:020B880000006B
+:020B890000006A
+:020B8A00000069
+:020B8B00000068
+:020B8C00000067
+:020B8D00000066
+:020B8E00000065
+:020B8F00000064
+:020B9000000063
+:020B9100000062
+:020B9200000061
+:020B9300000060
+:020B940000005F
+:020B950000005E
+:020B960000005D
+:020B970000005C
+:020B980000005B
+:020B990000005A
+:020B9A00000059
+:020B9B00000058
+:020B9C00000057
+:020B9D00000056
+:020B9E00000055
+:020B9F00000054
+:020BA000000053
+:020BA100000052
+:020BA200000051
+:020BA300000050
+:020BA40000004F
+:020BA50000004E
+:020BA60000004D
+:020BA70000004C
+:020BA80000004B
+:020BA90000004A
+:020BAA00000049
+:020BAB00000048
+:020BAC00000047
+:020BAD00000046
+:020BAE00000045
+:020BAF00000044
+:020BB000000043
+:020BB100000042
+:020BB200000041
+:020BB300000040
+:020BB40000003F
+:020BB50000003E
+:020BB60000003D
+:020BB70000003C
+:020BB80000003B
+:020BB90000003A
+:020BBA00000039
+:020BBB00000038
+:020BBC00000037
+:020BBD00000036
+:020BBE00000035
+:020BBF00000034
+:020BC000000033
+:020BC100000032
+:020BC200000031
+:020BC300000030
+:020BC40000002F
+:020BC50000002E
+:020BC60000002D
+:020BC70000002C
+:020BC80000002B
+:020BC90000002A
+:020BCA00000029
+:020BCB00000028
+:020BCC00000027
+:020BCD00000026
+:020BCE00000025
+:020BCF00000024
+:020BD000000023
+:020BD100000022
+:020BD200000021
+:020BD300000020
+:020BD40000001F
+:020BD50000001E
+:020BD60000001D
+:020BD70000001C
+:020BD80000001B
+:020BD90000001A
+:020BDA00000019
+:020BDB00000018
+:020BDC00000017
+:020BDD00000016
+:020BDE00000015
+:020BDF00000014
+:020BE000000013
+:020BE100000012
+:020BE200000011
+:020BE300000010
+:020BE40000000F
+:020BE50000000E
+:020BE60000000D
+:020BE70000000C
+:020BE80000000B
+:020BE90000000A
+:020BEA00000009
+:020BEB00000008
+:020BEC00000007
+:020BED00000006
+:020BEE00000005
+:020BEF00000004
+:020BF000000003
+:020BF100000002
+:020BF200000001
+:020BF300000000
+:020BF4000000FF
+:020BF5000000FE
+:020BF6000000FD
+:020BF7000000FC
+:020BF8000000FB
+:020BF9000000FA
+:020BFA000000F9
+:020BFB000000F8
+:020BFC000000F7
+:020BFD000000F6
+:020BFE000000F5
+:020BFF000000F4
+:020C00000000F2
+:020C01000000F1
+:020C02000000F0
+:020C03000000EF
+:020C04000000EE
+:020C05000000ED
+:020C06000000EC
+:020C07000000EB
+:020C08000000EA
+:020C09000000E9
+:020C0A000000E8
+:020C0B000000E7
+:020C0C000000E6
+:020C0D000000E5
+:020C0E000000E4
+:020C0F000000E3
+:020C10000000E2
+:020C11000000E1
+:020C12000000E0
+:020C13000000DF
+:020C14000000DE
+:020C15000000DD
+:020C16000000DC
+:020C17000000DB
+:020C18000000DA
+:020C19000000D9
+:020C1A000000D8
+:020C1B000000D7
+:020C1C000000D6
+:020C1D000000D5
+:020C1E000000D4
+:020C1F000000D3
+:020C20000000D2
+:020C21000000D1
+:020C22000000D0
+:020C23000000CF
+:020C24000000CE
+:020C25000000CD
+:020C26000000CC
+:020C27000000CB
+:020C28000000CA
+:020C29000000C9
+:020C2A000000C8
+:020C2B000000C7
+:020C2C000000C6
+:020C2D000000C5
+:020C2E000000C4
+:020C2F000000C3
+:020C30000000C2
+:020C31000000C1
+:020C32000000C0
+:020C33000000BF
+:020C34000000BE
+:020C35000000BD
+:020C36000000BC
+:020C37000000BB
+:020C38000000BA
+:020C39000000B9
+:020C3A000000B8
+:020C3B000000B7
+:020C3C000000B6
+:020C3D000000B5
+:020C3E000000B4
+:020C3F000000B3
+:020C40000000B2
+:020C41000000B1
+:020C42000000B0
+:020C43000000AF
+:020C44000000AE
+:020C45000000AD
+:020C46000000AC
+:020C47000000AB
+:020C48000000AA
+:020C49000000A9
+:020C4A000000A8
+:020C4B000000A7
+:020C4C000000A6
+:020C4D000000A5
+:020C4E000000A4
+:020C4F000000A3
+:020C50000000A2
+:020C51000000A1
+:020C52000000A0
+:020C530000009F
+:020C540000009E
+:020C550000009D
+:020C560000009C
+:020C570000009B
+:020C580000009A
+:020C5900000099
+:020C5A00000098
+:020C5B00000097
+:020C5C00000096
+:020C5D00000095
+:020C5E00000094
+:020C5F00000093
+:020C6000000092
+:020C6100000091
+:020C6200000090
+:020C630000008F
+:020C640000008E
+:020C650000008D
+:020C660000008C
+:020C670000008B
+:020C680000008A
+:020C6900000089
+:020C6A00000088
+:020C6B00000087
+:020C6C00000086
+:020C6D00000085
+:020C6E00000084
+:020C6F00000083
+:020C7000000082
+:020C7100000081
+:020C7200000080
+:020C730000007F
+:020C740000007E
+:020C750000007D
+:020C760000007C
+:020C770000007B
+:020C780000007A
+:020C7900000079
+:020C7A00000078
+:020C7B00000077
+:020C7C00000076
+:020C7D00000075
+:020C7E00000074
+:020C7F00000073
+:020C8000000072
+:020C8100000071
+:020C8200000070
+:020C830000006F
+:020C840000006E
+:020C850000006D
+:020C860000006C
+:020C870000006B
+:020C880000006A
+:020C8900000069
+:020C8A00000068
+:020C8B00000067
+:020C8C00000066
+:020C8D00000065
+:020C8E00000064
+:020C8F00000063
+:020C9000000062
+:020C9100000061
+:020C9200000060
+:020C930000005F
+:020C940000005E
+:020C950000005D
+:020C960000005C
+:020C970000005B
+:020C980000005A
+:020C9900000059
+:020C9A00000058
+:020C9B00000057
+:020C9C00000056
+:020C9D00000055
+:020C9E00000054
+:020C9F00000053
+:020CA000000052
+:020CA100000051
+:020CA200000050
+:020CA30000004F
+:020CA40000004E
+:020CA50000004D
+:020CA60000004C
+:020CA70000004B
+:020CA80000004A
+:020CA900000049
+:020CAA00000048
+:020CAB00000047
+:020CAC00000046
+:020CAD00000045
+:020CAE00000044
+:020CAF00000043
+:020CB000000042
+:020CB100000041
+:020CB200000040
+:020CB30000003F
+:020CB40000003E
+:020CB50000003D
+:020CB60000003C
+:020CB70000003B
+:020CB80000003A
+:020CB900000039
+:020CBA00000038
+:020CBB00000037
+:020CBC00000036
+:020CBD00000035
+:020CBE00000034
+:020CBF00000033
+:020CC000000032
+:020CC100000031
+:020CC200000030
+:020CC30000002F
+:020CC40000002E
+:020CC50000002D
+:020CC60000002C
+:020CC70000002B
+:020CC80000002A
+:020CC900000029
+:020CCA00000028
+:020CCB00000027
+:020CCC00000026
+:020CCD00000025
+:020CCE00000024
+:020CCF00000023
+:020CD000000022
+:020CD100000021
+:020CD200000020
+:020CD30000001F
+:020CD40000001E
+:020CD50000001D
+:020CD60000001C
+:020CD70000001B
+:020CD80000001A
+:020CD900000019
+:020CDA00000018
+:020CDB00000017
+:020CDC00000016
+:020CDD00000015
+:020CDE00000014
+:020CDF00000013
+:020CE000000012
+:020CE100000011
+:020CE200000010
+:020CE30000000F
+:020CE40000000E
+:020CE50000000D
+:020CE60000000C
+:020CE70000000B
+:020CE80000000A
+:020CE900000009
+:020CEA00000008
+:020CEB00000007
+:020CEC00000006
+:020CED00000005
+:020CEE00000004
+:020CEF00000003
+:020CF000000002
+:020CF100000001
+:020CF200000000
+:020CF3000000FF
+:020CF4000000FE
+:020CF5000000FD
+:020CF6000000FC
+:020CF7000000FB
+:020CF8000000FA
+:020CF9000000F9
+:020CFA000000F8
+:020CFB000000F7
+:020CFC000000F6
+:020CFD000000F5
+:020CFE000000F4
+:020CFF000000F3
+:020D00000000F1
+:020D01000000F0
+:020D02000000EF
+:020D03000000EE
+:020D04000000ED
+:020D05000000EC
+:020D06000000EB
+:020D07000000EA
+:020D08000000E9
+:020D09000000E8
+:020D0A000000E7
+:020D0B000000E6
+:020D0C000000E5
+:020D0D000000E4
+:020D0E000000E3
+:020D0F000000E2
+:020D10000000E1
+:020D11000000E0
+:020D12000000DF
+:020D13000000DE
+:020D14000000DD
+:020D15000000DC
+:020D16000000DB
+:020D17000000DA
+:020D18000000D9
+:020D19000000D8
+:020D1A000000D7
+:020D1B000000D6
+:020D1C000000D5
+:020D1D000000D4
+:020D1E000000D3
+:020D1F000000D2
+:020D20000000D1
+:020D21000000D0
+:020D22000000CF
+:020D23000000CE
+:020D24000000CD
+:020D25000000CC
+:020D26000000CB
+:020D27000000CA
+:020D28000000C9
+:020D29000000C8
+:020D2A000000C7
+:020D2B000000C6
+:020D2C000000C5
+:020D2D000000C4
+:020D2E000000C3
+:020D2F000000C2
+:020D30000000C1
+:020D31000000C0
+:020D32000000BF
+:020D33000000BE
+:020D34000000BD
+:020D35000000BC
+:020D36000000BB
+:020D37000000BA
+:020D38000000B9
+:020D39000000B8
+:020D3A000000B7
+:020D3B000000B6
+:020D3C000000B5
+:020D3D000000B4
+:020D3E000000B3
+:020D3F000000B2
+:020D40000000B1
+:020D41000000B0
+:020D42000000AF
+:020D43000000AE
+:020D44000000AD
+:020D45000000AC
+:020D46000000AB
+:020D47000000AA
+:020D48000000A9
+:020D49000000A8
+:020D4A000000A7
+:020D4B000000A6
+:020D4C000000A5
+:020D4D000000A4
+:020D4E000000A3
+:020D4F000000A2
+:020D50000000A1
+:020D51000000A0
+:020D520000009F
+:020D530000009E
+:020D540000009D
+:020D550000009C
+:020D560000009B
+:020D570000009A
+:020D5800000099
+:020D5900000098
+:020D5A00000097
+:020D5B00000096
+:020D5C00000095
+:020D5D00000094
+:020D5E00000093
+:020D5F00000092
+:020D6000000091
+:020D6100000090
+:020D620000008F
+:020D630000008E
+:020D640000008D
+:020D650000008C
+:020D660000008B
+:020D670000008A
+:020D6800000089
+:020D6900000088
+:020D6A00000087
+:020D6B00000086
+:020D6C00000085
+:020D6D00000084
+:020D6E00000083
+:020D6F00000082
+:020D7000000081
+:020D7100000080
+:020D720000007F
+:020D730000007E
+:020D740000007D
+:020D750000007C
+:020D760000007B
+:020D770000007A
+:020D7800000079
+:020D7900000078
+:020D7A00000077
+:020D7B00000076
+:020D7C00000075
+:020D7D00000074
+:020D7E00000073
+:020D7F00000072
+:020D8000000071
+:020D8100000070
+:020D820000006F
+:020D830000006E
+:020D840000006D
+:020D850000006C
+:020D860000006B
+:020D870000006A
+:020D8800000069
+:020D8900000068
+:020D8A00000067
+:020D8B00000066
+:020D8C00000065
+:020D8D00000064
+:020D8E00000063
+:020D8F00000062
+:020D9000000061
+:020D9100000060
+:020D920000005F
+:020D930000005E
+:020D940000005D
+:020D950000005C
+:020D960000005B
+:020D970000005A
+:020D9800000059
+:020D9900000058
+:020D9A00000057
+:020D9B00000056
+:020D9C00000055
+:020D9D00000054
+:020D9E00000053
+:020D9F00000052
+:020DA000000051
+:020DA100000050
+:020DA20000004F
+:020DA30000004E
+:020DA40000004D
+:020DA50000004C
+:020DA60000004B
+:020DA70000004A
+:020DA800000049
+:020DA900000048
+:020DAA00000047
+:020DAB00000046
+:020DAC00000045
+:020DAD00000044
+:020DAE00000043
+:020DAF00000042
+:020DB000000041
+:020DB100000040
+:020DB20000003F
+:020DB30000003E
+:020DB40000003D
+:020DB50000003C
+:020DB60000003B
+:020DB70000003A
+:020DB800000039
+:020DB900000038
+:020DBA00000037
+:020DBB00000036
+:020DBC00000035
+:020DBD00000034
+:020DBE00000033
+:020DBF00000032
+:020DC000000031
+:020DC100000030
+:020DC20000002F
+:020DC30000002E
+:020DC40000002D
+:020DC50000002C
+:020DC60000002B
+:020DC70000002A
+:020DC800000029
+:020DC900000028
+:020DCA00000027
+:020DCB00000026
+:020DCC00000025
+:020DCD00000024
+:020DCE00000023
+:020DCF00000022
+:020DD000000021
+:020DD100000020
+:020DD20000001F
+:020DD30000001E
+:020DD40000001D
+:020DD50000001C
+:020DD60000001B
+:020DD70000001A
+:020DD800000019
+:020DD900000018
+:020DDA00000017
+:020DDB00000016
+:020DDC00000015
+:020DDD00000014
+:020DDE00000013
+:020DDF00000012
+:020DE000000011
+:020DE100000010
+:020DE20000000F
+:020DE30000000E
+:020DE40000000D
+:020DE50000000C
+:020DE60000000B
+:020DE70000000A
+:020DE800000009
+:020DE900000008
+:020DEA00000007
+:020DEB00000006
+:020DEC00000005
+:020DED00000004
+:020DEE00000003
+:020DEF00000002
+:020DF000000001
+:020DF100000000
+:020DF2000000FF
+:020DF3000000FE
+:020DF4000000FD
+:020DF5000000FC
+:020DF6000000FB
+:020DF7000000FA
+:020DF8000000F9
+:020DF9000000F8
+:020DFA000000F7
+:020DFB000000F6
+:020DFC000000F5
+:020DFD000000F4
+:020DFE000000F3
+:020DFF000000F2
+:020E00000000F0
+:020E01000000EF
+:020E02000000EE
+:020E03000000ED
+:020E04000000EC
+:020E05000000EB
+:020E06000000EA
+:020E07000000E9
+:020E08000000E8
+:020E09000000E7
+:020E0A000000E6
+:020E0B000000E5
+:020E0C000000E4
+:020E0D000000E3
+:020E0E000000E2
+:020E0F000000E1
+:020E10000000E0
+:020E11000000DF
+:020E12000000DE
+:020E13000000DD
+:020E14000000DC
+:020E15000000DB
+:020E16000000DA
+:020E17000000D9
+:020E18000000D8
+:020E19000000D7
+:020E1A000000D6
+:020E1B000000D5
+:020E1C000000D4
+:020E1D000000D3
+:020E1E000000D2
+:020E1F000000D1
+:020E20000000D0
+:020E21000000CF
+:020E22000000CE
+:020E23000000CD
+:020E24000000CC
+:020E25000000CB
+:020E26000000CA
+:020E27000000C9
+:020E28000000C8
+:020E29000000C7
+:020E2A000000C6
+:020E2B000000C5
+:020E2C000000C4
+:020E2D000000C3
+:020E2E000000C2
+:020E2F000000C1
+:020E30000000C0
+:020E31000000BF
+:020E32000000BE
+:020E33000000BD
+:020E34000000BC
+:020E35000000BB
+:020E36000000BA
+:020E37000000B9
+:020E38000000B8
+:020E39000000B7
+:020E3A000000B6
+:020E3B000000B5
+:020E3C000000B4
+:020E3D000000B3
+:020E3E000000B2
+:020E3F000000B1
+:020E40000000B0
+:020E41000000AF
+:020E42000000AE
+:020E43000000AD
+:020E44000000AC
+:020E45000000AB
+:020E46000000AA
+:020E47000000A9
+:020E48000000A8
+:020E49000000A7
+:020E4A000000A6
+:020E4B000000A5
+:020E4C000000A4
+:020E4D000000A3
+:020E4E000000A2
+:020E4F000000A1
+:020E50000000A0
+:020E510000009F
+:020E520000009E
+:020E530000009D
+:020E540000009C
+:020E550000009B
+:020E560000009A
+:020E5700000099
+:020E5800000098
+:020E5900000097
+:020E5A00000096
+:020E5B00000095
+:020E5C00000094
+:020E5D00000093
+:020E5E00000092
+:020E5F00000091
+:020E6000000090
+:020E610000008F
+:020E620000008E
+:020E630000008D
+:020E640000008C
+:020E650000008B
+:020E660000008A
+:020E6700000089
+:020E6800000088
+:020E6900000087
+:020E6A00000086
+:020E6B00000085
+:020E6C00000084
+:020E6D00000083
+:020E6E00000082
+:020E6F00000081
+:020E7000000080
+:020E710000007F
+:020E720000007E
+:020E730000007D
+:020E740000007C
+:020E750000007B
+:020E760000007A
+:020E7700000079
+:020E7800000078
+:020E7900000077
+:020E7A00000076
+:020E7B00000075
+:020E7C00000074
+:020E7D00000073
+:020E7E00000072
+:020E7F00000071
+:020E8000000070
+:020E810000006F
+:020E820000006E
+:020E830000006D
+:020E840000006C
+:020E850000006B
+:020E860000006A
+:020E8700000069
+:020E8800000068
+:020E8900000067
+:020E8A00000066
+:020E8B00000065
+:020E8C00000064
+:020E8D00000063
+:020E8E00000062
+:020E8F00000061
+:020E9000000060
+:020E910000005F
+:020E920000005E
+:020E930000005D
+:020E940000005C
+:020E950000005B
+:020E960000005A
+:020E9700000059
+:020E9800000058
+:020E9900000057
+:020E9A00000056
+:020E9B00000055
+:020E9C00000054
+:020E9D00000053
+:020E9E00000052
+:020E9F00000051
+:020EA000000050
+:020EA10000004F
+:020EA20000004E
+:020EA30000004D
+:020EA40000004C
+:020EA50000004B
+:020EA60000004A
+:020EA700000049
+:020EA800000048
+:020EA900000047
+:020EAA00000046
+:020EAB00000045
+:020EAC00000044
+:020EAD00000043
+:020EAE00000042
+:020EAF00000041
+:020EB000000040
+:020EB10000003F
+:020EB20000003E
+:020EB30000003D
+:020EB40000003C
+:020EB50000003B
+:020EB60000003A
+:020EB700000039
+:020EB800000038
+:020EB900000037
+:020EBA00000036
+:020EBB00000035
+:020EBC00000034
+:020EBD00000033
+:020EBE00000032
+:020EBF00000031
+:020EC000000030
+:020EC10000002F
+:020EC20000002E
+:020EC30000002D
+:020EC40000002C
+:020EC50000002B
+:020EC60000002A
+:020EC700000029
+:020EC800000028
+:020EC900000027
+:020ECA00000026
+:020ECB00000025
+:020ECC00000024
+:020ECD00000023
+:020ECE00000022
+:020ECF00000021
+:020ED000000020
+:020ED10000001F
+:020ED20000001E
+:020ED30000001D
+:020ED40000001C
+:020ED50000001B
+:020ED60000001A
+:020ED700000019
+:020ED800000018
+:020ED900000017
+:020EDA00000016
+:020EDB00000015
+:020EDC00000014
+:020EDD00000013
+:020EDE00000012
+:020EDF00000011
+:020EE000000010
+:020EE10000000F
+:020EE20000000E
+:020EE30000000D
+:020EE40000000C
+:020EE50000000B
+:020EE60000000A
+:020EE700000009
+:020EE800000008
+:020EE900000007
+:020EEA00000006
+:020EEB00000005
+:020EEC00000004
+:020EED00000003
+:020EEE00000002
+:020EEF00000001
+:020EF000000000
+:020EF1000000FF
+:020EF2000000FE
+:020EF3000000FD
+:020EF4000000FC
+:020EF5000000FB
+:020EF6000000FA
+:020EF7000000F9
+:020EF8000000F8
+:020EF9000000F7
+:020EFA000000F6
+:020EFB000000F5
+:020EFC000000F4
+:020EFD000000F3
+:020EFE000000F2
+:020EFF000000F1
+:020F00000000EF
+:020F01000000EE
+:020F02000000ED
+:020F03000000EC
+:020F04000000EB
+:020F05000000EA
+:020F06000000E9
+:020F07000000E8
+:020F08000000E7
+:020F09000000E6
+:020F0A000000E5
+:020F0B000000E4
+:020F0C000000E3
+:020F0D000000E2
+:020F0E000000E1
+:020F0F000000E0
+:020F10000000DF
+:020F11000000DE
+:020F12000000DD
+:020F13000000DC
+:020F14000000DB
+:020F15000000DA
+:020F16000000D9
+:020F17000000D8
+:020F18000000D7
+:020F19000000D6
+:020F1A000000D5
+:020F1B000000D4
+:020F1C000000D3
+:020F1D000000D2
+:020F1E000000D1
+:020F1F000000D0
+:020F20000000CF
+:020F21000000CE
+:020F22000000CD
+:020F23000000CC
+:020F24000000CB
+:020F25000000CA
+:020F26000000C9
+:020F27000000C8
+:020F28000000C7
+:020F29000000C6
+:020F2A000000C5
+:020F2B000000C4
+:020F2C000000C3
+:020F2D000000C2
+:020F2E000000C1
+:020F2F000000C0
+:020F30000000BF
+:020F31000000BE
+:020F32000000BD
+:020F33000000BC
+:020F34000000BB
+:020F35000000BA
+:020F36000000B9
+:020F37000000B8
+:020F38000000B7
+:020F39000000B6
+:020F3A000000B5
+:020F3B000000B4
+:020F3C000000B3
+:020F3D000000B2
+:020F3E000000B1
+:020F3F000000B0
+:020F40000000AF
+:020F41000000AE
+:020F42000000AD
+:020F43000000AC
+:020F44000000AB
+:020F45000000AA
+:020F46000000A9
+:020F47000000A8
+:020F48000000A7
+:020F49000000A6
+:020F4A000000A5
+:020F4B000000A4
+:020F4C000000A3
+:020F4D000000A2
+:020F4E000000A1
+:020F4F000000A0
+:020F500000009F
+:020F510000009E
+:020F520000009D
+:020F530000009C
+:020F540000009B
+:020F550000009A
+:020F5600000099
+:020F5700000098
+:020F5800000097
+:020F5900000096
+:020F5A00000095
+:020F5B00000094
+:020F5C00000093
+:020F5D00000092
+:020F5E00000091
+:020F5F00000090
+:020F600000008F
+:020F610000008E
+:020F620000008D
+:020F630000008C
+:020F640000008B
+:020F650000008A
+:020F6600000089
+:020F6700000088
+:020F6800000087
+:020F6900000086
+:020F6A00000085
+:020F6B00000084
+:020F6C00000083
+:020F6D00000082
+:020F6E00000081
+:020F6F00000080
+:020F700000007F
+:020F710000007E
+:020F720000007D
+:020F730000007C
+:020F740000007B
+:020F750000007A
+:020F7600000079
+:020F7700000078
+:020F7800000077
+:020F7900000076
+:020F7A00000075
+:020F7B00000074
+:020F7C00000073
+:020F7D00000072
+:020F7E00000071
+:020F7F00000070
+:020F800000006F
+:020F810000006E
+:020F820000006D
+:020F830000006C
+:020F840000006B
+:020F850000006A
+:020F8600000069
+:020F8700000068
+:020F8800000067
+:020F8900000066
+:020F8A00000065
+:020F8B00000064
+:020F8C00000063
+:020F8D00000062
+:020F8E00000061
+:020F8F00000060
+:020F900000005F
+:020F910000005E
+:020F920000005D
+:020F930000005C
+:020F940000005B
+:020F950000005A
+:020F9600000059
+:020F9700000058
+:020F9800000057
+:020F9900000056
+:020F9A00000055
+:020F9B00000054
+:020F9C00000053
+:020F9D00000052
+:020F9E00000051
+:020F9F00000050
+:020FA00000004F
+:020FA10000004E
+:020FA20000004D
+:020FA30000004C
+:020FA40000004B
+:020FA50000004A
+:020FA600000049
+:020FA700000048
+:020FA800000047
+:020FA900000046
+:020FAA00000045
+:020FAB00000044
+:020FAC00000043
+:020FAD00000042
+:020FAE00000041
+:020FAF00000040
+:020FB00000003F
+:020FB10000003E
+:020FB20000003D
+:020FB30000003C
+:020FB40000003B
+:020FB50000003A
+:020FB600000039
+:020FB700000038
+:020FB800000037
+:020FB900000036
+:020FBA00000035
+:020FBB00000034
+:020FBC00000033
+:020FBD00000032
+:020FBE00000031
+:020FBF00000030
+:020FC00000002F
+:020FC10000002E
+:020FC20000002D
+:020FC30000002C
+:020FC40000002B
+:020FC50000002A
+:020FC600000029
+:020FC700000028
+:020FC800000027
+:020FC900000026
+:020FCA00000025
+:020FCB00000024
+:020FCC00000023
+:020FCD00000022
+:020FCE00000021
+:020FCF00000020
+:020FD00000001F
+:020FD10000001E
+:020FD20000001D
+:020FD30000001C
+:020FD40000001B
+:020FD50000001A
+:020FD600000019
+:020FD700000018
+:020FD800000017
+:020FD900000016
+:020FDA00000015
+:020FDB00000014
+:020FDC00000013
+:020FDD00000012
+:020FDE00000011
+:020FDF00000010
+:020FE00000000F
+:020FE10000000E
+:020FE20000000D
+:020FE30000000C
+:020FE40000000B
+:020FE50000000A
+:020FE600000009
+:020FE700000008
+:020FE800000007
+:020FE900000006
+:020FEA00000005
+:020FEB00000004
+:020FEC00000003
+:020FED00000002
+:020FEE00000001
+:020FEF00000000
+:020FF0000000FF
+:020FF1000000FE
+:020FF2000000FD
+:020FF3000000FC
+:020FF4000000FB
+:020FF5000000FA
+:020FF6000000F9
+:020FF7000000F8
+:020FF8000000F7
+:020FF9000000F6
+:020FFA000000F5
+:020FFB000000F4
+:020FFC000000F3
+:020FFD000000F2
+:020FFE000000F1
+:020FFF000000F0
+:021000000000EE
+:021001000000ED
+:021002000000EC
+:021003000000EB
+:021004000000EA
+:021005000000E9
+:021006000000E8
+:021007000000E7
+:021008000000E6
+:021009000000E5
+:02100A000000E4
+:02100B000000E3
+:02100C000000E2
+:02100D000000E1
+:02100E000000E0
+:02100F000000DF
+:021010000000DE
+:021011000000DD
+:021012000000DC
+:021013000000DB
+:021014000000DA
+:021015000000D9
+:021016000000D8
+:021017000000D7
+:021018000000D6
+:021019000000D5
+:02101A000000D4
+:02101B000000D3
+:02101C000000D2
+:02101D000000D1
+:02101E000000D0
+:02101F000000CF
+:021020000000CE
+:021021000000CD
+:021022000000CC
+:021023000000CB
+:021024000000CA
+:021025000000C9
+:021026000000C8
+:021027000000C7
+:021028000000C6
+:021029000000C5
+:02102A000000C4
+:02102B000000C3
+:02102C000000C2
+:02102D000000C1
+:02102E000000C0
+:02102F000000BF
+:021030000000BE
+:021031000000BD
+:021032000000BC
+:021033000000BB
+:021034000000BA
+:021035000000B9
+:021036000000B8
+:021037000000B7
+:021038000000B6
+:021039000000B5
+:02103A000000B4
+:02103B000000B3
+:02103C000000B2
+:02103D000000B1
+:02103E000000B0
+:02103F000000AF
+:021040000000AE
+:021041000000AD
+:021042000000AC
+:021043000000AB
+:021044000000AA
+:021045000000A9
+:021046000000A8
+:021047000000A7
+:021048000000A6
+:021049000000A5
+:02104A000000A4
+:02104B000000A3
+:02104C000000A2
+:02104D000000A1
+:02104E000000A0
+:02104F0000009F
+:0210500000009E
+:0210510000009D
+:0210520000009C
+:0210530000009B
+:0210540000009A
+:02105500000099
+:02105600000098
+:02105700000097
+:02105800000096
+:02105900000095
+:02105A00000094
+:02105B00000093
+:02105C00000092
+:02105D00000091
+:02105E00000090
+:02105F0000008F
+:0210600000008E
+:0210610000008D
+:0210620000008C
+:0210630000008B
+:0210640000008A
+:02106500000089
+:02106600000088
+:02106700000087
+:02106800000086
+:02106900000085
+:02106A00000084
+:02106B00000083
+:02106C00000082
+:02106D00000081
+:02106E00000080
+:02106F0000007F
+:0210700000007E
+:0210710000007D
+:0210720000007C
+:0210730000007B
+:0210740000007A
+:02107500000079
+:02107600000078
+:02107700000077
+:02107800000076
+:02107900000075
+:02107A00000074
+:02107B00000073
+:02107C00000072
+:02107D00000071
+:02107E00000070
+:02107F0000006F
+:0210800000006E
+:0210810000006D
+:0210820000006C
+:0210830000006B
+:0210840000006A
+:02108500000069
+:02108600000068
+:02108700000067
+:02108800000066
+:02108900000065
+:02108A00000064
+:02108B00000063
+:02108C00000062
+:02108D00000061
+:02108E00000060
+:02108F0000005F
+:0210900000005E
+:0210910000005D
+:0210920000005C
+:0210930000005B
+:0210940000005A
+:02109500000059
+:02109600000058
+:02109700000057
+:02109800000056
+:02109900000055
+:02109A00000054
+:02109B00000053
+:02109C00000052
+:02109D00000051
+:02109E00000050
+:02109F0000004F
+:0210A00000004E
+:0210A10000004D
+:0210A20000004C
+:0210A30000004B
+:0210A40000004A
+:0210A500000049
+:0210A600000048
+:0210A700000047
+:0210A800000046
+:0210A900000045
+:0210AA00000044
+:0210AB00000043
+:0210AC00000042
+:0210AD00000041
+:0210AE00000040
+:0210AF0000003F
+:0210B00000003E
+:0210B10000003D
+:0210B20000003C
+:0210B30000003B
+:0210B40000003A
+:0210B500000039
+:0210B600000038
+:0210B700000037
+:0210B800000036
+:0210B900000035
+:0210BA00000034
+:0210BB00000033
+:0210BC00000032
+:0210BD00000031
+:0210BE00000030
+:0210BF0000002F
+:0210C00000002E
+:0210C10000002D
+:0210C20000002C
+:0210C30000002B
+:0210C40000002A
+:0210C500000029
+:0210C600000028
+:0210C700000027
+:0210C800000026
+:0210C900000025
+:0210CA00000024
+:0210CB00000023
+:0210CC00000022
+:0210CD00000021
+:0210CE00000020
+:0210CF0000001F
+:0210D00000001E
+:0210D10000001D
+:0210D20000001C
+:0210D30000001B
+:0210D40000001A
+:0210D500000019
+:0210D600000018
+:0210D700000017
+:0210D800000016
+:0210D900000015
+:0210DA00000014
+:0210DB00000013
+:0210DC00000012
+:0210DD00000011
+:0210DE00000010
+:0210DF0000000F
+:0210E00000000E
+:0210E10000000D
+:0210E20000000C
+:0210E30000000B
+:0210E40000000A
+:0210E500000009
+:0210E600000008
+:0210E700000007
+:0210E800000006
+:0210E900000005
+:0210EA00000004
+:0210EB00000003
+:0210EC00000002
+:0210ED00000001
+:0210EE00000000
+:0210EF000000FF
+:0210F0000000FE
+:0210F1000000FD
+:0210F2000000FC
+:0210F3000000FB
+:0210F4000000FA
+:0210F5000000F9
+:0210F6000000F8
+:0210F7000000F7
+:0210F8000000F6
+:0210F9000000F5
+:0210FA000000F4
+:0210FB000000F3
+:0210FC000000F2
+:0210FD000000F1
+:0210FE000000F0
+:0210FF000000EF
+:021100000000ED
+:021101000000EC
+:021102000000EB
+:021103000000EA
+:021104000000E9
+:021105000000E8
+:021106000000E7
+:021107000000E6
+:021108000000E5
+:021109000000E4
+:02110A000000E3
+:02110B000000E2
+:02110C000000E1
+:02110D000000E0
+:02110E000000DF
+:02110F000000DE
+:021110000000DD
+:021111000000DC
+:021112000000DB
+:021113000000DA
+:021114000000D9
+:021115000000D8
+:021116000000D7
+:021117000000D6
+:021118000000D5
+:021119000000D4
+:02111A000000D3
+:02111B000000D2
+:02111C000000D1
+:02111D000000D0
+:02111E000000CF
+:02111F000000CE
+:021120000000CD
+:021121000000CC
+:021122000000CB
+:021123000000CA
+:021124000000C9
+:021125000000C8
+:021126000000C7
+:021127000000C6
+:021128000000C5
+:021129000000C4
+:02112A000000C3
+:02112B000000C2
+:02112C000000C1
+:02112D000000C0
+:02112E000000BF
+:02112F000000BE
+:021130000000BD
+:021131000000BC
+:021132000000BB
+:021133000000BA
+:021134000000B9
+:021135000000B8
+:021136000000B7
+:021137000000B6
+:021138000000B5
+:021139000000B4
+:02113A000000B3
+:02113B000000B2
+:02113C000000B1
+:02113D000000B0
+:02113E000000AF
+:02113F000000AE
+:021140000000AD
+:021141000000AC
+:021142000000AB
+:021143000000AA
+:021144000000A9
+:021145000000A8
+:021146000000A7
+:021147000000A6
+:021148000000A5
+:021149000000A4
+:02114A000000A3
+:02114B000000A2
+:02114C000000A1
+:02114D000000A0
+:02114E0000009F
+:02114F0000009E
+:0211500000009D
+:0211510000009C
+:0211520000009B
+:0211530000009A
+:02115400000099
+:02115500000098
+:02115600000097
+:02115700000096
+:02115800000095
+:02115900000094
+:02115A00000093
+:02115B00000092
+:02115C00000091
+:02115D00000090
+:02115E0000008F
+:02115F0000008E
+:0211600000008D
+:0211610000008C
+:0211620000008B
+:0211630000008A
+:02116400000089
+:02116500000088
+:02116600000087
+:02116700000086
+:02116800000085
+:02116900000084
+:02116A00000083
+:02116B00000082
+:02116C00000081
+:02116D00000080
+:02116E0000007F
+:02116F0000007E
+:0211700000007D
+:0211710000007C
+:0211720000007B
+:0211730000007A
+:02117400000079
+:02117500000078
+:02117600000077
+:02117700000076
+:02117800000075
+:02117900000074
+:02117A00000073
+:02117B00000072
+:02117C00000071
+:02117D00000070
+:02117E0000006F
+:02117F0000006E
+:0211800000006D
+:0211810000006C
+:0211820000006B
+:0211830000006A
+:02118400000069
+:02118500000068
+:02118600000067
+:02118700000066
+:02118800000065
+:02118900000064
+:02118A00000063
+:02118B00000062
+:02118C00000061
+:02118D00000060
+:02118E0000005F
+:02118F0000005E
+:0211900000005D
+:0211910000005C
+:0211920000005B
+:0211930000005A
+:02119400000059
+:02119500000058
+:02119600000057
+:02119700000056
+:02119800000055
+:02119900000054
+:02119A00000053
+:02119B00000052
+:02119C00000051
+:02119D00000050
+:02119E0000004F
+:02119F0000004E
+:0211A00000004D
+:0211A10000004C
+:0211A20000004B
+:0211A30000004A
+:0211A400000049
+:0211A500000048
+:0211A600000047
+:0211A700000046
+:0211A800000045
+:0211A900000044
+:0211AA00000043
+:0211AB00000042
+:0211AC00000041
+:0211AD00000040
+:0211AE0000003F
+:0211AF0000003E
+:0211B00000003D
+:0211B10000003C
+:0211B20000003B
+:0211B30000003A
+:0211B400000039
+:0211B500000038
+:0211B600000037
+:0211B700000036
+:0211B800000035
+:0211B900000034
+:0211BA00000033
+:0211BB00000032
+:0211BC00000031
+:0211BD00000030
+:0211BE0000002F
+:0211BF0000002E
+:0211C00000002D
+:0211C10000002C
+:0211C20000002B
+:0211C30000002A
+:0211C400000029
+:0211C500000028
+:0211C600000027
+:0211C700000026
+:0211C800000025
+:0211C900000024
+:0211CA00000023
+:0211CB00000022
+:0211CC00000021
+:0211CD00000020
+:0211CE0000001F
+:0211CF0000001E
+:0211D00000001D
+:0211D10000001C
+:0211D20000001B
+:0211D30000001A
+:0211D400000019
+:0211D500000018
+:0211D600000017
+:0211D700000016
+:0211D800000015
+:0211D900000014
+:0211DA00000013
+:0211DB00000012
+:0211DC00000011
+:0211DD00000010
+:0211DE0000000F
+:0211DF0000000E
+:0211E00000000D
+:0211E10000000C
+:0211E20000000B
+:0211E30000000A
+:0211E400000009
+:0211E500000008
+:0211E600000007
+:0211E700000006
+:0211E800000005
+:0211E900000004
+:0211EA00000003
+:0211EB00000002
+:0211EC00000001
+:0211ED00000000
+:0211EE000000FF
+:0211EF000000FE
+:0211F0000000FD
+:0211F1000000FC
+:0211F2000000FB
+:0211F3000000FA
+:0211F4000000F9
+:0211F5000000F8
+:0211F6000000F7
+:0211F7000000F6
+:0211F8000000F5
+:0211F9000000F4
+:0211FA000000F3
+:0211FB000000F2
+:0211FC000000F1
+:0211FD000000F0
+:0211FE000000EF
+:0211FF000000EE
+:021200000000EC
+:021201000000EB
+:021202000000EA
+:021203000000E9
+:021204000000E8
+:021205000000E7
+:021206000000E6
+:021207000000E5
+:021208000000E4
+:021209000000E3
+:02120A000000E2
+:02120B000000E1
+:02120C000000E0
+:02120D000000DF
+:02120E000000DE
+:02120F000000DD
+:021210000000DC
+:021211000000DB
+:021212000000DA
+:021213000000D9
+:021214000000D8
+:021215000000D7
+:021216000000D6
+:021217000000D5
+:021218000000D4
+:021219000000D3
+:02121A000000D2
+:02121B000000D1
+:02121C000000D0
+:02121D000000CF
+:02121E000000CE
+:02121F000000CD
+:021220000000CC
+:021221000000CB
+:021222000000CA
+:021223000000C9
+:021224000000C8
+:021225000000C7
+:021226000000C6
+:021227000000C5
+:021228000000C4
+:021229000000C3
+:02122A000000C2
+:02122B000000C1
+:02122C000000C0
+:02122D000000BF
+:02122E000000BE
+:02122F000000BD
+:021230000000BC
+:021231000000BB
+:021232000000BA
+:021233000000B9
+:021234000000B8
+:021235000000B7
+:021236000000B6
+:021237000000B5
+:021238000000B4
+:021239000000B3
+:02123A000000B2
+:02123B000000B1
+:02123C000000B0
+:02123D000000AF
+:02123E000000AE
+:02123F000000AD
+:021240000000AC
+:021241000000AB
+:021242000000AA
+:021243000000A9
+:021244000000A8
+:021245000000A7
+:021246000000A6
+:021247000000A5
+:021248000000A4
+:021249000000A3
+:02124A000000A2
+:02124B000000A1
+:02124C000000A0
+:02124D0000009F
+:02124E0000009E
+:02124F0000009D
+:0212500000009C
+:0212510000009B
+:0212520000009A
+:02125300000099
+:02125400000098
+:02125500000097
+:02125600000096
+:02125700000095
+:02125800000094
+:02125900000093
+:02125A00000092
+:02125B00000091
+:02125C00000090
+:02125D0000008F
+:02125E0000008E
+:02125F0000008D
+:0212600000008C
+:0212610000008B
+:0212620000008A
+:02126300000089
+:02126400000088
+:02126500000087
+:02126600000086
+:02126700000085
+:02126800000084
+:02126900000083
+:02126A00000082
+:02126B00000081
+:02126C00000080
+:02126D0000007F
+:02126E0000007E
+:02126F0000007D
+:0212700000007C
+:0212710000007B
+:0212720000007A
+:02127300000079
+:02127400000078
+:02127500000077
+:02127600000076
+:02127700000075
+:02127800000074
+:02127900000073
+:02127A00000072
+:02127B00000071
+:02127C00000070
+:02127D0000006F
+:02127E0000006E
+:02127F0000006D
+:0212800000006C
+:0212810000006B
+:0212820000006A
+:02128300000069
+:02128400000068
+:02128500000067
+:02128600000066
+:02128700000065
+:02128800000064
+:02128900000063
+:02128A00000062
+:02128B00000061
+:02128C00000060
+:02128D0000005F
+:02128E0000005E
+:02128F0000005D
+:0212900000005C
+:0212910000005B
+:0212920000005A
+:02129300000059
+:02129400000058
+:02129500000057
+:02129600000056
+:02129700000055
+:02129800000054
+:02129900000053
+:02129A00000052
+:02129B00000051
+:02129C00000050
+:02129D0000004F
+:02129E0000004E
+:02129F0000004D
+:0212A00000004C
+:0212A10000004B
+:0212A20000004A
+:0212A300000049
+:0212A400000048
+:0212A500000047
+:0212A600000046
+:0212A700000045
+:0212A800000044
+:0212A900000043
+:0212AA00000042
+:0212AB00000041
+:0212AC00000040
+:0212AD0000003F
+:0212AE0000003E
+:0212AF0000003D
+:0212B00000003C
+:0212B10000003B
+:0212B20000003A
+:0212B300000039
+:0212B400000038
+:0212B500000037
+:0212B600000036
+:0212B700000035
+:0212B800000034
+:0212B900000033
+:0212BA00000032
+:0212BB00000031
+:0212BC00000030
+:0212BD0000002F
+:0212BE0000002E
+:0212BF0000002D
+:0212C00000002C
+:0212C10000002B
+:0212C20000002A
+:0212C300000029
+:0212C400000028
+:0212C500000027
+:0212C600000026
+:0212C700000025
+:0212C800000024
+:0212C900000023
+:0212CA00000022
+:0212CB00000021
+:0212CC00000020
+:0212CD0000001F
+:0212CE0000001E
+:0212CF0000001D
+:0212D00000001C
+:0212D10000001B
+:0212D20000001A
+:0212D300000019
+:0212D400000018
+:0212D500000017
+:0212D600000016
+:0212D700000015
+:0212D800000014
+:0212D900000013
+:0212DA00000012
+:0212DB00000011
+:0212DC00000010
+:0212DD0000000F
+:0212DE0000000E
+:0212DF0000000D
+:0212E00000000C
+:0212E10000000B
+:0212E20000000A
+:0212E300000009
+:0212E400000008
+:0212E500000007
+:0212E600000006
+:0212E700000005
+:0212E800000004
+:0212E900000003
+:0212EA00000002
+:0212EB00000001
+:0212EC00000000
+:0212ED000000FF
+:0212EE000000FE
+:0212EF000000FD
+:0212F0000000FC
+:0212F1000000FB
+:0212F2000000FA
+:0212F3000000F9
+:0212F4000000F8
+:0212F5000000F7
+:0212F6000000F6
+:0212F7000000F5
+:0212F8000000F4
+:0212F9000000F3
+:0212FA000000F2
+:0212FB000000F1
+:0212FC000000F0
+:0212FD000000EF
+:0212FE000000EE
+:0212FF000000ED
+:021300000000EB
+:021301000000EA
+:021302000000E9
+:021303000000E8
+:021304000000E7
+:021305000000E6
+:021306000000E5
+:021307000000E4
+:021308000000E3
+:021309000000E2
+:02130A000000E1
+:02130B000000E0
+:02130C000000DF
+:02130D000000DE
+:02130E000000DD
+:02130F000000DC
+:021310000000DB
+:021311000000DA
+:021312000000D9
+:021313000000D8
+:021314000000D7
+:021315000000D6
+:021316000000D5
+:021317000000D4
+:021318000000D3
+:021319000000D2
+:02131A000000D1
+:02131B000000D0
+:02131C000000CF
+:02131D000000CE
+:02131E000000CD
+:02131F000000CC
+:021320000000CB
+:021321000000CA
+:021322000000C9
+:021323000000C8
+:021324000000C7
+:021325000000C6
+:021326000000C5
+:021327000000C4
+:021328000000C3
+:021329000000C2
+:02132A000000C1
+:02132B000000C0
+:02132C000000BF
+:02132D000000BE
+:02132E000000BD
+:02132F000000BC
+:021330000000BB
+:021331000000BA
+:021332000000B9
+:021333000000B8
+:021334000000B7
+:021335000000B6
+:021336000000B5
+:021337000000B4
+:021338000000B3
+:021339000000B2
+:02133A000000B1
+:02133B000000B0
+:02133C000000AF
+:02133D000000AE
+:02133E000000AD
+:02133F000000AC
+:021340000000AB
+:021341000000AA
+:021342000000A9
+:021343000000A8
+:021344000000A7
+:021345000000A6
+:021346000000A5
+:021347000000A4
+:021348000000A3
+:021349000000A2
+:02134A000000A1
+:02134B000000A0
+:02134C0000009F
+:02134D0000009E
+:02134E0000009D
+:02134F0000009C
+:0213500000009B
+:0213510000009A
+:02135200000099
+:02135300000098
+:02135400000097
+:02135500000096
+:02135600000095
+:02135700000094
+:02135800000093
+:02135900000092
+:02135A00000091
+:02135B00000090
+:02135C0000008F
+:02135D0000008E
+:02135E0000008D
+:02135F0000008C
+:0213600000008B
+:0213610000008A
+:02136200000089
+:02136300000088
+:02136400000087
+:02136500000086
+:02136600000085
+:02136700000084
+:02136800000083
+:02136900000082
+:02136A00000081
+:02136B00000080
+:02136C0000007F
+:02136D0000007E
+:02136E0000007D
+:02136F0000007C
+:0213700000007B
+:0213710000007A
+:02137200000079
+:02137300000078
+:02137400000077
+:02137500000076
+:02137600000075
+:02137700000074
+:02137800000073
+:02137900000072
+:02137A00000071
+:02137B00000070
+:02137C0000006F
+:02137D0000006E
+:02137E0000006D
+:02137F0000006C
+:0213800000006B
+:0213810000006A
+:02138200000069
+:02138300000068
+:02138400000067
+:02138500000066
+:02138600000065
+:02138700000064
+:02138800000063
+:02138900000062
+:02138A00000061
+:02138B00000060
+:02138C0000005F
+:02138D0000005E
+:02138E0000005D
+:02138F0000005C
+:0213900000005B
+:0213910000005A
+:02139200000059
+:02139300000058
+:02139400000057
+:02139500000056
+:02139600000055
+:02139700000054
+:02139800000053
+:02139900000052
+:02139A00000051
+:02139B00000050
+:02139C0000004F
+:02139D0000004E
+:02139E0000004D
+:02139F0000004C
+:0213A00000004B
+:0213A10000004A
+:0213A200000049
+:0213A300000048
+:0213A400000047
+:0213A500000046
+:0213A600000045
+:0213A700000044
+:0213A800000043
+:0213A900000042
+:0213AA00000041
+:0213AB00000040
+:0213AC0000003F
+:0213AD0000003E
+:0213AE0000003D
+:0213AF0000003C
+:0213B00000003B
+:0213B10000003A
+:0213B200000039
+:0213B300000038
+:0213B400000037
+:0213B500000036
+:0213B600000035
+:0213B700000034
+:0213B800000033
+:0213B900000032
+:0213BA00000031
+:0213BB00000030
+:0213BC0000002F
+:0213BD0000002E
+:0213BE0000002D
+:0213BF0000002C
+:0213C00000002B
+:0213C10000002A
+:0213C200000029
+:0213C300000028
+:0213C400000027
+:0213C500000026
+:0213C600000025
+:0213C700000024
+:0213C800000023
+:0213C900000022
+:0213CA00000021
+:0213CB00000020
+:0213CC0000001F
+:0213CD0000001E
+:0213CE0000001D
+:0213CF0000001C
+:0213D00000001B
+:0213D10000001A
+:0213D200000019
+:0213D300000018
+:0213D400000017
+:0213D500000016
+:0213D600000015
+:0213D700000014
+:0213D800000013
+:0213D900000012
+:0213DA00000011
+:0213DB00000010
+:0213DC0000000F
+:0213DD0000000E
+:0213DE0000000D
+:0213DF0000000C
+:0213E00000000B
+:0213E10000000A
+:0213E200000009
+:0213E300000008
+:0213E400000007
+:0213E500000006
+:0213E600000005
+:0213E700000004
+:0213E800000003
+:0213E900000002
+:0213EA00000001
+:0213EB00000000
+:0213EC000000FF
+:0213ED000000FE
+:0213EE000000FD
+:0213EF000000FC
+:0213F0000000FB
+:0213F1000000FA
+:0213F2000000F9
+:0213F3000000F8
+:0213F4000000F7
+:0213F5000000F6
+:0213F6000000F5
+:0213F7000000F4
+:0213F8000000F3
+:0213F9000000F2
+:0213FA000000F1
+:0213FB000000F0
+:0213FC000000EF
+:0213FD000000EE
+:0213FE000000ED
+:0213FF000000EC
+:021400000000EA
+:021401000000E9
+:021402000000E8
+:021403000000E7
+:021404000000E6
+:021405000000E5
+:021406000000E4
+:021407000000E3
+:021408000000E2
+:021409000000E1
+:02140A000000E0
+:02140B000000DF
+:02140C000000DE
+:02140D000000DD
+:02140E000000DC
+:02140F000000DB
+:021410000000DA
+:021411000000D9
+:021412000000D8
+:021413000000D7
+:021414000000D6
+:021415000000D5
+:021416000000D4
+:021417000000D3
+:021418000000D2
+:021419000000D1
+:02141A000000D0
+:02141B000000CF
+:02141C000000CE
+:02141D000000CD
+:02141E000000CC
+:02141F000000CB
+:021420000000CA
+:021421000000C9
+:021422000000C8
+:021423000000C7
+:021424000000C6
+:021425000000C5
+:021426000000C4
+:021427000000C3
+:021428000000C2
+:021429000000C1
+:02142A000000C0
+:02142B000000BF
+:02142C000000BE
+:02142D000000BD
+:02142E000000BC
+:02142F000000BB
+:021430000000BA
+:021431000000B9
+:021432000000B8
+:021433000000B7
+:021434000000B6
+:021435000000B5
+:021436000000B4
+:021437000000B3
+:021438000000B2
+:021439000000B1
+:02143A000000B0
+:02143B000000AF
+:02143C000000AE
+:02143D000000AD
+:02143E000000AC
+:02143F000000AB
+:021440000000AA
+:021441000000A9
+:021442000000A8
+:021443000000A7
+:021444000000A6
+:021445000000A5
+:021446000000A4
+:021447000000A3
+:021448000000A2
+:021449000000A1
+:02144A000000A0
+:02144B0000009F
+:02144C0000009E
+:02144D0000009D
+:02144E0000009C
+:02144F0000009B
+:0214500000009A
+:02145100000099
+:02145200000098
+:02145300000097
+:02145400000096
+:02145500000095
+:02145600000094
+:02145700000093
+:02145800000092
+:02145900000091
+:02145A00000090
+:02145B0000008F
+:02145C0000008E
+:02145D0000008D
+:02145E0000008C
+:02145F0000008B
+:0214600000008A
+:02146100000089
+:02146200000088
+:02146300000087
+:02146400000086
+:02146500000085
+:02146600000084
+:02146700000083
+:02146800000082
+:02146900000081
+:02146A00000080
+:02146B0000007F
+:02146C0000007E
+:02146D0000007D
+:02146E0000007C
+:02146F0000007B
+:0214700000007A
+:02147100000079
+:02147200000078
+:02147300000077
+:02147400000076
+:02147500000075
+:02147600000074
+:02147700000073
+:02147800000072
+:02147900000071
+:02147A00000070
+:02147B0000006F
+:02147C0000006E
+:02147D0000006D
+:02147E0000006C
+:02147F0000006B
+:0214800000006A
+:02148100000069
+:02148200000068
+:02148300000067
+:02148400000066
+:02148500000065
+:02148600000064
+:02148700000063
+:02148800000062
+:02148900000061
+:02148A00000060
+:02148B0000005F
+:02148C0000005E
+:02148D0000005D
+:02148E0000005C
+:02148F0000005B
+:0214900000005A
+:02149100000059
+:02149200000058
+:02149300000057
+:02149400000056
+:02149500000055
+:02149600000054
+:02149700000053
+:02149800000052
+:02149900000051
+:02149A00000050
+:02149B0000004F
+:02149C0000004E
+:02149D0000004D
+:02149E0000004C
+:02149F0000004B
+:0214A00000004A
+:0214A100000049
+:0214A200000048
+:0214A300000047
+:0214A400000046
+:0214A500000045
+:0214A600000044
+:0214A700000043
+:0214A800000042
+:0214A900000041
+:0214AA00000040
+:0214AB0000003F
+:0214AC0000003E
+:0214AD0000003D
+:0214AE0000003C
+:0214AF0000003B
+:0214B00000003A
+:0214B100000039
+:0214B200000038
+:0214B300000037
+:0214B400000036
+:0214B500000035
+:0214B600000034
+:0214B700000033
+:0214B800000032
+:0214B900000031
+:0214BA00000030
+:0214BB0000002F
+:0214BC0000002E
+:0214BD0000002D
+:0214BE0000002C
+:0214BF0000002B
+:0214C00000002A
+:0214C100000029
+:0214C200000028
+:0214C300000027
+:0214C400000026
+:0214C500000025
+:0214C600000024
+:0214C700000023
+:0214C800000022
+:0214C900000021
+:0214CA00000020
+:0214CB0000001F
+:0214CC0000001E
+:0214CD0000001D
+:0214CE0000001C
+:0214CF0000001B
+:0214D00000001A
+:0214D100000019
+:0214D200000018
+:0214D300000017
+:0214D400000016
+:0214D500000015
+:0214D600000014
+:0214D700000013
+:0214D800000012
+:0214D900000011
+:0214DA00000010
+:0214DB0000000F
+:0214DC0000000E
+:0214DD0000000D
+:0214DE0000000C
+:0214DF0000000B
+:0214E00000000A
+:0214E100000009
+:0214E200000008
+:0214E300000007
+:0214E400000006
+:0214E500000005
+:0214E600000004
+:0214E700000003
+:0214E800000002
+:0214E900000001
+:0214EA00000000
+:0214EB000000FF
+:0214EC000000FE
+:0214ED000000FD
+:0214EE000000FC
+:0214EF000000FB
+:0214F0000000FA
+:0214F1000000F9
+:0214F2000000F8
+:0214F3000000F7
+:0214F4000000F6
+:0214F5000000F5
+:0214F6000000F4
+:0214F7000000F3
+:0214F8000000F2
+:0214F9000000F1
+:0214FA000000F0
+:0214FB000000EF
+:0214FC000000EE
+:0214FD000000ED
+:0214FE000000EC
+:0214FF000000EB
+:021500000000E9
+:021501000000E8
+:021502000000E7
+:021503000000E6
+:021504000000E5
+:021505000000E4
+:021506000000E3
+:021507000000E2
+:021508000000E1
+:021509000000E0
+:02150A000000DF
+:02150B000000DE
+:02150C000000DD
+:02150D000000DC
+:02150E000000DB
+:02150F000000DA
+:021510000000D9
+:021511000000D8
+:021512000000D7
+:021513000000D6
+:021514000000D5
+:021515000000D4
+:021516000000D3
+:021517000000D2
+:021518000000D1
+:021519000000D0
+:02151A000000CF
+:02151B000000CE
+:02151C000000CD
+:02151D000000CC
+:02151E000000CB
+:02151F000000CA
+:021520000000C9
+:021521000000C8
+:021522000000C7
+:021523000000C6
+:021524000000C5
+:021525000000C4
+:021526000000C3
+:021527000000C2
+:021528000000C1
+:021529000000C0
+:02152A000000BF
+:02152B000000BE
+:02152C000000BD
+:02152D000000BC
+:02152E000000BB
+:02152F000000BA
+:021530000000B9
+:021531000000B8
+:021532000000B7
+:021533000000B6
+:021534000000B5
+:021535000000B4
+:021536000000B3
+:021537000000B2
+:021538000000B1
+:021539000000B0
+:02153A000000AF
+:02153B000000AE
+:02153C000000AD
+:02153D000000AC
+:02153E000000AB
+:02153F000000AA
+:021540000000A9
+:021541000000A8
+:021542000000A7
+:021543000000A6
+:021544000000A5
+:021545000000A4
+:021546000000A3
+:021547000000A2
+:021548000000A1
+:021549000000A0
+:02154A0000009F
+:02154B0000009E
+:02154C0000009D
+:02154D0000009C
+:02154E0000009B
+:02154F0000009A
+:02155000000099
+:02155100000098
+:02155200000097
+:02155300000096
+:02155400000095
+:02155500000094
+:02155600000093
+:02155700000092
+:02155800000091
+:02155900000090
+:02155A0000008F
+:02155B0000008E
+:02155C0000008D
+:02155D0000008C
+:02155E0000008B
+:02155F0000008A
+:02156000000089
+:02156100000088
+:02156200000087
+:02156300000086
+:02156400000085
+:02156500000084
+:02156600000083
+:02156700000082
+:02156800000081
+:02156900000080
+:02156A0000007F
+:02156B0000007E
+:02156C0000007D
+:02156D0000007C
+:02156E0000007B
+:02156F0000007A
+:02157000000079
+:02157100000078
+:02157200000077
+:02157300000076
+:02157400000075
+:02157500000074
+:02157600000073
+:02157700000072
+:02157800000071
+:02157900000070
+:02157A0000006F
+:02157B0000006E
+:02157C0000006D
+:02157D0000006C
+:02157E0000006B
+:02157F0000006A
+:02158000000069
+:02158100000068
+:02158200000067
+:02158300000066
+:02158400000065
+:02158500000064
+:02158600000063
+:02158700000062
+:02158800000061
+:02158900000060
+:02158A0000005F
+:02158B0000005E
+:02158C0000005D
+:02158D0000005C
+:02158E0000005B
+:02158F0000005A
+:02159000000059
+:02159100000058
+:02159200000057
+:02159300000056
+:02159400000055
+:02159500000054
+:02159600000053
+:02159700000052
+:02159800000051
+:02159900000050
+:02159A0000004F
+:02159B0000004E
+:02159C0000004D
+:02159D0000004C
+:02159E0000004B
+:02159F0000004A
+:0215A000000049
+:0215A100000048
+:0215A200000047
+:0215A300000046
+:0215A400000045
+:0215A500000044
+:0215A600000043
+:0215A700000042
+:0215A800000041
+:0215A900000040
+:0215AA0000003F
+:0215AB0000003E
+:0215AC0000003D
+:0215AD0000003C
+:0215AE0000003B
+:0215AF0000003A
+:0215B000000039
+:0215B100000038
+:0215B200000037
+:0215B300000036
+:0215B400000035
+:0215B500000034
+:0215B600000033
+:0215B700000032
+:0215B800000031
+:0215B900000030
+:0215BA0000002F
+:0215BB0000002E
+:0215BC0000002D
+:0215BD0000002C
+:0215BE0000002B
+:0215BF0000002A
+:0215C000000029
+:0215C100000028
+:0215C200000027
+:0215C300000026
+:0215C400000025
+:0215C500000024
+:0215C600000023
+:0215C700000022
+:0215C800000021
+:0215C900000020
+:0215CA0000001F
+:0215CB0000001E
+:0215CC0000001D
+:0215CD0000001C
+:0215CE0000001B
+:0215CF0000001A
+:0215D000000019
+:0215D100000018
+:0215D200000017
+:0215D300000016
+:0215D400000015
+:0215D500000014
+:0215D600000013
+:0215D700000012
+:0215D800000011
+:0215D900000010
+:0215DA0000000F
+:0215DB0000000E
+:0215DC0000000D
+:0215DD0000000C
+:0215DE0000000B
+:0215DF0000000A
+:0215E000000009
+:0215E100000008
+:0215E200000007
+:0215E300000006
+:0215E400000005
+:0215E500000004
+:0215E600000003
+:0215E700000002
+:0215E800000001
+:0215E900000000
+:0215EA000000FF
+:0215EB000000FE
+:0215EC000000FD
+:0215ED000000FC
+:0215EE000000FB
+:0215EF000000FA
+:0215F0000000F9
+:0215F1000000F8
+:0215F2000000F7
+:0215F3000000F6
+:0215F4000000F5
+:0215F5000000F4
+:0215F6000000F3
+:0215F7000000F2
+:0215F8000000F1
+:0215F9000000F0
+:0215FA000000EF
+:0215FB000000EE
+:0215FC000000ED
+:0215FD000000EC
+:0215FE000000EB
+:0215FF000000EA
+:021600000000E8
+:021601000000E7
+:021602000000E6
+:021603000000E5
+:021604000000E4
+:021605000000E3
+:021606000000E2
+:021607000000E1
+:021608000000E0
+:021609000000DF
+:02160A000000DE
+:02160B000000DD
+:02160C000000DC
+:02160D000000DB
+:02160E000000DA
+:02160F000000D9
+:021610000000D8
+:021611000000D7
+:021612000000D6
+:021613000000D5
+:021614000000D4
+:021615000000D3
+:021616000000D2
+:021617000000D1
+:021618000000D0
+:021619000000CF
+:02161A000000CE
+:02161B000000CD
+:02161C000000CC
+:02161D000000CB
+:02161E000000CA
+:02161F000000C9
+:021620000000C8
+:021621000000C7
+:021622000000C6
+:021623000000C5
+:021624000000C4
+:021625000000C3
+:021626000000C2
+:021627000000C1
+:021628000000C0
+:021629000000BF
+:02162A000000BE
+:02162B000000BD
+:02162C000000BC
+:02162D000000BB
+:02162E000000BA
+:02162F000000B9
+:021630000000B8
+:021631000000B7
+:021632000000B6
+:021633000000B5
+:021634000000B4
+:021635000000B3
+:021636000000B2
+:021637000000B1
+:021638000000B0
+:021639000000AF
+:02163A000000AE
+:02163B000000AD
+:02163C000000AC
+:02163D000000AB
+:02163E000000AA
+:02163F000000A9
+:021640000000A8
+:021641000000A7
+:021642000000A6
+:021643000000A5
+:021644000000A4
+:021645000000A3
+:021646000000A2
+:021647000000A1
+:021648000000A0
+:0216490000009F
+:02164A0000009E
+:02164B0000009D
+:02164C0000009C
+:02164D0000009B
+:02164E0000009A
+:02164F00000099
+:02165000000098
+:02165100000097
+:02165200000096
+:02165300000095
+:02165400000094
+:02165500000093
+:02165600000092
+:02165700000091
+:02165800000090
+:0216590000008F
+:02165A0000008E
+:02165B0000008D
+:02165C0000008C
+:02165D0000008B
+:02165E0000008A
+:02165F00000089
+:02166000000088
+:02166100000087
+:02166200000086
+:02166300000085
+:02166400000084
+:02166500000083
+:02166600000082
+:02166700000081
+:02166800000080
+:0216690000007F
+:02166A0000007E
+:02166B0000007D
+:02166C0000007C
+:02166D0000007B
+:02166E0000007A
+:02166F00000079
+:02167000000078
+:02167100000077
+:02167200000076
+:02167300000075
+:02167400000074
+:02167500000073
+:02167600000072
+:02167700000071
+:02167800000070
+:0216790000006F
+:02167A0000006E
+:02167B0000006D
+:02167C0000006C
+:02167D0000006B
+:02167E0000006A
+:02167F00000069
+:02168000000068
+:02168100000067
+:02168200000066
+:02168300000065
+:02168400000064
+:02168500000063
+:02168600000062
+:02168700000061
+:02168800000060
+:0216890000005F
+:02168A0000005E
+:02168B0000005D
+:02168C0000005C
+:02168D0000005B
+:02168E0000005A
+:02168F00000059
+:02169000000058
+:02169100000057
+:02169200000056
+:02169300000055
+:02169400000054
+:02169500000053
+:02169600000052
+:02169700000051
+:02169800000050
+:0216990000004F
+:02169A0000004E
+:02169B0000004D
+:02169C0000004C
+:02169D0000004B
+:02169E0000004A
+:02169F00000049
+:0216A000000048
+:0216A100000047
+:0216A200000046
+:0216A300000045
+:0216A400000044
+:0216A500000043
+:0216A600000042
+:0216A700000041
+:0216A800000040
+:0216A90000003F
+:0216AA0000003E
+:0216AB0000003D
+:0216AC0000003C
+:0216AD0000003B
+:0216AE0000003A
+:0216AF00000039
+:0216B000000038
+:0216B100000037
+:0216B200000036
+:0216B300000035
+:0216B400000034
+:0216B500000033
+:0216B600000032
+:0216B700000031
+:0216B800000030
+:0216B90000002F
+:0216BA0000002E
+:0216BB0000002D
+:0216BC0000002C
+:0216BD0000002B
+:0216BE0000002A
+:0216BF00000029
+:0216C000000028
+:0216C100000027
+:0216C200000026
+:0216C300000025
+:0216C400000024
+:0216C500000023
+:0216C600000022
+:0216C700000021
+:0216C800000020
+:0216C90000001F
+:0216CA0000001E
+:0216CB0000001D
+:0216CC0000001C
+:0216CD0000001B
+:0216CE0000001A
+:0216CF00000019
+:0216D000000018
+:0216D100000017
+:0216D200000016
+:0216D300000015
+:0216D400000014
+:0216D500000013
+:0216D600000012
+:0216D700000011
+:0216D800000010
+:0216D90000000F
+:0216DA0000000E
+:0216DB0000000D
+:0216DC0000000C
+:0216DD0000000B
+:0216DE0000000A
+:0216DF00000009
+:0216E000000008
+:0216E100000007
+:0216E200000006
+:0216E300000005
+:0216E400000004
+:0216E500000003
+:0216E600000002
+:0216E700000001
+:0216E800000000
+:0216E9000000FF
+:0216EA000000FE
+:0216EB000000FD
+:0216EC000000FC
+:0216ED000000FB
+:0216EE000000FA
+:0216EF000000F9
+:0216F0000000F8
+:0216F1000000F7
+:0216F2000000F6
+:0216F3000000F5
+:0216F4000000F4
+:0216F5000000F3
+:0216F6000000F2
+:0216F7000000F1
+:0216F8000000F0
+:0216F9000000EF
+:0216FA000000EE
+:0216FB000000ED
+:0216FC000000EC
+:0216FD000000EB
+:0216FE000000EA
+:0216FF000000E9
+:021700000000E7
+:021701000000E6
+:021702000000E5
+:021703000000E4
+:021704000000E3
+:021705000000E2
+:021706000000E1
+:021707000000E0
+:021708000000DF
+:021709000000DE
+:02170A000000DD
+:02170B000000DC
+:02170C000000DB
+:02170D000000DA
+:02170E000000D9
+:02170F000000D8
+:021710000000D7
+:021711000000D6
+:021712000000D5
+:021713000000D4
+:021714000000D3
+:021715000000D2
+:021716000000D1
+:021717000000D0
+:021718000000CF
+:021719000000CE
+:02171A000000CD
+:02171B000000CC
+:02171C000000CB
+:02171D000000CA
+:02171E000000C9
+:02171F000000C8
+:021720000000C7
+:021721000000C6
+:021722000000C5
+:021723000000C4
+:021724000000C3
+:021725000000C2
+:021726000000C1
+:021727000000C0
+:021728000000BF
+:021729000000BE
+:02172A000000BD
+:02172B000000BC
+:02172C000000BB
+:02172D000000BA
+:02172E000000B9
+:02172F000000B8
+:021730000000B7
+:021731000000B6
+:021732000000B5
+:021733000000B4
+:021734000000B3
+:021735000000B2
+:021736000000B1
+:021737000000B0
+:021738000000AF
+:021739000000AE
+:02173A000000AD
+:02173B000000AC
+:02173C000000AB
+:02173D000000AA
+:02173E000000A9
+:02173F000000A8
+:021740000000A7
+:021741000000A6
+:021742000000A5
+:021743000000A4
+:021744000000A3
+:021745000000A2
+:021746000000A1
+:021747000000A0
+:0217480000009F
+:0217490000009E
+:02174A0000009D
+:02174B0000009C
+:02174C0000009B
+:02174D0000009A
+:02174E00000099
+:02174F00000098
+:02175000000097
+:02175100000096
+:02175200000095
+:02175300000094
+:02175400000093
+:02175500000092
+:02175600000091
+:02175700000090
+:0217580000008F
+:0217590000008E
+:02175A0000008D
+:02175B0000008C
+:02175C0000008B
+:02175D0000008A
+:02175E00000089
+:02175F00000088
+:02176000000087
+:02176100000086
+:02176200000085
+:02176300000084
+:02176400000083
+:02176500000082
+:02176600000081
+:02176700000080
+:0217680000007F
+:0217690000007E
+:02176A0000007D
+:02176B0000007C
+:02176C0000007B
+:02176D0000007A
+:02176E00000079
+:02176F00000078
+:02177000000077
+:02177100000076
+:02177200000075
+:02177300000074
+:02177400000073
+:02177500000072
+:02177600000071
+:02177700000070
+:0217780000006F
+:0217790000006E
+:02177A0000006D
+:02177B0000006C
+:02177C0000006B
+:02177D0000006A
+:02177E00000069
+:02177F00000068
+:02178000000067
+:02178100000066
+:02178200000065
+:02178300000064
+:02178400000063
+:02178500000062
+:02178600000061
+:02178700000060
+:0217880000005F
+:0217890000005E
+:02178A0000005D
+:02178B0000005C
+:02178C0000005B
+:02178D0000005A
+:02178E00000059
+:02178F00000058
+:02179000000057
+:02179100000056
+:02179200000055
+:02179300000054
+:02179400000053
+:02179500000052
+:02179600000051
+:02179700000050
+:0217980000004F
+:0217990000004E
+:02179A0000004D
+:02179B0000004C
+:02179C0000004B
+:02179D0000004A
+:02179E00000049
+:02179F00000048
+:0217A000000047
+:0217A100000046
+:0217A200000045
+:0217A300000044
+:0217A400000043
+:0217A500000042
+:0217A600000041
+:0217A700000040
+:0217A80000003F
+:0217A90000003E
+:0217AA0000003D
+:0217AB0000003C
+:0217AC0000003B
+:0217AD0000003A
+:0217AE00000039
+:0217AF00000038
+:0217B000000037
+:0217B100000036
+:0217B200000035
+:0217B300000034
+:0217B400000033
+:0217B500000032
+:0217B600000031
+:0217B700000030
+:0217B80000002F
+:0217B90000002E
+:0217BA0000002D
+:0217BB0000002C
+:0217BC0000002B
+:0217BD0000002A
+:0217BE00000029
+:0217BF00000028
+:0217C000000027
+:0217C100000026
+:0217C200000025
+:0217C300000024
+:0217C400000023
+:0217C500000022
+:0217C600000021
+:0217C700000020
+:0217C80000001F
+:0217C90000001E
+:0217CA0000001D
+:0217CB0000001C
+:0217CC0000001B
+:0217CD0000001A
+:0217CE00000019
+:0217CF00000018
+:0217D000000017
+:0217D100000016
+:0217D200000015
+:0217D300000014
+:0217D400000013
+:0217D500000012
+:0217D600000011
+:0217D700000010
+:0217D80000000F
+:0217D90000000E
+:0217DA0000000D
+:0217DB0000000C
+:0217DC0000000B
+:0217DD0000000A
+:0217DE00000009
+:0217DF00000008
+:0217E000000007
+:0217E100000006
+:0217E200000005
+:0217E300000004
+:0217E400000003
+:0217E500000002
+:0217E600000001
+:0217E700000000
+:0217E8000000FF
+:0217E9000000FE
+:0217EA000000FD
+:0217EB000000FC
+:0217EC000000FB
+:0217ED000000FA
+:0217EE000000F9
+:0217EF000000F8
+:0217F0000000F7
+:0217F1000000F6
+:0217F2000000F5
+:0217F3000000F4
+:0217F4000000F3
+:0217F5000000F2
+:0217F6000000F1
+:0217F7000000F0
+:0217F8000000EF
+:0217F9000000EE
+:0217FA000000ED
+:0217FB000000EC
+:0217FC000000EB
+:0217FD000000EA
+:0217FE000000E9
+:0217FF000000E8
+:021800000000E6
+:021801000000E5
+:021802000000E4
+:021803000000E3
+:021804000000E2
+:021805000000E1
+:021806000000E0
+:021807000000DF
+:021808000000DE
+:021809000000DD
+:02180A000000DC
+:02180B000000DB
+:02180C000000DA
+:02180D000000D9
+:02180E000000D8
+:02180F000000D7
+:021810000000D6
+:021811000000D5
+:021812000000D4
+:021813000000D3
+:021814000000D2
+:021815000000D1
+:021816000000D0
+:021817000000CF
+:021818000000CE
+:021819000000CD
+:02181A000000CC
+:02181B000000CB
+:02181C000000CA
+:02181D000000C9
+:02181E000000C8
+:02181F000000C7
+:021820000000C6
+:021821000000C5
+:021822000000C4
+:021823000000C3
+:021824000000C2
+:021825000000C1
+:021826000000C0
+:021827000000BF
+:021828000000BE
+:021829000000BD
+:02182A000000BC
+:02182B000000BB
+:02182C000000BA
+:02182D000000B9
+:02182E000000B8
+:02182F000000B7
+:021830000000B6
+:021831000000B5
+:021832000000B4
+:021833000000B3
+:021834000000B2
+:021835000000B1
+:021836000000B0
+:021837000000AF
+:021838000000AE
+:021839000000AD
+:02183A000000AC
+:02183B000000AB
+:02183C000000AA
+:02183D000000A9
+:02183E000000A8
+:02183F000000A7
+:021840000000A6
+:021841000000A5
+:021842000000A4
+:021843000000A3
+:021844000000A2
+:021845000000A1
+:021846000000A0
+:0218470000009F
+:0218480000009E
+:0218490000009D
+:02184A0000009C
+:02184B0000009B
+:02184C0000009A
+:02184D00000099
+:02184E00000098
+:02184F00000097
+:02185000000096
+:02185100000095
+:02185200000094
+:02185300000093
+:02185400000092
+:02185500000091
+:02185600000090
+:0218570000008F
+:0218580000008E
+:0218590000008D
+:02185A0000008C
+:02185B0000008B
+:02185C0000008A
+:02185D00000089
+:02185E00000088
+:02185F00000087
+:02186000000086
+:02186100000085
+:02186200000084
+:02186300000083
+:02186400000082
+:02186500000081
+:02186600000080
+:0218670000007F
+:0218680000007E
+:0218690000007D
+:02186A0000007C
+:02186B0000007B
+:02186C0000007A
+:02186D00000079
+:02186E00000078
+:02186F00000077
+:02187000000076
+:02187100000075
+:02187200000074
+:02187300000073
+:02187400000072
+:02187500000071
+:02187600000070
+:0218770000006F
+:0218780000006E
+:0218790000006D
+:02187A0000006C
+:02187B0000006B
+:02187C0000006A
+:02187D00000069
+:02187E00000068
+:02187F00000067
+:02188000000066
+:02188100000065
+:02188200000064
+:02188300000063
+:02188400000062
+:02188500000061
+:02188600000060
+:0218870000005F
+:0218880000005E
+:0218890000005D
+:02188A0000005C
+:02188B0000005B
+:02188C0000005A
+:02188D00000059
+:02188E00000058
+:02188F00000057
+:02189000000056
+:02189100000055
+:02189200000054
+:02189300000053
+:02189400000052
+:02189500000051
+:02189600000050
+:0218970000004F
+:0218980000004E
+:0218990000004D
+:02189A0000004C
+:02189B0000004B
+:02189C0000004A
+:02189D00000049
+:02189E00000048
+:02189F00000047
+:0218A000000046
+:0218A100000045
+:0218A200000044
+:0218A300000043
+:0218A400000042
+:0218A500000041
+:0218A600000040
+:0218A70000003F
+:0218A80000003E
+:0218A90000003D
+:0218AA0000003C
+:0218AB0000003B
+:0218AC0000003A
+:0218AD00000039
+:0218AE00000038
+:0218AF00000037
+:0218B000000036
+:0218B100000035
+:0218B200000034
+:0218B300000033
+:0218B400000032
+:0218B500000031
+:0218B600000030
+:0218B70000002F
+:0218B80000002E
+:0218B90000002D
+:0218BA0000002C
+:0218BB0000002B
+:0218BC0000002A
+:0218BD00000029
+:0218BE00000028
+:0218BF00000027
+:0218C000000026
+:0218C100000025
+:0218C200000024
+:0218C300000023
+:0218C400000022
+:0218C500000021
+:0218C600000020
+:0218C70000001F
+:0218C80000001E
+:0218C90000001D
+:0218CA0000001C
+:0218CB0000001B
+:0218CC0000001A
+:0218CD00000019
+:0218CE00000018
+:0218CF00000017
+:0218D000000016
+:0218D100000015
+:0218D200000014
+:0218D300000013
+:0218D400000012
+:0218D500000011
+:0218D600000010
+:0218D70000000F
+:0218D80000000E
+:0218D90000000D
+:0218DA0000000C
+:0218DB0000000B
+:0218DC0000000A
+:0218DD00000009
+:0218DE00000008
+:0218DF00000007
+:0218E000000006
+:0218E100000005
+:0218E200000004
+:0218E300000003
+:0218E400000002
+:0218E500000001
+:0218E600000000
+:0218E7000000FF
+:0218E8000000FE
+:0218E9000000FD
+:0218EA000000FC
+:0218EB000000FB
+:0218EC000000FA
+:0218ED000000F9
+:0218EE000000F8
+:0218EF000000F7
+:0218F0000000F6
+:0218F1000000F5
+:0218F2000000F4
+:0218F3000000F3
+:0218F4000000F2
+:0218F5000000F1
+:0218F6000000F0
+:0218F7000000EF
+:0218F8000000EE
+:0218F9000000ED
+:0218FA000000EC
+:0218FB000000EB
+:0218FC000000EA
+:0218FD000000E9
+:0218FE000000E8
+:0218FF000000E7
+:021900000000E5
+:021901000000E4
+:021902000000E3
+:021903000000E2
+:021904000000E1
+:021905000000E0
+:021906000000DF
+:021907000000DE
+:021908000000DD
+:021909000000DC
+:02190A000000DB
+:02190B000000DA
+:02190C000000D9
+:02190D000000D8
+:02190E000000D7
+:02190F000000D6
+:021910000000D5
+:021911000000D4
+:021912000000D3
+:021913000000D2
+:021914000000D1
+:021915000000D0
+:021916000000CF
+:021917000000CE
+:021918000000CD
+:021919000000CC
+:02191A000000CB
+:02191B000000CA
+:02191C000000C9
+:02191D000000C8
+:02191E000000C7
+:02191F000000C6
+:021920000000C5
+:021921000000C4
+:021922000000C3
+:021923000000C2
+:021924000000C1
+:021925000000C0
+:021926000000BF
+:021927000000BE
+:021928000000BD
+:021929000000BC
+:02192A000000BB
+:02192B000000BA
+:02192C000000B9
+:02192D000000B8
+:02192E000000B7
+:02192F000000B6
+:021930000000B5
+:021931000000B4
+:021932000000B3
+:021933000000B2
+:021934000000B1
+:021935000000B0
+:021936000000AF
+:021937000000AE
+:021938000000AD
+:021939000000AC
+:02193A000000AB
+:02193B000000AA
+:02193C000000A9
+:02193D000000A8
+:02193E000000A7
+:02193F000000A6
+:021940000000A5
+:021941000000A4
+:021942000000A3
+:021943000000A2
+:021944000000A1
+:021945000000A0
+:0219460000009F
+:0219470000009E
+:0219480000009D
+:0219490000009C
+:02194A0000009B
+:02194B0000009A
+:02194C00000099
+:02194D00000098
+:02194E00000097
+:02194F00000096
+:02195000000095
+:02195100000094
+:02195200000093
+:02195300000092
+:02195400000091
+:02195500000090
+:0219560000008F
+:0219570000008E
+:0219580000008D
+:0219590000008C
+:02195A0000008B
+:02195B0000008A
+:02195C00000089
+:02195D00000088
+:02195E00000087
+:02195F00000086
+:02196000000085
+:02196100000084
+:02196200000083
+:02196300000082
+:02196400000081
+:02196500000080
+:0219660000007F
+:0219670000007E
+:0219680000007D
+:0219690000007C
+:02196A0000007B
+:02196B0000007A
+:02196C00000079
+:02196D00000078
+:02196E00000077
+:02196F00000076
+:02197000000075
+:02197100000074
+:02197200000073
+:02197300000072
+:02197400000071
+:02197500000070
+:0219760000006F
+:0219770000006E
+:0219780000006D
+:0219790000006C
+:02197A0000006B
+:02197B0000006A
+:02197C00000069
+:02197D00000068
+:02197E00000067
+:02197F00000066
+:02198000000065
+:02198100000064
+:02198200000063
+:02198300000062
+:02198400000061
+:02198500000060
+:0219860000005F
+:0219870000005E
+:0219880000005D
+:0219890000005C
+:02198A0000005B
+:02198B0000005A
+:02198C00000059
+:02198D00000058
+:02198E00000057
+:02198F00000056
+:02199000000055
+:02199100000054
+:02199200000053
+:02199300000052
+:02199400000051
+:02199500000050
+:0219960000004F
+:0219970000004E
+:0219980000004D
+:0219990000004C
+:02199A0000004B
+:02199B0000004A
+:02199C00000049
+:02199D00000048
+:02199E00000047
+:02199F00000046
+:0219A000000045
+:0219A100000044
+:0219A200000043
+:0219A300000042
+:0219A400000041
+:0219A500000040
+:0219A60000003F
+:0219A70000003E
+:0219A80000003D
+:0219A90000003C
+:0219AA0000003B
+:0219AB0000003A
+:0219AC00000039
+:0219AD00000038
+:0219AE00000037
+:0219AF00000036
+:0219B000000035
+:0219B100000034
+:0219B200000033
+:0219B300000032
+:0219B400000031
+:0219B500000030
+:0219B60000002F
+:0219B70000002E
+:0219B80000002D
+:0219B90000002C
+:0219BA0000002B
+:0219BB0000002A
+:0219BC00000029
+:0219BD00000028
+:0219BE00000027
+:0219BF00000026
+:0219C000000025
+:0219C100000024
+:0219C200000023
+:0219C300000022
+:0219C400000021
+:0219C500000020
+:0219C60000001F
+:0219C70000001E
+:0219C80000001D
+:0219C90000001C
+:0219CA0000001B
+:0219CB0000001A
+:0219CC00000019
+:0219CD00000018
+:0219CE00000017
+:0219CF00000016
+:0219D000000015
+:0219D100000014
+:0219D200000013
+:0219D300000012
+:0219D400000011
+:0219D500000010
+:0219D60000000F
+:0219D70000000E
+:0219D80000000D
+:0219D90000000C
+:0219DA0000000B
+:0219DB0000000A
+:0219DC00000009
+:0219DD00000008
+:0219DE00000007
+:0219DF00000006
+:0219E000000005
+:0219E100000004
+:0219E200000003
+:0219E300000002
+:0219E400000001
+:0219E500000000
+:0219E6000000FF
+:0219E7000000FE
+:0219E8000000FD
+:0219E9000000FC
+:0219EA000000FB
+:0219EB000000FA
+:0219EC000000F9
+:0219ED000000F8
+:0219EE000000F7
+:0219EF000000F6
+:0219F0000000F5
+:0219F1000000F4
+:0219F2000000F3
+:0219F3000000F2
+:0219F4000000F1
+:0219F5000000F0
+:0219F6000000EF
+:0219F7000000EE
+:0219F8000000ED
+:0219F9000000EC
+:0219FA000000EB
+:0219FB000000EA
+:0219FC000000E9
+:0219FD000000E8
+:0219FE000000E7
+:0219FF000000E6
+:021A00000000E4
+:021A01000000E3
+:021A02000000E2
+:021A03000000E1
+:021A04000000E0
+:021A05000000DF
+:021A06000000DE
+:021A07000000DD
+:021A08000000DC
+:021A09000000DB
+:021A0A000000DA
+:021A0B000000D9
+:021A0C000000D8
+:021A0D000000D7
+:021A0E000000D6
+:021A0F000000D5
+:021A10000000D4
+:021A11000000D3
+:021A12000000D2
+:021A13000000D1
+:021A14000000D0
+:021A15000000CF
+:021A16000000CE
+:021A17000000CD
+:021A18000000CC
+:021A19000000CB
+:021A1A000000CA
+:021A1B000000C9
+:021A1C000000C8
+:021A1D000000C7
+:021A1E000000C6
+:021A1F000000C5
+:021A20000000C4
+:021A21000000C3
+:021A22000000C2
+:021A23000000C1
+:021A24000000C0
+:021A25000000BF
+:021A26000000BE
+:021A27000000BD
+:021A28000000BC
+:021A29000000BB
+:021A2A000000BA
+:021A2B000000B9
+:021A2C000000B8
+:021A2D000000B7
+:021A2E000000B6
+:021A2F000000B5
+:021A30000000B4
+:021A31000000B3
+:021A32000000B2
+:021A33000000B1
+:021A34000000B0
+:021A35000000AF
+:021A36000000AE
+:021A37000000AD
+:021A38000000AC
+:021A39000000AB
+:021A3A000000AA
+:021A3B000000A9
+:021A3C000000A8
+:021A3D000000A7
+:021A3E000000A6
+:021A3F000000A5
+:021A40000000A4
+:021A41000000A3
+:021A42000000A2
+:021A43000000A1
+:021A44000000A0
+:021A450000009F
+:021A460000009E
+:021A470000009D
+:021A480000009C
+:021A490000009B
+:021A4A0000009A
+:021A4B00000099
+:021A4C00000098
+:021A4D00000097
+:021A4E00000096
+:021A4F00000095
+:021A5000000094
+:021A5100000093
+:021A5200000092
+:021A5300000091
+:021A5400000090
+:021A550000008F
+:021A560000008E
+:021A570000008D
+:021A580000008C
+:021A590000008B
+:021A5A0000008A
+:021A5B00000089
+:021A5C00000088
+:021A5D00000087
+:021A5E00000086
+:021A5F00000085
+:021A6000000084
+:021A6100000083
+:021A6200000082
+:021A6300000081
+:021A6400000080
+:021A650000007F
+:021A660000007E
+:021A670000007D
+:021A680000007C
+:021A690000007B
+:021A6A0000007A
+:021A6B00000079
+:021A6C00000078
+:021A6D00000077
+:021A6E00000076
+:021A6F00000075
+:021A7000000074
+:021A7100000073
+:021A7200000072
+:021A7300000071
+:021A7400000070
+:021A750000006F
+:021A760000006E
+:021A770000006D
+:021A780000006C
+:021A790000006B
+:021A7A0000006A
+:021A7B00000069
+:021A7C00000068
+:021A7D00000067
+:021A7E00000066
+:021A7F00000065
+:021A8000000064
+:021A8100000063
+:021A8200000062
+:021A8300000061
+:021A8400000060
+:021A850000005F
+:021A860000005E
+:021A870000005D
+:021A880000005C
+:021A890000005B
+:021A8A0000005A
+:021A8B00000059
+:021A8C00000058
+:021A8D00000057
+:021A8E00000056
+:021A8F00000055
+:021A9000000054
+:021A9100000053
+:021A9200000052
+:021A9300000051
+:021A9400000050
+:021A950000004F
+:021A960000004E
+:021A970000004D
+:021A980000004C
+:021A990000004B
+:021A9A0000004A
+:021A9B00000049
+:021A9C00000048
+:021A9D00000047
+:021A9E00000046
+:021A9F00000045
+:021AA000000044
+:021AA100000043
+:021AA200000042
+:021AA300000041
+:021AA400000040
+:021AA50000003F
+:021AA60000003E
+:021AA70000003D
+:021AA80000003C
+:021AA90000003B
+:021AAA0000003A
+:021AAB00000039
+:021AAC00000038
+:021AAD00000037
+:021AAE00000036
+:021AAF00000035
+:021AB000000034
+:021AB100000033
+:021AB200000032
+:021AB300000031
+:021AB400000030
+:021AB50000002F
+:021AB60000002E
+:021AB70000002D
+:021AB80000002C
+:021AB90000002B
+:021ABA0000002A
+:021ABB00000029
+:021ABC00000028
+:021ABD00000027
+:021ABE00000026
+:021ABF00000025
+:021AC000000024
+:021AC100000023
+:021AC200000022
+:021AC300000021
+:021AC400000020
+:021AC50000001F
+:021AC60000001E
+:021AC70000001D
+:021AC80000001C
+:021AC90000001B
+:021ACA0000001A
+:021ACB00000019
+:021ACC00000018
+:021ACD00000017
+:021ACE00000016
+:021ACF00000015
+:021AD000000014
+:021AD100000013
+:021AD200000012
+:021AD300000011
+:021AD400000010
+:021AD50000000F
+:021AD60000000E
+:021AD70000000D
+:021AD80000000C
+:021AD90000000B
+:021ADA0000000A
+:021ADB00000009
+:021ADC00000008
+:021ADD00000007
+:021ADE00000006
+:021ADF00000005
+:021AE000000004
+:021AE100000003
+:021AE200000002
+:021AE300000001
+:021AE400000000
+:021AE5000000FF
+:021AE6000000FE
+:021AE7000000FD
+:021AE8000000FC
+:021AE9000000FB
+:021AEA000000FA
+:021AEB000000F9
+:021AEC000000F8
+:021AED000000F7
+:021AEE000000F6
+:021AEF000000F5
+:021AF0000000F4
+:021AF1000000F3
+:021AF2000000F2
+:021AF3000000F1
+:021AF4000000F0
+:021AF5000000EF
+:021AF6000000EE
+:021AF7000000ED
+:021AF8000000EC
+:021AF9000000EB
+:021AFA000000EA
+:021AFB000000E9
+:021AFC000000E8
+:021AFD000000E7
+:021AFE000000E6
+:021AFF000000E5
+:021B00000000E3
+:021B01000000E2
+:021B02000000E1
+:021B03000000E0
+:021B04000000DF
+:021B05000000DE
+:021B06000000DD
+:021B07000000DC
+:021B08000000DB
+:021B09000000DA
+:021B0A000000D9
+:021B0B000000D8
+:021B0C000000D7
+:021B0D000000D6
+:021B0E000000D5
+:021B0F000000D4
+:021B10000000D3
+:021B11000000D2
+:021B12000000D1
+:021B13000000D0
+:021B14000000CF
+:021B15000000CE
+:021B16000000CD
+:021B17000000CC
+:021B18000000CB
+:021B19000000CA
+:021B1A000000C9
+:021B1B000000C8
+:021B1C000000C7
+:021B1D000000C6
+:021B1E000000C5
+:021B1F000000C4
+:021B20000000C3
+:021B21000000C2
+:021B22000000C1
+:021B23000000C0
+:021B24000000BF
+:021B25000000BE
+:021B26000000BD
+:021B27000000BC
+:021B28000000BB
+:021B29000000BA
+:021B2A000000B9
+:021B2B000000B8
+:021B2C000000B7
+:021B2D000000B6
+:021B2E000000B5
+:021B2F000000B4
+:021B30000000B3
+:021B31000000B2
+:021B32000000B1
+:021B33000000B0
+:021B34000000AF
+:021B35000000AE
+:021B36000000AD
+:021B37000000AC
+:021B38000000AB
+:021B39000000AA
+:021B3A000000A9
+:021B3B000000A8
+:021B3C000000A7
+:021B3D000000A6
+:021B3E000000A5
+:021B3F000000A4
+:021B40000000A3
+:021B41000000A2
+:021B42000000A1
+:021B43000000A0
+:021B440000009F
+:021B450000009E
+:021B460000009D
+:021B470000009C
+:021B480000009B
+:021B490000009A
+:021B4A00000099
+:021B4B00000098
+:021B4C00000097
+:021B4D00000096
+:021B4E00000095
+:021B4F00000094
+:021B5000000093
+:021B5100000092
+:021B5200000091
+:021B5300000090
+:021B540000008F
+:021B550000008E
+:021B560000008D
+:021B570000008C
+:021B580000008B
+:021B590000008A
+:021B5A00000089
+:021B5B00000088
+:021B5C00000087
+:021B5D00000086
+:021B5E00000085
+:021B5F00000084
+:021B6000000083
+:021B6100000082
+:021B6200000081
+:021B6300000080
+:021B640000007F
+:021B650000007E
+:021B660000007D
+:021B670000007C
+:021B680000007B
+:021B690000007A
+:021B6A00000079
+:021B6B00000078
+:021B6C00000077
+:021B6D00000076
+:021B6E00000075
+:021B6F00000074
+:021B7000000073
+:021B7100000072
+:021B7200000071
+:021B7300000070
+:021B740000006F
+:021B750000006E
+:021B760000006D
+:021B770000006C
+:021B780000006B
+:021B790000006A
+:021B7A00000069
+:021B7B00000068
+:021B7C00000067
+:021B7D00000066
+:021B7E00000065
+:021B7F00000064
+:021B8000000063
+:021B8100000062
+:021B8200000061
+:021B8300000060
+:021B840000005F
+:021B850000005E
+:021B860000005D
+:021B870000005C
+:021B880000005B
+:021B890000005A
+:021B8A00000059
+:021B8B00000058
+:021B8C00000057
+:021B8D00000056
+:021B8E00000055
+:021B8F00000054
+:021B9000000053
+:021B9100000052
+:021B9200000051
+:021B9300000050
+:021B940000004F
+:021B950000004E
+:021B960000004D
+:021B970000004C
+:021B980000004B
+:021B990000004A
+:021B9A00000049
+:021B9B00000048
+:021B9C00000047
+:021B9D00000046
+:021B9E00000045
+:021B9F00000044
+:021BA000000043
+:021BA100000042
+:021BA200000041
+:021BA300000040
+:021BA40000003F
+:021BA50000003E
+:021BA60000003D
+:021BA70000003C
+:021BA80000003B
+:021BA90000003A
+:021BAA00000039
+:021BAB00000038
+:021BAC00000037
+:021BAD00000036
+:021BAE00000035
+:021BAF00000034
+:021BB000000033
+:021BB100000032
+:021BB200000031
+:021BB300000030
+:021BB40000002F
+:021BB50000002E
+:021BB60000002D
+:021BB70000002C
+:021BB80000002B
+:021BB90000002A
+:021BBA00000029
+:021BBB00000028
+:021BBC00000027
+:021BBD00000026
+:021BBE00000025
+:021BBF00000024
+:021BC000000023
+:021BC100000022
+:021BC200000021
+:021BC300000020
+:021BC40000001F
+:021BC50000001E
+:021BC60000001D
+:021BC70000001C
+:021BC80000001B
+:021BC90000001A
+:021BCA00000019
+:021BCB00000018
+:021BCC00000017
+:021BCD00000016
+:021BCE00000015
+:021BCF00000014
+:021BD000000013
+:021BD100000012
+:021BD200000011
+:021BD300000010
+:021BD40000000F
+:021BD50000000E
+:021BD60000000D
+:021BD70000000C
+:021BD80000000B
+:021BD90000000A
+:021BDA00000009
+:021BDB00000008
+:021BDC00000007
+:021BDD00000006
+:021BDE00000005
+:021BDF00000004
+:021BE000000003
+:021BE100000002
+:021BE200000001
+:021BE300000000
+:021BE4000000FF
+:021BE5000000FE
+:021BE6000000FD
+:021BE7000000FC
+:021BE8000000FB
+:021BE9000000FA
+:021BEA000000F9
+:021BEB000000F8
+:021BEC000000F7
+:021BED000000F6
+:021BEE000000F5
+:021BEF000000F4
+:021BF0000000F3
+:021BF1000000F2
+:021BF2000000F1
+:021BF3000000F0
+:021BF4000000EF
+:021BF5000000EE
+:021BF6000000ED
+:021BF7000000EC
+:021BF8000000EB
+:021BF9000000EA
+:021BFA000000E9
+:021BFB000000E8
+:021BFC000000E7
+:021BFD000000E6
+:021BFE000000E5
+:021BFF000000E4
+:021C00000000E2
+:021C01000000E1
+:021C02000000E0
+:021C03000000DF
+:021C04000000DE
+:021C05000000DD
+:021C06000000DC
+:021C07000000DB
+:021C08000000DA
+:021C09000000D9
+:021C0A000000D8
+:021C0B000000D7
+:021C0C000000D6
+:021C0D000000D5
+:021C0E000000D4
+:021C0F000000D3
+:021C10000000D2
+:021C11000000D1
+:021C12000000D0
+:021C13000000CF
+:021C14000000CE
+:021C15000000CD
+:021C16000000CC
+:021C17000000CB
+:021C18000000CA
+:021C19000000C9
+:021C1A000000C8
+:021C1B000000C7
+:021C1C000000C6
+:021C1D000000C5
+:021C1E000000C4
+:021C1F000000C3
+:021C20000000C2
+:021C21000000C1
+:021C22000000C0
+:021C23000000BF
+:021C24000000BE
+:021C25000000BD
+:021C26000000BC
+:021C27000000BB
+:021C28000000BA
+:021C29000000B9
+:021C2A000000B8
+:021C2B000000B7
+:021C2C000000B6
+:021C2D000000B5
+:021C2E000000B4
+:021C2F000000B3
+:021C30000000B2
+:021C31000000B1
+:021C32000000B0
+:021C33000000AF
+:021C34000000AE
+:021C35000000AD
+:021C36000000AC
+:021C37000000AB
+:021C38000000AA
+:021C39000000A9
+:021C3A000000A8
+:021C3B000000A7
+:021C3C000000A6
+:021C3D000000A5
+:021C3E000000A4
+:021C3F000000A3
+:021C40000000A2
+:021C41000000A1
+:021C42000000A0
+:021C430000009F
+:021C440000009E
+:021C450000009D
+:021C460000009C
+:021C470000009B
+:021C480000009A
+:021C4900000099
+:021C4A00000098
+:021C4B00000097
+:021C4C00000096
+:021C4D00000095
+:021C4E00000094
+:021C4F00000093
+:021C5000000092
+:021C5100000091
+:021C5200000090
+:021C530000008F
+:021C540000008E
+:021C550000008D
+:021C560000008C
+:021C570000008B
+:021C580000008A
+:021C5900000089
+:021C5A00000088
+:021C5B00000087
+:021C5C00000086
+:021C5D00000085
+:021C5E00000084
+:021C5F00000083
+:021C6000000082
+:021C6100000081
+:021C6200000080
+:021C630000007F
+:021C640000007E
+:021C650000007D
+:021C660000007C
+:021C670000007B
+:021C680000007A
+:021C6900000079
+:021C6A00000078
+:021C6B00000077
+:021C6C00000076
+:021C6D00000075
+:021C6E00000074
+:021C6F00000073
+:021C7000000072
+:021C7100000071
+:021C7200000070
+:021C730000006F
+:021C740000006E
+:021C750000006D
+:021C760000006C
+:021C770000006B
+:021C780000006A
+:021C7900000069
+:021C7A00000068
+:021C7B00000067
+:021C7C00000066
+:021C7D00000065
+:021C7E00000064
+:021C7F00000063
+:021C8000000062
+:021C8100000061
+:021C8200000060
+:021C830000005F
+:021C840000005E
+:021C850000005D
+:021C860000005C
+:021C870000005B
+:021C880000005A
+:021C8900000059
+:021C8A00000058
+:021C8B00000057
+:021C8C00000056
+:021C8D00000055
+:021C8E00000054
+:021C8F00000053
+:021C9000000052
+:021C9100000051
+:021C9200000050
+:021C930000004F
+:021C940000004E
+:021C950000004D
+:021C960000004C
+:021C970000004B
+:021C980000004A
+:021C9900000049
+:021C9A00000048
+:021C9B00000047
+:021C9C00000046
+:021C9D00000045
+:021C9E00000044
+:021C9F00000043
+:021CA000000042
+:021CA100000041
+:021CA200000040
+:021CA30000003F
+:021CA40000003E
+:021CA50000003D
+:021CA60000003C
+:021CA70000003B
+:021CA80000003A
+:021CA900000039
+:021CAA00000038
+:021CAB00000037
+:021CAC00000036
+:021CAD00000035
+:021CAE00000034
+:021CAF00000033
+:021CB000000032
+:021CB100000031
+:021CB200000030
+:021CB30000002F
+:021CB40000002E
+:021CB50000002D
+:021CB60000002C
+:021CB70000002B
+:021CB80000002A
+:021CB900000029
+:021CBA00000028
+:021CBB00000027
+:021CBC00000026
+:021CBD00000025
+:021CBE00000024
+:021CBF00000023
+:021CC000000022
+:021CC100000021
+:021CC200000020
+:021CC30000001F
+:021CC40000001E
+:021CC50000001D
+:021CC60000001C
+:021CC70000001B
+:021CC80000001A
+:021CC900000019
+:021CCA00000018
+:021CCB00000017
+:021CCC00000016
+:021CCD00000015
+:021CCE00000014
+:021CCF00000013
+:021CD000000012
+:021CD100000011
+:021CD200000010
+:021CD30000000F
+:021CD40000000E
+:021CD50000000D
+:021CD60000000C
+:021CD70000000B
+:021CD80000000A
+:021CD900000009
+:021CDA00000008
+:021CDB00000007
+:021CDC00000006
+:021CDD00000005
+:021CDE00000004
+:021CDF00000003
+:021CE000000002
+:021CE100000001
+:021CE200000000
+:021CE3000000FF
+:021CE4000000FE
+:021CE5000000FD
+:021CE6000000FC
+:021CE7000000FB
+:021CE8000000FA
+:021CE9000000F9
+:021CEA000000F8
+:021CEB000000F7
+:021CEC000000F6
+:021CED000000F5
+:021CEE000000F4
+:021CEF000000F3
+:021CF0000000F2
+:021CF1000000F1
+:021CF2000000F0
+:021CF3000000EF
+:021CF4000000EE
+:021CF5000000ED
+:021CF6000000EC
+:021CF7000000EB
+:021CF8000000EA
+:021CF9000000E9
+:021CFA000000E8
+:021CFB000000E7
+:021CFC000000E6
+:021CFD000000E5
+:021CFE000000E4
+:021CFF000000E3
+:021D00000000E1
+:021D01000000E0
+:021D02000000DF
+:021D03000000DE
+:021D04000000DD
+:021D05000000DC
+:021D06000000DB
+:021D07000000DA
+:021D08000000D9
+:021D09000000D8
+:021D0A000000D7
+:021D0B000000D6
+:021D0C000000D5
+:021D0D000000D4
+:021D0E000000D3
+:021D0F000000D2
+:021D10000000D1
+:021D11000000D0
+:021D12000000CF
+:021D13000000CE
+:021D14000000CD
+:021D15000000CC
+:021D16000000CB
+:021D17000000CA
+:021D18000000C9
+:021D19000000C8
+:021D1A000000C7
+:021D1B000000C6
+:021D1C000000C5
+:021D1D000000C4
+:021D1E000000C3
+:021D1F000000C2
+:021D20000000C1
+:021D21000000C0
+:021D22000000BF
+:021D23000000BE
+:021D24000000BD
+:021D25000000BC
+:021D26000000BB
+:021D27000000BA
+:021D28000000B9
+:021D29000000B8
+:021D2A000000B7
+:021D2B000000B6
+:021D2C000000B5
+:021D2D000000B4
+:021D2E000000B3
+:021D2F000000B2
+:021D30000000B1
+:021D31000000B0
+:021D32000000AF
+:021D33000000AE
+:021D34000000AD
+:021D35000000AC
+:021D36000000AB
+:021D37000000AA
+:021D38000000A9
+:021D39000000A8
+:021D3A000000A7
+:021D3B000000A6
+:021D3C000000A5
+:021D3D000000A4
+:021D3E000000A3
+:021D3F000000A2
+:021D40000000A1
+:021D41000000A0
+:021D420000009F
+:021D430000009E
+:021D440000009D
+:021D450000009C
+:021D460000009B
+:021D470000009A
+:021D4800000099
+:021D4900000098
+:021D4A00000097
+:021D4B00000096
+:021D4C00000095
+:021D4D00000094
+:021D4E00000093
+:021D4F00000092
+:021D5000000091
+:021D5100000090
+:021D520000008F
+:021D530000008E
+:021D540000008D
+:021D550000008C
+:021D560000008B
+:021D570000008A
+:021D5800000089
+:021D5900000088
+:021D5A00000087
+:021D5B00000086
+:021D5C00000085
+:021D5D00000084
+:021D5E00000083
+:021D5F00000082
+:021D6000000081
+:021D6100000080
+:021D620000007F
+:021D630000007E
+:021D640000007D
+:021D650000007C
+:021D660000007B
+:021D670000007A
+:021D6800000079
+:021D6900000078
+:021D6A00000077
+:021D6B00000076
+:021D6C00000075
+:021D6D00000074
+:021D6E00000073
+:021D6F00000072
+:021D7000000071
+:021D7100000070
+:021D720000006F
+:021D730000006E
+:021D740000006D
+:021D750000006C
+:021D760000006B
+:021D770000006A
+:021D7800000069
+:021D7900000068
+:021D7A00000067
+:021D7B00000066
+:021D7C00000065
+:021D7D00000064
+:021D7E00000063
+:021D7F00000062
+:021D8000000061
+:021D8100000060
+:021D820000005F
+:021D830000005E
+:021D840000005D
+:021D850000005C
+:021D860000005B
+:021D870000005A
+:021D8800000059
+:021D8900000058
+:021D8A00000057
+:021D8B00000056
+:021D8C00000055
+:021D8D00000054
+:021D8E00000053
+:021D8F00000052
+:021D9000000051
+:021D9100000050
+:021D920000004F
+:021D930000004E
+:021D940000004D
+:021D950000004C
+:021D960000004B
+:021D970000004A
+:021D9800000049
+:021D9900000048
+:021D9A00000047
+:021D9B00000046
+:021D9C00000045
+:021D9D00000044
+:021D9E00000043
+:021D9F00000042
+:021DA000000041
+:021DA100000040
+:021DA20000003F
+:021DA30000003E
+:021DA40000003D
+:021DA50000003C
+:021DA60000003B
+:021DA70000003A
+:021DA800000039
+:021DA900000038
+:021DAA00000037
+:021DAB00000036
+:021DAC00000035
+:021DAD00000034
+:021DAE00000033
+:021DAF00000032
+:021DB000000031
+:021DB100000030
+:021DB20000002F
+:021DB30000002E
+:021DB40000002D
+:021DB50000002C
+:021DB60000002B
+:021DB70000002A
+:021DB800000029
+:021DB900000028
+:021DBA00000027
+:021DBB00000026
+:021DBC00000025
+:021DBD00000024
+:021DBE00000023
+:021DBF00000022
+:021DC000000021
+:021DC100000020
+:021DC20000001F
+:021DC30000001E
+:021DC40000001D
+:021DC50000001C
+:021DC60000001B
+:021DC70000001A
+:021DC800000019
+:021DC900000018
+:021DCA00000017
+:021DCB00000016
+:021DCC00000015
+:021DCD00000014
+:021DCE00000013
+:021DCF00000012
+:021DD000000011
+:021DD100000010
+:021DD20000000F
+:021DD30000000E
+:021DD40000000D
+:021DD50000000C
+:021DD60000000B
+:021DD70000000A
+:021DD800000009
+:021DD900000008
+:021DDA00000007
+:021DDB00000006
+:021DDC00000005
+:021DDD00000004
+:021DDE00000003
+:021DDF00000002
+:021DE000000001
+:021DE100000000
+:021DE2000000FF
+:021DE3000000FE
+:021DE4000000FD
+:021DE5000000FC
+:021DE6000000FB
+:021DE7000000FA
+:021DE8000000F9
+:021DE9000000F8
+:021DEA000000F7
+:021DEB000000F6
+:021DEC000000F5
+:021DED000000F4
+:021DEE000000F3
+:021DEF000000F2
+:021DF0000000F1
+:021DF1000000F0
+:021DF2000000EF
+:021DF3000000EE
+:021DF4000000ED
+:021DF5000000EC
+:021DF6000000EB
+:021DF7000000EA
+:021DF8000000E9
+:021DF9000000E8
+:021DFA000000E7
+:021DFB000000E6
+:021DFC000000E5
+:021DFD000000E4
+:021DFE000000E3
+:021DFF000000E2
+:021E00000000E0
+:021E01000000DF
+:021E02000000DE
+:021E03000000DD
+:021E04000000DC
+:021E05000000DB
+:021E06000000DA
+:021E07000000D9
+:021E08000000D8
+:021E09000000D7
+:021E0A000000D6
+:021E0B000000D5
+:021E0C000000D4
+:021E0D000000D3
+:021E0E000000D2
+:021E0F000000D1
+:021E10000000D0
+:021E11000000CF
+:021E12000000CE
+:021E13000000CD
+:021E14000000CC
+:021E15000000CB
+:021E16000000CA
+:021E17000000C9
+:021E18000000C8
+:021E19000000C7
+:021E1A000000C6
+:021E1B000000C5
+:021E1C000000C4
+:021E1D000000C3
+:021E1E000000C2
+:021E1F000000C1
+:021E20000000C0
+:021E21000000BF
+:021E22000000BE
+:021E23000000BD
+:021E24000000BC
+:021E25000000BB
+:021E26000000BA
+:021E27000000B9
+:021E28000000B8
+:021E29000000B7
+:021E2A000000B6
+:021E2B000000B5
+:021E2C000000B4
+:021E2D000000B3
+:021E2E000000B2
+:021E2F000000B1
+:021E30000000B0
+:021E31000000AF
+:021E32000000AE
+:021E33000000AD
+:021E34000000AC
+:021E35000000AB
+:021E36000000AA
+:021E37000000A9
+:021E38000000A8
+:021E39000000A7
+:021E3A000000A6
+:021E3B000000A5
+:021E3C000000A4
+:021E3D000000A3
+:021E3E000000A2
+:021E3F000000A1
+:021E40000000A0
+:021E410000009F
+:021E420000009E
+:021E430000009D
+:021E440000009C
+:021E450000009B
+:021E460000009A
+:021E4700000099
+:021E4800000098
+:021E4900000097
+:021E4A00000096
+:021E4B00000095
+:021E4C00000094
+:021E4D00000093
+:021E4E00000092
+:021E4F00000091
+:021E5000000090
+:021E510000008F
+:021E520000008E
+:021E530000008D
+:021E540000008C
+:021E550000008B
+:021E560000008A
+:021E5700000089
+:021E5800000088
+:021E5900000087
+:021E5A00000086
+:021E5B00000085
+:021E5C00000084
+:021E5D00000083
+:021E5E00000082
+:021E5F00000081
+:021E6000000080
+:021E610000007F
+:021E620000007E
+:021E630000007D
+:021E640000007C
+:021E650000007B
+:021E660000007A
+:021E6700000079
+:021E6800000078
+:021E6900000077
+:021E6A00000076
+:021E6B00000075
+:021E6C00000074
+:021E6D00000073
+:021E6E00000072
+:021E6F00000071
+:021E7000000070
+:021E710000006F
+:021E720000006E
+:021E730000006D
+:021E740000006C
+:021E750000006B
+:021E760000006A
+:021E7700000069
+:021E7800000068
+:021E7900000067
+:021E7A00000066
+:021E7B00000065
+:021E7C00000064
+:021E7D00000063
+:021E7E00000062
+:021E7F00000061
+:021E8000000060
+:021E810000005F
+:021E820000005E
+:021E830000005D
+:021E840000005C
+:021E850000005B
+:021E860000005A
+:021E8700000059
+:021E8800000058
+:021E8900000057
+:021E8A00000056
+:021E8B00000055
+:021E8C00000054
+:021E8D00000053
+:021E8E00000052
+:021E8F00000051
+:021E9000000050
+:021E910000004F
+:021E920000004E
+:021E930000004D
+:021E940000004C
+:021E950000004B
+:021E960000004A
+:021E9700000049
+:021E9800000048
+:021E9900000047
+:021E9A00000046
+:021E9B00000045
+:021E9C00000044
+:021E9D00000043
+:021E9E00000042
+:021E9F00000041
+:021EA000000040
+:021EA10000003F
+:021EA20000003E
+:021EA30000003D
+:021EA40000003C
+:021EA50000003B
+:021EA60000003A
+:021EA700000039
+:021EA800000038
+:021EA900000037
+:021EAA00000036
+:021EAB00000035
+:021EAC00000034
+:021EAD00000033
+:021EAE00000032
+:021EAF00000031
+:021EB000000030
+:021EB10000002F
+:021EB20000002E
+:021EB30000002D
+:021EB40000002C
+:021EB50000002B
+:021EB60000002A
+:021EB700000029
+:021EB800000028
+:021EB900000027
+:021EBA00000026
+:021EBB00000025
+:021EBC00000024
+:021EBD00000023
+:021EBE00000022
+:021EBF00000021
+:021EC000000020
+:021EC10000001F
+:021EC20000001E
+:021EC30000001D
+:021EC40000001C
+:021EC50000001B
+:021EC60000001A
+:021EC700000019
+:021EC800000018
+:021EC900000017
+:021ECA00000016
+:021ECB00000015
+:021ECC00000014
+:021ECD00000013
+:021ECE00000012
+:021ECF00000011
+:021ED000000010
+:021ED10000000F
+:021ED20000000E
+:021ED30000000D
+:021ED40000000C
+:021ED50000000B
+:021ED60000000A
+:021ED700000009
+:021ED800000008
+:021ED900000007
+:021EDA00000006
+:021EDB00000005
+:021EDC00000004
+:021EDD00000003
+:021EDE00000002
+:021EDF00000001
+:021EE000000000
+:021EE1000000FF
+:021EE2000000FE
+:021EE3000000FD
+:021EE4000000FC
+:021EE5000000FB
+:021EE6000000FA
+:021EE7000000F9
+:021EE8000000F8
+:021EE9000000F7
+:021EEA000000F6
+:021EEB000000F5
+:021EEC000000F4
+:021EED000000F3
+:021EEE000000F2
+:021EEF000000F1
+:021EF0000000F0
+:021EF1000000EF
+:021EF2000000EE
+:021EF3000000ED
+:021EF4000000EC
+:021EF5000000EB
+:021EF6000000EA
+:021EF7000000E9
+:021EF8000000E8
+:021EF9000000E7
+:021EFA000000E6
+:021EFB000000E5
+:021EFC000000E4
+:021EFD000000E3
+:021EFE000000E2
+:021EFF000000E1
+:021F00000000DF
+:021F01000000DE
+:021F02000000DD
+:021F03000000DC
+:021F04000000DB
+:021F05000000DA
+:021F06000000D9
+:021F07000000D8
+:021F08000000D7
+:021F09000000D6
+:021F0A000000D5
+:021F0B000000D4
+:021F0C000000D3
+:021F0D000000D2
+:021F0E000000D1
+:021F0F000000D0
+:021F10000000CF
+:021F11000000CE
+:021F12000000CD
+:021F13000000CC
+:021F14000000CB
+:021F15000000CA
+:021F16000000C9
+:021F17000000C8
+:021F18000000C7
+:021F19000000C6
+:021F1A000000C5
+:021F1B000000C4
+:021F1C000000C3
+:021F1D000000C2
+:021F1E000000C1
+:021F1F000000C0
+:021F20000000BF
+:021F21000000BE
+:021F22000000BD
+:021F23000000BC
+:021F24000000BB
+:021F25000000BA
+:021F26000000B9
+:021F27000000B8
+:021F28000000B7
+:021F29000000B6
+:021F2A000000B5
+:021F2B000000B4
+:021F2C000000B3
+:021F2D000000B2
+:021F2E000000B1
+:021F2F000000B0
+:021F30000000AF
+:021F31000000AE
+:021F32000000AD
+:021F33000000AC
+:021F34000000AB
+:021F35000000AA
+:021F36000000A9
+:021F37000000A8
+:021F38000000A7
+:021F39000000A6
+:021F3A000000A5
+:021F3B000000A4
+:021F3C000000A3
+:021F3D000000A2
+:021F3E000000A1
+:021F3F000000A0
+:021F400000009F
+:021F410000009E
+:021F420000009D
+:021F430000009C
+:021F440000009B
+:021F450000009A
+:021F4600000099
+:021F4700000098
+:021F4800000097
+:021F4900000096
+:021F4A00000095
+:021F4B00000094
+:021F4C00000093
+:021F4D00000092
+:021F4E00000091
+:021F4F00000090
+:021F500000008F
+:021F510000008E
+:021F520000008D
+:021F530000008C
+:021F540000008B
+:021F550000008A
+:021F5600000089
+:021F5700000088
+:021F5800000087
+:021F5900000086
+:021F5A00000085
+:021F5B00000084
+:021F5C00000083
+:021F5D00000082
+:021F5E00000081
+:021F5F00000080
+:021F600000007F
+:021F610000007E
+:021F620000007D
+:021F630000007C
+:021F640000007B
+:021F650000007A
+:021F6600000079
+:021F6700000078
+:021F6800000077
+:021F6900000076
+:021F6A00000075
+:021F6B00000074
+:021F6C00000073
+:021F6D00000072
+:021F6E00000071
+:021F6F00000070
+:021F700000006F
+:021F710000006E
+:021F720000006D
+:021F730000006C
+:021F740000006B
+:021F750000006A
+:021F7600000069
+:021F7700000068
+:021F7800000067
+:021F7900000066
+:021F7A00000065
+:021F7B00000064
+:021F7C00000063
+:021F7D00000062
+:021F7E00000061
+:021F7F00000060
+:021F800000005F
+:021F810000005E
+:021F820000005D
+:021F830000005C
+:021F840000005B
+:021F850000005A
+:021F8600000059
+:021F8700000058
+:021F8800000057
+:021F8900000056
+:021F8A00000055
+:021F8B00000054
+:021F8C00000053
+:021F8D00000052
+:021F8E00000051
+:021F8F00000050
+:021F900000004F
+:021F910000004E
+:021F920000004D
+:021F930000004C
+:021F940000004B
+:021F950000004A
+:021F9600000049
+:021F9700000048
+:021F9800000047
+:021F9900000046
+:021F9A00000045
+:021F9B00000044
+:021F9C00000043
+:021F9D00000042
+:021F9E00000041
+:021F9F00000040
+:021FA00000003F
+:021FA10000003E
+:021FA20000003D
+:021FA30000003C
+:021FA40000003B
+:021FA50000003A
+:021FA600000039
+:021FA700000038
+:021FA800000037
+:021FA900000036
+:021FAA00000035
+:021FAB00000034
+:021FAC00000033
+:021FAD00000032
+:021FAE00000031
+:021FAF00000030
+:021FB00000002F
+:021FB10000002E
+:021FB20000002D
+:021FB30000002C
+:021FB40000002B
+:021FB50000002A
+:021FB600000029
+:021FB700000028
+:021FB800000027
+:021FB900000026
+:021FBA00000025
+:021FBB00000024
+:021FBC00000023
+:021FBD00000022
+:021FBE00000021
+:021FBF00000020
+:021FC00000001F
+:021FC10000001E
+:021FC20000001D
+:021FC30000001C
+:021FC40000001B
+:021FC50000001A
+:021FC600000019
+:021FC700000018
+:021FC800000017
+:021FC900000016
+:021FCA00000015
+:021FCB00000014
+:021FCC00000013
+:021FCD00000012
+:021FCE00000011
+:021FCF00000010
+:021FD00000000F
+:021FD10000000E
+:021FD20000000D
+:021FD30000000C
+:021FD40000000B
+:021FD50000000A
+:021FD600000009
+:021FD700000008
+:021FD800000007
+:021FD900000006
+:021FDA00000005
+:021FDB00000004
+:021FDC00000003
+:021FDD00000002
+:021FDE00000001
+:021FDF00000000
+:021FE0000000FF
+:021FE1000000FE
+:021FE2000000FD
+:021FE3000000FC
+:021FE4000000FB
+:021FE5000000FA
+:021FE6000000F9
+:021FE7000000F8
+:021FE8000000F7
+:021FE9000000F6
+:021FEA000000F5
+:021FEB000000F4
+:021FEC000000F3
+:021FED000000F2
+:021FEE000000F1
+:021FEF000000F0
+:021FF0000000EF
+:021FF1000000EE
+:021FF2000000ED
+:021FF3000000EC
+:021FF4000000EB
+:021FF5000000EA
+:021FF6000000E9
+:021FF7000000E8
+:021FF8000000E7
+:021FF9000000E6
+:021FFA000000E5
+:021FFB000000E4
+:021FFC000000E3
+:021FFD000000E2
+:021FFE000000E1
+:021FFF000000E0
+:022000000000DE
+:022001000000DD
+:022002000000DC
+:022003000000DB
+:022004000000DA
+:022005000000D9
+:022006000000D8
+:022007000000D7
+:022008000000D6
+:022009000000D5
+:02200A000000D4
+:02200B000000D3
+:02200C000000D2
+:02200D000000D1
+:02200E000000D0
+:02200F000000CF
+:022010000000CE
+:022011000000CD
+:022012000000CC
+:022013000000CB
+:022014000000CA
+:022015000000C9
+:022016000000C8
+:022017000000C7
+:022018000000C6
+:022019000000C5
+:02201A000000C4
+:02201B000000C3
+:02201C000000C2
+:02201D000000C1
+:02201E000000C0
+:02201F000000BF
+:022020000000BE
+:022021000000BD
+:022022000000BC
+:022023000000BB
+:022024000000BA
+:022025000000B9
+:022026000000B8
+:022027000000B7
+:022028000000B6
+:022029000000B5
+:02202A000000B4
+:02202B000000B3
+:02202C000000B2
+:02202D000000B1
+:02202E000000B0
+:02202F000000AF
+:022030000000AE
+:022031000000AD
+:022032000000AC
+:022033000000AB
+:022034000000AA
+:022035000000A9
+:022036000000A8
+:022037000000A7
+:022038000000A6
+:022039000000A5
+:02203A000000A4
+:02203B000000A3
+:02203C000000A2
+:02203D000000A1
+:02203E000000A0
+:02203F0000009F
+:0220400000009E
+:0220410000009D
+:0220420000009C
+:0220430000009B
+:0220440000009A
+:02204500000099
+:02204600000098
+:02204700000097
+:02204800000096
+:02204900000095
+:02204A00000094
+:02204B00000093
+:02204C00000092
+:02204D00000091
+:02204E00000090
+:02204F0000008F
+:0220500000008E
+:0220510000008D
+:0220520000008C
+:0220530000008B
+:0220540000008A
+:02205500000089
+:02205600000088
+:02205700000087
+:02205800000086
+:02205900000085
+:02205A00000084
+:02205B00000083
+:02205C00000082
+:02205D00000081
+:02205E00000080
+:02205F0000007F
+:0220600000007E
+:0220610000007D
+:0220620000007C
+:0220630000007B
+:0220640000007A
+:02206500000079
+:02206600000078
+:02206700000077
+:02206800000076
+:02206900000075
+:02206A00000074
+:02206B00000073
+:02206C00000072
+:02206D00000071
+:02206E00000070
+:02206F0000006F
+:0220700000006E
+:0220710000006D
+:0220720000006C
+:0220730000006B
+:0220740000006A
+:02207500000069
+:02207600000068
+:02207700000067
+:02207800000066
+:02207900000065
+:02207A00000064
+:02207B00000063
+:02207C00000062
+:02207D00000061
+:02207E00000060
+:02207F0000005F
+:0220800000005E
+:0220810000005D
+:0220820000005C
+:0220830000005B
+:0220840000005A
+:02208500000059
+:02208600000058
+:02208700000057
+:02208800000056
+:02208900000055
+:02208A00000054
+:02208B00000053
+:02208C00000052
+:02208D00000051
+:02208E00000050
+:02208F0000004F
+:0220900000004E
+:0220910000004D
+:0220920000004C
+:0220930000004B
+:0220940000004A
+:02209500000049
+:02209600000048
+:02209700000047
+:02209800000046
+:02209900000045
+:02209A00000044
+:02209B00000043
+:02209C00000042
+:02209D00000041
+:02209E00000040
+:02209F0000003F
+:0220A00000003E
+:0220A10000003D
+:0220A20000003C
+:0220A30000003B
+:0220A40000003A
+:0220A500000039
+:0220A600000038
+:0220A700000037
+:0220A800000036
+:0220A900000035
+:0220AA00000034
+:0220AB00000033
+:0220AC00000032
+:0220AD00000031
+:0220AE00000030
+:0220AF0000002F
+:0220B00000002E
+:0220B10000002D
+:0220B20000002C
+:0220B30000002B
+:0220B40000002A
+:0220B500000029
+:0220B600000028
+:0220B700000027
+:0220B800000026
+:0220B900000025
+:0220BA00000024
+:0220BB00000023
+:0220BC00000022
+:0220BD00000021
+:0220BE00000020
+:0220BF0000001F
+:0220C00000001E
+:0220C10000001D
+:0220C20000001C
+:0220C30000001B
+:0220C40000001A
+:0220C500000019
+:0220C600000018
+:0220C700000017
+:0220C800000016
+:0220C900000015
+:0220CA00000014
+:0220CB00000013
+:0220CC00000012
+:0220CD00000011
+:0220CE00000010
+:0220CF0000000F
+:0220D00000000E
+:0220D10000000D
+:0220D20000000C
+:0220D30000000B
+:0220D40000000A
+:0220D500000009
+:0220D600000008
+:0220D700000007
+:0220D800000006
+:0220D900000005
+:0220DA00000004
+:0220DB00000003
+:0220DC00000002
+:0220DD00000001
+:0220DE00000000
+:0220DF000000FF
+:0220E0000000FE
+:0220E1000000FD
+:0220E2000000FC
+:0220E3000000FB
+:0220E4000000FA
+:0220E5000000F9
+:0220E6000000F8
+:0220E7000000F7
+:0220E8000000F6
+:0220E9000000F5
+:0220EA000000F4
+:0220EB000000F3
+:0220EC000000F2
+:0220ED000000F1
+:0220EE000000F0
+:0220EF000000EF
+:0220F0000000EE
+:0220F1000000ED
+:0220F2000000EC
+:0220F3000000EB
+:0220F4000000EA
+:0220F5000000E9
+:0220F6000000E8
+:0220F7000000E7
+:0220F8000000E6
+:0220F9000000E5
+:0220FA000000E4
+:0220FB000000E3
+:0220FC000000E2
+:0220FD000000E1
+:0220FE000000E0
+:0220FF000000DF
+:022100000000DD
+:022101000000DC
+:022102000000DB
+:022103000000DA
+:022104000000D9
+:022105000000D8
+:022106000000D7
+:022107000000D6
+:022108000000D5
+:022109000000D4
+:02210A000000D3
+:02210B000000D2
+:02210C000000D1
+:02210D000000D0
+:02210E000000CF
+:02210F000000CE
+:022110000000CD
+:022111000000CC
+:022112000000CB
+:022113000000CA
+:022114000000C9
+:022115000000C8
+:022116000000C7
+:022117000000C6
+:022118000000C5
+:022119000000C4
+:02211A000000C3
+:02211B000000C2
+:02211C000000C1
+:02211D000000C0
+:02211E000000BF
+:02211F000000BE
+:022120000000BD
+:022121000000BC
+:022122000000BB
+:022123000000BA
+:022124000000B9
+:022125000000B8
+:022126000000B7
+:022127000000B6
+:022128000000B5
+:022129000000B4
+:02212A000000B3
+:02212B000000B2
+:02212C000000B1
+:02212D000000B0
+:02212E000000AF
+:02212F000000AE
+:022130000000AD
+:022131000000AC
+:022132000000AB
+:022133000000AA
+:022134000000A9
+:022135000000A8
+:022136000000A7
+:022137000000A6
+:022138000000A5
+:022139000000A4
+:02213A000000A3
+:02213B000000A2
+:02213C000000A1
+:02213D000000A0
+:02213E0000009F
+:02213F0000009E
+:0221400000009D
+:0221410000009C
+:0221420000009B
+:0221430000009A
+:02214400000099
+:02214500000098
+:02214600000097
+:02214700000096
+:02214800000095
+:02214900000094
+:02214A00000093
+:02214B00000092
+:02214C00000091
+:02214D00000090
+:02214E0000008F
+:02214F0000008E
+:0221500000008D
+:0221510000008C
+:0221520000008B
+:0221530000008A
+:02215400000089
+:02215500000088
+:02215600000087
+:02215700000086
+:02215800000085
+:02215900000084
+:02215A00000083
+:02215B00000082
+:02215C00000081
+:02215D00000080
+:02215E0000007F
+:02215F0000007E
+:0221600000007D
+:0221610000007C
+:0221620000007B
+:0221630000007A
+:02216400000079
+:02216500000078
+:02216600000077
+:02216700000076
+:02216800000075
+:02216900000074
+:02216A00000073
+:02216B00000072
+:02216C00000071
+:02216D00000070
+:02216E0000006F
+:02216F0000006E
+:0221700000006D
+:0221710000006C
+:0221720000006B
+:0221730000006A
+:02217400000069
+:02217500000068
+:02217600000067
+:02217700000066
+:02217800000065
+:02217900000064
+:02217A00000063
+:02217B00000062
+:02217C00000061
+:02217D00000060
+:02217E0000005F
+:02217F0000005E
+:0221800000005D
+:0221810000005C
+:0221820000005B
+:0221830000005A
+:02218400000059
+:02218500000058
+:02218600000057
+:02218700000056
+:02218800000055
+:02218900000054
+:02218A00000053
+:02218B00000052
+:02218C00000051
+:02218D00000050
+:02218E0000004F
+:02218F0000004E
+:0221900000004D
+:0221910000004C
+:0221920000004B
+:0221930000004A
+:02219400000049
+:02219500000048
+:02219600000047
+:02219700000046
+:02219800000045
+:02219900000044
+:02219A00000043
+:02219B00000042
+:02219C00000041
+:02219D00000040
+:02219E0000003F
+:02219F0000003E
+:0221A00000003D
+:0221A10000003C
+:0221A20000003B
+:0221A30000003A
+:0221A400000039
+:0221A500000038
+:0221A600000037
+:0221A700000036
+:0221A800000035
+:0221A900000034
+:0221AA00000033
+:0221AB00000032
+:0221AC00000031
+:0221AD00000030
+:0221AE0000002F
+:0221AF0000002E
+:0221B00000002D
+:0221B10000002C
+:0221B20000002B
+:0221B30000002A
+:0221B400000029
+:0221B500000028
+:0221B600000027
+:0221B700000026
+:0221B800000025
+:0221B900000024
+:0221BA00000023
+:0221BB00000022
+:0221BC00000021
+:0221BD00000020
+:0221BE0000001F
+:0221BF0000001E
+:0221C00000001D
+:0221C10000001C
+:0221C20000001B
+:0221C30000001A
+:0221C400000019
+:0221C500000018
+:0221C600000017
+:0221C700000016
+:0221C800000015
+:0221C900000014
+:0221CA00000013
+:0221CB00000012
+:0221CC00000011
+:0221CD00000010
+:0221CE0000000F
+:0221CF0000000E
+:0221D00000000D
+:0221D10000000C
+:0221D20000000B
+:0221D30000000A
+:0221D400000009
+:0221D500000008
+:0221D600000007
+:0221D700000006
+:0221D800000005
+:0221D900000004
+:0221DA00000003
+:0221DB00000002
+:0221DC00000001
+:0221DD00000000
+:0221DE000000FF
+:0221DF000000FE
+:0221E0000000FD
+:0221E1000000FC
+:0221E2000000FB
+:0221E3000000FA
+:0221E4000000F9
+:0221E5000000F8
+:0221E6000000F7
+:0221E7000000F6
+:0221E8000000F5
+:0221E9000000F4
+:0221EA000000F3
+:0221EB000000F2
+:0221EC000000F1
+:0221ED000000F0
+:0221EE000000EF
+:0221EF000000EE
+:0221F0000000ED
+:0221F1000000EC
+:0221F2000000EB
+:0221F3000000EA
+:0221F4000000E9
+:0221F5000000E8
+:0221F6000000E7
+:0221F7000000E6
+:0221F8000000E5
+:0221F9000000E4
+:0221FA000000E3
+:0221FB000000E2
+:0221FC000000E1
+:0221FD000000E0
+:0221FE000000DF
+:0221FF000000DE
+:022200000000DC
+:022201000000DB
+:022202000000DA
+:022203000000D9
+:022204000000D8
+:022205000000D7
+:022206000000D6
+:022207000000D5
+:022208000000D4
+:022209000000D3
+:02220A000000D2
+:02220B000000D1
+:02220C000000D0
+:02220D000000CF
+:02220E000000CE
+:02220F000000CD
+:022210000000CC
+:022211000000CB
+:022212000000CA
+:022213000000C9
+:022214000000C8
+:022215000000C7
+:022216000000C6
+:022217000000C5
+:022218000000C4
+:022219000000C3
+:02221A000000C2
+:02221B000000C1
+:02221C000000C0
+:02221D000000BF
+:02221E000000BE
+:02221F000000BD
+:022220000000BC
+:022221000000BB
+:022222000000BA
+:022223000000B9
+:022224000000B8
+:022225000000B7
+:022226000000B6
+:022227000000B5
+:022228000000B4
+:022229000000B3
+:02222A000000B2
+:02222B000000B1
+:02222C000000B0
+:02222D000000AF
+:02222E000000AE
+:02222F000000AD
+:022230000000AC
+:022231000000AB
+:022232000000AA
+:022233000000A9
+:022234000000A8
+:022235000000A7
+:022236000000A6
+:022237000000A5
+:022238000000A4
+:022239000000A3
+:02223A000000A2
+:02223B000000A1
+:02223C000000A0
+:02223D0000009F
+:02223E0000009E
+:02223F0000009D
+:0222400000009C
+:0222410000009B
+:0222420000009A
+:02224300000099
+:02224400000098
+:02224500000097
+:02224600000096
+:02224700000095
+:02224800000094
+:02224900000093
+:02224A00000092
+:02224B00000091
+:02224C00000090
+:02224D0000008F
+:02224E0000008E
+:02224F0000008D
+:0222500000008C
+:0222510000008B
+:0222520000008A
+:02225300000089
+:02225400000088
+:02225500000087
+:02225600000086
+:02225700000085
+:02225800000084
+:02225900000083
+:02225A00000082
+:02225B00000081
+:02225C00000080
+:02225D0000007F
+:02225E0000007E
+:02225F0000007D
+:0222600000007C
+:0222610000007B
+:0222620000007A
+:02226300000079
+:02226400000078
+:02226500000077
+:02226600000076
+:02226700000075
+:02226800000074
+:02226900000073
+:02226A00000072
+:02226B00000071
+:02226C00000070
+:02226D0000006F
+:02226E0000006E
+:02226F0000006D
+:0222700000006C
+:0222710000006B
+:0222720000006A
+:02227300000069
+:02227400000068
+:02227500000067
+:02227600000066
+:02227700000065
+:02227800000064
+:02227900000063
+:02227A00000062
+:02227B00000061
+:02227C00000060
+:02227D0000005F
+:02227E0000005E
+:02227F0000005D
+:0222800000005C
+:0222810000005B
+:0222820000005A
+:02228300000059
+:02228400000058
+:02228500000057
+:02228600000056
+:02228700000055
+:02228800000054
+:02228900000053
+:02228A00000052
+:02228B00000051
+:02228C00000050
+:02228D0000004F
+:02228E0000004E
+:02228F0000004D
+:0222900000004C
+:0222910000004B
+:0222920000004A
+:02229300000049
+:02229400000048
+:02229500000047
+:02229600000046
+:02229700000045
+:02229800000044
+:02229900000043
+:02229A00000042
+:02229B00000041
+:02229C00000040
+:02229D0000003F
+:02229E0000003E
+:02229F0000003D
+:0222A00000003C
+:0222A10000003B
+:0222A20000003A
+:0222A300000039
+:0222A400000038
+:0222A500000037
+:0222A600000036
+:0222A700000035
+:0222A800000034
+:0222A900000033
+:0222AA00000032
+:0222AB00000031
+:0222AC00000030
+:0222AD0000002F
+:0222AE0000002E
+:0222AF0000002D
+:0222B00000002C
+:0222B10000002B
+:0222B20000002A
+:0222B300000029
+:0222B400000028
+:0222B500000027
+:0222B600000026
+:0222B700000025
+:0222B800000024
+:0222B900000023
+:0222BA00000022
+:0222BB00000021
+:0222BC00000020
+:0222BD0000001F
+:0222BE0000001E
+:0222BF0000001D
+:0222C00000001C
+:0222C10000001B
+:0222C20000001A
+:0222C300000019
+:0222C400000018
+:0222C500000017
+:0222C600000016
+:0222C700000015
+:0222C800000014
+:0222C900000013
+:0222CA00000012
+:0222CB00000011
+:0222CC00000010
+:0222CD0000000F
+:0222CE0000000E
+:0222CF0000000D
+:0222D00000000C
+:0222D10000000B
+:0222D20000000A
+:0222D300000009
+:0222D400000008
+:0222D500000007
+:0222D600000006
+:0222D700000005
+:0222D800000004
+:0222D900000003
+:0222DA00000002
+:0222DB00000001
+:0222DC00000000
+:0222DD000000FF
+:0222DE000000FE
+:0222DF000000FD
+:0222E0000000FC
+:0222E1000000FB
+:0222E2000000FA
+:0222E3000000F9
+:0222E4000000F8
+:0222E5000000F7
+:0222E6000000F6
+:0222E7000000F5
+:0222E8000000F4
+:0222E9000000F3
+:0222EA000000F2
+:0222EB000000F1
+:0222EC000000F0
+:0222ED000000EF
+:0222EE000000EE
+:0222EF000000ED
+:0222F0000000EC
+:0222F1000000EB
+:0222F2000000EA
+:0222F3000000E9
+:0222F4000000E8
+:0222F5000000E7
+:0222F6000000E6
+:0222F7000000E5
+:0222F8000000E4
+:0222F9000000E3
+:0222FA000000E2
+:0222FB000000E1
+:0222FC000000E0
+:0222FD000000DF
+:0222FE000000DE
+:0222FF000000DD
+:022300000000DB
+:022301000000DA
+:022302000000D9
+:022303000000D8
+:022304000000D7
+:022305000000D6
+:022306000000D5
+:022307000000D4
+:022308000000D3
+:022309000000D2
+:02230A000000D1
+:02230B000000D0
+:02230C000000CF
+:02230D000000CE
+:02230E000000CD
+:02230F000000CC
+:022310000000CB
+:022311000000CA
+:022312000000C9
+:022313000000C8
+:022314000000C7
+:022315000000C6
+:022316000000C5
+:022317000000C4
+:022318000000C3
+:022319000000C2
+:02231A000000C1
+:02231B000000C0
+:02231C000000BF
+:02231D000000BE
+:02231E000000BD
+:02231F000000BC
+:022320000000BB
+:022321000000BA
+:022322000000B9
+:022323000000B8
+:022324000000B7
+:022325000000B6
+:022326000000B5
+:022327000000B4
+:022328000000B3
+:022329000000B2
+:02232A000000B1
+:02232B000000B0
+:02232C000000AF
+:02232D000000AE
+:02232E000000AD
+:02232F000000AC
+:022330000000AB
+:022331000000AA
+:022332000000A9
+:022333000000A8
+:022334000000A7
+:022335000000A6
+:022336000000A5
+:022337000000A4
+:022338000000A3
+:022339000000A2
+:02233A000000A1
+:02233B000000A0
+:02233C0000009F
+:02233D0000009E
+:02233E0000009D
+:02233F0000009C
+:0223400000009B
+:0223410000009A
+:02234200000099
+:02234300000098
+:02234400000097
+:02234500000096
+:02234600000095
+:02234700000094
+:02234800000093
+:02234900000092
+:02234A00000091
+:02234B00000090
+:02234C0000008F
+:02234D0000008E
+:02234E0000008D
+:02234F0000008C
+:0223500000008B
+:0223510000008A
+:02235200000089
+:02235300000088
+:02235400000087
+:02235500000086
+:02235600000085
+:02235700000084
+:02235800000083
+:02235900000082
+:02235A00000081
+:02235B00000080
+:02235C0000007F
+:02235D0000007E
+:02235E0000007D
+:02235F0000007C
+:0223600000007B
+:0223610000007A
+:02236200000079
+:02236300000078
+:02236400000077
+:02236500000076
+:02236600000075
+:02236700000074
+:02236800000073
+:02236900000072
+:02236A00000071
+:02236B00000070
+:02236C0000006F
+:02236D0000006E
+:02236E0000006D
+:02236F0000006C
+:0223700000006B
+:0223710000006A
+:02237200000069
+:02237300000068
+:02237400000067
+:02237500000066
+:02237600000065
+:02237700000064
+:02237800000063
+:02237900000062
+:02237A00000061
+:02237B00000060
+:02237C0000005F
+:02237D0000005E
+:02237E0000005D
+:02237F0000005C
+:0223800000005B
+:0223810000005A
+:02238200000059
+:02238300000058
+:02238400000057
+:02238500000056
+:02238600000055
+:02238700000054
+:02238800000053
+:02238900000052
+:02238A00000051
+:02238B00000050
+:02238C0000004F
+:02238D0000004E
+:02238E0000004D
+:02238F0000004C
+:0223900000004B
+:0223910000004A
+:02239200000049
+:02239300000048
+:02239400000047
+:02239500000046
+:02239600000045
+:02239700000044
+:02239800000043
+:02239900000042
+:02239A00000041
+:02239B00000040
+:02239C0000003F
+:02239D0000003E
+:02239E0000003D
+:02239F0000003C
+:0223A00000003B
+:0223A10000003A
+:0223A200000039
+:0223A300000038
+:0223A400000037
+:0223A500000036
+:0223A600000035
+:0223A700000034
+:0223A800000033
+:0223A900000032
+:0223AA00000031
+:0223AB00000030
+:0223AC0000002F
+:0223AD0000002E
+:0223AE0000002D
+:0223AF0000002C
+:0223B00000002B
+:0223B10000002A
+:0223B200000029
+:0223B300000028
+:0223B400000027
+:0223B500000026
+:0223B600000025
+:0223B700000024
+:0223B800000023
+:0223B900000022
+:0223BA00000021
+:0223BB00000020
+:0223BC0000001F
+:0223BD0000001E
+:0223BE0000001D
+:0223BF0000001C
+:0223C00000001B
+:0223C10000001A
+:0223C200000019
+:0223C300000018
+:0223C400000017
+:0223C500000016
+:0223C600000015
+:0223C700000014
+:0223C800000013
+:0223C900000012
+:0223CA00000011
+:0223CB00000010
+:0223CC0000000F
+:0223CD0000000E
+:0223CE0000000D
+:0223CF0000000C
+:0223D00000000B
+:0223D10000000A
+:0223D200000009
+:0223D300000008
+:0223D400000007
+:0223D500000006
+:0223D600000005
+:0223D700000004
+:0223D800000003
+:0223D900000002
+:0223DA00000001
+:0223DB00000000
+:0223DC000000FF
+:0223DD000000FE
+:0223DE000000FD
+:0223DF000000FC
+:0223E0000000FB
+:0223E1000000FA
+:0223E2000000F9
+:0223E3000000F8
+:0223E4000000F7
+:0223E5000000F6
+:0223E6000000F5
+:0223E7000000F4
+:0223E8000000F3
+:0223E9000000F2
+:0223EA000000F1
+:0223EB000000F0
+:0223EC000000EF
+:0223ED000000EE
+:0223EE000000ED
+:0223EF000000EC
+:0223F0000000EB
+:0223F1000000EA
+:0223F2000000E9
+:0223F3000000E8
+:0223F4000000E7
+:0223F5000000E6
+:0223F6000000E5
+:0223F7000000E4
+:0223F8000000E3
+:0223F9000000E2
+:0223FA000000E1
+:0223FB000000E0
+:0223FC000000DF
+:0223FD000000DE
+:0223FE000000DD
+:0223FF000000DC
+:022400000000DA
+:022401000000D9
+:022402000000D8
+:022403000000D7
+:022404000000D6
+:022405000000D5
+:022406000000D4
+:022407000000D3
+:022408000000D2
+:022409000000D1
+:02240A000000D0
+:02240B000000CF
+:02240C000000CE
+:02240D000000CD
+:02240E000000CC
+:02240F000000CB
+:022410000000CA
+:022411000000C9
+:022412000000C8
+:022413000000C7
+:022414000000C6
+:022415000000C5
+:022416000000C4
+:022417000000C3
+:022418000000C2
+:022419000000C1
+:02241A000000C0
+:02241B000000BF
+:02241C000000BE
+:02241D000000BD
+:02241E000000BC
+:02241F000000BB
+:022420000000BA
+:022421000000B9
+:022422000000B8
+:022423000000B7
+:022424000000B6
+:022425000000B5
+:022426000000B4
+:022427000000B3
+:022428000000B2
+:022429000000B1
+:02242A000000B0
+:02242B000000AF
+:02242C000000AE
+:02242D000000AD
+:02242E000000AC
+:02242F000000AB
+:022430000000AA
+:022431000000A9
+:022432000000A8
+:022433000000A7
+:022434000000A6
+:022435000000A5
+:022436000000A4
+:022437000000A3
+:022438000000A2
+:022439000000A1
+:02243A000000A0
+:02243B0000009F
+:02243C0000009E
+:02243D0000009D
+:02243E0000009C
+:02243F0000009B
+:0224400000009A
+:02244100000099
+:02244200000098
+:02244300000097
+:02244400000096
+:02244500000095
+:02244600000094
+:02244700000093
+:02244800000092
+:02244900000091
+:02244A00000090
+:02244B0000008F
+:02244C0000008E
+:02244D0000008D
+:02244E0000008C
+:02244F0000008B
+:0224500000008A
+:02245100000089
+:02245200000088
+:02245300000087
+:02245400000086
+:02245500000085
+:02245600000084
+:02245700000083
+:02245800000082
+:02245900000081
+:02245A00000080
+:02245B0000007F
+:02245C0000007E
+:02245D0000007D
+:02245E0000007C
+:02245F0000007B
+:0224600000007A
+:02246100000079
+:02246200000078
+:02246300000077
+:02246400000076
+:02246500000075
+:02246600000074
+:02246700000073
+:02246800000072
+:02246900000071
+:02246A00000070
+:02246B0000006F
+:02246C0000006E
+:02246D0000006D
+:02246E0000006C
+:02246F0000006B
+:0224700000006A
+:02247100000069
+:02247200000068
+:02247300000067
+:02247400000066
+:02247500000065
+:02247600000064
+:02247700000063
+:02247800000062
+:02247900000061
+:02247A00000060
+:02247B0000005F
+:02247C0000005E
+:02247D0000005D
+:02247E0000005C
+:02247F0000005B
+:0224800000005A
+:02248100000059
+:02248200000058
+:02248300000057
+:02248400000056
+:02248500000055
+:02248600000054
+:02248700000053
+:02248800000052
+:02248900000051
+:02248A00000050
+:02248B0000004F
+:02248C0000004E
+:02248D0000004D
+:02248E0000004C
+:02248F0000004B
+:0224900000004A
+:02249100000049
+:02249200000048
+:02249300000047
+:02249400000046
+:02249500000045
+:02249600000044
+:02249700000043
+:02249800000042
+:02249900000041
+:02249A00000040
+:02249B0000003F
+:02249C0000003E
+:02249D0000003D
+:02249E0000003C
+:02249F0000003B
+:0224A00000003A
+:0224A100000039
+:0224A200000038
+:0224A300000037
+:0224A400000036
+:0224A500000035
+:0224A600000034
+:0224A700000033
+:0224A800000032
+:0224A900000031
+:0224AA00000030
+:0224AB0000002F
+:0224AC0000002E
+:0224AD0000002D
+:0224AE0000002C
+:0224AF0000002B
+:0224B00000002A
+:0224B100000029
+:0224B200000028
+:0224B300000027
+:0224B400000026
+:0224B500000025
+:0224B600000024
+:0224B700000023
+:0224B800000022
+:0224B900000021
+:0224BA00000020
+:0224BB0000001F
+:0224BC0000001E
+:0224BD0000001D
+:0224BE0000001C
+:0224BF0000001B
+:0224C00000001A
+:0224C100000019
+:0224C200000018
+:0224C300000017
+:0224C400000016
+:0224C500000015
+:0224C600000014
+:0224C700000013
+:0224C800000012
+:0224C900000011
+:0224CA00000010
+:0224CB0000000F
+:0224CC0000000E
+:0224CD0000000D
+:0224CE0000000C
+:0224CF0000000B
+:0224D00000000A
+:0224D100000009
+:0224D200000008
+:0224D300000007
+:0224D400000006
+:0224D500000005
+:0224D600000004
+:0224D700000003
+:0224D800000002
+:0224D900000001
+:0224DA00000000
+:0224DB000000FF
+:0224DC000000FE
+:0224DD000000FD
+:0224DE000000FC
+:0224DF000000FB
+:0224E0000000FA
+:0224E1000000F9
+:0224E2000000F8
+:0224E3000000F7
+:0224E4000000F6
+:0224E5000000F5
+:0224E6000000F4
+:0224E7000000F3
+:0224E8000000F2
+:0224E9000000F1
+:0224EA000000F0
+:0224EB000000EF
+:0224EC000000EE
+:0224ED000000ED
+:0224EE000000EC
+:0224EF000000EB
+:0224F0000000EA
+:0224F1000000E9
+:0224F2000000E8
+:0224F3000000E7
+:0224F4000000E6
+:0224F5000000E5
+:0224F6000000E4
+:0224F7000000E3
+:0224F8000000E2
+:0224F9000000E1
+:0224FA000000E0
+:0224FB000000DF
+:0224FC000000DE
+:0224FD000000DD
+:0224FE000000DC
+:0224FF000000DB
+:022500000000D9
+:022501000000D8
+:022502000000D7
+:022503000000D6
+:022504000000D5
+:022505000000D4
+:022506000000D3
+:022507000000D2
+:022508000000D1
+:022509000000D0
+:02250A000000CF
+:02250B000000CE
+:02250C000000CD
+:02250D000000CC
+:02250E000000CB
+:02250F000000CA
+:022510000000C9
+:022511000000C8
+:022512000000C7
+:022513000000C6
+:022514000000C5
+:022515000000C4
+:022516000000C3
+:022517000000C2
+:022518000000C1
+:022519000000C0
+:02251A000000BF
+:02251B000000BE
+:02251C000000BD
+:02251D000000BC
+:02251E000000BB
+:02251F000000BA
+:022520000000B9
+:022521000000B8
+:022522000000B7
+:022523000000B6
+:022524000000B5
+:022525000000B4
+:022526000000B3
+:022527000000B2
+:022528000000B1
+:022529000000B0
+:02252A000000AF
+:02252B000000AE
+:02252C000000AD
+:02252D000000AC
+:02252E000000AB
+:02252F000000AA
+:022530000000A9
+:022531000000A8
+:022532000000A7
+:022533000000A6
+:022534000000A5
+:022535000000A4
+:022536000000A3
+:022537000000A2
+:022538000000A1
+:022539000000A0
+:02253A0000009F
+:02253B0000009E
+:02253C0000009D
+:02253D0000009C
+:02253E0000009B
+:02253F0000009A
+:02254000000099
+:02254100000098
+:02254200000097
+:02254300000096
+:02254400000095
+:02254500000094
+:02254600000093
+:02254700000092
+:02254800000091
+:02254900000090
+:02254A0000008F
+:02254B0000008E
+:02254C0000008D
+:02254D0000008C
+:02254E0000008B
+:02254F0000008A
+:02255000000089
+:02255100000088
+:02255200000087
+:02255300000086
+:02255400000085
+:02255500000084
+:02255600000083
+:02255700000082
+:02255800000081
+:02255900000080
+:02255A0000007F
+:02255B0000007E
+:02255C0000007D
+:02255D0000007C
+:02255E0000007B
+:02255F0000007A
+:02256000000079
+:02256100000078
+:02256200000077
+:02256300000076
+:02256400000075
+:02256500000074
+:02256600000073
+:02256700000072
+:02256800000071
+:02256900000070
+:02256A0000006F
+:02256B0000006E
+:02256C0000006D
+:02256D0000006C
+:02256E0000006B
+:02256F0000006A
+:02257000000069
+:02257100000068
+:02257200000067
+:02257300000066
+:02257400000065
+:02257500000064
+:02257600000063
+:02257700000062
+:02257800000061
+:02257900000060
+:02257A0000005F
+:02257B0000005E
+:02257C0000005D
+:02257D0000005C
+:02257E0000005B
+:02257F0000005A
+:02258000000059
+:02258100000058
+:02258200000057
+:02258300000056
+:02258400000055
+:02258500000054
+:02258600000053
+:02258700000052
+:02258800000051
+:02258900000050
+:02258A0000004F
+:02258B0000004E
+:02258C0000004D
+:02258D0000004C
+:02258E0000004B
+:02258F0000004A
+:02259000000049
+:02259100000048
+:02259200000047
+:02259300000046
+:02259400000045
+:02259500000044
+:02259600000043
+:02259700000042
+:02259800000041
+:02259900000040
+:02259A0000003F
+:02259B0000003E
+:02259C0000003D
+:02259D0000003C
+:02259E0000003B
+:02259F0000003A
+:0225A000000039
+:0225A100000038
+:0225A200000037
+:0225A300000036
+:0225A400000035
+:0225A500000034
+:0225A600000033
+:0225A700000032
+:0225A800000031
+:0225A900000030
+:0225AA0000002F
+:0225AB0000002E
+:0225AC0000002D
+:0225AD0000002C
+:0225AE0000002B
+:0225AF0000002A
+:0225B000000029
+:0225B100000028
+:0225B200000027
+:0225B300000026
+:0225B400000025
+:0225B500000024
+:0225B600000023
+:0225B700000022
+:0225B800000021
+:0225B900000020
+:0225BA0000001F
+:0225BB0000001E
+:0225BC0000001D
+:0225BD0000001C
+:0225BE0000001B
+:0225BF0000001A
+:0225C000000019
+:0225C100000018
+:0225C200000017
+:0225C300000016
+:0225C400000015
+:0225C500000014
+:0225C600000013
+:0225C700000012
+:0225C800000011
+:0225C900000010
+:0225CA0000000F
+:0225CB0000000E
+:0225CC0000000D
+:0225CD0000000C
+:0225CE0000000B
+:0225CF0000000A
+:0225D000000009
+:0225D100000008
+:0225D200000007
+:0225D300000006
+:0225D400000005
+:0225D500000004
+:0225D600000003
+:0225D700000002
+:0225D800000001
+:0225D900000000
+:0225DA000000FF
+:0225DB000000FE
+:0225DC000000FD
+:0225DD000000FC
+:0225DE000000FB
+:0225DF000000FA
+:0225E0000000F9
+:0225E1000000F8
+:0225E2000000F7
+:0225E3000000F6
+:0225E4000000F5
+:0225E5000000F4
+:0225E6000000F3
+:0225E7000000F2
+:0225E8000000F1
+:0225E9000000F0
+:0225EA000000EF
+:0225EB000000EE
+:0225EC000000ED
+:0225ED000000EC
+:0225EE000000EB
+:0225EF000000EA
+:0225F0000000E9
+:0225F1000000E8
+:0225F2000000E7
+:0225F3000000E6
+:0225F4000000E5
+:0225F5000000E4
+:0225F6000000E3
+:0225F7000000E2
+:0225F8000000E1
+:0225F9000000E0
+:0225FA000000DF
+:0225FB000000DE
+:0225FC000000DD
+:0225FD000000DC
+:0225FE000000DB
+:0225FF000000DA
+:022600000000D8
+:022601000000D7
+:022602000000D6
+:022603000000D5
+:022604000000D4
+:022605000000D3
+:022606000000D2
+:022607000000D1
+:022608000000D0
+:022609000000CF
+:02260A000000CE
+:02260B000000CD
+:02260C000000CC
+:02260D000000CB
+:02260E000000CA
+:02260F000000C9
+:022610000000C8
+:022611000000C7
+:022612000000C6
+:022613000000C5
+:022614000000C4
+:022615000000C3
+:022616000000C2
+:022617000000C1
+:022618000000C0
+:022619000000BF
+:02261A000000BE
+:02261B000000BD
+:02261C000000BC
+:02261D000000BB
+:02261E000000BA
+:02261F000000B9
+:022620000000B8
+:022621000000B7
+:022622000000B6
+:022623000000B5
+:022624000000B4
+:022625000000B3
+:022626000000B2
+:022627000000B1
+:022628000000B0
+:022629000000AF
+:02262A000000AE
+:02262B000000AD
+:02262C000000AC
+:02262D000000AB
+:02262E000000AA
+:02262F000000A9
+:022630000000A8
+:022631000000A7
+:022632000000A6
+:022633000000A5
+:022634000000A4
+:022635000000A3
+:022636000000A2
+:022637000000A1
+:022638000000A0
+:0226390000009F
+:02263A0000009E
+:02263B0000009D
+:02263C0000009C
+:02263D0000009B
+:02263E0000009A
+:02263F00000099
+:02264000000098
+:02264100000097
+:02264200000096
+:02264300000095
+:02264400000094
+:02264500000093
+:02264600000092
+:02264700000091
+:02264800000090
+:0226490000008F
+:02264A0000008E
+:02264B0000008D
+:02264C0000008C
+:02264D0000008B
+:02264E0000008A
+:02264F00000089
+:02265000000088
+:02265100000087
+:02265200000086
+:02265300000085
+:02265400000084
+:02265500000083
+:02265600000082
+:02265700000081
+:02265800000080
+:0226590000007F
+:02265A0000007E
+:02265B0000007D
+:02265C0000007C
+:02265D0000007B
+:02265E0000007A
+:02265F00000079
+:02266000000078
+:02266100000077
+:02266200000076
+:02266300000075
+:02266400000074
+:02266500000073
+:02266600000072
+:02266700000071
+:02266800000070
+:0226690000006F
+:02266A0000006E
+:02266B0000006D
+:02266C0000006C
+:02266D0000006B
+:02266E0000006A
+:02266F00000069
+:02267000000068
+:02267100000067
+:02267200000066
+:02267300000065
+:02267400000064
+:02267500000063
+:02267600000062
+:02267700000061
+:02267800000060
+:0226790000005F
+:02267A0000005E
+:02267B0000005D
+:02267C0000005C
+:02267D0000005B
+:02267E0000005A
+:02267F00000059
+:02268000000058
+:02268100000057
+:02268200000056
+:02268300000055
+:02268400000054
+:02268500000053
+:02268600000052
+:02268700000051
+:02268800000050
+:0226890000004F
+:02268A0000004E
+:02268B0000004D
+:02268C0000004C
+:02268D0000004B
+:02268E0000004A
+:02268F00000049
+:02269000000048
+:02269100000047
+:02269200000046
+:02269300000045
+:02269400000044
+:02269500000043
+:02269600000042
+:02269700000041
+:02269800000040
+:0226990000003F
+:02269A0000003E
+:02269B0000003D
+:02269C0000003C
+:02269D0000003B
+:02269E0000003A
+:02269F00000039
+:0226A000000038
+:0226A100000037
+:0226A200000036
+:0226A300000035
+:0226A400000034
+:0226A500000033
+:0226A600000032
+:0226A700000031
+:0226A800000030
+:0226A90000002F
+:0226AA0000002E
+:0226AB0000002D
+:0226AC0000002C
+:0226AD0000002B
+:0226AE0000002A
+:0226AF00000029
+:0226B000000028
+:0226B100000027
+:0226B200000026
+:0226B300000025
+:0226B400000024
+:0226B500000023
+:0226B600000022
+:0226B700000021
+:0226B800000020
+:0226B90000001F
+:0226BA0000001E
+:0226BB0000001D
+:0226BC0000001C
+:0226BD0000001B
+:0226BE0000001A
+:0226BF00000019
+:0226C000000018
+:0226C100000017
+:0226C200000016
+:0226C300000015
+:0226C400000014
+:0226C500000013
+:0226C600000012
+:0226C700000011
+:0226C800000010
+:0226C90000000F
+:0226CA0000000E
+:0226CB0000000D
+:0226CC0000000C
+:0226CD0000000B
+:0226CE0000000A
+:0226CF00000009
+:0226D000000008
+:0226D100000007
+:0226D200000006
+:0226D300000005
+:0226D400000004
+:0226D500000003
+:0226D600000002
+:0226D700000001
+:0226D800000000
+:0226D9000000FF
+:0226DA000000FE
+:0226DB000000FD
+:0226DC000000FC
+:0226DD000000FB
+:0226DE000000FA
+:0226DF000000F9
+:0226E0000000F8
+:0226E1000000F7
+:0226E2000000F6
+:0226E3000000F5
+:0226E4000000F4
+:0226E5000000F3
+:0226E6000000F2
+:0226E7000000F1
+:0226E8000000F0
+:0226E9000000EF
+:0226EA000000EE
+:0226EB000000ED
+:0226EC000000EC
+:0226ED000000EB
+:0226EE000000EA
+:0226EF000000E9
+:0226F0000000E8
+:0226F1000000E7
+:0226F2000000E6
+:0226F3000000E5
+:0226F4000000E4
+:0226F5000000E3
+:0226F6000000E2
+:0226F7000000E1
+:0226F8000000E0
+:0226F9000000DF
+:0226FA000000DE
+:0226FB000000DD
+:0226FC000000DC
+:0226FD000000DB
+:0226FE000000DA
+:0226FF000000D9
+:022700000000D7
+:022701000000D6
+:022702000000D5
+:022703000000D4
+:022704000000D3
+:022705000000D2
+:022706000000D1
+:022707000000D0
+:022708000000CF
+:022709000000CE
+:02270A000000CD
+:02270B000000CC
+:02270C000000CB
+:02270D000000CA
+:02270E000000C9
+:02270F000000C8
+:022710000000C7
+:022711000000C6
+:022712000000C5
+:022713000000C4
+:022714000000C3
+:022715000000C2
+:022716000000C1
+:022717000000C0
+:022718000000BF
+:022719000000BE
+:02271A000000BD
+:02271B000000BC
+:02271C000000BB
+:02271D000000BA
+:02271E000000B9
+:02271F000000B8
+:022720000000B7
+:022721000000B6
+:022722000000B5
+:022723000000B4
+:022724000000B3
+:022725000000B2
+:022726000000B1
+:022727000000B0
+:022728000000AF
+:022729000000AE
+:02272A000000AD
+:02272B000000AC
+:02272C000000AB
+:02272D000000AA
+:02272E000000A9
+:02272F000000A8
+:022730000000A7
+:022731000000A6
+:022732000000A5
+:022733000000A4
+:022734000000A3
+:022735000000A2
+:022736000000A1
+:022737000000A0
+:0227380000009F
+:0227390000009E
+:02273A0000009D
+:02273B0000009C
+:02273C0000009B
+:02273D0000009A
+:02273E00000099
+:02273F00000098
+:02274000000097
+:02274100000096
+:02274200000095
+:02274300000094
+:02274400000093
+:02274500000092
+:02274600000091
+:02274700000090
+:0227480000008F
+:0227490000008E
+:02274A0000008D
+:02274B0000008C
+:02274C0000008B
+:02274D0000008A
+:02274E00000089
+:02274F00000088
+:02275000000087
+:02275100000086
+:02275200000085
+:02275300000084
+:02275400000083
+:02275500000082
+:02275600000081
+:02275700000080
+:0227580000007F
+:0227590000007E
+:02275A0000007D
+:02275B0000007C
+:02275C0000007B
+:02275D0000007A
+:02275E00000079
+:02275F00000078
+:02276000000077
+:02276100000076
+:02276200000075
+:02276300000074
+:02276400000073
+:02276500000072
+:02276600000071
+:02276700000070
+:0227680000006F
+:0227690000006E
+:02276A0000006D
+:02276B0000006C
+:02276C0000006B
+:02276D0000006A
+:02276E00000069
+:02276F00000068
+:02277000000067
+:02277100000066
+:02277200000065
+:02277300000064
+:02277400000063
+:02277500000062
+:02277600000061
+:02277700000060
+:0227780000005F
+:0227790000005E
+:02277A0000005D
+:02277B0000005C
+:02277C0000005B
+:02277D0000005A
+:02277E00000059
+:02277F00000058
+:02278000000057
+:02278100000056
+:02278200000055
+:02278300000054
+:02278400000053
+:02278500000052
+:02278600000051
+:02278700000050
+:0227880000004F
+:0227890000004E
+:02278A0000004D
+:02278B0000004C
+:02278C0000004B
+:02278D0000004A
+:02278E00000049
+:02278F00000048
+:02279000000047
+:02279100000046
+:02279200000045
+:02279300000044
+:02279400000043
+:02279500000042
+:02279600000041
+:02279700000040
+:0227980000003F
+:0227990000003E
+:02279A0000003D
+:02279B0000003C
+:02279C0000003B
+:02279D0000003A
+:02279E00000039
+:02279F00000038
+:0227A000000037
+:0227A100000036
+:0227A200000035
+:0227A300000034
+:0227A400000033
+:0227A500000032
+:0227A600000031
+:0227A700000030
+:0227A80000002F
+:0227A90000002E
+:0227AA0000002D
+:0227AB0000002C
+:0227AC0000002B
+:0227AD0000002A
+:0227AE00000029
+:0227AF00000028
+:0227B000000027
+:0227B100000026
+:0227B200000025
+:0227B300000024
+:0227B400000023
+:0227B500000022
+:0227B600000021
+:0227B700000020
+:0227B80000001F
+:0227B90000001E
+:0227BA0000001D
+:0227BB0000001C
+:0227BC0000001B
+:0227BD0000001A
+:0227BE00000019
+:0227BF00000018
+:0227C000000017
+:0227C100000016
+:0227C200000015
+:0227C300000014
+:0227C400000013
+:0227C500000012
+:0227C600000011
+:0227C700000010
+:0227C80000000F
+:0227C90000000E
+:0227CA0000000D
+:0227CB0000000C
+:0227CC0000000B
+:0227CD0000000A
+:0227CE00000009
+:0227CF00000008
+:0227D000000007
+:0227D100000006
+:0227D200000005
+:0227D300000004
+:0227D400000003
+:0227D500000002
+:0227D600000001
+:0227D700000000
+:0227D8000000FF
+:0227D9000000FE
+:0227DA000000FD
+:0227DB000000FC
+:0227DC000000FB
+:0227DD000000FA
+:0227DE000000F9
+:0227DF000000F8
+:0227E0000000F7
+:0227E1000000F6
+:0227E2000000F5
+:0227E3000000F4
+:0227E4000000F3
+:0227E5000000F2
+:0227E6000000F1
+:0227E7000000F0
+:0227E8000000EF
+:0227E9000000EE
+:0227EA000000ED
+:0227EB000000EC
+:0227EC000000EB
+:0227ED000000EA
+:0227EE000000E9
+:0227EF000000E8
+:0227F0000000E7
+:0227F1000000E6
+:0227F2000000E5
+:0227F3000000E4
+:0227F4000000E3
+:0227F5000000E2
+:0227F6000000E1
+:0227F7000000E0
+:0227F8000000DF
+:0227F9000000DE
+:0227FA000000DD
+:0227FB000000DC
+:0227FC000000DB
+:0227FD000000DA
+:0227FE000000D9
+:0227FF000000D8
+:022800000000D6
+:022801000000D5
+:022802000000D4
+:022803000000D3
+:022804000000D2
+:022805000000D1
+:022806000000D0
+:022807000000CF
+:022808000000CE
+:022809000000CD
+:02280A000000CC
+:02280B000000CB
+:02280C000000CA
+:02280D000000C9
+:02280E000000C8
+:02280F000000C7
+:022810000000C6
+:022811000000C5
+:022812000000C4
+:022813000000C3
+:022814000000C2
+:022815000000C1
+:022816000000C0
+:022817000000BF
+:022818000000BE
+:022819000000BD
+:02281A000000BC
+:02281B000000BB
+:02281C000000BA
+:02281D000000B9
+:02281E000000B8
+:02281F000000B7
+:022820000000B6
+:022821000000B5
+:022822000000B4
+:022823000000B3
+:022824000000B2
+:022825000000B1
+:022826000000B0
+:022827000000AF
+:022828000000AE
+:022829000000AD
+:02282A000000AC
+:02282B000000AB
+:02282C000000AA
+:02282D000000A9
+:02282E000000A8
+:02282F000000A7
+:022830000000A6
+:022831000000A5
+:022832000000A4
+:022833000000A3
+:022834000000A2
+:022835000000A1
+:022836000000A0
+:0228370000009F
+:0228380000009E
+:0228390000009D
+:02283A0000009C
+:02283B0000009B
+:02283C0000009A
+:02283D00000099
+:02283E00000098
+:02283F00000097
+:02284000000096
+:02284100000095
+:02284200000094
+:02284300000093
+:02284400000092
+:02284500000091
+:02284600000090
+:0228470000008F
+:0228480000008E
+:0228490000008D
+:02284A0000008C
+:02284B0000008B
+:02284C0000008A
+:02284D00000089
+:02284E00000088
+:02284F00000087
+:02285000000086
+:02285100000085
+:02285200000084
+:02285300000083
+:02285400000082
+:02285500000081
+:02285600000080
+:0228570000007F
+:0228580000007E
+:0228590000007D
+:02285A0000007C
+:02285B0000007B
+:02285C0000007A
+:02285D00000079
+:02285E00000078
+:02285F00000077
+:02286000000076
+:02286100000075
+:02286200000074
+:02286300000073
+:02286400000072
+:02286500000071
+:02286600000070
+:0228670000006F
+:0228680000006E
+:0228690000006D
+:02286A0000006C
+:02286B0000006B
+:02286C0000006A
+:02286D00000069
+:02286E00000068
+:02286F00000067
+:02287000000066
+:02287100000065
+:02287200000064
+:02287300000063
+:02287400000062
+:02287500000061
+:02287600000060
+:0228770000005F
+:0228780000005E
+:0228790000005D
+:02287A0000005C
+:02287B0000005B
+:02287C0000005A
+:02287D00000059
+:02287E00000058
+:02287F00000057
+:02288000000056
+:02288100000055
+:02288200000054
+:02288300000053
+:02288400000052
+:02288500000051
+:02288600000050
+:0228870000004F
+:0228880000004E
+:0228890000004D
+:02288A0000004C
+:02288B0000004B
+:02288C0000004A
+:02288D00000049
+:02288E00000048
+:02288F00000047
+:02289000000046
+:02289100000045
+:02289200000044
+:02289300000043
+:02289400000042
+:02289500000041
+:02289600000040
+:0228970000003F
+:0228980000003E
+:0228990000003D
+:02289A0000003C
+:02289B0000003B
+:02289C0000003A
+:02289D00000039
+:02289E00000038
+:02289F00000037
+:0228A000000036
+:0228A100000035
+:0228A200000034
+:0228A300000033
+:0228A400000032
+:0228A500000031
+:0228A600000030
+:0228A70000002F
+:0228A80000002E
+:0228A90000002D
+:0228AA0000002C
+:0228AB0000002B
+:0228AC0000002A
+:0228AD00000029
+:0228AE00000028
+:0228AF00000027
+:0228B000000026
+:0228B100000025
+:0228B200000024
+:0228B300000023
+:0228B400000022
+:0228B500000021
+:0228B600000020
+:0228B70000001F
+:0228B80000001E
+:0228B90000001D
+:0228BA0000001C
+:0228BB0000001B
+:0228BC0000001A
+:0228BD00000019
+:0228BE00000018
+:0228BF00000017
+:0228C000000016
+:0228C100000015
+:0228C200000014
+:0228C300000013
+:0228C400000012
+:0228C500000011
+:0228C600000010
+:0228C70000000F
+:0228C80000000E
+:0228C90000000D
+:0228CA0000000C
+:0228CB0000000B
+:0228CC0000000A
+:0228CD00000009
+:0228CE00000008
+:0228CF00000007
+:0228D000000006
+:0228D100000005
+:0228D200000004
+:0228D300000003
+:0228D400000002
+:0228D500000001
+:0228D600000000
+:0228D7000000FF
+:0228D8000000FE
+:0228D9000000FD
+:0228DA000000FC
+:0228DB000000FB
+:0228DC000000FA
+:0228DD000000F9
+:0228DE000000F8
+:0228DF000000F7
+:0228E0000000F6
+:0228E1000000F5
+:0228E2000000F4
+:0228E3000000F3
+:0228E4000000F2
+:0228E5000000F1
+:0228E6000000F0
+:0228E7000000EF
+:0228E8000000EE
+:0228E9000000ED
+:0228EA000000EC
+:0228EB000000EB
+:0228EC000000EA
+:0228ED000000E9
+:0228EE000000E8
+:0228EF000000E7
+:0228F0000000E6
+:0228F1000000E5
+:0228F2000000E4
+:0228F3000000E3
+:0228F4000000E2
+:0228F5000000E1
+:0228F6000000E0
+:0228F7000000DF
+:0228F8000000DE
+:0228F9000000DD
+:0228FA000000DC
+:0228FB000000DB
+:0228FC000000DA
+:0228FD000000D9
+:0228FE000000D8
+:0228FF000000D7
+:022900000000D5
+:022901000000D4
+:022902000000D3
+:022903000000D2
+:022904000000D1
+:022905000000D0
+:022906000000CF
+:022907000000CE
+:022908000000CD
+:022909000000CC
+:02290A000000CB
+:02290B000000CA
+:02290C000000C9
+:02290D000000C8
+:02290E000000C7
+:02290F000000C6
+:022910000000C5
+:022911000000C4
+:022912000000C3
+:022913000000C2
+:022914000000C1
+:022915000000C0
+:022916000000BF
+:022917000000BE
+:022918000000BD
+:022919000000BC
+:02291A000000BB
+:02291B000000BA
+:02291C000000B9
+:02291D000000B8
+:02291E000000B7
+:02291F000000B6
+:022920000000B5
+:022921000000B4
+:022922000000B3
+:022923000000B2
+:022924000000B1
+:022925000000B0
+:022926000000AF
+:022927000000AE
+:022928000000AD
+:022929000000AC
+:02292A000000AB
+:02292B000000AA
+:02292C000000A9
+:02292D000000A8
+:02292E000000A7
+:02292F000000A6
+:022930000000A5
+:022931000000A4
+:022932000000A3
+:022933000000A2
+:022934000000A1
+:022935000000A0
+:0229360000009F
+:0229370000009E
+:0229380000009D
+:0229390000009C
+:02293A0000009B
+:02293B0000009A
+:02293C00000099
+:02293D00000098
+:02293E00000097
+:02293F00000096
+:02294000000095
+:02294100000094
+:02294200000093
+:02294300000092
+:02294400000091
+:02294500000090
+:0229460000008F
+:0229470000008E
+:0229480000008D
+:0229490000008C
+:02294A0000008B
+:02294B0000008A
+:02294C00000089
+:02294D00000088
+:02294E00000087
+:02294F00000086
+:02295000000085
+:02295100000084
+:02295200000083
+:02295300000082
+:02295400000081
+:02295500000080
+:0229560000007F
+:0229570000007E
+:0229580000007D
+:0229590000007C
+:02295A0000007B
+:02295B0000007A
+:02295C00000079
+:02295D00000078
+:02295E00000077
+:02295F00000076
+:02296000000075
+:02296100000074
+:02296200000073
+:02296300000072
+:02296400000071
+:02296500000070
+:0229660000006F
+:0229670000006E
+:0229680000006D
+:0229690000006C
+:02296A0000006B
+:02296B0000006A
+:02296C00000069
+:02296D00000068
+:02296E00000067
+:02296F00000066
+:02297000000065
+:02297100000064
+:02297200000063
+:02297300000062
+:02297400000061
+:02297500000060
+:0229760000005F
+:0229770000005E
+:0229780000005D
+:0229790000005C
+:02297A0000005B
+:02297B0000005A
+:02297C00000059
+:02297D00000058
+:02297E00000057
+:02297F00000056
+:02298000000055
+:02298100000054
+:02298200000053
+:02298300000052
+:02298400000051
+:02298500000050
+:0229860000004F
+:0229870000004E
+:0229880000004D
+:0229890000004C
+:02298A0000004B
+:02298B0000004A
+:02298C00000049
+:02298D00000048
+:02298E00000047
+:02298F00000046
+:02299000000045
+:02299100000044
+:02299200000043
+:02299300000042
+:02299400000041
+:02299500000040
+:0229960000003F
+:0229970000003E
+:0229980000003D
+:0229990000003C
+:02299A0000003B
+:02299B0000003A
+:02299C00000039
+:02299D00000038
+:02299E00000037
+:02299F00000036
+:0229A000000035
+:0229A100000034
+:0229A200000033
+:0229A300000032
+:0229A400000031
+:0229A500000030
+:0229A60000002F
+:0229A70000002E
+:0229A80000002D
+:0229A90000002C
+:0229AA0000002B
+:0229AB0000002A
+:0229AC00000029
+:0229AD00000028
+:0229AE00000027
+:0229AF00000026
+:0229B000000025
+:0229B100000024
+:0229B200000023
+:0229B300000022
+:0229B400000021
+:0229B500000020
+:0229B60000001F
+:0229B70000001E
+:0229B80000001D
+:0229B90000001C
+:0229BA0000001B
+:0229BB0000001A
+:0229BC00000019
+:0229BD00000018
+:0229BE00000017
+:0229BF00000016
+:0229C000000015
+:0229C100000014
+:0229C200000013
+:0229C300000012
+:0229C400000011
+:0229C500000010
+:0229C60000000F
+:0229C70000000E
+:0229C80000000D
+:0229C90000000C
+:0229CA0000000B
+:0229CB0000000A
+:0229CC00000009
+:0229CD00000008
+:0229CE00000007
+:0229CF00000006
+:0229D000000005
+:0229D100000004
+:0229D200000003
+:0229D300000002
+:0229D400000001
+:0229D500000000
+:0229D6000000FF
+:0229D7000000FE
+:0229D8000000FD
+:0229D9000000FC
+:0229DA000000FB
+:0229DB000000FA
+:0229DC000000F9
+:0229DD000000F8
+:0229DE000000F7
+:0229DF000000F6
+:0229E0000000F5
+:0229E1000000F4
+:0229E2000000F3
+:0229E3000000F2
+:0229E4000000F1
+:0229E5000000F0
+:0229E6000000EF
+:0229E7000000EE
+:0229E8000000ED
+:0229E9000000EC
+:0229EA000000EB
+:0229EB000000EA
+:0229EC000000E9
+:0229ED000000E8
+:0229EE000000E7
+:0229EF000000E6
+:0229F0000000E5
+:0229F1000000E4
+:0229F2000000E3
+:0229F3000000E2
+:0229F4000000E1
+:0229F5000000E0
+:0229F6000000DF
+:0229F7000000DE
+:0229F8000000DD
+:0229F9000000DC
+:0229FA000000DB
+:0229FB000000DA
+:0229FC000000D9
+:0229FD000000D8
+:0229FE000000D7
+:0229FF000000D6
+:022A00000000D4
+:022A01000000D3
+:022A02000000D2
+:022A03000000D1
+:022A04000000D0
+:022A05000000CF
+:022A06000000CE
+:022A07000000CD
+:022A08000000CC
+:022A09000000CB
+:022A0A000000CA
+:022A0B000000C9
+:022A0C000000C8
+:022A0D000000C7
+:022A0E000000C6
+:022A0F000000C5
+:022A10000000C4
+:022A11000000C3
+:022A12000000C2
+:022A13000000C1
+:022A14000000C0
+:022A15000000BF
+:022A16000000BE
+:022A17000000BD
+:022A18000000BC
+:022A19000000BB
+:022A1A000000BA
+:022A1B000000B9
+:022A1C000000B8
+:022A1D000000B7
+:022A1E000000B6
+:022A1F000000B5
+:022A20000000B4
+:022A21000000B3
+:022A22000000B2
+:022A23000000B1
+:022A24000000B0
+:022A25000000AF
+:022A26000000AE
+:022A27000000AD
+:022A28000000AC
+:022A29000000AB
+:022A2A000000AA
+:022A2B000000A9
+:022A2C000000A8
+:022A2D000000A7
+:022A2E000000A6
+:022A2F000000A5
+:022A30000000A4
+:022A31000000A3
+:022A32000000A2
+:022A33000000A1
+:022A34000000A0
+:022A350000009F
+:022A360000009E
+:022A370000009D
+:022A380000009C
+:022A390000009B
+:022A3A0000009A
+:022A3B00000099
+:022A3C00000098
+:022A3D00000097
+:022A3E00000096
+:022A3F00000095
+:022A4000000094
+:022A4100000093
+:022A4200000092
+:022A4300000091
+:022A4400000090
+:022A450000008F
+:022A460000008E
+:022A470000008D
+:022A480000008C
+:022A490000008B
+:022A4A0000008A
+:022A4B00000089
+:022A4C00000088
+:022A4D00000087
+:022A4E00000086
+:022A4F00000085
+:022A5000000084
+:022A5100000083
+:022A5200000082
+:022A5300000081
+:022A5400000080
+:022A550000007F
+:022A560000007E
+:022A570000007D
+:022A580000007C
+:022A590000007B
+:022A5A0000007A
+:022A5B00000079
+:022A5C00000078
+:022A5D00000077
+:022A5E00000076
+:022A5F00000075
+:022A6000000074
+:022A6100000073
+:022A6200000072
+:022A6300000071
+:022A6400000070
+:022A650000006F
+:022A660000006E
+:022A670000006D
+:022A680000006C
+:022A690000006B
+:022A6A0000006A
+:022A6B00000069
+:022A6C00000068
+:022A6D00000067
+:022A6E00000066
+:022A6F00000065
+:022A7000000064
+:022A7100000063
+:022A7200000062
+:022A7300000061
+:022A7400000060
+:022A750000005F
+:022A760000005E
+:022A770000005D
+:022A780000005C
+:022A790000005B
+:022A7A0000005A
+:022A7B00000059
+:022A7C00000058
+:022A7D00000057
+:022A7E00000056
+:022A7F00000055
+:022A8000000054
+:022A8100000053
+:022A8200000052
+:022A8300000051
+:022A8400000050
+:022A850000004F
+:022A860000004E
+:022A870000004D
+:022A880000004C
+:022A890000004B
+:022A8A0000004A
+:022A8B00000049
+:022A8C00000048
+:022A8D00000047
+:022A8E00000046
+:022A8F00000045
+:022A9000000044
+:022A9100000043
+:022A9200000042
+:022A9300000041
+:022A9400000040
+:022A950000003F
+:022A960000003E
+:022A970000003D
+:022A980000003C
+:022A990000003B
+:022A9A0000003A
+:022A9B00000039
+:022A9C00000038
+:022A9D00000037
+:022A9E00000036
+:022A9F00000035
+:022AA000000034
+:022AA100000033
+:022AA200000032
+:022AA300000031
+:022AA400000030
+:022AA50000002F
+:022AA60000002E
+:022AA70000002D
+:022AA80000002C
+:022AA90000002B
+:022AAA0000002A
+:022AAB00000029
+:022AAC00000028
+:022AAD00000027
+:022AAE00000026
+:022AAF00000025
+:022AB000000024
+:022AB100000023
+:022AB200000022
+:022AB300000021
+:022AB400000020
+:022AB50000001F
+:022AB60000001E
+:022AB70000001D
+:022AB80000001C
+:022AB90000001B
+:022ABA0000001A
+:022ABB00000019
+:022ABC00000018
+:022ABD00000017
+:022ABE00000016
+:022ABF00000015
+:022AC000000014
+:022AC100000013
+:022AC200000012
+:022AC300000011
+:022AC400000010
+:022AC50000000F
+:022AC60000000E
+:022AC70000000D
+:022AC80000000C
+:022AC90000000B
+:022ACA0000000A
+:022ACB00000009
+:022ACC00000008
+:022ACD00000007
+:022ACE00000006
+:022ACF00000005
+:022AD000000004
+:022AD100000003
+:022AD200000002
+:022AD300000001
+:022AD400000000
+:022AD5000000FF
+:022AD6000000FE
+:022AD7000000FD
+:022AD8000000FC
+:022AD9000000FB
+:022ADA000000FA
+:022ADB000000F9
+:022ADC000000F8
+:022ADD000000F7
+:022ADE000000F6
+:022ADF000000F5
+:022AE0000000F4
+:022AE1000000F3
+:022AE2000000F2
+:022AE3000000F1
+:022AE4000000F0
+:022AE5000000EF
+:022AE6000000EE
+:022AE7000000ED
+:022AE8000000EC
+:022AE9000000EB
+:022AEA000000EA
+:022AEB000000E9
+:022AEC000000E8
+:022AED000000E7
+:022AEE000000E6
+:022AEF000000E5
+:022AF0000000E4
+:022AF1000000E3
+:022AF2000000E2
+:022AF3000000E1
+:022AF4000000E0
+:022AF5000000DF
+:022AF6000000DE
+:022AF7000000DD
+:022AF8000000DC
+:022AF9000000DB
+:022AFA000000DA
+:022AFB000000D9
+:022AFC000000D8
+:022AFD000000D7
+:022AFE000000D6
+:022AFF000000D5
+:022B00000000D3
+:022B01000000D2
+:022B02000000D1
+:022B03000000D0
+:022B04000000CF
+:022B05000000CE
+:022B06000000CD
+:022B07000000CC
+:022B08000000CB
+:022B09000000CA
+:022B0A000000C9
+:022B0B000000C8
+:022B0C000000C7
+:022B0D000000C6
+:022B0E000000C5
+:022B0F000000C4
+:022B10000000C3
+:022B11000000C2
+:022B12000000C1
+:022B13000000C0
+:022B14000000BF
+:022B15000000BE
+:022B16000000BD
+:022B17000000BC
+:022B18000000BB
+:022B19000000BA
+:022B1A000000B9
+:022B1B000000B8
+:022B1C000000B7
+:022B1D000000B6
+:022B1E000000B5
+:022B1F000000B4
+:022B20000000B3
+:022B21000000B2
+:022B22000000B1
+:022B23000000B0
+:022B24000000AF
+:022B25000000AE
+:022B26000000AD
+:022B27000000AC
+:022B28000000AB
+:022B29000000AA
+:022B2A000000A9
+:022B2B000000A8
+:022B2C000000A7
+:022B2D000000A6
+:022B2E000000A5
+:022B2F000000A4
+:022B30000000A3
+:022B31000000A2
+:022B32000000A1
+:022B33000000A0
+:022B340000009F
+:022B350000009E
+:022B360000009D
+:022B370000009C
+:022B380000009B
+:022B390000009A
+:022B3A00000099
+:022B3B00000098
+:022B3C00000097
+:022B3D00000096
+:022B3E00000095
+:022B3F00000094
+:022B4000000093
+:022B4100000092
+:022B4200000091
+:022B4300000090
+:022B440000008F
+:022B450000008E
+:022B460000008D
+:022B470000008C
+:022B480000008B
+:022B490000008A
+:022B4A00000089
+:022B4B00000088
+:022B4C00000087
+:022B4D00000086
+:022B4E00000085
+:022B4F00000084
+:022B5000000083
+:022B5100000082
+:022B5200000081
+:022B5300000080
+:022B540000007F
+:022B550000007E
+:022B560000007D
+:022B570000007C
+:022B580000007B
+:022B590000007A
+:022B5A00000079
+:022B5B00000078
+:022B5C00000077
+:022B5D00000076
+:022B5E00000075
+:022B5F00000074
+:022B6000000073
+:022B6100000072
+:022B6200000071
+:022B6300000070
+:022B640000006F
+:022B650000006E
+:022B660000006D
+:022B670000006C
+:022B680000006B
+:022B690000006A
+:022B6A00000069
+:022B6B00000068
+:022B6C00000067
+:022B6D00000066
+:022B6E00000065
+:022B6F00000064
+:022B7000000063
+:022B7100000062
+:022B7200000061
+:022B7300000060
+:022B740000005F
+:022B750000005E
+:022B760000005D
+:022B770000005C
+:022B780000005B
+:022B790000005A
+:022B7A00000059
+:022B7B00000058
+:022B7C00000057
+:022B7D00000056
+:022B7E00000055
+:022B7F00000054
+:022B8000000053
+:022B8100000052
+:022B8200000051
+:022B8300000050
+:022B840000004F
+:022B850000004E
+:022B860000004D
+:022B870000004C
+:022B880000004B
+:022B890000004A
+:022B8A00000049
+:022B8B00000048
+:022B8C00000047
+:022B8D00000046
+:022B8E00000045
+:022B8F00000044
+:022B9000000043
+:022B9100000042
+:022B9200000041
+:022B9300000040
+:022B940000003F
+:022B950000003E
+:022B960000003D
+:022B970000003C
+:022B980000003B
+:022B990000003A
+:022B9A00000039
+:022B9B00000038
+:022B9C00000037
+:022B9D00000036
+:022B9E00000035
+:022B9F00000034
+:022BA000000033
+:022BA100000032
+:022BA200000031
+:022BA300000030
+:022BA40000002F
+:022BA50000002E
+:022BA60000002D
+:022BA70000002C
+:022BA80000002B
+:022BA90000002A
+:022BAA00000029
+:022BAB00000028
+:022BAC00000027
+:022BAD00000026
+:022BAE00000025
+:022BAF00000024
+:022BB000000023
+:022BB100000022
+:022BB200000021
+:022BB300000020
+:022BB40000001F
+:022BB50000001E
+:022BB60000001D
+:022BB70000001C
+:022BB80000001B
+:022BB90000001A
+:022BBA00000019
+:022BBB00000018
+:022BBC00000017
+:022BBD00000016
+:022BBE00000015
+:022BBF00000014
+:022BC000000013
+:022BC100000012
+:022BC200000011
+:022BC300000010
+:022BC40000000F
+:022BC50000000E
+:022BC60000000D
+:022BC70000000C
+:022BC80000000B
+:022BC90000000A
+:022BCA00000009
+:022BCB00000008
+:022BCC00000007
+:022BCD00000006
+:022BCE00000005
+:022BCF00000004
+:022BD000000003
+:022BD100000002
+:022BD200000001
+:022BD300000000
+:022BD4000000FF
+:022BD5000000FE
+:022BD6000000FD
+:022BD7000000FC
+:022BD8000000FB
+:022BD9000000FA
+:022BDA000000F9
+:022BDB000000F8
+:022BDC000000F7
+:022BDD000000F6
+:022BDE000000F5
+:022BDF000000F4
+:022BE0000000F3
+:022BE1000000F2
+:022BE2000000F1
+:022BE3000000F0
+:022BE4000000EF
+:022BE5000000EE
+:022BE6000000ED
+:022BE7000000EC
+:022BE8000000EB
+:022BE9000000EA
+:022BEA000000E9
+:022BEB000000E8
+:022BEC000000E7
+:022BED000000E6
+:022BEE000000E5
+:022BEF000000E4
+:022BF0000000E3
+:022BF1000000E2
+:022BF2000000E1
+:022BF3000000E0
+:022BF4000000DF
+:022BF5000000DE
+:022BF6000000DD
+:022BF7000000DC
+:022BF8000000DB
+:022BF9000000DA
+:022BFA000000D9
+:022BFB000000D8
+:022BFC000000D7
+:022BFD000000D6
+:022BFE000000D5
+:022BFF000000D4
+:022C00000000D2
+:022C01000000D1
+:022C02000000D0
+:022C03000000CF
+:022C04000000CE
+:022C05000000CD
+:022C06000000CC
+:022C07000000CB
+:022C08000000CA
+:022C09000000C9
+:022C0A000000C8
+:022C0B000000C7
+:022C0C000000C6
+:022C0D000000C5
+:022C0E000000C4
+:022C0F000000C3
+:022C10000000C2
+:022C11000000C1
+:022C12000000C0
+:022C13000000BF
+:022C14000000BE
+:022C15000000BD
+:022C16000000BC
+:022C17000000BB
+:022C18000000BA
+:022C19000000B9
+:022C1A000000B8
+:022C1B000000B7
+:022C1C000000B6
+:022C1D000000B5
+:022C1E000000B4
+:022C1F000000B3
+:022C20000000B2
+:022C21000000B1
+:022C22000000B0
+:022C23000000AF
+:022C24000000AE
+:022C25000000AD
+:022C26000000AC
+:022C27000000AB
+:022C28000000AA
+:022C29000000A9
+:022C2A000000A8
+:022C2B000000A7
+:022C2C000000A6
+:022C2D000000A5
+:022C2E000000A4
+:022C2F000000A3
+:022C30000000A2
+:022C31000000A1
+:022C32000000A0
+:022C330000009F
+:022C340000009E
+:022C350000009D
+:022C360000009C
+:022C370000009B
+:022C380000009A
+:022C3900000099
+:022C3A00000098
+:022C3B00000097
+:022C3C00000096
+:022C3D00000095
+:022C3E00000094
+:022C3F00000093
+:022C4000000092
+:022C4100000091
+:022C4200000090
+:022C430000008F
+:022C440000008E
+:022C450000008D
+:022C460000008C
+:022C470000008B
+:022C480000008A
+:022C4900000089
+:022C4A00000088
+:022C4B00000087
+:022C4C00000086
+:022C4D00000085
+:022C4E00000084
+:022C4F00000083
+:022C5000000082
+:022C5100000081
+:022C5200000080
+:022C530000007F
+:022C540000007E
+:022C550000007D
+:022C560000007C
+:022C570000007B
+:022C580000007A
+:022C5900000079
+:022C5A00000078
+:022C5B00000077
+:022C5C00000076
+:022C5D00000075
+:022C5E00000074
+:022C5F00000073
+:022C6000000072
+:022C6100000071
+:022C6200000070
+:022C630000006F
+:022C640000006E
+:022C650000006D
+:022C660000006C
+:022C670000006B
+:022C680000006A
+:022C6900000069
+:022C6A00000068
+:022C6B00000067
+:022C6C00000066
+:022C6D00000065
+:022C6E00000064
+:022C6F00000063
+:022C7000000062
+:022C7100000061
+:022C7200000060
+:022C730000005F
+:022C740000005E
+:022C750000005D
+:022C760000005C
+:022C770000005B
+:022C780000005A
+:022C7900000059
+:022C7A00000058
+:022C7B00000057
+:022C7C00000056
+:022C7D00000055
+:022C7E00000054
+:022C7F00000053
+:022C8000000052
+:022C8100000051
+:022C8200000050
+:022C830000004F
+:022C840000004E
+:022C850000004D
+:022C860000004C
+:022C870000004B
+:022C880000004A
+:022C8900000049
+:022C8A00000048
+:022C8B00000047
+:022C8C00000046
+:022C8D00000045
+:022C8E00000044
+:022C8F00000043
+:022C9000000042
+:022C9100000041
+:022C9200000040
+:022C930000003F
+:022C940000003E
+:022C950000003D
+:022C960000003C
+:022C970000003B
+:022C980000003A
+:022C9900000039
+:022C9A00000038
+:022C9B00000037
+:022C9C00000036
+:022C9D00000035
+:022C9E00000034
+:022C9F00000033
+:022CA000000032
+:022CA100000031
+:022CA200000030
+:022CA30000002F
+:022CA40000002E
+:022CA50000002D
+:022CA60000002C
+:022CA70000002B
+:022CA80000002A
+:022CA900000029
+:022CAA00000028
+:022CAB00000027
+:022CAC00000026
+:022CAD00000025
+:022CAE00000024
+:022CAF00000023
+:022CB000000022
+:022CB100000021
+:022CB200000020
+:022CB30000001F
+:022CB40000001E
+:022CB50000001D
+:022CB60000001C
+:022CB70000001B
+:022CB80000001A
+:022CB900000019
+:022CBA00000018
+:022CBB00000017
+:022CBC00000016
+:022CBD00000015
+:022CBE00000014
+:022CBF00000013
+:022CC000000012
+:022CC100000011
+:022CC200000010
+:022CC30000000F
+:022CC40000000E
+:022CC50000000D
+:022CC60000000C
+:022CC70000000B
+:022CC80000000A
+:022CC900000009
+:022CCA00000008
+:022CCB00000007
+:022CCC00000006
+:022CCD00000005
+:022CCE00000004
+:022CCF00000003
+:022CD000000002
+:022CD100000001
+:022CD200000000
+:022CD3000000FF
+:022CD4000000FE
+:022CD5000000FD
+:022CD6000000FC
+:022CD7000000FB
+:022CD8000000FA
+:022CD9000000F9
+:022CDA000000F8
+:022CDB000000F7
+:022CDC000000F6
+:022CDD000000F5
+:022CDE000000F4
+:022CDF000000F3
+:022CE0000000F2
+:022CE1000000F1
+:022CE2000000F0
+:022CE3000000EF
+:022CE4000000EE
+:022CE5000000ED
+:022CE6000000EC
+:022CE7000000EB
+:022CE8000000EA
+:022CE9000000E9
+:022CEA000000E8
+:022CEB000000E7
+:022CEC000000E6
+:022CED000000E5
+:022CEE000000E4
+:022CEF000000E3
+:022CF0000000E2
+:022CF1000000E1
+:022CF2000000E0
+:022CF3000000DF
+:022CF4000000DE
+:022CF5000000DD
+:022CF6000000DC
+:022CF7000000DB
+:022CF8000000DA
+:022CF9000000D9
+:022CFA000000D8
+:022CFB000000D7
+:022CFC000000D6
+:022CFD000000D5
+:022CFE000000D4
+:022CFF000000D3
+:022D00000000D1
+:022D01000000D0
+:022D02000000CF
+:022D03000000CE
+:022D04000000CD
+:022D05000000CC
+:022D06000000CB
+:022D07000000CA
+:022D08000000C9
+:022D09000000C8
+:022D0A000000C7
+:022D0B000000C6
+:022D0C000000C5
+:022D0D000000C4
+:022D0E000000C3
+:022D0F000000C2
+:022D10000000C1
+:022D11000000C0
+:022D12000000BF
+:022D13000000BE
+:022D14000000BD
+:022D15000000BC
+:022D16000000BB
+:022D17000000BA
+:022D18000000B9
+:022D19000000B8
+:022D1A000000B7
+:022D1B000000B6
+:022D1C000000B5
+:022D1D000000B4
+:022D1E000000B3
+:022D1F000000B2
+:022D20000000B1
+:022D21000000B0
+:022D22000000AF
+:022D23000000AE
+:022D24000000AD
+:022D25000000AC
+:022D26000000AB
+:022D27000000AA
+:022D28000000A9
+:022D29000000A8
+:022D2A000000A7
+:022D2B000000A6
+:022D2C000000A5
+:022D2D000000A4
+:022D2E000000A3
+:022D2F000000A2
+:022D30000000A1
+:022D31000000A0
+:022D320000009F
+:022D330000009E
+:022D340000009D
+:022D350000009C
+:022D360000009B
+:022D370000009A
+:022D3800000099
+:022D3900000098
+:022D3A00000097
+:022D3B00000096
+:022D3C00000095
+:022D3D00000094
+:022D3E00000093
+:022D3F00000092
+:022D4000000091
+:022D4100000090
+:022D420000008F
+:022D430000008E
+:022D440000008D
+:022D450000008C
+:022D460000008B
+:022D470000008A
+:022D4800000089
+:022D4900000088
+:022D4A00000087
+:022D4B00000086
+:022D4C00000085
+:022D4D00000084
+:022D4E00000083
+:022D4F00000082
+:022D5000000081
+:022D5100000080
+:022D520000007F
+:022D530000007E
+:022D540000007D
+:022D550000007C
+:022D560000007B
+:022D570000007A
+:022D5800000079
+:022D5900000078
+:022D5A00000077
+:022D5B00000076
+:022D5C00000075
+:022D5D00000074
+:022D5E00000073
+:022D5F00000072
+:022D6000000071
+:022D6100000070
+:022D620000006F
+:022D630000006E
+:022D640000006D
+:022D650000006C
+:022D660000006B
+:022D670000006A
+:022D6800000069
+:022D6900000068
+:022D6A00000067
+:022D6B00000066
+:022D6C00000065
+:022D6D00000064
+:022D6E00000063
+:022D6F00000062
+:022D7000000061
+:022D7100000060
+:022D720000005F
+:022D730000005E
+:022D740000005D
+:022D750000005C
+:022D760000005B
+:022D770000005A
+:022D7800000059
+:022D7900000058
+:022D7A00000057
+:022D7B00000056
+:022D7C00000055
+:022D7D00000054
+:022D7E00000053
+:022D7F00000052
+:022D8000000051
+:022D8100000050
+:022D820000004F
+:022D830000004E
+:022D840000004D
+:022D850000004C
+:022D860000004B
+:022D870000004A
+:022D8800000049
+:022D8900000048
+:022D8A00000047
+:022D8B00000046
+:022D8C00000045
+:022D8D00000044
+:022D8E00000043
+:022D8F00000042
+:022D9000000041
+:022D9100000040
+:022D920000003F
+:022D930000003E
+:022D940000003D
+:022D950000003C
+:022D960000003B
+:022D970000003A
+:022D9800000039
+:022D9900000038
+:022D9A00000037
+:022D9B00000036
+:022D9C00000035
+:022D9D00000034
+:022D9E00000033
+:022D9F00000032
+:022DA000000031
+:022DA100000030
+:022DA20000002F
+:022DA30000002E
+:022DA40000002D
+:022DA50000002C
+:022DA60000002B
+:022DA70000002A
+:022DA800000029
+:022DA900000028
+:022DAA00000027
+:022DAB00000026
+:022DAC00000025
+:022DAD00000024
+:022DAE00000023
+:022DAF00000022
+:022DB000000021
+:022DB100000020
+:022DB20000001F
+:022DB30000001E
+:022DB40000001D
+:022DB50000001C
+:022DB60000001B
+:022DB70000001A
+:022DB800000019
+:022DB900000018
+:022DBA00000017
+:022DBB00000016
+:022DBC00000015
+:022DBD00000014
+:022DBE00000013
+:022DBF00000012
+:022DC000000011
+:022DC100000010
+:022DC20000000F
+:022DC30000000E
+:022DC40000000D
+:022DC50000000C
+:022DC60000000B
+:022DC70000000A
+:022DC800000009
+:022DC900000008
+:022DCA00000007
+:022DCB00000006
+:022DCC00000005
+:022DCD00000004
+:022DCE00000003
+:022DCF00000002
+:022DD000000001
+:022DD100000000
+:022DD2000000FF
+:022DD3000000FE
+:022DD4000000FD
+:022DD5000000FC
+:022DD6000000FB
+:022DD7000000FA
+:022DD8000000F9
+:022DD9000000F8
+:022DDA000000F7
+:022DDB000000F6
+:022DDC000000F5
+:022DDD000000F4
+:022DDE000000F3
+:022DDF000000F2
+:022DE0000000F1
+:022DE1000000F0
+:022DE2000000EF
+:022DE3000000EE
+:022DE4000000ED
+:022DE5000000EC
+:022DE6000000EB
+:022DE7000000EA
+:022DE8000000E9
+:022DE9000000E8
+:022DEA000000E7
+:022DEB000000E6
+:022DEC000000E5
+:022DED000000E4
+:022DEE000000E3
+:022DEF000000E2
+:022DF0000000E1
+:022DF1000000E0
+:022DF2000000DF
+:022DF3000000DE
+:022DF4000000DD
+:022DF5000000DC
+:022DF6000000DB
+:022DF7000000DA
+:022DF8000000D9
+:022DF9000000D8
+:022DFA000000D7
+:022DFB000000D6
+:022DFC000000D5
+:022DFD000000D4
+:022DFE000000D3
+:022DFF000000D2
+:022E00000000D0
+:022E01000000CF
+:022E02000000CE
+:022E03000000CD
+:022E04000000CC
+:022E05000000CB
+:022E06000000CA
+:022E07000000C9
+:022E08000000C8
+:022E09000000C7
+:022E0A000000C6
+:022E0B000000C5
+:022E0C000000C4
+:022E0D000000C3
+:022E0E000000C2
+:022E0F000000C1
+:022E10000000C0
+:022E11000000BF
+:022E12000000BE
+:022E13000000BD
+:022E14000000BC
+:022E15000000BB
+:022E16000000BA
+:022E17000000B9
+:022E18000000B8
+:022E19000000B7
+:022E1A000000B6
+:022E1B000000B5
+:022E1C000000B4
+:022E1D000000B3
+:022E1E000000B2
+:022E1F000000B1
+:022E20000000B0
+:022E21000000AF
+:022E22000000AE
+:022E23000000AD
+:022E24000000AC
+:022E25000000AB
+:022E26000000AA
+:022E27000000A9
+:022E28000000A8
+:022E29000000A7
+:022E2A000000A6
+:022E2B000000A5
+:022E2C000000A4
+:022E2D000000A3
+:022E2E000000A2
+:022E2F000000A1
+:022E30000000A0
+:022E310000009F
+:022E320000009E
+:022E330000009D
+:022E340000009C
+:022E350000009B
+:022E360000009A
+:022E3700000099
+:022E3800000098
+:022E3900000097
+:022E3A00000096
+:022E3B00000095
+:022E3C00000094
+:022E3D00000093
+:022E3E00000092
+:022E3F00000091
+:022E4000000090
+:022E410000008F
+:022E420000008E
+:022E430000008D
+:022E440000008C
+:022E450000008B
+:022E460000008A
+:022E4700000089
+:022E4800000088
+:022E4900000087
+:022E4A00000086
+:022E4B00000085
+:022E4C00000084
+:022E4D00000083
+:022E4E00000082
+:022E4F00000081
+:022E5000000080
+:022E510000007F
+:022E520000007E
+:022E530000007D
+:022E540000007C
+:022E550000007B
+:022E560000007A
+:022E5700000079
+:022E5800000078
+:022E5900000077
+:022E5A00000076
+:022E5B00000075
+:022E5C00000074
+:022E5D00000073
+:022E5E00000072
+:022E5F00000071
+:022E6000000070
+:022E610000006F
+:022E620000006E
+:022E630000006D
+:022E640000006C
+:022E650000006B
+:022E660000006A
+:022E6700000069
+:022E6800000068
+:022E6900000067
+:022E6A00000066
+:022E6B00000065
+:022E6C00000064
+:022E6D00000063
+:022E6E00000062
+:022E6F00000061
+:022E7000000060
+:022E710000005F
+:022E720000005E
+:022E730000005D
+:022E740000005C
+:022E750000005B
+:022E760000005A
+:022E7700000059
+:022E7800000058
+:022E7900000057
+:022E7A00000056
+:022E7B00000055
+:022E7C00000054
+:022E7D00000053
+:022E7E00000052
+:022E7F00000051
+:022E8000000050
+:022E810000004F
+:022E820000004E
+:022E830000004D
+:022E840000004C
+:022E850000004B
+:022E860000004A
+:022E8700000049
+:022E8800000048
+:022E8900000047
+:022E8A00000046
+:022E8B00000045
+:022E8C00000044
+:022E8D00000043
+:022E8E00000042
+:022E8F00000041
+:022E9000000040
+:022E910000003F
+:022E920000003E
+:022E930000003D
+:022E940000003C
+:022E950000003B
+:022E960000003A
+:022E9700000039
+:022E9800000038
+:022E9900000037
+:022E9A00000036
+:022E9B00000035
+:022E9C00000034
+:022E9D00000033
+:022E9E00000032
+:022E9F00000031
+:022EA000000030
+:022EA10000002F
+:022EA20000002E
+:022EA30000002D
+:022EA40000002C
+:022EA50000002B
+:022EA60000002A
+:022EA700000029
+:022EA800000028
+:022EA900000027
+:022EAA00000026
+:022EAB00000025
+:022EAC00000024
+:022EAD00000023
+:022EAE00000022
+:022EAF00000021
+:022EB000000020
+:022EB10000001F
+:022EB20000001E
+:022EB30000001D
+:022EB40000001C
+:022EB50000001B
+:022EB60000001A
+:022EB700000019
+:022EB800000018
+:022EB900000017
+:022EBA00000016
+:022EBB00000015
+:022EBC00000014
+:022EBD00000013
+:022EBE00000012
+:022EBF00000011
+:022EC000000010
+:022EC10000000F
+:022EC20000000E
+:022EC30000000D
+:022EC40000000C
+:022EC50000000B
+:022EC60000000A
+:022EC700000009
+:022EC800000008
+:022EC900000007
+:022ECA00000006
+:022ECB00000005
+:022ECC00000004
+:022ECD00000003
+:022ECE00000002
+:022ECF00000001
+:022ED000000000
+:022ED1000000FF
+:022ED2000000FE
+:022ED3000000FD
+:022ED4000000FC
+:022ED5000000FB
+:022ED6000000FA
+:022ED7000000F9
+:022ED8000000F8
+:022ED9000000F7
+:022EDA000000F6
+:022EDB000000F5
+:022EDC000000F4
+:022EDD000000F3
+:022EDE000000F2
+:022EDF000000F1
+:022EE0000000F0
+:022EE1000000EF
+:022EE2000000EE
+:022EE3000000ED
+:022EE4000000EC
+:022EE5000000EB
+:022EE6000000EA
+:022EE7000000E9
+:022EE8000000E8
+:022EE9000000E7
+:022EEA000000E6
+:022EEB000000E5
+:022EEC000000E4
+:022EED000000E3
+:022EEE000000E2
+:022EEF000000E1
+:022EF0000000E0
+:022EF1000000DF
+:022EF2000000DE
+:022EF3000000DD
+:022EF4000000DC
+:022EF5000000DB
+:022EF6000000DA
+:022EF7000000D9
+:022EF8000000D8
+:022EF9000000D7
+:022EFA000000D6
+:022EFB000000D5
+:022EFC000000D4
+:022EFD000000D3
+:022EFE000000D2
+:022EFF000000D1
+:022F00000000CF
+:022F01000000CE
+:022F02000000CD
+:022F03000000CC
+:022F04000000CB
+:022F05000000CA
+:022F06000000C9
+:022F07000000C8
+:022F08000000C7
+:022F09000000C6
+:022F0A000000C5
+:022F0B000000C4
+:022F0C000000C3
+:022F0D000000C2
+:022F0E000000C1
+:022F0F000000C0
+:022F10000000BF
+:022F11000000BE
+:022F12000000BD
+:022F13000000BC
+:022F14000000BB
+:022F15000000BA
+:022F16000000B9
+:022F17000000B8
+:022F18000000B7
+:022F19000000B6
+:022F1A000000B5
+:022F1B000000B4
+:022F1C000000B3
+:022F1D000000B2
+:022F1E000000B1
+:022F1F000000B0
+:022F20000000AF
+:022F21000000AE
+:022F22000000AD
+:022F23000000AC
+:022F24000000AB
+:022F25000000AA
+:022F26000000A9
+:022F27000000A8
+:022F28000000A7
+:022F29000000A6
+:022F2A000000A5
+:022F2B000000A4
+:022F2C000000A3
+:022F2D000000A2
+:022F2E000000A1
+:022F2F000000A0
+:022F300000009F
+:022F310000009E
+:022F320000009D
+:022F330000009C
+:022F340000009B
+:022F350000009A
+:022F3600000099
+:022F3700000098
+:022F3800000097
+:022F3900000096
+:022F3A00000095
+:022F3B00000094
+:022F3C00000093
+:022F3D00000092
+:022F3E00000091
+:022F3F00000090
+:022F400000008F
+:022F410000008E
+:022F420000008D
+:022F430000008C
+:022F440000008B
+:022F450000008A
+:022F4600000089
+:022F4700000088
+:022F4800000087
+:022F4900000086
+:022F4A00000085
+:022F4B00000084
+:022F4C00000083
+:022F4D00000082
+:022F4E00000081
+:022F4F00000080
+:022F500000007F
+:022F510000007E
+:022F520000007D
+:022F530000007C
+:022F540000007B
+:022F550000007A
+:022F5600000079
+:022F5700000078
+:022F5800000077
+:022F5900000076
+:022F5A00000075
+:022F5B00000074
+:022F5C00000073
+:022F5D00000072
+:022F5E00000071
+:022F5F00000070
+:022F600000006F
+:022F610000006E
+:022F620000006D
+:022F630000006C
+:022F640000006B
+:022F650000006A
+:022F6600000069
+:022F6700000068
+:022F6800000067
+:022F6900000066
+:022F6A00000065
+:022F6B00000064
+:022F6C00000063
+:022F6D00000062
+:022F6E00000061
+:022F6F00000060
+:022F700000005F
+:022F710000005E
+:022F720000005D
+:022F730000005C
+:022F740000005B
+:022F750000005A
+:022F7600000059
+:022F7700000058
+:022F7800000057
+:022F7900000056
+:022F7A00000055
+:022F7B00000054
+:022F7C00000053
+:022F7D00000052
+:022F7E00000051
+:022F7F00000050
+:022F800000004F
+:022F810000004E
+:022F820000004D
+:022F830000004C
+:022F840000004B
+:022F850000004A
+:022F8600000049
+:022F8700000048
+:022F8800000047
+:022F8900000046
+:022F8A00000045
+:022F8B00000044
+:022F8C00000043
+:022F8D00000042
+:022F8E00000041
+:022F8F00000040
+:022F900000003F
+:022F910000003E
+:022F920000003D
+:022F930000003C
+:022F940000003B
+:022F950000003A
+:022F9600000039
+:022F9700000038
+:022F9800000037
+:022F9900000036
+:022F9A00000035
+:022F9B00000034
+:022F9C00000033
+:022F9D00000032
+:022F9E00000031
+:022F9F00000030
+:022FA00000002F
+:022FA10000002E
+:022FA20000002D
+:022FA30000002C
+:022FA40000002B
+:022FA50000002A
+:022FA600000029
+:022FA700000028
+:022FA800000027
+:022FA900000026
+:022FAA00000025
+:022FAB00000024
+:022FAC00000023
+:022FAD00000022
+:022FAE00000021
+:022FAF00000020
+:022FB00000001F
+:022FB10000001E
+:022FB20000001D
+:022FB30000001C
+:022FB40000001B
+:022FB50000001A
+:022FB600000019
+:022FB700000018
+:022FB800000017
+:022FB900000016
+:022FBA00000015
+:022FBB00000014
+:022FBC00000013
+:022FBD00000012
+:022FBE00000011
+:022FBF00000010
+:022FC00000000F
+:022FC10000000E
+:022FC20000000D
+:022FC30000000C
+:022FC40000000B
+:022FC50000000A
+:022FC600000009
+:022FC700000008
+:022FC800000007
+:022FC900000006
+:022FCA00000005
+:022FCB00000004
+:022FCC00000003
+:022FCD00000002
+:022FCE00000001
+:022FCF00000000
+:022FD0000000FF
+:022FD1000000FE
+:022FD2000000FD
+:022FD3000000FC
+:022FD4000000FB
+:022FD5000000FA
+:022FD6000000F9
+:022FD7000000F8
+:022FD8000000F7
+:022FD9000000F6
+:022FDA000000F5
+:022FDB000000F4
+:022FDC000000F3
+:022FDD000000F2
+:022FDE000000F1
+:022FDF000000F0
+:022FE0000000EF
+:022FE1000000EE
+:022FE2000000ED
+:022FE3000000EC
+:022FE4000000EB
+:022FE5000000EA
+:022FE6000000E9
+:022FE7000000E8
+:022FE8000000E7
+:022FE9000000E6
+:022FEA000000E5
+:022FEB000000E4
+:022FEC000000E3
+:022FED000000E2
+:022FEE000000E1
+:022FEF000000E0
+:022FF0000000DF
+:022FF1000000DE
+:022FF2000000DD
+:022FF3000000DC
+:022FF4000000DB
+:022FF5000000DA
+:022FF6000000D9
+:022FF7000000D8
+:022FF8000000D7
+:022FF9000000D6
+:022FFA000000D5
+:022FFB000000D4
+:022FFC000000D3
+:022FFD000000D2
+:022FFE000000D1
+:022FFF000000D0
+:023000000000CE
+:023001000000CD
+:023002000000CC
+:023003000000CB
+:023004000000CA
+:023005000000C9
+:023006000000C8
+:023007000000C7
+:023008000000C6
+:023009000000C5
+:02300A000000C4
+:02300B000000C3
+:02300C000000C2
+:02300D000000C1
+:02300E000000C0
+:02300F000000BF
+:023010000000BE
+:023011000000BD
+:023012000000BC
+:023013000000BB
+:023014000000BA
+:023015000000B9
+:023016000000B8
+:023017000000B7
+:023018000000B6
+:023019000000B5
+:02301A000000B4
+:02301B000000B3
+:02301C000000B2
+:02301D000000B1
+:02301E000000B0
+:02301F000000AF
+:023020000000AE
+:023021000000AD
+:023022000000AC
+:023023000000AB
+:023024000000AA
+:023025000000A9
+:023026000000A8
+:023027000000A7
+:023028000000A6
+:023029000000A5
+:02302A000000A4
+:02302B000000A3
+:02302C000000A2
+:02302D000000A1
+:02302E000000A0
+:02302F0000009F
+:0230300000009E
+:0230310000009D
+:0230320000009C
+:0230330000009B
+:0230340000009A
+:02303500000099
+:02303600000098
+:02303700000097
+:02303800000096
+:02303900000095
+:02303A00000094
+:02303B00000093
+:02303C00000092
+:02303D00000091
+:02303E00000090
+:02303F0000008F
+:0230400000008E
+:0230410000008D
+:0230420000008C
+:0230430000008B
+:0230440000008A
+:02304500000089
+:02304600000088
+:02304700000087
+:02304800000086
+:02304900000085
+:02304A00000084
+:02304B00000083
+:02304C00000082
+:02304D00000081
+:02304E00000080
+:02304F0000007F
+:0230500000007E
+:0230510000007D
+:0230520000007C
+:0230530000007B
+:0230540000007A
+:02305500000079
+:02305600000078
+:02305700000077
+:02305800000076
+:02305900000075
+:02305A00000074
+:02305B00000073
+:02305C00000072
+:02305D00000071
+:02305E00000070
+:02305F0000006F
+:0230600000006E
+:0230610000006D
+:0230620000006C
+:0230630000006B
+:0230640000006A
+:02306500000069
+:02306600000068
+:02306700000067
+:02306800000066
+:02306900000065
+:02306A00000064
+:02306B00000063
+:02306C00000062
+:02306D00000061
+:02306E00000060
+:02306F0000005F
+:0230700000005E
+:0230710000005D
+:0230720000005C
+:0230730000005B
+:0230740000005A
+:02307500000059
+:02307600000058
+:02307700000057
+:02307800000056
+:02307900000055
+:02307A00000054
+:02307B00000053
+:02307C00000052
+:02307D00000051
+:02307E00000050
+:02307F0000004F
+:0230800000004E
+:0230810000004D
+:0230820000004C
+:0230830000004B
+:0230840000004A
+:02308500000049
+:02308600000048
+:02308700000047
+:02308800000046
+:02308900000045
+:02308A00000044
+:02308B00000043
+:02308C00000042
+:02308D00000041
+:02308E00000040
+:02308F0000003F
+:0230900000003E
+:0230910000003D
+:0230920000003C
+:0230930000003B
+:0230940000003A
+:02309500000039
+:02309600000038
+:02309700000037
+:02309800000036
+:02309900000035
+:02309A00000034
+:02309B00000033
+:02309C00000032
+:02309D00000031
+:02309E00000030
+:02309F0000002F
+:0230A00000002E
+:0230A10000002D
+:0230A20000002C
+:0230A30000002B
+:0230A40000002A
+:0230A500000029
+:0230A600000028
+:0230A700000027
+:0230A800000026
+:0230A900000025
+:0230AA00000024
+:0230AB00000023
+:0230AC00000022
+:0230AD00000021
+:0230AE00000020
+:0230AF0000001F
+:0230B00000001E
+:0230B10000001D
+:0230B20000001C
+:0230B30000001B
+:0230B40000001A
+:0230B500000019
+:0230B600000018
+:0230B700000017
+:0230B800000016
+:0230B900000015
+:0230BA00000014
+:0230BB00000013
+:0230BC00000012
+:0230BD00000011
+:0230BE00000010
+:0230BF0000000F
+:0230C00000000E
+:0230C10000000D
+:0230C20000000C
+:0230C30000000B
+:0230C40000000A
+:0230C500000009
+:0230C600000008
+:0230C700000007
+:0230C800000006
+:0230C900000005
+:0230CA00000004
+:0230CB00000003
+:0230CC00000002
+:0230CD00000001
+:0230CE00000000
+:0230CF000000FF
+:0230D0000000FE
+:0230D1000000FD
+:0230D2000000FC
+:0230D3000000FB
+:0230D4000000FA
+:0230D5000000F9
+:0230D6000000F8
+:0230D7000000F7
+:0230D8000000F6
+:0230D9000000F5
+:0230DA000000F4
+:0230DB000000F3
+:0230DC000000F2
+:0230DD000000F1
+:0230DE000000F0
+:0230DF000000EF
+:0230E0000000EE
+:0230E1000000ED
+:0230E2000000EC
+:0230E3000000EB
+:0230E4000000EA
+:0230E5000000E9
+:0230E6000000E8
+:0230E7000000E7
+:0230E8000000E6
+:0230E9000000E5
+:0230EA000000E4
+:0230EB000000E3
+:0230EC000000E2
+:0230ED000000E1
+:0230EE000000E0
+:0230EF000000DF
+:0230F0000000DE
+:0230F1000000DD
+:0230F2000000DC
+:0230F3000000DB
+:0230F4000000DA
+:0230F5000000D9
+:0230F6000000D8
+:0230F7000000D7
+:0230F8000000D6
+:0230F9000000D5
+:0230FA000000D4
+:0230FB000000D3
+:0230FC000000D2
+:0230FD000000D1
+:0230FE000000D0
+:0230FF000000CF
+:023100000000CD
+:023101000000CC
+:023102000000CB
+:023103000000CA
+:023104000000C9
+:023105000000C8
+:023106000000C7
+:023107000000C6
+:023108000000C5
+:023109000000C4
+:02310A000000C3
+:02310B000000C2
+:02310C000000C1
+:02310D000000C0
+:02310E000000BF
+:02310F000000BE
+:023110000000BD
+:023111000000BC
+:023112000000BB
+:023113000000BA
+:023114000000B9
+:023115000000B8
+:023116000000B7
+:023117000000B6
+:023118000000B5
+:023119000000B4
+:02311A000000B3
+:02311B000000B2
+:02311C000000B1
+:02311D000000B0
+:02311E000000AF
+:02311F000000AE
+:023120000000AD
+:023121000000AC
+:023122000000AB
+:023123000000AA
+:023124000000A9
+:023125000000A8
+:023126000000A7
+:023127000000A6
+:023128000000A5
+:023129000000A4
+:02312A000000A3
+:02312B000000A2
+:02312C000000A1
+:02312D000000A0
+:02312E0000009F
+:02312F0000009E
+:0231300000009D
+:0231310000009C
+:0231320000009B
+:0231330000009A
+:02313400000099
+:02313500000098
+:02313600000097
+:02313700000096
+:02313800000095
+:02313900000094
+:02313A00000093
+:02313B00000092
+:02313C00000091
+:02313D00000090
+:02313E0000008F
+:02313F0000008E
+:0231400000008D
+:0231410000008C
+:0231420000008B
+:0231430000008A
+:02314400000089
+:02314500000088
+:02314600000087
+:02314700000086
+:02314800000085
+:02314900000084
+:02314A00000083
+:02314B00000082
+:02314C00000081
+:02314D00000080
+:02314E0000007F
+:02314F0000007E
+:0231500000007D
+:0231510000007C
+:0231520000007B
+:0231530000007A
+:02315400000079
+:02315500000078
+:02315600000077
+:02315700000076
+:02315800000075
+:02315900000074
+:02315A00000073
+:02315B00000072
+:02315C00000071
+:02315D00000070
+:02315E0000006F
+:02315F0000006E
+:0231600000006D
+:0231610000006C
+:0231620000006B
+:0231630000006A
+:02316400000069
+:02316500000068
+:02316600000067
+:02316700000066
+:02316800000065
+:02316900000064
+:02316A00000063
+:02316B00000062
+:02316C00000061
+:02316D00000060
+:02316E0000005F
+:02316F0000005E
+:0231700000005D
+:0231710000005C
+:0231720000005B
+:0231730000005A
+:02317400000059
+:02317500000058
+:02317600000057
+:02317700000056
+:02317800000055
+:02317900000054
+:02317A00000053
+:02317B00000052
+:02317C00000051
+:02317D00000050
+:02317E0000004F
+:02317F0000004E
+:0231800000004D
+:0231810000004C
+:0231820000004B
+:0231830000004A
+:02318400000049
+:02318500000048
+:02318600000047
+:02318700000046
+:02318800000045
+:02318900000044
+:02318A00000043
+:02318B00000042
+:02318C00000041
+:02318D00000040
+:02318E0000003F
+:02318F0000003E
+:0231900000003D
+:0231910000003C
+:0231920000003B
+:0231930000003A
+:02319400000039
+:02319500000038
+:02319600000037
+:02319700000036
+:02319800000035
+:02319900000034
+:02319A00000033
+:02319B00000032
+:02319C00000031
+:02319D00000030
+:02319E0000002F
+:02319F0000002E
+:0231A00000002D
+:0231A10000002C
+:0231A20000002B
+:0231A30000002A
+:0231A400000029
+:0231A500000028
+:0231A600000027
+:0231A700000026
+:0231A800000025
+:0231A900000024
+:0231AA00000023
+:0231AB00000022
+:0231AC00000021
+:0231AD00000020
+:0231AE0000001F
+:0231AF0000001E
+:0231B00000001D
+:0231B10000001C
+:0231B20000001B
+:0231B30000001A
+:0231B400000019
+:0231B500000018
+:0231B600000017
+:0231B700000016
+:0231B800000015
+:0231B900000014
+:0231BA00000013
+:0231BB00000012
+:0231BC00000011
+:0231BD00000010
+:0231BE0000000F
+:0231BF0000000E
+:0231C00000000D
+:0231C10000000C
+:0231C20000000B
+:0231C30000000A
+:0231C400000009
+:0231C500000008
+:0231C600000007
+:0231C700000006
+:0231C800000005
+:0231C900000004
+:0231CA00000003
+:0231CB00000002
+:0231CC00000001
+:0231CD00000000
+:0231CE000000FF
+:0231CF000000FE
+:0231D0000000FD
+:0231D1000000FC
+:0231D2000000FB
+:0231D3000000FA
+:0231D4000000F9
+:0231D5000000F8
+:0231D6000000F7
+:0231D7000000F6
+:0231D8000000F5
+:0231D9000000F4
+:0231DA000000F3
+:0231DB000000F2
+:0231DC000000F1
+:0231DD000000F0
+:0231DE000000EF
+:0231DF000000EE
+:0231E0000000ED
+:0231E1000000EC
+:0231E2000000EB
+:0231E3000000EA
+:0231E4000000E9
+:0231E5000000E8
+:0231E6000000E7
+:0231E7000000E6
+:0231E8000000E5
+:0231E9000000E4
+:0231EA000000E3
+:0231EB000000E2
+:0231EC000000E1
+:0231ED000000E0
+:0231EE000000DF
+:0231EF000000DE
+:0231F0000000DD
+:0231F1000000DC
+:0231F2000000DB
+:0231F3000000DA
+:0231F4000000D9
+:0231F5000000D8
+:0231F6000000D7
+:0231F7000000D6
+:0231F8000000D5
+:0231F9000000D4
+:0231FA000000D3
+:0231FB000000D2
+:0231FC000000D1
+:0231FD000000D0
+:0231FE000000CF
+:0231FF000000CE
+:023200000000CC
+:023201000000CB
+:023202000000CA
+:023203000000C9
+:023204000000C8
+:023205000000C7
+:023206000000C6
+:023207000000C5
+:023208000000C4
+:023209000000C3
+:02320A000000C2
+:02320B000000C1
+:02320C000000C0
+:02320D000000BF
+:02320E000000BE
+:02320F000000BD
+:023210000000BC
+:023211000000BB
+:023212000000BA
+:023213000000B9
+:023214000000B8
+:023215000000B7
+:023216000000B6
+:023217000000B5
+:023218000000B4
+:023219000000B3
+:02321A000000B2
+:02321B000000B1
+:02321C000000B0
+:02321D000000AF
+:02321E000000AE
+:02321F000000AD
+:023220000000AC
+:023221000000AB
+:023222000000AA
+:023223000000A9
+:023224000000A8
+:023225000000A7
+:023226000000A6
+:023227000000A5
+:023228000000A4
+:023229000000A3
+:02322A000000A2
+:02322B000000A1
+:02322C000000A0
+:02322D0000009F
+:02322E0000009E
+:02322F0000009D
+:0232300000009C
+:0232310000009B
+:0232320000009A
+:02323300000099
+:02323400000098
+:02323500000097
+:02323600000096
+:02323700000095
+:02323800000094
+:02323900000093
+:02323A00000092
+:02323B00000091
+:02323C00000090
+:02323D0000008F
+:02323E0000008E
+:02323F0000008D
+:0232400000008C
+:0232410000008B
+:0232420000008A
+:02324300000089
+:02324400000088
+:02324500000087
+:02324600000086
+:02324700000085
+:02324800000084
+:02324900000083
+:02324A00000082
+:02324B00000081
+:02324C00000080
+:02324D0000007F
+:02324E0000007E
+:02324F0000007D
+:0232500000007C
+:0232510000007B
+:0232520000007A
+:02325300000079
+:02325400000078
+:02325500000077
+:02325600000076
+:02325700000075
+:02325800000074
+:02325900000073
+:02325A00000072
+:02325B00000071
+:02325C00000070
+:02325D0000006F
+:02325E0000006E
+:02325F0000006D
+:0232600000006C
+:0232610000006B
+:0232620000006A
+:02326300000069
+:02326400000068
+:02326500000067
+:02326600000066
+:02326700000065
+:02326800000064
+:02326900000063
+:02326A00000062
+:02326B00000061
+:02326C00000060
+:02326D0000005F
+:02326E0000005E
+:02326F0000005D
+:0232700000005C
+:0232710000005B
+:0232720000005A
+:02327300000059
+:02327400000058
+:02327500000057
+:02327600000056
+:02327700000055
+:02327800000054
+:02327900000053
+:02327A00000052
+:02327B00000051
+:02327C00000050
+:02327D0000004F
+:02327E0000004E
+:02327F0000004D
+:0232800000004C
+:0232810000004B
+:0232820000004A
+:02328300000049
+:02328400000048
+:02328500000047
+:02328600000046
+:02328700000045
+:02328800000044
+:02328900000043
+:02328A00000042
+:02328B00000041
+:02328C00000040
+:02328D0000003F
+:02328E0000003E
+:02328F0000003D
+:0232900000003C
+:0232910000003B
+:0232920000003A
+:02329300000039
+:02329400000038
+:02329500000037
+:02329600000036
+:02329700000035
+:02329800000034
+:02329900000033
+:02329A00000032
+:02329B00000031
+:02329C00000030
+:02329D0000002F
+:02329E0000002E
+:02329F0000002D
+:0232A00000002C
+:0232A10000002B
+:0232A20000002A
+:0232A300000029
+:0232A400000028
+:0232A500000027
+:0232A600000026
+:0232A700000025
+:0232A800000024
+:0232A900000023
+:0232AA00000022
+:0232AB00000021
+:0232AC00000020
+:0232AD0000001F
+:0232AE0000001E
+:0232AF0000001D
+:0232B00000001C
+:0232B10000001B
+:0232B20000001A
+:0232B300000019
+:0232B400000018
+:0232B500000017
+:0232B600000016
+:0232B700000015
+:0232B800000014
+:0232B900000013
+:0232BA00000012
+:0232BB00000011
+:0232BC00000010
+:0232BD0000000F
+:0232BE0000000E
+:0232BF0000000D
+:0232C00000000C
+:0232C10000000B
+:0232C20000000A
+:0232C300000009
+:0232C400000008
+:0232C500000007
+:0232C600000006
+:0232C700000005
+:0232C800000004
+:0232C900000003
+:0232CA00000002
+:0232CB00000001
+:0232CC00000000
+:0232CD000000FF
+:0232CE000000FE
+:0232CF000000FD
+:0232D0000000FC
+:0232D1000000FB
+:0232D2000000FA
+:0232D3000000F9
+:0232D4000000F8
+:0232D5000000F7
+:0232D6000000F6
+:0232D7000000F5
+:0232D8000000F4
+:0232D9000000F3
+:0232DA000000F2
+:0232DB000000F1
+:0232DC000000F0
+:0232DD000000EF
+:0232DE000000EE
+:0232DF000000ED
+:0232E0000000EC
+:0232E1000000EB
+:0232E2000000EA
+:0232E3000000E9
+:0232E4000000E8
+:0232E5000000E7
+:0232E6000000E6
+:0232E7000000E5
+:0232E8000000E4
+:0232E9000000E3
+:0232EA000000E2
+:0232EB000000E1
+:0232EC000000E0
+:0232ED000000DF
+:0232EE000000DE
+:0232EF000000DD
+:0232F0000000DC
+:0232F1000000DB
+:0232F2000000DA
+:0232F3000000D9
+:0232F4000000D8
+:0232F5000000D7
+:0232F6000000D6
+:0232F7000000D5
+:0232F8000000D4
+:0232F9000000D3
+:0232FA000000D2
+:0232FB000000D1
+:0232FC000000D0
+:0232FD000000CF
+:0232FE000000CE
+:0232FF000000CD
+:023300000000CB
+:023301000000CA
+:023302000000C9
+:023303000000C8
+:023304000000C7
+:023305000000C6
+:023306000000C5
+:023307000000C4
+:023308000000C3
+:023309000000C2
+:02330A000000C1
+:02330B000000C0
+:02330C000000BF
+:02330D000000BE
+:02330E000000BD
+:02330F000000BC
+:023310000000BB
+:023311000000BA
+:023312000000B9
+:023313000000B8
+:023314000000B7
+:023315000000B6
+:023316000000B5
+:023317000000B4
+:023318000000B3
+:023319000000B2
+:02331A000000B1
+:02331B000000B0
+:02331C000000AF
+:02331D000000AE
+:02331E000000AD
+:02331F000000AC
+:023320000000AB
+:023321000000AA
+:023322000000A9
+:023323000000A8
+:023324000000A7
+:023325000000A6
+:023326000000A5
+:023327000000A4
+:023328000000A3
+:023329000000A2
+:02332A000000A1
+:02332B000000A0
+:02332C0000009F
+:02332D0000009E
+:02332E0000009D
+:02332F0000009C
+:0233300000009B
+:0233310000009A
+:02333200000099
+:02333300000098
+:02333400000097
+:02333500000096
+:02333600000095
+:02333700000094
+:02333800000093
+:02333900000092
+:02333A00000091
+:02333B00000090
+:02333C0000008F
+:02333D0000008E
+:02333E0000008D
+:02333F0000008C
+:0233400000008B
+:0233410000008A
+:02334200000089
+:02334300000088
+:02334400000087
+:02334500000086
+:02334600000085
+:02334700000084
+:02334800000083
+:02334900000082
+:02334A00000081
+:02334B00000080
+:02334C0000007F
+:02334D0000007E
+:02334E0000007D
+:02334F0000007C
+:0233500000007B
+:0233510000007A
+:02335200000079
+:02335300000078
+:02335400000077
+:02335500000076
+:02335600000075
+:02335700000074
+:02335800000073
+:02335900000072
+:02335A00000071
+:02335B00000070
+:02335C0000006F
+:02335D0000006E
+:02335E0000006D
+:02335F0000006C
+:0233600000006B
+:0233610000006A
+:02336200000069
+:02336300000068
+:02336400000067
+:02336500000066
+:02336600000065
+:02336700000064
+:02336800000063
+:02336900000062
+:02336A00000061
+:02336B00000060
+:02336C0000005F
+:02336D0000005E
+:02336E0000005D
+:02336F0000005C
+:0233700000005B
+:0233710000005A
+:02337200000059
+:02337300000058
+:02337400000057
+:02337500000056
+:02337600000055
+:02337700000054
+:02337800000053
+:02337900000052
+:02337A00000051
+:02337B00000050
+:02337C0000004F
+:02337D0000004E
+:02337E0000004D
+:02337F0000004C
+:0233800000004B
+:0233810000004A
+:02338200000049
+:02338300000048
+:02338400000047
+:02338500000046
+:02338600000045
+:02338700000044
+:02338800000043
+:02338900000042
+:02338A00000041
+:02338B00000040
+:02338C0000003F
+:02338D0000003E
+:02338E0000003D
+:02338F0000003C
+:0233900000003B
+:0233910000003A
+:02339200000039
+:02339300000038
+:02339400000037
+:02339500000036
+:02339600000035
+:02339700000034
+:02339800000033
+:02339900000032
+:02339A00000031
+:02339B00000030
+:02339C0000002F
+:02339D0000002E
+:02339E0000002D
+:02339F0000002C
+:0233A00000002B
+:0233A10000002A
+:0233A200000029
+:0233A300000028
+:0233A400000027
+:0233A500000026
+:0233A600000025
+:0233A700000024
+:0233A800000023
+:0233A900000022
+:0233AA00000021
+:0233AB00000020
+:0233AC0000001F
+:0233AD0000001E
+:0233AE0000001D
+:0233AF0000001C
+:0233B00000001B
+:0233B10000001A
+:0233B200000019
+:0233B300000018
+:0233B400000017
+:0233B500000016
+:0233B600000015
+:0233B700000014
+:0233B800000013
+:0233B900000012
+:0233BA00000011
+:0233BB00000010
+:0233BC0000000F
+:0233BD0000000E
+:0233BE0000000D
+:0233BF0000000C
+:0233C00000000B
+:0233C10000000A
+:0233C200000009
+:0233C300000008
+:0233C400000007
+:0233C500000006
+:0233C600000005
+:0233C700000004
+:0233C800000003
+:0233C900000002
+:0233CA00000001
+:0233CB00000000
+:0233CC000000FF
+:0233CD000000FE
+:0233CE000000FD
+:0233CF000000FC
+:0233D0000000FB
+:0233D1000000FA
+:0233D2000000F9
+:0233D3000000F8
+:0233D4000000F7
+:0233D5000000F6
+:0233D6000000F5
+:0233D7000000F4
+:0233D8000000F3
+:0233D9000000F2
+:0233DA000000F1
+:0233DB000000F0
+:0233DC000000EF
+:0233DD000000EE
+:0233DE000000ED
+:0233DF000000EC
+:0233E0000000EB
+:0233E1000000EA
+:0233E2000000E9
+:0233E3000000E8
+:0233E4000000E7
+:0233E5000000E6
+:0233E6000000E5
+:0233E7000000E4
+:0233E8000000E3
+:0233E9000000E2
+:0233EA000000E1
+:0233EB000000E0
+:0233EC000000DF
+:0233ED000000DE
+:0233EE000000DD
+:0233EF000000DC
+:0233F0000000DB
+:0233F1000000DA
+:0233F2000000D9
+:0233F3000000D8
+:0233F4000000D7
+:0233F5000000D6
+:0233F6000000D5
+:0233F7000000D4
+:0233F8000000D3
+:0233F9000000D2
+:0233FA000000D1
+:0233FB000000D0
+:0233FC000000CF
+:0233FD000000CE
+:0233FE000000CD
+:0233FF000000CC
+:023400000000CA
+:023401000000C9
+:023402000000C8
+:023403000000C7
+:023404000000C6
+:023405000000C5
+:023406000000C4
+:023407000000C3
+:023408000000C2
+:023409000000C1
+:02340A000000C0
+:02340B000000BF
+:02340C000000BE
+:02340D000000BD
+:02340E000000BC
+:02340F000000BB
+:023410000000BA
+:023411000000B9
+:023412000000B8
+:023413000000B7
+:023414000000B6
+:023415000000B5
+:023416000000B4
+:023417000000B3
+:023418000000B2
+:023419000000B1
+:02341A000000B0
+:02341B000000AF
+:02341C000000AE
+:02341D000000AD
+:02341E000000AC
+:02341F000000AB
+:023420000000AA
+:023421000000A9
+:023422000000A8
+:023423000000A7
+:023424000000A6
+:023425000000A5
+:023426000000A4
+:023427000000A3
+:023428000000A2
+:023429000000A1
+:02342A000000A0
+:02342B0000009F
+:02342C0000009E
+:02342D0000009D
+:02342E0000009C
+:02342F0000009B
+:0234300000009A
+:02343100000099
+:02343200000098
+:02343300000097
+:02343400000096
+:02343500000095
+:02343600000094
+:02343700000093
+:02343800000092
+:02343900000091
+:02343A00000090
+:02343B0000008F
+:02343C0000008E
+:02343D0000008D
+:02343E0000008C
+:02343F0000008B
+:0234400000008A
+:02344100000089
+:02344200000088
+:02344300000087
+:02344400000086
+:02344500000085
+:02344600000084
+:02344700000083
+:02344800000082
+:02344900000081
+:02344A00000080
+:02344B0000007F
+:02344C0000007E
+:02344D0000007D
+:02344E0000007C
+:02344F0000007B
+:0234500000007A
+:02345100000079
+:02345200000078
+:02345300000077
+:02345400000076
+:02345500000075
+:02345600000074
+:02345700000073
+:02345800000072
+:02345900000071
+:02345A00000070
+:02345B0000006F
+:02345C0000006E
+:02345D0000006D
+:02345E0000006C
+:02345F0000006B
+:0234600000006A
+:02346100000069
+:02346200000068
+:02346300000067
+:02346400000066
+:02346500000065
+:02346600000064
+:02346700000063
+:02346800000062
+:02346900000061
+:02346A00000060
+:02346B0000005F
+:02346C0000005E
+:02346D0000005D
+:02346E0000005C
+:02346F0000005B
+:0234700000005A
+:02347100000059
+:02347200000058
+:02347300000057
+:02347400000056
+:02347500000055
+:02347600000054
+:02347700000053
+:02347800000052
+:02347900000051
+:02347A00000050
+:02347B0000004F
+:02347C0000004E
+:02347D0000004D
+:02347E0000004C
+:02347F0000004B
+:0234800000004A
+:02348100000049
+:02348200000048
+:02348300000047
+:02348400000046
+:02348500000045
+:02348600000044
+:02348700000043
+:02348800000042
+:02348900000041
+:02348A00000040
+:02348B0000003F
+:02348C0000003E
+:02348D0000003D
+:02348E0000003C
+:02348F0000003B
+:0234900000003A
+:02349100000039
+:02349200000038
+:02349300000037
+:02349400000036
+:02349500000035
+:02349600000034
+:02349700000033
+:02349800000032
+:02349900000031
+:02349A00000030
+:02349B0000002F
+:02349C0000002E
+:02349D0000002D
+:02349E0000002C
+:02349F0000002B
+:0234A00000002A
+:0234A100000029
+:0234A200000028
+:0234A300000027
+:0234A400000026
+:0234A500000025
+:0234A600000024
+:0234A700000023
+:0234A800000022
+:0234A900000021
+:0234AA00000020
+:0234AB0000001F
+:0234AC0000001E
+:0234AD0000001D
+:0234AE0000001C
+:0234AF0000001B
+:0234B00000001A
+:0234B100000019
+:0234B200000018
+:0234B300000017
+:0234B400000016
+:0234B500000015
+:0234B600000014
+:0234B700000013
+:0234B800000012
+:0234B900000011
+:0234BA00000010
+:0234BB0000000F
+:0234BC0000000E
+:0234BD0000000D
+:0234BE0000000C
+:0234BF0000000B
+:0234C00000000A
+:0234C100000009
+:0234C200000008
+:0234C300000007
+:0234C400000006
+:0234C500000005
+:0234C600000004
+:0234C700000003
+:0234C800000002
+:0234C900000001
+:0234CA00000000
+:0234CB000000FF
+:0234CC000000FE
+:0234CD000000FD
+:0234CE000000FC
+:0234CF000000FB
+:0234D0000000FA
+:0234D1000000F9
+:0234D2000000F8
+:0234D3000000F7
+:0234D4000000F6
+:0234D5000000F5
+:0234D6000000F4
+:0234D7000000F3
+:0234D8000000F2
+:0234D9000000F1
+:0234DA000000F0
+:0234DB000000EF
+:0234DC000000EE
+:0234DD000000ED
+:0234DE000000EC
+:0234DF000000EB
+:0234E0000000EA
+:0234E1000000E9
+:0234E2000000E8
+:0234E3000000E7
+:0234E4000000E6
+:0234E5000000E5
+:0234E6000000E4
+:0234E7000000E3
+:0234E8000000E2
+:0234E9000000E1
+:0234EA000000E0
+:0234EB000000DF
+:0234EC000000DE
+:0234ED000000DD
+:0234EE000000DC
+:0234EF000000DB
+:0234F0000000DA
+:0234F1000000D9
+:0234F2000000D8
+:0234F3000000D7
+:0234F4000000D6
+:0234F5000000D5
+:0234F6000000D4
+:0234F7000000D3
+:0234F8000000D2
+:0234F9000000D1
+:0234FA000000D0
+:0234FB000000CF
+:0234FC000000CE
+:0234FD000000CD
+:0234FE000000CC
+:0234FF000000CB
+:023500000000C9
+:023501000000C8
+:023502000000C7
+:023503000000C6
+:023504000000C5
+:023505000000C4
+:023506000000C3
+:023507000000C2
+:023508000000C1
+:023509000000C0
+:02350A000000BF
+:02350B000000BE
+:02350C000000BD
+:02350D000000BC
+:02350E000000BB
+:02350F000000BA
+:023510000000B9
+:023511000000B8
+:023512000000B7
+:023513000000B6
+:023514000000B5
+:023515000000B4
+:023516000000B3
+:023517000000B2
+:023518000000B1
+:023519000000B0
+:02351A000000AF
+:02351B000000AE
+:02351C000000AD
+:02351D000000AC
+:02351E000000AB
+:02351F000000AA
+:023520000000A9
+:023521000000A8
+:023522000000A7
+:023523000000A6
+:023524000000A5
+:023525000000A4
+:023526000000A3
+:023527000000A2
+:023528000000A1
+:023529000000A0
+:02352A0000009F
+:02352B0000009E
+:02352C0000009D
+:02352D0000009C
+:02352E0000009B
+:02352F0000009A
+:02353000000099
+:02353100000098
+:02353200000097
+:02353300000096
+:02353400000095
+:02353500000094
+:02353600000093
+:02353700000092
+:02353800000091
+:02353900000090
+:02353A0000008F
+:02353B0000008E
+:02353C0000008D
+:02353D0000008C
+:02353E0000008B
+:02353F0000008A
+:02354000000089
+:02354100000088
+:02354200000087
+:02354300000086
+:02354400000085
+:02354500000084
+:02354600000083
+:02354700000082
+:02354800000081
+:02354900000080
+:02354A0000007F
+:02354B0000007E
+:02354C0000007D
+:02354D0000007C
+:02354E0000007B
+:02354F0000007A
+:02355000000079
+:02355100000078
+:02355200000077
+:02355300000076
+:02355400000075
+:02355500000074
+:02355600000073
+:02355700000072
+:02355800000071
+:02355900000070
+:02355A0000006F
+:02355B0000006E
+:02355C0000006D
+:02355D0000006C
+:02355E0000006B
+:02355F0000006A
+:02356000000069
+:02356100000068
+:02356200000067
+:02356300000066
+:02356400000065
+:02356500000064
+:02356600000063
+:02356700000062
+:02356800000061
+:02356900000060
+:02356A0000005F
+:02356B0000005E
+:02356C0000005D
+:02356D0000005C
+:02356E0000005B
+:02356F0000005A
+:02357000000059
+:02357100000058
+:02357200000057
+:02357300000056
+:02357400000055
+:02357500000054
+:02357600000053
+:02357700000052
+:02357800000051
+:02357900000050
+:02357A0000004F
+:02357B0000004E
+:02357C0000004D
+:02357D0000004C
+:02357E0000004B
+:02357F0000004A
+:02358000000049
+:02358100000048
+:02358200000047
+:02358300000046
+:02358400000045
+:02358500000044
+:02358600000043
+:02358700000042
+:02358800000041
+:02358900000040
+:02358A0000003F
+:02358B0000003E
+:02358C0000003D
+:02358D0000003C
+:02358E0000003B
+:02358F0000003A
+:02359000000039
+:02359100000038
+:02359200000037
+:02359300000036
+:02359400000035
+:02359500000034
+:02359600000033
+:02359700000032
+:02359800000031
+:02359900000030
+:02359A0000002F
+:02359B0000002E
+:02359C0000002D
+:02359D0000002C
+:02359E0000002B
+:02359F0000002A
+:0235A000000029
+:0235A100000028
+:0235A200000027
+:0235A300000026
+:0235A400000025
+:0235A500000024
+:0235A600000023
+:0235A700000022
+:0235A800000021
+:0235A900000020
+:0235AA0000001F
+:0235AB0000001E
+:0235AC0000001D
+:0235AD0000001C
+:0235AE0000001B
+:0235AF0000001A
+:0235B000000019
+:0235B100000018
+:0235B200000017
+:0235B300000016
+:0235B400000015
+:0235B500000014
+:0235B600000013
+:0235B700000012
+:0235B800000011
+:0235B900000010
+:0235BA0000000F
+:0235BB0000000E
+:0235BC0000000D
+:0235BD0000000C
+:0235BE0000000B
+:0235BF0000000A
+:0235C000000009
+:0235C100000008
+:0235C200000007
+:0235C300000006
+:0235C400000005
+:0235C500000004
+:0235C600000003
+:0235C700000002
+:0235C800000001
+:0235C900000000
+:0235CA000000FF
+:0235CB000000FE
+:0235CC000000FD
+:0235CD000000FC
+:0235CE000000FB
+:0235CF000000FA
+:0235D0000000F9
+:0235D1000000F8
+:0235D2000000F7
+:0235D3000000F6
+:0235D4000000F5
+:0235D5000000F4
+:0235D6000000F3
+:0235D7000000F2
+:0235D8000000F1
+:0235D9000000F0
+:0235DA000000EF
+:0235DB000000EE
+:0235DC000000ED
+:0235DD000000EC
+:0235DE000000EB
+:0235DF000000EA
+:0235E0000000E9
+:0235E1000000E8
+:0235E2000000E7
+:0235E3000000E6
+:0235E4000000E5
+:0235E5000000E4
+:0235E6000000E3
+:0235E7000000E2
+:0235E8000000E1
+:0235E9000000E0
+:0235EA000000DF
+:0235EB000000DE
+:0235EC000000DD
+:0235ED000000DC
+:0235EE000000DB
+:0235EF000000DA
+:0235F0000000D9
+:0235F1000000D8
+:0235F2000000D7
+:0235F3000000D6
+:0235F4000000D5
+:0235F5000000D4
+:0235F6000000D3
+:0235F7000000D2
+:0235F8000000D1
+:0235F9000000D0
+:0235FA000000CF
+:0235FB000000CE
+:0235FC000000CD
+:0235FD000000CC
+:0235FE000000CB
+:0235FF000000CA
+:023600000000C8
+:023601000000C7
+:023602000000C6
+:023603000000C5
+:023604000000C4
+:023605000000C3
+:023606000000C2
+:023607000000C1
+:023608000000C0
+:023609000000BF
+:02360A000000BE
+:02360B000000BD
+:02360C000000BC
+:02360D000000BB
+:02360E000000BA
+:02360F000000B9
+:023610000000B8
+:023611000000B7
+:023612000000B6
+:023613000000B5
+:023614000000B4
+:023615000000B3
+:023616000000B2
+:023617000000B1
+:023618000000B0
+:023619000000AF
+:02361A000000AE
+:02361B000000AD
+:02361C000000AC
+:02361D000000AB
+:02361E000000AA
+:02361F000000A9
+:023620000000A8
+:023621000000A7
+:023622000000A6
+:023623000000A5
+:023624000000A4
+:023625000000A3
+:023626000000A2
+:023627000000A1
+:023628000000A0
+:0236290000009F
+:02362A0000009E
+:02362B0000009D
+:02362C0000009C
+:02362D0000009B
+:02362E0000009A
+:02362F00000099
+:02363000000098
+:02363100000097
+:02363200000096
+:02363300000095
+:02363400000094
+:02363500000093
+:02363600000092
+:02363700000091
+:02363800000090
+:0236390000008F
+:02363A0000008E
+:02363B0000008D
+:02363C0000008C
+:02363D0000008B
+:02363E0000008A
+:02363F00000089
+:02364000000088
+:02364100000087
+:02364200000086
+:02364300000085
+:02364400000084
+:02364500000083
+:02364600000082
+:02364700000081
+:02364800000080
+:0236490000007F
+:02364A0000007E
+:02364B0000007D
+:02364C0000007C
+:02364D0000007B
+:02364E0000007A
+:02364F00000079
+:02365000000078
+:02365100000077
+:02365200000076
+:02365300000075
+:02365400000074
+:02365500000073
+:02365600000072
+:02365700000071
+:02365800000070
+:0236590000006F
+:02365A0000006E
+:02365B0000006D
+:02365C0000006C
+:02365D0000006B
+:02365E0000006A
+:02365F00000069
+:02366000000068
+:02366100000067
+:02366200000066
+:02366300000065
+:02366400000064
+:02366500000063
+:02366600000062
+:02366700000061
+:02366800000060
+:0236690000005F
+:02366A0000005E
+:02366B0000005D
+:02366C0000005C
+:02366D0000005B
+:02366E0000005A
+:02366F00000059
+:02367000000058
+:02367100000057
+:02367200000056
+:02367300000055
+:02367400000054
+:02367500000053
+:02367600000052
+:02367700000051
+:02367800000050
+:0236790000004F
+:02367A0000004E
+:02367B0000004D
+:02367C0000004C
+:02367D0000004B
+:02367E0000004A
+:02367F00000049
+:02368000000048
+:02368100000047
+:02368200000046
+:02368300000045
+:02368400000044
+:02368500000043
+:02368600000042
+:02368700000041
+:02368800000040
+:0236890000003F
+:02368A0000003E
+:02368B0000003D
+:02368C0000003C
+:02368D0000003B
+:02368E0000003A
+:02368F00000039
+:02369000000038
+:02369100000037
+:02369200000036
+:02369300000035
+:02369400000034
+:02369500000033
+:02369600000032
+:02369700000031
+:02369800000030
+:0236990000002F
+:02369A0000002E
+:02369B0000002D
+:02369C0000002C
+:02369D0000002B
+:02369E0000002A
+:02369F00000029
+:0236A000000028
+:0236A100000027
+:0236A200000026
+:0236A300000025
+:0236A400000024
+:0236A500000023
+:0236A600000022
+:0236A700000021
+:0236A800000020
+:0236A90000001F
+:0236AA0000001E
+:0236AB0000001D
+:0236AC0000001C
+:0236AD0000001B
+:0236AE0000001A
+:0236AF00000019
+:0236B000000018
+:0236B100000017
+:0236B200000016
+:0236B300000015
+:0236B400000014
+:0236B500000013
+:0236B600000012
+:0236B700000011
+:0236B800000010
+:0236B90000000F
+:0236BA0000000E
+:0236BB0000000D
+:0236BC0000000C
+:0236BD0000000B
+:0236BE0000000A
+:0236BF00000009
+:0236C000000008
+:0236C100000007
+:0236C200000006
+:0236C300000005
+:0236C400000004
+:0236C500000003
+:0236C600000002
+:0236C700000001
+:0236C800000000
+:0236C9000000FF
+:0236CA000000FE
+:0236CB000000FD
+:0236CC000000FC
+:0236CD000000FB
+:0236CE000000FA
+:0236CF000000F9
+:0236D0000000F8
+:0236D1000000F7
+:0236D2000000F6
+:0236D3000000F5
+:0236D4000000F4
+:0236D5000000F3
+:0236D6000000F2
+:0236D7000000F1
+:0236D8000000F0
+:0236D9000000EF
+:0236DA000000EE
+:0236DB000000ED
+:0236DC000000EC
+:0236DD000000EB
+:0236DE000000EA
+:0236DF000000E9
+:0236E0000000E8
+:0236E1000000E7
+:0236E2000000E6
+:0236E3000000E5
+:0236E4000000E4
+:0236E5000000E3
+:0236E6000000E2
+:0236E7000000E1
+:0236E8000000E0
+:0236E9000000DF
+:0236EA000000DE
+:0236EB000000DD
+:0236EC000000DC
+:0236ED000000DB
+:0236EE000000DA
+:0236EF000000D9
+:0236F0000000D8
+:0236F1000000D7
+:0236F2000000D6
+:0236F3000000D5
+:0236F4000000D4
+:0236F5000000D3
+:0236F6000000D2
+:0236F7000000D1
+:0236F8000000D0
+:0236F9000000CF
+:0236FA000000CE
+:0236FB000000CD
+:0236FC000000CC
+:0236FD000000CB
+:0236FE000000CA
+:0236FF000000C9
+:023700000000C7
+:023701000000C6
+:023702000000C5
+:023703000000C4
+:023704000000C3
+:023705000000C2
+:023706000000C1
+:023707000000C0
+:023708000000BF
+:023709000000BE
+:02370A000000BD
+:02370B000000BC
+:02370C000000BB
+:02370D000000BA
+:02370E000000B9
+:02370F000000B8
+:023710000000B7
+:023711000000B6
+:023712000000B5
+:023713000000B4
+:023714000000B3
+:023715000000B2
+:023716000000B1
+:023717000000B0
+:023718000000AF
+:023719000000AE
+:02371A000000AD
+:02371B000000AC
+:02371C000000AB
+:02371D000000AA
+:02371E000000A9
+:02371F000000A8
+:023720000000A7
+:023721000000A6
+:023722000000A5
+:023723000000A4
+:023724000000A3
+:023725000000A2
+:023726000000A1
+:023727000000A0
+:0237280000009F
+:0237290000009E
+:02372A0000009D
+:02372B0000009C
+:02372C0000009B
+:02372D0000009A
+:02372E00000099
+:02372F00000098
+:02373000000097
+:02373100000096
+:02373200000095
+:02373300000094
+:02373400000093
+:02373500000092
+:02373600000091
+:02373700000090
+:0237380000008F
+:0237390000008E
+:02373A0000008D
+:02373B0000008C
+:02373C0000008B
+:02373D0000008A
+:02373E00000089
+:02373F00000088
+:02374000000087
+:02374100000086
+:02374200000085
+:02374300000084
+:02374400000083
+:02374500000082
+:02374600000081
+:02374700000080
+:0237480000007F
+:0237490000007E
+:02374A0000007D
+:02374B0000007C
+:02374C0000007B
+:02374D0000007A
+:02374E00000079
+:02374F00000078
+:02375000000077
+:02375100000076
+:02375200000075
+:02375300000074
+:02375400000073
+:02375500000072
+:02375600000071
+:02375700000070
+:0237580000006F
+:0237590000006E
+:02375A0000006D
+:02375B0000006C
+:02375C0000006B
+:02375D0000006A
+:02375E00000069
+:02375F00000068
+:02376000000067
+:02376100000066
+:02376200000065
+:02376300000064
+:02376400000063
+:02376500000062
+:02376600000061
+:02376700000060
+:0237680000005F
+:0237690000005E
+:02376A0000005D
+:02376B0000005C
+:02376C0000005B
+:02376D0000005A
+:02376E00000059
+:02376F00000058
+:02377000000057
+:02377100000056
+:02377200000055
+:02377300000054
+:02377400000053
+:02377500000052
+:02377600000051
+:02377700000050
+:0237780000004F
+:0237790000004E
+:02377A0000004D
+:02377B0000004C
+:02377C0000004B
+:02377D0000004A
+:02377E00000049
+:02377F00000048
+:02378000000047
+:02378100000046
+:02378200000045
+:02378300000044
+:02378400000043
+:02378500000042
+:02378600000041
+:02378700000040
+:0237880000003F
+:0237890000003E
+:02378A0000003D
+:02378B0000003C
+:02378C0000003B
+:02378D0000003A
+:02378E00000039
+:02378F00000038
+:02379000000037
+:02379100000036
+:02379200000035
+:02379300000034
+:02379400000033
+:02379500000032
+:02379600000031
+:02379700000030
+:0237980000002F
+:0237990000002E
+:02379A0000002D
+:02379B0000002C
+:02379C0000002B
+:02379D0000002A
+:02379E00000029
+:02379F00000028
+:0237A000000027
+:0237A100000026
+:0237A200000025
+:0237A300000024
+:0237A400000023
+:0237A500000022
+:0237A600000021
+:0237A700000020
+:0237A80000001F
+:0237A90000001E
+:0237AA0000001D
+:0237AB0000001C
+:0237AC0000001B
+:0237AD0000001A
+:0237AE00000019
+:0237AF00000018
+:0237B000000017
+:0237B100000016
+:0237B200000015
+:0237B300000014
+:0237B400000013
+:0237B500000012
+:0237B600000011
+:0237B700000010
+:0237B80000000F
+:0237B90000000E
+:0237BA0000000D
+:0237BB0000000C
+:0237BC0000000B
+:0237BD0000000A
+:0237BE00000009
+:0237BF00000008
+:0237C000000007
+:0237C100000006
+:0237C200000005
+:0237C300000004
+:0237C400000003
+:0237C500000002
+:0237C600000001
+:0237C700000000
+:0237C8000000FF
+:0237C9000000FE
+:0237CA000000FD
+:0237CB000000FC
+:0237CC000000FB
+:0237CD000000FA
+:0237CE000000F9
+:0237CF000000F8
+:0237D0000000F7
+:0237D1000000F6
+:0237D2000000F5
+:0237D3000000F4
+:0237D4000000F3
+:0237D5000000F2
+:0237D6000000F1
+:0237D7000000F0
+:0237D8000000EF
+:0237D9000000EE
+:0237DA000000ED
+:0237DB000000EC
+:0237DC000000EB
+:0237DD000000EA
+:0237DE000000E9
+:0237DF000000E8
+:0237E0000000E7
+:0237E1000000E6
+:0237E2000000E5
+:0237E3000000E4
+:0237E4000000E3
+:0237E5000000E2
+:0237E6000000E1
+:0237E7000000E0
+:0237E8000000DF
+:0237E9000000DE
+:0237EA000000DD
+:0237EB000000DC
+:0237EC000000DB
+:0237ED000000DA
+:0237EE000000D9
+:0237EF000000D8
+:0237F0000000D7
+:0237F1000000D6
+:0237F2000000D5
+:0237F3000000D4
+:0237F4000000D3
+:0237F5000000D2
+:0237F6000000D1
+:0237F7000000D0
+:0237F8000000CF
+:0237F9000000CE
+:0237FA000000CD
+:0237FB000000CC
+:0237FC000000CB
+:0237FD000000CA
+:0237FE000000C9
+:0237FF000000C8
+:023800000000C6
+:023801000000C5
+:023802000000C4
+:023803000000C3
+:023804000000C2
+:023805000000C1
+:023806000000C0
+:023807000000BF
+:023808000000BE
+:023809000000BD
+:02380A000000BC
+:02380B000000BB
+:02380C000000BA
+:02380D000000B9
+:02380E000000B8
+:02380F000000B7
+:023810000000B6
+:023811000000B5
+:023812000000B4
+:023813000000B3
+:023814000000B2
+:023815000000B1
+:023816000000B0
+:023817000000AF
+:023818000000AE
+:023819000000AD
+:02381A000000AC
+:02381B000000AB
+:02381C000000AA
+:02381D000000A9
+:02381E000000A8
+:02381F000000A7
+:023820000000A6
+:023821000000A5
+:023822000000A4
+:023823000000A3
+:023824000000A2
+:023825000000A1
+:023826000000A0
+:0238270000009F
+:0238280000009E
+:0238290000009D
+:02382A0000009C
+:02382B0000009B
+:02382C0000009A
+:02382D00000099
+:02382E00000098
+:02382F00000097
+:02383000000096
+:02383100000095
+:02383200000094
+:02383300000093
+:02383400000092
+:02383500000091
+:02383600000090
+:0238370000008F
+:0238380000008E
+:0238390000008D
+:02383A0000008C
+:02383B0000008B
+:02383C0000008A
+:02383D00000089
+:02383E00000088
+:02383F00000087
+:02384000000086
+:02384100000085
+:02384200000084
+:02384300000083
+:02384400000082
+:02384500000081
+:02384600000080
+:0238470000007F
+:0238480000007E
+:0238490000007D
+:02384A0000007C
+:02384B0000007B
+:02384C0000007A
+:02384D00000079
+:02384E00000078
+:02384F00000077
+:02385000000076
+:02385100000075
+:02385200000074
+:02385300000073
+:02385400000072
+:02385500000071
+:02385600000070
+:0238570000006F
+:0238580000006E
+:0238590000006D
+:02385A0000006C
+:02385B0000006B
+:02385C0000006A
+:02385D00000069
+:02385E00000068
+:02385F00000067
+:02386000000066
+:02386100000065
+:02386200000064
+:02386300000063
+:02386400000062
+:02386500000061
+:02386600000060
+:0238670000005F
+:0238680000005E
+:0238690000005D
+:02386A0000005C
+:02386B0000005B
+:02386C0000005A
+:02386D00000059
+:02386E00000058
+:02386F00000057
+:02387000000056
+:02387100000055
+:02387200000054
+:02387300000053
+:02387400000052
+:02387500000051
+:02387600000050
+:0238770000004F
+:0238780000004E
+:0238790000004D
+:02387A0000004C
+:02387B0000004B
+:02387C0000004A
+:02387D00000049
+:02387E00000048
+:02387F00000047
+:02388000000046
+:02388100000045
+:02388200000044
+:02388300000043
+:02388400000042
+:02388500000041
+:02388600000040
+:0238870000003F
+:0238880000003E
+:0238890000003D
+:02388A0000003C
+:02388B0000003B
+:02388C0000003A
+:02388D00000039
+:02388E00000038
+:02388F00000037
+:02389000000036
+:02389100000035
+:02389200000034
+:02389300000033
+:02389400000032
+:02389500000031
+:02389600000030
+:0238970000002F
+:0238980000002E
+:0238990000002D
+:02389A0000002C
+:02389B0000002B
+:02389C0000002A
+:02389D00000029
+:02389E00000028
+:02389F00000027
+:0238A000000026
+:0238A100000025
+:0238A200000024
+:0238A300000023
+:0238A400000022
+:0238A500000021
+:0238A600000020
+:0238A70000001F
+:0238A80000001E
+:0238A90000001D
+:0238AA0000001C
+:0238AB0000001B
+:0238AC0000001A
+:0238AD00000019
+:0238AE00000018
+:0238AF00000017
+:0238B000000016
+:0238B100000015
+:0238B200000014
+:0238B300000013
+:0238B400000012
+:0238B500000011
+:0238B600000010
+:0238B70000000F
+:0238B80000000E
+:0238B90000000D
+:0238BA0000000C
+:0238BB0000000B
+:0238BC0000000A
+:0238BD00000009
+:0238BE00000008
+:0238BF00000007
+:0238C000000006
+:0238C100000005
+:0238C200000004
+:0238C300000003
+:0238C400000002
+:0238C500000001
+:0238C600000000
+:0238C7000000FF
+:0238C8000000FE
+:0238C9000000FD
+:0238CA000000FC
+:0238CB000000FB
+:0238CC000000FA
+:0238CD000000F9
+:0238CE000000F8
+:0238CF000000F7
+:0238D0000000F6
+:0238D1000000F5
+:0238D2000000F4
+:0238D3000000F3
+:0238D4000000F2
+:0238D5000000F1
+:0238D6000000F0
+:0238D7000000EF
+:0238D8000000EE
+:0238D9000000ED
+:0238DA000000EC
+:0238DB000000EB
+:0238DC000000EA
+:0238DD000000E9
+:0238DE000000E8
+:0238DF000000E7
+:0238E0000000E6
+:0238E1000000E5
+:0238E2000000E4
+:0238E3000000E3
+:0238E4000000E2
+:0238E5000000E1
+:0238E6000000E0
+:0238E7000000DF
+:0238E8000000DE
+:0238E9000000DD
+:0238EA000000DC
+:0238EB000000DB
+:0238EC000000DA
+:0238ED000000D9
+:0238EE000000D8
+:0238EF000000D7
+:0238F0000000D6
+:0238F1000000D5
+:0238F2000000D4
+:0238F3000000D3
+:0238F4000000D2
+:0238F5000000D1
+:0238F6000000D0
+:0238F7000000CF
+:0238F8000000CE
+:0238F9000000CD
+:0238FA000000CC
+:0238FB000000CB
+:0238FC000000CA
+:0238FD000000C9
+:0238FE000000C8
+:0238FF000000C7
+:023900000000C5
+:023901000000C4
+:023902000000C3
+:023903000000C2
+:023904000000C1
+:023905000000C0
+:023906000000BF
+:023907000000BE
+:023908000000BD
+:023909000000BC
+:02390A000000BB
+:02390B000000BA
+:02390C000000B9
+:02390D000000B8
+:02390E000000B7
+:02390F000000B6
+:023910000000B5
+:023911000000B4
+:023912000000B3
+:023913000000B2
+:023914000000B1
+:023915000000B0
+:023916000000AF
+:023917000000AE
+:023918000000AD
+:023919000000AC
+:02391A000000AB
+:02391B000000AA
+:02391C000000A9
+:02391D000000A8
+:02391E000000A7
+:02391F000000A6
+:023920000000A5
+:023921000000A4
+:023922000000A3
+:023923000000A2
+:023924000000A1
+:023925000000A0
+:0239260000009F
+:0239270000009E
+:0239280000009D
+:0239290000009C
+:02392A0000009B
+:02392B0000009A
+:02392C00000099
+:02392D00000098
+:02392E00000097
+:02392F00000096
+:02393000000095
+:02393100000094
+:02393200000093
+:02393300000092
+:02393400000091
+:02393500000090
+:0239360000008F
+:0239370000008E
+:0239380000008D
+:0239390000008C
+:02393A0000008B
+:02393B0000008A
+:02393C00000089
+:02393D00000088
+:02393E00000087
+:02393F00000086
+:02394000000085
+:02394100000084
+:02394200000083
+:02394300000082
+:02394400000081
+:02394500000080
+:0239460000007F
+:0239470000007E
+:0239480000007D
+:0239490000007C
+:02394A0000007B
+:02394B0000007A
+:02394C00000079
+:02394D00000078
+:02394E00000077
+:02394F00000076
+:02395000000075
+:02395100000074
+:02395200000073
+:02395300000072
+:02395400000071
+:02395500000070
+:0239560000006F
+:0239570000006E
+:0239580000006D
+:0239590000006C
+:02395A0000006B
+:02395B0000006A
+:02395C00000069
+:02395D00000068
+:02395E00000067
+:02395F00000066
+:02396000000065
+:02396100000064
+:02396200000063
+:02396300000062
+:02396400000061
+:02396500000060
+:0239660000005F
+:0239670000005E
+:0239680000005D
+:0239690000005C
+:02396A0000005B
+:02396B0000005A
+:02396C00000059
+:02396D00000058
+:02396E00000057
+:02396F00000056
+:02397000000055
+:02397100000054
+:02397200000053
+:02397300000052
+:02397400000051
+:02397500000050
+:0239760000004F
+:0239770000004E
+:0239780000004D
+:0239790000004C
+:02397A0000004B
+:02397B0000004A
+:02397C00000049
+:02397D00000048
+:02397E00000047
+:02397F00000046
+:02398000000045
+:02398100000044
+:02398200000043
+:02398300000042
+:02398400000041
+:02398500000040
+:0239860000003F
+:0239870000003E
+:0239880000003D
+:0239890000003C
+:02398A0000003B
+:02398B0000003A
+:02398C00000039
+:02398D00000038
+:02398E00000037
+:02398F00000036
+:02399000000035
+:02399100000034
+:02399200000033
+:02399300000032
+:02399400000031
+:02399500000030
+:0239960000002F
+:0239970000002E
+:0239980000002D
+:0239990000002C
+:02399A0000002B
+:02399B0000002A
+:02399C00000029
+:02399D00000028
+:02399E00000027
+:02399F00000026
+:0239A000000025
+:0239A100000024
+:0239A200000023
+:0239A300000022
+:0239A400000021
+:0239A500000020
+:0239A60000001F
+:0239A70000001E
+:0239A80000001D
+:0239A90000001C
+:0239AA0000001B
+:0239AB0000001A
+:0239AC00000019
+:0239AD00000018
+:0239AE00000017
+:0239AF00000016
+:0239B000000015
+:0239B100000014
+:0239B200000013
+:0239B300000012
+:0239B400000011
+:0239B500000010
+:0239B60000000F
+:0239B70000000E
+:0239B80000000D
+:0239B90000000C
+:0239BA0000000B
+:0239BB0000000A
+:0239BC00000009
+:0239BD00000008
+:0239BE00000007
+:0239BF00000006
+:0239C000000005
+:0239C100000004
+:0239C200000003
+:0239C300000002
+:0239C400000001
+:0239C500000000
+:0239C6000000FF
+:0239C7000000FE
+:0239C8000000FD
+:0239C9000000FC
+:0239CA000000FB
+:0239CB000000FA
+:0239CC000000F9
+:0239CD000000F8
+:0239CE000000F7
+:0239CF000000F6
+:0239D0000000F5
+:0239D1000000F4
+:0239D2000000F3
+:0239D3000000F2
+:0239D4000000F1
+:0239D5000000F0
+:0239D6000000EF
+:0239D7000000EE
+:0239D8000000ED
+:0239D9000000EC
+:0239DA000000EB
+:0239DB000000EA
+:0239DC000000E9
+:0239DD000000E8
+:0239DE000000E7
+:0239DF000000E6
+:0239E0000000E5
+:0239E1000000E4
+:0239E2000000E3
+:0239E3000000E2
+:0239E4000000E1
+:0239E5000000E0
+:0239E6000000DF
+:0239E7000000DE
+:0239E8000000DD
+:0239E9000000DC
+:0239EA000000DB
+:0239EB000000DA
+:0239EC000000D9
+:0239ED000000D8
+:0239EE000000D7
+:0239EF000000D6
+:0239F0000000D5
+:0239F1000000D4
+:0239F2000000D3
+:0239F3000000D2
+:0239F4000000D1
+:0239F5000000D0
+:0239F6000000CF
+:0239F7000000CE
+:0239F8000000CD
+:0239F9000000CC
+:0239FA000000CB
+:0239FB000000CA
+:0239FC000000C9
+:0239FD000000C8
+:0239FE000000C7
+:0239FF000000C6
+:023A00000000C4
+:023A01000000C3
+:023A02000000C2
+:023A03000000C1
+:023A04000000C0
+:023A05000000BF
+:023A06000000BE
+:023A07000000BD
+:023A08000000BC
+:023A09000000BB
+:023A0A000000BA
+:023A0B000000B9
+:023A0C000000B8
+:023A0D000000B7
+:023A0E000000B6
+:023A0F000000B5
+:023A10000000B4
+:023A11000000B3
+:023A12000000B2
+:023A13000000B1
+:023A14000000B0
+:023A15000000AF
+:023A16000000AE
+:023A17000000AD
+:023A18000000AC
+:023A19000000AB
+:023A1A000000AA
+:023A1B000000A9
+:023A1C000000A8
+:023A1D000000A7
+:023A1E000000A6
+:023A1F000000A5
+:023A20000000A4
+:023A21000000A3
+:023A22000000A2
+:023A23000000A1
+:023A24000000A0
+:023A250000009F
+:023A260000009E
+:023A270000009D
+:023A280000009C
+:023A290000009B
+:023A2A0000009A
+:023A2B00000099
+:023A2C00000098
+:023A2D00000097
+:023A2E00000096
+:023A2F00000095
+:023A3000000094
+:023A3100000093
+:023A3200000092
+:023A3300000091
+:023A3400000090
+:023A350000008F
+:023A360000008E
+:023A370000008D
+:023A380000008C
+:023A390000008B
+:023A3A0000008A
+:023A3B00000089
+:023A3C00000088
+:023A3D00000087
+:023A3E00000086
+:023A3F00000085
+:023A4000000084
+:023A4100000083
+:023A4200000082
+:023A4300000081
+:023A4400000080
+:023A450000007F
+:023A460000007E
+:023A470000007D
+:023A480000007C
+:023A490000007B
+:023A4A0000007A
+:023A4B00000079
+:023A4C00000078
+:023A4D00000077
+:023A4E00000076
+:023A4F00000075
+:023A5000000074
+:023A5100000073
+:023A5200000072
+:023A5300000071
+:023A5400000070
+:023A550000006F
+:023A560000006E
+:023A570000006D
+:023A580000006C
+:023A590000006B
+:023A5A0000006A
+:023A5B00000069
+:023A5C00000068
+:023A5D00000067
+:023A5E00000066
+:023A5F00000065
+:023A6000000064
+:023A6100000063
+:023A6200000062
+:023A6300000061
+:023A6400000060
+:023A650000005F
+:023A660000005E
+:023A670000005D
+:023A680000005C
+:023A690000005B
+:023A6A0000005A
+:023A6B00000059
+:023A6C00000058
+:023A6D00000057
+:023A6E00000056
+:023A6F00000055
+:023A7000000054
+:023A7100000053
+:023A7200000052
+:023A7300000051
+:023A7400000050
+:023A750000004F
+:023A760000004E
+:023A770000004D
+:023A780000004C
+:023A790000004B
+:023A7A0000004A
+:023A7B00000049
+:023A7C00000048
+:023A7D00000047
+:023A7E00000046
+:023A7F00000045
+:023A8000000044
+:023A8100000043
+:023A8200000042
+:023A8300000041
+:023A8400000040
+:023A850000003F
+:023A860000003E
+:023A870000003D
+:023A880000003C
+:023A890000003B
+:023A8A0000003A
+:023A8B00000039
+:023A8C00000038
+:023A8D00000037
+:023A8E00000036
+:023A8F00000035
+:023A9000000034
+:023A9100000033
+:023A9200000032
+:023A9300000031
+:023A9400000030
+:023A950000002F
+:023A960000002E
+:023A970000002D
+:023A980000002C
+:023A990000002B
+:023A9A0000002A
+:023A9B00000029
+:023A9C00000028
+:023A9D00000027
+:023A9E00000026
+:023A9F00000025
+:023AA000000024
+:023AA100000023
+:023AA200000022
+:023AA300000021
+:023AA400000020
+:023AA50000001F
+:023AA60000001E
+:023AA70000001D
+:023AA80000001C
+:023AA90000001B
+:023AAA0000001A
+:023AAB00000019
+:023AAC00000018
+:023AAD00000017
+:023AAE00000016
+:023AAF00000015
+:023AB000000014
+:023AB100000013
+:023AB200000012
+:023AB300000011
+:023AB400000010
+:023AB50000000F
+:023AB60000000E
+:023AB70000000D
+:023AB80000000C
+:023AB90000000B
+:023ABA0000000A
+:023ABB00000009
+:023ABC00000008
+:023ABD00000007
+:023ABE00000006
+:023ABF00000005
+:023AC000000004
+:023AC100000003
+:023AC200000002
+:023AC300000001
+:023AC400000000
+:023AC5000000FF
+:023AC6000000FE
+:023AC7000000FD
+:023AC8000000FC
+:023AC9000000FB
+:023ACA000000FA
+:023ACB000000F9
+:023ACC000000F8
+:023ACD000000F7
+:023ACE000000F6
+:023ACF000000F5
+:023AD0000000F4
+:023AD1000000F3
+:023AD2000000F2
+:023AD3000000F1
+:023AD4000000F0
+:023AD5000000EF
+:023AD6000000EE
+:023AD7000000ED
+:023AD8000000EC
+:023AD9000000EB
+:023ADA000000EA
+:023ADB000000E9
+:023ADC000000E8
+:023ADD000000E7
+:023ADE000000E6
+:023ADF000000E5
+:023AE0000000E4
+:023AE1000000E3
+:023AE2000000E2
+:023AE3000000E1
+:023AE4000000E0
+:023AE5000000DF
+:023AE6000000DE
+:023AE7000000DD
+:023AE8000000DC
+:023AE9000000DB
+:023AEA000000DA
+:023AEB000000D9
+:023AEC000000D8
+:023AED000000D7
+:023AEE000000D6
+:023AEF000000D5
+:023AF0000000D4
+:023AF1000000D3
+:023AF2000000D2
+:023AF3000000D1
+:023AF4000000D0
+:023AF5000000CF
+:023AF6000000CE
+:023AF7000000CD
+:023AF8000000CC
+:023AF9000000CB
+:023AFA000000CA
+:023AFB000000C9
+:023AFC000000C8
+:023AFD000000C7
+:023AFE000000C6
+:023AFF000000C5
+:023B00000000C3
+:023B01000000C2
+:023B02000000C1
+:023B03000000C0
+:023B04000000BF
+:023B05000000BE
+:023B06000000BD
+:023B07000000BC
+:023B08000000BB
+:023B09000000BA
+:023B0A000000B9
+:023B0B000000B8
+:023B0C000000B7
+:023B0D000000B6
+:023B0E000000B5
+:023B0F000000B4
+:023B10000000B3
+:023B11000000B2
+:023B12000000B1
+:023B13000000B0
+:023B14000000AF
+:023B15000000AE
+:023B16000000AD
+:023B17000000AC
+:023B18000000AB
+:023B19000000AA
+:023B1A000000A9
+:023B1B000000A8
+:023B1C000000A7
+:023B1D000000A6
+:023B1E000000A5
+:023B1F000000A4
+:023B20000000A3
+:023B21000000A2
+:023B22000000A1
+:023B23000000A0
+:023B240000009F
+:023B250000009E
+:023B260000009D
+:023B270000009C
+:023B280000009B
+:023B290000009A
+:023B2A00000099
+:023B2B00000098
+:023B2C00000097
+:023B2D00000096
+:023B2E00000095
+:023B2F00000094
+:023B3000000093
+:023B3100000092
+:023B3200000091
+:023B3300000090
+:023B340000008F
+:023B350000008E
+:023B360000008D
+:023B370000008C
+:023B380000008B
+:023B390000008A
+:023B3A00000089
+:023B3B00000088
+:023B3C00000087
+:023B3D00000086
+:023B3E00000085
+:023B3F00000084
+:023B4000000083
+:023B4100000082
+:023B4200000081
+:023B4300000080
+:023B440000007F
+:023B450000007E
+:023B460000007D
+:023B470000007C
+:023B480000007B
+:023B490000007A
+:023B4A00000079
+:023B4B00000078
+:023B4C00000077
+:023B4D00000076
+:023B4E00000075
+:023B4F00000074
+:023B5000000073
+:023B5100000072
+:023B5200000071
+:023B5300000070
+:023B540000006F
+:023B550000006E
+:023B560000006D
+:023B570000006C
+:023B580000006B
+:023B590000006A
+:023B5A00000069
+:023B5B00000068
+:023B5C00000067
+:023B5D00000066
+:023B5E00000065
+:023B5F00000064
+:023B6000000063
+:023B6100000062
+:023B6200000061
+:023B6300000060
+:023B640000005F
+:023B650000005E
+:023B660000005D
+:023B670000005C
+:023B680000005B
+:023B690000005A
+:023B6A00000059
+:023B6B00000058
+:023B6C00000057
+:023B6D00000056
+:023B6E00000055
+:023B6F00000054
+:023B7000000053
+:023B7100000052
+:023B7200000051
+:023B7300000050
+:023B740000004F
+:023B750000004E
+:023B760000004D
+:023B770000004C
+:023B780000004B
+:023B790000004A
+:023B7A00000049
+:023B7B00000048
+:023B7C00000047
+:023B7D00000046
+:023B7E00000045
+:023B7F00000044
+:023B8000000043
+:023B8100000042
+:023B8200000041
+:023B8300000040
+:023B840000003F
+:023B850000003E
+:023B860000003D
+:023B870000003C
+:023B880000003B
+:023B890000003A
+:023B8A00000039
+:023B8B00000038
+:023B8C00000037
+:023B8D00000036
+:023B8E00000035
+:023B8F00000034
+:023B9000000033
+:023B9100000032
+:023B9200000031
+:023B9300000030
+:023B940000002F
+:023B950000002E
+:023B960000002D
+:023B970000002C
+:023B980000002B
+:023B990000002A
+:023B9A00000029
+:023B9B00000028
+:023B9C00000027
+:023B9D00000026
+:023B9E00000025
+:023B9F00000024
+:023BA000000023
+:023BA100000022
+:023BA200000021
+:023BA300000020
+:023BA40000001F
+:023BA50000001E
+:023BA60000001D
+:023BA70000001C
+:023BA80000001B
+:023BA90000001A
+:023BAA00000019
+:023BAB00000018
+:023BAC00000017
+:023BAD00000016
+:023BAE00000015
+:023BAF00000014
+:023BB000000013
+:023BB100000012
+:023BB200000011
+:023BB300000010
+:023BB40000000F
+:023BB50000000E
+:023BB60000000D
+:023BB70000000C
+:023BB80000000B
+:023BB90000000A
+:023BBA00000009
+:023BBB00000008
+:023BBC00000007
+:023BBD00000006
+:023BBE00000005
+:023BBF00000004
+:023BC000000003
+:023BC100000002
+:023BC200000001
+:023BC300000000
+:023BC4000000FF
+:023BC5000000FE
+:023BC6000000FD
+:023BC7000000FC
+:023BC8000000FB
+:023BC9000000FA
+:023BCA000000F9
+:023BCB000000F8
+:023BCC000000F7
+:023BCD000000F6
+:023BCE000000F5
+:023BCF000000F4
+:023BD0000000F3
+:023BD1000000F2
+:023BD2000000F1
+:023BD3000000F0
+:023BD4000000EF
+:023BD5000000EE
+:023BD6000000ED
+:023BD7000000EC
+:023BD8000000EB
+:023BD9000000EA
+:023BDA000000E9
+:023BDB000000E8
+:023BDC000000E7
+:023BDD000000E6
+:023BDE000000E5
+:023BDF000000E4
+:023BE0000000E3
+:023BE1000000E2
+:023BE2000000E1
+:023BE3000000E0
+:023BE4000000DF
+:023BE5000000DE
+:023BE6000000DD
+:023BE7000000DC
+:023BE8000000DB
+:023BE9000000DA
+:023BEA000000D9
+:023BEB000000D8
+:023BEC000000D7
+:023BED000000D6
+:023BEE000000D5
+:023BEF000000D4
+:023BF0000000D3
+:023BF1000000D2
+:023BF2000000D1
+:023BF3000000D0
+:023BF4000000CF
+:023BF5000000CE
+:023BF6000000CD
+:023BF7000000CC
+:023BF8000000CB
+:023BF9000000CA
+:023BFA000000C9
+:023BFB000000C8
+:023BFC000000C7
+:023BFD000000C6
+:023BFE000000C5
+:023BFF000000C4
+:023C00000000C2
+:023C01000000C1
+:023C02000000C0
+:023C03000000BF
+:023C04000000BE
+:023C05000000BD
+:023C06000000BC
+:023C07000000BB
+:023C08000000BA
+:023C09000000B9
+:023C0A000000B8
+:023C0B000000B7
+:023C0C000000B6
+:023C0D000000B5
+:023C0E000000B4
+:023C0F000000B3
+:023C10000000B2
+:023C11000000B1
+:023C12000000B0
+:023C13000000AF
+:023C14000000AE
+:023C15000000AD
+:023C16000000AC
+:023C17000000AB
+:023C18000000AA
+:023C19000000A9
+:023C1A000000A8
+:023C1B000000A7
+:023C1C000000A6
+:023C1D000000A5
+:023C1E000000A4
+:023C1F000000A3
+:023C20000000A2
+:023C21000000A1
+:023C22000000A0
+:023C230000009F
+:023C240000009E
+:023C250000009D
+:023C260000009C
+:023C270000009B
+:023C280000009A
+:023C2900000099
+:023C2A00000098
+:023C2B00000097
+:023C2C00000096
+:023C2D00000095
+:023C2E00000094
+:023C2F00000093
+:023C3000000092
+:023C3100000091
+:023C3200000090
+:023C330000008F
+:023C340000008E
+:023C350000008D
+:023C360000008C
+:023C370000008B
+:023C380000008A
+:023C3900000089
+:023C3A00000088
+:023C3B00000087
+:023C3C00000086
+:023C3D00000085
+:023C3E00000084
+:023C3F00000083
+:023C4000000082
+:023C4100000081
+:023C4200000080
+:023C430000007F
+:023C440000007E
+:023C450000007D
+:023C460000007C
+:023C470000007B
+:023C480000007A
+:023C4900000079
+:023C4A00000078
+:023C4B00000077
+:023C4C00000076
+:023C4D00000075
+:023C4E00000074
+:023C4F00000073
+:023C5000000072
+:023C5100000071
+:023C5200000070
+:023C530000006F
+:023C540000006E
+:023C550000006D
+:023C560000006C
+:023C570000006B
+:023C580000006A
+:023C5900000069
+:023C5A00000068
+:023C5B00000067
+:023C5C00000066
+:023C5D00000065
+:023C5E00000064
+:023C5F00000063
+:023C6000000062
+:023C6100000061
+:023C6200000060
+:023C630000005F
+:023C640000005E
+:023C650000005D
+:023C660000005C
+:023C670000005B
+:023C680000005A
+:023C6900000059
+:023C6A00000058
+:023C6B00000057
+:023C6C00000056
+:023C6D00000055
+:023C6E00000054
+:023C6F00000053
+:023C7000000052
+:023C7100000051
+:023C7200000050
+:023C730000004F
+:023C740000004E
+:023C750000004D
+:023C760000004C
+:023C770000004B
+:023C780000004A
+:023C7900000049
+:023C7A00000048
+:023C7B00000047
+:023C7C00000046
+:023C7D00000045
+:023C7E00000044
+:023C7F00000043
+:023C8000000042
+:023C8100000041
+:023C8200000040
+:023C830000003F
+:023C840000003E
+:023C850000003D
+:023C860000003C
+:023C870000003B
+:023C880000003A
+:023C8900000039
+:023C8A00000038
+:023C8B00000037
+:023C8C00000036
+:023C8D00000035
+:023C8E00000034
+:023C8F00000033
+:023C9000000032
+:023C9100000031
+:023C9200000030
+:023C930000002F
+:023C940000002E
+:023C950000002D
+:023C960000002C
+:023C970000002B
+:023C980000002A
+:023C9900000029
+:023C9A00000028
+:023C9B00000027
+:023C9C00000026
+:023C9D00000025
+:023C9E00000024
+:023C9F00000023
+:023CA000000022
+:023CA100000021
+:023CA200000020
+:023CA30000001F
+:023CA40000001E
+:023CA50000001D
+:023CA60000001C
+:023CA70000001B
+:023CA80000001A
+:023CA900000019
+:023CAA00000018
+:023CAB00000017
+:023CAC00000016
+:023CAD00000015
+:023CAE00000014
+:023CAF00000013
+:023CB000000012
+:023CB100000011
+:023CB200000010
+:023CB30000000F
+:023CB40000000E
+:023CB50000000D
+:023CB60000000C
+:023CB70000000B
+:023CB80000000A
+:023CB900000009
+:023CBA00000008
+:023CBB00000007
+:023CBC00000006
+:023CBD00000005
+:023CBE00000004
+:023CBF00000003
+:023CC000000002
+:023CC100000001
+:023CC200000000
+:023CC3000000FF
+:023CC4000000FE
+:023CC5000000FD
+:023CC6000000FC
+:023CC7000000FB
+:023CC8000000FA
+:023CC9000000F9
+:023CCA000000F8
+:023CCB000000F7
+:023CCC000000F6
+:023CCD000000F5
+:023CCE000000F4
+:023CCF000000F3
+:023CD0000000F2
+:023CD1000000F1
+:023CD2000000F0
+:023CD3000000EF
+:023CD4000000EE
+:023CD5000000ED
+:023CD6000000EC
+:023CD7000000EB
+:023CD8000000EA
+:023CD9000000E9
+:023CDA000000E8
+:023CDB000000E7
+:023CDC000000E6
+:023CDD000000E5
+:023CDE000000E4
+:023CDF000000E3
+:023CE0000000E2
+:023CE1000000E1
+:023CE2000000E0
+:023CE3000000DF
+:023CE4000000DE
+:023CE5000000DD
+:023CE6000000DC
+:023CE7000000DB
+:023CE8000000DA
+:023CE9000000D9
+:023CEA000000D8
+:023CEB000000D7
+:023CEC000000D6
+:023CED000000D5
+:023CEE000000D4
+:023CEF000000D3
+:023CF0000000D2
+:023CF1000000D1
+:023CF2000000D0
+:023CF3000000CF
+:023CF4000000CE
+:023CF5000000CD
+:023CF6000000CC
+:023CF7000000CB
+:023CF8000000CA
+:023CF9000000C9
+:023CFA000000C8
+:023CFB000000C7
+:023CFC000000C6
+:023CFD000000C5
+:023CFE000000C4
+:023CFF000000C3
+:023D00000000C1
+:023D01000000C0
+:023D02000000BF
+:023D03000000BE
+:023D04000000BD
+:023D05000000BC
+:023D06000000BB
+:023D07000000BA
+:023D08000000B9
+:023D09000000B8
+:023D0A000000B7
+:023D0B000000B6
+:023D0C000000B5
+:023D0D000000B4
+:023D0E000000B3
+:023D0F000000B2
+:023D10000000B1
+:023D11000000B0
+:023D12000000AF
+:023D13000000AE
+:023D14000000AD
+:023D15000000AC
+:023D16000000AB
+:023D17000000AA
+:023D18000000A9
+:023D19000000A8
+:023D1A000000A7
+:023D1B000000A6
+:023D1C000000A5
+:023D1D000000A4
+:023D1E000000A3
+:023D1F000000A2
+:023D20000000A1
+:023D21000000A0
+:023D220000009F
+:023D230000009E
+:023D240000009D
+:023D250000009C
+:023D260000009B
+:023D270000009A
+:023D2800000099
+:023D2900000098
+:023D2A00000097
+:023D2B00000096
+:023D2C00000095
+:023D2D00000094
+:023D2E00000093
+:023D2F00000092
+:023D3000000091
+:023D3100000090
+:023D320000008F
+:023D330000008E
+:023D340000008D
+:023D350000008C
+:023D360000008B
+:023D370000008A
+:023D3800000089
+:023D3900000088
+:023D3A00000087
+:023D3B00000086
+:023D3C00000085
+:023D3D00000084
+:023D3E00000083
+:023D3F00000082
+:023D4000000081
+:023D4100000080
+:023D420000007F
+:023D430000007E
+:023D440000007D
+:023D450000007C
+:023D460000007B
+:023D470000007A
+:023D4800000079
+:023D4900000078
+:023D4A00000077
+:023D4B00000076
+:023D4C00000075
+:023D4D00000074
+:023D4E00000073
+:023D4F00000072
+:023D5000000071
+:023D5100000070
+:023D520000006F
+:023D530000006E
+:023D540000006D
+:023D550000006C
+:023D560000006B
+:023D570000006A
+:023D5800000069
+:023D5900000068
+:023D5A00000067
+:023D5B00000066
+:023D5C00000065
+:023D5D00000064
+:023D5E00000063
+:023D5F00000062
+:023D6000000061
+:023D6100000060
+:023D620000005F
+:023D630000005E
+:023D640000005D
+:023D650000005C
+:023D660000005B
+:023D670000005A
+:023D6800000059
+:023D6900000058
+:023D6A00000057
+:023D6B00000056
+:023D6C00000055
+:023D6D00000054
+:023D6E00000053
+:023D6F00000052
+:023D7000000051
+:023D7100000050
+:023D720000004F
+:023D730000004E
+:023D740000004D
+:023D750000004C
+:023D760000004B
+:023D770000004A
+:023D7800000049
+:023D7900000048
+:023D7A00000047
+:023D7B00000046
+:023D7C00000045
+:023D7D00000044
+:023D7E00000043
+:023D7F00000042
+:023D8000000041
+:023D8100000040
+:023D820000003F
+:023D830000003E
+:023D840000003D
+:023D850000003C
+:023D860000003B
+:023D870000003A
+:023D8800000039
+:023D8900000038
+:023D8A00000037
+:023D8B00000036
+:023D8C00000035
+:023D8D00000034
+:023D8E00000033
+:023D8F00000032
+:023D9000000031
+:023D9100000030
+:023D920000002F
+:023D930000002E
+:023D940000002D
+:023D950000002C
+:023D960000002B
+:023D970000002A
+:023D9800000029
+:023D9900000028
+:023D9A00000027
+:023D9B00000026
+:023D9C00000025
+:023D9D00000024
+:023D9E00000023
+:023D9F00000022
+:023DA000000021
+:023DA100000020
+:023DA20000001F
+:023DA30000001E
+:023DA40000001D
+:023DA50000001C
+:023DA60000001B
+:023DA70000001A
+:023DA800000019
+:023DA900000018
+:023DAA00000017
+:023DAB00000016
+:023DAC00000015
+:023DAD00000014
+:023DAE00000013
+:023DAF00000012
+:023DB000000011
+:023DB100000010
+:023DB20000000F
+:023DB30000000E
+:023DB40000000D
+:023DB50000000C
+:023DB60000000B
+:023DB70000000A
+:023DB800000009
+:023DB900000008
+:023DBA00000007
+:023DBB00000006
+:023DBC00000005
+:023DBD00000004
+:023DBE00000003
+:023DBF00000002
+:023DC000000001
+:023DC100000000
+:023DC2000000FF
+:023DC3000000FE
+:023DC4000000FD
+:023DC5000000FC
+:023DC6000000FB
+:023DC7000000FA
+:023DC8000000F9
+:023DC9000000F8
+:023DCA000000F7
+:023DCB000000F6
+:023DCC000000F5
+:023DCD000000F4
+:023DCE000000F3
+:023DCF000000F2
+:023DD0000000F1
+:023DD1000000F0
+:023DD2000000EF
+:023DD3000000EE
+:023DD4000000ED
+:023DD5000000EC
+:023DD6000000EB
+:023DD7000000EA
+:023DD8000000E9
+:023DD9000000E8
+:023DDA000000E7
+:023DDB000000E6
+:023DDC000000E5
+:023DDD000000E4
+:023DDE000000E3
+:023DDF000000E2
+:023DE0000000E1
+:023DE1000000E0
+:023DE2000000DF
+:023DE3000000DE
+:023DE4000000DD
+:023DE5000000DC
+:023DE6000000DB
+:023DE7000000DA
+:023DE8000000D9
+:023DE9000000D8
+:023DEA000000D7
+:023DEB000000D6
+:023DEC000000D5
+:023DED000000D4
+:023DEE000000D3
+:023DEF000000D2
+:023DF0000000D1
+:023DF1000000D0
+:023DF2000000CF
+:023DF3000000CE
+:023DF4000000CD
+:023DF5000000CC
+:023DF6000000CB
+:023DF7000000CA
+:023DF8000000C9
+:023DF9000000C8
+:023DFA000000C7
+:023DFB000000C6
+:023DFC000000C5
+:023DFD000000C4
+:023DFE000000C3
+:023DFF000000C2
+:023E00000000C0
+:023E01000000BF
+:023E02000000BE
+:023E03000000BD
+:023E04000000BC
+:023E05000000BB
+:023E06000000BA
+:023E07000000B9
+:023E08000000B8
+:023E09000000B7
+:023E0A000000B6
+:023E0B000000B5
+:023E0C000000B4
+:023E0D000000B3
+:023E0E000000B2
+:023E0F000000B1
+:023E10000000B0
+:023E11000000AF
+:023E12000000AE
+:023E13000000AD
+:023E14000000AC
+:023E15000000AB
+:023E16000000AA
+:023E17000000A9
+:023E18000000A8
+:023E19000000A7
+:023E1A000000A6
+:023E1B000000A5
+:023E1C000000A4
+:023E1D000000A3
+:023E1E000000A2
+:023E1F000000A1
+:023E20000000A0
+:023E210000009F
+:023E220000009E
+:023E230000009D
+:023E240000009C
+:023E250000009B
+:023E260000009A
+:023E2700000099
+:023E2800000098
+:023E2900000097
+:023E2A00000096
+:023E2B00000095
+:023E2C00000094
+:023E2D00000093
+:023E2E00000092
+:023E2F00000091
+:023E3000000090
+:023E310000008F
+:023E320000008E
+:023E330000008D
+:023E340000008C
+:023E350000008B
+:023E360000008A
+:023E3700000089
+:023E3800000088
+:023E3900000087
+:023E3A00000086
+:023E3B00000085
+:023E3C00000084
+:023E3D00000083
+:023E3E00000082
+:023E3F00000081
+:023E4000000080
+:023E410000007F
+:023E420000007E
+:023E430000007D
+:023E440000007C
+:023E450000007B
+:023E460000007A
+:023E4700000079
+:023E4800000078
+:023E4900000077
+:023E4A00000076
+:023E4B00000075
+:023E4C00000074
+:023E4D00000073
+:023E4E00000072
+:023E4F00000071
+:023E5000000070
+:023E510000006F
+:023E520000006E
+:023E530000006D
+:023E540000006C
+:023E550000006B
+:023E560000006A
+:023E5700000069
+:023E5800000068
+:023E5900000067
+:023E5A00000066
+:023E5B00000065
+:023E5C00000064
+:023E5D00000063
+:023E5E00000062
+:023E5F00000061
+:023E6000000060
+:023E610000005F
+:023E620000005E
+:023E630000005D
+:023E640000005C
+:023E650000005B
+:023E660000005A
+:023E6700000059
+:023E6800000058
+:023E6900000057
+:023E6A00000056
+:023E6B00000055
+:023E6C00000054
+:023E6D00000053
+:023E6E00000052
+:023E6F00000051
+:023E7000000050
+:023E710000004F
+:023E720000004E
+:023E730000004D
+:023E740000004C
+:023E750000004B
+:023E760000004A
+:023E7700000049
+:023E7800000048
+:023E7900000047
+:023E7A00000046
+:023E7B00000045
+:023E7C00000044
+:023E7D00000043
+:023E7E00000042
+:023E7F00000041
+:023E8000000040
+:023E810000003F
+:023E820000003E
+:023E830000003D
+:023E840000003C
+:023E850000003B
+:023E860000003A
+:023E8700000039
+:023E8800000038
+:023E8900000037
+:023E8A00000036
+:023E8B00000035
+:023E8C00000034
+:023E8D00000033
+:023E8E00000032
+:023E8F00000031
+:023E9000000030
+:023E910000002F
+:023E920000002E
+:023E930000002D
+:023E940000002C
+:023E950000002B
+:023E960000002A
+:023E9700000029
+:023E9800000028
+:023E9900000027
+:023E9A00000026
+:023E9B00000025
+:023E9C00000024
+:023E9D00000023
+:023E9E00000022
+:023E9F00000021
+:023EA000000020
+:023EA10000001F
+:023EA20000001E
+:023EA30000001D
+:023EA40000001C
+:023EA50000001B
+:023EA60000001A
+:023EA700000019
+:023EA800000018
+:023EA900000017
+:023EAA00000016
+:023EAB00000015
+:023EAC00000014
+:023EAD00000013
+:023EAE00000012
+:023EAF00000011
+:023EB000000010
+:023EB10000000F
+:023EB20000000E
+:023EB30000000D
+:023EB40000000C
+:023EB50000000B
+:023EB60000000A
+:023EB700000009
+:023EB800000008
+:023EB900000007
+:023EBA00000006
+:023EBB00000005
+:023EBC00000004
+:023EBD00000003
+:023EBE00000002
+:023EBF00000001
+:023EC000000000
+:023EC1000000FF
+:023EC2000000FE
+:023EC3000000FD
+:023EC4000000FC
+:023EC5000000FB
+:023EC6000000FA
+:023EC7000000F9
+:023EC8000000F8
+:023EC9000000F7
+:023ECA000000F6
+:023ECB000000F5
+:023ECC000000F4
+:023ECD000000F3
+:023ECE000000F2
+:023ECF000000F1
+:023ED0000000F0
+:023ED1000000EF
+:023ED2000000EE
+:023ED3000000ED
+:023ED4000000EC
+:023ED5000000EB
+:023ED6000000EA
+:023ED7000000E9
+:023ED8000000E8
+:023ED9000000E7
+:023EDA000000E6
+:023EDB000000E5
+:023EDC000000E4
+:023EDD000000E3
+:023EDE000000E2
+:023EDF000000E1
+:023EE0000000E0
+:023EE1000000DF
+:023EE2000000DE
+:023EE3000000DD
+:023EE4000000DC
+:023EE5000000DB
+:023EE6000000DA
+:023EE7000000D9
+:023EE8000000D8
+:023EE9000000D7
+:023EEA000000D6
+:023EEB000000D5
+:023EEC000000D4
+:023EED000000D3
+:023EEE000000D2
+:023EEF000000D1
+:023EF0000000D0
+:023EF1000000CF
+:023EF2000000CE
+:023EF3000000CD
+:023EF4000000CC
+:023EF5000000CB
+:023EF6000000CA
+:023EF7000000C9
+:023EF8000000C8
+:023EF9000000C7
+:023EFA000000C6
+:023EFB000000C5
+:023EFC000000C4
+:023EFD000000C3
+:023EFE000000C2
+:023EFF000000C1
+:023F00000000BF
+:023F01000000BE
+:023F02000000BD
+:023F03000000BC
+:023F04000000BB
+:023F05000000BA
+:023F06000000B9
+:023F07000000B8
+:023F08000000B7
+:023F09000000B6
+:023F0A000000B5
+:023F0B000000B4
+:023F0C000000B3
+:023F0D000000B2
+:023F0E000000B1
+:023F0F000000B0
+:023F10000000AF
+:023F11000000AE
+:023F12000000AD
+:023F13000000AC
+:023F14000000AB
+:023F15000000AA
+:023F16000000A9
+:023F17000000A8
+:023F18000000A7
+:023F19000000A6
+:023F1A000000A5
+:023F1B000000A4
+:023F1C000000A3
+:023F1D000000A2
+:023F1E000000A1
+:023F1F000000A0
+:023F200000009F
+:023F210000009E
+:023F220000009D
+:023F230000009C
+:023F240000009B
+:023F250000009A
+:023F2600000099
+:023F2700000098
+:023F2800000097
+:023F2900000096
+:023F2A00000095
+:023F2B00000094
+:023F2C00000093
+:023F2D00000092
+:023F2E00000091
+:023F2F00000090
+:023F300000008F
+:023F310000008E
+:023F320000008D
+:023F330000008C
+:023F340000008B
+:023F350000008A
+:023F3600000089
+:023F3700000088
+:023F3800000087
+:023F3900000086
+:023F3A00000085
+:023F3B00000084
+:023F3C00000083
+:023F3D00000082
+:023F3E00000081
+:023F3F00000080
+:023F400000007F
+:023F410000007E
+:023F420000007D
+:023F430000007C
+:023F440000007B
+:023F450000007A
+:023F4600000079
+:023F4700000078
+:023F4800000077
+:023F4900000076
+:023F4A00000075
+:023F4B00000074
+:023F4C00000073
+:023F4D00000072
+:023F4E00000071
+:023F4F00000070
+:023F500000006F
+:023F510000006E
+:023F520000006D
+:023F530000006C
+:023F540000006B
+:023F550000006A
+:023F5600000069
+:023F5700000068
+:023F5800000067
+:023F5900000066
+:023F5A00000065
+:023F5B00000064
+:023F5C00000063
+:023F5D00000062
+:023F5E00000061
+:023F5F00000060
+:023F600000005F
+:023F610000005E
+:023F620000005D
+:023F630000005C
+:023F640000005B
+:023F650000005A
+:023F6600000059
+:023F6700000058
+:023F6800000057
+:023F6900000056
+:023F6A00000055
+:023F6B00000054
+:023F6C00000053
+:023F6D00000052
+:023F6E00000051
+:023F6F00000050
+:023F700000004F
+:023F710000004E
+:023F720000004D
+:023F730000004C
+:023F740000004B
+:023F750000004A
+:023F7600000049
+:023F7700000048
+:023F7800000047
+:023F7900000046
+:023F7A00000045
+:023F7B00000044
+:023F7C00000043
+:023F7D00000042
+:023F7E00000041
+:023F7F00000040
+:023F800000003F
+:023F810000003E
+:023F820000003D
+:023F830000003C
+:023F840000003B
+:023F850000003A
+:023F8600000039
+:023F8700000038
+:023F8800000037
+:023F8900000036
+:023F8A00000035
+:023F8B00000034
+:023F8C00000033
+:023F8D00000032
+:023F8E00000031
+:023F8F00000030
+:023F900000002F
+:023F910000002E
+:023F920000002D
+:023F930000002C
+:023F940000002B
+:023F950000002A
+:023F9600000029
+:023F9700000028
+:023F9800000027
+:023F9900000026
+:023F9A00000025
+:023F9B00000024
+:023F9C00000023
+:023F9D00000022
+:023F9E00000021
+:023F9F00000020
+:023FA00000001F
+:023FA10000001E
+:023FA20000001D
+:023FA30000001C
+:023FA40000001B
+:023FA50000001A
+:023FA600000019
+:023FA700000018
+:023FA800000017
+:023FA900000016
+:023FAA00000015
+:023FAB00000014
+:023FAC00000013
+:023FAD00000012
+:023FAE00000011
+:023FAF00000010
+:023FB00000000F
+:023FB10000000E
+:023FB20000000D
+:023FB30000000C
+:023FB40000000B
+:023FB50000000A
+:023FB600000009
+:023FB700000008
+:023FB800000007
+:023FB900000006
+:023FBA00000005
+:023FBB00000004
+:023FBC00000003
+:023FBD00000002
+:023FBE00000001
+:023FBF00000000
+:023FC0000000FF
+:023FC1000000FE
+:023FC2000000FD
+:023FC3000000FC
+:023FC4000000FB
+:023FC5000000FA
+:023FC6000000F9
+:023FC7000000F8
+:023FC8000000F7
+:023FC9000000F6
+:023FCA000000F5
+:023FCB000000F4
+:023FCC000000F3
+:023FCD000000F2
+:023FCE000000F1
+:023FCF000000F0
+:023FD0000000EF
+:023FD1000000EE
+:023FD2000000ED
+:023FD3000000EC
+:023FD4000000EB
+:023FD5000000EA
+:023FD6000000E9
+:023FD7000000E8
+:023FD8000000E7
+:023FD9000000E6
+:023FDA000000E5
+:023FDB000000E4
+:023FDC000000E3
+:023FDD000000E2
+:023FDE000000E1
+:023FDF000000E0
+:023FE0000000DF
+:023FE1000000DE
+:023FE2000000DD
+:023FE3000000DC
+:023FE4000000DB
+:023FE5000000DA
+:023FE6000000D9
+:023FE7000000D8
+:023FE8000000D7
+:023FE9000000D6
+:023FEA000000D5
+:023FEB000000D4
+:023FEC000000D3
+:023FED000000D2
+:023FEE000000D1
+:023FEF000000D0
+:023FF0000000CF
+:023FF1000000CE
+:023FF2000000CD
+:023FF3000000CC
+:023FF4000000CB
+:023FF5000000CA
+:023FF6000000C9
+:023FF7000000C8
+:023FF8000000C7
+:023FF9000000C6
+:023FFA000000C5
+:023FFB000000C4
+:023FFC000000C3
+:023FFD000000C2
+:023FFE000000C1
+:023FFF000000C0
+:024000000000BE
+:024001000000BD
+:024002000000BC
+:024003000000BB
+:024004000000BA
+:024005000000B9
+:024006000000B8
+:024007000000B7
+:024008000000B6
+:024009000000B5
+:02400A000000B4
+:02400B000000B3
+:02400C000000B2
+:02400D000000B1
+:02400E000000B0
+:02400F000000AF
+:024010000000AE
+:024011000000AD
+:024012000000AC
+:024013000000AB
+:024014000000AA
+:024015000000A9
+:024016000000A8
+:024017000000A7
+:024018000000A6
+:024019000000A5
+:02401A000000A4
+:02401B000000A3
+:02401C000000A2
+:02401D000000A1
+:02401E000000A0
+:02401F0000009F
+:0240200000009E
+:0240210000009D
+:0240220000009C
+:0240230000009B
+:0240240000009A
+:02402500000099
+:02402600000098
+:02402700000097
+:02402800000096
+:02402900000095
+:02402A00000094
+:02402B00000093
+:02402C00000092
+:02402D00000091
+:02402E00000090
+:02402F0000008F
+:0240300000008E
+:0240310000008D
+:0240320000008C
+:0240330000008B
+:0240340000008A
+:02403500000089
+:02403600000088
+:02403700000087
+:02403800000086
+:02403900000085
+:02403A00000084
+:02403B00000083
+:02403C00000082
+:02403D00000081
+:02403E00000080
+:02403F0000007F
+:0240400000007E
+:0240410000007D
+:0240420000007C
+:0240430000007B
+:0240440000007A
+:02404500000079
+:02404600000078
+:02404700000077
+:02404800000076
+:02404900000075
+:02404A00000074
+:02404B00000073
+:02404C00000072
+:02404D00000071
+:02404E00000070
+:02404F0000006F
+:0240500000006E
+:0240510000006D
+:0240520000006C
+:0240530000006B
+:0240540000006A
+:02405500000069
+:02405600000068
+:02405700000067
+:02405800000066
+:02405900000065
+:02405A00000064
+:02405B00000063
+:02405C00000062
+:02405D00000061
+:02405E00000060
+:02405F0000005F
+:0240600000005E
+:0240610000005D
+:0240620000005C
+:0240630000005B
+:0240640000005A
+:02406500000059
+:02406600000058
+:02406700000057
+:02406800000056
+:02406900000055
+:02406A00000054
+:02406B00000053
+:02406C00000052
+:02406D00000051
+:02406E00000050
+:02406F0000004F
+:0240700000004E
+:0240710000004D
+:0240720000004C
+:0240730000004B
+:0240740000004A
+:02407500000049
+:02407600000048
+:02407700000047
+:02407800000046
+:02407900000045
+:02407A00000044
+:02407B00000043
+:02407C00000042
+:02407D00000041
+:02407E00000040
+:02407F0000003F
+:0240800000003E
+:0240810000003D
+:0240820000003C
+:0240830000003B
+:0240840000003A
+:02408500000039
+:02408600000038
+:02408700000037
+:02408800000036
+:02408900000035
+:02408A00000034
+:02408B00000033
+:02408C00000032
+:02408D00000031
+:02408E00000030
+:02408F0000002F
+:0240900000002E
+:0240910000002D
+:0240920000002C
+:0240930000002B
+:0240940000002A
+:02409500000029
+:02409600000028
+:02409700000027
+:02409800000026
+:02409900000025
+:02409A00000024
+:02409B00000023
+:02409C00000022
+:02409D00000021
+:02409E00000020
+:02409F0000001F
+:0240A00000001E
+:0240A10000001D
+:0240A20000001C
+:0240A30000001B
+:0240A40000001A
+:0240A500000019
+:0240A600000018
+:0240A700000017
+:0240A800000016
+:0240A900000015
+:0240AA00000014
+:0240AB00000013
+:0240AC00000012
+:0240AD00000011
+:0240AE00000010
+:0240AF0000000F
+:0240B00000000E
+:0240B10000000D
+:0240B20000000C
+:0240B30000000B
+:0240B40000000A
+:0240B500000009
+:0240B600000008
+:0240B700000007
+:0240B800000006
+:0240B900000005
+:0240BA00000004
+:0240BB00000003
+:0240BC00000002
+:0240BD00000001
+:0240BE00000000
+:0240BF000000FF
+:0240C0000000FE
+:0240C1000000FD
+:0240C2000000FC
+:0240C3000000FB
+:0240C4000000FA
+:0240C5000000F9
+:0240C6000000F8
+:0240C7000000F7
+:0240C8000000F6
+:0240C9000000F5
+:0240CA000000F4
+:0240CB000000F3
+:0240CC000000F2
+:0240CD000000F1
+:0240CE000000F0
+:0240CF000000EF
+:0240D0000000EE
+:0240D1000000ED
+:0240D2000000EC
+:0240D3000000EB
+:0240D4000000EA
+:0240D5000000E9
+:0240D6000000E8
+:0240D7000000E7
+:0240D8000000E6
+:0240D9000000E5
+:0240DA000000E4
+:0240DB000000E3
+:0240DC000000E2
+:0240DD000000E1
+:0240DE000000E0
+:0240DF000000DF
+:0240E0000000DE
+:0240E1000000DD
+:0240E2000000DC
+:0240E3000000DB
+:0240E4000000DA
+:0240E5000000D9
+:0240E6000000D8
+:0240E7000000D7
+:0240E8000000D6
+:0240E9000000D5
+:0240EA000000D4
+:0240EB000000D3
+:0240EC000000D2
+:0240ED000000D1
+:0240EE000000D0
+:0240EF000000CF
+:0240F0000000CE
+:0240F1000000CD
+:0240F2000000CC
+:0240F3000000CB
+:0240F4000000CA
+:0240F5000000C9
+:0240F6000000C8
+:0240F7000000C7
+:0240F8000000C6
+:0240F9000000C5
+:0240FA000000C4
+:0240FB000000C3
+:0240FC000000C2
+:0240FD000000C1
+:0240FE000000C0
+:0240FF000000BF
+:024100000000BD
+:024101000000BC
+:024102000000BB
+:024103000000BA
+:024104000000B9
+:024105000000B8
+:024106000000B7
+:024107000000B6
+:024108000000B5
+:024109000000B4
+:02410A000000B3
+:02410B000000B2
+:02410C000000B1
+:02410D000000B0
+:02410E000000AF
+:02410F000000AE
+:024110000000AD
+:024111000000AC
+:024112000000AB
+:024113000000AA
+:024114000000A9
+:024115000000A8
+:024116000000A7
+:024117000000A6
+:024118000000A5
+:024119000000A4
+:02411A000000A3
+:02411B000000A2
+:02411C000000A1
+:02411D000000A0
+:02411E0000009F
+:02411F0000009E
+:0241200000009D
+:0241210000009C
+:0241220000009B
+:0241230000009A
+:02412400000099
+:02412500000098
+:02412600000097
+:02412700000096
+:02412800000095
+:02412900000094
+:02412A00000093
+:02412B00000092
+:02412C00000091
+:02412D00000090
+:02412E0000008F
+:02412F0000008E
+:0241300000008D
+:0241310000008C
+:0241320000008B
+:0241330000008A
+:02413400000089
+:02413500000088
+:02413600000087
+:02413700000086
+:02413800000085
+:02413900000084
+:02413A00000083
+:02413B00000082
+:02413C00000081
+:02413D00000080
+:02413E0000007F
+:02413F0000007E
+:0241400000007D
+:0241410000007C
+:0241420000007B
+:0241430000007A
+:02414400000079
+:02414500000078
+:02414600000077
+:02414700000076
+:02414800000075
+:02414900000074
+:02414A00000073
+:02414B00000072
+:02414C00000071
+:02414D00000070
+:02414E0000006F
+:02414F0000006E
+:0241500000006D
+:0241510000006C
+:0241520000006B
+:0241530000006A
+:02415400000069
+:02415500000068
+:02415600000067
+:02415700000066
+:02415800000065
+:02415900000064
+:02415A00000063
+:02415B00000062
+:02415C00000061
+:02415D00000060
+:02415E0000005F
+:02415F0000005E
+:0241600000005D
+:0241610000005C
+:0241620000005B
+:0241630000005A
+:02416400000059
+:02416500000058
+:02416600000057
+:02416700000056
+:02416800000055
+:02416900000054
+:02416A00000053
+:02416B00000052
+:02416C00000051
+:02416D00000050
+:02416E0000004F
+:02416F0000004E
+:0241700000004D
+:0241710000004C
+:0241720000004B
+:0241730000004A
+:02417400000049
+:02417500000048
+:02417600000047
+:02417700000046
+:02417800000045
+:02417900000044
+:02417A00000043
+:02417B00000042
+:02417C00000041
+:02417D00000040
+:02417E0000003F
+:02417F0000003E
+:0241800000003D
+:0241810000003C
+:0241820000003B
+:0241830000003A
+:02418400000039
+:02418500000038
+:02418600000037
+:02418700000036
+:02418800000035
+:02418900000034
+:02418A00000033
+:02418B00000032
+:02418C00000031
+:02418D00000030
+:02418E0000002F
+:02418F0000002E
+:0241900000002D
+:0241910000002C
+:0241920000002B
+:0241930000002A
+:02419400000029
+:02419500000028
+:02419600000027
+:02419700000026
+:02419800000025
+:02419900000024
+:02419A00000023
+:02419B00000022
+:02419C00000021
+:02419D00000020
+:02419E0000001F
+:02419F0000001E
+:0241A00000001D
+:0241A10000001C
+:0241A20000001B
+:0241A30000001A
+:0241A400000019
+:0241A500000018
+:0241A600000017
+:0241A700000016
+:0241A800000015
+:0241A900000014
+:0241AA00000013
+:0241AB00000012
+:0241AC00000011
+:0241AD00000010
+:0241AE0000000F
+:0241AF0000000E
+:0241B00000000D
+:0241B10000000C
+:0241B20000000B
+:0241B30000000A
+:0241B400000009
+:0241B500000008
+:0241B600000007
+:0241B700000006
+:0241B800000005
+:0241B900000004
+:0241BA00000003
+:0241BB00000002
+:0241BC00000001
+:0241BD00000000
+:0241BE000000FF
+:0241BF000000FE
+:0241C0000000FD
+:0241C1000000FC
+:0241C2000000FB
+:0241C3000000FA
+:0241C4000000F9
+:0241C5000000F8
+:0241C6000000F7
+:0241C7000000F6
+:0241C8000000F5
+:0241C9000000F4
+:0241CA000000F3
+:0241CB000000F2
+:0241CC000000F1
+:0241CD000000F0
+:0241CE000000EF
+:0241CF000000EE
+:0241D0000000ED
+:0241D1000000EC
+:0241D2000000EB
+:0241D3000000EA
+:0241D4000000E9
+:0241D5000000E8
+:0241D6000000E7
+:0241D7000000E6
+:0241D8000000E5
+:0241D9000000E4
+:0241DA000000E3
+:0241DB000000E2
+:0241DC000000E1
+:0241DD000000E0
+:0241DE000000DF
+:0241DF000000DE
+:0241E0000000DD
+:0241E1000000DC
+:0241E2000000DB
+:0241E3000000DA
+:0241E4000000D9
+:0241E5000000D8
+:0241E6000000D7
+:0241E7000000D6
+:0241E8000000D5
+:0241E9000000D4
+:0241EA000000D3
+:0241EB000000D2
+:0241EC000000D1
+:0241ED000000D0
+:0241EE000000CF
+:0241EF000000CE
+:0241F0000000CD
+:0241F1000000CC
+:0241F2000000CB
+:0241F3000000CA
+:0241F4000000C9
+:0241F5000000C8
+:0241F6000000C7
+:0241F7000000C6
+:0241F8000000C5
+:0241F9000000C4
+:0241FA000000C3
+:0241FB000000C2
+:0241FC000000C1
+:0241FD000000C0
+:0241FE000000BF
+:0241FF000000BE
+:024200000000BC
+:024201000000BB
+:024202000000BA
+:024203000000B9
+:024204000000B8
+:024205000000B7
+:024206000000B6
+:024207000000B5
+:024208000000B4
+:024209000000B3
+:02420A000000B2
+:02420B000000B1
+:02420C000000B0
+:02420D000000AF
+:02420E000000AE
+:02420F000000AD
+:024210000000AC
+:024211000000AB
+:024212000000AA
+:024213000000A9
+:024214000000A8
+:024215000000A7
+:024216000000A6
+:024217000000A5
+:024218000000A4
+:024219000000A3
+:02421A000000A2
+:02421B000000A1
+:02421C000000A0
+:02421D0000009F
+:02421E0000009E
+:02421F0000009D
+:0242200000009C
+:0242210000009B
+:0242220000009A
+:02422300000099
+:02422400000098
+:02422500000097
+:02422600000096
+:02422700000095
+:02422800000094
+:02422900000093
+:02422A00000092
+:02422B00000091
+:02422C00000090
+:02422D0000008F
+:02422E0000008E
+:02422F0000008D
+:0242300000008C
+:0242310000008B
+:0242320000008A
+:02423300000089
+:02423400000088
+:02423500000087
+:02423600000086
+:02423700000085
+:02423800000084
+:02423900000083
+:02423A00000082
+:02423B00000081
+:02423C00000080
+:02423D0000007F
+:02423E0000007E
+:02423F0000007D
+:0242400000007C
+:0242410000007B
+:0242420000007A
+:02424300000079
+:02424400000078
+:02424500000077
+:02424600000076
+:02424700000075
+:02424800000074
+:02424900000073
+:02424A00000072
+:02424B00000071
+:02424C00000070
+:02424D0000006F
+:02424E0000006E
+:02424F0000006D
+:0242500000006C
+:0242510000006B
+:0242520000006A
+:02425300000069
+:02425400000068
+:02425500000067
+:02425600000066
+:02425700000065
+:02425800000064
+:02425900000063
+:02425A00000062
+:02425B00000061
+:02425C00000060
+:02425D0000005F
+:02425E0000005E
+:02425F0000005D
+:0242600000005C
+:0242610000005B
+:0242620000005A
+:02426300000059
+:02426400000058
+:02426500000057
+:02426600000056
+:02426700000055
+:02426800000054
+:02426900000053
+:02426A00000052
+:02426B00000051
+:02426C00000050
+:02426D0000004F
+:02426E0000004E
+:02426F0000004D
+:0242700000004C
+:0242710000004B
+:0242720000004A
+:02427300000049
+:02427400000048
+:02427500000047
+:02427600000046
+:02427700000045
+:02427800000044
+:02427900000043
+:02427A00000042
+:02427B00000041
+:02427C00000040
+:02427D0000003F
+:02427E0000003E
+:02427F0000003D
+:0242800000003C
+:0242810000003B
+:0242820000003A
+:02428300000039
+:02428400000038
+:02428500000037
+:02428600000036
+:02428700000035
+:02428800000034
+:02428900000033
+:02428A00000032
+:02428B00000031
+:02428C00000030
+:02428D0000002F
+:02428E0000002E
+:02428F0000002D
+:0242900000002C
+:0242910000002B
+:0242920000002A
+:02429300000029
+:02429400000028
+:02429500000027
+:02429600000026
+:02429700000025
+:02429800000024
+:02429900000023
+:02429A00000022
+:02429B00000021
+:02429C00000020
+:02429D0000001F
+:02429E0000001E
+:02429F0000001D
+:0242A00000001C
+:0242A10000001B
+:0242A20000001A
+:0242A300000019
+:0242A400000018
+:0242A500000017
+:0242A600000016
+:0242A700000015
+:0242A800000014
+:0242A900000013
+:0242AA00000012
+:0242AB00000011
+:0242AC00000010
+:0242AD0000000F
+:0242AE0000000E
+:0242AF0000000D
+:0242B00000000C
+:0242B10000000B
+:0242B20000000A
+:0242B300000009
+:0242B400000008
+:0242B500000007
+:0242B600000006
+:0242B700000005
+:0242B800000004
+:0242B900000003
+:0242BA00000002
+:0242BB00000001
+:0242BC00000000
+:0242BD000000FF
+:0242BE000000FE
+:0242BF000000FD
+:0242C0000000FC
+:0242C1000000FB
+:0242C2000000FA
+:0242C3000000F9
+:0242C4000000F8
+:0242C5000000F7
+:0242C6000000F6
+:0242C7000000F5
+:0242C8000000F4
+:0242C9000000F3
+:0242CA000000F2
+:0242CB000000F1
+:0242CC000000F0
+:0242CD000000EF
+:0242CE000000EE
+:0242CF000000ED
+:0242D0000000EC
+:0242D1000000EB
+:0242D2000000EA
+:0242D3000000E9
+:0242D4000000E8
+:0242D5000000E7
+:0242D6000000E6
+:0242D7000000E5
+:0242D8000000E4
+:0242D9000000E3
+:0242DA000000E2
+:0242DB000000E1
+:0242DC000000E0
+:0242DD000000DF
+:0242DE000000DE
+:0242DF000000DD
+:0242E0000000DC
+:0242E1000000DB
+:0242E2000000DA
+:0242E3000000D9
+:0242E4000000D8
+:0242E5000000D7
+:0242E6000000D6
+:0242E7000000D5
+:0242E8000000D4
+:0242E9000000D3
+:0242EA000000D2
+:0242EB000000D1
+:0242EC000000D0
+:0242ED000000CF
+:0242EE000000CE
+:0242EF000000CD
+:0242F0000000CC
+:0242F1000000CB
+:0242F2000000CA
+:0242F3000000C9
+:0242F4000000C8
+:0242F5000000C7
+:0242F6000000C6
+:0242F7000000C5
+:0242F8000000C4
+:0242F9000000C3
+:0242FA000000C2
+:0242FB000000C1
+:0242FC000000C0
+:0242FD000000BF
+:0242FE000000BE
+:0242FF000000BD
+:024300000000BB
+:024301000000BA
+:024302000000B9
+:024303000000B8
+:024304000000B7
+:024305000000B6
+:024306000000B5
+:024307000000B4
+:024308000000B3
+:024309000000B2
+:02430A000000B1
+:02430B000000B0
+:02430C000000AF
+:02430D000000AE
+:02430E000000AD
+:02430F000000AC
+:024310000000AB
+:024311000000AA
+:024312000000A9
+:024313000000A8
+:024314000000A7
+:024315000000A6
+:024316000000A5
+:024317000000A4
+:024318000000A3
+:024319000000A2
+:02431A000000A1
+:02431B000000A0
+:02431C0000009F
+:02431D0000009E
+:02431E0000009D
+:02431F0000009C
+:0243200000009B
+:0243210000009A
+:02432200000099
+:02432300000098
+:02432400000097
+:02432500000096
+:02432600000095
+:02432700000094
+:02432800000093
+:02432900000092
+:02432A00000091
+:02432B00000090
+:02432C0000008F
+:02432D0000008E
+:02432E0000008D
+:02432F0000008C
+:0243300000008B
+:0243310000008A
+:02433200000089
+:02433300000088
+:02433400000087
+:02433500000086
+:02433600000085
+:02433700000084
+:02433800000083
+:02433900000082
+:02433A00000081
+:02433B00000080
+:02433C0000007F
+:02433D0000007E
+:02433E0000007D
+:02433F0000007C
+:0243400000007B
+:0243410000007A
+:02434200000079
+:02434300000078
+:02434400000077
+:02434500000076
+:02434600000075
+:02434700000074
+:02434800000073
+:02434900000072
+:02434A00000071
+:02434B00000070
+:02434C0000006F
+:02434D0000006E
+:02434E0000006D
+:02434F0000006C
+:0243500000006B
+:0243510000006A
+:02435200000069
+:02435300000068
+:02435400000067
+:02435500000066
+:02435600000065
+:02435700000064
+:02435800000063
+:02435900000062
+:02435A00000061
+:02435B00000060
+:02435C0000005F
+:02435D0000005E
+:02435E0000005D
+:02435F0000005C
+:0243600000005B
+:0243610000005A
+:02436200000059
+:02436300000058
+:02436400000057
+:02436500000056
+:02436600000055
+:02436700000054
+:02436800000053
+:02436900000052
+:02436A00000051
+:02436B00000050
+:02436C0000004F
+:02436D0000004E
+:02436E0000004D
+:02436F0000004C
+:0243700000004B
+:0243710000004A
+:02437200000049
+:02437300000048
+:02437400000047
+:02437500000046
+:02437600000045
+:02437700000044
+:02437800000043
+:02437900000042
+:02437A00000041
+:02437B00000040
+:02437C0000003F
+:02437D0000003E
+:02437E0000003D
+:02437F0000003C
+:0243800000003B
+:0243810000003A
+:02438200000039
+:02438300000038
+:02438400000037
+:02438500000036
+:02438600000035
+:02438700000034
+:02438800000033
+:02438900000032
+:02438A00000031
+:02438B00000030
+:02438C0000002F
+:02438D0000002E
+:02438E0000002D
+:02438F0000002C
+:0243900000002B
+:0243910000002A
+:02439200000029
+:02439300000028
+:02439400000027
+:02439500000026
+:02439600000025
+:02439700000024
+:02439800000023
+:02439900000022
+:02439A00000021
+:02439B00000020
+:02439C0000001F
+:02439D0000001E
+:02439E0000001D
+:02439F0000001C
+:0243A00000001B
+:0243A10000001A
+:0243A200000019
+:0243A300000018
+:0243A400000017
+:0243A500000016
+:0243A600000015
+:0243A700000014
+:0243A800000013
+:0243A900000012
+:0243AA00000011
+:0243AB00000010
+:0243AC0000000F
+:0243AD0000000E
+:0243AE0000000D
+:0243AF0000000C
+:0243B00000000B
+:0243B10000000A
+:0243B200000009
+:0243B300000008
+:0243B400000007
+:0243B500000006
+:0243B600000005
+:0243B700000004
+:0243B800000003
+:0243B900000002
+:0243BA00000001
+:0243BB00000000
+:0243BC000000FF
+:0243BD000000FE
+:0243BE000000FD
+:0243BF000000FC
+:0243C0000000FB
+:0243C1000000FA
+:0243C2000000F9
+:0243C3000000F8
+:0243C4000000F7
+:0243C5000000F6
+:0243C6000000F5
+:0243C7000000F4
+:0243C8000000F3
+:0243C9000000F2
+:0243CA000000F1
+:0243CB000000F0
+:0243CC000000EF
+:0243CD000000EE
+:0243CE000000ED
+:0243CF000000EC
+:0243D0000000EB
+:0243D1000000EA
+:0243D2000000E9
+:0243D3000000E8
+:0243D4000000E7
+:0243D5000000E6
+:0243D6000000E5
+:0243D7000000E4
+:0243D8000000E3
+:0243D9000000E2
+:0243DA000000E1
+:0243DB000000E0
+:0243DC000000DF
+:0243DD000000DE
+:0243DE000000DD
+:0243DF000000DC
+:0243E0000000DB
+:0243E1000000DA
+:0243E2000000D9
+:0243E3000000D8
+:0243E4000000D7
+:0243E5000000D6
+:0243E6000000D5
+:0243E7000000D4
+:0243E8000000D3
+:0243E9000000D2
+:0243EA000000D1
+:0243EB000000D0
+:0243EC000000CF
+:0243ED000000CE
+:0243EE000000CD
+:0243EF000000CC
+:0243F0000000CB
+:0243F1000000CA
+:0243F2000000C9
+:0243F3000000C8
+:0243F4000000C7
+:0243F5000000C6
+:0243F6000000C5
+:0243F7000000C4
+:0243F8000000C3
+:0243F9000000C2
+:0243FA000000C1
+:0243FB000000C0
+:0243FC000000BF
+:0243FD000000BE
+:0243FE000000BD
+:0243FF000000BC
+:024400000000BA
+:024401000000B9
+:024402000000B8
+:024403000000B7
+:024404000000B6
+:024405000000B5
+:024406000000B4
+:024407000000B3
+:024408000000B2
+:024409000000B1
+:02440A000000B0
+:02440B000000AF
+:02440C000000AE
+:02440D000000AD
+:02440E000000AC
+:02440F000000AB
+:024410000000AA
+:024411000000A9
+:024412000000A8
+:024413000000A7
+:024414000000A6
+:024415000000A5
+:024416000000A4
+:024417000000A3
+:024418000000A2
+:024419000000A1
+:02441A000000A0
+:02441B0000009F
+:02441C0000009E
+:02441D0000009D
+:02441E0000009C
+:02441F0000009B
+:0244200000009A
+:02442100000099
+:02442200000098
+:02442300000097
+:02442400000096
+:02442500000095
+:02442600000094
+:02442700000093
+:02442800000092
+:02442900000091
+:02442A00000090
+:02442B0000008F
+:02442C0000008E
+:02442D0000008D
+:02442E0000008C
+:02442F0000008B
+:0244300000008A
+:02443100000089
+:02443200000088
+:02443300000087
+:02443400000086
+:02443500000085
+:02443600000084
+:02443700000083
+:02443800000082
+:02443900000081
+:02443A00000080
+:02443B0000007F
+:02443C0000007E
+:02443D0000007D
+:02443E0000007C
+:02443F0000007B
+:0244400000007A
+:02444100000079
+:02444200000078
+:02444300000077
+:02444400000076
+:02444500000075
+:02444600000074
+:02444700000073
+:02444800000072
+:02444900000071
+:02444A00000070
+:02444B0000006F
+:02444C0000006E
+:02444D0000006D
+:02444E0000006C
+:02444F0000006B
+:0244500000006A
+:02445100000069
+:02445200000068
+:02445300000067
+:02445400000066
+:02445500000065
+:02445600000064
+:02445700000063
+:02445800000062
+:02445900000061
+:02445A00000060
+:02445B0000005F
+:02445C0000005E
+:02445D0000005D
+:02445E0000005C
+:02445F0000005B
+:0244600000005A
+:02446100000059
+:02446200000058
+:02446300000057
+:02446400000056
+:02446500000055
+:02446600000054
+:02446700000053
+:02446800000052
+:02446900000051
+:02446A00000050
+:02446B0000004F
+:02446C0000004E
+:02446D0000004D
+:02446E0000004C
+:02446F0000004B
+:0244700000004A
+:02447100000049
+:02447200000048
+:02447300000047
+:02447400000046
+:02447500000045
+:02447600000044
+:02447700000043
+:02447800000042
+:02447900000041
+:02447A00000040
+:02447B0000003F
+:02447C0000003E
+:02447D0000003D
+:02447E0000003C
+:02447F0000003B
+:0244800000003A
+:02448100000039
+:02448200000038
+:02448300000037
+:02448400000036
+:02448500000035
+:02448600000034
+:02448700000033
+:02448800000032
+:02448900000031
+:02448A00000030
+:02448B0000002F
+:02448C0000002E
+:02448D0000002D
+:02448E0000002C
+:02448F0000002B
+:0244900000002A
+:02449100000029
+:02449200000028
+:02449300000027
+:02449400000026
+:02449500000025
+:02449600000024
+:02449700000023
+:02449800000022
+:02449900000021
+:02449A00000020
+:02449B0000001F
+:02449C0000001E
+:02449D0000001D
+:02449E0000001C
+:02449F0000001B
+:0244A00000001A
+:0244A100000019
+:0244A200000018
+:0244A300000017
+:0244A400000016
+:0244A500000015
+:0244A600000014
+:0244A700000013
+:0244A800000012
+:0244A900000011
+:0244AA00000010
+:0244AB0000000F
+:0244AC0000000E
+:0244AD0000000D
+:0244AE0000000C
+:0244AF0000000B
+:0244B00000000A
+:0244B100000009
+:0244B200000008
+:0244B300000007
+:0244B400000006
+:0244B500000005
+:0244B600000004
+:0244B700000003
+:0244B800000002
+:0244B900000001
+:0244BA00000000
+:0244BB000000FF
+:0244BC000000FE
+:0244BD000000FD
+:0244BE000000FC
+:0244BF000000FB
+:0244C0000000FA
+:0244C1000000F9
+:0244C2000000F8
+:0244C3000000F7
+:0244C4000000F6
+:0244C5000000F5
+:0244C6000000F4
+:0244C7000000F3
+:0244C8000000F2
+:0244C9000000F1
+:0244CA000000F0
+:0244CB000000EF
+:0244CC000000EE
+:0244CD000000ED
+:0244CE000000EC
+:0244CF000000EB
+:0244D0000000EA
+:0244D1000000E9
+:0244D2000000E8
+:0244D3000000E7
+:0244D4000000E6
+:0244D5000000E5
+:0244D6000000E4
+:0244D7000000E3
+:0244D8000000E2
+:0244D9000000E1
+:0244DA000000E0
+:0244DB000000DF
+:0244DC000000DE
+:0244DD000000DD
+:0244DE000000DC
+:0244DF000000DB
+:0244E0000000DA
+:0244E1000000D9
+:0244E2000000D8
+:0244E3000000D7
+:0244E4000000D6
+:0244E5000000D5
+:0244E6000000D4
+:0244E7000000D3
+:0244E8000000D2
+:0244E9000000D1
+:0244EA000000D0
+:0244EB000000CF
+:0244EC000000CE
+:0244ED000000CD
+:0244EE000000CC
+:0244EF000000CB
+:0244F0000000CA
+:0244F1000000C9
+:0244F2000000C8
+:0244F3000000C7
+:0244F4000000C6
+:0244F5000000C5
+:0244F6000000C4
+:0244F7000000C3
+:0244F8000000C2
+:0244F9000000C1
+:0244FA000000C0
+:0244FB000000BF
+:0244FC000000BE
+:0244FD000000BD
+:0244FE000000BC
+:0244FF000000BB
+:024500000000B9
+:024501000000B8
+:024502000000B7
+:024503000000B6
+:024504000000B5
+:024505000000B4
+:024506000000B3
+:024507000000B2
+:024508000000B1
+:024509000000B0
+:02450A000000AF
+:02450B000000AE
+:02450C000000AD
+:02450D000000AC
+:02450E000000AB
+:02450F000000AA
+:024510000000A9
+:024511000000A8
+:024512000000A7
+:024513000000A6
+:024514000000A5
+:024515000000A4
+:024516000000A3
+:024517000000A2
+:024518000000A1
+:024519000000A0
+:02451A0000009F
+:02451B0000009E
+:02451C0000009D
+:02451D0000009C
+:02451E0000009B
+:02451F0000009A
+:02452000000099
+:02452100000098
+:02452200000097
+:02452300000096
+:02452400000095
+:02452500000094
+:02452600000093
+:02452700000092
+:02452800000091
+:02452900000090
+:02452A0000008F
+:02452B0000008E
+:02452C0000008D
+:02452D0000008C
+:02452E0000008B
+:02452F0000008A
+:02453000000089
+:02453100000088
+:02453200000087
+:02453300000086
+:02453400000085
+:02453500000084
+:02453600000083
+:02453700000082
+:02453800000081
+:02453900000080
+:02453A0000007F
+:02453B0000007E
+:02453C0000007D
+:02453D0000007C
+:02453E0000007B
+:02453F0000007A
+:02454000000079
+:02454100000078
+:02454200000077
+:02454300000076
+:02454400000075
+:02454500000074
+:02454600000073
+:02454700000072
+:02454800000071
+:02454900000070
+:02454A0000006F
+:02454B0000006E
+:02454C0000006D
+:02454D0000006C
+:02454E0000006B
+:02454F0000006A
+:02455000000069
+:02455100000068
+:02455200000067
+:02455300000066
+:02455400000065
+:02455500000064
+:02455600000063
+:02455700000062
+:02455800000061
+:02455900000060
+:02455A0000005F
+:02455B0000005E
+:02455C0000005D
+:02455D0000005C
+:02455E0000005B
+:02455F0000005A
+:02456000000059
+:02456100000058
+:02456200000057
+:02456300000056
+:02456400000055
+:02456500000054
+:02456600000053
+:02456700000052
+:02456800000051
+:02456900000050
+:02456A0000004F
+:02456B0000004E
+:02456C0000004D
+:02456D0000004C
+:02456E0000004B
+:02456F0000004A
+:02457000000049
+:02457100000048
+:02457200000047
+:02457300000046
+:02457400000045
+:02457500000044
+:02457600000043
+:02457700000042
+:02457800000041
+:02457900000040
+:02457A0000003F
+:02457B0000003E
+:02457C0000003D
+:02457D0000003C
+:02457E0000003B
+:02457F0000003A
+:02458000000039
+:02458100000038
+:02458200000037
+:02458300000036
+:02458400000035
+:02458500000034
+:02458600000033
+:02458700000032
+:02458800000031
+:02458900000030
+:02458A0000002F
+:02458B0000002E
+:02458C0000002D
+:02458D0000002C
+:02458E0000002B
+:02458F0000002A
+:02459000000029
+:02459100000028
+:02459200000027
+:02459300000026
+:02459400000025
+:02459500000024
+:02459600000023
+:02459700000022
+:02459800000021
+:02459900000020
+:02459A0000001F
+:02459B0000001E
+:02459C0000001D
+:02459D0000001C
+:02459E0000001B
+:02459F0000001A
+:0245A000000019
+:0245A100000018
+:0245A200000017
+:0245A300000016
+:0245A400000015
+:0245A500000014
+:0245A600000013
+:0245A700000012
+:0245A800000011
+:0245A900000010
+:0245AA0000000F
+:0245AB0000000E
+:0245AC0000000D
+:0245AD0000000C
+:0245AE0000000B
+:0245AF0000000A
+:0245B000000009
+:0245B100000008
+:0245B200000007
+:0245B300000006
+:0245B400000005
+:0245B500000004
+:0245B600000003
+:0245B700000002
+:0245B800000001
+:0245B900000000
+:0245BA000000FF
+:0245BB000000FE
+:0245BC000000FD
+:0245BD000000FC
+:0245BE000000FB
+:0245BF000000FA
+:0245C0000000F9
+:0245C1000000F8
+:0245C2000000F7
+:0245C3000000F6
+:0245C4000000F5
+:0245C5000000F4
+:0245C6000000F3
+:0245C7000000F2
+:0245C8000000F1
+:0245C9000000F0
+:0245CA000000EF
+:0245CB000000EE
+:0245CC000000ED
+:0245CD000000EC
+:0245CE000000EB
+:0245CF000000EA
+:0245D0000000E9
+:0245D1000000E8
+:0245D2000000E7
+:0245D3000000E6
+:0245D4000000E5
+:0245D5000000E4
+:0245D6000000E3
+:0245D7000000E2
+:0245D8000000E1
+:0245D9000000E0
+:0245DA000000DF
+:0245DB000000DE
+:0245DC000000DD
+:0245DD000000DC
+:0245DE000000DB
+:0245DF000000DA
+:0245E0000000D9
+:0245E1000000D8
+:0245E2000000D7
+:0245E3000000D6
+:0245E4000000D5
+:0245E5000000D4
+:0245E6000000D3
+:0245E7000000D2
+:0245E8000000D1
+:0245E9000000D0
+:0245EA000000CF
+:0245EB000000CE
+:0245EC000000CD
+:0245ED000000CC
+:0245EE000000CB
+:0245EF000000CA
+:0245F0000000C9
+:0245F1000000C8
+:0245F2000000C7
+:0245F3000000C6
+:0245F4000000C5
+:0245F5000000C4
+:0245F6000000C3
+:0245F7000000C2
+:0245F8000000C1
+:0245F9000000C0
+:0245FA000000BF
+:0245FB000000BE
+:0245FC000000BD
+:0245FD000000BC
+:0245FE000000BB
+:0245FF000000BA
+:024600000000B8
+:024601000000B7
+:024602000000B6
+:024603000000B5
+:024604000000B4
+:024605000000B3
+:024606000000B2
+:024607000000B1
+:024608000000B0
+:024609000000AF
+:02460A000000AE
+:02460B000000AD
+:02460C000000AC
+:02460D000000AB
+:02460E000000AA
+:02460F000000A9
+:024610000000A8
+:024611000000A7
+:024612000000A6
+:024613000000A5
+:024614000000A4
+:024615000000A3
+:024616000000A2
+:024617000000A1
+:024618000000A0
+:0246190000009F
+:02461A0000009E
+:02461B0000009D
+:02461C0000009C
+:02461D0000009B
+:02461E0000009A
+:02461F00000099
+:02462000000098
+:02462100000097
+:02462200000096
+:02462300000095
+:02462400000094
+:02462500000093
+:02462600000092
+:02462700000091
+:02462800000090
+:0246290000008F
+:02462A0000008E
+:02462B0000008D
+:02462C0000008C
+:02462D0000008B
+:02462E0000008A
+:02462F00000089
+:02463000000088
+:02463100000087
+:02463200000086
+:02463300000085
+:02463400000084
+:02463500000083
+:02463600000082
+:02463700000081
+:02463800000080
+:0246390000007F
+:02463A0000007E
+:02463B0000007D
+:02463C0000007C
+:02463D0000007B
+:02463E0000007A
+:02463F00000079
+:02464000000078
+:02464100000077
+:02464200000076
+:02464300000075
+:02464400000074
+:02464500000073
+:02464600000072
+:02464700000071
+:02464800000070
+:0246490000006F
+:02464A0000006E
+:02464B0000006D
+:02464C0000006C
+:02464D0000006B
+:02464E0000006A
+:02464F00000069
+:02465000000068
+:02465100000067
+:02465200000066
+:02465300000065
+:02465400000064
+:02465500000063
+:02465600000062
+:02465700000061
+:02465800000060
+:0246590000005F
+:02465A0000005E
+:02465B0000005D
+:02465C0000005C
+:02465D0000005B
+:02465E0000005A
+:02465F00000059
+:02466000000058
+:02466100000057
+:02466200000056
+:02466300000055
+:02466400000054
+:02466500000053
+:02466600000052
+:02466700000051
+:02466800000050
+:0246690000004F
+:02466A0000004E
+:02466B0000004D
+:02466C0000004C
+:02466D0000004B
+:02466E0000004A
+:02466F00000049
+:02467000000048
+:02467100000047
+:02467200000046
+:02467300000045
+:02467400000044
+:02467500000043
+:02467600000042
+:02467700000041
+:02467800000040
+:0246790000003F
+:02467A0000003E
+:02467B0000003D
+:02467C0000003C
+:02467D0000003B
+:02467E0000003A
+:02467F00000039
+:02468000000038
+:02468100000037
+:02468200000036
+:02468300000035
+:02468400000034
+:02468500000033
+:02468600000032
+:02468700000031
+:02468800000030
+:0246890000002F
+:02468A0000002E
+:02468B0000002D
+:02468C0000002C
+:02468D0000002B
+:02468E0000002A
+:02468F00000029
+:02469000000028
+:02469100000027
+:02469200000026
+:02469300000025
+:02469400000024
+:02469500000023
+:02469600000022
+:02469700000021
+:02469800000020
+:0246990000001F
+:02469A0000001E
+:02469B0000001D
+:02469C0000001C
+:02469D0000001B
+:02469E0000001A
+:02469F00000019
+:0246A000000018
+:0246A100000017
+:0246A200000016
+:0246A300000015
+:0246A400000014
+:0246A500000013
+:0246A600000012
+:0246A700000011
+:0246A800000010
+:0246A90000000F
+:0246AA0000000E
+:0246AB0000000D
+:0246AC0000000C
+:0246AD0000000B
+:0246AE0000000A
+:0246AF00000009
+:0246B000000008
+:0246B100000007
+:0246B200000006
+:0246B300000005
+:0246B400000004
+:0246B500000003
+:0246B600000002
+:0246B700000001
+:0246B800000000
+:0246B9000000FF
+:0246BA000000FE
+:0246BB000000FD
+:0246BC000000FC
+:0246BD000000FB
+:0246BE000000FA
+:0246BF000000F9
+:0246C0000000F8
+:0246C1000000F7
+:0246C2000000F6
+:0246C3000000F5
+:0246C4000000F4
+:0246C5000000F3
+:0246C6000000F2
+:0246C7000000F1
+:0246C8000000F0
+:0246C9000000EF
+:0246CA000000EE
+:0246CB000000ED
+:0246CC000000EC
+:0246CD000000EB
+:0246CE000000EA
+:0246CF000000E9
+:0246D0000000E8
+:0246D1000000E7
+:0246D2000000E6
+:0246D3000000E5
+:0246D4000000E4
+:0246D5000000E3
+:0246D6000000E2
+:0246D7000000E1
+:0246D8000000E0
+:0246D9000000DF
+:0246DA000000DE
+:0246DB000000DD
+:0246DC000000DC
+:0246DD000000DB
+:0246DE000000DA
+:0246DF000000D9
+:0246E0000000D8
+:0246E1000000D7
+:0246E2000000D6
+:0246E3000000D5
+:0246E4000000D4
+:0246E5000000D3
+:0246E6000000D2
+:0246E7000000D1
+:0246E8000000D0
+:0246E9000000CF
+:0246EA000000CE
+:0246EB000000CD
+:0246EC000000CC
+:0246ED000000CB
+:0246EE000000CA
+:0246EF000000C9
+:0246F0000000C8
+:0246F1000000C7
+:0246F2000000C6
+:0246F3000000C5
+:0246F4000000C4
+:0246F5000000C3
+:0246F6000000C2
+:0246F7000000C1
+:0246F8000000C0
+:0246F9000000BF
+:0246FA000000BE
+:0246FB000000BD
+:0246FC000000BC
+:0246FD000000BB
+:0246FE000000BA
+:0246FF000000B9
+:024700000000B7
+:024701000000B6
+:024702000000B5
+:024703000000B4
+:024704000000B3
+:024705000000B2
+:024706000000B1
+:024707000000B0
+:024708000000AF
+:024709000000AE
+:02470A000000AD
+:02470B000000AC
+:02470C000000AB
+:02470D000000AA
+:02470E000000A9
+:02470F000000A8
+:024710000000A7
+:024711000000A6
+:024712000000A5
+:024713000000A4
+:024714000000A3
+:024715000000A2
+:024716000000A1
+:024717000000A0
+:0247180000009F
+:0247190000009E
+:02471A0000009D
+:02471B0000009C
+:02471C0000009B
+:02471D0000009A
+:02471E00000099
+:02471F00000098
+:02472000000097
+:02472100000096
+:02472200000095
+:02472300000094
+:02472400000093
+:02472500000092
+:02472600000091
+:02472700000090
+:0247280000008F
+:0247290000008E
+:02472A0000008D
+:02472B0000008C
+:02472C0000008B
+:02472D0000008A
+:02472E00000089
+:02472F00000088
+:02473000000087
+:02473100000086
+:02473200000085
+:02473300000084
+:02473400000083
+:02473500000082
+:02473600000081
+:02473700000080
+:0247380000007F
+:0247390000007E
+:02473A0000007D
+:02473B0000007C
+:02473C0000007B
+:02473D0000007A
+:02473E00000079
+:02473F00000078
+:02474000000077
+:02474100000076
+:02474200000075
+:02474300000074
+:02474400000073
+:02474500000072
+:02474600000071
+:02474700000070
+:0247480000006F
+:0247490000006E
+:02474A0000006D
+:02474B0000006C
+:02474C0000006B
+:02474D0000006A
+:02474E00000069
+:02474F00000068
+:02475000000067
+:02475100000066
+:02475200000065
+:02475300000064
+:02475400000063
+:02475500000062
+:02475600000061
+:02475700000060
+:0247580000005F
+:0247590000005E
+:02475A0000005D
+:02475B0000005C
+:02475C0000005B
+:02475D0000005A
+:02475E00000059
+:02475F00000058
+:02476000000057
+:02476100000056
+:02476200000055
+:02476300000054
+:02476400000053
+:02476500000052
+:02476600000051
+:02476700000050
+:0247680000004F
+:0247690000004E
+:02476A0000004D
+:02476B0000004C
+:02476C0000004B
+:02476D0000004A
+:02476E00000049
+:02476F00000048
+:02477000000047
+:02477100000046
+:02477200000045
+:02477300000044
+:02477400000043
+:02477500000042
+:02477600000041
+:02477700000040
+:0247780000003F
+:0247790000003E
+:02477A0000003D
+:02477B0000003C
+:02477C0000003B
+:02477D0000003A
+:02477E00000039
+:02477F00000038
+:02478000000037
+:02478100000036
+:02478200000035
+:02478300000034
+:02478400000033
+:02478500000032
+:02478600000031
+:02478700000030
+:0247880000002F
+:0247890000002E
+:02478A0000002D
+:02478B0000002C
+:02478C0000002B
+:02478D0000002A
+:02478E00000029
+:02478F00000028
+:02479000000027
+:02479100000026
+:02479200000025
+:02479300000024
+:02479400000023
+:02479500000022
+:02479600000021
+:02479700000020
+:0247980000001F
+:0247990000001E
+:02479A0000001D
+:02479B0000001C
+:02479C0000001B
+:02479D0000001A
+:02479E00000019
+:02479F00000018
+:0247A000000017
+:0247A100000016
+:0247A200000015
+:0247A300000014
+:0247A400000013
+:0247A500000012
+:0247A600000011
+:0247A700000010
+:0247A80000000F
+:0247A90000000E
+:0247AA0000000D
+:0247AB0000000C
+:0247AC0000000B
+:0247AD0000000A
+:0247AE00000009
+:0247AF00000008
+:0247B000000007
+:0247B100000006
+:0247B200000005
+:0247B300000004
+:0247B400000003
+:0247B500000002
+:0247B600000001
+:0247B700000000
+:0247B8000000FF
+:0247B9000000FE
+:0247BA000000FD
+:0247BB000000FC
+:0247BC000000FB
+:0247BD000000FA
+:0247BE000000F9
+:0247BF000000F8
+:0247C0000000F7
+:0247C1000000F6
+:0247C2000000F5
+:0247C3000000F4
+:0247C4000000F3
+:0247C5000000F2
+:0247C6000000F1
+:0247C7000000F0
+:0247C8000000EF
+:0247C9000000EE
+:0247CA000000ED
+:0247CB000000EC
+:0247CC000000EB
+:0247CD000000EA
+:0247CE000000E9
+:0247CF000000E8
+:0247D0000000E7
+:0247D1000000E6
+:0247D2000000E5
+:0247D3000000E4
+:0247D4000000E3
+:0247D5000000E2
+:0247D6000000E1
+:0247D7000000E0
+:0247D8000000DF
+:0247D9000000DE
+:0247DA000000DD
+:0247DB000000DC
+:0247DC000000DB
+:0247DD000000DA
+:0247DE000000D9
+:0247DF000000D8
+:0247E0000000D7
+:0247E1000000D6
+:0247E2000000D5
+:0247E3000000D4
+:0247E4000000D3
+:0247E5000000D2
+:0247E6000000D1
+:0247E7000000D0
+:0247E8000000CF
+:0247E9000000CE
+:0247EA000000CD
+:0247EB000000CC
+:0247EC000000CB
+:0247ED000000CA
+:0247EE000000C9
+:0247EF000000C8
+:0247F0000000C7
+:0247F1000000C6
+:0247F2000000C5
+:0247F3000000C4
+:0247F4000000C3
+:0247F5000000C2
+:0247F6000000C1
+:0247F7000000C0
+:0247F8000000BF
+:0247F9000000BE
+:0247FA000000BD
+:0247FB000000BC
+:0247FC000000BB
+:0247FD000000BA
+:0247FE000000B9
+:0247FF000000B8
+:024800000000B6
+:024801000000B5
+:024802000000B4
+:024803000000B3
+:024804000000B2
+:024805000000B1
+:024806000000B0
+:024807000000AF
+:024808000000AE
+:024809000000AD
+:02480A000000AC
+:02480B000000AB
+:02480C000000AA
+:02480D000000A9
+:02480E000000A8
+:02480F000000A7
+:024810000000A6
+:024811000000A5
+:024812000000A4
+:024813000000A3
+:024814000000A2
+:024815000000A1
+:024816000000A0
+:0248170000009F
+:0248180000009E
+:0248190000009D
+:02481A0000009C
+:02481B0000009B
+:02481C0000009A
+:02481D00000099
+:02481E00000098
+:02481F00000097
+:02482000000096
+:02482100000095
+:02482200000094
+:02482300000093
+:02482400000092
+:02482500000091
+:02482600000090
+:0248270000008F
+:0248280000008E
+:0248290000008D
+:02482A0000008C
+:02482B0000008B
+:02482C0000008A
+:02482D00000089
+:02482E00000088
+:02482F00000087
+:02483000000086
+:02483100000085
+:02483200000084
+:02483300000083
+:02483400000082
+:02483500000081
+:02483600000080
+:0248370000007F
+:0248380000007E
+:0248390000007D
+:02483A0000007C
+:02483B0000007B
+:02483C0000007A
+:02483D00000079
+:02483E00000078
+:02483F00000077
+:02484000000076
+:02484100000075
+:02484200000074
+:02484300000073
+:02484400000072
+:02484500000071
+:02484600000070
+:0248470000006F
+:0248480000006E
+:0248490000006D
+:02484A0000006C
+:02484B0000006B
+:02484C0000006A
+:02484D00000069
+:02484E00000068
+:02484F00000067
+:02485000000066
+:02485100000065
+:02485200000064
+:02485300000063
+:02485400000062
+:02485500000061
+:02485600000060
+:0248570000005F
+:0248580000005E
+:0248590000005D
+:02485A0000005C
+:02485B0000005B
+:02485C0000005A
+:02485D00000059
+:02485E00000058
+:02485F00000057
+:02486000000056
+:02486100000055
+:02486200000054
+:02486300000053
+:02486400000052
+:02486500000051
+:02486600000050
+:0248670000004F
+:0248680000004E
+:0248690000004D
+:02486A0000004C
+:02486B0000004B
+:02486C0000004A
+:02486D00000049
+:02486E00000048
+:02486F00000047
+:02487000000046
+:02487100000045
+:02487200000044
+:02487300000043
+:02487400000042
+:02487500000041
+:02487600000040
+:0248770000003F
+:0248780000003E
+:0248790000003D
+:02487A0000003C
+:02487B0000003B
+:02487C0000003A
+:02487D00000039
+:02487E00000038
+:02487F00000037
+:02488000000036
+:02488100000035
+:02488200000034
+:02488300000033
+:02488400000032
+:02488500000031
+:02488600000030
+:0248870000002F
+:0248880000002E
+:0248890000002D
+:02488A0000002C
+:02488B0000002B
+:02488C0000002A
+:02488D00000029
+:02488E00000028
+:02488F00000027
+:02489000000026
+:02489100000025
+:02489200000024
+:02489300000023
+:02489400000022
+:02489500000021
+:02489600000020
+:0248970000001F
+:0248980000001E
+:0248990000001D
+:02489A0000001C
+:02489B0000001B
+:02489C0000001A
+:02489D00000019
+:02489E00000018
+:02489F00000017
+:0248A000000016
+:0248A100000015
+:0248A200000014
+:0248A300000013
+:0248A400000012
+:0248A500000011
+:0248A600000010
+:0248A70000000F
+:0248A80000000E
+:0248A90000000D
+:0248AA0000000C
+:0248AB0000000B
+:0248AC0000000A
+:0248AD00000009
+:0248AE00000008
+:0248AF00000007
+:0248B000000006
+:0248B100000005
+:0248B200000004
+:0248B300000003
+:0248B400000002
+:0248B500000001
+:0248B600000000
+:0248B7000000FF
+:0248B8000000FE
+:0248B9000000FD
+:0248BA000000FC
+:0248BB000000FB
+:0248BC000000FA
+:0248BD000000F9
+:0248BE000000F8
+:0248BF000000F7
+:0248C0000000F6
+:0248C1000000F5
+:0248C2000000F4
+:0248C3000000F3
+:0248C4000000F2
+:0248C5000000F1
+:0248C6000000F0
+:0248C7000000EF
+:0248C8000000EE
+:0248C9000000ED
+:0248CA000000EC
+:0248CB000000EB
+:0248CC000000EA
+:0248CD000000E9
+:0248CE000000E8
+:0248CF000000E7
+:0248D0000000E6
+:0248D1000000E5
+:0248D2000000E4
+:0248D3000000E3
+:0248D4000000E2
+:0248D5000000E1
+:0248D6000000E0
+:0248D7000000DF
+:0248D8000000DE
+:0248D9000000DD
+:0248DA000000DC
+:0248DB000000DB
+:0248DC000000DA
+:0248DD000000D9
+:0248DE000000D8
+:0248DF000000D7
+:0248E0000000D6
+:0248E1000000D5
+:0248E2000000D4
+:0248E3000000D3
+:0248E4000000D2
+:0248E5000000D1
+:0248E6000000D0
+:0248E7000000CF
+:0248E8000000CE
+:0248E9000000CD
+:0248EA000000CC
+:0248EB000000CB
+:0248EC000000CA
+:0248ED000000C9
+:0248EE000000C8
+:0248EF000000C7
+:0248F0000000C6
+:0248F1000000C5
+:0248F2000000C4
+:0248F3000000C3
+:0248F4000000C2
+:0248F5000000C1
+:0248F6000000C0
+:0248F7000000BF
+:0248F8000000BE
+:0248F9000000BD
+:0248FA000000BC
+:0248FB000000BB
+:0248FC000000BA
+:0248FD000000B9
+:0248FE000000B8
+:0248FF000000B7
+:024900000000B5
+:024901000000B4
+:024902000000B3
+:024903000000B2
+:024904000000B1
+:024905000000B0
+:024906000000AF
+:024907000000AE
+:024908000000AD
+:024909000000AC
+:02490A000000AB
+:02490B000000AA
+:02490C000000A9
+:02490D000000A8
+:02490E000000A7
+:02490F000000A6
+:024910000000A5
+:024911000000A4
+:024912000000A3
+:024913000000A2
+:024914000000A1
+:024915000000A0
+:0249160000009F
+:0249170000009E
+:0249180000009D
+:0249190000009C
+:02491A0000009B
+:02491B0000009A
+:02491C00000099
+:02491D00000098
+:02491E00000097
+:02491F00000096
+:02492000000095
+:02492100000094
+:02492200000093
+:02492300000092
+:02492400000091
+:02492500000090
+:0249260000008F
+:0249270000008E
+:0249280000008D
+:0249290000008C
+:02492A0000008B
+:02492B0000008A
+:02492C00000089
+:02492D00000088
+:02492E00000087
+:02492F00000086
+:02493000000085
+:02493100000084
+:02493200000083
+:02493300000082
+:02493400000081
+:02493500000080
+:0249360000007F
+:0249370000007E
+:0249380000007D
+:0249390000007C
+:02493A0000007B
+:02493B0000007A
+:02493C00000079
+:02493D00000078
+:02493E00000077
+:02493F00000076
+:02494000000075
+:02494100000074
+:02494200000073
+:02494300000072
+:02494400000071
+:02494500000070
+:0249460000006F
+:0249470000006E
+:0249480000006D
+:0249490000006C
+:02494A0000006B
+:02494B0000006A
+:02494C00000069
+:02494D00000068
+:02494E00000067
+:02494F00000066
+:02495000000065
+:02495100000064
+:02495200000063
+:02495300000062
+:02495400000061
+:02495500000060
+:0249560000005F
+:0249570000005E
+:0249580000005D
+:0249590000005C
+:02495A0000005B
+:02495B0000005A
+:02495C00000059
+:02495D00000058
+:02495E00000057
+:02495F00000056
+:02496000000055
+:02496100000054
+:02496200000053
+:02496300000052
+:02496400000051
+:02496500000050
+:0249660000004F
+:0249670000004E
+:0249680000004D
+:0249690000004C
+:02496A0000004B
+:02496B0000004A
+:02496C00000049
+:02496D00000048
+:02496E00000047
+:02496F00000046
+:02497000000045
+:02497100000044
+:02497200000043
+:02497300000042
+:02497400000041
+:02497500000040
+:0249760000003F
+:0249770000003E
+:0249780000003D
+:0249790000003C
+:02497A0000003B
+:02497B0000003A
+:02497C00000039
+:02497D00000038
+:02497E00000037
+:02497F00000036
+:02498000000035
+:02498100000034
+:02498200000033
+:02498300000032
+:02498400000031
+:02498500000030
+:0249860000002F
+:0249870000002E
+:0249880000002D
+:0249890000002C
+:02498A0000002B
+:02498B0000002A
+:02498C00000029
+:02498D00000028
+:02498E00000027
+:02498F00000026
+:02499000000025
+:02499100000024
+:02499200000023
+:02499300000022
+:02499400000021
+:02499500000020
+:0249960000001F
+:0249970000001E
+:0249980000001D
+:0249990000001C
+:02499A0000001B
+:02499B0000001A
+:02499C00000019
+:02499D00000018
+:02499E00000017
+:02499F00000016
+:0249A000000015
+:0249A100000014
+:0249A200000013
+:0249A300000012
+:0249A400000011
+:0249A500000010
+:0249A60000000F
+:0249A70000000E
+:0249A80000000D
+:0249A90000000C
+:0249AA0000000B
+:0249AB0000000A
+:0249AC00000009
+:0249AD00000008
+:0249AE00000007
+:0249AF00000006
+:0249B000000005
+:0249B100000004
+:0249B200000003
+:0249B300000002
+:0249B400000001
+:0249B500000000
+:0249B6000000FF
+:0249B7000000FE
+:0249B8000000FD
+:0249B9000000FC
+:0249BA000000FB
+:0249BB000000FA
+:0249BC000000F9
+:0249BD000000F8
+:0249BE000000F7
+:0249BF000000F6
+:0249C0000000F5
+:0249C1000000F4
+:0249C2000000F3
+:0249C3000000F2
+:0249C4000000F1
+:0249C5000000F0
+:0249C6000000EF
+:0249C7000000EE
+:0249C8000000ED
+:0249C9000000EC
+:0249CA000000EB
+:0249CB000000EA
+:0249CC000000E9
+:0249CD000000E8
+:0249CE000000E7
+:0249CF000000E6
+:0249D0000000E5
+:0249D1000000E4
+:0249D2000000E3
+:0249D3000000E2
+:0249D4000000E1
+:0249D5000000E0
+:0249D6000000DF
+:0249D7000000DE
+:0249D8000000DD
+:0249D9000000DC
+:0249DA000000DB
+:0249DB000000DA
+:0249DC000000D9
+:0249DD000000D8
+:0249DE000000D7
+:0249DF000000D6
+:0249E0000000D5
+:0249E1000000D4
+:0249E2000000D3
+:0249E3000000D2
+:0249E4000000D1
+:0249E5000000D0
+:0249E6000000CF
+:0249E7000000CE
+:0249E8000000CD
+:0249E9000000CC
+:0249EA000000CB
+:0249EB000000CA
+:0249EC000000C9
+:0249ED000000C8
+:0249EE000000C7
+:0249EF000000C6
+:0249F0000000C5
+:0249F1000000C4
+:0249F2000000C3
+:0249F3000000C2
+:0249F4000000C1
+:0249F5000000C0
+:0249F6000000BF
+:0249F7000000BE
+:0249F8000000BD
+:0249F9000000BC
+:0249FA000000BB
+:0249FB000000BA
+:0249FC000000B9
+:0249FD000000B8
+:0249FE000000B7
+:0249FF000000B6
+:024A00000000B4
+:024A01000000B3
+:024A02000000B2
+:024A03000000B1
+:024A04000000B0
+:024A05000000AF
+:024A06000000AE
+:024A07000000AD
+:024A08000000AC
+:024A09000000AB
+:024A0A000000AA
+:024A0B000000A9
+:024A0C000000A8
+:024A0D000000A7
+:024A0E000000A6
+:024A0F000000A5
+:024A10000000A4
+:024A11000000A3
+:024A12000000A2
+:024A13000000A1
+:024A14000000A0
+:024A150000009F
+:024A160000009E
+:024A170000009D
+:024A180000009C
+:024A190000009B
+:024A1A0000009A
+:024A1B00000099
+:024A1C00000098
+:024A1D00000097
+:024A1E00000096
+:024A1F00000095
+:024A2000000094
+:024A2100000093
+:024A2200000092
+:024A2300000091
+:024A2400000090
+:024A250000008F
+:024A260000008E
+:024A270000008D
+:024A280000008C
+:024A290000008B
+:024A2A0000008A
+:024A2B00000089
+:024A2C00000088
+:024A2D00000087
+:024A2E00000086
+:024A2F00000085
+:024A3000000084
+:024A3100000083
+:024A3200000082
+:024A3300000081
+:024A3400000080
+:024A350000007F
+:024A360000007E
+:024A370000007D
+:024A380000007C
+:024A390000007B
+:024A3A0000007A
+:024A3B00000079
+:024A3C00000078
+:024A3D00000077
+:024A3E00000076
+:024A3F00000075
+:024A4000000074
+:024A4100000073
+:024A4200000072
+:024A4300000071
+:024A4400000070
+:024A450000006F
+:024A460000006E
+:024A470000006D
+:024A480000006C
+:024A490000006B
+:024A4A0000006A
+:024A4B00000069
+:024A4C00000068
+:024A4D00000067
+:024A4E00000066
+:024A4F00000065
+:024A5000000064
+:024A5100000063
+:024A5200000062
+:024A5300000061
+:024A5400000060
+:024A550000005F
+:024A560000005E
+:024A570000005D
+:024A580000005C
+:024A590000005B
+:024A5A0000005A
+:024A5B00000059
+:024A5C00000058
+:024A5D00000057
+:024A5E00000056
+:024A5F00000055
+:024A6000000054
+:024A6100000053
+:024A6200000052
+:024A6300000051
+:024A6400000050
+:024A650000004F
+:024A660000004E
+:024A670000004D
+:024A680000004C
+:024A690000004B
+:024A6A0000004A
+:024A6B00000049
+:024A6C00000048
+:024A6D00000047
+:024A6E00000046
+:024A6F00000045
+:024A7000000044
+:024A7100000043
+:024A7200000042
+:024A7300000041
+:024A7400000040
+:024A750000003F
+:024A760000003E
+:024A770000003D
+:024A780000003C
+:024A790000003B
+:024A7A0000003A
+:024A7B00000039
+:024A7C00000038
+:024A7D00000037
+:024A7E00000036
+:024A7F00000035
+:024A8000000034
+:024A8100000033
+:024A8200000032
+:024A8300000031
+:024A8400000030
+:024A850000002F
+:024A860000002E
+:024A870000002D
+:024A880000002C
+:024A890000002B
+:024A8A0000002A
+:024A8B00000029
+:024A8C00000028
+:024A8D00000027
+:024A8E00000026
+:024A8F00000025
+:024A9000000024
+:024A9100000023
+:024A9200000022
+:024A9300000021
+:024A9400000020
+:024A950000001F
+:024A960000001E
+:024A970000001D
+:024A980000001C
+:024A990000001B
+:024A9A0000001A
+:024A9B00000019
+:024A9C00000018
+:024A9D00000017
+:024A9E00000016
+:024A9F00000015
+:024AA000000014
+:024AA100000013
+:024AA200000012
+:024AA300000011
+:024AA400000010
+:024AA50000000F
+:024AA60000000E
+:024AA70000000D
+:024AA80000000C
+:024AA90000000B
+:024AAA0000000A
+:024AAB00000009
+:024AAC00000008
+:024AAD00000007
+:024AAE00000006
+:024AAF00000005
+:024AB000000004
+:024AB100000003
+:024AB200000002
+:024AB300000001
+:024AB400000000
+:024AB5000000FF
+:024AB6000000FE
+:024AB7000000FD
+:024AB8000000FC
+:024AB9000000FB
+:024ABA000000FA
+:024ABB000000F9
+:024ABC000000F8
+:024ABD000000F7
+:024ABE000000F6
+:024ABF000000F5
+:024AC0000000F4
+:024AC1000000F3
+:024AC2000000F2
+:024AC3000000F1
+:024AC4000000F0
+:024AC5000000EF
+:024AC6000000EE
+:024AC7000000ED
+:024AC8000000EC
+:024AC9000000EB
+:024ACA000000EA
+:024ACB000000E9
+:024ACC000000E8
+:024ACD000000E7
+:024ACE000000E6
+:024ACF000000E5
+:024AD0000000E4
+:024AD1000000E3
+:024AD2000000E2
+:024AD3000000E1
+:024AD4000000E0
+:024AD5000000DF
+:024AD6000000DE
+:024AD7000000DD
+:024AD8000000DC
+:024AD9000000DB
+:024ADA000000DA
+:024ADB000000D9
+:024ADC000000D8
+:024ADD000000D7
+:024ADE000000D6
+:024ADF000000D5
+:024AE0000000D4
+:024AE1000000D3
+:024AE2000000D2
+:024AE3000000D1
+:024AE4000000D0
+:024AE5000000CF
+:024AE6000000CE
+:024AE7000000CD
+:024AE8000000CC
+:024AE9000000CB
+:024AEA000000CA
+:024AEB000000C9
+:024AEC000000C8
+:024AED000000C7
+:024AEE000000C6
+:024AEF000000C5
+:024AF0000000C4
+:024AF1000000C3
+:024AF2000000C2
+:024AF3000000C1
+:024AF4000000C0
+:024AF5000000BF
+:024AF6000000BE
+:024AF7000000BD
+:024AF8000000BC
+:024AF9000000BB
+:024AFA000000BA
+:024AFB000000B9
+:024AFC000000B8
+:024AFD000000B7
+:024AFE000000B6
+:024AFF000000B5
+:024B00000000B3
+:024B01000000B2
+:024B02000000B1
+:024B03000000B0
+:024B04000000AF
+:024B05000000AE
+:024B06000000AD
+:024B07000000AC
+:024B08000000AB
+:024B09000000AA
+:024B0A000000A9
+:024B0B000000A8
+:024B0C000000A7
+:024B0D000000A6
+:024B0E000000A5
+:024B0F000000A4
+:024B10000000A3
+:024B11000000A2
+:024B12000000A1
+:024B13000000A0
+:024B140000009F
+:024B150000009E
+:024B160000009D
+:024B170000009C
+:024B180000009B
+:024B190000009A
+:024B1A00000099
+:024B1B00000098
+:024B1C00000097
+:024B1D00000096
+:024B1E00000095
+:024B1F00000094
+:024B2000000093
+:024B2100000092
+:024B2200000091
+:024B2300000090
+:024B240000008F
+:024B250000008E
+:024B260000008D
+:024B270000008C
+:024B280000008B
+:024B290000008A
+:024B2A00000089
+:024B2B00000088
+:024B2C00000087
+:024B2D00000086
+:024B2E00000085
+:024B2F00000084
+:024B3000000083
+:024B3100000082
+:024B3200000081
+:024B3300000080
+:024B340000007F
+:024B350000007E
+:024B360000007D
+:024B370000007C
+:024B380000007B
+:024B390000007A
+:024B3A00000079
+:024B3B00000078
+:024B3C00000077
+:024B3D00000076
+:024B3E00000075
+:024B3F00000074
+:024B4000000073
+:024B4100000072
+:024B4200000071
+:024B4300000070
+:024B440000006F
+:024B450000006E
+:024B460000006D
+:024B470000006C
+:024B480000006B
+:024B490000006A
+:024B4A00000069
+:024B4B00000068
+:024B4C00000067
+:024B4D00000066
+:024B4E00000065
+:024B4F00000064
+:024B5000000063
+:024B5100000062
+:024B5200000061
+:024B5300000060
+:024B540000005F
+:024B550000005E
+:024B560000005D
+:024B570000005C
+:024B580000005B
+:024B590000005A
+:024B5A00000059
+:024B5B00000058
+:024B5C00000057
+:024B5D00000056
+:024B5E00000055
+:024B5F00000054
+:024B6000000053
+:024B6100000052
+:024B6200000051
+:024B6300000050
+:024B640000004F
+:024B650000004E
+:024B660000004D
+:024B670000004C
+:024B680000004B
+:024B690000004A
+:024B6A00000049
+:024B6B00000048
+:024B6C00000047
+:024B6D00000046
+:024B6E00000045
+:024B6F00000044
+:024B7000000043
+:024B7100000042
+:024B7200000041
+:024B7300000040
+:024B740000003F
+:024B750000003E
+:024B760000003D
+:024B770000003C
+:024B780000003B
+:024B790000003A
+:024B7A00000039
+:024B7B00000038
+:024B7C00000037
+:024B7D00000036
+:024B7E00000035
+:024B7F00000034
+:024B8000000033
+:024B8100000032
+:024B8200000031
+:024B8300000030
+:024B840000002F
+:024B850000002E
+:024B860000002D
+:024B870000002C
+:024B880000002B
+:024B890000002A
+:024B8A00000029
+:024B8B00000028
+:024B8C00000027
+:024B8D00000026
+:024B8E00000025
+:024B8F00000024
+:024B9000000023
+:024B9100000022
+:024B9200000021
+:024B9300000020
+:024B940000001F
+:024B950000001E
+:024B960000001D
+:024B970000001C
+:024B980000001B
+:024B990000001A
+:024B9A00000019
+:024B9B00000018
+:024B9C00000017
+:024B9D00000016
+:024B9E00000015
+:024B9F00000014
+:024BA000000013
+:024BA100000012
+:024BA200000011
+:024BA300000010
+:024BA40000000F
+:024BA50000000E
+:024BA60000000D
+:024BA70000000C
+:024BA80000000B
+:024BA90000000A
+:024BAA00000009
+:024BAB00000008
+:024BAC00000007
+:024BAD00000006
+:024BAE00000005
+:024BAF00000004
+:024BB000000003
+:024BB100000002
+:024BB200000001
+:024BB300000000
+:024BB4000000FF
+:024BB5000000FE
+:024BB6000000FD
+:024BB7000000FC
+:024BB8000000FB
+:024BB9000000FA
+:024BBA000000F9
+:024BBB000000F8
+:024BBC000000F7
+:024BBD000000F6
+:024BBE000000F5
+:024BBF000000F4
+:024BC0000000F3
+:024BC1000000F2
+:024BC2000000F1
+:024BC3000000F0
+:024BC4000000EF
+:024BC5000000EE
+:024BC6000000ED
+:024BC7000000EC
+:024BC8000000EB
+:024BC9000000EA
+:024BCA000000E9
+:024BCB000000E8
+:024BCC000000E7
+:024BCD000000E6
+:024BCE000000E5
+:024BCF000000E4
+:024BD0000000E3
+:024BD1000000E2
+:024BD2000000E1
+:024BD3000000E0
+:024BD4000000DF
+:024BD5000000DE
+:024BD6000000DD
+:024BD7000000DC
+:024BD8000000DB
+:024BD9000000DA
+:024BDA000000D9
+:024BDB000000D8
+:024BDC000000D7
+:024BDD000000D6
+:024BDE000000D5
+:024BDF000000D4
+:024BE0000000D3
+:024BE1000000D2
+:024BE2000000D1
+:024BE3000000D0
+:024BE4000000CF
+:024BE5000000CE
+:024BE6000000CD
+:024BE7000000CC
+:024BE8000000CB
+:024BE9000000CA
+:024BEA000000C9
+:024BEB000000C8
+:024BEC000000C7
+:024BED000000C6
+:024BEE000000C5
+:024BEF000000C4
+:024BF0000000C3
+:024BF1000000C2
+:024BF2000000C1
+:024BF3000000C0
+:024BF4000000BF
+:024BF5000000BE
+:024BF6000000BD
+:024BF7000000BC
+:024BF8000000BB
+:024BF9000000BA
+:024BFA000000B9
+:024BFB000000B8
+:024BFC000000B7
+:024BFD000000B6
+:024BFE000000B5
+:024BFF000000B4
+:024C00000000B2
+:024C01000000B1
+:024C02000000B0
+:024C03000000AF
+:024C04000000AE
+:024C05000000AD
+:024C06000000AC
+:024C07000000AB
+:024C08000000AA
+:024C09000000A9
+:024C0A000000A8
+:024C0B000000A7
+:024C0C000000A6
+:024C0D000000A5
+:024C0E000000A4
+:024C0F000000A3
+:024C10000000A2
+:024C11000000A1
+:024C12000000A0
+:024C130000009F
+:024C140000009E
+:024C150000009D
+:024C160000009C
+:024C170000009B
+:024C180000009A
+:024C1900000099
+:024C1A00000098
+:024C1B00000097
+:024C1C00000096
+:024C1D00000095
+:024C1E00000094
+:024C1F00000093
+:024C2000000092
+:024C2100000091
+:024C2200000090
+:024C230000008F
+:024C240000008E
+:024C250000008D
+:024C260000008C
+:024C270000008B
+:024C280000008A
+:024C2900000089
+:024C2A00000088
+:024C2B00000087
+:024C2C00000086
+:024C2D00000085
+:024C2E00000084
+:024C2F00000083
+:024C3000000082
+:024C3100000081
+:024C3200000080
+:024C330000007F
+:024C340000007E
+:024C350000007D
+:024C360000007C
+:024C370000007B
+:024C380000007A
+:024C3900000079
+:024C3A00000078
+:024C3B00000077
+:024C3C00000076
+:024C3D00000075
+:024C3E00000074
+:024C3F00000073
+:024C4000000072
+:024C4100000071
+:024C4200000070
+:024C430000006F
+:024C440000006E
+:024C450000006D
+:024C460000006C
+:024C470000006B
+:024C480000006A
+:024C4900000069
+:024C4A00000068
+:024C4B00000067
+:024C4C00000066
+:024C4D00000065
+:024C4E00000064
+:024C4F00000063
+:024C5000000062
+:024C5100000061
+:024C5200000060
+:024C530000005F
+:024C540000005E
+:024C550000005D
+:024C560000005C
+:024C570000005B
+:024C580000005A
+:024C5900000059
+:024C5A00000058
+:024C5B00000057
+:024C5C00000056
+:024C5D00000055
+:024C5E00000054
+:024C5F00000053
+:024C6000000052
+:024C6100000051
+:024C6200000050
+:024C630000004F
+:024C640000004E
+:024C650000004D
+:024C660000004C
+:024C670000004B
+:024C680000004A
+:024C6900000049
+:024C6A00000048
+:024C6B00000047
+:024C6C00000046
+:024C6D00000045
+:024C6E00000044
+:024C6F00000043
+:024C7000000042
+:024C7100000041
+:024C7200000040
+:024C730000003F
+:024C740000003E
+:024C750000003D
+:024C760000003C
+:024C770000003B
+:024C780000003A
+:024C7900000039
+:024C7A00000038
+:024C7B00000037
+:024C7C00000036
+:024C7D00000035
+:024C7E00000034
+:024C7F00000033
+:024C8000000032
+:024C8100000031
+:024C8200000030
+:024C830000002F
+:024C840000002E
+:024C850000002D
+:024C860000002C
+:024C870000002B
+:024C880000002A
+:024C8900000029
+:024C8A00000028
+:024C8B00000027
+:024C8C00000026
+:024C8D00000025
+:024C8E00000024
+:024C8F00000023
+:024C9000000022
+:024C9100000021
+:024C9200000020
+:024C930000001F
+:024C940000001E
+:024C950000001D
+:024C960000001C
+:024C970000001B
+:024C980000001A
+:024C9900000019
+:024C9A00000018
+:024C9B00000017
+:024C9C00000016
+:024C9D00000015
+:024C9E00000014
+:024C9F00000013
+:024CA000000012
+:024CA100000011
+:024CA200000010
+:024CA30000000F
+:024CA40000000E
+:024CA50000000D
+:024CA60000000C
+:024CA70000000B
+:024CA80000000A
+:024CA900000009
+:024CAA00000008
+:024CAB00000007
+:024CAC00000006
+:024CAD00000005
+:024CAE00000004
+:024CAF00000003
+:024CB000000002
+:024CB100000001
+:024CB200000000
+:024CB3000000FF
+:024CB4000000FE
+:024CB5000000FD
+:024CB6000000FC
+:024CB7000000FB
+:024CB8000000FA
+:024CB9000000F9
+:024CBA000000F8
+:024CBB000000F7
+:024CBC000000F6
+:024CBD000000F5
+:024CBE000000F4
+:024CBF000000F3
+:024CC0000000F2
+:024CC1000000F1
+:024CC2000000F0
+:024CC3000000EF
+:024CC4000000EE
+:024CC5000000ED
+:024CC6000000EC
+:024CC7000000EB
+:024CC8000000EA
+:024CC9000000E9
+:024CCA000000E8
+:024CCB000000E7
+:024CCC000000E6
+:024CCD000000E5
+:024CCE000000E4
+:024CCF000000E3
+:024CD0000000E2
+:024CD1000000E1
+:024CD2000000E0
+:024CD3000000DF
+:024CD4000000DE
+:024CD5000000DD
+:024CD6000000DC
+:024CD7000000DB
+:024CD8000000DA
+:024CD9000000D9
+:024CDA000000D8
+:024CDB000000D7
+:024CDC000000D6
+:024CDD000000D5
+:024CDE000000D4
+:024CDF000000D3
+:024CE0000000D2
+:024CE1000000D1
+:024CE2000000D0
+:024CE3000000CF
+:024CE4000000CE
+:024CE5000000CD
+:024CE6000000CC
+:024CE7000000CB
+:024CE8000000CA
+:024CE9000000C9
+:024CEA000000C8
+:024CEB000000C7
+:024CEC000000C6
+:024CED000000C5
+:024CEE000000C4
+:024CEF000000C3
+:024CF0000000C2
+:024CF1000000C1
+:024CF2000000C0
+:024CF3000000BF
+:024CF4000000BE
+:024CF5000000BD
+:024CF6000000BC
+:024CF7000000BB
+:024CF8000000BA
+:024CF9000000B9
+:024CFA000000B8
+:024CFB000000B7
+:024CFC000000B6
+:024CFD000000B5
+:024CFE000000B4
+:024CFF000000B3
+:024D00000000B1
+:024D01000000B0
+:024D02000000AF
+:024D03000000AE
+:024D04000000AD
+:024D05000000AC
+:024D06000000AB
+:024D07000000AA
+:024D08000000A9
+:024D09000000A8
+:024D0A000000A7
+:024D0B000000A6
+:024D0C000000A5
+:024D0D000000A4
+:024D0E000000A3
+:024D0F000000A2
+:024D10000000A1
+:024D11000000A0
+:024D120000009F
+:024D130000009E
+:024D140000009D
+:024D150000009C
+:024D160000009B
+:024D170000009A
+:024D1800000099
+:024D1900000098
+:024D1A00000097
+:024D1B00000096
+:024D1C00000095
+:024D1D00000094
+:024D1E00000093
+:024D1F00000092
+:024D2000000091
+:024D2100000090
+:024D220000008F
+:024D230000008E
+:024D240000008D
+:024D250000008C
+:024D260000008B
+:024D270000008A
+:024D2800000089
+:024D2900000088
+:024D2A00000087
+:024D2B00000086
+:024D2C00000085
+:024D2D00000084
+:024D2E00000083
+:024D2F00000082
+:024D3000000081
+:024D3100000080
+:024D320000007F
+:024D330000007E
+:024D340000007D
+:024D350000007C
+:024D360000007B
+:024D370000007A
+:024D3800000079
+:024D3900000078
+:024D3A00000077
+:024D3B00000076
+:024D3C00000075
+:024D3D00000074
+:024D3E00000073
+:024D3F00000072
+:024D4000000071
+:024D4100000070
+:024D420000006F
+:024D430000006E
+:024D440000006D
+:024D450000006C
+:024D460000006B
+:024D470000006A
+:024D4800000069
+:024D4900000068
+:024D4A00000067
+:024D4B00000066
+:024D4C00000065
+:024D4D00000064
+:024D4E00000063
+:024D4F00000062
+:024D5000000061
+:024D5100000060
+:024D520000005F
+:024D530000005E
+:024D540000005D
+:024D550000005C
+:024D560000005B
+:024D570000005A
+:024D5800000059
+:024D5900000058
+:024D5A00000057
+:024D5B00000056
+:024D5C00000055
+:024D5D00000054
+:024D5E00000053
+:024D5F00000052
+:024D6000000051
+:024D6100000050
+:024D620000004F
+:024D630000004E
+:024D640000004D
+:024D650000004C
+:024D660000004B
+:024D670000004A
+:024D6800000049
+:024D6900000048
+:024D6A00000047
+:024D6B00000046
+:024D6C00000045
+:024D6D00000044
+:024D6E00000043
+:024D6F00000042
+:024D7000000041
+:024D7100000040
+:024D720000003F
+:024D730000003E
+:024D740000003D
+:024D750000003C
+:024D760000003B
+:024D770000003A
+:024D7800000039
+:024D7900000038
+:024D7A00000037
+:024D7B00000036
+:024D7C00000035
+:024D7D00000034
+:024D7E00000033
+:024D7F00000032
+:024D8000000031
+:024D8100000030
+:024D820000002F
+:024D830000002E
+:024D840000002D
+:024D850000002C
+:024D860000002B
+:024D870000002A
+:024D8800000029
+:024D8900000028
+:024D8A00000027
+:024D8B00000026
+:024D8C00000025
+:024D8D00000024
+:024D8E00000023
+:024D8F00000022
+:024D9000000021
+:024D9100000020
+:024D920000001F
+:024D930000001E
+:024D940000001D
+:024D950000001C
+:024D960000001B
+:024D970000001A
+:024D9800000019
+:024D9900000018
+:024D9A00000017
+:024D9B00000016
+:024D9C00000015
+:024D9D00000014
+:024D9E00000013
+:024D9F00000012
+:024DA000000011
+:024DA100000010
+:024DA20000000F
+:024DA30000000E
+:024DA40000000D
+:024DA50000000C
+:024DA60000000B
+:024DA70000000A
+:024DA800000009
+:024DA900000008
+:024DAA00000007
+:024DAB00000006
+:024DAC00000005
+:024DAD00000004
+:024DAE00000003
+:024DAF00000002
+:024DB000000001
+:024DB100000000
+:024DB2000000FF
+:024DB3000000FE
+:024DB4000000FD
+:024DB5000000FC
+:024DB6000000FB
+:024DB7000000FA
+:024DB8000000F9
+:024DB9000000F8
+:024DBA000000F7
+:024DBB000000F6
+:024DBC000000F5
+:024DBD000000F4
+:024DBE000000F3
+:024DBF000000F2
+:024DC0000000F1
+:024DC1000000F0
+:024DC2000000EF
+:024DC3000000EE
+:024DC4000000ED
+:024DC5000000EC
+:024DC6000000EB
+:024DC7000000EA
+:024DC8000000E9
+:024DC9000000E8
+:024DCA000000E7
+:024DCB000000E6
+:024DCC000000E5
+:024DCD000000E4
+:024DCE000000E3
+:024DCF000000E2
+:024DD0000000E1
+:024DD1000000E0
+:024DD2000000DF
+:024DD3000000DE
+:024DD4000000DD
+:024DD5000000DC
+:024DD6000000DB
+:024DD7000000DA
+:024DD8000000D9
+:024DD9000000D8
+:024DDA000000D7
+:024DDB000000D6
+:024DDC000000D5
+:024DDD000000D4
+:024DDE000000D3
+:024DDF000000D2
+:024DE0000000D1
+:024DE1000000D0
+:024DE2000000CF
+:024DE3000000CE
+:024DE4000000CD
+:024DE5000000CC
+:024DE6000000CB
+:024DE7000000CA
+:024DE8000000C9
+:024DE9000000C8
+:024DEA000000C7
+:024DEB000000C6
+:024DEC000000C5
+:024DED000000C4
+:024DEE000000C3
+:024DEF000000C2
+:024DF0000000C1
+:024DF1000000C0
+:024DF2000000BF
+:024DF3000000BE
+:024DF4000000BD
+:024DF5000000BC
+:024DF6000000BB
+:024DF7000000BA
+:024DF8000000B9
+:024DF9000000B8
+:024DFA000000B7
+:024DFB000000B6
+:024DFC000000B5
+:024DFD000000B4
+:024DFE000000B3
+:024DFF000000B2
+:024E00000000B0
+:024E01000000AF
+:024E02000000AE
+:024E03000000AD
+:024E04000000AC
+:024E05000000AB
+:024E06000000AA
+:024E07000000A9
+:024E08000000A8
+:024E09000000A7
+:024E0A000000A6
+:024E0B000000A5
+:024E0C000000A4
+:024E0D000000A3
+:024E0E000000A2
+:024E0F000000A1
+:024E10000000A0
+:024E110000009F
+:024E120000009E
+:024E130000009D
+:024E140000009C
+:024E150000009B
+:024E160000009A
+:024E1700000099
+:024E1800000098
+:024E1900000097
+:024E1A00000096
+:024E1B00000095
+:024E1C00000094
+:024E1D00000093
+:024E1E00000092
+:024E1F00000091
+:024E2000000090
+:024E210000008F
+:024E220000008E
+:024E230000008D
+:024E240000008C
+:024E250000008B
+:024E260000008A
+:024E2700000089
+:024E2800000088
+:024E2900000087
+:024E2A00000086
+:024E2B00000085
+:024E2C00000084
+:024E2D00000083
+:024E2E00000082
+:024E2F00000081
+:024E3000000080
+:024E310000007F
+:024E320000007E
+:024E330000007D
+:024E340000007C
+:024E350000007B
+:024E360000007A
+:024E3700000079
+:024E3800000078
+:024E3900000077
+:024E3A00000076
+:024E3B00000075
+:024E3C00000074
+:024E3D00000073
+:024E3E00000072
+:024E3F00000071
+:024E4000000070
+:024E410000006F
+:024E420000006E
+:024E430000006D
+:024E440000006C
+:024E450000006B
+:024E460000006A
+:024E4700000069
+:024E4800000068
+:024E4900000067
+:024E4A00000066
+:024E4B00000065
+:024E4C00000064
+:024E4D00000063
+:024E4E00000062
+:024E4F00000061
+:024E5000000060
+:024E510000005F
+:024E520000005E
+:024E530000005D
+:024E540000005C
+:024E550000005B
+:024E560000005A
+:024E5700000059
+:024E5800000058
+:024E5900000057
+:024E5A00000056
+:024E5B00000055
+:024E5C00000054
+:024E5D00000053
+:024E5E00000052
+:024E5F00000051
+:024E6000000050
+:024E610000004F
+:024E620000004E
+:024E630000004D
+:024E640000004C
+:024E650000004B
+:024E660000004A
+:024E6700000049
+:024E6800000048
+:024E6900000047
+:024E6A00000046
+:024E6B00000045
+:024E6C00000044
+:024E6D00000043
+:024E6E00000042
+:024E6F00000041
+:024E7000000040
+:024E710000003F
+:024E720000003E
+:024E730000003D
+:024E740000003C
+:024E750000003B
+:024E760000003A
+:024E7700000039
+:024E7800000038
+:024E7900000037
+:024E7A00000036
+:024E7B00000035
+:024E7C00000034
+:024E7D00000033
+:024E7E00000032
+:024E7F00000031
+:024E8000000030
+:024E810000002F
+:024E820000002E
+:024E830000002D
+:024E840000002C
+:024E850000002B
+:024E860000002A
+:024E8700000029
+:024E8800000028
+:024E8900000027
+:024E8A00000026
+:024E8B00000025
+:024E8C00000024
+:024E8D00000023
+:024E8E00000022
+:024E8F00000021
+:024E9000000020
+:024E910000001F
+:024E920000001E
+:024E930000001D
+:024E940000001C
+:024E950000001B
+:024E960000001A
+:024E9700000019
+:024E9800000018
+:024E9900000017
+:024E9A00000016
+:024E9B00000015
+:024E9C00000014
+:024E9D00000013
+:024E9E00000012
+:024E9F00000011
+:024EA000000010
+:024EA10000000F
+:024EA20000000E
+:024EA30000000D
+:024EA40000000C
+:024EA50000000B
+:024EA60000000A
+:024EA700000009
+:024EA800000008
+:024EA900000007
+:024EAA00000006
+:024EAB00000005
+:024EAC00000004
+:024EAD00000003
+:024EAE00000002
+:024EAF00000001
+:024EB000000000
+:024EB1000000FF
+:024EB2000000FE
+:024EB3000000FD
+:024EB4000000FC
+:024EB5000000FB
+:024EB6000000FA
+:024EB7000000F9
+:024EB8000000F8
+:024EB9000000F7
+:024EBA000000F6
+:024EBB000000F5
+:024EBC000000F4
+:024EBD000000F3
+:024EBE000000F2
+:024EBF000000F1
+:024EC0000000F0
+:024EC1000000EF
+:024EC2000000EE
+:024EC3000000ED
+:024EC4000000EC
+:024EC5000000EB
+:024EC6000000EA
+:024EC7000000E9
+:024EC8000000E8
+:024EC9000000E7
+:024ECA000000E6
+:024ECB000000E5
+:024ECC000000E4
+:024ECD000000E3
+:024ECE000000E2
+:024ECF000000E1
+:024ED0000000E0
+:024ED1000000DF
+:024ED2000000DE
+:024ED3000000DD
+:024ED4000000DC
+:024ED5000000DB
+:024ED6000000DA
+:024ED7000000D9
+:024ED8000000D8
+:024ED9000000D7
+:024EDA000000D6
+:024EDB000000D5
+:024EDC000000D4
+:024EDD000000D3
+:024EDE000000D2
+:024EDF000000D1
+:024EE0000000D0
+:024EE1000000CF
+:024EE2000000CE
+:024EE3000000CD
+:024EE4000000CC
+:024EE5000000CB
+:024EE6000000CA
+:024EE7000000C9
+:024EE8000000C8
+:024EE9000000C7
+:024EEA000000C6
+:024EEB000000C5
+:024EEC000000C4
+:024EED000000C3
+:024EEE000000C2
+:024EEF000000C1
+:024EF0000000C0
+:024EF1000000BF
+:024EF2000000BE
+:024EF3000000BD
+:024EF4000000BC
+:024EF5000000BB
+:024EF6000000BA
+:024EF7000000B9
+:024EF8000000B8
+:024EF9000000B7
+:024EFA000000B6
+:024EFB000000B5
+:024EFC000000B4
+:024EFD000000B3
+:024EFE000000B2
+:024EFF000000B1
+:024F00000000AF
+:024F01000000AE
+:024F02000000AD
+:024F03000000AC
+:024F04000000AB
+:024F05000000AA
+:024F06000000A9
+:024F07000000A8
+:024F08000000A7
+:024F09000000A6
+:024F0A000000A5
+:024F0B000000A4
+:024F0C000000A3
+:024F0D000000A2
+:024F0E000000A1
+:024F0F000000A0
+:024F100000009F
+:024F110000009E
+:024F120000009D
+:024F130000009C
+:024F140000009B
+:024F150000009A
+:024F1600000099
+:024F1700000098
+:024F1800000097
+:024F1900000096
+:024F1A00000095
+:024F1B00000094
+:024F1C00000093
+:024F1D00000092
+:024F1E00000091
+:024F1F00000090
+:024F200000008F
+:024F210000008E
+:024F220000008D
+:024F230000008C
+:024F240000008B
+:024F250000008A
+:024F2600000089
+:024F2700000088
+:024F2800000087
+:024F2900000086
+:024F2A00000085
+:024F2B00000084
+:024F2C00000083
+:024F2D00000082
+:024F2E00000081
+:024F2F00000080
+:024F300000007F
+:024F310000007E
+:024F320000007D
+:024F330000007C
+:024F340000007B
+:024F350000007A
+:024F3600000079
+:024F3700000078
+:024F3800000077
+:024F3900000076
+:024F3A00000075
+:024F3B00000074
+:024F3C00000073
+:024F3D00000072
+:024F3E00000071
+:024F3F00000070
+:024F400000006F
+:024F410000006E
+:024F420000006D
+:024F430000006C
+:024F440000006B
+:024F450000006A
+:024F4600000069
+:024F4700000068
+:024F4800000067
+:024F4900000066
+:024F4A00000065
+:024F4B00000064
+:024F4C00000063
+:024F4D00000062
+:024F4E00000061
+:024F4F00000060
+:024F500000005F
+:024F510000005E
+:024F520000005D
+:024F530000005C
+:024F540000005B
+:024F550000005A
+:024F5600000059
+:024F5700000058
+:024F5800000057
+:024F5900000056
+:024F5A00000055
+:024F5B00000054
+:024F5C00000053
+:024F5D00000052
+:024F5E00000051
+:024F5F00000050
+:024F600000004F
+:024F610000004E
+:024F620000004D
+:024F630000004C
+:024F640000004B
+:024F650000004A
+:024F6600000049
+:024F6700000048
+:024F6800000047
+:024F6900000046
+:024F6A00000045
+:024F6B00000044
+:024F6C00000043
+:024F6D00000042
+:024F6E00000041
+:024F6F00000040
+:024F700000003F
+:024F710000003E
+:024F720000003D
+:024F730000003C
+:024F740000003B
+:024F750000003A
+:024F7600000039
+:024F7700000038
+:024F7800000037
+:024F7900000036
+:024F7A00000035
+:024F7B00000034
+:024F7C00000033
+:024F7D00000032
+:024F7E00000031
+:024F7F00000030
+:024F800000002F
+:024F810000002E
+:024F820000002D
+:024F830000002C
+:024F840000002B
+:024F850000002A
+:024F8600000029
+:024F8700000028
+:024F8800000027
+:024F8900000026
+:024F8A00000025
+:024F8B00000024
+:024F8C00000023
+:024F8D00000022
+:024F8E00000021
+:024F8F00000020
+:024F900000001F
+:024F910000001E
+:024F920000001D
+:024F930000001C
+:024F940000001B
+:024F950000001A
+:024F9600000019
+:024F9700000018
+:024F9800000017
+:024F9900000016
+:024F9A00000015
+:024F9B00000014
+:024F9C00000013
+:024F9D00000012
+:024F9E00000011
+:024F9F00000010
+:024FA00000000F
+:024FA10000000E
+:024FA20000000D
+:024FA30000000C
+:024FA40000000B
+:024FA50000000A
+:024FA600000009
+:024FA700000008
+:024FA800000007
+:024FA900000006
+:024FAA00000005
+:024FAB00000004
+:024FAC00000003
+:024FAD00000002
+:024FAE00000001
+:024FAF00000000
+:024FB0000000FF
+:024FB1000000FE
+:024FB2000000FD
+:024FB3000000FC
+:024FB4000000FB
+:024FB5000000FA
+:024FB6000000F9
+:024FB7000000F8
+:024FB8000000F7
+:024FB9000000F6
+:024FBA000000F5
+:024FBB000000F4
+:024FBC000000F3
+:024FBD000000F2
+:024FBE000000F1
+:024FBF000000F0
+:024FC0000000EF
+:024FC1000000EE
+:024FC2000000ED
+:024FC3000000EC
+:024FC4000000EB
+:024FC5000000EA
+:024FC6000000E9
+:024FC7000000E8
+:024FC8000000E7
+:024FC9000000E6
+:024FCA000000E5
+:024FCB000000E4
+:024FCC000000E3
+:024FCD000000E2
+:024FCE000000E1
+:024FCF000000E0
+:024FD0000000DF
+:024FD1000000DE
+:024FD2000000DD
+:024FD3000000DC
+:024FD4000000DB
+:024FD5000000DA
+:024FD6000000D9
+:024FD7000000D8
+:024FD8000000D7
+:024FD9000000D6
+:024FDA000000D5
+:024FDB000000D4
+:024FDC000000D3
+:024FDD000000D2
+:024FDE000000D1
+:024FDF000000D0
+:024FE0000000CF
+:024FE1000000CE
+:024FE2000000CD
+:024FE3000000CC
+:024FE4000000CB
+:024FE5000000CA
+:024FE6000000C9
+:024FE7000000C8
+:024FE8000000C7
+:024FE9000000C6
+:024FEA000000C5
+:024FEB000000C4
+:024FEC000000C3
+:024FED000000C2
+:024FEE000000C1
+:024FEF000000C0
+:024FF0000000BF
+:024FF1000000BE
+:024FF2000000BD
+:024FF3000000BC
+:024FF4000000BB
+:024FF5000000BA
+:024FF6000000B9
+:024FF7000000B8
+:024FF8000000B7
+:024FF9000000B6
+:024FFA000000B5
+:024FFB000000B4
+:024FFC000000B3
+:024FFD000000B2
+:024FFE000000B1
+:024FFF000000B0
+:025000000000AE
+:025001000000AD
+:025002000000AC
+:025003000000AB
+:025004000000AA
+:025005000000A9
+:025006000000A8
+:025007000000A7
+:025008000000A6
+:025009000000A5
+:02500A000000A4
+:02500B000000A3
+:02500C000000A2
+:02500D000000A1
+:02500E000000A0
+:02500F0000009F
+:0250100000009E
+:0250110000009D
+:0250120000009C
+:0250130000009B
+:0250140000009A
+:02501500000099
+:02501600000098
+:02501700000097
+:02501800000096
+:02501900000095
+:02501A00000094
+:02501B00000093
+:02501C00000092
+:02501D00000091
+:02501E00000090
+:02501F0000008F
+:0250200000008E
+:0250210000008D
+:0250220000008C
+:0250230000008B
+:0250240000008A
+:02502500000089
+:02502600000088
+:02502700000087
+:02502800000086
+:02502900000085
+:02502A00000084
+:02502B00000083
+:02502C00000082
+:02502D00000081
+:02502E00000080
+:02502F0000007F
+:0250300000007E
+:0250310000007D
+:0250320000007C
+:0250330000007B
+:0250340000007A
+:02503500000079
+:02503600000078
+:02503700000077
+:02503800000076
+:02503900000075
+:02503A00000074
+:02503B00000073
+:02503C00000072
+:02503D00000071
+:02503E00000070
+:02503F0000006F
+:0250400000006E
+:0250410000006D
+:0250420000006C
+:0250430000006B
+:0250440000006A
+:02504500000069
+:02504600000068
+:02504700000067
+:02504800000066
+:02504900000065
+:02504A00000064
+:02504B00000063
+:02504C00000062
+:02504D00000061
+:02504E00000060
+:02504F0000005F
+:0250500000005E
+:0250510000005D
+:0250520000005C
+:0250530000005B
+:0250540000005A
+:02505500000059
+:02505600000058
+:02505700000057
+:02505800000056
+:02505900000055
+:02505A00000054
+:02505B00000053
+:02505C00000052
+:02505D00000051
+:02505E00000050
+:02505F0000004F
+:0250600000004E
+:0250610000004D
+:0250620000004C
+:0250630000004B
+:0250640000004A
+:02506500000049
+:02506600000048
+:02506700000047
+:02506800000046
+:02506900000045
+:02506A00000044
+:02506B00000043
+:02506C00000042
+:02506D00000041
+:02506E00000040
+:02506F0000003F
+:0250700000003E
+:0250710000003D
+:0250720000003C
+:0250730000003B
+:0250740000003A
+:02507500000039
+:02507600000038
+:02507700000037
+:02507800000036
+:02507900000035
+:02507A00000034
+:02507B00000033
+:02507C00000032
+:02507D00000031
+:02507E00000030
+:02507F0000002F
+:0250800000002E
+:0250810000002D
+:0250820000002C
+:0250830000002B
+:0250840000002A
+:02508500000029
+:02508600000028
+:02508700000027
+:02508800000026
+:02508900000025
+:02508A00000024
+:02508B00000023
+:02508C00000022
+:02508D00000021
+:02508E00000020
+:02508F0000001F
+:0250900000001E
+:0250910000001D
+:0250920000001C
+:0250930000001B
+:0250940000001A
+:02509500000019
+:02509600000018
+:02509700000017
+:02509800000016
+:02509900000015
+:02509A00000014
+:02509B00000013
+:02509C00000012
+:02509D00000011
+:02509E00000010
+:02509F0000000F
+:0250A00000000E
+:0250A10000000D
+:0250A20000000C
+:0250A30000000B
+:0250A40000000A
+:0250A500000009
+:0250A600000008
+:0250A700000007
+:0250A800000006
+:0250A900000005
+:0250AA00000004
+:0250AB00000003
+:0250AC00000002
+:0250AD00000001
+:0250AE00000000
+:0250AF000000FF
+:0250B0000000FE
+:0250B1000000FD
+:0250B2000000FC
+:0250B3000000FB
+:0250B4000000FA
+:0250B5000000F9
+:0250B6000000F8
+:0250B7000000F7
+:0250B8000000F6
+:0250B9000000F5
+:0250BA000000F4
+:0250BB000000F3
+:0250BC000000F2
+:0250BD000000F1
+:0250BE000000F0
+:0250BF000000EF
+:0250C0000000EE
+:0250C1000000ED
+:0250C2000000EC
+:0250C3000000EB
+:0250C4000000EA
+:0250C5000000E9
+:0250C6000000E8
+:0250C7000000E7
+:0250C8000000E6
+:0250C9000000E5
+:0250CA000000E4
+:0250CB000000E3
+:0250CC000000E2
+:0250CD000000E1
+:0250CE000000E0
+:0250CF000000DF
+:0250D0000000DE
+:0250D1000000DD
+:0250D2000000DC
+:0250D3000000DB
+:0250D4000000DA
+:0250D5000000D9
+:0250D6000000D8
+:0250D7000000D7
+:0250D8000000D6
+:0250D9000000D5
+:0250DA000000D4
+:0250DB000000D3
+:0250DC000000D2
+:0250DD000000D1
+:0250DE000000D0
+:0250DF000000CF
+:0250E0000000CE
+:0250E1000000CD
+:0250E2000000CC
+:0250E3000000CB
+:0250E4000000CA
+:0250E5000000C9
+:0250E6000000C8
+:0250E7000000C7
+:0250E8000000C6
+:0250E9000000C5
+:0250EA000000C4
+:0250EB000000C3
+:0250EC000000C2
+:0250ED000000C1
+:0250EE000000C0
+:0250EF000000BF
+:0250F0000000BE
+:0250F1000000BD
+:0250F2000000BC
+:0250F3000000BB
+:0250F4000000BA
+:0250F5000000B9
+:0250F6000000B8
+:0250F7000000B7
+:0250F8000000B6
+:0250F9000000B5
+:0250FA000000B4
+:0250FB000000B3
+:0250FC000000B2
+:0250FD000000B1
+:0250FE000000B0
+:0250FF000000AF
+:025100000000AD
+:025101000000AC
+:025102000000AB
+:025103000000AA
+:025104000000A9
+:025105000000A8
+:025106000000A7
+:025107000000A6
+:025108000000A5
+:025109000000A4
+:02510A000000A3
+:02510B000000A2
+:02510C000000A1
+:02510D000000A0
+:02510E0000009F
+:02510F0000009E
+:0251100000009D
+:0251110000009C
+:0251120000009B
+:0251130000009A
+:02511400000099
+:02511500000098
+:02511600000097
+:02511700000096
+:02511800000095
+:02511900000094
+:02511A00000093
+:02511B00000092
+:02511C00000091
+:02511D00000090
+:02511E0000008F
+:02511F0000008E
+:0251200000008D
+:0251210000008C
+:0251220000008B
+:0251230000008A
+:02512400000089
+:02512500000088
+:02512600000087
+:02512700000086
+:02512800000085
+:02512900000084
+:02512A00000083
+:02512B00000082
+:02512C00000081
+:02512D00000080
+:02512E0000007F
+:02512F0000007E
+:0251300000007D
+:0251310000007C
+:0251320000007B
+:0251330000007A
+:02513400000079
+:02513500000078
+:02513600000077
+:02513700000076
+:02513800000075
+:02513900000074
+:02513A00000073
+:02513B00000072
+:02513C00000071
+:02513D00000070
+:02513E0000006F
+:02513F0000006E
+:0251400000006D
+:0251410000006C
+:0251420000006B
+:0251430000006A
+:02514400000069
+:02514500000068
+:02514600000067
+:02514700000066
+:02514800000065
+:02514900000064
+:02514A00000063
+:02514B00000062
+:02514C00000061
+:02514D00000060
+:02514E0000005F
+:02514F0000005E
+:0251500000005D
+:0251510000005C
+:0251520000005B
+:0251530000005A
+:02515400000059
+:02515500000058
+:02515600000057
+:02515700000056
+:02515800000055
+:02515900000054
+:02515A00000053
+:02515B00000052
+:02515C00000051
+:02515D00000050
+:02515E0000004F
+:02515F0000004E
+:0251600000004D
+:0251610000004C
+:0251620000004B
+:0251630000004A
+:02516400000049
+:02516500000048
+:02516600000047
+:02516700000046
+:02516800000045
+:02516900000044
+:02516A00000043
+:02516B00000042
+:02516C00000041
+:02516D00000040
+:02516E0000003F
+:02516F0000003E
+:0251700000003D
+:0251710000003C
+:0251720000003B
+:0251730000003A
+:02517400000039
+:02517500000038
+:02517600000037
+:02517700000036
+:02517800000035
+:02517900000034
+:02517A00000033
+:02517B00000032
+:02517C00000031
+:02517D00000030
+:02517E0000002F
+:02517F0000002E
+:0251800000002D
+:0251810000002C
+:0251820000002B
+:0251830000002A
+:02518400000029
+:02518500000028
+:02518600000027
+:02518700000026
+:02518800000025
+:02518900000024
+:02518A00000023
+:02518B00000022
+:02518C00000021
+:02518D00000020
+:02518E0000001F
+:02518F0000001E
+:0251900000001D
+:0251910000001C
+:0251920000001B
+:0251930000001A
+:02519400000019
+:02519500000018
+:02519600000017
+:02519700000016
+:02519800000015
+:02519900000014
+:02519A00000013
+:02519B00000012
+:02519C00000011
+:02519D00000010
+:02519E0000000F
+:02519F0000000E
+:0251A00000000D
+:0251A10000000C
+:0251A20000000B
+:0251A30000000A
+:0251A400000009
+:0251A500000008
+:0251A600000007
+:0251A700000006
+:0251A800000005
+:0251A900000004
+:0251AA00000003
+:0251AB00000002
+:0251AC00000001
+:0251AD00000000
+:0251AE000000FF
+:0251AF000000FE
+:0251B0000000FD
+:0251B1000000FC
+:0251B2000000FB
+:0251B3000000FA
+:0251B4000000F9
+:0251B5000000F8
+:0251B6000000F7
+:0251B7000000F6
+:0251B8000000F5
+:0251B9000000F4
+:0251BA000000F3
+:0251BB000000F2
+:0251BC000000F1
+:0251BD000000F0
+:0251BE000000EF
+:0251BF000000EE
+:0251C0000000ED
+:0251C1000000EC
+:0251C2000000EB
+:0251C3000000EA
+:0251C4000000E9
+:0251C5000000E8
+:0251C6000000E7
+:0251C7000000E6
+:0251C8000000E5
+:0251C9000000E4
+:0251CA000000E3
+:0251CB000000E2
+:0251CC000000E1
+:0251CD000000E0
+:0251CE000000DF
+:0251CF000000DE
+:0251D0000000DD
+:0251D1000000DC
+:0251D2000000DB
+:0251D3000000DA
+:0251D4000000D9
+:0251D5000000D8
+:0251D6000000D7
+:0251D7000000D6
+:0251D8000000D5
+:0251D9000000D4
+:0251DA000000D3
+:0251DB000000D2
+:0251DC000000D1
+:0251DD000000D0
+:0251DE000000CF
+:0251DF000000CE
+:0251E0000000CD
+:0251E1000000CC
+:0251E2000000CB
+:0251E3000000CA
+:0251E4000000C9
+:0251E5000000C8
+:0251E6000000C7
+:0251E7000000C6
+:0251E8000000C5
+:0251E9000000C4
+:0251EA000000C3
+:0251EB000000C2
+:0251EC000000C1
+:0251ED000000C0
+:0251EE000000BF
+:0251EF000000BE
+:0251F0000000BD
+:0251F1000000BC
+:0251F2000000BB
+:0251F3000000BA
+:0251F4000000B9
+:0251F5000000B8
+:0251F6000000B7
+:0251F7000000B6
+:0251F8000000B5
+:0251F9000000B4
+:0251FA000000B3
+:0251FB000000B2
+:0251FC000000B1
+:0251FD000000B0
+:0251FE000000AF
+:0251FF000000AE
+:025200000000AC
+:025201000000AB
+:025202000000AA
+:025203000000A9
+:025204000000A8
+:025205000000A7
+:025206000000A6
+:025207000000A5
+:025208000000A4
+:025209000000A3
+:02520A000000A2
+:02520B000000A1
+:02520C000000A0
+:02520D0000009F
+:02520E0000009E
+:02520F0000009D
+:0252100000009C
+:0252110000009B
+:0252120000009A
+:02521300000099
+:02521400000098
+:02521500000097
+:02521600000096
+:02521700000095
+:02521800000094
+:02521900000093
+:02521A00000092
+:02521B00000091
+:02521C00000090
+:02521D0000008F
+:02521E0000008E
+:02521F0000008D
+:0252200000008C
+:0252210000008B
+:0252220000008A
+:02522300000089
+:02522400000088
+:02522500000087
+:02522600000086
+:02522700000085
+:02522800000084
+:02522900000083
+:02522A00000082
+:02522B00000081
+:02522C00000080
+:02522D0000007F
+:02522E0000007E
+:02522F0000007D
+:0252300000007C
+:0252310000007B
+:0252320000007A
+:02523300000079
+:02523400000078
+:02523500000077
+:02523600000076
+:02523700000075
+:02523800000074
+:02523900000073
+:02523A00000072
+:02523B00000071
+:02523C00000070
+:02523D0000006F
+:02523E0000006E
+:02523F0000006D
+:0252400000006C
+:0252410000006B
+:0252420000006A
+:02524300000069
+:02524400000068
+:02524500000067
+:02524600000066
+:02524700000065
+:02524800000064
+:02524900000063
+:02524A00000062
+:02524B00000061
+:02524C00000060
+:02524D0000005F
+:02524E0000005E
+:02524F0000005D
+:0252500000005C
+:0252510000005B
+:0252520000005A
+:02525300000059
+:02525400000058
+:02525500000057
+:02525600000056
+:02525700000055
+:02525800000054
+:02525900000053
+:02525A00000052
+:02525B00000051
+:02525C00000050
+:02525D0000004F
+:02525E0000004E
+:02525F0000004D
+:0252600000004C
+:0252610000004B
+:0252620000004A
+:02526300000049
+:02526400000048
+:02526500000047
+:02526600000046
+:02526700000045
+:02526800000044
+:02526900000043
+:02526A00000042
+:02526B00000041
+:02526C00000040
+:02526D0000003F
+:02526E0000003E
+:02526F0000003D
+:0252700000003C
+:0252710000003B
+:0252720000003A
+:02527300000039
+:02527400000038
+:02527500000037
+:02527600000036
+:02527700000035
+:02527800000034
+:02527900000033
+:02527A00000032
+:02527B00000031
+:02527C00000030
+:02527D0000002F
+:02527E0000002E
+:02527F0000002D
+:0252800000002C
+:0252810000002B
+:0252820000002A
+:02528300000029
+:02528400000028
+:02528500000027
+:02528600000026
+:02528700000025
+:02528800000024
+:02528900000023
+:02528A00000022
+:02528B00000021
+:02528C00000020
+:02528D0000001F
+:02528E0000001E
+:02528F0000001D
+:0252900000001C
+:0252910000001B
+:0252920000001A
+:02529300000019
+:02529400000018
+:02529500000017
+:02529600000016
+:02529700000015
+:02529800000014
+:02529900000013
+:02529A00000012
+:02529B00000011
+:02529C00000010
+:02529D0000000F
+:02529E0000000E
+:02529F0000000D
+:0252A00000000C
+:0252A10000000B
+:0252A20000000A
+:0252A300000009
+:0252A400000008
+:0252A500000007
+:0252A600000006
+:0252A700000005
+:0252A800000004
+:0252A900000003
+:0252AA00000002
+:0252AB00000001
+:0252AC00000000
+:0252AD000000FF
+:0252AE000000FE
+:0252AF000000FD
+:0252B0000000FC
+:0252B1000000FB
+:0252B2000000FA
+:0252B3000000F9
+:0252B4000000F8
+:0252B5000000F7
+:0252B6000000F6
+:0252B7000000F5
+:0252B8000000F4
+:0252B9000000F3
+:0252BA000000F2
+:0252BB000000F1
+:0252BC000000F0
+:0252BD000000EF
+:0252BE000000EE
+:0252BF000000ED
+:0252C0000000EC
+:0252C1000000EB
+:0252C2000000EA
+:0252C3000000E9
+:0252C4000000E8
+:0252C5000000E7
+:0252C6000000E6
+:0252C7000000E5
+:0252C8000000E4
+:0252C9000000E3
+:0252CA000000E2
+:0252CB000000E1
+:0252CC000000E0
+:0252CD000000DF
+:0252CE000000DE
+:0252CF000000DD
+:0252D0000000DC
+:0252D1000000DB
+:0252D2000000DA
+:0252D3000000D9
+:0252D4000000D8
+:0252D5000000D7
+:0252D6000000D6
+:0252D7000000D5
+:0252D8000000D4
+:0252D9000000D3
+:0252DA000000D2
+:0252DB000000D1
+:0252DC000000D0
+:0252DD000000CF
+:0252DE000000CE
+:0252DF000000CD
+:0252E0000000CC
+:0252E1000000CB
+:0252E2000000CA
+:0252E3000000C9
+:0252E4000000C8
+:0252E5000000C7
+:0252E6000000C6
+:0252E7000000C5
+:0252E8000000C4
+:0252E9000000C3
+:0252EA000000C2
+:0252EB000000C1
+:0252EC000000C0
+:0252ED000000BF
+:0252EE000000BE
+:0252EF000000BD
+:0252F0000000BC
+:0252F1000000BB
+:0252F2000000BA
+:0252F3000000B9
+:0252F4000000B8
+:0252F5000000B7
+:0252F6000000B6
+:0252F7000000B5
+:0252F8000000B4
+:0252F9000000B3
+:0252FA000000B2
+:0252FB000000B1
+:0252FC000000B0
+:0252FD000000AF
+:0252FE000000AE
+:0252FF000000AD
+:025300000000AB
+:025301000000AA
+:025302000000A9
+:025303000000A8
+:025304000000A7
+:025305000000A6
+:025306000000A5
+:025307000000A4
+:025308000000A3
+:025309000000A2
+:02530A000000A1
+:02530B000000A0
+:02530C0000009F
+:02530D0000009E
+:02530E0000009D
+:02530F0000009C
+:0253100000009B
+:0253110000009A
+:02531200000099
+:02531300000098
+:02531400000097
+:02531500000096
+:02531600000095
+:02531700000094
+:02531800000093
+:02531900000092
+:02531A00000091
+:02531B00000090
+:02531C0000008F
+:02531D0000008E
+:02531E0000008D
+:02531F0000008C
+:0253200000008B
+:0253210000008A
+:02532200000089
+:02532300000088
+:02532400000087
+:02532500000086
+:02532600000085
+:02532700000084
+:02532800000083
+:02532900000082
+:02532A00000081
+:02532B00000080
+:02532C0000007F
+:02532D0000007E
+:02532E0000007D
+:02532F0000007C
+:0253300000007B
+:0253310000007A
+:02533200000079
+:02533300000078
+:02533400000077
+:02533500000076
+:02533600000075
+:02533700000074
+:02533800000073
+:02533900000072
+:02533A00000071
+:02533B00000070
+:02533C0000006F
+:02533D0000006E
+:02533E0000006D
+:02533F0000006C
+:0253400000006B
+:0253410000006A
+:02534200000069
+:02534300000068
+:02534400000067
+:02534500000066
+:02534600000065
+:02534700000064
+:02534800000063
+:02534900000062
+:02534A00000061
+:02534B00000060
+:02534C0000005F
+:02534D0000005E
+:02534E0000005D
+:02534F0000005C
+:0253500000005B
+:0253510000005A
+:02535200000059
+:02535300000058
+:02535400000057
+:02535500000056
+:02535600000055
+:02535700000054
+:02535800000053
+:02535900000052
+:02535A00000051
+:02535B00000050
+:02535C0000004F
+:02535D0000004E
+:02535E0000004D
+:02535F0000004C
+:0253600000004B
+:0253610000004A
+:02536200000049
+:02536300000048
+:02536400000047
+:02536500000046
+:02536600000045
+:02536700000044
+:02536800000043
+:02536900000042
+:02536A00000041
+:02536B00000040
+:02536C0000003F
+:02536D0000003E
+:02536E0000003D
+:02536F0000003C
+:0253700000003B
+:0253710000003A
+:02537200000039
+:02537300000038
+:02537400000037
+:02537500000036
+:02537600000035
+:02537700000034
+:02537800000033
+:02537900000032
+:02537A00000031
+:02537B00000030
+:02537C0000002F
+:02537D0000002E
+:02537E0000002D
+:02537F0000002C
+:0253800000002B
+:0253810000002A
+:02538200000029
+:02538300000028
+:02538400000027
+:02538500000026
+:02538600000025
+:02538700000024
+:02538800000023
+:02538900000022
+:02538A00000021
+:02538B00000020
+:02538C0000001F
+:02538D0000001E
+:02538E0000001D
+:02538F0000001C
+:0253900000001B
+:0253910000001A
+:02539200000019
+:02539300000018
+:02539400000017
+:02539500000016
+:02539600000015
+:02539700000014
+:02539800000013
+:02539900000012
+:02539A00000011
+:02539B00000010
+:02539C0000000F
+:02539D0000000E
+:02539E0000000D
+:02539F0000000C
+:0253A00000000B
+:0253A10000000A
+:0253A200000009
+:0253A300000008
+:0253A400000007
+:0253A500000006
+:0253A600000005
+:0253A700000004
+:0253A800000003
+:0253A900000002
+:0253AA00000001
+:0253AB00000000
+:0253AC000000FF
+:0253AD000000FE
+:0253AE000000FD
+:0253AF000000FC
+:0253B0000000FB
+:0253B1000000FA
+:0253B2000000F9
+:0253B3000000F8
+:0253B4000000F7
+:0253B5000000F6
+:0253B6000000F5
+:0253B7000000F4
+:0253B8000000F3
+:0253B9000000F2
+:0253BA000000F1
+:0253BB000000F0
+:0253BC000000EF
+:0253BD000000EE
+:0253BE000000ED
+:0253BF000000EC
+:0253C0000000EB
+:0253C1000000EA
+:0253C2000000E9
+:0253C3000000E8
+:0253C4000000E7
+:0253C5000000E6
+:0253C6000000E5
+:0253C7000000E4
+:0253C8000000E3
+:0253C9000000E2
+:0253CA000000E1
+:0253CB000000E0
+:0253CC000000DF
+:0253CD000000DE
+:0253CE000000DD
+:0253CF000000DC
+:0253D0000000DB
+:0253D1000000DA
+:0253D2000000D9
+:0253D3000000D8
+:0253D4000000D7
+:0253D5000000D6
+:0253D6000000D5
+:0253D7000000D4
+:0253D8000000D3
+:0253D9000000D2
+:0253DA000000D1
+:0253DB000000D0
+:0253DC000000CF
+:0253DD000000CE
+:0253DE000000CD
+:0253DF000000CC
+:0253E0000000CB
+:0253E1000000CA
+:0253E2000000C9
+:0253E3000000C8
+:0253E4000000C7
+:0253E5000000C6
+:0253E6000000C5
+:0253E7000000C4
+:0253E8000000C3
+:0253E9000000C2
+:0253EA000000C1
+:0253EB000000C0
+:0253EC000000BF
+:0253ED000000BE
+:0253EE000000BD
+:0253EF000000BC
+:0253F0000000BB
+:0253F1000000BA
+:0253F2000000B9
+:0253F3000000B8
+:0253F4000000B7
+:0253F5000000B6
+:0253F6000000B5
+:0253F7000000B4
+:0253F8000000B3
+:0253F9000000B2
+:0253FA000000B1
+:0253FB000000B0
+:0253FC000000AF
+:0253FD000000AE
+:0253FE000000AD
+:0253FF000000AC
+:025400000000AA
+:025401000000A9
+:025402000000A8
+:025403000000A7
+:025404000000A6
+:025405000000A5
+:025406000000A4
+:025407000000A3
+:025408000000A2
+:025409000000A1
+:02540A000000A0
+:02540B0000009F
+:02540C0000009E
+:02540D0000009D
+:02540E0000009C
+:02540F0000009B
+:0254100000009A
+:02541100000099
+:02541200000098
+:02541300000097
+:02541400000096
+:02541500000095
+:02541600000094
+:02541700000093
+:02541800000092
+:02541900000091
+:02541A00000090
+:02541B0000008F
+:02541C0000008E
+:02541D0000008D
+:02541E0000008C
+:02541F0000008B
+:0254200000008A
+:02542100000089
+:02542200000088
+:02542300000087
+:02542400000086
+:02542500000085
+:02542600000084
+:02542700000083
+:02542800000082
+:02542900000081
+:02542A00000080
+:02542B0000007F
+:02542C0000007E
+:02542D0000007D
+:02542E0000007C
+:02542F0000007B
+:0254300000007A
+:02543100000079
+:02543200000078
+:02543300000077
+:02543400000076
+:02543500000075
+:02543600000074
+:02543700000073
+:02543800000072
+:02543900000071
+:02543A00000070
+:02543B0000006F
+:02543C0000006E
+:02543D0000006D
+:02543E0000006C
+:02543F0000006B
+:0254400000006A
+:02544100000069
+:02544200000068
+:02544300000067
+:02544400000066
+:02544500000065
+:02544600000064
+:02544700000063
+:02544800000062
+:02544900000061
+:02544A00000060
+:02544B0000005F
+:02544C0000005E
+:02544D0000005D
+:02544E0000005C
+:02544F0000005B
+:0254500000005A
+:02545100000059
+:02545200000058
+:02545300000057
+:02545400000056
+:02545500000055
+:02545600000054
+:02545700000053
+:02545800000052
+:02545900000051
+:02545A00000050
+:02545B0000004F
+:02545C0000004E
+:02545D0000004D
+:02545E0000004C
+:02545F0000004B
+:0254600000004A
+:02546100000049
+:02546200000048
+:02546300000047
+:02546400000046
+:02546500000045
+:02546600000044
+:02546700000043
+:02546800000042
+:02546900000041
+:02546A00000040
+:02546B0000003F
+:02546C0000003E
+:02546D0000003D
+:02546E0000003C
+:02546F0000003B
+:0254700000003A
+:02547100000039
+:02547200000038
+:02547300000037
+:02547400000036
+:02547500000035
+:02547600000034
+:02547700000033
+:02547800000032
+:02547900000031
+:02547A00000030
+:02547B0000002F
+:02547C0000002E
+:02547D0000002D
+:02547E0000002C
+:02547F0000002B
+:0254800000002A
+:02548100000029
+:02548200000028
+:02548300000027
+:02548400000026
+:02548500000025
+:02548600000024
+:02548700000023
+:02548800000022
+:02548900000021
+:02548A00000020
+:02548B0000001F
+:02548C0000001E
+:02548D0000001D
+:02548E0000001C
+:02548F0000001B
+:0254900000001A
+:02549100000019
+:02549200000018
+:02549300000017
+:02549400000016
+:02549500000015
+:02549600000014
+:02549700000013
+:02549800000012
+:02549900000011
+:02549A00000010
+:02549B0000000F
+:02549C0000000E
+:02549D0000000D
+:02549E0000000C
+:02549F0000000B
+:0254A00000000A
+:0254A100000009
+:0254A200000008
+:0254A300000007
+:0254A400000006
+:0254A500000005
+:0254A600000004
+:0254A700000003
+:0254A800000002
+:0254A900000001
+:0254AA00000000
+:0254AB000000FF
+:0254AC000000FE
+:0254AD000000FD
+:0254AE000000FC
+:0254AF000000FB
+:0254B0000000FA
+:0254B1000000F9
+:0254B2000000F8
+:0254B3000000F7
+:0254B4000000F6
+:0254B5000000F5
+:0254B6000000F4
+:0254B7000000F3
+:0254B8000000F2
+:0254B9000000F1
+:0254BA000000F0
+:0254BB000000EF
+:0254BC000000EE
+:0254BD000000ED
+:0254BE000000EC
+:0254BF000000EB
+:0254C0000000EA
+:0254C1000000E9
+:0254C2000000E8
+:0254C3000000E7
+:0254C4000000E6
+:0254C5000000E5
+:0254C6000000E4
+:0254C7000000E3
+:0254C8000000E2
+:0254C9000000E1
+:0254CA000000E0
+:0254CB000000DF
+:0254CC000000DE
+:0254CD000000DD
+:0254CE000000DC
+:0254CF000000DB
+:0254D0000000DA
+:0254D1000000D9
+:0254D2000000D8
+:0254D3000000D7
+:0254D4000000D6
+:0254D5000000D5
+:0254D6000000D4
+:0254D7000000D3
+:0254D8000000D2
+:0254D9000000D1
+:0254DA000000D0
+:0254DB000000CF
+:0254DC000000CE
+:0254DD000000CD
+:0254DE000000CC
+:0254DF000000CB
+:0254E0000000CA
+:0254E1000000C9
+:0254E2000000C8
+:0254E3000000C7
+:0254E4000000C6
+:0254E5000000C5
+:0254E6000000C4
+:0254E7000000C3
+:0254E8000000C2
+:0254E9000000C1
+:0254EA000000C0
+:0254EB000000BF
+:0254EC000000BE
+:0254ED000000BD
+:0254EE000000BC
+:0254EF000000BB
+:0254F0000000BA
+:0254F1000000B9
+:0254F2000000B8
+:0254F3000000B7
+:0254F4000000B6
+:0254F5000000B5
+:0254F6000000B4
+:0254F7000000B3
+:0254F8000000B2
+:0254F9000000B1
+:0254FA000000B0
+:0254FB000000AF
+:0254FC000000AE
+:0254FD000000AD
+:0254FE000000AC
+:0254FF000000AB
+:025500000000A9
+:025501000000A8
+:025502000000A7
+:025503000000A6
+:025504000000A5
+:025505000000A4
+:025506000000A3
+:025507000000A2
+:025508000000A1
+:025509000000A0
+:02550A0000009F
+:02550B0000009E
+:02550C0000009D
+:02550D0000009C
+:02550E0000009B
+:02550F0000009A
+:02551000000099
+:02551100000098
+:02551200000097
+:02551300000096
+:02551400000095
+:02551500000094
+:02551600000093
+:02551700000092
+:02551800000091
+:02551900000090
+:02551A0000008F
+:02551B0000008E
+:02551C0000008D
+:02551D0000008C
+:02551E0000008B
+:02551F0000008A
+:02552000000089
+:02552100000088
+:02552200000087
+:02552300000086
+:02552400000085
+:02552500000084
+:02552600000083
+:02552700000082
+:02552800000081
+:02552900000080
+:02552A0000007F
+:02552B0000007E
+:02552C0000007D
+:02552D0000007C
+:02552E0000007B
+:02552F0000007A
+:02553000000079
+:02553100000078
+:02553200000077
+:02553300000076
+:02553400000075
+:02553500000074
+:02553600000073
+:02553700000072
+:02553800000071
+:02553900000070
+:02553A0000006F
+:02553B0000006E
+:02553C0000006D
+:02553D0000006C
+:02553E0000006B
+:02553F0000006A
+:02554000000069
+:02554100000068
+:02554200000067
+:02554300000066
+:02554400000065
+:02554500000064
+:02554600000063
+:02554700000062
+:02554800000061
+:02554900000060
+:02554A0000005F
+:02554B0000005E
+:02554C0000005D
+:02554D0000005C
+:02554E0000005B
+:02554F0000005A
+:02555000000059
+:02555100000058
+:02555200000057
+:02555300000056
+:02555400000055
+:02555500000054
+:02555600000053
+:02555700000052
+:02555800000051
+:02555900000050
+:02555A0000004F
+:02555B0000004E
+:02555C0000004D
+:02555D0000004C
+:02555E0000004B
+:02555F0000004A
+:02556000000049
+:02556100000048
+:02556200000047
+:02556300000046
+:02556400000045
+:02556500000044
+:02556600000043
+:02556700000042
+:02556800000041
+:02556900000040
+:02556A0000003F
+:02556B0000003E
+:02556C0000003D
+:02556D0000003C
+:02556E0000003B
+:02556F0000003A
+:02557000000039
+:02557100000038
+:02557200000037
+:02557300000036
+:02557400000035
+:02557500000034
+:02557600000033
+:02557700000032
+:02557800000031
+:02557900000030
+:02557A0000002F
+:02557B0000002E
+:02557C0000002D
+:02557D0000002C
+:02557E0000002B
+:02557F0000002A
+:02558000000029
+:02558100000028
+:02558200000027
+:02558300000026
+:02558400000025
+:02558500000024
+:02558600000023
+:02558700000022
+:02558800000021
+:02558900000020
+:02558A0000001F
+:02558B0000001E
+:02558C0000001D
+:02558D0000001C
+:02558E0000001B
+:02558F0000001A
+:02559000000019
+:02559100000018
+:02559200000017
+:02559300000016
+:02559400000015
+:02559500000014
+:02559600000013
+:02559700000012
+:02559800000011
+:02559900000010
+:02559A0000000F
+:02559B0000000E
+:02559C0000000D
+:02559D0000000C
+:02559E0000000B
+:02559F0000000A
+:0255A000000009
+:0255A100000008
+:0255A200000007
+:0255A300000006
+:0255A400000005
+:0255A500000004
+:0255A600000003
+:0255A700000002
+:0255A800000001
+:0255A900000000
+:0255AA000000FF
+:0255AB000000FE
+:0255AC000000FD
+:0255AD000000FC
+:0255AE000000FB
+:0255AF000000FA
+:0255B0000000F9
+:0255B1000000F8
+:0255B2000000F7
+:0255B3000000F6
+:0255B4000000F5
+:0255B5000000F4
+:0255B6000000F3
+:0255B7000000F2
+:0255B8000000F1
+:0255B9000000F0
+:0255BA000000EF
+:0255BB000000EE
+:0255BC000000ED
+:0255BD000000EC
+:0255BE000000EB
+:0255BF000000EA
+:0255C0000000E9
+:0255C1000000E8
+:0255C2000000E7
+:0255C3000000E6
+:0255C4000000E5
+:0255C5000000E4
+:0255C6000000E3
+:0255C7000000E2
+:0255C8000000E1
+:0255C9000000E0
+:0255CA000000DF
+:0255CB000000DE
+:0255CC000000DD
+:0255CD000000DC
+:0255CE000000DB
+:0255CF000000DA
+:0255D0000000D9
+:0255D1000000D8
+:0255D2000000D7
+:0255D3000000D6
+:0255D4000000D5
+:0255D5000000D4
+:0255D6000000D3
+:0255D7000000D2
+:0255D8000000D1
+:0255D9000000D0
+:0255DA000000CF
+:0255DB000000CE
+:0255DC000000CD
+:0255DD000000CC
+:0255DE000000CB
+:0255DF000000CA
+:0255E0000000C9
+:0255E1000000C8
+:0255E2000000C7
+:0255E3000000C6
+:0255E4000000C5
+:0255E5000000C4
+:0255E6000000C3
+:0255E7000000C2
+:0255E8000000C1
+:0255E9000000C0
+:0255EA000000BF
+:0255EB000000BE
+:0255EC000000BD
+:0255ED000000BC
+:0255EE000000BB
+:0255EF000000BA
+:0255F0000000B9
+:0255F1000000B8
+:0255F2000000B7
+:0255F3000000B6
+:0255F4000000B5
+:0255F5000000B4
+:0255F6000000B3
+:0255F7000000B2
+:0255F8000000B1
+:0255F9000000B0
+:0255FA000000AF
+:0255FB000000AE
+:0255FC000000AD
+:0255FD000000AC
+:0255FE000000AB
+:0255FF000000AA
+:025600000000A8
+:025601000000A7
+:025602000000A6
+:025603000000A5
+:025604000000A4
+:025605000000A3
+:025606000000A2
+:025607000000A1
+:025608000000A0
+:0256090000009F
+:02560A0000009E
+:02560B0000009D
+:02560C0000009C
+:02560D0000009B
+:02560E0000009A
+:02560F00000099
+:02561000000098
+:02561100000097
+:02561200000096
+:02561300000095
+:02561400000094
+:02561500000093
+:02561600000092
+:02561700000091
+:02561800000090
+:0256190000008F
+:02561A0000008E
+:02561B0000008D
+:02561C0000008C
+:02561D0000008B
+:02561E0000008A
+:02561F00000089
+:02562000000088
+:02562100000087
+:02562200000086
+:02562300000085
+:02562400000084
+:02562500000083
+:02562600000082
+:02562700000081
+:02562800000080
+:0256290000007F
+:02562A0000007E
+:02562B0000007D
+:02562C0000007C
+:02562D0000007B
+:02562E0000007A
+:02562F00000079
+:02563000000078
+:02563100000077
+:02563200000076
+:02563300000075
+:02563400000074
+:02563500000073
+:02563600000072
+:02563700000071
+:02563800000070
+:0256390000006F
+:02563A0000006E
+:02563B0000006D
+:02563C0000006C
+:02563D0000006B
+:02563E0000006A
+:02563F00000069
+:02564000000068
+:02564100000067
+:02564200000066
+:02564300000065
+:02564400000064
+:02564500000063
+:02564600000062
+:02564700000061
+:02564800000060
+:0256490000005F
+:02564A0000005E
+:02564B0000005D
+:02564C0000005C
+:02564D0000005B
+:02564E0000005A
+:02564F00000059
+:02565000000058
+:02565100000057
+:02565200000056
+:02565300000055
+:02565400000054
+:02565500000053
+:02565600000052
+:02565700000051
+:02565800000050
+:0256590000004F
+:02565A0000004E
+:02565B0000004D
+:02565C0000004C
+:02565D0000004B
+:02565E0000004A
+:02565F00000049
+:02566000000048
+:02566100000047
+:02566200000046
+:02566300000045
+:02566400000044
+:02566500000043
+:02566600000042
+:02566700000041
+:02566800000040
+:0256690000003F
+:02566A0000003E
+:02566B0000003D
+:02566C0000003C
+:02566D0000003B
+:02566E0000003A
+:02566F00000039
+:02567000000038
+:02567100000037
+:02567200000036
+:02567300000035
+:02567400000034
+:02567500000033
+:02567600000032
+:02567700000031
+:02567800000030
+:0256790000002F
+:02567A0000002E
+:02567B0000002D
+:02567C0000002C
+:02567D0000002B
+:02567E0000002A
+:02567F00000029
+:02568000000028
+:02568100000027
+:02568200000026
+:02568300000025
+:02568400000024
+:02568500000023
+:02568600000022
+:02568700000021
+:02568800000020
+:0256890000001F
+:02568A0000001E
+:02568B0000001D
+:02568C0000001C
+:02568D0000001B
+:02568E0000001A
+:02568F00000019
+:02569000000018
+:02569100000017
+:02569200000016
+:02569300000015
+:02569400000014
+:02569500000013
+:02569600000012
+:02569700000011
+:02569800000010
+:0256990000000F
+:02569A0000000E
+:02569B0000000D
+:02569C0000000C
+:02569D0000000B
+:02569E0000000A
+:02569F00000009
+:0256A000000008
+:0256A100000007
+:0256A200000006
+:0256A300000005
+:0256A400000004
+:0256A500000003
+:0256A600000002
+:0256A700000001
+:0256A800000000
+:0256A9000000FF
+:0256AA000000FE
+:0256AB000000FD
+:0256AC000000FC
+:0256AD000000FB
+:0256AE000000FA
+:0256AF000000F9
+:0256B0000000F8
+:0256B1000000F7
+:0256B2000000F6
+:0256B3000000F5
+:0256B4000000F4
+:0256B5000000F3
+:0256B6000000F2
+:0256B7000000F1
+:0256B8000000F0
+:0256B9000000EF
+:0256BA000000EE
+:0256BB000000ED
+:0256BC000000EC
+:0256BD000000EB
+:0256BE000000EA
+:0256BF000000E9
+:0256C0000000E8
+:0256C1000000E7
+:0256C2000000E6
+:0256C3000000E5
+:0256C4000000E4
+:0256C5000000E3
+:0256C6000000E2
+:0256C7000000E1
+:0256C8000000E0
+:0256C9000000DF
+:0256CA000000DE
+:0256CB000000DD
+:0256CC000000DC
+:0256CD000000DB
+:0256CE000000DA
+:0256CF000000D9
+:0256D0000000D8
+:0256D1000000D7
+:0256D2000000D6
+:0256D3000000D5
+:0256D4000000D4
+:0256D5000000D3
+:0256D6000000D2
+:0256D7000000D1
+:0256D8000000D0
+:0256D9000000CF
+:0256DA000000CE
+:0256DB000000CD
+:0256DC000000CC
+:0256DD000000CB
+:0256DE000000CA
+:0256DF000000C9
+:0256E0000000C8
+:0256E1000000C7
+:0256E2000000C6
+:0256E3000000C5
+:0256E4000000C4
+:0256E5000000C3
+:0256E6000000C2
+:0256E7000000C1
+:0256E8000000C0
+:0256E9000000BF
+:0256EA000000BE
+:0256EB000000BD
+:0256EC000000BC
+:0256ED000000BB
+:0256EE000000BA
+:0256EF000000B9
+:0256F0000000B8
+:0256F1000000B7
+:0256F2000000B6
+:0256F3000000B5
+:0256F4000000B4
+:0256F5000000B3
+:0256F6000000B2
+:0256F7000000B1
+:0256F8000000B0
+:0256F9000000AF
+:0256FA000000AE
+:0256FB000000AD
+:0256FC000000AC
+:0256FD000000AB
+:0256FE000000AA
+:0256FF000000A9
+:025700000000A7
+:025701000000A6
+:025702000000A5
+:025703000000A4
+:025704000000A3
+:025705000000A2
+:025706000000A1
+:025707000000A0
+:0257080000009F
+:0257090000009E
+:02570A0000009D
+:02570B0000009C
+:02570C0000009B
+:02570D0000009A
+:02570E00000099
+:02570F00000098
+:02571000000097
+:02571100000096
+:02571200000095
+:02571300000094
+:02571400000093
+:02571500000092
+:02571600000091
+:02571700000090
+:0257180000008F
+:0257190000008E
+:02571A0000008D
+:02571B0000008C
+:02571C0000008B
+:02571D0000008A
+:02571E00000089
+:02571F00000088
+:02572000000087
+:02572100000086
+:02572200000085
+:02572300000084
+:02572400000083
+:02572500000082
+:02572600000081
+:02572700000080
+:0257280000007F
+:0257290000007E
+:02572A0000007D
+:02572B0000007C
+:02572C0000007B
+:02572D0000007A
+:02572E00000079
+:02572F00000078
+:02573000000077
+:02573100000076
+:02573200000075
+:02573300000074
+:02573400000073
+:02573500000072
+:02573600000071
+:02573700000070
+:0257380000006F
+:0257390000006E
+:02573A0000006D
+:02573B0000006C
+:02573C0000006B
+:02573D0000006A
+:02573E00000069
+:02573F00000068
+:02574000000067
+:02574100000066
+:02574200000065
+:02574300000064
+:02574400000063
+:02574500000062
+:02574600000061
+:02574700000060
+:0257480000005F
+:0257490000005E
+:02574A0000005D
+:02574B0000005C
+:02574C0000005B
+:02574D0000005A
+:02574E00000059
+:02574F00000058
+:02575000000057
+:02575100000056
+:02575200000055
+:02575300000054
+:02575400000053
+:02575500000052
+:02575600000051
+:02575700000050
+:0257580000004F
+:0257590000004E
+:02575A0000004D
+:02575B0000004C
+:02575C0000004B
+:02575D0000004A
+:02575E00000049
+:02575F00000048
+:02576000000047
+:02576100000046
+:02576200000045
+:02576300000044
+:02576400000043
+:02576500000042
+:02576600000041
+:02576700000040
+:0257680000003F
+:0257690000003E
+:02576A0000003D
+:02576B0000003C
+:02576C0000003B
+:02576D0000003A
+:02576E00000039
+:02576F00000038
+:02577000000037
+:02577100000036
+:02577200000035
+:02577300000034
+:02577400000033
+:02577500000032
+:02577600000031
+:02577700000030
+:0257780000002F
+:0257790000002E
+:02577A0000002D
+:02577B0000002C
+:02577C0000002B
+:02577D0000002A
+:02577E00000029
+:02577F00000028
+:02578000000027
+:02578100000026
+:02578200000025
+:02578300000024
+:02578400000023
+:02578500000022
+:02578600000021
+:02578700000020
+:0257880000001F
+:0257890000001E
+:02578A0000001D
+:02578B0000001C
+:02578C0000001B
+:02578D0000001A
+:02578E00000019
+:02578F00000018
+:02579000000017
+:02579100000016
+:02579200000015
+:02579300000014
+:02579400000013
+:02579500000012
+:02579600000011
+:02579700000010
+:0257980000000F
+:0257990000000E
+:02579A0000000D
+:02579B0000000C
+:02579C0000000B
+:02579D0000000A
+:02579E00000009
+:02579F00000008
+:0257A000000007
+:0257A100000006
+:0257A200000005
+:0257A300000004
+:0257A400000003
+:0257A500000002
+:0257A600000001
+:0257A700000000
+:0257A8000000FF
+:0257A9000000FE
+:0257AA000000FD
+:0257AB000000FC
+:0257AC000000FB
+:0257AD000000FA
+:0257AE000000F9
+:0257AF000000F8
+:0257B0000000F7
+:0257B1000000F6
+:0257B2000000F5
+:0257B3000000F4
+:0257B4000000F3
+:0257B5000000F2
+:0257B6000000F1
+:0257B7000000F0
+:0257B8000000EF
+:0257B9000000EE
+:0257BA000000ED
+:0257BB000000EC
+:0257BC000000EB
+:0257BD000000EA
+:0257BE000000E9
+:0257BF000000E8
+:0257C0000000E7
+:0257C1000000E6
+:0257C2000000E5
+:0257C3000000E4
+:0257C4000000E3
+:0257C5000000E2
+:0257C6000000E1
+:0257C7000000E0
+:0257C8000000DF
+:0257C9000000DE
+:0257CA000000DD
+:0257CB000000DC
+:0257CC000000DB
+:0257CD000000DA
+:0257CE000000D9
+:0257CF000000D8
+:0257D0000000D7
+:0257D1000000D6
+:0257D2000000D5
+:0257D3000000D4
+:0257D4000000D3
+:0257D5000000D2
+:0257D6000000D1
+:0257D7000000D0
+:0257D8000000CF
+:0257D9000000CE
+:0257DA000000CD
+:0257DB000000CC
+:0257DC000000CB
+:0257DD000000CA
+:0257DE000000C9
+:0257DF000000C8
+:0257E0000000C7
+:0257E1000000C6
+:0257E2000000C5
+:0257E3000000C4
+:0257E4000000C3
+:0257E5000000C2
+:0257E6000000C1
+:0257E7000000C0
+:0257E8000000BF
+:0257E9000000BE
+:0257EA000000BD
+:0257EB000000BC
+:0257EC000000BB
+:0257ED000000BA
+:0257EE000000B9
+:0257EF000000B8
+:0257F0000000B7
+:0257F1000000B6
+:0257F2000000B5
+:0257F3000000B4
+:0257F4000000B3
+:0257F5000000B2
+:0257F6000000B1
+:0257F7000000B0
+:0257F8000000AF
+:0257F9000000AE
+:0257FA000000AD
+:0257FB000000AC
+:0257FC000000AB
+:0257FD000000AA
+:0257FE000000A9
+:0257FF000000A8
+:025800000000A6
+:025801000000A5
+:025802000000A4
+:025803000000A3
+:025804000000A2
+:025805000000A1
+:025806000000A0
+:0258070000009F
+:0258080000009E
+:0258090000009D
+:02580A0000009C
+:02580B0000009B
+:02580C0000009A
+:02580D00000099
+:02580E00000098
+:02580F00000097
+:02581000000096
+:02581100000095
+:02581200000094
+:02581300000093
+:02581400000092
+:02581500000091
+:02581600000090
+:0258170000008F
+:0258180000008E
+:0258190000008D
+:02581A0000008C
+:02581B0000008B
+:02581C0000008A
+:02581D00000089
+:02581E00000088
+:02581F00000087
+:02582000000086
+:02582100000085
+:02582200000084
+:02582300000083
+:02582400000082
+:02582500000081
+:02582600000080
+:0258270000007F
+:0258280000007E
+:0258290000007D
+:02582A0000007C
+:02582B0000007B
+:02582C0000007A
+:02582D00000079
+:02582E00000078
+:02582F00000077
+:02583000000076
+:02583100000075
+:02583200000074
+:02583300000073
+:02583400000072
+:02583500000071
+:02583600000070
+:0258370000006F
+:0258380000006E
+:0258390000006D
+:02583A0000006C
+:02583B0000006B
+:02583C0000006A
+:02583D00000069
+:02583E00000068
+:02583F00000067
+:02584000000066
+:02584100000065
+:02584200000064
+:02584300000063
+:02584400000062
+:02584500000061
+:02584600000060
+:0258470000005F
+:0258480000005E
+:0258490000005D
+:02584A0000005C
+:02584B0000005B
+:02584C0000005A
+:02584D00000059
+:02584E00000058
+:02584F00000057
+:02585000000056
+:02585100000055
+:02585200000054
+:02585300000053
+:02585400000052
+:02585500000051
+:02585600000050
+:0258570000004F
+:0258580000004E
+:0258590000004D
+:02585A0000004C
+:02585B0000004B
+:02585C0000004A
+:02585D00000049
+:02585E00000048
+:02585F00000047
+:02586000000046
+:02586100000045
+:02586200000044
+:02586300000043
+:02586400000042
+:02586500000041
+:02586600000040
+:0258670000003F
+:0258680000003E
+:0258690000003D
+:02586A0000003C
+:02586B0000003B
+:02586C0000003A
+:02586D00000039
+:02586E00000038
+:02586F00000037
+:02587000000036
+:02587100000035
+:02587200000034
+:02587300000033
+:02587400000032
+:02587500000031
+:02587600000030
+:0258770000002F
+:0258780000002E
+:0258790000002D
+:02587A0000002C
+:02587B0000002B
+:02587C0000002A
+:02587D00000029
+:02587E00000028
+:02587F00000027
+:02588000000026
+:02588100000025
+:02588200000024
+:02588300000023
+:02588400000022
+:02588500000021
+:02588600000020
+:0258870000001F
+:0258880000001E
+:0258890000001D
+:02588A0000001C
+:02588B0000001B
+:02588C0000001A
+:02588D00000019
+:02588E00000018
+:02588F00000017
+:02589000000016
+:02589100000015
+:02589200000014
+:02589300000013
+:02589400000012
+:02589500000011
+:02589600000010
+:0258970000000F
+:0258980000000E
+:0258990000000D
+:02589A0000000C
+:02589B0000000B
+:02589C0000000A
+:02589D00000009
+:02589E00000008
+:02589F00000007
+:0258A000000006
+:0258A100000005
+:0258A200000004
+:0258A300000003
+:0258A400000002
+:0258A500000001
+:0258A600000000
+:0258A7000000FF
+:0258A8000000FE
+:0258A9000000FD
+:0258AA000000FC
+:0258AB000000FB
+:0258AC000000FA
+:0258AD000000F9
+:0258AE000000F8
+:0258AF000000F7
+:0258B0000000F6
+:0258B1000000F5
+:0258B2000000F4
+:0258B3000000F3
+:0258B4000000F2
+:0258B5000000F1
+:0258B6000000F0
+:0258B7000000EF
+:0258B8000000EE
+:0258B9000000ED
+:0258BA000000EC
+:0258BB000000EB
+:0258BC000000EA
+:0258BD000000E9
+:0258BE000000E8
+:0258BF000000E7
+:0258C0000000E6
+:0258C1000000E5
+:0258C2000000E4
+:0258C3000000E3
+:0258C4000000E2
+:0258C5000000E1
+:0258C6000000E0
+:0258C7000000DF
+:0258C8000000DE
+:0258C9000000DD
+:0258CA000000DC
+:0258CB000000DB
+:0258CC000000DA
+:0258CD000000D9
+:0258CE000000D8
+:0258CF000000D7
+:0258D0000000D6
+:0258D1000000D5
+:0258D2000000D4
+:0258D3000000D3
+:0258D4000000D2
+:0258D5000000D1
+:0258D6000000D0
+:0258D7000000CF
+:0258D8000000CE
+:0258D9000000CD
+:0258DA000000CC
+:0258DB000000CB
+:0258DC000000CA
+:0258DD000000C9
+:0258DE000000C8
+:0258DF000000C7
+:0258E0000000C6
+:0258E1000000C5
+:0258E2000000C4
+:0258E3000000C3
+:0258E4000000C2
+:0258E5000000C1
+:0258E6000000C0
+:0258E7000000BF
+:0258E8000000BE
+:0258E9000000BD
+:0258EA000000BC
+:0258EB000000BB
+:0258EC000000BA
+:0258ED000000B9
+:0258EE000000B8
+:0258EF000000B7
+:0258F0000000B6
+:0258F1000000B5
+:0258F2000000B4
+:0258F3000000B3
+:0258F4000000B2
+:0258F5000000B1
+:0258F6000000B0
+:0258F7000000AF
+:0258F8000000AE
+:0258F9000000AD
+:0258FA000000AC
+:0258FB000000AB
+:0258FC000000AA
+:0258FD000000A9
+:0258FE000000A8
+:0258FF000000A7
+:025900000000A5
+:025901000000A4
+:025902000000A3
+:025903000000A2
+:025904000000A1
+:025905000000A0
+:0259060000009F
+:0259070000009E
+:0259080000009D
+:0259090000009C
+:02590A0000009B
+:02590B0000009A
+:02590C00000099
+:02590D00000098
+:02590E00000097
+:02590F00000096
+:02591000000095
+:02591100000094
+:02591200000093
+:02591300000092
+:02591400000091
+:02591500000090
+:0259160000008F
+:0259170000008E
+:0259180000008D
+:0259190000008C
+:02591A0000008B
+:02591B0000008A
+:02591C00000089
+:02591D00000088
+:02591E00000087
+:02591F00000086
+:02592000000085
+:02592100000084
+:02592200000083
+:02592300000082
+:02592400000081
+:02592500000080
+:0259260000007F
+:0259270000007E
+:0259280000007D
+:0259290000007C
+:02592A0000007B
+:02592B0000007A
+:02592C00000079
+:02592D00000078
+:02592E00000077
+:02592F00000076
+:02593000000075
+:02593100000074
+:02593200000073
+:02593300000072
+:02593400000071
+:02593500000070
+:0259360000006F
+:0259370000006E
+:0259380000006D
+:0259390000006C
+:02593A0000006B
+:02593B0000006A
+:02593C00000069
+:02593D00000068
+:02593E00000067
+:02593F00000066
+:02594000000065
+:02594100000064
+:02594200000063
+:02594300000062
+:02594400000061
+:02594500000060
+:0259460000005F
+:0259470000005E
+:0259480000005D
+:0259490000005C
+:02594A0000005B
+:02594B0000005A
+:02594C00000059
+:02594D00000058
+:02594E00000057
+:02594F00000056
+:02595000000055
+:02595100000054
+:02595200000053
+:02595300000052
+:02595400000051
+:02595500000050
+:0259560000004F
+:0259570000004E
+:0259580000004D
+:0259590000004C
+:02595A0000004B
+:02595B0000004A
+:02595C00000049
+:02595D00000048
+:02595E00000047
+:02595F00000046
+:02596000000045
+:02596100000044
+:02596200000043
+:02596300000042
+:02596400000041
+:02596500000040
+:0259660000003F
+:0259670000003E
+:0259680000003D
+:0259690000003C
+:02596A0000003B
+:02596B0000003A
+:02596C00000039
+:02596D00000038
+:02596E00000037
+:02596F00000036
+:02597000000035
+:02597100000034
+:02597200000033
+:02597300000032
+:02597400000031
+:02597500000030
+:0259760000002F
+:0259770000002E
+:0259780000002D
+:0259790000002C
+:02597A0000002B
+:02597B0000002A
+:02597C00000029
+:02597D00000028
+:02597E00000027
+:02597F00000026
+:02598000000025
+:02598100000024
+:02598200000023
+:02598300000022
+:02598400000021
+:02598500000020
+:0259860000001F
+:0259870000001E
+:0259880000001D
+:0259890000001C
+:02598A0000001B
+:02598B0000001A
+:02598C00000019
+:02598D00000018
+:02598E00000017
+:02598F00000016
+:02599000000015
+:02599100000014
+:02599200000013
+:02599300000012
+:02599400000011
+:02599500000010
+:0259960000000F
+:0259970000000E
+:0259980000000D
+:0259990000000C
+:02599A0000000B
+:02599B0000000A
+:02599C00000009
+:02599D00000008
+:02599E00000007
+:02599F00000006
+:0259A000000005
+:0259A100000004
+:0259A200000003
+:0259A300000002
+:0259A400000001
+:0259A500000000
+:0259A6000000FF
+:0259A7000000FE
+:0259A8000000FD
+:0259A9000000FC
+:0259AA000000FB
+:0259AB000000FA
+:0259AC000000F9
+:0259AD000000F8
+:0259AE000000F7
+:0259AF000000F6
+:0259B0000000F5
+:0259B1000000F4
+:0259B2000000F3
+:0259B3000000F2
+:0259B4000000F1
+:0259B5000000F0
+:0259B6000000EF
+:0259B7000000EE
+:0259B8000000ED
+:0259B9000000EC
+:0259BA000000EB
+:0259BB000000EA
+:0259BC000000E9
+:0259BD000000E8
+:0259BE000000E7
+:0259BF000000E6
+:0259C0000000E5
+:0259C1000000E4
+:0259C2000000E3
+:0259C3000000E2
+:0259C4000000E1
+:0259C5000000E0
+:0259C6000000DF
+:0259C7000000DE
+:0259C8000000DD
+:0259C9000000DC
+:0259CA000000DB
+:0259CB000000DA
+:0259CC000000D9
+:0259CD000000D8
+:0259CE000000D7
+:0259CF000000D6
+:0259D0000000D5
+:0259D1000000D4
+:0259D2000000D3
+:0259D3000000D2
+:0259D4000000D1
+:0259D5000000D0
+:0259D6000000CF
+:0259D7000000CE
+:0259D8000000CD
+:0259D9000000CC
+:0259DA000000CB
+:0259DB000000CA
+:0259DC000000C9
+:0259DD000000C8
+:0259DE000000C7
+:0259DF000000C6
+:0259E0000000C5
+:0259E1000000C4
+:0259E2000000C3
+:0259E3000000C2
+:0259E4000000C1
+:0259E5000000C0
+:0259E6000000BF
+:0259E7000000BE
+:0259E8000000BD
+:0259E9000000BC
+:0259EA000000BB
+:0259EB000000BA
+:0259EC000000B9
+:0259ED000000B8
+:0259EE000000B7
+:0259EF000000B6
+:0259F0000000B5
+:0259F1000000B4
+:0259F2000000B3
+:0259F3000000B2
+:0259F4000000B1
+:0259F5000000B0
+:0259F6000000AF
+:0259F7000000AE
+:0259F8000000AD
+:0259F9000000AC
+:0259FA000000AB
+:0259FB000000AA
+:0259FC000000A9
+:0259FD000000A8
+:0259FE000000A7
+:0259FF000000A6
+:025A00000000A4
+:025A01000000A3
+:025A02000000A2
+:025A03000000A1
+:025A04000000A0
+:025A050000009F
+:025A060000009E
+:025A070000009D
+:025A080000009C
+:025A090000009B
+:025A0A0000009A
+:025A0B00000099
+:025A0C00000098
+:025A0D00000097
+:025A0E00000096
+:025A0F00000095
+:025A1000000094
+:025A1100000093
+:025A1200000092
+:025A1300000091
+:025A1400000090
+:025A150000008F
+:025A160000008E
+:025A170000008D
+:025A180000008C
+:025A190000008B
+:025A1A0000008A
+:025A1B00000089
+:025A1C00000088
+:025A1D00000087
+:025A1E00000086
+:025A1F00000085
+:025A2000000084
+:025A2100000083
+:025A2200000082
+:025A2300000081
+:025A2400000080
+:025A250000007F
+:025A260000007E
+:025A270000007D
+:025A280000007C
+:025A290000007B
+:025A2A0000007A
+:025A2B00000079
+:025A2C00000078
+:025A2D00000077
+:025A2E00000076
+:025A2F00000075
+:025A3000000074
+:025A3100000073
+:025A3200000072
+:025A3300000071
+:025A3400000070
+:025A350000006F
+:025A360000006E
+:025A370000006D
+:025A380000006C
+:025A390000006B
+:025A3A0000006A
+:025A3B00000069
+:025A3C00000068
+:025A3D00000067
+:025A3E00000066
+:025A3F00000065
+:025A4000000064
+:025A4100000063
+:025A4200000062
+:025A4300000061
+:025A4400000060
+:025A450000005F
+:025A460000005E
+:025A470000005D
+:025A480000005C
+:025A490000005B
+:025A4A0000005A
+:025A4B00000059
+:025A4C00000058
+:025A4D00000057
+:025A4E00000056
+:025A4F00000055
+:025A5000000054
+:025A5100000053
+:025A5200000052
+:025A5300000051
+:025A5400000050
+:025A550000004F
+:025A560000004E
+:025A570000004D
+:025A580000004C
+:025A590000004B
+:025A5A0000004A
+:025A5B00000049
+:025A5C00000048
+:025A5D00000047
+:025A5E00000046
+:025A5F00000045
+:025A6000000044
+:025A6100000043
+:025A6200000042
+:025A6300000041
+:025A6400000040
+:025A650000003F
+:025A660000003E
+:025A670000003D
+:025A680000003C
+:025A690000003B
+:025A6A0000003A
+:025A6B00000039
+:025A6C00000038
+:025A6D00000037
+:025A6E00000036
+:025A6F00000035
+:025A7000000034
+:025A7100000033
+:025A7200000032
+:025A7300000031
+:025A7400000030
+:025A750000002F
+:025A760000002E
+:025A770000002D
+:025A780000002C
+:025A790000002B
+:025A7A0000002A
+:025A7B00000029
+:025A7C00000028
+:025A7D00000027
+:025A7E00000026
+:025A7F00000025
+:025A8000000024
+:025A8100000023
+:025A8200000022
+:025A8300000021
+:025A8400000020
+:025A850000001F
+:025A860000001E
+:025A870000001D
+:025A880000001C
+:025A890000001B
+:025A8A0000001A
+:025A8B00000019
+:025A8C00000018
+:025A8D00000017
+:025A8E00000016
+:025A8F00000015
+:025A9000000014
+:025A9100000013
+:025A9200000012
+:025A9300000011
+:025A9400000010
+:025A950000000F
+:025A960000000E
+:025A970000000D
+:025A980000000C
+:025A990000000B
+:025A9A0000000A
+:025A9B00000009
+:025A9C00000008
+:025A9D00000007
+:025A9E00000006
+:025A9F00000005
+:025AA000000004
+:025AA100000003
+:025AA200000002
+:025AA300000001
+:025AA400000000
+:025AA5000000FF
+:025AA6000000FE
+:025AA7000000FD
+:025AA8000000FC
+:025AA9000000FB
+:025AAA000000FA
+:025AAB000000F9
+:025AAC000000F8
+:025AAD000000F7
+:025AAE000000F6
+:025AAF000000F5
+:025AB0000000F4
+:025AB1000000F3
+:025AB2000000F2
+:025AB3000000F1
+:025AB4000000F0
+:025AB5000000EF
+:025AB6000000EE
+:025AB7000000ED
+:025AB8000000EC
+:025AB9000000EB
+:025ABA000000EA
+:025ABB000000E9
+:025ABC000000E8
+:025ABD000000E7
+:025ABE000000E6
+:025ABF000000E5
+:025AC0000000E4
+:025AC1000000E3
+:025AC2000000E2
+:025AC3000000E1
+:025AC4000000E0
+:025AC5000000DF
+:025AC6000000DE
+:025AC7000000DD
+:025AC8000000DC
+:025AC9000000DB
+:025ACA000000DA
+:025ACB000000D9
+:025ACC000000D8
+:025ACD000000D7
+:025ACE000000D6
+:025ACF000000D5
+:025AD0000000D4
+:025AD1000000D3
+:025AD2000000D2
+:025AD3000000D1
+:025AD4000000D0
+:025AD5000000CF
+:025AD6000000CE
+:025AD7000000CD
+:025AD8000000CC
+:025AD9000000CB
+:025ADA000000CA
+:025ADB000000C9
+:025ADC000000C8
+:025ADD000000C7
+:025ADE000000C6
+:025ADF000000C5
+:025AE0000000C4
+:025AE1000000C3
+:025AE2000000C2
+:025AE3000000C1
+:025AE4000000C0
+:025AE5000000BF
+:025AE6000000BE
+:025AE7000000BD
+:025AE8000000BC
+:025AE9000000BB
+:025AEA000000BA
+:025AEB000000B9
+:025AEC000000B8
+:025AED000000B7
+:025AEE000000B6
+:025AEF000000B5
+:025AF0000000B4
+:025AF1000000B3
+:025AF2000000B2
+:025AF3000000B1
+:025AF4000000B0
+:025AF5000000AF
+:025AF6000000AE
+:025AF7000000AD
+:025AF8000000AC
+:025AF9000000AB
+:025AFA000000AA
+:025AFB000000A9
+:025AFC000000A8
+:025AFD000000A7
+:025AFE000000A6
+:025AFF000000A5
+:025B00000000A3
+:025B01000000A2
+:025B02000000A1
+:025B03000000A0
+:025B040000009F
+:025B050000009E
+:025B060000009D
+:025B070000009C
+:025B080000009B
+:025B090000009A
+:025B0A00000099
+:025B0B00000098
+:025B0C00000097
+:025B0D00000096
+:025B0E00000095
+:025B0F00000094
+:025B1000000093
+:025B1100000092
+:025B1200000091
+:025B1300000090
+:025B140000008F
+:025B150000008E
+:025B160000008D
+:025B170000008C
+:025B180000008B
+:025B190000008A
+:025B1A00000089
+:025B1B00000088
+:025B1C00000087
+:025B1D00000086
+:025B1E00000085
+:025B1F00000084
+:025B2000000083
+:025B2100000082
+:025B2200000081
+:025B2300000080
+:025B240000007F
+:025B250000007E
+:025B260000007D
+:025B270000007C
+:025B280000007B
+:025B290000007A
+:025B2A00000079
+:025B2B00000078
+:025B2C00000077
+:025B2D00000076
+:025B2E00000075
+:025B2F00000074
+:025B3000000073
+:025B3100000072
+:025B3200000071
+:025B3300000070
+:025B340000006F
+:025B350000006E
+:025B360000006D
+:025B370000006C
+:025B380000006B
+:025B390000006A
+:025B3A00000069
+:025B3B00000068
+:025B3C00000067
+:025B3D00000066
+:025B3E00000065
+:025B3F00000064
+:025B4000000063
+:025B4100000062
+:025B4200000061
+:025B4300000060
+:025B440000005F
+:025B450000005E
+:025B460000005D
+:025B470000005C
+:025B480000005B
+:025B490000005A
+:025B4A00000059
+:025B4B00000058
+:025B4C00000057
+:025B4D00000056
+:025B4E00000055
+:025B4F00000054
+:025B5000000053
+:025B5100000052
+:025B5200000051
+:025B5300000050
+:025B540000004F
+:025B550000004E
+:025B560000004D
+:025B570000004C
+:025B580000004B
+:025B590000004A
+:025B5A00000049
+:025B5B00000048
+:025B5C00000047
+:025B5D00000046
+:025B5E00000045
+:025B5F00000044
+:025B6000000043
+:025B6100000042
+:025B6200000041
+:025B6300000040
+:025B640000003F
+:025B650000003E
+:025B660000003D
+:025B670000003C
+:025B680000003B
+:025B690000003A
+:025B6A00000039
+:025B6B00000038
+:025B6C00000037
+:025B6D00000036
+:025B6E00000035
+:025B6F00000034
+:025B7000000033
+:025B7100000032
+:025B7200000031
+:025B7300000030
+:025B740000002F
+:025B750000002E
+:025B760000002D
+:025B770000002C
+:025B780000002B
+:025B790000002A
+:025B7A00000029
+:025B7B00000028
+:025B7C00000027
+:025B7D00000026
+:025B7E00000025
+:025B7F00000024
+:025B8000000023
+:025B8100000022
+:025B8200000021
+:025B8300000020
+:025B840000001F
+:025B850000001E
+:025B860000001D
+:025B870000001C
+:025B880000001B
+:025B890000001A
+:025B8A00000019
+:025B8B00000018
+:025B8C00000017
+:025B8D00000016
+:025B8E00000015
+:025B8F00000014
+:025B9000000013
+:025B9100000012
+:025B9200000011
+:025B9300000010
+:025B940000000F
+:025B950000000E
+:025B960000000D
+:025B970000000C
+:025B980000000B
+:025B990000000A
+:025B9A00000009
+:025B9B00000008
+:025B9C00000007
+:025B9D00000006
+:025B9E00000005
+:025B9F00000004
+:025BA000000003
+:025BA100000002
+:025BA200000001
+:025BA300000000
+:025BA4000000FF
+:025BA5000000FE
+:025BA6000000FD
+:025BA7000000FC
+:025BA8000000FB
+:025BA9000000FA
+:025BAA000000F9
+:025BAB000000F8
+:025BAC000000F7
+:025BAD000000F6
+:025BAE000000F5
+:025BAF000000F4
+:025BB0000000F3
+:025BB1000000F2
+:025BB2000000F1
+:025BB3000000F0
+:025BB4000000EF
+:025BB5000000EE
+:025BB6000000ED
+:025BB7000000EC
+:025BB8000000EB
+:025BB9000000EA
+:025BBA000000E9
+:025BBB000000E8
+:025BBC000000E7
+:025BBD000000E6
+:025BBE000000E5
+:025BBF000000E4
+:025BC0000000E3
+:025BC1000000E2
+:025BC2000000E1
+:025BC3000000E0
+:025BC4000000DF
+:025BC5000000DE
+:025BC6000000DD
+:025BC7000000DC
+:025BC8000000DB
+:025BC9000000DA
+:025BCA000000D9
+:025BCB000000D8
+:025BCC000000D7
+:025BCD000000D6
+:025BCE000000D5
+:025BCF000000D4
+:025BD0000000D3
+:025BD1000000D2
+:025BD2000000D1
+:025BD3000000D0
+:025BD4000000CF
+:025BD5000000CE
+:025BD6000000CD
+:025BD7000000CC
+:025BD8000000CB
+:025BD9000000CA
+:025BDA000000C9
+:025BDB000000C8
+:025BDC000000C7
+:025BDD000000C6
+:025BDE000000C5
+:025BDF000000C4
+:025BE0000000C3
+:025BE1000000C2
+:025BE2000000C1
+:025BE3000000C0
+:025BE4000000BF
+:025BE5000000BE
+:025BE6000000BD
+:025BE7000000BC
+:025BE8000000BB
+:025BE9000000BA
+:025BEA000000B9
+:025BEB000000B8
+:025BEC000000B7
+:025BED000000B6
+:025BEE000000B5
+:025BEF000000B4
+:025BF0000000B3
+:025BF1000000B2
+:025BF2000000B1
+:025BF3000000B0
+:025BF4000000AF
+:025BF5000000AE
+:025BF6000000AD
+:025BF7000000AC
+:025BF8000000AB
+:025BF9000000AA
+:025BFA000000A9
+:025BFB000000A8
+:025BFC000000A7
+:025BFD000000A6
+:025BFE000000A5
+:025BFF000000A4
+:025C00000000A2
+:025C01000000A1
+:025C02000000A0
+:025C030000009F
+:025C040000009E
+:025C050000009D
+:025C060000009C
+:025C070000009B
+:025C080000009A
+:025C0900000099
+:025C0A00000098
+:025C0B00000097
+:025C0C00000096
+:025C0D00000095
+:025C0E00000094
+:025C0F00000093
+:025C1000000092
+:025C1100000091
+:025C1200000090
+:025C130000008F
+:025C140000008E
+:025C150000008D
+:025C160000008C
+:025C170000008B
+:025C180000008A
+:025C1900000089
+:025C1A00000088
+:025C1B00000087
+:025C1C00000086
+:025C1D00000085
+:025C1E00000084
+:025C1F00000083
+:025C2000000082
+:025C2100000081
+:025C2200000080
+:025C230000007F
+:025C240000007E
+:025C250000007D
+:025C260000007C
+:025C270000007B
+:025C280000007A
+:025C2900000079
+:025C2A00000078
+:025C2B00000077
+:025C2C00000076
+:025C2D00000075
+:025C2E00000074
+:025C2F00000073
+:025C3000000072
+:025C3100000071
+:025C3200000070
+:025C330000006F
+:025C340000006E
+:025C350000006D
+:025C360000006C
+:025C370000006B
+:025C380000006A
+:025C3900000069
+:025C3A00000068
+:025C3B00000067
+:025C3C00000066
+:025C3D00000065
+:025C3E00000064
+:025C3F00000063
+:025C4000000062
+:025C4100000061
+:025C4200000060
+:025C430000005F
+:025C440000005E
+:025C450000005D
+:025C460000005C
+:025C470000005B
+:025C480000005A
+:025C4900000059
+:025C4A00000058
+:025C4B00000057
+:025C4C00000056
+:025C4D00000055
+:025C4E00000054
+:025C4F00000053
+:025C5000000052
+:025C5100000051
+:025C5200000050
+:025C530000004F
+:025C540000004E
+:025C550000004D
+:025C560000004C
+:025C570000004B
+:025C580000004A
+:025C5900000049
+:025C5A00000048
+:025C5B00000047
+:025C5C00000046
+:025C5D00000045
+:025C5E00000044
+:025C5F00000043
+:025C6000000042
+:025C6100000041
+:025C6200000040
+:025C630000003F
+:025C640000003E
+:025C650000003D
+:025C660000003C
+:025C670000003B
+:025C680000003A
+:025C6900000039
+:025C6A00000038
+:025C6B00000037
+:025C6C00000036
+:025C6D00000035
+:025C6E00000034
+:025C6F00000033
+:025C7000000032
+:025C7100000031
+:025C7200000030
+:025C730000002F
+:025C740000002E
+:025C750000002D
+:025C760000002C
+:025C770000002B
+:025C780000002A
+:025C7900000029
+:025C7A00000028
+:025C7B00000027
+:025C7C00000026
+:025C7D00000025
+:025C7E00000024
+:025C7F00000023
+:025C8000000022
+:025C8100000021
+:025C8200000020
+:025C830000001F
+:025C840000001E
+:025C850000001D
+:025C860000001C
+:025C870000001B
+:025C880000001A
+:025C8900000019
+:025C8A00000018
+:025C8B00000017
+:025C8C00000016
+:025C8D00000015
+:025C8E00000014
+:025C8F00000013
+:025C9000000012
+:025C9100000011
+:025C9200000010
+:025C930000000F
+:025C940000000E
+:025C950000000D
+:025C960000000C
+:025C970000000B
+:025C980000000A
+:025C9900000009
+:025C9A00000008
+:025C9B00000007
+:025C9C00000006
+:025C9D00000005
+:025C9E00000004
+:025C9F00000003
+:025CA000000002
+:025CA100000001
+:025CA200000000
+:025CA3000000FF
+:025CA4000000FE
+:025CA5000000FD
+:025CA6000000FC
+:025CA7000000FB
+:025CA8000000FA
+:025CA9000000F9
+:025CAA000000F8
+:025CAB000000F7
+:025CAC000000F6
+:025CAD000000F5
+:025CAE000000F4
+:025CAF000000F3
+:025CB0000000F2
+:025CB1000000F1
+:025CB2000000F0
+:025CB3000000EF
+:025CB4000000EE
+:025CB5000000ED
+:025CB6000000EC
+:025CB7000000EB
+:025CB8000000EA
+:025CB9000000E9
+:025CBA000000E8
+:025CBB000000E7
+:025CBC000000E6
+:025CBD000000E5
+:025CBE000000E4
+:025CBF000000E3
+:025CC0000000E2
+:025CC1000000E1
+:025CC2000000E0
+:025CC3000000DF
+:025CC4000000DE
+:025CC5000000DD
+:025CC6000000DC
+:025CC7000000DB
+:025CC8000000DA
+:025CC9000000D9
+:025CCA000000D8
+:025CCB000000D7
+:025CCC000000D6
+:025CCD000000D5
+:025CCE000000D4
+:025CCF000000D3
+:025CD0000000D2
+:025CD1000000D1
+:025CD2000000D0
+:025CD3000000CF
+:025CD4000000CE
+:025CD5000000CD
+:025CD6000000CC
+:025CD7000000CB
+:025CD8000000CA
+:025CD9000000C9
+:025CDA000000C8
+:025CDB000000C7
+:025CDC000000C6
+:025CDD000000C5
+:025CDE000000C4
+:025CDF000000C3
+:025CE0000000C2
+:025CE1000000C1
+:025CE2000000C0
+:025CE3000000BF
+:025CE4000000BE
+:025CE5000000BD
+:025CE6000000BC
+:025CE7000000BB
+:025CE8000000BA
+:025CE9000000B9
+:025CEA000000B8
+:025CEB000000B7
+:025CEC000000B6
+:025CED000000B5
+:025CEE000000B4
+:025CEF000000B3
+:025CF0000000B2
+:025CF1000000B1
+:025CF2000000B0
+:025CF3000000AF
+:025CF4000000AE
+:025CF5000000AD
+:025CF6000000AC
+:025CF7000000AB
+:025CF8000000AA
+:025CF9000000A9
+:025CFA000000A8
+:025CFB000000A7
+:025CFC000000A6
+:025CFD000000A5
+:025CFE000000A4
+:025CFF000000A3
+:025D00000000A1
+:025D01000000A0
+:025D020000009F
+:025D030000009E
+:025D040000009D
+:025D050000009C
+:025D060000009B
+:025D070000009A
+:025D0800000099
+:025D0900000098
+:025D0A00000097
+:025D0B00000096
+:025D0C00000095
+:025D0D00000094
+:025D0E00000093
+:025D0F00000092
+:025D1000000091
+:025D1100000090
+:025D120000008F
+:025D130000008E
+:025D140000008D
+:025D150000008C
+:025D160000008B
+:025D170000008A
+:025D1800000089
+:025D1900000088
+:025D1A00000087
+:025D1B00000086
+:025D1C00000085
+:025D1D00000084
+:025D1E00000083
+:025D1F00000082
+:025D2000000081
+:025D2100000080
+:025D220000007F
+:025D230000007E
+:025D240000007D
+:025D250000007C
+:025D260000007B
+:025D270000007A
+:025D2800000079
+:025D2900000078
+:025D2A00000077
+:025D2B00000076
+:025D2C00000075
+:025D2D00000074
+:025D2E00000073
+:025D2F00000072
+:025D3000000071
+:025D3100000070
+:025D320000006F
+:025D330000006E
+:025D340000006D
+:025D350000006C
+:025D360000006B
+:025D370000006A
+:025D3800000069
+:025D3900000068
+:025D3A00000067
+:025D3B00000066
+:025D3C00000065
+:025D3D00000064
+:025D3E00000063
+:025D3F00000062
+:025D4000000061
+:025D4100000060
+:025D420000005F
+:025D430000005E
+:025D440000005D
+:025D450000005C
+:025D460000005B
+:025D470000005A
+:025D4800000059
+:025D4900000058
+:025D4A00000057
+:025D4B00000056
+:025D4C00000055
+:025D4D00000054
+:025D4E00000053
+:025D4F00000052
+:025D5000000051
+:025D5100000050
+:025D520000004F
+:025D530000004E
+:025D540000004D
+:025D550000004C
+:025D560000004B
+:025D570000004A
+:025D5800000049
+:025D5900000048
+:025D5A00000047
+:025D5B00000046
+:025D5C00000045
+:025D5D00000044
+:025D5E00000043
+:025D5F00000042
+:025D6000000041
+:025D6100000040
+:025D620000003F
+:025D630000003E
+:025D640000003D
+:025D650000003C
+:025D660000003B
+:025D670000003A
+:025D6800000039
+:025D6900000038
+:025D6A00000037
+:025D6B00000036
+:025D6C00000035
+:025D6D00000034
+:025D6E00000033
+:025D6F00000032
+:025D7000000031
+:025D7100000030
+:025D720000002F
+:025D730000002E
+:025D740000002D
+:025D750000002C
+:025D760000002B
+:025D770000002A
+:025D7800000029
+:025D7900000028
+:025D7A00000027
+:025D7B00000026
+:025D7C00000025
+:025D7D00000024
+:025D7E00000023
+:025D7F00000022
+:025D8000000021
+:025D8100000020
+:025D820000001F
+:025D830000001E
+:025D840000001D
+:025D850000001C
+:025D860000001B
+:025D870000001A
+:025D8800000019
+:025D8900000018
+:025D8A00000017
+:025D8B00000016
+:025D8C00000015
+:025D8D00000014
+:025D8E00000013
+:025D8F00000012
+:025D9000000011
+:025D9100000010
+:025D920000000F
+:025D930000000E
+:025D940000000D
+:025D950000000C
+:025D960000000B
+:025D970000000A
+:025D9800000009
+:025D9900000008
+:025D9A00000007
+:025D9B00000006
+:025D9C00000005
+:025D9D00000004
+:025D9E00000003
+:025D9F00000002
+:025DA000000001
+:025DA100000000
+:025DA2000000FF
+:025DA3000000FE
+:025DA4000000FD
+:025DA5000000FC
+:025DA6000000FB
+:025DA7000000FA
+:025DA8000000F9
+:025DA9000000F8
+:025DAA000000F7
+:025DAB000000F6
+:025DAC000000F5
+:025DAD000000F4
+:025DAE000000F3
+:025DAF000000F2
+:025DB0000000F1
+:025DB1000000F0
+:025DB2000000EF
+:025DB3000000EE
+:025DB4000000ED
+:025DB5000000EC
+:025DB6000000EB
+:025DB7000000EA
+:025DB8000000E9
+:025DB9000000E8
+:025DBA000000E7
+:025DBB000000E6
+:025DBC000000E5
+:025DBD000000E4
+:025DBE000000E3
+:025DBF000000E2
+:025DC0000000E1
+:025DC1000000E0
+:025DC2000000DF
+:025DC3000000DE
+:025DC4000000DD
+:025DC5000000DC
+:025DC6000000DB
+:025DC7000000DA
+:025DC8000000D9
+:025DC9000000D8
+:025DCA000000D7
+:025DCB000000D6
+:025DCC000000D5
+:025DCD000000D4
+:025DCE000000D3
+:025DCF000000D2
+:025DD0000000D1
+:025DD1000000D0
+:025DD2000000CF
+:025DD3000000CE
+:025DD4000000CD
+:025DD5000000CC
+:025DD6000000CB
+:025DD7000000CA
+:025DD8000000C9
+:025DD9000000C8
+:025DDA000000C7
+:025DDB000000C6
+:025DDC000000C5
+:025DDD000000C4
+:025DDE000000C3
+:025DDF000000C2
+:025DE0000000C1
+:025DE1000000C0
+:025DE2000000BF
+:025DE3000000BE
+:025DE4000000BD
+:025DE5000000BC
+:025DE6000000BB
+:025DE7000000BA
+:025DE8000000B9
+:025DE9000000B8
+:025DEA000000B7
+:025DEB000000B6
+:025DEC000000B5
+:025DED000000B4
+:025DEE000000B3
+:025DEF000000B2
+:025DF0000000B1
+:025DF1000000B0
+:025DF2000000AF
+:025DF3000000AE
+:025DF4000000AD
+:025DF5000000AC
+:025DF6000000AB
+:025DF7000000AA
+:025DF8000000A9
+:025DF9000000A8
+:025DFA000000A7
+:025DFB000000A6
+:025DFC000000A5
+:025DFD000000A4
+:025DFE000000A3
+:025DFF000000A2
+:025E00000000A0
+:025E010000009F
+:025E020000009E
+:025E030000009D
+:025E040000009C
+:025E050000009B
+:025E060000009A
+:025E0700000099
+:025E0800000098
+:025E0900000097
+:025E0A00000096
+:025E0B00000095
+:025E0C00000094
+:025E0D00000093
+:025E0E00000092
+:025E0F00000091
+:025E1000000090
+:025E110000008F
+:025E120000008E
+:025E130000008D
+:025E140000008C
+:025E150000008B
+:025E160000008A
+:025E1700000089
+:025E1800000088
+:025E1900000087
+:025E1A00000086
+:025E1B00000085
+:025E1C00000084
+:025E1D00000083
+:025E1E00000082
+:025E1F00000081
+:025E2000000080
+:025E210000007F
+:025E220000007E
+:025E230000007D
+:025E240000007C
+:025E250000007B
+:025E260000007A
+:025E2700000079
+:025E2800000078
+:025E2900000077
+:025E2A00000076
+:025E2B00000075
+:025E2C00000074
+:025E2D00000073
+:025E2E00000072
+:025E2F00000071
+:025E3000000070
+:025E310000006F
+:025E320000006E
+:025E330000006D
+:025E340000006C
+:025E350000006B
+:025E360000006A
+:025E3700000069
+:025E3800000068
+:025E3900000067
+:025E3A00000066
+:025E3B00000065
+:025E3C00000064
+:025E3D00000063
+:025E3E00000062
+:025E3F00000061
+:025E4000000060
+:025E410000005F
+:025E420000005E
+:025E430000005D
+:025E440000005C
+:025E450000005B
+:025E460000005A
+:025E4700000059
+:025E4800000058
+:025E4900000057
+:025E4A00000056
+:025E4B00000055
+:025E4C00000054
+:025E4D00000053
+:025E4E00000052
+:025E4F00000051
+:025E5000000050
+:025E510000004F
+:025E520000004E
+:025E530000004D
+:025E540000004C
+:025E550000004B
+:025E560000004A
+:025E5700000049
+:025E5800000048
+:025E5900000047
+:025E5A00000046
+:025E5B00000045
+:025E5C00000044
+:025E5D00000043
+:025E5E00000042
+:025E5F00000041
+:025E6000000040
+:025E610000003F
+:025E620000003E
+:025E630000003D
+:025E640000003C
+:025E650000003B
+:025E660000003A
+:025E6700000039
+:025E6800000038
+:025E6900000037
+:025E6A00000036
+:025E6B00000035
+:025E6C00000034
+:025E6D00000033
+:025E6E00000032
+:025E6F00000031
+:025E7000000030
+:025E710000002F
+:025E720000002E
+:025E730000002D
+:025E740000002C
+:025E750000002B
+:025E760000002A
+:025E7700000029
+:025E7800000028
+:025E7900000027
+:025E7A00000026
+:025E7B00000025
+:025E7C00000024
+:025E7D00000023
+:025E7E00000022
+:025E7F00000021
+:025E8000000020
+:025E810000001F
+:025E820000001E
+:025E830000001D
+:025E840000001C
+:025E850000001B
+:025E860000001A
+:025E8700000019
+:025E8800000018
+:025E8900000017
+:025E8A00000016
+:025E8B00000015
+:025E8C00000014
+:025E8D00000013
+:025E8E00000012
+:025E8F00000011
+:025E9000000010
+:025E910000000F
+:025E920000000E
+:025E930000000D
+:025E940000000C
+:025E950000000B
+:025E960000000A
+:025E9700000009
+:025E9800000008
+:025E9900000007
+:025E9A00000006
+:025E9B00000005
+:025E9C00000004
+:025E9D00000003
+:025E9E00000002
+:025E9F00000001
+:025EA000000000
+:025EA1000000FF
+:025EA2000000FE
+:025EA3000000FD
+:025EA4000000FC
+:025EA5000000FB
+:025EA6000000FA
+:025EA7000000F9
+:025EA8000000F8
+:025EA9000000F7
+:025EAA000000F6
+:025EAB000000F5
+:025EAC000000F4
+:025EAD000000F3
+:025EAE000000F2
+:025EAF000000F1
+:025EB0000000F0
+:025EB1000000EF
+:025EB2000000EE
+:025EB3000000ED
+:025EB4000000EC
+:025EB5000000EB
+:025EB6000000EA
+:025EB7000000E9
+:025EB8000000E8
+:025EB9000000E7
+:025EBA000000E6
+:025EBB000000E5
+:025EBC000000E4
+:025EBD000000E3
+:025EBE000000E2
+:025EBF000000E1
+:025EC0000000E0
+:025EC1000000DF
+:025EC2000000DE
+:025EC3000000DD
+:025EC4000000DC
+:025EC5000000DB
+:025EC6000000DA
+:025EC7000000D9
+:025EC8000000D8
+:025EC9000000D7
+:025ECA000000D6
+:025ECB000000D5
+:025ECC000000D4
+:025ECD000000D3
+:025ECE000000D2
+:025ECF000000D1
+:025ED0000000D0
+:025ED1000000CF
+:025ED2000000CE
+:025ED3000000CD
+:025ED4000000CC
+:025ED5000000CB
+:025ED6000000CA
+:025ED7000000C9
+:025ED8000000C8
+:025ED9000000C7
+:025EDA000000C6
+:025EDB000000C5
+:025EDC000000C4
+:025EDD000000C3
+:025EDE000000C2
+:025EDF000000C1
+:025EE0000000C0
+:025EE1000000BF
+:025EE2000000BE
+:025EE3000000BD
+:025EE4000000BC
+:025EE5000000BB
+:025EE6000000BA
+:025EE7000000B9
+:025EE8000000B8
+:025EE9000000B7
+:025EEA000000B6
+:025EEB000000B5
+:025EEC000000B4
+:025EED000000B3
+:025EEE000000B2
+:025EEF000000B1
+:025EF0000000B0
+:025EF1000000AF
+:025EF2000000AE
+:025EF3000000AD
+:025EF4000000AC
+:025EF5000000AB
+:025EF6000000AA
+:025EF7000000A9
+:025EF8000000A8
+:025EF9000000A7
+:025EFA000000A6
+:025EFB000000A5
+:025EFC000000A4
+:025EFD000000A3
+:025EFE000000A2
+:025EFF000000A1
+:025F000000009F
+:025F010000009E
+:025F020000009D
+:025F030000009C
+:025F040000009B
+:025F050000009A
+:025F0600000099
+:025F0700000098
+:025F0800000097
+:025F0900000096
+:025F0A00000095
+:025F0B00000094
+:025F0C00000093
+:025F0D00000092
+:025F0E00000091
+:025F0F00000090
+:025F100000008F
+:025F110000008E
+:025F120000008D
+:025F130000008C
+:025F140000008B
+:025F150000008A
+:025F1600000089
+:025F1700000088
+:025F1800000087
+:025F1900000086
+:025F1A00000085
+:025F1B00000084
+:025F1C00000083
+:025F1D00000082
+:025F1E00000081
+:025F1F00000080
+:025F200000007F
+:025F210000007E
+:025F220000007D
+:025F230000007C
+:025F240000007B
+:025F250000007A
+:025F2600000079
+:025F2700000078
+:025F2800000077
+:025F2900000076
+:025F2A00000075
+:025F2B00000074
+:025F2C00000073
+:025F2D00000072
+:025F2E00000071
+:025F2F00000070
+:025F300000006F
+:025F310000006E
+:025F320000006D
+:025F330000006C
+:025F340000006B
+:025F350000006A
+:025F3600000069
+:025F3700000068
+:025F3800000067
+:025F3900000066
+:025F3A00000065
+:025F3B00000064
+:025F3C00000063
+:025F3D00000062
+:025F3E00000061
+:025F3F00000060
+:025F400000005F
+:025F410000005E
+:025F420000005D
+:025F430000005C
+:025F440000005B
+:025F450000005A
+:025F4600000059
+:025F4700000058
+:025F4800000057
+:025F4900000056
+:025F4A00000055
+:025F4B00000054
+:025F4C00000053
+:025F4D00000052
+:025F4E00000051
+:025F4F00000050
+:025F500000004F
+:025F510000004E
+:025F520000004D
+:025F530000004C
+:025F540000004B
+:025F550000004A
+:025F5600000049
+:025F5700000048
+:025F5800000047
+:025F5900000046
+:025F5A00000045
+:025F5B00000044
+:025F5C00000043
+:025F5D00000042
+:025F5E00000041
+:025F5F00000040
+:025F600000003F
+:025F610000003E
+:025F620000003D
+:025F630000003C
+:025F640000003B
+:025F650000003A
+:025F6600000039
+:025F6700000038
+:025F6800000037
+:025F6900000036
+:025F6A00000035
+:025F6B00000034
+:025F6C00000033
+:025F6D00000032
+:025F6E00000031
+:025F6F00000030
+:025F700000002F
+:025F710000002E
+:025F720000002D
+:025F730000002C
+:025F740000002B
+:025F750000002A
+:025F7600000029
+:025F7700000028
+:025F7800000027
+:025F7900000026
+:025F7A00000025
+:025F7B00000024
+:025F7C00000023
+:025F7D00000022
+:025F7E00000021
+:025F7F00000020
+:025F800000001F
+:025F810000001E
+:025F820000001D
+:025F830000001C
+:025F840000001B
+:025F850000001A
+:025F8600000019
+:025F8700000018
+:025F8800000017
+:025F8900000016
+:025F8A00000015
+:025F8B00000014
+:025F8C00000013
+:025F8D00000012
+:025F8E00000011
+:025F8F00000010
+:025F900000000F
+:025F910000000E
+:025F920000000D
+:025F930000000C
+:025F940000000B
+:025F950000000A
+:025F9600000009
+:025F9700000008
+:025F9800000007
+:025F9900000006
+:025F9A00000005
+:025F9B00000004
+:025F9C00000003
+:025F9D00000002
+:025F9E00000001
+:025F9F00000000
+:025FA0000000FF
+:025FA1000000FE
+:025FA2000000FD
+:025FA3000000FC
+:025FA4000000FB
+:025FA5000000FA
+:025FA6000000F9
+:025FA7000000F8
+:025FA8000000F7
+:025FA9000000F6
+:025FAA000000F5
+:025FAB000000F4
+:025FAC000000F3
+:025FAD000000F2
+:025FAE000000F1
+:025FAF000000F0
+:025FB0000000EF
+:025FB1000000EE
+:025FB2000000ED
+:025FB3000000EC
+:025FB4000000EB
+:025FB5000000EA
+:025FB6000000E9
+:025FB7000000E8
+:025FB8000000E7
+:025FB9000000E6
+:025FBA000000E5
+:025FBB000000E4
+:025FBC000000E3
+:025FBD000000E2
+:025FBE000000E1
+:025FBF000000E0
+:025FC0000000DF
+:025FC1000000DE
+:025FC2000000DD
+:025FC3000000DC
+:025FC4000000DB
+:025FC5000000DA
+:025FC6000000D9
+:025FC7000000D8
+:025FC8000000D7
+:025FC9000000D6
+:025FCA000000D5
+:025FCB000000D4
+:025FCC000000D3
+:025FCD000000D2
+:025FCE000000D1
+:025FCF000000D0
+:025FD0000000CF
+:025FD1000000CE
+:025FD2000000CD
+:025FD3000000CC
+:025FD4000000CB
+:025FD5000000CA
+:025FD6000000C9
+:025FD7000000C8
+:025FD8000000C7
+:025FD9000000C6
+:025FDA000000C5
+:025FDB000000C4
+:025FDC000000C3
+:025FDD000000C2
+:025FDE000000C1
+:025FDF000000C0
+:025FE0000000BF
+:025FE1000000BE
+:025FE2000000BD
+:025FE3000000BC
+:025FE4000000BB
+:025FE5000000BA
+:025FE6000000B9
+:025FE7000000B8
+:025FE8000000B7
+:025FE9000000B6
+:025FEA000000B5
+:025FEB000000B4
+:025FEC000000B3
+:025FED000000B2
+:025FEE000000B1
+:025FEF000000B0
+:025FF0000000AF
+:025FF1000000AE
+:025FF2000000AD
+:025FF3000000AC
+:025FF4000000AB
+:025FF5000000AA
+:025FF6000000A9
+:025FF7000000A8
+:025FF8000000A7
+:025FF9000000A6
+:025FFA000000A5
+:025FFB000000A4
+:025FFC000000A3
+:025FFD000000A2
+:025FFE000000A1
+:025FFF000000A0
+:0260000000009E
+:0260010000009D
+:0260020000009C
+:0260030000009B
+:0260040000009A
+:02600500000099
+:02600600000098
+:02600700000097
+:02600800000096
+:02600900000095
+:02600A00000094
+:02600B00000093
+:02600C00000092
+:02600D00000091
+:02600E00000090
+:02600F0000008F
+:0260100000008E
+:0260110000008D
+:0260120000008C
+:0260130000008B
+:0260140000008A
+:02601500000089
+:02601600000088
+:02601700000087
+:02601800000086
+:02601900000085
+:02601A00000084
+:02601B00000083
+:02601C00000082
+:02601D00000081
+:02601E00000080
+:02601F0000007F
+:0260200000007E
+:0260210000007D
+:0260220000007C
+:0260230000007B
+:0260240000007A
+:02602500000079
+:02602600000078
+:02602700000077
+:02602800000076
+:02602900000075
+:02602A00000074
+:02602B00000073
+:02602C00000072
+:02602D00000071
+:02602E00000070
+:02602F0000006F
+:0260300000006E
+:0260310000006D
+:0260320000006C
+:0260330000006B
+:0260340000006A
+:02603500000069
+:02603600000068
+:02603700000067
+:02603800000066
+:02603900000065
+:02603A00000064
+:02603B00000063
+:02603C00000062
+:02603D00000061
+:02603E00000060
+:02603F0000005F
+:0260400000005E
+:0260410000005D
+:0260420000005C
+:0260430000005B
+:0260440000005A
+:02604500000059
+:02604600000058
+:02604700000057
+:02604800000056
+:02604900000055
+:02604A00000054
+:02604B00000053
+:02604C00000052
+:02604D00000051
+:02604E00000050
+:02604F0000004F
+:0260500000004E
+:0260510000004D
+:0260520000004C
+:0260530000004B
+:0260540000004A
+:02605500000049
+:02605600000048
+:02605700000047
+:02605800000046
+:02605900000045
+:02605A00000044
+:02605B00000043
+:02605C00000042
+:02605D00000041
+:02605E00000040
+:02605F0000003F
+:0260600000003E
+:0260610000003D
+:0260620000003C
+:0260630000003B
+:0260640000003A
+:02606500000039
+:02606600000038
+:02606700000037
+:02606800000036
+:02606900000035
+:02606A00000034
+:02606B00000033
+:02606C00000032
+:02606D00000031
+:02606E00000030
+:02606F0000002F
+:0260700000002E
+:0260710000002D
+:0260720000002C
+:0260730000002B
+:0260740000002A
+:02607500000029
+:02607600000028
+:02607700000027
+:02607800000026
+:02607900000025
+:02607A00000024
+:02607B00000023
+:02607C00000022
+:02607D00000021
+:02607E00000020
+:02607F0000001F
+:0260800000001E
+:0260810000001D
+:0260820000001C
+:0260830000001B
+:0260840000001A
+:02608500000019
+:02608600000018
+:02608700000017
+:02608800000016
+:02608900000015
+:02608A00000014
+:02608B00000013
+:02608C00000012
+:02608D00000011
+:02608E00000010
+:02608F0000000F
+:0260900000000E
+:0260910000000D
+:0260920000000C
+:0260930000000B
+:0260940000000A
+:02609500000009
+:02609600000008
+:02609700000007
+:02609800000006
+:02609900000005
+:02609A00000004
+:02609B00000003
+:02609C00000002
+:02609D00000001
+:02609E00000000
+:02609F000000FF
+:0260A0000000FE
+:0260A1000000FD
+:0260A2000000FC
+:0260A3000000FB
+:0260A4000000FA
+:0260A5000000F9
+:0260A6000000F8
+:0260A7000000F7
+:0260A8000000F6
+:0260A9000000F5
+:0260AA000000F4
+:0260AB000000F3
+:0260AC000000F2
+:0260AD000000F1
+:0260AE000000F0
+:0260AF000000EF
+:0260B0000000EE
+:0260B1000000ED
+:0260B2000000EC
+:0260B3000000EB
+:0260B4000000EA
+:0260B5000000E9
+:0260B6000000E8
+:0260B7000000E7
+:0260B8000000E6
+:0260B9000000E5
+:0260BA000000E4
+:0260BB000000E3
+:0260BC000000E2
+:0260BD000000E1
+:0260BE000000E0
+:0260BF000000DF
+:0260C0000000DE
+:0260C1000000DD
+:0260C2000000DC
+:0260C3000000DB
+:0260C4000000DA
+:0260C5000000D9
+:0260C6000000D8
+:0260C7000000D7
+:0260C8000000D6
+:0260C9000000D5
+:0260CA000000D4
+:0260CB000000D3
+:0260CC000000D2
+:0260CD000000D1
+:0260CE000000D0
+:0260CF000000CF
+:0260D0000000CE
+:0260D1000000CD
+:0260D2000000CC
+:0260D3000000CB
+:0260D4000000CA
+:0260D5000000C9
+:0260D6000000C8
+:0260D7000000C7
+:0260D8000000C6
+:0260D9000000C5
+:0260DA000000C4
+:0260DB000000C3
+:0260DC000000C2
+:0260DD000000C1
+:0260DE000000C0
+:0260DF000000BF
+:0260E0000000BE
+:0260E1000000BD
+:0260E2000000BC
+:0260E3000000BB
+:0260E4000000BA
+:0260E5000000B9
+:0260E6000000B8
+:0260E7000000B7
+:0260E8000000B6
+:0260E9000000B5
+:0260EA000000B4
+:0260EB000000B3
+:0260EC000000B2
+:0260ED000000B1
+:0260EE000000B0
+:0260EF000000AF
+:0260F0000000AE
+:0260F1000000AD
+:0260F2000000AC
+:0260F3000000AB
+:0260F4000000AA
+:0260F5000000A9
+:0260F6000000A8
+:0260F7000000A7
+:0260F8000000A6
+:0260F9000000A5
+:0260FA000000A4
+:0260FB000000A3
+:0260FC000000A2
+:0260FD000000A1
+:0260FE000000A0
+:0260FF0000009F
+:0261000000009D
+:0261010000009C
+:0261020000009B
+:0261030000009A
+:02610400000099
+:02610500000098
+:02610600000097
+:02610700000096
+:02610800000095
+:02610900000094
+:02610A00000093
+:02610B00000092
+:02610C00000091
+:02610D00000090
+:02610E0000008F
+:02610F0000008E
+:0261100000008D
+:0261110000008C
+:0261120000008B
+:0261130000008A
+:02611400000089
+:02611500000088
+:02611600000087
+:02611700000086
+:02611800000085
+:02611900000084
+:02611A00000083
+:02611B00000082
+:02611C00000081
+:02611D00000080
+:02611E0000007F
+:02611F0000007E
+:0261200000007D
+:0261210000007C
+:0261220000007B
+:0261230000007A
+:02612400000079
+:02612500000078
+:02612600000077
+:02612700000076
+:02612800000075
+:02612900000074
+:02612A00000073
+:02612B00000072
+:02612C00000071
+:02612D00000070
+:02612E0000006F
+:02612F0000006E
+:0261300000006D
+:0261310000006C
+:0261320000006B
+:0261330000006A
+:02613400000069
+:02613500000068
+:02613600000067
+:02613700000066
+:02613800000065
+:02613900000064
+:02613A00000063
+:02613B00000062
+:02613C00000061
+:02613D00000060
+:02613E0000005F
+:02613F0000005E
+:0261400000005D
+:0261410000005C
+:0261420000005B
+:0261430000005A
+:02614400000059
+:02614500000058
+:02614600000057
+:02614700000056
+:02614800000055
+:02614900000054
+:02614A00000053
+:02614B00000052
+:02614C00000051
+:02614D00000050
+:02614E0000004F
+:02614F0000004E
+:0261500000004D
+:0261510000004C
+:0261520000004B
+:0261530000004A
+:02615400000049
+:02615500000048
+:02615600000047
+:02615700000046
+:02615800000045
+:02615900000044
+:02615A00000043
+:02615B00000042
+:02615C00000041
+:02615D00000040
+:02615E0000003F
+:02615F0000003E
+:0261600000003D
+:0261610000003C
+:0261620000003B
+:0261630000003A
+:02616400000039
+:02616500000038
+:02616600000037
+:02616700000036
+:02616800000035
+:02616900000034
+:02616A00000033
+:02616B00000032
+:02616C00000031
+:02616D00000030
+:02616E0000002F
+:02616F0000002E
+:0261700000002D
+:0261710000002C
+:0261720000002B
+:0261730000002A
+:02617400000029
+:02617500000028
+:02617600000027
+:02617700000026
+:02617800000025
+:02617900000024
+:02617A00000023
+:02617B00000022
+:02617C00000021
+:02617D00000020
+:02617E0000001F
+:02617F0000001E
+:0261800000001D
+:0261810000001C
+:0261820000001B
+:0261830000001A
+:02618400000019
+:02618500000018
+:02618600000017
+:02618700000016
+:02618800000015
+:02618900000014
+:02618A00000013
+:02618B00000012
+:02618C00000011
+:02618D00000010
+:02618E0000000F
+:02618F0000000E
+:0261900000000D
+:0261910000000C
+:0261920000000B
+:0261930000000A
+:02619400000009
+:02619500000008
+:02619600000007
+:02619700000006
+:02619800000005
+:02619900000004
+:02619A00000003
+:02619B00000002
+:02619C00000001
+:02619D00000000
+:02619E000000FF
+:02619F000000FE
+:0261A0000000FD
+:0261A1000000FC
+:0261A2000000FB
+:0261A3000000FA
+:0261A4000000F9
+:0261A5000000F8
+:0261A6000000F7
+:0261A7000000F6
+:0261A8000000F5
+:0261A9000000F4
+:0261AA000000F3
+:0261AB000000F2
+:0261AC000000F1
+:0261AD000000F0
+:0261AE000000EF
+:0261AF000000EE
+:0261B0000000ED
+:0261B1000000EC
+:0261B2000000EB
+:0261B3000000EA
+:0261B4000000E9
+:0261B5000000E8
+:0261B6000000E7
+:0261B7000000E6
+:0261B8000000E5
+:0261B9000000E4
+:0261BA000000E3
+:0261BB000000E2
+:0261BC000000E1
+:0261BD000000E0
+:0261BE000000DF
+:0261BF000000DE
+:0261C0000000DD
+:0261C1000000DC
+:0261C2000000DB
+:0261C3000000DA
+:0261C4000000D9
+:0261C5000000D8
+:0261C6000000D7
+:0261C7000000D6
+:0261C8000000D5
+:0261C9000000D4
+:0261CA000000D3
+:0261CB000000D2
+:0261CC000000D1
+:0261CD000000D0
+:0261CE000000CF
+:0261CF000000CE
+:0261D0000000CD
+:0261D1000000CC
+:0261D2000000CB
+:0261D3000000CA
+:0261D4000000C9
+:0261D5000000C8
+:0261D6000000C7
+:0261D7000000C6
+:0261D8000000C5
+:0261D9000000C4
+:0261DA000000C3
+:0261DB000000C2
+:0261DC000000C1
+:0261DD000000C0
+:0261DE000000BF
+:0261DF000000BE
+:0261E0000000BD
+:0261E1000000BC
+:0261E2000000BB
+:0261E3000000BA
+:0261E4000000B9
+:0261E5000000B8
+:0261E6000000B7
+:0261E7000000B6
+:0261E8000000B5
+:0261E9000000B4
+:0261EA000000B3
+:0261EB000000B2
+:0261EC000000B1
+:0261ED000000B0
+:0261EE000000AF
+:0261EF000000AE
+:0261F0000000AD
+:0261F1000000AC
+:0261F2000000AB
+:0261F3000000AA
+:0261F4000000A9
+:0261F5000000A8
+:0261F6000000A7
+:0261F7000000A6
+:0261F8000000A5
+:0261F9000000A4
+:0261FA000000A3
+:0261FB000000A2
+:0261FC000000A1
+:0261FD000000A0
+:0261FE0000009F
+:0261FF0000009E
+:0262000000009C
+:0262010000009B
+:0262020000009A
+:02620300000099
+:02620400000098
+:02620500000097
+:02620600000096
+:02620700000095
+:02620800000094
+:02620900000093
+:02620A00000092
+:02620B00000091
+:02620C00000090
+:02620D0000008F
+:02620E0000008E
+:02620F0000008D
+:0262100000008C
+:0262110000008B
+:0262120000008A
+:02621300000089
+:02621400000088
+:02621500000087
+:02621600000086
+:02621700000085
+:02621800000084
+:02621900000083
+:02621A00000082
+:02621B00000081
+:02621C00000080
+:02621D0000007F
+:02621E0000007E
+:02621F0000007D
+:0262200000007C
+:0262210000007B
+:0262220000007A
+:02622300000079
+:02622400000078
+:02622500000077
+:02622600000076
+:02622700000075
+:02622800000074
+:02622900000073
+:02622A00000072
+:02622B00000071
+:02622C00000070
+:02622D0000006F
+:02622E0000006E
+:02622F0000006D
+:0262300000006C
+:0262310000006B
+:0262320000006A
+:02623300000069
+:02623400000068
+:02623500000067
+:02623600000066
+:02623700000065
+:02623800000064
+:02623900000063
+:02623A00000062
+:02623B00000061
+:02623C00000060
+:02623D0000005F
+:02623E0000005E
+:02623F0000005D
+:0262400000005C
+:0262410000005B
+:0262420000005A
+:02624300000059
+:02624400000058
+:02624500000057
+:02624600000056
+:02624700000055
+:02624800000054
+:02624900000053
+:02624A00000052
+:02624B00000051
+:02624C00000050
+:02624D0000004F
+:02624E0000004E
+:02624F0000004D
+:0262500000004C
+:0262510000004B
+:0262520000004A
+:02625300000049
+:02625400000048
+:02625500000047
+:02625600000046
+:02625700000045
+:02625800000044
+:02625900000043
+:02625A00000042
+:02625B00000041
+:02625C00000040
+:02625D0000003F
+:02625E0000003E
+:02625F0000003D
+:0262600000003C
+:0262610000003B
+:0262620000003A
+:02626300000039
+:02626400000038
+:02626500000037
+:02626600000036
+:02626700000035
+:02626800000034
+:02626900000033
+:02626A00000032
+:02626B00000031
+:02626C00000030
+:02626D0000002F
+:02626E0000002E
+:02626F0000002D
+:0262700000002C
+:0262710000002B
+:0262720000002A
+:02627300000029
+:02627400000028
+:02627500000027
+:02627600000026
+:02627700000025
+:02627800000024
+:02627900000023
+:02627A00000022
+:02627B00000021
+:02627C00000020
+:02627D0000001F
+:02627E0000001E
+:02627F0000001D
+:0262800000001C
+:0262810000001B
+:0262820000001A
+:02628300000019
+:02628400000018
+:02628500000017
+:02628600000016
+:02628700000015
+:02628800000014
+:02628900000013
+:02628A00000012
+:02628B00000011
+:02628C00000010
+:02628D0000000F
+:02628E0000000E
+:02628F0000000D
+:0262900000000C
+:0262910000000B
+:0262920000000A
+:02629300000009
+:02629400000008
+:02629500000007
+:02629600000006
+:02629700000005
+:02629800000004
+:02629900000003
+:02629A00000002
+:02629B00000001
+:02629C00000000
+:02629D000000FF
+:02629E000000FE
+:02629F000000FD
+:0262A0000000FC
+:0262A1000000FB
+:0262A2000000FA
+:0262A3000000F9
+:0262A4000000F8
+:0262A5000000F7
+:0262A6000000F6
+:0262A7000000F5
+:0262A8000000F4
+:0262A9000000F3
+:0262AA000000F2
+:0262AB000000F1
+:0262AC000000F0
+:0262AD000000EF
+:0262AE000000EE
+:0262AF000000ED
+:0262B0000000EC
+:0262B1000000EB
+:0262B2000000EA
+:0262B3000000E9
+:0262B4000000E8
+:0262B5000000E7
+:0262B6000000E6
+:0262B7000000E5
+:0262B8000000E4
+:0262B9000000E3
+:0262BA000000E2
+:0262BB000000E1
+:0262BC000000E0
+:0262BD000000DF
+:0262BE000000DE
+:0262BF000000DD
+:0262C0000000DC
+:0262C1000000DB
+:0262C2000000DA
+:0262C3000000D9
+:0262C4000000D8
+:0262C5000000D7
+:0262C6000000D6
+:0262C7000000D5
+:0262C8000000D4
+:0262C9000000D3
+:0262CA000000D2
+:0262CB000000D1
+:0262CC000000D0
+:0262CD000000CF
+:0262CE000000CE
+:0262CF000000CD
+:0262D0000000CC
+:0262D1000000CB
+:0262D2000000CA
+:0262D3000000C9
+:0262D4000000C8
+:0262D5000000C7
+:0262D6000000C6
+:0262D7000000C5
+:0262D8000000C4
+:0262D9000000C3
+:0262DA000000C2
+:0262DB000000C1
+:0262DC000000C0
+:0262DD000000BF
+:0262DE000000BE
+:0262DF000000BD
+:0262E0000000BC
+:0262E1000000BB
+:0262E2000000BA
+:0262E3000000B9
+:0262E4000000B8
+:0262E5000000B7
+:0262E6000000B6
+:0262E7000000B5
+:0262E8000000B4
+:0262E9000000B3
+:0262EA000000B2
+:0262EB000000B1
+:0262EC000000B0
+:0262ED000000AF
+:0262EE000000AE
+:0262EF000000AD
+:0262F0000000AC
+:0262F1000000AB
+:0262F2000000AA
+:0262F3000000A9
+:0262F4000000A8
+:0262F5000000A7
+:0262F6000000A6
+:0262F7000000A5
+:0262F8000000A4
+:0262F9000000A3
+:0262FA000000A2
+:0262FB000000A1
+:0262FC000000A0
+:0262FD0000009F
+:0262FE0000009E
+:0262FF0000009D
+:0263000000009B
+:0263010000009A
+:02630200000099
+:02630300000098
+:02630400000097
+:02630500000096
+:02630600000095
+:02630700000094
+:02630800000093
+:02630900000092
+:02630A00000091
+:02630B00000090
+:02630C0000008F
+:02630D0000008E
+:02630E0000008D
+:02630F0000008C
+:0263100000008B
+:0263110000008A
+:02631200000089
+:02631300000088
+:02631400000087
+:02631500000086
+:02631600000085
+:02631700000084
+:02631800000083
+:02631900000082
+:02631A00000081
+:02631B00000080
+:02631C0000007F
+:02631D0000007E
+:02631E0000007D
+:02631F0000007C
+:0263200000007B
+:0263210000007A
+:02632200000079
+:02632300000078
+:02632400000077
+:02632500000076
+:02632600000075
+:02632700000074
+:02632800000073
+:02632900000072
+:02632A00000071
+:02632B00000070
+:02632C0000006F
+:02632D0000006E
+:02632E0000006D
+:02632F0000006C
+:0263300000006B
+:0263310000006A
+:02633200000069
+:02633300000068
+:02633400000067
+:02633500000066
+:02633600000065
+:02633700000064
+:02633800000063
+:02633900000062
+:02633A00000061
+:02633B00000060
+:02633C0000005F
+:02633D0000005E
+:02633E0000005D
+:02633F0000005C
+:0263400000005B
+:0263410000005A
+:02634200000059
+:02634300000058
+:02634400000057
+:02634500000056
+:02634600000055
+:02634700000054
+:02634800000053
+:02634900000052
+:02634A00000051
+:02634B00000050
+:02634C0000004F
+:02634D0000004E
+:02634E0000004D
+:02634F0000004C
+:0263500000004B
+:0263510000004A
+:02635200000049
+:02635300000048
+:02635400000047
+:02635500000046
+:02635600000045
+:02635700000044
+:02635800000043
+:02635900000042
+:02635A00000041
+:02635B00000040
+:02635C0000003F
+:02635D0000003E
+:02635E0000003D
+:02635F0000003C
+:0263600000003B
+:0263610000003A
+:02636200000039
+:02636300000038
+:02636400000037
+:02636500000036
+:02636600000035
+:02636700000034
+:02636800000033
+:02636900000032
+:02636A00000031
+:02636B00000030
+:02636C0000002F
+:02636D0000002E
+:02636E0000002D
+:02636F0000002C
+:0263700000002B
+:0263710000002A
+:02637200000029
+:02637300000028
+:02637400000027
+:02637500000026
+:02637600000025
+:02637700000024
+:02637800000023
+:02637900000022
+:02637A00000021
+:02637B00000020
+:02637C0000001F
+:02637D0000001E
+:02637E0000001D
+:02637F0000001C
+:0263800000001B
+:0263810000001A
+:02638200000019
+:02638300000018
+:02638400000017
+:02638500000016
+:02638600000015
+:02638700000014
+:02638800000013
+:02638900000012
+:02638A00000011
+:02638B00000010
+:02638C0000000F
+:02638D0000000E
+:02638E0000000D
+:02638F0000000C
+:0263900000000B
+:0263910000000A
+:02639200000009
+:02639300000008
+:02639400000007
+:02639500000006
+:02639600000005
+:02639700000004
+:02639800000003
+:02639900000002
+:02639A00000001
+:02639B00000000
+:02639C000000FF
+:02639D000000FE
+:02639E000000FD
+:02639F000000FC
+:0263A0000000FB
+:0263A1000000FA
+:0263A2000000F9
+:0263A3000000F8
+:0263A4000000F7
+:0263A5000000F6
+:0263A6000000F5
+:0263A7000000F4
+:0263A8000000F3
+:0263A9000000F2
+:0263AA000000F1
+:0263AB000000F0
+:0263AC000000EF
+:0263AD000000EE
+:0263AE000000ED
+:0263AF000000EC
+:0263B0000000EB
+:0263B1000000EA
+:0263B2000000E9
+:0263B3000000E8
+:0263B4000000E7
+:0263B5000000E6
+:0263B6000000E5
+:0263B7000000E4
+:0263B8000000E3
+:0263B9000000E2
+:0263BA000000E1
+:0263BB000000E0
+:0263BC000000DF
+:0263BD000000DE
+:0263BE000000DD
+:0263BF000000DC
+:0263C0000000DB
+:0263C1000000DA
+:0263C2000000D9
+:0263C3000000D8
+:0263C4000000D7
+:0263C5000000D6
+:0263C6000000D5
+:0263C7000000D4
+:0263C8000000D3
+:0263C9000000D2
+:0263CA000000D1
+:0263CB000000D0
+:0263CC000000CF
+:0263CD000000CE
+:0263CE000000CD
+:0263CF000000CC
+:0263D0000000CB
+:0263D1000000CA
+:0263D2000000C9
+:0263D3000000C8
+:0263D4000000C7
+:0263D5000000C6
+:0263D6000000C5
+:0263D7000000C4
+:0263D8000000C3
+:0263D9000000C2
+:0263DA000000C1
+:0263DB000000C0
+:0263DC000000BF
+:0263DD000000BE
+:0263DE000000BD
+:0263DF000000BC
+:0263E0000000BB
+:0263E1000000BA
+:0263E2000000B9
+:0263E3000000B8
+:0263E4000000B7
+:0263E5000000B6
+:0263E6000000B5
+:0263E7000000B4
+:0263E8000000B3
+:0263E9000000B2
+:0263EA000000B1
+:0263EB000000B0
+:0263EC000000AF
+:0263ED000000AE
+:0263EE000000AD
+:0263EF000000AC
+:0263F0000000AB
+:0263F1000000AA
+:0263F2000000A9
+:0263F3000000A8
+:0263F4000000A7
+:0263F5000000A6
+:0263F6000000A5
+:0263F7000000A4
+:0263F8000000A3
+:0263F9000000A2
+:0263FA000000A1
+:0263FB000000A0
+:0263FC0000009F
+:0263FD0000009E
+:0263FE0000009D
+:0263FF0000009C
+:0264000000009A
+:02640100000099
+:02640200000098
+:02640300000097
+:02640400000096
+:02640500000095
+:02640600000094
+:02640700000093
+:02640800000092
+:02640900000091
+:02640A00000090
+:02640B0000008F
+:02640C0000008E
+:02640D0000008D
+:02640E0000008C
+:02640F0000008B
+:0264100000008A
+:02641100000089
+:02641200000088
+:02641300000087
+:02641400000086
+:02641500000085
+:02641600000084
+:02641700000083
+:02641800000082
+:02641900000081
+:02641A00000080
+:02641B0000007F
+:02641C0000007E
+:02641D0000007D
+:02641E0000007C
+:02641F0000007B
+:0264200000007A
+:02642100000079
+:02642200000078
+:02642300000077
+:02642400000076
+:02642500000075
+:02642600000074
+:02642700000073
+:02642800000072
+:02642900000071
+:02642A00000070
+:02642B0000006F
+:02642C0000006E
+:02642D0000006D
+:02642E0000006C
+:02642F0000006B
+:0264300000006A
+:02643100000069
+:02643200000068
+:02643300000067
+:02643400000066
+:02643500000065
+:02643600000064
+:02643700000063
+:02643800000062
+:02643900000061
+:02643A00000060
+:02643B0000005F
+:02643C0000005E
+:02643D0000005D
+:02643E0000005C
+:02643F0000005B
+:0264400000005A
+:02644100000059
+:02644200000058
+:02644300000057
+:02644400000056
+:02644500000055
+:02644600000054
+:02644700000053
+:02644800000052
+:02644900000051
+:02644A00000050
+:02644B0000004F
+:02644C0000004E
+:02644D0000004D
+:02644E0000004C
+:02644F0000004B
+:0264500000004A
+:02645100000049
+:02645200000048
+:02645300000047
+:02645400000046
+:02645500000045
+:02645600000044
+:02645700000043
+:02645800000042
+:02645900000041
+:02645A00000040
+:02645B0000003F
+:02645C0000003E
+:02645D0000003D
+:02645E0000003C
+:02645F0000003B
+:0264600000003A
+:02646100000039
+:02646200000038
+:02646300000037
+:02646400000036
+:02646500000035
+:02646600000034
+:02646700000033
+:02646800000032
+:02646900000031
+:02646A00000030
+:02646B0000002F
+:02646C0000002E
+:02646D0000002D
+:02646E0000002C
+:02646F0000002B
+:0264700000002A
+:02647100000029
+:02647200000028
+:02647300000027
+:02647400000026
+:02647500000025
+:02647600000024
+:02647700000023
+:02647800000022
+:02647900000021
+:02647A00000020
+:02647B0000001F
+:02647C0000001E
+:02647D0000001D
+:02647E0000001C
+:02647F0000001B
+:0264800000001A
+:02648100000019
+:02648200000018
+:02648300000017
+:02648400000016
+:02648500000015
+:02648600000014
+:02648700000013
+:02648800000012
+:02648900000011
+:02648A00000010
+:02648B0000000F
+:02648C0000000E
+:02648D0000000D
+:02648E0000000C
+:02648F0000000B
+:0264900000000A
+:02649100000009
+:02649200000008
+:02649300000007
+:02649400000006
+:02649500000005
+:02649600000004
+:02649700000003
+:02649800000002
+:02649900000001
+:02649A00000000
+:02649B000000FF
+:02649C000000FE
+:02649D000000FD
+:02649E000000FC
+:02649F000000FB
+:0264A0000000FA
+:0264A1000000F9
+:0264A2000000F8
+:0264A3000000F7
+:0264A4000000F6
+:0264A5000000F5
+:0264A6000000F4
+:0264A7000000F3
+:0264A8000000F2
+:0264A9000000F1
+:0264AA000000F0
+:0264AB000000EF
+:0264AC000000EE
+:0264AD000000ED
+:0264AE000000EC
+:0264AF000000EB
+:0264B0000000EA
+:0264B1000000E9
+:0264B2000000E8
+:0264B3000000E7
+:0264B4000000E6
+:0264B5000000E5
+:0264B6000000E4
+:0264B7000000E3
+:0264B8000000E2
+:0264B9000000E1
+:0264BA000000E0
+:0264BB000000DF
+:0264BC000000DE
+:0264BD000000DD
+:0264BE000000DC
+:0264BF000000DB
+:0264C0000000DA
+:0264C1000000D9
+:0264C2000000D8
+:0264C3000000D7
+:0264C4000000D6
+:0264C5000000D5
+:0264C6000000D4
+:0264C7000000D3
+:0264C8000000D2
+:0264C9000000D1
+:0264CA000000D0
+:0264CB000000CF
+:0264CC000000CE
+:0264CD000000CD
+:0264CE000000CC
+:0264CF000000CB
+:0264D0000000CA
+:0264D1000000C9
+:0264D2000000C8
+:0264D3000000C7
+:0264D4000000C6
+:0264D5000000C5
+:0264D6000000C4
+:0264D7000000C3
+:0264D8000000C2
+:0264D9000000C1
+:0264DA000000C0
+:0264DB000000BF
+:0264DC000000BE
+:0264DD000000BD
+:0264DE000000BC
+:0264DF000000BB
+:0264E0000000BA
+:0264E1000000B9
+:0264E2000000B8
+:0264E3000000B7
+:0264E4000000B6
+:0264E5000000B5
+:0264E6000000B4
+:0264E7000000B3
+:0264E8000000B2
+:0264E9000000B1
+:0264EA000000B0
+:0264EB000000AF
+:0264EC000000AE
+:0264ED000000AD
+:0264EE000000AC
+:0264EF000000AB
+:0264F0000000AA
+:0264F1000000A9
+:0264F2000000A8
+:0264F3000000A7
+:0264F4000000A6
+:0264F5000000A5
+:0264F6000000A4
+:0264F7000000A3
+:0264F8000000A2
+:0264F9000000A1
+:0264FA000000A0
+:0264FB0000009F
+:0264FC0000009E
+:0264FD0000009D
+:0264FE0000009C
+:0264FF0000009B
+:02650000000099
+:02650100000098
+:02650200000097
+:02650300000096
+:02650400000095
+:02650500000094
+:02650600000093
+:02650700000092
+:02650800000091
+:02650900000090
+:02650A0000008F
+:02650B0000008E
+:02650C0000008D
+:02650D0000008C
+:02650E0000008B
+:02650F0000008A
+:02651000000089
+:02651100000088
+:02651200000087
+:02651300000086
+:02651400000085
+:02651500000084
+:02651600000083
+:02651700000082
+:02651800000081
+:02651900000080
+:02651A0000007F
+:02651B0000007E
+:02651C0000007D
+:02651D0000007C
+:02651E0000007B
+:02651F0000007A
+:02652000000079
+:02652100000078
+:02652200000077
+:02652300000076
+:02652400000075
+:02652500000074
+:02652600000073
+:02652700000072
+:02652800000071
+:02652900000070
+:02652A0000006F
+:02652B0000006E
+:02652C0000006D
+:02652D0000006C
+:02652E0000006B
+:02652F0000006A
+:02653000000069
+:02653100000068
+:02653200000067
+:02653300000066
+:02653400000065
+:02653500000064
+:02653600000063
+:02653700000062
+:02653800000061
+:02653900000060
+:02653A0000005F
+:02653B0000005E
+:02653C0000005D
+:02653D0000005C
+:02653E0000005B
+:02653F0000005A
+:02654000000059
+:02654100000058
+:02654200000057
+:02654300000056
+:02654400000055
+:02654500000054
+:02654600000053
+:02654700000052
+:02654800000051
+:02654900000050
+:02654A0000004F
+:02654B0000004E
+:02654C0000004D
+:02654D0000004C
+:02654E0000004B
+:02654F0000004A
+:02655000000049
+:02655100000048
+:02655200000047
+:02655300000046
+:02655400000045
+:02655500000044
+:02655600000043
+:02655700000042
+:02655800000041
+:02655900000040
+:02655A0000003F
+:02655B0000003E
+:02655C0000003D
+:02655D0000003C
+:02655E0000003B
+:02655F0000003A
+:02656000000039
+:02656100000038
+:02656200000037
+:02656300000036
+:02656400000035
+:02656500000034
+:02656600000033
+:02656700000032
+:02656800000031
+:02656900000030
+:02656A0000002F
+:02656B0000002E
+:02656C0000002D
+:02656D0000002C
+:02656E0000002B
+:02656F0000002A
+:02657000000029
+:02657100000028
+:02657200000027
+:02657300000026
+:02657400000025
+:02657500000024
+:02657600000023
+:02657700000022
+:02657800000021
+:02657900000020
+:02657A0000001F
+:02657B0000001E
+:02657C0000001D
+:02657D0000001C
+:02657E0000001B
+:02657F0000001A
+:02658000000019
+:02658100000018
+:02658200000017
+:02658300000016
+:02658400000015
+:02658500000014
+:02658600000013
+:02658700000012
+:02658800000011
+:02658900000010
+:02658A0000000F
+:02658B0000000E
+:02658C0000000D
+:02658D0000000C
+:02658E0000000B
+:02658F0000000A
+:02659000000009
+:02659100000008
+:02659200000007
+:02659300000006
+:02659400000005
+:02659500000004
+:02659600000003
+:02659700000002
+:02659800000001
+:02659900000000
+:02659A000000FF
+:02659B000000FE
+:02659C000000FD
+:02659D000000FC
+:02659E000000FB
+:02659F000000FA
+:0265A0000000F9
+:0265A1000000F8
+:0265A2000000F7
+:0265A3000000F6
+:0265A4000000F5
+:0265A5000000F4
+:0265A6000000F3
+:0265A7000000F2
+:0265A8000000F1
+:0265A9000000F0
+:0265AA000000EF
+:0265AB000000EE
+:0265AC000000ED
+:0265AD000000EC
+:0265AE000000EB
+:0265AF000000EA
+:0265B0000000E9
+:0265B1000000E8
+:0265B2000000E7
+:0265B3000000E6
+:0265B4000000E5
+:0265B5000000E4
+:0265B6000000E3
+:0265B7000000E2
+:0265B8000000E1
+:0265B9000000E0
+:0265BA000000DF
+:0265BB000000DE
+:0265BC000000DD
+:0265BD000000DC
+:0265BE000000DB
+:0265BF000000DA
+:0265C0000000D9
+:0265C1000000D8
+:0265C2000000D7
+:0265C3000000D6
+:0265C4000000D5
+:0265C5000000D4
+:0265C6000000D3
+:0265C7000000D2
+:0265C8000000D1
+:0265C9000000D0
+:0265CA000000CF
+:0265CB000000CE
+:0265CC000000CD
+:0265CD000000CC
+:0265CE000000CB
+:0265CF000000CA
+:0265D0000000C9
+:0265D1000000C8
+:0265D2000000C7
+:0265D3000000C6
+:0265D4000000C5
+:0265D5000000C4
+:0265D6000000C3
+:0265D7000000C2
+:0265D8000000C1
+:0265D9000000C0
+:0265DA000000BF
+:0265DB000000BE
+:0265DC000000BD
+:0265DD000000BC
+:0265DE000000BB
+:0265DF000000BA
+:0265E0000000B9
+:0265E1000000B8
+:0265E2000000B7
+:0265E3000000B6
+:0265E4000000B5
+:0265E5000000B4
+:0265E6000000B3
+:0265E7000000B2
+:0265E8000000B1
+:0265E9000000B0
+:0265EA000000AF
+:0265EB000000AE
+:0265EC000000AD
+:0265ED000000AC
+:0265EE000000AB
+:0265EF000000AA
+:0265F0000000A9
+:0265F1000000A8
+:0265F2000000A7
+:0265F3000000A6
+:0265F4000000A5
+:0265F5000000A4
+:0265F6000000A3
+:0265F7000000A2
+:0265F8000000A1
+:0265F9000000A0
+:0265FA0000009F
+:0265FB0000009E
+:0265FC0000009D
+:0265FD0000009C
+:0265FE0000009B
+:0265FF0000009A
+:02660000000098
+:02660100000097
+:02660200000096
+:02660300000095
+:02660400000094
+:02660500000093
+:02660600000092
+:02660700000091
+:02660800000090
+:0266090000008F
+:02660A0000008E
+:02660B0000008D
+:02660C0000008C
+:02660D0000008B
+:02660E0000008A
+:02660F00000089
+:02661000000088
+:02661100000087
+:02661200000086
+:02661300000085
+:02661400000084
+:02661500000083
+:02661600000082
+:02661700000081
+:02661800000080
+:0266190000007F
+:02661A0000007E
+:02661B0000007D
+:02661C0000007C
+:02661D0000007B
+:02661E0000007A
+:02661F00000079
+:02662000000078
+:02662100000077
+:02662200000076
+:02662300000075
+:02662400000074
+:02662500000073
+:02662600000072
+:02662700000071
+:02662800000070
+:0266290000006F
+:02662A0000006E
+:02662B0000006D
+:02662C0000006C
+:02662D0000006B
+:02662E0000006A
+:02662F00000069
+:02663000000068
+:02663100000067
+:02663200000066
+:02663300000065
+:02663400000064
+:02663500000063
+:02663600000062
+:02663700000061
+:02663800000060
+:0266390000005F
+:02663A0000005E
+:02663B0000005D
+:02663C0000005C
+:02663D0000005B
+:02663E0000005A
+:02663F00000059
+:02664000000058
+:02664100000057
+:02664200000056
+:02664300000055
+:02664400000054
+:02664500000053
+:02664600000052
+:02664700000051
+:02664800000050
+:0266490000004F
+:02664A0000004E
+:02664B0000004D
+:02664C0000004C
+:02664D0000004B
+:02664E0000004A
+:02664F00000049
+:02665000000048
+:02665100000047
+:02665200000046
+:02665300000045
+:02665400000044
+:02665500000043
+:02665600000042
+:02665700000041
+:02665800000040
+:0266590000003F
+:02665A0000003E
+:02665B0000003D
+:02665C0000003C
+:02665D0000003B
+:02665E0000003A
+:02665F00000039
+:02666000000038
+:02666100000037
+:02666200000036
+:02666300000035
+:02666400000034
+:02666500000033
+:02666600000032
+:02666700000031
+:02666800000030
+:0266690000002F
+:02666A0000002E
+:02666B0000002D
+:02666C0000002C
+:02666D0000002B
+:02666E0000002A
+:02666F00000029
+:02667000000028
+:02667100000027
+:02667200000026
+:02667300000025
+:02667400000024
+:02667500000023
+:02667600000022
+:02667700000021
+:02667800000020
+:0266790000001F
+:02667A0000001E
+:02667B0000001D
+:02667C0000001C
+:02667D0000001B
+:02667E0000001A
+:02667F00000019
+:02668000000018
+:02668100000017
+:02668200000016
+:02668300000015
+:02668400000014
+:02668500000013
+:02668600000012
+:02668700000011
+:02668800000010
+:0266890000000F
+:02668A0000000E
+:02668B0000000D
+:02668C0000000C
+:02668D0000000B
+:02668E0000000A
+:02668F00000009
+:02669000000008
+:02669100000007
+:02669200000006
+:02669300000005
+:02669400000004
+:02669500000003
+:02669600000002
+:02669700000001
+:02669800000000
+:026699000000FF
+:02669A000000FE
+:02669B000000FD
+:02669C000000FC
+:02669D000000FB
+:02669E000000FA
+:02669F000000F9
+:0266A0000000F8
+:0266A1000000F7
+:0266A2000000F6
+:0266A3000000F5
+:0266A4000000F4
+:0266A5000000F3
+:0266A6000000F2
+:0266A7000000F1
+:0266A8000000F0
+:0266A9000000EF
+:0266AA000000EE
+:0266AB000000ED
+:0266AC000000EC
+:0266AD000000EB
+:0266AE000000EA
+:0266AF000000E9
+:0266B0000000E8
+:0266B1000000E7
+:0266B2000000E6
+:0266B3000000E5
+:0266B4000000E4
+:0266B5000000E3
+:0266B6000000E2
+:0266B7000000E1
+:0266B8000000E0
+:0266B9000000DF
+:0266BA000000DE
+:0266BB000000DD
+:0266BC000000DC
+:0266BD000000DB
+:0266BE000000DA
+:0266BF000000D9
+:0266C0000000D8
+:0266C1000000D7
+:0266C2000000D6
+:0266C3000000D5
+:0266C4000000D4
+:0266C5000000D3
+:0266C6000000D2
+:0266C7000000D1
+:0266C8000000D0
+:0266C9000000CF
+:0266CA000000CE
+:0266CB000000CD
+:0266CC000000CC
+:0266CD000000CB
+:0266CE000000CA
+:0266CF000000C9
+:0266D0000000C8
+:0266D1000000C7
+:0266D2000000C6
+:0266D3000000C5
+:0266D4000000C4
+:0266D5000000C3
+:0266D6000000C2
+:0266D7000000C1
+:0266D8000000C0
+:0266D9000000BF
+:0266DA000000BE
+:0266DB000000BD
+:0266DC000000BC
+:0266DD000000BB
+:0266DE000000BA
+:0266DF000000B9
+:0266E0000000B8
+:0266E1000000B7
+:0266E2000000B6
+:0266E3000000B5
+:0266E4000000B4
+:0266E5000000B3
+:0266E6000000B2
+:0266E7000000B1
+:0266E8000000B0
+:0266E9000000AF
+:0266EA000000AE
+:0266EB000000AD
+:0266EC000000AC
+:0266ED000000AB
+:0266EE000000AA
+:0266EF000000A9
+:0266F0000000A8
+:0266F1000000A7
+:0266F2000000A6
+:0266F3000000A5
+:0266F4000000A4
+:0266F5000000A3
+:0266F6000000A2
+:0266F7000000A1
+:0266F8000000A0
+:0266F90000009F
+:0266FA0000009E
+:0266FB0000009D
+:0266FC0000009C
+:0266FD0000009B
+:0266FE0000009A
+:0266FF00000099
+:02670000000097
+:02670100000096
+:02670200000095
+:02670300000094
+:02670400000093
+:02670500000092
+:02670600000091
+:02670700000090
+:0267080000008F
+:0267090000008E
+:02670A0000008D
+:02670B0000008C
+:02670C0000008B
+:02670D0000008A
+:02670E00000089
+:02670F00000088
+:02671000000087
+:02671100000086
+:02671200000085
+:02671300000084
+:02671400000083
+:02671500000082
+:02671600000081
+:02671700000080
+:0267180000007F
+:0267190000007E
+:02671A0000007D
+:02671B0000007C
+:02671C0000007B
+:02671D0000007A
+:02671E00000079
+:02671F00000078
+:02672000000077
+:02672100000076
+:02672200000075
+:02672300000074
+:02672400000073
+:02672500000072
+:02672600000071
+:02672700000070
+:0267280000006F
+:0267290000006E
+:02672A0000006D
+:02672B0000006C
+:02672C0000006B
+:02672D0000006A
+:02672E00000069
+:02672F00000068
+:02673000000067
+:02673100000066
+:02673200000065
+:02673300000064
+:02673400000063
+:02673500000062
+:02673600000061
+:02673700000060
+:0267380000005F
+:0267390000005E
+:02673A0000005D
+:02673B0000005C
+:02673C0000005B
+:02673D0000005A
+:02673E00000059
+:02673F00000058
+:02674000000057
+:02674100000056
+:02674200000055
+:02674300000054
+:02674400000053
+:02674500000052
+:02674600000051
+:02674700000050
+:0267480000004F
+:0267490000004E
+:02674A0000004D
+:02674B0000004C
+:02674C0000004B
+:02674D0000004A
+:02674E00000049
+:02674F00000048
+:02675000000047
+:02675100000046
+:02675200000045
+:02675300000044
+:02675400000043
+:02675500000042
+:02675600000041
+:02675700000040
+:0267580000003F
+:0267590000003E
+:02675A0000003D
+:02675B0000003C
+:02675C0000003B
+:02675D0000003A
+:02675E00000039
+:02675F00000038
+:02676000000037
+:02676100000036
+:02676200000035
+:02676300000034
+:02676400000033
+:02676500000032
+:02676600000031
+:02676700000030
+:0267680000002F
+:0267690000002E
+:02676A0000002D
+:02676B0000002C
+:02676C0000002B
+:02676D0000002A
+:02676E00000029
+:02676F00000028
+:02677000000027
+:02677100000026
+:02677200000025
+:02677300000024
+:02677400000023
+:02677500000022
+:02677600000021
+:02677700000020
+:0267780000001F
+:0267790000001E
+:02677A0000001D
+:02677B0000001C
+:02677C0000001B
+:02677D0000001A
+:02677E00000019
+:02677F00000018
+:02678000000017
+:02678100000016
+:02678200000015
+:02678300000014
+:02678400000013
+:02678500000012
+:02678600000011
+:02678700000010
+:0267880000000F
+:0267890000000E
+:02678A0000000D
+:02678B0000000C
+:02678C0000000B
+:02678D0000000A
+:02678E00000009
+:02678F00000008
+:02679000000007
+:02679100000006
+:02679200000005
+:02679300000004
+:02679400000003
+:02679500000002
+:02679600000001
+:02679700000000
+:026798000000FF
+:026799000000FE
+:02679A000000FD
+:02679B000000FC
+:02679C000000FB
+:02679D000000FA
+:02679E000000F9
+:02679F000000F8
+:0267A0000000F7
+:0267A1000000F6
+:0267A2000000F5
+:0267A3000000F4
+:0267A4000000F3
+:0267A5000000F2
+:0267A6000000F1
+:0267A7000000F0
+:0267A8000000EF
+:0267A9000000EE
+:0267AA000000ED
+:0267AB000000EC
+:0267AC000000EB
+:0267AD000000EA
+:0267AE000000E9
+:0267AF000000E8
+:0267B0000000E7
+:0267B1000000E6
+:0267B2000000E5
+:0267B3000000E4
+:0267B4000000E3
+:0267B5000000E2
+:0267B6000000E1
+:0267B7000000E0
+:0267B8000000DF
+:0267B9000000DE
+:0267BA000000DD
+:0267BB000000DC
+:0267BC000000DB
+:0267BD000000DA
+:0267BE000000D9
+:0267BF000000D8
+:0267C0000000D7
+:0267C1000000D6
+:0267C2000000D5
+:0267C3000000D4
+:0267C4000000D3
+:0267C5000000D2
+:0267C6000000D1
+:0267C7000000D0
+:0267C8000000CF
+:0267C9000000CE
+:0267CA000000CD
+:0267CB000000CC
+:0267CC000000CB
+:0267CD000000CA
+:0267CE000000C9
+:0267CF000000C8
+:0267D0000000C7
+:0267D1000000C6
+:0267D2000000C5
+:0267D3000000C4
+:0267D4000000C3
+:0267D5000000C2
+:0267D6000000C1
+:0267D7000000C0
+:0267D8000000BF
+:0267D9000000BE
+:0267DA000000BD
+:0267DB000000BC
+:0267DC000000BB
+:0267DD000000BA
+:0267DE000000B9
+:0267DF000000B8
+:0267E0000000B7
+:0267E1000000B6
+:0267E2000000B5
+:0267E3000000B4
+:0267E4000000B3
+:0267E5000000B2
+:0267E6000000B1
+:0267E7000000B0
+:0267E8000000AF
+:0267E9000000AE
+:0267EA000000AD
+:0267EB000000AC
+:0267EC000000AB
+:0267ED000000AA
+:0267EE000000A9
+:0267EF000000A8
+:0267F0000000A7
+:0267F1000000A6
+:0267F2000000A5
+:0267F3000000A4
+:0267F4000000A3
+:0267F5000000A2
+:0267F6000000A1
+:0267F7000000A0
+:0267F80000009F
+:0267F90000009E
+:0267FA0000009D
+:0267FB0000009C
+:0267FC0000009B
+:0267FD0000009A
+:0267FE00000099
+:0267FF00000098
+:02680000000096
+:02680100000095
+:02680200000094
+:02680300000093
+:02680400000092
+:02680500000091
+:02680600000090
+:0268070000008F
+:0268080000008E
+:0268090000008D
+:02680A0000008C
+:02680B0000008B
+:02680C0000008A
+:02680D00000089
+:02680E00000088
+:02680F00000087
+:02681000000086
+:02681100000085
+:02681200000084
+:02681300000083
+:02681400000082
+:02681500000081
+:02681600000080
+:0268170000007F
+:0268180000007E
+:0268190000007D
+:02681A0000007C
+:02681B0000007B
+:02681C0000007A
+:02681D00000079
+:02681E00000078
+:02681F00000077
+:02682000000076
+:02682100000075
+:02682200000074
+:02682300000073
+:02682400000072
+:02682500000071
+:02682600000070
+:0268270000006F
+:0268280000006E
+:0268290000006D
+:02682A0000006C
+:02682B0000006B
+:02682C0000006A
+:02682D00000069
+:02682E00000068
+:02682F00000067
+:02683000000066
+:02683100000065
+:02683200000064
+:02683300000063
+:02683400000062
+:02683500000061
+:02683600000060
+:0268370000005F
+:0268380000005E
+:0268390000005D
+:02683A0000005C
+:02683B0000005B
+:02683C0000005A
+:02683D00000059
+:02683E00000058
+:02683F00000057
+:02684000000056
+:02684100000055
+:02684200000054
+:02684300000053
+:02684400000052
+:02684500000051
+:02684600000050
+:0268470000004F
+:0268480000004E
+:0268490000004D
+:02684A0000004C
+:02684B0000004B
+:02684C0000004A
+:02684D00000049
+:02684E00000048
+:02684F00000047
+:02685000000046
+:02685100000045
+:02685200000044
+:02685300000043
+:02685400000042
+:02685500000041
+:02685600000040
+:0268570000003F
+:0268580000003E
+:0268590000003D
+:02685A0000003C
+:02685B0000003B
+:02685C0000003A
+:02685D00000039
+:02685E00000038
+:02685F00000037
+:02686000000036
+:02686100000035
+:02686200000034
+:02686300000033
+:02686400000032
+:02686500000031
+:02686600000030
+:0268670000002F
+:0268680000002E
+:0268690000002D
+:02686A0000002C
+:02686B0000002B
+:02686C0000002A
+:02686D00000029
+:02686E00000028
+:02686F00000027
+:02687000000026
+:02687100000025
+:02687200000024
+:02687300000023
+:02687400000022
+:02687500000021
+:02687600000020
+:0268770000001F
+:0268780000001E
+:0268790000001D
+:02687A0000001C
+:02687B0000001B
+:02687C0000001A
+:02687D00000019
+:02687E00000018
+:02687F00000017
+:02688000000016
+:02688100000015
+:02688200000014
+:02688300000013
+:02688400000012
+:02688500000011
+:02688600000010
+:0268870000000F
+:0268880000000E
+:0268890000000D
+:02688A0000000C
+:02688B0000000B
+:02688C0000000A
+:02688D00000009
+:02688E00000008
+:02688F00000007
+:02689000000006
+:02689100000005
+:02689200000004
+:02689300000003
+:02689400000002
+:02689500000001
+:02689600000000
+:026897000000FF
+:026898000000FE
+:026899000000FD
+:02689A000000FC
+:02689B000000FB
+:02689C000000FA
+:02689D000000F9
+:02689E000000F8
+:02689F000000F7
+:0268A0000000F6
+:0268A1000000F5
+:0268A2000000F4
+:0268A3000000F3
+:0268A4000000F2
+:0268A5000000F1
+:0268A6000000F0
+:0268A7000000EF
+:0268A8000000EE
+:0268A9000000ED
+:0268AA000000EC
+:0268AB000000EB
+:0268AC000000EA
+:0268AD000000E9
+:0268AE000000E8
+:0268AF000000E7
+:0268B0000000E6
+:0268B1000000E5
+:0268B2000000E4
+:0268B3000000E3
+:0268B4000000E2
+:0268B5000000E1
+:0268B6000000E0
+:0268B7000000DF
+:0268B8000000DE
+:0268B9000000DD
+:0268BA000000DC
+:0268BB000000DB
+:0268BC000000DA
+:0268BD000000D9
+:0268BE000000D8
+:0268BF000000D7
+:0268C0000000D6
+:0268C1000000D5
+:0268C2000000D4
+:0268C3000000D3
+:0268C4000000D2
+:0268C5000000D1
+:0268C6000000D0
+:0268C7000000CF
+:0268C8000000CE
+:0268C9000000CD
+:0268CA000000CC
+:0268CB000000CB
+:0268CC000000CA
+:0268CD000000C9
+:0268CE000000C8
+:0268CF000000C7
+:0268D0000000C6
+:0268D1000000C5
+:0268D2000000C4
+:0268D3000000C3
+:0268D4000000C2
+:0268D5000000C1
+:0268D6000000C0
+:0268D7000000BF
+:0268D8000000BE
+:0268D9000000BD
+:0268DA000000BC
+:0268DB000000BB
+:0268DC000000BA
+:0268DD000000B9
+:0268DE000000B8
+:0268DF000000B7
+:0268E0000000B6
+:0268E1000000B5
+:0268E2000000B4
+:0268E3000000B3
+:0268E4000000B2
+:0268E5000000B1
+:0268E6000000B0
+:0268E7000000AF
+:0268E8000000AE
+:0268E9000000AD
+:0268EA000000AC
+:0268EB000000AB
+:0268EC000000AA
+:0268ED000000A9
+:0268EE000000A8
+:0268EF000000A7
+:0268F0000000A6
+:0268F1000000A5
+:0268F2000000A4
+:0268F3000000A3
+:0268F4000000A2
+:0268F5000000A1
+:0268F6000000A0
+:0268F70000009F
+:0268F80000009E
+:0268F90000009D
+:0268FA0000009C
+:0268FB0000009B
+:0268FC0000009A
+:0268FD00000099
+:0268FE00000098
+:0268FF00000097
+:02690000000095
+:02690100000094
+:02690200000093
+:02690300000092
+:02690400000091
+:02690500000090
+:0269060000008F
+:0269070000008E
+:0269080000008D
+:0269090000008C
+:02690A0000008B
+:02690B0000008A
+:02690C00000089
+:02690D00000088
+:02690E00000087
+:02690F00000086
+:02691000000085
+:02691100000084
+:02691200000083
+:02691300000082
+:02691400000081
+:02691500000080
+:0269160000007F
+:0269170000007E
+:0269180000007D
+:0269190000007C
+:02691A0000007B
+:02691B0000007A
+:02691C00000079
+:02691D00000078
+:02691E00000077
+:02691F00000076
+:02692000000075
+:02692100000074
+:02692200000073
+:02692300000072
+:02692400000071
+:02692500000070
+:0269260000006F
+:0269270000006E
+:0269280000006D
+:0269290000006C
+:02692A0000006B
+:02692B0000006A
+:02692C00000069
+:02692D00000068
+:02692E00000067
+:02692F00000066
+:02693000000065
+:02693100000064
+:02693200000063
+:02693300000062
+:02693400000061
+:02693500000060
+:0269360000005F
+:0269370000005E
+:0269380000005D
+:0269390000005C
+:02693A0000005B
+:02693B0000005A
+:02693C00000059
+:02693D00000058
+:02693E00000057
+:02693F00000056
+:02694000000055
+:02694100000054
+:02694200000053
+:02694300000052
+:02694400000051
+:02694500000050
+:0269460000004F
+:0269470000004E
+:0269480000004D
+:0269490000004C
+:02694A0000004B
+:02694B0000004A
+:02694C00000049
+:02694D00000048
+:02694E00000047
+:02694F00000046
+:02695000000045
+:02695100000044
+:02695200000043
+:02695300000042
+:02695400000041
+:02695500000040
+:0269560000003F
+:0269570000003E
+:0269580000003D
+:0269590000003C
+:02695A0000003B
+:02695B0000003A
+:02695C00000039
+:02695D00000038
+:02695E00000037
+:02695F00000036
+:02696000000035
+:02696100000034
+:02696200000033
+:02696300000032
+:02696400000031
+:02696500000030
+:0269660000002F
+:0269670000002E
+:0269680000002D
+:0269690000002C
+:02696A0000002B
+:02696B0000002A
+:02696C00000029
+:02696D00000028
+:02696E00000027
+:02696F00000026
+:02697000000025
+:02697100000024
+:02697200000023
+:02697300000022
+:02697400000021
+:02697500000020
+:0269760000001F
+:0269770000001E
+:0269780000001D
+:0269790000001C
+:02697A0000001B
+:02697B0000001A
+:02697C00000019
+:02697D00000018
+:02697E00000017
+:02697F00000016
+:02698000000015
+:02698100000014
+:02698200000013
+:02698300000012
+:02698400000011
+:02698500000010
+:0269860000000F
+:0269870000000E
+:0269880000000D
+:0269890000000C
+:02698A0000000B
+:02698B0000000A
+:02698C00000009
+:02698D00000008
+:02698E00000007
+:02698F00000006
+:02699000000005
+:02699100000004
+:02699200000003
+:02699300000002
+:02699400000001
+:02699500000000
+:026996000000FF
+:026997000000FE
+:026998000000FD
+:026999000000FC
+:02699A000000FB
+:02699B000000FA
+:02699C000000F9
+:02699D000000F8
+:02699E000000F7
+:02699F000000F6
+:0269A0000000F5
+:0269A1000000F4
+:0269A2000000F3
+:0269A3000000F2
+:0269A4000000F1
+:0269A5000000F0
+:0269A6000000EF
+:0269A7000000EE
+:0269A8000000ED
+:0269A9000000EC
+:0269AA000000EB
+:0269AB000000EA
+:0269AC000000E9
+:0269AD000000E8
+:0269AE000000E7
+:0269AF000000E6
+:0269B0000000E5
+:0269B1000000E4
+:0269B2000000E3
+:0269B3000000E2
+:0269B4000000E1
+:0269B5000000E0
+:0269B6000000DF
+:0269B7000000DE
+:0269B8000000DD
+:0269B9000000DC
+:0269BA000000DB
+:0269BB000000DA
+:0269BC000000D9
+:0269BD000000D8
+:0269BE000000D7
+:0269BF000000D6
+:0269C0000000D5
+:0269C1000000D4
+:0269C2000000D3
+:0269C3000000D2
+:0269C4000000D1
+:0269C5000000D0
+:0269C6000000CF
+:0269C7000000CE
+:0269C8000000CD
+:0269C9000000CC
+:0269CA000000CB
+:0269CB000000CA
+:0269CC000000C9
+:0269CD000000C8
+:0269CE000000C7
+:0269CF000000C6
+:0269D0000000C5
+:0269D1000000C4
+:0269D2000000C3
+:0269D3000000C2
+:0269D4000000C1
+:0269D5000000C0
+:0269D6000000BF
+:0269D7000000BE
+:0269D8000000BD
+:0269D9000000BC
+:0269DA000000BB
+:0269DB000000BA
+:0269DC000000B9
+:0269DD000000B8
+:0269DE000000B7
+:0269DF000000B6
+:0269E0000000B5
+:0269E1000000B4
+:0269E2000000B3
+:0269E3000000B2
+:0269E4000000B1
+:0269E5000000B0
+:0269E6000000AF
+:0269E7000000AE
+:0269E8000000AD
+:0269E9000000AC
+:0269EA000000AB
+:0269EB000000AA
+:0269EC000000A9
+:0269ED000000A8
+:0269EE000000A7
+:0269EF000000A6
+:0269F0000000A5
+:0269F1000000A4
+:0269F2000000A3
+:0269F3000000A2
+:0269F4000000A1
+:0269F5000000A0
+:0269F60000009F
+:0269F70000009E
+:0269F80000009D
+:0269F90000009C
+:0269FA0000009B
+:0269FB0000009A
+:0269FC00000099
+:0269FD00000098
+:0269FE00000097
+:0269FF00000096
+:026A0000000094
+:026A0100000093
+:026A0200000092
+:026A0300000091
+:026A0400000090
+:026A050000008F
+:026A060000008E
+:026A070000008D
+:026A080000008C
+:026A090000008B
+:026A0A0000008A
+:026A0B00000089
+:026A0C00000088
+:026A0D00000087
+:026A0E00000086
+:026A0F00000085
+:026A1000000084
+:026A1100000083
+:026A1200000082
+:026A1300000081
+:026A1400000080
+:026A150000007F
+:026A160000007E
+:026A170000007D
+:026A180000007C
+:026A190000007B
+:026A1A0000007A
+:026A1B00000079
+:026A1C00000078
+:026A1D00000077
+:026A1E00000076
+:026A1F00000075
+:026A2000000074
+:026A2100000073
+:026A2200000072
+:026A2300000071
+:026A2400000070
+:026A250000006F
+:026A260000006E
+:026A270000006D
+:026A280000006C
+:026A290000006B
+:026A2A0000006A
+:026A2B00000069
+:026A2C00000068
+:026A2D00000067
+:026A2E00000066
+:026A2F00000065
+:026A3000000064
+:026A3100000063
+:026A3200000062
+:026A3300000061
+:026A3400000060
+:026A350000005F
+:026A360000005E
+:026A370000005D
+:026A380000005C
+:026A390000005B
+:026A3A0000005A
+:026A3B00000059
+:026A3C00000058
+:026A3D00000057
+:026A3E00000056
+:026A3F00000055
+:026A4000000054
+:026A4100000053
+:026A4200000052
+:026A4300000051
+:026A4400000050
+:026A450000004F
+:026A460000004E
+:026A470000004D
+:026A480000004C
+:026A490000004B
+:026A4A0000004A
+:026A4B00000049
+:026A4C00000048
+:026A4D00000047
+:026A4E00000046
+:026A4F00000045
+:026A5000000044
+:026A5100000043
+:026A5200000042
+:026A5300000041
+:026A5400000040
+:026A550000003F
+:026A560000003E
+:026A570000003D
+:026A580000003C
+:026A590000003B
+:026A5A0000003A
+:026A5B00000039
+:026A5C00000038
+:026A5D00000037
+:026A5E00000036
+:026A5F00000035
+:026A6000000034
+:026A6100000033
+:026A6200000032
+:026A6300000031
+:026A6400000030
+:026A650000002F
+:026A660000002E
+:026A670000002D
+:026A680000002C
+:026A690000002B
+:026A6A0000002A
+:026A6B00000029
+:026A6C00000028
+:026A6D00000027
+:026A6E00000026
+:026A6F00000025
+:026A7000000024
+:026A7100000023
+:026A7200000022
+:026A7300000021
+:026A7400000020
+:026A750000001F
+:026A760000001E
+:026A770000001D
+:026A780000001C
+:026A790000001B
+:026A7A0000001A
+:026A7B00000019
+:026A7C00000018
+:026A7D00000017
+:026A7E00000016
+:026A7F00000015
+:026A8000000014
+:026A8100000013
+:026A8200000012
+:026A8300000011
+:026A8400000010
+:026A850000000F
+:026A860000000E
+:026A870000000D
+:026A880000000C
+:026A890000000B
+:026A8A0000000A
+:026A8B00000009
+:026A8C00000008
+:026A8D00000007
+:026A8E00000006
+:026A8F00000005
+:026A9000000004
+:026A9100000003
+:026A9200000002
+:026A9300000001
+:026A9400000000
+:026A95000000FF
+:026A96000000FE
+:026A97000000FD
+:026A98000000FC
+:026A99000000FB
+:026A9A000000FA
+:026A9B000000F9
+:026A9C000000F8
+:026A9D000000F7
+:026A9E000000F6
+:026A9F000000F5
+:026AA0000000F4
+:026AA1000000F3
+:026AA2000000F2
+:026AA3000000F1
+:026AA4000000F0
+:026AA5000000EF
+:026AA6000000EE
+:026AA7000000ED
+:026AA8000000EC
+:026AA9000000EB
+:026AAA000000EA
+:026AAB000000E9
+:026AAC000000E8
+:026AAD000000E7
+:026AAE000000E6
+:026AAF000000E5
+:026AB0000000E4
+:026AB1000000E3
+:026AB2000000E2
+:026AB3000000E1
+:026AB4000000E0
+:026AB5000000DF
+:026AB6000000DE
+:026AB7000000DD
+:026AB8000000DC
+:026AB9000000DB
+:026ABA000000DA
+:026ABB000000D9
+:026ABC000000D8
+:026ABD000000D7
+:026ABE000000D6
+:026ABF000000D5
+:026AC0000000D4
+:026AC1000000D3
+:026AC2000000D2
+:026AC3000000D1
+:026AC4000000D0
+:026AC5000000CF
+:026AC6000000CE
+:026AC7000000CD
+:026AC8000000CC
+:026AC9000000CB
+:026ACA000000CA
+:026ACB000000C9
+:026ACC000000C8
+:026ACD000000C7
+:026ACE000000C6
+:026ACF000000C5
+:026AD0000000C4
+:026AD1000000C3
+:026AD2000000C2
+:026AD3000000C1
+:026AD4000000C0
+:026AD5000000BF
+:026AD6000000BE
+:026AD7000000BD
+:026AD8000000BC
+:026AD9000000BB
+:026ADA000000BA
+:026ADB000000B9
+:026ADC000000B8
+:026ADD000000B7
+:026ADE000000B6
+:026ADF000000B5
+:026AE0000000B4
+:026AE1000000B3
+:026AE2000000B2
+:026AE3000000B1
+:026AE4000000B0
+:026AE5000000AF
+:026AE6000000AE
+:026AE7000000AD
+:026AE8000000AC
+:026AE9000000AB
+:026AEA000000AA
+:026AEB000000A9
+:026AEC000000A8
+:026AED000000A7
+:026AEE000000A6
+:026AEF000000A5
+:026AF0000000A4
+:026AF1000000A3
+:026AF2000000A2
+:026AF3000000A1
+:026AF4000000A0
+:026AF50000009F
+:026AF60000009E
+:026AF70000009D
+:026AF80000009C
+:026AF90000009B
+:026AFA0000009A
+:026AFB00000099
+:026AFC00000098
+:026AFD00000097
+:026AFE00000096
+:026AFF00000095
+:026B0000000093
+:026B0100000092
+:026B0200000091
+:026B0300000090
+:026B040000008F
+:026B050000008E
+:026B060000008D
+:026B070000008C
+:026B080000008B
+:026B090000008A
+:026B0A00000089
+:026B0B00000088
+:026B0C00000087
+:026B0D00000086
+:026B0E00000085
+:026B0F00000084
+:026B1000000083
+:026B1100000082
+:026B1200000081
+:026B1300000080
+:026B140000007F
+:026B150000007E
+:026B160000007D
+:026B170000007C
+:026B180000007B
+:026B190000007A
+:026B1A00000079
+:026B1B00000078
+:026B1C00000077
+:026B1D00000076
+:026B1E00000075
+:026B1F00000074
+:026B2000000073
+:026B2100000072
+:026B2200000071
+:026B2300000070
+:026B240000006F
+:026B250000006E
+:026B260000006D
+:026B270000006C
+:026B280000006B
+:026B290000006A
+:026B2A00000069
+:026B2B00000068
+:026B2C00000067
+:026B2D00000066
+:026B2E00000065
+:026B2F00000064
+:026B3000000063
+:026B3100000062
+:026B3200000061
+:026B3300000060
+:026B340000005F
+:026B350000005E
+:026B360000005D
+:026B370000005C
+:026B380000005B
+:026B390000005A
+:026B3A00000059
+:026B3B00000058
+:026B3C00000057
+:026B3D00000056
+:026B3E00000055
+:026B3F00000054
+:026B4000000053
+:026B4100000052
+:026B4200000051
+:026B4300000050
+:026B440000004F
+:026B450000004E
+:026B460000004D
+:026B470000004C
+:026B480000004B
+:026B490000004A
+:026B4A00000049
+:026B4B00000048
+:026B4C00000047
+:026B4D00000046
+:026B4E00000045
+:026B4F00000044
+:026B5000000043
+:026B5100000042
+:026B5200000041
+:026B5300000040
+:026B540000003F
+:026B550000003E
+:026B560000003D
+:026B570000003C
+:026B580000003B
+:026B590000003A
+:026B5A00000039
+:026B5B00000038
+:026B5C00000037
+:026B5D00000036
+:026B5E00000035
+:026B5F00000034
+:026B6000000033
+:026B6100000032
+:026B6200000031
+:026B6300000030
+:026B640000002F
+:026B650000002E
+:026B660000002D
+:026B670000002C
+:026B680000002B
+:026B690000002A
+:026B6A00000029
+:026B6B00000028
+:026B6C00000027
+:026B6D00000026
+:026B6E00000025
+:026B6F00000024
+:026B7000000023
+:026B7100000022
+:026B7200000021
+:026B7300000020
+:026B740000001F
+:026B750000001E
+:026B760000001D
+:026B770000001C
+:026B780000001B
+:026B790000001A
+:026B7A00000019
+:026B7B00000018
+:026B7C00000017
+:026B7D00000016
+:026B7E00000015
+:026B7F00000014
+:026B8000000013
+:026B8100000012
+:026B8200000011
+:026B8300000010
+:026B840000000F
+:026B850000000E
+:026B860000000D
+:026B870000000C
+:026B880000000B
+:026B890000000A
+:026B8A00000009
+:026B8B00000008
+:026B8C00000007
+:026B8D00000006
+:026B8E00000005
+:026B8F00000004
+:026B9000000003
+:026B9100000002
+:026B9200000001
+:026B9300000000
+:026B94000000FF
+:026B95000000FE
+:026B96000000FD
+:026B97000000FC
+:026B98000000FB
+:026B99000000FA
+:026B9A000000F9
+:026B9B000000F8
+:026B9C000000F7
+:026B9D000000F6
+:026B9E000000F5
+:026B9F000000F4
+:026BA0000000F3
+:026BA1000000F2
+:026BA2000000F1
+:026BA3000000F0
+:026BA4000000EF
+:026BA5000000EE
+:026BA6000000ED
+:026BA7000000EC
+:026BA8000000EB
+:026BA9000000EA
+:026BAA000000E9
+:026BAB000000E8
+:026BAC000000E7
+:026BAD000000E6
+:026BAE000000E5
+:026BAF000000E4
+:026BB0000000E3
+:026BB1000000E2
+:026BB2000000E1
+:026BB3000000E0
+:026BB4000000DF
+:026BB5000000DE
+:026BB6000000DD
+:026BB7000000DC
+:026BB8000000DB
+:026BB9000000DA
+:026BBA000000D9
+:026BBB000000D8
+:026BBC000000D7
+:026BBD000000D6
+:026BBE000000D5
+:026BBF000000D4
+:026BC0000000D3
+:026BC1000000D2
+:026BC2000000D1
+:026BC3000000D0
+:026BC4000000CF
+:026BC5000000CE
+:026BC6000000CD
+:026BC7000000CC
+:026BC8000000CB
+:026BC9000000CA
+:026BCA000000C9
+:026BCB000000C8
+:026BCC000000C7
+:026BCD000000C6
+:026BCE000000C5
+:026BCF000000C4
+:026BD0000000C3
+:026BD1000000C2
+:026BD2000000C1
+:026BD3000000C0
+:026BD4000000BF
+:026BD5000000BE
+:026BD6000000BD
+:026BD7000000BC
+:026BD8000000BB
+:026BD9000000BA
+:026BDA000000B9
+:026BDB000000B8
+:026BDC000000B7
+:026BDD000000B6
+:026BDE000000B5
+:026BDF000000B4
+:026BE0000000B3
+:026BE1000000B2
+:026BE2000000B1
+:026BE3000000B0
+:026BE4000000AF
+:026BE5000000AE
+:026BE6000000AD
+:026BE7000000AC
+:026BE8000000AB
+:026BE9000000AA
+:026BEA000000A9
+:026BEB000000A8
+:026BEC000000A7
+:026BED000000A6
+:026BEE000000A5
+:026BEF000000A4
+:026BF0000000A3
+:026BF1000000A2
+:026BF2000000A1
+:026BF3000000A0
+:026BF40000009F
+:026BF50000009E
+:026BF60000009D
+:026BF70000009C
+:026BF80000009B
+:026BF90000009A
+:026BFA00000099
+:026BFB00000098
+:026BFC00000097
+:026BFD00000096
+:026BFE00000095
+:026BFF00000094
+:026C0000000092
+:026C0100000091
+:026C0200000090
+:026C030000008F
+:026C040000008E
+:026C050000008D
+:026C060000008C
+:026C070000008B
+:026C080000008A
+:026C0900000089
+:026C0A00000088
+:026C0B00000087
+:026C0C00000086
+:026C0D00000085
+:026C0E00000084
+:026C0F00000083
+:026C1000000082
+:026C1100000081
+:026C1200000080
+:026C130000007F
+:026C140000007E
+:026C150000007D
+:026C160000007C
+:026C170000007B
+:026C180000007A
+:026C1900000079
+:026C1A00000078
+:026C1B00000077
+:026C1C00000076
+:026C1D00000075
+:026C1E00000074
+:026C1F00000073
+:026C2000000072
+:026C2100000071
+:026C2200000070
+:026C230000006F
+:026C240000006E
+:026C250000006D
+:026C260000006C
+:026C270000006B
+:026C280000006A
+:026C2900000069
+:026C2A00000068
+:026C2B00000067
+:026C2C00000066
+:026C2D00000065
+:026C2E00000064
+:026C2F00000063
+:026C3000000062
+:026C3100000061
+:026C3200000060
+:026C330000005F
+:026C340000005E
+:026C350000005D
+:026C360000005C
+:026C370000005B
+:026C380000005A
+:026C3900000059
+:026C3A00000058
+:026C3B00000057
+:026C3C00000056
+:026C3D00000055
+:026C3E00000054
+:026C3F00000053
+:026C4000000052
+:026C4100000051
+:026C4200000050
+:026C430000004F
+:026C440000004E
+:026C450000004D
+:026C460000004C
+:026C470000004B
+:026C480000004A
+:026C4900000049
+:026C4A00000048
+:026C4B00000047
+:026C4C00000046
+:026C4D00000045
+:026C4E00000044
+:026C4F00000043
+:026C5000000042
+:026C5100000041
+:026C5200000040
+:026C530000003F
+:026C540000003E
+:026C550000003D
+:026C560000003C
+:026C570000003B
+:026C580000003A
+:026C5900000039
+:026C5A00000038
+:026C5B00000037
+:026C5C00000036
+:026C5D00000035
+:026C5E00000034
+:026C5F00000033
+:026C6000000032
+:026C6100000031
+:026C6200000030
+:026C630000002F
+:026C640000002E
+:026C650000002D
+:026C660000002C
+:026C670000002B
+:026C680000002A
+:026C6900000029
+:026C6A00000028
+:026C6B00000027
+:026C6C00000026
+:026C6D00000025
+:026C6E00000024
+:026C6F00000023
+:026C7000000022
+:026C7100000021
+:026C7200000020
+:026C730000001F
+:026C740000001E
+:026C750000001D
+:026C760000001C
+:026C770000001B
+:026C780000001A
+:026C7900000019
+:026C7A00000018
+:026C7B00000017
+:026C7C00000016
+:026C7D00000015
+:026C7E00000014
+:026C7F00000013
+:026C8000000012
+:026C8100000011
+:026C8200000010
+:026C830000000F
+:026C840000000E
+:026C850000000D
+:026C860000000C
+:026C870000000B
+:026C880000000A
+:026C8900000009
+:026C8A00000008
+:026C8B00000007
+:026C8C00000006
+:026C8D00000005
+:026C8E00000004
+:026C8F00000003
+:026C9000000002
+:026C9100000001
+:026C9200000000
+:026C93000000FF
+:026C94000000FE
+:026C95000000FD
+:026C96000000FC
+:026C97000000FB
+:026C98000000FA
+:026C99000000F9
+:026C9A000000F8
+:026C9B000000F7
+:026C9C000000F6
+:026C9D000000F5
+:026C9E000000F4
+:026C9F000000F3
+:026CA0000000F2
+:026CA1000000F1
+:026CA2000000F0
+:026CA3000000EF
+:026CA4000000EE
+:026CA5000000ED
+:026CA6000000EC
+:026CA7000000EB
+:026CA8000000EA
+:026CA9000000E9
+:026CAA000000E8
+:026CAB000000E7
+:026CAC000000E6
+:026CAD000000E5
+:026CAE000000E4
+:026CAF000000E3
+:026CB0000000E2
+:026CB1000000E1
+:026CB2000000E0
+:026CB3000000DF
+:026CB4000000DE
+:026CB5000000DD
+:026CB6000000DC
+:026CB7000000DB
+:026CB8000000DA
+:026CB9000000D9
+:026CBA000000D8
+:026CBB000000D7
+:026CBC000000D6
+:026CBD000000D5
+:026CBE000000D4
+:026CBF000000D3
+:026CC0000000D2
+:026CC1000000D1
+:026CC2000000D0
+:026CC3000000CF
+:026CC4000000CE
+:026CC5000000CD
+:026CC6000000CC
+:026CC7000000CB
+:026CC8000000CA
+:026CC9000000C9
+:026CCA000000C8
+:026CCB000000C7
+:026CCC000000C6
+:026CCD000000C5
+:026CCE000000C4
+:026CCF000000C3
+:026CD0000000C2
+:026CD1000000C1
+:026CD2000000C0
+:026CD3000000BF
+:026CD4000000BE
+:026CD5000000BD
+:026CD6000000BC
+:026CD7000000BB
+:026CD8000000BA
+:026CD9000000B9
+:026CDA000000B8
+:026CDB000000B7
+:026CDC000000B6
+:026CDD000000B5
+:026CDE000000B4
+:026CDF000000B3
+:026CE0000000B2
+:026CE1000000B1
+:026CE2000000B0
+:026CE3000000AF
+:026CE4000000AE
+:026CE5000000AD
+:026CE6000000AC
+:026CE7000000AB
+:026CE8000000AA
+:026CE9000000A9
+:026CEA000000A8
+:026CEB000000A7
+:026CEC000000A6
+:026CED000000A5
+:026CEE000000A4
+:026CEF000000A3
+:026CF0000000A2
+:026CF1000000A1
+:026CF2000000A0
+:026CF30000009F
+:026CF40000009E
+:026CF50000009D
+:026CF60000009C
+:026CF70000009B
+:026CF80000009A
+:026CF900000099
+:026CFA00000098
+:026CFB00000097
+:026CFC00000096
+:026CFD00000095
+:026CFE00000094
+:026CFF00000093
+:026D0000000091
+:026D0100000090
+:026D020000008F
+:026D030000008E
+:026D040000008D
+:026D050000008C
+:026D060000008B
+:026D070000008A
+:026D0800000089
+:026D0900000088
+:026D0A00000087
+:026D0B00000086
+:026D0C00000085
+:026D0D00000084
+:026D0E00000083
+:026D0F00000082
+:026D1000000081
+:026D1100000080
+:026D120000007F
+:026D130000007E
+:026D140000007D
+:026D150000007C
+:026D160000007B
+:026D170000007A
+:026D1800000079
+:026D1900000078
+:026D1A00000077
+:026D1B00000076
+:026D1C00000075
+:026D1D00000074
+:026D1E00000073
+:026D1F00000072
+:026D2000000071
+:026D2100000070
+:026D220000006F
+:026D230000006E
+:026D240000006D
+:026D250000006C
+:026D260000006B
+:026D270000006A
+:026D2800000069
+:026D2900000068
+:026D2A00000067
+:026D2B00000066
+:026D2C00000065
+:026D2D00000064
+:026D2E00000063
+:026D2F00000062
+:026D3000000061
+:026D3100000060
+:026D320000005F
+:026D330000005E
+:026D340000005D
+:026D350000005C
+:026D360000005B
+:026D370000005A
+:026D3800000059
+:026D3900000058
+:026D3A00000057
+:026D3B00000056
+:026D3C00000055
+:026D3D00000054
+:026D3E00000053
+:026D3F00000052
+:026D4000000051
+:026D4100000050
+:026D420000004F
+:026D430000004E
+:026D440000004D
+:026D450000004C
+:026D460000004B
+:026D470000004A
+:026D4800000049
+:026D4900000048
+:026D4A00000047
+:026D4B00000046
+:026D4C00000045
+:026D4D00000044
+:026D4E00000043
+:026D4F00000042
+:026D5000000041
+:026D5100000040
+:026D520000003F
+:026D530000003E
+:026D540000003D
+:026D550000003C
+:026D560000003B
+:026D570000003A
+:026D5800000039
+:026D5900000038
+:026D5A00000037
+:026D5B00000036
+:026D5C00000035
+:026D5D00000034
+:026D5E00000033
+:026D5F00000032
+:026D6000000031
+:026D6100000030
+:026D620000002F
+:026D630000002E
+:026D640000002D
+:026D650000002C
+:026D660000002B
+:026D670000002A
+:026D6800000029
+:026D6900000028
+:026D6A00000027
+:026D6B00000026
+:026D6C00000025
+:026D6D00000024
+:026D6E00000023
+:026D6F00000022
+:026D7000000021
+:026D7100000020
+:026D720000001F
+:026D730000001E
+:026D740000001D
+:026D750000001C
+:026D760000001B
+:026D770000001A
+:026D7800000019
+:026D7900000018
+:026D7A00000017
+:026D7B00000016
+:026D7C00000015
+:026D7D00000014
+:026D7E00000013
+:026D7F00000012
+:026D8000000011
+:026D8100000010
+:026D820000000F
+:026D830000000E
+:026D840000000D
+:026D850000000C
+:026D860000000B
+:026D870000000A
+:026D8800000009
+:026D8900000008
+:026D8A00000007
+:026D8B00000006
+:026D8C00000005
+:026D8D00000004
+:026D8E00000003
+:026D8F00000002
+:026D9000000001
+:026D9100000000
+:026D92000000FF
+:026D93000000FE
+:026D94000000FD
+:026D95000000FC
+:026D96000000FB
+:026D97000000FA
+:026D98000000F9
+:026D99000000F8
+:026D9A000000F7
+:026D9B000000F6
+:026D9C000000F5
+:026D9D000000F4
+:026D9E000000F3
+:026D9F000000F2
+:026DA0000000F1
+:026DA1000000F0
+:026DA2000000EF
+:026DA3000000EE
+:026DA4000000ED
+:026DA5000000EC
+:026DA6000000EB
+:026DA7000000EA
+:026DA8000000E9
+:026DA9000000E8
+:026DAA000000E7
+:026DAB000000E6
+:026DAC000000E5
+:026DAD000000E4
+:026DAE000000E3
+:026DAF000000E2
+:026DB0000000E1
+:026DB1000000E0
+:026DB2000000DF
+:026DB3000000DE
+:026DB4000000DD
+:026DB5000000DC
+:026DB6000000DB
+:026DB7000000DA
+:026DB8000000D9
+:026DB9000000D8
+:026DBA000000D7
+:026DBB000000D6
+:026DBC000000D5
+:026DBD000000D4
+:026DBE000000D3
+:026DBF000000D2
+:026DC0000000D1
+:026DC1000000D0
+:026DC2000000CF
+:026DC3000000CE
+:026DC4000000CD
+:026DC5000000CC
+:026DC6000000CB
+:026DC7000000CA
+:026DC8000000C9
+:026DC9000000C8
+:026DCA000000C7
+:026DCB000000C6
+:026DCC000000C5
+:026DCD000000C4
+:026DCE000000C3
+:026DCF000000C2
+:026DD0000000C1
+:026DD1000000C0
+:026DD2000000BF
+:026DD3000000BE
+:026DD4000000BD
+:026DD5000000BC
+:026DD6000000BB
+:026DD7000000BA
+:026DD8000000B9
+:026DD9000000B8
+:026DDA000000B7
+:026DDB000000B6
+:026DDC000000B5
+:026DDD000000B4
+:026DDE000000B3
+:026DDF000000B2
+:026DE0000000B1
+:026DE1000000B0
+:026DE2000000AF
+:026DE3000000AE
+:026DE4000000AD
+:026DE5000000AC
+:026DE6000000AB
+:026DE7000000AA
+:026DE8000000A9
+:026DE9000000A8
+:026DEA000000A7
+:026DEB000000A6
+:026DEC000000A5
+:026DED000000A4
+:026DEE000000A3
+:026DEF000000A2
+:026DF0000000A1
+:026DF1000000A0
+:026DF20000009F
+:026DF30000009E
+:026DF40000009D
+:026DF50000009C
+:026DF60000009B
+:026DF70000009A
+:026DF800000099
+:026DF900000098
+:026DFA00000097
+:026DFB00000096
+:026DFC00000095
+:026DFD00000094
+:026DFE00000093
+:026DFF00000092
+:026E0000000090
+:026E010000008F
+:026E020000008E
+:026E030000008D
+:026E040000008C
+:026E050000008B
+:026E060000008A
+:026E0700000089
+:026E0800000088
+:026E0900000087
+:026E0A00000086
+:026E0B00000085
+:026E0C00000084
+:026E0D00000083
+:026E0E00000082
+:026E0F00000081
+:026E1000000080
+:026E110000007F
+:026E120000007E
+:026E130000007D
+:026E140000007C
+:026E150000007B
+:026E160000007A
+:026E1700000079
+:026E1800000078
+:026E1900000077
+:026E1A00000076
+:026E1B00000075
+:026E1C00000074
+:026E1D00000073
+:026E1E00000072
+:026E1F00000071
+:026E2000000070
+:026E210000006F
+:026E220000006E
+:026E230000006D
+:026E240000006C
+:026E250000006B
+:026E260000006A
+:026E2700000069
+:026E2800000068
+:026E2900000067
+:026E2A00000066
+:026E2B00000065
+:026E2C00000064
+:026E2D00000063
+:026E2E00000062
+:026E2F00000061
+:026E3000000060
+:026E310000005F
+:026E320000005E
+:026E330000005D
+:026E340000005C
+:026E350000005B
+:026E360000005A
+:026E3700000059
+:026E3800000058
+:026E3900000057
+:026E3A00000056
+:026E3B00000055
+:026E3C00000054
+:026E3D00000053
+:026E3E00000052
+:026E3F00000051
+:026E4000000050
+:026E410000004F
+:026E420000004E
+:026E430000004D
+:026E440000004C
+:026E450000004B
+:026E460000004A
+:026E4700000049
+:026E4800000048
+:026E4900000047
+:026E4A00000046
+:026E4B00000045
+:026E4C00000044
+:026E4D00000043
+:026E4E00000042
+:026E4F00000041
+:026E5000000040
+:026E510000003F
+:026E520000003E
+:026E530000003D
+:026E540000003C
+:026E550000003B
+:026E560000003A
+:026E5700000039
+:026E5800000038
+:026E5900000037
+:026E5A00000036
+:026E5B00000035
+:026E5C00000034
+:026E5D00000033
+:026E5E00000032
+:026E5F00000031
+:026E6000000030
+:026E610000002F
+:026E620000002E
+:026E630000002D
+:026E640000002C
+:026E650000002B
+:026E660000002A
+:026E6700000029
+:026E6800000028
+:026E6900000027
+:026E6A00000026
+:026E6B00000025
+:026E6C00000024
+:026E6D00000023
+:026E6E00000022
+:026E6F00000021
+:026E7000000020
+:026E710000001F
+:026E720000001E
+:026E730000001D
+:026E740000001C
+:026E750000001B
+:026E760000001A
+:026E7700000019
+:026E7800000018
+:026E7900000017
+:026E7A00000016
+:026E7B00000015
+:026E7C00000014
+:026E7D00000013
+:026E7E00000012
+:026E7F00000011
+:026E8000000010
+:026E810000000F
+:026E820000000E
+:026E830000000D
+:026E840000000C
+:026E850000000B
+:026E860000000A
+:026E8700000009
+:026E8800000008
+:026E8900000007
+:026E8A00000006
+:026E8B00000005
+:026E8C00000004
+:026E8D00000003
+:026E8E00000002
+:026E8F00000001
+:026E9000000000
+:026E91000000FF
+:026E92000000FE
+:026E93000000FD
+:026E94000000FC
+:026E95000000FB
+:026E96000000FA
+:026E97000000F9
+:026E98000000F8
+:026E99000000F7
+:026E9A000000F6
+:026E9B000000F5
+:026E9C000000F4
+:026E9D000000F3
+:026E9E000000F2
+:026E9F000000F1
+:026EA0000000F0
+:026EA1000000EF
+:026EA2000000EE
+:026EA3000000ED
+:026EA4000000EC
+:026EA5000000EB
+:026EA6000000EA
+:026EA7000000E9
+:026EA8000000E8
+:026EA9000000E7
+:026EAA000000E6
+:026EAB000000E5
+:026EAC000000E4
+:026EAD000000E3
+:026EAE000000E2
+:026EAF000000E1
+:026EB0000000E0
+:026EB1000000DF
+:026EB2000000DE
+:026EB3000000DD
+:026EB4000000DC
+:026EB5000000DB
+:026EB6000000DA
+:026EB7000000D9
+:026EB8000000D8
+:026EB9000000D7
+:026EBA000000D6
+:026EBB000000D5
+:026EBC000000D4
+:026EBD000000D3
+:026EBE000000D2
+:026EBF000000D1
+:026EC0000000D0
+:026EC1000000CF
+:026EC2000000CE
+:026EC3000000CD
+:026EC4000000CC
+:026EC5000000CB
+:026EC6000000CA
+:026EC7000000C9
+:026EC8000000C8
+:026EC9000000C7
+:026ECA000000C6
+:026ECB000000C5
+:026ECC000000C4
+:026ECD000000C3
+:026ECE000000C2
+:026ECF000000C1
+:026ED0000000C0
+:026ED1000000BF
+:026ED2000000BE
+:026ED3000000BD
+:026ED4000000BC
+:026ED5000000BB
+:026ED6000000BA
+:026ED7000000B9
+:026ED8000000B8
+:026ED9000000B7
+:026EDA000000B6
+:026EDB000000B5
+:026EDC000000B4
+:026EDD000000B3
+:026EDE000000B2
+:026EDF000000B1
+:026EE0000000B0
+:026EE1000000AF
+:026EE2000000AE
+:026EE3000000AD
+:026EE4000000AC
+:026EE5000000AB
+:026EE6000000AA
+:026EE7000000A9
+:026EE8000000A8
+:026EE9000000A7
+:026EEA000000A6
+:026EEB000000A5
+:026EEC000000A4
+:026EED000000A3
+:026EEE000000A2
+:026EEF000000A1
+:026EF0000000A0
+:026EF10000009F
+:026EF20000009E
+:026EF30000009D
+:026EF40000009C
+:026EF50000009B
+:026EF60000009A
+:026EF700000099
+:026EF800000098
+:026EF900000097
+:026EFA00000096
+:026EFB00000095
+:026EFC00000094
+:026EFD00000093
+:026EFE00000092
+:026EFF00000091
+:026F000000008F
+:026F010000008E
+:026F020000008D
+:026F030000008C
+:026F040000008B
+:026F050000008A
+:026F0600000089
+:026F0700000088
+:026F0800000087
+:026F0900000086
+:026F0A00000085
+:026F0B00000084
+:026F0C00000083
+:026F0D00000082
+:026F0E00000081
+:026F0F00000080
+:026F100000007F
+:026F110000007E
+:026F120000007D
+:026F130000007C
+:026F140000007B
+:026F150000007A
+:026F1600000079
+:026F1700000078
+:026F1800000077
+:026F1900000076
+:026F1A00000075
+:026F1B00000074
+:026F1C00000073
+:026F1D00000072
+:026F1E00000071
+:026F1F00000070
+:026F200000006F
+:026F210000006E
+:026F220000006D
+:026F230000006C
+:026F240000006B
+:026F250000006A
+:026F2600000069
+:026F2700000068
+:026F2800000067
+:026F2900000066
+:026F2A00000065
+:026F2B00000064
+:026F2C00000063
+:026F2D00000062
+:026F2E00000061
+:026F2F00000060
+:026F300000005F
+:026F310000005E
+:026F320000005D
+:026F330000005C
+:026F340000005B
+:026F350000005A
+:026F3600000059
+:026F3700000058
+:026F3800000057
+:026F3900000056
+:026F3A00000055
+:026F3B00000054
+:026F3C00000053
+:026F3D00000052
+:026F3E00000051
+:026F3F00000050
+:026F400000004F
+:026F410000004E
+:026F420000004D
+:026F430000004C
+:026F440000004B
+:026F450000004A
+:026F4600000049
+:026F4700000048
+:026F4800000047
+:026F4900000046
+:026F4A00000045
+:026F4B00000044
+:026F4C00000043
+:026F4D00000042
+:026F4E00000041
+:026F4F00000040
+:026F500000003F
+:026F510000003E
+:026F520000003D
+:026F530000003C
+:026F540000003B
+:026F550000003A
+:026F5600000039
+:026F5700000038
+:026F5800000037
+:026F5900000036
+:026F5A00000035
+:026F5B00000034
+:026F5C00000033
+:026F5D00000032
+:026F5E00000031
+:026F5F00000030
+:026F600000002F
+:026F610000002E
+:026F620000002D
+:026F630000002C
+:026F640000002B
+:026F650000002A
+:026F6600000029
+:026F6700000028
+:026F6800000027
+:026F6900000026
+:026F6A00000025
+:026F6B00000024
+:026F6C00000023
+:026F6D00000022
+:026F6E00000021
+:026F6F00000020
+:026F700000001F
+:026F710000001E
+:026F720000001D
+:026F730000001C
+:026F740000001B
+:026F750000001A
+:026F7600000019
+:026F7700000018
+:026F7800000017
+:026F7900000016
+:026F7A00000015
+:026F7B00000014
+:026F7C00000013
+:026F7D00000012
+:026F7E00000011
+:026F7F00000010
+:026F800000000F
+:026F810000000E
+:026F820000000D
+:026F830000000C
+:026F840000000B
+:026F850000000A
+:026F8600000009
+:026F8700000008
+:026F8800000007
+:026F8900000006
+:026F8A00000005
+:026F8B00000004
+:026F8C00000003
+:026F8D00000002
+:026F8E00000001
+:026F8F00000000
+:026F90000000FF
+:026F91000000FE
+:026F92000000FD
+:026F93000000FC
+:026F94000000FB
+:026F95000000FA
+:026F96000000F9
+:026F97000000F8
+:026F98000000F7
+:026F99000000F6
+:026F9A000000F5
+:026F9B000000F4
+:026F9C000000F3
+:026F9D000000F2
+:026F9E000000F1
+:026F9F000000F0
+:026FA0000000EF
+:026FA1000000EE
+:026FA2000000ED
+:026FA3000000EC
+:026FA4000000EB
+:026FA5000000EA
+:026FA6000000E9
+:026FA7000000E8
+:026FA8000000E7
+:026FA9000000E6
+:026FAA000000E5
+:026FAB000000E4
+:026FAC000000E3
+:026FAD000000E2
+:026FAE000000E1
+:026FAF000000E0
+:026FB0000000DF
+:026FB1000000DE
+:026FB2000000DD
+:026FB3000000DC
+:026FB4000000DB
+:026FB5000000DA
+:026FB6000000D9
+:026FB7000000D8
+:026FB8000000D7
+:026FB9000000D6
+:026FBA000000D5
+:026FBB000000D4
+:026FBC000000D3
+:026FBD000000D2
+:026FBE000000D1
+:026FBF000000D0
+:026FC0000000CF
+:026FC1000000CE
+:026FC2000000CD
+:026FC3000000CC
+:026FC4000000CB
+:026FC5000000CA
+:026FC6000000C9
+:026FC7000000C8
+:026FC8000000C7
+:026FC9000000C6
+:026FCA000000C5
+:026FCB000000C4
+:026FCC000000C3
+:026FCD000000C2
+:026FCE000000C1
+:026FCF000000C0
+:026FD0000000BF
+:026FD1000000BE
+:026FD2000000BD
+:026FD3000000BC
+:026FD4000000BB
+:026FD5000000BA
+:026FD6000000B9
+:026FD7000000B8
+:026FD8000000B7
+:026FD9000000B6
+:026FDA000000B5
+:026FDB000000B4
+:026FDC000000B3
+:026FDD000000B2
+:026FDE000000B1
+:026FDF000000B0
+:026FE0000000AF
+:026FE1000000AE
+:026FE2000000AD
+:026FE3000000AC
+:026FE4000000AB
+:026FE5000000AA
+:026FE6000000A9
+:026FE7000000A8
+:026FE8000000A7
+:026FE9000000A6
+:026FEA000000A5
+:026FEB000000A4
+:026FEC000000A3
+:026FED000000A2
+:026FEE000000A1
+:026FEF000000A0
+:026FF00000009F
+:026FF10000009E
+:026FF20000009D
+:026FF30000009C
+:026FF40000009B
+:026FF50000009A
+:026FF600000099
+:026FF700000098
+:026FF800000097
+:026FF900000096
+:026FFA00000095
+:026FFB00000094
+:026FFC00000093
+:026FFD00000092
+:026FFE00000091
+:026FFF00000090
+:0270000000008E
+:0270010000008D
+:0270020000008C
+:0270030000008B
+:0270040000008A
+:02700500000089
+:02700600000088
+:02700700000087
+:02700800000086
+:02700900000085
+:02700A00000084
+:02700B00000083
+:02700C00000082
+:02700D00000081
+:02700E00000080
+:02700F0000007F
+:0270100000007E
+:0270110000007D
+:0270120000007C
+:0270130000007B
+:0270140000007A
+:02701500000079
+:02701600000078
+:02701700000077
+:02701800000076
+:02701900000075
+:02701A00000074
+:02701B00000073
+:02701C00000072
+:02701D00000071
+:02701E00000070
+:02701F0000006F
+:0270200000006E
+:0270210000006D
+:0270220000006C
+:0270230000006B
+:0270240000006A
+:02702500000069
+:02702600000068
+:02702700000067
+:02702800000066
+:02702900000065
+:02702A00000064
+:02702B00000063
+:02702C00000062
+:02702D00000061
+:02702E00000060
+:02702F0000005F
+:0270300000005E
+:0270310000005D
+:0270320000005C
+:0270330000005B
+:0270340000005A
+:02703500000059
+:02703600000058
+:02703700000057
+:02703800000056
+:02703900000055
+:02703A00000054
+:02703B00000053
+:02703C00000052
+:02703D00000051
+:02703E00000050
+:02703F0000004F
+:0270400000004E
+:0270410000004D
+:0270420000004C
+:0270430000004B
+:0270440000004A
+:02704500000049
+:02704600000048
+:02704700000047
+:02704800000046
+:02704900000045
+:02704A00000044
+:02704B00000043
+:02704C00000042
+:02704D00000041
+:02704E00000040
+:02704F0000003F
+:0270500000003E
+:0270510000003D
+:0270520000003C
+:0270530000003B
+:0270540000003A
+:02705500000039
+:02705600000038
+:02705700000037
+:02705800000036
+:02705900000035
+:02705A00000034
+:02705B00000033
+:02705C00000032
+:02705D00000031
+:02705E00000030
+:02705F0000002F
+:0270600000002E
+:0270610000002D
+:0270620000002C
+:0270630000002B
+:0270640000002A
+:02706500000029
+:02706600000028
+:02706700000027
+:02706800000026
+:02706900000025
+:02706A00000024
+:02706B00000023
+:02706C00000022
+:02706D00000021
+:02706E00000020
+:02706F0000001F
+:0270700000001E
+:0270710000001D
+:0270720000001C
+:0270730000001B
+:0270740000001A
+:02707500000019
+:02707600000018
+:02707700000017
+:02707800000016
+:02707900000015
+:02707A00000014
+:02707B00000013
+:02707C00000012
+:02707D00000011
+:02707E00000010
+:02707F0000000F
+:0270800000000E
+:0270810000000D
+:0270820000000C
+:0270830000000B
+:0270840000000A
+:02708500000009
+:02708600000008
+:02708700000007
+:02708800000006
+:02708900000005
+:02708A00000004
+:02708B00000003
+:02708C00000002
+:02708D00000001
+:02708E00000000
+:02708F000000FF
+:027090000000FE
+:027091000000FD
+:027092000000FC
+:027093000000FB
+:027094000000FA
+:027095000000F9
+:027096000000F8
+:027097000000F7
+:027098000000F6
+:027099000000F5
+:02709A000000F4
+:02709B000000F3
+:02709C000000F2
+:02709D000000F1
+:02709E000000F0
+:02709F000000EF
+:0270A0000000EE
+:0270A1000000ED
+:0270A2000000EC
+:0270A3000000EB
+:0270A4000000EA
+:0270A5000000E9
+:0270A6000000E8
+:0270A7000000E7
+:0270A8000000E6
+:0270A9000000E5
+:0270AA000000E4
+:0270AB000000E3
+:0270AC000000E2
+:0270AD000000E1
+:0270AE000000E0
+:0270AF000000DF
+:0270B0000000DE
+:0270B1000000DD
+:0270B2000000DC
+:0270B3000000DB
+:0270B4000000DA
+:0270B5000000D9
+:0270B6000000D8
+:0270B7000000D7
+:0270B8000000D6
+:0270B9000000D5
+:0270BA000000D4
+:0270BB000000D3
+:0270BC000000D2
+:0270BD000000D1
+:0270BE000000D0
+:0270BF000000CF
+:0270C0000000CE
+:0270C1000000CD
+:0270C2000000CC
+:0270C3000000CB
+:0270C4000000CA
+:0270C5000000C9
+:0270C6000000C8
+:0270C7000000C7
+:0270C8000000C6
+:0270C9000000C5
+:0270CA000000C4
+:0270CB000000C3
+:0270CC000000C2
+:0270CD000000C1
+:0270CE000000C0
+:0270CF000000BF
+:0270D0000000BE
+:0270D1000000BD
+:0270D2000000BC
+:0270D3000000BB
+:0270D4000000BA
+:0270D5000000B9
+:0270D6000000B8
+:0270D7000000B7
+:0270D8000000B6
+:0270D9000000B5
+:0270DA000000B4
+:0270DB000000B3
+:0270DC000000B2
+:0270DD000000B1
+:0270DE000000B0
+:0270DF000000AF
+:0270E0000000AE
+:0270E1000000AD
+:0270E2000000AC
+:0270E3000000AB
+:0270E4000000AA
+:0270E5000000A9
+:0270E6000000A8
+:0270E7000000A7
+:0270E8000000A6
+:0270E9000000A5
+:0270EA000000A4
+:0270EB000000A3
+:0270EC000000A2
+:0270ED000000A1
+:0270EE000000A0
+:0270EF0000009F
+:0270F00000009E
+:0270F10000009D
+:0270F20000009C
+:0270F30000009B
+:0270F40000009A
+:0270F500000099
+:0270F600000098
+:0270F700000097
+:0270F800000096
+:0270F900000095
+:0270FA00000094
+:0270FB00000093
+:0270FC00000092
+:0270FD00000091
+:0270FE00000090
+:0270FF0000008F
+:0271000000008D
+:0271010000008C
+:0271020000008B
+:0271030000008A
+:02710400000089
+:02710500000088
+:02710600000087
+:02710700000086
+:02710800000085
+:02710900000084
+:02710A00000083
+:02710B00000082
+:02710C00000081
+:02710D00000080
+:02710E0000007F
+:02710F0000007E
+:0271100000007D
+:0271110000007C
+:0271120000007B
+:0271130000007A
+:02711400000079
+:02711500000078
+:02711600000077
+:02711700000076
+:02711800000075
+:02711900000074
+:02711A00000073
+:02711B00000072
+:02711C00000071
+:02711D00000070
+:02711E0000006F
+:02711F0000006E
+:0271200000006D
+:0271210000006C
+:0271220000006B
+:0271230000006A
+:02712400000069
+:02712500000068
+:02712600000067
+:02712700000066
+:02712800000065
+:02712900000064
+:02712A00000063
+:02712B00000062
+:02712C00000061
+:02712D00000060
+:02712E0000005F
+:02712F0000005E
+:0271300000005D
+:0271310000005C
+:0271320000005B
+:0271330000005A
+:02713400000059
+:02713500000058
+:02713600000057
+:02713700000056
+:02713800000055
+:02713900000054
+:02713A00000053
+:02713B00000052
+:02713C00000051
+:02713D00000050
+:02713E0000004F
+:02713F0000004E
+:0271400000004D
+:0271410000004C
+:0271420000004B
+:0271430000004A
+:02714400000049
+:02714500000048
+:02714600000047
+:02714700000046
+:02714800000045
+:02714900000044
+:02714A00000043
+:02714B00000042
+:02714C00000041
+:02714D00000040
+:02714E0000003F
+:02714F0000003E
+:0271500000003D
+:0271510000003C
+:0271520000003B
+:0271530000003A
+:02715400000039
+:02715500000038
+:02715600000037
+:02715700000036
+:02715800000035
+:02715900000034
+:02715A00000033
+:02715B00000032
+:02715C00000031
+:02715D00000030
+:02715E0000002F
+:02715F0000002E
+:0271600000002D
+:0271610000002C
+:0271620000002B
+:0271630000002A
+:02716400000029
+:02716500000028
+:02716600000027
+:02716700000026
+:02716800000025
+:02716900000024
+:02716A00000023
+:02716B00000022
+:02716C00000021
+:02716D00000020
+:02716E0000001F
+:02716F0000001E
+:0271700000001D
+:0271710000001C
+:0271720000001B
+:0271730000001A
+:02717400000019
+:02717500000018
+:02717600000017
+:02717700000016
+:02717800000015
+:02717900000014
+:02717A00000013
+:02717B00000012
+:02717C00000011
+:02717D00000010
+:02717E0000000F
+:02717F0000000E
+:0271800000000D
+:0271810000000C
+:0271820000000B
+:0271830000000A
+:02718400000009
+:02718500000008
+:02718600000007
+:02718700000006
+:02718800000005
+:02718900000004
+:02718A00000003
+:02718B00000002
+:02718C00000001
+:02718D00000000
+:02718E000000FF
+:02718F000000FE
+:027190000000FD
+:027191000000FC
+:027192000000FB
+:027193000000FA
+:027194000000F9
+:027195000000F8
+:027196000000F7
+:027197000000F6
+:027198000000F5
+:027199000000F4
+:02719A000000F3
+:02719B000000F2
+:02719C000000F1
+:02719D000000F0
+:02719E000000EF
+:02719F000000EE
+:0271A0000000ED
+:0271A1000000EC
+:0271A2000000EB
+:0271A3000000EA
+:0271A4000000E9
+:0271A5000000E8
+:0271A6000000E7
+:0271A7000000E6
+:0271A8000000E5
+:0271A9000000E4
+:0271AA000000E3
+:0271AB000000E2
+:0271AC000000E1
+:0271AD000000E0
+:0271AE000000DF
+:0271AF000000DE
+:0271B0000000DD
+:0271B1000000DC
+:0271B2000000DB
+:0271B3000000DA
+:0271B4000000D9
+:0271B5000000D8
+:0271B6000000D7
+:0271B7000000D6
+:0271B8000000D5
+:0271B9000000D4
+:0271BA000000D3
+:0271BB000000D2
+:0271BC000000D1
+:0271BD000000D0
+:0271BE000000CF
+:0271BF000000CE
+:0271C0000000CD
+:0271C1000000CC
+:0271C2000000CB
+:0271C3000000CA
+:0271C4000000C9
+:0271C5000000C8
+:0271C6000000C7
+:0271C7000000C6
+:0271C8000000C5
+:0271C9000000C4
+:0271CA000000C3
+:0271CB000000C2
+:0271CC000000C1
+:0271CD000000C0
+:0271CE000000BF
+:0271CF000000BE
+:0271D0000000BD
+:0271D1000000BC
+:0271D2000000BB
+:0271D3000000BA
+:0271D4000000B9
+:0271D5000000B8
+:0271D6000000B7
+:0271D7000000B6
+:0271D8000000B5
+:0271D9000000B4
+:0271DA000000B3
+:0271DB000000B2
+:0271DC000000B1
+:0271DD000000B0
+:0271DE000000AF
+:0271DF000000AE
+:0271E0000000AD
+:0271E1000000AC
+:0271E2000000AB
+:0271E3000000AA
+:0271E4000000A9
+:0271E5000000A8
+:0271E6000000A7
+:0271E7000000A6
+:0271E8000000A5
+:0271E9000000A4
+:0271EA000000A3
+:0271EB000000A2
+:0271EC000000A1
+:0271ED000000A0
+:0271EE0000009F
+:0271EF0000009E
+:0271F00000009D
+:0271F10000009C
+:0271F20000009B
+:0271F30000009A
+:0271F400000099
+:0271F500000098
+:0271F600000097
+:0271F700000096
+:0271F800000095
+:0271F900000094
+:0271FA00000093
+:0271FB00000092
+:0271FC00000091
+:0271FD00000090
+:0271FE0000008F
+:0271FF0000008E
+:0272000000008C
+:0272010000008B
+:0272020000008A
+:02720300000089
+:02720400000088
+:02720500000087
+:02720600000086
+:02720700000085
+:02720800000084
+:02720900000083
+:02720A00000082
+:02720B00000081
+:02720C00000080
+:02720D0000007F
+:02720E0000007E
+:02720F0000007D
+:0272100000007C
+:0272110000007B
+:0272120000007A
+:02721300000079
+:02721400000078
+:02721500000077
+:02721600000076
+:02721700000075
+:02721800000074
+:02721900000073
+:02721A00000072
+:02721B00000071
+:02721C00000070
+:02721D0000006F
+:02721E0000006E
+:02721F0000006D
+:0272200000006C
+:0272210000006B
+:0272220000006A
+:02722300000069
+:02722400000068
+:02722500000067
+:02722600000066
+:02722700000065
+:02722800000064
+:02722900000063
+:02722A00000062
+:02722B00000061
+:02722C00000060
+:02722D0000005F
+:02722E0000005E
+:02722F0000005D
+:0272300000005C
+:0272310000005B
+:0272320000005A
+:02723300000059
+:02723400000058
+:02723500000057
+:02723600000056
+:02723700000055
+:02723800000054
+:02723900000053
+:02723A00000052
+:02723B00000051
+:02723C00000050
+:02723D0000004F
+:02723E0000004E
+:02723F0000004D
+:0272400000004C
+:0272410000004B
+:0272420000004A
+:02724300000049
+:02724400000048
+:02724500000047
+:02724600000046
+:02724700000045
+:02724800000044
+:02724900000043
+:02724A00000042
+:02724B00000041
+:02724C00000040
+:02724D0000003F
+:02724E0000003E
+:02724F0000003D
+:0272500000003C
+:0272510000003B
+:0272520000003A
+:02725300000039
+:02725400000038
+:02725500000037
+:02725600000036
+:02725700000035
+:02725800000034
+:02725900000033
+:02725A00000032
+:02725B00000031
+:02725C00000030
+:02725D0000002F
+:02725E0000002E
+:02725F0000002D
+:0272600000002C
+:0272610000002B
+:0272620000002A
+:02726300000029
+:02726400000028
+:02726500000027
+:02726600000026
+:02726700000025
+:02726800000024
+:02726900000023
+:02726A00000022
+:02726B00000021
+:02726C00000020
+:02726D0000001F
+:02726E0000001E
+:02726F0000001D
+:0272700000001C
+:0272710000001B
+:0272720000001A
+:02727300000019
+:02727400000018
+:02727500000017
+:02727600000016
+:02727700000015
+:02727800000014
+:02727900000013
+:02727A00000012
+:02727B00000011
+:02727C00000010
+:02727D0000000F
+:02727E0000000E
+:02727F0000000D
+:0272800000000C
+:0272810000000B
+:0272820000000A
+:02728300000009
+:02728400000008
+:02728500000007
+:02728600000006
+:02728700000005
+:02728800000004
+:02728900000003
+:02728A00000002
+:02728B00000001
+:02728C00000000
+:02728D000000FF
+:02728E000000FE
+:02728F000000FD
+:027290000000FC
+:027291000000FB
+:027292000000FA
+:027293000000F9
+:027294000000F8
+:027295000000F7
+:027296000000F6
+:027297000000F5
+:027298000000F4
+:027299000000F3
+:02729A000000F2
+:02729B000000F1
+:02729C000000F0
+:02729D000000EF
+:02729E000000EE
+:02729F000000ED
+:0272A0000000EC
+:0272A1000000EB
+:0272A2000000EA
+:0272A3000000E9
+:0272A4000000E8
+:0272A5000000E7
+:0272A6000000E6
+:0272A7000000E5
+:0272A8000000E4
+:0272A9000000E3
+:0272AA000000E2
+:0272AB000000E1
+:0272AC000000E0
+:0272AD000000DF
+:0272AE000000DE
+:0272AF000000DD
+:0272B0000000DC
+:0272B1000000DB
+:0272B2000000DA
+:0272B3000000D9
+:0272B4000000D8
+:0272B5000000D7
+:0272B6000000D6
+:0272B7000000D5
+:0272B8000000D4
+:0272B9000000D3
+:0272BA000000D2
+:0272BB000000D1
+:0272BC000000D0
+:0272BD000000CF
+:0272BE000000CE
+:0272BF000000CD
+:0272C0000000CC
+:0272C1000000CB
+:0272C2000000CA
+:0272C3000000C9
+:0272C4000000C8
+:0272C5000000C7
+:0272C6000000C6
+:0272C7000000C5
+:0272C8000000C4
+:0272C9000000C3
+:0272CA000000C2
+:0272CB000000C1
+:0272CC000000C0
+:0272CD000000BF
+:0272CE000000BE
+:0272CF000000BD
+:0272D0000000BC
+:0272D1000000BB
+:0272D2000000BA
+:0272D3000000B9
+:0272D4000000B8
+:0272D5000000B7
+:0272D6000000B6
+:0272D7000000B5
+:0272D8000000B4
+:0272D9000000B3
+:0272DA000000B2
+:0272DB000000B1
+:0272DC000000B0
+:0272DD000000AF
+:0272DE000000AE
+:0272DF000000AD
+:0272E0000000AC
+:0272E1000000AB
+:0272E2000000AA
+:0272E3000000A9
+:0272E4000000A8
+:0272E5000000A7
+:0272E6000000A6
+:0272E7000000A5
+:0272E8000000A4
+:0272E9000000A3
+:0272EA000000A2
+:0272EB000000A1
+:0272EC000000A0
+:0272ED0000009F
+:0272EE0000009E
+:0272EF0000009D
+:0272F00000009C
+:0272F10000009B
+:0272F20000009A
+:0272F300000099
+:0272F400000098
+:0272F500000097
+:0272F600000096
+:0272F700000095
+:0272F800000094
+:0272F900000093
+:0272FA00000092
+:0272FB00000091
+:0272FC00000090
+:0272FD0000008F
+:0272FE0000008E
+:0272FF0000008D
+:0273000000008B
+:0273010000008A
+:02730200000089
+:02730300000088
+:02730400000087
+:02730500000086
+:02730600000085
+:02730700000084
+:02730800000083
+:02730900000082
+:02730A00000081
+:02730B00000080
+:02730C0000007F
+:02730D0000007E
+:02730E0000007D
+:02730F0000007C
+:0273100000007B
+:0273110000007A
+:02731200000079
+:02731300000078
+:02731400000077
+:02731500000076
+:02731600000075
+:02731700000074
+:02731800000073
+:02731900000072
+:02731A00000071
+:02731B00000070
+:02731C0000006F
+:02731D0000006E
+:02731E0000006D
+:02731F0000006C
+:0273200000006B
+:0273210000006A
+:02732200000069
+:02732300000068
+:02732400000067
+:02732500000066
+:02732600000065
+:02732700000064
+:02732800000063
+:02732900000062
+:02732A00000061
+:02732B00000060
+:02732C0000005F
+:02732D0000005E
+:02732E0000005D
+:02732F0000005C
+:0273300000005B
+:0273310000005A
+:02733200000059
+:02733300000058
+:02733400000057
+:02733500000056
+:02733600000055
+:02733700000054
+:02733800000053
+:02733900000052
+:02733A00000051
+:02733B00000050
+:02733C0000004F
+:02733D0000004E
+:02733E0000004D
+:02733F0000004C
+:0273400000004B
+:0273410000004A
+:02734200000049
+:02734300000048
+:02734400000047
+:02734500000046
+:02734600000045
+:02734700000044
+:02734800000043
+:02734900000042
+:02734A00000041
+:02734B00000040
+:02734C0000003F
+:02734D0000003E
+:02734E0000003D
+:02734F0000003C
+:0273500000003B
+:0273510000003A
+:02735200000039
+:02735300000038
+:02735400000037
+:02735500000036
+:02735600000035
+:02735700000034
+:02735800000033
+:02735900000032
+:02735A00000031
+:02735B00000030
+:02735C0000002F
+:02735D0000002E
+:02735E0000002D
+:02735F0000002C
+:0273600000002B
+:0273610000002A
+:02736200000029
+:02736300000028
+:02736400000027
+:02736500000026
+:02736600000025
+:02736700000024
+:02736800000023
+:02736900000022
+:02736A00000021
+:02736B00000020
+:02736C0000001F
+:02736D0000001E
+:02736E0000001D
+:02736F0000001C
+:0273700000001B
+:0273710000001A
+:02737200000019
+:02737300000018
+:02737400000017
+:02737500000016
+:02737600000015
+:02737700000014
+:02737800000013
+:02737900000012
+:02737A00000011
+:02737B00000010
+:02737C0000000F
+:02737D0000000E
+:02737E0000000D
+:02737F0000000C
+:0273800000000B
+:0273810000000A
+:02738200000009
+:02738300000008
+:02738400000007
+:02738500000006
+:02738600000005
+:02738700000004
+:02738800000003
+:02738900000002
+:02738A00000001
+:02738B00000000
+:02738C000000FF
+:02738D000000FE
+:02738E000000FD
+:02738F000000FC
+:027390000000FB
+:027391000000FA
+:027392000000F9
+:027393000000F8
+:027394000000F7
+:027395000000F6
+:027396000000F5
+:027397000000F4
+:027398000000F3
+:027399000000F2
+:02739A000000F1
+:02739B000000F0
+:02739C000000EF
+:02739D000000EE
+:02739E000000ED
+:02739F000000EC
+:0273A0000000EB
+:0273A1000000EA
+:0273A2000000E9
+:0273A3000000E8
+:0273A4000000E7
+:0273A5000000E6
+:0273A6000000E5
+:0273A7000000E4
+:0273A8000000E3
+:0273A9000000E2
+:0273AA000000E1
+:0273AB000000E0
+:0273AC000000DF
+:0273AD000000DE
+:0273AE000000DD
+:0273AF000000DC
+:0273B0000000DB
+:0273B1000000DA
+:0273B2000000D9
+:0273B3000000D8
+:0273B4000000D7
+:0273B5000000D6
+:0273B6000000D5
+:0273B7000000D4
+:0273B8000000D3
+:0273B9000000D2
+:0273BA000000D1
+:0273BB000000D0
+:0273BC000000CF
+:0273BD000000CE
+:0273BE000000CD
+:0273BF000000CC
+:0273C0000000CB
+:0273C1000000CA
+:0273C2000000C9
+:0273C3000000C8
+:0273C4000000C7
+:0273C5000000C6
+:0273C6000000C5
+:0273C7000000C4
+:0273C8000000C3
+:0273C9000000C2
+:0273CA000000C1
+:0273CB000000C0
+:0273CC000000BF
+:0273CD000000BE
+:0273CE000000BD
+:0273CF000000BC
+:0273D0000000BB
+:0273D1000000BA
+:0273D2000000B9
+:0273D3000000B8
+:0273D4000000B7
+:0273D5000000B6
+:0273D6000000B5
+:0273D7000000B4
+:0273D8000000B3
+:0273D9000000B2
+:0273DA000000B1
+:0273DB000000B0
+:0273DC000000AF
+:0273DD000000AE
+:0273DE000000AD
+:0273DF000000AC
+:0273E0000000AB
+:0273E1000000AA
+:0273E2000000A9
+:0273E3000000A8
+:0273E4000000A7
+:0273E5000000A6
+:0273E6000000A5
+:0273E7000000A4
+:0273E8000000A3
+:0273E9000000A2
+:0273EA000000A1
+:0273EB000000A0
+:0273EC0000009F
+:0273ED0000009E
+:0273EE0000009D
+:0273EF0000009C
+:0273F00000009B
+:0273F10000009A
+:0273F200000099
+:0273F300000098
+:0273F400000097
+:0273F500000096
+:0273F600000095
+:0273F700000094
+:0273F800000093
+:0273F900000092
+:0273FA00000091
+:0273FB00000090
+:0273FC0000008F
+:0273FD0000008E
+:0273FE0000008D
+:0273FF0000008C
+:0274000000008A
+:02740100000089
+:02740200000088
+:02740300000087
+:02740400000086
+:02740500000085
+:02740600000084
+:02740700000083
+:02740800000082
+:02740900000081
+:02740A00000080
+:02740B0000007F
+:02740C0000007E
+:02740D0000007D
+:02740E0000007C
+:02740F0000007B
+:0274100000007A
+:02741100000079
+:02741200000078
+:02741300000077
+:02741400000076
+:02741500000075
+:02741600000074
+:02741700000073
+:02741800000072
+:02741900000071
+:02741A00000070
+:02741B0000006F
+:02741C0000006E
+:02741D0000006D
+:02741E0000006C
+:02741F0000006B
+:0274200000006A
+:02742100000069
+:02742200000068
+:02742300000067
+:02742400000066
+:02742500000065
+:02742600000064
+:02742700000063
+:02742800000062
+:02742900000061
+:02742A00000060
+:02742B0000005F
+:02742C0000005E
+:02742D0000005D
+:02742E0000005C
+:02742F0000005B
+:0274300000005A
+:02743100000059
+:02743200000058
+:02743300000057
+:02743400000056
+:02743500000055
+:02743600000054
+:02743700000053
+:02743800000052
+:02743900000051
+:02743A00000050
+:02743B0000004F
+:02743C0000004E
+:02743D0000004D
+:02743E0000004C
+:02743F0000004B
+:0274400000004A
+:02744100000049
+:02744200000048
+:02744300000047
+:02744400000046
+:02744500000045
+:02744600000044
+:02744700000043
+:02744800000042
+:02744900000041
+:02744A00000040
+:02744B0000003F
+:02744C0000003E
+:02744D0000003D
+:02744E0000003C
+:02744F0000003B
+:0274500000003A
+:02745100000039
+:02745200000038
+:02745300000037
+:02745400000036
+:02745500000035
+:02745600000034
+:02745700000033
+:02745800000032
+:02745900000031
+:02745A00000030
+:02745B0000002F
+:02745C0000002E
+:02745D0000002D
+:02745E0000002C
+:02745F0000002B
+:0274600000002A
+:02746100000029
+:02746200000028
+:02746300000027
+:02746400000026
+:02746500000025
+:02746600000024
+:02746700000023
+:02746800000022
+:02746900000021
+:02746A00000020
+:02746B0000001F
+:02746C0000001E
+:02746D0000001D
+:02746E0000001C
+:02746F0000001B
+:0274700000001A
+:02747100000019
+:02747200000018
+:02747300000017
+:02747400000016
+:02747500000015
+:02747600000014
+:02747700000013
+:02747800000012
+:02747900000011
+:02747A00000010
+:02747B0000000F
+:02747C0000000E
+:02747D0000000D
+:02747E0000000C
+:02747F0000000B
+:0274800000000A
+:02748100000009
+:02748200000008
+:02748300000007
+:02748400000006
+:02748500000005
+:02748600000004
+:02748700000003
+:02748800000002
+:02748900000001
+:02748A00000000
+:02748B000000FF
+:02748C000000FE
+:02748D000000FD
+:02748E000000FC
+:02748F000000FB
+:027490000000FA
+:027491000000F9
+:027492000000F8
+:027493000000F7
+:027494000000F6
+:027495000000F5
+:027496000000F4
+:027497000000F3
+:027498000000F2
+:027499000000F1
+:02749A000000F0
+:02749B000000EF
+:02749C000000EE
+:02749D000000ED
+:02749E000000EC
+:02749F000000EB
+:0274A0000000EA
+:0274A1000000E9
+:0274A2000000E8
+:0274A3000000E7
+:0274A4000000E6
+:0274A5000000E5
+:0274A6000000E4
+:0274A7000000E3
+:0274A8000000E2
+:0274A9000000E1
+:0274AA000000E0
+:0274AB000000DF
+:0274AC000000DE
+:0274AD000000DD
+:0274AE000000DC
+:0274AF000000DB
+:0274B0000000DA
+:0274B1000000D9
+:0274B2000000D8
+:0274B3000000D7
+:0274B4000000D6
+:0274B5000000D5
+:0274B6000000D4
+:0274B7000000D3
+:0274B8000000D2
+:0274B9000000D1
+:0274BA000000D0
+:0274BB000000CF
+:0274BC000000CE
+:0274BD000000CD
+:0274BE000000CC
+:0274BF000000CB
+:0274C0000000CA
+:0274C1000000C9
+:0274C2000000C8
+:0274C3000000C7
+:0274C4000000C6
+:0274C5000000C5
+:0274C6000000C4
+:0274C7000000C3
+:0274C8000000C2
+:0274C9000000C1
+:0274CA000000C0
+:0274CB000000BF
+:0274CC000000BE
+:0274CD000000BD
+:0274CE000000BC
+:0274CF000000BB
+:0274D0000000BA
+:0274D1000000B9
+:0274D2000000B8
+:0274D3000000B7
+:0274D4000000B6
+:0274D5000000B5
+:0274D6000000B4
+:0274D7000000B3
+:0274D8000000B2
+:0274D9000000B1
+:0274DA000000B0
+:0274DB000000AF
+:0274DC000000AE
+:0274DD000000AD
+:0274DE000000AC
+:0274DF000000AB
+:0274E0000000AA
+:0274E1000000A9
+:0274E2000000A8
+:0274E3000000A7
+:0274E4000000A6
+:0274E5000000A5
+:0274E6000000A4
+:0274E7000000A3
+:0274E8000000A2
+:0274E9000000A1
+:0274EA000000A0
+:0274EB0000009F
+:0274EC0000009E
+:0274ED0000009D
+:0274EE0000009C
+:0274EF0000009B
+:0274F00000009A
+:0274F100000099
+:0274F200000098
+:0274F300000097
+:0274F400000096
+:0274F500000095
+:0274F600000094
+:0274F700000093
+:0274F800000092
+:0274F900000091
+:0274FA00000090
+:0274FB0000008F
+:0274FC0000008E
+:0274FD0000008D
+:0274FE0000008C
+:0274FF0000008B
+:02750000000089
+:02750100000088
+:02750200000087
+:02750300000086
+:02750400000085
+:02750500000084
+:02750600000083
+:02750700000082
+:02750800000081
+:02750900000080
+:02750A0000007F
+:02750B0000007E
+:02750C0000007D
+:02750D0000007C
+:02750E0000007B
+:02750F0000007A
+:02751000000079
+:02751100000078
+:02751200000077
+:02751300000076
+:02751400000075
+:02751500000074
+:02751600000073
+:02751700000072
+:02751800000071
+:02751900000070
+:02751A0000006F
+:02751B0000006E
+:02751C0000006D
+:02751D0000006C
+:02751E0000006B
+:02751F0000006A
+:02752000000069
+:02752100000068
+:02752200000067
+:02752300000066
+:02752400000065
+:02752500000064
+:02752600000063
+:02752700000062
+:02752800000061
+:02752900000060
+:02752A0000005F
+:02752B0000005E
+:02752C0000005D
+:02752D0000005C
+:02752E0000005B
+:02752F0000005A
+:02753000000059
+:02753100000058
+:02753200000057
+:02753300000056
+:02753400000055
+:02753500000054
+:02753600000053
+:02753700000052
+:02753800000051
+:02753900000050
+:02753A0000004F
+:02753B0000004E
+:02753C0000004D
+:02753D0000004C
+:02753E0000004B
+:02753F0000004A
+:02754000000049
+:02754100000048
+:02754200000047
+:02754300000046
+:02754400000045
+:02754500000044
+:02754600000043
+:02754700000042
+:02754800000041
+:02754900000040
+:02754A0000003F
+:02754B0000003E
+:02754C0000003D
+:02754D0000003C
+:02754E0000003B
+:02754F0000003A
+:02755000000039
+:02755100000038
+:02755200000037
+:02755300000036
+:02755400000035
+:02755500000034
+:02755600000033
+:02755700000032
+:02755800000031
+:02755900000030
+:02755A0000002F
+:02755B0000002E
+:02755C0000002D
+:02755D0000002C
+:02755E0000002B
+:02755F0000002A
+:02756000000029
+:02756100000028
+:02756200000027
+:02756300000026
+:02756400000025
+:02756500000024
+:02756600000023
+:02756700000022
+:02756800000021
+:02756900000020
+:02756A0000001F
+:02756B0000001E
+:02756C0000001D
+:02756D0000001C
+:02756E0000001B
+:02756F0000001A
+:02757000000019
+:02757100000018
+:02757200000017
+:02757300000016
+:02757400000015
+:02757500000014
+:02757600000013
+:02757700000012
+:02757800000011
+:02757900000010
+:02757A0000000F
+:02757B0000000E
+:02757C0000000D
+:02757D0000000C
+:02757E0000000B
+:02757F0000000A
+:02758000000009
+:02758100000008
+:02758200000007
+:02758300000006
+:02758400000005
+:02758500000004
+:02758600000003
+:02758700000002
+:02758800000001
+:02758900000000
+:02758A000000FF
+:02758B000000FE
+:02758C000000FD
+:02758D000000FC
+:02758E000000FB
+:02758F000000FA
+:027590000000F9
+:027591000000F8
+:027592000000F7
+:027593000000F6
+:027594000000F5
+:027595000000F4
+:027596000000F3
+:027597000000F2
+:027598000000F1
+:027599000000F0
+:02759A000000EF
+:02759B000000EE
+:02759C000000ED
+:02759D000000EC
+:02759E000000EB
+:02759F000000EA
+:0275A0000000E9
+:0275A1000000E8
+:0275A2000000E7
+:0275A3000000E6
+:0275A4000000E5
+:0275A5000000E4
+:0275A6000000E3
+:0275A7000000E2
+:0275A8000000E1
+:0275A9000000E0
+:0275AA000000DF
+:0275AB000000DE
+:0275AC000000DD
+:0275AD000000DC
+:0275AE000000DB
+:0275AF000000DA
+:0275B0000000D9
+:0275B1000000D8
+:0275B2000000D7
+:0275B3000000D6
+:0275B4000000D5
+:0275B5000000D4
+:0275B6000000D3
+:0275B7000000D2
+:0275B8000000D1
+:0275B9000000D0
+:0275BA000000CF
+:0275BB000000CE
+:0275BC000000CD
+:0275BD000000CC
+:0275BE000000CB
+:0275BF000000CA
+:0275C0000000C9
+:0275C1000000C8
+:0275C2000000C7
+:0275C3000000C6
+:0275C4000000C5
+:0275C5000000C4
+:0275C6000000C3
+:0275C7000000C2
+:0275C8000000C1
+:0275C9000000C0
+:0275CA000000BF
+:0275CB000000BE
+:0275CC000000BD
+:0275CD000000BC
+:0275CE000000BB
+:0275CF000000BA
+:0275D0000000B9
+:0275D1000000B8
+:0275D2000000B7
+:0275D3000000B6
+:0275D4000000B5
+:0275D5000000B4
+:0275D6000000B3
+:0275D7000000B2
+:0275D8000000B1
+:0275D9000000B0
+:0275DA000000AF
+:0275DB000000AE
+:0275DC000000AD
+:0275DD000000AC
+:0275DE000000AB
+:0275DF000000AA
+:0275E0000000A9
+:0275E1000000A8
+:0275E2000000A7
+:0275E3000000A6
+:0275E4000000A5
+:0275E5000000A4
+:0275E6000000A3
+:0275E7000000A2
+:0275E8000000A1
+:0275E9000000A0
+:0275EA0000009F
+:0275EB0000009E
+:0275EC0000009D
+:0275ED0000009C
+:0275EE0000009B
+:0275EF0000009A
+:0275F000000099
+:0275F100000098
+:0275F200000097
+:0275F300000096
+:0275F400000095
+:0275F500000094
+:0275F600000093
+:0275F700000092
+:0275F800000091
+:0275F900000090
+:0275FA0000008F
+:0275FB0000008E
+:0275FC0000008D
+:0275FD0000008C
+:0275FE0000008B
+:0275FF0000008A
+:02760000000088
+:02760100000087
+:02760200000086
+:02760300000085
+:02760400000084
+:02760500000083
+:02760600000082
+:02760700000081
+:02760800000080
+:0276090000007F
+:02760A0000007E
+:02760B0000007D
+:02760C0000007C
+:02760D0000007B
+:02760E0000007A
+:02760F00000079
+:02761000000078
+:02761100000077
+:02761200000076
+:02761300000075
+:02761400000074
+:02761500000073
+:02761600000072
+:02761700000071
+:02761800000070
+:0276190000006F
+:02761A0000006E
+:02761B0000006D
+:02761C0000006C
+:02761D0000006B
+:02761E0000006A
+:02761F00000069
+:02762000000068
+:02762100000067
+:02762200000066
+:02762300000065
+:02762400000064
+:02762500000063
+:02762600000062
+:02762700000061
+:02762800000060
+:0276290000005F
+:02762A0000005E
+:02762B0000005D
+:02762C0000005C
+:02762D0000005B
+:02762E0000005A
+:02762F00000059
+:02763000000058
+:02763100000057
+:02763200000056
+:02763300000055
+:02763400000054
+:02763500000053
+:02763600000052
+:02763700000051
+:02763800000050
+:0276390000004F
+:02763A0000004E
+:02763B0000004D
+:02763C0000004C
+:02763D0000004B
+:02763E0000004A
+:02763F00000049
+:02764000000048
+:02764100000047
+:02764200000046
+:02764300000045
+:02764400000044
+:02764500000043
+:02764600000042
+:02764700000041
+:02764800000040
+:0276490000003F
+:02764A0000003E
+:02764B0000003D
+:02764C0000003C
+:02764D0000003B
+:02764E0000003A
+:02764F00000039
+:02765000000038
+:02765100000037
+:02765200000036
+:02765300000035
+:02765400000034
+:02765500000033
+:02765600000032
+:02765700000031
+:02765800000030
+:0276590000002F
+:02765A0000002E
+:02765B0000002D
+:02765C0000002C
+:02765D0000002B
+:02765E0000002A
+:02765F00000029
+:02766000000028
+:02766100000027
+:02766200000026
+:02766300000025
+:02766400000024
+:02766500000023
+:02766600000022
+:02766700000021
+:02766800000020
+:0276690000001F
+:02766A0000001E
+:02766B0000001D
+:02766C0000001C
+:02766D0000001B
+:02766E0000001A
+:02766F00000019
+:02767000000018
+:02767100000017
+:02767200000016
+:02767300000015
+:02767400000014
+:02767500000013
+:02767600000012
+:02767700000011
+:02767800000010
+:0276790000000F
+:02767A0000000E
+:02767B0000000D
+:02767C0000000C
+:02767D0000000B
+:02767E0000000A
+:02767F00000009
+:02768000000008
+:02768100000007
+:02768200000006
+:02768300000005
+:02768400000004
+:02768500000003
+:02768600000002
+:02768700000001
+:02768800000000
+:027689000000FF
+:02768A000000FE
+:02768B000000FD
+:02768C000000FC
+:02768D000000FB
+:02768E000000FA
+:02768F000000F9
+:027690000000F8
+:027691000000F7
+:027692000000F6
+:027693000000F5
+:027694000000F4
+:027695000000F3
+:027696000000F2
+:027697000000F1
+:027698000000F0
+:027699000000EF
+:02769A000000EE
+:02769B000000ED
+:02769C000000EC
+:02769D000000EB
+:02769E000000EA
+:02769F000000E9
+:0276A0000000E8
+:0276A1000000E7
+:0276A2000000E6
+:0276A3000000E5
+:0276A4000000E4
+:0276A5000000E3
+:0276A6000000E2
+:0276A7000000E1
+:0276A8000000E0
+:0276A9000000DF
+:0276AA000000DE
+:0276AB000000DD
+:0276AC000000DC
+:0276AD000000DB
+:0276AE000000DA
+:0276AF000000D9
+:0276B0000000D8
+:0276B1000000D7
+:0276B2000000D6
+:0276B3000000D5
+:0276B4000000D4
+:0276B5000000D3
+:0276B6000000D2
+:0276B7000000D1
+:0276B8000000D0
+:0276B9000000CF
+:0276BA000000CE
+:0276BB000000CD
+:0276BC000000CC
+:0276BD000000CB
+:0276BE000000CA
+:0276BF000000C9
+:0276C0000000C8
+:0276C1000000C7
+:0276C2000000C6
+:0276C3000000C5
+:0276C4000000C4
+:0276C5000000C3
+:0276C6000000C2
+:0276C7000000C1
+:0276C8000000C0
+:0276C9000000BF
+:0276CA000000BE
+:0276CB000000BD
+:0276CC000000BC
+:0276CD000000BB
+:0276CE000000BA
+:0276CF000000B9
+:0276D0000000B8
+:0276D1000000B7
+:0276D2000000B6
+:0276D3000000B5
+:0276D4000000B4
+:0276D5000000B3
+:0276D6000000B2
+:0276D7000000B1
+:0276D8000000B0
+:0276D9000000AF
+:0276DA000000AE
+:0276DB000000AD
+:0276DC000000AC
+:0276DD000000AB
+:0276DE000000AA
+:0276DF000000A9
+:0276E0000000A8
+:0276E1000000A7
+:0276E2000000A6
+:0276E3000000A5
+:0276E4000000A4
+:0276E5000000A3
+:0276E6000000A2
+:0276E7000000A1
+:0276E8000000A0
+:0276E90000009F
+:0276EA0000009E
+:0276EB0000009D
+:0276EC0000009C
+:0276ED0000009B
+:0276EE0000009A
+:0276EF00000099
+:0276F000000098
+:0276F100000097
+:0276F200000096
+:0276F300000095
+:0276F400000094
+:0276F500000093
+:0276F600000092
+:0276F700000091
+:0276F800000090
+:0276F90000008F
+:0276FA0000008E
+:0276FB0000008D
+:0276FC0000008C
+:0276FD0000008B
+:0276FE0000008A
+:0276FF00000089
+:02770000000087
+:02770100000086
+:02770200000085
+:02770300000084
+:02770400000083
+:02770500000082
+:02770600000081
+:02770700000080
+:0277080000007F
+:0277090000007E
+:02770A0000007D
+:02770B0000007C
+:02770C0000007B
+:02770D0000007A
+:02770E00000079
+:02770F00000078
+:02771000000077
+:02771100000076
+:02771200000075
+:02771300000074
+:02771400000073
+:02771500000072
+:02771600000071
+:02771700000070
+:0277180000006F
+:0277190000006E
+:02771A0000006D
+:02771B0000006C
+:02771C0000006B
+:02771D0000006A
+:02771E00000069
+:02771F00000068
+:02772000000067
+:02772100000066
+:02772200000065
+:02772300000064
+:02772400000063
+:02772500000062
+:02772600000061
+:02772700000060
+:0277280000005F
+:0277290000005E
+:02772A0000005D
+:02772B0000005C
+:02772C0000005B
+:02772D0000005A
+:02772E00000059
+:02772F00000058
+:02773000000057
+:02773100000056
+:02773200000055
+:02773300000054
+:02773400000053
+:02773500000052
+:02773600000051
+:02773700000050
+:0277380000004F
+:0277390000004E
+:02773A0000004D
+:02773B0000004C
+:02773C0000004B
+:02773D0000004A
+:02773E00000049
+:02773F00000048
+:02774000000047
+:02774100000046
+:02774200000045
+:02774300000044
+:02774400000043
+:02774500000042
+:02774600000041
+:02774700000040
+:0277480000003F
+:0277490000003E
+:02774A0000003D
+:02774B0000003C
+:02774C0000003B
+:02774D0000003A
+:02774E00000039
+:02774F00000038
+:02775000000037
+:02775100000036
+:02775200000035
+:02775300000034
+:02775400000033
+:02775500000032
+:02775600000031
+:02775700000030
+:0277580000002F
+:0277590000002E
+:02775A0000002D
+:02775B0000002C
+:02775C0000002B
+:02775D0000002A
+:02775E00000029
+:02775F00000028
+:02776000000027
+:02776100000026
+:02776200000025
+:02776300000024
+:02776400000023
+:02776500000022
+:02776600000021
+:02776700000020
+:0277680000001F
+:0277690000001E
+:02776A0000001D
+:02776B0000001C
+:02776C0000001B
+:02776D0000001A
+:02776E00000019
+:02776F00000018
+:02777000000017
+:02777100000016
+:02777200000015
+:02777300000014
+:02777400000013
+:02777500000012
+:02777600000011
+:02777700000010
+:0277780000000F
+:0277790000000E
+:02777A0000000D
+:02777B0000000C
+:02777C0000000B
+:02777D0000000A
+:02777E00000009
+:02777F00000008
+:02778000000007
+:02778100000006
+:02778200000005
+:02778300000004
+:02778400000003
+:02778500000002
+:02778600000001
+:02778700000000
+:027788000000FF
+:027789000000FE
+:02778A000000FD
+:02778B000000FC
+:02778C000000FB
+:02778D000000FA
+:02778E000000F9
+:02778F000000F8
+:027790000000F7
+:027791000000F6
+:027792000000F5
+:027793000000F4
+:027794000000F3
+:027795000000F2
+:027796000000F1
+:027797000000F0
+:027798000000EF
+:027799000000EE
+:02779A000000ED
+:02779B000000EC
+:02779C000000EB
+:02779D000000EA
+:02779E000000E9
+:02779F000000E8
+:0277A0000000E7
+:0277A1000000E6
+:0277A2000000E5
+:0277A3000000E4
+:0277A4000000E3
+:0277A5000000E2
+:0277A6000000E1
+:0277A7000000E0
+:0277A8000000DF
+:0277A9000000DE
+:0277AA000000DD
+:0277AB000000DC
+:0277AC000000DB
+:0277AD000000DA
+:0277AE000000D9
+:0277AF000000D8
+:0277B0000000D7
+:0277B1000000D6
+:0277B2000000D5
+:0277B3000000D4
+:0277B4000000D3
+:0277B5000000D2
+:0277B6000000D1
+:0277B7000000D0
+:0277B8000000CF
+:0277B9000000CE
+:0277BA000000CD
+:0277BB000000CC
+:0277BC000000CB
+:0277BD000000CA
+:0277BE000000C9
+:0277BF000000C8
+:0277C0000000C7
+:0277C1000000C6
+:0277C2000000C5
+:0277C3000000C4
+:0277C4000000C3
+:0277C5000000C2
+:0277C6000000C1
+:0277C7000000C0
+:0277C8000000BF
+:0277C9000000BE
+:0277CA000000BD
+:0277CB000000BC
+:0277CC000000BB
+:0277CD000000BA
+:0277CE000000B9
+:0277CF000000B8
+:0277D0000000B7
+:0277D1000000B6
+:0277D2000000B5
+:0277D3000000B4
+:0277D4000000B3
+:0277D5000000B2
+:0277D6000000B1
+:0277D7000000B0
+:0277D8000000AF
+:0277D9000000AE
+:0277DA000000AD
+:0277DB000000AC
+:0277DC000000AB
+:0277DD000000AA
+:0277DE000000A9
+:0277DF000000A8
+:0277E0000000A7
+:0277E1000000A6
+:0277E2000000A5
+:0277E3000000A4
+:0277E4000000A3
+:0277E5000000A2
+:0277E6000000A1
+:0277E7000000A0
+:0277E80000009F
+:0277E90000009E
+:0277EA0000009D
+:0277EB0000009C
+:0277EC0000009B
+:0277ED0000009A
+:0277EE00000099
+:0277EF00000098
+:0277F000000097
+:0277F100000096
+:0277F200000095
+:0277F300000094
+:0277F400000093
+:0277F500000092
+:0277F600000091
+:0277F700000090
+:0277F80000008F
+:0277F90000008E
+:0277FA0000008D
+:0277FB0000008C
+:0277FC0000008B
+:0277FD0000008A
+:0277FE00000089
+:0277FF00000088
+:02780000000086
+:02780100000085
+:02780200000084
+:02780300000083
+:02780400000082
+:02780500000081
+:02780600000080
+:0278070000007F
+:0278080000007E
+:0278090000007D
+:02780A0000007C
+:02780B0000007B
+:02780C0000007A
+:02780D00000079
+:02780E00000078
+:02780F00000077
+:02781000000076
+:02781100000075
+:02781200000074
+:02781300000073
+:02781400000072
+:02781500000071
+:02781600000070
+:0278170000006F
+:0278180000006E
+:0278190000006D
+:02781A0000006C
+:02781B0000006B
+:02781C0000006A
+:02781D00000069
+:02781E00000068
+:02781F00000067
+:02782000000066
+:02782100000065
+:02782200000064
+:02782300000063
+:02782400000062
+:02782500000061
+:02782600000060
+:0278270000005F
+:0278280000005E
+:0278290000005D
+:02782A0000005C
+:02782B0000005B
+:02782C0000005A
+:02782D00000059
+:02782E00000058
+:02782F00000057
+:02783000000056
+:02783100000055
+:02783200000054
+:02783300000053
+:02783400000052
+:02783500000051
+:02783600000050
+:0278370000004F
+:0278380000004E
+:0278390000004D
+:02783A0000004C
+:02783B0000004B
+:02783C0000004A
+:02783D00000049
+:02783E00000048
+:02783F00000047
+:02784000000046
+:02784100000045
+:02784200000044
+:02784300000043
+:02784400000042
+:02784500000041
+:02784600000040
+:0278470000003F
+:0278480000003E
+:0278490000003D
+:02784A0000003C
+:02784B0000003B
+:02784C0000003A
+:02784D00000039
+:02784E00000038
+:02784F00000037
+:02785000000036
+:02785100000035
+:02785200000034
+:02785300000033
+:02785400000032
+:02785500000031
+:02785600000030
+:0278570000002F
+:0278580000002E
+:0278590000002D
+:02785A0000002C
+:02785B0000002B
+:02785C0000002A
+:02785D00000029
+:02785E00000028
+:02785F00000027
+:02786000000026
+:02786100000025
+:02786200000024
+:02786300000023
+:02786400000022
+:02786500000021
+:02786600000020
+:0278670000001F
+:0278680000001E
+:0278690000001D
+:02786A0000001C
+:02786B0000001B
+:02786C0000001A
+:02786D00000019
+:02786E00000018
+:02786F00000017
+:02787000000016
+:02787100000015
+:02787200000014
+:02787300000013
+:02787400000012
+:02787500000011
+:02787600000010
+:0278770000000F
+:0278780000000E
+:0278790000000D
+:02787A0000000C
+:02787B0000000B
+:02787C0000000A
+:02787D00000009
+:02787E00000008
+:02787F00000007
+:02788000000006
+:02788100000005
+:02788200000004
+:02788300000003
+:02788400000002
+:02788500000001
+:02788600000000
+:027887000000FF
+:027888000000FE
+:027889000000FD
+:02788A000000FC
+:02788B000000FB
+:02788C000000FA
+:02788D000000F9
+:02788E000000F8
+:02788F000000F7
+:027890000000F6
+:027891000000F5
+:027892000000F4
+:027893000000F3
+:027894000000F2
+:027895000000F1
+:027896000000F0
+:027897000000EF
+:027898000000EE
+:027899000000ED
+:02789A000000EC
+:02789B000000EB
+:02789C000000EA
+:02789D000000E9
+:02789E000000E8
+:02789F000000E7
+:0278A0000000E6
+:0278A1000000E5
+:0278A2000000E4
+:0278A3000000E3
+:0278A4000000E2
+:0278A5000000E1
+:0278A6000000E0
+:0278A7000000DF
+:0278A8000000DE
+:0278A9000000DD
+:0278AA000000DC
+:0278AB000000DB
+:0278AC000000DA
+:0278AD000000D9
+:0278AE000000D8
+:0278AF000000D7
+:0278B0000000D6
+:0278B1000000D5
+:0278B2000000D4
+:0278B3000000D3
+:0278B4000000D2
+:0278B5000000D1
+:0278B6000000D0
+:0278B7000000CF
+:0278B8000000CE
+:0278B9000000CD
+:0278BA000000CC
+:0278BB000000CB
+:0278BC000000CA
+:0278BD000000C9
+:0278BE000000C8
+:0278BF000000C7
+:0278C0000000C6
+:0278C1000000C5
+:0278C2000000C4
+:0278C3000000C3
+:0278C4000000C2
+:0278C5000000C1
+:0278C6000000C0
+:0278C7000000BF
+:0278C8000000BE
+:0278C9000000BD
+:0278CA000000BC
+:0278CB000000BB
+:0278CC000000BA
+:0278CD000000B9
+:0278CE000000B8
+:0278CF000000B7
+:0278D0000000B6
+:0278D1000000B5
+:0278D2000000B4
+:0278D3000000B3
+:0278D4000000B2
+:0278D5000000B1
+:0278D6000000B0
+:0278D7000000AF
+:0278D8000000AE
+:0278D9000000AD
+:0278DA000000AC
+:0278DB000000AB
+:0278DC000000AA
+:0278DD000000A9
+:0278DE000000A8
+:0278DF000000A7
+:0278E0000000A6
+:0278E1000000A5
+:0278E2000000A4
+:0278E3000000A3
+:0278E4000000A2
+:0278E5000000A1
+:0278E6000000A0
+:0278E70000009F
+:0278E80000009E
+:0278E90000009D
+:0278EA0000009C
+:0278EB0000009B
+:0278EC0000009A
+:0278ED00000099
+:0278EE00000098
+:0278EF00000097
+:0278F000000096
+:0278F100000095
+:0278F200000094
+:0278F300000093
+:0278F400000092
+:0278F500000091
+:0278F600000090
+:0278F70000008F
+:0278F80000008E
+:0278F90000008D
+:0278FA0000008C
+:0278FB0000008B
+:0278FC0000008A
+:0278FD00000089
+:0278FE00000088
+:0278FF00000087
+:02790000000085
+:02790100000084
+:02790200000083
+:02790300000082
+:02790400000081
+:02790500000080
+:0279060000007F
+:0279070000007E
+:0279080000007D
+:0279090000007C
+:02790A0000007B
+:02790B0000007A
+:02790C00000079
+:02790D00000078
+:02790E00000077
+:02790F00000076
+:02791000000075
+:02791100000074
+:02791200000073
+:02791300000072
+:02791400000071
+:02791500000070
+:0279160000006F
+:0279170000006E
+:0279180000006D
+:0279190000006C
+:02791A0000006B
+:02791B0000006A
+:02791C00000069
+:02791D00000068
+:02791E00000067
+:02791F00000066
+:02792000000065
+:02792100000064
+:02792200000063
+:02792300000062
+:02792400000061
+:02792500000060
+:0279260000005F
+:0279270000005E
+:0279280000005D
+:0279290000005C
+:02792A0000005B
+:02792B0000005A
+:02792C00000059
+:02792D00000058
+:02792E00000057
+:02792F00000056
+:02793000000055
+:02793100000054
+:02793200000053
+:02793300000052
+:02793400000051
+:02793500000050
+:0279360000004F
+:0279370000004E
+:0279380000004D
+:0279390000004C
+:02793A0000004B
+:02793B0000004A
+:02793C00000049
+:02793D00000048
+:02793E00000047
+:02793F00000046
+:02794000000045
+:02794100000044
+:02794200000043
+:02794300000042
+:02794400000041
+:02794500000040
+:0279460000003F
+:0279470000003E
+:0279480000003D
+:0279490000003C
+:02794A0000003B
+:02794B0000003A
+:02794C00000039
+:02794D00000038
+:02794E00000037
+:02794F00000036
+:02795000000035
+:02795100000034
+:02795200000033
+:02795300000032
+:02795400000031
+:02795500000030
+:0279560000002F
+:0279570000002E
+:0279580000002D
+:0279590000002C
+:02795A0000002B
+:02795B0000002A
+:02795C00000029
+:02795D00000028
+:02795E00000027
+:02795F00000026
+:02796000000025
+:02796100000024
+:02796200000023
+:02796300000022
+:02796400000021
+:02796500000020
+:0279660000001F
+:0279670000001E
+:0279680000001D
+:0279690000001C
+:02796A0000001B
+:02796B0000001A
+:02796C00000019
+:02796D00000018
+:02796E00000017
+:02796F00000016
+:02797000000015
+:02797100000014
+:02797200000013
+:02797300000012
+:02797400000011
+:02797500000010
+:0279760000000F
+:0279770000000E
+:0279780000000D
+:0279790000000C
+:02797A0000000B
+:02797B0000000A
+:02797C00000009
+:02797D00000008
+:02797E00000007
+:02797F00000006
+:02798000000005
+:02798100000004
+:02798200000003
+:02798300000002
+:02798400000001
+:02798500000000
+:027986000000FF
+:027987000000FE
+:027988000000FD
+:027989000000FC
+:02798A000000FB
+:02798B000000FA
+:02798C000000F9
+:02798D000000F8
+:02798E000000F7
+:02798F000000F6
+:027990000000F5
+:027991000000F4
+:027992000000F3
+:027993000000F2
+:027994000000F1
+:027995000000F0
+:027996000000EF
+:027997000000EE
+:027998000000ED
+:027999000000EC
+:02799A000000EB
+:02799B000000EA
+:02799C000000E9
+:02799D000000E8
+:02799E000000E7
+:02799F000000E6
+:0279A0000000E5
+:0279A1000000E4
+:0279A2000000E3
+:0279A3000000E2
+:0279A4000000E1
+:0279A5000000E0
+:0279A6000000DF
+:0279A7000000DE
+:0279A8000000DD
+:0279A9000000DC
+:0279AA000000DB
+:0279AB000000DA
+:0279AC000000D9
+:0279AD000000D8
+:0279AE000000D7
+:0279AF000000D6
+:0279B0000000D5
+:0279B1000000D4
+:0279B2000000D3
+:0279B3000000D2
+:0279B4000000D1
+:0279B5000000D0
+:0279B6000000CF
+:0279B7000000CE
+:0279B8000000CD
+:0279B9000000CC
+:0279BA000000CB
+:0279BB000000CA
+:0279BC000000C9
+:0279BD000000C8
+:0279BE000000C7
+:0279BF000000C6
+:0279C0000000C5
+:0279C1000000C4
+:0279C2000000C3
+:0279C3000000C2
+:0279C4000000C1
+:0279C5000000C0
+:0279C6000000BF
+:0279C7000000BE
+:0279C8000000BD
+:0279C9000000BC
+:0279CA000000BB
+:0279CB000000BA
+:0279CC000000B9
+:0279CD000000B8
+:0279CE000000B7
+:0279CF000000B6
+:0279D0000000B5
+:0279D1000000B4
+:0279D2000000B3
+:0279D3000000B2
+:0279D4000000B1
+:0279D5000000B0
+:0279D6000000AF
+:0279D7000000AE
+:0279D8000000AD
+:0279D9000000AC
+:0279DA000000AB
+:0279DB000000AA
+:0279DC000000A9
+:0279DD000000A8
+:0279DE000000A7
+:0279DF000000A6
+:0279E0000000A5
+:0279E1000000A4
+:0279E2000000A3
+:0279E3000000A2
+:0279E4000000A1
+:0279E5000000A0
+:0279E60000009F
+:0279E70000009E
+:0279E80000009D
+:0279E90000009C
+:0279EA0000009B
+:0279EB0000009A
+:0279EC00000099
+:0279ED00000098
+:0279EE00000097
+:0279EF00000096
+:0279F000000095
+:0279F100000094
+:0279F200000093
+:0279F300000092
+:0279F400000091
+:0279F500000090
+:0279F60000008F
+:0279F70000008E
+:0279F80000008D
+:0279F90000008C
+:0279FA0000008B
+:0279FB0000008A
+:0279FC00000089
+:0279FD00000088
+:0279FE00000087
+:0279FF00000086
+:027A0000000084
+:027A0100000083
+:027A0200000082
+:027A0300000081
+:027A0400000080
+:027A050000007F
+:027A060000007E
+:027A070000007D
+:027A080000007C
+:027A090000007B
+:027A0A0000007A
+:027A0B00000079
+:027A0C00000078
+:027A0D00000077
+:027A0E00000076
+:027A0F00000075
+:027A1000000074
+:027A1100000073
+:027A1200000072
+:027A1300000071
+:027A1400000070
+:027A150000006F
+:027A160000006E
+:027A170000006D
+:027A180000006C
+:027A190000006B
+:027A1A0000006A
+:027A1B00000069
+:027A1C00000068
+:027A1D00000067
+:027A1E00000066
+:027A1F00000065
+:027A2000000064
+:027A2100000063
+:027A2200000062
+:027A2300000061
+:027A2400000060
+:027A250000005F
+:027A260000005E
+:027A270000005D
+:027A280000005C
+:027A290000005B
+:027A2A0000005A
+:027A2B00000059
+:027A2C00000058
+:027A2D00000057
+:027A2E00000056
+:027A2F00000055
+:027A3000000054
+:027A3100000053
+:027A3200000052
+:027A3300000051
+:027A3400000050
+:027A350000004F
+:027A360000004E
+:027A370000004D
+:027A380000004C
+:027A390000004B
+:027A3A0000004A
+:027A3B00000049
+:027A3C00000048
+:027A3D00000047
+:027A3E00000046
+:027A3F00000045
+:027A4000000044
+:027A4100000043
+:027A4200000042
+:027A4300000041
+:027A4400000040
+:027A450000003F
+:027A460000003E
+:027A470000003D
+:027A480000003C
+:027A490000003B
+:027A4A0000003A
+:027A4B00000039
+:027A4C00000038
+:027A4D00000037
+:027A4E00000036
+:027A4F00000035
+:027A5000000034
+:027A5100000033
+:027A5200000032
+:027A5300000031
+:027A5400000030
+:027A550000002F
+:027A560000002E
+:027A570000002D
+:027A580000002C
+:027A590000002B
+:027A5A0000002A
+:027A5B00000029
+:027A5C00000028
+:027A5D00000027
+:027A5E00000026
+:027A5F00000025
+:027A6000000024
+:027A6100000023
+:027A6200000022
+:027A6300000021
+:027A6400000020
+:027A650000001F
+:027A660000001E
+:027A670000001D
+:027A680000001C
+:027A690000001B
+:027A6A0000001A
+:027A6B00000019
+:027A6C00000018
+:027A6D00000017
+:027A6E00000016
+:027A6F00000015
+:027A7000000014
+:027A7100000013
+:027A7200000012
+:027A7300000011
+:027A7400000010
+:027A750000000F
+:027A760000000E
+:027A770000000D
+:027A780000000C
+:027A790000000B
+:027A7A0000000A
+:027A7B00000009
+:027A7C00000008
+:027A7D00000007
+:027A7E00000006
+:027A7F00000005
+:027A8000000004
+:027A8100000003
+:027A8200000002
+:027A8300000001
+:027A8400000000
+:027A85000000FF
+:027A86000000FE
+:027A87000000FD
+:027A88000000FC
+:027A89000000FB
+:027A8A000000FA
+:027A8B000000F9
+:027A8C000000F8
+:027A8D000000F7
+:027A8E000000F6
+:027A8F000000F5
+:027A90000000F4
+:027A91000000F3
+:027A92000000F2
+:027A93000000F1
+:027A94000000F0
+:027A95000000EF
+:027A96000000EE
+:027A97000000ED
+:027A98000000EC
+:027A99000000EB
+:027A9A000000EA
+:027A9B000000E9
+:027A9C000000E8
+:027A9D000000E7
+:027A9E000000E6
+:027A9F000000E5
+:027AA0000000E4
+:027AA1000000E3
+:027AA2000000E2
+:027AA3000000E1
+:027AA4000000E0
+:027AA5000000DF
+:027AA6000000DE
+:027AA7000000DD
+:027AA8000000DC
+:027AA9000000DB
+:027AAA000000DA
+:027AAB000000D9
+:027AAC000000D8
+:027AAD000000D7
+:027AAE000000D6
+:027AAF000000D5
+:027AB0000000D4
+:027AB1000000D3
+:027AB2000000D2
+:027AB3000000D1
+:027AB4000000D0
+:027AB5000000CF
+:027AB6000000CE
+:027AB7000000CD
+:027AB8000000CC
+:027AB9000000CB
+:027ABA000000CA
+:027ABB000000C9
+:027ABC000000C8
+:027ABD000000C7
+:027ABE000000C6
+:027ABF000000C5
+:027AC0000000C4
+:027AC1000000C3
+:027AC2000000C2
+:027AC3000000C1
+:027AC4000000C0
+:027AC5000000BF
+:027AC6000000BE
+:027AC7000000BD
+:027AC8000000BC
+:027AC9000000BB
+:027ACA000000BA
+:027ACB000000B9
+:027ACC000000B8
+:027ACD000000B7
+:027ACE000000B6
+:027ACF000000B5
+:027AD0000000B4
+:027AD1000000B3
+:027AD2000000B2
+:027AD3000000B1
+:027AD4000000B0
+:027AD5000000AF
+:027AD6000000AE
+:027AD7000000AD
+:027AD8000000AC
+:027AD9000000AB
+:027ADA000000AA
+:027ADB000000A9
+:027ADC000000A8
+:027ADD000000A7
+:027ADE000000A6
+:027ADF000000A5
+:027AE0000000A4
+:027AE1000000A3
+:027AE2000000A2
+:027AE3000000A1
+:027AE4000000A0
+:027AE50000009F
+:027AE60000009E
+:027AE70000009D
+:027AE80000009C
+:027AE90000009B
+:027AEA0000009A
+:027AEB00000099
+:027AEC00000098
+:027AED00000097
+:027AEE00000096
+:027AEF00000095
+:027AF000000094
+:027AF100000093
+:027AF200000092
+:027AF300000091
+:027AF400000090
+:027AF50000008F
+:027AF60000008E
+:027AF70000008D
+:027AF80000008C
+:027AF90000008B
+:027AFA0000008A
+:027AFB00000089
+:027AFC00000088
+:027AFD00000087
+:027AFE00000086
+:027AFF00000085
+:027B0000000083
+:027B0100000082
+:027B0200000081
+:027B0300000080
+:027B040000007F
+:027B050000007E
+:027B060000007D
+:027B070000007C
+:027B080000007B
+:027B090000007A
+:027B0A00000079
+:027B0B00000078
+:027B0C00000077
+:027B0D00000076
+:027B0E00000075
+:027B0F00000074
+:027B1000000073
+:027B1100000072
+:027B1200000071
+:027B1300000070
+:027B140000006F
+:027B150000006E
+:027B160000006D
+:027B170000006C
+:027B180000006B
+:027B190000006A
+:027B1A00000069
+:027B1B00000068
+:027B1C00000067
+:027B1D00000066
+:027B1E00000065
+:027B1F00000064
+:027B2000000063
+:027B2100000062
+:027B2200000061
+:027B2300000060
+:027B240000005F
+:027B250000005E
+:027B260000005D
+:027B270000005C
+:027B280000005B
+:027B290000005A
+:027B2A00000059
+:027B2B00000058
+:027B2C00000057
+:027B2D00000056
+:027B2E00000055
+:027B2F00000054
+:027B3000000053
+:027B3100000052
+:027B3200000051
+:027B3300000050
+:027B340000004F
+:027B350000004E
+:027B360000004D
+:027B370000004C
+:027B380000004B
+:027B390000004A
+:027B3A00000049
+:027B3B00000048
+:027B3C00000047
+:027B3D00000046
+:027B3E00000045
+:027B3F00000044
+:027B4000000043
+:027B4100000042
+:027B4200000041
+:027B4300000040
+:027B440000003F
+:027B450000003E
+:027B460000003D
+:027B470000003C
+:027B480000003B
+:027B490000003A
+:027B4A00000039
+:027B4B00000038
+:027B4C00000037
+:027B4D00000036
+:027B4E00000035
+:027B4F00000034
+:027B5000000033
+:027B5100000032
+:027B5200000031
+:027B5300000030
+:027B540000002F
+:027B550000002E
+:027B560000002D
+:027B570000002C
+:027B580000002B
+:027B590000002A
+:027B5A00000029
+:027B5B00000028
+:027B5C00000027
+:027B5D00000026
+:027B5E00000025
+:027B5F00000024
+:027B6000000023
+:027B6100000022
+:027B6200000021
+:027B6300000020
+:027B640000001F
+:027B650000001E
+:027B660000001D
+:027B670000001C
+:027B680000001B
+:027B690000001A
+:027B6A00000019
+:027B6B00000018
+:027B6C00000017
+:027B6D00000016
+:027B6E00000015
+:027B6F00000014
+:027B7000000013
+:027B7100000012
+:027B7200000011
+:027B7300000010
+:027B740000000F
+:027B750000000E
+:027B760000000D
+:027B770000000C
+:027B780000000B
+:027B790000000A
+:027B7A00000009
+:027B7B00000008
+:027B7C00000007
+:027B7D00000006
+:027B7E00000005
+:027B7F00000004
+:027B8000000003
+:027B8100000002
+:027B8200000001
+:027B8300000000
+:027B84000000FF
+:027B85000000FE
+:027B86000000FD
+:027B87000000FC
+:027B88000000FB
+:027B89000000FA
+:027B8A000000F9
+:027B8B000000F8
+:027B8C000000F7
+:027B8D000000F6
+:027B8E000000F5
+:027B8F000000F4
+:027B90000000F3
+:027B91000000F2
+:027B92000000F1
+:027B93000000F0
+:027B94000000EF
+:027B95000000EE
+:027B96000000ED
+:027B97000000EC
+:027B98000000EB
+:027B99000000EA
+:027B9A000000E9
+:027B9B000000E8
+:027B9C000000E7
+:027B9D000000E6
+:027B9E000000E5
+:027B9F000000E4
+:027BA0000000E3
+:027BA1000000E2
+:027BA2000000E1
+:027BA3000000E0
+:027BA4000000DF
+:027BA5000000DE
+:027BA6000000DD
+:027BA7000000DC
+:027BA8000000DB
+:027BA9000000DA
+:027BAA000000D9
+:027BAB000000D8
+:027BAC000000D7
+:027BAD000000D6
+:027BAE000000D5
+:027BAF000000D4
+:027BB0000000D3
+:027BB1000000D2
+:027BB2000000D1
+:027BB3000000D0
+:027BB4000000CF
+:027BB5000000CE
+:027BB6000000CD
+:027BB7000000CC
+:027BB8000000CB
+:027BB9000000CA
+:027BBA000000C9
+:027BBB000000C8
+:027BBC000000C7
+:027BBD000000C6
+:027BBE000000C5
+:027BBF000000C4
+:027BC0000000C3
+:027BC1000000C2
+:027BC2000000C1
+:027BC3000000C0
+:027BC4000000BF
+:027BC5000000BE
+:027BC6000000BD
+:027BC7000000BC
+:027BC8000000BB
+:027BC9000000BA
+:027BCA000000B9
+:027BCB000000B8
+:027BCC000000B7
+:027BCD000000B6
+:027BCE000000B5
+:027BCF000000B4
+:027BD0000000B3
+:027BD1000000B2
+:027BD2000000B1
+:027BD3000000B0
+:027BD4000000AF
+:027BD5000000AE
+:027BD6000000AD
+:027BD7000000AC
+:027BD8000000AB
+:027BD9000000AA
+:027BDA000000A9
+:027BDB000000A8
+:027BDC000000A7
+:027BDD000000A6
+:027BDE000000A5
+:027BDF000000A4
+:027BE0000000A3
+:027BE1000000A2
+:027BE2000000A1
+:027BE3000000A0
+:027BE40000009F
+:027BE50000009E
+:027BE60000009D
+:027BE70000009C
+:027BE80000009B
+:027BE90000009A
+:027BEA00000099
+:027BEB00000098
+:027BEC00000097
+:027BED00000096
+:027BEE00000095
+:027BEF00000094
+:027BF000000093
+:027BF100000092
+:027BF200000091
+:027BF300000090
+:027BF40000008F
+:027BF50000008E
+:027BF60000008D
+:027BF70000008C
+:027BF80000008B
+:027BF90000008A
+:027BFA00000089
+:027BFB00000088
+:027BFC00000087
+:027BFD00000086
+:027BFE00000085
+:027BFF00000084
+:027C0000000082
+:027C0100000081
+:027C0200000080
+:027C030000007F
+:027C040000007E
+:027C050000007D
+:027C060000007C
+:027C070000007B
+:027C080000007A
+:027C0900000079
+:027C0A00000078
+:027C0B00000077
+:027C0C00000076
+:027C0D00000075
+:027C0E00000074
+:027C0F00000073
+:027C1000000072
+:027C1100000071
+:027C1200000070
+:027C130000006F
+:027C140000006E
+:027C150000006D
+:027C160000006C
+:027C170000006B
+:027C180000006A
+:027C1900000069
+:027C1A00000068
+:027C1B00000067
+:027C1C00000066
+:027C1D00000065
+:027C1E00000064
+:027C1F00000063
+:027C2000000062
+:027C2100000061
+:027C2200000060
+:027C230000005F
+:027C240000005E
+:027C250000005D
+:027C260000005C
+:027C270000005B
+:027C280000005A
+:027C2900000059
+:027C2A00000058
+:027C2B00000057
+:027C2C00000056
+:027C2D00000055
+:027C2E00000054
+:027C2F00000053
+:027C3000000052
+:027C3100000051
+:027C3200000050
+:027C330000004F
+:027C340000004E
+:027C350000004D
+:027C360000004C
+:027C370000004B
+:027C380000004A
+:027C3900000049
+:027C3A00000048
+:027C3B00000047
+:027C3C00000046
+:027C3D00000045
+:027C3E00000044
+:027C3F00000043
+:027C4000000042
+:027C4100000041
+:027C4200000040
+:027C430000003F
+:027C440000003E
+:027C450000003D
+:027C460000003C
+:027C470000003B
+:027C480000003A
+:027C4900000039
+:027C4A00000038
+:027C4B00000037
+:027C4C00000036
+:027C4D00000035
+:027C4E00000034
+:027C4F00000033
+:027C5000000032
+:027C5100000031
+:027C5200000030
+:027C530000002F
+:027C540000002E
+:027C550000002D
+:027C560000002C
+:027C570000002B
+:027C580000002A
+:027C5900000029
+:027C5A00000028
+:027C5B00000027
+:027C5C00000026
+:027C5D00000025
+:027C5E00000024
+:027C5F00000023
+:027C6000000022
+:027C6100000021
+:027C6200000020
+:027C630000001F
+:027C640000001E
+:027C650000001D
+:027C660000001C
+:027C670000001B
+:027C680000001A
+:027C6900000019
+:027C6A00000018
+:027C6B00000017
+:027C6C00000016
+:027C6D00000015
+:027C6E00000014
+:027C6F00000013
+:027C7000000012
+:027C7100000011
+:027C7200000010
+:027C730000000F
+:027C740000000E
+:027C750000000D
+:027C760000000C
+:027C770000000B
+:027C780000000A
+:027C7900000009
+:027C7A00000008
+:027C7B00000007
+:027C7C00000006
+:027C7D00000005
+:027C7E00000004
+:027C7F00000003
+:027C8000000002
+:027C8100000001
+:027C8200000000
+:027C83000000FF
+:027C84000000FE
+:027C85000000FD
+:027C86000000FC
+:027C87000000FB
+:027C88000000FA
+:027C89000000F9
+:027C8A000000F8
+:027C8B000000F7
+:027C8C000000F6
+:027C8D000000F5
+:027C8E000000F4
+:027C8F000000F3
+:027C90000000F2
+:027C91000000F1
+:027C92000000F0
+:027C93000000EF
+:027C94000000EE
+:027C95000000ED
+:027C96000000EC
+:027C97000000EB
+:027C98000000EA
+:027C99000000E9
+:027C9A000000E8
+:027C9B000000E7
+:027C9C000000E6
+:027C9D000000E5
+:027C9E000000E4
+:027C9F000000E3
+:027CA0000000E2
+:027CA1000000E1
+:027CA2000000E0
+:027CA3000000DF
+:027CA4000000DE
+:027CA5000000DD
+:027CA6000000DC
+:027CA7000000DB
+:027CA8000000DA
+:027CA9000000D9
+:027CAA000000D8
+:027CAB000000D7
+:027CAC000000D6
+:027CAD000000D5
+:027CAE000000D4
+:027CAF000000D3
+:027CB0000000D2
+:027CB1000000D1
+:027CB2000000D0
+:027CB3000000CF
+:027CB4000000CE
+:027CB5000000CD
+:027CB6000000CC
+:027CB7000000CB
+:027CB8000000CA
+:027CB9000000C9
+:027CBA000000C8
+:027CBB000000C7
+:027CBC000000C6
+:027CBD000000C5
+:027CBE000000C4
+:027CBF000000C3
+:027CC0000000C2
+:027CC1000000C1
+:027CC2000000C0
+:027CC3000000BF
+:027CC4000000BE
+:027CC5000000BD
+:027CC6000000BC
+:027CC7000000BB
+:027CC8000000BA
+:027CC9000000B9
+:027CCA000000B8
+:027CCB000000B7
+:027CCC000000B6
+:027CCD000000B5
+:027CCE000000B4
+:027CCF000000B3
+:027CD0000000B2
+:027CD1000000B1
+:027CD2000000B0
+:027CD3000000AF
+:027CD4000000AE
+:027CD5000000AD
+:027CD6000000AC
+:027CD7000000AB
+:027CD8000000AA
+:027CD9000000A9
+:027CDA000000A8
+:027CDB000000A7
+:027CDC000000A6
+:027CDD000000A5
+:027CDE000000A4
+:027CDF000000A3
+:027CE0000000A2
+:027CE1000000A1
+:027CE2000000A0
+:027CE30000009F
+:027CE40000009E
+:027CE50000009D
+:027CE60000009C
+:027CE70000009B
+:027CE80000009A
+:027CE900000099
+:027CEA00000098
+:027CEB00000097
+:027CEC00000096
+:027CED00000095
+:027CEE00000094
+:027CEF00000093
+:027CF000000092
+:027CF100000091
+:027CF200000090
+:027CF30000008F
+:027CF40000008E
+:027CF50000008D
+:027CF60000008C
+:027CF70000008B
+:027CF80000008A
+:027CF900000089
+:027CFA00000088
+:027CFB00000087
+:027CFC00000086
+:027CFD00000085
+:027CFE00000084
+:027CFF00000083
+:027D0000000081
+:027D0100000080
+:027D020000007F
+:027D030000007E
+:027D040000007D
+:027D050000007C
+:027D060000007B
+:027D070000007A
+:027D0800000079
+:027D0900000078
+:027D0A00000077
+:027D0B00000076
+:027D0C00000075
+:027D0D00000074
+:027D0E00000073
+:027D0F00000072
+:027D1000000071
+:027D1100000070
+:027D120000006F
+:027D130000006E
+:027D140000006D
+:027D150000006C
+:027D160000006B
+:027D170000006A
+:027D1800000069
+:027D1900000068
+:027D1A00000067
+:027D1B00000066
+:027D1C00000065
+:027D1D00000064
+:027D1E00000063
+:027D1F00000062
+:027D2000000061
+:027D2100000060
+:027D220000005F
+:027D230000005E
+:027D240000005D
+:027D250000005C
+:027D260000005B
+:027D270000005A
+:027D2800000059
+:027D2900000058
+:027D2A00000057
+:027D2B00000056
+:027D2C00000055
+:027D2D00000054
+:027D2E00000053
+:027D2F00000052
+:027D3000000051
+:027D3100000050
+:027D320000004F
+:027D330000004E
+:027D340000004D
+:027D350000004C
+:027D360000004B
+:027D370000004A
+:027D3800000049
+:027D3900000048
+:027D3A00000047
+:027D3B00000046
+:027D3C00000045
+:027D3D00000044
+:027D3E00000043
+:027D3F00000042
+:027D4000000041
+:027D4100000040
+:027D420000003F
+:027D430000003E
+:027D440000003D
+:027D450000003C
+:027D460000003B
+:027D470000003A
+:027D4800000039
+:027D4900000038
+:027D4A00000037
+:027D4B00000036
+:027D4C00000035
+:027D4D00000034
+:027D4E00000033
+:027D4F00000032
+:027D5000000031
+:027D5100000030
+:027D520000002F
+:027D530000002E
+:027D540000002D
+:027D550000002C
+:027D560000002B
+:027D570000002A
+:027D5800000029
+:027D5900000028
+:027D5A00000027
+:027D5B00000026
+:027D5C00000025
+:027D5D00000024
+:027D5E00000023
+:027D5F00000022
+:027D6000000021
+:027D6100000020
+:027D620000001F
+:027D630000001E
+:027D640000001D
+:027D650000001C
+:027D660000001B
+:027D670000001A
+:027D6800000019
+:027D6900000018
+:027D6A00000017
+:027D6B00000016
+:027D6C00000015
+:027D6D00000014
+:027D6E00000013
+:027D6F00000012
+:027D7000000011
+:027D7100000010
+:027D720000000F
+:027D730000000E
+:027D740000000D
+:027D750000000C
+:027D760000000B
+:027D770000000A
+:027D7800000009
+:027D7900000008
+:027D7A00000007
+:027D7B00000006
+:027D7C00000005
+:027D7D00000004
+:027D7E00000003
+:027D7F00000002
+:027D8000000001
+:027D8100000000
+:027D82000000FF
+:027D83000000FE
+:027D84000000FD
+:027D85000000FC
+:027D86000000FB
+:027D87000000FA
+:027D88000000F9
+:027D89000000F8
+:027D8A000000F7
+:027D8B000000F6
+:027D8C000000F5
+:027D8D000000F4
+:027D8E000000F3
+:027D8F000000F2
+:027D90000000F1
+:027D91000000F0
+:027D92000000EF
+:027D93000000EE
+:027D94000000ED
+:027D95000000EC
+:027D96000000EB
+:027D97000000EA
+:027D98000000E9
+:027D99000000E8
+:027D9A000000E7
+:027D9B000000E6
+:027D9C000000E5
+:027D9D000000E4
+:027D9E000000E3
+:027D9F000000E2
+:027DA0000000E1
+:027DA1000000E0
+:027DA2000000DF
+:027DA3000000DE
+:027DA4000000DD
+:027DA5000000DC
+:027DA6000000DB
+:027DA7000000DA
+:027DA8000000D9
+:027DA9000000D8
+:027DAA000000D7
+:027DAB000000D6
+:027DAC000000D5
+:027DAD000000D4
+:027DAE000000D3
+:027DAF000000D2
+:027DB0000000D1
+:027DB1000000D0
+:027DB2000000CF
+:027DB3000000CE
+:027DB4000000CD
+:027DB5000000CC
+:027DB6000000CB
+:027DB7000000CA
+:027DB8000000C9
+:027DB9000000C8
+:027DBA000000C7
+:027DBB000000C6
+:027DBC000000C5
+:027DBD000000C4
+:027DBE000000C3
+:027DBF000000C2
+:027DC0000000C1
+:027DC1000000C0
+:027DC2000000BF
+:027DC3000000BE
+:027DC4000000BD
+:027DC5000000BC
+:027DC6000000BB
+:027DC7000000BA
+:027DC8000000B9
+:027DC9000000B8
+:027DCA000000B7
+:027DCB000000B6
+:027DCC000000B5
+:027DCD000000B4
+:027DCE000000B3
+:027DCF000000B2
+:027DD0000000B1
+:027DD1000000B0
+:027DD2000000AF
+:027DD3000000AE
+:027DD4000000AD
+:027DD5000000AC
+:027DD6000000AB
+:027DD7000000AA
+:027DD8000000A9
+:027DD9000000A8
+:027DDA000000A7
+:027DDB000000A6
+:027DDC000000A5
+:027DDD000000A4
+:027DDE000000A3
+:027DDF000000A2
+:027DE0000000A1
+:027DE1000000A0
+:027DE20000009F
+:027DE30000009E
+:027DE40000009D
+:027DE50000009C
+:027DE60000009B
+:027DE70000009A
+:027DE800000099
+:027DE900000098
+:027DEA00000097
+:027DEB00000096
+:027DEC00000095
+:027DED00000094
+:027DEE00000093
+:027DEF00000092
+:027DF000000091
+:027DF100000090
+:027DF20000008F
+:027DF30000008E
+:027DF40000008D
+:027DF50000008C
+:027DF60000008B
+:027DF70000008A
+:027DF800000089
+:027DF900000088
+:027DFA00000087
+:027DFB00000086
+:027DFC00000085
+:027DFD00000084
+:027DFE00000083
+:027DFF00000082
+:027E0000000080
+:027E010000007F
+:027E020000007E
+:027E030000007D
+:027E040000007C
+:027E050000007B
+:027E060000007A
+:027E0700000079
+:027E0800000078
+:027E0900000077
+:027E0A00000076
+:027E0B00000075
+:027E0C00000074
+:027E0D00000073
+:027E0E00000072
+:027E0F00000071
+:027E1000000070
+:027E110000006F
+:027E120000006E
+:027E130000006D
+:027E140000006C
+:027E150000006B
+:027E160000006A
+:027E1700000069
+:027E1800000068
+:027E1900000067
+:027E1A00000066
+:027E1B00000065
+:027E1C00000064
+:027E1D00000063
+:027E1E00000062
+:027E1F00000061
+:027E2000000060
+:027E210000005F
+:027E220000005E
+:027E230000005D
+:027E240000005C
+:027E250000005B
+:027E260000005A
+:027E2700000059
+:027E2800000058
+:027E2900000057
+:027E2A00000056
+:027E2B00000055
+:027E2C00000054
+:027E2D00000053
+:027E2E00000052
+:027E2F00000051
+:027E3000000050
+:027E310000004F
+:027E320000004E
+:027E330000004D
+:027E340000004C
+:027E350000004B
+:027E360000004A
+:027E3700000049
+:027E3800000048
+:027E3900000047
+:027E3A00000046
+:027E3B00000045
+:027E3C00000044
+:027E3D00000043
+:027E3E00000042
+:027E3F00000041
+:027E4000000040
+:027E410000003F
+:027E420000003E
+:027E430000003D
+:027E440000003C
+:027E450000003B
+:027E460000003A
+:027E4700000039
+:027E4800000038
+:027E4900000037
+:027E4A00000036
+:027E4B00000035
+:027E4C00000034
+:027E4D00000033
+:027E4E00000032
+:027E4F00000031
+:027E5000000030
+:027E510000002F
+:027E520000002E
+:027E530000002D
+:027E540000002C
+:027E550000002B
+:027E560000002A
+:027E5700000029
+:027E5800000028
+:027E5900000027
+:027E5A00000026
+:027E5B00000025
+:027E5C00000024
+:027E5D00000023
+:027E5E00000022
+:027E5F00000021
+:027E6000000020
+:027E610000001F
+:027E620000001E
+:027E630000001D
+:027E640000001C
+:027E650000001B
+:027E660000001A
+:027E6700000019
+:027E6800000018
+:027E6900000017
+:027E6A00000016
+:027E6B00000015
+:027E6C00000014
+:027E6D00000013
+:027E6E00000012
+:027E6F00000011
+:027E7000000010
+:027E710000000F
+:027E720000000E
+:027E730000000D
+:027E740000000C
+:027E750000000B
+:027E760000000A
+:027E7700000009
+:027E7800000008
+:027E7900000007
+:027E7A00000006
+:027E7B00000005
+:027E7C00000004
+:027E7D00000003
+:027E7E00000002
+:027E7F00000001
+:027E8000000000
+:027E81000000FF
+:027E82000000FE
+:027E83000000FD
+:027E84000000FC
+:027E85000000FB
+:027E86000000FA
+:027E87000000F9
+:027E88000000F8
+:027E89000000F7
+:027E8A000000F6
+:027E8B000000F5
+:027E8C000000F4
+:027E8D000000F3
+:027E8E000000F2
+:027E8F000000F1
+:027E90000000F0
+:027E91000000EF
+:027E92000000EE
+:027E93000000ED
+:027E94000000EC
+:027E95000000EB
+:027E96000000EA
+:027E97000000E9
+:027E98000000E8
+:027E99000000E7
+:027E9A000000E6
+:027E9B000000E5
+:027E9C000000E4
+:027E9D000000E3
+:027E9E000000E2
+:027E9F000000E1
+:027EA0000000E0
+:027EA1000000DF
+:027EA2000000DE
+:027EA3000000DD
+:027EA4000000DC
+:027EA5000000DB
+:027EA6000000DA
+:027EA7000000D9
+:027EA8000000D8
+:027EA9000000D7
+:027EAA000000D6
+:027EAB000000D5
+:027EAC000000D4
+:027EAD000000D3
+:027EAE000000D2
+:027EAF000000D1
+:027EB0000000D0
+:027EB1000000CF
+:027EB2000000CE
+:027EB3000000CD
+:027EB4000000CC
+:027EB5000000CB
+:027EB6000000CA
+:027EB7000000C9
+:027EB8000000C8
+:027EB9000000C7
+:027EBA000000C6
+:027EBB000000C5
+:027EBC000000C4
+:027EBD000000C3
+:027EBE000000C2
+:027EBF000000C1
+:027EC0000000C0
+:027EC1000000BF
+:027EC2000000BE
+:027EC3000000BD
+:027EC4000000BC
+:027EC5000000BB
+:027EC6000000BA
+:027EC7000000B9
+:027EC8000000B8
+:027EC9000000B7
+:027ECA000000B6
+:027ECB000000B5
+:027ECC000000B4
+:027ECD000000B3
+:027ECE000000B2
+:027ECF000000B1
+:027ED0000000B0
+:027ED1000000AF
+:027ED2000000AE
+:027ED3000000AD
+:027ED4000000AC
+:027ED5000000AB
+:027ED6000000AA
+:027ED7000000A9
+:027ED8000000A8
+:027ED9000000A7
+:027EDA000000A6
+:027EDB000000A5
+:027EDC000000A4
+:027EDD000000A3
+:027EDE000000A2
+:027EDF000000A1
+:027EE0000000A0
+:027EE10000009F
+:027EE20000009E
+:027EE30000009D
+:027EE40000009C
+:027EE50000009B
+:027EE60000009A
+:027EE700000099
+:027EE800000098
+:027EE900000097
+:027EEA00000096
+:027EEB00000095
+:027EEC00000094
+:027EED00000093
+:027EEE00000092
+:027EEF00000091
+:027EF000000090
+:027EF10000008F
+:027EF20000008E
+:027EF30000008D
+:027EF40000008C
+:027EF50000008B
+:027EF60000008A
+:027EF700000089
+:027EF800000088
+:027EF900000087
+:027EFA00000086
+:027EFB00000085
+:027EFC00000084
+:027EFD00000083
+:027EFE00000082
+:027EFF00000081
+:027F000000007F
+:027F010000007E
+:027F020000007D
+:027F030000007C
+:027F040000007B
+:027F050000007A
+:027F0600000079
+:027F0700000078
+:027F0800000077
+:027F0900000076
+:027F0A00000075
+:027F0B00000074
+:027F0C00000073
+:027F0D00000072
+:027F0E00000071
+:027F0F00000070
+:027F100000006F
+:027F110000006E
+:027F120000006D
+:027F130000006C
+:027F140000006B
+:027F150000006A
+:027F1600000069
+:027F1700000068
+:027F1800000067
+:027F1900000066
+:027F1A00000065
+:027F1B00000064
+:027F1C00000063
+:027F1D00000062
+:027F1E00000061
+:027F1F00000060
+:027F200000005F
+:027F210000005E
+:027F220000005D
+:027F230000005C
+:027F240000005B
+:027F250000005A
+:027F2600000059
+:027F2700000058
+:027F2800000057
+:027F2900000056
+:027F2A00000055
+:027F2B00000054
+:027F2C00000053
+:027F2D00000052
+:027F2E00000051
+:027F2F00000050
+:027F300000004F
+:027F310000004E
+:027F320000004D
+:027F330000004C
+:027F340000004B
+:027F350000004A
+:027F3600000049
+:027F3700000048
+:027F3800000047
+:027F3900000046
+:027F3A00000045
+:027F3B00000044
+:027F3C00000043
+:027F3D00000042
+:027F3E00000041
+:027F3F00000040
+:027F400000003F
+:027F410000003E
+:027F420000003D
+:027F430000003C
+:027F440000003B
+:027F450000003A
+:027F4600000039
+:027F4700000038
+:027F4800000037
+:027F4900000036
+:027F4A00000035
+:027F4B00000034
+:027F4C00000033
+:027F4D00000032
+:027F4E00000031
+:027F4F00000030
+:027F500000002F
+:027F510000002E
+:027F520000002D
+:027F530000002C
+:027F540000002B
+:027F550000002A
+:027F5600000029
+:027F5700000028
+:027F5800000027
+:027F5900000026
+:027F5A00000025
+:027F5B00000024
+:027F5C00000023
+:027F5D00000022
+:027F5E00000021
+:027F5F00000020
+:027F600000001F
+:027F610000001E
+:027F620000001D
+:027F630000001C
+:027F640000001B
+:027F650000001A
+:027F6600000019
+:027F6700000018
+:027F6800000017
+:027F6900000016
+:027F6A00000015
+:027F6B00000014
+:027F6C00000013
+:027F6D00000012
+:027F6E00000011
+:027F6F00000010
+:027F700000000F
+:027F710000000E
+:027F720000000D
+:027F730000000C
+:027F740000000B
+:027F750000000A
+:027F7600000009
+:027F7700000008
+:027F7800000007
+:027F7900000006
+:027F7A00000005
+:027F7B00000004
+:027F7C00000003
+:027F7D00000002
+:027F7E00000001
+:027F7F00000000
+:027F80000000FF
+:027F81000000FE
+:027F82000000FD
+:027F83000000FC
+:027F84000000FB
+:027F85000000FA
+:027F86000000F9
+:027F87000000F8
+:027F88000000F7
+:027F89000000F6
+:027F8A000000F5
+:027F8B000000F4
+:027F8C000000F3
+:027F8D000000F2
+:027F8E000000F1
+:027F8F000000F0
+:027F90000000EF
+:027F91000000EE
+:027F92000000ED
+:027F93000000EC
+:027F94000000EB
+:027F95000000EA
+:027F96000000E9
+:027F97000000E8
+:027F98000000E7
+:027F99000000E6
+:027F9A000000E5
+:027F9B000000E4
+:027F9C000000E3
+:027F9D000000E2
+:027F9E000000E1
+:027F9F000000E0
+:027FA0000000DF
+:027FA1000000DE
+:027FA2000000DD
+:027FA3000000DC
+:027FA4000000DB
+:027FA5000000DA
+:027FA6000000D9
+:027FA7000000D8
+:027FA8000000D7
+:027FA9000000D6
+:027FAA000000D5
+:027FAB000000D4
+:027FAC000000D3
+:027FAD000000D2
+:027FAE000000D1
+:027FAF000000D0
+:027FB0000000CF
+:027FB1000000CE
+:027FB2000000CD
+:027FB3000000CC
+:027FB4000000CB
+:027FB5000000CA
+:027FB6000000C9
+:027FB7000000C8
+:027FB8000000C7
+:027FB9000000C6
+:027FBA000000C5
+:027FBB000000C4
+:027FBC000000C3
+:027FBD000000C2
+:027FBE000000C1
+:027FBF000000C0
+:027FC0000000BF
+:027FC1000000BE
+:027FC2000000BD
+:027FC3000000BC
+:027FC4000000BB
+:027FC5000000BA
+:027FC6000000B9
+:027FC7000000B8
+:027FC8000000B7
+:027FC9000000B6
+:027FCA000000B5
+:027FCB000000B4
+:027FCC000000B3
+:027FCD000000B2
+:027FCE000000B1
+:027FCF000000B0
+:027FD0000000AF
+:027FD1000000AE
+:027FD2000000AD
+:027FD3000000AC
+:027FD4000000AB
+:027FD5000000AA
+:027FD6000000A9
+:027FD7000000A8
+:027FD8000000A7
+:027FD9000000A6
+:027FDA000000A5
+:027FDB000000A4
+:027FDC000000A3
+:027FDD000000A2
+:027FDE000000A1
+:027FDF000000A0
+:027FE00000009F
+:027FE10000009E
+:027FE20000009D
+:027FE30000009C
+:027FE40000009B
+:027FE50000009A
+:027FE600000099
+:027FE700000098
+:027FE800000097
+:027FE900000096
+:027FEA00000095
+:027FEB00000094
+:027FEC00000093
+:027FED00000092
+:027FEE00000091
+:027FEF00000090
+:027FF00000008F
+:027FF10000008E
+:027FF20000008D
+:027FF30000008C
+:027FF40000008B
+:027FF50000008A
+:027FF600000089
+:027FF700000088
+:027FF800000087
+:027FF900000086
+:027FFA00000085
+:00000001ff
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.v
new file mode 100644
index 0000000..0a49a6f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_log_ram.v
@@ -0,0 +1,87 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_log_ram (
+                       // inputs:
+                        address,
+                        byteenable,
+                        chipselect,
+                        clk,
+                        clken,
+                        freeze,
+                        reset,
+                        reset_req,
+                        write,
+                        writedata,
+
+                       // outputs:
+                        readdata
+                     )
+;
+
+  output  [ 15: 0] readdata;
+  input   [ 13: 0] address;
+  input   [  1: 0] byteenable;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [ 15: 0] writedata;
+
+
+wire             clocken0;
+wire    [ 15: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=logR",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 16384,
+           the_altsyncram.numwords_a = 16384,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.widthad_a = 14;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v
new file mode 100644
index 0000000..1784535
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0.v
@@ -0,0 +1,412 @@
+// q_sys_mem_if_ddr3_emif_0.v
+
+// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mem_if_ddr3_emif_0 (
+		input  wire        pll_ref_clk,        //      pll_ref_clk.clk
+		input  wire        global_reset_n,     //     global_reset.reset_n
+		input  wire        soft_reset_n,       //       soft_reset.reset_n
+		output wire        afi_clk,            //          afi_clk.clk
+		output wire        afi_half_clk,       //     afi_half_clk.clk
+		output wire        afi_reset_n,        //        afi_reset.reset_n
+		output wire        afi_reset_export_n, // afi_reset_export.reset_n
+		output wire [13:0] mem_a,              //           memory.mem_a
+		output wire [2:0]  mem_ba,             //                 .mem_ba
+		inout  wire [0:0]  mem_ck,             //                 .mem_ck
+		inout  wire [0:0]  mem_ck_n,           //                 .mem_ck_n
+		output wire [0:0]  mem_cke,            //                 .mem_cke
+		output wire [0:0]  mem_cs_n,           //                 .mem_cs_n
+		output wire [0:0]  mem_dm,             //                 .mem_dm
+		output wire [0:0]  mem_ras_n,          //                 .mem_ras_n
+		output wire [0:0]  mem_cas_n,          //                 .mem_cas_n
+		output wire [0:0]  mem_we_n,           //                 .mem_we_n
+		output wire        mem_reset_n,        //                 .mem_reset_n
+		inout  wire [7:0]  mem_dq,             //                 .mem_dq
+		inout  wire [0:0]  mem_dqs,            //                 .mem_dqs
+		inout  wire [0:0]  mem_dqs_n,          //                 .mem_dqs_n
+		output wire [0:0]  mem_odt,            //                 .mem_odt
+		output wire        avl_ready,          //              avl.waitrequest_n
+		input  wire        avl_burstbegin,     //                 .beginbursttransfer
+		input  wire [24:0] avl_addr,           //                 .address
+		output wire        avl_rdata_valid,    //                 .readdatavalid
+		output wire [31:0] avl_rdata,          //                 .readdata
+		input  wire [31:0] avl_wdata,          //                 .writedata
+		input  wire [3:0]  avl_be,             //                 .byteenable
+		input  wire        avl_read_req,       //                 .read
+		input  wire        avl_write_req,      //                 .write
+		input  wire [2:0]  avl_size,           //                 .burstcount
+		output wire        local_init_done,    //           status.local_init_done
+		output wire        local_cal_success,  //                 .local_cal_success
+		output wire        local_cal_fail,     //                 .local_cal_fail
+		output wire        pll_mem_clk,        //      pll_sharing.pll_mem_clk
+		output wire        pll_write_clk,      //                 .pll_write_clk
+		output wire        pll_locked,         //                 .pll_locked
+		output wire        pll_capture0_clk,   //                 .pll_capture0_clk
+		output wire        pll_capture1_clk    //                 .pll_capture1_clk
+	);
+
+	wire   [1:0] m0_phy_mux_afi_rdata_en_full;       // m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
+	wire   [5:0] p0_afi_afi_rlat;                    // p0:afi_rlat -> m0:phy_mux_rlat
+	wire         p0_afi_afi_cal_success;             // p0:afi_cal_success -> m0:phy_mux_cal_success
+	wire   [1:0] m0_phy_mux_afi_wdata_valid;         // m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
+	wire  [31:0] p0_afi_afi_rdata;                   // p0:afi_rdata -> m0:phy_mux_rdata
+	wire  [31:0] m0_phy_mux_afi_wdata;               // m0:phy_mux_wdata -> p0:afi_wdata
+	wire   [1:0] m0_phy_mux_afi_rst_n;               // m0:phy_mux_rst_n -> p0:afi_rst_n
+	wire   [1:0] m0_phy_mux_afi_dqs_burst;           // m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
+	wire  [27:0] m0_phy_mux_afi_addr;                // m0:phy_mux_addr -> p0:afi_addr
+	wire   [5:0] m0_phy_mux_afi_ba;                  // m0:phy_mux_ba -> p0:afi_ba
+	wire   [5:0] p0_afi_afi_wlat;                    // p0:afi_wlat -> m0:phy_mux_wlat
+	wire   [3:0] m0_phy_mux_afi_dm;                  // m0:phy_mux_dm -> p0:afi_dm
+	wire         p0_afi_afi_cal_fail;                // p0:afi_cal_fail -> m0:phy_mux_cal_fail
+	wire   [1:0] p0_afi_afi_rdata_valid;             // p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
+	wire   [1:0] m0_phy_mux_afi_we_n;                // m0:phy_mux_we_n -> p0:afi_we_n
+	wire   [1:0] m0_phy_mux_afi_cas_n;               // m0:phy_mux_cas_n -> p0:afi_cas_n
+	wire   [1:0] m0_phy_mux_afi_cs_n;                // m0:phy_mux_cs_n -> p0:afi_cs_n
+	wire   [1:0] m0_phy_mux_afi_rdata_en;            // m0:phy_mux_rdata_en -> p0:afi_rdata_en
+	wire   [1:0] m0_phy_mux_afi_odt;                 // m0:phy_mux_odt -> p0:afi_odt
+	wire   [1:0] m0_phy_mux_afi_ras_n;               // m0:phy_mux_ras_n -> p0:afi_ras_n
+	wire   [1:0] m0_phy_mux_afi_cke;                 // m0:phy_mux_cke -> p0:afi_cke
+	wire   [5:0] m0_afi_afi_rlat;                    // m0:afi_rlat -> c0:afi_rlat
+	wire         m0_afi_afi_cal_success;             // m0:afi_cal_success -> c0:afi_cal_success
+	wire  [31:0] m0_afi_afi_rdata;                   // m0:afi_rdata -> c0:afi_rdata
+	wire   [5:0] m0_afi_afi_wlat;                    // m0:afi_wlat -> c0:afi_wlat
+	wire         m0_afi_afi_cal_fail;                // m0:afi_cal_fail -> c0:afi_cal_fail
+	wire   [1:0] m0_afi_afi_rdata_valid;             // m0:afi_rdata_valid -> c0:afi_rdata_valid
+	wire         p0_avl_clk_clk;                     // p0:avl_clk -> s0:avl_clk
+	wire         p0_avl_reset_reset;                 // p0:avl_reset_n -> s0:avl_reset_n
+	wire         s0_pll_reconfig_scanclk;            // s0:scanclk -> pll0:scanclk
+	wire         s0_pll_reconfig_phaseupdown;        // s0:phaseupdown -> pll0:phaseupdown
+	wire   [2:0] s0_pll_reconfig_phasecounterselect; // s0:phasecounterselect -> pll0:phasecounterselect
+	wire         s0_pll_reconfig_phasestep;          // s0:phasestep -> pll0:phasestep
+	wire         pll0_pll_reconfig_phasedone;        // pll0:phasedone -> s0:phasedone
+	wire         s0_phase_detector_pd_ack;           // s0:pd_ack -> p0:pd_ack
+	wire         s0_phase_detector_pd_reset_n;       // s0:pd_reset_n -> p0:pd_reset_n
+	wire         p0_phase_detector_pd_down;          // p0:pd_down -> s0:pd_down
+	wire         p0_phase_detector_pd_up;            // p0:pd_up -> s0:pd_up
+	wire   [1:0] s0_afi_afi_rdata_en_full;           // s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
+	wire   [1:0] s0_afi_afi_wdata_valid;             // s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
+	wire  [31:0] m0_seq_mux_afi_rdata;               // m0:seq_mux_rdata -> s0:afi_rdata
+	wire  [31:0] s0_afi_afi_wdata;                   // s0:afi_wdata -> m0:seq_mux_wdata
+	wire   [1:0] s0_afi_afi_rst_n;                   // s0:afi_rst_n -> m0:seq_mux_rst_n
+	wire   [1:0] s0_afi_afi_dqs_burst;               // s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
+	wire  [27:0] s0_afi_afi_addr;                    // s0:afi_addr -> m0:seq_mux_addr
+	wire   [5:0] s0_afi_afi_ba;                      // s0:afi_ba -> m0:seq_mux_ba
+	wire   [3:0] s0_afi_afi_dm;                      // s0:afi_dm -> m0:seq_mux_dm
+	wire   [1:0] m0_seq_mux_afi_rdata_valid;         // m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
+	wire   [1:0] s0_afi_afi_we_n;                    // s0:afi_we_n -> m0:seq_mux_we_n
+	wire   [1:0] s0_afi_afi_cas_n;                   // s0:afi_cas_n -> m0:seq_mux_cas_n
+	wire   [1:0] s0_afi_afi_cs_n;                    // s0:afi_cs_n -> m0:seq_mux_cs_n
+	wire   [1:0] s0_afi_afi_rdata_en;                // s0:afi_rdata_en -> m0:seq_mux_rdata_en
+	wire   [1:0] s0_afi_afi_odt;                     // s0:afi_odt -> m0:seq_mux_odt
+	wire   [1:0] s0_afi_afi_ras_n;                   // s0:afi_ras_n -> m0:seq_mux_ras_n
+	wire   [1:0] s0_afi_afi_cke;                     // s0:afi_cke -> m0:seq_mux_cke
+	wire         s0_mux_sel_mux_sel;                 // s0:phy_mux_sel -> m0:mux_sel
+	wire   [5:0] s0_phy_phy_afi_rlat;                // s0:phy_afi_rlat -> p0:phy_afi_rlat
+	wire         p0_phy_phy_clk;                     // p0:phy_clk -> s0:phy_clk
+	wire   [4:0] s0_phy_phy_read_latency_counter;    // s0:phy_read_latency_counter -> p0:phy_read_latency_counter
+	wire   [5:0] s0_phy_phy_afi_wlat;                // s0:phy_afi_wlat -> p0:phy_afi_wlat
+	wire         s0_phy_phy_reset_mem_stable;        // s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_qr; // s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
+	wire   [0:0] s0_phy_phy_vfifo_rd_en_override;    // s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
+	wire   [0:0] s0_phy_phy_read_fifo_reset;         // s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
+	wire   [1:0] s0_phy_phy_write_fr_cycle_shifts;   // s0:phy_write_fr_cycle_shifts -> p0:phy_write_fr_cycle_shifts
+	wire         s0_phy_phy_cal_fail;                // s0:phy_cal_fail -> p0:phy_cal_fail
+	wire         s0_phy_phy_cal_success;             // s0:phy_cal_success -> p0:phy_cal_success
+	wire         p0_phy_phy_reset_n;                 // p0:phy_reset_n -> s0:phy_reset_n
+	wire  [31:0] s0_phy_phy_cal_debug_info;          // s0:phy_cal_debug_info -> p0:phy_cal_debug_info
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_hr; // s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
+	wire   [0:0] s0_phy_phy_read_increment_vfifo_fr; // s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
+	wire  [31:0] p0_phy_phy_read_fifo_q;             // p0:phy_read_fifo_q -> s0:phy_read_fifo_q
+	wire   [7:0] p0_calib_calib_skip_steps;          // p0:calib_skip_steps -> s0:calib_skip_steps
+	wire   [1:0] c0_afi_afi_rdata_en_full;           // c0:afi_rdata_en_full -> m0:afi_rdata_en_full
+	wire   [1:0] c0_afi_afi_wdata_valid;             // c0:afi_wdata_valid -> m0:afi_wdata_valid
+	wire  [31:0] c0_afi_afi_wdata;                   // c0:afi_wdata -> m0:afi_wdata
+	wire   [1:0] c0_afi_afi_rst_n;                   // c0:afi_rst_n -> m0:afi_rst_n
+	wire         c0_afi_afi_cal_req;                 // c0:afi_cal_req -> s0:afi_cal_req
+	wire   [1:0] c0_afi_afi_dqs_burst;               // c0:afi_dqs_burst -> m0:afi_dqs_burst
+	wire  [27:0] c0_afi_afi_addr;                    // c0:afi_addr -> m0:afi_addr
+	wire   [5:0] c0_afi_afi_ba;                      // c0:afi_ba -> m0:afi_ba
+	wire   [3:0] c0_afi_afi_dm;                      // c0:afi_dm -> m0:afi_dm
+	wire   [0:0] c0_afi_afi_mem_clk_disable;         // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
+	wire         c0_afi_afi_init_req;                // c0:afi_init_req -> s0:afi_init_req
+	wire   [1:0] c0_afi_afi_we_n;                    // c0:afi_we_n -> m0:afi_we_n
+	wire   [1:0] c0_afi_afi_cas_n;                   // c0:afi_cas_n -> m0:afi_cas_n
+	wire   [1:0] c0_afi_afi_cs_n;                    // c0:afi_cs_n -> m0:afi_cs_n
+	wire   [1:0] c0_afi_afi_rdata_en;                // c0:afi_rdata_en -> m0:afi_rdata_en
+	wire   [1:0] c0_afi_afi_odt;                     // c0:afi_odt -> m0:afi_odt
+	wire   [1:0] c0_afi_afi_ras_n;                   // c0:afi_ras_n -> m0:afi_ras_n
+	wire   [1:0] c0_afi_afi_cke;                     // c0:afi_cke -> m0:afi_cke
+
+	q_sys_mem_if_ddr3_emif_0_pll0 pll0 (
+		.global_reset_n     (global_reset_n),                     // global_reset.reset_n
+		.afi_clk            (afi_clk),                            //      afi_clk.clk
+		.afi_half_clk       (afi_half_clk),                       // afi_half_clk.clk
+		.pll_ref_clk        (pll_ref_clk),                        //  pll_ref_clk.clk
+		.pll_mem_clk        (pll_mem_clk),                        //  pll_sharing.pll_mem_clk
+		.pll_write_clk      (pll_write_clk),                      //             .pll_write_clk
+		.pll_locked         (pll_locked),                         //             .pll_locked
+		.pll_capture0_clk   (pll_capture0_clk),                   //             .pll_capture0_clk
+		.pll_capture1_clk   (pll_capture1_clk),                   //             .pll_capture1_clk
+		.phasecounterselect (s0_pll_reconfig_phasecounterselect), // pll_reconfig.phasecounterselect
+		.phasestep          (s0_pll_reconfig_phasestep),          //             .phasestep
+		.phaseupdown        (s0_pll_reconfig_phaseupdown),        //             .phaseupdown
+		.scanclk            (s0_pll_reconfig_scanclk),            //             .scanclk
+		.phasedone          (pll0_pll_reconfig_phasedone)         //             .phasedone
+	);
+
+	q_sys_mem_if_ddr3_emif_0_p0 p0 (
+		.global_reset_n              (global_reset_n),                     //        global_reset.reset_n
+		.soft_reset_n                (soft_reset_n),                       //          soft_reset.reset_n
+		.afi_reset_n                 (afi_reset_n),                        //           afi_reset.reset_n
+		.afi_reset_export_n          (afi_reset_export_n),                 //    afi_reset_export.reset_n
+		.afi_clk                     (afi_clk),                            //             afi_clk.clk
+		.afi_half_clk                (afi_half_clk),                       //        afi_half_clk.clk
+		.avl_clk                     (p0_avl_clk_clk),                     //             avl_clk.clk
+		.avl_reset_n                 (p0_avl_reset_reset),                 //           avl_reset.reset_n
+		.afi_addr                    (m0_phy_mux_afi_addr),                //                 afi.afi_addr
+		.afi_ba                      (m0_phy_mux_afi_ba),                  //                    .afi_ba
+		.afi_ras_n                   (m0_phy_mux_afi_ras_n),               //                    .afi_ras_n
+		.afi_we_n                    (m0_phy_mux_afi_we_n),                //                    .afi_we_n
+		.afi_cas_n                   (m0_phy_mux_afi_cas_n),               //                    .afi_cas_n
+		.afi_odt                     (m0_phy_mux_afi_odt),                 //                    .afi_odt
+		.afi_cke                     (m0_phy_mux_afi_cke),                 //                    .afi_cke
+		.afi_cs_n                    (m0_phy_mux_afi_cs_n),                //                    .afi_cs_n
+		.afi_dqs_burst               (m0_phy_mux_afi_dqs_burst),           //                    .afi_dqs_burst
+		.afi_wdata_valid             (m0_phy_mux_afi_wdata_valid),         //                    .afi_wdata_valid
+		.afi_wdata                   (m0_phy_mux_afi_wdata),               //                    .afi_wdata
+		.afi_dm                      (m0_phy_mux_afi_dm),                  //                    .afi_dm
+		.afi_rdata                   (p0_afi_afi_rdata),                   //                    .afi_rdata
+		.afi_rst_n                   (m0_phy_mux_afi_rst_n),               //                    .afi_rst_n
+		.afi_rdata_en                (m0_phy_mux_afi_rdata_en),            //                    .afi_rdata_en
+		.afi_rdata_en_full           (m0_phy_mux_afi_rdata_en_full),       //                    .afi_rdata_en_full
+		.afi_rdata_valid             (p0_afi_afi_rdata_valid),             //                    .afi_rdata_valid
+		.afi_cal_success             (p0_afi_afi_cal_success),             //                    .afi_cal_success
+		.afi_cal_fail                (p0_afi_afi_cal_fail),                //                    .afi_cal_fail
+		.afi_wlat                    (p0_afi_afi_wlat),                    //                    .afi_wlat
+		.afi_rlat                    (p0_afi_afi_rlat),                    //                    .afi_rlat
+		.phy_clk                     (p0_phy_phy_clk),                     //                 phy.phy_clk
+		.phy_reset_n                 (p0_phy_phy_reset_n),                 //                    .phy_reset_n
+		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),    //                    .phy_read_latency_counter
+		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                //                    .phy_afi_wlat
+		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                //                    .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), //                    .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), //                    .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), //                    .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),        //                    .phy_reset_mem_stable
+		.phy_cal_success             (s0_phy_phy_cal_success),             //                    .phy_cal_success
+		.phy_cal_fail                (s0_phy_phy_cal_fail),                //                    .phy_cal_fail
+		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),          //                    .phy_cal_debug_info
+		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),         //                    .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),    //                    .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),             //                    .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (s0_phy_phy_write_fr_cycle_shifts),   //                    .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (p0_calib_calib_skip_steps),          //               calib.calib_skip_steps
+		.pd_reset_n                  (s0_phase_detector_pd_reset_n),       //      phase_detector.pd_reset_n
+		.pd_ack                      (s0_phase_detector_pd_ack),           //                    .pd_ack
+		.pd_up                       (p0_phase_detector_pd_up),            //                    .pd_up
+		.pd_down                     (p0_phase_detector_pd_down),          //                    .pd_down
+		.afi_mem_clk_disable         (c0_afi_afi_mem_clk_disable),         // afi_mem_clk_disable.afi_mem_clk_disable
+		.pll_mem_clk                 (pll_mem_clk),                        //         pll_sharing.pll_mem_clk
+		.pll_write_clk               (pll_write_clk),                      //                    .pll_write_clk
+		.pll_locked                  (pll_locked),                         //                    .pll_locked
+		.pll_capture0_clk            (pll_capture0_clk),                   //                    .pll_capture0_clk
+		.pll_capture1_clk            (pll_capture1_clk),                   //                    .pll_capture1_clk
+		.mem_a                       (mem_a),                              //              memory.mem_a
+		.mem_ba                      (mem_ba),                             //                    .mem_ba
+		.mem_ck                      (mem_ck),                             //                    .mem_ck
+		.mem_ck_n                    (mem_ck_n),                           //                    .mem_ck_n
+		.mem_cke                     (mem_cke),                            //                    .mem_cke
+		.mem_cs_n                    (mem_cs_n),                           //                    .mem_cs_n
+		.mem_dm                      (mem_dm),                             //                    .mem_dm
+		.mem_ras_n                   (mem_ras_n),                          //                    .mem_ras_n
+		.mem_cas_n                   (mem_cas_n),                          //                    .mem_cas_n
+		.mem_we_n                    (mem_we_n),                           //                    .mem_we_n
+		.mem_reset_n                 (mem_reset_n),                        //                    .mem_reset_n
+		.mem_dq                      (mem_dq),                             //                    .mem_dq
+		.mem_dqs                     (mem_dqs),                            //                    .mem_dqs
+		.mem_dqs_n                   (mem_dqs_n),                          //                    .mem_dqs_n
+		.mem_odt                     (mem_odt),                            //                    .mem_odt
+		.csr_soft_reset_req          (1'b0)                                //         (terminated)
+	);
+
+	afi_mux_ddr3_ddrx #(
+		.AFI_RATE_RATIO            (2),
+		.AFI_ADDR_WIDTH            (28),
+		.AFI_BANKADDR_WIDTH        (6),
+		.AFI_CONTROL_WIDTH         (2),
+		.AFI_CS_WIDTH              (2),
+		.AFI_CLK_EN_WIDTH          (2),
+		.AFI_DM_WIDTH              (4),
+		.AFI_DQ_WIDTH              (32),
+		.AFI_ODT_WIDTH             (2),
+		.AFI_WRITE_DQS_WIDTH       (2),
+		.AFI_RLAT_WIDTH            (6),
+		.AFI_WLAT_WIDTH            (6),
+		.AFI_RRANK_WIDTH           (2),
+		.AFI_WRANK_WIDTH           (2),
+		.MRS_MIRROR_PING_PONG_ATSO (0)
+	) m0 (
+		.clk                   (afi_clk),                      //     clk.clk
+		.afi_addr              (c0_afi_afi_addr),              //     afi.afi_addr
+		.afi_ba                (c0_afi_afi_ba),                //        .afi_ba
+		.afi_ras_n             (c0_afi_afi_ras_n),             //        .afi_ras_n
+		.afi_we_n              (c0_afi_afi_we_n),              //        .afi_we_n
+		.afi_cas_n             (c0_afi_afi_cas_n),             //        .afi_cas_n
+		.afi_odt               (c0_afi_afi_odt),               //        .afi_odt
+		.afi_cke               (c0_afi_afi_cke),               //        .afi_cke
+		.afi_cs_n              (c0_afi_afi_cs_n),              //        .afi_cs_n
+		.afi_dqs_burst         (c0_afi_afi_dqs_burst),         //        .afi_dqs_burst
+		.afi_wdata_valid       (c0_afi_afi_wdata_valid),       //        .afi_wdata_valid
+		.afi_wdata             (c0_afi_afi_wdata),             //        .afi_wdata
+		.afi_dm                (c0_afi_afi_dm),                //        .afi_dm
+		.afi_rdata             (m0_afi_afi_rdata),             //        .afi_rdata
+		.afi_rst_n             (c0_afi_afi_rst_n),             //        .afi_rst_n
+		.afi_rdata_en          (c0_afi_afi_rdata_en),          //        .afi_rdata_en
+		.afi_rdata_en_full     (c0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
+		.afi_rdata_valid       (m0_afi_afi_rdata_valid),       //        .afi_rdata_valid
+		.afi_cal_success       (m0_afi_afi_cal_success),       //        .afi_cal_success
+		.afi_cal_fail          (m0_afi_afi_cal_fail),          //        .afi_cal_fail
+		.afi_wlat              (m0_afi_afi_wlat),              //        .afi_wlat
+		.afi_rlat              (m0_afi_afi_rlat),              //        .afi_rlat
+		.phy_mux_addr          (m0_phy_mux_afi_addr),          // phy_mux.afi_addr
+		.phy_mux_ba            (m0_phy_mux_afi_ba),            //        .afi_ba
+		.phy_mux_ras_n         (m0_phy_mux_afi_ras_n),         //        .afi_ras_n
+		.phy_mux_we_n          (m0_phy_mux_afi_we_n),          //        .afi_we_n
+		.phy_mux_cas_n         (m0_phy_mux_afi_cas_n),         //        .afi_cas_n
+		.phy_mux_odt           (m0_phy_mux_afi_odt),           //        .afi_odt
+		.phy_mux_cke           (m0_phy_mux_afi_cke),           //        .afi_cke
+		.phy_mux_cs_n          (m0_phy_mux_afi_cs_n),          //        .afi_cs_n
+		.phy_mux_dqs_burst     (m0_phy_mux_afi_dqs_burst),     //        .afi_dqs_burst
+		.phy_mux_wdata_valid   (m0_phy_mux_afi_wdata_valid),   //        .afi_wdata_valid
+		.phy_mux_wdata         (m0_phy_mux_afi_wdata),         //        .afi_wdata
+		.phy_mux_dm            (m0_phy_mux_afi_dm),            //        .afi_dm
+		.phy_mux_rdata         (p0_afi_afi_rdata),             //        .afi_rdata
+		.phy_mux_rst_n         (m0_phy_mux_afi_rst_n),         //        .afi_rst_n
+		.phy_mux_rdata_en      (m0_phy_mux_afi_rdata_en),      //        .afi_rdata_en
+		.phy_mux_rdata_en_full (m0_phy_mux_afi_rdata_en_full), //        .afi_rdata_en_full
+		.phy_mux_rdata_valid   (p0_afi_afi_rdata_valid),       //        .afi_rdata_valid
+		.phy_mux_cal_success   (p0_afi_afi_cal_success),       //        .afi_cal_success
+		.phy_mux_cal_fail      (p0_afi_afi_cal_fail),          //        .afi_cal_fail
+		.phy_mux_wlat          (p0_afi_afi_wlat),              //        .afi_wlat
+		.phy_mux_rlat          (p0_afi_afi_rlat),              //        .afi_rlat
+		.seq_mux_addr          (s0_afi_afi_addr),              // seq_mux.afi_addr
+		.seq_mux_ba            (s0_afi_afi_ba),                //        .afi_ba
+		.seq_mux_ras_n         (s0_afi_afi_ras_n),             //        .afi_ras_n
+		.seq_mux_we_n          (s0_afi_afi_we_n),              //        .afi_we_n
+		.seq_mux_cas_n         (s0_afi_afi_cas_n),             //        .afi_cas_n
+		.seq_mux_odt           (s0_afi_afi_odt),               //        .afi_odt
+		.seq_mux_cke           (s0_afi_afi_cke),               //        .afi_cke
+		.seq_mux_cs_n          (s0_afi_afi_cs_n),              //        .afi_cs_n
+		.seq_mux_dqs_burst     (s0_afi_afi_dqs_burst),         //        .afi_dqs_burst
+		.seq_mux_wdata_valid   (s0_afi_afi_wdata_valid),       //        .afi_wdata_valid
+		.seq_mux_wdata         (s0_afi_afi_wdata),             //        .afi_wdata
+		.seq_mux_dm            (s0_afi_afi_dm),                //        .afi_dm
+		.seq_mux_rdata         (m0_seq_mux_afi_rdata),         //        .afi_rdata
+		.seq_mux_rst_n         (s0_afi_afi_rst_n),             //        .afi_rst_n
+		.seq_mux_rdata_en      (s0_afi_afi_rdata_en),          //        .afi_rdata_en
+		.seq_mux_rdata_en_full (s0_afi_afi_rdata_en_full),     //        .afi_rdata_en_full
+		.seq_mux_rdata_valid   (m0_seq_mux_afi_rdata_valid),   //        .afi_rdata_valid
+		.mux_sel               (s0_mux_sel_mux_sel)            // mux_sel.mux_sel
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0 s0 (
+		.avl_clk                     (p0_avl_clk_clk),                     //          avl_clk.clk
+		.avl_reset_n                 (p0_avl_reset_reset),                 //        avl_reset.reset_n
+		.phasecounterselect          (s0_pll_reconfig_phasecounterselect), //     pll_reconfig.phasecounterselect
+		.phasestep                   (s0_pll_reconfig_phasestep),          //                 .phasestep
+		.phaseupdown                 (s0_pll_reconfig_phaseupdown),        //                 .phaseupdown
+		.scanclk                     (s0_pll_reconfig_scanclk),            //                 .scanclk
+		.phasedone                   (pll0_pll_reconfig_phasedone),        //                 .phasedone
+		.afi_init_req                (c0_afi_afi_init_req),                // afi_init_cal_req.afi_init_req
+		.afi_cal_req                 (c0_afi_afi_cal_req),                 //                 .afi_cal_req
+		.pd_reset_n                  (s0_phase_detector_pd_reset_n),       //   phase_detector.pd_reset_n
+		.pd_ack                      (s0_phase_detector_pd_ack),           //                 .pd_ack
+		.pd_up                       (p0_phase_detector_pd_up),            //                 .pd_up
+		.pd_down                     (p0_phase_detector_pd_down),          //                 .pd_down
+		.phy_clk                     (p0_phy_phy_clk),                     //              phy.phy_clk
+		.phy_reset_n                 (p0_phy_phy_reset_n),                 //                 .phy_reset_n
+		.phy_read_latency_counter    (s0_phy_phy_read_latency_counter),    //                 .phy_read_latency_counter
+		.phy_afi_wlat                (s0_phy_phy_afi_wlat),                //                 .phy_afi_wlat
+		.phy_afi_rlat                (s0_phy_phy_afi_rlat),                //                 .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), //                 .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), //                 .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), //                 .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (s0_phy_phy_reset_mem_stable),        //                 .phy_reset_mem_stable
+		.phy_cal_success             (s0_phy_phy_cal_success),             //                 .phy_cal_success
+		.phy_cal_fail                (s0_phy_phy_cal_fail),                //                 .phy_cal_fail
+		.phy_cal_debug_info          (s0_phy_phy_cal_debug_info),          //                 .phy_cal_debug_info
+		.phy_read_fifo_reset         (s0_phy_phy_read_fifo_reset),         //                 .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (s0_phy_phy_vfifo_rd_en_override),    //                 .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (p0_phy_phy_read_fifo_q),             //                 .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (s0_phy_phy_write_fr_cycle_shifts),   //                 .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (p0_calib_calib_skip_steps),          //            calib.calib_skip_steps
+		.phy_mux_sel                 (s0_mux_sel_mux_sel),                 //          mux_sel.mux_sel
+		.afi_clk                     (afi_clk),                            //          afi_clk.clk
+		.afi_reset_n                 (afi_reset_n),                        //        afi_reset.reset_n
+		.afi_addr                    (s0_afi_afi_addr),                    //              afi.afi_addr
+		.afi_ba                      (s0_afi_afi_ba),                      //                 .afi_ba
+		.afi_ras_n                   (s0_afi_afi_ras_n),                   //                 .afi_ras_n
+		.afi_we_n                    (s0_afi_afi_we_n),                    //                 .afi_we_n
+		.afi_cas_n                   (s0_afi_afi_cas_n),                   //                 .afi_cas_n
+		.afi_odt                     (s0_afi_afi_odt),                     //                 .afi_odt
+		.afi_cke                     (s0_afi_afi_cke),                     //                 .afi_cke
+		.afi_cs_n                    (s0_afi_afi_cs_n),                    //                 .afi_cs_n
+		.afi_dqs_burst               (s0_afi_afi_dqs_burst),               //                 .afi_dqs_burst
+		.afi_wdata_valid             (s0_afi_afi_wdata_valid),             //                 .afi_wdata_valid
+		.afi_wdata                   (s0_afi_afi_wdata),                   //                 .afi_wdata
+		.afi_dm                      (s0_afi_afi_dm),                      //                 .afi_dm
+		.afi_rdata                   (m0_seq_mux_afi_rdata),               //                 .afi_rdata
+		.afi_rst_n                   (s0_afi_afi_rst_n),                   //                 .afi_rst_n
+		.afi_rdata_en                (s0_afi_afi_rdata_en),                //                 .afi_rdata_en
+		.afi_rdata_en_full           (s0_afi_afi_rdata_en_full),           //                 .afi_rdata_en_full
+		.afi_rdata_valid             (m0_seq_mux_afi_rdata_valid)          //                 .afi_rdata_valid
+	);
+
+	q_sys_mem_if_ddr3_emif_0_c0 c0 (
+		.afi_reset_n         (afi_reset_n),                //    afi_reset.reset_n
+		.afi_clk             (afi_clk),                    //      afi_clk.clk
+		.afi_half_clk        (afi_half_clk),               // afi_half_clk.clk
+		.local_init_done     (local_init_done),            //       status.local_init_done
+		.local_cal_success   (local_cal_success),          //             .local_cal_success
+		.local_cal_fail      (local_cal_fail),             //             .local_cal_fail
+		.afi_addr            (c0_afi_afi_addr),            //          afi.afi_addr
+		.afi_ba              (c0_afi_afi_ba),              //             .afi_ba
+		.afi_ras_n           (c0_afi_afi_ras_n),           //             .afi_ras_n
+		.afi_we_n            (c0_afi_afi_we_n),            //             .afi_we_n
+		.afi_cas_n           (c0_afi_afi_cas_n),           //             .afi_cas_n
+		.afi_odt             (c0_afi_afi_odt),             //             .afi_odt
+		.afi_cke             (c0_afi_afi_cke),             //             .afi_cke
+		.afi_cs_n            (c0_afi_afi_cs_n),            //             .afi_cs_n
+		.afi_dqs_burst       (c0_afi_afi_dqs_burst),       //             .afi_dqs_burst
+		.afi_wdata_valid     (c0_afi_afi_wdata_valid),     //             .afi_wdata_valid
+		.afi_wdata           (c0_afi_afi_wdata),           //             .afi_wdata
+		.afi_dm              (c0_afi_afi_dm),              //             .afi_dm
+		.afi_rdata           (m0_afi_afi_rdata),           //             .afi_rdata
+		.afi_rst_n           (c0_afi_afi_rst_n),           //             .afi_rst_n
+		.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), //             .afi_mem_clk_disable
+		.afi_init_req        (c0_afi_afi_init_req),        //             .afi_init_req
+		.afi_cal_req         (c0_afi_afi_cal_req),         //             .afi_cal_req
+		.afi_rdata_en        (c0_afi_afi_rdata_en),        //             .afi_rdata_en
+		.afi_rdata_en_full   (c0_afi_afi_rdata_en_full),   //             .afi_rdata_en_full
+		.afi_rdata_valid     (m0_afi_afi_rdata_valid),     //             .afi_rdata_valid
+		.afi_cal_success     (m0_afi_afi_cal_success),     //             .afi_cal_success
+		.afi_cal_fail        (m0_afi_afi_cal_fail),        //             .afi_cal_fail
+		.afi_wlat            (m0_afi_afi_wlat),            //             .afi_wlat
+		.afi_rlat            (m0_afi_afi_rlat),            //             .afi_rlat
+		.avl_ready           (avl_ready),                  //          avl.waitrequest_n
+		.avl_burstbegin      (avl_burstbegin),             //             .beginbursttransfer
+		.avl_addr            (avl_addr),                   //             .address
+		.avl_rdata_valid     (avl_rdata_valid),            //             .readdatavalid
+		.avl_rdata           (avl_rdata),                  //             .readdata
+		.avl_wdata           (avl_wdata),                  //             .writedata
+		.avl_be              (avl_be),                     //             .byteenable
+		.avl_read_req        (avl_read_req),               //             .read
+		.avl_write_req       (avl_write_req),              //             .write
+		.avl_size            (avl_size)                    //             .burstcount
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
new file mode 100644
index 0000000..edfb751
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_c0.v
@@ -0,0 +1,309 @@
+// q_sys_mem_if_ddr3_emif_0_c0.v
+
+// This file was auto-generated from alt_mem_if_nextgen_ddr3_controller_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mem_if_ddr3_emif_0_c0 (
+		input  wire        afi_reset_n,         //    afi_reset.reset_n
+		input  wire        afi_clk,             //      afi_clk.clk
+		input  wire        afi_half_clk,        // afi_half_clk.clk
+		output wire        local_init_done,     //       status.local_init_done
+		output wire        local_cal_success,   //             .local_cal_success
+		output wire        local_cal_fail,      //             .local_cal_fail
+		output wire [27:0] afi_addr,            //          afi.afi_addr
+		output wire [5:0]  afi_ba,              //             .afi_ba
+		output wire [1:0]  afi_ras_n,           //             .afi_ras_n
+		output wire [1:0]  afi_we_n,            //             .afi_we_n
+		output wire [1:0]  afi_cas_n,           //             .afi_cas_n
+		output wire [1:0]  afi_odt,             //             .afi_odt
+		output wire [1:0]  afi_cke,             //             .afi_cke
+		output wire [1:0]  afi_cs_n,            //             .afi_cs_n
+		output wire [1:0]  afi_dqs_burst,       //             .afi_dqs_burst
+		output wire [1:0]  afi_wdata_valid,     //             .afi_wdata_valid
+		output wire [31:0] afi_wdata,           //             .afi_wdata
+		output wire [3:0]  afi_dm,              //             .afi_dm
+		input  wire [31:0] afi_rdata,           //             .afi_rdata
+		output wire [1:0]  afi_rst_n,           //             .afi_rst_n
+		output wire [0:0]  afi_mem_clk_disable, //             .afi_mem_clk_disable
+		output wire        afi_init_req,        //             .afi_init_req
+		output wire        afi_cal_req,         //             .afi_cal_req
+		output wire [1:0]  afi_rdata_en,        //             .afi_rdata_en
+		output wire [1:0]  afi_rdata_en_full,   //             .afi_rdata_en_full
+		input  wire [1:0]  afi_rdata_valid,     //             .afi_rdata_valid
+		input  wire        afi_cal_success,     //             .afi_cal_success
+		input  wire        afi_cal_fail,        //             .afi_cal_fail
+		input  wire [5:0]  afi_wlat,            //             .afi_wlat
+		input  wire [5:0]  afi_rlat,            //             .afi_rlat
+		output wire        avl_ready,           //          avl.waitrequest_n
+		input  wire        avl_burstbegin,      //             .beginbursttransfer
+		input  wire [24:0] avl_addr,            //             .address
+		output wire        avl_rdata_valid,     //             .readdatavalid
+		output wire [31:0] avl_rdata,           //             .readdata
+		input  wire [31:0] avl_wdata,           //             .writedata
+		input  wire [3:0]  avl_be,              //             .byteenable
+		input  wire        avl_read_req,        //             .read
+		input  wire        avl_write_req,       //             .write
+		input  wire [2:0]  avl_size             //             .burstcount
+	);
+
+	wire         a0_native_st_itf_wr_data_begin;     // a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
+	wire         ng0_native_st_itf_rd_data_last;     // ng0:itf_rd_data_last -> a0:itf_rd_data_last
+	wire         a0_native_st_itf_cmd_autopercharge; // a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
+	wire         ng0_native_st_itf_rd_data_error;    // ng0:itf_rd_data_error -> a0:itf_rd_data_error
+	wire         a0_native_st_itf_cmd_priority;      // a0:itf_cmd_priority -> ng0:itf_cmd_priority
+	wire   [3:0] a0_native_st_itf_wr_data_byte_en;   // a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
+	wire   [7:0] ng0_native_st_itf_rd_data_id;       // ng0:itf_rd_data_id -> a0:itf_rd_data_id
+	wire  [31:0] a0_native_st_itf_wr_data;           // a0:itf_wr_data -> ng0:itf_wr_data
+	wire         a0_native_st_itf_wr_data_valid;     // a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
+	wire   [7:0] a0_native_st_itf_cmd_id;            // a0:itf_cmd_id -> ng0:itf_cmd_id
+	wire  [31:0] ng0_native_st_itf_rd_data;          // ng0:itf_rd_data -> a0:itf_rd_data
+	wire         ng0_native_st_itf_cmd_ready;        // ng0:itf_cmd_ready -> a0:itf_cmd_ready
+	wire         ng0_native_st_itf_rd_data_begin;    // ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
+	wire         a0_native_st_itf_cmd_multicast;     // a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
+	wire         a0_native_st_itf_wr_data_last;      // a0:itf_wr_data_last -> ng0:itf_wr_data_last
+	wire         ng0_native_st_itf_rd_data_valid;    // ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
+	wire         a0_native_st_itf_cmd_valid;         // a0:itf_cmd_valid -> ng0:itf_cmd_valid
+	wire         ng0_native_st_itf_wr_data_ready;    // ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
+	wire         a0_native_st_itf_rd_data_ready;     // a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
+	wire   [2:0] a0_native_st_itf_cmd_burstlen;      // a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
+	wire         a0_native_st_itf_cmd;               // a0:itf_cmd -> ng0:itf_cmd
+	wire  [24:0] a0_native_st_itf_cmd_address;       // a0:itf_cmd_address -> ng0:itf_cmd_address
+	wire   [7:0] a0_native_st_itf_wr_data_id;        // a0:itf_wr_data_id -> ng0:itf_wr_data_id
+
+	alt_mem_if_nextgen_ddr3_controller_core #(
+		.MEM_IF_ADDR_WIDTH                (14),
+		.MEM_IF_ROW_ADDR_WIDTH            (14),
+		.MEM_IF_COL_ADDR_WIDTH            (10),
+		.MEM_IF_DM_WIDTH                  (1),
+		.MEM_IF_DQS_WIDTH                 (1),
+		.MEM_IF_CS_WIDTH                  (1),
+		.MEM_IF_CHIP_BITS                 (1),
+		.MEM_IF_BANKADDR_WIDTH            (3),
+		.MEM_IF_DQ_WIDTH                  (8),
+		.MEM_IF_CLK_EN_WIDTH              (1),
+		.MEM_IF_CLK_PAIR_COUNT            (1),
+		.MEM_TRC                          (15),
+		.MEM_TRAS                         (11),
+		.MEM_TRCD                         (5),
+		.MEM_TRP                          (5),
+		.MEM_TREFI                        (2341),
+		.MEM_TRFC                         (34),
+		.MEM_TWR                          (5),
+		.MEM_TFAW                         (10),
+		.MEM_TRRD                         (2),
+		.MEM_TRTP                         (3),
+		.MEM_IF_ODT_WIDTH                 (1),
+		.MEM_WTCL_INT                     (5),
+		.MEM_IF_RD_TO_WR_TURNAROUND_OCT   (2),
+		.MEM_IF_WR_TO_RD_TURNAROUND_OCT   (3),
+		.CTL_RD_TO_PCH_EXTRA_CLK          (0),
+		.CTL_RD_TO_RD_EXTRA_CLK           (0),
+		.CTL_WR_TO_WR_EXTRA_CLK           (0),
+		.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK (1),
+		.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK (1),
+		.MEM_TCL                          (5),
+		.MEM_TMRD_CK                      (4),
+		.MEM_TWTR                         (6),
+		.CSR_ADDR_WIDTH                   (8),
+		.CSR_DATA_WIDTH                   (32),
+		.CSR_BE_WIDTH                     (4),
+		.CTL_CS_WIDTH                     (1),
+		.AVL_ADDR_WIDTH                   (25),
+		.AVL_BE_WIDTH                     (4),
+		.AVL_DATA_WIDTH                   (32),
+		.AVL_SIZE_WIDTH                   (3),
+		.DWIDTH_RATIO                     (4),
+		.CTL_ODT_ENABLED                  (0),
+		.CTL_OUTPUT_REGD                  (0),
+		.CTL_ECC_MULTIPLES_16_24_40_72    (1),
+		.CTL_REGDIMM_ENABLED              (0),
+		.CTL_TBP_NUM                      (4),
+		.CTL_USR_REFRESH                  (0),
+		.CFG_TYPE                         (2),
+		.CFG_INTERFACE_WIDTH              (8),
+		.CFG_BURST_LENGTH                 (8),
+		.CFG_ADDR_ORDER                   (0),
+		.CFG_PDN_EXIT_CYCLES              (10),
+		.CFG_POWER_SAVING_EXIT_CYCLES     (5),
+		.CFG_MEM_CLK_ENTRY_CYCLES         (20),
+		.CFG_SELF_RFSH_EXIT_CYCLES        (512),
+		.CFG_PORT_WIDTH_WRITE_ODT_CHIP    (1),
+		.CFG_PORT_WIDTH_READ_ODT_CHIP     (1),
+		.CFG_WRITE_ODT_CHIP               (1),
+		.CFG_READ_ODT_CHIP                (0),
+		.LOCAL_CS_WIDTH                   (0),
+		.CFG_CLR_INTR                     (0),
+		.CFG_ENABLE_NO_DM                 (0),
+		.MEM_ADD_LAT                      (0),
+		.CTL_ENABLE_BURST_INTERRUPT_INT   (0),
+		.CTL_ENABLE_BURST_TERMINATE_INT   (0),
+		.CFG_ERRCMD_FIFO_REG              (0),
+		.CFG_ECC_DECODER_REG              (0),
+		.CTL_ENABLE_WDATA_PATH_LATENCY    (0),
+		.CFG_STARVE_LIMIT                 (10),
+		.MEM_AUTO_PD_CYCLES               (0),
+		.CONTINUE_AFTER_CAL_FAIL          (0),
+		.MAX10_CFG                        (1),
+		.CFG_REORDER_DATA                 (1),
+		.CTL_CSR_ENABLED                  (0),
+		.CTL_ECC_ENABLED                  (0),
+		.CTL_ECC_AUTO_CORRECTION_ENABLED  (0),
+		.ENABLE_BURST_MERGE               (0),
+		.LOCAL_ID_WIDTH                   (8),
+		.RDBUFFER_ADDR_WIDTH              (7),
+		.WRBUFFER_ADDR_WIDTH              (6),
+		.MAX_PENDING_WR_CMD               (16),
+		.MAX_PENDING_RD_CMD               (32),
+		.CFG_DATA_REORDERING_TYPE         ("INTER_BANK"),
+		.USE_DQS_TRACKING                 (0),
+		.USE_SHADOW_REGS                  (0),
+		.AFI_RATE_RATIO                   (2),
+		.AFI_ADDR_WIDTH                   (28),
+		.AFI_BANKADDR_WIDTH               (6),
+		.AFI_CONTROL_WIDTH                (2),
+		.AFI_CS_WIDTH                     (2),
+		.AFI_CLK_EN_WIDTH                 (2),
+		.AFI_DM_WIDTH                     (4),
+		.AFI_DQ_WIDTH                     (32),
+		.AFI_ODT_WIDTH                    (2),
+		.AFI_WRITE_DQS_WIDTH              (2),
+		.AFI_RLAT_WIDTH                   (6),
+		.AFI_WLAT_WIDTH                   (6),
+		.AFI_RRANK_WIDTH                  (2),
+		.AFI_WRANK_WIDTH                  (2)
+	) ng0 (
+		.afi_reset_n             (afi_reset_n),                          //    afi_reset.reset_n
+		.afi_half_clk            (afi_half_clk),                         // afi_half_clk.clk
+		.afi_clk                 (afi_clk),                              //      afi_clk.clk
+		.local_init_done         (local_init_done),                      //       status.local_init_done
+		.local_cal_success       (local_cal_success),                    //             .local_cal_success
+		.local_cal_fail          (local_cal_fail),                       //             .local_cal_fail
+		.itf_cmd_ready           (ng0_native_st_itf_cmd_ready),          //    native_st.itf_cmd_ready
+		.itf_cmd_valid           (a0_native_st_itf_cmd_valid),           //             .itf_cmd_valid
+		.itf_cmd                 (a0_native_st_itf_cmd),                 //             .itf_cmd
+		.itf_cmd_address         (a0_native_st_itf_cmd_address),         //             .itf_cmd_address
+		.itf_cmd_burstlen        (a0_native_st_itf_cmd_burstlen),        //             .itf_cmd_burstlen
+		.itf_cmd_id              (a0_native_st_itf_cmd_id),              //             .itf_cmd_id
+		.itf_cmd_priority        (a0_native_st_itf_cmd_priority),        //             .itf_cmd_priority
+		.itf_cmd_autopercharge   (a0_native_st_itf_cmd_autopercharge),   //             .itf_cmd_autopercharge
+		.itf_cmd_multicast       (a0_native_st_itf_cmd_multicast),       //             .itf_cmd_multicast
+		.itf_wr_data_ready       (ng0_native_st_itf_wr_data_ready),      //             .itf_wr_data_ready
+		.itf_wr_data_valid       (a0_native_st_itf_wr_data_valid),       //             .itf_wr_data_valid
+		.itf_wr_data             (a0_native_st_itf_wr_data),             //             .itf_wr_data
+		.itf_wr_data_byte_en     (a0_native_st_itf_wr_data_byte_en),     //             .itf_wr_data_byte_en
+		.itf_wr_data_begin       (a0_native_st_itf_wr_data_begin),       //             .itf_wr_data_begin
+		.itf_wr_data_last        (a0_native_st_itf_wr_data_last),        //             .itf_wr_data_last
+		.itf_wr_data_id          (a0_native_st_itf_wr_data_id),          //             .itf_wr_data_id
+		.itf_rd_data_ready       (a0_native_st_itf_rd_data_ready),       //             .itf_rd_data_ready
+		.itf_rd_data_valid       (ng0_native_st_itf_rd_data_valid),      //             .itf_rd_data_valid
+		.itf_rd_data             (ng0_native_st_itf_rd_data),            //             .itf_rd_data
+		.itf_rd_data_error       (ng0_native_st_itf_rd_data_error),      //             .itf_rd_data_error
+		.itf_rd_data_begin       (ng0_native_st_itf_rd_data_begin),      //             .itf_rd_data_begin
+		.itf_rd_data_last        (ng0_native_st_itf_rd_data_last),       //             .itf_rd_data_last
+		.itf_rd_data_id          (ng0_native_st_itf_rd_data_id),         //             .itf_rd_data_id
+		.afi_addr                (afi_addr),                             //          afi.afi_addr
+		.afi_ba                  (afi_ba),                               //             .afi_ba
+		.afi_ras_n               (afi_ras_n),                            //             .afi_ras_n
+		.afi_we_n                (afi_we_n),                             //             .afi_we_n
+		.afi_cas_n               (afi_cas_n),                            //             .afi_cas_n
+		.afi_odt                 (afi_odt),                              //             .afi_odt
+		.afi_cke                 (afi_cke),                              //             .afi_cke
+		.afi_cs_n                (afi_cs_n),                             //             .afi_cs_n
+		.afi_dqs_burst           (afi_dqs_burst),                        //             .afi_dqs_burst
+		.afi_wdata_valid         (afi_wdata_valid),                      //             .afi_wdata_valid
+		.afi_wdata               (afi_wdata),                            //             .afi_wdata
+		.afi_dm                  (afi_dm),                               //             .afi_dm
+		.afi_rdata               (afi_rdata),                            //             .afi_rdata
+		.afi_rst_n               (afi_rst_n),                            //             .afi_rst_n
+		.afi_mem_clk_disable     (afi_mem_clk_disable),                  //             .afi_mem_clk_disable
+		.afi_init_req            (afi_init_req),                         //             .afi_init_req
+		.afi_cal_req             (afi_cal_req),                          //             .afi_cal_req
+		.afi_rdata_en            (afi_rdata_en),                         //             .afi_rdata_en
+		.afi_rdata_en_full       (afi_rdata_en_full),                    //             .afi_rdata_en_full
+		.afi_rdata_valid         (afi_rdata_valid),                      //             .afi_rdata_valid
+		.afi_cal_success         (afi_cal_success),                      //             .afi_cal_success
+		.afi_cal_fail            (afi_cal_fail),                         //             .afi_cal_fail
+		.afi_wlat                (afi_wlat),                             //             .afi_wlat
+		.afi_rlat                (afi_rlat),                             //             .afi_rlat
+		.csr_write_req           (1'b0),                                 //  (terminated)
+		.csr_read_req            (1'b0),                                 //  (terminated)
+		.csr_waitrequest         (),                                     //  (terminated)
+		.csr_addr                (8'b00000000),                          //  (terminated)
+		.csr_be                  (4'b0000),                              //  (terminated)
+		.csr_wdata               (32'b00000000000000000000000000000000), //  (terminated)
+		.csr_rdata               (),                                     //  (terminated)
+		.csr_rdata_valid         (),                                     //  (terminated)
+		.afi_seq_busy            (1'b0),                                 //  (terminated)
+		.afi_ctl_refresh_done    (),                                     //  (terminated)
+		.afi_ctl_long_idle       (),                                     //  (terminated)
+		.afi_rrank               (),                                     //  (terminated)
+		.afi_wrank               (),                                     //  (terminated)
+		.local_multicast         (1'b0),                                 //  (terminated)
+		.local_refresh_req       (1'b0),                                 //  (terminated)
+		.local_refresh_chip      (1'b0),                                 //  (terminated)
+		.local_refresh_ack       (),                                     //  (terminated)
+		.local_self_rfsh_req     (1'b0),                                 //  (terminated)
+		.local_self_rfsh_chip    (1'b0),                                 //  (terminated)
+		.local_self_rfsh_ack     (),                                     //  (terminated)
+		.local_deep_powerdn_req  (1'b0),                                 //  (terminated)
+		.local_deep_powerdn_chip (1'b0),                                 //  (terminated)
+		.local_deep_powerdn_ack  (),                                     //  (terminated)
+		.local_powerdn_ack       (),                                     //  (terminated)
+		.local_priority          (1'b0),                                 //  (terminated)
+		.local_zqcal_req         (1'b0),                                 //  (terminated)
+		.local_zqcal_chip        (1'b0)                                  //  (terminated)
+	);
+
+	alt_mem_ddrx_mm_st_converter #(
+		.AVL_SIZE_WIDTH   (3),
+		.AVL_ADDR_WIDTH   (25),
+		.AVL_DATA_WIDTH   (32),
+		.LOCAL_ID_WIDTH   (8),
+		.CFG_DWIDTH_RATIO (4)
+	) a0 (
+		.ctl_clk               (afi_clk),                            //        afi_clk.clk
+		.ctl_reset_n           (afi_reset_n),                        //      afi_reset.reset_n
+		.ctl_half_clk          (afi_half_clk),                       //   afi_half_clk.clk
+		.ctl_half_clk_reset_n  (afi_reset_n),                        // afi_half_reset.reset_n
+		.avl_ready             (avl_ready),                          //            avl.waitrequest_n
+		.avl_burstbegin        (avl_burstbegin),                     //               .beginbursttransfer
+		.avl_addr              (avl_addr),                           //               .address
+		.avl_rdata_valid       (avl_rdata_valid),                    //               .readdatavalid
+		.avl_rdata             (avl_rdata),                          //               .readdata
+		.avl_wdata             (avl_wdata),                          //               .writedata
+		.avl_be                (avl_be),                             //               .byteenable
+		.avl_read_req          (avl_read_req),                       //               .read
+		.avl_write_req         (avl_write_req),                      //               .write
+		.avl_size              (avl_size),                           //               .burstcount
+		.itf_cmd_ready         (ng0_native_st_itf_cmd_ready),        //      native_st.itf_cmd_ready
+		.itf_cmd_valid         (a0_native_st_itf_cmd_valid),         //               .itf_cmd_valid
+		.itf_cmd               (a0_native_st_itf_cmd),               //               .itf_cmd
+		.itf_cmd_address       (a0_native_st_itf_cmd_address),       //               .itf_cmd_address
+		.itf_cmd_burstlen      (a0_native_st_itf_cmd_burstlen),      //               .itf_cmd_burstlen
+		.itf_cmd_id            (a0_native_st_itf_cmd_id),            //               .itf_cmd_id
+		.itf_cmd_priority      (a0_native_st_itf_cmd_priority),      //               .itf_cmd_priority
+		.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), //               .itf_cmd_autopercharge
+		.itf_cmd_multicast     (a0_native_st_itf_cmd_multicast),     //               .itf_cmd_multicast
+		.itf_wr_data_ready     (ng0_native_st_itf_wr_data_ready),    //               .itf_wr_data_ready
+		.itf_wr_data_valid     (a0_native_st_itf_wr_data_valid),     //               .itf_wr_data_valid
+		.itf_wr_data           (a0_native_st_itf_wr_data),           //               .itf_wr_data
+		.itf_wr_data_byte_en   (a0_native_st_itf_wr_data_byte_en),   //               .itf_wr_data_byte_en
+		.itf_wr_data_begin     (a0_native_st_itf_wr_data_begin),     //               .itf_wr_data_begin
+		.itf_wr_data_last      (a0_native_st_itf_wr_data_last),      //               .itf_wr_data_last
+		.itf_wr_data_id        (a0_native_st_itf_wr_data_id),        //               .itf_wr_data_id
+		.itf_rd_data_ready     (a0_native_st_itf_rd_data_ready),     //               .itf_rd_data_ready
+		.itf_rd_data_valid     (ng0_native_st_itf_rd_data_valid),    //               .itf_rd_data_valid
+		.itf_rd_data           (ng0_native_st_itf_rd_data),          //               .itf_rd_data
+		.itf_rd_data_error     (ng0_native_st_itf_rd_data_error),    //               .itf_rd_data_error
+		.itf_rd_data_begin     (ng0_native_st_itf_rd_data_begin),    //               .itf_rd_data_begin
+		.itf_rd_data_last      (ng0_native_st_itf_rd_data_last),     //               .itf_rd_data_last
+		.itf_rd_data_id        (ng0_native_st_itf_rd_data_id),       //               .itf_rd_data_id
+		.local_multicast       (1'b0),                               //    (terminated)
+		.local_autopch_req     (1'b0),                               //    (terminated)
+		.local_priority        (1'b0)                                //    (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf
new file mode 100644
index 0000000..7b44c1c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.ppf
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan variation_name="q_sys_mem_if_ddr3_emif_0_p0" megafunction_name="altera_mem_if_ddr3_phy_core" specifies="all_ports">
+   <global>
+      <pin name="global_reset_n" direction="input" scope="internal" />
+      <pin name="soft_reset_n" direction="input" scope="internal" />
+      <pin name="csr_soft_reset_req" direction="input" scope="internal" />
+      <pin name="afi_reset_n" direction="output" scope="internal" />
+      <pin name="afi_reset_export_n" direction="output" scope="internal" />
+      <pin name="afi_clk" direction="input" scope="internal" />
+      <pin name="afi_half_clk" direction="input" scope="internal" />
+      <pin name="avl_clk" direction="output" scope="internal" />
+      <pin name="avl_reset_n" direction="output" scope="internal" />
+      <pin name="afi_addr[27..0]" direction="input" scope="internal" />
+      <pin name="afi_addr[0]" direction="input" scope="internal" />
+      <pin name="afi_addr[1]" direction="input" scope="internal" />
+      <pin name="afi_addr[2]" direction="input" scope="internal" />
+      <pin name="afi_addr[3]" direction="input" scope="internal" />
+      <pin name="afi_addr[4]" direction="input" scope="internal" />
+      <pin name="afi_addr[5]" direction="input" scope="internal" />
+      <pin name="afi_addr[6]" direction="input" scope="internal" />
+      <pin name="afi_addr[7]" direction="input" scope="internal" />
+      <pin name="afi_addr[8]" direction="input" scope="internal" />
+      <pin name="afi_addr[9]" direction="input" scope="internal" />
+      <pin name="afi_addr[10]" direction="input" scope="internal" />
+      <pin name="afi_addr[11]" direction="input" scope="internal" />
+      <pin name="afi_addr[12]" direction="input" scope="internal" />
+      <pin name="afi_addr[13]" direction="input" scope="internal" />
+      <pin name="afi_addr[14]" direction="input" scope="internal" />
+      <pin name="afi_addr[15]" direction="input" scope="internal" />
+      <pin name="afi_addr[16]" direction="input" scope="internal" />
+      <pin name="afi_addr[17]" direction="input" scope="internal" />
+      <pin name="afi_addr[18]" direction="input" scope="internal" />
+      <pin name="afi_addr[19]" direction="input" scope="internal" />
+      <pin name="afi_addr[20]" direction="input" scope="internal" />
+      <pin name="afi_addr[21]" direction="input" scope="internal" />
+      <pin name="afi_addr[22]" direction="input" scope="internal" />
+      <pin name="afi_addr[23]" direction="input" scope="internal" />
+      <pin name="afi_addr[24]" direction="input" scope="internal" />
+      <pin name="afi_addr[25]" direction="input" scope="internal" />
+      <pin name="afi_addr[26]" direction="input" scope="internal" />
+      <pin name="afi_addr[27]" direction="input" scope="internal" />
+      <pin name="afi_ba[5..0]" direction="input" scope="internal" />
+      <pin name="afi_ba[0]" direction="input" scope="internal" />
+      <pin name="afi_ba[1]" direction="input" scope="internal" />
+      <pin name="afi_ba[2]" direction="input" scope="internal" />
+      <pin name="afi_ba[3]" direction="input" scope="internal" />
+      <pin name="afi_ba[4]" direction="input" scope="internal" />
+      <pin name="afi_ba[5]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[0]" direction="input" scope="internal" />
+      <pin name="afi_ras_n[1]" direction="input" scope="internal" />
+      <pin name="afi_we_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_we_n[0]" direction="input" scope="internal" />
+      <pin name="afi_we_n[1]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[0]" direction="input" scope="internal" />
+      <pin name="afi_cas_n[1]" direction="input" scope="internal" />
+      <pin name="afi_odt[1..0]" direction="input" scope="internal" />
+      <pin name="afi_odt[0]" direction="input" scope="internal" />
+      <pin name="afi_odt[1]" direction="input" scope="internal" />
+      <pin name="afi_cke[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cke[0]" direction="input" scope="internal" />
+      <pin name="afi_cke[1]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[0]" direction="input" scope="internal" />
+      <pin name="afi_cs_n[1]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[1..0]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[0]" direction="input" scope="internal" />
+      <pin name="afi_dqs_burst[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[1..0]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[0]" direction="input" scope="internal" />
+      <pin name="afi_wdata_valid[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata[31..0]" direction="input" scope="internal" />
+      <pin name="afi_wdata[0]" direction="input" scope="internal" />
+      <pin name="afi_wdata[1]" direction="input" scope="internal" />
+      <pin name="afi_wdata[2]" direction="input" scope="internal" />
+      <pin name="afi_wdata[3]" direction="input" scope="internal" />
+      <pin name="afi_wdata[4]" direction="input" scope="internal" />
+      <pin name="afi_wdata[5]" direction="input" scope="internal" />
+      <pin name="afi_wdata[6]" direction="input" scope="internal" />
+      <pin name="afi_wdata[7]" direction="input" scope="internal" />
+      <pin name="afi_wdata[8]" direction="input" scope="internal" />
+      <pin name="afi_wdata[9]" direction="input" scope="internal" />
+      <pin name="afi_wdata[10]" direction="input" scope="internal" />
+      <pin name="afi_wdata[11]" direction="input" scope="internal" />
+      <pin name="afi_wdata[12]" direction="input" scope="internal" />
+      <pin name="afi_wdata[13]" direction="input" scope="internal" />
+      <pin name="afi_wdata[14]" direction="input" scope="internal" />
+      <pin name="afi_wdata[15]" direction="input" scope="internal" />
+      <pin name="afi_wdata[16]" direction="input" scope="internal" />
+      <pin name="afi_wdata[17]" direction="input" scope="internal" />
+      <pin name="afi_wdata[18]" direction="input" scope="internal" />
+      <pin name="afi_wdata[19]" direction="input" scope="internal" />
+      <pin name="afi_wdata[20]" direction="input" scope="internal" />
+      <pin name="afi_wdata[21]" direction="input" scope="internal" />
+      <pin name="afi_wdata[22]" direction="input" scope="internal" />
+      <pin name="afi_wdata[23]" direction="input" scope="internal" />
+      <pin name="afi_wdata[24]" direction="input" scope="internal" />
+      <pin name="afi_wdata[25]" direction="input" scope="internal" />
+      <pin name="afi_wdata[26]" direction="input" scope="internal" />
+      <pin name="afi_wdata[27]" direction="input" scope="internal" />
+      <pin name="afi_wdata[28]" direction="input" scope="internal" />
+      <pin name="afi_wdata[29]" direction="input" scope="internal" />
+      <pin name="afi_wdata[30]" direction="input" scope="internal" />
+      <pin name="afi_wdata[31]" direction="input" scope="internal" />
+      <pin name="afi_dm[3..0]" direction="input" scope="internal" />
+      <pin name="afi_dm[0]" direction="input" scope="internal" />
+      <pin name="afi_dm[1]" direction="input" scope="internal" />
+      <pin name="afi_dm[2]" direction="input" scope="internal" />
+      <pin name="afi_dm[3]" direction="input" scope="internal" />
+      <pin name="afi_rdata[31..0]" direction="output" scope="internal" />
+      <pin name="afi_rdata[0]" direction="output" scope="internal" />
+      <pin name="afi_rdata[1]" direction="output" scope="internal" />
+      <pin name="afi_rdata[2]" direction="output" scope="internal" />
+      <pin name="afi_rdata[3]" direction="output" scope="internal" />
+      <pin name="afi_rdata[4]" direction="output" scope="internal" />
+      <pin name="afi_rdata[5]" direction="output" scope="internal" />
+      <pin name="afi_rdata[6]" direction="output" scope="internal" />
+      <pin name="afi_rdata[7]" direction="output" scope="internal" />
+      <pin name="afi_rdata[8]" direction="output" scope="internal" />
+      <pin name="afi_rdata[9]" direction="output" scope="internal" />
+      <pin name="afi_rdata[10]" direction="output" scope="internal" />
+      <pin name="afi_rdata[11]" direction="output" scope="internal" />
+      <pin name="afi_rdata[12]" direction="output" scope="internal" />
+      <pin name="afi_rdata[13]" direction="output" scope="internal" />
+      <pin name="afi_rdata[14]" direction="output" scope="internal" />
+      <pin name="afi_rdata[15]" direction="output" scope="internal" />
+      <pin name="afi_rdata[16]" direction="output" scope="internal" />
+      <pin name="afi_rdata[17]" direction="output" scope="internal" />
+      <pin name="afi_rdata[18]" direction="output" scope="internal" />
+      <pin name="afi_rdata[19]" direction="output" scope="internal" />
+      <pin name="afi_rdata[20]" direction="output" scope="internal" />
+      <pin name="afi_rdata[21]" direction="output" scope="internal" />
+      <pin name="afi_rdata[22]" direction="output" scope="internal" />
+      <pin name="afi_rdata[23]" direction="output" scope="internal" />
+      <pin name="afi_rdata[24]" direction="output" scope="internal" />
+      <pin name="afi_rdata[25]" direction="output" scope="internal" />
+      <pin name="afi_rdata[26]" direction="output" scope="internal" />
+      <pin name="afi_rdata[27]" direction="output" scope="internal" />
+      <pin name="afi_rdata[28]" direction="output" scope="internal" />
+      <pin name="afi_rdata[29]" direction="output" scope="internal" />
+      <pin name="afi_rdata[30]" direction="output" scope="internal" />
+      <pin name="afi_rdata[31]" direction="output" scope="internal" />
+      <pin name="afi_rst_n[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rst_n[0]" direction="input" scope="internal" />
+      <pin name="afi_rst_n[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[1..0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[0]" direction="input" scope="internal" />
+      <pin name="afi_rdata_en_full[1]" direction="input" scope="internal" />
+      <pin name="afi_rdata_valid[1..0]" direction="output" scope="internal" />
+      <pin name="afi_rdata_valid[0]" direction="output" scope="internal" />
+      <pin name="afi_rdata_valid[1]" direction="output" scope="internal" />
+      <pin name="afi_cal_success" direction="output" scope="internal" />
+      <pin name="afi_cal_fail" direction="output" scope="internal" />
+      <pin name="afi_wlat[5..0]" direction="output" scope="internal" />
+      <pin name="afi_wlat[0]" direction="output" scope="internal" />
+      <pin name="afi_wlat[1]" direction="output" scope="internal" />
+      <pin name="afi_wlat[2]" direction="output" scope="internal" />
+      <pin name="afi_wlat[3]" direction="output" scope="internal" />
+      <pin name="afi_wlat[4]" direction="output" scope="internal" />
+      <pin name="afi_wlat[5]" direction="output" scope="internal" />
+      <pin name="afi_rlat[5..0]" direction="output" scope="internal" />
+      <pin name="afi_rlat[0]" direction="output" scope="internal" />
+      <pin name="afi_rlat[1]" direction="output" scope="internal" />
+      <pin name="afi_rlat[2]" direction="output" scope="internal" />
+      <pin name="afi_rlat[3]" direction="output" scope="internal" />
+      <pin name="afi_rlat[4]" direction="output" scope="internal" />
+      <pin name="afi_rlat[5]" direction="output" scope="internal" />
+      <pin name="phy_clk" direction="output" scope="internal" />
+      <pin name="phy_reset_n" direction="output" scope="internal" />
+      <pin name="phy_read_latency_counter[4..0]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[0]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[1]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[2]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[3]" direction="input" scope="internal" />
+      <pin name="phy_read_latency_counter[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[5..0]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[0]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[1]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[2]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[3]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_wlat[5]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[5..0]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[0]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[1]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[2]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[3]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[4]" direction="input" scope="internal" />
+      <pin name="phy_afi_rlat[5]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_fr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_fr[0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_hr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_hr[0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_qr[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_increment_vfifo_qr[0]" direction="input" scope="internal" />
+      <pin name="phy_reset_mem_stable" direction="input" scope="internal" />
+      <pin name="phy_cal_success" direction="input" scope="internal" />
+      <pin name="phy_cal_fail" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[31..0]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[0]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[1]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[2]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[3]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[4]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[5]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[6]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[7]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[8]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[9]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[10]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[11]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[12]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[13]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[14]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[15]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[16]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[17]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[18]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[19]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[20]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[21]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[22]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[23]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[24]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[25]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[26]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[27]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[28]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[29]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[30]" direction="input" scope="internal" />
+      <pin name="phy_cal_debug_info[31]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_reset[0..0]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_reset[0]" direction="input" scope="internal" />
+      <pin name="phy_vfifo_rd_en_override[0..0]" direction="input" scope="internal" />
+      <pin name="phy_vfifo_rd_en_override[0]" direction="input" scope="internal" />
+      <pin name="phy_read_fifo_q[31..0]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[0]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[1]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[2]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[3]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[4]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[5]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[6]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[7]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[8]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[9]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[10]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[11]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[12]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[13]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[14]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[15]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[16]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[17]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[18]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[19]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[20]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[21]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[22]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[23]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[24]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[25]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[26]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[27]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[28]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[29]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[30]" direction="output" scope="internal" />
+      <pin name="phy_read_fifo_q[31]" direction="output" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[1..0]" direction="input" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[0]" direction="input" scope="internal" />
+      <pin name="phy_write_fr_cycle_shifts[1]" direction="input" scope="internal" />
+      <pin name="calib_skip_steps[7..0]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[0]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[1]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[2]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[3]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[4]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[5]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[6]" direction="output" scope="internal" />
+      <pin name="calib_skip_steps[7]" direction="output" scope="internal" />
+      <pin name="pd_reset_n" direction="input" scope="internal" />
+      <pin name="pd_ack" direction="input" scope="internal" />
+      <pin name="pd_up" direction="output" scope="internal" />
+      <pin name="pd_down" direction="output" scope="internal" />
+      <pin name="afi_mem_clk_disable[0..0]" direction="input" scope="internal" />
+      <pin name="afi_mem_clk_disable[0]" direction="input" scope="internal" />
+      <pin name="pll_mem_clk" direction="input" scope="internal" />
+      <pin name="pll_write_clk" direction="input" scope="internal" />
+      <pin name="pll_locked" direction="input" scope="internal" />
+      <pin name="pll_capture0_clk" direction="input" scope="internal" />
+      <pin name="pll_capture1_clk" direction="input" scope="internal" />
+      <pin name="mem_a[13..0]" direction="output" scope="external" />
+      <pin name="mem_a[0]" direction="output" scope="external" />
+      <pin name="mem_a[1]" direction="output" scope="external" />
+      <pin name="mem_a[2]" direction="output" scope="external" />
+      <pin name="mem_a[3]" direction="output" scope="external" />
+      <pin name="mem_a[4]" direction="output" scope="external" />
+      <pin name="mem_a[5]" direction="output" scope="external" />
+      <pin name="mem_a[6]" direction="output" scope="external" />
+      <pin name="mem_a[7]" direction="output" scope="external" />
+      <pin name="mem_a[8]" direction="output" scope="external" />
+      <pin name="mem_a[9]" direction="output" scope="external" />
+      <pin name="mem_a[10]" direction="output" scope="external" />
+      <pin name="mem_a[11]" direction="output" scope="external" />
+      <pin name="mem_a[12]" direction="output" scope="external" />
+      <pin name="mem_a[13]" direction="output" scope="external" />
+      <pin name="mem_ba[2..0]" direction="output" scope="external" />
+      <pin name="mem_ba[0]" direction="output" scope="external" />
+      <pin name="mem_ba[1]" direction="output" scope="external" />
+      <pin name="mem_ba[2]" direction="output" scope="external" />
+      <pin name="mem_ck[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_ck[0]" direction="bidir" scope="external" />
+      <pin name="mem_ck_n[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_ck_n[0]" direction="bidir" scope="external" />
+      <pin name="mem_cke[0..0]" direction="output" scope="external" />
+      <pin name="mem_cke[0]" direction="output" scope="external" />
+      <pin name="mem_cs_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_cs_n[0]" direction="output" scope="external" />
+      <pin name="mem_dm[0..0]" direction="output" scope="external" />
+      <pin name="mem_dm[0]" direction="output" scope="external" />
+      <pin name="mem_ras_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_ras_n[0]" direction="output" scope="external" />
+      <pin name="mem_cas_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_cas_n[0]" direction="output" scope="external" />
+      <pin name="mem_we_n[0..0]" direction="output" scope="external" />
+      <pin name="mem_we_n[0]" direction="output" scope="external" />
+      <pin name="mem_reset_n" direction="output" scope="external" />
+      <pin name="mem_dq[7..0]" direction="bidir" scope="external" />
+      <pin name="mem_dq[0]" direction="bidir" scope="external" />
+      <pin name="mem_dq[1]" direction="bidir" scope="external" />
+      <pin name="mem_dq[2]" direction="bidir" scope="external" />
+      <pin name="mem_dq[3]" direction="bidir" scope="external" />
+      <pin name="mem_dq[4]" direction="bidir" scope="external" />
+      <pin name="mem_dq[5]" direction="bidir" scope="external" />
+      <pin name="mem_dq[6]" direction="bidir" scope="external" />
+      <pin name="mem_dq[7]" direction="bidir" scope="external" />
+      <pin name="mem_dqs[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs[0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs_n[0..0]" direction="bidir" scope="external" />
+      <pin name="mem_dqs_n[0]" direction="bidir" scope="external" />
+      <pin name="mem_odt[0..0]" direction="output" scope="external" />
+      <pin name="mem_odt[0]" direction="output" scope="external" />
+   </global>
+</pinplan>
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc
new file mode 100644
index 0000000..b6f498f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sdc
@@ -0,0 +1,480 @@
+# (C) 2001-2018 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+#####################################################################
+#
+# THIS IS AN AUTO-GENERATED FILE!
+# -------------------------------
+# If you modify this files, all your changes will be lost if you
+# regenerate the core!
+#
+# FILE DESCRIPTION
+# ----------------
+# This file contains the timing constraints for the UniPHY memory
+# interface.
+#    * The timing parameters used by this file are assigned
+#      in the q_sys_mem_if_ddr3_emif_0_p0_timing.tcl script.
+#    * The helper routines are defined in q_sys_mem_if_ddr3_emif_0_p0_pin_map.tcl
+#
+# NOTE
+# ----
+
+set script_dir [file dirname [info script]]
+
+source "$script_dir/q_sys_mem_if_ddr3_emif_0_p0_parameters.tcl"
+source "$script_dir/q_sys_mem_if_ddr3_emif_0_p0_timing.tcl"
+source "$script_dir/q_sys_mem_if_ddr3_emif_0_p0_pin_map.tcl"
+
+load_package ddr_timing_model
+
+set synthesis_flow 0
+set sta_flow 0
+set fit_flow 0
+if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" } {
+	set synthesis_flow 1
+} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } {
+	set sta_flow 1
+} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_fit" } {
+	set fit_flow 1
+}
+
+set is_es 0
+if { [string match -nocase "*es" $::TimeQuestInfo(part)] } {
+	set is_es 1
+}
+
+####################
+#                  #
+# GENERAL SETTINGS #
+#                  #
+####################
+
+# This is a global setting and will apply to the whole design.
+# This setting is required for the memory interface to be
+# properly constrained.
+derive_clock_uncertainty
+
+# Debug switch. Change to 1 to get more run-time debug information
+set debug 0
+
+# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision
+set_time_format -unit ns -decimal_places 3
+
+# Determine if entity names are on
+set entity_names_on [ q_sys_mem_if_ddr3_emif_0_p0_are_entity_names_on ]
+
+##################
+#                #
+# QUERIED TIMING #
+#                #
+##################
+
+set io_standard "$::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_io_standard CLASS I"
+
+
+set outputDQSpathjitter 0.060
+set outputDQSpathjitter_setup_prop 0.25
+set tJITper 0.253 
+
+##################
+#                #
+# DERIVED TIMING #
+#                #
+##################
+
+# These parameters are used to make constraints more readeable
+
+# Half of memory clock cycle
+set half_period [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr $t(CK) / 2.0 ] ]
+
+# Half of reference clock
+set ref_half_period [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr $t(refCK) / 2.0 ] ]
+
+# AFI cycle
+set tCK_AFI [ expr $t(CK) * 2.0 ]
+
+# Minimum delay on data output pins
+set t(wru_output_min_delay_external) [expr $t(DH) + $board(intra_DQS_group_skew)/2 + $ISI(DQ)/2 + $ISI(DQS)/2 - $board(DQ_DQS_skew)]
+set t(wru_output_min_delay_internal) [expr $outputDQSpathjitter*(1.0-$outputDQSpathjitter_setup_prop) + $SSN(rel_pullin_o)]
+set data_output_min_delay [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr - $t(wru_output_min_delay_external) - $t(wru_output_min_delay_internal)]]
+
+# Maximum delay on data output pins
+set t(wru_output_max_delay_external) [expr $t(DS) + $board(intra_DQS_group_skew)/2 + $ISI(DQ)/2 + $ISI(DQS)/2 + $board(DQ_DQS_skew)]
+set t(wru_output_max_delay_internal) [expr $outputDQSpathjitter*$outputDQSpathjitter_setup_prop + $SSN(rel_pushout_o)]
+set data_output_max_delay [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr $t(wru_output_max_delay_external) + $t(wru_output_max_delay_internal)]]
+
+# Minimum delay on address and command paths
+set t(ac_output_min_delay_external) [expr $t(IH) + $board(intra_addr_ctrl_skew) + $ISI(addresscmd_hold) - $board(addresscmd_CK_skew)]
+set t(ac_output_min_delay_internal) [expr $outputDQSpathjitter*(1.0-$outputDQSpathjitter_setup_prop) + $SSN(rel_pullin_o)]
+set ac_min_delay [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr - $t(ac_output_min_delay_external) - $t(ac_output_min_delay_internal)]]
+
+# Maximum delay on address and command paths
+set t(ac_output_max_delay_external) [expr $t(IS) + $board(intra_addr_ctrl_skew) + $ISI(addresscmd_setup) + $board(addresscmd_CK_skew)]
+set t(ac_output_max_delay_internal) [expr $outputDQSpathjitter*$outputDQSpathjitter_setup_prop + $SSN(rel_pushout_o)]
+set ac_max_delay [ q_sys_mem_if_ddr3_emif_0_p0_round_3dp [ expr $t(ac_output_max_delay_external) + $t(ac_output_max_delay_internal)]]
+
+if { $debug } {
+	post_message -type info "SDC: Computed Parameters:"
+	post_message -type info "SDC: --------------------"
+	post_message -type info "SDC: half_period: $half_period"
+	post_message -type info "SDC: data_output_min_delay: $data_output_min_delay"
+	post_message -type info "SDC: data_output_max_delay: $data_output_max_delay"
+	post_message -type info "SDC: data_input_min_delay: $data_input_min_delay"
+	post_message -type info "SDC: data_input_max_delay: $data_input_max_delay"
+	post_message -type info "SDC: ac_min_delay: $ac_min_delay"
+	post_message -type info "SDC: ac_max_delay: $ac_max_delay"
+	post_message -type info "SDC: Using Timing Models: Micro"
+}
+
+# This is the main call to the netlist traversal routines
+# that will automatically find all pins and registers required
+# to apply timing constraints.
+# During the fitter, the routines will be called only once
+# and cached data will be used in all subsequent calls.
+if { ! [ info exists q_sys_mem_if_ddr3_emif_0_p0_sdc_cache ] } {
+	set q_sys_mem_if_ddr3_emif_0_p0_sdc_cache 1
+	q_sys_mem_if_ddr3_emif_0_p0_initialize_ddr_db q_sys_mem_if_ddr3_emif_0_p0_ddr_db
+} else {
+	if { $debug } {
+		post_message -type info "SDC: reusing cached DDR DB"
+	}
+}
+
+# If multiple instances of this core are present in the
+# design they will all be constrained through the
+# following loop
+set instances [ array names q_sys_mem_if_ddr3_emif_0_p0_ddr_db ]
+foreach { inst } $instances {
+	if { [ info exists pins ] } {
+		# Clean-up stale content
+		unset pins
+	}
+	array set pins $q_sys_mem_if_ddr3_emif_0_p0_ddr_db($inst)
+
+	set prefix $inst
+	if { $entity_names_on } {
+		set prefix [ string map "| |*:" $inst ]
+		set prefix "*:$prefix"
+	}
+
+	#####################################################
+	#                                                   #
+	# Transfer the pin names to more readable variables #
+	#                                                   #
+	#####################################################
+
+	set dqs_pins $pins(dqs_pins)
+	set dqsn_pins $pins(dqsn_pins)
+	set q_groups [ list ]
+	foreach { q_group } $pins(q_groups) {
+		set q_group $q_group
+		lappend q_groups $q_group
+	}
+	set all_dq_pins [ join [ join $q_groups ] ]
+
+	set ck_pins $pins(ck_pins)
+	set ckn_pins $pins(ckn_pins)
+	set add_pins $pins(add_pins)
+	set ba_pins $pins(ba_pins)
+	set cmd_pins $pins(cmd_pins)
+	set reset_pins $pins(reset_pins)
+	set ac_pins [ concat $add_pins $ba_pins $cmd_pins ]
+	set dm_pins $pins(dm_pins)
+	set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ]
+
+	set pll_ref_clock $pins(pll_ref_clock)
+	set pll_afi_clock $pins(pll_afi_clock)
+	set pll_dq_write_clock $pins(pll_dq_write_clock)
+	set pll_write_clock $pins(pll_write_clock)
+
+	set dqs_in_clocks $pins(dqs_in_clocks)
+	set dqs_out_clocks $pins(dqs_out_clocks)
+	set dqsn_out_clocks $pins(dqsn_out_clocks)
+
+	set afi_reset_reg $pins(afi_reset_reg)
+	set seq_reset_reg $pins(seq_reset_reg)
+	set sync_reg $pins(sync_reg)
+	set read_capture_ddio $pins(read_capture_ddio)
+	set fifo_wraddress_reg $pins(fifo_wraddress_reg)
+	set fifo_rdaddress_reg $pins(fifo_rdaddress_reg)
+	set fifo_wrload_reg $pins(fifo_wrload_reg)
+	set fifo_rdload_reg $pins(fifo_rdload_reg)
+	set fifo_wrdata_reg $pins(fifo_wrdata_reg)
+	set fifo_rddata_reg $pins(fifo_rddata_reg)
+
+	# ----------------------- #
+	# -                     - #
+	# --- REFERENCE CLOCK --- #
+	# -                     - #
+	# ----------------------- #
+
+	# This is the reference clock used by the PLL to derive any other clock in the core
+	if { [get_collection_size [get_clocks -nowarn $pll_ref_clock]] > 0 } { remove_clock $pll_ref_clock }
+	create_clock -period $t(refCK) -waveform [ list 0 $ref_half_period ] $pll_ref_clock
+
+	# ------------------ #
+	# -                - #
+	# --- PLL CLOCKS --- #
+	# -                - #
+	# ------------------ #
+	
+	# AFI clock
+	set local_pll_afi_clk [ q_sys_mem_if_ddr3_emif_0_p0_get_or_add_clock_vseries \
+		-target $pll_afi_clock \
+		-suffix "afi_clk" \
+		-source $pll_ref_clock \
+		-multiply_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_mult(PLL_AFI_CLK) \
+		-divide_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_div(PLL_AFI_CLK) \
+		-phase $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_phase(PLL_AFI_CLK) ]
+	
+	# DQ write clock
+	set local_pll_dq_write_clk [ q_sys_mem_if_ddr3_emif_0_p0_get_or_add_clock_vseries \
+		-target $pll_dq_write_clock \
+		-suffix "dq_write_clk" \
+		-source $pll_ref_clock \
+		-multiply_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_mult(PLL_WRITE_CLK) \
+		-divide_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_div(PLL_WRITE_CLK) \
+		-phase $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_phase(PLL_WRITE_CLK) ]
+
+    	# DQS write clock
+  	set local_pll_write_clk [ q_sys_mem_if_ddr3_emif_0_p0_get_or_add_clock_vseries \
+  		-target $pll_write_clock \
+  		-suffix "write_clk" \
+  		-source $pll_ref_clock \
+  		-multiply_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_mult(PLL_MEM_CLK) \
+  		-divide_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_div(PLL_MEM_CLK) \
+  		-phase $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_phase(PLL_MEM_CLK) ]
+  
+ 	# -------------------- #
+	# -                  - #
+	# --- SYSTEM CLOCK --- #
+	# -                  - #
+	# -------------------- #
+
+	# This is the CK clock
+	foreach { ck_pin } $ck_pins {
+		create_generated_clock -multiply_by 1 -source $pll_write_clock -master_clock "$local_pll_write_clk" $ck_pin -name $ck_pin
+		set_clock_uncertainty -to [get_clocks $ck_pin] 0.025
+	}
+
+	# This is the CK#clock
+	foreach { ckn_pin } $ckn_pins {
+		create_generated_clock -multiply_by 1 -invert -source $pll_write_clock -master_clock "$local_pll_write_clk" $ckn_pin -name $ckn_pin
+		set_clock_uncertainty -to [get_clocks $ckn_pin] 0.025
+	}
+
+        # ------------------- #
+        # -                 - #
+        # --- READ CLOCKS --- #
+        # -                 - #
+        # ------------------- #
+        
+        foreach dqs_in_clock_struct $dqs_in_clocks {
+        	array set dqs_in_clock $dqs_in_clock_struct
+        	# This is the DQS clock for Read Capture analysis (micro model)
+        	create_clock -period $t(CK) -waveform [ list 0 $half_period ] $dqs_in_clock(dqs_pin) -name $dqs_in_clock(dqs_pin)_IN -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -from [ get_clocks $dqs_in_clock(dqs_pin)_IN ] 0
+        }
+        
+        	set resync_clock ${inst}|pll0|upll_memphy|auto_generated|pll1|clk\[2\]
+          	
+                set local_resync_clk [ q_sys_mem_if_ddr3_emif_0_p0_get_or_add_clock_vseries \
+          		-target $resync_clock \
+          		-suffix "resync_clk" \
+          		-source $pll_ref_clock \
+          		-multiply_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_mult(PLL_ADDR_CMD_CLK) \
+          		-divide_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_div(PLL_ADDR_CMD_CLK) \
+          		-phase $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_phase(PLL_ADDR_CMD_CLK) ]
+        
+        
+        	set tracking_clock ${inst}|pll0|upll_memphy|auto_generated|pll1|clk\[3\]
+          	
+                set local_tracking_clk [ q_sys_mem_if_ddr3_emif_0_p0_get_or_add_clock_vseries \
+          		-target $tracking_clock \
+          		-suffix "tracking_clk" \
+          		-source $pll_ref_clock \
+          		-multiply_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_mult(PLL_AFI_HALF_CLK) \
+          		-divide_by $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_div(PLL_AFI_HALF_CLK) \
+          		-phase $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_pll_phase(PLL_AFI_HALF_CLK) ]
+        
+        
+        
+        for { set i 0 } { $i < $::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_number_of_dqs_groups } { incr i } {
+            set resync_x2_capture_clockname "${inst}_resync_x2_capture_${i}"
+            create_generated_clock -name $resync_x2_capture_clockname -source [get_pins ${inst}|p0|umemphy|dq_ddio\[$i\].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clk] -divide_by 2 [get_pins ${inst}|p0|umemphy|dq_ddio\[$i\].ubidir_dq_dqs|dq_ddio_io|clock_divider*_hr_clock.io_clkdiv|clkout] -add
+        }
+        
+        # -------------------- #
+        # -                  - #
+        # --- WRITE CLOCKS --- #
+        # -                  - #
+        # -------------------- #
+        
+        # This is the DQS clock for Data Write analysis (micro model)
+        foreach dqs_out_clock_struct $dqs_out_clocks {
+        	array set dqs_out_clock $dqs_out_clock_struct
+        	create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqs_out_clock(dst) -name $dqs_out_clock(dst)_OUT -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -to [ get_clocks $dqs_out_clock(dst)_OUT ] 0
+        }
+        
+        # This is the DQS#clock for Data Write analysis (micro model)
+        foreach dqsn_out_clock_struct $dqsn_out_clocks {
+        	array set dqsn_out_clock $dqsn_out_clock_struct
+        	create_generated_clock -multiply_by 1 -invert -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqsn_out_clock(dst) -name $dqsn_out_clock(dst)_OUT -add
+        
+        	# Clock Uncertainty is accounted for by the ...pathjitter parameters
+        	set_clock_uncertainty -to [ get_clocks $dqsn_out_clock(dst)_OUT ] 0
+        }
+	
+        ##################
+        #                #
+        # READ DATA PATH #
+        #                #
+        ##################
+
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		set_max_skew -from [get_ports $dq_pin] 0.1
+        	}
+        }
+        
+        ###################
+        #                 #
+        # WRITE DATA PATH #
+        #                 #
+        ###################
+        
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		# Specifies the minimum delay difference between the DQS pin and the DQ pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS pin and the DQ pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        	}
+        }
+        
+        foreach { dqsn_pin } $dqsn_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		# Specifies the minimum delay difference between the DQS#pin and the DQ pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS#pin and the DQ pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
+        	}
+        }
+        
+        foreach dqs_out_clock_struct $dqs_out_clocks {
+        	array set dqs_out_clock $dqs_out_clock_struct
+        
+        	if { [string length $dqs_out_clock(dm_pin)] > 0 } {
+        		# Specifies the minimum delay difference between the DQS and the DM pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS and the DM pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
+        	}
+        }
+        
+        foreach dqsn_out_clock_struct $dqsn_out_clocks {
+        	array set dqsn_out_clock $dqsn_out_clock_struct
+        
+        	if { [string length $dqsn_out_clock(dm_pin)] > 0 } {
+        		# Specifies the minimum delay difference between the DQS and the DM pins:
+        		set_output_delay -min $data_output_min_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
+        
+        		# Specifies the maximum delay difference between the DQS and the DM pins:
+        		set_output_delay -max $data_output_max_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
+        	}
+        }
+        
+        ###################
+        ###
+        ##DQS vs CK PATH #
+        ###
+        ###################
+        
+        foreach { ck_pin } $ck_pins { 
+        	set_output_delay -add_delay -clock [get_clocks $ck_pin] -max [q_sys_mem_if_ddr3_emif_0_p0_round_3dp [expr $t(CK) - $t(DQSS)*$t(CK) - $board(minCK_DQS_skew) ]] $dqs_pins
+        	set_output_delay -add_delay -clock [get_clocks $ck_pin] -min [q_sys_mem_if_ddr3_emif_0_p0_round_3dp [expr $t(DQSS)*$t(CK) - $board(maxCK_DQS_skew) ]] $dqs_pins
+        	set_false_path -fall_from [get_clocks $local_pll_write_clk ] -to [get_ports $dqs_pins]
+        }
+        
+        ############
+        #          #
+        # A/C PATH #
+        #          #
+        ############
+        
+        foreach { ck_pin } $ck_pins {
+        	# ac_pins can contain input ports such as mem_err_out_n
+        	# Loop through each ac pin to make sure we only apply set_output_delay to output ports
+        	foreach { ac_pin } $ac_pins {
+        		set ac_port [ get_ports $ac_pin ]
+        		if {[get_collection_size $ac_port] > 0} {
+        			if [ get_port_info -is_output_port $ac_port ] {
+        				# Specifies the minimum delay difference between the DQS pin and the address/control pins:
+        				set_output_delay -min $ac_min_delay -clock [get_clocks $ck_pin] $ac_port -add_delay
+        
+        				# Specifies the maximum delay difference between the DQS pin and the address/control pins:
+        				set_output_delay -max $ac_max_delay -clock [get_clocks $ck_pin] $ac_port -add_delay
+        			}
+        		}
+        	}
+        }
+        
+#########################
+#                       #
+#  FALSE PATH           #
+#                       #
+#########################
+
+        foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
+        	foreach { dq_pin } $dq_pins {
+        		        set_false_path -from [get_registers *dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*] -to [get_ports $dq_pin]
+        	}
+        }
+        
+        set_false_path -rise_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ]
+
+        foreach { pin } [concat $dqs_pins $dqsn_pins $ck_pins $ckn_pins $reset_pins] {
+        	set_max_skew -to [get_ports $pin] 0.1
+        }
+
+#########################
+#                       #
+# FITTER OVERCONSTRAINT #
+#                       #
+#########################
+
+        if ($fit_flow) {
+        set_max_delay -from [get_registers *hr_to_fr*] -to [get_registers *out_path_enhanced_ddr*] 2.8
+        set_max_delay -from [get_registers *hr_to_fr*] -to [get_registers *oe_path_enhanced_ddr*] 3.3
+
+        set_min_delay -from [get_registers *input*] -to [get_registers *dq_r*] 0.1
+        }
+
+}
+
+######################
+#                    #
+# REPORT DDR COMMAND #
+#                    #
+######################
+
+add_ddr_report_command "source [list [file join [file dirname [info script]] ${::GLOBAL_q_sys_mem_if_ddr3_emif_0_p0_corename}_report_timing.tcl]]"
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
new file mode 100644
index 0000000..10051e5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0.sv
@@ -0,0 +1,448 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_ddr3_phy_core; -name IP_TOOL_VERSION 18.0; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100" *)
+module q_sys_mem_if_ddr3_emif_0_p0 (
+    global_reset_n,
+    soft_reset_n,
+	csr_soft_reset_req,
+	pll_mem_clk,
+	pll_write_clk,
+	pll_capture0_clk,
+	pll_capture1_clk,
+	pll_locked,
+	afi_reset_n,
+	afi_reset_export_n,
+	afi_clk,
+	afi_half_clk,
+	afi_addr,
+	afi_ba,
+	afi_cke,
+	afi_cs_n,
+	afi_ras_n,
+	afi_we_n,
+	afi_cas_n,
+	afi_rst_n,
+	afi_odt,
+	afi_dqs_burst,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_dm,
+	afi_rdata,
+	afi_rdata_en,
+	afi_rdata_en_full,
+	afi_rdata_valid,
+	afi_cal_success,
+	afi_cal_fail,
+	afi_wlat,
+	afi_rlat,
+	afi_mem_clk_disable,
+	mem_a,
+	mem_ba,
+	mem_ck,
+	mem_ck_n,
+	mem_cke,
+	mem_cs_n,
+	mem_dm,
+	mem_ras_n,
+	mem_cas_n,
+	mem_we_n,
+	mem_dq,
+	mem_dqs,
+	mem_dqs_n,
+	mem_reset_n,
+	mem_odt,
+	avl_clk,
+	avl_reset_n,
+	pd_reset_n,
+	pd_ack,
+	pd_up,
+	pd_down,
+	phy_clk,
+	phy_reset_n,
+	phy_read_latency_counter,
+	phy_afi_wlat,
+	phy_afi_rlat,
+	phy_read_increment_vfifo_fr,
+	phy_read_increment_vfifo_hr,
+	phy_read_increment_vfifo_qr,
+	phy_reset_mem_stable,
+	phy_write_fr_cycle_shifts,
+	phy_cal_debug_info,
+	phy_read_fifo_reset,
+	phy_vfifo_rd_en_override,
+	phy_cal_success,
+	phy_cal_fail,
+	phy_read_fifo_q,
+	calib_skip_steps
+);
+
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver. 
+parameter DEVICE_FAMILY = "MAX 10";
+
+// choose between abstract (fast) and regular model
+`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL
+  `define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0
+`endif
+
+parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
+
+localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
+
+
+// On-chip termination
+parameter OCT_TERM_CONTROL_WIDTH   = 14;
+
+// PHY-Memory Interface
+// Memory device specific parameters, they are set according to the memory spec.
+parameter MEM_IF_ADDR_WIDTH			= 14;
+parameter MEM_IF_BANKADDR_WIDTH     = 3;
+parameter MEM_IF_CK_WIDTH			= 1;
+parameter MEM_IF_CLK_EN_WIDTH		= 1;
+parameter MEM_IF_CS_WIDTH			= 1;
+parameter MEM_IF_DM_WIDTH         	= 1;
+parameter MEM_IF_CONTROL_WIDTH    	= 1; 
+parameter MEM_IF_DQ_WIDTH         	= 8;
+parameter MEM_IF_DQS_WIDTH         	= 1;
+parameter MEM_IF_READ_DQS_WIDTH    	= 1;
+parameter MEM_IF_WRITE_DQS_WIDTH   	= 1;
+parameter MEM_IF_ODT_WIDTH         	= 1;
+parameter MEM_IF_NUMBER_OF_RANKS	= 1;
+
+// PHY-Controller (AFI) Interface
+// The AFI interface widths are derived from the memory interface widths based on full/half rate operations.
+// The calculations are done on higher level wrapper.
+parameter AFI_ADDR_WIDTH 	        = 28; 
+parameter AFI_DM_WIDTH 	        	= 4; 
+parameter AFI_BANKADDR_WIDTH        = 6; 
+parameter AFI_CS_WIDTH				= 2;
+parameter AFI_CLK_EN_WIDTH          = 2;
+parameter AFI_CONTROL_WIDTH         = 2; 
+parameter AFI_ODT_WIDTH             = 2; 
+parameter AFI_DQ_WIDTH				= 32; 
+parameter AFI_WRITE_DQS_WIDTH		= 2;
+parameter AFI_RATE_RATIO			= 2;
+parameter AFI_WLAT_WIDTH			= 6;
+parameter AFI_RLAT_WIDTH			= 6;
+parameter AFI_RRANK_WIDTH           = 2;
+parameter AFI_WRANK_WIDTH           = 2;
+
+// DLL Interface
+parameter DLL_DELAY_CTRL_WIDTH	= 6;
+
+parameter SCC_DATA_WIDTH            = 1;
+
+parameter NUM_SUBGROUP_PER_READ_DQS        = 1;
+parameter QVLD_EXTRA_FLOP_STAGES		   = 0;
+parameter QVLD_WR_ADDRESS_OFFSET		   = 4;
+	
+// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture.
+// Read valid prediction FIFO
+parameter READ_VALID_FIFO_SIZE             = 16;
+
+// Data resynchronization FIFO
+parameter READ_FIFO_SIZE                   = 8;
+
+// Latency calibration parameters
+parameter MAX_LATENCY_COUNT_WIDTH		   = 5; // calibration finds the best latency by reducing the maximum latency
+localparam MAX_READ_LATENCY				   = 2**MAX_LATENCY_COUNT_WIDTH; 
+
+// Write Datapath
+// The sequencer uses this value to control write latency during calibration
+parameter MAX_WRITE_LATENCY_COUNT_WIDTH = 4;
+parameter NUM_WRITE_PATH_FLOP_STAGES    = 1;
+parameter NUM_WRITE_FR_CYCLE_SHIFTS = 1;
+
+// Add additional FF stage between core and periphery
+parameter REGISTER_C2P = "false";
+
+// Address/Command Datapath
+parameter NUM_AC_FR_CYCLE_SHIFTS = 0;
+
+parameter MR1_ODS								= 0;
+parameter MR1_RTT								= 0;
+parameter MR2_RTT_WR							= 0;
+parameter MEM_T_WL								= 5;
+
+localparam MEM_T_RL								= 5;
+
+// The sequencer issues back-to-back reads during calibration, NOPs may need to be inserted depending on the burst length
+parameter SEQ_BURST_COUNT_WIDTH = 1;
+
+// The DLL offset control width
+parameter DLL_OFFSET_CTRL_WIDTH = 6;
+
+parameter MEM_CLK_FREQ = 300.0;
+parameter DELAY_BUFFER_MODE = "HIGH";
+parameter DQS_DELAY_CHAIN_PHASE_SETTING = 2;
+parameter DQS_PHASE_SHIFT = 9000;
+parameter DELAYED_CLOCK_PHASE_SETTING = 2;
+parameter AFI_DEBUG_INFO_WIDTH = 32;
+
+parameter CALIB_REG_WIDTH = 8;
+
+
+parameter TB_PROTOCOL       = "DDR3";
+parameter TB_MEM_CLK_FREQ   = "300.0";
+parameter TB_RATE           = "HALF";
+parameter TB_MEM_DQ_WIDTH   = "8";
+parameter TB_MEM_DQS_WIDTH  = "1";
+parameter TB_PLL_DLL_MASTER = "true";
+
+parameter FAST_SIM_CALIBRATION = "false";
+
+
+parameter EXTRA_VFIFO_SHIFT = 0;
+
+localparam SIM_FILESET = ("false" == "true");
+
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+
+// ******************************************************************************************************************************** 
+// BEGIN PORT SECTION
+
+
+// When the PHY is selected to be a PLL/DLL SLAVE, the PLL and DLL are instantied at the top level of the example design
+input	pll_mem_clk;	
+input	pll_write_clk;
+input	pll_capture0_clk;
+input	pll_capture1_clk;
+input	pll_locked;
+
+
+
+
+
+
+// Reset Interface, AFI 2.0
+input   global_reset_n;		// Resets (active-low) the whole system (all PHY logic + PLL)
+input	soft_reset_n;		// Resets (active-low) PHY logic only, PLL is NOT reset
+output	afi_reset_export_n;	// Asynchronously asserted and synchronously de-asserted on afi_clk domain
+output	afi_reset_n;		// Asynchronously asserted and synchronously de-asserted on afi_clk domain
+							// should be used to reset system level afi_clk domain logic
+input csr_soft_reset_req;  // Reset request (active_high) being driven by external debug master
+
+// OCT termination control signals
+
+// PHY-Controller Interface, AFI 2.0
+// Control Interface
+input   [AFI_ADDR_WIDTH-1:0]        afi_addr;		// address
+input   [AFI_BANKADDR_WIDTH-1:0]    afi_ba;			// bank
+input   [AFI_CLK_EN_WIDTH-1:0]      afi_cke;		// clock enable
+input   [AFI_CS_WIDTH-1:0]          afi_cs_n;		// chip select
+input   [AFI_CONTROL_WIDTH-1:0]     afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_cas_n;
+input   [AFI_ODT_WIDTH-1:0]         afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0]     afi_rst_n;
+
+
+// Write data interface
+input   [AFI_WRITE_DQS_WIDTH-1:0]   afi_dqs_burst;
+input   [AFI_DQ_WIDTH-1:0]          afi_wdata;			// write data
+input	[AFI_WRITE_DQS_WIDTH-1:0]	afi_wdata_valid;	// write data valid, used to maintain write latency required by protocol spec
+input   [AFI_DM_WIDTH-1:0]          afi_dm;				// write data mask
+
+// Read data interface
+output  [AFI_DQ_WIDTH-1:0]    afi_rdata;           // read data				
+input   [AFI_RATE_RATIO-1:0]  afi_rdata_en;        // read enable, used to maintain the read latency calibrated by PHY
+input   [AFI_RATE_RATIO-1:0]  afi_rdata_en_full;   // read enable full burst, used to create DQS enable
+output  [AFI_RATE_RATIO-1:0]  afi_rdata_valid;     // read data valid
+
+
+// Status interface
+output  afi_cal_success;	// calibration success
+output  afi_cal_fail;		// calibration failure
+
+output [AFI_WLAT_WIDTH-1:0]			afi_wlat;
+output [AFI_RLAT_WIDTH-1:0]			afi_rlat;
+input  [MEM_IF_CK_WIDTH-1:0] afi_mem_clk_disable;
+
+
+// Ping Pong PHY signals
+
+// PHY-Memory Interface
+
+output  [MEM_IF_ADDR_WIDTH-1:0]       mem_a;        // address
+output  [MEM_IF_BANKADDR_WIDTH-1:0]   mem_ba;       // bank
+inout   [MEM_IF_CK_WIDTH-1:0]         mem_ck;       // differential address and command clock
+inout   [MEM_IF_CK_WIDTH-1:0]         mem_ck_n;
+output  [MEM_IF_CLK_EN_WIDTH-1:0]     mem_cke;      // clock enable
+output  [MEM_IF_CS_WIDTH-1:0]         mem_cs_n;     // chip select
+output  [MEM_IF_DM_WIDTH-1:0]         mem_dm;       // data mask
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_ras_n;		
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_cas_n;		
+output  [MEM_IF_CONTROL_WIDTH-1:0]    mem_we_n;		
+inout	[MEM_IF_DQ_WIDTH-1:0]         mem_dq;       // bidirectional data bus
+inout	[MEM_IF_DQS_WIDTH-1:0]        mem_dqs;      // bidirectional data strobe
+inout	[MEM_IF_DQS_WIDTH-1:0]        mem_dqs_n;    // differential bidirectional data strobe
+output  [MEM_IF_ODT_WIDTH-1:0]        mem_odt;
+output	                              mem_reset_n;
+
+// PLL Interface
+input	afi_clk;
+input	afi_half_clk;
+
+
+
+
+output  avl_clk;
+output  avl_reset_n;
+input  pd_reset_n;
+input  pd_ack;
+output pd_up;
+output pd_down;
+
+output  phy_clk;
+output  phy_reset_n;
+
+input  [MAX_LATENCY_COUNT_WIDTH-1:0]  phy_read_latency_counter;
+input           [AFI_WLAT_WIDTH-1:0]  phy_afi_wlat;
+input           [AFI_RLAT_WIDTH-1:0]  phy_afi_rlat;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_fr;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_hr;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_increment_vfifo_qr;
+input                                 phy_reset_mem_stable;
+input	[MEM_IF_WRITE_DQS_WIDTH*2-1:0] phy_write_fr_cycle_shifts;
+input   [AFI_DEBUG_INFO_WIDTH - 1:0]  phy_cal_debug_info;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_read_fifo_reset;
+input    [MEM_IF_READ_DQS_WIDTH-1:0]  phy_vfifo_rd_en_override;
+input                                 phy_cal_success;	// calibration success
+input                                 phy_cal_fail;		// calibration failure
+output            [AFI_DQ_WIDTH-1:0]  phy_read_fifo_q; 
+
+output         [CALIB_REG_WIDTH-1:0]  calib_skip_steps;
+
+
+// END PORT SECTION
+
+
+initial $display("Using %0s core emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular");
+
+
+assign afi_cal_success = phy_cal_success;
+assign afi_cal_fail = phy_cal_fail;
+
+assign avl_clk = afi_clk;
+assign avl_reset_n = afi_reset_n; 
+
+
+integer MEM_T_WL_int = (MEM_T_WL/2);
+assign afi_wlat = MEM_T_WL_int[AFI_WLAT_WIDTH-1:0];
+
+
+// Exporting read latency is currently not supported
+assign afi_rlat = 0;
+
+
+q_sys_mem_if_ddr3_emif_0_p0_memphy_m10 #(
+	.DEVICE_FAMILY(DEVICE_FAMILY),
+	.MEM_ADDRESS_WIDTH(MEM_IF_ADDR_WIDTH),
+	.MEM_BANK_WIDTH(MEM_IF_BANKADDR_WIDTH),
+	.MEM_CLK_EN_WIDTH(MEM_IF_CLK_EN_WIDTH),
+	.MEM_CK_WIDTH(MEM_IF_CK_WIDTH),
+	.MEM_ODT_WIDTH(MEM_IF_ODT_WIDTH),
+	.MEM_DQS_WIDTH(MEM_IF_DQS_WIDTH),
+	.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
+	.MEM_DM_WIDTH(MEM_IF_DM_WIDTH),
+	.MEM_CONTROL_WIDTH(MEM_IF_CONTROL_WIDTH),
+	.MEM_DQ_WIDTH(MEM_IF_DQ_WIDTH),
+	.MEM_READ_DQS_WIDTH(MEM_IF_READ_DQS_WIDTH),
+	.MEM_WRITE_DQS_WIDTH(MEM_IF_WRITE_DQS_WIDTH),
+	.AFI_ADDRESS_WIDTH(AFI_ADDR_WIDTH),
+	.AFI_BANK_WIDTH(AFI_BANKADDR_WIDTH),
+	.AFI_CHIP_SELECT_WIDTH(AFI_CS_WIDTH),
+	.AFI_CLK_EN_WIDTH(AFI_CLK_EN_WIDTH),
+	.AFI_ODT_WIDTH(AFI_ODT_WIDTH),
+	.AFI_DATA_MASK_WIDTH(AFI_DM_WIDTH),
+	.AFI_DQS_WIDTH(AFI_WRITE_DQS_WIDTH),
+	.AFI_CONTROL_WIDTH(AFI_CONTROL_WIDTH),
+	.AFI_DATA_WIDTH(AFI_DQ_WIDTH),
+	.AFI_RATE_RATIO(AFI_RATE_RATIO),
+	.MEM_T_RL(MEM_T_RL),
+	.MAX_LATENCY_COUNT_WIDTH(MAX_LATENCY_COUNT_WIDTH),
+	.NUM_WRITE_PATH_FLOP_STAGES(NUM_WRITE_PATH_FLOP_STAGES),
+	.NUM_WRITE_FR_CYCLE_SHIFTS(NUM_WRITE_FR_CYCLE_SHIFTS),
+	.NUM_AC_FR_CYCLE_SHIFTS(NUM_AC_FR_CYCLE_SHIFTS),
+	.CALIB_REG_WIDTH(CALIB_REG_WIDTH),
+	.AFI_DEBUG_INFO_WIDTH(AFI_DEBUG_INFO_WIDTH)
+) umemphy (
+	.global_reset_n(global_reset_n),
+	.soft_reset_n(soft_reset_n & ~csr_soft_reset_req),
+	.ctl_reset_n(afi_reset_n),
+	.ctl_reset_export_n(afi_reset_export_n),
+	.pll_locked(pll_locked),
+	.afi_addr(afi_addr),
+	.afi_ba(afi_ba),
+	.afi_cke(afi_cke),
+	.afi_cs_n(afi_cs_n),
+	.afi_ras_n(afi_ras_n),
+	.afi_we_n(afi_we_n),
+	.afi_cas_n(afi_cas_n),
+	.afi_rst_n(afi_rst_n),
+	.afi_mem_clk_disable(afi_mem_clk_disable),
+	.afi_odt(afi_odt),
+	.afi_dqs_burst(afi_dqs_burst),
+	.afi_wdata(afi_wdata),
+	.afi_wdata_valid(afi_wdata_valid),
+	.afi_dm(afi_dm),
+	.afi_rdata(afi_rdata),
+	.afi_rdata_en(afi_rdata_en),
+	.afi_rdata_valid(afi_rdata_valid),
+	.afi_cal_success(afi_cal_success),
+	.afi_cal_fail(afi_cal_fail),
+	.mem_a(mem_a),
+	.mem_ba(mem_ba),
+	.mem_ck(mem_ck),
+	.mem_ck_n(mem_ck_n),
+	.mem_cke(mem_cke),
+	.mem_cs_n(mem_cs_n),
+	.mem_dm(mem_dm),
+	.mem_ras_n(mem_ras_n),
+	.mem_cas_n(mem_cas_n),
+	.mem_we_n(mem_we_n),
+	.mem_reset_n(mem_reset_n),
+	.mem_dq(mem_dq),
+	.mem_dqs(mem_dqs),
+	.mem_dqs_n(mem_dqs_n),
+	.mem_odt(mem_odt),
+	.pll_afi_clk(afi_clk),
+	.pll_mem_clk(pll_mem_clk),
+	.pll_write_clk(pll_write_clk),
+	.pll_capture0_clk(pll_capture0_clk),
+	.pll_capture1_clk(pll_capture1_clk),
+	.phy_read_latency_counter(phy_read_latency_counter),
+	.phy_read_increment_vfifo_hr(phy_read_increment_vfifo_hr),
+	.phy_cal_debug_info(phy_cal_debug_info),
+	.phy_read_fifo_reset(phy_read_fifo_reset),
+	.phy_vfifo_rd_en_override(phy_vfifo_rd_en_override),
+	.calib_skip_steps(calib_skip_steps),
+	.phy_clk(phy_clk),
+	.phy_reset_n(phy_reset_n),
+	.pd_reset_n(pd_reset_n),
+	.pd_ack(pd_ack),
+	.pd_up(pd_up),
+	.pd_down(pd_down)
+);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
new file mode 100644
index 0000000..56dcd94
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath.v
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath(
+	clk,
+	reset_n,
+	afi_address,
+	afi_bank,
+	afi_cs_n,
+	afi_cke,
+	afi_odt,
+	afi_ras_n,
+	afi_cas_n,
+	afi_we_n,
+	afi_rst_n,
+	phy_ddio_address,
+	phy_ddio_bank,
+	phy_ddio_cs_n,
+	phy_ddio_cke,
+	phy_ddio_we_n,
+	phy_ddio_ras_n,
+	phy_ddio_cas_n,
+	phy_ddio_reset_n,
+	phy_ddio_odt
+);
+
+
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_BANK_WIDTH        = "";
+parameter MEM_CHIP_SELECT_WIDTH = "";
+parameter MEM_CLK_EN_WIDTH 		= "";
+parameter MEM_ODT_WIDTH 		= "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+parameter AFI_ADDRESS_WIDTH         = "";
+parameter AFI_BANK_WIDTH            = "";
+parameter AFI_CHIP_SELECT_WIDTH     = "";
+parameter AFI_CLK_EN_WIDTH     		= "";
+parameter AFI_ODT_WIDTH     		= "";
+parameter AFI_DATA_MASK_WIDTH       = "";
+parameter AFI_CONTROL_WIDTH         = "";
+parameter AFI_DATA_WIDTH            = "";
+
+parameter NUM_AC_FR_CYCLE_SHIFTS    = "";
+
+localparam RATE_MULT = 2;
+
+
+input	reset_n;
+input	clk;
+input	[AFI_ADDRESS_WIDTH-1:0]	afi_address;
+input   [AFI_BANK_WIDTH-1:0] afi_bank;
+input   [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
+input   [AFI_CLK_EN_WIDTH-1:0] afi_cke;
+input   [AFI_ODT_WIDTH-1:0] afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
+
+output	[AFI_ADDRESS_WIDTH-1:0]	phy_ddio_address;
+output	[AFI_BANK_WIDTH-1:0] phy_ddio_bank;
+output	[AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
+output	[AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
+output	[AFI_ODT_WIDTH-1:0] phy_ddio_odt;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
+output	[AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
+
+	// some bits of afi_address are tied low during calibration (only a few addresses are used for calibration)
+	// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
+	// sclr pin is very slow and causes timing failures
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_ADDRESS_WIDTH-1:0] afi_address_r;
+	reg [AFI_BANK_WIDTH-1:0] afi_bank_r;
+	reg [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r;
+	reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
+	reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
+	reg [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r;
+
+	always @(posedge clk)
+	begin
+		afi_address_r <= afi_address;
+		afi_bank_r <= afi_bank;
+		afi_cs_n_r <= afi_cs_n;
+		afi_cke_r <= afi_cke;
+		afi_odt_r <= afi_odt;
+		afi_ras_n_r <= afi_ras_n;
+		afi_cas_n_r <= afi_cas_n;
+		afi_we_n_r <= afi_we_n;
+		afi_rst_n_r <= afi_rst_n;
+	end
+
+
+	wire [1:0] shift_fr_cycle =
+		(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 	2'b00 : (
+		(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 	2'b01 : (
+		(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 	2'b10 : (
+											2'b11 )));
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_address_r),
+		.dataout (phy_ddio_address)
+	);
+	defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
+	defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
+
+
+
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_bank_r),
+		.dataout (phy_ddio_bank)
+	);
+	defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
+	defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cke_r),
+		.dataout (phy_ddio_cke)
+	);
+	defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
+	defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cs_n_r),
+		.dataout (phy_ddio_cs_n)
+	);
+	defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
+	defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_odt_r),
+		.dataout (phy_ddio_odt)
+	);
+	defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
+	defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_ras_n_r),
+		.dataout (phy_ddio_ras_n)
+	);
+	defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_cas_n_r),
+		.dataout (phy_ddio_cas_n)
+	);
+	defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_we_n_r),
+		.dataout (phy_ddio_we_n)
+	);
+	defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_rst_n(
+		.clk (clk),
+		.reset_n (reset_n),
+		.shift_by (shift_fr_cycle),
+		.datain (afi_rst_n_r),
+		.dataout (phy_ddio_reset_n)
+	);
+	defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
+	defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "false";
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
new file mode 100644
index 0000000..74cf11f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10.v
@@ -0,0 +1,513 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10(
+    reset_n,
+    pll_afi_clk,
+    pll_mem_clk,
+    pll_mem_clk_ddio,
+    pll_write_clk,
+    enable_mem_clk,
+    phy_ddio_address,
+    phy_ddio_cke,
+    phy_ddio_cs_n,
+    phy_ddio_bank,
+    phy_ddio_odt,
+    phy_ddio_we_n,
+    phy_ddio_ras_n,
+    phy_ddio_cas_n,
+    phy_mem_bank,
+    phy_mem_odt,
+    phy_mem_we_n,
+    phy_mem_ras_n,
+    phy_mem_cas_n,
+    phy_ddio_reset_n,
+    phy_mem_reset_n,
+    phy_mem_address,
+    phy_mem_cs_n,
+    phy_mem_cke,
+    phy_mem_ck,
+    phy_mem_ck_n,
+    mimic_clock
+);
+
+// *****************************************************************
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in 
+// from higher level wrapper with the controller and driver
+//Global parameters
+parameter DEVICE_FAMILY = "";
+
+// Width of the addr/cmd signals going out to the external memory
+parameter MEM_ADDRESS_WIDTH     = ""; 
+parameter MEM_CONTROL_WIDTH     = ""; 
+parameter INVERT_OUTPUT_CLOCK   = "";
+parameter MEM_CHIP_SELECT_WIDTH = ""; 
+parameter MEM_CLK_EN_WIDTH      = ""; 
+
+parameter MEM_BANK_WIDTH        = ""; 
+parameter MEM_CK_WIDTH          = ""; 
+parameter MEM_ODT_WIDTH         = ""; 
+
+// Width of the addr/cmd signals coming in from the AFI
+parameter AFI_ADDRESS_WIDTH         = ""; 
+parameter AFI_CONTROL_WIDTH         = ""; 
+parameter AFI_CHIP_SELECT_WIDTH     = ""; 
+parameter AFI_CLK_EN_WIDTH          = ""; 
+
+parameter AFI_BANK_WIDTH            = ""; 
+parameter AFI_ODT_WIDTH             = ""; 
+
+// *****************************************************************
+// BEGIN PORT SECTION
+
+input   reset_n;
+input   pll_afi_clk;
+input   pll_mem_clk;
+input   pll_mem_clk_ddio;
+input   pll_write_clk;
+input   [MEM_CK_WIDTH-1:0]              enable_mem_clk;
+input   [AFI_ADDRESS_WIDTH-1:0]         phy_ddio_address;
+input   [AFI_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n;
+input   [AFI_CLK_EN_WIDTH-1:0]          phy_ddio_cke;
+
+output  [MEM_ADDRESS_WIDTH-1:0]         phy_mem_address;
+output  [MEM_CHIP_SELECT_WIDTH-1:0]     phy_mem_cs_n;
+output  [MEM_CLK_EN_WIDTH-1:0]          phy_mem_cke;
+inout   [MEM_CK_WIDTH-1:0]              phy_mem_ck;
+inout   [MEM_CK_WIDTH-1:0]              phy_mem_ck_n;
+output  mimic_clock;
+input   [AFI_BANK_WIDTH-1:0]            phy_ddio_bank;
+input   [AFI_ODT_WIDTH-1:0]             phy_ddio_odt;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_we_n;
+
+output  [MEM_BANK_WIDTH-1:0]            phy_mem_bank;
+output  [MEM_ODT_WIDTH-1:0]             phy_mem_odt;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_we_n;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_ras_n;
+output  [MEM_CONTROL_WIDTH-1:0]         phy_mem_cas_n;
+input   [AFI_CONTROL_WIDTH-1:0]         phy_ddio_reset_n;
+output                                  phy_mem_reset_n;
+
+// The rest of this file performs HR->FR conversion for HR interfaces, and
+// FR-SDR->FR-DDR for protocols that require it.
+
+wire    [MEM_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n_l;
+wire    [MEM_CHIP_SELECT_WIDTH-1:0]     phy_ddio_cs_n_h;
+wire    [MEM_CLK_EN_WIDTH-1:0]          phy_ddio_cke_l;
+wire    [MEM_CLK_EN_WIDTH-1:0]          phy_ddio_cke_h;
+
+wire    [MEM_ADDRESS_WIDTH-1:0]         phy_ddio_address_l;
+wire    [MEM_ADDRESS_WIDTH-1:0]         phy_ddio_address_h;
+wire    [MEM_BANK_WIDTH-1:0]            phy_ddio_bank_l;
+wire    [MEM_BANK_WIDTH-1:0]            phy_ddio_bank_h;
+wire    [MEM_ODT_WIDTH-1:0]             phy_ddio_odt_l;
+wire    [MEM_ODT_WIDTH-1:0]             phy_ddio_odt_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_ras_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_ras_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_cas_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_cas_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_we_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_we_n_h;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_reset_n_l;
+wire    [MEM_CONTROL_WIDTH-1:0]         phy_ddio_reset_n_h;
+
+// each signal has a high and a low portion,
+// connecting to the high and low inputs of the DDIO_OUT,
+// for the purpose of creating double data rate
+    assign phy_ddio_cke_l           = phy_ddio_cke[MEM_CLK_EN_WIDTH-1:0];
+    assign phy_ddio_cs_n_l          = phy_ddio_cs_n[MEM_CHIP_SELECT_WIDTH-1:0];
+    assign phy_ddio_address_l       = phy_ddio_address[MEM_ADDRESS_WIDTH-1:0];
+    assign phy_ddio_bank_l          = phy_ddio_bank[MEM_BANK_WIDTH-1:0];
+    assign phy_ddio_odt_l           = phy_ddio_odt[MEM_ODT_WIDTH-1:0];
+    assign phy_ddio_we_n_l          = phy_ddio_we_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_ras_n_l         = phy_ddio_ras_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_cas_n_l         = phy_ddio_cas_n[MEM_CONTROL_WIDTH-1:0];
+    assign phy_ddio_reset_n_l       = phy_ddio_reset_n[MEM_CONTROL_WIDTH-1:0];
+
+    assign phy_ddio_cke_h           = phy_ddio_cke[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
+    assign phy_ddio_cs_n_h          = phy_ddio_cs_n[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
+    assign phy_ddio_address_h       = phy_ddio_address[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
+    assign phy_ddio_bank_h          = phy_ddio_bank[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
+    assign phy_ddio_odt_h           = phy_ddio_odt[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
+    assign phy_ddio_we_n_h          = phy_ddio_we_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_ras_n_h         = phy_ddio_ras_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_cas_n_h         = phy_ddio_cas_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+    assign phy_ddio_reset_n_h       = phy_ddio_reset_n[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
+
+// Generate MUXSEL for ADC 
+
+reg gen_muxsel_r1;
+reg gen_muxsel_r2;
+reg muxsel;
+
+always @ (posedge pll_mem_clk)
+begin
+    gen_muxsel_r1 <= reset_n;
+    gen_muxsel_r2 <= gen_muxsel_r1;
+end
+
+generate
+begin: gen_adc_sel
+    always @ (posedge pll_mem_clk)
+        begin
+            if (gen_muxsel_r1 & ~gen_muxsel_r2)
+                muxsel <= 1'b0;
+            else
+                muxsel <= ~muxsel;
+        end
+end
+endgenerate
+
+//if "half_rate_mode = true" in a DDIO_OUT, datain_l is sent out first and datain_h is sent out next
+//if "half_rate_mode = false" in a DDIO_OUT, datain_h is sent out first and datain_l is sent out next
+//in this file (addr_cmd_pads.v), all the address and command pads are instantiated using altddio_out (i.e. half_rate_mode = false)
+//inside io_pads (altdqdqs is used), the output signals to be the memory are sent using 2 layers of DDIO_OUT,
+//first layer with half_rate_mode = true and second layer with half_rate_mode = false
+//so for all the memory write interface signals, datain_l will be sent out first
+//in order to be consistent, address and commands should also follow the same order (i.e. datain_l is sent out first)
+//therefore, phy_ddio_*_h is mapped to datain_l and phy_ddio_*_l is mapped to datain_h for all the altddio_out in this file
+
+    genvar i;
+    generate
+    for (i = 0; i < MEM_ADDRESS_WIDTH; i = i + 1)
+    begin :address_gen
+        addr_cmd_pad_m10 uaddress_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_address_h[i], phy_ddio_address_l[i]}),
+            .datain_lo          ({phy_ddio_address_h[i], phy_ddio_address_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_address[i])
+        );
+        defparam uaddress_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+    generate
+    for (i = 0; i < MEM_CHIP_SELECT_WIDTH; i = i + 1)
+    begin :cs_n_gen
+        addr_cmd_pad_m10 ucs_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cs_n_h[i], phy_ddio_cs_n_l[i]}),
+            .datain_lo          ({phy_ddio_cs_n_h[i], phy_ddio_cs_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_cs_n[i])
+        );
+        defparam ucs_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+    generate
+    for (i = 0; i < MEM_CLK_EN_WIDTH; i = i + 1)
+    begin :cke_gen
+        addr_cmd_pad_m10 ucke_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cke_h[i], phy_ddio_cke_l[i]}),
+            .datain_lo          ({phy_ddio_cke_h[i], phy_ddio_cke_l[i]}),
+            .enable             (1'b1),
+            .pad                (phy_mem_cke[i])
+        );
+        defparam ucke_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+
+    generate
+    for (i = 0; i < MEM_BANK_WIDTH; i = i + 1)
+    begin :bank_gen
+        addr_cmd_pad_m10 ubank_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_bank_h[i], phy_ddio_bank_l[i]}),
+            .datain_lo          ({phy_ddio_bank_h[i], phy_ddio_bank_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_bank[i])
+        );
+        defparam ubank_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+    end
+    endgenerate
+
+        generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :odt_gen
+        addr_cmd_pad_m10 uodt_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_odt_h[i], phy_ddio_odt_l[i]}),
+            .datain_lo          ({phy_ddio_odt_h[i], phy_ddio_odt_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_odt[i])
+        );
+        defparam uodt_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :we_n_gen
+        addr_cmd_pad_m10 uwe_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_we_n_h[i], phy_ddio_we_n_l[i]}),
+            .datain_lo          ({phy_ddio_we_n_h[i], phy_ddio_we_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_we_n[i])
+        );
+        defparam uwe_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :ras_n_gen
+        addr_cmd_pad_m10 uras_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_ras_n_h[i], phy_ddio_ras_n_l[i]}),
+            .datain_lo          ({phy_ddio_ras_n_h[i], phy_ddio_ras_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_ras_n[i])
+        );
+        defparam uras_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :cas_n_gen
+        addr_cmd_pad_m10 ucas_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_cas_n_h[i], phy_ddio_cas_n_l[i]}),
+            .datain_lo          ({phy_ddio_cas_n_h[i], phy_ddio_cas_n_l[i]}),
+            .enable             (|enable_mem_clk),
+            .pad                (phy_mem_cas_n[i])
+        );
+        defparam ucas_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+    generate
+    for (i = 0; i < MEM_CONTROL_WIDTH; i = i + 1)
+    begin :reset_n_gen
+        addr_cmd_pad_m10 ureset_n_pad (
+            .muxsel             (muxsel),
+            .pll_afi_clk        (pll_afi_clk),
+            .pll_mem_clk        (pll_mem_clk),
+            .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+            .pll_write_clk      (pll_write_clk),
+            .datain_hi          ({phy_ddio_reset_n_h[i], phy_ddio_reset_n_l[i]}),
+            .datain_lo          ({phy_ddio_reset_n_h[i], phy_ddio_reset_n_l[i]}),
+            .enable             (1'b1),
+            .pad                (phy_mem_reset_n)
+        );
+        defparam ureset_n_pad.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
+        end
+        endgenerate
+
+
+  wire    [MEM_CK_WIDTH-1:0] mem_ck;
+
+
+//An address/cmd CPS was used to generate mem_ck clock. However, this would only work as 
+//long as the mem_ck clock has same phase as an address/command clock. If they require 
+//different phase setttings (e.g., LPDDR), the fitter cannot merge them and mem_ck cannot 
+//be placed in the same DQSLB as the addr/cmd pins. A DQS CPS is now used for mem_ck to 
+//make its placement flexible (case:31912). Setting the following parameter to 'true' 
+//will turn on the legacy behavior.
+localparam USE_ADDR_CMD_CPS_FOR_MEM_CK = "true";
+
+
+generate
+genvar clock_width;
+        for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
+        begin: clock_gen
+
+        altera_gpio_lite #(
+            .PIN_TYPE                  ("bidir"),
+            .SIZE                      (1),
+            .REGISTER_MODE             ("ddr"),
+            .BUFFER_TYPE               ("pseudo_differential"),
+            .ASYNC_MODE                ("none"),
+            .SYNC_MODE                 ("none"),
+            .BUS_HOLD                  ("false"),
+            .OPEN_DRAIN_OUTPUT         ("false"),
+            .SET_REGISTER_OUTPUTS_HIGH ("false"),
+            .INVERT_OUTPUT             ("false"),
+            .INVERT_INPUT_CLOCK        ("false"),
+            .INVERT_OUTPUT_CLOCK       ("false"),
+            .INVERT_OE_INCLOCK         ("false"),
+            .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+            .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+            .USE_ADVANCED_DDR_FEATURES ("false"),
+            .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+            .ENABLE_HR_CLOCK           ("false"),
+            .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+            .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+            .ENABLE_PHASE_DETECTOR_FOR_CK  ("true")
+
+        ) umem_ck_pad (
+            .sclr                      (1'b0),
+            .outclock                  (pll_mem_clk_ddio),
+            .din                       ({1'b0, enable_mem_clk[clock_width]}),
+            .outclocken                (1'b1),     
+            .inclock                   (1'b0),     
+            .inclocken                 (1'b0),     
+            .fr_clock                  (),         
+            .hr_clock                  (),         
+            .invert_hr_clock           (1'b0),     
+            .phy_mem_clock             (pll_mem_clk_ddio),
+            .dout                      (),         
+            .pad_io                    (phy_mem_ck[clock_width]),
+            .pad_io_b                  (phy_mem_ck_n[clock_width]),
+            .pad_in                    (1'b0),     
+            .pad_in_b                  (1'b0),     
+            .aset                      (1'b0),     
+            .aclr                      (1'b0),     
+            .oe                        (1'b1),     
+            .mimic_clock               (mimic_clock)
+        );
+
+    end
+endgenerate
+
+endmodule
+
+module addr_cmd_pad_m10 (
+        pll_afi_clk,
+        pll_mem_clk,
+        pll_mem_clk_ddio,
+        pll_write_clk,
+        muxsel,
+        datain_hi,
+        datain_lo,
+        enable,
+        pad
+);
+
+parameter INVERT_OUTPUT_CLOCK = "";
+
+input           muxsel;
+input            pll_afi_clk;
+input            pll_mem_clk;
+input            pll_mem_clk_ddio;
+input            pll_write_clk;
+input [1:0]     datain_hi;
+input [1:0]     datain_lo;
+input           enable;
+output          pad;
+
+wire datain_h;
+wire datain_l;
+
+        q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH (1)
+        ) hr_to_fr_lo (
+            .hr_clk         (pll_afi_clk),
+            .fr_clk         (pll_mem_clk),
+            .datain_rise    (datain_hi[1]),
+            .datain_fall    (datain_hi[0]),
+            .muxsel         (muxsel),
+            .dataout        (datain_l)
+        );
+
+        q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH (1)
+        ) hr_to_fr_hi (
+            .hr_clk         (pll_afi_clk),
+            .fr_clk         (pll_mem_clk),
+            .datain_rise    (datain_lo[1]),
+            .datain_fall    (datain_lo[0]),
+            .muxsel         (muxsel),
+            .dataout        (datain_h)
+        );
+
+        altera_gpio_lite #(
+            .PIN_TYPE                  ("output"),
+            .SIZE                      (1),
+            .REGISTER_MODE             ("ddr"),
+            .BUFFER_TYPE               ("single-ended"),
+            .ASYNC_MODE                ("none"),
+            .SYNC_MODE                 ("none"),
+            .BUS_HOLD                  ("false"),
+            .OPEN_DRAIN_OUTPUT         ("false"),
+            .SET_REGISTER_OUTPUTS_HIGH ("false"),
+            .INVERT_OUTPUT             ("false"),
+            .INVERT_INPUT_CLOCK        ("false"),
+            .INVERT_OUTPUT_CLOCK       (INVERT_OUTPUT_CLOCK),
+            .INVERT_OE_INCLOCK         ("false"),
+            .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+            .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+            .USE_ADVANCED_DDR_FEATURES ("true"),
+            .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+            .ENABLE_HR_CLOCK           ("false"),
+            .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+            .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+            .ENABLE_OE_PORT            ("true")
+        ) uadc_pad (
+            .sclr                      (1'b0),
+            .outclock                  (pll_write_clk),
+            .phy_mem_clock             (pll_mem_clk_ddio),
+            .din                       ({datain_h, datain_l}),
+            .pad_out                   (pad),
+            .aclr                      (1'b0),          
+            .outclocken                (1'b1),          
+            .inclock                   (1'b0),          
+            .inclocken                 (1'b0),          
+            .fr_clock                  (),              
+            .hr_clock                  (),              
+            .invert_hr_clock           (1'b0),          
+            .dout                      (),              
+            .pad_io                    (),              
+            .pad_io_b                  (),              
+            .pad_in                    (1'b0),          
+            .pad_in_b                  (1'b0),          
+            .pad_out_b                 (),              
+            .aset                      (1'b0),          
+            .oe                        (enable)
+        );
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
new file mode 100644
index 0000000..c12f896
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
@@ -0,0 +1,101 @@
+//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="MAX 10" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
+//VERSION_BEGIN 18.0 cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2018  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details.
+
+
+
+//synthesis_resources = fiftyfivenm_io_obuf 2 fiftyfivenm_pseudo_diff_out 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator
+	( 
+	datain,
+	dataout,
+	dataout_b) /* synthesis synthesis_clearbox=1 */;
+	input   [0:0]  datain;
+	output   [0:0]  dataout;
+	output   [0:0]  dataout_b;
+
+	wire  [0:0]   wire_obuf_ba_o;
+	wire  [0:0]   wire_obufa_o;
+	wire  [0:0]   wire_pseudo_diffa_o;
+	wire  [0:0]   wire_pseudo_diffa_obar;
+	wire [0:0]  oe_b;
+	wire  [0:0]  oe_w;
+
+	fiftyfivenm_io_obuf   obuf_ba_0
+	( 
+	.i(wire_pseudo_diffa_obar),
+	.o(wire_obuf_ba_o[0:0]),
+	.obar(),
+	.oe(oe_b)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.seriesterminationcontrol({16{1'b0}})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devoe(1'b1)
+	// synopsys translate_on
+	);
+	defparam
+		obuf_ba_0.bus_hold = "false",
+		obuf_ba_0.open_drain_output = "false",
+		obuf_ba_0.lpm_type = "fiftyfivenm_io_obuf";
+	fiftyfivenm_io_obuf   obufa_0
+	( 
+	.i(wire_pseudo_diffa_o),
+	.o(wire_obufa_o[0:0]),
+	.obar(),
+	.oe(oe_w)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.seriesterminationcontrol({16{1'b0}})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devoe(1'b1)
+	// synopsys translate_on
+	);
+	defparam
+		obufa_0.bus_hold = "false",
+		obufa_0.open_drain_output = "false",
+		obufa_0.lpm_type = "fiftyfivenm_io_obuf";
+	fiftyfivenm_pseudo_diff_out   pseudo_diffa_0
+	( 
+	.i(datain),
+	.o(wire_pseudo_diffa_o[0:0]),
+	.obar(wire_pseudo_diffa_obar[0:0]));
+	assign
+		dataout = wire_obufa_o,
+		dataout_b = wire_obuf_ba_o,
+		oe_b = 1'b1,
+		oe_w = 1'b1;
+endmodule //q_sys_mem_if_ddr3_emif_0_p0_clock_pair_generator
+//VALID FILE
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
new file mode 100644
index 0000000..2883427
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10.sv
@@ -0,0 +1,414 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10 (
+        reset_n_afi_clk,
+        pll_afi_clk,            // PLL AFI clock, 150 MHz, 0 phase        
+        pll_mem_clk_ddio,       // Memory clock, 300MHz, 0 phase, PHYCLK network
+        pll_mem_clk,            // Memory clock, 300MHz, 0 phase, GCLK network
+        pll_write_clk,          // Write and AC clock, 300MHz, -90 phase
+        enable_mem_clk,
+        dq_capture_clk,        // Calibrated Read capture clock, 200MHz
+        read_capture_clk_hr_dq, // Div2 HR dropback clock 
+        invert_hr_clock,
+
+        mem_dqs_n,              // memory DQS#
+
+        rdata_hr,               // FR read data out 
+        write_oe_in,            // write output enable
+        write_data_in,          // write input data
+        output_strobe_ena,      // DQS output enable
+
+        extra_write_data_in,    
+        extra_write_data_out,
+
+        phy_mem_dq,             // memory DQ
+        mem_dqs                // memory DQS
+);
+
+parameter       PIN_WIDTH = 8;
+parameter       EXTRA_OUTPUT_WIDTH = 1;
+parameter       REVERSE_READ_WORDS = "false";
+parameter       MEM_CK_WIDTH = "";
+
+localparam      rate_mult_out =  4 ;
+localparam      WRITE_OE_WIDTH = PIN_WIDTH * rate_mult_out / 2;
+localparam      WRITE_OUPUT_FR_WIDTH = PIN_WIDTH * rate_mult_out / 2;
+localparam      fpga_width_out = PIN_WIDTH * rate_mult_out;
+localparam      extra_fpga_width_out = EXTRA_OUTPUT_WIDTH * rate_mult_out;
+localparam      EXTRA_OUTPUT_FR_WIDTH = EXTRA_OUTPUT_WIDTH * rate_mult_out/2;
+
+localparam      rate_mult_in = 2;
+localparam      READ_PHY_DQ_WIDTH = PIN_WIDTH * rate_mult_in;
+
+input                           reset_n_afi_clk;
+input                           pll_afi_clk;
+input                           pll_mem_clk_ddio;
+input                           pll_mem_clk;
+input                           pll_write_clk;
+input   [MEM_CK_WIDTH-1:0]      enable_mem_clk;
+input                           dq_capture_clk;
+output                          read_capture_clk_hr_dq;
+input                           invert_hr_clock;
+
+inout [PIN_WIDTH-1:0]           phy_mem_dq;
+inout                           mem_dqs;
+inout                           mem_dqs_n;
+output logic [fpga_width_out-1:0]     rdata_hr;
+
+input [WRITE_OE_WIDTH-1:0]      write_oe_in;
+input [fpga_width_out-1:0]      write_data_in;
+input [1:0]                     output_strobe_ena;
+
+input [extra_fpga_width_out-1:0] extra_write_data_in;
+output [EXTRA_OUTPUT_WIDTH-1:0]  extra_write_data_out;
+
+wire [EXTRA_OUTPUT_WIDTH-1:0]   extra_wr_fr_data_hi;
+wire [EXTRA_OUTPUT_WIDTH-1:0]   extra_wr_fr_data_lo;
+
+wire [PIN_WIDTH-1:0]            rd_fr_data_hi;
+wire [PIN_WIDTH-1:0]            rd_fr_data_lo;
+wire [PIN_WIDTH-1:0]            wr_fr_data_hi;
+wire [PIN_WIDTH-1:0]            wr_fr_data_lo;
+wire [PIN_WIDTH-1:0]            fr_oe;
+
+wire                            fr_os_hi;
+wire                            fr_os_lo;
+wire                            fr_os_oe;
+reg                             fr_os_oe_r;
+
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq;
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq_r;
+logic [READ_PHY_DQ_WIDTH-1:0]   ddio_phy_dq_r1;
+logic [PIN_WIDTH-1:0]           read_capture_clk_fr_dq;
+
+reg wrdata_valid_r1;
+reg wrdata_valid_r2;
+reg wrdata_muxsel;
+
+reg wr_dqs_ena_r1;
+reg wr_dqs_ena_r2;
+reg dqs_ena_muxsel;
+
+//############################################
+// Generate the muxsel signal for DQ and DQS
+// these muxsel signal generated in memclk domain
+//############################################
+
+always_ff @ (posedge pll_mem_clk)
+begin
+        wrdata_valid_r1 <= |write_oe_in;
+        wrdata_valid_r2 <= wrdata_valid_r1;
+        wr_dqs_ena_r1 <= |output_strobe_ena;
+        wr_dqs_ena_r2 <= wr_dqs_ena_r1;
+
+end
+
+generate
+begin: gen_wdata_sel
+    always_ff @ (posedge pll_mem_clk)
+        begin
+            if (wrdata_valid_r1 & ~wrdata_valid_r2)
+                wrdata_muxsel <= 1'b1;
+            else
+                wrdata_muxsel <= ~wrdata_muxsel;
+        end
+end
+endgenerate
+
+generate
+begin: gen_dqs_ena_sel
+    always_ff @ (posedge pll_mem_clk)
+        begin
+            if (wr_dqs_ena_r1 & ~wr_dqs_ena_r2)
+                dqs_ena_muxsel <= 1'b1;
+            else
+                dqs_ena_muxsel <= ~dqs_ena_muxsel;
+        end
+end
+endgenerate
+
+generate
+    genvar opin_num;
+    for (opin_num = 0; opin_num < PIN_WIDTH; opin_num = opin_num + 1)
+    begin :output_path_gen
+                wire hr_data_t0 = write_data_in [opin_num + 0*PIN_WIDTH];
+                wire hr_data_t1 = write_data_in [opin_num + 1*PIN_WIDTH];
+                wire hr_data_t2 = write_data_in [opin_num + 2*PIN_WIDTH];
+                wire hr_data_t3 = write_data_in [opin_num + 3*PIN_WIDTH];
+        
+                q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_lo (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t2),
+                    .datain_fall   (hr_data_t0),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (wr_fr_data_lo[opin_num])
+                );
+        
+                q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_hi (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t3),
+                    .datain_fall   (hr_data_t1),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (wr_fr_data_hi[opin_num])
+                );
+        
+                q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_oe (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (write_oe_in [opin_num + PIN_WIDTH]),
+                    .datain_fall   (write_oe_in [opin_num + 0]),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (fr_oe[opin_num])
+                );
+
+                // FR capture
+                always_ff @ (posedge read_capture_clk_fr_dq[opin_num])
+                    begin
+                        ddio_phy_dq_r[opin_num]                 <= ddio_phy_dq[opin_num];
+                        ddio_phy_dq_r[opin_num + PIN_WIDTH]     <= ddio_phy_dq[opin_num + PIN_WIDTH];
+                        ddio_phy_dq_r1[opin_num]                 <= ddio_phy_dq_r[opin_num];
+                        ddio_phy_dq_r1[opin_num + PIN_WIDTH]     <= ddio_phy_dq_r[opin_num + PIN_WIDTH];
+                    end
+                
+        end
+endgenerate
+
+                altera_gpio_lite #(
+                    .PIN_TYPE                  ("bidir"),
+                    .SIZE                      (PIN_WIDTH),
+                    .REGISTER_MODE             ("ddr"),
+                    .BUFFER_TYPE               ("single-ended"),
+                    .ASYNC_MODE                ("none"),
+                    .SYNC_MODE                 ("none"),
+                    .BUS_HOLD                  ("false"),
+                    .OPEN_DRAIN_OUTPUT         ("false"),
+                    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+                    .INVERT_OUTPUT             ("false"),
+                    .INVERT_INPUT_CLOCK        ("true"),
+                    .INVERT_OUTPUT_CLOCK       ("false"),
+                    .INVERT_OE_INCLOCK         ("false"),
+                    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+                    .USE_DDIO_REG_TO_DRIVE_OE  ("true"),
+                    .USE_ADVANCED_DDR_FEATURES ("true"),
+                    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+                    .ENABLE_HR_CLOCK           ("true"),
+                    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+                    .ENABLE_PHASE_INVERT_CTRL_PORT ("true"),
+                    .ENABLE_NSLEEP_PORT        ("true")
+                ) dq_ddio_io (
+                    .sclr                      (1'b0),
+                    .inclock                   (dq_capture_clk),
+                    .fr_clock                  (read_capture_clk_fr_dq),
+                    .hr_clock                  (read_capture_clk_hr_dq),
+                    .invert_hr_clock           (invert_hr_clock), 
+                    .outclock                  (pll_write_clk),
+                    .phy_mem_clock             (pll_mem_clk_ddio),
+                    .dout                      ({rd_fr_data_hi, rd_fr_data_lo}),
+                    .din                       ({wr_fr_data_hi, wr_fr_data_lo}),
+                    .pad_io                    (phy_mem_dq),
+                    .oe                        (fr_oe),
+                    .inclocken                 (1'b1),            
+                    .outclocken                (1'b1),            
+                    .pad_io_b                  (),                
+                    .pad_in                    (8'b0000),         
+                    .pad_in_b                  (8'b0000),         
+                    .pad_out                   (),                
+                    .pad_out_b                 (),                
+                    .aset                      (1'b0),            
+                    .aclr                      (1'b0),            
+                    .nsleep                    ({8{|enable_mem_clk}})
+                    );
+
+generate
+if (REVERSE_READ_WORDS == "true")
+begin
+    assign ddio_phy_dq [PIN_WIDTH -1 : 0] = rd_fr_data_hi;
+    assign ddio_phy_dq [READ_PHY_DQ_WIDTH-1 :PIN_WIDTH] = rd_fr_data_lo;
+end
+else
+begin
+    assign ddio_phy_dq [PIN_WIDTH -1 : 0] = rd_fr_data_lo;
+    assign ddio_phy_dq [READ_PHY_DQ_WIDTH-1 :PIN_WIDTH] = rd_fr_data_hi;
+end
+endgenerate
+
+// FR to HR conversion
+
+always_ff @ (posedge read_capture_clk_hr_dq) rdata_hr <= {ddio_phy_dq_r,ddio_phy_dq_r1};
+
+
+always_ff @ (posedge pll_mem_clk) fr_os_oe_r <= fr_os_oe;
+
+//######################################
+// Instantiate DQS group
+//######################################
+generate
+begin: dqs_en 
+        q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+            .DATA_WIDTH    (1)
+        ) hr_to_fr_os_oe (
+            .hr_clk        (pll_afi_clk),
+            .fr_clk        (pll_mem_clk),
+            .datain_rise   (output_strobe_ena[1]),
+            .datain_fall   (output_strobe_ena[0]),
+            .muxsel        (dqs_ena_muxsel),
+            .dataout       (fr_os_oe)
+        );
+end
+endgenerate
+
+altera_gpio_lite #(
+    .PIN_TYPE                  ("bidir"),
+    .SIZE                      (1),
+    .REGISTER_MODE             ("ddr"),
+    .BUFFER_TYPE               ("pseudo_differential"),
+    .ASYNC_MODE                ("none"),
+    .SYNC_MODE                 ("none"),
+    .BUS_HOLD                  ("false"),
+    .OPEN_DRAIN_OUTPUT         ("false"),
+    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+    .INVERT_OUTPUT             ("false"),
+    .INVERT_INPUT_CLOCK        ("false"),
+    .INVERT_OUTPUT_CLOCK       ("false"),
+    .INVERT_OE_INCLOCK         ("false"),
+    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+    .USE_DDIO_REG_TO_DRIVE_OE  ("true"),
+    .USE_ADVANCED_DDR_FEATURES ("false"),
+    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+    .ENABLE_HR_CLOCK           ("false"),
+    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+    .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+    .ENABLE_OE_PORT            ("true"),
+    .ENABLE_NSLEEP_PORT        ("true")
+) dqs_ddio_io (
+    .inclock                   (1'b0),
+    .fr_clock                  (),
+    .hr_clock                  (),
+    .invert_hr_clock           (1'b0),
+    .dout                      (),
+    .pad_io                   (mem_dqs),         
+    .pad_io_b                 (mem_dqs_n),       
+    .pad_out                    (),
+    .pad_out_b                  (),
+    .sclr                      (1'b0),
+    .outclock                  (pll_mem_clk_ddio),
+    .phy_mem_clock             (pll_mem_clk_ddio),
+    .din                       (2'b01),
+
+    .oe                        (fr_os_oe_r),
+    .inclocken                 (1'b1),            
+    .outclocken                (1'b1),            
+    .pad_in                    (1'b1),            
+    .pad_in_b                  (1'b1),            
+    .aset                      (1'b0),            
+    .aclr                      (1'b0),            
+    .nsleep                    (|enable_mem_clk)
+    );
+
+
+//######################################
+// Instantiate extra output pins
+//######################################
+generate
+    genvar epin_num;
+    for (epin_num = 0; epin_num < EXTRA_OUTPUT_WIDTH; epin_num = epin_num + 1)
+    begin :extra_output_pad_gen
+            wire hr_data_t0 = extra_write_data_in [epin_num + 0*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t1 = extra_write_data_in [epin_num + 1*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t2 = extra_write_data_in [epin_num + 2*EXTRA_OUTPUT_WIDTH];
+            wire hr_data_t3 = extra_write_data_in [epin_num + 3*EXTRA_OUTPUT_WIDTH];
+
+                q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_lo (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t2),
+                    .datain_fall   (hr_data_t0),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (extra_wr_fr_data_lo[epin_num])
+                );
+
+                q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10    # (
+                    .DATA_WIDTH    (1)
+                ) hr_to_fr_hi (
+                    .hr_clk        (pll_afi_clk),
+                    .fr_clk        (pll_mem_clk),
+                    .datain_rise   (hr_data_t3),
+                    .datain_fall   (hr_data_t1),
+                    .muxsel        (wrdata_muxsel),
+                    .dataout       (extra_wr_fr_data_hi[epin_num])
+                );
+
+        end
+endgenerate
+                altera_gpio_lite #(
+                    .PIN_TYPE                  ("output"),
+                    .SIZE                      (1),
+                    .REGISTER_MODE             ("ddr"),
+                    .BUFFER_TYPE               ("single-ended"),
+                    .ASYNC_MODE                ("none"),
+                    .SYNC_MODE                 ("none"),
+                    .BUS_HOLD                  ("false"),
+                    .OPEN_DRAIN_OUTPUT         ("false"),
+                    .SET_REGISTER_OUTPUTS_HIGH ("false"),
+                    .INVERT_OUTPUT             ("false"),
+                    .INVERT_INPUT_CLOCK        ("false"),
+                    .INVERT_OUTPUT_CLOCK       ("false"),
+                    .INVERT_OE_INCLOCK         ("false"),
+                    .USE_ONE_REG_TO_DRIVE_OE   ("false"),
+                    .USE_DDIO_REG_TO_DRIVE_OE  ("false"),
+                    .USE_ADVANCED_DDR_FEATURES ("true"),
+                    .INVERT_CLKDIV_INPUT_CLOCK ("false"),
+                    .ENABLE_HR_CLOCK           ("false"),
+                    .ENABLE_OE_HALF_CYCLE_DELAY("false"),
+                    .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
+                    .ENABLE_OE_PORT            ("true")
+                ) extra_ddio_out (
+                    .sclr                      (1'b0),
+                    .outclock                  (pll_write_clk),                  
+                    .phy_mem_clock             (pll_mem_clk_ddio),             
+                    .din                       ({extra_wr_fr_data_hi, extra_wr_fr_data_lo}),                       
+                    .pad_out                   (extra_write_data_out),                       
+                    .oe                        (|enable_mem_clk),                   
+                    .outclocken                (1'b1),          
+                    .inclock                   (1'b0),          
+                    .inclocken                 (1'b0),          
+                    .fr_clock                  (),              
+                    .hr_clock                  (),              
+                    .invert_hr_clock           (1'b0),          
+                    .dout                      (),              
+                    .pad_io                    (),              
+                    .pad_io_b                  (),              
+                    .pad_in                    (1'b1),          
+                    .pad_in_b                  (1'b1),          
+                    .pad_out_b                 (),              
+                    .aset                      (1'b0),          
+                    .aclr                      (1'b0)           
+                    );
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
new file mode 100644
index 0000000..28ab199
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_flop_mem.v
@@ -0,0 +1,109 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
+module q_sys_mem_if_ddr3_emif_0_p0_flop_mem(
+	wr_reset_n,
+	wr_clk,
+	wr_en,
+	wr_addr,
+	wr_data,
+	rd_reset_n,
+	rd_clk,
+	rd_en,
+	rd_addr,
+	rd_data
+);
+
+parameter WRITE_MEM_DEPTH	= "";
+parameter WRITE_ADDR_WIDTH	= "";
+parameter WRITE_DATA_WIDTH	= "";
+parameter READ_MEM_DEPTH	= "";
+parameter READ_ADDR_WIDTH	= "";		 
+parameter READ_DATA_WIDTH	= "";
+
+
+input	wr_reset_n;
+input	wr_clk;
+input	wr_en;
+input	[WRITE_ADDR_WIDTH-1:0] wr_addr;
+input	[WRITE_DATA_WIDTH-1:0] wr_data;
+input	rd_reset_n;
+input	rd_clk;
+input	rd_en;
+input	[READ_ADDR_WIDTH-1:0] rd_addr;
+output	[READ_DATA_WIDTH-1:0] rd_data;
+
+
+
+wire	[WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
+wire	[READ_DATA_WIDTH-1:0] mux_data_out;
+
+
+
+// declare a memory with WRITE_MEM_DEPTH entries
+// each entry contains a data size of WRITE_DATA_WIDTH
+reg	[WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
+reg	[READ_DATA_WIDTH-1:0] rd_data;
+
+generate
+genvar entry;
+	for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
+	begin: mem_location
+		assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry]; 
+		
+		always @(posedge wr_clk or negedge wr_reset_n)
+		begin
+			if (~wr_reset_n) begin
+				data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
+			end else begin
+				if (wr_en) begin
+					if (entry == wr_addr) begin
+						data_stored[entry] <= wr_data;
+					end
+				end
+			end
+		end		
+	end
+endgenerate
+
+// mux to select the correct output data based on read address
+lpm_mux	uread_mux(
+	.sel (rd_addr),
+	.data (all_data),
+	.result (mux_data_out)
+	// synopsys translate_off
+	,
+	.aclr (),
+	.clken (),
+	.clock ()
+	// synopsys translate_on
+	);
+ defparam uread_mux.lpm_size = READ_MEM_DEPTH;
+ defparam uread_mux.lpm_type = "LPM_MUX";
+ defparam uread_mux.lpm_width = READ_DATA_WIDTH;
+ defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
+
+always @(posedge rd_clk or negedge rd_reset_n)	
+begin
+	if (~rd_reset_n) begin
+		rd_data <= {READ_DATA_WIDTH{1'b0}};
+	end else begin
+		rd_data <= mux_data_out;
+	end
+end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
new file mode 100644
index 0000000..4a4dbf5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter.v
@@ -0,0 +1,88 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: fr_cycle_shifter.v
+//
+// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
+// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
+// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
+// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
+// "__" means don't-care.
+//
+// shift_by          dataout in current cycle            dataout in next clock cycle 
+//    00                {T3, T2, T1, T0}                    {__, __, __, __}
+//    01                {T2, T1, T0, __}                    {__, __, __, T3}
+//    10                {T1, T0, __, __}                    {__, __, T3, T2}
+//    11                {T0, __, __, __}                    {__, T3, T2, T1}
+// 
+// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
+// (i.e. you can only shift by 0 or 1 fr-cycle).
+// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
+//
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter(
+	clk,
+	reset_n,
+	shift_by,
+	datain,
+	dataout
+);
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver 
+
+parameter DATA_WIDTH = ""; 
+parameter REG_POST_RESET_HIGH = "false";
+
+localparam RATE_MULT = 2;
+localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+input	clk;
+input	reset_n;
+input	[1:0] shift_by; 
+input	[FULL_DATA_WIDTH-1:0] datain;
+output	[FULL_DATA_WIDTH-1:0] dataout;
+
+
+reg [FULL_DATA_WIDTH-1:0] datain_r;
+always @(posedge clk or negedge reset_n)
+begin
+	if (~reset_n) begin
+		if (REG_POST_RESET_HIGH == "true")
+			datain_r <= {FULL_DATA_WIDTH{1'b1}};
+		else
+			datain_r <= {FULL_DATA_WIDTH{1'b0}};
+	end else begin
+		datain_r <= datain;
+	end
+end
+
+wire [FULL_DATA_WIDTH-1:0] dataout_pre;
+
+
+wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
+wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
+wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
+
+assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
+	
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
new file mode 100644
index 0000000..141991b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_iss_probe.v
@@ -0,0 +1,60 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_iss_probe (
+	probe_input
+);
+parameter WIDTH = 1;
+parameter ID_NAME = "PROB";
+
+input [WIDTH-1:0] probe_input;
+
+	
+altsource_probe	iss_probe_inst (
+				.probe (probe_input),
+				.source ()
+				// synopsys translate_off
+				,
+				.clr (),
+				.ena (),
+				.ir_in (),
+				.ir_out (),
+				.jtag_state_cdr (),
+				.jtag_state_cir (),
+				.jtag_state_e1dr (),
+				.jtag_state_sdr (),
+				.jtag_state_tlr (),
+				.jtag_state_udr (),
+				.jtag_state_uir (),
+				.raw_tck (),
+				.source_clk (),
+				.source_ena (),
+				.tdi (),
+				.tdo (),
+				.usr1 ()
+				// synopsys translate_on
+				);
+	defparam
+		iss_probe_inst.enable_metastability = "NO",
+		iss_probe_inst.instance_id = ID_NAME,
+		iss_probe_inst.probe_width = WIDTH,
+		iss_probe_inst.sld_auto_instance_index = "YES",
+		iss_probe_inst.sld_instance_index = 0,
+		iss_probe_inst.source_initial_value = "0",
+		iss_probe_inst.source_width = 0;
+		
+		
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
new file mode 100644
index 0000000..8f7c86f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_memphy_m10.sv
@@ -0,0 +1,580 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: memphy.v
+// This file instantiates all the main components of the PHY. 
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_memphy_m10(
+    global_reset_n,
+    soft_reset_n,
+    ctl_reset_n,
+    ctl_reset_export_n,
+    pll_locked,
+    afi_addr,
+    afi_cke,
+    afi_cs_n,
+    afi_ba,
+    afi_ras_n,
+    afi_cas_n,
+    afi_we_n,
+    afi_odt,
+    afi_rst_n,
+    afi_mem_clk_disable,
+    afi_dqs_burst,
+    afi_wdata,
+    afi_wdata_valid,
+    afi_dm,
+    afi_rdata,
+    afi_rdata_en,
+    afi_rdata_valid,
+    afi_cal_debug_info,
+    afi_cal_success,
+    afi_cal_fail,
+
+    mem_a,
+    mem_ba,
+    mem_odt,
+    mem_ras_n,
+    mem_cas_n,
+    mem_we_n,
+    mem_reset_n,
+    mem_ck,
+    mem_ck_n,
+    mem_cke,
+    mem_cs_n,
+    mem_dm,
+    mem_dq,
+    mem_dqs,
+    mem_dqs_n,
+    phy_read_latency_counter,
+    phy_read_increment_vfifo_hr,
+    phy_cal_debug_info,
+    phy_read_fifo_reset,
+    phy_vfifo_rd_en_override,
+    calib_skip_steps,
+    pll_afi_clk,
+    pll_mem_clk,
+    pll_write_clk,
+    pll_capture0_clk,
+    pll_capture1_clk,
+    phy_clk,
+    phy_reset_n,
+    
+    pd_reset_n,
+    pd_ack,
+    pd_up,
+    pd_down
+);
+
+//  ******************************************************************************************************************************** 
+//  BEGIN PARAMETER SECTION
+//  All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver 
+parameter DEVICE_FAMILY                         = "";
+
+// PHY-Memory Interface
+// Memory device specific parameters, they are set according to the memory spec
+parameter MEM_ADDRESS_WIDTH                     = ""; 
+parameter MEM_BANK_WIDTH                        = "";
+parameter MEM_CLK_EN_WIDTH                      = ""; 
+parameter MEM_CK_WIDTH                          = ""; 
+parameter MEM_ODT_WIDTH                         = ""; 
+parameter MEM_DQS_WIDTH                         = "";
+parameter MEM_CHIP_SELECT_WIDTH                 = ""; 
+parameter MEM_CONTROL_WIDTH                     = ""; 
+parameter MEM_DM_WIDTH                          = ""; 
+parameter MEM_DQ_WIDTH                          = ""; 
+parameter MEM_READ_DQS_WIDTH                    = ""; 
+parameter MEM_WRITE_DQS_WIDTH                   = "";
+
+//  PHY-Controller (AFI) Interface
+//  The AFI interface widths are derived from the memory interface widths based on full/half rate operations
+//  The calculations are done on higher level wrapper
+parameter AFI_ADDRESS_WIDTH                     = ""; 
+parameter AFI_DEBUG_INFO_WIDTH                  = "";
+parameter AFI_BANK_WIDTH                        = "";
+parameter AFI_CHIP_SELECT_WIDTH                 = "";
+parameter AFI_CLK_EN_WIDTH                      = "";
+parameter AFI_ODT_WIDTH                         = "";
+parameter AFI_DATA_MASK_WIDTH                   = "";
+parameter AFI_CONTROL_WIDTH                     = "";
+parameter AFI_DATA_WIDTH                        = "";
+parameter AFI_DQS_WIDTH                         = "";
+parameter AFI_RATE_RATIO                        = "";
+
+// Write Datapath
+//The sequencer uses this value to control write latency during calibration
+parameter NUM_WRITE_PATH_FLOP_STAGES            = "";
+parameter NUM_WRITE_FR_CYCLE_SHIFTS             = "";
+
+parameter NUM_AC_FR_CYCLE_SHIFTS                = "";
+
+parameter CALIB_REG_WIDTH                       = "";
+
+//  The number of AFI Resets to generate
+localparam NUM_AFI_RESET = 4;
+
+//  Read Datapath parameters
+parameter MEM_T_RL                              = "";
+parameter MAX_LATENCY_COUNT_WIDTH               = "";
+localparam MAX_READ_LATENCY                     = MEM_T_RL/2 + 12; 
+localparam INVERT_HR_CLOCK                      = MEM_T_RL % 2;
+
+//  END PARAMETER SECTION
+//  ******************************************************************************************************************************** 
+
+//  ******************************************************************************************************************************** 
+//  BEGIN PORT SECTION
+
+//   Reset Interface
+input                                            global_reset_n;        //Resets (active-low) the whole system (all PHY logic + PLL)
+input                                            soft_reset_n;        
+input                                            pll_locked;        
+output                                           ctl_reset_export_n;    
+output                                           ctl_reset_n;        
+
+//  PHY-Controller Interface, AFI 2.0
+//  Control Interface
+input   [AFI_ADDRESS_WIDTH-1:0]                 afi_addr;               
+input   [AFI_CLK_EN_WIDTH-1:0]                  afi_cke;
+input   [AFI_CHIP_SELECT_WIDTH-1:0]             afi_cs_n;
+
+input   [AFI_BANK_WIDTH-1:0]                    afi_ba;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_cas_n;
+input   [AFI_ODT_WIDTH-1:0]                     afi_odt;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_ras_n;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_we_n;
+input   [AFI_CONTROL_WIDTH-1:0]                 afi_rst_n;
+
+input   [MEM_CK_WIDTH-1:0]                      afi_mem_clk_disable;
+input   [AFI_DQS_WIDTH-1:0]                     afi_dqs_burst;
+
+//  Write data interface
+input   [AFI_DATA_WIDTH-1:0]                    afi_wdata;              //write data
+input   [AFI_DQS_WIDTH-1:0]                     afi_wdata_valid;        
+
+input   [AFI_DATA_MASK_WIDTH-1:0]               afi_dm;                 
+
+//  Read data interface
+output  [AFI_DATA_WIDTH-1:0]                    afi_rdata;              //read data                
+input   [AFI_RATE_RATIO-1:0]                    afi_rdata_en;           
+output  [AFI_RATE_RATIO-1:0]                    afi_rdata_valid;        
+
+//  Status interface
+input                                           afi_cal_success;        //calibration success
+input                                           afi_cal_fail;           
+output  [AFI_DEBUG_INFO_WIDTH - 1:0]            afi_cal_debug_info;
+
+
+//  PHY-Memory Interface
+output  [MEM_ADDRESS_WIDTH-1:0]                 mem_a;
+output  [MEM_BANK_WIDTH-1:0]                    mem_ba;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_ras_n;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_cas_n;
+output  [MEM_CONTROL_WIDTH-1:0]                 mem_we_n;
+output  [MEM_ODT_WIDTH-1:0]                     mem_odt;
+output                                          mem_reset_n;
+inout   [MEM_CK_WIDTH-1:0]                      mem_ck;
+inout   [MEM_CK_WIDTH-1:0]                      mem_ck_n;
+output  [MEM_CLK_EN_WIDTH-1:0]                  mem_cke;
+output  [MEM_CHIP_SELECT_WIDTH-1:0]             mem_cs_n;
+output  [MEM_DM_WIDTH-1:0]                      mem_dm;
+inout   [MEM_DQ_WIDTH-1:0]                      mem_dq;
+inout   [MEM_DQS_WIDTH-1:0]                     mem_dqs;
+inout   [MEM_DQS_WIDTH-1:0]                     mem_dqs_n;
+
+input   [MAX_LATENCY_COUNT_WIDTH-1:0]           phy_read_latency_counter;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_read_increment_vfifo_hr;
+input   [AFI_DEBUG_INFO_WIDTH - 1:0]            phy_cal_debug_info;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_read_fifo_reset;
+input   [MEM_READ_DQS_WIDTH-1:0]                phy_vfifo_rd_en_override;
+
+output  [CALIB_REG_WIDTH-1:0]                   calib_skip_steps;
+
+//  PLL Interface
+input                                           pll_afi_clk;        //clocks AFI interface logic
+input                                           pll_mem_clk;        
+input                                           pll_write_clk;        
+input                                           pll_capture0_clk;
+input                                           pll_capture1_clk;
+
+//  output to sequencer
+output                                          phy_clk;
+output                                          phy_reset_n;
+
+input                                           pd_reset_n;
+input                                           pd_ack;
+output                                          pd_up;
+output                                          pd_down;
+
+//  END PORT SECTION
+//  ******************************************************************************************************************************** 
+
+// PHY clock tree buffered clock driving to DDIO
+wire                                            pll_mem_clk_ddio;           
+wire                                            pll_write_clk_ddio;      
+wire                                            pll_capture0_clk_ddio;
+wire                                            pll_capture1_clk_ddio;
+
+wire    [AFI_ADDRESS_WIDTH-1:0]                 phy_ddio_address;
+wire    [AFI_BANK_WIDTH-1:0]                    phy_ddio_bank;
+wire    [AFI_CHIP_SELECT_WIDTH-1:0]             phy_ddio_cs_n;
+wire    [AFI_CLK_EN_WIDTH-1:0]                  phy_ddio_cke;
+wire    [AFI_ODT_WIDTH-1:0]                     phy_ddio_odt;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_ras_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_cas_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_we_n;
+wire    [AFI_CONTROL_WIDTH-1:0]                 phy_ddio_reset_n;
+wire    [AFI_DATA_WIDTH-1:0]                    phy_ddio_dq;
+wire    [AFI_DQS_WIDTH-1:0]                     phy_ddio_dqs_en;
+wire    [AFI_DQS_WIDTH-1:0]                     phy_ddio_wrdata_en;
+wire    [AFI_DATA_MASK_WIDTH-1:0]               phy_ddio_wrdata_mask;
+wire    [AFI_DATA_WIDTH-1:0]                    ddio_phy_dq;
+wire    [MEM_READ_DQS_WIDTH-1:0]                read_capture_clk_hr_dq;
+
+
+wire    [NUM_AFI_RESET-1:0]                     reset_n_afi_clk;
+wire                                            reset_n_resync_clk;
+wire                                            invert_hr_clock;
+
+localparam SKIP_CALIBRATION_STEPS       = 7'b1111111;
+localparam CALIBRATION_STEPS            = SKIP_CALIBRATION_STEPS;
+localparam SKIP_MEM_INIT                = 1'b1;
+localparam SEQ_CALIB_INIT               = {CALIBRATION_STEPS, SKIP_MEM_INIT};
+
+localparam NUM_OF_DQDQS                 = MEM_WRITE_DQS_WIDTH;
+localparam DQDQS_DATA_WIDTH             = MEM_DQ_WIDTH / NUM_OF_DQDQS;
+localparam DQDQS_DM_WIDTH               = MEM_DM_WIDTH / NUM_OF_DQDQS;
+localparam DQDQS_DDIO_PHY_DQ_WIDTH      = AFI_DATA_WIDTH / NUM_OF_DQDQS;
+
+reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
+
+//  Initialization of the sequencer status register. This register
+//  is preserved in the netlist so that it can be forced during simulation
+always @(posedge pll_afi_clk)
+    `ifndef SYNTH_FOR_SIM
+    `endif
+    seq_calib_init_reg <= SEQ_CALIB_INIT;
+    `ifndef SYNTH_FOR_SIM
+    `endif
+    `ifndef SYNTH_FOR_SIM
+    `endif
+
+//  ******************************************************************************************************************************** 
+//  Instantiate PHYCLK buffer for fitter 
+//  ******************************************************************************************************************************** 
+        fiftyfivenm_phy_clkbuf uphy_clkbuf(
+                .inclk ({pll_capture1_clk, pll_capture0_clk, pll_write_clk, pll_mem_clk}),
+                .outclk ({pll_capture1_clk_ddio, pll_capture0_clk_ddio, pll_write_clk_ddio, pll_mem_clk_ddio})
+        );
+
+//  ******************************************************************************************************************************** 
+//  The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
+//  The reset block has 2 main functionalities:
+//  1. Keep all the PHY logic in reset state until after the PLL is locked
+//  2. Synchronize the reset to each clock domain 
+//  ******************************************************************************************************************************** 
+
+
+    q_sys_mem_if_ddr3_emif_0_p0_reset_m10    ureset(
+        .pll_afi_clk            (pll_afi_clk),
+        .pll_write_clk          (pll_write_clk),
+        .pll_locked             (pll_locked),
+        .global_reset_n         (global_reset_n),
+        .soft_reset_n           (soft_reset_n),
+        .ctl_reset_export_n     (ctl_reset_export_n),
+        .ctl_reset_n            (ctl_reset_n),
+        .reset_n_afi_clk        (reset_n_afi_clk),
+        .reset_n_resync_clk     (reset_n_resync_clk)
+    );
+
+    defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
+    defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
+
+assign calib_skip_steps = seq_calib_init_reg;
+assign afi_cal_debug_info = phy_cal_debug_info;
+
+assign phy_clk = pll_afi_clk;
+assign phy_reset_n = reset_n_afi_clk[0];
+
+
+//  ******************************************************************************************************************************** 
+//  The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
+//  interface and the output DDIOs.
+//  ******************************************************************************************************************************** 
+
+    q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_datapath    uaddr_cmd_datapath(
+        .clk                (pll_afi_clk), 
+        .reset_n            (reset_n_afi_clk[1]), 
+        .afi_address        (afi_addr),
+        .afi_cke            (afi_cke),
+        .afi_cs_n           (afi_cs_n),
+        .afi_bank           (afi_ba),
+        .afi_odt            (afi_odt),
+        .afi_ras_n          (afi_ras_n),
+        .afi_cas_n          (afi_cas_n),
+        .afi_we_n           (afi_we_n),
+        .phy_ddio_odt       (phy_ddio_odt),
+        .phy_ddio_bank      (phy_ddio_bank),
+        .phy_ddio_we_n      (phy_ddio_we_n),
+        .phy_ddio_ras_n     (phy_ddio_ras_n),
+        .phy_ddio_cas_n     (phy_ddio_cas_n),
+        .afi_rst_n          (afi_rst_n),
+        .phy_ddio_reset_n   (phy_ddio_reset_n),
+        .phy_ddio_address   (phy_ddio_address),
+        .phy_ddio_cke       (phy_ddio_cke),
+        .phy_ddio_cs_n      (phy_ddio_cs_n)
+    );
+        defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH                  = MEM_ADDRESS_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_BANK_WIDTH                     = MEM_BANK_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH              = MEM_CHIP_SELECT_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH                   = MEM_CLK_EN_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_ODT_WIDTH                      = MEM_ODT_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_DM_WIDTH                       = MEM_DM_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH                  = MEM_CONTROL_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_DQ_WIDTH                       = MEM_DQ_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH                 = MEM_READ_DQS_WIDTH;
+        defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH                = MEM_WRITE_DQS_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH                  = AFI_ADDRESS_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_BANK_WIDTH                     = AFI_BANK_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH              = AFI_CHIP_SELECT_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH                   = AFI_CLK_EN_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_ODT_WIDTH                      = AFI_ODT_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH                = AFI_DATA_MASK_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH                  = AFI_CONTROL_WIDTH;
+        defparam uaddr_cmd_datapath.AFI_DATA_WIDTH                     = AFI_DATA_WIDTH;
+        defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS             = NUM_AC_FR_CYCLE_SHIFTS;    
+
+
+
+//  ******************************************************************************************************************************** 
+//  The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface 
+//  and the output DDIOs.
+//  ******************************************************************************************************************************** 
+
+    q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10    uwrite_datapath(
+        .pll_afi_clk                   (pll_afi_clk),
+        .reset_n                       (reset_n_afi_clk[2]),
+        .afi_dqs_en                    (afi_dqs_burst),
+        .afi_wdata                     (afi_wdata),
+        .afi_wdata_valid               (afi_wdata_valid),
+        .afi_dm                        (afi_dm),
+        .phy_ddio_dq                   (phy_ddio_dq),
+        .phy_ddio_dqs_en               (phy_ddio_dqs_en),
+        .phy_ddio_wrdata_en            (phy_ddio_wrdata_en),
+        .phy_ddio_wrdata_mask          (phy_ddio_wrdata_mask)
+    );
+        defparam uwrite_datapath.MEM_ADDRESS_WIDTH                  = MEM_ADDRESS_WIDTH;
+        defparam uwrite_datapath.MEM_DM_WIDTH                       = MEM_DM_WIDTH;
+        defparam uwrite_datapath.MEM_CONTROL_WIDTH                  = MEM_CONTROL_WIDTH;
+        defparam uwrite_datapath.MEM_DQ_WIDTH                       = MEM_DQ_WIDTH;
+        defparam uwrite_datapath.MEM_READ_DQS_WIDTH                 = MEM_READ_DQS_WIDTH;
+        defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH                = MEM_WRITE_DQS_WIDTH;
+        defparam uwrite_datapath.AFI_ADDRESS_WIDTH                  = AFI_ADDRESS_WIDTH;
+        defparam uwrite_datapath.AFI_DATA_MASK_WIDTH                = AFI_DATA_MASK_WIDTH;
+        defparam uwrite_datapath.AFI_CONTROL_WIDTH                  = AFI_CONTROL_WIDTH;
+        defparam uwrite_datapath.AFI_DATA_WIDTH                     = AFI_DATA_WIDTH;
+        defparam uwrite_datapath.AFI_DQS_WIDTH                      = AFI_DQS_WIDTH;
+        defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES         = NUM_WRITE_PATH_FLOP_STAGES;
+        defparam uwrite_datapath.NUM_WRITE_FR_CYCLE_SHIFTS          = NUM_WRITE_FR_CYCLE_SHIFTS;
+
+     
+//  ******************************************************************************************************************************** 
+//  The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
+//  It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
+//  ******************************************************************************************************************************** 
+
+    q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10    uread_datapath(
+        .reset_n_afi_clk            (reset_n_afi_clk[3]),
+        .pll_afi_clk                (pll_afi_clk),
+        .read_capture_clk_hr_dq     (read_capture_clk_hr_dq),
+        .rdata_hr                   (ddio_phy_dq),
+        .seq_read_increment_vfifo   (phy_read_increment_vfifo_hr),
+        .seq_read_fifo_reset        (phy_read_fifo_reset),
+        .seq_read_latency_counter   (phy_read_latency_counter),
+        .afi_rdata_en               (afi_rdata_en),
+        .afi_rdata                  (afi_rdata),
+        .afi_rdata_valid            (afi_rdata_valid)
+    );
+    defparam uread_datapath.DEVICE_FAMILY                          = DEVICE_FAMILY;
+    defparam uread_datapath.MEM_ADDRESS_WIDTH                      = MEM_ADDRESS_WIDTH; 
+    defparam uread_datapath.MEM_DM_WIDTH                           = MEM_DM_WIDTH; 
+    defparam uread_datapath.MEM_CONTROL_WIDTH                      = MEM_CONTROL_WIDTH; 
+    defparam uread_datapath.MEM_DQ_WIDTH                           = MEM_DQ_WIDTH; 
+    defparam uread_datapath.MEM_READ_DQS_WIDTH                     = MEM_READ_DQS_WIDTH; 
+    defparam uread_datapath.MEM_WRITE_DQS_WIDTH                    = MEM_WRITE_DQS_WIDTH; 
+    defparam uread_datapath.AFI_ADDRESS_WIDTH                      = AFI_ADDRESS_WIDTH; 
+    defparam uread_datapath.AFI_DATA_MASK_WIDTH                    = AFI_DATA_MASK_WIDTH; 
+    defparam uread_datapath.AFI_CONTROL_WIDTH                      = AFI_CONTROL_WIDTH; 
+    defparam uread_datapath.AFI_DATA_WIDTH                         = AFI_DATA_WIDTH; 
+    defparam uread_datapath.AFI_DQS_WIDTH                          = AFI_DQS_WIDTH;
+    defparam uread_datapath.AFI_RATE_RATIO                         = AFI_RATE_RATIO;
+    defparam uread_datapath.NUM_OF_DQDQS                           = NUM_OF_DQDQS;
+    defparam uread_datapath.DQDQS_DATA_WIDTH                       = DQDQS_DATA_WIDTH;
+    defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH                = MAX_LATENCY_COUNT_WIDTH;
+    defparam uread_datapath.MAX_READ_LATENCY                       = MAX_READ_LATENCY;
+    defparam uread_datapath.MEM_T_RL                               = MEM_T_RL;
+
+//  ******************************************************************************************************************************** 
+//  The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
+//  ******************************************************************************************************************************** 
+
+wire addr_cmd_clk;
+wire mimic_clock;
+
+        assign addr_cmd_clk = pll_mem_clk_ddio;
+        localparam INVERT_OUTPUT_CLOCK = "true";
+
+    q_sys_mem_if_ddr3_emif_0_p0_addr_cmd_pads_m10 uaddr_cmd_pads(
+        .reset_n            (reset_n_afi_clk[3]),
+        .pll_afi_clk        (pll_afi_clk),
+        .pll_mem_clk_ddio   (pll_mem_clk_ddio),
+        .pll_mem_clk        (pll_mem_clk),
+        .pll_write_clk      (addr_cmd_clk),
+        .enable_mem_clk     (~afi_mem_clk_disable),
+        .phy_ddio_address   (phy_ddio_address),
+        .phy_ddio_cs_n      (phy_ddio_cs_n),
+        .phy_ddio_cke       (phy_ddio_cke),
+        .phy_ddio_bank      (phy_ddio_bank),
+        .phy_ddio_odt       (phy_ddio_odt),
+        .phy_ddio_we_n      (phy_ddio_we_n),    
+        .phy_ddio_ras_n     (phy_ddio_ras_n),
+        .phy_ddio_cas_n     (phy_ddio_cas_n),
+        .phy_ddio_reset_n   (phy_ddio_reset_n),
+
+        .phy_mem_cs_n       (mem_cs_n),
+        .phy_mem_cke        (mem_cke),
+        .phy_mem_address    (mem_a),
+        .phy_mem_bank       (mem_ba),
+        .phy_mem_odt        (mem_odt),
+        .phy_mem_we_n       (mem_we_n),
+        .phy_mem_ras_n      (mem_ras_n),
+        .phy_mem_cas_n      (mem_cas_n),
+        .phy_mem_reset_n    (mem_reset_n),
+        .phy_mem_ck         (mem_ck),
+        .phy_mem_ck_n       (mem_ck_n),
+        .mimic_clock        (mimic_clock)
+    );
+    defparam uaddr_cmd_pads.DEVICE_FAMILY           = DEVICE_FAMILY;
+    defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH       = MEM_ADDRESS_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH   = MEM_CHIP_SELECT_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH        = MEM_CLK_EN_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH       = MEM_CONTROL_WIDTH;
+    defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH       = AFI_ADDRESS_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH   = AFI_CHIP_SELECT_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH        = AFI_CLK_EN_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH       = AFI_CONTROL_WIDTH; 
+    defparam uaddr_cmd_pads.INVERT_OUTPUT_CLOCK     = INVERT_OUTPUT_CLOCK;
+
+    defparam uaddr_cmd_pads.MEM_BANK_WIDTH          = MEM_BANK_WIDTH;
+    defparam uaddr_cmd_pads.MEM_ODT_WIDTH           = MEM_ODT_WIDTH;
+    defparam uaddr_cmd_pads.MEM_CK_WIDTH            = MEM_CK_WIDTH;
+    defparam uaddr_cmd_pads.AFI_BANK_WIDTH          = AFI_BANK_WIDTH; 
+    defparam uaddr_cmd_pads.AFI_ODT_WIDTH           = AFI_ODT_WIDTH; 
+
+        generate
+        if (INVERT_HR_CLOCK == 1)
+                assign invert_hr_clock = 1'b1;
+        else
+                assign invert_hr_clock = 1'b0;
+        endgenerate
+
+        generate
+    genvar i;
+    for (i=0; i<NUM_OF_DQDQS; i=i+1)
+    begin: dq_ddio
+        wire dqs_busout;
+
+        //  The phy_ddio_dq bus is the write data for all DQS groups in one
+        //  AFI cycle. The bus is ordered by time slot and subordered by DQS group:
+        // 
+        // FR: D1_T1, D0_T1, D1_T0, D0_T0
+        // HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
+        //
+        // Extract the write data targeting the current DQS group
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
+
+        // Extract the OE signal targeting the current DQS group
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t0 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i]}};
+        wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t1 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i+NUM_OF_DQDQS]}};
+
+        // Extract the write data mask signal targeting the current DQS group
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
+        wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
+        assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS)];
+        assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS)];
+
+        wire pll_capture_clk;
+        assign  pll_capture_clk = pll_capture0_clk_ddio;
+
+        q_sys_mem_if_ddr3_emif_0_p0_dqdqs_pads_m10 ubidir_dq_dqs (
+            .reset_n_afi_clk        (reset_n_afi_clk[3]),
+            .pll_afi_clk            (pll_afi_clk),
+            .pll_mem_clk_ddio       (pll_mem_clk_ddio),
+            .pll_mem_clk            (pll_mem_clk),
+            .pll_write_clk          (pll_write_clk_ddio),
+            .enable_mem_clk         (~afi_mem_clk_disable),
+            .dq_capture_clk         (pll_capture_clk), // calibrated capture clock
+            .read_capture_clk_hr_dq (read_capture_clk_hr_dq[i]), // to read datapath
+            .invert_hr_clock        (invert_hr_clock),
+
+            .phy_mem_dq (mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
+            .mem_dqs                (mem_dqs[i]),
+            .mem_dqs_n              (mem_dqs_n[i]),
+
+            .extra_write_data_in    ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
+            .extra_write_data_out   (mem_dm[i]),
+
+            .rdata_hr               (ddio_phy_dq[(DQDQS_DDIO_PHY_DQ_WIDTH*(i+1)-1) : DQDQS_DDIO_PHY_DQ_WIDTH*i]),
+            .write_oe_in            ({phy_ddio_wrdata_en_t1, phy_ddio_wrdata_en_t0}),
+            .write_data_in          ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
+            .output_strobe_ena      ({phy_ddio_dqs_en[i+NUM_OF_DQDQS], phy_ddio_dqs_en[i]})
+        );
+        defparam ubidir_dq_dqs.MEM_CK_WIDTH            = MEM_CK_WIDTH;
+        
+    end
+    endgenerate
+    
+//  ******************************************************************************************************************************** 
+//  Instantiate phase detector
+//  ******************************************************************************************************************************** 
+    fiftyfivenm_phase_detector phase_detector_inst
+    (
+        .reset      (~pd_reset_n),
+        .phasedone  (pd_ack),
+        .clk        ({mimic_clock,pll_capture1_clk,pll_afi_clk}),
+        .up         (pd_up),
+        .down       (pd_down)
+    );
+
+// Calculate the ceiling of log_2 of the input value
+function integer ceil_log2;
+    input integer value;
+    begin
+        value = value - 1;
+        for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
+            value = value >> 1;
+    end
+endfunction
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
new file mode 100644
index 0000000..1846acf
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10.sv
@@ -0,0 +1,187 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// File name: read_datapath.sv
+// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
+// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+// altera message_off 10036 10030 10858
+module q_sys_mem_if_ddr3_emif_0_p0_read_datapath_m10(
+    pll_afi_clk,
+    reset_n_afi_clk,
+    read_capture_clk_hr_dq,
+    rdata_hr,
+    afi_rdata_en,
+    afi_rdata,
+    afi_rdata_valid,
+    seq_read_fifo_reset,
+    seq_read_latency_counter,
+    seq_read_increment_vfifo
+);
+
+// ********************************************************************************************************************************
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
+
+parameter DEVICE_FAMILY = "";
+
+// PHY-Memory Interface
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+// PHY-Controller (AFI) Interface
+parameter AFI_ADDRESS_WIDTH         = "";
+parameter AFI_DATA_MASK_WIDTH       = "";
+parameter AFI_CONTROL_WIDTH         = "";
+parameter AFI_DATA_WIDTH            = "";
+parameter AFI_DQS_WIDTH             = "";
+parameter AFI_RATE_RATIO            = "";
+parameter NUM_OF_DQDQS              = "";
+parameter DQDQS_DATA_WIDTH          = "";
+parameter MAX_READ_LATENCY          = "";
+parameter MAX_LATENCY_COUNT_WIDTH   = "";
+parameter DEVICE_WIDTH              = 1;
+parameter MEM_T_RL                  = "";
+
+// Local parameters
+localparam DDIO_PHY_DQ_WIDTH = AFI_DATA_WIDTH/NUM_OF_DQDQS;
+
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+input                                       reset_n_afi_clk;
+input                                       pll_afi_clk;
+input           [AFI_DATA_WIDTH-1:0]        rdata_hr;
+
+input           [MEM_READ_DQS_WIDTH-1:0]    seq_read_fifo_reset; // reset from sequencer to read and write pointers of the data resynchronization FIFO
+input           [MEM_READ_DQS_WIDTH-1:0]    seq_read_increment_vfifo;
+input           [MAX_LATENCY_COUNT_WIDTH-1:0] seq_read_latency_counter;
+input           [MEM_READ_DQS_WIDTH-1:0]    read_capture_clk_hr_dq;
+
+
+input           [AFI_RATE_RATIO-1:0]        afi_rdata_en;
+
+output          [AFI_DATA_WIDTH-1:0]        afi_rdata;
+output          [AFI_RATE_RATIO-1:0]        afi_rdata_valid;
+
+logic           [AFI_DATA_WIDTH-1:0]        rdata_reorder;
+logic           [NUM_OF_DQDQS-1 : 0]        vfifo_output;
+
+reg             [MEM_READ_DQS_WIDTH-1:0]    read_enable_from_lfifo;
+wire            [MEM_READ_DQS_WIDTH-1:0]    rdata_fifo_full;
+wire            [MEM_READ_DQS_WIDTH-1:0]    lfifo_full;
+
+// VFIFO read increment per capture clock
+
+// VFIFO pointer
+
+logic [MAX_READ_LATENCY-1:0] vfifo;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_shifter
+        if (!reset_n_afi_clk)
+            vfifo <= 0;
+        else
+            vfifo <= {vfifo[MAX_READ_LATENCY-2:0], afi_rdata_en[0]};
+    end
+
+logic [2:0] vfifo_pointer;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_pointer_gen
+        if (!reset_n_afi_clk)
+            vfifo_pointer <= 0;
+        else if (seq_read_increment_vfifo[0])
+            vfifo_pointer <= vfifo_pointer + 1'b1;
+    end
+
+localparam VFIFO_OFFSET = MAX_READ_LATENCY - 8;
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin: vfifo_rden
+        if (!reset_n_afi_clk)
+            vfifo_output <= 0;
+        else
+            vfifo_output <= vfifo[vfifo_pointer+VFIFO_OFFSET];
+    end
+
+logic [3:0] reset_counter;
+logic	write_req;
+logic	read_req;
+
+always_ff @ (posedge pll_afi_clk, negedge reset_n_afi_clk)
+    begin
+        if (!reset_n_afi_clk)
+			begin
+				write_req	<=	0;
+				read_req		<=	0;
+				reset_counter	<=	'0;
+			end
+		else
+			begin
+				if (!(&reset_counter))
+					reset_counter	<=	reset_counter + 1'b1;
+				
+				if (reset_counter > 5)
+					write_req	<=	1;
+				
+				if (reset_counter > 9)
+					read_req		<=	1;
+			end
+	end
+
+// HR rdata clock cross into afi_clk domain
+
+wire [DDIO_PHY_DQ_WIDTH-1:0] read_fifo_output_per_dqs;
+
+    max10emif_dcfifo    rdata_fifo (
+                .data (rdata_hr),
+                .rdclk (pll_afi_clk),
+                .rdreq (read_req),
+                .wrclk (read_capture_clk_hr_dq[0]),
+                .wrreq (write_req),
+                .q (rdata_reorder),
+                .aclr (~reset_n_afi_clk));
+    defparam
+        rdata_fifo.numwords = 8,
+        rdata_fifo.width = AFI_DATA_WIDTH,
+        rdata_fifo.widthu = 3;
+
+// Read data reorder
+generate
+genvar i;
+for (i=0; i<NUM_OF_DQDQS; i=i+1)
+begin: rdata_per_dq_group
+
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+1)-1 : DQDQS_DATA_WIDTH*(i*4+0)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+2)-1 : DQDQS_DATA_WIDTH*(i*4+1)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+3)-1 : DQDQS_DATA_WIDTH*(i*4+2)];
+        assign afi_rdata[DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)] = rdata_reorder[DQDQS_DATA_WIDTH*(i*4+4)-1 : DQDQS_DATA_WIDTH*(i*4+3)];
+
+end
+endgenerate
+
+assign afi_rdata_valid = {2{vfifo_output}};
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
new file mode 100644
index 0000000..9b25aa5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector.v
@@ -0,0 +1,89 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_read_valid_selector(
+	reset_n,
+	pll_afi_clk,
+	latency_shifter,
+	latency_counter,
+	read_enable,
+	read_valid
+);
+
+parameter MAX_LATENCY_COUNT_WIDTH	= "";
+
+localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
+
+input	reset_n;
+input	pll_afi_clk;
+input	[LATENCY_NUM-1:0] latency_shifter;
+input	[MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
+output	read_enable;
+output	read_valid;
+
+wire	[LATENCY_NUM-1:0] selector;
+reg [LATENCY_NUM-1:0] selector_reg;
+reg	read_enable;
+reg reading_data;
+reg	read_valid;
+
+wire	[LATENCY_NUM-1:0] valid_select;
+
+
+	lpm_decode	uvalid_select(
+        .data (latency_counter),
+        .eq (selector)
+        // synopsys translate_off
+        ,
+        .aclr (),
+        .clken (),
+        .clock (),
+        .enable ()
+        // synopsys translate_on
+	);
+
+	defparam uvalid_select.lpm_decodes = LATENCY_NUM;
+	defparam uvalid_select.lpm_type = "LPM_DECODE";
+	defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
+
+
+	always @(posedge pll_afi_clk or negedge reset_n)
+	begin
+		if (~reset_n)
+			selector_reg <= {LATENCY_NUM{1'b0}};
+		else
+			selector_reg <= selector;
+	end
+
+	assign valid_select = selector_reg & latency_shifter;
+
+
+    always @(posedge pll_afi_clk or negedge reset_n)
+    begin
+        if (~reset_n)
+        begin
+            read_enable <= 1'b0;
+            read_valid <= 1'b0;
+        end
+        else
+        begin
+            read_enable <= |valid_select;
+	
+            read_valid <= |valid_select;
+        end
+    end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
new file mode 100644
index 0000000..ad46221
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_m10.v
@@ -0,0 +1,82 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
+module q_sys_mem_if_ddr3_emif_0_p0_reset_m10(
+	pll_afi_clk,
+	pll_write_clk,
+	pll_locked,
+	global_reset_n,
+	soft_reset_n,
+	ctl_reset_n,
+	ctl_reset_export_n,
+	reset_n_afi_clk,
+	reset_n_resync_clk
+);
+
+
+parameter MEM_READ_DQS_WIDTH = ""; 
+
+parameter NUM_AFI_RESET = 1;
+
+
+
+input	pll_afi_clk;
+input	pll_write_clk;
+input	pll_locked;
+input	global_reset_n;
+input	soft_reset_n;
+output	ctl_reset_n;
+output  ctl_reset_export_n;
+output	[NUM_AFI_RESET-1:0] reset_n_afi_clk;
+output	reset_n_resync_clk;
+// Apply the synthesis keep attribute on the synchronized reset wires
+// so that these names can be constrained using QSF settings to keep
+// the resets on local routing.
+wire	phy_reset_n /* synthesis keep = 1 */;
+wire	phy_reset_mem_stable_n /* synthesis keep = 1*/;
+
+wire	[MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
+
+        assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
+
+	q_sys_mem_if_ddr3_emif_0_p0_reset_sync	ureset_afi_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_afi_clk),
+		.reset_n_sync	(reset_n_afi_clk)
+	);
+	defparam ureset_afi_clk.RESET_SYNC_STAGES = 15; 
+	defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
+
+	q_sys_mem_if_ddr3_emif_0_p0_reset_sync	ureset_ctl_reset_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_afi_clk),
+		.reset_n_sync	({ctl_reset_n, ctl_reset_export_n})
+	);
+	defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
+	defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
+
+
+	q_sys_mem_if_ddr3_emif_0_p0_reset_sync	ureset_resync_clk(
+		.reset_n		(phy_reset_n),
+		.clk			(pll_write_clk),
+		.reset_n_sync	(reset_n_resync_clk)
+	);
+	defparam ureset_resync_clk.RESET_SYNC_STAGES = 15; 
+	defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
new file mode 100644
index 0000000..7a5af1e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_reset_sync.v
@@ -0,0 +1,62 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_reset_sync(
+	reset_n,
+	clk,
+	reset_n_sync
+);
+
+parameter RESET_SYNC_STAGES = 4;
+parameter NUM_RESET_OUTPUT = 1;
+
+input	reset_n;
+input	clk;
+output	[NUM_RESET_OUTPUT-1:0] reset_n_sync;
+
+
+
+
+// identify the synchronizer chain so that Quartus can analyze metastability.
+// Since these resets are localized to the PHY alone, make them routed locally
+// to avoid using global networks.
+(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg	[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
+
+generate
+genvar i;
+	for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
+	begin: reset_stage
+		always @(posedge clk or negedge reset_n)
+		begin
+			if (~reset_n)
+				reset_reg[i] <= 1'b0;
+			else
+			begin
+				if (i==0)
+					reset_reg[i] <= 1'b1;
+				else if (i < RESET_SYNC_STAGES)
+					reset_reg[i] <= reset_reg[i-1];
+				else
+					reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
+				
+			end
+		end
+	end
+endgenerate
+
+	assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
new file mode 100644
index 0000000..babe56d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10.sv
@@ -0,0 +1,94 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// *****************************************************************
+// File name: simple_ddio_out_m10.sv
+//
+// This module can be used to double the data rate of the datain*
+// bus. Outputs at the dataout. 
+//
+// Example 1:
+//
+// datain_rise = T1 at clk cycle x of hr_clk, where each Ty is a data item
+// datain_fall = T0 at clk cycle x of hr_clk, where each Ty is a data item
+// with width DATA_WIDTH
+//
+//
+// dataout = {T0} at positive phase of clk cycle x clocked by fr_clk
+// dataout = {T1} at negative phase of clk cycle x clocked by fr_clk
+//
+// *****************************************************************
+
+
+`timescale 1 ps / 1 ps
+
+module q_sys_mem_if_ddr3_emif_0_p0_simple_ddio_out_m10(
+	hr_clk,
+	fr_clk,
+	datain_rise,
+        datain_fall,
+        muxsel,
+	dataout
+);
+
+// *****************************************************************
+// BEGIN PARAMETER SECTION
+
+parameter DATA_WIDTH = ""; 
+
+// END PARAMETER SECTION
+// *****************************************************************
+
+input	hr_clk;
+input   fr_clk;
+input	[DATA_WIDTH-1:0] datain_rise;
+input   [DATA_WIDTH-1:0] datain_fall;
+input   muxsel;
+output	[DATA_WIDTH-1:0] dataout;
+
+generate
+genvar i, j;
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [DATA_WIDTH-1:0] datain_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+	(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [DATA_WIDTH-1:0] datain_f /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+
+
+        always_ff @ (posedge hr_clk )
+	begin
+		datain_r <= datain_rise;
+	end
+
+        always_ff @ (negedge hr_clk)
+        begin
+                datain_f <= datain_fall;
+        end
+
+
+	reg [DATA_WIDTH-1:0] dataout_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
+	for (i=0; i<DATA_WIDTH; i=i+1)
+	begin: ddio_group
+
+                always_ff @ (posedge fr_clk)
+                begin
+                        if (muxsel)
+                        begin
+			        dataout_r[i] <= datain_f;
+                        end else begin
+                                dataout_r[i] <= datain_r;
+                        end
+		end
+	end
+	
+	assign dataout = dataout_r;
+	
+endgenerate
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
new file mode 100644
index 0000000..b0109db
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10.v
@@ -0,0 +1,195 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ***************************************************************************
+// File name: write_datapath.v
+// ***************************************************************************
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+module q_sys_mem_if_ddr3_emif_0_p0_write_datapath_m10(
+	pll_afi_clk,
+	reset_n,
+	afi_dqs_en,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_dm,
+	phy_ddio_dq,
+	phy_ddio_dqs_en,
+	phy_ddio_wrdata_en,
+	phy_ddio_wrdata_mask
+);
+
+
+parameter MEM_ADDRESS_WIDTH     = "";
+parameter MEM_DM_WIDTH          = "";
+parameter MEM_CONTROL_WIDTH     = "";
+parameter MEM_DQ_WIDTH          = "";
+parameter MEM_READ_DQS_WIDTH    = "";
+parameter MEM_WRITE_DQS_WIDTH   = "";
+
+parameter AFI_ADDRESS_WIDTH     = "";
+parameter AFI_DATA_MASK_WIDTH   = "";
+parameter AFI_CONTROL_WIDTH     = "";
+parameter AFI_DATA_WIDTH        = "";
+parameter AFI_DQS_WIDTH	        = "";
+
+parameter NUM_WRITE_PATH_FLOP_STAGES = "";
+parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
+
+localparam RATE_MULT = 2;
+localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
+
+localparam DM_GROUP_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
+
+
+input	pll_afi_clk;
+input	reset_n;
+input	[AFI_DQS_WIDTH-1:0] afi_dqs_en;
+input	[AFI_DATA_WIDTH-1:0] afi_wdata;
+input	[AFI_DQS_WIDTH-1:0] afi_wdata_valid;
+input	[AFI_DATA_MASK_WIDTH-1:0] afi_dm;
+output	[AFI_DATA_WIDTH-1:0] phy_ddio_dq;
+output	[AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
+output	[AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
+output	[AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
+
+wire	[AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
+wire	[AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
+wire	[AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
+wire	[AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
+
+generate
+genvar stage;
+if (NUM_WRITE_PATH_FLOP_STAGES == 0)
+begin
+	assign phy_ddio_dq_pre_shift = afi_wdata;
+	assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
+	assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
+        assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
+end
+else
+begin
+        reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
+        reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        
+        // phy_ddio_wrdata_mask is tied low during calibration
+        // the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
+        // sclr pin is very slow and causes timing failures
+        (* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
+        
+        for (stage = 0; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
+        begin : stage_gen
+        	always @(posedge pll_afi_clk)
+        	begin
+        		afi_wdata_r[stage]       <= (stage == 0) ? afi_wdata       : afi_wdata_r[stage-1];
+        		afi_wdata_valid_r[stage] <= (stage == 0) ? afi_wdata_valid : afi_wdata_valid_r[stage-1];
+        		afi_dm_r[stage]          <= (stage == 0) ? afi_dm          : afi_dm_r[stage-1];
+        		afi_dqs_en_r[stage]      <= (stage == 0) ? afi_dqs_en      : afi_dqs_en_r[stage-1];
+        	end
+        end
+        
+        assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+        assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
+end
+endgenerate
+
+generate
+genvar i, t;
+for (i=0; i<MEM_WRITE_DQS_WIDTH; i=i+1)
+begin: bs_wr_grp
+	
+	wire [1:0] shift_fr_cycle = 
+		(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 	2'b00 : 2'b01;
+											
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en_pre_shift;
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en;
+	
+	wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq_pre_shift;
+	wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq;
+	
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en_pre_shift;
+	wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en;
+
+	wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask_pre_shift;
+	wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask;
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter dq_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_dq_pre_shift),
+		.dataout (grp_dq)	
+	);
+	defparam dq_shifter.DATA_WIDTH = (DQ_GROUP_WIDTH * 2);
+	
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter wrdata_mask_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_wrdata_mask_pre_shift),
+		.dataout (grp_wrdata_mask)
+	);
+	defparam wrdata_mask_shifter.DATA_WIDTH = (DM_GROUP_WIDTH * 2);
+	
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter wrdata_en_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_wrdata_en_pre_shift),
+		.dataout (grp_wrdata_en)
+	);
+	defparam wrdata_en_shifter.DATA_WIDTH = 1;
+
+	q_sys_mem_if_ddr3_emif_0_p0_fr_cycle_shifter dqs_en_shifter(
+		.clk (pll_afi_clk),
+		.shift_by (shift_fr_cycle),
+		.reset_n (1'b1),
+		.datain (grp_dqs_en_pre_shift),
+		.dataout (grp_dqs_en)
+	);
+	defparam dqs_en_shifter.DATA_WIDTH = 1;
+
+	for (t=0; t<RATE_MULT*2; t=t+1)
+	begin: extract_ddr_grp
+		wire [DQ_GROUP_WIDTH-1:0] dq_t_pre_shift = phy_ddio_dq_pre_shift[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t];
+		assign grp_dq_pre_shift[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH] = dq_t_pre_shift;
+		
+		wire [DQ_GROUP_WIDTH-1:0] dq_t = grp_dq[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH];
+		assign phy_ddio_dq[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t] = dq_t;
+
+		wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t_pre_shift = phy_ddio_wrdata_mask_pre_shift[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t];
+		assign grp_wrdata_mask_pre_shift[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH] = wrdata_mask_t_pre_shift;
+		
+		wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t = grp_wrdata_mask[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH];
+		assign phy_ddio_wrdata_mask[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t] = wrdata_mask_t;		
+	end
+	
+	for (t=0; t<RATE_MULT; t=t+1)
+	begin: extract_sdr_grp
+		assign grp_dqs_en_pre_shift[t] = phy_ddio_dqs_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
+		assign phy_ddio_dqs_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_dqs_en[t];
+		
+		assign grp_wrdata_en_pre_shift[t] = phy_ddio_wrdata_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
+		assign phy_ddio_wrdata_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_wrdata_en[t];
+		
+	end
+end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
new file mode 100644
index 0000000..76daeb0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_pll0.sv
@@ -0,0 +1,223 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******************************************************************************************************************************** 
+// This file instantiates the PLL.
+// ******************************************************************************************************************************** 
+
+`timescale 1 ps / 1 ps
+
+(* altera_attribute = "-name IP_TOOL_NAME common; -name IP_TOOL_VERSION 18.0; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
+
+module q_sys_mem_if_ddr3_emif_0_pll0 (
+	global_reset_n,
+	pll_ref_clk,
+	pll_locked,
+	
+	afi_clk,
+	afi_half_clk,
+	pll_mem_clk,
+	pll_write_clk,
+	pll_capture0_clk,
+	pll_capture1_clk,
+	
+	scanclk,
+	phasecounterselect,
+	phasestep,
+	phaseupdown,
+	phasedone
+);
+
+// ******************************************************************************************************************************** 
+// BEGIN PARAMETER SECTION
+// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver. 
+parameter DEVICE_FAMILY = "MAX 10";
+
+// Clock settings
+parameter REF_CLK_PERIOD_PS = 20000;
+
+parameter PLL_AFI_CLK_DIV           = 1;
+parameter PLL_MEM_CLK_DIV           = 1;
+parameter PLL_WRITE_CLK_DIV         = 1;
+parameter PLL_CAP0_CLK_DIV          = 1;
+parameter PLL_CAP1_CLK_DIV          = 1;
+
+parameter PLL_AFI_CLK_MULT          = 3;
+parameter PLL_MEM_CLK_MULT          = 6;
+parameter PLL_WRITE_CLK_MULT        = 6;
+parameter PLL_CAP0_CLK_MULT         = 6;
+parameter PLL_CAP1_CLK_MULT         = 6;
+
+parameter PLL_AFI_CLK_PHASE_PS      = "0";
+parameter PLL_MEM_CLK_PHASE_PS      = "0";
+parameter PLL_WRITE_CLK_PHASE_PS    = "2500";
+parameter PLL_CAP0_CLK_PHASE_PS     = "0";
+parameter PLL_CAP1_CLK_PHASE_PS     = "2500";
+
+// END PARAMETER SECTION
+// ******************************************************************************************************************************** 
+
+// ******************************************************************************************************************************** 
+// BEGIN PORT SECTION
+
+input   global_reset_n;		// Resets (active-low) the whole system (all PHY logic + PLL)
+input	pll_ref_clk;		// PLL reference clock
+output	pll_locked;    // When 0, PLL is out of lock
+
+// When the PHY is selected to be a PLL/DLL MASTER, the PLL and DLL are instantied on this top level
+output  afi_clk;		// See pll_memphy instantiation below for detailed description of each clock
+output  afi_half_clk; 
+output	pll_mem_clk;
+output	pll_write_clk;
+output	pll_capture0_clk;
+output	pll_capture1_clk;
+
+input	[2:0] phasecounterselect;
+input	phasestep;
+input	phaseupdown;
+output	phasedone;
+input	scanclk;
+
+assign afi_half_clk = 1'b0;
+
+// END PORT SECTION
+// ******************************************************************************************************************************** 
+
+    wire [4:0] sub_wire;
+	wire  afi_clk         = sub_wire[4];
+	wire  pll_mem_clk         = sub_wire[0];
+	wire  pll_write_clk       = sub_wire[1];
+	wire  pll_capture0_clk    = sub_wire[2];
+	wire  pll_capture1_clk    = sub_wire[3];
+
+	altpll	upll_memphy (
+				.areset (~global_reset_n),
+				.inclk ({1'h0, pll_ref_clk}),
+				.phasecounterselect (phasecounterselect),
+				.phasestep (phasestep),
+				.scanclk (scanclk),
+				.phaseupdown (phaseupdown),
+				.clk (sub_wire),
+				.locked (pll_locked),
+				.phasedone (phasedone),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		upll_memphy.bandwidth_type = "AUTO",
+		
+		upll_memphy.clk4_divide_by = PLL_AFI_CLK_DIV,
+		upll_memphy.clk4_duty_cycle = 50,
+		upll_memphy.clk4_multiply_by = PLL_AFI_CLK_MULT,
+		upll_memphy.clk4_phase_shift = PLL_AFI_CLK_PHASE_PS,
+		
+		upll_memphy.clk0_divide_by = PLL_MEM_CLK_DIV,
+		upll_memphy.clk0_duty_cycle = 50,
+		upll_memphy.clk0_multiply_by = PLL_MEM_CLK_MULT,
+		upll_memphy.clk0_phase_shift = PLL_MEM_CLK_PHASE_PS,
+		
+		upll_memphy.clk1_divide_by = PLL_WRITE_CLK_DIV,
+		upll_memphy.clk1_duty_cycle = 50,
+		upll_memphy.clk1_multiply_by = PLL_WRITE_CLK_MULT,
+		upll_memphy.clk1_phase_shift = PLL_WRITE_CLK_PHASE_PS,
+		
+		upll_memphy.clk2_divide_by = PLL_CAP0_CLK_DIV,
+		upll_memphy.clk2_duty_cycle = 50,
+		upll_memphy.clk2_multiply_by = PLL_CAP0_CLK_MULT,
+		upll_memphy.clk2_phase_shift = PLL_CAP0_CLK_PHASE_PS,
+		
+		upll_memphy.clk3_divide_by = PLL_CAP1_CLK_DIV,
+		upll_memphy.clk3_duty_cycle = 50,
+		upll_memphy.clk3_multiply_by = PLL_CAP1_CLK_MULT,
+		upll_memphy.clk3_phase_shift = PLL_CAP1_CLK_PHASE_PS,
+		
+		upll_memphy.compensate_clock = "CLK1",
+		upll_memphy.inclk0_input_frequency = REF_CLK_PERIOD_PS,
+		upll_memphy.intended_device_family = DEVICE_FAMILY,
+		upll_memphy.lpm_type = "altpll",
+		upll_memphy.operation_mode = "NORMAL",
+		upll_memphy.pll_type = "AUTO",
+		upll_memphy.port_activeclock = "PORT_UNUSED",
+		upll_memphy.port_areset = "PORT_USED",
+		upll_memphy.port_clkbad0 = "PORT_UNUSED",
+		upll_memphy.port_clkbad1 = "PORT_UNUSED",
+		upll_memphy.port_clkloss = "PORT_UNUSED",
+		upll_memphy.port_clkswitch = "PORT_UNUSED",
+		upll_memphy.port_configupdate = "PORT_UNUSED",
+		upll_memphy.port_fbin = "PORT_UNUSED",
+		upll_memphy.port_inclk0 = "PORT_USED",
+		upll_memphy.port_inclk1 = "PORT_UNUSED",
+		upll_memphy.port_locked = "PORT_USED",
+		upll_memphy.port_pfdena = "PORT_UNUSED",
+		upll_memphy.port_phasecounterselect = "PORT_USED",
+		upll_memphy.port_phasedone = "PORT_USED",
+		upll_memphy.port_phasestep = "PORT_USED",
+		upll_memphy.port_phaseupdown = "PORT_USED",
+		upll_memphy.port_pllena = "PORT_UNUSED",
+		upll_memphy.port_scanaclr = "PORT_UNUSED",
+		upll_memphy.port_scanclk = "PORT_USED",
+		upll_memphy.port_scanclkena = "PORT_UNUSED",
+		upll_memphy.port_scandata = "PORT_UNUSED",
+		upll_memphy.port_scandataout = "PORT_UNUSED",
+		upll_memphy.port_scandone = "PORT_UNUSED",
+		upll_memphy.port_scanread = "PORT_UNUSED",
+		upll_memphy.port_scanwrite = "PORT_UNUSED",
+		upll_memphy.port_clk0 = "PORT_USED",
+		upll_memphy.port_clk1 = "PORT_USED",
+		upll_memphy.port_clk2 = "PORT_USED",
+		upll_memphy.port_clk3 = "PORT_USED",
+		upll_memphy.port_clk4 = "PORT_USED",
+		upll_memphy.port_clk5 = "PORT_UNUSED",
+		upll_memphy.port_clkena0 = "PORT_UNUSED",
+		upll_memphy.port_clkena1 = "PORT_UNUSED",
+		upll_memphy.port_clkena2 = "PORT_UNUSED",
+		upll_memphy.port_clkena3 = "PORT_UNUSED",
+		upll_memphy.port_clkena4 = "PORT_UNUSED",
+		upll_memphy.port_clkena5 = "PORT_UNUSED",
+		upll_memphy.port_extclk0 = "PORT_UNUSED",
+		upll_memphy.port_extclk1 = "PORT_UNUSED",
+		upll_memphy.port_extclk2 = "PORT_UNUSED",
+		upll_memphy.port_extclk3 = "PORT_UNUSED",
+		upll_memphy.self_reset_on_loss_lock = "OFF",
+		upll_memphy.vco_frequency_control = "MANUAL_PHASE",
+		upll_memphy.vco_phase_shift_step = 104,
+		upll_memphy.width_clock = 5,
+		upll_memphy.width_phasecounterselect = 3;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
new file mode 100644
index 0000000..792c334
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0.v
@@ -0,0 +1,289 @@
+// q_sys_mem_if_ddr3_emif_0_s0.v
+
+// This file was auto-generated from qsys_sequencer_110_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mem_if_ddr3_emif_0_s0 (
+		input  wire        avl_clk,                     //          avl_clk.clk
+		input  wire        avl_reset_n,                 //    sequencer_rst.reset
+		output wire        pd_reset_n,                  //   phase_detector.pd_reset_n
+		output wire        pd_ack,                      //                 .pd_ack
+		input  wire        pd_up,                       //                 .pd_up
+		input  wire        pd_down,                     //                 .pd_down
+		output wire [2:0]  phasecounterselect,          //     pll_reconfig.phasecounterselect
+		output wire        phasestep,                   //                 .phasestep
+		output wire        phaseupdown,                 //                 .phaseupdown
+		output wire        scanclk,                     //                 .scanclk
+		input  wire        phasedone,                   //                 .phasedone
+		input  wire        phy_clk,                     //              phy.phy_clk
+		input  wire        phy_reset_n,                 //                 .phy_reset_n
+		output wire [4:0]  phy_read_latency_counter,    //                 .phy_read_latency_counter
+		output wire [5:0]  phy_afi_wlat,                //                 .phy_afi_wlat
+		output wire [5:0]  phy_afi_rlat,                //                 .phy_afi_rlat
+		output wire [0:0]  phy_read_increment_vfifo_fr, //                 .phy_read_increment_vfifo_fr
+		output wire [0:0]  phy_read_increment_vfifo_hr, //                 .phy_read_increment_vfifo_hr
+		output wire [0:0]  phy_read_increment_vfifo_qr, //                 .phy_read_increment_vfifo_qr
+		output wire        phy_reset_mem_stable,        //                 .phy_reset_mem_stable
+		output wire        phy_cal_success,             //                 .phy_cal_success
+		output wire        phy_cal_fail,                //                 .phy_cal_fail
+		output wire [31:0] phy_cal_debug_info,          //                 .phy_cal_debug_info
+		output wire [0:0]  phy_read_fifo_reset,         //                 .phy_read_fifo_reset
+		output wire [0:0]  phy_vfifo_rd_en_override,    //                 .phy_vfifo_rd_en_override
+		input  wire [31:0] phy_read_fifo_q,             //                 .phy_read_fifo_q
+		output wire [1:0]  phy_write_fr_cycle_shifts,   //                 .phy_write_fr_cycle_shifts
+		output wire        phy_mux_sel,                 //          mux_sel.mux_sel
+		input  wire [7:0]  calib_skip_steps,            //            calib.calib_skip_steps
+		input  wire        afi_clk,                     //          afi_clk.clk
+		input  wire        afi_reset_n,                 //        afi_reset.reset_n
+		output wire [27:0] afi_addr,                    //              afi.afi_addr
+		output wire [5:0]  afi_ba,                      //                 .afi_ba
+		output wire [1:0]  afi_cs_n,                    //                 .afi_cs_n
+		output wire [1:0]  afi_cke,                     //                 .afi_cke
+		output wire [1:0]  afi_odt,                     //                 .afi_odt
+		output wire [1:0]  afi_ras_n,                   //                 .afi_ras_n
+		output wire [1:0]  afi_cas_n,                   //                 .afi_cas_n
+		output wire [1:0]  afi_we_n,                    //                 .afi_we_n
+		output wire [1:0]  afi_dqs_burst,               //                 .afi_dqs_burst
+		output wire [1:0]  afi_rst_n,                   //                 .afi_rst_n
+		output wire [31:0] afi_wdata,                   //                 .afi_wdata
+		output wire [1:0]  afi_wdata_valid,             //                 .afi_wdata_valid
+		output wire [3:0]  afi_dm,                      //                 .afi_dm
+		output wire [1:0]  afi_rdata_en,                //                 .afi_rdata_en
+		output wire [1:0]  afi_rdata_en_full,           //                 .afi_rdata_en_full
+		input  wire [31:0] afi_rdata,                   //                 .afi_rdata
+		input  wire [1:0]  afi_rdata_valid,             //                 .afi_rdata_valid
+		input  wire        afi_init_req,                // afi_init_cal_req.afi_init_req
+		input  wire        afi_cal_req                  //                 .afi_cal_req
+	);
+
+	wire         sequencer_rst_reset_out_reset;                            // sequencer_rst:reset_out -> [cpu_inst:reset_n, mm_interconnect_0:cpu_inst_reset_n_reset_bridge_in_reset_reset, mm_interconnect_0:sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_pll_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst:avl_reset_n]
+	wire  [31:0] cpu_inst_data_master_readdata;                            // mm_interconnect_0:cpu_inst_data_master_readdata -> cpu_inst:readdata
+	wire         cpu_inst_data_master_waitrequest;                         // mm_interconnect_0:cpu_inst_data_master_waitrequest -> cpu_inst:waitrequest
+	wire  [19:0] cpu_inst_data_master_address;                             // cpu_inst:address -> mm_interconnect_0:cpu_inst_data_master_address
+	wire         cpu_inst_data_master_read;                                // cpu_inst:read -> mm_interconnect_0:cpu_inst_data_master_read
+	wire         cpu_inst_data_master_write;                               // cpu_inst:write -> mm_interconnect_0:cpu_inst_data_master_write
+	wire  [31:0] cpu_inst_data_master_writedata;                           // cpu_inst:writedata -> mm_interconnect_0:cpu_inst_data_master_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata;    // sequencer_phy_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_address;     // mm_interconnect_0:sequencer_phy_mgr_inst_avl_address -> sequencer_phy_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_read;        // mm_interconnect_0:sequencer_phy_mgr_inst_avl_read -> sequencer_phy_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_phy_mgr_inst_avl_write;       // mm_interconnect_0:sequencer_phy_mgr_inst_avl_write -> sequencer_phy_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata;   // mm_interconnect_0:sequencer_phy_mgr_inst_avl_writedata -> sequencer_phy_mgr_inst:avl_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata;     // sequencer_rw_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest;  // sequencer_rw_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_address;      // mm_interconnect_0:sequencer_rw_mgr_inst_avl_address -> sequencer_rw_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_read;         // mm_interconnect_0:sequencer_rw_mgr_inst_avl_read -> sequencer_rw_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_rw_mgr_inst_avl_write;        // mm_interconnect_0:sequencer_rw_mgr_inst_avl_write -> sequencer_rw_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata;    // mm_interconnect_0:sequencer_rw_mgr_inst_avl_writedata -> sequencer_rw_mgr_inst:avl_writedata
+	wire  [31:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata;    // sequencer_pll_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_readdata
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest; // sequencer_pll_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_waitrequest
+	wire  [12:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_address;     // mm_interconnect_0:sequencer_pll_mgr_inst_avl_address -> sequencer_pll_mgr_inst:avl_address
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_read;        // mm_interconnect_0:sequencer_pll_mgr_inst_avl_read -> sequencer_pll_mgr_inst:avl_read
+	wire         mm_interconnect_0_sequencer_pll_mgr_inst_avl_write;       // mm_interconnect_0:sequencer_pll_mgr_inst_avl_write -> sequencer_pll_mgr_inst:avl_write
+	wire  [31:0] mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata;   // mm_interconnect_0:sequencer_pll_mgr_inst_avl_writedata -> sequencer_pll_mgr_inst:avl_writedata
+
+	altera_mem_if_sequencer_rst #(
+		.DEPTH            (10),
+		.CLKEN_LAGS_RESET (0)
+	) sequencer_rst (
+		.clk       (avl_clk),                       //       clk.clk
+		.rst       (avl_reset_n),                   //       rst.reset
+		.reset_out (sequencer_rst_reset_out_reset), // reset_out.reset
+		.clken_out ()                               // clken_out.clken
+	);
+
+	sequencer_m10 #(
+		.AVL_DATA_WIDTH       (32),
+		.AVL_ADDR_WIDTH       (20),
+		.READ_VALID_FIFO_SIZE (16),
+		.HPS_PROTOCOL         ("DDR3"),
+		.PHY_MGR_BASE         (294912),
+		.RW_MGR_BASE          (327680),
+		.PLL_MGR_BASE         (360448),
+		.MEM_DQ_WIDTH         (8)
+	) cpu_inst (
+		.clk         (avl_clk),                          //            clk.clk
+		.reset_n     (~sequencer_rst_reset_out_reset),   //        reset_n.reset_n
+		.address     (cpu_inst_data_master_address),     //    data_master.address
+		.write       (cpu_inst_data_master_write),       //               .write
+		.writedata   (cpu_inst_data_master_writedata),   //               .writedata
+		.read        (cpu_inst_data_master_read),        //               .read
+		.readdata    (cpu_inst_data_master_readdata),    //               .readdata
+		.waitrequest (cpu_inst_data_master_waitrequest), //               .waitrequest
+		.pd_reset_n  (pd_reset_n),                       // phase_detector.pd_reset_n
+		.pd_ack      (pd_ack),                           //               .pd_ack
+		.pd_up       (pd_up),                            //               .pd_up
+		.pd_down     (pd_down)                           //               .pd_down
+	);
+
+	sequencer_pll_mgr #(
+		.AVL_DATA_WIDTH (32),
+		.AVL_ADDR_WIDTH (13)
+	) sequencer_pll_mgr_inst (
+		.avl_clk            (avl_clk),                                                  //          avl_clk.clk
+		.avl_reset_n        (~sequencer_rst_reset_out_reset),                           //        avl_reset.reset_n
+		.avl_address        (mm_interconnect_0_sequencer_pll_mgr_inst_avl_address),     //              avl.address
+		.avl_write          (mm_interconnect_0_sequencer_pll_mgr_inst_avl_write),       //                 .write
+		.avl_writedata      (mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata),   //                 .writedata
+		.avl_read           (mm_interconnect_0_sequencer_pll_mgr_inst_avl_read),        //                 .read
+		.avl_readdata       (mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata),    //                 .readdata
+		.avl_waitrequest    (mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest), //                 .waitrequest
+		.phasecounterselect (phasecounterselect),                                       //     pll_reconfig.phasecounterselect
+		.phasestep          (phasestep),                                                //                 .phasestep
+		.phaseupdown        (phaseupdown),                                              //                 .phaseupdown
+		.scanclk            (scanclk),                                                  //                 .scanclk
+		.phasedone          (phasedone),                                                //                 .phasedone
+		.afi_init_req       (afi_init_req),                                             // afi_init_cal_req.afi_init_req
+		.afi_cal_req        (afi_cal_req)                                               //                 .afi_cal_req
+	);
+
+	sequencer_phy_mgr #(
+		.AVL_DATA_WIDTH                    (32),
+		.AVL_ADDR_WIDTH                    (13),
+		.MAX_LATENCY_COUNT_WIDTH           (5),
+		.MEM_IF_READ_DQS_WIDTH             (1),
+		.MEM_IF_WRITE_DQS_WIDTH            (1),
+		.AFI_DQ_WIDTH                      (32),
+		.AFI_DEBUG_INFO_WIDTH              (32),
+		.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
+		.AFI_MAX_READ_LATENCY_COUNT_WIDTH  (6),
+		.CALIB_VFIFO_OFFSET                (12),
+		.CALIB_LFIFO_OFFSET                (4),
+		.CALIB_REG_WIDTH                   (8),
+		.READ_VALID_FIFO_SIZE              (16),
+		.MEM_T_WL                          (5),
+		.MEM_T_RL                          (5),
+		.CTL_REGDIMM_ENABLED               (0),
+		.NUM_WRITE_FR_CYCLE_SHIFTS         (1),
+		.VFIFO_CONTROL_WIDTH_PER_DQS       (1),
+		.DEVICE_FAMILY                     ("MAX10")
+	) sequencer_phy_mgr_inst (
+		.avl_clk                     (avl_clk),                                                  //   avl_clk.clk
+		.avl_reset_n                 (~sequencer_rst_reset_out_reset),                           // avl_reset.reset_n
+		.avl_address                 (mm_interconnect_0_sequencer_phy_mgr_inst_avl_address),     //       avl.address
+		.avl_write                   (mm_interconnect_0_sequencer_phy_mgr_inst_avl_write),       //          .write
+		.avl_writedata               (mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata),   //          .writedata
+		.avl_read                    (mm_interconnect_0_sequencer_phy_mgr_inst_avl_read),        //          .read
+		.avl_readdata                (mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata),    //          .readdata
+		.avl_waitrequest             (mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest), //          .waitrequest
+		.phy_clk                     (phy_clk),                                                  //       phy.phy_clk
+		.phy_reset_n                 (phy_reset_n),                                              //          .phy_reset_n
+		.phy_read_latency_counter    (phy_read_latency_counter),                                 //          .phy_read_latency_counter
+		.phy_afi_wlat                (phy_afi_wlat),                                             //          .phy_afi_wlat
+		.phy_afi_rlat                (phy_afi_rlat),                                             //          .phy_afi_rlat
+		.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr),                              //          .phy_read_increment_vfifo_fr
+		.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr),                              //          .phy_read_increment_vfifo_hr
+		.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr),                              //          .phy_read_increment_vfifo_qr
+		.phy_reset_mem_stable        (phy_reset_mem_stable),                                     //          .phy_reset_mem_stable
+		.phy_cal_success             (phy_cal_success),                                          //          .phy_cal_success
+		.phy_cal_fail                (phy_cal_fail),                                             //          .phy_cal_fail
+		.phy_cal_debug_info          (phy_cal_debug_info),                                       //          .phy_cal_debug_info
+		.phy_read_fifo_reset         (phy_read_fifo_reset),                                      //          .phy_read_fifo_reset
+		.phy_vfifo_rd_en_override    (phy_vfifo_rd_en_override),                                 //          .phy_vfifo_rd_en_override
+		.phy_read_fifo_q             (phy_read_fifo_q),                                          //          .phy_read_fifo_q
+		.phy_write_fr_cycle_shifts   (phy_write_fr_cycle_shifts),                                //          .phy_write_fr_cycle_shifts
+		.calib_skip_steps            (calib_skip_steps),                                         //     calib.calib_skip_steps
+		.phy_mux_sel                 (phy_mux_sel)                                               //   mux_sel.mux_sel
+	);
+
+	rw_manager_ddr3 #(
+		.RATE                                 ("Half"),
+		.AVL_DATA_WIDTH                       (32),
+		.AVL_ADDR_WIDTH                       (13),
+		.MEM_ADDRESS_WIDTH                    (14),
+		.MEM_CONTROL_WIDTH                    (1),
+		.MEM_DQ_WIDTH                         (8),
+		.MEM_DM_WIDTH                         (1),
+		.MEM_NUMBER_OF_RANKS                  (1),
+		.MEM_CLK_EN_WIDTH                     (1),
+		.MEM_BANK_WIDTH                       (3),
+		.MEM_ODT_WIDTH                        (1),
+		.MEM_CHIP_SELECT_WIDTH                (1),
+		.MEM_READ_DQS_WIDTH                   (1),
+		.MEM_WRITE_DQS_WIDTH                  (1),
+		.AFI_RATIO                            (2),
+		.AC_BUS_WIDTH                         (27),
+		.HCX_COMPAT_MODE                      (0),
+		.DEVICE_FAMILY                        ("MAX10"),
+		.AC_ROM_INIT_FILE_NAME                ("q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex"),
+		.INST_ROM_INIT_FILE_NAME              ("q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex"),
+		.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT (0),
+		.DEBUG_WRITE_TO_READ_RATIO            (1),
+		.MAX_DI_BUFFER_WORDS_LOG_2            (2),
+		.AP_MODE_EN                           (2'b00),
+		.AVL_CLK_PS                           (6667),
+		.AFI_CLK_PS                           (6667),
+		.ENABLE_NON_DES_CAL                   (0),
+		.TREFI                                (35100),
+		.REFRESH_INTERVAL                     (15000),
+		.TRFC                                 (350)
+	) sequencer_rw_mgr_inst (
+		.avl_clk           (avl_clk),                                                 //   avl_clk.clk
+		.avl_reset_n       (~sequencer_rst_reset_out_reset),                          // avl_reset.reset_n
+		.avl_address       (mm_interconnect_0_sequencer_rw_mgr_inst_avl_address),     //       avl.address
+		.avl_write         (mm_interconnect_0_sequencer_rw_mgr_inst_avl_write),       //          .write
+		.avl_writedata     (mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata),   //          .writedata
+		.avl_read          (mm_interconnect_0_sequencer_rw_mgr_inst_avl_read),        //          .read
+		.avl_readdata      (mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata),    //          .readdata
+		.avl_waitrequest   (mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest), //          .waitrequest
+		.afi_clk           (afi_clk),                                                 //   afi_clk.clk
+		.afi_reset_n       (afi_reset_n),                                             // afi_reset.reset_n
+		.afi_addr          (afi_addr),                                                //       afi.afi_addr
+		.afi_ba            (afi_ba),                                                  //          .afi_ba
+		.afi_cs_n          (afi_cs_n),                                                //          .afi_cs_n
+		.afi_cke           (afi_cke),                                                 //          .afi_cke
+		.afi_odt           (afi_odt),                                                 //          .afi_odt
+		.afi_ras_n         (afi_ras_n),                                               //          .afi_ras_n
+		.afi_cas_n         (afi_cas_n),                                               //          .afi_cas_n
+		.afi_we_n          (afi_we_n),                                                //          .afi_we_n
+		.afi_dqs_burst     (afi_dqs_burst),                                           //          .afi_dqs_burst
+		.afi_rst_n         (afi_rst_n),                                               //          .afi_rst_n
+		.afi_wdata         (afi_wdata),                                               //          .afi_wdata
+		.afi_wdata_valid   (afi_wdata_valid),                                         //          .afi_wdata_valid
+		.afi_dm            (afi_dm),                                                  //          .afi_dm
+		.afi_rdata_en      (afi_rdata_en),                                            //          .afi_rdata_en
+		.afi_rdata_en_full (afi_rdata_en_full),                                       //          .afi_rdata_en_full
+		.afi_rdata         (afi_rdata),                                               //          .afi_rdata
+		.afi_rdata_valid   (afi_rdata_valid),                                         //          .afi_rdata_valid
+		.csr_clk           (),                                                        //       csr.csr_clk
+		.csr_ena           (),                                                        //          .csr_ena
+		.csr_dout_phy      (),                                                        //          .csr_dout_phy
+		.csr_dout          (),                                                        //          .csr_dout
+		.afi_rrank         (),                                                        // (terminated)
+		.afi_wrank         ()                                                         // (terminated)
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0 mm_interconnect_0 (
+		.avl_clk_out_clk_clk                                          (avl_clk),                                                  //                                        avl_clk_out_clk.clk
+		.cpu_inst_reset_n_reset_bridge_in_reset_reset                 (sequencer_rst_reset_out_reset),                            //                 cpu_inst_reset_n_reset_bridge_in_reset.reset
+		.sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset),                            // sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
+		.cpu_inst_data_master_address                                 (cpu_inst_data_master_address),                             //                                   cpu_inst_data_master.address
+		.cpu_inst_data_master_waitrequest                             (cpu_inst_data_master_waitrequest),                         //                                                       .waitrequest
+		.cpu_inst_data_master_read                                    (cpu_inst_data_master_read),                                //                                                       .read
+		.cpu_inst_data_master_readdata                                (cpu_inst_data_master_readdata),                            //                                                       .readdata
+		.cpu_inst_data_master_write                                   (cpu_inst_data_master_write),                               //                                                       .write
+		.cpu_inst_data_master_writedata                               (cpu_inst_data_master_writedata),                           //                                                       .writedata
+		.sequencer_phy_mgr_inst_avl_address                           (mm_interconnect_0_sequencer_phy_mgr_inst_avl_address),     //                             sequencer_phy_mgr_inst_avl.address
+		.sequencer_phy_mgr_inst_avl_write                             (mm_interconnect_0_sequencer_phy_mgr_inst_avl_write),       //                                                       .write
+		.sequencer_phy_mgr_inst_avl_read                              (mm_interconnect_0_sequencer_phy_mgr_inst_avl_read),        //                                                       .read
+		.sequencer_phy_mgr_inst_avl_readdata                          (mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata),    //                                                       .readdata
+		.sequencer_phy_mgr_inst_avl_writedata                         (mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata),   //                                                       .writedata
+		.sequencer_phy_mgr_inst_avl_waitrequest                       (mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest), //                                                       .waitrequest
+		.sequencer_pll_mgr_inst_avl_address                           (mm_interconnect_0_sequencer_pll_mgr_inst_avl_address),     //                             sequencer_pll_mgr_inst_avl.address
+		.sequencer_pll_mgr_inst_avl_write                             (mm_interconnect_0_sequencer_pll_mgr_inst_avl_write),       //                                                       .write
+		.sequencer_pll_mgr_inst_avl_read                              (mm_interconnect_0_sequencer_pll_mgr_inst_avl_read),        //                                                       .read
+		.sequencer_pll_mgr_inst_avl_readdata                          (mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata),    //                                                       .readdata
+		.sequencer_pll_mgr_inst_avl_writedata                         (mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata),   //                                                       .writedata
+		.sequencer_pll_mgr_inst_avl_waitrequest                       (mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest), //                                                       .waitrequest
+		.sequencer_rw_mgr_inst_avl_address                            (mm_interconnect_0_sequencer_rw_mgr_inst_avl_address),      //                              sequencer_rw_mgr_inst_avl.address
+		.sequencer_rw_mgr_inst_avl_write                              (mm_interconnect_0_sequencer_rw_mgr_inst_avl_write),        //                                                       .write
+		.sequencer_rw_mgr_inst_avl_read                               (mm_interconnect_0_sequencer_rw_mgr_inst_avl_read),         //                                                       .read
+		.sequencer_rw_mgr_inst_avl_readdata                           (mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata),     //                                                       .readdata
+		.sequencer_rw_mgr_inst_avl_writedata                          (mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata),    //                                                       .writedata
+		.sequencer_rw_mgr_inst_avl_waitrequest                        (mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest)   //                                                       .waitrequest
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
new file mode 100644
index 0000000..19f0a5c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_AC_ROM.hex
@@ -0,0 +1,41 @@
+:04000000180E0000D6
+:04000100180F0000D4
+:040002000C010211DA
+:040003000C010310D9
+:040004000C012000CB
+:040005000C014000AA
+:040006000C01600089
+:040007000C070400DE
+:040008000C010209DC
+:040009000C0102885C
+:04000A000C014000A5
+:04000B000C012000C4
+:04000C000C01600083
+:04000D001C0F0000C4
+:04000E001E0F0000C1
+:04000F001C0F0000C2
+:040010000C0D0000D3
+:040011000C0D600072
+:040012000C050400D5
+:040013000C090000D4
+:040014000F330000A6
+:040015000F33600045
+:040016000F3300089C
+:040017000F3360083B
+:040018001E2F000097
+:040019001F3F000085
+:04001A001E0F0000B5
+:04001B000E030000D0
+:04001C000E230000AF
+:04001D000CCB000008
+:04001E000CCB6000A7
+:04001F000CCB0008FE
+:040020000CCB60089D
+:040021001CCF0000F0
+:040022000C0B0008BB
+:040023000C0F0000BE
+:0400240000000000D8
+:0400250000000000D7
+:0400260000000000D6
+:0400270000000000D5
+:00000001FF
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
new file mode 100644
index 0000000..3eb8c97
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_inst_ROM.hex
@@ -0,0 +1,129 @@
+:03000000080000F5
+:0300010000078075
+:030002000806806D
+:0300030000018079
+:030004000806806B
+:03000500000200F6
+:0300060008068069
+:0300070000028074
+:0300080008068067
+:03000900000300F1
+:03000A0008068065
+:03000B000003806F
+:03000C0008068063
+:03000D00000100EF
+:03000E0008068061
+:03000F00000800E6
+:03001000008680E7
+:0300110000088064
+:0300120000A680C5
+:030013000806805C
+:03001400000900E0
+:030015000806805A
+:030016000009805E
+:03001700008680E0
+:0300180008068057
+:03001900000B6871
+:03001A0000CCE82F
+:03001B00000AE8F0
+:03001C00008CE86D
+:03001D00000B884D
+:03001E0000EC886B
+:03001F00000A08CC
+:0300200000AC88A9
+:030021000806804E
+:0300220000CE000D
+:0300230000CD808D
+:0300240000E700F2
+:03002500000C00CC
+:03002600020CE0E9
+:03002700020CE0E8
+:03002800000D00C8
+:030029000006804E
+:03002A000006804D
+:03002B00060E803E
+:03002C000610803B
+:03002D0000A680AA
+:03002E00008680C9
+:03002F0008068040
+:0300300000CE00FF
+:0300310000CD807F
+:0300320000E700E4
+:03003300000C00BE
+:03003400030CE0DA
+:03003500030CE0D9
+:03003600000D00BA
+:0300370000068040
+:030038000006803F
+:03003900070E802F
+:03003A000710802C
+:03003B0000A6809C
+:03003C00008680BB
+:03003D0008068032
+:03003E0000115856
+:03003F000006D8E0
+:030040000806802F
+:03004100040E8822
+:030042000410881F
+:03004300040F683F
+:030044000410E8BD
+:0300450000A68092
+:03004600040FE8BC
+:030047000410E8BA
+:0300480004100899
+:0300490004108818
+:03004A00001100A2
+:03004B0000C6806C
+:03004C00008680AB
+:03004D0000E6804A
+:03004E0008068021
+:03004F00000000AE
+:03005000000000AD
+:0300510000A0000C
+:030052000080002B
+:03005300080000A2
+:0300540000008029
+:0300550000008028
+:0300560000008027
+:0300570000008026
+:0300580000A08085
+:03005900008080A4
+:03005A000800801B
+:03005B000086809C
+:03005C0000A6807B
+:03005D0008068012
+:03005E00040F0884
+:03005F0008068010
+:030060000000009D
+:030061000000009C
+:030062000000009B
+:030063000000009A
+:0300640000000099
+:0300650000000098
+:0300660000000097
+:0300670000000096
+:0300680000000095
+:0300690000000094
+:03006A0000000093
+:03006B0000000092
+:03006C0000000091
+:03006D0000000090
+:03006E000000008F
+:03006F000000008E
+:030070000000008D
+:030071000000008C
+:030072000000008B
+:030073000000008A
+:0300740000000089
+:0300750000000088
+:0300760000000087
+:0300770000000086
+:0300780000000085
+:0300790000000084
+:03007A0000000083
+:03007B0000000082
+:03007C0000000081
+:03007D0000000080
+:03007E000000007F
+:03007F000000007E
+:00000001FF
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
new file mode 100644
index 0000000..40292f3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
@@ -0,0 +1,1258 @@
+// q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0 (
+		input  wire        avl_clk_out_clk_clk,                                          //                                        avl_clk_out_clk.clk
+		input  wire        cpu_inst_reset_n_reset_bridge_in_reset_reset,                 //                 cpu_inst_reset_n_reset_bridge_in_reset.reset
+		input  wire        sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, // sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
+		input  wire [19:0] cpu_inst_data_master_address,                                 //                                   cpu_inst_data_master.address
+		output wire        cpu_inst_data_master_waitrequest,                             //                                                       .waitrequest
+		input  wire        cpu_inst_data_master_read,                                    //                                                       .read
+		output wire [31:0] cpu_inst_data_master_readdata,                                //                                                       .readdata
+		input  wire        cpu_inst_data_master_write,                                   //                                                       .write
+		input  wire [31:0] cpu_inst_data_master_writedata,                               //                                                       .writedata
+		output wire [12:0] sequencer_phy_mgr_inst_avl_address,                           //                             sequencer_phy_mgr_inst_avl.address
+		output wire        sequencer_phy_mgr_inst_avl_write,                             //                                                       .write
+		output wire        sequencer_phy_mgr_inst_avl_read,                              //                                                       .read
+		input  wire [31:0] sequencer_phy_mgr_inst_avl_readdata,                          //                                                       .readdata
+		output wire [31:0] sequencer_phy_mgr_inst_avl_writedata,                         //                                                       .writedata
+		input  wire        sequencer_phy_mgr_inst_avl_waitrequest,                       //                                                       .waitrequest
+		output wire [12:0] sequencer_pll_mgr_inst_avl_address,                           //                             sequencer_pll_mgr_inst_avl.address
+		output wire        sequencer_pll_mgr_inst_avl_write,                             //                                                       .write
+		output wire        sequencer_pll_mgr_inst_avl_read,                              //                                                       .read
+		input  wire [31:0] sequencer_pll_mgr_inst_avl_readdata,                          //                                                       .readdata
+		output wire [31:0] sequencer_pll_mgr_inst_avl_writedata,                         //                                                       .writedata
+		input  wire        sequencer_pll_mgr_inst_avl_waitrequest,                       //                                                       .waitrequest
+		output wire [12:0] sequencer_rw_mgr_inst_avl_address,                            //                              sequencer_rw_mgr_inst_avl.address
+		output wire        sequencer_rw_mgr_inst_avl_write,                              //                                                       .write
+		output wire        sequencer_rw_mgr_inst_avl_read,                               //                                                       .read
+		input  wire [31:0] sequencer_rw_mgr_inst_avl_readdata,                           //                                                       .readdata
+		output wire [31:0] sequencer_rw_mgr_inst_avl_writedata,                          //                                                       .writedata
+		input  wire        sequencer_rw_mgr_inst_avl_waitrequest                         //                                                       .waitrequest
+	);
+
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest;   // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
+	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata;      // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess;   // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
+	wire  [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address;       // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_read;          // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
+	wire   [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable;    // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_lock;          // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
+	wire         cpu_inst_data_master_translator_avalon_universal_master_0_write;         // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
+	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata;     // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
+	wire   [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount;    // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
+	wire         rsp_mux_src_valid;                                                       // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
+	wire  [91:0] rsp_mux_src_data;                                                        // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
+	wire         rsp_mux_src_ready;                                                       // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
+	wire   [2:0] rsp_mux_src_channel;                                                     // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
+	wire         rsp_mux_src_startofpacket;                                               // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
+	wire         rsp_mux_src_endofpacket;                                                 // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
+	wire  [31:0] sequencer_phy_mgr_inst_avl_agent_m0_readdata;                            // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_waitrequest;                         // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_debugaccess;                         // sequencer_phy_mgr_inst_avl_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_phy_mgr_inst_avl_agent_m0_address;                             // sequencer_phy_mgr_inst_avl_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_phy_mgr_inst_avl_agent_m0_byteenable;                          // sequencer_phy_mgr_inst_avl_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_read;                                // sequencer_phy_mgr_inst_avl_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid;                       // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_lock;                                // sequencer_phy_mgr_inst_avl_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_phy_mgr_inst_avl_agent_m0_writedata;                           // sequencer_phy_mgr_inst_avl_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_phy_mgr_inst_avl_agent_m0_write;                               // sequencer_phy_mgr_inst_avl_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_phy_mgr_inst_avl_agent_m0_burstcount;                          // sequencer_phy_mgr_inst_avl_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_valid;                        // sequencer_phy_mgr_inst_avl_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_phy_mgr_inst_avl_agent_rf_source_data;                         // sequencer_phy_mgr_inst_avl_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_ready;                        // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket;                // sequencer_phy_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket;                  // sequencer_phy_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid;                     // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data;                      // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready;                     // sequencer_phy_mgr_inst_avl_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;             // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;               // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_src_valid;                                                       // cmd_mux:src_valid -> sequencer_phy_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_src_data;                                                        // cmd_mux:src_data -> sequencer_phy_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_src_ready;                                                       // sequencer_phy_mgr_inst_avl_agent:cp_ready -> cmd_mux:src_ready
+	wire   [2:0] cmd_mux_src_channel;                                                     // cmd_mux:src_channel -> sequencer_phy_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_src_startofpacket;                                               // cmd_mux:src_startofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_src_endofpacket;                                                 // cmd_mux:src_endofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_endofpacket
+	wire  [31:0] sequencer_rw_mgr_inst_avl_agent_m0_readdata;                             // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_waitrequest;                          // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_debugaccess;                          // sequencer_rw_mgr_inst_avl_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_rw_mgr_inst_avl_agent_m0_address;                              // sequencer_rw_mgr_inst_avl_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_rw_mgr_inst_avl_agent_m0_byteenable;                           // sequencer_rw_mgr_inst_avl_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_read;                                 // sequencer_rw_mgr_inst_avl_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid;                        // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_lock;                                 // sequencer_rw_mgr_inst_avl_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_rw_mgr_inst_avl_agent_m0_writedata;                            // sequencer_rw_mgr_inst_avl_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_rw_mgr_inst_avl_agent_m0_write;                                // sequencer_rw_mgr_inst_avl_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_rw_mgr_inst_avl_agent_m0_burstcount;                           // sequencer_rw_mgr_inst_avl_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_valid;                         // sequencer_rw_mgr_inst_avl_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_rw_mgr_inst_avl_agent_rf_source_data;                          // sequencer_rw_mgr_inst_avl_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_ready;                         // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket;                 // sequencer_rw_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket;                   // sequencer_rw_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid;                      // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data;                       // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready;                      // sequencer_rw_mgr_inst_avl_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;              // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;                // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_001_src_valid;                                                   // cmd_mux_001:src_valid -> sequencer_rw_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_001_src_data;                                                    // cmd_mux_001:src_data -> sequencer_rw_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_001_src_ready;                                                   // sequencer_rw_mgr_inst_avl_agent:cp_ready -> cmd_mux_001:src_ready
+	wire   [2:0] cmd_mux_001_src_channel;                                                 // cmd_mux_001:src_channel -> sequencer_rw_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_001_src_startofpacket;                                           // cmd_mux_001:src_startofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_001_src_endofpacket;                                             // cmd_mux_001:src_endofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_endofpacket
+	wire  [31:0] sequencer_pll_mgr_inst_avl_agent_m0_readdata;                            // sequencer_pll_mgr_inst_avl_translator:uav_readdata -> sequencer_pll_mgr_inst_avl_agent:m0_readdata
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_waitrequest;                         // sequencer_pll_mgr_inst_avl_translator:uav_waitrequest -> sequencer_pll_mgr_inst_avl_agent:m0_waitrequest
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_debugaccess;                         // sequencer_pll_mgr_inst_avl_agent:m0_debugaccess -> sequencer_pll_mgr_inst_avl_translator:uav_debugaccess
+	wire  [19:0] sequencer_pll_mgr_inst_avl_agent_m0_address;                             // sequencer_pll_mgr_inst_avl_agent:m0_address -> sequencer_pll_mgr_inst_avl_translator:uav_address
+	wire   [3:0] sequencer_pll_mgr_inst_avl_agent_m0_byteenable;                          // sequencer_pll_mgr_inst_avl_agent:m0_byteenable -> sequencer_pll_mgr_inst_avl_translator:uav_byteenable
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_read;                                // sequencer_pll_mgr_inst_avl_agent:m0_read -> sequencer_pll_mgr_inst_avl_translator:uav_read
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid;                       // sequencer_pll_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_pll_mgr_inst_avl_agent:m0_readdatavalid
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_lock;                                // sequencer_pll_mgr_inst_avl_agent:m0_lock -> sequencer_pll_mgr_inst_avl_translator:uav_lock
+	wire  [31:0] sequencer_pll_mgr_inst_avl_agent_m0_writedata;                           // sequencer_pll_mgr_inst_avl_agent:m0_writedata -> sequencer_pll_mgr_inst_avl_translator:uav_writedata
+	wire         sequencer_pll_mgr_inst_avl_agent_m0_write;                               // sequencer_pll_mgr_inst_avl_agent:m0_write -> sequencer_pll_mgr_inst_avl_translator:uav_write
+	wire   [2:0] sequencer_pll_mgr_inst_avl_agent_m0_burstcount;                          // sequencer_pll_mgr_inst_avl_agent:m0_burstcount -> sequencer_pll_mgr_inst_avl_translator:uav_burstcount
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_valid;                        // sequencer_pll_mgr_inst_avl_agent:rf_source_valid -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_valid
+	wire  [92:0] sequencer_pll_mgr_inst_avl_agent_rf_source_data;                         // sequencer_pll_mgr_inst_avl_agent:rf_source_data -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_ready;                        // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_pll_mgr_inst_avl_agent:rf_source_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket;                // sequencer_pll_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket;                  // sequencer_pll_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid;                     // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_pll_mgr_inst_avl_agent:rf_sink_valid
+	wire  [92:0] sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data;                      // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_pll_mgr_inst_avl_agent:rf_sink_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready;                     // sequencer_pll_mgr_inst_avl_agent:rf_sink_ready -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket;             // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket;               // sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_endofpacket
+	wire         cmd_mux_002_src_valid;                                                   // cmd_mux_002:src_valid -> sequencer_pll_mgr_inst_avl_agent:cp_valid
+	wire  [91:0] cmd_mux_002_src_data;                                                    // cmd_mux_002:src_data -> sequencer_pll_mgr_inst_avl_agent:cp_data
+	wire         cmd_mux_002_src_ready;                                                   // sequencer_pll_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready
+	wire   [2:0] cmd_mux_002_src_channel;                                                 // cmd_mux_002:src_channel -> sequencer_pll_mgr_inst_avl_agent:cp_channel
+	wire         cmd_mux_002_src_startofpacket;                                           // cmd_mux_002:src_startofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_startofpacket
+	wire         cmd_mux_002_src_endofpacket;                                             // cmd_mux_002:src_endofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_endofpacket
+	wire         cpu_inst_data_master_agent_cp_valid;                                     // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
+	wire  [91:0] cpu_inst_data_master_agent_cp_data;                                      // cpu_inst_data_master_agent:cp_data -> router:sink_data
+	wire         cpu_inst_data_master_agent_cp_ready;                                     // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
+	wire         cpu_inst_data_master_agent_cp_startofpacket;                             // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
+	wire         cpu_inst_data_master_agent_cp_endofpacket;                               // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
+	wire         router_src_valid;                                                        // router:src_valid -> cmd_demux:sink_valid
+	wire  [91:0] router_src_data;                                                         // router:src_data -> cmd_demux:sink_data
+	wire         router_src_ready;                                                        // cmd_demux:sink_ready -> router:src_ready
+	wire   [2:0] router_src_channel;                                                      // router:src_channel -> cmd_demux:sink_channel
+	wire         router_src_startofpacket;                                                // router:src_startofpacket -> cmd_demux:sink_startofpacket
+	wire         router_src_endofpacket;                                                  // router:src_endofpacket -> cmd_demux:sink_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_valid;                               // sequencer_phy_mgr_inst_avl_agent:rp_valid -> router_001:sink_valid
+	wire  [91:0] sequencer_phy_mgr_inst_avl_agent_rp_data;                                // sequencer_phy_mgr_inst_avl_agent:rp_data -> router_001:sink_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_ready;                               // router_001:sink_ready -> sequencer_phy_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_startofpacket;                       // sequencer_phy_mgr_inst_avl_agent:rp_startofpacket -> router_001:sink_startofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rp_endofpacket;                         // sequencer_phy_mgr_inst_avl_agent:rp_endofpacket -> router_001:sink_endofpacket
+	wire         router_001_src_valid;                                                    // router_001:src_valid -> rsp_demux:sink_valid
+	wire  [91:0] router_001_src_data;                                                     // router_001:src_data -> rsp_demux:sink_data
+	wire         router_001_src_ready;                                                    // rsp_demux:sink_ready -> router_001:src_ready
+	wire   [2:0] router_001_src_channel;                                                  // router_001:src_channel -> rsp_demux:sink_channel
+	wire         router_001_src_startofpacket;                                            // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
+	wire         router_001_src_endofpacket;                                              // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_valid;                                // sequencer_rw_mgr_inst_avl_agent:rp_valid -> router_002:sink_valid
+	wire  [91:0] sequencer_rw_mgr_inst_avl_agent_rp_data;                                 // sequencer_rw_mgr_inst_avl_agent:rp_data -> router_002:sink_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_ready;                                // router_002:sink_ready -> sequencer_rw_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_startofpacket;                        // sequencer_rw_mgr_inst_avl_agent:rp_startofpacket -> router_002:sink_startofpacket
+	wire         sequencer_rw_mgr_inst_avl_agent_rp_endofpacket;                          // sequencer_rw_mgr_inst_avl_agent:rp_endofpacket -> router_002:sink_endofpacket
+	wire         router_002_src_valid;                                                    // router_002:src_valid -> rsp_demux_001:sink_valid
+	wire  [91:0] router_002_src_data;                                                     // router_002:src_data -> rsp_demux_001:sink_data
+	wire         router_002_src_ready;                                                    // rsp_demux_001:sink_ready -> router_002:src_ready
+	wire   [2:0] router_002_src_channel;                                                  // router_002:src_channel -> rsp_demux_001:sink_channel
+	wire         router_002_src_startofpacket;                                            // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
+	wire         router_002_src_endofpacket;                                              // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_valid;                               // sequencer_pll_mgr_inst_avl_agent:rp_valid -> router_003:sink_valid
+	wire  [91:0] sequencer_pll_mgr_inst_avl_agent_rp_data;                                // sequencer_pll_mgr_inst_avl_agent:rp_data -> router_003:sink_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_ready;                               // router_003:sink_ready -> sequencer_pll_mgr_inst_avl_agent:rp_ready
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_startofpacket;                       // sequencer_pll_mgr_inst_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
+	wire         sequencer_pll_mgr_inst_avl_agent_rp_endofpacket;                         // sequencer_pll_mgr_inst_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
+	wire         router_003_src_valid;                                                    // router_003:src_valid -> rsp_demux_002:sink_valid
+	wire  [91:0] router_003_src_data;                                                     // router_003:src_data -> rsp_demux_002:sink_data
+	wire         router_003_src_ready;                                                    // rsp_demux_002:sink_ready -> router_003:src_ready
+	wire   [2:0] router_003_src_channel;                                                  // router_003:src_channel -> rsp_demux_002:sink_channel
+	wire         router_003_src_startofpacket;                                            // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
+	wire         router_003_src_endofpacket;                                              // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
+	wire         cmd_demux_src0_valid;                                                    // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+	wire  [91:0] cmd_demux_src0_data;                                                     // cmd_demux:src0_data -> cmd_mux:sink0_data
+	wire         cmd_demux_src0_ready;                                                    // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+	wire   [2:0] cmd_demux_src0_channel;                                                  // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+	wire         cmd_demux_src0_startofpacket;                                            // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+	wire         cmd_demux_src0_endofpacket;                                              // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+	wire         cmd_demux_src1_valid;                                                    // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
+	wire  [91:0] cmd_demux_src1_data;                                                     // cmd_demux:src1_data -> cmd_mux_001:sink0_data
+	wire         cmd_demux_src1_ready;                                                    // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
+	wire   [2:0] cmd_demux_src1_channel;                                                  // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
+	wire         cmd_demux_src1_startofpacket;                                            // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
+	wire         cmd_demux_src1_endofpacket;                                              // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
+	wire         cmd_demux_src2_valid;                                                    // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
+	wire  [91:0] cmd_demux_src2_data;                                                     // cmd_demux:src2_data -> cmd_mux_002:sink0_data
+	wire         cmd_demux_src2_ready;                                                    // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
+	wire   [2:0] cmd_demux_src2_channel;                                                  // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
+	wire         cmd_demux_src2_startofpacket;                                            // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
+	wire         cmd_demux_src2_endofpacket;                                              // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
+	wire         rsp_demux_src0_valid;                                                    // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+	wire  [91:0] rsp_demux_src0_data;                                                     // rsp_demux:src0_data -> rsp_mux:sink0_data
+	wire         rsp_demux_src0_ready;                                                    // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+	wire   [2:0] rsp_demux_src0_channel;                                                  // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+	wire         rsp_demux_src0_startofpacket;                                            // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+	wire         rsp_demux_src0_endofpacket;                                              // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+	wire         rsp_demux_001_src0_valid;                                                // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
+	wire  [91:0] rsp_demux_001_src0_data;                                                 // rsp_demux_001:src0_data -> rsp_mux:sink1_data
+	wire         rsp_demux_001_src0_ready;                                                // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
+	wire   [2:0] rsp_demux_001_src0_channel;                                              // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
+	wire         rsp_demux_001_src0_startofpacket;                                        // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
+	wire         rsp_demux_001_src0_endofpacket;                                          // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
+	wire         rsp_demux_002_src0_valid;                                                // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
+	wire  [91:0] rsp_demux_002_src0_data;                                                 // rsp_demux_002:src0_data -> rsp_mux:sink2_data
+	wire         rsp_demux_002_src0_ready;                                                // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
+	wire   [2:0] rsp_demux_002_src0_channel;                                              // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
+	wire         rsp_demux_002_src0_startofpacket;                                        // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
+	wire         rsp_demux_002_src0_endofpacket;                                          // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
+	wire         sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid;                   // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
+	wire  [33:0] sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data;                    // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
+	wire         sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready;                   // avalon_st_adapter:in_0_ready -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_out_0_valid;                                           // avalon_st_adapter:out_0_valid -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_out_0_data;                                            // avalon_st_adapter:out_0_data -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_out_0_ready;                                           // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+	wire   [0:0] avalon_st_adapter_out_0_error;                                           // avalon_st_adapter:out_0_error -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_error
+	wire         sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid;                    // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
+	wire  [33:0] sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data;                     // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
+	wire         sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready;                    // avalon_st_adapter_001:in_0_ready -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_001_out_0_valid;                                       // avalon_st_adapter_001:out_0_valid -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_001_out_0_data;                                        // avalon_st_adapter_001:out_0_data -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_001_out_0_ready;                                       // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire   [0:0] avalon_st_adapter_001_out_0_error;                                       // avalon_st_adapter_001:out_0_error -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_error
+	wire         sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid;                   // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
+	wire  [33:0] sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data;                    // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
+	wire         sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready;                   // avalon_st_adapter_002:in_0_ready -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_002_out_0_valid;                                       // avalon_st_adapter_002:out_0_valid -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_002_out_0_data;                                        // avalon_st_adapter_002:out_0_data -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_002_out_0_ready;                                       // sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
+	wire   [0:0] avalon_st_adapter_002_out_0_error;                                       // avalon_st_adapter_002:out_0_error -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_error
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (20),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (20),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) cpu_inst_data_master_translator (
+		.clk                    (avl_clk_out_clk_clk),                                                     //                       clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset),            //                     reset.reset
+		.uav_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (cpu_inst_data_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (cpu_inst_data_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (cpu_inst_data_master_read),                                               //                          .read
+		.av_readdata            (cpu_inst_data_master_readdata),                                           //                          .readdata
+		.av_write               (cpu_inst_data_master_write),                                              //                          .write
+		.av_writedata           (cpu_inst_data_master_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                    //               (terminated)
+		.av_byteenable          (4'b1111),                                                                 //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                    //               (terminated)
+		.av_begintransfer       (1'b0),                                                                    //               (terminated)
+		.av_chipselect          (1'b0),                                                                    //               (terminated)
+		.av_readdatavalid       (),                                                                        //               (terminated)
+		.av_lock                (1'b0),                                                                    //               (terminated)
+		.av_debugaccess         (1'b0),                                                                    //               (terminated)
+		.uav_clken              (),                                                                        //               (terminated)
+		.av_clken               (1'b1),                                                                    //               (terminated)
+		.uav_response           (2'b00),                                                                   //               (terminated)
+		.av_response            (),                                                                        //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                    //               (terminated)
+		.av_writeresponsevalid  ()                                                                         //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_phy_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_phy_mgr_inst_avl_agent_m0_address),                  // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_phy_mgr_inst_avl_agent_m0_burstcount),               //                         .burstcount
+		.uav_read               (sequencer_phy_mgr_inst_avl_agent_m0_read),                     //                         .read
+		.uav_write              (sequencer_phy_mgr_inst_avl_agent_m0_write),                    //                         .write
+		.uav_waitrequest        (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest),              //                         .waitrequest
+		.uav_readdatavalid      (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid),            //                         .readdatavalid
+		.uav_byteenable         (sequencer_phy_mgr_inst_avl_agent_m0_byteenable),               //                         .byteenable
+		.uav_readdata           (sequencer_phy_mgr_inst_avl_agent_m0_readdata),                 //                         .readdata
+		.uav_writedata          (sequencer_phy_mgr_inst_avl_agent_m0_writedata),                //                         .writedata
+		.uav_lock               (sequencer_phy_mgr_inst_avl_agent_m0_lock),                     //                         .lock
+		.uav_debugaccess        (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess),              //                         .debugaccess
+		.av_address             (sequencer_phy_mgr_inst_avl_address),                           //      avalon_anti_slave_0.address
+		.av_write               (sequencer_phy_mgr_inst_avl_write),                             //                         .write
+		.av_read                (sequencer_phy_mgr_inst_avl_read),                              //                         .read
+		.av_readdata            (sequencer_phy_mgr_inst_avl_readdata),                          //                         .readdata
+		.av_writedata           (sequencer_phy_mgr_inst_avl_writedata),                         //                         .writedata
+		.av_waitrequest         (sequencer_phy_mgr_inst_avl_waitrequest),                       //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_rw_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_rw_mgr_inst_avl_agent_m0_address),                   // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_rw_mgr_inst_avl_agent_m0_burstcount),                //                         .burstcount
+		.uav_read               (sequencer_rw_mgr_inst_avl_agent_m0_read),                      //                         .read
+		.uav_write              (sequencer_rw_mgr_inst_avl_agent_m0_write),                     //                         .write
+		.uav_waitrequest        (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest),               //                         .waitrequest
+		.uav_readdatavalid      (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid),             //                         .readdatavalid
+		.uav_byteenable         (sequencer_rw_mgr_inst_avl_agent_m0_byteenable),                //                         .byteenable
+		.uav_readdata           (sequencer_rw_mgr_inst_avl_agent_m0_readdata),                  //                         .readdata
+		.uav_writedata          (sequencer_rw_mgr_inst_avl_agent_m0_writedata),                 //                         .writedata
+		.uav_lock               (sequencer_rw_mgr_inst_avl_agent_m0_lock),                      //                         .lock
+		.uav_debugaccess        (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess),               //                         .debugaccess
+		.av_address             (sequencer_rw_mgr_inst_avl_address),                            //      avalon_anti_slave_0.address
+		.av_write               (sequencer_rw_mgr_inst_avl_write),                              //                         .write
+		.av_read                (sequencer_rw_mgr_inst_avl_read),                               //                         .read
+		.av_readdata            (sequencer_rw_mgr_inst_avl_readdata),                           //                         .readdata
+		.av_writedata           (sequencer_rw_mgr_inst_avl_writedata),                          //                         .writedata
+		.av_waitrequest         (sequencer_rw_mgr_inst_avl_waitrequest),                        //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (13),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sequencer_pll_mgr_inst_avl_translator (
+		.clk                    (avl_clk_out_clk_clk),                                          //                      clk.clk
+		.reset                  (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sequencer_pll_mgr_inst_avl_agent_m0_address),                  // avalon_universal_slave_0.address
+		.uav_burstcount         (sequencer_pll_mgr_inst_avl_agent_m0_burstcount),               //                         .burstcount
+		.uav_read               (sequencer_pll_mgr_inst_avl_agent_m0_read),                     //                         .read
+		.uav_write              (sequencer_pll_mgr_inst_avl_agent_m0_write),                    //                         .write
+		.uav_waitrequest        (sequencer_pll_mgr_inst_avl_agent_m0_waitrequest),              //                         .waitrequest
+		.uav_readdatavalid      (sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid),            //                         .readdatavalid
+		.uav_byteenable         (sequencer_pll_mgr_inst_avl_agent_m0_byteenable),               //                         .byteenable
+		.uav_readdata           (sequencer_pll_mgr_inst_avl_agent_m0_readdata),                 //                         .readdata
+		.uav_writedata          (sequencer_pll_mgr_inst_avl_agent_m0_writedata),                //                         .writedata
+		.uav_lock               (sequencer_pll_mgr_inst_avl_agent_m0_lock),                     //                         .lock
+		.uav_debugaccess        (sequencer_pll_mgr_inst_avl_agent_m0_debugaccess),              //                         .debugaccess
+		.av_address             (sequencer_pll_mgr_inst_avl_address),                           //      avalon_anti_slave_0.address
+		.av_write               (sequencer_pll_mgr_inst_avl_write),                             //                         .write
+		.av_read                (sequencer_pll_mgr_inst_avl_read),                              //                         .read
+		.av_readdata            (sequencer_pll_mgr_inst_avl_readdata),                          //                         .readdata
+		.av_writedata           (sequencer_pll_mgr_inst_avl_writedata),                         //                         .writedata
+		.av_waitrequest         (sequencer_pll_mgr_inst_avl_waitrequest),                       //                         .waitrequest
+		.av_begintransfer       (),                                                             //              (terminated)
+		.av_beginbursttransfer  (),                                                             //              (terminated)
+		.av_burstcount          (),                                                             //              (terminated)
+		.av_byteenable          (),                                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                                         //              (terminated)
+		.av_writebyteenable     (),                                                             //              (terminated)
+		.av_lock                (),                                                             //              (terminated)
+		.av_chipselect          (),                                                             //              (terminated)
+		.av_clken               (),                                                             //              (terminated)
+		.uav_clken              (1'b0),                                                         //              (terminated)
+		.av_debugaccess         (),                                                             //              (terminated)
+		.av_outputenable        (),                                                             //              (terminated)
+		.uav_response           (),                                                             //              (terminated)
+		.av_response            (2'b00),                                                        //              (terminated)
+		.uav_writeresponsevalid (),                                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                          //              (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_QOS_H                 (74),
+		.PKT_QOS_L                 (74),
+		.PKT_DATA_SIDEBAND_H       (72),
+		.PKT_DATA_SIDEBAND_L       (72),
+		.PKT_ADDR_SIDEBAND_H       (71),
+		.PKT_ADDR_SIDEBAND_L       (71),
+		.PKT_BURST_TYPE_H          (70),
+		.PKT_BURST_TYPE_L          (69),
+		.PKT_CACHE_H               (86),
+		.PKT_CACHE_L               (83),
+		.PKT_THREAD_ID_H           (79),
+		.PKT_THREAD_ID_L           (79),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_EXCLUSIVE       (61),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.ST_DATA_W                 (92),
+		.ST_CHANNEL_W              (3),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (0),
+		.BURSTWRAP_VALUE           (1),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) cpu_inst_data_master_agent (
+		.clk                   (avl_clk_out_clk_clk),                                                     //       clk.clk
+		.reset                 (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
+		.av_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (cpu_inst_data_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (cpu_inst_data_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (cpu_inst_data_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (cpu_inst_data_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (cpu_inst_data_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_src_valid),                                                       //        rp.valid
+		.rp_data               (rsp_mux_src_data),                                                        //          .data
+		.rp_channel            (rsp_mux_src_channel),                                                     //          .channel
+		.rp_startofpacket      (rsp_mux_src_startofpacket),                                               //          .startofpacket
+		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                 //          .endofpacket
+		.rp_ready              (rsp_mux_src_ready),                                                       //          .ready
+		.av_response           (),                                                                        // (terminated)
+		.av_writeresponsevalid ()                                                                         // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_phy_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_phy_mgr_inst_avl_agent_m0_address),                  //              m0.address
+		.m0_burstcount           (sequencer_phy_mgr_inst_avl_agent_m0_burstcount),               //                .burstcount
+		.m0_byteenable           (sequencer_phy_mgr_inst_avl_agent_m0_byteenable),               //                .byteenable
+		.m0_debugaccess          (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess),              //                .debugaccess
+		.m0_lock                 (sequencer_phy_mgr_inst_avl_agent_m0_lock),                     //                .lock
+		.m0_readdata             (sequencer_phy_mgr_inst_avl_agent_m0_readdata),                 //                .readdata
+		.m0_readdatavalid        (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid),            //                .readdatavalid
+		.m0_read                 (sequencer_phy_mgr_inst_avl_agent_m0_read),                     //                .read
+		.m0_waitrequest          (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest),              //                .waitrequest
+		.m0_writedata            (sequencer_phy_mgr_inst_avl_agent_m0_writedata),                //                .writedata
+		.m0_write                (sequencer_phy_mgr_inst_avl_agent_m0_write),                    //                .write
+		.rp_endofpacket          (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket),              //              rp.endofpacket
+		.rp_ready                (sequencer_phy_mgr_inst_avl_agent_rp_ready),                    //                .ready
+		.rp_valid                (sequencer_phy_mgr_inst_avl_agent_rp_valid),                    //                .valid
+		.rp_data                 (sequencer_phy_mgr_inst_avl_agent_rp_data),                     //                .data
+		.rp_startofpacket        (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket),            //                .startofpacket
+		.cp_ready                (cmd_mux_src_ready),                                            //              cp.ready
+		.cp_valid                (cmd_mux_src_valid),                                            //                .valid
+		.cp_data                 (cmd_mux_src_data),                                             //                .data
+		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //                .startofpacket
+		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //                .endofpacket
+		.cp_channel              (cmd_mux_src_channel),                                          //                .channel
+		.rf_sink_ready           (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready),          //         rf_sink.ready
+		.rf_sink_valid           (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid),          //                .valid
+		.rf_sink_startofpacket   (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //                .endofpacket
+		.rf_sink_data            (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data),           //                .data
+		.rf_source_ready         (sequencer_phy_mgr_inst_avl_agent_rf_source_ready),             //       rf_source.ready
+		.rf_source_valid         (sequencer_phy_mgr_inst_avl_agent_rf_source_valid),             //                .valid
+		.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket),     //                .startofpacket
+		.rf_source_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket),       //                .endofpacket
+		.rf_source_data          (sequencer_phy_mgr_inst_avl_agent_rf_source_data),              //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                 //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                //                .error
+		.rdata_fifo_src_ready    (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready),        //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid),        //                .valid
+		.rdata_fifo_src_data     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data),         //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_phy_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_phy_mgr_inst_avl_agent_rf_source_data),              //        in.data
+		.in_valid          (sequencer_phy_mgr_inst_avl_agent_rf_source_valid),             //          .valid
+		.in_ready          (sequencer_phy_mgr_inst_avl_agent_rf_source_ready),             //          .ready
+		.in_startofpacket  (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket),     //          .startofpacket
+		.in_endofpacket    (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket),       //          .endofpacket
+		.out_data          (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data),           //       out.data
+		.out_valid         (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid),          //          .valid
+		.out_ready         (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready),          //          .ready
+		.out_startofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
+		.out_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_rw_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_rw_mgr_inst_avl_agent_m0_address),                   //              m0.address
+		.m0_burstcount           (sequencer_rw_mgr_inst_avl_agent_m0_burstcount),                //                .burstcount
+		.m0_byteenable           (sequencer_rw_mgr_inst_avl_agent_m0_byteenable),                //                .byteenable
+		.m0_debugaccess          (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess),               //                .debugaccess
+		.m0_lock                 (sequencer_rw_mgr_inst_avl_agent_m0_lock),                      //                .lock
+		.m0_readdata             (sequencer_rw_mgr_inst_avl_agent_m0_readdata),                  //                .readdata
+		.m0_readdatavalid        (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid),             //                .readdatavalid
+		.m0_read                 (sequencer_rw_mgr_inst_avl_agent_m0_read),                      //                .read
+		.m0_waitrequest          (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest),               //                .waitrequest
+		.m0_writedata            (sequencer_rw_mgr_inst_avl_agent_m0_writedata),                 //                .writedata
+		.m0_write                (sequencer_rw_mgr_inst_avl_agent_m0_write),                     //                .write
+		.rp_endofpacket          (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket),               //              rp.endofpacket
+		.rp_ready                (sequencer_rw_mgr_inst_avl_agent_rp_ready),                     //                .ready
+		.rp_valid                (sequencer_rw_mgr_inst_avl_agent_rp_valid),                     //                .valid
+		.rp_data                 (sequencer_rw_mgr_inst_avl_agent_rp_data),                      //                .data
+		.rp_startofpacket        (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket),             //                .startofpacket
+		.cp_ready                (cmd_mux_001_src_ready),                                        //              cp.ready
+		.cp_valid                (cmd_mux_001_src_valid),                                        //                .valid
+		.cp_data                 (cmd_mux_001_src_data),                                         //                .data
+		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                                //                .startofpacket
+		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                                  //                .endofpacket
+		.cp_channel              (cmd_mux_001_src_channel),                                      //                .channel
+		.rf_sink_ready           (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready),           //         rf_sink.ready
+		.rf_sink_valid           (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid),           //                .valid
+		.rf_sink_startofpacket   (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
+		.rf_sink_data            (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data),            //                .data
+		.rf_source_ready         (sequencer_rw_mgr_inst_avl_agent_rf_source_ready),              //       rf_source.ready
+		.rf_source_valid         (sequencer_rw_mgr_inst_avl_agent_rf_source_valid),              //                .valid
+		.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket),      //                .startofpacket
+		.rf_source_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket),        //                .endofpacket
+		.rf_source_data          (sequencer_rw_mgr_inst_avl_agent_rf_source_data),               //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                            // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                            //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                             //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                            //                .error
+		.rdata_fifo_src_ready    (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid),         //                .valid
+		.rdata_fifo_src_data     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data),          //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_rw_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_rw_mgr_inst_avl_agent_rf_source_data),               //        in.data
+		.in_valid          (sequencer_rw_mgr_inst_avl_agent_rf_source_valid),              //          .valid
+		.in_ready          (sequencer_rw_mgr_inst_avl_agent_rf_source_ready),              //          .ready
+		.in_startofpacket  (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket),      //          .startofpacket
+		.in_endofpacket    (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket),        //          .endofpacket
+		.out_data          (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data),            //       out.data
+		.out_valid         (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid),           //          .valid
+		.out_ready         (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready),           //          .ready
+		.out_startofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
+		.out_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (91),
+		.PKT_ORI_BURST_SIZE_L      (89),
+		.PKT_RESPONSE_STATUS_H     (88),
+		.PKT_RESPONSE_STATUS_L     (87),
+		.PKT_BURST_SIZE_H          (68),
+		.PKT_BURST_SIZE_L          (66),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (73),
+		.PKT_PROTECTION_H          (82),
+		.PKT_PROTECTION_L          (80),
+		.PKT_BURSTWRAP_H           (65),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (76),
+		.PKT_SRC_ID_L              (75),
+		.PKT_DEST_ID_H             (78),
+		.PKT_DEST_ID_L             (77),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (3),
+		.ST_DATA_W                 (92),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sequencer_pll_mgr_inst_avl_agent (
+		.clk                     (avl_clk_out_clk_clk),                                          //             clk.clk
+		.reset                   (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sequencer_pll_mgr_inst_avl_agent_m0_address),                  //              m0.address
+		.m0_burstcount           (sequencer_pll_mgr_inst_avl_agent_m0_burstcount),               //                .burstcount
+		.m0_byteenable           (sequencer_pll_mgr_inst_avl_agent_m0_byteenable),               //                .byteenable
+		.m0_debugaccess          (sequencer_pll_mgr_inst_avl_agent_m0_debugaccess),              //                .debugaccess
+		.m0_lock                 (sequencer_pll_mgr_inst_avl_agent_m0_lock),                     //                .lock
+		.m0_readdata             (sequencer_pll_mgr_inst_avl_agent_m0_readdata),                 //                .readdata
+		.m0_readdatavalid        (sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid),            //                .readdatavalid
+		.m0_read                 (sequencer_pll_mgr_inst_avl_agent_m0_read),                     //                .read
+		.m0_waitrequest          (sequencer_pll_mgr_inst_avl_agent_m0_waitrequest),              //                .waitrequest
+		.m0_writedata            (sequencer_pll_mgr_inst_avl_agent_m0_writedata),                //                .writedata
+		.m0_write                (sequencer_pll_mgr_inst_avl_agent_m0_write),                    //                .write
+		.rp_endofpacket          (sequencer_pll_mgr_inst_avl_agent_rp_endofpacket),              //              rp.endofpacket
+		.rp_ready                (sequencer_pll_mgr_inst_avl_agent_rp_ready),                    //                .ready
+		.rp_valid                (sequencer_pll_mgr_inst_avl_agent_rp_valid),                    //                .valid
+		.rp_data                 (sequencer_pll_mgr_inst_avl_agent_rp_data),                     //                .data
+		.rp_startofpacket        (sequencer_pll_mgr_inst_avl_agent_rp_startofpacket),            //                .startofpacket
+		.cp_ready                (cmd_mux_002_src_ready),                                        //              cp.ready
+		.cp_valid                (cmd_mux_002_src_valid),                                        //                .valid
+		.cp_data                 (cmd_mux_002_src_data),                                         //                .data
+		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                                //                .startofpacket
+		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                                  //                .endofpacket
+		.cp_channel              (cmd_mux_002_src_channel),                                      //                .channel
+		.rf_sink_ready           (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready),          //         rf_sink.ready
+		.rf_sink_valid           (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid),          //                .valid
+		.rf_sink_startofpacket   (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //                .startofpacket
+		.rf_sink_endofpacket     (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //                .endofpacket
+		.rf_sink_data            (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data),           //                .data
+		.rf_source_ready         (sequencer_pll_mgr_inst_avl_agent_rf_source_ready),             //       rf_source.ready
+		.rf_source_valid         (sequencer_pll_mgr_inst_avl_agent_rf_source_valid),             //                .valid
+		.rf_source_startofpacket (sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket),     //                .startofpacket
+		.rf_source_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket),       //                .endofpacket
+		.rf_source_data          (sequencer_pll_mgr_inst_avl_agent_rf_source_data),              //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),                            // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),                            //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                             //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),                            //                .error
+		.rdata_fifo_src_ready    (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready),        //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid),        //                .valid
+		.rdata_fifo_src_data     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data),         //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (93),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sequencer_pll_mgr_inst_avl_agent_rsp_fifo (
+		.clk               (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset             (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sequencer_pll_mgr_inst_avl_agent_rf_source_data),              //        in.data
+		.in_valid          (sequencer_pll_mgr_inst_avl_agent_rf_source_valid),             //          .valid
+		.in_ready          (sequencer_pll_mgr_inst_avl_agent_rf_source_ready),             //          .ready
+		.in_startofpacket  (sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket),     //          .startofpacket
+		.in_endofpacket    (sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket),       //          .endofpacket
+		.out_data          (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data),           //       out.data
+		.out_valid         (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid),          //          .valid
+		.out_ready         (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready),          //          .ready
+		.out_startofpacket (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
+		.out_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router router (
+		.sink_ready         (cpu_inst_data_master_agent_cp_ready),                          //      sink.ready
+		.sink_valid         (cpu_inst_data_master_agent_cp_valid),                          //          .valid
+		.sink_data          (cpu_inst_data_master_agent_cp_data),                           //          .data
+		.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket),                  //          .startofpacket
+		.sink_endofpacket   (cpu_inst_data_master_agent_cp_endofpacket),                    //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_src_ready),                                             //       src.ready
+		.src_valid          (router_src_valid),                                             //          .valid
+		.src_data           (router_src_data),                                              //          .data
+		.src_channel        (router_src_channel),                                           //          .channel
+		.src_startofpacket  (router_src_startofpacket),                                     //          .startofpacket
+		.src_endofpacket    (router_src_endofpacket)                                        //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001 router_001 (
+		.sink_ready         (sequencer_phy_mgr_inst_avl_agent_rp_ready),                    //      sink.ready
+		.sink_valid         (sequencer_phy_mgr_inst_avl_agent_rp_valid),                    //          .valid
+		.sink_data          (sequencer_phy_mgr_inst_avl_agent_rp_data),                     //          .data
+		.sink_startofpacket (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket),              //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_001_src_ready),                                         //       src.ready
+		.src_valid          (router_001_src_valid),                                         //          .valid
+		.src_data           (router_001_src_data),                                          //          .data
+		.src_channel        (router_001_src_channel),                                       //          .channel
+		.src_startofpacket  (router_001_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_001_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001 router_002 (
+		.sink_ready         (sequencer_rw_mgr_inst_avl_agent_rp_ready),                     //      sink.ready
+		.sink_valid         (sequencer_rw_mgr_inst_avl_agent_rp_valid),                     //          .valid
+		.sink_data          (sequencer_rw_mgr_inst_avl_agent_rp_data),                      //          .data
+		.sink_startofpacket (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket),             //          .startofpacket
+		.sink_endofpacket   (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket),               //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_002_src_ready),                                         //       src.ready
+		.src_valid          (router_002_src_valid),                                         //          .valid
+		.src_data           (router_002_src_data),                                          //          .data
+		.src_channel        (router_002_src_channel),                                       //          .channel
+		.src_startofpacket  (router_002_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_002_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001 router_003 (
+		.sink_ready         (sequencer_pll_mgr_inst_avl_agent_rp_ready),                    //      sink.ready
+		.sink_valid         (sequencer_pll_mgr_inst_avl_agent_rp_valid),                    //          .valid
+		.sink_data          (sequencer_pll_mgr_inst_avl_agent_rp_data),                     //          .data
+		.sink_startofpacket (sequencer_pll_mgr_inst_avl_agent_rp_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (sequencer_pll_mgr_inst_avl_agent_rp_endofpacket),              //          .endofpacket
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_003_src_ready),                                         //       src.ready
+		.src_valid          (router_003_src_valid),                                         //          .valid
+		.src_data           (router_003_src_data),                                          //          .data
+		.src_channel        (router_003_src_channel),                                       //          .channel
+		.src_startofpacket  (router_003_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket    (router_003_src_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux cmd_demux (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_src_ready),                                             //      sink.ready
+		.sink_channel       (router_src_channel),                                           //          .channel
+		.sink_data          (router_src_data),                                              //          .data
+		.sink_startofpacket (router_src_startofpacket),                                     //          .startofpacket
+		.sink_endofpacket   (router_src_endofpacket),                                       //          .endofpacket
+		.sink_valid         (router_src_valid),                                             //          .valid
+		.src0_ready         (cmd_demux_src0_ready),                                         //      src0.ready
+		.src0_valid         (cmd_demux_src0_valid),                                         //          .valid
+		.src0_data          (cmd_demux_src0_data),                                          //          .data
+		.src0_channel       (cmd_demux_src0_channel),                                       //          .channel
+		.src0_startofpacket (cmd_demux_src0_startofpacket),                                 //          .startofpacket
+		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                   //          .endofpacket
+		.src1_ready         (cmd_demux_src1_ready),                                         //      src1.ready
+		.src1_valid         (cmd_demux_src1_valid),                                         //          .valid
+		.src1_data          (cmd_demux_src1_data),                                          //          .data
+		.src1_channel       (cmd_demux_src1_channel),                                       //          .channel
+		.src1_startofpacket (cmd_demux_src1_startofpacket),                                 //          .startofpacket
+		.src1_endofpacket   (cmd_demux_src1_endofpacket),                                   //          .endofpacket
+		.src2_ready         (cmd_demux_src2_ready),                                         //      src2.ready
+		.src2_valid         (cmd_demux_src2_valid),                                         //          .valid
+		.src2_data          (cmd_demux_src2_data),                                          //          .data
+		.src2_channel       (cmd_demux_src2_channel),                                       //          .channel
+		.src2_startofpacket (cmd_demux_src2_startofpacket),                                 //          .startofpacket
+		.src2_endofpacket   (cmd_demux_src2_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_src_ready),                                            //       src.ready
+		.src_valid           (cmd_mux_src_valid),                                            //          .valid
+		.src_data            (cmd_mux_src_data),                                             //          .data
+		.src_channel         (cmd_mux_src_channel),                                          //          .channel
+		.src_startofpacket   (cmd_mux_src_startofpacket),                                    //          .startofpacket
+		.src_endofpacket     (cmd_mux_src_endofpacket),                                      //          .endofpacket
+		.sink0_ready         (cmd_demux_src0_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src0_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src0_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src0_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_001 (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_001_src_ready),                                        //       src.ready
+		.src_valid           (cmd_mux_001_src_valid),                                        //          .valid
+		.src_data            (cmd_mux_001_src_data),                                         //          .data
+		.src_channel         (cmd_mux_001_src_channel),                                      //          .channel
+		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                //          .startofpacket
+		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                  //          .endofpacket
+		.sink0_ready         (cmd_demux_src1_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src1_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src1_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src1_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src1_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_002 (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_002_src_ready),                                        //       src.ready
+		.src_valid           (cmd_mux_002_src_valid),                                        //          .valid
+		.src_data            (cmd_mux_002_src_data),                                         //          .data
+		.src_channel         (cmd_mux_002_src_channel),                                      //          .channel
+		.src_startofpacket   (cmd_mux_002_src_startofpacket),                                //          .startofpacket
+		.src_endofpacket     (cmd_mux_002_src_endofpacket),                                  //          .endofpacket
+		.sink0_ready         (cmd_demux_src2_ready),                                         //     sink0.ready
+		.sink0_valid         (cmd_demux_src2_valid),                                         //          .valid
+		.sink0_channel       (cmd_demux_src2_channel),                                       //          .channel
+		.sink0_data          (cmd_demux_src2_data),                                          //          .data
+		.sink0_startofpacket (cmd_demux_src2_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux rsp_demux (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_001_src_ready),                                         //      sink.ready
+		.sink_channel       (router_001_src_channel),                                       //          .channel
+		.sink_data          (router_001_src_data),                                          //          .data
+		.sink_startofpacket (router_001_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_001_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_001_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_src0_ready),                                         //      src0.ready
+		.src0_valid         (rsp_demux_src0_valid),                                         //          .valid
+		.src0_data          (rsp_demux_src0_data),                                          //          .data
+		.src0_channel       (rsp_demux_src0_channel),                                       //          .channel
+		.src0_startofpacket (rsp_demux_src0_startofpacket),                                 //          .startofpacket
+		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                    //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux rsp_demux_001 (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_002_src_ready),                                         //      sink.ready
+		.sink_channel       (router_002_src_channel),                                       //          .channel
+		.sink_data          (router_002_src_data),                                          //          .data
+		.sink_startofpacket (router_002_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_002_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_002_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_001_src0_ready),                                     //      src0.ready
+		.src0_valid         (rsp_demux_001_src0_valid),                                     //          .valid
+		.src0_data          (rsp_demux_001_src0_data),                                      //          .data
+		.src0_channel       (rsp_demux_001_src0_channel),                                   //          .channel
+		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                             //          .startofpacket
+		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux rsp_demux_002 (
+		.clk                (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset              (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_003_src_ready),                                         //      sink.ready
+		.sink_channel       (router_003_src_channel),                                       //          .channel
+		.sink_data          (router_003_src_data),                                          //          .data
+		.sink_startofpacket (router_003_src_startofpacket),                                 //          .startofpacket
+		.sink_endofpacket   (router_003_src_endofpacket),                                   //          .endofpacket
+		.sink_valid         (router_003_src_valid),                                         //          .valid
+		.src0_ready         (rsp_demux_002_src0_ready),                                     //      src0.ready
+		.src0_valid         (rsp_demux_002_src0_valid),                                     //          .valid
+		.src0_data          (rsp_demux_002_src0_data),                                      //          .data
+		.src0_channel       (rsp_demux_002_src0_channel),                                   //          .channel
+		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                             //          .startofpacket
+		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux rsp_mux (
+		.clk                 (avl_clk_out_clk_clk),                                          //       clk.clk
+		.reset               (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_src_ready),                                            //       src.ready
+		.src_valid           (rsp_mux_src_valid),                                            //          .valid
+		.src_data            (rsp_mux_src_data),                                             //          .data
+		.src_channel         (rsp_mux_src_channel),                                          //          .channel
+		.src_startofpacket   (rsp_mux_src_startofpacket),                                    //          .startofpacket
+		.src_endofpacket     (rsp_mux_src_endofpacket),                                      //          .endofpacket
+		.sink0_ready         (rsp_demux_src0_ready),                                         //     sink0.ready
+		.sink0_valid         (rsp_demux_src0_valid),                                         //          .valid
+		.sink0_channel       (rsp_demux_src0_channel),                                       //          .channel
+		.sink0_data          (rsp_demux_src0_data),                                          //          .data
+		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                                   //          .endofpacket
+		.sink1_ready         (rsp_demux_001_src0_ready),                                     //     sink1.ready
+		.sink1_valid         (rsp_demux_001_src0_valid),                                     //          .valid
+		.sink1_channel       (rsp_demux_001_src0_channel),                                   //          .channel
+		.sink1_data          (rsp_demux_001_src0_data),                                      //          .data
+		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                             //          .startofpacket
+		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                               //          .endofpacket
+		.sink2_ready         (rsp_demux_002_src0_ready),                                     //     sink2.ready
+		.sink2_valid         (rsp_demux_002_src0_valid),                                     //          .valid
+		.sink2_channel       (rsp_demux_002_src0_channel),                                   //          .channel
+		.sink2_data          (rsp_demux_002_src0_data),                                      //          .data
+		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                             //          .startofpacket
+		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data),         //     in_0.data
+		.in_0_valid     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid),        //         .valid
+		.in_0_ready     (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready),        //         .ready
+		.out_0_data     (avalon_st_adapter_out_0_data),                                 //    out_0.data
+		.out_0_valid    (avalon_st_adapter_out_0_valid),                                //         .valid
+		.out_0_ready    (avalon_st_adapter_out_0_ready),                                //         .ready
+		.out_0_error    (avalon_st_adapter_out_0_error)                                 //         .error
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data),          //     in_0.data
+		.in_0_valid     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid),         //         .valid
+		.in_0_ready     (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready),         //         .ready
+		.out_0_data     (avalon_st_adapter_001_out_0_data),                             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                            //         .valid
+		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                            //         .ready
+		.out_0_error    (avalon_st_adapter_001_out_0_error)                             //         .error
+	);
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_002 (
+		.in_clk_0_clk   (avl_clk_out_clk_clk),                                          // in_clk_0.clk
+		.in_rst_0_reset (sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data),         //     in_0.data
+		.in_0_valid     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid),        //         .valid
+		.in_0_ready     (sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready),        //         .ready
+		.out_0_data     (avalon_st_adapter_002_out_0_data),                             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_002_out_0_valid),                            //         .valid
+		.out_0_ready    (avalon_st_adapter_002_out_0_ready),                            //         .ready
+		.out_0_error    (avalon_st_adapter_002_out_0_error)                             //         .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
new file mode 100644
index 0000000..f6b35b7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
@@ -0,0 +1,202 @@
+// q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..12ea2d2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
new file mode 100644
index 0000000..97ee585
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
@@ -0,0 +1,130 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+//   NUM_OUTPUTS:         3
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
+    input  [3-1 : 0]   sink_channel, // ST_CHANNEL_W=3
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src0_channel, // ST_CHANNEL_W=3
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [92-1    : 0] src1_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src1_channel, // ST_CHANNEL_W=3
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [92-1    : 0] src2_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src2_channel, // ST_CHANNEL_W=3
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 3;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
new file mode 100644
index 0000000..f179453
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+// ------------------------------------------
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [92-1   : 0]  sink0_data,
+    input [3-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [92-1    : 0] src_data,
+    output [3-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 92 + 3 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 92;
+    localparam ST_CHANNEL_W     = 3;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
new file mode 100644
index 0000000..9ac5bf3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
@@ -0,0 +1,234 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [78 - 77 : 0] default_destination_id,
+   output [3-1 : 0] default_wr_channel,
+   output [3-1 : 0] default_rd_channel,
+   output [3-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[78 - 77 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 3'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 3'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 3'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [92-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [92-1    : 0] src_data,
+    output reg [3-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 78;
+    localparam PKT_DEST_ID_L = 77;
+    localparam PKT_PROTECTION_H = 82;
+    localparam PKT_PROTECTION_L = 80;
+    localparam ST_DATA_W = 92;
+    localparam ST_CHANNEL_W = 3;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h50000 - 64'h48000); 
+    localparam PAD1 = log2ceil(64'h58000 - 64'h50000); 
+    localparam PAD2 = log2ceil(64'h60000 - 64'h58000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h60000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [3-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x48000 .. 0x50000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h48000   ) begin
+            src_channel = 3'b001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+    // ( 0x50000 .. 0x58000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h50000   ) begin
+            src_channel = 3'b010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x58000 .. 0x60000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h58000   ) begin
+            src_channel = 3'b100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
new file mode 100644
index 0000000..d461653
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [78 - 77 : 0] default_destination_id,
+   output [3-1 : 0] default_wr_channel,
+   output [3-1 : 0] default_rd_channel,
+   output [3-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[78 - 77 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 3'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 3'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 3'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [92-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [92-1    : 0] src_data,
+    output reg [3-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 78;
+    localparam PKT_DEST_ID_L = 77;
+    localparam PKT_PROTECTION_H = 82;
+    localparam PKT_PROTECTION_L = 80;
+    localparam ST_DATA_W = 92;
+    localparam ST_CHANNEL_W = 3;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [3-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 3'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
new file mode 100644
index 0000000..6831553
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
+    input  [3-1 : 0]   sink_channel, // ST_CHANNEL_W=3
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
+    output reg [3-1 : 0] src0_channel, // ST_CHANNEL_W=3
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
new file mode 100644
index 0000000..ad73ac5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
@@ -0,0 +1,365 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux
+//   NUM_INPUTS:          3
+//   ARBITRATION_SHARES:  1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           92
+//   ST_CHANNEL_W:        3
+// ------------------------------------------
+
+module q_sys_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [92-1   : 0]  sink0_data,
+    input [3-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [92-1   : 0]  sink1_data,
+    input [3-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [92-1   : 0]  sink2_data,
+    input [3-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [92-1    : 0] src_data,
+    output [3-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 92 + 3 + 2;
+    localparam NUM_INPUTS       = 3;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 92;
+    localparam ST_CHANNEL_W     = 3;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[60];
+      lock[1] = sink1_data[60];
+      lock[2] = sink2_data[60];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
new file mode 100644
index 0000000..765350d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_defines.h
@@ -0,0 +1,164 @@
+/*
+Copyright (C) 2016 Intel Corporation
+All rights reserved.
+
+SPDX-License-Identifier:    BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000000000
+#define AC_ROM_MR1_OCD_ENABLE 
+#define AC_ROM_MR2_MIRR 0000000000000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB 
+#define AC_ROM_MR0_DLL_RESET_MIRR 0001010001000
+#define AC_ROM_MR0_DLL_RESET 0001100010000
+#define AC_ROM_MR0_MIRR 0001000001001
+#define AC_ROM_MR0 0001000010001
+#define AC_ROM_MR1 0000000000000
+#define AC_ROM_MR2 0000000000000
+#define AC_ROM_MR3 0000000000000
+#define AC_ROM_USER_ADD_0 0_0000_0000_0000
+#define AC_ROM_USER_ADD_1 0_0000_0000_1000
+#define AFI_CLK_FREQ 151
+#define AFI_RATE_RATIO 2
+#define AP_MODE 0
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 1
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 4
+#define CALIB_VFIFO_OFFSET 12
+#define CYCLONEV 0
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DELAY_CHAIN_WRITE 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 0
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_NON_DES_CAL_TEST 0
+#define ENABLE_NON_DES_CAL 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FAKE_CAL_FAIL 0
+#define FIX_READ_LATENCY 8
+#define FULL_RATE 0
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 1
+#define HARD_PHY 0
+#define HARD_VFIFO 0
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 0
+#define HPS_HW 0
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 50
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 50
+#define IO_DELAY_PER_OPA_TAP 416
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 14
+#define IO_DQS_EN_DELAY_MAX 7
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 15
+#define IO_DQS_IN_RESERVE 3
+#define IO_DQS_OUT_RESERVE 3
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 15
+#define IO_IO_OUT1_DELAY_MAX 15
+#define IO_IO_OUT2_DELAY_MAX 7
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MRS_MIRROR_PING_PONG_ATSO 0
+#define NON_DES_CAL 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 0
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 14
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 1
+#define RW_MGR_MEM_DATA_WIDTH 8
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 1
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 1
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 1
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SET_FIX_READ_LATENCY_ENABLE 0
+#define SKEW_CALIBRATION 0
+#define SKIP_PTAP_0_DQS_EN_CAL 0
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 36
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 36
+#define USE_DQS_TRACKING 0
+#define USE_SHADOW_REGS 0
+#define USE_USER_RDIMM_VALUE 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
new file mode 100644
index 0000000..02c003f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.c
@@ -0,0 +1,720 @@
+
+#include "sequencer_defines.h"
+
+#include "alt_types.h"
+#include "system.h"
+#include "io.h"
+#include "sequencer_m10.h"
+#include "sequencer_auto.h"
+
+// Just to make the debugging code more uniform
+#ifndef RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 0
+#endif
+
+// To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
+// instead of static, we use boolean logic to select between
+// non-skip and skip values
+//
+// The mask is set to include all bits when not-skipping, but is
+// zero when skipping
+
+gbl_t *gbl = 0;
+param_t *param = 0;
+
+void initialize(void)
+{
+	alt_u32 i;
+	
+	// Initial LFIFO is max
+	
+	IOWR_32DIRECT (PHY_MGR_PHY_RLAT, 0, 0xf);
+
+	//USER calibration has control over path to memory 
+
+	IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 1);
+
+	//USER memory clock is not stable we begin initialization 
+
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 0);
+
+	//USER calibration status all set to zero 
+
+	IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, 0);
+
+	param->read_correct_mask_vg  = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+	param->write_correct_mask_vg = ((t_btfld)1 << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+	param->read_correct_mask     = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
+	param->write_correct_mask    = ((t_btfld)1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+	param->dm_correct_mask       = ((t_btfld)1 << (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH)) - 1;
+}
+
+void set_rank_and_odt_mask(alt_u32 rank)
+{
+	alt_u32 odt_mask_0 = 0;
+	alt_u32 odt_mask_1 = 0;
+	alt_u32 cs_and_odt_mask;
+	
+	odt_mask_0 = 0x0;
+	odt_mask_1 = 0x0;
+
+	cs_and_odt_mask = 
+		(0xFF & ~(1 << rank)) |
+		((0xFF & odt_mask_0) << 8) |
+		((0xFF & odt_mask_1) << 16);
+
+	IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, cs_and_odt_mask);
+}
+
+// should always use constants as argument to ensure all computations are performed at compile time
+static inline void delay_for_n_mem_clocks(const alt_u32 clocks)
+{
+	alt_u32 afi_clocks;
+	alt_u8 inner;
+	alt_u8 outer;
+	alt_u16 c_loop;
+
+	afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO; /* scale (rounding up) to get afi clocks */
+
+	// Note, we don't bother accounting for being off a little bit because of a few extra instructions in outer loops
+	// Note, the loops have a test at the end, and do the test before the decrement, and so always perform the loop
+	// 1 time more than the counter value
+	if (afi_clocks == 0) {
+		inner = outer = c_loop = 0;
+	} else if (afi_clocks <= 0x100) {
+		inner = afi_clocks-1;
+		outer = 0;
+		c_loop = 0;
+	} else if (afi_clocks <= 0x10000) {
+		inner = 0xff;
+		outer = (afi_clocks-1) >> 8;
+		c_loop = 0;
+	} else {
+		inner = 0xff;
+		outer = 0xff;
+		c_loop = (afi_clocks-1) >> 16;
+	}
+
+	// rom instructions are structured as follows:
+	//
+	//    IDLE_LOOP2: jnz cntr0, TARGET_A
+	//    IDLE_LOOP1: jnz cntr1, TARGET_B
+	//                return
+	//
+	// so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and TARGET_B is
+	// set to IDLE_LOOP2 as well
+	//
+	// if we have no outer loop, though, then we can use IDLE_LOOP1 only, and set
+	// TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
+	//
+	// a little confusing, but it helps save precious space in the inst_rom and sequencer rom
+	// and keeps the delays more accurate and reduces overhead
+	if (afi_clocks <= 0x100) {
+
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, inner);
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP1);
+		IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP1);
+
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, inner);
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, outer);
+	
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_IDLE_LOOP2);
+		IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_IDLE_LOOP2);
+
+		// hack to get around compiler not being smart enough
+		if (afi_clocks <= 0x10000) {
+			// only need to run once
+			IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
+		} else {
+			do {
+				IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_IDLE_LOOP2);
+			} while (c_loop-- != 0);
+		}
+	}
+
+}
+
+// should always use constants as argument to ensure all computations are performed at compile time
+static inline void delay_for_n_ns(const alt_u32 nanoseconds)
+{
+	delay_for_n_mem_clocks((1000*nanoseconds) / (1000000/AFI_CLK_FREQ) * AFI_RATE_RATIO);
+}
+
+#if DDR3
+void rw_mgr_mem_initialize (void)
+{
+	//USER The reset / cke part of initialization is broadcasted to all ranks
+	IOWR_32DIRECT (RW_MGR_SET_CS_AND_ODT_MASK, 0, RW_MGR_RANK_ALL);
+
+	//USER start with memory RESET activated
+	//USER tINIT = 200us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0xFF
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0x6A
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_0_CKE_0_inloop);
+
+	//USER Execute count instruction
+	//USER IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0);
+
+	//USER indicate that memory is stable
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER transition the RESET to high 
+	//USER Wait for 500us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0x83
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0xFF
+
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0_inloop_1);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0);
+
+	//USER bring up clock enable 
+
+	//USER tXRP < 250 ck cycles
+	delay_for_n_mem_clocks(250);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_DLL_RESET);
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ZQCL);
+    
+	//USER tZQinit = tDLLK = 512 ck cycles
+	delay_for_n_mem_clocks(512);
+
+}
+#endif // DDR3
+
+#if DDR2
+void rw_mgr_mem_initialize (void)
+{
+	//USER start with CKE low 
+	//USER tINIT = 200us
+
+	//USER Load counters
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x2);//was 0xFF
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x2);//was 0x76
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0_inloop);
+
+	//USER Execute count instruction
+	//USER IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER indicate that memory is stable 
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER Bring up CKE 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_NOP);
+
+	//USER *** STAGE (4)
+
+	//USER Wait for 400ns 
+	delay_for_n_ns(400);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER *** STAGE (5)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2);
+    
+	//USER *** STAGE (6)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3);
+    
+	//USER *** STAGE (7)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+    
+	//USER *** STAGE (8)
+	//USER DLL reset
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_DLL_RESET);
+    
+	//USER *** STAGE (9)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER *** STAGE (10)
+    
+	//USER Issue 2 refresh commands spaced by tREF 
+    
+	//USER First REFRESH
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH);
+    
+	//USER tREF = 200ns
+	delay_for_n_ns(200);
+    
+	//USER Second REFRESH
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_REFRESH);
+    
+	//USER Second idle loop
+	delay_for_n_ns(200);
+    
+	//USER *** STAGE (11)
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_CALIB);
+    
+	//USER *** STAGE (12)
+	//USER OCD defaults
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR_OCD_ENABLE);
+    
+	//USER *** STAGE (13)
+	//USER OCD exit
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+    
+	//USER *** STAGE (14)
+    
+	//USER The memory is now initialized. Before being able to use it, we must still
+	//USER wait for the DLL to lock, 200 clock cycles after it was reset @ STAGE (8).
+	//USER Since we cannot keep track of time in any other way, let's start counting from now
+	delay_for_n_mem_clocks(200);
+}
+#endif // DDR2 
+
+#if LPDDR2
+void rw_mgr_mem_initialize (void)
+{
+	//USER start with CKE low 
+	//USER tINIT1 = 100ns
+
+	//USER Load counter
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x10);
+	
+	//USER Load jump address
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER Execute count instruction
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0);
+
+	//USER tINIT3 = 200us
+	delay_for_n_ns(200000);
+
+	//USER indicate that memory is stable 
+	IOWR_32DIRECT (PHY_MGR_RESET_MEM_STBL, 0, 1);
+
+	//USER MRW RESET
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR63_RESET);
+
+	//USER tINIT5 = 10us
+	delay_for_n_ns(10000);
+
+	//USER MRW ZQC
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR10_ZQC);
+    
+	//USER tZQINIT = 1us
+	delay_for_n_ns(1000);
+    
+	//USER MRW MR1
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_CALIB);
+    
+	//USER MRW MR2
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2);
+    
+	//USER MRW MR3
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3);
+}
+#endif // LPDDR2 
+
+//USER  At the end of calibration we have to program the user settings in, and
+//USER  hand off the memory to the user.
+
+#if DDR3
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks ... 
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	//USER load up MR settings specified by user 
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS2);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS3);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS1);
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MRS0_USER);
+}
+#endif // DDR3
+
+#if DDR2
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks ... 
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+
+	//USER load up MR settings specified by user 
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR2);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR3);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_EMR);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR_USER);
+}
+#endif //USER DDR2
+
+#if LPDDR2
+void rw_mgr_mem_handoff (void)
+{
+	//USER precharge all banks...
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+
+	//USER load up MR settings specified by user
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR1_USER);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR2);
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_MR3);
+}
+#endif //USER LPDDR2
+
+//USER load up the patterns we are going to use during a read test 
+void rw_mgr_mem_calibrate_read_load_patterns ()
+{
+	//USER Load up a constant bursts
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x20);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_GUARANTEED_WRITE_WAIT0);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x20);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_GUARANTEED_WRITE_WAIT1);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x02);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_GUARANTEED_WRITE_WAIT2);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x02);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_GUARANTEED_WRITE_WAIT3);
+    
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_GUARANTEED_WRITE);
+}
+
+//USER  try a read and see if it returns correct data back. has dummy reads inserted into the mix
+//USER  used to align dqs enable. has more thorough checks than the regular read test.
+alt_u32 rw_mgr_mem_calibrate_read_test (alt_u32 group, alt_u32 num_tries, alt_u32 all_correct, t_btfld *bit_chk, alt_u32 all_groups)
+{
+	alt_u32 vg;
+	t_btfld correct_mask_vg;
+	t_btfld tmp_bit_chk;
+
+	*bit_chk = param->read_correct_mask;
+	correct_mask_vg = param->read_correct_mask_vg;
+	
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x10);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1);
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x10);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2);
+	
+	if (all_groups) {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x06);
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x32);
+	}
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B);
+	if(all_groups) {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, RW_MGR_MEM_IF_READ_DQS_WIDTH * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1);
+	} else {
+		IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0);
+	}
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B);
+	
+	tmp_bit_chk = 0;
+	for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--)
+	{
+		//USER reset the fifos to get pointers to known state 
+
+		IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0);
+		IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0);	
+
+		tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
+
+		IOWR_32DIRECT (all_groups ? RW_MGR_RUN_ALL_GROUPS : RW_MGR_RUN_SINGLE_GROUP, ((group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS+vg) << 2), __RW_MGR_READ_B2B);
+		tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(IORD_32DIRECT(BASE_RW_MGR, 0)));
+
+		if (vg == 0) {
+			break;
+		}
+	}
+	*bit_chk &= tmp_bit_chk;
+
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, (group << 2), __RW_MGR_CLEAR_DQS_ENABLE);
+	
+	if (all_correct)
+	{
+		return (*bit_chk == param->read_correct_mask);
+	}
+	else
+	{
+		return (*bit_chk != 0x00);
+	}
+}
+
+//USER find a good dqs enable to use 
+alt_u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase (alt_u32 grp)
+{
+	alt_u32 v;
+	alt_u32 p;
+	t_btfld bit_chk;
+	alt_u32 found_vfifo;
+	alt_u32 vfifo_not_found;
+	alt_u32 counter;
+	alt_u32 test_status;
+	alt_u32 fail_to_fail_phase;
+	alt_u32 capture_clk;
+	
+	if (grp == 2) {
+	    capture_clk = 1;
+	} else {
+	    capture_clk = grp;
+	}
+
+	//USER ********************************************************
+	//USER * step 2: find working VFIFO
+	found_vfifo = 0;
+	vfifo_not_found = 0;
+	counter = 0;
+	while (1) {
+	    for (v = 0; v < RTL_VFIFO_SIZE; v++) {
+		    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ALL_BITS, &bit_chk, 0);
+		    
+		    if (test_status) {
+				found_vfifo = 1;
+				break;
+			}
+			
+			IOWR_32DIRECT (PHY_MGR_CMD_INC_VFIFO_HR, 0, grp);
+		}
+		
+		if (found_vfifo) {
+			break;
+		}
+		
+		PLL_INCR(capture_clk << 2);
+		
+		#if LPDDR2
+		PLL_INCR(capture_clk+0x4);
+		#endif
+		
+		// 600 steps of 10ps is one full clock at 167Mhz
+		// 10ps is the PLL phase step resolution
+		// trying this value for now, we know that sometimes we need to sweep two clock due to reset condition of div 2 register
+		counter++;
+		if (counter == 600) {
+		    vfifo_not_found = 1;
+		    break;
+		}
+	}
+	
+	//USER ********************************************************
+	//USER * step 3: decrement phase until read fails
+	
+	while (1) {
+	    if (vfifo_not_found) {
+	        break;
+	    }
+	    
+	    // decrement first because the current phase would work
+	    PLL_DECR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_DECR(capture_clk+0x4);
+        #endif
+	    
+	    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
+	    
+	    if (!test_status) {
+	        break;
+	    }
+	}
+	
+	//USER ********************************************************
+	//USER * step 4: increment phase until read fails to determine window
+	fail_to_fail_phase = 0;
+	while (1) {
+	    if (vfifo_not_found) {
+	        break;
+	    }
+	    
+	    // increment first since the current phase wouldnt work
+	    PLL_INCR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_INCR(capture_clk+0x4);
+        #endif
+	    
+	    fail_to_fail_phase++;
+	    
+	    test_status = rw_mgr_mem_calibrate_read_test (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
+	    
+	    if (!test_status) {
+	        break;
+	    }
+	}
+	
+	//back by half to get best margin
+	for (p = 0; p < (fail_to_fail_phase/2); p++) {
+	    PLL_DECR(capture_clk << 2);
+	    
+	    #if LPDDR2
+        PLL_DECR(capture_clk+0x4);
+        #endif
+	}
+	
+	if (found_vfifo) {
+		return 1;
+	} else {
+	    return 0;
+	}
+}
+
+//USER VFIFO Calibration -- Full Calibration
+alt_u32 rw_mgr_mem_calibrate_vfifo ()
+{
+	rw_mgr_mem_calibrate_read_load_patterns ();
+	
+	int group0=0;
+	int group1=0;
+	
+	#if M10_DQ_WIDTH_8
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=1;
+	#endif
+	
+	#if M10_DQ_WIDTH_16
+	    #if TW0_CAPTURE_CLOCKS
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(1);
+	    #else
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=1;
+	    #endif
+	#endif
+	
+	#if M10_DQ_WIDTH_24
+	group0=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(0);
+	group1=rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(2);
+	#endif
+	
+	if (group0 && group1) {
+		return 1;
+	} else {
+	    return 0;
+	}
+}
+
+//USER precharge all banks and activate row 0 in bank "000..." and bank "111..." 
+void mem_precharge_and_activate (void)
+{
+	//USER precharge all banks ... 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0F);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT1);
+    
+	IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0F);
+	IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2);
+    
+	//USER activate rows 
+	IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1);
+}
+
+//USER Configure various memory related parameters.
+void mem_config (void)
+{
+	alt_u32 wlat;
+
+	//USER read in write and read latency 
+
+	wlat = IORD_32DIRECT (MEM_T_WL_ADD, 0);
+	
+	//USER write latency 
+	wlat = (wlat - 1) / 2 + 1;
+
+	//USER advertise write latency 
+	gbl->curr_write_lat = wlat;
+	IOWR_32DIRECT (PHY_MGR_AFI_WLAT, 0, wlat - 1);
+	
+	mem_precharge_and_activate ();
+}
+
+//USER Memory calibration entry point
+ 
+alt_u32 mem_calibrate (void)
+{
+	// Initialize the data settings
+
+	gbl->error_substage = CAL_SUBSTAGE_NIL;
+	gbl->error_stage = CAL_STAGE_NIL;
+	gbl->error_group = 0xff;
+
+	mem_config ();
+	
+	//USER Calibrate the VFIFO
+	
+	if (!rw_mgr_mem_calibrate_vfifo ()) {
+	    return 0;
+	} else {
+	    return 1;
+	}
+}
+
+alt_u32 run_mem_calibrate(void) {
+	alt_u32 pass;
+
+    initialize();
+	
+    set_rank_and_odt_mask(0);
+    
+	rw_mgr_mem_initialize ();
+
+	pass = mem_calibrate ();
+
+	mem_precharge_and_activate ();
+	
+	IOWR_32DIRECT (PHY_MGR_CMD_FIFO_RESET, 0, 0);
+
+	//USER Handoff
+
+	rw_mgr_mem_handoff ();
+
+	IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0);
+
+	if (pass) {
+
+		IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_SUCCESS);
+
+	} else {
+		
+		IOWR_32DIRECT (PHY_MGR_CAL_STATUS, 0, PHY_MGR_CAL_FAIL);
+	}
+
+	return pass;
+}
+
+int main(void)
+{
+	param_t my_param;
+	gbl_t my_gbl;
+	alt_u32 pass;
+
+	param = &my_param;
+	gbl = &my_gbl;
+
+	IOWR_32DIRECT (RW_MGR_SOFT_RESET, 0, 0);
+
+	pass = run_mem_calibrate ();
+
+	while (1) {
+	}
+
+	return pass;
+}
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
new file mode 100644
index 0000000..26b58af
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mem_if_ddr3_emif_0_s0_software/sequencer_m10.h
@@ -0,0 +1,345 @@
+#ifndef _SEQUENCER_H_
+#define _SEQUENCER_H_
+
+/*
+Copyright (c) 2012, Altera Corporation
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Altera Corporation nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#if ENABLE_ASSERT
+#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s"
+
+extern void err_report_internal_error (const char* description, const char* module, const char* file, int line);
+
+#define ALTERA_INTERNAL_ERROR(string) {err_report_internal_error(string, "SEQ", __FILE__, __LINE__); exit(-1);}
+
+#define ALTERA_ASSERT(condition) \
+    if (!(condition)) { ALTERA_INTERNAL_ERROR(#condition); }
+#define ALTERA_INFO_ASSERT(condition,text) \
+    if (!(condition)) { ALTERA_INTERNAL_ERROR(text); }
+
+#else
+
+#define ALTERA_ASSERT(condition)
+#define ALTERA_INFO_ASSERT(condition,text)
+
+#endif
+
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
+
+#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR
+#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400
+
+#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0010)
+
+#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
+#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
+#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808
+#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C
+
+#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00
+#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04
+#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08
+#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C
+
+#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000
+#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000
+
+#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400
+#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400
+
+#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200
+
+#define RW_MGR_RANK_NONE 0xFF
+#define RW_MGR_RANK_ALL 0x00
+
+#define RW_MGR_ODT_MODE_OFF 0
+#define RW_MGR_ODT_MODE_READ_WRITE 1
+
+#define NUM_CALIB_REPEAT	1
+
+#define NUM_READ_TESTS			7
+#define NUM_READ_PB_TESTS		7
+#define NUM_WRITE_TESTS			15
+#define NUM_WRITE_PB_TESTS		31
+
+#define PASS_ALL_BITS			1
+#define PASS_ONE_BIT			0
+
+/* calibration stages */
+
+#define CAL_STAGE_NIL			0
+#define CAL_STAGE_VFIFO			1
+#define CAL_STAGE_WLEVEL		2
+#define CAL_STAGE_LFIFO			3
+#define CAL_STAGE_WRITES		4
+#define CAL_STAGE_FULLTEST		5
+#define CAL_STAGE_REFRESH		6
+#define CAL_STAGE_CAL_SKIPPED		7
+#define CAL_STAGE_CAL_ABORTED		8
+#define CAL_STAGE_VFIFO_AFTER_WRITES	9
+
+/* calibration substages */
+
+#define CAL_SUBSTAGE_NIL		0
+#define CAL_SUBSTAGE_GUARANTEED_READ	1
+#define CAL_SUBSTAGE_DQS_EN_PHASE	2
+#define CAL_SUBSTAGE_VFIFO_CENTER	3
+#define CAL_SUBSTAGE_WORKING_DELAY	1
+#define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
+#define CAL_SUBSTAGE_WLEVEL_COPY	3
+#define CAL_SUBSTAGE_WRITES_CENTER	1
+#define CAL_SUBSTAGE_READ_LATENCY	1
+#define CAL_SUBSTAGE_REFRESH		1
+
+#define MAX_RANKS			(RW_MGR_MEM_NUMBER_OF_RANKS)
+#define MAX_DQS				(RW_MGR_MEM_IF_WRITE_DQS_WIDTH > RW_MGR_MEM_IF_READ_DQS_WIDTH ? RW_MGR_MEM_IF_WRITE_DQS_WIDTH : RW_MGR_MEM_IF_READ_DQS_WIDTH)
+#define MAX_DQ				(RW_MGR_MEM_DATA_WIDTH)
+#define MAX_DM				(RW_MGR_MEM_DATA_MASK_WIDTH)
+
+/* length of VFIFO, from SW_MACROS */
+#define VFIFO_SIZE			(READ_VALID_FIFO_SIZE)
+
+/* Memory for data transfer between TCL scripts and NIOS.
+ *
+ * - First word is a command request.
+ * - The remaining words are part of the transfer.
+ */
+
+/* Define the base address of each manager. */
+
+/* MarkW: how should these base addresses be done for A-V? */
+#define BASE_PTR_MGR 					SEQUENCER_PTR_MGR_INST_BASE
+#define BASE_PHY_MGR 					SEQUENCER_PHY_MGR_INST_BASE
+#define BASE_RW_MGR  					SEQUENCER_RW_MGR_INST_BASE
+#define BASE_DATA_MGR					SEQUENCER_DATA_MGR_INST_BASE
+#define BASE_PLL_MGR					0x00058000 /* Aidil - todo */
+#define BASE_REG_FILE					SEQUENCER_REG_FILE_INST_BASE
+#define BASE_TIMER					SEQUENCER_TIMER_INST_BASE
+#define BASE_MMR                                        (0x000C0000)
+#define BASE_TRK_MGR					(0x000D0000)
+
+/* Register file addresses. */
+#define REG_FILE_SIGNATURE				(BASE_REG_FILE + 0x0000)
+#define REG_FILE_DEBUG_DATA_ADDR		(BASE_REG_FILE + 0x0004)
+#define REG_FILE_CUR_STAGE              (BASE_REG_FILE + 0x0008)
+#define REG_FILE_FOM                    (BASE_REG_FILE + 0x000C)
+#define REG_FILE_FAILING_STAGE          (BASE_REG_FILE + 0x0010)
+#define REG_FILE_DEBUG1                 (BASE_REG_FILE + 0x0014)
+#define REG_FILE_DEBUG2                 (BASE_REG_FILE + 0x0018)
+
+#if TRACKING_WATCH_TEST || TRACKING_ERROR_TEST
+#define REG_FILE_TRK_SAMPLE_CHECK	(BASE_REG_FILE + 0x003C)
+#elif MARGIN_VARIATION_TEST
+#define IO_DQS_EN_DELAY_OFFSET		(IORD_32DIRECT(BASE_REG_FILE + 0x003C, 0))
+#endif
+
+/* Tracking slave addresses. */
+#define TRK_DTAPS_PER_PTAP     (BASE_TRK_MGR + 0x0000)
+#define TRK_SAMPLE_COUNT       (BASE_TRK_MGR + 0x0004)
+#define TRK_LONGIDLE           (BASE_TRK_MGR + 0x0008)
+#define TRK_DELAYS             (BASE_TRK_MGR + 0x000C)
+#define TRK_RW_MGR_ADDR        (BASE_TRK_MGR + 0x0010)
+#define TRK_READ_DQS_WIDTH     (BASE_TRK_MGR + 0x0014)
+#define TRK_RFSH               (BASE_TRK_MGR + 0x0018)
+#define TRK_STALL              (BASE_TRK_MGR + 0x001C)
+#define TRK_V_POINTER          (BASE_TRK_MGR + 0x0020)
+
+#define TRK_STALL_REQ_VAL      (0x1)
+#define TRK_STALL_ACKED_VAL    (0x80000000 | TRK_STALL_REQ_VAL)
+
+/* PHY manager configuration registers. */
+
+#define PHY_MGR_PHY_RLAT				(BASE_PHY_MGR + 0x4000)
+#define PHY_MGR_RESET_MEM_STBL			(BASE_PHY_MGR + 0x4004)
+#define PHY_MGR_MUX_SEL					(BASE_PHY_MGR + 0x4008)
+#define PHY_MGR_CAL_STATUS				(BASE_PHY_MGR + 0x400c)
+#define PHY_MGR_CAL_DEBUG_INFO			(BASE_PHY_MGR + 0x4010)
+#define PHY_MGR_VFIFO_RD_EN_OVRD		(BASE_PHY_MGR + 0x4014)
+#if CALIBRATE_BIT_SLIPS
+#define PHY_MGR_FR_SHIFT				(BASE_PHY_MGR + 0x4020)
+#define PHY_MGR_AFI_WLAT				(BASE_PHY_MGR + 0x4018)
+#else
+#define PHY_MGR_AFI_WLAT				(BASE_PHY_MGR + 0x4018)
+#endif
+#define PHY_MGR_AFI_RLAT				(BASE_PHY_MGR + 0x401c)
+
+#define PHY_MGR_CAL_SUCCESS				(1)
+#define PHY_MGR_CAL_FAIL				(2)
+
+/* PHY manager command addresses. */
+
+#define PHY_MGR_CMD_INC_VFIFO_FR		(BASE_PHY_MGR + 0x0000)
+#define PHY_MGR_CMD_INC_VFIFO_HR		(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY	(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_CMD_FIFO_RESET			(BASE_PHY_MGR + 0x0008)
+#define PHY_MGR_CMD_INC_VFIFO_FR_HR		(BASE_PHY_MGR + 0x000C)
+#define PHY_MGR_CMD_INC_VFIFO_QR		(BASE_PHY_MGR + 0x0010)
+
+/* PHY manager parameters. */
+
+#define PHY_MGR_MAX_RLAT_WIDTH			(BASE_PHY_MGR + 0x0000)
+#define PHY_MGR_MAX_AFI_WLAT_WIDTH 		(BASE_PHY_MGR + 0x0004)
+#define PHY_MGR_MAX_AFI_RLAT_WIDTH 		(BASE_PHY_MGR + 0x0008)
+#define PHY_MGR_CALIB_SKIP_STEPS		(BASE_PHY_MGR + 0x000c)
+#define PHY_MGR_CALIB_VFIFO_OFFSET		(BASE_PHY_MGR + 0x0010)
+#define PHY_MGR_CALIB_LFIFO_OFFSET		(BASE_PHY_MGR + 0x0014)
+#define PHY_MGR_RDIMM					(BASE_PHY_MGR + 0x0018)
+#define PHY_MGR_MEM_T_WL				(BASE_PHY_MGR + 0x001c)
+#define PHY_MGR_MEM_T_RL				(BASE_PHY_MGR + 0x0020)
+
+/* Data Manager */
+#define DATA_MGR_DRAM_CFG				(BASE_DATA_MGR + 0x0000)
+#define DATA_MGR_MEM_T_WL				(BASE_DATA_MGR + 0x0004)
+#define DATA_MGR_MEM_T_ADD				(BASE_DATA_MGR + 0x0008)
+#define DATA_MGR_MEM_T_RL				(BASE_DATA_MGR + 0x000C)
+#define DATA_MGR_MEM_T_RFC				(BASE_DATA_MGR + 0x0010)
+#define DATA_MGR_MEM_T_REFI				(BASE_DATA_MGR + 0x0014)
+#define DATA_MGR_MEM_T_WR				(BASE_DATA_MGR + 0x0018)
+#define DATA_MGR_MEM_T_MRD				(BASE_DATA_MGR + 0x001C)
+#define DATA_MGR_COL_WIDTH				(BASE_DATA_MGR + 0x0020)
+#define DATA_MGR_ROW_WIDTH				(BASE_DATA_MGR + 0x0024)
+#define DATA_MGR_BANK_WIDTH				(BASE_DATA_MGR + 0x0028)
+#define DATA_MGR_CS_WIDTH				(BASE_DATA_MGR + 0x002C)
+#define DATA_MGR_ITF_WIDTH				(BASE_DATA_MGR + 0x0030)
+#define DATA_MGR_DVC_WIDTH				(BASE_DATA_MGR + 0x0034)
+
+#define MEM_T_WL_ADD PHY_MGR_MEM_T_WL
+#define MEM_T_RL_ADD PHY_MGR_MEM_T_RL
+
+#define CALIB_SKIP_DELAY_LOOPS			(1 << 0)
+#define CALIB_SKIP_ALL_BITS_CHK			(1 << 1)
+#define CALIB_SKIP_DELAY_SWEEPS			(1 << 2)
+#define CALIB_SKIP_VFIFO				(1 << 3)
+#define CALIB_SKIP_LFIFO				(1 << 4)
+#define CALIB_SKIP_WLEVEL				(1 << 5)
+#define CALIB_SKIP_WRITES				(1 << 6)
+#define CALIB_SKIP_FULL_TEST			(1 << 7)
+#define CALIB_SKIP_ALL					(CALIB_SKIP_VFIFO | CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
+#define CALIB_IN_RTL_SIM				(1 << 8)
+
+// PHY Debug mode flag constants
+#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
+#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
+#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
+#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
+#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
+#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
+
+/* PLL manager command addresses */
+
+#define PLL_INCR(group)	IOWR_32DIRECT(BASE_PLL_MGR, group, 0x1)
+#define PLL_DECR(group)	IOWR_32DIRECT(BASE_PLL_MGR, group, 0x0)
+#define RTL_VFIFO_SIZE  8
+
+/* Bitfield type changes depending on protocol */
+typedef alt_u32 t_btfld;
+
+#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
+#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
+
+extern const alt_u32 inst_rom_init_size;
+extern const alt_u32 inst_rom_init[];
+extern const alt_u32 ac_rom_init_size;
+extern const alt_u32 ac_rom_init[];
+
+
+
+/* parameter variable holder */
+
+typedef struct param_type {
+	t_btfld dm_correct_mask;
+	t_btfld read_correct_mask;
+	t_btfld read_correct_mask_vg;
+	t_btfld write_correct_mask;
+	t_btfld write_correct_mask_vg;	
+
+	/* set a particular entry to 1 if we need to skip a particular rank */
+
+	alt_u32 skip_ranks[MAX_RANKS];
+
+	/* set a particular entry to 1 if we need to skip a particular group */
+
+	alt_u32 skip_groups;
+	
+	/* set a particular entry to 1 if the shadow register (which represents a set of ranks) needs to be skipped */
+	
+	alt_u32 skip_shadow_regs[NUM_SHADOW_REGS];
+
+} param_t;
+
+
+/* global variable holder */
+
+typedef struct gbl_type {
+
+	alt_u32 phy_debug_mode_flags;
+
+	/* current read latency */
+
+	alt_u32 curr_read_lat;
+	
+	/* current write latency */
+	
+	alt_u32 curr_write_lat;
+
+	/* error code */
+
+	alt_u32 error_substage;
+	alt_u32 error_stage;
+	alt_u32 error_group;
+
+	/* figure-of-merit in, figure-of-merit out */
+
+	alt_u32 fom_in;
+	alt_u32 fom_out;
+
+	//USER Number of RW Mgr NOP cycles between write command and write data
+#if MULTIPLE_AFI_WLAT
+	alt_u32 rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
+#endif
+	alt_u32 rw_wl_nop_cycles;
+} gbl_t;
+
+// External global variables
+extern gbl_t *gbl;
+extern param_t *param;
+
+// External functions
+alt_u32 rw_mgr_mem_calibrate_full_test (alt_u32 min_correct, t_btfld *bit_chk, alt_u32 test_dm);
+extern alt_u32 run_mem_calibrate (void);
+extern void rw_mgr_mem_calibrate_eye_diag_aid (void);
+extern void rw_mgr_load_mrs_calib (void);
+extern void rw_mgr_load_mrs_exec (void);
+extern void rw_mgr_mem_initialize (void);
+extern void rw_mgr_mem_dll_lock_wait(void);
+#if HPS_HW
+extern int sdram_calibration(void);
+#endif
+#endif
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v
new file mode 100644
index 0000000..ab8cb2b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v
@@ -0,0 +1,161 @@
+// q_sys_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0 (
+		input  wire        sys_clk_clk_clk,                                        //                                sys_clk_clk.clk
+		input  wire        sensor_interface_rst_reset_bridge_in_reset_reset,       // sensor_interface_rst_reset_bridge_in_reset.reset
+		input  wire [8:0]  sensor_interface_calibration_ram_interface_address,     // sensor_interface_calibration_ram_interface.address
+		output wire        sensor_interface_calibration_ram_interface_waitrequest, //                                           .waitrequest
+		input  wire        sensor_interface_calibration_ram_interface_read,        //                                           .read
+		output wire [15:0] sensor_interface_calibration_ram_interface_readdata,    //                                           .readdata
+		output wire [8:0]  calibration_ram_s2_address,                             //                         calibration_ram_s2.address
+		output wire        calibration_ram_s2_write,                               //                                           .write
+		input  wire [15:0] calibration_ram_s2_readdata,                            //                                           .readdata
+		output wire [15:0] calibration_ram_s2_writedata,                           //                                           .writedata
+		output wire [1:0]  calibration_ram_s2_byteenable,                          //                                           .byteenable
+		output wire        calibration_ram_s2_chipselect,                          //                                           .chipselect
+		output wire        calibration_ram_s2_clken                                //                                           .clken
+	);
+
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_waitrequest;   // calibration_ram_s2_translator:uav_waitrequest -> sensor_interface_calibration_ram_interface_translator:uav_waitrequest
+	wire  [15:0] sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdata;      // calibration_ram_s2_translator:uav_readdata -> sensor_interface_calibration_ram_interface_translator:uav_readdata
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_debugaccess;   // sensor_interface_calibration_ram_interface_translator:uav_debugaccess -> calibration_ram_s2_translator:uav_debugaccess
+	wire   [9:0] sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_address;       // sensor_interface_calibration_ram_interface_translator:uav_address -> calibration_ram_s2_translator:uav_address
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_read;          // sensor_interface_calibration_ram_interface_translator:uav_read -> calibration_ram_s2_translator:uav_read
+	wire   [1:0] sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_byteenable;    // sensor_interface_calibration_ram_interface_translator:uav_byteenable -> calibration_ram_s2_translator:uav_byteenable
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdatavalid; // calibration_ram_s2_translator:uav_readdatavalid -> sensor_interface_calibration_ram_interface_translator:uav_readdatavalid
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_lock;          // sensor_interface_calibration_ram_interface_translator:uav_lock -> calibration_ram_s2_translator:uav_lock
+	wire         sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_write;         // sensor_interface_calibration_ram_interface_translator:uav_write -> calibration_ram_s2_translator:uav_write
+	wire  [15:0] sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_writedata;     // sensor_interface_calibration_ram_interface_translator:uav_writedata -> calibration_ram_s2_translator:uav_writedata
+	wire   [1:0] sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_burstcount;    // sensor_interface_calibration_ram_interface_translator:uav_burstcount -> calibration_ram_s2_translator:uav_burstcount
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (9),
+		.AV_DATA_W                   (16),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (2),
+		.UAV_ADDRESS_W               (10),
+		.UAV_BURSTCOUNT_W            (2),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (2),
+		.AV_ADDRESS_SYMBOLS          (0),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) sensor_interface_calibration_ram_interface_translator (
+		.clk                    (sys_clk_clk_clk),                                                                               //                       clk.clk
+		.reset                  (sensor_interface_rst_reset_bridge_in_reset_reset),                                              //                     reset.reset
+		.uav_address            (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (sensor_interface_calibration_ram_interface_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (sensor_interface_calibration_ram_interface_waitrequest),                                        //                          .waitrequest
+		.av_read                (sensor_interface_calibration_ram_interface_read),                                               //                          .read
+		.av_readdata            (sensor_interface_calibration_ram_interface_readdata),                                           //                          .readdata
+		.av_burstcount          (1'b1),                                                                                          //               (terminated)
+		.av_byteenable          (2'b11),                                                                                         //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                                          //               (terminated)
+		.av_begintransfer       (1'b0),                                                                                          //               (terminated)
+		.av_chipselect          (1'b0),                                                                                          //               (terminated)
+		.av_readdatavalid       (),                                                                                              //               (terminated)
+		.av_write               (1'b0),                                                                                          //               (terminated)
+		.av_writedata           (16'b0000000000000000),                                                                          //               (terminated)
+		.av_lock                (1'b0),                                                                                          //               (terminated)
+		.av_debugaccess         (1'b0),                                                                                          //               (terminated)
+		.uav_clken              (),                                                                                              //               (terminated)
+		.av_clken               (1'b1),                                                                                          //               (terminated)
+		.uav_response           (2'b00),                                                                                         //               (terminated)
+		.av_response            (),                                                                                              //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                                          //               (terminated)
+		.av_writeresponsevalid  ()                                                                                               //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (9),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (16),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (2),
+		.UAV_BYTEENABLE_W               (2),
+		.UAV_ADDRESS_W                  (10),
+		.UAV_BURSTCOUNT_W               (2),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (2),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) calibration_ram_s2_translator (
+		.clk                    (sys_clk_clk_clk),                                                                               //                      clk.clk
+		.reset                  (sensor_interface_rst_reset_bridge_in_reset_reset),                                              //                    reset.reset
+		.uav_address            (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
+		.uav_read               (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_read),          //                         .read
+		.uav_write              (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_write),         //                         .write
+		.uav_waitrequest        (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
+		.uav_readdata           (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_readdata),      //                         .readdata
+		.uav_writedata          (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_writedata),     //                         .writedata
+		.uav_lock               (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_lock),          //                         .lock
+		.uav_debugaccess        (sensor_interface_calibration_ram_interface_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
+		.av_address             (calibration_ram_s2_address),                                                                    //      avalon_anti_slave_0.address
+		.av_write               (calibration_ram_s2_write),                                                                      //                         .write
+		.av_readdata            (calibration_ram_s2_readdata),                                                                   //                         .readdata
+		.av_writedata           (calibration_ram_s2_writedata),                                                                  //                         .writedata
+		.av_byteenable          (calibration_ram_s2_byteenable),                                                                 //                         .byteenable
+		.av_chipselect          (calibration_ram_s2_chipselect),                                                                 //                         .chipselect
+		.av_clken               (calibration_ram_s2_clken),                                                                      //                         .clken
+		.av_read                (),                                                                                              //              (terminated)
+		.av_begintransfer       (),                                                                                              //              (terminated)
+		.av_beginbursttransfer  (),                                                                                              //              (terminated)
+		.av_burstcount          (),                                                                                              //              (terminated)
+		.av_readdatavalid       (1'b0),                                                                                          //              (terminated)
+		.av_waitrequest         (1'b0),                                                                                          //              (terminated)
+		.av_writebyteenable     (),                                                                                              //              (terminated)
+		.av_lock                (),                                                                                              //              (terminated)
+		.uav_clken              (1'b0),                                                                                          //              (terminated)
+		.av_debugaccess         (),                                                                                              //              (terminated)
+		.av_outputenable        (),                                                                                              //              (terminated)
+		.uav_response           (),                                                                                              //              (terminated)
+		.av_response            (2'b00),                                                                                         //              (terminated)
+		.uav_writeresponsevalid (),                                                                                              //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                                                           //              (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
new file mode 100644
index 0000000..b5984bd
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_0_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010.v
new file mode 100644
index 0000000..1a45b3c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_0_avalon_st_adapter_010.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0_avalon_st_adapter_010 #(
+		parameter inBitsPerSymbol = 130,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 130,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 130,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire         in_clk_0_clk,   // in_clk_0.clk
+		input  wire         in_rst_0_reset, // in_rst_0.reset
+		input  wire [129:0] in_0_data,      //     in_0.data
+		input  wire         in_0_valid,     //         .valid
+		output wire         in_0_ready,     //         .ready
+		output wire [129:0] out_0_data,     //    out_0.data
+		output wire         out_0_valid,    //         .valid
+		input  wire         out_0_ready,    //         .ready
+		output wire [0:0]   out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0.sv
new file mode 100644
index 0000000..7c5df1b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         130
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [130-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [130-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012.v
new file mode 100644
index 0000000..4cbf024
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_0_avalon_st_adapter_012.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0_avalon_st_adapter_012 #(
+		parameter inBitsPerSymbol = 130,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 130,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 130,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire         in_clk_0_clk,   // in_clk_0.clk
+		input  wire         in_rst_0_reset, // in_rst_0.reset
+		input  wire [129:0] in_0_data,      //     in_0.data
+		input  wire         in_0_valid,     //         .valid
+		output wire         in_0_ready,     //         .ready
+		output wire [129:0] out_0_data,     //    out_0.data
+		output wire         out_0_valid,    //         .valid
+		input  wire         out_0_ready,    //         .ready
+		output wire [0:0]   out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0.sv
new file mode 100644
index 0000000..2fac6b2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         130
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [130-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [130-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013.v
new file mode 100644
index 0000000..3510d48
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_0_avalon_st_adapter_013.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0_avalon_st_adapter_013 #(
+		parameter inBitsPerSymbol = 130,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 130,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 130,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire         in_clk_0_clk,   // in_clk_0.clk
+		input  wire         in_rst_0_reset, // in_rst_0.reset
+		input  wire [129:0] in_0_data,      //     in_0.data
+		input  wire         in_0_valid,     //         .valid
+		output wire         in_0_ready,     //         .ready
+		output wire [129:0] out_0_data,     //    out_0.data
+		output wire         out_0_valid,    //         .valid
+		input  wire         out_0_ready,    //         .ready
+		output wire [0:0]   out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 130)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0.sv
new file mode 100644
index 0000000..f8efede
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         130
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_0_avalon_st_adapter_013_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [130-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [130-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020.v
new file mode 100644
index 0000000..ff509fe
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_0_avalon_st_adapter_020.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_0_avalon_st_adapter_020 #(
+		parameter inBitsPerSymbol = 18,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 18,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 18,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [17:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [17:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0.sv
new file mode 100644
index 0000000..518f643
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         18
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_0_avalon_st_adapter_020_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [18-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [18-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..3971bd1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
new file mode 100644
index 0000000..034787c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         22
+//   VALID_WIDTH:         22
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [22-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src4_channel, // ST_CHANNEL_W=22
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+    output reg                      src5_valid,
+    output reg [121-1    : 0] src5_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src5_channel, // ST_CHANNEL_W=22
+    output reg                      src5_startofpacket,
+    output reg                      src5_endofpacket,
+    input                           src5_ready,
+
+    output reg                      src6_valid,
+    output reg [121-1    : 0] src6_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src6_channel, // ST_CHANNEL_W=22
+    output reg                      src6_startofpacket,
+    output reg                      src6_endofpacket,
+    input                           src6_ready,
+
+    output reg                      src7_valid,
+    output reg [121-1    : 0] src7_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src7_channel, // ST_CHANNEL_W=22
+    output reg                      src7_startofpacket,
+    output reg                      src7_endofpacket,
+    input                           src7_ready,
+
+    output reg                      src8_valid,
+    output reg [121-1    : 0] src8_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src8_channel, // ST_CHANNEL_W=22
+    output reg                      src8_startofpacket,
+    output reg                      src8_endofpacket,
+    input                           src8_ready,
+
+    output reg                      src9_valid,
+    output reg [121-1    : 0] src9_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src9_channel, // ST_CHANNEL_W=22
+    output reg                      src9_startofpacket,
+    output reg                      src9_endofpacket,
+    input                           src9_ready,
+
+    output reg                      src10_valid,
+    output reg [121-1    : 0] src10_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src10_channel, // ST_CHANNEL_W=22
+    output reg                      src10_startofpacket,
+    output reg                      src10_endofpacket,
+    input                           src10_ready,
+
+    output reg                      src11_valid,
+    output reg [121-1    : 0] src11_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src11_channel, // ST_CHANNEL_W=22
+    output reg                      src11_startofpacket,
+    output reg                      src11_endofpacket,
+    input                           src11_ready,
+
+    output reg                      src12_valid,
+    output reg [121-1    : 0] src12_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src12_channel, // ST_CHANNEL_W=22
+    output reg                      src12_startofpacket,
+    output reg                      src12_endofpacket,
+    input                           src12_ready,
+
+    output reg                      src13_valid,
+    output reg [121-1    : 0] src13_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src13_channel, // ST_CHANNEL_W=22
+    output reg                      src13_startofpacket,
+    output reg                      src13_endofpacket,
+    input                           src13_ready,
+
+    output reg                      src14_valid,
+    output reg [121-1    : 0] src14_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src14_channel, // ST_CHANNEL_W=22
+    output reg                      src14_startofpacket,
+    output reg                      src14_endofpacket,
+    input                           src14_ready,
+
+    output reg                      src15_valid,
+    output reg [121-1    : 0] src15_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src15_channel, // ST_CHANNEL_W=22
+    output reg                      src15_startofpacket,
+    output reg                      src15_endofpacket,
+    input                           src15_ready,
+
+    output reg                      src16_valid,
+    output reg [121-1    : 0] src16_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src16_channel, // ST_CHANNEL_W=22
+    output reg                      src16_startofpacket,
+    output reg                      src16_endofpacket,
+    input                           src16_ready,
+
+    output reg                      src17_valid,
+    output reg [121-1    : 0] src17_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src17_channel, // ST_CHANNEL_W=22
+    output reg                      src17_startofpacket,
+    output reg                      src17_endofpacket,
+    input                           src17_ready,
+
+    output reg                      src18_valid,
+    output reg [121-1    : 0] src18_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src18_channel, // ST_CHANNEL_W=22
+    output reg                      src18_startofpacket,
+    output reg                      src18_endofpacket,
+    input                           src18_ready,
+
+    output reg                      src19_valid,
+    output reg [121-1    : 0] src19_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src19_channel, // ST_CHANNEL_W=22
+    output reg                      src19_startofpacket,
+    output reg                      src19_endofpacket,
+    input                           src19_ready,
+
+    output reg                      src20_valid,
+    output reg [121-1    : 0] src20_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src20_channel, // ST_CHANNEL_W=22
+    output reg                      src20_startofpacket,
+    output reg                      src20_endofpacket,
+    input                           src20_ready,
+
+    output reg                      src21_valid,
+    output reg [121-1    : 0] src21_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src21_channel, // ST_CHANNEL_W=22
+    output reg                      src21_startofpacket,
+    output reg                      src21_endofpacket,
+    input                           src21_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 22;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid[2];
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid[3];
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid[4];
+
+        src5_data          = sink_data;
+        src5_startofpacket = sink_startofpacket;
+        src5_endofpacket   = sink_endofpacket;
+        src5_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src5_valid         = sink_channel[5] && sink_valid[5];
+
+        src6_data          = sink_data;
+        src6_startofpacket = sink_startofpacket;
+        src6_endofpacket   = sink_endofpacket;
+        src6_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src6_valid         = sink_channel[6] && sink_valid[6];
+
+        src7_data          = sink_data;
+        src7_startofpacket = sink_startofpacket;
+        src7_endofpacket   = sink_endofpacket;
+        src7_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src7_valid         = sink_channel[7] && sink_valid[7];
+
+        src8_data          = sink_data;
+        src8_startofpacket = sink_startofpacket;
+        src8_endofpacket   = sink_endofpacket;
+        src8_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src8_valid         = sink_channel[8] && sink_valid[8];
+
+        src9_data          = sink_data;
+        src9_startofpacket = sink_startofpacket;
+        src9_endofpacket   = sink_endofpacket;
+        src9_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src9_valid         = sink_channel[9] && sink_valid[9];
+
+        src10_data          = sink_data;
+        src10_startofpacket = sink_startofpacket;
+        src10_endofpacket   = sink_endofpacket;
+        src10_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src10_valid         = sink_channel[10] && sink_valid[10];
+
+        src11_data          = sink_data;
+        src11_startofpacket = sink_startofpacket;
+        src11_endofpacket   = sink_endofpacket;
+        src11_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src11_valid         = sink_channel[11] && sink_valid[11];
+
+        src12_data          = sink_data;
+        src12_startofpacket = sink_startofpacket;
+        src12_endofpacket   = sink_endofpacket;
+        src12_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src12_valid         = sink_channel[12] && sink_valid[12];
+
+        src13_data          = sink_data;
+        src13_startofpacket = sink_startofpacket;
+        src13_endofpacket   = sink_endofpacket;
+        src13_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src13_valid         = sink_channel[13] && sink_valid[13];
+
+        src14_data          = sink_data;
+        src14_startofpacket = sink_startofpacket;
+        src14_endofpacket   = sink_endofpacket;
+        src14_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src14_valid         = sink_channel[14] && sink_valid[14];
+
+        src15_data          = sink_data;
+        src15_startofpacket = sink_startofpacket;
+        src15_endofpacket   = sink_endofpacket;
+        src15_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src15_valid         = sink_channel[15] && sink_valid[15];
+
+        src16_data          = sink_data;
+        src16_startofpacket = sink_startofpacket;
+        src16_endofpacket   = sink_endofpacket;
+        src16_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src16_valid         = sink_channel[16] && sink_valid[16];
+
+        src17_data          = sink_data;
+        src17_startofpacket = sink_startofpacket;
+        src17_endofpacket   = sink_endofpacket;
+        src17_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src17_valid         = sink_channel[17] && sink_valid[17];
+
+        src18_data          = sink_data;
+        src18_startofpacket = sink_startofpacket;
+        src18_endofpacket   = sink_endofpacket;
+        src18_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src18_valid         = sink_channel[18] && sink_valid[18];
+
+        src19_data          = sink_data;
+        src19_startofpacket = sink_startofpacket;
+        src19_endofpacket   = sink_endofpacket;
+        src19_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src19_valid         = sink_channel[19] && sink_valid[19];
+
+        src20_data          = sink_data;
+        src20_startofpacket = sink_startofpacket;
+        src20_endofpacket   = sink_endofpacket;
+        src20_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src20_valid         = sink_channel[20] && sink_valid[20];
+
+        src21_data          = sink_data;
+        src21_startofpacket = sink_startofpacket;
+        src21_endofpacket   = sink_endofpacket;
+        src21_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src21_valid         = sink_channel[21] && sink_valid[21];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+    assign ready_vector[5] = src5_ready;
+    assign ready_vector[6] = src6_ready;
+    assign ready_vector[7] = src7_ready;
+    assign ready_vector[8] = src8_ready;
+    assign ready_vector[9] = src9_ready;
+    assign ready_vector[10] = src10_ready;
+    assign ready_vector[11] = src11_ready;
+    assign ready_vector[12] = src12_ready;
+    assign ready_vector[13] = src13_ready;
+    assign ready_vector[14] = src14_ready;
+    assign ready_vector[15] = src15_ready;
+    assign ready_vector[16] = src16_ready;
+    assign ready_vector[17] = src17_ready;
+    assign ready_vector[18] = src18_ready;
+    assign ready_vector[19] = src19_ready;
+    assign ready_vector[20] = src20_ready;
+    assign ready_vector[21] = src21_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
new file mode 100644
index 0000000..2fda173
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_001.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_001
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         22
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_001
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [22-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid[2];
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid[3];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{18{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
new file mode 100644
index 0000000..fbf5d24
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_002.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_002
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_002
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{21{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_003.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_003.sv
new file mode 100644
index 0000000..6aa6701
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_003.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_003
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_003
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{20{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_004.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_004.sv
new file mode 100644
index 0000000..1a0a0f9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_004.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_004
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_004
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{21{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_005.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_005.sv
new file mode 100644
index 0000000..ffbad8a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_005.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_005
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         21
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_005
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [21-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid[2];
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid[3];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_006.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_006.sv
new file mode 100644
index 0000000..af4f537
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_006.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_006
+//   ST_DATA_W:           119
+//   ST_CHANNEL_W:        16
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         16
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_006
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [16-1      : 0]   sink_valid,
+    input  [119-1    : 0]   sink_data, // ST_DATA_W=119
+    input  [16-1 : 0]   sink_channel, // ST_CHANNEL_W=16
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [119-1    : 0] src0_data, // ST_DATA_W=119
+    output reg [16-1 : 0] src0_channel, // ST_CHANNEL_W=16
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [119-1    : 0] src1_data, // ST_DATA_W=119
+    output reg [16-1 : 0] src1_channel, // ST_CHANNEL_W=16
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{14{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_007.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_007.sv
new file mode 100644
index 0000000..b6e4827
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_demux_007.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_demux_007
+//   ST_DATA_W:           119
+//   ST_CHANNEL_W:        16
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_demux_007
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [119-1    : 0]   sink_data, // ST_DATA_W=119
+    input  [16-1 : 0]   sink_channel, // ST_CHANNEL_W=16
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [119-1    : 0] src0_data, // ST_DATA_W=119
+    output reg [16-1 : 0] src0_channel, // ST_CHANNEL_W=16
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [119-1    : 0] src1_data, // ST_DATA_W=119
+    output reg [16-1 : 0] src1_channel, // ST_CHANNEL_W=16
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{14{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
new file mode 100644
index 0000000..9c12703
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux.sv
@@ -0,0 +1,408 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [22-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [22-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [22-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
new file mode 100644
index 0000000..d1370f3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_001.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_001
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_001
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
new file mode 100644
index 0000000..c18f2a8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_002.sv
@@ -0,0 +1,366 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_002
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_002
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [22-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_003.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_003.sv
new file mode 100644
index 0000000..997871a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_003.sv
@@ -0,0 +1,366 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_003
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_003
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_004.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_004.sv
new file mode 100644
index 0000000..7bae86e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_004.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_004
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_004
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
new file mode 100644
index 0000000..b8e1944
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_010.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_010
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      72 (arbitration locking enabled)
+//   ST_DATA_W:           122
+//   ST_CHANNEL_W:        14
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_010
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [122-1   : 0]  sink0_data,
+    input [14-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [122-1   : 0]  sink1_data,
+    input [14-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [122-1   : 0]  sink2_data,
+    input [14-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [122-1   : 0]  sink3_data,
+    input [14-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [122-1   : 0]  sink4_data,
+    input [14-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [122-1    : 0] src_data,
+    output [14-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 122 + 14 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 122;
+    localparam ST_CHANNEL_W     = 14;
+    localparam PKT_TRANS_LOCK   = 72;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[72];
+      lock[1] = sink1_data[72];
+      lock[2] = sink2_data[72];
+      lock[3] = sink3_data[72];
+      lock[4] = sink4_data[72];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_012.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_012.sv
new file mode 100644
index 0000000..ddda47d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_012.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_012
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        18
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_012
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [18-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [18-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [18-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [18-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [18-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [18-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 18 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 18;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_013.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_013.sv
new file mode 100644
index 0000000..6bbe23f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_013.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_013
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        18
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_013
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [18-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [18-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [18-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [18-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [18-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [18-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 18 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 18;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv
new file mode 100644
index 0000000..8517d39
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_014.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_014
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_014
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [22-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [22-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [22-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [22-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_015.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_015.sv
new file mode 100644
index 0000000..c2387a7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_015.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_015
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_015
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [21-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_016.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_016.sv
new file mode 100644
index 0000000..852858a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_cmd_mux_016.sv
@@ -0,0 +1,450 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_cmd_mux_016
+//   NUM_INPUTS:          6
+//   ARBITRATION_SHARES:  1 1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_cmd_mux_016
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [21-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+    input                       sink5_valid,
+    input [121-1   : 0]  sink5_data,
+    input [21-1: 0]  sink5_channel,
+    input                       sink5_startofpacket,
+    input                       sink5_endofpacket,
+    output                      sink5_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 6;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+    wire [PAYLOAD_W - 1 : 0] sink5_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+    assign valid[5] = sink5_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+    assign eop[5] = sink5_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+      lock[5] = sink5_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+    // 5      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+    share_5 & { SHARE_COUNTER_W {next_grant[5]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+    wire final_packet_5 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_5,
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+    assign sink5_ready = src_ready && grant[5];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} } |
+      sink5_payload & {PAYLOAD_W {grant[5]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+    assign sink5_payload = {sink5_channel,sink5_data,
+    sink5_startofpacket,sink5_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv
new file mode 100644
index 0000000..a96b6ae
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router.sv
@@ -0,0 +1,372 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    localparam PAD1 = log2ceil(64'h18000000 - 64'h14000000); 
+    localparam PAD2 = log2ceil(64'h18400000 - 64'h18200000); 
+    localparam PAD3 = log2ceil(64'h18402000 - 64'h18400000); 
+    localparam PAD4 = log2ceil(64'h18403000 - 64'h18402800); 
+    localparam PAD5 = log2ceil(64'h18403400 - 64'h18403000); 
+    localparam PAD6 = log2ceil(64'h18403800 - 64'h18403400); 
+    localparam PAD7 = log2ceil(64'h18403c00 - 64'h18403800); 
+    localparam PAD8 = log2ceil(64'h18403c20 - 64'h18403c00); 
+    localparam PAD9 = log2ceil(64'h18403c40 - 64'h18403c20); 
+    localparam PAD10 = log2ceil(64'h18403c60 - 64'h18403c40); 
+    localparam PAD11 = log2ceil(64'h18403c80 - 64'h18403c60); 
+    localparam PAD12 = log2ceil(64'h18403ca0 - 64'h18403c80); 
+    localparam PAD13 = log2ceil(64'h18403cc0 - 64'h18403ca0); 
+    localparam PAD14 = log2ceil(64'h18403ce0 - 64'h18403cc0); 
+    localparam PAD15 = log2ceil(64'h18403d00 - 64'h18403ce0); 
+    localparam PAD16 = log2ceil(64'h18403d20 - 64'h18403d00); 
+    localparam PAD17 = log2ceil(64'h18403d40 - 64'h18403d20); 
+    localparam PAD18 = log2ceil(64'h18403d50 - 64'h18403d40); 
+    localparam PAD19 = log2ceil(64'h18403d60 - 64'h18403d50); 
+    localparam PAD20 = log2ceil(64'h18403d68 - 64'h18403d60); 
+    localparam PAD21 = log2ceil(64'h18403d70 - 64'h18403d68); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18403d70;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x8000000 .. 0x10000000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 29'h8000000   ) begin
+            src_channel = 22'b0000000000000000000001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+    end
+
+    // ( 0x14000000 .. 0x18000000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 29'h14000000   ) begin
+            src_channel = 22'b0000000000000000000100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
+    end
+
+    // ( 0x18200000 .. 0x18400000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 29'h18200000   ) begin
+            src_channel = 22'b0000000000010000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16;
+    end
+
+    // ( 0x18400000 .. 0x18402000 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 29'h18400000   ) begin
+            src_channel = 22'b0000000100000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+    end
+
+    // ( 0x18402800 .. 0x18403000 )
+    if ( {address[RG:PAD4],{PAD4{1'b0}}} == 29'h18402800   ) begin
+            src_channel = 22'b0000000000100000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x18403000 .. 0x18403400 )
+    if ( {address[RG:PAD5],{PAD5{1'b0}}} == 29'h18403000   ) begin
+            src_channel = 22'b0000000000000000001000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
+    end
+
+    // ( 0x18403400 .. 0x18403800 )
+    if ( {address[RG:PAD6],{PAD6{1'b0}}} == 29'h18403400   ) begin
+            src_channel = 22'b0100000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+    // ( 0x18403800 .. 0x18403c00 )
+    if ( {address[RG:PAD7],{PAD7{1'b0}}} == 29'h18403800   ) begin
+            src_channel = 22'b1000000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
+    end
+
+    // ( 0x18403c00 .. 0x18403c20 )
+    if ( {address[RG:PAD8],{PAD8{1'b0}}} == 29'h18403c00   ) begin
+            src_channel = 22'b0010000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
+    end
+
+    // ( 0x18403c20 .. 0x18403c40 )
+    if ( {address[RG:PAD9],{PAD9{1'b0}}} == 29'h18403c20   ) begin
+            src_channel = 22'b0001000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
+    end
+
+    // ( 0x18403c40 .. 0x18403c60 )
+    if ( {address[RG:PAD10],{PAD10{1'b0}}} == 29'h18403c40   ) begin
+            src_channel = 22'b0000010000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17;
+    end
+
+    // ( 0x18403c60 .. 0x18403c80 )
+    if ( {address[RG:PAD11],{PAD11{1'b0}}} == 29'h18403c60   ) begin
+            src_channel = 22'b0000001000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 19;
+    end
+
+    // ( 0x18403c80 .. 0x18403ca0 )
+    if ( {address[RG:PAD12],{PAD12{1'b0}}} == 29'h18403c80   ) begin
+            src_channel = 22'b0000000010000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
+    end
+
+    // ( 0x18403ca0 .. 0x18403cc0 )
+    if ( {address[RG:PAD13],{PAD13{1'b0}}} == 29'h18403ca0   ) begin
+            src_channel = 22'b0000000001000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
+    end
+
+    // ( 0x18403cc0 .. 0x18403ce0 )
+    if ( {address[RG:PAD14],{PAD14{1'b0}}} == 29'h18403cc0   ) begin
+            src_channel = 22'b0000000000000100000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 21;
+    end
+
+    // ( 0x18403ce0 .. 0x18403d00 )
+    if ( {address[RG:PAD15],{PAD15{1'b0}}} == 29'h18403ce0   ) begin
+            src_channel = 22'b0000000000000001000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
+    end
+
+    // ( 0x18403d00 .. 0x18403d20 )
+    if ( {address[RG:PAD16],{PAD16{1'b0}}} == 29'h18403d00   ) begin
+            src_channel = 22'b0000000000000000100000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
+    end
+
+    // ( 0x18403d20 .. 0x18403d40 )
+    if ( {address[RG:PAD17],{PAD17{1'b0}}} == 29'h18403d20   ) begin
+            src_channel = 22'b0000000000000000000010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
+    end
+
+    // ( 0x18403d40 .. 0x18403d50 )
+    if ( {address[RG:PAD18],{PAD18{1'b0}}} == 29'h18403d40  && read_transaction  ) begin
+            src_channel = 22'b0000100000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+    // ( 0x18403d50 .. 0x18403d60 )
+    if ( {address[RG:PAD19],{PAD19{1'b0}}} == 29'h18403d50   ) begin
+            src_channel = 22'b0000000000001000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 18;
+    end
+
+    // ( 0x18403d60 .. 0x18403d68 )
+    if ( {address[RG:PAD20],{PAD20{1'b0}}} == 29'h18403d60   ) begin
+            src_channel = 22'b0000000000000010000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
+    end
+
+    // ( 0x18403d68 .. 0x18403d70 )
+    if ( {address[RG:PAD21],{PAD21{1'b0}}} == 29'h18403d68  && read_transaction  ) begin
+            src_channel = 22'b0000000000000000010000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 20;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv
new file mode 100644
index 0000000..0ab4924
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_001.sv
@@ -0,0 +1,241 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_001_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_001
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    localparam PAD1 = log2ceil(64'h18000000 - 64'h14000000); 
+    localparam PAD2 = log2ceil(64'h18400000 - 64'h18200000); 
+    localparam PAD3 = log2ceil(64'h18403000 - 64'h18402800); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18403000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_001_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x8000000 .. 0x10000000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 29'h8000000   ) begin
+            src_channel = 22'b0001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+    end
+
+    // ( 0x14000000 .. 0x18000000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 29'h14000000   ) begin
+            src_channel = 22'b0010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
+    end
+
+    // ( 0x18200000 .. 0x18400000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 29'h18200000   ) begin
+            src_channel = 22'b0100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16;
+    end
+
+    // ( 0x18402800 .. 0x18403000 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 29'h18402800   ) begin
+            src_channel = 22'b1000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv
new file mode 100644
index 0000000..850eb9a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_002.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_002_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_002
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h10000000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_002_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 8000000 .. 10000000 )
+          src_channel = 22'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_003.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_003.sv
new file mode 100644
index 0000000..928418c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_003.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_003_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 2 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [20-1 : 0] default_wr_channel,
+   output [20-1 : 0] default_rd_channel,
+   output [20-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 20'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 20'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 20'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_003
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [20-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 20;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h10000000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [20-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_003_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 8000000 .. 10000000 )
+          src_channel = 20'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv
new file mode 100644
index 0000000..4c35171
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_004.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_004_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 5 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_004
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h18402000 - 64'h18400000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18402000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_004_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 18400000 .. 18402000 )
+          src_channel = 22'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_005.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_005.sv
new file mode 100644
index 0000000..14dc91e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_005.sv
@@ -0,0 +1,241 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_005_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 2 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_005
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    localparam PAD1 = log2ceil(64'h18000000 - 64'h14000000); 
+    localparam PAD2 = log2ceil(64'h18100000 - 64'h18080000); 
+    localparam PAD3 = log2ceil(64'h18123000 - 64'h18122800); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18123000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_005_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x8000000 .. 0x10000000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 29'h8000000   ) begin
+            src_channel = 21'b0001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x14000000 .. 0x18000000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 29'h14000000   ) begin
+            src_channel = 21'b0010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
+    end
+
+    // ( 0x18080000 .. 0x18100000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 29'h18080000   ) begin
+            src_channel = 21'b0100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
+    end
+
+    // ( 0x18122800 .. 0x18123000 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 29'h18122800   ) begin
+            src_channel = 21'b1000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_006.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_006.sv
new file mode 100644
index 0000000..48684dc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_006.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_006_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 2 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_006
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h10000000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_006_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 8000000 .. 10000000 )
+          src_channel = 21'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv
new file mode 100644
index 0000000..324694b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_008.sv
@@ -0,0 +1,234 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_008_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_008
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_008_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b0001;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 22'b0010;
+        end
+
+        if (destid == 7  && read_transaction) begin
+            src_channel = 22'b0100;
+        end
+
+        if (destid == 4  && write_transaction) begin
+            src_channel = 22'b1000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv
new file mode 100644
index 0000000..5f3f092
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_009.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_009_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_009
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_009_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv
new file mode 100644
index 0000000..ca2fb19
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_010.sv
@@ -0,0 +1,224 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_010_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_010
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_010_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b01;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 22'b10;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_011.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_011.sv
new file mode 100644
index 0000000..ab91110
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_011.sv
@@ -0,0 +1,224 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_011_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_011
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_011_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b01;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 21'b10;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_012.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_012.sv
new file mode 100644
index 0000000..f5ea671
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_012.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_012_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_012
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_012_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_013.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_013.sv
new file mode 100644
index 0000000..3e75c73
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_013.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_013_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_013
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_013_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_014.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_014.sv
new file mode 100644
index 0000000..9304e00
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_014.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_014_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [213 - 210 : 0] default_destination_id,
+   output [16-1 : 0] default_wr_channel,
+   output [16-1 : 0] default_rd_channel,
+   output [16-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[213 - 210 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 16'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 16'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 16'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_014
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [227-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [227-1    : 0] src_data,
+    output reg [16-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 172;
+    localparam PKT_ADDR_L = 144;
+    localparam PKT_DEST_ID_H = 213;
+    localparam PKT_DEST_ID_L = 210;
+    localparam PKT_PROTECTION_H = 217;
+    localparam PKT_PROTECTION_L = 215;
+    localparam ST_DATA_W = 227;
+    localparam ST_CHANNEL_W = 16;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 175;
+    localparam PKT_TRANS_READ  = 176;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [16-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_014_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 16'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv
new file mode 100644
index 0000000..b748a96
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_018.sv
@@ -0,0 +1,238 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_018_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [108 - 105 : 0] default_destination_id,
+   output [14-1 : 0] default_wr_channel,
+   output [14-1 : 0] default_rd_channel,
+   output [14-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[108 - 105 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 14'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 14'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 14'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_018
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [122-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [122-1    : 0] src_data,
+    output reg [14-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 67;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 108;
+    localparam PKT_DEST_ID_L = 105;
+    localparam PKT_PROTECTION_H = 112;
+    localparam PKT_PROTECTION_L = 110;
+    localparam ST_DATA_W = 122;
+    localparam ST_CHANNEL_W = 14;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 70;
+    localparam PKT_TRANS_READ  = 71;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [14-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_018_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 14'b00001;
+        end
+
+        if (destid == 2  && read_transaction) begin
+            src_channel = 14'b00010;
+        end
+
+        if (destid == 5  && read_transaction) begin
+            src_channel = 14'b00100;
+        end
+
+        if (destid == 6  && write_transaction) begin
+            src_channel = 14'b01000;
+        end
+
+        if (destid == 3  && write_transaction) begin
+            src_channel = 14'b10000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_020.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_020.sv
new file mode 100644
index 0000000..d659a2c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_020.sv
@@ -0,0 +1,238 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_020_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [18-1 : 0] default_wr_channel,
+   output [18-1 : 0] default_rd_channel,
+   output [18-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 18'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_020
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [18-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 18;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [18-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_020_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 18'b00001;
+        end
+
+        if (destid == 5  && read_transaction) begin
+            src_channel = 18'b00010;
+        end
+
+        if (destid == 2  && read_transaction) begin
+            src_channel = 18'b00100;
+        end
+
+        if (destid == 6  && write_transaction) begin
+            src_channel = 18'b01000;
+        end
+
+        if (destid == 3  && write_transaction) begin
+            src_channel = 18'b10000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_021.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_021.sv
new file mode 100644
index 0000000..2493537
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_021.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_021_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [215 - 211 : 0] default_destination_id,
+   output [20-1 : 0] default_wr_channel,
+   output [20-1 : 0] default_rd_channel,
+   output [20-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[215 - 211 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 20'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 20'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 20'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_021
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [229-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [229-1    : 0] src_data,
+    output reg [20-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 172;
+    localparam PKT_ADDR_L = 144;
+    localparam PKT_DEST_ID_H = 215;
+    localparam PKT_DEST_ID_L = 211;
+    localparam PKT_PROTECTION_H = 219;
+    localparam PKT_PROTECTION_L = 217;
+    localparam ST_DATA_W = 229;
+    localparam ST_CHANNEL_W = 20;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 175;
+    localparam PKT_TRANS_READ  = 176;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [20-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_021_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 20'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_022.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_022.sv
new file mode 100644
index 0000000..aca80b1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_022.sv
@@ -0,0 +1,238 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_022_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_022
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_022_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b00001;
+        end
+
+        if (destid == 5  && read_transaction) begin
+            src_channel = 22'b00010;
+        end
+
+        if (destid == 2  && read_transaction) begin
+            src_channel = 22'b00100;
+        end
+
+        if (destid == 6  && write_transaction) begin
+            src_channel = 22'b01000;
+        end
+
+        if (destid == 3  && write_transaction) begin
+            src_channel = 22'b10000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_023.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_023.sv
new file mode 100644
index 0000000..1c21972
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_023.sv
@@ -0,0 +1,238 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_023_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_023
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_023_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b00001;
+        end
+
+        if (destid == 5  && read_transaction) begin
+            src_channel = 21'b00010;
+        end
+
+        if (destid == 2  && read_transaction) begin
+            src_channel = 21'b00100;
+        end
+
+        if (destid == 6  && write_transaction) begin
+            src_channel = 21'b01000;
+        end
+
+        if (destid == 3  && write_transaction) begin
+            src_channel = 21'b10000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_024.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_024.sv
new file mode 100644
index 0000000..0353899
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_024.sv
@@ -0,0 +1,242 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_024_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [20-1 : 0] default_wr_channel,
+   output [20-1 : 0] default_rd_channel,
+   output [20-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 20'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 20'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 20'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_024
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [20-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 20;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [20-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_024_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 20'b000001;
+        end
+
+        if (destid == 8  && read_transaction) begin
+            src_channel = 20'b000010;
+        end
+
+        if (destid == 6  && read_transaction) begin
+            src_channel = 20'b000100;
+        end
+
+        if (destid == 3  && read_transaction) begin
+            src_channel = 20'b001000;
+        end
+
+        if (destid == 7  && write_transaction) begin
+            src_channel = 20'b010000;
+        end
+
+        if (destid == 4  && write_transaction) begin
+            src_channel = 20'b100000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_025.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_025.sv
new file mode 100644
index 0000000..99e3ecb
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_025.sv
@@ -0,0 +1,242 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_025_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_025
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_0_router_025_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b000001;
+        end
+
+        if (destid == 8  && read_transaction) begin
+            src_channel = 21'b000010;
+        end
+
+        if (destid == 6  && read_transaction) begin
+            src_channel = 21'b000100;
+        end
+
+        if (destid == 3  && read_transaction) begin
+            src_channel = 21'b001000;
+        end
+
+        if (destid == 7  && write_transaction) begin
+            src_channel = 21'b010000;
+        end
+
+        if (destid == 4  && write_transaction) begin
+            src_channel = 21'b100000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_028.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_028.sv
new file mode 100644
index 0000000..981509b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_router_028.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_0_router_028_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [89 - 85 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[89 - 85 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_0_router_028
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [103-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [103-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 46;
+    localparam PKT_ADDR_L = 18;
+    localparam PKT_DEST_ID_H = 89;
+    localparam PKT_DEST_ID_L = 85;
+    localparam PKT_PROTECTION_H = 93;
+    localparam PKT_PROTECTION_L = 91;
+    localparam ST_DATA_W = 103;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 49;
+    localparam PKT_TRANS_READ  = 50;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_0_router_028_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
new file mode 100644
index 0000000..045245d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{18{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv
new file mode 100644
index 0000000..b0e93f9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_001.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_001
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_001
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{21{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
new file mode 100644
index 0000000..a5616a3
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_002.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_002
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_002
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{20{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
new file mode 100644
index 0000000..1b35dab
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_003.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_003
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_003
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{19{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
new file mode 100644
index 0000000..92f9378
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_010.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_010
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_010
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{20{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_011.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_011.sv
new file mode 100644
index 0000000..89d4eb5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_011.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_011
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_011
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{19{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_012.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_012.sv
new file mode 100644
index 0000000..98f219b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_012.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_012
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        18
+//   NUM_OUTPUTS:         5
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_012
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [18-1 : 0]   sink_channel, // ST_CHANNEL_W=18
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 5;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+
+    assign sink_ready = |(sink_channel & {{13{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_013.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_013.sv
new file mode 100644
index 0000000..fd80c2a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_013.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_013
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        18
+//   NUM_OUTPUTS:         5
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_013
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [18-1 : 0]   sink_channel, // ST_CHANNEL_W=18
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 5;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+
+    assign sink_ready = |(sink_channel & {{13{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv
new file mode 100644
index 0000000..32d3a75
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_014.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_014
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         5
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_014
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src4_channel, // ST_CHANNEL_W=22
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 5;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+
+    assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_015.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_015.sv
new file mode 100644
index 0000000..e9c2949
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_015.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_015
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         5
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_015
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src4_channel, // ST_CHANNEL_W=21
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 5;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+
+    assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_016.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_016.sv
new file mode 100644
index 0000000..56415fc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_016.sv
@@ -0,0 +1,175 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_016
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         6
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_016
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src4_channel, // ST_CHANNEL_W=21
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+    output reg                      src5_valid,
+    output reg [121-1    : 0] src5_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src5_channel, // ST_CHANNEL_W=21
+    output reg                      src5_startofpacket,
+    output reg                      src5_endofpacket,
+    input                           src5_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 6;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+        src5_data          = sink_data;
+        src5_startofpacket = sink_startofpacket;
+        src5_endofpacket   = sink_endofpacket;
+        src5_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src5_valid         = sink_channel[5] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+    assign ready_vector[5] = src5_ready;
+
+    assign sink_ready = |(sink_channel & {{15{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_021.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_021.sv
new file mode 100644
index 0000000..04a8813
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_demux_021.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_demux_021
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_demux_021
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [22-1 : 0]   sink_channel, // ST_CHANNEL_W=22
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src0_channel, // ST_CHANNEL_W=22
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src1_channel, // ST_CHANNEL_W=22
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src2_channel, // ST_CHANNEL_W=22
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [22-1 : 0] src3_channel, // ST_CHANNEL_W=22
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{18{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
new file mode 100644
index 0000000..d5a9e81
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux.sv
@@ -0,0 +1,745 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux
+//   NUM_INPUTS:          22
+//   ARBITRATION_SHARES:  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [22-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [22-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [22-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [22-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+    input                       sink5_valid,
+    input [121-1   : 0]  sink5_data,
+    input [22-1: 0]  sink5_channel,
+    input                       sink5_startofpacket,
+    input                       sink5_endofpacket,
+    output                      sink5_ready,
+
+    input                       sink6_valid,
+    input [121-1   : 0]  sink6_data,
+    input [22-1: 0]  sink6_channel,
+    input                       sink6_startofpacket,
+    input                       sink6_endofpacket,
+    output                      sink6_ready,
+
+    input                       sink7_valid,
+    input [121-1   : 0]  sink7_data,
+    input [22-1: 0]  sink7_channel,
+    input                       sink7_startofpacket,
+    input                       sink7_endofpacket,
+    output                      sink7_ready,
+
+    input                       sink8_valid,
+    input [121-1   : 0]  sink8_data,
+    input [22-1: 0]  sink8_channel,
+    input                       sink8_startofpacket,
+    input                       sink8_endofpacket,
+    output                      sink8_ready,
+
+    input                       sink9_valid,
+    input [121-1   : 0]  sink9_data,
+    input [22-1: 0]  sink9_channel,
+    input                       sink9_startofpacket,
+    input                       sink9_endofpacket,
+    output                      sink9_ready,
+
+    input                       sink10_valid,
+    input [121-1   : 0]  sink10_data,
+    input [22-1: 0]  sink10_channel,
+    input                       sink10_startofpacket,
+    input                       sink10_endofpacket,
+    output                      sink10_ready,
+
+    input                       sink11_valid,
+    input [121-1   : 0]  sink11_data,
+    input [22-1: 0]  sink11_channel,
+    input                       sink11_startofpacket,
+    input                       sink11_endofpacket,
+    output                      sink11_ready,
+
+    input                       sink12_valid,
+    input [121-1   : 0]  sink12_data,
+    input [22-1: 0]  sink12_channel,
+    input                       sink12_startofpacket,
+    input                       sink12_endofpacket,
+    output                      sink12_ready,
+
+    input                       sink13_valid,
+    input [121-1   : 0]  sink13_data,
+    input [22-1: 0]  sink13_channel,
+    input                       sink13_startofpacket,
+    input                       sink13_endofpacket,
+    output                      sink13_ready,
+
+    input                       sink14_valid,
+    input [121-1   : 0]  sink14_data,
+    input [22-1: 0]  sink14_channel,
+    input                       sink14_startofpacket,
+    input                       sink14_endofpacket,
+    output                      sink14_ready,
+
+    input                       sink15_valid,
+    input [121-1   : 0]  sink15_data,
+    input [22-1: 0]  sink15_channel,
+    input                       sink15_startofpacket,
+    input                       sink15_endofpacket,
+    output                      sink15_ready,
+
+    input                       sink16_valid,
+    input [121-1   : 0]  sink16_data,
+    input [22-1: 0]  sink16_channel,
+    input                       sink16_startofpacket,
+    input                       sink16_endofpacket,
+    output                      sink16_ready,
+
+    input                       sink17_valid,
+    input [121-1   : 0]  sink17_data,
+    input [22-1: 0]  sink17_channel,
+    input                       sink17_startofpacket,
+    input                       sink17_endofpacket,
+    output                      sink17_ready,
+
+    input                       sink18_valid,
+    input [121-1   : 0]  sink18_data,
+    input [22-1: 0]  sink18_channel,
+    input                       sink18_startofpacket,
+    input                       sink18_endofpacket,
+    output                      sink18_ready,
+
+    input                       sink19_valid,
+    input [121-1   : 0]  sink19_data,
+    input [22-1: 0]  sink19_channel,
+    input                       sink19_startofpacket,
+    input                       sink19_endofpacket,
+    output                      sink19_ready,
+
+    input                       sink20_valid,
+    input [121-1   : 0]  sink20_data,
+    input [22-1: 0]  sink20_channel,
+    input                       sink20_startofpacket,
+    input                       sink20_endofpacket,
+    output                      sink20_ready,
+
+    input                       sink21_valid,
+    input [121-1   : 0]  sink21_data,
+    input [22-1: 0]  sink21_channel,
+    input                       sink21_startofpacket,
+    input                       sink21_endofpacket,
+    output                      sink21_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 22;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+    wire [PAYLOAD_W - 1 : 0] sink5_payload;
+    wire [PAYLOAD_W - 1 : 0] sink6_payload;
+    wire [PAYLOAD_W - 1 : 0] sink7_payload;
+    wire [PAYLOAD_W - 1 : 0] sink8_payload;
+    wire [PAYLOAD_W - 1 : 0] sink9_payload;
+    wire [PAYLOAD_W - 1 : 0] sink10_payload;
+    wire [PAYLOAD_W - 1 : 0] sink11_payload;
+    wire [PAYLOAD_W - 1 : 0] sink12_payload;
+    wire [PAYLOAD_W - 1 : 0] sink13_payload;
+    wire [PAYLOAD_W - 1 : 0] sink14_payload;
+    wire [PAYLOAD_W - 1 : 0] sink15_payload;
+    wire [PAYLOAD_W - 1 : 0] sink16_payload;
+    wire [PAYLOAD_W - 1 : 0] sink17_payload;
+    wire [PAYLOAD_W - 1 : 0] sink18_payload;
+    wire [PAYLOAD_W - 1 : 0] sink19_payload;
+    wire [PAYLOAD_W - 1 : 0] sink20_payload;
+    wire [PAYLOAD_W - 1 : 0] sink21_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+    assign valid[5] = sink5_valid;
+    assign valid[6] = sink6_valid;
+    assign valid[7] = sink7_valid;
+    assign valid[8] = sink8_valid;
+    assign valid[9] = sink9_valid;
+    assign valid[10] = sink10_valid;
+    assign valid[11] = sink11_valid;
+    assign valid[12] = sink12_valid;
+    assign valid[13] = sink13_valid;
+    assign valid[14] = sink14_valid;
+    assign valid[15] = sink15_valid;
+    assign valid[16] = sink16_valid;
+    assign valid[17] = sink17_valid;
+    assign valid[18] = sink18_valid;
+    assign valid[19] = sink19_valid;
+    assign valid[20] = sink20_valid;
+    assign valid[21] = sink21_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+      lock[5] = sink5_data[69];
+      lock[6] = sink6_data[69];
+      lock[7] = sink7_data[69];
+      lock[8] = sink8_data[69];
+      lock[9] = sink9_data[69];
+      lock[10] = sink10_data[69];
+      lock[11] = sink11_data[69];
+      lock[12] = sink12_data[69];
+      lock[13] = sink13_data[69];
+      lock[14] = sink14_data[69];
+      lock[15] = sink15_data[69];
+      lock[16] = sink16_data[69];
+      lock[17] = sink17_data[69];
+      lock[18] = sink18_data[69];
+      lock[19] = sink19_data[69];
+      lock[20] = sink20_data[69];
+      lock[21] = sink21_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+    // 5      |      1       |  0
+    // 6      |      1       |  0
+    // 7      |      1       |  0
+    // 8      |      1       |  0
+    // 9      |      1       |  0
+    // 10      |      1       |  0
+    // 11      |      1       |  0
+    // 12      |      1       |  0
+    // 13      |      1       |  0
+    // 14      |      1       |  0
+    // 15      |      1       |  0
+    // 16      |      1       |  0
+    // 17      |      1       |  0
+    // 18      |      1       |  0
+    // 19      |      1       |  0
+    // 20      |      1       |  0
+    // 21      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_18 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_19 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_20 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_21 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+    share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
+    share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
+    share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
+    share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
+    share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
+    share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
+    share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
+    share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
+    share_13 & { SHARE_COUNTER_W {next_grant[13]} } |
+    share_14 & { SHARE_COUNTER_W {next_grant[14]} } |
+    share_15 & { SHARE_COUNTER_W {next_grant[15]} } |
+    share_16 & { SHARE_COUNTER_W {next_grant[16]} } |
+    share_17 & { SHARE_COUNTER_W {next_grant[17]} } |
+    share_18 & { SHARE_COUNTER_W {next_grant[18]} } |
+    share_19 & { SHARE_COUNTER_W {next_grant[19]} } |
+    share_20 & { SHARE_COUNTER_W {next_grant[20]} } |
+    share_21 & { SHARE_COUNTER_W {next_grant[21]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+    wire final_packet_5 = 1'b1;
+
+    wire final_packet_6 = 1'b1;
+
+    wire final_packet_7 = 1'b1;
+
+    wire final_packet_8 = 1'b1;
+
+    wire final_packet_9 = 1'b1;
+
+    wire final_packet_10 = 1'b1;
+
+    wire final_packet_11 = 1'b1;
+
+    wire final_packet_12 = 1'b1;
+
+    wire final_packet_13 = 1'b1;
+
+    wire final_packet_14 = 1'b1;
+
+    wire final_packet_15 = 1'b1;
+
+    wire final_packet_16 = 1'b1;
+
+    wire final_packet_17 = 1'b1;
+
+    wire final_packet_18 = 1'b1;
+
+    wire final_packet_19 = 1'b1;
+
+    wire final_packet_20 = 1'b1;
+
+    wire final_packet_21 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_21,
+    final_packet_20,
+    final_packet_19,
+    final_packet_18,
+    final_packet_17,
+    final_packet_16,
+    final_packet_15,
+    final_packet_14,
+    final_packet_13,
+    final_packet_12,
+    final_packet_11,
+    final_packet_10,
+    final_packet_9,
+    final_packet_8,
+    final_packet_7,
+    final_packet_6,
+    final_packet_5,
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+    assign sink5_ready = src_ready && grant[5];
+    assign sink6_ready = src_ready && grant[6];
+    assign sink7_ready = src_ready && grant[7];
+    assign sink8_ready = src_ready && grant[8];
+    assign sink9_ready = src_ready && grant[9];
+    assign sink10_ready = src_ready && grant[10];
+    assign sink11_ready = src_ready && grant[11];
+    assign sink12_ready = src_ready && grant[12];
+    assign sink13_ready = src_ready && grant[13];
+    assign sink14_ready = src_ready && grant[14];
+    assign sink15_ready = src_ready && grant[15];
+    assign sink16_ready = src_ready && grant[16];
+    assign sink17_ready = src_ready && grant[17];
+    assign sink18_ready = src_ready && grant[18];
+    assign sink19_ready = src_ready && grant[19];
+    assign sink20_ready = src_ready && grant[20];
+    assign sink21_ready = src_ready && grant[21];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} } |
+      sink5_payload & {PAYLOAD_W {grant[5]} } |
+      sink6_payload & {PAYLOAD_W {grant[6]} } |
+      sink7_payload & {PAYLOAD_W {grant[7]} } |
+      sink8_payload & {PAYLOAD_W {grant[8]} } |
+      sink9_payload & {PAYLOAD_W {grant[9]} } |
+      sink10_payload & {PAYLOAD_W {grant[10]} } |
+      sink11_payload & {PAYLOAD_W {grant[11]} } |
+      sink12_payload & {PAYLOAD_W {grant[12]} } |
+      sink13_payload & {PAYLOAD_W {grant[13]} } |
+      sink14_payload & {PAYLOAD_W {grant[14]} } |
+      sink15_payload & {PAYLOAD_W {grant[15]} } |
+      sink16_payload & {PAYLOAD_W {grant[16]} } |
+      sink17_payload & {PAYLOAD_W {grant[17]} } |
+      sink18_payload & {PAYLOAD_W {grant[18]} } |
+      sink19_payload & {PAYLOAD_W {grant[19]} } |
+      sink20_payload & {PAYLOAD_W {grant[20]} } |
+      sink21_payload & {PAYLOAD_W {grant[21]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+    assign sink5_payload = {sink5_channel,sink5_data,
+    sink5_startofpacket,sink5_endofpacket};
+    assign sink6_payload = {sink6_channel,sink6_data,
+    sink6_startofpacket,sink6_endofpacket};
+    assign sink7_payload = {sink7_channel,sink7_data,
+    sink7_startofpacket,sink7_endofpacket};
+    assign sink8_payload = {sink8_channel,sink8_data,
+    sink8_startofpacket,sink8_endofpacket};
+    assign sink9_payload = {sink9_channel,sink9_data,
+    sink9_startofpacket,sink9_endofpacket};
+    assign sink10_payload = {sink10_channel,sink10_data,
+    sink10_startofpacket,sink10_endofpacket};
+    assign sink11_payload = {sink11_channel,sink11_data,
+    sink11_startofpacket,sink11_endofpacket};
+    assign sink12_payload = {sink12_channel,sink12_data,
+    sink12_startofpacket,sink12_endofpacket};
+    assign sink13_payload = {sink13_channel,sink13_data,
+    sink13_startofpacket,sink13_endofpacket};
+    assign sink14_payload = {sink14_channel,sink14_data,
+    sink14_startofpacket,sink14_endofpacket};
+    assign sink15_payload = {sink15_channel,sink15_data,
+    sink15_startofpacket,sink15_endofpacket};
+    assign sink16_payload = {sink16_channel,sink16_data,
+    sink16_startofpacket,sink16_endofpacket};
+    assign sink17_payload = {sink17_channel,sink17_data,
+    sink17_startofpacket,sink17_endofpacket};
+    assign sink18_payload = {sink18_channel,sink18_data,
+    sink18_startofpacket,sink18_endofpacket};
+    assign sink19_payload = {sink19_channel,sink19_data,
+    sink19_startofpacket,sink19_endofpacket};
+    assign sink20_payload = {sink20_channel,sink20_data,
+    sink20_startofpacket,sink20_endofpacket};
+    assign sink21_payload = {sink21_channel,sink21_data,
+    sink21_startofpacket,sink21_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
new file mode 100644
index 0000000..3a92be2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_001.sv
@@ -0,0 +1,385 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_001
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_001
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [22-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [22-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [22-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
new file mode 100644
index 0000000..800b377
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_002.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_002
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_002
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_003.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_003.sv
new file mode 100644
index 0000000..76ddb55
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_003.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_003
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        20
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_003
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [20-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [20-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 20 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 20;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_004.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_004.sv
new file mode 100644
index 0000000..a1635a6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_004.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_004
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        22
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_004
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [22-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [22-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 22 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 22;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_005.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_005.sv
new file mode 100644
index 0000000..de274a2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_005.sv
@@ -0,0 +1,385 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_005
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_005
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_006.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_006.sv
new file mode 100644
index 0000000..225998a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_0_rsp_mux_006.sv
@@ -0,0 +1,345 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/18.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/01/31 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_0_rsp_mux_006
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           119
+//   ST_CHANNEL_W:        16
+// ------------------------------------------
+
+module q_sys_mm_interconnect_0_rsp_mux_006
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [119-1   : 0]  sink0_data,
+    input [16-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [119-1   : 0]  sink1_data,
+    input [16-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [119-1    : 0] src_data,
+    output [16-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 119 + 16 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 119;
+    localparam ST_CHANNEL_W     = 16;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v
new file mode 100644
index 0000000..42c9405
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v
@@ -0,0 +1,10366 @@
+// q_sys_mm_interconnect_1.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_1 (
+		input  wire        ddr3_ram_afi_clk_clk,                                      //                                    ddr3_ram_afi_clk.clk
+		input  wire        ext_flash_clock_bridge_out_clk_clk,                        //                      ext_flash_clock_bridge_out_clk.clk
+		input  wire        sys_clk_clk_clk,                                           //                                         sys_clk_clk.clk
+		input  wire        cpu_reset_reset_bridge_in_reset_reset,                     //                     cpu_reset_reset_bridge_in_reset.reset
+		input  wire        ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset, // ddr3_ram_avl_translator_reset_reset_bridge_in_reset.reset
+		input  wire        ddr3_ram_soft_reset_reset_bridge_in_reset_reset,           //           ddr3_ram_soft_reset_reset_bridge_in_reset.reset
+		input  wire        eth_tse_reset_connection_reset_bridge_in_reset_reset,      //      eth_tse_reset_connection_reset_bridge_in_reset.reset
+		input  wire        ext_flash_reset_reset_bridge_in_reset_reset,               //               ext_flash_reset_reset_bridge_in_reset.reset
+		input  wire [28:0] cpu_data_master_address,                                   //                                     cpu_data_master.address
+		output wire        cpu_data_master_waitrequest,                               //                                                    .waitrequest
+		input  wire [3:0]  cpu_data_master_byteenable,                                //                                                    .byteenable
+		input  wire        cpu_data_master_read,                                      //                                                    .read
+		output wire [31:0] cpu_data_master_readdata,                                  //                                                    .readdata
+		output wire        cpu_data_master_readdatavalid,                             //                                                    .readdatavalid
+		input  wire        cpu_data_master_write,                                     //                                                    .write
+		input  wire [31:0] cpu_data_master_writedata,                                 //                                                    .writedata
+		input  wire        cpu_data_master_debugaccess,                               //                                                    .debugaccess
+		input  wire [28:0] cpu_instruction_master_address,                            //                              cpu_instruction_master.address
+		output wire        cpu_instruction_master_waitrequest,                        //                                                    .waitrequest
+		input  wire        cpu_instruction_master_read,                               //                                                    .read
+		output wire [31:0] cpu_instruction_master_readdata,                           //                                                    .readdata
+		output wire        cpu_instruction_master_readdatavalid,                      //                                                    .readdatavalid
+		input  wire [28:0] msgdma_rx_descriptor_read_master_address,                  //                    msgdma_rx_descriptor_read_master.address
+		output wire        msgdma_rx_descriptor_read_master_waitrequest,              //                                                    .waitrequest
+		input  wire        msgdma_rx_descriptor_read_master_read,                     //                                                    .read
+		output wire [31:0] msgdma_rx_descriptor_read_master_readdata,                 //                                                    .readdata
+		output wire        msgdma_rx_descriptor_read_master_readdatavalid,            //                                                    .readdatavalid
+		input  wire [28:0] msgdma_rx_descriptor_write_master_address,                 //                   msgdma_rx_descriptor_write_master.address
+		output wire        msgdma_rx_descriptor_write_master_waitrequest,             //                                                    .waitrequest
+		input  wire [3:0]  msgdma_rx_descriptor_write_master_byteenable,              //                                                    .byteenable
+		input  wire        msgdma_rx_descriptor_write_master_write,                   //                                                    .write
+		input  wire [31:0] msgdma_rx_descriptor_write_master_writedata,               //                                                    .writedata
+		output wire [1:0]  msgdma_rx_descriptor_write_master_response,                //                                                    .response
+		output wire        msgdma_rx_descriptor_write_master_writeresponsevalid,      //                                                    .writeresponsevalid
+		input  wire [27:0] msgdma_rx_mm_write_address,                                //                                  msgdma_rx_mm_write.address
+		output wire        msgdma_rx_mm_write_waitrequest,                            //                                                    .waitrequest
+		input  wire [3:0]  msgdma_rx_mm_write_byteenable,                             //                                                    .byteenable
+		input  wire        msgdma_rx_mm_write_write,                                  //                                                    .write
+		input  wire [31:0] msgdma_rx_mm_write_writedata,                              //                                                    .writedata
+		input  wire [28:0] msgdma_tx_descriptor_read_master_address,                  //                    msgdma_tx_descriptor_read_master.address
+		output wire        msgdma_tx_descriptor_read_master_waitrequest,              //                                                    .waitrequest
+		input  wire        msgdma_tx_descriptor_read_master_read,                     //                                                    .read
+		output wire [31:0] msgdma_tx_descriptor_read_master_readdata,                 //                                                    .readdata
+		output wire        msgdma_tx_descriptor_read_master_readdatavalid,            //                                                    .readdatavalid
+		input  wire [28:0] msgdma_tx_descriptor_write_master_address,                 //                   msgdma_tx_descriptor_write_master.address
+		output wire        msgdma_tx_descriptor_write_master_waitrequest,             //                                                    .waitrequest
+		input  wire [3:0]  msgdma_tx_descriptor_write_master_byteenable,              //                                                    .byteenable
+		input  wire        msgdma_tx_descriptor_write_master_write,                   //                                                    .write
+		input  wire [31:0] msgdma_tx_descriptor_write_master_writedata,               //                                                    .writedata
+		output wire [1:0]  msgdma_tx_descriptor_write_master_response,                //                                                    .response
+		output wire        msgdma_tx_descriptor_write_master_writeresponsevalid,      //                                                    .writeresponsevalid
+		input  wire [27:0] msgdma_tx_mm_read_address,                                 //                                   msgdma_tx_mm_read.address
+		output wire        msgdma_tx_mm_read_waitrequest,                             //                                                    .waitrequest
+		input  wire [3:0]  msgdma_tx_mm_read_byteenable,                              //                                                    .byteenable
+		input  wire        msgdma_tx_mm_read_read,                                    //                                                    .read
+		output wire [31:0] msgdma_tx_mm_read_readdata,                                //                                                    .readdata
+		output wire        msgdma_tx_mm_read_readdatavalid,                           //                                                    .readdatavalid
+		output wire [1:0]  button_pio_s1_address,                                     //                                       button_pio_s1.address
+		input  wire [31:0] button_pio_s1_readdata,                                    //                                                    .readdata
+		output wire [8:0]  calibration_ram_s1_address,                                //                                  calibration_ram_s1.address
+		output wire        calibration_ram_s1_write,                                  //                                                    .write
+		input  wire [15:0] calibration_ram_s1_readdata,                               //                                                    .readdata
+		output wire [15:0] calibration_ram_s1_writedata,                              //                                                    .writedata
+		output wire [1:0]  calibration_ram_s1_byteenable,                             //                                                    .byteenable
+		output wire        calibration_ram_s1_chipselect,                             //                                                    .chipselect
+		output wire        calibration_ram_s1_clken,                                  //                                                    .clken
+		output wire [8:0]  cpu_debug_mem_slave_address,                               //                                 cpu_debug_mem_slave.address
+		output wire        cpu_debug_mem_slave_write,                                 //                                                    .write
+		output wire        cpu_debug_mem_slave_read,                                  //                                                    .read
+		input  wire [31:0] cpu_debug_mem_slave_readdata,                              //                                                    .readdata
+		output wire [31:0] cpu_debug_mem_slave_writedata,                             //                                                    .writedata
+		output wire [3:0]  cpu_debug_mem_slave_byteenable,                            //                                                    .byteenable
+		input  wire        cpu_debug_mem_slave_waitrequest,                           //                                                    .waitrequest
+		output wire        cpu_debug_mem_slave_debugaccess,                           //                                                    .debugaccess
+		output wire [24:0] ddr3_ram_avl_address,                                      //                                        ddr3_ram_avl.address
+		output wire        ddr3_ram_avl_write,                                        //                                                    .write
+		output wire        ddr3_ram_avl_read,                                         //                                                    .read
+		input  wire [31:0] ddr3_ram_avl_readdata,                                     //                                                    .readdata
+		output wire [31:0] ddr3_ram_avl_writedata,                                    //                                                    .writedata
+		output wire        ddr3_ram_avl_beginbursttransfer,                           //                                                    .beginbursttransfer
+		output wire [2:0]  ddr3_ram_avl_burstcount,                                   //                                                    .burstcount
+		output wire [3:0]  ddr3_ram_avl_byteenable,                                   //                                                    .byteenable
+		input  wire        ddr3_ram_avl_readdatavalid,                                //                                                    .readdatavalid
+		input  wire        ddr3_ram_avl_waitrequest,                                  //                                                    .waitrequest
+		output wire [2:0]  debug_uart_s1_address,                                     //                                       debug_uart_s1.address
+		output wire        debug_uart_s1_write,                                       //                                                    .write
+		output wire        debug_uart_s1_read,                                        //                                                    .read
+		input  wire [15:0] debug_uart_s1_readdata,                                    //                                                    .readdata
+		output wire [15:0] debug_uart_s1_writedata,                                   //                                                    .writedata
+		output wire        debug_uart_s1_begintransfer,                               //                                                    .begintransfer
+		output wire        debug_uart_s1_chipselect,                                  //                                                    .chipselect
+		output wire [10:0] descriptor_memory_s1_address,                              //                                descriptor_memory_s1.address
+		output wire        descriptor_memory_s1_write,                                //                                                    .write
+		input  wire [31:0] descriptor_memory_s1_readdata,                             //                                                    .readdata
+		output wire [31:0] descriptor_memory_s1_writedata,                            //                                                    .writedata
+		output wire [3:0]  descriptor_memory_s1_byteenable,                           //                                                    .byteenable
+		output wire        descriptor_memory_s1_chipselect,                           //                                                    .chipselect
+		output wire        descriptor_memory_s1_clken,                                //                                                    .clken
+		output wire [7:0]  eth_tse_control_port_address,                              //                                eth_tse_control_port.address
+		output wire        eth_tse_control_port_write,                                //                                                    .write
+		output wire        eth_tse_control_port_read,                                 //                                                    .read
+		input  wire [31:0] eth_tse_control_port_readdata,                             //                                                    .readdata
+		output wire [31:0] eth_tse_control_port_writedata,                            //                                                    .writedata
+		input  wire        eth_tse_control_port_waitrequest,                          //                                                    .waitrequest
+		output wire [2:0]  ext_flash_avl_csr_address,                                 //                                   ext_flash_avl_csr.address
+		output wire        ext_flash_avl_csr_write,                                   //                                                    .write
+		output wire        ext_flash_avl_csr_read,                                    //                                                    .read
+		input  wire [31:0] ext_flash_avl_csr_readdata,                                //                                                    .readdata
+		output wire [31:0] ext_flash_avl_csr_writedata,                               //                                                    .writedata
+		input  wire        ext_flash_avl_csr_readdatavalid,                           //                                                    .readdatavalid
+		input  wire        ext_flash_avl_csr_waitrequest,                             //                                                    .waitrequest
+		output wire [23:0] ext_flash_avl_mem_address,                                 //                                   ext_flash_avl_mem.address
+		output wire        ext_flash_avl_mem_write,                                   //                                                    .write
+		output wire        ext_flash_avl_mem_read,                                    //                                                    .read
+		input  wire [31:0] ext_flash_avl_mem_readdata,                                //                                                    .readdata
+		output wire [31:0] ext_flash_avl_mem_writedata,                               //                                                    .writedata
+		output wire [6:0]  ext_flash_avl_mem_burstcount,                              //                                                    .burstcount
+		output wire [3:0]  ext_flash_avl_mem_byteenable,                              //                                                    .byteenable
+		input  wire        ext_flash_avl_mem_readdatavalid,                           //                                                    .readdatavalid
+		input  wire        ext_flash_avl_mem_waitrequest,                             //                                                    .waitrequest
+		output wire [2:0]  frame_timer_s1_address,                                    //                                      frame_timer_s1.address
+		output wire        frame_timer_s1_write,                                      //                                                    .write
+		input  wire [15:0] frame_timer_s1_readdata,                                   //                                                    .readdata
+		output wire [15:0] frame_timer_s1_writedata,                                  //                                                    .writedata
+		output wire        frame_timer_s1_chipselect,                                 //                                                    .chipselect
+		output wire [2:0]  msgdma_rx_csr_address,                                     //                                       msgdma_rx_csr.address
+		output wire        msgdma_rx_csr_write,                                       //                                                    .write
+		output wire        msgdma_rx_csr_read,                                        //                                                    .read
+		input  wire [31:0] msgdma_rx_csr_readdata,                                    //                                                    .readdata
+		output wire [31:0] msgdma_rx_csr_writedata,                                   //                                                    .writedata
+		output wire [3:0]  msgdma_rx_csr_byteenable,                                  //                                                    .byteenable
+		output wire [2:0]  msgdma_rx_prefetcher_csr_address,                          //                            msgdma_rx_prefetcher_csr.address
+		output wire        msgdma_rx_prefetcher_csr_write,                            //                                                    .write
+		output wire        msgdma_rx_prefetcher_csr_read,                             //                                                    .read
+		input  wire [31:0] msgdma_rx_prefetcher_csr_readdata,                         //                                                    .readdata
+		output wire [31:0] msgdma_rx_prefetcher_csr_writedata,                        //                                                    .writedata
+		output wire [2:0]  msgdma_tx_csr_address,                                     //                                       msgdma_tx_csr.address
+		output wire        msgdma_tx_csr_write,                                       //                                                    .write
+		output wire        msgdma_tx_csr_read,                                        //                                                    .read
+		input  wire [31:0] msgdma_tx_csr_readdata,                                    //                                                    .readdata
+		output wire [31:0] msgdma_tx_csr_writedata,                                   //                                                    .writedata
+		output wire [3:0]  msgdma_tx_csr_byteenable,                                  //                                                    .byteenable
+		output wire [2:0]  msgdma_tx_prefetcher_csr_address,                          //                            msgdma_tx_prefetcher_csr.address
+		output wire        msgdma_tx_prefetcher_csr_write,                            //                                                    .write
+		output wire        msgdma_tx_prefetcher_csr_read,                             //                                                    .read
+		input  wire [31:0] msgdma_tx_prefetcher_csr_readdata,                         //                                                    .readdata
+		output wire [31:0] msgdma_tx_prefetcher_csr_writedata,                        //                                                    .writedata
+		output wire [0:0]  onchip_flash_csr_address,                                  //                                    onchip_flash_csr.address
+		output wire        onchip_flash_csr_write,                                    //                                                    .write
+		output wire        onchip_flash_csr_read,                                     //                                                    .read
+		input  wire [31:0] onchip_flash_csr_readdata,                                 //                                                    .readdata
+		output wire [31:0] onchip_flash_csr_writedata,                                //                                                    .writedata
+		output wire [18:0] onchip_flash_data_address,                                 //                                   onchip_flash_data.address
+		output wire        onchip_flash_data_write,                                   //                                                    .write
+		output wire        onchip_flash_data_read,                                    //                                                    .read
+		input  wire [31:0] onchip_flash_data_readdata,                                //                                                    .readdata
+		output wire [31:0] onchip_flash_data_writedata,                               //                                                    .writedata
+		output wire [3:0]  onchip_flash_data_burstcount,                              //                                                    .burstcount
+		input  wire        onchip_flash_data_readdatavalid,                           //                                                    .readdatavalid
+		input  wire        onchip_flash_data_waitrequest,                             //                                                    .waitrequest
+		output wire [2:0]  output_pio_s1_address,                                     //                                       output_pio_s1.address
+		output wire        output_pio_s1_write,                                       //                                                    .write
+		input  wire [31:0] output_pio_s1_readdata,                                    //                                                    .readdata
+		output wire [31:0] output_pio_s1_writedata,                                   //                                                    .writedata
+		output wire        output_pio_s1_chipselect,                                  //                                                    .chipselect
+		output wire [1:0]  sensor_interface_csr_address,                              //                                sensor_interface_csr.address
+		output wire        sensor_interface_csr_write,                                //                                                    .write
+		output wire        sensor_interface_csr_read,                                 //                                                    .read
+		input  wire [31:0] sensor_interface_csr_readdata,                             //                                                    .readdata
+		output wire [31:0] sensor_interface_csr_writedata,                            //                                                    .writedata
+		output wire [3:0]  sensor_interface_csr_byteenable,                           //                                                    .byteenable
+		output wire [2:0]  sys_clk_timer_s1_address,                                  //                                    sys_clk_timer_s1.address
+		output wire        sys_clk_timer_s1_write,                                    //                                                    .write
+		input  wire [15:0] sys_clk_timer_s1_readdata,                                 //                                                    .readdata
+		output wire [15:0] sys_clk_timer_s1_writedata,                                //                                                    .writedata
+		output wire        sys_clk_timer_s1_chipselect,                               //                                                    .chipselect
+		output wire [0:0]  sysid_control_slave_address,                               //                                 sysid_control_slave.address
+		input  wire [31:0] sysid_control_slave_readdata,                              //                                                    .readdata
+		output wire [2:0]  udp_generator_csr_address,                                 //                                   udp_generator_csr.address
+		output wire        udp_generator_csr_write,                                   //                                                    .write
+		output wire        udp_generator_csr_read,                                    //                                                    .read
+		input  wire [31:0] udp_generator_csr_readdata,                                //                                                    .readdata
+		output wire [31:0] udp_generator_csr_writedata,                               //                                                    .writedata
+		output wire [3:0]  udp_generator_csr_byteenable                               //                                                    .byteenable
+	);
+
+	wire          cpu_data_master_translator_avalon_universal_master_0_waitrequest;                          // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
+	wire   [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata;                             // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
+	wire          cpu_data_master_translator_avalon_universal_master_0_debugaccess;                          // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
+	wire   [28:0] cpu_data_master_translator_avalon_universal_master_0_address;                              // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
+	wire          cpu_data_master_translator_avalon_universal_master_0_read;                                 // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
+	wire    [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable;                           // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
+	wire          cpu_data_master_translator_avalon_universal_master_0_readdatavalid;                        // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
+	wire          cpu_data_master_translator_avalon_universal_master_0_lock;                                 // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
+	wire          cpu_data_master_translator_avalon_universal_master_0_write;                                // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
+	wire   [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata;                            // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
+	wire    [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount;                           // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_waitrequest;                   // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
+	wire   [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata;                      // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_debugaccess;                   // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
+	wire   [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address;                       // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_read;                          // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
+	wire    [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable;                    // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid;                 // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_lock;                          // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
+	wire          cpu_instruction_master_translator_avalon_universal_master_0_write;                         // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
+	wire   [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata;                     // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
+	wire    [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount;                    // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_waitrequest;                        // msgdma_tx_mm_read_agent:av_waitrequest -> msgdma_tx_mm_read_translator:uav_waitrequest
+	wire   [31:0] msgdma_tx_mm_read_translator_avalon_universal_master_0_readdata;                           // msgdma_tx_mm_read_agent:av_readdata -> msgdma_tx_mm_read_translator:uav_readdata
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_debugaccess;                        // msgdma_tx_mm_read_translator:uav_debugaccess -> msgdma_tx_mm_read_agent:av_debugaccess
+	wire   [28:0] msgdma_tx_mm_read_translator_avalon_universal_master_0_address;                            // msgdma_tx_mm_read_translator:uav_address -> msgdma_tx_mm_read_agent:av_address
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_read;                               // msgdma_tx_mm_read_translator:uav_read -> msgdma_tx_mm_read_agent:av_read
+	wire    [3:0] msgdma_tx_mm_read_translator_avalon_universal_master_0_byteenable;                         // msgdma_tx_mm_read_translator:uav_byteenable -> msgdma_tx_mm_read_agent:av_byteenable
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_readdatavalid;                      // msgdma_tx_mm_read_agent:av_readdatavalid -> msgdma_tx_mm_read_translator:uav_readdatavalid
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_lock;                               // msgdma_tx_mm_read_translator:uav_lock -> msgdma_tx_mm_read_agent:av_lock
+	wire          msgdma_tx_mm_read_translator_avalon_universal_master_0_write;                              // msgdma_tx_mm_read_translator:uav_write -> msgdma_tx_mm_read_agent:av_write
+	wire   [31:0] msgdma_tx_mm_read_translator_avalon_universal_master_0_writedata;                          // msgdma_tx_mm_read_translator:uav_writedata -> msgdma_tx_mm_read_agent:av_writedata
+	wire    [2:0] msgdma_tx_mm_read_translator_avalon_universal_master_0_burstcount;                         // msgdma_tx_mm_read_translator:uav_burstcount -> msgdma_tx_mm_read_agent:av_burstcount
+	wire          rsp_mux_002_src_valid;                                                                     // rsp_mux_002:src_valid -> msgdma_tx_mm_read_agent:rp_valid
+	wire  [120:0] rsp_mux_002_src_data;                                                                      // rsp_mux_002:src_data -> msgdma_tx_mm_read_agent:rp_data
+	wire          rsp_mux_002_src_ready;                                                                     // msgdma_tx_mm_read_agent:rp_ready -> rsp_mux_002:src_ready
+	wire   [20:0] rsp_mux_002_src_channel;                                                                   // rsp_mux_002:src_channel -> msgdma_tx_mm_read_agent:rp_channel
+	wire          rsp_mux_002_src_startofpacket;                                                             // rsp_mux_002:src_startofpacket -> msgdma_tx_mm_read_agent:rp_startofpacket
+	wire          rsp_mux_002_src_endofpacket;                                                               // rsp_mux_002:src_endofpacket -> msgdma_tx_mm_read_agent:rp_endofpacket
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_waitrequest;                       // msgdma_rx_mm_write_agent:av_waitrequest -> msgdma_rx_mm_write_translator:uav_waitrequest
+	wire   [31:0] msgdma_rx_mm_write_translator_avalon_universal_master_0_readdata;                          // msgdma_rx_mm_write_agent:av_readdata -> msgdma_rx_mm_write_translator:uav_readdata
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_debugaccess;                       // msgdma_rx_mm_write_translator:uav_debugaccess -> msgdma_rx_mm_write_agent:av_debugaccess
+	wire   [28:0] msgdma_rx_mm_write_translator_avalon_universal_master_0_address;                           // msgdma_rx_mm_write_translator:uav_address -> msgdma_rx_mm_write_agent:av_address
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_read;                              // msgdma_rx_mm_write_translator:uav_read -> msgdma_rx_mm_write_agent:av_read
+	wire    [3:0] msgdma_rx_mm_write_translator_avalon_universal_master_0_byteenable;                        // msgdma_rx_mm_write_translator:uav_byteenable -> msgdma_rx_mm_write_agent:av_byteenable
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_readdatavalid;                     // msgdma_rx_mm_write_agent:av_readdatavalid -> msgdma_rx_mm_write_translator:uav_readdatavalid
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_lock;                              // msgdma_rx_mm_write_translator:uav_lock -> msgdma_rx_mm_write_agent:av_lock
+	wire          msgdma_rx_mm_write_translator_avalon_universal_master_0_write;                             // msgdma_rx_mm_write_translator:uav_write -> msgdma_rx_mm_write_agent:av_write
+	wire   [31:0] msgdma_rx_mm_write_translator_avalon_universal_master_0_writedata;                         // msgdma_rx_mm_write_translator:uav_writedata -> msgdma_rx_mm_write_agent:av_writedata
+	wire    [2:0] msgdma_rx_mm_write_translator_avalon_universal_master_0_burstcount;                        // msgdma_rx_mm_write_translator:uav_burstcount -> msgdma_rx_mm_write_agent:av_burstcount
+	wire          rsp_mux_003_src_valid;                                                                     // rsp_mux_003:src_valid -> msgdma_rx_mm_write_agent:rp_valid
+	wire  [120:0] rsp_mux_003_src_data;                                                                      // rsp_mux_003:src_data -> msgdma_rx_mm_write_agent:rp_data
+	wire          rsp_mux_003_src_ready;                                                                     // msgdma_rx_mm_write_agent:rp_ready -> rsp_mux_003:src_ready
+	wire   [20:0] rsp_mux_003_src_channel;                                                                   // rsp_mux_003:src_channel -> msgdma_rx_mm_write_agent:rp_channel
+	wire          rsp_mux_003_src_startofpacket;                                                             // rsp_mux_003:src_startofpacket -> msgdma_rx_mm_write_agent:rp_startofpacket
+	wire          rsp_mux_003_src_endofpacket;                                                               // rsp_mux_003:src_endofpacket -> msgdma_rx_mm_write_agent:rp_endofpacket
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest;         // msgdma_tx_descriptor_read_master_agent:av_waitrequest -> msgdma_tx_descriptor_read_master_translator:uav_waitrequest
+	wire   [31:0] msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdata;            // msgdma_tx_descriptor_read_master_agent:av_readdata -> msgdma_tx_descriptor_read_master_translator:uav_readdata
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess;         // msgdma_tx_descriptor_read_master_translator:uav_debugaccess -> msgdma_tx_descriptor_read_master_agent:av_debugaccess
+	wire   [28:0] msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_address;             // msgdma_tx_descriptor_read_master_translator:uav_address -> msgdma_tx_descriptor_read_master_agent:av_address
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_read;                // msgdma_tx_descriptor_read_master_translator:uav_read -> msgdma_tx_descriptor_read_master_agent:av_read
+	wire    [3:0] msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_byteenable;          // msgdma_tx_descriptor_read_master_translator:uav_byteenable -> msgdma_tx_descriptor_read_master_agent:av_byteenable
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid;       // msgdma_tx_descriptor_read_master_agent:av_readdatavalid -> msgdma_tx_descriptor_read_master_translator:uav_readdatavalid
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_lock;                // msgdma_tx_descriptor_read_master_translator:uav_lock -> msgdma_tx_descriptor_read_master_agent:av_lock
+	wire          msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_write;               // msgdma_tx_descriptor_read_master_translator:uav_write -> msgdma_tx_descriptor_read_master_agent:av_write
+	wire   [31:0] msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_writedata;           // msgdma_tx_descriptor_read_master_translator:uav_writedata -> msgdma_tx_descriptor_read_master_agent:av_writedata
+	wire    [2:0] msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_burstcount;          // msgdma_tx_descriptor_read_master_translator:uav_burstcount -> msgdma_tx_descriptor_read_master_agent:av_burstcount
+	wire          rsp_mux_004_src_valid;                                                                     // rsp_mux_004:src_valid -> msgdma_tx_descriptor_read_master_agent:rp_valid
+	wire  [120:0] rsp_mux_004_src_data;                                                                      // rsp_mux_004:src_data -> msgdma_tx_descriptor_read_master_agent:rp_data
+	wire          rsp_mux_004_src_ready;                                                                     // msgdma_tx_descriptor_read_master_agent:rp_ready -> rsp_mux_004:src_ready
+	wire   [20:0] rsp_mux_004_src_channel;                                                                   // rsp_mux_004:src_channel -> msgdma_tx_descriptor_read_master_agent:rp_channel
+	wire          rsp_mux_004_src_startofpacket;                                                             // rsp_mux_004:src_startofpacket -> msgdma_tx_descriptor_read_master_agent:rp_startofpacket
+	wire          rsp_mux_004_src_endofpacket;                                                               // rsp_mux_004:src_endofpacket -> msgdma_tx_descriptor_read_master_agent:rp_endofpacket
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest;         // msgdma_rx_descriptor_read_master_agent:av_waitrequest -> msgdma_rx_descriptor_read_master_translator:uav_waitrequest
+	wire   [31:0] msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdata;            // msgdma_rx_descriptor_read_master_agent:av_readdata -> msgdma_rx_descriptor_read_master_translator:uav_readdata
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess;         // msgdma_rx_descriptor_read_master_translator:uav_debugaccess -> msgdma_rx_descriptor_read_master_agent:av_debugaccess
+	wire   [28:0] msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_address;             // msgdma_rx_descriptor_read_master_translator:uav_address -> msgdma_rx_descriptor_read_master_agent:av_address
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_read;                // msgdma_rx_descriptor_read_master_translator:uav_read -> msgdma_rx_descriptor_read_master_agent:av_read
+	wire    [3:0] msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_byteenable;          // msgdma_rx_descriptor_read_master_translator:uav_byteenable -> msgdma_rx_descriptor_read_master_agent:av_byteenable
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid;       // msgdma_rx_descriptor_read_master_agent:av_readdatavalid -> msgdma_rx_descriptor_read_master_translator:uav_readdatavalid
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_lock;                // msgdma_rx_descriptor_read_master_translator:uav_lock -> msgdma_rx_descriptor_read_master_agent:av_lock
+	wire          msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_write;               // msgdma_rx_descriptor_read_master_translator:uav_write -> msgdma_rx_descriptor_read_master_agent:av_write
+	wire   [31:0] msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_writedata;           // msgdma_rx_descriptor_read_master_translator:uav_writedata -> msgdma_rx_descriptor_read_master_agent:av_writedata
+	wire    [2:0] msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_burstcount;          // msgdma_rx_descriptor_read_master_translator:uav_burstcount -> msgdma_rx_descriptor_read_master_agent:av_burstcount
+	wire          rsp_mux_005_src_valid;                                                                     // rsp_mux_005:src_valid -> msgdma_rx_descriptor_read_master_agent:rp_valid
+	wire  [120:0] rsp_mux_005_src_data;                                                                      // rsp_mux_005:src_data -> msgdma_rx_descriptor_read_master_agent:rp_data
+	wire          rsp_mux_005_src_ready;                                                                     // msgdma_rx_descriptor_read_master_agent:rp_ready -> rsp_mux_005:src_ready
+	wire   [20:0] rsp_mux_005_src_channel;                                                                   // rsp_mux_005:src_channel -> msgdma_rx_descriptor_read_master_agent:rp_channel
+	wire          rsp_mux_005_src_startofpacket;                                                             // rsp_mux_005:src_startofpacket -> msgdma_rx_descriptor_read_master_agent:rp_startofpacket
+	wire          rsp_mux_005_src_endofpacket;                                                               // rsp_mux_005:src_endofpacket -> msgdma_rx_descriptor_read_master_agent:rp_endofpacket
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess;        // msgdma_tx_descriptor_write_master_translator:uav_debugaccess -> msgdma_tx_descriptor_write_master_agent:av_debugaccess
+	wire   [28:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_address;            // msgdma_tx_descriptor_write_master_translator:uav_address -> msgdma_tx_descriptor_write_master_agent:av_address
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_read;               // msgdma_tx_descriptor_write_master_translator:uav_read -> msgdma_tx_descriptor_write_master_agent:av_read
+	wire    [3:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_byteenable;         // msgdma_tx_descriptor_write_master_translator:uav_byteenable -> msgdma_tx_descriptor_write_master_agent:av_byteenable
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid;      // msgdma_tx_descriptor_write_master_agent:av_readdatavalid -> msgdma_tx_descriptor_write_master_translator:uav_readdatavalid
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest;        // msgdma_tx_descriptor_write_master_agent:av_waitrequest -> msgdma_tx_descriptor_write_master_translator:uav_waitrequest
+	wire   [31:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdata;           // msgdma_tx_descriptor_write_master_agent:av_readdata -> msgdma_tx_descriptor_write_master_translator:uav_readdata
+	wire    [1:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_response;           // msgdma_tx_descriptor_write_master_agent:av_response -> msgdma_tx_descriptor_write_master_translator:uav_response
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_lock;               // msgdma_tx_descriptor_write_master_translator:uav_lock -> msgdma_tx_descriptor_write_master_agent:av_lock
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_write;              // msgdma_tx_descriptor_write_master_translator:uav_write -> msgdma_tx_descriptor_write_master_agent:av_write
+	wire   [31:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writedata;          // msgdma_tx_descriptor_write_master_translator:uav_writedata -> msgdma_tx_descriptor_write_master_agent:av_writedata
+	wire          msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid; // msgdma_tx_descriptor_write_master_agent:av_writeresponsevalid -> msgdma_tx_descriptor_write_master_translator:uav_writeresponsevalid
+	wire    [2:0] msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_burstcount;         // msgdma_tx_descriptor_write_master_translator:uav_burstcount -> msgdma_tx_descriptor_write_master_agent:av_burstcount
+	wire          rsp_mux_006_src_valid;                                                                     // rsp_mux_006:src_valid -> msgdma_tx_descriptor_write_master_agent:rp_valid
+	wire  [120:0] rsp_mux_006_src_data;                                                                      // rsp_mux_006:src_data -> msgdma_tx_descriptor_write_master_agent:rp_data
+	wire          rsp_mux_006_src_ready;                                                                     // msgdma_tx_descriptor_write_master_agent:rp_ready -> rsp_mux_006:src_ready
+	wire   [20:0] rsp_mux_006_src_channel;                                                                   // rsp_mux_006:src_channel -> msgdma_tx_descriptor_write_master_agent:rp_channel
+	wire          rsp_mux_006_src_startofpacket;                                                             // rsp_mux_006:src_startofpacket -> msgdma_tx_descriptor_write_master_agent:rp_startofpacket
+	wire          rsp_mux_006_src_endofpacket;                                                               // rsp_mux_006:src_endofpacket -> msgdma_tx_descriptor_write_master_agent:rp_endofpacket
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess;        // msgdma_rx_descriptor_write_master_translator:uav_debugaccess -> msgdma_rx_descriptor_write_master_agent:av_debugaccess
+	wire   [28:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_address;            // msgdma_rx_descriptor_write_master_translator:uav_address -> msgdma_rx_descriptor_write_master_agent:av_address
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_read;               // msgdma_rx_descriptor_write_master_translator:uav_read -> msgdma_rx_descriptor_write_master_agent:av_read
+	wire    [3:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_byteenable;         // msgdma_rx_descriptor_write_master_translator:uav_byteenable -> msgdma_rx_descriptor_write_master_agent:av_byteenable
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid;      // msgdma_rx_descriptor_write_master_agent:av_readdatavalid -> msgdma_rx_descriptor_write_master_translator:uav_readdatavalid
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest;        // msgdma_rx_descriptor_write_master_agent:av_waitrequest -> msgdma_rx_descriptor_write_master_translator:uav_waitrequest
+	wire   [31:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdata;           // msgdma_rx_descriptor_write_master_agent:av_readdata -> msgdma_rx_descriptor_write_master_translator:uav_readdata
+	wire    [1:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_response;           // msgdma_rx_descriptor_write_master_agent:av_response -> msgdma_rx_descriptor_write_master_translator:uav_response
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_lock;               // msgdma_rx_descriptor_write_master_translator:uav_lock -> msgdma_rx_descriptor_write_master_agent:av_lock
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_write;              // msgdma_rx_descriptor_write_master_translator:uav_write -> msgdma_rx_descriptor_write_master_agent:av_write
+	wire   [31:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writedata;          // msgdma_rx_descriptor_write_master_translator:uav_writedata -> msgdma_rx_descriptor_write_master_agent:av_writedata
+	wire          msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid; // msgdma_rx_descriptor_write_master_agent:av_writeresponsevalid -> msgdma_rx_descriptor_write_master_translator:uav_writeresponsevalid
+	wire    [2:0] msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_burstcount;         // msgdma_rx_descriptor_write_master_translator:uav_burstcount -> msgdma_rx_descriptor_write_master_agent:av_burstcount
+	wire          rsp_mux_007_src_valid;                                                                     // rsp_mux_007:src_valid -> msgdma_rx_descriptor_write_master_agent:rp_valid
+	wire  [120:0] rsp_mux_007_src_data;                                                                      // rsp_mux_007:src_data -> msgdma_rx_descriptor_write_master_agent:rp_data
+	wire          rsp_mux_007_src_ready;                                                                     // msgdma_rx_descriptor_write_master_agent:rp_ready -> rsp_mux_007:src_ready
+	wire   [20:0] rsp_mux_007_src_channel;                                                                   // rsp_mux_007:src_channel -> msgdma_rx_descriptor_write_master_agent:rp_channel
+	wire          rsp_mux_007_src_startofpacket;                                                             // rsp_mux_007:src_startofpacket -> msgdma_rx_descriptor_write_master_agent:rp_startofpacket
+	wire          rsp_mux_007_src_endofpacket;                                                               // rsp_mux_007:src_endofpacket -> msgdma_rx_descriptor_write_master_agent:rp_endofpacket
+	wire   [31:0] ddr3_ram_avl_agent_m0_readdata;                                                            // ddr3_ram_avl_translator:uav_readdata -> ddr3_ram_avl_agent:m0_readdata
+	wire          ddr3_ram_avl_agent_m0_waitrequest;                                                         // ddr3_ram_avl_translator:uav_waitrequest -> ddr3_ram_avl_agent:m0_waitrequest
+	wire          ddr3_ram_avl_agent_m0_debugaccess;                                                         // ddr3_ram_avl_agent:m0_debugaccess -> ddr3_ram_avl_translator:uav_debugaccess
+	wire   [28:0] ddr3_ram_avl_agent_m0_address;                                                             // ddr3_ram_avl_agent:m0_address -> ddr3_ram_avl_translator:uav_address
+	wire    [3:0] ddr3_ram_avl_agent_m0_byteenable;                                                          // ddr3_ram_avl_agent:m0_byteenable -> ddr3_ram_avl_translator:uav_byteenable
+	wire          ddr3_ram_avl_agent_m0_read;                                                                // ddr3_ram_avl_agent:m0_read -> ddr3_ram_avl_translator:uav_read
+	wire          ddr3_ram_avl_agent_m0_readdatavalid;                                                       // ddr3_ram_avl_translator:uav_readdatavalid -> ddr3_ram_avl_agent:m0_readdatavalid
+	wire          ddr3_ram_avl_agent_m0_lock;                                                                // ddr3_ram_avl_agent:m0_lock -> ddr3_ram_avl_translator:uav_lock
+	wire   [31:0] ddr3_ram_avl_agent_m0_writedata;                                                           // ddr3_ram_avl_agent:m0_writedata -> ddr3_ram_avl_translator:uav_writedata
+	wire          ddr3_ram_avl_agent_m0_write;                                                               // ddr3_ram_avl_agent:m0_write -> ddr3_ram_avl_translator:uav_write
+	wire    [4:0] ddr3_ram_avl_agent_m0_burstcount;                                                          // ddr3_ram_avl_agent:m0_burstcount -> ddr3_ram_avl_translator:uav_burstcount
+	wire          ddr3_ram_avl_agent_rf_source_valid;                                                        // ddr3_ram_avl_agent:rf_source_valid -> ddr3_ram_avl_agent_rsp_fifo:in_valid
+	wire  [121:0] ddr3_ram_avl_agent_rf_source_data;                                                         // ddr3_ram_avl_agent:rf_source_data -> ddr3_ram_avl_agent_rsp_fifo:in_data
+	wire          ddr3_ram_avl_agent_rf_source_ready;                                                        // ddr3_ram_avl_agent_rsp_fifo:in_ready -> ddr3_ram_avl_agent:rf_source_ready
+	wire          ddr3_ram_avl_agent_rf_source_startofpacket;                                                // ddr3_ram_avl_agent:rf_source_startofpacket -> ddr3_ram_avl_agent_rsp_fifo:in_startofpacket
+	wire          ddr3_ram_avl_agent_rf_source_endofpacket;                                                  // ddr3_ram_avl_agent:rf_source_endofpacket -> ddr3_ram_avl_agent_rsp_fifo:in_endofpacket
+	wire          ddr3_ram_avl_agent_rsp_fifo_out_valid;                                                     // ddr3_ram_avl_agent_rsp_fifo:out_valid -> ddr3_ram_avl_agent:rf_sink_valid
+	wire  [121:0] ddr3_ram_avl_agent_rsp_fifo_out_data;                                                      // ddr3_ram_avl_agent_rsp_fifo:out_data -> ddr3_ram_avl_agent:rf_sink_data
+	wire          ddr3_ram_avl_agent_rsp_fifo_out_ready;                                                     // ddr3_ram_avl_agent:rf_sink_ready -> ddr3_ram_avl_agent_rsp_fifo:out_ready
+	wire          ddr3_ram_avl_agent_rsp_fifo_out_startofpacket;                                             // ddr3_ram_avl_agent_rsp_fifo:out_startofpacket -> ddr3_ram_avl_agent:rf_sink_startofpacket
+	wire          ddr3_ram_avl_agent_rsp_fifo_out_endofpacket;                                               // ddr3_ram_avl_agent_rsp_fifo:out_endofpacket -> ddr3_ram_avl_agent:rf_sink_endofpacket
+	wire          ddr3_ram_avl_agent_rdata_fifo_src_valid;                                                   // ddr3_ram_avl_agent:rdata_fifo_src_valid -> ddr3_ram_avl_agent_rdata_fifo:in_valid
+	wire   [33:0] ddr3_ram_avl_agent_rdata_fifo_src_data;                                                    // ddr3_ram_avl_agent:rdata_fifo_src_data -> ddr3_ram_avl_agent_rdata_fifo:in_data
+	wire          ddr3_ram_avl_agent_rdata_fifo_src_ready;                                                   // ddr3_ram_avl_agent_rdata_fifo:in_ready -> ddr3_ram_avl_agent:rdata_fifo_src_ready
+	wire          cmd_mux_src_valid;                                                                         // cmd_mux:src_valid -> ddr3_ram_avl_agent:cp_valid
+	wire  [120:0] cmd_mux_src_data;                                                                          // cmd_mux:src_data -> ddr3_ram_avl_agent:cp_data
+	wire          cmd_mux_src_ready;                                                                         // ddr3_ram_avl_agent:cp_ready -> cmd_mux:src_ready
+	wire   [20:0] cmd_mux_src_channel;                                                                       // cmd_mux:src_channel -> ddr3_ram_avl_agent:cp_channel
+	wire          cmd_mux_src_startofpacket;                                                                 // cmd_mux:src_startofpacket -> ddr3_ram_avl_agent:cp_startofpacket
+	wire          cmd_mux_src_endofpacket;                                                                   // cmd_mux:src_endofpacket -> ddr3_ram_avl_agent:cp_endofpacket
+	wire   [31:0] ext_flash_avl_csr_agent_m0_readdata;                                                       // ext_flash_avl_csr_translator:uav_readdata -> ext_flash_avl_csr_agent:m0_readdata
+	wire          ext_flash_avl_csr_agent_m0_waitrequest;                                                    // ext_flash_avl_csr_translator:uav_waitrequest -> ext_flash_avl_csr_agent:m0_waitrequest
+	wire          ext_flash_avl_csr_agent_m0_debugaccess;                                                    // ext_flash_avl_csr_agent:m0_debugaccess -> ext_flash_avl_csr_translator:uav_debugaccess
+	wire   [28:0] ext_flash_avl_csr_agent_m0_address;                                                        // ext_flash_avl_csr_agent:m0_address -> ext_flash_avl_csr_translator:uav_address
+	wire    [3:0] ext_flash_avl_csr_agent_m0_byteenable;                                                     // ext_flash_avl_csr_agent:m0_byteenable -> ext_flash_avl_csr_translator:uav_byteenable
+	wire          ext_flash_avl_csr_agent_m0_read;                                                           // ext_flash_avl_csr_agent:m0_read -> ext_flash_avl_csr_translator:uav_read
+	wire          ext_flash_avl_csr_agent_m0_readdatavalid;                                                  // ext_flash_avl_csr_translator:uav_readdatavalid -> ext_flash_avl_csr_agent:m0_readdatavalid
+	wire          ext_flash_avl_csr_agent_m0_lock;                                                           // ext_flash_avl_csr_agent:m0_lock -> ext_flash_avl_csr_translator:uav_lock
+	wire   [31:0] ext_flash_avl_csr_agent_m0_writedata;                                                      // ext_flash_avl_csr_agent:m0_writedata -> ext_flash_avl_csr_translator:uav_writedata
+	wire          ext_flash_avl_csr_agent_m0_write;                                                          // ext_flash_avl_csr_agent:m0_write -> ext_flash_avl_csr_translator:uav_write
+	wire    [2:0] ext_flash_avl_csr_agent_m0_burstcount;                                                     // ext_flash_avl_csr_agent:m0_burstcount -> ext_flash_avl_csr_translator:uav_burstcount
+	wire          ext_flash_avl_csr_agent_rf_source_valid;                                                   // ext_flash_avl_csr_agent:rf_source_valid -> ext_flash_avl_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] ext_flash_avl_csr_agent_rf_source_data;                                                    // ext_flash_avl_csr_agent:rf_source_data -> ext_flash_avl_csr_agent_rsp_fifo:in_data
+	wire          ext_flash_avl_csr_agent_rf_source_ready;                                                   // ext_flash_avl_csr_agent_rsp_fifo:in_ready -> ext_flash_avl_csr_agent:rf_source_ready
+	wire          ext_flash_avl_csr_agent_rf_source_startofpacket;                                           // ext_flash_avl_csr_agent:rf_source_startofpacket -> ext_flash_avl_csr_agent_rsp_fifo:in_startofpacket
+	wire          ext_flash_avl_csr_agent_rf_source_endofpacket;                                             // ext_flash_avl_csr_agent:rf_source_endofpacket -> ext_flash_avl_csr_agent_rsp_fifo:in_endofpacket
+	wire          ext_flash_avl_csr_agent_rsp_fifo_out_valid;                                                // ext_flash_avl_csr_agent_rsp_fifo:out_valid -> ext_flash_avl_csr_agent:rf_sink_valid
+	wire  [121:0] ext_flash_avl_csr_agent_rsp_fifo_out_data;                                                 // ext_flash_avl_csr_agent_rsp_fifo:out_data -> ext_flash_avl_csr_agent:rf_sink_data
+	wire          ext_flash_avl_csr_agent_rsp_fifo_out_ready;                                                // ext_flash_avl_csr_agent:rf_sink_ready -> ext_flash_avl_csr_agent_rsp_fifo:out_ready
+	wire          ext_flash_avl_csr_agent_rsp_fifo_out_startofpacket;                                        // ext_flash_avl_csr_agent_rsp_fifo:out_startofpacket -> ext_flash_avl_csr_agent:rf_sink_startofpacket
+	wire          ext_flash_avl_csr_agent_rsp_fifo_out_endofpacket;                                          // ext_flash_avl_csr_agent_rsp_fifo:out_endofpacket -> ext_flash_avl_csr_agent:rf_sink_endofpacket
+	wire          ext_flash_avl_csr_agent_rdata_fifo_src_valid;                                              // ext_flash_avl_csr_agent:rdata_fifo_src_valid -> ext_flash_avl_csr_agent_rdata_fifo:in_valid
+	wire   [33:0] ext_flash_avl_csr_agent_rdata_fifo_src_data;                                               // ext_flash_avl_csr_agent:rdata_fifo_src_data -> ext_flash_avl_csr_agent_rdata_fifo:in_data
+	wire          ext_flash_avl_csr_agent_rdata_fifo_src_ready;                                              // ext_flash_avl_csr_agent_rdata_fifo:in_ready -> ext_flash_avl_csr_agent:rdata_fifo_src_ready
+	wire          cmd_mux_001_src_valid;                                                                     // cmd_mux_001:src_valid -> ext_flash_avl_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_001_src_data;                                                                      // cmd_mux_001:src_data -> ext_flash_avl_csr_agent:cp_data
+	wire          cmd_mux_001_src_ready;                                                                     // ext_flash_avl_csr_agent:cp_ready -> cmd_mux_001:src_ready
+	wire   [20:0] cmd_mux_001_src_channel;                                                                   // cmd_mux_001:src_channel -> ext_flash_avl_csr_agent:cp_channel
+	wire          cmd_mux_001_src_startofpacket;                                                             // cmd_mux_001:src_startofpacket -> ext_flash_avl_csr_agent:cp_startofpacket
+	wire          cmd_mux_001_src_endofpacket;                                                               // cmd_mux_001:src_endofpacket -> ext_flash_avl_csr_agent:cp_endofpacket
+	wire   [31:0] ext_flash_avl_mem_agent_m0_readdata;                                                       // ext_flash_avl_mem_translator:uav_readdata -> ext_flash_avl_mem_agent:m0_readdata
+	wire          ext_flash_avl_mem_agent_m0_waitrequest;                                                    // ext_flash_avl_mem_translator:uav_waitrequest -> ext_flash_avl_mem_agent:m0_waitrequest
+	wire          ext_flash_avl_mem_agent_m0_debugaccess;                                                    // ext_flash_avl_mem_agent:m0_debugaccess -> ext_flash_avl_mem_translator:uav_debugaccess
+	wire   [28:0] ext_flash_avl_mem_agent_m0_address;                                                        // ext_flash_avl_mem_agent:m0_address -> ext_flash_avl_mem_translator:uav_address
+	wire    [3:0] ext_flash_avl_mem_agent_m0_byteenable;                                                     // ext_flash_avl_mem_agent:m0_byteenable -> ext_flash_avl_mem_translator:uav_byteenable
+	wire          ext_flash_avl_mem_agent_m0_read;                                                           // ext_flash_avl_mem_agent:m0_read -> ext_flash_avl_mem_translator:uav_read
+	wire          ext_flash_avl_mem_agent_m0_readdatavalid;                                                  // ext_flash_avl_mem_translator:uav_readdatavalid -> ext_flash_avl_mem_agent:m0_readdatavalid
+	wire          ext_flash_avl_mem_agent_m0_lock;                                                           // ext_flash_avl_mem_agent:m0_lock -> ext_flash_avl_mem_translator:uav_lock
+	wire   [31:0] ext_flash_avl_mem_agent_m0_writedata;                                                      // ext_flash_avl_mem_agent:m0_writedata -> ext_flash_avl_mem_translator:uav_writedata
+	wire          ext_flash_avl_mem_agent_m0_write;                                                          // ext_flash_avl_mem_agent:m0_write -> ext_flash_avl_mem_translator:uav_write
+	wire    [8:0] ext_flash_avl_mem_agent_m0_burstcount;                                                     // ext_flash_avl_mem_agent:m0_burstcount -> ext_flash_avl_mem_translator:uav_burstcount
+	wire          ext_flash_avl_mem_agent_rf_source_valid;                                                   // ext_flash_avl_mem_agent:rf_source_valid -> ext_flash_avl_mem_agent_rsp_fifo:in_valid
+	wire  [121:0] ext_flash_avl_mem_agent_rf_source_data;                                                    // ext_flash_avl_mem_agent:rf_source_data -> ext_flash_avl_mem_agent_rsp_fifo:in_data
+	wire          ext_flash_avl_mem_agent_rf_source_ready;                                                   // ext_flash_avl_mem_agent_rsp_fifo:in_ready -> ext_flash_avl_mem_agent:rf_source_ready
+	wire          ext_flash_avl_mem_agent_rf_source_startofpacket;                                           // ext_flash_avl_mem_agent:rf_source_startofpacket -> ext_flash_avl_mem_agent_rsp_fifo:in_startofpacket
+	wire          ext_flash_avl_mem_agent_rf_source_endofpacket;                                             // ext_flash_avl_mem_agent:rf_source_endofpacket -> ext_flash_avl_mem_agent_rsp_fifo:in_endofpacket
+	wire          ext_flash_avl_mem_agent_rsp_fifo_out_valid;                                                // ext_flash_avl_mem_agent_rsp_fifo:out_valid -> ext_flash_avl_mem_agent:rf_sink_valid
+	wire  [121:0] ext_flash_avl_mem_agent_rsp_fifo_out_data;                                                 // ext_flash_avl_mem_agent_rsp_fifo:out_data -> ext_flash_avl_mem_agent:rf_sink_data
+	wire          ext_flash_avl_mem_agent_rsp_fifo_out_ready;                                                // ext_flash_avl_mem_agent:rf_sink_ready -> ext_flash_avl_mem_agent_rsp_fifo:out_ready
+	wire          ext_flash_avl_mem_agent_rsp_fifo_out_startofpacket;                                        // ext_flash_avl_mem_agent_rsp_fifo:out_startofpacket -> ext_flash_avl_mem_agent:rf_sink_startofpacket
+	wire          ext_flash_avl_mem_agent_rsp_fifo_out_endofpacket;                                          // ext_flash_avl_mem_agent_rsp_fifo:out_endofpacket -> ext_flash_avl_mem_agent:rf_sink_endofpacket
+	wire          ext_flash_avl_mem_agent_rdata_fifo_src_valid;                                              // ext_flash_avl_mem_agent:rdata_fifo_src_valid -> ext_flash_avl_mem_agent_rdata_fifo:in_valid
+	wire   [33:0] ext_flash_avl_mem_agent_rdata_fifo_src_data;                                               // ext_flash_avl_mem_agent:rdata_fifo_src_data -> ext_flash_avl_mem_agent_rdata_fifo:in_data
+	wire          ext_flash_avl_mem_agent_rdata_fifo_src_ready;                                              // ext_flash_avl_mem_agent_rdata_fifo:in_ready -> ext_flash_avl_mem_agent:rdata_fifo_src_ready
+	wire   [31:0] eth_tse_control_port_agent_m0_readdata;                                                    // eth_tse_control_port_translator:uav_readdata -> eth_tse_control_port_agent:m0_readdata
+	wire          eth_tse_control_port_agent_m0_waitrequest;                                                 // eth_tse_control_port_translator:uav_waitrequest -> eth_tse_control_port_agent:m0_waitrequest
+	wire          eth_tse_control_port_agent_m0_debugaccess;                                                 // eth_tse_control_port_agent:m0_debugaccess -> eth_tse_control_port_translator:uav_debugaccess
+	wire   [28:0] eth_tse_control_port_agent_m0_address;                                                     // eth_tse_control_port_agent:m0_address -> eth_tse_control_port_translator:uav_address
+	wire    [3:0] eth_tse_control_port_agent_m0_byteenable;                                                  // eth_tse_control_port_agent:m0_byteenable -> eth_tse_control_port_translator:uav_byteenable
+	wire          eth_tse_control_port_agent_m0_read;                                                        // eth_tse_control_port_agent:m0_read -> eth_tse_control_port_translator:uav_read
+	wire          eth_tse_control_port_agent_m0_readdatavalid;                                               // eth_tse_control_port_translator:uav_readdatavalid -> eth_tse_control_port_agent:m0_readdatavalid
+	wire          eth_tse_control_port_agent_m0_lock;                                                        // eth_tse_control_port_agent:m0_lock -> eth_tse_control_port_translator:uav_lock
+	wire   [31:0] eth_tse_control_port_agent_m0_writedata;                                                   // eth_tse_control_port_agent:m0_writedata -> eth_tse_control_port_translator:uav_writedata
+	wire          eth_tse_control_port_agent_m0_write;                                                       // eth_tse_control_port_agent:m0_write -> eth_tse_control_port_translator:uav_write
+	wire    [2:0] eth_tse_control_port_agent_m0_burstcount;                                                  // eth_tse_control_port_agent:m0_burstcount -> eth_tse_control_port_translator:uav_burstcount
+	wire          eth_tse_control_port_agent_rf_source_valid;                                                // eth_tse_control_port_agent:rf_source_valid -> eth_tse_control_port_agent_rsp_fifo:in_valid
+	wire  [121:0] eth_tse_control_port_agent_rf_source_data;                                                 // eth_tse_control_port_agent:rf_source_data -> eth_tse_control_port_agent_rsp_fifo:in_data
+	wire          eth_tse_control_port_agent_rf_source_ready;                                                // eth_tse_control_port_agent_rsp_fifo:in_ready -> eth_tse_control_port_agent:rf_source_ready
+	wire          eth_tse_control_port_agent_rf_source_startofpacket;                                        // eth_tse_control_port_agent:rf_source_startofpacket -> eth_tse_control_port_agent_rsp_fifo:in_startofpacket
+	wire          eth_tse_control_port_agent_rf_source_endofpacket;                                          // eth_tse_control_port_agent:rf_source_endofpacket -> eth_tse_control_port_agent_rsp_fifo:in_endofpacket
+	wire          eth_tse_control_port_agent_rsp_fifo_out_valid;                                             // eth_tse_control_port_agent_rsp_fifo:out_valid -> eth_tse_control_port_agent:rf_sink_valid
+	wire  [121:0] eth_tse_control_port_agent_rsp_fifo_out_data;                                              // eth_tse_control_port_agent_rsp_fifo:out_data -> eth_tse_control_port_agent:rf_sink_data
+	wire          eth_tse_control_port_agent_rsp_fifo_out_ready;                                             // eth_tse_control_port_agent:rf_sink_ready -> eth_tse_control_port_agent_rsp_fifo:out_ready
+	wire          eth_tse_control_port_agent_rsp_fifo_out_startofpacket;                                     // eth_tse_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_control_port_agent:rf_sink_startofpacket
+	wire          eth_tse_control_port_agent_rsp_fifo_out_endofpacket;                                       // eth_tse_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_control_port_agent:rf_sink_endofpacket
+	wire          cmd_mux_003_src_valid;                                                                     // cmd_mux_003:src_valid -> eth_tse_control_port_agent:cp_valid
+	wire  [120:0] cmd_mux_003_src_data;                                                                      // cmd_mux_003:src_data -> eth_tse_control_port_agent:cp_data
+	wire          cmd_mux_003_src_ready;                                                                     // eth_tse_control_port_agent:cp_ready -> cmd_mux_003:src_ready
+	wire   [20:0] cmd_mux_003_src_channel;                                                                   // cmd_mux_003:src_channel -> eth_tse_control_port_agent:cp_channel
+	wire          cmd_mux_003_src_startofpacket;                                                             // cmd_mux_003:src_startofpacket -> eth_tse_control_port_agent:cp_startofpacket
+	wire          cmd_mux_003_src_endofpacket;                                                               // cmd_mux_003:src_endofpacket -> eth_tse_control_port_agent:cp_endofpacket
+	wire   [31:0] sysid_control_slave_agent_m0_readdata;                                                     // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_agent:m0_readdata
+	wire          sysid_control_slave_agent_m0_waitrequest;                                                  // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_agent:m0_waitrequest
+	wire          sysid_control_slave_agent_m0_debugaccess;                                                  // sysid_control_slave_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
+	wire   [28:0] sysid_control_slave_agent_m0_address;                                                      // sysid_control_slave_agent:m0_address -> sysid_control_slave_translator:uav_address
+	wire    [3:0] sysid_control_slave_agent_m0_byteenable;                                                   // sysid_control_slave_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
+	wire          sysid_control_slave_agent_m0_read;                                                         // sysid_control_slave_agent:m0_read -> sysid_control_slave_translator:uav_read
+	wire          sysid_control_slave_agent_m0_readdatavalid;                                                // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_agent:m0_readdatavalid
+	wire          sysid_control_slave_agent_m0_lock;                                                         // sysid_control_slave_agent:m0_lock -> sysid_control_slave_translator:uav_lock
+	wire   [31:0] sysid_control_slave_agent_m0_writedata;                                                    // sysid_control_slave_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
+	wire          sysid_control_slave_agent_m0_write;                                                        // sysid_control_slave_agent:m0_write -> sysid_control_slave_translator:uav_write
+	wire    [2:0] sysid_control_slave_agent_m0_burstcount;                                                   // sysid_control_slave_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
+	wire          sysid_control_slave_agent_rf_source_valid;                                                 // sysid_control_slave_agent:rf_source_valid -> sysid_control_slave_agent_rsp_fifo:in_valid
+	wire  [121:0] sysid_control_slave_agent_rf_source_data;                                                  // sysid_control_slave_agent:rf_source_data -> sysid_control_slave_agent_rsp_fifo:in_data
+	wire          sysid_control_slave_agent_rf_source_ready;                                                 // sysid_control_slave_agent_rsp_fifo:in_ready -> sysid_control_slave_agent:rf_source_ready
+	wire          sysid_control_slave_agent_rf_source_startofpacket;                                         // sysid_control_slave_agent:rf_source_startofpacket -> sysid_control_slave_agent_rsp_fifo:in_startofpacket
+	wire          sysid_control_slave_agent_rf_source_endofpacket;                                           // sysid_control_slave_agent:rf_source_endofpacket -> sysid_control_slave_agent_rsp_fifo:in_endofpacket
+	wire          sysid_control_slave_agent_rsp_fifo_out_valid;                                              // sysid_control_slave_agent_rsp_fifo:out_valid -> sysid_control_slave_agent:rf_sink_valid
+	wire  [121:0] sysid_control_slave_agent_rsp_fifo_out_data;                                               // sysid_control_slave_agent_rsp_fifo:out_data -> sysid_control_slave_agent:rf_sink_data
+	wire          sysid_control_slave_agent_rsp_fifo_out_ready;                                              // sysid_control_slave_agent:rf_sink_ready -> sysid_control_slave_agent_rsp_fifo:out_ready
+	wire          sysid_control_slave_agent_rsp_fifo_out_startofpacket;                                      // sysid_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_agent:rf_sink_startofpacket
+	wire          sysid_control_slave_agent_rsp_fifo_out_endofpacket;                                        // sysid_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_agent:rf_sink_endofpacket
+	wire          cmd_mux_004_src_valid;                                                                     // cmd_mux_004:src_valid -> sysid_control_slave_agent:cp_valid
+	wire  [120:0] cmd_mux_004_src_data;                                                                      // cmd_mux_004:src_data -> sysid_control_slave_agent:cp_data
+	wire          cmd_mux_004_src_ready;                                                                     // sysid_control_slave_agent:cp_ready -> cmd_mux_004:src_ready
+	wire   [20:0] cmd_mux_004_src_channel;                                                                   // cmd_mux_004:src_channel -> sysid_control_slave_agent:cp_channel
+	wire          cmd_mux_004_src_startofpacket;                                                             // cmd_mux_004:src_startofpacket -> sysid_control_slave_agent:cp_startofpacket
+	wire          cmd_mux_004_src_endofpacket;                                                               // cmd_mux_004:src_endofpacket -> sysid_control_slave_agent:cp_endofpacket
+	wire   [31:0] msgdma_tx_csr_agent_m0_readdata;                                                           // msgdma_tx_csr_translator:uav_readdata -> msgdma_tx_csr_agent:m0_readdata
+	wire          msgdma_tx_csr_agent_m0_waitrequest;                                                        // msgdma_tx_csr_translator:uav_waitrequest -> msgdma_tx_csr_agent:m0_waitrequest
+	wire          msgdma_tx_csr_agent_m0_debugaccess;                                                        // msgdma_tx_csr_agent:m0_debugaccess -> msgdma_tx_csr_translator:uav_debugaccess
+	wire   [28:0] msgdma_tx_csr_agent_m0_address;                                                            // msgdma_tx_csr_agent:m0_address -> msgdma_tx_csr_translator:uav_address
+	wire    [3:0] msgdma_tx_csr_agent_m0_byteenable;                                                         // msgdma_tx_csr_agent:m0_byteenable -> msgdma_tx_csr_translator:uav_byteenable
+	wire          msgdma_tx_csr_agent_m0_read;                                                               // msgdma_tx_csr_agent:m0_read -> msgdma_tx_csr_translator:uav_read
+	wire          msgdma_tx_csr_agent_m0_readdatavalid;                                                      // msgdma_tx_csr_translator:uav_readdatavalid -> msgdma_tx_csr_agent:m0_readdatavalid
+	wire          msgdma_tx_csr_agent_m0_lock;                                                               // msgdma_tx_csr_agent:m0_lock -> msgdma_tx_csr_translator:uav_lock
+	wire   [31:0] msgdma_tx_csr_agent_m0_writedata;                                                          // msgdma_tx_csr_agent:m0_writedata -> msgdma_tx_csr_translator:uav_writedata
+	wire          msgdma_tx_csr_agent_m0_write;                                                              // msgdma_tx_csr_agent:m0_write -> msgdma_tx_csr_translator:uav_write
+	wire    [2:0] msgdma_tx_csr_agent_m0_burstcount;                                                         // msgdma_tx_csr_agent:m0_burstcount -> msgdma_tx_csr_translator:uav_burstcount
+	wire          msgdma_tx_csr_agent_rf_source_valid;                                                       // msgdma_tx_csr_agent:rf_source_valid -> msgdma_tx_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] msgdma_tx_csr_agent_rf_source_data;                                                        // msgdma_tx_csr_agent:rf_source_data -> msgdma_tx_csr_agent_rsp_fifo:in_data
+	wire          msgdma_tx_csr_agent_rf_source_ready;                                                       // msgdma_tx_csr_agent_rsp_fifo:in_ready -> msgdma_tx_csr_agent:rf_source_ready
+	wire          msgdma_tx_csr_agent_rf_source_startofpacket;                                               // msgdma_tx_csr_agent:rf_source_startofpacket -> msgdma_tx_csr_agent_rsp_fifo:in_startofpacket
+	wire          msgdma_tx_csr_agent_rf_source_endofpacket;                                                 // msgdma_tx_csr_agent:rf_source_endofpacket -> msgdma_tx_csr_agent_rsp_fifo:in_endofpacket
+	wire          msgdma_tx_csr_agent_rsp_fifo_out_valid;                                                    // msgdma_tx_csr_agent_rsp_fifo:out_valid -> msgdma_tx_csr_agent:rf_sink_valid
+	wire  [121:0] msgdma_tx_csr_agent_rsp_fifo_out_data;                                                     // msgdma_tx_csr_agent_rsp_fifo:out_data -> msgdma_tx_csr_agent:rf_sink_data
+	wire          msgdma_tx_csr_agent_rsp_fifo_out_ready;                                                    // msgdma_tx_csr_agent:rf_sink_ready -> msgdma_tx_csr_agent_rsp_fifo:out_ready
+	wire          msgdma_tx_csr_agent_rsp_fifo_out_startofpacket;                                            // msgdma_tx_csr_agent_rsp_fifo:out_startofpacket -> msgdma_tx_csr_agent:rf_sink_startofpacket
+	wire          msgdma_tx_csr_agent_rsp_fifo_out_endofpacket;                                              // msgdma_tx_csr_agent_rsp_fifo:out_endofpacket -> msgdma_tx_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_005_src_valid;                                                                     // cmd_mux_005:src_valid -> msgdma_tx_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_005_src_data;                                                                      // cmd_mux_005:src_data -> msgdma_tx_csr_agent:cp_data
+	wire          cmd_mux_005_src_ready;                                                                     // msgdma_tx_csr_agent:cp_ready -> cmd_mux_005:src_ready
+	wire   [20:0] cmd_mux_005_src_channel;                                                                   // cmd_mux_005:src_channel -> msgdma_tx_csr_agent:cp_channel
+	wire          cmd_mux_005_src_startofpacket;                                                             // cmd_mux_005:src_startofpacket -> msgdma_tx_csr_agent:cp_startofpacket
+	wire          cmd_mux_005_src_endofpacket;                                                               // cmd_mux_005:src_endofpacket -> msgdma_tx_csr_agent:cp_endofpacket
+	wire   [31:0] msgdma_rx_csr_agent_m0_readdata;                                                           // msgdma_rx_csr_translator:uav_readdata -> msgdma_rx_csr_agent:m0_readdata
+	wire          msgdma_rx_csr_agent_m0_waitrequest;                                                        // msgdma_rx_csr_translator:uav_waitrequest -> msgdma_rx_csr_agent:m0_waitrequest
+	wire          msgdma_rx_csr_agent_m0_debugaccess;                                                        // msgdma_rx_csr_agent:m0_debugaccess -> msgdma_rx_csr_translator:uav_debugaccess
+	wire   [28:0] msgdma_rx_csr_agent_m0_address;                                                            // msgdma_rx_csr_agent:m0_address -> msgdma_rx_csr_translator:uav_address
+	wire    [3:0] msgdma_rx_csr_agent_m0_byteenable;                                                         // msgdma_rx_csr_agent:m0_byteenable -> msgdma_rx_csr_translator:uav_byteenable
+	wire          msgdma_rx_csr_agent_m0_read;                                                               // msgdma_rx_csr_agent:m0_read -> msgdma_rx_csr_translator:uav_read
+	wire          msgdma_rx_csr_agent_m0_readdatavalid;                                                      // msgdma_rx_csr_translator:uav_readdatavalid -> msgdma_rx_csr_agent:m0_readdatavalid
+	wire          msgdma_rx_csr_agent_m0_lock;                                                               // msgdma_rx_csr_agent:m0_lock -> msgdma_rx_csr_translator:uav_lock
+	wire   [31:0] msgdma_rx_csr_agent_m0_writedata;                                                          // msgdma_rx_csr_agent:m0_writedata -> msgdma_rx_csr_translator:uav_writedata
+	wire          msgdma_rx_csr_agent_m0_write;                                                              // msgdma_rx_csr_agent:m0_write -> msgdma_rx_csr_translator:uav_write
+	wire    [2:0] msgdma_rx_csr_agent_m0_burstcount;                                                         // msgdma_rx_csr_agent:m0_burstcount -> msgdma_rx_csr_translator:uav_burstcount
+	wire          msgdma_rx_csr_agent_rf_source_valid;                                                       // msgdma_rx_csr_agent:rf_source_valid -> msgdma_rx_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] msgdma_rx_csr_agent_rf_source_data;                                                        // msgdma_rx_csr_agent:rf_source_data -> msgdma_rx_csr_agent_rsp_fifo:in_data
+	wire          msgdma_rx_csr_agent_rf_source_ready;                                                       // msgdma_rx_csr_agent_rsp_fifo:in_ready -> msgdma_rx_csr_agent:rf_source_ready
+	wire          msgdma_rx_csr_agent_rf_source_startofpacket;                                               // msgdma_rx_csr_agent:rf_source_startofpacket -> msgdma_rx_csr_agent_rsp_fifo:in_startofpacket
+	wire          msgdma_rx_csr_agent_rf_source_endofpacket;                                                 // msgdma_rx_csr_agent:rf_source_endofpacket -> msgdma_rx_csr_agent_rsp_fifo:in_endofpacket
+	wire          msgdma_rx_csr_agent_rsp_fifo_out_valid;                                                    // msgdma_rx_csr_agent_rsp_fifo:out_valid -> msgdma_rx_csr_agent:rf_sink_valid
+	wire  [121:0] msgdma_rx_csr_agent_rsp_fifo_out_data;                                                     // msgdma_rx_csr_agent_rsp_fifo:out_data -> msgdma_rx_csr_agent:rf_sink_data
+	wire          msgdma_rx_csr_agent_rsp_fifo_out_ready;                                                    // msgdma_rx_csr_agent:rf_sink_ready -> msgdma_rx_csr_agent_rsp_fifo:out_ready
+	wire          msgdma_rx_csr_agent_rsp_fifo_out_startofpacket;                                            // msgdma_rx_csr_agent_rsp_fifo:out_startofpacket -> msgdma_rx_csr_agent:rf_sink_startofpacket
+	wire          msgdma_rx_csr_agent_rsp_fifo_out_endofpacket;                                              // msgdma_rx_csr_agent_rsp_fifo:out_endofpacket -> msgdma_rx_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_006_src_valid;                                                                     // cmd_mux_006:src_valid -> msgdma_rx_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_006_src_data;                                                                      // cmd_mux_006:src_data -> msgdma_rx_csr_agent:cp_data
+	wire          cmd_mux_006_src_ready;                                                                     // msgdma_rx_csr_agent:cp_ready -> cmd_mux_006:src_ready
+	wire   [20:0] cmd_mux_006_src_channel;                                                                   // cmd_mux_006:src_channel -> msgdma_rx_csr_agent:cp_channel
+	wire          cmd_mux_006_src_startofpacket;                                                             // cmd_mux_006:src_startofpacket -> msgdma_rx_csr_agent:cp_startofpacket
+	wire          cmd_mux_006_src_endofpacket;                                                               // cmd_mux_006:src_endofpacket -> msgdma_rx_csr_agent:cp_endofpacket
+	wire   [31:0] onchip_flash_csr_agent_m0_readdata;                                                        // onchip_flash_csr_translator:uav_readdata -> onchip_flash_csr_agent:m0_readdata
+	wire          onchip_flash_csr_agent_m0_waitrequest;                                                     // onchip_flash_csr_translator:uav_waitrequest -> onchip_flash_csr_agent:m0_waitrequest
+	wire          onchip_flash_csr_agent_m0_debugaccess;                                                     // onchip_flash_csr_agent:m0_debugaccess -> onchip_flash_csr_translator:uav_debugaccess
+	wire   [28:0] onchip_flash_csr_agent_m0_address;                                                         // onchip_flash_csr_agent:m0_address -> onchip_flash_csr_translator:uav_address
+	wire    [3:0] onchip_flash_csr_agent_m0_byteenable;                                                      // onchip_flash_csr_agent:m0_byteenable -> onchip_flash_csr_translator:uav_byteenable
+	wire          onchip_flash_csr_agent_m0_read;                                                            // onchip_flash_csr_agent:m0_read -> onchip_flash_csr_translator:uav_read
+	wire          onchip_flash_csr_agent_m0_readdatavalid;                                                   // onchip_flash_csr_translator:uav_readdatavalid -> onchip_flash_csr_agent:m0_readdatavalid
+	wire          onchip_flash_csr_agent_m0_lock;                                                            // onchip_flash_csr_agent:m0_lock -> onchip_flash_csr_translator:uav_lock
+	wire   [31:0] onchip_flash_csr_agent_m0_writedata;                                                       // onchip_flash_csr_agent:m0_writedata -> onchip_flash_csr_translator:uav_writedata
+	wire          onchip_flash_csr_agent_m0_write;                                                           // onchip_flash_csr_agent:m0_write -> onchip_flash_csr_translator:uav_write
+	wire    [2:0] onchip_flash_csr_agent_m0_burstcount;                                                      // onchip_flash_csr_agent:m0_burstcount -> onchip_flash_csr_translator:uav_burstcount
+	wire          onchip_flash_csr_agent_rf_source_valid;                                                    // onchip_flash_csr_agent:rf_source_valid -> onchip_flash_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] onchip_flash_csr_agent_rf_source_data;                                                     // onchip_flash_csr_agent:rf_source_data -> onchip_flash_csr_agent_rsp_fifo:in_data
+	wire          onchip_flash_csr_agent_rf_source_ready;                                                    // onchip_flash_csr_agent_rsp_fifo:in_ready -> onchip_flash_csr_agent:rf_source_ready
+	wire          onchip_flash_csr_agent_rf_source_startofpacket;                                            // onchip_flash_csr_agent:rf_source_startofpacket -> onchip_flash_csr_agent_rsp_fifo:in_startofpacket
+	wire          onchip_flash_csr_agent_rf_source_endofpacket;                                              // onchip_flash_csr_agent:rf_source_endofpacket -> onchip_flash_csr_agent_rsp_fifo:in_endofpacket
+	wire          onchip_flash_csr_agent_rsp_fifo_out_valid;                                                 // onchip_flash_csr_agent_rsp_fifo:out_valid -> onchip_flash_csr_agent:rf_sink_valid
+	wire  [121:0] onchip_flash_csr_agent_rsp_fifo_out_data;                                                  // onchip_flash_csr_agent_rsp_fifo:out_data -> onchip_flash_csr_agent:rf_sink_data
+	wire          onchip_flash_csr_agent_rsp_fifo_out_ready;                                                 // onchip_flash_csr_agent:rf_sink_ready -> onchip_flash_csr_agent_rsp_fifo:out_ready
+	wire          onchip_flash_csr_agent_rsp_fifo_out_startofpacket;                                         // onchip_flash_csr_agent_rsp_fifo:out_startofpacket -> onchip_flash_csr_agent:rf_sink_startofpacket
+	wire          onchip_flash_csr_agent_rsp_fifo_out_endofpacket;                                           // onchip_flash_csr_agent_rsp_fifo:out_endofpacket -> onchip_flash_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_007_src_valid;                                                                     // cmd_mux_007:src_valid -> onchip_flash_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_007_src_data;                                                                      // cmd_mux_007:src_data -> onchip_flash_csr_agent:cp_data
+	wire          cmd_mux_007_src_ready;                                                                     // onchip_flash_csr_agent:cp_ready -> cmd_mux_007:src_ready
+	wire   [20:0] cmd_mux_007_src_channel;                                                                   // cmd_mux_007:src_channel -> onchip_flash_csr_agent:cp_channel
+	wire          cmd_mux_007_src_startofpacket;                                                             // cmd_mux_007:src_startofpacket -> onchip_flash_csr_agent:cp_startofpacket
+	wire          cmd_mux_007_src_endofpacket;                                                               // cmd_mux_007:src_endofpacket -> onchip_flash_csr_agent:cp_endofpacket
+	wire   [31:0] udp_generator_csr_agent_m0_readdata;                                                       // udp_generator_csr_translator:uav_readdata -> udp_generator_csr_agent:m0_readdata
+	wire          udp_generator_csr_agent_m0_waitrequest;                                                    // udp_generator_csr_translator:uav_waitrequest -> udp_generator_csr_agent:m0_waitrequest
+	wire          udp_generator_csr_agent_m0_debugaccess;                                                    // udp_generator_csr_agent:m0_debugaccess -> udp_generator_csr_translator:uav_debugaccess
+	wire   [28:0] udp_generator_csr_agent_m0_address;                                                        // udp_generator_csr_agent:m0_address -> udp_generator_csr_translator:uav_address
+	wire    [3:0] udp_generator_csr_agent_m0_byteenable;                                                     // udp_generator_csr_agent:m0_byteenable -> udp_generator_csr_translator:uav_byteenable
+	wire          udp_generator_csr_agent_m0_read;                                                           // udp_generator_csr_agent:m0_read -> udp_generator_csr_translator:uav_read
+	wire          udp_generator_csr_agent_m0_readdatavalid;                                                  // udp_generator_csr_translator:uav_readdatavalid -> udp_generator_csr_agent:m0_readdatavalid
+	wire          udp_generator_csr_agent_m0_lock;                                                           // udp_generator_csr_agent:m0_lock -> udp_generator_csr_translator:uav_lock
+	wire   [31:0] udp_generator_csr_agent_m0_writedata;                                                      // udp_generator_csr_agent:m0_writedata -> udp_generator_csr_translator:uav_writedata
+	wire          udp_generator_csr_agent_m0_write;                                                          // udp_generator_csr_agent:m0_write -> udp_generator_csr_translator:uav_write
+	wire    [2:0] udp_generator_csr_agent_m0_burstcount;                                                     // udp_generator_csr_agent:m0_burstcount -> udp_generator_csr_translator:uav_burstcount
+	wire          udp_generator_csr_agent_rf_source_valid;                                                   // udp_generator_csr_agent:rf_source_valid -> udp_generator_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] udp_generator_csr_agent_rf_source_data;                                                    // udp_generator_csr_agent:rf_source_data -> udp_generator_csr_agent_rsp_fifo:in_data
+	wire          udp_generator_csr_agent_rf_source_ready;                                                   // udp_generator_csr_agent_rsp_fifo:in_ready -> udp_generator_csr_agent:rf_source_ready
+	wire          udp_generator_csr_agent_rf_source_startofpacket;                                           // udp_generator_csr_agent:rf_source_startofpacket -> udp_generator_csr_agent_rsp_fifo:in_startofpacket
+	wire          udp_generator_csr_agent_rf_source_endofpacket;                                             // udp_generator_csr_agent:rf_source_endofpacket -> udp_generator_csr_agent_rsp_fifo:in_endofpacket
+	wire          udp_generator_csr_agent_rsp_fifo_out_valid;                                                // udp_generator_csr_agent_rsp_fifo:out_valid -> udp_generator_csr_agent:rf_sink_valid
+	wire  [121:0] udp_generator_csr_agent_rsp_fifo_out_data;                                                 // udp_generator_csr_agent_rsp_fifo:out_data -> udp_generator_csr_agent:rf_sink_data
+	wire          udp_generator_csr_agent_rsp_fifo_out_ready;                                                // udp_generator_csr_agent:rf_sink_ready -> udp_generator_csr_agent_rsp_fifo:out_ready
+	wire          udp_generator_csr_agent_rsp_fifo_out_startofpacket;                                        // udp_generator_csr_agent_rsp_fifo:out_startofpacket -> udp_generator_csr_agent:rf_sink_startofpacket
+	wire          udp_generator_csr_agent_rsp_fifo_out_endofpacket;                                          // udp_generator_csr_agent_rsp_fifo:out_endofpacket -> udp_generator_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_008_src_valid;                                                                     // cmd_mux_008:src_valid -> udp_generator_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_008_src_data;                                                                      // cmd_mux_008:src_data -> udp_generator_csr_agent:cp_data
+	wire          cmd_mux_008_src_ready;                                                                     // udp_generator_csr_agent:cp_ready -> cmd_mux_008:src_ready
+	wire   [20:0] cmd_mux_008_src_channel;                                                                   // cmd_mux_008:src_channel -> udp_generator_csr_agent:cp_channel
+	wire          cmd_mux_008_src_startofpacket;                                                             // cmd_mux_008:src_startofpacket -> udp_generator_csr_agent:cp_startofpacket
+	wire          cmd_mux_008_src_endofpacket;                                                               // cmd_mux_008:src_endofpacket -> udp_generator_csr_agent:cp_endofpacket
+	wire   [31:0] sensor_interface_csr_agent_m0_readdata;                                                    // sensor_interface_csr_translator:uav_readdata -> sensor_interface_csr_agent:m0_readdata
+	wire          sensor_interface_csr_agent_m0_waitrequest;                                                 // sensor_interface_csr_translator:uav_waitrequest -> sensor_interface_csr_agent:m0_waitrequest
+	wire          sensor_interface_csr_agent_m0_debugaccess;                                                 // sensor_interface_csr_agent:m0_debugaccess -> sensor_interface_csr_translator:uav_debugaccess
+	wire   [28:0] sensor_interface_csr_agent_m0_address;                                                     // sensor_interface_csr_agent:m0_address -> sensor_interface_csr_translator:uav_address
+	wire    [3:0] sensor_interface_csr_agent_m0_byteenable;                                                  // sensor_interface_csr_agent:m0_byteenable -> sensor_interface_csr_translator:uav_byteenable
+	wire          sensor_interface_csr_agent_m0_read;                                                        // sensor_interface_csr_agent:m0_read -> sensor_interface_csr_translator:uav_read
+	wire          sensor_interface_csr_agent_m0_readdatavalid;                                               // sensor_interface_csr_translator:uav_readdatavalid -> sensor_interface_csr_agent:m0_readdatavalid
+	wire          sensor_interface_csr_agent_m0_lock;                                                        // sensor_interface_csr_agent:m0_lock -> sensor_interface_csr_translator:uav_lock
+	wire   [31:0] sensor_interface_csr_agent_m0_writedata;                                                   // sensor_interface_csr_agent:m0_writedata -> sensor_interface_csr_translator:uav_writedata
+	wire          sensor_interface_csr_agent_m0_write;                                                       // sensor_interface_csr_agent:m0_write -> sensor_interface_csr_translator:uav_write
+	wire    [2:0] sensor_interface_csr_agent_m0_burstcount;                                                  // sensor_interface_csr_agent:m0_burstcount -> sensor_interface_csr_translator:uav_burstcount
+	wire          sensor_interface_csr_agent_rf_source_valid;                                                // sensor_interface_csr_agent:rf_source_valid -> sensor_interface_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] sensor_interface_csr_agent_rf_source_data;                                                 // sensor_interface_csr_agent:rf_source_data -> sensor_interface_csr_agent_rsp_fifo:in_data
+	wire          sensor_interface_csr_agent_rf_source_ready;                                                // sensor_interface_csr_agent_rsp_fifo:in_ready -> sensor_interface_csr_agent:rf_source_ready
+	wire          sensor_interface_csr_agent_rf_source_startofpacket;                                        // sensor_interface_csr_agent:rf_source_startofpacket -> sensor_interface_csr_agent_rsp_fifo:in_startofpacket
+	wire          sensor_interface_csr_agent_rf_source_endofpacket;                                          // sensor_interface_csr_agent:rf_source_endofpacket -> sensor_interface_csr_agent_rsp_fifo:in_endofpacket
+	wire          sensor_interface_csr_agent_rsp_fifo_out_valid;                                             // sensor_interface_csr_agent_rsp_fifo:out_valid -> sensor_interface_csr_agent:rf_sink_valid
+	wire  [121:0] sensor_interface_csr_agent_rsp_fifo_out_data;                                              // sensor_interface_csr_agent_rsp_fifo:out_data -> sensor_interface_csr_agent:rf_sink_data
+	wire          sensor_interface_csr_agent_rsp_fifo_out_ready;                                             // sensor_interface_csr_agent:rf_sink_ready -> sensor_interface_csr_agent_rsp_fifo:out_ready
+	wire          sensor_interface_csr_agent_rsp_fifo_out_startofpacket;                                     // sensor_interface_csr_agent_rsp_fifo:out_startofpacket -> sensor_interface_csr_agent:rf_sink_startofpacket
+	wire          sensor_interface_csr_agent_rsp_fifo_out_endofpacket;                                       // sensor_interface_csr_agent_rsp_fifo:out_endofpacket -> sensor_interface_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_009_src_valid;                                                                     // cmd_mux_009:src_valid -> sensor_interface_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_009_src_data;                                                                      // cmd_mux_009:src_data -> sensor_interface_csr_agent:cp_data
+	wire          cmd_mux_009_src_ready;                                                                     // sensor_interface_csr_agent:cp_ready -> cmd_mux_009:src_ready
+	wire   [20:0] cmd_mux_009_src_channel;                                                                   // cmd_mux_009:src_channel -> sensor_interface_csr_agent:cp_channel
+	wire          cmd_mux_009_src_startofpacket;                                                             // cmd_mux_009:src_startofpacket -> sensor_interface_csr_agent:cp_startofpacket
+	wire          cmd_mux_009_src_endofpacket;                                                               // cmd_mux_009:src_endofpacket -> sensor_interface_csr_agent:cp_endofpacket
+	wire   [31:0] onchip_flash_data_agent_m0_readdata;                                                       // onchip_flash_data_translator:uav_readdata -> onchip_flash_data_agent:m0_readdata
+	wire          onchip_flash_data_agent_m0_waitrequest;                                                    // onchip_flash_data_translator:uav_waitrequest -> onchip_flash_data_agent:m0_waitrequest
+	wire          onchip_flash_data_agent_m0_debugaccess;                                                    // onchip_flash_data_agent:m0_debugaccess -> onchip_flash_data_translator:uav_debugaccess
+	wire   [28:0] onchip_flash_data_agent_m0_address;                                                        // onchip_flash_data_agent:m0_address -> onchip_flash_data_translator:uav_address
+	wire    [3:0] onchip_flash_data_agent_m0_byteenable;                                                     // onchip_flash_data_agent:m0_byteenable -> onchip_flash_data_translator:uav_byteenable
+	wire          onchip_flash_data_agent_m0_read;                                                           // onchip_flash_data_agent:m0_read -> onchip_flash_data_translator:uav_read
+	wire          onchip_flash_data_agent_m0_readdatavalid;                                                  // onchip_flash_data_translator:uav_readdatavalid -> onchip_flash_data_agent:m0_readdatavalid
+	wire          onchip_flash_data_agent_m0_lock;                                                           // onchip_flash_data_agent:m0_lock -> onchip_flash_data_translator:uav_lock
+	wire   [31:0] onchip_flash_data_agent_m0_writedata;                                                      // onchip_flash_data_agent:m0_writedata -> onchip_flash_data_translator:uav_writedata
+	wire          onchip_flash_data_agent_m0_write;                                                          // onchip_flash_data_agent:m0_write -> onchip_flash_data_translator:uav_write
+	wire    [5:0] onchip_flash_data_agent_m0_burstcount;                                                     // onchip_flash_data_agent:m0_burstcount -> onchip_flash_data_translator:uav_burstcount
+	wire          onchip_flash_data_agent_rf_source_valid;                                                   // onchip_flash_data_agent:rf_source_valid -> onchip_flash_data_agent_rsp_fifo:in_valid
+	wire  [121:0] onchip_flash_data_agent_rf_source_data;                                                    // onchip_flash_data_agent:rf_source_data -> onchip_flash_data_agent_rsp_fifo:in_data
+	wire          onchip_flash_data_agent_rf_source_ready;                                                   // onchip_flash_data_agent_rsp_fifo:in_ready -> onchip_flash_data_agent:rf_source_ready
+	wire          onchip_flash_data_agent_rf_source_startofpacket;                                           // onchip_flash_data_agent:rf_source_startofpacket -> onchip_flash_data_agent_rsp_fifo:in_startofpacket
+	wire          onchip_flash_data_agent_rf_source_endofpacket;                                             // onchip_flash_data_agent:rf_source_endofpacket -> onchip_flash_data_agent_rsp_fifo:in_endofpacket
+	wire          onchip_flash_data_agent_rsp_fifo_out_valid;                                                // onchip_flash_data_agent_rsp_fifo:out_valid -> onchip_flash_data_agent:rf_sink_valid
+	wire  [121:0] onchip_flash_data_agent_rsp_fifo_out_data;                                                 // onchip_flash_data_agent_rsp_fifo:out_data -> onchip_flash_data_agent:rf_sink_data
+	wire          onchip_flash_data_agent_rsp_fifo_out_ready;                                                // onchip_flash_data_agent:rf_sink_ready -> onchip_flash_data_agent_rsp_fifo:out_ready
+	wire          onchip_flash_data_agent_rsp_fifo_out_startofpacket;                                        // onchip_flash_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_data_agent:rf_sink_startofpacket
+	wire          onchip_flash_data_agent_rsp_fifo_out_endofpacket;                                          // onchip_flash_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_data_agent:rf_sink_endofpacket
+	wire          cmd_mux_010_src_valid;                                                                     // cmd_mux_010:src_valid -> onchip_flash_data_agent:cp_valid
+	wire  [120:0] cmd_mux_010_src_data;                                                                      // cmd_mux_010:src_data -> onchip_flash_data_agent:cp_data
+	wire          cmd_mux_010_src_ready;                                                                     // onchip_flash_data_agent:cp_ready -> cmd_mux_010:src_ready
+	wire   [20:0] cmd_mux_010_src_channel;                                                                   // cmd_mux_010:src_channel -> onchip_flash_data_agent:cp_channel
+	wire          cmd_mux_010_src_startofpacket;                                                             // cmd_mux_010:src_startofpacket -> onchip_flash_data_agent:cp_startofpacket
+	wire          cmd_mux_010_src_endofpacket;                                                               // cmd_mux_010:src_endofpacket -> onchip_flash_data_agent:cp_endofpacket
+	wire   [31:0] cpu_debug_mem_slave_agent_m0_readdata;                                                     // cpu_debug_mem_slave_translator:uav_readdata -> cpu_debug_mem_slave_agent:m0_readdata
+	wire          cpu_debug_mem_slave_agent_m0_waitrequest;                                                  // cpu_debug_mem_slave_translator:uav_waitrequest -> cpu_debug_mem_slave_agent:m0_waitrequest
+	wire          cpu_debug_mem_slave_agent_m0_debugaccess;                                                  // cpu_debug_mem_slave_agent:m0_debugaccess -> cpu_debug_mem_slave_translator:uav_debugaccess
+	wire   [28:0] cpu_debug_mem_slave_agent_m0_address;                                                      // cpu_debug_mem_slave_agent:m0_address -> cpu_debug_mem_slave_translator:uav_address
+	wire    [3:0] cpu_debug_mem_slave_agent_m0_byteenable;                                                   // cpu_debug_mem_slave_agent:m0_byteenable -> cpu_debug_mem_slave_translator:uav_byteenable
+	wire          cpu_debug_mem_slave_agent_m0_read;                                                         // cpu_debug_mem_slave_agent:m0_read -> cpu_debug_mem_slave_translator:uav_read
+	wire          cpu_debug_mem_slave_agent_m0_readdatavalid;                                                // cpu_debug_mem_slave_translator:uav_readdatavalid -> cpu_debug_mem_slave_agent:m0_readdatavalid
+	wire          cpu_debug_mem_slave_agent_m0_lock;                                                         // cpu_debug_mem_slave_agent:m0_lock -> cpu_debug_mem_slave_translator:uav_lock
+	wire   [31:0] cpu_debug_mem_slave_agent_m0_writedata;                                                    // cpu_debug_mem_slave_agent:m0_writedata -> cpu_debug_mem_slave_translator:uav_writedata
+	wire          cpu_debug_mem_slave_agent_m0_write;                                                        // cpu_debug_mem_slave_agent:m0_write -> cpu_debug_mem_slave_translator:uav_write
+	wire    [2:0] cpu_debug_mem_slave_agent_m0_burstcount;                                                   // cpu_debug_mem_slave_agent:m0_burstcount -> cpu_debug_mem_slave_translator:uav_burstcount
+	wire          cpu_debug_mem_slave_agent_rf_source_valid;                                                 // cpu_debug_mem_slave_agent:rf_source_valid -> cpu_debug_mem_slave_agent_rsp_fifo:in_valid
+	wire  [121:0] cpu_debug_mem_slave_agent_rf_source_data;                                                  // cpu_debug_mem_slave_agent:rf_source_data -> cpu_debug_mem_slave_agent_rsp_fifo:in_data
+	wire          cpu_debug_mem_slave_agent_rf_source_ready;                                                 // cpu_debug_mem_slave_agent_rsp_fifo:in_ready -> cpu_debug_mem_slave_agent:rf_source_ready
+	wire          cpu_debug_mem_slave_agent_rf_source_startofpacket;                                         // cpu_debug_mem_slave_agent:rf_source_startofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_startofpacket
+	wire          cpu_debug_mem_slave_agent_rf_source_endofpacket;                                           // cpu_debug_mem_slave_agent:rf_source_endofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_endofpacket
+	wire          cpu_debug_mem_slave_agent_rsp_fifo_out_valid;                                              // cpu_debug_mem_slave_agent_rsp_fifo:out_valid -> cpu_debug_mem_slave_agent:rf_sink_valid
+	wire  [121:0] cpu_debug_mem_slave_agent_rsp_fifo_out_data;                                               // cpu_debug_mem_slave_agent_rsp_fifo:out_data -> cpu_debug_mem_slave_agent:rf_sink_data
+	wire          cpu_debug_mem_slave_agent_rsp_fifo_out_ready;                                              // cpu_debug_mem_slave_agent:rf_sink_ready -> cpu_debug_mem_slave_agent_rsp_fifo:out_ready
+	wire          cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket;                                      // cpu_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> cpu_debug_mem_slave_agent:rf_sink_startofpacket
+	wire          cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket;                                        // cpu_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> cpu_debug_mem_slave_agent:rf_sink_endofpacket
+	wire          cmd_mux_011_src_valid;                                                                     // cmd_mux_011:src_valid -> cpu_debug_mem_slave_agent:cp_valid
+	wire  [120:0] cmd_mux_011_src_data;                                                                      // cmd_mux_011:src_data -> cpu_debug_mem_slave_agent:cp_data
+	wire          cmd_mux_011_src_ready;                                                                     // cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_011:src_ready
+	wire   [20:0] cmd_mux_011_src_channel;                                                                   // cmd_mux_011:src_channel -> cpu_debug_mem_slave_agent:cp_channel
+	wire          cmd_mux_011_src_startofpacket;                                                             // cmd_mux_011:src_startofpacket -> cpu_debug_mem_slave_agent:cp_startofpacket
+	wire          cmd_mux_011_src_endofpacket;                                                               // cmd_mux_011:src_endofpacket -> cpu_debug_mem_slave_agent:cp_endofpacket
+	wire   [31:0] msgdma_tx_prefetcher_csr_agent_m0_readdata;                                                // msgdma_tx_prefetcher_csr_translator:uav_readdata -> msgdma_tx_prefetcher_csr_agent:m0_readdata
+	wire          msgdma_tx_prefetcher_csr_agent_m0_waitrequest;                                             // msgdma_tx_prefetcher_csr_translator:uav_waitrequest -> msgdma_tx_prefetcher_csr_agent:m0_waitrequest
+	wire          msgdma_tx_prefetcher_csr_agent_m0_debugaccess;                                             // msgdma_tx_prefetcher_csr_agent:m0_debugaccess -> msgdma_tx_prefetcher_csr_translator:uav_debugaccess
+	wire   [28:0] msgdma_tx_prefetcher_csr_agent_m0_address;                                                 // msgdma_tx_prefetcher_csr_agent:m0_address -> msgdma_tx_prefetcher_csr_translator:uav_address
+	wire    [3:0] msgdma_tx_prefetcher_csr_agent_m0_byteenable;                                              // msgdma_tx_prefetcher_csr_agent:m0_byteenable -> msgdma_tx_prefetcher_csr_translator:uav_byteenable
+	wire          msgdma_tx_prefetcher_csr_agent_m0_read;                                                    // msgdma_tx_prefetcher_csr_agent:m0_read -> msgdma_tx_prefetcher_csr_translator:uav_read
+	wire          msgdma_tx_prefetcher_csr_agent_m0_readdatavalid;                                           // msgdma_tx_prefetcher_csr_translator:uav_readdatavalid -> msgdma_tx_prefetcher_csr_agent:m0_readdatavalid
+	wire          msgdma_tx_prefetcher_csr_agent_m0_lock;                                                    // msgdma_tx_prefetcher_csr_agent:m0_lock -> msgdma_tx_prefetcher_csr_translator:uav_lock
+	wire   [31:0] msgdma_tx_prefetcher_csr_agent_m0_writedata;                                               // msgdma_tx_prefetcher_csr_agent:m0_writedata -> msgdma_tx_prefetcher_csr_translator:uav_writedata
+	wire          msgdma_tx_prefetcher_csr_agent_m0_write;                                                   // msgdma_tx_prefetcher_csr_agent:m0_write -> msgdma_tx_prefetcher_csr_translator:uav_write
+	wire    [2:0] msgdma_tx_prefetcher_csr_agent_m0_burstcount;                                              // msgdma_tx_prefetcher_csr_agent:m0_burstcount -> msgdma_tx_prefetcher_csr_translator:uav_burstcount
+	wire          msgdma_tx_prefetcher_csr_agent_rf_source_valid;                                            // msgdma_tx_prefetcher_csr_agent:rf_source_valid -> msgdma_tx_prefetcher_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] msgdma_tx_prefetcher_csr_agent_rf_source_data;                                             // msgdma_tx_prefetcher_csr_agent:rf_source_data -> msgdma_tx_prefetcher_csr_agent_rsp_fifo:in_data
+	wire          msgdma_tx_prefetcher_csr_agent_rf_source_ready;                                            // msgdma_tx_prefetcher_csr_agent_rsp_fifo:in_ready -> msgdma_tx_prefetcher_csr_agent:rf_source_ready
+	wire          msgdma_tx_prefetcher_csr_agent_rf_source_startofpacket;                                    // msgdma_tx_prefetcher_csr_agent:rf_source_startofpacket -> msgdma_tx_prefetcher_csr_agent_rsp_fifo:in_startofpacket
+	wire          msgdma_tx_prefetcher_csr_agent_rf_source_endofpacket;                                      // msgdma_tx_prefetcher_csr_agent:rf_source_endofpacket -> msgdma_tx_prefetcher_csr_agent_rsp_fifo:in_endofpacket
+	wire          msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_valid;                                         // msgdma_tx_prefetcher_csr_agent_rsp_fifo:out_valid -> msgdma_tx_prefetcher_csr_agent:rf_sink_valid
+	wire  [121:0] msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_data;                                          // msgdma_tx_prefetcher_csr_agent_rsp_fifo:out_data -> msgdma_tx_prefetcher_csr_agent:rf_sink_data
+	wire          msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_ready;                                         // msgdma_tx_prefetcher_csr_agent:rf_sink_ready -> msgdma_tx_prefetcher_csr_agent_rsp_fifo:out_ready
+	wire          msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_startofpacket;                                 // msgdma_tx_prefetcher_csr_agent_rsp_fifo:out_startofpacket -> msgdma_tx_prefetcher_csr_agent:rf_sink_startofpacket
+	wire          msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_endofpacket;                                   // msgdma_tx_prefetcher_csr_agent_rsp_fifo:out_endofpacket -> msgdma_tx_prefetcher_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_012_src_valid;                                                                     // cmd_mux_012:src_valid -> msgdma_tx_prefetcher_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_012_src_data;                                                                      // cmd_mux_012:src_data -> msgdma_tx_prefetcher_csr_agent:cp_data
+	wire          cmd_mux_012_src_ready;                                                                     // msgdma_tx_prefetcher_csr_agent:cp_ready -> cmd_mux_012:src_ready
+	wire   [20:0] cmd_mux_012_src_channel;                                                                   // cmd_mux_012:src_channel -> msgdma_tx_prefetcher_csr_agent:cp_channel
+	wire          cmd_mux_012_src_startofpacket;                                                             // cmd_mux_012:src_startofpacket -> msgdma_tx_prefetcher_csr_agent:cp_startofpacket
+	wire          cmd_mux_012_src_endofpacket;                                                               // cmd_mux_012:src_endofpacket -> msgdma_tx_prefetcher_csr_agent:cp_endofpacket
+	wire   [31:0] msgdma_rx_prefetcher_csr_agent_m0_readdata;                                                // msgdma_rx_prefetcher_csr_translator:uav_readdata -> msgdma_rx_prefetcher_csr_agent:m0_readdata
+	wire          msgdma_rx_prefetcher_csr_agent_m0_waitrequest;                                             // msgdma_rx_prefetcher_csr_translator:uav_waitrequest -> msgdma_rx_prefetcher_csr_agent:m0_waitrequest
+	wire          msgdma_rx_prefetcher_csr_agent_m0_debugaccess;                                             // msgdma_rx_prefetcher_csr_agent:m0_debugaccess -> msgdma_rx_prefetcher_csr_translator:uav_debugaccess
+	wire   [28:0] msgdma_rx_prefetcher_csr_agent_m0_address;                                                 // msgdma_rx_prefetcher_csr_agent:m0_address -> msgdma_rx_prefetcher_csr_translator:uav_address
+	wire    [3:0] msgdma_rx_prefetcher_csr_agent_m0_byteenable;                                              // msgdma_rx_prefetcher_csr_agent:m0_byteenable -> msgdma_rx_prefetcher_csr_translator:uav_byteenable
+	wire          msgdma_rx_prefetcher_csr_agent_m0_read;                                                    // msgdma_rx_prefetcher_csr_agent:m0_read -> msgdma_rx_prefetcher_csr_translator:uav_read
+	wire          msgdma_rx_prefetcher_csr_agent_m0_readdatavalid;                                           // msgdma_rx_prefetcher_csr_translator:uav_readdatavalid -> msgdma_rx_prefetcher_csr_agent:m0_readdatavalid
+	wire          msgdma_rx_prefetcher_csr_agent_m0_lock;                                                    // msgdma_rx_prefetcher_csr_agent:m0_lock -> msgdma_rx_prefetcher_csr_translator:uav_lock
+	wire   [31:0] msgdma_rx_prefetcher_csr_agent_m0_writedata;                                               // msgdma_rx_prefetcher_csr_agent:m0_writedata -> msgdma_rx_prefetcher_csr_translator:uav_writedata
+	wire          msgdma_rx_prefetcher_csr_agent_m0_write;                                                   // msgdma_rx_prefetcher_csr_agent:m0_write -> msgdma_rx_prefetcher_csr_translator:uav_write
+	wire    [2:0] msgdma_rx_prefetcher_csr_agent_m0_burstcount;                                              // msgdma_rx_prefetcher_csr_agent:m0_burstcount -> msgdma_rx_prefetcher_csr_translator:uav_burstcount
+	wire          msgdma_rx_prefetcher_csr_agent_rf_source_valid;                                            // msgdma_rx_prefetcher_csr_agent:rf_source_valid -> msgdma_rx_prefetcher_csr_agent_rsp_fifo:in_valid
+	wire  [121:0] msgdma_rx_prefetcher_csr_agent_rf_source_data;                                             // msgdma_rx_prefetcher_csr_agent:rf_source_data -> msgdma_rx_prefetcher_csr_agent_rsp_fifo:in_data
+	wire          msgdma_rx_prefetcher_csr_agent_rf_source_ready;                                            // msgdma_rx_prefetcher_csr_agent_rsp_fifo:in_ready -> msgdma_rx_prefetcher_csr_agent:rf_source_ready
+	wire          msgdma_rx_prefetcher_csr_agent_rf_source_startofpacket;                                    // msgdma_rx_prefetcher_csr_agent:rf_source_startofpacket -> msgdma_rx_prefetcher_csr_agent_rsp_fifo:in_startofpacket
+	wire          msgdma_rx_prefetcher_csr_agent_rf_source_endofpacket;                                      // msgdma_rx_prefetcher_csr_agent:rf_source_endofpacket -> msgdma_rx_prefetcher_csr_agent_rsp_fifo:in_endofpacket
+	wire          msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_valid;                                         // msgdma_rx_prefetcher_csr_agent_rsp_fifo:out_valid -> msgdma_rx_prefetcher_csr_agent:rf_sink_valid
+	wire  [121:0] msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_data;                                          // msgdma_rx_prefetcher_csr_agent_rsp_fifo:out_data -> msgdma_rx_prefetcher_csr_agent:rf_sink_data
+	wire          msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_ready;                                         // msgdma_rx_prefetcher_csr_agent:rf_sink_ready -> msgdma_rx_prefetcher_csr_agent_rsp_fifo:out_ready
+	wire          msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_startofpacket;                                 // msgdma_rx_prefetcher_csr_agent_rsp_fifo:out_startofpacket -> msgdma_rx_prefetcher_csr_agent:rf_sink_startofpacket
+	wire          msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_endofpacket;                                   // msgdma_rx_prefetcher_csr_agent_rsp_fifo:out_endofpacket -> msgdma_rx_prefetcher_csr_agent:rf_sink_endofpacket
+	wire          cmd_mux_013_src_valid;                                                                     // cmd_mux_013:src_valid -> msgdma_rx_prefetcher_csr_agent:cp_valid
+	wire  [120:0] cmd_mux_013_src_data;                                                                      // cmd_mux_013:src_data -> msgdma_rx_prefetcher_csr_agent:cp_data
+	wire          cmd_mux_013_src_ready;                                                                     // msgdma_rx_prefetcher_csr_agent:cp_ready -> cmd_mux_013:src_ready
+	wire   [20:0] cmd_mux_013_src_channel;                                                                   // cmd_mux_013:src_channel -> msgdma_rx_prefetcher_csr_agent:cp_channel
+	wire          cmd_mux_013_src_startofpacket;                                                             // cmd_mux_013:src_startofpacket -> msgdma_rx_prefetcher_csr_agent:cp_startofpacket
+	wire          cmd_mux_013_src_endofpacket;                                                               // cmd_mux_013:src_endofpacket -> msgdma_rx_prefetcher_csr_agent:cp_endofpacket
+	wire   [31:0] descriptor_memory_s1_agent_m0_readdata;                                                    // descriptor_memory_s1_translator:uav_readdata -> descriptor_memory_s1_agent:m0_readdata
+	wire          descriptor_memory_s1_agent_m0_waitrequest;                                                 // descriptor_memory_s1_translator:uav_waitrequest -> descriptor_memory_s1_agent:m0_waitrequest
+	wire          descriptor_memory_s1_agent_m0_debugaccess;                                                 // descriptor_memory_s1_agent:m0_debugaccess -> descriptor_memory_s1_translator:uav_debugaccess
+	wire   [28:0] descriptor_memory_s1_agent_m0_address;                                                     // descriptor_memory_s1_agent:m0_address -> descriptor_memory_s1_translator:uav_address
+	wire    [3:0] descriptor_memory_s1_agent_m0_byteenable;                                                  // descriptor_memory_s1_agent:m0_byteenable -> descriptor_memory_s1_translator:uav_byteenable
+	wire          descriptor_memory_s1_agent_m0_read;                                                        // descriptor_memory_s1_agent:m0_read -> descriptor_memory_s1_translator:uav_read
+	wire          descriptor_memory_s1_agent_m0_readdatavalid;                                               // descriptor_memory_s1_translator:uav_readdatavalid -> descriptor_memory_s1_agent:m0_readdatavalid
+	wire          descriptor_memory_s1_agent_m0_lock;                                                        // descriptor_memory_s1_agent:m0_lock -> descriptor_memory_s1_translator:uav_lock
+	wire   [31:0] descriptor_memory_s1_agent_m0_writedata;                                                   // descriptor_memory_s1_agent:m0_writedata -> descriptor_memory_s1_translator:uav_writedata
+	wire          descriptor_memory_s1_agent_m0_write;                                                       // descriptor_memory_s1_agent:m0_write -> descriptor_memory_s1_translator:uav_write
+	wire    [2:0] descriptor_memory_s1_agent_m0_burstcount;                                                  // descriptor_memory_s1_agent:m0_burstcount -> descriptor_memory_s1_translator:uav_burstcount
+	wire          descriptor_memory_s1_agent_rf_source_valid;                                                // descriptor_memory_s1_agent:rf_source_valid -> descriptor_memory_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] descriptor_memory_s1_agent_rf_source_data;                                                 // descriptor_memory_s1_agent:rf_source_data -> descriptor_memory_s1_agent_rsp_fifo:in_data
+	wire          descriptor_memory_s1_agent_rf_source_ready;                                                // descriptor_memory_s1_agent_rsp_fifo:in_ready -> descriptor_memory_s1_agent:rf_source_ready
+	wire          descriptor_memory_s1_agent_rf_source_startofpacket;                                        // descriptor_memory_s1_agent:rf_source_startofpacket -> descriptor_memory_s1_agent_rsp_fifo:in_startofpacket
+	wire          descriptor_memory_s1_agent_rf_source_endofpacket;                                          // descriptor_memory_s1_agent:rf_source_endofpacket -> descriptor_memory_s1_agent_rsp_fifo:in_endofpacket
+	wire          descriptor_memory_s1_agent_rsp_fifo_out_valid;                                             // descriptor_memory_s1_agent_rsp_fifo:out_valid -> descriptor_memory_s1_agent:rf_sink_valid
+	wire  [121:0] descriptor_memory_s1_agent_rsp_fifo_out_data;                                              // descriptor_memory_s1_agent_rsp_fifo:out_data -> descriptor_memory_s1_agent:rf_sink_data
+	wire          descriptor_memory_s1_agent_rsp_fifo_out_ready;                                             // descriptor_memory_s1_agent:rf_sink_ready -> descriptor_memory_s1_agent_rsp_fifo:out_ready
+	wire          descriptor_memory_s1_agent_rsp_fifo_out_startofpacket;                                     // descriptor_memory_s1_agent_rsp_fifo:out_startofpacket -> descriptor_memory_s1_agent:rf_sink_startofpacket
+	wire          descriptor_memory_s1_agent_rsp_fifo_out_endofpacket;                                       // descriptor_memory_s1_agent_rsp_fifo:out_endofpacket -> descriptor_memory_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_014_src_valid;                                                                     // cmd_mux_014:src_valid -> descriptor_memory_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_014_src_data;                                                                      // cmd_mux_014:src_data -> descriptor_memory_s1_agent:cp_data
+	wire          cmd_mux_014_src_ready;                                                                     // descriptor_memory_s1_agent:cp_ready -> cmd_mux_014:src_ready
+	wire   [20:0] cmd_mux_014_src_channel;                                                                   // cmd_mux_014:src_channel -> descriptor_memory_s1_agent:cp_channel
+	wire          cmd_mux_014_src_startofpacket;                                                             // cmd_mux_014:src_startofpacket -> descriptor_memory_s1_agent:cp_startofpacket
+	wire          cmd_mux_014_src_endofpacket;                                                               // cmd_mux_014:src_endofpacket -> descriptor_memory_s1_agent:cp_endofpacket
+	wire   [31:0] sys_clk_timer_s1_agent_m0_readdata;                                                        // sys_clk_timer_s1_translator:uav_readdata -> sys_clk_timer_s1_agent:m0_readdata
+	wire          sys_clk_timer_s1_agent_m0_waitrequest;                                                     // sys_clk_timer_s1_translator:uav_waitrequest -> sys_clk_timer_s1_agent:m0_waitrequest
+	wire          sys_clk_timer_s1_agent_m0_debugaccess;                                                     // sys_clk_timer_s1_agent:m0_debugaccess -> sys_clk_timer_s1_translator:uav_debugaccess
+	wire   [28:0] sys_clk_timer_s1_agent_m0_address;                                                         // sys_clk_timer_s1_agent:m0_address -> sys_clk_timer_s1_translator:uav_address
+	wire    [3:0] sys_clk_timer_s1_agent_m0_byteenable;                                                      // sys_clk_timer_s1_agent:m0_byteenable -> sys_clk_timer_s1_translator:uav_byteenable
+	wire          sys_clk_timer_s1_agent_m0_read;                                                            // sys_clk_timer_s1_agent:m0_read -> sys_clk_timer_s1_translator:uav_read
+	wire          sys_clk_timer_s1_agent_m0_readdatavalid;                                                   // sys_clk_timer_s1_translator:uav_readdatavalid -> sys_clk_timer_s1_agent:m0_readdatavalid
+	wire          sys_clk_timer_s1_agent_m0_lock;                                                            // sys_clk_timer_s1_agent:m0_lock -> sys_clk_timer_s1_translator:uav_lock
+	wire   [31:0] sys_clk_timer_s1_agent_m0_writedata;                                                       // sys_clk_timer_s1_agent:m0_writedata -> sys_clk_timer_s1_translator:uav_writedata
+	wire          sys_clk_timer_s1_agent_m0_write;                                                           // sys_clk_timer_s1_agent:m0_write -> sys_clk_timer_s1_translator:uav_write
+	wire    [2:0] sys_clk_timer_s1_agent_m0_burstcount;                                                      // sys_clk_timer_s1_agent:m0_burstcount -> sys_clk_timer_s1_translator:uav_burstcount
+	wire          sys_clk_timer_s1_agent_rf_source_valid;                                                    // sys_clk_timer_s1_agent:rf_source_valid -> sys_clk_timer_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] sys_clk_timer_s1_agent_rf_source_data;                                                     // sys_clk_timer_s1_agent:rf_source_data -> sys_clk_timer_s1_agent_rsp_fifo:in_data
+	wire          sys_clk_timer_s1_agent_rf_source_ready;                                                    // sys_clk_timer_s1_agent_rsp_fifo:in_ready -> sys_clk_timer_s1_agent:rf_source_ready
+	wire          sys_clk_timer_s1_agent_rf_source_startofpacket;                                            // sys_clk_timer_s1_agent:rf_source_startofpacket -> sys_clk_timer_s1_agent_rsp_fifo:in_startofpacket
+	wire          sys_clk_timer_s1_agent_rf_source_endofpacket;                                              // sys_clk_timer_s1_agent:rf_source_endofpacket -> sys_clk_timer_s1_agent_rsp_fifo:in_endofpacket
+	wire          sys_clk_timer_s1_agent_rsp_fifo_out_valid;                                                 // sys_clk_timer_s1_agent_rsp_fifo:out_valid -> sys_clk_timer_s1_agent:rf_sink_valid
+	wire  [121:0] sys_clk_timer_s1_agent_rsp_fifo_out_data;                                                  // sys_clk_timer_s1_agent_rsp_fifo:out_data -> sys_clk_timer_s1_agent:rf_sink_data
+	wire          sys_clk_timer_s1_agent_rsp_fifo_out_ready;                                                 // sys_clk_timer_s1_agent:rf_sink_ready -> sys_clk_timer_s1_agent_rsp_fifo:out_ready
+	wire          sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket;                                         // sys_clk_timer_s1_agent_rsp_fifo:out_startofpacket -> sys_clk_timer_s1_agent:rf_sink_startofpacket
+	wire          sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket;                                           // sys_clk_timer_s1_agent_rsp_fifo:out_endofpacket -> sys_clk_timer_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_015_src_valid;                                                                     // cmd_mux_015:src_valid -> sys_clk_timer_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_015_src_data;                                                                      // cmd_mux_015:src_data -> sys_clk_timer_s1_agent:cp_data
+	wire          cmd_mux_015_src_ready;                                                                     // sys_clk_timer_s1_agent:cp_ready -> cmd_mux_015:src_ready
+	wire   [20:0] cmd_mux_015_src_channel;                                                                   // cmd_mux_015:src_channel -> sys_clk_timer_s1_agent:cp_channel
+	wire          cmd_mux_015_src_startofpacket;                                                             // cmd_mux_015:src_startofpacket -> sys_clk_timer_s1_agent:cp_startofpacket
+	wire          cmd_mux_015_src_endofpacket;                                                               // cmd_mux_015:src_endofpacket -> sys_clk_timer_s1_agent:cp_endofpacket
+	wire   [31:0] output_pio_s1_agent_m0_readdata;                                                           // output_pio_s1_translator:uav_readdata -> output_pio_s1_agent:m0_readdata
+	wire          output_pio_s1_agent_m0_waitrequest;                                                        // output_pio_s1_translator:uav_waitrequest -> output_pio_s1_agent:m0_waitrequest
+	wire          output_pio_s1_agent_m0_debugaccess;                                                        // output_pio_s1_agent:m0_debugaccess -> output_pio_s1_translator:uav_debugaccess
+	wire   [28:0] output_pio_s1_agent_m0_address;                                                            // output_pio_s1_agent:m0_address -> output_pio_s1_translator:uav_address
+	wire    [3:0] output_pio_s1_agent_m0_byteenable;                                                         // output_pio_s1_agent:m0_byteenable -> output_pio_s1_translator:uav_byteenable
+	wire          output_pio_s1_agent_m0_read;                                                               // output_pio_s1_agent:m0_read -> output_pio_s1_translator:uav_read
+	wire          output_pio_s1_agent_m0_readdatavalid;                                                      // output_pio_s1_translator:uav_readdatavalid -> output_pio_s1_agent:m0_readdatavalid
+	wire          output_pio_s1_agent_m0_lock;                                                               // output_pio_s1_agent:m0_lock -> output_pio_s1_translator:uav_lock
+	wire   [31:0] output_pio_s1_agent_m0_writedata;                                                          // output_pio_s1_agent:m0_writedata -> output_pio_s1_translator:uav_writedata
+	wire          output_pio_s1_agent_m0_write;                                                              // output_pio_s1_agent:m0_write -> output_pio_s1_translator:uav_write
+	wire    [2:0] output_pio_s1_agent_m0_burstcount;                                                         // output_pio_s1_agent:m0_burstcount -> output_pio_s1_translator:uav_burstcount
+	wire          output_pio_s1_agent_rf_source_valid;                                                       // output_pio_s1_agent:rf_source_valid -> output_pio_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] output_pio_s1_agent_rf_source_data;                                                        // output_pio_s1_agent:rf_source_data -> output_pio_s1_agent_rsp_fifo:in_data
+	wire          output_pio_s1_agent_rf_source_ready;                                                       // output_pio_s1_agent_rsp_fifo:in_ready -> output_pio_s1_agent:rf_source_ready
+	wire          output_pio_s1_agent_rf_source_startofpacket;                                               // output_pio_s1_agent:rf_source_startofpacket -> output_pio_s1_agent_rsp_fifo:in_startofpacket
+	wire          output_pio_s1_agent_rf_source_endofpacket;                                                 // output_pio_s1_agent:rf_source_endofpacket -> output_pio_s1_agent_rsp_fifo:in_endofpacket
+	wire          output_pio_s1_agent_rsp_fifo_out_valid;                                                    // output_pio_s1_agent_rsp_fifo:out_valid -> output_pio_s1_agent:rf_sink_valid
+	wire  [121:0] output_pio_s1_agent_rsp_fifo_out_data;                                                     // output_pio_s1_agent_rsp_fifo:out_data -> output_pio_s1_agent:rf_sink_data
+	wire          output_pio_s1_agent_rsp_fifo_out_ready;                                                    // output_pio_s1_agent:rf_sink_ready -> output_pio_s1_agent_rsp_fifo:out_ready
+	wire          output_pio_s1_agent_rsp_fifo_out_startofpacket;                                            // output_pio_s1_agent_rsp_fifo:out_startofpacket -> output_pio_s1_agent:rf_sink_startofpacket
+	wire          output_pio_s1_agent_rsp_fifo_out_endofpacket;                                              // output_pio_s1_agent_rsp_fifo:out_endofpacket -> output_pio_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_016_src_valid;                                                                     // cmd_mux_016:src_valid -> output_pio_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_016_src_data;                                                                      // cmd_mux_016:src_data -> output_pio_s1_agent:cp_data
+	wire          cmd_mux_016_src_ready;                                                                     // output_pio_s1_agent:cp_ready -> cmd_mux_016:src_ready
+	wire   [20:0] cmd_mux_016_src_channel;                                                                   // cmd_mux_016:src_channel -> output_pio_s1_agent:cp_channel
+	wire          cmd_mux_016_src_startofpacket;                                                             // cmd_mux_016:src_startofpacket -> output_pio_s1_agent:cp_startofpacket
+	wire          cmd_mux_016_src_endofpacket;                                                               // cmd_mux_016:src_endofpacket -> output_pio_s1_agent:cp_endofpacket
+	wire   [31:0] button_pio_s1_agent_m0_readdata;                                                           // button_pio_s1_translator:uav_readdata -> button_pio_s1_agent:m0_readdata
+	wire          button_pio_s1_agent_m0_waitrequest;                                                        // button_pio_s1_translator:uav_waitrequest -> button_pio_s1_agent:m0_waitrequest
+	wire          button_pio_s1_agent_m0_debugaccess;                                                        // button_pio_s1_agent:m0_debugaccess -> button_pio_s1_translator:uav_debugaccess
+	wire   [28:0] button_pio_s1_agent_m0_address;                                                            // button_pio_s1_agent:m0_address -> button_pio_s1_translator:uav_address
+	wire    [3:0] button_pio_s1_agent_m0_byteenable;                                                         // button_pio_s1_agent:m0_byteenable -> button_pio_s1_translator:uav_byteenable
+	wire          button_pio_s1_agent_m0_read;                                                               // button_pio_s1_agent:m0_read -> button_pio_s1_translator:uav_read
+	wire          button_pio_s1_agent_m0_readdatavalid;                                                      // button_pio_s1_translator:uav_readdatavalid -> button_pio_s1_agent:m0_readdatavalid
+	wire          button_pio_s1_agent_m0_lock;                                                               // button_pio_s1_agent:m0_lock -> button_pio_s1_translator:uav_lock
+	wire   [31:0] button_pio_s1_agent_m0_writedata;                                                          // button_pio_s1_agent:m0_writedata -> button_pio_s1_translator:uav_writedata
+	wire          button_pio_s1_agent_m0_write;                                                              // button_pio_s1_agent:m0_write -> button_pio_s1_translator:uav_write
+	wire    [2:0] button_pio_s1_agent_m0_burstcount;                                                         // button_pio_s1_agent:m0_burstcount -> button_pio_s1_translator:uav_burstcount
+	wire          button_pio_s1_agent_rf_source_valid;                                                       // button_pio_s1_agent:rf_source_valid -> button_pio_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] button_pio_s1_agent_rf_source_data;                                                        // button_pio_s1_agent:rf_source_data -> button_pio_s1_agent_rsp_fifo:in_data
+	wire          button_pio_s1_agent_rf_source_ready;                                                       // button_pio_s1_agent_rsp_fifo:in_ready -> button_pio_s1_agent:rf_source_ready
+	wire          button_pio_s1_agent_rf_source_startofpacket;                                               // button_pio_s1_agent:rf_source_startofpacket -> button_pio_s1_agent_rsp_fifo:in_startofpacket
+	wire          button_pio_s1_agent_rf_source_endofpacket;                                                 // button_pio_s1_agent:rf_source_endofpacket -> button_pio_s1_agent_rsp_fifo:in_endofpacket
+	wire          button_pio_s1_agent_rsp_fifo_out_valid;                                                    // button_pio_s1_agent_rsp_fifo:out_valid -> button_pio_s1_agent:rf_sink_valid
+	wire  [121:0] button_pio_s1_agent_rsp_fifo_out_data;                                                     // button_pio_s1_agent_rsp_fifo:out_data -> button_pio_s1_agent:rf_sink_data
+	wire          button_pio_s1_agent_rsp_fifo_out_ready;                                                    // button_pio_s1_agent:rf_sink_ready -> button_pio_s1_agent_rsp_fifo:out_ready
+	wire          button_pio_s1_agent_rsp_fifo_out_startofpacket;                                            // button_pio_s1_agent_rsp_fifo:out_startofpacket -> button_pio_s1_agent:rf_sink_startofpacket
+	wire          button_pio_s1_agent_rsp_fifo_out_endofpacket;                                              // button_pio_s1_agent_rsp_fifo:out_endofpacket -> button_pio_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_017_src_valid;                                                                     // cmd_mux_017:src_valid -> button_pio_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_017_src_data;                                                                      // cmd_mux_017:src_data -> button_pio_s1_agent:cp_data
+	wire          cmd_mux_017_src_ready;                                                                     // button_pio_s1_agent:cp_ready -> cmd_mux_017:src_ready
+	wire   [20:0] cmd_mux_017_src_channel;                                                                   // cmd_mux_017:src_channel -> button_pio_s1_agent:cp_channel
+	wire          cmd_mux_017_src_startofpacket;                                                             // cmd_mux_017:src_startofpacket -> button_pio_s1_agent:cp_startofpacket
+	wire          cmd_mux_017_src_endofpacket;                                                               // cmd_mux_017:src_endofpacket -> button_pio_s1_agent:cp_endofpacket
+	wire   [31:0] debug_uart_s1_agent_m0_readdata;                                                           // debug_uart_s1_translator:uav_readdata -> debug_uart_s1_agent:m0_readdata
+	wire          debug_uart_s1_agent_m0_waitrequest;                                                        // debug_uart_s1_translator:uav_waitrequest -> debug_uart_s1_agent:m0_waitrequest
+	wire          debug_uart_s1_agent_m0_debugaccess;                                                        // debug_uart_s1_agent:m0_debugaccess -> debug_uart_s1_translator:uav_debugaccess
+	wire   [28:0] debug_uart_s1_agent_m0_address;                                                            // debug_uart_s1_agent:m0_address -> debug_uart_s1_translator:uav_address
+	wire    [3:0] debug_uart_s1_agent_m0_byteenable;                                                         // debug_uart_s1_agent:m0_byteenable -> debug_uart_s1_translator:uav_byteenable
+	wire          debug_uart_s1_agent_m0_read;                                                               // debug_uart_s1_agent:m0_read -> debug_uart_s1_translator:uav_read
+	wire          debug_uart_s1_agent_m0_readdatavalid;                                                      // debug_uart_s1_translator:uav_readdatavalid -> debug_uart_s1_agent:m0_readdatavalid
+	wire          debug_uart_s1_agent_m0_lock;                                                               // debug_uart_s1_agent:m0_lock -> debug_uart_s1_translator:uav_lock
+	wire   [31:0] debug_uart_s1_agent_m0_writedata;                                                          // debug_uart_s1_agent:m0_writedata -> debug_uart_s1_translator:uav_writedata
+	wire          debug_uart_s1_agent_m0_write;                                                              // debug_uart_s1_agent:m0_write -> debug_uart_s1_translator:uav_write
+	wire    [2:0] debug_uart_s1_agent_m0_burstcount;                                                         // debug_uart_s1_agent:m0_burstcount -> debug_uart_s1_translator:uav_burstcount
+	wire          debug_uart_s1_agent_rf_source_valid;                                                       // debug_uart_s1_agent:rf_source_valid -> debug_uart_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] debug_uart_s1_agent_rf_source_data;                                                        // debug_uart_s1_agent:rf_source_data -> debug_uart_s1_agent_rsp_fifo:in_data
+	wire          debug_uart_s1_agent_rf_source_ready;                                                       // debug_uart_s1_agent_rsp_fifo:in_ready -> debug_uart_s1_agent:rf_source_ready
+	wire          debug_uart_s1_agent_rf_source_startofpacket;                                               // debug_uart_s1_agent:rf_source_startofpacket -> debug_uart_s1_agent_rsp_fifo:in_startofpacket
+	wire          debug_uart_s1_agent_rf_source_endofpacket;                                                 // debug_uart_s1_agent:rf_source_endofpacket -> debug_uart_s1_agent_rsp_fifo:in_endofpacket
+	wire          debug_uart_s1_agent_rsp_fifo_out_valid;                                                    // debug_uart_s1_agent_rsp_fifo:out_valid -> debug_uart_s1_agent:rf_sink_valid
+	wire  [121:0] debug_uart_s1_agent_rsp_fifo_out_data;                                                     // debug_uart_s1_agent_rsp_fifo:out_data -> debug_uart_s1_agent:rf_sink_data
+	wire          debug_uart_s1_agent_rsp_fifo_out_ready;                                                    // debug_uart_s1_agent:rf_sink_ready -> debug_uart_s1_agent_rsp_fifo:out_ready
+	wire          debug_uart_s1_agent_rsp_fifo_out_startofpacket;                                            // debug_uart_s1_agent_rsp_fifo:out_startofpacket -> debug_uart_s1_agent:rf_sink_startofpacket
+	wire          debug_uart_s1_agent_rsp_fifo_out_endofpacket;                                              // debug_uart_s1_agent_rsp_fifo:out_endofpacket -> debug_uart_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_018_src_valid;                                                                     // cmd_mux_018:src_valid -> debug_uart_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_018_src_data;                                                                      // cmd_mux_018:src_data -> debug_uart_s1_agent:cp_data
+	wire          cmd_mux_018_src_ready;                                                                     // debug_uart_s1_agent:cp_ready -> cmd_mux_018:src_ready
+	wire   [20:0] cmd_mux_018_src_channel;                                                                   // cmd_mux_018:src_channel -> debug_uart_s1_agent:cp_channel
+	wire          cmd_mux_018_src_startofpacket;                                                             // cmd_mux_018:src_startofpacket -> debug_uart_s1_agent:cp_startofpacket
+	wire          cmd_mux_018_src_endofpacket;                                                               // cmd_mux_018:src_endofpacket -> debug_uart_s1_agent:cp_endofpacket
+	wire   [31:0] frame_timer_s1_agent_m0_readdata;                                                          // frame_timer_s1_translator:uav_readdata -> frame_timer_s1_agent:m0_readdata
+	wire          frame_timer_s1_agent_m0_waitrequest;                                                       // frame_timer_s1_translator:uav_waitrequest -> frame_timer_s1_agent:m0_waitrequest
+	wire          frame_timer_s1_agent_m0_debugaccess;                                                       // frame_timer_s1_agent:m0_debugaccess -> frame_timer_s1_translator:uav_debugaccess
+	wire   [28:0] frame_timer_s1_agent_m0_address;                                                           // frame_timer_s1_agent:m0_address -> frame_timer_s1_translator:uav_address
+	wire    [3:0] frame_timer_s1_agent_m0_byteenable;                                                        // frame_timer_s1_agent:m0_byteenable -> frame_timer_s1_translator:uav_byteenable
+	wire          frame_timer_s1_agent_m0_read;                                                              // frame_timer_s1_agent:m0_read -> frame_timer_s1_translator:uav_read
+	wire          frame_timer_s1_agent_m0_readdatavalid;                                                     // frame_timer_s1_translator:uav_readdatavalid -> frame_timer_s1_agent:m0_readdatavalid
+	wire          frame_timer_s1_agent_m0_lock;                                                              // frame_timer_s1_agent:m0_lock -> frame_timer_s1_translator:uav_lock
+	wire   [31:0] frame_timer_s1_agent_m0_writedata;                                                         // frame_timer_s1_agent:m0_writedata -> frame_timer_s1_translator:uav_writedata
+	wire          frame_timer_s1_agent_m0_write;                                                             // frame_timer_s1_agent:m0_write -> frame_timer_s1_translator:uav_write
+	wire    [2:0] frame_timer_s1_agent_m0_burstcount;                                                        // frame_timer_s1_agent:m0_burstcount -> frame_timer_s1_translator:uav_burstcount
+	wire          frame_timer_s1_agent_rf_source_valid;                                                      // frame_timer_s1_agent:rf_source_valid -> frame_timer_s1_agent_rsp_fifo:in_valid
+	wire  [121:0] frame_timer_s1_agent_rf_source_data;                                                       // frame_timer_s1_agent:rf_source_data -> frame_timer_s1_agent_rsp_fifo:in_data
+	wire          frame_timer_s1_agent_rf_source_ready;                                                      // frame_timer_s1_agent_rsp_fifo:in_ready -> frame_timer_s1_agent:rf_source_ready
+	wire          frame_timer_s1_agent_rf_source_startofpacket;                                              // frame_timer_s1_agent:rf_source_startofpacket -> frame_timer_s1_agent_rsp_fifo:in_startofpacket
+	wire          frame_timer_s1_agent_rf_source_endofpacket;                                                // frame_timer_s1_agent:rf_source_endofpacket -> frame_timer_s1_agent_rsp_fifo:in_endofpacket
+	wire          frame_timer_s1_agent_rsp_fifo_out_valid;                                                   // frame_timer_s1_agent_rsp_fifo:out_valid -> frame_timer_s1_agent:rf_sink_valid
+	wire  [121:0] frame_timer_s1_agent_rsp_fifo_out_data;                                                    // frame_timer_s1_agent_rsp_fifo:out_data -> frame_timer_s1_agent:rf_sink_data
+	wire          frame_timer_s1_agent_rsp_fifo_out_ready;                                                   // frame_timer_s1_agent:rf_sink_ready -> frame_timer_s1_agent_rsp_fifo:out_ready
+	wire          frame_timer_s1_agent_rsp_fifo_out_startofpacket;                                           // frame_timer_s1_agent_rsp_fifo:out_startofpacket -> frame_timer_s1_agent:rf_sink_startofpacket
+	wire          frame_timer_s1_agent_rsp_fifo_out_endofpacket;                                             // frame_timer_s1_agent_rsp_fifo:out_endofpacket -> frame_timer_s1_agent:rf_sink_endofpacket
+	wire          cmd_mux_019_src_valid;                                                                     // cmd_mux_019:src_valid -> frame_timer_s1_agent:cp_valid
+	wire  [120:0] cmd_mux_019_src_data;                                                                      // cmd_mux_019:src_data -> frame_timer_s1_agent:cp_data
+	wire          cmd_mux_019_src_ready;                                                                     // frame_timer_s1_agent:cp_ready -> cmd_mux_019:src_ready
+	wire   [20:0] cmd_mux_019_src_channel;                                                                   // cmd_mux_019:src_channel -> frame_timer_s1_agent:cp_channel
+	wire          cmd_mux_019_src_startofpacket;                                                             // cmd_mux_019:src_startofpacket -> frame_timer_s1_agent:cp_startofpacket
+	wire          cmd_mux_019_src_endofpacket;                                                               // cmd_mux_019:src_endofpacket -> frame_timer_s1_agent:cp_endofpacket
+	wire   [15:0] calibration_ram_s1_agent_m0_readdata;                                                      // calibration_ram_s1_translator:uav_readdata -> calibration_ram_s1_agent:m0_readdata
+	wire          calibration_ram_s1_agent_m0_waitrequest;                                                   // calibration_ram_s1_translator:uav_waitrequest -> calibration_ram_s1_agent:m0_waitrequest
+	wire          calibration_ram_s1_agent_m0_debugaccess;                                                   // calibration_ram_s1_agent:m0_debugaccess -> calibration_ram_s1_translator:uav_debugaccess
+	wire   [28:0] calibration_ram_s1_agent_m0_address;                                                       // calibration_ram_s1_agent:m0_address -> calibration_ram_s1_translator:uav_address
+	wire    [1:0] calibration_ram_s1_agent_m0_byteenable;                                                    // calibration_ram_s1_agent:m0_byteenable -> calibration_ram_s1_translator:uav_byteenable
+	wire          calibration_ram_s1_agent_m0_read;                                                          // calibration_ram_s1_agent:m0_read -> calibration_ram_s1_translator:uav_read
+	wire          calibration_ram_s1_agent_m0_readdatavalid;                                                 // calibration_ram_s1_translator:uav_readdatavalid -> calibration_ram_s1_agent:m0_readdatavalid
+	wire          calibration_ram_s1_agent_m0_lock;                                                          // calibration_ram_s1_agent:m0_lock -> calibration_ram_s1_translator:uav_lock
+	wire   [15:0] calibration_ram_s1_agent_m0_writedata;                                                     // calibration_ram_s1_agent:m0_writedata -> calibration_ram_s1_translator:uav_writedata
+	wire          calibration_ram_s1_agent_m0_write;                                                         // calibration_ram_s1_agent:m0_write -> calibration_ram_s1_translator:uav_write
+	wire    [1:0] calibration_ram_s1_agent_m0_burstcount;                                                    // calibration_ram_s1_agent:m0_burstcount -> calibration_ram_s1_translator:uav_burstcount
+	wire          calibration_ram_s1_agent_rf_source_valid;                                                  // calibration_ram_s1_agent:rf_source_valid -> calibration_ram_s1_agent_rsp_fifo:in_valid
+	wire  [103:0] calibration_ram_s1_agent_rf_source_data;                                                   // calibration_ram_s1_agent:rf_source_data -> calibration_ram_s1_agent_rsp_fifo:in_data
+	wire          calibration_ram_s1_agent_rf_source_ready;                                                  // calibration_ram_s1_agent_rsp_fifo:in_ready -> calibration_ram_s1_agent:rf_source_ready
+	wire          calibration_ram_s1_agent_rf_source_startofpacket;                                          // calibration_ram_s1_agent:rf_source_startofpacket -> calibration_ram_s1_agent_rsp_fifo:in_startofpacket
+	wire          calibration_ram_s1_agent_rf_source_endofpacket;                                            // calibration_ram_s1_agent:rf_source_endofpacket -> calibration_ram_s1_agent_rsp_fifo:in_endofpacket
+	wire          calibration_ram_s1_agent_rsp_fifo_out_valid;                                               // calibration_ram_s1_agent_rsp_fifo:out_valid -> calibration_ram_s1_agent:rf_sink_valid
+	wire  [103:0] calibration_ram_s1_agent_rsp_fifo_out_data;                                                // calibration_ram_s1_agent_rsp_fifo:out_data -> calibration_ram_s1_agent:rf_sink_data
+	wire          calibration_ram_s1_agent_rsp_fifo_out_ready;                                               // calibration_ram_s1_agent:rf_sink_ready -> calibration_ram_s1_agent_rsp_fifo:out_ready
+	wire          calibration_ram_s1_agent_rsp_fifo_out_startofpacket;                                       // calibration_ram_s1_agent_rsp_fifo:out_startofpacket -> calibration_ram_s1_agent:rf_sink_startofpacket
+	wire          calibration_ram_s1_agent_rsp_fifo_out_endofpacket;                                         // calibration_ram_s1_agent_rsp_fifo:out_endofpacket -> calibration_ram_s1_agent:rf_sink_endofpacket
+	wire          cpu_data_master_agent_cp_valid;                                                            // cpu_data_master_agent:cp_valid -> router:sink_valid
+	wire  [120:0] cpu_data_master_agent_cp_data;                                                             // cpu_data_master_agent:cp_data -> router:sink_data
+	wire          cpu_data_master_agent_cp_ready;                                                            // router:sink_ready -> cpu_data_master_agent:cp_ready
+	wire          cpu_data_master_agent_cp_startofpacket;                                                    // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
+	wire          cpu_data_master_agent_cp_endofpacket;                                                      // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
+	wire          cpu_instruction_master_agent_cp_valid;                                                     // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
+	wire  [120:0] cpu_instruction_master_agent_cp_data;                                                      // cpu_instruction_master_agent:cp_data -> router_001:sink_data
+	wire          cpu_instruction_master_agent_cp_ready;                                                     // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
+	wire          cpu_instruction_master_agent_cp_startofpacket;                                             // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
+	wire          cpu_instruction_master_agent_cp_endofpacket;                                               // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
+	wire          msgdma_tx_mm_read_agent_cp_valid;                                                          // msgdma_tx_mm_read_agent:cp_valid -> router_002:sink_valid
+	wire  [120:0] msgdma_tx_mm_read_agent_cp_data;                                                           // msgdma_tx_mm_read_agent:cp_data -> router_002:sink_data
+	wire          msgdma_tx_mm_read_agent_cp_ready;                                                          // router_002:sink_ready -> msgdma_tx_mm_read_agent:cp_ready
+	wire          msgdma_tx_mm_read_agent_cp_startofpacket;                                                  // msgdma_tx_mm_read_agent:cp_startofpacket -> router_002:sink_startofpacket
+	wire          msgdma_tx_mm_read_agent_cp_endofpacket;                                                    // msgdma_tx_mm_read_agent:cp_endofpacket -> router_002:sink_endofpacket
+	wire          router_002_src_valid;                                                                      // router_002:src_valid -> cmd_demux_002:sink_valid
+	wire  [120:0] router_002_src_data;                                                                       // router_002:src_data -> cmd_demux_002:sink_data
+	wire          router_002_src_ready;                                                                      // cmd_demux_002:sink_ready -> router_002:src_ready
+	wire   [20:0] router_002_src_channel;                                                                    // router_002:src_channel -> cmd_demux_002:sink_channel
+	wire          router_002_src_startofpacket;                                                              // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
+	wire          router_002_src_endofpacket;                                                                // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
+	wire          msgdma_rx_mm_write_agent_cp_valid;                                                         // msgdma_rx_mm_write_agent:cp_valid -> router_003:sink_valid
+	wire  [120:0] msgdma_rx_mm_write_agent_cp_data;                                                          // msgdma_rx_mm_write_agent:cp_data -> router_003:sink_data
+	wire          msgdma_rx_mm_write_agent_cp_ready;                                                         // router_003:sink_ready -> msgdma_rx_mm_write_agent:cp_ready
+	wire          msgdma_rx_mm_write_agent_cp_startofpacket;                                                 // msgdma_rx_mm_write_agent:cp_startofpacket -> router_003:sink_startofpacket
+	wire          msgdma_rx_mm_write_agent_cp_endofpacket;                                                   // msgdma_rx_mm_write_agent:cp_endofpacket -> router_003:sink_endofpacket
+	wire          router_003_src_valid;                                                                      // router_003:src_valid -> cmd_demux_003:sink_valid
+	wire  [120:0] router_003_src_data;                                                                       // router_003:src_data -> cmd_demux_003:sink_data
+	wire          router_003_src_ready;                                                                      // cmd_demux_003:sink_ready -> router_003:src_ready
+	wire   [20:0] router_003_src_channel;                                                                    // router_003:src_channel -> cmd_demux_003:sink_channel
+	wire          router_003_src_startofpacket;                                                              // router_003:src_startofpacket -> cmd_demux_003:sink_startofpacket
+	wire          router_003_src_endofpacket;                                                                // router_003:src_endofpacket -> cmd_demux_003:sink_endofpacket
+	wire          msgdma_tx_descriptor_read_master_agent_cp_valid;                                           // msgdma_tx_descriptor_read_master_agent:cp_valid -> router_004:sink_valid
+	wire  [120:0] msgdma_tx_descriptor_read_master_agent_cp_data;                                            // msgdma_tx_descriptor_read_master_agent:cp_data -> router_004:sink_data
+	wire          msgdma_tx_descriptor_read_master_agent_cp_ready;                                           // router_004:sink_ready -> msgdma_tx_descriptor_read_master_agent:cp_ready
+	wire          msgdma_tx_descriptor_read_master_agent_cp_startofpacket;                                   // msgdma_tx_descriptor_read_master_agent:cp_startofpacket -> router_004:sink_startofpacket
+	wire          msgdma_tx_descriptor_read_master_agent_cp_endofpacket;                                     // msgdma_tx_descriptor_read_master_agent:cp_endofpacket -> router_004:sink_endofpacket
+	wire          router_004_src_valid;                                                                      // router_004:src_valid -> cmd_demux_004:sink_valid
+	wire  [120:0] router_004_src_data;                                                                       // router_004:src_data -> cmd_demux_004:sink_data
+	wire          router_004_src_ready;                                                                      // cmd_demux_004:sink_ready -> router_004:src_ready
+	wire   [20:0] router_004_src_channel;                                                                    // router_004:src_channel -> cmd_demux_004:sink_channel
+	wire          router_004_src_startofpacket;                                                              // router_004:src_startofpacket -> cmd_demux_004:sink_startofpacket
+	wire          router_004_src_endofpacket;                                                                // router_004:src_endofpacket -> cmd_demux_004:sink_endofpacket
+	wire          msgdma_rx_descriptor_read_master_agent_cp_valid;                                           // msgdma_rx_descriptor_read_master_agent:cp_valid -> router_005:sink_valid
+	wire  [120:0] msgdma_rx_descriptor_read_master_agent_cp_data;                                            // msgdma_rx_descriptor_read_master_agent:cp_data -> router_005:sink_data
+	wire          msgdma_rx_descriptor_read_master_agent_cp_ready;                                           // router_005:sink_ready -> msgdma_rx_descriptor_read_master_agent:cp_ready
+	wire          msgdma_rx_descriptor_read_master_agent_cp_startofpacket;                                   // msgdma_rx_descriptor_read_master_agent:cp_startofpacket -> router_005:sink_startofpacket
+	wire          msgdma_rx_descriptor_read_master_agent_cp_endofpacket;                                     // msgdma_rx_descriptor_read_master_agent:cp_endofpacket -> router_005:sink_endofpacket
+	wire          router_005_src_valid;                                                                      // router_005:src_valid -> cmd_demux_005:sink_valid
+	wire  [120:0] router_005_src_data;                                                                       // router_005:src_data -> cmd_demux_005:sink_data
+	wire          router_005_src_ready;                                                                      // cmd_demux_005:sink_ready -> router_005:src_ready
+	wire   [20:0] router_005_src_channel;                                                                    // router_005:src_channel -> cmd_demux_005:sink_channel
+	wire          router_005_src_startofpacket;                                                              // router_005:src_startofpacket -> cmd_demux_005:sink_startofpacket
+	wire          router_005_src_endofpacket;                                                                // router_005:src_endofpacket -> cmd_demux_005:sink_endofpacket
+	wire          msgdma_tx_descriptor_write_master_agent_cp_valid;                                          // msgdma_tx_descriptor_write_master_agent:cp_valid -> router_006:sink_valid
+	wire  [120:0] msgdma_tx_descriptor_write_master_agent_cp_data;                                           // msgdma_tx_descriptor_write_master_agent:cp_data -> router_006:sink_data
+	wire          msgdma_tx_descriptor_write_master_agent_cp_ready;                                          // router_006:sink_ready -> msgdma_tx_descriptor_write_master_agent:cp_ready
+	wire          msgdma_tx_descriptor_write_master_agent_cp_startofpacket;                                  // msgdma_tx_descriptor_write_master_agent:cp_startofpacket -> router_006:sink_startofpacket
+	wire          msgdma_tx_descriptor_write_master_agent_cp_endofpacket;                                    // msgdma_tx_descriptor_write_master_agent:cp_endofpacket -> router_006:sink_endofpacket
+	wire          router_006_src_valid;                                                                      // router_006:src_valid -> cmd_demux_006:sink_valid
+	wire  [120:0] router_006_src_data;                                                                       // router_006:src_data -> cmd_demux_006:sink_data
+	wire          router_006_src_ready;                                                                      // cmd_demux_006:sink_ready -> router_006:src_ready
+	wire   [20:0] router_006_src_channel;                                                                    // router_006:src_channel -> cmd_demux_006:sink_channel
+	wire          router_006_src_startofpacket;                                                              // router_006:src_startofpacket -> cmd_demux_006:sink_startofpacket
+	wire          router_006_src_endofpacket;                                                                // router_006:src_endofpacket -> cmd_demux_006:sink_endofpacket
+	wire          msgdma_rx_descriptor_write_master_agent_cp_valid;                                          // msgdma_rx_descriptor_write_master_agent:cp_valid -> router_007:sink_valid
+	wire  [120:0] msgdma_rx_descriptor_write_master_agent_cp_data;                                           // msgdma_rx_descriptor_write_master_agent:cp_data -> router_007:sink_data
+	wire          msgdma_rx_descriptor_write_master_agent_cp_ready;                                          // router_007:sink_ready -> msgdma_rx_descriptor_write_master_agent:cp_ready
+	wire          msgdma_rx_descriptor_write_master_agent_cp_startofpacket;                                  // msgdma_rx_descriptor_write_master_agent:cp_startofpacket -> router_007:sink_startofpacket
+	wire          msgdma_rx_descriptor_write_master_agent_cp_endofpacket;                                    // msgdma_rx_descriptor_write_master_agent:cp_endofpacket -> router_007:sink_endofpacket
+	wire          router_007_src_valid;                                                                      // router_007:src_valid -> cmd_demux_007:sink_valid
+	wire  [120:0] router_007_src_data;                                                                       // router_007:src_data -> cmd_demux_007:sink_data
+	wire          router_007_src_ready;                                                                      // cmd_demux_007:sink_ready -> router_007:src_ready
+	wire   [20:0] router_007_src_channel;                                                                    // router_007:src_channel -> cmd_demux_007:sink_channel
+	wire          router_007_src_startofpacket;                                                              // router_007:src_startofpacket -> cmd_demux_007:sink_startofpacket
+	wire          router_007_src_endofpacket;                                                                // router_007:src_endofpacket -> cmd_demux_007:sink_endofpacket
+	wire          ddr3_ram_avl_agent_rp_valid;                                                               // ddr3_ram_avl_agent:rp_valid -> router_008:sink_valid
+	wire  [120:0] ddr3_ram_avl_agent_rp_data;                                                                // ddr3_ram_avl_agent:rp_data -> router_008:sink_data
+	wire          ddr3_ram_avl_agent_rp_ready;                                                               // router_008:sink_ready -> ddr3_ram_avl_agent:rp_ready
+	wire          ddr3_ram_avl_agent_rp_startofpacket;                                                       // ddr3_ram_avl_agent:rp_startofpacket -> router_008:sink_startofpacket
+	wire          ddr3_ram_avl_agent_rp_endofpacket;                                                         // ddr3_ram_avl_agent:rp_endofpacket -> router_008:sink_endofpacket
+	wire          router_008_src_valid;                                                                      // router_008:src_valid -> rsp_demux:sink_valid
+	wire  [120:0] router_008_src_data;                                                                       // router_008:src_data -> rsp_demux:sink_data
+	wire          router_008_src_ready;                                                                      // rsp_demux:sink_ready -> router_008:src_ready
+	wire   [20:0] router_008_src_channel;                                                                    // router_008:src_channel -> rsp_demux:sink_channel
+	wire          router_008_src_startofpacket;                                                              // router_008:src_startofpacket -> rsp_demux:sink_startofpacket
+	wire          router_008_src_endofpacket;                                                                // router_008:src_endofpacket -> rsp_demux:sink_endofpacket
+	wire          ext_flash_avl_csr_agent_rp_valid;                                                          // ext_flash_avl_csr_agent:rp_valid -> router_009:sink_valid
+	wire  [120:0] ext_flash_avl_csr_agent_rp_data;                                                           // ext_flash_avl_csr_agent:rp_data -> router_009:sink_data
+	wire          ext_flash_avl_csr_agent_rp_ready;                                                          // router_009:sink_ready -> ext_flash_avl_csr_agent:rp_ready
+	wire          ext_flash_avl_csr_agent_rp_startofpacket;                                                  // ext_flash_avl_csr_agent:rp_startofpacket -> router_009:sink_startofpacket
+	wire          ext_flash_avl_csr_agent_rp_endofpacket;                                                    // ext_flash_avl_csr_agent:rp_endofpacket -> router_009:sink_endofpacket
+	wire          router_009_src_valid;                                                                      // router_009:src_valid -> rsp_demux_001:sink_valid
+	wire  [120:0] router_009_src_data;                                                                       // router_009:src_data -> rsp_demux_001:sink_data
+	wire          router_009_src_ready;                                                                      // rsp_demux_001:sink_ready -> router_009:src_ready
+	wire   [20:0] router_009_src_channel;                                                                    // router_009:src_channel -> rsp_demux_001:sink_channel
+	wire          router_009_src_startofpacket;                                                              // router_009:src_startofpacket -> rsp_demux_001:sink_startofpacket
+	wire          router_009_src_endofpacket;                                                                // router_009:src_endofpacket -> rsp_demux_001:sink_endofpacket
+	wire          ext_flash_avl_mem_agent_rp_valid;                                                          // ext_flash_avl_mem_agent:rp_valid -> router_010:sink_valid
+	wire  [120:0] ext_flash_avl_mem_agent_rp_data;                                                           // ext_flash_avl_mem_agent:rp_data -> router_010:sink_data
+	wire          ext_flash_avl_mem_agent_rp_ready;                                                          // router_010:sink_ready -> ext_flash_avl_mem_agent:rp_ready
+	wire          ext_flash_avl_mem_agent_rp_startofpacket;                                                  // ext_flash_avl_mem_agent:rp_startofpacket -> router_010:sink_startofpacket
+	wire          ext_flash_avl_mem_agent_rp_endofpacket;                                                    // ext_flash_avl_mem_agent:rp_endofpacket -> router_010:sink_endofpacket
+	wire          router_010_src_valid;                                                                      // router_010:src_valid -> rsp_demux_002:sink_valid
+	wire  [120:0] router_010_src_data;                                                                       // router_010:src_data -> rsp_demux_002:sink_data
+	wire          router_010_src_ready;                                                                      // rsp_demux_002:sink_ready -> router_010:src_ready
+	wire   [20:0] router_010_src_channel;                                                                    // router_010:src_channel -> rsp_demux_002:sink_channel
+	wire          router_010_src_startofpacket;                                                              // router_010:src_startofpacket -> rsp_demux_002:sink_startofpacket
+	wire          router_010_src_endofpacket;                                                                // router_010:src_endofpacket -> rsp_demux_002:sink_endofpacket
+	wire          eth_tse_control_port_agent_rp_valid;                                                       // eth_tse_control_port_agent:rp_valid -> router_011:sink_valid
+	wire  [120:0] eth_tse_control_port_agent_rp_data;                                                        // eth_tse_control_port_agent:rp_data -> router_011:sink_data
+	wire          eth_tse_control_port_agent_rp_ready;                                                       // router_011:sink_ready -> eth_tse_control_port_agent:rp_ready
+	wire          eth_tse_control_port_agent_rp_startofpacket;                                               // eth_tse_control_port_agent:rp_startofpacket -> router_011:sink_startofpacket
+	wire          eth_tse_control_port_agent_rp_endofpacket;                                                 // eth_tse_control_port_agent:rp_endofpacket -> router_011:sink_endofpacket
+	wire          router_011_src_valid;                                                                      // router_011:src_valid -> rsp_demux_003:sink_valid
+	wire  [120:0] router_011_src_data;                                                                       // router_011:src_data -> rsp_demux_003:sink_data
+	wire          router_011_src_ready;                                                                      // rsp_demux_003:sink_ready -> router_011:src_ready
+	wire   [20:0] router_011_src_channel;                                                                    // router_011:src_channel -> rsp_demux_003:sink_channel
+	wire          router_011_src_startofpacket;                                                              // router_011:src_startofpacket -> rsp_demux_003:sink_startofpacket
+	wire          router_011_src_endofpacket;                                                                // router_011:src_endofpacket -> rsp_demux_003:sink_endofpacket
+	wire          sysid_control_slave_agent_rp_valid;                                                        // sysid_control_slave_agent:rp_valid -> router_012:sink_valid
+	wire  [120:0] sysid_control_slave_agent_rp_data;                                                         // sysid_control_slave_agent:rp_data -> router_012:sink_data
+	wire          sysid_control_slave_agent_rp_ready;                                                        // router_012:sink_ready -> sysid_control_slave_agent:rp_ready
+	wire          sysid_control_slave_agent_rp_startofpacket;                                                // sysid_control_slave_agent:rp_startofpacket -> router_012:sink_startofpacket
+	wire          sysid_control_slave_agent_rp_endofpacket;                                                  // sysid_control_slave_agent:rp_endofpacket -> router_012:sink_endofpacket
+	wire          router_012_src_valid;                                                                      // router_012:src_valid -> rsp_demux_004:sink_valid
+	wire  [120:0] router_012_src_data;                                                                       // router_012:src_data -> rsp_demux_004:sink_data
+	wire          router_012_src_ready;                                                                      // rsp_demux_004:sink_ready -> router_012:src_ready
+	wire   [20:0] router_012_src_channel;                                                                    // router_012:src_channel -> rsp_demux_004:sink_channel
+	wire          router_012_src_startofpacket;                                                              // router_012:src_startofpacket -> rsp_demux_004:sink_startofpacket
+	wire          router_012_src_endofpacket;                                                                // router_012:src_endofpacket -> rsp_demux_004:sink_endofpacket
+	wire          msgdma_tx_csr_agent_rp_valid;                                                              // msgdma_tx_csr_agent:rp_valid -> router_013:sink_valid
+	wire  [120:0] msgdma_tx_csr_agent_rp_data;                                                               // msgdma_tx_csr_agent:rp_data -> router_013:sink_data
+	wire          msgdma_tx_csr_agent_rp_ready;                                                              // router_013:sink_ready -> msgdma_tx_csr_agent:rp_ready
+	wire          msgdma_tx_csr_agent_rp_startofpacket;                                                      // msgdma_tx_csr_agent:rp_startofpacket -> router_013:sink_startofpacket
+	wire          msgdma_tx_csr_agent_rp_endofpacket;                                                        // msgdma_tx_csr_agent:rp_endofpacket -> router_013:sink_endofpacket
+	wire          router_013_src_valid;                                                                      // router_013:src_valid -> rsp_demux_005:sink_valid
+	wire  [120:0] router_013_src_data;                                                                       // router_013:src_data -> rsp_demux_005:sink_data
+	wire          router_013_src_ready;                                                                      // rsp_demux_005:sink_ready -> router_013:src_ready
+	wire   [20:0] router_013_src_channel;                                                                    // router_013:src_channel -> rsp_demux_005:sink_channel
+	wire          router_013_src_startofpacket;                                                              // router_013:src_startofpacket -> rsp_demux_005:sink_startofpacket
+	wire          router_013_src_endofpacket;                                                                // router_013:src_endofpacket -> rsp_demux_005:sink_endofpacket
+	wire          msgdma_rx_csr_agent_rp_valid;                                                              // msgdma_rx_csr_agent:rp_valid -> router_014:sink_valid
+	wire  [120:0] msgdma_rx_csr_agent_rp_data;                                                               // msgdma_rx_csr_agent:rp_data -> router_014:sink_data
+	wire          msgdma_rx_csr_agent_rp_ready;                                                              // router_014:sink_ready -> msgdma_rx_csr_agent:rp_ready
+	wire          msgdma_rx_csr_agent_rp_startofpacket;                                                      // msgdma_rx_csr_agent:rp_startofpacket -> router_014:sink_startofpacket
+	wire          msgdma_rx_csr_agent_rp_endofpacket;                                                        // msgdma_rx_csr_agent:rp_endofpacket -> router_014:sink_endofpacket
+	wire          router_014_src_valid;                                                                      // router_014:src_valid -> rsp_demux_006:sink_valid
+	wire  [120:0] router_014_src_data;                                                                       // router_014:src_data -> rsp_demux_006:sink_data
+	wire          router_014_src_ready;                                                                      // rsp_demux_006:sink_ready -> router_014:src_ready
+	wire   [20:0] router_014_src_channel;                                                                    // router_014:src_channel -> rsp_demux_006:sink_channel
+	wire          router_014_src_startofpacket;                                                              // router_014:src_startofpacket -> rsp_demux_006:sink_startofpacket
+	wire          router_014_src_endofpacket;                                                                // router_014:src_endofpacket -> rsp_demux_006:sink_endofpacket
+	wire          onchip_flash_csr_agent_rp_valid;                                                           // onchip_flash_csr_agent:rp_valid -> router_015:sink_valid
+	wire  [120:0] onchip_flash_csr_agent_rp_data;                                                            // onchip_flash_csr_agent:rp_data -> router_015:sink_data
+	wire          onchip_flash_csr_agent_rp_ready;                                                           // router_015:sink_ready -> onchip_flash_csr_agent:rp_ready
+	wire          onchip_flash_csr_agent_rp_startofpacket;                                                   // onchip_flash_csr_agent:rp_startofpacket -> router_015:sink_startofpacket
+	wire          onchip_flash_csr_agent_rp_endofpacket;                                                     // onchip_flash_csr_agent:rp_endofpacket -> router_015:sink_endofpacket
+	wire          router_015_src_valid;                                                                      // router_015:src_valid -> rsp_demux_007:sink_valid
+	wire  [120:0] router_015_src_data;                                                                       // router_015:src_data -> rsp_demux_007:sink_data
+	wire          router_015_src_ready;                                                                      // rsp_demux_007:sink_ready -> router_015:src_ready
+	wire   [20:0] router_015_src_channel;                                                                    // router_015:src_channel -> rsp_demux_007:sink_channel
+	wire          router_015_src_startofpacket;                                                              // router_015:src_startofpacket -> rsp_demux_007:sink_startofpacket
+	wire          router_015_src_endofpacket;                                                                // router_015:src_endofpacket -> rsp_demux_007:sink_endofpacket
+	wire          udp_generator_csr_agent_rp_valid;                                                          // udp_generator_csr_agent:rp_valid -> router_016:sink_valid
+	wire  [120:0] udp_generator_csr_agent_rp_data;                                                           // udp_generator_csr_agent:rp_data -> router_016:sink_data
+	wire          udp_generator_csr_agent_rp_ready;                                                          // router_016:sink_ready -> udp_generator_csr_agent:rp_ready
+	wire          udp_generator_csr_agent_rp_startofpacket;                                                  // udp_generator_csr_agent:rp_startofpacket -> router_016:sink_startofpacket
+	wire          udp_generator_csr_agent_rp_endofpacket;                                                    // udp_generator_csr_agent:rp_endofpacket -> router_016:sink_endofpacket
+	wire          router_016_src_valid;                                                                      // router_016:src_valid -> rsp_demux_008:sink_valid
+	wire  [120:0] router_016_src_data;                                                                       // router_016:src_data -> rsp_demux_008:sink_data
+	wire          router_016_src_ready;                                                                      // rsp_demux_008:sink_ready -> router_016:src_ready
+	wire   [20:0] router_016_src_channel;                                                                    // router_016:src_channel -> rsp_demux_008:sink_channel
+	wire          router_016_src_startofpacket;                                                              // router_016:src_startofpacket -> rsp_demux_008:sink_startofpacket
+	wire          router_016_src_endofpacket;                                                                // router_016:src_endofpacket -> rsp_demux_008:sink_endofpacket
+	wire          sensor_interface_csr_agent_rp_valid;                                                       // sensor_interface_csr_agent:rp_valid -> router_017:sink_valid
+	wire  [120:0] sensor_interface_csr_agent_rp_data;                                                        // sensor_interface_csr_agent:rp_data -> router_017:sink_data
+	wire          sensor_interface_csr_agent_rp_ready;                                                       // router_017:sink_ready -> sensor_interface_csr_agent:rp_ready
+	wire          sensor_interface_csr_agent_rp_startofpacket;                                               // sensor_interface_csr_agent:rp_startofpacket -> router_017:sink_startofpacket
+	wire          sensor_interface_csr_agent_rp_endofpacket;                                                 // sensor_interface_csr_agent:rp_endofpacket -> router_017:sink_endofpacket
+	wire          router_017_src_valid;                                                                      // router_017:src_valid -> rsp_demux_009:sink_valid
+	wire  [120:0] router_017_src_data;                                                                       // router_017:src_data -> rsp_demux_009:sink_data
+	wire          router_017_src_ready;                                                                      // rsp_demux_009:sink_ready -> router_017:src_ready
+	wire   [20:0] router_017_src_channel;                                                                    // router_017:src_channel -> rsp_demux_009:sink_channel
+	wire          router_017_src_startofpacket;                                                              // router_017:src_startofpacket -> rsp_demux_009:sink_startofpacket
+	wire          router_017_src_endofpacket;                                                                // router_017:src_endofpacket -> rsp_demux_009:sink_endofpacket
+	wire          onchip_flash_data_agent_rp_valid;                                                          // onchip_flash_data_agent:rp_valid -> router_018:sink_valid
+	wire  [120:0] onchip_flash_data_agent_rp_data;                                                           // onchip_flash_data_agent:rp_data -> router_018:sink_data
+	wire          onchip_flash_data_agent_rp_ready;                                                          // router_018:sink_ready -> onchip_flash_data_agent:rp_ready
+	wire          onchip_flash_data_agent_rp_startofpacket;                                                  // onchip_flash_data_agent:rp_startofpacket -> router_018:sink_startofpacket
+	wire          onchip_flash_data_agent_rp_endofpacket;                                                    // onchip_flash_data_agent:rp_endofpacket -> router_018:sink_endofpacket
+	wire          router_018_src_valid;                                                                      // router_018:src_valid -> rsp_demux_010:sink_valid
+	wire  [120:0] router_018_src_data;                                                                       // router_018:src_data -> rsp_demux_010:sink_data
+	wire          router_018_src_ready;                                                                      // rsp_demux_010:sink_ready -> router_018:src_ready
+	wire   [20:0] router_018_src_channel;                                                                    // router_018:src_channel -> rsp_demux_010:sink_channel
+	wire          router_018_src_startofpacket;                                                              // router_018:src_startofpacket -> rsp_demux_010:sink_startofpacket
+	wire          router_018_src_endofpacket;                                                                // router_018:src_endofpacket -> rsp_demux_010:sink_endofpacket
+	wire          cpu_debug_mem_slave_agent_rp_valid;                                                        // cpu_debug_mem_slave_agent:rp_valid -> router_019:sink_valid
+	wire  [120:0] cpu_debug_mem_slave_agent_rp_data;                                                         // cpu_debug_mem_slave_agent:rp_data -> router_019:sink_data
+	wire          cpu_debug_mem_slave_agent_rp_ready;                                                        // router_019:sink_ready -> cpu_debug_mem_slave_agent:rp_ready
+	wire          cpu_debug_mem_slave_agent_rp_startofpacket;                                                // cpu_debug_mem_slave_agent:rp_startofpacket -> router_019:sink_startofpacket
+	wire          cpu_debug_mem_slave_agent_rp_endofpacket;                                                  // cpu_debug_mem_slave_agent:rp_endofpacket -> router_019:sink_endofpacket
+	wire          router_019_src_valid;                                                                      // router_019:src_valid -> rsp_demux_011:sink_valid
+	wire  [120:0] router_019_src_data;                                                                       // router_019:src_data -> rsp_demux_011:sink_data
+	wire          router_019_src_ready;                                                                      // rsp_demux_011:sink_ready -> router_019:src_ready
+	wire   [20:0] router_019_src_channel;                                                                    // router_019:src_channel -> rsp_demux_011:sink_channel
+	wire          router_019_src_startofpacket;                                                              // router_019:src_startofpacket -> rsp_demux_011:sink_startofpacket
+	wire          router_019_src_endofpacket;                                                                // router_019:src_endofpacket -> rsp_demux_011:sink_endofpacket
+	wire          msgdma_tx_prefetcher_csr_agent_rp_valid;                                                   // msgdma_tx_prefetcher_csr_agent:rp_valid -> router_020:sink_valid
+	wire  [120:0] msgdma_tx_prefetcher_csr_agent_rp_data;                                                    // msgdma_tx_prefetcher_csr_agent:rp_data -> router_020:sink_data
+	wire          msgdma_tx_prefetcher_csr_agent_rp_ready;                                                   // router_020:sink_ready -> msgdma_tx_prefetcher_csr_agent:rp_ready
+	wire          msgdma_tx_prefetcher_csr_agent_rp_startofpacket;                                           // msgdma_tx_prefetcher_csr_agent:rp_startofpacket -> router_020:sink_startofpacket
+	wire          msgdma_tx_prefetcher_csr_agent_rp_endofpacket;                                             // msgdma_tx_prefetcher_csr_agent:rp_endofpacket -> router_020:sink_endofpacket
+	wire          router_020_src_valid;                                                                      // router_020:src_valid -> rsp_demux_012:sink_valid
+	wire  [120:0] router_020_src_data;                                                                       // router_020:src_data -> rsp_demux_012:sink_data
+	wire          router_020_src_ready;                                                                      // rsp_demux_012:sink_ready -> router_020:src_ready
+	wire   [20:0] router_020_src_channel;                                                                    // router_020:src_channel -> rsp_demux_012:sink_channel
+	wire          router_020_src_startofpacket;                                                              // router_020:src_startofpacket -> rsp_demux_012:sink_startofpacket
+	wire          router_020_src_endofpacket;                                                                // router_020:src_endofpacket -> rsp_demux_012:sink_endofpacket
+	wire          msgdma_rx_prefetcher_csr_agent_rp_valid;                                                   // msgdma_rx_prefetcher_csr_agent:rp_valid -> router_021:sink_valid
+	wire  [120:0] msgdma_rx_prefetcher_csr_agent_rp_data;                                                    // msgdma_rx_prefetcher_csr_agent:rp_data -> router_021:sink_data
+	wire          msgdma_rx_prefetcher_csr_agent_rp_ready;                                                   // router_021:sink_ready -> msgdma_rx_prefetcher_csr_agent:rp_ready
+	wire          msgdma_rx_prefetcher_csr_agent_rp_startofpacket;                                           // msgdma_rx_prefetcher_csr_agent:rp_startofpacket -> router_021:sink_startofpacket
+	wire          msgdma_rx_prefetcher_csr_agent_rp_endofpacket;                                             // msgdma_rx_prefetcher_csr_agent:rp_endofpacket -> router_021:sink_endofpacket
+	wire          router_021_src_valid;                                                                      // router_021:src_valid -> rsp_demux_013:sink_valid
+	wire  [120:0] router_021_src_data;                                                                       // router_021:src_data -> rsp_demux_013:sink_data
+	wire          router_021_src_ready;                                                                      // rsp_demux_013:sink_ready -> router_021:src_ready
+	wire   [20:0] router_021_src_channel;                                                                    // router_021:src_channel -> rsp_demux_013:sink_channel
+	wire          router_021_src_startofpacket;                                                              // router_021:src_startofpacket -> rsp_demux_013:sink_startofpacket
+	wire          router_021_src_endofpacket;                                                                // router_021:src_endofpacket -> rsp_demux_013:sink_endofpacket
+	wire          descriptor_memory_s1_agent_rp_valid;                                                       // descriptor_memory_s1_agent:rp_valid -> router_022:sink_valid
+	wire  [120:0] descriptor_memory_s1_agent_rp_data;                                                        // descriptor_memory_s1_agent:rp_data -> router_022:sink_data
+	wire          descriptor_memory_s1_agent_rp_ready;                                                       // router_022:sink_ready -> descriptor_memory_s1_agent:rp_ready
+	wire          descriptor_memory_s1_agent_rp_startofpacket;                                               // descriptor_memory_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
+	wire          descriptor_memory_s1_agent_rp_endofpacket;                                                 // descriptor_memory_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
+	wire          router_022_src_valid;                                                                      // router_022:src_valid -> rsp_demux_014:sink_valid
+	wire  [120:0] router_022_src_data;                                                                       // router_022:src_data -> rsp_demux_014:sink_data
+	wire          router_022_src_ready;                                                                      // rsp_demux_014:sink_ready -> router_022:src_ready
+	wire   [20:0] router_022_src_channel;                                                                    // router_022:src_channel -> rsp_demux_014:sink_channel
+	wire          router_022_src_startofpacket;                                                              // router_022:src_startofpacket -> rsp_demux_014:sink_startofpacket
+	wire          router_022_src_endofpacket;                                                                // router_022:src_endofpacket -> rsp_demux_014:sink_endofpacket
+	wire          sys_clk_timer_s1_agent_rp_valid;                                                           // sys_clk_timer_s1_agent:rp_valid -> router_023:sink_valid
+	wire  [120:0] sys_clk_timer_s1_agent_rp_data;                                                            // sys_clk_timer_s1_agent:rp_data -> router_023:sink_data
+	wire          sys_clk_timer_s1_agent_rp_ready;                                                           // router_023:sink_ready -> sys_clk_timer_s1_agent:rp_ready
+	wire          sys_clk_timer_s1_agent_rp_startofpacket;                                                   // sys_clk_timer_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
+	wire          sys_clk_timer_s1_agent_rp_endofpacket;                                                     // sys_clk_timer_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
+	wire          router_023_src_valid;                                                                      // router_023:src_valid -> rsp_demux_015:sink_valid
+	wire  [120:0] router_023_src_data;                                                                       // router_023:src_data -> rsp_demux_015:sink_data
+	wire          router_023_src_ready;                                                                      // rsp_demux_015:sink_ready -> router_023:src_ready
+	wire   [20:0] router_023_src_channel;                                                                    // router_023:src_channel -> rsp_demux_015:sink_channel
+	wire          router_023_src_startofpacket;                                                              // router_023:src_startofpacket -> rsp_demux_015:sink_startofpacket
+	wire          router_023_src_endofpacket;                                                                // router_023:src_endofpacket -> rsp_demux_015:sink_endofpacket
+	wire          output_pio_s1_agent_rp_valid;                                                              // output_pio_s1_agent:rp_valid -> router_024:sink_valid
+	wire  [120:0] output_pio_s1_agent_rp_data;                                                               // output_pio_s1_agent:rp_data -> router_024:sink_data
+	wire          output_pio_s1_agent_rp_ready;                                                              // router_024:sink_ready -> output_pio_s1_agent:rp_ready
+	wire          output_pio_s1_agent_rp_startofpacket;                                                      // output_pio_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
+	wire          output_pio_s1_agent_rp_endofpacket;                                                        // output_pio_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
+	wire          router_024_src_valid;                                                                      // router_024:src_valid -> rsp_demux_016:sink_valid
+	wire  [120:0] router_024_src_data;                                                                       // router_024:src_data -> rsp_demux_016:sink_data
+	wire          router_024_src_ready;                                                                      // rsp_demux_016:sink_ready -> router_024:src_ready
+	wire   [20:0] router_024_src_channel;                                                                    // router_024:src_channel -> rsp_demux_016:sink_channel
+	wire          router_024_src_startofpacket;                                                              // router_024:src_startofpacket -> rsp_demux_016:sink_startofpacket
+	wire          router_024_src_endofpacket;                                                                // router_024:src_endofpacket -> rsp_demux_016:sink_endofpacket
+	wire          button_pio_s1_agent_rp_valid;                                                              // button_pio_s1_agent:rp_valid -> router_025:sink_valid
+	wire  [120:0] button_pio_s1_agent_rp_data;                                                               // button_pio_s1_agent:rp_data -> router_025:sink_data
+	wire          button_pio_s1_agent_rp_ready;                                                              // router_025:sink_ready -> button_pio_s1_agent:rp_ready
+	wire          button_pio_s1_agent_rp_startofpacket;                                                      // button_pio_s1_agent:rp_startofpacket -> router_025:sink_startofpacket
+	wire          button_pio_s1_agent_rp_endofpacket;                                                        // button_pio_s1_agent:rp_endofpacket -> router_025:sink_endofpacket
+	wire          router_025_src_valid;                                                                      // router_025:src_valid -> rsp_demux_017:sink_valid
+	wire  [120:0] router_025_src_data;                                                                       // router_025:src_data -> rsp_demux_017:sink_data
+	wire          router_025_src_ready;                                                                      // rsp_demux_017:sink_ready -> router_025:src_ready
+	wire   [20:0] router_025_src_channel;                                                                    // router_025:src_channel -> rsp_demux_017:sink_channel
+	wire          router_025_src_startofpacket;                                                              // router_025:src_startofpacket -> rsp_demux_017:sink_startofpacket
+	wire          router_025_src_endofpacket;                                                                // router_025:src_endofpacket -> rsp_demux_017:sink_endofpacket
+	wire          debug_uart_s1_agent_rp_valid;                                                              // debug_uart_s1_agent:rp_valid -> router_026:sink_valid
+	wire  [120:0] debug_uart_s1_agent_rp_data;                                                               // debug_uart_s1_agent:rp_data -> router_026:sink_data
+	wire          debug_uart_s1_agent_rp_ready;                                                              // router_026:sink_ready -> debug_uart_s1_agent:rp_ready
+	wire          debug_uart_s1_agent_rp_startofpacket;                                                      // debug_uart_s1_agent:rp_startofpacket -> router_026:sink_startofpacket
+	wire          debug_uart_s1_agent_rp_endofpacket;                                                        // debug_uart_s1_agent:rp_endofpacket -> router_026:sink_endofpacket
+	wire          router_026_src_valid;                                                                      // router_026:src_valid -> rsp_demux_018:sink_valid
+	wire  [120:0] router_026_src_data;                                                                       // router_026:src_data -> rsp_demux_018:sink_data
+	wire          router_026_src_ready;                                                                      // rsp_demux_018:sink_ready -> router_026:src_ready
+	wire   [20:0] router_026_src_channel;                                                                    // router_026:src_channel -> rsp_demux_018:sink_channel
+	wire          router_026_src_startofpacket;                                                              // router_026:src_startofpacket -> rsp_demux_018:sink_startofpacket
+	wire          router_026_src_endofpacket;                                                                // router_026:src_endofpacket -> rsp_demux_018:sink_endofpacket
+	wire          frame_timer_s1_agent_rp_valid;                                                             // frame_timer_s1_agent:rp_valid -> router_027:sink_valid
+	wire  [120:0] frame_timer_s1_agent_rp_data;                                                              // frame_timer_s1_agent:rp_data -> router_027:sink_data
+	wire          frame_timer_s1_agent_rp_ready;                                                             // router_027:sink_ready -> frame_timer_s1_agent:rp_ready
+	wire          frame_timer_s1_agent_rp_startofpacket;                                                     // frame_timer_s1_agent:rp_startofpacket -> router_027:sink_startofpacket
+	wire          frame_timer_s1_agent_rp_endofpacket;                                                       // frame_timer_s1_agent:rp_endofpacket -> router_027:sink_endofpacket
+	wire          router_027_src_valid;                                                                      // router_027:src_valid -> rsp_demux_019:sink_valid
+	wire  [120:0] router_027_src_data;                                                                       // router_027:src_data -> rsp_demux_019:sink_data
+	wire          router_027_src_ready;                                                                      // rsp_demux_019:sink_ready -> router_027:src_ready
+	wire   [20:0] router_027_src_channel;                                                                    // router_027:src_channel -> rsp_demux_019:sink_channel
+	wire          router_027_src_startofpacket;                                                              // router_027:src_startofpacket -> rsp_demux_019:sink_startofpacket
+	wire          router_027_src_endofpacket;                                                                // router_027:src_endofpacket -> rsp_demux_019:sink_endofpacket
+	wire          calibration_ram_s1_agent_rp_valid;                                                         // calibration_ram_s1_agent:rp_valid -> router_028:sink_valid
+	wire  [102:0] calibration_ram_s1_agent_rp_data;                                                          // calibration_ram_s1_agent:rp_data -> router_028:sink_data
+	wire          calibration_ram_s1_agent_rp_ready;                                                         // router_028:sink_ready -> calibration_ram_s1_agent:rp_ready
+	wire          calibration_ram_s1_agent_rp_startofpacket;                                                 // calibration_ram_s1_agent:rp_startofpacket -> router_028:sink_startofpacket
+	wire          calibration_ram_s1_agent_rp_endofpacket;                                                   // calibration_ram_s1_agent:rp_endofpacket -> router_028:sink_endofpacket
+	wire          router_src_valid;                                                                          // router:src_valid -> cpu_data_master_limiter:cmd_sink_valid
+	wire  [120:0] router_src_data;                                                                           // router:src_data -> cpu_data_master_limiter:cmd_sink_data
+	wire          router_src_ready;                                                                          // cpu_data_master_limiter:cmd_sink_ready -> router:src_ready
+	wire   [20:0] router_src_channel;                                                                        // router:src_channel -> cpu_data_master_limiter:cmd_sink_channel
+	wire          router_src_startofpacket;                                                                  // router:src_startofpacket -> cpu_data_master_limiter:cmd_sink_startofpacket
+	wire          router_src_endofpacket;                                                                    // router:src_endofpacket -> cpu_data_master_limiter:cmd_sink_endofpacket
+	wire  [120:0] cpu_data_master_limiter_cmd_src_data;                                                      // cpu_data_master_limiter:cmd_src_data -> cmd_demux:sink_data
+	wire          cpu_data_master_limiter_cmd_src_ready;                                                     // cmd_demux:sink_ready -> cpu_data_master_limiter:cmd_src_ready
+	wire   [20:0] cpu_data_master_limiter_cmd_src_channel;                                                   // cpu_data_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
+	wire          cpu_data_master_limiter_cmd_src_startofpacket;                                             // cpu_data_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
+	wire          cpu_data_master_limiter_cmd_src_endofpacket;                                               // cpu_data_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
+	wire          rsp_mux_src_valid;                                                                         // rsp_mux:src_valid -> cpu_data_master_limiter:rsp_sink_valid
+	wire  [120:0] rsp_mux_src_data;                                                                          // rsp_mux:src_data -> cpu_data_master_limiter:rsp_sink_data
+	wire          rsp_mux_src_ready;                                                                         // cpu_data_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
+	wire   [20:0] rsp_mux_src_channel;                                                                       // rsp_mux:src_channel -> cpu_data_master_limiter:rsp_sink_channel
+	wire          rsp_mux_src_startofpacket;                                                                 // rsp_mux:src_startofpacket -> cpu_data_master_limiter:rsp_sink_startofpacket
+	wire          rsp_mux_src_endofpacket;                                                                   // rsp_mux:src_endofpacket -> cpu_data_master_limiter:rsp_sink_endofpacket
+	wire          cpu_data_master_limiter_rsp_src_valid;                                                     // cpu_data_master_limiter:rsp_src_valid -> cpu_data_master_agent:rp_valid
+	wire  [120:0] cpu_data_master_limiter_rsp_src_data;                                                      // cpu_data_master_limiter:rsp_src_data -> cpu_data_master_agent:rp_data
+	wire          cpu_data_master_limiter_rsp_src_ready;                                                     // cpu_data_master_agent:rp_ready -> cpu_data_master_limiter:rsp_src_ready
+	wire   [20:0] cpu_data_master_limiter_rsp_src_channel;                                                   // cpu_data_master_limiter:rsp_src_channel -> cpu_data_master_agent:rp_channel
+	wire          cpu_data_master_limiter_rsp_src_startofpacket;                                             // cpu_data_master_limiter:rsp_src_startofpacket -> cpu_data_master_agent:rp_startofpacket
+	wire          cpu_data_master_limiter_rsp_src_endofpacket;                                               // cpu_data_master_limiter:rsp_src_endofpacket -> cpu_data_master_agent:rp_endofpacket
+	wire          router_001_src_valid;                                                                      // router_001:src_valid -> cpu_instruction_master_limiter:cmd_sink_valid
+	wire  [120:0] router_001_src_data;                                                                       // router_001:src_data -> cpu_instruction_master_limiter:cmd_sink_data
+	wire          router_001_src_ready;                                                                      // cpu_instruction_master_limiter:cmd_sink_ready -> router_001:src_ready
+	wire   [20:0] router_001_src_channel;                                                                    // router_001:src_channel -> cpu_instruction_master_limiter:cmd_sink_channel
+	wire          router_001_src_startofpacket;                                                              // router_001:src_startofpacket -> cpu_instruction_master_limiter:cmd_sink_startofpacket
+	wire          router_001_src_endofpacket;                                                                // router_001:src_endofpacket -> cpu_instruction_master_limiter:cmd_sink_endofpacket
+	wire  [120:0] cpu_instruction_master_limiter_cmd_src_data;                                               // cpu_instruction_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
+	wire          cpu_instruction_master_limiter_cmd_src_ready;                                              // cmd_demux_001:sink_ready -> cpu_instruction_master_limiter:cmd_src_ready
+	wire   [20:0] cpu_instruction_master_limiter_cmd_src_channel;                                            // cpu_instruction_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
+	wire          cpu_instruction_master_limiter_cmd_src_startofpacket;                                      // cpu_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
+	wire          cpu_instruction_master_limiter_cmd_src_endofpacket;                                        // cpu_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
+	wire          rsp_mux_001_src_valid;                                                                     // rsp_mux_001:src_valid -> cpu_instruction_master_limiter:rsp_sink_valid
+	wire  [120:0] rsp_mux_001_src_data;                                                                      // rsp_mux_001:src_data -> cpu_instruction_master_limiter:rsp_sink_data
+	wire          rsp_mux_001_src_ready;                                                                     // cpu_instruction_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
+	wire   [20:0] rsp_mux_001_src_channel;                                                                   // rsp_mux_001:src_channel -> cpu_instruction_master_limiter:rsp_sink_channel
+	wire          rsp_mux_001_src_startofpacket;                                                             // rsp_mux_001:src_startofpacket -> cpu_instruction_master_limiter:rsp_sink_startofpacket
+	wire          rsp_mux_001_src_endofpacket;                                                               // rsp_mux_001:src_endofpacket -> cpu_instruction_master_limiter:rsp_sink_endofpacket
+	wire          cpu_instruction_master_limiter_rsp_src_valid;                                              // cpu_instruction_master_limiter:rsp_src_valid -> cpu_instruction_master_agent:rp_valid
+	wire  [120:0] cpu_instruction_master_limiter_rsp_src_data;                                               // cpu_instruction_master_limiter:rsp_src_data -> cpu_instruction_master_agent:rp_data
+	wire          cpu_instruction_master_limiter_rsp_src_ready;                                              // cpu_instruction_master_agent:rp_ready -> cpu_instruction_master_limiter:rsp_src_ready
+	wire   [20:0] cpu_instruction_master_limiter_rsp_src_channel;                                            // cpu_instruction_master_limiter:rsp_src_channel -> cpu_instruction_master_agent:rp_channel
+	wire          cpu_instruction_master_limiter_rsp_src_startofpacket;                                      // cpu_instruction_master_limiter:rsp_src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
+	wire          cpu_instruction_master_limiter_rsp_src_endofpacket;                                        // cpu_instruction_master_limiter:rsp_src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
+	wire          cmd_mux_002_src_valid;                                                                     // cmd_mux_002:src_valid -> ext_flash_avl_mem_burst_adapter:sink0_valid
+	wire  [120:0] cmd_mux_002_src_data;                                                                      // cmd_mux_002:src_data -> ext_flash_avl_mem_burst_adapter:sink0_data
+	wire          cmd_mux_002_src_ready;                                                                     // ext_flash_avl_mem_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
+	wire   [20:0] cmd_mux_002_src_channel;                                                                   // cmd_mux_002:src_channel -> ext_flash_avl_mem_burst_adapter:sink0_channel
+	wire          cmd_mux_002_src_startofpacket;                                                             // cmd_mux_002:src_startofpacket -> ext_flash_avl_mem_burst_adapter:sink0_startofpacket
+	wire          cmd_mux_002_src_endofpacket;                                                               // cmd_mux_002:src_endofpacket -> ext_flash_avl_mem_burst_adapter:sink0_endofpacket
+	wire          ext_flash_avl_mem_burst_adapter_source0_valid;                                             // ext_flash_avl_mem_burst_adapter:source0_valid -> ext_flash_avl_mem_agent:cp_valid
+	wire  [120:0] ext_flash_avl_mem_burst_adapter_source0_data;                                              // ext_flash_avl_mem_burst_adapter:source0_data -> ext_flash_avl_mem_agent:cp_data
+	wire          ext_flash_avl_mem_burst_adapter_source0_ready;                                             // ext_flash_avl_mem_agent:cp_ready -> ext_flash_avl_mem_burst_adapter:source0_ready
+	wire   [20:0] ext_flash_avl_mem_burst_adapter_source0_channel;                                           // ext_flash_avl_mem_burst_adapter:source0_channel -> ext_flash_avl_mem_agent:cp_channel
+	wire          ext_flash_avl_mem_burst_adapter_source0_startofpacket;                                     // ext_flash_avl_mem_burst_adapter:source0_startofpacket -> ext_flash_avl_mem_agent:cp_startofpacket
+	wire          ext_flash_avl_mem_burst_adapter_source0_endofpacket;                                       // ext_flash_avl_mem_burst_adapter:source0_endofpacket -> ext_flash_avl_mem_agent:cp_endofpacket
+	wire          calibration_ram_s1_burst_adapter_source0_valid;                                            // calibration_ram_s1_burst_adapter:source0_valid -> calibration_ram_s1_agent:cp_valid
+	wire  [102:0] calibration_ram_s1_burst_adapter_source0_data;                                             // calibration_ram_s1_burst_adapter:source0_data -> calibration_ram_s1_agent:cp_data
+	wire          calibration_ram_s1_burst_adapter_source0_ready;                                            // calibration_ram_s1_agent:cp_ready -> calibration_ram_s1_burst_adapter:source0_ready
+	wire   [20:0] calibration_ram_s1_burst_adapter_source0_channel;                                          // calibration_ram_s1_burst_adapter:source0_channel -> calibration_ram_s1_agent:cp_channel
+	wire          calibration_ram_s1_burst_adapter_source0_startofpacket;                                    // calibration_ram_s1_burst_adapter:source0_startofpacket -> calibration_ram_s1_agent:cp_startofpacket
+	wire          calibration_ram_s1_burst_adapter_source0_endofpacket;                                      // calibration_ram_s1_burst_adapter:source0_endofpacket -> calibration_ram_s1_agent:cp_endofpacket
+	wire          cmd_demux_src3_valid;                                                                      // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
+	wire  [120:0] cmd_demux_src3_data;                                                                       // cmd_demux:src3_data -> cmd_mux_003:sink0_data
+	wire          cmd_demux_src3_ready;                                                                      // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
+	wire   [20:0] cmd_demux_src3_channel;                                                                    // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
+	wire          cmd_demux_src3_startofpacket;                                                              // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
+	wire          cmd_demux_src3_endofpacket;                                                                // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
+	wire          cmd_demux_src4_valid;                                                                      // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
+	wire  [120:0] cmd_demux_src4_data;                                                                       // cmd_demux:src4_data -> cmd_mux_004:sink0_data
+	wire          cmd_demux_src4_ready;                                                                      // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
+	wire   [20:0] cmd_demux_src4_channel;                                                                    // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
+	wire          cmd_demux_src4_startofpacket;                                                              // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
+	wire          cmd_demux_src4_endofpacket;                                                                // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
+	wire          cmd_demux_src5_valid;                                                                      // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
+	wire  [120:0] cmd_demux_src5_data;                                                                       // cmd_demux:src5_data -> cmd_mux_005:sink0_data
+	wire          cmd_demux_src5_ready;                                                                      // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
+	wire   [20:0] cmd_demux_src5_channel;                                                                    // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
+	wire          cmd_demux_src5_startofpacket;                                                              // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
+	wire          cmd_demux_src5_endofpacket;                                                                // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
+	wire          cmd_demux_src6_valid;                                                                      // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
+	wire  [120:0] cmd_demux_src6_data;                                                                       // cmd_demux:src6_data -> cmd_mux_006:sink0_data
+	wire          cmd_demux_src6_ready;                                                                      // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
+	wire   [20:0] cmd_demux_src6_channel;                                                                    // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
+	wire          cmd_demux_src6_startofpacket;                                                              // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
+	wire          cmd_demux_src6_endofpacket;                                                                // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
+	wire          cmd_demux_src7_valid;                                                                      // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
+	wire  [120:0] cmd_demux_src7_data;                                                                       // cmd_demux:src7_data -> cmd_mux_007:sink0_data
+	wire          cmd_demux_src7_ready;                                                                      // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
+	wire   [20:0] cmd_demux_src7_channel;                                                                    // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
+	wire          cmd_demux_src7_startofpacket;                                                              // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
+	wire          cmd_demux_src7_endofpacket;                                                                // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
+	wire          cmd_demux_src8_valid;                                                                      // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
+	wire  [120:0] cmd_demux_src8_data;                                                                       // cmd_demux:src8_data -> cmd_mux_008:sink0_data
+	wire          cmd_demux_src8_ready;                                                                      // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
+	wire   [20:0] cmd_demux_src8_channel;                                                                    // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
+	wire          cmd_demux_src8_startofpacket;                                                              // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
+	wire          cmd_demux_src8_endofpacket;                                                                // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
+	wire          cmd_demux_src9_valid;                                                                      // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
+	wire  [120:0] cmd_demux_src9_data;                                                                       // cmd_demux:src9_data -> cmd_mux_009:sink0_data
+	wire          cmd_demux_src9_ready;                                                                      // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
+	wire   [20:0] cmd_demux_src9_channel;                                                                    // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
+	wire          cmd_demux_src9_startofpacket;                                                              // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
+	wire          cmd_demux_src9_endofpacket;                                                                // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
+	wire          cmd_demux_src10_valid;                                                                     // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
+	wire  [120:0] cmd_demux_src10_data;                                                                      // cmd_demux:src10_data -> cmd_mux_010:sink0_data
+	wire          cmd_demux_src10_ready;                                                                     // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
+	wire   [20:0] cmd_demux_src10_channel;                                                                   // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
+	wire          cmd_demux_src10_startofpacket;                                                             // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
+	wire          cmd_demux_src10_endofpacket;                                                               // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
+	wire          cmd_demux_src11_valid;                                                                     // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
+	wire  [120:0] cmd_demux_src11_data;                                                                      // cmd_demux:src11_data -> cmd_mux_011:sink0_data
+	wire          cmd_demux_src11_ready;                                                                     // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
+	wire   [20:0] cmd_demux_src11_channel;                                                                   // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
+	wire          cmd_demux_src11_startofpacket;                                                             // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
+	wire          cmd_demux_src11_endofpacket;                                                               // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
+	wire          cmd_demux_src12_valid;                                                                     // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
+	wire  [120:0] cmd_demux_src12_data;                                                                      // cmd_demux:src12_data -> cmd_mux_012:sink0_data
+	wire          cmd_demux_src12_ready;                                                                     // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
+	wire   [20:0] cmd_demux_src12_channel;                                                                   // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
+	wire          cmd_demux_src12_startofpacket;                                                             // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
+	wire          cmd_demux_src12_endofpacket;                                                               // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
+	wire          cmd_demux_src13_valid;                                                                     // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
+	wire  [120:0] cmd_demux_src13_data;                                                                      // cmd_demux:src13_data -> cmd_mux_013:sink0_data
+	wire          cmd_demux_src13_ready;                                                                     // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
+	wire   [20:0] cmd_demux_src13_channel;                                                                   // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
+	wire          cmd_demux_src13_startofpacket;                                                             // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
+	wire          cmd_demux_src13_endofpacket;                                                               // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
+	wire          cmd_demux_src14_valid;                                                                     // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
+	wire  [120:0] cmd_demux_src14_data;                                                                      // cmd_demux:src14_data -> cmd_mux_014:sink0_data
+	wire          cmd_demux_src14_ready;                                                                     // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
+	wire   [20:0] cmd_demux_src14_channel;                                                                   // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
+	wire          cmd_demux_src14_startofpacket;                                                             // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
+	wire          cmd_demux_src14_endofpacket;                                                               // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
+	wire          cmd_demux_src15_valid;                                                                     // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
+	wire  [120:0] cmd_demux_src15_data;                                                                      // cmd_demux:src15_data -> cmd_mux_015:sink0_data
+	wire          cmd_demux_src15_ready;                                                                     // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
+	wire   [20:0] cmd_demux_src15_channel;                                                                   // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
+	wire          cmd_demux_src15_startofpacket;                                                             // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
+	wire          cmd_demux_src15_endofpacket;                                                               // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
+	wire          cmd_demux_src16_valid;                                                                     // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
+	wire  [120:0] cmd_demux_src16_data;                                                                      // cmd_demux:src16_data -> cmd_mux_016:sink0_data
+	wire          cmd_demux_src16_ready;                                                                     // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
+	wire   [20:0] cmd_demux_src16_channel;                                                                   // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
+	wire          cmd_demux_src16_startofpacket;                                                             // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
+	wire          cmd_demux_src16_endofpacket;                                                               // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
+	wire          cmd_demux_src17_valid;                                                                     // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
+	wire  [120:0] cmd_demux_src17_data;                                                                      // cmd_demux:src17_data -> cmd_mux_017:sink0_data
+	wire          cmd_demux_src17_ready;                                                                     // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
+	wire   [20:0] cmd_demux_src17_channel;                                                                   // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
+	wire          cmd_demux_src17_startofpacket;                                                             // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
+	wire          cmd_demux_src17_endofpacket;                                                               // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
+	wire          cmd_demux_src18_valid;                                                                     // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
+	wire  [120:0] cmd_demux_src18_data;                                                                      // cmd_demux:src18_data -> cmd_mux_018:sink0_data
+	wire          cmd_demux_src18_ready;                                                                     // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
+	wire   [20:0] cmd_demux_src18_channel;                                                                   // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
+	wire          cmd_demux_src18_startofpacket;                                                             // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
+	wire          cmd_demux_src18_endofpacket;                                                               // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
+	wire          cmd_demux_src19_valid;                                                                     // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
+	wire  [120:0] cmd_demux_src19_data;                                                                      // cmd_demux:src19_data -> cmd_mux_019:sink0_data
+	wire          cmd_demux_src19_ready;                                                                     // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
+	wire   [20:0] cmd_demux_src19_channel;                                                                   // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
+	wire          cmd_demux_src19_startofpacket;                                                             // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
+	wire          cmd_demux_src19_endofpacket;                                                               // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
+	wire          cmd_demux_src20_valid;                                                                     // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
+	wire  [120:0] cmd_demux_src20_data;                                                                      // cmd_demux:src20_data -> cmd_mux_020:sink0_data
+	wire          cmd_demux_src20_ready;                                                                     // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
+	wire   [20:0] cmd_demux_src20_channel;                                                                   // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
+	wire          cmd_demux_src20_startofpacket;                                                             // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
+	wire          cmd_demux_src20_endofpacket;                                                               // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
+	wire          cmd_demux_001_src2_valid;                                                                  // cmd_demux_001:src2_valid -> cmd_mux_010:sink1_valid
+	wire  [120:0] cmd_demux_001_src2_data;                                                                   // cmd_demux_001:src2_data -> cmd_mux_010:sink1_data
+	wire          cmd_demux_001_src2_ready;                                                                  // cmd_mux_010:sink1_ready -> cmd_demux_001:src2_ready
+	wire   [20:0] cmd_demux_001_src2_channel;                                                                // cmd_demux_001:src2_channel -> cmd_mux_010:sink1_channel
+	wire          cmd_demux_001_src2_startofpacket;                                                          // cmd_demux_001:src2_startofpacket -> cmd_mux_010:sink1_startofpacket
+	wire          cmd_demux_001_src2_endofpacket;                                                            // cmd_demux_001:src2_endofpacket -> cmd_mux_010:sink1_endofpacket
+	wire          cmd_demux_001_src3_valid;                                                                  // cmd_demux_001:src3_valid -> cmd_mux_011:sink1_valid
+	wire  [120:0] cmd_demux_001_src3_data;                                                                   // cmd_demux_001:src3_data -> cmd_mux_011:sink1_data
+	wire          cmd_demux_001_src3_ready;                                                                  // cmd_mux_011:sink1_ready -> cmd_demux_001:src3_ready
+	wire   [20:0] cmd_demux_001_src3_channel;                                                                // cmd_demux_001:src3_channel -> cmd_mux_011:sink1_channel
+	wire          cmd_demux_001_src3_startofpacket;                                                          // cmd_demux_001:src3_startofpacket -> cmd_mux_011:sink1_startofpacket
+	wire          cmd_demux_001_src3_endofpacket;                                                            // cmd_demux_001:src3_endofpacket -> cmd_mux_011:sink1_endofpacket
+	wire          cmd_demux_004_src0_valid;                                                                  // cmd_demux_004:src0_valid -> cmd_mux_014:sink1_valid
+	wire  [120:0] cmd_demux_004_src0_data;                                                                   // cmd_demux_004:src0_data -> cmd_mux_014:sink1_data
+	wire          cmd_demux_004_src0_ready;                                                                  // cmd_mux_014:sink1_ready -> cmd_demux_004:src0_ready
+	wire   [20:0] cmd_demux_004_src0_channel;                                                                // cmd_demux_004:src0_channel -> cmd_mux_014:sink1_channel
+	wire          cmd_demux_004_src0_startofpacket;                                                          // cmd_demux_004:src0_startofpacket -> cmd_mux_014:sink1_startofpacket
+	wire          cmd_demux_004_src0_endofpacket;                                                            // cmd_demux_004:src0_endofpacket -> cmd_mux_014:sink1_endofpacket
+	wire          cmd_demux_005_src0_valid;                                                                  // cmd_demux_005:src0_valid -> cmd_mux_014:sink2_valid
+	wire  [120:0] cmd_demux_005_src0_data;                                                                   // cmd_demux_005:src0_data -> cmd_mux_014:sink2_data
+	wire          cmd_demux_005_src0_ready;                                                                  // cmd_mux_014:sink2_ready -> cmd_demux_005:src0_ready
+	wire   [20:0] cmd_demux_005_src0_channel;                                                                // cmd_demux_005:src0_channel -> cmd_mux_014:sink2_channel
+	wire          cmd_demux_005_src0_startofpacket;                                                          // cmd_demux_005:src0_startofpacket -> cmd_mux_014:sink2_startofpacket
+	wire          cmd_demux_005_src0_endofpacket;                                                            // cmd_demux_005:src0_endofpacket -> cmd_mux_014:sink2_endofpacket
+	wire          cmd_demux_006_src0_valid;                                                                  // cmd_demux_006:src0_valid -> cmd_mux_014:sink3_valid
+	wire  [120:0] cmd_demux_006_src0_data;                                                                   // cmd_demux_006:src0_data -> cmd_mux_014:sink3_data
+	wire          cmd_demux_006_src0_ready;                                                                  // cmd_mux_014:sink3_ready -> cmd_demux_006:src0_ready
+	wire   [20:0] cmd_demux_006_src0_channel;                                                                // cmd_demux_006:src0_channel -> cmd_mux_014:sink3_channel
+	wire          cmd_demux_006_src0_startofpacket;                                                          // cmd_demux_006:src0_startofpacket -> cmd_mux_014:sink3_startofpacket
+	wire          cmd_demux_006_src0_endofpacket;                                                            // cmd_demux_006:src0_endofpacket -> cmd_mux_014:sink3_endofpacket
+	wire          cmd_demux_007_src0_valid;                                                                  // cmd_demux_007:src0_valid -> cmd_mux_014:sink4_valid
+	wire  [120:0] cmd_demux_007_src0_data;                                                                   // cmd_demux_007:src0_data -> cmd_mux_014:sink4_data
+	wire          cmd_demux_007_src0_ready;                                                                  // cmd_mux_014:sink4_ready -> cmd_demux_007:src0_ready
+	wire   [20:0] cmd_demux_007_src0_channel;                                                                // cmd_demux_007:src0_channel -> cmd_mux_014:sink4_channel
+	wire          cmd_demux_007_src0_startofpacket;                                                          // cmd_demux_007:src0_startofpacket -> cmd_mux_014:sink4_startofpacket
+	wire          cmd_demux_007_src0_endofpacket;                                                            // cmd_demux_007:src0_endofpacket -> cmd_mux_014:sink4_endofpacket
+	wire          rsp_demux_003_src0_valid;                                                                  // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
+	wire  [120:0] rsp_demux_003_src0_data;                                                                   // rsp_demux_003:src0_data -> rsp_mux:sink3_data
+	wire          rsp_demux_003_src0_ready;                                                                  // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
+	wire   [20:0] rsp_demux_003_src0_channel;                                                                // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
+	wire          rsp_demux_003_src0_startofpacket;                                                          // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
+	wire          rsp_demux_003_src0_endofpacket;                                                            // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
+	wire          rsp_demux_004_src0_valid;                                                                  // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
+	wire  [120:0] rsp_demux_004_src0_data;                                                                   // rsp_demux_004:src0_data -> rsp_mux:sink4_data
+	wire          rsp_demux_004_src0_ready;                                                                  // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
+	wire   [20:0] rsp_demux_004_src0_channel;                                                                // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
+	wire          rsp_demux_004_src0_startofpacket;                                                          // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
+	wire          rsp_demux_004_src0_endofpacket;                                                            // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
+	wire          rsp_demux_005_src0_valid;                                                                  // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
+	wire  [120:0] rsp_demux_005_src0_data;                                                                   // rsp_demux_005:src0_data -> rsp_mux:sink5_data
+	wire          rsp_demux_005_src0_ready;                                                                  // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
+	wire   [20:0] rsp_demux_005_src0_channel;                                                                // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
+	wire          rsp_demux_005_src0_startofpacket;                                                          // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
+	wire          rsp_demux_005_src0_endofpacket;                                                            // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
+	wire          rsp_demux_006_src0_valid;                                                                  // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
+	wire  [120:0] rsp_demux_006_src0_data;                                                                   // rsp_demux_006:src0_data -> rsp_mux:sink6_data
+	wire          rsp_demux_006_src0_ready;                                                                  // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
+	wire   [20:0] rsp_demux_006_src0_channel;                                                                // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
+	wire          rsp_demux_006_src0_startofpacket;                                                          // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
+	wire          rsp_demux_006_src0_endofpacket;                                                            // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
+	wire          rsp_demux_007_src0_valid;                                                                  // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
+	wire  [120:0] rsp_demux_007_src0_data;                                                                   // rsp_demux_007:src0_data -> rsp_mux:sink7_data
+	wire          rsp_demux_007_src0_ready;                                                                  // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
+	wire   [20:0] rsp_demux_007_src0_channel;                                                                // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
+	wire          rsp_demux_007_src0_startofpacket;                                                          // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
+	wire          rsp_demux_007_src0_endofpacket;                                                            // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
+	wire          rsp_demux_008_src0_valid;                                                                  // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
+	wire  [120:0] rsp_demux_008_src0_data;                                                                   // rsp_demux_008:src0_data -> rsp_mux:sink8_data
+	wire          rsp_demux_008_src0_ready;                                                                  // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
+	wire   [20:0] rsp_demux_008_src0_channel;                                                                // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
+	wire          rsp_demux_008_src0_startofpacket;                                                          // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
+	wire          rsp_demux_008_src0_endofpacket;                                                            // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
+	wire          rsp_demux_009_src0_valid;                                                                  // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
+	wire  [120:0] rsp_demux_009_src0_data;                                                                   // rsp_demux_009:src0_data -> rsp_mux:sink9_data
+	wire          rsp_demux_009_src0_ready;                                                                  // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
+	wire   [20:0] rsp_demux_009_src0_channel;                                                                // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
+	wire          rsp_demux_009_src0_startofpacket;                                                          // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
+	wire          rsp_demux_009_src0_endofpacket;                                                            // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
+	wire          rsp_demux_010_src0_valid;                                                                  // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
+	wire  [120:0] rsp_demux_010_src0_data;                                                                   // rsp_demux_010:src0_data -> rsp_mux:sink10_data
+	wire          rsp_demux_010_src0_ready;                                                                  // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
+	wire   [20:0] rsp_demux_010_src0_channel;                                                                // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
+	wire          rsp_demux_010_src0_startofpacket;                                                          // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
+	wire          rsp_demux_010_src0_endofpacket;                                                            // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
+	wire          rsp_demux_010_src1_valid;                                                                  // rsp_demux_010:src1_valid -> rsp_mux_001:sink2_valid
+	wire  [120:0] rsp_demux_010_src1_data;                                                                   // rsp_demux_010:src1_data -> rsp_mux_001:sink2_data
+	wire          rsp_demux_010_src1_ready;                                                                  // rsp_mux_001:sink2_ready -> rsp_demux_010:src1_ready
+	wire   [20:0] rsp_demux_010_src1_channel;                                                                // rsp_demux_010:src1_channel -> rsp_mux_001:sink2_channel
+	wire          rsp_demux_010_src1_startofpacket;                                                          // rsp_demux_010:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
+	wire          rsp_demux_010_src1_endofpacket;                                                            // rsp_demux_010:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
+	wire          rsp_demux_011_src0_valid;                                                                  // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
+	wire  [120:0] rsp_demux_011_src0_data;                                                                   // rsp_demux_011:src0_data -> rsp_mux:sink11_data
+	wire          rsp_demux_011_src0_ready;                                                                  // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
+	wire   [20:0] rsp_demux_011_src0_channel;                                                                // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
+	wire          rsp_demux_011_src0_startofpacket;                                                          // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
+	wire          rsp_demux_011_src0_endofpacket;                                                            // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
+	wire          rsp_demux_011_src1_valid;                                                                  // rsp_demux_011:src1_valid -> rsp_mux_001:sink3_valid
+	wire  [120:0] rsp_demux_011_src1_data;                                                                   // rsp_demux_011:src1_data -> rsp_mux_001:sink3_data
+	wire          rsp_demux_011_src1_ready;                                                                  // rsp_mux_001:sink3_ready -> rsp_demux_011:src1_ready
+	wire   [20:0] rsp_demux_011_src1_channel;                                                                // rsp_demux_011:src1_channel -> rsp_mux_001:sink3_channel
+	wire          rsp_demux_011_src1_startofpacket;                                                          // rsp_demux_011:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
+	wire          rsp_demux_011_src1_endofpacket;                                                            // rsp_demux_011:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
+	wire          rsp_demux_012_src0_valid;                                                                  // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
+	wire  [120:0] rsp_demux_012_src0_data;                                                                   // rsp_demux_012:src0_data -> rsp_mux:sink12_data
+	wire          rsp_demux_012_src0_ready;                                                                  // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
+	wire   [20:0] rsp_demux_012_src0_channel;                                                                // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
+	wire          rsp_demux_012_src0_startofpacket;                                                          // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
+	wire          rsp_demux_012_src0_endofpacket;                                                            // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
+	wire          rsp_demux_013_src0_valid;                                                                  // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
+	wire  [120:0] rsp_demux_013_src0_data;                                                                   // rsp_demux_013:src0_data -> rsp_mux:sink13_data
+	wire          rsp_demux_013_src0_ready;                                                                  // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
+	wire   [20:0] rsp_demux_013_src0_channel;                                                                // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
+	wire          rsp_demux_013_src0_startofpacket;                                                          // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
+	wire          rsp_demux_013_src0_endofpacket;                                                            // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
+	wire          rsp_demux_014_src0_valid;                                                                  // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
+	wire  [120:0] rsp_demux_014_src0_data;                                                                   // rsp_demux_014:src0_data -> rsp_mux:sink14_data
+	wire          rsp_demux_014_src0_ready;                                                                  // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
+	wire   [20:0] rsp_demux_014_src0_channel;                                                                // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
+	wire          rsp_demux_014_src0_startofpacket;                                                          // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
+	wire          rsp_demux_014_src0_endofpacket;                                                            // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
+	wire          rsp_demux_014_src1_valid;                                                                  // rsp_demux_014:src1_valid -> rsp_mux_004:sink0_valid
+	wire  [120:0] rsp_demux_014_src1_data;                                                                   // rsp_demux_014:src1_data -> rsp_mux_004:sink0_data
+	wire          rsp_demux_014_src1_ready;                                                                  // rsp_mux_004:sink0_ready -> rsp_demux_014:src1_ready
+	wire   [20:0] rsp_demux_014_src1_channel;                                                                // rsp_demux_014:src1_channel -> rsp_mux_004:sink0_channel
+	wire          rsp_demux_014_src1_startofpacket;                                                          // rsp_demux_014:src1_startofpacket -> rsp_mux_004:sink0_startofpacket
+	wire          rsp_demux_014_src1_endofpacket;                                                            // rsp_demux_014:src1_endofpacket -> rsp_mux_004:sink0_endofpacket
+	wire          rsp_demux_014_src2_valid;                                                                  // rsp_demux_014:src2_valid -> rsp_mux_005:sink0_valid
+	wire  [120:0] rsp_demux_014_src2_data;                                                                   // rsp_demux_014:src2_data -> rsp_mux_005:sink0_data
+	wire          rsp_demux_014_src2_ready;                                                                  // rsp_mux_005:sink0_ready -> rsp_demux_014:src2_ready
+	wire   [20:0] rsp_demux_014_src2_channel;                                                                // rsp_demux_014:src2_channel -> rsp_mux_005:sink0_channel
+	wire          rsp_demux_014_src2_startofpacket;                                                          // rsp_demux_014:src2_startofpacket -> rsp_mux_005:sink0_startofpacket
+	wire          rsp_demux_014_src2_endofpacket;                                                            // rsp_demux_014:src2_endofpacket -> rsp_mux_005:sink0_endofpacket
+	wire          rsp_demux_014_src3_valid;                                                                  // rsp_demux_014:src3_valid -> rsp_mux_006:sink0_valid
+	wire  [120:0] rsp_demux_014_src3_data;                                                                   // rsp_demux_014:src3_data -> rsp_mux_006:sink0_data
+	wire          rsp_demux_014_src3_ready;                                                                  // rsp_mux_006:sink0_ready -> rsp_demux_014:src3_ready
+	wire   [20:0] rsp_demux_014_src3_channel;                                                                // rsp_demux_014:src3_channel -> rsp_mux_006:sink0_channel
+	wire          rsp_demux_014_src3_startofpacket;                                                          // rsp_demux_014:src3_startofpacket -> rsp_mux_006:sink0_startofpacket
+	wire          rsp_demux_014_src3_endofpacket;                                                            // rsp_demux_014:src3_endofpacket -> rsp_mux_006:sink0_endofpacket
+	wire          rsp_demux_014_src4_valid;                                                                  // rsp_demux_014:src4_valid -> rsp_mux_007:sink0_valid
+	wire  [120:0] rsp_demux_014_src4_data;                                                                   // rsp_demux_014:src4_data -> rsp_mux_007:sink0_data
+	wire          rsp_demux_014_src4_ready;                                                                  // rsp_mux_007:sink0_ready -> rsp_demux_014:src4_ready
+	wire   [20:0] rsp_demux_014_src4_channel;                                                                // rsp_demux_014:src4_channel -> rsp_mux_007:sink0_channel
+	wire          rsp_demux_014_src4_startofpacket;                                                          // rsp_demux_014:src4_startofpacket -> rsp_mux_007:sink0_startofpacket
+	wire          rsp_demux_014_src4_endofpacket;                                                            // rsp_demux_014:src4_endofpacket -> rsp_mux_007:sink0_endofpacket
+	wire          rsp_demux_015_src0_valid;                                                                  // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
+	wire  [120:0] rsp_demux_015_src0_data;                                                                   // rsp_demux_015:src0_data -> rsp_mux:sink15_data
+	wire          rsp_demux_015_src0_ready;                                                                  // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
+	wire   [20:0] rsp_demux_015_src0_channel;                                                                // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
+	wire          rsp_demux_015_src0_startofpacket;                                                          // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
+	wire          rsp_demux_015_src0_endofpacket;                                                            // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
+	wire          rsp_demux_016_src0_valid;                                                                  // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
+	wire  [120:0] rsp_demux_016_src0_data;                                                                   // rsp_demux_016:src0_data -> rsp_mux:sink16_data
+	wire          rsp_demux_016_src0_ready;                                                                  // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
+	wire   [20:0] rsp_demux_016_src0_channel;                                                                // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
+	wire          rsp_demux_016_src0_startofpacket;                                                          // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
+	wire          rsp_demux_016_src0_endofpacket;                                                            // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
+	wire          rsp_demux_017_src0_valid;                                                                  // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
+	wire  [120:0] rsp_demux_017_src0_data;                                                                   // rsp_demux_017:src0_data -> rsp_mux:sink17_data
+	wire          rsp_demux_017_src0_ready;                                                                  // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
+	wire   [20:0] rsp_demux_017_src0_channel;                                                                // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
+	wire          rsp_demux_017_src0_startofpacket;                                                          // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
+	wire          rsp_demux_017_src0_endofpacket;                                                            // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
+	wire          rsp_demux_018_src0_valid;                                                                  // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
+	wire  [120:0] rsp_demux_018_src0_data;                                                                   // rsp_demux_018:src0_data -> rsp_mux:sink18_data
+	wire          rsp_demux_018_src0_ready;                                                                  // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
+	wire   [20:0] rsp_demux_018_src0_channel;                                                                // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
+	wire          rsp_demux_018_src0_startofpacket;                                                          // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
+	wire          rsp_demux_018_src0_endofpacket;                                                            // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
+	wire          rsp_demux_019_src0_valid;                                                                  // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
+	wire  [120:0] rsp_demux_019_src0_data;                                                                   // rsp_demux_019:src0_data -> rsp_mux:sink19_data
+	wire          rsp_demux_019_src0_ready;                                                                  // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
+	wire   [20:0] rsp_demux_019_src0_channel;                                                                // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
+	wire          rsp_demux_019_src0_startofpacket;                                                          // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
+	wire          rsp_demux_019_src0_endofpacket;                                                            // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
+	wire          rsp_demux_020_src0_valid;                                                                  // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
+	wire  [120:0] rsp_demux_020_src0_data;                                                                   // rsp_demux_020:src0_data -> rsp_mux:sink20_data
+	wire          rsp_demux_020_src0_ready;                                                                  // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
+	wire   [20:0] rsp_demux_020_src0_channel;                                                                // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
+	wire          rsp_demux_020_src0_startofpacket;                                                          // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
+	wire          rsp_demux_020_src0_endofpacket;                                                            // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
+	wire          router_028_src_valid;                                                                      // router_028:src_valid -> calibration_ram_s1_rsp_width_adapter:in_valid
+	wire  [102:0] router_028_src_data;                                                                       // router_028:src_data -> calibration_ram_s1_rsp_width_adapter:in_data
+	wire          router_028_src_ready;                                                                      // calibration_ram_s1_rsp_width_adapter:in_ready -> router_028:src_ready
+	wire   [20:0] router_028_src_channel;                                                                    // router_028:src_channel -> calibration_ram_s1_rsp_width_adapter:in_channel
+	wire          router_028_src_startofpacket;                                                              // router_028:src_startofpacket -> calibration_ram_s1_rsp_width_adapter:in_startofpacket
+	wire          router_028_src_endofpacket;                                                                // router_028:src_endofpacket -> calibration_ram_s1_rsp_width_adapter:in_endofpacket
+	wire          calibration_ram_s1_rsp_width_adapter_src_valid;                                            // calibration_ram_s1_rsp_width_adapter:out_valid -> rsp_demux_020:sink_valid
+	wire  [120:0] calibration_ram_s1_rsp_width_adapter_src_data;                                             // calibration_ram_s1_rsp_width_adapter:out_data -> rsp_demux_020:sink_data
+	wire          calibration_ram_s1_rsp_width_adapter_src_ready;                                            // rsp_demux_020:sink_ready -> calibration_ram_s1_rsp_width_adapter:out_ready
+	wire   [20:0] calibration_ram_s1_rsp_width_adapter_src_channel;                                          // calibration_ram_s1_rsp_width_adapter:out_channel -> rsp_demux_020:sink_channel
+	wire          calibration_ram_s1_rsp_width_adapter_src_startofpacket;                                    // calibration_ram_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_020:sink_startofpacket
+	wire          calibration_ram_s1_rsp_width_adapter_src_endofpacket;                                      // calibration_ram_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_020:sink_endofpacket
+	wire          cmd_mux_020_src_valid;                                                                     // cmd_mux_020:src_valid -> calibration_ram_s1_cmd_width_adapter:in_valid
+	wire  [120:0] cmd_mux_020_src_data;                                                                      // cmd_mux_020:src_data -> calibration_ram_s1_cmd_width_adapter:in_data
+	wire          cmd_mux_020_src_ready;                                                                     // calibration_ram_s1_cmd_width_adapter:in_ready -> cmd_mux_020:src_ready
+	wire   [20:0] cmd_mux_020_src_channel;                                                                   // cmd_mux_020:src_channel -> calibration_ram_s1_cmd_width_adapter:in_channel
+	wire          cmd_mux_020_src_startofpacket;                                                             // cmd_mux_020:src_startofpacket -> calibration_ram_s1_cmd_width_adapter:in_startofpacket
+	wire          cmd_mux_020_src_endofpacket;                                                               // cmd_mux_020:src_endofpacket -> calibration_ram_s1_cmd_width_adapter:in_endofpacket
+	wire          calibration_ram_s1_cmd_width_adapter_src_valid;                                            // calibration_ram_s1_cmd_width_adapter:out_valid -> calibration_ram_s1_burst_adapter:sink0_valid
+	wire  [102:0] calibration_ram_s1_cmd_width_adapter_src_data;                                             // calibration_ram_s1_cmd_width_adapter:out_data -> calibration_ram_s1_burst_adapter:sink0_data
+	wire          calibration_ram_s1_cmd_width_adapter_src_ready;                                            // calibration_ram_s1_burst_adapter:sink0_ready -> calibration_ram_s1_cmd_width_adapter:out_ready
+	wire   [20:0] calibration_ram_s1_cmd_width_adapter_src_channel;                                          // calibration_ram_s1_cmd_width_adapter:out_channel -> calibration_ram_s1_burst_adapter:sink0_channel
+	wire          calibration_ram_s1_cmd_width_adapter_src_startofpacket;                                    // calibration_ram_s1_cmd_width_adapter:out_startofpacket -> calibration_ram_s1_burst_adapter:sink0_startofpacket
+	wire          calibration_ram_s1_cmd_width_adapter_src_endofpacket;                                      // calibration_ram_s1_cmd_width_adapter:out_endofpacket -> calibration_ram_s1_burst_adapter:sink0_endofpacket
+	wire          cmd_demux_src0_valid;                                                                      // cmd_demux:src0_valid -> crosser:in_valid
+	wire  [120:0] cmd_demux_src0_data;                                                                       // cmd_demux:src0_data -> crosser:in_data
+	wire          cmd_demux_src0_ready;                                                                      // crosser:in_ready -> cmd_demux:src0_ready
+	wire   [20:0] cmd_demux_src0_channel;                                                                    // cmd_demux:src0_channel -> crosser:in_channel
+	wire          cmd_demux_src0_startofpacket;                                                              // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
+	wire          cmd_demux_src0_endofpacket;                                                                // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
+	wire          crosser_out_valid;                                                                         // crosser:out_valid -> cmd_mux:sink0_valid
+	wire  [120:0] crosser_out_data;                                                                          // crosser:out_data -> cmd_mux:sink0_data
+	wire          crosser_out_ready;                                                                         // cmd_mux:sink0_ready -> crosser:out_ready
+	wire   [20:0] crosser_out_channel;                                                                       // crosser:out_channel -> cmd_mux:sink0_channel
+	wire          crosser_out_startofpacket;                                                                 // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
+	wire          crosser_out_endofpacket;                                                                   // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
+	wire          cmd_demux_src1_valid;                                                                      // cmd_demux:src1_valid -> crosser_001:in_valid
+	wire  [120:0] cmd_demux_src1_data;                                                                       // cmd_demux:src1_data -> crosser_001:in_data
+	wire          cmd_demux_src1_ready;                                                                      // crosser_001:in_ready -> cmd_demux:src1_ready
+	wire   [20:0] cmd_demux_src1_channel;                                                                    // cmd_demux:src1_channel -> crosser_001:in_channel
+	wire          cmd_demux_src1_startofpacket;                                                              // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
+	wire          cmd_demux_src1_endofpacket;                                                                // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
+	wire          crosser_001_out_valid;                                                                     // crosser_001:out_valid -> cmd_mux_001:sink0_valid
+	wire  [120:0] crosser_001_out_data;                                                                      // crosser_001:out_data -> cmd_mux_001:sink0_data
+	wire          crosser_001_out_ready;                                                                     // cmd_mux_001:sink0_ready -> crosser_001:out_ready
+	wire   [20:0] crosser_001_out_channel;                                                                   // crosser_001:out_channel -> cmd_mux_001:sink0_channel
+	wire          crosser_001_out_startofpacket;                                                             // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
+	wire          crosser_001_out_endofpacket;                                                               // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
+	wire          cmd_demux_src2_valid;                                                                      // cmd_demux:src2_valid -> crosser_002:in_valid
+	wire  [120:0] cmd_demux_src2_data;                                                                       // cmd_demux:src2_data -> crosser_002:in_data
+	wire          cmd_demux_src2_ready;                                                                      // crosser_002:in_ready -> cmd_demux:src2_ready
+	wire   [20:0] cmd_demux_src2_channel;                                                                    // cmd_demux:src2_channel -> crosser_002:in_channel
+	wire          cmd_demux_src2_startofpacket;                                                              // cmd_demux:src2_startofpacket -> crosser_002:in_startofpacket
+	wire          cmd_demux_src2_endofpacket;                                                                // cmd_demux:src2_endofpacket -> crosser_002:in_endofpacket
+	wire          crosser_002_out_valid;                                                                     // crosser_002:out_valid -> cmd_mux_002:sink0_valid
+	wire  [120:0] crosser_002_out_data;                                                                      // crosser_002:out_data -> cmd_mux_002:sink0_data
+	wire          crosser_002_out_ready;                                                                     // cmd_mux_002:sink0_ready -> crosser_002:out_ready
+	wire   [20:0] crosser_002_out_channel;                                                                   // crosser_002:out_channel -> cmd_mux_002:sink0_channel
+	wire          crosser_002_out_startofpacket;                                                             // crosser_002:out_startofpacket -> cmd_mux_002:sink0_startofpacket
+	wire          crosser_002_out_endofpacket;                                                               // crosser_002:out_endofpacket -> cmd_mux_002:sink0_endofpacket
+	wire          cmd_demux_001_src0_valid;                                                                  // cmd_demux_001:src0_valid -> crosser_003:in_valid
+	wire  [120:0] cmd_demux_001_src0_data;                                                                   // cmd_demux_001:src0_data -> crosser_003:in_data
+	wire          cmd_demux_001_src0_ready;                                                                  // crosser_003:in_ready -> cmd_demux_001:src0_ready
+	wire   [20:0] cmd_demux_001_src0_channel;                                                                // cmd_demux_001:src0_channel -> crosser_003:in_channel
+	wire          cmd_demux_001_src0_startofpacket;                                                          // cmd_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
+	wire          cmd_demux_001_src0_endofpacket;                                                            // cmd_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
+	wire          crosser_003_out_valid;                                                                     // crosser_003:out_valid -> cmd_mux:sink1_valid
+	wire  [120:0] crosser_003_out_data;                                                                      // crosser_003:out_data -> cmd_mux:sink1_data
+	wire          crosser_003_out_ready;                                                                     // cmd_mux:sink1_ready -> crosser_003:out_ready
+	wire   [20:0] crosser_003_out_channel;                                                                   // crosser_003:out_channel -> cmd_mux:sink1_channel
+	wire          crosser_003_out_startofpacket;                                                             // crosser_003:out_startofpacket -> cmd_mux:sink1_startofpacket
+	wire          crosser_003_out_endofpacket;                                                               // crosser_003:out_endofpacket -> cmd_mux:sink1_endofpacket
+	wire          cmd_demux_001_src1_valid;                                                                  // cmd_demux_001:src1_valid -> crosser_004:in_valid
+	wire  [120:0] cmd_demux_001_src1_data;                                                                   // cmd_demux_001:src1_data -> crosser_004:in_data
+	wire          cmd_demux_001_src1_ready;                                                                  // crosser_004:in_ready -> cmd_demux_001:src1_ready
+	wire   [20:0] cmd_demux_001_src1_channel;                                                                // cmd_demux_001:src1_channel -> crosser_004:in_channel
+	wire          cmd_demux_001_src1_startofpacket;                                                          // cmd_demux_001:src1_startofpacket -> crosser_004:in_startofpacket
+	wire          cmd_demux_001_src1_endofpacket;                                                            // cmd_demux_001:src1_endofpacket -> crosser_004:in_endofpacket
+	wire          crosser_004_out_valid;                                                                     // crosser_004:out_valid -> cmd_mux_002:sink1_valid
+	wire  [120:0] crosser_004_out_data;                                                                      // crosser_004:out_data -> cmd_mux_002:sink1_data
+	wire          crosser_004_out_ready;                                                                     // cmd_mux_002:sink1_ready -> crosser_004:out_ready
+	wire   [20:0] crosser_004_out_channel;                                                                   // crosser_004:out_channel -> cmd_mux_002:sink1_channel
+	wire          crosser_004_out_startofpacket;                                                             // crosser_004:out_startofpacket -> cmd_mux_002:sink1_startofpacket
+	wire          crosser_004_out_endofpacket;                                                               // crosser_004:out_endofpacket -> cmd_mux_002:sink1_endofpacket
+	wire          cmd_demux_002_src0_valid;                                                                  // cmd_demux_002:src0_valid -> crosser_005:in_valid
+	wire  [120:0] cmd_demux_002_src0_data;                                                                   // cmd_demux_002:src0_data -> crosser_005:in_data
+	wire          cmd_demux_002_src0_ready;                                                                  // crosser_005:in_ready -> cmd_demux_002:src0_ready
+	wire   [20:0] cmd_demux_002_src0_channel;                                                                // cmd_demux_002:src0_channel -> crosser_005:in_channel
+	wire          cmd_demux_002_src0_startofpacket;                                                          // cmd_demux_002:src0_startofpacket -> crosser_005:in_startofpacket
+	wire          cmd_demux_002_src0_endofpacket;                                                            // cmd_demux_002:src0_endofpacket -> crosser_005:in_endofpacket
+	wire          crosser_005_out_valid;                                                                     // crosser_005:out_valid -> cmd_mux:sink2_valid
+	wire  [120:0] crosser_005_out_data;                                                                      // crosser_005:out_data -> cmd_mux:sink2_data
+	wire          crosser_005_out_ready;                                                                     // cmd_mux:sink2_ready -> crosser_005:out_ready
+	wire   [20:0] crosser_005_out_channel;                                                                   // crosser_005:out_channel -> cmd_mux:sink2_channel
+	wire          crosser_005_out_startofpacket;                                                             // crosser_005:out_startofpacket -> cmd_mux:sink2_startofpacket
+	wire          crosser_005_out_endofpacket;                                                               // crosser_005:out_endofpacket -> cmd_mux:sink2_endofpacket
+	wire          cmd_demux_003_src0_valid;                                                                  // cmd_demux_003:src0_valid -> crosser_006:in_valid
+	wire  [120:0] cmd_demux_003_src0_data;                                                                   // cmd_demux_003:src0_data -> crosser_006:in_data
+	wire          cmd_demux_003_src0_ready;                                                                  // crosser_006:in_ready -> cmd_demux_003:src0_ready
+	wire   [20:0] cmd_demux_003_src0_channel;                                                                // cmd_demux_003:src0_channel -> crosser_006:in_channel
+	wire          cmd_demux_003_src0_startofpacket;                                                          // cmd_demux_003:src0_startofpacket -> crosser_006:in_startofpacket
+	wire          cmd_demux_003_src0_endofpacket;                                                            // cmd_demux_003:src0_endofpacket -> crosser_006:in_endofpacket
+	wire          crosser_006_out_valid;                                                                     // crosser_006:out_valid -> cmd_mux:sink3_valid
+	wire  [120:0] crosser_006_out_data;                                                                      // crosser_006:out_data -> cmd_mux:sink3_data
+	wire          crosser_006_out_ready;                                                                     // cmd_mux:sink3_ready -> crosser_006:out_ready
+	wire   [20:0] crosser_006_out_channel;                                                                   // crosser_006:out_channel -> cmd_mux:sink3_channel
+	wire          crosser_006_out_startofpacket;                                                             // crosser_006:out_startofpacket -> cmd_mux:sink3_startofpacket
+	wire          crosser_006_out_endofpacket;                                                               // crosser_006:out_endofpacket -> cmd_mux:sink3_endofpacket
+	wire          rsp_demux_src0_valid;                                                                      // rsp_demux:src0_valid -> crosser_007:in_valid
+	wire  [120:0] rsp_demux_src0_data;                                                                       // rsp_demux:src0_data -> crosser_007:in_data
+	wire          rsp_demux_src0_ready;                                                                      // crosser_007:in_ready -> rsp_demux:src0_ready
+	wire   [20:0] rsp_demux_src0_channel;                                                                    // rsp_demux:src0_channel -> crosser_007:in_channel
+	wire          rsp_demux_src0_startofpacket;                                                              // rsp_demux:src0_startofpacket -> crosser_007:in_startofpacket
+	wire          rsp_demux_src0_endofpacket;                                                                // rsp_demux:src0_endofpacket -> crosser_007:in_endofpacket
+	wire          crosser_007_out_valid;                                                                     // crosser_007:out_valid -> rsp_mux:sink0_valid
+	wire  [120:0] crosser_007_out_data;                                                                      // crosser_007:out_data -> rsp_mux:sink0_data
+	wire          crosser_007_out_ready;                                                                     // rsp_mux:sink0_ready -> crosser_007:out_ready
+	wire   [20:0] crosser_007_out_channel;                                                                   // crosser_007:out_channel -> rsp_mux:sink0_channel
+	wire          crosser_007_out_startofpacket;                                                             // crosser_007:out_startofpacket -> rsp_mux:sink0_startofpacket
+	wire          crosser_007_out_endofpacket;                                                               // crosser_007:out_endofpacket -> rsp_mux:sink0_endofpacket
+	wire          rsp_demux_src1_valid;                                                                      // rsp_demux:src1_valid -> crosser_008:in_valid
+	wire  [120:0] rsp_demux_src1_data;                                                                       // rsp_demux:src1_data -> crosser_008:in_data
+	wire          rsp_demux_src1_ready;                                                                      // crosser_008:in_ready -> rsp_demux:src1_ready
+	wire   [20:0] rsp_demux_src1_channel;                                                                    // rsp_demux:src1_channel -> crosser_008:in_channel
+	wire          rsp_demux_src1_startofpacket;                                                              // rsp_demux:src1_startofpacket -> crosser_008:in_startofpacket
+	wire          rsp_demux_src1_endofpacket;                                                                // rsp_demux:src1_endofpacket -> crosser_008:in_endofpacket
+	wire          crosser_008_out_valid;                                                                     // crosser_008:out_valid -> rsp_mux_001:sink0_valid
+	wire  [120:0] crosser_008_out_data;                                                                      // crosser_008:out_data -> rsp_mux_001:sink0_data
+	wire          crosser_008_out_ready;                                                                     // rsp_mux_001:sink0_ready -> crosser_008:out_ready
+	wire   [20:0] crosser_008_out_channel;                                                                   // crosser_008:out_channel -> rsp_mux_001:sink0_channel
+	wire          crosser_008_out_startofpacket;                                                             // crosser_008:out_startofpacket -> rsp_mux_001:sink0_startofpacket
+	wire          crosser_008_out_endofpacket;                                                               // crosser_008:out_endofpacket -> rsp_mux_001:sink0_endofpacket
+	wire          rsp_demux_src2_valid;                                                                      // rsp_demux:src2_valid -> crosser_009:in_valid
+	wire  [120:0] rsp_demux_src2_data;                                                                       // rsp_demux:src2_data -> crosser_009:in_data
+	wire          rsp_demux_src2_ready;                                                                      // crosser_009:in_ready -> rsp_demux:src2_ready
+	wire   [20:0] rsp_demux_src2_channel;                                                                    // rsp_demux:src2_channel -> crosser_009:in_channel
+	wire          rsp_demux_src2_startofpacket;                                                              // rsp_demux:src2_startofpacket -> crosser_009:in_startofpacket
+	wire          rsp_demux_src2_endofpacket;                                                                // rsp_demux:src2_endofpacket -> crosser_009:in_endofpacket
+	wire          crosser_009_out_valid;                                                                     // crosser_009:out_valid -> rsp_mux_002:sink0_valid
+	wire  [120:0] crosser_009_out_data;                                                                      // crosser_009:out_data -> rsp_mux_002:sink0_data
+	wire          crosser_009_out_ready;                                                                     // rsp_mux_002:sink0_ready -> crosser_009:out_ready
+	wire   [20:0] crosser_009_out_channel;                                                                   // crosser_009:out_channel -> rsp_mux_002:sink0_channel
+	wire          crosser_009_out_startofpacket;                                                             // crosser_009:out_startofpacket -> rsp_mux_002:sink0_startofpacket
+	wire          crosser_009_out_endofpacket;                                                               // crosser_009:out_endofpacket -> rsp_mux_002:sink0_endofpacket
+	wire          rsp_demux_src3_valid;                                                                      // rsp_demux:src3_valid -> crosser_010:in_valid
+	wire  [120:0] rsp_demux_src3_data;                                                                       // rsp_demux:src3_data -> crosser_010:in_data
+	wire          rsp_demux_src3_ready;                                                                      // crosser_010:in_ready -> rsp_demux:src3_ready
+	wire   [20:0] rsp_demux_src3_channel;                                                                    // rsp_demux:src3_channel -> crosser_010:in_channel
+	wire          rsp_demux_src3_startofpacket;                                                              // rsp_demux:src3_startofpacket -> crosser_010:in_startofpacket
+	wire          rsp_demux_src3_endofpacket;                                                                // rsp_demux:src3_endofpacket -> crosser_010:in_endofpacket
+	wire          crosser_010_out_valid;                                                                     // crosser_010:out_valid -> rsp_mux_003:sink0_valid
+	wire  [120:0] crosser_010_out_data;                                                                      // crosser_010:out_data -> rsp_mux_003:sink0_data
+	wire          crosser_010_out_ready;                                                                     // rsp_mux_003:sink0_ready -> crosser_010:out_ready
+	wire   [20:0] crosser_010_out_channel;                                                                   // crosser_010:out_channel -> rsp_mux_003:sink0_channel
+	wire          crosser_010_out_startofpacket;                                                             // crosser_010:out_startofpacket -> rsp_mux_003:sink0_startofpacket
+	wire          crosser_010_out_endofpacket;                                                               // crosser_010:out_endofpacket -> rsp_mux_003:sink0_endofpacket
+	wire          rsp_demux_001_src0_valid;                                                                  // rsp_demux_001:src0_valid -> crosser_011:in_valid
+	wire  [120:0] rsp_demux_001_src0_data;                                                                   // rsp_demux_001:src0_data -> crosser_011:in_data
+	wire          rsp_demux_001_src0_ready;                                                                  // crosser_011:in_ready -> rsp_demux_001:src0_ready
+	wire   [20:0] rsp_demux_001_src0_channel;                                                                // rsp_demux_001:src0_channel -> crosser_011:in_channel
+	wire          rsp_demux_001_src0_startofpacket;                                                          // rsp_demux_001:src0_startofpacket -> crosser_011:in_startofpacket
+	wire          rsp_demux_001_src0_endofpacket;                                                            // rsp_demux_001:src0_endofpacket -> crosser_011:in_endofpacket
+	wire          crosser_011_out_valid;                                                                     // crosser_011:out_valid -> rsp_mux:sink1_valid
+	wire  [120:0] crosser_011_out_data;                                                                      // crosser_011:out_data -> rsp_mux:sink1_data
+	wire          crosser_011_out_ready;                                                                     // rsp_mux:sink1_ready -> crosser_011:out_ready
+	wire   [20:0] crosser_011_out_channel;                                                                   // crosser_011:out_channel -> rsp_mux:sink1_channel
+	wire          crosser_011_out_startofpacket;                                                             // crosser_011:out_startofpacket -> rsp_mux:sink1_startofpacket
+	wire          crosser_011_out_endofpacket;                                                               // crosser_011:out_endofpacket -> rsp_mux:sink1_endofpacket
+	wire          rsp_demux_002_src0_valid;                                                                  // rsp_demux_002:src0_valid -> crosser_012:in_valid
+	wire  [120:0] rsp_demux_002_src0_data;                                                                   // rsp_demux_002:src0_data -> crosser_012:in_data
+	wire          rsp_demux_002_src0_ready;                                                                  // crosser_012:in_ready -> rsp_demux_002:src0_ready
+	wire   [20:0] rsp_demux_002_src0_channel;                                                                // rsp_demux_002:src0_channel -> crosser_012:in_channel
+	wire          rsp_demux_002_src0_startofpacket;                                                          // rsp_demux_002:src0_startofpacket -> crosser_012:in_startofpacket
+	wire          rsp_demux_002_src0_endofpacket;                                                            // rsp_demux_002:src0_endofpacket -> crosser_012:in_endofpacket
+	wire          crosser_012_out_valid;                                                                     // crosser_012:out_valid -> rsp_mux:sink2_valid
+	wire  [120:0] crosser_012_out_data;                                                                      // crosser_012:out_data -> rsp_mux:sink2_data
+	wire          crosser_012_out_ready;                                                                     // rsp_mux:sink2_ready -> crosser_012:out_ready
+	wire   [20:0] crosser_012_out_channel;                                                                   // crosser_012:out_channel -> rsp_mux:sink2_channel
+	wire          crosser_012_out_startofpacket;                                                             // crosser_012:out_startofpacket -> rsp_mux:sink2_startofpacket
+	wire          crosser_012_out_endofpacket;                                                               // crosser_012:out_endofpacket -> rsp_mux:sink2_endofpacket
+	wire          rsp_demux_002_src1_valid;                                                                  // rsp_demux_002:src1_valid -> crosser_013:in_valid
+	wire  [120:0] rsp_demux_002_src1_data;                                                                   // rsp_demux_002:src1_data -> crosser_013:in_data
+	wire          rsp_demux_002_src1_ready;                                                                  // crosser_013:in_ready -> rsp_demux_002:src1_ready
+	wire   [20:0] rsp_demux_002_src1_channel;                                                                // rsp_demux_002:src1_channel -> crosser_013:in_channel
+	wire          rsp_demux_002_src1_startofpacket;                                                          // rsp_demux_002:src1_startofpacket -> crosser_013:in_startofpacket
+	wire          rsp_demux_002_src1_endofpacket;                                                            // rsp_demux_002:src1_endofpacket -> crosser_013:in_endofpacket
+	wire          crosser_013_out_valid;                                                                     // crosser_013:out_valid -> rsp_mux_001:sink1_valid
+	wire  [120:0] crosser_013_out_data;                                                                      // crosser_013:out_data -> rsp_mux_001:sink1_data
+	wire          crosser_013_out_ready;                                                                     // rsp_mux_001:sink1_ready -> crosser_013:out_ready
+	wire   [20:0] crosser_013_out_channel;                                                                   // crosser_013:out_channel -> rsp_mux_001:sink1_channel
+	wire          crosser_013_out_startofpacket;                                                             // crosser_013:out_startofpacket -> rsp_mux_001:sink1_startofpacket
+	wire          crosser_013_out_endofpacket;                                                               // crosser_013:out_endofpacket -> rsp_mux_001:sink1_endofpacket
+	wire   [20:0] cpu_data_master_limiter_cmd_valid_data;                                                    // cpu_data_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
+	wire   [20:0] cpu_instruction_master_limiter_cmd_valid_data;                                             // cpu_instruction_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
+	wire          ddr3_ram_avl_agent_rdata_fifo_out_valid;                                                   // ddr3_ram_avl_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
+	wire   [33:0] ddr3_ram_avl_agent_rdata_fifo_out_data;                                                    // ddr3_ram_avl_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
+	wire          ddr3_ram_avl_agent_rdata_fifo_out_ready;                                                   // avalon_st_adapter:in_0_ready -> ddr3_ram_avl_agent_rdata_fifo:out_ready
+	wire          avalon_st_adapter_out_0_valid;                                                             // avalon_st_adapter:out_0_valid -> ddr3_ram_avl_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_out_0_data;                                                              // avalon_st_adapter:out_0_data -> ddr3_ram_avl_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_out_0_ready;                                                             // ddr3_ram_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+	wire    [0:0] avalon_st_adapter_out_0_error;                                                             // avalon_st_adapter:out_0_error -> ddr3_ram_avl_agent:rdata_fifo_sink_error
+	wire          ext_flash_avl_csr_agent_rdata_fifo_out_valid;                                              // ext_flash_avl_csr_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
+	wire   [33:0] ext_flash_avl_csr_agent_rdata_fifo_out_data;                                               // ext_flash_avl_csr_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
+	wire          ext_flash_avl_csr_agent_rdata_fifo_out_ready;                                              // avalon_st_adapter_001:in_0_ready -> ext_flash_avl_csr_agent_rdata_fifo:out_ready
+	wire          avalon_st_adapter_001_out_0_valid;                                                         // avalon_st_adapter_001:out_0_valid -> ext_flash_avl_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_001_out_0_data;                                                          // avalon_st_adapter_001:out_0_data -> ext_flash_avl_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_001_out_0_ready;                                                         // ext_flash_avl_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire    [0:0] avalon_st_adapter_001_out_0_error;                                                         // avalon_st_adapter_001:out_0_error -> ext_flash_avl_csr_agent:rdata_fifo_sink_error
+	wire          ext_flash_avl_mem_agent_rdata_fifo_out_valid;                                              // ext_flash_avl_mem_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
+	wire   [33:0] ext_flash_avl_mem_agent_rdata_fifo_out_data;                                               // ext_flash_avl_mem_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
+	wire          ext_flash_avl_mem_agent_rdata_fifo_out_ready;                                              // avalon_st_adapter_002:in_0_ready -> ext_flash_avl_mem_agent_rdata_fifo:out_ready
+	wire          avalon_st_adapter_002_out_0_valid;                                                         // avalon_st_adapter_002:out_0_valid -> ext_flash_avl_mem_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_002_out_0_data;                                                          // avalon_st_adapter_002:out_0_data -> ext_flash_avl_mem_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_002_out_0_ready;                                                         // ext_flash_avl_mem_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
+	wire    [0:0] avalon_st_adapter_002_out_0_error;                                                         // avalon_st_adapter_002:out_0_error -> ext_flash_avl_mem_agent:rdata_fifo_sink_error
+	wire          eth_tse_control_port_agent_rdata_fifo_src_valid;                                           // eth_tse_control_port_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
+	wire   [33:0] eth_tse_control_port_agent_rdata_fifo_src_data;                                            // eth_tse_control_port_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
+	wire          eth_tse_control_port_agent_rdata_fifo_src_ready;                                           // avalon_st_adapter_003:in_0_ready -> eth_tse_control_port_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_003_out_0_valid;                                                         // avalon_st_adapter_003:out_0_valid -> eth_tse_control_port_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_003_out_0_data;                                                          // avalon_st_adapter_003:out_0_data -> eth_tse_control_port_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_003_out_0_ready;                                                         // eth_tse_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
+	wire    [0:0] avalon_st_adapter_003_out_0_error;                                                         // avalon_st_adapter_003:out_0_error -> eth_tse_control_port_agent:rdata_fifo_sink_error
+	wire          sysid_control_slave_agent_rdata_fifo_src_valid;                                            // sysid_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
+	wire   [33:0] sysid_control_slave_agent_rdata_fifo_src_data;                                             // sysid_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
+	wire          sysid_control_slave_agent_rdata_fifo_src_ready;                                            // avalon_st_adapter_004:in_0_ready -> sysid_control_slave_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_004_out_0_valid;                                                         // avalon_st_adapter_004:out_0_valid -> sysid_control_slave_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_004_out_0_data;                                                          // avalon_st_adapter_004:out_0_data -> sysid_control_slave_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_004_out_0_ready;                                                         // sysid_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
+	wire    [0:0] avalon_st_adapter_004_out_0_error;                                                         // avalon_st_adapter_004:out_0_error -> sysid_control_slave_agent:rdata_fifo_sink_error
+	wire          msgdma_tx_csr_agent_rdata_fifo_src_valid;                                                  // msgdma_tx_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
+	wire   [33:0] msgdma_tx_csr_agent_rdata_fifo_src_data;                                                   // msgdma_tx_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
+	wire          msgdma_tx_csr_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter_005:in_0_ready -> msgdma_tx_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_005_out_0_valid;                                                         // avalon_st_adapter_005:out_0_valid -> msgdma_tx_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_005_out_0_data;                                                          // avalon_st_adapter_005:out_0_data -> msgdma_tx_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_005_out_0_ready;                                                         // msgdma_tx_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
+	wire    [0:0] avalon_st_adapter_005_out_0_error;                                                         // avalon_st_adapter_005:out_0_error -> msgdma_tx_csr_agent:rdata_fifo_sink_error
+	wire          msgdma_rx_csr_agent_rdata_fifo_src_valid;                                                  // msgdma_rx_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
+	wire   [33:0] msgdma_rx_csr_agent_rdata_fifo_src_data;                                                   // msgdma_rx_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
+	wire          msgdma_rx_csr_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter_006:in_0_ready -> msgdma_rx_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_006_out_0_valid;                                                         // avalon_st_adapter_006:out_0_valid -> msgdma_rx_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_006_out_0_data;                                                          // avalon_st_adapter_006:out_0_data -> msgdma_rx_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_006_out_0_ready;                                                         // msgdma_rx_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
+	wire    [0:0] avalon_st_adapter_006_out_0_error;                                                         // avalon_st_adapter_006:out_0_error -> msgdma_rx_csr_agent:rdata_fifo_sink_error
+	wire          onchip_flash_csr_agent_rdata_fifo_src_valid;                                               // onchip_flash_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
+	wire   [33:0] onchip_flash_csr_agent_rdata_fifo_src_data;                                                // onchip_flash_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
+	wire          onchip_flash_csr_agent_rdata_fifo_src_ready;                                               // avalon_st_adapter_007:in_0_ready -> onchip_flash_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_007_out_0_valid;                                                         // avalon_st_adapter_007:out_0_valid -> onchip_flash_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_007_out_0_data;                                                          // avalon_st_adapter_007:out_0_data -> onchip_flash_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_007_out_0_ready;                                                         // onchip_flash_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
+	wire    [0:0] avalon_st_adapter_007_out_0_error;                                                         // avalon_st_adapter_007:out_0_error -> onchip_flash_csr_agent:rdata_fifo_sink_error
+	wire          udp_generator_csr_agent_rdata_fifo_src_valid;                                              // udp_generator_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
+	wire   [33:0] udp_generator_csr_agent_rdata_fifo_src_data;                                               // udp_generator_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
+	wire          udp_generator_csr_agent_rdata_fifo_src_ready;                                              // avalon_st_adapter_008:in_0_ready -> udp_generator_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_008_out_0_valid;                                                         // avalon_st_adapter_008:out_0_valid -> udp_generator_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_008_out_0_data;                                                          // avalon_st_adapter_008:out_0_data -> udp_generator_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_008_out_0_ready;                                                         // udp_generator_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
+	wire    [0:0] avalon_st_adapter_008_out_0_error;                                                         // avalon_st_adapter_008:out_0_error -> udp_generator_csr_agent:rdata_fifo_sink_error
+	wire          sensor_interface_csr_agent_rdata_fifo_src_valid;                                           // sensor_interface_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
+	wire   [33:0] sensor_interface_csr_agent_rdata_fifo_src_data;                                            // sensor_interface_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
+	wire          sensor_interface_csr_agent_rdata_fifo_src_ready;                                           // avalon_st_adapter_009:in_0_ready -> sensor_interface_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_009_out_0_valid;                                                         // avalon_st_adapter_009:out_0_valid -> sensor_interface_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_009_out_0_data;                                                          // avalon_st_adapter_009:out_0_data -> sensor_interface_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_009_out_0_ready;                                                         // sensor_interface_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
+	wire    [0:0] avalon_st_adapter_009_out_0_error;                                                         // avalon_st_adapter_009:out_0_error -> sensor_interface_csr_agent:rdata_fifo_sink_error
+	wire          onchip_flash_data_agent_rdata_fifo_src_valid;                                              // onchip_flash_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
+	wire   [33:0] onchip_flash_data_agent_rdata_fifo_src_data;                                               // onchip_flash_data_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
+	wire          onchip_flash_data_agent_rdata_fifo_src_ready;                                              // avalon_st_adapter_010:in_0_ready -> onchip_flash_data_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_010_out_0_valid;                                                         // avalon_st_adapter_010:out_0_valid -> onchip_flash_data_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_010_out_0_data;                                                          // avalon_st_adapter_010:out_0_data -> onchip_flash_data_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_010_out_0_ready;                                                         // onchip_flash_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
+	wire    [0:0] avalon_st_adapter_010_out_0_error;                                                         // avalon_st_adapter_010:out_0_error -> onchip_flash_data_agent:rdata_fifo_sink_error
+	wire          cpu_debug_mem_slave_agent_rdata_fifo_src_valid;                                            // cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_011:in_0_valid
+	wire   [33:0] cpu_debug_mem_slave_agent_rdata_fifo_src_data;                                             // cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_011:in_0_data
+	wire          cpu_debug_mem_slave_agent_rdata_fifo_src_ready;                                            // avalon_st_adapter_011:in_0_ready -> cpu_debug_mem_slave_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_011_out_0_valid;                                                         // avalon_st_adapter_011:out_0_valid -> cpu_debug_mem_slave_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_011_out_0_data;                                                          // avalon_st_adapter_011:out_0_data -> cpu_debug_mem_slave_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_011_out_0_ready;                                                         // cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_011:out_0_ready
+	wire    [0:0] avalon_st_adapter_011_out_0_error;                                                         // avalon_st_adapter_011:out_0_error -> cpu_debug_mem_slave_agent:rdata_fifo_sink_error
+	wire          msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_valid;                                       // msgdma_tx_prefetcher_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_012:in_0_valid
+	wire   [33:0] msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_data;                                        // msgdma_tx_prefetcher_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_012:in_0_data
+	wire          msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_ready;                                       // avalon_st_adapter_012:in_0_ready -> msgdma_tx_prefetcher_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_012_out_0_valid;                                                         // avalon_st_adapter_012:out_0_valid -> msgdma_tx_prefetcher_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_012_out_0_data;                                                          // avalon_st_adapter_012:out_0_data -> msgdma_tx_prefetcher_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_012_out_0_ready;                                                         // msgdma_tx_prefetcher_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_012:out_0_ready
+	wire    [0:0] avalon_st_adapter_012_out_0_error;                                                         // avalon_st_adapter_012:out_0_error -> msgdma_tx_prefetcher_csr_agent:rdata_fifo_sink_error
+	wire          msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_valid;                                       // msgdma_rx_prefetcher_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_013:in_0_valid
+	wire   [33:0] msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_data;                                        // msgdma_rx_prefetcher_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_013:in_0_data
+	wire          msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_ready;                                       // avalon_st_adapter_013:in_0_ready -> msgdma_rx_prefetcher_csr_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_013_out_0_valid;                                                         // avalon_st_adapter_013:out_0_valid -> msgdma_rx_prefetcher_csr_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_013_out_0_data;                                                          // avalon_st_adapter_013:out_0_data -> msgdma_rx_prefetcher_csr_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_013_out_0_ready;                                                         // msgdma_rx_prefetcher_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_013:out_0_ready
+	wire    [0:0] avalon_st_adapter_013_out_0_error;                                                         // avalon_st_adapter_013:out_0_error -> msgdma_rx_prefetcher_csr_agent:rdata_fifo_sink_error
+	wire          descriptor_memory_s1_agent_rdata_fifo_src_valid;                                           // descriptor_memory_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_014:in_0_valid
+	wire   [33:0] descriptor_memory_s1_agent_rdata_fifo_src_data;                                            // descriptor_memory_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_014:in_0_data
+	wire          descriptor_memory_s1_agent_rdata_fifo_src_ready;                                           // avalon_st_adapter_014:in_0_ready -> descriptor_memory_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_014_out_0_valid;                                                         // avalon_st_adapter_014:out_0_valid -> descriptor_memory_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_014_out_0_data;                                                          // avalon_st_adapter_014:out_0_data -> descriptor_memory_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_014_out_0_ready;                                                         // descriptor_memory_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_014:out_0_ready
+	wire    [0:0] avalon_st_adapter_014_out_0_error;                                                         // avalon_st_adapter_014:out_0_error -> descriptor_memory_s1_agent:rdata_fifo_sink_error
+	wire          sys_clk_timer_s1_agent_rdata_fifo_src_valid;                                               // sys_clk_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_015:in_0_valid
+	wire   [33:0] sys_clk_timer_s1_agent_rdata_fifo_src_data;                                                // sys_clk_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_015:in_0_data
+	wire          sys_clk_timer_s1_agent_rdata_fifo_src_ready;                                               // avalon_st_adapter_015:in_0_ready -> sys_clk_timer_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_015_out_0_valid;                                                         // avalon_st_adapter_015:out_0_valid -> sys_clk_timer_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_015_out_0_data;                                                          // avalon_st_adapter_015:out_0_data -> sys_clk_timer_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_015_out_0_ready;                                                         // sys_clk_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_015:out_0_ready
+	wire    [0:0] avalon_st_adapter_015_out_0_error;                                                         // avalon_st_adapter_015:out_0_error -> sys_clk_timer_s1_agent:rdata_fifo_sink_error
+	wire          output_pio_s1_agent_rdata_fifo_src_valid;                                                  // output_pio_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_016:in_0_valid
+	wire   [33:0] output_pio_s1_agent_rdata_fifo_src_data;                                                   // output_pio_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_016:in_0_data
+	wire          output_pio_s1_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter_016:in_0_ready -> output_pio_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_016_out_0_valid;                                                         // avalon_st_adapter_016:out_0_valid -> output_pio_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_016_out_0_data;                                                          // avalon_st_adapter_016:out_0_data -> output_pio_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_016_out_0_ready;                                                         // output_pio_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_016:out_0_ready
+	wire    [0:0] avalon_st_adapter_016_out_0_error;                                                         // avalon_st_adapter_016:out_0_error -> output_pio_s1_agent:rdata_fifo_sink_error
+	wire          button_pio_s1_agent_rdata_fifo_src_valid;                                                  // button_pio_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_017:in_0_valid
+	wire   [33:0] button_pio_s1_agent_rdata_fifo_src_data;                                                   // button_pio_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_017:in_0_data
+	wire          button_pio_s1_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter_017:in_0_ready -> button_pio_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_017_out_0_valid;                                                         // avalon_st_adapter_017:out_0_valid -> button_pio_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_017_out_0_data;                                                          // avalon_st_adapter_017:out_0_data -> button_pio_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_017_out_0_ready;                                                         // button_pio_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_017:out_0_ready
+	wire    [0:0] avalon_st_adapter_017_out_0_error;                                                         // avalon_st_adapter_017:out_0_error -> button_pio_s1_agent:rdata_fifo_sink_error
+	wire          debug_uart_s1_agent_rdata_fifo_src_valid;                                                  // debug_uart_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_018:in_0_valid
+	wire   [33:0] debug_uart_s1_agent_rdata_fifo_src_data;                                                   // debug_uart_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_018:in_0_data
+	wire          debug_uart_s1_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter_018:in_0_ready -> debug_uart_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_018_out_0_valid;                                                         // avalon_st_adapter_018:out_0_valid -> debug_uart_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_018_out_0_data;                                                          // avalon_st_adapter_018:out_0_data -> debug_uart_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_018_out_0_ready;                                                         // debug_uart_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_018:out_0_ready
+	wire    [0:0] avalon_st_adapter_018_out_0_error;                                                         // avalon_st_adapter_018:out_0_error -> debug_uart_s1_agent:rdata_fifo_sink_error
+	wire          frame_timer_s1_agent_rdata_fifo_src_valid;                                                 // frame_timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_019:in_0_valid
+	wire   [33:0] frame_timer_s1_agent_rdata_fifo_src_data;                                                  // frame_timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_019:in_0_data
+	wire          frame_timer_s1_agent_rdata_fifo_src_ready;                                                 // avalon_st_adapter_019:in_0_ready -> frame_timer_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_019_out_0_valid;                                                         // avalon_st_adapter_019:out_0_valid -> frame_timer_s1_agent:rdata_fifo_sink_valid
+	wire   [33:0] avalon_st_adapter_019_out_0_data;                                                          // avalon_st_adapter_019:out_0_data -> frame_timer_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_019_out_0_ready;                                                         // frame_timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_019:out_0_ready
+	wire    [0:0] avalon_st_adapter_019_out_0_error;                                                         // avalon_st_adapter_019:out_0_error -> frame_timer_s1_agent:rdata_fifo_sink_error
+	wire          calibration_ram_s1_agent_rdata_fifo_src_valid;                                             // calibration_ram_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_020:in_0_valid
+	wire   [17:0] calibration_ram_s1_agent_rdata_fifo_src_data;                                              // calibration_ram_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_020:in_0_data
+	wire          calibration_ram_s1_agent_rdata_fifo_src_ready;                                             // avalon_st_adapter_020:in_0_ready -> calibration_ram_s1_agent:rdata_fifo_src_ready
+	wire          avalon_st_adapter_020_out_0_valid;                                                         // avalon_st_adapter_020:out_0_valid -> calibration_ram_s1_agent:rdata_fifo_sink_valid
+	wire   [17:0] avalon_st_adapter_020_out_0_data;                                                          // avalon_st_adapter_020:out_0_data -> calibration_ram_s1_agent:rdata_fifo_sink_data
+	wire          avalon_st_adapter_020_out_0_ready;                                                         // calibration_ram_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_020:out_0_ready
+	wire    [0:0] avalon_st_adapter_020_out_0_error;                                                         // avalon_st_adapter_020:out_0_error -> calibration_ram_s1_agent:rdata_fifo_sink_error
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (1),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) cpu_data_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                    //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                              //                     reset.reset
+		.uav_address            (cpu_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (cpu_data_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (cpu_data_master_waitrequest),                                        //                          .waitrequest
+		.av_byteenable          (cpu_data_master_byteenable),                                         //                          .byteenable
+		.av_read                (cpu_data_master_read),                                               //                          .read
+		.av_readdata            (cpu_data_master_readdata),                                           //                          .readdata
+		.av_readdatavalid       (cpu_data_master_readdatavalid),                                      //                          .readdatavalid
+		.av_write               (cpu_data_master_write),                                              //                          .write
+		.av_writedata           (cpu_data_master_writedata),                                          //                          .writedata
+		.av_debugaccess         (cpu_data_master_debugaccess),                                        //                          .debugaccess
+		.av_burstcount          (1'b1),                                                               //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                               //               (terminated)
+		.av_begintransfer       (1'b0),                                                               //               (terminated)
+		.av_chipselect          (1'b0),                                                               //               (terminated)
+		.av_lock                (1'b0),                                                               //               (terminated)
+		.uav_clken              (),                                                                   //               (terminated)
+		.av_clken               (1'b1),                                                               //               (terminated)
+		.uav_response           (2'b00),                                                              //               (terminated)
+		.av_response            (),                                                                   //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                               //               (terminated)
+		.av_writeresponsevalid  ()                                                                    //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (1),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (1),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) cpu_instruction_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                           //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                     //                     reset.reset
+		.uav_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (cpu_instruction_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (cpu_instruction_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (cpu_instruction_master_read),                                               //                          .read
+		.av_readdata            (cpu_instruction_master_readdata),                                           //                          .readdata
+		.av_readdatavalid       (cpu_instruction_master_readdatavalid),                                      //                          .readdatavalid
+		.av_burstcount          (1'b1),                                                                      //               (terminated)
+		.av_byteenable          (4'b1111),                                                                   //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                      //               (terminated)
+		.av_begintransfer       (1'b0),                                                                      //               (terminated)
+		.av_chipselect          (1'b0),                                                                      //               (terminated)
+		.av_write               (1'b0),                                                                      //               (terminated)
+		.av_writedata           (32'b00000000000000000000000000000000),                                      //               (terminated)
+		.av_lock                (1'b0),                                                                      //               (terminated)
+		.av_debugaccess         (1'b0),                                                                      //               (terminated)
+		.uav_clken              (),                                                                          //               (terminated)
+		.av_clken               (1'b1),                                                                      //               (terminated)
+		.uav_response           (2'b00),                                                                     //               (terminated)
+		.av_response            (),                                                                          //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                      //               (terminated)
+		.av_writeresponsevalid  ()                                                                           //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (28),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (1),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_tx_mm_read_translator (
+		.clk                    (sys_clk_clk_clk),                                                      //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                //                     reset.reset
+		.uav_address            (msgdma_tx_mm_read_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_tx_mm_read_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (msgdma_tx_mm_read_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (msgdma_tx_mm_read_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (msgdma_tx_mm_read_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (msgdma_tx_mm_read_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (msgdma_tx_mm_read_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (msgdma_tx_mm_read_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (msgdma_tx_mm_read_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (msgdma_tx_mm_read_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (msgdma_tx_mm_read_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (msgdma_tx_mm_read_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_tx_mm_read_waitrequest),                                        //                          .waitrequest
+		.av_byteenable          (msgdma_tx_mm_read_byteenable),                                         //                          .byteenable
+		.av_read                (msgdma_tx_mm_read_read),                                               //                          .read
+		.av_readdata            (msgdma_tx_mm_read_readdata),                                           //                          .readdata
+		.av_readdatavalid       (msgdma_tx_mm_read_readdatavalid),                                      //                          .readdatavalid
+		.av_burstcount          (1'b1),                                                                 //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                 //               (terminated)
+		.av_begintransfer       (1'b0),                                                                 //               (terminated)
+		.av_chipselect          (1'b0),                                                                 //               (terminated)
+		.av_write               (1'b0),                                                                 //               (terminated)
+		.av_writedata           (32'b00000000000000000000000000000000),                                 //               (terminated)
+		.av_lock                (1'b0),                                                                 //               (terminated)
+		.av_debugaccess         (1'b0),                                                                 //               (terminated)
+		.uav_clken              (),                                                                     //               (terminated)
+		.av_clken               (1'b1),                                                                 //               (terminated)
+		.uav_response           (2'b00),                                                                //               (terminated)
+		.av_response            (),                                                                     //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                 //               (terminated)
+		.av_writeresponsevalid  ()                                                                      //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (28),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (0),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_rx_mm_write_translator (
+		.clk                    (sys_clk_clk_clk),                                                       //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                 //                     reset.reset
+		.uav_address            (msgdma_rx_mm_write_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_rx_mm_write_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (msgdma_rx_mm_write_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (msgdma_rx_mm_write_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (msgdma_rx_mm_write_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (msgdma_rx_mm_write_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (msgdma_rx_mm_write_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (msgdma_rx_mm_write_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (msgdma_rx_mm_write_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (msgdma_rx_mm_write_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (msgdma_rx_mm_write_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (msgdma_rx_mm_write_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_rx_mm_write_waitrequest),                                        //                          .waitrequest
+		.av_byteenable          (msgdma_rx_mm_write_byteenable),                                         //                          .byteenable
+		.av_write               (msgdma_rx_mm_write_write),                                              //                          .write
+		.av_writedata           (msgdma_rx_mm_write_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                  //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                  //               (terminated)
+		.av_begintransfer       (1'b0),                                                                  //               (terminated)
+		.av_chipselect          (1'b0),                                                                  //               (terminated)
+		.av_read                (1'b0),                                                                  //               (terminated)
+		.av_readdata            (),                                                                      //               (terminated)
+		.av_readdatavalid       (),                                                                      //               (terminated)
+		.av_lock                (1'b0),                                                                  //               (terminated)
+		.av_debugaccess         (1'b0),                                                                  //               (terminated)
+		.uav_clken              (),                                                                      //               (terminated)
+		.av_clken               (1'b1),                                                                  //               (terminated)
+		.uav_response           (2'b00),                                                                 //               (terminated)
+		.av_response            (),                                                                      //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                  //               (terminated)
+		.av_writeresponsevalid  ()                                                                       //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (1),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_tx_descriptor_read_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                                     //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                               //                     reset.reset
+		.uav_address            (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (msgdma_tx_descriptor_read_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_tx_descriptor_read_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (msgdma_tx_descriptor_read_master_read),                                               //                          .read
+		.av_readdata            (msgdma_tx_descriptor_read_master_readdata),                                           //                          .readdata
+		.av_readdatavalid       (msgdma_tx_descriptor_read_master_readdatavalid),                                      //                          .readdatavalid
+		.av_burstcount          (1'b1),                                                                                //               (terminated)
+		.av_byteenable          (4'b1111),                                                                             //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                                //               (terminated)
+		.av_begintransfer       (1'b0),                                                                                //               (terminated)
+		.av_chipselect          (1'b0),                                                                                //               (terminated)
+		.av_write               (1'b0),                                                                                //               (terminated)
+		.av_writedata           (32'b00000000000000000000000000000000),                                                //               (terminated)
+		.av_lock                (1'b0),                                                                                //               (terminated)
+		.av_debugaccess         (1'b0),                                                                                //               (terminated)
+		.uav_clken              (),                                                                                    //               (terminated)
+		.av_clken               (1'b1),                                                                                //               (terminated)
+		.uav_response           (2'b00),                                                                               //               (terminated)
+		.av_response            (),                                                                                    //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                                //               (terminated)
+		.av_writeresponsevalid  ()                                                                                     //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (1),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_rx_descriptor_read_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                                     //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                               //                     reset.reset
+		.uav_address            (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (msgdma_rx_descriptor_read_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_rx_descriptor_read_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (msgdma_rx_descriptor_read_master_read),                                               //                          .read
+		.av_readdata            (msgdma_rx_descriptor_read_master_readdata),                                           //                          .readdata
+		.av_readdatavalid       (msgdma_rx_descriptor_read_master_readdatavalid),                                      //                          .readdatavalid
+		.av_burstcount          (1'b1),                                                                                //               (terminated)
+		.av_byteenable          (4'b1111),                                                                             //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                                //               (terminated)
+		.av_begintransfer       (1'b0),                                                                                //               (terminated)
+		.av_chipselect          (1'b0),                                                                                //               (terminated)
+		.av_write               (1'b0),                                                                                //               (terminated)
+		.av_writedata           (32'b00000000000000000000000000000000),                                                //               (terminated)
+		.av_lock                (1'b0),                                                                                //               (terminated)
+		.av_debugaccess         (1'b0),                                                                                //               (terminated)
+		.uav_clken              (),                                                                                    //               (terminated)
+		.av_clken               (1'b1),                                                                                //               (terminated)
+		.uav_response           (2'b00),                                                                               //               (terminated)
+		.av_response            (),                                                                                    //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                                //               (terminated)
+		.av_writeresponsevalid  ()                                                                                     //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (0),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (1),
+		.USE_WRITERESPONSE           (1),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_tx_descriptor_write_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                                           //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                                     //                     reset.reset
+		.uav_address            (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_address),            // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_burstcount),         //                          .burstcount
+		.uav_read               (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_read),               //                          .read
+		.uav_write              (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_write),              //                          .write
+		.uav_waitrequest        (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest),        //                          .waitrequest
+		.uav_readdatavalid      (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid),      //                          .readdatavalid
+		.uav_byteenable         (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_byteenable),         //                          .byteenable
+		.uav_readdata           (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdata),           //                          .readdata
+		.uav_writedata          (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writedata),          //                          .writedata
+		.uav_lock               (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_lock),               //                          .lock
+		.uav_debugaccess        (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess),        //                          .debugaccess
+		.uav_response           (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_response),           //                          .response
+		.uav_writeresponsevalid (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid), //                          .writeresponsevalid
+		.av_address             (msgdma_tx_descriptor_write_master_address),                                                 //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_tx_descriptor_write_master_waitrequest),                                             //                          .waitrequest
+		.av_byteenable          (msgdma_tx_descriptor_write_master_byteenable),                                              //                          .byteenable
+		.av_write               (msgdma_tx_descriptor_write_master_write),                                                   //                          .write
+		.av_writedata           (msgdma_tx_descriptor_write_master_writedata),                                               //                          .writedata
+		.av_response            (msgdma_tx_descriptor_write_master_response),                                                //                          .response
+		.av_writeresponsevalid  (msgdma_tx_descriptor_write_master_writeresponsevalid),                                      //                          .writeresponsevalid
+		.av_burstcount          (1'b1),                                                                                      //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                                      //               (terminated)
+		.av_begintransfer       (1'b0),                                                                                      //               (terminated)
+		.av_chipselect          (1'b0),                                                                                      //               (terminated)
+		.av_read                (1'b0),                                                                                      //               (terminated)
+		.av_readdata            (),                                                                                          //               (terminated)
+		.av_readdatavalid       (),                                                                                          //               (terminated)
+		.av_lock                (1'b0),                                                                                      //               (terminated)
+		.av_debugaccess         (1'b0),                                                                                      //               (terminated)
+		.uav_clken              (),                                                                                          //               (terminated)
+		.av_clken               (1'b1)                                                                                       //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (29),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (29),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (0),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (1),
+		.USE_WRITERESPONSE           (1),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) msgdma_rx_descriptor_write_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                                           //                       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                                                     //                     reset.reset
+		.uav_address            (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_address),            // avalon_universal_master_0.address
+		.uav_burstcount         (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_burstcount),         //                          .burstcount
+		.uav_read               (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_read),               //                          .read
+		.uav_write              (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_write),              //                          .write
+		.uav_waitrequest        (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest),        //                          .waitrequest
+		.uav_readdatavalid      (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid),      //                          .readdatavalid
+		.uav_byteenable         (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_byteenable),         //                          .byteenable
+		.uav_readdata           (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdata),           //                          .readdata
+		.uav_writedata          (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writedata),          //                          .writedata
+		.uav_lock               (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_lock),               //                          .lock
+		.uav_debugaccess        (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess),        //                          .debugaccess
+		.uav_response           (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_response),           //                          .response
+		.uav_writeresponsevalid (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid), //                          .writeresponsevalid
+		.av_address             (msgdma_rx_descriptor_write_master_address),                                                 //      avalon_anti_master_0.address
+		.av_waitrequest         (msgdma_rx_descriptor_write_master_waitrequest),                                             //                          .waitrequest
+		.av_byteenable          (msgdma_rx_descriptor_write_master_byteenable),                                              //                          .byteenable
+		.av_write               (msgdma_rx_descriptor_write_master_write),                                                   //                          .write
+		.av_writedata           (msgdma_rx_descriptor_write_master_writedata),                                               //                          .writedata
+		.av_response            (msgdma_rx_descriptor_write_master_response),                                                //                          .response
+		.av_writeresponsevalid  (msgdma_rx_descriptor_write_master_writeresponsevalid),                                      //                          .writeresponsevalid
+		.av_burstcount          (1'b1),                                                                                      //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                                      //               (terminated)
+		.av_begintransfer       (1'b0),                                                                                      //               (terminated)
+		.av_chipselect          (1'b0),                                                                                      //               (terminated)
+		.av_read                (1'b0),                                                                                      //               (terminated)
+		.av_readdata            (),                                                                                          //               (terminated)
+		.av_readdatavalid       (),                                                                                          //               (terminated)
+		.av_lock                (1'b0),                                                                                      //               (terminated)
+		.av_debugaccess         (1'b0),                                                                                      //               (terminated)
+		.uav_clken              (),                                                                                          //               (terminated)
+		.av_clken               (1'b1)                                                                                       //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (25),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (3),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (5),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (1),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) ddr3_ram_avl_translator (
+		.clk                    (ddr3_ram_afi_clk_clk),                                      //                      clk.clk
+		.reset                  (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (ddr3_ram_avl_agent_m0_address),                             // avalon_universal_slave_0.address
+		.uav_burstcount         (ddr3_ram_avl_agent_m0_burstcount),                          //                         .burstcount
+		.uav_read               (ddr3_ram_avl_agent_m0_read),                                //                         .read
+		.uav_write              (ddr3_ram_avl_agent_m0_write),                               //                         .write
+		.uav_waitrequest        (ddr3_ram_avl_agent_m0_waitrequest),                         //                         .waitrequest
+		.uav_readdatavalid      (ddr3_ram_avl_agent_m0_readdatavalid),                       //                         .readdatavalid
+		.uav_byteenable         (ddr3_ram_avl_agent_m0_byteenable),                          //                         .byteenable
+		.uav_readdata           (ddr3_ram_avl_agent_m0_readdata),                            //                         .readdata
+		.uav_writedata          (ddr3_ram_avl_agent_m0_writedata),                           //                         .writedata
+		.uav_lock               (ddr3_ram_avl_agent_m0_lock),                                //                         .lock
+		.uav_debugaccess        (ddr3_ram_avl_agent_m0_debugaccess),                         //                         .debugaccess
+		.av_address             (ddr3_ram_avl_address),                                      //      avalon_anti_slave_0.address
+		.av_write               (ddr3_ram_avl_write),                                        //                         .write
+		.av_read                (ddr3_ram_avl_read),                                         //                         .read
+		.av_readdata            (ddr3_ram_avl_readdata),                                     //                         .readdata
+		.av_writedata           (ddr3_ram_avl_writedata),                                    //                         .writedata
+		.av_beginbursttransfer  (ddr3_ram_avl_beginbursttransfer),                           //                         .beginbursttransfer
+		.av_burstcount          (ddr3_ram_avl_burstcount),                                   //                         .burstcount
+		.av_byteenable          (ddr3_ram_avl_byteenable),                                   //                         .byteenable
+		.av_readdatavalid       (ddr3_ram_avl_readdatavalid),                                //                         .readdatavalid
+		.av_waitrequest         (ddr3_ram_avl_waitrequest),                                  //                         .waitrequest
+		.av_begintransfer       (),                                                          //              (terminated)
+		.av_writebyteenable     (),                                                          //              (terminated)
+		.av_lock                (),                                                          //              (terminated)
+		.av_chipselect          (),                                                          //              (terminated)
+		.av_clken               (),                                                          //              (terminated)
+		.uav_clken              (1'b0),                                                      //              (terminated)
+		.av_debugaccess         (),                                                          //              (terminated)
+		.av_outputenable        (),                                                          //              (terminated)
+		.uav_response           (),                                                          //              (terminated)
+		.av_response            (2'b00),                                                     //              (terminated)
+		.uav_writeresponsevalid (),                                                          //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                       //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (1),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) ext_flash_avl_csr_translator (
+		.clk                    (ext_flash_clock_bridge_out_clk_clk),          //                      clk.clk
+		.reset                  (ext_flash_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (ext_flash_avl_csr_agent_m0_address),          // avalon_universal_slave_0.address
+		.uav_burstcount         (ext_flash_avl_csr_agent_m0_burstcount),       //                         .burstcount
+		.uav_read               (ext_flash_avl_csr_agent_m0_read),             //                         .read
+		.uav_write              (ext_flash_avl_csr_agent_m0_write),            //                         .write
+		.uav_waitrequest        (ext_flash_avl_csr_agent_m0_waitrequest),      //                         .waitrequest
+		.uav_readdatavalid      (ext_flash_avl_csr_agent_m0_readdatavalid),    //                         .readdatavalid
+		.uav_byteenable         (ext_flash_avl_csr_agent_m0_byteenable),       //                         .byteenable
+		.uav_readdata           (ext_flash_avl_csr_agent_m0_readdata),         //                         .readdata
+		.uav_writedata          (ext_flash_avl_csr_agent_m0_writedata),        //                         .writedata
+		.uav_lock               (ext_flash_avl_csr_agent_m0_lock),             //                         .lock
+		.uav_debugaccess        (ext_flash_avl_csr_agent_m0_debugaccess),      //                         .debugaccess
+		.av_address             (ext_flash_avl_csr_address),                   //      avalon_anti_slave_0.address
+		.av_write               (ext_flash_avl_csr_write),                     //                         .write
+		.av_read                (ext_flash_avl_csr_read),                      //                         .read
+		.av_readdata            (ext_flash_avl_csr_readdata),                  //                         .readdata
+		.av_writedata           (ext_flash_avl_csr_writedata),                 //                         .writedata
+		.av_readdatavalid       (ext_flash_avl_csr_readdatavalid),             //                         .readdatavalid
+		.av_waitrequest         (ext_flash_avl_csr_waitrequest),               //                         .waitrequest
+		.av_begintransfer       (),                                            //              (terminated)
+		.av_beginbursttransfer  (),                                            //              (terminated)
+		.av_burstcount          (),                                            //              (terminated)
+		.av_byteenable          (),                                            //              (terminated)
+		.av_writebyteenable     (),                                            //              (terminated)
+		.av_lock                (),                                            //              (terminated)
+		.av_chipselect          (),                                            //              (terminated)
+		.av_clken               (),                                            //              (terminated)
+		.uav_clken              (1'b0),                                        //              (terminated)
+		.av_debugaccess         (),                                            //              (terminated)
+		.av_outputenable        (),                                            //              (terminated)
+		.uav_response           (),                                            //              (terminated)
+		.av_response            (2'b00),                                       //              (terminated)
+		.uav_writeresponsevalid (),                                            //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                         //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (24),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (7),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (9),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (1),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (1),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) ext_flash_avl_mem_translator (
+		.clk                    (ext_flash_clock_bridge_out_clk_clk),          //                      clk.clk
+		.reset                  (ext_flash_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (ext_flash_avl_mem_agent_m0_address),          // avalon_universal_slave_0.address
+		.uav_burstcount         (ext_flash_avl_mem_agent_m0_burstcount),       //                         .burstcount
+		.uav_read               (ext_flash_avl_mem_agent_m0_read),             //                         .read
+		.uav_write              (ext_flash_avl_mem_agent_m0_write),            //                         .write
+		.uav_waitrequest        (ext_flash_avl_mem_agent_m0_waitrequest),      //                         .waitrequest
+		.uav_readdatavalid      (ext_flash_avl_mem_agent_m0_readdatavalid),    //                         .readdatavalid
+		.uav_byteenable         (ext_flash_avl_mem_agent_m0_byteenable),       //                         .byteenable
+		.uav_readdata           (ext_flash_avl_mem_agent_m0_readdata),         //                         .readdata
+		.uav_writedata          (ext_flash_avl_mem_agent_m0_writedata),        //                         .writedata
+		.uav_lock               (ext_flash_avl_mem_agent_m0_lock),             //                         .lock
+		.uav_debugaccess        (ext_flash_avl_mem_agent_m0_debugaccess),      //                         .debugaccess
+		.av_address             (ext_flash_avl_mem_address),                   //      avalon_anti_slave_0.address
+		.av_write               (ext_flash_avl_mem_write),                     //                         .write
+		.av_read                (ext_flash_avl_mem_read),                      //                         .read
+		.av_readdata            (ext_flash_avl_mem_readdata),                  //                         .readdata
+		.av_writedata           (ext_flash_avl_mem_writedata),                 //                         .writedata
+		.av_burstcount          (ext_flash_avl_mem_burstcount),                //                         .burstcount
+		.av_byteenable          (ext_flash_avl_mem_byteenable),                //                         .byteenable
+		.av_readdatavalid       (ext_flash_avl_mem_readdatavalid),             //                         .readdatavalid
+		.av_waitrequest         (ext_flash_avl_mem_waitrequest),               //                         .waitrequest
+		.av_begintransfer       (),                                            //              (terminated)
+		.av_beginbursttransfer  (),                                            //              (terminated)
+		.av_writebyteenable     (),                                            //              (terminated)
+		.av_lock                (),                                            //              (terminated)
+		.av_chipselect          (),                                            //              (terminated)
+		.av_clken               (),                                            //              (terminated)
+		.uav_clken              (1'b0),                                        //              (terminated)
+		.av_debugaccess         (),                                            //              (terminated)
+		.av_outputenable        (),                                            //              (terminated)
+		.uav_response           (),                                            //              (terminated)
+		.av_response            (2'b00),                                       //              (terminated)
+		.uav_writeresponsevalid (),                                            //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                         //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (8),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (1),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) eth_tse_control_port_translator (
+		.clk                    (sys_clk_clk_clk),                                      //                      clk.clk
+		.reset                  (eth_tse_reset_connection_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (eth_tse_control_port_agent_m0_address),                // avalon_universal_slave_0.address
+		.uav_burstcount         (eth_tse_control_port_agent_m0_burstcount),             //                         .burstcount
+		.uav_read               (eth_tse_control_port_agent_m0_read),                   //                         .read
+		.uav_write              (eth_tse_control_port_agent_m0_write),                  //                         .write
+		.uav_waitrequest        (eth_tse_control_port_agent_m0_waitrequest),            //                         .waitrequest
+		.uav_readdatavalid      (eth_tse_control_port_agent_m0_readdatavalid),          //                         .readdatavalid
+		.uav_byteenable         (eth_tse_control_port_agent_m0_byteenable),             //                         .byteenable
+		.uav_readdata           (eth_tse_control_port_agent_m0_readdata),               //                         .readdata
+		.uav_writedata          (eth_tse_control_port_agent_m0_writedata),              //                         .writedata
+		.uav_lock               (eth_tse_control_port_agent_m0_lock),                   //                         .lock
+		.uav_debugaccess        (eth_tse_control_port_agent_m0_debugaccess),            //                         .debugaccess
+		.av_address             (eth_tse_control_port_address),                         //      avalon_anti_slave_0.address
+		.av_write               (eth_tse_control_port_write),                           //                         .write
+		.av_read                (eth_tse_control_port_read),                            //                         .read
+		.av_readdata            (eth_tse_control_port_readdata),                        //                         .readdata
+		.av_writedata           (eth_tse_control_port_writedata),                       //                         .writedata
+		.av_waitrequest         (eth_tse_control_port_waitrequest),                     //                         .waitrequest
+		.av_begintransfer       (),                                                     //              (terminated)
+		.av_beginbursttransfer  (),                                                     //              (terminated)
+		.av_burstcount          (),                                                     //              (terminated)
+		.av_byteenable          (),                                                     //              (terminated)
+		.av_readdatavalid       (1'b0),                                                 //              (terminated)
+		.av_writebyteenable     (),                                                     //              (terminated)
+		.av_lock                (),                                                     //              (terminated)
+		.av_chipselect          (),                                                     //              (terminated)
+		.av_clken               (),                                                     //              (terminated)
+		.uav_clken              (1'b0),                                                 //              (terminated)
+		.av_debugaccess         (),                                                     //              (terminated)
+		.av_outputenable        (),                                                     //              (terminated)
+		.uav_response           (),                                                     //              (terminated)
+		.av_response            (2'b00),                                                //              (terminated)
+		.uav_writeresponsevalid (),                                                     //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                  //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (1),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sysid_control_slave_translator (
+		.clk                    (sys_clk_clk_clk),                                      //                      clk.clk
+		.reset                  (eth_tse_reset_connection_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sysid_control_slave_agent_m0_address),                 // avalon_universal_slave_0.address
+		.uav_burstcount         (sysid_control_slave_agent_m0_burstcount),              //                         .burstcount
+		.uav_read               (sysid_control_slave_agent_m0_read),                    //                         .read
+		.uav_write              (sysid_control_slave_agent_m0_write),                   //                         .write
+		.uav_waitrequest        (sysid_control_slave_agent_m0_waitrequest),             //                         .waitrequest
+		.uav_readdatavalid      (sysid_control_slave_agent_m0_readdatavalid),           //                         .readdatavalid
+		.uav_byteenable         (sysid_control_slave_agent_m0_byteenable),              //                         .byteenable
+		.uav_readdata           (sysid_control_slave_agent_m0_readdata),                //                         .readdata
+		.uav_writedata          (sysid_control_slave_agent_m0_writedata),               //                         .writedata
+		.uav_lock               (sysid_control_slave_agent_m0_lock),                    //                         .lock
+		.uav_debugaccess        (sysid_control_slave_agent_m0_debugaccess),             //                         .debugaccess
+		.av_address             (sysid_control_slave_address),                          //      avalon_anti_slave_0.address
+		.av_readdata            (sysid_control_slave_readdata),                         //                         .readdata
+		.av_write               (),                                                     //              (terminated)
+		.av_read                (),                                                     //              (terminated)
+		.av_writedata           (),                                                     //              (terminated)
+		.av_begintransfer       (),                                                     //              (terminated)
+		.av_beginbursttransfer  (),                                                     //              (terminated)
+		.av_burstcount          (),                                                     //              (terminated)
+		.av_byteenable          (),                                                     //              (terminated)
+		.av_readdatavalid       (1'b0),                                                 //              (terminated)
+		.av_waitrequest         (1'b0),                                                 //              (terminated)
+		.av_writebyteenable     (),                                                     //              (terminated)
+		.av_lock                (),                                                     //              (terminated)
+		.av_chipselect          (),                                                     //              (terminated)
+		.av_clken               (),                                                     //              (terminated)
+		.uav_clken              (1'b0),                                                 //              (terminated)
+		.av_debugaccess         (),                                                     //              (terminated)
+		.av_outputenable        (),                                                     //              (terminated)
+		.uav_response           (),                                                     //              (terminated)
+		.av_response            (2'b00),                                                //              (terminated)
+		.uav_writeresponsevalid (),                                                     //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                  //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) msgdma_tx_csr_translator (
+		.clk                    (sys_clk_clk_clk),                       //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (msgdma_tx_csr_agent_m0_address),        // avalon_universal_slave_0.address
+		.uav_burstcount         (msgdma_tx_csr_agent_m0_burstcount),     //                         .burstcount
+		.uav_read               (msgdma_tx_csr_agent_m0_read),           //                         .read
+		.uav_write              (msgdma_tx_csr_agent_m0_write),          //                         .write
+		.uav_waitrequest        (msgdma_tx_csr_agent_m0_waitrequest),    //                         .waitrequest
+		.uav_readdatavalid      (msgdma_tx_csr_agent_m0_readdatavalid),  //                         .readdatavalid
+		.uav_byteenable         (msgdma_tx_csr_agent_m0_byteenable),     //                         .byteenable
+		.uav_readdata           (msgdma_tx_csr_agent_m0_readdata),       //                         .readdata
+		.uav_writedata          (msgdma_tx_csr_agent_m0_writedata),      //                         .writedata
+		.uav_lock               (msgdma_tx_csr_agent_m0_lock),           //                         .lock
+		.uav_debugaccess        (msgdma_tx_csr_agent_m0_debugaccess),    //                         .debugaccess
+		.av_address             (msgdma_tx_csr_address),                 //      avalon_anti_slave_0.address
+		.av_write               (msgdma_tx_csr_write),                   //                         .write
+		.av_read                (msgdma_tx_csr_read),                    //                         .read
+		.av_readdata            (msgdma_tx_csr_readdata),                //                         .readdata
+		.av_writedata           (msgdma_tx_csr_writedata),               //                         .writedata
+		.av_byteenable          (msgdma_tx_csr_byteenable),              //                         .byteenable
+		.av_begintransfer       (),                                      //              (terminated)
+		.av_beginbursttransfer  (),                                      //              (terminated)
+		.av_burstcount          (),                                      //              (terminated)
+		.av_readdatavalid       (1'b0),                                  //              (terminated)
+		.av_waitrequest         (1'b0),                                  //              (terminated)
+		.av_writebyteenable     (),                                      //              (terminated)
+		.av_lock                (),                                      //              (terminated)
+		.av_chipselect          (),                                      //              (terminated)
+		.av_clken               (),                                      //              (terminated)
+		.uav_clken              (1'b0),                                  //              (terminated)
+		.av_debugaccess         (),                                      //              (terminated)
+		.av_outputenable        (),                                      //              (terminated)
+		.uav_response           (),                                      //              (terminated)
+		.av_response            (2'b00),                                 //              (terminated)
+		.uav_writeresponsevalid (),                                      //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) msgdma_rx_csr_translator (
+		.clk                    (sys_clk_clk_clk),                       //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (msgdma_rx_csr_agent_m0_address),        // avalon_universal_slave_0.address
+		.uav_burstcount         (msgdma_rx_csr_agent_m0_burstcount),     //                         .burstcount
+		.uav_read               (msgdma_rx_csr_agent_m0_read),           //                         .read
+		.uav_write              (msgdma_rx_csr_agent_m0_write),          //                         .write
+		.uav_waitrequest        (msgdma_rx_csr_agent_m0_waitrequest),    //                         .waitrequest
+		.uav_readdatavalid      (msgdma_rx_csr_agent_m0_readdatavalid),  //                         .readdatavalid
+		.uav_byteenable         (msgdma_rx_csr_agent_m0_byteenable),     //                         .byteenable
+		.uav_readdata           (msgdma_rx_csr_agent_m0_readdata),       //                         .readdata
+		.uav_writedata          (msgdma_rx_csr_agent_m0_writedata),      //                         .writedata
+		.uav_lock               (msgdma_rx_csr_agent_m0_lock),           //                         .lock
+		.uav_debugaccess        (msgdma_rx_csr_agent_m0_debugaccess),    //                         .debugaccess
+		.av_address             (msgdma_rx_csr_address),                 //      avalon_anti_slave_0.address
+		.av_write               (msgdma_rx_csr_write),                   //                         .write
+		.av_read                (msgdma_rx_csr_read),                    //                         .read
+		.av_readdata            (msgdma_rx_csr_readdata),                //                         .readdata
+		.av_writedata           (msgdma_rx_csr_writedata),               //                         .writedata
+		.av_byteenable          (msgdma_rx_csr_byteenable),              //                         .byteenable
+		.av_begintransfer       (),                                      //              (terminated)
+		.av_beginbursttransfer  (),                                      //              (terminated)
+		.av_burstcount          (),                                      //              (terminated)
+		.av_readdatavalid       (1'b0),                                  //              (terminated)
+		.av_waitrequest         (1'b0),                                  //              (terminated)
+		.av_writebyteenable     (),                                      //              (terminated)
+		.av_lock                (),                                      //              (terminated)
+		.av_chipselect          (),                                      //              (terminated)
+		.av_clken               (),                                      //              (terminated)
+		.uav_clken              (1'b0),                                  //              (terminated)
+		.av_debugaccess         (),                                      //              (terminated)
+		.av_outputenable        (),                                      //              (terminated)
+		.uav_response           (),                                      //              (terminated)
+		.av_response            (2'b00),                                 //              (terminated)
+		.uav_writeresponsevalid (),                                      //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (1),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) onchip_flash_csr_translator (
+		.clk                    (sys_clk_clk_clk),                         //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),   //                    reset.reset
+		.uav_address            (onchip_flash_csr_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (onchip_flash_csr_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (onchip_flash_csr_agent_m0_read),          //                         .read
+		.uav_write              (onchip_flash_csr_agent_m0_write),         //                         .write
+		.uav_waitrequest        (onchip_flash_csr_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (onchip_flash_csr_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (onchip_flash_csr_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (onchip_flash_csr_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (onchip_flash_csr_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (onchip_flash_csr_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (onchip_flash_csr_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (onchip_flash_csr_address),                //      avalon_anti_slave_0.address
+		.av_write               (onchip_flash_csr_write),                  //                         .write
+		.av_read                (onchip_flash_csr_read),                   //                         .read
+		.av_readdata            (onchip_flash_csr_readdata),               //                         .readdata
+		.av_writedata           (onchip_flash_csr_writedata),              //                         .writedata
+		.av_begintransfer       (),                                        //              (terminated)
+		.av_beginbursttransfer  (),                                        //              (terminated)
+		.av_burstcount          (),                                        //              (terminated)
+		.av_byteenable          (),                                        //              (terminated)
+		.av_readdatavalid       (1'b0),                                    //              (terminated)
+		.av_waitrequest         (1'b0),                                    //              (terminated)
+		.av_writebyteenable     (),                                        //              (terminated)
+		.av_lock                (),                                        //              (terminated)
+		.av_chipselect          (),                                        //              (terminated)
+		.av_clken               (),                                        //              (terminated)
+		.uav_clken              (1'b0),                                    //              (terminated)
+		.av_debugaccess         (),                                        //              (terminated)
+		.av_outputenable        (),                                        //              (terminated)
+		.uav_response           (),                                        //              (terminated)
+		.av_response            (2'b00),                                   //              (terminated)
+		.uav_writeresponsevalid (),                                        //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) udp_generator_csr_translator (
+		.clk                    (sys_clk_clk_clk),                          //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),    //                    reset.reset
+		.uav_address            (udp_generator_csr_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (udp_generator_csr_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (udp_generator_csr_agent_m0_read),          //                         .read
+		.uav_write              (udp_generator_csr_agent_m0_write),         //                         .write
+		.uav_waitrequest        (udp_generator_csr_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (udp_generator_csr_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (udp_generator_csr_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (udp_generator_csr_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (udp_generator_csr_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (udp_generator_csr_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (udp_generator_csr_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (udp_generator_csr_address),                //      avalon_anti_slave_0.address
+		.av_write               (udp_generator_csr_write),                  //                         .write
+		.av_read                (udp_generator_csr_read),                   //                         .read
+		.av_readdata            (udp_generator_csr_readdata),               //                         .readdata
+		.av_writedata           (udp_generator_csr_writedata),              //                         .writedata
+		.av_byteenable          (udp_generator_csr_byteenable),             //                         .byteenable
+		.av_begintransfer       (),                                         //              (terminated)
+		.av_beginbursttransfer  (),                                         //              (terminated)
+		.av_burstcount          (),                                         //              (terminated)
+		.av_readdatavalid       (1'b0),                                     //              (terminated)
+		.av_waitrequest         (1'b0),                                     //              (terminated)
+		.av_writebyteenable     (),                                         //              (terminated)
+		.av_lock                (),                                         //              (terminated)
+		.av_chipselect          (),                                         //              (terminated)
+		.av_clken               (),                                         //              (terminated)
+		.uav_clken              (1'b0),                                     //              (terminated)
+		.av_debugaccess         (),                                         //              (terminated)
+		.av_outputenable        (),                                         //              (terminated)
+		.uav_response           (),                                         //              (terminated)
+		.av_response            (2'b00),                                    //              (terminated)
+		.uav_writeresponsevalid (),                                         //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                      //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (2),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sensor_interface_csr_translator (
+		.clk                    (sys_clk_clk_clk),                             //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),       //                    reset.reset
+		.uav_address            (sensor_interface_csr_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (sensor_interface_csr_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (sensor_interface_csr_agent_m0_read),          //                         .read
+		.uav_write              (sensor_interface_csr_agent_m0_write),         //                         .write
+		.uav_waitrequest        (sensor_interface_csr_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (sensor_interface_csr_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (sensor_interface_csr_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (sensor_interface_csr_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (sensor_interface_csr_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (sensor_interface_csr_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (sensor_interface_csr_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (sensor_interface_csr_address),                //      avalon_anti_slave_0.address
+		.av_write               (sensor_interface_csr_write),                  //                         .write
+		.av_read                (sensor_interface_csr_read),                   //                         .read
+		.av_readdata            (sensor_interface_csr_readdata),               //                         .readdata
+		.av_writedata           (sensor_interface_csr_writedata),              //                         .writedata
+		.av_byteenable          (sensor_interface_csr_byteenable),             //                         .byteenable
+		.av_begintransfer       (),                                            //              (terminated)
+		.av_beginbursttransfer  (),                                            //              (terminated)
+		.av_burstcount          (),                                            //              (terminated)
+		.av_readdatavalid       (1'b0),                                        //              (terminated)
+		.av_waitrequest         (1'b0),                                        //              (terminated)
+		.av_writebyteenable     (),                                            //              (terminated)
+		.av_lock                (),                                            //              (terminated)
+		.av_chipselect          (),                                            //              (terminated)
+		.av_clken               (),                                            //              (terminated)
+		.uav_clken              (1'b0),                                        //              (terminated)
+		.av_debugaccess         (),                                            //              (terminated)
+		.av_outputenable        (),                                            //              (terminated)
+		.uav_response           (),                                            //              (terminated)
+		.av_response            (2'b00),                                       //              (terminated)
+		.uav_writeresponsevalid (),                                            //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                         //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (19),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (4),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (6),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (1),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) onchip_flash_data_translator (
+		.clk                    (sys_clk_clk_clk),                          //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),    //                    reset.reset
+		.uav_address            (onchip_flash_data_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (onchip_flash_data_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (onchip_flash_data_agent_m0_read),          //                         .read
+		.uav_write              (onchip_flash_data_agent_m0_write),         //                         .write
+		.uav_waitrequest        (onchip_flash_data_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (onchip_flash_data_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (onchip_flash_data_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (onchip_flash_data_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (onchip_flash_data_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (onchip_flash_data_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (onchip_flash_data_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (onchip_flash_data_address),                //      avalon_anti_slave_0.address
+		.av_write               (onchip_flash_data_write),                  //                         .write
+		.av_read                (onchip_flash_data_read),                   //                         .read
+		.av_readdata            (onchip_flash_data_readdata),               //                         .readdata
+		.av_writedata           (onchip_flash_data_writedata),              //                         .writedata
+		.av_burstcount          (onchip_flash_data_burstcount),             //                         .burstcount
+		.av_readdatavalid       (onchip_flash_data_readdatavalid),          //                         .readdatavalid
+		.av_waitrequest         (onchip_flash_data_waitrequest),            //                         .waitrequest
+		.av_begintransfer       (),                                         //              (terminated)
+		.av_beginbursttransfer  (),                                         //              (terminated)
+		.av_byteenable          (),                                         //              (terminated)
+		.av_writebyteenable     (),                                         //              (terminated)
+		.av_lock                (),                                         //              (terminated)
+		.av_chipselect          (),                                         //              (terminated)
+		.av_clken               (),                                         //              (terminated)
+		.uav_clken              (1'b0),                                     //              (terminated)
+		.av_debugaccess         (),                                         //              (terminated)
+		.av_outputenable        (),                                         //              (terminated)
+		.uav_response           (),                                         //              (terminated)
+		.av_response            (2'b00),                                    //              (terminated)
+		.uav_writeresponsevalid (),                                         //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                      //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (9),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) cpu_debug_mem_slave_translator (
+		.clk                    (sys_clk_clk_clk),                            //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),      //                    reset.reset
+		.uav_address            (cpu_debug_mem_slave_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (cpu_debug_mem_slave_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (cpu_debug_mem_slave_agent_m0_read),          //                         .read
+		.uav_write              (cpu_debug_mem_slave_agent_m0_write),         //                         .write
+		.uav_waitrequest        (cpu_debug_mem_slave_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (cpu_debug_mem_slave_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (cpu_debug_mem_slave_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (cpu_debug_mem_slave_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (cpu_debug_mem_slave_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (cpu_debug_mem_slave_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (cpu_debug_mem_slave_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (cpu_debug_mem_slave_address),                //      avalon_anti_slave_0.address
+		.av_write               (cpu_debug_mem_slave_write),                  //                         .write
+		.av_read                (cpu_debug_mem_slave_read),                   //                         .read
+		.av_readdata            (cpu_debug_mem_slave_readdata),               //                         .readdata
+		.av_writedata           (cpu_debug_mem_slave_writedata),              //                         .writedata
+		.av_byteenable          (cpu_debug_mem_slave_byteenable),             //                         .byteenable
+		.av_waitrequest         (cpu_debug_mem_slave_waitrequest),            //                         .waitrequest
+		.av_debugaccess         (cpu_debug_mem_slave_debugaccess),            //                         .debugaccess
+		.av_begintransfer       (),                                           //              (terminated)
+		.av_beginbursttransfer  (),                                           //              (terminated)
+		.av_burstcount          (),                                           //              (terminated)
+		.av_readdatavalid       (1'b0),                                       //              (terminated)
+		.av_writebyteenable     (),                                           //              (terminated)
+		.av_lock                (),                                           //              (terminated)
+		.av_chipselect          (),                                           //              (terminated)
+		.av_clken               (),                                           //              (terminated)
+		.uav_clken              (1'b0),                                       //              (terminated)
+		.av_outputenable        (),                                           //              (terminated)
+		.uav_response           (),                                           //              (terminated)
+		.av_response            (2'b00),                                      //              (terminated)
+		.uav_writeresponsevalid (),                                           //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                        //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) msgdma_tx_prefetcher_csr_translator (
+		.clk                    (sys_clk_clk_clk),                                 //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),           //                    reset.reset
+		.uav_address            (msgdma_tx_prefetcher_csr_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (msgdma_tx_prefetcher_csr_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (msgdma_tx_prefetcher_csr_agent_m0_read),          //                         .read
+		.uav_write              (msgdma_tx_prefetcher_csr_agent_m0_write),         //                         .write
+		.uav_waitrequest        (msgdma_tx_prefetcher_csr_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (msgdma_tx_prefetcher_csr_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (msgdma_tx_prefetcher_csr_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (msgdma_tx_prefetcher_csr_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (msgdma_tx_prefetcher_csr_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (msgdma_tx_prefetcher_csr_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (msgdma_tx_prefetcher_csr_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (msgdma_tx_prefetcher_csr_address),                //      avalon_anti_slave_0.address
+		.av_write               (msgdma_tx_prefetcher_csr_write),                  //                         .write
+		.av_read                (msgdma_tx_prefetcher_csr_read),                   //                         .read
+		.av_readdata            (msgdma_tx_prefetcher_csr_readdata),               //                         .readdata
+		.av_writedata           (msgdma_tx_prefetcher_csr_writedata),              //                         .writedata
+		.av_begintransfer       (),                                                //              (terminated)
+		.av_beginbursttransfer  (),                                                //              (terminated)
+		.av_burstcount          (),                                                //              (terminated)
+		.av_byteenable          (),                                                //              (terminated)
+		.av_readdatavalid       (1'b0),                                            //              (terminated)
+		.av_waitrequest         (1'b0),                                            //              (terminated)
+		.av_writebyteenable     (),                                                //              (terminated)
+		.av_lock                (),                                                //              (terminated)
+		.av_chipselect          (),                                                //              (terminated)
+		.av_clken               (),                                                //              (terminated)
+		.uav_clken              (1'b0),                                            //              (terminated)
+		.av_debugaccess         (),                                                //              (terminated)
+		.av_outputenable        (),                                                //              (terminated)
+		.uav_response           (),                                                //              (terminated)
+		.av_response            (2'b00),                                           //              (terminated)
+		.uav_writeresponsevalid (),                                                //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) msgdma_rx_prefetcher_csr_translator (
+		.clk                    (sys_clk_clk_clk),                                 //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),           //                    reset.reset
+		.uav_address            (msgdma_rx_prefetcher_csr_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (msgdma_rx_prefetcher_csr_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (msgdma_rx_prefetcher_csr_agent_m0_read),          //                         .read
+		.uav_write              (msgdma_rx_prefetcher_csr_agent_m0_write),         //                         .write
+		.uav_waitrequest        (msgdma_rx_prefetcher_csr_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (msgdma_rx_prefetcher_csr_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (msgdma_rx_prefetcher_csr_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (msgdma_rx_prefetcher_csr_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (msgdma_rx_prefetcher_csr_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (msgdma_rx_prefetcher_csr_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (msgdma_rx_prefetcher_csr_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (msgdma_rx_prefetcher_csr_address),                //      avalon_anti_slave_0.address
+		.av_write               (msgdma_rx_prefetcher_csr_write),                  //                         .write
+		.av_read                (msgdma_rx_prefetcher_csr_read),                   //                         .read
+		.av_readdata            (msgdma_rx_prefetcher_csr_readdata),               //                         .readdata
+		.av_writedata           (msgdma_rx_prefetcher_csr_writedata),              //                         .writedata
+		.av_begintransfer       (),                                                //              (terminated)
+		.av_beginbursttransfer  (),                                                //              (terminated)
+		.av_burstcount          (),                                                //              (terminated)
+		.av_byteenable          (),                                                //              (terminated)
+		.av_readdatavalid       (1'b0),                                            //              (terminated)
+		.av_waitrequest         (1'b0),                                            //              (terminated)
+		.av_writebyteenable     (),                                                //              (terminated)
+		.av_lock                (),                                                //              (terminated)
+		.av_chipselect          (),                                                //              (terminated)
+		.av_clken               (),                                                //              (terminated)
+		.uav_clken              (1'b0),                                            //              (terminated)
+		.av_debugaccess         (),                                                //              (terminated)
+		.av_outputenable        (),                                                //              (terminated)
+		.uav_response           (),                                                //              (terminated)
+		.av_response            (2'b00),                                           //              (terminated)
+		.uav_writeresponsevalid (),                                                //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (11),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) descriptor_memory_s1_translator (
+		.clk                    (sys_clk_clk_clk),                                      //                      clk.clk
+		.reset                  (eth_tse_reset_connection_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (descriptor_memory_s1_agent_m0_address),                // avalon_universal_slave_0.address
+		.uav_burstcount         (descriptor_memory_s1_agent_m0_burstcount),             //                         .burstcount
+		.uav_read               (descriptor_memory_s1_agent_m0_read),                   //                         .read
+		.uav_write              (descriptor_memory_s1_agent_m0_write),                  //                         .write
+		.uav_waitrequest        (descriptor_memory_s1_agent_m0_waitrequest),            //                         .waitrequest
+		.uav_readdatavalid      (descriptor_memory_s1_agent_m0_readdatavalid),          //                         .readdatavalid
+		.uav_byteenable         (descriptor_memory_s1_agent_m0_byteenable),             //                         .byteenable
+		.uav_readdata           (descriptor_memory_s1_agent_m0_readdata),               //                         .readdata
+		.uav_writedata          (descriptor_memory_s1_agent_m0_writedata),              //                         .writedata
+		.uav_lock               (descriptor_memory_s1_agent_m0_lock),                   //                         .lock
+		.uav_debugaccess        (descriptor_memory_s1_agent_m0_debugaccess),            //                         .debugaccess
+		.av_address             (descriptor_memory_s1_address),                         //      avalon_anti_slave_0.address
+		.av_write               (descriptor_memory_s1_write),                           //                         .write
+		.av_readdata            (descriptor_memory_s1_readdata),                        //                         .readdata
+		.av_writedata           (descriptor_memory_s1_writedata),                       //                         .writedata
+		.av_byteenable          (descriptor_memory_s1_byteenable),                      //                         .byteenable
+		.av_chipselect          (descriptor_memory_s1_chipselect),                      //                         .chipselect
+		.av_clken               (descriptor_memory_s1_clken),                           //                         .clken
+		.av_read                (),                                                     //              (terminated)
+		.av_begintransfer       (),                                                     //              (terminated)
+		.av_beginbursttransfer  (),                                                     //              (terminated)
+		.av_burstcount          (),                                                     //              (terminated)
+		.av_readdatavalid       (1'b0),                                                 //              (terminated)
+		.av_waitrequest         (1'b0),                                                 //              (terminated)
+		.av_writebyteenable     (),                                                     //              (terminated)
+		.av_lock                (),                                                     //              (terminated)
+		.uav_clken              (1'b0),                                                 //              (terminated)
+		.av_debugaccess         (),                                                     //              (terminated)
+		.av_outputenable        (),                                                     //              (terminated)
+		.uav_response           (),                                                     //              (terminated)
+		.av_response            (2'b00),                                                //              (terminated)
+		.uav_writeresponsevalid (),                                                     //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                  //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) sys_clk_timer_s1_translator (
+		.clk                    (sys_clk_clk_clk),                                      //                      clk.clk
+		.reset                  (eth_tse_reset_connection_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (sys_clk_timer_s1_agent_m0_address),                    // avalon_universal_slave_0.address
+		.uav_burstcount         (sys_clk_timer_s1_agent_m0_burstcount),                 //                         .burstcount
+		.uav_read               (sys_clk_timer_s1_agent_m0_read),                       //                         .read
+		.uav_write              (sys_clk_timer_s1_agent_m0_write),                      //                         .write
+		.uav_waitrequest        (sys_clk_timer_s1_agent_m0_waitrequest),                //                         .waitrequest
+		.uav_readdatavalid      (sys_clk_timer_s1_agent_m0_readdatavalid),              //                         .readdatavalid
+		.uav_byteenable         (sys_clk_timer_s1_agent_m0_byteenable),                 //                         .byteenable
+		.uav_readdata           (sys_clk_timer_s1_agent_m0_readdata),                   //                         .readdata
+		.uav_writedata          (sys_clk_timer_s1_agent_m0_writedata),                  //                         .writedata
+		.uav_lock               (sys_clk_timer_s1_agent_m0_lock),                       //                         .lock
+		.uav_debugaccess        (sys_clk_timer_s1_agent_m0_debugaccess),                //                         .debugaccess
+		.av_address             (sys_clk_timer_s1_address),                             //      avalon_anti_slave_0.address
+		.av_write               (sys_clk_timer_s1_write),                               //                         .write
+		.av_readdata            (sys_clk_timer_s1_readdata),                            //                         .readdata
+		.av_writedata           (sys_clk_timer_s1_writedata),                           //                         .writedata
+		.av_chipselect          (sys_clk_timer_s1_chipselect),                          //                         .chipselect
+		.av_read                (),                                                     //              (terminated)
+		.av_begintransfer       (),                                                     //              (terminated)
+		.av_beginbursttransfer  (),                                                     //              (terminated)
+		.av_burstcount          (),                                                     //              (terminated)
+		.av_byteenable          (),                                                     //              (terminated)
+		.av_readdatavalid       (1'b0),                                                 //              (terminated)
+		.av_waitrequest         (1'b0),                                                 //              (terminated)
+		.av_writebyteenable     (),                                                     //              (terminated)
+		.av_lock                (),                                                     //              (terminated)
+		.av_clken               (),                                                     //              (terminated)
+		.uav_clken              (1'b0),                                                 //              (terminated)
+		.av_debugaccess         (),                                                     //              (terminated)
+		.av_outputenable        (),                                                     //              (terminated)
+		.uav_response           (),                                                     //              (terminated)
+		.av_response            (2'b00),                                                //              (terminated)
+		.uav_writeresponsevalid (),                                                     //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                  //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) output_pio_s1_translator (
+		.clk                    (sys_clk_clk_clk),                                      //                      clk.clk
+		.reset                  (eth_tse_reset_connection_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (output_pio_s1_agent_m0_address),                       // avalon_universal_slave_0.address
+		.uav_burstcount         (output_pio_s1_agent_m0_burstcount),                    //                         .burstcount
+		.uav_read               (output_pio_s1_agent_m0_read),                          //                         .read
+		.uav_write              (output_pio_s1_agent_m0_write),                         //                         .write
+		.uav_waitrequest        (output_pio_s1_agent_m0_waitrequest),                   //                         .waitrequest
+		.uav_readdatavalid      (output_pio_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
+		.uav_byteenable         (output_pio_s1_agent_m0_byteenable),                    //                         .byteenable
+		.uav_readdata           (output_pio_s1_agent_m0_readdata),                      //                         .readdata
+		.uav_writedata          (output_pio_s1_agent_m0_writedata),                     //                         .writedata
+		.uav_lock               (output_pio_s1_agent_m0_lock),                          //                         .lock
+		.uav_debugaccess        (output_pio_s1_agent_m0_debugaccess),                   //                         .debugaccess
+		.av_address             (output_pio_s1_address),                                //      avalon_anti_slave_0.address
+		.av_write               (output_pio_s1_write),                                  //                         .write
+		.av_readdata            (output_pio_s1_readdata),                               //                         .readdata
+		.av_writedata           (output_pio_s1_writedata),                              //                         .writedata
+		.av_chipselect          (output_pio_s1_chipselect),                             //                         .chipselect
+		.av_read                (),                                                     //              (terminated)
+		.av_begintransfer       (),                                                     //              (terminated)
+		.av_beginbursttransfer  (),                                                     //              (terminated)
+		.av_burstcount          (),                                                     //              (terminated)
+		.av_byteenable          (),                                                     //              (terminated)
+		.av_readdatavalid       (1'b0),                                                 //              (terminated)
+		.av_waitrequest         (1'b0),                                                 //              (terminated)
+		.av_writebyteenable     (),                                                     //              (terminated)
+		.av_lock                (),                                                     //              (terminated)
+		.av_clken               (),                                                     //              (terminated)
+		.uav_clken              (1'b0),                                                 //              (terminated)
+		.av_debugaccess         (),                                                     //              (terminated)
+		.av_outputenable        (),                                                     //              (terminated)
+		.uav_response           (),                                                     //              (terminated)
+		.av_response            (2'b00),                                                //              (terminated)
+		.uav_writeresponsevalid (),                                                     //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                  //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (2),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) button_pio_s1_translator (
+		.clk                    (sys_clk_clk_clk),                       //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (button_pio_s1_agent_m0_address),        // avalon_universal_slave_0.address
+		.uav_burstcount         (button_pio_s1_agent_m0_burstcount),     //                         .burstcount
+		.uav_read               (button_pio_s1_agent_m0_read),           //                         .read
+		.uav_write              (button_pio_s1_agent_m0_write),          //                         .write
+		.uav_waitrequest        (button_pio_s1_agent_m0_waitrequest),    //                         .waitrequest
+		.uav_readdatavalid      (button_pio_s1_agent_m0_readdatavalid),  //                         .readdatavalid
+		.uav_byteenable         (button_pio_s1_agent_m0_byteenable),     //                         .byteenable
+		.uav_readdata           (button_pio_s1_agent_m0_readdata),       //                         .readdata
+		.uav_writedata          (button_pio_s1_agent_m0_writedata),      //                         .writedata
+		.uav_lock               (button_pio_s1_agent_m0_lock),           //                         .lock
+		.uav_debugaccess        (button_pio_s1_agent_m0_debugaccess),    //                         .debugaccess
+		.av_address             (button_pio_s1_address),                 //      avalon_anti_slave_0.address
+		.av_readdata            (button_pio_s1_readdata),                //                         .readdata
+		.av_write               (),                                      //              (terminated)
+		.av_read                (),                                      //              (terminated)
+		.av_writedata           (),                                      //              (terminated)
+		.av_begintransfer       (),                                      //              (terminated)
+		.av_beginbursttransfer  (),                                      //              (terminated)
+		.av_burstcount          (),                                      //              (terminated)
+		.av_byteenable          (),                                      //              (terminated)
+		.av_readdatavalid       (1'b0),                                  //              (terminated)
+		.av_waitrequest         (1'b0),                                  //              (terminated)
+		.av_writebyteenable     (),                                      //              (terminated)
+		.av_lock                (),                                      //              (terminated)
+		.av_chipselect          (),                                      //              (terminated)
+		.av_clken               (),                                      //              (terminated)
+		.uav_clken              (1'b0),                                  //              (terminated)
+		.av_debugaccess         (),                                      //              (terminated)
+		.av_outputenable        (),                                      //              (terminated)
+		.uav_response           (),                                      //              (terminated)
+		.av_response            (2'b00),                                 //              (terminated)
+		.uav_writeresponsevalid (),                                      //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (1),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) debug_uart_s1_translator (
+		.clk                    (sys_clk_clk_clk),                       //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (debug_uart_s1_agent_m0_address),        // avalon_universal_slave_0.address
+		.uav_burstcount         (debug_uart_s1_agent_m0_burstcount),     //                         .burstcount
+		.uav_read               (debug_uart_s1_agent_m0_read),           //                         .read
+		.uav_write              (debug_uart_s1_agent_m0_write),          //                         .write
+		.uav_waitrequest        (debug_uart_s1_agent_m0_waitrequest),    //                         .waitrequest
+		.uav_readdatavalid      (debug_uart_s1_agent_m0_readdatavalid),  //                         .readdatavalid
+		.uav_byteenable         (debug_uart_s1_agent_m0_byteenable),     //                         .byteenable
+		.uav_readdata           (debug_uart_s1_agent_m0_readdata),       //                         .readdata
+		.uav_writedata          (debug_uart_s1_agent_m0_writedata),      //                         .writedata
+		.uav_lock               (debug_uart_s1_agent_m0_lock),           //                         .lock
+		.uav_debugaccess        (debug_uart_s1_agent_m0_debugaccess),    //                         .debugaccess
+		.av_address             (debug_uart_s1_address),                 //      avalon_anti_slave_0.address
+		.av_write               (debug_uart_s1_write),                   //                         .write
+		.av_read                (debug_uart_s1_read),                    //                         .read
+		.av_readdata            (debug_uart_s1_readdata),                //                         .readdata
+		.av_writedata           (debug_uart_s1_writedata),               //                         .writedata
+		.av_begintransfer       (debug_uart_s1_begintransfer),           //                         .begintransfer
+		.av_chipselect          (debug_uart_s1_chipselect),              //                         .chipselect
+		.av_beginbursttransfer  (),                                      //              (terminated)
+		.av_burstcount          (),                                      //              (terminated)
+		.av_byteenable          (),                                      //              (terminated)
+		.av_readdatavalid       (1'b0),                                  //              (terminated)
+		.av_waitrequest         (1'b0),                                  //              (terminated)
+		.av_writebyteenable     (),                                      //              (terminated)
+		.av_lock                (),                                      //              (terminated)
+		.av_clken               (),                                      //              (terminated)
+		.uav_clken              (1'b0),                                  //              (terminated)
+		.av_debugaccess         (),                                      //              (terminated)
+		.av_outputenable        (),                                      //              (terminated)
+		.uav_response           (),                                      //              (terminated)
+		.av_response            (2'b00),                                 //              (terminated)
+		.uav_writeresponsevalid (),                                      //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (3),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) frame_timer_s1_translator (
+		.clk                    (sys_clk_clk_clk),                       //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (frame_timer_s1_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (frame_timer_s1_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (frame_timer_s1_agent_m0_read),          //                         .read
+		.uav_write              (frame_timer_s1_agent_m0_write),         //                         .write
+		.uav_waitrequest        (frame_timer_s1_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (frame_timer_s1_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (frame_timer_s1_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (frame_timer_s1_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (frame_timer_s1_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (frame_timer_s1_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (frame_timer_s1_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (frame_timer_s1_address),                //      avalon_anti_slave_0.address
+		.av_write               (frame_timer_s1_write),                  //                         .write
+		.av_readdata            (frame_timer_s1_readdata),               //                         .readdata
+		.av_writedata           (frame_timer_s1_writedata),              //                         .writedata
+		.av_chipselect          (frame_timer_s1_chipselect),             //                         .chipselect
+		.av_read                (),                                      //              (terminated)
+		.av_begintransfer       (),                                      //              (terminated)
+		.av_beginbursttransfer  (),                                      //              (terminated)
+		.av_burstcount          (),                                      //              (terminated)
+		.av_byteenable          (),                                      //              (terminated)
+		.av_readdatavalid       (1'b0),                                  //              (terminated)
+		.av_waitrequest         (1'b0),                                  //              (terminated)
+		.av_writebyteenable     (),                                      //              (terminated)
+		.av_lock                (),                                      //              (terminated)
+		.av_clken               (),                                      //              (terminated)
+		.uav_clken              (1'b0),                                  //              (terminated)
+		.av_debugaccess         (),                                      //              (terminated)
+		.av_outputenable        (),                                      //              (terminated)
+		.uav_response           (),                                      //              (terminated)
+		.av_response            (2'b00),                                 //              (terminated)
+		.uav_writeresponsevalid (),                                      //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                   //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (9),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (16),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (2),
+		.UAV_BYTEENABLE_W               (2),
+		.UAV_ADDRESS_W                  (29),
+		.UAV_BURSTCOUNT_W               (2),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (2),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) calibration_ram_s1_translator (
+		.clk                    (sys_clk_clk_clk),                           //                      clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),     //                    reset.reset
+		.uav_address            (calibration_ram_s1_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (calibration_ram_s1_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (calibration_ram_s1_agent_m0_read),          //                         .read
+		.uav_write              (calibration_ram_s1_agent_m0_write),         //                         .write
+		.uav_waitrequest        (calibration_ram_s1_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (calibration_ram_s1_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (calibration_ram_s1_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (calibration_ram_s1_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (calibration_ram_s1_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (calibration_ram_s1_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (calibration_ram_s1_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (calibration_ram_s1_address),                //      avalon_anti_slave_0.address
+		.av_write               (calibration_ram_s1_write),                  //                         .write
+		.av_readdata            (calibration_ram_s1_readdata),               //                         .readdata
+		.av_writedata           (calibration_ram_s1_writedata),              //                         .writedata
+		.av_byteenable          (calibration_ram_s1_byteenable),             //                         .byteenable
+		.av_chipselect          (calibration_ram_s1_chipselect),             //                         .chipselect
+		.av_clken               (calibration_ram_s1_clken),                  //                         .clken
+		.av_read                (),                                          //              (terminated)
+		.av_begintransfer       (),                                          //              (terminated)
+		.av_beginbursttransfer  (),                                          //              (terminated)
+		.av_burstcount          (),                                          //              (terminated)
+		.av_readdatavalid       (1'b0),                                      //              (terminated)
+		.av_waitrequest         (1'b0),                                      //              (terminated)
+		.av_writebyteenable     (),                                          //              (terminated)
+		.av_lock                (),                                          //              (terminated)
+		.uav_clken              (1'b0),                                      //              (terminated)
+		.av_debugaccess         (),                                          //              (terminated)
+		.av_outputenable        (),                                          //              (terminated)
+		.uav_response           (),                                          //              (terminated)
+		.av_response            (2'b00),                                     //              (terminated)
+		.uav_writeresponsevalid (),                                          //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                       //              (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (0),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) cpu_data_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                    //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                              // clk_reset.reset
+		.av_address            (cpu_data_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (cpu_data_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (cpu_data_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (cpu_data_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (cpu_data_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (cpu_data_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (cpu_data_master_limiter_rsp_src_valid),                              //        rp.valid
+		.rp_data               (cpu_data_master_limiter_rsp_src_data),                               //          .data
+		.rp_channel            (cpu_data_master_limiter_rsp_src_channel),                            //          .channel
+		.rp_startofpacket      (cpu_data_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
+		.rp_endofpacket        (cpu_data_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
+		.rp_ready              (cpu_data_master_limiter_rsp_src_ready),                              //          .ready
+		.av_response           (),                                                                   // (terminated)
+		.av_writeresponsevalid ()                                                                    // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (1),
+		.BURSTWRAP_VALUE           (3),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) cpu_instruction_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                           //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                     // clk_reset.reset
+		.av_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (cpu_instruction_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (cpu_instruction_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (cpu_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (cpu_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (cpu_instruction_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (cpu_instruction_master_limiter_rsp_src_valid),                              //        rp.valid
+		.rp_data               (cpu_instruction_master_limiter_rsp_src_data),                               //          .data
+		.rp_channel            (cpu_instruction_master_limiter_rsp_src_channel),                            //          .channel
+		.rp_startofpacket      (cpu_instruction_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
+		.rp_endofpacket        (cpu_instruction_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
+		.rp_ready              (cpu_instruction_master_limiter_rsp_src_ready),                              //          .ready
+		.av_response           (),                                                                          // (terminated)
+		.av_writeresponsevalid ()                                                                           // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (7),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) msgdma_tx_mm_read_agent (
+		.clk                   (sys_clk_clk_clk),                                                      //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                // clk_reset.reset
+		.av_address            (msgdma_tx_mm_read_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (msgdma_tx_mm_read_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (msgdma_tx_mm_read_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (msgdma_tx_mm_read_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (msgdma_tx_mm_read_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (msgdma_tx_mm_read_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (msgdma_tx_mm_read_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (msgdma_tx_mm_read_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (msgdma_tx_mm_read_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (msgdma_tx_mm_read_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (msgdma_tx_mm_read_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (msgdma_tx_mm_read_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (msgdma_tx_mm_read_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (msgdma_tx_mm_read_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (msgdma_tx_mm_read_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (msgdma_tx_mm_read_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_002_src_valid),                                                //        rp.valid
+		.rp_data               (rsp_mux_002_src_data),                                                 //          .data
+		.rp_channel            (rsp_mux_002_src_channel),                                              //          .channel
+		.rp_startofpacket      (rsp_mux_002_src_startofpacket),                                        //          .startofpacket
+		.rp_endofpacket        (rsp_mux_002_src_endofpacket),                                          //          .endofpacket
+		.rp_ready              (rsp_mux_002_src_ready),                                                //          .ready
+		.av_response           (),                                                                     // (terminated)
+		.av_writeresponsevalid ()                                                                      // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (4),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) msgdma_rx_mm_write_agent (
+		.clk                   (sys_clk_clk_clk),                                                       //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                 // clk_reset.reset
+		.av_address            (msgdma_rx_mm_write_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (msgdma_rx_mm_write_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (msgdma_rx_mm_write_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (msgdma_rx_mm_write_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (msgdma_rx_mm_write_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (msgdma_rx_mm_write_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (msgdma_rx_mm_write_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (msgdma_rx_mm_write_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (msgdma_rx_mm_write_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (msgdma_rx_mm_write_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (msgdma_rx_mm_write_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (msgdma_rx_mm_write_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (msgdma_rx_mm_write_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (msgdma_rx_mm_write_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (msgdma_rx_mm_write_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (msgdma_rx_mm_write_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_003_src_valid),                                                 //        rp.valid
+		.rp_data               (rsp_mux_003_src_data),                                                  //          .data
+		.rp_channel            (rsp_mux_003_src_channel),                                               //          .channel
+		.rp_startofpacket      (rsp_mux_003_src_startofpacket),                                         //          .startofpacket
+		.rp_endofpacket        (rsp_mux_003_src_endofpacket),                                           //          .endofpacket
+		.rp_ready              (rsp_mux_003_src_ready),                                                 //          .ready
+		.av_response           (),                                                                      // (terminated)
+		.av_writeresponsevalid ()                                                                       // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (5),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) msgdma_tx_descriptor_read_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                                     //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
+		.av_address            (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (msgdma_tx_descriptor_read_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (msgdma_tx_descriptor_read_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (msgdma_tx_descriptor_read_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (msgdma_tx_descriptor_read_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (msgdma_tx_descriptor_read_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (msgdma_tx_descriptor_read_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_004_src_valid),                                                               //        rp.valid
+		.rp_data               (rsp_mux_004_src_data),                                                                //          .data
+		.rp_channel            (rsp_mux_004_src_channel),                                                             //          .channel
+		.rp_startofpacket      (rsp_mux_004_src_startofpacket),                                                       //          .startofpacket
+		.rp_endofpacket        (rsp_mux_004_src_endofpacket),                                                         //          .endofpacket
+		.rp_ready              (rsp_mux_004_src_ready),                                                               //          .ready
+		.av_response           (),                                                                                    // (terminated)
+		.av_writeresponsevalid ()                                                                                     // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (2),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) msgdma_rx_descriptor_read_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                                     //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
+		.av_address            (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (msgdma_rx_descriptor_read_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (msgdma_rx_descriptor_read_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (msgdma_rx_descriptor_read_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (msgdma_rx_descriptor_read_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (msgdma_rx_descriptor_read_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (msgdma_rx_descriptor_read_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_005_src_valid),                                                               //        rp.valid
+		.rp_data               (rsp_mux_005_src_data),                                                                //          .data
+		.rp_channel            (rsp_mux_005_src_channel),                                                             //          .channel
+		.rp_startofpacket      (rsp_mux_005_src_startofpacket),                                                       //          .startofpacket
+		.rp_endofpacket        (rsp_mux_005_src_endofpacket),                                                         //          .endofpacket
+		.rp_ready              (rsp_mux_005_src_ready),                                                               //          .ready
+		.av_response           (),                                                                                    // (terminated)
+		.av_writeresponsevalid ()                                                                                     // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (6),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (1),
+		.USE_WRITERESPONSE         (1)
+	) msgdma_tx_descriptor_write_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                                           //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                                     // clk_reset.reset
+		.av_address            (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_address),            //        av.address
+		.av_write              (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_write),              //          .write
+		.av_read               (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_read),               //          .read
+		.av_writedata          (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writedata),          //          .writedata
+		.av_readdata           (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdata),           //          .readdata
+		.av_waitrequest        (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest),        //          .waitrequest
+		.av_readdatavalid      (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid),      //          .readdatavalid
+		.av_byteenable         (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_byteenable),         //          .byteenable
+		.av_burstcount         (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_burstcount),         //          .burstcount
+		.av_debugaccess        (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess),        //          .debugaccess
+		.av_lock               (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_lock),               //          .lock
+		.av_response           (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_response),           //          .response
+		.av_writeresponsevalid (msgdma_tx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid), //          .writeresponsevalid
+		.cp_valid              (msgdma_tx_descriptor_write_master_agent_cp_valid),                                          //        cp.valid
+		.cp_data               (msgdma_tx_descriptor_write_master_agent_cp_data),                                           //          .data
+		.cp_startofpacket      (msgdma_tx_descriptor_write_master_agent_cp_startofpacket),                                  //          .startofpacket
+		.cp_endofpacket        (msgdma_tx_descriptor_write_master_agent_cp_endofpacket),                                    //          .endofpacket
+		.cp_ready              (msgdma_tx_descriptor_write_master_agent_cp_ready),                                          //          .ready
+		.rp_valid              (rsp_mux_006_src_valid),                                                                     //        rp.valid
+		.rp_data               (rsp_mux_006_src_data),                                                                      //          .data
+		.rp_channel            (rsp_mux_006_src_channel),                                                                   //          .channel
+		.rp_startofpacket      (rsp_mux_006_src_startofpacket),                                                             //          .startofpacket
+		.rp_endofpacket        (rsp_mux_006_src_endofpacket),                                                               //          .endofpacket
+		.rp_ready              (rsp_mux_006_src_ready)                                                                      //          .ready
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_QOS_H                 (97),
+		.PKT_QOS_L                 (97),
+		.PKT_DATA_SIDEBAND_H       (95),
+		.PKT_DATA_SIDEBAND_L       (95),
+		.PKT_ADDR_SIDEBAND_H       (94),
+		.PKT_ADDR_SIDEBAND_L       (94),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_CACHE_H               (115),
+		.PKT_CACHE_L               (112),
+		.PKT_THREAD_ID_H           (108),
+		.PKT_THREAD_ID_L           (108),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_EXCLUSIVE       (70),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (3),
+		.BURSTWRAP_VALUE           (511),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (1),
+		.USE_WRITERESPONSE         (1)
+	) msgdma_rx_descriptor_write_master_agent (
+		.clk                   (sys_clk_clk_clk),                                                                           //       clk.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                                                     // clk_reset.reset
+		.av_address            (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_address),            //        av.address
+		.av_write              (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_write),              //          .write
+		.av_read               (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_read),               //          .read
+		.av_writedata          (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writedata),          //          .writedata
+		.av_readdata           (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdata),           //          .readdata
+		.av_waitrequest        (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_waitrequest),        //          .waitrequest
+		.av_readdatavalid      (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_readdatavalid),      //          .readdatavalid
+		.av_byteenable         (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_byteenable),         //          .byteenable
+		.av_burstcount         (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_burstcount),         //          .burstcount
+		.av_debugaccess        (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_debugaccess),        //          .debugaccess
+		.av_lock               (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_lock),               //          .lock
+		.av_response           (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_response),           //          .response
+		.av_writeresponsevalid (msgdma_rx_descriptor_write_master_translator_avalon_universal_master_0_writeresponsevalid), //          .writeresponsevalid
+		.cp_valid              (msgdma_rx_descriptor_write_master_agent_cp_valid),                                          //        cp.valid
+		.cp_data               (msgdma_rx_descriptor_write_master_agent_cp_data),                                           //          .data
+		.cp_startofpacket      (msgdma_rx_descriptor_write_master_agent_cp_startofpacket),                                  //          .startofpacket
+		.cp_endofpacket        (msgdma_rx_descriptor_write_master_agent_cp_endofpacket),                                    //          .endofpacket
+		.cp_ready              (msgdma_rx_descriptor_write_master_agent_cp_ready),                                          //          .ready
+		.rp_valid              (rsp_mux_007_src_valid),                                                                     //        rp.valid
+		.rp_data               (rsp_mux_007_src_data),                                                                      //          .data
+		.rp_channel            (rsp_mux_007_src_channel),                                                                   //          .channel
+		.rp_startofpacket      (rsp_mux_007_src_startofpacket),                                                             //          .startofpacket
+		.rp_endofpacket        (rsp_mux_007_src_endofpacket),                                                               //          .endofpacket
+		.rp_ready              (rsp_mux_007_src_ready)                                                                      //          .ready
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (5),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) ddr3_ram_avl_agent (
+		.clk                     (ddr3_ram_afi_clk_clk),                                      //             clk.clk
+		.reset                   (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (ddr3_ram_avl_agent_m0_address),                             //              m0.address
+		.m0_burstcount           (ddr3_ram_avl_agent_m0_burstcount),                          //                .burstcount
+		.m0_byteenable           (ddr3_ram_avl_agent_m0_byteenable),                          //                .byteenable
+		.m0_debugaccess          (ddr3_ram_avl_agent_m0_debugaccess),                         //                .debugaccess
+		.m0_lock                 (ddr3_ram_avl_agent_m0_lock),                                //                .lock
+		.m0_readdata             (ddr3_ram_avl_agent_m0_readdata),                            //                .readdata
+		.m0_readdatavalid        (ddr3_ram_avl_agent_m0_readdatavalid),                       //                .readdatavalid
+		.m0_read                 (ddr3_ram_avl_agent_m0_read),                                //                .read
+		.m0_waitrequest          (ddr3_ram_avl_agent_m0_waitrequest),                         //                .waitrequest
+		.m0_writedata            (ddr3_ram_avl_agent_m0_writedata),                           //                .writedata
+		.m0_write                (ddr3_ram_avl_agent_m0_write),                               //                .write
+		.rp_endofpacket          (ddr3_ram_avl_agent_rp_endofpacket),                         //              rp.endofpacket
+		.rp_ready                (ddr3_ram_avl_agent_rp_ready),                               //                .ready
+		.rp_valid                (ddr3_ram_avl_agent_rp_valid),                               //                .valid
+		.rp_data                 (ddr3_ram_avl_agent_rp_data),                                //                .data
+		.rp_startofpacket        (ddr3_ram_avl_agent_rp_startofpacket),                       //                .startofpacket
+		.cp_ready                (cmd_mux_src_ready),                                         //              cp.ready
+		.cp_valid                (cmd_mux_src_valid),                                         //                .valid
+		.cp_data                 (cmd_mux_src_data),                                          //                .data
+		.cp_startofpacket        (cmd_mux_src_startofpacket),                                 //                .startofpacket
+		.cp_endofpacket          (cmd_mux_src_endofpacket),                                   //                .endofpacket
+		.cp_channel              (cmd_mux_src_channel),                                       //                .channel
+		.rf_sink_ready           (ddr3_ram_avl_agent_rsp_fifo_out_ready),                     //         rf_sink.ready
+		.rf_sink_valid           (ddr3_ram_avl_agent_rsp_fifo_out_valid),                     //                .valid
+		.rf_sink_startofpacket   (ddr3_ram_avl_agent_rsp_fifo_out_startofpacket),             //                .startofpacket
+		.rf_sink_endofpacket     (ddr3_ram_avl_agent_rsp_fifo_out_endofpacket),               //                .endofpacket
+		.rf_sink_data            (ddr3_ram_avl_agent_rsp_fifo_out_data),                      //                .data
+		.rf_source_ready         (ddr3_ram_avl_agent_rf_source_ready),                        //       rf_source.ready
+		.rf_source_valid         (ddr3_ram_avl_agent_rf_source_valid),                        //                .valid
+		.rf_source_startofpacket (ddr3_ram_avl_agent_rf_source_startofpacket),                //                .startofpacket
+		.rf_source_endofpacket   (ddr3_ram_avl_agent_rf_source_endofpacket),                  //                .endofpacket
+		.rf_source_data          (ddr3_ram_avl_agent_rf_source_data),                         //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                             // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                             //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                              //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                             //                .error
+		.rdata_fifo_src_ready    (ddr3_ram_avl_agent_rdata_fifo_src_ready),                   //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (ddr3_ram_avl_agent_rdata_fifo_src_valid),                   //                .valid
+		.rdata_fifo_src_data     (ddr3_ram_avl_agent_rdata_fifo_src_data),                    //                .data
+		.m0_response             (2'b00),                                                     //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (33),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ddr3_ram_avl_agent_rsp_fifo (
+		.clk               (ddr3_ram_afi_clk_clk),                                      //       clk.clk
+		.reset             (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (ddr3_ram_avl_agent_rf_source_data),                         //        in.data
+		.in_valid          (ddr3_ram_avl_agent_rf_source_valid),                        //          .valid
+		.in_ready          (ddr3_ram_avl_agent_rf_source_ready),                        //          .ready
+		.in_startofpacket  (ddr3_ram_avl_agent_rf_source_startofpacket),                //          .startofpacket
+		.in_endofpacket    (ddr3_ram_avl_agent_rf_source_endofpacket),                  //          .endofpacket
+		.out_data          (ddr3_ram_avl_agent_rsp_fifo_out_data),                      //       out.data
+		.out_valid         (ddr3_ram_avl_agent_rsp_fifo_out_valid),                     //          .valid
+		.out_ready         (ddr3_ram_avl_agent_rsp_fifo_out_ready),                     //          .ready
+		.out_startofpacket (ddr3_ram_avl_agent_rsp_fifo_out_startofpacket),             //          .startofpacket
+		.out_endofpacket   (ddr3_ram_avl_agent_rsp_fifo_out_endofpacket),               //          .endofpacket
+		.csr_address       (2'b00),                                                     // (terminated)
+		.csr_read          (1'b0),                                                      // (terminated)
+		.csr_write         (1'b0),                                                      // (terminated)
+		.csr_readdata      (),                                                          // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
+		.almost_full_data  (),                                                          // (terminated)
+		.almost_empty_data (),                                                          // (terminated)
+		.in_empty          (1'b0),                                                      // (terminated)
+		.out_empty         (),                                                          // (terminated)
+		.in_error          (1'b0),                                                      // (terminated)
+		.out_error         (),                                                          // (terminated)
+		.in_channel        (1'b0),                                                      // (terminated)
+		.out_channel       ()                                                           // (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (34),
+		.FIFO_DEPTH          (64),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (0),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (3),
+		.USE_MEMORY_BLOCKS   (1),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ddr3_ram_avl_agent_rdata_fifo (
+		.clk               (ddr3_ram_afi_clk_clk),                                      //       clk.clk
+		.reset             (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (ddr3_ram_avl_agent_rdata_fifo_src_data),                    //        in.data
+		.in_valid          (ddr3_ram_avl_agent_rdata_fifo_src_valid),                   //          .valid
+		.in_ready          (ddr3_ram_avl_agent_rdata_fifo_src_ready),                   //          .ready
+		.out_data          (ddr3_ram_avl_agent_rdata_fifo_out_data),                    //       out.data
+		.out_valid         (ddr3_ram_avl_agent_rdata_fifo_out_valid),                   //          .valid
+		.out_ready         (ddr3_ram_avl_agent_rdata_fifo_out_ready),                   //          .ready
+		.csr_address       (2'b00),                                                     // (terminated)
+		.csr_read          (1'b0),                                                      // (terminated)
+		.csr_write         (1'b0),                                                      // (terminated)
+		.csr_readdata      (),                                                          // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
+		.almost_full_data  (),                                                          // (terminated)
+		.almost_empty_data (),                                                          // (terminated)
+		.in_startofpacket  (1'b0),                                                      // (terminated)
+		.in_endofpacket    (1'b0),                                                      // (terminated)
+		.out_startofpacket (),                                                          // (terminated)
+		.out_endofpacket   (),                                                          // (terminated)
+		.in_empty          (1'b0),                                                      // (terminated)
+		.out_empty         (),                                                          // (terminated)
+		.in_error          (1'b0),                                                      // (terminated)
+		.out_error         (),                                                          // (terminated)
+		.in_channel        (1'b0),                                                      // (terminated)
+		.out_channel       ()                                                           // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) ext_flash_avl_csr_agent (
+		.clk                     (ext_flash_clock_bridge_out_clk_clk),                 //             clk.clk
+		.reset                   (ext_flash_reset_reset_bridge_in_reset_reset),        //       clk_reset.reset
+		.m0_address              (ext_flash_avl_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (ext_flash_avl_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (ext_flash_avl_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (ext_flash_avl_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (ext_flash_avl_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (ext_flash_avl_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (ext_flash_avl_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (ext_flash_avl_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (ext_flash_avl_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (ext_flash_avl_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (ext_flash_avl_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (ext_flash_avl_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (ext_flash_avl_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (ext_flash_avl_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (ext_flash_avl_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (ext_flash_avl_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_001_src_ready),                              //              cp.ready
+		.cp_valid                (cmd_mux_001_src_valid),                              //                .valid
+		.cp_data                 (cmd_mux_001_src_data),                               //                .data
+		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                      //                .startofpacket
+		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                        //                .endofpacket
+		.cp_channel              (cmd_mux_001_src_channel),                            //                .channel
+		.rf_sink_ready           (ext_flash_avl_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (ext_flash_avl_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (ext_flash_avl_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (ext_flash_avl_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (ext_flash_avl_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (ext_flash_avl_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (ext_flash_avl_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (ext_flash_avl_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (ext_flash_avl_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (ext_flash_avl_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                  // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                  //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                   //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                  //                .error
+		.rdata_fifo_src_ready    (ext_flash_avl_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (ext_flash_avl_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (ext_flash_avl_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                              //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ext_flash_avl_csr_agent_rsp_fifo (
+		.clk               (ext_flash_clock_bridge_out_clk_clk),                 //       clk.clk
+		.reset             (ext_flash_reset_reset_bridge_in_reset_reset),        // clk_reset.reset
+		.in_data           (ext_flash_avl_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (ext_flash_avl_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (ext_flash_avl_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (ext_flash_avl_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (ext_flash_avl_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (ext_flash_avl_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (ext_flash_avl_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (ext_flash_avl_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (ext_flash_avl_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (ext_flash_avl_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (34),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (0),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (0),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ext_flash_avl_csr_agent_rdata_fifo (
+		.clk               (ext_flash_clock_bridge_out_clk_clk),           //       clk.clk
+		.reset             (ext_flash_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.in_data           (ext_flash_avl_csr_agent_rdata_fifo_src_data),  //        in.data
+		.in_valid          (ext_flash_avl_csr_agent_rdata_fifo_src_valid), //          .valid
+		.in_ready          (ext_flash_avl_csr_agent_rdata_fifo_src_ready), //          .ready
+		.out_data          (ext_flash_avl_csr_agent_rdata_fifo_out_data),  //       out.data
+		.out_valid         (ext_flash_avl_csr_agent_rdata_fifo_out_valid), //          .valid
+		.out_ready         (ext_flash_avl_csr_agent_rdata_fifo_out_ready), //          .ready
+		.csr_address       (2'b00),                                        // (terminated)
+		.csr_read          (1'b0),                                         // (terminated)
+		.csr_write         (1'b0),                                         // (terminated)
+		.csr_readdata      (),                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
+		.almost_full_data  (),                                             // (terminated)
+		.almost_empty_data (),                                             // (terminated)
+		.in_startofpacket  (1'b0),                                         // (terminated)
+		.in_endofpacket    (1'b0),                                         // (terminated)
+		.out_startofpacket (),                                             // (terminated)
+		.out_endofpacket   (),                                             // (terminated)
+		.in_empty          (1'b0),                                         // (terminated)
+		.out_empty         (),                                             // (terminated)
+		.in_error          (1'b0),                                         // (terminated)
+		.out_error         (),                                             // (terminated)
+		.in_channel        (1'b0),                                         // (terminated)
+		.out_channel       ()                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (9),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) ext_flash_avl_mem_agent (
+		.clk                     (ext_flash_clock_bridge_out_clk_clk),                    //             clk.clk
+		.reset                   (ext_flash_reset_reset_bridge_in_reset_reset),           //       clk_reset.reset
+		.m0_address              (ext_flash_avl_mem_agent_m0_address),                    //              m0.address
+		.m0_burstcount           (ext_flash_avl_mem_agent_m0_burstcount),                 //                .burstcount
+		.m0_byteenable           (ext_flash_avl_mem_agent_m0_byteenable),                 //                .byteenable
+		.m0_debugaccess          (ext_flash_avl_mem_agent_m0_debugaccess),                //                .debugaccess
+		.m0_lock                 (ext_flash_avl_mem_agent_m0_lock),                       //                .lock
+		.m0_readdata             (ext_flash_avl_mem_agent_m0_readdata),                   //                .readdata
+		.m0_readdatavalid        (ext_flash_avl_mem_agent_m0_readdatavalid),              //                .readdatavalid
+		.m0_read                 (ext_flash_avl_mem_agent_m0_read),                       //                .read
+		.m0_waitrequest          (ext_flash_avl_mem_agent_m0_waitrequest),                //                .waitrequest
+		.m0_writedata            (ext_flash_avl_mem_agent_m0_writedata),                  //                .writedata
+		.m0_write                (ext_flash_avl_mem_agent_m0_write),                      //                .write
+		.rp_endofpacket          (ext_flash_avl_mem_agent_rp_endofpacket),                //              rp.endofpacket
+		.rp_ready                (ext_flash_avl_mem_agent_rp_ready),                      //                .ready
+		.rp_valid                (ext_flash_avl_mem_agent_rp_valid),                      //                .valid
+		.rp_data                 (ext_flash_avl_mem_agent_rp_data),                       //                .data
+		.rp_startofpacket        (ext_flash_avl_mem_agent_rp_startofpacket),              //                .startofpacket
+		.cp_ready                (ext_flash_avl_mem_burst_adapter_source0_ready),         //              cp.ready
+		.cp_valid                (ext_flash_avl_mem_burst_adapter_source0_valid),         //                .valid
+		.cp_data                 (ext_flash_avl_mem_burst_adapter_source0_data),          //                .data
+		.cp_startofpacket        (ext_flash_avl_mem_burst_adapter_source0_startofpacket), //                .startofpacket
+		.cp_endofpacket          (ext_flash_avl_mem_burst_adapter_source0_endofpacket),   //                .endofpacket
+		.cp_channel              (ext_flash_avl_mem_burst_adapter_source0_channel),       //                .channel
+		.rf_sink_ready           (ext_flash_avl_mem_agent_rsp_fifo_out_ready),            //         rf_sink.ready
+		.rf_sink_valid           (ext_flash_avl_mem_agent_rsp_fifo_out_valid),            //                .valid
+		.rf_sink_startofpacket   (ext_flash_avl_mem_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
+		.rf_sink_endofpacket     (ext_flash_avl_mem_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
+		.rf_sink_data            (ext_flash_avl_mem_agent_rsp_fifo_out_data),             //                .data
+		.rf_source_ready         (ext_flash_avl_mem_agent_rf_source_ready),               //       rf_source.ready
+		.rf_source_valid         (ext_flash_avl_mem_agent_rf_source_valid),               //                .valid
+		.rf_source_startofpacket (ext_flash_avl_mem_agent_rf_source_startofpacket),       //                .startofpacket
+		.rf_source_endofpacket   (ext_flash_avl_mem_agent_rf_source_endofpacket),         //                .endofpacket
+		.rf_source_data          (ext_flash_avl_mem_agent_rf_source_data),                //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),                     // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),                     //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                      //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),                     //                .error
+		.rdata_fifo_src_ready    (ext_flash_avl_mem_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (ext_flash_avl_mem_agent_rdata_fifo_src_valid),          //                .valid
+		.rdata_fifo_src_data     (ext_flash_avl_mem_agent_rdata_fifo_src_data),           //                .data
+		.m0_response             (2'b00),                                                 //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                   //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ext_flash_avl_mem_agent_rsp_fifo (
+		.clk               (ext_flash_clock_bridge_out_clk_clk),                 //       clk.clk
+		.reset             (ext_flash_reset_reset_bridge_in_reset_reset),        // clk_reset.reset
+		.in_data           (ext_flash_avl_mem_agent_rf_source_data),             //        in.data
+		.in_valid          (ext_flash_avl_mem_agent_rf_source_valid),            //          .valid
+		.in_ready          (ext_flash_avl_mem_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (ext_flash_avl_mem_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (ext_flash_avl_mem_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (ext_flash_avl_mem_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (ext_flash_avl_mem_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (ext_flash_avl_mem_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (ext_flash_avl_mem_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (ext_flash_avl_mem_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (34),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (0),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (0),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) ext_flash_avl_mem_agent_rdata_fifo (
+		.clk               (ext_flash_clock_bridge_out_clk_clk),           //       clk.clk
+		.reset             (ext_flash_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.in_data           (ext_flash_avl_mem_agent_rdata_fifo_src_data),  //        in.data
+		.in_valid          (ext_flash_avl_mem_agent_rdata_fifo_src_valid), //          .valid
+		.in_ready          (ext_flash_avl_mem_agent_rdata_fifo_src_ready), //          .ready
+		.out_data          (ext_flash_avl_mem_agent_rdata_fifo_out_data),  //       out.data
+		.out_valid         (ext_flash_avl_mem_agent_rdata_fifo_out_valid), //          .valid
+		.out_ready         (ext_flash_avl_mem_agent_rdata_fifo_out_ready), //          .ready
+		.csr_address       (2'b00),                                        // (terminated)
+		.csr_read          (1'b0),                                         // (terminated)
+		.csr_write         (1'b0),                                         // (terminated)
+		.csr_readdata      (),                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
+		.almost_full_data  (),                                             // (terminated)
+		.almost_empty_data (),                                             // (terminated)
+		.in_startofpacket  (1'b0),                                         // (terminated)
+		.in_endofpacket    (1'b0),                                         // (terminated)
+		.out_startofpacket (),                                             // (terminated)
+		.out_endofpacket   (),                                             // (terminated)
+		.in_empty          (1'b0),                                         // (terminated)
+		.out_empty         (),                                             // (terminated)
+		.in_error          (1'b0),                                         // (terminated)
+		.out_error         (),                                             // (terminated)
+		.in_channel        (1'b0),                                         // (terminated)
+		.out_channel       ()                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) eth_tse_control_port_agent (
+		.clk                     (sys_clk_clk_clk),                                       //             clk.clk
+		.reset                   (eth_tse_reset_connection_reset_bridge_in_reset_reset),  //       clk_reset.reset
+		.m0_address              (eth_tse_control_port_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (eth_tse_control_port_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (eth_tse_control_port_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (eth_tse_control_port_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (eth_tse_control_port_agent_m0_lock),                    //                .lock
+		.m0_readdata             (eth_tse_control_port_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (eth_tse_control_port_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (eth_tse_control_port_agent_m0_read),                    //                .read
+		.m0_waitrequest          (eth_tse_control_port_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (eth_tse_control_port_agent_m0_writedata),               //                .writedata
+		.m0_write                (eth_tse_control_port_agent_m0_write),                   //                .write
+		.rp_endofpacket          (eth_tse_control_port_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (eth_tse_control_port_agent_rp_ready),                   //                .ready
+		.rp_valid                (eth_tse_control_port_agent_rp_valid),                   //                .valid
+		.rp_data                 (eth_tse_control_port_agent_rp_data),                    //                .data
+		.rp_startofpacket        (eth_tse_control_port_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_003_src_ready),                                 //              cp.ready
+		.cp_valid                (cmd_mux_003_src_valid),                                 //                .valid
+		.cp_data                 (cmd_mux_003_src_data),                                  //                .data
+		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                         //                .startofpacket
+		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                           //                .endofpacket
+		.cp_channel              (cmd_mux_003_src_channel),                               //                .channel
+		.rf_sink_ready           (eth_tse_control_port_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (eth_tse_control_port_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (eth_tse_control_port_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (eth_tse_control_port_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (eth_tse_control_port_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (eth_tse_control_port_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (eth_tse_control_port_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (eth_tse_control_port_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (eth_tse_control_port_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (eth_tse_control_port_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                     // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                     //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                      //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                     //                .error
+		.rdata_fifo_src_ready    (eth_tse_control_port_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (eth_tse_control_port_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (eth_tse_control_port_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                 //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                   //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) eth_tse_control_port_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                       //       clk.clk
+		.reset             (eth_tse_reset_connection_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.in_data           (eth_tse_control_port_agent_rf_source_data),             //        in.data
+		.in_valid          (eth_tse_control_port_agent_rf_source_valid),            //          .valid
+		.in_ready          (eth_tse_control_port_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (eth_tse_control_port_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (eth_tse_control_port_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (eth_tse_control_port_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (eth_tse_control_port_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (eth_tse_control_port_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (eth_tse_control_port_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (eth_tse_control_port_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                 // (terminated)
+		.csr_read          (1'b0),                                                  // (terminated)
+		.csr_write         (1'b0),                                                  // (terminated)
+		.csr_readdata      (),                                                      // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
+		.almost_full_data  (),                                                      // (terminated)
+		.almost_empty_data (),                                                      // (terminated)
+		.in_empty          (1'b0),                                                  // (terminated)
+		.out_empty         (),                                                      // (terminated)
+		.in_error          (1'b0),                                                  // (terminated)
+		.out_error         (),                                                      // (terminated)
+		.in_channel        (1'b0),                                                  // (terminated)
+		.out_channel       ()                                                       // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sysid_control_slave_agent (
+		.clk                     (sys_clk_clk_clk),                                      //             clk.clk
+		.reset                   (eth_tse_reset_connection_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sysid_control_slave_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (sysid_control_slave_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (sysid_control_slave_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (sysid_control_slave_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (sysid_control_slave_agent_m0_lock),                    //                .lock
+		.m0_readdata             (sysid_control_slave_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (sysid_control_slave_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (sysid_control_slave_agent_m0_read),                    //                .read
+		.m0_waitrequest          (sysid_control_slave_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (sysid_control_slave_agent_m0_writedata),               //                .writedata
+		.m0_write                (sysid_control_slave_agent_m0_write),                   //                .write
+		.rp_endofpacket          (sysid_control_slave_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (sysid_control_slave_agent_rp_ready),                   //                .ready
+		.rp_valid                (sysid_control_slave_agent_rp_valid),                   //                .valid
+		.rp_data                 (sysid_control_slave_agent_rp_data),                    //                .data
+		.rp_startofpacket        (sysid_control_slave_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_004_src_ready),                                //              cp.ready
+		.cp_valid                (cmd_mux_004_src_valid),                                //                .valid
+		.cp_data                 (cmd_mux_004_src_data),                                 //                .data
+		.cp_startofpacket        (cmd_mux_004_src_startofpacket),                        //                .startofpacket
+		.cp_endofpacket          (cmd_mux_004_src_endofpacket),                          //                .endofpacket
+		.cp_channel              (cmd_mux_004_src_channel),                              //                .channel
+		.rf_sink_ready           (sysid_control_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (sysid_control_slave_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (sysid_control_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (sysid_control_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (sysid_control_slave_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (sysid_control_slave_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (sysid_control_slave_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (sysid_control_slave_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (sysid_control_slave_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (sysid_control_slave_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_004_out_0_ready),                    // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_004_out_0_valid),                    //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_004_out_0_data),                     //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_004_out_0_error),                    //                .error
+		.rdata_fifo_src_ready    (sysid_control_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sysid_control_slave_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (sysid_control_slave_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sysid_control_slave_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                      //       clk.clk
+		.reset             (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sysid_control_slave_agent_rf_source_data),             //        in.data
+		.in_valid          (sysid_control_slave_agent_rf_source_valid),            //          .valid
+		.in_ready          (sysid_control_slave_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (sysid_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (sysid_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (sysid_control_slave_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (sysid_control_slave_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (sysid_control_slave_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (sysid_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                // (terminated)
+		.csr_read          (1'b0),                                                 // (terminated)
+		.csr_write         (1'b0),                                                 // (terminated)
+		.csr_readdata      (),                                                     // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
+		.almost_full_data  (),                                                     // (terminated)
+		.almost_empty_data (),                                                     // (terminated)
+		.in_empty          (1'b0),                                                 // (terminated)
+		.out_empty         (),                                                     // (terminated)
+		.in_error          (1'b0),                                                 // (terminated)
+		.out_error         (),                                                     // (terminated)
+		.in_channel        (1'b0),                                                 // (terminated)
+		.out_channel       ()                                                      // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) msgdma_tx_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
+		.m0_address              (msgdma_tx_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (msgdma_tx_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (msgdma_tx_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (msgdma_tx_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (msgdma_tx_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (msgdma_tx_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (msgdma_tx_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (msgdma_tx_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (msgdma_tx_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (msgdma_tx_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (msgdma_tx_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (msgdma_tx_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (msgdma_tx_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (msgdma_tx_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (msgdma_tx_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (msgdma_tx_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_005_src_ready),                          //              cp.ready
+		.cp_valid                (cmd_mux_005_src_valid),                          //                .valid
+		.cp_data                 (cmd_mux_005_src_data),                           //                .data
+		.cp_startofpacket        (cmd_mux_005_src_startofpacket),                  //                .startofpacket
+		.cp_endofpacket          (cmd_mux_005_src_endofpacket),                    //                .endofpacket
+		.cp_channel              (cmd_mux_005_src_channel),                        //                .channel
+		.rf_sink_ready           (msgdma_tx_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (msgdma_tx_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (msgdma_tx_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (msgdma_tx_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (msgdma_tx_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (msgdma_tx_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (msgdma_tx_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (msgdma_tx_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (msgdma_tx_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (msgdma_tx_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_005_out_0_ready),              // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_005_out_0_valid),              //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_005_out_0_data),               //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_005_out_0_error),              //                .error
+		.rdata_fifo_src_ready    (msgdma_tx_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (msgdma_tx_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (msgdma_tx_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                          //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) msgdma_tx_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
+		.in_data           (msgdma_tx_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (msgdma_tx_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (msgdma_tx_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (msgdma_tx_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (msgdma_tx_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (msgdma_tx_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (msgdma_tx_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (msgdma_tx_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (msgdma_tx_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (msgdma_tx_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                          // (terminated)
+		.csr_read          (1'b0),                                           // (terminated)
+		.csr_write         (1'b0),                                           // (terminated)
+		.csr_readdata      (),                                               // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
+		.almost_full_data  (),                                               // (terminated)
+		.almost_empty_data (),                                               // (terminated)
+		.in_empty          (1'b0),                                           // (terminated)
+		.out_empty         (),                                               // (terminated)
+		.in_error          (1'b0),                                           // (terminated)
+		.out_error         (),                                               // (terminated)
+		.in_channel        (1'b0),                                           // (terminated)
+		.out_channel       ()                                                // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) msgdma_rx_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
+		.m0_address              (msgdma_rx_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (msgdma_rx_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (msgdma_rx_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (msgdma_rx_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (msgdma_rx_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (msgdma_rx_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (msgdma_rx_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (msgdma_rx_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (msgdma_rx_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (msgdma_rx_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (msgdma_rx_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (msgdma_rx_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (msgdma_rx_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (msgdma_rx_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (msgdma_rx_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (msgdma_rx_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_006_src_ready),                          //              cp.ready
+		.cp_valid                (cmd_mux_006_src_valid),                          //                .valid
+		.cp_data                 (cmd_mux_006_src_data),                           //                .data
+		.cp_startofpacket        (cmd_mux_006_src_startofpacket),                  //                .startofpacket
+		.cp_endofpacket          (cmd_mux_006_src_endofpacket),                    //                .endofpacket
+		.cp_channel              (cmd_mux_006_src_channel),                        //                .channel
+		.rf_sink_ready           (msgdma_rx_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (msgdma_rx_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (msgdma_rx_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (msgdma_rx_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (msgdma_rx_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (msgdma_rx_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (msgdma_rx_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (msgdma_rx_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (msgdma_rx_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (msgdma_rx_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_006_out_0_ready),              // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_006_out_0_valid),              //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_006_out_0_data),               //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_006_out_0_error),              //                .error
+		.rdata_fifo_src_ready    (msgdma_rx_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (msgdma_rx_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (msgdma_rx_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                          //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) msgdma_rx_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
+		.in_data           (msgdma_rx_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (msgdma_rx_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (msgdma_rx_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (msgdma_rx_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (msgdma_rx_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (msgdma_rx_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (msgdma_rx_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (msgdma_rx_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (msgdma_rx_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (msgdma_rx_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                          // (terminated)
+		.csr_read          (1'b0),                                           // (terminated)
+		.csr_write         (1'b0),                                           // (terminated)
+		.csr_readdata      (),                                               // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
+		.almost_full_data  (),                                               // (terminated)
+		.almost_empty_data (),                                               // (terminated)
+		.in_empty          (1'b0),                                           // (terminated)
+		.out_empty         (),                                               // (terminated)
+		.in_error          (1'b0),                                           // (terminated)
+		.out_error         (),                                               // (terminated)
+		.in_channel        (1'b0),                                           // (terminated)
+		.out_channel       ()                                                // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) onchip_flash_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                   //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),             //       clk_reset.reset
+		.m0_address              (onchip_flash_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (onchip_flash_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (onchip_flash_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (onchip_flash_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (onchip_flash_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (onchip_flash_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (onchip_flash_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (onchip_flash_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (onchip_flash_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (onchip_flash_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (onchip_flash_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (onchip_flash_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (onchip_flash_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (onchip_flash_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (onchip_flash_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (onchip_flash_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_007_src_ready),                             //              cp.ready
+		.cp_valid                (cmd_mux_007_src_valid),                             //                .valid
+		.cp_data                 (cmd_mux_007_src_data),                              //                .data
+		.cp_startofpacket        (cmd_mux_007_src_startofpacket),                     //                .startofpacket
+		.cp_endofpacket          (cmd_mux_007_src_endofpacket),                       //                .endofpacket
+		.cp_channel              (cmd_mux_007_src_channel),                           //                .channel
+		.rf_sink_ready           (onchip_flash_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (onchip_flash_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (onchip_flash_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (onchip_flash_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (onchip_flash_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (onchip_flash_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (onchip_flash_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (onchip_flash_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (onchip_flash_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (onchip_flash_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_007_out_0_ready),                 // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_007_out_0_valid),                 //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_007_out_0_data),                  //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_007_out_0_error),                 //                .error
+		.rdata_fifo_src_ready    (onchip_flash_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (onchip_flash_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (onchip_flash_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                             //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                               //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) onchip_flash_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                   //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),             // clk_reset.reset
+		.in_data           (onchip_flash_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (onchip_flash_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (onchip_flash_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (onchip_flash_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (onchip_flash_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (onchip_flash_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (onchip_flash_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (onchip_flash_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (onchip_flash_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (onchip_flash_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                             // (terminated)
+		.csr_read          (1'b0),                                              // (terminated)
+		.csr_write         (1'b0),                                              // (terminated)
+		.csr_readdata      (),                                                  // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated)
+		.almost_full_data  (),                                                  // (terminated)
+		.almost_empty_data (),                                                  // (terminated)
+		.in_empty          (1'b0),                                              // (terminated)
+		.out_empty         (),                                                  // (terminated)
+		.in_error          (1'b0),                                              // (terminated)
+		.out_error         (),                                                  // (terminated)
+		.in_channel        (1'b0),                                              // (terminated)
+		.out_channel       ()                                                   // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) udp_generator_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                    //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),              //       clk_reset.reset
+		.m0_address              (udp_generator_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (udp_generator_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (udp_generator_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (udp_generator_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (udp_generator_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (udp_generator_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (udp_generator_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (udp_generator_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (udp_generator_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (udp_generator_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (udp_generator_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (udp_generator_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (udp_generator_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (udp_generator_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (udp_generator_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (udp_generator_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_008_src_ready),                              //              cp.ready
+		.cp_valid                (cmd_mux_008_src_valid),                              //                .valid
+		.cp_data                 (cmd_mux_008_src_data),                               //                .data
+		.cp_startofpacket        (cmd_mux_008_src_startofpacket),                      //                .startofpacket
+		.cp_endofpacket          (cmd_mux_008_src_endofpacket),                        //                .endofpacket
+		.cp_channel              (cmd_mux_008_src_channel),                            //                .channel
+		.rf_sink_ready           (udp_generator_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (udp_generator_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (udp_generator_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (udp_generator_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (udp_generator_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (udp_generator_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (udp_generator_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (udp_generator_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (udp_generator_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (udp_generator_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_008_out_0_ready),                  // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_008_out_0_valid),                  //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_008_out_0_data),                   //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_008_out_0_error),                  //                .error
+		.rdata_fifo_src_ready    (udp_generator_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (udp_generator_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (udp_generator_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                              //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) udp_generator_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                    //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
+		.in_data           (udp_generator_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (udp_generator_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (udp_generator_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (udp_generator_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (udp_generator_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (udp_generator_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (udp_generator_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (udp_generator_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (udp_generator_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (udp_generator_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sensor_interface_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                       //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                 //       clk_reset.reset
+		.m0_address              (sensor_interface_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (sensor_interface_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (sensor_interface_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (sensor_interface_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (sensor_interface_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (sensor_interface_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (sensor_interface_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (sensor_interface_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (sensor_interface_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (sensor_interface_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (sensor_interface_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (sensor_interface_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (sensor_interface_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (sensor_interface_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (sensor_interface_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (sensor_interface_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_009_src_ready),                                 //              cp.ready
+		.cp_valid                (cmd_mux_009_src_valid),                                 //                .valid
+		.cp_data                 (cmd_mux_009_src_data),                                  //                .data
+		.cp_startofpacket        (cmd_mux_009_src_startofpacket),                         //                .startofpacket
+		.cp_endofpacket          (cmd_mux_009_src_endofpacket),                           //                .endofpacket
+		.cp_channel              (cmd_mux_009_src_channel),                               //                .channel
+		.rf_sink_ready           (sensor_interface_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (sensor_interface_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (sensor_interface_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (sensor_interface_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (sensor_interface_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (sensor_interface_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (sensor_interface_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (sensor_interface_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (sensor_interface_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (sensor_interface_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_009_out_0_ready),                     // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_009_out_0_valid),                     //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_009_out_0_data),                      //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_009_out_0_error),                     //                .error
+		.rdata_fifo_src_ready    (sensor_interface_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sensor_interface_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (sensor_interface_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                 //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                   //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sensor_interface_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                       //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),                 // clk_reset.reset
+		.in_data           (sensor_interface_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (sensor_interface_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (sensor_interface_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (sensor_interface_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (sensor_interface_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (sensor_interface_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (sensor_interface_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (sensor_interface_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (sensor_interface_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (sensor_interface_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                 // (terminated)
+		.csr_read          (1'b0),                                                  // (terminated)
+		.csr_write         (1'b0),                                                  // (terminated)
+		.csr_readdata      (),                                                      // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
+		.almost_full_data  (),                                                      // (terminated)
+		.almost_empty_data (),                                                      // (terminated)
+		.in_empty          (1'b0),                                                  // (terminated)
+		.out_empty         (),                                                      // (terminated)
+		.in_error          (1'b0),                                                  // (terminated)
+		.out_error         (),                                                      // (terminated)
+		.in_channel        (1'b0),                                                  // (terminated)
+		.out_channel       ()                                                       // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (6),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) onchip_flash_data_agent (
+		.clk                     (sys_clk_clk_clk),                                    //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),              //       clk_reset.reset
+		.m0_address              (onchip_flash_data_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (onchip_flash_data_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (onchip_flash_data_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (onchip_flash_data_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (onchip_flash_data_agent_m0_lock),                    //                .lock
+		.m0_readdata             (onchip_flash_data_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (onchip_flash_data_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (onchip_flash_data_agent_m0_read),                    //                .read
+		.m0_waitrequest          (onchip_flash_data_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (onchip_flash_data_agent_m0_writedata),               //                .writedata
+		.m0_write                (onchip_flash_data_agent_m0_write),                   //                .write
+		.rp_endofpacket          (onchip_flash_data_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (onchip_flash_data_agent_rp_ready),                   //                .ready
+		.rp_valid                (onchip_flash_data_agent_rp_valid),                   //                .valid
+		.rp_data                 (onchip_flash_data_agent_rp_data),                    //                .data
+		.rp_startofpacket        (onchip_flash_data_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_010_src_ready),                              //              cp.ready
+		.cp_valid                (cmd_mux_010_src_valid),                              //                .valid
+		.cp_data                 (cmd_mux_010_src_data),                               //                .data
+		.cp_startofpacket        (cmd_mux_010_src_startofpacket),                      //                .startofpacket
+		.cp_endofpacket          (cmd_mux_010_src_endofpacket),                        //                .endofpacket
+		.cp_channel              (cmd_mux_010_src_channel),                            //                .channel
+		.rf_sink_ready           (onchip_flash_data_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (onchip_flash_data_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (onchip_flash_data_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (onchip_flash_data_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (onchip_flash_data_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (onchip_flash_data_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (onchip_flash_data_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (onchip_flash_data_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (onchip_flash_data_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (onchip_flash_data_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_010_out_0_ready),                  // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_010_out_0_valid),                  //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_010_out_0_data),                   //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_010_out_0_error),                  //                .error
+		.rdata_fifo_src_ready    (onchip_flash_data_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (onchip_flash_data_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (onchip_flash_data_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                              //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) onchip_flash_data_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                    //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
+		.in_data           (onchip_flash_data_agent_rf_source_data),             //        in.data
+		.in_valid          (onchip_flash_data_agent_rf_source_valid),            //          .valid
+		.in_ready          (onchip_flash_data_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (onchip_flash_data_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (onchip_flash_data_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (onchip_flash_data_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (onchip_flash_data_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (onchip_flash_data_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (onchip_flash_data_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (onchip_flash_data_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) cpu_debug_mem_slave_agent (
+		.clk                     (sys_clk_clk_clk),                                      //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                //       clk_reset.reset
+		.m0_address              (cpu_debug_mem_slave_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (cpu_debug_mem_slave_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (cpu_debug_mem_slave_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (cpu_debug_mem_slave_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (cpu_debug_mem_slave_agent_m0_lock),                    //                .lock
+		.m0_readdata             (cpu_debug_mem_slave_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (cpu_debug_mem_slave_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (cpu_debug_mem_slave_agent_m0_read),                    //                .read
+		.m0_waitrequest          (cpu_debug_mem_slave_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (cpu_debug_mem_slave_agent_m0_writedata),               //                .writedata
+		.m0_write                (cpu_debug_mem_slave_agent_m0_write),                   //                .write
+		.rp_endofpacket          (cpu_debug_mem_slave_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (cpu_debug_mem_slave_agent_rp_ready),                   //                .ready
+		.rp_valid                (cpu_debug_mem_slave_agent_rp_valid),                   //                .valid
+		.rp_data                 (cpu_debug_mem_slave_agent_rp_data),                    //                .data
+		.rp_startofpacket        (cpu_debug_mem_slave_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_011_src_ready),                                //              cp.ready
+		.cp_valid                (cmd_mux_011_src_valid),                                //                .valid
+		.cp_data                 (cmd_mux_011_src_data),                                 //                .data
+		.cp_startofpacket        (cmd_mux_011_src_startofpacket),                        //                .startofpacket
+		.cp_endofpacket          (cmd_mux_011_src_endofpacket),                          //                .endofpacket
+		.cp_channel              (cmd_mux_011_src_channel),                              //                .channel
+		.rf_sink_ready           (cpu_debug_mem_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (cpu_debug_mem_slave_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (cpu_debug_mem_slave_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (cpu_debug_mem_slave_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (cpu_debug_mem_slave_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (cpu_debug_mem_slave_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (cpu_debug_mem_slave_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (cpu_debug_mem_slave_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_011_out_0_ready),                    // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_011_out_0_valid),                    //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_011_out_0_data),                     //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_011_out_0_error),                    //                .error
+		.rdata_fifo_src_ready    (cpu_debug_mem_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (cpu_debug_mem_slave_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (cpu_debug_mem_slave_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) cpu_debug_mem_slave_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                      //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
+		.in_data           (cpu_debug_mem_slave_agent_rf_source_data),             //        in.data
+		.in_valid          (cpu_debug_mem_slave_agent_rf_source_valid),            //          .valid
+		.in_ready          (cpu_debug_mem_slave_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (cpu_debug_mem_slave_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (cpu_debug_mem_slave_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (cpu_debug_mem_slave_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (cpu_debug_mem_slave_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (cpu_debug_mem_slave_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                // (terminated)
+		.csr_read          (1'b0),                                                 // (terminated)
+		.csr_write         (1'b0),                                                 // (terminated)
+		.csr_readdata      (),                                                     // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
+		.almost_full_data  (),                                                     // (terminated)
+		.almost_empty_data (),                                                     // (terminated)
+		.in_empty          (1'b0),                                                 // (terminated)
+		.out_empty         (),                                                     // (terminated)
+		.in_error          (1'b0),                                                 // (terminated)
+		.out_error         (),                                                     // (terminated)
+		.in_channel        (1'b0),                                                 // (terminated)
+		.out_channel       ()                                                      // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) msgdma_tx_prefetcher_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                           //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                     //       clk_reset.reset
+		.m0_address              (msgdma_tx_prefetcher_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (msgdma_tx_prefetcher_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (msgdma_tx_prefetcher_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (msgdma_tx_prefetcher_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (msgdma_tx_prefetcher_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (msgdma_tx_prefetcher_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (msgdma_tx_prefetcher_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (msgdma_tx_prefetcher_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (msgdma_tx_prefetcher_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (msgdma_tx_prefetcher_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (msgdma_tx_prefetcher_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (msgdma_tx_prefetcher_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (msgdma_tx_prefetcher_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (msgdma_tx_prefetcher_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (msgdma_tx_prefetcher_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (msgdma_tx_prefetcher_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_012_src_ready),                                     //              cp.ready
+		.cp_valid                (cmd_mux_012_src_valid),                                     //                .valid
+		.cp_data                 (cmd_mux_012_src_data),                                      //                .data
+		.cp_startofpacket        (cmd_mux_012_src_startofpacket),                             //                .startofpacket
+		.cp_endofpacket          (cmd_mux_012_src_endofpacket),                               //                .endofpacket
+		.cp_channel              (cmd_mux_012_src_channel),                                   //                .channel
+		.rf_sink_ready           (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (msgdma_tx_prefetcher_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (msgdma_tx_prefetcher_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (msgdma_tx_prefetcher_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (msgdma_tx_prefetcher_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (msgdma_tx_prefetcher_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_012_out_0_ready),                         // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_012_out_0_valid),                         //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_012_out_0_data),                          //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_012_out_0_error),                         //                .error
+		.rdata_fifo_src_ready    (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                     //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) msgdma_tx_prefetcher_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                           //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),                     // clk_reset.reset
+		.in_data           (msgdma_tx_prefetcher_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (msgdma_tx_prefetcher_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (msgdma_tx_prefetcher_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (msgdma_tx_prefetcher_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (msgdma_tx_prefetcher_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (msgdma_tx_prefetcher_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                     // (terminated)
+		.csr_read          (1'b0),                                                      // (terminated)
+		.csr_write         (1'b0),                                                      // (terminated)
+		.csr_readdata      (),                                                          // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
+		.almost_full_data  (),                                                          // (terminated)
+		.almost_empty_data (),                                                          // (terminated)
+		.in_empty          (1'b0),                                                      // (terminated)
+		.out_empty         (),                                                          // (terminated)
+		.in_error          (1'b0),                                                      // (terminated)
+		.out_error         (),                                                          // (terminated)
+		.in_channel        (1'b0),                                                      // (terminated)
+		.out_channel       ()                                                           // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) msgdma_rx_prefetcher_csr_agent (
+		.clk                     (sys_clk_clk_clk),                                           //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                     //       clk_reset.reset
+		.m0_address              (msgdma_rx_prefetcher_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (msgdma_rx_prefetcher_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (msgdma_rx_prefetcher_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (msgdma_rx_prefetcher_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (msgdma_rx_prefetcher_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (msgdma_rx_prefetcher_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (msgdma_rx_prefetcher_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (msgdma_rx_prefetcher_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (msgdma_rx_prefetcher_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (msgdma_rx_prefetcher_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (msgdma_rx_prefetcher_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (msgdma_rx_prefetcher_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (msgdma_rx_prefetcher_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (msgdma_rx_prefetcher_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (msgdma_rx_prefetcher_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (msgdma_rx_prefetcher_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_013_src_ready),                                     //              cp.ready
+		.cp_valid                (cmd_mux_013_src_valid),                                     //                .valid
+		.cp_data                 (cmd_mux_013_src_data),                                      //                .data
+		.cp_startofpacket        (cmd_mux_013_src_startofpacket),                             //                .startofpacket
+		.cp_endofpacket          (cmd_mux_013_src_endofpacket),                               //                .endofpacket
+		.cp_channel              (cmd_mux_013_src_channel),                                   //                .channel
+		.rf_sink_ready           (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (msgdma_rx_prefetcher_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (msgdma_rx_prefetcher_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (msgdma_rx_prefetcher_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (msgdma_rx_prefetcher_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (msgdma_rx_prefetcher_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_013_out_0_ready),                         // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_013_out_0_valid),                         //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_013_out_0_data),                          //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_013_out_0_error),                         //                .error
+		.rdata_fifo_src_ready    (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                     //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) msgdma_rx_prefetcher_csr_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                           //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),                     // clk_reset.reset
+		.in_data           (msgdma_rx_prefetcher_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (msgdma_rx_prefetcher_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (msgdma_rx_prefetcher_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (msgdma_rx_prefetcher_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (msgdma_rx_prefetcher_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (msgdma_rx_prefetcher_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                     // (terminated)
+		.csr_read          (1'b0),                                                      // (terminated)
+		.csr_write         (1'b0),                                                      // (terminated)
+		.csr_readdata      (),                                                          // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
+		.almost_full_data  (),                                                          // (terminated)
+		.almost_empty_data (),                                                          // (terminated)
+		.in_empty          (1'b0),                                                      // (terminated)
+		.out_empty         (),                                                          // (terminated)
+		.in_error          (1'b0),                                                      // (terminated)
+		.out_error         (),                                                          // (terminated)
+		.in_channel        (1'b0),                                                      // (terminated)
+		.out_channel       ()                                                           // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) descriptor_memory_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                       //             clk.clk
+		.reset                   (eth_tse_reset_connection_reset_bridge_in_reset_reset),  //       clk_reset.reset
+		.m0_address              (descriptor_memory_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (descriptor_memory_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (descriptor_memory_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (descriptor_memory_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (descriptor_memory_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (descriptor_memory_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (descriptor_memory_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (descriptor_memory_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (descriptor_memory_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (descriptor_memory_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (descriptor_memory_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (descriptor_memory_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (descriptor_memory_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (descriptor_memory_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (descriptor_memory_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (descriptor_memory_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_014_src_ready),                                 //              cp.ready
+		.cp_valid                (cmd_mux_014_src_valid),                                 //                .valid
+		.cp_data                 (cmd_mux_014_src_data),                                  //                .data
+		.cp_startofpacket        (cmd_mux_014_src_startofpacket),                         //                .startofpacket
+		.cp_endofpacket          (cmd_mux_014_src_endofpacket),                           //                .endofpacket
+		.cp_channel              (cmd_mux_014_src_channel),                               //                .channel
+		.rf_sink_ready           (descriptor_memory_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (descriptor_memory_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (descriptor_memory_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (descriptor_memory_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (descriptor_memory_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (descriptor_memory_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (descriptor_memory_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (descriptor_memory_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (descriptor_memory_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (descriptor_memory_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_014_out_0_ready),                     // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_014_out_0_valid),                     //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_014_out_0_data),                      //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_014_out_0_error),                     //                .error
+		.rdata_fifo_src_ready    (descriptor_memory_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (descriptor_memory_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (descriptor_memory_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                 //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                   //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) descriptor_memory_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                       //       clk.clk
+		.reset             (eth_tse_reset_connection_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.in_data           (descriptor_memory_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (descriptor_memory_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (descriptor_memory_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (descriptor_memory_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (descriptor_memory_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (descriptor_memory_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (descriptor_memory_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (descriptor_memory_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (descriptor_memory_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (descriptor_memory_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                 // (terminated)
+		.csr_read          (1'b0),                                                  // (terminated)
+		.csr_write         (1'b0),                                                  // (terminated)
+		.csr_readdata      (),                                                      // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
+		.almost_full_data  (),                                                      // (terminated)
+		.almost_empty_data (),                                                      // (terminated)
+		.in_empty          (1'b0),                                                  // (terminated)
+		.out_empty         (),                                                      // (terminated)
+		.in_error          (1'b0),                                                  // (terminated)
+		.out_error         (),                                                      // (terminated)
+		.in_channel        (1'b0),                                                  // (terminated)
+		.out_channel       ()                                                       // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) sys_clk_timer_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                      //             clk.clk
+		.reset                   (eth_tse_reset_connection_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (sys_clk_timer_s1_agent_m0_address),                    //              m0.address
+		.m0_burstcount           (sys_clk_timer_s1_agent_m0_burstcount),                 //                .burstcount
+		.m0_byteenable           (sys_clk_timer_s1_agent_m0_byteenable),                 //                .byteenable
+		.m0_debugaccess          (sys_clk_timer_s1_agent_m0_debugaccess),                //                .debugaccess
+		.m0_lock                 (sys_clk_timer_s1_agent_m0_lock),                       //                .lock
+		.m0_readdata             (sys_clk_timer_s1_agent_m0_readdata),                   //                .readdata
+		.m0_readdatavalid        (sys_clk_timer_s1_agent_m0_readdatavalid),              //                .readdatavalid
+		.m0_read                 (sys_clk_timer_s1_agent_m0_read),                       //                .read
+		.m0_waitrequest          (sys_clk_timer_s1_agent_m0_waitrequest),                //                .waitrequest
+		.m0_writedata            (sys_clk_timer_s1_agent_m0_writedata),                  //                .writedata
+		.m0_write                (sys_clk_timer_s1_agent_m0_write),                      //                .write
+		.rp_endofpacket          (sys_clk_timer_s1_agent_rp_endofpacket),                //              rp.endofpacket
+		.rp_ready                (sys_clk_timer_s1_agent_rp_ready),                      //                .ready
+		.rp_valid                (sys_clk_timer_s1_agent_rp_valid),                      //                .valid
+		.rp_data                 (sys_clk_timer_s1_agent_rp_data),                       //                .data
+		.rp_startofpacket        (sys_clk_timer_s1_agent_rp_startofpacket),              //                .startofpacket
+		.cp_ready                (cmd_mux_015_src_ready),                                //              cp.ready
+		.cp_valid                (cmd_mux_015_src_valid),                                //                .valid
+		.cp_data                 (cmd_mux_015_src_data),                                 //                .data
+		.cp_startofpacket        (cmd_mux_015_src_startofpacket),                        //                .startofpacket
+		.cp_endofpacket          (cmd_mux_015_src_endofpacket),                          //                .endofpacket
+		.cp_channel              (cmd_mux_015_src_channel),                              //                .channel
+		.rf_sink_ready           (sys_clk_timer_s1_agent_rsp_fifo_out_ready),            //         rf_sink.ready
+		.rf_sink_valid           (sys_clk_timer_s1_agent_rsp_fifo_out_valid),            //                .valid
+		.rf_sink_startofpacket   (sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
+		.rf_sink_endofpacket     (sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
+		.rf_sink_data            (sys_clk_timer_s1_agent_rsp_fifo_out_data),             //                .data
+		.rf_source_ready         (sys_clk_timer_s1_agent_rf_source_ready),               //       rf_source.ready
+		.rf_source_valid         (sys_clk_timer_s1_agent_rf_source_valid),               //                .valid
+		.rf_source_startofpacket (sys_clk_timer_s1_agent_rf_source_startofpacket),       //                .startofpacket
+		.rf_source_endofpacket   (sys_clk_timer_s1_agent_rf_source_endofpacket),         //                .endofpacket
+		.rf_source_data          (sys_clk_timer_s1_agent_rf_source_data),                //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_015_out_0_ready),                    // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_015_out_0_valid),                    //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_015_out_0_data),                     //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_015_out_0_error),                    //                .error
+		.rdata_fifo_src_ready    (sys_clk_timer_s1_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (sys_clk_timer_s1_agent_rdata_fifo_src_valid),          //                .valid
+		.rdata_fifo_src_data     (sys_clk_timer_s1_agent_rdata_fifo_src_data),           //                .data
+		.m0_response             (2'b00),                                                //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) sys_clk_timer_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                      //       clk.clk
+		.reset             (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (sys_clk_timer_s1_agent_rf_source_data),                //        in.data
+		.in_valid          (sys_clk_timer_s1_agent_rf_source_valid),               //          .valid
+		.in_ready          (sys_clk_timer_s1_agent_rf_source_ready),               //          .ready
+		.in_startofpacket  (sys_clk_timer_s1_agent_rf_source_startofpacket),       //          .startofpacket
+		.in_endofpacket    (sys_clk_timer_s1_agent_rf_source_endofpacket),         //          .endofpacket
+		.out_data          (sys_clk_timer_s1_agent_rsp_fifo_out_data),             //       out.data
+		.out_valid         (sys_clk_timer_s1_agent_rsp_fifo_out_valid),            //          .valid
+		.out_ready         (sys_clk_timer_s1_agent_rsp_fifo_out_ready),            //          .ready
+		.out_startofpacket (sys_clk_timer_s1_agent_rsp_fifo_out_startofpacket),    //          .startofpacket
+		.out_endofpacket   (sys_clk_timer_s1_agent_rsp_fifo_out_endofpacket),      //          .endofpacket
+		.csr_address       (2'b00),                                                // (terminated)
+		.csr_read          (1'b0),                                                 // (terminated)
+		.csr_write         (1'b0),                                                 // (terminated)
+		.csr_readdata      (),                                                     // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
+		.almost_full_data  (),                                                     // (terminated)
+		.almost_empty_data (),                                                     // (terminated)
+		.in_empty          (1'b0),                                                 // (terminated)
+		.out_empty         (),                                                     // (terminated)
+		.in_error          (1'b0),                                                 // (terminated)
+		.out_error         (),                                                     // (terminated)
+		.in_channel        (1'b0),                                                 // (terminated)
+		.out_channel       ()                                                      // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) output_pio_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                      //             clk.clk
+		.reset                   (eth_tse_reset_connection_reset_bridge_in_reset_reset), //       clk_reset.reset
+		.m0_address              (output_pio_s1_agent_m0_address),                       //              m0.address
+		.m0_burstcount           (output_pio_s1_agent_m0_burstcount),                    //                .burstcount
+		.m0_byteenable           (output_pio_s1_agent_m0_byteenable),                    //                .byteenable
+		.m0_debugaccess          (output_pio_s1_agent_m0_debugaccess),                   //                .debugaccess
+		.m0_lock                 (output_pio_s1_agent_m0_lock),                          //                .lock
+		.m0_readdata             (output_pio_s1_agent_m0_readdata),                      //                .readdata
+		.m0_readdatavalid        (output_pio_s1_agent_m0_readdatavalid),                 //                .readdatavalid
+		.m0_read                 (output_pio_s1_agent_m0_read),                          //                .read
+		.m0_waitrequest          (output_pio_s1_agent_m0_waitrequest),                   //                .waitrequest
+		.m0_writedata            (output_pio_s1_agent_m0_writedata),                     //                .writedata
+		.m0_write                (output_pio_s1_agent_m0_write),                         //                .write
+		.rp_endofpacket          (output_pio_s1_agent_rp_endofpacket),                   //              rp.endofpacket
+		.rp_ready                (output_pio_s1_agent_rp_ready),                         //                .ready
+		.rp_valid                (output_pio_s1_agent_rp_valid),                         //                .valid
+		.rp_data                 (output_pio_s1_agent_rp_data),                          //                .data
+		.rp_startofpacket        (output_pio_s1_agent_rp_startofpacket),                 //                .startofpacket
+		.cp_ready                (cmd_mux_016_src_ready),                                //              cp.ready
+		.cp_valid                (cmd_mux_016_src_valid),                                //                .valid
+		.cp_data                 (cmd_mux_016_src_data),                                 //                .data
+		.cp_startofpacket        (cmd_mux_016_src_startofpacket),                        //                .startofpacket
+		.cp_endofpacket          (cmd_mux_016_src_endofpacket),                          //                .endofpacket
+		.cp_channel              (cmd_mux_016_src_channel),                              //                .channel
+		.rf_sink_ready           (output_pio_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
+		.rf_sink_valid           (output_pio_s1_agent_rsp_fifo_out_valid),               //                .valid
+		.rf_sink_startofpacket   (output_pio_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
+		.rf_sink_endofpacket     (output_pio_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
+		.rf_sink_data            (output_pio_s1_agent_rsp_fifo_out_data),                //                .data
+		.rf_source_ready         (output_pio_s1_agent_rf_source_ready),                  //       rf_source.ready
+		.rf_source_valid         (output_pio_s1_agent_rf_source_valid),                  //                .valid
+		.rf_source_startofpacket (output_pio_s1_agent_rf_source_startofpacket),          //                .startofpacket
+		.rf_source_endofpacket   (output_pio_s1_agent_rf_source_endofpacket),            //                .endofpacket
+		.rf_source_data          (output_pio_s1_agent_rf_source_data),                   //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_016_out_0_ready),                    // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_016_out_0_valid),                    //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_016_out_0_data),                     //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_016_out_0_error),                    //                .error
+		.rdata_fifo_src_ready    (output_pio_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (output_pio_s1_agent_rdata_fifo_src_valid),             //                .valid
+		.rdata_fifo_src_data     (output_pio_s1_agent_rdata_fifo_src_data),              //                .data
+		.m0_response             (2'b00),                                                //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) output_pio_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                      //       clk.clk
+		.reset             (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.in_data           (output_pio_s1_agent_rf_source_data),                   //        in.data
+		.in_valid          (output_pio_s1_agent_rf_source_valid),                  //          .valid
+		.in_ready          (output_pio_s1_agent_rf_source_ready),                  //          .ready
+		.in_startofpacket  (output_pio_s1_agent_rf_source_startofpacket),          //          .startofpacket
+		.in_endofpacket    (output_pio_s1_agent_rf_source_endofpacket),            //          .endofpacket
+		.out_data          (output_pio_s1_agent_rsp_fifo_out_data),                //       out.data
+		.out_valid         (output_pio_s1_agent_rsp_fifo_out_valid),               //          .valid
+		.out_ready         (output_pio_s1_agent_rsp_fifo_out_ready),               //          .ready
+		.out_startofpacket (output_pio_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
+		.out_endofpacket   (output_pio_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
+		.csr_address       (2'b00),                                                // (terminated)
+		.csr_read          (1'b0),                                                 // (terminated)
+		.csr_write         (1'b0),                                                 // (terminated)
+		.csr_readdata      (),                                                     // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
+		.almost_full_data  (),                                                     // (terminated)
+		.almost_empty_data (),                                                     // (terminated)
+		.in_empty          (1'b0),                                                 // (terminated)
+		.out_empty         (),                                                     // (terminated)
+		.in_error          (1'b0),                                                 // (terminated)
+		.out_error         (),                                                     // (terminated)
+		.in_channel        (1'b0),                                                 // (terminated)
+		.out_channel       ()                                                      // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) button_pio_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
+		.m0_address              (button_pio_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (button_pio_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (button_pio_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (button_pio_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (button_pio_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (button_pio_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (button_pio_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (button_pio_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (button_pio_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (button_pio_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (button_pio_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (button_pio_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (button_pio_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (button_pio_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (button_pio_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (button_pio_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_017_src_ready),                          //              cp.ready
+		.cp_valid                (cmd_mux_017_src_valid),                          //                .valid
+		.cp_data                 (cmd_mux_017_src_data),                           //                .data
+		.cp_startofpacket        (cmd_mux_017_src_startofpacket),                  //                .startofpacket
+		.cp_endofpacket          (cmd_mux_017_src_endofpacket),                    //                .endofpacket
+		.cp_channel              (cmd_mux_017_src_channel),                        //                .channel
+		.rf_sink_ready           (button_pio_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (button_pio_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (button_pio_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (button_pio_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (button_pio_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (button_pio_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (button_pio_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (button_pio_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (button_pio_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (button_pio_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_017_out_0_ready),              // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_017_out_0_valid),              //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_017_out_0_data),               //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_017_out_0_error),              //                .error
+		.rdata_fifo_src_ready    (button_pio_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (button_pio_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (button_pio_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                          //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) button_pio_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
+		.in_data           (button_pio_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (button_pio_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (button_pio_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (button_pio_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (button_pio_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (button_pio_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (button_pio_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (button_pio_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (button_pio_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (button_pio_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                          // (terminated)
+		.csr_read          (1'b0),                                           // (terminated)
+		.csr_write         (1'b0),                                           // (terminated)
+		.csr_readdata      (),                                               // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
+		.almost_full_data  (),                                               // (terminated)
+		.almost_empty_data (),                                               // (terminated)
+		.in_empty          (1'b0),                                           // (terminated)
+		.out_empty         (),                                               // (terminated)
+		.in_error          (1'b0),                                           // (terminated)
+		.out_error         (),                                               // (terminated)
+		.in_channel        (1'b0),                                           // (terminated)
+		.out_channel       ()                                                // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) debug_uart_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
+		.m0_address              (debug_uart_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (debug_uart_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (debug_uart_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (debug_uart_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (debug_uart_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (debug_uart_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (debug_uart_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (debug_uart_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (debug_uart_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (debug_uart_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (debug_uart_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (debug_uart_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (debug_uart_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (debug_uart_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (debug_uart_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (debug_uart_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_018_src_ready),                          //              cp.ready
+		.cp_valid                (cmd_mux_018_src_valid),                          //                .valid
+		.cp_data                 (cmd_mux_018_src_data),                           //                .data
+		.cp_startofpacket        (cmd_mux_018_src_startofpacket),                  //                .startofpacket
+		.cp_endofpacket          (cmd_mux_018_src_endofpacket),                    //                .endofpacket
+		.cp_channel              (cmd_mux_018_src_channel),                        //                .channel
+		.rf_sink_ready           (debug_uart_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (debug_uart_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (debug_uart_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (debug_uart_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (debug_uart_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (debug_uart_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (debug_uart_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (debug_uart_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (debug_uart_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (debug_uart_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_018_out_0_ready),              // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_018_out_0_valid),              //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_018_out_0_data),               //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_018_out_0_error),              //                .error
+		.rdata_fifo_src_ready    (debug_uart_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (debug_uart_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (debug_uart_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                          //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) debug_uart_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
+		.in_data           (debug_uart_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (debug_uart_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (debug_uart_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (debug_uart_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (debug_uart_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (debug_uart_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (debug_uart_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (debug_uart_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (debug_uart_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (debug_uart_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                          // (terminated)
+		.csr_read          (1'b0),                                           // (terminated)
+		.csr_write         (1'b0),                                           // (terminated)
+		.csr_readdata      (),                                               // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
+		.almost_full_data  (),                                               // (terminated)
+		.almost_empty_data (),                                               // (terminated)
+		.in_empty          (1'b0),                                           // (terminated)
+		.out_empty         (),                                               // (terminated)
+		.in_error          (1'b0),                                           // (terminated)
+		.out_error         (),                                               // (terminated)
+		.in_channel        (1'b0),                                           // (terminated)
+		.out_channel       ()                                                // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (120),
+		.PKT_ORI_BURST_SIZE_L      (118),
+		.PKT_RESPONSE_STATUS_H     (117),
+		.PKT_RESPONSE_STATUS_L     (116),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_TRANS_LOCK            (69),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_PROTECTION_H          (111),
+		.PKT_PROTECTION_L          (109),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (121),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) frame_timer_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                 //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),           //       clk_reset.reset
+		.m0_address              (frame_timer_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (frame_timer_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (frame_timer_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (frame_timer_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (frame_timer_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (frame_timer_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (frame_timer_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (frame_timer_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (frame_timer_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (frame_timer_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (frame_timer_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (frame_timer_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (frame_timer_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (frame_timer_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (frame_timer_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (frame_timer_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_019_src_ready),                           //              cp.ready
+		.cp_valid                (cmd_mux_019_src_valid),                           //                .valid
+		.cp_data                 (cmd_mux_019_src_data),                            //                .data
+		.cp_startofpacket        (cmd_mux_019_src_startofpacket),                   //                .startofpacket
+		.cp_endofpacket          (cmd_mux_019_src_endofpacket),                     //                .endofpacket
+		.cp_channel              (cmd_mux_019_src_channel),                         //                .channel
+		.rf_sink_ready           (frame_timer_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (frame_timer_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (frame_timer_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (frame_timer_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (frame_timer_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (frame_timer_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (frame_timer_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (frame_timer_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (frame_timer_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (frame_timer_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_019_out_0_ready),               // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_019_out_0_valid),               //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_019_out_0_data),                //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_019_out_0_error),               //                .error
+		.rdata_fifo_src_ready    (frame_timer_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (frame_timer_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (frame_timer_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                           //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                             //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (122),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) frame_timer_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                 //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),           // clk_reset.reset
+		.in_data           (frame_timer_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (frame_timer_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (frame_timer_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (frame_timer_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (frame_timer_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (frame_timer_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (frame_timer_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (frame_timer_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (frame_timer_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (frame_timer_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                           // (terminated)
+		.csr_read          (1'b0),                                            // (terminated)
+		.csr_write         (1'b0),                                            // (terminated)
+		.csr_readdata      (),                                                // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
+		.almost_full_data  (),                                                // (terminated)
+		.almost_empty_data (),                                                // (terminated)
+		.in_empty          (1'b0),                                            // (terminated)
+		.out_empty         (),                                                // (terminated)
+		.in_error          (1'b0),                                            // (terminated)
+		.out_error         (),                                                // (terminated)
+		.in_channel        (1'b0),                                            // (terminated)
+		.out_channel       ()                                                 // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (102),
+		.PKT_ORI_BURST_SIZE_L      (100),
+		.PKT_RESPONSE_STATUS_H     (99),
+		.PKT_RESPONSE_STATUS_L     (98),
+		.PKT_BURST_SIZE_H          (73),
+		.PKT_BURST_SIZE_L          (71),
+		.PKT_TRANS_LOCK            (51),
+		.PKT_BEGIN_BURST           (78),
+		.PKT_PROTECTION_H          (93),
+		.PKT_PROTECTION_L          (91),
+		.PKT_BURSTWRAP_H           (70),
+		.PKT_BURSTWRAP_L           (62),
+		.PKT_BYTE_CNT_H            (61),
+		.PKT_BYTE_CNT_L            (53),
+		.PKT_ADDR_H                (46),
+		.PKT_ADDR_L                (18),
+		.PKT_TRANS_COMPRESSED_READ (47),
+		.PKT_TRANS_POSTED          (48),
+		.PKT_TRANS_WRITE           (49),
+		.PKT_TRANS_READ            (50),
+		.PKT_DATA_H                (15),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (17),
+		.PKT_BYTEEN_L              (16),
+		.PKT_SRC_ID_H              (84),
+		.PKT_SRC_ID_L              (80),
+		.PKT_DEST_ID_H             (89),
+		.PKT_DEST_ID_L             (85),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (21),
+		.ST_DATA_W                 (103),
+		.AVS_BURSTCOUNT_W          (2),
+		.SUPPRESS_0_BYTEEN_CMD     (1),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) calibration_ram_s1_agent (
+		.clk                     (sys_clk_clk_clk),                                        //             clk.clk
+		.reset                   (cpu_reset_reset_bridge_in_reset_reset),                  //       clk_reset.reset
+		.m0_address              (calibration_ram_s1_agent_m0_address),                    //              m0.address
+		.m0_burstcount           (calibration_ram_s1_agent_m0_burstcount),                 //                .burstcount
+		.m0_byteenable           (calibration_ram_s1_agent_m0_byteenable),                 //                .byteenable
+		.m0_debugaccess          (calibration_ram_s1_agent_m0_debugaccess),                //                .debugaccess
+		.m0_lock                 (calibration_ram_s1_agent_m0_lock),                       //                .lock
+		.m0_readdata             (calibration_ram_s1_agent_m0_readdata),                   //                .readdata
+		.m0_readdatavalid        (calibration_ram_s1_agent_m0_readdatavalid),              //                .readdatavalid
+		.m0_read                 (calibration_ram_s1_agent_m0_read),                       //                .read
+		.m0_waitrequest          (calibration_ram_s1_agent_m0_waitrequest),                //                .waitrequest
+		.m0_writedata            (calibration_ram_s1_agent_m0_writedata),                  //                .writedata
+		.m0_write                (calibration_ram_s1_agent_m0_write),                      //                .write
+		.rp_endofpacket          (calibration_ram_s1_agent_rp_endofpacket),                //              rp.endofpacket
+		.rp_ready                (calibration_ram_s1_agent_rp_ready),                      //                .ready
+		.rp_valid                (calibration_ram_s1_agent_rp_valid),                      //                .valid
+		.rp_data                 (calibration_ram_s1_agent_rp_data),                       //                .data
+		.rp_startofpacket        (calibration_ram_s1_agent_rp_startofpacket),              //                .startofpacket
+		.cp_ready                (calibration_ram_s1_burst_adapter_source0_ready),         //              cp.ready
+		.cp_valid                (calibration_ram_s1_burst_adapter_source0_valid),         //                .valid
+		.cp_data                 (calibration_ram_s1_burst_adapter_source0_data),          //                .data
+		.cp_startofpacket        (calibration_ram_s1_burst_adapter_source0_startofpacket), //                .startofpacket
+		.cp_endofpacket          (calibration_ram_s1_burst_adapter_source0_endofpacket),   //                .endofpacket
+		.cp_channel              (calibration_ram_s1_burst_adapter_source0_channel),       //                .channel
+		.rf_sink_ready           (calibration_ram_s1_agent_rsp_fifo_out_ready),            //         rf_sink.ready
+		.rf_sink_valid           (calibration_ram_s1_agent_rsp_fifo_out_valid),            //                .valid
+		.rf_sink_startofpacket   (calibration_ram_s1_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
+		.rf_sink_endofpacket     (calibration_ram_s1_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
+		.rf_sink_data            (calibration_ram_s1_agent_rsp_fifo_out_data),             //                .data
+		.rf_source_ready         (calibration_ram_s1_agent_rf_source_ready),               //       rf_source.ready
+		.rf_source_valid         (calibration_ram_s1_agent_rf_source_valid),               //                .valid
+		.rf_source_startofpacket (calibration_ram_s1_agent_rf_source_startofpacket),       //                .startofpacket
+		.rf_source_endofpacket   (calibration_ram_s1_agent_rf_source_endofpacket),         //                .endofpacket
+		.rf_source_data          (calibration_ram_s1_agent_rf_source_data),                //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_020_out_0_ready),                      // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_020_out_0_valid),                      //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_020_out_0_data),                       //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_020_out_0_error),                      //                .error
+		.rdata_fifo_src_ready    (calibration_ram_s1_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (calibration_ram_s1_agent_rdata_fifo_src_valid),          //                .valid
+		.rdata_fifo_src_data     (calibration_ram_s1_agent_rdata_fifo_src_data),           //                .data
+		.m0_response             (2'b00),                                                  //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                    //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (104),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) calibration_ram_s1_agent_rsp_fifo (
+		.clk               (sys_clk_clk_clk),                                     //       clk.clk
+		.reset             (cpu_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
+		.in_data           (calibration_ram_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (calibration_ram_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (calibration_ram_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (calibration_ram_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (calibration_ram_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (calibration_ram_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (calibration_ram_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (calibration_ram_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (calibration_ram_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (calibration_ram_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                               // (terminated)
+		.csr_read          (1'b0),                                                // (terminated)
+		.csr_write         (1'b0),                                                // (terminated)
+		.csr_readdata      (),                                                    // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated)
+		.almost_full_data  (),                                                    // (terminated)
+		.almost_empty_data (),                                                    // (terminated)
+		.in_empty          (1'b0),                                                // (terminated)
+		.out_empty         (),                                                    // (terminated)
+		.in_error          (1'b0),                                                // (terminated)
+		.out_error         (),                                                    // (terminated)
+		.in_channel        (1'b0),                                                // (terminated)
+		.out_channel       ()                                                     // (terminated)
+	);
+
+	q_sys_mm_interconnect_1_router router (
+		.sink_ready         (cpu_data_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (cpu_data_master_agent_cp_valid),         //          .valid
+		.sink_data          (cpu_data_master_agent_cp_data),          //          .data
+		.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (cpu_data_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                        //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.src_ready          (router_src_ready),                       //       src.ready
+		.src_valid          (router_src_valid),                       //          .valid
+		.src_data           (router_src_data),                        //          .data
+		.src_channel        (router_src_channel),                     //          .channel
+		.src_startofpacket  (router_src_startofpacket),               //          .startofpacket
+		.src_endofpacket    (router_src_endofpacket)                  //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_001 router_001 (
+		.sink_ready         (cpu_instruction_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (cpu_instruction_master_agent_cp_valid),         //          .valid
+		.sink_data          (cpu_instruction_master_agent_cp_data),          //          .data
+		.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (cpu_instruction_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                               //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
+		.src_ready          (router_001_src_ready),                          //       src.ready
+		.src_valid          (router_001_src_valid),                          //          .valid
+		.src_data           (router_001_src_data),                           //          .data
+		.src_channel        (router_001_src_channel),                        //          .channel
+		.src_startofpacket  (router_001_src_startofpacket),                  //          .startofpacket
+		.src_endofpacket    (router_001_src_endofpacket)                     //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_002 router_002 (
+		.sink_ready         (msgdma_tx_mm_read_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_tx_mm_read_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_tx_mm_read_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_tx_mm_read_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_tx_mm_read_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                          //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
+		.src_ready          (router_002_src_ready),                     //       src.ready
+		.src_valid          (router_002_src_valid),                     //          .valid
+		.src_data           (router_002_src_data),                      //          .data
+		.src_channel        (router_002_src_channel),                   //          .channel
+		.src_startofpacket  (router_002_src_startofpacket),             //          .startofpacket
+		.src_endofpacket    (router_002_src_endofpacket)                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_002 router_003 (
+		.sink_ready         (msgdma_rx_mm_write_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_rx_mm_write_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_rx_mm_write_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_rx_mm_write_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_rx_mm_write_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                           //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
+		.src_ready          (router_003_src_ready),                      //       src.ready
+		.src_valid          (router_003_src_valid),                      //          .valid
+		.src_data           (router_003_src_data),                       //          .data
+		.src_channel        (router_003_src_channel),                    //          .channel
+		.src_startofpacket  (router_003_src_startofpacket),              //          .startofpacket
+		.src_endofpacket    (router_003_src_endofpacket)                 //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_004 router_004 (
+		.sink_ready         (msgdma_tx_descriptor_read_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_tx_descriptor_read_master_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_tx_descriptor_read_master_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_tx_descriptor_read_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_tx_descriptor_read_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                         //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                   // clk_reset.reset
+		.src_ready          (router_004_src_ready),                                    //       src.ready
+		.src_valid          (router_004_src_valid),                                    //          .valid
+		.src_data           (router_004_src_data),                                     //          .data
+		.src_channel        (router_004_src_channel),                                  //          .channel
+		.src_startofpacket  (router_004_src_startofpacket),                            //          .startofpacket
+		.src_endofpacket    (router_004_src_endofpacket)                               //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_004 router_005 (
+		.sink_ready         (msgdma_rx_descriptor_read_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_rx_descriptor_read_master_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_rx_descriptor_read_master_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_rx_descriptor_read_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_rx_descriptor_read_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                         //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                   // clk_reset.reset
+		.src_ready          (router_005_src_ready),                                    //       src.ready
+		.src_valid          (router_005_src_valid),                                    //          .valid
+		.src_data           (router_005_src_data),                                     //          .data
+		.src_channel        (router_005_src_channel),                                  //          .channel
+		.src_startofpacket  (router_005_src_startofpacket),                            //          .startofpacket
+		.src_endofpacket    (router_005_src_endofpacket)                               //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_004 router_006 (
+		.sink_ready         (msgdma_tx_descriptor_write_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_tx_descriptor_write_master_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_tx_descriptor_write_master_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_tx_descriptor_write_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_tx_descriptor_write_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                          //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                    // clk_reset.reset
+		.src_ready          (router_006_src_ready),                                     //       src.ready
+		.src_valid          (router_006_src_valid),                                     //          .valid
+		.src_data           (router_006_src_data),                                      //          .data
+		.src_channel        (router_006_src_channel),                                   //          .channel
+		.src_startofpacket  (router_006_src_startofpacket),                             //          .startofpacket
+		.src_endofpacket    (router_006_src_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_004 router_007 (
+		.sink_ready         (msgdma_rx_descriptor_write_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (msgdma_rx_descriptor_write_master_agent_cp_valid),         //          .valid
+		.sink_data          (msgdma_rx_descriptor_write_master_agent_cp_data),          //          .data
+		.sink_startofpacket (msgdma_rx_descriptor_write_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_rx_descriptor_write_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                          //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                    // clk_reset.reset
+		.src_ready          (router_007_src_ready),                                     //       src.ready
+		.src_valid          (router_007_src_valid),                                     //          .valid
+		.src_data           (router_007_src_data),                                      //          .data
+		.src_channel        (router_007_src_channel),                                   //          .channel
+		.src_startofpacket  (router_007_src_startofpacket),                             //          .startofpacket
+		.src_endofpacket    (router_007_src_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_008 router_008 (
+		.sink_ready         (ddr3_ram_avl_agent_rp_ready),                               //      sink.ready
+		.sink_valid         (ddr3_ram_avl_agent_rp_valid),                               //          .valid
+		.sink_data          (ddr3_ram_avl_agent_rp_data),                                //          .data
+		.sink_startofpacket (ddr3_ram_avl_agent_rp_startofpacket),                       //          .startofpacket
+		.sink_endofpacket   (ddr3_ram_avl_agent_rp_endofpacket),                         //          .endofpacket
+		.clk                (ddr3_ram_afi_clk_clk),                                      //       clk.clk
+		.reset              (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_008_src_ready),                                      //       src.ready
+		.src_valid          (router_008_src_valid),                                      //          .valid
+		.src_data           (router_008_src_data),                                       //          .data
+		.src_channel        (router_008_src_channel),                                    //          .channel
+		.src_startofpacket  (router_008_src_startofpacket),                              //          .startofpacket
+		.src_endofpacket    (router_008_src_endofpacket)                                 //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_009 (
+		.sink_ready         (ext_flash_avl_csr_agent_rp_ready),            //      sink.ready
+		.sink_valid         (ext_flash_avl_csr_agent_rp_valid),            //          .valid
+		.sink_data          (ext_flash_avl_csr_agent_rp_data),             //          .data
+		.sink_startofpacket (ext_flash_avl_csr_agent_rp_startofpacket),    //          .startofpacket
+		.sink_endofpacket   (ext_flash_avl_csr_agent_rp_endofpacket),      //          .endofpacket
+		.clk                (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset              (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_009_src_ready),                        //       src.ready
+		.src_valid          (router_009_src_valid),                        //          .valid
+		.src_data           (router_009_src_data),                         //          .data
+		.src_channel        (router_009_src_channel),                      //          .channel
+		.src_startofpacket  (router_009_src_startofpacket),                //          .startofpacket
+		.src_endofpacket    (router_009_src_endofpacket)                   //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_010 router_010 (
+		.sink_ready         (ext_flash_avl_mem_agent_rp_ready),            //      sink.ready
+		.sink_valid         (ext_flash_avl_mem_agent_rp_valid),            //          .valid
+		.sink_data          (ext_flash_avl_mem_agent_rp_data),             //          .data
+		.sink_startofpacket (ext_flash_avl_mem_agent_rp_startofpacket),    //          .startofpacket
+		.sink_endofpacket   (ext_flash_avl_mem_agent_rp_endofpacket),      //          .endofpacket
+		.clk                (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset              (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_010_src_ready),                        //       src.ready
+		.src_valid          (router_010_src_valid),                        //          .valid
+		.src_data           (router_010_src_data),                         //          .data
+		.src_channel        (router_010_src_channel),                      //          .channel
+		.src_startofpacket  (router_010_src_startofpacket),                //          .startofpacket
+		.src_endofpacket    (router_010_src_endofpacket)                   //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_011 (
+		.sink_ready         (eth_tse_control_port_agent_rp_ready),                  //      sink.ready
+		.sink_valid         (eth_tse_control_port_agent_rp_valid),                  //          .valid
+		.sink_data          (eth_tse_control_port_agent_rp_data),                   //          .data
+		.sink_startofpacket (eth_tse_control_port_agent_rp_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (eth_tse_control_port_agent_rp_endofpacket),            //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_011_src_ready),                                 //       src.ready
+		.src_valid          (router_011_src_valid),                                 //          .valid
+		.src_data           (router_011_src_data),                                  //          .data
+		.src_channel        (router_011_src_channel),                               //          .channel
+		.src_startofpacket  (router_011_src_startofpacket),                         //          .startofpacket
+		.src_endofpacket    (router_011_src_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_012 (
+		.sink_ready         (sysid_control_slave_agent_rp_ready),                   //      sink.ready
+		.sink_valid         (sysid_control_slave_agent_rp_valid),                   //          .valid
+		.sink_data          (sysid_control_slave_agent_rp_data),                    //          .data
+		.sink_startofpacket (sysid_control_slave_agent_rp_startofpacket),           //          .startofpacket
+		.sink_endofpacket   (sysid_control_slave_agent_rp_endofpacket),             //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_012_src_ready),                                 //       src.ready
+		.src_valid          (router_012_src_valid),                                 //          .valid
+		.src_data           (router_012_src_data),                                  //          .data
+		.src_channel        (router_012_src_channel),                               //          .channel
+		.src_startofpacket  (router_012_src_startofpacket),                         //          .startofpacket
+		.src_endofpacket    (router_012_src_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_013 (
+		.sink_ready         (msgdma_tx_csr_agent_rp_ready),          //      sink.ready
+		.sink_valid         (msgdma_tx_csr_agent_rp_valid),          //          .valid
+		.sink_data          (msgdma_tx_csr_agent_rp_data),           //          .data
+		.sink_startofpacket (msgdma_tx_csr_agent_rp_startofpacket),  //          .startofpacket
+		.sink_endofpacket   (msgdma_tx_csr_agent_rp_endofpacket),    //          .endofpacket
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_013_src_ready),                  //       src.ready
+		.src_valid          (router_013_src_valid),                  //          .valid
+		.src_data           (router_013_src_data),                   //          .data
+		.src_channel        (router_013_src_channel),                //          .channel
+		.src_startofpacket  (router_013_src_startofpacket),          //          .startofpacket
+		.src_endofpacket    (router_013_src_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_014 (
+		.sink_ready         (msgdma_rx_csr_agent_rp_ready),          //      sink.ready
+		.sink_valid         (msgdma_rx_csr_agent_rp_valid),          //          .valid
+		.sink_data          (msgdma_rx_csr_agent_rp_data),           //          .data
+		.sink_startofpacket (msgdma_rx_csr_agent_rp_startofpacket),  //          .startofpacket
+		.sink_endofpacket   (msgdma_rx_csr_agent_rp_endofpacket),    //          .endofpacket
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_014_src_ready),                  //       src.ready
+		.src_valid          (router_014_src_valid),                  //          .valid
+		.src_data           (router_014_src_data),                   //          .data
+		.src_channel        (router_014_src_channel),                //          .channel
+		.src_startofpacket  (router_014_src_startofpacket),          //          .startofpacket
+		.src_endofpacket    (router_014_src_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_015 (
+		.sink_ready         (onchip_flash_csr_agent_rp_ready),         //      sink.ready
+		.sink_valid         (onchip_flash_csr_agent_rp_valid),         //          .valid
+		.sink_data          (onchip_flash_csr_agent_rp_data),          //          .data
+		.sink_startofpacket (onchip_flash_csr_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (onchip_flash_csr_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                         //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
+		.src_ready          (router_015_src_ready),                    //       src.ready
+		.src_valid          (router_015_src_valid),                    //          .valid
+		.src_data           (router_015_src_data),                     //          .data
+		.src_channel        (router_015_src_channel),                  //          .channel
+		.src_startofpacket  (router_015_src_startofpacket),            //          .startofpacket
+		.src_endofpacket    (router_015_src_endofpacket)               //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_016 (
+		.sink_ready         (udp_generator_csr_agent_rp_ready),         //      sink.ready
+		.sink_valid         (udp_generator_csr_agent_rp_valid),         //          .valid
+		.sink_data          (udp_generator_csr_agent_rp_data),          //          .data
+		.sink_startofpacket (udp_generator_csr_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (udp_generator_csr_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                          //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
+		.src_ready          (router_016_src_ready),                     //       src.ready
+		.src_valid          (router_016_src_valid),                     //          .valid
+		.src_data           (router_016_src_data),                      //          .data
+		.src_channel        (router_016_src_channel),                   //          .channel
+		.src_startofpacket  (router_016_src_startofpacket),             //          .startofpacket
+		.src_endofpacket    (router_016_src_endofpacket)                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_017 (
+		.sink_ready         (sensor_interface_csr_agent_rp_ready),         //      sink.ready
+		.sink_valid         (sensor_interface_csr_agent_rp_valid),         //          .valid
+		.sink_data          (sensor_interface_csr_agent_rp_data),          //          .data
+		.sink_startofpacket (sensor_interface_csr_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (sensor_interface_csr_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                             //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
+		.src_ready          (router_017_src_ready),                        //       src.ready
+		.src_valid          (router_017_src_valid),                        //          .valid
+		.src_data           (router_017_src_data),                         //          .data
+		.src_channel        (router_017_src_channel),                      //          .channel
+		.src_startofpacket  (router_017_src_startofpacket),                //          .startofpacket
+		.src_endofpacket    (router_017_src_endofpacket)                   //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_010 router_018 (
+		.sink_ready         (onchip_flash_data_agent_rp_ready),         //      sink.ready
+		.sink_valid         (onchip_flash_data_agent_rp_valid),         //          .valid
+		.sink_data          (onchip_flash_data_agent_rp_data),          //          .data
+		.sink_startofpacket (onchip_flash_data_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (onchip_flash_data_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                          //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
+		.src_ready          (router_018_src_ready),                     //       src.ready
+		.src_valid          (router_018_src_valid),                     //          .valid
+		.src_data           (router_018_src_data),                      //          .data
+		.src_channel        (router_018_src_channel),                   //          .channel
+		.src_startofpacket  (router_018_src_startofpacket),             //          .startofpacket
+		.src_endofpacket    (router_018_src_endofpacket)                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_010 router_019 (
+		.sink_ready         (cpu_debug_mem_slave_agent_rp_ready),         //      sink.ready
+		.sink_valid         (cpu_debug_mem_slave_agent_rp_valid),         //          .valid
+		.sink_data          (cpu_debug_mem_slave_agent_rp_data),          //          .data
+		.sink_startofpacket (cpu_debug_mem_slave_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (cpu_debug_mem_slave_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                            //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
+		.src_ready          (router_019_src_ready),                       //       src.ready
+		.src_valid          (router_019_src_valid),                       //          .valid
+		.src_data           (router_019_src_data),                        //          .data
+		.src_channel        (router_019_src_channel),                     //          .channel
+		.src_startofpacket  (router_019_src_startofpacket),               //          .startofpacket
+		.src_endofpacket    (router_019_src_endofpacket)                  //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_020 (
+		.sink_ready         (msgdma_tx_prefetcher_csr_agent_rp_ready),         //      sink.ready
+		.sink_valid         (msgdma_tx_prefetcher_csr_agent_rp_valid),         //          .valid
+		.sink_data          (msgdma_tx_prefetcher_csr_agent_rp_data),          //          .data
+		.sink_startofpacket (msgdma_tx_prefetcher_csr_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_tx_prefetcher_csr_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                 //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),           // clk_reset.reset
+		.src_ready          (router_020_src_ready),                            //       src.ready
+		.src_valid          (router_020_src_valid),                            //          .valid
+		.src_data           (router_020_src_data),                             //          .data
+		.src_channel        (router_020_src_channel),                          //          .channel
+		.src_startofpacket  (router_020_src_startofpacket),                    //          .startofpacket
+		.src_endofpacket    (router_020_src_endofpacket)                       //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_021 (
+		.sink_ready         (msgdma_rx_prefetcher_csr_agent_rp_ready),         //      sink.ready
+		.sink_valid         (msgdma_rx_prefetcher_csr_agent_rp_valid),         //          .valid
+		.sink_data          (msgdma_rx_prefetcher_csr_agent_rp_data),          //          .data
+		.sink_startofpacket (msgdma_rx_prefetcher_csr_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (msgdma_rx_prefetcher_csr_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                 //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),           // clk_reset.reset
+		.src_ready          (router_021_src_ready),                            //       src.ready
+		.src_valid          (router_021_src_valid),                            //          .valid
+		.src_data           (router_021_src_data),                             //          .data
+		.src_channel        (router_021_src_channel),                          //          .channel
+		.src_startofpacket  (router_021_src_startofpacket),                    //          .startofpacket
+		.src_endofpacket    (router_021_src_endofpacket)                       //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_022 router_022 (
+		.sink_ready         (descriptor_memory_s1_agent_rp_ready),                  //      sink.ready
+		.sink_valid         (descriptor_memory_s1_agent_rp_valid),                  //          .valid
+		.sink_data          (descriptor_memory_s1_agent_rp_data),                   //          .data
+		.sink_startofpacket (descriptor_memory_s1_agent_rp_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (descriptor_memory_s1_agent_rp_endofpacket),            //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_022_src_ready),                                 //       src.ready
+		.src_valid          (router_022_src_valid),                                 //          .valid
+		.src_data           (router_022_src_data),                                  //          .data
+		.src_channel        (router_022_src_channel),                               //          .channel
+		.src_startofpacket  (router_022_src_startofpacket),                         //          .startofpacket
+		.src_endofpacket    (router_022_src_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_023 (
+		.sink_ready         (sys_clk_timer_s1_agent_rp_ready),                      //      sink.ready
+		.sink_valid         (sys_clk_timer_s1_agent_rp_valid),                      //          .valid
+		.sink_data          (sys_clk_timer_s1_agent_rp_data),                       //          .data
+		.sink_startofpacket (sys_clk_timer_s1_agent_rp_startofpacket),              //          .startofpacket
+		.sink_endofpacket   (sys_clk_timer_s1_agent_rp_endofpacket),                //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_023_src_ready),                                 //       src.ready
+		.src_valid          (router_023_src_valid),                                 //          .valid
+		.src_data           (router_023_src_data),                                  //          .data
+		.src_channel        (router_023_src_channel),                               //          .channel
+		.src_startofpacket  (router_023_src_startofpacket),                         //          .startofpacket
+		.src_endofpacket    (router_023_src_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_024 (
+		.sink_ready         (output_pio_s1_agent_rp_ready),                         //      sink.ready
+		.sink_valid         (output_pio_s1_agent_rp_valid),                         //          .valid
+		.sink_data          (output_pio_s1_agent_rp_data),                          //          .data
+		.sink_startofpacket (output_pio_s1_agent_rp_startofpacket),                 //          .startofpacket
+		.sink_endofpacket   (output_pio_s1_agent_rp_endofpacket),                   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_024_src_ready),                                 //       src.ready
+		.src_valid          (router_024_src_valid),                                 //          .valid
+		.src_data           (router_024_src_data),                                  //          .data
+		.src_channel        (router_024_src_channel),                               //          .channel
+		.src_startofpacket  (router_024_src_startofpacket),                         //          .startofpacket
+		.src_endofpacket    (router_024_src_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_025 (
+		.sink_ready         (button_pio_s1_agent_rp_ready),          //      sink.ready
+		.sink_valid         (button_pio_s1_agent_rp_valid),          //          .valid
+		.sink_data          (button_pio_s1_agent_rp_data),           //          .data
+		.sink_startofpacket (button_pio_s1_agent_rp_startofpacket),  //          .startofpacket
+		.sink_endofpacket   (button_pio_s1_agent_rp_endofpacket),    //          .endofpacket
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_025_src_ready),                  //       src.ready
+		.src_valid          (router_025_src_valid),                  //          .valid
+		.src_data           (router_025_src_data),                   //          .data
+		.src_channel        (router_025_src_channel),                //          .channel
+		.src_startofpacket  (router_025_src_startofpacket),          //          .startofpacket
+		.src_endofpacket    (router_025_src_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_026 (
+		.sink_ready         (debug_uart_s1_agent_rp_ready),          //      sink.ready
+		.sink_valid         (debug_uart_s1_agent_rp_valid),          //          .valid
+		.sink_data          (debug_uart_s1_agent_rp_data),           //          .data
+		.sink_startofpacket (debug_uart_s1_agent_rp_startofpacket),  //          .startofpacket
+		.sink_endofpacket   (debug_uart_s1_agent_rp_endofpacket),    //          .endofpacket
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_026_src_ready),                  //       src.ready
+		.src_valid          (router_026_src_valid),                  //          .valid
+		.src_data           (router_026_src_data),                   //          .data
+		.src_channel        (router_026_src_channel),                //          .channel
+		.src_startofpacket  (router_026_src_startofpacket),          //          .startofpacket
+		.src_endofpacket    (router_026_src_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_009 router_027 (
+		.sink_ready         (frame_timer_s1_agent_rp_ready),         //      sink.ready
+		.sink_valid         (frame_timer_s1_agent_rp_valid),         //          .valid
+		.sink_data          (frame_timer_s1_agent_rp_data),          //          .data
+		.sink_startofpacket (frame_timer_s1_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (frame_timer_s1_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_027_src_ready),                  //       src.ready
+		.src_valid          (router_027_src_valid),                  //          .valid
+		.src_data           (router_027_src_data),                   //          .data
+		.src_channel        (router_027_src_channel),                //          .channel
+		.src_startofpacket  (router_027_src_startofpacket),          //          .startofpacket
+		.src_endofpacket    (router_027_src_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_router_028 router_028 (
+		.sink_ready         (calibration_ram_s1_agent_rp_ready),         //      sink.ready
+		.sink_valid         (calibration_ram_s1_agent_rp_valid),         //          .valid
+		.sink_data          (calibration_ram_s1_agent_rp_data),          //          .data
+		.sink_startofpacket (calibration_ram_s1_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (calibration_ram_s1_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (sys_clk_clk_clk),                           //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
+		.src_ready          (router_028_src_ready),                      //       src.ready
+		.src_valid          (router_028_src_valid),                      //          .valid
+		.src_data           (router_028_src_data),                       //          .data
+		.src_channel        (router_028_src_channel),                    //          .channel
+		.src_startofpacket  (router_028_src_startofpacket),              //          .startofpacket
+		.src_endofpacket    (router_028_src_endofpacket)                 //          .endofpacket
+	);
+
+	altera_merlin_traffic_limiter #(
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.MAX_OUTSTANDING_RESPONSES (36),
+		.PIPELINED                 (0),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.VALID_WIDTH               (21),
+		.ENFORCE_ORDER             (1),
+		.PREVENT_HAZARDS           (0),
+		.SUPPORTS_POSTED_WRITES    (1),
+		.SUPPORTS_NONPOSTED_WRITES (0),
+		.REORDER                   (0)
+	) cpu_data_master_limiter (
+		.clk                    (sys_clk_clk_clk),                               //       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
+		.cmd_sink_ready         (router_src_ready),                              //  cmd_sink.ready
+		.cmd_sink_valid         (router_src_valid),                              //          .valid
+		.cmd_sink_data          (router_src_data),                               //          .data
+		.cmd_sink_channel       (router_src_channel),                            //          .channel
+		.cmd_sink_startofpacket (router_src_startofpacket),                      //          .startofpacket
+		.cmd_sink_endofpacket   (router_src_endofpacket),                        //          .endofpacket
+		.cmd_src_ready          (cpu_data_master_limiter_cmd_src_ready),         //   cmd_src.ready
+		.cmd_src_data           (cpu_data_master_limiter_cmd_src_data),          //          .data
+		.cmd_src_channel        (cpu_data_master_limiter_cmd_src_channel),       //          .channel
+		.cmd_src_startofpacket  (cpu_data_master_limiter_cmd_src_startofpacket), //          .startofpacket
+		.cmd_src_endofpacket    (cpu_data_master_limiter_cmd_src_endofpacket),   //          .endofpacket
+		.rsp_sink_ready         (rsp_mux_src_ready),                             //  rsp_sink.ready
+		.rsp_sink_valid         (rsp_mux_src_valid),                             //          .valid
+		.rsp_sink_channel       (rsp_mux_src_channel),                           //          .channel
+		.rsp_sink_data          (rsp_mux_src_data),                              //          .data
+		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                     //          .startofpacket
+		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                       //          .endofpacket
+		.rsp_src_ready          (cpu_data_master_limiter_rsp_src_ready),         //   rsp_src.ready
+		.rsp_src_valid          (cpu_data_master_limiter_rsp_src_valid),         //          .valid
+		.rsp_src_data           (cpu_data_master_limiter_rsp_src_data),          //          .data
+		.rsp_src_channel        (cpu_data_master_limiter_rsp_src_channel),       //          .channel
+		.rsp_src_startofpacket  (cpu_data_master_limiter_rsp_src_startofpacket), //          .startofpacket
+		.rsp_src_endofpacket    (cpu_data_master_limiter_rsp_src_endofpacket),   //          .endofpacket
+		.cmd_src_valid          (cpu_data_master_limiter_cmd_valid_data)         // cmd_valid.data
+	);
+
+	altera_merlin_traffic_limiter #(
+		.PKT_DEST_ID_H             (107),
+		.PKT_DEST_ID_L             (103),
+		.PKT_SRC_ID_H              (102),
+		.PKT_SRC_ID_L              (98),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_TRANS_POSTED          (66),
+		.PKT_TRANS_WRITE           (67),
+		.MAX_OUTSTANDING_RESPONSES (36),
+		.PIPELINED                 (0),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.VALID_WIDTH               (21),
+		.ENFORCE_ORDER             (1),
+		.PREVENT_HAZARDS           (0),
+		.SUPPORTS_POSTED_WRITES    (1),
+		.SUPPORTS_NONPOSTED_WRITES (0),
+		.REORDER                   (0)
+	) cpu_instruction_master_limiter (
+		.clk                    (sys_clk_clk_clk),                                      //       clk.clk
+		.reset                  (cpu_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
+		.cmd_sink_ready         (router_001_src_ready),                                 //  cmd_sink.ready
+		.cmd_sink_valid         (router_001_src_valid),                                 //          .valid
+		.cmd_sink_data          (router_001_src_data),                                  //          .data
+		.cmd_sink_channel       (router_001_src_channel),                               //          .channel
+		.cmd_sink_startofpacket (router_001_src_startofpacket),                         //          .startofpacket
+		.cmd_sink_endofpacket   (router_001_src_endofpacket),                           //          .endofpacket
+		.cmd_src_ready          (cpu_instruction_master_limiter_cmd_src_ready),         //   cmd_src.ready
+		.cmd_src_data           (cpu_instruction_master_limiter_cmd_src_data),          //          .data
+		.cmd_src_channel        (cpu_instruction_master_limiter_cmd_src_channel),       //          .channel
+		.cmd_src_startofpacket  (cpu_instruction_master_limiter_cmd_src_startofpacket), //          .startofpacket
+		.cmd_src_endofpacket    (cpu_instruction_master_limiter_cmd_src_endofpacket),   //          .endofpacket
+		.rsp_sink_ready         (rsp_mux_001_src_ready),                                //  rsp_sink.ready
+		.rsp_sink_valid         (rsp_mux_001_src_valid),                                //          .valid
+		.rsp_sink_channel       (rsp_mux_001_src_channel),                              //          .channel
+		.rsp_sink_data          (rsp_mux_001_src_data),                                 //          .data
+		.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket),                        //          .startofpacket
+		.rsp_sink_endofpacket   (rsp_mux_001_src_endofpacket),                          //          .endofpacket
+		.rsp_src_ready          (cpu_instruction_master_limiter_rsp_src_ready),         //   rsp_src.ready
+		.rsp_src_valid          (cpu_instruction_master_limiter_rsp_src_valid),         //          .valid
+		.rsp_src_data           (cpu_instruction_master_limiter_rsp_src_data),          //          .data
+		.rsp_src_channel        (cpu_instruction_master_limiter_rsp_src_channel),       //          .channel
+		.rsp_src_startofpacket  (cpu_instruction_master_limiter_rsp_src_startofpacket), //          .startofpacket
+		.rsp_src_endofpacket    (cpu_instruction_master_limiter_rsp_src_endofpacket),   //          .endofpacket
+		.cmd_src_valid          (cpu_instruction_master_limiter_cmd_valid_data)         // cmd_valid.data
+	);
+
+	altera_merlin_burst_adapter #(
+		.PKT_ADDR_H                (64),
+		.PKT_ADDR_L                (36),
+		.PKT_BEGIN_BURST           (96),
+		.PKT_BYTE_CNT_H            (79),
+		.PKT_BYTE_CNT_L            (71),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_BURST_SIZE_H          (91),
+		.PKT_BURST_SIZE_L          (89),
+		.PKT_BURST_TYPE_H          (93),
+		.PKT_BURST_TYPE_L          (92),
+		.PKT_BURSTWRAP_H           (88),
+		.PKT_BURSTWRAP_L           (80),
+		.PKT_TRANS_COMPRESSED_READ (65),
+		.PKT_TRANS_WRITE           (67),
+		.PKT_TRANS_READ            (68),
+		.OUT_NARROW_SIZE           (0),
+		.IN_NARROW_SIZE            (0),
+		.OUT_FIXED                 (0),
+		.OUT_COMPLETE_WRAP         (0),
+		.ST_DATA_W                 (121),
+		.ST_CHANNEL_W              (21),
+		.OUT_BYTE_CNT_H            (79),
+		.OUT_BURSTWRAP_H           (87),
+		.COMPRESSED_READ_SUPPORT   (0),
+		.BYTEENABLE_SYNTHESIS      (1),
+		.PIPE_INPUTS               (0),
+		.NO_WRAP_SUPPORT           (0),
+		.INCOMPLETE_WRAP_SUPPORT   (0),
+		.BURSTWRAP_CONST_MASK      (3),
+		.BURSTWRAP_CONST_VALUE     (3),
+		.ADAPTER_VERSION           ("13.1")
+	) ext_flash_avl_mem_burst_adapter (
+		.clk                   (ext_flash_clock_bridge_out_clk_clk),                    //       cr0.clk
+		.reset                 (ext_flash_reset_reset_bridge_in_reset_reset),           // cr0_reset.reset
+		.sink0_valid           (cmd_mux_002_src_valid),                                 //     sink0.valid
+		.sink0_data            (cmd_mux_002_src_data),                                  //          .data
+		.sink0_channel         (cmd_mux_002_src_channel),                               //          .channel
+		.sink0_startofpacket   (cmd_mux_002_src_startofpacket),                         //          .startofpacket
+		.sink0_endofpacket     (cmd_mux_002_src_endofpacket),                           //          .endofpacket
+		.sink0_ready           (cmd_mux_002_src_ready),                                 //          .ready
+		.source0_valid         (ext_flash_avl_mem_burst_adapter_source0_valid),         //   source0.valid
+		.source0_data          (ext_flash_avl_mem_burst_adapter_source0_data),          //          .data
+		.source0_channel       (ext_flash_avl_mem_burst_adapter_source0_channel),       //          .channel
+		.source0_startofpacket (ext_flash_avl_mem_burst_adapter_source0_startofpacket), //          .startofpacket
+		.source0_endofpacket   (ext_flash_avl_mem_burst_adapter_source0_endofpacket),   //          .endofpacket
+		.source0_ready         (ext_flash_avl_mem_burst_adapter_source0_ready)          //          .ready
+	);
+
+	altera_merlin_burst_adapter #(
+		.PKT_ADDR_H                (46),
+		.PKT_ADDR_L                (18),
+		.PKT_BEGIN_BURST           (78),
+		.PKT_BYTE_CNT_H            (61),
+		.PKT_BYTE_CNT_L            (53),
+		.PKT_BYTEEN_H              (17),
+		.PKT_BYTEEN_L              (16),
+		.PKT_BURST_SIZE_H          (73),
+		.PKT_BURST_SIZE_L          (71),
+		.PKT_BURST_TYPE_H          (75),
+		.PKT_BURST_TYPE_L          (74),
+		.PKT_BURSTWRAP_H           (70),
+		.PKT_BURSTWRAP_L           (62),
+		.PKT_TRANS_COMPRESSED_READ (47),
+		.PKT_TRANS_WRITE           (49),
+		.PKT_TRANS_READ            (50),
+		.OUT_NARROW_SIZE           (0),
+		.IN_NARROW_SIZE            (0),
+		.OUT_FIXED                 (0),
+		.OUT_COMPLETE_WRAP         (0),
+		.ST_DATA_W                 (103),
+		.ST_CHANNEL_W              (21),
+		.OUT_BYTE_CNT_H            (54),
+		.OUT_BURSTWRAP_H           (70),
+		.COMPRESSED_READ_SUPPORT   (0),
+		.BYTEENABLE_SYNTHESIS      (1),
+		.PIPE_INPUTS               (0),
+		.NO_WRAP_SUPPORT           (0),
+		.INCOMPLETE_WRAP_SUPPORT   (0),
+		.BURSTWRAP_CONST_MASK      (511),
+		.BURSTWRAP_CONST_VALUE     (511),
+		.ADAPTER_VERSION           ("13.1")
+	) calibration_ram_s1_burst_adapter (
+		.clk                   (sys_clk_clk_clk),                                        //       cr0.clk
+		.reset                 (cpu_reset_reset_bridge_in_reset_reset),                  // cr0_reset.reset
+		.sink0_valid           (calibration_ram_s1_cmd_width_adapter_src_valid),         //     sink0.valid
+		.sink0_data            (calibration_ram_s1_cmd_width_adapter_src_data),          //          .data
+		.sink0_channel         (calibration_ram_s1_cmd_width_adapter_src_channel),       //          .channel
+		.sink0_startofpacket   (calibration_ram_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
+		.sink0_endofpacket     (calibration_ram_s1_cmd_width_adapter_src_endofpacket),   //          .endofpacket
+		.sink0_ready           (calibration_ram_s1_cmd_width_adapter_src_ready),         //          .ready
+		.source0_valid         (calibration_ram_s1_burst_adapter_source0_valid),         //   source0.valid
+		.source0_data          (calibration_ram_s1_burst_adapter_source0_data),          //          .data
+		.source0_channel       (calibration_ram_s1_burst_adapter_source0_channel),       //          .channel
+		.source0_startofpacket (calibration_ram_s1_burst_adapter_source0_startofpacket), //          .startofpacket
+		.source0_endofpacket   (calibration_ram_s1_burst_adapter_source0_endofpacket),   //          .endofpacket
+		.source0_ready         (calibration_ram_s1_burst_adapter_source0_ready)          //          .ready
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux cmd_demux (
+		.clk                 (sys_clk_clk_clk),                               //        clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset),         //  clk_reset.reset
+		.sink_ready          (cpu_data_master_limiter_cmd_src_ready),         //       sink.ready
+		.sink_channel        (cpu_data_master_limiter_cmd_src_channel),       //           .channel
+		.sink_data           (cpu_data_master_limiter_cmd_src_data),          //           .data
+		.sink_startofpacket  (cpu_data_master_limiter_cmd_src_startofpacket), //           .startofpacket
+		.sink_endofpacket    (cpu_data_master_limiter_cmd_src_endofpacket),   //           .endofpacket
+		.sink_valid          (cpu_data_master_limiter_cmd_valid_data),        // sink_valid.data
+		.src0_ready          (cmd_demux_src0_ready),                          //       src0.ready
+		.src0_valid          (cmd_demux_src0_valid),                          //           .valid
+		.src0_data           (cmd_demux_src0_data),                           //           .data
+		.src0_channel        (cmd_demux_src0_channel),                        //           .channel
+		.src0_startofpacket  (cmd_demux_src0_startofpacket),                  //           .startofpacket
+		.src0_endofpacket    (cmd_demux_src0_endofpacket),                    //           .endofpacket
+		.src1_ready          (cmd_demux_src1_ready),                          //       src1.ready
+		.src1_valid          (cmd_demux_src1_valid),                          //           .valid
+		.src1_data           (cmd_demux_src1_data),                           //           .data
+		.src1_channel        (cmd_demux_src1_channel),                        //           .channel
+		.src1_startofpacket  (cmd_demux_src1_startofpacket),                  //           .startofpacket
+		.src1_endofpacket    (cmd_demux_src1_endofpacket),                    //           .endofpacket
+		.src2_ready          (cmd_demux_src2_ready),                          //       src2.ready
+		.src2_valid          (cmd_demux_src2_valid),                          //           .valid
+		.src2_data           (cmd_demux_src2_data),                           //           .data
+		.src2_channel        (cmd_demux_src2_channel),                        //           .channel
+		.src2_startofpacket  (cmd_demux_src2_startofpacket),                  //           .startofpacket
+		.src2_endofpacket    (cmd_demux_src2_endofpacket),                    //           .endofpacket
+		.src3_ready          (cmd_demux_src3_ready),                          //       src3.ready
+		.src3_valid          (cmd_demux_src3_valid),                          //           .valid
+		.src3_data           (cmd_demux_src3_data),                           //           .data
+		.src3_channel        (cmd_demux_src3_channel),                        //           .channel
+		.src3_startofpacket  (cmd_demux_src3_startofpacket),                  //           .startofpacket
+		.src3_endofpacket    (cmd_demux_src3_endofpacket),                    //           .endofpacket
+		.src4_ready          (cmd_demux_src4_ready),                          //       src4.ready
+		.src4_valid          (cmd_demux_src4_valid),                          //           .valid
+		.src4_data           (cmd_demux_src4_data),                           //           .data
+		.src4_channel        (cmd_demux_src4_channel),                        //           .channel
+		.src4_startofpacket  (cmd_demux_src4_startofpacket),                  //           .startofpacket
+		.src4_endofpacket    (cmd_demux_src4_endofpacket),                    //           .endofpacket
+		.src5_ready          (cmd_demux_src5_ready),                          //       src5.ready
+		.src5_valid          (cmd_demux_src5_valid),                          //           .valid
+		.src5_data           (cmd_demux_src5_data),                           //           .data
+		.src5_channel        (cmd_demux_src5_channel),                        //           .channel
+		.src5_startofpacket  (cmd_demux_src5_startofpacket),                  //           .startofpacket
+		.src5_endofpacket    (cmd_demux_src5_endofpacket),                    //           .endofpacket
+		.src6_ready          (cmd_demux_src6_ready),                          //       src6.ready
+		.src6_valid          (cmd_demux_src6_valid),                          //           .valid
+		.src6_data           (cmd_demux_src6_data),                           //           .data
+		.src6_channel        (cmd_demux_src6_channel),                        //           .channel
+		.src6_startofpacket  (cmd_demux_src6_startofpacket),                  //           .startofpacket
+		.src6_endofpacket    (cmd_demux_src6_endofpacket),                    //           .endofpacket
+		.src7_ready          (cmd_demux_src7_ready),                          //       src7.ready
+		.src7_valid          (cmd_demux_src7_valid),                          //           .valid
+		.src7_data           (cmd_demux_src7_data),                           //           .data
+		.src7_channel        (cmd_demux_src7_channel),                        //           .channel
+		.src7_startofpacket  (cmd_demux_src7_startofpacket),                  //           .startofpacket
+		.src7_endofpacket    (cmd_demux_src7_endofpacket),                    //           .endofpacket
+		.src8_ready          (cmd_demux_src8_ready),                          //       src8.ready
+		.src8_valid          (cmd_demux_src8_valid),                          //           .valid
+		.src8_data           (cmd_demux_src8_data),                           //           .data
+		.src8_channel        (cmd_demux_src8_channel),                        //           .channel
+		.src8_startofpacket  (cmd_demux_src8_startofpacket),                  //           .startofpacket
+		.src8_endofpacket    (cmd_demux_src8_endofpacket),                    //           .endofpacket
+		.src9_ready          (cmd_demux_src9_ready),                          //       src9.ready
+		.src9_valid          (cmd_demux_src9_valid),                          //           .valid
+		.src9_data           (cmd_demux_src9_data),                           //           .data
+		.src9_channel        (cmd_demux_src9_channel),                        //           .channel
+		.src9_startofpacket  (cmd_demux_src9_startofpacket),                  //           .startofpacket
+		.src9_endofpacket    (cmd_demux_src9_endofpacket),                    //           .endofpacket
+		.src10_ready         (cmd_demux_src10_ready),                         //      src10.ready
+		.src10_valid         (cmd_demux_src10_valid),                         //           .valid
+		.src10_data          (cmd_demux_src10_data),                          //           .data
+		.src10_channel       (cmd_demux_src10_channel),                       //           .channel
+		.src10_startofpacket (cmd_demux_src10_startofpacket),                 //           .startofpacket
+		.src10_endofpacket   (cmd_demux_src10_endofpacket),                   //           .endofpacket
+		.src11_ready         (cmd_demux_src11_ready),                         //      src11.ready
+		.src11_valid         (cmd_demux_src11_valid),                         //           .valid
+		.src11_data          (cmd_demux_src11_data),                          //           .data
+		.src11_channel       (cmd_demux_src11_channel),                       //           .channel
+		.src11_startofpacket (cmd_demux_src11_startofpacket),                 //           .startofpacket
+		.src11_endofpacket   (cmd_demux_src11_endofpacket),                   //           .endofpacket
+		.src12_ready         (cmd_demux_src12_ready),                         //      src12.ready
+		.src12_valid         (cmd_demux_src12_valid),                         //           .valid
+		.src12_data          (cmd_demux_src12_data),                          //           .data
+		.src12_channel       (cmd_demux_src12_channel),                       //           .channel
+		.src12_startofpacket (cmd_demux_src12_startofpacket),                 //           .startofpacket
+		.src12_endofpacket   (cmd_demux_src12_endofpacket),                   //           .endofpacket
+		.src13_ready         (cmd_demux_src13_ready),                         //      src13.ready
+		.src13_valid         (cmd_demux_src13_valid),                         //           .valid
+		.src13_data          (cmd_demux_src13_data),                          //           .data
+		.src13_channel       (cmd_demux_src13_channel),                       //           .channel
+		.src13_startofpacket (cmd_demux_src13_startofpacket),                 //           .startofpacket
+		.src13_endofpacket   (cmd_demux_src13_endofpacket),                   //           .endofpacket
+		.src14_ready         (cmd_demux_src14_ready),                         //      src14.ready
+		.src14_valid         (cmd_demux_src14_valid),                         //           .valid
+		.src14_data          (cmd_demux_src14_data),                          //           .data
+		.src14_channel       (cmd_demux_src14_channel),                       //           .channel
+		.src14_startofpacket (cmd_demux_src14_startofpacket),                 //           .startofpacket
+		.src14_endofpacket   (cmd_demux_src14_endofpacket),                   //           .endofpacket
+		.src15_ready         (cmd_demux_src15_ready),                         //      src15.ready
+		.src15_valid         (cmd_demux_src15_valid),                         //           .valid
+		.src15_data          (cmd_demux_src15_data),                          //           .data
+		.src15_channel       (cmd_demux_src15_channel),                       //           .channel
+		.src15_startofpacket (cmd_demux_src15_startofpacket),                 //           .startofpacket
+		.src15_endofpacket   (cmd_demux_src15_endofpacket),                   //           .endofpacket
+		.src16_ready         (cmd_demux_src16_ready),                         //      src16.ready
+		.src16_valid         (cmd_demux_src16_valid),                         //           .valid
+		.src16_data          (cmd_demux_src16_data),                          //           .data
+		.src16_channel       (cmd_demux_src16_channel),                       //           .channel
+		.src16_startofpacket (cmd_demux_src16_startofpacket),                 //           .startofpacket
+		.src16_endofpacket   (cmd_demux_src16_endofpacket),                   //           .endofpacket
+		.src17_ready         (cmd_demux_src17_ready),                         //      src17.ready
+		.src17_valid         (cmd_demux_src17_valid),                         //           .valid
+		.src17_data          (cmd_demux_src17_data),                          //           .data
+		.src17_channel       (cmd_demux_src17_channel),                       //           .channel
+		.src17_startofpacket (cmd_demux_src17_startofpacket),                 //           .startofpacket
+		.src17_endofpacket   (cmd_demux_src17_endofpacket),                   //           .endofpacket
+		.src18_ready         (cmd_demux_src18_ready),                         //      src18.ready
+		.src18_valid         (cmd_demux_src18_valid),                         //           .valid
+		.src18_data          (cmd_demux_src18_data),                          //           .data
+		.src18_channel       (cmd_demux_src18_channel),                       //           .channel
+		.src18_startofpacket (cmd_demux_src18_startofpacket),                 //           .startofpacket
+		.src18_endofpacket   (cmd_demux_src18_endofpacket),                   //           .endofpacket
+		.src19_ready         (cmd_demux_src19_ready),                         //      src19.ready
+		.src19_valid         (cmd_demux_src19_valid),                         //           .valid
+		.src19_data          (cmd_demux_src19_data),                          //           .data
+		.src19_channel       (cmd_demux_src19_channel),                       //           .channel
+		.src19_startofpacket (cmd_demux_src19_startofpacket),                 //           .startofpacket
+		.src19_endofpacket   (cmd_demux_src19_endofpacket),                   //           .endofpacket
+		.src20_ready         (cmd_demux_src20_ready),                         //      src20.ready
+		.src20_valid         (cmd_demux_src20_valid),                         //           .valid
+		.src20_data          (cmd_demux_src20_data),                          //           .data
+		.src20_channel       (cmd_demux_src20_channel),                       //           .channel
+		.src20_startofpacket (cmd_demux_src20_startofpacket),                 //           .startofpacket
+		.src20_endofpacket   (cmd_demux_src20_endofpacket)                    //           .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_001 cmd_demux_001 (
+		.clk                (sys_clk_clk_clk),                                      //        clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                //  clk_reset.reset
+		.sink_ready         (cpu_instruction_master_limiter_cmd_src_ready),         //       sink.ready
+		.sink_channel       (cpu_instruction_master_limiter_cmd_src_channel),       //           .channel
+		.sink_data          (cpu_instruction_master_limiter_cmd_src_data),          //           .data
+		.sink_startofpacket (cpu_instruction_master_limiter_cmd_src_startofpacket), //           .startofpacket
+		.sink_endofpacket   (cpu_instruction_master_limiter_cmd_src_endofpacket),   //           .endofpacket
+		.sink_valid         (cpu_instruction_master_limiter_cmd_valid_data),        // sink_valid.data
+		.src0_ready         (cmd_demux_001_src0_ready),                             //       src0.ready
+		.src0_valid         (cmd_demux_001_src0_valid),                             //           .valid
+		.src0_data          (cmd_demux_001_src0_data),                              //           .data
+		.src0_channel       (cmd_demux_001_src0_channel),                           //           .channel
+		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                     //           .startofpacket
+		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),                       //           .endofpacket
+		.src1_ready         (cmd_demux_001_src1_ready),                             //       src1.ready
+		.src1_valid         (cmd_demux_001_src1_valid),                             //           .valid
+		.src1_data          (cmd_demux_001_src1_data),                              //           .data
+		.src1_channel       (cmd_demux_001_src1_channel),                           //           .channel
+		.src1_startofpacket (cmd_demux_001_src1_startofpacket),                     //           .startofpacket
+		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),                       //           .endofpacket
+		.src2_ready         (cmd_demux_001_src2_ready),                             //       src2.ready
+		.src2_valid         (cmd_demux_001_src2_valid),                             //           .valid
+		.src2_data          (cmd_demux_001_src2_data),                              //           .data
+		.src2_channel       (cmd_demux_001_src2_channel),                           //           .channel
+		.src2_startofpacket (cmd_demux_001_src2_startofpacket),                     //           .startofpacket
+		.src2_endofpacket   (cmd_demux_001_src2_endofpacket),                       //           .endofpacket
+		.src3_ready         (cmd_demux_001_src3_ready),                             //       src3.ready
+		.src3_valid         (cmd_demux_001_src3_valid),                             //           .valid
+		.src3_data          (cmd_demux_001_src3_data),                              //           .data
+		.src3_channel       (cmd_demux_001_src3_channel),                           //           .channel
+		.src3_startofpacket (cmd_demux_001_src3_startofpacket),                     //           .startofpacket
+		.src3_endofpacket   (cmd_demux_001_src3_endofpacket)                        //           .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_002 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_002_src_ready),                  //      sink.ready
+		.sink_channel       (router_002_src_channel),                //          .channel
+		.sink_data          (router_002_src_data),                   //          .data
+		.sink_startofpacket (router_002_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_002_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_002_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_002_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_002_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_002_src0_data),               //          .data
+		.src0_channel       (cmd_demux_002_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_002_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_002_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_003 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_003_src_ready),                  //      sink.ready
+		.sink_channel       (router_003_src_channel),                //          .channel
+		.sink_data          (router_003_src_data),                   //          .data
+		.sink_startofpacket (router_003_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_003_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_003_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_003_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_003_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_003_src0_data),               //          .data
+		.src0_channel       (cmd_demux_003_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_003_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_003_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_004 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_004_src_ready),                  //      sink.ready
+		.sink_channel       (router_004_src_channel),                //          .channel
+		.sink_data          (router_004_src_data),                   //          .data
+		.sink_startofpacket (router_004_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_004_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_004_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_004_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_004_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_004_src0_data),               //          .data
+		.src0_channel       (cmd_demux_004_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_004_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_004_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_005 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_005_src_ready),                  //      sink.ready
+		.sink_channel       (router_005_src_channel),                //          .channel
+		.sink_data          (router_005_src_data),                   //          .data
+		.sink_startofpacket (router_005_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_005_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_005_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_005_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_005_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_005_src0_data),               //          .data
+		.src0_channel       (cmd_demux_005_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_005_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_005_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_006 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_006_src_ready),                  //      sink.ready
+		.sink_channel       (router_006_src_channel),                //          .channel
+		.sink_data          (router_006_src_data),                   //          .data
+		.sink_startofpacket (router_006_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_006_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_006_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_006_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_006_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_006_src0_data),               //          .data
+		.src0_channel       (cmd_demux_006_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_006_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_006_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 cmd_demux_007 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_007_src_ready),                  //      sink.ready
+		.sink_channel       (router_007_src_channel),                //          .channel
+		.sink_data          (router_007_src_data),                   //          .data
+		.sink_startofpacket (router_007_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_007_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_007_src_valid),                  //          .valid
+		.src0_ready         (cmd_demux_007_src0_ready),              //      src0.ready
+		.src0_valid         (cmd_demux_007_src0_valid),              //          .valid
+		.src0_data          (cmd_demux_007_src0_data),               //          .data
+		.src0_channel       (cmd_demux_007_src0_channel),            //          .channel
+		.src0_startofpacket (cmd_demux_007_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (cmd_demux_007_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux cmd_mux (
+		.clk                 (ddr3_ram_afi_clk_clk),                                      //       clk.clk
+		.reset               (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_src_ready),                                         //       src.ready
+		.src_valid           (cmd_mux_src_valid),                                         //          .valid
+		.src_data            (cmd_mux_src_data),                                          //          .data
+		.src_channel         (cmd_mux_src_channel),                                       //          .channel
+		.src_startofpacket   (cmd_mux_src_startofpacket),                                 //          .startofpacket
+		.src_endofpacket     (cmd_mux_src_endofpacket),                                   //          .endofpacket
+		.sink0_ready         (crosser_out_ready),                                         //     sink0.ready
+		.sink0_valid         (crosser_out_valid),                                         //          .valid
+		.sink0_channel       (crosser_out_channel),                                       //          .channel
+		.sink0_data          (crosser_out_data),                                          //          .data
+		.sink0_startofpacket (crosser_out_startofpacket),                                 //          .startofpacket
+		.sink0_endofpacket   (crosser_out_endofpacket),                                   //          .endofpacket
+		.sink1_ready         (crosser_003_out_ready),                                     //     sink1.ready
+		.sink1_valid         (crosser_003_out_valid),                                     //          .valid
+		.sink1_channel       (crosser_003_out_channel),                                   //          .channel
+		.sink1_data          (crosser_003_out_data),                                      //          .data
+		.sink1_startofpacket (crosser_003_out_startofpacket),                             //          .startofpacket
+		.sink1_endofpacket   (crosser_003_out_endofpacket),                               //          .endofpacket
+		.sink2_ready         (crosser_005_out_ready),                                     //     sink2.ready
+		.sink2_valid         (crosser_005_out_valid),                                     //          .valid
+		.sink2_channel       (crosser_005_out_channel),                                   //          .channel
+		.sink2_data          (crosser_005_out_data),                                      //          .data
+		.sink2_startofpacket (crosser_005_out_startofpacket),                             //          .startofpacket
+		.sink2_endofpacket   (crosser_005_out_endofpacket),                               //          .endofpacket
+		.sink3_ready         (crosser_006_out_ready),                                     //     sink3.ready
+		.sink3_valid         (crosser_006_out_valid),                                     //          .valid
+		.sink3_channel       (crosser_006_out_channel),                                   //          .channel
+		.sink3_data          (crosser_006_out_data),                                      //          .data
+		.sink3_startofpacket (crosser_006_out_startofpacket),                             //          .startofpacket
+		.sink3_endofpacket   (crosser_006_out_endofpacket)                                //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_001 (
+		.clk                 (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset               (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_001_src_ready),                       //       src.ready
+		.src_valid           (cmd_mux_001_src_valid),                       //          .valid
+		.src_data            (cmd_mux_001_src_data),                        //          .data
+		.src_channel         (cmd_mux_001_src_channel),                     //          .channel
+		.src_startofpacket   (cmd_mux_001_src_startofpacket),               //          .startofpacket
+		.src_endofpacket     (cmd_mux_001_src_endofpacket),                 //          .endofpacket
+		.sink0_ready         (crosser_001_out_ready),                       //     sink0.ready
+		.sink0_valid         (crosser_001_out_valid),                       //          .valid
+		.sink0_channel       (crosser_001_out_channel),                     //          .channel
+		.sink0_data          (crosser_001_out_data),                        //          .data
+		.sink0_startofpacket (crosser_001_out_startofpacket),               //          .startofpacket
+		.sink0_endofpacket   (crosser_001_out_endofpacket)                  //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
+		.clk                 (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset               (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_002_src_ready),                       //       src.ready
+		.src_valid           (cmd_mux_002_src_valid),                       //          .valid
+		.src_data            (cmd_mux_002_src_data),                        //          .data
+		.src_channel         (cmd_mux_002_src_channel),                     //          .channel
+		.src_startofpacket   (cmd_mux_002_src_startofpacket),               //          .startofpacket
+		.src_endofpacket     (cmd_mux_002_src_endofpacket),                 //          .endofpacket
+		.sink0_ready         (crosser_002_out_ready),                       //     sink0.ready
+		.sink0_valid         (crosser_002_out_valid),                       //          .valid
+		.sink0_channel       (crosser_002_out_channel),                     //          .channel
+		.sink0_data          (crosser_002_out_data),                        //          .data
+		.sink0_startofpacket (crosser_002_out_startofpacket),               //          .startofpacket
+		.sink0_endofpacket   (crosser_002_out_endofpacket),                 //          .endofpacket
+		.sink1_ready         (crosser_004_out_ready),                       //     sink1.ready
+		.sink1_valid         (crosser_004_out_valid),                       //          .valid
+		.sink1_channel       (crosser_004_out_channel),                     //          .channel
+		.sink1_data          (crosser_004_out_data),                        //          .data
+		.sink1_startofpacket (crosser_004_out_startofpacket),               //          .startofpacket
+		.sink1_endofpacket   (crosser_004_out_endofpacket)                  //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_003 (
+		.clk                 (sys_clk_clk_clk),                                      //       clk.clk
+		.reset               (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_003_src_ready),                                //       src.ready
+		.src_valid           (cmd_mux_003_src_valid),                                //          .valid
+		.src_data            (cmd_mux_003_src_data),                                 //          .data
+		.src_channel         (cmd_mux_003_src_channel),                              //          .channel
+		.src_startofpacket   (cmd_mux_003_src_startofpacket),                        //          .startofpacket
+		.src_endofpacket     (cmd_mux_003_src_endofpacket),                          //          .endofpacket
+		.sink0_ready         (cmd_demux_src3_ready),                                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src3_valid),                                 //          .valid
+		.sink0_channel       (cmd_demux_src3_channel),                               //          .channel
+		.sink0_data          (cmd_demux_src3_data),                                  //          .data
+		.sink0_startofpacket (cmd_demux_src3_startofpacket),                         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src3_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_004 (
+		.clk                 (sys_clk_clk_clk),                                      //       clk.clk
+		.reset               (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_004_src_ready),                                //       src.ready
+		.src_valid           (cmd_mux_004_src_valid),                                //          .valid
+		.src_data            (cmd_mux_004_src_data),                                 //          .data
+		.src_channel         (cmd_mux_004_src_channel),                              //          .channel
+		.src_startofpacket   (cmd_mux_004_src_startofpacket),                        //          .startofpacket
+		.src_endofpacket     (cmd_mux_004_src_endofpacket),                          //          .endofpacket
+		.sink0_ready         (cmd_demux_src4_ready),                                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src4_valid),                                 //          .valid
+		.sink0_channel       (cmd_demux_src4_channel),                               //          .channel
+		.sink0_data          (cmd_demux_src4_data),                                  //          .data
+		.sink0_startofpacket (cmd_demux_src4_startofpacket),                         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src4_endofpacket)                            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_005 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_005_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_005_src_valid),                 //          .valid
+		.src_data            (cmd_mux_005_src_data),                  //          .data
+		.src_channel         (cmd_mux_005_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_005_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_005_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src5_ready),                  //     sink0.ready
+		.sink0_valid         (cmd_demux_src5_valid),                  //          .valid
+		.sink0_channel       (cmd_demux_src5_channel),                //          .channel
+		.sink0_data          (cmd_demux_src5_data),                   //          .data
+		.sink0_startofpacket (cmd_demux_src5_startofpacket),          //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src5_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_006 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_006_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_006_src_valid),                 //          .valid
+		.src_data            (cmd_mux_006_src_data),                  //          .data
+		.src_channel         (cmd_mux_006_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_006_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_006_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src6_ready),                  //     sink0.ready
+		.sink0_valid         (cmd_demux_src6_valid),                  //          .valid
+		.sink0_channel       (cmd_demux_src6_channel),                //          .channel
+		.sink0_data          (cmd_demux_src6_data),                   //          .data
+		.sink0_startofpacket (cmd_demux_src6_startofpacket),          //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src6_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_007 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_007_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_007_src_valid),                 //          .valid
+		.src_data            (cmd_mux_007_src_data),                  //          .data
+		.src_channel         (cmd_mux_007_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_007_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_007_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src7_ready),                  //     sink0.ready
+		.sink0_valid         (cmd_demux_src7_valid),                  //          .valid
+		.sink0_channel       (cmd_demux_src7_channel),                //          .channel
+		.sink0_data          (cmd_demux_src7_data),                   //          .data
+		.sink0_startofpacket (cmd_demux_src7_startofpacket),          //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src7_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_008 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_008_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_008_src_valid),                 //          .valid
+		.src_data            (cmd_mux_008_src_data),                  //          .data
+		.src_channel         (cmd_mux_008_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_008_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_008_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src8_ready),                  //     sink0.ready
+		.sink0_valid         (cmd_demux_src8_valid),                  //          .valid
+		.sink0_channel       (cmd_demux_src8_channel),                //          .channel
+		.sink0_data          (cmd_demux_src8_data),                   //          .data
+		.sink0_startofpacket (cmd_demux_src8_startofpacket),          //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src8_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_009 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_009_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_009_src_valid),                 //          .valid
+		.src_data            (cmd_mux_009_src_data),                  //          .data
+		.src_channel         (cmd_mux_009_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_009_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_009_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src9_ready),                  //     sink0.ready
+		.sink0_valid         (cmd_demux_src9_valid),                  //          .valid
+		.sink0_channel       (cmd_demux_src9_channel),                //          .channel
+		.sink0_data          (cmd_demux_src9_data),                   //          .data
+		.sink0_startofpacket (cmd_demux_src9_startofpacket),          //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src9_endofpacket)             //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_002 cmd_mux_010 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_010_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_010_src_valid),                 //          .valid
+		.src_data            (cmd_mux_010_src_data),                  //          .data
+		.src_channel         (cmd_mux_010_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_010_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_010_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src10_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src10_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src10_channel),               //          .channel
+		.sink0_data          (cmd_demux_src10_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src10_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src10_endofpacket),           //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src2_ready),              //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src2_valid),              //          .valid
+		.sink1_channel       (cmd_demux_001_src2_channel),            //          .channel
+		.sink1_data          (cmd_demux_001_src2_data),               //          .data
+		.sink1_startofpacket (cmd_demux_001_src2_startofpacket),      //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src2_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_002 cmd_mux_011 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_011_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_011_src_valid),                 //          .valid
+		.src_data            (cmd_mux_011_src_data),                  //          .data
+		.src_channel         (cmd_mux_011_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_011_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_011_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src11_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src11_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src11_channel),               //          .channel
+		.sink0_data          (cmd_demux_src11_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src11_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src11_endofpacket),           //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src3_ready),              //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src3_valid),              //          .valid
+		.sink1_channel       (cmd_demux_001_src3_channel),            //          .channel
+		.sink1_data          (cmd_demux_001_src3_data),               //          .data
+		.sink1_startofpacket (cmd_demux_001_src3_startofpacket),      //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src3_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_012 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_012_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_012_src_valid),                 //          .valid
+		.src_data            (cmd_mux_012_src_data),                  //          .data
+		.src_channel         (cmd_mux_012_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_012_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_012_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src12_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src12_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src12_channel),               //          .channel
+		.sink0_data          (cmd_demux_src12_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src12_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src12_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_013 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_013_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_013_src_valid),                 //          .valid
+		.src_data            (cmd_mux_013_src_data),                  //          .data
+		.src_channel         (cmd_mux_013_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_013_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_013_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src13_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src13_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src13_channel),               //          .channel
+		.sink0_data          (cmd_demux_src13_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src13_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src13_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_014 cmd_mux_014 (
+		.clk                 (sys_clk_clk_clk),                                      //       clk.clk
+		.reset               (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_014_src_ready),                                //       src.ready
+		.src_valid           (cmd_mux_014_src_valid),                                //          .valid
+		.src_data            (cmd_mux_014_src_data),                                 //          .data
+		.src_channel         (cmd_mux_014_src_channel),                              //          .channel
+		.src_startofpacket   (cmd_mux_014_src_startofpacket),                        //          .startofpacket
+		.src_endofpacket     (cmd_mux_014_src_endofpacket),                          //          .endofpacket
+		.sink0_ready         (cmd_demux_src14_ready),                                //     sink0.ready
+		.sink0_valid         (cmd_demux_src14_valid),                                //          .valid
+		.sink0_channel       (cmd_demux_src14_channel),                              //          .channel
+		.sink0_data          (cmd_demux_src14_data),                                 //          .data
+		.sink0_startofpacket (cmd_demux_src14_startofpacket),                        //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src14_endofpacket),                          //          .endofpacket
+		.sink1_ready         (cmd_demux_004_src0_ready),                             //     sink1.ready
+		.sink1_valid         (cmd_demux_004_src0_valid),                             //          .valid
+		.sink1_channel       (cmd_demux_004_src0_channel),                           //          .channel
+		.sink1_data          (cmd_demux_004_src0_data),                              //          .data
+		.sink1_startofpacket (cmd_demux_004_src0_startofpacket),                     //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_004_src0_endofpacket),                       //          .endofpacket
+		.sink2_ready         (cmd_demux_005_src0_ready),                             //     sink2.ready
+		.sink2_valid         (cmd_demux_005_src0_valid),                             //          .valid
+		.sink2_channel       (cmd_demux_005_src0_channel),                           //          .channel
+		.sink2_data          (cmd_demux_005_src0_data),                              //          .data
+		.sink2_startofpacket (cmd_demux_005_src0_startofpacket),                     //          .startofpacket
+		.sink2_endofpacket   (cmd_demux_005_src0_endofpacket),                       //          .endofpacket
+		.sink3_ready         (cmd_demux_006_src0_ready),                             //     sink3.ready
+		.sink3_valid         (cmd_demux_006_src0_valid),                             //          .valid
+		.sink3_channel       (cmd_demux_006_src0_channel),                           //          .channel
+		.sink3_data          (cmd_demux_006_src0_data),                              //          .data
+		.sink3_startofpacket (cmd_demux_006_src0_startofpacket),                     //          .startofpacket
+		.sink3_endofpacket   (cmd_demux_006_src0_endofpacket),                       //          .endofpacket
+		.sink4_ready         (cmd_demux_007_src0_ready),                             //     sink4.ready
+		.sink4_valid         (cmd_demux_007_src0_valid),                             //          .valid
+		.sink4_channel       (cmd_demux_007_src0_channel),                           //          .channel
+		.sink4_data          (cmd_demux_007_src0_data),                              //          .data
+		.sink4_startofpacket (cmd_demux_007_src0_startofpacket),                     //          .startofpacket
+		.sink4_endofpacket   (cmd_demux_007_src0_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_015 (
+		.clk                 (sys_clk_clk_clk),                                      //       clk.clk
+		.reset               (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_015_src_ready),                                //       src.ready
+		.src_valid           (cmd_mux_015_src_valid),                                //          .valid
+		.src_data            (cmd_mux_015_src_data),                                 //          .data
+		.src_channel         (cmd_mux_015_src_channel),                              //          .channel
+		.src_startofpacket   (cmd_mux_015_src_startofpacket),                        //          .startofpacket
+		.src_endofpacket     (cmd_mux_015_src_endofpacket),                          //          .endofpacket
+		.sink0_ready         (cmd_demux_src15_ready),                                //     sink0.ready
+		.sink0_valid         (cmd_demux_src15_valid),                                //          .valid
+		.sink0_channel       (cmd_demux_src15_channel),                              //          .channel
+		.sink0_data          (cmd_demux_src15_data),                                 //          .data
+		.sink0_startofpacket (cmd_demux_src15_startofpacket),                        //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src15_endofpacket)                           //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_016 (
+		.clk                 (sys_clk_clk_clk),                                      //       clk.clk
+		.reset               (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_016_src_ready),                                //       src.ready
+		.src_valid           (cmd_mux_016_src_valid),                                //          .valid
+		.src_data            (cmd_mux_016_src_data),                                 //          .data
+		.src_channel         (cmd_mux_016_src_channel),                              //          .channel
+		.src_startofpacket   (cmd_mux_016_src_startofpacket),                        //          .startofpacket
+		.src_endofpacket     (cmd_mux_016_src_endofpacket),                          //          .endofpacket
+		.sink0_ready         (cmd_demux_src16_ready),                                //     sink0.ready
+		.sink0_valid         (cmd_demux_src16_valid),                                //          .valid
+		.sink0_channel       (cmd_demux_src16_channel),                              //          .channel
+		.sink0_data          (cmd_demux_src16_data),                                 //          .data
+		.sink0_startofpacket (cmd_demux_src16_startofpacket),                        //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src16_endofpacket)                           //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_017 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_017_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_017_src_valid),                 //          .valid
+		.src_data            (cmd_mux_017_src_data),                  //          .data
+		.src_channel         (cmd_mux_017_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_017_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_017_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src17_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src17_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src17_channel),               //          .channel
+		.sink0_data          (cmd_demux_src17_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src17_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src17_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_018 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_018_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_018_src_valid),                 //          .valid
+		.src_data            (cmd_mux_018_src_data),                  //          .data
+		.src_channel         (cmd_mux_018_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_018_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_018_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src18_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src18_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src18_channel),               //          .channel
+		.sink0_data          (cmd_demux_src18_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src18_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src18_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_019 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_019_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_019_src_valid),                 //          .valid
+		.src_data            (cmd_mux_019_src_data),                  //          .data
+		.src_channel         (cmd_mux_019_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_019_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_019_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src19_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src19_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src19_channel),               //          .channel
+		.sink0_data          (cmd_demux_src19_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src19_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src19_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_mux_001 cmd_mux_020 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_020_src_ready),                 //       src.ready
+		.src_valid           (cmd_mux_020_src_valid),                 //          .valid
+		.src_data            (cmd_mux_020_src_data),                  //          .data
+		.src_channel         (cmd_mux_020_src_channel),               //          .channel
+		.src_startofpacket   (cmd_mux_020_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (cmd_mux_020_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (cmd_demux_src20_ready),                 //     sink0.ready
+		.sink0_valid         (cmd_demux_src20_valid),                 //          .valid
+		.sink0_channel       (cmd_demux_src20_channel),               //          .channel
+		.sink0_data          (cmd_demux_src20_data),                  //          .data
+		.sink0_startofpacket (cmd_demux_src20_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src20_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux rsp_demux (
+		.clk                (ddr3_ram_afi_clk_clk),                                      //       clk.clk
+		.reset              (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_008_src_ready),                                      //      sink.ready
+		.sink_channel       (router_008_src_channel),                                    //          .channel
+		.sink_data          (router_008_src_data),                                       //          .data
+		.sink_startofpacket (router_008_src_startofpacket),                              //          .startofpacket
+		.sink_endofpacket   (router_008_src_endofpacket),                                //          .endofpacket
+		.sink_valid         (router_008_src_valid),                                      //          .valid
+		.src0_ready         (rsp_demux_src0_ready),                                      //      src0.ready
+		.src0_valid         (rsp_demux_src0_valid),                                      //          .valid
+		.src0_data          (rsp_demux_src0_data),                                       //          .data
+		.src0_channel       (rsp_demux_src0_channel),                                    //          .channel
+		.src0_startofpacket (rsp_demux_src0_startofpacket),                              //          .startofpacket
+		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                //          .endofpacket
+		.src1_ready         (rsp_demux_src1_ready),                                      //      src1.ready
+		.src1_valid         (rsp_demux_src1_valid),                                      //          .valid
+		.src1_data          (rsp_demux_src1_data),                                       //          .data
+		.src1_channel       (rsp_demux_src1_channel),                                    //          .channel
+		.src1_startofpacket (rsp_demux_src1_startofpacket),                              //          .startofpacket
+		.src1_endofpacket   (rsp_demux_src1_endofpacket),                                //          .endofpacket
+		.src2_ready         (rsp_demux_src2_ready),                                      //      src2.ready
+		.src2_valid         (rsp_demux_src2_valid),                                      //          .valid
+		.src2_data          (rsp_demux_src2_data),                                       //          .data
+		.src2_channel       (rsp_demux_src2_channel),                                    //          .channel
+		.src2_startofpacket (rsp_demux_src2_startofpacket),                              //          .startofpacket
+		.src2_endofpacket   (rsp_demux_src2_endofpacket),                                //          .endofpacket
+		.src3_ready         (rsp_demux_src3_ready),                                      //      src3.ready
+		.src3_valid         (rsp_demux_src3_valid),                                      //          .valid
+		.src3_data          (rsp_demux_src3_data),                                       //          .data
+		.src3_channel       (rsp_demux_src3_channel),                                    //          .channel
+		.src3_startofpacket (rsp_demux_src3_startofpacket),                              //          .startofpacket
+		.src3_endofpacket   (rsp_demux_src3_endofpacket)                                 //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux_001 rsp_demux_001 (
+		.clk                (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset              (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_009_src_ready),                        //      sink.ready
+		.sink_channel       (router_009_src_channel),                      //          .channel
+		.sink_data          (router_009_src_data),                         //          .data
+		.sink_startofpacket (router_009_src_startofpacket),                //          .startofpacket
+		.sink_endofpacket   (router_009_src_endofpacket),                  //          .endofpacket
+		.sink_valid         (router_009_src_valid),                        //          .valid
+		.src0_ready         (rsp_demux_001_src0_ready),                    //      src0.ready
+		.src0_valid         (rsp_demux_001_src0_valid),                    //          .valid
+		.src0_data          (rsp_demux_001_src0_data),                     //          .data
+		.src0_channel       (rsp_demux_001_src0_channel),                  //          .channel
+		.src0_startofpacket (rsp_demux_001_src0_startofpacket),            //          .startofpacket
+		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)               //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
+		.clk                (ext_flash_clock_bridge_out_clk_clk),          //       clk.clk
+		.reset              (ext_flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_010_src_ready),                        //      sink.ready
+		.sink_channel       (router_010_src_channel),                      //          .channel
+		.sink_data          (router_010_src_data),                         //          .data
+		.sink_startofpacket (router_010_src_startofpacket),                //          .startofpacket
+		.sink_endofpacket   (router_010_src_endofpacket),                  //          .endofpacket
+		.sink_valid         (router_010_src_valid),                        //          .valid
+		.src0_ready         (rsp_demux_002_src0_ready),                    //      src0.ready
+		.src0_valid         (rsp_demux_002_src0_valid),                    //          .valid
+		.src0_data          (rsp_demux_002_src0_data),                     //          .data
+		.src0_channel       (rsp_demux_002_src0_channel),                  //          .channel
+		.src0_startofpacket (rsp_demux_002_src0_startofpacket),            //          .startofpacket
+		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),              //          .endofpacket
+		.src1_ready         (rsp_demux_002_src1_ready),                    //      src1.ready
+		.src1_valid         (rsp_demux_002_src1_valid),                    //          .valid
+		.src1_data          (rsp_demux_002_src1_data),                     //          .data
+		.src1_channel       (rsp_demux_002_src1_channel),                  //          .channel
+		.src1_startofpacket (rsp_demux_002_src1_startofpacket),            //          .startofpacket
+		.src1_endofpacket   (rsp_demux_002_src1_endofpacket)               //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_003 (
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_011_src_ready),                                 //      sink.ready
+		.sink_channel       (router_011_src_channel),                               //          .channel
+		.sink_data          (router_011_src_data),                                  //          .data
+		.sink_startofpacket (router_011_src_startofpacket),                         //          .startofpacket
+		.sink_endofpacket   (router_011_src_endofpacket),                           //          .endofpacket
+		.sink_valid         (router_011_src_valid),                                 //          .valid
+		.src0_ready         (rsp_demux_003_src0_ready),                             //      src0.ready
+		.src0_valid         (rsp_demux_003_src0_valid),                             //          .valid
+		.src0_data          (rsp_demux_003_src0_data),                              //          .data
+		.src0_channel       (rsp_demux_003_src0_channel),                           //          .channel
+		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                     //          .startofpacket
+		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_004 (
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_012_src_ready),                                 //      sink.ready
+		.sink_channel       (router_012_src_channel),                               //          .channel
+		.sink_data          (router_012_src_data),                                  //          .data
+		.sink_startofpacket (router_012_src_startofpacket),                         //          .startofpacket
+		.sink_endofpacket   (router_012_src_endofpacket),                           //          .endofpacket
+		.sink_valid         (router_012_src_valid),                                 //          .valid
+		.src0_ready         (rsp_demux_004_src0_ready),                             //      src0.ready
+		.src0_valid         (rsp_demux_004_src0_valid),                             //          .valid
+		.src0_data          (rsp_demux_004_src0_data),                              //          .data
+		.src0_channel       (rsp_demux_004_src0_channel),                           //          .channel
+		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                     //          .startofpacket
+		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_005 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_013_src_ready),                  //      sink.ready
+		.sink_channel       (router_013_src_channel),                //          .channel
+		.sink_data          (router_013_src_data),                   //          .data
+		.sink_startofpacket (router_013_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_013_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_013_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_005_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_005_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_005_src0_data),               //          .data
+		.src0_channel       (rsp_demux_005_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_005_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_006 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_014_src_ready),                  //      sink.ready
+		.sink_channel       (router_014_src_channel),                //          .channel
+		.sink_data          (router_014_src_data),                   //          .data
+		.sink_startofpacket (router_014_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_014_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_014_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_006_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_006_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_006_src0_data),               //          .data
+		.src0_channel       (rsp_demux_006_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_006_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_006_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_007 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_015_src_ready),                  //      sink.ready
+		.sink_channel       (router_015_src_channel),                //          .channel
+		.sink_data          (router_015_src_data),                   //          .data
+		.sink_startofpacket (router_015_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_015_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_015_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_007_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_007_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_007_src0_data),               //          .data
+		.src0_channel       (rsp_demux_007_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_007_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_007_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_008 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_016_src_ready),                  //      sink.ready
+		.sink_channel       (router_016_src_channel),                //          .channel
+		.sink_data          (router_016_src_data),                   //          .data
+		.sink_startofpacket (router_016_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_016_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_016_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_008_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_008_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_008_src0_data),               //          .data
+		.src0_channel       (rsp_demux_008_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_008_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_008_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_009 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_017_src_ready),                  //      sink.ready
+		.sink_channel       (router_017_src_channel),                //          .channel
+		.sink_data          (router_017_src_data),                   //          .data
+		.sink_startofpacket (router_017_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_017_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_017_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_009_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_009_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_009_src0_data),               //          .data
+		.src0_channel       (rsp_demux_009_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_009_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_009_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux_010 rsp_demux_010 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_018_src_ready),                  //      sink.ready
+		.sink_channel       (router_018_src_channel),                //          .channel
+		.sink_data          (router_018_src_data),                   //          .data
+		.sink_startofpacket (router_018_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_018_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_018_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_010_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_010_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_010_src0_data),               //          .data
+		.src0_channel       (rsp_demux_010_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_010_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_010_src0_endofpacket),        //          .endofpacket
+		.src1_ready         (rsp_demux_010_src1_ready),              //      src1.ready
+		.src1_valid         (rsp_demux_010_src1_valid),              //          .valid
+		.src1_data          (rsp_demux_010_src1_data),               //          .data
+		.src1_channel       (rsp_demux_010_src1_channel),            //          .channel
+		.src1_startofpacket (rsp_demux_010_src1_startofpacket),      //          .startofpacket
+		.src1_endofpacket   (rsp_demux_010_src1_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux_010 rsp_demux_011 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_019_src_ready),                  //      sink.ready
+		.sink_channel       (router_019_src_channel),                //          .channel
+		.sink_data          (router_019_src_data),                   //          .data
+		.sink_startofpacket (router_019_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_019_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_019_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_011_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_011_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_011_src0_data),               //          .data
+		.src0_channel       (rsp_demux_011_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_011_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_011_src0_endofpacket),        //          .endofpacket
+		.src1_ready         (rsp_demux_011_src1_ready),              //      src1.ready
+		.src1_valid         (rsp_demux_011_src1_valid),              //          .valid
+		.src1_data          (rsp_demux_011_src1_data),               //          .data
+		.src1_channel       (rsp_demux_011_src1_channel),            //          .channel
+		.src1_startofpacket (rsp_demux_011_src1_startofpacket),      //          .startofpacket
+		.src1_endofpacket   (rsp_demux_011_src1_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_012 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_020_src_ready),                  //      sink.ready
+		.sink_channel       (router_020_src_channel),                //          .channel
+		.sink_data          (router_020_src_data),                   //          .data
+		.sink_startofpacket (router_020_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_020_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_020_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_012_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_012_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_012_src0_data),               //          .data
+		.src0_channel       (rsp_demux_012_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_012_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_012_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_013 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_021_src_ready),                  //      sink.ready
+		.sink_channel       (router_021_src_channel),                //          .channel
+		.sink_data          (router_021_src_data),                   //          .data
+		.sink_startofpacket (router_021_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_021_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_021_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_013_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_013_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_013_src0_data),               //          .data
+		.src0_channel       (rsp_demux_013_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_013_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_013_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_demux_014 rsp_demux_014 (
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_022_src_ready),                                 //      sink.ready
+		.sink_channel       (router_022_src_channel),                               //          .channel
+		.sink_data          (router_022_src_data),                                  //          .data
+		.sink_startofpacket (router_022_src_startofpacket),                         //          .startofpacket
+		.sink_endofpacket   (router_022_src_endofpacket),                           //          .endofpacket
+		.sink_valid         (router_022_src_valid),                                 //          .valid
+		.src0_ready         (rsp_demux_014_src0_ready),                             //      src0.ready
+		.src0_valid         (rsp_demux_014_src0_valid),                             //          .valid
+		.src0_data          (rsp_demux_014_src0_data),                              //          .data
+		.src0_channel       (rsp_demux_014_src0_channel),                           //          .channel
+		.src0_startofpacket (rsp_demux_014_src0_startofpacket),                     //          .startofpacket
+		.src0_endofpacket   (rsp_demux_014_src0_endofpacket),                       //          .endofpacket
+		.src1_ready         (rsp_demux_014_src1_ready),                             //      src1.ready
+		.src1_valid         (rsp_demux_014_src1_valid),                             //          .valid
+		.src1_data          (rsp_demux_014_src1_data),                              //          .data
+		.src1_channel       (rsp_demux_014_src1_channel),                           //          .channel
+		.src1_startofpacket (rsp_demux_014_src1_startofpacket),                     //          .startofpacket
+		.src1_endofpacket   (rsp_demux_014_src1_endofpacket),                       //          .endofpacket
+		.src2_ready         (rsp_demux_014_src2_ready),                             //      src2.ready
+		.src2_valid         (rsp_demux_014_src2_valid),                             //          .valid
+		.src2_data          (rsp_demux_014_src2_data),                              //          .data
+		.src2_channel       (rsp_demux_014_src2_channel),                           //          .channel
+		.src2_startofpacket (rsp_demux_014_src2_startofpacket),                     //          .startofpacket
+		.src2_endofpacket   (rsp_demux_014_src2_endofpacket),                       //          .endofpacket
+		.src3_ready         (rsp_demux_014_src3_ready),                             //      src3.ready
+		.src3_valid         (rsp_demux_014_src3_valid),                             //          .valid
+		.src3_data          (rsp_demux_014_src3_data),                              //          .data
+		.src3_channel       (rsp_demux_014_src3_channel),                           //          .channel
+		.src3_startofpacket (rsp_demux_014_src3_startofpacket),                     //          .startofpacket
+		.src3_endofpacket   (rsp_demux_014_src3_endofpacket),                       //          .endofpacket
+		.src4_ready         (rsp_demux_014_src4_ready),                             //      src4.ready
+		.src4_valid         (rsp_demux_014_src4_valid),                             //          .valid
+		.src4_data          (rsp_demux_014_src4_data),                              //          .data
+		.src4_channel       (rsp_demux_014_src4_channel),                           //          .channel
+		.src4_startofpacket (rsp_demux_014_src4_startofpacket),                     //          .startofpacket
+		.src4_endofpacket   (rsp_demux_014_src4_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_015 (
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_023_src_ready),                                 //      sink.ready
+		.sink_channel       (router_023_src_channel),                               //          .channel
+		.sink_data          (router_023_src_data),                                  //          .data
+		.sink_startofpacket (router_023_src_startofpacket),                         //          .startofpacket
+		.sink_endofpacket   (router_023_src_endofpacket),                           //          .endofpacket
+		.sink_valid         (router_023_src_valid),                                 //          .valid
+		.src0_ready         (rsp_demux_015_src0_ready),                             //      src0.ready
+		.src0_valid         (rsp_demux_015_src0_valid),                             //          .valid
+		.src0_data          (rsp_demux_015_src0_data),                              //          .data
+		.src0_channel       (rsp_demux_015_src0_channel),                           //          .channel
+		.src0_startofpacket (rsp_demux_015_src0_startofpacket),                     //          .startofpacket
+		.src0_endofpacket   (rsp_demux_015_src0_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_016 (
+		.clk                (sys_clk_clk_clk),                                      //       clk.clk
+		.reset              (eth_tse_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_024_src_ready),                                 //      sink.ready
+		.sink_channel       (router_024_src_channel),                               //          .channel
+		.sink_data          (router_024_src_data),                                  //          .data
+		.sink_startofpacket (router_024_src_startofpacket),                         //          .startofpacket
+		.sink_endofpacket   (router_024_src_endofpacket),                           //          .endofpacket
+		.sink_valid         (router_024_src_valid),                                 //          .valid
+		.src0_ready         (rsp_demux_016_src0_ready),                             //      src0.ready
+		.src0_valid         (rsp_demux_016_src0_valid),                             //          .valid
+		.src0_data          (rsp_demux_016_src0_data),                              //          .data
+		.src0_channel       (rsp_demux_016_src0_channel),                           //          .channel
+		.src0_startofpacket (rsp_demux_016_src0_startofpacket),                     //          .startofpacket
+		.src0_endofpacket   (rsp_demux_016_src0_endofpacket)                        //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_017 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_025_src_ready),                  //      sink.ready
+		.sink_channel       (router_025_src_channel),                //          .channel
+		.sink_data          (router_025_src_data),                   //          .data
+		.sink_startofpacket (router_025_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_025_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_025_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_017_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_017_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_017_src0_data),               //          .data
+		.src0_channel       (rsp_demux_017_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_017_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_017_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_018 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_026_src_ready),                  //      sink.ready
+		.sink_channel       (router_026_src_channel),                //          .channel
+		.sink_data          (router_026_src_data),                   //          .data
+		.sink_startofpacket (router_026_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_026_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_026_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_018_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_018_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_018_src0_data),               //          .data
+		.src0_channel       (rsp_demux_018_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_018_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_018_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_019 (
+		.clk                (sys_clk_clk_clk),                       //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_027_src_ready),                  //      sink.ready
+		.sink_channel       (router_027_src_channel),                //          .channel
+		.sink_data          (router_027_src_data),                   //          .data
+		.sink_startofpacket (router_027_src_startofpacket),          //          .startofpacket
+		.sink_endofpacket   (router_027_src_endofpacket),            //          .endofpacket
+		.sink_valid         (router_027_src_valid),                  //          .valid
+		.src0_ready         (rsp_demux_019_src0_ready),              //      src0.ready
+		.src0_valid         (rsp_demux_019_src0_valid),              //          .valid
+		.src0_data          (rsp_demux_019_src0_data),               //          .data
+		.src0_channel       (rsp_demux_019_src0_channel),            //          .channel
+		.src0_startofpacket (rsp_demux_019_src0_startofpacket),      //          .startofpacket
+		.src0_endofpacket   (rsp_demux_019_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_cmd_demux_002 rsp_demux_020 (
+		.clk                (sys_clk_clk_clk),                                        //       clk.clk
+		.reset              (cpu_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
+		.sink_ready         (calibration_ram_s1_rsp_width_adapter_src_ready),         //      sink.ready
+		.sink_channel       (calibration_ram_s1_rsp_width_adapter_src_channel),       //          .channel
+		.sink_data          (calibration_ram_s1_rsp_width_adapter_src_data),          //          .data
+		.sink_startofpacket (calibration_ram_s1_rsp_width_adapter_src_startofpacket), //          .startofpacket
+		.sink_endofpacket   (calibration_ram_s1_rsp_width_adapter_src_endofpacket),   //          .endofpacket
+		.sink_valid         (calibration_ram_s1_rsp_width_adapter_src_valid),         //          .valid
+		.src0_ready         (rsp_demux_020_src0_ready),                               //      src0.ready
+		.src0_valid         (rsp_demux_020_src0_valid),                               //          .valid
+		.src0_data          (rsp_demux_020_src0_data),                                //          .data
+		.src0_channel       (rsp_demux_020_src0_channel),                             //          .channel
+		.src0_startofpacket (rsp_demux_020_src0_startofpacket),                       //          .startofpacket
+		.src0_endofpacket   (rsp_demux_020_src0_endofpacket)                          //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux rsp_mux (
+		.clk                  (sys_clk_clk_clk),                       //       clk.clk
+		.reset                (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready            (rsp_mux_src_ready),                     //       src.ready
+		.src_valid            (rsp_mux_src_valid),                     //          .valid
+		.src_data             (rsp_mux_src_data),                      //          .data
+		.src_channel          (rsp_mux_src_channel),                   //          .channel
+		.src_startofpacket    (rsp_mux_src_startofpacket),             //          .startofpacket
+		.src_endofpacket      (rsp_mux_src_endofpacket),               //          .endofpacket
+		.sink0_ready          (crosser_007_out_ready),                 //     sink0.ready
+		.sink0_valid          (crosser_007_out_valid),                 //          .valid
+		.sink0_channel        (crosser_007_out_channel),               //          .channel
+		.sink0_data           (crosser_007_out_data),                  //          .data
+		.sink0_startofpacket  (crosser_007_out_startofpacket),         //          .startofpacket
+		.sink0_endofpacket    (crosser_007_out_endofpacket),           //          .endofpacket
+		.sink1_ready          (crosser_011_out_ready),                 //     sink1.ready
+		.sink1_valid          (crosser_011_out_valid),                 //          .valid
+		.sink1_channel        (crosser_011_out_channel),               //          .channel
+		.sink1_data           (crosser_011_out_data),                  //          .data
+		.sink1_startofpacket  (crosser_011_out_startofpacket),         //          .startofpacket
+		.sink1_endofpacket    (crosser_011_out_endofpacket),           //          .endofpacket
+		.sink2_ready          (crosser_012_out_ready),                 //     sink2.ready
+		.sink2_valid          (crosser_012_out_valid),                 //          .valid
+		.sink2_channel        (crosser_012_out_channel),               //          .channel
+		.sink2_data           (crosser_012_out_data),                  //          .data
+		.sink2_startofpacket  (crosser_012_out_startofpacket),         //          .startofpacket
+		.sink2_endofpacket    (crosser_012_out_endofpacket),           //          .endofpacket
+		.sink3_ready          (rsp_demux_003_src0_ready),              //     sink3.ready
+		.sink3_valid          (rsp_demux_003_src0_valid),              //          .valid
+		.sink3_channel        (rsp_demux_003_src0_channel),            //          .channel
+		.sink3_data           (rsp_demux_003_src0_data),               //          .data
+		.sink3_startofpacket  (rsp_demux_003_src0_startofpacket),      //          .startofpacket
+		.sink3_endofpacket    (rsp_demux_003_src0_endofpacket),        //          .endofpacket
+		.sink4_ready          (rsp_demux_004_src0_ready),              //     sink4.ready
+		.sink4_valid          (rsp_demux_004_src0_valid),              //          .valid
+		.sink4_channel        (rsp_demux_004_src0_channel),            //          .channel
+		.sink4_data           (rsp_demux_004_src0_data),               //          .data
+		.sink4_startofpacket  (rsp_demux_004_src0_startofpacket),      //          .startofpacket
+		.sink4_endofpacket    (rsp_demux_004_src0_endofpacket),        //          .endofpacket
+		.sink5_ready          (rsp_demux_005_src0_ready),              //     sink5.ready
+		.sink5_valid          (rsp_demux_005_src0_valid),              //          .valid
+		.sink5_channel        (rsp_demux_005_src0_channel),            //          .channel
+		.sink5_data           (rsp_demux_005_src0_data),               //          .data
+		.sink5_startofpacket  (rsp_demux_005_src0_startofpacket),      //          .startofpacket
+		.sink5_endofpacket    (rsp_demux_005_src0_endofpacket),        //          .endofpacket
+		.sink6_ready          (rsp_demux_006_src0_ready),              //     sink6.ready
+		.sink6_valid          (rsp_demux_006_src0_valid),              //          .valid
+		.sink6_channel        (rsp_demux_006_src0_channel),            //          .channel
+		.sink6_data           (rsp_demux_006_src0_data),               //          .data
+		.sink6_startofpacket  (rsp_demux_006_src0_startofpacket),      //          .startofpacket
+		.sink6_endofpacket    (rsp_demux_006_src0_endofpacket),        //          .endofpacket
+		.sink7_ready          (rsp_demux_007_src0_ready),              //     sink7.ready
+		.sink7_valid          (rsp_demux_007_src0_valid),              //          .valid
+		.sink7_channel        (rsp_demux_007_src0_channel),            //          .channel
+		.sink7_data           (rsp_demux_007_src0_data),               //          .data
+		.sink7_startofpacket  (rsp_demux_007_src0_startofpacket),      //          .startofpacket
+		.sink7_endofpacket    (rsp_demux_007_src0_endofpacket),        //          .endofpacket
+		.sink8_ready          (rsp_demux_008_src0_ready),              //     sink8.ready
+		.sink8_valid          (rsp_demux_008_src0_valid),              //          .valid
+		.sink8_channel        (rsp_demux_008_src0_channel),            //          .channel
+		.sink8_data           (rsp_demux_008_src0_data),               //          .data
+		.sink8_startofpacket  (rsp_demux_008_src0_startofpacket),      //          .startofpacket
+		.sink8_endofpacket    (rsp_demux_008_src0_endofpacket),        //          .endofpacket
+		.sink9_ready          (rsp_demux_009_src0_ready),              //     sink9.ready
+		.sink9_valid          (rsp_demux_009_src0_valid),              //          .valid
+		.sink9_channel        (rsp_demux_009_src0_channel),            //          .channel
+		.sink9_data           (rsp_demux_009_src0_data),               //          .data
+		.sink9_startofpacket  (rsp_demux_009_src0_startofpacket),      //          .startofpacket
+		.sink9_endofpacket    (rsp_demux_009_src0_endofpacket),        //          .endofpacket
+		.sink10_ready         (rsp_demux_010_src0_ready),              //    sink10.ready
+		.sink10_valid         (rsp_demux_010_src0_valid),              //          .valid
+		.sink10_channel       (rsp_demux_010_src0_channel),            //          .channel
+		.sink10_data          (rsp_demux_010_src0_data),               //          .data
+		.sink10_startofpacket (rsp_demux_010_src0_startofpacket),      //          .startofpacket
+		.sink10_endofpacket   (rsp_demux_010_src0_endofpacket),        //          .endofpacket
+		.sink11_ready         (rsp_demux_011_src0_ready),              //    sink11.ready
+		.sink11_valid         (rsp_demux_011_src0_valid),              //          .valid
+		.sink11_channel       (rsp_demux_011_src0_channel),            //          .channel
+		.sink11_data          (rsp_demux_011_src0_data),               //          .data
+		.sink11_startofpacket (rsp_demux_011_src0_startofpacket),      //          .startofpacket
+		.sink11_endofpacket   (rsp_demux_011_src0_endofpacket),        //          .endofpacket
+		.sink12_ready         (rsp_demux_012_src0_ready),              //    sink12.ready
+		.sink12_valid         (rsp_demux_012_src0_valid),              //          .valid
+		.sink12_channel       (rsp_demux_012_src0_channel),            //          .channel
+		.sink12_data          (rsp_demux_012_src0_data),               //          .data
+		.sink12_startofpacket (rsp_demux_012_src0_startofpacket),      //          .startofpacket
+		.sink12_endofpacket   (rsp_demux_012_src0_endofpacket),        //          .endofpacket
+		.sink13_ready         (rsp_demux_013_src0_ready),              //    sink13.ready
+		.sink13_valid         (rsp_demux_013_src0_valid),              //          .valid
+		.sink13_channel       (rsp_demux_013_src0_channel),            //          .channel
+		.sink13_data          (rsp_demux_013_src0_data),               //          .data
+		.sink13_startofpacket (rsp_demux_013_src0_startofpacket),      //          .startofpacket
+		.sink13_endofpacket   (rsp_demux_013_src0_endofpacket),        //          .endofpacket
+		.sink14_ready         (rsp_demux_014_src0_ready),              //    sink14.ready
+		.sink14_valid         (rsp_demux_014_src0_valid),              //          .valid
+		.sink14_channel       (rsp_demux_014_src0_channel),            //          .channel
+		.sink14_data          (rsp_demux_014_src0_data),               //          .data
+		.sink14_startofpacket (rsp_demux_014_src0_startofpacket),      //          .startofpacket
+		.sink14_endofpacket   (rsp_demux_014_src0_endofpacket),        //          .endofpacket
+		.sink15_ready         (rsp_demux_015_src0_ready),              //    sink15.ready
+		.sink15_valid         (rsp_demux_015_src0_valid),              //          .valid
+		.sink15_channel       (rsp_demux_015_src0_channel),            //          .channel
+		.sink15_data          (rsp_demux_015_src0_data),               //          .data
+		.sink15_startofpacket (rsp_demux_015_src0_startofpacket),      //          .startofpacket
+		.sink15_endofpacket   (rsp_demux_015_src0_endofpacket),        //          .endofpacket
+		.sink16_ready         (rsp_demux_016_src0_ready),              //    sink16.ready
+		.sink16_valid         (rsp_demux_016_src0_valid),              //          .valid
+		.sink16_channel       (rsp_demux_016_src0_channel),            //          .channel
+		.sink16_data          (rsp_demux_016_src0_data),               //          .data
+		.sink16_startofpacket (rsp_demux_016_src0_startofpacket),      //          .startofpacket
+		.sink16_endofpacket   (rsp_demux_016_src0_endofpacket),        //          .endofpacket
+		.sink17_ready         (rsp_demux_017_src0_ready),              //    sink17.ready
+		.sink17_valid         (rsp_demux_017_src0_valid),              //          .valid
+		.sink17_channel       (rsp_demux_017_src0_channel),            //          .channel
+		.sink17_data          (rsp_demux_017_src0_data),               //          .data
+		.sink17_startofpacket (rsp_demux_017_src0_startofpacket),      //          .startofpacket
+		.sink17_endofpacket   (rsp_demux_017_src0_endofpacket),        //          .endofpacket
+		.sink18_ready         (rsp_demux_018_src0_ready),              //    sink18.ready
+		.sink18_valid         (rsp_demux_018_src0_valid),              //          .valid
+		.sink18_channel       (rsp_demux_018_src0_channel),            //          .channel
+		.sink18_data          (rsp_demux_018_src0_data),               //          .data
+		.sink18_startofpacket (rsp_demux_018_src0_startofpacket),      //          .startofpacket
+		.sink18_endofpacket   (rsp_demux_018_src0_endofpacket),        //          .endofpacket
+		.sink19_ready         (rsp_demux_019_src0_ready),              //    sink19.ready
+		.sink19_valid         (rsp_demux_019_src0_valid),              //          .valid
+		.sink19_channel       (rsp_demux_019_src0_channel),            //          .channel
+		.sink19_data          (rsp_demux_019_src0_data),               //          .data
+		.sink19_startofpacket (rsp_demux_019_src0_startofpacket),      //          .startofpacket
+		.sink19_endofpacket   (rsp_demux_019_src0_endofpacket),        //          .endofpacket
+		.sink20_ready         (rsp_demux_020_src0_ready),              //    sink20.ready
+		.sink20_valid         (rsp_demux_020_src0_valid),              //          .valid
+		.sink20_channel       (rsp_demux_020_src0_channel),            //          .channel
+		.sink20_data          (rsp_demux_020_src0_data),               //          .data
+		.sink20_startofpacket (rsp_demux_020_src0_startofpacket),      //          .startofpacket
+		.sink20_endofpacket   (rsp_demux_020_src0_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_001 rsp_mux_001 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_001_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_001_src_valid),                 //          .valid
+		.src_data            (rsp_mux_001_src_data),                  //          .data
+		.src_channel         (rsp_mux_001_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_001_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_001_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (crosser_008_out_ready),                 //     sink0.ready
+		.sink0_valid         (crosser_008_out_valid),                 //          .valid
+		.sink0_channel       (crosser_008_out_channel),               //          .channel
+		.sink0_data          (crosser_008_out_data),                  //          .data
+		.sink0_startofpacket (crosser_008_out_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (crosser_008_out_endofpacket),           //          .endofpacket
+		.sink1_ready         (crosser_013_out_ready),                 //     sink1.ready
+		.sink1_valid         (crosser_013_out_valid),                 //          .valid
+		.sink1_channel       (crosser_013_out_channel),               //          .channel
+		.sink1_data          (crosser_013_out_data),                  //          .data
+		.sink1_startofpacket (crosser_013_out_startofpacket),         //          .startofpacket
+		.sink1_endofpacket   (crosser_013_out_endofpacket),           //          .endofpacket
+		.sink2_ready         (rsp_demux_010_src1_ready),              //     sink2.ready
+		.sink2_valid         (rsp_demux_010_src1_valid),              //          .valid
+		.sink2_channel       (rsp_demux_010_src1_channel),            //          .channel
+		.sink2_data          (rsp_demux_010_src1_data),               //          .data
+		.sink2_startofpacket (rsp_demux_010_src1_startofpacket),      //          .startofpacket
+		.sink2_endofpacket   (rsp_demux_010_src1_endofpacket),        //          .endofpacket
+		.sink3_ready         (rsp_demux_011_src1_ready),              //     sink3.ready
+		.sink3_valid         (rsp_demux_011_src1_valid),              //          .valid
+		.sink3_channel       (rsp_demux_011_src1_channel),            //          .channel
+		.sink3_data          (rsp_demux_011_src1_data),               //          .data
+		.sink3_startofpacket (rsp_demux_011_src1_startofpacket),      //          .startofpacket
+		.sink3_endofpacket   (rsp_demux_011_src1_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_002 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_002_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_002_src_valid),                 //          .valid
+		.src_data            (rsp_mux_002_src_data),                  //          .data
+		.src_channel         (rsp_mux_002_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_002_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_002_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (crosser_009_out_ready),                 //     sink0.ready
+		.sink0_valid         (crosser_009_out_valid),                 //          .valid
+		.sink0_channel       (crosser_009_out_channel),               //          .channel
+		.sink0_data          (crosser_009_out_data),                  //          .data
+		.sink0_startofpacket (crosser_009_out_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (crosser_009_out_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_003 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_003_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_003_src_valid),                 //          .valid
+		.src_data            (rsp_mux_003_src_data),                  //          .data
+		.src_channel         (rsp_mux_003_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_003_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_003_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (crosser_010_out_ready),                 //     sink0.ready
+		.sink0_valid         (crosser_010_out_valid),                 //          .valid
+		.sink0_channel       (crosser_010_out_channel),               //          .channel
+		.sink0_data          (crosser_010_out_data),                  //          .data
+		.sink0_startofpacket (crosser_010_out_startofpacket),         //          .startofpacket
+		.sink0_endofpacket   (crosser_010_out_endofpacket)            //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_004 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_004_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_004_src_valid),                 //          .valid
+		.src_data            (rsp_mux_004_src_data),                  //          .data
+		.src_channel         (rsp_mux_004_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_004_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_004_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (rsp_demux_014_src1_ready),              //     sink0.ready
+		.sink0_valid         (rsp_demux_014_src1_valid),              //          .valid
+		.sink0_channel       (rsp_demux_014_src1_channel),            //          .channel
+		.sink0_data          (rsp_demux_014_src1_data),               //          .data
+		.sink0_startofpacket (rsp_demux_014_src1_startofpacket),      //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_014_src1_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_005 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_005_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_005_src_valid),                 //          .valid
+		.src_data            (rsp_mux_005_src_data),                  //          .data
+		.src_channel         (rsp_mux_005_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_005_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_005_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (rsp_demux_014_src2_ready),              //     sink0.ready
+		.sink0_valid         (rsp_demux_014_src2_valid),              //          .valid
+		.sink0_channel       (rsp_demux_014_src2_channel),            //          .channel
+		.sink0_data          (rsp_demux_014_src2_data),               //          .data
+		.sink0_startofpacket (rsp_demux_014_src2_startofpacket),      //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_014_src2_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_006 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_006_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_006_src_valid),                 //          .valid
+		.src_data            (rsp_mux_006_src_data),                  //          .data
+		.src_channel         (rsp_mux_006_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_006_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_006_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (rsp_demux_014_src3_ready),              //     sink0.ready
+		.sink0_valid         (rsp_demux_014_src3_valid),              //          .valid
+		.sink0_channel       (rsp_demux_014_src3_channel),            //          .channel
+		.sink0_data          (rsp_demux_014_src3_data),               //          .data
+		.sink0_startofpacket (rsp_demux_014_src3_startofpacket),      //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_014_src3_endofpacket)         //          .endofpacket
+	);
+
+	q_sys_mm_interconnect_1_rsp_mux_002 rsp_mux_007 (
+		.clk                 (sys_clk_clk_clk),                       //       clk.clk
+		.reset               (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_007_src_ready),                 //       src.ready
+		.src_valid           (rsp_mux_007_src_valid),                 //          .valid
+		.src_data            (rsp_mux_007_src_data),                  //          .data
+		.src_channel         (rsp_mux_007_src_channel),               //          .channel
+		.src_startofpacket   (rsp_mux_007_src_startofpacket),         //          .startofpacket
+		.src_endofpacket     (rsp_mux_007_src_endofpacket),           //          .endofpacket
+		.sink0_ready         (rsp_demux_014_src4_ready),              //     sink0.ready
+		.sink0_valid         (rsp_demux_014_src4_valid),              //          .valid
+		.sink0_channel       (rsp_demux_014_src4_channel),            //          .channel
+		.sink0_data          (rsp_demux_014_src4_data),               //          .data
+		.sink0_startofpacket (rsp_demux_014_src4_startofpacket),      //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_014_src4_endofpacket)         //          .endofpacket
+	);
+
+	altera_merlin_width_adapter #(
+		.IN_PKT_ADDR_H                 (46),
+		.IN_PKT_ADDR_L                 (18),
+		.IN_PKT_DATA_H                 (15),
+		.IN_PKT_DATA_L                 (0),
+		.IN_PKT_BYTEEN_H               (17),
+		.IN_PKT_BYTEEN_L               (16),
+		.IN_PKT_BYTE_CNT_H             (61),
+		.IN_PKT_BYTE_CNT_L             (53),
+		.IN_PKT_TRANS_COMPRESSED_READ  (47),
+		.IN_PKT_TRANS_WRITE            (49),
+		.IN_PKT_BURSTWRAP_H            (70),
+		.IN_PKT_BURSTWRAP_L            (62),
+		.IN_PKT_BURST_SIZE_H           (73),
+		.IN_PKT_BURST_SIZE_L           (71),
+		.IN_PKT_RESPONSE_STATUS_H      (99),
+		.IN_PKT_RESPONSE_STATUS_L      (98),
+		.IN_PKT_TRANS_EXCLUSIVE        (52),
+		.IN_PKT_BURST_TYPE_H           (75),
+		.IN_PKT_BURST_TYPE_L           (74),
+		.IN_PKT_ORI_BURST_SIZE_L       (100),
+		.IN_PKT_ORI_BURST_SIZE_H       (102),
+		.IN_ST_DATA_W                  (103),
+		.OUT_PKT_ADDR_H                (64),
+		.OUT_PKT_ADDR_L                (36),
+		.OUT_PKT_DATA_H                (31),
+		.OUT_PKT_DATA_L                (0),
+		.OUT_PKT_BYTEEN_H              (35),
+		.OUT_PKT_BYTEEN_L              (32),
+		.OUT_PKT_BYTE_CNT_H            (79),
+		.OUT_PKT_BYTE_CNT_L            (71),
+		.OUT_PKT_TRANS_COMPRESSED_READ (65),
+		.OUT_PKT_BURST_SIZE_H          (91),
+		.OUT_PKT_BURST_SIZE_L          (89),
+		.OUT_PKT_RESPONSE_STATUS_H     (117),
+		.OUT_PKT_RESPONSE_STATUS_L     (116),
+		.OUT_PKT_TRANS_EXCLUSIVE       (70),
+		.OUT_PKT_BURST_TYPE_H          (93),
+		.OUT_PKT_BURST_TYPE_L          (92),
+		.OUT_PKT_ORI_BURST_SIZE_L      (118),
+		.OUT_PKT_ORI_BURST_SIZE_H      (120),
+		.OUT_ST_DATA_W                 (121),
+		.ST_CHANNEL_W                  (21),
+		.OPTIMIZE_FOR_RSP              (1),
+		.RESPONSE_PATH                 (1),
+		.CONSTANT_BURST_SIZE           (1),
+		.PACKING                       (1),
+		.ENABLE_ADDRESS_ALIGNMENT      (0)
+	) calibration_ram_s1_rsp_width_adapter (
+		.clk                  (sys_clk_clk_clk),                                        //       clk.clk
+		.reset                (cpu_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
+		.in_valid             (router_028_src_valid),                                   //      sink.valid
+		.in_channel           (router_028_src_channel),                                 //          .channel
+		.in_startofpacket     (router_028_src_startofpacket),                           //          .startofpacket
+		.in_endofpacket       (router_028_src_endofpacket),                             //          .endofpacket
+		.in_ready             (router_028_src_ready),                                   //          .ready
+		.in_data              (router_028_src_data),                                    //          .data
+		.out_endofpacket      (calibration_ram_s1_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
+		.out_data             (calibration_ram_s1_rsp_width_adapter_src_data),          //          .data
+		.out_channel          (calibration_ram_s1_rsp_width_adapter_src_channel),       //          .channel
+		.out_valid            (calibration_ram_s1_rsp_width_adapter_src_valid),         //          .valid
+		.out_ready            (calibration_ram_s1_rsp_width_adapter_src_ready),         //          .ready
+		.out_startofpacket    (calibration_ram_s1_rsp_width_adapter_src_startofpacket), //          .startofpacket
+		.in_command_size_data (3'b000)                                                  // (terminated)
+	);
+
+	altera_merlin_width_adapter #(
+		.IN_PKT_ADDR_H                 (64),
+		.IN_PKT_ADDR_L                 (36),
+		.IN_PKT_DATA_H                 (31),
+		.IN_PKT_DATA_L                 (0),
+		.IN_PKT_BYTEEN_H               (35),
+		.IN_PKT_BYTEEN_L               (32),
+		.IN_PKT_BYTE_CNT_H             (79),
+		.IN_PKT_BYTE_CNT_L             (71),
+		.IN_PKT_TRANS_COMPRESSED_READ  (65),
+		.IN_PKT_TRANS_WRITE            (67),
+		.IN_PKT_BURSTWRAP_H            (88),
+		.IN_PKT_BURSTWRAP_L            (80),
+		.IN_PKT_BURST_SIZE_H           (91),
+		.IN_PKT_BURST_SIZE_L           (89),
+		.IN_PKT_RESPONSE_STATUS_H      (117),
+		.IN_PKT_RESPONSE_STATUS_L      (116),
+		.IN_PKT_TRANS_EXCLUSIVE        (70),
+		.IN_PKT_BURST_TYPE_H           (93),
+		.IN_PKT_BURST_TYPE_L           (92),
+		.IN_PKT_ORI_BURST_SIZE_L       (118),
+		.IN_PKT_ORI_BURST_SIZE_H       (120),
+		.IN_ST_DATA_W                  (121),
+		.OUT_PKT_ADDR_H                (46),
+		.OUT_PKT_ADDR_L                (18),
+		.OUT_PKT_DATA_H                (15),
+		.OUT_PKT_DATA_L                (0),
+		.OUT_PKT_BYTEEN_H              (17),
+		.OUT_PKT_BYTEEN_L              (16),
+		.OUT_PKT_BYTE_CNT_H            (61),
+		.OUT_PKT_BYTE_CNT_L            (53),
+		.OUT_PKT_TRANS_COMPRESSED_READ (47),
+		.OUT_PKT_BURST_SIZE_H          (73),
+		.OUT_PKT_BURST_SIZE_L          (71),
+		.OUT_PKT_RESPONSE_STATUS_H     (99),
+		.OUT_PKT_RESPONSE_STATUS_L     (98),
+		.OUT_PKT_TRANS_EXCLUSIVE       (52),
+		.OUT_PKT_BURST_TYPE_H          (75),
+		.OUT_PKT_BURST_TYPE_L          (74),
+		.OUT_PKT_ORI_BURST_SIZE_L      (100),
+		.OUT_PKT_ORI_BURST_SIZE_H      (102),
+		.OUT_ST_DATA_W                 (103),
+		.ST_CHANNEL_W                  (21),
+		.OPTIMIZE_FOR_RSP              (0),
+		.RESPONSE_PATH                 (0),
+		.CONSTANT_BURST_SIZE           (1),
+		.PACKING                       (1),
+		.ENABLE_ADDRESS_ALIGNMENT      (0)
+	) calibration_ram_s1_cmd_width_adapter (
+		.clk                  (sys_clk_clk_clk),                                        //       clk.clk
+		.reset                (cpu_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
+		.in_valid             (cmd_mux_020_src_valid),                                  //      sink.valid
+		.in_channel           (cmd_mux_020_src_channel),                                //          .channel
+		.in_startofpacket     (cmd_mux_020_src_startofpacket),                          //          .startofpacket
+		.in_endofpacket       (cmd_mux_020_src_endofpacket),                            //          .endofpacket
+		.in_ready             (cmd_mux_020_src_ready),                                  //          .ready
+		.in_data              (cmd_mux_020_src_data),                                   //          .data
+		.out_endofpacket      (calibration_ram_s1_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
+		.out_data             (calibration_ram_s1_cmd_width_adapter_src_data),          //          .data
+		.out_channel          (calibration_ram_s1_cmd_width_adapter_src_channel),       //          .channel
+		.out_valid            (calibration_ram_s1_cmd_width_adapter_src_valid),         //          .valid
+		.out_ready            (calibration_ram_s1_cmd_width_adapter_src_ready),         //          .ready
+		.out_startofpacket    (calibration_ram_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
+		.in_command_size_data (3'b000)                                                  // (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser (
+		.in_clk            (sys_clk_clk_clk),                                           //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),                     //  in_clk_reset.reset
+		.out_clk           (ddr3_ram_afi_clk_clk),                                      //       out_clk.clk
+		.out_reset         (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_src0_ready),                                      //            in.ready
+		.in_valid          (cmd_demux_src0_valid),                                      //              .valid
+		.in_startofpacket  (cmd_demux_src0_startofpacket),                              //              .startofpacket
+		.in_endofpacket    (cmd_demux_src0_endofpacket),                                //              .endofpacket
+		.in_channel        (cmd_demux_src0_channel),                                    //              .channel
+		.in_data           (cmd_demux_src0_data),                                       //              .data
+		.out_ready         (crosser_out_ready),                                         //           out.ready
+		.out_valid         (crosser_out_valid),                                         //              .valid
+		.out_startofpacket (crosser_out_startofpacket),                                 //              .startofpacket
+		.out_endofpacket   (crosser_out_endofpacket),                                   //              .endofpacket
+		.out_channel       (crosser_out_channel),                                       //              .channel
+		.out_data          (crosser_out_data),                                          //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_001 (
+		.in_clk            (sys_clk_clk_clk),                             //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),       //  in_clk_reset.reset
+		.out_clk           (ext_flash_clock_bridge_out_clk_clk),          //       out_clk.clk
+		.out_reset         (ext_flash_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_src1_ready),                        //            in.ready
+		.in_valid          (cmd_demux_src1_valid),                        //              .valid
+		.in_startofpacket  (cmd_demux_src1_startofpacket),                //              .startofpacket
+		.in_endofpacket    (cmd_demux_src1_endofpacket),                  //              .endofpacket
+		.in_channel        (cmd_demux_src1_channel),                      //              .channel
+		.in_data           (cmd_demux_src1_data),                         //              .data
+		.out_ready         (crosser_001_out_ready),                       //           out.ready
+		.out_valid         (crosser_001_out_valid),                       //              .valid
+		.out_startofpacket (crosser_001_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_001_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_001_out_channel),                     //              .channel
+		.out_data          (crosser_001_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_002 (
+		.in_clk            (sys_clk_clk_clk),                             //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),       //  in_clk_reset.reset
+		.out_clk           (ext_flash_clock_bridge_out_clk_clk),          //       out_clk.clk
+		.out_reset         (ext_flash_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_src2_ready),                        //            in.ready
+		.in_valid          (cmd_demux_src2_valid),                        //              .valid
+		.in_startofpacket  (cmd_demux_src2_startofpacket),                //              .startofpacket
+		.in_endofpacket    (cmd_demux_src2_endofpacket),                  //              .endofpacket
+		.in_channel        (cmd_demux_src2_channel),                      //              .channel
+		.in_data           (cmd_demux_src2_data),                         //              .data
+		.out_ready         (crosser_002_out_ready),                       //           out.ready
+		.out_valid         (crosser_002_out_valid),                       //              .valid
+		.out_startofpacket (crosser_002_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_002_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_002_out_channel),                     //              .channel
+		.out_data          (crosser_002_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_003 (
+		.in_clk            (sys_clk_clk_clk),                                           //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),                     //  in_clk_reset.reset
+		.out_clk           (ddr3_ram_afi_clk_clk),                                      //       out_clk.clk
+		.out_reset         (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_001_src0_ready),                                  //            in.ready
+		.in_valid          (cmd_demux_001_src0_valid),                                  //              .valid
+		.in_startofpacket  (cmd_demux_001_src0_startofpacket),                          //              .startofpacket
+		.in_endofpacket    (cmd_demux_001_src0_endofpacket),                            //              .endofpacket
+		.in_channel        (cmd_demux_001_src0_channel),                                //              .channel
+		.in_data           (cmd_demux_001_src0_data),                                   //              .data
+		.out_ready         (crosser_003_out_ready),                                     //           out.ready
+		.out_valid         (crosser_003_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_003_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_003_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_003_out_channel),                                   //              .channel
+		.out_data          (crosser_003_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_004 (
+		.in_clk            (sys_clk_clk_clk),                             //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),       //  in_clk_reset.reset
+		.out_clk           (ext_flash_clock_bridge_out_clk_clk),          //       out_clk.clk
+		.out_reset         (ext_flash_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_001_src1_ready),                    //            in.ready
+		.in_valid          (cmd_demux_001_src1_valid),                    //              .valid
+		.in_startofpacket  (cmd_demux_001_src1_startofpacket),            //              .startofpacket
+		.in_endofpacket    (cmd_demux_001_src1_endofpacket),              //              .endofpacket
+		.in_channel        (cmd_demux_001_src1_channel),                  //              .channel
+		.in_data           (cmd_demux_001_src1_data),                     //              .data
+		.out_ready         (crosser_004_out_ready),                       //           out.ready
+		.out_valid         (crosser_004_out_valid),                       //              .valid
+		.out_startofpacket (crosser_004_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_004_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_004_out_channel),                     //              .channel
+		.out_data          (crosser_004_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_005 (
+		.in_clk            (sys_clk_clk_clk),                                           //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),                     //  in_clk_reset.reset
+		.out_clk           (ddr3_ram_afi_clk_clk),                                      //       out_clk.clk
+		.out_reset         (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_002_src0_ready),                                  //            in.ready
+		.in_valid          (cmd_demux_002_src0_valid),                                  //              .valid
+		.in_startofpacket  (cmd_demux_002_src0_startofpacket),                          //              .startofpacket
+		.in_endofpacket    (cmd_demux_002_src0_endofpacket),                            //              .endofpacket
+		.in_channel        (cmd_demux_002_src0_channel),                                //              .channel
+		.in_data           (cmd_demux_002_src0_data),                                   //              .data
+		.out_ready         (crosser_005_out_ready),                                     //           out.ready
+		.out_valid         (crosser_005_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_005_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_005_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_005_out_channel),                                   //              .channel
+		.out_data          (crosser_005_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_006 (
+		.in_clk            (sys_clk_clk_clk),                                           //        in_clk.clk
+		.in_reset          (cpu_reset_reset_bridge_in_reset_reset),                     //  in_clk_reset.reset
+		.out_clk           (ddr3_ram_afi_clk_clk),                                      //       out_clk.clk
+		.out_reset         (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+		.in_ready          (cmd_demux_003_src0_ready),                                  //            in.ready
+		.in_valid          (cmd_demux_003_src0_valid),                                  //              .valid
+		.in_startofpacket  (cmd_demux_003_src0_startofpacket),                          //              .startofpacket
+		.in_endofpacket    (cmd_demux_003_src0_endofpacket),                            //              .endofpacket
+		.in_channel        (cmd_demux_003_src0_channel),                                //              .channel
+		.in_data           (cmd_demux_003_src0_data),                                   //              .data
+		.out_ready         (crosser_006_out_ready),                                     //           out.ready
+		.out_valid         (crosser_006_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_006_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_006_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_006_out_channel),                                   //              .channel
+		.out_data          (crosser_006_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_007 (
+		.in_clk            (ddr3_ram_afi_clk_clk),                                      //        in_clk.clk
+		.in_reset          (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                                           //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),                     // out_clk_reset.reset
+		.in_ready          (rsp_demux_src0_ready),                                      //            in.ready
+		.in_valid          (rsp_demux_src0_valid),                                      //              .valid
+		.in_startofpacket  (rsp_demux_src0_startofpacket),                              //              .startofpacket
+		.in_endofpacket    (rsp_demux_src0_endofpacket),                                //              .endofpacket
+		.in_channel        (rsp_demux_src0_channel),                                    //              .channel
+		.in_data           (rsp_demux_src0_data),                                       //              .data
+		.out_ready         (crosser_007_out_ready),                                     //           out.ready
+		.out_valid         (crosser_007_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_007_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_007_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_007_out_channel),                                   //              .channel
+		.out_data          (crosser_007_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_008 (
+		.in_clk            (ddr3_ram_afi_clk_clk),                                      //        in_clk.clk
+		.in_reset          (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                                           //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),                     // out_clk_reset.reset
+		.in_ready          (rsp_demux_src1_ready),                                      //            in.ready
+		.in_valid          (rsp_demux_src1_valid),                                      //              .valid
+		.in_startofpacket  (rsp_demux_src1_startofpacket),                              //              .startofpacket
+		.in_endofpacket    (rsp_demux_src1_endofpacket),                                //              .endofpacket
+		.in_channel        (rsp_demux_src1_channel),                                    //              .channel
+		.in_data           (rsp_demux_src1_data),                                       //              .data
+		.out_ready         (crosser_008_out_ready),                                     //           out.ready
+		.out_valid         (crosser_008_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_008_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_008_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_008_out_channel),                                   //              .channel
+		.out_data          (crosser_008_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_009 (
+		.in_clk            (ddr3_ram_afi_clk_clk),                                      //        in_clk.clk
+		.in_reset          (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                                           //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),                     // out_clk_reset.reset
+		.in_ready          (rsp_demux_src2_ready),                                      //            in.ready
+		.in_valid          (rsp_demux_src2_valid),                                      //              .valid
+		.in_startofpacket  (rsp_demux_src2_startofpacket),                              //              .startofpacket
+		.in_endofpacket    (rsp_demux_src2_endofpacket),                                //              .endofpacket
+		.in_channel        (rsp_demux_src2_channel),                                    //              .channel
+		.in_data           (rsp_demux_src2_data),                                       //              .data
+		.out_ready         (crosser_009_out_ready),                                     //           out.ready
+		.out_valid         (crosser_009_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_009_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_009_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_009_out_channel),                                   //              .channel
+		.out_data          (crosser_009_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_010 (
+		.in_clk            (ddr3_ram_afi_clk_clk),                                      //        in_clk.clk
+		.in_reset          (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                                           //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),                     // out_clk_reset.reset
+		.in_ready          (rsp_demux_src3_ready),                                      //            in.ready
+		.in_valid          (rsp_demux_src3_valid),                                      //              .valid
+		.in_startofpacket  (rsp_demux_src3_startofpacket),                              //              .startofpacket
+		.in_endofpacket    (rsp_demux_src3_endofpacket),                                //              .endofpacket
+		.in_channel        (rsp_demux_src3_channel),                                    //              .channel
+		.in_data           (rsp_demux_src3_data),                                       //              .data
+		.out_ready         (crosser_010_out_ready),                                     //           out.ready
+		.out_valid         (crosser_010_out_valid),                                     //              .valid
+		.out_startofpacket (crosser_010_out_startofpacket),                             //              .startofpacket
+		.out_endofpacket   (crosser_010_out_endofpacket),                               //              .endofpacket
+		.out_channel       (crosser_010_out_channel),                                   //              .channel
+		.out_data          (crosser_010_out_data),                                      //              .data
+		.in_empty          (1'b0),                                                      //   (terminated)
+		.in_error          (1'b0),                                                      //   (terminated)
+		.out_empty         (),                                                          //   (terminated)
+		.out_error         ()                                                           //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_011 (
+		.in_clk            (ext_flash_clock_bridge_out_clk_clk),          //        in_clk.clk
+		.in_reset          (ext_flash_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                             //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),       // out_clk_reset.reset
+		.in_ready          (rsp_demux_001_src0_ready),                    //            in.ready
+		.in_valid          (rsp_demux_001_src0_valid),                    //              .valid
+		.in_startofpacket  (rsp_demux_001_src0_startofpacket),            //              .startofpacket
+		.in_endofpacket    (rsp_demux_001_src0_endofpacket),              //              .endofpacket
+		.in_channel        (rsp_demux_001_src0_channel),                  //              .channel
+		.in_data           (rsp_demux_001_src0_data),                     //              .data
+		.out_ready         (crosser_011_out_ready),                       //           out.ready
+		.out_valid         (crosser_011_out_valid),                       //              .valid
+		.out_startofpacket (crosser_011_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_011_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_011_out_channel),                     //              .channel
+		.out_data          (crosser_011_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_012 (
+		.in_clk            (ext_flash_clock_bridge_out_clk_clk),          //        in_clk.clk
+		.in_reset          (ext_flash_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                             //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),       // out_clk_reset.reset
+		.in_ready          (rsp_demux_002_src0_ready),                    //            in.ready
+		.in_valid          (rsp_demux_002_src0_valid),                    //              .valid
+		.in_startofpacket  (rsp_demux_002_src0_startofpacket),            //              .startofpacket
+		.in_endofpacket    (rsp_demux_002_src0_endofpacket),              //              .endofpacket
+		.in_channel        (rsp_demux_002_src0_channel),                  //              .channel
+		.in_data           (rsp_demux_002_src0_data),                     //              .data
+		.out_ready         (crosser_012_out_ready),                       //           out.ready
+		.out_valid         (crosser_012_out_valid),                       //              .valid
+		.out_startofpacket (crosser_012_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_012_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_012_out_channel),                     //              .channel
+		.out_data          (crosser_012_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	altera_avalon_st_handshake_clock_crosser #(
+		.DATA_WIDTH          (121),
+		.BITS_PER_SYMBOL     (121),
+		.USE_PACKETS         (1),
+		.USE_CHANNEL         (1),
+		.CHANNEL_WIDTH       (21),
+		.USE_ERROR           (0),
+		.ERROR_WIDTH         (1),
+		.VALID_SYNC_DEPTH    (2),
+		.READY_SYNC_DEPTH    (2),
+		.USE_OUTPUT_PIPELINE (0)
+	) crosser_013 (
+		.in_clk            (ext_flash_clock_bridge_out_clk_clk),          //        in_clk.clk
+		.in_reset          (ext_flash_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
+		.out_clk           (sys_clk_clk_clk),                             //       out_clk.clk
+		.out_reset         (cpu_reset_reset_bridge_in_reset_reset),       // out_clk_reset.reset
+		.in_ready          (rsp_demux_002_src1_ready),                    //            in.ready
+		.in_valid          (rsp_demux_002_src1_valid),                    //              .valid
+		.in_startofpacket  (rsp_demux_002_src1_startofpacket),            //              .startofpacket
+		.in_endofpacket    (rsp_demux_002_src1_endofpacket),              //              .endofpacket
+		.in_channel        (rsp_demux_002_src1_channel),                  //              .channel
+		.in_data           (rsp_demux_002_src1_data),                     //              .data
+		.out_ready         (crosser_013_out_ready),                       //           out.ready
+		.out_valid         (crosser_013_out_valid),                       //              .valid
+		.out_startofpacket (crosser_013_out_startofpacket),               //              .startofpacket
+		.out_endofpacket   (crosser_013_out_endofpacket),                 //              .endofpacket
+		.out_channel       (crosser_013_out_channel),                     //              .channel
+		.out_data          (crosser_013_out_data),                        //              .data
+		.in_empty          (1'b0),                                        //   (terminated)
+		.in_error          (1'b0),                                        //   (terminated)
+		.out_empty         (),                                            //   (terminated)
+		.out_error         ()                                             //   (terminated)
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk   (ddr3_ram_afi_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (ddr3_ram_avl_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (ddr3_ram_avl_agent_rdata_fifo_out_data),                    //     in_0.data
+		.in_0_valid     (ddr3_ram_avl_agent_rdata_fifo_out_valid),                   //         .valid
+		.in_0_ready     (ddr3_ram_avl_agent_rdata_fifo_out_ready),                   //         .ready
+		.out_0_data     (avalon_st_adapter_out_0_data),                              //    out_0.data
+		.out_0_valid    (avalon_st_adapter_out_0_valid),                             //         .valid
+		.out_0_ready    (avalon_st_adapter_out_0_ready),                             //         .ready
+		.out_0_error    (avalon_st_adapter_out_0_error)                              //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk   (ext_flash_clock_bridge_out_clk_clk),           // in_clk_0.clk
+		.in_rst_0_reset (ext_flash_reset_reset_bridge_in_reset_reset),  // in_rst_0.reset
+		.in_0_data      (ext_flash_avl_csr_agent_rdata_fifo_out_data),  //     in_0.data
+		.in_0_valid     (ext_flash_avl_csr_agent_rdata_fifo_out_valid), //         .valid
+		.in_0_ready     (ext_flash_avl_csr_agent_rdata_fifo_out_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_001_out_0_data),             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_001_out_0_valid),            //         .valid
+		.out_0_ready    (avalon_st_adapter_001_out_0_ready),            //         .ready
+		.out_0_error    (avalon_st_adapter_001_out_0_error)             //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_002 (
+		.in_clk_0_clk   (ext_flash_clock_bridge_out_clk_clk),           // in_clk_0.clk
+		.in_rst_0_reset (ext_flash_reset_reset_bridge_in_reset_reset),  // in_rst_0.reset
+		.in_0_data      (ext_flash_avl_mem_agent_rdata_fifo_out_data),  //     in_0.data
+		.in_0_valid     (ext_flash_avl_mem_agent_rdata_fifo_out_valid), //         .valid
+		.in_0_ready     (ext_flash_avl_mem_agent_rdata_fifo_out_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_002_out_0_data),             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_002_out_0_valid),            //         .valid
+		.out_0_ready    (avalon_st_adapter_002_out_0_ready),            //         .ready
+		.out_0_error    (avalon_st_adapter_002_out_0_error)             //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_003 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (eth_tse_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (eth_tse_control_port_agent_rdata_fifo_src_data),       //     in_0.data
+		.in_0_valid     (eth_tse_control_port_agent_rdata_fifo_src_valid),      //         .valid
+		.in_0_ready     (eth_tse_control_port_agent_rdata_fifo_src_ready),      //         .ready
+		.out_0_data     (avalon_st_adapter_003_out_0_data),                     //    out_0.data
+		.out_0_valid    (avalon_st_adapter_003_out_0_valid),                    //         .valid
+		.out_0_ready    (avalon_st_adapter_003_out_0_ready),                    //         .ready
+		.out_0_error    (avalon_st_adapter_003_out_0_error)                     //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_004 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (eth_tse_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sysid_control_slave_agent_rdata_fifo_src_data),        //     in_0.data
+		.in_0_valid     (sysid_control_slave_agent_rdata_fifo_src_valid),       //         .valid
+		.in_0_ready     (sysid_control_slave_agent_rdata_fifo_src_ready),       //         .ready
+		.out_0_data     (avalon_st_adapter_004_out_0_data),                     //    out_0.data
+		.out_0_valid    (avalon_st_adapter_004_out_0_valid),                    //         .valid
+		.out_0_ready    (avalon_st_adapter_004_out_0_ready),                    //         .ready
+		.out_0_error    (avalon_st_adapter_004_out_0_error)                     //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_005 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                          // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
+		.in_0_data      (msgdma_tx_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (msgdma_tx_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (msgdma_tx_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_005_out_0_data),         //    out_0.data
+		.out_0_valid    (avalon_st_adapter_005_out_0_valid),        //         .valid
+		.out_0_ready    (avalon_st_adapter_005_out_0_ready),        //         .ready
+		.out_0_error    (avalon_st_adapter_005_out_0_error)         //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_006 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                          // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
+		.in_0_data      (msgdma_rx_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (msgdma_rx_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (msgdma_rx_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_006_out_0_data),         //    out_0.data
+		.out_0_valid    (avalon_st_adapter_006_out_0_valid),        //         .valid
+		.out_0_ready    (avalon_st_adapter_006_out_0_ready),        //         .ready
+		.out_0_error    (avalon_st_adapter_006_out_0_error)         //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_007 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                             // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),       // in_rst_0.reset
+		.in_0_data      (onchip_flash_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (onchip_flash_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (onchip_flash_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_007_out_0_data),            //    out_0.data
+		.out_0_valid    (avalon_st_adapter_007_out_0_valid),           //         .valid
+		.out_0_ready    (avalon_st_adapter_007_out_0_ready),           //         .ready
+		.out_0_error    (avalon_st_adapter_007_out_0_error)            //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_008 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                              // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
+		.in_0_data      (udp_generator_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (udp_generator_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (udp_generator_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_008_out_0_data),             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_008_out_0_valid),            //         .valid
+		.out_0_ready    (avalon_st_adapter_008_out_0_ready),            //         .ready
+		.out_0_error    (avalon_st_adapter_008_out_0_error)             //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_009 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                 // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),           // in_rst_0.reset
+		.in_0_data      (sensor_interface_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (sensor_interface_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (sensor_interface_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_009_out_0_data),                //    out_0.data
+		.out_0_valid    (avalon_st_adapter_009_out_0_valid),               //         .valid
+		.out_0_ready    (avalon_st_adapter_009_out_0_ready),               //         .ready
+		.out_0_error    (avalon_st_adapter_009_out_0_error)                //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_010 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                              // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
+		.in_0_data      (onchip_flash_data_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (onchip_flash_data_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (onchip_flash_data_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_010_out_0_data),             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_010_out_0_valid),            //         .valid
+		.out_0_ready    (avalon_st_adapter_010_out_0_ready),            //         .ready
+		.out_0_error    (avalon_st_adapter_010_out_0_error)             //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_011 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),          // in_rst_0.reset
+		.in_0_data      (cpu_debug_mem_slave_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_011_out_0_data),               //    out_0.data
+		.out_0_valid    (avalon_st_adapter_011_out_0_valid),              //         .valid
+		.out_0_ready    (avalon_st_adapter_011_out_0_ready),              //         .ready
+		.out_0_error    (avalon_st_adapter_011_out_0_error)               //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_012 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                     // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),               // in_rst_0.reset
+		.in_0_data      (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (msgdma_tx_prefetcher_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_012_out_0_data),                    //    out_0.data
+		.out_0_valid    (avalon_st_adapter_012_out_0_valid),                   //         .valid
+		.out_0_ready    (avalon_st_adapter_012_out_0_ready),                   //         .ready
+		.out_0_error    (avalon_st_adapter_012_out_0_error)                    //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_013 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                     // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),               // in_rst_0.reset
+		.in_0_data      (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (msgdma_rx_prefetcher_csr_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_013_out_0_data),                    //    out_0.data
+		.out_0_valid    (avalon_st_adapter_013_out_0_valid),                   //         .valid
+		.out_0_ready    (avalon_st_adapter_013_out_0_ready),                   //         .ready
+		.out_0_error    (avalon_st_adapter_013_out_0_error)                    //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_014 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (eth_tse_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (descriptor_memory_s1_agent_rdata_fifo_src_data),       //     in_0.data
+		.in_0_valid     (descriptor_memory_s1_agent_rdata_fifo_src_valid),      //         .valid
+		.in_0_ready     (descriptor_memory_s1_agent_rdata_fifo_src_ready),      //         .ready
+		.out_0_data     (avalon_st_adapter_014_out_0_data),                     //    out_0.data
+		.out_0_valid    (avalon_st_adapter_014_out_0_valid),                    //         .valid
+		.out_0_ready    (avalon_st_adapter_014_out_0_ready),                    //         .ready
+		.out_0_error    (avalon_st_adapter_014_out_0_error)                     //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_015 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (eth_tse_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (sys_clk_timer_s1_agent_rdata_fifo_src_data),           //     in_0.data
+		.in_0_valid     (sys_clk_timer_s1_agent_rdata_fifo_src_valid),          //         .valid
+		.in_0_ready     (sys_clk_timer_s1_agent_rdata_fifo_src_ready),          //         .ready
+		.out_0_data     (avalon_st_adapter_015_out_0_data),                     //    out_0.data
+		.out_0_valid    (avalon_st_adapter_015_out_0_valid),                    //         .valid
+		.out_0_ready    (avalon_st_adapter_015_out_0_ready),                    //         .ready
+		.out_0_error    (avalon_st_adapter_015_out_0_error)                     //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_016 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                                      // in_clk_0.clk
+		.in_rst_0_reset (eth_tse_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (output_pio_s1_agent_rdata_fifo_src_data),              //     in_0.data
+		.in_0_valid     (output_pio_s1_agent_rdata_fifo_src_valid),             //         .valid
+		.in_0_ready     (output_pio_s1_agent_rdata_fifo_src_ready),             //         .ready
+		.out_0_data     (avalon_st_adapter_016_out_0_data),                     //    out_0.data
+		.out_0_valid    (avalon_st_adapter_016_out_0_valid),                    //         .valid
+		.out_0_ready    (avalon_st_adapter_016_out_0_ready),                    //         .ready
+		.out_0_error    (avalon_st_adapter_016_out_0_error)                     //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_017 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                          // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
+		.in_0_data      (button_pio_s1_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (button_pio_s1_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (button_pio_s1_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_017_out_0_data),         //    out_0.data
+		.out_0_valid    (avalon_st_adapter_017_out_0_valid),        //         .valid
+		.out_0_ready    (avalon_st_adapter_017_out_0_ready),        //         .ready
+		.out_0_error    (avalon_st_adapter_017_out_0_error)         //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_018 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                          // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),    // in_rst_0.reset
+		.in_0_data      (debug_uart_s1_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (debug_uart_s1_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (debug_uart_s1_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_018_out_0_data),         //    out_0.data
+		.out_0_valid    (avalon_st_adapter_018_out_0_valid),        //         .valid
+		.out_0_ready    (avalon_st_adapter_018_out_0_ready),        //         .ready
+		.out_0_error    (avalon_st_adapter_018_out_0_error)         //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_019 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                           // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),     // in_rst_0.reset
+		.in_0_data      (frame_timer_s1_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (frame_timer_s1_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (frame_timer_s1_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_019_out_0_data),          //    out_0.data
+		.out_0_valid    (avalon_st_adapter_019_out_0_valid),         //         .valid
+		.out_0_ready    (avalon_st_adapter_019_out_0_ready),         //         .ready
+		.out_0_error    (avalon_st_adapter_019_out_0_error)          //         .error
+	);
+
+	q_sys_mm_interconnect_1_avalon_st_adapter_020 #(
+		.inBitsPerSymbol (18),
+		.inUsePackets    (0),
+		.inDataWidth     (18),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (18),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_020 (
+		.in_clk_0_clk   (sys_clk_clk_clk),                               // in_clk_0.clk
+		.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset),         // in_rst_0.reset
+		.in_0_data      (calibration_ram_s1_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (calibration_ram_s1_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (calibration_ram_s1_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_020_out_0_data),              //    out_0.data
+		.out_0_valid    (avalon_st_adapter_020_out_0_valid),             //         .valid
+		.out_0_ready    (avalon_st_adapter_020_out_0_ready),             //         .ready
+		.out_0_error    (avalon_st_adapter_020_out_0_error)              //         .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v
new file mode 100644
index 0000000..ce843a1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_1_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_1_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v
new file mode 100644
index 0000000..5fe2086
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_1_avalon_st_adapter_020.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_1_avalon_st_adapter_020 #(
+		parameter inBitsPerSymbol = 18,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 18,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 18,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [17:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [17:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv
new file mode 100644
index 0000000..1a6bec7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         18
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [18-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [18-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021.v
new file mode 100644
index 0000000..34557fc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021.v
@@ -0,0 +1,202 @@
+// q_sys_mm_interconnect_1_avalon_st_adapter_021.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_mm_interconnect_1_avalon_st_adapter_021 #(
+		parameter inBitsPerSymbol = 18,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 18,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 18,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [17:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [17:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 18)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0.sv
new file mode 100644
index 0000000..b3add7f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         18
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_1_avalon_st_adapter_021_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [18-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [18-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..93e5dd0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv
new file mode 100644
index 0000000..5646dc0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv
@@ -0,0 +1,400 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_demux
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         21
+//   VALID_WIDTH:         21
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [21-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src4_channel, // ST_CHANNEL_W=21
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+    output reg                      src5_valid,
+    output reg [121-1    : 0] src5_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src5_channel, // ST_CHANNEL_W=21
+    output reg                      src5_startofpacket,
+    output reg                      src5_endofpacket,
+    input                           src5_ready,
+
+    output reg                      src6_valid,
+    output reg [121-1    : 0] src6_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src6_channel, // ST_CHANNEL_W=21
+    output reg                      src6_startofpacket,
+    output reg                      src6_endofpacket,
+    input                           src6_ready,
+
+    output reg                      src7_valid,
+    output reg [121-1    : 0] src7_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src7_channel, // ST_CHANNEL_W=21
+    output reg                      src7_startofpacket,
+    output reg                      src7_endofpacket,
+    input                           src7_ready,
+
+    output reg                      src8_valid,
+    output reg [121-1    : 0] src8_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src8_channel, // ST_CHANNEL_W=21
+    output reg                      src8_startofpacket,
+    output reg                      src8_endofpacket,
+    input                           src8_ready,
+
+    output reg                      src9_valid,
+    output reg [121-1    : 0] src9_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src9_channel, // ST_CHANNEL_W=21
+    output reg                      src9_startofpacket,
+    output reg                      src9_endofpacket,
+    input                           src9_ready,
+
+    output reg                      src10_valid,
+    output reg [121-1    : 0] src10_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src10_channel, // ST_CHANNEL_W=21
+    output reg                      src10_startofpacket,
+    output reg                      src10_endofpacket,
+    input                           src10_ready,
+
+    output reg                      src11_valid,
+    output reg [121-1    : 0] src11_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src11_channel, // ST_CHANNEL_W=21
+    output reg                      src11_startofpacket,
+    output reg                      src11_endofpacket,
+    input                           src11_ready,
+
+    output reg                      src12_valid,
+    output reg [121-1    : 0] src12_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src12_channel, // ST_CHANNEL_W=21
+    output reg                      src12_startofpacket,
+    output reg                      src12_endofpacket,
+    input                           src12_ready,
+
+    output reg                      src13_valid,
+    output reg [121-1    : 0] src13_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src13_channel, // ST_CHANNEL_W=21
+    output reg                      src13_startofpacket,
+    output reg                      src13_endofpacket,
+    input                           src13_ready,
+
+    output reg                      src14_valid,
+    output reg [121-1    : 0] src14_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src14_channel, // ST_CHANNEL_W=21
+    output reg                      src14_startofpacket,
+    output reg                      src14_endofpacket,
+    input                           src14_ready,
+
+    output reg                      src15_valid,
+    output reg [121-1    : 0] src15_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src15_channel, // ST_CHANNEL_W=21
+    output reg                      src15_startofpacket,
+    output reg                      src15_endofpacket,
+    input                           src15_ready,
+
+    output reg                      src16_valid,
+    output reg [121-1    : 0] src16_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src16_channel, // ST_CHANNEL_W=21
+    output reg                      src16_startofpacket,
+    output reg                      src16_endofpacket,
+    input                           src16_ready,
+
+    output reg                      src17_valid,
+    output reg [121-1    : 0] src17_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src17_channel, // ST_CHANNEL_W=21
+    output reg                      src17_startofpacket,
+    output reg                      src17_endofpacket,
+    input                           src17_ready,
+
+    output reg                      src18_valid,
+    output reg [121-1    : 0] src18_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src18_channel, // ST_CHANNEL_W=21
+    output reg                      src18_startofpacket,
+    output reg                      src18_endofpacket,
+    input                           src18_ready,
+
+    output reg                      src19_valid,
+    output reg [121-1    : 0] src19_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src19_channel, // ST_CHANNEL_W=21
+    output reg                      src19_startofpacket,
+    output reg                      src19_endofpacket,
+    input                           src19_ready,
+
+    output reg                      src20_valid,
+    output reg [121-1    : 0] src20_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src20_channel, // ST_CHANNEL_W=21
+    output reg                      src20_startofpacket,
+    output reg                      src20_endofpacket,
+    input                           src20_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 21;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid[2];
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid[3];
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid[4];
+
+        src5_data          = sink_data;
+        src5_startofpacket = sink_startofpacket;
+        src5_endofpacket   = sink_endofpacket;
+        src5_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src5_valid         = sink_channel[5] && sink_valid[5];
+
+        src6_data          = sink_data;
+        src6_startofpacket = sink_startofpacket;
+        src6_endofpacket   = sink_endofpacket;
+        src6_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src6_valid         = sink_channel[6] && sink_valid[6];
+
+        src7_data          = sink_data;
+        src7_startofpacket = sink_startofpacket;
+        src7_endofpacket   = sink_endofpacket;
+        src7_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src7_valid         = sink_channel[7] && sink_valid[7];
+
+        src8_data          = sink_data;
+        src8_startofpacket = sink_startofpacket;
+        src8_endofpacket   = sink_endofpacket;
+        src8_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src8_valid         = sink_channel[8] && sink_valid[8];
+
+        src9_data          = sink_data;
+        src9_startofpacket = sink_startofpacket;
+        src9_endofpacket   = sink_endofpacket;
+        src9_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src9_valid         = sink_channel[9] && sink_valid[9];
+
+        src10_data          = sink_data;
+        src10_startofpacket = sink_startofpacket;
+        src10_endofpacket   = sink_endofpacket;
+        src10_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src10_valid         = sink_channel[10] && sink_valid[10];
+
+        src11_data          = sink_data;
+        src11_startofpacket = sink_startofpacket;
+        src11_endofpacket   = sink_endofpacket;
+        src11_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src11_valid         = sink_channel[11] && sink_valid[11];
+
+        src12_data          = sink_data;
+        src12_startofpacket = sink_startofpacket;
+        src12_endofpacket   = sink_endofpacket;
+        src12_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src12_valid         = sink_channel[12] && sink_valid[12];
+
+        src13_data          = sink_data;
+        src13_startofpacket = sink_startofpacket;
+        src13_endofpacket   = sink_endofpacket;
+        src13_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src13_valid         = sink_channel[13] && sink_valid[13];
+
+        src14_data          = sink_data;
+        src14_startofpacket = sink_startofpacket;
+        src14_endofpacket   = sink_endofpacket;
+        src14_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src14_valid         = sink_channel[14] && sink_valid[14];
+
+        src15_data          = sink_data;
+        src15_startofpacket = sink_startofpacket;
+        src15_endofpacket   = sink_endofpacket;
+        src15_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src15_valid         = sink_channel[15] && sink_valid[15];
+
+        src16_data          = sink_data;
+        src16_startofpacket = sink_startofpacket;
+        src16_endofpacket   = sink_endofpacket;
+        src16_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src16_valid         = sink_channel[16] && sink_valid[16];
+
+        src17_data          = sink_data;
+        src17_startofpacket = sink_startofpacket;
+        src17_endofpacket   = sink_endofpacket;
+        src17_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src17_valid         = sink_channel[17] && sink_valid[17];
+
+        src18_data          = sink_data;
+        src18_startofpacket = sink_startofpacket;
+        src18_endofpacket   = sink_endofpacket;
+        src18_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src18_valid         = sink_channel[18] && sink_valid[18];
+
+        src19_data          = sink_data;
+        src19_startofpacket = sink_startofpacket;
+        src19_endofpacket   = sink_endofpacket;
+        src19_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src19_valid         = sink_channel[19] && sink_valid[19];
+
+        src20_data          = sink_data;
+        src20_startofpacket = sink_startofpacket;
+        src20_endofpacket   = sink_endofpacket;
+        src20_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src20_valid         = sink_channel[20] && sink_valid[20];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+    assign ready_vector[5] = src5_ready;
+    assign ready_vector[6] = src6_ready;
+    assign ready_vector[7] = src7_ready;
+    assign ready_vector[8] = src8_ready;
+    assign ready_vector[9] = src9_ready;
+    assign ready_vector[10] = src10_ready;
+    assign ready_vector[11] = src11_ready;
+    assign ready_vector[12] = src12_ready;
+    assign ready_vector[13] = src13_ready;
+    assign ready_vector[14] = src14_ready;
+    assign ready_vector[15] = src15_ready;
+    assign ready_vector[16] = src16_ready;
+    assign ready_vector[17] = src17_ready;
+    assign ready_vector[18] = src18_ready;
+    assign ready_vector[19] = src19_ready;
+    assign ready_vector[20] = src20_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv
new file mode 100644
index 0000000..c64779a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_demux_001
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         21
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_demux_001
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [21-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid[0];
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid[1];
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid[2];
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid[3];
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv
new file mode 100644
index 0000000..2d3a112
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_demux_002
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_demux_002
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{20{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv
new file mode 100644
index 0000000..9646598
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv
@@ -0,0 +1,408 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_mux
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv
new file mode 100644
index 0000000..93bcec5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_mux_001
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_mux_001
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv
new file mode 100644
index 0000000..6193fc2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv
@@ -0,0 +1,366 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_mux_002
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_mux_002
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv
new file mode 100644
index 0000000..13fdeb9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv
@@ -0,0 +1,429 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_cmd_mux_014
+//   NUM_INPUTS:          5
+//   ARBITRATION_SHARES:  1 1 1 1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_cmd_mux_014
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [21-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 5;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+    assign eop[2] = sink2_endofpacket;
+    assign eop[3] = sink3_endofpacket;
+    assign eop[4] = sink4_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv
new file mode 100644
index 0000000..996a967
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv
@@ -0,0 +1,365 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    localparam PAD1 = log2ceil(64'h18000000 - 64'h14000000); 
+    localparam PAD2 = log2ceil(64'h18400000 - 64'h18200000); 
+    localparam PAD3 = log2ceil(64'h18402000 - 64'h18400000); 
+    localparam PAD4 = log2ceil(64'h18403000 - 64'h18402800); 
+    localparam PAD5 = log2ceil(64'h18403400 - 64'h18403000); 
+    localparam PAD6 = log2ceil(64'h18403800 - 64'h18403400); 
+    localparam PAD7 = log2ceil(64'h18403c20 - 64'h18403c00); 
+    localparam PAD8 = log2ceil(64'h18403c40 - 64'h18403c20); 
+    localparam PAD9 = log2ceil(64'h18403c60 - 64'h18403c40); 
+    localparam PAD10 = log2ceil(64'h18403c80 - 64'h18403c60); 
+    localparam PAD11 = log2ceil(64'h18403ca0 - 64'h18403c80); 
+    localparam PAD12 = log2ceil(64'h18403cc0 - 64'h18403ca0); 
+    localparam PAD13 = log2ceil(64'h18403ce0 - 64'h18403cc0); 
+    localparam PAD14 = log2ceil(64'h18403d00 - 64'h18403ce0); 
+    localparam PAD15 = log2ceil(64'h18403d20 - 64'h18403d00); 
+    localparam PAD16 = log2ceil(64'h18403d40 - 64'h18403d20); 
+    localparam PAD17 = log2ceil(64'h18403d50 - 64'h18403d40); 
+    localparam PAD18 = log2ceil(64'h18403d60 - 64'h18403d50); 
+    localparam PAD19 = log2ceil(64'h18403d68 - 64'h18403d60); 
+    localparam PAD20 = log2ceil(64'h18403d70 - 64'h18403d68); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18403d70;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_1_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x8000000 .. 0x10000000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 29'h8000000   ) begin
+            src_channel = 21'b000000000000000000001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+    end
+
+    // ( 0x14000000 .. 0x18000000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 29'h14000000   ) begin
+            src_channel = 21'b000000000000000000100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
+    end
+
+    // ( 0x18200000 .. 0x18400000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 29'h18200000   ) begin
+            src_channel = 21'b000000000010000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
+    end
+
+    // ( 0x18400000 .. 0x18402000 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 29'h18400000   ) begin
+            src_channel = 21'b000000100000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+    end
+
+    // ( 0x18402800 .. 0x18403000 )
+    if ( {address[RG:PAD4],{PAD4{1'b0}}} == 29'h18402800   ) begin
+            src_channel = 21'b000000000100000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x18403000 .. 0x18403400 )
+    if ( {address[RG:PAD5],{PAD5{1'b0}}} == 29'h18403000   ) begin
+            src_channel = 21'b000000000000000001000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
+    end
+
+    // ( 0x18403400 .. 0x18403800 )
+    if ( {address[RG:PAD6],{PAD6{1'b0}}} == 29'h18403400   ) begin
+            src_channel = 21'b100000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+    // ( 0x18403c00 .. 0x18403c20 )
+    if ( {address[RG:PAD7],{PAD7{1'b0}}} == 29'h18403c00   ) begin
+            src_channel = 21'b010000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
+    end
+
+    // ( 0x18403c20 .. 0x18403c40 )
+    if ( {address[RG:PAD8],{PAD8{1'b0}}} == 29'h18403c20   ) begin
+            src_channel = 21'b001000000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
+    end
+
+    // ( 0x18403c40 .. 0x18403c60 )
+    if ( {address[RG:PAD9],{PAD9{1'b0}}} == 29'h18403c40   ) begin
+            src_channel = 21'b000010000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16;
+    end
+
+    // ( 0x18403c60 .. 0x18403c80 )
+    if ( {address[RG:PAD10],{PAD10{1'b0}}} == 29'h18403c60   ) begin
+            src_channel = 21'b000001000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 18;
+    end
+
+    // ( 0x18403c80 .. 0x18403ca0 )
+    if ( {address[RG:PAD11],{PAD11{1'b0}}} == 29'h18403c80   ) begin
+            src_channel = 21'b000000010000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
+    end
+
+    // ( 0x18403ca0 .. 0x18403cc0 )
+    if ( {address[RG:PAD12],{PAD12{1'b0}}} == 29'h18403ca0   ) begin
+            src_channel = 21'b000000001000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
+    end
+
+    // ( 0x18403cc0 .. 0x18403ce0 )
+    if ( {address[RG:PAD13],{PAD13{1'b0}}} == 29'h18403cc0   ) begin
+            src_channel = 21'b000000000000100000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 20;
+    end
+
+    // ( 0x18403ce0 .. 0x18403d00 )
+    if ( {address[RG:PAD14],{PAD14{1'b0}}} == 29'h18403ce0   ) begin
+            src_channel = 21'b000000000000001000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
+    end
+
+    // ( 0x18403d00 .. 0x18403d20 )
+    if ( {address[RG:PAD15],{PAD15{1'b0}}} == 29'h18403d00   ) begin
+            src_channel = 21'b000000000000000100000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
+    end
+
+    // ( 0x18403d20 .. 0x18403d40 )
+    if ( {address[RG:PAD16],{PAD16{1'b0}}} == 29'h18403d20   ) begin
+            src_channel = 21'b000000000000000000010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
+    end
+
+    // ( 0x18403d40 .. 0x18403d50 )
+    if ( {address[RG:PAD17],{PAD17{1'b0}}} == 29'h18403d40  && read_transaction  ) begin
+            src_channel = 21'b000100000000000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+    // ( 0x18403d50 .. 0x18403d60 )
+    if ( {address[RG:PAD18],{PAD18{1'b0}}} == 29'h18403d50   ) begin
+            src_channel = 21'b000000000001000000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17;
+    end
+
+    // ( 0x18403d60 .. 0x18403d68 )
+    if ( {address[RG:PAD19],{PAD19{1'b0}}} == 29'h18403d60   ) begin
+            src_channel = 21'b000000000000010000000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
+    end
+
+    // ( 0x18403d68 .. 0x18403d70 )
+    if ( {address[RG:PAD20],{PAD20{1'b0}}} == 29'h18403d68  && read_transaction  ) begin
+            src_channel = 21'b000000000000000010000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 19;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv
new file mode 100644
index 0000000..fdfe7a5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv
@@ -0,0 +1,241 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_001_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_001
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    localparam PAD1 = log2ceil(64'h18000000 - 64'h14000000); 
+    localparam PAD2 = log2ceil(64'h18400000 - 64'h18200000); 
+    localparam PAD3 = log2ceil(64'h18403000 - 64'h18402800); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18403000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_001_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x8000000 .. 0x10000000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 29'h8000000   ) begin
+            src_channel = 21'b0001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+    end
+
+    // ( 0x14000000 .. 0x18000000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 29'h14000000   ) begin
+            src_channel = 21'b0010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
+    end
+
+    // ( 0x18200000 .. 0x18400000 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 29'h18200000   ) begin
+            src_channel = 21'b0100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
+    end
+
+    // ( 0x18402800 .. 0x18403000 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 29'h18402800   ) begin
+            src_channel = 21'b1000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv
new file mode 100644
index 0000000..a2ab759
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_002_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 3 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_002
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h10000000 - 64'h8000000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h10000000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_002_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 8000000 .. 10000000 )
+          src_channel = 21'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv
new file mode 100644
index 0000000..96d3f91
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_004_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 5 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_004
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h18402000 - 64'h18400000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h18402000;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_004_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+           
+         
+          // ( 18400000 .. 18402000 )
+          src_channel = 21'b1;
+          src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
+	     
+        
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv
new file mode 100644
index 0000000..03e7310
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv
@@ -0,0 +1,234 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_008_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_008
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_1_router_008_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b0001;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 21'b0010;
+        end
+
+        if (destid == 7  && read_transaction) begin
+            src_channel = 21'b0100;
+        end
+
+        if (destid == 4  && write_transaction) begin
+            src_channel = 21'b1000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv
new file mode 100644
index 0000000..a3530a2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_009_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_009
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_009_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv
new file mode 100644
index 0000000..ffb4ec8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv
@@ -0,0 +1,224 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_010_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_010
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_1_router_010_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b01;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 21'b10;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv
new file mode 100644
index 0000000..fc8148a
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv
@@ -0,0 +1,238 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_022_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [107 - 103 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[107 - 103 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_022
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [121-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [121-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 64;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 107;
+    localparam PKT_DEST_ID_L = 103;
+    localparam PKT_PROTECTION_H = 111;
+    localparam PKT_PROTECTION_L = 109;
+    localparam ST_DATA_W = 121;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 67;
+    localparam PKT_TRANS_READ  = 68;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire write_transaction;
+    assign write_transaction = sink_data[PKT_TRANS_WRITE];
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    q_sys_mm_interconnect_1_router_022_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b00001;
+        end
+
+        if (destid == 5  && read_transaction) begin
+            src_channel = 21'b00010;
+        end
+
+        if (destid == 2  && read_transaction) begin
+            src_channel = 21'b00100;
+        end
+
+        if (destid == 6  && write_transaction) begin
+            src_channel = 21'b01000;
+        end
+
+        if (destid == 3  && write_transaction) begin
+            src_channel = 21'b10000;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv
new file mode 100644
index 0000000..d53d91f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_028_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [89 - 85 : 0] default_destination_id,
+   output [21-1 : 0] default_wr_channel,
+   output [21-1 : 0] default_rd_channel,
+   output [21-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[89 - 85 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 21'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 21'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 21'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_028
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [103-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [103-1    : 0] src_data,
+    output reg [21-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 46;
+    localparam PKT_ADDR_L = 18;
+    localparam PKT_DEST_ID_H = 89;
+    localparam PKT_DEST_ID_L = 85;
+    localparam PKT_PROTECTION_H = 93;
+    localparam PKT_PROTECTION_L = 91;
+    localparam ST_DATA_W = 103;
+    localparam ST_CHANNEL_W = 21;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 49;
+    localparam PKT_TRANS_READ  = 50;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [21-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_028_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 21'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_029.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_029.sv
new file mode 100644
index 0000000..b668ea7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_029.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module q_sys_mm_interconnect_1_router_029_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [89 - 85 : 0] default_destination_id,
+   output [22-1 : 0] default_wr_channel,
+   output [22-1 : 0] default_rd_channel,
+   output [22-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[89 - 85 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module q_sys_mm_interconnect_1_router_029
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [103-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [103-1    : 0] src_data,
+    output reg [22-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 46;
+    localparam PKT_ADDR_L = 18;
+    localparam PKT_DEST_ID_H = 89;
+    localparam PKT_DEST_ID_L = 85;
+    localparam PKT_PROTECTION_H = 93;
+    localparam PKT_PROTECTION_L = 91;
+    localparam ST_DATA_W = 103;
+    localparam ST_CHANNEL_W = 22;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 49;
+    localparam PKT_TRANS_READ  = 50;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [22-1 : 0] default_src_channel;
+
+
+
+
+
+
+    q_sys_mm_interconnect_1_router_029_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 22'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv
new file mode 100644
index 0000000..af2f669
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv
@@ -0,0 +1,145 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_demux
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv
new file mode 100644
index 0000000..2aa540f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_demux_001
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_demux_001
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{20{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv
new file mode 100644
index 0000000..0c99e42
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_demux_002
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_demux_002
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{19{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv
new file mode 100644
index 0000000..18dcc52
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_demux_010
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_demux_010
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{19{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv
new file mode 100644
index 0000000..4d48e7e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv
@@ -0,0 +1,160 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_demux_014
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+//   NUM_OUTPUTS:         5
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_demux_014
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [121-1    : 0]   sink_data, // ST_DATA_W=121
+    input  [21-1 : 0]   sink_channel, // ST_CHANNEL_W=21
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [121-1    : 0] src0_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src0_channel, // ST_CHANNEL_W=21
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [121-1    : 0] src1_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src1_channel, // ST_CHANNEL_W=21
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [121-1    : 0] src2_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src2_channel, // ST_CHANNEL_W=21
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [121-1    : 0] src3_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src3_channel, // ST_CHANNEL_W=21
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+    output reg                      src4_valid,
+    output reg [121-1    : 0] src4_data, // ST_DATA_W=121
+    output reg [21-1 : 0] src4_channel, // ST_CHANNEL_W=21
+    output reg                      src4_startofpacket,
+    output reg                      src4_endofpacket,
+    input                           src4_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 5;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+        src4_data          = sink_data;
+        src4_startofpacket = sink_startofpacket;
+        src4_endofpacket   = sink_endofpacket;
+        src4_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src4_valid         = sink_channel[4] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+    assign ready_vector[4] = src4_ready;
+
+    assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv
new file mode 100644
index 0000000..683708f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv
@@ -0,0 +1,725 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_mux
+//   NUM_INPUTS:          21
+//   ARBITRATION_SHARES:  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+    input                       sink4_valid,
+    input [121-1   : 0]  sink4_data,
+    input [21-1: 0]  sink4_channel,
+    input                       sink4_startofpacket,
+    input                       sink4_endofpacket,
+    output                      sink4_ready,
+
+    input                       sink5_valid,
+    input [121-1   : 0]  sink5_data,
+    input [21-1: 0]  sink5_channel,
+    input                       sink5_startofpacket,
+    input                       sink5_endofpacket,
+    output                      sink5_ready,
+
+    input                       sink6_valid,
+    input [121-1   : 0]  sink6_data,
+    input [21-1: 0]  sink6_channel,
+    input                       sink6_startofpacket,
+    input                       sink6_endofpacket,
+    output                      sink6_ready,
+
+    input                       sink7_valid,
+    input [121-1   : 0]  sink7_data,
+    input [21-1: 0]  sink7_channel,
+    input                       sink7_startofpacket,
+    input                       sink7_endofpacket,
+    output                      sink7_ready,
+
+    input                       sink8_valid,
+    input [121-1   : 0]  sink8_data,
+    input [21-1: 0]  sink8_channel,
+    input                       sink8_startofpacket,
+    input                       sink8_endofpacket,
+    output                      sink8_ready,
+
+    input                       sink9_valid,
+    input [121-1   : 0]  sink9_data,
+    input [21-1: 0]  sink9_channel,
+    input                       sink9_startofpacket,
+    input                       sink9_endofpacket,
+    output                      sink9_ready,
+
+    input                       sink10_valid,
+    input [121-1   : 0]  sink10_data,
+    input [21-1: 0]  sink10_channel,
+    input                       sink10_startofpacket,
+    input                       sink10_endofpacket,
+    output                      sink10_ready,
+
+    input                       sink11_valid,
+    input [121-1   : 0]  sink11_data,
+    input [21-1: 0]  sink11_channel,
+    input                       sink11_startofpacket,
+    input                       sink11_endofpacket,
+    output                      sink11_ready,
+
+    input                       sink12_valid,
+    input [121-1   : 0]  sink12_data,
+    input [21-1: 0]  sink12_channel,
+    input                       sink12_startofpacket,
+    input                       sink12_endofpacket,
+    output                      sink12_ready,
+
+    input                       sink13_valid,
+    input [121-1   : 0]  sink13_data,
+    input [21-1: 0]  sink13_channel,
+    input                       sink13_startofpacket,
+    input                       sink13_endofpacket,
+    output                      sink13_ready,
+
+    input                       sink14_valid,
+    input [121-1   : 0]  sink14_data,
+    input [21-1: 0]  sink14_channel,
+    input                       sink14_startofpacket,
+    input                       sink14_endofpacket,
+    output                      sink14_ready,
+
+    input                       sink15_valid,
+    input [121-1   : 0]  sink15_data,
+    input [21-1: 0]  sink15_channel,
+    input                       sink15_startofpacket,
+    input                       sink15_endofpacket,
+    output                      sink15_ready,
+
+    input                       sink16_valid,
+    input [121-1   : 0]  sink16_data,
+    input [21-1: 0]  sink16_channel,
+    input                       sink16_startofpacket,
+    input                       sink16_endofpacket,
+    output                      sink16_ready,
+
+    input                       sink17_valid,
+    input [121-1   : 0]  sink17_data,
+    input [21-1: 0]  sink17_channel,
+    input                       sink17_startofpacket,
+    input                       sink17_endofpacket,
+    output                      sink17_ready,
+
+    input                       sink18_valid,
+    input [121-1   : 0]  sink18_data,
+    input [21-1: 0]  sink18_channel,
+    input                       sink18_startofpacket,
+    input                       sink18_endofpacket,
+    output                      sink18_ready,
+
+    input                       sink19_valid,
+    input [121-1   : 0]  sink19_data,
+    input [21-1: 0]  sink19_channel,
+    input                       sink19_startofpacket,
+    input                       sink19_endofpacket,
+    output                      sink19_ready,
+
+    input                       sink20_valid,
+    input [121-1   : 0]  sink20_data,
+    input [21-1: 0]  sink20_channel,
+    input                       sink20_startofpacket,
+    input                       sink20_endofpacket,
+    output                      sink20_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 21;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+    wire [PAYLOAD_W - 1 : 0] sink4_payload;
+    wire [PAYLOAD_W - 1 : 0] sink5_payload;
+    wire [PAYLOAD_W - 1 : 0] sink6_payload;
+    wire [PAYLOAD_W - 1 : 0] sink7_payload;
+    wire [PAYLOAD_W - 1 : 0] sink8_payload;
+    wire [PAYLOAD_W - 1 : 0] sink9_payload;
+    wire [PAYLOAD_W - 1 : 0] sink10_payload;
+    wire [PAYLOAD_W - 1 : 0] sink11_payload;
+    wire [PAYLOAD_W - 1 : 0] sink12_payload;
+    wire [PAYLOAD_W - 1 : 0] sink13_payload;
+    wire [PAYLOAD_W - 1 : 0] sink14_payload;
+    wire [PAYLOAD_W - 1 : 0] sink15_payload;
+    wire [PAYLOAD_W - 1 : 0] sink16_payload;
+    wire [PAYLOAD_W - 1 : 0] sink17_payload;
+    wire [PAYLOAD_W - 1 : 0] sink18_payload;
+    wire [PAYLOAD_W - 1 : 0] sink19_payload;
+    wire [PAYLOAD_W - 1 : 0] sink20_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+    assign valid[4] = sink4_valid;
+    assign valid[5] = sink5_valid;
+    assign valid[6] = sink6_valid;
+    assign valid[7] = sink7_valid;
+    assign valid[8] = sink8_valid;
+    assign valid[9] = sink9_valid;
+    assign valid[10] = sink10_valid;
+    assign valid[11] = sink11_valid;
+    assign valid[12] = sink12_valid;
+    assign valid[13] = sink13_valid;
+    assign valid[14] = sink14_valid;
+    assign valid[15] = sink15_valid;
+    assign valid[16] = sink16_valid;
+    assign valid[17] = sink17_valid;
+    assign valid[18] = sink18_valid;
+    assign valid[19] = sink19_valid;
+    assign valid[20] = sink20_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+      lock[4] = sink4_data[69];
+      lock[5] = sink5_data[69];
+      lock[6] = sink6_data[69];
+      lock[7] = sink7_data[69];
+      lock[8] = sink8_data[69];
+      lock[9] = sink9_data[69];
+      lock[10] = sink10_data[69];
+      lock[11] = sink11_data[69];
+      lock[12] = sink12_data[69];
+      lock[13] = sink13_data[69];
+      lock[14] = sink14_data[69];
+      lock[15] = sink15_data[69];
+      lock[16] = sink16_data[69];
+      lock[17] = sink17_data[69];
+      lock[18] = sink18_data[69];
+      lock[19] = sink19_data[69];
+      lock[20] = sink20_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+    // 4      |      1       |  0
+    // 5      |      1       |  0
+    // 6      |      1       |  0
+    // 7      |      1       |  0
+    // 8      |      1       |  0
+    // 9      |      1       |  0
+    // 10      |      1       |  0
+    // 11      |      1       |  0
+    // 12      |      1       |  0
+    // 13      |      1       |  0
+    // 14      |      1       |  0
+    // 15      |      1       |  0
+    // 16      |      1       |  0
+    // 17      |      1       |  0
+    // 18      |      1       |  0
+    // 19      |      1       |  0
+    // 20      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_18 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_19 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_20 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+    share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
+    share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
+    share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
+    share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
+    share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
+    share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
+    share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
+    share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
+    share_13 & { SHARE_COUNTER_W {next_grant[13]} } |
+    share_14 & { SHARE_COUNTER_W {next_grant[14]} } |
+    share_15 & { SHARE_COUNTER_W {next_grant[15]} } |
+    share_16 & { SHARE_COUNTER_W {next_grant[16]} } |
+    share_17 & { SHARE_COUNTER_W {next_grant[17]} } |
+    share_18 & { SHARE_COUNTER_W {next_grant[18]} } |
+    share_19 & { SHARE_COUNTER_W {next_grant[19]} } |
+    share_20 & { SHARE_COUNTER_W {next_grant[20]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+    wire final_packet_4 = 1'b1;
+
+    wire final_packet_5 = 1'b1;
+
+    wire final_packet_6 = 1'b1;
+
+    wire final_packet_7 = 1'b1;
+
+    wire final_packet_8 = 1'b1;
+
+    wire final_packet_9 = 1'b1;
+
+    wire final_packet_10 = 1'b1;
+
+    wire final_packet_11 = 1'b1;
+
+    wire final_packet_12 = 1'b1;
+
+    wire final_packet_13 = 1'b1;
+
+    wire final_packet_14 = 1'b1;
+
+    wire final_packet_15 = 1'b1;
+
+    wire final_packet_16 = 1'b1;
+
+    wire final_packet_17 = 1'b1;
+
+    wire final_packet_18 = 1'b1;
+
+    wire final_packet_19 = 1'b1;
+
+    wire final_packet_20 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_20,
+    final_packet_19,
+    final_packet_18,
+    final_packet_17,
+    final_packet_16,
+    final_packet_15,
+    final_packet_14,
+    final_packet_13,
+    final_packet_12,
+    final_packet_11,
+    final_packet_10,
+    final_packet_9,
+    final_packet_8,
+    final_packet_7,
+    final_packet_6,
+    final_packet_5,
+    final_packet_4,
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+    assign sink4_ready = src_ready && grant[4];
+    assign sink5_ready = src_ready && grant[5];
+    assign sink6_ready = src_ready && grant[6];
+    assign sink7_ready = src_ready && grant[7];
+    assign sink8_ready = src_ready && grant[8];
+    assign sink9_ready = src_ready && grant[9];
+    assign sink10_ready = src_ready && grant[10];
+    assign sink11_ready = src_ready && grant[11];
+    assign sink12_ready = src_ready && grant[12];
+    assign sink13_ready = src_ready && grant[13];
+    assign sink14_ready = src_ready && grant[14];
+    assign sink15_ready = src_ready && grant[15];
+    assign sink16_ready = src_ready && grant[16];
+    assign sink17_ready = src_ready && grant[17];
+    assign sink18_ready = src_ready && grant[18];
+    assign sink19_ready = src_ready && grant[19];
+    assign sink20_ready = src_ready && grant[20];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} } |
+      sink5_payload & {PAYLOAD_W {grant[5]} } |
+      sink6_payload & {PAYLOAD_W {grant[6]} } |
+      sink7_payload & {PAYLOAD_W {grant[7]} } |
+      sink8_payload & {PAYLOAD_W {grant[8]} } |
+      sink9_payload & {PAYLOAD_W {grant[9]} } |
+      sink10_payload & {PAYLOAD_W {grant[10]} } |
+      sink11_payload & {PAYLOAD_W {grant[11]} } |
+      sink12_payload & {PAYLOAD_W {grant[12]} } |
+      sink13_payload & {PAYLOAD_W {grant[13]} } |
+      sink14_payload & {PAYLOAD_W {grant[14]} } |
+      sink15_payload & {PAYLOAD_W {grant[15]} } |
+      sink16_payload & {PAYLOAD_W {grant[16]} } |
+      sink17_payload & {PAYLOAD_W {grant[17]} } |
+      sink18_payload & {PAYLOAD_W {grant[18]} } |
+      sink19_payload & {PAYLOAD_W {grant[19]} } |
+      sink20_payload & {PAYLOAD_W {grant[20]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+    assign sink4_payload = {sink4_channel,sink4_data,
+    sink4_startofpacket,sink4_endofpacket};
+    assign sink5_payload = {sink5_channel,sink5_data,
+    sink5_startofpacket,sink5_endofpacket};
+    assign sink6_payload = {sink6_channel,sink6_data,
+    sink6_startofpacket,sink6_endofpacket};
+    assign sink7_payload = {sink7_channel,sink7_data,
+    sink7_startofpacket,sink7_endofpacket};
+    assign sink8_payload = {sink8_channel,sink8_data,
+    sink8_startofpacket,sink8_endofpacket};
+    assign sink9_payload = {sink9_channel,sink9_data,
+    sink9_startofpacket,sink9_endofpacket};
+    assign sink10_payload = {sink10_channel,sink10_data,
+    sink10_startofpacket,sink10_endofpacket};
+    assign sink11_payload = {sink11_channel,sink11_data,
+    sink11_startofpacket,sink11_endofpacket};
+    assign sink12_payload = {sink12_channel,sink12_data,
+    sink12_startofpacket,sink12_endofpacket};
+    assign sink13_payload = {sink13_channel,sink13_data,
+    sink13_startofpacket,sink13_endofpacket};
+    assign sink14_payload = {sink14_channel,sink14_data,
+    sink14_startofpacket,sink14_endofpacket};
+    assign sink15_payload = {sink15_channel,sink15_data,
+    sink15_startofpacket,sink15_endofpacket};
+    assign sink16_payload = {sink16_channel,sink16_data,
+    sink16_startofpacket,sink16_endofpacket};
+    assign sink17_payload = {sink17_channel,sink17_data,
+    sink17_startofpacket,sink17_endofpacket};
+    assign sink18_payload = {sink18_channel,sink18_data,
+    sink18_startofpacket,sink18_endofpacket};
+    assign sink19_payload = {sink19_channel,sink19_data,
+    sink19_startofpacket,sink19_endofpacket};
+    assign sink20_payload = {sink20_channel,sink20_data,
+    sink20_startofpacket,sink20_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv
new file mode 100644
index 0000000..0dcf6f1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv
@@ -0,0 +1,385 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_mux_001
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_mux_001
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [121-1   : 0]  sink1_data,
+    input [21-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [121-1   : 0]  sink2_data,
+    input [21-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [121-1   : 0]  sink3_data,
+    input [21-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[69];
+      lock[1] = sink1_data[69];
+      lock[2] = sink2_data[69];
+      lock[3] = sink3_data[69];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv
new file mode 100644
index 0000000..c8a74f0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         q_sys_mm_interconnect_1_rsp_mux_002
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      69 (arbitration locking enabled)
+//   ST_DATA_W:           121
+//   ST_CHANNEL_W:        21
+// ------------------------------------------
+
+module q_sys_mm_interconnect_1_rsp_mux_002
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [121-1   : 0]  sink0_data,
+    input [21-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [121-1    : 0] src_data,
+    output [21-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 121 + 21 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 121;
+    localparam ST_CHANNEL_W     = 21;
+    localparam PKT_TRANS_LOCK   = 69;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_debug_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_debug_tx.v
new file mode 100644
index 0000000..f8b8151
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_debug_tx.v
@@ -0,0 +1,144 @@
+// q_sys_msgdma_debug_tx.v
+
+// This file was auto-generated from altera_msgdma_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_msgdma_debug_tx (
+		output wire [27:0]  mm_read_address,              //          mm_read.address
+		output wire         mm_read_read,                 //                 .read
+		output wire [3:0]   mm_read_byteenable,           //                 .byteenable
+		input  wire [31:0]  mm_read_readdata,             //                 .readdata
+		input  wire         mm_read_waitrequest,          //                 .waitrequest
+		input  wire         mm_read_readdatavalid,        //                 .readdatavalid
+		input  wire         clock_clk,                    //            clock.clk
+		input  wire         reset_n_reset_n,              //          reset_n.reset_n
+		input  wire [31:0]  csr_writedata,                //              csr.writedata
+		input  wire         csr_write,                    //                 .write
+		input  wire [3:0]   csr_byteenable,               //                 .byteenable
+		output wire [31:0]  csr_readdata,                 //                 .readdata
+		input  wire         csr_read,                     //                 .read
+		input  wire [2:0]   csr_address,                  //                 .address
+		input  wire         descriptor_slave_write,       // descriptor_slave.write
+		output wire         descriptor_slave_waitrequest, //                 .waitrequest
+		input  wire [127:0] descriptor_slave_writedata,   //                 .writedata
+		input  wire [15:0]  descriptor_slave_byteenable,  //                 .byteenable
+		output wire         csr_irq_irq,                  //          csr_irq.irq
+		output wire [31:0]  st_source_data,               //        st_source.data
+		output wire         st_source_valid,              //                 .valid
+		input  wire         st_source_ready,              //                 .ready
+		output wire         st_source_startofpacket,      //                 .startofpacket
+		output wire         st_source_endofpacket,        //                 .endofpacket
+		output wire [1:0]   st_source_empty,              //                 .empty
+		output wire         st_source_error               //                 .error
+	);
+
+	wire          dispatcher_internal_read_command_source_valid; // dispatcher_internal:src_read_master_valid -> read_mstr_internal:snk_command_valid
+	wire  [255:0] dispatcher_internal_read_command_source_data;  // dispatcher_internal:src_read_master_data -> read_mstr_internal:snk_command_data
+	wire          dispatcher_internal_read_command_source_ready; // read_mstr_internal:snk_command_ready -> dispatcher_internal:src_read_master_ready
+	wire          read_mstr_internal_response_source_valid;      // read_mstr_internal:src_response_valid -> dispatcher_internal:snk_read_master_valid
+	wire  [255:0] read_mstr_internal_response_source_data;       // read_mstr_internal:src_response_data -> dispatcher_internal:snk_read_master_data
+	wire          read_mstr_internal_response_source_ready;      // dispatcher_internal:snk_read_master_ready -> read_mstr_internal:src_response_ready
+
+	dispatcher #(
+		.MODE                        (1),
+		.RESPONSE_PORT               (2),
+		.DESCRIPTOR_INTERFACE        (0),
+		.DESCRIPTOR_FIFO_DEPTH       (8),
+		.ENHANCED_FEATURES           (0),
+		.DESCRIPTOR_WIDTH            (128),
+		.DESCRIPTOR_BYTEENABLE_WIDTH (16)
+	) dispatcher_internal (
+		.clk                     (clock_clk),                                                                                                                                                                                                                                                             //               clock.clk
+		.reset                   (~reset_n_reset_n),                                                                                                                                                                                                                                                      //         clock_reset.reset
+		.csr_writedata           (csr_writedata),                                                                                                                                                                                                                                                         //                 CSR.writedata
+		.csr_write               (csr_write),                                                                                                                                                                                                                                                             //                    .write
+		.csr_byteenable          (csr_byteenable),                                                                                                                                                                                                                                                        //                    .byteenable
+		.csr_readdata            (csr_readdata),                                                                                                                                                                                                                                                          //                    .readdata
+		.csr_read                (csr_read),                                                                                                                                                                                                                                                              //                    .read
+		.csr_address             (csr_address),                                                                                                                                                                                                                                                           //                    .address
+		.descriptor_write        (descriptor_slave_write),                                                                                                                                                                                                                                                //    Descriptor_Slave.write
+		.descriptor_waitrequest  (descriptor_slave_waitrequest),                                                                                                                                                                                                                                          //                    .waitrequest
+		.descriptor_writedata    (descriptor_slave_writedata),                                                                                                                                                                                                                                            //                    .writedata
+		.descriptor_byteenable   (descriptor_slave_byteenable),                                                                                                                                                                                                                                           //                    .byteenable
+		.src_read_master_data    (dispatcher_internal_read_command_source_data),                                                                                                                                                                                                                          // Read_Command_Source.data
+		.src_read_master_valid   (dispatcher_internal_read_command_source_valid),                                                                                                                                                                                                                         //                    .valid
+		.src_read_master_ready   (dispatcher_internal_read_command_source_ready),                                                                                                                                                                                                                         //                    .ready
+		.snk_read_master_data    (read_mstr_internal_response_source_data),                                                                                                                                                                                                                               //  Read_Response_Sink.data
+		.snk_read_master_valid   (read_mstr_internal_response_source_valid),                                                                                                                                                                                                                              //                    .valid
+		.snk_read_master_ready   (read_mstr_internal_response_source_ready),                                                                                                                                                                                                                              //                    .ready
+		.csr_irq                 (csr_irq_irq),                                                                                                                                                                                                                                                           //             csr_irq.irq
+		.src_response_data       (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_response_valid      (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_response_ready      (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_descriptor_data     (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                                                                 //         (terminated)
+		.snk_descriptor_valid    (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_descriptor_ready    (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_waitrequest (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_byteenable  (4'b0000),                                                                                                                                                                                                                                                               //         (terminated)
+		.mm_response_address     (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.mm_response_readdata    (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_read        (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.src_write_master_data   (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_valid  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_ready  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_data   (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //         (terminated)
+		.snk_write_master_valid  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_ready  ()                                                                                                                                                                                                                                                                       //         (terminated)
+	);
+
+	read_master #(
+		.DATA_WIDTH                (32),
+		.LENGTH_WIDTH              (12),
+		.FIFO_DEPTH                (32),
+		.STRIDE_ENABLE             (0),
+		.BURST_ENABLE              (0),
+		.PACKET_ENABLE             (1),
+		.ERROR_ENABLE              (1),
+		.ERROR_WIDTH               (1),
+		.CHANNEL_ENABLE            (0),
+		.CHANNEL_WIDTH             (8),
+		.BYTE_ENABLE_WIDTH         (4),
+		.BYTE_ENABLE_WIDTH_LOG2    (2),
+		.ADDRESS_WIDTH             (28),
+		.FIFO_DEPTH_LOG2           (5),
+		.SYMBOL_WIDTH              (8),
+		.NUMBER_OF_SYMBOLS         (4),
+		.NUMBER_OF_SYMBOLS_LOG2    (2),
+		.MAX_BURST_COUNT_WIDTH     (1),
+		.UNALIGNED_ACCESSES_ENABLE (0),
+		.ONLY_FULL_ACCESS_ENABLE   (0),
+		.BURST_WRAPPING_SUPPORT    (0),
+		.PROGRAMMABLE_BURST_ENABLE (0),
+		.MAX_BURST_COUNT           (1),
+		.FIFO_SPEED_OPTIMIZATION   (1),
+		.STRIDE_WIDTH              (1)
+	) read_mstr_internal (
+		.clk                  (clock_clk),                                     //            Clock.clk
+		.reset                (~reset_n_reset_n),                              //      Clock_reset.reset
+		.master_address       (mm_read_address),                               // Data_Read_Master.address
+		.master_read          (mm_read_read),                                  //                 .read
+		.master_byteenable    (mm_read_byteenable),                            //                 .byteenable
+		.master_readdata      (mm_read_readdata),                              //                 .readdata
+		.master_waitrequest   (mm_read_waitrequest),                           //                 .waitrequest
+		.master_readdatavalid (mm_read_readdatavalid),                         //                 .readdatavalid
+		.src_data             (st_source_data),                                //      Data_Source.data
+		.src_valid            (st_source_valid),                               //                 .valid
+		.src_ready            (st_source_ready),                               //                 .ready
+		.src_sop              (st_source_startofpacket),                       //                 .startofpacket
+		.src_eop              (st_source_endofpacket),                         //                 .endofpacket
+		.src_empty            (st_source_empty),                               //                 .empty
+		.src_error            (st_source_error),                               //                 .error
+		.snk_command_data     (dispatcher_internal_read_command_source_data),  //     Command_Sink.data
+		.snk_command_valid    (dispatcher_internal_read_command_source_valid), //                 .valid
+		.snk_command_ready    (dispatcher_internal_read_command_source_ready), //                 .ready
+		.src_response_data    (read_mstr_internal_response_source_data),       //  Response_Source.data
+		.src_response_valid   (read_mstr_internal_response_source_valid),      //                 .valid
+		.src_response_ready   (read_mstr_internal_response_source_ready),      //                 .ready
+		.master_burstcount    (),                                              //      (terminated)
+		.src_channel          ()                                               //      (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_rx.v
new file mode 100644
index 0000000..94a7251
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_rx.v
@@ -0,0 +1,200 @@
+// q_sys_msgdma_rx.v
+
+// This file was auto-generated from altera_msgdma_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_msgdma_rx (
+		output wire [27:0] mm_write_address,                           //                mm_write.address
+		output wire        mm_write_write,                             //                        .write
+		output wire [3:0]  mm_write_byteenable,                        //                        .byteenable
+		output wire [31:0] mm_write_writedata,                         //                        .writedata
+		input  wire        mm_write_waitrequest,                       //                        .waitrequest
+		output wire [28:0] descriptor_read_master_address,             //  descriptor_read_master.address
+		output wire        descriptor_read_master_read,                //                        .read
+		input  wire [31:0] descriptor_read_master_readdata,            //                        .readdata
+		input  wire        descriptor_read_master_waitrequest,         //                        .waitrequest
+		input  wire        descriptor_read_master_readdatavalid,       //                        .readdatavalid
+		output wire [28:0] descriptor_write_master_address,            // descriptor_write_master.address
+		output wire        descriptor_write_master_write,              //                        .write
+		output wire [3:0]  descriptor_write_master_byteenable,         //                        .byteenable
+		output wire [31:0] descriptor_write_master_writedata,          //                        .writedata
+		input  wire        descriptor_write_master_waitrequest,        //                        .waitrequest
+		input  wire [1:0]  descriptor_write_master_response,           //                        .response
+		input  wire        descriptor_write_master_writeresponsevalid, //                        .writeresponsevalid
+		input  wire        clock_clk,                                  //                   clock.clk
+		input  wire        reset_n_reset_n,                            //                 reset_n.reset_n
+		input  wire [31:0] csr_writedata,                              //                     csr.writedata
+		input  wire        csr_write,                                  //                        .write
+		input  wire [3:0]  csr_byteenable,                             //                        .byteenable
+		output wire [31:0] csr_readdata,                               //                        .readdata
+		input  wire        csr_read,                                   //                        .read
+		input  wire [2:0]  csr_address,                                //                        .address
+		input  wire [2:0]  prefetcher_csr_address,                     //          prefetcher_csr.address
+		input  wire        prefetcher_csr_read,                        //                        .read
+		input  wire        prefetcher_csr_write,                       //                        .write
+		input  wire [31:0] prefetcher_csr_writedata,                   //                        .writedata
+		output wire [31:0] prefetcher_csr_readdata,                    //                        .readdata
+		output wire        csr_irq_irq,                                //                 csr_irq.irq
+		input  wire [31:0] st_sink_data,                               //                 st_sink.data
+		input  wire        st_sink_valid,                              //                        .valid
+		output wire        st_sink_ready,                              //                        .ready
+		input  wire        st_sink_startofpacket,                      //                        .startofpacket
+		input  wire        st_sink_endofpacket,                        //                        .endofpacket
+		input  wire [1:0]  st_sink_empty,                              //                        .empty
+		input  wire [5:0]  st_sink_error                               //                        .error
+	);
+
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_valid; // prefetcher_internal:st_src_descr_valid -> dispatcher_internal:snk_descriptor_valid
+	wire  [127:0] prefetcher_internal_descriptor_write_dispatcher_source_data;  // prefetcher_internal:st_src_descr_data -> dispatcher_internal:snk_descriptor_data
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_ready; // dispatcher_internal:snk_descriptor_ready -> prefetcher_internal:st_src_descr_ready
+	wire          dispatcher_internal_response_source_valid;                    // dispatcher_internal:src_response_valid -> prefetcher_internal:st_snk_valid
+	wire  [255:0] dispatcher_internal_response_source_data;                     // dispatcher_internal:src_response_data -> prefetcher_internal:st_snk_data
+	wire          dispatcher_internal_response_source_ready;                    // prefetcher_internal:st_snk_ready -> dispatcher_internal:src_response_ready
+	wire          dispatcher_internal_write_command_source_valid;               // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
+	wire  [255:0] dispatcher_internal_write_command_source_data;                // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
+	wire          dispatcher_internal_write_command_source_ready;               // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
+	wire          write_mstr_internal_response_source_valid;                    // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
+	wire  [255:0] write_mstr_internal_response_source_data;                     // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
+	wire          write_mstr_internal_response_source_ready;                    // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
+
+	dispatcher #(
+		.MODE                        (2),
+		.RESPONSE_PORT               (1),
+		.DESCRIPTOR_INTERFACE        (1),
+		.DESCRIPTOR_FIFO_DEPTH       (8),
+		.ENHANCED_FEATURES           (0),
+		.DESCRIPTOR_WIDTH            (128),
+		.DESCRIPTOR_BYTEENABLE_WIDTH (16)
+	) dispatcher_internal (
+		.clk                     (clock_clk),                                                                                                                                                                                                                                                             //                clock.clk
+		.reset                   (~reset_n_reset_n),                                                                                                                                                                                                                                                      //          clock_reset.reset
+		.csr_writedata           (csr_writedata),                                                                                                                                                                                                                                                         //                  CSR.writedata
+		.csr_write               (csr_write),                                                                                                                                                                                                                                                             //                     .write
+		.csr_byteenable          (csr_byteenable),                                                                                                                                                                                                                                                        //                     .byteenable
+		.csr_readdata            (csr_readdata),                                                                                                                                                                                                                                                          //                     .readdata
+		.csr_read                (csr_read),                                                                                                                                                                                                                                                              //                     .read
+		.csr_address             (csr_address),                                                                                                                                                                                                                                                           //                     .address
+		.src_response_data       (dispatcher_internal_response_source_data),                                                                                                                                                                                                                              //      Response_Source.data
+		.src_response_valid      (dispatcher_internal_response_source_valid),                                                                                                                                                                                                                             //                     .valid
+		.src_response_ready      (dispatcher_internal_response_source_ready),                                                                                                                                                                                                                             //                     .ready
+		.snk_descriptor_data     (prefetcher_internal_descriptor_write_dispatcher_source_data),                                                                                                                                                                                                           //      Descriptor_Sink.data
+		.snk_descriptor_valid    (prefetcher_internal_descriptor_write_dispatcher_source_valid),                                                                                                                                                                                                          //                     .valid
+		.snk_descriptor_ready    (prefetcher_internal_descriptor_write_dispatcher_source_ready),                                                                                                                                                                                                          //                     .ready
+		.src_write_master_data   (dispatcher_internal_write_command_source_data),                                                                                                                                                                                                                         // Write_Command_Source.data
+		.src_write_master_valid  (dispatcher_internal_write_command_source_valid),                                                                                                                                                                                                                        //                     .valid
+		.src_write_master_ready  (dispatcher_internal_write_command_source_ready),                                                                                                                                                                                                                        //                     .ready
+		.snk_write_master_data   (write_mstr_internal_response_source_data),                                                                                                                                                                                                                              //  Write_Response_Sink.data
+		.snk_write_master_valid  (write_mstr_internal_response_source_valid),                                                                                                                                                                                                                             //                     .valid
+		.snk_write_master_ready  (write_mstr_internal_response_source_ready),                                                                                                                                                                                                                             //                     .ready
+		.descriptor_write        (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.descriptor_waitrequest  (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.descriptor_writedata    (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                                                                 //          (terminated)
+		.descriptor_byteenable   (16'b0000000000000000),                                                                                                                                                                                                                                                  //          (terminated)
+		.mm_response_waitrequest (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.mm_response_byteenable  (4'b0000),                                                                                                                                                                                                                                                               //          (terminated)
+		.mm_response_address     (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.mm_response_readdata    (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.mm_response_read        (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.src_read_master_data    (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.src_read_master_valid   (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.src_read_master_ready   (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.snk_read_master_data    (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //          (terminated)
+		.snk_read_master_valid   (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.snk_read_master_ready   (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.csr_irq                 ()                                                                                                                                                                                                                                                                       //          (terminated)
+	);
+
+	altera_msgdma_prefetcher #(
+		.ENHANCED_FEATURES          (0),
+		.ENABLE_READ_BURST          (0),
+		.MAX_READ_BURST_COUNT       (1),
+		.MAX_READ_BURST_COUNT_WIDTH (1),
+		.DATA_WIDTH                 (32),
+		.DATA_BYTEENABLE_WIDTH      (4),
+		.DESCRIPTOR_WIDTH           (128),
+		.ADDRESS_WIDTH              (29),
+		.RESPONSE_FIFO_DEPTH        (16),
+		.RESPONSE_FIFO_DEPTH_LOG2   (4)
+	) prefetcher_internal (
+		.clk                         (clock_clk),                                                    //                              Clock.clk
+		.reset                       (~reset_n_reset_n),                                             //                        Clock_reset.reset
+		.mm_read_address             (descriptor_read_master_address),                               //             Descriptor_Read_Master.address
+		.mm_read_read                (descriptor_read_master_read),                                  //                                   .read
+		.mm_read_readdata            (descriptor_read_master_readdata),                              //                                   .readdata
+		.mm_read_waitrequest         (descriptor_read_master_waitrequest),                           //                                   .waitrequest
+		.mm_read_readdatavalid       (descriptor_read_master_readdatavalid),                         //                                   .readdatavalid
+		.mm_write_address            (descriptor_write_master_address),                              //            Descriptor_Write_Master.address
+		.mm_write_write              (descriptor_write_master_write),                                //                                   .write
+		.mm_write_byteenable         (descriptor_write_master_byteenable),                           //                                   .byteenable
+		.mm_write_writedata          (descriptor_write_master_writedata),                            //                                   .writedata
+		.mm_write_waitrequest        (descriptor_write_master_waitrequest),                          //                                   .waitrequest
+		.mm_write_response           (descriptor_write_master_response),                             //                                   .response
+		.mm_write_writeresponsevalid (descriptor_write_master_writeresponsevalid),                   //                                   .writeresponsevalid
+		.st_src_descr_data           (prefetcher_internal_descriptor_write_dispatcher_source_data),  // Descriptor_Write_Dispatcher_Source.data
+		.st_src_descr_valid          (prefetcher_internal_descriptor_write_dispatcher_source_valid), //                                   .valid
+		.st_src_descr_ready          (prefetcher_internal_descriptor_write_dispatcher_source_ready), //                                   .ready
+		.st_snk_data                 (dispatcher_internal_response_source_data),                     //                      Response_Sink.data
+		.st_snk_valid                (dispatcher_internal_response_source_valid),                    //                                   .valid
+		.st_snk_ready                (dispatcher_internal_response_source_ready),                    //                                   .ready
+		.mm_csr_address              (prefetcher_csr_address),                                       //                                Csr.address
+		.mm_csr_read                 (prefetcher_csr_read),                                          //                                   .read
+		.mm_csr_write                (prefetcher_csr_write),                                         //                                   .write
+		.mm_csr_writedata            (prefetcher_csr_writedata),                                     //                                   .writedata
+		.mm_csr_readdata             (prefetcher_csr_readdata),                                      //                                   .readdata
+		.csr_irq                     (csr_irq_irq),                                                  //                            Csr_Irq.irq
+		.mm_read_burstcount          ()                                                              //                        (terminated)
+	);
+
+	write_master #(
+		.DATA_WIDTH                     (32),
+		.LENGTH_WIDTH                   (12),
+		.FIFO_DEPTH                     (32),
+		.STRIDE_ENABLE                  (0),
+		.BURST_ENABLE                   (0),
+		.PACKET_ENABLE                  (1),
+		.ERROR_ENABLE                   (1),
+		.ERROR_WIDTH                    (6),
+		.BYTE_ENABLE_WIDTH              (4),
+		.BYTE_ENABLE_WIDTH_LOG2         (2),
+		.ADDRESS_WIDTH                  (28),
+		.FIFO_DEPTH_LOG2                (5),
+		.SYMBOL_WIDTH                   (8),
+		.NUMBER_OF_SYMBOLS              (4),
+		.NUMBER_OF_SYMBOLS_LOG2         (2),
+		.MAX_BURST_COUNT_WIDTH          (1),
+		.UNALIGNED_ACCESSES_ENABLE      (0),
+		.ONLY_FULL_ACCESS_ENABLE        (0),
+		.BURST_WRAPPING_SUPPORT         (0),
+		.PROGRAMMABLE_BURST_ENABLE      (0),
+		.MAX_BURST_COUNT                (1),
+		.FIFO_SPEED_OPTIMIZATION        (1),
+		.STRIDE_WIDTH                   (1),
+		.ACTUAL_BYTES_TRANSFERRED_WIDTH (13)
+	) write_mstr_internal (
+		.clk                (clock_clk),                                      //             Clock.clk
+		.reset              (~reset_n_reset_n),                               //       Clock_reset.reset
+		.master_address     (mm_write_address),                               // Data_Write_Master.address
+		.master_write       (mm_write_write),                                 //                  .write
+		.master_byteenable  (mm_write_byteenable),                            //                  .byteenable
+		.master_writedata   (mm_write_writedata),                             //                  .writedata
+		.master_waitrequest (mm_write_waitrequest),                           //                  .waitrequest
+		.snk_data           (st_sink_data),                                   //         Data_Sink.data
+		.snk_valid          (st_sink_valid),                                  //                  .valid
+		.snk_ready          (st_sink_ready),                                  //                  .ready
+		.snk_sop            (st_sink_startofpacket),                          //                  .startofpacket
+		.snk_eop            (st_sink_endofpacket),                            //                  .endofpacket
+		.snk_empty          (st_sink_empty),                                  //                  .empty
+		.snk_error          (st_sink_error),                                  //                  .error
+		.snk_command_data   (dispatcher_internal_write_command_source_data),  //      Command_Sink.data
+		.snk_command_valid  (dispatcher_internal_write_command_source_valid), //                  .valid
+		.snk_command_ready  (dispatcher_internal_write_command_source_ready), //                  .ready
+		.src_response_data  (write_mstr_internal_response_source_data),       //   Response_Source.data
+		.src_response_valid (write_mstr_internal_response_source_valid),      //                  .valid
+		.src_response_ready (write_mstr_internal_response_source_ready),      //                  .ready
+		.master_burstcount  ()                                                //       (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_tx.v
new file mode 100644
index 0000000..8a6c8c1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_msgdma_tx.v
@@ -0,0 +1,204 @@
+// q_sys_msgdma_tx.v
+
+// This file was auto-generated from altera_msgdma_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module q_sys_msgdma_tx (
+		output wire [27:0] mm_read_address,                            //                 mm_read.address
+		output wire        mm_read_read,                               //                        .read
+		output wire [3:0]  mm_read_byteenable,                         //                        .byteenable
+		input  wire [31:0] mm_read_readdata,                           //                        .readdata
+		input  wire        mm_read_waitrequest,                        //                        .waitrequest
+		input  wire        mm_read_readdatavalid,                      //                        .readdatavalid
+		output wire [28:0] descriptor_read_master_address,             //  descriptor_read_master.address
+		output wire        descriptor_read_master_read,                //                        .read
+		input  wire [31:0] descriptor_read_master_readdata,            //                        .readdata
+		input  wire        descriptor_read_master_waitrequest,         //                        .waitrequest
+		input  wire        descriptor_read_master_readdatavalid,       //                        .readdatavalid
+		output wire [28:0] descriptor_write_master_address,            // descriptor_write_master.address
+		output wire        descriptor_write_master_write,              //                        .write
+		output wire [3:0]  descriptor_write_master_byteenable,         //                        .byteenable
+		output wire [31:0] descriptor_write_master_writedata,          //                        .writedata
+		input  wire        descriptor_write_master_waitrequest,        //                        .waitrequest
+		input  wire [1:0]  descriptor_write_master_response,           //                        .response
+		input  wire        descriptor_write_master_writeresponsevalid, //                        .writeresponsevalid
+		input  wire        clock_clk,                                  //                   clock.clk
+		input  wire        reset_n_reset_n,                            //                 reset_n.reset_n
+		input  wire [31:0] csr_writedata,                              //                     csr.writedata
+		input  wire        csr_write,                                  //                        .write
+		input  wire [3:0]  csr_byteenable,                             //                        .byteenable
+		output wire [31:0] csr_readdata,                               //                        .readdata
+		input  wire        csr_read,                                   //                        .read
+		input  wire [2:0]  csr_address,                                //                        .address
+		input  wire [2:0]  prefetcher_csr_address,                     //          prefetcher_csr.address
+		input  wire        prefetcher_csr_read,                        //                        .read
+		input  wire        prefetcher_csr_write,                       //                        .write
+		input  wire [31:0] prefetcher_csr_writedata,                   //                        .writedata
+		output wire [31:0] prefetcher_csr_readdata,                    //                        .readdata
+		output wire        csr_irq_irq,                                //                 csr_irq.irq
+		output wire [31:0] st_source_data,                             //               st_source.data
+		output wire        st_source_valid,                            //                        .valid
+		input  wire        st_source_ready,                            //                        .ready
+		output wire        st_source_startofpacket,                    //                        .startofpacket
+		output wire        st_source_endofpacket,                      //                        .endofpacket
+		output wire [1:0]  st_source_empty,                            //                        .empty
+		output wire        st_source_error                             //                        .error
+	);
+
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_valid; // prefetcher_internal:st_src_descr_valid -> dispatcher_internal:snk_descriptor_valid
+	wire  [127:0] prefetcher_internal_descriptor_write_dispatcher_source_data;  // prefetcher_internal:st_src_descr_data -> dispatcher_internal:snk_descriptor_data
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_ready; // dispatcher_internal:snk_descriptor_ready -> prefetcher_internal:st_src_descr_ready
+	wire          dispatcher_internal_response_source_valid;                    // dispatcher_internal:src_response_valid -> prefetcher_internal:st_snk_valid
+	wire  [255:0] dispatcher_internal_response_source_data;                     // dispatcher_internal:src_response_data -> prefetcher_internal:st_snk_data
+	wire          dispatcher_internal_response_source_ready;                    // prefetcher_internal:st_snk_ready -> dispatcher_internal:src_response_ready
+	wire          dispatcher_internal_read_command_source_valid;                // dispatcher_internal:src_read_master_valid -> read_mstr_internal:snk_command_valid
+	wire  [255:0] dispatcher_internal_read_command_source_data;                 // dispatcher_internal:src_read_master_data -> read_mstr_internal:snk_command_data
+	wire          dispatcher_internal_read_command_source_ready;                // read_mstr_internal:snk_command_ready -> dispatcher_internal:src_read_master_ready
+	wire          read_mstr_internal_response_source_valid;                     // read_mstr_internal:src_response_valid -> dispatcher_internal:snk_read_master_valid
+	wire  [255:0] read_mstr_internal_response_source_data;                      // read_mstr_internal:src_response_data -> dispatcher_internal:snk_read_master_data
+	wire          read_mstr_internal_response_source_ready;                     // dispatcher_internal:snk_read_master_ready -> read_mstr_internal:src_response_ready
+
+	dispatcher #(
+		.MODE                        (1),
+		.RESPONSE_PORT               (1),
+		.DESCRIPTOR_INTERFACE        (1),
+		.DESCRIPTOR_FIFO_DEPTH       (8),
+		.ENHANCED_FEATURES           (0),
+		.DESCRIPTOR_WIDTH            (128),
+		.DESCRIPTOR_BYTEENABLE_WIDTH (16)
+	) dispatcher_internal (
+		.clk                     (clock_clk),                                                                                                                                                                                                                                                             //               clock.clk
+		.reset                   (~reset_n_reset_n),                                                                                                                                                                                                                                                      //         clock_reset.reset
+		.csr_writedata           (csr_writedata),                                                                                                                                                                                                                                                         //                 CSR.writedata
+		.csr_write               (csr_write),                                                                                                                                                                                                                                                             //                    .write
+		.csr_byteenable          (csr_byteenable),                                                                                                                                                                                                                                                        //                    .byteenable
+		.csr_readdata            (csr_readdata),                                                                                                                                                                                                                                                          //                    .readdata
+		.csr_read                (csr_read),                                                                                                                                                                                                                                                              //                    .read
+		.csr_address             (csr_address),                                                                                                                                                                                                                                                           //                    .address
+		.src_response_data       (dispatcher_internal_response_source_data),                                                                                                                                                                                                                              //     Response_Source.data
+		.src_response_valid      (dispatcher_internal_response_source_valid),                                                                                                                                                                                                                             //                    .valid
+		.src_response_ready      (dispatcher_internal_response_source_ready),                                                                                                                                                                                                                             //                    .ready
+		.snk_descriptor_data     (prefetcher_internal_descriptor_write_dispatcher_source_data),                                                                                                                                                                                                           //     Descriptor_Sink.data
+		.snk_descriptor_valid    (prefetcher_internal_descriptor_write_dispatcher_source_valid),                                                                                                                                                                                                          //                    .valid
+		.snk_descriptor_ready    (prefetcher_internal_descriptor_write_dispatcher_source_ready),                                                                                                                                                                                                          //                    .ready
+		.src_read_master_data    (dispatcher_internal_read_command_source_data),                                                                                                                                                                                                                          // Read_Command_Source.data
+		.src_read_master_valid   (dispatcher_internal_read_command_source_valid),                                                                                                                                                                                                                         //                    .valid
+		.src_read_master_ready   (dispatcher_internal_read_command_source_ready),                                                                                                                                                                                                                         //                    .ready
+		.snk_read_master_data    (read_mstr_internal_response_source_data),                                                                                                                                                                                                                               //  Read_Response_Sink.data
+		.snk_read_master_valid   (read_mstr_internal_response_source_valid),                                                                                                                                                                                                                              //                    .valid
+		.snk_read_master_ready   (read_mstr_internal_response_source_ready),                                                                                                                                                                                                                              //                    .ready
+		.descriptor_write        (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.descriptor_waitrequest  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.descriptor_writedata    (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                                                                 //         (terminated)
+		.descriptor_byteenable   (16'b0000000000000000),                                                                                                                                                                                                                                                  //         (terminated)
+		.mm_response_waitrequest (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_byteenable  (4'b0000),                                                                                                                                                                                                                                                               //         (terminated)
+		.mm_response_address     (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.mm_response_readdata    (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_read        (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.src_write_master_data   (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_valid  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_ready  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_data   (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //         (terminated)
+		.snk_write_master_valid  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_ready  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.csr_irq                 ()                                                                                                                                                                                                                                                                       //         (terminated)
+	);
+
+	altera_msgdma_prefetcher #(
+		.ENHANCED_FEATURES          (0),
+		.ENABLE_READ_BURST          (0),
+		.MAX_READ_BURST_COUNT       (1),
+		.MAX_READ_BURST_COUNT_WIDTH (1),
+		.DATA_WIDTH                 (32),
+		.DATA_BYTEENABLE_WIDTH      (4),
+		.DESCRIPTOR_WIDTH           (128),
+		.ADDRESS_WIDTH              (29),
+		.RESPONSE_FIFO_DEPTH        (16),
+		.RESPONSE_FIFO_DEPTH_LOG2   (4)
+	) prefetcher_internal (
+		.clk                         (clock_clk),                                                    //                              Clock.clk
+		.reset                       (~reset_n_reset_n),                                             //                        Clock_reset.reset
+		.mm_read_address             (descriptor_read_master_address),                               //             Descriptor_Read_Master.address
+		.mm_read_read                (descriptor_read_master_read),                                  //                                   .read
+		.mm_read_readdata            (descriptor_read_master_readdata),                              //                                   .readdata
+		.mm_read_waitrequest         (descriptor_read_master_waitrequest),                           //                                   .waitrequest
+		.mm_read_readdatavalid       (descriptor_read_master_readdatavalid),                         //                                   .readdatavalid
+		.mm_write_address            (descriptor_write_master_address),                              //            Descriptor_Write_Master.address
+		.mm_write_write              (descriptor_write_master_write),                                //                                   .write
+		.mm_write_byteenable         (descriptor_write_master_byteenable),                           //                                   .byteenable
+		.mm_write_writedata          (descriptor_write_master_writedata),                            //                                   .writedata
+		.mm_write_waitrequest        (descriptor_write_master_waitrequest),                          //                                   .waitrequest
+		.mm_write_response           (descriptor_write_master_response),                             //                                   .response
+		.mm_write_writeresponsevalid (descriptor_write_master_writeresponsevalid),                   //                                   .writeresponsevalid
+		.st_src_descr_data           (prefetcher_internal_descriptor_write_dispatcher_source_data),  // Descriptor_Write_Dispatcher_Source.data
+		.st_src_descr_valid          (prefetcher_internal_descriptor_write_dispatcher_source_valid), //                                   .valid
+		.st_src_descr_ready          (prefetcher_internal_descriptor_write_dispatcher_source_ready), //                                   .ready
+		.st_snk_data                 (dispatcher_internal_response_source_data),                     //                      Response_Sink.data
+		.st_snk_valid                (dispatcher_internal_response_source_valid),                    //                                   .valid
+		.st_snk_ready                (dispatcher_internal_response_source_ready),                    //                                   .ready
+		.mm_csr_address              (prefetcher_csr_address),                                       //                                Csr.address
+		.mm_csr_read                 (prefetcher_csr_read),                                          //                                   .read
+		.mm_csr_write                (prefetcher_csr_write),                                         //                                   .write
+		.mm_csr_writedata            (prefetcher_csr_writedata),                                     //                                   .writedata
+		.mm_csr_readdata             (prefetcher_csr_readdata),                                      //                                   .readdata
+		.csr_irq                     (csr_irq_irq),                                                  //                            Csr_Irq.irq
+		.mm_read_burstcount          ()                                                              //                        (terminated)
+	);
+
+	read_master #(
+		.DATA_WIDTH                (32),
+		.LENGTH_WIDTH              (12),
+		.FIFO_DEPTH                (32),
+		.STRIDE_ENABLE             (0),
+		.BURST_ENABLE              (0),
+		.PACKET_ENABLE             (1),
+		.ERROR_ENABLE              (1),
+		.ERROR_WIDTH               (1),
+		.CHANNEL_ENABLE            (0),
+		.CHANNEL_WIDTH             (8),
+		.BYTE_ENABLE_WIDTH         (4),
+		.BYTE_ENABLE_WIDTH_LOG2    (2),
+		.ADDRESS_WIDTH             (28),
+		.FIFO_DEPTH_LOG2           (5),
+		.SYMBOL_WIDTH              (8),
+		.NUMBER_OF_SYMBOLS         (4),
+		.NUMBER_OF_SYMBOLS_LOG2    (2),
+		.MAX_BURST_COUNT_WIDTH     (1),
+		.UNALIGNED_ACCESSES_ENABLE (0),
+		.ONLY_FULL_ACCESS_ENABLE   (0),
+		.BURST_WRAPPING_SUPPORT    (0),
+		.PROGRAMMABLE_BURST_ENABLE (0),
+		.MAX_BURST_COUNT           (1),
+		.FIFO_SPEED_OPTIMIZATION   (1),
+		.STRIDE_WIDTH              (1)
+	) read_mstr_internal (
+		.clk                  (clock_clk),                                     //            Clock.clk
+		.reset                (~reset_n_reset_n),                              //      Clock_reset.reset
+		.master_address       (mm_read_address),                               // Data_Read_Master.address
+		.master_read          (mm_read_read),                                  //                 .read
+		.master_byteenable    (mm_read_byteenable),                            //                 .byteenable
+		.master_readdata      (mm_read_readdata),                              //                 .readdata
+		.master_waitrequest   (mm_read_waitrequest),                           //                 .waitrequest
+		.master_readdatavalid (mm_read_readdatavalid),                         //                 .readdatavalid
+		.src_data             (st_source_data),                                //      Data_Source.data
+		.src_valid            (st_source_valid),                               //                 .valid
+		.src_ready            (st_source_ready),                               //                 .ready
+		.src_sop              (st_source_startofpacket),                       //                 .startofpacket
+		.src_eop              (st_source_endofpacket),                         //                 .endofpacket
+		.src_empty            (st_source_empty),                               //                 .empty
+		.src_error            (st_source_error),                               //                 .error
+		.snk_command_data     (dispatcher_internal_read_command_source_data),  //     Command_Sink.data
+		.snk_command_valid    (dispatcher_internal_read_command_source_valid), //                 .valid
+		.snk_command_ready    (dispatcher_internal_read_command_source_ready), //                 .ready
+		.src_response_data    (read_mstr_internal_response_source_data),       //  Response_Source.data
+		.src_response_valid   (read_mstr_internal_response_source_valid),      //                 .valid
+		.src_response_ready   (read_mstr_internal_response_source_ready),      //                 .ready
+		.master_burstcount    (),                                              //      (terminated)
+		.src_channel          ()                                               //      (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_onchip_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_onchip_ram.v
new file mode 100644
index 0000000..563f042
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_onchip_ram.v
@@ -0,0 +1,86 @@
+//Legal Notice: (C)2019 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_onchip_ram (
+                          // inputs:
+                           address,
+                           byteenable,
+                           chipselect,
+                           clk,
+                           clken,
+                           freeze,
+                           reset,
+                           reset_req,
+                           write,
+                           writedata,
+
+                          // outputs:
+                           readdata
+                        )
+;
+
+  output  [ 31: 0] readdata;
+  input   [ 13: 0] address;
+  input   [  3: 0] byteenable;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+wire             clocken0;
+wire    [ 31: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 16384,
+           the_altsyncram.numwords_a = 16384,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 14;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_output_pio.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_output_pio.v
new file mode 100644
index 0000000..dfb45e6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_output_pio.v
@@ -0,0 +1,70 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_output_pio (
+                          // inputs:
+                           address,
+                           chipselect,
+                           clk,
+                           reset_n,
+                           write_n,
+                           writedata,
+
+                          // outputs:
+                           out_port,
+                           readdata
+                        )
+;
+
+  output  [  7: 0] out_port;
+  output  [ 31: 0] readdata;
+  input   [  2: 0] address;
+  input            chipselect;
+  input            clk;
+  input            reset_n;
+  input            write_n;
+  input   [ 31: 0] writedata;
+
+
+wire             clk_en;
+reg     [  7: 0] data_out;
+wire    [  7: 0] out_port;
+wire    [  7: 0] read_mux_out;
+wire    [ 31: 0] readdata;
+wire             wr_strobe;
+  assign clk_en = 1;
+  //s1, which is an e_avalon_slave
+  assign read_mux_out = {8 {(address == 0)}} & data_out;
+  assign wr_strobe = chipselect && ~write_n;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          data_out <= 0;
+      else if (clk_en)
+          if (wr_strobe)
+              data_out <= (address == 5)? data_out & ~writedata[7 : 0]: (address == 4)? data_out | writedata[7 : 0]: (address == 0)? writedata[7 : 0]: data_out;
+    end
+
+
+  assign readdata = {32'b0 | read_mux_out};
+  assign out_port = data_out;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_rx.v
new file mode 100644
index 0000000..85b3409
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_rx.v
@@ -0,0 +1,2275 @@
+//Legal Notice: (C)2019 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module control_status_slave_which_resides_within_q_sys_sgdma_rx (
+                                                                  // inputs:
+                                                                   atlantic_error,
+                                                                   chain_run,
+                                                                   clk,
+                                                                   command_fifo_empty,
+                                                                   csr_address,
+                                                                   csr_chipselect,
+                                                                   csr_read,
+                                                                   csr_write,
+                                                                   csr_writedata,
+                                                                   desc_address_fifo_empty,
+                                                                   descriptor_read_address,
+                                                                   descriptor_read_read,
+                                                                   descriptor_write_busy,
+                                                                   descriptor_write_write,
+                                                                   owned_by_hw,
+                                                                   reset_n,
+                                                                   status_token_fifo_empty,
+                                                                   status_token_fifo_rdreq,
+                                                                   t_eop,
+                                                                   write_go,
+
+                                                                  // outputs:
+                                                                   csr_irq,
+                                                                   csr_readdata,
+                                                                   descriptor_pointer_lower_reg_out,
+                                                                   descriptor_pointer_upper_reg_out,
+                                                                   park,
+                                                                   pollen_clear_run,
+                                                                   run,
+                                                                   sw_reset
+                                                                )
+;
+
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] descriptor_pointer_lower_reg_out;
+  output  [ 31: 0] descriptor_pointer_upper_reg_out;
+  output           park;
+  output           pollen_clear_run;
+  output           run;
+  output           sw_reset;
+  input            atlantic_error;
+  input            chain_run;
+  input            clk;
+  input            command_fifo_empty;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input            desc_address_fifo_empty;
+  input   [ 31: 0] descriptor_read_address;
+  input            descriptor_read_read;
+  input            descriptor_write_busy;
+  input            descriptor_write_write;
+  input            owned_by_hw;
+  input            reset_n;
+  input            status_token_fifo_empty;
+  input            status_token_fifo_rdreq;
+  input            t_eop;
+  input            write_go;
+
+
+reg              busy;
+reg              can_have_new_chain_complete;
+reg              chain_completed;
+reg              chain_completed_int;
+wire             chain_completed_int_rise;
+wire             clear_chain_completed;
+wire             clear_descriptor_completed;
+wire             clear_eop_encountered;
+wire             clear_error;
+reg              clear_interrupt;
+wire             clear_run;
+reg     [ 31: 0] control_reg;
+wire             control_reg_en;
+wire             csr_control;
+reg              csr_irq;
+reg     [ 31: 0] csr_readdata;
+wire             csr_status;
+reg              delayed_chain_completed_int;
+reg              delayed_csr_write;
+reg     [  7: 0] delayed_descriptor_counter;
+reg              delayed_descriptor_write_write;
+reg              delayed_eop_encountered;
+wire    [  7: 0] delayed_max_desc_processed;
+reg              delayed_run;
+reg              descriptor_completed;
+reg     [  7: 0] descriptor_counter;
+wire    [ 31: 0] descriptor_pointer_data;
+reg     [ 31: 0] descriptor_pointer_lower_reg;
+wire             descriptor_pointer_lower_reg_en;
+wire    [ 31: 0] descriptor_pointer_lower_reg_out;
+reg     [ 31: 0] descriptor_pointer_upper_reg;
+wire             descriptor_pointer_upper_reg_en;
+wire    [ 31: 0] descriptor_pointer_upper_reg_out;
+reg              descriptor_read_read_r;
+wire             descriptor_read_read_rising;
+wire             descriptor_write_write_fall;
+reg              do_restart;
+reg              do_restart_compare;
+reg              eop_encountered;
+wire             eop_encountered_rise;
+reg              error;
+wire    [  3: 0] hw_version;
+wire             ie_chain_completed;
+wire             ie_descriptor_completed;
+wire             ie_eop_encountered;
+wire             ie_error;
+wire             ie_global;
+wire             ie_max_desc_processed;
+wire    [  7: 0] max_desc_processed;
+wire             park;
+wire             poll_en;
+wire             pollen_clear_run;
+wire             run;
+wire    [ 31: 0] status_reg;
+wire             stop_dma_error;
+wire             sw_reset;
+reg     [ 15: 0] timeout_counter;
+wire    [ 10: 0] timeout_reg;
+wire             version_reg;
+  //csr, which is an e_avalon_slave
+  //Control Status Register (Readdata)
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          csr_readdata <= 0;
+      else if (csr_read)
+          case (csr_address) // synthesis parallel_case
+          
+              {4'b0000}: begin
+                  csr_readdata <= status_reg;
+              end // {4'b0000} 
+          
+              {4'b0001}: begin
+                  csr_readdata <= version_reg;
+              end // {4'b0001} 
+          
+              {4'b0100}: begin
+                  csr_readdata <= control_reg;
+              end // {4'b0100} 
+          
+              {4'b1000}: begin
+                  csr_readdata <= descriptor_pointer_lower_reg;
+              end // {4'b1000} 
+          
+              {4'b1100}: begin
+                  csr_readdata <= descriptor_pointer_upper_reg;
+              end // {4'b1100} 
+          
+              default: begin
+                  csr_readdata <= 32'b0;
+              end // default
+          
+          endcase // csr_address
+    end
+
+
+  //register outs
+  assign descriptor_pointer_upper_reg_out = descriptor_pointer_upper_reg;
+  assign descriptor_pointer_lower_reg_out = descriptor_pointer_lower_reg;
+  //control register bits
+  assign ie_error = control_reg[0];
+  assign ie_eop_encountered = control_reg[1];
+  assign ie_descriptor_completed = control_reg[2];
+  assign ie_chain_completed = control_reg[3];
+  assign ie_global = control_reg[4];
+  assign run = control_reg[5] && (!(stop_dma_error && error) && ((!chain_completed_int ) ||( do_restart && poll_en && chain_completed_int)));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_run <= 0;
+      else 
+        delayed_run <= run;
+    end
+
+
+  assign stop_dma_error = control_reg[6];
+  assign ie_max_desc_processed = control_reg[7];
+  assign max_desc_processed = control_reg[15 : 8];
+  assign sw_reset = control_reg[16];
+  assign park = control_reg[17];
+  assign poll_en = control_reg[18];
+  assign timeout_reg = control_reg[30 : 20];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          timeout_counter <= 0;
+      else if ((control_reg[5] && !busy && poll_en )|| do_restart)
+          timeout_counter <= do_restart ? 0:(timeout_counter + 1'b1);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_restart_compare <= 0;
+      else 
+        do_restart_compare <= timeout_counter == {timeout_reg,5'b11111};
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_restart <= 0;
+      else 
+        do_restart <= poll_en && do_restart_compare;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          clear_interrupt <= 0;
+      else 
+        clear_interrupt <= control_reg_en ? csr_writedata[31] : 0;
+    end
+
+
+  //control register
+  assign control_reg_en = (csr_address == { 4'b0100}) && csr_write && csr_chipselect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          control_reg <= 0;
+      else if (control_reg_en)
+          control_reg <= {1'b0, csr_writedata[30 : 0]};
+    end
+
+
+  //descriptor_pointer_upper_reg
+  assign descriptor_pointer_upper_reg_en = (csr_address == { 4'b1100}) && csr_write && csr_chipselect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_pointer_upper_reg <= 0;
+      else if (descriptor_pointer_upper_reg_en)
+          descriptor_pointer_upper_reg <= csr_writedata;
+    end
+
+
+  //section to update the descriptor pointer
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_read_r <= 0;
+      else 
+        descriptor_read_read_r <= descriptor_read_read;
+    end
+
+
+  assign descriptor_read_read_rising = descriptor_read_read && !descriptor_read_read_r;
+  assign descriptor_pointer_data = descriptor_read_read_rising ? descriptor_read_address:csr_writedata;
+  //descriptor_pointer_lower_reg
+  assign descriptor_pointer_lower_reg_en = ((csr_address == { 4'b1000}) && csr_write && csr_chipselect) || (poll_en && descriptor_read_read_rising);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_pointer_lower_reg <= 0;
+      else if (descriptor_pointer_lower_reg_en)
+          descriptor_pointer_lower_reg <= descriptor_pointer_data;
+    end
+
+
+  //Hardware Version Register
+  assign hw_version = 4'b0001;
+  assign version_reg = {24'h000000, hw_version};
+  //status register
+  assign status_reg = {27'b0, busy, chain_completed, descriptor_completed, eop_encountered, error};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          busy <= 0;
+      else 
+        busy <= ~command_fifo_empty || ~status_token_fifo_empty || ~desc_address_fifo_empty || chain_run || descriptor_write_busy || delayed_csr_write || owned_by_hw || write_go;
+    end
+
+
+  //Chain Completed Status Register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_completed <= 0;
+      else if ((run && ~owned_by_hw && ~busy) || clear_chain_completed || do_restart)
+          chain_completed <= (clear_chain_completed || do_restart)? 1'b0 : ~delayed_csr_write;
+    end
+
+
+  //chain_completed_int is the internal chain completed state for SGDMA.
+  //Will not be affected with clearing of chain_completed Status Register,to prevent SGDMA being restarted when the status bit is cleared
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_completed_int <= 0;
+      else if ((run && ~owned_by_hw && ~busy) || clear_run || do_restart)
+          chain_completed_int <= (clear_run || do_restart) ? 1'b0 : ~delayed_csr_write;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_csr_write <= 0;
+      else 
+        delayed_csr_write <= csr_write;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_completed <= 0;
+      else if (descriptor_write_write_fall || clear_descriptor_completed)
+          descriptor_completed <= ~clear_descriptor_completed;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          error <= 0;
+      else if (atlantic_error || clear_error)
+          error <= ~clear_error;
+    end
+
+
+  assign csr_status = csr_write && csr_chipselect && (csr_address == 4'b0);
+  assign clear_chain_completed = csr_writedata[3] && csr_status;
+  assign clear_descriptor_completed = csr_writedata[2] && csr_status;
+  assign clear_error = csr_writedata[0] && csr_status;
+  assign csr_control = csr_write && csr_chipselect && (csr_address == 4'h4);
+  assign clear_run = !csr_writedata[5] && csr_control;
+  assign pollen_clear_run = poll_en & clear_run;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_eop_encountered <= 0;
+      else 
+        delayed_eop_encountered <= eop_encountered;
+    end
+
+
+  assign eop_encountered_rise = ~delayed_eop_encountered && eop_encountered;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_descriptor_write_write <= 0;
+      else 
+        delayed_descriptor_write_write <= descriptor_write_write;
+    end
+
+
+  assign descriptor_write_write_fall = delayed_descriptor_write_write && ~descriptor_write_write;
+  //eop_encountered register
+  assign clear_eop_encountered = csr_writedata[1] && csr_status;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          eop_encountered <= 0;
+      else if (t_eop || clear_eop_encountered)
+          eop_encountered <= ~clear_eop_encountered;
+    end
+
+
+  //chain_completed rising edge detector
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_chain_completed_int <= 0;
+      else 
+        delayed_chain_completed_int <= chain_completed_int;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          can_have_new_chain_complete <= 0;
+      else if (descriptor_write_write || (~delayed_chain_completed_int && chain_completed_int))
+          can_have_new_chain_complete <= descriptor_write_write;
+    end
+
+
+  assign chain_completed_int_rise = ~delayed_chain_completed_int && chain_completed_int && can_have_new_chain_complete;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_counter <= 0;
+      else if (status_token_fifo_rdreq)
+          descriptor_counter <= descriptor_counter + 1'b1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_descriptor_counter <= 0;
+      else 
+        delayed_descriptor_counter <= descriptor_counter;
+    end
+
+
+  assign delayed_max_desc_processed = max_desc_processed - 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          csr_irq <= 0;
+      else 
+        csr_irq <= csr_irq ? ~clear_interrupt : (delayed_run && ie_global && ((ie_error && error) || (ie_eop_encountered && eop_encountered_rise) || (ie_descriptor_completed && descriptor_write_write_fall) || (ie_chain_completed && chain_completed_int_rise) || (ie_max_desc_processed && (descriptor_counter == max_desc_processed) && (delayed_descriptor_counter == delayed_max_desc_processed) )));
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo (
+                                                                               // inputs:
+                                                                                clk,
+                                                                                controlbitsfifo_data,
+                                                                                controlbitsfifo_rdreq,
+                                                                                controlbitsfifo_wrreq,
+                                                                                reset,
+
+                                                                               // outputs:
+                                                                                controlbitsfifo_empty,
+                                                                                controlbitsfifo_full,
+                                                                                controlbitsfifo_q
+                                                                             )
+;
+
+  output           controlbitsfifo_empty;
+  output           controlbitsfifo_full;
+  output  [  6: 0] controlbitsfifo_q;
+  input            clk;
+  input   [  6: 0] controlbitsfifo_data;
+  input            controlbitsfifo_rdreq;
+  input            controlbitsfifo_wrreq;
+  input            reset;
+
+
+wire             controlbitsfifo_empty;
+wire             controlbitsfifo_full;
+wire    [  6: 0] controlbitsfifo_q;
+  scfifo descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (controlbitsfifo_data),
+      .empty (controlbitsfifo_empty),
+      .full (controlbitsfifo_full),
+      .q (controlbitsfifo_q),
+      .rdreq (controlbitsfifo_rdreq),
+      .wrreq (controlbitsfifo_wrreq)
+    );
+
+  defparam descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.add_ram_output_register = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.intended_device_family = "MAX10",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_numwords = 2,
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_showahead = "OFF",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_type = "scfifo",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_width = 7,
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.lpm_widthu = 1,
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.overflow_checking = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.underflow_checking = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo_controlbitsfifo.use_eab = "OFF";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_read_which_resides_within_q_sys_sgdma_rx (
+                                                             // inputs:
+                                                              clk,
+                                                              command_fifo_full,
+                                                              controlbitsfifo_rdreq,
+                                                              desc_address_fifo_full,
+                                                              descriptor_pointer_lower_reg_out,
+                                                              descriptor_pointer_upper_reg_out,
+                                                              descriptor_read_readdata,
+                                                              descriptor_read_readdatavalid,
+                                                              descriptor_read_waitrequest,
+                                                              pollen_clear_run,
+                                                              reset,
+                                                              reset_n,
+                                                              run,
+
+                                                             // outputs:
+                                                              atlantic_channel,
+                                                              chain_run,
+                                                              command_fifo_data,
+                                                              command_fifo_wrreq,
+                                                              control,
+                                                              controlbitsfifo_q,
+                                                              desc_address_fifo_data,
+                                                              desc_address_fifo_wrreq,
+                                                              descriptor_read_address,
+                                                              descriptor_read_read,
+                                                              generate_eop,
+                                                              next_desc,
+                                                              owned_by_hw,
+                                                              read_fixed_address,
+                                                              write_fixed_address
+                                                           )
+;
+
+  output  [  3: 0] atlantic_channel;
+  output           chain_run;
+  output  [103: 0] command_fifo_data;
+  output           command_fifo_wrreq;
+  output  [  7: 0] control;
+  output  [  6: 0] controlbitsfifo_q;
+  output  [ 31: 0] desc_address_fifo_data;
+  output           desc_address_fifo_wrreq;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output           generate_eop;
+  output  [ 31: 0] next_desc;
+  output           owned_by_hw;
+  output           read_fixed_address;
+  output           write_fixed_address;
+  input            clk;
+  input            command_fifo_full;
+  input            controlbitsfifo_rdreq;
+  input            desc_address_fifo_full;
+  input   [ 31: 0] descriptor_pointer_lower_reg_out;
+  input   [ 31: 0] descriptor_pointer_upper_reg_out;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            pollen_clear_run;
+  input            reset;
+  input            reset_n;
+  input            run;
+
+
+wire    [  3: 0] atlantic_channel;
+wire    [ 15: 0] bytes_to_transfer;
+reg              chain_run;
+wire    [103: 0] command_fifo_data;
+reg              command_fifo_wrreq;
+wire             command_fifo_wrreq_in;
+wire    [  7: 0] control;
+wire    [  6: 0] controlbitsfifo_data;
+wire             controlbitsfifo_empty;
+wire             controlbitsfifo_full;
+wire    [  6: 0] controlbitsfifo_q;
+wire             controlbitsfifo_wrreq;
+reg              delayed_desc_reg_en;
+reg              delayed_run;
+reg     [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_wrreq;
+reg     [255: 0] desc_assembler;
+reg              desc_read_start;
+reg     [255: 0] desc_reg;
+wire             desc_reg_en;
+reg     [ 31: 0] descriptor_read_address;
+reg              descriptor_read_completed;
+wire             descriptor_read_completed_in;
+reg              descriptor_read_read;
+wire             fifos_not_full;
+wire             generate_eop;
+wire             got_one_descriptor;
+wire    [255: 0] init_descriptor;
+wire    [ 31: 0] next_desc;
+wire             owned_by_hw;
+wire    [255: 0] pollen_clear_run_desc;
+reg     [  3: 0] posted_desc_counter;
+reg              posted_read_queued;
+wire    [ 31: 0] read_address;
+wire    [  7: 0] read_burst;
+wire             read_fixed_address;
+reg     [  3: 0] received_desc_counter;
+reg              run_rising_edge;
+wire             run_rising_edge_in;
+reg              started;
+wire             started_in;
+wire    [ 31: 0] write_address;
+wire    [  7: 0] write_burst;
+wire             write_fixed_address;
+  //descriptor_read, which is an e_avalon_master
+  //Control assignments
+  assign command_fifo_wrreq_in = chain_run && fifos_not_full && delayed_desc_reg_en && owned_by_hw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_fifo_wrreq <= 0;
+      else 
+        command_fifo_wrreq <= command_fifo_wrreq_in;
+    end
+
+
+  assign desc_address_fifo_wrreq = command_fifo_wrreq;
+  assign fifos_not_full = ~command_fifo_full && ~desc_address_fifo_full;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_desc_reg_en <= 0;
+      else 
+        delayed_desc_reg_en <= desc_reg_en;
+    end
+
+
+  assign read_address = desc_reg[31 : 0];
+  assign write_address = desc_reg[95 : 64];
+  assign next_desc = desc_reg[159 : 128];
+  assign bytes_to_transfer = desc_reg[207 : 192];
+  assign read_burst = desc_reg[215 : 208];
+  assign write_burst = desc_reg[223 : 216];
+  assign control = desc_reg[255 : 248];
+  assign command_fifo_data = {control, write_burst, read_burst, bytes_to_transfer, write_address, read_address};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_address_fifo_data <= 0;
+      else if (desc_reg_en)
+          desc_address_fifo_data <= next_desc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          received_desc_counter <= 0;
+      else 
+        received_desc_counter <= (received_desc_counter == 8)? 0 : (descriptor_read_readdatavalid ? (received_desc_counter + 1) : received_desc_counter);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          posted_desc_counter <= 0;
+      else 
+        posted_desc_counter <= (desc_read_start & owned_by_hw & (posted_desc_counter != 8)) ? 8 : ((|posted_desc_counter & ~descriptor_read_waitrequest & fifos_not_full) ? (posted_desc_counter - 1) : posted_desc_counter);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_read_start <= 0;
+      else if (~descriptor_read_waitrequest)
+          desc_read_start <= desc_read_start ? 0 : ((~(desc_reg_en | delayed_desc_reg_en | command_fifo_wrreq | |received_desc_counter)) ? (chain_run & fifos_not_full & ~|posted_desc_counter & ~posted_read_queued) : 0);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_run <= 0;
+      else 
+        chain_run <= (run && owned_by_hw | (delayed_desc_reg_en | desc_reg_en) | |posted_desc_counter | |received_desc_counter) || run_rising_edge_in;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_read <= 0;
+      else if (~descriptor_read_waitrequest)
+          descriptor_read_read <= |posted_desc_counter & fifos_not_full;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_address <= 0;
+      else if (~descriptor_read_waitrequest)
+          descriptor_read_address <= (descriptor_read_read)? (descriptor_read_address + 4) : next_desc;
+    end
+
+
+  assign descriptor_read_completed_in = started ? (run && ~owned_by_hw && ~|posted_desc_counter) : descriptor_read_completed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          posted_read_queued <= 0;
+      else 
+        posted_read_queued <= posted_read_queued ? ~(got_one_descriptor) : (descriptor_read_read);
+    end
+
+
+  //control bits
+  assign generate_eop = control[0];
+  assign read_fixed_address = control[1];
+  assign write_fixed_address = control[2];
+  assign atlantic_channel = control[6 : 3];
+  assign owned_by_hw = control[7];
+  assign got_one_descriptor = received_desc_counter == 8;
+  //read descriptor
+  assign desc_reg_en = chain_run && got_one_descriptor;
+  assign init_descriptor = {1'b1, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
+  //Clear owned_by_hw bit when run is clear in Descriptor Polling Mode
+  assign pollen_clear_run_desc = {1'b0, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_reg <= 0;
+      else if (desc_reg_en || run_rising_edge_in || pollen_clear_run)
+          desc_reg <= run_rising_edge_in ? init_descriptor : pollen_clear_run ? pollen_clear_run_desc: desc_assembler;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_assembler <= 0;
+      else if (descriptor_read_readdatavalid)
+          desc_assembler <= desc_assembler >> 32 | {descriptor_read_readdata, 224'b0};
+    end
+
+
+  //descriptor_read_completed register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_completed <= 0;
+      else 
+        descriptor_read_completed <= descriptor_read_completed_in;
+    end
+
+
+  //started register
+  assign started_in = (run_rising_edge || run_rising_edge_in) ? 1'b1 : (descriptor_read_completed ? 1'b0 : started);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          started <= 0;
+      else 
+        started <= started_in;
+    end
+
+
+  //delayed_run signal for the rising edge detector
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_run <= 0;
+      else 
+        delayed_run <= run;
+    end
+
+
+  //Run rising edge detector
+  assign run_rising_edge_in = run & ~delayed_run;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          run_rising_edge <= 0;
+      else if (run_rising_edge_in || desc_reg_en)
+          run_rising_edge <= run_rising_edge_in;
+    end
+
+
+  //the_descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo, which is an e_instance
+  descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo the_descriptor_read_which_resides_within_q_sys_sgdma_rx_control_bits_fifo
+    (
+      .clk                   (clk),
+      .controlbitsfifo_data  (controlbitsfifo_data),
+      .controlbitsfifo_empty (controlbitsfifo_empty),
+      .controlbitsfifo_full  (controlbitsfifo_full),
+      .controlbitsfifo_q     (controlbitsfifo_q),
+      .controlbitsfifo_rdreq (controlbitsfifo_rdreq),
+      .controlbitsfifo_wrreq (controlbitsfifo_wrreq),
+      .reset                 (reset)
+    );
+
+  assign controlbitsfifo_data = control[6 : 0];
+  assign controlbitsfifo_wrreq = command_fifo_wrreq;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_write_which_resides_within_q_sys_sgdma_rx (
+                                                              // inputs:
+                                                               clk,
+                                                               controlbitsfifo_q,
+                                                               desc_address_fifo_empty,
+                                                               desc_address_fifo_q,
+                                                               descriptor_write_waitrequest,
+                                                               park,
+                                                               reset_n,
+                                                               status_token_fifo_data,
+                                                               status_token_fifo_empty,
+                                                               status_token_fifo_q,
+
+                                                              // outputs:
+                                                               atlantic_error,
+                                                               controlbitsfifo_rdreq,
+                                                               desc_address_fifo_rdreq,
+                                                               descriptor_write_address,
+                                                               descriptor_write_busy,
+                                                               descriptor_write_write,
+                                                               descriptor_write_writedata,
+                                                               status_token_fifo_rdreq,
+                                                               t_eop
+                                                            )
+;
+
+  output           atlantic_error;
+  output           controlbitsfifo_rdreq;
+  output           desc_address_fifo_rdreq;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_busy;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output           status_token_fifo_rdreq;
+  output           t_eop;
+  input            clk;
+  input   [  6: 0] controlbitsfifo_q;
+  input            desc_address_fifo_empty;
+  input   [ 31: 0] desc_address_fifo_q;
+  input            descriptor_write_waitrequest;
+  input            park;
+  input            reset_n;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_empty;
+  input   [ 23: 0] status_token_fifo_q;
+
+
+wire             atlantic_error;
+wire             can_write;
+wire             controlbitsfifo_rdreq;
+wire             desc_address_fifo_rdreq;
+reg     [ 31: 0] descriptor_write_address;
+wire             descriptor_write_busy;
+reg              descriptor_write_write;
+reg              descriptor_write_write0;
+reg     [ 31: 0] descriptor_write_writedata;
+wire             fifos_not_empty;
+wire    [  7: 0] status_reg;
+reg              status_token_fifo_rdreq;
+wire             status_token_fifo_rdreq_in;
+wire             t_eop;
+  //descriptor_write, which is an e_avalon_master
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_writedata <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_writedata <= {park, controlbitsfifo_q, status_token_fifo_q};
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_address <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_address <= desc_address_fifo_q + 28;
+    end
+
+
+  assign fifos_not_empty = ~status_token_fifo_empty && ~desc_address_fifo_empty;
+  assign can_write = ~descriptor_write_waitrequest && fifos_not_empty;
+  //write register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_write0 <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_write0 <= status_token_fifo_rdreq;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_write <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_write <= descriptor_write_write0;
+    end
+
+
+  //status_token_fifo_rdreq register
+  assign status_token_fifo_rdreq_in = status_token_fifo_rdreq ? 1'b0 : can_write;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          status_token_fifo_rdreq <= 0;
+      else 
+        status_token_fifo_rdreq <= status_token_fifo_rdreq_in;
+    end
+
+
+  assign desc_address_fifo_rdreq = status_token_fifo_rdreq;
+  assign descriptor_write_busy = descriptor_write_write0 | descriptor_write_write;
+  assign status_reg = status_token_fifo_data[23 : 16];
+  assign t_eop = status_reg[7];
+  assign atlantic_error = status_reg[6] | status_reg[5] | status_reg[4] | status_reg[3] | status_reg[2] | status_reg[1] | status_reg[0];
+  assign controlbitsfifo_rdreq = status_token_fifo_rdreq;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_chain (
+                              // inputs:
+                               clk,
+                               command_fifo_empty,
+                               command_fifo_full,
+                               csr_address,
+                               csr_chipselect,
+                               csr_read,
+                               csr_write,
+                               csr_writedata,
+                               desc_address_fifo_empty,
+                               desc_address_fifo_full,
+                               desc_address_fifo_q,
+                               descriptor_read_readdata,
+                               descriptor_read_readdatavalid,
+                               descriptor_read_waitrequest,
+                               descriptor_write_waitrequest,
+                               reset,
+                               reset_n,
+                               status_token_fifo_data,
+                               status_token_fifo_empty,
+                               status_token_fifo_q,
+                               write_go,
+
+                              // outputs:
+                               command_fifo_data,
+                               command_fifo_wrreq,
+                               csr_irq,
+                               csr_readdata,
+                               desc_address_fifo_data,
+                               desc_address_fifo_rdreq,
+                               desc_address_fifo_wrreq,
+                               descriptor_read_address,
+                               descriptor_read_read,
+                               descriptor_write_address,
+                               descriptor_write_write,
+                               descriptor_write_writedata,
+                               status_token_fifo_rdreq,
+                               sw_reset
+                            )
+;
+
+  output  [103: 0] command_fifo_data;
+  output           command_fifo_wrreq;
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] desc_address_fifo_data;
+  output           desc_address_fifo_rdreq;
+  output           desc_address_fifo_wrreq;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output           status_token_fifo_rdreq;
+  output           sw_reset;
+  input            clk;
+  input            command_fifo_empty;
+  input            command_fifo_full;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input            desc_address_fifo_empty;
+  input            desc_address_fifo_full;
+  input   [ 31: 0] desc_address_fifo_q;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            descriptor_write_waitrequest;
+  input            reset;
+  input            reset_n;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_empty;
+  input   [ 23: 0] status_token_fifo_q;
+  input            write_go;
+
+
+wire    [  3: 0] atlantic_channel;
+wire             atlantic_error;
+wire             chain_run;
+wire    [103: 0] command_fifo_data;
+wire             command_fifo_wrreq;
+wire    [  7: 0] control;
+wire    [  6: 0] controlbitsfifo_q;
+wire             controlbitsfifo_rdreq;
+wire             csr_irq;
+wire    [ 31: 0] csr_readdata;
+wire    [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_rdreq;
+wire             desc_address_fifo_wrreq;
+wire    [ 31: 0] descriptor_pointer_lower_reg_out;
+wire    [ 31: 0] descriptor_pointer_upper_reg_out;
+wire    [ 31: 0] descriptor_read_address;
+wire             descriptor_read_read;
+wire    [ 31: 0] descriptor_write_address;
+wire             descriptor_write_busy;
+wire             descriptor_write_write;
+wire    [ 31: 0] descriptor_write_writedata;
+wire             generate_eop;
+wire    [ 31: 0] next_desc;
+wire             owned_by_hw;
+wire             park;
+wire             pollen_clear_run;
+wire             read_fixed_address;
+wire             run;
+wire             status_token_fifo_rdreq;
+wire             sw_reset;
+wire             t_eop;
+wire             write_fixed_address;
+  control_status_slave_which_resides_within_q_sys_sgdma_rx the_control_status_slave_which_resides_within_q_sys_sgdma_rx
+    (
+      .atlantic_error                   (atlantic_error),
+      .chain_run                        (chain_run),
+      .clk                              (clk),
+      .command_fifo_empty               (command_fifo_empty),
+      .csr_address                      (csr_address),
+      .csr_chipselect                   (csr_chipselect),
+      .csr_irq                          (csr_irq),
+      .csr_read                         (csr_read),
+      .csr_readdata                     (csr_readdata),
+      .csr_write                        (csr_write),
+      .csr_writedata                    (csr_writedata),
+      .desc_address_fifo_empty          (desc_address_fifo_empty),
+      .descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
+      .descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
+      .descriptor_read_address          (descriptor_read_address),
+      .descriptor_read_read             (descriptor_read_read),
+      .descriptor_write_busy            (descriptor_write_busy),
+      .descriptor_write_write           (descriptor_write_write),
+      .owned_by_hw                      (owned_by_hw),
+      .park                             (park),
+      .pollen_clear_run                 (pollen_clear_run),
+      .reset_n                          (reset_n),
+      .run                              (run),
+      .status_token_fifo_empty          (status_token_fifo_empty),
+      .status_token_fifo_rdreq          (status_token_fifo_rdreq),
+      .sw_reset                         (sw_reset),
+      .t_eop                            (t_eop),
+      .write_go                         (write_go)
+    );
+
+  descriptor_read_which_resides_within_q_sys_sgdma_rx the_descriptor_read_which_resides_within_q_sys_sgdma_rx
+    (
+      .atlantic_channel                 (atlantic_channel),
+      .chain_run                        (chain_run),
+      .clk                              (clk),
+      .command_fifo_data                (command_fifo_data),
+      .command_fifo_full                (command_fifo_full),
+      .command_fifo_wrreq               (command_fifo_wrreq),
+      .control                          (control),
+      .controlbitsfifo_q                (controlbitsfifo_q),
+      .controlbitsfifo_rdreq            (controlbitsfifo_rdreq),
+      .desc_address_fifo_data           (desc_address_fifo_data),
+      .desc_address_fifo_full           (desc_address_fifo_full),
+      .desc_address_fifo_wrreq          (desc_address_fifo_wrreq),
+      .descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
+      .descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
+      .descriptor_read_address          (descriptor_read_address),
+      .descriptor_read_read             (descriptor_read_read),
+      .descriptor_read_readdata         (descriptor_read_readdata),
+      .descriptor_read_readdatavalid    (descriptor_read_readdatavalid),
+      .descriptor_read_waitrequest      (descriptor_read_waitrequest),
+      .generate_eop                     (generate_eop),
+      .next_desc                        (next_desc),
+      .owned_by_hw                      (owned_by_hw),
+      .pollen_clear_run                 (pollen_clear_run),
+      .read_fixed_address               (read_fixed_address),
+      .reset                            (reset),
+      .reset_n                          (reset_n),
+      .run                              (run),
+      .write_fixed_address              (write_fixed_address)
+    );
+
+  descriptor_write_which_resides_within_q_sys_sgdma_rx the_descriptor_write_which_resides_within_q_sys_sgdma_rx
+    (
+      .atlantic_error               (atlantic_error),
+      .clk                          (clk),
+      .controlbitsfifo_q            (controlbitsfifo_q),
+      .controlbitsfifo_rdreq        (controlbitsfifo_rdreq),
+      .desc_address_fifo_empty      (desc_address_fifo_empty),
+      .desc_address_fifo_q          (desc_address_fifo_q),
+      .desc_address_fifo_rdreq      (desc_address_fifo_rdreq),
+      .descriptor_write_address     (descriptor_write_address),
+      .descriptor_write_busy        (descriptor_write_busy),
+      .descriptor_write_waitrequest (descriptor_write_waitrequest),
+      .descriptor_write_write       (descriptor_write_write),
+      .descriptor_write_writedata   (descriptor_write_writedata),
+      .park                         (park),
+      .reset_n                      (reset_n),
+      .status_token_fifo_data       (status_token_fifo_data),
+      .status_token_fifo_empty      (status_token_fifo_empty),
+      .status_token_fifo_q          (status_token_fifo_q),
+      .status_token_fifo_rdreq      (status_token_fifo_rdreq),
+      .t_eop                        (t_eop)
+    );
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_command_grabber (
+                                        // inputs:
+                                         clk,
+                                         command_fifo_empty,
+                                         command_fifo_q,
+                                         m_write_waitrequest,
+                                         reset_n,
+                                         write_go,
+
+                                        // outputs:
+                                         command_fifo_rdreq,
+                                         generate_eop,
+                                         write_command_data,
+                                         write_command_valid
+                                      )
+;
+
+  output           command_fifo_rdreq;
+  output           generate_eop;
+  output  [ 56: 0] write_command_data;
+  output           write_command_valid;
+  input            clk;
+  input            command_fifo_empty;
+  input   [103: 0] command_fifo_q;
+  input            m_write_waitrequest;
+  input            reset_n;
+  input            write_go;
+
+
+wire    [  3: 0] atlantic_channel;
+wire    [ 15: 0] bytes_to_transfer;
+wire             command_fifo_rdreq;
+wire             command_fifo_rdreq_in;
+reg              command_fifo_rdreq_reg;
+reg              command_valid;
+wire    [  7: 0] control;
+reg              delay1_command_valid;
+wire             generate_eop;
+wire    [ 31: 0] read_address;
+wire    [  7: 0] read_burst;
+wire             read_fixed_address;
+wire    [ 31: 0] write_address;
+wire    [  7: 0] write_burst;
+reg     [ 56: 0] write_command_data;
+wire             write_command_valid;
+wire             write_fixed_address;
+  //Descriptor components
+  assign read_address = command_fifo_q[31 : 0];
+  assign write_address = command_fifo_q[63 : 32];
+  assign bytes_to_transfer = command_fifo_q[79 : 64];
+  assign read_burst = command_fifo_q[87 : 80];
+  assign write_burst = command_fifo_q[95 : 88];
+  assign control = command_fifo_q[103 : 96];
+  //control bits
+  assign generate_eop = control[0];
+  assign read_fixed_address = control[1];
+  assign write_fixed_address = control[2];
+  assign atlantic_channel = control[6 : 3];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          write_command_data <= 0;
+      else 
+        write_command_data <= {~write_fixed_address, write_burst, bytes_to_transfer, write_address};
+    end
+
+
+  assign write_command_valid = command_valid;
+  //command_fifo_rdreq register
+  assign command_fifo_rdreq_in = (command_fifo_rdreq_reg || command_valid) ? 1'b0 : (~write_go && ~m_write_waitrequest);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_fifo_rdreq_reg <= 0;
+      else if (~command_fifo_empty)
+          command_fifo_rdreq_reg <= command_fifo_rdreq_in;
+    end
+
+
+  assign command_fifo_rdreq = command_fifo_rdreq_reg;
+  //command_valid register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delay1_command_valid <= 0;
+      else 
+        delay1_command_valid <= command_fifo_rdreq_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_valid <= 0;
+      else 
+        command_valid <= delay1_command_valid;
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module sixteen_bit_byteenable_FSM_which_resides_within_q_sys_sgdma_rx (
+                                                                        // inputs:
+                                                                         byteenable_in,
+                                                                         clk,
+                                                                         reset_n,
+                                                                         waitrequest_in,
+                                                                         write_in,
+
+                                                                        // outputs:
+                                                                         byteenable_out,
+                                                                         waitrequest_out
+                                                                      )
+;
+
+  output  [  1: 0] byteenable_out;
+  output           waitrequest_out;
+  input   [  1: 0] byteenable_in;
+  input            clk;
+  input            reset_n;
+  input            waitrequest_in;
+  input            write_in;
+
+
+wire    [  1: 0] byteenable_out;
+wire             waitrequest_out;
+  assign byteenable_out = byteenable_in & {2{write_in}};
+  assign waitrequest_out = waitrequest_in | ((write_in == 1) & (waitrequest_in == 1));
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module thirty_two_bit_byteenable_FSM_which_resides_within_q_sys_sgdma_rx (
+                                                                           // inputs:
+                                                                            byteenable_in,
+                                                                            clk,
+                                                                            reset_n,
+                                                                            waitrequest_in,
+                                                                            write_in,
+
+                                                                           // outputs:
+                                                                            byteenable_out,
+                                                                            waitrequest_out
+                                                                         )
+;
+
+  output  [  3: 0] byteenable_out;
+  output           waitrequest_out;
+  input   [  3: 0] byteenable_in;
+  input            clk;
+  input            reset_n;
+  input            waitrequest_in;
+  input            write_in;
+
+
+wire             advance_to_next_state;
+wire    [  3: 0] byteenable_out;
+wire             full_lower_half_transfer;
+wire             full_upper_half_transfer;
+wire             full_word_transfer;
+wire             lower_enable;
+wire             lower_stall;
+wire             partial_lower_half_transfer;
+wire             partial_upper_half_transfer;
+reg              state_bit;
+wire             transfer_done;
+wire             two_stage_transfer;
+wire             upper_enable;
+wire             upper_stall;
+wire             waitrequest_out;
+  assign partial_lower_half_transfer = byteenable_in[1 : 0] != 0;
+  assign full_lower_half_transfer = byteenable_in[1 : 0] == {2 {1'b1}};
+  assign partial_upper_half_transfer = byteenable_in[3 : 2] != 0;
+  assign full_upper_half_transfer = byteenable_in[3 : 2] == {2 {1'b1}};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          state_bit <= 0;
+      else if (transfer_done == 1)
+          state_bit <= 0;
+      else if (advance_to_next_state == 1)
+          state_bit <= 1;
+    end
+
+
+  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
+  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
+  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);
+  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | 
+    ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) |
+    ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));
+
+  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |
+    ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) |
+    ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));
+
+  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |
+    ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) |
+    ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));
+
+  //lower_sixteen_bit_byteenable_FSM, which is an e_instance
+  sixteen_bit_byteenable_FSM_which_resides_within_q_sys_sgdma_rx lower_sixteen_bit_byteenable_FSM
+    (
+      .byteenable_in   (byteenable_in[1 : 0]),
+      .byteenable_out  (byteenable_out[1 : 0]),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .waitrequest_in  (waitrequest_in),
+      .waitrequest_out (lower_stall),
+      .write_in        (lower_enable)
+    );
+
+  //upper_sixteen_bit_byteenable_FSM, which is an e_instance
+  sixteen_bit_byteenable_FSM_which_resides_within_q_sys_sgdma_rx upper_sixteen_bit_byteenable_FSM
+    (
+      .byteenable_in   (byteenable_in[3 : 2]),
+      .byteenable_out  (byteenable_out[3 : 2]),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .waitrequest_in  (waitrequest_in),
+      .waitrequest_out (upper_stall),
+      .write_in        (upper_enable)
+    );
+
+  assign waitrequest_out = waitrequest_in | ((transfer_done == 0) & (write_in == 1));
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module byteenable_gen_which_resides_within_q_sys_sgdma_rx (
+                                                            // inputs:
+                                                             byteenable_in,
+                                                             clk,
+                                                             reset_n,
+                                                             waitrequest_in,
+                                                             write_in,
+
+                                                            // outputs:
+                                                             byteenable_out,
+                                                             waitrequest_out
+                                                          )
+;
+
+  output  [  3: 0] byteenable_out;
+  output           waitrequest_out;
+  input   [  3: 0] byteenable_in;
+  input            clk;
+  input            reset_n;
+  input            waitrequest_in;
+  input            write_in;
+
+
+wire    [  3: 0] byteenable_out;
+wire             waitrequest_out;
+  //the_thirty_two_bit_byteenable_FSM, which is an e_instance
+  thirty_two_bit_byteenable_FSM_which_resides_within_q_sys_sgdma_rx the_thirty_two_bit_byteenable_FSM
+    (
+      .byteenable_in   (byteenable_in),
+      .byteenable_out  (byteenable_out),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .waitrequest_in  (waitrequest_in),
+      .waitrequest_out (waitrequest_out),
+      .write_in        (write_in)
+    );
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_m_write (
+                                // inputs:
+                                 clk,
+                                 enough_data,
+                                 eop_found,
+                                 m_write_waitrequest,
+                                 reset_n,
+                                 sink_stream_data,
+                                 sink_stream_empty,
+                                 sink_stream_endofpacket,
+                                 sink_stream_error,
+                                 sink_stream_startofpacket,
+                                 sink_stream_valid,
+                                 status_token_fifo_full,
+                                 write_command_data,
+                                 write_command_valid,
+
+                                // outputs:
+                                 m_write_address,
+                                 m_write_byteenable,
+                                 m_write_write,
+                                 m_write_writedata,
+                                 sink_stream_ready,
+                                 status_token_fifo_data,
+                                 status_token_fifo_wrreq,
+                                 write_go
+                              )
+;
+
+  output  [ 31: 0] m_write_address;
+  output  [  3: 0] m_write_byteenable;
+  output           m_write_write;
+  output  [ 31: 0] m_write_writedata;
+  output           sink_stream_ready;
+  output  [ 23: 0] status_token_fifo_data;
+  output           status_token_fifo_wrreq;
+  output           write_go;
+  input            clk;
+  input            enough_data;
+  input            eop_found;
+  input            m_write_waitrequest;
+  input            reset_n;
+  input   [ 31: 0] sink_stream_data;
+  input   [  1: 0] sink_stream_empty;
+  input            sink_stream_endofpacket;
+  input   [  5: 0] sink_stream_error;
+  input            sink_stream_startofpacket;
+  input            sink_stream_valid;
+  input            status_token_fifo_full;
+  input   [ 56: 0] write_command_data;
+  input            write_command_valid;
+
+
+wire    [ 15: 0] actual_bytes_transferred;
+wire    [  3: 0] all_one;
+reg     [  3: 0] burst_counter;
+wire             burst_counter_decrement;
+wire    [  3: 0] burst_counter_next;
+reg     [  3: 0] burst_counter_reg;
+wire    [  3: 0] burst_size;
+reg              byteenable_enable;
+wire    [ 15: 0] bytes_to_transfer;
+reg     [ 15: 0] counter;
+wire    [ 15: 0] counter_in;
+reg              delayed_write_command_valid;
+reg              delayed_write_go;
+wire             e_00;
+wire             e_01;
+wire             e_02;
+wire             e_03;
+wire             e_04;
+wire             e_05;
+wire             e_06;
+reg              eop_found_hold;
+reg              eop_reg;
+wire             increment;
+wire             increment_address;
+reg     [ 31: 0] m_write_address;
+wire    [  3: 0] m_write_byteenable;
+wire    [  3: 0] m_write_byteenable_in;
+reg     [  3: 0] m_write_byteenable_reg;
+wire             m_write_waitrequest_out;
+reg              m_write_write;
+reg              m_write_write_sig;
+wire    [ 31: 0] m_write_writedata;
+reg     [ 31: 0] m_write_writedata_reg;
+wire             m_writefifo_fill;
+wire    [  3: 0] shift0;
+wire    [  3: 0] shift1;
+wire    [  3: 0] shift2;
+wire    [  3: 0] shift3;
+wire             single_transfer;
+wire    [  3: 0] sink_stream_empty_shift;
+wire             sink_stream_ready;
+wire             sink_stream_really_valid;
+wire    [ 31: 0] start_address;
+reg     [  7: 0] status_reg;
+wire    [  7: 0] status_reg_in;
+wire    [ 23: 0] status_token_fifo_data;
+wire             status_token_fifo_wrreq;
+wire    [  7: 0] status_word;
+wire             t_eop;
+reg     [ 56: 0] write_command_data_reg;
+wire             write_go;
+reg              write_go_fall_reg;
+wire             write_go_fall_reg_in;
+reg              write_go_reg;
+wire             write_go_reg_in;
+wire             write_go_reg_in_teop;
+  //m_write, which is an e_avalon_master
+  assign burst_size = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_write_write <= 0;
+      else if (~m_write_waitrequest_out)
+          m_write_write <= write_go_reg & (sink_stream_really_valid | m_write_write_sig);
+    end
+
+
+  assign m_writefifo_fill = 1;
+  //command input
+  assign start_address = write_command_data_reg[31 : 0];
+  assign bytes_to_transfer = write_command_data_reg[47 : 32];
+  assign increment_address = write_command_data_reg[56];
+  //increment or keep constant, the m_write_address depending on the command bit
+  assign m_write_writedata = m_write_writedata_reg;
+  assign increment = write_go_reg & sink_stream_really_valid;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_write_writedata_reg <= 0;
+      else if (~m_write_waitrequest_out)
+          m_write_writedata_reg <= sink_stream_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_write_write_sig <= 0;
+      else if (m_write_waitrequest_out)
+          m_write_write_sig <= sink_stream_really_valid & ~m_write_write;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_write_address <= 0;
+      else if (~m_write_waitrequest_out)
+          m_write_address <= delayed_write_command_valid ? start_address : (increment_address ? (m_write_write ? (m_write_address + 4) : m_write_address) : start_address);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          eop_found_hold <= 0;
+      else if (write_go_reg)
+          eop_found_hold <= eop_found_hold ? ~(sink_stream_endofpacket & sink_stream_really_valid) : eop_found;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          burst_counter_reg <= 0;
+      else if (~m_write_waitrequest_out)
+          burst_counter_reg <= burst_counter;
+    end
+
+
+  assign burst_counter_decrement = |burst_counter & write_go_reg & sink_stream_really_valid;
+  assign burst_counter_next = burst_counter - 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          burst_counter <= 0;
+      else if (~|burst_counter & ~|burst_counter_reg & write_go_reg)
+        begin
+          if (enough_data)
+              burst_counter <= burst_size;
+          else if (eop_found_hold)
+              burst_counter <= m_writefifo_fill;
+        end
+      else if (~m_write_waitrequest_out)
+          if (burst_counter_decrement)
+              burst_counter <= burst_counter_next;
+    end
+
+
+  assign shift3 = {3'b0, all_one[0]};
+  assign shift2 = {2'b0, all_one[1 : 0]};
+  assign shift1 = {1'b0, all_one[2 : 0]};
+  assign shift0 = all_one;
+  assign sink_stream_empty_shift = ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_write_byteenable_reg <= 0;
+      else if (~m_write_waitrequest_out)
+          m_write_byteenable_reg <= ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
+    end
+
+
+  assign all_one = 4'b1111;
+  assign m_write_byteenable_in = byteenable_enable ? m_write_byteenable_reg : all_one;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          byteenable_enable <= 0;
+      else if (~m_write_waitrequest_out)
+          byteenable_enable <= sink_stream_endofpacket;
+    end
+
+
+  assign sink_stream_ready = write_go_reg & ~m_write_waitrequest_out & ~eop_reg & (|bytes_to_transfer ? ~(counter >= bytes_to_transfer) : 1);
+  //sink_stream_ready_sig
+  //sink_stream_valid is only really valid when we're ready
+  assign sink_stream_really_valid = sink_stream_valid && sink_stream_ready;
+  //write_command_data_reg
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          write_command_data_reg <= 0;
+      else if (write_command_valid)
+          write_command_data_reg <= write_command_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_write_command_valid <= 0;
+      else 
+        delayed_write_command_valid <= write_command_valid;
+    end
+
+
+  //8-bits up-counter
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          counter <= 0;
+      else if (~m_write_waitrequest_out)
+          counter <= counter_in;
+    end
+
+
+  //write_go bit for all of this operation until count is up
+  assign write_go_reg_in = (delayed_write_command_valid) ? 1'b1 : (counter >= bytes_to_transfer) ? 1'b0 : write_go_reg;
+  assign write_go_reg_in_teop = eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : 1'b1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          eop_reg <= 0;
+      else 
+        eop_reg <= eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : sink_stream_endofpacket & sink_stream_really_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          write_go_reg <= 0;
+      else if (~m_write_waitrequest_out)
+          write_go_reg <= (write_go_reg && (bytes_to_transfer == 0)) ? write_go_reg_in_teop : write_go_reg_in;
+    end
+
+
+  assign write_go = write_go_reg;
+  assign t_eop = (sink_stream_endofpacket && sink_stream_really_valid) && (bytes_to_transfer == 0);
+  assign single_transfer = sink_stream_startofpacket & sink_stream_endofpacket;
+  assign counter_in = (delayed_write_command_valid) ? 16'b0 : (increment ? (counter + 4 - (sink_stream_endofpacket ? sink_stream_empty : 0)) : counter);
+  //status register
+  assign status_reg_in = write_go_fall_reg ? 0 : (status_word | status_reg);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          status_reg <= 0;
+      else 
+        status_reg <= status_reg_in;
+    end
+
+
+  //actual_bytes_transferred register
+  assign actual_bytes_transferred = counter;
+  //status_token consists of the status signals and actual_bytes_transferred
+  assign status_token_fifo_data = {status_reg, actual_bytes_transferred};
+  assign status_word = {t_eop, e_06, e_05, e_04, e_03, e_02, e_01, e_00};
+  assign e_00 = sink_stream_error[0];
+  assign e_01 = sink_stream_error[1];
+  assign e_02 = sink_stream_error[2];
+  assign e_03 = sink_stream_error[3];
+  assign e_04 = sink_stream_error[4];
+  assign e_05 = sink_stream_error[5];
+  assign e_06 = 1'b0;
+  //delayed write go register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_write_go <= 0;
+      else 
+        delayed_write_go <= write_go_reg;
+    end
+
+
+  //write_go falling edge detector
+  assign write_go_fall_reg_in = delayed_write_go && ~write_go_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          write_go_fall_reg <= 0;
+      else 
+        write_go_fall_reg <= write_go_fall_reg_in;
+    end
+
+
+  assign status_token_fifo_wrreq = write_go_fall_reg && ~status_token_fifo_full;
+  byteenable_gen_which_resides_within_q_sys_sgdma_rx the_byteenable_gen_which_resides_within_q_sys_sgdma_rx
+    (
+      .byteenable_in   (m_write_byteenable_in),
+      .byteenable_out  (m_write_byteenable),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .waitrequest_in  (m_write_waitrequest),
+      .waitrequest_out (m_write_waitrequest_out),
+      .write_in        (m_write_write)
+    );
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_command_fifo (
+                                     // inputs:
+                                      clk,
+                                      command_fifo_data,
+                                      command_fifo_rdreq,
+                                      command_fifo_wrreq,
+                                      reset,
+
+                                     // outputs:
+                                      command_fifo_empty,
+                                      command_fifo_full,
+                                      command_fifo_q
+                                   )
+;
+
+  output           command_fifo_empty;
+  output           command_fifo_full;
+  output  [103: 0] command_fifo_q;
+  input            clk;
+  input   [103: 0] command_fifo_data;
+  input            command_fifo_rdreq;
+  input            command_fifo_wrreq;
+  input            reset;
+
+
+wire             command_fifo_empty;
+wire             command_fifo_full;
+wire    [103: 0] command_fifo_q;
+  scfifo q_sys_sgdma_rx_command_fifo_command_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (command_fifo_data),
+      .empty (command_fifo_empty),
+      .full (command_fifo_full),
+      .q (command_fifo_q),
+      .rdreq (command_fifo_rdreq),
+      .wrreq (command_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_rx_command_fifo_command_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_rx_command_fifo_command_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_rx_command_fifo_command_fifo.lpm_numwords = 2,
+           q_sys_sgdma_rx_command_fifo_command_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_rx_command_fifo_command_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_rx_command_fifo_command_fifo.lpm_width = 104,
+           q_sys_sgdma_rx_command_fifo_command_fifo.lpm_widthu = 1,
+           q_sys_sgdma_rx_command_fifo_command_fifo.overflow_checking = "ON",
+           q_sys_sgdma_rx_command_fifo_command_fifo.underflow_checking = "ON",
+           q_sys_sgdma_rx_command_fifo_command_fifo.use_eab = "ON";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_desc_address_fifo (
+                                          // inputs:
+                                           clk,
+                                           desc_address_fifo_data,
+                                           desc_address_fifo_rdreq,
+                                           desc_address_fifo_wrreq,
+                                           reset,
+
+                                          // outputs:
+                                           desc_address_fifo_empty,
+                                           desc_address_fifo_full,
+                                           desc_address_fifo_q
+                                        )
+;
+
+  output           desc_address_fifo_empty;
+  output           desc_address_fifo_full;
+  output  [ 31: 0] desc_address_fifo_q;
+  input            clk;
+  input   [ 31: 0] desc_address_fifo_data;
+  input            desc_address_fifo_rdreq;
+  input            desc_address_fifo_wrreq;
+  input            reset;
+
+
+wire             desc_address_fifo_empty;
+wire             desc_address_fifo_full;
+wire    [ 31: 0] desc_address_fifo_q;
+  scfifo q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (desc_address_fifo_data),
+      .empty (desc_address_fifo_empty),
+      .full (desc_address_fifo_full),
+      .q (desc_address_fifo_q),
+      .rdreq (desc_address_fifo_rdreq),
+      .wrreq (desc_address_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_width = 32,
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
+           q_sys_sgdma_rx_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx_status_token_fifo (
+                                          // inputs:
+                                           clk,
+                                           reset,
+                                           status_token_fifo_data,
+                                           status_token_fifo_rdreq,
+                                           status_token_fifo_wrreq,
+
+                                          // outputs:
+                                           status_token_fifo_empty,
+                                           status_token_fifo_full,
+                                           status_token_fifo_q
+                                        )
+;
+
+  output           status_token_fifo_empty;
+  output           status_token_fifo_full;
+  output  [ 23: 0] status_token_fifo_q;
+  input            clk;
+  input            reset;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_rdreq;
+  input            status_token_fifo_wrreq;
+
+
+wire             status_token_fifo_empty;
+wire             status_token_fifo_full;
+wire    [ 23: 0] status_token_fifo_q;
+  scfifo q_sys_sgdma_rx_status_token_fifo_status_token_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (status_token_fifo_data),
+      .empty (status_token_fifo_empty),
+      .full (status_token_fifo_full),
+      .q (status_token_fifo_q),
+      .rdreq (status_token_fifo_rdreq),
+      .wrreq (status_token_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_rx_status_token_fifo_status_token_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.lpm_numwords = 2,
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.lpm_width = 24,
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.lpm_widthu = 1,
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.overflow_checking = "ON",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.underflow_checking = "ON",
+           q_sys_sgdma_rx_status_token_fifo_status_token_fifo.use_eab = "ON";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_rx (
+                        // inputs:
+                         clk,
+                         csr_address,
+                         csr_chipselect,
+                         csr_read,
+                         csr_write,
+                         csr_writedata,
+                         descriptor_read_readdata,
+                         descriptor_read_readdatavalid,
+                         descriptor_read_waitrequest,
+                         descriptor_write_waitrequest,
+                         in_data,
+                         in_empty,
+                         in_endofpacket,
+                         in_error,
+                         in_startofpacket,
+                         in_valid,
+                         m_write_waitrequest,
+                         system_reset_n,
+
+                        // outputs:
+                         csr_irq,
+                         csr_readdata,
+                         descriptor_read_address,
+                         descriptor_read_read,
+                         descriptor_write_address,
+                         descriptor_write_write,
+                         descriptor_write_writedata,
+                         in_ready,
+                         m_write_address,
+                         m_write_byteenable,
+                         m_write_write,
+                         m_write_writedata
+                      )
+;
+
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output           in_ready;
+  output  [ 31: 0] m_write_address;
+  output  [  3: 0] m_write_byteenable;
+  output           m_write_write;
+  output  [ 31: 0] m_write_writedata;
+  input            clk;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            descriptor_write_waitrequest;
+  input   [ 31: 0] in_data;
+  input   [  1: 0] in_empty;
+  input            in_endofpacket;
+  input   [  5: 0] in_error;
+  input            in_startofpacket;
+  input            in_valid;
+  input            m_write_waitrequest;
+  input            system_reset_n;
+
+
+wire    [103: 0] command_fifo_data;
+wire             command_fifo_empty;
+wire             command_fifo_full;
+wire    [103: 0] command_fifo_q;
+wire             command_fifo_rdreq;
+wire             command_fifo_wrreq;
+wire             csr_irq;
+wire    [ 31: 0] csr_readdata;
+wire    [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_empty;
+wire             desc_address_fifo_full;
+wire    [ 31: 0] desc_address_fifo_q;
+wire             desc_address_fifo_rdreq;
+wire             desc_address_fifo_wrreq;
+wire    [ 31: 0] descriptor_read_address;
+wire             descriptor_read_read;
+wire    [ 31: 0] descriptor_write_address;
+wire             descriptor_write_write;
+wire    [ 31: 0] descriptor_write_writedata;
+wire             generate_eop;
+wire             in_ready;
+wire    [ 31: 0] m_write_address;
+wire    [  3: 0] m_write_byteenable;
+wire             m_write_write;
+wire    [ 31: 0] m_write_writedata;
+wire             reset;
+reg              reset_n;
+wire    [ 31: 0] sink_stream_data;
+wire    [  1: 0] sink_stream_empty;
+wire             sink_stream_endofpacket;
+wire    [  5: 0] sink_stream_error;
+wire             sink_stream_ready;
+wire             sink_stream_startofpacket;
+wire             sink_stream_valid;
+wire    [ 23: 0] status_token_fifo_data;
+wire             status_token_fifo_empty;
+wire             status_token_fifo_full;
+wire    [ 23: 0] status_token_fifo_q;
+wire             status_token_fifo_rdreq;
+wire             status_token_fifo_wrreq;
+wire             sw_reset;
+reg              sw_reset_d1;
+reg              sw_reset_request;
+wire    [ 56: 0] write_command_data;
+wire             write_command_valid;
+wire             write_go;
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          reset_n <= 0;
+      else 
+        reset_n <= ~(~system_reset_n | sw_reset_request);
+    end
+
+
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          sw_reset_d1 <= 0;
+      else if (sw_reset | sw_reset_request)
+          sw_reset_d1 <= sw_reset & ~sw_reset_request;
+    end
+
+
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          sw_reset_request <= 0;
+      else if (sw_reset | sw_reset_request)
+          sw_reset_request <= sw_reset_d1 & ~sw_reset_request;
+    end
+
+
+  assign reset = ~reset_n;
+  q_sys_sgdma_rx_chain the_q_sys_sgdma_rx_chain
+    (
+      .clk                           (clk),
+      .command_fifo_data             (command_fifo_data),
+      .command_fifo_empty            (command_fifo_empty),
+      .command_fifo_full             (command_fifo_full),
+      .command_fifo_wrreq            (command_fifo_wrreq),
+      .csr_address                   (csr_address),
+      .csr_chipselect                (csr_chipselect),
+      .csr_irq                       (csr_irq),
+      .csr_read                      (csr_read),
+      .csr_readdata                  (csr_readdata),
+      .csr_write                     (csr_write),
+      .csr_writedata                 (csr_writedata),
+      .desc_address_fifo_data        (desc_address_fifo_data),
+      .desc_address_fifo_empty       (desc_address_fifo_empty),
+      .desc_address_fifo_full        (desc_address_fifo_full),
+      .desc_address_fifo_q           (desc_address_fifo_q),
+      .desc_address_fifo_rdreq       (desc_address_fifo_rdreq),
+      .desc_address_fifo_wrreq       (desc_address_fifo_wrreq),
+      .descriptor_read_address       (descriptor_read_address),
+      .descriptor_read_read          (descriptor_read_read),
+      .descriptor_read_readdata      (descriptor_read_readdata),
+      .descriptor_read_readdatavalid (descriptor_read_readdatavalid),
+      .descriptor_read_waitrequest   (descriptor_read_waitrequest & descriptor_read_read),
+      .descriptor_write_address      (descriptor_write_address),
+      .descriptor_write_waitrequest  (descriptor_write_waitrequest & descriptor_write_write),
+      .descriptor_write_write        (descriptor_write_write),
+      .descriptor_write_writedata    (descriptor_write_writedata),
+      .reset                         (reset),
+      .reset_n                       (reset_n),
+      .status_token_fifo_data        (status_token_fifo_data),
+      .status_token_fifo_empty       (status_token_fifo_empty),
+      .status_token_fifo_q           (status_token_fifo_q),
+      .status_token_fifo_rdreq       (status_token_fifo_rdreq),
+      .sw_reset                      (sw_reset),
+      .write_go                      (write_go)
+    );
+
+  q_sys_sgdma_rx_command_grabber the_q_sys_sgdma_rx_command_grabber
+    (
+      .clk                 (clk),
+      .command_fifo_empty  (command_fifo_empty),
+      .command_fifo_q      (command_fifo_q),
+      .command_fifo_rdreq  (command_fifo_rdreq),
+      .generate_eop        (generate_eop),
+      .m_write_waitrequest (m_write_waitrequest & m_write_write),
+      .reset_n             (reset_n),
+      .write_command_data  (write_command_data),
+      .write_command_valid (write_command_valid),
+      .write_go            (write_go)
+    );
+
+  q_sys_sgdma_rx_m_write the_q_sys_sgdma_rx_m_write
+    (
+      .clk                       (clk),
+      .enough_data               (1'b1),
+      .eop_found                 (1'b0),
+      .m_write_address           (m_write_address),
+      .m_write_byteenable        (m_write_byteenable),
+      .m_write_waitrequest       (m_write_waitrequest & m_write_write),
+      .m_write_write             (m_write_write),
+      .m_write_writedata         (m_write_writedata),
+      .reset_n                   (reset_n),
+      .sink_stream_data          (sink_stream_data),
+      .sink_stream_empty         (sink_stream_empty),
+      .sink_stream_endofpacket   (sink_stream_endofpacket),
+      .sink_stream_error         (sink_stream_error),
+      .sink_stream_ready         (sink_stream_ready),
+      .sink_stream_startofpacket (sink_stream_startofpacket),
+      .sink_stream_valid         (sink_stream_valid),
+      .status_token_fifo_data    (status_token_fifo_data),
+      .status_token_fifo_full    (status_token_fifo_full),
+      .status_token_fifo_wrreq   (status_token_fifo_wrreq),
+      .write_command_data        (write_command_data),
+      .write_command_valid       (write_command_valid),
+      .write_go                  (write_go)
+    );
+
+  //the_q_sys_sgdma_rx_command_fifo, which is an e_instance
+  q_sys_sgdma_rx_command_fifo the_q_sys_sgdma_rx_command_fifo
+    (
+      .clk                (clk),
+      .command_fifo_data  (command_fifo_data),
+      .command_fifo_empty (command_fifo_empty),
+      .command_fifo_full  (command_fifo_full),
+      .command_fifo_q     (command_fifo_q),
+      .command_fifo_rdreq (command_fifo_rdreq),
+      .command_fifo_wrreq (command_fifo_wrreq),
+      .reset              (reset)
+    );
+
+  //the_q_sys_sgdma_rx_desc_address_fifo, which is an e_instance
+  q_sys_sgdma_rx_desc_address_fifo the_q_sys_sgdma_rx_desc_address_fifo
+    (
+      .clk                     (clk),
+      .desc_address_fifo_data  (desc_address_fifo_data),
+      .desc_address_fifo_empty (desc_address_fifo_empty),
+      .desc_address_fifo_full  (desc_address_fifo_full),
+      .desc_address_fifo_q     (desc_address_fifo_q),
+      .desc_address_fifo_rdreq (desc_address_fifo_rdreq),
+      .desc_address_fifo_wrreq (desc_address_fifo_wrreq),
+      .reset                   (reset)
+    );
+
+  //the_q_sys_sgdma_rx_status_token_fifo, which is an e_instance
+  q_sys_sgdma_rx_status_token_fifo the_q_sys_sgdma_rx_status_token_fifo
+    (
+      .clk                     (clk),
+      .reset                   (reset),
+      .status_token_fifo_data  (status_token_fifo_data),
+      .status_token_fifo_empty (status_token_fifo_empty),
+      .status_token_fifo_full  (status_token_fifo_full),
+      .status_token_fifo_q     (status_token_fifo_q),
+      .status_token_fifo_rdreq (status_token_fifo_rdreq),
+      .status_token_fifo_wrreq (status_token_fifo_wrreq)
+    );
+
+  //descriptor_read, which is an e_avalon_master
+  //descriptor_write, which is an e_avalon_master
+  //csr, which is an e_avalon_slave
+  //m_write, which is an e_avalon_master
+  assign sink_stream_empty = in_empty;
+  assign sink_stream_error = sink_stream_valid ? in_error : 0;
+  //in, which is an e_atlantic_slave
+  assign sink_stream_endofpacket = in_endofpacket;
+  assign sink_stream_startofpacket = in_startofpacket;
+  assign sink_stream_valid = in_valid;
+  assign in_ready = sink_stream_ready;
+  assign sink_stream_data = {in_data[7 : 0], in_data[15 : 8], in_data[23 : 16], in_data[31 : 24]};
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_tx.v
new file mode 100644
index 0000000..3080686
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sgdma_tx.v
@@ -0,0 +1,2339 @@
+//Legal Notice: (C)2019 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module control_status_slave_which_resides_within_q_sys_sgdma_tx (
+                                                                  // inputs:
+                                                                   atlantic_error,
+                                                                   chain_run,
+                                                                   clk,
+                                                                   command_fifo_empty,
+                                                                   csr_address,
+                                                                   csr_chipselect,
+                                                                   csr_read,
+                                                                   csr_write,
+                                                                   csr_writedata,
+                                                                   desc_address_fifo_empty,
+                                                                   descriptor_read_address,
+                                                                   descriptor_read_read,
+                                                                   descriptor_write_busy,
+                                                                   descriptor_write_write,
+                                                                   owned_by_hw,
+                                                                   read_go,
+                                                                   reset_n,
+                                                                   status_token_fifo_empty,
+                                                                   status_token_fifo_rdreq,
+
+                                                                  // outputs:
+                                                                   csr_irq,
+                                                                   csr_readdata,
+                                                                   descriptor_pointer_lower_reg_out,
+                                                                   descriptor_pointer_upper_reg_out,
+                                                                   park,
+                                                                   pollen_clear_run,
+                                                                   run,
+                                                                   sw_reset
+                                                                )
+;
+
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] descriptor_pointer_lower_reg_out;
+  output  [ 31: 0] descriptor_pointer_upper_reg_out;
+  output           park;
+  output           pollen_clear_run;
+  output           run;
+  output           sw_reset;
+  input            atlantic_error;
+  input            chain_run;
+  input            clk;
+  input            command_fifo_empty;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input            desc_address_fifo_empty;
+  input   [ 31: 0] descriptor_read_address;
+  input            descriptor_read_read;
+  input            descriptor_write_busy;
+  input            descriptor_write_write;
+  input            owned_by_hw;
+  input            read_go;
+  input            reset_n;
+  input            status_token_fifo_empty;
+  input            status_token_fifo_rdreq;
+
+
+reg              busy;
+reg              can_have_new_chain_complete;
+reg              chain_completed;
+reg              chain_completed_int;
+wire             chain_completed_int_rise;
+wire             clear_chain_completed;
+wire             clear_descriptor_completed;
+wire             clear_error;
+reg              clear_interrupt;
+wire             clear_run;
+reg     [ 31: 0] control_reg;
+wire             control_reg_en;
+wire             csr_control;
+reg              csr_irq;
+reg     [ 31: 0] csr_readdata;
+wire             csr_status;
+reg              delayed_chain_completed_int;
+reg              delayed_csr_write;
+reg     [  7: 0] delayed_descriptor_counter;
+reg              delayed_descriptor_write_write;
+reg              delayed_eop_encountered;
+wire    [  7: 0] delayed_max_desc_processed;
+reg              delayed_run;
+reg              descriptor_completed;
+reg     [  7: 0] descriptor_counter;
+wire    [ 31: 0] descriptor_pointer_data;
+reg     [ 31: 0] descriptor_pointer_lower_reg;
+wire             descriptor_pointer_lower_reg_en;
+wire    [ 31: 0] descriptor_pointer_lower_reg_out;
+reg     [ 31: 0] descriptor_pointer_upper_reg;
+wire             descriptor_pointer_upper_reg_en;
+wire    [ 31: 0] descriptor_pointer_upper_reg_out;
+reg              descriptor_read_read_r;
+wire             descriptor_read_read_rising;
+wire             descriptor_write_write_fall;
+reg              do_restart;
+reg              do_restart_compare;
+wire             eop_encountered;
+wire             eop_encountered_rise;
+reg              error;
+wire    [  3: 0] hw_version;
+wire             ie_chain_completed;
+wire             ie_descriptor_completed;
+wire             ie_eop_encountered;
+wire             ie_error;
+wire             ie_global;
+wire             ie_max_desc_processed;
+wire    [  7: 0] max_desc_processed;
+wire             park;
+wire             poll_en;
+wire             pollen_clear_run;
+wire             run;
+wire    [ 31: 0] status_reg;
+wire             stop_dma_error;
+wire             sw_reset;
+reg     [ 15: 0] timeout_counter;
+wire    [ 10: 0] timeout_reg;
+wire             version_reg;
+  //csr, which is an e_avalon_slave
+  //Control Status Register (Readdata)
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          csr_readdata <= 0;
+      else if (csr_read)
+          case (csr_address) // synthesis parallel_case
+          
+              {4'b0000}: begin
+                  csr_readdata <= status_reg;
+              end // {4'b0000} 
+          
+              {4'b0001}: begin
+                  csr_readdata <= version_reg;
+              end // {4'b0001} 
+          
+              {4'b0100}: begin
+                  csr_readdata <= control_reg;
+              end // {4'b0100} 
+          
+              {4'b1000}: begin
+                  csr_readdata <= descriptor_pointer_lower_reg;
+              end // {4'b1000} 
+          
+              {4'b1100}: begin
+                  csr_readdata <= descriptor_pointer_upper_reg;
+              end // {4'b1100} 
+          
+              default: begin
+                  csr_readdata <= 32'b0;
+              end // default
+          
+          endcase // csr_address
+    end
+
+
+  //register outs
+  assign descriptor_pointer_upper_reg_out = descriptor_pointer_upper_reg;
+  assign descriptor_pointer_lower_reg_out = descriptor_pointer_lower_reg;
+  //control register bits
+  assign ie_error = control_reg[0];
+  assign ie_eop_encountered = control_reg[1];
+  assign ie_descriptor_completed = control_reg[2];
+  assign ie_chain_completed = control_reg[3];
+  assign ie_global = control_reg[4];
+  assign run = control_reg[5] && (!(stop_dma_error && error) && ((!chain_completed_int ) ||( do_restart && poll_en && chain_completed_int)));
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_run <= 0;
+      else 
+        delayed_run <= run;
+    end
+
+
+  assign stop_dma_error = control_reg[6];
+  assign ie_max_desc_processed = control_reg[7];
+  assign max_desc_processed = control_reg[15 : 8];
+  assign sw_reset = control_reg[16];
+  assign park = control_reg[17];
+  assign poll_en = control_reg[18];
+  assign timeout_reg = control_reg[30 : 20];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          timeout_counter <= 0;
+      else if ((control_reg[5] && !busy && poll_en )|| do_restart)
+          timeout_counter <= do_restart ? 0:(timeout_counter + 1'b1);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_restart_compare <= 0;
+      else 
+        do_restart_compare <= timeout_counter == {timeout_reg,5'b11111};
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          do_restart <= 0;
+      else 
+        do_restart <= poll_en && do_restart_compare;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          clear_interrupt <= 0;
+      else 
+        clear_interrupt <= control_reg_en ? csr_writedata[31] : 0;
+    end
+
+
+  //control register
+  assign control_reg_en = (csr_address == { 4'b0100}) && csr_write && csr_chipselect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          control_reg <= 0;
+      else if (control_reg_en)
+          control_reg <= {1'b0, csr_writedata[30 : 0]};
+    end
+
+
+  //descriptor_pointer_upper_reg
+  assign descriptor_pointer_upper_reg_en = (csr_address == { 4'b1100}) && csr_write && csr_chipselect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_pointer_upper_reg <= 0;
+      else if (descriptor_pointer_upper_reg_en)
+          descriptor_pointer_upper_reg <= csr_writedata;
+    end
+
+
+  //section to update the descriptor pointer
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_read_r <= 0;
+      else 
+        descriptor_read_read_r <= descriptor_read_read;
+    end
+
+
+  assign descriptor_read_read_rising = descriptor_read_read && !descriptor_read_read_r;
+  assign descriptor_pointer_data = descriptor_read_read_rising ? descriptor_read_address:csr_writedata;
+  //descriptor_pointer_lower_reg
+  assign descriptor_pointer_lower_reg_en = ((csr_address == { 4'b1000}) && csr_write && csr_chipselect) || (poll_en && descriptor_read_read_rising);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_pointer_lower_reg <= 0;
+      else if (descriptor_pointer_lower_reg_en)
+          descriptor_pointer_lower_reg <= descriptor_pointer_data;
+    end
+
+
+  //Hardware Version Register
+  assign hw_version = 4'b0001;
+  assign version_reg = {24'h000000, hw_version};
+  //status register
+  assign status_reg = {27'b0, busy, chain_completed, descriptor_completed, eop_encountered, error};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          busy <= 0;
+      else 
+        busy <= ~command_fifo_empty || ~status_token_fifo_empty || ~desc_address_fifo_empty || chain_run || descriptor_write_busy || delayed_csr_write || owned_by_hw || read_go;
+    end
+
+
+  //Chain Completed Status Register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_completed <= 0;
+      else if ((run && ~owned_by_hw && ~busy) || clear_chain_completed || do_restart)
+          chain_completed <= (clear_chain_completed || do_restart)? 1'b0 : ~delayed_csr_write;
+    end
+
+
+  //chain_completed_int is the internal chain completed state for SGDMA.
+  //Will not be affected with clearing of chain_completed Status Register,to prevent SGDMA being restarted when the status bit is cleared
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_completed_int <= 0;
+      else if ((run && ~owned_by_hw && ~busy) || clear_run || do_restart)
+          chain_completed_int <= (clear_run || do_restart) ? 1'b0 : ~delayed_csr_write;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_csr_write <= 0;
+      else 
+        delayed_csr_write <= csr_write;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_completed <= 0;
+      else if (descriptor_write_write_fall || clear_descriptor_completed)
+          descriptor_completed <= ~clear_descriptor_completed;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          error <= 0;
+      else if (atlantic_error || clear_error)
+          error <= ~clear_error;
+    end
+
+
+  assign csr_status = csr_write && csr_chipselect && (csr_address == 4'b0);
+  assign clear_chain_completed = csr_writedata[3] && csr_status;
+  assign clear_descriptor_completed = csr_writedata[2] && csr_status;
+  assign clear_error = csr_writedata[0] && csr_status;
+  assign csr_control = csr_write && csr_chipselect && (csr_address == 4'h4);
+  assign clear_run = !csr_writedata[5] && csr_control;
+  assign pollen_clear_run = poll_en & clear_run;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_eop_encountered <= 0;
+      else 
+        delayed_eop_encountered <= eop_encountered;
+    end
+
+
+  assign eop_encountered_rise = ~delayed_eop_encountered && eop_encountered;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_descriptor_write_write <= 0;
+      else 
+        delayed_descriptor_write_write <= descriptor_write_write;
+    end
+
+
+  assign descriptor_write_write_fall = delayed_descriptor_write_write && ~descriptor_write_write;
+  assign eop_encountered = 1'b0;
+  //chain_completed rising edge detector
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_chain_completed_int <= 0;
+      else 
+        delayed_chain_completed_int <= chain_completed_int;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          can_have_new_chain_complete <= 0;
+      else if (descriptor_write_write || (~delayed_chain_completed_int && chain_completed_int))
+          can_have_new_chain_complete <= descriptor_write_write;
+    end
+
+
+  assign chain_completed_int_rise = ~delayed_chain_completed_int && chain_completed_int && can_have_new_chain_complete;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_counter <= 0;
+      else if (status_token_fifo_rdreq)
+          descriptor_counter <= descriptor_counter + 1'b1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_descriptor_counter <= 0;
+      else 
+        delayed_descriptor_counter <= descriptor_counter;
+    end
+
+
+  assign delayed_max_desc_processed = max_desc_processed - 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          csr_irq <= 0;
+      else 
+        csr_irq <= csr_irq ? ~clear_interrupt : (delayed_run && ie_global && ((ie_error && error) || (ie_eop_encountered && eop_encountered_rise) || (ie_descriptor_completed && descriptor_write_write_fall) || (ie_chain_completed && chain_completed_int_rise) || (ie_max_desc_processed && (descriptor_counter == max_desc_processed) && (delayed_descriptor_counter == delayed_max_desc_processed) )));
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo (
+                                                                               // inputs:
+                                                                                clk,
+                                                                                controlbitsfifo_data,
+                                                                                controlbitsfifo_rdreq,
+                                                                                controlbitsfifo_wrreq,
+                                                                                reset,
+
+                                                                               // outputs:
+                                                                                controlbitsfifo_empty,
+                                                                                controlbitsfifo_full,
+                                                                                controlbitsfifo_q
+                                                                             )
+;
+
+  output           controlbitsfifo_empty;
+  output           controlbitsfifo_full;
+  output  [  6: 0] controlbitsfifo_q;
+  input            clk;
+  input   [  6: 0] controlbitsfifo_data;
+  input            controlbitsfifo_rdreq;
+  input            controlbitsfifo_wrreq;
+  input            reset;
+
+
+wire             controlbitsfifo_empty;
+wire             controlbitsfifo_full;
+wire    [  6: 0] controlbitsfifo_q;
+  scfifo descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (controlbitsfifo_data),
+      .empty (controlbitsfifo_empty),
+      .full (controlbitsfifo_full),
+      .q (controlbitsfifo_q),
+      .rdreq (controlbitsfifo_rdreq),
+      .wrreq (controlbitsfifo_wrreq)
+    );
+
+  defparam descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.add_ram_output_register = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.intended_device_family = "MAX10",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.lpm_numwords = 2,
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.lpm_showahead = "OFF",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.lpm_type = "scfifo",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.lpm_width = 7,
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.lpm_widthu = 1,
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.overflow_checking = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.underflow_checking = "ON",
+           descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo_controlbitsfifo.use_eab = "OFF";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_read_which_resides_within_q_sys_sgdma_tx (
+                                                             // inputs:
+                                                              clk,
+                                                              command_fifo_full,
+                                                              controlbitsfifo_rdreq,
+                                                              desc_address_fifo_full,
+                                                              descriptor_pointer_lower_reg_out,
+                                                              descriptor_pointer_upper_reg_out,
+                                                              descriptor_read_readdata,
+                                                              descriptor_read_readdatavalid,
+                                                              descriptor_read_waitrequest,
+                                                              pollen_clear_run,
+                                                              reset,
+                                                              reset_n,
+                                                              run,
+
+                                                             // outputs:
+                                                              atlantic_channel,
+                                                              chain_run,
+                                                              command_fifo_data,
+                                                              command_fifo_wrreq,
+                                                              control,
+                                                              controlbitsfifo_q,
+                                                              desc_address_fifo_data,
+                                                              desc_address_fifo_wrreq,
+                                                              descriptor_read_address,
+                                                              descriptor_read_read,
+                                                              generate_eop,
+                                                              next_desc,
+                                                              owned_by_hw,
+                                                              read_fixed_address,
+                                                              write_fixed_address
+                                                           )
+;
+
+  output  [  3: 0] atlantic_channel;
+  output           chain_run;
+  output  [103: 0] command_fifo_data;
+  output           command_fifo_wrreq;
+  output  [  7: 0] control;
+  output  [  6: 0] controlbitsfifo_q;
+  output  [ 31: 0] desc_address_fifo_data;
+  output           desc_address_fifo_wrreq;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output           generate_eop;
+  output  [ 31: 0] next_desc;
+  output           owned_by_hw;
+  output           read_fixed_address;
+  output           write_fixed_address;
+  input            clk;
+  input            command_fifo_full;
+  input            controlbitsfifo_rdreq;
+  input            desc_address_fifo_full;
+  input   [ 31: 0] descriptor_pointer_lower_reg_out;
+  input   [ 31: 0] descriptor_pointer_upper_reg_out;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            pollen_clear_run;
+  input            reset;
+  input            reset_n;
+  input            run;
+
+
+wire    [  3: 0] atlantic_channel;
+wire    [ 15: 0] bytes_to_transfer;
+reg              chain_run;
+wire    [103: 0] command_fifo_data;
+reg              command_fifo_wrreq;
+wire             command_fifo_wrreq_in;
+wire    [  7: 0] control;
+wire    [  6: 0] controlbitsfifo_data;
+wire             controlbitsfifo_empty;
+wire             controlbitsfifo_full;
+wire    [  6: 0] controlbitsfifo_q;
+wire             controlbitsfifo_wrreq;
+reg              delayed_desc_reg_en;
+reg              delayed_run;
+reg     [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_wrreq;
+reg     [255: 0] desc_assembler;
+reg              desc_read_start;
+reg     [255: 0] desc_reg;
+wire             desc_reg_en;
+reg     [ 31: 0] descriptor_read_address;
+reg              descriptor_read_completed;
+wire             descriptor_read_completed_in;
+reg              descriptor_read_read;
+wire             fifos_not_full;
+wire             generate_eop;
+wire             got_one_descriptor;
+wire    [255: 0] init_descriptor;
+wire    [ 31: 0] next_desc;
+wire             owned_by_hw;
+wire    [255: 0] pollen_clear_run_desc;
+reg     [  3: 0] posted_desc_counter;
+reg              posted_read_queued;
+wire    [ 31: 0] read_address;
+wire    [  7: 0] read_burst;
+wire             read_fixed_address;
+reg     [  3: 0] received_desc_counter;
+reg              run_rising_edge;
+wire             run_rising_edge_in;
+reg              started;
+wire             started_in;
+wire    [ 31: 0] write_address;
+wire    [  7: 0] write_burst;
+wire             write_fixed_address;
+  //descriptor_read, which is an e_avalon_master
+  //Control assignments
+  assign command_fifo_wrreq_in = chain_run && fifos_not_full && delayed_desc_reg_en && owned_by_hw;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_fifo_wrreq <= 0;
+      else 
+        command_fifo_wrreq <= command_fifo_wrreq_in;
+    end
+
+
+  assign desc_address_fifo_wrreq = command_fifo_wrreq;
+  assign fifos_not_full = ~command_fifo_full && ~desc_address_fifo_full;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_desc_reg_en <= 0;
+      else 
+        delayed_desc_reg_en <= desc_reg_en;
+    end
+
+
+  assign read_address = desc_reg[31 : 0];
+  assign write_address = desc_reg[95 : 64];
+  assign next_desc = desc_reg[159 : 128];
+  assign bytes_to_transfer = desc_reg[207 : 192];
+  assign read_burst = desc_reg[215 : 208];
+  assign write_burst = desc_reg[223 : 216];
+  assign control = desc_reg[255 : 248];
+  assign command_fifo_data = {control, write_burst, read_burst, bytes_to_transfer, write_address, read_address};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_address_fifo_data <= 0;
+      else if (desc_reg_en)
+          desc_address_fifo_data <= next_desc;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          received_desc_counter <= 0;
+      else 
+        received_desc_counter <= (received_desc_counter == 8)? 0 : (descriptor_read_readdatavalid ? (received_desc_counter + 1) : received_desc_counter);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          posted_desc_counter <= 0;
+      else 
+        posted_desc_counter <= (desc_read_start & owned_by_hw & (posted_desc_counter != 8)) ? 8 : ((|posted_desc_counter & ~descriptor_read_waitrequest & fifos_not_full) ? (posted_desc_counter - 1) : posted_desc_counter);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_read_start <= 0;
+      else if (~descriptor_read_waitrequest)
+          desc_read_start <= desc_read_start ? 0 : ((~(desc_reg_en | delayed_desc_reg_en | command_fifo_wrreq | |received_desc_counter)) ? (chain_run & fifos_not_full & ~|posted_desc_counter & ~posted_read_queued) : 0);
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          chain_run <= 0;
+      else 
+        chain_run <= (run && owned_by_hw | (delayed_desc_reg_en | desc_reg_en) | |posted_desc_counter | |received_desc_counter) || run_rising_edge_in;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_read <= 0;
+      else if (~descriptor_read_waitrequest)
+          descriptor_read_read <= |posted_desc_counter & fifos_not_full;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_address <= 0;
+      else if (~descriptor_read_waitrequest)
+          descriptor_read_address <= (descriptor_read_read)? (descriptor_read_address + 4) : next_desc;
+    end
+
+
+  assign descriptor_read_completed_in = started ? (run && ~owned_by_hw && ~|posted_desc_counter) : descriptor_read_completed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          posted_read_queued <= 0;
+      else 
+        posted_read_queued <= posted_read_queued ? ~(got_one_descriptor) : (descriptor_read_read);
+    end
+
+
+  //control bits
+  assign generate_eop = control[0];
+  assign read_fixed_address = control[1];
+  assign write_fixed_address = control[2];
+  assign atlantic_channel = control[6 : 3];
+  assign owned_by_hw = control[7];
+  assign got_one_descriptor = received_desc_counter == 8;
+  //read descriptor
+  assign desc_reg_en = chain_run && got_one_descriptor;
+  assign init_descriptor = {1'b1, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
+  //Clear owned_by_hw bit when run is clear in Descriptor Polling Mode
+  assign pollen_clear_run_desc = {1'b0, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_reg <= 0;
+      else if (desc_reg_en || run_rising_edge_in || pollen_clear_run)
+          desc_reg <= run_rising_edge_in ? init_descriptor : pollen_clear_run ? pollen_clear_run_desc: desc_assembler;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          desc_assembler <= 0;
+      else if (descriptor_read_readdatavalid)
+          desc_assembler <= desc_assembler >> 32 | {descriptor_read_readdata, 224'b0};
+    end
+
+
+  //descriptor_read_completed register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_read_completed <= 0;
+      else 
+        descriptor_read_completed <= descriptor_read_completed_in;
+    end
+
+
+  //started register
+  assign started_in = (run_rising_edge || run_rising_edge_in) ? 1'b1 : (descriptor_read_completed ? 1'b0 : started);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          started <= 0;
+      else 
+        started <= started_in;
+    end
+
+
+  //delayed_run signal for the rising edge detector
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_run <= 0;
+      else 
+        delayed_run <= run;
+    end
+
+
+  //Run rising edge detector
+  assign run_rising_edge_in = run & ~delayed_run;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          run_rising_edge <= 0;
+      else if (run_rising_edge_in || desc_reg_en)
+          run_rising_edge <= run_rising_edge_in;
+    end
+
+
+  //the_descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo, which is an e_instance
+  descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo the_descriptor_read_which_resides_within_q_sys_sgdma_tx_control_bits_fifo
+    (
+      .clk                   (clk),
+      .controlbitsfifo_data  (controlbitsfifo_data),
+      .controlbitsfifo_empty (controlbitsfifo_empty),
+      .controlbitsfifo_full  (controlbitsfifo_full),
+      .controlbitsfifo_q     (controlbitsfifo_q),
+      .controlbitsfifo_rdreq (controlbitsfifo_rdreq),
+      .controlbitsfifo_wrreq (controlbitsfifo_wrreq),
+      .reset                 (reset)
+    );
+
+  assign controlbitsfifo_data = control[6 : 0];
+  assign controlbitsfifo_wrreq = command_fifo_wrreq;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module descriptor_write_which_resides_within_q_sys_sgdma_tx (
+                                                              // inputs:
+                                                               clk,
+                                                               controlbitsfifo_q,
+                                                               desc_address_fifo_empty,
+                                                               desc_address_fifo_q,
+                                                               descriptor_write_waitrequest,
+                                                               park,
+                                                               reset_n,
+                                                               status_token_fifo_data,
+                                                               status_token_fifo_empty,
+                                                               status_token_fifo_q,
+
+                                                              // outputs:
+                                                               atlantic_error,
+                                                               controlbitsfifo_rdreq,
+                                                               desc_address_fifo_rdreq,
+                                                               descriptor_write_address,
+                                                               descriptor_write_busy,
+                                                               descriptor_write_write,
+                                                               descriptor_write_writedata,
+                                                               status_token_fifo_rdreq,
+                                                               t_eop
+                                                            )
+;
+
+  output           atlantic_error;
+  output           controlbitsfifo_rdreq;
+  output           desc_address_fifo_rdreq;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_busy;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output           status_token_fifo_rdreq;
+  output           t_eop;
+  input            clk;
+  input   [  6: 0] controlbitsfifo_q;
+  input            desc_address_fifo_empty;
+  input   [ 31: 0] desc_address_fifo_q;
+  input            descriptor_write_waitrequest;
+  input            park;
+  input            reset_n;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_empty;
+  input   [ 23: 0] status_token_fifo_q;
+
+
+wire             atlantic_error;
+wire             can_write;
+wire             controlbitsfifo_rdreq;
+wire             desc_address_fifo_rdreq;
+reg     [ 31: 0] descriptor_write_address;
+wire             descriptor_write_busy;
+reg              descriptor_write_write;
+reg              descriptor_write_write0;
+reg     [ 31: 0] descriptor_write_writedata;
+wire             fifos_not_empty;
+wire    [  7: 0] status_reg;
+reg              status_token_fifo_rdreq;
+wire             status_token_fifo_rdreq_in;
+wire             t_eop;
+  //descriptor_write, which is an e_avalon_master
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_writedata <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_writedata <= {park, controlbitsfifo_q, status_token_fifo_q};
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_address <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_address <= desc_address_fifo_q + 28;
+    end
+
+
+  assign fifos_not_empty = ~status_token_fifo_empty && ~desc_address_fifo_empty;
+  assign can_write = ~descriptor_write_waitrequest && fifos_not_empty;
+  //write register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_write0 <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_write0 <= status_token_fifo_rdreq;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          descriptor_write_write <= 0;
+      else if (~descriptor_write_waitrequest)
+          descriptor_write_write <= descriptor_write_write0;
+    end
+
+
+  //status_token_fifo_rdreq register
+  assign status_token_fifo_rdreq_in = status_token_fifo_rdreq ? 1'b0 : can_write;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          status_token_fifo_rdreq <= 0;
+      else 
+        status_token_fifo_rdreq <= status_token_fifo_rdreq_in;
+    end
+
+
+  assign desc_address_fifo_rdreq = status_token_fifo_rdreq;
+  assign descriptor_write_busy = descriptor_write_write0 | descriptor_write_write;
+  assign status_reg = status_token_fifo_data[23 : 16];
+  assign t_eop = status_reg[7];
+  assign atlantic_error = status_reg[6] | status_reg[5] | status_reg[4] | status_reg[3] | status_reg[2] | status_reg[1] | status_reg[0];
+  assign controlbitsfifo_rdreq = status_token_fifo_rdreq;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_chain (
+                              // inputs:
+                               clk,
+                               command_fifo_empty,
+                               command_fifo_full,
+                               csr_address,
+                               csr_chipselect,
+                               csr_read,
+                               csr_write,
+                               csr_writedata,
+                               desc_address_fifo_empty,
+                               desc_address_fifo_full,
+                               desc_address_fifo_q,
+                               descriptor_read_readdata,
+                               descriptor_read_readdatavalid,
+                               descriptor_read_waitrequest,
+                               descriptor_write_waitrequest,
+                               read_go,
+                               reset,
+                               reset_n,
+                               status_token_fifo_data,
+                               status_token_fifo_empty,
+                               status_token_fifo_q,
+
+                              // outputs:
+                               command_fifo_data,
+                               command_fifo_wrreq,
+                               csr_irq,
+                               csr_readdata,
+                               desc_address_fifo_data,
+                               desc_address_fifo_rdreq,
+                               desc_address_fifo_wrreq,
+                               descriptor_read_address,
+                               descriptor_read_read,
+                               descriptor_write_address,
+                               descriptor_write_write,
+                               descriptor_write_writedata,
+                               status_token_fifo_rdreq,
+                               sw_reset
+                            )
+;
+
+  output  [103: 0] command_fifo_data;
+  output           command_fifo_wrreq;
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] desc_address_fifo_data;
+  output           desc_address_fifo_rdreq;
+  output           desc_address_fifo_wrreq;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output           status_token_fifo_rdreq;
+  output           sw_reset;
+  input            clk;
+  input            command_fifo_empty;
+  input            command_fifo_full;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input            desc_address_fifo_empty;
+  input            desc_address_fifo_full;
+  input   [ 31: 0] desc_address_fifo_q;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            descriptor_write_waitrequest;
+  input            read_go;
+  input            reset;
+  input            reset_n;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_empty;
+  input   [ 23: 0] status_token_fifo_q;
+
+
+wire    [  3: 0] atlantic_channel;
+wire             atlantic_error;
+wire             chain_run;
+wire    [103: 0] command_fifo_data;
+wire             command_fifo_wrreq;
+wire    [  7: 0] control;
+wire    [  6: 0] controlbitsfifo_q;
+wire             controlbitsfifo_rdreq;
+wire             csr_irq;
+wire    [ 31: 0] csr_readdata;
+wire    [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_rdreq;
+wire             desc_address_fifo_wrreq;
+wire    [ 31: 0] descriptor_pointer_lower_reg_out;
+wire    [ 31: 0] descriptor_pointer_upper_reg_out;
+wire    [ 31: 0] descriptor_read_address;
+wire             descriptor_read_read;
+wire    [ 31: 0] descriptor_write_address;
+wire             descriptor_write_busy;
+wire             descriptor_write_write;
+wire    [ 31: 0] descriptor_write_writedata;
+wire             generate_eop;
+wire    [ 31: 0] next_desc;
+wire             owned_by_hw;
+wire             park;
+wire             pollen_clear_run;
+wire             read_fixed_address;
+wire             run;
+wire             status_token_fifo_rdreq;
+wire             sw_reset;
+wire             t_eop;
+wire             write_fixed_address;
+  control_status_slave_which_resides_within_q_sys_sgdma_tx the_control_status_slave_which_resides_within_q_sys_sgdma_tx
+    (
+      .atlantic_error                   (atlantic_error),
+      .chain_run                        (chain_run),
+      .clk                              (clk),
+      .command_fifo_empty               (command_fifo_empty),
+      .csr_address                      (csr_address),
+      .csr_chipselect                   (csr_chipselect),
+      .csr_irq                          (csr_irq),
+      .csr_read                         (csr_read),
+      .csr_readdata                     (csr_readdata),
+      .csr_write                        (csr_write),
+      .csr_writedata                    (csr_writedata),
+      .desc_address_fifo_empty          (desc_address_fifo_empty),
+      .descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
+      .descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
+      .descriptor_read_address          (descriptor_read_address),
+      .descriptor_read_read             (descriptor_read_read),
+      .descriptor_write_busy            (descriptor_write_busy),
+      .descriptor_write_write           (descriptor_write_write),
+      .owned_by_hw                      (owned_by_hw),
+      .park                             (park),
+      .pollen_clear_run                 (pollen_clear_run),
+      .read_go                          (read_go),
+      .reset_n                          (reset_n),
+      .run                              (run),
+      .status_token_fifo_empty          (status_token_fifo_empty),
+      .status_token_fifo_rdreq          (status_token_fifo_rdreq),
+      .sw_reset                         (sw_reset)
+    );
+
+  descriptor_read_which_resides_within_q_sys_sgdma_tx the_descriptor_read_which_resides_within_q_sys_sgdma_tx
+    (
+      .atlantic_channel                 (atlantic_channel),
+      .chain_run                        (chain_run),
+      .clk                              (clk),
+      .command_fifo_data                (command_fifo_data),
+      .command_fifo_full                (command_fifo_full),
+      .command_fifo_wrreq               (command_fifo_wrreq),
+      .control                          (control),
+      .controlbitsfifo_q                (controlbitsfifo_q),
+      .controlbitsfifo_rdreq            (controlbitsfifo_rdreq),
+      .desc_address_fifo_data           (desc_address_fifo_data),
+      .desc_address_fifo_full           (desc_address_fifo_full),
+      .desc_address_fifo_wrreq          (desc_address_fifo_wrreq),
+      .descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
+      .descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
+      .descriptor_read_address          (descriptor_read_address),
+      .descriptor_read_read             (descriptor_read_read),
+      .descriptor_read_readdata         (descriptor_read_readdata),
+      .descriptor_read_readdatavalid    (descriptor_read_readdatavalid),
+      .descriptor_read_waitrequest      (descriptor_read_waitrequest),
+      .generate_eop                     (generate_eop),
+      .next_desc                        (next_desc),
+      .owned_by_hw                      (owned_by_hw),
+      .pollen_clear_run                 (pollen_clear_run),
+      .read_fixed_address               (read_fixed_address),
+      .reset                            (reset),
+      .reset_n                          (reset_n),
+      .run                              (run),
+      .write_fixed_address              (write_fixed_address)
+    );
+
+  descriptor_write_which_resides_within_q_sys_sgdma_tx the_descriptor_write_which_resides_within_q_sys_sgdma_tx
+    (
+      .atlantic_error               (atlantic_error),
+      .clk                          (clk),
+      .controlbitsfifo_q            (controlbitsfifo_q),
+      .controlbitsfifo_rdreq        (controlbitsfifo_rdreq),
+      .desc_address_fifo_empty      (desc_address_fifo_empty),
+      .desc_address_fifo_q          (desc_address_fifo_q),
+      .desc_address_fifo_rdreq      (desc_address_fifo_rdreq),
+      .descriptor_write_address     (descriptor_write_address),
+      .descriptor_write_busy        (descriptor_write_busy),
+      .descriptor_write_waitrequest (descriptor_write_waitrequest),
+      .descriptor_write_write       (descriptor_write_write),
+      .descriptor_write_writedata   (descriptor_write_writedata),
+      .park                         (park),
+      .reset_n                      (reset_n),
+      .status_token_fifo_data       (status_token_fifo_data),
+      .status_token_fifo_empty      (status_token_fifo_empty),
+      .status_token_fifo_q          (status_token_fifo_q),
+      .status_token_fifo_rdreq      (status_token_fifo_rdreq),
+      .t_eop                        (t_eop)
+    );
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_command_grabber (
+                                        // inputs:
+                                         clk,
+                                         command_fifo_empty,
+                                         command_fifo_q,
+                                         m_read_waitrequest,
+                                         read_go,
+                                         reset_n,
+
+                                        // outputs:
+                                         command_fifo_rdreq,
+                                         read_command_data,
+                                         read_command_valid
+                                      )
+;
+
+  output           command_fifo_rdreq;
+  output  [ 58: 0] read_command_data;
+  output           read_command_valid;
+  input            clk;
+  input            command_fifo_empty;
+  input   [103: 0] command_fifo_q;
+  input            m_read_waitrequest;
+  input            read_go;
+  input            reset_n;
+
+
+wire    [  3: 0] atlantic_channel;
+wire    [ 15: 0] bytes_to_transfer;
+wire             command_fifo_rdreq;
+wire             command_fifo_rdreq_in;
+reg              command_fifo_rdreq_reg;
+reg              command_valid;
+wire    [  7: 0] control;
+reg              delay1_command_valid;
+wire             generate_eop;
+wire    [ 31: 0] read_address;
+wire    [  7: 0] read_burst;
+reg     [ 58: 0] read_command_data;
+wire             read_command_valid;
+wire             read_fixed_address;
+wire    [ 31: 0] write_address;
+wire    [  7: 0] write_burst;
+wire             write_fixed_address;
+  //Descriptor components
+  assign read_address = command_fifo_q[31 : 0];
+  assign write_address = command_fifo_q[63 : 32];
+  assign bytes_to_transfer = command_fifo_q[79 : 64];
+  assign read_burst = command_fifo_q[87 : 80];
+  assign write_burst = command_fifo_q[95 : 88];
+  assign control = command_fifo_q[103 : 96];
+  //control bits
+  assign generate_eop = control[0];
+  assign read_fixed_address = control[1];
+  assign write_fixed_address = control[2];
+  assign atlantic_channel = control[6 : 3];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          read_command_data <= 0;
+      else 
+        read_command_data <= {write_fixed_address, generate_eop, ~read_fixed_address, read_burst, bytes_to_transfer, read_address};
+    end
+
+
+  assign read_command_valid = command_valid;
+  //command_fifo_rdreq register
+  assign command_fifo_rdreq_in = (command_fifo_rdreq_reg || command_valid) ? 1'b0 : (~read_go && ~m_read_waitrequest);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_fifo_rdreq_reg <= 0;
+      else if (~command_fifo_empty)
+          command_fifo_rdreq_reg <= command_fifo_rdreq_in;
+    end
+
+
+  assign command_fifo_rdreq = command_fifo_rdreq_reg;
+  //command_valid register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delay1_command_valid <= 0;
+      else 
+        delay1_command_valid <= command_fifo_rdreq_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          command_valid <= 0;
+      else 
+        command_valid <= delay1_command_valid;
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_m_read (
+                               // inputs:
+                                clk,
+                                m_read_readdata,
+                                m_read_readdatavalid,
+                                m_read_waitrequest,
+                                read_command_data,
+                                read_command_valid,
+                                reset_n,
+                                source_stream_ready,
+                                status_token_fifo_full,
+
+                               // outputs:
+                                m_read_address,
+                                m_read_read,
+                                read_go,
+                                source_stream_data,
+                                source_stream_empty,
+                                source_stream_endofpacket,
+                                source_stream_error,
+                                source_stream_startofpacket,
+                                source_stream_valid,
+                                status_token_fifo_data,
+                                status_token_fifo_wrreq
+                             )
+;
+
+  output  [ 31: 0] m_read_address;
+  output           m_read_read;
+  output           read_go;
+  output  [ 31: 0] source_stream_data;
+  output  [  1: 0] source_stream_empty;
+  output           source_stream_endofpacket;
+  output           source_stream_error;
+  output           source_stream_startofpacket;
+  output           source_stream_valid;
+  output  [ 23: 0] status_token_fifo_data;
+  output           status_token_fifo_wrreq;
+  input            clk;
+  input   [ 31: 0] m_read_readdata;
+  input            m_read_readdatavalid;
+  input            m_read_waitrequest;
+  input   [ 58: 0] read_command_data;
+  input            read_command_valid;
+  input            reset_n;
+  input            source_stream_ready;
+  input            status_token_fifo_full;
+
+
+wire    [ 15: 0] actual_bytes_transferred;
+wire    [  3: 0] burst_size;
+wire    [  5: 0] burst_size_right_shifted;
+wire             burst_value;
+wire    [ 15: 0] bytes_to_transfer;
+wire             e_00;
+wire             e_01;
+wire             e_02;
+wire             e_03;
+wire             e_04;
+wire             e_05;
+wire             e_06;
+wire    [  2: 0] empty_operand;
+reg     [  2: 0] empty_value;
+wire             endofpacket;
+wire             generate_eop;
+wire             generate_sop;
+wire             has_transactions_to_post;
+wire             increment_address;
+reg     [ 31: 0] m_read_address;
+wire    [ 31: 0] m_read_address_inc;
+reg              m_read_read;
+reg     [  6: 0] m_read_state;
+wire             maximum_transactions_in_queue;
+reg     [ 58: 0] read_command_data_reg;
+wire             read_go;
+wire             read_posted;
+reg     [ 15: 0] received_data_counter;
+wire             received_enough_data;
+reg     [ 15: 0] remaining_transactions;
+wire             single_transfer;
+wire    [ 31: 0] source_stream_data;
+wire    [  1: 0] source_stream_empty;
+wire             source_stream_endofpacket;
+wire             source_stream_error;
+reg              source_stream_startofpacket;
+wire             source_stream_valid;
+wire    [ 31: 0] start_address;
+reg     [  7: 0] status_reg;
+wire    [  7: 0] status_reg_in;
+wire    [ 23: 0] status_token_fifo_data;
+wire             status_token_fifo_wrreq;
+wire    [  7: 0] status_word;
+wire             still_got_full_burst;
+wire             t_eop;
+reg     [  6: 0] transactions_in_queue;
+reg     [ 15: 0] transactions_left_to_post;
+wire             tx_shift;
+  assign source_stream_error = 0;
+  //m_read, which is an e_avalon_master
+  //read_command_data_reg
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          read_command_data_reg <= 0;
+      else if (read_command_valid)
+          read_command_data_reg <= read_command_data;
+    end
+
+
+  //command input
+  assign start_address = read_command_data_reg[31 : 0];
+  assign bytes_to_transfer = read_command_data_reg[47 : 32];
+  assign increment_address = read_command_data_reg[56];
+  assign generate_eop = read_command_data_reg[57];
+  assign generate_sop = read_command_data_reg[58];
+  assign burst_size = 1;
+  assign burst_size_right_shifted = {burst_size, 2'b0};
+  //Request Path
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          transactions_left_to_post <= 0;
+      else if (m_read_state == 7'b0000100)
+          transactions_left_to_post <= (bytes_to_transfer >> 2) + |bytes_to_transfer[1 : 0];
+      else if (~m_read_waitrequest)
+        begin
+          if (m_read_state == 7'b0001000 )
+              transactions_left_to_post <= transactions_left_to_post - burst_value;
+        end
+      else if (m_read_state == 7'b1000000)
+          transactions_left_to_post <= 0;
+    end
+
+
+  assign still_got_full_burst = transactions_left_to_post >= burst_size;
+  assign burst_value = still_got_full_burst ? burst_size : transactions_left_to_post;
+  assign has_transactions_to_post = |transactions_left_to_post;
+  assign read_posted = m_read_read & ~m_read_waitrequest;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          transactions_in_queue <= 0;
+      else 
+        transactions_in_queue <= (read_posted & ~m_read_readdatavalid) ? (transactions_in_queue + 1) : ((~read_posted & m_read_readdatavalid) ? (transactions_in_queue - 1) : transactions_in_queue);
+    end
+
+
+  assign maximum_transactions_in_queue = transactions_in_queue >= (31 - 1);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_read_read <= 0;
+      else if (~m_read_waitrequest)
+          m_read_read <= read_go & (m_read_state == 7'b0001000) & has_transactions_to_post;
+    end
+
+
+  assign m_read_address_inc = increment_address ? (m_read_address + burst_size_right_shifted) : m_read_address;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_read_address <= 0;
+      else if (m_read_state == 7'b0000100)
+          m_read_address <= {start_address[31 : 2], 2'b0};
+      else if (~m_read_waitrequest)
+          if (read_go & m_read_read)
+              m_read_address <= m_read_address_inc;
+    end
+
+
+  //Unaligned transfer not supported, tx_shift is always 0.
+  assign tx_shift = 0;
+  //Response Path
+  assign single_transfer = source_stream_startofpacket & source_stream_endofpacket;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          received_data_counter <= 0;
+      else if (m_read_readdatavalid)
+        begin
+          if (single_transfer)
+              received_data_counter <= received_data_counter + 4 - tx_shift - source_stream_empty;
+          else if (endofpacket)
+              received_data_counter <= received_data_counter + (|bytes_to_transfer[1 : 0] ? bytes_to_transfer[1 : 0] : 4);
+          else if (~|received_data_counter)
+              received_data_counter <= received_data_counter + 4 - tx_shift;
+          else 
+            received_data_counter <= received_data_counter + 4;
+        end
+      else if (m_read_state == 7'b0000010)
+          received_data_counter <= 0;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          remaining_transactions <= 0;
+      else if (m_read_state == 7'b0000100)
+          remaining_transactions <= (bytes_to_transfer >> 2) + |bytes_to_transfer[1 : 0];
+      else if (read_go & m_read_readdatavalid)
+          remaining_transactions <= remaining_transactions -1;
+    end
+
+
+  assign endofpacket = remaining_transactions == 1;
+  //FSM
+  assign received_enough_data = received_data_counter >= bytes_to_transfer;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_read_state <= 7'b0000001;
+      else if (1)
+          case (m_read_state) // synthesis parallel_case
+          
+              7'b0000001: begin
+                  if (read_command_valid)
+                      m_read_state <= 7'b0000010;
+              end // 7'b0000001 
+          
+              7'b0000010: begin
+                  m_read_state <= 7'b0000100;
+              end // 7'b0000010 
+          
+              7'b0000100: begin
+                  if (~source_stream_ready)
+                      m_read_state <= 7'b0010000;
+                  else 
+                    m_read_state <= 7'b0001000;
+              end // 7'b0000100 
+          
+              7'b0001000: begin
+                  if (~source_stream_ready | maximum_transactions_in_queue)
+                      m_read_state <= 7'b0010000;
+                  else if (~has_transactions_to_post)
+                      m_read_state <= 7'b0100000;
+                  else if (received_enough_data)
+                      m_read_state <= 7'b1000000;
+              end // 7'b0001000 
+          
+              7'b0010000: begin
+                  if (received_enough_data)
+                      m_read_state <= 7'b1000000;
+                  else if (~has_transactions_to_post)
+                      m_read_state <= 7'b0100000;
+                  else if (source_stream_ready & ~m_read_waitrequest & ~maximum_transactions_in_queue)
+                      m_read_state <= 7'b0001000;
+              end // 7'b0010000 
+          
+              7'b0100000: begin
+                  if (received_enough_data)
+                      m_read_state <= 7'b1000000;
+              end // 7'b0100000 
+          
+              7'b1000000: begin
+                  m_read_state <= 7'b0000001;
+              end // 7'b1000000 
+          
+              default: begin
+                  m_read_state <= 7'b0000001;
+              end // default
+          
+          endcase // m_read_state
+    end
+
+
+  assign read_go = |(m_read_state & (7'b0001000 | 7'b0010000 | 7'b0100000 | 7'b1000000));
+  //Output on the Av-ST Source
+  assign source_stream_data = m_read_readdata;
+  assign source_stream_valid = read_go & m_read_readdatavalid;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          source_stream_startofpacket <= 0;
+      else if (~source_stream_startofpacket)
+          source_stream_startofpacket <= (m_read_state == 7'b0000100) & generate_sop;
+      else if (source_stream_valid)
+          source_stream_startofpacket <= ~source_stream_ready;
+    end
+
+
+  assign source_stream_endofpacket = read_go & endofpacket & m_read_readdatavalid & generate_eop;
+  assign source_stream_empty = (endofpacket && source_stream_valid) ? empty_value : 0;
+  assign empty_operand = 3'b100;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          empty_value <= 0;
+      else 
+        empty_value <= empty_operand - bytes_to_transfer[1 : 0];
+    end
+
+
+  //status register
+  //T_EOP does not exist for a M-T-S configuration.
+  assign t_eop = 1'b0;
+  assign status_word = {t_eop, e_06, e_05, e_04, e_03, e_02, e_01, e_00};
+  assign e_00 = 1'b0;
+  assign e_01 = 1'b0;
+  assign e_02 = 1'b0;
+  assign e_03 = 1'b0;
+  assign e_04 = 1'b0;
+  assign e_05 = 1'b0;
+  assign e_06 = 1'b0;
+  assign status_reg_in = (m_read_state == 7'b1000000) ? 0 : (status_word | status_reg);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          status_reg <= 0;
+      else 
+        status_reg <= status_reg_in;
+    end
+
+
+  //actual_bytes_transferred register
+  assign actual_bytes_transferred = received_data_counter;
+  //status_token consists of the status signals and actual_bytes_transferred
+  assign status_token_fifo_data = {status_reg, actual_bytes_transferred};
+  assign status_token_fifo_wrreq = m_read_state == 7'b1000000;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_m_readfifo_m_readfifo (
+                                              // inputs:
+                                               clk,
+                                               m_readfifo_data,
+                                               m_readfifo_rdreq,
+                                               m_readfifo_wrreq,
+                                               reset,
+
+                                              // outputs:
+                                               m_readfifo_empty,
+                                               m_readfifo_full,
+                                               m_readfifo_q,
+                                               m_readfifo_usedw
+                                            )
+;
+
+  output           m_readfifo_empty;
+  output           m_readfifo_full;
+  output  [ 36: 0] m_readfifo_q;
+  output  [  5: 0] m_readfifo_usedw;
+  input            clk;
+  input   [ 36: 0] m_readfifo_data;
+  input            m_readfifo_rdreq;
+  input            m_readfifo_wrreq;
+  input            reset;
+
+
+wire             m_readfifo_empty;
+wire             m_readfifo_full;
+wire    [ 36: 0] m_readfifo_q;
+wire    [  5: 0] m_readfifo_usedw;
+  scfifo q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (m_readfifo_data),
+      .empty (m_readfifo_empty),
+      .full (m_readfifo_full),
+      .q (m_readfifo_q),
+      .rdreq (m_readfifo_rdreq),
+      .usedw (m_readfifo_usedw),
+      .wrreq (m_readfifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.add_ram_output_register = "ON",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.intended_device_family = "MAX10",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.lpm_numwords = 64,
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.lpm_showahead = "OFF",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.lpm_type = "scfifo",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.lpm_width = 37,
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.lpm_widthu = 6,
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.overflow_checking = "ON",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.underflow_checking = "ON",
+           q_sys_sgdma_tx_m_readfifo_m_readfifo_m_readfifo.use_eab = "ON";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_m_readfifo (
+                                   // inputs:
+                                    clk,
+                                    reset,
+                                    reset_n,
+                                    sink_stream_data,
+                                    sink_stream_empty,
+                                    sink_stream_endofpacket,
+                                    sink_stream_error,
+                                    sink_stream_startofpacket,
+                                    sink_stream_valid,
+                                    source_stream_ready,
+
+                                   // outputs:
+                                    sink_stream_ready,
+                                    source_stream_data,
+                                    source_stream_empty,
+                                    source_stream_endofpacket,
+                                    source_stream_error,
+                                    source_stream_startofpacket,
+                                    source_stream_valid
+                                 )
+;
+
+  output           sink_stream_ready;
+  output  [ 31: 0] source_stream_data;
+  output  [  1: 0] source_stream_empty;
+  output           source_stream_endofpacket;
+  output           source_stream_error;
+  output           source_stream_startofpacket;
+  output           source_stream_valid;
+  input            clk;
+  input            reset;
+  input            reset_n;
+  input   [ 31: 0] sink_stream_data;
+  input   [  1: 0] sink_stream_empty;
+  input            sink_stream_endofpacket;
+  input            sink_stream_error;
+  input            sink_stream_startofpacket;
+  input            sink_stream_valid;
+  input            source_stream_ready;
+
+
+reg              delayed_m_readfifo_empty;
+wire             hold_condition;
+reg     [ 36: 0] m_readfifo_data;
+wire             m_readfifo_empty;
+wire             m_readfifo_empty_fall;
+wire             m_readfifo_full;
+wire    [ 36: 0] m_readfifo_q;
+wire             m_readfifo_rdreq;
+reg              m_readfifo_rdreq_delay;
+wire    [  5: 0] m_readfifo_usedw;
+reg              m_readfifo_wrreq;
+wire             sink_stream_ready;
+wire    [ 31: 0] source_stream_data;
+wire    [  1: 0] source_stream_empty;
+reg     [  1: 0] source_stream_empty_hold;
+wire    [  1: 0] source_stream_empty_sig;
+wire             source_stream_endofpacket;
+wire             source_stream_endofpacket_from_fifo;
+reg              source_stream_endofpacket_hold;
+wire             source_stream_endofpacket_sig;
+wire             source_stream_error;
+reg              source_stream_error_hold;
+wire             source_stream_error_sig;
+wire             source_stream_startofpacket;
+wire             source_stream_valid;
+reg              source_stream_valid_reg;
+reg              transmitted_eop;
+  //the_q_sys_sgdma_tx_m_readfifo_m_readfifo, which is an e_instance
+  q_sys_sgdma_tx_m_readfifo_m_readfifo the_q_sys_sgdma_tx_m_readfifo_m_readfifo
+    (
+      .clk              (clk),
+      .m_readfifo_data  (m_readfifo_data),
+      .m_readfifo_empty (m_readfifo_empty),
+      .m_readfifo_full  (m_readfifo_full),
+      .m_readfifo_q     (m_readfifo_q),
+      .m_readfifo_rdreq (m_readfifo_rdreq),
+      .m_readfifo_usedw (m_readfifo_usedw),
+      .m_readfifo_wrreq (m_readfifo_wrreq),
+      .reset            (reset)
+    );
+
+  assign sink_stream_ready = ~m_readfifo_usedw[5] && ~m_readfifo_full;
+  assign m_readfifo_rdreq = ~m_readfifo_empty & source_stream_ready | m_readfifo_empty_fall & ~hold_condition;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_m_readfifo_empty <= 0;
+      else 
+        delayed_m_readfifo_empty <= m_readfifo_empty;
+    end
+
+
+  assign m_readfifo_empty_fall = ~m_readfifo_empty & delayed_m_readfifo_empty;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          source_stream_valid_reg <= 0;
+      else if (source_stream_ready | m_readfifo_rdreq)
+          source_stream_valid_reg <= m_readfifo_rdreq;
+    end
+
+
+  assign source_stream_valid = source_stream_valid_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_readfifo_wrreq <= 0;
+      else 
+        m_readfifo_wrreq <= sink_stream_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_readfifo_rdreq_delay <= 0;
+      else 
+        m_readfifo_rdreq_delay <= m_readfifo_rdreq;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          transmitted_eop <= 0;
+      else 
+        transmitted_eop <= transmitted_eop ? ~m_readfifo_rdreq : source_stream_endofpacket & source_stream_ready & source_stream_valid;
+    end
+
+
+  assign source_stream_endofpacket_sig = m_readfifo_rdreq_delay? source_stream_endofpacket_from_fifo | source_stream_endofpacket_hold : (source_stream_endofpacket_from_fifo & ~transmitted_eop) | source_stream_endofpacket_hold;
+  assign source_stream_endofpacket = source_stream_endofpacket_sig;
+  assign hold_condition = source_stream_valid & ~source_stream_ready;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          source_stream_endofpacket_hold <= 0;
+      else 
+        source_stream_endofpacket_hold <= hold_condition ? source_stream_endofpacket_sig : (source_stream_ready ? 0 : source_stream_endofpacket_hold);
+    end
+
+
+  assign source_stream_empty_sig = m_readfifo_q[33 : 32];
+  assign source_stream_empty = source_stream_empty_sig | source_stream_empty_hold;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          source_stream_empty_hold <= 0;
+      else 
+        source_stream_empty_hold <= hold_condition ? source_stream_empty_sig : (source_stream_ready ? 0 : source_stream_empty_hold);
+    end
+
+
+  assign source_stream_error_sig = m_readfifo_q[34];
+  assign source_stream_error = source_stream_error_sig | source_stream_error_hold;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          source_stream_error_hold <= 0;
+      else 
+        source_stream_error_hold <= hold_condition ? source_stream_error_sig : (source_stream_ready ? 0 : source_stream_error_hold);
+    end
+
+
+  assign source_stream_data = m_readfifo_q[31 : 0];
+  assign source_stream_endofpacket_from_fifo = m_readfifo_q[35];
+  assign source_stream_startofpacket = m_readfifo_q[36];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          m_readfifo_data <= 0;
+      else 
+        m_readfifo_data <= {sink_stream_startofpacket, sink_stream_endofpacket, sink_stream_error, sink_stream_empty, sink_stream_data};
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_command_fifo (
+                                     // inputs:
+                                      clk,
+                                      command_fifo_data,
+                                      command_fifo_rdreq,
+                                      command_fifo_wrreq,
+                                      reset,
+
+                                     // outputs:
+                                      command_fifo_empty,
+                                      command_fifo_full,
+                                      command_fifo_q
+                                   )
+;
+
+  output           command_fifo_empty;
+  output           command_fifo_full;
+  output  [103: 0] command_fifo_q;
+  input            clk;
+  input   [103: 0] command_fifo_data;
+  input            command_fifo_rdreq;
+  input            command_fifo_wrreq;
+  input            reset;
+
+
+wire             command_fifo_empty;
+wire             command_fifo_full;
+wire    [103: 0] command_fifo_q;
+  scfifo q_sys_sgdma_tx_command_fifo_command_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (command_fifo_data),
+      .empty (command_fifo_empty),
+      .full (command_fifo_full),
+      .q (command_fifo_q),
+      .rdreq (command_fifo_rdreq),
+      .wrreq (command_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_tx_command_fifo_command_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_tx_command_fifo_command_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_tx_command_fifo_command_fifo.lpm_numwords = 2,
+           q_sys_sgdma_tx_command_fifo_command_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_tx_command_fifo_command_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_tx_command_fifo_command_fifo.lpm_width = 104,
+           q_sys_sgdma_tx_command_fifo_command_fifo.lpm_widthu = 1,
+           q_sys_sgdma_tx_command_fifo_command_fifo.overflow_checking = "ON",
+           q_sys_sgdma_tx_command_fifo_command_fifo.underflow_checking = "ON",
+           q_sys_sgdma_tx_command_fifo_command_fifo.use_eab = "ON";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_desc_address_fifo (
+                                          // inputs:
+                                           clk,
+                                           desc_address_fifo_data,
+                                           desc_address_fifo_rdreq,
+                                           desc_address_fifo_wrreq,
+                                           reset,
+
+                                          // outputs:
+                                           desc_address_fifo_empty,
+                                           desc_address_fifo_full,
+                                           desc_address_fifo_q
+                                        )
+;
+
+  output           desc_address_fifo_empty;
+  output           desc_address_fifo_full;
+  output  [ 31: 0] desc_address_fifo_q;
+  input            clk;
+  input   [ 31: 0] desc_address_fifo_data;
+  input            desc_address_fifo_rdreq;
+  input            desc_address_fifo_wrreq;
+  input            reset;
+
+
+wire             desc_address_fifo_empty;
+wire             desc_address_fifo_full;
+wire    [ 31: 0] desc_address_fifo_q;
+  scfifo q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (desc_address_fifo_data),
+      .empty (desc_address_fifo_empty),
+      .full (desc_address_fifo_full),
+      .q (desc_address_fifo_q),
+      .rdreq (desc_address_fifo_rdreq),
+      .wrreq (desc_address_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.lpm_width = 32,
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
+           q_sys_sgdma_tx_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx_status_token_fifo (
+                                          // inputs:
+                                           clk,
+                                           reset,
+                                           status_token_fifo_data,
+                                           status_token_fifo_rdreq,
+                                           status_token_fifo_wrreq,
+
+                                          // outputs:
+                                           status_token_fifo_empty,
+                                           status_token_fifo_full,
+                                           status_token_fifo_q
+                                        )
+;
+
+  output           status_token_fifo_empty;
+  output           status_token_fifo_full;
+  output  [ 23: 0] status_token_fifo_q;
+  input            clk;
+  input            reset;
+  input   [ 23: 0] status_token_fifo_data;
+  input            status_token_fifo_rdreq;
+  input            status_token_fifo_wrreq;
+
+
+wire             status_token_fifo_empty;
+wire             status_token_fifo_full;
+wire    [ 23: 0] status_token_fifo_q;
+  scfifo q_sys_sgdma_tx_status_token_fifo_status_token_fifo
+    (
+      .aclr (reset),
+      .clock (clk),
+      .data (status_token_fifo_data),
+      .empty (status_token_fifo_empty),
+      .full (status_token_fifo_full),
+      .q (status_token_fifo_q),
+      .rdreq (status_token_fifo_rdreq),
+      .wrreq (status_token_fifo_wrreq)
+    );
+
+  defparam q_sys_sgdma_tx_status_token_fifo_status_token_fifo.add_ram_output_register = "ON",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.intended_device_family = "MAX10",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.lpm_numwords = 2,
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.lpm_width = 24,
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.lpm_widthu = 1,
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.overflow_checking = "ON",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.underflow_checking = "ON",
+           q_sys_sgdma_tx_status_token_fifo_status_token_fifo.use_eab = "ON";
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sgdma_tx (
+                        // inputs:
+                         clk,
+                         csr_address,
+                         csr_chipselect,
+                         csr_read,
+                         csr_write,
+                         csr_writedata,
+                         descriptor_read_readdata,
+                         descriptor_read_readdatavalid,
+                         descriptor_read_waitrequest,
+                         descriptor_write_waitrequest,
+                         m_read_readdata,
+                         m_read_readdatavalid,
+                         m_read_waitrequest,
+                         out_ready,
+                         system_reset_n,
+
+                        // outputs:
+                         csr_irq,
+                         csr_readdata,
+                         descriptor_read_address,
+                         descriptor_read_read,
+                         descriptor_write_address,
+                         descriptor_write_write,
+                         descriptor_write_writedata,
+                         m_read_address,
+                         m_read_read,
+                         out_data,
+                         out_empty,
+                         out_endofpacket,
+                         out_error,
+                         out_startofpacket,
+                         out_valid
+                      )
+;
+
+  output           csr_irq;
+  output  [ 31: 0] csr_readdata;
+  output  [ 31: 0] descriptor_read_address;
+  output           descriptor_read_read;
+  output  [ 31: 0] descriptor_write_address;
+  output           descriptor_write_write;
+  output  [ 31: 0] descriptor_write_writedata;
+  output  [ 31: 0] m_read_address;
+  output           m_read_read;
+  output  [ 31: 0] out_data;
+  output  [  1: 0] out_empty;
+  output           out_endofpacket;
+  output           out_error;
+  output           out_startofpacket;
+  output           out_valid;
+  input            clk;
+  input   [  3: 0] csr_address;
+  input            csr_chipselect;
+  input            csr_read;
+  input            csr_write;
+  input   [ 31: 0] csr_writedata;
+  input   [ 31: 0] descriptor_read_readdata;
+  input            descriptor_read_readdatavalid;
+  input            descriptor_read_waitrequest;
+  input            descriptor_write_waitrequest;
+  input   [ 31: 0] m_read_readdata;
+  input            m_read_readdatavalid;
+  input            m_read_waitrequest;
+  input            out_ready;
+  input            system_reset_n;
+
+
+wire    [103: 0] command_fifo_data;
+wire             command_fifo_empty;
+wire             command_fifo_full;
+wire    [103: 0] command_fifo_q;
+wire             command_fifo_rdreq;
+wire             command_fifo_wrreq;
+wire             csr_irq;
+wire    [ 31: 0] csr_readdata;
+wire    [ 31: 0] data_to_fifo;
+wire    [ 31: 0] desc_address_fifo_data;
+wire             desc_address_fifo_empty;
+wire             desc_address_fifo_full;
+wire    [ 31: 0] desc_address_fifo_q;
+wire             desc_address_fifo_rdreq;
+wire             desc_address_fifo_wrreq;
+wire    [ 31: 0] descriptor_read_address;
+wire             descriptor_read_read;
+wire    [ 31: 0] descriptor_write_address;
+wire             descriptor_write_write;
+wire    [ 31: 0] descriptor_write_writedata;
+wire    [  1: 0] empty_to_fifo;
+wire             eop_to_fifo;
+wire             error_to_fifo;
+wire    [ 31: 0] m_read_address;
+wire             m_read_read;
+wire    [ 31: 0] out_data;
+wire    [  1: 0] out_empty;
+wire             out_endofpacket;
+wire             out_error;
+wire             out_startofpacket;
+wire             out_valid;
+wire    [ 58: 0] read_command_data;
+wire             read_command_valid;
+wire             read_go;
+wire             ready_from_fifo;
+wire             reset;
+reg              reset_n;
+wire             sop_to_fifo;
+wire    [ 31: 0] source_stream_data;
+wire    [  1: 0] source_stream_empty;
+wire             source_stream_endofpacket;
+wire             source_stream_error;
+wire             source_stream_ready;
+wire             source_stream_startofpacket;
+wire             source_stream_valid;
+wire    [ 23: 0] status_token_fifo_data;
+wire             status_token_fifo_empty;
+wire             status_token_fifo_full;
+wire    [ 23: 0] status_token_fifo_q;
+wire             status_token_fifo_rdreq;
+wire             status_token_fifo_wrreq;
+wire             sw_reset;
+reg              sw_reset_d1;
+reg              sw_reset_request;
+wire             valid_to_fifo;
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          reset_n <= 0;
+      else 
+        reset_n <= ~(~system_reset_n | sw_reset_request);
+    end
+
+
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          sw_reset_d1 <= 0;
+      else if (sw_reset | sw_reset_request)
+          sw_reset_d1 <= sw_reset & ~sw_reset_request;
+    end
+
+
+  always @(posedge clk or negedge system_reset_n)
+    begin
+      if (system_reset_n == 0)
+          sw_reset_request <= 0;
+      else if (sw_reset | sw_reset_request)
+          sw_reset_request <= sw_reset_d1 & ~sw_reset_request;
+    end
+
+
+  assign reset = ~reset_n;
+  q_sys_sgdma_tx_chain the_q_sys_sgdma_tx_chain
+    (
+      .clk                           (clk),
+      .command_fifo_data             (command_fifo_data),
+      .command_fifo_empty            (command_fifo_empty),
+      .command_fifo_full             (command_fifo_full),
+      .command_fifo_wrreq            (command_fifo_wrreq),
+      .csr_address                   (csr_address),
+      .csr_chipselect                (csr_chipselect),
+      .csr_irq                       (csr_irq),
+      .csr_read                      (csr_read),
+      .csr_readdata                  (csr_readdata),
+      .csr_write                     (csr_write),
+      .csr_writedata                 (csr_writedata),
+      .desc_address_fifo_data        (desc_address_fifo_data),
+      .desc_address_fifo_empty       (desc_address_fifo_empty),
+      .desc_address_fifo_full        (desc_address_fifo_full),
+      .desc_address_fifo_q           (desc_address_fifo_q),
+      .desc_address_fifo_rdreq       (desc_address_fifo_rdreq),
+      .desc_address_fifo_wrreq       (desc_address_fifo_wrreq),
+      .descriptor_read_address       (descriptor_read_address),
+      .descriptor_read_read          (descriptor_read_read),
+      .descriptor_read_readdata      (descriptor_read_readdata),
+      .descriptor_read_readdatavalid (descriptor_read_readdatavalid),
+      .descriptor_read_waitrequest   (descriptor_read_waitrequest & descriptor_read_read),
+      .descriptor_write_address      (descriptor_write_address),
+      .descriptor_write_waitrequest  (descriptor_write_waitrequest & descriptor_write_write),
+      .descriptor_write_write        (descriptor_write_write),
+      .descriptor_write_writedata    (descriptor_write_writedata),
+      .read_go                       (read_go),
+      .reset                         (reset),
+      .reset_n                       (reset_n),
+      .status_token_fifo_data        (status_token_fifo_data),
+      .status_token_fifo_empty       (status_token_fifo_empty),
+      .status_token_fifo_q           (status_token_fifo_q),
+      .status_token_fifo_rdreq       (status_token_fifo_rdreq),
+      .sw_reset                      (sw_reset)
+    );
+
+  q_sys_sgdma_tx_command_grabber the_q_sys_sgdma_tx_command_grabber
+    (
+      .clk                (clk),
+      .command_fifo_empty (command_fifo_empty),
+      .command_fifo_q     (command_fifo_q),
+      .command_fifo_rdreq (command_fifo_rdreq),
+      .m_read_waitrequest (m_read_waitrequest & m_read_read),
+      .read_command_data  (read_command_data),
+      .read_command_valid (read_command_valid),
+      .read_go            (read_go),
+      .reset_n            (reset_n)
+    );
+
+  q_sys_sgdma_tx_m_read the_q_sys_sgdma_tx_m_read
+    (
+      .clk                         (clk),
+      .m_read_address              (m_read_address),
+      .m_read_read                 (m_read_read),
+      .m_read_readdata             (m_read_readdata),
+      .m_read_readdatavalid        (m_read_readdatavalid),
+      .m_read_waitrequest          (m_read_waitrequest & m_read_read),
+      .read_command_data           (read_command_data),
+      .read_command_valid          (read_command_valid),
+      .read_go                     (read_go),
+      .reset_n                     (reset_n),
+      .source_stream_data          (data_to_fifo),
+      .source_stream_empty         (empty_to_fifo),
+      .source_stream_endofpacket   (eop_to_fifo),
+      .source_stream_error         (error_to_fifo),
+      .source_stream_ready         (ready_from_fifo),
+      .source_stream_startofpacket (sop_to_fifo),
+      .source_stream_valid         (valid_to_fifo),
+      .status_token_fifo_data      (status_token_fifo_data),
+      .status_token_fifo_full      (status_token_fifo_full),
+      .status_token_fifo_wrreq     (status_token_fifo_wrreq)
+    );
+
+  q_sys_sgdma_tx_m_readfifo the_q_sys_sgdma_tx_m_readfifo
+    (
+      .clk                         (clk),
+      .reset                       (reset),
+      .reset_n                     (reset_n),
+      .sink_stream_data            (data_to_fifo),
+      .sink_stream_empty           (empty_to_fifo),
+      .sink_stream_endofpacket     (eop_to_fifo),
+      .sink_stream_error           (error_to_fifo),
+      .sink_stream_ready           (ready_from_fifo),
+      .sink_stream_startofpacket   (sop_to_fifo),
+      .sink_stream_valid           (valid_to_fifo),
+      .source_stream_data          (source_stream_data),
+      .source_stream_empty         (source_stream_empty),
+      .source_stream_endofpacket   (source_stream_endofpacket),
+      .source_stream_error         (source_stream_error),
+      .source_stream_ready         (source_stream_ready),
+      .source_stream_startofpacket (source_stream_startofpacket),
+      .source_stream_valid         (source_stream_valid)
+    );
+
+  //the_q_sys_sgdma_tx_command_fifo, which is an e_instance
+  q_sys_sgdma_tx_command_fifo the_q_sys_sgdma_tx_command_fifo
+    (
+      .clk                (clk),
+      .command_fifo_data  (command_fifo_data),
+      .command_fifo_empty (command_fifo_empty),
+      .command_fifo_full  (command_fifo_full),
+      .command_fifo_q     (command_fifo_q),
+      .command_fifo_rdreq (command_fifo_rdreq),
+      .command_fifo_wrreq (command_fifo_wrreq),
+      .reset              (reset)
+    );
+
+  //the_q_sys_sgdma_tx_desc_address_fifo, which is an e_instance
+  q_sys_sgdma_tx_desc_address_fifo the_q_sys_sgdma_tx_desc_address_fifo
+    (
+      .clk                     (clk),
+      .desc_address_fifo_data  (desc_address_fifo_data),
+      .desc_address_fifo_empty (desc_address_fifo_empty),
+      .desc_address_fifo_full  (desc_address_fifo_full),
+      .desc_address_fifo_q     (desc_address_fifo_q),
+      .desc_address_fifo_rdreq (desc_address_fifo_rdreq),
+      .desc_address_fifo_wrreq (desc_address_fifo_wrreq),
+      .reset                   (reset)
+    );
+
+  //the_q_sys_sgdma_tx_status_token_fifo, which is an e_instance
+  q_sys_sgdma_tx_status_token_fifo the_q_sys_sgdma_tx_status_token_fifo
+    (
+      .clk                     (clk),
+      .reset                   (reset),
+      .status_token_fifo_data  (status_token_fifo_data),
+      .status_token_fifo_empty (status_token_fifo_empty),
+      .status_token_fifo_full  (status_token_fifo_full),
+      .status_token_fifo_q     (status_token_fifo_q),
+      .status_token_fifo_rdreq (status_token_fifo_rdreq),
+      .status_token_fifo_wrreq (status_token_fifo_wrreq)
+    );
+
+  //descriptor_read, which is an e_avalon_master
+  //descriptor_write, which is an e_avalon_master
+  //csr, which is an e_avalon_slave
+  //m_read, which is an e_avalon_master
+  assign out_empty = source_stream_empty;
+  assign out_error = source_stream_error;
+  //out, which is an e_atlantic_master
+  assign out_data = {source_stream_data[7 : 0], source_stream_data[15 : 8], source_stream_data[23 : 16], source_stream_data[31 : 24]};
+  assign out_valid = source_stream_valid;
+  assign source_stream_ready = out_ready;
+  assign out_endofpacket = source_stream_endofpacket;
+  assign out_startofpacket = source_stream_startofpacket;
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v
new file mode 100644
index 0000000..4527401
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v
@@ -0,0 +1,211 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sys_clk_timer (
+                             // inputs:
+                              address,
+                              chipselect,
+                              clk,
+                              reset_n,
+                              write_n,
+                              writedata,
+
+                             // outputs:
+                              irq,
+                              readdata
+                           )
+;
+
+  output           irq;
+  output  [ 15: 0] readdata;
+  input   [  2: 0] address;
+  input            chipselect;
+  input            clk;
+  input            reset_n;
+  input            write_n;
+  input   [ 15: 0] writedata;
+
+
+wire             clk_en;
+wire             control_continuous;
+wire             control_interrupt_enable;
+reg     [  3: 0] control_register;
+wire             control_wr_strobe;
+reg              counter_is_running;
+wire             counter_is_zero;
+wire    [ 31: 0] counter_load_value;
+reg     [ 31: 0] counter_snapshot;
+reg              delayed_unxcounter_is_zeroxx0;
+wire             do_start_counter;
+wire             do_stop_counter;
+reg              force_reload;
+reg     [ 31: 0] internal_counter;
+wire             irq;
+reg     [ 15: 0] period_h_register;
+wire             period_h_wr_strobe;
+reg     [ 15: 0] period_l_register;
+wire             period_l_wr_strobe;
+wire    [ 15: 0] read_mux_out;
+reg     [ 15: 0] readdata;
+wire             snap_h_wr_strobe;
+wire             snap_l_wr_strobe;
+wire    [ 31: 0] snap_read_value;
+wire             snap_strobe;
+wire             start_strobe;
+wire             status_wr_strobe;
+wire             stop_strobe;
+wire             timeout_event;
+reg              timeout_occurred;
+  assign clk_en = 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          internal_counter <= 32'h7A11F;
+      else if (counter_is_running || force_reload)
+          if (counter_is_zero    || force_reload)
+              internal_counter <= counter_load_value;
+          else 
+            internal_counter <= internal_counter - 1;
+    end
+
+
+  assign counter_is_zero = internal_counter == 0;
+  assign counter_load_value = {period_h_register,
+    period_l_register};
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          force_reload <= 0;
+      else if (clk_en)
+          force_reload <= period_h_wr_strobe || period_l_wr_strobe;
+    end
+
+
+  assign do_start_counter = start_strobe;
+  assign do_stop_counter = (stop_strobe                            ) ||
+    (force_reload                           ) ||
+    (counter_is_zero && ~control_continuous );
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          counter_is_running <= 1'b0;
+      else if (clk_en)
+          if (do_start_counter)
+              counter_is_running <= -1;
+          else if (do_stop_counter)
+              counter_is_running <= 0;
+    end
+
+
+  //delayed_unxcounter_is_zeroxx0, which is an e_register
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          delayed_unxcounter_is_zeroxx0 <= 0;
+      else if (clk_en)
+          delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
+    end
+
+
+  assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          timeout_occurred <= 0;
+      else if (clk_en)
+          if (status_wr_strobe)
+              timeout_occurred <= 0;
+          else if (timeout_event)
+              timeout_occurred <= -1;
+    end
+
+
+  assign irq = timeout_occurred && control_interrupt_enable;
+  //s1, which is an e_avalon_slave
+  assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
+    ({16 {(address == 3)}} & period_h_register) |
+    ({16 {(address == 4)}} & snap_read_value[15 : 0]) |
+    ({16 {(address == 5)}} & snap_read_value[31 : 16]) |
+    ({16 {(address == 1)}} & control_register) |
+    ({16 {(address == 0)}} & {counter_is_running,
+    timeout_occurred});
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          readdata <= 0;
+      else if (clk_en)
+          readdata <= read_mux_out;
+    end
+
+
+  assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
+  assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          period_l_register <= 41247;
+      else if (period_l_wr_strobe)
+          period_l_register <= writedata;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          period_h_register <= 7;
+      else if (period_h_wr_strobe)
+          period_h_register <= writedata;
+    end
+
+
+  assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
+  assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
+  assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          counter_snapshot <= 0;
+      else if (snap_strobe)
+          counter_snapshot <= internal_counter;
+    end
+
+
+  assign snap_read_value = counter_snapshot;
+  assign control_wr_strobe = chipselect && ~write_n && (address == 1);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          control_register <= 0;
+      else if (control_wr_strobe)
+          control_register <= writedata[3 : 0];
+    end
+
+
+  assign stop_strobe = writedata[3] && control_wr_strobe;
+  assign start_strobe = writedata[2] && control_wr_strobe;
+  assign control_continuous = control_register[1];
+  assign control_interrupt_enable = control_register[0];
+  assign status_wr_strobe = chipselect && ~write_n && (address == 0);
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sysid.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sysid.v
new file mode 100644
index 0000000..5fe9ae1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_sysid.v
@@ -0,0 +1,56 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//Legal Notice: (C)2010 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module q_sys_sysid (
+               // inputs:
+                address,
+                clock,
+                reset_n,
+
+               // outputs:
+                readdata
+             )
+;
+
+  output  [ 31: 0] readdata;
+  input            address;
+  input            clock;
+  input            reset_n;
+
+  wire    [ 31: 0] readdata;
+  //control_slave, which is an e_avalon_slave
+  assign readdata = address ? 1728634208 : 4207856382;
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_rx.v
new file mode 100644
index 0000000..ec96993
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_rx.v
@@ -0,0 +1,200 @@
+// q_sys_tse_0_dma_rx.v
+
+// This file was auto-generated from altera_msgdma_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_tse_0_dma_rx (
+		output wire [28:0] mm_write_address,                           //                mm_write.address
+		output wire        mm_write_write,                             //                        .write
+		output wire [3:0]  mm_write_byteenable,                        //                        .byteenable
+		output wire [31:0] mm_write_writedata,                         //                        .writedata
+		input  wire        mm_write_waitrequest,                       //                        .waitrequest
+		output wire [28:0] descriptor_read_master_address,             //  descriptor_read_master.address
+		output wire        descriptor_read_master_read,                //                        .read
+		input  wire [31:0] descriptor_read_master_readdata,            //                        .readdata
+		input  wire        descriptor_read_master_waitrequest,         //                        .waitrequest
+		input  wire        descriptor_read_master_readdatavalid,       //                        .readdatavalid
+		output wire [28:0] descriptor_write_master_address,            // descriptor_write_master.address
+		output wire        descriptor_write_master_write,              //                        .write
+		output wire [3:0]  descriptor_write_master_byteenable,         //                        .byteenable
+		output wire [31:0] descriptor_write_master_writedata,          //                        .writedata
+		input  wire        descriptor_write_master_waitrequest,        //                        .waitrequest
+		input  wire [1:0]  descriptor_write_master_response,           //                        .response
+		input  wire        descriptor_write_master_writeresponsevalid, //                        .writeresponsevalid
+		input  wire        clock_clk,                                  //                   clock.clk
+		input  wire        reset_n_reset_n,                            //                 reset_n.reset_n
+		input  wire [31:0] csr_writedata,                              //                     csr.writedata
+		input  wire        csr_write,                                  //                        .write
+		input  wire [3:0]  csr_byteenable,                             //                        .byteenable
+		output wire [31:0] csr_readdata,                               //                        .readdata
+		input  wire        csr_read,                                   //                        .read
+		input  wire [2:0]  csr_address,                                //                        .address
+		input  wire [2:0]  prefetcher_csr_address,                     //          prefetcher_csr.address
+		input  wire        prefetcher_csr_read,                        //                        .read
+		input  wire        prefetcher_csr_write,                       //                        .write
+		input  wire [31:0] prefetcher_csr_writedata,                   //                        .writedata
+		output wire [31:0] prefetcher_csr_readdata,                    //                        .readdata
+		output wire        csr_irq_irq,                                //                 csr_irq.irq
+		input  wire [31:0] st_sink_data,                               //                 st_sink.data
+		input  wire        st_sink_valid,                              //                        .valid
+		output wire        st_sink_ready,                              //                        .ready
+		input  wire        st_sink_startofpacket,                      //                        .startofpacket
+		input  wire        st_sink_endofpacket,                        //                        .endofpacket
+		input  wire [1:0]  st_sink_empty,                              //                        .empty
+		input  wire [5:0]  st_sink_error                               //                        .error
+	);
+
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_valid; // prefetcher_internal:st_src_descr_valid -> dispatcher_internal:snk_descriptor_valid
+	wire  [127:0] prefetcher_internal_descriptor_write_dispatcher_source_data;  // prefetcher_internal:st_src_descr_data -> dispatcher_internal:snk_descriptor_data
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_ready; // dispatcher_internal:snk_descriptor_ready -> prefetcher_internal:st_src_descr_ready
+	wire          dispatcher_internal_response_source_valid;                    // dispatcher_internal:src_response_valid -> prefetcher_internal:st_snk_valid
+	wire  [255:0] dispatcher_internal_response_source_data;                     // dispatcher_internal:src_response_data -> prefetcher_internal:st_snk_data
+	wire          dispatcher_internal_response_source_ready;                    // prefetcher_internal:st_snk_ready -> dispatcher_internal:src_response_ready
+	wire          dispatcher_internal_write_command_source_valid;               // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
+	wire  [255:0] dispatcher_internal_write_command_source_data;                // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
+	wire          dispatcher_internal_write_command_source_ready;               // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
+	wire          write_mstr_internal_response_source_valid;                    // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
+	wire  [255:0] write_mstr_internal_response_source_data;                     // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
+	wire          write_mstr_internal_response_source_ready;                    // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
+
+	dispatcher #(
+		.MODE                        (2),
+		.RESPONSE_PORT               (1),
+		.DESCRIPTOR_INTERFACE        (1),
+		.DESCRIPTOR_FIFO_DEPTH       (8),
+		.ENHANCED_FEATURES           (0),
+		.DESCRIPTOR_WIDTH            (128),
+		.DESCRIPTOR_BYTEENABLE_WIDTH (16)
+	) dispatcher_internal (
+		.clk                     (clock_clk),                                                                                                                                                                                                                                                             //                clock.clk
+		.reset                   (~reset_n_reset_n),                                                                                                                                                                                                                                                      //          clock_reset.reset
+		.csr_writedata           (csr_writedata),                                                                                                                                                                                                                                                         //                  CSR.writedata
+		.csr_write               (csr_write),                                                                                                                                                                                                                                                             //                     .write
+		.csr_byteenable          (csr_byteenable),                                                                                                                                                                                                                                                        //                     .byteenable
+		.csr_readdata            (csr_readdata),                                                                                                                                                                                                                                                          //                     .readdata
+		.csr_read                (csr_read),                                                                                                                                                                                                                                                              //                     .read
+		.csr_address             (csr_address),                                                                                                                                                                                                                                                           //                     .address
+		.src_response_data       (dispatcher_internal_response_source_data),                                                                                                                                                                                                                              //      Response_Source.data
+		.src_response_valid      (dispatcher_internal_response_source_valid),                                                                                                                                                                                                                             //                     .valid
+		.src_response_ready      (dispatcher_internal_response_source_ready),                                                                                                                                                                                                                             //                     .ready
+		.snk_descriptor_data     (prefetcher_internal_descriptor_write_dispatcher_source_data),                                                                                                                                                                                                           //      Descriptor_Sink.data
+		.snk_descriptor_valid    (prefetcher_internal_descriptor_write_dispatcher_source_valid),                                                                                                                                                                                                          //                     .valid
+		.snk_descriptor_ready    (prefetcher_internal_descriptor_write_dispatcher_source_ready),                                                                                                                                                                                                          //                     .ready
+		.src_write_master_data   (dispatcher_internal_write_command_source_data),                                                                                                                                                                                                                         // Write_Command_Source.data
+		.src_write_master_valid  (dispatcher_internal_write_command_source_valid),                                                                                                                                                                                                                        //                     .valid
+		.src_write_master_ready  (dispatcher_internal_write_command_source_ready),                                                                                                                                                                                                                        //                     .ready
+		.snk_write_master_data   (write_mstr_internal_response_source_data),                                                                                                                                                                                                                              //  Write_Response_Sink.data
+		.snk_write_master_valid  (write_mstr_internal_response_source_valid),                                                                                                                                                                                                                             //                     .valid
+		.snk_write_master_ready  (write_mstr_internal_response_source_ready),                                                                                                                                                                                                                             //                     .ready
+		.descriptor_write        (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.descriptor_waitrequest  (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.descriptor_writedata    (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                                                                 //          (terminated)
+		.descriptor_byteenable   (16'b0000000000000000),                                                                                                                                                                                                                                                  //          (terminated)
+		.mm_response_waitrequest (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.mm_response_byteenable  (4'b0000),                                                                                                                                                                                                                                                               //          (terminated)
+		.mm_response_address     (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.mm_response_readdata    (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.mm_response_read        (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.src_read_master_data    (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.src_read_master_valid   (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.src_read_master_ready   (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.snk_read_master_data    (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //          (terminated)
+		.snk_read_master_valid   (1'b0),                                                                                                                                                                                                                                                                  //          (terminated)
+		.snk_read_master_ready   (),                                                                                                                                                                                                                                                                      //          (terminated)
+		.csr_irq                 ()                                                                                                                                                                                                                                                                       //          (terminated)
+	);
+
+	altera_msgdma_prefetcher #(
+		.ENHANCED_FEATURES          (0),
+		.ENABLE_READ_BURST          (0),
+		.MAX_READ_BURST_COUNT       (1),
+		.MAX_READ_BURST_COUNT_WIDTH (1),
+		.DATA_WIDTH                 (32),
+		.DATA_BYTEENABLE_WIDTH      (4),
+		.DESCRIPTOR_WIDTH           (128),
+		.ADDRESS_WIDTH              (29),
+		.RESPONSE_FIFO_DEPTH        (16),
+		.RESPONSE_FIFO_DEPTH_LOG2   (4)
+	) prefetcher_internal (
+		.clk                         (clock_clk),                                                    //                              Clock.clk
+		.reset                       (~reset_n_reset_n),                                             //                        Clock_reset.reset
+		.mm_read_address             (descriptor_read_master_address),                               //             Descriptor_Read_Master.address
+		.mm_read_read                (descriptor_read_master_read),                                  //                                   .read
+		.mm_read_readdata            (descriptor_read_master_readdata),                              //                                   .readdata
+		.mm_read_waitrequest         (descriptor_read_master_waitrequest),                           //                                   .waitrequest
+		.mm_read_readdatavalid       (descriptor_read_master_readdatavalid),                         //                                   .readdatavalid
+		.mm_write_address            (descriptor_write_master_address),                              //            Descriptor_Write_Master.address
+		.mm_write_write              (descriptor_write_master_write),                                //                                   .write
+		.mm_write_byteenable         (descriptor_write_master_byteenable),                           //                                   .byteenable
+		.mm_write_writedata          (descriptor_write_master_writedata),                            //                                   .writedata
+		.mm_write_waitrequest        (descriptor_write_master_waitrequest),                          //                                   .waitrequest
+		.mm_write_response           (descriptor_write_master_response),                             //                                   .response
+		.mm_write_writeresponsevalid (descriptor_write_master_writeresponsevalid),                   //                                   .writeresponsevalid
+		.st_src_descr_data           (prefetcher_internal_descriptor_write_dispatcher_source_data),  // Descriptor_Write_Dispatcher_Source.data
+		.st_src_descr_valid          (prefetcher_internal_descriptor_write_dispatcher_source_valid), //                                   .valid
+		.st_src_descr_ready          (prefetcher_internal_descriptor_write_dispatcher_source_ready), //                                   .ready
+		.st_snk_data                 (dispatcher_internal_response_source_data),                     //                      Response_Sink.data
+		.st_snk_valid                (dispatcher_internal_response_source_valid),                    //                                   .valid
+		.st_snk_ready                (dispatcher_internal_response_source_ready),                    //                                   .ready
+		.mm_csr_address              (prefetcher_csr_address),                                       //                                Csr.address
+		.mm_csr_read                 (prefetcher_csr_read),                                          //                                   .read
+		.mm_csr_write                (prefetcher_csr_write),                                         //                                   .write
+		.mm_csr_writedata            (prefetcher_csr_writedata),                                     //                                   .writedata
+		.mm_csr_readdata             (prefetcher_csr_readdata),                                      //                                   .readdata
+		.csr_irq                     (csr_irq_irq),                                                  //                            Csr_Irq.irq
+		.mm_read_burstcount          ()                                                              //                        (terminated)
+	);
+
+	write_master #(
+		.DATA_WIDTH                     (32),
+		.LENGTH_WIDTH                   (12),
+		.FIFO_DEPTH                     (64),
+		.STRIDE_ENABLE                  (0),
+		.BURST_ENABLE                   (0),
+		.PACKET_ENABLE                  (1),
+		.ERROR_ENABLE                   (1),
+		.ERROR_WIDTH                    (6),
+		.BYTE_ENABLE_WIDTH              (4),
+		.BYTE_ENABLE_WIDTH_LOG2         (2),
+		.ADDRESS_WIDTH                  (29),
+		.FIFO_DEPTH_LOG2                (6),
+		.SYMBOL_WIDTH                   (8),
+		.NUMBER_OF_SYMBOLS              (4),
+		.NUMBER_OF_SYMBOLS_LOG2         (2),
+		.MAX_BURST_COUNT_WIDTH          (1),
+		.UNALIGNED_ACCESSES_ENABLE      (0),
+		.ONLY_FULL_ACCESS_ENABLE        (0),
+		.BURST_WRAPPING_SUPPORT         (0),
+		.PROGRAMMABLE_BURST_ENABLE      (0),
+		.MAX_BURST_COUNT                (1),
+		.FIFO_SPEED_OPTIMIZATION        (1),
+		.STRIDE_WIDTH                   (1),
+		.ACTUAL_BYTES_TRANSFERRED_WIDTH (13)
+	) write_mstr_internal (
+		.clk                (clock_clk),                                      //             Clock.clk
+		.reset              (~reset_n_reset_n),                               //       Clock_reset.reset
+		.master_address     (mm_write_address),                               // Data_Write_Master.address
+		.master_write       (mm_write_write),                                 //                  .write
+		.master_byteenable  (mm_write_byteenable),                            //                  .byteenable
+		.master_writedata   (mm_write_writedata),                             //                  .writedata
+		.master_waitrequest (mm_write_waitrequest),                           //                  .waitrequest
+		.snk_data           (st_sink_data),                                   //         Data_Sink.data
+		.snk_valid          (st_sink_valid),                                  //                  .valid
+		.snk_ready          (st_sink_ready),                                  //                  .ready
+		.snk_sop            (st_sink_startofpacket),                          //                  .startofpacket
+		.snk_eop            (st_sink_endofpacket),                            //                  .endofpacket
+		.snk_empty          (st_sink_empty),                                  //                  .empty
+		.snk_error          (st_sink_error),                                  //                  .error
+		.snk_command_data   (dispatcher_internal_write_command_source_data),  //      Command_Sink.data
+		.snk_command_valid  (dispatcher_internal_write_command_source_valid), //                  .valid
+		.snk_command_ready  (dispatcher_internal_write_command_source_ready), //                  .ready
+		.src_response_data  (write_mstr_internal_response_source_data),       //   Response_Source.data
+		.src_response_valid (write_mstr_internal_response_source_valid),      //                  .valid
+		.src_response_ready (write_mstr_internal_response_source_ready),      //                  .ready
+		.master_burstcount  ()                                                //       (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_tx.v
new file mode 100644
index 0000000..e280441
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_dma_tx.v
@@ -0,0 +1,204 @@
+// q_sys_tse_0_dma_tx.v
+
+// This file was auto-generated from altera_msgdma_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_tse_0_dma_tx (
+		output wire [28:0] mm_read_address,                            //                 mm_read.address
+		output wire        mm_read_read,                               //                        .read
+		output wire [3:0]  mm_read_byteenable,                         //                        .byteenable
+		input  wire [31:0] mm_read_readdata,                           //                        .readdata
+		input  wire        mm_read_waitrequest,                        //                        .waitrequest
+		input  wire        mm_read_readdatavalid,                      //                        .readdatavalid
+		output wire [28:0] descriptor_read_master_address,             //  descriptor_read_master.address
+		output wire        descriptor_read_master_read,                //                        .read
+		input  wire [31:0] descriptor_read_master_readdata,            //                        .readdata
+		input  wire        descriptor_read_master_waitrequest,         //                        .waitrequest
+		input  wire        descriptor_read_master_readdatavalid,       //                        .readdatavalid
+		output wire [28:0] descriptor_write_master_address,            // descriptor_write_master.address
+		output wire        descriptor_write_master_write,              //                        .write
+		output wire [3:0]  descriptor_write_master_byteenable,         //                        .byteenable
+		output wire [31:0] descriptor_write_master_writedata,          //                        .writedata
+		input  wire        descriptor_write_master_waitrequest,        //                        .waitrequest
+		input  wire [1:0]  descriptor_write_master_response,           //                        .response
+		input  wire        descriptor_write_master_writeresponsevalid, //                        .writeresponsevalid
+		input  wire        clock_clk,                                  //                   clock.clk
+		input  wire        reset_n_reset_n,                            //                 reset_n.reset_n
+		input  wire [31:0] csr_writedata,                              //                     csr.writedata
+		input  wire        csr_write,                                  //                        .write
+		input  wire [3:0]  csr_byteenable,                             //                        .byteenable
+		output wire [31:0] csr_readdata,                               //                        .readdata
+		input  wire        csr_read,                                   //                        .read
+		input  wire [2:0]  csr_address,                                //                        .address
+		input  wire [2:0]  prefetcher_csr_address,                     //          prefetcher_csr.address
+		input  wire        prefetcher_csr_read,                        //                        .read
+		input  wire        prefetcher_csr_write,                       //                        .write
+		input  wire [31:0] prefetcher_csr_writedata,                   //                        .writedata
+		output wire [31:0] prefetcher_csr_readdata,                    //                        .readdata
+		output wire        csr_irq_irq,                                //                 csr_irq.irq
+		output wire [31:0] st_source_data,                             //               st_source.data
+		output wire        st_source_valid,                            //                        .valid
+		input  wire        st_source_ready,                            //                        .ready
+		output wire        st_source_startofpacket,                    //                        .startofpacket
+		output wire        st_source_endofpacket,                      //                        .endofpacket
+		output wire [1:0]  st_source_empty,                            //                        .empty
+		output wire        st_source_error                             //                        .error
+	);
+
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_valid; // prefetcher_internal:st_src_descr_valid -> dispatcher_internal:snk_descriptor_valid
+	wire  [127:0] prefetcher_internal_descriptor_write_dispatcher_source_data;  // prefetcher_internal:st_src_descr_data -> dispatcher_internal:snk_descriptor_data
+	wire          prefetcher_internal_descriptor_write_dispatcher_source_ready; // dispatcher_internal:snk_descriptor_ready -> prefetcher_internal:st_src_descr_ready
+	wire          dispatcher_internal_response_source_valid;                    // dispatcher_internal:src_response_valid -> prefetcher_internal:st_snk_valid
+	wire  [255:0] dispatcher_internal_response_source_data;                     // dispatcher_internal:src_response_data -> prefetcher_internal:st_snk_data
+	wire          dispatcher_internal_response_source_ready;                    // prefetcher_internal:st_snk_ready -> dispatcher_internal:src_response_ready
+	wire          dispatcher_internal_read_command_source_valid;                // dispatcher_internal:src_read_master_valid -> read_mstr_internal:snk_command_valid
+	wire  [255:0] dispatcher_internal_read_command_source_data;                 // dispatcher_internal:src_read_master_data -> read_mstr_internal:snk_command_data
+	wire          dispatcher_internal_read_command_source_ready;                // read_mstr_internal:snk_command_ready -> dispatcher_internal:src_read_master_ready
+	wire          read_mstr_internal_response_source_valid;                     // read_mstr_internal:src_response_valid -> dispatcher_internal:snk_read_master_valid
+	wire  [255:0] read_mstr_internal_response_source_data;                      // read_mstr_internal:src_response_data -> dispatcher_internal:snk_read_master_data
+	wire          read_mstr_internal_response_source_ready;                     // dispatcher_internal:snk_read_master_ready -> read_mstr_internal:src_response_ready
+
+	dispatcher #(
+		.MODE                        (1),
+		.RESPONSE_PORT               (1),
+		.DESCRIPTOR_INTERFACE        (1),
+		.DESCRIPTOR_FIFO_DEPTH       (8),
+		.ENHANCED_FEATURES           (0),
+		.DESCRIPTOR_WIDTH            (128),
+		.DESCRIPTOR_BYTEENABLE_WIDTH (16)
+	) dispatcher_internal (
+		.clk                     (clock_clk),                                                                                                                                                                                                                                                             //               clock.clk
+		.reset                   (~reset_n_reset_n),                                                                                                                                                                                                                                                      //         clock_reset.reset
+		.csr_writedata           (csr_writedata),                                                                                                                                                                                                                                                         //                 CSR.writedata
+		.csr_write               (csr_write),                                                                                                                                                                                                                                                             //                    .write
+		.csr_byteenable          (csr_byteenable),                                                                                                                                                                                                                                                        //                    .byteenable
+		.csr_readdata            (csr_readdata),                                                                                                                                                                                                                                                          //                    .readdata
+		.csr_read                (csr_read),                                                                                                                                                                                                                                                              //                    .read
+		.csr_address             (csr_address),                                                                                                                                                                                                                                                           //                    .address
+		.src_response_data       (dispatcher_internal_response_source_data),                                                                                                                                                                                                                              //     Response_Source.data
+		.src_response_valid      (dispatcher_internal_response_source_valid),                                                                                                                                                                                                                             //                    .valid
+		.src_response_ready      (dispatcher_internal_response_source_ready),                                                                                                                                                                                                                             //                    .ready
+		.snk_descriptor_data     (prefetcher_internal_descriptor_write_dispatcher_source_data),                                                                                                                                                                                                           //     Descriptor_Sink.data
+		.snk_descriptor_valid    (prefetcher_internal_descriptor_write_dispatcher_source_valid),                                                                                                                                                                                                          //                    .valid
+		.snk_descriptor_ready    (prefetcher_internal_descriptor_write_dispatcher_source_ready),                                                                                                                                                                                                          //                    .ready
+		.src_read_master_data    (dispatcher_internal_read_command_source_data),                                                                                                                                                                                                                          // Read_Command_Source.data
+		.src_read_master_valid   (dispatcher_internal_read_command_source_valid),                                                                                                                                                                                                                         //                    .valid
+		.src_read_master_ready   (dispatcher_internal_read_command_source_ready),                                                                                                                                                                                                                         //                    .ready
+		.snk_read_master_data    (read_mstr_internal_response_source_data),                                                                                                                                                                                                                               //  Read_Response_Sink.data
+		.snk_read_master_valid   (read_mstr_internal_response_source_valid),                                                                                                                                                                                                                              //                    .valid
+		.snk_read_master_ready   (read_mstr_internal_response_source_ready),                                                                                                                                                                                                                              //                    .ready
+		.descriptor_write        (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.descriptor_waitrequest  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.descriptor_writedata    (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                                                                 //         (terminated)
+		.descriptor_byteenable   (16'b0000000000000000),                                                                                                                                                                                                                                                  //         (terminated)
+		.mm_response_waitrequest (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_byteenable  (4'b0000),                                                                                                                                                                                                                                                               //         (terminated)
+		.mm_response_address     (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.mm_response_readdata    (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.mm_response_read        (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.src_write_master_data   (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_valid  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.src_write_master_ready  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_data   (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //         (terminated)
+		.snk_write_master_valid  (1'b0),                                                                                                                                                                                                                                                                  //         (terminated)
+		.snk_write_master_ready  (),                                                                                                                                                                                                                                                                      //         (terminated)
+		.csr_irq                 ()                                                                                                                                                                                                                                                                       //         (terminated)
+	);
+
+	altera_msgdma_prefetcher #(
+		.ENHANCED_FEATURES          (0),
+		.ENABLE_READ_BURST          (0),
+		.MAX_READ_BURST_COUNT       (1),
+		.MAX_READ_BURST_COUNT_WIDTH (1),
+		.DATA_WIDTH                 (32),
+		.DATA_BYTEENABLE_WIDTH      (4),
+		.DESCRIPTOR_WIDTH           (128),
+		.ADDRESS_WIDTH              (29),
+		.RESPONSE_FIFO_DEPTH        (16),
+		.RESPONSE_FIFO_DEPTH_LOG2   (4)
+	) prefetcher_internal (
+		.clk                         (clock_clk),                                                    //                              Clock.clk
+		.reset                       (~reset_n_reset_n),                                             //                        Clock_reset.reset
+		.mm_read_address             (descriptor_read_master_address),                               //             Descriptor_Read_Master.address
+		.mm_read_read                (descriptor_read_master_read),                                  //                                   .read
+		.mm_read_readdata            (descriptor_read_master_readdata),                              //                                   .readdata
+		.mm_read_waitrequest         (descriptor_read_master_waitrequest),                           //                                   .waitrequest
+		.mm_read_readdatavalid       (descriptor_read_master_readdatavalid),                         //                                   .readdatavalid
+		.mm_write_address            (descriptor_write_master_address),                              //            Descriptor_Write_Master.address
+		.mm_write_write              (descriptor_write_master_write),                                //                                   .write
+		.mm_write_byteenable         (descriptor_write_master_byteenable),                           //                                   .byteenable
+		.mm_write_writedata          (descriptor_write_master_writedata),                            //                                   .writedata
+		.mm_write_waitrequest        (descriptor_write_master_waitrequest),                          //                                   .waitrequest
+		.mm_write_response           (descriptor_write_master_response),                             //                                   .response
+		.mm_write_writeresponsevalid (descriptor_write_master_writeresponsevalid),                   //                                   .writeresponsevalid
+		.st_src_descr_data           (prefetcher_internal_descriptor_write_dispatcher_source_data),  // Descriptor_Write_Dispatcher_Source.data
+		.st_src_descr_valid          (prefetcher_internal_descriptor_write_dispatcher_source_valid), //                                   .valid
+		.st_src_descr_ready          (prefetcher_internal_descriptor_write_dispatcher_source_ready), //                                   .ready
+		.st_snk_data                 (dispatcher_internal_response_source_data),                     //                      Response_Sink.data
+		.st_snk_valid                (dispatcher_internal_response_source_valid),                    //                                   .valid
+		.st_snk_ready                (dispatcher_internal_response_source_ready),                    //                                   .ready
+		.mm_csr_address              (prefetcher_csr_address),                                       //                                Csr.address
+		.mm_csr_read                 (prefetcher_csr_read),                                          //                                   .read
+		.mm_csr_write                (prefetcher_csr_write),                                         //                                   .write
+		.mm_csr_writedata            (prefetcher_csr_writedata),                                     //                                   .writedata
+		.mm_csr_readdata             (prefetcher_csr_readdata),                                      //                                   .readdata
+		.csr_irq                     (csr_irq_irq),                                                  //                            Csr_Irq.irq
+		.mm_read_burstcount          ()                                                              //                        (terminated)
+	);
+
+	read_master #(
+		.DATA_WIDTH                (32),
+		.LENGTH_WIDTH              (12),
+		.FIFO_DEPTH                (64),
+		.STRIDE_ENABLE             (0),
+		.BURST_ENABLE              (0),
+		.PACKET_ENABLE             (1),
+		.ERROR_ENABLE              (1),
+		.ERROR_WIDTH               (1),
+		.CHANNEL_ENABLE            (0),
+		.CHANNEL_WIDTH             (8),
+		.BYTE_ENABLE_WIDTH         (4),
+		.BYTE_ENABLE_WIDTH_LOG2    (2),
+		.ADDRESS_WIDTH             (29),
+		.FIFO_DEPTH_LOG2           (6),
+		.SYMBOL_WIDTH              (8),
+		.NUMBER_OF_SYMBOLS         (4),
+		.NUMBER_OF_SYMBOLS_LOG2    (2),
+		.MAX_BURST_COUNT_WIDTH     (1),
+		.UNALIGNED_ACCESSES_ENABLE (0),
+		.ONLY_FULL_ACCESS_ENABLE   (0),
+		.BURST_WRAPPING_SUPPORT    (0),
+		.PROGRAMMABLE_BURST_ENABLE (0),
+		.MAX_BURST_COUNT           (1),
+		.FIFO_SPEED_OPTIMIZATION   (1),
+		.STRIDE_WIDTH              (1)
+	) read_mstr_internal (
+		.clk                  (clock_clk),                                     //            Clock.clk
+		.reset                (~reset_n_reset_n),                              //      Clock_reset.reset
+		.master_address       (mm_read_address),                               // Data_Read_Master.address
+		.master_read          (mm_read_read),                                  //                 .read
+		.master_byteenable    (mm_read_byteenable),                            //                 .byteenable
+		.master_readdata      (mm_read_readdata),                              //                 .readdata
+		.master_waitrequest   (mm_read_waitrequest),                           //                 .waitrequest
+		.master_readdatavalid (mm_read_readdatavalid),                         //                 .readdatavalid
+		.src_data             (st_source_data),                                //      Data_Source.data
+		.src_valid            (st_source_valid),                               //                 .valid
+		.src_ready            (st_source_ready),                               //                 .ready
+		.src_sop              (st_source_startofpacket),                       //                 .startofpacket
+		.src_eop              (st_source_endofpacket),                         //                 .endofpacket
+		.src_empty            (st_source_empty),                               //                 .empty
+		.src_error            (st_source_error),                               //                 .error
+		.snk_command_data     (dispatcher_internal_read_command_source_data),  //     Command_Sink.data
+		.snk_command_valid    (dispatcher_internal_read_command_source_valid), //                 .valid
+		.snk_command_ready    (dispatcher_internal_read_command_source_ready), //                 .ready
+		.src_response_data    (read_mstr_internal_response_source_data),       //  Response_Source.data
+		.src_response_valid   (read_mstr_internal_response_source_valid),      //                 .valid
+		.src_response_ready   (read_mstr_internal_response_source_ready),      //                 .ready
+		.master_burstcount    (),                                              //      (terminated)
+		.src_channel          ()                                               //      (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_tse.v b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_tse.v
new file mode 100644
index 0000000..c9f1fab
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tse_0_tse.v
@@ -0,0 +1,406 @@
+// q_sys_tse_0_tse.v
+
+// This file was auto-generated from altera_eth_tse_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.0 614
+
+`timescale 1 ps / 1 ps
+module q_sys_tse_0_tse (
+		input  wire        clk,           // control_port_clock_connection.clk
+		input  wire        reset,         //              reset_connection.reset
+		input  wire [7:0]  reg_addr,      //                  control_port.address
+		output wire [31:0] reg_data_out,  //                              .readdata
+		input  wire        reg_rd,        //                              .read
+		input  wire [31:0] reg_data_in,   //                              .writedata
+		input  wire        reg_wr,        //                              .write
+		output wire        reg_busy,      //                              .waitrequest
+		input  wire        tx_clk,        //   pcs_mac_tx_clock_connection.clk
+		input  wire        rx_clk,        //   pcs_mac_rx_clock_connection.clk
+		input  wire        set_10,        //         mac_status_connection.set_10
+		input  wire        set_1000,      //                              .set_1000
+		output wire        eth_mode,      //                              .eth_mode
+		output wire        ena_10,        //                              .ena_10
+		input  wire [3:0]  rgmii_in,      //          mac_rgmii_connection.rgmii_in
+		output wire [3:0]  rgmii_out,     //                              .rgmii_out
+		input  wire        rx_control,    //                              .rx_control
+		output wire        tx_control,    //                              .tx_control
+		input  wire        ff_rx_clk,     //      receive_clock_connection.clk
+		input  wire        ff_tx_clk,     //     transmit_clock_connection.clk
+		output wire [31:0] ff_rx_data,    //                       receive.data
+		output wire        ff_rx_eop,     //                              .endofpacket
+		output wire [5:0]  rx_err,        //                              .error
+		output wire [1:0]  ff_rx_mod,     //                              .empty
+		input  wire        ff_rx_rdy,     //                              .ready
+		output wire        ff_rx_sop,     //                              .startofpacket
+		output wire        ff_rx_dval,    //                              .valid
+		input  wire [31:0] ff_tx_data,    //                      transmit.data
+		input  wire        ff_tx_eop,     //                              .endofpacket
+		input  wire        ff_tx_err,     //                              .error
+		input  wire [1:0]  ff_tx_mod,     //                              .empty
+		output wire        ff_tx_rdy,     //                              .ready
+		input  wire        ff_tx_sop,     //                              .startofpacket
+		input  wire        ff_tx_wren,    //                              .valid
+		output wire        mdc,           //           mac_mdio_connection.mdc
+		input  wire        mdio_in,       //                              .mdio_in
+		output wire        mdio_out,      //                              .mdio_out
+		output wire        mdio_oen,      //                              .mdio_oen
+		output wire        magic_wakeup,  //           mac_misc_connection.magic_wakeup
+		input  wire        magic_sleep_n, //                              .magic_sleep_n
+		input  wire        ff_tx_crc_fwd, //                              .ff_tx_crc_fwd
+		output wire        ff_tx_septy,   //                              .ff_tx_septy
+		output wire        tx_ff_uflow,   //                              .tx_ff_uflow
+		output wire        ff_tx_a_full,  //                              .ff_tx_a_full
+		output wire        ff_tx_a_empty, //                              .ff_tx_a_empty
+		output wire [17:0] rx_err_stat,   //                              .rx_err_stat
+		output wire [3:0]  rx_frm_type,   //                              .rx_frm_type
+		output wire        ff_rx_dsav,    //                              .ff_rx_dsav
+		output wire        ff_rx_a_full,  //                              .ff_rx_a_full
+		output wire        ff_rx_a_empty  //                              .ff_rx_a_empty
+	);
+
+	wire  [3:0] i_tse_mac_rgmii_in4_pad_export;   // i_tse_mac:rgmii_in4_pad -> rgmii_in4_0:pad_in
+	wire  [7:0] rgmii_in4_0_dout_export;          // rgmii_in4_0:dout -> i_tse_mac:rgmii_in4_dout
+	wire        i_tse_mac_rgmii_in4_ck_export;    // i_tse_mac:rgmii_in4_ck -> rgmii_in4_0:inclock
+	wire        i_tse_mac_rgmii_in1_pad_export;   // i_tse_mac:rgmii_in1_pad -> rgmii_in1_0:pad_in
+	wire  [1:0] rgmii_in1_0_dout_export;          // rgmii_in1_0:dout -> i_tse_mac:rgmii_in1_dout
+	wire        i_tse_mac_rgmii_in1_ck_export;    // i_tse_mac:rgmii_in1_ck -> rgmii_in1_0:inclock
+	wire  [3:0] rgmii_out4_0_pad_out_export;      // rgmii_out4_0:pad_out -> i_tse_mac:rgmii_out4_pad
+	wire  [7:0] i_tse_mac_rgmii_out4_din_export;  // i_tse_mac:rgmii_out4_din -> rgmii_out4_0:din
+	wire        i_tse_mac_rgmii_out4_ck_export;   // i_tse_mac:rgmii_out4_ck -> rgmii_out4_0:outclock
+	wire        i_tse_mac_rgmii_out4_aclr_export; // i_tse_mac:rgmii_out4_aclr -> rgmii_out4_0:aclr
+	wire  [0:0] rgmii_out1_0_pad_out_export;      // rgmii_out1_0:pad_out -> i_tse_mac:rgmii_out1_pad
+	wire  [1:0] i_tse_mac_rgmii_out1_din_export;  // i_tse_mac:rgmii_out1_din -> rgmii_out1_0:din
+	wire        i_tse_mac_rgmii_out1_ck_export;   // i_tse_mac:rgmii_out1_ck -> rgmii_out1_0:outclock
+	wire        i_tse_mac_rgmii_out1_aclr_export; // i_tse_mac:rgmii_out1_aclr -> rgmii_out1_0:aclr
+
+	altera_eth_tse_mac #(
+		.ING_ADDR                 (11),
+		.ENABLE_MAC_RX_VLAN       (0),
+		.ENABLE_SUP_ADDR          (0),
+		.DEVICE_FAMILY            ("MAX10"),
+		.INSERT_TA                (0),
+		.ING_FIFO                 (2048),
+		.ENABLE_ECC               (0),
+		.CRC32DWIDTH              (8),
+		.ENABLE_ENA               (32),
+		.SYNCHRONIZER_DEPTH       (3),
+		.ENABLE_MAC_TX_VLAN       (0),
+		.RESET_LEVEL              (1),
+		.STAT_CNT_ENA             (1),
+		.CUST_VERSION             (0),
+		.CRC32S1L2_EXTERN         (0),
+		.MBIT_ONLY                (1),
+		.EG_ADDR                  (11),
+		.CORE_VERSION             (4608),
+		.CRC32GENDELAY            (6),
+		.EG_FIFO                  (2048),
+		.REDUCED_INTERFACE_ENA    (1),
+		.ENABLE_MAGIC_DETECT      (1),
+		.ENABLE_MDIO              (1),
+		.ENABLE_MAC_TXADDR_SET    (1),
+		.RAM_TYPE                 ("AUTO"),
+		.CRC32CHECK16BIT          (0),
+		.ENABLE_LGTH_CHECK        (1),
+		.ENABLE_MAC_FLOW_CTRL     (0),
+		.ENABLE_SHIFT16           (1),
+		.USE_SYNC_RESET           (1),
+		.REDUCED_CONTROL          (0),
+		.MDIO_CLK_DIV             (40),
+		.ENABLE_PADDING           (1),
+		.ENABLE_GMII_LOOPBACK     (0),
+		.GBIT_ONLY                (1),
+		.ENA_HASH                 (0),
+		.ENABLE_EXTENDED_STAT_REG (0),
+		.ENABLE_HD_LOGIC          (0)
+	) i_tse_mac (
+		.clk             (clk),                              // control_port_clock_connection.clk
+		.reset           (reset),                            //              reset_connection.reset
+		.reg_addr        (reg_addr),                         //                  control_port.address
+		.reg_data_out    (reg_data_out),                     //                              .readdata
+		.reg_rd          (reg_rd),                           //                              .read
+		.reg_data_in     (reg_data_in),                      //                              .writedata
+		.reg_wr          (reg_wr),                           //                              .write
+		.reg_busy        (reg_busy),                         //                              .waitrequest
+		.ff_tx_clk       (ff_tx_clk),                        //     transmit_clock_connection.clk
+		.ff_rx_clk       (ff_rx_clk),                        //      receive_clock_connection.clk
+		.ff_rx_data      (ff_rx_data),                       //                       receive.data
+		.ff_rx_eop       (ff_rx_eop),                        //                              .endofpacket
+		.rx_err          (rx_err),                           //                              .error
+		.ff_rx_mod       (ff_rx_mod),                        //                              .empty
+		.ff_rx_rdy       (ff_rx_rdy),                        //                              .ready
+		.ff_rx_sop       (ff_rx_sop),                        //                              .startofpacket
+		.ff_rx_dval      (ff_rx_dval),                       //                              .valid
+		.ff_tx_data      (ff_tx_data),                       //                      transmit.data
+		.ff_tx_eop       (ff_tx_eop),                        //                              .endofpacket
+		.ff_tx_err       (ff_tx_err),                        //                              .error
+		.ff_tx_mod       (ff_tx_mod),                        //                              .empty
+		.ff_tx_rdy       (ff_tx_rdy),                        //                              .ready
+		.ff_tx_sop       (ff_tx_sop),                        //                              .startofpacket
+		.ff_tx_wren      (ff_tx_wren),                       //                              .valid
+		.magic_wakeup    (magic_wakeup),                     //           mac_misc_connection.export
+		.magic_sleep_n   (magic_sleep_n),                    //                              .export
+		.ff_tx_crc_fwd   (ff_tx_crc_fwd),                    //                              .export
+		.ff_tx_septy     (ff_tx_septy),                      //                              .export
+		.tx_ff_uflow     (tx_ff_uflow),                      //                              .export
+		.ff_tx_a_full    (ff_tx_a_full),                     //                              .export
+		.ff_tx_a_empty   (ff_tx_a_empty),                    //                              .export
+		.rx_err_stat     (rx_err_stat),                      //                              .export
+		.rx_frm_type     (rx_frm_type),                      //                              .export
+		.ff_rx_dsav      (ff_rx_dsav),                       //                              .export
+		.ff_rx_a_full    (ff_rx_a_full),                     //                              .export
+		.ff_rx_a_empty   (ff_rx_a_empty),                    //                              .export
+		.mdc             (mdc),                              //           mac_mdio_connection.mdc
+		.mdio_in         (mdio_in),                          //                              .mdio_in
+		.mdio_out        (mdio_out),                         //                              .mdio_out
+		.mdio_oen        (mdio_oen),                         //                              .mdio_oen
+		.rgmii_out1_aclr (i_tse_mac_rgmii_out1_aclr_export), //               rgmii_out1_aclr.export
+		.rgmii_out1_din  (i_tse_mac_rgmii_out1_din_export),  //                rgmii_out1_din.export
+		.rgmii_in1_dout  (rgmii_in1_0_dout_export),          //                rgmii_in1_dout.export
+		.rgmii_in1_ck    (i_tse_mac_rgmii_in1_ck_export),    //                  rgmii_in1_ck.export
+		.rgmii_out4_din  (i_tse_mac_rgmii_out4_din_export),  //                rgmii_out4_din.export
+		.rgmii_out4_ck   (i_tse_mac_rgmii_out4_ck_export),   //                 rgmii_out4_ck.export
+		.rgmii_in1_pad   (i_tse_mac_rgmii_in1_pad_export),   //                 rgmii_in1_pad.export
+		.rgmii_out4_aclr (i_tse_mac_rgmii_out4_aclr_export), //               rgmii_out4_aclr.export
+		.rgmii_out1_pad  (rgmii_out1_0_pad_out_export),      //                rgmii_out1_pad.export
+		.rgmii_out1_ck   (i_tse_mac_rgmii_out1_ck_export),   //                 rgmii_out1_ck.export
+		.rgmii_in4_dout  (rgmii_in4_0_dout_export),          //                rgmii_in4_dout.export
+		.rgmii_in4_pad   (i_tse_mac_rgmii_in4_pad_export),   //                 rgmii_in4_pad.export
+		.rgmii_out4_pad  (rgmii_out4_0_pad_out_export),      //                rgmii_out4_pad.export
+		.rgmii_in4_ck    (i_tse_mac_rgmii_in4_ck_export),    //                  rgmii_in4_ck.export
+		.rgmii_in        (rgmii_in),                         //          mac_rgmii_connection.rgmii_in
+		.rgmii_out       (rgmii_out),                        //                              .rgmii_out
+		.rx_control      (rx_control),                       //                              .rx_control
+		.tx_control      (tx_control),                       //                              .tx_control
+		.set_10          (set_10),                           //         mac_status_connection.set_10
+		.set_1000        (set_1000),                         //                              .set_1000
+		.eth_mode        (eth_mode),                         //                              .eth_mode
+		.ena_10          (ena_10),                           //                              .ena_10
+		.tx_clk          (tx_clk),                           //   pcs_mac_tx_clock_connection.clk
+		.rx_clk          (rx_clk),                           //   pcs_mac_rx_clock_connection.clk
+		.rx_clkena       (1'b1),                             //                   (terminated)
+		.tx_clkena       (1'b1),                             //                   (terminated)
+		.xon_gen         (1'b0),                             //                   (terminated)
+		.xoff_gen        (1'b0),                             //                   (terminated)
+		.mac_eccstatus   (),                                 //                   (terminated)
+		.gm_rx_d         (8'b00000000),                      //                   (terminated)
+		.gm_rx_dv        (1'b0),                             //                   (terminated)
+		.gm_rx_err       (1'b0),                             //                   (terminated)
+		.gm_tx_d         (),                                 //                   (terminated)
+		.gm_tx_en        (),                                 //                   (terminated)
+		.gm_tx_err       (),                                 //                   (terminated)
+		.m_rx_d          (4'b0000),                          //                   (terminated)
+		.m_rx_en         (1'b0),                             //                   (terminated)
+		.m_rx_err        (1'b0),                             //                   (terminated)
+		.m_tx_d          (),                                 //                   (terminated)
+		.m_tx_en         (),                                 //                   (terminated)
+		.m_tx_err        (),                                 //                   (terminated)
+		.m_rx_crs        (1'b0),                             //                   (terminated)
+		.m_rx_col        (1'b0)                              //                   (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("input"),
+		.SIZE                                     (4),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("none"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_in4_0 (
+		.inclock         (i_tse_mac_rgmii_in4_ck_export),  // inclock.export
+		.dout            (rgmii_in4_0_dout_export),        //    dout.export
+		.pad_in          (i_tse_mac_rgmii_in4_pad_export), //  pad_in.export
+		.inclocken       (1'b1),                           // (terminated)
+		.fr_clock        (),                               // (terminated)
+		.hr_clock        (),                               // (terminated)
+		.invert_hr_clock (1'b0),                           // (terminated)
+		.outclock        (1'b0),                           // (terminated)
+		.outclocken      (1'b0),                           // (terminated)
+		.phy_mem_clock   (1'b0),                           // (terminated)
+		.mimic_clock     (),                               // (terminated)
+		.din             (8'b00000000),                    // (terminated)
+		.pad_io          (),                               // (terminated)
+		.pad_io_b        (),                               // (terminated)
+		.pad_in_b        (4'b0000),                        // (terminated)
+		.pad_out         (),                               // (terminated)
+		.pad_out_b       (),                               // (terminated)
+		.aset            (1'b0),                           // (terminated)
+		.aclr            (1'b0),                           // (terminated)
+		.sclr            (1'b0),                           // (terminated)
+		.nsleep          (4'b0000),                        // (terminated)
+		.oe              (4'b0000)                         // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("input"),
+		.SIZE                                     (1),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("none"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_in1_0 (
+		.inclock         (i_tse_mac_rgmii_in1_ck_export),  // inclock.export
+		.dout            (rgmii_in1_0_dout_export),        //    dout.export
+		.pad_in          (i_tse_mac_rgmii_in1_pad_export), //  pad_in.export
+		.inclocken       (1'b1),                           // (terminated)
+		.fr_clock        (),                               // (terminated)
+		.hr_clock        (),                               // (terminated)
+		.invert_hr_clock (1'b0),                           // (terminated)
+		.outclock        (1'b0),                           // (terminated)
+		.outclocken      (1'b0),                           // (terminated)
+		.phy_mem_clock   (1'b0),                           // (terminated)
+		.mimic_clock     (),                               // (terminated)
+		.din             (2'b00),                          // (terminated)
+		.pad_io          (),                               // (terminated)
+		.pad_io_b        (),                               // (terminated)
+		.pad_in_b        (1'b0),                           // (terminated)
+		.pad_out         (),                               // (terminated)
+		.pad_out_b       (),                               // (terminated)
+		.aset            (1'b0),                           // (terminated)
+		.aclr            (1'b0),                           // (terminated)
+		.sclr            (1'b0),                           // (terminated)
+		.nsleep          (1'b0),                           // (terminated)
+		.oe              (1'b0)                            // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("output"),
+		.SIZE                                     (4),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("clear"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_out4_0 (
+		.outclock        (i_tse_mac_rgmii_out4_ck_export),   // outclock.export
+		.din             (i_tse_mac_rgmii_out4_din_export),  //      din.export
+		.pad_out         (rgmii_out4_0_pad_out_export),      //  pad_out.export
+		.aclr            (i_tse_mac_rgmii_out4_aclr_export), //     aclr.export
+		.outclocken      (1'b1),                             // (terminated)
+		.inclock         (1'b0),                             // (terminated)
+		.inclocken       (1'b0),                             // (terminated)
+		.fr_clock        (),                                 // (terminated)
+		.hr_clock        (),                                 // (terminated)
+		.invert_hr_clock (1'b0),                             // (terminated)
+		.phy_mem_clock   (1'b0),                             // (terminated)
+		.mimic_clock     (),                                 // (terminated)
+		.dout            (),                                 // (terminated)
+		.pad_io          (),                                 // (terminated)
+		.pad_io_b        (),                                 // (terminated)
+		.pad_in          (4'b0000),                          // (terminated)
+		.pad_in_b        (4'b0000),                          // (terminated)
+		.pad_out_b       (),                                 // (terminated)
+		.aset            (1'b0),                             // (terminated)
+		.sclr            (1'b0),                             // (terminated)
+		.nsleep          (4'b0000),                          // (terminated)
+		.oe              (4'b0000)                           // (terminated)
+	);
+
+	altera_gpio_lite #(
+		.PIN_TYPE                                 ("output"),
+		.SIZE                                     (1),
+		.REGISTER_MODE                            ("ddr"),
+		.BUFFER_TYPE                              ("single-ended"),
+		.ASYNC_MODE                               ("clear"),
+		.SYNC_MODE                                ("none"),
+		.BUS_HOLD                                 ("false"),
+		.OPEN_DRAIN_OUTPUT                        ("false"),
+		.ENABLE_OE_PORT                           ("false"),
+		.ENABLE_NSLEEP_PORT                       ("false"),
+		.ENABLE_CLOCK_ENA_PORT                    ("false"),
+		.SET_REGISTER_OUTPUTS_HIGH                ("false"),
+		.INVERT_OUTPUT                            ("false"),
+		.INVERT_INPUT_CLOCK                       ("false"),
+		.USE_ONE_REG_TO_DRIVE_OE                  ("false"),
+		.USE_DDIO_REG_TO_DRIVE_OE                 ("false"),
+		.USE_ADVANCED_DDR_FEATURES                ("false"),
+		.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
+		.ENABLE_OE_HALF_CYCLE_DELAY               ("true"),
+		.INVERT_CLKDIV_INPUT_CLOCK                ("false"),
+		.ENABLE_PHASE_INVERT_CTRL_PORT            ("false"),
+		.ENABLE_HR_CLOCK                          ("false"),
+		.INVERT_OUTPUT_CLOCK                      ("false"),
+		.INVERT_OE_INCLOCK                        ("false"),
+		.ENABLE_PHASE_DETECTOR_FOR_CK             ("false")
+	) rgmii_out1_0 (
+		.outclock        (i_tse_mac_rgmii_out1_ck_export),   // outclock.export
+		.din             (i_tse_mac_rgmii_out1_din_export),  //      din.export
+		.pad_out         (rgmii_out1_0_pad_out_export),      //  pad_out.export
+		.aclr            (i_tse_mac_rgmii_out1_aclr_export), //     aclr.export
+		.outclocken      (1'b1),                             // (terminated)
+		.inclock         (1'b0),                             // (terminated)
+		.inclocken       (1'b0),                             // (terminated)
+		.fr_clock        (),                                 // (terminated)
+		.hr_clock        (),                                 // (terminated)
+		.invert_hr_clock (1'b0),                             // (terminated)
+		.phy_mem_clock   (1'b0),                             // (terminated)
+		.mimic_clock     (),                                 // (terminated)
+		.dout            (),                                 // (terminated)
+		.pad_io          (),                                 // (terminated)
+		.pad_io_b        (),                                 // (terminated)
+		.pad_in          (1'b0),                             // (terminated)
+		.pad_in_b        (1'b0),                             // (terminated)
+		.pad_out_b       (),                                 // (terminated)
+		.aset            (1'b0),                             // (terminated)
+		.sclr            (1'b0),                             // (terminated)
+		.nsleep          (1'b0),                             // (terminated)
+		.oe              (1'b0)                              // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv
new file mode 100644
index 0000000..c621824
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv
@@ -0,0 +1,273 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// altera message_level level1
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Multiplexer
+// --------------------------------------------------------------------------------
+
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        q_sys_tx_multiplexer
+//   use_packets:        true
+//   use_empty:          1
+//   empty_width:        2
+//   data_width:         32
+//   channel_width:      1
+//   error_width:        1
+//   num_inputs:         2
+//   inChWidth:          0
+//   selectWidth:        1
+//   selectBits:         1-1:0
+//   channelSelectBits:  1-1:0
+//   inPayloadMap:       in0_data,in0_startofpacket,in0_endofpacket,in0_empty,in0_error in1_data,in1_startofpacket,in1_endofpacket,in1_empty,in1_error
+//   outPayloadMap:      out_data,out_startofpacket,out_endofpacket,out_empty,out_error
+//   inPayloadWidth:     37
+//   use_packet_scheduling: true
+//   schedulingSize:        512
+//   schedulingSizeInBits:     9   
+//   
+// ------------------------------------------
+
+
+module q_sys_tx_multiplexer (     
+// Interface: out
+ output reg              out_channel,
+ output reg              out_valid,
+ input                   out_ready,
+ output reg    [32-1: 0] out_data,
+ output reg               out_error,
+ output reg              out_startofpacket,
+ output reg              out_endofpacket,
+ output reg    [2-1 : 0] out_empty,
+
+// Interface: in0
+ input           in0_valid,
+ output reg      in0_ready,
+ input [32-1: 0] in0_data,
+           
+ input            in0_error,
+ input           in0_startofpacket,
+ input           in0_endofpacket, 
+ input [2-1: 0]  in0_empty,
+// Interface: in1
+ input           in1_valid,
+ output reg      in1_ready,
+ input [32-1: 0] in1_data,
+           
+ input            in1_error,
+ input           in1_startofpacket,
+ input           in1_endofpacket, 
+ input [2-1: 0]  in1_empty,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+/*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   reg [37 -1:0]      in0_payload;
+   reg [37 -1:0]      in1_payload;
+ 
+   reg [1-1:0]        decision = 0;
+   reg [1-1:0]        select = 0;   
+   reg                selected_endofpacket = 0;
+   reg                selected_valid;
+   wire               out_valid_wire;
+   wire               selected_ready;
+   reg   [37 -1 :0]   selected_payload;  
+   reg                packet_in_progress;
+   wire [1-1:0]       out_select;   
+   wire [37 - 1:0]    out_payload;
+
+   // ---------------------------------------------------------------------
+   //| Input Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in0_payload = {in0_data,in0_startofpacket,in0_endofpacket,in0_empty,in0_error};
+     in1_payload = {in1_data,in1_startofpacket,in1_endofpacket,in1_empty,in1_error};
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Scheduling Algorithm
+   // ---------------------------------------------------------------------
+   always @* begin
+         
+      decision = 0;
+      case(select) 
+         0 : begin
+            if (in0_valid) decision = 0;
+            if (in1_valid) decision = 1;
+         end  
+         1 : begin
+            if (in1_valid) decision = 1;
+            if (in0_valid) decision = 0;
+         end  
+         default : begin // Same as '0', should never get used.
+            if (in0_valid) decision = 0;
+            if (in1_valid) decision = 1;
+         end  
+      endcase   
+   end
+
+   // ---------------------------------------------------------------------
+   //| Capture Decision
+   // ---------------------------------------------------------------------
+   always @ (negedge reset_n, posedge clk) begin
+      if (!reset_n) begin
+         select <= 0;
+         packet_in_progress <= 0;
+      end else begin
+         if (!selected_valid && !packet_in_progress) begin
+            select <= decision;
+         end else begin
+            packet_in_progress <= 1;
+         end
+         if (selected_endofpacket && selected_valid && selected_ready) begin
+            select <= decision;
+            packet_in_progress <= 0;
+         end
+      end
+   end
+
+
+
+   // ---------------------------------------------------------------------
+   //| Mux
+   // ---------------------------------------------------------------------
+   always @* begin
+      case(select) 
+         0 : begin
+            selected_payload = in0_payload;         
+            selected_valid   = in0_valid;
+            selected_endofpacket = in0_endofpacket;
+         end  
+         1 : begin
+            selected_payload = in1_payload;         
+            selected_valid   = in1_valid;
+            selected_endofpacket = in1_endofpacket;
+         end  
+         default : begin
+            selected_payload = in0_payload;         
+            selected_valid = in0_valid;
+            selected_endofpacket = in0_endofpacket;
+         end
+      endcase
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Back Pressure
+   // ---------------------------------------------------------------------
+   always @* begin
+      in0_ready <= ~in0_valid;
+      in1_ready <= ~in1_valid;
+      case(select)
+      0 : in0_ready <= selected_ready;
+      1 : in1_ready <= selected_ready;
+      default : in0_ready <= selected_ready;
+
+endcase // case (select)
+end // always @ *
+
+   // ---------------------------------------------------------------------
+   //| output Pipeline
+   // ---------------------------------------------------------------------
+   q_sys_tx_multiplexer_1stage_pipeline  #( .PAYLOAD_WIDTH( 37 + 1 ) ) outpipe
+              ( .clk      (clk ),
+                .reset_n  (reset_n  ),
+                .in_ready ( selected_ready ),
+                .in_valid ( selected_valid ),
+                .in_payload ({select,selected_payload}),
+                .out_ready(out_ready ),
+                .out_valid(out_valid_wire),
+                .out_payload({out_select,out_payload}) );
+
+
+   // ---------------------------------------------------------------------
+   //| Output Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+      out_valid   = out_valid_wire;
+      out_channel = out_select;
+      {out_data,out_startofpacket,out_endofpacket,out_empty,out_error} = out_payload;
+   end
+endmodule //
+
+//  --------------------------------------------------------------------------------
+// | single buffered pipeline stage
+//  --------------------------------------------------------------------------------
+module q_sys_tx_multiplexer_1stage_pipeline
+  #( parameter PAYLOAD_WIDTH = 8 )
+    ( input                             clk,
+         input                          reset_n,
+         output reg                     in_ready,
+         input                          in_valid,
+         input      [PAYLOAD_WIDTH-1:0] in_payload,
+         input                          out_ready,
+         output reg                     out_valid,
+         output reg [PAYLOAD_WIDTH-1:0] out_payload
+      );
+   reg                                  in_ready1;
+
+
+   always @* begin
+      in_ready = out_ready || ~out_valid;
+      //     in_ready = in_ready1;
+      //     if (!out_ready)
+      //       in_ready = 0;
+   end
+   always @ (negedge reset_n, posedge clk) begin
+      if (!reset_n) begin
+         in_ready1 <= 0;
+         out_valid <= 0;
+         out_payload <= 0;
+      end else begin
+         in_ready1 <= out_ready || !out_valid;
+         if (in_valid) begin
+            out_valid <= 1;
+         end else if (out_ready) begin
+            out_valid <= 0;
+         end
+         if(in_valid && in_ready) begin
+            out_payload <= in_payload;
+         end
+      end // else: !if(!reset_n)
+   end // always @ (negedge reset_n, posedge clk)
+
+endmodule //
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.qip b/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.qip
new file mode 100644
index 0000000..1b462d2
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram4bkg.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram4bkg_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram4bkg_bb.v"]
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.v b/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.v
new file mode 100644
index 0000000..d4e9c5b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/ram4bkg.v
@@ -0,0 +1,214 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4bkg.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4bkg (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[7:0]  rdaddress;
+	input	[7:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.numwords_b = 256,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.widthad_b = 8,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.qip b/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.qip
new file mode 100644
index 0000000..489f110
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram4sig.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram4sig_bb.v"]
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.v b/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.v
new file mode 100644
index 0000000..b1e4d33
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/ram4sig.v
@@ -0,0 +1,216 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4sig.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4sig (
+	data,
+	rdaddress,
+	rdclock,
+	wraddress,
+	wrclock,
+	wren,
+	q);
+
+	input	[31:0]  data;
+	input	[8:0]  rdaddress;
+	input	  rdclock;
+	input	[8:0]  wraddress;
+	input	  wrclock;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  wrclock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (wrclock),
+				.clock1 (rdclock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK1",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK1",
+		altsyncram_component.power_up_uninitialized = "TRUE",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "1"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
+// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
+// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4sig_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/read_burst_control.v b/FPGA_firmware/q_sys/synthesis/submodules/read_burst_control.v
new file mode 100644
index 0000000..9325ca0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/read_burst_control.v
@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block takes the length and forms the appropriate burst count.
+  Whenever one of the short access enables are asserted this block
+  will post a burst of one.  Posting a burst of one isn't necessary
+  but it will make it possible to add byte enable support to the
+  read master at a later date.
+
+
+  Revision History:
+
+  1.0  First version
+  
+  1.1  Added generate logic around the internal burst count logic to prevent zero
+       replication simulation bug.  In the case of a non-bursting master the
+       burst count is just hardcoded to 1.
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module read_burst_control (
+  address,
+  length,
+  maximum_burst_count,
+  short_first_access_enable,
+  short_last_access_enable,
+  short_first_and_last_access_enable,
+
+  burst_count
+);
+
+  parameter BURST_ENABLE = 1;      // set to 0 to hardwire the address and write signals straight out
+  parameter BURST_COUNT_WIDTH = 3;
+  parameter WORD_SIZE_LOG2 = 2;    // log2(DATA WIDTH/8)
+  parameter ADDRESS_WIDTH = 32;
+  parameter LENGTH_WIDTH = 32;
+  parameter BURST_WRAPPING_SUPPORT = 1;  // set 1 for on, set 0 for off.  This parameter can't be enabled when hte master supports programmable burst.
+  localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
+
+  input [ADDRESS_WIDTH-1:0] address;
+  input [LENGTH_WIDTH-1:0] length;
+  input [BURST_COUNT_WIDTH-1:0] maximum_burst_count;  // will be either a hardcoded input or programmable
+  input short_first_access_enable;
+  input short_last_access_enable;
+  input short_first_and_last_access_enable;
+
+  output wire [BURST_COUNT_WIDTH-1:0] burst_count;
+
+
+  wire [BURST_COUNT_WIDTH-1:0] posted_burst;   // when the burst statemachine is used this will be the burst count posted to the fabric
+  reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;  // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
+  wire burst_of_one_enable;     // asserted when partial word accesses are occuring
+  wire short_burst_enable;
+  wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
+
+
+  assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
+
+  // for unaligned or partial transfers we must use a burst length of 1 so that 
+  assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) |  // when performing partial accesses use a burst length of 1
+                               ((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0));  // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
+  assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
+
+generate
+  if ((BURST_ENABLE == 1) & (BURST_COUNT_WIDTH > 1))
+  begin
+   
+    always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
+    begin
+    case ({short_burst_enable, burst_of_one_enable})
+      2'b00 : internal_burst_count = maximum_burst_count;
+      2'b01 : internal_burst_count = 1;  // this is when the master starts unaligned
+      2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}});  // this could be followed by a burst of 1 if there are a few bytes leftover
+      2'b11 : internal_burst_count = 1;  // burst of 1 needs to win, this is when the master starts with very little data to transfer
+    endcase
+    end
+ 
+    assign burst_count = internal_burst_count;
+  end
+  else
+  begin
+    assign burst_count = 1;  // this will be stubbed at the top level but will be used for the address and pending reads incrementing
+  end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/read_master.v b/FPGA_firmware/q_sys/synthesis/submodules/read_master.v
new file mode 100644
index 0000000..2cb9b96
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/read_master.v
@@ -0,0 +1,795 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This read master module is responsible for reading data from memory and writing
+  the contents out to a streaming source port.  It is controlled by a streaming
+  sink port called the 'command port'.  Any information that must be communicated
+  back to a host such as the state of the master (reset/stop) is made available by the
+  streaming source port called the 'response port'.
+
+  There are various parameters to control the synthesis of this hardware
+  either for functionality changes or speed/resource optimizations.  Some
+  of the parameters will be hidden in the component GUI since they are derived
+  from some other parameters.  When this master module is used in a MM to MM
+  transfer disable the packet support since the packet hardware is not needed.
+
+  In order to increase the Fmax you should enable only full accesses so that
+  the unaligned access and byte enable blocks can be reduced to wires.  Also
+  only configure the length width to be as wide as you need as it will typically
+  be the critical path of this module.  
+
+
+  Revision History:
+
+  1.0 Initial version which used a simple exported hand shake control scheme.
+
+  2.0 Added support for unaligned accesses, stride, and streaming
+
+  2.1 Fixed bugs in the control logic which was causing too many reads to be posted
+
+  2.2 Added burst support and renamed the top level module to read master
+
+  2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
+  
+  2.4 Corrected burst bug that prevented full bursts from being presented to the
+      fabric.  Corrected the stop/reset logic to ensure masters can be stopped
+      or reset while idle.
+  
+  2.5 Added early done support for non unaligned or non packet based transfers
+  
+  2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
+      signal to avoid potential FIFO overflow issues.  The read master now requires the
+      FIFO depth to be 4x the maximum burst count setting.
+      
+  2.7 Added 64-bit addressing.
+  
+  2.8 Fixed another flow control issue when unaligned accesses is enabled.  Unaligned
+      accesses causes one more clock cycle of delay between the read data and the FIFO
+      so one more burst of room in the FIFO needs to be pre-allocated (3x instead of 2x)
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module read_master (
+  clk,
+  reset,
+
+  // descriptor commands sink port
+  snk_command_data,
+  snk_command_valid,
+  snk_command_ready,
+
+  // response source port
+  src_response_data,
+  src_response_valid,
+  src_response_ready,
+
+  // data path sink port
+  src_data,
+  src_valid,
+  src_ready,
+  src_sop,
+  src_eop,
+  src_empty,
+  src_error,
+  src_channel,
+
+  // data path master port
+  master_address,
+  master_read,
+  master_byteenable,
+  master_readdata,
+  master_waitrequest,
+  master_readdatavalid,
+  master_burstcount
+);
+
+  parameter UNALIGNED_ACCESSES_ENABLE = 0;        // when enabled allows transfers to begin from off word boundaries
+  parameter ONLY_FULL_ACCESS_ENABLE = 0;          // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
+  parameter STRIDE_ENABLE = 0;                    // stride support can only be enabled when unaligned accesses is disabled
+  parameter STRIDE_WIDTH = 1;                     // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width               
+  parameter PACKET_ENABLE = 0;
+  parameter ERROR_ENABLE = 0;
+  parameter ERROR_WIDTH = 8;                      // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
+  parameter CHANNEL_ENABLE = 0;
+  parameter CHANNEL_WIDTH = 8;                    // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
+  parameter DATA_WIDTH = 32;
+  parameter BYTE_ENABLE_WIDTH = 4;                // set by the .tcl file (hidden in GUI)
+  parameter BYTE_ENABLE_WIDTH_LOG2 = 2;           // set by the .tcl file (hidden in GUI)
+  parameter ADDRESS_WIDTH = 32;                   // set in the .tcl file (hidden in GUI) by the address span of the master
+  parameter LENGTH_WIDTH = 32;                    // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
+  parameter FIFO_DEPTH = 32;
+  parameter FIFO_DEPTH_LOG2 = 5;                  // set by the .tcl file (hidden in GUI)
+  parameter FIFO_SPEED_OPTIMIZATION = 1;          // set by the .tcl file (hidden in GUI)  The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
+  parameter SYMBOL_WIDTH = 8;                     // set in the .tcl file (hidden in GUI)
+  parameter NUMBER_OF_SYMBOLS = 4;                // set in the .tcl file (hidden in GUI)
+  parameter NUMBER_OF_SYMBOLS_LOG2 = 2;           // set by the .tcl file (hidden in GUI)
+  parameter BURST_ENABLE = 0;                     // when enabled stride must be disabled, 1 to enable, 0 to disable
+  parameter MAX_BURST_COUNT = 2;                  // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
+  parameter MAX_BURST_COUNT_WIDTH = 2;            // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
+  parameter PROGRAMMABLE_BURST_ENABLE = 0;        // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
+  parameter BURST_WRAPPING_SUPPORT = 1;           // will only be used when bursting is enabled.  This cannot be enabled with programmable burst capabilities.  Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
+
+  localparam FIFO_USE_MEMORY = 1;                 // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
+  localparam BIG_ENDIAN_ACCESS = 0;               // hiding this since it can blow your foot off if you are not careful.  It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
+  // handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
+  localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
+  // when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
+  localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
+  localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
+  localparam FIXED_STRIDE = 1'b1;  // default stride distance used when stride is disabled.  1 means increment the address by a word (i.e. sequential transfer)
+
+
+  input clk;
+  input reset;
+
+  // descriptor commands sink port
+  input [255:0] snk_command_data;
+  input snk_command_valid;
+  output reg snk_command_ready;
+
+  // response source port
+  output wire [255:0] src_response_data;
+  output reg src_response_valid;
+  input src_response_ready;
+
+  // data path source port
+  output wire [DATA_WIDTH-1:0] src_data;
+  output wire src_valid;
+  input src_ready;
+  output wire src_sop;
+  output wire src_eop;
+  output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
+  output wire [ERROR_WIDTH-1:0] src_error;
+  output wire [CHANNEL_WIDTH-1:0] src_channel;
+
+  // master inputs and outputs
+  input master_waitrequest;
+  output wire [ADDRESS_WIDTH-1:0] master_address;
+  output wire master_read;
+  output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
+  input [DATA_WIDTH-1:0] master_readdata;
+  input master_readdatavalid;
+  output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
+
+  // internal signals 
+  wire [63:0] descriptor_address;
+  wire [31:0] descriptor_length;
+  wire [15:0] descriptor_stride;
+  wire [7:0] descriptor_channel;
+  wire descriptor_generate_sop;
+  wire descriptor_generate_eop;
+  wire [7:0] descriptor_error;
+  wire [7:0] descriptor_programmable_burst_count;
+  wire descriptor_early_done_enable;
+  wire sw_stop_in;
+  wire sw_reset_in;
+  reg early_done_enable_d1;
+  reg [ERROR_WIDTH-1:0] error_d1;
+  reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
+  wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
+  reg generate_sop_d1;
+  reg generate_eop_d1;
+  reg [ADDRESS_WIDTH-1:0] address_counter;
+  reg [LENGTH_WIDTH-1:0] length_counter;
+  reg [CHANNEL_WIDTH-1:0] channel_d1;
+  reg [STRIDE_WIDTH-1:0] stride_d1;
+  wire [STRIDE_WIDTH-1:0] stride_amount;  // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
+  reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address;  // used to determine how far out of alignment the master starts
+  reg first_access;  // used to determine if the first read is occuring
+  wire first_word_boundary_not_reached;  // set when the first access doesn't reach the next word boundary
+  reg first_word_boundary_not_reached_d1;
+  reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
+  reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
+  wire [FIFO_WIDTH-1:0] fifo_write_data;
+  wire [FIFO_WIDTH-1:0] fifo_read_data;
+  wire fifo_write;
+  wire fifo_read;
+  wire fifo_empty;
+  wire fifo_full;
+  wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
+  wire too_many_pending_reads;
+  wire read_complete;  // handy signal for determining when a read has occured and completed
+  wire address_increment_enable;
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment;  // amount of bytes to increment the address
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
+  wire short_first_access_enable;           // when starting unaligned and the amount of data to transfer reaches the next word boundary
+  wire short_last_access_enable;            // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary 
+  wire short_first_and_last_access_enable;  // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
+  reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
+  wire go;
+  wire done;  // asserted when last read is issued
+  reg done_d1;
+  wire done_strobe;
+  wire all_reads_returned;  // asserted when last read returns
+  reg all_reads_returned_d1;
+  wire all_reads_returned_strobe;
+  reg all_reads_returned_strobe_d1;
+  reg all_reads_returned_strobe_d2;  // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
+  wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
+  wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
+  wire MM_to_ST_adapter_sop;
+  wire MM_to_ST_adapter_eop;
+  wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
+  wire masked_sop;
+  wire masked_eop;
+  reg flush;
+  reg stopped;
+  wire length_sync_reset;
+  wire set_src_response_valid;
+  reg master_read_reg;
+
+
+/********************************************* REGISTERS **************************************************/
+  // registering descriptor information
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      error_d1 <= 0;
+      generate_sop_d1 <= 0;
+      generate_eop_d1 <= 0;
+      channel_d1 <= 0;
+      stride_d1 <= 0;
+      programmable_burst_count_d1 <= 0;
+      early_done_enable_d1 <= 0;
+    end
+    else if (go == 1)
+    begin
+      error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
+      generate_sop_d1 <= descriptor_generate_sop;
+      generate_eop_d1 <= descriptor_generate_eop;
+      channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
+      stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
+      programmable_burst_count_d1 <= ((descriptor_programmable_burst_count == 0) | (descriptor_programmable_burst_count > MAX_BURST_COUNT)) ? MAX_BURST_COUNT : descriptor_programmable_burst_count;
+      early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable;  // early done cannot be used when unaligned data or packet support is enabled
+    end
+  end
+
+
+  // master word increment counter
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      address_counter <= 0;
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
+      end
+      else if (address_increment_enable == 1)
+      begin
+        address_counter <= address_counter + address_increment;
+      end
+    end
+  end
+
+
+  // master byte address, used to determine how far out of alignment the master began transfering data
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      start_byte_address <= 0;
+    end
+    else if (go == 1)
+    begin
+      start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
+    end
+  end
+
+
+  // first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset == 1)
+    begin
+      first_access <= 0;
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        first_access <= 1;
+      end
+      else if ((first_access == 1) & (address_increment_enable == 1))
+      begin
+        first_access <= 0;
+      end
+    end
+  end
+
+
+  // this register is used to determine if the first word boundary will be reached
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      first_word_boundary_not_reached_d1 <= 0;
+    end
+    else if (go == 1)
+    begin
+      first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
+    end
+  end
+
+
+  // master length logic, this will typically be the critical path followed by the FIFO
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      length_counter <= 0;
+    end
+    else
+    begin
+      if (length_sync_reset == 1)
+      begin
+        length_counter <= 0;
+      end
+      else if (go == 1)
+      begin
+        length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
+      end
+      else if (address_increment_enable == 1)
+      begin
+        length_counter <= length_counter - bytes_to_transfer;  // not using address_increment because stride might be enabled
+      end
+    end
+  end
+
+	
+  // the pending reads counter is used to determine how many outstanding reads are posted.  This will be used to determine
+  // if more reads can be posted based on the number of unused words in the FIFO.
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      pending_reads_counter <= 0;
+    end
+    else
+    begin
+      pending_reads_counter <= pending_reads_mux;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      done_d1 <= 1;    // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
+    end
+    else
+    begin
+      done_d1 <= done;
+    end
+  end
+
+
+  // this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      all_reads_returned_d1 <= 1;
+    end
+    else
+    begin
+      all_reads_returned_d1 <= all_reads_returned;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset == 1)
+    begin
+      flush <= 0;
+    end
+    else
+    begin
+      if ((pending_reads_counter == 0) & (flush == 1))
+      begin
+        flush <= 0;
+      end
+      else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
+      begin
+        flush <= 1;  // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      stopped <= 0;
+    end
+    else
+    begin
+      if ((sw_stop_in == 0) | (sw_reset_in == 1))
+      begin
+        stopped <= 0;
+      end
+      else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
+      begin
+        stopped <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      snk_command_ready <= 1;  // have to start ready to take commands
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        snk_command_ready <= 0;
+      end
+      else if ((src_response_ready == 1) & (src_response_valid == 1))  // need to make sure the response is popped before accepting more commands
+      begin
+        snk_command_ready <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      all_reads_returned_strobe_d1 <= 0;
+      all_reads_returned_strobe_d2 <= 0;
+    end
+    else
+    begin
+      all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
+      all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      src_response_valid <= 0;
+    end
+    else
+    begin
+      if (flush == 1)
+      begin
+        src_response_valid <= 0;
+      end
+      else if (set_src_response_valid == 1)  // all the reads have returned with MM to ST adapter latency taken into consideration
+      begin
+        src_response_valid <= 1;  // will be set only once
+      end
+      else if ((src_response_valid == 1) & (src_response_ready == 1))
+      begin
+        src_response_valid <= 0;  // will be reset only once when the dispatcher captures the data
+      end
+    end
+  end
+  
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      master_read_reg <= 0;
+    end
+    else
+    begin
+      if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
+      begin
+        master_read_reg <= 1;
+      end
+      else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
+      begin
+        master_read_reg <= 0;
+      end 
+    end
+  end
+/******************************************* END REGISTERS ************************************************/
+
+
+
+
+/************************************** MODULE INSTANTIATIONS *********************************************/
+  // This block is pipelined and can't throttle the reads
+  MM_to_ST_Adapter the_MM_to_ST_adapter (
+    .clk (clk),
+    .reset (reset),
+    .length (descriptor_length[LENGTH_WIDTH-1:0]),
+    .length_counter (length_counter),
+    .address (descriptor_address[ADDRESS_WIDTH-1:0]),
+    .reads_pending (pending_reads_counter),
+    .start (go),
+    .readdata (master_readdata),
+    .readdatavalid (master_readdatavalid),
+    .fifo_data (MM_to_ST_adapter_dataout),
+    .fifo_write (fifo_write),
+    .fifo_empty (MM_to_ST_adapter_empty),
+    .fifo_sop (MM_to_ST_adapter_sop),
+    .fifo_eop (MM_to_ST_adapter_eop)
+  );
+  defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
+  defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
+  defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
+  defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
+  defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
+  defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
+  defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
+  defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
+  defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
+
+
+  // buffered sop, eop, empty, data (in that order).  sop, eop, and empty are only buffered when packet support is enabled
+  scfifo the_master_to_st_fifo (
+    .aclr (reset),
+    .sclr (flush),
+    .clock (clk),
+    .data (fifo_write_data),
+    .full (fifo_full),
+    .empty (fifo_empty),
+    .usedw (fifo_used),
+    .q (fifo_read_data),
+    .rdreq (fifo_read),
+    .wrreq (fifo_write)
+  );
+  defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
+  defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
+  defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
+  defparam the_master_to_st_fifo.lpm_showahead = "ON";  // slower but doesn't require complex control logic to time with waitrequest
+  defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
+  defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
+  defparam the_master_to_st_fifo.underflow_checking = "OFF";
+  defparam the_master_to_st_fifo.overflow_checking = "OFF";
+
+
+  // burst block that takes the length and short access enables and forms a burst count based on them.  If any of the short access bits are asserted the block will default to a burst count of 1
+  read_burst_control the_read_burst_control (
+    .address (master_address),
+    .length (length_counter),
+    .maximum_burst_count (maximum_burst_count),
+    .short_first_access_enable (short_first_access_enable),
+    .short_last_access_enable (short_last_access_enable),
+    .short_first_and_last_access_enable (short_first_and_last_access_enable),
+    .burst_count (master_burstcount)
+  );
+  defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
+  defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
+  defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2;  // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
+  defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
+  defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
+  defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
+
+
+
+/************************************ END MODULE INSTANTIATIONS *******************************************/
+
+
+
+
+/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
+  // breakout the descriptor information into more manageable names
+  assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]};  // 64-bit addressing support
+  assign descriptor_length = snk_command_data[63:32];
+  assign descriptor_channel = snk_command_data[71:64];
+  assign descriptor_generate_sop = snk_command_data[72];
+  assign descriptor_generate_eop = snk_command_data[73];
+  assign descriptor_programmable_burst_count = snk_command_data[83:76];
+  assign descriptor_stride = snk_command_data[99:84];
+  assign descriptor_error = snk_command_data[107:100];
+  assign descriptor_early_done_enable = snk_command_data[108];
+  assign sw_stop_in = snk_command_data[74];
+  assign sw_reset_in = snk_command_data[75];
+
+  assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE;  // hardcoding to FIXED_STRIDE when stride capabilities are disabled
+  assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
+
+  // swap the bytes if big endian is enabled
+  generate
+    if (BIG_ENDIAN_ACCESS == 1)
+    begin
+      genvar j;
+      for(j=0; j < DATA_WIDTH; j = j + 8)
+      begin: byte_swap
+        assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
+      end
+    end
+    else
+    begin
+      assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
+    end
+  endgenerate
+
+
+  assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
+  assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
+  assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
+
+
+  // Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
+  generate
+    genvar i;
+    for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH)  // the data width is always a multiple of the symbol width
+    begin: symbol_swap
+      assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
+    end
+  endgenerate
+
+  // Format of internal FIFO data as following: {error, channel, sop, eop, empty, data}
+  assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
+  assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
+  assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
+  assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + CHANNEL_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
+  // case:220874 mSGDMA read master connects the wrong bits for the source error
+  //assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
+  assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + CHANNEL_WIDTH + 2)] : 0;
+  
+  assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
+  assign short_last_access_size = length_counter & LSB_MASK;
+  assign short_first_and_last_access_size = length_counter & LSB_MASK;
+
+
+  /* special case transfer enables and counter increment values (address and length counter)
+    short_first_access_enable is for transfers that start unaligned but reach the next word boundary
+    short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
+    short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
+  */
+  generate
+    if (UNALIGNED_ACCESSES_ENABLE == 1)
+    begin
+      assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
+      assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
+      assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
+      assign bytes_to_transfer = bytes_to_transfer_mux;
+      assign address_increment = bytes_to_transfer_mux;  // can't use stride when unaligned accesses are enabled
+    end
+    else if (ONLY_FULL_ACCESS_ENABLE == 1)
+    begin
+      assign short_first_access_enable = 0;
+      assign short_last_access_enable = 0;
+      assign short_first_and_last_access_enable = 0;
+      assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
+      if (STRIDE_ENABLE == 1)
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount;  // stride must be a static '1' when bursting is enabled
+      end
+      else
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount;  // stride must be a static '1' when bursting is enabled
+      end
+    end
+    else  // must be aligned but can end with any number of bytes
+    begin
+      assign short_first_access_enable = 0;
+      assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH;    // less than a word to transfer
+      assign short_first_and_last_access_enable = 0;
+      assign bytes_to_transfer = bytes_to_transfer_mux;
+      if (STRIDE_ENABLE == 1)
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount;  // stride must be a static '1' when bursting is enabled
+      end
+      else
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount;  // stride must be a static '1' when bursting is enabled
+      end      
+
+    end
+  endgenerate
+
+  // the burst count will be 1 for all short accesses
+  always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
+  begin
+    case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
+      3'b001: bytes_to_transfer_mux = short_first_access_size;
+      3'b010: bytes_to_transfer_mux = short_last_access_size;
+      3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
+      default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount;  // this is the only time master_burstcount can be a value other than 1
+    endcase
+  end
+
+  always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
+  begin
+    case ({master_readdatavalid, read_complete})
+      2'b00: pending_reads_mux = pending_reads_counter;                               // no read posted and no read data returned
+      2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount);         // read posted and no read data returned
+      2'b10: pending_reads_mux = (pending_reads_counter - 1'b1);                      // no read posted but read data returned
+      2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1);  // read posted and read data returned  
+    endcase
+  end
+
+  assign src_valid = (fifo_empty == 0);
+  assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
+                    (((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH);  // start address + length doesn't reach the next word boundary
+
+  assign go = (snk_command_valid == 1) & (snk_command_ready == 1);  // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
+  assign done = (length_counter == 0);  // all reads are posted but the master is not done since there could be reads pending
+  assign done_strobe = (done == 1) & (done_d1 == 0);
+  assign fifo_read = (src_valid == 1) & (src_ready == 1);
+  assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0);  // resetting the length counter will trigger the done condition
+
+  // need to adjust the read throttling based on unaligned accesses being enabled, when enabled there is an additional stage of pipelining before the FIFO that needs to be accounted for
+  generate
+    if (UNALIGNED_ACCESSES_ENABLE == 1)
+    begin
+      assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count * 3)));  // making sure a full burst can be posted, using 3x maximum_burst_count since the read signal is pipelined and there is a pipeline stage in the MM to ST adapter and so this signal will be late using maximum_burst_count alone
+    end
+    else
+    begin
+      assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count * 2)));  // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
+    end
+  endgenerate
+  
+  assign read_complete = (master_read == 1) & (master_waitrequest == 0);
+  assign address_increment_enable = read_complete;
+
+  assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};  // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
+
+  generate if (DATA_WIDTH > 8)
+  begin
+    assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} };  // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
+  end
+  else
+  begin
+    assign master_address = address_counter;  // don't need to mask any bits as the address will only advance one byte at a time
+  end
+  endgenerate
+
+  assign master_read = master_read_reg & (done == 0);  // need to mask the read with done so that it doesn't issue one extra read at the end
+	
+  assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
+  assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
+
+  // for now the done and early done strobes are the same.  Both will be triggered when the last data returns
+  generate
+  if (UNALIGNED_ACCESSES_ENABLE == 1)  // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
+  begin
+    assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush};  // 252 zeros: done strobe: early done strobe: stop state: reset delayed
+  end
+  else
+  begin
+    assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush};  // 252 zeros: done strobe: early done strobe: stop state: reset delayed
+  end
+  endgenerate
+
+  
+  assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
+                                  (early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
+/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/read_signal_breakout.v b/FPGA_firmware/q_sys/synthesis/submodules/read_signal_breakout.v
new file mode 100644
index 0000000..f19b244
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/read_signal_breakout.v
@@ -0,0 +1,137 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block is used to breakout the 256 bit streaming ports to and from the write master.
+  The information sent through the streaming ports is a bundle of wires and buses so it's
+  fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
+  This block also provides a layer of abstraction since the descriptor buffers block has
+  no clue what format the descriptors are in except that the 'go' bit is written to.  This
+  means that using this block you could move descriptor information around without affecting
+  the top level dispatcher logic.
+  
+  
+  1.0  06/29/2009 - First version of this block of wires
+  
+  1.1  02/15/2011 - Added read_early_done_enable to the wire breakout
+  
+  1.2  11/15/2012 - Added in an additional 32 bits of address for extended descriptors
+  
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module read_signal_breakout (
+  read_command_data_in,     // descriptor from the read FIFO
+  read_command_data_out,  // reformated descriptor to the read master
+
+  // breakout of command information
+  read_address,
+  read_length,
+  read_transmit_channel,
+  read_generate_sop,
+  read_generate_eop,
+  read_park,
+  read_transfer_complete_IRQ_mask,
+  read_burst_count,      // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+  read_stride,           // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+  read_sequence_number,  // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+  read_transmit_error,
+  read_early_done_enable,
+
+  // additional control information that needs to go out asynchronously with the command data
+  read_stop,
+  read_sw_reset
+);
+
+  parameter DATA_WIDTH = 256;  // 256 bits when enhanced settings are enabled otherwise 128 bits
+
+  input [DATA_WIDTH-1:0] read_command_data_in;
+  output wire [255:0] read_command_data_out;
+
+  output wire [63:0] read_address;
+  output wire [31:0] read_length;
+  output wire [7:0] read_transmit_channel;
+  output wire read_generate_sop;
+  output wire read_generate_eop;
+  output wire read_park;
+  output wire read_transfer_complete_IRQ_mask;
+  output wire [7:0] read_burst_count;
+  output wire [15:0] read_stride;
+  output wire [15:0] read_sequence_number;
+  output wire [7:0] read_transmit_error;
+  output wire read_early_done_enable;
+
+  input read_stop;
+  input read_sw_reset;
+  
+  
+  assign read_address[31:0] = read_command_data_in[31:0];
+  assign read_length = read_command_data_in[95:64];
+
+
+  generate
+    if (DATA_WIDTH == 256)
+    begin
+      assign read_early_done_enable = read_command_data_in[248];
+      assign read_transmit_error = read_command_data_in[247:240];
+      assign read_transmit_channel = read_command_data_in[231:224];
+      assign read_generate_sop = read_command_data_in[232];
+      assign read_generate_eop = read_command_data_in[233];
+      assign read_park = read_command_data_in[234];
+      assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
+      assign read_burst_count = read_command_data_in[119:112];
+      assign read_stride = read_command_data_in[143:128];
+      assign read_sequence_number = read_command_data_in[111:96];
+      assign read_address[63:32] = read_command_data_in[191:160];
+    end
+    else
+    begin
+      assign read_early_done_enable = read_command_data_in[120];
+      assign read_transmit_error = read_command_data_in[119:112];
+      assign read_transmit_channel = read_command_data_in[103:96];
+      assign read_generate_sop = read_command_data_in[104];
+      assign read_generate_eop = read_command_data_in[105];
+      assign read_park = read_command_data_in[106];
+      assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
+      assign read_burst_count = 8'h00;
+      assign read_stride = 16'h0000;
+      assign read_sequence_number = 16'h0000;  
+      assign read_address[63:32] = 32'h00000000;
+    end
+  endgenerate
+
+  // big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
+  assign read_command_data_out = {{115{1'b0}},  // zero pad the upper 115 bits
+                                 read_address[63:32],
+                                 read_early_done_enable,
+                                 read_transmit_error,
+                                 read_stride,
+                                 read_burst_count,
+                                 read_sw_reset,
+                                 read_stop,
+                                 read_generate_eop,
+                                 read_generate_sop,
+                                 read_transmit_channel,
+                                 read_length,
+                                 read_address[31:0]};
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/response_block.v b/FPGA_firmware/q_sys/synthesis/submodules/response_block.v
new file mode 100644
index 0000000..9d90ef7
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/response_block.v
@@ -0,0 +1,225 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This optional block is used for two purposes:
+
+  1)  Relay response information back to the host typically in ST->MM mode.
+      This information is 'actual bytes transferred', 'error', and 'early termination'.
+
+  2)  Relay response and interrupt information back to a prefetching master block
+      that will write the contents back to memory.  Interrupt information is also passed
+      since the interrupt needs to occur when the prefetching master block overwrites
+      the descriptor in main memory and not when the event occurs.  The host needs to read
+      the interrupt condition out of memory so it could potentially get out of sync if
+      the interrupt information wasn't buffered and delayed.
+
+  This block has three response port options:  MM slave, ST source, and disabled.
+  When you don't need access to response information (MM->MM or MM->ST) or interrupts in
+  the case of a prefetching descriptor master then you can safely disable the port.
+  By disabling the port you will not consume any logic resources or on-chip memory blocks.
+
+  When the source port is enabled bit 52 of the data stream represents the "descriptor full"
+  condition.  The descriptor prefetching master can use this signal to perform pipelined reads
+  without having to worry about flow control (since there is room for an entire descriptor to be
+  written).  This is benefical as apposed to performing descriptor reads, buffering the data, then
+  writting it out to the descriptor buffer block.
+
+
+  Version 1.0
+
+  1.0 - If you attempt to use the wrong response port type you will be issued a warning
+        but allowed to generate.  This is because in some cases you may not need the typical
+        behavior.  For example if you perform MM->MM transfers with some streaming IP between
+        the read and write masters you still might need access to error bits.  Likewise
+        if you don't enable the streaming sink port while using a descriptor pre-fetching block
+        you may not care if you get interrupted early and want to use the CSR block for interrupts
+        instead.
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module response_block (
+  clk,
+  reset,
+
+  mm_response_readdata,
+  mm_response_read,
+  mm_response_address,
+  mm_response_byteenable,
+  mm_response_waitrequest,
+
+  src_response_data,
+  src_response_valid,
+  src_response_ready,
+
+  sw_reset,
+  response_watermark,
+  response_fifo_full,
+  response_fifo_empty,
+  done_strobe,
+  actual_bytes_transferred,
+  error,
+  early_termination,
+  transfer_complete_IRQ_mask,
+  error_IRQ_mask,
+  early_termination_IRQ_mask,
+  descriptor_buffer_full
+);
+
+
+  parameter RESPONSE_PORT = 0;   // when disabled all the outputs will be disconnected by the component wrapper
+  parameter FIFO_DEPTH = 256;    // needs to be double the descriptor FIFO depth
+  parameter FIFO_DEPTH_LOG2 = 8;
+  localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51;  // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
+
+  input clk;
+  input reset;
+
+  output wire [31:0] mm_response_readdata;
+  input mm_response_read;
+  input mm_response_address;  // only have 2 addresses
+  input [3:0] mm_response_byteenable;
+  output wire mm_response_waitrequest;
+
+  output wire [255:0] src_response_data;  // not going to use all these bits, the remainder will be grounded
+  output wire src_response_valid;
+  input src_response_ready;
+
+  input sw_reset;
+  output wire [15:0] response_watermark;
+  output wire response_fifo_full;
+  output wire response_fifo_empty;
+  input done_strobe;
+  input [31:0] actual_bytes_transferred;
+  input [7:0] error;
+  input early_termination;
+  // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
+  input transfer_complete_IRQ_mask;
+  input [7:0] error_IRQ_mask;
+  input early_termination_IRQ_mask;
+  input descriptor_buffer_full;  // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
+
+
+  /* internal signals and registers */
+  wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
+  wire fifo_full;
+  wire fifo_empty;
+  wire fifo_read;
+  wire [FIFO_WIDTH-1:0] fifo_input;
+  wire [FIFO_WIDTH-1:0] fifo_output;
+
+
+  generate
+    if (RESPONSE_PORT == 0)  // slave port used for response data
+    begin
+
+      assign fifo_input = {early_termination, error, actual_bytes_transferred};  
+      assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1);  // reading from the upper byte (byte offset 7) pops the fifo
+      scfifo the_response_FIFO (
+        .clock (clk),
+        .aclr (reset),
+        .sclr (sw_reset),
+        .data (fifo_input),
+        .wrreq (done_strobe),
+        .rdreq (fifo_read),
+        .q (fifo_output),
+        .full (fifo_full),
+        .empty (fifo_empty),
+        .usedw (fifo_used)
+      );
+      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
+      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
+      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
+      defparam the_response_FIFO.lpm_showahead = "ON";
+      defparam the_response_FIFO.use_eab = "ON";
+      defparam the_response_FIFO.overflow_checking = "OFF";
+      defparam the_response_FIFO.underflow_checking = "OFF";
+      defparam the_response_FIFO.add_ram_output_register = "ON";
+      defparam the_response_FIFO.lpm_type = "scfifo";
+
+      // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
+      assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
+      assign mm_response_waitrequest = fifo_empty;
+      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};  // zero padding plus the 'true used' FIFO amount
+      assign response_fifo_full = fifo_full;
+      assign response_fifo_empty = fifo_empty;
+
+      // no streaming port so ground all of its outputs
+      assign src_response_data = 0;
+      assign src_response_valid = 0;
+
+    end
+    else if (RESPONSE_PORT == 1)  // streaming source port used for response data (prefetcher will catch this data)
+    begin
+
+      assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
+      assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
+      scfifo the_response_FIFO (
+        .clock (clk),
+        .aclr (reset | sw_reset),
+        .data (fifo_input),
+        .wrreq (done_strobe),
+        .rdreq (fifo_read),
+        .q (fifo_output),
+        .full (fifo_full),
+        .empty (fifo_empty),
+        .usedw (fifo_used)
+      );
+      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
+      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
+      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
+      defparam the_response_FIFO.lpm_showahead = "ON";
+      defparam the_response_FIFO.use_eab = "ON";
+      defparam the_response_FIFO.overflow_checking = "OFF";
+      defparam the_response_FIFO.underflow_checking = "OFF";
+      defparam the_response_FIFO.add_ram_output_register = "ON";
+      defparam the_response_FIFO.lpm_type = "scfifo";
+
+      assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output};  // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
+      assign src_response_valid = (fifo_empty == 0);
+      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};  // zero padding plus the 'true used' FIFO amount;
+      assign response_fifo_full = fifo_full;
+      assign response_fifo_empty = fifo_empty;
+
+      // no slave port so ground all of its outputs
+      assign mm_response_readdata = 0;
+      assign mm_response_waitrequest = 0;
+
+    end
+    else  // no response port so grounding all outputs
+    begin
+
+      assign fifo_input = 0;
+      assign fifo_output = 0;
+      assign mm_response_readdata = 0;
+      assign mm_response_waitrequest = 0;
+      assign src_response_data = 0;
+      assign src_response_valid = 0;
+      assign response_watermark = 0;
+      assign response_fifo_full = 0;
+      assign response_fifo_empty = 0;
+
+    end
+  endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rms.sv b/FPGA_firmware/q_sys/synthesis/submodules/rms.sv
new file mode 100644
index 0000000..5587357
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rms.sv
@@ -0,0 +1,396 @@
+//the module for rms
+/*
+if there is cluster:
+go through the data three times:
+first time, calc Xmean;
+second time calc Sigma;
+
+if there is no cluster:
+directly send it. 
+
+*/
+
+//
+
+//tested with algo_top_cl_cali_rms_tb.v 
+
+module rms(
+	
+	input  wire        	clk,                    //                     clk.clk
+	input  wire        	rst,         			// the reset should connect to the int_rst from sensor
+
+	//data for sig after bkg subtraction
+	input wire 			  bkg_sub_on, 					//indicate that bkg_sub is on 
+	input wire          sig_ram_last,				//the last channel is being wroten when sig_ram_last=1'b1
+	
+	output wire[8:0]		sig_rdaddress,             //0~319 for data. 500~502 for the 3 words head
+	input wire [15:0]		sig,
+	output wire 			sig_rd_eable, 					//eable read, get sig  next clock
+
+	//the output of cluster_locate
+	input wire[8:0]		sig_ch_left,	         //after sig_ram_last, if has_cluster, catch the sig_ch_left and right signal, and calc
+	input wire[8:0]		sig_ch_right,
+	input wire				has_cluster,
+	input wire				no_cluster,					// this is not used
+
+	//the result
+	output wire 			overflow,
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //4 * 32 bits data  
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	);
+	
+	
+	
+	
+	/* reg results has 32*4 bits
+	WORDS 163 [31:16]MeanXleftshift [15:0] Sigma0;
+			164 [31:16]MaxY; [15:0] STATUS;
+			165 for debug;
+			166 for debug;
+		for status register:
+		STATUS_BKG_SUB_ON  0x0001
+		STATUS_HAS_CLUSTER 0x0002
+		STATUS_NO_CLUSTER  0x0004	
+		*/
+
+	
+	reg[31:0] results[4];
+	
+	localparam WORDS_TO_SEND = 4;	 //results[4]
+	localparam SHIFT_BITS = 2;
+
+
+	reg[3:0] state;
+	localparam STATE_IDLE = 0; //when sig_ram_last, move to STATE_JUDGE
+	localparam STATE_JUDGE = 1; 
+	/*reset registers; If has_cluster to STATE_CAL1 => WAIT_4_CLK => DIV1 => CAL2 => WAIT_6CLK => DIV2 => SQRT => LOCK => SEND=>,
+	if not to =>SEND*/
+	localparam STATE_SEND = 2; // give a start_transmission signal and start the other statemachine for sending
+	localparam STATE_CAL1 = 4;
+	localparam STATE_WAIT_4CLK = 5;
+	localparam STATE_DIV1 = 6;
+	localparam STATE_CAL2 = 7; 
+	localparam STATE_WAIT_6CLK = 8;
+	localparam STATE_DIV2 = 9;
+	localparam STATE_SQRT = 10;
+	localparam STATE_LOCK = 11; //lock the MaxY, Sigma0, and MeanXleftshift  
+	
+
+	
+	// channel_ctr is address from sig_ram
+	// arrayID depends on the channel_ctr one clock ago
+	reg[8:0] channel_ctr;
+	localparam CH_NUM = 320; //channel number, 5 array, 320 channel
+	reg[8:0] ch_right;
+	reg[8:0] ch_left;
+	reg signed[3:0] arrayID;
+	
+	assign sig_rdaddress = channel_ctr;
+	assign sig_rd_eable = (state == STATE_CAL1 || state == STATE_CAL2)? 1'b1: 1'b0;
+	
+	// registers for CAL1
+	reg signed[13:0] X[2]; 
+	reg signed[15:0] Y[3]; //only Y[0] for cal1 //Y[2], Y[1], Y[0] for cal2, pipe 
+	reg signed[15:0] MaxY;
+	reg signed[31:0] SumY;
+	reg signed[31:0] XY;
+	reg signed[34:0] SumXY;
+	wire signed[36:0] SumXYleftshift;
+	reg signed[13:0] MeanXleftshift;
+	
+	assign SumXYleftshift = SumXY << SHIFT_BITS;
+	
+	
+	//the registers for CAL2
+	reg signed[31:0] SumYm1; //SumY - 1
+	reg signed[14:0] DiffxMeanX;
+	reg signed[28:0] DiffxMeanX2;
+	reg signed[43:0] DiffxMeanX2Yi;
+	reg signed[43:0] SumDiffxMeanX2Yi;
+	reg unsigned[25:0] Sigma2;
+	reg unsigned[12:0] Sigma0;
+	
+	
+	
+	
+	//the wait_ctr for different steps in each states
+	reg unsigned[8:0] wait_ctr;
+	
+	wire div_clken;
+	wire[29:0] denom;
+	wire[39:0] numer;
+	wire[31:0] quotient;
+	assign div_clken = (state == STATE_DIV1 || state == STATE_DIV2)? 1'b1: 1'b0;
+	assign denom = (state == STATE_DIV1)? SumY[29:0]: 
+						(state == STATE_DIV2)? (SumYm1[29:0]): 30'b1;
+	assign numer = (state == STATE_DIV1)? (SumXYleftshift[35:0]) :
+						(state == STATE_DIV2)? SumDiffxMeanX2Yi[39:0]: 0;
+	localparam DIV_LATENCY = 26;
+	//division with 26 clocks latency
+	div	div1 (
+	.clken ( div_clken ),
+	.clock ( clk),
+	.denom ( denom ),
+	.numer ( numer ),
+	.quotient ( quotient )
+	);
+	
+	wire sqrt_clken;
+	wire[25:0] radical_sig;
+	wire[12:0] q_sqrt;
+	assign sqrt_clken = (state == STATE_SQRT)? 1'b1: 1'b0;
+	assign radical_sig = (state == STATE_SQRT)? Sigma2: 26'b0;
+	localparam SQRT_LATENCY = 13;
+	//sqrt with 13 clocks latency
+	sqrt	sqrt_inst (
+	.clk ( clk),
+	.ena ( sqrt_clken ),
+	.radical ( radical_sig ),
+	.q ( q_sqrt )
+	);
+	
+
+	// 12 July 2024 I should change arrayID to wires
+	//the sequential logic for arrayID
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			arrayID <= 4'd0;
+		else if (channel_ctr>=9'h0 && channel_ctr<9'h40)
+			arrayID <= 4'd0;
+		else if (channel_ctr<9'h80)
+			arrayID <= 4'd1;
+		else if (channel_ctr<9'hC0)
+			arrayID <= 4'd2;
+		else if (channel_ctr<9'h100)
+			arrayID <= 4'd3;
+		else if (channel_ctr<9'h140)
+			arrayID <= 4'd4;
+		else
+			arrayID <= 4'd0;
+	end
+	
+	
+	always @ (posedge clk or posedge rst) 
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			X[0] <= 0; //For cal1
+			X[1] <= 0;
+			Y[0] <= 0;
+			MaxY <= 0;
+			XY <= 0; 
+			SumXY <= 0;
+			SumY <= 0;
+			SumDiffxMeanX2Yi <= 0;
+			wait_ctr <= 0;
+			MeanXleftshift <= 0;
+			Y[1] <= 0; //For cal2
+			Y[2] <= 0;
+			SumYm1 <= 0;
+			DiffxMeanX <= 0;
+			DiffxMeanX2 <= 0;
+			DiffxMeanX2Yi <= 0;
+			SumDiffxMeanX2Yi <= 0; 
+			Sigma2 <= 0;
+			Sigma0 <= 0;
+			results[0] <= 0; //Collect Results
+			results[1] <= 0;
+			results[2] <= 0;
+			results[3] <= 0;
+			ch_right <= 0;
+			ch_left <= 0;
+			if (sig_ram_last) begin
+				state <= STATE_JUDGE;
+			end
+		end
+		STATE_JUDGE:
+		begin
+			if (~sig_ram_last) begin
+				if (bkg_sub_on && has_cluster)	
+						state <= STATE_CAL1; 
+				else
+					state <= STATE_SEND;			
+				results[1][0] <= bkg_sub_on;
+				results[1][1] <= has_cluster;
+				results[1][2] <= no_cluster;
+				results[2][31:16] <= {7'b0,sig_ch_left};
+				results[2][15:0] <= {7'b0,sig_ch_right};
+				ch_right <= sig_ch_right;
+				ch_left <= sig_ch_left;
+				channel_ctr <= sig_ch_left;
+			end
+		end
+		STATE_CAL1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1][12:0]<= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			if (wait_ctr >= 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig;
+			end
+			if (wait_ctr>=2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr>=3) begin
+				SumXY <= SumXY + XY;
+			end			
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_4CLK;
+				channel_ctr <= ch_left;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_WAIT_4CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr < 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig;
+			end
+			if (wait_ctr < 2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr < 3) begin
+				SumXY <= SumXY + XY;
+			end
+			if (wait_ctr == 3) begin
+				state <= STATE_DIV1;
+				SumYm1 <= SumY - 1'b1;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_DIV1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				MeanXleftshift <= {1'b0,quotient[12:0]};
+				wait_ctr <= 0;
+				state <= STATE_CAL2;
+			end
+		end
+		STATE_CAL2:
+		begin
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1][12:0] <= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			wait_ctr <= wait_ctr + 1'b1;	
+			if (wait_ctr >= 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig;
+			end
+			if (wait_ctr >= 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr >= 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr >= 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr >= 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_6CLK;
+				wait_ctr <= 0;
+				channel_ctr <= ch_left;
+			end
+		end
+		STATE_WAIT_6CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr < 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig;
+			end
+			if (wait_ctr < 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr < 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr < 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr < 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (wait_ctr == 5) begin
+				wait_ctr <= 0;
+				state <= STATE_DIV2;
+			end
+		end
+		STATE_DIV2:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				Sigma2 <= quotient[25:0];
+				wait_ctr <= 0;
+				state <= STATE_SQRT;
+			end
+		end
+		STATE_SQRT:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == SQRT_LATENCY)
+			begin
+				state <= STATE_LOCK;
+				wait_ctr <= 0;
+				Sigma0 <= q_sqrt;
+			end
+		end
+		STATE_LOCK:
+		begin
+			results[0][31:16] <= MeanXleftshift;
+			results[0][15:0] <= Sigma0;
+			results[1][31:16] <= MaxY;
+			state <=  STATE_SEND;
+		end
+		STATE_SEND:
+		begin
+			if (to_udp_ready)
+			begin
+				wait_ctr <= wait_ctr + 1'b1;
+				if (wait_ctr == WORDS_TO_SEND-1)
+					state <= STATE_IDLE;
+			end
+		end
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	assign to_udp_data = (state == STATE_SEND)? results[wait_ctr]:32'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_SEND && wait_ctr == 9'b0)? 1'b1: 1'b0;
+	assign to_udp_valid = (state == STATE_SEND)? 1'b1: 1'b0;
+	assign to_udp_endofpacket = (state == STATE_SEND && wait_ctr == (WORDS_TO_SEND-1))? 1'b1: 1'b0;
+	
+	
+	
+	endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rom_bkg.v b/FPGA_firmware/q_sys/synthesis/submodules/rom_bkg.v
new file mode 100644
index 0000000..ce35e90
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rom_bkg.v
@@ -0,0 +1,236 @@
+// megafunction wizard: %ROM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_bkg.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_bkg (
+	address_a,
+	address_b,
+	clock,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire [15:0] sub_wire1;
+	wire [15:0] sub_wire2 = 16'h0;
+	wire  sub_wire3 = 1'h0;
+	wire [15:0] q_a = sub_wire0[15:0];
+	wire [15:0] q_b = sub_wire1[15:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (sub_wire2),
+				.data_b (sub_wire2),
+				.wren_a (sub_wire3),
+				.wren_b (sub_wire3),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr0 (),
+				.aclr1 (),
+				.addressstall_a (),
+				.addressstall_b (),
+				.byteena_a (),
+				.byteena_b (),
+				.clock1 (),
+				.clocken0 (),
+				.clocken1 (),
+				.clocken2 (),
+				.clocken3 (),
+				.eccstatus (),
+				.rden_a (),
+				.rden_b ()
+				// synopsys translate_on
+				);
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sum_peak//bkg_sub_mem/bkg_boards0.rif"
+`else
+		altsyncram_component.init_file = "/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sum_peak/bkg_sub_mem/bkg_boards0.hex"
+`endif
+,
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M9K",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 16,
+		altsyncram_component.width_b = 16,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./bkg_sub_mem/bkg_boards0.hex"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./bkg_sub_mem/bkg_boards0.hex"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bkg_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot.v b/FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot.v
new file mode 100644
index 0000000000000000000000000000000000000000..09894291911a6d75c39fb10e6d5a6ce16d55d8a7
GIT binary patch
literal 14888
zcmV+@I@iUE6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM3^ks!dyWycWxWCl+QY%snC
z%r(XwoL5In_n{c4vK@ARGVf58kZ$)>j4mVLoop<FrNL{DzF<*fh4Yc-cgI7FY*B4#
zNtQEm62?TZ&DUHVPd^Q%Xlb1jxd!QJfURF{SR;M9GQxAc<N-vV;+pY1gK<w2)>sn3
zD~ezOB3ZfIOKU;Dj5D3?^FyIU5t%|edClT?e*(ZS=u{g&Dy|@zFZnlJul_Str1jR)
zC4Yiau532=2Uf`si;}5FsceN*iSMy8mvDpcC$Rhe<ud$ok{lVthmSSrvZ=f44&<bZ
z<unK97P_W)H}n6o)n)>VD~8*ihG`ipYuL3~n#Sp2DK=YN#X!s%f!bc}%yWIdg1o%v
zUKE1eOGePi0YZZHtYMw^q4cFmbWy07T7cwtsh@9bUq6qlF(rQqA{$CfNVnNFMykf~
ztsPbtTRk3wQ^sHp8UT4pD77SlCkQ5620jb-4-Ps<lAfeLh!}fEz$#cNdsp~o0?b=>
zO^fM@XBzo}D5TRD517CY=Tj7!sC*o%;}U22SBJ#URlCUag5|evx`!Q+BrUw#5sCKj
z6<v-y0jnBGgZ)z&S|TwD@|S}*skR3ytXn^x#qa+gW#abTvZm1Dcjpc&{9bjrtP80n
zPk&;+cPt7o5>W+Lsyb&@(fnI*np|nW-K@gtm^{%JtD&zJ<Ex<H^%-~z<L2Fyrh22O
zk@r}#!QwYUXjaaVgLi9fop@5G*Yrw$o~9R7EyVm?nkS2Gm(BF|S$IT1AMtVjMi}@j
z^rnH4bZYwgJyY2S<Ti~W1ntBzZW~Kca*ty6biEAAY?Fj0PU6bt%GYT_=6TsOQO#Z_
zXCItEaWT76ukRRZ_!l4xt0P-`J#ju0IXZ|@J!q*f&`o+r(5Tk<%!BuP;9VUp{QmD>
zLj)$8onmMQfx8x(k!4J#LAW0em!7IWCbPG0I0o7vbx9-!Th~Q-`)hT82mxA5h!(ZD
zqyqxtKQ%tgc*0`p02bXbz|8M)(TgzA{DHYIR~wtdiPkVQ&!F5rZX}H0jAQeTVNbM!
z9(VvDFr)B3!_zVuo#xNo<`axDN}zpKL0e{oDdr-TgWY6$W_9b*h!V=~KLUw$-X<P>
zaYQ;&ZPclpg)QUZhWVU9({%|eu>8Z3$OE4sAkrqko1E^NdHJBSULd+bamgmj0L#1M
zhcKHw?bV?<7cUInQnv_N8+1aq^6A_HtMA9r4QHcdn}IOLw!7e^LxhGy@(UUwr*D_o
zuP>3{*1u_~?wB_YtoyM92{?r*QQ^L~TYrxX#SiwXV-8)B%30t|iSL_|*SqXllwfFS
z+Pzq~wk#x(2Kc;~n7b*=)V0J&G?<e_O2m&Um&?6UesRP>)lMY117<-~?Q9|!jn*)g
zZc$WTA0p?HAl`6pzPCOV5F*kqt>N?zFNmx1Ee~6zi2JZ`Z+mfNVo9{P57XFCO#p&r
zxxTg5?J9M?C$M<5LhDe4dNrme>#We(5}dCqY~BsaS6JRo;#%J)jh2(IA;4LaC&9N+
zDn2ikc)5%-Yl93uGqZ|xp*Y3^rM2>heMZGbZC%95Ce6z7z6GkXin~@p|8u10kfhW*
zHOB*<(Gg;;Pq@b?3EUL0(`8%}1g+@2aZh#>5L|(;j7|0oMTkB6=?71aqQnN3&6#*h
zp14jkEK07dQ#D{~BkX0zbiz9TF-SyNmU-lbjJoHZRHx4KKjNR0XC{GYiY54#pM)oo
zl2db`hM+_y7O=;knG|Rw!X}O(+b6I_p%M2>4Wwu>6FVp|^R(l=>+fFQ#rL(nWr7ud
z8DOToa@WDgb%Yq_eI&$%%Jb0;v&GV+(-e(EyXP*xWCr-gWIB|Up8p7a#8DHUF#_d+
zP*$4B1Ev8&1eqB#Zq*~7{AjHCHxNAtQSiDAO9L<woNpWL{Q7wAM4=|U%a3$Iv<Xug
z+VISipPu;A>TyMB(B!4v{KnWWG9dgb;u-VB!GxOj!)5p+z8WK&Dbrp8I7LHeWOlT)
z6GotJOY3zqj1{*<z28pa3%e`<y$)(8Ag%2MumZ%yditHPKvvKNQup3PIi%X_<>%~V
z0oUW|;+?N3p-$0E&&{?8vGHlzbVc^}eH;}N5FnAoAV`7sGqMNAqUd50-xbE1X2VD>
z2Jg{N)~YVi#qkb$xH{VIdfuu~&Q$(e1H%2#M#3f;V-@)wHBD233i(MJvT<#=ExDhN
z^<VLMVcFag#JVd2G6KCB>{`~-eL(99P^N@6PI0;n6Z41FVIYTpLBJ?L9?$iHb`=AN
zSjo+M;8)hOl*AEMSB$BfCq7-&qRV5YppO6=X*<H%N&u`wNo5qn%8+s!_L+XK173us
zOG&B`<ide1RR5Mkz6;6=CPrqHz%j*?TZ8FE+k)%!L+e0UYYj5-C3JF0bdrcroO{tN
z<l|=y6y510achoqVvd%~GlZ6+w2;9Vq3v8odBaEJ8U_^J?3j=e>;e*Bg(leT0aGpU
zxgB4NTcefN>9?jOfIb#<5FT*C=RPgE<oVgRI@vO^^}t`-<0cDXrD*;f#^Qcl&=BYz
zeC;Lpe|2-vjDx6(-?bsLM_^Rt61gX!svh#2q@!@`GNAjy#QYWBM`BUJ8C`PS2VGc{
zlIx~RCXm)0kp|H{S#?anD=5`Q*V8zpOYwGx21x6zcXW0bCf^o%kPJMe+2UvwsEQiS
zg8Fim5{E#G0so?Q5NABXfFOEa!`ysf&`469XhO;3D3+oNk(cF~nkyCs{X&p#zIJNE
z{X>oC68PQ<Ge5-Q#e_{tWdn;%!7?~>5>(%@BglWnZlwK1Er~n89rR9;i3SMx52NJ;
zO(MY&69$P~aR}$40YU;pOjod27P<J~_JwRD6janR{+#*}d*NTtO}3=Yt2=*|N%8cJ
zrCOod{*hvBx&k>-l4Z<8DlhK>%Zhoa<2R+Jyxf5JGT*o_&AIhXojAeOzNjl3U-`of
zSWBtE!+l6|3*s6Yx`}P6k;z@%@*+A|4>R1KuH&=_EoYhv@8gr}3T3f2G8~!=%qH3#
zHdLVUn&*PKM$5B=s0(X?dT#HW0${AWGM1X$7_y1Fyi3499YAK^kr#LWur=D!$i&g&
z^9APM{NHE-i<}?X_I_xotoCSp_k{Ie>9zR0GdzoUm2=1$v}Wb#&0BA@Bjl2UyuAY)
zTyF0W^%~#PRiATEj9z?9DlAd!n2zG7>v8<-wlIv5dO7|;z1F_MBoMAfIjM@|VoeQT
z<VvPL<PP!TAKidW=>?Uc(QoyM$!}#!`F#HalWC%oRXdLCg10fOG^L>>bm;EZnK2ue
zl(NZqF%X<=%UDH8B%uLtYc$b?Ko=l9t<#(k+E(s14)E6D+zR~gMRbDxNPkO8hQL_1
zWm6oihb@Q7H4Sv0^<3gA)xjNo`k^v;A;ljb5xQL~RTS`NeYg<G@q(V|v28i+j2_SF
zqT&*gf(?wa1`D`zXe8U4k8z_E(==J4?r)%!JsTVy0}smNcd`ec;uYyBm;6b`c6HD8
z7Y&sepQ+o&LL8t^*98W1DWXBh#PB~OZqVm@^#sx}?|W^X3kt-4tGiakp{3^U(QjZE
z)%Go=*m(s!&B|{f>z2Z$c+>2ngoy(L2=6_gkP}SeeGywdQ0F4WaNrKO;l-_BoXd3`
zt1`Wuf<+OS7a~c+H1)SL5~-D6X%I`WUy*AK0){NwC`_s`4ZFE~2%732=e8NthO+hc
zt|rRx`MK4}W4!u`mI8-hLNgZa9RYJ4HM68w7ho2Onl>-(m(((%x=9*6RNrsq#fDti
z>S&O832`0`Nzm1_sZ@;6GJL(|f^LQNM$bx+&l_ivVAW=for6*=q0s?QQKukOhxvXw
zihvV>h}ZV7nSzv@9;6;QANTbyxK8rvsvaoX+hz1`=~!(LPuH5~9O`tq0N?!&xUef<
zhLCI*E!d>GzE#?Q+U5Y7`Cn1sH)K!qlT0T<v4Br3UP3620hWfT*6(iK{+meyxw1?v
zginjNy-Unn=c8EPHEhOWGJQ!Npks1e8}{GU6R>`r_!JyWewGS;+Nmuq>7rHYvZb4w
zA?8K304Ccff6zx2AR`A%RALK-6~X5-i%zWynWH{P@ZqgPv4G(vFBKA0&^)uraQ6x>
zE}L4qdQ(&c@bpmXh=!X{0Ef|5!L>eejrH2H$ovxXfz#{pu|lH;D7;g6AOw;9uG5-K
zDgxUnG2C18vlxHFFL{ssLu49P=Ira+1ZK^Ypv=(%u3k^n>B`21sq+~G>efDE6j^;f
z%4yfi(3e5H-EC3b;zx*v7wR_B<atNp%2i6g8xlU#31m~{wlX7-n!8iVZe(0IW9~>^
zmeqqn66MadULY}$O!2;oW<Hw7d^`x#9@XALq63o9-hA-?mS0hLbv0ql!8p5d`#l{d
zDuI==8&nl*LuM-lc@U8CXi?GzU>W+BvwULo02bE5S7J(sk8;qohx^5)6Kcn+#n$I|
z>S><Lgn%$y;=!7L<70a!t^aj(p=4$73RqYwZ@JJQD)4vvssa8@AqIcL2@jNU*Q|2G
z=Sm%M%&I^56el_jPlL709%Xy#IBc1FB|P{WAk0jY(j0?m_tp|_Id)iYkZdK{CZk}Z
zPFFeBa`82>0iF2uZn^H*WWA;}JFe@pdhF_`#Oz{DP&j>)zf;083tnrp%E!?=I2ofg
zUmC$9uBYUUp3N9Sbg6wP-SODEqA%2~TQH3@iP$r-AA$d>3)!<nw+;%E4c2z8C3hAn
z(od_;2V#3#!%H0Z0r6WfNM4l}7@b3i+9_sQbHBgMH$fT(v!>H37o#=8B3B9FrlKJ#
z?FF)^A%4*Nv2!4YK)l)-(3b=r#cP96Z`yk(Jp<aiqPT+E<CTR&-S#s2O;G3ssBWux
zoWg85E+eZr+Vu!=y@aoy;+_+-3q!l~-Wju2N9fK7&qdD-6;Wwg5ZF|%#kE0dA^-Z_
z;^Mmu_egQTcL;lWVh*AUD|H7O2X<DBmn^k1_~UEUnJe<Wen6WEkX+Cx2J?DwZiFf&
z{&>0Dznm9F+Ym4?kva`CTFXrnGrj$9U_lByQyjAOD|QP7xlq+&C1uCb5tC2Li%tT`
z(MNg&Hp7TS6)b|QLMx7ah3x^xZE4b+NAzZ&9K}Roskc>Hh!&PHU5ky3ArGo(i}!O&
zo;AOA0TTp}Di3(3tGfBH4YB-A5vNX(<3;#{P&KjYQ|}aa`=#l69St)jtC}TA5*^Ua
z*U{&5g?8p7+?YxG9&o%qtCpt4YwZkuQS}7Ex2)&9&HOB+A(d}nrnPuFDV~M0l2E2Y
z6cgzIPY%EMF*X%gh#r;+u|<h3w8Gn_5T(PXpUKCCxmC@XQr)yZm7izeNr@o|?{Dbj
zN+l3k<isENd?L}(tt7+NDxA4ag9Pc-9h4Hyv<Edq%LmYZgG|X2^%)0I-*J`qmfcvm
zaoR&WBC_pI7?*SbaBrvdLs^cdJqVZs%q#jZ(vfQg`RrK7o%GK{1N24&w{nSV!L)D-
z)wkpScsw4W+fMLK2mtr$S^AJpa$pyH+rt(rt^{fQHXg52m4>I%?1eW(I7TWk4z&Z+
z`4O|B`7Q!UP`0%&w#MCtJc8Z-!`nBV-3H!>zJsB&iNVWW6OROGqonczl$>&}+BX=d
zJUS9h02)I8%k2n!18hk<a`f&-DA#Er5Duo#O}3eWFfn&4sYI>)x|oyHG$t_}QAxN3
z#{_+vjz?3uhV-=h_q*3#x|~w(fNMlyF#MEw*I0t3m#@2IwNvmT09@W1GG+y$madi7
z&?IEJDXV%T_pNSL`r+Et#?+;(u#29Q85XH3$LPr$g>@s~7&A)X{}V~dS(@kHyw<8F
zQ9Wj2f{e7S4+ok1qTa||GYs@z^7Ukw#eS3wsu!MjMB^K2?kec$?h0e!A+CERa6f{N
z-Kc|^^Z&BcMr5h+x#@#-1}DipkuZ!9)ss2L^JS%F`A(3=gk*BG*QvR_ey5gv$UK!=
za_H~mWXh7|GlqwTA|6UE!F!Ff@f)6A#dgl<408C4)TjLzeiMf^2=@IU+%JW;$>Pt<
zkzl-rBc9JfCbwo07Irp0EO$@mf14dEfQite_{6v#+N;Iiu|P_IrL0a*=3&898Tol;
z8<K-sOK<Nn9xjM1YJ9HSV}_w#1Dvy<?ytCBQEi(}bwOMZzm(CgGS^<(bGM5W?f5)~
zN+pUmpoZ5Ehg9v!8-TMK_pV+EaedlDJ#hHa6_g7aHG-#DV1&(w!L)KT%211AGR-*?
zqT`=!H}ZGj6Em;1Ivo}TAt;NgW}*Tp{4QoDE2A8Lj%^e%VGM_<i124uv3ycRgvwZP
z_Iac6QD1Y2<Sa`vmkgFSN(36fR4-i=6`p|NqdK`{bv`w|{ZucHD8eY2M+y-{BCEU6
z>GLP1;+S|%{lPxkOea^vzy_(*xh)2`yZFog%BX_VZ?0+_&Q)H^CHVzTDYpqgDUo_r
z5o=z}%AjD;F^)*vsKtrkGq=xq9Vp@a^y;p)TcUUkDE@G64hk)JEc=5u5n17BGl2)w
zLh<&Yv#k3Uh?i0_;x6XB8%`38oi<}^S7YxJy;R_*Tfl_@^2e$=-S`|l6zx+<#Y(;c
z%6@<Kwv@JDzD;35{#qQ9a~!;qLIwQKtEwG9*=~8$^n72h4EoE{|GAgM_eOvM9inz^
z;+}%K^I~?=-~o;8k9)n%9gWLu4pYHnu7X;3?jv)DWKZ-zJ0%791rFB3K5>jr8Bq>O
zp-aB$?Yj^@^y&{s<8(}(h+kBHksz+omak~9l;k5$uwpH<XgT^!recLfj!#eF;DiOV
z{pWDz=p;WSAYIs$HQ}RfM^O2v7n(!i5r3aYX$kAzkIl5GLbN0`)YBiUFPmogZP7r=
zC%AE|$xth8!2x=@%8_YTz7&0L{dyx2YNC#K`yHeD&5|FX7kwtuAUeu~vp>Az0b8%`
zR9RYgGNerdi!s~Sx8WQmDIprF9983R?15m}b`gms%*}Vfsrsx577}M^2Xu}*2a)nP
zMN-zmNEkK$>twDY4Hf;5EmIu;96~qtRuAdzK#dOgKQ)f5lsP|imSViN>z2O-G^<7b
zEeDn?_d%7rOI2AJ8nIrb7nN)4mZ?Qc8vKwM4ycZd56u=l;9n4`4A!2j1mMW8p))An
zOueJS8c?lE&v@aZ-nU7$<?f!>;u2{q&WB20VJ4luuAt;c8-ecCpQ`*VH26FIQ~gz)
zjcZLU@Iu}!Xvb7<H<`i!`|IqE@im19{TBJ69vh9+K&0(~lYQ>Jdn}&OpT_PA$66vV
z<!leVp2R4q$OU$9%57?I#*bskbK>s2>cZ$Bw1xlhqQbE-qkjtZ$9aadZ#({A7ZKFg
z{DNjTF8JX;5&ljt_Q4+S^3U$=npTT1!(d14sP6QS_@IR}FIrDdK{*lumxwc|7YRb7
zC0OQ<9hg^u^53SPT7nHTCF-;cQb_L>aMbJt25q%KzrcC1ELvV_1<nPB^sCsarcrrz
z>A`erX^&_GLk7AowMv&ObZsu!wR-eE2*gU1@&8kVb>s8uEqMK$ndiXhxi55s{#XGh
z63=mJuU+rcu8boGA?-(b1G2TK-e4{5U`~8CyGmDjeRFXT=NVpjR`vdXX}K}}H4XNn
z(Cmz_vv1N2Jm<qxAK}O6?`FO^%-WV}fG!2tIlG+0n3*XhVFk80<wmlsy1(x7J7CH?
z{;{eJXsLzD@p-jQdG3bNNvZ2##4Q;+j~pIwzQ6+wnVTnungxADPl7-sZhdGy0OT+{
z)qiG5n0r}z3rg7($r;w6a-vzfwJHjrd)oHjtZNx+XXq0c^}iE~J2!o!1d-Y)ma7{!
zkye(;LGv5U5JA#+nU(e^zVe6b<`+o6+mT6U@4OuEy-Q-2?;!5uhz-;PcTSh9PODL8
z5HP6@R3e9aHm;t7!Iau)%bQ%31GCKtBq%#VYUXrWF~soYmP#R44<9D9BIiHVd5R->
zj%o}+3*uu^uLORqGHa2vrLq)EuV92PjC)5Nomet9O2~-8hlb?W_IV5VH0t={ut0Z>
z{)Nx{P!dE8!haAxbI9$Elm)M%hu6McnkxV#n(uw1(rz@t)NThU&Uf52DVHTx{Dd`*
zOqewJ`yz$6h(q@ce$KCb!`z%aY!mAdejk$WuhaWa^o;cdIP(Q^ExIeNimYto;u2^T
z)=0(q%$7j8IEyd)pLFhOhW>YO^^)wA^-YMRe-K9(kQ|t2!5u}h;@bfz^g<eE`XNLH
z^Z2!k^@4@O%o8rfS^ciZJ(4=(`5Md>T1b~SCxp8)5uX<RxcYae^WGhgZWe!OJeGHD
zsHFm++gT{O)hSxkYKlYf?hXwX?&4~WoSnv{j4*{IUJ(NA4h{|4G!`<IXzLk2^)+nL
zaxT<Por;qvy%_+_fd{hicM1qcs?Q(0+46u-?<BzW*8qDlA~+rGs035qD=Fm*m--YW
zOF*x^4f?d)F)3<Qt^jb{<Y9`Wr<2D}kFbxjD?rghE(?`LXQh1s^nT}yMST~SxR}^s
z3>i0|ZT-MQqwY_7x;0GXig31)HM0C_*bsu)Oki<CJlf_Syus$8MmrdM92@&xJ-V?=
zT2N%V21)X{u@a@k18t0g^6UnFF<iS@f+}fK(3*Rx4*@BMOAVfJqA~3QWJNiQvZ6;u
zj;GFLP*Iegs2MM8!ImaDL$Q4os`fI0aAZDFezvhzVwTigY~m@Rc;G0$;wQdN?vywD
zHWD!XXfCdtA6`R+&jY+-8%Va(&?D#`qXCF@cn(ob7cn-xvrf-a0p$>1e0}O*XT1=6
z6m%ALm1>SV3)9~VmQN%!Y9b9oI!qV7&A%owSAGYn1eB8clZSmU+eOIMPnZwW$x#};
zWRyTho={yh=D;39<NOX^bvrcSCuvok$Sguyf059^R%0#0)>|x`$#_(FE!+3-8yuaD
z(oav=H;wC_{#Dt_GTZ<J-lvSuweX)ALbdmYxkqXM7+YA1Mp_0G04k+<V(+pLs*O<u
z;YZb@?~9+apq4d3@}&KF9%;?a;#gg~AB{FE54nsdb~8~$ke-8qUz40nBF!88KWcKc
zrT}o)=qJXvo}woV+$iQtC($)w3H5d%_2$GjVX_#!T{O?u8GP+slC_*&`9G0Ka~dR2
zn$@@h_fSz^hm^SEhU_-gd0enTmZF2^9HrVXpCKZuunJc8cELpV)V};a=#AWBi=uOK
zv2u(=yP65D4pw3mqZJ0zj@Nx5;g!R_%K~Vuh)mul1JhLvwH5?hAdsuA@|=hN*YTL$
zB_0KaitrcyGZ~)b)yEwd9RUfO{Fuk=Cn?dj90+*A&)x34nqWMV1rn1rc{a}=LstZw
zZ<h0NL-iJy4=}t5OrTp9o!*i&iaS~t0@iwEeew<U&WNWd*5vKrW%d3+jvBs3wG3`J
zHC>lylEaBAzHdtglcPz$oRN}$qVxR3{Y(I^*@I)Vi5pl!poQ>#gK`RF*Iiw|Gpuae
ziNCTt2ZlLO+j+lvaoUoJ4fm0u6p=FY>#+aVyg#t;%GcF{jP_M4adiN7<4Adu82hXL
z$D7Y3b6E-TVuP#`NAe9hm{aj6D`*75UVmJUB*>Eft5$YquSa9wmw|J~uHKqe(NH-B
z+{*)ptuEgch7a-GR%5&%3K?*B|LrvhE1B5(yw66GTYpZho<f^&=C**mP4)!!y9Ij~
zka?<C4=q!8GD4KhKB3=7s)tl@l0@-{pKTmEng82!OllIq*kFdi?-!=@E8R7d?08l`
zhk@r*W|yAigg%=gqPUtD7Lf_$PG02@nFuCuu%pcG=sN#fJxyCcPRH}m&ZDJ@f@Opa
z$M_AUH5a`J=6H^(STnVRsOgrPJFOXDuNfx2TV`Od0DWb|z0ztDeszukk)Z{q5*afZ
z*7%ge3>GG|bp7&HIMBZe(l2y^1M@+h>dGlskh(_SjLEAV64I%niD4@+CFd*c^9shY
z&yFJ6g;YAzg(6-QbcrjXh5K7cthf}<4rlqE+<pcbaCM|>s)Z>7H=jl5kB`G`Zr!1Y
zD(Lg!BwijN6|cwODnM+MO@?8;`NGYlNttz%bE?8T`wR1YVC9SBxU7J;_wq^m&k)o}
z!;D0wTL`4)WCr+}%TcSVn<lB6vYo0}Aci3~i*DeK6|+Xx_7Pku*W>r-`x`R9_C$}b
zn~0h4Rx}~G0Nu=-18>{r>Q7(2EJ0E(66hz<B<;rEa<8)f<E2toaY4p4APWkCH4MqA
z>v>drUB)sGvsx3elKTIXNYEJr=WL#mgX3orLSf;a<0{5U)mV}j6AtN-Ro6SCR}oVp
zy&40%8zC!?B2^{97BISp_g@0%kw<&XWHz$WG*)_>F=zV>?IGB3hV>o7N9DH*v7Xj{
zK-tXx*hcEbW7_ofw9cZNwj=afc)1c@=-_|}-P8f5I*Vf-Q*jbCSH8H}40DM;lUEL^
z3np3h0#cJ~ljiZXRGW-)nTvjd-y;!Kwn2aAjK%tM+8rxW0$7~F<)T-9y=c>7A&0P9
ztft6LL|S7m8vqJxeL8z^33!V*7N-Y?eOO@v02(*`!!cPR_vDZFY&K}hl}x)j9~NRN
zuyBZp1Iw`X9*O*Hb||N10OEto)MI~#BIksVslmbYzzdZo4mqRkC8f2fH4|5;xw-VK
zx`3srOl?XhpuphCce7N-NJQGpF$PRfKe%9N<_18>a_2`86sYTxl4531C~zVCdh-Su
z_G!`ndeFds$8UoO-6wxzhz;{zS$coAFCMF+t}`Yu0#Y0~8W;`wW<Q#Zrd)e}FtCNR
zJ^Vf3G>>5>>fNpG930G0C{uX{y=<_C5e{l>wds|(;5=yI{+(A^R0p#btPXcyhC;*K
zr?YFzzxMgwM9@B-JOZUKx^s3UQjo;A&-q9SG_9y-((8FE=)nHn<h%P^gR}c_yzW}g
zOro8?A+WoH3a1^_(`jRbpc)*p=|^You-)N3CbA`~8)KZ(i~}1_tm;%BL5sIb7yUDI
z+{UMg&QqM{SYZRlZi7<wYSfcB;tliz3H5!|c6a*IzliCCA?e_05FDeG{th=s^4KZC
z<XN~NOzHoQ@`~=s>uPWBowf|l|8SB72$g3YM4O?mneQE`kMK0~<F>Yhv?KxcU6=qU
zi|~Fc*Zo6ZrQ0$5)!{RK9vpe(T!yL3keSe~*Z^l`3cLE0`?&*$hL+!Q&3e{gJ#cr$
z<f0`<p-xr@H-=K&WzeMSGy(8<#;|rnPM6~-GEz!hF6y$Ea&cI9Ej;hD-pQi9uO+Z_
zS?XDFdvodP)b`t#?xy;$WH>BKFsH33cn$#q{^~9rJ>6ksD;h3FfP_j)i<PpQOU%HJ
zHZTLQqM)osdY18c$ydR@kBh|+0z#t!BDv?Mm<D=G0$%^=`(6GLeGu4sY2ba$sY=1=
zF9mAevgs@lUPVNhG6-C%sb43&_4<<#!HY7y8M?vs6dvFI(8bhF^*W0EJZTy{HdZhm
z0f{Zg3KXUcZ=8;PYw42%6O}T)>3X2##Z>*i_ILnAhkyJL@G(`?-hJ++BPA3?gYhg5
zkI1bL3}%PupufJ!wi29hPq6Jv;T<A>;j?{xc|C9v)|GkYed9@gzpzQ57Rq2?5)IEz
zXMGHFwIB&F%%+!g!eZz)hHFX0|1ts(WdMc!L{eu1R4-VAb~fl^%Kct#VBqky7;(GA
z2u+T`^X%qJRR~!1YVP;e^X_&i_!bJI5rbyv6&|{BG9XF0UW8=P^3aN;j*I_GG4<GR
zgdS7jIPIUH&(XA1DO;hC3D(l-{!Z~(3@x6WjOHOOPI@;sp@5J+J$CwlZJk1UucX~t
z9K~3w`$QB2muG6{T`UWt##a`Ct@hV^%Jir8ng;S6>Q$YPZv_d{!?5il<$F1uLpg3_
z$ioGOI%#VvB<<lvOeY1D{P?Gm&-o_-!Yzt4hry1n`A#TUx!$A|mW~~6QQX~*oHL^o
z2Il<L2N8*4ZZGzV5b<M4x@I^kT|x(WVp^TK>I3_NG+P)|t1E+SV;`<d-u{IS!NY7L
zJajy$p4gn;^dZ@4mq_^#25`L^a1yPN-|>eYPdv-F9MCXyOgTSGJ$9~8^6!R$5NR9F
zyHT6NkB?1qypwhf8w}=G7QTD8^MKJ|mmoy@S)hB>5*JxpBKtQu8vJ<<yy}owW$@0l
zM|U*^ahA49^$i$VHE#IqS`U_RX>gQE!jb$q$*v{yC=tKS>!dODF+d|BHDO%?Ur`(0
z?C2kHaw7+%_<bT>Wj%BENLm(5wu;koMHJYJ6Y`za%<iG%c@Dv??K#nvcDSu0S!na~
z)5wFNfSVT?Lh4x*_B5y=lJQzubBpVXbQy^)e`VdNET>Rxo^m>xu)Q+sC|ApLA1RG&
zG5gfnoq+lOkNCS?AK!Z4d+nNQ%Tz23Tr96Zg8P-7j}lqe@p=}kU8S9@qX>!6t72?E
zvr%D)m+5v<pl=)P#+ujjBHh-zgtGwHGX??IT-SKED}qoPmG)5}?ad%kQ4n@~3YC7a
z_}*3P46b1f$n<gfHK@l>Ivey{F9f@y*-$kG>y)AozjWWQ$cmTvg-O|iDYus+Rwt2V
zXG{H-cdp@9CuVx6oX)KuW(j$aT1q}VvJ<;zy}3VY#cAnJ<cD^Dfmf4=cPfyK{E4wK
zFbQM3Y?$|KmJH|?!JoojFox$}o%YFQ3P7c}i#K?7(9#DX>-BS*UR6BC@QHm|FdJl4
zhKIH++Srh+`x%QMw+D*HQi6#1SA~U`dfL~#6Ho1oy1!F3-HH}BRAUek%(vLZocoC<
zi5sBe>#*Bg_VcH!#9Iicx&tt?|1I^2#!@sNwvFvE6k$BfeSCXx%297s2UV6c*eIfQ
zn{JpCV*aibZ7(Qj1Y9C<MnT^5dLsk@GgYJCt2PQ0FDOFw1BkyThdUcP$d<X8IJGu_
zS)7@MLYr_vn?YHwrm*>p`ukinmv+6UGmTLiLRX7bHz|KEb5jswiKYr!^i^Y#k;FLV
z&f^42r9CORw49zVYs8-&|CY5Um4rbh&)>-p%A~Jn8Wg$0Rl^czm;1y{PR++~NyY}0
z0jnR?qA20`UMfG11V-bOS+FB#?SDcU=iJMbAQo0Ah;}5}!0T~#DPBRJH`*_8d1~^l
zHF1ukq=HCSY$dT*YH?lkvh@OkezD)U_=EJpKmde%TnyciXFz56G|}z4)M=TGaUr6E
zjEQXvuJG;@V#^->5R0ab;DzUfsE00i3=}l!z2cr;D|i|sRJ|DB2?|u3V?R}o+xk;r
z>(R-(n2@L%2`gyboX!sblKv21ImS%}7}?yhE8hnbQ&NPXbwKCJSThg^w#&?tOpz76
zm=(C=Z?h<mRSZ3rNt~c5!DJ-3jHfb9@eYI8fjGGlg;@lWLqVk7$x*p71#-N}L<*gm
z%C&f*_+k7U+1}9gFkKG~6oRkiO!KceZ_5o}P(}|lb&211yXQ5HlfFL*(|j7V<6&k+
zOxi}c1XuV9_pN~AVa$B-M@smpcW<$((XmeF#KI5Nz-oE7SRp=B9cFH-^#SIox!{na
z35ceZjiqdmqH#KnmEC-)i`gC%j6rQ(maP<ZBfkj!uEL_edN6jcX+>nmuFQ2_FQ1QT
z0;_FzX3Z=g%s71=IY&L$`F&3L91l4l(KRnQVx|#E_{|{qE-V$)FS1UO*3|Tdm4N!I
z44#J)%VOe8qcReQJ2YZsqleoxNgs#qVTY3TTnlRleh-wWh<cz7t&#%6Oy@1fEi@nY
zq9Sy;R7C^uMUnO1q!Gq!_e@MGqyt&?;cVQ;OA>@ePbr~ZBy0`T6qy2KH#4RVOmH8=
z{xXSD7#?jS0Hk!gwoh|uN=Z+fuc$0~qMVZYQa?d)QQpvDGTlg%o1fGC(4r;9Lf_(2
zm?;YtyJ^?Pbm-|X0qNiH$`wvQLR{?riZ1xii8FytrILfuor5U!QpQpjJML}zV_X06
zg81#CkK|6Q8AloQH>yk+qp&p<n>e@v5ZNNrK*to=CWC&KXp8CcIDbEmD0*#IN*7e%
zB$|?CNtaY+cko(2pZhGJ?B1S^{DS(lLP*4tTI*%=(vXWmN<$A}#~nL`KIu;C)T?{)
zC}weyhE_xCYfysHzPl@Mxv4HoB_+iV1cS`u#cd^$S~>DyxH&cQI8)6i8x-hYv;Kcn
zhfYZlfmIH(o@>-u$7tO?bfBM=hF3V+jDD|2LDR%GvSItXwHLnce`X$zbJDU<$LM&S
zE{d3=!L*M-Un|+g^gu}FekYu`D>-&V6C}q~#8~E`j~9}G^_Z)!W;o><yoY(UX4ii*
zzXRSKDzJZ54XQ>KYRsak#;`$(f4txKBll^<xEz-9sG+;X+%!!Q%Lp_|nny;a3&~wX
ztHg3pvwhPQawB*OppN)_D>jh6y$*|MTAW%EqGxJ(pBl+f@>%-kj_-Y8N|{7xFjK5k
zNL0641Y6XHB5OVLvf#51vlOSHJBSJ_z?&PWWNe=$uV0)0qz_taOO)QZB4z}h12H!T
zos{Op>6?qE=P9>y_0fBT;m;D3GN8lk2BrCs+=^b*yq8y+Ynh(u6|$}OMv&$A6dhUL
zedOacuhD=)kYu6BTGsPltMKQRRSBu%i=C5$VfZ#`r^x&rF-M156a#`#2-m3N{DUjx
zVbix=a_ZRpOS123r0m>BaLr|OMbv7!SJo8C<1&*%wi5(=tgf9Hc04hU7n^VImII*~
zR_MPGuX9G-*jKQJ+~D{>KX;uAwQ$r4pEOId?}y(?1Y*_-PwjE$6BX%Iwrt%|7ntdn
z*~LZPTpTu^_w)I-B;j0bzG%K#H})X*d)62!kTgy{Zr=+5Ev4861NDnF%K$+o-UW+a
z1KC>)xtNM~W&Dz@-jjMkKIgbP<G=XWrZ6EPiWW=hJvBhUagF6Ed51pyRsZ*22Yj!2
zIPfIpv-6r-t^Yr&%jdKZ5Jr9bF~eP)l=c98j{XQ~{KMvrQ-$Y4rlzs(e+r7YJh6)$
zeqzeJW-=wAj!laobs=({zA3=sIyYE@wngO_0sAVT!fU`2R8RgH#beZWRRj!vc>{rM
zoom0zl{rB8zv$8om)Rt|mE3aA(HEq$py0C<NFU^mW~pQ!XvTndXGND(`N}|@0CQ-N
zi&ycK<T&*pyj6BCIXs~r_wiFhG%4G_ovRC==2QS=QlG%jFIU0KdEQjJF>B9kp?_@C
zhy$HkTU~ahtM}3E%7?wm#@0JvJSHAv&NKC>oP`Idqh{O-ne``-RmiE5JO@o;2QtXG
z(VK(^=Pcs&Q{DENGqg@<jL+}@kj?9y{XN+DEqpN0>xLtqp)ml`qX{!_37-u(U-5=_
zsk!P-Z4~C28W<IV_!(oZ!Pp8{erz7t29oe5?TTj7fq>@ho_s#{Ens%KweR^P8*Adk
z9D0YkB@N;k<fIOwPHPd{mNwI5HDx1QKYHQ0^+t4tb`hxZfypZauu`t4Mdtf67%`F}
zx(RUnPUNaDm>Xv_GaWiC)6>QBTLm0FORAmRtCn_RjHIZlmo-nwz5T3?#nF(e)=D9P
zFuh3#37_XMz@lTy6e^~G^Lx3zDoKP9R6fopAG>YX8hFH-c?}ezzKVVp&hsugkDKem
zim>92#8w#Di<6n-S^y=x>`Dxys|&s)+2{n`+So@iaj_$TGoi2!?Z1yl(!j4I8JH(4
z9ui7R!TCKr)}3YKiwFHb20-4|gC^LJKH!Ix)BdIp^<&m22y3s`oi^)G`BjBnXaNwb
z04kmoU2hu!*s6`^g7t-v2<)u-N5jB?TtdEMxq)~W%qXcn#Hxfj#E0&$)Wt@-zQ#%Z
zrq4GGS{_OZFrXa`n_t3NI}!?TcbCMgfGdi%8=QCy2*GQ}VJy`kS0L|9+*3>@bv0@e
z^!`3sP0uC-TS$h_o|R<-iAOxeUNS8F%6wjZat-IgRkM`#01k*(=`k2R=`*((Uy-v$
zv4Tg~-^D5z>Y-lA^0h92^j)F7Jq(*%7yNLA1%MrGFC*+s_m>1xEkCfIH@7AwM~jqL
zVn1I@g=l0c>t26nGWya`9D#=*+uSz-F4~shb9_sECgGvau4h}B@2BhD(J5{nY~aCN
zm;p;6x44a0rFuPb?%4~t>S$PUhY%nt0re9aoKMf%r9X~3`vwx$lq;b9pb|%-X%N`U
z2OA&E(}t=<l=>`qR*cmMH87b({w?f=XOxnBkT~2!I=l0eu5v=Ek%;gzxrROCNZ<PM
z|LJl>IrQ8Tg$%{G0aO_TYc^6Oe(kTUSG+dtrHldMYh=fDf|%&BXY5!kZ3qc9<8gO3
zsJO@5vnno~p1VV76^Dm}#<iv-yJ0Sfb~1OCSr1d~D@d4I_*Cjc&FfcFS{`fevS5j+
zXs_b^k)IM|OT=Wk163X^UqkWa!$F2K3f3t`eNpN$_cJYG`vFn%4`#6#QZOcEfB1{g
z>vN``4`Ky%m%ue3LdMy>z|#JZYZ=mpAp7%e#C)YI4ucyJ{kuhQ=7gQ!`?Rn}7?olh
z9DnB4`@y7Of;h+9kDH#31&2&LEr_7g$4A|YOO3FaFs?^Vz1lFq^5@Eo?JK`j#&;sk
z#G{@j;rScZewPNsAyA!vO-1L9zL_N(7dWrmo(Z|<uile*hgSbsjZ_SlEy!5JQglfr
z@z5k6kUqQY#z=O#Pj*tnTOi#U{R?1FX~eDQ5~rsU4NG4FIOfj-zkwM(5FDx=t!AR|
zi-gFG$Pqngv@3l)(MxWV(|x2X+5Ph6ncBGgw?Hk39Xkn_%z$DGZDHu7`*}sJcScrd
zqE*|wSDrRGCvtHp$F)4=Hq>~>VKo5It;~zGgLi)~f*P<5D+qx?X*I0Sj)oZNOH2i!
z7arE!o7Vx3Tv-0IG-L@8XIy7j#TX0}@`V`9S&9m**Be1~+C0#rp_%=wAXKZIYn(j+
z!SWyH+VBvk`Qhg>aM$GsZe;u+fSI-Zv(YyUgY`h+LnzSDEp^>*<|+YT{CtTw--cDH
zJjQh=$~=7M$A}zDiU|McyQ_Z|FwPm?3p0DUSq2k=S->>{4nfcGqzUeCy?xS#cYkbS
zO7kKK_eQ}cAr?)qO0nPS5EBL(;L#!FO-ClJN|ft=OqCFOdl=@Yr9J&+(lqgxqX2PV
zd-?rD?*;jAUVvU4Rg8^ej98rBY%an1QUQWD8Xu4Mf4W8)5KXs;V%k39CF?r6n~~g6
z6;>YZ)4{emOLWvp`ZeM76i#RxwLwr?&3*E(>m_goaG#DCsk(Wo%+r?gca7BAl&)dA
z$kjmU<3N3&_4fjcjnkL1@6;Hd)vPFit^^8;Hz&4~wt$FH4;Qi-khebYPDdzoJXzxT
zsM8!<e`Y9Im?y@W0=v_eH62<#?d4)MYHMV@lc+!qTGCn%)}YZI!5<iQCw7rQ;_byn
zQlqChJma>y@*b-Q&&;F=H)dz&RhCQ$jNgS@3*_16MrDL3+c;mVu-ZbgJIRhc4h@YG
zmKrxRFrJKU_K{{mU^#Lh;Z0oBHFfpUTSRidjjo+f#xe$q+v4{Sg@iLKnPuB@l@u!U
z#F#C#YC`z}XNc5F!;4p^w?E-~!ki~1%X?s5riTbGN?UvH>7l9o8qR;7uNIb-i;@bJ
zr7wqkHOzPw<}=k9-pkt$P{i%dj3|Tu0U!%|`Dhu@K(vX!CV(|-e?K}#N}q*1?A2B>
zI}>cQE-Xb<D8y$}0!@i3WEA>2S{}=_!9CK@`R@?do7>^Irez|vd)QP%c7P)!nFT0m
z$?uOW{jMPe)aF=<Vf-MVO!=e6^gL^?8Y73b`&m|(scVM%x7S;;wN7XL<nOc95gjtE
znW-*VLD0{U|JsN?0tKIud6fp3hnN$O=rEzdkPLP1Y{E5F>_vSh7~^}a4E+j|)j{JA
z9}e(m|9enqg7U$mh}#8=Bf#;@pfyZl74}7C#CBW7+XOFA%|eqk272idw4;^6j5H6o
zXcPE4%iX2Z=XLIn-yMa%oVF>K5$<P22bCe2i0h5>+p=ZQ=*2iv=6ic-DE(O<V;9Xq
znjIMan9%l5`>StgopY697wpE$z?3NCIZey3avz+Fdq=aE>;69x*twIBtcQbj%TOS@
z$frDSA(V*t9=A#}aqcJ5`E%E!7SKzk1hLyzwttT3e{>T<e!k@wOi5X)eJW;BkQqlm
zoj|PFSc@&<I65MG-U__#)|c!YM`<`1<Z}ppdTv!66<YQ3buvL)D>kS{m?k?KV{kUQ
znyy~Q0+VykTBjj;5&)iE(MI5F%x=cc1SujtW{320Pq`kXzt^+$pD}UY&y;nyax|Mj
zEQ1*^T{*Zl#zZ8NLFc};A$=m{|4Ql36<<6bZQGg*(6()n=DdB}Bf)tJ&S-k4zuGV>
zkh*D+K#&q&V7YWN5(8g+owJBoh1T#7*%7~3plKgGjIrDQKa1{I10S#<_pcbNfwGDW
z4>TCQk5Y;dKGh`4yL>pl!a?3{Z;`|;kINxQduDczdC54Hq^&Z@O>j2r(?QD!()T{%
zsBwnfyB%_M{eyOgtFl6em1zffcksiSEXiKf8`?gMU>vGkj0!PMOPpegOg>ZAC|UfA
z5bLWG8|sY1v$kA^=6}JNH=1h~|K~D0>UetQ))t6w+EwZOmD;DP?wj6;g-TgL0;$+t
zPL37d?lNXB(g;?}@jxUb;|5UMEa|wNGCJ3Oa*Pb27|pCU&h*JvW21v(j+1dlwl!Ki
z?vFw`&-l*zP(XWS*b2+Bv{V5Pb@}v^k`FHkPp<}7>D!VV5|6Cn4bn#j<t{n6OB5Z=
z^DsxS0bc^vLMi_|El4PqDExO5*X-<B>69rAl7NWBd!|!s;HCnE8OeZL_8$3)X-hpM
zHSKpE=|!shbJ-$C;r2;0+3%P4+-3?l2Gfl@nRcN_z--GEBk=cLaI`EN1Hb6z7{ZZg
z(&5Vq-NXLKJ=sLljdy$~$Gr!LQmgt&hdJX^g5$O-ytY-JZ*(iKlBG|yMK1_`Cq}V}
z4dtLZSc|<XK+OkoUxu-!_Y=!=wtgZ2t(o5cs8%V?Z1tYThg}|WD11*2GHru2pMSX4
zXdD8}CmoOmxbg0hbx|x}VX`EIBbHEtgcDUDa-gzaC*wxB7%d)Ci{rO&;3v$I3a#4V
z@KbjWm&zpJnR_@a75h}k$k`PlJVyq<;}Mua*7wk81(*2ZxT2lKqQ#gU3^ba(p`43t
zqP1~b<)5xOQ2)i2%5g&!8_ZH;Wp(OV;LCV05S!5DOXaFglnUYcjU4vOtk?q@*M)d4
zlAWE)uj|HP(dimbcR5H(*k}3k^8IY5Vyvo|cTTR+VAsm7_$1sY+Nc;GdbeX~IXag4
zy>Ue95MCqOSYLRDK<f>vp*|nGvm3D`z4*G8#3nv9o{u^f1o+HD#j=E3kS}?6Iex%c
zJIXpSS@0fAkSgN{yw6N%?C9}`x;bMIm-KJt$}y+C(_5^=Ie_MjK<x3(X}V&r6Z5Kd
z-0!2UVo@(n3aptaN_@FJlm;Oti;Lsnq<4y?8ki)d9nXcJ!zu|o-yU#?eXX(<z!etG
aVfhZe(K_1=@dTosB1c>9LYs)WS<7T{Kksn>

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot_avmm.v b/FPGA_firmware/q_sys/synthesis/submodules/rtl/alt_dual_boot_avmm.v
new file mode 100644
index 0000000000000000000000000000000000000000..f8f056d533227feb118528fe273946d246607d6e
GIT binary patch
literal 5520
zcmV;B6>sW`6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM3^ks!dyWycWxWCl+QY%snC
z%r(XwoL5In_n{c4vK@ARGVf58kZ$)>j4mVLoop<FrNL{DzF<*fh4Yc-cgI7FY*B4#
zNtQEm62?TZ&DUHVPd^Q%Xlb1jxd!QJfURF{SR;M9GQxAc<N-vV;+pY1gK<w2)>sn3
zD~ezOB3ZfIOKU;Dj5D3?^FyIU5t%|edClT?e*(ZS=u{g&Dy|@zFZnlJul_Str1jR)
zC4Yiau532=2Uf`si;}5FsceN*iSMy8mvDpcC$Rhe<ud$ok{lVthmSSrvZ=f44&<bZ
z<unK97P_W)H}n6o)n)>VD~8*ihG`ipYuL3~n#Sp2DK=YN#X!s%f!bc}%yWIdg1o%v
zUKE1eOGePi0YZZHtYMw^q4cFmbWy07T7cwtsh@9bUq6qlF(rQqA{$CfNVnNFMykf~
ztsPbtTRk3wQ^sHp8UT4pD77SlCkQ5620jb-4-Ps<lAfeLh!}fEz$#cNdsp~o0?b=>
zO^fM@XBzo}D5TRD517CY=Tj7!sC*o%;}U22SBJ#URlCUag5|evx`!Q+BrUw#5sCKj
z6<v-y0jnBGgZ)z&S|TwD@|S}*skR3ytXn^x#qa+gW#abTvZm1Dcjpc&{9bjrtP80n
zPk&;+cPt7o5>W+Lsyb&@(fnI*np|nW-K@gtm^{%JtD&zJ<Ex<H^%-~z<L2Fyrh22O
zk@r}#!QwYUXjaaVgLi9fop@5G*Yrw$o~9R7EyVm?nkS2Gm(BF|S$IT1AMtVjMi}@j
z^rnH4bZYwgJyY2S<Ti~W1ntBzZW~Kca*ty6biEAAY?Fj0PU6bt%GYT_=6TsOQO#Z_
zXCItEaWT76ukRRZ_!l4xt0P-`J#ju0IXZ|@J!q*f&`o+r(5Tk<%!BuP;9VUp{QmD>
zLj)$8onmMQfx8x(k!4J#LAW0em!7IWCbPG0I0o7vbx9-!Th~Q-`)hT82mxA5h!(ZD
zqyqxtKQ%tgc*0`p02bXbz|8M)(TgzA{DHYIR~wtdiPkVQ&!F5rZX}H0jAQeTVNbM!
z9(VvDFr)B3!_zVuo#xNo<`axDN}zpKL0e{oDdr-TgWY6$W_9b*h!V=~KLUw$-X<P>
zaYQ;&ZPclpg)QUZhWVU9({%|eu>8Z3$OE4sAkrqko1E^NdHJBSULd+bamgmj0L#1M
zhcKH6Z9VWx#?FK=i0do*I_t!3|5S$+mrny`phRj&jN>snTp}VecJQo5x5<5d#x|C_
zu|k2P`~7s19Zqb9wr>m23G7?!f~QqRZ0!ZO(W*8r{0~g-9Hw(ZES=ya)Ekn~p#``h
z)D*JFWK++&3kXS|I~7GQ`<?FnrTLk17>p0x<cv!!FG^6BB&AP_sOA2E0Ys}MMV_(J
zrxS%*sECWVax34pO<UF36hDGbbg`>IYJ4ZuP#|;GjP<tZ&>fEDB>t(V9l@mcXxySY
zXlX;qq^4J2RxERUF`#bbJ%(S6FU(XMewoMzO9EtLu#x_k22!e;B*J(0s^<q<2Pl&W
zxW~+-c(}^xz_69AK2ymKiBG6cVax4WS6OlZ80~U?2>UQ1QRtT|*M#J1Yg8`U%ka|S
zvTIGAuW1g~*I%Oy5*o7>%?}B*KQOEO2;_5xec$*%htL-ib2Ksl$1le!D(^F4C}oq!
zy==*jUeHNBuP!ru+3*Jx0akH2@XLHU0(Gs&+HphOhLEk#q<j0)&L;z@t>ZZtjiH=b
z^QsTt%s)nnpvV=Qvl*eEys~{yoQS}(>v#mjOPV^TWmvD*DI=RkDv2wqK!W7oHw}bs
ziIklr;fm$ep{r`U$QX{XXPq0+;iFp~q;00M1$<gZs6rRNRTF~JRjPozq?Gh5$pbwO
zIwMWgEP#0UI^E}=eT-fC^R<D~jCtDV5k4X`Kot|(CDvQdXN{g$C}`h%@gHYws*Gea
zjHG}{YEtaHqGXznp$oXtm!Pm4*h^f(TwDBuH_yB6ec(YaJ|(C^J~YibLrX)Nxptm?
zHK8z)W}j-rE{fv5Xg8+i=(I(KvH_z125rLbu1HgXnl-(42cMw9(3oM6+5p?ZDVQ)-
zy|fz{L6}6dwSl~3Q=nKYRH^RFrn8Fy`uC5=LGXBEWcp3ue~CkzvAsB?8y<j*Pp}YW
zZKSLF<K9ebJb~?!sck_zL-LZ2LF+JEFQS4rUBH54lsG{gsfKn%cy?Q_-c#KGld~!-
z1AJPp1tZdSyx*~hjkpBz#G)u*p@sk%r|R^PSH(cqEnL2r0LrRpcNQXDNluM)Ws88{
z*7&)1NWuKm#;5pe-D_&ItFj0=8(?hm4?>wN?lgvlF^-TlInh`DK5~wFmF7Famc#&{
z*jE>)DL$4LJG=#~&71~xhI`vC1_yL-cL<7)ahQ5DJ|@QL5&0z>Nn9EX<d1rU8HCo0
zE&NQbjNfAvQ6Nyec<3EO%hQq?o!_EAMEqx@Pnlj<5<QaF=63WPE36G;r{!en^#tBS
z0{XXZP*nN`Gr-P}%g;xuWbbcD36C}9-_#m#)+NU8^pjFr=|jKg{VKki!v5<l3X#U>
zHkSq!6aSW3gl2%I*{ok(Fn*<FLHihT5*;>k&oyvOv0U5L#tC6JmhBt5yd%IMr7i3k
z?#(Fq3<isHcAyOk7v)=M6Mh3sk7OYY&<RXzwsrTyCY|}0YD7zuude2i?|t`k*RI|X
z(+dsD2`|Dp_zFYNRliYf*6&0+n}(bCcQVvRYlAGfeX{AlDcj$ZSkuw$Bq=jeW<^~4
zVX<rtdq$q~Zt-6UVpT$ejb0C~7TYL@(wvyLsY#5xbvmyMRBl_M+s1Fq#KLH#3ASW>
z#1&OJNODaR-_`&z;XC>Zn&2UbP!k(8P~vK|%SDl1yCj#>FX>#EQ3ex`-MhPXf2wg=
zhIJhjMOMwDNE^Pb$Il(v4&5-_wDFNi!dFRRR0Iar3h?fPdG$fIuwl~}`1M!}lf+rz
z&$_})c;6EHRYML1A9%y?V_ZTt8=}S~+RtF4{%5eOEm~IlV0gwO^!UNDOi0}x)`8N2
zqE{RlBTUQv%iAsqV3J`(ci{1$SnrtLE4$*f3rjW!19{SWVP)};!|9bU$Db{xhJwEL
z>~tL`P9VsI6d-baQz{)kO*TLzveqHvfMVagFJ~CE)Mc`5A7j|qX@3(q$=Rbc0*9Wq
z$7%Id`bp-96ej2!Q~dph`>9+OC*up%q_a^1kq;tXyjm^%DWh!j^wi%tV|IqF;g&p#
zn<U!m`^}HK$rrCZ;diyJDUVa%=fVq+*rUZkCzGu`bBltOwydfg*N$4-o?LOD4?M}l
zxh-g}m)-CelFaB3P;!HRw(lQiSNG&Sudkjp;GSkRQqKedJOJV`FIw3S_zEH_B;X;`
zzJ6Jg{c?tqNqp>FX83fe>m;G#Ew|%A#TTql946AGir#v<R9B0*!Bqy~2A_`-|9N!T
z=@QW^Q^*kPh8C^?da5$hk~NMemf6_*Jl!+)!3VAEnd(|U_g0-3X;iP$m7+#raZlbd
zPMn}+h~^aU4lPqkb%+Stak^(PQh)!1>p{2ZY|#d(Q$)!G-4%vO&{q)nic^aC&;Q!S
z;AmA*^pDLC8|Z2L6+SR(Jv%VeQ2#_dp{_>@A})zg*(6J_0Dyt-1OCRh*OpkD)@Xbl
zdvj2ZlTN;xOZ@#LMmt`{zWVvaggK~PXqr-BziufAmv9Y0soFV>hU_fDAM+&*j%!#K
zYsB55K%qmKEHzx0WuOe82Q+U9wuFufw|owI?Gb6#Sw;^1`>9}O>J9o_vQogztPa__
zoUWN^lzo@hd5Ys%CpO!IiZc-Zyx66CjS(S!kmDeQ>-G<h+f}hy`97*pM$0!BFXWR|
z1VR@B>l<#RxPWOr(qJq>*h&s<P_2JS!PTcddwfvn$Pk~r^UuBxeFPVaXs!KPlyqSU
z&hVC2oN#R9EkY{E!6%T5TF!hOZ_^iY$n7zU4hXsS-@F$f2C@)UG>CaihOJu|$aq9M
z$#JrRuvmV^Z;!t!rXYEUvY*S85Loxgo}tfl48n%j#yBUu=6>osArQB2NSGVNShN8A
zMrH*N74qY_UzfYZ9gGY+`FFNx_-sX4>Qa1WNUIrr@^OYtq5%0kdf(JbsuzD+M}sy{
zl(lBS3hmw#;m<?=NlN~sHbI<Uqhpx~-KzghWfrxjLC(1eqwb_qzz}{F8aB3RVcD_+
z(UGEJj)v4UL80Ud97#+fw>~A0KGkqJJ9N+?;WSuIodBrpYWKRkm`sbylqRI;C9|Gr
z*@x)BMQO8pdq<I9P@E!qfy(FQ;gd`@3AoJ^202bm9jyK^Gk;mVRMxKwZqaXkD~^?K
zBawhor=eR{yJpxchRL!Xt{Lk_x|$mqr*kvNU!EU^1(OJg;4CmmsoIVdTP;WAP_M*4
zyVw)GkX1a?fObAaDpBB>c2zkKpxc}9n33*qDGy=qzs|-Qmz_3|{IZw6-5=TnhaoG}
z^fAS6#|xIazBLXoWk<^)=pKtR{0?h>2vxYxy=b$X8j;+c58;Uzv4(-f{utD#w+}=b
ze!guH`QptnO2bc{$gx4jR$q8ogOKrJm{158t{DZ8y=b!!RI@nvQCDgQ`FENFo&%E0
zq63y+HS#S5n!vLj&^0!)J0N-7hyIYfr(T5$3MG{HSyy9eO_;8%JhS$Yxv9{tozp&h
zfx<I_Y~rDd6`Ce>4MR1Euxbd~EVv#bL&h@u2J(Yd!npE4t1#osa2#0_C4dR~L%U>Z
z3`3EpA0dB}B>mk{1w)zT8~_zTz3T92URw5{H~!iiv3lGUr}<JXe~HR{#f4owc&@eG
z3GsIb*q+JeTBi^xKtgBHPKv>p9T;9!G2f2c<H;{u2HdbYUXJ~5P31rxER}&Xvs&ox
zXV`cP8o~Xn0OJHVG#j5MwOB~s=p$_6Jy&wVxm$8;Xh|L>lS3Yr0T;TooRRD$cp@(2
zj(7(fh1L4pfiSC=;Os(AuUc7(`=t^lwP(JdQ8MEB{hl@Q=N4}kt@vMkFy1AJ88bRP
z7wF+xTR2rh0faJ4Qfqw$))DV4E}uot*SgK4I53h2S}unl_}@dw*AhgXS&xJ|h5kx0
zC_2pZ;C<`=(%gcub}65Ws^VYzS82MIv7jD>=`?per|*!^DDtsa8K3#&{DM8@)-FDe
zK(L|uY!?51AKG)Hhy{<Mb%qb|8Jk?Bn<EBWS0GoEszr;b#Q)|DE5LH#1I`OV^zklB
z&{w?`^D{tE8CS?6%SMwzr&TO7h#k*bP=vi*?6RrJAiLWWm+0>@VRN%Nw(_}pvW4lt
z=aDTd*5r6cvWvL?xvaf?9IzrGrv_|5p2ZlhmNVXj<h~j6x!PE76d$yK&hXh|<&mS;
zxq&I|qvmT?pdvOrzG})8h3SlSm=-4AGoMEixtEk+LpABny@U@y%UsaAxUfhnKut6b
zqShUjRz{Yg^!-@=;?7Qq#Qje`?)tUZu2sAzsdh3XZpqt`yLDSD$d?>DKdz3d0*9B#
z?3hOR9*I!}-;N4f>?laB()^!TWf!EjbP0SK@*Ou@T)NQA7?8i3Y4x06wiCqy?Q`ai
z4=k4IXnLDU*lc~yjH}4fk#-1C=1Ib*s5<HW*jpFpYMjs~#>TR1QTst$w)oLqAq3MO
zIYU%N!jeaK-^zHjY|E4;3>_r^S&^cr-KlgdD`0uD^=*Z)hK%>3?bY|#YjY4tnh5k1
z<bjgA5dNy()M{#>X_?_$K9ZQ(mB|F&{ZJGjF}=P5*lM*Btt`Q1gRg^a4z6w7IcETA
z_TUT%x6Oj{U!Ku7r03a(6W)LqnJZ1m459{{WTp!hv7@6O*%dE+a`lI9{p37MgZ1VE
z?|Gx}3piGGdCXB1`9$ou7m5|Xz0khjg(KgUf!dD_?zo1mJ~1^>(n!po7fmZ3fVE+T
z&nNpLc7v>tH|n?$_kCEug#Vy_uOk3vWwIJ;#C0c3wnI<?$`GXCG|v5vS@RdomP)A)
zRlnl?)=$dUq&hb8G^|JmFDMCL?8E_oT4UeFMQighWd?KRD%V82@*1Ug)CoU1t{^ym
zN!|y0Dc>uYKe0fY1F<(5f5Gn*Ag%d0iV$T|0X`ob{=JwK>Z5a{YYX?<66>L7MP!9`
zr-a61yDTsUs0C~;tAI8R#p5;<-dmdDYCO#x3+Sus3sVE1Ko8-~(jYr-G*b<(2^^1}
z8xQQA0sEY*LxV4LI!PpVE&?n-?yZm_ZS*a$=^fxTeLe{Cg+x`RuX1KjeEw>(kmT4W
zfJBEkU*Q1kooq<lbEl#*+_hF`R*s<~M@uLG@+KPA+4c#^@2<Xq@Jt@+!v?_6OdiJk
zeO>WS74HZC%ht&)IDAnF$-D0?g>7al=TQ5L?ZybGD^9nGhK!99Mi}Nmu@}T)7+slJ
ztW&~vaCqaBZGlL6JLn~_7|Hn4r?*&xT5zb?2RTL`O|q@C;x*~Jv|8ApV*<D}g~z!8
z$9&tu5R?aTi)G3y!)La>j1sqysmndUK-yYqZcQ;z6n`x*H(eUk#UvLB`XRU1=xT9O
zZ^Upiv1J$yL}7`7h6g?3?#U9_#I~m+_;l=j;0cg-8#&mu4u?<v$d*EEg~_$qIK?is
zPkjAqA|{)aR9DW_=5#gbagse<jy1l<azXTUqk1ocl8-sGcnNSojf@o5ofXq!HGyg7
zm!gY29}YF0=ns7bNiV^bFmWS4v?TJ(Q--g%!AHSEw~8|w{9y?JN9qH|!C0-Dk|-}0
z8hdqoc|Qo|eP@gT9>@_*XlP2UE@DbS35tnOMkkkaFSv`Rs|qB_%L}SzqjV-CLHahP
zyd=wR&z3>m=vW_vTQXDq3smGQ>f36d1fnkrNg-?R3O`Ki9sype7|*J%bW<6}f)tCg
z7|aEF{vHuv#ZL9s%e|O;HiP~Lbz#h)VB+)Dh6<-BciQgs&xa~>5FD#R-DbR^&swq+
z)K~_5$shK*^Pw*p_I~F^nFp+9NqR}_Hs8AZl#3_>Xrm_wtEGFrG3LszmpD=DbG)xr
zWR(cA=}~!WB1F^zJj;`w^VFNLmS6K@tT+xduOTjV5`6=YxU3BBIEu=mSztDJdYlGr
zN2Ta9<cor4l@v;dvZL<BsXyzFBx7WL6MdLIO_qOoQknbdZCgjjXsM+D@SgI_%!!Bw
SUWH*W&J1hUA1su~8PT|-)}S8%

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v b/FPGA_firmware/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v
new file mode 100644
index 0000000000000000000000000000000000000000..06103098eb697feac392d18c44c79dd583d72ce7
GIT binary patch
literal 4888
zcmV+z6X)!U6Pzyw00aPbk7N-a4?R50059g_|MSsZr#!Ei1CBXw?u<znu&sk(z61(D
zz1gq6@<pEg=xY5Ds=Nd|6s|)~`tJ-#aw_(rHwZuCCBM2!ns)4A(4Eq&a@FKOsNrvA
z!WK0>TO-ER<C%h_{bR_$?9rJ4L3Bgm0e<j22;023^BMD1o+6S&(I4X|TY3``KAxs1
z8D~<EBfb@Z_F87dO28ajgr<Z~97Pp{SiB>?p76(dsx$As<N-vV;+pY!MSwIiY5Fh#
zHLLt=;Hn!^n}eO8>ZrLq+MAYK0JJLIO#9^4RK^>Xu0$9IOr^gwQzqSHLjrrJj3mfp
z7r^z>R4phto5GuJw=$Q>$IMLoDv^*e=QyHJN+wV`L^@;Urwg#pDk!0M#9jTz<cu_*
zc)ttX{z@&gXqeK0@D*U((TRGcAjOH|=D)+0IBq<}F#;sjub;J)*1_qpvEa1;Gg=2d
z$Yt#}`vzl6jn+%T%0~J`MSI@@1R>ORkU9hx)(av!Z1x=PI`m>YKPBr0eYrKO+|_XD
z_z-zWyezq_Dv@YB_yOl|{wYxr#6$PsKF;B~6g|5?lKZX2eH|ciq=CE{RF+XaQ8He<
z(J)c0{7?ek#3$|Zbd*v&vuhg+8#m;vHjkf1!m)hgN@6V!YQ3Syy4#G}z;gAH(tV8r
z3*ic+DF^`_iWk)ES^r>P5avO`Ygy=fyv9B+SvG_Uh@W-oG(nJR+xXkWvQB^W-k58e
zRtZ<N(A4=2-K&b&TUWE(3L!Ao8@ss|VyGMWa4lHn>K?GQVMZ%NOpL-S)xuKaohTzZ
z6xxfWn$QpM!CL;M3;_g#b|T?9kJiuE`mvcpOP^-7Wa(_EGC|IT(|VQE1uf=~zW2-&
zES{xLl-2l7aZ4jBYL-_dJ#x27f!&Uv;gBC=oVvp@HE}5LOl0>Y5MIGXHO5ahU2bEW
z;_YQNb)C=+>o(P^-HED~AIqEO8QS!@(I+pE&BuA0vti(FLWUFi30hydqjX%e1z5}&
zqyRHkb&*HqbFVjd3<RKi4lnL0@*<e*_XAxO!91bU46msuTMi?rco)$WFa51P!X<Wc
zEl?F0U7C|{D)Y9zHUKU<C&`uFM6z!l%UbZ<9;f*x%}~f<=`4P`5O(O<W_?e^sWJZD
zRQNJ@+%){aI<1hebX%+ETUAiE*oo)e!xe?flXLb>q#aX*ODmIFHK&7M{VV=WZ5;Ey
zNr~#+-$dL;sf<H=FUf#tdrwya-<)`}kXGk*B-}?%%FvGq@VQl-b|RQHl)vR3a!gWH
zfgkkaACG(I!3gm<Eb;_rq%kV6%_+9x_`1thX!kV9@dFgZTOTSU*>)er&0k1vH>lto
zLO7dk8J85N<>7aKa&cha&dn)xT)i8Aq%aPGzfukR7bP%P&HTFyB#r1=H%~Kzb$h--
z6}=i|-Lj(HPP;1Tli5A#1S}}N!yzCF9H+{fd9lfk-Clh|;pd&&h4wFUR7|X+@{|sT
zchfo!285Xm^m@D2L1-DLNrFDpIYPR_3;@8b0YM)spNC3X)jssN#nad6!0ax7h@X)4
zCbvW|DQgr8tI4{~)i)ji1s5O|qEW~c{h$cktv#w)dHn(a@}V@^D;dF<jO8uL9>G=;
zmb7<F2@;q-0y!taUnjb%Wxd@^FIC&GoejU-_!zr9u&*A@(9(pqiJXyPs?6T6w{xT|
zt4BHQ*RI1~&Hbb?PYP(7*5~BEbE)t8qCdj<I#nWh-+`Y#h}*OdX^*M-_u<Ddh1@mM
zL1gt%q%me+hm4czVKNI9;;2^p<*rdEMUxMTD)La)u1zsJ8AGPfU;^n}i!`-I1h2Rv
zVWM<(aHpj|4Yh?)$QY2jCd@GtlfhojByDCFCMxE1QnD92Xz!<o-U8>&fHOQRL~)=A
z;MM~tTWk`M@_szxcB<+m^){p=rl)EObXPQTkmk>Lsc?BR0bwqnOe)sR_`SaG%5maY
zE8mtaBW&hSVnT$Z2D-)~)worc_I&R?lg(l(nOdpDPocR9Ex(-1wq)KYW=x)vQ6`1s
zj^~23H*vaS7eREswRTDBn7Yhd@59X-C6Nl2S(3-DpmE4Sri7c*Q|{*B`=2-)m4Sc%
zV)5=pbT2v@sp^yJR%qiK4;!~P?5S6BXZ_tmD4W6w4A40*Wuo_Hl@t~5e<?ocM(`~6
zG|gx95T5I#ZdPj;D6P1^8C2Hg(EcHjeYwR8N)jToVWbV{85xqf3?;HB__uXYkmRz-
z^TymsSo)qCu6Q}QTibZL^zm-&^881N$vID6E#8^eN}Rs%iUNo%a!%XS;x<cKVj-L<
z!mh6b6;av2NyxqBs)6$`DloHc&$hmVCDsyd^oqfg39#M2#m^8_^ty8%Wmq41**d1<
z28$~R`Xa40USfSejVw_w%I^DF*5X~wrKPd=q@5hA+s8o3WRsGS(4oKdS<Uub>5!y`
z_6DJTOeDB)^N(RFc_YTOYDoUxr1EjPJQDQN0y}n8QcJ^GJI(qH>YE3&LlwGhM^71g
ztaF7l{6*q{(_KP~!-jyPlE-wDE@+HOIb#6fRBP>Fe7FwKEBA!0z@$CMQ6x(zL*9B(
z_$7yM-8jAJ*~yX2NU#JlGSS9`*$ix@$Y2>Q0TS?nWeX|t-j}DUIoAm;`Q44Ch*{$}
zs~O=>kwGeT?T*NOcCepe2F-KX1JPIZX?thZKQTZC(G}UPCzAp#zz%|C^c~)B!4wdW
z{btj3vYXXu?nr1T83?-mWbv+R>Wj!yDL77uc}Hv!P8p1L$Pk%-5nOme@VRVaIeme*
zV2IwFbCJC5J<KsQ!1x%kWJX!lSFcY6Mq6)BHFXur&Ttxz{iT+$a<QQ(Sf8~gRVKe2
z$33Eeczy5TE7e-N`hO7hQj8+8d>>lKl;)_{KyBA>`LhxBgm`N8lw1F)8jxov()0Ks
z^k*qh`o*kfQ*82x@ajsrKUuq>Ub|F<YZLtX?u0#+B#CYl=zCa*__T2<Mx3=X(Yyda
zdnZzJ5>Fs=6@awm$LTi_puW`k@Fo%G_v@x)B`(exsT_KQZ3^2K@_8?3It&3$5MR9F
z2)?T*ft-u#AAPGA?`=yPjvoc6y#8j@FS{gZ!iHb_I#8qBgjb^IA~z{OX-yv><%i}C
zOT-jU6TIU<x$28MRalEa1+7;rC&I`QbU`QgHfCo<!OxsP?y-nnc>mB*w4q5{lP*T=
z5bE0`Dj%ZB$+|QE%>u01xsb7i*{sC=d<wYD@-scNmWk1?wim((4xZ55mwM?abn~V+
za|AU)+pLmuf1O%d4RsH8AFajxH<u(ydzKz#bhTfXXOWJ+8UvJX41l<_Pvr@vt=vvB
zYy!m&RF<)Fu!nl{`GsROy9%;4f<MyyU1&G`6b>l#;h3eGAOHu-00%I5kAV(8_p!!_
z!p|mY-1D5gHx~sOqwOo%`}G(JA24G(N#-Usq!S}3fiCpOhxWLzuY&uJiFVYX%zQCn
zW?DC#cMH&@p9xixgEr7#k5RZ)FlYf_I>b1^F)?NWW4GtM{xt$6<d#Ue4)iD_kt{g<
zCn}(!y+X2mdZ|V2fZB`TpYB}b3)VPL++7s>u$K>ms5O#L15gSbg$|APq9xCLhaqya
zWlQ;Y5T7iJz}IDSX5B_;222_t4ZDrIEsOp5=IYre^7F7$>9<7$0E8!5_Bhf^O8zS2
zGi$9=R6{h~NHw9=6=Q{;-6y<?_^ml#GitI&0o>s~#vy$!M~eg_KeLMdKlH5&4L_!;
zsjP(MW+c<mJQNYDe^^NBN?7Z0o9D<OR#T9V?V|jB0+n0rrz~k*1b>*b<DX_kTmT`x
zN)SyY@Jn^D@ks5*pKz-WKjaxrH~k8Z=~y?{K%k=1SYPs~QZxT$=s-0Vt-Ka90!?Z2
zb$<A#zb1+rbG7AZ&zJEQEtj|4?~aFJ!@nnmWuUJu!lTxwH-#lMRNODG^K6Bw9}D##
znw`Y<m*(qn{S9BshuL1|8ek2hl^%^3ShsEdydaGzR;Q-dEtMZOW0*ok!lG`N9!;+^
zJ_a<n!vtvAOf;Zp?qYDp5~~X}m6r~b$dHj{MON}!;y+ev>l!6}E9tvxJVkLDuvf1j
zR&>`0bLYi+DNa5NIazXvY1$)_doPH$VZ=kE?<Mbi9s1;*XS&T|8%=%TE=Ce4*=kXq
zpw(^dpgtWXrpWjR!Cy<Z>sGXbUSqj+he=^UdCllZb=23x@w0u(D*I0WPJO|&Ks`<F
z2$QAF_{49z8&r8afSv!0rQGs<Btyw_730SA!M!~s=>E&l3sas)D^>;(CYZ9_bJ)$+
zbv2b6bAEQsj46hUkeF>^n99O`F0?}>h-e<qHWu$jgNCZw!_%yFs=RTSY;X`dBjOaF
z4Qpp(b&d6E{&1{0{bOupqdd(Rf#l55Pi}0Ax)PZHXScMEN6uyBQ`UD}cz)<1((&hN
zJE>u8w+>#YuyKUTC9a^$A1hJm%L^(K+6%ocMcX`K?+OF<iroG)LxPvUsl6SK@VVq0
z7zN8)DD<TFCr-?mi1Z+#Rl%+m4D1KQag4r|%g3iLwA{XIhqDZm)y465?2}}7e)Rs`
z!LKOYusOp<UxZC%Re#B4xIc`W<jMh5E4`PyLucXLflL)^>;SxTyoYmxbr>LU>rPl2
znNT91#cgjCwiEn{x>P-6Kqb=KfSn8;dBKS8_fi1Y`<IPUqX=ivR`hk`<HaHTCZ9MW
zOhW39&4dNOkZd7gwUC_=C@22KKH-)$YdaVjksP&LeGOFEvFXQtH&Lc}fk3%xbH{BB
zEwzpX^d}yjQwt~n`<U&+PutRb2B3JWzjVg_P|lJP%Hlc0R*D_FutQjrAiipu)6k$*
zb3hzeZ-?w0;dj2D;85TRQL{;Y(RUpO_m!E%*4Ab_kY$iO@g89`i8&pNG(#H($M4kZ
zabF@OabHBd#lR=2vQrmCL3ro2uLz?P0plmlBjT=vDP{BlajiwwmVy~IsuuJ89%Vd=
zcA?Pn8(fo!I4kyz6&Z+skK%;uc_dSaCTiu49i<VrouIJTE}4Cf*gc)U694PxQ<Q#`
zQmp}_hn0wB5RD?pH;$12_srEzozr+;wst>a6clf~GKvhg64S>ByWFfjc}eA0=H)#A
zpbDX{G0JRcDd`@d=nWUCe(>n6pkcdS_hdi|+-hc-!lyR8ac>6?kQOnI9{8zOy7?US
zO=K4Vp<HJ>-1N+bf*k=nxhSNS8#4!#gV2p+4}TuN^M{gXJ#NW*dzqX^63d#<53m>G
z1brzJ7A;qyv799kC;7As$AFi0%r9d7T`COeK+<%5t{3;_BtsVNr=X6l+O9lH;)w<Z
z>Wa!}(OqVPQ_B?9nRSWAZ(aubL*$1V0Q6=K?Hk?xpU@S>UW`9lRne@j!by+U>du~G
zBUT7FxyjpB)~i8)SHYuRd2y~LPAK*s5ElZfN{ghPn$EvR5j!oPB<w`}vewb-5n`re
zfRgaZm5^v`(Opzo0KgjTLhUt|clYr8r}~Bb%)Ivvm<4fu64yQL=yZYM8-9}MQ6L3>
z*;j}l=>t71`X7aGNAT$BA4*!S*jk4e@iaHA@f?GoX|<I>a0I}(E8+E;;GV1xtSMIW
zNtg*zDXS~`xtDO`7+)xC!^|&HRQFigcXR<S*;FpRfU`IDF@KF7gDaJPLuTP%&ZjF@
z1iCWe^-B7)sWo+x62|H^h7mwY59s12!qNGAjz%28ojc8pJQZhlk^mD&C#yD>$DNR|
zm>tSXVRn3_`#gB7ekJjSgtRrFGX*xP?FOD|?b5Z47j>4!1_%zHfa6I7=}i9bKCFIa
zvA}b6G}-k%qxsFfJohE`5mWrh83<&i)^Ai-p*~U|aYO><;<x6ls>p=HllWRhinb&K
z3RFqCyx%VuvF{crG7cv<=3}%Tu23xyaiUFXX&L*^vkIHCupA8i=wDwam2mjf39_5@
z$ozSon7uz0<)&v~X@D=VxNRi&1&Vaoy*E9dhOO_CeexaYq2tPUd`>$gqMSgSLEj)&
zAbPLc^=p~U6=O#^H=MaAFM<OZSRB5yCMY+kiG-l@{B1JHG}KIUBvaKJPctv}(z5b%
zzaW}3**u?lih~ztgC$&KQA(Q~QF+;StvaCS$X*>u%@A|_q#<N4+g4{<Ofh17giYL)
z!FRBnmh5$OY2^W=MzOQ~#pl#GEOPou*9_1Je#9=n<26y)GwYZ+;#V~4w)rAKD!5-x
zBO&Krl80ina(-uVeDpLm4Q^1s{)<}vVYP?vbYhh<;c*`u(`-J2s7RaV|DPn$&}({Z
z$E>>f0k$!Z&1yrjF9923W7KXNJ<vmZinDctu0N(yfwM*(TNy0eVN&7C{3Cql^C*mr
z>f55gklv#U{*#_B*xh?mUR-IH&ss%Og^_+2!L<NTYF7|5{B6^V8X3Ktt>)ew0Jvup
KeaGq-IZo+~=YSpn

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v
new file mode 100644
index 0000000..aeef730
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ac_ROM_reg.v
@@ -0,0 +1,49 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_ac_ROM_reg(
+        rdaddress,
+        clock,
+        wraddress,
+        data,
+        wren,
+        q);
+
+parameter AC_ROM_DATA_WIDTH = "";
+parameter AC_ROM_ADDRESS_WIDTH = ""; 
+
+
+input   [(AC_ROM_ADDRESS_WIDTH-1):0]  rdaddress;
+input     clock;
+input [(AC_ROM_ADDRESS_WIDTH-1):0] wraddress;
+input [(AC_ROM_DATA_WIDTH-1):0] data;
+input wren;
+output reg [(AC_ROM_DATA_WIDTH-1):0]  q;
+
+reg [(AC_ROM_DATA_WIDTH-1):0] ac_mem[(2**AC_ROM_ADDRESS_WIDTH-1):0];
+
+always @(posedge clock)
+
+begin
+  if(wren)
+  ac_mem[wraddress] <= data;
+  q <= ac_mem[rdaddress];
+
+end
+
+
+
+endmodule
+ 
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_bitcheck.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_bitcheck.v
new file mode 100644
index 0000000..eb89b41
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_bitcheck.v
@@ -0,0 +1,96 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_bitcheck(
+	ck,
+	reset_n,
+	clear,
+	enable,
+	read_data,
+	reference_data,
+	mask,
+	error_word
+);
+
+	parameter DATA_WIDTH 		= "";
+	parameter AFI_RATIO		= "";
+
+	localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
+	localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
+
+	input ck;
+	input reset_n;
+	input clear;
+	input enable;
+	input [DATA_BUS_SIZE - 1 : 0] read_data;
+	input [DATA_BUS_SIZE - 1 : 0] reference_data;
+	input [NUMBER_OF_WORDS - 1 : 0] mask;
+	output [DATA_WIDTH - 1 : 0] error_word;
+
+	reg [DATA_BUS_SIZE - 1 : 0] read_data_r;
+	reg [DATA_WIDTH - 1 : 0] error_word;
+	reg enable_r;
+	wire [DATA_WIDTH - 1 : 0] error_compute;
+
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			error_word <= {DATA_WIDTH{1'b0}};
+			read_data_r <= {DATA_BUS_SIZE{1'b0}};
+			enable_r <= 1'b0;
+		end
+		else begin
+			if(clear) begin
+				error_word <= {DATA_WIDTH{1'b0}};
+			end
+			else if(enable_r) begin
+				error_word <= error_word | error_compute;
+			end
+			read_data_r <= read_data;
+			enable_r <= enable;
+		end
+	end
+
+	genvar b;
+	generate
+		for(b = 0; b < DATA_WIDTH; b = b + 1) 
+		begin : bit_loop
+			if (AFI_RATIO == 4) begin
+				assign error_compute[b] = 
+					((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
+					((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
+					((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2]) |
+					((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]) |
+					((read_data_r[b + 4 * DATA_WIDTH] ^ reference_data[b + 4 * DATA_WIDTH]) & ~mask[4]) |
+					((read_data_r[b + 5 * DATA_WIDTH] ^ reference_data[b + 5 * DATA_WIDTH]) & ~mask[5]) |
+					((read_data_r[b + 6 * DATA_WIDTH] ^ reference_data[b + 6 * DATA_WIDTH]) & ~mask[6]) |
+					((read_data_r[b + 7 * DATA_WIDTH] ^ reference_data[b + 7 * DATA_WIDTH]) & ~mask[7]);
+			end
+			else if (AFI_RATIO == 2) begin
+				assign error_compute[b] = 
+					((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
+					((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
+					((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH])  & ~mask[2])|
+					((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]);
+			end
+			else begin
+				assign error_compute[b] = 
+					((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
+					((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]);
+			end
+		end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_core.sv b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_core.sv
new file mode 100644
index 0000000..581e2ed
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_core.sv
@@ -0,0 +1,668 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+(* altera_attribute = "-name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 270" *)
+module rw_manager_core (
+	avl_clk,
+	avl_reset_n,
+	avl_address,
+	avl_readdata,
+	avl_writedata,
+ 
+	afi_clk,
+	afi_reset_n,
+	
+	afi_wdata,
+	afi_dm,
+	afi_rdata,
+	afi_rdata_valid,
+	afi_rrank,
+	afi_wrank,
+
+	afi_odt,
+
+	ac_masked_bus,
+	ac_bus,
+	
+	cmd_read,
+	cmd_write,
+	cmd_done,
+	csr_clk,
+	csr_ena,
+	csr_dout_phy,
+	csr_dout,
+
+
+	cs_mask_export,
+	jump_ptr_0_export, 	
+	jump_ptr_1_export, 
+	jump_cntr_0_export, 	
+	jump_cntr_1_export
+);
+
+	parameter AVL_DATA_WIDTH			= "";
+	parameter AVL_ADDRESS_WIDTH			= "";
+
+	parameter MEM_DQ_WIDTH				= "";
+	parameter MEM_DM_WIDTH				= "";
+	parameter MEM_ODT_WIDTH 			= "";
+	parameter MEM_NUMBER_OF_RANKS		= "";
+	
+	parameter AC_ODT_BIT				= "";
+	parameter AC_BUS_WIDTH				= "";
+	parameter AC_MASKED_BUS_WIDTH			= "";
+	parameter MASK_WIDTH				= "";
+	parameter AFI_RATIO				= "";
+
+	parameter MEM_READ_DQS_WIDTH 			= "";
+	parameter MEM_WRITE_DQS_WIDTH			= "";
+
+	parameter DEBUG_READ_DI_WIDTH			= "";
+	parameter DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT	= "";
+	parameter DEBUG_WRITE_TO_READ_RATIO	= "";
+	parameter MAX_DI_BUFFER_WORDS_LOG_2 = "";
+
+	parameter RATE = "";
+	parameter HCX_COMPAT_MODE = 0;
+	parameter DEVICE_FAMILY = "";
+
+	parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
+	parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
+	
+	parameter USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE = 0;
+
+	parameter AP_MODE_EN = 2'b00;
+
+	localparam AC_ROM_DATA_WIDTH = AC_BUS_WIDTH + ((RATE == "Quarter") ? 2 : AFI_RATIO);
+	localparam AC_ROM_FIXED_DATA_WIDTH = 32;
+	
+	localparam AC_ROM_ADDRESS_WIDTH = 6;
+	localparam INST_ROM_DATA_WIDTH = 20;
+	
+        localparam INST_ROM_ADDRESS_WIDTH = 7;
+	localparam JUMP_COUNTER_WIDTH = 8;
+
+	localparam GROUP_COUNTER_WIDTH = 8;
+	localparam NUMBER_OF_READ_DQ_PER_DQS = MEM_DQ_WIDTH / MEM_READ_DQS_WIDTH;
+	localparam NUMBER_OF_WRITE_DQ_PER_DQS = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
+
+	localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
+	localparam GROUP_BUS_SIZE = NUMBER_OF_READ_DQ_PER_DQS * NUMBER_OF_WORDS;
+
+	localparam CS_MASK_WIDTH = 8;
+	
+	localparam MAX_DI_BUFFER_WORDS = 2**MAX_DI_BUFFER_WORDS_LOG_2;
+	localparam DI_ADDR_WIDTH = MAX_DI_BUFFER_WORDS_LOG_2;
+	
+
+	input avl_clk;
+	input avl_reset_n;
+	input [AVL_DATA_WIDTH - 1:0] avl_writedata;
+	output [AVL_DATA_WIDTH - 1:0] avl_readdata;
+
+	// AFI interface portion
+
+	input afi_clk;
+	input afi_reset_n;
+	
+	output [AC_BUS_WIDTH - 1:0] ac_bus;
+	output [AC_MASKED_BUS_WIDTH - 1:0] ac_masked_bus;
+
+	output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
+	output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
+	output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
+	output [MEM_WRITE_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO - 1:0] afi_wrank;
+	output [MEM_READ_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO - 1:0] afi_rrank;
+	input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
+	input afi_rdata_valid;
+
+	input cmd_read;
+	input cmd_write;
+	output cmd_done;
+	input [AVL_ADDRESS_WIDTH - 1:0] avl_address;
+
+        input                         csr_clk;       
+        input                         csr_ena;       
+        input                         csr_dout_phy;      
+        output  csr_dout;
+
+	output	[7:0] jump_ptr_0_export; 	
+	output  [7:0] jump_ptr_1_export; 
+	output  [7:0] jump_cntr_0_export; 	
+	output  [7:0] jump_cntr_1_export;
+	output  [CS_MASK_WIDTH - 1:0] cs_mask_export;
+
+	reg [AVL_DATA_WIDTH - 1:0] avl_readdata;
+
+	reg di_buffer_clear;
+
+	wire [AC_ROM_FIXED_DATA_WIDTH - 1:0] ac_bus_from_rom;
+	wire [AC_ROM_DATA_WIDTH - 1:0] ac_bus_internal;
+	wire [GROUP_BUS_SIZE - 1 : 0] DI_mux;
+	wire [INST_ROM_DATA_WIDTH - 1:0] opcode;
+	wire [INST_ROM_ADDRESS_WIDTH - 1:0] next_PC;
+	reg [DI_ADDR_WIDTH-1:0] di_buffer_write_address;
+	wire [DEBUG_READ_DI_WIDTH - 1:0] di_buffer_read_data;
+	reg [INST_ROM_ADDRESS_WIDTH - 1:0] PC;
+	wire [GROUP_COUNTER_WIDTH - 1:0] group_select /* synthesis keep = 1 */;
+	wire [JUMP_COUNTER_WIDTH - 1:0] jump_group_counter_ext;
+	wire [GROUP_COUNTER_WIDTH - 1:0] jump_group_counter;
+	wire [GROUP_BUS_SIZE - 1 : 0] read_datapath_input;
+	wire read_datapath_valid;
+	reg r_wn_r;
+	reg group_mode;
+	reg loopback_mode;
+
+	wire [2 * NUMBER_OF_WRITE_DQ_PER_DQS * AFI_RATIO - 1 : 0] do_data;
+	wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
+
+	reg [2 * NUMBER_OF_WRITE_DQ_PER_DQS * AFI_RATIO - 1 : 0] do_data_r;
+	reg [NUMBER_OF_WORDS - 1 : 0] dm_data_r;
+
+	wire return_code = opcode[19];
+	wire r_wn = opcode[18];
+	wire DO_lfsr = opcode[17];
+	wire DM_lfsr = opcode[16];
+	wire jump = opcode[15];
+	wire [1:0] jump_reg = opcode[14:13];
+	wire [AC_ROM_ADDRESS_WIDTH - 1:0] ac_address = opcode[12:7];
+	wire [3:0] do_address = opcode[6:3];
+	wire [2:0] dm_address = opcode[2:0];
+	wire jump_taken;
+	wire [INST_ROM_ADDRESS_WIDTH - 1:0] jump_address;
+	wire [7:0] jump_address_jumplogic;
+	wire write_DO_lfsr_step = DO_lfsr && !r_wn;
+	wire write_DM_lfsr_step = DM_lfsr && !r_wn;
+	reg cmd_read_afi;
+	reg cmd_write_afi;
+
+	wire [NUMBER_OF_READ_DQ_PER_DQS - 1:0] error_word;
+
+	wire [(INST_ROM_DATA_WIDTH-1):0] inst_ROM_wrdata;
+	wire [(INST_ROM_ADDRESS_WIDTH-1):0] inst_ROM_wraddress;
+	wire [AC_ROM_FIXED_DATA_WIDTH-1:0] ac_ROM_wrdata_to_rom;
+	wire [(AC_ROM_DATA_WIDTH-1):0] ac_ROM_wrdata;
+	wire [(AC_ROM_ADDRESS_WIDTH-1):0] ac_ROM_wraddress;
+
+	reg [31:0] di_status_word;
+
+	wire csr_dout = 1'b0;
+
+
+	reg [AVL_DATA_WIDTH - 1:0] avl_writedata_afi;
+	reg [AVL_ADDRESS_WIDTH - 1:0] avl_address_afi;
+
+	always @(posedge afi_clk or negedge afi_reset_n)
+	begin
+		if (~afi_reset_n)
+		begin
+		    avl_writedata_afi    <= {AVL_DATA_WIDTH{1'b0}};
+		    avl_address_afi      <= {AVL_ADDRESS_WIDTH{1'b0}};
+		    cmd_read_afi	 <= 1'b0;
+		    cmd_write_afi	 <= 1'b0;
+		    r_wn_r               <= 1'b0;
+			do_data_r            <= 0;
+			dm_data_r            <= 0;
+		end
+		else begin
+		    avl_writedata_afi    <= avl_writedata;
+		    avl_address_afi      <= avl_address;
+		    cmd_read_afi	 <= cmd_read;
+		    cmd_write_afi	 <= cmd_write;
+		    r_wn_r               <= r_wn;
+			do_data_r            <= do_data;
+			dm_data_r            <= dm_data;
+		end
+	end
+
+	
+	assign inst_ROM_wrdata = avl_writedata_afi [(INST_ROM_DATA_WIDTH-1):0];
+
+	assign inst_ROM_wraddress = avl_address_afi[(INST_ROM_ADDRESS_WIDTH-1):0];
+
+	assign ac_ROM_wrdata = avl_writedata_afi[(AC_ROM_DATA_WIDTH-1):0];
+
+	assign ac_ROM_wraddress = avl_address_afi[(AC_ROM_ADDRESS_WIDTH-1):0];
+
+	reg [GROUP_BUS_SIZE - 1 : 0] DI_mux_r;
+	reg afi_rdata_valid_r;
+
+	always @(posedge afi_clk or negedge afi_reset_n)
+	begin
+		if (~afi_reset_n)
+		begin
+			DI_mux_r			<= {GROUP_BUS_SIZE{1'b0}};
+			afi_rdata_valid_r	<= 1'b0;
+		end
+		else begin
+			DI_mux_r			<= DI_mux;
+			afi_rdata_valid_r	<= afi_rdata_valid;
+		end
+	end
+
+	assign read_datapath_input = (loopback_mode) ? do_data: DI_mux_r;
+	assign read_datapath_valid = (loopback_mode) ? r_wn_r : afi_rdata_valid_r;
+	
+	assign ac_bus = ac_bus_internal[AC_BUS_WIDTH - 1:0];
+
+
+	wire [NUMBER_OF_READ_DQ_PER_DQS - 1:0] processed_error_word;
+	
+	genvar rank;
+	generate
+		for(rank = 0; rank < NUMBER_OF_READ_DQ_PER_DQS; rank = rank + 1)
+		begin: error_word_gen
+			assign processed_error_word[rank] = (error_word[rank] !== 1'b0);
+		end
+	endgenerate
+
+	always @ (*)
+	begin
+		di_status_word <= 0;
+		if (di_buffer_write_address[DI_ADDR_WIDTH-1:0] > MAX_DI_BUFFER_WORDS)
+			di_status_word[15:0] <= MAX_DI_BUFFER_WORDS[15:0];
+		else
+			di_status_word[DI_ADDR_WIDTH-1:0] <= di_buffer_write_address[DI_ADDR_WIDTH-1:0];
+		di_status_word[23:16] <= DEBUG_WRITE_TO_READ_RATIO[7:0];
+		di_status_word[31:24] <= DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT[7:0];
+	end
+	
+	always @ (*)
+	begin
+		if (avl_address_afi == 0)
+			avl_readdata <=  {{{32 - NUMBER_OF_READ_DQ_PER_DQS}{1'b0}}, processed_error_word};
+		else if (avl_address_afi == 1)
+			avl_readdata <= {{{32 - INST_ROM_ADDRESS_WIDTH}{1'b0}}, PC};
+		else if (avl_address_afi == 2)
+			avl_readdata <= di_status_word;
+		else if (avl_address_afi == 3)
+			avl_readdata <= di_status_word;
+		else
+			avl_readdata <= di_buffer_read_data;
+	end
+
+	typedef enum int unsigned {
+		RW_MGR_STATE_IDLE,
+		RW_MGR_STATE_RUNNING,
+		RW_MGR_STATE_READING,
+		RW_MGR_STATE_DONE
+	} RW_MGR_STATE_T;
+
+	RW_MGR_STATE_T state;
+
+	assign cmd_done = (state == RW_MGR_STATE_DONE);
+
+	reg [MEM_NUMBER_OF_RANKS - 1:0] active_rank;
+	reg [CS_MASK_WIDTH - 1:0] cs_mask;
+	reg [CS_MASK_WIDTH - 1:0] odt_0_mask;
+	reg [CS_MASK_WIDTH - 1:0] odt_1_mask;
+	reg cmd_reset_r;
+
+
+	assign cs_mask_export = cs_mask;
+
+	wire [3:0] cmd_opcode = avl_address_afi[11:8];
+	wire cmd_run_single_group = (cmd_opcode == 4'b0000) & cmd_write_afi; 
+	wire cmd_run_all_groups = (cmd_opcode == 4'b0001) & cmd_write_afi; 
+
+	wire cmd_load_cntr = (cmd_opcode == 4'b0010) & cmd_write_afi; 
+	wire cmd_load_jump_address = (cmd_opcode == 4'b0011) & cmd_write_afi; 
+	wire cmd_clear_read_datapath = (cmd_opcode == 4'b0100) & cmd_write_afi; 
+	wire cmd_set_cs_mask = (cmd_opcode == 4'b0101) & cmd_write_afi; 
+	wire inst_ROM_wren = (cmd_opcode == 4'b0110) & cmd_write_afi; 
+	wire ac_ROM_wren = (cmd_opcode == 4'b0111) & cmd_write_afi; 
+	wire cmd_reset = (cmd_opcode == 4'b1000) & cmd_write_afi; 
+	wire cmd_set_active_rank = (cmd_opcode == 4'b1001) & cmd_write_afi; 
+	wire cmd_load = (cmd_opcode != 4'b0000 && cmd_opcode != 4'b0001) & cmd_write_afi;
+	wire rw_soft_reset_n = afi_reset_n & ~cmd_reset_r /* synthesis keep = 1 */;
+
+	wire [GROUP_COUNTER_WIDTH - 1:0] cmd_run_group = avl_address_afi[GROUP_COUNTER_WIDTH - 1:0];
+	wire [INST_ROM_ADDRESS_WIDTH - 1:0] cmd_run_address = avl_writedata_afi[INST_ROM_ADDRESS_WIDTH - 1:0];
+	wire [1:0] cmd_reg_select = avl_address_afi[1:0];
+	wire cmd_run = cmd_run_single_group | cmd_run_all_groups;
+	wire [7:0] cs_mask_setting = avl_writedata_afi[7:0];
+	wire [MEM_NUMBER_OF_RANKS-1:0] active_rank_setting = avl_writedata_afi[MEM_NUMBER_OF_RANKS-1:0];
+	wire [7:0] odt_0_mask_setting = avl_writedata_afi[15:8];
+	wire [7:0] odt_1_mask_setting = avl_writedata_afi[23:16];
+
+	wire option_loopback_mode = avl_address_afi[7];
+	wire odt_select = ac_bus_internal[AC_ODT_BIT];
+	assign afi_odt = odt_select ?
+		{AFI_RATIO{odt_1_mask[MEM_ODT_WIDTH - 1:0]}} : 
+		{AFI_RATIO{odt_0_mask[MEM_ODT_WIDTH - 1:0]}};
+		
+	assign afi_wrank = {AFI_RATIO{ {MEM_WRITE_DQS_WIDTH{active_rank}} }};
+	assign afi_rrank = {AFI_RATIO{ {MEM_READ_DQS_WIDTH{active_rank}} }};
+
+	genvar rank2, rate;
+	generate
+		for(rate = 0; rate < AFI_RATIO; rate = rate + 1)
+		begin : rate_counter
+			for(rank2 = 0; rank2 < MASK_WIDTH; rank2 = rank2 + 1)
+			begin : rank_counter
+				if (RATE == "Quarter") begin
+					if (USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE == 0) begin
+						if (rate % 2 == 0)
+							assign ac_masked_bus[rate * MASK_WIDTH + rank2] = 1'b1;
+						else
+							assign ac_masked_bus[rate * MASK_WIDTH + rank2] = ac_bus_internal[AC_BUS_WIDTH + rate/2] | cs_mask[rank2];
+					end else begin
+						if (rate == 0)
+							assign ac_masked_bus[rate * MASK_WIDTH + rank2] = ac_bus_internal[AC_BUS_WIDTH + 0] | cs_mask[rank2];
+						else
+							assign ac_masked_bus[rate * MASK_WIDTH + rank2] = ac_bus_internal[AC_BUS_WIDTH + 1] | cs_mask[rank2];
+					end
+				end
+				else begin
+						assign ac_masked_bus[rate * MASK_WIDTH + rank2] = ac_bus_internal[AC_BUS_WIDTH + rate] | cs_mask[rank2];
+				end
+			end
+		end
+	endgenerate
+
+	wire [INST_ROM_ADDRESS_WIDTH - 1:0] inst_ROM_address = next_PC;
+
+	
+	generate
+		begin
+			if (HCX_COMPAT_MODE)
+				if (DEVICE_FAMILY == "STRATIXIII")
+					rw_manager_inst_ROM_hcx_compat_mode_stratixiii #(
+						.ROM_INIT_FILE_NAME(INST_ROM_INIT_FILE_NAME)
+					)
+					inst_ROM_i (
+						.data(inst_ROM_wrdata),
+						.wraddress(inst_ROM_wraddress),
+						.wren(inst_ROM_wren),
+						.rdaddress(inst_ROM_address),
+						.clock(afi_clk),
+						.q(opcode)
+					);
+				else
+					rw_manager_inst_ROM_hcx_compat_mode #(
+						.ROM_INIT_FILE_NAME(INST_ROM_INIT_FILE_NAME)
+					)
+					inst_ROM_i (
+						.data(inst_ROM_wrdata),
+						.wraddress(inst_ROM_wraddress),
+						.wren(inst_ROM_wren),
+						.rdaddress(inst_ROM_address),
+						.clock(afi_clk),
+						.q(opcode)
+					);
+			else
+			    begin
+			        if (DEVICE_FAMILY == "MAX10")
+				        rw_manager_m10_inst_ROM inst_ROM_i (
+				        	.rdaddress(inst_ROM_address),
+				        	.clock(afi_clk),
+				        	.q(opcode)
+				        );
+				    else
+				        rw_manager_inst_ROM_no_ifdef_params #(
+				        	.ROM_INIT_FILE_NAME(INST_ROM_INIT_FILE_NAME)
+				        )
+				        inst_ROM_i (
+				        	.data(inst_ROM_wrdata),
+				        	.wraddress(inst_ROM_wraddress),
+				        	.wren(inst_ROM_wren),
+				        	.rdaddress(inst_ROM_address),
+				        	.clock(afi_clk),
+				        	.q(opcode)
+				        );
+				end
+		end
+	endgenerate
+
+	assign ac_bus_internal = ac_bus_from_rom[AC_ROM_DATA_WIDTH-1:0];
+	assign ac_ROM_wrdata_to_rom = ac_ROM_wrdata;
+	
+	generate
+		begin
+			if (HCX_COMPAT_MODE)
+				rw_manager_ac_ROM_hcx_compat_mode #(
+					.ROM_INIT_FILE_NAME(AC_ROM_INIT_FILE_NAME)
+				)
+				ac_ROM_i (
+					.data(ac_ROM_wrdata_to_rom),
+					.wraddress(ac_ROM_wraddress),
+					.wren(ac_ROM_wren),
+					.rdaddress(ac_address),
+					.clock(afi_clk),
+					.q(ac_bus_from_rom)
+				);
+			else
+			    begin
+			        if (DEVICE_FAMILY == "MAX10")
+			            rw_manager_m10_ac_ROM ac_ROM_i (
+				        	.rdaddress(ac_address),
+				        	.clock(afi_clk),
+				        	.q(ac_bus_from_rom)
+				        );
+			        else
+				        rw_manager_ac_ROM_no_ifdef_params #(
+				        	.ROM_INIT_FILE_NAME(AC_ROM_INIT_FILE_NAME)
+				        )
+				        ac_ROM_i (
+				        	.data(ac_ROM_wrdata_to_rom),
+				        	.wraddress(ac_ROM_wraddress),
+				        	.wren(ac_ROM_wren),
+				        	.rdaddress(ac_address),
+				        	.clock(afi_clk),
+				        	.q(ac_bus_from_rom)
+				        );
+				end
+		end
+	endgenerate
+
+	function [DI_ADDR_WIDTH-1:0] truncate_di_buffer_bits(input[31:0] di_buffer_input);
+		return di_buffer_input[DI_ADDR_WIDTH-1:0];
+	endfunction
+
+	wire [DI_ADDR_WIDTH-1:0] di_buffer_read_address;
+	assign di_buffer_read_address = truncate_di_buffer_bits(avl_address_afi - 4);
+
+	rw_manager_di_buffer_wrap di_buffer_wrap_i(
+		.clock(afi_clk),
+		.data(read_datapath_input),
+		.rdaddress(di_buffer_read_address), 
+		.wraddress(di_buffer_write_address),
+		.wren(afi_rdata_valid_r),
+		.q(di_buffer_read_data),
+		.clear(di_buffer_clear));
+	defparam di_buffer_wrap_i.DATA_WIDTH = GROUP_BUS_SIZE;
+	defparam di_buffer_wrap_i.READ_DATA_SIZE = DEBUG_READ_DI_WIDTH;
+	defparam di_buffer_wrap_i.WRITE_TO_READ_RATIO_2_EXPONENT = DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT;
+	defparam di_buffer_wrap_i.WRITE_TO_READ_RATIO = DEBUG_WRITE_TO_READ_RATIO;
+	defparam di_buffer_wrap_i.ADDR_WIDTH = DI_ADDR_WIDTH;
+	defparam di_buffer_wrap_i.NUM_WORDS = MAX_DI_BUFFER_WORDS;
+
+	rw_manager_write_decoder write_decoder_i(
+		.ck(afi_clk),
+		.reset_n(rw_soft_reset_n),
+		.do_lfsr(DO_lfsr),
+		.dm_lfsr(DM_lfsr),
+		.do_lfsr_step(write_DO_lfsr_step),
+		.dm_lfsr_step(write_DM_lfsr_step),
+		.do_code(do_address),
+		.dm_code(dm_address),
+		.do_data(do_data),
+		.dm_data(dm_data)
+	);
+	defparam write_decoder_i.DATA_WIDTH = NUMBER_OF_WRITE_DQ_PER_DQS;
+	defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
+
+	wire enable_ap_mode;
+	assign enable_ap_mode = |(~cs_mask[1:0] & AP_MODE_EN); 
+
+
+
+	rw_manager_read_datapath read_datapath_i(
+		.ck(afi_clk),
+		.reset_n(rw_soft_reset_n),
+		.check_do(do_address),
+		.check_dm(dm_address),
+		.check_do_lfsr(DO_lfsr),
+		.check_dm_lfsr(DM_lfsr),
+		.check_pattern_push(r_wn),
+		.clear_error(cmd_clear_read_datapath),
+		.read_data(read_datapath_input),
+		.read_data_valid(read_datapath_valid),
+		.error_word(error_word),
+		.enable_ap_mode(enable_ap_mode)
+	);
+	defparam read_datapath_i.DATA_WIDTH = NUMBER_OF_READ_DQ_PER_DQS;
+	defparam read_datapath_i.AFI_RATIO = AFI_RATIO;
+
+	rw_manager_data_broadcast data_broadcast_i(
+		.dq_data_in(do_data_r),
+		.dm_data_in(dm_data_r),
+		.dq_data_out(afi_wdata),
+		.dm_data_out(afi_dm)
+	);
+	defparam data_broadcast_i.NUMBER_OF_DQS_GROUPS = MEM_WRITE_DQS_WIDTH;
+	defparam data_broadcast_i.NUMBER_OF_DQ_PER_DQS = NUMBER_OF_WRITE_DQ_PER_DQS;
+	defparam data_broadcast_i.AFI_RATIO = AFI_RATIO;
+	defparam data_broadcast_i.MEM_DM_WIDTH = MEM_DM_WIDTH;
+
+
+	assign jump_group_counter = jump_group_counter_ext[GROUP_COUNTER_WIDTH - 1:0];
+	assign group_select = group_mode ? jump_group_counter : cmd_run_group;
+
+	rw_manager_jumplogic jumplogic_i(
+		.ck(afi_clk),
+		.reset_n(rw_soft_reset_n),
+		.cntr_value(avl_writedata_afi[7:0]),
+		.cntr_load(cmd_load_cntr),
+		.reg_select(jump_reg),
+		.reg_load_select(cmd_reg_select),
+		.jump_value(avl_writedata_afi[7:0]),
+		.jump_load(cmd_load_jump_address),
+		.jump_check(jump),
+		.jump_taken(jump_taken),
+		.jump_address(jump_address_jumplogic),
+		.cntr_3(jump_group_counter_ext),
+		.jump_ptr_0_export(jump_ptr_0_export), 	
+		.jump_ptr_1_export(jump_ptr_1_export), 
+		.jump_cntr_0_export(jump_cntr_0_export), 	
+		.jump_cntr_1_export(jump_cntr_1_export) 
+	);
+
+	assign jump_address = jump_address_jumplogic[INST_ROM_ADDRESS_WIDTH - 1:0];
+		
+
+
+	genvar w;
+	generate
+		for(w = 0; w < 2 * AFI_RATIO; w = w + 1)
+		begin : mux_iter
+			rw_manager_datamux datamux_i(
+				.datain(afi_rdata[(w + 1) * MEM_READ_DQS_WIDTH * NUMBER_OF_READ_DQ_PER_DQS - 1 : w * MEM_READ_DQS_WIDTH * NUMBER_OF_READ_DQ_PER_DQS]),
+				.sel(group_select),
+				.dataout(DI_mux[ (w + 1) * NUMBER_OF_READ_DQ_PER_DQS - 1 : w * NUMBER_OF_READ_DQ_PER_DQS])
+			);
+			defparam datamux_i.DATA_WIDTH = NUMBER_OF_READ_DQ_PER_DQS;
+			defparam datamux_i.SELECT_WIDTH = GROUP_COUNTER_WIDTH;
+			defparam datamux_i.NUMBER_OF_CHANNELS = MEM_READ_DQS_WIDTH;
+		end
+	endgenerate
+
+	assign next_PC = (state == RW_MGR_STATE_IDLE && cmd_run) ? cmd_run_address :
+	                      ((jump_taken) ? jump_address : (return_code ? PC : (PC + 1'b1)));
+
+	always @(posedge afi_clk or negedge afi_reset_n) begin
+		if(~afi_reset_n) begin
+			state <= RW_MGR_STATE_IDLE;
+			group_mode <= 1'b0;
+			loopback_mode <= 1'b0;
+			di_buffer_write_address <= 0;
+			PC <= {INST_ROM_ADDRESS_WIDTH{1'b0}};
+			cs_mask <= {CS_MASK_WIDTH{1'b0}};			
+			odt_0_mask <= {CS_MASK_WIDTH{1'b0}};
+			odt_1_mask <= {CS_MASK_WIDTH{1'b0}};
+			active_rank <= {MEM_NUMBER_OF_RANKS{1'b0}};
+			cmd_reset_r <= 1'b0;
+			di_buffer_clear <= 1'b1;
+		end
+		else begin
+			if(~rw_soft_reset_n) begin
+				PC <= {INST_ROM_ADDRESS_WIDTH{1'b0}};
+			end
+			else begin
+				PC <= next_PC;
+			end
+
+			cmd_reset_r <= cmd_reset;
+
+			di_buffer_clear <= 1'b0;
+
+			if (cmd_clear_read_datapath && state == RW_MGR_STATE_IDLE) begin
+				di_buffer_clear <= 1'b1;
+				di_buffer_write_address <= 0;
+			end
+			else if (afi_rdata_valid_r) begin
+				di_buffer_write_address <= di_buffer_write_address + 1'b1;
+			end
+
+			if(cmd_set_cs_mask) begin
+				cs_mask <= cs_mask_setting;
+				odt_0_mask <= odt_0_mask_setting[CS_MASK_WIDTH - 1:0];
+				odt_1_mask <= odt_1_mask_setting[CS_MASK_WIDTH - 1:0];
+			end
+			
+			if(cmd_set_active_rank) begin
+				active_rank <= active_rank_setting;
+			end
+
+			case(state)
+				RW_MGR_STATE_IDLE : begin
+					if(cmd_run) begin
+						state <= RW_MGR_STATE_RUNNING;
+						group_mode <= cmd_run_all_groups;
+						loopback_mode <= option_loopback_mode;
+					end
+					else if(cmd_read) begin
+						state <= RW_MGR_STATE_READING;
+					end 
+					else if(cmd_load) begin
+						state <= RW_MGR_STATE_DONE;
+					end 
+				end
+
+				RW_MGR_STATE_READING : begin
+					state <= RW_MGR_STATE_DONE;
+				end
+
+				RW_MGR_STATE_RUNNING : begin
+					if(return_code) begin
+						state <= RW_MGR_STATE_DONE;
+					end
+				end
+
+				RW_MGR_STATE_DONE : begin
+					if(~cmd_read_afi & ~cmd_write_afi) begin
+						state <= RW_MGR_STATE_IDLE;
+					end
+				end
+			endcase
+		end
+	end
+
+// synthesis translate_off
+    assert property (@(posedge (state == RW_MGR_STATE_DONE)) 1);
+// synthesis translate_on
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_broadcast.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_broadcast.v
new file mode 100644
index 0000000..168dd39
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_broadcast.v
@@ -0,0 +1,58 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_data_broadcast(
+	dq_data_in,
+	dm_data_in,
+	dq_data_out,
+	dm_data_out
+);
+
+	parameter NUMBER_OF_DQS_GROUPS 	= "";
+	parameter NUMBER_OF_DQ_PER_DQS 	= "";
+	parameter AFI_RATIO 		= "";
+	parameter MEM_DM_WIDTH		= "";
+
+	localparam NUMBER_OF_DQ_BITS = NUMBER_OF_DQS_GROUPS * NUMBER_OF_DQ_PER_DQS;
+	localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
+
+	input [NUMBER_OF_DQ_PER_DQS * NUMBER_OF_WORDS - 1 : 0] dq_data_in;
+	input [NUMBER_OF_WORDS - 1 : 0] dm_data_in;
+	output [NUMBER_OF_DQ_BITS * NUMBER_OF_WORDS - 1 : 0] dq_data_out;
+	output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1 : 0] dm_data_out;
+
+	genvar gr, wr, dmbit;
+	generate
+		for(wr = 0; wr < NUMBER_OF_WORDS; wr = wr + 1)
+		begin : word
+			for(gr = 0; gr < NUMBER_OF_DQS_GROUPS; gr = gr + 1)
+			begin : group
+				assign dq_data_out[wr * NUMBER_OF_DQ_BITS + (gr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_BITS + gr * NUMBER_OF_DQ_PER_DQS] = 
+					dq_data_in[(wr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_PER_DQS];
+			end
+
+			for(dmbit = 0; dmbit < MEM_DM_WIDTH; dmbit = dmbit + 1)
+			begin : data_mask_bit
+				assign dm_data_out[wr * MEM_DM_WIDTH + dmbit] = dm_data_in[wr];
+			end
+		end
+	endgenerate
+	
+`ifdef ADD_UNIPHY_SIM_SVA
+	assert property (@dm_data_in NUMBER_OF_DQS_GROUPS == MEM_DM_WIDTH) else
+	    $error("%t, [DATA BROADCAST ASSERT] NUMBER_OF_DQS_GROUPS and MEM_DM_WIDTH mismatch, NUMBER_OF_DQS_GROUPS = %d, MEM_DM_WIDTH = %d", $time, NUMBER_OF_DQS_GROUPS, MEM_DM_WIDTH);
+`endif
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_decoder.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_decoder.v
new file mode 100644
index 0000000..07edfe8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_data_decoder.v
@@ -0,0 +1,80 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_data_decoder(
+	ck, 
+	reset_n, 
+	code, 
+	pattern
+);
+
+	parameter DATA_WIDTH 		= "";
+	parameter AFI_RATIO 		= "";
+
+	input ck;
+	input reset_n;
+	input [3:0] code;
+	output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] pattern;
+
+	reg [3:0] code_R;
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			code_R <= 4'b0000;
+		end
+		else begin
+			code_R <= code;
+		end
+	end
+
+	genvar j;
+	generate
+		for(j = 0; j < DATA_WIDTH; j = j + 1)
+		begin : bit_pattern
+			if(j % 2 == 0) begin
+				assign pattern[j] = code_R[3];
+				assign pattern[j + DATA_WIDTH] = code_R[2];
+				if (AFI_RATIO == 2) begin
+					assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
+					assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
+				end else if (AFI_RATIO == 4) begin 
+					assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
+					assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
+					assign pattern[j + 4 * DATA_WIDTH] = code_R[3];
+					assign pattern[j + 5 * DATA_WIDTH] = code_R[2];
+					assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1];
+					assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1];
+				end
+			end
+			else begin
+				assign pattern[j] = code_R[3] ^ code_R[0];
+				assign pattern[j + DATA_WIDTH] = code_R[2] ^ code_R[0];
+				if (AFI_RATIO == 2) begin
+					assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
+					assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
+				end else if (AFI_RATIO == 4) begin 
+					assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
+					assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
+					assign pattern[j + 4 * DATA_WIDTH] = code_R[3] ^ code_R[0];
+					assign pattern[j + 5 * DATA_WIDTH] = code_R[2] ^ code_R[0];
+					assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
+					assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
+				end
+			end
+		end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_datamux.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_datamux.v
new file mode 100644
index 0000000..abdd497
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_datamux.v
@@ -0,0 +1,42 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_datamux(datain, sel, dataout);
+	parameter DATA_WIDTH = 8;
+	parameter SELECT_WIDTH = 1;
+	parameter NUMBER_OF_CHANNELS = 2;
+
+	input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
+	input [SELECT_WIDTH - 1 : 0] sel;
+	output [DATA_WIDTH - 1 : 0] dataout;
+
+	wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
+
+	assign dataout = vectorized_data[sel];
+
+	genvar c;
+	generate
+		for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1) 
+		begin : channel_iterator
+			assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
+		end
+	endgenerate
+	
+`ifdef ADD_UNIPHY_SIM_SVA
+	assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
+	    $error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
+`endif
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ddr3.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ddr3.v
new file mode 100644
index 0000000..acebcb4
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ddr3.v
@@ -0,0 +1,232 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_ddr3 (
+	avl_clk,
+	avl_reset_n,
+	avl_address,
+	avl_write,
+	avl_writedata,
+	avl_read,
+	avl_readdata,
+	avl_waitrequest,
+
+	afi_clk,
+	afi_reset_n,
+	afi_addr,
+	afi_ba,
+	afi_cs_n,
+	afi_cke,
+	afi_odt,
+	afi_ras_n,
+	afi_cas_n,
+	afi_we_n,
+	afi_dqs_burst,
+	afi_rst_n,
+	afi_wdata,
+	afi_wdata_valid,
+	afi_dm,
+	afi_rdata_en,
+	afi_rdata_en_full,
+	afi_rdata,
+	afi_rdata_valid,
+	afi_wrank,
+	afi_rrank,
+	csr_clk,
+	csr_ena,
+	csr_dout_phy,
+	csr_dout
+);
+
+	parameter AVL_DATA_WIDTH 			= 32;
+	parameter AVL_ADDR_WIDTH			= 16;
+	
+	parameter MEM_ADDRESS_WIDTH			= 19;
+	parameter MEM_CONTROL_WIDTH			= 4;
+	parameter MEM_DQ_WIDTH				= 36;
+	parameter MEM_DM_WIDTH				= 4;
+	parameter MEM_NUMBER_OF_RANKS			= 1;
+	parameter MEM_CLK_EN_WIDTH			= 1;
+
+	parameter MEM_BANK_WIDTH			= 2;
+	parameter MEM_ODT_WIDTH				= 2;
+	parameter MEM_CHIP_SELECT_WIDTH			= 1;
+
+	parameter MEM_READ_DQS_WIDTH 			= 4;
+	parameter MEM_WRITE_DQS_WIDTH			= 4;
+
+	parameter AFI_RATIO = 2;
+
+	parameter RATE = "Half";
+	parameter HCX_COMPAT_MODE = 0;
+	parameter DEVICE_FAMILY = "STRATIXIV";
+
+	parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
+	parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
+	
+	parameter DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = 0;
+	parameter DEBUG_WRITE_TO_READ_RATIO = 0;
+	parameter MAX_DI_BUFFER_WORDS_LOG_2 = 0;
+
+	parameter AVL_CLK_PS = 123;
+	parameter AFI_CLK_PS = 456;
+	parameter ENABLE_NON_DES_CAL = 0;
+	parameter TREFI = 36000;
+	parameter REFRESH_INTERVAL = 30000;
+	parameter TRFC = 370;
+	parameter AP_MODE_EN= 2'b00;
+
+	input avl_clk;
+	input avl_reset_n;
+	input [AVL_ADDR_WIDTH-1:0] avl_address;
+	input avl_write;
+	input [AVL_DATA_WIDTH-1:0] avl_writedata;
+	input avl_read;
+	output [AVL_DATA_WIDTH-1:0] avl_readdata;
+	output avl_waitrequest;
+
+	input afi_clk;
+	input afi_reset_n;
+	output [MEM_ADDRESS_WIDTH * AFI_RATIO - 1:0] afi_addr;
+	
+	output [MEM_BANK_WIDTH * AFI_RATIO - 1:0] afi_ba;
+	output [MEM_CHIP_SELECT_WIDTH * AFI_RATIO - 1:0] afi_cs_n;
+	output [MEM_CLK_EN_WIDTH * AFI_RATIO - 1:0] afi_cke;
+	output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
+	output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_ras_n;
+	output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_cas_n;
+	output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_we_n;
+	output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_dqs_burst;
+	output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_rst_n;
+
+	output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
+	output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_wdata_valid;
+	output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
+	output [AFI_RATIO-1:0] afi_rdata_en;
+	output [AFI_RATIO-1:0] afi_rdata_en_full;
+	input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
+	input [AFI_RATIO-1:0] afi_rdata_valid;
+	output [MEM_WRITE_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO -1:0] afi_wrank;
+	output [MEM_READ_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO -1:0] afi_rrank;
+
+	input csr_clk;       
+	input csr_ena;       
+	input csr_dout_phy;  
+	output csr_dout;
+	
+	parameter AC_BUS_WIDTH = 30;
+
+	wire [AC_BUS_WIDTH - 1:0] ac_bus;
+
+	rw_manager_generic rw_mgr_inst (
+		.avl_clk(avl_clk),
+		.avl_reset_n(avl_reset_n),
+		.avl_address(avl_address),
+		.avl_write(avl_write),
+		.avl_writedata(avl_writedata),
+		.avl_read(avl_read),
+		.avl_readdata(avl_readdata),
+		.avl_waitrequest(avl_waitrequest),
+
+		.afi_clk(afi_clk),
+		.afi_reset_n(afi_reset_n),
+		.ac_masked_bus (afi_cs_n),
+		.ac_bus (ac_bus),
+		.afi_wdata(afi_wdata),
+		.afi_dm(afi_dm),
+		.afi_odt(afi_odt),
+		.afi_rdata(afi_rdata),
+		.afi_rdata_valid(afi_rdata_valid[0]),
+		.afi_wrank(afi_wrank),
+		.afi_rrank(afi_rrank),
+		.csr_clk(csr_clk),
+		.csr_ena(csr_ena),
+		.csr_dout_phy(csr_dout_phy),
+		.csr_dout(csr_dout)
+	);
+	defparam rw_mgr_inst.AVL_CLK_PS = AVL_CLK_PS;
+	defparam rw_mgr_inst.AFI_CLK_PS = AFI_CLK_PS;
+	defparam rw_mgr_inst.ENABLE_NON_DES_CAL = ENABLE_NON_DES_CAL;
+	defparam rw_mgr_inst.TREFI = TREFI;
+	defparam rw_mgr_inst.REFRESH_INTERVAL = REFRESH_INTERVAL;
+	defparam rw_mgr_inst.TRFC = TRFC;
+
+	defparam rw_mgr_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
+	defparam rw_mgr_inst.AVL_ADDRESS_WIDTH = AVL_ADDR_WIDTH;
+	defparam rw_mgr_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
+	defparam rw_mgr_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
+	defparam rw_mgr_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
+	defparam rw_mgr_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
+	defparam rw_mgr_inst.AC_MASKED_BUS_WIDTH = MEM_CHIP_SELECT_WIDTH * AFI_RATIO;
+	defparam rw_mgr_inst.MASK_WIDTH = MEM_CHIP_SELECT_WIDTH;
+	defparam rw_mgr_inst.AFI_RATIO = AFI_RATIO;
+	defparam rw_mgr_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
+	defparam rw_mgr_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
+	defparam rw_mgr_inst.MEM_NUMBER_OF_RANKS = MEM_NUMBER_OF_RANKS;
+	defparam rw_mgr_inst.RATE = RATE;
+	defparam rw_mgr_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
+	defparam rw_mgr_inst.DEVICE_FAMILY = DEVICE_FAMILY;
+	defparam rw_mgr_inst.DEBUG_READ_DI_WIDTH = 32;
+	defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT;
+	defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO = DEBUG_WRITE_TO_READ_RATIO;
+	defparam rw_mgr_inst.MAX_DI_BUFFER_WORDS_LOG_2 = MAX_DI_BUFFER_WORDS_LOG_2;
+	defparam rw_mgr_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
+	defparam rw_mgr_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
+	defparam rw_mgr_inst.AC_ODT_BIT =
+		(AFI_RATIO == 4) ? 27 : 
+		(AFI_RATIO == 2) ? 25 : 
+		24; 
+        defparam rw_mgr_inst.AP_MODE_EN = AP_MODE_EN;
+
+
+generate
+begin
+	wire [MEM_ADDRESS_WIDTH-1:0] afi_address_half;
+	assign afi_address_half = ac_bus[12:0];
+	assign afi_addr = {AFI_RATIO{afi_address_half}};
+	assign afi_ba = {AFI_RATIO{ac_bus[15:13]}};
+	assign afi_rst_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
+	assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
+	assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
+	assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[19]}};
+
+	if (AFI_RATIO == 4) begin
+		assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[23]}}, 
+		                       {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[22]}},
+		                       {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[21]}},
+		                     {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[20]}}};
+		assign afi_rdata_en_full = {AFI_RATIO{ac_bus[24]}};
+		assign afi_rdata_en = {AFI_RATIO{ac_bus[25]}};
+		assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[26]}};
+		assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[28]}};
+	end else if (AFI_RATIO == 2) begin
+		assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[21]}}, {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[20]}}};
+		assign afi_rdata_en_full = {AFI_RATIO{ac_bus[22]}};
+		assign afi_rdata_en = {AFI_RATIO{ac_bus[23]}};
+		assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[24]}};
+		assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[26]}};
+	end else begin
+		assign afi_dqs_burst = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[20]}};
+		assign afi_rdata_en_full = {AFI_RATIO{ac_bus[21]}};
+		assign afi_rdata_en = {AFI_RATIO{ac_bus[22]}};
+		assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[23]}};
+		assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[25]}};
+	end
+end
+endgenerate
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer.v
new file mode 100644
index 0000000..2ce3b83
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer.v
@@ -0,0 +1,139 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+
+
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rw_manager_di_buffer (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q,
+	clear);
+
+	parameter DATA_WIDTH = 32;
+	parameter ADDR_WIDTH = 4;
+	parameter NUM_WORDS = 16;
+
+	input	  clock;
+	input	[DATA_WIDTH-1:0]  data;
+	input	[ADDR_WIDTH-1:0]  rdaddress;
+	input	[ADDR_WIDTH-1:0]  wraddress;
+	input	  wren;
+	output	[DATA_WIDTH-1:0]  q;
+	input clear;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+// synthesis translate_off
+
+	reg	[DATA_WIDTH-1:0]  q;
+	reg [DATA_WIDTH-1:0] mem [0:NUM_WORDS-1];
+	integer i;
+/*
+	integer j;
+    always @(posedge clock or posedge clear) begin
+        if (clear) begin
+			for (i = 0; i < NUM_WORDS; i = i + 1) begin
+				for (j = 0; j < DATA_WIDTH/32; j = j+ 1) begin
+					mem[i][32*j+:32] <= i*(DATA_WIDTH/32) + j;
+				end
+			end
+		end
+		else begin
+			q <= mem[rdaddress];
+		end
+	end
+*/
+
+    always @(posedge clock or posedge clear) begin
+        if (clear) begin
+			for (i = 0; i < NUM_WORDS; i = i + 1) begin
+				mem[i] <= 0;
+			end
+		end
+		else begin
+			if (wren)
+				mem[wraddress] <= data;
+			q <= mem[rdaddress];
+		end
+	end
+
+// synthesis translate_on
+
+// synthesis read_comments_as_HDL on
+// 	wire [DATA_WIDTH-1:0] sub_wire0;
+// 	wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
+// 	
+// 	altsyncram	altsyncram_component (
+// 				.address_a (wraddress),
+// 				.clock0 (clock),
+// 				.data_a (data),
+// 				.wren_a (wren),
+// 				.address_b (rdaddress),
+// 				.q_b (sub_wire0),
+// 				.aclr0 (1'b0),
+// 				.aclr1 (1'b0),
+// 				.addressstall_a (1'b0),
+// 				.addressstall_b (1'b0),
+// 				.byteena_a (1'b1),
+// 				.byteena_b (1'b1),
+// 				.clock1 (1'b1),
+// 				.clocken0 (1'b1),
+// 				.clocken1 (1'b1),
+// 				.clocken2 (1'b1),
+// 				.clocken3 (1'b1),
+// 				.data_b ({DATA_WIDTH{1'b1}}),
+// 				.eccstatus (),
+// 				.q_a (),
+// 				.rden_a (1'b1),
+// 				.rden_b ((rdaddress < NUM_WORDS) ? 1'b1 : 1'b0),
+// 				.wren_b (1'b0));
+// 	defparam
+// 		altsyncram_component.address_aclr_b = "NONE",
+// 		altsyncram_component.address_reg_b = "CLOCK0",
+// 		altsyncram_component.clock_enable_input_a = "BYPASS",
+// 		altsyncram_component.clock_enable_input_b = "BYPASS",
+// 		altsyncram_component.clock_enable_output_b = "BYPASS",
+// 		altsyncram_component.intended_device_family = "Stratix III",
+// 		altsyncram_component.lpm_type = "altsyncram",
+// 		altsyncram_component.numwords_a = NUM_WORDS,
+// 		altsyncram_component.numwords_b = NUM_WORDS,
+// 		altsyncram_component.operation_mode = "DUAL_PORT",
+// 		altsyncram_component.outdata_aclr_b = "NONE",
+// 		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+// 		altsyncram_component.power_up_uninitialized = "FALSE",
+// 		altsyncram_component.ram_block_type = "MLAB",
+// 		altsyncram_component.widthad_a = ADDR_WIDTH,
+// 		altsyncram_component.widthad_b = ADDR_WIDTH,
+// 		altsyncram_component.width_a = DATA_WIDTH,
+// 		altsyncram_component.width_b = DATA_WIDTH,
+// 		altsyncram_component.width_byteena_a = 1;
+// synthesis read_comments_as_HDL off
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v
new file mode 100644
index 0000000..1627504
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_di_buffer_wrap.v
@@ -0,0 +1,78 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_di_buffer_wrap(
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q,
+	clear);
+
+	parameter DATA_WIDTH = 18;
+	parameter READ_DATA_SIZE = 9;
+	parameter WRITE_TO_READ_RATIO_2_EXPONENT = 2;
+	parameter WRITE_TO_READ_RATIO = 1;
+	parameter ADDR_WIDTH = 2;
+	parameter NUM_WORDS = 16;
+
+	input clock;
+	input [DATA_WIDTH-1:0] data;
+	input [ADDR_WIDTH - 1 : 0] rdaddress;
+	input [ADDR_WIDTH-1:0] wraddress;
+	input wren;
+	output [READ_DATA_SIZE - 1 : 0] q;
+	input clear;
+
+	wire [DATA_WIDTH-1:0] q_wire;
+	wire wren_gated;
+
+	wire [ADDR_WIDTH + ADDR_WIDTH - WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0] rdaddress_tmp = {{ADDR_WIDTH{1'b0}}, rdaddress[ADDR_WIDTH-1 : WRITE_TO_READ_RATIO_2_EXPONENT]};
+
+	assign wren_gated = (wraddress >= NUM_WORDS) ? 1'b0 : wren;
+
+	rw_manager_di_buffer rw_manager_di_buffer_i(
+		.clock(clock),
+		.data(data),
+		.rdaddress(rdaddress_tmp[ADDR_WIDTH-1 : 0]),
+		.wraddress(wraddress),
+		.wren(wren_gated),
+		.q(q_wire),
+		.clear(clear));
+	defparam rw_manager_di_buffer_i.DATA_WIDTH = DATA_WIDTH;
+	defparam rw_manager_di_buffer_i.ADDR_WIDTH = ADDR_WIDTH;
+	defparam rw_manager_di_buffer_i.NUM_WORDS = NUM_WORDS;
+	
+	generate
+		if(WRITE_TO_READ_RATIO_2_EXPONENT > 0) begin
+			
+			wire [WRITE_TO_READ_RATIO * READ_DATA_SIZE + DATA_WIDTH - 1 : 0] datain_tmp = {{(WRITE_TO_READ_RATIO * READ_DATA_SIZE){1'b0}}, q_wire};
+
+			rw_manager_datamux rw_manager_datamux_i(
+				.datain(datain_tmp[WRITE_TO_READ_RATIO*READ_DATA_SIZE-1:0]),
+				.sel(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0]),
+				.dataout(q)
+			);
+			defparam rw_manager_datamux_i.DATA_WIDTH = READ_DATA_SIZE;
+			defparam rw_manager_datamux_i.SELECT_WIDTH = WRITE_TO_READ_RATIO_2_EXPONENT;
+			defparam rw_manager_datamux_i.NUMBER_OF_CHANNELS = WRITE_TO_READ_RATIO;
+		end
+		else begin
+			assign q = q_wire;
+		end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_dm_decoder.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_dm_decoder.v
new file mode 100644
index 0000000..8ff5bf4
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_dm_decoder.v
@@ -0,0 +1,55 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_dm_decoder(ck, reset_n, code, pattern);
+	
+	parameter AFI_RATIO 	= "";
+
+	input ck;
+	input reset_n;
+	input [2:0] code;
+	output [2 * AFI_RATIO - 1 : 0] pattern;
+
+	reg [2:0] code_R;
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			code_R <= 3'b000;
+		end
+		else begin
+			code_R <= code;
+		end
+	end
+	
+	
+	assign pattern[0] = code_R[2];
+	assign pattern[1] = code_R[1];
+
+	generate
+	if (AFI_RATIO == 2)	begin
+	    assign pattern[2] = code_R[2] ^ code_R[0];
+	    assign pattern[3] = code_R[1] ^ code_R[0];
+	end else if (AFI_RATIO == 4) begin
+	    assign pattern[2] = code_R[2] ^ code_R[0];
+	    assign pattern[3] = code_R[1] ^ code_R[0];
+	    assign pattern[4] = code_R[2];
+	    assign pattern[5] = code_R[1];
+	    assign pattern[6] = code_R[2] ^ code_R[0];
+	    assign pattern[7] = code_R[1] ^ code_R[0];
+	end
+	endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_generic.sv b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_generic.sv
new file mode 100644
index 0000000..6a3e3cf
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_generic.sv
@@ -0,0 +1,713 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_generic (
+	avl_clk,
+	avl_reset_n,
+	avl_address,
+	avl_write,
+	avl_writedata,
+	avl_read,
+	avl_readdata,
+	avl_waitrequest,
+
+	afi_clk,
+	afi_reset_n,
+	afi_wdata,
+	afi_dm,
+	afi_odt,
+	afi_rdata,
+	afi_rdata_valid,
+	afi_wrank,
+	afi_rrank,
+
+	ac_masked_bus,
+	ac_bus,
+	csr_clk,
+	csr_ena,
+	csr_dout_phy,
+	csr_dout
+
+);
+
+	parameter AVL_DATA_WIDTH 			= "";
+	parameter AVL_ADDRESS_WIDTH			= "";
+	
+	parameter MEM_DQ_WIDTH				= "";
+	parameter MEM_DM_WIDTH				= "";
+	parameter MEM_ODT_WIDTH 			= "";
+	parameter MEM_NUMBER_OF_RANKS		= "";
+	parameter MASK_WIDTH				= "";
+	parameter AC_ODT_BIT				= "";
+	parameter AC_BUS_WIDTH				= "";
+	parameter AC_MASKED_BUS_WIDTH			= "";
+	parameter AFI_RATIO				= "";
+
+	parameter MEM_READ_DQS_WIDTH 			= "";
+	parameter MEM_WRITE_DQS_WIDTH			= "";
+
+	parameter DEBUG_READ_DI_WIDTH			= "";
+	parameter DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT	= "";
+	parameter DEBUG_WRITE_TO_READ_RATIO	= "";
+	parameter MAX_DI_BUFFER_WORDS_LOG_2 = "";
+
+	parameter RATE = "";
+	parameter HCX_COMPAT_MODE = 0;
+	parameter DEVICE_FAMILY = "";
+	parameter AC_ROM_INIT_FILE_NAME = "";
+	parameter INST_ROM_INIT_FILE_NAME = "";
+	
+	parameter USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE = 0;
+
+	parameter AP_MODE_EN = 2'b00;
+
+	parameter AVL_CLK_PS = 1000;
+	parameter AFI_CLK_PS = 1000;
+
+	parameter ENABLE_NON_DES_CAL = 0;
+	parameter TREFI = 36000;
+	parameter REFRESH_INTERVAL = 30000;
+	parameter TRFC = 370;
+	parameter REFRESH_RANKS_SIMUL = 1;
+
+	input avl_clk;
+	input avl_reset_n;
+	input [AVL_ADDRESS_WIDTH-1:0] avl_address;
+	input avl_write;
+	input [AVL_DATA_WIDTH-1:0] avl_writedata;
+	input avl_read;
+	output [AVL_DATA_WIDTH-1:0] avl_readdata;
+	output avl_waitrequest;
+
+	input afi_clk;
+	input afi_reset_n;
+	
+	output [AC_MASKED_BUS_WIDTH - 1:0] ac_masked_bus;
+	output [AC_BUS_WIDTH - 1:0] ac_bus;
+	output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
+	output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
+	output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
+	output [MEM_WRITE_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO - 1:0] afi_wrank;
+	output [MEM_READ_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO - 1:0] afi_rrank;
+
+	input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
+	input afi_rdata_valid;
+
+        input                         csr_clk;       
+        input                         csr_ena;       
+        input                         csr_dout_phy;       
+        output  csr_dout;
+
+
+
+	reg [AVL_DATA_WIDTH-1:0] avl_readdata;
+	reg avl_waitrequest;
+	
+	wire avl_wr;
+	reg cmd_done_avl;
+
+	wire [AC_BUS_WIDTH - 1:0] ac_bus;
+	wire [AC_MASKED_BUS_WIDTH - 1:0] ac_masked_bus;
+
+	reg [AVL_DATA_WIDTH-1:0] avl_readdata_raw;	
+
+	wire avl_rd;
+	wire cmd_read;
+	wire cmd_write;
+	reg avl_rd_r;
+	reg avl_wr_r;
+
+
+	typedef enum int unsigned {
+		STATE_RW_IDLE,
+		STATE_RW_EXEC,
+		STATE_RW_DONE,
+	 	STATE_RW_REFRESH,
+		STATE_RW_RESTORE
+	} STATE_RW_T;
+
+	STATE_RW_T state;
+
+
+	assign avl_rd = avl_read;
+
+
+	wire  [7:0] jump_ptr_0_export; 	
+	wire  [7:0] jump_ptr_1_export; 
+	wire  [7:0] jump_cntr_0_export; 	
+	wire  [7:0] jump_cntr_1_export;
+	wire  [7:0] cs_mask_export;
+
+	reg  [7:0] jump_ptr_0_reg; 	
+	reg  [7:0] jump_ptr_1_reg; 
+	reg  [7:0] jump_cntr_0_reg; 	
+	reg  [7:0] jump_cntr_1_reg;
+	reg  [7:0] cs_mask_reg;
+
+	reg req_avl_bus;
+	reg have_avl_bus;
+	wire all_refresh_done;
+	wire restore_done;
+	reg refresh_enabled;
+	reg refresh_took_too_long;
+
+	generate
+	if (ENABLE_NON_DES_CAL==1)
+	begin
+		wire decode_enable_refresh;
+		assign decode_enable_refresh = (avl_address [11:8] == 4'b1100);
+	
+		always @(posedge avl_clk or negedge avl_reset_n)
+		begin
+			if (~avl_reset_n)
+				refresh_enabled <= 1'b0;
+			else if (avl_write & decode_enable_refresh)
+			begin
+				if (avl_writedata == {AVL_DATA_WIDTH{1'b0}})
+					refresh_enabled <= 1'b0;
+				else
+					refresh_enabled <= 1'b1;
+			end
+		end
+
+		
+		assign avl_wr = avl_write & ~decode_enable_refresh;  
+		assign avl_readdata = (decode_enable_refresh)?  {'0, refresh_took_too_long}: avl_readdata_raw;
+
+	end
+	else
+	begin
+		assign req_avl_bus = 1'b0;
+		assign avl_wr = avl_write;
+		assign avl_readdata = avl_readdata_raw;
+	end
+	endgenerate
+
+
+
+
+	always_ff @(posedge avl_clk) begin
+		if (~avl_reset_n) begin
+			state <= STATE_RW_IDLE;
+			
+			cs_mask_reg <= '0;
+			jump_ptr_0_reg <= '0; 	
+			jump_ptr_1_reg <= '0; 
+			jump_cntr_0_reg <= '0; 	
+			jump_cntr_1_reg <= '0;
+		
+		end else begin
+			case (state)
+			STATE_RW_IDLE:
+				begin
+				    if (req_avl_bus) begin
+					state <= STATE_RW_REFRESH;
+
+					cs_mask_reg <= cs_mask_export;
+					jump_ptr_0_reg <= jump_ptr_0_export; 	
+					jump_ptr_1_reg <= jump_ptr_1_export; 
+					jump_cntr_0_reg <= jump_cntr_0_export; 	
+					jump_cntr_1_reg <= jump_cntr_1_export;
+
+
+
+			            end else
+				    begin		
+					    if (avl_rd) begin
+						    state <= STATE_RW_EXEC;
+					    end
+					    if (avl_wr) begin
+						    state <= STATE_RW_EXEC;
+					    end
+				    end
+				end
+			STATE_RW_EXEC: 
+				if (cmd_done_avl) begin
+					state <= STATE_RW_DONE;
+				end
+			STATE_RW_DONE: 
+				begin
+				    state <= STATE_RW_IDLE;
+				end
+			STATE_RW_REFRESH:
+				begin
+					if (all_refresh_done) begin		
+						state <= STATE_RW_RESTORE;
+					end
+				end
+			STATE_RW_RESTORE:
+				begin	
+					if (restore_done) begin
+						state <= STATE_RW_DONE;
+					end
+				end
+
+			endcase
+		end
+	end
+
+
+	reg [AVL_DATA_WIDTH - 1:0] avl_writedata_avl;
+	reg [AVL_ADDRESS_WIDTH - 1:0] avl_address_avl;
+	wire [AVL_DATA_WIDTH - 1:0] avl_readdata_afi;
+	wire cmd_done_afi;
+
+	reg [AVL_DATA_WIDTH - 1:0] avl_writedata_avl_refresh;
+	reg [AVL_ADDRESS_WIDTH - 1:0] avl_address_avl_refresh;
+	wire [AVL_DATA_WIDTH - 1:0] avl_writedata_avl_muxed;
+	wire [AVL_ADDRESS_WIDTH - 1:0] avl_address_avl_muxed;
+
+	wire cmd_read_muxed;
+	wire cmd_write_muxed;
+
+
+
+	generate
+	if (ENABLE_NON_DES_CAL==0)
+	begin
+		assign avl_writedata_avl_muxed = avl_writedata_avl;
+		assign avl_address_avl_muxed = avl_address_avl;
+		assign cmd_read_muxed = cmd_read;
+		assign cmd_write_muxed = cmd_write;
+	end
+	endgenerate
+
+	reg [AVL_DATA_WIDTH - 1:0] avl_readdata_g_avl;
+
+	always @(posedge avl_clk or negedge avl_reset_n)
+	begin
+		if (~avl_reset_n)
+		begin
+		    avl_writedata_avl   <= {AVL_DATA_WIDTH{1'b0}};
+		    avl_address_avl     <= {AVL_ADDRESS_WIDTH{1'b0}};
+		    avl_readdata_g_avl	<= {AVL_DATA_WIDTH{1'b0}};
+		    cmd_done_avl	<= 1'b0;
+		    avl_rd_r		<= 1'b0;
+		    avl_wr_r		<= 1'b0;
+		end
+		else begin
+		    avl_writedata_avl   <= avl_writedata;
+		    avl_address_avl     <= avl_address;
+		    avl_readdata_g_avl	<= avl_readdata_afi;
+		    cmd_done_avl	<= cmd_done_afi;
+		    avl_rd_r		<= avl_rd;
+		    avl_wr_r		<= avl_wr;
+		end
+	end
+
+	rw_manager_core rw_mgr_core_inst (
+		.avl_reset_n(avl_reset_n),
+		.avl_clk(avl_clk),
+		.afi_clk(afi_clk),
+		.avl_address(avl_address_avl_muxed),
+		.avl_readdata(avl_readdata_afi),
+		.avl_writedata(avl_writedata_avl_muxed),
+		.afi_reset_n(afi_reset_n),
+		.afi_wdata(afi_wdata),
+		.afi_dm(afi_dm),
+		.afi_odt(afi_odt),
+		.afi_rdata(afi_rdata),
+		.afi_rdata_valid(afi_rdata_valid),
+		.afi_wrank(afi_wrank),
+		.afi_rrank(afi_rrank),
+		.ac_bus(ac_bus),
+		.ac_masked_bus(ac_masked_bus),
+		.cmd_read(cmd_read_muxed),
+		.cmd_write(cmd_write_muxed),
+		.cmd_done(cmd_done_afi),
+		.csr_clk(csr_clk),
+		.csr_ena(csr_ena),
+		.csr_dout_phy(csr_dout_phy),
+		.csr_dout(csr_dout),
+
+		.cs_mask_export(cs_mask_export),
+		.jump_ptr_0_export(jump_ptr_0_export), 	
+		.jump_ptr_1_export(jump_ptr_1_export), 
+		.jump_cntr_0_export(jump_cntr_0_export), 	
+		.jump_cntr_1_export(jump_cntr_1_export)
+
+	);
+	defparam rw_mgr_core_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
+	defparam rw_mgr_core_inst.AVL_ADDRESS_WIDTH = AVL_ADDRESS_WIDTH;
+	defparam rw_mgr_core_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
+	defparam rw_mgr_core_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
+	defparam rw_mgr_core_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
+	defparam rw_mgr_core_inst.MEM_NUMBER_OF_RANKS = MEM_NUMBER_OF_RANKS;
+	defparam rw_mgr_core_inst.MASK_WIDTH = MASK_WIDTH;
+	defparam rw_mgr_core_inst.AC_ODT_BIT = AC_ODT_BIT;
+	defparam rw_mgr_core_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
+	defparam rw_mgr_core_inst.AC_MASKED_BUS_WIDTH = AC_MASKED_BUS_WIDTH;
+	defparam rw_mgr_core_inst.AFI_RATIO = AFI_RATIO;
+	defparam rw_mgr_core_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
+	defparam rw_mgr_core_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
+	defparam rw_mgr_core_inst.DEBUG_READ_DI_WIDTH = DEBUG_READ_DI_WIDTH;
+	defparam rw_mgr_core_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT;
+	defparam rw_mgr_core_inst.DEBUG_WRITE_TO_READ_RATIO = DEBUG_WRITE_TO_READ_RATIO;
+	defparam rw_mgr_core_inst.RATE = RATE;
+	defparam rw_mgr_core_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
+	defparam rw_mgr_core_inst.DEVICE_FAMILY = DEVICE_FAMILY;
+	defparam rw_mgr_core_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
+	defparam rw_mgr_core_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
+	defparam rw_mgr_core_inst.MAX_DI_BUFFER_WORDS_LOG_2 = MAX_DI_BUFFER_WORDS_LOG_2;
+	defparam rw_mgr_core_inst.USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE = USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE;
+	defparam rw_mgr_core_inst.AP_MODE_EN = AP_MODE_EN;
+
+	assign cmd_read = avl_rd_r & ~cmd_done_avl & (state == STATE_RW_EXEC);
+	assign cmd_write = avl_wr_r & ~cmd_done_avl & (state == STATE_RW_EXEC);
+
+
+	always_comb
+	begin
+		if (((avl_wr || avl_rd) && (~cmd_done_avl || state != STATE_RW_EXEC)) || ~avl_reset_n || state == STATE_RW_REFRESH) 
+			avl_waitrequest = 1;
+		else
+			avl_waitrequest = 0;
+			
+		if (avl_rd)
+			avl_readdata_raw = avl_readdata_g_avl;
+		else
+			avl_readdata_raw = '0;
+	end
+	
+    assert property (@(posedge avl_reset_n) AC_MASKED_BUS_WIDTH == MASK_WIDTH*AFI_RATIO)
+	    $display("%t, [GENERIC ASSERT] AC_MASKED_BUS_WIDTH PARAMETER is correct", $time);
+	else
+	    $error("%t, [GENERIC ASSERT] AC_MASKED_BUS_WIDTH PARAMETER is incorrect, AC_MASKED_BUS_WIDTH = %d, MASK_WIDTH*AFI_RATIO = %d", $time, AC_MASKED_BUS_WIDTH, MASK_WIDTH*AFI_RATIO);
+	
+	assert property (@(posedge avl_clk) !avl_reset_n |-> !cmd_read);
+	assert property (@(posedge avl_clk) !avl_reset_n |-> avl_waitrequest);
+
+
+generate
+if (ENABLE_NON_DES_CAL==1)
+begin
+
+
+	localparam MAX_REFI_COUNT= (REFRESH_INTERVAL*1000)/AVL_CLK_PS;
+	localparam REALLY_MAX_REFI_COUNT = (TREFI*1000)/AVL_CLK_PS;
+	localparam MAX_TRFC = (TRFC*1000)/AFI_CLK_PS;
+	localparam WAIT_TIME = 400000/AVL_CLK_PS;   
+	reg [16:0] refi_counter;
+
+	reg [2:0] rank_counter;
+	wire refresh_done;
+
+	wire time_for_refresh;
+	assign time_for_refresh = (ENABLE_NON_DES_CAL==1) & (refi_counter == MAX_REFI_COUNT[16:0]);
+
+	typedef enum int unsigned {
+		STATE_RF_IDLE,
+		STATE_RF_SET_MASK,
+		STATE_RF_PRECHARGE,
+		STATE_RF_REFRESH_0,
+		STATE_RF_REFRESH_1,
+		STATE_RF_REFRESH_2,
+		STATE_RF_REFRESH_3,
+		STATE_RF_REFRESH_4,
+	
+		STATE_RF_WAIT,
+
+		STATE_RF_ACTIVATE_0,
+		STATE_RF_ACTIVATE_1,
+		STATE_RF_ACTIVATE_2,
+		STATE_RF_ACTIVATE_3,
+		STATE_RF_ACTIVATE_4,
+
+		STATE_RF_RESTORE_0,
+		STATE_RF_RESTORE_1,
+		STATE_RF_RESTORE_2,
+		STATE_RF_RESTORE_3,
+		STATE_RF_RESTORE_4
+
+
+	} STATE_RF_T;
+
+	STATE_RF_T rf_state;
+
+	STATE_RF_T next_rf_state;
+	
+	wire start_refresh;
+	wire issue_refresh_cmd;
+	wire go_next_refresh;
+	
+	wire wait_done;
+	reg refresh_cmd;
+	reg refresh_wait;
+
+
+	
+	assign issue_refresh_cmd = refresh_cmd;
+	assign go_next_refresh = (cmd_done_avl == 1'b0) && (refresh_wait == 1'b1);
+
+	always @(posedge avl_clk or negedge avl_reset_n)
+	begin
+		if (~avl_reset_n)
+		begin
+			rf_state <= STATE_RF_IDLE;
+			refi_counter <= '0;
+			refresh_cmd <= 1'b0;
+			refresh_wait <= 1'b0;
+			refresh_took_too_long <= 1'b0;
+
+		end
+		else
+		begin
+		
+			if (refresh_enabled)
+				refi_counter <= (rf_state == STATE_RF_REFRESH_0 || rf_state == STATE_RF_REFRESH_4)? '0 : refi_counter + 1;
+
+			if (refi_counter > REALLY_MAX_REFI_COUNT [16:0])
+				refresh_took_too_long <= 1'b1;  
+
+			if (    ((rf_state == STATE_RF_WAIT) & wait_done) |
+				((rf_state == STATE_RF_IDLE) & (start_refresh | state == STATE_RW_RESTORE)) |
+				(~refresh_wait & cmd_done_avl & (rf_state != STATE_RF_WAIT && rf_state != STATE_RF_IDLE  )) )
+			begin
+				rf_state <= next_rf_state;
+				refresh_cmd <= 1'b0;
+				refresh_wait <= 1'b1;
+			end
+			else if (rf_state != STATE_RF_WAIT & rf_state != STATE_RF_IDLE)
+			begin
+				if (~cmd_done_avl)
+					refresh_wait <= 1'b0;
+
+				if (~refresh_wait)
+					refresh_cmd <= 1'b1;
+			end
+
+		
+
+		
+
+
+		end		
+
+	end
+
+	reg [16:0] wait_cntr;
+	
+	always @(posedge avl_clk or negedge avl_reset_n)
+	begin
+		if (~avl_reset_n)
+			wait_cntr <= '0;
+		else
+		begin
+			if (rf_state == STATE_RF_WAIT)
+				wait_cntr <= wait_cntr + 1;
+			else
+				wait_cntr <= 0;
+		end	
+	end	
+
+	assign wait_done = (wait_cntr == WAIT_TIME);
+	
+	
+	wire [AVL_DATA_WIDTH-1:0] rank_mask;
+	assign rank_mask = (REFRESH_RANKS_SIMUL == 1)? '0 :  {'0, ~(7'h01 << rank_counter)};
+
+	always_comb
+	begin
+		case (rf_state)
+		STATE_RF_IDLE:
+			begin
+				avl_address_avl_refresh = '0;
+				avl_writedata_avl_refresh = '0;
+				next_rf_state = (state == STATE_RW_REFRESH & start_refresh)? STATE_RF_SET_MASK : (state == STATE_RW_RESTORE)? STATE_RF_RESTORE_0 : STATE_RF_IDLE;
+			end
+		STATE_RF_SET_MASK: 
+			begin
+				avl_address_avl_refresh  = {20'h00000 ,4'b0101, 8'h00};	
+				avl_writedata_avl_refresh = rank_mask; 
+				next_rf_state = STATE_RF_PRECHARGE;
+			end
+		STATE_RF_PRECHARGE: 
+			begin
+				avl_address_avl_refresh = 32'h0000;
+				avl_writedata_avl_refresh = 32'h12;
+				next_rf_state = STATE_RF_REFRESH_0;
+			end
+		STATE_RF_REFRESH_0: 
+			begin
+				avl_address_avl_refresh = 32'h0300;
+				avl_writedata_avl_refresh = 32'h14;  
+				next_rf_state = STATE_RF_REFRESH_1;
+			end
+		STATE_RF_REFRESH_1: 
+			begin
+				avl_address_avl_refresh = 32'h0301; 
+				avl_writedata_avl_refresh = 32'h0015; 
+				next_rf_state = STATE_RF_REFRESH_2;
+			end
+		STATE_RF_REFRESH_2: 
+			begin
+				avl_address_avl_refresh = 32'h0200;  
+				avl_writedata_avl_refresh = 32'h0007;  
+				next_rf_state = STATE_RF_REFRESH_3;
+			end
+		STATE_RF_REFRESH_3: 
+			begin	
+				avl_address_avl_refresh = 32'h0201;   
+				avl_writedata_avl_refresh = MAX_TRFC;  
+				next_rf_state = STATE_RF_REFRESH_4;
+			end
+		STATE_RF_REFRESH_4: 
+			begin
+				avl_address_avl_refresh = 32'h0000;  
+				avl_writedata_avl_refresh = 32'h14; 
+				next_rf_state = STATE_RF_WAIT;
+			end
+		STATE_RF_WAIT:
+			begin
+				avl_address_avl_refresh = 32'h0000;  
+				avl_writedata_avl_refresh = 32'd0; 
+				next_rf_state = STATE_RF_ACTIVATE_0;
+			end
+		STATE_RF_ACTIVATE_0:
+			begin
+				avl_address_avl_refresh = 32'h0200;  
+				avl_writedata_avl_refresh = 32'h00;   
+				next_rf_state = STATE_RF_ACTIVATE_1;
+			end
+		STATE_RF_ACTIVATE_1:
+			begin
+				avl_address_avl_refresh = 32'h0201;  
+				avl_writedata_avl_refresh = 32'h0F;
+				next_rf_state = STATE_RF_ACTIVATE_2;
+			end
+		STATE_RF_ACTIVATE_2:
+			begin
+				avl_address_avl_refresh = 32'h0300;
+				avl_writedata_avl_refresh = 32'h0E;
+				next_rf_state = STATE_RF_ACTIVATE_3;
+			end
+		STATE_RF_ACTIVATE_3:
+			begin
+				avl_address_avl_refresh = 32'h0301;
+				avl_writedata_avl_refresh = 32'h10;
+				next_rf_state = STATE_RF_ACTIVATE_4;
+			end
+		STATE_RF_ACTIVATE_4:
+			begin
+				avl_address_avl_refresh = 32'h0000;
+				avl_writedata_avl_refresh = 32'h0D;
+				next_rf_state = STATE_RF_IDLE;
+			end
+		STATE_RF_RESTORE_0:
+			begin
+				avl_address_avl_refresh = {20'h00000 ,4'b0101, 8'h00}; 
+				avl_writedata_avl_refresh = cs_mask_reg;  
+				next_rf_state = STATE_RF_RESTORE_1;
+			end
+		STATE_RF_RESTORE_1:
+			begin
+				avl_address_avl_refresh = 32'h0200;  
+				avl_writedata_avl_refresh = jump_cntr_0_reg;
+				next_rf_state = STATE_RF_RESTORE_2;
+			end
+		STATE_RF_RESTORE_2:
+			begin
+				avl_address_avl_refresh = 32'h0201;  
+				avl_writedata_avl_refresh = jump_cntr_1_reg;
+				next_rf_state = STATE_RF_RESTORE_3;
+			end
+		STATE_RF_RESTORE_3:
+			begin
+				avl_address_avl_refresh = 32'h0300;
+				avl_writedata_avl_refresh = jump_ptr_0_reg; 
+				next_rf_state = STATE_RF_RESTORE_4;
+			end
+		STATE_RF_RESTORE_4:
+			begin
+				avl_address_avl_refresh = 32'h0301;
+				avl_writedata_avl_refresh = jump_ptr_1_reg;
+				next_rf_state = STATE_RF_IDLE;
+			end
+		default:
+			begin
+				avl_address_avl_refresh = 32'h0000;  
+				avl_writedata_avl_refresh = 32'd0; 
+				next_rf_state = STATE_RF_IDLE;
+
+			end
+		endcase
+	end
+
+	assign refresh_done = (rf_state == STATE_RF_ACTIVATE_3);   
+	assign restore_done = (rf_state == STATE_RF_RESTORE_4) & cmd_done_avl & ~refresh_wait;  
+
+
+	always @(posedge avl_clk or negedge avl_reset_n) 
+	begin
+		if (~avl_reset_n)
+			rank_counter <= '0;
+		else 
+		begin
+			if (all_refresh_done | (REFRESH_RANKS_SIMUL == 1))
+				rank_counter <= '0;
+			else if (refresh_done & go_next_refresh)
+				rank_counter <= rank_counter + 1;
+		end	
+	end
+
+
+	assign all_refresh_done = ((rank_counter == MEM_NUMBER_OF_RANKS[2:0]) | (REFRESH_RANKS_SIMUL == 1)) & refresh_done;
+
+
+
+	reg [7:0] idle_wait;
+	localparam IDLE_WAIT_CNT= 32;
+	assign start_refresh = (idle_wait == IDLE_WAIT_CNT[7:0]) & have_avl_bus; 
+	
+
+	assign avl_writedata_avl_muxed = (have_avl_bus)? avl_writedata_avl_refresh : avl_writedata_avl; 
+	assign avl_address_avl_muxed = (have_avl_bus)? avl_address_avl_refresh : avl_address_avl;
+	assign cmd_read_muxed = (have_avl_bus)? 1'b0 : cmd_read;
+	assign cmd_write_muxed = (have_avl_bus)? issue_refresh_cmd : cmd_write;
+
+	
+	always @(posedge avl_clk or negedge avl_reset_n)
+	begin
+		if (~avl_reset_n)
+		begin
+			idle_wait <= '0;
+			req_avl_bus <= 1'b0;
+			have_avl_bus <= 1'b0;
+		end
+		else
+		begin
+			if (time_for_refresh)
+				req_avl_bus <= 1'b1;
+			else if (have_avl_bus)
+				req_avl_bus <= 1'b0;
+
+			if (req_avl_bus & state == STATE_RW_REFRESH)
+				have_avl_bus <= 1'b1;
+			else if (restore_done )
+				have_avl_bus <= 1'b0;
+
+			if (have_avl_bus & rf_state == STATE_RF_IDLE)
+				idle_wait <= idle_wait +1;
+			else
+				idle_wait <= '0;
+
+		end
+	end
+end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v
new file mode 100644
index 0000000..cc523c0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_inst_ROM_reg.v
@@ -0,0 +1,50 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+
+module rw_manager_inst_ROM_reg(
+        rdaddress,
+        clock,
+        data,
+        wraddress,
+        wren,
+        q);
+
+
+parameter INST_ROM_DATA_WIDTH = "";
+parameter INST_ROM_ADDRESS_WIDTH = "";
+
+input [(INST_ROM_ADDRESS_WIDTH-1):0]  rdaddress;
+input     clock;
+input [(INST_ROM_ADDRESS_WIDTH-1):0] wraddress;
+input [(INST_ROM_DATA_WIDTH-1):0] data;
+input wren; 
+output reg [(INST_ROM_DATA_WIDTH-1):0]  q;
+
+reg [(INST_ROM_DATA_WIDTH-1):0] inst_mem[(2**INST_ROM_ADDRESS_WIDTH-1):0];
+
+always @(posedge clock)
+
+begin
+  if (wren)
+  inst_mem[wraddress]<= data;
+  q <= inst_mem[rdaddress];
+
+end
+
+
+
+endmodule
+ 
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_jumplogic.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_jumplogic.v
new file mode 100644
index 0000000..97b6bf5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_jumplogic.v
@@ -0,0 +1,127 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_jumplogic(
+	ck,
+	reset_n,
+	cntr_value,
+	cntr_load,
+	reg_select,
+	reg_load_select,
+	jump_value,
+	jump_load,
+	jump_check,
+	jump_taken,
+	jump_address,
+	cntr_3,
+
+
+
+	jump_ptr_0_export, 	
+	jump_ptr_1_export, 
+	jump_cntr_0_export, 	
+	jump_cntr_1_export 
+
+);
+
+	parameter DATA_WIDTH = 8;
+
+	input ck;
+	input reset_n;
+	input [DATA_WIDTH-1:0] cntr_value;
+	input cntr_load;
+	input [1:0] reg_select;
+	input [1:0] reg_load_select;
+	input [DATA_WIDTH-1:0] jump_value;
+	input jump_load;
+	input jump_check;
+	output jump_taken;
+	output [DATA_WIDTH-1:0] jump_address;
+	output [DATA_WIDTH-1:0] cntr_3;
+
+
+	output	[7:0] jump_ptr_0_export; 	
+	output  [7:0] jump_ptr_1_export; 
+	output  [7:0] jump_cntr_0_export; 	
+	output  [7:0] jump_cntr_1_export;
+
+	reg [7:0] cntr [0:3];
+	reg [7:0] cntr_shadow [0:3];
+	reg [7:0] jump_pointers [0:3];
+
+	assign jump_ptr_0_export = jump_pointers [0];
+ 	assign jump_ptr_1_export = jump_pointers [1];
+	assign jump_cntr_0_export = cntr [0];
+ 	assign jump_cntr_1_export = cntr [1];
+
+	wire [3:0] comparisons;
+
+	assign jump_address = jump_pointers[reg_select];
+
+	assign jump_taken = (jump_check & ~comparisons[reg_select]);
+
+	assign cntr_3 = cntr[3];
+
+	genvar c;
+	generate
+		for(c = 0; c < 4; c = c + 1) 
+		begin : jumpcounter
+
+			assign comparisons[c] = (cntr[c] == {DATA_WIDTH{1'b0}});
+		
+			always @(posedge ck or negedge reset_n) begin
+				if(~reset_n) begin
+					cntr[c] <= {DATA_WIDTH{1'b0}};
+				end
+				else if (cntr_load && reg_load_select == c) begin
+					cntr[c] <= cntr_value;
+				end
+				else if (jump_check && reg_select == c) begin
+					cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
+				end
+			end
+		end
+	endgenerate
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			jump_pointers[0] <= {DATA_WIDTH{1'b0}};
+			jump_pointers[1] <= {DATA_WIDTH{1'b0}};
+			jump_pointers[2] <= {DATA_WIDTH{1'b0}};
+			jump_pointers[3] <= {DATA_WIDTH{1'b0}};
+
+			cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
+			cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
+			cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
+			cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
+		end
+		else begin
+			if(jump_load) begin
+				jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
+				jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
+				jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
+				jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
+			end
+
+			if(cntr_load) begin
+				cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
+				cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
+				cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
+				cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
+			end
+		end
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr12.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr12.v
new file mode 100644
index 0000000..5e0350f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr12.v
@@ -0,0 +1,48 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_lfsr12(
+	clk, 
+	nrst, 
+	ena, 
+	word
+);
+
+	input clk;
+	input nrst;
+	input ena;
+	output reg [11:0] word;
+
+	always @(posedge clk or negedge nrst) begin
+		if(~nrst) begin
+			word <= 12'b101001101011;
+		end
+		else if(ena) begin
+			word[11] <= word[0];
+			word[10] <= word[11];
+			word[9] <= word[10];
+			word[8] <= word[9];
+			word[7] <= word[8];
+			word[6] <= word[7];
+			word[5] <= word[6] ^ word[0];
+			word[4] <= word[5];
+			word[3] <= word[4] ^ word[0];
+			word[2] <= word[3];
+			word[1] <= word[2];
+			word[0] <= word[1] ^ word[0];
+		end
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr36.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr36.v
new file mode 100644
index 0000000..a674249
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr36.v
@@ -0,0 +1,72 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_lfsr36(
+	clk, 
+	nrst, 
+	ena, 
+	word
+);
+
+	input clk;
+	input nrst;
+	input ena;
+	output reg [35:0] word;
+
+	always @(posedge clk or negedge nrst) begin
+		if(~nrst) begin
+			word <= 36'hF0F0AA55;
+		end
+		else if(ena) begin
+			word[35] <= word[0];
+			word[34] <= word[35];
+			word[33] <= word[34];
+			word[32] <= word[33];
+			word[31] <= word[32];
+			word[30] <= word[31];
+			word[29] <= word[30];
+			word[28] <= word[29];
+			word[27] <= word[28];
+			word[26] <= word[27];
+			word[25] <= word[26];
+			word[24] <= word[25] ^ word[0];
+			word[23] <= word[24];
+			word[22] <= word[23];
+			word[21] <= word[22];
+			word[20] <= word[21];
+			word[19] <= word[20];
+			word[18] <= word[19];
+			word[17] <= word[18];
+			word[16] <= word[17];
+			word[15] <= word[16];
+			word[14] <= word[15];
+			word[13] <= word[14];
+			word[12] <= word[13];
+			word[11] <= word[12];
+			word[10] <= word[11];
+			word[9] <= word[10];
+			word[8] <= word[9];
+			word[7] <= word[8];
+			word[6] <= word[7];
+			word[5] <= word[6];
+			word[4] <= word[5];
+			word[3] <= word[4];
+			word[2] <= word[3];
+			word[1] <= word[2];
+			word[0] <= word[1];
+		end
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr72.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr72.v
new file mode 100644
index 0000000..8e82da5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_lfsr72.v
@@ -0,0 +1,44 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_lfsr72(
+	clk, 
+	nrst, 
+	ena, 
+	word
+);
+
+	input clk;
+	input nrst;
+	input ena;
+	output reg [71:0] word;
+
+	always @(posedge clk or negedge nrst) begin
+		if(~nrst) begin
+			word <= 72'hAAF0F0AA55F0F0AA55;
+		end
+		else if(ena) begin
+			word[71] <= word[0];
+			word[70:66] <= word[71:67];
+			word[65] <= word[66] ^ word[0];
+			word[64:25] <= word[65:26];
+			word[24] <= word[25] ^ word[0];
+			word[23:19] <= word[24:20];
+			word[18] <= word[19] ^ word[0];
+			word[17:0] <= word[18:1];
+		end
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v
new file mode 100644
index 0000000..89d7b9c
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_ac_ROM.v
@@ -0,0 +1,61 @@
+`timescale 1 ps / 1 ps
+module rw_manager_m10_ac_ROM (
+	clock,
+	rdaddress,
+	q);
+	
+	input	  clock;
+	input	[5:0]  rdaddress;
+	output	[31:0]  q;
+	
+	reg	[31:0]  q;
+	
+	reg	[5:0]  rdaddress_r;
+always @ (posedge clock)
+    rdaddress_r <=  rdaddress;
+	
+always @ (posedge clock)
+    case(rdaddress_r)
+'h00 : q <= 'h180E0000;
+'h01 : q <= 'h180F0000;
+'h02 : q <= 'h0C010211;
+'h03 : q <= 'h0C010310;
+'h04 : q <= 'h0C012000;
+'h05 : q <= 'h0C014000;
+'h06 : q <= 'h0C016000;
+'h07 : q <= 'h0C070400;
+'h08 : q <= 'h0C010209;
+'h09 : q <= 'h0C010288;
+'h0A : q <= 'h0C014000;
+'h0B : q <= 'h0C012000;
+'h0C : q <= 'h0C016000;
+'h0D : q <= 'h1C0F0000;
+'h0E : q <= 'h1E0F0000;
+'h0F : q <= 'h1C0F0000;
+'h10 : q <= 'h0C0D0000;
+'h11 : q <= 'h0C0D6000;
+'h12 : q <= 'h0C050400;
+'h13 : q <= 'h0C090000;
+'h14 : q <= 'h0F330000;
+'h15 : q <= 'h0F336000;
+'h16 : q <= 'h0F330008;
+'h17 : q <= 'h0F336008;
+'h18 : q <= 'h1E2F0000;
+'h19 : q <= 'h1F3F0000;
+'h1A : q <= 'h1E0F0000;
+'h1B : q <= 'h0E030000;
+'h1C : q <= 'h0E230000;
+'h1D : q <= 'h0CCB0000;
+'h1E : q <= 'h0CCB6000;
+'h1F : q <= 'h0CCB0008;
+'h20 : q <= 'h0CCB6008;
+'h21 : q <= 'h1CCF0000;
+'h22 : q <= 'h0C0B0008;
+'h23 : q <= 'h0C0F0000;
+'h24 : q <= 'h00000000;
+'h25 : q <= 'h00000000;
+'h26 : q <= 'h00000000;
+'h27 : q <= 'h00000000;
+        default : q <= 0;
+    endcase
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v
new file mode 100644
index 0000000..3f96463
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_m10_inst_ROM.v
@@ -0,0 +1,148 @@
+`timescale 1 ps / 1 ps
+module rw_manager_m10_inst_ROM (
+	clock,
+	rdaddress,
+	q);
+	
+	input	  clock;
+	input	[6:0]  rdaddress;
+	output	[19:0]  q;
+	
+	reg	[19:0]  q;
+	
+	wire	[6:0]  rdaddress_r;
+  assign  rdaddress_r =   rdaddress;
+	
+always @ (posedge clock)
+    case(rdaddress_r)
+'h00 : q <= 'h080000;
+'h01 : q <= 'h000780;
+'h02 : q <= 'h080680;
+'h03 : q <= 'h000180;
+'h04 : q <= 'h080680;
+'h05 : q <= 'h000200;
+'h06 : q <= 'h080680;
+'h07 : q <= 'h000280;
+'h08 : q <= 'h080680;
+'h09 : q <= 'h000300;
+'h0A : q <= 'h080680;
+'h0B : q <= 'h000380;
+'h0C : q <= 'h080680;
+'h0D : q <= 'h000100;
+'h0E : q <= 'h080680;
+'h0F : q <= 'h000800;
+'h10 : q <= 'h008680;
+'h11 : q <= 'h000880;
+'h12 : q <= 'h00A680;
+'h13 : q <= 'h080680;
+'h14 : q <= 'h000900;
+'h15 : q <= 'h080680;
+'h16 : q <= 'h000980;
+'h17 : q <= 'h008680;
+'h18 : q <= 'h080680;
+'h19 : q <= 'h000B68;
+'h1A : q <= 'h00CCE8;
+'h1B : q <= 'h000AE8;
+'h1C : q <= 'h008CE8;
+'h1D : q <= 'h000B88;
+'h1E : q <= 'h00EC88;
+'h1F : q <= 'h000A08;
+'h20 : q <= 'h00AC88;
+'h21 : q <= 'h080680;
+'h22 : q <= 'h00CE00;
+'h23 : q <= 'h00CD80;
+'h24 : q <= 'h00E700;
+'h25 : q <= 'h000C00;
+'h26 : q <= 'h020CE0;
+'h27 : q <= 'h020CE0;
+'h28 : q <= 'h000D00;
+'h29 : q <= 'h000680;
+'h2A : q <= 'h000680;
+'h2B : q <= 'h060E80;
+'h2C : q <= 'h061080;
+'h2D : q <= 'h00A680;
+'h2E : q <= 'h008680;
+'h2F : q <= 'h080680;
+'h30 : q <= 'h00CE00;
+'h31 : q <= 'h00CD80;
+'h32 : q <= 'h00E700;
+'h33 : q <= 'h000C00;
+'h34 : q <= 'h030CE0;
+'h35 : q <= 'h030CE0;
+'h36 : q <= 'h000D00;
+'h37 : q <= 'h000680;
+'h38 : q <= 'h000680;
+'h39 : q <= 'h070E80;
+'h3A : q <= 'h071080;
+'h3B : q <= 'h00A680;
+'h3C : q <= 'h008680;
+'h3D : q <= 'h080680;
+'h3E : q <= 'h001158;
+'h3F : q <= 'h0006D8;
+'h40 : q <= 'h080680;
+'h41 : q <= 'h040E88;
+'h42 : q <= 'h041088;
+'h43 : q <= 'h040F68;
+'h44 : q <= 'h0410E8;
+'h45 : q <= 'h00A680;
+'h46 : q <= 'h040FE8;
+'h47 : q <= 'h0410E8;
+'h48 : q <= 'h041008;
+'h49 : q <= 'h041088;
+'h4A : q <= 'h001100;
+'h4B : q <= 'h00C680;
+'h4C : q <= 'h008680;
+'h4D : q <= 'h00E680;
+'h4E : q <= 'h080680;
+'h4F : q <= 'h000000;
+'h50 : q <= 'h000000;
+'h51 : q <= 'h00A000;
+'h52 : q <= 'h008000;
+'h53 : q <= 'h080000;
+'h54 : q <= 'h000080;
+'h55 : q <= 'h000080;
+'h56 : q <= 'h000080;
+'h57 : q <= 'h000080;
+'h58 : q <= 'h00A080;
+'h59 : q <= 'h008080;
+'h5A : q <= 'h080080;
+'h5B : q <= 'h008680;
+'h5C : q <= 'h00A680;
+'h5D : q <= 'h080680;
+'h5E : q <= 'h040F08;
+'h5F : q <= 'h080680;
+'h60 : q <= 'h000000;
+'h61 : q <= 'h000000;
+'h62 : q <= 'h000000;
+'h63 : q <= 'h000000;
+'h64 : q <= 'h000000;
+'h65 : q <= 'h000000;
+'h66 : q <= 'h000000;
+'h67 : q <= 'h000000;
+'h68 : q <= 'h000000;
+'h69 : q <= 'h000000;
+'h6A : q <= 'h000000;
+'h6B : q <= 'h000000;
+'h6C : q <= 'h000000;
+'h6D : q <= 'h000000;
+'h6E : q <= 'h000000;
+'h6F : q <= 'h000000;
+'h70 : q <= 'h000000;
+'h71 : q <= 'h000000;
+'h72 : q <= 'h000000;
+'h73 : q <= 'h000000;
+'h74 : q <= 'h000000;
+'h75 : q <= 'h000000;
+'h76 : q <= 'h000000;
+'h77 : q <= 'h000000;
+'h78 : q <= 'h000000;
+'h79 : q <= 'h000000;
+'h7A : q <= 'h000000;
+'h7B : q <= 'h000000;
+'h7C : q <= 'h000000;
+'h7D : q <= 'h000000;
+'h7E : q <= 'h000000;
+'h7F : q <= 'h000000;
+        default : q <= 0;
+    endcase
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v
new file mode 100644
index 0000000..0fffc86
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_pattern_fifo.v
@@ -0,0 +1,95 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+
+
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rw_manager_pattern_fifo (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[4:0]  rdaddress;
+	input	[4:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Stratix IV",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 32,
+		altsyncram_component.numwords_b = 32,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "MLAB",
+		altsyncram_component.widthad_a = 5,
+		altsyncram_component.widthad_b = 5,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram.v
new file mode 100644
index 0000000..d071e32
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram.v
@@ -0,0 +1,56 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_ram
+
+(
+
+ data,
+ rdaddress, 
+ wraddress,
+ wren, clock,
+ q
+
+);
+
+parameter DATA_WIDTH=36;
+parameter ADDR_WIDTH=8;
+
+input [(DATA_WIDTH-1):0] data;
+input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
+input wren, clock;
+output reg [(DATA_WIDTH-1):0] q;
+
+
+	reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
+
+
+	always @ (posedge clock)
+
+	begin
+
+		if (wren)
+
+		ram[wraddress] <= data[DATA_WIDTH-1:0];
+
+		q <= ram[rdaddress];
+
+	end
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram_csr.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram_csr.v
new file mode 100644
index 0000000..5682fc9
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_ram_csr.v
@@ -0,0 +1,89 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_ram_csr #(
+   parameter DATA_WIDTH = 32,
+   parameter ADDR_WIDTH = 2,
+   parameter NUM_WORDS = 4
+) (
+   input                         csr_clk,       
+   input                         csr_ena,       
+   input                         csr_din,       
+
+   input                         ram_clk,       
+   input                         wren,          
+   input      [(DATA_WIDTH-1):0] data,          
+   input      [(ADDR_WIDTH-1):0] wraddress,     
+   input      [(ADDR_WIDTH-1):0] rdaddress,     
+
+   output reg [(DATA_WIDTH-1):0] q,             
+
+   output reg                    csr_dout       
+);
+
+
+localparam integer DATA_COUNT = DATA_WIDTH*NUM_WORDS;
+
+reg  [DATA_COUNT-1:0] all_data;
+wire [DATA_COUNT-1:0] load_data;
+wire [DATA_WIDTH-1:0] row_data [NUM_WORDS-1:0];
+
+wire int_clk;
+
+assign int_clk = (~csr_ena)? csr_clk : ram_clk;
+
+always @(posedge int_clk)
+begin
+   if (~csr_ena)
+      all_data <= {all_data[DATA_COUNT-2:0], csr_din};
+   else if (wren)
+      all_data <= load_data;
+   else
+      all_data <= all_data;
+
+   q <= row_data[rdaddress];
+end
+
+always @(negedge csr_clk)
+begin
+   csr_dout <= all_data[DATA_COUNT-1];
+end
+
+generate
+
+genvar i;
+
+
+   for (i = 0; i < (NUM_WORDS); i = i + 1)
+   begin: row_assign
+     assign row_data[i] = all_data[(DATA_WIDTH*(i+1)-1) : (DATA_WIDTH*i)];
+   end
+
+endgenerate
+
+generate
+
+genvar j,k;
+
+   for (j = 0; j < (NUM_WORDS); j = j + 1)
+   begin: row
+     for (k = 0; k < (DATA_WIDTH); k = k + 1)
+     begin: column
+        assign load_data[(DATA_WIDTH*j)+k] = (wraddress == j)? data[k] : all_data[(DATA_WIDTH*j)+k];
+     end
+   end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_read_datapath.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_read_datapath.v
new file mode 100644
index 0000000..8be377e
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_read_datapath.v
@@ -0,0 +1,158 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_read_datapath(
+	ck,
+	reset_n,
+	check_do,
+	check_dm,
+	check_do_lfsr,
+	check_dm_lfsr,
+	check_pattern_push,
+	clear_error,
+	read_data,
+	read_data_valid,
+	error_word,
+	enable_ap_mode
+);
+
+	parameter DATA_WIDTH 		= "";
+	parameter AFI_RATIO 		= "";
+
+	localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
+	localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
+
+	input ck;
+	input reset_n;
+
+	input [3:0] check_do;
+	input [2:0] check_dm;
+	input check_do_lfsr;
+	input check_dm_lfsr;
+	input check_pattern_push;
+	input enable_ap_mode;
+	input clear_error;
+
+	input [DATA_BUS_SIZE - 1 : 0] read_data;
+	input read_data_valid;
+
+	output [DATA_WIDTH - 1 : 0] error_word;
+
+	reg [4:0] pattern_radd;
+	reg [4:0] pattern_wadd;
+	wire [4:0] pattern_radd_next;
+
+	wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
+	wire [8:0] check_word_read;
+	wire [3:0] check_do_read = check_word_read[8:5];
+	wire [2:0] check_dm_read = check_word_read[4:2];
+	wire check_do_lfsr_read = check_word_read[1];
+	wire check_dm_lfsr_read = check_word_read[0];
+
+	wire [DATA_BUS_SIZE - 1 : 0] do_data;
+	wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
+
+	wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
+	wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
+
+
+	reg h_data_valid;
+	reg h_data_valid_r;
+	
+	
+	always @(posedge ck)
+	begin
+		if (~reset_n)	
+		begin
+			h_data_valid <= 1'b0;
+			h_data_valid_r <= 1'b0;
+		end
+		else
+		begin
+			if (h_data_valid)
+				h_data_valid <= 1'b0;
+			else if (read_data_valid & ~h_data_valid)
+				h_data_valid <= 1'b1;
+		
+			h_data_valid_r <= h_data_valid;
+	
+		end
+	end
+	
+	wire [DATA_BUS_SIZE - 1 : 0] h_do_data;
+	assign h_do_data = (h_data_valid_r & enable_ap_mode)? {DATA_BUS_SIZE {1'b0}} : do_data; 
+
+
+	rw_manager_bitcheck bitcheck_i(
+		.ck(ck),
+		.reset_n(reset_n),
+		.clear(clear_error),
+		.enable(read_data_valid),
+		.read_data(read_data),
+		.reference_data(h_do_data),
+		.mask(dm_data),
+		.error_word(error_word)
+	);
+	defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
+	defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
+
+	rw_manager_write_decoder write_decoder_i(
+		.ck(ck),
+		.reset_n(reset_n),
+		.do_lfsr(check_do_lfsr_read),
+		.dm_lfsr(check_dm_lfsr_read),
+		.do_lfsr_step(do_lfsr_step),
+		.dm_lfsr_step(dm_lfsr_step),
+		.do_code(check_do_read),
+		.dm_code(check_dm_read),
+		.do_data(do_data),
+		.dm_data(dm_data)
+	);
+	defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
+	defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
+
+	rw_manager_pattern_fifo pattern_fifo_i(
+		.clock(ck),
+		.data(check_word_write),
+		.rdaddress(pattern_radd_next),
+		.wraddress(pattern_wadd),
+		.wren(check_pattern_push),
+		.q(check_word_read)
+	);
+
+
+	assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			pattern_radd <= 5'b00000;
+			pattern_wadd <= 5'b00000;
+		end
+		else begin
+			if (clear_error) begin
+			    pattern_radd <= 5'b00000;
+			    pattern_wadd <= 5'b00000;
+			end else begin
+			    if(read_data_valid) begin
+				    pattern_radd <= pattern_radd + 1'b1;
+			    end
+			    if(check_pattern_push) begin
+				    pattern_wadd <= pattern_wadd + 1'b1;
+			    end
+			end
+		end
+	end
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_write_decoder.v b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_write_decoder.v
new file mode 100644
index 0000000..9e08d22
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/rw_manager_write_decoder.v
@@ -0,0 +1,112 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module rw_manager_write_decoder(
+	ck,
+	reset_n,
+	do_lfsr,
+	dm_lfsr,
+	do_lfsr_step,
+	dm_lfsr_step,
+	do_code,
+	dm_code,
+	do_data,
+	dm_data
+);
+
+	parameter DATA_WIDTH = "";
+	parameter AFI_RATIO	= "";
+
+	localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
+	localparam DO_LFSR_WIDTH = ((AFI_RATIO == 4) ? 72 : 36);
+
+	input ck;
+	input reset_n;
+	input do_lfsr;
+	input dm_lfsr;
+	input do_lfsr_step;
+	input dm_lfsr_step;
+	input [3:0] do_code;
+	input [2:0] dm_code;
+	output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_data;
+	output [NUMBER_OF_WORDS-1:0] dm_data;
+
+	reg do_lfsr_r;
+	reg dm_lfsr_r;
+
+	wire [DO_LFSR_WIDTH-1:0] do_lfsr_word;
+	wire [11:0] dm_lfsr_word;
+	wire [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_word;
+	wire [NUMBER_OF_WORDS -1 : 0] dm_word;
+
+	rw_manager_data_decoder DO_decoder(
+		.ck(ck),
+		.reset_n(reset_n),
+		.code(do_code),
+		.pattern(do_word)
+	);
+	defparam DO_decoder.DATA_WIDTH = DATA_WIDTH;
+	defparam DO_decoder.AFI_RATIO = AFI_RATIO;
+
+	rw_manager_dm_decoder DM_decoder_i(
+		.ck(ck),
+		.reset_n(reset_n),
+		.code(dm_code),
+		.pattern(dm_word)
+	);
+	defparam DM_decoder_i.AFI_RATIO = AFI_RATIO;
+
+	generate
+		begin
+			if (AFI_RATIO == 4) begin
+				rw_manager_lfsr72 do_lfsr_i(
+					.clk(ck),
+					.nrst(reset_n), 
+					.ena(do_lfsr_step), 
+					.word(do_lfsr_word)
+				);
+			end else begin
+				rw_manager_lfsr36 do_lfsr_i(
+					.clk(ck), 
+					.nrst(reset_n), 
+					.ena(do_lfsr_step), 
+					.word(do_lfsr_word)
+				);
+			end
+		end
+	endgenerate
+
+	rw_manager_lfsr12 dm_lfsr_i(
+		.clk(ck), 
+		.nrst(reset_n), 
+		.ena(dm_lfsr_step), 
+		.word(dm_lfsr_word)
+	);
+
+	always @(posedge ck or negedge reset_n) begin
+		if(~reset_n) begin
+			do_lfsr_r <= 1'b0;
+			dm_lfsr_r <= 1'b0;
+		end
+		else begin
+			do_lfsr_r <= do_lfsr;
+			dm_lfsr_r <= dm_lfsr;
+		end
+	end
+
+	assign do_data = (do_lfsr_r) ? do_lfsr_word[2 * DATA_WIDTH * AFI_RATIO - 1 : 0] : do_word;
+	assign dm_data = (dm_lfsr_r) ? dm_lfsr_word[NUMBER_OF_WORDS+1: 2] : dm_word;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo.v
new file mode 100644
index 0000000..616096b
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo.v
@@ -0,0 +1,139 @@
+//module sensor_algo
+//combine sensor_interface bkg_subtraction, cluster_locate, and calibration, and rms
+
+
+module sensor_algo(
+
+	//Clock/reset
+	input  wire        	clk_clk,                    //                     clk.clk
+	input  wire        	rst_reset,                  //                     rst.reset
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+	//Avalon ST transmitter
+	output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+	output wire        	data_out_endofpacket,   	//                        .endofpacket
+	output wire        	data_out_startofpacket, 	//                        .startofpacket
+	input  wire        	data_out_ready,         	//                        .ready
+	output wire        	data_out_valid,         	//                        .valid
+	output wire [1:0]  	data_out_empty,         	//                        .empty
+	//Sensor interface
+	input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+	output wire        	out_adc_clk,                //                        .out_dac_clk
+	output wire        	out_adc_cnv,                //                        .out_dac_cnv
+	input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+	output wire        	out_sensor_rst,             //                        .out_sensor_rst
+	output wire        	out_sensor_clk,             //                        .out_sensor_clk
+	output wire        	out_sensor_gain,            //                        .out_sensor_gain
+	//Serial synchro interface
+	input  wire	   		serial_rx,					//receive data
+	output wire	   		serial_tx,					//send data
+	input  wire [7:0]  	ext_input,					//SMA etc.
+	//Debug information
+	output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+	
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input	 wire				waitrequest
+	
+);
+	
+
+	wire [31:0] data_out_data1;   // Output data
+	wire data_out_endofpacket1;    // Output end-of-packet signal
+	wire data_out_startofpacket1;  // Output start-of-packet signal
+	wire data_out_ready1;         // Output ready signal
+	wire data_out_valid1;         // Output valid signal
+	wire [1:0] data_out_empty1;   // Output empty signal
+
+	wire int_rst;
+	wire [7:0] cluster_threshold;
+	wire [7:0] cluster_size;
+	wire [7:0] in_algo_threshold;
+
+	  
+
+	sensor_interface the_sensor_interface (
+		.clk_clk			(clk_clk),                //      clk.clk
+		.rst_reset			(rst_reset),              //      rst.reset
+		
+		.csr_address			(csr_address),            //      csr.address
+		.csr_write			(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read			(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		
+		.data_out_data			(data_out_data1),          // data_out.data
+		.data_out_empty			(data_out_empty1),         //         .empty
+		.data_out_endofpacket		(data_out_endofpacket1),   //         .endofpacket
+		.data_out_startofpacket		(data_out_startofpacket1),//         .startofpacket
+		.data_out_ready			(data_out_ready1),         //         .ready
+		.data_out_valid			(data_out_valid1),          //         .valid
+		
+		.in_trg 			(in_trg),                                //                  sensor.in_trg
+		.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+		.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+		.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+		.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+		.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+		.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+		.serial_rx			(serial_rx),		//receive data
+		.serial_tx			(serial_tx),		//send data
+		.ext_input			(ext_input),			//SMA etc.
+		
+		.int_rst          (int_rst),
+		.cluster_threshold		(cluster_threshold),
+		.cluster_size				(cluster_size),
+		.in_algo_threshold		(in_algo_threshold)
+		
+	);
+	
+	
+	algo_top_cl_cali_rms recon(
+	
+		.clk		(clk_clk),
+		.rst		(int_rst),
+		
+		.data_in_data		(data_out_data1),
+		.data_in_ready		(data_out_ready1),
+		.data_in_valid		(data_out_valid1),
+		.data_in_empty		(data_out_empty1),
+		.data_in_startofpacket		(data_out_startofpacket1),
+		.data_in_endofpacket			(data_out_endofpacket1),
+		
+				
+		.CL_THRESHOLD		(cluster_threshold),
+		.CL_SIZE				(cluster_size),
+		.IN_ALGO_THRESHOLD	(in_algo_threshold),
+		
+		.address		(address),
+		.clken		(clken),
+		.cali_fac	(cali_fac),
+		.waitrequest(waitrequest),
+		
+		.to_udp_data (data_out_data),           
+		.to_udp_ready(data_out_ready),          
+		.to_udp_valid (data_out_valid),          
+		.to_udp_empty (data_out_empty),          
+		.to_udp_endofpacket (data_out_endofpacket),    
+		.to_udp_startofpacket (data_out_startofpacket)		
+	);
+
+
+
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
new file mode 100644
index 0000000..db40835
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
@@ -0,0 +1,212 @@
+// sensor_algo_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 16,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 0,
+		parameter outUseEmptyPort = 1,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		output wire [15:0] out_0_data,          //    out_0.data
+		output wire        out_0_valid,         //         .valid
+		input  wire        out_0_ready,         //         .ready
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket,   //         .endofpacket
+		output wire        out_0_empty          //         .empty
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 16)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	sensor_algo_avalon_st_adapter_data_format_adapter_0 data_format_adapter_0 (
+		.clk               (in_clk_0_clk),        //   clk.clk
+		.reset_n           (~in_rst_0_reset),     // reset.reset_n
+		.in_data           (in_0_data),           //    in.data
+		.in_valid          (in_0_valid),          //      .valid
+		.in_ready          (in_0_ready),          //      .ready
+		.in_startofpacket  (in_0_startofpacket),  //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),    //      .endofpacket
+		.in_empty          (in_0_empty),          //      .empty
+		.out_data          (out_0_data),          //   out.data
+		.out_valid         (out_0_valid),         //      .valid
+		.out_ready         (out_0_ready),         //      .ready
+		.out_startofpacket (out_0_startofpacket), //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket),   //      .endofpacket
+		.out_empty         (out_0_empty)          //      .empty
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
new file mode 100644
index 0000000..fea4720
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
@@ -0,0 +1,227 @@
+// sensor_algo_avalon_st_adapter_001.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_avalon_st_adapter_001 #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 32,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 0,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 0,
+		parameter outUseReady     = 0,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		output wire [31:0] out_0_data,          //    out_0.data
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket    //         .endofpacket
+	);
+
+	wire         data_format_adapter_0_out_valid;         // data_format_adapter_0:out_valid -> timing_adapter_0:in_valid
+	wire  [31:0] data_format_adapter_0_out_data;          // data_format_adapter_0:out_data -> timing_adapter_0:in_data
+	wire         data_format_adapter_0_out_ready;         // timing_adapter_0:in_ready -> data_format_adapter_0:out_ready
+	wire         data_format_adapter_0_out_startofpacket; // data_format_adapter_0:out_startofpacket -> timing_adapter_0:in_startofpacket
+	wire         data_format_adapter_0_out_endofpacket;   // data_format_adapter_0:out_endofpacket -> timing_adapter_0:in_endofpacket
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	sensor_algo_avalon_st_adapter_001_data_format_adapter_0 data_format_adapter_0 (
+		.clk               (in_clk_0_clk),                            //   clk.clk
+		.reset_n           (~in_rst_0_reset),                         // reset.reset_n
+		.in_data           (in_0_data),                               //    in.data
+		.in_valid          (in_0_valid),                              //      .valid
+		.in_ready          (in_0_ready),                              //      .ready
+		.in_startofpacket  (in_0_startofpacket),                      //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),                        //      .endofpacket
+		.in_empty          (in_0_empty),                              //      .empty
+		.out_data          (data_format_adapter_0_out_data),          //   out.data
+		.out_valid         (data_format_adapter_0_out_valid),         //      .valid
+		.out_ready         (data_format_adapter_0_out_ready),         //      .ready
+		.out_startofpacket (data_format_adapter_0_out_startofpacket), //      .startofpacket
+		.out_endofpacket   (data_format_adapter_0_out_endofpacket)    //      .endofpacket
+	);
+
+	sensor_algo_avalon_st_adapter_001_timing_adapter_0 timing_adapter_0 (
+		.clk               (in_clk_0_clk),                            //   clk.clk
+		.reset_n           (~in_rst_0_reset),                         // reset.reset_n
+		.in_data           (data_format_adapter_0_out_data),          //    in.data
+		.in_valid          (data_format_adapter_0_out_valid),         //      .valid
+		.in_ready          (data_format_adapter_0_out_ready),         //      .ready
+		.in_startofpacket  (data_format_adapter_0_out_startofpacket), //      .startofpacket
+		.in_endofpacket    (data_format_adapter_0_out_endofpacket),   //      .endofpacket
+		.out_data          (out_0_data),                              //   out.data
+		.out_startofpacket (out_0_startofpacket),                     //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket)                        //      .endofpacket
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
new file mode 100644
index 0000000..66deb05
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
@@ -0,0 +1,99 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_data_format_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/21 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Data Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_001_data_format_adapter_0
+//   usePackets:         true
+//   hasInEmpty:         true
+//   inEmptyWidth:       2
+//   hasOutEmpty:        false 
+//   outEmptyWidth:      0
+//   inDataWidth:        32
+//   outDataWidth:       32
+//   channelWidth:       0
+//   inErrorWidth:       0
+//   outErrorWidth:      0
+//   inSymbolsPerBeat:   4
+//   outSymbolsPerBeat:  4
+//   maxState:           3
+//   stateWidth:         2
+//   maxChannel:         0
+//   symbolWidth:        8
+//   numMemSymbols:      3
+//   symbolWidth:        8
+
+
+// ------------------------------------------
+
+ 
+module sensor_algo_avalon_st_adapter_001_data_format_adapter_0 (
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1 : 0]    in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1 : 0] in_empty,
+ // Interface: out
+ input                out_ready,
+ output reg           out_valid,
+ output reg [32-1: 0]  out_data,
+ output reg           out_startofpacket,
+ output reg           out_endofpacket,
+
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+);
+
+
+   always @* begin
+      in_ready = out_ready; 
+      out_valid = in_valid;
+      out_data = in_data;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+   end
+
+endmodule
+
+   
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
new file mode 100644
index 0000000..402adf1
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_001_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      false
+//   in_use_valid:       true
+//   out_use_valid:      false
+//   use_packets:        true
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        0
+//   in_ready_latency:   0
+//   out_ready_latency:  0
+//   in_payload_width:   34
+//   out_payload_width:  34
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket
+// ------------------------------------------
+
+
+
+module sensor_algo_avalon_st_adapter_001_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ // Interface: out
+ output reg [32-1: 0] out_data,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg [34-1:0]   in_payload;
+   reg [34-1:0]   out_payload;
+   reg [1-1:0]   ready;   
+   reg            out_valid;
+   // synthesis translate_off
+   always @(negedge out_valid) begin
+      $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+   end
+   // synthesis translate_on
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket};
+     {out_data,out_startofpacket,out_endofpacket} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always_comb begin
+     ready[0] = 1;
+     out_valid = in_valid;
+     out_payload = in_payload;
+     in_ready    = ready[0];
+   end
+
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
new file mode 100644
index 0000000..ee7aadc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
@@ -0,0 +1,396 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_data_format_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/21 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Data Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_data_format_adapter_0
+//   usePackets:         true
+//   hasInEmpty:         true
+//   inEmptyWidth:       2
+//   hasOutEmpty:        true 
+//   outEmptyWidth:      1
+//   inDataWidth:        32
+//   outDataWidth:       16
+//   channelWidth:       0
+//   inErrorWidth:       0
+//   outErrorWidth:      0
+//   inSymbolsPerBeat:   4
+//   outSymbolsPerBeat:  2
+//   maxState:           3
+//   stateWidth:         2
+//   maxChannel:         0
+//   symbolWidth:        8
+//   numMemSymbols:      3
+//   symbolWidth:        8
+
+
+// ------------------------------------------
+
+ 
+module sensor_algo_avalon_st_adapter_data_format_adapter_0 (
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1 : 0]    in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1 : 0] in_empty,
+ // Interface: out
+ input                out_ready,
+ output reg           out_valid,
+ output reg [16-1: 0]  out_data,
+ output reg           out_startofpacket,
+ output reg           out_endofpacket,
+ output reg           out_empty,
+
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+);
+
+
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   reg         state_read_addr;
+   wire [2-1:0]   state_from_memory;
+   reg  [2-1:0]   state;
+   reg  [2-1:0]   new_state;
+   reg  [2-1:0]   state_d1;
+    
+   reg            in_ready_d1;
+   reg            mem_readaddr; 
+   reg            mem_readaddr_d1;
+   reg            a_ready;
+   reg            a_valid;
+   reg            a_channel;
+   reg [8-1:0]    a_data0; 
+   reg [8-1:0]    a_data1; 
+   reg [8-1:0]    a_data2; 
+   reg [8-1:0]    a_data3; 
+   reg            a_startofpacket;
+   reg            a_endofpacket;
+   reg  [2-1:0]   a_empty;
+   reg            a_error;
+   reg            b_ready;
+   reg            b_valid;
+   reg            b_channel;
+   reg  [16-1:0]   b_data;
+   reg            b_startofpacket; 
+   wire           b_startofpacket_wire; 
+   reg            b_endofpacket; 
+   reg  [1-1:0]   b_empty;
+   reg            b_error; 
+   reg            mem_write0;
+   reg  [8-1:0]   mem_writedata0;
+   wire [8-1:0]   mem_readdata0;
+   wire           mem_waitrequest0;
+   reg  [8-1:0]   mem0[0:0];
+   reg            mem_write1;
+   reg  [8-1:0]   mem_writedata1;
+   wire [8-1:0]   mem_readdata1;
+   wire           mem_waitrequest1;
+   reg  [8-1:0]   mem1[0:0];
+   reg            mem_write2;
+   reg  [8-1:0]   mem_writedata2;
+   wire [8-1:0]   mem_readdata2;
+   wire           mem_waitrequest2;
+   reg  [8-1:0]   mem2[0:0];
+   reg            sop_mem_writeenable;
+   reg            sop_mem_writedata;
+   wire           mem_waitrequest_sop; 
+
+   wire           state_waitrequest;
+   reg            state_waitrequest_d1; 
+
+   reg            in_channel = 0;
+   reg            out_channel;
+
+
+
+   reg in_error = 0;
+   reg out_error; 
+
+
+   reg  [2-1:0]   state_register;
+   reg            sop_register; 
+   reg            error_register;
+   reg  [8-1:0]   data0_register;
+   reg  [8-1:0]   data1_register;
+   reg  [8-1:0]   data2_register;
+
+   // ---------------------------------------------------------------------
+   //| Input Register Stage
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         a_valid   <= 0;
+         a_channel <= 0;
+         a_data0   <= 0;
+         a_data1   <= 0;
+         a_data2   <= 0;
+         a_data3   <= 0;
+         a_startofpacket <= 0;
+         a_endofpacket   <= 0;
+         a_empty <= 0; 
+         a_error <= 0;
+      end else begin
+         if (in_ready) begin
+            a_valid   <= in_valid;
+            a_channel <= in_channel;
+            a_error   <= in_error;
+            a_data0 <= in_data[31:24];
+            a_data1 <= in_data[23:16];
+            a_data2 <= in_data[15:8];
+            a_data3 <= in_data[7:0];
+            a_startofpacket <= in_startofpacket;
+            a_endofpacket   <= in_endofpacket;
+            a_empty         <= 0; 
+            if (in_endofpacket)
+               a_empty <= in_empty;
+         end
+      end 
+   end
+
+   always @* begin 
+      state_read_addr = a_channel;
+      if (in_ready)
+         state_read_addr = in_channel;
+   end
+   
+
+   // ---------------------------------------------------------------------
+   //| State & Memory Keepers
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         in_ready_d1          <= 0;
+         state_d1             <= 0;
+         mem_readaddr_d1      <= 0;
+         state_waitrequest_d1 <= 0;
+      end else begin
+         in_ready_d1          <= in_ready;
+         state_d1             <= state;
+         mem_readaddr_d1      <= mem_readaddr;
+         state_waitrequest_d1 <= state_waitrequest;
+      end
+   end
+   
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         state_register <= 0;
+         sop_register   <= 0;
+         data0_register <= 0;
+         data1_register <= 0;
+         data2_register <= 0;
+      end else begin
+         state_register <= new_state;
+         if (sop_mem_writeenable)
+            sop_register   <= sop_mem_writedata;
+         if (mem_write0)
+            data0_register <= mem_writedata0;
+         if (mem_write1)
+            data1_register <= mem_writedata1;
+         if (mem_write2)
+            data2_register <= mem_writedata2;
+         end
+      end
+   
+      assign state_from_memory = state_register;
+      assign b_startofpacket_wire = sop_register;
+      assign mem_readdata0 = data0_register;
+      assign mem_readdata1 = data1_register;
+      assign mem_readdata2 = data2_register;
+   
+   // ---------------------------------------------------------------------
+   //| State Machine
+   // ---------------------------------------------------------------------
+   always @* begin
+
+      
+   b_ready = (out_ready || ~out_valid);
+
+   a_ready   = 0;
+   b_data    = 0;
+   b_valid   = 0;
+   b_channel = a_channel;
+   b_error   = a_error;
+      
+   state = state_from_memory;
+      
+   new_state           = state;
+   mem_write0          = 0;
+   mem_writedata0      = a_data0;
+   mem_write1          = 0;
+   mem_writedata1      = a_data0;
+   mem_write2          = 0;
+   mem_writedata2      = a_data0;
+   sop_mem_writeenable = 0;
+
+   b_endofpacket = a_endofpacket;
+      
+   b_startofpacket = 0;
+      
+   b_endofpacket = 0;
+   b_empty = 0;
+       
+   case (state) 
+            0 : begin
+            b_data[15:8] = a_data0;
+            b_data[7:0] = a_data1;
+            b_startofpacket = a_startofpacket;
+            if (out_ready || ~out_valid) begin
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 2) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 2;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         1 : begin
+            b_data[15:8] = a_data2;
+            b_data[7:0] = a_data3;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+            a_ready = 1;
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 0) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 0;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         2 : begin
+            b_data[15:8] = a_data0;
+            b_data[7:0] = a_data1;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 2) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 2;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         3 : begin
+            b_data[15:8] = a_data2;
+            b_data[7:0] = a_data3;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+            a_ready = 1;
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = 0;
+                     if (a_endofpacket && (a_empty >= 0) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 0;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+
+   endcase
+
+      in_ready = (a_ready || ~a_valid);
+
+      mem_readaddr = in_channel; 
+      if (~in_ready)
+         mem_readaddr = mem_readaddr_d1;
+
+      
+      sop_mem_writedata = 0;
+      if (a_valid)
+         sop_mem_writedata = a_startofpacket;
+      if (b_ready && b_valid && b_startofpacket)
+         sop_mem_writeenable = 1;
+
+   end
+
+
+   // ---------------------------------------------------------------------
+   //| Output Register Stage
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         out_valid         <= 0;
+         out_data          <= 0;
+         out_channel       <= 0;
+         out_startofpacket <= 0;
+         out_endofpacket   <= 0;
+         out_empty         <= 0;
+         out_error         <= 0;
+      end else begin
+         if (out_ready || ~out_valid) begin
+            out_valid         <= b_valid;
+            out_data          <= b_data;
+            out_channel       <= b_channel; 
+            out_startofpacket <= b_startofpacket;
+            out_endofpacket   <= b_endofpacket;
+            out_empty         <= b_empty;
+            out_error         <= b_error;
+         end
+      end 
+   end
+   
+
+
+
+endmodule
+
+   
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
new file mode 100644
index 0000000..a9417a6
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
@@ -0,0 +1,360 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//  -----------------------------------------------------------------------------------
+// | Lookahead Multiport Memory
+//  -----------------------------------------------------------------------------------
+// | Module Name     : sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram
+// | Author          : kjo, dmunday
+// | Created On      : 2013 Nov 21
+// | Description     :
+// |   Standard multi-port memory, where a read on cycle n responds with data on 
+// |   cycle n+2.  The lookahead protection means that if you write data on cycle n or 
+// |   cycle n+1, the data returned on cycle n+2 is the written data.
+//  -----------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   memName:          sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram
+//   dataWidth:        8
+//   addrWidth:        1
+//   numReadPorts:     1
+//   depth:            1
+//   clrOnRST:         0 
+
+module sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram (
+  // Interface: clock
+  input                clk,
+  input                reset_n,
+  // Interface: read0 
+  input                rd0_address,
+  output reg [8 -1: 0] rd0_readdata,
+  // Interface: write
+  input                wr_address,
+  input      [8 -1: 0] wr_writedata,
+  input                wr_write,
+  output reg           wr_waitrequest                                                               
+);
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH           = 1;   
+   localparam  DATA_WIDTH      = 8;   
+   localparam  ADDRESS_WIDTH   = 1;   
+   localparam  CLEAR_ON_RESET  = 0;   
+
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [DATA_WIDTH-1:0]        wr_writedata1;
+   reg [ADDRESS_WIDTH-1:0]     reset_count;
+   reg [DATA_WIDTH-1:0]        mem_wr_writedata;
+   reg [ADDRESS_WIDTH-1:0]     mem_wr_address;
+   reg                         mem_wr_write;
+   reg [DATA_WIDTH-1:0]        mem [DEPTH-1:0];  
+   reg                         rd0_bypass;
+   reg [DATA_WIDTH-1:0]        rd0_mem_readdata;
+   
+   // ---------------------------------------------------------------------
+   // Synchronous Stuff
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         wr_writedata1  <= 0;
+         wr_waitrequest <= 1;
+         if (CLEAR_ON_RESET) begin
+            reset_count    <= DEPTH-1'b1;
+         end else begin
+            reset_count    <= 0;
+         end
+         rd0_bypass     <= 0;
+
+      end else begin
+         rd0_bypass   <= (rd0_address == wr_address) && wr_write;
+         wr_writedata1  <= wr_writedata;  
+  // Memory reset state machine
+         if (reset_count > 0) begin
+            reset_count <= reset_count - 1'b1;
+         end else begin
+            wr_waitrequest <= 0;
+         end
+      end
+   end
+   
+   // ---------------------------------------------------------------------
+   // Combinatorial Memory Control
+   // --------------------------------------------------------------------- 
+   always @* begin
+      rd0_readdata     = rd0_mem_readdata;
+      mem_wr_write     = wr_write;
+      mem_wr_address   = wr_address;
+      mem_wr_writedata = wr_writedata;
+      
+      // Lookahead
+      if (rd0_bypass) begin
+         rd0_readdata   = wr_writedata1;
+      end
+      // Memory Reset
+      if (CLEAR_ON_RESET) begin
+         if ( wr_waitrequest ) begin
+            mem_wr_write  = 1;
+            mem_wr_address = reset_count;
+            mem_wr_writedata    = 0;
+         end
+      end
+   end
+   
+   // --------------------------------------------------------------------- 
+   // Infer Memory
+   // --------------------------------------------------------------------- 
+   always @(posedge clk) begin
+      if (mem_wr_write)
+         mem[mem_wr_address] <= mem_wr_writedata;
+      rd0_mem_readdata       <= mem[rd0_address];
+   end
+   
+endmodule
+
+// synthesis translate_off
+
+//  --------------------------------------------------------------------------------
+// | test bench
+//  --------------------------------------------------------------------------------
+`ifdef RUN_INTERNAL_TEST
+module test_sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram;
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH                   = 1
+   localparam  DATA_WIDTH              = 8
+   localparam  ADDRESS_WIDTH           = 1
+   localparam  CLEAR_ON_RESET          = 0
+   localparam  CLOCK_HALF_PERIOD       = 10;
+   localparam  CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
+   localparam  RESET_TIME              = 25;
+   
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg                       clk            = 0;
+   reg                       reset_n        = 0;
+   reg                       test_success   = 1;
+   reg                       success        = 1;
+   reg [ADDRESS_WIDTH-1:0]   wr_address;
+   reg [DATA_WIDTH-1:0]      wr_writedata;
+   reg                       wr_write;
+   wire                      wr_waitrequest;
+   reg [ADDRESS_WIDTH-1:0]   rd0_address;
+   wire [DATA_WIDTH-1:0]     rd0_readdata;
+   reg [DATA_WIDTH-1:0]      mem_mirror [DEPTH-1:0];
+    
+   // ---------------------------------------------------------------------
+   //| DUT
+   // ---------------------------------------------------------------------
+   sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram dut ( 
+    .clk              (clk),
+    .reset_n          (reset_n),
+    .rd0_address      (rd0_address),
+    .rd0_readdata     (rd0_readdata),
+    .wr_address       (wr_address),
+    .wr_writedata     (wr_writedata),
+    .wr_write         (wr_write),
+    .wr_waitrequest   (wr_waitrequest)          
+   );
+
+   // ---------------------------------------------------------------------
+   //| Clock & Reset
+   // ---------------------------------------------------------------------
+   initial begin
+      reset_n = 0;
+      #RESET_TIME;
+      reset_n = 1;
+   end
+   
+   always begin
+      #CLOCK_HALF_PERIOD;
+      clk <= ~clk;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Main Test
+   // ---------------------------------------------------------------------
+   initial begin
+      test_reset();
+      test_random();
+      test_single_channel();
+      
+      $finish;
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Test reset
+   // ---------------------------------------------------------------------
+   task test_reset;
+      integer i;
+      begin
+       test_success = 1;
+
+        if (CLEAR_ON_RESET) begin
+            @(posedge clk);
+                test_assert ("Memory's wr_waitrequest should be test_asserted while held in reset.", wr_waitrequest);
+
+                    wait (reset_n == 1);
+                        test_assert ("Memory should still be in reset immediately after clearing the in_reset signal.", wr_waitrequest);
+
+                            wait (wr_waitrequest == 0);
+                                
+
+    for (i=0; i<DEPTH; i=i+1) begin
+       rd0_address <= i;
+       @(posedge clk);
+       test_assert ("Memory location should be 0.", rd0_readdata==0);
+    end
+ end else begin
+        @(posedge clk);
+        test_assert ("Memory's in_reset should be asserted while held in reset.", wr_waitrequest);
+        wait (reset_n == 1);
+        @(posedge clk);
+        #1 test_assert ("Memory should have in_reset=0 immediately after reset!!.", wr_waitrequest==0);
+     end // else: !if(CLEAR_ON_RESET)
+  endtest("test_reset");
+endtest 
+endtask
+
+   // ---------------------------------------------------------------------
+   //| Test random in & out data
+   // ---------------------------------------------------------------------
+   task test_random;
+      integer i;
+      begin
+
+
+       // Initialize mem_mirror
+        for (i=0; i<DEPTH; i=i+1) begin
+           if (CLEAR_ON_RESET) begin
+              mem_mirror[i] = 0;
+           end else begin
+              mem_mirror[i] = 256'bX;
+           end
+        end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         fork
+            begin
+               repeat (20*DEPTH) begin // do 20x Depth writes.
+                  #1;
+                  wr_write = $random % 2;
+                  wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  wr_writedata = $random;
+                  #1;
+                  if (wr_write)
+                    mem_mirror[wr_address] = wr_writedata;
+                  @(posedge clk);
+               end
+            end
+            
+            begin
+               repeat (80*DEPTH) begin // do 80x Depth reads.
+                  rd0_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  @(posedge clk);
+                  #1;
+                  test_assert("Data Mismatch (port 0)", mem_mirror[rd0_address] == rd0_readdata);
+               end
+            end
+         join
+         endtest("test_random");
+      end
+   endtask // test_random
+
+   // ---------------------------------------------------------------------
+   //| Test a single port
+   // ---------------------------------------------------------------------
+   task test_single_channel;
+      integer i;
+      begin
+
+         reset_n <= 0;
+         @(posedge clk);
+         reset_n <= 1;
+          
+          // Initialize mem_mirror
+         for (i=0; i<DEPTH; i=i+1) begin
+            if (CLEAR_ON_RESET) begin
+               mem_mirror[i] = 0;
+            end else begin
+               mem_mirror[i] = 256'bX;
+            end
+         end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         wr_write  = 0;
+         wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+         rd0_address  = wr_address;
+         
+         repeat (200) begin // do 200 times
+            wr_write  = ($random & 1'b1);
+            wr_writedata    = $dist_uniform(23,0,256);
+            #1;
+            mem_mirror[wr_address] = wr_writedata;
+            @(posedge clk);
+            #1;
+            test_assert("Data Mismatch", mem_mirror[rd0_address] == rd0_readdata);
+         end
+         endtest("test_single_channel");
+      end
+   endtask // test_random
+   
+   
+   // ---------------------------------------------------------------------
+   //| Test_assert
+   // ---------------------------------------------------------------------
+   task test_assert;
+      input [256:0] message;
+      input         condition;
+      begin
+       if (! condition) begin
+          $display("%t: %s ",$time, message);
+          success = 0;
+          test_success = 0;
+       end
+      end
+   endtask
+
+   // ---------------------------------------------------------------------
+   //| End Test
+   // ---------------------------------------------------------------------
+   task endtest;
+      input [256:0] message;
+      begin
+         if (test_success) begin
+            $display("(sim)%t: %-40s: Pass",$time, message);
+         end else begin
+            $display("(sim)%t: %-40s: Fail",$time, message);
+         end
+         success = success & test_success;
+      end
+   endtask
+
+endmodule
+`endif
+// synthesis translate_on
+
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
new file mode 100644
index 0000000..bb63968
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
@@ -0,0 +1,360 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//  -----------------------------------------------------------------------------------
+// | Lookahead Multiport Memory
+//  -----------------------------------------------------------------------------------
+// | Module Name     : sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram
+// | Author          : kjo, dmunday
+// | Created On      : 2013 Nov 21
+// | Description     :
+// |   Standard multi-port memory, where a read on cycle n responds with data on 
+// |   cycle n+2.  The lookahead protection means that if you write data on cycle n or 
+// |   cycle n+1, the data returned on cycle n+2 is the written data.
+//  -----------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   memName:          sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram
+//   dataWidth:        2
+//   addrWidth:        1
+//   numReadPorts:     1
+//   depth:            1
+//   clrOnRST:         1 
+
+module sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram (
+  // Interface: clock
+  input                clk,
+  input                reset_n,
+  // Interface: read0 
+  input                rd0_address,
+  output reg [2 -1: 0] rd0_readdata,
+  // Interface: write
+  input                wr_address,
+  input      [2 -1: 0] wr_writedata,
+  input                wr_write,
+  output reg           wr_waitrequest                                                               
+);
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH           = 1;   
+   localparam  DATA_WIDTH      = 2;   
+   localparam  ADDRESS_WIDTH   = 1;   
+   localparam  CLEAR_ON_RESET  = 1;   
+
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [DATA_WIDTH-1:0]        wr_writedata1;
+   reg [ADDRESS_WIDTH-1:0]     reset_count;
+   reg [DATA_WIDTH-1:0]        mem_wr_writedata;
+   reg [ADDRESS_WIDTH-1:0]     mem_wr_address;
+   reg                         mem_wr_write;
+   reg [DATA_WIDTH-1:0]        mem [DEPTH-1:0];  
+   reg                         rd0_bypass;
+   reg [DATA_WIDTH-1:0]        rd0_mem_readdata;
+   
+   // ---------------------------------------------------------------------
+   // Synchronous Stuff
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         wr_writedata1  <= 0;
+         wr_waitrequest <= 1;
+         if (CLEAR_ON_RESET) begin
+            reset_count    <= DEPTH-1'b1;
+         end else begin
+            reset_count    <= 0;
+         end
+         rd0_bypass     <= 0;
+
+      end else begin
+         rd0_bypass   <= (rd0_address == wr_address) && wr_write;
+         wr_writedata1  <= wr_writedata;  
+  // Memory reset state machine
+         if (reset_count > 0) begin
+            reset_count <= reset_count - 1'b1;
+         end else begin
+            wr_waitrequest <= 0;
+         end
+      end
+   end
+   
+   // ---------------------------------------------------------------------
+   // Combinatorial Memory Control
+   // --------------------------------------------------------------------- 
+   always @* begin
+      rd0_readdata     = rd0_mem_readdata;
+      mem_wr_write     = wr_write;
+      mem_wr_address   = wr_address;
+      mem_wr_writedata = wr_writedata;
+      
+      // Lookahead
+      if (rd0_bypass) begin
+         rd0_readdata   = wr_writedata1;
+      end
+      // Memory Reset
+      if (CLEAR_ON_RESET) begin
+         if ( wr_waitrequest ) begin
+            mem_wr_write  = 1;
+            mem_wr_address = reset_count;
+            mem_wr_writedata    = 0;
+         end
+      end
+   end
+   
+   // --------------------------------------------------------------------- 
+   // Infer Memory
+   // --------------------------------------------------------------------- 
+   always @(posedge clk) begin
+      if (mem_wr_write)
+         mem[mem_wr_address] <= mem_wr_writedata;
+      rd0_mem_readdata       <= mem[rd0_address];
+   end
+   
+endmodule
+
+// synthesis translate_off
+
+//  --------------------------------------------------------------------------------
+// | test bench
+//  --------------------------------------------------------------------------------
+`ifdef RUN_INTERNAL_TEST
+module test_sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram;
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH                   = 1
+   localparam  DATA_WIDTH              = 2
+   localparam  ADDRESS_WIDTH           = 1
+   localparam  CLEAR_ON_RESET          = 1
+   localparam  CLOCK_HALF_PERIOD       = 10;
+   localparam  CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
+   localparam  RESET_TIME              = 25;
+   
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg                       clk            = 0;
+   reg                       reset_n        = 0;
+   reg                       test_success   = 1;
+   reg                       success        = 1;
+   reg [ADDRESS_WIDTH-1:0]   wr_address;
+   reg [DATA_WIDTH-1:0]      wr_writedata;
+   reg                       wr_write;
+   wire                      wr_waitrequest;
+   reg [ADDRESS_WIDTH-1:0]   rd0_address;
+   wire [DATA_WIDTH-1:0]     rd0_readdata;
+   reg [DATA_WIDTH-1:0]      mem_mirror [DEPTH-1:0];
+    
+   // ---------------------------------------------------------------------
+   //| DUT
+   // ---------------------------------------------------------------------
+   sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram dut ( 
+    .clk              (clk),
+    .reset_n          (reset_n),
+    .rd0_address      (rd0_address),
+    .rd0_readdata     (rd0_readdata),
+    .wr_address       (wr_address),
+    .wr_writedata     (wr_writedata),
+    .wr_write         (wr_write),
+    .wr_waitrequest   (wr_waitrequest)          
+   );
+
+   // ---------------------------------------------------------------------
+   //| Clock & Reset
+   // ---------------------------------------------------------------------
+   initial begin
+      reset_n = 0;
+      #RESET_TIME;
+      reset_n = 1;
+   end
+   
+   always begin
+      #CLOCK_HALF_PERIOD;
+      clk <= ~clk;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Main Test
+   // ---------------------------------------------------------------------
+   initial begin
+      test_reset();
+      test_random();
+      test_single_channel();
+      
+      $finish;
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Test reset
+   // ---------------------------------------------------------------------
+   task test_reset;
+      integer i;
+      begin
+       test_success = 1;
+
+        if (CLEAR_ON_RESET) begin
+            @(posedge clk);
+                test_assert ("Memory's wr_waitrequest should be test_asserted while held in reset.", wr_waitrequest);
+
+                    wait (reset_n == 1);
+                        test_assert ("Memory should still be in reset immediately after clearing the in_reset signal.", wr_waitrequest);
+
+                            wait (wr_waitrequest == 0);
+                                
+
+    for (i=0; i<DEPTH; i=i+1) begin
+       rd0_address <= i;
+       @(posedge clk);
+       test_assert ("Memory location should be 0.", rd0_readdata==0);
+    end
+ end else begin
+        @(posedge clk);
+        test_assert ("Memory's in_reset should be asserted while held in reset.", wr_waitrequest);
+        wait (reset_n == 1);
+        @(posedge clk);
+        #1 test_assert ("Memory should have in_reset=0 immediately after reset!!.", wr_waitrequest==0);
+     end // else: !if(CLEAR_ON_RESET)
+  endtest("test_reset");
+endtest 
+endtask
+
+   // ---------------------------------------------------------------------
+   //| Test random in & out data
+   // ---------------------------------------------------------------------
+   task test_random;
+      integer i;
+      begin
+
+
+       // Initialize mem_mirror
+        for (i=0; i<DEPTH; i=i+1) begin
+           if (CLEAR_ON_RESET) begin
+              mem_mirror[i] = 0;
+           end else begin
+              mem_mirror[i] = 256'bX;
+           end
+        end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         fork
+            begin
+               repeat (20*DEPTH) begin // do 20x Depth writes.
+                  #1;
+                  wr_write = $random % 2;
+                  wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  wr_writedata = $random;
+                  #1;
+                  if (wr_write)
+                    mem_mirror[wr_address] = wr_writedata;
+                  @(posedge clk);
+               end
+            end
+            
+            begin
+               repeat (80*DEPTH) begin // do 80x Depth reads.
+                  rd0_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  @(posedge clk);
+                  #1;
+                  test_assert("Data Mismatch (port 0)", mem_mirror[rd0_address] == rd0_readdata);
+               end
+            end
+         join
+         endtest("test_random");
+      end
+   endtask // test_random
+
+   // ---------------------------------------------------------------------
+   //| Test a single port
+   // ---------------------------------------------------------------------
+   task test_single_channel;
+      integer i;
+      begin
+
+         reset_n <= 0;
+         @(posedge clk);
+         reset_n <= 1;
+          
+          // Initialize mem_mirror
+         for (i=0; i<DEPTH; i=i+1) begin
+            if (CLEAR_ON_RESET) begin
+               mem_mirror[i] = 0;
+            end else begin
+               mem_mirror[i] = 256'bX;
+            end
+         end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         wr_write  = 0;
+         wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+         rd0_address  = wr_address;
+         
+         repeat (200) begin // do 200 times
+            wr_write  = ($random & 1'b1);
+            wr_writedata    = $dist_uniform(23,0,256);
+            #1;
+            mem_mirror[wr_address] = wr_writedata;
+            @(posedge clk);
+            #1;
+            test_assert("Data Mismatch", mem_mirror[rd0_address] == rd0_readdata);
+         end
+         endtest("test_single_channel");
+      end
+   endtask // test_random
+   
+   
+   // ---------------------------------------------------------------------
+   //| Test_assert
+   // ---------------------------------------------------------------------
+   task test_assert;
+      input [256:0] message;
+      input         condition;
+      begin
+       if (! condition) begin
+          $display("%t: %s ",$time, message);
+          success = 0;
+          test_success = 0;
+       end
+      end
+   endtask
+
+   // ---------------------------------------------------------------------
+   //| End Test
+   // ---------------------------------------------------------------------
+   task endtest;
+      input [256:0] message;
+      begin
+         if (test_success) begin
+            $display("(sim)%t: %-40s: Pass",$time, message);
+         end else begin
+            $display("(sim)%t: %-40s: Fail",$time, message);
+         end
+         success = success & test_success;
+      end
+   endtask
+
+endmodule
+`endif
+// synthesis translate_on
+
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
new file mode 100644
index 0000000..df635cf
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      false
+//   in_use_valid:       true
+//   out_use_valid:      false
+//   use_packets:        true
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        0
+//   in_ready_latency:   0
+//   out_ready_latency:  0
+//   in_payload_width:   34
+//   out_payload_width:  34
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket
+// ------------------------------------------
+
+
+
+module sensor_algo_avalon_st_adapter_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ // Interface: out
+ output reg [32-1: 0] out_data,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg [34-1:0]   in_payload;
+   reg [34-1:0]   out_payload;
+   reg [1-1:0]   ready;   
+   reg            out_valid;
+   // synthesis translate_off
+   always @(negedge out_valid) begin
+      $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+   end
+   // synthesis translate_on
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket};
+     {out_data,out_startofpacket,out_endofpacket} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always_comb begin
+     ready[0] = 1;
+     out_valid = in_valid;
+     out_payload = in_payload;
+     in_ready    = ready[0];
+   end
+
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_cali_fac.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
new file mode 100644
index 0000000..942da48
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module sensor_algo_cali_fac (
+                              // inputs:
+                               address,
+                               address2,
+                               byteenable,
+                               byteenable2,
+                               chipselect,
+                               chipselect2,
+                               clk,
+                               clk2,
+                               clken,
+                               clken2,
+                               freeze,
+                               reset,
+                               reset2,
+                               reset_req,
+                               reset_req2,
+                               write,
+                               write2,
+                               writedata,
+                               writedata2,
+
+                              // outputs:
+                               readdata,
+                               readdata2
+                            )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  7: 0] address;
+  input   [  7: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 160,
+           the_altsyncram.numwords_a = 160,
+           the_altsyncram.numwords_b = 160,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 8,
+           the_altsyncram.widthad_b = 8,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_calibration.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_calibration.v
new file mode 100644
index 0000000..ccf8a59
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_calibration.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module sensor_algo_calibration (
+                                 // inputs:
+                                  address,
+                                  address2,
+                                  byteenable,
+                                  byteenable2,
+                                  chipselect,
+                                  chipselect2,
+                                  clk,
+                                  clk2,
+                                  clken,
+                                  clken2,
+                                  freeze,
+                                  reset,
+                                  reset2,
+                                  reset_req,
+                                  reset_req2,
+                                  write,
+                                  write2,
+                                  writedata,
+                                  writedata2,
+
+                                 // outputs:
+                                  readdata,
+                                  readdata2
+                               )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  7: 0] address;
+  input   [  7: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 160,
+           the_altsyncram.numwords_a = 160,
+           the_altsyncram.numwords_b = 160,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 8,
+           the_altsyncram.widthad_b = 8,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
new file mode 100644
index 0000000..903c0aa
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
@@ -0,0 +1,163 @@
+// sensor_algo_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_mm_interconnect_0 (
+		input  wire        sys_clk_clk_clk,                           //                         sys_clk_clk.clk
+		input  wire        ST2MM_0_reset_reset_bridge_in_reset_reset, // ST2MM_0_reset_reset_bridge_in_reset.reset
+		input  wire [8:0]  ST2MM_0_avalon_master_address,             //               ST2MM_0_avalon_master.address
+		output wire        ST2MM_0_avalon_master_waitrequest,         //                                    .waitrequest
+		input  wire        ST2MM_0_avalon_master_chipselect,          //                                    .chipselect
+		output wire [15:0] ST2MM_0_avalon_master_readdata,            //                                    .readdata
+		input  wire        ST2MM_0_avalon_master_write,               //                                    .write
+		input  wire [15:0] ST2MM_0_avalon_master_writedata,           //                                    .writedata
+		output wire [7:0]  calibration_s1_address,                    //                      calibration_s1.address
+		output wire        calibration_s1_write,                      //                                    .write
+		input  wire [15:0] calibration_s1_readdata,                   //                                    .readdata
+		output wire [15:0] calibration_s1_writedata,                  //                                    .writedata
+		output wire [1:0]  calibration_s1_byteenable,                 //                                    .byteenable
+		output wire        calibration_s1_chipselect,                 //                                    .chipselect
+		output wire        calibration_s1_clken                       //                                    .clken
+	);
+
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest;   // calibration_s1_translator:uav_waitrequest -> ST2MM_0_avalon_master_translator:uav_waitrequest
+	wire  [15:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata;      // calibration_s1_translator:uav_readdata -> ST2MM_0_avalon_master_translator:uav_readdata
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess;   // ST2MM_0_avalon_master_translator:uav_debugaccess -> calibration_s1_translator:uav_debugaccess
+	wire   [8:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_address;       // ST2MM_0_avalon_master_translator:uav_address -> calibration_s1_translator:uav_address
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_read;          // ST2MM_0_avalon_master_translator:uav_read -> calibration_s1_translator:uav_read
+	wire   [1:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable;    // ST2MM_0_avalon_master_translator:uav_byteenable -> calibration_s1_translator:uav_byteenable
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // calibration_s1_translator:uav_readdatavalid -> ST2MM_0_avalon_master_translator:uav_readdatavalid
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_lock;          // ST2MM_0_avalon_master_translator:uav_lock -> calibration_s1_translator:uav_lock
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_write;         // ST2MM_0_avalon_master_translator:uav_write -> calibration_s1_translator:uav_write
+	wire  [15:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata;     // ST2MM_0_avalon_master_translator:uav_writedata -> calibration_s1_translator:uav_writedata
+	wire   [1:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount;    // ST2MM_0_avalon_master_translator:uav_burstcount -> calibration_s1_translator:uav_burstcount
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (9),
+		.AV_DATA_W                   (16),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (2),
+		.UAV_ADDRESS_W               (9),
+		.UAV_BURSTCOUNT_W            (2),
+		.USE_READ                    (0),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (1),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (2),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) st2mm_0_avalon_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                          //                       clk.clk
+		.reset                  (ST2MM_0_reset_reset_bridge_in_reset_reset),                                //                     reset.reset
+		.uav_address            (st2mm_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (st2mm_0_avalon_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (st2mm_0_avalon_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (st2mm_0_avalon_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (ST2MM_0_avalon_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (ST2MM_0_avalon_master_waitrequest),                                        //                          .waitrequest
+		.av_chipselect          (ST2MM_0_avalon_master_chipselect),                                         //                          .chipselect
+		.av_readdata            (ST2MM_0_avalon_master_readdata),                                           //                          .readdata
+		.av_write               (ST2MM_0_avalon_master_write),                                              //                          .write
+		.av_writedata           (ST2MM_0_avalon_master_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                     //               (terminated)
+		.av_byteenable          (2'b11),                                                                    //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                     //               (terminated)
+		.av_begintransfer       (1'b0),                                                                     //               (terminated)
+		.av_read                (1'b0),                                                                     //               (terminated)
+		.av_readdatavalid       (),                                                                         //               (terminated)
+		.av_lock                (1'b0),                                                                     //               (terminated)
+		.av_debugaccess         (1'b0),                                                                     //               (terminated)
+		.uav_clken              (),                                                                         //               (terminated)
+		.av_clken               (1'b1),                                                                     //               (terminated)
+		.uav_response           (2'b00),                                                                    //               (terminated)
+		.av_response            (),                                                                         //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                     //               (terminated)
+		.av_writeresponsevalid  ()                                                                          //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (8),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (16),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (2),
+		.UAV_BYTEENABLE_W               (2),
+		.UAV_ADDRESS_W                  (9),
+		.UAV_BURSTCOUNT_W               (2),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (2),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) calibration_s1_translator (
+		.clk                    (sys_clk_clk_clk),                                                          //                      clk.clk
+		.reset                  (ST2MM_0_reset_reset_bridge_in_reset_reset),                                //                    reset.reset
+		.uav_address            (st2mm_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
+		.uav_read               (st2mm_0_avalon_master_translator_avalon_universal_master_0_read),          //                         .read
+		.uav_write              (st2mm_0_avalon_master_translator_avalon_universal_master_0_write),         //                         .write
+		.uav_waitrequest        (st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
+		.uav_readdata           (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                         .readdata
+		.uav_writedata          (st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                         .writedata
+		.uav_lock               (st2mm_0_avalon_master_translator_avalon_universal_master_0_lock),          //                         .lock
+		.uav_debugaccess        (st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
+		.av_address             (calibration_s1_address),                                                   //      avalon_anti_slave_0.address
+		.av_write               (calibration_s1_write),                                                     //                         .write
+		.av_readdata            (calibration_s1_readdata),                                                  //                         .readdata
+		.av_writedata           (calibration_s1_writedata),                                                 //                         .writedata
+		.av_byteenable          (calibration_s1_byteenable),                                                //                         .byteenable
+		.av_chipselect          (calibration_s1_chipselect),                                                //                         .chipselect
+		.av_clken               (calibration_s1_clken),                                                     //                         .clken
+		.av_read                (),                                                                         //              (terminated)
+		.av_begintransfer       (),                                                                         //              (terminated)
+		.av_beginbursttransfer  (),                                                                         //              (terminated)
+		.av_burstcount          (),                                                                         //              (terminated)
+		.av_readdatavalid       (1'b0),                                                                     //              (terminated)
+		.av_waitrequest         (1'b0),                                                                     //              (terminated)
+		.av_writebyteenable     (),                                                                         //              (terminated)
+		.av_lock                (),                                                                         //              (terminated)
+		.uav_clken              (1'b0),                                                                     //              (terminated)
+		.av_debugaccess         (),                                                                         //              (terminated)
+		.av_outputenable        (),                                                                         //              (terminated)
+		.uav_response           (),                                                                         //              (terminated)
+		.av_response            (2'b00),                                                                    //              (terminated)
+		.uav_writeresponsevalid (),                                                                         //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                                      //              (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_interface.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_interface.v
new file mode 100644
index 0000000..66f9722
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_interface.v
@@ -0,0 +1,784 @@
+// sensor_interface.v
+
+
+
+`timescale 1 ps / 1 ps
+module sensor_interface (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		//Avalon MM slave
+        input  wire [1:0]  	csr_address,                //            avalon_slave.address
+        input  wire        	csr_read,                   //                        .read
+        output wire [31:0] 	csr_readdata,               //                        .readdata
+        input  wire        	csr_write,                  //                        .write
+        input  wire [31:0] 	csr_writedata,              //                        .writedata
+        input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty,         	//                        .empty
+		//Sensor interface
+        input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+        output wire        	out_adc_clk,                //                        .out_dac_clk
+        output wire        	out_adc_cnv,                //                        .out_dac_cnv
+        input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+        output wire        	out_sensor_rst,             //                        .out_sensor_rst
+        output wire        	out_sensor_clk,             //                        .out_sensor_clk
+        output wire        	out_sensor_gain,            //                        .out_sensor_gain
+			//Serial synchro interface
+			input  wire	   		serial_rx,					//receive data
+			output wire	   		serial_tx,					//send data
+			input  wire [7:0]  	ext_input,					//SMA etc.
+			//Debug information
+			output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+			
+			output reg 				int_rst,						//the reset for each new run 
+			output reg	[7:0]		cluster_threshold,		//from registers[3][7:0] 
+			output reg	[7:0]		cluster_size,				//from registers[3][15:8]
+			output reg  [7:0]		in_algo_threshold			//from registers[3][23:16]
+    );
+	
+
+		//Very important globals
+	reg[31:0] 	transmit_buffer[162:0];		//Data to send: 3 words header plus sensor data
+	wire 		readout_ready;				//pulsing this signal causes copying data from frame buffer to transmit buffer and initiating transmission
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[15:0]	local_sync_ctr;				//local synchronization counter, it increments by one at each frame
+	wire[8:0]	global_sync_ctr;			//global synchronization counter, it's simply the received value from serial RX.
+	wire		global_sync_error;			//RX error in the global synchronization counter
+
+		//Common generate variables
+	genvar i;	//for generate loops
+	genvar j;
+	integer xi;	//for normal loops
+	integer xj;
+
+	// *********************** CSR stuff ************************
+	/*
+		There are 4 32-bit R/W-able registers. They are used for setting up the module and checking its state
+		Reg0 is a bit different: when read, bits 15-8 (the status byte) are taken directly from device internals, not from register contents.
+		The bus can be accessed 32-, 16- or 8-bit-wise.
+
+		Register definition
+		//reg0
+		#define SENSOR_REG_COMMAND		0	//8 bits
+		#define SENSOR_REG_STATUS		1	//8 bits
+		#define SENSOR_REG_SENSORCLK	2	//8 bits, 6 used	divider for producing sensor clock ('4' MHz)
+		#define SESNOR_REG_ADCCNV		3	//8 bits, 6 used	time of conversion pulse in ADC clocks, should be > 500 ns
+		//reg1		
+		#define SENSOR_REG_DELAY		4	//16 bits, 12 used	reset signal delay in 50 MHz clocks
+		#define SENSOR_REG_SHUTTER		6	//16 bits, 12 used	sensor reset ('shutter') time in sensor clocks
+		//reg2		
+		#define SENSOR_REG_SERSPEED		8	//8 bits 		synchro baudrate, 50 for 1 Mbps
+		#define SENSOR_REG_HEADER_ANYDATA	9	//8 bits		any data transmitted with SMA state (8 bits SMA + 8 bits anydata)
+		#define SENSOR_REG_HEADER_CMD		10	//16 bits 		command field of the command header transmitted in packet
+		//reg3										//configure reg3  17.July.2024 Qin,L
+		#define SENSOR_REG_CLUSTER_THRESHOLD	12 //8 bits	 the threshold for cluster locate, range 0~255
+		#define SENSOR_REG_CLUSTER_SIZE			13 //8 bits  the size for clluster locate, range 0~255
+		#define SENSOR_REG_IN_ALGO_THRESHOLD	14 //8 bits	 the threshold inside Linear Regression, range 0~255
+		#define SENSOR_REG_RESERVED				15 //8 bits  not used 
+
+		Command bitmasks
+		#define SENSOR_CSR_EN_BITMASK		0x01	//enable operation
+		#define SENSOR_CSR_GAIN_BITMASK		0x02	//gain selection
+		#define SENSOR_CSR_ADCK_BITMASK 	0x04	//ADC clock divider on/off
+		#define SENSOR_CSR_RESET_BITMASK	0x08	//Reset all logic  //registers[0][3]
+
+		Status bitmasks
+		#define SENSOR_STATUS_SEND		0x01	//Sending over Avalon-ST
+		#define SENSOR_STATUS_TRG_WAITING	0x02	//The trigger came and is being delayed now
+		#define SENSOR_STATUS_RESET_ACTIVE	0x04	//The RESET signal for the sensor is active now
+		#define SENSOR_STATUS_ADC_ACTIVE	0x08	//The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high
+		#define SESNOR_STATUS_ADC_FINISHED	0x10	//The ADC waits for reset high
+		#define SESNOR_STATUS_TX_ACTIVE		0x20	//Sync port is sending
+		#define SESNOR_STATUS_RX_ACTIVE		0x40	//Sync port is receiving
+
+	*/
+
+	reg 	[31:0] 	registers[3:0];		//main register space
+	wire 	[31:0]	reg0_read;		//reg[0] is read indirectly to include status byt(bits 15-8)
+
+		//read logic
+	assign reg0_read[7:0] 	= registers[0][7:0];		// Readback of control bits
+	assign reg0_read[31:16] = registers[0][31:16];		// Readback of payload size
+	assign reg0_read[15] 	= 0;							// Unused bits of the status byte 
+	assign csr_readdata 	= (csr_address==0) ? reg0_read : registers[csr_address];
+
+		//write logic
+	generate
+	for (i = 0; i < 4; i = i+1)
+	begin : write_registers	//Quartus wants labels for 'for' blocks
+		for (j = 0; j < 4; j = j+1)
+		begin : write_bytes
+			always @(posedge clk_clk or posedge rst_reset)
+			begin 
+				if (rst_reset)
+					registers[i][8*j+7:8*j] <= 8'd0;
+				else
+					if (csr_byteenable[j] && (csr_address == i) && (csr_write))
+						registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
+			end
+		end
+	end	
+	endgenerate
+
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input and reset bit (reg0.3).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	//reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset | registers[0][3];
+	end
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+	
+	//localparam DATA_OUT_STATE_PEND 	= 3; //the pending when sending data
+
+	localparam WORDS_TO_SEND = 163;	
+	
+		//registers to drive output pins of ST interfaces
+//	reg		reg_valid;
+//	reg	[31:0]	reg_data;
+//	reg		reg_startofpacket;
+//	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			data_out_state <= DATA_OUT_STATE_IDLE;
+			cluster_threshold <= registers[3][7:0];
+			cluster_size <= registers[3][15:8];
+			in_algo_threshold <= registers[3][23:16];
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+						cluster_threshold <= registers[3][7:0];
+						cluster_size <= registers[3][15:8];
+						in_algo_threshold <= registers[3][23:16];
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr + 1'b1;
+						if (tx_ctr == (WORDS_TO_SEND-1))
+							data_out_state <= DATA_OUT_STATE_LOCK;
+					end
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+					data_out_state <= DATA_OUT_STATE_IDLE;
+			endcase
+	end
+
+	assign data_out_valid = (data_out_state == DATA_OUT_STATE_SEND)? 1'b1: 1'b0;
+	assign data_out_data = (data_out_state == DATA_OUT_STATE_SEND)? transmit_buffer[tx_ctr]: 32'b0;
+	assign data_out_startofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == 0) ? 1'b1: 1'b0;
+	assign data_out_endofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == (WORDS_TO_SEND-1)) ? 1'b1: 1'b0;
+
+	assign reg0_read[8] = ~(data_out_state == DATA_OUT_STATE_IDLE);		//to status register
+
+	// *********************** Detector gain logic ************************
+	/*
+		The gain signal is simply derived from reg0.
+	*/
+
+	assign out_sensor_gain = registers[0][1];
+
+	// *********************** Trigger delay logic ************************
+	/*
+		Individual trigger delay settings are needed to synchronize multiple boards.
+		A 12-bit downcounter allows for delaying incoming trigger's rising edge by up to 4095 50MHz clock cycles, i.e. 81.9 us.
+		Note: A further delay of one sensor clock will be added in the sensor clock generation logic.
+	*/
+
+	reg	[11:0]	trg_delay_ctr;
+	wire		int_trg;
+	reg	[1:0]	trg_state;
+	localparam TRG_STATE_IDLE	= 0;	//waiting for external trigger
+	localparam TRG_STATE_DELAY	= 1;	//downcounting
+	localparam TRG_STATE_ACTIVE	= 2;	//internal trigger active 
+	localparam TRG_STATE_LOCK	= 3;	//waiting for external trigger inactive 
+
+	//localparam TRG_DURATION		= 4;	//duration of the trigger signal
+
+	assign int_trg = (trg_state == TRG_STATE_ACTIVE) ? 1'b1 : 1'b0;
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			trg_state <= TRG_STATE_LOCK;
+		end
+		else
+		begin
+			case(trg_state)
+				TRG_STATE_IDLE:
+				begin
+					if (in_trg && registers[0][0])	//react on trigger only if enabled
+					begin
+						trg_delay_ctr <= registers[1][11:0];
+						trg_state <= TRG_STATE_DELAY;
+					end
+				end
+				TRG_STATE_DELAY:
+				begin
+					trg_delay_ctr <= trg_delay_ctr - 1'b1;
+					if (trg_delay_ctr == 0)
+					begin
+						//trg_delay_ctr <= TRG_DURATION-1;
+						trg_state <= TRG_STATE_ACTIVE;
+					end
+				end
+				TRG_STATE_ACTIVE:
+				begin
+					//trg_delay_ctr <= trg_delay_ctr - 1;
+					//if (trg_delay_ctr == 0)
+					//begin
+						trg_state <= TRG_STATE_LOCK;	//only one cycle of active int_trg
+					//end
+				end
+				TRG_STATE_LOCK:
+				begin
+					if (~in_trg)
+						trg_state <= TRG_STATE_IDLE;
+				end
+			endcase		
+		end
+	end
+
+	assign reg0_read[9] = ~(trg_state == TRG_STATE_IDLE);	//to status register
+
+	// *********************** Sensor clock logic  ************************
+	/*
+		The sensor needs a clock of max. 4 MHz, which is generated by this module. 
+		The actual clock speed is configurable by a register with a formula: Fs = Fi/2/(div+1),
+		where Fs is the sensor clock, Fi is input clock (50 MHz nom.) and div is a divider taken from the register.
+		A 5-bit downcounter allows for frequencies from 0.39 MHz (div=63) to 12.5 MHz (div=1).
+		The nominal setting is 6, giving 3.5714285 MHz.
+		
+		Important: The sensor clock is synchronized to the rising edge of the (delayed) trigger input, 
+		so that there is a positive slope at exactly one sensor clock period after the trigger.
+		This positive slope is then used to synchronize integration start signal (sensor reset or shutter). 
+		The synchronization is done so that one of clock states (0 or 1) gets extended, but never shortened.
+
+		Note: 4 MHz is also the top speed accepted by the ADC module.
+	*/
+
+	reg [5:0]	sensor_clk_ctr;
+	reg [1:0]	sensor_clk_state;
+
+	localparam SENSOR_CLK_STATE_LOW	= 2'd0;
+	localparam SENSOR_CLK_STATE_HIGH = 2'd1;
+	localparam SENSOR_CLK_STATE_LOWAIT = 2'd2;
+	localparam SENSOR_CLK_STATE_HIWAIT = 2'd3;	
+
+	assign out_sensor_clk = sensor_clk_state[0];
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+			sensor_clk_ctr <= registers[0][21:16];
+		end
+		else
+		begin
+			case(sensor_clk_state)
+				SENSOR_CLK_STATE_LOW:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIGH;
+					end
+				end
+				SENSOR_CLK_STATE_HIGH:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end			
+				end
+				SENSOR_CLK_STATE_LOWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+				SENSOR_CLK_STATE_HIWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+			endcase
+		end
+	end
+
+	// *********************** Sensor reset (shutter) logic ************************
+	/*
+		This block generates a 'reset' (shutter) signal for the sensor.
+		It defines the integration time and is programmable by means of a register in sensor clock units.
+		The leading (positive) slope of this signal is synchronized with the first positive slope of the sensor clock after the trigger. 
+		An internal 12-bit downcounter allows for a max. integration time of ca 1.15 ms. It can be further extended by slowing down the sensor clock.
+		It's user's responsibility to check if the integration period fits into the trigger period. If this requirement is not fulfilled, some triggers will be skipped.
+		Sorry for this ugly code, but since it works...
+
+		Important remark from sensor's specification: Rise of a RESET pulse must be set outside the video output period. 
+		This must by guaranteed by user by means of proper timing. First video comes 18 cycles after negative slope of sensor reset and is 2 cycles long.
+		Then 2 cycles pause (here we can come with the positive reset slope), then next video and so on, every 4 cycles.
+		The minimum duration of reset low is 21 clocks, and 20 clocks for reset high.
+		Our logic requires that new reset low comes only after all channels are read.
+	*/
+
+	reg [11:0]	sensor_rst_ctr;
+	reg		sensor_rst_state;
+
+	assign out_sensor_rst = sensor_rst_state;
+
+	always @(posedge int_trg or posedge out_sensor_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_rst_state <= 0;
+			sensor_rst_ctr <= 0;
+		end
+		else if (int_trg)
+		begin
+			sensor_rst_ctr <= registers[1][27:16];
+		end	
+		else
+		begin
+			if (sensor_rst_ctr == 0)
+			begin
+				sensor_rst_state <= 0;
+			end
+			else 
+			begin
+				sensor_rst_ctr <= sensor_rst_ctr - 1'b1;
+				sensor_rst_state <= 1'b1;
+			end
+		end
+	end
+
+	assign reg0_read[10] = sensor_rst_state;	//to status register
+
+	// *********************** ADC trigger logic ************************
+	/*
+		This piece produces triggering signals for ADC framework and cares about counting ADC samples.
+		It doesn't rely on incoming Trig signals, just generates them internally by counting clocks.
+
+	*/
+
+	reg [5:0] 	adc_current_channel;
+	reg [2:0]	adc_trg_state;
+	reg [4:0]	adc_trg_downctr;
+	wire 		int_adc_trg;
+	wire 		adc_trg_frame_ready;
+
+	localparam ADC_TRG_STATE_IDLE 	= 0;	//nothing happens, RESET is high or initial state
+	localparam ADC_TRG_STATE_WAIT 	= 1;	//waiting for the first video
+	localparam ADC_TRG_STATE_VIDEO1 = 2;	//capturing video
+	localparam ADC_TRG_STATE_VIDEO2 = 3;	//second cycle
+	localparam ADC_TRG_STATE_VIDEO3 = 4;	//third cycle
+	localparam ADC_TRG_STATE_VIDEO4 = 5;	//fourth cycle
+	localparam ADC_TRG_STATE_FINISH = 6;	//finished readout, waiting for RESET high to enter idle
+	localparam ADC_TRG_STATE_INIT 	= 7;	//used only for reset procedure
+
+	localparam ADC_TRG_INITIALWAIT = 5'd17;	//initial wait for the first video
+	localparam ADC_TRG_VIDEOPERIOD = 4;	//video output period
+
+	always @(posedge out_sensor_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_current_channel <= 63;
+			adc_trg_downctr <= 0;
+			adc_trg_state <= ADC_TRG_STATE_INIT;	//will go to IDLE when adc_trg_reset is high
+		end
+		else
+			case(adc_trg_state)
+				ADC_TRG_STATE_IDLE:
+				begin
+					if (~out_sensor_rst)
+					begin
+						adc_trg_downctr <= ADC_TRG_INITIALWAIT;
+						adc_current_channel <= 63;
+						adc_trg_state <= ADC_TRG_STATE_WAIT;
+					end
+				end
+				ADC_TRG_STATE_WAIT:
+				begin
+					adc_trg_downctr <= adc_trg_downctr - 1'b1;
+					if (adc_trg_downctr == 0)
+					begin
+						adc_trg_state <= ADC_TRG_STATE_VIDEO1;
+					end
+				end
+				ADC_TRG_STATE_VIDEO1:
+				begin
+					adc_current_channel <= adc_current_channel + 1'b1;
+					adc_trg_state = ADC_TRG_STATE_VIDEO2;			
+				end
+				ADC_TRG_STATE_VIDEO2:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO3;			
+				end
+				ADC_TRG_STATE_VIDEO3:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO4;			
+				end
+				ADC_TRG_STATE_VIDEO4:
+				begin
+					if (adc_current_channel == 63)
+						adc_trg_state <= ADC_TRG_STATE_FINISH;
+					else
+						adc_trg_state = ADC_TRG_STATE_VIDEO1;			
+				end	
+				ADC_TRG_STATE_FINISH, ADC_TRG_STATE_INIT:
+				begin
+					if (out_sensor_rst)
+						adc_trg_state <= ADC_TRG_STATE_IDLE;
+				end		
+			endcase
+	end
+
+	//Producing internal trigger for ADC framework (see below)
+	assign int_adc_trg = (adc_trg_state == ADC_TRG_STATE_VIDEO1)  ? 1'b1 : 1'b0;
+
+	assign adc_trg_frame_ready = (adc_trg_state == ADC_TRG_STATE_FINISH) ? 1'b1 : 1'b0;	//trigger data collection machine when the frame is ready
+
+	assign reg0_read[11] = ~(adc_trg_state == ADC_TRG_STATE_IDLE);		//to status register
+	assign reg0_read[12] = (adc_trg_state == ADC_TRG_STATE_FINISH);		//to status register
+
+	// *********************** ADC logic ************************
+	/*
+		SPI interface for ADCs. Triggers conversion and reads out the data on each incoming int_adc_trg.
+		The ADC framework and SPI runs with full clock frequency or with half of it, depending on register setting.
+		The ADC works in the 'CS Mode, 3-Wire Without Busy Indicator Serial Interface'.
+		The CNV signal length is defined by register and expressed in ADC clocks. 
+		It's user's responsibility to ensure that the CNV pulse is longer than 500 ns (required by ADC spec).
+		The ADC clock can be selected to be either full or half system clock.
+	*/
+
+		//Clock divider and selection
+	reg		adc_halfclock;
+	wire		int_adc_clk;
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+			adc_halfclock <= 0;
+		else
+			adc_halfclock <= ~adc_halfclock;
+	end
+	assign int_adc_clk = registers[0][2] ? adc_halfclock : clk_clk;
+
+		//The main state machine
+	reg [2:0]	adc_state;
+	reg [5:0]	adc_downctr;
+
+	localparam ADC_STATE_IDLE 	= 0;		//waiting for conversion
+	localparam ADC_STATE_CNV 	= 1;		//conversion on-going
+	localparam ADC_STATE_STARTREAD	= 2;	//prepare to read, conversion finished
+	localparam ADC_STATE_READ 	= 3;		//reading data
+	localparam ADC_STATE_FINISH	= 4;		//copy data to global buffer
+	localparam ADC_STATE_FINISHED	= 5;	//wait until trigger low, then go to idle
+	
+	always @(posedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_downctr <= 0;
+			adc_state <= ADC_STATE_IDLE;	
+		end
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_IDLE:
+				begin
+					adc_downctr <= registers[0][29:24];
+					if (int_adc_trg)
+						adc_state <= ADC_STATE_CNV;
+				end
+				ADC_STATE_CNV:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_STARTREAD;
+				end
+				ADC_STATE_STARTREAD:
+				begin
+					adc_downctr <= 15;
+					adc_state <= ADC_STATE_READ;
+				end
+				ADC_STATE_READ:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_FINISH;
+				end
+				ADC_STATE_FINISH:
+				begin
+					adc_state <= ADC_STATE_FINISHED;
+				end
+				ADC_STATE_FINISHED:
+				begin
+					if (!int_adc_trg)
+						adc_state <= ADC_STATE_IDLE;
+				end
+				default
+				begin
+					adc_state <= ADC_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Reading data - this happens on the negative slope of clock!
+	reg [15:0] adc_buffer[4:0];		//A shift register for SPI acquisition
+	reg [15:0] frame_buffer[319:0];		//The 'big buffer' for whole frame
+
+	always @(negedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			for (xi = 0; xi < 5; xi = xi+1)
+				adc_buffer[xi] <= 0;
+		end		
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_STARTREAD:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						adc_buffer[xi] <= 0;
+				end
+				ADC_STATE_READ:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+					begin
+						adc_buffer[xi][15:1] <= adc_buffer[xi][14:0];
+						adc_buffer[xi][0] <= in_adc_data[xi];
+					end
+				end
+				ADC_STATE_FINISH:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						frame_buffer[64*xi + adc_current_channel] <= adc_buffer[xi];
+				end
+			endcase
+		end
+	end
+
+
+	assign out_adc_cnv = (adc_state == ADC_STATE_CNV) ? 1'b1 : 1'b0;
+	assign out_adc_clk = (adc_state == ADC_STATE_READ) ? int_adc_clk : 1'b1;
+
+
+	// *********************** Putting data together and letting transmit it ************************
+	/*
+		The data is sent together with a 3-word header (6 16-bit numbers),
+		which is compatible with v.1 head structures:
+			typedef struct
+			{
+				unsigned short marker;	//must be 0x5555
+				unsigned short command;
+				unsigned short length;
+			} command_header;
+			typedef struct
+			{
+				//unsigned short channel_id;
+				unsigned short local_ctr;
+				unsigned short global_ctr;
+				unsigned short sma_state;
+			} sync_frame;
+
+	*/
+	
+	reg [2:0]	merger_state;
+
+	localparam MERGER_STATE_IDLE 	= 0;		//waiting for ADC
+	localparam MERGER_STATE_COLLECT	= 1;		//collect frame information
+	localparam MERGER_STATE_SEND	= 2;		//run Avalon sender
+	localparam MERGER_STATE_FINISH	= 3;		//roll to idle
+	
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			merger_state <= ADC_STATE_IDLE;	
+			for (xi= 0; xi < 163; xi = xi+1)
+				transmit_buffer[xi] <= 0;
+		end
+		else
+		begin
+			case(merger_state)
+				MERGER_STATE_IDLE:
+				begin
+					if (adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_COLLECT;
+				end
+				MERGER_STATE_COLLECT:
+				begin
+					transmit_buffer[0][31:16] 	<= 16'h5555;		//command_header.marker = 0x5555
+					transmit_buffer[0][15:0] 	<= registers[2][31:16];	//command_header.command = reg2.31-16
+					transmit_buffer[1][31:16]	<= 16'd323;	//16'd652;		//command_header.length = 320 samples + 6 sync bytes = 323 * 16bit //16'h143
+					transmit_buffer[1][15:0]	<= local_sync_ctr[15:0];	//sync_frame.local_ctr
+					transmit_buffer[2][24:16]	<= global_sync_ctr;	//sync_frame.global_ctr
+					transmit_buffer[2][25]		<= global_sync_error;	
+					transmit_buffer[2][31:26]	<= 0;
+					transmit_buffer[2][7:0]		<= ext_input;		//sync_frame.sma_state[7:0] = ext_input
+					transmit_buffer[2][15:8]	<= registers[2][15:8];	//sync_frame.sma_state[15:8] = reg2.15-8	
+					for (xi = 0; xi < 160; xi = xi+1)
+					begin
+						//transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi][15:0];	//ADC data
+						//transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi+1][15:0];
+						transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi][15:0];	//ADC data	//CHANGED 26.11.2019
+						transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi+1][15:0];
+					end
+					merger_state <= MERGER_STATE_SEND;
+
+				end
+				MERGER_STATE_SEND:
+				begin
+					merger_state <= MERGER_STATE_FINISH;
+				end
+				MERGER_STATE_FINISH:
+				begin
+					if (~adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Generate Avalon trigger signal
+	assign start_transmission = (merger_state == MERGER_STATE_SEND) ? 1'b1 : 1'b0;
+
+	// *********************** Synchro counter update ************************
+	/*
+		Just increment sunchronization counter at every trigger.
+		The counter is reset by int_reset.
+	*/
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			local_sync_ctr <= 0;
+		end
+		else
+		begin
+			if (int_trg)
+				local_sync_ctr <= local_sync_ctr + 1'b1;
+		end
+	end
+
+
+
+	// *********************** Synchronization serial ports ************************
+	/*
+		There is one TX and one RX module.
+		The TX is getting triggered by int_trg (same as for the main readout framework).
+		It sends 9 LSBs of the local synchro counter with programmed baudrate.
+		The default baudrate is 1 Mbps, which needs a setting of 50 for fclk=50MHz.
+		The RX puts freshly received data into global_sync_ctr. It does not need any triggering.
+	*/
+
+	wire tx_idle;
+	wire rx_idle;
+	assign reg0_read[13] = ~tx_idle;
+	assign reg0_read[14] = ~rx_idle;
+	
+	serial_tx synchro_tx (
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.data		(local_sync_ctr[8:0]),  	//  data to send
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.trigger	(start_transmission),       //  pulse to start transmission - just AFTER collecting data from sensors
+		.tx			(serial_tx),         		//  tx serial connection
+		.idle		(tx_idle)					//	1 if sender in idle state
+	);	
+
+	serial_rx synchro_rx(
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.rx			(serial_rx),         		//  rx serial connection
+		.newdata	(),							//	pulses for new data received
+		.data		(global_sync_ctr),      	//  data received
+		.error		(global_sync_error),		//	bad start or stop bit
+		.idle		(rx_idle)					//	1 if receiver in idle state
+	);
+
+	// *********************** Status output ************************
+	/*
+		The status of the module (== reg0_read[15:8]) is available at the output status bus.
+		It can be then routed to a scope or whatever for debugging
+	*/	
+	
+	assign status_out[7:0] = reg0_read[15:8];	
+	
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sensor_rms.v b/FPGA_firmware/q_sys/synthesis/submodules/sensor_rms.v
new file mode 100644
index 0000000..40bbff5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sensor_rms.v
@@ -0,0 +1,180 @@
+//module top
+//the output datapacket is 166 words; 0~2 is header; 3~162 is data's inverse signed; and last 4 words are not inversed
+
+module sensor_rms (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		//Avalon MM slave
+        input  wire [1:0]  	csr_address,                //            avalon_slave.address
+        input  wire        	csr_read,                   //                        .read
+        output wire [31:0] 	csr_readdata,               //                        .readdata
+        input  wire        	csr_write,                  //                        .write
+        input  wire [31:0] 	csr_writedata,              //                        .writedata
+        input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty,         	//                        .empty
+		//Sensor interface
+        input  wire        	in_trg,                     //                  sensor.in_trg
+        output wire        	out_adc_clk,                //                        .out_dac_clk
+        output wire        	out_adc_cnv,                //                        .out_dac_cnv
+        input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+        output wire        	out_sensor_rst,             //                        .out_sensor_rst
+        output wire        	out_sensor_clk,             //                        .out_sensor_clk
+        output wire        	out_sensor_gain,            //                        .out_sensor_gain
+		//Serial synchro interface
+		input  wire	   		serial_rx,					//receive data
+		output wire	   		serial_tx,					//send data
+		input  wire [7:0]  	ext_input,					//SMA etc.
+		//Debug information
+		output wire [7:0] 	status_out					//status bits - same as in reg0_read[15:8]
+		//output wire[26:0] frameID
+    );
+
+	 
+	 
+ 
+		wire [31:0] data_out_data1;   // Output data
+		wire data_out_endofpacket1;    // Output end-of-packet signal
+		wire data_out_startofpacket1;  // Output start-of-packet signal
+		wire data_out_ready1;         // Output ready signal
+		wire data_out_valid1;         // Output valid signal
+		wire [1:0] data_out_empty1;   // Output empty signal
+
+
+		wire [31:0] data_out_data_algo;   // Output data
+		wire data_out_endofpacket_algo;    // Output end-of-packet signal
+		wire data_out_startofpacket_algo;  // Output start-of-packet signal
+		wire data_out_ready_algo;         // Output ready signal
+		wire data_out_valid_algo;         // Output valid signal
+		wire [1:0] data_out_empty_algo;   // Output empty signal
+
+		wire int_rst;
+
+		wire sig_ram_last;
+
+		wire bkg_sub_on;
+		wire rst_frame;
+		 
+		//data for sig after bkg subtraction
+		wire			   sig_rdclk;						//the read port for sig_ram
+		wire[8:0]		sig_rdaddress;             //0~319 for data. 500~502 for the 3 words head
+		wire[31:0]		sig_out;
+
+		//the output of cluster_locate
+		wire[8:0]		sig_ch_left;
+		wire[8:0]		sig_ch_right;
+		wire				has_cluster;
+		wire				no_cluster;
+			
+
+	  sensor_interface the_sensor_interface (
+			.clk_clk			(clk_clk),                //      clk.clk
+			.rst_reset			(rst_reset),              //      rst.reset
+			.csr_address			(csr_address),            //      csr.address
+			.csr_write			(csr_write),              //         .write
+			.csr_writedata			(csr_writedata),          //         .writedata
+			.csr_byteenable			(csr_byteenable),         //         .byteenable
+			.csr_read			(csr_read),               //         .read
+			.csr_readdata			(csr_readdata),           //         .readdata
+			.data_out_data			(data_out_data1),          // data_out.data
+			.data_out_empty			(data_out_empty1),         //         .empty
+			.data_out_endofpacket		(data_out_endofpacket1),   //         .endofpacket
+			.data_out_startofpacket		(data_out_startofpacket1),//         .startofpacket
+			.data_out_ready			(data_out_ready1),         //         .ready
+			.data_out_valid			(data_out_valid1),          //         .valid
+			.in_trg 			(in_trg),                                //                  sensor.in_trg
+			.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+			.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+			.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+			.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+			.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+			.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+			.serial_rx			(serial_rx),		//receive data
+			.serial_tx			(serial_tx),		//send data
+			.ext_input			(ext_input),			//SMA etc.
+			.int_rst          (int_rst)
+	);
+	
+	
+	
+  data_interface #(.BKG_FRAME(8192), .CLU_THRESHOLD(14), .CLU_SIZE(4)) data_interface_dut (
+			.clk_clk(clk_clk),                              // Clock input
+			.rst_reset(int_rst),                          // Reset input
+			
+			
+			.data_in_data(data_out_data1),                     // Input data
+			.data_in_ready(data_out_ready1),                   // Input ready signal
+			.data_in_valid(data_out_valid1),                   // Input valid signal
+			.data_in_empty(data_out_empty1),                   // Input empty signal
+			.data_in_endofpacket(data_out_endofpacket1),       // Input end-of-packet signal
+			.data_in_startofpacket(data_out_startofpacket1),   // Input start-of-packet signal
+			
+			.data_out_data(data_out_data_algo),                   // Output data
+			.data_out_endofpacket(data_out_endofpacket_algo),     // Output end-of-packet signal
+			.data_out_startofpacket(data_out_startofpacket_algo), // Output start-of-packet signal
+			.data_out_ready(data_out_ready_algo),                 // Output ready signal
+			.data_out_valid(data_out_valid_algo),                 // Output valid signal
+			.data_out_empty(data_out_empty_algo),                  // Output empty signal
+			.bkg_sub_on(bkg_sub_on), 
+			.rst_frame(rst_frame),
+				 
+																//data for sig after bkg subtraction
+			.sig_rdclk(sig_rdclk),						//the read port for sig_ram
+			.sig_rdaddress(sig_rdaddress),             //0~319 for data. 500~502 for the 3 words head
+			.sig_out(sig_out),
+			.sig_ram_last(sig_ram_last),
+			.sig_ch_left(sig_ch_left),			
+			.sig_ch_right(sig_ch_right),
+			.has_cluster(has_cluster),
+			.no_cluster(no_cluster)
+			
+			
+  );
+  
+	
+	rms rms_but(
+	
+			.clk_clk(clk_clk),                    //                     clk.clk
+			.rst_reset(rst_frame),         			// the reset should connect to the rst_frame
+
+			//data for sig after bkg subtraction
+			.bkg_sub_on(bkg_sub_on), 					//indicate that bkg_sub is on 
+			.sig_rdclk(sig_rdclk),						//the read port for sig_ram
+			.sig_rdaddress(sig_rdaddress),             //0~319 for data. 500~502 for the 3 words head
+			.sig(sig_out),
+			.sig_ram_last(sig_ram_last),
+
+
+			 .data_in_data(data_out_data_algo),                     // Input data
+			.data_in_ready(data_out_ready_algo),                   // Input ready signal
+			.data_in_valid(data_out_valid_algo),                   // Input valid signal
+			.data_in_empty(data_out_empty_algo),                   // Input empty signal
+			.data_in_endofpacket(data_out_endofpacket_algo),       // Input end-of-packet signal
+			.data_in_startofpacket(data_out_startofpacket_algo),   // Input start-of-packet signal
+
+
+
+
+			//the output of cluster_locate
+			.sig_ch_left(sig_ch_left),
+			.sig_ch_right(sig_ch_right),
+			.has_cluster(has_cluster),
+			.no_cluster(no_cluster),
+
+
+			.data_out_data(data_out_data),                   // Output data
+			.data_out_endofpacket(data_out_endofpacket),     // Output end-of-packet signal
+			.data_out_startofpacket(data_out_startofpacket), // Output start-of-packet signal
+			.data_out_ready(data_out_ready),                 // Output ready signal
+			.data_out_valid(data_out_valid),                 // Output valid signal
+			.data_out_empty(data_out_empty)                 // Output empty signal
+
+	);
+
+	endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sequencer_m10.sv b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_m10.sv
new file mode 100644
index 0000000..06442a0
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_m10.sv
@@ -0,0 +1,1209 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******
+// sequencer_m10
+// ******
+//
+// Max10 RTL Sequencer
+//
+// General Description
+// -------------------
+//
+// This component replaces the NIOS to calibrate Max10 EMIF
+// Max10 EMIF uses PLL clock to capture DQ data
+//
+//
+
+`timescale 1 ps / 1 ps
+
+module sequencer_m10 #
+    ( parameter
+        AVL_DATA_WIDTH          = 32,
+        AVL_ADDR_WIDTH          = 20, 
+        READ_VALID_FIFO_SIZE    = 16,
+        HPS_PROTOCOL            = "DDR3",
+        PHY_MGR_BASE            = 294912,
+        RW_MGR_BASE             = 327680,
+        PLL_MGR_BASE            = 360448,
+        MEM_DQ_WIDTH            = 24
+    )
+    (
+	clk,
+	reset_n,
+	address,
+	write,
+	writedata,
+	read,
+	readdata,
+	waitrequest,
+	pd_reset_n,
+	pd_ack,
+	pd_up,
+	pd_down
+);
+
+    localparam  PRE_N_ACT_1 =   (HPS_PROTOCOL == "DDR3") ? 'h14 : ((HPS_PROTOCOL == "DDR2") ? 'h16 : 'h14);
+    localparam  PRE_N_ACT_2 =   (HPS_PROTOCOL == "DDR3") ? 'hf  : ((HPS_PROTOCOL == "DDR2") ? 'hf  : 'hf );
+    localparam  PRE_N_ACT_3 =   (HPS_PROTOCOL == "DDR3") ? 'h10 : ((HPS_PROTOCOL == "DDR2") ? 'h12 : 'h10);
+    localparam  PRE_N_ACT_4 =   (HPS_PROTOCOL == "DDR3") ? 'hf  : ((HPS_PROTOCOL == "DDR2") ? 'hf  : 'hf );
+    localparam  PRE_N_ACT_5 =   (HPS_PROTOCOL == "DDR3") ? 'h12 : ((HPS_PROTOCOL == "DDR2") ? 'h14 : 'h12);
+    localparam  PRE_N_ACT_6 =   (HPS_PROTOCOL == "DDR3") ? 'hf  : ((HPS_PROTOCOL == "DDR2") ? 'h11 : 'hf );
+    
+    localparam  GRNTEE_WR_1 =   (HPS_PROTOCOL == "DDR3") ? 'h20 : ((HPS_PROTOCOL == "DDR2") ? 'h20 : 'h20);
+    localparam  GRNTEE_WR_2 =   (HPS_PROTOCOL == "DDR3") ? 'h1c : ((HPS_PROTOCOL == "DDR2") ? 'h1d : 'h19);
+    localparam  GRNTEE_WR_3 =   (HPS_PROTOCOL == "DDR3") ? 'h20 : ((HPS_PROTOCOL == "DDR2") ? 'h20 : 'h20);
+    localparam  GRNTEE_WR_4 =   (HPS_PROTOCOL == "DDR3") ? 'h20 : ((HPS_PROTOCOL == "DDR2") ? 'h21 : 'h1d);
+    localparam  GRNTEE_WR_5 =   (HPS_PROTOCOL == "DDR3") ? 'h2  : ((HPS_PROTOCOL == "DDR2") ? 'h2  : 'h2 );
+    localparam  GRNTEE_WR_6 =   (HPS_PROTOCOL == "DDR3") ? 'h1a : ((HPS_PROTOCOL == "DDR2") ? 'h1b : 'h17);
+    localparam  GRNTEE_WR_7 =   (HPS_PROTOCOL == "DDR3") ? 'h2  : ((HPS_PROTOCOL == "DDR2") ? 'h2  : 'h2 );
+    localparam  GRNTEE_WR_8 =   (HPS_PROTOCOL == "DDR3") ? 'h1e : ((HPS_PROTOCOL == "DDR2") ? 'h1f : 'h1b);
+    localparam  GRNTEE_WR_9 =   (HPS_PROTOCOL == "DDR3") ? 'h19 : ((HPS_PROTOCOL == "DDR2") ? 'h1a : 'h16);
+    
+    localparam  READ_CHK_1  =   (HPS_PROTOCOL == "DDR3") ? 'h10 : ((HPS_PROTOCOL == "DDR2") ? 'h10 : 'h10);
+    localparam  READ_CHK_2  =   (HPS_PROTOCOL == "DDR3") ? 'h45 : ((HPS_PROTOCOL == "DDR2") ? 'h46 : 'h42);
+    localparam  READ_CHK_3  =   (HPS_PROTOCOL == "DDR3") ? 'h10 : ((HPS_PROTOCOL == "DDR2") ? 'h10 : 'h10);
+    localparam  READ_CHK_4  =   (HPS_PROTOCOL == "DDR3") ? 'h4b : ((HPS_PROTOCOL == "DDR2") ? 'h4c : 'h48);
+    localparam  READ_CHK_5  =   (HPS_PROTOCOL == "DDR3") ? 'h1  : ((HPS_PROTOCOL == "DDR2") ? 'h1  : 'h1 );
+    localparam  READ_CHK_6  =   (HPS_PROTOCOL == "DDR3") ? 'h41 : ((HPS_PROTOCOL == "DDR2") ? 'h42 : 'h3e);
+    localparam  READ_CHK_7  =   (HPS_PROTOCOL == "DDR3") ? 'h1  : ((HPS_PROTOCOL == "DDR2") ? 'h1  : 'h1 );
+    localparam  READ_CHK_8  =   (HPS_PROTOCOL == "DDR3") ? 'h41 : ((HPS_PROTOCOL == "DDR2") ? 'h42 : 'h3e);
+    localparam  READ_CHK_9  =   (HPS_PROTOCOL == "DDR3") ? 'h0  : ((HPS_PROTOCOL == "DDR2") ? 'h0  : 'h0 );
+    localparam  READ_CHK_10 =   (HPS_PROTOCOL == "DDR3") ? 'h41 : ((HPS_PROTOCOL == "DDR2") ? 'h42 : 'h3e);
+    localparam  READ_CHK_11 =   (HPS_PROTOCOL == "DDR3") ? 'h3e : ((HPS_PROTOCOL == "DDR2") ? 'h3f : 'h3b);
+    
+    localparam  READ_LATENCY    =   5'h16;
+    localparam  DISABLE_FILTER  =    1'b0;
+    localparam  DISABLE_PD      =    1'b0; 
+
+	input                              clk;
+	input                              reset_n;
+	output [AVL_ADDR_WIDTH - 1:0]      address;
+	output                             write;
+	output [AVL_DATA_WIDTH - 1:0]      writedata;
+	output                             read;
+	input [AVL_DATA_WIDTH - 1:0]       readdata;
+	input                              waitrequest;
+	output                             pd_reset_n;
+	output                             pd_ack;
+	input                              pd_up;
+	input                              pd_down;
+	
+	logic [AVL_ADDR_WIDTH - 1:0]       address;
+	logic                              write;
+	logic [AVL_DATA_WIDTH - 1:0]       writedata;
+	logic                              read;
+	logic                              pd_reset_n;
+	logic                              pd_ack;
+	
+	logic [5:0]    seq_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       main_address;
+	logic                              main_write;
+	logic [AVL_DATA_WIDTH - 1:0]       main_writedata;
+	logic                              main_read;
+	logic [23:0]   readdata_reg;
+	logic [23:0]   best_comp_result;
+	logic          data_mismatch;
+	logic [2:0]    vfifo;
+	logic [7:0]    count;
+	logic [7:0]    valid_phase;
+	logic          reverse;
+	logic          finding_window;
+	logic          window_found;
+	logic          latency_calib;
+	logic [1:0]    grp;
+	
+	logic    start_ddr3_init;
+	logic    ddr3_init_done;
+	logic    start_ddr2_init;
+	logic    ddr2_init_done;
+	logic    start_lpddr2_init;
+	logic    lpddr2_init_done;
+	logic    start_write;
+	logic    write_done;
+	logic    start_user_mr;
+	logic    user_mr_done;
+	logic    pd_start;
+	logic    cal_init_req;
+	
+	logic          wr_and_not_waitrequest;
+	
+	assign    wr_and_not_waitrequest    =    main_write & ~waitrequest;
+	
+    always_ff @(posedge clk, negedge reset_n)
+        begin
+            if (!reset_n)
+                begin
+                    seq_state         <=  0;
+                    main_address      <=  '0;
+                    main_write        <=  0;
+                    main_writedata    <=  '0;
+                    main_read         <=  0;
+                    readdata_reg      <=  '0;
+                    best_comp_result  <=  '0;
+                    data_mismatch     <=  0;
+                    vfifo             <=  '0;
+                    count             <=  0;
+                    valid_phase       <=  0;
+                    reverse           <=  0;
+                    finding_window    <=  0;
+                    window_found      <=  0;
+                    latency_calib     <=  0;
+                    start_ddr3_init   <=  0;
+                    start_ddr2_init   <=  0;
+                    start_lpddr2_init <=  0;
+                    start_write       <=  0;
+                    start_user_mr     <=  0;
+                    pd_start          <=  0;
+                    grp               <=  '0;
+                end
+            else
+                case(seq_state)
+                    0   :
+                        begin
+                            best_comp_result <= {24{1'b1}};
+                            if (HPS_PROTOCOL == "DDR3")
+                                seq_state       <=  1;
+                            else if (HPS_PROTOCOL == "DDR2")
+                                seq_state       <=  2;
+                            else // LPDDR2
+                                seq_state       <=  3;
+                        end
+                    
+                    // start DDR3 initialization sequence
+                    1   :
+                        begin
+                            start_ddr3_init     <=  1;
+                            if (ddr3_init_done)
+                                begin
+                                    start_ddr3_init <=  0;
+                                    seq_state       <=  4;
+                                end
+                        end
+                    // end of DDR3 initialization sequence
+                    
+                    // start DDR2 initialization sequence
+                    2   :
+                        begin
+                            start_ddr2_init     <=  1;
+                            if (ddr2_init_done)
+                                begin
+                                    start_ddr2_init <=  0;
+                                    seq_state       <=  4;
+                                end
+                        end
+                    // end of DDR2 initialization sequence
+                    
+                    // start LPDDR2 initialization sequence
+                    3   :
+                        begin
+                            start_lpddr2_init   <=  1;
+                            if (lpddr2_init_done)
+                                begin
+                                    start_lpddr2_init   <=  0;
+                                    seq_state       <=  4;
+                                end
+                        end
+                    // end of LPDDR2 initialization sequence
+                    
+                    // precharge and activate then guarantee write
+                    4   :
+                        begin
+                            start_write   <=  1;
+                            if (write_done)
+                                begin
+                                    start_write     <=  0;
+                                    seq_state       <=  5;
+                                end
+                        end
+                    
+                    // read data checking routine
+                    5   : write_task_rw ('h201     ,READ_CHK_1  ,6  );
+                    6   : write_task_rw ('h301     ,READ_CHK_2  ,7  );
+                    7   : write_task_rw ('h202     ,READ_CHK_3  ,8  );
+                    8   : write_task_rw ('h302     ,READ_CHK_4  ,9  );
+                    9   : write_task_rw ('h200     ,READ_CHK_5  ,10 );
+                    10  : write_task_rw ('h300     ,READ_CHK_6  ,11 );
+                    11  : write_task_rw ('h203     ,READ_CHK_7  ,12 );
+                    12  : write_task_rw ('h303     ,READ_CHK_8  ,13 );
+                    13  : write_task_ph ('h2       ,'h0         ,14 ); // PHY manager, read fifo reset
+                    14  : write_task_rw ('h400     ,READ_CHK_9  ,15 );
+                    15  : write_task_rw (grp       ,READ_CHK_10 ,16 );
+                    16  :
+                        begin
+                            main_read    <=  1;
+                            main_address <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0];//
+                            if (main_read && !waitrequest)
+                                begin
+                                    main_read       <=  0;
+                                    main_address    <=  '0;
+                                    seq_state       <=  38;
+                                    if (grp == 2)
+                                        readdata_reg[23:16]    <=  readdata[7:0];
+                                    else if (grp == 1)
+                                        readdata_reg[15:8]    <=  readdata[7:0];
+                                    else
+                                        readdata_reg[7:0]    <=  readdata[7:0];
+                                end
+                        end
+                    38  :
+                        begin
+                            if (MEM_DQ_WIDTH == 24)
+                                begin
+                                    if (grp == 2)
+                                        begin
+                                            grp         <=  0;
+                                            seq_state   <=  17;
+                                        end
+                                    else
+                                        begin
+                                            grp         <=  grp + 1'b1;
+                                            seq_state   <=  5;
+                                        end
+                                end
+                            else if (MEM_DQ_WIDTH == 16)
+                                begin
+                                    if (grp == 1)
+                                        begin
+                                            grp         <=  0;
+                                            seq_state   <=  17;
+                                        end
+                                    else
+                                        begin
+                                            grp         <=  grp + 1'b1;
+                                            seq_state   <=  5;
+                                        end
+                                end
+                            else 
+                                seq_state   <=  17;
+                        end
+                    17  : write_task_rw ('h0       ,READ_CHK_11 ,18 );
+                    18  :
+                        begin
+                            if (readdata_reg != 0)
+                                data_mismatch   <=  1;
+                            else
+                                data_mismatch   <=  0;
+                            
+                            if (readdata_reg[23:16] < best_comp_result[23:16])
+                                best_comp_result[23:16]    <=  readdata_reg[23:16];
+                            
+                            if (readdata_reg[15:8] < best_comp_result[15:8])
+                                best_comp_result[15:8]    <=  readdata_reg[15:8];
+                            
+                            if (readdata_reg[7:0] < best_comp_result[7:0])
+                                best_comp_result[7:0]    <=  readdata_reg[7:0];
+                                
+                            if (latency_calib)
+                                seq_state   <=  29;
+                            else if (finding_window)
+                                seq_state   <=  26;
+                            else if (reverse)
+                                seq_state   <=  24;
+                            else
+                                seq_state   <=  19;
+                        end
+                    // end read data checking routine
+                    
+                    // find first working phase
+                    19  :
+                        begin
+                            if (data_mismatch) // data mismatch
+                                begin
+                                    if (count == 150) // 57x2 is the calculated steps for 167Mhz
+                                        seq_state   <=  22; // give up, fail calibration
+                                    else if (vfifo == 7) // increment PLL phase
+                                        begin
+                                            write_task_capture_clock (1         ,20 );
+                                            
+                                            if (wr_and_not_waitrequest)
+                                                count       <=  count + 1'b1;
+                                        end
+                                    else
+                                        seq_state   <=  20;
+                                end
+                            else // data match! then reverse phase
+                                begin
+                                    $display("          --- SEQUENCER FOUND FIRST WORKING PHASE --- ");
+                                    reverse             <=  1;
+                                    seq_state           <=  5 ;
+                                end
+                        end
+                    20  :
+                        begin
+                            vfifo       <=  vfifo + 1'b1;
+                            seq_state   <=  21;
+                        end
+                    21  : write_task_ph ('h1       ,'hff        ,5  ); // increment vfifo for all groups
+                    // algorithm ends here
+                    
+                    // PHY manager, cal fail
+                    22  : write_task_ph ('h1003    ,'h2         ,36 );
+                    
+                    // reverse phase until fail, useful if already in a working phase on start
+                    24 :
+                        begin
+                            if (data_mismatch) //data mismatch, increment and move to finding window
+                                begin
+                                    reverse     <=  0;
+                                    write_task_capture_clock (1         ,25 );
+                                end
+                            else // data match, decrement until it fails
+                                write_task_capture_clock (0         ,5  );
+                        end
+                    
+                    // finding window, sweep till fail
+                    25  :
+                        begin
+                            $display("          --- START FINDING WINDOW --- ");
+                            finding_window      <=  1;
+                            count               <=  1;
+                            seq_state           <=  5 ;
+                        end
+                    26  :
+                        begin
+                            if (data_mismatch) // data mismatch
+                                begin
+                                    if (!window_found) 
+                                        write_task_capture_clock (1         ,5  ); 
+                                    else
+                                        begin
+                                            $display("          --- TOTAL VALID PHASE %d --- ",count - 1);
+                                            valid_phase     <=  count-1'b1;
+                                            finding_window  <=  0;
+                                            count           <=  count/2'd2; // formula to move the correct number of phase
+                                            $display("          --- REVERSE TO CENTER %d PHASE(S)--- ",((count - 2)/2)+2);
+                                            seq_state       <=  27;
+                                        end
+                                end
+                            else
+                                begin
+                                    window_found    <=  1;
+                                    write_task_capture_clock (1         ,5  ); // increment PLL phase
+                                    
+                                    if (wr_and_not_waitrequest)
+                                        count           <=  count+1'b1;
+                                end
+                        end
+                    
+                    // going to the center of window after sweep
+                    27  :
+                        begin
+                            if (count != 0)
+                                begin
+                                    write_task_capture_clock (0         ,27 ); // decrement PLL phase
+                                    
+                                    if (wr_and_not_waitrequest)
+                                        count       <=  count-1'b1;
+                                end
+                            else
+                                seq_state   <=  31;
+                        end
+                    
+                    // calibration done
+                    31  : write_task_rw ('h0       ,PRE_N_ACT_1 ,32 ); // precharge
+                    32  : write_task_ph ('h2       ,'h0         ,33 ); // PHY manager, read fifo reset
+                    33  :
+                        begin
+                            start_user_mr   <=  1;
+                            if (user_mr_done)
+                                begin
+                                    start_user_mr   <=  0;
+                                    seq_state       <=  34;
+                                end
+                        end
+                    
+                    // PHY manager, mux sel
+                    34  : write_task_ph ('h1002    ,'h0         ,35 );
+                    // PHY manager, cal success
+                    35  : write_task_ph ('h1003    ,'h1         ,36 );
+                    // PHY manager, debug info reports window size, best comparison data
+                    36  : write_task_ph ('h1004    ,{best_comp_result,valid_phase}         ,37 );
+                    // calibration done
+                    37  : 
+                        begin
+                            if (pd_start && cal_init_req)
+                                begin
+                                    pd_start <=  0;
+                                    seq_state   <=  39;
+                                    
+                                    readdata_reg      <=  '0;
+                                    best_comp_result  <=  '0;
+                                    data_mismatch     <=  0;
+                                    vfifo             <=  '0;
+                                    count             <=  0;
+                                    valid_phase       <=  0;
+                                    reverse           <=  0;
+                                    finding_window    <=  0;
+                                    window_found      <=  0;
+                                    latency_calib     <=  0;
+                                    grp               <=  '0;
+                                end
+                            else
+                                begin
+                                    pd_start <=  1;
+                                end
+                        end
+                    39  : write_task_ph ('h1003    ,'h0         ,40 );
+                    40  : write_task_ph ('h1002    ,'h1         ,0  );
+                endcase
+        end
+        
+task write_task_rw;
+    input [AVL_ADDR_WIDTH - 1:0] task_address;
+    input [AVL_DATA_WIDTH - 1:0] data;
+    input [5:0] next_state;
+    
+    begin
+        main_write       <=  1;
+        main_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+        main_writedata   <=  data;
+        if (wr_and_not_waitrequest)
+            begin
+                main_write       <=  0;
+                main_address     <=  '0;
+                main_writedata   <=  '0;
+                seq_state   <=  next_state;
+            end
+    end
+endtask
+
+task write_task_ph;
+    input [AVL_ADDR_WIDTH - 1:0] task_address;
+    input [AVL_DATA_WIDTH - 1:0] data;
+    input [5:0] next_state;
+    
+    begin
+        main_write       <=  1;
+        main_address     <=  PHY_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+        main_writedata   <=  data;
+        if (wr_and_not_waitrequest)
+            begin
+                main_write       <=  0;
+                main_address     <=  '0;
+                main_writedata   <=  '0;
+                seq_state   <=  next_state;
+            end
+    end
+endtask
+
+task write_task_capture_clock;
+    input data;
+    input [5:0] next_state;
+    
+    begin
+        main_write       <=  1;
+        main_address     <=  PLL_MGR_BASE[AVL_ADDR_WIDTH - 1:0];
+        main_writedata   <=  data;
+        if (wr_and_not_waitrequest)
+            begin
+                main_write       <=  0;
+                main_address     <=  '0;
+                main_writedata   <=  '0;
+                seq_state   <=  next_state;
+            end
+    end
+endtask
+    
+	logic [4:0]    ddr3_init_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       ddr3_init_address;
+	logic                              ddr3_init_write;
+	logic [AVL_DATA_WIDTH - 1:0]       ddr3_init_writedata;
+
+generate
+    if (HPS_PROTOCOL == "DDR3")
+        begin
+            task ddr3_init_write_task_rw;
+                input [AVL_ADDR_WIDTH - 1:0] task_address;
+                input [AVL_DATA_WIDTH - 1:0] data;
+                input [4:0] next_state;
+            
+                begin
+                    ddr3_init_write       <=  1;
+                    ddr3_init_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+                    ddr3_init_writedata   <=  data;
+                    if (ddr3_init_write && !waitrequest)
+                        begin
+                            ddr3_init_write       <=  0;
+                            ddr3_init_address     <=  '0;
+                            ddr3_init_writedata   <=  '0;
+                            ddr3_init_state   <=  next_state;
+                        end
+                end
+            endtask            
+            always_ff @(posedge clk, negedge reset_n)
+                begin
+                    if (!reset_n)
+                        begin
+                            ddr3_init_state       <=  0;
+                            ddr3_init_done        <=  0;
+                            ddr3_init_address     <=  '0;
+                            ddr3_init_write       <=  0;
+                            ddr3_init_writedata   <=  '0;
+                        end
+                    else
+                        case(ddr3_init_state)
+                            0   : if (start_ddr3_init) ddr3_init_state <=  1;
+                            // start DDR3 initialization sequence
+                            //                   address    data         next_state
+                            1   : ddr3_init_write_task_rw ('h800     ,'h0         ,2  );
+                            2   : ddr3_init_write_task_rw ('h500     ,'hfe        ,3  );
+                            3   : ddr3_init_write_task_rw ('h500     ,'h0         ,4  );
+                            4   : ddr3_init_write_task_rw ('h200     ,'hff         ,5  );
+                            5   : ddr3_init_write_task_rw ('h201     ,'hff         ,6  );
+                            6   : ddr3_init_write_task_rw ('h300     ,'h4f        ,7  );
+                            7   : ddr3_init_write_task_rw ('h301     ,'h50        ,8  );
+                            8   : ddr3_init_write_task_rw ('h0       ,'h4f        ,9  ); // delay?
+                            9   : ddr3_init_write_task_rw ('h200     ,'hff         ,10 );
+                            10  : ddr3_init_write_task_rw ('h201     ,'hff         ,11 );
+                            11  : ddr3_init_write_task_rw ('h300     ,'h54        ,12 );
+                            12  : ddr3_init_write_task_rw ('h301     ,'h55        ,13 );
+                            13  : ddr3_init_write_task_rw ('h0       ,'h54        ,14 ); // reset goes high
+                            14  : ddr3_init_write_task_rw ('h201     ,'h7c        ,15 ); 
+                            15  : ddr3_init_write_task_rw ('h301     ,'h5c        ,16 ); 
+                            16  : ddr3_init_write_task_rw ('h0       ,'h5c        ,17 ); /// cke goes high
+                            17  : ddr3_init_write_task_rw ('h0       ,'h7         ,18 ); // MR bank 2
+                            18  : ddr3_init_write_task_rw ('h0       ,'h9         ,19 ); // MR bank 3
+                            19  : ddr3_init_write_task_rw ('h0       ,'h5         ,20 ); // MR bank 1
+                            20  : ddr3_init_write_task_rw ('h0       ,'h3         ,21 ); // DLL reset
+                            21  : ddr3_init_write_task_rw ('h0       ,'hb         ,22 ); // ZQ cal
+                            // end of DDR3 initialization sequence
+                            22  :
+                                begin
+                                    if (cal_init_req)
+                                        begin
+                                            ddr3_init_done      <=  0;
+                                            ddr3_init_state     <=  0;
+                                        end
+                                    else
+                                        ddr3_init_done    <=  1;
+                                end
+                        endcase
+                end
+            
+        end
+    else
+        begin
+            assign  ddr3_init_done          =   0;
+            assign  ddr3_init_address       =   '0;
+            assign  ddr3_init_write         =   0;
+            assign  ddr3_init_writedata     =   '0;
+        end
+endgenerate
+        
+    logic [4:0]    ddr2_init_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       ddr2_init_address;
+	logic                              ddr2_init_write;
+	logic [AVL_DATA_WIDTH - 1:0]       ddr2_init_writedata;
+	logic [6:0]    count2;
+
+generate
+    if (HPS_PROTOCOL == "DDR2")
+        begin
+                task ddr2_init_write_task_rw;
+                input [AVL_ADDR_WIDTH - 1:0] task_address;
+                input [AVL_DATA_WIDTH - 1:0] data;
+                input [4:0] next_state;
+            
+                begin
+                    ddr2_init_write       <=  1;
+                    ddr2_init_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+                    ddr2_init_writedata   <=  data;
+                    if (ddr2_init_write && !waitrequest)
+                        begin
+                            ddr2_init_write       <=  0;
+                            ddr2_init_address     <=  '0;
+                            ddr2_init_writedata   <=  '0;
+                            ddr2_init_state   <=  next_state;
+                        end
+                end
+            endtask
+            always_ff @(posedge clk, negedge reset_n)
+                begin
+                    if (!reset_n)
+                        begin
+                            ddr2_init_state       <=  0;
+                            ddr2_init_done        <=  0;
+                            ddr2_init_address     <=  '0;
+                            ddr2_init_write       <=  0;
+                            ddr2_init_writedata   <=  '0;
+                            count2                <=  '0;
+                        end
+                    else
+                        case(ddr2_init_state)
+                            0   : if (start_ddr2_init) ddr2_init_state <=  1;
+                            // start DDR2 initialization sequence
+                            //                   address    data         next_state
+                            1   : ddr2_init_write_task_rw ('h800     ,'h0         ,2  );
+                            2   : ddr2_init_write_task_rw ('h500     ,'hfe        ,3  );
+                            3   : ddr2_init_write_task_rw ('h200     ,'hff        ,4  );
+                            4   : ddr2_init_write_task_rw ('h201     ,'hff        ,5  );
+                            5   : ddr2_init_write_task_rw ('h300     ,'h50        ,6  );
+                            6   : ddr2_init_write_task_rw ('h301     ,'h51        ,7  );
+                            7   : ddr2_init_write_task_rw ('h0       ,'h50        ,8  ); // delay?
+                            8   : ddr2_init_write_task_rw ('h0       ,'h1         ,22 ); // CKE goes high
+                            22  :
+                                begin
+                                    if (count2 == 100)
+                                        begin
+                                            ddr2_init_state   <=  9;
+                                            count2            <=  0;
+                                        end
+                                    else
+                                        count2      <=  count2 + 1'b1;
+                                end
+                            9   : ddr2_init_write_task_rw ('h0       ,'h16        ,10 ); // precharge
+                            10  : ddr2_init_write_task_rw ('h0       ,'hd         ,11 ); // MR bank 2
+                            11  : ddr2_init_write_task_rw ('h0       ,'hf         ,12 ); // MR bank 3
+                            12  : ddr2_init_write_task_rw ('h0       ,'h9         ,13 ); // MR bank 1
+                            13  : ddr2_init_write_task_rw ('h0       ,'h7         ,14 ); // MR bank 0
+                            14  : ddr2_init_write_task_rw ('h0       ,'h16        ,15 ); // precharge
+                            15  : ddr2_init_write_task_rw ('h0       ,'h18        ,16 ); // refresh
+                            16  :
+                                begin
+                                    if (count2 == 100)
+                                        begin
+                                            ddr2_init_state   <=  17;
+                                            count2            <=  0;
+                                        end
+                                    else
+                                        count2      <=  count2 + 1'b1;
+                                end
+                            17  : ddr2_init_write_task_rw ('h0       ,'h18        ,23 ); // refresh
+                            23  :
+                                begin
+                                    if (count2 == 100)
+                                        begin
+                                            ddr2_init_state   <=  18;
+                                            count2            <=  0;
+                                        end
+                                    else
+                                        count2      <=  count2 + 1'b1;
+                                end
+                            18  : ddr2_init_write_task_rw ('h0       ,'h5         ,19 ); // MR bank 0
+                            19  : ddr2_init_write_task_rw ('h0       ,'hb         ,20 ); // MR bank 1
+                            20  : ddr2_init_write_task_rw ('h0       ,'h9         ,21 ); // MR bank 1
+                            // end of DDR2 initialization sequence
+                            21  :
+                                begin
+                                    if (cal_init_req)
+                                        begin
+                                            ddr2_init_done      <=  0;
+                                            ddr2_init_state     <=  0;
+                                        end
+                                    else
+                                        ddr2_init_done    <=  1;
+                                end
+                        endcase
+                end
+            
+        end
+    else
+        begin
+            assign  ddr2_init_done          =   0;
+            assign  ddr2_init_address       =   '0;
+            assign  ddr2_init_write         =   0;
+            assign  ddr2_init_writedata     =   '0;
+        end
+endgenerate
+        
+    logic [3:0]    lpddr2_init_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       lpddr2_init_address;
+	logic                              lpddr2_init_write;
+	logic [AVL_DATA_WIDTH - 1:0]       lpddr2_init_writedata;
+	logic [7:0]    count4;
+	logic [7:0]    count5;
+
+generate
+    if (HPS_PROTOCOL == "LPDDR2")
+        begin
+            task lpddr2_init_write_task_rw;
+                input [AVL_ADDR_WIDTH - 1:0] task_address;
+                input [AVL_DATA_WIDTH - 1:0] data;
+                input [3:0] next_state;
+                begin
+                    lpddr2_init_write       <=  1;
+                    lpddr2_init_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+                    lpddr2_init_writedata   <=  data;
+                    if (lpddr2_init_write && !waitrequest)
+                        begin
+                            lpddr2_init_write       <=  0;
+                            lpddr2_init_address     <=  '0;
+                            lpddr2_init_writedata   <=  '0;
+                            lpddr2_init_state   <=  next_state;
+                        end
+                end
+            endtask
+            
+            always_ff @(posedge clk, negedge reset_n)
+                begin
+                    if (!reset_n)
+                        begin
+                            lpddr2_init_state       <=  0;
+                            lpddr2_init_done        <=  0;
+                            lpddr2_init_address     <=  '0;
+                            lpddr2_init_write       <=  0;
+                            lpddr2_init_writedata   <=  '0;
+                            count4                  <=  '0;
+                            count5                  <=  '0;
+                        end
+                    else
+                        case(lpddr2_init_state)
+                            0   : if (start_lpddr2_init) lpddr2_init_state <=  1;
+                            // start LPDDR2 initialization sequence
+                            //                   address    data         next_state
+                            1   : lpddr2_init_write_task_rw ('h800     ,'h0         ,2  );
+                            2   : lpddr2_init_write_task_rw ('h500     ,'hfe        ,3  );
+                            3   : lpddr2_init_write_task_rw ('h200     ,'h10        ,4  );
+                            4   : lpddr2_init_write_task_rw ('h300     ,'h4c        ,15  );
+                            15  : 
+                                begin
+                                    if (&count4)
+                                        begin
+                                            count4 <=  0;
+                                            if (&count5)
+                                                begin
+                                                    count5 <= 0;
+                                                    lpddr2_init_state   <=  5;
+                                                end
+                                            else
+                                                count5 <=  count5 + 1'b1;
+                                        end
+                                    else
+                                        count4 <=  count4 + 1'b1;
+                                end 
+                            5   : lpddr2_init_write_task_rw ('h0       ,'h4c        ,12 ); // CKE goes high
+                            12  : //200us delay
+                                begin
+                                    if (&count4)
+                                        begin
+                                            count4            <=  0;
+                                            if (&count5)
+                                                begin
+                                                    lpddr2_init_state   <=  6;
+                                                    count5            <=  0;
+                                                end
+                                            else
+                                                count5      <=  count5 + 1'b1;
+                                        end
+                                    else
+                                        count4      <=  count4 + 1'b1;
+                                end
+                            6   : lpddr2_init_write_task_rw ('h0       ,'hd         ,13 ); // MRW reset
+                            13  : //10us delay
+                                begin
+                                    if (count4 == 100)
+                                        begin
+                                            count4            <=  0;
+                                            if (count5 == 10)
+                                                begin
+                                                    lpddr2_init_state   <=  7;
+                                                    count5            <=  0;
+                                                end
+                                            else
+                                                count5      <=  count5 + 1'b1;
+                                        end
+                                    else
+                                        count4      <=  count4 + 1'b1;
+                                end
+                            7   : lpddr2_init_write_task_rw ('h0       ,'hb         ,14 ); // MRW MR10 ZQcal FF
+                            14  : //1us delay
+                                begin
+                                    if (count4 == 100)
+                                        begin
+                                            lpddr2_init_state   <=  8;
+                                            count4            <=  0;
+                                        end
+                                    else
+                                        count4      <=  count4 + 1'b1;
+                                end
+                            8   : lpddr2_init_write_task_rw ('h0       ,'h3         ,9  ); // MRW MR1
+                            9   : lpddr2_init_write_task_rw ('h0       ,'h7         ,10 ); // MRW MR2
+                            10  : lpddr2_init_write_task_rw ('h0       ,'h9         ,11 ); // MRW MR3
+                            // end of LPDDR2 initialization sequence
+                            11  :
+                                begin
+                                    if (cal_init_req)
+                                        begin
+                                            lpddr2_init_done      <=  0;
+                                            lpddr2_init_state     <=  0;
+                                        end
+                                    else
+                                        lpddr2_init_done    <=  1;
+                                end
+                        endcase
+                end
+            
+        end
+    else
+        begin
+            assign  lpddr2_init_done        =   0;
+            assign  lpddr2_init_address     =   '0;
+            assign  lpddr2_init_write       =   0;
+            assign  lpddr2_init_writedata   =   '0;
+        end
+endgenerate
+        
+    logic [4:0]    write_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       write_address;
+	logic                              write_write;
+	logic [AVL_DATA_WIDTH - 1:0]       write_writedata;
+	logic [8:0]    count3;
+
+    always_ff @(posedge clk, negedge reset_n)
+        begin
+            if (!reset_n)
+                begin
+                    write_state       <=  0;
+                    write_done        <=  0;
+                    write_address     <=  '0;
+                    write_write       <=  0;
+                    write_writedata   <=  '0;
+                    count3            <=  '0;
+                end
+            else
+                case(write_state)
+                    0   : if (start_write) write_state <=  1;
+                    // precharge and activate
+                    1   :
+                        begin
+                            if (&count3)
+                                begin
+                                    write_state <=  2;
+                                    count3      <=  0;
+                                end
+                            else
+                                count3      <=  count3 + 1'b1;
+                        end
+                    2   : write_write_task_rw ('h0       ,PRE_N_ACT_1 ,3  );
+                    3   : write_write_task_rw ('h200     ,PRE_N_ACT_2 ,4  );
+                    4   : write_write_task_rw ('h300     ,PRE_N_ACT_3 ,5  );
+                    5   : write_write_task_rw ('h201     ,PRE_N_ACT_4 ,6  );
+                    6   : write_write_task_rw ('h301     ,PRE_N_ACT_5 ,7  );
+                    7   : write_write_task_rw ('h0       ,PRE_N_ACT_6 ,8  );
+                    
+                    // guaranteed write
+                    8   : write_write_task_rw ('h200     ,GRNTEE_WR_1 ,9  );
+                    9   : write_write_task_rw ('h300     ,GRNTEE_WR_2 ,10 );
+                    10  : write_write_task_rw ('h201     ,GRNTEE_WR_3 ,11 );
+                    11  : write_write_task_rw ('h301     ,GRNTEE_WR_4 ,12 );
+                    12  : write_write_task_rw ('h202     ,GRNTEE_WR_5 ,13 );
+                    13  : write_write_task_rw ('h302     ,GRNTEE_WR_6 ,14 );
+                    14  : write_write_task_rw ('h203     ,GRNTEE_WR_7 ,15 );
+                    15  : write_write_task_rw ('h303     ,GRNTEE_WR_8 ,16 );
+                    16  : write_write_task_rw ('h0       ,GRNTEE_WR_9 ,17 );
+                    17  :
+                        begin
+                            if (cal_init_req)
+                                begin
+                                    write_done      <=  0;
+                                    write_state     <=  0;
+                                end
+                            else
+                                write_done    <=  1;
+                        end
+                endcase
+        end
+        
+task write_write_task_rw;
+    input [AVL_ADDR_WIDTH - 1:0] task_address;
+    input [AVL_DATA_WIDTH - 1:0] data;
+    input [4:0] next_state;
+    
+    begin
+        write_write       <=  1;
+        write_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+        write_writedata   <=  data;
+        if (write_write && !waitrequest)
+            begin
+                write_write       <=  0;
+                write_address     <=  '0;
+                write_writedata   <=  '0;
+                write_state   <=  next_state;
+            end
+    end
+endtask
+    
+    logic [3:0]    user_mr_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       user_mr_address;
+	logic                              user_mr_write;
+	logic [AVL_DATA_WIDTH - 1:0]       user_mr_writedata;
+
+    always_ff @(posedge clk, negedge reset_n)
+        begin
+            if (!reset_n)
+                begin
+                    user_mr_state       <=  0;
+                    user_mr_done        <=  0;
+                    user_mr_address     <=  '0;
+                    user_mr_write       <=  0;
+                    user_mr_writedata   <=  '0;
+                end
+            else
+                case(user_mr_state)
+                    0   : if (start_user_mr) user_mr_state <=  1;
+                    // precharge and activate
+                    1   :
+                        begin
+                            if (HPS_PROTOCOL == "DDR3")
+                                user_mr_state   <=  2;
+                            else if (HPS_PROTOCOL == "DDR2")
+                                user_mr_state   <=  7;
+                            else // LPDDR2
+                                user_mr_state   <=  11;
+                        end
+                    
+                    // DDR3 user MR start
+                    2   : user_mr_write_task_rw ('h0       ,'h14        ,3  );
+                    3   : user_mr_write_task_rw ('h0       ,'h7         ,4  );
+                    4   : user_mr_write_task_rw ('h0       ,'h9         ,5  );
+                    5   : user_mr_write_task_rw ('h0       ,'h5         ,6  );
+                    6   : user_mr_write_task_rw ('h0       ,'hd         ,14 );
+                    // DDR3 user MR ends
+                    
+                    // DDR2 user MR start
+                    7   : user_mr_write_task_rw ('h0       ,'hd         ,8  );
+                    8   : user_mr_write_task_rw ('h0       ,'hf         ,9  );
+                    9   : user_mr_write_task_rw ('h0       ,'h9         ,10 );
+                    10  : user_mr_write_task_rw ('h0       ,'h3         ,14 );
+                    // DDR2 user MR ends
+                    
+                    // LPDDR2 user MR start
+                    11  : user_mr_write_task_rw ('h0       ,'h5         ,12 );
+                    12  : user_mr_write_task_rw ('h0       ,'h7         ,13 );
+                    13  : user_mr_write_task_rw ('h0       ,'h9         ,14 );
+                    // LPDDR2 user MR ends
+                    14  :
+                        begin
+                            if (cal_init_req)
+                                begin
+                                    user_mr_done      <=  0;
+                                    user_mr_state     <=  0;
+                                end
+                            else
+                                user_mr_done    <=  1;
+                        end
+                endcase
+        end
+        
+task user_mr_write_task_rw;
+    input [AVL_ADDR_WIDTH - 1:0] task_address;
+    input [AVL_DATA_WIDTH - 1:0] data;
+    input [3:0] next_state;
+    
+    begin
+        user_mr_write       <=  1;
+        user_mr_address     <=  RW_MGR_BASE[AVL_ADDR_WIDTH - 1:0] + {task_address[AVL_ADDR_WIDTH - 3:0],2'b0};
+        user_mr_writedata   <=  data;
+        if (user_mr_write && !waitrequest)
+            begin
+                user_mr_write       <=  0;
+                user_mr_address     <=  '0;
+                user_mr_writedata   <=  '0;
+                user_mr_state   <=  next_state;
+            end
+    end
+endtask
+    
+    logic [3:0]    pd_state;
+	logic [AVL_ADDR_WIDTH - 1:0]       pd_address;
+	logic                              pd_write;
+	logic                              pd_read;
+	logic [AVL_DATA_WIDTH - 1:0]       pd_writedata;
+	logic [3:0]    lock_count;
+	logic                              pd_down_r;
+	logic                              pd_up_r;
+	logic [3:0]    cal_chk_count;
+
+    always_ff @(posedge clk, negedge reset_n)
+        begin
+            if (!reset_n)
+                begin
+                    pd_down_r      <=  0;
+                    pd_up_r        <=  0;
+                end
+            else
+                if (pd_state == 2 || pd_state == 6)
+                    begin
+                        pd_down_r   <=  pd_down;
+                        pd_up_r     <=  pd_up;
+                    end
+        end
+                    
+    always_ff @(posedge clk, negedge reset_n)
+        begin
+            if (!reset_n)
+                begin
+                    pd_state       <=  0;
+                    pd_address     <=  '0;
+                    pd_write       <=  0;
+                    pd_read        <=  0;
+                    pd_writedata   <=  '0;
+                    pd_reset_n     <=  0;
+                    pd_ack         <=  0;
+                    lock_count     <=  '0;
+                    cal_init_req   <=  0;
+                    cal_chk_count  <=  '0;
+                end
+            else
+                case(pd_state)
+                    0   :
+                        begin
+                            if (pd_start && !cal_init_req)
+                                begin
+                                    pd_reset_n  <=  1;
+                                    pd_state    <=  1;
+                                end
+                            
+                            if (cal_init_req)
+                                cal_init_req    <=  0;
+                        end
+                    1   :
+                        begin
+                            pd_ack  <=  0;
+                            if (pd_down)
+                                pd_write_task_tracking_clock (0,2);
+                            else if (pd_up)
+                                pd_write_task_tracking_clock (1,2);
+                        end
+                    2   :
+                        begin
+                            if (pd_down_r && pd_up)
+                                lock_count  <=  lock_count + 1'b1;
+                            else if (pd_up_r && pd_down)
+                                lock_count  <=  lock_count + 1'b1;
+                            
+                            pd_ack  <=  1;
+                            pd_state    <=  3;
+                        end
+                    3   :
+                        begin
+                            if (lock_count >= 8)
+                                pd_state    <=  4;
+                            else
+                                pd_state    <=  1;
+                        end
+                    4   :
+                        begin
+                            pd_ack  <=  0;
+                            if (pd_down)
+                                begin
+                                    if (pd_down_r || DISABLE_FILTER)
+                                        begin
+                                            if (DISABLE_PD)
+                                                pd_state    <=  5;
+                                            else
+                                                pd_write_task_capture_clock (0,5);
+                                        end
+                                    else
+                                        pd_state    <=  5;
+                                end
+                            else if (pd_up)
+                                begin
+                                    if (pd_up_r || DISABLE_FILTER)
+                                        begin
+                                            if (DISABLE_PD)
+                                                pd_state    <=  5;
+                                            else
+                                                pd_write_task_capture_clock (1,5);
+                                        end
+                                    else
+                                        pd_state    <=  5;
+                                end
+                        end
+                    5   :
+                        begin
+                            if (pd_down)
+                                pd_write_task_tracking_clock (0,6);
+                            else if (pd_up)
+                                pd_write_task_tracking_clock (1,6);
+                        end
+                    6   :
+                        begin
+                            pd_ack      <=  1;
+                            if (cal_chk_count == 4'd10)
+                                begin
+                                    cal_chk_count   <=  '0;
+                                    pd_state    <=  7;
+                                end
+                            else
+                                begin
+                                    cal_chk_count   <=  cal_chk_count + 1'b1;
+                                    pd_state    <=  8;
+                                end
+                        end
+                    7   :
+                        begin
+                            pd_read    <=  1;
+                            pd_address <=  PLL_MGR_BASE[AVL_ADDR_WIDTH - 1:0]+{2'd2,2'b00}; 
+                            if (pd_read && !waitrequest)
+                                begin
+                                    pd_read       <=  0;
+                                    pd_address    <=  '0;
+                                    if (readdata[0] == 1)
+                                        begin
+                                            pd_state        <=  0;
+                                            cal_init_req    <=  1;
+                                            lock_count      <=  0;
+                                        end
+                                    else
+                                        pd_state      <=  8;
+                                end
+                        end
+                    8   :
+                        pd_state    <=  4;
+                endcase
+        end
+
+task pd_write_task_tracking_clock;
+    input data;
+    input [2:0] next_state;
+    
+    begin
+        pd_write       <=  1;
+        pd_address     <=  PLL_MGR_BASE[AVL_ADDR_WIDTH - 1:0]+{1'b1,2'b00}; // tracking clock
+        pd_writedata   <=  data;
+        if (pd_write && !waitrequest)
+            begin
+                pd_write       <=  0;
+                pd_address     <=  '0;
+                pd_writedata   <=  '0;
+                pd_state   <=  next_state;
+            end
+    end
+endtask
+
+task pd_write_task_capture_clock;
+    input data;
+    input [2:0] next_state;
+    
+    begin
+        pd_write       <=  1;
+        pd_address     <=  PLL_MGR_BASE[AVL_ADDR_WIDTH - 1:0];
+        pd_writedata   <=  data;
+        if (pd_write && !waitrequest)
+            begin
+                pd_write       <=  0;
+                pd_address     <=  '0;
+                pd_writedata   <=  '0;
+                pd_state   <=  next_state;
+            end
+    end
+endtask
+
+	assign    address        =    main_address | ddr3_init_address | ddr2_init_address | lpddr2_init_address | write_address | user_mr_address | pd_address;
+	assign    write          =    main_write | ddr3_init_write | ddr2_init_write | lpddr2_init_write | write_write | user_mr_write | pd_write;
+	assign    writedata      =    main_writedata | ddr3_init_writedata | ddr2_init_writedata | lpddr2_init_writedata | write_writedata | user_mr_writedata | pd_writedata;
+	assign    read           =    main_read | pd_read;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sequencer_phy_mgr.sv b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_phy_mgr.sv
new file mode 100644
index 0000000..2cfb056
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_phy_mgr.sv
@@ -0,0 +1,537 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******
+// phy_mgr
+// ******
+//
+// PHY Manager
+//
+// General Description
+// -------------------
+//
+// This component allows a way for a master on the Avalon bus to
+// control various aspects of the PHY connection.
+//
+// Architecture
+// ------------
+//
+// The PHY Manager is organized as follows
+//    - Avalon Interface: it's a Memory-Mapped interface to the Avalon
+//      Bus.
+//    - Register File: it's a set of registers used to control the functioning
+//		of the PHY. This register file can be read and written from the Avalon
+//      interface and can only be read by the PHY.
+//	  - Command Issue: a write to this port runs a particular sequence at PHY
+//		speeds. 
+//
+// Address Space
+// -------------
+//
+// The address space is divided into 2 identical portions.
+// The most significant bit select one of the internal components.
+// The rest of the address word (whose size depend on parameterization)
+// is used to access a specific location of the selected component.
+//
+// 0 - Instruction/Configuration Address.
+//     Data written to this component is intepreted as a command.
+//	   Data read from this component returns various parameters specific
+//	   to the PHY manager.
+//     During read, case (lower address bits)
+//			000: returns MAX_LATENCY_COUNT_WIDTH
+//			001: returns AFI_MAX_WRITE_LATENCY_COUNT_WIDTH
+//			010: returns AFI_MAX_READ_LATENCY_COUNT_WIDTH
+//     During write, case (lower address bits)
+//			000: increments vfifo_fr specified by word being written
+//			001: increments vfifo_hr specified by word being written
+//			010: resets the fifo.
+//			(the following only used by quarter-rate PHY)
+//			011: asserts vfifo_fr and vfifo_hr
+//			100: asserts vfifo_qr
+//
+// 1 - Register File.
+//	   8 registers controlling various aspects of the PHY are provided.
+//	   The lowest three bits are used to address the specific register
+//	   begin read/written from/to.
+//	   During reads/writes, case (lower address bits)
+//			000: returns/sets read latency counter
+//			001: returns/sets mem stable bit.
+//
+
+`timescale 1 ps / 1 ps
+
+module sequencer_phy_mgr (
+	// Avalon Interface
+	
+	avl_clk,
+	avl_reset_n,
+	avl_address,
+	avl_write,
+	avl_writedata,
+	avl_read,
+	avl_readdata,
+	avl_waitrequest,
+
+	// PHY control
+
+	phy_clk,
+	phy_reset_n,
+	phy_read_latency_counter,
+	phy_read_increment_vfifo_fr,
+	phy_read_increment_vfifo_hr,
+	phy_read_increment_vfifo_qr,
+	phy_reset_mem_stable,
+	phy_afi_wlat,
+	phy_afi_rlat,
+	phy_mux_sel,
+	phy_cal_success,
+	phy_cal_fail,
+	phy_cal_debug_info,
+	phy_read_fifo_reset,
+	phy_vfifo_rd_en_override,
+	phy_read_fifo_q,
+	phy_write_fr_cycle_shifts,
+	calib_skip_steps
+);
+
+	parameter AVL_DATA_WIDTH = 32;
+	parameter AVL_ADDR_WIDTH = 13;
+
+	parameter MAX_LATENCY_COUNT_WIDTH = 5;
+	parameter MEM_IF_READ_DQS_WIDTH = 1;
+	parameter MEM_IF_WRITE_DQS_WIDTH = 1;
+	parameter AFI_DQ_WIDTH = 64;
+	parameter AFI_DEBUG_INFO_WIDTH = 32;
+	parameter AFI_MAX_WRITE_LATENCY_COUNT_WIDTH = 5;
+	parameter AFI_MAX_READ_LATENCY_COUNT_WIDTH	= 5;
+	parameter CALIB_VFIFO_OFFSET = 10;
+	parameter CALIB_LFIFO_OFFSET = 3;
+	parameter CALIB_REG_WIDTH = 8;
+	parameter READ_VALID_FIFO_SIZE = 16;
+	parameter MEM_T_WL = 1;
+	parameter MEM_T_RL = 2;
+	parameter CTL_REGDIMM_ENABLED = 0;
+	parameter NUM_WRITE_FR_CYCLE_SHIFTS = 0;
+	parameter DEVICE_FAMILY = "";
+	parameter VFIFO_CONTROL_WIDTH_PER_DQS = 1;
+	
+	localparam  WRITE_FR_CYCLE_SHIFT_WIDTH = 2*MEM_IF_WRITE_DQS_WIDTH;
+	localparam  AFI_GROUP_WRITE_LATENCY_COUNT_WIDTH = (AFI_MAX_WRITE_LATENCY_COUNT_WIDTH <= 6) ? AFI_MAX_WRITE_LATENCY_COUNT_WIDTH : AFI_MAX_WRITE_LATENCY_COUNT_WIDTH/MEM_IF_WRITE_DQS_WIDTH;
+	
+	input avl_clk;
+	input avl_reset_n;
+	input [AVL_ADDR_WIDTH - 1:0] avl_address;
+	input avl_write;
+	input [AVL_DATA_WIDTH - 1:0] avl_writedata;
+	input avl_read;
+	output [AVL_DATA_WIDTH - 1:0] avl_readdata;
+	output avl_waitrequest;
+
+	input phy_clk;
+	input phy_reset_n;
+	output [MAX_LATENCY_COUNT_WIDTH - 1:0] phy_read_latency_counter;
+	output [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_fr;
+	output [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_hr;
+	output [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_qr;
+	output phy_reset_mem_stable;
+	output [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH - 1:0] phy_afi_wlat;
+	output [AFI_MAX_READ_LATENCY_COUNT_WIDTH - 1:0] phy_afi_rlat;
+	output [WRITE_FR_CYCLE_SHIFT_WIDTH - 1:0] phy_write_fr_cycle_shifts;
+	output phy_mux_sel;
+	output phy_cal_success;
+	output phy_cal_fail;
+	output [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
+	output [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_fifo_reset;
+	output [MEM_IF_READ_DQS_WIDTH - 1:0] phy_vfifo_rd_en_override;
+	input  [AFI_DQ_WIDTH-1:0] phy_read_fifo_q;
+
+	input [CALIB_REG_WIDTH - 1:0] calib_skip_steps;
+	
+	reg avl_waitrequest;
+	reg [AVL_DATA_WIDTH - 1:0] avl_readdata_r;
+	reg [AVL_DATA_WIDTH - 1:0] avl_readdata;
+
+	reg avl_rfile_wr;
+	reg avl_issue_wr;
+	reg [VFIFO_CONTROL_WIDTH_PER_DQS*MEM_IF_READ_DQS_WIDTH - 1:0] avl_read_increment_vfifo_fr;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] avl_read_increment_vfifo_hr;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] avl_read_increment_vfifo_qr;	
+	reg avl_read_fifo_reset;
+	
+	reg [MAX_LATENCY_COUNT_WIDTH - 1:0] phy_read_latency_counter;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_fr;
+	reg [VFIFO_CONTROL_WIDTH_PER_DQS*MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_fr_pre_combined /* synthesis preserve = 1 */;
+	wire [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_fr_combined /* synthesis keep = 1 */;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_hr;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_increment_vfifo_qr;	
+	reg phy_reset_mem_stable;
+	reg [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH - 1:0] phy_afi_wlat;
+	reg [AFI_MAX_READ_LATENCY_COUNT_WIDTH - 1:0] phy_afi_rlat;
+	reg [WRITE_FR_CYCLE_SHIFT_WIDTH - 1:0] phy_write_fr_cycle_shifts;
+	reg phy_mux_sel;
+	reg phy_cal_success;
+	reg phy_cal_fail;
+	reg [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] phy_read_fifo_reset;
+	reg [MEM_IF_READ_DQS_WIDTH - 1:0] phy_vfifo_rd_en_override;
+	reg phy_done;
+	
+	wire [32 - 1:0] num_fr_cycle_shifts;
+	assign num_fr_cycle_shifts = NUM_WRITE_FR_CYCLE_SHIFTS;
+	
+	function integer ceil_log2;
+		input integer value;
+		begin
+			value = value - 1;
+			for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
+				value = value >> 1;
+		end
+	endfunction	
+	
+	localparam RFILE_ADDR_WIDTH = (NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 3 : ((AFI_MAX_WRITE_LATENCY_COUNT_WIDTH <= 6) ? ceil_log2(7 + MEM_IF_WRITE_DQS_WIDTH + 1) : ceil_log2(7 + 2*MEM_IF_WRITE_DQS_WIDTH + 1));
+	
+	integer i;
+
+	typedef enum int unsigned {
+		STATE_AVL_IDLE,
+		STATE_AVL_EXEC,
+		STATE_AVL_DONE
+	} STATE_AVL_T;
+
+	STATE_AVL_T state_avl_curr;
+
+	typedef enum int unsigned {
+		STATE_PHY_IDLE,
+		STATE_PHY_DONE
+	} STATE_PHY_T;
+
+	STATE_PHY_T state_phy_curr;
+
+	// the register file
+	
+	reg [AVL_DATA_WIDTH - 1:0] rfile [0:(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 7 : ((AFI_MAX_WRITE_LATENCY_COUNT_WIDTH <= 6) ? 7 + MEM_IF_WRITE_DQS_WIDTH : 7+2*MEM_IF_WRITE_DQS_WIDTH)];
+	
+	// register file selected
+	
+	wire sel_rfile, sel_rfile_wr, sel_rfile_rd;
+	
+	// command issue selected
+	
+	wire sel_any;
+	wire sel_issue, sel_issue_wr, sel_issue_rd;
+	
+	assign sel_rfile = avl_address[AVL_ADDR_WIDTH - 1];
+	assign sel_rfile_wr = sel_rfile & avl_write;
+	assign sel_rfile_rd = sel_rfile & avl_read;
+	
+	assign sel_issue = ~avl_address[AVL_ADDR_WIDTH - 1];
+	assign sel_issue_wr = sel_issue & avl_write;
+	assign sel_issue_rd = sel_issue & avl_read;
+	
+	assign sel_any = sel_rfile_wr | sel_rfile_rd | sel_issue_wr | sel_issue_rd;
+	
+	// State machine, AVALON side
+		
+	always_ff @ (posedge avl_clk or negedge avl_reset_n) begin
+		integer reg_file_index;
+		if (avl_reset_n == 0) begin
+			state_avl_curr <= STATE_AVL_IDLE;
+
+			avl_readdata_r <= '0;
+			avl_rfile_wr <= 0;
+			avl_issue_wr <= 0;
+			avl_read_increment_vfifo_fr <= '0;
+			avl_read_increment_vfifo_hr <= '0;
+			avl_read_increment_vfifo_qr <= '0;
+			avl_read_fifo_reset <= 0;
+
+			rfile[0][MAX_LATENCY_COUNT_WIDTH - 1:0] <= '0;
+			rfile[1][0] <= 0;
+			rfile[2][0] <= 1;
+			rfile[3][1:0] <= '0;
+			rfile[4] <= '0;
+			rfile[5][0] <= 0;
+			rfile[6] <= 0;
+			rfile[7] <= 0;
+			if (NUM_WRITE_FR_CYCLE_SHIFTS == -1) begin
+				for (reg_file_index = 8; reg_file_index < 8 + MEM_IF_WRITE_DQS_WIDTH; reg_file_index++) begin
+					rfile[reg_file_index] <= '0;
+				end
+				if (AFI_MAX_WRITE_LATENCY_COUNT_WIDTH > 6) begin
+					for (reg_file_index = 8 + MEM_IF_WRITE_DQS_WIDTH; reg_file_index < 8 + 2*MEM_IF_WRITE_DQS_WIDTH; reg_file_index++) begin
+						rfile[reg_file_index] <= '0;
+					end
+				end
+			end 
+		end else begin
+			case (state_avl_curr)
+			STATE_AVL_IDLE: begin
+				if (sel_rfile_rd) begin
+					// NIOS is reading from the register file
+					
+					state_avl_curr <= STATE_AVL_DONE;
+					
+					avl_readdata_r <= '0 /*rfile[avl_address[RFILE_ADDR_WIDTH - 1:0]] */; // removing address file access for further optimization.
+				end else if (sel_issue_rd) begin
+					// NIOS is reading parameters
+
+					state_avl_curr <= STATE_AVL_DONE;
+					
+					case (avl_address[3:0])
+					4'b0000: avl_readdata_r <= MAX_LATENCY_COUNT_WIDTH;
+					4'b0001: avl_readdata_r <= AFI_MAX_WRITE_LATENCY_COUNT_WIDTH;
+					4'b0010: avl_readdata_r <= AFI_MAX_READ_LATENCY_COUNT_WIDTH;
+					`ifndef SYNTH_FOR_SIM
+					//synthesis translate_off
+					`endif
+					// extra bit indicates we are in the simulator
+					4'b0011: avl_readdata_r <= {{(AVL_DATA_WIDTH-CALIB_REG_WIDTH-1){1'b0}},1'b1,calib_skip_steps};
+					`ifndef SYNTH_FOR_SIM
+					//synthesis translate_on
+					`endif
+					`ifndef SYNTH_FOR_SIM
+					//synthesis read_comments_as_HDL on
+					`endif
+					`ifndef SYNTH_FOR_SIM
+					// synthesis read_comments_as_HDL off
+					`endif
+					// 4'b0011: avl_readdata_r <= {{(AVL_DATA_WIDTH-CALIB_REG_WIDTH){1'b0}},calib_skip_steps};
+					4'b0100: avl_readdata_r <= CALIB_VFIFO_OFFSET;
+					4'b0101: avl_readdata_r <= CALIB_LFIFO_OFFSET;
+					4'b0110:
+						if (CTL_REGDIMM_ENABLED == 1)
+							avl_readdata_r <= 1;
+						else
+							avl_readdata_r <= 0;
+					4'b0111: avl_readdata_r <= MEM_T_WL;
+					4'b1000: avl_readdata_r <= MEM_T_RL;
+					4'b1001: avl_readdata_r <= READ_VALID_FIFO_SIZE;
+					endcase
+				end else if (sel_rfile_wr) begin
+					// NIOS is writing into the register file.
+					// Need to issue a command the PHY side to pick up changes.
+
+					state_avl_curr <= STATE_AVL_EXEC;
+
+					avl_rfile_wr <= 1;
+					
+					rfile[avl_address[RFILE_ADDR_WIDTH - 1:0]] <= avl_writedata;
+				end else if (sel_issue_wr) begin
+					// NIOS is asking for a particular command to be issued
+					
+					state_avl_curr <= STATE_AVL_EXEC;
+					
+					avl_issue_wr <= 1;
+					
+					case (avl_address[2:0])
+					3'b000:
+						if (avl_writedata == 8'b11111111) begin
+							avl_read_increment_vfifo_fr <= {(MEM_IF_READ_DQS_WIDTH*VFIFO_CONTROL_WIDTH_PER_DQS){1'b1}};
+						end else begin
+							avl_read_increment_vfifo_fr[avl_writedata] <= 1;
+						end
+					3'b001:
+						if (avl_writedata == 8'b11111111) begin
+							avl_read_increment_vfifo_hr <= {MEM_IF_READ_DQS_WIDTH{1'b1}};
+						end else begin
+							avl_read_increment_vfifo_hr[avl_writedata] <= 1;
+						end
+					3'b010:
+						avl_read_fifo_reset <= 1;
+					3'b011:
+						if (avl_writedata == 8'b11111111) begin
+							avl_read_increment_vfifo_fr <= {(MEM_IF_READ_DQS_WIDTH*VFIFO_CONTROL_WIDTH_PER_DQS){1'b1}};
+							avl_read_increment_vfifo_hr <= {MEM_IF_READ_DQS_WIDTH{1'b1}};
+						end else begin
+							avl_read_increment_vfifo_fr[avl_writedata] <= 1;
+							avl_read_increment_vfifo_hr[avl_writedata] <= 1;
+						end
+					3'b100:
+						if (avl_writedata == 8'b11111111) begin
+							avl_read_increment_vfifo_qr <= {MEM_IF_READ_DQS_WIDTH{1'b1}};
+						end else begin
+							avl_read_increment_vfifo_qr[avl_writedata] <= 1;
+						end
+					endcase
+				end
+			end
+			STATE_AVL_EXEC: begin
+				// We are currently executing a command on the PHY side.
+				// Wait until it is done.
+				
+				if (phy_done) begin
+					state_avl_curr <= STATE_AVL_DONE;
+					
+					// Need to bring all the command lines down to prevent
+					// the PHY from reexecuting the same command.
+					
+					avl_rfile_wr <= 0;
+					avl_issue_wr <= 0;
+					avl_read_increment_vfifo_fr <= '0;
+					avl_read_increment_vfifo_hr <= '0;
+					avl_read_increment_vfifo_qr <= '0;
+					avl_read_fifo_reset <= 0;
+				end
+			end
+			STATE_AVL_DONE: begin
+				// Done operation. During this clock waitrequest is de-asserted.
+				// Return to idle state next clock.
+				
+				state_avl_curr <= STATE_AVL_IDLE;
+			end
+			endcase
+		end
+	end
+
+	// State machine, PHY side
+		
+	always_ff @ (posedge phy_clk or negedge phy_reset_n) begin
+		integer reg_file_index;
+		integer offset;
+		if (phy_reset_n == 0) begin
+			state_phy_curr <= STATE_PHY_IDLE;
+
+			phy_done <= 0;
+			phy_read_increment_vfifo_fr_pre_combined <= '0;
+			phy_read_increment_vfifo_hr <= '0;
+			phy_read_increment_vfifo_qr <= '0;
+			phy_read_fifo_reset <= '0;
+			phy_reset_mem_stable <= 0;
+			phy_mux_sel <= 1;
+			phy_cal_success <= 0;
+			phy_cal_fail <= 0;
+			phy_cal_debug_info <= '0;
+			phy_vfifo_rd_en_override <= '0;
+			phy_write_fr_cycle_shifts <= '0;
+			phy_afi_rlat <= '0;	
+			phy_afi_wlat <= '0;
+			phy_read_latency_counter <= '0;
+		end else begin
+			case (state_phy_curr)
+			STATE_PHY_IDLE: begin
+				// Waiting for a command to arrive.
+				
+				if (avl_rfile_wr) begin
+					// Register file was just changed on the AVL side. Pick
+					// up changes.
+					
+					state_phy_curr <= STATE_PHY_DONE;
+					
+					phy_done <= 1;
+					
+					phy_read_latency_counter <= rfile[0][MAX_LATENCY_COUNT_WIDTH - 1:0];
+					phy_reset_mem_stable <= rfile[1][0];
+					phy_mux_sel <= rfile[2][0];
+					phy_cal_success <= rfile[3][0];
+					phy_cal_fail <= rfile[3][1];
+					phy_cal_debug_info <= rfile[4][AFI_DEBUG_INFO_WIDTH - 1:0];
+					phy_vfifo_rd_en_override <= {(MEM_IF_READ_DQS_WIDTH){rfile[5][0]}};
+					if (NUM_WRITE_FR_CYCLE_SHIFTS == -1) begin
+						for (reg_file_index = 8; reg_file_index < 8 + MEM_IF_WRITE_DQS_WIDTH; reg_file_index++) begin
+							offset = (reg_file_index - 8)*WRITE_FR_CYCLE_SHIFT_WIDTH/MEM_IF_WRITE_DQS_WIDTH;
+							phy_write_fr_cycle_shifts[offset+:WRITE_FR_CYCLE_SHIFT_WIDTH/MEM_IF_WRITE_DQS_WIDTH] <= rfile[reg_file_index][WRITE_FR_CYCLE_SHIFT_WIDTH/MEM_IF_WRITE_DQS_WIDTH - 1:0];
+						end
+						if (AFI_MAX_WRITE_LATENCY_COUNT_WIDTH > 6) begin
+							for (reg_file_index = 8 + MEM_IF_WRITE_DQS_WIDTH; reg_file_index < 8 + 2*MEM_IF_WRITE_DQS_WIDTH; reg_file_index++) begin
+								offset = (reg_file_index - 8 - MEM_IF_WRITE_DQS_WIDTH)*AFI_GROUP_WRITE_LATENCY_COUNT_WIDTH;
+								phy_afi_wlat[offset+:AFI_GROUP_WRITE_LATENCY_COUNT_WIDTH] <= rfile[reg_file_index][AFI_GROUP_WRITE_LATENCY_COUNT_WIDTH - 1:0];
+							end
+						end else begin
+							phy_afi_wlat <= rfile[6][AFI_MAX_WRITE_LATENCY_COUNT_WIDTH - 1:0];
+						end
+					end else begin
+						for (reg_file_index = 0; reg_file_index < MEM_IF_WRITE_DQS_WIDTH; reg_file_index++) begin
+							offset = reg_file_index*WRITE_FR_CYCLE_SHIFT_WIDTH/MEM_IF_WRITE_DQS_WIDTH;
+							phy_write_fr_cycle_shifts[offset+:WRITE_FR_CYCLE_SHIFT_WIDTH/MEM_IF_WRITE_DQS_WIDTH] <= num_fr_cycle_shifts[1:0];
+						end
+						phy_afi_wlat <= rfile[6][AFI_MAX_WRITE_LATENCY_COUNT_WIDTH - 1:0];
+					end
+					phy_afi_rlat <= rfile[7][AFI_MAX_READ_LATENCY_COUNT_WIDTH - 1:0];
+				end else if (avl_issue_wr) begin
+					// NIOS just issued a command to be run.
+					
+					state_phy_curr <= STATE_PHY_DONE;
+					
+					phy_done <= 1;
+					
+					phy_read_increment_vfifo_fr_pre_combined <= avl_read_increment_vfifo_fr;
+					phy_read_increment_vfifo_hr <= avl_read_increment_vfifo_hr;
+					phy_read_increment_vfifo_qr <= avl_read_increment_vfifo_qr;
+					phy_read_fifo_reset <= {(MEM_IF_READ_DQS_WIDTH){avl_read_fifo_reset}};
+				end
+			end
+			STATE_PHY_DONE: begin
+				phy_read_increment_vfifo_fr_pre_combined <= '0;
+				phy_read_increment_vfifo_hr <= '0;
+				phy_read_increment_vfifo_qr <= '0;
+				phy_read_fifo_reset <= '0;
+
+				if (~avl_rfile_wr && ~avl_issue_wr) begin
+					state_phy_curr <= STATE_PHY_IDLE;
+					phy_done <= 0;
+				end
+			end
+			endcase
+		end
+	end
+	
+	// Do not modify the following logic. This is used by the fitter to identify VFIFO control structures in Arria V
+	generate
+	if (DEVICE_FAMILY == "ARRIAV" && VFIFO_CONTROL_WIDTH_PER_DQS != 1)
+	begin
+		genvar dqs_index;
+		for (dqs_index=0; dqs_index < MEM_IF_READ_DQS_WIDTH; dqs_index=dqs_index+1)
+		begin : vfifo_fb56390_gen
+			wire [5:0] phy_read_increment_vfifo_fr_pre_combined_ext;
+			assign phy_read_increment_vfifo_fr_pre_combined_ext = {2'b00, phy_read_increment_vfifo_fr_pre_combined[(dqs_index*VFIFO_CONTROL_WIDTH_PER_DQS+VFIFO_CONTROL_WIDTH_PER_DQS-1):dqs_index*VFIFO_CONTROL_WIDTH_PER_DQS]};
+			// synthesis read_comments_as_HDL on
+			// arriav_lcell_comb vfifo_fb56390
+			// (
+				// .dataa(phy_read_increment_vfifo_fr_pre_combined_ext[0]),
+				// .datab(phy_read_increment_vfifo_fr_pre_combined_ext[1]),
+				// .datac(phy_read_increment_vfifo_fr_pre_combined_ext[2]),
+				// .datad(phy_read_increment_vfifo_fr_pre_combined_ext[3]),
+				// .datae(phy_read_increment_vfifo_fr_pre_combined_ext[4]),
+				// .dataf(phy_read_increment_vfifo_fr_pre_combined_ext[5]),
+				// .combout(phy_read_increment_vfifo_fr_combined[dqs_index])
+			// );
+			// defparam vfifo_fb56390.lut_mask = 64'h000000000000FFFE;
+			// synthesis read_comments_as_HDL off
+			// synthesis translate_off
+			assign phy_read_increment_vfifo_fr_combined[dqs_index] = phy_read_increment_vfifo_fr_pre_combined[dqs_index*VFIFO_CONTROL_WIDTH_PER_DQS];
+			// synthesis translate_on
+		end
+	end
+	else
+	begin
+		assign phy_read_increment_vfifo_fr_combined = phy_read_increment_vfifo_fr_pre_combined;
+	end
+	endgenerate
+	assign phy_read_increment_vfifo_fr = phy_read_increment_vfifo_fr_combined;
+
+	// wait request management and read data gating
+	
+	always_comb
+	begin
+		if (sel_any && state_avl_curr != STATE_AVL_DONE || ~avl_reset_n)
+			avl_waitrequest <= 1;
+		else 
+			avl_waitrequest <= 0;
+
+		if (sel_rfile_rd || sel_issue_rd)
+			avl_readdata <= avl_readdata_r;
+		else 
+			avl_readdata <= '0;
+	end
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sequencer_pll_mgr.sv b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_pll_mgr.sv
new file mode 100644
index 0000000..3fc46e5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sequencer_pll_mgr.sv
@@ -0,0 +1,193 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// ******
+// pll_mgr
+// ******
+//
+// PLL Manager
+//
+// General Description
+// -------------------
+//
+// This component allows a way for a master on the Avalon bus to
+// control PLL output clock phase during calibration
+
+//
+
+`timescale 1 ps / 1 ps
+
+module sequencer_pll_mgr (
+	// Avalon Interface
+	
+	avl_clk,
+	avl_reset_n,
+	avl_address,
+	avl_write,
+	avl_writedata,
+	avl_read,
+	avl_readdata,
+	avl_waitrequest,
+
+	// PLL control
+
+	phasecounterselect,
+	phasestep,
+	phaseupdown,
+	scanclk,
+	phasedone,
+	
+	afi_init_req,
+	afi_cal_req
+);
+
+	parameter AVL_DATA_WIDTH = 32;
+	parameter AVL_ADDR_WIDTH = 1;
+	
+	localparam PHASE_COUNTER_WIDTH = 16;
+	localparam PLL_COUNTER_BIT_WIDTH = 3;
+	localparam PLL_COUNTER = 2;
+
+	input avl_clk;
+	input avl_reset_n;
+	input [AVL_ADDR_WIDTH - 1:0] avl_address;
+	input avl_write;
+	input [AVL_DATA_WIDTH - 1:0] avl_writedata;
+	input avl_read;
+	output [AVL_DATA_WIDTH - 1:0] avl_readdata;
+	output avl_waitrequest;
+
+	output [PLL_COUNTER_BIT_WIDTH - 1:0] phasecounterselect;
+	output phasestep;
+	output phaseupdown;
+	output scanclk;
+	input phasedone;
+	
+	input afi_init_req;
+	input afi_cal_req;
+	
+	logic scanclk;
+	logic [PHASE_COUNTER_WIDTH - 1:0] mem_array [PLL_COUNTER - 1:0];
+	logic [AVL_DATA_WIDTH - 1:0] avl_readdata;
+	logic int_waitrequest;
+	
+	logic [AVL_ADDR_WIDTH - 1:0] int_address;
+	logic [AVL_DATA_WIDTH - 1:0] int_writedata;
+	
+	logic [PLL_COUNTER_BIT_WIDTH - 1:0] phasecounterselect;
+	logic phasestep;
+	logic phaseupdown;
+	
+	typedef enum int unsigned {
+		IDLE,
+		WRITE,
+		PLLWAIT,
+		PLLWAIT2,
+		PLLWAIT3,
+		READ,
+		READWAIT
+	} PLL_MGR_STATE;
+
+	PLL_MGR_STATE state;
+	
+	assign scanclk = avl_clk;
+	assign avl_waitrequest = ((state == IDLE) && ((avl_read == 1) || (avl_write == 1))) ? 1'b1 : int_waitrequest;
+	
+	// State machine
+		
+	always_ff @ (posedge avl_clk or negedge avl_reset_n)
+	    begin
+	        if (avl_reset_n == 0)
+	            begin
+	                state <= IDLE;
+	                avl_readdata <= 0;
+	                int_waitrequest <= 0;
+	                for (int i=0; i < PLL_COUNTER; i++)
+	                    mem_array[i] <= 0;
+	                phasecounterselect <= 0;
+	                phasestep <= 0;
+	                phaseupdown <= 0;
+	            end
+	        else
+	            begin
+	                case(state)
+	                    IDLE :
+	                        begin
+	                            int_waitrequest <= 0;
+	                            if (avl_write)
+	                                begin
+	                                    state <= WRITE;
+	                                    int_waitrequest <= 1;
+	                                end
+	                            else if (avl_read)
+	                                begin
+	                                    state <= READ;
+	                                    int_waitrequest <= 1;
+	                                end
+	                        end
+	                    WRITE :
+	                        begin
+	                            if (int_writedata[0]) 
+	                                mem_array [int_address]    <=    mem_array [int_address] + 1'b1;
+	                            else
+	                                mem_array [int_address]    <=    mem_array [int_address] - 1'b1;
+	                            
+	                            phaseupdown <= int_writedata[0];
+	                            phasecounterselect <= int_address[2:0] + 3'd4;
+	                            phasestep <= 1;
+	                            state <= PLLWAIT;
+	                        end
+	                    PLLWAIT :
+	                        state <= PLLWAIT2;
+	                    PLLWAIT2 :
+	                        begin
+	                            state <= PLLWAIT3;
+	                            int_waitrequest <= 0;
+	                        end
+	                    PLLWAIT3 :
+	                        begin
+	                            phasestep <= 0;
+	                            state <= IDLE;
+	                        end
+	                    READ :
+	                        begin
+	                            if (int_address < PLL_COUNTER)
+	                                avl_readdata <= mem_array [int_address];
+	                            else
+	                                avl_readdata <= afi_init_req | afi_cal_req;
+	                            int_waitrequest <= 0;
+	                            state <= READWAIT;
+	                        end
+	                    READWAIT :
+	                        begin
+	                            state <= IDLE;
+	                        end
+	                endcase
+	            end
+	    end
+	
+	always_ff @ (posedge avl_clk or negedge avl_reset_n)
+	    begin
+	        if (avl_reset_n == 0)
+	            begin
+	                int_address <= 0;
+	                int_writedata <= 0;
+	            end
+	        else
+	            begin
+	                int_address <= avl_address;
+	                int_writedata <= avl_writedata;
+	            end
+	    end
+	
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/serial_rx.v b/FPGA_firmware/q_sys/synthesis/submodules/serial_rx.v
new file mode 100644
index 0000000..cc1f14d
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/serial_rx.v
@@ -0,0 +1,84 @@
+// 9-bit Serial port receiver
+// It's very simple, just single sample halfway of each bit.
+// If start bit is not zero or stop bit is not one, an error will be signaled.
+// In general, this module is prone to glitches in signal. First of all, any glitch > Tclk will trigger the reception process.
+// RX is high on idle.
+// Baud rate is programmable via clk_divisor
+// clk_divisor ids internally divided by 2 to get in the middle of bit, so need to be at least 2.
+
+`timescale 100 ps / 100 ps
+module serial_rx (
+		input  wire        	clk,                	//      full-speed clock
+		input  wire        	rst,              	//      reset
+		input  wire [7:0]  	clk_divisor,         //      defines baudrate
+		input  wire 	   	rx,         		//      rx serial connection
+		output wire	   		newdata,		//	pulses for new data received
+		output wire [8:0]  	data,            	//      data to send
+		output wire	   		error,		//	bad start or stop bit
+		output wire	   		idle			//	1 if receiver in idle state
+	);
+
+	reg	[1:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_DATA		= 1;	//sending data
+	localparam STATE_FINISH		= 2;	//finished
+
+	reg	[4:0]	rx_ctr;			//counter of received data words
+	reg [7:0]	downctr;		//counter to generate baudrate
+	reg	[10:0]	buffer;			//internal latch/shift register with start and stop bit
+	reg	[8:0]	reg_data;		//latched received data
+	reg			reg_error;		//latched error
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			reg_data <= 0;
+			reg_error <= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (~rx)
+					begin
+						state 		<= STATE_DATA;
+						rx_ctr 		<= 10;
+						downctr[6:0]<= clk_divisor[7:1];	//wait half a bit
+						downctr[7]	<= 0;
+						buffer		<= 0;
+					end
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr 	<= clk_divisor;
+						rx_ctr 		<= rx_ctr - 1;
+						buffer[9:0] <= buffer[10:1];
+						buffer[10] 	<= rx;
+						if (rx_ctr == 0)
+							state 	<= STATE_FINISH;
+					end
+				end
+				STATE_FINISH:
+				begin
+					reg_data[8:0] 	<= buffer[9:1];
+					reg_error		<= buffer[0] | ~buffer[10];	//high start or low stop bit
+					state 			<= STATE_IDLE;
+				end
+				default:
+					state 			<= STATE_IDLE;
+			endcase
+	end
+	
+		//assignments
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+	assign data = reg_data;
+	assign error =  reg_error;
+
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/serial_tx.v b/FPGA_firmware/q_sys/synthesis/submodules/serial_tx.v
new file mode 100644
index 0000000..ab1b607
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/serial_tx.v
@@ -0,0 +1,115 @@
+// 9-bit Serial port transmitter
+// TX is high on idle.
+// Baud rate is programmable via clk_divisor
+
+`timescale 100 ps / 100 ps
+module serial_tx (
+		input  wire        clk,                	//      full-speed clock
+		input  wire        rst,              	//      reset
+		input  wire [8:0]  data,            	//      data to send
+		input  wire [7:0]  clk_divisor,         //      defines baudrate
+		input  wire 	   trigger,          	//      pulse to start transmission
+		output wire 	   tx,         		//      tx serial connection
+		output wire	   idle			//	1 if sender in idle state
+
+	);
+
+	reg	[2:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_STARTBIT	= 1;	//sending start bit
+	localparam STATE_DATA		= 2;	//sending data
+	localparam STATE_STOPBIT	= 3;	//sending stop bit
+	localparam STATE_FINISH		= 4;	//finished
+
+	reg	[4:0]	tx_ctr;			//counter of sent data words
+	reg 	[7:0]	downctr;		//counter to generate baudrate
+	reg	[8:0]	buffer;			//internal latch/shift register
+	reg		reg_tx;
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+			state <= STATE_FINISH;
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (trigger)
+					begin
+						state <= STATE_STARTBIT;
+						tx_ctr <= 8;
+						buffer <= data;
+						downctr <= clk_divisor;
+					end
+				end
+				STATE_STARTBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_DATA;
+					end
+
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						tx_ctr <= tx_ctr - 1;
+						buffer[7:0] <= buffer[8:1];
+						buffer[8] <= 0;
+						if (tx_ctr == 0)
+							state <= STATE_STOPBIT;
+					end
+				end
+				STATE_STOPBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_FINISH;
+					end
+
+				end
+				STATE_FINISH:
+				begin
+					if (~trigger)
+						state <= STATE_IDLE;
+				end
+				default:
+					state <= STATE_FINISH;
+			endcase
+	end
+	
+		//tx assignment
+	always @( * )
+	begin
+		if (rst)
+			reg_tx = 1;
+		else
+			case(state)
+				STATE_IDLE:
+					reg_tx = 1;
+				STATE_STARTBIT:
+					reg_tx = 0;
+				STATE_DATA:
+					reg_tx = buffer[0];
+				STATE_STOPBIT:
+					reg_tx = 1;
+				STATE_FINISH:
+					reg_tx = 1;
+				default:
+					reg_tx = 1;
+			endcase
+	end
+	assign tx = reg_tx;
+
+		//idle assignment
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/soft_asmiblock.sv b/FPGA_firmware/q_sys/synthesis/submodules/soft_asmiblock.sv
new file mode 100644
index 0000000..42749df
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/soft_asmiblock.sv
@@ -0,0 +1,81 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//---------------------------------------------------------------------
+//
+// Module Name : asmiblock
+// Description : Standard/QUAD IO mode
+//
+//---------------------------------------------------------------------
+
+`timescale 1 ps/1 ps
+module  soft_asmiblock #(
+	parameter IO_MODE = "STANDARD",
+	parameter CS_WIDTH = 1
+)(
+	dclk,
+	sce,
+	dataout,
+	dataoe,
+	datain,
+	dclk_out,
+	ncs
+);
+
+input 					dclk;
+input  [CS_WIDTH-1:0]	sce;
+input  [3:0]			dataout;
+input  [3:0]			dataoe;
+inout  [3:0]			datain;
+output 					dclk_out;
+output [CS_WIDTH-1:0]	ncs;
+
+wire oe;
+wire data[3:0];
+wire data_buf[3:0];
+
+assign oe = 1'b0;
+
+assign dclk_out = (oe === 1'b0) ? dclk : (oe === 1'b1) ? 1'bz : 1'bx;
+assign ncs = (oe === 1'b0) ? sce : (oe === 1'b1) ? 1'bz : 1'bx;
+
+assign data[0] = (oe === 1'b0) ? data_buf[0] : (oe === 1'b1) ? 1'bz : 1'bx;
+assign data_buf[0] = (dataoe[0] === 1'b1) ? dataout[0] : (dataoe[0] === 1'b0) ? 1'bz : 1'bx;
+assign datain[0] = data[0];
+
+assign data[1] = (oe === 1'b0) ? data_buf[1] : (oe === 1'b1) ? 1'bz : 1'bx;
+assign data_buf[1] = (dataoe[1] === 1'b1) ? dataout[1] : (dataoe[1] === 1'b0) ? 1'bz : 1'bx;
+assign datain[1] = data[1];
+
+generate 
+	if (IO_MODE == "STANDARD") begin
+		assign data[2] = (oe === 1'b0) ? data_buf[2] : (oe === 1'b1) ? 1'bz : 1'bx;
+		assign data_buf[2] = (dataoe[2] === 1'b1) ? 1'b1 : (dataoe[2] === 1'b0) ? 1'bz : 1'bx;
+		assign datain[2] = data[2];
+		
+		assign data[3] = (oe === 1'b0) ? data_buf[3] : (oe === 1'b1) ? 1'bz : 1'bx;
+		assign data_buf[3] = (dataoe[3] === 1'b1) ? 1'b1 : (dataoe[3] === 1'b0) ? 1'bz : 1'bx;
+		assign datain[3] = data[3];
+	end
+	else begin
+		assign data[2] = (oe === 1'b0) ? data_buf[2] : (oe === 1'b1) ? 1'bz : 1'bx;
+		assign data_buf[2] = (dataoe[2] === 1'b1) ? dataout[2] : (dataoe[2] === 1'b0) ? 1'bz : 1'bx;
+		assign datain[2] = data[2];
+		
+		assign data[3] = (oe === 1'b0) ? data_buf[3] : (oe === 1'b1) ? 1'bz : 1'bx;
+		assign data_buf[3] = (dataoe[3] === 1'b1) ? dataout[3] : (dataoe[3] === 1'b0) ? 1'bz : 1'bx;
+		assign datain[3] = data[3];
+	end
+endgenerate
+
+endmodule	//	asmiblock
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sqrt.qip b/FPGA_firmware/q_sys/synthesis/submodules/sqrt.qip
new file mode 100644
index 0000000..01e42de
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sqrt.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTSQRT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sqrt.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sqrt_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sqrt_bb.v"]
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/sqrt.v b/FPGA_firmware/q_sys/synthesis/submodules/sqrt.v
new file mode 100644
index 0000000..a3a89bc
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/sqrt.v
@@ -0,0 +1,104 @@
+// megafunction wizard: %ALTSQRT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTSQRT 
+
+// ============================================================
+// File Name: sqrt.v
+// Megafunction Name(s):
+// 			ALTSQRT
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sqrt (
+	clk,
+	ena,
+	radical,
+	q,
+	remainder);
+
+	input	  clk;
+	input	  ena;
+	input	[25:0]  radical;
+	output	[12:0]  q;
+	output	[13:0]  remainder;
+
+	wire [12:0] sub_wire0;
+	wire [13:0] sub_wire1;
+	wire [12:0] q = sub_wire0[12:0];
+	wire [13:0] remainder = sub_wire1[13:0];
+
+	altsqrt	ALTSQRT_component (
+				.clk (clk),
+				.ena (ena),
+				.radical (radical),
+				.q (sub_wire0),
+				.remainder (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr ()
+				// synopsys translate_on
+				);
+	defparam
+		ALTSQRT_component.pipeline = 13,
+		ALTSQRT_component.q_port_width = 13,
+		ALTSQRT_component.r_port_width = 14,
+		ALTSQRT_component.width = 26;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: PIPELINE NUMERIC "13"
+// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13"
+// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "26"
+// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
+// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]"
+// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]"
+// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
+// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
+// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/st2mm.v b/FPGA_firmware/q_sys/synthesis/submodules/st2mm.v
new file mode 100644
index 0000000..fbaeb81
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/st2mm.v
@@ -0,0 +1,81 @@
+//a module bridge the avalon streaming interface and avalon memory map interface
+//collect data from interface and write to RAM
+
+//32 2; OR 16 1
+module st2mm #(parameter BITSIZE = 32, EMPTY_SIZE = 2)(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [BITSIZE-1:0] st_data,           //  st.data
+	output wire        st_ready,          //         .ready
+	input  wire        st_valid,          //         .valid
+	input  wire [EMPTY_SIZE-1:0]  st_empty,          //         .empty
+	input  wire        st_endofpacket,    //         .endofpacket
+	input  wire        st_startofpacket,  //         .startofpacket
+	
+	//avalon MM(Memory Mapped) source  writelatency 0; readlatency 1 but no read logic here
+	output wire [8:0] mm_address,
+	output wire       mm_chipselect, // only for write
+	//output wire			mm_clken, //only for write; write enable
+	input wire	[BITSIZE-1:0]mm_readdate, //do not read
+	output wire 		mm_write,
+	output wire [BITSIZE-1:0] mm_writedata,
+	input wire mm_waitrequest_n
+	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE_WRITE = 2'd1; //write to mm
+	localparam STATE_LOCK = 2'd3; //Finish writing
+	
+	reg[8:0] ctr; // count data and the address for MM
+	localparam CTR_ZERO = 9'd0;
+	assign mm_address = ctr;
+	assign mm_writedata = st_data;
+	
+	assign mm_chipselect = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	//assign mm_clken = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	assign st_ready = (state == STATE_WRITE)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			ctr <= CTR_ZERO;
+		end
+		else case(state)
+				STATE_IDLE:
+				begin
+					ctr <= CTR_ZERO;
+					if (st_startofpacket)
+						state <= STATE_WRITE;
+				end
+				STATE_WRITE:
+				begin
+					if (st_valid && mm_waitrequest_n)
+					begin
+						ctr <= ctr + 1'b1;
+						if (st_endofpacket)
+							state <= STATE_LOCK;
+					end
+				end
+				STATE_LOCK:
+				begin
+					state <= STATE_IDLE;
+					ctr <= CTR_ZERO;
+				end
+				default:
+					state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+endmodule
+	
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.qip b/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.qip
new file mode 100644
index 0000000..ff332e8
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.qip
@@ -0,0 +1,52 @@
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "st_splitter16" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../st_splitter16.sopcinfo"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name SLD_INFO "QSYS_NAME st_splitter16 HAS_SOPCINFO 1 GENERATION_ID 1719926165"
+set_global_assignment -library "st_splitter16" -name MISC_FILE [file join $::quartus(qip_path) "../st_splitter16.cmp"]
+set_global_assignment -library "st_splitter16" -name SLD_FILE [file join $::quartus(qip_path) "st_splitter16.debuginfo"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "st_splitter16" -name MISC_FILE [file join $::quartus(qip_path) "../../st_splitter16.qsys"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_NAME "c3Rfc3BsaXR0ZXIxNg=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_DISPLAY_NAME "c3Rfc3BsaXR0ZXIxNg=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcxOTkyNjE2NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9zcGxpdHRlcg=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFNwbGl0dGVy"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIFNwbGl0dGVy"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX09VVFBVVFM=::Mg==::TlVNQkVSX09GX09VVFBVVFM="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "UVVBTElGWV9WQUxJRF9PVVQ=::MQ==::UVVBTElGWV9WQUxJRF9PVVQ="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURZ::MQ==::VVNFX1JFQURZ"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1ZBTElE::MQ==::VVNFX1ZBTElE"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MQ==::VVNFX1BBQ0tFVFM="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0NIQU5ORUw=::MA==::VVNFX0NIQU5ORUw="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0VSUk9S::MA==::VVNFX0VSUk9S"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEE=::MQ==::VVNFX0RBVEE="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MTY=::REFUQV9XSURUSA=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MQ==::Q0hBTk5FTF9XSURUSA=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MQ==::RVJST1JfV0lEVEg="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::OA==::QklUU19QRVJfU1lNQk9M"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "UkVBRFlfTEFURU5DWQ==::MA==::UkVBRFlfTEFURU5DWQ=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "RU1QVFlfV0lEVEg=::MQ==::RU1QVFlfV0lEVEg="
+
+set_global_assignment -library "st_splitter16" -name VERILOG_FILE [file join $::quartus(qip_path) "st_splitter16.v"]
+set_global_assignment -library "st_splitter16" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_splitter.sv"]
+
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_NAME "altera_avalon_st_splitter"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_ENV "Qsys"
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.v b/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.v
new file mode 100644
index 0000000..823c35f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/st_splitter16.v
@@ -0,0 +1,179 @@
+// st_splitter16.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module st_splitter16 (
+		input  wire        st_splitter16_clk_clk,            //   st_splitter16_clk.clk
+		output wire        st_splitter16_in_ready,           //    st_splitter16_in.ready
+		input  wire        st_splitter16_in_valid,           //                    .valid
+		input  wire        st_splitter16_in_startofpacket,   //                    .startofpacket
+		input  wire        st_splitter16_in_endofpacket,     //                    .endofpacket
+		input  wire [0:0]  st_splitter16_in_empty,           //                    .empty
+		input  wire [15:0] st_splitter16_in_data,            //                    .data
+		input  wire        st_splitter16_out0_ready,         //  st_splitter16_out0.ready
+		output wire        st_splitter16_out0_valid,         //                    .valid
+		output wire        st_splitter16_out0_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out0_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out0_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out0_data,          //                    .data
+		input  wire        st_splitter16_out1_ready,         //  st_splitter16_out1.ready
+		output wire        st_splitter16_out1_valid,         //                    .valid
+		output wire        st_splitter16_out1_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out1_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out1_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out1_data,          //                    .data
+		input  wire        st_splitter16_reset_reset         // st_splitter16_reset.reset
+	);
+
+	altera_avalon_st_splitter #(
+		.NUMBER_OF_OUTPUTS (2),
+		.QUALIFY_VALID_OUT (1),
+		.USE_PACKETS       (1),
+		.DATA_WIDTH        (16),
+		.CHANNEL_WIDTH     (1),
+		.ERROR_WIDTH       (1),
+		.BITS_PER_SYMBOL   (8),
+		.EMPTY_WIDTH       (1)
+	) st_splitter16 (
+		.clk                 (st_splitter16_clk_clk),            //   clk.clk
+		.reset               (st_splitter16_reset_reset),        // reset.reset
+		.in0_ready           (st_splitter16_in_ready),           //    in.ready
+		.in0_valid           (st_splitter16_in_valid),           //      .valid
+		.in0_startofpacket   (st_splitter16_in_startofpacket),   //      .startofpacket
+		.in0_endofpacket     (st_splitter16_in_endofpacket),     //      .endofpacket
+		.in0_empty           (st_splitter16_in_empty),           //      .empty
+		.in0_data            (st_splitter16_in_data),            //      .data
+		.out0_ready          (st_splitter16_out0_ready),         //  out0.ready
+		.out0_valid          (st_splitter16_out0_valid),         //      .valid
+		.out0_startofpacket  (st_splitter16_out0_startofpacket), //      .startofpacket
+		.out0_endofpacket    (st_splitter16_out0_endofpacket),   //      .endofpacket
+		.out0_empty          (st_splitter16_out0_empty),         //      .empty
+		.out0_data           (st_splitter16_out0_data),          //      .data
+		.out1_ready          (st_splitter16_out1_ready),         //  out1.ready
+		.out1_valid          (st_splitter16_out1_valid),         //      .valid
+		.out1_startofpacket  (st_splitter16_out1_startofpacket), //      .startofpacket
+		.out1_endofpacket    (st_splitter16_out1_endofpacket),   //      .endofpacket
+		.out1_empty          (st_splitter16_out1_empty),         //      .empty
+		.out1_data           (st_splitter16_out1_data),          //      .data
+		.in0_channel         (1'b0),                             // (terminated)
+		.in0_error           (1'b0),                             // (terminated)
+		.out0_channel        (),                                 // (terminated)
+		.out0_error          (),                                 // (terminated)
+		.out1_channel        (),                                 // (terminated)
+		.out1_error          (),                                 // (terminated)
+		.out2_ready          (1'b1),                             // (terminated)
+		.out2_valid          (),                                 // (terminated)
+		.out2_startofpacket  (),                                 // (terminated)
+		.out2_endofpacket    (),                                 // (terminated)
+		.out2_empty          (),                                 // (terminated)
+		.out2_channel        (),                                 // (terminated)
+		.out2_error          (),                                 // (terminated)
+		.out2_data           (),                                 // (terminated)
+		.out3_ready          (1'b1),                             // (terminated)
+		.out3_valid          (),                                 // (terminated)
+		.out3_startofpacket  (),                                 // (terminated)
+		.out3_endofpacket    (),                                 // (terminated)
+		.out3_empty          (),                                 // (terminated)
+		.out3_channel        (),                                 // (terminated)
+		.out3_error          (),                                 // (terminated)
+		.out3_data           (),                                 // (terminated)
+		.out4_ready          (1'b1),                             // (terminated)
+		.out4_valid          (),                                 // (terminated)
+		.out4_startofpacket  (),                                 // (terminated)
+		.out4_endofpacket    (),                                 // (terminated)
+		.out4_empty          (),                                 // (terminated)
+		.out4_channel        (),                                 // (terminated)
+		.out4_error          (),                                 // (terminated)
+		.out4_data           (),                                 // (terminated)
+		.out5_ready          (1'b1),                             // (terminated)
+		.out5_valid          (),                                 // (terminated)
+		.out5_startofpacket  (),                                 // (terminated)
+		.out5_endofpacket    (),                                 // (terminated)
+		.out5_empty          (),                                 // (terminated)
+		.out5_channel        (),                                 // (terminated)
+		.out5_error          (),                                 // (terminated)
+		.out5_data           (),                                 // (terminated)
+		.out6_ready          (1'b1),                             // (terminated)
+		.out6_valid          (),                                 // (terminated)
+		.out6_startofpacket  (),                                 // (terminated)
+		.out6_endofpacket    (),                                 // (terminated)
+		.out6_empty          (),                                 // (terminated)
+		.out6_channel        (),                                 // (terminated)
+		.out6_error          (),                                 // (terminated)
+		.out6_data           (),                                 // (terminated)
+		.out7_ready          (1'b1),                             // (terminated)
+		.out7_valid          (),                                 // (terminated)
+		.out7_startofpacket  (),                                 // (terminated)
+		.out7_endofpacket    (),                                 // (terminated)
+		.out7_empty          (),                                 // (terminated)
+		.out7_channel        (),                                 // (terminated)
+		.out7_error          (),                                 // (terminated)
+		.out7_data           (),                                 // (terminated)
+		.out8_ready          (1'b1),                             // (terminated)
+		.out8_valid          (),                                 // (terminated)
+		.out8_startofpacket  (),                                 // (terminated)
+		.out8_endofpacket    (),                                 // (terminated)
+		.out8_empty          (),                                 // (terminated)
+		.out8_channel        (),                                 // (terminated)
+		.out8_error          (),                                 // (terminated)
+		.out8_data           (),                                 // (terminated)
+		.out9_ready          (1'b1),                             // (terminated)
+		.out9_valid          (),                                 // (terminated)
+		.out9_startofpacket  (),                                 // (terminated)
+		.out9_endofpacket    (),                                 // (terminated)
+		.out9_empty          (),                                 // (terminated)
+		.out9_channel        (),                                 // (terminated)
+		.out9_error          (),                                 // (terminated)
+		.out9_data           (),                                 // (terminated)
+		.out10_ready         (1'b1),                             // (terminated)
+		.out10_valid         (),                                 // (terminated)
+		.out10_startofpacket (),                                 // (terminated)
+		.out10_endofpacket   (),                                 // (terminated)
+		.out10_empty         (),                                 // (terminated)
+		.out10_channel       (),                                 // (terminated)
+		.out10_error         (),                                 // (terminated)
+		.out10_data          (),                                 // (terminated)
+		.out11_ready         (1'b1),                             // (terminated)
+		.out11_valid         (),                                 // (terminated)
+		.out11_startofpacket (),                                 // (terminated)
+		.out11_endofpacket   (),                                 // (terminated)
+		.out11_empty         (),                                 // (terminated)
+		.out11_channel       (),                                 // (terminated)
+		.out11_error         (),                                 // (terminated)
+		.out11_data          (),                                 // (terminated)
+		.out12_ready         (1'b1),                             // (terminated)
+		.out12_valid         (),                                 // (terminated)
+		.out12_startofpacket (),                                 // (terminated)
+		.out12_endofpacket   (),                                 // (terminated)
+		.out12_empty         (),                                 // (terminated)
+		.out12_channel       (),                                 // (terminated)
+		.out12_error         (),                                 // (terminated)
+		.out12_data          (),                                 // (terminated)
+		.out13_ready         (1'b1),                             // (terminated)
+		.out13_valid         (),                                 // (terminated)
+		.out13_startofpacket (),                                 // (terminated)
+		.out13_endofpacket   (),                                 // (terminated)
+		.out13_empty         (),                                 // (terminated)
+		.out13_channel       (),                                 // (terminated)
+		.out13_error         (),                                 // (terminated)
+		.out13_data          (),                                 // (terminated)
+		.out14_ready         (1'b1),                             // (terminated)
+		.out14_valid         (),                                 // (terminated)
+		.out14_startofpacket (),                                 // (terminated)
+		.out14_endofpacket   (),                                 // (terminated)
+		.out14_empty         (),                                 // (terminated)
+		.out14_channel       (),                                 // (terminated)
+		.out14_error         (),                                 // (terminated)
+		.out14_data          (),                                 // (terminated)
+		.out15_ready         (1'b1),                             // (terminated)
+		.out15_valid         (),                                 // (terminated)
+		.out15_startofpacket (),                                 // (terminated)
+		.out15_endofpacket   (),                                 // (terminated)
+		.out15_empty         (),                                 // (terminated)
+		.out15_channel       (),                                 // (terminated)
+		.out15_error         (),                                 // (terminated)
+		.out15_data          ()                                  // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/stl2sts.v b/FPGA_firmware/q_sys/synthesis/submodules/stl2sts.v
new file mode 100644
index 0000000..a846124
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/stl2sts.v
@@ -0,0 +1,84 @@
+//a module bridge the avalon streaming interfaces with data length from 32 bit to 16 bit
+//long to short
+//32 bits to 16 bits [31:16] streaming out first and then [15:0]
+//ST long to ST short
+
+
+
+//tested by stl2sts_tb.v
+module stl2sts(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	output  wire [15:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire        data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE1 = 2'd1; //streaming [31:16]
+	localparam STATE2 = 2'd3; //streaming [15:0]
+	localparam STATE_LOCK = 2'd2; //Finishing streaming
+	
+	assign data_in_ready = (state == STATE2 && data_out_ready)? 1'b1:1'b0;
+	
+	assign data_out_data = (state == STATE1)? data_in_data[31:16]:(state== STATE2)? data_in_data[15:0]: 16'b0;
+	assign data_out_valid = (state == STATE1 || state == STATE2)?data_in_valid:1'b0;
+	assign data_out_empty = 1'b0;
+	assign data_out_startofpacket = (state == STATE1)? data_in_startofpacket: 1'b0;
+	assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			state <= STATE_IDLE;
+		else case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket)
+				state <= STATE1;
+		end
+		STATE1:
+		begin
+			if (data_in_valid && data_out_ready)
+				state <= STATE2;
+		end
+		STATE2:
+		begin
+			if (data_in_valid && data_out_ready)
+			begin
+				if (data_in_endofpacket)
+					state <= STATE_LOCK;
+				else
+					state <= STATE1;
+			end
+		end
+		STATE_LOCK:
+			state <= STATE_IDLE;
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+	
+
+
+endmodule
+	
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/udp_generator.v b/FPGA_firmware/q_sys/synthesis/submodules/udp_generator.v
new file mode 100644
index 0000000..c3b1535
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/udp_generator.v
@@ -0,0 +1,396 @@
+// UDP generator
+/*
+Takes an input stream and generates a valid UDP/IPv4 packet, then outputs it as a stream which can be directly connected to TSE.
+
+Remarks:
+- Both input and output are Avalon ST ports, 8-bit symbol, 4 symbols per beat
+- Start/end of packet signals are REQUIRED.
+- Empty signals are discarded. An incoming packet should have a length of 4N. If not, it will be padded with what's on the bus.
+- Backpressure is supported and actively used during transfer. Data source must be backpressurizable.
+- The transfer is performed on the fly, without buffering. Input gets backpressed for the time of sending headers.
+- Size of payload must be known in advance and programmed over Avalon MM interface. 
+- Longer packets will be cut. Shorter packets will be padded with zeros.
+- UDP checksum is not calculated (the price of realtime approach) and filled with zeros. IP header checksum is calculated.
+- The Programming interface is an Avalon MM. It's 32-bit wide and allows byte, halfword and word operations. Block transfers are not supported.
+- Source MAC is not programmable; it must be filled by TSE. 
+- Two leading zero bytes are added on front of the packet for 32-bit alignment. TSE settings must comply wit this.
+- If transfer is disabled (see control bits), the input will be backpressed all the time.
+- Maximum transfer size is about 64K, but limitations of the Ethernet must be taken into account.
+- The IPv4 header has the 'Don't fragment' flag set.
+
+Register map: (byte offsets are given)
+UDPGEN_REG_CSR		0	//16 bits 	8 bits control(LSB) + 8 bits status(MSB)
+UDPGEN_REG_SIZE		2	//16 bits	payload size in words
+UDPGEN_REG_SRCIP	4	//32 bits	source IP, last octet first
+UDPGEN_REG_DSTIP	8	//32 bits	destination IP. last octet first
+UDPGEN_REG_DSTPORT	12	//16 bits	destination port
+UDPGEN_REG_SRCPORT	14	//16 bits	source port
+UDPGEN_REG_DSTMAC	16	//2*32 bits	destination MAC, last octet first
+UDPGEN_REG_RES1		24	//32 bits	reserved
+UDPGEN_REG_RES2		28 	//32 bits	reserved
+
+Control bits:
+0: transfer enable
+1-7: unused
+
+Status bits:
+0-3: state of the machine
+7-4: unused
+
+*/
+
+
+`timescale 100 ps / 100 ps
+module udp_generator (
+		input  wire        clk_clk,                //      clk.clk
+		input  wire        rst_reset,              //      rst.reset
+		input  wire [2:0]  csr_address,            //      csr.address
+		input  wire        csr_write,              //         .write
+		input  wire [31:0] csr_writedata,          //         .writedata
+		input  wire [3:0]  csr_byteenable,         //         .byteenable
+		input  wire        csr_read,               //         .read
+		output wire [31:0] csr_readdata,           //         .readdata
+		input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+		output wire [31:0] data_out_data,          // data_out.data
+		output wire [1:0]  data_out_empty,         //         .empty
+		output wire        data_out_endofpacket,   //         .endofpacket
+		output wire        data_out_startofpacket, //         .startofpacket
+		input  wire        data_out_ready,         //         .ready
+		output wire        data_out_valid          //         .valid
+	);
+
+
+	// *********************** CSR stuff ************************
+	
+	reg 	[31:0] 	registers[7:0];		//main register space
+	wire 	[31:0]	reg0_read;		//reg[0] is read indirectly to include status byt(bits 15-8)
+
+		//read logic
+	assign reg0_read[7:0] 	= registers[0][7:0];		// Readback of control bits
+	assign reg0_read[31:16] = registers[0][31:16];		// Readback of payload size
+	assign reg0_read[15:12] = 0;				// Unused bits of the status byte
+	assign csr_readdata 	= (csr_address==0) ? reg0_read : registers[csr_address];
+
+		//write logic
+	genvar i;
+	genvar j;
+	generate
+	for (i = 0; i < 8; i = i+1)
+	begin : write_registers	//Quartus wants labels for 'for' blocks
+		for (j = 0; j < 4; j = j+1)
+		begin : write_bytes
+			always @(posedge clk_clk or posedge rst_reset)
+			begin 
+				if (rst_reset)
+					registers[i][8*j+7:8*j] <= 8'd0;
+				else
+					if (csr_byteenable[j] && (csr_address == i) && (csr_write))
+						registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
+			end
+		end
+	end	
+	endgenerate
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 0;	//waiting for SOP
+	localparam STATE_MAC1	= 1;	//sending first word of MAC header: 				00 00 dest_mac[5:4]
+	localparam STATE_MAC2	= 2;	//sending second word of MAC header: 				dest_mac[3:0]
+	localparam STATE_MAC3	= 3;	//sending zeroes as source MAC msbs:				00 00 00 00
+	localparam STATE_MAC4	= 4;	//sending zeroes as source MAC lsbs & packet type:		00 00 08 00
+	localparam STATE_IP1	= 5;	//sending IP ver & header size, DSF, total length		45 00 length[1:0]
+	localparam STATE_IP2	= 6;	//sending IP id, flags (don't fragment), fragm. offset=0	ip_id[1:0] 40 00
+	localparam STATE_IP3	= 7;	//sending TTL, protocol, header checksum			80 11 checksum[1:0]
+	localparam STATE_IP4	= 8;	//sending source IP						src_ip[4:0]
+	localparam STATE_IP5	= 9;	//sending destination IP					dst_ip[4:0]
+	localparam STATE_UDP1	= 10;	//sending src & dest port					src_port[1:0] dst_port[1:0]
+	localparam STATE_UDP2	= 11;	//sending UDP frame length and (unused) checksum		udp_length[1:0] 00 00
+	localparam STATE_DATA	= 12;	//sending packet data but the last word
+	localparam STATE_PAD	= 13;	//padding packet with zeros if incoming packet was too short
+	localparam STATE_DUMP	= 14;	//dumping tail of incoming packet if it was too long
+	localparam STATE_END	= 15;	//transfer finished, just wait one cycle
+
+	reg		reg_ready;	//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+	reg		reg_empty;
+
+		//Helper stuff
+	wire	[15:0]	udp_length;	
+	wire	[15:0]	total_length;
+	wire	[19:0]  int_checksum;
+	wire 	[16:0]	int_checksum2;	
+	wire	[15:0]	header_checksum;	
+	reg	[15:0]	ip_id;	//unique identifier of a packet
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+	assign reg0_read[11:8] = state;	//state forwarded to status register
+
+	assign udp_length = 4*registers[0][31:16] + 16'd8;	
+	assign total_length = 4*registers[0][31:16] + 16'd28;
+
+	assign int_checksum = 20'h10511 + total_length + ip_id + registers[1][31:16] + registers[1][15:0] + registers[2][31:16] + registers[2][15:0];
+	assign int_checksum2 = int_checksum[15:0] + int_checksum[19:16];
+	assign header_checksum = ~(int_checksum2[15:0] + int_checksum2[16]);
+
+		//The state machine
+	always @(posedge clk_clk or posedge rst_reset)
+	begin 
+		if (rst_reset)
+		begin
+			state <= STATE_IDLE;
+			ip_id<= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket && registers[0][0])
+					begin
+						state <= STATE_MAC1;
+						ip_id <= ip_id+1;
+						tx_ctr <= 1;
+					end
+				end
+				STATE_MAC1, STATE_MAC2, STATE_MAC3, STATE_MAC4, STATE_IP1, STATE_IP2, STATE_IP3, STATE_IP4, STATE_IP5, STATE_UDP1, STATE_UDP2:
+				begin
+					if (data_out_ready)
+						state <= state + 1;
+				end
+				STATE_DATA:
+				begin
+					if (data_out_ready && data_in_valid)
+					begin
+						tx_ctr <= tx_ctr+1;
+						if ((tx_ctr == registers[0][31:16]) && data_in_endofpacket)	//last word, size matches
+							state <= STATE_END;
+						else if (data_in_endofpacket)					//packet too short
+							state <= STATE_PAD;
+						else if (tx_ctr == registers[0][31:16])				//packet too long
+							state <= STATE_DUMP;
+					end
+				end
+				STATE_PAD:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1;
+						if (tx_ctr == registers[0][31:16])				
+							state <= STATE_END;
+					end	
+				end
+				STATE_DUMP:
+				begin
+					if (data_out_ready && data_in_valid)
+					begin
+						if (data_in_endofpacket)
+							state <= STATE_END;
+					end
+				end
+
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		//Driving bus signals
+	always @( * )
+	begin
+		if (rst_reset)
+		begin
+			reg_ready = 0;
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+			reg_empty = 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16] 	= 0;
+					reg_data[15:0] 		= registers[5][15:0];
+					reg_startofpacket 	= 1;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= registers[4];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC3:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= 32'h00000000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC4:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= 32'h00000800;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= 16'h4500;
+					reg_data[15:0]		= total_length;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= ip_id;
+					reg_data[15:0]		= 16'h4000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP3:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= 16'h8011;
+					reg_data[15:0]		= header_checksum;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP4:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[1];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP5:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[2];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_UDP1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[3];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_UDP2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= udp_length;
+					reg_data[15:0]		= 16'h0000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_DATA:
+				begin
+					reg_ready 		= data_out_ready;
+					reg_valid 		= data_in_valid;
+					reg_data		= data_in_data;
+					reg_startofpacket 	= 0;
+					if (tx_ctr == registers[0][31:16])
+						reg_endofpacket 	= 1;
+					else
+						reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_PAD:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= 32'h0;
+					reg_startofpacket 	= 0;
+					if (tx_ctr == registers[0][31:16])
+						reg_endofpacket 	= 1;
+					else
+						reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_DUMP:
+				begin
+					reg_ready 		= 1;
+					reg_valid 		= 0;
+					reg_data		= 0;
+					reg_startofpacket = 0;
+					reg_endofpacket = 0;
+					reg_empty 		= 0;
+				end
+				STATE_END:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				default:
+				begin
+					reg_ready = 0;
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket = 0;
+					reg_endofpacket = 0;
+					reg_empty = 0;
+				end
+			endcase
+	end
+
+	
+	assign data_in_ready = reg_ready;
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+	assign data_out_empty = reg_empty;
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/write_burst_control.v b/FPGA_firmware/q_sys/synthesis/submodules/write_burst_control.v
new file mode 100644
index 0000000..6b42731
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/write_burst_control.v
@@ -0,0 +1,300 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This block is responsible determine the appropriate burst count based on the
+  master length register as well as the buffer watermark and eop/early termination
+  conditions.
+
+  Within this block is a burst counter which is used to control when the next burst
+  is started.  This down counter is loaded with whatever burst count is presented
+  to the fabric and counts down when waitrequest is deasserted.  When it reaches 1
+  it can either start another burst or reach 0.  When the counter reaches 0 this is
+  considered the idle state which can occur if there is not enough data buffered to
+  start another burst.
+
+  During write bursts the address and burst count must be held for all the beats.
+  This block will register the address and burst count to keep these signals
+  held constant to the fabric.  This block will not begin a burst until enough
+  data has been buffered to start the burst so it will assert the stall signal
+  to keep the write master from advancing to the next word (just like waitrequest)
+  and will filter the write signal accordingly. 
+
+
+  Revision History:
+
+  1.0 Initial version
+  
+  1.1 Added sw_stop and stopped so that the write master will not be
+      stopped in the middle of a burst write transaction.
+  
+  1.2 Added the sink ready and valid signals to this block and qualified the
+      eop signal with them.
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module write_burst_control (
+  clk,
+  reset,
+  sw_reset,
+  sw_stop,
+
+  length,
+  eop_enabled,
+  eop,
+  ready,
+  valid,
+  early_termination,
+  address_in,
+  write_in,
+  max_burst_count,
+  write_fifo_used,
+  waitrequest,
+  short_first_access_enable,
+  short_last_access_enable,
+  short_first_and_last_access_enable,
+  last_access,  // JCJB:  new signal to let the burst counter reload logic know not to reload if the final word is being written to memory and data if buffered in FIFO
+
+  address_out,
+  write_out,
+  burst_count,
+  stall,
+  reset_taken,
+  stopped
+);
+
+  parameter BURST_ENABLE = 1;  // set to 0 to hardwire the address and write signals straight out
+  parameter BURST_COUNT_WIDTH = 3;
+  parameter WORD_SIZE = 4;
+  parameter WORD_SIZE_LOG2 = 2;
+  parameter ADDRESS_WIDTH = 32;
+  parameter LENGTH_WIDTH = 32;
+  parameter WRITE_FIFO_USED_WIDTH = 5;
+  parameter BURST_WRAPPING_SUPPORT = 1;  // set 1 for on, set 0 for off.  This parameter can't be enabled when the master supports programmable bursting.
+  localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
+
+  input clk;
+  input reset;
+  input sw_reset;
+  input sw_stop;
+
+  input [LENGTH_WIDTH-1:0] length;
+  input eop_enabled;
+  input eop;
+  input ready;
+  input valid;
+  input early_termination;
+  input [ADDRESS_WIDTH-1:0] address_in;
+  input write_in;
+  input [BURST_COUNT_WIDTH-1:0] max_burst_count;  // will be either a hardcoded input or programmable
+  input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used;  // using the fifo full MSB as well
+  input waitrequest;  // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
+  input short_first_access_enable;
+  input short_last_access_enable;
+  input short_first_and_last_access_enable;
+  // JCJB:  Added done input so that we can suppress the burst counter from incorrectly reloading at the end of a transfer
+  input last_access;
+
+  output wire [ADDRESS_WIDTH-1:0] address_out;
+  output wire write_out;
+  output wire [BURST_COUNT_WIDTH-1:0] burst_count;
+  output wire stall;  // need to issue a stall if there isn't enough data buffered to start a burst
+  output wire reset_taken;  // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
+  output wire stopped;  // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
+
+
+  reg [ADDRESS_WIDTH-1:0] address_d1;
+  reg [BURST_COUNT_WIDTH-1:0] burst_counter;  // interal statemachine register
+  wire idle_state;
+  wire decrement_burst_counter;
+  wire ready_during_idle_state;  // when there is enough data buffered to start up the burst counter state machine again
+  wire ready_for_quick_burst;    // when there is enough data bufferred to start another burst immediately 
+  wire burst_begin_from_idle_state;
+  wire burst_begin_quickly;      // start another burst immediately after the previous burst completes
+  wire burst_begin;
+  wire burst_of_one_enable;      // asserted when partial word accesses are occuring or the last early termination word is being written out
+  wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
+  wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
+  wire short_length_burst_enable;
+  wire short_early_termination_burst_enable;
+  wire short_packet_burst_enable;
+  wire [3:0] mux_select;
+  reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
+  reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
+  reg packet_complete;
+  wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
+
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      packet_complete <= 0;
+    end
+    else
+    begin
+      if ((packet_complete == 1) & (write_fifo_used == 0))
+      begin
+        packet_complete <= 0;
+      end
+      else if ((eop == 1) & (ready == 1) & (valid == 1))
+      begin
+        packet_complete <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      address_d1 <= 0;
+    end
+    else if (burst_begin == 1)
+    begin
+      address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      burst_counter <= 0;
+    end
+    else
+    if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0))  // for reset and stop we need to let the burst complete so the fabric doesn't lock up
+    begin
+      burst_counter <= internal_burst_count;
+    end
+    else if (decrement_burst_counter == 1)
+    begin
+      burst_counter <= burst_counter - 1'b1;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      internal_burst_count_d1 <= 0;
+    end
+    else if (burst_begin == 1)
+    begin
+      internal_burst_count_d1 <= internal_burst_count;
+    end
+  end
+
+
+  // state machine status and control
+  assign idle_state = (burst_counter == 0);  // any time idle_state is set then there is no burst underway
+  assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
+
+  // control for all the various cases that a burst of one beat needs to be posted
+  assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
+  assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
+                               ((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) |  // need to make sure bursts start on burst boundaries
+                               ((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1)));  // need to make sure bursts start on burst boundaries
+  assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
+  assign short_early_termination_burst_enable = (short_packet_burst_enable == 0) & ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0);  // trim back the burst count regardless if there is enough data buffered for a full burst
+  assign short_packet_burst_enable = (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
+
+  // various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux.  short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
+generate
+if (BURST_COUNT_WIDTH > 1) begin
+  assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
+  assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
+end
+else begin
+  assign short_length_burst = 1'b1;
+  assign short_packet_burst = 1'b1;
+end
+endgenerate
+
+  // since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
+  assign ready_during_idle_state = (burst_of_one_enable == 1) |  // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
+                                   ((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
+                                   ((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
+                                   ((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
+                                    (write_fifo_used >= max_burst_count);
+
+  // same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
+  assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) &  // address and length lags by one clock cycle so this will let the state machine catch up
+                                 (  ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
+                                    ((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
+                                    ((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
+                                     (write_fifo_used > max_burst_count)  );
+
+
+  // burst begin signals used to start up the burst counter state machine
+  assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1);   // start the state machine up again
+  /* JCJB:  added qualifier (last_access == 0) to make sure when the last beat of the last burst completes we don't reload the burst
+            counter if there is ample data already buffered for the next descriptor.  The burst counter being non-zero is what
+            drives write_out high.  This qualifier is not needed for burst_begin_from_idle_state since there is already an idle cycle between
+            writes so that write_in will already be low in time and buffered data won't reload the burst counter.
+  */
+  assign burst_begin_quickly = (last_access == 0) & (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
+  assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
+
+  assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
+
+  // one-hot mux that selects the appropriate burst count to present to the fabric
+  always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
+  begin
+    case (mux_select)
+      4'b0001 : internal_burst_count = 1;
+      4'b0010 : internal_burst_count = short_length_burst;
+      4'b0100 : internal_burst_count = short_length_burst;
+      4'b1000 : internal_burst_count = short_packet_burst;
+      default : internal_burst_count = max_burst_count;
+    endcase
+  end
+
+
+generate
+  if (BURST_ENABLE == 1)
+  begin
+    // outputs that need to be held constant throughout the entire burst transaction
+    assign address_out = address_d1;
+    assign burst_count = internal_burst_count_d1;
+    assign write_out = (idle_state == 0);
+    assign stall = (idle_state == 1);
+    assign reset_taken = (sw_reset == 1) & (idle_state == 1);  // for bursts of 1 the write master logic will handle the correct reset timing
+	assign stopped = (sw_stop == 1) & (idle_state == 1);       // for bursts of 1 the write master logic will handle the correct stop timing
+  end
+  else
+  begin
+    assign address_out = address_in;
+    assign burst_count = 1;  // this will be stubbed at the top level
+    assign write_out = write_in;
+    assign stall = 0;
+    assign reset_taken = sw_reset;
+	assign stopped = sw_stop;
+  end
+endgenerate
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/write_master.v b/FPGA_firmware/q_sys/synthesis/submodules/write_master.v
new file mode 100644
index 0000000..af36d1f
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/write_master.v
@@ -0,0 +1,920 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+  This write master module is responsible for taking in streaming data and
+  writing the contents out to memory.  It is controlled by a streaming
+  sink port called the 'command port'.  Any information that must be communicated
+  back to a host such as an error in transfer is made available by the
+  streaming source port called the 'response port'.
+
+  There are various parameters to control the synthesis of this hardware
+  either for functionality changes or speed/resource optimizations.  Some
+  of the parameters will be hidden in the component GUI since they are derived
+  from some other parameters.  When this master module is used in a MM to MM
+  transfer disable the packet support since the packet hardware is not needed.
+
+  In order to increase the Fmax you should enable only full accesses so that
+  the unaligned access and byte enable blocks can be reduced to wires.  Also
+  only configure the length width to be as wide as you need as it will typically
+  be the critical path of this module.
+
+
+  Revision History:
+
+  1.0 Initial version which used a simple exported hand shake control scheme.
+
+  2.0 Added support for unaligned accesses, stride, and streaming.
+
+  2.1 Fixed control logic and removed the early termination enable logic (it's
+      always on now so for packet transfers make sure the length register is
+      programmed accordingly.
+
+  2.2 Added burst support.
+
+  2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
+  
+  2.4 Corrected burst bug that prevented full bursts from being presented to the
+      fabric.  Corrected the stop/reset logic to ensure masters can be stopped
+      or reset while idle.
+      
+  2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
+      Added 64-bit addressing.
+
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module write_master (
+  clk,
+  reset,
+
+  // descriptor commands sink port
+  snk_command_data,
+  snk_command_valid,
+  snk_command_ready,
+
+  // response source port
+  src_response_data,
+  src_response_valid,
+  src_response_ready,
+
+  // data path sink port
+  snk_data,
+  snk_valid,
+  snk_ready,
+  snk_sop,
+  snk_eop,
+  snk_empty,
+  snk_error,
+
+  // data path master port
+  master_address,
+  master_write,
+  master_byteenable,
+  master_writedata,
+  master_waitrequest,
+  master_burstcount
+);
+
+  parameter UNALIGNED_ACCESSES_ENABLE = 0;        // when enabled allows transfers to begin from off word boundaries
+  parameter ONLY_FULL_ACCESS_ENABLE = 0;          // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
+  parameter STRIDE_ENABLE = 0;                    // stride support can only be enabled when unaligned accesses is disabled
+  parameter STRIDE_WIDTH = 1;                     // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width               
+  parameter PACKET_ENABLE = 0;
+  parameter ERROR_ENABLE = 0;
+  parameter ERROR_WIDTH = 8;                      // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
+  parameter DATA_WIDTH = 32;
+  parameter BYTE_ENABLE_WIDTH = 4;                // set by the .tcl file (hidden in GUI)
+  parameter BYTE_ENABLE_WIDTH_LOG2 = 2;           // set by the .tcl file (hidden in GUI)
+  parameter ADDRESS_WIDTH = 32;                   // set in the .tcl file (hidden in GUI) by the address span of the master
+  parameter LENGTH_WIDTH = 32;                    // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
+  parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32;  // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32).  A warning will be issued if overrun protection is enabled and this setting is less than the length width.
+  parameter FIFO_DEPTH = 32;
+  parameter FIFO_DEPTH_LOG2 = 5;                  // set by the .tcl file (hidden in GUI)
+  parameter FIFO_SPEED_OPTIMIZATION = 1;          // set by the .tcl file (hidden in GUI)  The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
+  parameter SYMBOL_WIDTH = 8;                     // set by the .tcl file (hidden in GUI)
+  parameter NUMBER_OF_SYMBOLS = 4;                // set by the .tcl file (hidden in GUI)
+  parameter NUMBER_OF_SYMBOLS_LOG2 = 2;           // set by the .tcl file (hidden in GUI)
+  parameter BURST_ENABLE = 0;
+  parameter MAX_BURST_COUNT = 2;                  // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
+  parameter MAX_BURST_COUNT_WIDTH = 2;            // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
+  parameter PROGRAMMABLE_BURST_ENABLE = 0;        // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
+  parameter BURST_WRAPPING_SUPPORT = 1;           // will only be used when bursting is enabled.  This cannot be enabled with programmable burst capabilities.  Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
+
+  localparam FIFO_USE_MEMORY = 1;                 // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
+  localparam BIG_ENDIAN_ACCESS = 0;               // hiding this since it can blow your foot off if you are not careful and it's not tested.  It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
+  // handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
+  localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
+  //need to buffer the empty, eop, sop, and error bits.  If these are not needed then the logic will be synthesized away
+  localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH);  // data, sop, eop, empty, and error bits
+  localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
+  localparam FIXED_STRIDE = 1'b1;  // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
+
+
+  input clk;
+  input reset;
+
+  // descriptor commands sink port
+  input [255:0] snk_command_data;
+  input snk_command_valid;
+  output reg snk_command_ready;
+
+  // response source port
+  output wire [255:0] src_response_data;
+  output reg src_response_valid;
+  input src_response_ready;
+
+  // data path sink port
+  input [DATA_WIDTH-1:0] snk_data;
+  input snk_valid;
+  output wire snk_ready;
+  input snk_sop;
+  input snk_eop;
+  input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
+  input [ERROR_WIDTH-1:0] snk_error;
+
+  // master inputs and outputs
+  input master_waitrequest;
+  output wire [ADDRESS_WIDTH-1:0] master_address;
+  output wire master_write;
+  output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
+  output wire [DATA_WIDTH-1:0] master_writedata;
+  output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
+
+
+  // internal wires and registers
+  wire [63:0] descriptor_address;
+  wire [31:0] descriptor_length;
+  wire [15:0] descriptor_stride;
+  wire descriptor_end_on_eop_enable;
+  wire [7:0] descriptor_programmable_burst_count;
+  reg [ADDRESS_WIDTH-1:0] address_counter;
+  wire [ADDRESS_WIDTH-1:0] address;  // unfiltered version of master_address
+  wire write;  // unfiltered version of master_write
+  reg [LENGTH_WIDTH-1:0] length_counter;
+  reg [STRIDE_WIDTH-1:0] stride_d1;
+  wire [STRIDE_WIDTH-1:0] stride_amount;  // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
+  reg descriptor_end_on_eop_enable_d1;
+  reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
+  wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
+  reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address;  // used to determine how far out of alignement the master started
+  reg first_access;  // used to prevent extra writes when the unaligned access starts and ends during the same write
+  wire first_word_boundary_not_reached;   // set when the first access doesn't reach the next word boundary
+  reg first_word_boundary_not_reached_d1;
+  wire increment_address;  // enable the address incrementing
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment;  // amount of bytes to increment the address
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
+  wire short_first_access_enable;           // when starting unaligned and the amount of data to transfer reaches the next word boundary
+  wire short_last_access_enable;            // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary 
+  wire short_first_and_last_access_enable;  // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
+  wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
+  reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;  
+  wire [FIFO_WIDTH-1:0] fifo_write_data;
+  wire [FIFO_WIDTH-1:0] fifo_read_data;
+  wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
+  wire fifo_write;
+  wire fifo_read;
+  wire fifo_empty;
+  wire fifo_full;
+  wire [DATA_WIDTH-1:0] fifo_read_data_rearranged;  // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
+  wire go;
+  wire done;
+  reg done_d1;
+  wire done_strobe;
+  wire [DATA_WIDTH-1:0] buffered_data;
+  wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
+  wire buffered_eop;
+  wire buffered_sop;  // not wired to anything so synthesized away, included for debug purposes
+  wire [ERROR_WIDTH-1:0] buffered_error;
+  wire length_sync_reset;  // syncronous reset for the length counter for eop support
+  reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter;  // width will be in the range of 1-32
+  wire [31:0] response_actual_bytes_transferred;
+  wire early_termination;
+  reg early_termination_d1;
+  wire eop_enable;
+  reg [ERROR_WIDTH-1:0] error;    // SRFF so that we don't loose any errors if EOP doesn't arrive right away
+  wire [7:0] response_error;      // need to pad upper error bits with zeros if they are not present at the data streaming port
+  wire sw_stop_in;
+  wire sw_reset_in;
+  reg stopped;                    // SRFF to make sure we don't attempt to stop in the middle of a transfer
+  reg reset_taken;                // FF to make sure we don't attempt to reset the master in the middle of a transfer
+  wire reset_taken_from_write_burst_control;  // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
+  wire stopped_from_write_burst_control;      // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
+  wire stop_state;
+  wire reset_delayed;
+  wire write_complete;            // handy signal for determining when a write has occured and completed
+  wire write_stall_from_byte_enable_generator;  // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
+  wire write_stall_from_write_burst_control;    // when there isn't enough data buffered to start a burst this signal will be asserted
+  wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1];  // a bunch of masks that will be provided to unsupported_byteenable
+  wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable;  // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
+  wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable;  // output from the byte enable generation block
+  wire extra_write;  // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
+  wire st_to_mm_adapter_enable;
+  wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size;  // number of bytes coming in from the data stream when packet support is enabled
+  wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
+  reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1;  // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
+  reg eop_seen;  // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted.  It is used to determine if an extra write must occur (unaligned accesses only)
+
+  wire last_access;  // JCJB: new signal to flag that the final access is occuring, will be used to supress the burst counter from reloading incorrectly at the end of the transfer
+
+/********************************************* REGISTERS ****************************************************************************************/
+  // registering the stride control bit
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      stride_d1 <= 0;
+    end
+    else if (go == 1)
+    begin
+      stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
+    end
+  end
+
+
+  // registering the end on eop bit (will be optimized away if packet support is disabled)
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      descriptor_end_on_eop_enable_d1 <= 1'b0;
+    end
+    else if (go == 1)
+    begin
+      descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
+    end
+  end
+
+
+  // registering the programmable burst count (will be optimized away if this support is disabled)
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      programmable_burst_count_d1 <= 0;
+    end
+    else if (go == 1)
+    begin
+      programmable_burst_count_d1 <= ((descriptor_programmable_burst_count == 0) | (descriptor_programmable_burst_count > MAX_BURST_COUNT)) ? MAX_BURST_COUNT : descriptor_programmable_burst_count;
+    end
+  end
+
+
+  // master address increment counter
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      address_counter <= 0;
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
+      end
+      else if (increment_address == 1)
+      begin
+        address_counter <= address_counter + address_increment;
+      end
+    end
+  end
+
+
+  // master byte address, used to determine how far out of alignment the master began transfering data
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      start_byte_address <= 0;
+    end
+    else if (go == 1)
+    begin
+      start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
+    end
+  end
+
+
+  // first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      first_access <= 0;
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        first_access <= 1;
+      end
+      else if ((first_access == 1) & (increment_address == 1))
+      begin
+        first_access <= 0;
+      end
+    end
+  end
+
+
+  // this register is used to determine if the first word boundary will be reached
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      first_word_boundary_not_reached_d1 <= 0;
+    end
+    else if (go == 1)
+    begin
+      first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
+    end
+  end
+
+
+  // master length logic, this will typically be the critical path followed by the FIFO
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      length_counter <= 0;
+    end
+    else
+    begin
+      if (length_sync_reset == 1)  // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
+      begin
+        length_counter <= 0;  // when EOP arrives need to stop counting, length=0 is the done condition
+      end
+      else if (go == 1)
+      begin
+        length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
+      end
+      else if (increment_address == 1)
+      begin
+        length_counter <= length_counter - bytes_to_transfer;  // not using address_increment because stride might be enabled
+      end
+    end
+  end
+
+
+  // master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      actual_bytes_transferred_counter <= 0;
+    end
+    else
+    begin
+      if ((go == 1) | (reset_taken == 1))
+      begin
+        actual_bytes_transferred_counter <= 0;
+      end
+      else if(increment_address == 1)
+      begin
+        actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      done_d1 <= 1;     // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
+    end
+    else
+    begin
+      done_d1 <= done;
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      early_termination_d1 <= 0;
+    end
+    else
+    begin
+      early_termination_d1 <= early_termination;
+    end
+  end
+
+
+  generate
+  genvar l;
+  for(l = 0; l < ERROR_WIDTH; l = l + 1)
+  begin: error_SRFF
+    always @ (posedge clk or posedge reset)
+    begin
+      if (reset)
+      begin
+        error[l] <= 0;
+      end
+      else
+      begin
+        if ((go == 1) | (reset_taken == 1))
+        begin
+          error[l] <= 0;
+        end
+        else if ((buffered_error[l] == 1) & (done == 0))
+        begin
+          error[l] <= 1;
+        end
+      end
+    end
+  end
+  endgenerate
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      snk_command_ready <= 1;  // have to start ready to take commands
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        snk_command_ready <= 0;
+      end
+      else if (((src_response_ready == 1) & (src_response_valid == 1)) | (reset_taken == 1))  // need to make sure the response is popped before accepting more commands
+      begin
+        snk_command_ready <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      src_response_valid <= 0;
+    end
+    else
+    begin
+      if (reset_taken == 1)
+      begin
+        src_response_valid <= 0;
+      end
+      else if (done_strobe == 1)
+      begin
+        src_response_valid <= 1;  // will be set only once
+      end
+      else if ((src_response_valid == 1) & (src_response_ready == 1))
+      begin
+        src_response_valid <= 0;  // will be reset only once when the dispatcher captures the data
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      stopped <= 0;
+    end
+    else
+    begin
+      if ((sw_stop_in == 0) | (reset_taken == 1))
+      begin
+        stopped <= 0;
+      end
+      else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
+      begin
+        stopped <= 1;
+      end
+    end
+  end
+
+
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      reset_taken <= 0;
+    end
+    else
+    begin
+      reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
+    end
+  end
+
+
+  // eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      eop_seen <= 0;
+    end
+    else
+    begin
+      if (done == 1)
+      begin
+        eop_seen <= 0;
+      end
+      else if ((buffered_eop == 1) & (write_complete == 1))
+      begin
+        eop_seen <= 1;
+      end
+    end
+  end
+
+
+  // when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset)
+    begin
+      packet_bytes_buffered_d1 <= 0;
+    end
+    else
+    begin
+      if (go == 1)
+      begin
+        packet_bytes_buffered_d1 <= 0;
+      end
+      else if (write_complete == 1)
+      begin
+        packet_bytes_buffered_d1 <= packet_bytes_buffered; 
+      end
+    end
+  end
+/********************************************* END REGISTERS ************************************************************************************/
+
+
+
+
+/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
+  /* buffered sop, eop, empty, error, data (in that order).  sop, eop, and empty are only used when packet support is enabled,
+     likewise error is only used when error support is enabled */
+  scfifo the_st_to_master_fifo (
+    .aclr (reset),
+    .sclr (reset_taken),
+    .clock (clk),
+    .data (fifo_write_data),
+    .full (fifo_full),
+    .empty (fifo_empty),
+    .q (fifo_read_data),
+    .rdreq (fifo_read),
+    .usedw (fifo_used),
+    .wrreq (fifo_write)
+  );
+  defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
+  defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
+  defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
+  defparam the_st_to_master_fifo.lpm_showahead = "ON";  // slower but doesn't require complex control logic to time with waitrequest
+  defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
+  defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
+  defparam the_st_to_master_fifo.underflow_checking = "OFF";
+  defparam the_st_to_master_fifo.overflow_checking = "OFF";
+
+
+  /* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
+     part of the FIFO word when off boundary).  When unaligned accesses is disabled then the data passes
+     as wires.  The byte enable generator might require multiple cycles to perform partial accesses so a
+     'stall' bit is used (triggers a stall like waitrequest)
+   */
+  ST_to_MM_Adapter the_ST_to_MM_Adapter (
+    .clk (clk),
+    .reset (reset),
+    .enable (st_to_mm_adapter_enable),
+    .address (descriptor_address[ADDRESS_WIDTH-1:0]),
+    .start (go),
+    .waitrequest (master_waitrequest),
+    .stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
+    .write_data (master_writedata),
+    .fifo_data (buffered_data),
+    .fifo_empty (fifo_empty),
+    .fifo_readack (fifo_read)
+  );
+  defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
+  defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
+  defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
+  defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
+
+
+  /* this block is responsible for presenting the fabric with supported byte enable combinations which can
+     take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
+  byte_enable_generator the_byte_enable_generator (
+    .clk (clk),
+    .reset (reset),
+    .write_in (write),
+    .byteenable_in (unsupported_byteenable),
+    .waitrequest_out (write_stall_from_byte_enable_generator),
+    .byteenable_out (supported_byteenable),
+    .waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
+  );
+  defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
+
+
+  // this block will be used to drive write, address, and burstcount to the fabric
+  write_burst_control the_write_burst_control (
+    .clk (clk),
+    .reset (reset),
+    .sw_reset (sw_reset_in),
+	  .sw_stop (sw_stop_in),
+    .length (length_counter),
+    .eop_enabled (descriptor_end_on_eop_enable_d1),
+    .eop (snk_eop),
+    .ready (snk_ready),
+    .valid (snk_valid),
+    .early_termination (early_termination),
+    .address_in (address),
+    .write_in (write),
+    .max_burst_count (maximum_burst_count),
+    .write_fifo_used ({fifo_full,fifo_used}),
+    .waitrequest (master_waitrequest),
+    .short_first_access_enable (short_first_access_enable),
+    .short_last_access_enable (short_last_access_enable),
+    .short_first_and_last_access_enable (short_first_and_last_access_enable),
+    .last_access (last_access),   // JCJB;  feeding done signal into burst module so that we can suppress the burst logic from sending an extra burst if data if still buffered in FIFO
+    .address_out (master_address),
+    .write_out (master_write),  // filtered version of 'write'
+    .burst_count (master_burstcount),
+    .stall (write_stall_from_write_burst_control),
+    .reset_taken (reset_taken_from_write_burst_control),
+	.stopped (stopped_from_write_burst_control)
+  );
+  defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
+  defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
+  defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
+  defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2;  // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
+  defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
+  defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
+  defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
+  defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
+
+/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
+
+
+
+
+
+/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
+  // breakout the descriptor information into more manageable names
+  assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]};  // 64-bit addressing support
+  assign descriptor_length = snk_command_data[63:32];
+  assign descriptor_programmable_burst_count = snk_command_data[75:68];
+  assign descriptor_stride = snk_command_data[91:76];
+  assign descriptor_end_on_eop_enable = snk_command_data[64];
+  assign sw_stop_in = snk_command_data[66];
+  assign sw_reset_in = snk_command_data[67];
+
+
+  assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE;  // hardcoding to FIXED_STRIDE when stride capabilities are disabled
+  assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
+  assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0;  // no eop or early termination support when packet support is disabled
+  assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0);  // set_done asserts the done register so this strobe fires when the last write completes
+  assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
+  assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
+
+
+  // transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
+  assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
+  assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
+  assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
+
+  // JCJB:  new signal that is high any time there is a word or less to trasnfer, will be used to suppress reloading of the burst counter if data for the next descriptor is buffered
+  assign last_access = (length_counter <= (DATA_WIDTH/8));
+
+  /* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
+     short_first_access_enable is for transfers that start aligned but reach the next word boundary
+     short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
+     short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
+  */
+  generate
+    if (UNALIGNED_ACCESSES_ENABLE == 1)
+    begin
+      // all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
+      assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
+      assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
+      assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
+      assign bytes_to_transfer = bytes_to_transfer_mux;
+      assign address_increment = bytes_to_transfer_mux;  // can't use stride when unaligned accesses are enabled
+    end
+    else if (ONLY_FULL_ACCESS_ENABLE == 1)
+    begin 
+      assign short_first_access_enable = 0;
+      assign short_last_access_enable = 0;
+      assign short_first_and_last_access_enable = 0;
+      assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
+      if (STRIDE_ENABLE == 1)
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;  // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
+      end
+      else
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH;  // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
+      end
+    end
+    else  // must be aligned but can end with any number of bytes
+    begin 
+      assign short_first_access_enable = 0;
+      assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH);    // less than a word to transfer
+      assign short_first_and_last_access_enable = 0;
+      assign bytes_to_transfer = bytes_to_transfer_mux;
+      if (STRIDE_ENABLE == 1)
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
+      end
+      else
+      begin
+        assign address_increment = BYTE_ENABLE_WIDTH;
+      end
+    end
+  endgenerate
+
+  // the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
+  always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
+  begin
+    case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
+      3'b001: bytes_to_transfer_mux = short_first_access_size;            // unaligned and reaches the next word boundary
+      3'b010: bytes_to_transfer_mux = short_last_access_size;             // aligned and does not reach the next word boundary
+      3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;   // unaligned and does not reach the next word boundary
+      default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH;                 // aligned and reaches the next word boundary (i.e. a full word transfer)
+    endcase
+  end
+
+
+  // Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
+  generate
+    genvar i;
+    for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH)  // the data width is always a multiple of the symbol width
+    begin: symbol_swap
+      assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
+    end
+  endgenerate
+
+  // sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
+  assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:{NUMBER_OF_SYMBOLS_LOG2{1'b0}}, snk_sop, snk_eop};
+
+
+  // swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
+  generate
+  if(BIG_ENDIAN_ACCESS == 1)
+  begin
+    genvar j;
+    for(j=0; j < DATA_WIDTH; j = j + 8)
+    begin: byte_swap
+      assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
+      assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
+    end
+  end
+  else
+  begin
+    assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0];  // little endian so no byte swapping necessary
+    assign master_byteenable = supported_byteenable;    // dito
+  end
+  endgenerate
+
+  // fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
+  assign buffered_data = fifo_read_data_rearranged;
+  assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
+
+
+  generate
+  if (PACKET_ENABLE == 1)
+  begin
+    assign buffered_eop = fifo_read_data[DATA_WIDTH];
+    assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
+    if (ONLY_FULL_ACCESS_ENABLE == 1)
+    begin
+      assign buffered_empty = 0;  // ignore the empty signal and assume it was a full beat
+    end
+    else
+    begin
+      assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2];  // empty is packed into the upper FIFO bits
+    end
+  end
+  else
+  begin
+    assign buffered_empty = 0;
+    assign buffered_eop = 0;
+    assign buffered_sop = 0;
+  end
+  endgenerate
+
+
+  /*  Generating mask bits based on the size of the transfer before the unaligned access adjustment.  This is based on the
+      transfer size to determine how many byte enables would be asserted in the aligned case.  Afterwards the
+      byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
+      first transfer).  If the data path is 32 bits wide then the following masks are generated:
+
+      Transfer Size       Index           Mask
+            1               0             0001
+            2               1             0011
+            3               2             0111
+            4               3             1111
+
+      Note that the index is just the transfer size minus one
+  */
+  generate if (BYTE_ENABLE_WIDTH > 1)
+  begin
+    genvar k;
+    for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
+    begin: byte_enable_loop
+      assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} };  // Byte enable width - k zeros followed by k ones
+    end
+  end
+  else
+  begin
+    assign byteenable_masks[0] = 1'b1;  // will be stubbed at top level
+  end
+  endgenerate
+
+
+  /* byteenable_mask is based on an aligned access determined by the transfer size.  This value is then shifted
+     to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
+     correct byte enables are enabled.  When the accesses are aligned then no barrelshifting is needed and when full
+     accesses are used then all byte enables will be asserted always. */
+  generate if (ONLY_FULL_ACCESS_ENABLE == 1)
+  begin
+    assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};  // always full accesses so the byte enables are all ones
+  end
+  else if (UNALIGNED_ACCESSES_ENABLE == 0)
+  begin
+    assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1];  // aligned so no unaligned adjustment required
+  end
+  else  // unaligned case
+  begin
+    assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK);  // barrelshift adjusts for unaligned start address
+  end
+  endgenerate
+
+
+  generate if (BYTE_ENABLE_WIDTH > 1)
+  begin
+    assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} };  // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
+  end
+  else
+  begin
+    assign address = address_counter;  // don't need to mask any bits as the address will only advance one byte at a time
+  end
+  endgenerate
+
+  assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
+
+  assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty);  // when the eop arrives we can't add more to packet_bytes_buffered_d1
+  assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
+
+  // extra_write is only applicable when unaligned accesses are performed.  This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
+  assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))? 
+                       ((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
+                       ((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0])));  // non-packet transfer and there are extra bytes buffered so performing an extra access
+
+
+  assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) &  // length is less than the word size
+                                           (((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH);  // start address + length doesn't reach the next word boundary (not used for packet transfers)
+  
+  assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0) & (early_termination_d1 == 0);
+  assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
+
+  assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0);  // writing still occuring and no reasons to prevent the write cycle from completing
+  assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
+  assign go = (snk_command_valid == 1) & (snk_command_ready == 1);  // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
+
+  assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
+                     (((PACKET_ENABLE == 1) & (snk_sop == 1) & ((eop_enable == 1) | (snk_command_ready == 1)) & (fifo_empty == 0)) != 1);  // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
+
+  assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
+
+
+  assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
+
+  assign early_termination = (eop_enable == 1) & 
+                             (   ((write_complete == 1) & (length_counter < bytes_to_transfer)) |  // packet transfer and the length counter is about to roll over so stop transfering
+                                 ((length_counter == 0) & (eop_seen == 0) & (go == 0))   );        // length counter hit zero and eop beat still hasn't been written to memory   
+  
+  assign stop_state = stopped;
+  assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
+  assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
+/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
+
+endmodule
diff --git a/FPGA_firmware/q_sys/synthesis/submodules/write_signal_breakout.v b/FPGA_firmware/q_sys/synthesis/submodules/write_signal_breakout.v
new file mode 100644
index 0000000..74c6cc5
--- /dev/null
+++ b/FPGA_firmware/q_sys/synthesis/submodules/write_signal_breakout.v
@@ -0,0 +1,125 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+/*
+
+  This block is used to breakout the 256 bit streaming ports to and from the write master.
+  The information sent through the streaming ports is a bundle of wires and buses so it's
+  fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
+  This block also provides a layer of abstraction since the descriptor buffers block has
+  no clue what format the descriptors are in except that the 'go' bit is written to.  This
+  means that using this block you could move descriptor information around without affecting
+  the top level dispatcher logic.
+  
+  
+  1.0  06/29/2009 - First version of this block of wires
+  
+  1.1  11/15/2012 - Added in an additional 32 bits of address for extended descriptors
+  
+*/
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+
+module write_signal_breakout (
+  write_command_data_in,     // descriptor from the write FIFO
+  write_command_data_out,  // reformated descriptor to the write master
+
+  // breakout of command information
+  write_address,
+  write_length,
+  write_park,
+  write_end_on_eop,
+  write_transfer_complete_IRQ_mask,
+  write_early_termination_IRQ_mask,
+  write_error_IRQ_mask,
+  write_burst_count,      // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+  write_stride,           // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+  write_sequence_number,  // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
+
+  // additional control information that needs to go out asynchronously with the command data
+  write_stop,
+  write_sw_reset
+);
+
+  parameter DATA_WIDTH = 256;  // 256 bits when enhanced settings are enabled otherwise 128 bits
+
+  input [DATA_WIDTH-1:0] write_command_data_in;
+  output wire [255:0] write_command_data_out;
+
+  output wire [63:0] write_address;
+  output wire [31:0] write_length;
+  output wire write_park;
+  output wire write_end_on_eop;
+  output wire write_transfer_complete_IRQ_mask;
+  output wire write_early_termination_IRQ_mask;
+  output wire [7:0] write_error_IRQ_mask;
+  output wire [7:0] write_burst_count;
+  output wire [15:0] write_stride;
+  output wire [15:0] write_sequence_number;
+
+  input write_stop;
+  input write_sw_reset;
+
+  assign write_address[31:0] = write_command_data_in[63:32];
+  assign write_length = write_command_data_in[95:64];
+
+
+  generate
+    if (DATA_WIDTH == 256)
+    begin
+      assign write_park = write_command_data_in[235];
+      assign write_end_on_eop = write_command_data_in[236];
+      assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
+      assign write_early_termination_IRQ_mask = write_command_data_in[239];
+      assign write_error_IRQ_mask = write_command_data_in[247:240];
+      assign write_burst_count = write_command_data_in[127:120];
+      assign write_stride = write_command_data_in[159:144];
+      assign write_sequence_number = write_command_data_in[111:96];
+      assign write_address[63:32] = write_command_data_in[223:192];
+    end
+    else
+    begin
+      assign write_park = write_command_data_in[107];
+      assign write_end_on_eop = write_command_data_in[108];
+      assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
+      assign write_early_termination_IRQ_mask = write_command_data_in[111];
+      assign write_error_IRQ_mask = write_command_data_in[119:112];
+      assign write_burst_count = 8'h00;
+      assign write_stride = 16'h0000;
+      assign write_sequence_number = 16'h0000; 
+      assign write_address[63:32] = 32'h00000000;    
+    end
+  endgenerate
+
+
+  // big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
+  assign write_command_data_out = {{132{1'b0}},  // zero pad the upper 132 bits
+                                  write_address[63:32],
+                                  write_stride,
+                                  write_burst_count,
+                                  write_sw_reset,
+                                  write_stop,
+                                  1'b0,  // used to be the early termination bit so now it's reserved
+                                  write_end_on_eop,
+                                  write_length,
+                                  write_address[31:0]};
+
+endmodule
diff --git a/FPGA_firmware/q_sys_bk.qsys b/FPGA_firmware/q_sys_bk.qsys
new file mode 100644
index 0000000..0bfbc99
--- /dev/null
+++ b/FPGA_firmware/q_sys_bk.qsys
@@ -0,0 +1,2547 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element algo_reconstruction_0
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+   }
+   element altpll_shift
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element button_pio
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element button_pio.s1
+   {
+      datum baseAddress
+      {
+         value = "406861152";
+         type = "String";
+      }
+   }
+   element channel_adapter_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element cpu
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element cpu.debug_mem_slave
+   {
+      datum baseAddress
+      {
+         value = "406857728";
+         type = "String";
+      }
+   }
+   element ddr3_ram
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element ddr3_ram.avl
+   {
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element ddr3_ram_resetn
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element debug_uart
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element debug_uart.s1
+   {
+      datum baseAddress
+      {
+         value = "406860832";
+         type = "String";
+      }
+   }
+   element descriptor_memory
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element descriptor_memory.s1
+   {
+      datum baseAddress
+      {
+         value = "406847488";
+         type = "String";
+      }
+   }
+   element dual_boot
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element dual_boot.avalon
+   {
+      datum baseAddress
+      {
+         value = "403846496";
+         type = "String";
+      }
+   }
+   element enet_pll
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element eth_tse
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element eth_tse.control_port
+   {
+      datum baseAddress
+      {
+         value = "406859776";
+         type = "String";
+      }
+   }
+   element ext_flash
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element ext_flash.avl_csr
+   {
+      datum baseAddress
+      {
+         value = "406861120";
+         type = "String";
+      }
+   }
+   element ext_flash.avl_mem
+   {
+      datum baseAddress
+      {
+         value = "335544320";
+         type = "String";
+      }
+   }
+   element ext_flash_clock_bridge
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element frame_timer
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
+   element frame_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "406860800";
+         type = "String";
+      }
+   }
+   element msgdma_rx
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element msgdma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "406861056";
+         type = "String";
+      }
+   }
+   element msgdma_rx.prefetcher_csr
+   {
+      datum baseAddress
+      {
+         value = "406860928";
+         type = "String";
+      }
+   }
+   element msgdma_tx
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element msgdma_tx.csr
+   {
+      datum baseAddress
+      {
+         value = "406861088";
+         type = "String";
+      }
+   }
+   element msgdma_tx.prefetcher_csr
+   {
+      datum baseAddress
+      {
+         value = "406860960";
+         type = "String";
+      }
+   }
+   element onchip_flash
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element onchip_flash.csr
+   {
+      datum baseAddress
+      {
+         value = "406861168";
+         type = "String";
+      }
+   }
+   element onchip_flash.data
+   {
+      datum baseAddress
+      {
+         value = "404750336";
+         type = "String";
+      }
+   }
+   element onchip_ram
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element onchip_ram.s1
+   {
+      datum baseAddress
+      {
+         value = "403767296";
+         type = "String";
+      }
+   }
+   element output_pio
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element output_pio.s1
+   {
+      datum baseAddress
+      {
+         value = "406860864";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element q_sys
+   {
+      datum _originalDeviceFamily
+      {
+         value = "MAX 10";
+         type = "String";
+      }
+   }
+   element sensor_interface
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element sensor_interface.csr
+   {
+      datum baseAddress
+      {
+         value = "406860992";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_clk_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "406860896";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sysid.clk
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum baseAddress
+      {
+         value = "406861176";
+         type = "String";
+      }
+   }
+   element tx_multiplexer
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element udp_generator
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element udp_generator.csr
+   {
+      datum baseAddress
+      {
+         value = "406861024";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="hit20v3.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altpll_shift_c0"
+   internal="altpll_shift.c0"
+   type="clock"
+   dir="start" />
+ <interface name="altpll_shift_c1" internal="altpll_shift.c1" />
+ <interface name="altpll_shift_c2" internal="altpll_shift.c2" />
+ <interface
+   name="altpll_shift_locked_conduit"
+   internal="altpll_shift.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="button_pio_external_connection"
+   internal="button_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="clock_bridge_0_in_clk"
+   internal="ext_flash_clock_bridge.in_clk"
+   type="clock"
+   dir="end" />
+ <interface name="ddr2_lo_latency_128m_auxfull" internal=".auxfull" />
+ <interface name="ddr2_lo_latency_128m_global_reset_n" internal=".global_reset_n" />
+ <interface name="ddr2_lo_latency_128m_memory" internal=".memory" />
+ <interface
+   name="debug_uart_external_connection"
+   internal="debug_uart.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="dipsw_pio_out" internal=".external_connection" />
+ <interface name="enet_pll_c0" internal="enet_pll.c0" type="clock" dir="start" />
+ <interface name="enet_pll_c1" internal="enet_pll.c1" type="clock" dir="start" />
+ <interface name="enet_pll_c2" internal="enet_pll.c2" type="clock" dir="start" />
+ <interface name="enet_pll_c3" internal="enet_pll.c3" type="clock" dir="start" />
+ <interface name="enet_pll_c4" internal="enet_pll.c4" type="clock" dir="start" />
+ <interface
+   name="enet_pll_locked_conduit"
+   internal="enet_pll.locked_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_mdio_connection"
+   internal="eth_tse.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_rgmii_connection"
+   internal="eth_tse.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_mac_status_connection"
+   internal="eth_tse.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_rx_clock_connection"
+   internal="eth_tse.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="eth_tse_pcs_mac_tx_clock_connection"
+   internal="eth_tse.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface name="eth_tse_serial_connection" internal="eth_tse.serial_connection" />
+ <interface
+   name="eth_tse_status_led_connection"
+   internal="eth_tse.status_led_connection" />
+ <interface
+   name="ext_flash_flash_dataout"
+   internal="ext_flash.flash_dataout"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_dclk_out"
+   internal="ext_flash.flash_dclk_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="ext_flash_flash_ncs"
+   internal="ext_flash.flash_ncs"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="frame_timer"
+   internal="frame_timer.external_port"
+   type="conduit"
+   dir="end" />
+ <interface name="jtag_avalon_master_clk_reset" internal=".clk_reset" />
+ <interface
+   name="led_pio_external_connection"
+   internal="output_pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_if_ddr3_emif_0_status"
+   internal="ddr3_ram.status"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="mem_resetn_in_reset"
+   internal="ddr3_ram_resetn.in_reset"
+   type="reset"
+   dir="end" />
+ <interface name="memory" internal="ddr3_ram.memory" type="conduit" dir="end" />
+ <interface name="ref_clk_clk_in" internal=".clk_in" />
+ <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface
+   name="sensor"
+   internal="sensor_interface.sensor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_status"
+   internal="sensor_interface.status_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_synchro"
+   internal="sensor_interface.synchro"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <module
+   name="algo_reconstruction_0"
+   kind="algo_reconstruction"
+   version="0"
+   enabled="1" />
+ <module name="altpll_shift" kind="altpll" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="15000" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_UNUSED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="button_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="9" />
+ </module>
+ <module
+   name="channel_adapter_0"
+   kind="channel_adapter"
+   version="19.1"
+   enabled="1">
+  <parameter name="inBitsPerSymbol" value="8" />
+  <parameter name="inChannelWidth" value="1" />
+  <parameter name="inErrorDescriptor" value="" />
+  <parameter name="inErrorWidth" value="1" />
+  <parameter name="inMaxChannel" value="1" />
+  <parameter name="inReadyLatency" value="0" />
+  <parameter name="inSymbolsPerBeat" value="4" />
+  <parameter name="inUseEmpty" value="false" />
+  <parameter name="inUseEmptyPort" value="YES" />
+  <parameter name="inUsePackets" value="true" />
+  <parameter name="inUseReady" value="true" />
+  <parameter name="outChannelWidth" value="0" />
+  <parameter name="outMaxChannel" value="1" />
+ </module>
+ <module name="cpu" kind="altera_nios2_gen2" version="19.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="12" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="12" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="29" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='frame_timer.s1' start='0x18403400' end='0x18403420' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403420' end='0x18403440' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403440' end='0x18403460' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403460' end='0x18403480' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403480' end='0x184034A0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x184034A0' end='0x184034C0' type='altera_msgdma.prefetcher_csr' /><slave name='sensor_interface.csr' start='0x184034C0' end='0x184034D0' type='Sensor_interface.csr' /><slave name='udp_generator.csr' start='0x184034E0' end='0x18403500' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403500' end='0x18403520' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403520' end='0x18403540' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403540' end='0x18403560' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403560' end='0x18403570' type='altera_avalon_pio.s1' /><slave name='onchip_flash.csr' start='0x18403570' end='0x18403578' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403578' end='0x18403580' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="2" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="288" />
+  <parameter name="exceptionSlave" value="ddr3_ram.avl" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="2048" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="instAddrWidth" value="29" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="61" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="3" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="ext_flash.avl_mem" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="0" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+   name="ddr3_ram"
+   kind="altera_mem_if_ddr3_emif"
+   version="19.1"
+   enabled="1">
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
+  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="AP_MODE" value="false" />
+  <parameter name="AP_MODE_EN" value="0" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL" value="false" />
+  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="FIX_READ_LATENCY" value="8" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="MEM_CLK_FREQ" value="300.0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_DQ_WIDTH" value="8" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_RTT_NOM" value="ODT Disabled" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_TCL" value="5" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="MEM_WTCL" value="5" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="RATE" value="Half" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="REFRESH_INTERVAL" value="15000" />
+  <parameter name="REF_CLK_FREQ" value="50.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="SPEED_GRADE" value="6" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="TREFI" value="35100" />
+  <parameter name="TRFC" value="350" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+ </module>
+ <module
+   name="ddr3_ram_resetn"
+   kind="altera_reset_bridge"
+   version="19.1"
+   enabled="1">
+  <parameter name="ACTIVE_LOW_RESET" value="1" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="NUM_RESET_OUTPUTS" value="1" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
+  <parameter name="USE_RESET_REQUEST" value="0" />
+ </module>
+ <module
+   name="debug_uart"
+   kind="altera_avalon_uart"
+   version="19.1"
+   enabled="1">
+  <parameter name="baud" value="115200" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+ </module>
+ <module
+   name="descriptor_memory"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_descriptor_memory</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName">/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex</parameter>
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="8192" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="dual_boot" kind="altera_dual_boot" version="19.1" enabled="0">
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+ </module>
+ <module name="enet_pll" kind="altpll" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="2" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="5" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="2" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="0" />
+  <parameter name="CLK2_DIVIDE_BY" value="20" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_MULTIPLY_BY" value="1" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_DIVIDE_BY" value="2" />
+  <parameter name="CLK3_DUTY_CYCLE" value="50" />
+  <parameter name="CLK3_MULTIPLY_BY" value="5" />
+  <parameter name="CLK3_PHASE_SHIFT" value="-3000" />
+  <parameter name="CLK4_DIVIDE_BY" value="2" />
+  <parameter name="CLK4_DUTY_CYCLE" value="50" />
+  <parameter name="CLK4_MULTIPLY_BY" value="1" />
+  <parameter name="CLK4_PHASE_SHIFT" value="-10000" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_USED" />
+  <parameter name="PORT_clk3" value="PORT_USED" />
+  <parameter name="PORT_clk4" value="PORT_USED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module name="eth_tse" kind="altera_eth_tse" version="19.1" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="enable_gmii_loopback" value="true" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="false" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="enable_sgmii" value="true" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="mdio_clk_div" value="40" />
+  <parameter name="nf_phyip_rcfg_enable" value="true" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="use_mac_clken" value="false" />
+  <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+   name="ext_flash"
+   kind="altera_generic_quad_spi_controller"
+   version="19.1"
+   enabled="1">
+  <parameter name="CHIP_SELS" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="FLASH_TYPE" value="Micron512" />
+  <parameter name="IO_MODE" value="QUAD" />
+  <parameter name="UNIQUE_ID">$${FILENAME}_ext_flash</parameter>
+  <parameter name="clkFreq" value="0" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module
+   name="ext_flash_clock_bridge"
+   kind="altera_clock_bridge"
+   version="19.1"
+   enabled="1">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   name="frame_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="5000" />
+  <parameter name="periodUnits" value="CLOCKS" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="false" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="true" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module name="msgdma_rx" kind="altera_msgdma" version="19.1" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="2" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module name="msgdma_tx" kind="altera_msgdma" version="19.1" enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"><![CDATA[<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
+  <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
+  <parameter name="BURST_ENABLE" value="0" />
+  <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
+  <parameter name="CHANNEL_ENABLE" value="0" />
+  <parameter name="CHANNEL_WIDTH" value="8" />
+  <parameter name="DATA_FIFO_DEPTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
+  <parameter name="ENHANCED_FEATURES" value="0" />
+  <parameter name="ERROR_ENABLE" value="1" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="EXPOSE_ST_PORT" value="0" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
+  <parameter name="MAX_BURST_COUNT" value="2" />
+  <parameter name="MAX_BYTE" value="2048" />
+  <parameter name="MAX_STRIDE" value="1" />
+  <parameter name="MODE" value="1" />
+  <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="1" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
+  <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
+  <parameter name="RESPONSE_PORT" value="2" />
+  <parameter name="STRIDE_ENABLE" value="0" />
+  <parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
+ </module>
+ <module
+   name="onchip_flash"
+   kind="altera_onchip_flash"
+   version="19.1"
+   enabled="1">
+  <parameter name="AUTO_CLOCK_RATE" value="50000000" />
+  <parameter name="CLOCK_FREQUENCY" value="50.0" />
+  <parameter name="CONFIGURATION_MODE">Single Uncompressed Image with Memory Initialization</parameter>
+  <parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
+  <parameter name="DATA_INTERFACE" value="Parallel" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="PART_NAME" value="10M50DAF484C6GES" />
+  <parameter name="READ_BURST_COUNT" value="8" />
+  <parameter name="READ_BURST_MODE" value="Incrementing" />
+  <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
+  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash</parameter>
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="initializationFileName">D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex</parameter>
+  <parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
+  <parameter name="useNonDefaultInitFile" value="false" />
+ </module>
+ <module
+   name="onchip_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="0">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName" value="q_sys_onchip_ram" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="output_pio" kind="altera_avalon_pio" version="19.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module
+   name="sensor_interface"
+   kind="Sensor_interface"
+   version="1.1"
+   enabled="1" />
+ <module name="sys_clk" kind="clock_source" version="19.1" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   name="sys_clk_timer"
+   kind="altera_avalon_timer"
+   version="19.1"
+   enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="10" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="19.1"
+   enabled="1">
+  <parameter name="id" value="-87110914" />
+ </module>
+ <module name="tx_multiplexer" kind="multiplexer" version="19.1" enabled="1">
+  <parameter name="bitsPerSymbol" value="8" />
+  <parameter name="errorWidth" value="1" />
+  <parameter name="numInputInterfaces" value="2" />
+  <parameter name="outChannelWidth" value="1" />
+  <parameter name="packetScheduling" value="true" />
+  <parameter name="schedulingSize" value="512" />
+  <parameter name="symbolsPerBeat" value="4" />
+  <parameter name="useHighBitsOfChannel" value="true" />
+  <parameter name="usePackets" value="true" />
+ </module>
+ <module name="udp_generator" kind="udp_generator" version="1.0" enabled="1" />
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="dual_boot.avalon">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18123560" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403540" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="eth_tse.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403578" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403520" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403500" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403570" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="udp_generator.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x184034e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sensor_interface.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x184034c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18402800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_tx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x184034a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="msgdma_rx.prefetcher_csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403460" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="output_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="button_pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403560" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="debug_uart.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403420" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="frame_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18403400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.data_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_read_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.descriptor_write_master"
+   end="descriptor_memory.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18400000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="ext_flash.avl_mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x14000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="onchip_flash.data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="cpu.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18402800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="cpu.instruction_master"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_tx.mm_read"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="ddr3_ram.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.1"
+   start="msgdma_rx.mm_write"
+   end="onchip_ram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x18110000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="sensor_interface.data_out"
+   end="algo_reconstruction_0.data_in" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="algo_reconstruction_0.data_out"
+   end="udp_generator.data_in" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="udp_generator.data_out"
+   end="tx_multiplexer.in1" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="tx_multiplexer.out"
+   end="channel_adapter_0.in" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="channel_adapter_0.out"
+   end="eth_tse.transmit" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="eth_tse.receive"
+   end="msgdma_rx.st_sink" />
+ <connection
+   kind="avalon_streaming"
+   version="19.1"
+   start="msgdma_tx.st_source"
+   end="tx_multiplexer.in0" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="sysid.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sys_clk_timer.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="cpu.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="output_pio.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="dual_boot.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="button_pio.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="debug_uart.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="onchip_flash.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="tx_multiplexer.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="channel_adapter_0.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="udp_generator.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="sensor_interface.clk" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="frame_timer.clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="descriptor_memory.clk1" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="onchip_ram.clk1" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_tx.clock" />
+ <connection kind="clock" version="19.1" start="sys_clk.clk" end="msgdma_rx.clock" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="algo_reconstruction_0.clock_sink" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.control_port_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="enet_pll.inclk_interface" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="altpll_shift.inclk_interface" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="ddr3_ram.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="sys_clk.clk"
+   end="eth_tse.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="19.1"
+   start="ext_flash_clock_bridge.out_clk"
+   end="ext_flash.clock_sink" />
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_tx.csr_irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="msgdma_rx.csr_irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="ext_flash.interrupt_sender">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="19.1"
+   start="cpu.irq"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="19.1" start="cpu.irq" end="debug_uart.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="dual_boot.nreset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="onchip_flash.nreset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sysid.reset" />
+ <connection kind="reset" version="19.1" start="sys_clk.clk_reset" end="cpu.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="button_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="debug_uart.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="tx_multiplexer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="channel_adapter_0.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="frame_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="onchip_ram.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_tx.reset_n" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="msgdma_rx.reset_n" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="algo_reconstruction_0.reset_sink" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="udp_generator.rst" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="sys_clk.clk_reset"
+   end="sensor_interface.rst" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ext_flash.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="output_pio.reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="descriptor_memory.reset1" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="eth_tse.reset_connection" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="cpu.debug_reset_request"
+   end="ddr3_ram.soft_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.global_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="altpll_shift.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="enet_pll.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="19.1"
+   start="ddr3_ram_resetn.out_reset"
+   end="ddr3_ram.soft_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
diff --git a/FPGA_firmware/q_sys_ddr3_ram_p0_summary.csv b/FPGA_firmware/q_sys_ddr3_ram_p0_summary.csv
new file mode 100644
index 0000000..2a4d413
--- /dev/null
+++ b/FPGA_firmware/q_sys_ddr3_ram_p0_summary.csv
@@ -0,0 +1,23 @@
+Core: q_sys_ddr3_ram_p0 - Instance: q_sys_inst|ddr3_ram
+Path, Setup Margin, Hold Margin
+"Address Command (Slow 1200mV 85C Model)",1.139,1.136
+"Bus Turnaround Time (Slow 1200mV 85C Model)",5.328,--
+"Core (Slow 1200mV 85C Model)",0.117,0.092
+"Core Recovery/Removal (Slow 1200mV 85C Model)",0.976,0.861
+"DQS vs CK (Slow 1200mV 85C Model)",1.805,1.736
+"Read Capture (Slow 1200mV 85C Model)",0.134,0.134
+"Write (Slow 1200mV 85C Model)",0.281,0.285
+"Address Command (Slow 1200mV 0C Model)",1.106,1.092
+"Bus Turnaround Time (Slow 1200mV 0C Model)",5.259,--
+"Core (Slow 1200mV 0C Model)",0.373,0.011
+"Core Recovery/Removal (Slow 1200mV 0C Model)",1.932,0.771
+"DQS vs CK (Slow 1200mV 0C Model)",1.781,1.707
+"Read Capture (Slow 1200mV 0C Model)",0.137,0.137
+"Write (Slow 1200mV 0C Model)",0.263,0.24
+"Address Command (Fast 1200mV 0C Model)",1.133,1.126
+"Bus Turnaround Time (Fast 1200mV 0C Model)",5.34,--
+"Core (Fast 1200mV 0C Model)",1.044,0.054
+"Core Recovery/Removal (Fast 1200mV 0C Model)",3.998,0.405
+"DQS vs CK (Fast 1200mV 0C Model)",1.051,1.799
+"Read Capture (Fast 1200mV 0C Model)",0.146,0.146
+"Write (Fast 1200mV 0C Model)",0.392,0.391
diff --git a/FPGA_firmware/q_sys_mem_if_ddr3_emif_0_p0_summary.csv b/FPGA_firmware/q_sys_mem_if_ddr3_emif_0_p0_summary.csv
new file mode 100644
index 0000000..32e3a93
--- /dev/null
+++ b/FPGA_firmware/q_sys_mem_if_ddr3_emif_0_p0_summary.csv
@@ -0,0 +1,23 @@
+Core: q_sys_mem_if_ddr3_emif_0_p0 - Instance: q_sys_inst|mem_if_ddr3_emif_0
+Path, Setup Margin, Hold Margin
+"Address Command (Slow 1200mV 85C Model)",0.912,0.909
+"Bus Turnaround Time (Slow 1200mV 85C Model)",4.874,--
+"Core (Slow 1200mV 85C Model)",-0.211,0.298
+"Core Recovery/Removal (Slow 1200mV 85C Model)",0.529,0.575
+"DQS vs CK (Slow 1200mV 85C Model)",1.731,1.584
+"Read Capture (Slow 1200mV 85C Model)",0.134,0.134
+"Write (Slow 1200mV 85C Model)",0.054,0.058
+"Address Command (Slow 1200mV 0C Model)",0.929,0.915
+"Bus Turnaround Time (Slow 1200mV 0C Model)",4.905,--
+"Core (Slow 1200mV 0C Model)",0.363,0.258
+"Core Recovery/Removal (Slow 1200mV 0C Model)",0.867,0.469
+"DQS vs CK (Slow 1200mV 0C Model)",1.747,1.598
+"Read Capture (Slow 1200mV 0C Model)",0.137,0.137
+"Write (Slow 1200mV 0C Model)",0.086,0.063
+"Address Command (Fast 1200mV 0C Model)",0.999,0.992
+"Bus Turnaround Time (Fast 1200mV 0C Model)",5.072,--
+"Core (Fast 1200mV 0C Model)",1.012,0.14
+"Core Recovery/Removal (Fast 1200mV 0C Model)",1.826,0.117
+"DQS vs CK (Fast 1200mV 0C Model)",1.051,1.665
+"Read Capture (Fast 1200mV 0C Model)",0.146,0.146
+"Write (Fast 1200mV 0C Model)",0.258,0.257
diff --git a/FPGA_firmware/quartus.ini b/FPGA_firmware/quartus.ini
new file mode 100644
index 0000000..d09a26d
--- /dev/null
+++ b/FPGA_firmware/quartus.ini
@@ -0,0 +1 @@
+PGMIO_SWAP_HEX_BYTE_DATA=ON
diff --git a/FPGA_firmware/rgmii_sdc/rgmii_clocks.sdc b/FPGA_firmware/rgmii_sdc/rgmii_clocks.sdc
new file mode 100644
index 0000000..4cace44
--- /dev/null
+++ b/FPGA_firmware/rgmii_sdc/rgmii_clocks.sdc
@@ -0,0 +1,90 @@
+#
+# This file is intended to be sourced from a top.sdc
+# It contains references to TCL variables that are defined in the top.sdc
+#
+
+post_message -type info "Reading file: \'rgmii_clocks.sdc\'"
+
+# Set the periods of the clocks used in the design
+set PERIOD_125 8.0
+set PERIOD_25 [expr 8.0 * 5]
+set PERIOD_2p5 [expr 8.0 * 50]
+
+# Create the erx_clk on the port
+create_clock \
+    -name enet_rx_clk \
+    -period $PERIOD_125 \
+    [get_ports {enet_rx_clk}]
+
+# Create the external virtual PHY clock
+create_clock \
+    -name virtual_phy_clk \
+    -period $PERIOD_125 \
+
+# Define the clocks that can appear on the output of the TX clock mux
+# Create the 125MHz mux output
+create_generated_clock \
+    -name tx_clk_125 \
+    -source [get_pins "$enet_pll_125"] \
+    [get_pins {tx_clk_to_the_tse_mac|combout}]
+
+# Create the 25MHz mux output
+create_generated_clock \
+    -name tx_clk_25 \
+    -source [get_pins "$enet_pll_25"] \
+    -add \
+    [get_pins {tx_clk_to_the_tse_mac|combout}]
+
+# Create the 2.5MHz mux output
+create_generated_clock \
+    -name tx_clk_2p5 \
+    -source [get_pins "$enet_pll_2p5"] \
+    -add \
+    [get_pins {tx_clk_to_the_tse_mac|combout}]
+
+# All of the mux outputs are exclusive
+set_clock_groups \
+    -exclusive \
+    -group [get_clocks {tx_clk_125}] \
+    -group [get_clocks {tx_clk_25}] \
+    -group [get_clocks {tx_clk_2p5}]
+    
+# Create the 125Mhz etx_clk output
+create_generated_clock \
+    -name enet_gtx_clk_125 \
+    -source [get_pins {tx_clk_to_the_tse_mac|combout}] \
+    -master_clock {tx_clk_125} \
+    [get_ports {enet_gtx_clk}]
+    
+
+# Create the 25Mhz etx_clk output
+create_generated_clock \
+    -name enet_gtx_clk_25 \
+    -source [get_pins {tx_clk_to_the_tse_mac|combout}] \
+    -master_clock {tx_clk_25} \
+    -add \
+    [get_ports {enet_gtx_clk}]
+    
+# Create the 2p5Mhz etx_clk output
+create_generated_clock \
+    -name enet_gtx_clk_2p5 \
+    -source [get_pins {tx_clk_to_the_tse_mac|combout}] \
+    -master_clock {tx_clk_2p5} \
+    -add \
+    [get_ports {enet_gtx_clk}]
+
+# Cut all the unrelated clock transfers to the external clocks
+set_clock_groups -exclusive \
+    -group [get_clocks {tx_clk_125}] \
+    -group [get_clocks {enet_gtx_clk_25 enet_gtx_clk_2p5}]
+    
+set_clock_groups -exclusive \
+    -group [get_clocks {tx_clk_25}] \
+    -group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_2p5}]
+    
+set_clock_groups -exclusive \
+    -group [get_clocks {tx_clk_2p5}] \
+    -group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25}]
+
+# This path does not need to be constrained
+set_false_path -to [get_ports {enet_gtx_clk}]
diff --git a/FPGA_firmware/rgmii_sdc/rgmii_input.sdc b/FPGA_firmware/rgmii_sdc/rgmii_input.sdc
new file mode 100644
index 0000000..58a6362
--- /dev/null
+++ b/FPGA_firmware/rgmii_sdc/rgmii_input.sdc
@@ -0,0 +1,63 @@
+#
+# This file is intended to be sourced from a top.sdc
+#
+
+post_message -type info "Reading file: \'rgmii_input.sdc\'"
+
+#**************************************************************
+# Input Delay Constraints (Center aligned, Same Edge Analysis)
+#**************************************************************
+#set Tco_max 0.350	Changed M.D. 2019.10.07
+#set Tco_min -0.350
+set Tco_max 0.9
+set Tco_min -1.3
+
+#set Td_max 1.0 Changed M.D. 2019.10.07
+#set Td_min 0.9
+set Td_max 1.6
+set Td_min 1.5
+
+set longest_src_clk 0.0
+set shortest_src_clk 0.0
+set longest_dest_clk 1.0
+set shortest_dest_clk 0.9
+
+set Tcs_largest [expr $shortest_dest_clk - $longest_src_clk]
+set Tcs_smallest [expr $longest_dest_clk - $shortest_src_clk]
+
+set IMD [expr $Td_max + $Tco_max - $Tcs_largest]
+post_message -type info "Input Max Delay = $IMD"
+set ImD [expr $Td_min + $Tco_min - $Tcs_smallest]
+post_message -type info "Input Min Delay = $ImD"
+
+# Constraint the path to the rising edge of the phy clock
+set_input_delay -add_delay -clock virtual_phy_clk -max $IMD [get_ports {enet_rx_dv enet_rx_d*}]
+set_input_delay -add_delay -clock virtual_phy_clk -min $ImD [get_ports {enet_rx_dv enet_rx_d*}]
+
+# Constraint the path to the falling edge of the phy clock
+set_input_delay -add_delay -clock virtual_phy_clk -max -clock_fall $IMD [get_ports {enet_rx_dv enet_rx_d*}]
+set_input_delay -add_delay -clock virtual_phy_clk -min -clock_fall $ImD [get_ports {enet_rx_dv enet_rx_d*}]
+
+# On a same edge capture DDR interface the paths from RISE to FALL and
+# from FALL to RISE on not valid for setup analysis
+set_false_path \
+    -setup \
+    -rise_from [get_clocks {virtual_phy_clk}] \
+    -fall_to [get_clocks {enet_rx_clk}]
+
+set_false_path \
+    -setup \
+    -fall_from [get_clocks {virtual_phy_clk}] \
+    -rise_to [get_clocks {enet_rx_clk}]
+
+# On a same edge capture DDR interface the paths from RISE to RISE and
+# FALL to FALL are not avlid for hold analysis
+set_false_path \
+    -hold \
+    -rise_from [get_clocks {virtual_phy_clk}] \
+    -rise_to [get_clocks {enet_rx_clk}]
+
+set_false_path \
+    -hold \
+    -fall_from [get_clocks {virtual_phy_clk}] \
+    -fall_to [get_clocks {enet_rx_clk}]
diff --git a/FPGA_firmware/rgmii_sdc/rgmii_output.sdc b/FPGA_firmware/rgmii_sdc/rgmii_output.sdc
new file mode 100644
index 0000000..cb6d3d2
--- /dev/null
+++ b/FPGA_firmware/rgmii_sdc/rgmii_output.sdc
@@ -0,0 +1,90 @@
+#
+# This file is intended to be sourced from a top.sdc
+#
+
+post_message -type info "Reading file: \'rgmii_output.sdc\'"
+
+#**************************************************************
+# Output Delay Constraints (Edge Aligned, Same Edge Capture)
+#**************************************************************
+# Create the output constraints related to the ext_clk withn 125MHz is selected
+#set Tsu [expr (-1 * $PERIOD_125/4) + 0.35]
+#set Th [expr ($PERIOD_125/4) + 0.35]
+set Tsu 1.0
+set Th  0.8
+set Td_max 0.0
+set Td_min 0.0
+set longest_src_clk 0.0
+set shortest_src_clk 0.0
+set longest_dest_clk 0.0
+set shortest_dest_clk 0.0
+
+set Tcs_largest [expr $shortest_dest_clk - $longest_src_clk]
+set Tcs_smallest [expr $longest_dest_clk - $shortest_src_clk]
+
+set OMD [expr $Td_max + $Tsu - $Tcs_largest]
+set OmD [expr $Td_min - $Th - $Tcs_smallest]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_125] -max $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_125] -min $OmD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_125] -max -clock_fall $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_125] -min -clock_fall $OmD [get_ports {enet_tx_en enet_tx_d*}]
+
+# Create the output constraints related to the ext_clk withn 25MHz is selected
+#set Tsu [expr (-1 * $PERIOD_25/4) + 0.35]
+#set Th [expr ($PERIOD_25/4) + 0.35]
+set Tsu 1.0
+set Th  0.8
+set OMD [expr $Td_max + $Tsu - $Tcs_largest]
+set OmD [expr $Td_min - $Th - $Tcs_smallest]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_25] -max $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_25] -min $OmD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_25] -max -clock_fall $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_25] -min -clock_fall $OmD [get_ports {enet_tx_en enet_tx_d*}]
+
+# Create the output constraints related to the ext_clk withn 2p5MHz is selected
+#set Tsu [expr (-1 * $PERIOD_2p5/4) + 0.35]
+#set Th [expr ($PERIOD_2p5/4) + 0.35]
+set Tsu 1.0
+set Th  0.8
+set OMD [expr $Td_max + $Tsu - $Tcs_largest]
+set OmD [expr $Td_min - $Th - $Tcs_smallest]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_2p5] -max $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_2p5] -min $OmD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_2p5] -max -clock_fall $OMD [get_ports {enet_tx_en enet_tx_d*}]
+set_output_delay -add_delay -clock [get_clocks enet_gtx_clk_2p5] -min -clock_fall $OmD [get_ports {enet_tx_en enet_tx_d*}]
+
+
+# On same edge capture DDR interface the paths from RISE to FALL and
+# from FALL to RISE on not valid for setup analysis
+set_false_path \
+    -setup \
+    -rise_from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+    -fall_to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+
+set_false_path \
+    -setup \
+    -fall_from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+    -rise_to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+
+# On same edge capture DDR interface the paths from RISE to RISE and
+# FALL to FALL are not valid for hold analysis
+set_false_path \
+    -hold \
+    -rise_from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+    -rise_to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+
+set_false_path \
+    -hold \
+    -fall_from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+    -fall_to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}]
+
+#set_multicycle_path 0 \
+#    -from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+#    -to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}] \
+#    -setup \
+#    -end
+#set_multicycle_path -1 \
+#    -from [get_clocks {tx_clk_125 tx_clk_25 tx_clk_2p5}] \
+#    -to [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25 enet_gtx_clk_2p5}] \
+#    -hold \
+#    -end
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram.xml
new file mode 100644
index 0000000..89483ff
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram.xml
@@ -0,0 +1,2185 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="3" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="2" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="1" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="-1" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="0" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Parameters">
+									<replacement id="dockablesingle Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram_schematic.nlv b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram_schematic.nlv
new file mode 100644
index 0000000..16f6d2a
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/cali_ram_schematic.nlv
@@ -0,0 +1,8 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst unsaved.clk_0 -pg 1 -lvl 1 -y 30
+preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)clk_0.clk_in_reset,(SLAVE)unsaved.reset) 1 0 1 NJ
+levelinfo -pg 1 0 50 270
+levelinfo -hier unsaved 60 90 260
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/filters.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/filters.xml
new file mode 100644
index 0000000..9927661
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="19.1" />
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/preferences.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/preferences.xml
new file mode 100644
index 0000000..d610355
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/preferences.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+   <name preferredWidth="241" />
+   <export preferredWidth="243" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Library,Project" />
+ <window width="1920" height="1017" x="0" y="64" />
+ <generation path="q_sys" />
+</preferences>
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo.xml
new file mode 100644
index 0000000..64639f1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo.xml
@@ -0,0 +1,2167 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.2900523560209424">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="1" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="3" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6019202363367798">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="0" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="4" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="2" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Parameters">
+										<replacement id="dockablesingle Parameters"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Parameters</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo_schematic.nlv b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo_schematic.nlv
new file mode 100644
index 0000000..178975c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_algo_schematic.nlv
@@ -0,0 +1,12 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst sensor_algo.cali_fac -pg 1 -lvl 1 -y 30
+preplace inst sensor_algo -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)sensor_algo.cali_fac_s1,(SLAVE)cali_fac.s1) 1 0 1 NJ
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)cali_fac.clk1,(SLAVE)sensor_algo.cali_fac_clk1) 1 0 1 NJ
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)cali_fac.reset1,(SLAVE)sensor_algo.cali_fac_reset1) 1 0 1 NJ
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)sensor_algo.cali_fac_clk2,(SLAVE)cali_fac.clk2) 1 0 1 NJ
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)cali_fac.reset2,(SLAVE)sensor_algo.cali_fac_reset2) 1 0 1 NJ
+preplace netloc EXPORT<net_container>sensor_algo</net_container>(SLAVE)sensor_algo.cali_fac_s2,(SLAVE)cali_fac.s2) 1 0 1 NJ
+levelinfo -pg 1 0 110 240
+levelinfo -hier sensor_algo 120 150 230
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon.xml
new file mode 100644
index 0000000..67b18d1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon.xml
@@ -0,0 +1,2185 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="2" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="0" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="3" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="-1" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="1" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Parameters">
+									<replacement id="dockablesingle Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon_schematic.nlv b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/sensor_recon_schematic.nlv
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16.xml
new file mode 100644
index 0000000..67b18d1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16.xml
@@ -0,0 +1,2185 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="2" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="0" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="3" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="-1" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="1" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Parameters">
+									<replacement id="dockablesingle Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16_schematic.nlv b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16_schematic.nlv
new file mode 100644
index 0000000..0c00078
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/st_splitter16_schematic.nlv
@@ -0,0 +1,8 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst unsaved.clk_0 -pg 1 -lvl 1 -y 30
+preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)clk_0.clk_in_reset,(SLAVE)unsaved.reset) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)clk_0.clk_in,(SLAVE)unsaved.clk) 1 0 1 NJ
+levelinfo -pg 1 0 50 270
+levelinfo -hier unsaved 60 90 260
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved.xml b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved.xml
new file mode 100644
index 0000000..7f9ede7
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved.xml
@@ -0,0 +1,2185 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="1" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="3" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="2" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="-1" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="0" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>2</index>
+									<placeholder>dock.single.Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Parameters">
+									<replacement id="dockablesingle Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved_schematic.nlv b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved_schematic.nlv
new file mode 100644
index 0000000..f46b208
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/.qsys_edit/unsaved_schematic.nlv
@@ -0,0 +1,14 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst unsaved.sensor_recon_0 -pg 1 -lvl 1 -y 30
+preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>unsaved</net_container>(MASTER)sensor_recon_0.data_out,(MASTER)unsaved.sensor_recon_0_data_out) 1 1 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.sensor_recon_0_synchro,(SLAVE)sensor_recon_0.synchro) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.sensor_recon_0_rst,(SLAVE)sensor_recon_0.rst) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.sensor_recon_0_status_out,(SLAVE)sensor_recon_0.status_out) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.sensor_recon_0_sensor,(SLAVE)sensor_recon_0.sensor) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.sensor_recon_0_csr,(SLAVE)sensor_recon_0.csr) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)sensor_recon_0.clk,(SLAVE)unsaved.sensor_recon_0_clk) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(MASTER)unsaved.sensor_recon_0_calibration_ram_interface,(MASTER)sensor_recon_0.calibration_ram_interface) 1 1 1 NJ
+levelinfo -pg 1 0 170 650
+levelinfo -hier unsaved 180 210 430
diff --git a/FPGA_firmware/sensor_algo_qsys/algo_top.v b/FPGA_firmware/sensor_algo_qsys/algo_top.v
new file mode 100644
index 0000000..a95ccd2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/algo_top.v
@@ -0,0 +1,91 @@
+// module algo_top
+
+//bkg + stl2sts tested by algo_top_tb.v
+module algo_top(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // ?? word only with data
+	output  wire [15:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+	
+);
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[2:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	
+	bkg_subtraction #(.BKG_FRAME(4)) bkg_subtraction0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0)
+		
+	);
+	
+
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	
+	
+endmodule
+	
+	
+	
+	
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/algo_top_cl.v b/FPGA_firmware/sensor_algo_qsys/algo_top_cl.v
new file mode 100644
index 0000000..6be5e48
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/algo_top_cl.v
@@ -0,0 +1,125 @@
+//module algo_top_cl
+
+module algo_top_cl(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // ?? word only with data
+	output  wire [15:0] data_out_data,           //  st.data
+	//input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket,  //         .startofpacket	
+	
+	//for cluster => will be in register map
+	input wire [15:0] CL_THRESHOLD,
+	input wire [15:0] CL_SIZE
+	
+);
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[2:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	
+	bkg_subtraction #(.BKG_FRAME(4)) bkg_subtraction0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0)
+		
+	);
+	
+	
+	wire data_out_ready; 
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire has_cluster;
+	wire no_cluster;
+	
+	
+	
+	cluster_locate cluster_locate0(
+		
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_out_data),
+		.data_in_ready		(data_out_ready),
+		.data_in_valid		(data_out_valid),
+		.data_in_empty		(data_out_empty),
+		.data_in_startofpacket		(data_out_startofpacket),
+		.data_in_endofpacket			(data_out_endofpacket),
+		
+		.THRESHOLD			(CL_THRESHOLD),
+		.SIZE					(CL_SIZE),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster)	
+	
+	); 
+
+	
+	
+endmodule
+	
+	
+	
+	
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali.v b/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali.v
new file mode 100644
index 0000000..07c6a89
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali.v
@@ -0,0 +1,206 @@
+//module algo_top_cl_cali
+//combine bkg_subtraction, cluster_locate, and calibration
+
+//tested with algo_top_cl_cali_tb
+module algo_top_cl_cali(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+//	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // ?? word only with data
+//	output  wire [15:0] data_out_data,           //  st.data
+//	//input   wire        data_out_ready,          //         .ready
+//	output  wire        data_out_valid,          //         .valid
+//	output  wire [1:0]  data_out_empty,          //         .empty
+//	output  wire        data_out_endofpacket,    //         .endofpacket
+//	output  wire        data_out_startofpacket,  //         .startofpacket	
+//	
+	//for cluster => will be in register map
+	input wire [15:0] CL_THRESHOLD,
+	input wire [15:0] CL_SIZE,
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac
+	
+);
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[1:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	
+	bkg_subtraction_pipe #(.BKG_FRAME(4)) bkg_subtraction0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0)
+		
+	);
+	
+	
+	wire [15:0] wire_data1;
+	wire 			wire_ready1;
+	wire			wire_valid1;
+	wire	      wire_empty1;
+	wire			wire_endofpacket1;
+	wire			wire_startofpacket1;
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(wire_data1),
+		.data_out_empty	(wire_empty1),
+		.data_out_endofpacket		(wire_endofpacket1),
+		.data_out_startofpacket		(wire_startofpacket1),
+		.data_out_ready	(wire_ready1),
+		.data_out_valid	(wire_valid1)
+		
+	);
+	
+		//from st_splitter0 to cluster_locate
+		wire [15:0] wire_data2;
+		wire 			wire_ready2;
+		wire			wire_valid2;
+		wire	      wire_empty2;
+		wire			wire_endofpacket2;
+		wire			wire_startofpacket2;
+		
+		//from st_splitter0 to calibration
+		wire [15:0] wire_data3;
+		wire 			wire_ready3;
+		wire			wire_valid3;
+		wire	      wire_empty3;
+		wire			wire_endofpacket3;
+		wire			wire_startofpacket3;
+	
+	st_splitter16 st_splitter0 (
+		.st_splitter16_clk_clk            (clk),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (rst),        // st_splitter16_reset.reset
+		
+		
+		.st_splitter16_in_ready           (wire_ready1),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (wire_valid1),           //                    .valid
+		.st_splitter16_in_startofpacket   (wire_startofpacket1),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (wire_endofpacket1),     //                    .endofpacket
+		.st_splitter16_in_empty           (wire_empty1),           //                    .empty
+		.st_splitter16_in_data            (wire_data1),            //                    .data
+		
+		
+		.st_splitter16_out0_ready         (wire_ready2),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (wire_valid2),         //                    .valid
+		.st_splitter16_out0_startofpacket (wire_startofpacket2), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (wire_endofpacket2),   //                    .endofpacket
+		.st_splitter16_out0_empty         (wire_empty2),         //                    .empty
+		.st_splitter16_out0_data          (wire_data2),          //                    .data
+		
+		
+		.st_splitter16_out1_ready         (wire_ready3),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (wire_valid3),         //                    .valid
+		.st_splitter16_out1_startofpacket (wire_startofpacket3), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (wire_endofpacket3),   //                    .endofpacket
+		.st_splitter16_out1_empty         (wire_empty3),         //                    .empty
+		.st_splitter16_out1_data          (wire_data3)           //                    .data
+	);
+
+
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire has_cluster;
+	wire no_cluster;
+	
+	cluster_locate cluster_locate0(
+		
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data2),
+		.data_in_ready		(wire_ready2),
+		.data_in_valid		(wire_valid2),
+		.data_in_empty		(wire_empty2),
+		.data_in_startofpacket		(wire_startofpacket2),
+		.data_in_endofpacket			(wire_endofpacket2),
+		
+		.THRESHOLD			(CL_THRESHOLD),
+		.SIZE					(CL_SIZE),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster)	
+	
+	); 
+	
+	
+	wire[8:0]		data_caled_address;
+	wire [31:0]		data_caled;
+
+	
+	
+	calibration calibration0(
+	
+	.clk(clk),
+	.rst(rst),
+		
+	.data_in_data		(wire_data3),
+	.data_in_ready		(wire_ready3),
+	.data_in_valid		(wire_valid3),
+	.data_in_empty		(wire_empty3),
+	.data_in_startofpacket		(wire_startofpacket3),
+	.data_in_endofpacket			(wire_endofpacket3),
+	
+	.address		(address),
+	.clken		(clken),
+	.cali_fac	(cali_fac),
+	
+	.data_caled_address(data_caled_address),
+	.data_caled(data_caled)
+	);
+
+	
+	
+endmodule
+	
+	
+	
+	
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali_rms.v b/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali_rms.v
new file mode 100644
index 0000000..2c9db87
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/algo_top_cl_cali_rms.v
@@ -0,0 +1,352 @@
+//module algo_top_cl_cali_rms
+//combine bkg_subtraction, cluster_locate, and calibration, and rms
+
+//tested with algo_top_cl_cali_rms_tb.v
+module algo_top_cl_cali_rms(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // 3 + 160 + 4 = 167 words * 32bit 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket , //         .startofpacket	
+	
+
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+
+	//for cluster => will be in register map
+	input wire [7:0] 		CL_THRESHOLD,
+	input wire [7:0] 		CL_SIZE,
+	input wire [7:0]		IN_ALGO_THRESHOLD,
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest
+	
+);
+	//avalon source for header 
+	wire [31:0] header_data;
+	wire			header_ready;
+	wire [1:0]	header_empty;
+	wire			header_endofpacket;
+	wire			header_startofpacket;
+	wire			header_valid;
+	
+	//avalon source for channel data
+	wire [31:0] channel_data;
+	wire			channel_ready;
+	wire [1:0]	channel_empty;
+	wire			channel_endofpacket;
+	wire			channel_startofpacket;
+	wire			channel_valid;
+	
+	//avalon source for result
+	wire [31:0] recon_data;
+	wire			recon_ready;
+	wire [1:0]	recon_empty;
+	wire			recon_endofpacket;
+	wire			recon_startofpacket;
+	wire			recon_valid;
+	
+	/******************** merge three data source together *****************************************/
+	reg [1:0] avalon_sender_state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_HEADER = 2'd1;
+	localparam STATE_CHANNEL = 2'd3;
+	localparam STATE_RECON = 2'd2;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			avalon_sender_state <= STATE_IDLE;
+		end
+		else case(avalon_sender_state)
+		STATE_IDLE:
+		begin
+			if (header_startofpacket)
+				avalon_sender_state <= STATE_HEADER;
+		end
+		STATE_HEADER:
+		begin
+			if (channel_startofpacket)
+				avalon_sender_state <= STATE_CHANNEL;
+		end
+		STATE_CHANNEL:
+		begin
+			if (recon_startofpacket)
+				avalon_sender_state <= STATE_RECON;
+		end
+		STATE_RECON:
+		begin
+			if (recon_endofpacket && to_udp_ready)
+				avalon_sender_state <= STATE_IDLE;
+		end
+		default:
+			avalon_sender_state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	assign to_udp_data = (avalon_sender_state == STATE_HEADER)? header_data: (avalon_sender_state == STATE_CHANNEL)? channel_data: (avalon_sender_state == STATE_RECON)? recon_data: 32'd0;
+	assign header_ready = (avalon_sender_state == STATE_HEADER)? to_udp_ready: 1'b0;
+	assign channel_ready = (avalon_sender_state == STATE_CHANNEL)? to_udp_ready: 1'b0;
+	assign recon_ready = (avalon_sender_state == STATE_RECON)? to_udp_ready: 1'b0;
+	
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (avalon_sender_state == STATE_HEADER)? header_startofpacket: 1'b0;
+	assign to_udp_endofpacket = (avalon_sender_state == STATE_RECON)? recon_endofpacket: 1'b0;
+	assign to_udp_valid = (avalon_sender_state == STATE_HEADER)? header_valid: (avalon_sender_state == STATE_CHANNEL)? channel_valid: (avalon_sender_state == STATE_RECON)? recon_valid: 1'b0;
+	
+		
+	
+	
+	
+	
+	
+	
+	
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[1:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	wire			bkg_sub_on;
+	
+	bkg_subtraction_pipe #(.BKG_FRAME(8192)) bkg_subtraction0( //4 for simulation, 8192 for real firmware setup
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0),
+		.bkg_sub_on			(bkg_sub_on),
+		
+		
+		//3 header
+		.to_udp_data (header_data),           
+		.to_udp_ready(header_ready),          
+		.to_udp_valid (header_valid),          
+		.to_udp_empty (header_empty),          
+		.to_udp_endofpacket (header_endofpacket),    
+		.to_udp_startofpacket (header_startofpacket)
+		
+		
+		
+	);
+	
+	
+	wire [15:0] wire_data1;
+	wire 			wire_ready1;
+	wire			wire_valid1;
+	wire	      wire_empty1;
+	wire			wire_endofpacket1;
+	wire			wire_startofpacket1;
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(wire_data1),
+		.data_out_empty	(wire_empty1),
+		.data_out_endofpacket		(wire_endofpacket1),
+		.data_out_startofpacket		(wire_startofpacket1),
+		.data_out_ready	(wire_ready1),
+		.data_out_valid	(wire_valid1)
+		
+	);
+	
+		//from st_splitter0 to cluster_locate
+		wire [15:0] wire_data2;
+		wire 			wire_ready2;
+		wire			wire_valid2;
+		wire	      wire_empty2;
+		wire			wire_endofpacket2;
+		wire			wire_startofpacket2;
+		
+		//from st_splitter0 to calibration
+		wire [15:0] wire_data3;
+		wire 			wire_ready3;
+		wire			wire_valid3;
+		wire	      wire_empty3;
+		wire			wire_endofpacket3;
+		wire			wire_startofpacket3;
+	
+	st_splitter16 st_splitter0 (
+		.st_splitter16_clk_clk            (clk),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (rst),        // st_splitter16_reset.reset
+		
+		
+		.st_splitter16_in_ready           (wire_ready1),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (wire_valid1),           //                    .valid
+		.st_splitter16_in_startofpacket   (wire_startofpacket1),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (wire_endofpacket1),     //                    .endofpacket
+		.st_splitter16_in_empty           (wire_empty1),           //                    .empty
+		.st_splitter16_in_data            (wire_data1),            //                    .data
+		
+		
+		.st_splitter16_out0_ready         (wire_ready2),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (wire_valid2),         //                    .valid
+		.st_splitter16_out0_startofpacket (wire_startofpacket2), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (wire_endofpacket2),   //                    .endofpacket
+		.st_splitter16_out0_empty         (wire_empty2),         //                    .empty
+		.st_splitter16_out0_data          (wire_data2),          //                    .data
+		
+		
+		.st_splitter16_out1_ready         (wire_ready3),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (wire_valid3),         //                    .valid
+		.st_splitter16_out1_startofpacket (wire_startofpacket3), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (wire_endofpacket3),   //                    .endofpacket
+		.st_splitter16_out1_empty         (wire_empty3),         //                    .empty
+		.st_splitter16_out1_data          (wire_data3)           //                    .data
+	);
+
+
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire has_cluster;
+	wire no_cluster;
+	
+	wire cl_last_channel;
+	cluster_locate cluster_locate0(
+		
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data2),
+		.data_in_ready		(wire_ready2),
+		.data_in_valid		(wire_valid2),
+		.data_in_empty		(wire_empty2),
+		.data_in_startofpacket		(wire_startofpacket2),
+		.data_in_endofpacket			(wire_endofpacket2),
+		
+		.THRESHOLD			({8'b0,CL_THRESHOLD}),
+		.SIZE					({1'b0,CL_SIZE}),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+	
+		.data_in_last		(cl_last_channel)
+	
+	); 
+	
+	
+	wire[8:0]		data_caled_address;
+	wire [15:0]		data_caled;
+	wire				data_caled_rd_enable;
+
+	//when bkg_sub_on is off, it equals to 8192.... the scaled 1 for calibration factor
+	wire [15:0] cali_fac_masked = bkg_sub_on? cali_fac:16'd8192;
+	calibration calibration0(
+	
+	.clk(clk),
+	.rst(rst),
+		
+	.data_in_data		(wire_data3),
+	.data_in_ready		(wire_ready3),
+	.data_in_valid		(wire_valid3),
+	.data_in_empty		(wire_empty3),
+	.data_in_startofpacket		(wire_startofpacket3),
+	.data_in_endofpacket			(wire_endofpacket3),
+	
+	.address		(address),
+	.clken		(clken),
+	.cali_fac	(cali_fac_masked),
+	.waitrequest(waitrequest),
+	
+	.data_caled_address(data_caled_address),
+	.data_caled(data_caled),
+	.data_caled_rd_enable(data_caled_rd_enable),
+
+	.to_udp_data (channel_data),           
+	.to_udp_ready(channel_ready),          
+	.to_udp_valid (channel_valid),          
+	.to_udp_empty (channel_empty),          
+	.to_udp_endofpacket (channel_endofpacket),    
+	.to_udp_startofpacket (channel_startofpacket)
+
+	);
+
+	
+	rms rms0(
+
+
+		.clk(clk),
+		.rst(rst),
+
+		.bkg_sub_on			(bkg_sub_on),
+		.sig_ram_last		(cl_last_channel),
+
+		.sig_rdaddress(data_caled_address),            
+		.sig(data_caled),
+		.sig_rd_eable(data_caled_rd_enable),
+
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+
+		.to_udp_data (recon_data),           
+		.to_udp_ready(recon_ready),          
+		.to_udp_valid (recon_valid),          
+		.to_udp_empty (recon_empty),          
+		.to_udp_endofpacket (recon_endofpacket),    
+		.to_udp_startofpacket (recon_startofpacket)
+
+
+	);
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/bkg_ram.sv b/FPGA_firmware/sensor_algo_qsys/bkg_ram.sv
new file mode 100644
index 0000000..987828d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/bkg_ram.sv
@@ -0,0 +1,130 @@
+/*
+The ram provides the background signal.
+when frameID is 1, reset ram content to 0
+frameID is 2~1+TOTAL_FRAME, sum the signal store in the ram
+when rameID is TOTAL_FRAME+2, output the background signal
+The TOTAL_FRAME has to be the power of 2, and it belongs to [2,65536]
+In general, TOTAL_FRAME = 8192
+*/
+
+
+
+module bkg_ram #(parameter TOTAL_FRAME = 4)
+(
+
+	input wire clk_clk,
+	input wire rst_reset,
+	input wire enable,
+	
+	input wire[26:0] frameID,
+	
+	input wire [7:0] address, 
+	input  wire [31:0] data_in_data,
+	input wire 		data_in_valid,
+	output wire [31:0] bkg_signal,
+	output wire bkg_sub_status
+	); 
+	
+	wire wren;
+	reg[7:0] wraddress_buffer; //delay address 3 clocks
+	//reg[31:0] reg_data_in; //delay data_in_data 1 clocks
+
+	
+	wire[31:0] q_sig1; //output from ram
+	wire[31:0] data_sig1; //write in the ram
+	reg[31:0] reg_sum1;
+	
+	wire[31:0] q_sig2;
+	wire[31:0] data_sig2;
+	reg[31:0] reg_sum2;
+
+	//	localparam TOTAL_FRAME = 8192; //2^13= 8192
+	//	localparam SHIFG_BIT = 13; 
+	
+	//for fast simulation
+	//localparam TOTAL_FRAME = 4; //2^2= 4
+	localparam SHIFT_BIT = $clog2(TOTAL_FRAME); 
+	
+	ram4bkg ram4bkg1 (
+    .data(data_sig1),
+    .rdaddress(address),
+    .clock(clk_clk),
+    .wraddress(wraddress_buffer),
+    .wren(wren),
+    .q(q_sig1)
+  );
+  
+  ram4bkg ram4bkg2 (
+    .data(data_sig2),
+    .rdaddress(address),
+    .clock(clk_clk),
+    .wraddress(wraddress_buffer),
+    .wren(wren),
+    .q(q_sig2)
+  );
+  
+  reg[1:0] states;
+  localparam STATE_IDLE = 0;
+  localparam STATE_RAM_RST = 1;
+  localparam STATE_BKG_ADD = 3;
+  localparam STATE_BKG_OUT = 2;
+  
+  assign bkg_sub_status = (states==STATE_BKG_OUT)? 1'b1:1'b0;
+  
+  always @(posedge clk_clk or posedge rst_reset)
+  begin
+   if (rst_reset)
+		states <= STATE_IDLE;
+	else if (frameID <=27'd1)
+		states <= STATE_RAM_RST;
+	else if (frameID >TOTAL_FRAME+1)
+		states <= STATE_BKG_OUT;
+	else 
+		states <= STATE_BKG_ADD;
+	end
+		
+	assign bkg_signal[31:16] = (states==STATE_BKG_OUT)?q_sig1[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	assign bkg_signal[15:0] = (states==STATE_BKG_OUT)?q_sig2[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+
+   assign wren = (states==STATE_RAM_RST || states==STATE_BKG_ADD)? 1'b1: 1'b0;
+	assign data_sig1 = (states==STATE_BKG_ADD)? reg_sum1: 0;
+	assign data_sig2 = (states==STATE_BKG_ADD)? reg_sum2: 0;
+	
+	
+	
+	always @(posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			reg_sum1 <= 0;
+			//reg_data_in[1] <= 0;
+			wraddress_buffer <= 0;
+			reg_sum2 <= 0;
+
+		end
+		else 
+			case(states)
+				STATE_IDLE:
+				begin
+					reg_sum1 <= 0;
+					//reg_data_in[1] <= 0;
+					reg_sum2 <= 0;
+
+				end
+				STATE_BKG_ADD:
+				begin
+					if (data_in_valid)
+					begin
+						//reg_data_in <= data_in_data;
+						reg_sum1 <= q_sig1 + data_in_data[31:16];
+						reg_sum2 <= q_sig2 + data_in_data[15:0];
+						wraddress_buffer <= address;
+					end
+				end
+				STATE_RAM_RST:
+					wraddress_buffer[0] <= address;
+			endcase
+	end
+	
+	
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/bkg_subtraction.v b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction.v
new file mode 100644
index 0000000..471848d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction.v
@@ -0,0 +1,217 @@
+//background subtraction module
+
+//tested with bkg_subtraction_tb.v
+module bkg_subtraction #(parameter BKG_FRAME = 4)(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
+	output  wire [31:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+	
+	//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it?  26.June. 2024
+);
+	
+	wire bkg_sub_on;
+	wire rst_frame = data_in_startofpacket; 
+	
+	/************************* Frame Counter***********************************/
+	/*
+	This is a frame counter; 
+	frameID +1 at the rising edge of data_in_startofpacket
+	if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
+	*/
+	reg [26:0] frameID;
+	reg data_in_startofpacket_last;
+	
+	always @(posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			data_in_startofpacket_last <= 1'b0;
+			frameID<= 27'b0;
+		end
+		else 
+		begin
+			data_in_startofpacket_last <= data_in_startofpacket;
+			if (~data_in_startofpacket_last && data_in_startofpacket)
+				frameID<= frameID + 1'b1; 
+		end
+	end
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 5'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 5'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 5'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 5'd3;	//sending third word :				
+	localparam STATE_DATA_PRO	= 5'd4;	//blocking data get bkg_signal; and do the subtraction
+	localparam STATE_DATA_NEXT  = 5'd7;  //sending data
+	localparam STATE_LOC	= 5'd5;	//calculatebb
+	
+	
+	//Helper stuff
+	reg	[7:0]	tx_ctr;	//counter of sent data words range: 0~255
+	localparam WORDS_TO_SEND = 163;
+
+	//the number of clocks for STATE_DATA_PRO
+	reg [5:0] delay_ctr;
+	localparam DELAY_CLOCKS = 6'd2; 
+	
+	/************** bkg RAM ****************************/
+	/*
+	for prepare the bkg signal by two RAM;
+	one for data_in_data[31:16]; the other for data_in_data[15:0]
+	the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
+	*/
+
+	wire[15:0] bkgH;
+	wire[15:0] bkgL;
+
+	wire[31:0] bkg_input_data;
+	wire		  bkg_input_valid;
+	assign	  bkg_input_valid = (state == STATE_DATA_NEXT && data_out_ready);
+	//assign	  bkg_input_valid = 1'b1;
+	
+	//signal after subtract background
+	//got the background signal at the third clock in STATE_DATA_PRO
+	//and subtract it to 16 bit by giving up the LSM, i.e. divide 2. 
+	reg [16:0] signal0_17bit;
+	reg [16:0] signal1_17bit;
+	wire[15:0] signal0;
+	wire[15:0] signal1;
+	
+	assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
+	assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
+	
+	bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_ram0(
+		.clk_clk(clk),
+		.rst_reset(rst),
+		.frameID(frameID[26:0]),
+		.address(tx_ctr), 
+		.data_in_data(bkg_input_data),
+		.data_in_valid(bkg_input_valid),
+		.bkg_signal({bkgH,bkgL}),
+		.bkg_sub_status(bkg_sub_on)
+	); 
+	
+	assign bkg_input_data = (state==STATE_DATA_NEXT)?data_in_data:15'b0;
+	
+	wire data_out_ready_for3header = 1'b1; 
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+						tx_ctr <= 0;
+					end
+				end
+				STATE_WORD0:
+				begin
+				if (data_in_valid && data_out_ready_for3header)
+					begin
+					state <= STATE_WORD1;
+					tx_ctr <= tx_ctr+ 1'b1;
+					end
+				end
+				STATE_WORD1:
+				begin
+				if (data_in_valid && data_out_ready_for3header)
+					begin
+					state <= STATE_WORD2;
+					tx_ctr <= tx_ctr +1'b1;
+					end
+				end
+				STATE_WORD2:
+				begin
+				if (data_in_valid && data_out_ready_for3header)
+					begin
+					state <= STATE_DATA_PRO;
+					tx_ctr <= tx_ctr +1'b1;
+					delay_ctr <= DELAY_CLOCKS -1'b1;
+					end
+				end
+				STATE_DATA_PRO:
+				begin
+					if (data_in_valid)
+					begin
+						delay_ctr <= delay_ctr -1'b1;
+						if (delay_ctr == 0)
+						begin
+							state <= STATE_DATA_NEXT;
+							delay_ctr <= DELAY_CLOCKS - 1'b1;
+							signal0_17bit <= {1'b0, data_in_data[31:16]}-{1'b0,bkgH};
+							signal1_17bit <= {1'b0, data_in_data[15:0]}-{1'b0,bkgL};
+						end
+					end
+				end
+				STATE_DATA_NEXT:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1'b1;
+						if (tx_ctr == WORDS_TO_SEND -1)	//last word, size matches
+							state <= STATE_LOC;
+						else
+							state <= STATE_DATA_PRO;
+					end
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+	//output 163 words
+	//assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready; 
+	//assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1'b1 : 1'b0; 
+	//the output data is be reversed....so during transfer without signal it's FFFFF, the software HIT-DAQ will reverse it again
+	//assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
+	//								(state == STATE_DATA_NEXT)? {signal0,signal1}: 0;
+	//assign data_out_startofpacket = data_in_startofpacket;	
+	//assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;	
+	//assign data_out_empty = 0;
+	
+	//output 160 words
+	assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) || (state == STATE_DATA_NEXT && data_out_ready); 
+	assign data_out_valid = (state == STATE_DATA_NEXT) ? 1'b1 : 1'b0; 
+	assign data_out_data = (state == STATE_DATA_NEXT)? {signal0,signal1}: 0;
+	assign data_out_startofpacket = (state == STATE_DATA_NEXT && tx_ctr == 8'd3)? 1'b1: 1'b0;
+	assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;
+   assign data_out_empty = 0;	
+
+
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v
new file mode 100644
index 0000000..cbc6521
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/bkg_subtraction_pipe.v
@@ -0,0 +1,312 @@
+//background subtraction module
+
+//tested with algo_top_cl_cali_tb.v with bkg_subtraction_pipe
+//tested with bkg_subtraction_pipe_tb
+
+//okay... it is not really pipe.... has to read a ram after use the previous output of this ram 
+
+module bkg_subtraction_pipe #(parameter BKG_FRAME = 4)(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
+	output  wire [31:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket,  //         .startofpacket	
+	
+	output wire				bkg_sub_on,
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //3 headers 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it?  26.June. 2024
+);
+	localparam SHIFT_BIT = $clog2(BKG_FRAME); 
+	
+	wire rst_frame = data_in_startofpacket; 
+	
+	wire data_out_ready_for3header = to_udp_ready;
+	
+	/************************* Frame Counter***********************************/
+	/*
+	This is a frame counter; 
+	frameID +1 at the rising edge of data_in_startofpacket
+	if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
+	*/
+	reg [26:0] frameID;
+	reg data_in_startofpacket_last;
+	
+	always @(posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			data_in_startofpacket_last <= 1'b0;
+			frameID<= 27'b0;
+		end
+		else 
+		begin
+			data_in_startofpacket_last <= data_in_startofpacket;
+			if (~data_in_startofpacket_last && data_in_startofpacket)
+				frameID<= frameID + 1'b1; 
+		end
+	end
+	
+	//**********************bkg_subtraction or not *****************
+	
+  reg[1:0] state_bkg;
+  localparam STATE_BKG_IDLE = 0;
+  localparam STATE_RAM_RST = 1;
+  localparam STATE_BKG_ADD = 3;
+  localparam STATE_BKG_OUT = 2;
+  
+  assign bkg_sub_on = (state_bkg == STATE_BKG_OUT)? 1'b1:1'b0;
+  
+  always @(posedge clk or posedge rst)
+  begin
+   if (rst)
+		state_bkg <= STATE_BKG_IDLE;
+	else if (frameID <=27'd1)
+		state_bkg <= STATE_RAM_RST;
+	else if (frameID >BKG_FRAME+1)
+		state_bkg <= STATE_BKG_OUT;
+	else 
+		state_bkg <= STATE_BKG_ADD;
+	end
+	
+	
+	
+	/************** bkg RAM ****************************/
+	/*
+	for prepare the bkg signal by two RAM;
+	one for data_in_data[31:16]; the other for data_in_data[15:0]
+	the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
+	*/
+	
+	reg[8:0] rdaddress; //for read ram
+	reg[8:0] wraddress;
+	wire		wren;
+	
+	//data_in_data + ram0_q
+	reg[31:0] ram0_data;
+	reg[31:0] ram1_data;
+	
+	wire[31:0] ram0_q;
+	wire[31:0] ram1_q;
+	
+	
+	
+	ram4bkg ram4bkg0 (
+    .data(ram0_data), //32 bits
+    .rdaddress(rdaddress),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram0_q) //32 bits
+  );
+  
+  ram4bkg ram4bkg1 (
+    .data(ram1_data), //32 bits
+    .rdaddress(rdaddress),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram1_q) //32 bits
+  );
+	
+	wire[15:0] bkg0;
+	wire[15:0] bkg1;
+	
+	assign bkg0 = bkg_sub_on?ram0_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	assign bkg1 = bkg_sub_on?ram1_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	
+
+	
+	//data_in_data - bkg0
+	reg[16:0] data0_sub;
+	reg[16:0] data1_sub;
+	
+	//data_in_data
+	wire[15:0] data0_in_data;
+	wire[15:0] data1_in_data;
+	
+	//reverse the polarity of ADC signal for calculation => no for simulation
+	assign data0_in_data = ~data_in_data[31:16];
+	assign data1_in_data = ~data_in_data[15:0];
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[3:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 4'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 4'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 4'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 4'd3;	//sending third word :
+	localparam STATE_RDRAM0 = 4'd4; //wait to read the first channel of ram
+	localparam STATE_INPUT0 = 4'd5; //data_in_ready do sub and sum
+	localparam STATE_RDRAM1 = 4'd6; //data_in_data is ready to output, data_out_startofpacket is high; read next ram
+	localparam STATE_INPUT = 4'd7; //data_in_ready do sub and sum for next
+	localparam STATE_RDRAM = 4'd8;
+	localparam STATE_OUTPUT_LAST = 4'd9; //output last, data_out_endofpacket is high
+	localparam STATE_LOC	= 4'd10;	//
+
+	
+	wire state_bkg_valid;
+	wire state_data_valid;
+	// Check if state_bkg is either STATE_RAM_RST or STATE_BKG_ADD for write
+	assign state_bkg_valid = (state_bkg == STATE_RAM_RST) || (state_bkg == STATE_BKG_ADD);
+	// Check if state is STATE_DATA and both data_in_valid and data_out_ready are true
+	assign state_data_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST);
+
+	// Final wren assignment combining the conditions
+	assign wren = (state_bkg_valid && state_data_valid)? 1'b1 : 1'b0;
+
+	
+	
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					rdaddress <= 0;
+					wraddress <= 0; 
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+					end
+				end
+				STATE_WORD0:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD1;
+					end
+				end
+				STATE_WORD1:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD2;
+					end
+				end
+				STATE_WORD2:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_RDRAM0;
+						rdaddress <= 0;
+					end
+				end
+				STATE_RDRAM0:
+				begin
+					state <= STATE_INPUT0;
+				end
+				STATE_INPUT0:
+				begin
+					if (data_in_valid)
+					begin
+						state <= STATE_RDRAM1;
+						rdaddress <= rdaddress + 1'b1;
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+					end
+				end
+				STATE_RDRAM1:
+				begin
+				if (data_out_ready)
+					state <= STATE_INPUT;
+				end
+				STATE_INPUT:
+				begin
+					if (data_in_valid)
+					begin
+						if (data_in_endofpacket)
+							state <= STATE_OUTPUT_LAST;
+						else
+							state <= STATE_RDRAM;
+						rdaddress <= rdaddress + 1'b1;
+						wraddress <= wraddress + 1'b1;
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+					end
+				end
+				STATE_RDRAM:
+				begin
+					if (data_out_ready)
+						state <= STATE_INPUT;
+				end
+				STATE_OUTPUT_LAST:
+				begin
+					if (data_out_ready)
+						state <= STATE_LOC;
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+
+	//output 160 words
+	assign data_in_ready = ((state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) && data_out_ready_for3header) || (state == STATE_INPUT) ||(state == STATE_INPUT0); 
+	assign data_out_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0; 
+	assign data_out_data = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST)? (bkg_sub_on? {data0_sub[16:1],data1_sub[16:1]}: {data0_sub[15:0],data1_sub[15:0]}):0;
+	assign data_out_startofpacket = (state == STATE_RDRAM1)? 1'b1: 1'b0;
+	assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;
+   assign data_out_empty = 0;	
+
+	//output the 3 header to upd
+	assign to_udp_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:0;
+	assign to_udp_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_valid: 1'b0;
+	assign to_udp_empty = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_empty: 2'b0;
+	assign to_udp_startofpacket = data_in_startofpacket;
+	assign to_udp_endofpacket = (state == STATE_WORD2)?data_in_valid: 1'b0;
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/cali_ram.qsys b/FPGA_firmware/sensor_algo_qsys/cali_ram.qsys
new file mode 100644
index 0000000..aebd76b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/cali_ram.qsys
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element cali_ram
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="cali_ram_clk1" internal="cali_ram.clk1" type="clock" dir="end" />
+ <interface name="cali_ram_clk2" internal="cali_ram.clk2" type="clock" dir="end" />
+ <interface
+   name="cali_ram_reset1"
+   internal="cali_ram.reset1"
+   type="reset"
+   dir="end" />
+ <interface
+   name="cali_ram_reset2"
+   internal="cali_ram.reset2"
+   type="reset"
+   dir="end" />
+ <interface name="cali_ram_s1" internal="cali_ram.s1" type="avalon" dir="end" />
+ <interface name="cali_ram_s2" internal="cali_ram.s2" type="avalon" dir="end" />
+ <module
+   name="cali_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_cali_ram</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/FPGA_firmware/sensor_algo_qsys/cali_ram.sopcinfo b/FPGA_firmware/sensor_algo_qsys/cali_ram.sopcinfo
new file mode 100644
index 0000000..3d42a60
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/cali_ram.sopcinfo
@@ -0,0 +1,1491 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="cali_ram" kind="cali_ram" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.02.15:49:42 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1719928182</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk1</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk1</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK1_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk1</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk2</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk2</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CALI_RAM_CLK2_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>cali_ram_clk2</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="cali_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="cali_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>cali_ram_cali_ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>640</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>16</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>cali_ram_cali_ram</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>onchip_mem.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>640</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>cali_ram_cali_ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>cali_ram_cali_ram.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="s2" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address2</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>chipselect2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>clken2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>write2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata2</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata2</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable2</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk2" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset2" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_onchip_memory2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/calibration.v b/FPGA_firmware/sensor_algo_qsys/calibration.v
new file mode 100644
index 0000000..568dfbc
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/calibration.v
@@ -0,0 +1,233 @@
+//module calibration has two functions: calibration and merge 16-bit stream to 32-bit stream and then output
+//calibration output 16-bit data_caled
+//a better design is a design seperate these two functions
+//tested by calibration_tb 25.07.2024
+
+module calibration
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input  wire signed[15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	output wire [8:0] 	address,
+	output wire 			clken, //read
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest,
+	
+	//the interface for provide the calibrated data in a ram // one clock latency
+	input  wire [8:0]			data_caled_address,
+	output wire [15:0]		data_caled,
+	input  wire					data_caled_rd_enable, // to enable read
+	
+	output wire					data_in_last, //....
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 * 32 bits data  
+	// channel 0 [31:16] channel 1 [15:0]
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	localparam SHIFT_BIT = 13; //2^13 = 8192, the calibration factor 1 is represented by 8192 
+	
+	//for to_udp_data
+	reg [15:0] first_data_buffer;
+	
+	//for read calibration ram
+	reg [8:0]  	read_cali_address;
+	reg signed[16:0]   cali_fac_buffer;
+	wire read;
+	assign clken = read;
+	assign address = read_cali_address;
+	
+	//for write and read the calibrated data
+	reg signed[31:0]	data_caled_data_32bit;
+	wire 			data_caled_wren_a;
+	reg [8:0]	data_caled_address_a;
+	wire [8:0]	address_b;
+	assign		address_b = (data_caled_rd_enable)? data_caled_address: 9'd0;
+	wire[15:0]	data_caled_data_a;
+	assign data_caled_data_a = {data_caled_data_32bit[31],data_caled_data_32bit[14+SHIFT_BIT:SHIFT_BIT]};
+	
+	
+	data_caled_ram	data_caled_ram0 (
+		
+		.clock ( clk ),
+		
+		.address_a (data_caled_address_a),
+		.data_a (data_caled_data_a),
+		.wren_a (data_caled_wren_a),
+		.q_a ( ),
+
+		.address_b ( address_b ),
+		.data_b ( ),
+		.wren_b (1'b0),
+		.q_b ( data_caled)
+		);
+		
+	//the state machine for read calibration factor from ram
+	reg[3:0] state;
+	localparam STATE_IDLE = 4'd0; //waiting for startofpacket
+	localparam STATE_CAL0 = 4'd1; //get califactor for channel0
+	localparam STATE_INPUT0 = 4'd2; // stream in data for channel0;
+	localparam STATE_CAL1 = 4'd3; // get califactor for channel1
+	localparam STATE_INPUT1 = 4'd4; // stream in data for channel1;
+	localparam STATE_CAL2 = 4'd5; //get califactor for channel1; output the first 32-bit udp data [channel0, channel1]
+	localparam STATE_INPUT_EVEN = 4'd6; // stream in data for channel 2,4,6.....
+	localparam STATE_CAL_ODD = 4'd7; 
+	localparam STATE_INPUT_ODD = 4'd8;
+	localparam STATE_CAL_EVEN = 4'd9;
+	localparam STATE_OUTPUT_LAST = 4'd10; //outout the last 32-bit udp data 
+	
+
+	assign data_in_ready = (state == STATE_INPUT0 || state == STATE_INPUT1 || state == STATE_INPUT_EVEN || state == STATE_INPUT_ODD)?1'b1:1'b0;
+	assign data_caled_wren_a = (state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD || state == STATE_OUTPUT_LAST)?1'b1:1'b0;
+	assign read = (state == STATE_CAL0 ||state == STATE_CAL1 || state == STATE_CAL2 || state == STATE_CAL_EVEN || state == STATE_CAL_ODD)?1'b1:1'b0;
+	
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			data_caled_address_a <= 0;
+			read_cali_address <= 0; 
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			data_caled_address_a <= 0;
+			read_cali_address <= 0; 
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_CAL0;
+			end
+		end
+		STATE_CAL0:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT0;
+			end
+		end
+		STATE_INPUT0:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= 16'd0;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				state <= STATE_CAL1;
+			end
+		end
+		STATE_CAL1:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT1;
+			end
+		end
+		STATE_INPUT1:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= data_caled_data_a;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				state <= STATE_CAL2;
+			end
+		end
+		STATE_CAL2:
+		begin
+			if (~waitrequest & to_udp_ready) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_EVEN;
+			end
+		end
+		STATE_INPUT_EVEN:
+		begin
+			if (data_in_valid) 
+			begin
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				first_data_buffer <= 16'd0;
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				if (data_in_endofpacket)
+					state <= STATE_OUTPUT_LAST;
+				else
+					state <= STATE_CAL_ODD;
+			end
+		end
+		STATE_CAL_ODD:
+		begin
+			if (~waitrequest) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_ODD;
+			end
+		end
+		STATE_INPUT_ODD:
+		begin
+			if (data_in_valid) 
+			begin
+				first_data_buffer <= data_caled_data_a;
+				data_caled_data_32bit <= data_in_data*cali_fac_buffer;
+				//data_caled_data_32bit <= cali_fac_buffer;// test! cali 
+				read_cali_address <= read_cali_address + 1'b1;
+				data_caled_address_a <= data_caled_address_a + 1'b1;
+				if (data_in_endofpacket)
+					state <= STATE_OUTPUT_LAST;
+				else
+					state <= STATE_CAL_EVEN;
+			end
+		end
+		STATE_CAL_EVEN:
+		begin
+			if (~waitrequest & to_udp_ready) begin
+				cali_fac_buffer <= {1'b0,cali_fac};
+				state <= STATE_INPUT_EVEN;
+			end
+		end
+		STATE_OUTPUT_LAST: 
+		begin
+			if (to_udp_ready)
+				state <= STATE_IDLE;
+		end
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	//output the 160 32bit words to upd, first channel [31:16] , second channel [15:16]
+	//output  wire [31:0] to_udp_data,           //  st.data
+	assign to_udp_valid = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_CAL2 && (~waitrequest))? 1'b1:1'b0;
+	assign to_udp_endofpacket = (state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+	//reverse the polarity for output => no for simulation
+	assign to_udp_data = (((state == STATE_CAL2 || state == STATE_CAL_EVEN) && (~waitrequest))|| state == STATE_OUTPUT_LAST) ? {~first_data_buffer,~data_caled_data_a}: 32'b0; 
+	
+	
+	
+	
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv b/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv
new file mode 100644
index 0000000..698db7a
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/cluster_locate.sv
@@ -0,0 +1,186 @@
+/*
+CLUSTER LOCATE:
+if there is continuous [equal or more than SIZE]signals above THRESHOLD, there is cluster;
+The STATE_FIRST_CLUSTER find the left position of the Cluster; sig_ch_left
+if there is more than one cluster, the STATE_LAST_CLUSTER determine the right position of the Cluster; sig_ch_right
+When the address is 319, it goes to output state:
+the has_cluster, no_cluster, sig_ch_left and sig_ch_right keep for two clocks
+*/
+
+//the interface tested  by algo_top_cl_tb.v
+//the detailed math precise tested by cluster_locate_tb.v
+
+module cluster_locate // #(parameter THRESHOLD=54, SIZE=4)
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input logic signed [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+
+	input wire[15:0] THRESHOLD, //range 0~255
+	input wire[8:0] SIZE,	//range 0~255
+	
+	output wire[8:0] sig_ch_left,
+	output wire[8:0] sig_ch_right,
+	output wire has_cluster,
+	output wire no_cluster,
+	
+	output wire data_in_last //.... after this, there is has_cluster of no_cluster signal
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	localparam CHANNEL_NUM = 320;
+	reg signed[15:0] REG_THRESHOLD;
+	reg unsigned[8:0] REG_SIZE;
+	
+	reg[2:0] states;
+	localparam STATE_IDLE = 3'b000;
+	localparam STATE_REC = 3'b001;
+	localparam STATE_FIRST_CLUSTER = 3'b011;
+	localparam STATE_LAST_CLUSTER = 3'b010;
+	localparam STATE_HAS_CLUSTER = 3'b110;
+	localparam STATE_NO_CLUSTER = 3'b111;
+	localparam STATE_HAS_CLUSTER_KEEP = 3'b101;
+	localparam STATE_NO_CLUSTER_KEEP = 3'b100;
+	
+	reg unsigned[8:0] size_ctr; //the same as the channel
+	reg[8:0] ch_left;
+	reg[8:0] ch_right;
+	reg[8:0] address; 
+	
+	
+	assign sig_ch_left = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_left: 9'd0;
+	assign sig_ch_right = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_right: 9'd0;
+	assign has_cluster = (states==STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? 1'b1: 1'b0;
+	assign no_cluster = (states==STATE_NO_CLUSTER || states == STATE_NO_CLUSTER_KEEP)? 1'b1 : 1'b0;
+	
+	assign data_in_ready = (states == STATE_REC || states == STATE_FIRST_CLUSTER || states == STATE_LAST_CLUSTER)? 1'b1: 1'b0;
+	
+	wire data_over_th;  /* synthesis keep */
+	assign data_over_th = (data_in_data > REG_THRESHOLD)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			ch_left <= 0;
+			ch_right <= 0;
+			address <= 0; 
+			size_ctr <= 0;
+			states <= STATE_IDLE;
+			REG_THRESHOLD <= THRESHOLD;
+			REG_SIZE <= SIZE; 
+		end
+		else
+			case(states)
+				STATE_IDLE:
+				begin
+					ch_left <= 0;
+					ch_right <= 0;
+					address <= 0; 
+					size_ctr <= 0;
+					REG_THRESHOLD <= THRESHOLD;
+					REG_SIZE <= SIZE;
+					if (data_in_startofpacket)
+						states <= STATE_REC;
+				end
+				STATE_REC:
+				begin
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket) 
+							states <= STATE_NO_CLUSTER;
+						else if (data_over_th)
+						begin
+							size_ctr <= size_ctr + 1'b1;
+							states <= STATE_FIRST_CLUSTER;
+							ch_left <= address;
+						end
+					end	
+				end
+				STATE_FIRST_CLUSTER:
+				begin
+					if (data_in_valid) 
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+							if ((size_ctr + data_over_th) > REG_SIZE)
+							begin
+								states <= STATE_HAS_CLUSTER;
+								ch_right <= address;
+							end else
+								states <= STATE_NO_CLUSTER;
+						end
+						else if (data_over_th)
+							size_ctr <= size_ctr + 1'b1;
+						else   
+						begin
+							size_ctr <= 0;
+							if (size_ctr > REG_SIZE)
+							begin
+								states <= STATE_LAST_CLUSTER;
+								ch_right <= address -1'b1;
+							end else
+							begin
+								states <= STATE_REC;
+								ch_left <= 0; 
+							end
+						end
+					end
+				end
+				STATE_LAST_CLUSTER:
+				begin	
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+						states <= STATE_HAS_CLUSTER;
+						if ((size_ctr + data_over_th) > REG_SIZE)
+							ch_right <= address - ~data_over_th; //2024.09.30 ch_right <= address - ~data_over_th;
+						end	
+						else if (data_over_th)
+							size_ctr<= size_ctr + 1'b1;
+						else 
+						begin
+							if (size_ctr > REG_SIZE)
+								ch_right <= address-1'b1;
+							size_ctr <= 0;
+						end
+					end
+				end
+				STATE_HAS_CLUSTER:
+				begin
+					states <= STATE_HAS_CLUSTER_KEEP;
+				end
+				STATE_NO_CLUSTER:
+				begin
+					states <= STATE_NO_CLUSTER_KEEP;
+				end
+				STATE_HAS_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				STATE_NO_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				default:
+					states <= STATE_IDLE;
+			endcase		
+	end
+
+endmodule
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/cluster_locate.v b/FPGA_firmware/sensor_algo_qsys/cluster_locate.v
new file mode 100644
index 0000000..7dfd543
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/cluster_locate.v
@@ -0,0 +1,165 @@
+/*
+CLUSTER LOCATE:
+The total CHANNEL_NUM is 320; 
+if there is continuous [equal or more than SIZE]signals above THRESHOLD, there is cluster;
+The STATE_FIRST_CLUSTER find the left position of the Cluster; sig_ch_left
+if there is more than one cluster, the STATE_LAST_CLUSTER determine the right position of the Cluster; sig_ch_right
+When the address is 319, it goes to output state:
+the has_cluster, no_cluster, sig_ch_left and sig_ch_right keep for two clocks
+*/
+
+
+module cluster_locate #(parameter THRESHOLD=54, SIZE=4)
+(
+
+	input wire clk_clk,
+	input wire rst_reset, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input  logic signed [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+
+	
+	output wire[8:0] sig_ch_left,
+	output wire[8:0] sig_ch_right,
+	output wire has_cluster,
+	output wire no_cluster
+);
+	
+	reg[8:0] address; 
+	localparam CHANNEL_NUM = 320;
+	reg signed[15:0] REG_THRESHOLD;
+	reg signed[15:0] REG_SIZE;
+	
+	reg[6:0] states;
+	localparam STATE_IDLE = 7'b1;
+	localparam STATE_FIRST_CLUSTER = 7'b10;
+	localparam STATE_LAST_CLUSTER = 7'b100;
+	localparam STATE_HAS_CLUSTER = 7'b1000;
+	localparam STATE_NO_CLUSTER = 7'b10000;
+	localparam STATE_HAS_CLUSTER_KEEP = 7'b100000;
+	localparam STATE_NO_CLUSTER_KEEP = 7'b1000000;
+	
+	reg[8:0] size_ctr; //the same as the channel
+	reg[8:0] ch_left;
+	reg[8:0] ch_right;
+	
+	
+	assign sig_ch_left = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_left: 9'd0;
+	assign sig_ch_right = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_right: 9'd0;
+	assign has_cluster = (states==STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? 1'b1: 1'b0;
+	assign no_cluster = (states==STATE_NO_CLUSTER || states == STATE_NO_CLUSTER_KEEP)? 1'b1 : 1'b0;
+	
+	assign data_in_ready = (states == STATE_FIRST_CLUSTER || states == STATE_LAST_CLUSTER)? 1'b1: 1'b0;
+	
+	wire data_over_th;  /* synthesis keep */
+	assign data_over_th = (data_in_data > REG_THRESHOLD)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			ch_left <= 0;
+			ch_right <= 0;
+			states <= STATE_IDLE;
+			REG_THRESHOLD <= THRESHOLD;
+			REG_SIZE <= SIZE; 
+		end
+		else
+			case(states)
+				STATE_IDLE:
+				begin
+					ch_left <= 0;
+					ch_right <= 0;
+					REG_THRESHOLD <= THRESHOLD;
+					REG_SIZE <= SIZE; 
+					if (data_in_valid)
+					begin
+						if (data_in_endofpacket) 
+							states <= STATE_NO_CLUSTER;
+						else if (data_over_th) 
+						begin
+							states <= STATE_FIRST_CLUSTER;
+							size_ctr <= 1;
+							ch_left <= address;
+						end
+					end	
+				end
+				STATE_FIRST_CLUSTER:
+				begin
+					if (data_in_endofpacket)
+					begin
+						if (size_ctr > REG_SIZE)
+						begin
+							states <= STATE_HAS_CLUSTER;
+							ch_right <= address;
+						end
+						else
+							states <= STATE_NO_CLUSTER;
+					end
+					else if (data_in_valid)
+					begin
+						if (data_over_th)
+							size_ctr <= size_ctr + 1'b1;
+						else 
+						begin
+							if (size_ctr > REG_SIZE)
+							begin
+								states <= STATE_LAST_CLUSTER;
+								size_ctr <= 0;
+								ch_right <= address -1'b1;
+							end
+							else
+								states <= STATE_IDLE;
+						end
+					end
+				end
+				STATE_LAST_CLUSTER:
+				begin				
+					 if (data_in_endofpacket)
+					 begin
+						states <= STATE_HAS_CLUSTER;
+						if (size_ctr > REG_SIZE)
+							ch_right <= address;
+					 end	
+					 else if (data_in_valid)
+					 begin
+						if (data_over_th)
+							size_ctr<= size_ctr + 1'b1;
+						else
+						begin
+							if (size_ctr > REG_SIZE)
+								ch_right <= address-1'b1;
+							size_ctr <= 0;
+						end
+					 end
+				end
+				STATE_HAS_CLUSTER:
+				begin
+					states <= STATE_HAS_CLUSTER_KEEP;
+				end
+				STATE_NO_CLUSTER:
+				begin
+					states <= STATE_NO_CLUSTER_KEEP;
+				end
+				STATE_HAS_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				STATE_NO_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				default:
+					states <= STATE_IDLE;
+			endcase		
+	end
+
+endmodule
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/data_caled_ram.qip b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.qip
new file mode 100644
index 0000000..0276769
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "data_caled_ram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_bb.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v
new file mode 100644
index 0000000..dc286ee
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/data_caled_ram.v
@@ -0,0 +1,243 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: data_caled_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module data_caled_ram (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[15:0]  data_a;
+	input	[15:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire [15:0] sub_wire1;
+	wire [15:0] q_a = sub_wire0[15:0];
+	wire [15:0] q_b = sub_wire1[15:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (data_a),
+				.data_b (data_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 16,
+		altsyncram_component.width_b = 16,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/data_caled_ram_bb.v b/FPGA_firmware/sensor_algo_qsys/data_caled_ram_bb.v
new file mode 100644
index 0000000..7057d6e
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/data_caled_ram_bb.v
@@ -0,0 +1,180 @@
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: data_caled_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module data_caled_ram (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[15:0]  data_a;
+	input	[15:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/data_caled_ram_inst.v b/FPGA_firmware/sensor_algo_qsys/data_caled_ram_inst.v
new file mode 100644
index 0000000..93d2834
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/data_caled_ram_inst.v
@@ -0,0 +1,11 @@
+data_caled_ram	data_caled_ram_inst (
+	.address_a ( address_a_sig ),
+	.address_b ( address_b_sig ),
+	.clock ( clock_sig ),
+	.data_a ( data_a_sig ),
+	.data_b ( data_b_sig ),
+	.wren_a ( wren_a_sig ),
+	.wren_b ( wren_b_sig ),
+	.q_a ( q_a_sig ),
+	.q_b ( q_b_sig )
+	);
diff --git a/FPGA_firmware/sensor_algo_qsys/div.bsf b/FPGA_firmware/sensor_algo_qsys/div.bsf
new file mode 100644
index 0000000..5125cda
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/div.bsf
@@ -0,0 +1,86 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 176 112)
+	(text "div" (rect 82 0 100 13)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 99 23 108)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "numer[39..0]" (rect 0 0 62 10)(font "Arial" (font_size 8)))
+		(text "numer[39..0]" (rect 20 19 72 28)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 16 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "denom[29..0]" (rect 0 0 64 10)(font "Arial" (font_size 8)))
+		(text "denom[29..0]" (rect 20 35 74 44)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 24 10)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 51 39 60)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 25 10)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 67 40 76)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72))
+	)
+	(port
+		(pt 176 24)
+		(output)
+		(text "quotient[39..0]" (rect 0 0 70 10)(font "Arial" (font_size 8)))
+		(text "quotient[39..0]" (rect 97 19 156 28)(font "Arial" (font_size 8)))
+		(line (pt 176 24)(pt 160 24)(line_width 3))
+	)
+	(port
+		(pt 176 40)
+		(output)
+		(text "remain[29..0]" (rect 0 0 64 10)(font "Arial" (font_size 8)))
+		(text "remain[29..0]" (rect 102 35 156 44)(font "Arial" (font_size 8)))
+		(line (pt 176 40)(pt 160 40)(line_width 3))
+	)
+	(drawing
+		(text "Numer is UNSIGNED" (rect 89 52 245 112)(font "Arial" ))
+		(text "Denom is UNSIGNED" (rect 87 68 242 144)(font "Arial" ))
+		(text "Pipeline length of 26" (rect 88 84 243 176)(font "Arial" ))
+		(line (pt 16 16)(pt 16 96))
+		(line (pt 16 16)(pt 160 16))
+		(line (pt 16 96)(pt 160 96))
+		(line (pt 160 16)(pt 160 96))
+		(line (pt 0 0)(pt 178 0))
+		(line (pt 178 0)(pt 178 114))
+		(line (pt 0 114)(pt 178 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/div.qip b/FPGA_firmware/sensor_algo_qsys/div.qip
new file mode 100644
index 0000000..4cb52ad
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/div.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_DIVIDE"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "div.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "div.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "div_inst.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/div.v b/FPGA_firmware/sensor_algo_qsys/div.v
new file mode 100644
index 0000000..5d50d2d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/div.v
@@ -0,0 +1,116 @@
+// megafunction wizard: %LPM_DIVIDE%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_DIVIDE 
+
+// ============================================================
+// File Name: div.v
+// Megafunction Name(s):
+// 			LPM_DIVIDE
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module div (
+	clken,
+	clock,
+	denom,
+	numer,
+	quotient,
+	remain);
+
+	input	  clken;
+	input	  clock;
+	input	[29:0]  denom;
+	input	[39:0]  numer;
+	output	[39:0]  quotient;
+	output	[29:0]  remain;
+
+	wire [39:0] sub_wire0;
+	wire [29:0] sub_wire1;
+	wire [39:0] quotient = sub_wire0[39:0];
+	wire [29:0] remain = sub_wire1[29:0];
+
+	lpm_divide	LPM_DIVIDE_component (
+				.clken (clken),
+				.clock (clock),
+				.denom (denom),
+				.numer (numer),
+				.quotient (sub_wire0),
+				.remain (sub_wire1),
+				.aclr (1'b0));
+	defparam
+		LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
+		LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_pipeline = 26,
+		LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
+		LPM_DIVIDE_component.lpm_widthd = 30,
+		LPM_DIVIDE_component.lpm_widthn = 40;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
+// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
+// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "26"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
+// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "30"
+// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "40"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: denom 0 0 30 0 INPUT NODEFVAL "denom[29..0]"
+// Retrieval info: USED_PORT: numer 0 0 40 0 INPUT NODEFVAL "numer[39..0]"
+// Retrieval info: USED_PORT: quotient 0 0 40 0 OUTPUT NODEFVAL "quotient[39..0]"
+// Retrieval info: USED_PORT: remain 0 0 30 0 OUTPUT NODEFVAL "remain[29..0]"
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @denom 0 0 30 0 denom 0 0 30 0
+// Retrieval info: CONNECT: @numer 0 0 40 0 numer 0 0 40 0
+// Retrieval info: CONNECT: quotient 0 0 40 0 @quotient 0 0 40 0
+// Retrieval info: CONNECT: remain 0 0 30 0 @remain 0 0 30 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE
+// Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_firmware/sensor_algo_qsys/div_inst.v b/FPGA_firmware/sensor_algo_qsys/div_inst.v
new file mode 100644
index 0000000..4a8f87b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/div_inst.v
@@ -0,0 +1,8 @@
+div	div_inst (
+	.clken ( clken_sig ),
+	.clock ( clock_sig ),
+	.denom ( denom_sig ),
+	.numer ( numer_sig ),
+	.quotient ( quotient_sig ),
+	.remain ( remain_sig )
+	);
diff --git a/FPGA_firmware/sensor_algo_qsys/frame_counter.v b/FPGA_firmware/sensor_algo_qsys/frame_counter.v
new file mode 100644
index 0000000..2df7a6d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/frame_counter.v
@@ -0,0 +1,36 @@
+//the frame counter
+//count the frame number by the sensor_interface status_out[0] rising edge
+
+
+
+module frame_counter(
+	
+	input wire clk_clk,
+	input wire rst_reset, //this reset should connect to sensor_interface int_rst
+	
+	input wire sig,
+	input wire [31:0] data_in, //for connect in qsys only
+	input wire data_in_endofpacket, // for connect in qsys only
+	
+	output reg [26:0] frame_Num
+);
+
+
+	reg sig_last;
+	
+	always @(posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			sig_last <= 1'b0;
+			frame_Num <= 27'b0;
+		end
+		else 
+		begin
+			sig_last <= sig;
+			if (~sig_last&&sig)
+				frame_Num <= frame_Num + 1'b1; 
+		end
+	end
+			
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/greybox_tmp/cbx_args.txt b/FPGA_firmware/sensor_algo_qsys/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..6fe92de
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/greybox_tmp/cbx_args.txt
@@ -0,0 +1,14 @@
+LPM_DREPRESENTATION=UNSIGNED
+LPM_HINT=LPM_REMAINDERPOSITIVE=TRUE
+LPM_NREPRESENTATION=UNSIGNED
+LPM_PIPELINE=26
+LPM_TYPE=LPM_DIVIDE
+LPM_WIDTHD=30
+LPM_WIDTHN=40
+DEVICE_FAMILY="MAX 10"
+clken
+clock
+denom
+numer
+quotient
+remain
diff --git a/FPGA_firmware/sensor_algo_qsys/greybox_tmp/greybox_tmp/mgd3n.v b/FPGA_firmware/sensor_algo_qsys/greybox_tmp/greybox_tmp/mgd3n.v
new file mode 100644
index 0000000..9a4965a
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/greybox_tmp/greybox_tmp/mgd3n.v
@@ -0,0 +1,67 @@
+//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_PIPELINE=26 LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=30 LPM_WIDTHN=40 clken clock denom numer quotient remain
+//VERSION_BEGIN 19.1 cbx_mgl 2019:09:22:09:26:20:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_util_mgl 2019:09:22:08:02:34:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = lpm_divide 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  mgd3n
+	( 
+	clken,
+	clock,
+	denom,
+	numer,
+	quotient,
+	remain) /* synthesis synthesis_clearbox=1 */;
+	input   clken;
+	input   clock;
+	input   [29:0]  denom;
+	input   [39:0]  numer;
+	output   [39:0]  quotient;
+	output   [29:0]  remain;
+
+	wire  [39:0]   wire_mgl_prim1_quotient;
+	wire  [29:0]   wire_mgl_prim1_remain;
+
+	lpm_divide   mgl_prim1
+	( 
+	.clken(clken),
+	.clock(clock),
+	.denom(denom),
+	.numer(numer),
+	.quotient(wire_mgl_prim1_quotient),
+	.remain(wire_mgl_prim1_remain));
+	defparam
+		mgl_prim1.lpm_drepresentation = "UNSIGNED",
+		mgl_prim1.lpm_nrepresentation = "UNSIGNED",
+		mgl_prim1.lpm_pipeline = 26,
+		mgl_prim1.lpm_type = "LPM_DIVIDE",
+		mgl_prim1.lpm_widthd = 30,
+		mgl_prim1.lpm_widthn = 40,
+		mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
+	assign
+		quotient = wire_mgl_prim1_quotient,
+		remain = wire_mgl_prim1_remain;
+endmodule //mgd3n
+//VALID FILE
diff --git a/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.pof b/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.pof
new file mode 100644
index 0000000000000000000000000000000000000000..c8aa4abc5f3b03e6844022e7b13d94446fbdcbbf
GIT binary patch
literal 1450250
zcmeFa3%n&)UFW;@&LNzHhMb0=;bCU&=A?5HGogbafESZWC&)wEgvY2CQ3L5HXbTL&
zg{v4Up~c7rZcKAgX*3xL=;(+V6&0@%qt_v$C?YEHsxuejW9~Q~nShVXpv>>L*7{fd
zt9I4i`*fcq4gCJes`Y=Z|628}+WWj#*S_+KuM8nf!h_TC0FKXj^^0Els#kwUyz-SV
z{q}2ceEGM$@<reN?bp0Ae$6$n{EnBt{AKZir<{Mm`TOGjSHJYo!FbV=_QicqdHfTe
z@c1X}yWlDDdC!W^e(9^OiBCKD(pMojOvA%a@`8N_p1AMwOTY5MCtvuq=Y^BPDe(QP
zm%ZwxuR3(i!SIN%0h1E(AJ=m3-=7<Hhh6cD=uGmn@P2l=baGC6_cIPHAF?3h!T+!z
zsE`PVfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y
z2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0P
zh=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)fCz|y2#A0Ph=2%)
zfCz|y2#A0Ph`>%0xbm}4|LlR!KJ$*tKD+-hfBV?43p-tZg?fKga{k-bK%ifZ_6fAV
zMf)#k--5=Rm!r{liEIA={RrA=XzxP%0NUATe}MJ_Xn$PnA47i<8gm|u_PEk>>{p>Z
z1nqx8yX1Kv4`lEdw5!p+4Xq=gmCv>+w2h69`T1s?-aDaP=ZBDdr=#P4kke1^XJvnH
z=zU<G9-d#S?m}NxRp8aA(0Ez!f3;DCXT$MqxUy`d6zFRqtRrK6-6Csr!H;879{X5}
zpkMzPXN2HGIj{@0c5xM6s<ak*Yyh&7Y-FLnUNzz3W!FUVNEb;e$5>6Kx_BDNLzaG|
zN+Vg{MK-2b2V5_FVICB&d@lZjJQqj&AHp|&V~Maspjdm~2<6n|VR|F*_D5KZBQe6n
z-010=Vi{laHR&R`$d%JDSwrOccD?=jp7)%zz6pn?1J{@2IgEtK!{#Fh)42=h{lXWf
zL1jqkN`yH{I#GDu_jlR9fsQeBXQKW2pJ#Wty(=Mn@Pj47j=?+bK)e0+K=SSDhXJ}v
z<P6-2ANyDuX^}j#J6o>Es!5Rlf`WqUgYVa$b7lIEl^*gv6NV{vR?o>a9#%J3%_7!c
z@9qshGM{?Djh{>W$B!2tu2wHUC0;=%WFH!qb|qfB6uM6PnGi}iJ9A`j2xnXu!q<Hr
za{_$djQ`l-_{|j}*It_<`M^jKIxcQQ=6)Jxdr%0Ez6G#ekk*07)9@d=r{P{Z9jEfh
zN9G%fuMW7-;h2>3&TC6Td)`5sC*^kDhqFO5oRp5YV-0Q*41@`4vpiZiG%2?+lOFa-
z5IJo^PF`jqymLR=JL}?|1-L?(;h2<D-AgQ`?A{#${%1S&?&K+l-E?sb+QYE&hozSb
zgRW+{=oukgbWs_CZW2NrCfC(9lyF`6kvfOC&bqFzgZJ(9yy;mXTouBPAfJh0f@4y?
z;wxx6nNIQIhmH2c+npZ{y0e^(^*#RaX8HaRxBy3w*52jy$EQj2{pS79_p)Zsm(3^L
z9>OJ;42C`uLhlY}&ka*;e%U+SFrNEf)H)wuJWV#Jl&?~FxBIo?CqKx>^;xK2cxkY3
z@v>v&^cR8bk5CIPlGG}MpZ@6-$p<=bx(N*<G4)w(hyl7GbUv{P;R7E?uZQF-hc?2b
zx%rxPw9$9H>-y{QKkus3E3WTdj9vFyjD`Ek5Z?RVoScrF<_&K^!-xs^wIK%RhR`{_
zzO(j+@T<RC2Hw~e5H!L}VDS6DAMM5)IosZ<j7pL3r@KT>zN$Gh4xu}b4Dr$se(9Im
zac^hj?KtB9aB{G(qr9FB966NU7n#2X5HGa%RraaKcYk;4@_}Ca$~(o?s+$-C`73i8
zw&#07_|ET4QI2UPoP1sLUe559uVCyIIO6{h!^=xWu8)CBv(UTu#$e&%Wyi=94u|kv
z-$gCBNK$caI%nYGOuvwaEIATRPggUXe<r-&@D1V87t#MB9PvNa_e~|6>to>Rt1r6@
z|05DkuY-jzqZ4jO6UigtDUqwMrrNGN7v_*6ba0v?=0;D?g>?w8e|<`Dk;|$OesE6+
zKm5bYflMyNe~?RY#Qz~Y^r1PBqlnCAXoy670r^OHS9yD8fbLI*@ZbmcMx1iWWP<<s
z^#(VA2}YbkcZvMW{t$lQ7gEq7h@E2DpDVrnu=OPXK{0#P9z!;M;&<C|ft(``9jVr`
zISn<xekIA>Mm7eHlddoFTEx~@CACdjx4QIC_-5Nm3;{RIu+%*_zBY8mBHZ2u?R05W
z?2Wy=XM1yFcegIaPTl!bDYyEzTiY>pt0s+{ab`}^cSOz(8*3p{jUzT%RuIfmn^OAx
zV^6oXt*y#A&Dd<#xf?phj&t>KonfmOc2lL?ITThQW~IG`fgE4_PZn2yJOp0-s?pKu
zePJ!%ub?0C|2ht#Ml-n*w?~zX8iAO!Jc6&mbnirrEs+$iaP;?U^SX~Ij9)w?vHNaM
zHtXEw+F8djQcDLaNo-uGlbMeJ<NW(VOfkHEi(GEXK;ORZt5iGY*S+1ZRT`3yNsW2t
zrglj8>&H?|hvOx%;C@Y<kGH<Y=lgXLXE9oxz#@+6`+?O<DRYDXIkueh8*g;EmD8!(
zTQ}77j$Xc9Ozy~pMs|m)(Wy*rY#Qf6%@?uO*L(|$1$EYx##T)trmg*&@|U=FP5ztA
zJm~UfY%W~RC)IV|`eIG%y)TZFe8RS%rcRZ{()^Vt^4MP!efj5vl86(E{2zx<2cxuR
z$_>ej0A+%<k$#1i%*YdpNlk}}SD{8-D3l&bo)9Y}srhq2gbIa%ug#dVtO<6s0QAZ#
z)-cf6HG+zB-w(tvwfN<AxIF2VjjNN%L-YMWaYfR+1w*r4VcLd6FqBXlsd>Nt#JRL<
zv>R~3H-sCYW@`9-<L=!Xn1w%X-~#U16XP^SWI}KOt8h8$V|f+McUsr$7@ekB<IEeo
zao^$WP@8qvBX~ucVdML;^xYhbL@amDG@x{zlPj(cqiB`pbZf#uRKuD!u%>i#MUMT^
zIGx@?EpRoLU(WyYnlLBU#B;&o!y4z@z=ANe#{cU9r-GTWEXv02>hd-GA8yZUiqjh~
zu&n7YDz0(PW=#lUEEnIb>5u-Hb-0qa2ggV&jli*ee?=G)(-CWeR9SD1SZfi0hon<Y
zr_dBF@zJrVZW+hibR)-R6csEx3l@~uRBXQ{ECv79=~%*fT&bPL#uBmaa#MhqQqBi;
zoA;r{9jQ4<la~dRaf}vs=J=FX!&B2OIUWM-*Qxm`x4m`V_xb5*ZmnZFJ#zY2KYmO@
zzu*SF_nh%l{=&K6$l%!TIdb~Y&yI6cq$QyHtz~hn8t=D79FMi`=i|6VoW8K$-;Vw2
z>V8|D-J<*LBl!=?s~7tM$o#~C@skv<c{buT&t#Ej0k6s3KhcbgS*zHk1C;@3en20H
z6<6g#vHYOj?n6Yd{0NO0<YRxGx>-7Q4;#<_)~=&i5q*V*ANQ$xsml7?Zy8d!vZNR`
z>Z;DazCdoIpL<l<p+zbk;kHr8rP+yn!C2FWpOvgx_MQ00Q@=Wde=7S*S6^+pOsfz0
zyv!uK|IIdkeO{j7eS1=eZXT~sw!@-(Z<tH*)**cBJt6!!x6MYh3T+kH+|I8kCnFW<
z@4vrZ*XHIo)BLO4^eY9IJN7GvDi5z?TgLq^80Y6|Sbd*rI@2mMM*8Ud(EkJ+$ApZt
z;GCoBrLTInH&YB_njGj!tS{zRSNXt-WBiaYeWjPxD)U*6yDlShlHuQ_znLK+jwI0?
zOHI2+EVp8?D|N8>=^xX(W9F=MPhl*!>bFv7m1`Kh&v3qlVad$-JXWnbsHJ$}^>DxD
z!R%6Rg**&@<@NZR(9@x$Ir{bB<hNfD4QdwDwbJy}+1ngbtZK}pn0Zy#oh)vGvN#=)
zhk2>zU72S!6mUMS-*RI1*SYJ>WhccTE@Ja-r`=RG$ognXc+-nRc#UnkZM;Qk)4GwW
zYi`T(OS)=c<lJl3pW8tG1LPvNuf4EL9&HhoDJ%9kH~ihUk+D-{ip8jR!~z}XQlnm)
zF_2I>pTCZ9*Df@#`sB^|FQaY%xxRpZQ(RR>--;cVdX-`>pXq+d73_$%P<rEINv=w7
z_3Zv0TDOfUL)tk}+s0e0*Pr{NA$;U(drq2F&sX)<+1ywq&+^$P-SSJ{jE6lG$FS9<
zS9|q=$h5J35Pd^_xTDWot{-{scn(>&;^wQ&Yd-7EU-~Am=ihPD&ksFv0_)3U$yf9-
zb{6iB_5McRo^tLqgqy!|dt;Vo`}1Cuy=tDXQN~2?8`BrmUupbU-C;jjKJM3tV_k1=
zU6qgaVm`F0K2|Rd6<9W3iO-FNKl!X5s=cCbu677ydHZw9_<?v^xvZ~hJu7M3&0neL
zu_l#sSUP+lFD@A5V!!#n4&+tYN7kze=C2lI4y><}zAWyOU2gRLW6<x%@jvmA5WcAV
zYxKn{wez!narQ9xGPW8UyR7!I__5X<8#m^kUk5q<?U#+^kNB$*e{#>yk=)Igk@%vL
z+lj?qa^LQSJLYzBIdB{K<oxO{;-H>XJ)7o`ub;L`j*YQg>*@D8?d?dk<Q1-Elgly4
z@7VMeiKdL$#eMD*Lb&Xez1+&#)GNO(=-&1^hoyWfMN-_4hrct1G1e^kz8mr}H#JLi
zc7!j&X6p!j#o^=T3qFoK=1{B;E}kR9#~8vdK4v&XFIgw4P_HUFJK9OuyI7UIEmOuU
zm$9PL=X1?phPQc*qbOF(dW*x3-bdSF=#%b!&;whM$i5#hG4E#{TVG;vSl^Gs{^)HX
z{PK^NK!v&3Od7lR8k-3vx5;<o(s<Z0DLI$<wArZ7*>J_uQrz44wP+P;cxtZq$ME~L
zSY3+r3NHR&j$fu;1%r<LaO|I~ZG;*AS`ZPNhESb^hXPDu;DZ7ta9ldUpI0~VD^>0(
zpP)gKW3o|)$)u(;uA|T?VeJ;g;J_0c;FzpevBo6Vg%COKT9{sy))ppvV4%ga3<Q&K
zy)XEgVpNzbHQ1(?Q0_|H`<R!+dJB4+y4mPs-?lNOkIts<?6<u#gqL!?6`Dx}rQaB<
zFpsq`qBG7|Bg}&lOG`2MXj39|`q;At_91XxPyJ1p$%e0jY7J_V3dg1~r!<Z+f6|@b
zZ1&bFr<)Ja5ZMq*jSkaGZ#MfPr|${jW&aLF1z%-evx|>@#ydjWjfur>a*7?{NDVf7
zO60-p($g2In;*ZX#@hawKVvaQsa#7oaswNs=#}-wmuwfe{8)Su`5oQc$YDGQd&YA7
z`FDhH;LA&Buq*i$f^3wEzP`A;ekj>xOtfIhPwOapK%Z>pSR87k-O5Mzhw$`UVaMjr
zHEqze+2Q<~$0|GcE<%~|Q1O7bn~nYJ)p|Uft?rSto5aH#m=O|raFJxw2id<q+lWcS
z8(3F9dQ%90_=oUKu%>BUf=w12sV1K)hljdVFkwd+>5o?@RfTsxg(~6=a1v^U`464e
zCy^=!rBlnlbjF)+oTSr?bZ}(Nq7=*<*-!9ak~DAFQ#aRj?Ya2c{~vO2>9GoH)3tOi
zRaIY~YfSO>jM-zw(UXmE=^iR!<Ek*_a_T(uWc^C4AmU$M)it8{r(Jkf*7F}8!l$3Y
z>|FPzD=wOR?BLN)9=hkwe}-?@O$Tl}<%4@~{^aX!d*(myz3cANZaVa->ppn)(SJO2
z(}8O*y7!vzeaGu=`<@T(z3U$j9=YP$i|^We@Xd#g{Q5I5y7x18A31RGMR)GK?C8NG
zzj5H=yFPR9$f1jGyYuXm?z;QPi>|on&TBV+<#lJ?bLZaKy$6q6b>Ox;U%&SQht9n1
znNOPBwR!XvnETqZf92q5HyyZS_nmuheg)>fcJIA+pLXPmCnba*{W!k%Tob|(tSzm4
z;h|7pm@^hUp0RCBuJ`Bvy0uSq?M<iR*-vxdr|t}keC|70%V=)1X0&k&`c-mz!~f#V
zJ%=;N_4s9*=XqQca;|O67ne=8jasf0xyAI5C+FPGy8N&cU5`7vz@N3hB@dL%`*D_C
zlU444ks8&&q@&kuq(-O2Dmi|D<@4*M={|n^dfGSkm%Tbw&z>_^SxdyIRr2PF4>)$J
zjxW7R%~f)I&0(F4PsjHujZ}^16hGIHZa(YX(7}2xKBx}VY4R4unxvjGHirK6{T}+U
zoL;G8FuCXHvZpN>7?;FT*w$$MDq~y@zjsdJ#>e97`@MTro!`TIiQZVQ-*_%^s^L8D
zG1(dEt+6RO=5G>;vT9y`+yi5i+n>J1&0RbFL{lRc)ZC-@(c<z?(km7J#DYt`@P6cZ
zBw0|vQWo~dJHB81c<c4X$A10gHuvGgE0*PPp0NwnTSKSRqF5(!#Mth5``Y2l4f%Y0
z=XA3C-P5*H&!3;y7uE22Ugwy;y{OJk$A;z}@~uAa>lXaGqiyYXSUBbJt+89WU#o9-
zv$N%MyuK`VD1K}{vi!-99NX9vchoYL{grPwzdt_PWckg1KO9@`<r-F5hvoHi`}Xn~
zhckQ~)BFAK$n3RTTBcjSXk0f&maqMzu5aGz*B$yg)z6u)GVbwXy*@tT_#@kyXZ74~
z`j+vPaSzFTE32<_@j6&%sMe5gaiunTJY(A`)X4GC_HUNDp(WPNtzpSTI~cxi*Svqh
zJ$c{UulMcwtOox6T?6;wy#8&gtt@A8eSVEzXNI@Eo=11%{d~(=)Ni*Y^M}UxIr{Ns
zwjbN-Wcf$WYwdZ>)-v=p%4ggBmd{vU_xWD8vF0<|`tADr<2b(W>)Vz?|5%JUi{+7*
zkH@(ur<MLZtJ*_({4=Zl%;@8$vmchfJ4ipr+IZ|OszM#m(t4+pvbX3`<nR|O*wYjz
zRlwh=!xWCmWV!)^`=0XWHlf>?&=G-=f8C#S_B_FXztLk86!$y@6iN;h!k(uZ1FC>&
zFob)a5aTp?-n6dp>Q7_PbREWeS{E$Dv$TB8XFcQ8&9**|%g1H$ey+F2_3wKwW1erD
z%e_V06I*w`XBAt&#ri(pBbLJ$#cbc_Jx_<uw|Gi)2VdXkbZfM=ZK#d&eP8d_uzRxg
zzv#PdP8)0W^S+|_c`cv4?YnF1b@Q#}P~3c0&+LBBIK}+g;-05B{b1JTk6hP~um;8Y
zY;}(|kM%y^e7?81`S4+YcZ6{3w|1*`E#uZ7%NizDZ>aY<rn9%)v27y0z8{DEqx(a6
z(pk9%-(Lm=d!Fiz%WxCrI(+w{Omo*9x3lM|JCog?rPO}B36_0Uy-47mrw`&DNaOjg
zSaA%qxT;Bw10}6>osZw)k|SCkP?d8)at?4*jfMc<Pa``BPL1)r$|>}mjV(?5H|sUb
z%H9W<&S;Xn=ZWho!aYyB=l-UT`M9UaNvx95?0LeTFRTGl_B^fUzvpa($sRcKo+hr3
zOMyLU_ex#IQIuWW^Ym9olfJh1u1}wq_B?IoJx>?id+>X2I`DJNo+s{Uy6Mn8?Vcy>
zX?n-&ey-W`#63+nAG)d8^K{RhXU{r&o}PKhq}lUy^mS+6bl~FM&7P;551q+9P0gOC
zqX$ppo~CBc6ZTuBRpP)sM3>CW8tS`u&QQi;UvsT`X}pKn#^Sy7VsgE&8-G^Kb{4z6
ziHDc7)XP04YhS-8ZM(}@mQSWTEz9QI>G|+A2i%_itVMN~t!XGe<nwdvG&?_^*ZrLL
zi{6|VxxV_D_sg93$0YX~RPGfy?YD+bY3MD-`Jx}wF?^ut{nJ^NKTyJ4{6gCis~tPu
zY%rN|yG^VgNIi!4?6%6>q7Z6Xk?~vktgNN7Xnp;`vF}*H?$>YE*beUJw2@&g4!b+v
zWi>rNuXl<RW4IO>--+hA4~?Gp#d+7L$L=+s;293D&1YwQEYH{P=gcsaKA$sR`FK5V
zc%)V6&!3<3WYMOt8tnm4BEA70m^Od++za5os*vBj7xcn|=CXUSHwd=^_mKQ%^Id2!
z{yAm(`+8vE^S4JYsjyp8rZ;HRB-aP;9St8xU}S;Yy!6{zKsA)T6zI^Pr9N`I<6oDw
zkyBk-gbCG3S=&g8E9N4v>Zjh97pFhhu+4os7Z1M94YKva<4+8)zvmV)T@*Y1Ga<{p
z>Gzwf)*53w=3k|*XVK4J6zk_MvhQ1toSFL_s-Ir8hDEXC;m5i=#c6Df_dUP<%)k79
z^*yak)~%dT)KwVX*PPl_&1+)}$NcjZmV35;eq{N__sQ4yq1F2Jd3`8%72i&>TV=k*
zIb`{}?_8YIMpwCC+w2EkGuGB`=lc0vuiIH!P1;%K9+B(bZt+!n&(w75eT^ZXkFTN+
zoyRKUm@_oiGw8>C%;p&KS!}2u&L`*DZ(IHY&BfMny#4UG9&gn}<H_;E|KFkvUehtY
zeSiP@FRFWg#*C}=_to6~{Jox^J@iBG;=E+$xp~`ITij}x-CwuG`~Fq!q4Ay(<Fvic
z+kU*y>Ce9?*3b2}uTOurx##Iooo8Q@kL7w+)Xlb@b*MAn`{?&#^~|@-wmj?m`R4a5
zcERaw>SlAi=^V>kFIL~@_%TCqKR)Z+a}(b{-SVlE%OW<+*^c=0vT=Uh=JRV9@~x%k
zPW|8C<zu<_v<h{o*6YAMO=vMxA%<rlk>7Nq#dSE)_#7v+yys~PG5&rOEjiX>4TCN3
zc{(Gk!9Zo;!7mBXDtwwT8+om9stVOBta}Yl`&iqx9>cRS@8!X+9r^z6_&YqFW`g9k
zwagj$4R6!gQ_Rj*Yxm>JY#Wa$F}1BH-$%6lc;@DLxu@y-o=uxM6w9;wA?LOJF*}d8
zy36xz9^U8vUZ>t)KYf<ZpQF~(bDkdl15lG#tlu+8pZQbrHtqg++J22(tF3=MJuB&3
ze$VDv)Z5R4i*k-7X4i3O>{@trGp#Xc&yRbaT2}U+(8hDc`^vU!ZtF6ev!0RmJiQ_P
z{g!c_1RK|A`L?bh+sB6DDAU|0LvcUeu06->3hzs}>9a<EX2(5GVfIcKe1=@Ev6gyU
zcb<#Saq7=ME%}qw2fWptbGXgn9GowYr$sv+e(e6Re{Gf@n3U(sc{zixs|WM%jI$fK
z0E}jhR=DR0Yi;)yRWKt{Pe%(i50G@m>v&h>+h|Qssy3~tLZ-QkDUn7+$2#67(*SO4
zqHs_uMK6O`Hf-)`s^BPc@xL=I%>C7dd!7cQJdepDRe6q6^PH#9-SdR^{<MC~KiQK8
z@i|UhPMucPj7xP7-E&uZjuZDh-TDaZ$w|*~`Wx(dx_I(2?s-bjaXN%OPw!8Ap7L{?
z&cmLk|DN_d<>xq^k3CQCFMFQ&9H+-)&(k~7o~KRhX}agm^RegYXnM}mUhHYQ?U@&2
z&(qQLoTsyo9>Q~+xaa9+Jm={{uityu-{3h;h;QDE=RAGr+P?zuBL{x1?0GtHtx;gl
zJwzv(%s&^YUE$}{dSl+Z)2=?>RITkbBzL55cY^n$;ond0k7@JkpL=s|{;~UNzIb01
z?$y0N*=25Azz1&aEyK*Xo%@l4FrX2yH_k5*WncR2y02~ieVx6IjmeXH92mD4)Cw($
zjT^Jg@9!JxZ2XF7<GpTU`n}bNE`WQaqRsJ;IvsI{McG$+vtic7m2#XvxtpLR4fM7S
zhHU*#kFAgUasK}I8QbE)Npw0@Z?nGH>?f^VK}|M$FR>Ui^rmxMPa<var{e-Tdt%=}
z`&>(jP#7PIF=saqMGC9h>{t|zg>Gi?c6m0=aEBr7<mYQk##yp$R%UMZG3T>*#681;
z?9q}~PlLJr>qUPoe#Uu@>?!_w!Ho2I;k@`q0hRY*OdY)g`mD9<!mXLZLeUi0Tds4Z
zH5EHX9~jU#(r4HGRQmRJAnaWgjTq9e0;uwP+lqZen^MVAO-$>aH`22pK8aaPV~YyC
zPAbm{Ij*E-q~7~u4cBG~V@xBl(YVZXowkzF`Wubc2=~N|#?ta)lR>3Q7V?sUo|3wl
z_B?(1Uu0K0)=uxMRdJ-==Aw@$7OBijHSe1D*!lB3>NcEsF=l+*P*;nsna0pGpRp+^
z<}POLET^zZ_pwW?eR9cxYxf-msY|u@0`A>O(uoz{SZ7EpONda64Slqi$Rv&=_&Osg
z$-PRRE!5ZPk0Ym{JU?b$C$~RY`7@K-Ytcnh)>6&aZ$0r?me&qnrlEXSj73><M1tLR
zmWU_bXF-gT%|6&18#w;z%sH)8m3`c&lccgqV{!OyV5-W;qrI8HX}Q*0p4rx$A7dLa
z-EypN5{hCcVg7!eos0L|82ZZB^yq(=Vq>hP^>%&C9`DKW_a8kT&ykr+fL=MXQT@6b
z=SXgJ2}7#It!GZZzPC*$57RjY64P<DL+p)RZB&!R{SI&acw-);5|@m_8mmPqetciw
z8W`wv2EwDRv3t+gvwO9lYxnh7@%6NStbX5EyyvfImur`FXPcj{K{>u_-Yw~C#crr)
zwm}zgYK|9f-k<bE{Dxys^gj}$;%(9H{xP1zaE&yq^5>X5%MaD^ls3cPE3tJCYW?^z
ztgTZQ<NGBop8U(-SIP2W|HB6Ld%wQIxJrdx;t+d3&QiV4YIvXJ4fXxJzCAR?e13hV
zM+<JFx3Qk7`EnWVA^9&487divoFl%W+#%n{@MCrlG4<y+6z63A{`ZqdZ){utf7A03
z`or>i$a!A+>+9JSM?@YLNN<c~R;KuKwOsGByhVLPaNmLi#@QZ)=7sackyC)*zXwLz
zeVJb;IsVAY`gyeDyt8umLi2s>eA>Kcpw?Ux&uvI-%@M(|oc_3ep0`ntrMyIEjOk5^
zt*3DmWh4BjXPM7&DwA=a&fNDv74x|^)<j=XH=*wA6k|@bgl>LCH}fNvGS@8Y>Bt!8
ziD+ABwAmt>32hUv(?{F;sPp*?kQh^!4oSuNH!jR+dgK@i<L*5)mh;cSkz>o0EWiAF
zkyiCmtMUzl`KvOY^;}4!bL<Sw)&#Zc**?bfWOJ=ULZ%$=g|#CZdy4hh%J!@nJU`=E
zevcZ>ZqGd>$6`m+i)DD~%G#p+9@fW9@2;PFa{lXIG6sLe^|4V<gLd-KHr?X%%?dNt
z+(O%j7SX&!7#zb!osH*(#_LWqeHIep9h-hgOviFKBR$9Izy3isV^u-H??~}`j%l@3
zBNv}thZ_r@T^Fkt;Vz4a?Lj*!gsWne9FvI8t~&*Lp7@7s%$cqk@-}8Mte=ACI9-4}
zPx~h8IG6k!Cvd0{Uq1tXgI~v{skdR0I;3;ORMYB_Xt<X*&sYy>uho@l86ol)qw8sp
z)?Z(Zv!8C18$QC%dBLl)`C(#ImRau7y$HQJr}!g!--<i=IA&7fyap8e=9%{jr#74G
zdJtN<hdO;sdxu_e5MlZ&)T*FXG52XM*w!ciq{PuDVL!`i#TeJmp7#gk0yM6Ld8nUy
zTN`_hWzTy9Yv5}j^6TIvob*-bBGw-94{am#d`NwM{#0_7^}tPr75Zj95&ER~(Fd*#
zIrJsDAnO%#=;JzkW1RVUJ+`jqd?Ioq!em!oyWBVQdwe!YWKHyBYEsb`iywLt*hy%!
z&9cedWE)4bV~(fS6X)l8DTpU_<Oeg-COha9u;to5@TD}sI{j^idgLKXg)ugN@_3s%
zS~bhL)Klx*WLzYzjd^B6kHt>x{Q7o>7k;rNqUXJk?w6RHe9lu|Tegu<)-q!N5}nOC
z=!Y*gbjjv<n+$Q~oE*yrNo$}&Ki(I5Hup6B?T0PS97=Qz>g-koB8bmm@Rb>Hv<4M=
zz42l!j6SZ9eGJpoH!H!Or+B#e>^fv*;hg@QV88f`SzZa>@u+2sJ@+*I@UOtd&#r6y
z9PewCy+z!6G(jlx!1t3g>U2M61D|boY4Rc~m#R*xs6wV?U@;<w%`n9zhP4>l&#v2-
z;vq&%lQu+cq?PVD9MWq9KJICH+Mnh$96O6_yiUo_W13=b(v8_WeNe=Qm^OQ!xDl0-
zKD(~MQZO^tnm@Y^7q|WFx{Wl~%iqIn?s>v%3TK@5G?mY;<DRF^XV>Ag?b^?-v*$du
zpIyh#wrfATj(eVd?tA=a*KyBN`s}*2=V@<#&XfP_I()XB|Li(G=c)bdx{K0tp14Qo
zdH<4op5CAKJf+o#h>ndCN7`(}-_PGFdFUERSFKoHr_0;ayEfPRB|lS!c4EmFEpnpt
z+?(^VlNYUK*^+(SSa_eW&0El7=qs2V;rQ6`bPdMXhGYU~EY0Gyy~JWz&-Z}x5;RxI
z$Q{>H;>khV&M{}SUvtdPJ-NQCvpcUF?^spG8Zc}PaUe#Qt!XSiGOTfv9VM1VeMn+)
zlG~6(II$LXnHvmS8-0DT^D_T>dOp@aek1Kg<Dv~1=q<Kre190uzp`=tnD<*v`n(_J
zphV~8*giKOcd2+6PZD#t_-JeLS$(c}rugrM@YV0NoM;Mqoco}};<bJtsWM;5sm=C%
ziFwyTcJpiRz6OWtS#f;tH7Ca0IQjGSx*r(5(b38APXBMh<Is9LLsl?iFK1PIUm4fW
z@0DxJp}fA&Y&$Qr$%?w!PzNOrdb>`$CS9+$$oW9}cegRSOE-SMGObCXF)vjtKHpQf
zd&B&2C5ffC&TQ-HH%`=-Nkqb|BvJPqXq#|7(G1s*<-3%gdfQt=c<AWgMeMwLgVNm5
zIi2oQm*7-O==WjLCY4xoI<$)~F`?dHo5c}oq$vQ8XBL}`tdv^O*W5&??&Z<+Ic@mV
zuMXkY?r!bXwYYlf!pwSMbbI$9OY!{gYl&$BvU}RWW0`B;ii6y(Wg{Y$bf7XM7!>FI
z^}K7;Qw`rMZT?zOnHO7kM`!Ft7c(`FP3-!ALa~%iA3N4+h9Beg)kZhxl$Pqp59#z7
z52zi99c!Vnja1fo4SsJqCj1&RFLB<LJY)Wm^u~Rx<C+3Jh4t7dF&%gA(68rhuXkr8
z$EW{U*SEUWuiLk+(vZLJGrQl1;}l=dbYF7F=i{a?&->E_&utmLU#<4C-sbN2W8?aH
zw9N-~Wr-zotRE}X&u5<bs2{tW`rku%<I9hI{LZW+9?t@Hc<kzHdGViwaPOzLJN;Pw
zG5>b!-(UGFtapN6SA)@a-0s%Y4oh18D!6G0_<Nm+Y0-TfT3Ikm@m~@A4bNm2FlCnJ
zN0DeA|0S2dsm@ZHf?v}&YNJ){G^WMiepiRTE1EP~Y!~6a#$#BPI(3X-1aj9Cqs#sc
z9245;lb2deJ^fleA8UTsuyHtj?|{Em;!zLC$joreOsdR_r;y0NhPI!}PfMJvUs@uZ
zEdLi%3`b0WBPYd#_%BUZyqG#q2pfWrub@pD(|xenwxH97nvP|{D%mWHvyEhyw0se8
zEa&~(e~7$vZgp7#?JT^H7E2rm5BZoj=4b4Il(=wmGI-QKbW&#PxPXZ={s2=>E8@p$
zG6l)QNakgPL|#lvjXUL*<eP5bLg4~Jcrl?xTsqz<ynwib_>+27v<ep#C2^m$6UG$d
zVTM?W9>z5JvbqVej5<viHgLb>2}6zhB~P;-%iw*KCd4#J!!j^EWeew*H9Idj(|Ox@
zVcC>)B%`OKXJ;XrmXu<Jk!8^rBaf*@Il|1ZB?iE#k+NhguyGk9IPS;ypP1*ba))Dk
zUdD(Vn)A+Qm$G9zrU)55{I`<L!=ikIYvz>8M=kQuaB>_99mXrPBIVM-f)<Oj+%33A
z%+tm&VYBQ8ye)&{^Swf?ia4-g!YMmSJ7Jh)4~{LT*!bc(Z|h!vjAR~0<@aQiCL3#$
z{7S;&SOcxbe?0P)m10~jZg6;0n_{mD`6Nb&Rq0;AG4ZMLqPX1rI)fHrkWKy%7Wtsj
z52>5U%7pviMBzHcKqit+X^2(uSNJc#Cs+A(lqXEFbZ#-7b2{&c{M^zx^FDbu{$}5t
zH^LCdGA0KO%ts!D$4DhDD=A5fS;Yd2G+N@5o$j?%v1IX@!af$GiMIDpT|%6i%Sh5p
z12X3G_fX>lACpE)=T*GTgv}BV_{<AJcucC>OlU=pv5&_%ZYPEf%{}C6=i>R_gFR>C
z5_=)Dt!J1zo0sSf=*#S0`l#vaQ1>>>j>KYF-w7sz=YPuU=KZZFw(6+H95zZ!$9yo|
zdKX%%atzxti6x=m`*9ZYKI(Dz^WTAe690ep*KfRPdeVjOdG^LFlehg=cuT$h;i|g2
ze*5~Pr-vW@;WIX_eCXuVt(WZDH>obWa_{8PC;f+8X5pIfmf0<9FL}n=1=VHWH@)!I
z%g?~rH-;asFFbkc5tr5PJLS<Q9e%=xH#V-Ue=AO3f)DJfuD){5<k8b-?fURDs_@X+
zEhoR^ch+XrWk2+m$+=rL?}ckyyKlK5oMrRcx~ja)z%@U0FO2ju=ljgGyx=D_Qz8$L
z=A9$I!=!Jx;jYr#851fVN*QG5=N+NkBu4sc9w;##n}Sn(Lj>8dd8-nBIJUthS&!(d
zFxxkMc2#ptbz1Y|*50#@U5TgPzW$tga`KB$z3TA32ZfU+@7XwGa(leJ3hQr<*!yzj
z+V1H|Z`!rCUaeoZ`<9cZ@0{-2AD&lV7p^*E7WUm<VVz&OHC^8qo;H2l;XP|-tY3Nf
z_Ge5^n!NFx{a5|w>DPsme(=rM9&=UPn0)2>o5Q}1YWH=!r(4rqw+5Tn)^*#XLwNQt
zgkbARYhQSX3!~c$?nJGftYNjR4=W2fzLodm{VH+6Z2ef@UNAI;7UeIBEv`#WSCqZN
zi!*)nSm!&|ah!YE*rE8452ZS_`Z;}@`OAgR%DC)jm*?$lMqIJns(CAxyARXe`H$np
z+vkyt=d2!y3sNm+{esjKS~YK3o%=pch8w@Qlk?cQThH1<y7&2<zTd~FQ(`){eK8w9
z?N}Q12Uf`VnwLJXYxsPh{rTS-!cSek^en5T89SVC)hEXb@^9_ilYK5dI^9(Bv7ea}
zJ#9)X&2;vZSQ>RN(HlK|QOr{NIke4ZJzO1$9jj}!F|s@LMcwGQ)s7p^Sv78X)(=-}
zy^HetvA*3_$yz^7d&mcOk{F9py4EDScYjAWy4Y%dN<&&(XLt<blM<pnCb0ypr)j$N
z^qE9cT;KQ6?)%_cO>EJ~HZ}G}#`G+|ulRV+-I&eqwBX^tDT-)T3u@Tn0TR(XQ=h}Q
ziLcks;lHOav06UIkBydy-t=klnO)4((Kj@newz#GpfGN=hZ1bO)u(NG&ga+5r~EZ_
z%gz4bV}$z|Xx$n)*Yn7p_BfQ^Mza>3V^RJ-m*-VpBd&pCw@TnarMGSkN;ISNelC9w
z{jp59XRj<`-Ybvwknz{Qo__ncZ$5|f$Kv3*QLoVaJqNQR9Aj&>-q*2YpGTd|gx5Qo
zQF_)gALBlsDU6*%1rpOS|65J!mTP|YtY^Y{W5QUUskif5CXe;wIp2+FF*#p(ed@|#
ztMt(?06P9nTqFJU#3s_-KRf~RTfVpJGR9(deQ8@BQ;ZGDjf$;#U&-LTN}<hrfi*dv
zJ;nN%EdOs0vx9Lv-+jr&XQw^t@2GM;R-ZO=BNZpMX6I_oBiHkhtg{YfhBh=l1<N6#
zxBON7R*&QQ;<@(Ei@6bv<A>(s>zr{Ddyio5P`>50J-PnTovl5rjn#_7=^d}nF%FjC
zW9D0>_slH6Uu$g5mcOj`<E^%>ze>-R{P>4h!+cFW{DXK(Oh+8tVtvhlu(`T@8NaXV
zZLTlFbuZ>kH@$a{>i%By>m8~SQN`z2(IKD3e9t_8&*SrpeiTprf343M(rt}gQ$+LE
z!0SU}>5C;WbWRLe4d$6Xl-u{&dE3`o)-tgeZLeG0_nY1r(EWH@Uq5XlvApVueSbec
zBEi@5`7>`6-H-QrKef-s;?a~PJ=Zk0E*om|b1s{2%YrNPHr}TW&&lU_y(|43Zt;jg
zrrY?wz0U%r_i<ZqFJ-AYwC1rvoS*s8CD1lr=I{5GZvMW_@nf-mF75d>KPc@BVvJ0>
z@%H(1T|cw4L{nUEZ2cJXxwNFxADxpn+t^s2Yr}kPuUmYqXD<1f_&KTj7<0TG>412j
zAD^TCNS1%`5$`d5(Kuh9`OyZU-{*9y%#Bn=q+g3^_PyrFkfm-ij7zeZV_#dC+dp56
zo8S8JvShh+y~X?I#d;=Qr_b9qZuxvxZD;yLKa+8Wp|4rTIy2ALpR?6z&za9gyZ-6s
zx9eo~qJDAR`H^wn)!YkqEttZ!MJfXl2Yh|kB7Qu-{y8qQef^>FKJN9FF}>vc(zKT$
z!s^BtUrmOX`;pNbPUn1{F++=LZ6O{@4tvV7HTUc1QSH&<eqPfpX4!q){F&op(zE0j
zUFSAGpQo?qb)RRtt;y`M{Ada2y>9LypT+vU&Dp;f`+5Cquq@xk_s5yv_qK-I^Z9fC
zl%BH?OOnNTZ%`+feqH(_ntfe)GIZusn9tuOL^KL*6VrXYp?q6|jib#mu{c=YY^%vo
z<N?yp&)$3-%D1?!i@d3G9-q%Vzc%Kaj+V!f<vY$}ju+-{6$f==Mi*;y>^>Srm=m2&
zHP_E`Gj6u6&D)GqVmju7#Vtnf%*A>AVzGHXl!!K=;>2vL=g-BZHRo$z1Gh?$<H$Cm
zk!@eBZhqF>Q(n@KbN&7thHM)XOYXknpiSYJSQ^*D^EI3AHMTxmEA1^b+B|>S)Y(jS
zrDx;4_HAY}_Ea=JPw&Y!K5L~8(<fsO-NsrBuf=RvBKGBI569G76&zKVJb4->{5Jw;
zV1-=sIcPI1_sKDA?2C0cZ&HT~C+p!n%zR;3t1k?p#?7|=R6Go8bE69HM3FaR%u}(#
z%`mMVi-z-Adn_I{wYDC^3o*?z5a%yOGv8<8c|VisW3jGvoD}Dy@LnLJEgBH(SMf*W
zGmq=%`EM3GqGwHVvFpxtkT?AlZ!?eAg~I&&IiOGax3u&6sm-sAb5pox*7dgeeb0F!
z8hhs3+GtZ~a~)hKuRG_qo;i%uwzaZ`+0?hvGYGG4KJ#n~K8o+h))|p!>#%&Yt>^rH
z-L`(~8KZccW6wy>%lp(FDTo8}A{z577x!Lzud;u1PJ4ou$LD;Gv-ugP*xD|DZu#{4
z_X>_-%!D?_^B#P1a=vlOZmZa_=(%?O{8H9uO`DH7CRWd4W;0G7=Z<I;%b|~Y-zE=^
zH^1?LD+yzih_;bFzx2ZQ(B9$!!akz$+)hE``8@?~R&4sMK~4FV%QbO4ZR%#*T4<kA
z8hzwJo7apn+H8*s@5a}rd>&jceXPqCL;n2IcO$Tcv*cX7i)T1m4r`r*e?9eWn1pf8
z!F~&WiDA!wvq2v|Ei`?8Db&uoFf6Sp=fuO0!snMhYK9Nugr7XQ9^=S<Bm5s<f^PO^
z81}3`*2t1Sztla;uR>a6jIX_oI-ffYj;)djCr!w-G9~vBi5uxJN)?N&Z{UFS)SFlw
z)HH~F4Eb4pk(-@SrVjQjKc4rK+RsYB$Bgp*qLty#FWqRL<(E=1dzH=|&*aPJij|~S
zL71K%ky1Xt6!Vv7{jIH^o)T-U4Cjt<>3s@y4+lI?@1Nn^#b^2b(7pEgrFY}=OD}St
zU&?3s-R3^ObQ7OndXM}3(!F?=-)-*mOV7sVm)_()zqCBd@8Y{YlRv){&+5ao{P?WD
zvyUDupI>?epI>?>KEL#Ce12(umLH$>cm6N%S$?;b&o6x@o{+{<%q@Q&Xlt8)`#nk~
zi8!W<pUpInw-fi0Gpzr}zvoaNE2YpK%jcK!7HXt!v}Fn}bX=Ci`0u6f>6^^<#S<p!
z*=jA1h$NQffx1bAvJZ_zQyl#*#dhTq6UNzM>CttB`F;$8rDnxBD2#6=EgyV7xtrVq
zC7OZWuF0(UNS3wPJY~x(X-(&A(@ERr=J?j;v-~z5!yGRcz~Eda%#UcP1_Co@TV2Ne
zyzLwaKw>)P9wm}kj@c1jwnbvODJRb7!<F89*&8>g9pU>s#lFX3%|2Hjr#>&6@AW>b
zm3`#eW$1JJx^asLu+^pa=j!zt;@uVJYh%}f(Z~Y?wJY`<&v-=RT4C3g&vU2Wq&5Y8
zx<(vaB$|TW*6mz#>QD~91lZhZ0F1mg?iKmX|71nd+%DH@F_%kn%SuDcwrdHyPJxjF
z>NIg1%i560gZZcze@&fI>}>RoE><(Ng=TA_O?fC<-<JaAU^ViW%O+Br?Z<kZnOrx<
zH@VH|q>%CZe%^dGmSf5|3#Hz!0gaeE85(mbwobFNcj2*Sw70(Gqu-0IjXutUIV$Rr
zhrEoem7~w^1YmHy#kWe3-@C=4v$MFlFyHO?fiem7=3KMqtj@FN7`L3fcdyMie;$|f
zOvm?Sjm(N>wJd;j)~2&(+(~UZnL<xC&yjiQjR?I7Ie76l^-VO6i)fVY_kCTCjIZ(F
z#B9z_;e8&dKrDv7rd{T)IUmKZWs*L>^yntsHDlZofpHtpr%~i8Q%Y|vC$W8R;?E|O
z8ZDyvIbgD8&ED1kJAIGv3_2lOxohG!{uRZKf5g-X@2Bz}RZ~9~wP{=J%b~M=M5C~F
zq|!=_Z*Ci3gnlw!@D=LdXNnqT65f+oN4<_oSnrl><A~=uO#JJfdvmsag8{pbsZ+{2
zvr&$=R`!^7C5a`AT(}lWbZbqHfkWkdvFH=@&}*8UpSG7+jIuqZ37MaciiaX~?o-El
zwmy#c=V#Y6!r#h=J_x<$8Xkn^^YQuQFK+X)#@9(q|99`P{yB8(wAaDbz-p%3^*~)p
zosQ*TIo?N|KYLOv-n-6qbTQ`f+#oetlNw=|G|ud($&j^;WrS|m!@t+`#vzMBZvXl~
z)-$XM25M~(9;J-isFT$mDyXrTc5XDQ;$vrPa?I-#26WWzEU8L?mQyjCj>(+I&jk}d
zz_w!Z(Nm%Ia_LTzCZ6W`WAQP!qHc>VgV&0U+O?}!hp^{GOvkCr$y(Z{(_VY7%b%=G
z!GZMCM(w6P=kj&^d2x)F2*cvkDVw>QJAYrZq;$I2u|nOqyW#fS?R?6;+es^Ht2@q~
z;kYtVmsZ$v|5*Jy445$A<}{z##)5u3-}(28d1h9JJ!|yV<in=dRBXNo-PS-q#pY)%
z%cGyR#c22E^EPVMrEbk!H%GGRD^i;>-gCdh`#WEHY#nxg`gQW__a0Yl6FT#`hDCg=
zCWl5Iig-WA^Zm)s*I5{1mLH*0%r1SMoH#^N&@<-k5~@qzbp7?m66yPGzzo;HboTl4
zOaJIr^G%@e=eQv;wib(~jP%U+V|+g5sW}Y3)EAxIBB>E%<G4n=eqQ6v%39Cn`FZKb
zBZBmipIs-Y9qF^}+TYfExtbrJ_m7#M^Z51j*J6``Vcirp=X_tA3w4ri^*D#k>2gd>
zEc@}kZMB*~P`c;sBl9|P>j*dM){LTFZC~GMQ@GCld0IZ>-8GSA{0aK|!taqOcK`W%
zFh}x{=VUeQ`<qRl0G&Br%<iAN`Th9l2SVrhG49XF#`RMBW^L>22fWQ3&e7+}oGl(8
zoNs<k?!|fW<5B_+c5aL2<UC&bHe+RcO`Y@ia+061`SmopDTj63nvxH$B=%lwar0Zx
z+Wnt3eT=%zZ#{j+Fw$`1bDZ0$Z~uB{H0#bkLy~hVc3(!g$cD9zxy9g0V*Xg{9?RnG
zb^}amX6z|x5j}HIyGGZSnvRk4?ZhGzk5MAV4V+8Oa&G;}rY{RQ{*O;n=la-OF5Mxb
z^%>Id#hCW*4?Aaz`!TEN{k2#<8*A}s4)oM5uRpKxu{ekEd%=k2eK0$+C}wNGucCgn
zGpHE(Jv4oOY2s*WdII7Xpta-kfQO+YZ_8s(o3Br-qee%m&(3`sAEDbCtsZ?8t7ETk
z+7ZocsA(*HZ1#0yZ?<czYwUQ9tp@UI+M8&Un2zmQ;IEm>nl|2kCV*Wt9qUa!)Vi$Q
zY`Bsy`OEpkMV2?7#~}Acu<jR?9$gZfgWTAd!=A#P>>^r`w8k|UcK=4qi}^Tj%^cKY
zpT2i6o)I>$6@~RTVcU4iVT?NC5zVd*eVDICOJez`k%ay|Xm%~iT2d_H$a)-a;~tW2
zzSq`J)0~k?5zg!8uIZ-z#c2=G*MA0T&6<3#X1}jA+H73UX0BaBO?F|N?DpC)n(r<8
zVrkU9O-{6JT@Qv%mh{6{b58pBy##-+hV$h5swbt-FMSrjS3yq1<IF<%3beDrw7R4Y
z@vJILAGQ{z)3q30jw{VIo`zi1ieFlVjk9BzoR2+E5qq9a!A!hw5D$;TZSl|;)=$Q7
zH6A~y!^xBNaAsHw=ZCeLHO|Ab&d1;2AG}_Lw}vXb1-`S>nx@rhfi0|^x*o272<H8o
z5bGBp#^0+>65nfH3vK!@0Fl@095lY}87Bkw<jeCWW5nwjY_5xbzJFl->E5FMd^C<@
zk2Rzo@l=;<MU7OG<H?uzP`N+S?>t$P4N^Y>joitX^PG|P4&C%R##od5xmNak-EggB
zb|xBsw&5Im(auG~^-0%{YXYxyuAG-~&Ot$bI>#;OV4l`YKj%IR&F(eYtjBR|oOc@b
z{bzJ3hk5j$LkA?UI|Tb(FY_r}2br)Q*G(3j_k6THSj(59kLYc^b}bN3*PZ;3m&UOU
zZ95;XkLSmp!k+P6rJ;jx-_WPtM2#_i@4`H;hx=uCt!8LEA8g>RpNRHl(0P6F-d4xb
z5a;!%dEI!exOR-Kna4&!tmYhuCt;j(MKtv3{=qq<^TPE)F4y*&H!yh%HuBRo=DJvi
zf|_Z~JWt*O6s$9`w4B1Xw)^!g#L3m-Gt}mFB6|wrH90fR`VkE|NoX@KqU{Pdd;ndI
z#@y6XpYV|OJY|lwxh68@I$4+ZD(rO5tVyB&U!q~I8e?kK#I;IX>BE|NAJn)%((7*v
zxx6pvXKkEA8iTc`@vsAG*XU|q6TH^<hwzA>giUGAk@MQ?2Wr}1#3#ejk8P5r&+F$r
z>-dwzvk=VjP;a3Y_B^FEoDwGNVOKY7;n~j@U`Cz`bGRPp>AYdvYh(Y~3~y?PW5(1&
z4`i~IKEL#Jd|Ax+`K6GG*OK#^@P3WhTZHqQ-iY$3AHgb($C=lhFB{zRw1)X>-e0NO
zv|<p0Fqjh2@B~J*iuLed@{oR&%A&l7ISA|#XVnPD2L03T!@77rcq;C5@w3&-pr(wI
z{6guRlj$0nxIItP3u6dh8)CJ|Tr77lx|8uMWBv_iiWA~%4DbE<qo(osrEf$W%UnMh
zbDbXE^hyppx$Ko%+vew&V$aii#y-C^?|JHee(6oapI>_Op)+rLX5RCZKEKrMc}kyO
z>h?TwkI>sMET3Qco||96)pv!=)5Yq#laKz0HghrBzVW)yrtosmrbIOAXf<^<+Usa0
zUe7+R_m_Dq^d<HkqjohK=>~>Qx|^|r#XTf%_TTeYEX&uB32nSy!^9k==eheO*n1vd
zmy`%@>`i7xadm2oJ=qlWvDItxHo@(k*t32tPU`*|m>=$%F^-|&Ju<+qsnZ{!v!`&~
zwx&o2gy#zewT&-*&6t~S!*gPdmI=AO{pXo)wfVh<<<L*zJg#2y#dK^Bw3$b-HD{}>
zUDme|5n!`*LuLJ%eK~LT$>z1QwMFQZn2zni#+rvUOt|icn}MG1Lv}8#TWZ%(8!7&D
z+xRt}fj}NhZcn+T8IYCA+Z@bw`0*tk{d(xzQv#){o$2+?TF*feuT@8?mZSIE8ax*t
zcX~~oZwwKQ`MohUZN_*%@`YtKO<o7uHXnUM;%kz%$s|1==c#Wo+xN&z*TZ~%ocVmu
zxLs%Zi=A9Nz^)?$PJBMy9MhAUIkD$7lli@Ks~Owk0pjbij^*0CKHkr#y-2JEbJoJg
zzP9AnHb*;_d!Dk`eAb)a`e;h&`8~=iV)gu*IL_W5Vz)?Q+I3~i-nX`3y7RF7dT5Nx
z>x8}E*2Ug*Ci@)PK1RD0GW_znmtPz2YQ}?Jug9LvIE6R5f6s+p(@(MSwsx~~v|Tgf
zv*NT|%ke$O$Kv4mL$B>R6?ZcyZHpNj&x|_jd10Q7q2K3Q9(`<9GyC}*r~mdT%VF=n
zw@>ag7Y^W6;lDJVb<RoAd|*w)(>WbRZ$DdY<#5feJ8uqDxocvN%O_T|WBv^;o<f`$
z!dRqIq~zBy^Y^+Iz*^Ec*b$BIne1(R8Q0hdB}VBrQRd?J3o$a1B$hsXACYzLF?rv?
z;;$^;?;{+YH`i=e=uB>*!nGBtE#LVp*6n#BI9Id^tr0uV#!-}hJ!jXw+&Yeou{<|6
zu`~ZzZ<i3CPY!PX@pt-pJm+-Y`J7VNI9M)2oc9KEl%BrpoDX^F`bXz8mAPybo65h2
zQUHr(j>Ua$ijN$8KF>FnJo-(iYY!UhM>GoKL(=ybhI6UePp&Wd0S4{-cvqlC92&=S
zZt^&2MPaR~&8?|M9!8{g{;AWCQ?0pnwDd2Enz}JpWjA!rIhv2{xpN=R@4Ujt#&rKR
zx*gxmcK+HT(UjcR-sClQV;HJ=aFWi|>}ZPXd*fYXvFaIl-H+<sgSCq_I_9@E!guT2
zT~4FsHIj9EzVt;pAog0HWpnTt+j)Gv_C{atv6;&)aa+G1-pRG^mzY2%Xnst}<!cHY
zlMdDTln*-z$C5Q$|9ywPF`18Xzrz9hUNqQwvNwIKR&)WEThndVfqLYjCtSZ5H{QFG
z?qmIN^XJoY;b70(a(xZ+`AMTUp!*!ZmR=f6vV6zw^e@h9->Z#N<e(y4-#)Zh?4hn#
zzh=%BTBHJr>6j0_+$Q4v)H!c#qTTz-=UR%-H6MG{StLWXd_H;S{bTFD?fuk^m-)wP
z*|}JL!~o>h>?tuF7av&L&c)@|Hp=F<-u$JnaUM->FP2QZull{!qu=H?9|xK*(kO!5
z+UZmqo5p5%;?3-bCGQ_IR@Pf?GzGoQO_$eQN=LPI_uixGPEv2JF$e3?_fnUdH8c2q
z_lVRzf8XYL&G~v`2F-k~+(UBKPYos%XZkw=bYsJwEIs#C*s`3}pzfr0I#t?ijr8i*
zO~5H5wJoFW)i8frlOH?u9&E|1f!x~cwkO9AeM4(6*81O5jjhe9L@2$SdIq0gx8<U*
zsYf1`OWjLp?B0C6v~0$CZw(h)k~LFC`hhuWq_T|&IsfFqu=(^@Tt3<ES@w*xQDQpg
z!wAzc)@hKRgO0wPE4Th=4)k6ho7<&(wf06|UsMZUubzOvf26<1*|>d0v2pxc^33_R
zif-?XX7g_t#?^eZ$$+&Y8tU-(B{g*ut3x{$C-Wh7I-)POu}^;ZQa?dbgpPYG<<Z_m
z>y5F$fgqCO%rl|R@qEn}e{C`Lh?zg>#h3DJ9{NJ~#Cv%x@8dOf#&gZQe~i8@G@f@v
zBO}@r{tjt|W*j4QHr8MadW|j#e05P%7jY~s$)TpR)J-;Ppmy>z2B|q$L}Lt6^RUJP
zWYXqxd=j45CK_!v@Tx5zX3a5-Q^*oIb)*47Ud=wDH=VW#bKy^Qi?6m=@h6-2S>BU#
zb^1NZR<bi=#%QBfYDMQ7YPif_Bi`6Jr)1k0+DN63*D+mV)}e6UKshhg;{Je?SH?Cr
z_I;$iANcKCg=*D$+Vk||zrnMA5!y=;=P!A`1ddpxHa!J<o@Q(OCt4e+<{s2WyD>&Q
zf<EGur{TKw={la@#OFBWy$rbCH*9XO)qKuVy=%gIU=3?rtFd;jaqU6t;qb2Y3ZI|I
zmahY*sve4ly$I8_wQ&9EYZ1{Ho{c!~q0INAECFx6Cwc$zzNF1ILz`fY=qNQAv5|%8
zG21+!8Y;)tYo)O`@@n|#Ph-x5&H2&DIW?G+nsc$SzBLBm!~T}Hy)uL!yMQ*orn1q`
z7E9yW?R5n;)rjcXunv<NN*!^)95ww|FYoypU20q-8{<3&&Qb0I`lvgb>$)6YtJ?K2
zzrRNMxOn<0v}0-LlF)~i)&#Y-7NMi@9BOoFZPeMg9`q@;1{;m%#YWCG)S5M2D{J7s
zqHAm`7UxZk{Pv+ySck$Me%7GWY^+}zeUzGw^N<;JHjW{$*v3+PGsgq(0mK5wp<_)5
z*Y<z@C2iz2LUvpqo0FP4eT;KHuFLK*>TsDq#kOFdLuZcFRN$*^4YVU{UUQsF4V^Z}
zqCNkP5PtsgP-`~&`Vxy{hJJ$P*GrvqA;$SqoO!%fuv5L5`*aS_)9a8u^O0L)eB+~y
z7=7GZ#1_`jgIn?;2H~EkgKtS{I*Y9FXlp}1yEPkWT{BccZOAkou|CXSZ(N2CP>qL^
zE5(_^77^v#S@NDI`X|McbBcj3hOj@*Z1$F7*7zK!*WkT0%xY|Fx+R1PdRi;v>vb9r
zh0nxW=d<f3s1&(IzUS_#@-@RLa31hp1J@c_DG{?#PAxg{eu;2}7Hc>#5`q(kQd6a4
z7aS>odC^a=!+?CRbI;Rh|HkszFBI%e;#vcq$5iLU>4PGEyB%URgB_daIBmoUHawjX
zYRrs#qdez{<KCRct=$mT`5dR)zMSTR(w?WAu6R;@j#GKglRd`?`;Pv3?_Hlh?WRNj
zJw3<i&`k%fz3ARU-<zJ})a-dW@4@yQr@N0FxcH(w&%f;G!K1&??s<CrNq60SG(E>@
z^XTi&yywpIXZPM+p5t`$x92@iw;p{(-t%-QJ?H68>}kq-p8f{UdAbBAvXP#PbO}!3
z$bt7K5b0##Z^i5F-I3$z9%xe=Ef#GHz3I#~n>r<;(Pt8&uu-tQ)Tmp2evZ>?4t0IB
zR+HFItNM;(v^^wOVt0Cu(~o`Bxdv69tBKcZIDP48N$AOhEusyH)oIzaSzEY=BTT$@
zl5CcqW0-F}{Z_|vX`3F4J}bT1Fq<6eRuiw$+SY@<witW9>MfS*-@>P(b<UqQC39`p
zmc8?~`K{+VYc!jOc0}`HG4G>3;i2N89b+7_w>`23Yme26h^2byDLi+6ugiM$$I|2N
zEeUJUZ}s|p+Q*Yq2an9pYvrD&Fa4#VB&#_T>-+pY$=JZy+K-7axPD4RV?NJ`!nd7R
z?giRj$b`c0Te$u)-pny!4u3YWd|TVlSomri$7|3RH>M8Zjep8`|J?JKc0Ufs*ts(1
z^_;u-7!kHLFU}l~+MKNA#m;9eK9p;|Xvzw`)n}^bYV-F?<ntxNU;a_X#`5~(7TL2!
z!4+a-*TA3KqB3?4L;1^mHrDEUhUV+{LpA$3A??lE^Tp=x&trb}{d!~e7^hf@jm1lN
zu<OrdwJh1Mn>zEE!{){3dH<O1=cPV0-k;A<Jf!D5ef_`X9R9t6dZg1ygigQBW%;x@
z53f7*;-@R3H4>rCIh*KGrS7kvb2+J;p45lnXgSdZ`Mo~HV$`j+`DnAX{9bz@^M-|c
zOoqkkTHnvI`TG8yu;U6vhStS#wyvT0qSyCWtmWtzMQ(?m<2`*n!ojh2uQBfR;kw-%
zj)BCH+~l_N&8Z8Il|_fxlvr&!eIA_0*0EWV@O?u?b*P?Sm&Nn=Z@aq;?{t~X`2FaU
zeeH;V=gPd3co>klqK|2It^-4sy8QY|a@8NyU$c)7j2~p&j^RF>@9g}Io;7$5$9f(^
zYiQ@Yf3@RTi`{#xub3<^xpGlH*W-SSUzFOsA1zF}AA+8teZOzhGDc3GmE~LSb4~B}
zeta97{z0qvwY=Y<?>(OTwqNW1u%nxV47}|^No8!9Q$I7?tLKvC#uXgpui3KKzvV8=
z8(!VG*XoXEwCh}Ujuy9`H5b(%iVgY3*G87l{kie@>XDu1y86uHna0BUvCL(0e?7)(
z<h^)%4vxo<{cF^sn*EqR7q461kk4ZMe%X01i}&ko$6gD+^TzRf?jf0%RliovkDT``
z<FqV3U$OPXR$Zu#@%4Vw`|F`?vGGaB@%HrD^FulPnnO9}+fJ^HIhKCeJj>5{e%56*
z=SK{^FaPL*pFfB1*P*&YzWeIEb=C78V(Q0I_c=b+KOc)(zV$xOa=b6=+=uf|@0|Cy
z9?#0^*!zOn%=URU+Q-ee-JUhZ>dX-H=gT~^t>=8+&+lRTHgo8=F^rp7uJz`h@5!?M
z&*o>XAtsC)Kg(sF<yy~}Ux($c+V{sUvwdBz-RILbHq4vx05Ko?K39wT9Qr7hOWoqs
zy{v_w{fxJ%x12tDn~!m=eWpHcx<4oSI5*oST14Zz*i6Q38)td!*FyZN+_!bPw<y#B
zEv<JtS&QLP%v2$fHSqfe8f;TICKEizDdM*h5wR&6dUGIFBViqTW7yI)s8M4bf6!mY
zHYr@NDqIKuLs4i~SVL@DO)w3HpmD!b43{I$c^O*^pZI1B;=E`%hES6H*>+h+jgHW^
z#(?SUqqCtV$@AqHb&8F#7=8U1bIiv$J`L}~xzERLjC+f+_}33THrJTWct2*gpTpME
z&u0!B?-iTNazlRp6dxs&a{6ndpJINioxQo9>FgK98RHtb7O&gd%#U!AweU;Wa@PvS
zw68DjD{AL!{n@w5Ypt!^)$APD&(I<ob>n9}eJ1A1oVd2l>n&z$%dzbBI_p?t)a!k_
z&xmpQD7J?Fc*cxzevZ>#x(0>o;&>BZYe+Yr@BP@JHCZn6s58eJeO#-Z6Yad`=@(x^
z&7R{#ox<@HTyH#6iF=yNhc_$uxe?PO=T^<0CqH*Piff67AGx2S^7HJtHWRnD{p+)|
zrwJi{HJQmhPrLpfj)&k~5qnChL9l-zgqjD8N>2Oix)9;Y11e~g0wE@)hND8mWRV@D
zoZ3F9F&R7~Wam9kHBP>whjX%LOH%ec)y2d_&kf=CzpF7DrK+!QbSkk*W_cbHKJhe7
zi@MWYk*h1a4Y22FPfkn^-P*7d#`aa7@`JGF=`i|qdg-(4zU<F)`rf<#0-s%XakJ;?
zqI<8wXV<+yeRdu9JY9U(S@`U_PqllV?mQcxUH5b4v+J(7_O?6u*>y+KXV-Dh(>-^d
zJv(~v2g;tOZ@<`{<HXOd+dTT+XWn$+;@$Tiv^`IU&OCzsR(EaQj6F{uN}p|a<iPvN
zXV)FLmY;2BSDMdF`m;BrHRE8{)@=5C|DoTwTaMYxq4e$Soj>v(WUiOKZ87GOZQ`4p
zT<@zpUz;q~)@63vx1(F%3fg$V6$a;&Q_`NNUBA#DU_8@n2tl)bUZ08C=xgT9eDVsq
z<y)P;9Z`cZ_9m7?n=wz4HpP6_XYc$qHb45>=^eG@z`Z$>w|0UsEY6<7K2mYg|9WZb
zw3NP0zxO%4wlUVb*w~olk2aw6ejHshG|#Ia@7u_&InIk8Z+d?m^Nm#=ORk@`bYHHs
zo=#x7QQN$6c`h>Y^b2xpe(~^euOpOX@FXnQ>ur73_rl}n-oWF2oO>_tkCVNV1jzWO
z#CRu>&eam*IV8vASahHAIZxw~-cs;J)V#Hfr*^)^Fm3GpYe9+e&~X&w`}5HI?~reJ
z0o+6KH~lZw!>RJFL?B;Ia=qX$Y(W1W>)V#s?|q)vnRgtwO@Eqg*}UiOJ0Z89|AenU
zHRAy|;cZR1tz<i?`Mx>d`Ow^Jef8Hl_v!r5g1;>dOeWU|0kV8z`n~r^g4`<;;NB6j
zTp8EW#P{%5H6t>-e{3XK?u7)%auMr=gB9!$5X%mZ<1)BMMEB)!AzW!NIp1*mN~ua(
zKtLQ9z}dkN_vz?<-5H={`Oc5+Osy~UD%>OVxx|v|{pNT3tHz(f+dWVCqj}j|RD~ES
z#PE$G8x6Mn@kwsa6Mt=hR`xvAFxarY3BQ@dpWR^uw&JK@u+g!GHmy({Eg5jwH2L>}
z_<Sg=_pWnMu&fK2C$w-+Q<v`vz1(JTT=#PapJC9XJRl194V{SVG8lL8<uf9AKh{X_
z0e15_Pm9+6KrQbTUpGE8pYvp&6KB6o9>QO5?6+`JY+5wFTT!a@+2O2>ALHST{Q-NL
z7X8NfgWrhp<+JPZr0vw)^90FTfYP2PSdp%@>Y5rP8Mf!CrYB7}t*AoE(ql@bQPG?B
zJmG9=zWGwxRnigZU}c*Z11OI;KXp9VgHRd=_dE><_9oTNUG?`og}mnpDg4M&zW3*)
z4D5MIOKtW_u`Zsa#3$0EJx{kjB82=Lr@OJ|>7u;nDLu#OAoe`rv+MTW{K<nyuDJH%
zyEd`s>7KObDL=<4e|Fsm_wuvt4qcr0Jl&M`Jmu#&?Zuv_BWcgmUiaB`-1Bs{`|P>{
zx83=A?rA!Lx$oM{&v`l@dv1<k?mPG9=R9Gpjc^aqi6+-SW_(5W=X&e$WppCn^t&Ci
zV{nhji6?wfoj_90uZ7(9pEd8_Sx@^u$GY{-7JtC1?dhIYXB`jh{TSU^ynce+k8YKw
za<9l8e+R2JkNTY^@cF+V=l;3RFZ#3bD?`ST<0HU5O^fzC9bfe?jM3a<@`2HRul$9<
z;8@SH-P1H*fm}cT#D7EM^_@FYa{JT`J6G=usnVkRk^6KcJ3~Nwo_2;Kt7y;D&a%{g
zhn?fOh^6+A?Hp(AdD=Oa+Viw?EEnw&A!o_)6VRTg<7a3U7TvGhrz6=J0^0MmGaOmv
zb8631m7n8edvdtH$o3XZ5yKzKEBuAM+4Iys$7#wxqF4AUdJJyQ6SpzpPu#gN21gAC
zTiWjg#~O_Ew~pfAG;I8%J?EZQ_)|F=RBV6>_@jB1rpoKee49N_NITKxMBekXXzx(_
z{HYU*@QJ+ViEBF%_YK(<T(masc{<UAdzu#Qc}nZ;>@Tu+iSC)Ky5}kFY3dH0x7?nm
z{%?%Ar^)Ym!dn-lpXK&E@vSm4XN`xN2S_rw=ZQ*9PqXKV1MsexB&H*ciW>Jk<pC*a
zXwOqFQ#S*+r^)YmVwpvfpU31syN-LB@cvw-QFw&bo}}2Gr#gKtX!ktXUMW1*2~aiy
z_cTG8Jx?FoJo-t$=ZSlo{GO)|o_+Km^JmxDo+s{UYWF-n^P+n{<M%wZpIyi2Jl*u`
z`8iJf?7Fh&iF=ydo~QiTbqCXD*YP<|`LpZVJx|;t<o7(K)t|rzu6NO%rxR`I+(YuY
zwB8eq-`IM{_21iLu*Q<)pCce{b4Yf?!M!57ACDj9qP-&8kF$*L-1lX31IX~|Uzu~u
zu@Zshd|8Hjo}Tm#D-~4I2m$SR8UeG!O>T?!m@FBt@CX5M9Rah%&3!n!AD2MdMtIS)
zhqQle8z7gYYR}UWK-&mw@5nY_{ZIDZ2JDinDif{m<RpFxQN93?2u`eyogaci;4;zi
zYNqldlWuI1G%X@VZz4So4>mtD3SJSzPNs)sd_ddogbM^s90{1rB+uAFaLD)=VZ<~b
z7l-iE3EW5S#F>ozT+EDK;?;21yY^nYR@FJRzw=XHcU7IWzNf18Ui)wDch{+NzH{ES
z_9j&g%S`~9v)K4!a{{(tb>loO2wbh1adB#ZY*E&5ZU<P4<J1n0(n~7#knzU^rRA@E
z;XI8B`Z=8riSv|G28aL2oqjwQMc_PzuuW7x@`oq_=Lr-h9Fg-B6fSU{@S{9vOk+~;
z5BZ$Q)`J<O#1Hl*=Sku?i5XPLB5|H1-}P%(IZs`U<Fwg&8s}*<gr=8wHICDCYrR%;
zo*I8a37jYC2Tu_Qo>C&<JT=8}3Irjp+A8O%7Eg%=aKRo9dn9q3=s8OQt49T$AYlqQ
zCmb|*tV$fGI5lQ4@jMGE&QS|31JOuxt->6u@ujG0jq^mBq(p9#aF=`>Cwku~xLu6n
z<T+2+yN*YeI8QM?6gW?No|08KPce>Di1Q?IoFeBb#BmbN)4SeuIPP7CI8Wd-Y0i_x
zagsPsM;|$Kt>!%Gz3X^yyAa1o;yg(lCyDcf8EVcG&$#0!<2-eIfo3+Z@#z<Pc)_p5
z<V525#v__Ar#A}YJT)!Va`&V0ahh<QT@MUXoTu4)vYJf@7{*P=w5PW?PqSf}isJ;1
ziOKv37&m8r%%nw%n`8H*pfumrI8XE8m8xxVoKon_UzX&L=`Y*n@7h`@1dOMnz*sVA
zSS|^mYHnC6Fj`2a_+#LZm@JQgadDQ%P<lwkAF}&ZP+IP4oTugR)2%IzlSX6tbc#O)
zPEOZE;y9IdF}KKNh37oc59hUbO7u@mPNg`&c_LnuP@Mcv?(|!>D5%U4uc^X$A_Wtm
zNQp8Uh84nj8WogPoF@$9f9m&~rx?d6*hPg=`hjmWH|uJ=q%L!wQt_v{ygyu*<2((S
z^Q7ZAf%XHTCs;-1;XHXZQKfmAp*T;~z3a*%iSxwmE1V~`%7vQzgK>rP<Qo*BJWQeF
zJaIvS^8{v5t~pPk0jaf=oTs2|;ygu8Q>d30oQRw!iQ^=kr%m>*TbqavrS`6)p2y%7
zY0lGyk4qdUALmK$UB{fKBYN+;E3VUf*CEbRjN^3C(Z6HP(+=93PH~<N?z-qS&3V#$
z*Mak-_pXC&0fxwVl6=>%#(C=c3bkXOadX<ivEGZ}T1RBIJh&nj$7wdK7OiD`oJEnF
zy`5n^J65ThDQ+G(PbO&uz#&O-p3<$Yv<U&@JT)Pc)*EhVd=@P=&eNjEO|~=6(<CN~
zYQT3$ah?|KcU9Y^_zu9@q#Xo|r_&CO=*6&X4@+=FQqO?)Mq2HjjPuma`Wuez;J8^Y
z#(CNdq1nrg^E5kFo7Dv8CdGN$to^YrhrLzK6Mj-JIZw=Ks&Jn0p_>j6k#MNJ>p*iN
z3X?wq=gE-*hj5<8l*w=e1^7-lpa9KjR8a49aE25z3=}wEujV|FveVMlI8K{^)>Y0^
zm*Y4A)71WOUFKtTmGhL^yAE-l>ii-+CF-I%Pf|7t2|TSJO`IoR>dzeKN$p*y%OtJ$
zuJh3@%9t16Jdu>#qJnZc9sF$LhhWSI=gC1+<vaz`b8dx9fjYu@a{K@$Maj&<9CP73
zRk&8wz3a*r)PMw>rzsNSG5NA0+g5N&I8RxX^HlC#m#v-UD~7%6f~nGu`_+5b{omh`
zWfI3J@Q%JNahxR1lis@yd)w)~>mE1<d)w{1NOPXH->UYmBhHiFyAE-lB#u+$JQ1f!
zbDsX{$Fodxo;(Kr3=UD(B()b@qrLST;TTN{uatlANb_J8kEj`&REcqOQs|`1>f9Xt
z(%AC*Q4f|j^Z1my#fAk}<i<Z+tZjc=P5WfBb+ZA+fBef^*Z->YoZ{mE<KfA%y-&eu
zvio$oyJ#BcN&c@{uIJ&me#eWO=LlR)=10IdPxE6YEmHBZz|)x~_FA8YN?HdjAG)Qi
z0}Ktv5|4RO;5+=}cg@qn>NX+J#2vAFvk9@Z{<lBdTn?;F+CiY{zHO)X)#|0rd9v63
z;_H9!{>iq2CvY}d9s%I^=zm<kAL}8@Qt`6D(=llW0pmQigClzB73Zla_pXEO;1~Jd
z-vj3f3dC^=oF~s|!Ush<PzHtKJb}jK|8t~w6_kZIPL7l)lQ>QpDNqIlnLr(R1;!o~
zit|+AT8%SEh4aLkZlAi$d8)@tqE(9myS3;ttv}Xj@P_{S^kY5hY~yt~juU2(;$wmH
z)HMO8DaCnWd&Ay!!YuMniRw&d<vg{zcO98P0qjV`GNf5b&J$i#Idp8bLyCkm;5;GW
zpyA)XM}>d3;^7O)`HW0~6gW@50eU4Ve=vt4Cx!3E#RlLs{ry!`=w-rCDUd7TF;QP7
z=V?UY|7i5Q;2IR~?<`IT=gFZqp8ejG4T%qhz3X7#KmL$!Cvl!Wzx~#)YtGXH=lD2I
z66Xn=rYh$NoTe+TlQ>U$?>g*lw@czU9Xa;|>}{v_uH(J!4j*~5<~-5Z70wg!t*(>3
z>yFaicHjs-=L03@iLLMO$>KP5cyW%AX?O)1=V>vpf!nWt=VEQGRWkzMiqyGe&9$wh
z34uBvhu>{O<vJfnmo@cg`YHmz@PRK^b(U)v0dSt`_i?);48ON&oTuT>difa|H)nYa
zr}a?B)!uuip){!j59e=RHmNtwVhE&S4>j?}78_}`TY>M8!g{sQnQ!*S9hncWRBgjD
zh0gqCsn|on+N2!>>YS%`dR@I<fMbe7vU-SY&5Y|f<MY0K=AR#H@Nj<b$L4QmEv6%o
zialifvFVsCqU{UkX;je9>2$ze#CggogTw#iPCuTDB5<BU*d{8+hZ{OX5janvFyZh|
zJ9^>;g(C$HC@P#M&S=gPey}e&Piu;6<?W(k65%}gT=&mi<vevYj?-o<+T}P;UFJMZ
zi{nHu%1#S7PrrGtH?fhB6F5&Y5j;g8cuI+Y^VAf_Nn_9|=cyJ?iEMGf9;N_E9H%UY
z7FLf6Izhq|a!xpC@K}{NPH}3UNQ8M7bmXXomJZKaNQsyzxJ9&!2HIVT^W>W~pDXd0
zxLTF-w2`fy#cI!a+7MHO^Ax#K;5_YlN|wFnsa&1=jd7eFJMsi+Pn9@M66fjQzQ?ZD
zoF{Oad>kjwc><?NbDo&fq&QD{?>g*l7vnhHw(rct*xQacO`7v`<eb}Hr#Vls6dWRn
z^Td{S{A8S`jxSJ)=A}3!TON<7#d&n8t7%-Z@GR|;nVq!dHScRStIo%1u4yGr2mnLl
ziZr3qj@~eC2gg(|#(7GiQ<kOnt^>!!WPSwd+?@G)Slt$>ctmzTE_Pplhm*o}v0hiR
z6|mGi9DHuK&+d!g3#m9x#&=j8*Lq9i>C_QfJa1Soj$OT_VOd9HxqOO01`dhI@(9$q
zILr6Ax;>=0V|Kr`b6<dmlft>3QC6cDi{sSpI@kGQ`hO{Ka=IqZ+FrLP#BnM-=ZOdc
z6tJVnaD?CA@gurdfO|x|CZRa_pWJE2qM$NI|4vpoPo&VCCmMzo!g(4MlvSLka$L`O
z(tFqWGO8b>i}+Ue1{6#EwH`02T6+9)b<Pv+VH{nMR2(Ppin=O&<2-d0N3l!Cc`6w^
zQW~zrdD3y5#z8%*Rhx(N<k>{E4kSx^+tv5elOpV0hrR8DTU5q*Vyj%J$5W|ro_vEM
zl!qyloF^_waGvnG%{AvKG$6H>GQL#M*5W+Hx)P5`6nVj^$a#`DPFdhQNgOBPJV_j<
zK)+g(I8LhHQ#I#F;y6j1rwbq7d!yz&NgSuhc{*~=rJD1k_pZa<cHlHsI8Wd-J#y$;
ziSu-D*F~pk&XeA|4tv|_z3X6`;2?3HB;WO`ah|%qLhaZ$jhoX>&#T>w;kwxRgDaBa
z;4RjxwbBUG`8Zwr{I2cna~c?1oTueiFvZOS=gB0E05~Km&QrRzl{O(@oTnya()v1X
zUHRT9ZFTocEzVPWYgFevwb%3N^#s0y=8vr&0`1N?#diSKChZ_#Je_uML@$PAdsu=a
zl6nTTH_~eNWSpmV*1wLUeb>|uuJv9l&Ql$c#q-8_S{%E2OK@)LoTqx7F6Ciwm6L;?
z)Jx7&HW5z=AG+xP*$9W)yACub&y1m`Uf?`AQs5BI)0i?Dj-UYF2?rFQIgJYHoes{B
zLWY3?2kh0HCmN~K0`AaF4|Uqasm9egPg5%$2W6MzI025-{%~F9V@-?mbR3p<V#w6q
zb>KYJ`9*k2)J1ciq-+!t^89GxJV||AInEPtno^u6aGI(%m250<o=8e=Q9-$!4t}=r
zLojB9^W>nZa-M?eIk!TlKpo*cIeH?qlvYBK3+E}uaq@OO^*O#aodY!~<~hz&nTx3y
zkI8F_xOZLPE@f5DQ@M9t1LrAnrNDX8d)Fb(lf-d~ah?wDx=wSR^xk#gJb}}6VTJRw
z?;_24+J5Vs&eWVIy>}frPvA6FI8VfB(wrxW<0NsOA}W*shp20E!!w&L>YKe5kEnSq
zQzgdDNuiT2t8;V0!<8G^{g}qCsT5q1RGg=#cBY>lfjZ}D_Lf7fIqj3-=5zi3{!Mco
zV7z*=7>-Rifzx!~?>Cj2eij6b^E3-e)9a+-<^Wfd`4Omdp62gibz7wFNAPq^+CiYs
zdBW#<{n@^qQC6cD@EuZdo>l{ec4leZk#=yDUQ*l<U~SS40(RfFgClw|&Qp6>rsCoN
zXOra-sB@l{?{Rf|NZqgC>6o;GfN`GM!4bVo<2-ftf2qR9agsPs;1>zEXhdZh6pHiY
zIZgPWNC(QGP@E^wnEZc^G-H&J!jS?8$|Q~x^^D)>S%G12K!LGGh2lI-#Fr}fuH(J!
zs72QW+@UI`tUDI(u6@@`s}==zYtdy|f2`Bs4W;5d9cz2^cwLU;1UplFEO4H>COVE&
zqitdDI$;)#r&OGk^VI6zb!0~w$Ejje$$7$yDn}Vx?T{kj3^-3nIA|j0iC={ys6s<L
ziK!+DI8VL-R|<_#LXT*!z2UoYu|X}4lR$_jQ)MC^Q+4k;iuZRGw-e5j<B?0wlf-e7
zI8S=-I%-%*94AV1oTmrQx$W!1c{+H-g=;a6Q;hR;^c$M<r1!2voTpuC?>g*lCvlu2
z=jrf~H*3z5-n$NQp7h>z*xOFxI7ytRsUUSoX>pu7v>3<H6yrQC2EO687;c-j0#~HY
zCEKixl}{p2kB<}H__<=8kE6>bdos;51c0H%ahirqdpdBQ>i2Pby{|@3#(7$7osFBb
z7;c-js^e<!J)0rs%Po%6Y&gwYD;0al_+zu8xOqMB9a30t-h<T;1dKZ(NGyLfESJYn
z_h9@njmFlcjq}tFw#LP22gl8NspE{#`}UcCGt?%_EsoP9Cd+72v4@O5whXe>w$nII
z)f(N%jSBiXoeqiflv4(W|H++xJQqdaJcY1LR8Ifk;1EUNJb}W5!$0lli5C=(6gZ%$
zaGp4mtp_ux9e%JcIZw=Ks&JmDm_*_{`CRv(tzC`t)YUjnvaU_nF2{N5GUutQah#gg
z8G6lmY9!<Y&Xe?mrw9a3DG_j<n&LRogDFa@oTpkmB^tzqftd3oah&KmO9HD$1)U&a
z3OOenG<d8^9H%%nW-#$Q3o6c03oRX<wU81qQB*lkG|=uWQ*oYrv*vRp9urrqa-KG_
zwX<05IZqp6%325@72`vJ^Q8B#1D7hsaeC~?6V%D6dha^k+iu@u*K5v`-n$Na+kw-h
zIZu_n>yDgzg5J9hoF~0^-C^u)N1P_jd7?N@k#7atFfnk5{_N9P2F?>twBsk^Jav45
zS~M@kA+dNwivew%r^RqXtIJNUv~@aH=i}%yOV5S?FdQ~lBzz2-4UR3T1&lBJ;+AyX
zp-zu4&fq+~=)MlY(NR<Cd)I}}^lU9SCMNSE0Nmd3;`!TIi!4jUBeMH(u{#7joD{B$
z^}3p^ERIvV>;B8P#Qq$ma6|#O#H1YrjHlBMj_Ad(G%VXgpxvHQ{4sDywCK<JT5stI
z1f13Y$A7qAYb?De0;%{z_4{?vF;=}DcsMDXR~?^u=5KMF=0R)ox+(q`I5}OD$v8vh
z-gRtmg<FL0K<S^DJS+GB=ZSbtLUHmxxzoF_D5%U4^{B#mB8BEW75pz!$$1(TRIWHr
z7|Q?D?>SF;?>b*b#X<UkuUMO9^>|5T$?;9qIZyapg`*4dncJcjj#4<HfLGL2G0s!F
zD>EzSNyl-*(+fgRu!_vXdGc(cO7k*9d)rm_t}BbMcOCY&6K+u%=ZURyp(c}&Dx4?Z
zpa|t*3MJ=>3lf|syl!*Nc?u0ktp(I0$4~2^1?TCyt8^8gmUv83k{6tcoF|Fnlm*UH
z;50?flf-cf^sBXr_)sB^lf-#qP80EpB+irGyAE-lz-c<DIZu_n>#n#??_Gzz?P44!
ziSq<b(<6tjl{in8z3Xn<cc$LE4tv{494CqMBsfT%C&_pHYMiI8uTVSo88@dL9P7Op
zu60Ca%Y!SD;^58Ji`7aYQ0F{#>GONa?hcnZvJFQRVEpK{F>8qh5lC_Kz<DxBBLEIb
zo%57#VWqPm09=h@G7D1GI(6Le-ea;n0v6|Kc?_k8I_F9BcAXyqa7QeT)BLzKwMg+D
zj6c?d+WdOsJk5_;Qwzhg37Prz;E1H20rU50Ev6v=oQ*>=4Vn3LbsX)xrupz|sO?CP
zBMNvrhX(Is7pFTd;if4U(E-bs{Kz6L2hqm0ISX)Z4jpZ?$C>(Ccn+|4*K_q4_({Fw
zJP|p7GT9j1A{?GAK>y^3LhW4#nv-Y7&{HpPo*XG~2<K@`8Ga=PML`)H66a}D&<J$U
zs7!*AVTAJpdo|~YM%rp|%M1YS(8(`fribIxw$6DvK2}VQ+T}P-ur{?nT$lM+U5)ef
zx|dDf1EK-vsm?FL)2l9;^CV^T1Y?osM-%5s>f_3Bo`}<w;yi)VRJEy$rv%OuiKhTb
zoTnTrw%Q>@!WrQ_IcTb!r(k-{6_F`WM>tP`NE8~OB*PqY;XKK>A<mPE;}ob#XyFB%
zrzsNSG5NA0%L`5k=P9dlp31%JvbD2(MT+ADbAqYTj{BupN*u>Y;ylUTburG<!ClvB
z&XeA|4so8qX}Yk&dD?f8<~(h`^-X7L&XeA|4xA@&nkt;9qmMjUbDkuQlf-%Q82B?d
zL|u~`p4n_s-|QV|JR;Y;LYtP%)E2mX&z+n0wQ3b+!tVe4L^CXQKQ?2NDgjsI7vGwy
zu_|TLKCR3;_jFre{0np}C*^0C<@!0Mt=;^iHDh_n|0BIk)&a(|NiT6sP0ghW=P3iH
z>6Hhi#U#d5lH<eeoI-6Nx?RDV*-taqAC-O1)JD}WTb8M57>t|R@P7v2m^_^hE%JYj
z)=f`qjHcJ<w{{wy<%}MEQ<<)(fa}&vvDHH~-8*fKJMr%@aNG0FRQHYdTps?LO*LM&
zEP+R{Y~N@<frsi;jXnLoeD?3E+O;HjI;$ho@tJS_&3ypNzkX@i8=jZ5KQqgAE0}UL
zXB<($cTjPjqTUkoBQPI#r13dAW#D=0PHEm#)hGT@v*Eznq#Xq2yKmbWvmd=QzXwg)
z@9Tm?a^lBP>ht!#R7YwmrmkKK`TIUt(K?+2&h5%-K4XF7^}m-wQsbi2sWz)w_Kg1~
z^ParN!PBXJr!g%r?d3WYyeILH8CI{e)dQA)T5U+Vd9j+e{=|SCQB*K<^1f3VS1Awb
zQU^}X^Y@pvn^VUEuhOomb`<Npcil}d@}=Mx`S}LU6BLp2bUD+QDx4?qniS^=G$#L_
zBfU$bj1-O(I8ZjuPR+)Y$#Ae@toE++c#I0+JW(`|(U`bamr+NTQ3F30;QLShD|HCF
z_#Q<&IVid10z2fuU^+cHIJiSU@G+@}Ykl3t_G$Xb{+8E>z2oc`_<c(9Sh>;`*j>tc
z?fZbbt!2%2Qm~1|5xzJw5%7jy@gF3Yx{8f*P1S9qY@ETikKJAGOE49E-JW`RQ$5ko
zb1l~vt$ylDx^0Om?n!W-%GZ(DBv&cZ?d$W<Ws9c8UVjCr>Ahb;U!t#%N%?JW<?k4o
zM#D9wj$E^BR?gGrd)JX2mz)|nPo9*i?@e%;-uy#k#5Tt^`8ZCnzak~)i5`>ma3jI|
zGKUihXTW(v!a>8mjS9R%Nk%w@hMXyo1?R~(;7a<dS158)P&ba_I2ELz2H-UP5aWwH
zzxX-PbQ+=mEMsmGr>c9`QM|viSS_3<=k1lf>oz1ll*D<u@vpdg<UC0nC(@n@&eH>N
z|G2L_`QQ~7t(AM%?Yr^dt`D93z&S_1p*c@_?>g*lw@czU(cX2~+fL#*Mb6XVBX8E6
zr+tt8sp35SAJ@F;@UH6+W6E=$ZhIX#LSOiw*t_oDlZo^6I<|h|g!`_%_k3FC(V(86
z=wwL+7HZ6U?fu4=(Us3H+3A)y2ZtoZ(b{qY208$6wYWO-FRtM>KW4MEc-3?K{TSY;
zs7ZKBi&x!?uT|ESGHHYSh~8;X13Fz(r%^8@Qdh3Ju8bvDlu13g>iS6Qy2wjCxoRD~
zFQ-M9$Ml=OOE*Hlmq9@f`}Gkph7d!0W8)G|uI2k3eZ*lcokllhS&q!c?w!|An~Z4R
zjxOJg6B$3I4%etdG&p%3?Vfcu8Wh~$CF^K%gQF9K-q3QMFzphY?LV+lkZx^#+X-&l
z{_HGN$lRD3oB<;@Zr;6(-vBRJca+^x&<R52qZ@oO&$f-%^PSis)}2<+*r$a#&=~ts
zWj%AKKPFqQ%(lHJ&(Zvn^%2eY<cm=u%g>+_DM;?P8FssM!GY!gHMKvLE+g2Ut*>nm
z4#hajPb{|W_c#H=*9*ou1F@zt77S007_Sw1Xv>f=hP?9JH!wVzF+R&-V2`0-yv`Ut
z>kioJF{U~+p2ip$(nnBWym4BA^!m0@z?dPW@(pSOjPvzv``2@i@x@$s;}SG4F{Wzc
zozEgww#FDEMM9X}ge!H3wFkxp(fIS6FuciQymm1aK&ZnKV|}j?PEOrxm>cSQjA=Z=
z_;x6O@h@GCl*v{h0B+s~UcXhnce-C!TE{P)GCPsltUSy9vi2n@UT7k9{-Z9FIxBc}
zo6NaV4h+BeXlzj_i`u~_QukqF+00mhV|v4Zc|fE`ca$QgD3R+-d+B0YSM;9LmP}xX
zH#x}6V}R55<3HmY*?D#ZfLnWU^Ync=yA4CE30%+kR-Rdo^K9=u1**0zh3;?W*OP9v
zNm}<wuiJ^&@+Qrz#o#@D=W<<CJ6!QxD%RU-@pZTMMgYGoh4t2sKCIr2tJmIo8kX&0
ziJnri-hj19I|zWYm%_T8Q99X+Ytt&=c;g?n*`xI}4FTYM)BR-$KJU-=nZInaqA926
zU5lGnDbw{VJsSe4{VhFTceZ}4RvH0tAX8YUTQ5}V7HKsqGMCW-d;i<n_`<N@!~fq-
z|9Fcca7;s(JQ@lgZs-t2;Fy9kio-wc=!q8;jubecU{)4oXk-k-3Nis^umZ|aLA}$#
z9MVcWzl;U;BCehYb=+wISM#Qax@Y2XjGO0{K?6L_Pk;Y1J#1ZD*!E$1>2y)RA?>Pd
zO?ZK0DslB1zfs=if610U1pbjI=n9T05h(U6RZQyVN4`I>5Mt?+go>+Iw+S567*}uP
zvaCS+Sc?=a%rOOr6i>x0hYnVc3OYf;6mm{DXz*B-xOx5o9F#s&P%cL;v~=7nCE~bI
z!9S)%yJ(=@S*GIZQJbVhE~s!tvnt0l?iK1erZH}wa7+tn2ac)4&7%>y-xxP9#ML{v
z>o9RhZ~MB$)vN3k`uN@(!6DTgQ*cN%$Mn{{hd!b?rh2bXa7-WHd+3^7nq#{C*4I%?
zzsNC_xOu`c1v226N?g4pQXMITy?x?r8pm|;8z;pf1+FIZBQT9)s^2f>?{Rfnyykt)
zbFK4nnrp6XiQ8=E!0?X!o7J-NfPh;B31IxIFJ7eOVB6Gjtmo&RI5<zw_|<uv6;m2a
z(@m+CR*lldQ%h%U!ymtW58)&J)b1+E*ybORZ&Q<iW8$Td#8zEro$I3G$N8o^m>Iuh
zH^A)=Kb5Rvg$)R#xMJn~*w8qsE|R4!6dvb$xcS}%59h!9+ZJYMU1Y#g^KkIF-9Ec7
zeq*S(d5(I)5ykip5sIY~#?x6E!q|af8KGD@VOTB=VWoo<rwJSqE%v^p(U_Wc)3m_x
zY|p))R&2V>5pYuFzK=_4@>;)NCu^8y76ib<(cH0F+E|_G2ms4t%)^;(NdL7CQ+UOn
zG*1MaoUX~w+)=lv+$)srt#FI*KRJCZkY@!S;5-qpNhnVKS9W?A76p|#`ggLzc_Ib<
z<jy20lok9hQptH56;!S`PZ$ac9HXMTSEw(eq9FaiSFFvlYJ9p<f4oz5&J#XY;pl>V
z=C){sqZE!P;1zXMjPum)%FN1n(sA?f6oJqatRnMpo|0d@6X%J7jBu5bRpf^f&J!2X
zQ_;uOLoK$-1%tR*h4bVa6rns!A?H?T#03e?6JEEu<~)T4q}BqimE)&%(1P=H-Br4Z
zPYX9mO7enJk@F;R^MvyhHX)6iCyAR!2%zEGh!iA|^F(QmoA;ilLY<AlD>`_^g=-R5
zPwy29&eKIlw|`58^HkX@^or~BUZL1aG{()7xOzJ-T+^JV%3h(j?K@NN6^gw?4-wxA
zar0<wj;qI3(g_@*=X^kN-M<>=srzfxhK19(Ic@a2>U|ili`@a>iljJri}h-)Gy=f*
z?#oII-f8*Wwp3Ya5&<`<iW-#RhysjNoTsR_L=~sa@c8zhYpwy#(~OeOSg+-3Ma%ug
z?nW`SNdg>_-`u}RB`cmA0pObA?o>Oh|F>5yU8Njw3vrxy+KKm_{P^NhZ1wOnzlIwO
zaas?a&J|zM8cQ#VK%MinXg}62%fNTg{4v91IRsLC2ViZ|4g$v0X$MF2Vpz6^B{(9f
zXFz)+t#(hq**GN2-vf0V?YpMsF{K_{IAUkDI8RY;iTM#Q&eQyuHMIcerceAa*jwd1
zjcIBn=ZVMxl*z_<R%AFlTYx@ziz38v5{i@mW}TjTLE%V&LpV=k%J8c>C<@Bp00{~-
zr%^#8(7_o}$S_dgfW3(0BypbbeC@JyHICC}nAJH?o7JDA+|5yUqH34pIKkLdtfVgU
zvAP=PN#Zz7+z6xq=c&#w!c(Fyn)4)O^aNv(=SLIgN$TUuah_BhCtW7#7{`ee{#)?!
zyKr!xpcc*(J^1h(C1I-_QY4%a&Xa?t%6ST==Ufq)0(FG*<gzd&ZiEt6<idH1ah$we
zDvnd2CUFx!f%7y)G&hNgi!3j=mT;c3D(8uw{oa%&&Xcs`ekqpH6VzMeJV_j<80YEW
zuIn`CN$(Yky+pxjy0F4|+INxWJZ-=AO=oJ(lin*7dx?V6RN*|uy+VDQCyC=Eah`bQ
z;RFs**CZ9ksc-gLJfg+!F5~7bh8tSdxjFKFfik-vfx=AUbS-d2zM6>hr0WhOU77!}
zm=iG0-*_xW8ul2PH&&l1FkUfnZO<2+rmeeAi?+>`{zj5m{yOm=OZmZl#?HYpdH72+
zR$iHE6Sz*D`DfoXRn1D^YBE0p^Kr$b|3VU5b#3uAJJrOwU$@hGdB*kAv|b0Ej!8QR
z)HzT1T(3Xdw=>EhdvP=?98th`P;s83-V*a8VBC@UF-x^baYul)NjnJGecKL>=%vni
zviGIMvHgepD{Y<50cVrt5vX&XmhW+Odq{Ecz|%2l2La<ewSyyiIZm7>x6lj<zjxiP
z=la&*7x|yu1Lp|}#d!jasls`JLUEozWAgtw(z`UuNa09<17#e#i8A~jQ&5lzGzgUV
z4c^Cb8Wo%*0+i-jjY;Y8jhrXebo&JEP?b~G9ea2Ge$^IQwJ5M#i!Rgp1=DWEcBogW
z3*OKZr_b2>7+33Z94A1L;$wmH)HTs@oEmMb#Z>Z7iE8axIZv(bT}LLAahxjll$<BL
zsB)CC)eb2V&VciTgoB2^O&t~f*-B4EmYmPX6i9*d<Qs&SYWWpx7-qwF<6;AFn*P3w
z<5ZHf(BBl9h{sgjyN=@hoyDz$^W^-uh>`Oo@u4Knlf-e7ekG0*b;6vd%HDMp=Lwvq
zeHG5r(QjzZlis@yd)w)~>#(;SI87DKlis`Tkwe$&z3Z^Ioy2jHI8PGCN#Z<Bfv8g|
zi{sR(<v4D}80Tp*=nc2UaNDfaU7wufl5N(;$|n&3j<5guNxf;>MZj=w2hYR5YWHg!
zNS^ZIEW77fZS=HyeE_?CWt`~M17L|68+J>8M@>`r-B~}dT;D@#4J=Oj-673r@wpfl
zC3c2Ii3L)r*N8n&O04X@F)T_1%G6Unlzt7BHCHqBuXi=i8`zmlAdr)0Z7;>-0Cr>i
zAj2A8&-n|^^ivGy=r@;wvLkGiL_)vRkmh0}Npe1O#n2H|l%}K!O}Q2|FMRbZr!Kgo
ztLXcox(%UD_LaYsRDZ88dA!;7NA7AaJ60v%|9#CPb=|%_uWGjac$L7WzyIswHTq)X
z;(zA8*}T|H+izvxH!O!~>iY&@YqA&u@O4gMyI8NQ*Q)MMP9IvL)cwhIS*&D<Is#5B
zfZ?OpMopzGYAvx80`S?d-^WXJxPp!0BmIYOUcrekIpxKC%a<H<1)A4!wfCOJMR&Rc
ze&oOSGOe-nG6<yh&an6g%OG2A3xC}d*45gUOCeys&na}~D>E$T!)vqJ7XM%~gxV>u
z`|P*V>+1DlzU0Sd&FeVh^S*uNp9y=XYt{B4sg&t@mYxlP)ZQ5u|6n!@XQ_3ZeD-HC
ztx{)H5Ep<B*{39@3=aIt&xa_2&wki;gv#h292}wuKKpRN$KjuL^u!AaM+zKJRDAY1
zldT6csGT2oR8a49$UY=uMixZ&DUo~!pRG=8!xg^oPkKmex{=<(eMq)+g7Ay4#~Rqu
z0q5wv%Rc*E-G?LvulCt*bSMu#`_d1dA`m>KMBuaEv=51XezfYdU)v9aY;nOJ_Su(x
zNU|JSSUoD}1PN2fIpLteV^#JciBn^e7tgbx;vBWm(#glo60tDHGFAW@kichO?Nj2F
z&F9K~B3!NNvmf^%@jm+-Vv6|e$Nf#<v%lvlS*CsV<31!|pOS;S4xe1{+28lr_1b42
zKKT!vQ~K<~Ctv&Q-@5nEN3_rWQS!;xKKt;=-=%%_xBGoaWS<h*hvb~FPYLD=A9&fP
zq#35}l$g(cch+L7EvfIPp~tiRG&CBsr>FVs>-US<ds@AkwS7pOMxf5e(PfsN4FO<i
zT#?zZTC|p7yeM+Bw=>SuY*?i@P2iZA%#T2wn=^k8tJ~svf6+X5yC0jeNtJ+ylfpIC
z*2<~~*ghmxJeJL=eMlVjg(C{MB_{14U_706a6~VLrD53~0`2yc;*WttqQ$;*(r6^p
zPL~45+CC+^*wS+#aMS(GmFxFwb4@ErApjmu3g=W?E2|=4`;b)eST>j9kAaiZHJRKe
zBkV&`c+M03a6T@%Mfl;I{)rI<I8VfD5{i@m$(`PXML}hbC`uL16Dc(3iH2c?aGpj5
zWfkWML;0Wj{XQjeACh1f6-Ma?zR_IfJe9fbr0Sd}e6H%sXRFVYaYP-Ng(C`hMO_u+
zJhi(rvvQvFJ|uX0LF!+_%)@!|Y$D&!#QBo-ZCPz^6shyz!7O{=r#wZ8pNa)az&&EC
z9C9Q~Myhb0c)(GCLXt3roD+@|1sy5Q6JEEu<~$Xo@WUV>0?w0TyMhLsrvuNC;_@o{
ziHIgII2AchvJXiXI8UBTMehh}{>3T#kOcbGn(RZO`sIB{g!2Sm(LvgWMD{7U@bSGj
zYR=O|N4I~=LCtwOa?Yii^K|&gxhH7O(_=@@*;e5^?YMAFbDj?Fy67~`d6IodWS<h*
zheY-%5gcTn63KV{+854~yzhWxa>Fybj%xSp18yHVqkDGs-J)rnr@qhWSlAD)NQ#4Z
zENmG17<E1lo}uy_9s1n2Xnv0R#SsM<t2j?lZ;AO3NOAMPc``{O01iot^OSCFrA-JJ
z=cx&qwBB$_<1<I8({;hqIh^2<>AIFqBT(l&rE6Ph3IT9OERItOq4~;Ed<Wx?&4*>G
z_B76u{g0GFtho$WzT@KNax0k~0dPc8&w$x`vYIIbfU|K(QV7jfR>#r4YnlzWO=>wR
z#}TC#=PBwfF+T#vd72-yrWWAbq&QDa?T(io_EtGh_({FwJP|p7GMe*5A8tsI<ypZ;
zh~p#_C;!blJ@taZkphQsp2n2nS8`Akl)-`D;6Za571TQ&oFRn_<A3TOXRudup74C_
zvVc2uQwQTXZH8H$^R!w0V^!YeI8MOe!+7~LNSFCoU5)ef>Hi$TbTJhY;5^m&MbqHd
zoG0mno?tBU{Al7lNqt;7&J%H(Qk*AnnyNOH@sz-MBB{nx%AsPb9a1Em5zdo?rpkE=
zrsrG{nF4hr&Xbd$HcKlp$6Pp1wfIshj#Ho}p))VwJWY`pkI9$O+d#o7;XGwk&J#WR
zy(vwcCuzt160hh9>Me4fh*$K4#8NuC{noGVJGkpQ&3W2;=!)w!=jo9{yDqx0!g<<v
zk>)&Yzx7RLYR=O+x9vOgu;M&P9H+>63UQoh?AL+wBypT1&XdQ$pTQyOnxr^FeX|!F
z6O;K7FmBHLm`RH|H%HztP;U35pfukVT#?tjZ@xBGdp-o}oTvF(TWvug#m520Cd(mU
zah#UJ53P;!v^a(bUmM%Hm<kEtYBE0p#(A0_Gii~E;{=|LNjnJCIZyapuRq(jGs+-)
zaWpF&QNVXlah{^y67wT4jfXRTFV;d3NO4DiwMjb&*nQg$j_9S%d9wGV#j&l$adNsR
z;B2xy0(H*Q@;$C@4=D~FcseHSAYh!Qc5p;5z2ZC-<=%C$9sDBU7LBNk6^io&8WZ!K
zGWxKH%1|iI6KG8SKgTuCc_M`)1rC%+94G#dDJU=u4j*^K$8j1Jlw|^x=30$O>G6%6
zC)RZP1ny9kQ`Q}O>wCb_szrg_T6CG#Z*kgD|2U$6H>Bb`MST|%U5?`fd{TTYaGts*
zI*wDLZMB$6{wYzdJuBy_)xGP;gtY>8l$<BzNJ`EVUQ{_$Y_&s*gfrkgA>p8joF{%2
zj-Uz+@g%02B;Y*x23#pLLJ2*hx%LKi<8*u}aGI{WimTu>VQ4G~iHUej)xGN|-rreV
zQ#enKM=m)}630p6JV_iU=~v=7Q76oKs_b1yah~+vbw18hxpy7nJn6mb5a&tnU57YN
zdha@p^Q8B#qrL4Uj+4ZBk~mHh=Sku?Nt~xTK3&WAC61He1`bJzqb2q1Iv)bYd72L|
zscpCk6762^`lQ8qY6DT=`1+r3qbKVlg@EClLTC1}!@p|x>+EPX*F5FLS$5B}n#--E
z83ACouZ$DjT+vD<5HRc}Ael>%y6^BFW3oH~_Fla_hSEdov!&gyg3@x=Q~uUI6D^A1
zPm?eC^S-cX>lJ86U;F~2Hy>1U&10HV_{unZ<%|S=uM1M9{P)jL7dWwu_?u@=t`}ZK
z=QaP0FY@u*<QzFKelVnI-<Tjy5}EU^vB<|%Q4XV0MQlUAD~iNaUK&vjNZ*bJaePGy
zwV=A|jM0nEB*hx?bY(444(VVlOm_H+ePch)bPxu>%VS1ok4fRp#}pVD%2VnRn9nAz
ztzR5UFqr?#xs1*<0G%-?1{nJRgBFAGfRrcM0A94e4lN4Kj2R6$LY}gG4g(gPN4LNW
z2dDfZ&^gTeyth+58Wd)D6Oi|U`)Ji=;<ZHH?d!CFjB-Y)oDs^iZNL{u?k5G7ktD}r
zLLA*Gj&-9AS|}`?UrbJoGTbRxKw83ee+MB|(1KEzbf1(1=3ziGgUYycKMmuTRSigH
z_yMyGx>Njs{A%;VTta5>9fSdC7)U{8AV;!J^Yba07b$t(GOu7pj@rQJy;mberEC(?
zf)S;1WLa{YxsPzBtbZ+`fJ}}OOcvvy7mO&`r{@nN0*vnYu{b-vSA5Q+!RcJe9VfUX
z;!xtGa0p9>>IJvqQ&>7mmnpeh2>v|QjHz(1pr9O3Er-8XP+Z`|;-5L3tPB&1r?3C*
z=T+CATH>`t82M*1-7COGjy3;EA|!I^mJY{8!CV}qhq-ivJAWVHwvK-&EBIcaGaFub
zqhPLoolz>M3|>k8k8;3=4(RD{JkZ2|q(vFulr#+R@vpOjbOrtSXL8|RM}9yy!OxB7
z%=6BvzCU=*xKBQEI~hQKI0r#}FS#VB)tc0Z_1Gj|!^MhfNr4uNx`)(jiSUsMQw9W1
zLCSl`iHe4fX2fBDkI2+}C=OHJsywgIC=QtA(oL5A-OJ^*6bCE|S0IJ?-~2CEV4@9E
zT<!Vir|o%Hx&H1g*Njeh!FzvX<My?iKbpPGt$(U0Ug6%p{*2N7r+n&+jVr%(?UeIg
zdFlmg#iduCv-XS=K6d-I?4M?D+jjf-m6wm7S6uq9M=yBKWoJ;^w`9NJUU1TRPrcN=
z{p4qyu>bj=+Ss_#eKa4va(!d1c*T`xtvzG3^VCmWUS!|8?e>#i`HAti;?j4%jrx{x
zUobxJwA-JToh{>vT}4<!*!;hIA7%IjkLS!Ny!6)`s^mD4#3zS;!te)fQWx>TR-jhs
zhH8T{NP>rVj)cPrlJhxsIHC_kBpWhr5sLr)mqQ}hwe5n@j}#6zxePXc_xQc*XRK#W
zyMO&Ew|3G`pK{Iq3r@^VSbOir8Eg0F_ZQjvTk~w=nk&brjZXNLQ^)5O>(`%l`$?mB
zk1n_*dx^U~yXK5-*#-9(WakUd8?9fE{qX3!_n$RBWBtng_g}tt!rEJ&b;&jV>1o$z
zC%ogW8|&FM`NrA{*Wa35uu+_L{b{4~MyI|flX1na!_UaFUwgc?D_C!rIS~MkPyXRK
z8?9h<!>OG`N30CH-<HSH;*l(mVX6m<o0CGPoif9?9UN1=?0Hp|rJfb3wp&^D_kZ2o
zJAP|7SquT=DJ+H?S{ZhWV~1yXisP|(&(=~9sJ~yXQ2`E<g%NPn5=RtZZ2Ol+I2KN%
zK64<}pGg`4i{+QbXVFrNNw*ksb=>TIXE7Y>tq_0iZ(ml|T7D4(>aqM5>BHK11Q5r|
z_AhPkZm{@s?O~bf$>PtY(3!8yu$&LCRPA~!zf@f-TO0w4LAN+|x@8?l`>si&vvAr`
zOB_*b|I!G>(g};@w={&YgI>k*Bdhzqe`y51qlqrZ@=HNx`<JHBX)a5}%j?_zrCs>0
z@`vt@Si6`C3B>xV?iDKj4Aq*m#`3GSn#|e$rHqN~U%Kn?$+my#<m;miO)8e3?H9Qi
z!WNTmG2GC~_Agx=JJr&ubOx@-S8e}N4N2?iI_IhN0am2L6dwl|n=FR_I87;xm+O5s
zS{vtS@pVq^7YSTV=0~8;d78h6)oqcwA8r5A_U?;1=gEGjn;Bb2HE~1%-@*1Tjc_cL
zFz(1w@J%!}{@4U0TcWW0wmn$uoTo1Q4%6Q3j%`o2f9claUFSS){fNUI;imhW=Vtqt
zHe)kyiE*ChMXb4guQ*SI?O)owlI@gqne$}(m$tLU(u?h1DoC_*1*hqCoB1``{-s#~
zxNZMZ+rPB-va|h5Yk;h1);Ld#Exh5j7;c-j0#~HYCEKixl}{p&;))m_XA-X&G)~t6
zhHoqPm8+ELdX`=s0pmO^j-9kL&XXW9-_^J|^WimXZNqg|q-xxef0Jd0|6=C0R&f&q
zQn81OKeh>Ya}<N`kivS7u2#OPaYx#_1q{pfutZPBA8QxSrrzqDr>1(QPa|MloHRad
zl^V_qBk6QY@Nj--XVg^6qSg{KBk=CeH&-?OSTi>Bmh^@5G$Ote{aEfK&Qneq96nOY
z82cQ0#VEsGiQ^4Y;P4x-j<ElsSJ1|Xv}pouy0}3<yJMHdHGc$!BLxopD33iA$CTm!
z^f`n5mK_ZQC5=hPsGt$(SPSEd8Cek6d-QzCb@J-8Rp31R#T{DHjdWMzIBkXwctv%t
z)@E&vRe6^=PkTO`WvLic#|oo)#?hRou&L{0^T2tM0z5?^^n{9nI8Vj;w*66|5_npP
za2zMeG+i%Q-zIy>)@^$5V3s}bQ`8VPja)_#Hj-G26fEm#zm7r-p3}k4zEOb`Nti;;
z2?vdDkoyKQHE#vxS<pd+*t9mw9QR6zIBryMi)a@Ov^&e5`W&h{n~X<e?z4>ZG#cj^
zJukR}jcn~KpU7e3hM2O(6Q+uVb6if{tnYbBmc8exK8t=2UUA{t=eOVb^?i>Wd4ja3
z9;8@G51ez`*WYw_#}nrqedNgp_dRy~1LxlQjeQ4qU3cN*dvAQ#n-2f02hKVAjlGAi
zxbC8(+rQ<ueFy(&$Aypo-6Mx~U3B4*b1uDg@1c+Ey6EWN?LD;bqQghdJ>lphhpxTi
z!Xwvhzx7RLK6d1sZIACgbj_~AN8WtSZTrqVyyL>PquXzN9gTh6xwr0p^1)pfohEUd
zF!mv`4VHpK^lkq*%MOukY<b5|#(C=a0<~yfibDeKj>-H880Tqz%%sI-r%H;iPUnn|
zqtRF_4GdG9r^R};RvH1rSfjBuY2!T2hU*``xw#%VCMNSEVBDPfF_RXlctmzT3QF@`
z!NW=6I$v+AUEAU~wY&Z*j+3LFaYO;P#H1YrjHlBMj_Ad(G%VXgpxvHQ{4sDywD6bD
zT4Cv#5CD$%?w_fuRoVoBRQ#d({kln4R@{I9csMDX8=9HgBj7X;!1B8ioF`q^(wifY
z;*Wuo(>3|y=SGX1PcgU1WrgQF(J$2W<2C(uO-K0sJ>v`%;2sgDNhnU9O+fF$qM$PB
zbgja9A_e{A&Lk+5(J-tK&eN!%tl~VC<9f~$I8B=KM75)I5#OIlaGJm^>Y~&+PxxGg
zqYLtx+oBbYQaGY?d4D+LJjG>dB{3`KN$*`Z4kM3h7R<wW@@%472a+YuQ++=@DH6_;
zaEs`{M*^M@Tjh`=Vd7AQ^W+;8TpB9l0gP6Tj)D$qm4{bon3}f|8N6<(u;e@yr0~Na
zA>ye=cv=Sm=jrdSl3aNeZjxy7f>V+6w85Mv(gn^_;50?f6F5zp^EAPgB2JU$JTa$9
zah||w(wrx7nkt+p;xuW_6F5zp^8`*)h4TbXlj1yq)1*01;52E@6F5!8d3qi3t*(P@
zf&(~2&-sAlI(c>4D%iXBOs(m58XS|<-ge!#{`gr3-1fdDj_+d15=$XqoTtU$16L%)
z!CS0XYo!sW^KtMQ0EfxK2smnqBMLBn^xBxU#DWN<xOw0_nWPZ_ha|;$O1HMsCIpQ0
z)Pzi0U&qbfchY#xS_+=d-)<Jyde+WXyk4F2wBm3qHGObLERNGs5LOzWePSi+bk6u=
z8ja=B#(7#8KUZ%FEKmHky4LcGAOMa?iu1HcpVnp)0pM&Ll1W_V)zopc@0#XCaB6)=
zS{zZp(>e6Tn6<<b2ms3zPiKj)SFR~IH+{kq_EtGL_$9sMJTa%K!g-<(H>Au!M8Xl`
zI0?ncf3r?cy`XTUz#*KcF=hCb925m*aNsw1(40mE^-c$8NFl@cpZdoc?A4qnJYTyk
z;11pNP?s&7Zd;x6G`-fb*LFFM6VSLAFP~Cenar{-^Rc=b=jqe`IU-oW5?XMc>inWA
z{HT>>n)Bo}`~>5qJU^N^Pf{OOj`O7AIO#G;$2d-;VDeHpqa2(kl9F3gP%fu~9(E)S
zClbyG=gC1+<vfj`LPJzUrl5m{$@$sq=!wkYIZsGJkqhT3#&Po2sW?u7nuHc!z<HV?
zF&>jID<qDSaGtU%=ZT*E-jpWJleFW0C61GDo+OS_;2nKk;y4NCN#ZyO=Sku?m7FIZ
z$4NL(630n6Pce>D;5<njr^tB<ah!zn^k<*;ahxR1lg0-eqOM7bBh)v0!7(wJ9|7a$
z%#WG0sB?3|!<CEeeiW4EyMin7n)l7u#%j-pK%Mh6Uu&x^2&DKpz}RGN1e|UGPSbNP
z(;7?9i-2*S=0&WmfAF<2?P4k<fUC*;2-G=G^Y^g2EmCouz|%2l2Z1{037_lrXZv<W
z8DuYxW`!dP_zo)0Q`B2xeguq%Ge2gj7Afusur_H20lRP8!4bXGIZyV!v^ch@I8MOX
zWO)SYoTue`T-_d096a!JOcqAK>6RAfNu#k`y5pRu%DQKTkK-h9p1>~>ZqbO!GAPs@
za-cE!U)kxyBFdmpoF~wj{C|#Xp7TTsM+zJ$lQ>TNA5&0Z7#yA<Q0`sFl`CAUG1Vd7
zz+uICVokSC;0{$eW!<s2z6TtwS`^r=MVD#)7N;Hck0T0rLn_Ww)OR7#<v32j=fnOb
zG!-gvp1LMFj#Hy;VedN6;0c7GTIE?ePp$4<M>dpkoGJ#DoF}}fa+LAHIHX881I`l?
z4w}e$;#c7as?d-g&l%Mu0q4m#;7XwpO6U>IwKse>E;gveaS{m8WU5TWW2)|5NAdp7
z;&#G$ay)X$d6M{066Z<pT}KTIy>}frPnEsvDAtnRyUuf-%DwBrdD45=f%ByIt^?;u
z?_I~7C%tzaah~+vb>KWn94CqMBypT1&eK$oj<3?`;Vq7nMq_2tm3siQ1~*5=d0H7D
zmYt|^#g;{IdV6q1>RhtvHBFmBpw7n$Z~WY(&d1SZsXkY{%<1_9LlwuVQl{%!dT|86
zd8*&Xi}$vgEsgWE*t#1xXEEG1YgNb9-g`Df%$Hjnr`d3twN@(jknzW6MRD_b;5($S
z-n@sEuHp3Tfn_bulP<RO90(W>XAZDtsH);Pxq5YAZPE?`b<R^ey{=v_#>F`{YhK40
zpZD!E|4i6BU8@$ysZyrvS$Z}EQn81OKQ<eNv()N1=P6EMRM5}qbiiJ4a&pSx@ISfJ
zkLRKYoToC56F%I~A&S6x0)+{Of7;O#FDM)-a6nPvJaHyl4`xt1{9s>lp7h>z-YzO8
z5zdp(b^qDg)i_UGjpHQi+H~z$oF}L4gl)ArPrCTHrn?%)NrB>2nv>u>Nt~xfLQdd3
zNn1QcAb3iNfb-N8$B7<HQCj6Z)#549ATA8VoF|FnM9*0gSUoD}1PN2fIpLteV^!if
z#i=oaiRW2RagJJO>F}(Dl!%F<%6X!Jc4wK2^W>W~pDXd0xLTF-6yrE~&eMjNB5|H#
zd?;|9B#smH!~MoMPLCaVf^?@!94CqMBypT1&Qlr3>5A*Hx1Gdsk~mKi$7$~&ALmK$
zU5CBxVjQR2_MLecd)sZl^>v!_BypUucO7iQe8C}-I8VrTU0`o2&QsUy2gjsO_I3%s
z6o<s(5iPb-(>PDzS-Mz<E7U3#$EnW8Ss_?jn<_9gu1ITePVLAro(jvdN~b%pI8Pdl
z=5%WBI&e%(HbubIYXCPD=c!(7`2+%~ctmzTCV)#6frpdAHPO_HY6w^yry3wjW>p*~
zM_u8FVtj`P#nK7m=`0Ol?7*;$P%ND=ESH9`(m^Wz7&s(a>^moo#_Va}n2Pf>drwv~
z6@RFHzZzPLApjmu3g^XoU71!+&(z{LX*8Bkr}$&w<aA9WjuYACylv&)b!_iMJf%^U
z^F+KRp*Z=U-059d6jVl?#=Yy9g@jQQ=c(XfOU~1%pmN1|@|>nID^aHRuG4%cs=%Bl
zT)QNxI8OC=NnNqK&UwP;s;+#tQgNIdnS~<?ctu^6F2{N50q1FAS#_MJlEG7}Mw}-d
z#|cjn2tC0nG7sm;vxzFr%M9&pSKm)h3bA(`_O=slQ5olnt#Y9rPo=_n@(qem9;Q%o
zp12^vdBW>9*PN%&fYe&b_)<Yzi}MugN<1b}<OQc9=Sku?Wr6dw$=-Eq6Y-&l)1*01
z;1wMtUXjFky72M6H)_rkI87DK(~)y7)tslpN6tM#bDqFys&JmbX$pJSVQ;&GyDmCS
zbDkuQlW?9Sj+4ZB5*#GXljJ*ib=oG2^Q6%jZW`Pi700P^4-9wKTR*dDoTsfHwf`gB
z^=%f%=~%2Ha6a<i%aOYD8NRft`zhe~*md2vv+oxEi=V09uYI4-R@wi^k>;LHIj6bI
zO40}byKUb{*Rj&+2pD$LahXMX{#)$6n+2y?>-=9&ZmtQeP1-@={FAawW8IbShufLm
zvF!y|e&3%Q+cAea8nC?fbJf||y;;R$p4|U-sJS+<HfaZe^Itf5-?r29>h%IFfAE)9
zZ{Axm<2si1J<@V0?|E)>`;UFJxy(wYBk-?|PS-<gcs66xRFcB;!M8WHI)3_p`R5a3
zkL34#*qe{DJljuo9DYdOprZBo2+OIMv>VW7m(Wqr&+pVA^9|_AKi9A0M|p0wEq3Fm
z0UfcySXzZ{3TjZ$fA+Bfb-{MM@i$nT(=gsHDiG-jzG80nv^T_L=Mu1O*XuiH78~@m
zd#kqLhU|*Kwr{z%E7nZf@pHdW)oJYZe70KFh1`QL&9cAyVPy$8LJcB3rZELr%EH84
zL*0yGHQ})ZLDd2YlAO=sw7zYBwtoYUqzPeK5ovi$Wz(Juv+T>Ss8r99;}afo7_^|n
zx1^yRGTa?b+#d|e>BuG<kkX-KKTgzOlxR>;m7ETAgW!1Kag0P90h#gNWZ9GccS;n<
z%^>R=IV^J-MbCqbJxht6=;)V>qR2}mdEs!O(MG7AZID8@qi%|uzdg(T>TM_`A;s(e
z;?S;JE<AG1T|`2n&FGHq`KO2Wy`M-(cm3wRgF9)nxjkp!`lj~~3F$-c+IwgxZ8mrH
zxwq|m4+U1b>+_EsdO2-2_oL_By7%rwyDqxx8+#A!-gTJrM<2P92vGM>;HBNKe(cES
zhyZmb5unbez)PR~<-<E}Ap+Ewi2!x}k#ld|^Xh|f?4LctV_)$BH8yPXhGyBG|C(j@
z{}0J^=lZHYXto75cTIlfy;+vBxoh_J#U9}L{NL@1wcWAPaNC--01w3O$K|oD^OBbD
z(R!GMKpkiQ!Dd=b)1?pqFX{iiJ5|HVHbVgXkUDS4?#Ing^X1<p`AhZxBl7de*XSP>
zU4OPwTdh@W(py`%g4<*q|G(ZQmF6$rY}lE5EH<e*6(_9kPoKR>ODpaz0$ATyp4eOS
z&G1bSsIM<x<WpbhoAhJF-9!NE`>i*0(>Akec?9aO-{pI>9=e2pt#6lBqkUU!ecQ*h
zOFi29c4;-*x5d`CeN4O5qpfe3R-=7e>g#L&`?inq@$3=n`-2}lo)*~HTZusZ^-E*9
zC0@f0?dfO|*Hkd4e%fyV({!74yTnwdc3n)>&aPaxy^Iw5!TLV&4pHkXsxVD1D3M-c
zBA|n2Owi<EF{uxvHNZ#<2T`Ydx>mEG%0b2jcjdn%r6F_ZX((k%Y>Z*6lE*UNl4?XF
zDDBFw3QEIZ%&MS+jgNI%!^8U0NgU9GCEy@g!2w-4I$)5bGcqA9(SXp3TF1Flx*&Bh
zCE`RXbeq!=43-=;8P@kZt2{u*1&f`~7Dtn~rh<X!izVl=Y<n3#_VcyNXzhPd)Q#6z
zzp+NTVA=NR-pf*qgJTxKE2Az2DR4AN(Nxe?J=XWX?<lRqq^C{1tYN7>A@H^Tlx6=z
z_~m^v+-#i*0j%$<PM@i&Rq7!EU)yi%+rwp>+2pTn&$64Jp{wiv1)#6J8|S+2yr2Jd
zTm8QP^z`{3BEuJ)<I|YVIZ`!Kpb8~E$!FA7;#3+*3{x8#-D22+j%F!pMPjI^y>SlN
zXt0z`9X1r!j1e59X(0)J&2bTfy(*q-GiUwR-jikDei4#6=SzS?whpRP3&jGLLw?!-
zq2A=BVO|1TQMQP1c?in_PUW?H#fTzvwPG<?sRgb==_Zr)QZZC&dgC0j(O@Y%j_bQO
z%U*mY?8t*L)9nt0WwoFXxE%5oXhVg@%Q0EsY~|PYX<7E@^RNiHUx^=}MY@u(FX(XB
zX5a4e>_3w8|Dz{fk`>QAHOroX@-wLX4BEV8TlO?6|99D?#KF8YE1o^h+?iDV^HhEf
z%JXbY$8)Isjcb=?pL&umr~8P?PIMP!&*k!qefhVaMD3|8NBITWiT7WSJv+NNd-)ob
zpK?-m`_rlXhp6m4I;d>z{*CNORQ^+R{Lc}}>5kLoG><1`*HZblzWj75|6ZEMd2~?Q
zH7Y-a=J`@O-cJz-9zAj7=lKIv9&i{@+0$vRe?ZU9h(pB5<M4Ev%O4O<f<we9;BY#X
z-<`xEui_v$3Jw9Mm#?ic4o+|iICz}aXr5~U2aglJzk2?Ep+`F7v__>SLqY)SYrh{2
zX+^7Z!TQ$u?erRU)mmGgv&TmK2cli9vA%cjZ@13{db9Q2!u5UQKd7vTtK=-xYXrXb
z^(^}rU+VP~%=iQXSl_o_pQvC(y+**+x7W+Jsqq)OrC-1J3JZsbPK$2UuJq;5*2sa&
zEB(@^<5IrunlfEW*&0;=*|PNs!&KI#I`s4$*6#Pde|ni|yNv+W?t?#6wbA}ztm4tt
z+&#C`*WLdtTIVEX>nBL`?i$xnTaI<UBC)rRu50P;BJdnC?Lg68`^>WW5IFrUllA4<
zi?ufC9Rf~Utk?3fFX$3W_Z0!WF2h>7zRtny_6XebsVtlJ3^sg*g#gxh+tY_Nr&XMd
zt>bE}`g1O@*XvML8f*EaTZb~6)t<)}{{2d=<r?PuTb1w4z>%f@>PFcZ$9hhin9)&W
zF2h0Ebw08Ux=}Wu!PYz60F6djo;`(*4b^~&@9R_<2UX@{jjH0<pdHod*iOCYbdZL}
z^?nrVJSMvGP8l=|H9!=Blc_T7@;^<EqFpp@2CWmj!nk4==6lIaRELJ4!_kQaJr7a7
z^L1JFyI<v*xgpMPd~NfrF!!N}+^1j3>F!O;y+`wQ+EzWk$IsOzy-io<C$qTv{wy2F
z{A5ae{p8)1EFQDY1=SB0NEGz2Cf}88jh_0**My5QF2WO<pXAvFC8-&`MacaTTWye*
zi=yWpRmrKC_Gokd-67URBBvwRgm*A6rA>ZJ(bJX2^yd1ezQobR+Z4?8YIXj?fh>Ff
z`=KCnGJ2;96Tp}b7GR*94i?8}ng+%rL5i&_Vm0oDEkOl`6Nv=Wp~}9dua=DpD&%f(
z^__C695>n(M|0eXAJ<nVjf`7B!xkd37VScg<ZD-E*&8cy=z)wDbi{_|r46h?SJ4Kp
z!D>0NJ(3AERkl!RO6JIVn+qhBtn)yn!W$Ixc})34tnE1O&sYHdh@lKFLE(x8pUcy9
z9AbGMQ=E{McbG~vfs3lSjA~S*0VjNfg7`C1j6;r;M<9vA!T0aJGrRKq54@YYzwzT)
zcJTc_ap%21dj2i@UUbJBcHH&Fod<7z=<a)8|7_%UUw+qvuQ_=0&aZC2>b_f^crEgK
zUPbvkwqJGU7x(?_2X{Yo&z|!Seu483zWUi8_=$(V_R{n3{mg6b*#6^p?%8qvEf0P3
zeQ$X7y+8V@4{kqtH}X3le(&!4zWHP4e_;ELufBB0hd9q;zgos7+i2|5DZhIM#wOcn
z?9;zVWAEUxANpPz`zK#bV?T_sZ{GQ8%I}e}DS!4C{yfWmgZA9U*su+-3|TPW{U4p2
zVeKZEtk6@<x6#Y*u7A$PyPi&ArOp2QyC$bE_bS%br1J<kZJ}Pf6MkHmSh_C=z-J(=
zo$HIuX6Nh(m`}*;SoN`{t#2P!ZFZY4bW8jE%s!aaTnYjB7JTR>OLbw5k0SzgzYuK-
z*4Ct-2w?3}YunFRt%lX`1+ldo##$dJn&*LaHt9bC(|ms9d!qi&Znb8Bwfw~A;+&nN
zY&`{ueqB?3Am+c-ueD5Bi?uXAkrYDxDQoiiv1f39)=(^c;$@t2lGj(Pvq}FEFrT0P
zuc6Ffnh%~lci|^u(mMp)G>fs8U-_eHC8p~e0xRY7L;f|G?`<#lt5h(L6i+BR;Cn;7
zW9{?9%v|mBLk%2N#=&LeUn9OXM2vN$B?>EbgM-R)5KpNxA6y0oZRzt9$K|otdF+BJ
z<KQxkO%257hqQiNKg@dYHOj&;R5s>uF*fXiV7{Mw5mHpP0s_AmS>K^e7jvuoz0jf$
zMt<qWI29LDA@P;GuIXR?9^#NU$x!Df_a}UQh9>ao`MJG3E63-Y&dTS9b;{>w;t5>P
zLmE6@0trpMIJz|W*KiR%?MM8`_tj(T@%jd7s7OihGitCYr<zrpxZ`M3*^#5<#uz?5
z!Q4<(ge$$z9H3;5EKSDy{ID&s$zd2jP(fJ|$7kv+cxb?C)KtDT=%z%)A*VW|%DzJ$
zjY<kCmT?6gC*$TQLrsT7>_(*u=yRNWhiuoQWlRzF`H^B=;qy}!AfrXxlc-ymn#VFW
zyj&+23w(lcP`a`vD~qxycI$0cC0u9Hpt32Y@=A{J^g}x?ptJ8*`TY16%?5FKV%TV~
z?+9mEc{kOdvYxD6shNV4#-WHcOP?RFLM@g*ekCrs;|!fHC!d}}%IAlDdX&$P_vtBp
ze%Pl+`TW4ANBjJUUk&-)c%L8g>Crwv<l{p=J*CeN{Ef8FkN6u!pP!o_`reAq5Bv0J
zpP!v)SA2fH!1?I&gL%RS=6C3Qh-~|}$PZnbe13*HZ}^2w^KlyLe1|kItlc!9pCQe0
z$a6`po%w6^cje(TkXqaR&de+a0(GAdd_asJ5)GohA>hbh98s{opMGo1T4G=bn9omt
z78Je(=JV5^_0pD_Ux-Gdf9aH82-eo5HwZXw={>h+*$ZlWH0g3n_X7c}W6I~JAG0tk
zH$$NA^JD*OZiZNQ%dwXGf4aN&nPsyhFwGCdUYoPy*R`6j{mEvFu+}ESK%mLzXBe|v
zomrSK$ZD*0eVy(1mfozp)0V;y<mvB@no3#JTB0`yr1tSK|E=CE<EDnLjL%QlPe*)y
z3i??XhyQgS?>gX+mOek8jY^Ev;Pb;iJ=B0&c%PrzemX=F@cZ~s12l^J_)r5LhS}0Y
z>IyzTaok|n$$9hsLSPTaahWAs*<UE5iIDhlX&Ar15L6_k&yUX!@a*)Q;1~0q!KX{>
zhmfA;^D~5bVGi(l(f&+B`>qA^yW$m?=`aO8J$0X^p{-$k<>2%4&*N`x?fTbH*ZhuA
zV(9nrp{IMnZvmw-R3+!P7`%hgJ5~^SuaUil$md72{#xL@idy-14X^WlM$~)G1AApS
zJND^G`TX$PPmb!;@id<wGMuEqiQf>p8jVySAFWpV>EQh=M<K)&IHMZ6alSLCd^ad5
z$Hg$d8d+8C22K2Eg`~V)v0AVTK0Vs!$FBz3h@hg9T%{>lnwsToLs^WWlsJ_}lI>AC
z^hC1c{xy1~xj)C}@+1ZW-5?%{;PWF&wOC$NlqH<PeW%6a<gl0#WG-hMrVJYzH{c*$
z7n1PT92akJfuxeD`yI(XJ}?Us{c3{GPu#~R`23Xn_ynIH*~cgN{HVQjc%L8H$4B=0
zk$rrk&rjUPC;0qe4<YUI6ZY}J9z)(X>>*V8{FM9nc%Pr(Zxnrg>i$MNNjkv?=EIjt
zZunR8`5FEi4`qht^V8pzw6*K++QIUaPY-+sO!|$$+pll7-`2Moo4%CHv%dH@!K7aZ
zeE7x9_QL1Kq#p>tx1jFxW3R_fuAQq}g|++Me^%F8z7Ggs?NUBJeVD^4+n8EA_==eH
zAA!2h58fB;y|JI``reO6yB(!)L@~a3grfI}X?`NTpVW#@z}9j&3vX*VoVCPEQhPGN
zhd_&cX3}VMI_<P|SjW$QLTfDDR|KZ*{~~j#zg|Ue*M1=YKakWq_iHw*Z7tR^<@2-J
z==5*)skMYp$k1eRpBMTRsC<5~mrp@o!{Fd=)xv%{;M<~%wA_H{tyC8F)8PibYzz)A
z`_}M&I=-9e^D`#Do{G;;*vE%?!&DZ>^}~#1A0M$x#?8d8B7>z(`wOXke1ctBDXX!*
z<$U26GgPVj{NR6^p8kL1$aEZ0;1hH8T`@bj1m;)wi5b!)r}_L0X?}VxE@a^I^U1rB
zY1h9dBS#48+V_g?vz!j)^8-~WYxF+h9OXCYpr#}RU6f6%QztG8y|UWTx%By&_DsP(
zKH~F3edoSTA+42f4N4sAVGC^XR&lC8F2@Pg;yyp|S-?I&l%vXHs*uycGZ_^~#11(J
z4R@nD%%PKN4xOMI0))>pOdMBg^8P|DM<v)r0-v7;%YDa4Gu@YkE0?Bn7ANW1$s}S)
zuqfuKMnybgrHXojO(~xrUpZJVEpthPs|O+~T}*j!#NbRol3~LVmeo;HNukn6PU3_a
zIp9#mi47_{qZ$>Nf`cwE%1rE5<5U(;8g%9PAJ9HO@T(yopEqEiANbwSUOLF{mVJJ<
zUv=Lt+UJM%()r@PiqB8j$4B=0`SCmVRD6Dp-i`cD+SkYL^RwftFWsShezd<4_W7aw
z?j6eK=bNuZUitjc*xKhu`5Up%&$}PyeSDrx{zk~}DWUK_KRQ2zbZTE4`1}k_QuDR_
zMEbkh<~L$%*IxwsYxzCjllJ-P@660{jR4m9o<G$ZOZO20TgN`G+Wa<u_DAgXIzMX1
zuf^XGU*oV5T94lXEIBgP@0Z@bWGB}AxFKNccif<FW#Bh{zrFri0dkX0KJxp`6|e>-
zTZ;fNPOZV#j&8jJ0b7IPe;?Qy9Gf*rJ!|ZFzx8Wi_xaXiyx9mJrO!O6*TH7(t-M_X
zupTeJxZOUjx5W|ocjr~s!x3A>3z18F@^a8uh^|7horO^Xz6r~SIJ{J?2wA%LB&s^E
z6gms_Konrojn^oN;(~cGq;Yh3p)runLzXT+DK?No+2F@0ZTMer@a+n|$iQCr{73!O
z&YL5!?{~878&_^#uj@7b<ZqiT#2ouBSHCjLQgiJ4{HEEDIY0CCX(hwe;rq>1oAZ!X
z)4reX_iEbu^?Usg+tz;H>-QR_tjGH5*tcs`8HY(P5pZNRjwo2)Pro&0Eio_z5W85v
zeg`(aK~3k|u9=KoJg5l{crsYKR1DPtPkj(mORXK&R*QZ9(P(ro?X*RRdHcXgT4U)x
zB2bTA+{ZbX&6^_ts`r6n^LkdJ`v_Q!)b6j*tQOi@&Wcn&>ZRh{n!8Ou)^HXp5eqf7
z*0c0sb&fv*SVxP6di>X6t1YOnv;E$()rhy&ztcS--tE)h9W|A*sI^3I5J<(l#af#T
z0|CUgO|A7XW=XS9v5OJgxM0$-qXK!y*`TzKU5psQKKkGY(GS;gY=j2X!p9I+v5OJg
zn7WCvi_xeOyO<hzvhg|-ml4}IjvMScnZ}gZ#TW`>@<BEswlQhS*u^vyVkU=}${DOh
z13rRX&_J-hpL>x{<BZu3SrFeh|JX2RSdU#iq*;C?r@QysA<d{d7tGIM7gsUqS<cn%
zMeO2NpDSAOH_0g-;s}eD9?tY8vL1>`Ex*4Mq^7ro>O<L)Vq;v;xmu)R7gLW)*64|c
z_Xm2H@b6l_j9W*WyiU$!6Swm38eUt*F6M!yDqmfuV;57?AcZ7+M>(=6rFSwCm<gL4
zmm=lgsaV6+Xruz_I3bQ*oI^!GVqQU9fds1g4!JX^d^ad5$Hg#l+-f&y;zuha<?V{q
zf?bGR{OHqBhlRAjQwu68$yJ(?rKwrYQz?rvloF@XNXDrJJ$fQZ#V+=yqz$SWkvZ<Q
zJc+@)I9`noY1Z`7ry{{1(bY;DaB^782r{>29HtB#I&Q!rlxBq_{58kL8(bi%WW5GB
z<D_F3qppr0oKb9J9lIE@jdko|j%{3tU3}jyDt_=Ch;3YnU3}G@4_0CqBet=MUA!H!
zjYHgI#4g^B*v2Y$vA0ddE~ePVI(9K)8$ayhCUflKSCehueBT=oyBM}S2-^e?#Pa>{
zrIH)|74uES`W+eqh=03E^BvOqS?uEeu4aAh_)Vt2(^)yo-}hUUDLb8m&wxq45lHz2
z*!uQ+ZDGBwZ~xaYHG|ap!so}N9|*v=;6pFzhplF16#=YW%5S7v+j3n(z}Buyt1-VV
zsn;ERMNImSK;7pD-yzud2>o2w_kKLu?I?vKit)`O6unQFpGfbQFiybMGD6Y&gso-o
zm#{K{lur+Q2u%8qK;0Ll|1(<M8Kiu-?DaZ~`vQI-sdXO4ELUR|Sj(0016hsboLEc!
zJraCEh9;-HGtS8Q6wO%q{8W5v@U0sBYnW^6eSWABH(=&2l?C4#M?6#K%ZNp)e17;F
z9p&=_pPq`(55{ILEDw`YH)Ix8!P^C&o|E&^=SRkkb`=>~ls-Q+w)Xk)K0P#qA7+CR
zQHHp_@Y!k-_{9uW>OMc=4(j7{9T|-y3VdR&zAI)2m%#kY=Vutp>cTYO^Yh8Ok)h{0
z_OZ$7LOwrqR#MFEUqkOz?9#x!a!)y(mCujrosw%9(@_Eserifm&_&tAI&}&i=cK~B
zhJPuRK0kP_)J6OJP~W+)Q*bqhZqQMVEJ_>_Y>R(0f>oR<pwDqawRQR{kO>V)%l0@_
zjvZnqqk<}x9dZsD?nZT(Lnos-u`3Is$S`qSsp-e%#;}V7K0iNpqfh%YK+_T`LRFd?
zD@e~SOg9$z+A2#mD&i3<Rn(Kms$iWzBgwujIZ|GfK~Usg8_$ev%n1}w6gY{&<ywSc
z{lcM25Y$vss5Fw3IAKN(232ulgUZgRMn$IJpv#Lg6T8(omBo_=kx!5I`GHRl`S`ry
z^5A#FK0V}Db9wN)*?!f16`vpY^z5tn{CK~b;CFM!cKGz1f6GJB?*=|S=ijpP;rH&o
z@7~Y6<_`AhQ9eJ~-v~ZGl;5p=e&Exy<1Xd%Lt|^7ALVbvK0oh%ILpG=$nPnkARq8Q
z*STS&Q$8-MHedK2nDhbxSGN*t_e=H1UcHj#JBdKu=ckiKno&~`fX~P0-!-+!lmkEj
z>#KbR@G%jGNpBHw+H$O~+Q+9-rt4X{p9sLGN56jiIg8b?I_1*?-vg6=B7n6^`5yFh
zR;yukeeLY?Pp8-2Y3tw%V*B`LM24BJ`}_=ZmcySF_~r+S;m>nbW|-oeW35ewfq?mm
z3}YQJ3tP+KtR;K|QqSPw%yhM9Vm?2^SpWJu+V3rcSXW20z!9ak&rj4_qJIdO&rko>
ztjXe)*~cdUfcaK^Lc%*v@cDtiPsQg)?WY4?vLiYG4o`xu?5E?197{!Dn9?Ep>5v9m
zYT@_!A?A0*=O>Koxv-!(hi;g40NeaNJ|_peWLz3T_7}>i5r&w$zYylDeSXm6z{KhK
z!0+X^2fB|B=9${-X2||bU&+&R*Y`jl)0m(6{Pb_-yibp^JNVZ?1D_vyIFs7~h}Oa9
z2P!RGlw~>T=v{-v(UI`4*`TLA^;l3XG$o-&dQKPb^Fu{d$tkORetcnRlOIzxDX24L
zlP_^}@iv7b)xamk=ZDP+`}n}h4Jvl900ZT8usA-mtp$=up=MUZYBVddBTNxpu)zHl
z9n#s?^wqLaL2B*>R~k1;wZj~G8O?Dgeq89$G0^033%Zsas{Mta_dY*rpC8hQsa#Aa
zbi_U8!Bo!E2^K{gxQ3MQmF-a)MybpfWfG|zCvS6sq>`!o*OcXXndB6kg_Ps0KVw#Y
zA0GitgTfUHK9{HIIK=WirZ^$pI!q;+z(v(uFsp3cfRlKM6|rXN`{b9zpJQ<zQ%D?q
z|L!}nkB|8L9DM&z+zFqb=y!ATLw8qves13R)vC`A@10Zn{HVQj;Pb;iJ<8|j-XDF{
z2YDZ#;PVsr@rgb^YHYHN#y(y9{Lt8^Yo8zT;rU7I<5T+lRQ!$3hK~#O@ezNc%H#)_
z!F*FbKSP@`d<#}-zC&BTly8CgYxQ@v>pnlVH=+JcY?ziiJuUbQ)b{z&#g^_l0(GCC
zo=?ZjuOVRTTLWZZS@Zen&w|3YAm#JZpP8(tr752ttgT5u5y0A|*0!IsS`Dk=3u0?G
zjJ2-&g6QuFu+Ca^nbupnQwTV+21gX|&DB0XQE!R<Az;1({adq?#VOwbthLE75U|(n
zFxC;XsQdib=c4|u?dLyHvEAt$*4d>02-JOk`ah%9ok40JANYxw3<Cl4`5DGKViqgq
z^F#hM+UKX>uVU~Ckq-FY5S3W_{4l*$`}|M?N0o7KS#>`hM_Qt=Qa3oLEYFH8qsn}6
z85p#s&rcke$0mX^H7KYu4lcvk)Ij$6A*~<R4<q{vWnma98}qmr8~gk~sy;ug8uST%
zFIAte;Y@cx`}j;<6t$0!qY5~pz$d2flJe;p`uwiGzwfIzX@9woPbkajs(gODwitPT
zkTp2XRHdMYG+ZR;$(_d%N2vz?8ZM%zJ@r^ntstTGczuHuRHUTbTgWLbwWez8JZ9A<
z?l{_1HbLu+@%!H&W)cgEn1aubp9Gl`e12dHY;r)w4^&W=#POL-2p$?zv%a5B?(0bd
zspinF?~q5MX%}3R-a%OkK06sVM;0|55{wb-QmF#D94Fr)+x4?ghk^w@KQ5&Cf_;9f
zf`!x~?n%@wOwD5%a%!DiEbs|$S*gUNl@w(<cI$0cC0u9Hpt32Y@=A{J^g}x?ptJ8*
z`TY16%?5FKV%TV~?+E8|Nv9c9)~mr!1ygX+I25sM>GR`NsKs*Q$8pIyjg#!-BR)T}
zk59SJ5AUTDeSRLgXV3WumCsMy$0zLbBYrjHhw~uswIloZ1fL(;*N6OxN}nJ28)=`P
zDgH*^Tk-k1dFQLEK0iBoAD`&+^99cDk$rwJNBF?VK0nA0UCiglzmA8#&O?|V{6fC8
za|kn8%{iFA)-c!op6{`Jeul8JSjT(*bO<xCIiwJ<bxxtvpR&*Xh`nC>vszj9H^kRC
zY{a-eEm_4@tluxay`r*Aj}Wl+>(OFOF%_R%?DaPVn1QM6^XV`a)Yfqr>$ur0{^lF@
zf5>JSb-Db7pU<-I_*|DQ9Hwo*{xj3&<$oW>ngj{ICl{RMAIE*c0ltJ^Yjdy5vLYnn
z&&={WaQs<1bm6$7RHJTkR#ZkKjbp9)IXMps?xvuO>Y}VReKa)P)L=iaKmo|nge1<p
zG8#(K2FH1YE($auk#6G8<kSr?Kj9_5+|T=Bk4i4J3$hLAb*jAvz+mf$Y@>XUp&INQ
z`zam>)v_#flVvyf^(kmgsP0<ks0&I5K1--Z!D-Qr%R)8jCJ)tOH$0M~=Aj!lD$5Hp
zn!5<2UG7ICUS_UGqjt(*M_HMd7%cN5qiLQLLVb-Z9mvDHWnR)v-C&uQ7%cOWd3zMI
zT;^SahX=!&yzwX{X>umV8G+p209X_M?7Ex`g6?Fxm)N$0;RdJGTF<t#Dmy^;5#2wu
zf}t9^AstoaYD6rdG<WT*W!Y1>8&XjhjtU)B-;io~=w=+M#co118I9V>NWPme+Qn4B
zT~tS-?kl5FtxXIjqofO-w;BzN4~W6ijm)dbV40W9y9Q5w@?F#`UI!i?j6qZ6Ge5h0
zie6<b)QcCiASw7vHjBXafP3sls`2y5SKROy9+;D%3&$BXTF#2fXryth^$#9S=0U;T
z6qHe2l+{8v;YKODnZaN`ukggEjE0dbqd}22m{817izFJ147$PV;EyjujwBi!argSH
z2v-@H?-}U0MIK7IbEKtO>}GNMxa;)tp-LDj=jv)Sw#2cvT$d^uC`=n1=jC53wb7_~
zfj&s28-728B3M$p1Ed-mouigiD>&oV<j+4#8J;)2qA<N&Y8TWgYF<tUwglm|!2Lq6
z-)tn+wo``f_SN_?fNuDOhXJJ<e&9ILql*oGnTOH13#lgEgle%He!O8Mhl9F^BY8{c
zWiF$ki_4{&AB{Ad8_e?(gV`u*Mx&vN127o#l5XO>8VshYp$l(`RKs%%-Qc+-1{ahh
z4GUf;@4Onxb+5>%wwJKT1?R{v5!koo_e$n?l$metjZi%r9SoLkW-!>#E8Mkt=r7JY
z4G-0pk-R00x$lF!D117iJo#)273lJemz8NtwTl3--G5`deOhlG0mF9d?u4t~QN3?Z
z{EnTkIO&E{pOIg>_9=P~ahG0v(kl;KpBLvnaA58E8+%WE;K~Ep#@>AV9j6@LcEhRT
zZ$0Jt51w)A_?;iU_${LsT%VtC`&-cVgtbpydEi>NH(x*Dz;ES6{y?_&{HN_*AAiT?
zmp*Opc_)3x`r+r@aO#O~JAwK>^~86+<>He@FZeBL`#|xj4C59DE_Qp*TOX}I|5F<>
zuGl5xid{0U*d^nNT{5oN1tc-&|L{V3t0KE7OaJ1Ia_ISELV2NQYIt<}M{jt7XKUn|
zh^KZTk7h?12)QxxRW5kbMKy9+#M=k;0yjw#j7pO8nNCGWg!h6lZfO@<lN5ZWi}MNp
zc_)r5c7+cz8CM%!GCqS+_hZf{-jHQCxdYjGmmC<Mw(-;3e|Y_r@7_2oFV=tMz}h9_
z@u?S|Ho9iKfBl80-Eh_gZe#8GORgmUnYC^AU%5YDJ1ZZb{3{y|UY=i;ZEQU4TDO0F
z{e&CN8lSPg{_DSf*7(G?u5G*In*F!0kG73Q7u>#nvAe9eeDt(!=RKvkDI0G)Z<Mc}
z_Ni?A!|Nx>xUg&e;$OdC#udBbxWO(NSL~8;#jfWP78qCT3dr!~vov#)ZXvMt+Gcxf
zy_&H(UM03(#|!zz#!ao)?gtj@bI7fL$zPs5<QcX<H^XdxOuu%M-DmTo)}IzvzcS0-
z{^kDIJFBJ7JiWOlxRoZ|Mj*wVwDs%u+QB+ozwWP5%EHw8Vc#W_ek1Vq>#O#Mul873
zUte8TZDqNxBJk<AM#~(fa73xEZ!EAxZxE=zezoBjI-Rq0ml44JOtx=YmshCSHmsfP
z&(w@hmrLqvXP<GpyjqjCJ#bP*=X9>VpO!AObbk=QIvyzcW3O4-j6iA~EzCqSZhb4U
z{g?W-V$Js2S~g?Tw-Q^+zO7i=-qe1E*oVoa{|I0mQ~NOWe}=0wgZet^?;Gl`S6#L`
z2=#8Jjx5Fz1$${d{oOHZi5??h`=a%D@urymq+6#bg9`g<4NWHZ&7yY|>`g`o=DVIx
z-=7R#IVf}N?E?oMI>-^|DOsLv6!g5K!<UWWB1@IS{$!*i|DX{c)L=|bMcb(|b(K*o
zKQ?=NuCwD0y7CT1-Y(e}P3)3!sVi;}x@p?4E&JSys5`362kcT(Utb!r_mY3Cc?#HD
zY^YM-H*HAs{7O!D@3ljkQFShuUuxg9YVH2zurJz>=SM5zWK|@AebZijF0}NR&dNQ?
zped!m`$CqJ0#9f!eqS_xi$K$gIDY&Wq~l(>ET=R1uR6MH;N74iYt*rGq{4%L#6>iw
zwuyD>6gtjH<!y45Ds7tf9)W$)WZyLE8%;?HK09=Sj&fwt+9AQV_%|b1#i;`N94AzZ
z`=*5kq-A>?D#s2nlTks{%MLjQ4R@nD%%PLfoY*CX$}n+Usp-e%#;}V7`=UKs?wdxM
z`a*?@s9c(g9E<eq!gPZg7oK97cV&`O9<fqMJ$bAO*7-A%jr)OdJr9ac^0|4~0_9?`
zEFP)+uzulCB?xLNDO4KCNt`ev2OO$6u|Z{LRHGtOaM0yNnTg$MoXX-!gRVUP1MjBp
zW#2UHi}val-SLJUcYSdu_AaBn$!^*AqC0lWzG<{K*)31J7J0vK8tsGj#eF~f!QJJ)
zX<=Wque}uesNJzW?28unO*?w`o*n1kvXk~nyYJr5yylMWJHGnT9UtO6@0+H_#=dEk
z-@W6m2VW!mrhSvf-r>jg`=-&@5Bojac;7VH7mdc|ebYXCX_m#YY0tJ23cqif&JQ8I
z|D(;bz`kiilhk~%_m)XN5y0A|_TK8}tX9M7`r6^G$fUCfIBgkx0^avqT4U)UA%OKw
z`3wwcuB$i~Ti;=?I(&NU_1m8{PWkk}_rRo|2-N*X`Z<f$wA$9Lzv~WP5c9R`@A}PZ
zdEMs+-yzud2(zMhT<bYKI{4=A{dm+=%A(d1y+I(wH^*9=3<Cl46B))jVivZR!&yuC
z2<T_9eI^>r+B!WGtn=qBKBb1Fmud6e>gBS{Z8ZEu>b_lbcVZ1Xfq?n^bYdA=F#<jx
zDW9KK2I){Im~YkRCwy}je170pBfd2Sn5gip5#Ji3x00sxtsx@pD8m+cdGz`5lwD$(
z2A>}^;6r?V$ls^p^ApDPT-fytW8(1N=E1fN`d*LrAq;kT@+~o8gI(lnlu-k;@OCL*
zBiM!cR(yV_`j7>FFV*!O)@<v3FStWQ>i$f+OzQOH>c~zUQQ#AEHTKFKs9=6W_K6v)
z&(A0CuHBHqzXn?P{LsUh9@ZdQ2cI9Pv~Up|9{f9pzwHzLHSp=79t*0ErX=(-&*|cQ
zeyFG_Ic1g4k1s538dqzh<J_C;d-cVRF5aeKZoO3|K0p3_tMvKVpqkWL`TU?MX-L@C
zLQ<%i6|g5qie^Q2geisw(E1MP>}&dJ*{GoEzC$DmoV-*!%%Q}%(JoF&16Ph)P^Gd%
z_!_w!svz+B`PmtKejKI~ZQ#bpMH{GFR+cANriD=|6-AjuD#yu#P#~#<eSTCPwUp#4
zjU=0egu_Y9q6OfO7|P&ikngbI>g7q6Of>0X)mnI*q?t0vt6W*asRo?z5enkZNR_@%
z-jt+4@af5v&yV=kkdMzBE{D(0%@5sO@%g!V=U1yfKjhP+eSW^c`3J@ChJAXJ&(FO-
z`l=6ZS3W=R>8bksO!ym}u6=%J?9;W+4~_kkudev~+_^`_hR+XtT;Ba~^!XY5&RCdl
z$_EBF$dClS1@-yXZulWhcW`t0($3~7nZH&uHeD~N`}}m>UbC-606qieYgghiv{c<E
z1n-yjp4r<~c4Rq@C|F;$&rj4_Vi*XR&rg5W5xxZ}pP&BBWHl{K`4(VpP5Oxd)=saj
zeg5gsI>Hy^Mb&+N`eVFVT0!7IQOQ;^SZ9;|BLKd6YMuK(!_}FA`3?+gt+nq!eP&o|
zlU^d=>Q-Yd?>)7ywR|5DsQdi%aSmp)M<C@RfOR(MKLT~1AN#$fziX=Y@o_W@98usW
zVloT_%;#qq>xfybl+RDt$47iZ3VuX|cO3ZM5dT;E{4g_D`}|M?M|1!jTo(56i9SE@
z>p?d-s4NHZlq&PVWnj>jK0l!w-d~6b&eWiw$~d?z_!^1N4{80lei+$bC=0_-*_g-0
z*ziSyRDFK91J)1d<n&zN_ww6`eSUP^zNLq}j}O+O?$4yx=PS9+^)sFF=^6U`;PW#y
zflp7x=O?EbDxV)e-(rM^GCg_WG*gv=9@1Qtg{L)&9UTq+HC#kbd+M>ET0!W!pHp(Y
zzCmXyQc~_M<dl|LQ?+&9s-owPqfKQIT5pVHA0HYpNFfRK`QZ-n78UmSfi1Af0Tn;_
zg0duz&tyXI(2$z-{d96)PZ~%yhi-j`JQ_{A;F_hc5wcFk&5=V*hXi8;yHu(`F2~7t
z$ablHeEj}GC=UXkpQ>OXwTOEXbqiDTSjL89Dqfr<!qr<=D$AOzE6S4Ct+!c~aGgnm
z%BGacD>=r~5AC>s&c0ja^W$4I8^q;_VWYvmBb>`6on}y3Pu8x~Ou<RxP{f+0&yQE3
z7K`lTBYD}!M|^%{A0OH0NA~d%pPzCcAHUDf!?KT0@cGeu>9F68?Bf%BerR7G-p5CL
ze&BDUeSXB>DDLxf^Fw|gAKB;U=AFEcPwDgH_wk87KQ(_N%o9E^vd@pqd&pPw`5E%+
z4r^}a7t-(bO!<Y>{k7toP`{@<RO_9d7<>k7pC66Lu+nv(pJC0;W@GC+?0dj`e)_Y%
z@GUT(pZ=_uwzTdSqRTAZeFU^mPu*Iqtw}!-fG<dDZTmT^)w3GwsC_~39f5sM(EIzq
z(F|}z0pDEh^Aq)!=pO>+^V7dIYqHqZvI&`f>dk+vpX)ZS)pegA`^+>ig2%1C(<5UY
zZ66<v$S~7&pPymQa`>~deSC(s#;Ltu%ztY*YrQf)KVd%|%ojdC1$_;J!+)!WPl@1=
zmOek8jY^Evaz7nzKrN>3r$b-PjrgDjXtbSr&*|VHs1Z2Ud<37LIBu}(WUAb>zYy5N
z)J5rQL_?|lg)$7ooL!6^_W6MZQu_S({Ls%s-sh+8^Mkv#$N%3reJ{f2MeXBLDbw}(
zn#TN6K0ke(m)JejeSBno)2>yYpLYFg3K|ga80G8R@8d&n1qD6)wNRCu-)8U*Ru*w<
zdbc4Z`61C+NrCsOP$X*aXGFc{Jg}(w>f$~=ViPqdDfrAMdh6j1(eX5&AAWz82F_2c
z;`773uy0My$=D%suE2Rj2PVlrKTt?FC@IH<UA`L4yxI-7K{r%|1S!<a3aaLEq_~@G
z9X>q|-UtN?X)$vxsHh}YX-Z1Z4yeF}QmVPkl_i{Fdz6l?#qb3y{Ta#9m&KcsHmGLA
z#IRy8;egH|=#XZ;Q6N)FFh~@IB*Jw%PEK&hV|B)1%CMnA0}j%>kc7YHxOjsLB$Z6v
z@95psz4rNu`}l-?eki|N`}{odTIBb<D(>?`d+BJOAGMbb@AI?c{97K<K0lP-Nj^UJ
z#eIH0#QD<a2YU!<pP#!Pd`;EohsTaSKM&ut=X~0?C;I#Zf1|TypPw)`^1RQF-~k^P
z?DMlKVm?2sveNyZr}_N!cMWar`nz_pJms$ip8=D8Bk=a?tM=;;%k}luWz|-e>nZ|j
zA0J0H;)qgT-&kOY-XKta{c6ME^JCHv1mIg>K0p0ftGbm~JM%55qtcIjeeLWsPCwR7
ztbCxlkB<{QuD1V+Mx(#!y3bF4XJVFX->o_t@GUSI1_I_MGK_V^ENm@pEr)}^ux66-
z-+~W;N&gWrUy%N<q0FGZUz7g6q5gW+WzycRokPHpML43s4@B+r6ZMwp9|E?IPyf~|
zWpT=X3qB!36WPb7oEN>TD4(B-Zw-i|VLu)4e^KU`Jqk7|9aI+g@hSX1KTr}GmMVw+
zbf^J!6McTh#I&yX{9tUbXPH5p<<t!~2*ZqJA0M$x#-&!E+-6ykp+)KQ6UGg8WuJQy
zb%!Bvz%C{A^&P_dYi%DNr>2|1FJ`Dx_xTypJmC|Q+UKY5bH)73=cn(h=<Ro58l}$<
zp6#X2PbdzTVs8H$yzLa!ntSD5ayl!YAJ)aw8a?)%qbwf$)Rd&4i?WGz>J&Q8NriWf
zEOT^}K0njmBffAT%VeJ)>N}?fBn6)xx<N-dvS{s)U|al~5v<}=0ey}Wszsll(15h)
zhH_LHsT?`XWK__#?2vQNa5t*M96A}ziCto-3=_wdn)UsKvJ5^yYM&qK6`*Os1cH>N
zibmUzN2O1owi2h(NP5IdCE4h)Dp=>wNR~c7T;QSb$^XB-?~S$Ws_r}Q`r^C+x4I-u
zfh1D5=~%I*K_wI=k&;N;HbFB(Ld<k*3OEuWsEr(q6{)SN@FClyQLv)48b&j;fYU%K
z+>RAn5yEyF=YvI67lEm)*1=(nrQ}=GU_K($54gYI+W*!$@80A0#^Z4JerrqToVEY0
zz1DBtd(VCM?cZ5EyDEybd0Ef?0!0QXFT2hlQJ79%S0L}ji5>+SL=zm2Si~SM8%xMS
zx~{=NkMOlp)M}h+_g;f;KmMrZ{Ny}7InPhd<C8f*$KD(B_+-uxcr-73bj10&{OpMH
zlk)f!&d)a=J~QI{oP6=llZx|G^7tgq59+5+D$Y;M<CF6IU~SF$QELn5C+G3Gkn;Rg
zC}N%;UGG6Y_ta)D$oc85%=tUbC(@hmJ^N$4k#?gyjU8`AR<;&_pe-XO!1DNLMEa5$
z-#N}eU)~-*Z!Erj$DEuVd;hi*<2g<bxd&F-L}1DrY150tX|=_!-MEtrVqCj+<F{YS
zr<@=DhG4%V>=(Ts=(wO)CwD;Q@fr2$aVEEcz}$Xw<8QSQ!~IxkoS*%m)W#T#WgBtY
zkCo&I=+9vLPP8A?+8e_-fAHz{>^6(X2pD&3j7P6E%k$GuWR3IFPb|s#nB)BP<7xDS
z{{B3^JERiguV(m`m^eS=)nsms=T6j=$0zQ!oz15chBQI;BPY%eRmhP!KPit-;ryg^
z<6c-ktUsxdU-S6wbp>fP97%S?&9~SIo9vQ@?0Z>aZGIv8JL3F6W6!1MJU)!ul=q_l
zzM1lwbYEjJ53rX<DdfbcJU^wq7lHm6=cm1B{;!88HYa`!Tgmwut~I|V<?*5FL{`At
z+@TgZKb0eaCKiW7aemmOZCb{LdiIz>#Yt=I2)IPfPwI-z>YO=0i3#E`9mNYFB+vpb
z<Zws{au!=XMM^6Qz6_%Ra&KY@>B?K-fKLXT<H$H{Sa>vx8eXw(DPx6>?Rm8zO5(a~
zr(*go>v~+PLUN6QV^b=VJU?j7rsfe;BpO{ZHFwaWVuOsxJ#rO$REwZg>%NMV98b|^
zPf?Y%`D<#wtD;C^7NsE7c&1nK6+;<Z42m9l8D3B8aVY(+NFu0MM4W1OF(@{L+9T2i
zoL*tRBj(Z>6z3=B(kXd<E?#+f#QC{+>cuhV=al5}DV(3gtI52ZlE)|I`FZS)yB|NM
zI6p7F@A#v~Mx3AHmo(=GYai8|AFO>;bAECjpUU}(d3<u7pPa`h=lPj{+FjN1_;eT2
zt{s}oCt`f9c0)hq{Iu)I;j{cZe>}?bGyURG00FC?MZN$*&g1g6jH7_>PWg+HehSOl
zv1KBkBEzEAft>Y}VH<?JPQGp!R+{s;d@UVo1zJH{;<XOh<Wc=@UnS1k>`m?oGAh@`
zv#EjodrKaduW>}cWy$zn|6HDO4nq0Le%24y;mi7)JbZJ=Cc1hXdczK^ya9i3eTd(R
z`7L-Cr!ZWP#{sSItvh%J1q(m8m3((z;x|4AY!>&)cs~sHJ51Q&SJl;%!!Bmx?;~i&
z3OAtrLv%rw#j4(+vTy_!a~8|R&dPC-`vxrgP7ipYHVDDrJJ{ttI$+kY3OL^)YQv5j
zc5Z+LZWn5YH^Jv8Ip}(*Tmi@s!Z5rOJ<i|fp?0}gdAD-IVkbX0;OqiVj=)g<{RJzz
z>^Y8y+K5BJ3APZ2g41&0i38li_}v|saL72JRdB$vfNaP(ptggi`(4JN-~<COXHjsv
z4?}?iaDuRKG#DaWNH{?)<NKeU830+pm~%J~9yt$Zi{0>R=VjviLn^*I%Z2#mp~vET
zp!f#BkFu}$hWt9;5MKs!V0?e)>p8w`vC<O)<m~;2KkvyS^F<>t<z()llZTZi5eTrF
zM=6Z2%ClG6P3Qvw<J`6r$G`s}%cIv$wDwv$$L(Wmt+a^%W2a+l-+#6`jzL>TF6Jc9
zp6)ieAq39*&Bij$R@z5^e6P7Ux9{QM@xZuyeZ^XH_okjP)>isJz}~lg#F1W1Ik)|I
zcKAG*=3mnYFwR!mM_|giwg0!Y8&j1>FTe{PrI4p-r4Iy*bK6H8>BXVq++t4`{mpsy
zynIBZI}Z1IVLzAV+;UqQT6g6@-+&1L+W~k;A9f=y1~;U9b^)z2fs-%`o7VgwOJG9m
z!~QnKxlL-8m?aZNTwgAc^5}7++Yu-$>&9hre!n3tBNMnT58A~t=G;nCZ>OLgBJcFa
zKcHLsk$cXg$0$wt#5!`{cDg3-oN+?~wO{%5%|=fB+dOi6d#0RWd?1x_*ONu;Mj)s5
zw|+sn;~+2P9-$gN?g{wZN1i==$d8N1hqQDJ>C>9s0mlY@t90Sh9vVGHr2?28#N{sT
zQ0!8r=JpG!6|*sHH_jThi{fHa?c(g!GUw65f~oi{4CLI3!hyZGlcCTS+7yUNbl#(i
z666dM5<@bNoaVE0aa^8|hXtyQ3S~7c<z-}C7yd~t<aHgZ92qDSyOiYF?s$p{#V(ac
zkDS|4A?J2n7)V`s*OnEXnCeQOsG=*ege;^hXX#Q$N~^DZRODEVHhYSy>@`SrrkSb*
z+Tzkd8gY(l73VgN-fWQc&n#OEj*57uvVv1>rX)DkrcgzZ*5IUZ@MU=B4de!nlJbeK
z@!~}0Dd*A4oZFm7FX!3IdGs>p_R1q?j$crm+r(=voZFH|@4YF{-h-!~(45=nA3S|o
zb8gA^)tuYR_br^;iz$y@&a-#%)IDR)?J3ElcTdi<H{tuzM{-cVeA_V4Hr9JD#<}f1
z!u|MXyv(*^X?*Fn<EN|-N*>4=_~2)Bi^)A9Fy;L8<eT{dPA1;JIuBd<1Hi!P0s(S<
zzWkmpT<P8kato$;_U!%GM%Wp<fB#||wwjfD5zw5TX)j}IrA-9L1(}O&n_eA0s~Jbl
z1>t?s?v2gA4gx&jQ405)t2}$9-GufKFz!HmG23LZ#c~reZMGYKtIfC_)N14W92Bvw
z86UJIjN>1@QMZ`fBLY*-Pmewx2A`&R^z3idwxj-;-`Q-x@wYZ((^}6u&QF)`UGi!Y
z=jZZ|a941UBmSyJkGY4ma(?1&RP0Et`Rrsuzyu!Htz5V@<ouvzAqOUK(lKavIONwJ
zOyC}CITGimtefmQg25xskK!6}_b^mct`U|}T%&=@#4WN|JK4n+mdg2w_1@1t=h>Tb
ze)y{8(P#<U?r*zM9=%bY9@nZ&|E8RnR()A#H#t2$`?t<#a(-%_y=%*_foi#9)c1GH
zqla68$A`Zz7~<qM!#h~*;{B%Dq$l8p!Fv^EX<|j>89}>~g+~*DaC+uAKXTinLMmRz
z`GMgmo+r5}$}p_tSua)#x5lxlDr6;io;i$aLR7}4sD?dtT`m)cK?!b&gX2h+AZMz<
z5EM$$E({BfO;O=4IX%Bwe}6#h43~xT98a}m&4E3%p_Xwi*;Kp5o>~<fQB6oiyQRBw
zS!i>#T!eUXN~ZWS%VvW!NSHyj@OtHORfQu}@k*w+9;c9Ta2z8=3|g~n>fV4u>Qy*M
zi{m*O>?x`uIH|gz^#Igs&QHmsm-6hPep+*WzJD+4XYRg`^X!3Fqd7l0j~+Nc!udIw
z^5|Viyc^U{f#Xv-KYu3m%K3Tdg;OKW&qL3CY|QzQwcnca?A1JaG0$GkqnGpS<ve<*
zpP_Bpe{x_Rcs|$myl84iCldYrxjQ>?W*=^lH*)T&@xb`;FmAKj_94L7{q?Esv&$@c
zc?68F_3{{P^N2aV7C8e}+D1TgKIn<QCr;z5``Y&U@K~?%_yl;(qm*fUONR-~ATWLZ
zYQxF-vC;+t<Q7ahKW$iURx)<REok#~FpZsk$7w5$lRQ2_TTiZtmG%*sa(>$P=<s@=
zxm!~d$Stta2Li?u=_8Kx!eVK$><59qJelKfkwajmeFTgP(tZrH2h)5_`uB$E`&IYl
z`F7np1OhDLQ3`n=D$h@8H=#WQERRonF`Kjab)VhbOHN2{CFk*}e&Md7I6ot94gdR}
z^67B@FZ+UQ3E*y29Oxsb2OD1l_L+v*x8&B=!udfDXB5uQ61<)f=Z9;{URds+9UN7~
zT?f&woX02ImDj~AnSgaUqjG*y9-m~_@Z7thj!W>MU8+puixrzM?yH+!ATOrZGUfdA
z<R>{Xb9sIm^fhRk>EBzwrd#@w4*};V<cMW~oS%Dsg01+NzJ~l7-gclmYQ=TH{Ri)k
zUAb+L^D{0x_}C8tZT#TJR1}YkvPs(1NxG6&X%0A7&d<7g1oQZ0&JT1unU+k!Y{jkN
zY_y=zmUuHNl4rZ)iNi{spELojOZEj$qvTklCku~jRVX#Kh#IBPu`RC_vRy+mG%r)u
z%_FDzh45_X+lN8r`GHn~rVAZNrJ9;sv<<E_MuDSM2}-6I5vz@`F=FMVEuJY>&X06N
zD5A)-tD;Dom-Xx~P-Kwuvg-^Ih3VvV1@c~;=ux0SG{NDBMGWGyv4kw7>lz&N2wy8j
zt;VT#?=|T5<Bw|2PtN0$^ZevIKAH1_TsoID=LbBR7d|@T{G>cS-?@`{f4*?+{g=;-
zI6vQfnDxr}Ir-w9Cl%+X<nc*)eo#MsQgMD>0^jIl<QqlKPtN0$^86^ik>vTwd3-Y8
zs6r9*{OEcQ@|5GEeIn<lw=(B1xd&F-M8J3>ZN`mOPh-bhk(D+OASdA1=i9K=tUNdZ
zjPD$0;NTi<#x@~f@!h6qToYS@)<RCt(ff3Z$=i&;9H)oe11n7+5T;f#c5irm+G_O{
z5Mb<#uhl}N_S#4;h{bL%F1@u(IY0aj!G1?*BFaHqN$!Bk<1^~h<4kS?fw}$W#@}iq
zhWoM7I6wPAsf{rf%QoV)A1lcb(4WEfooGL(wKs-w{@~N?*=-h&5isu77>{0S(>y=D
z`q`;pLHos6-ao?=(PK^CZUoll@!4*RUzv6E_vi85A(aq+HN&^W#Q7nwCUa{%ccQ9%
zI^1u|32_p4qmJ_Fgdt6k{m40=4hC})ew>S(pOnX^aDLLdaW5<%)}PeKuX+6Tx`MPC
zj<{%7+<c3*lU?8%4VYBzQd}c)e(3Lr^Mm0%m!9+ZFm6-ci~jp&%4gDjjm12`ULK{8
z6LZ%?rP`f9|9Z}Y(<|qv=J81{$;7W=jhr8RIOD^b8?94L9X9DAT?0O;<*tEqz%j$G
zNqKxcMy2iBc$+)aBIgH-jf+E7aeiWFwP`sX&3lQ9=0>ftJKz#+O6E>yl{`Q3ep)#{
zD~!Z!#rfe>w4jKsK1&=qc-rGA!7JF2Tuc+#8WrLkN5)~p!ee+;NWt?I%UGdfBiAi<
ziIgXVx~|8ds!-(@V*CC%KY{KP8)PbL#fFT9^vFqYsMTsiZ1buMqGL6J;3=xIHh)d+
zcU2Tg%%T*e8qW-Xe8o@(OV~Ju%MKYjk$K7?%MEc<u0?}Ot*8wdr`lBvicJ_XDjRTm
zh53${OJ`7=pPWml<oU^Yd~%+ji>F>3bADnTpThY`d3-YO=CQx{*ogD<*d2F2eoS$G
zUV7j0M~{s-KgTa=&QH$clQ}<F`>5vp<UBq#&ri(blk@zL<H9^XInU1|IwOP|tpsg1
z{rywR<D(%ld5aOa^~qvfC{hxPuQf%ao%)pX(~jk4DLDgkd43F`wh@?eLinAi!|z3H
z2WkJ-2Mpy=3gfHt{FHVR`apo3ALHz`5leCl<~ToXcyV~GoZ}WSwpQ9ifU%p4ZJS;l
z4y%px(@&hw`^~;E&Q{t-fcwpLob7MTreYejwT$HteOR}c+%f{1J3v45dy}!Y(j)?5
zYBgi|^mEfztG9^2l=IV~4`y>jV4D9$<H9&wX&-?p=g0ov(r!#u9-ja&c$7k(h?PDN
zuslC~#F1VcD$Wo1HS{;<`SJ1*mF_s?-eCW)=KRRcT+R8xgn&N-c}U+lpH4t4_QOIA
z5A-?ihs9tyq>npj2bc5wBsELSk_jWO5tm4Ld@|<;s^YqFnVer}NXy6suFGRFI4m6F
zTRA_{)b*)n&QH&IeE6cA@|pAtm7Ew|@M3SSJpJn<lY_2J{nLG|$WzXejuAOOy%lnL
z{&#(@Wsr|t#rcW;dfXGpgV-TyW?VdGNY@}!V`so+1HVSP@M#Z?9-~qL%nssmcZD;$
zR7pIe4K_K99NQ#{i%nHgfVf)bJU&=36`uv+{6r_%8#zC;g*F8)6BqKRq69g^_r%c1
zBd7UvTpX7t<Y9qoqe58?ZhIM7xkjvpysl%7BLfA&h;}K-v*vh;3dJs!$0z0&Vt*>k
z^D{1cxh~0fC#JeGS`4Qvv4kw7YqYF3){)ZYYY!DUR-?_HqAGh0Qk`k0YJs-6bdW}z
zqguuJiK90gB>gkX7K5WAo@+>>E43#DxHN<!MPUt28V6s7Z_Ib}iLY^tD+6;LpUnBm
zd3<u7pA#{c&civ+&y`2cFmF%c{3Kq@7jmAT#H(TbS>gOVc=`#=`FZ}q)0Z{phkPT=
z`N@2v!uh#)CFb$Td45tJpUU|;C3$@A$$5Szd?Pwa4ouGTQylMDpucl@Z+df`+=9d8
zZ%^?vUP#-~oa2QUU#s2N8t13o*zL#iDd%TDb8JjI2u$P4KNGApjX==Wlk;=SdvuG*
z+lm0W1yjzCy&tzVT4TEyySM(!(iVzjLK6tgae5eAD{UfRoS!!1Hno~@oN__z-Z(|6
zxq5)bJWAnybCu_(w42Z#0*vL9C(@o5W-$@4SoZZgn0sF`)>isJz&Jns#Bq-E(}$Pl
z#gy}7h_s2oG>?z{t=eWBv(<0@oh->U=$i4jG#YKo>o`9hy?5*Dmb{w8`FZW9hr#1#
z7#?wFD?R2O(#rXXyHT+twdT{2378Q%KZ;w!d^*@58}s;J0w<L`K9~@H@!?)r9EtN&
z)=hRDahvlCk@EvJm1~5h$m!v_D-X3i(z;keI6rJ*sd;{4z4!BB;{5Pc%cIc}wB6*q
zs60NSK0U5gnf^^VF|GQt&hB3G_^k6aw~_Nx^ZZ;}ehpOfZlT`aF^>;E-90}1b-_n~
zlUoe$V6{tT<8FgSaDH%B#q(a3x^i>m89{sG{N!f2hLXo;Y?H5}mJl7QP`r-w1H(}~
zPjW+)VVd(J9V(wrQ798U&vcGzLR7}4sD?dtT`m)c!Sk^iP7yWHlB{s>7#18mlU?NW
z{N@|kAO)@TTo(>h#VHwL)*Obxi4C=z7O4`HOi^%BZPbMF3iH>*?*~zpoP&}nW`lu4
z?uk$&&QESk@YSlXqDbp;3K<7ih6@gBmQ4dT;E<>LEX1qhB^vB0s<JlU(F0JgIX@+j
zPs;Oy`f1Ji`To7EpSk-&&hrCajpqF1JU-w63FqhJ@k>`U=Lhvu;P_O|&!0)Xa(*6q
z;naxp^U$*&8*_eS?ZWw~d3<7?pPa`h=lRKbd{93_+cF;Hz%b8GE|XVrZtmtve}B&M
z{B#q~o*f}C<gZWl>|wvY8DFdI*v|2_$QiKGHUiT;Ao_dHG`_m8ZLbfH^(v1~fY&@q
znZ~ztn9vLY)Az47oSYvkZ6H8y!IbmUhUI1@V>ibeF@&}k0gK)C#%4d3z2g@~qk^tk
z{uhl#yYiIt)2=6Gx#n(7(U|Txx4$>12(?pZEYE$o9ed5v%?PaH{MdVQGhW-=!&u(?
ztJ`d$*>(^F=J;FW5Ljs+0po(SAH(dyl)I(xqto}R?#uJ-x^)NySj3|g@<3FcpVDqZ
zdk9z_pY~!lXYuPkySbN~klsqp<5T^@T}5$zHs#adep~hh**(hLs5rp+N!*$+_?YKM
z_RlKLk9-m;&QH$c16A=;l55MJVQlKcE^MfQZr<slT{(|WwkxlTSu!E1shppb$0u`s
zY91e1W(CEi^cdeC|3Gn%LeMpGetIoE=lLNgM(6qI?Ry~o`;~E?pRQh}>o`BX#V`jf
zB!Qft-;)2uk>^l3KdC!i{DJv3yzM}>+%Y1C4mHL3K~0q%+$Tan13&mN6~*JCY?3y0
zk}i@k<W7cjz)?9r>*DsU^TUwy{6M$E1QajlKsC7ah(fuqp#_Du#G6r(Jlh>lT%_dr
zDWBmnpHASkqL7{}Jcd_=Qe%s#Q3@T~@@gU5l?~0yly&pSX?~$$Am>Nr`GHn~rVAZN
zrJ9;sv<<E_MuDSM2}-6I5vz@`F=FMVEuJZE%wHqpA}CRm^X6qe`wJ8qq`d4pgG6CE
zd0m0L7bkiY7<QWAaKs`8aoJcx7SeSM4tj*Im7-STRJ->Ybo=o~HRmVi@yU69avq<|
z`8oF9CoXBuPtN00IX@|n&v))*-k&cVd;jG#BhJq^A7;IBeonr4=Sju+DS3QSo*&dt
zpH!Tmn#U*Q`N?^FQl1~hH<CO*IgihUl;@{H5%c`$dJpnkUK?_LdMk7OT0W6>qiwtq
zi(R`2v}-vz0dt(6c0Du8i2&m}#~Cn`+D2d+U;Y_jr5^;y>G|?|`thfCPo|t6{eC3(
zz)BMcgsGK`oyzkw?Y8<BBf!`hUu%m4G-I0O@tFaqqpm6Ehxbi=@9fCc-dqXVA?`O<
zd3;8FdYs8^ATYPzoUyjj2Lg=cT&(->@^E-zvFs<#<OtaNvY&Wv^29hln~-U%-Qw6*
zysp+-%ky)!$Zg*|#_}`cJU`oKq*=5t1Uk>-vj+qE%RD}*g!ro&emP5=AM$E4x5jfP
zYRcmi_u9_p(+NYGAp4PXJ{_o_8vHmH^ZcYdJ|)jjS~u>6<-_`u8u>Mkzv!(Xt%f7X
zuDJOYJ7H^np#hV)#M=Bq^moMhfySOo&v|?pH_dxtUH|4g<umC%j%}y}*vg|6a$;1T
zpVHooK>sYyPkYg<d3=)XiC@DSIY0Pt#)ma&1&Q;+CS9a!7#!M`(jIW0;n$=*J|3eI
zSpjczhg#(PV6ky=s4C7+?5sA$HPsXkWy+@56L5((r7krgikb5hKancuXNB%S3%HQO
zAtlIJZ1of=apd63Fn9$!l8aO!g||W~#5s<P!-j=Nv#8;9@N$;ZSfOKEUM+}{xGvkN
zc*yH|*2O{!<QfG>DV0f{AGBsu^9U*ujV_s*J7`g{K}O^rxr#lirPvVLyy}AJSdBJ&
zimI&5UsL;C6-5%WC<Up;Grf{jfy&@wQ1sBt@OoO0L+N)#5<$fx;#9kfL9r>+9+5WS
z^a}GGF_+GuI6pa;PRa9=^Z4XEKNnBEIOhDsJU$=Id43YFCi89{`-_i_I6sfwarfiL
z6zAuq_Z@%q*ogCU{F3JUfNykEbAGV)QO)_ud3<V~pP0ud=lLPWg?W5(o}U=Q3A7zm
z>96JS=_sI`yE2!@$M{<92H*Hv?Z)nrpES--yU`n4{>azIbzNhet+bB-<2V=R_B}j2
z9?Zq@8^3gTaA?KTFV1Xo{O;4OcyV~`{P?Ff`)={ujLo+6Sp2pn5?5!(T>O6fXRl7D
z&DuW##Q4Ae>Hf#t$ZL;)#o*dwdQgoPgM%V=b>rtgYwYv>>M%XXEPI_F1g%$Rti|Bf
z!Sx_opTc*ZxzD15=(4e|90A7T1Gl_#J*MFmB9L~W{PE2>9@xjlJu<H9jp7Mz^ND+7
z@)j6uuGqy;G%q2#!BfP6;^hogp^DOk6SfHByxhUis0oT$0uG31RyIH}i<9$-tT@j^
zEAkY`%xJ^g{|5UZ&dT7laFp%59)a)OzP_EUAN{YJ`&#Lt5C8N3wPNkn*?HG*^zY*o
z8T$NVN2jgr*XMk)->0`fzH`5CTKp`2+mAro7S6r@_-s@wZ6h#!c5(XiK%AP!SNFB;
z_2IGp|NMUOH9+D~$~3;E!-QrKn7)6t;e58Sl{OIIGgPO~Hg3amvy!p1=ij#ZI<VNa
z8MkcpJ0wS9u8qIn@R_$(+DBme?Be!4I=mj7_nUp6ZUwi$H#cLo?LCa;xesr<m1f_5
z5LoxTTYGQr2f6JV!&u(?tJ`OnS#)&>%sso9&q}q@J_7d4+xBCaJ-G3WS&CPEADzBm
zb>DcF)wT$M09$yJ!sp$-@qtn`p<x6V%h!FjVF%3g5dw3u<g;&kD}VTbsYkf0q-O}z
z-_f&+`CvdkCs-buh<(6r@Ijsyh%Ln2MvT569vmO=7qA&P#J(l>4s+A+YJooVa7KJ~
zF(xdrIk`N$n0;KEOT=Xy)Ii3%JkY0~T^#%3x|kL1@&jkYXBT5aUN_k_es(eKQe_%n
zuG)I}&tDyR5Oi(&d|%zyx=i1u&o*w|r)>YXUBAB3NBU>aE+!J~mylfGvy0=ijrrN0
zo?VRR2&e9J@w_h#4mI2aQmM}_mfJ#ZmTQpPj)yE-rOn|SpIwYkcP~x#v;)N<pw16|
z+#OJ`W}F>qGSa3_NwGsyv?)NUHm$oy<YyOiDs(%!BvS&_P?5B9Hd;_<OS~Bs$+O+@
z#9@4Pv1cVsK&#jjIISq8Cku~3RiV__B5IUE$F{s$$aW2BmAp(@H;;_#%4FJw!e<x%
z&FJse=y~krISr&(O=V3=)*O<%shJmXvDQNsMT&^kMrevyd1;Ghit_AYM=2I%5F1=<
zE$7Y4dXC8k*I1-wQwWP58Ch$CS2D%DIMJg(gT^?CL0mSLkcD(zgM%L7Yo(~wIMwdG
z2B~Kk)2zqt*z^40OL&&?=@Sn<`!PP-c>L_*D-YxO!7r3&7t6DaFF%`~U3}ppo^Aa8
z%V$m=zjP%%Klls!*~Ri~<I%H=?|xiAyO_^5*3T}cZTi{8@@!)~H@QB$_=%%x?VI>)
z<1gP<o?ZL})Ss<T3<IC_+gmyJ)Mk$ko4@w_+s&_qZSS$?-)?(^HrqFi9dAWewibb)
zEh8u3zkFV|nA{TrjPD$0peJ7sqc0ZUzN1b~kG+4}iSZn#hui}zZ6aX2kv8K-t1Wiz
z#*SPN<Jz?wzx`T1<^1qB1p6Ifzv%ry#|6DQ_nSZXwbC-`E3GCpgTUN=bH>_A9|)}D
z{Pf}3;q$^`*-y;L5t#c7?#I(Z=Sk2WGtPfB+H<3OO>PAN<8HMQsaIwvc_LG8*DKR#
zvwu(s80Y5)h5WT&mz<9&=cni2k?8N`AJI6bU(OQehn$`f=ZCzS%&o!p)_|Ycc*ISx
z3v6(8gXa9iExXudnm9k4AV=o>V3+lX^OM$%dttf7Imi)z&7*BAEVdesB)jsuViW8F
z*J$9j+K}y1TqD{=f1i6d#$dvp?Zj;EtdRGzm($gclT%I)Um>|n`AoVmk7?u@U?-1K
z$cee@p;GNmpnt~sX)mmi)1&N8{2I29^Mem(&=yE5NSq%w=^|ZZ7UWOo0BMF_LrxDg
zdW=eB1-#82YLWAUu5odwD$Y;rtTyqkFe)C(lufZO;1X?0U85<iWX?~#Z|yo5h2n(}
z5@-PzayX;}Ig72HBBd1tUxrZuxi_(dbmgsZz$XLFabz4eEIgV;4X;?Yl(9m`_PkmU
zC2?K0Q}K}3^{k796v#CSj#4V*{5<=KT;nyHn%k&IG`eJJ?x01*1{sli<SO>4mSRI}
z^QsG?V>R0BDXJozA61VAl?GR&D2Q1UgVf`hUddMsWpFVlD)chEp4Q_~`dyJkP_c+O
z)$U?YYznnUqzyP_mY6TYEB7fHJd4AHFP*+TD9#T#J>=DZ<MVG$JoLh;3m30E3|>v;
z{0OJ#iA&$VmmHuocMGRSbAG-Bjt_V>nRg?c9>w{2?2fx1*PI`6dX9}aKYRE_M>XdM
ze50e9^FvP0JtNM~<uiG0*me^+E)P6kI6pTPlsXmY?;Pi+H@C?xI86Tb7Qesz%w~^_
zueBMQZSR?Kezx6Sv#%mR&cNLJvW_&VMFfl!(qhy$+8ofsqZG#XvDcNV37sKeoS$|A
zN^Zd%=cgS{4yUDa+ychdN}C8Uc5|_9)2nW+4%#zvK_+>AbhpV3A#mPrHkNU=(mn#*
zZ$202_B}j29vF9^uUOA<2N-KBeIQ`(+dkq*FO2ikPb}v+0*tej_7O17Px~><9_;)<
zmgIjfq0}IdCt{@!1dQ|3M;z(JI?hi&-c39KzlQ#1PKcL}DQ*G9LGBH<5^K(n?9A1i
zA4~`s%tQK89-qSbA+LvOc%aV>ei$%V4(a0#+RFJU>&n{L;EV|#gLz0_;u>Yn4_f28
zahaT7Xh_STZz=0?ZOJbLEo06P8agjMbAEcx<HMKbl+UDJs^rA9Uf%k(kq1H7dhl<K
zvvk*!+S@*4a(eFhiQ-Eb9Aw4$i9LQ1`5-$a&5Vo33{oWU$?Zx{fV6>MBVG8khenT4
zsifJ<-4z<prAo~$6jUo_W7w{&Ikrg@7n|x7&R#9Q^rhrU>F`A&=O;P=b5fok+CrNG
zQHcwAR8fMQVM1bP<dM^SIxddO6Y{W-IX?m&AzXMFi94tiFXxcgb*$2^KtV8~T}tw-
zIiAG)XqU?46Y~qPKNWI*#)W~@CDW6jmcF~vCrHqhSV9)kHCk31>qu$ywWp|!Hme>P
zv)7<H6_Oj(2$cjYgA_6pit`g^Y&J;xXO=An*QIMn*BMmDWwUC_8k{r^zKpD#pV-7v
zQa&M{$1c@|K{!2%^ON)VRL&1MJ(crw<&iVT!J~OG=lOa5J9n~9j*sN|DS3P{=jXxG
zPiW51^ADZ|pQv(v$T!lQpUgKZd44Wld8_2{L5`u5%rSKF)IDR)&nd~{Q#d~pz7ZWI
z2j<V;8#zD4@s0)K{B#`L&RjEINZSFO<AoSstKHZd=cnD+?Z<NC{Okv%cE?zJ+l}1@
z%Y$ww=jZ5sy2a#eMS$D_<NR!Ebmr}1?B4Kr854?RLK6tgae5eAD{Ue`F34PL+w|)2
zS<N^a7o@wm2YAGz6z(_wldqPl2@NA)+<}IJH!<B}IRT{cs`0lP58yt{H_p#Kf!gw6
z#s%5(09_;VEY8;m$RDs8%j5F{4!|{D{{GL76b4;0{+33gZMk#KPkr5zSCcqDKmQDN
zJ>zE>9&u+Yw}EmGY32OH{lM6fnm9kJGyyXr=Vy{n2YZDVa$o`{9fNj<Lzcj#xLX?g
zVH4-4tefmQg25xskK!6}_b^mct`U|}`Gp29BYSqacCw2tES2*U>%E_i^V3X(gSM2M
zmt%ihT1I`PwPAt&&2eHHc1=ttr>AHC*2RaMpPJ|A+VX3lnp_s#QgVrTd~hr9`0&>S
zL!8`Zcn7OpG8=arG=hhOvnrnVs??R6BhLuhoh+Q2<r+#JpRrB8j>4@+6jJdz&JPSn
z@jS^*QHDisjj~#}HBQD9g)+hOOy{U3L}hG>YS>fP<uY*?JRhs!6j2i`$qENwh9$em
z>Cv2@7!8@8P8_I;Q!>P?IS>^puVq{tLhTVra8hm5gz^gW*TnA!QI(v7k|}0`hiXuS
zB5{7|@MKVK@L5P#zCv_~IE9RZD}92)nq|{~4LIcKJ`3^cc!>skimI&5ck}?%YtB!}
z<C8c)s3UI=cr_`{PtD_#I6ugxqd7k+myU3LP9DE>MRR^oKLw6Y<^24a)GOzQIfOLl
zN39(>Kf*UEoS)|-->7hY65ptBe$v{kOP-&M2RSgz^V4w&+Bf?9Lr>|JzGZR?EYD99
zF%DBJ8M}{9KlY}BtiF{97+-5E!?JIq=J;BV{N%pX*uX7DfN^}}>sxG~nYM2P=Hh7Y
z*L}md)dRorOZI-<>HtlQ`|i`j@I`K%v(h92jNivU)uicWG!U@(wf!>S_ZEBqwH?E3
zy?sB;Nc4NPzbE^N?cDqIyWi`_&t5%w^K+X$d)HrX?z5g(2LWRK$$z1B`&23aA3mQN
z<p0SoRmwld^RW2uWAvtfJNq=S{F^%d!vw=z>Jb%rSXNVZ43z&~r<FpQRkm6<X;7<)
ziaf0RdnOK3|5nc{tv9&%1zN8xkcMS7gO^sd%^<I|-e9#_RG|zOO(E&aYEWfNuKQ=H
zUH(~qOGM34o96-BDDP6+c^7S6!1e{?fy3y>lD6kzl%XcZ=WJ5LMFUm{E^gRZaf-t*
z)CX*28I~S`$FQtM;*++Z3{X>63J|FV@qtlP<8g?AX|)qn6EJ|oxH8qqN-twD{YnO(
zFMegeu@e1)O7VN}5MIXM2v77o`vo=8Z>&VWvKrK+FebnK&0MqV-xUJm&nB$ucpzFR
z@qWPwp1{GjBRKe487`y<@;!k)zEb$wIiH6)G>IAy!DC8RBd^T!Xr!7S#vyMbs0a`P
z-xGN?ht*sj=Fv_yX;^%LQ%x}#t4B*tq}6Ug!x6p@)M|c6!vfj^<stdyAUevPM^Zt*
zhv--G+o6HO%4*8s3J?797)Uik;DO=M5=@PLCBHp-IV`Io=0_evBc}>Hv<bz@87H3v
z&X6J~K;n!tOk86_9+uRkVO5RT$APpjez1rTUEI4`99Gn%VbRSvab&O<6;~5WLQ<a9
z9Ms_AR}5<mA9T8;_n-zVc%lkra8}8f{Ev6$nwk-tMl=4-?F-4SeFB<?6{C~ES<OBG
zJ)c$-6)shZ-}CTbbVxIzC3vy8)F3K+s$@0kWm#WuX*6T<SKr`Zj^yVOHQ|tv9=3Ui
zCk86TL7RD8$io~e$8e-!RgEmjHy%~skm&&`0>txqHLk?tSRUrldjdxq7T-?t{&i^N
zN>qU(4l4!|1+|(O%wYlTG`RTXARc4g<KRl!@8nl9*rA8Rpn^v+IQw1v@))qj;Nn*@
zI1fv!xliAPdCFkafP|dW{em(_vp`!c0%Wv3+Lqdji>$lUC@xaYYWBPc#61iM994$V
zc4-)`hL#|$`6CV$ml}wYtd>`TiaIQ*DFz32N|9kz&0d3}UjlX=CaZD&Xf-y>8;sQ)
zN1+shS)rOA{paelsTj;&E7t;nbD!9(h1gqpbr2x7bJ)K+s~!feKHT*mE4FW6edLDM
zy!q6xUw`(7A9c6wJahJj<=?yQmg|4x{C&>f{FU=N_qppn_m$hv537&3<(pso#T!53
zcCUNw+n;^Y4a-kIb<6KA-m!f1iQ9gcbFbTZ=JxZy7Ovym&pYqFGVHwl4IkP4ihpK!
z!$)qu{>{5z{He1yyyoBSzWtfi4X^q1@7{9#;vJud?!2x)e@pnt&AW@dZni70o9)W$
zX1nsb*{-~9wkv-$)93&8E`DapM>GBomp|oS?xPoX9>*62{^piHP5k)IBVB>#{0Z%(
z!eR2KIf#_fP;P}~T_4-irPwvS)s=Na9G@=5uGgH6?b)th+<omoTHLyP(=dc5>GLhG
zUwr8PaDKS?*7M8PuReV2*4vR2=Pl0f{@(eWTbIilesA^ciRHQ7cfJ1XTizB{JNKP^
z%koXDog1IL{hZr*i(4K!_qpALd*`rPz2Vowx!v9C-f-j1KfJs9$xpsz`I_I~x$)Ky
zEq`(M`WqLEw|#E+mheu0VzGP6C!h5956c^GUbx-YKU3DtcI9=mU3uMXS6(;UmDkO7
zeFL8T6M&HIO5WRLOA%nacJAF$<IJo*2w1%KK(f^hr@vzFuY(4NnEl_I4m#^_k2lQL
z$A9j1^qu?H&#~5a5cpJm7Q-H+@A{2BP0crO@8pjiZQhMT>wxWjZ9DW9zqaGYyh^rr
zx$PLvS#No>=Fn-s&*IyD4Cg%f=`akRx^HfT^=%UZb9vD$Khriv>R`4oc9x&%V3=*o
zXp7ypMB?CfFrSva?+%VzYcm+<^S(8!&E6>je2j#}af(X2b<4lhZtM<Xx#dke2wK}c
z)?&Hc@i~ZfmKW_HXtg`m@@cgjJ8ikeQKQj~9N-C$QkY9?=MPHNgoY7dEMGUyo7S*5
zhuied^P=quF8%$(59sC{RB)vHWV>#2eljvg0|xVm#G(bJInZU@u=42QF)X1EN6t@%
z7PewW%$t_-qLsX9Y2C>7+!Ym~hD*q?!g)0uNp|IRvBWM9tUHhc6|!BEd~G!^TCxkn
zJ1ar^!@OueK8mmIZC_sg+GZc<d#~l&4)3ZN-&^;a{`H(!tk=A0H7{Cv1tJGoNFwv5
z;lp_mKigB@wA5EFyO8iv?{MKKw0x4wlbtZlrzc)Wdpf1OXdYEgMai>wc@w~_adD_7
zn^vW#+7#C;9kQk<PFiD6z-5J@i`=CqMDbhahv7?KqKt_H?xIq>&|L#9;6hFsaS9@c
zt)3z!vCfxaq9(hTCQvzt1)k%`IBZyWG>aNu0bD6#g^ulcwIE93x@;G_^17aNv5>+}
zQNtR_BySp8QZ%HOCn^$+E}1HIoT#eUAR}^*T*V&MQf!EAUUflqtVWwXMOD`31FQY6
ziXw?wl!8>_nO@0P3}tXJD0=8+cs;Ghq4c{ViJ)Q;ajM<Lpx6{@k4PJE;#Vk^c%~#c
zI7-prcxGLSOV@Z|ZnEL_<B#UNX*n-i$(wdD<weVR(=MKR@z{HxxK#6|oszt0AI*8w
zz9sc%bKbPa{^Da_IQIU_XL8=O$L_fM@nhe7n03jU_R{-~KYHxsi+7$ZdDD(xih0pu
z-n7U5^*=s}`stG?ZyMG<`qI6u$GmCCgZ8WUVC|YW?Q&WB!o^cJF;Cc^zjqjN&bE>B
z9aiY?VagL`dC}T_5zpmkVr;FniGbxzYbtI*TT9Ns2S1}*OzsH*<An4S&Aq-@eD`9~
zQ_D{W<NUM|PjU<9I6tlUaaiq~;}$TsR@y{>v73u+n_e9btBv#1Pn^&D&Au?sR+>W~
zz+xVyaKHJVe6>_fXcz(G4m2FRHKrSXYYiwJHre~OpP(A&r=M8<(Hlp;1YKjCt+bDT
zaems5VfNt0@%uG5%auG4D}5kfoS#18NG}c*=Lh^6&H3^2Qw+C&;vn}1TZuL2M|S2W
zZjJ0o#)N>uJfsi&ni1!RydJ9Ifj-BLrx+}U^l=C6;FdVZ`6=tl+Pkv0$6y}P$F(sb
zbAHeo*Nw~UCa%$tmO<ZA*5%r?i)GCDk*2Os<h_hJUH!OA-+Jb~9Q)f6s{n~dDdfbo
zUgkJGz57SbPj7{so)PEA!9&IQiT?UU<b&*xG&3$9AJW{%i%)J>dIF>k{2J-Pr#&=!
zj7lZVMy@wBpi7m+GumL2!^p8sqPW;p6$OZ^B{@CG+|=dM75AC*5FM*9Cvkpg3vCKq
zCNAVrMG10-vc%BHBNexXYNA34fhTb;D#SS|l-1DV(Vf@L=!CqkV;@Hb3Pp{QJlh>l
zQK8uNoAvJ*a()84b0OzvT!@S=nVtl-G}V<p)>NEA>4*Xy)MXse!PmZ`HrlLuWXxWJ
z>QqQ>R1-Yo(m^_Kj%pR>C(hVxko3<iTMUkhc+QazYYnR7Ch((U4Ne*dU*=ZMPi*2S
zDWCWnFHU5hPCOKOHJS5sBJpY-yW{w!$oUao&BNf`uzvc=BWI3-M^iXI&wuAm)(ht+
z^J>7uiM*Q!Pd}kKKhHmS`m*NykZ+_pKbdb-I6oJ!ymiF+xp?ZHG3V#hO(V|Fx1@e1
z^Nr{uIWP}AA2~m)_g;+i(|d&b@y~c6ZO791T5ZQ~ll9~b%*A%oJZo<Q0po<U5vQxQ
z(&Bry$h9%gI6rN~iB^(ZV4R<J;-xJ$UWi7cJ$a7P!`NDB69MD=v>CUl)r{jD=Vv<J
z>TM#x{pJ?uHe)xn+PDK#MB1%eEZdFUI?Ii}wGNg3+KltlM@)?i(nlO$&I^n4%OTW8
zKY1W?oS!zlFe@_xb9sD>zm-vH|9WURKPjJ1=KS~}VEb%90J#N}2ltRx&QIKpiXEvn
zpN>oj7|a8^l`*(-e$W#0_+SDjl{`KeEX!c9?3hlRpR#VU>xkQ&Ux>Shp{8<;u$1B&
z4R8b{uAA**3rpqv#Cq>%<NUN4VRBx2<}=a1InGa;QL9$>n#ZSlxK|o;ey%OQ#$!3&
zF$zIpSV|rr+zLEC{B^+)C$|{h!D^Sx#@z;u;QZjMis!v5b>-&BGlF&}3+HCJ2I2I~
zaen0X<2V?K*KvMeIEv?Kkh>W!BhHU>sC+uSpE+s7DR@eBj%q?w#wJ-!dg{7dCJuvD
zV>O&2YN91s;o!@#sBm|Z#|N#%Qx^_Y#VHwL)*R>rmDe(^4WagkBsi%yYC?I1`D^0$
zgQ!Z*LCF-e!9z7DLXkK>b$Bu;H~1{1>w26*#=({0g2S3+(|`>)<mo;O@#=Vq278LC
ztj%|n^Z3v#mXgOO<@q6}M{|B^9-oxwC+G1=oS)3A$()~@$LB)I^ON)V6wXh{<CF6I
zB)(DM{3yOr<ov`uKAH1V^Z3L(KZ$QtI6sMR#JX^P#7Ueo=O@>DzZ&PK_XzjnpK*TL
zjitq|-PqCcIZh8b16JBb;8XW)w%_8r8JkvmEWWKo>gw#Ai!V7pR@y*-+ydkLv=OVR
zm5kjSZ)7^&>f3{W#cq3IaW$6Az3<2svC=*Q#`$SKhS`HTP7k>SR{B7|cp`nokzQCV
zEtdTt(3dB3{4H__thA4SaY5RTVfJ8-3u5orj8fZI<NUN8KW)9`@zH3sFVFF}$O-AK
z?9KCn&7g|&!(2WdTU&X^M$wc{Cv$$#DidTQEc#MD9hngOuw7Mgev+EP`N?^FuuR-R
z%e7_CF!sY@7j{`UF0;&ee6n46UCfdRNloSaD6Y{8OFZ}P0R>CMWk#E24@Z3Ie=Owu
z^jdn(^FvOIaemr;<sK%^Pe@^^oFDQWD(7b$MSoy^&9E5wkuP@)+=x&d4#oLlQ!P9A
z*bf19e(+-|ipNFSByH*>T}i7n2b?SCC$6c+Lu4MG%=v+C7kj;20&hIL{Ww-RJ5Uf?
z;?0OwiR9Vtc;c|a`AHMdN;RlqFeS$tJz02Mt3s)<Mbs#Tj%|6hknI`<&-QFrT{n-M
z<`)`<3FilM37Rf+AeCxrZqYWl(ijDCv9^UOiWCv6jj%Cd<)tm2DQ?VPBjXZwQRaE`
zvYy=qiXpJd5|@pEi!E~INL9R&DelFI9t8%ICO90ih(T3Z$nEL61_wRD*Gf?v4OTre
zX0JiFAAeMHerg_{nCB<w@yVPY<kGpMIX~dhyztQx=O^Xy$$5U>fBDRa^YhJzSwDrm
zJ~7YF$rtZDsW?9+k59_;gZk-{iu3c*y{s$F57yS4AH_Ek&QH$c1HO@PekxLt^P}rM
z$mgEg>;*YLy_GqC$vv>rCIZGAX)|uL+G5vk?7s0!^PHb{J?qnQ#_Nl=ajKc%TD+PG
zl^AOAYAasfecC<`+ltuOTE_3=pBlGWtsMj`e(l6+ou$0r+52xDGTYhq5B{y)@3u2C
z(W<}s-e&6<J1g6X0An*3yY004a9G8Al*Oi<Sli#w?Zk?fTD&Y?Z6VN>wf6q9c(sK<
zTh`k9%i`4*0&Q9Q$WPjDPHjbOv$c<WeQ#ghHpe)ll+C9em4HJRmnyP>Rd>ja*-^uE
zH>~K@^FkTEqqfGz#%xm>Qfy*9Od4IPQ}<+E>ZzBI#H4VKO?9N+t{YpaTNyH%8}vlT
zZc<m(qQa-f5Td{i7e(1FoJ3ysxaD(as5W6g@hS}GmW<=~{wfY|*vjk%=a$RQ;aFlL
zy%bz_cpzKT0@HAKKkVWN?1q+Mb$&H0R@fNNxl8O{UM|r}h*5TSoE(n3%Q5#!7{~+D
zRx)h`wGb8yt{E^nunz~yj>BZ<XpeKdp3ZS54_dOq+_T9hiS;rJ0eX3?Rt}Rft=P1?
zOE-87JC0}iBQ`-Jnwc?5+mu{^PTCYWBhGaLY;pr2pigl!6s#~i+O$|eE!k|#fXM+T
z>UNl&Y=Xuix<R9Mcnmuk2k2dhZqAdrfCsu|F0^1OXM^>|d2ncF2YQE{cijYYJbHMb
zi<OiDV^`j<5~s5SZh@`^Oj`~CV|gGJj@}K#3)&Ei*bx$F=p$bA3zHdtDGXEu4F-J<
z^UlfKFrX@BXU9do(Jsy%y!3F*h1j$}9ePvz*{S0{xElXqxF5ZNLoh>LHkeGCq*d00
z+GrEq5YW&}e~8J;#6Q|Z!)T6^c>$7W-+^Afb{x()i5nhm)XM{tvrS$U49kGYoSWi5
za30}htGtY3{6#OP;E>peZcOGp=p7h;uE03{!xtb#4I+3s?>PyCT!tmcnWr6*oSfr{
zdR0l#*OpL3xSiyzSI>p@G?YcoK}0sj;?gzGjR2&^$tCMebF(j5h4KfGZkWqvu}SrZ
zByYA!4Njs@*ASvGu_^V+C7ZqDQmao_Uh<mRrUyT)I)joSru*x-(Q3^hz&Nh^9@U&9
zX7Fqr?fu%v3&h^9eZ-Mo%zf_K`?Zfa+xxYTINJNQpE%BW@~XXG^Iu*wi^sowX9iqd
z*FIK0h+@Cr!C}7xU#)R>e}Am`B`b!2Az%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cX
zAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA
z7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}
zfFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp
z2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eoj
zhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~Jg
zU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?
z0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cX
zAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA
z7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}
zfFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp
z2p9r}fFWQA7y^cXAz%m?0)~JgU<eojhJYbp2p9r}fFWQA7y^cXAz%m?0)~JgU<eoj
zhJYbp2p9r}fFWQA7y^cXA<!%WKRTQqa(UZg7<PsapS<l>_qJ3h{1oM%yXUrd{qoyb
i{h7Dp1mS0XR@(p79q;;O8J?Q|X>8sdplo>0bN?UP;9jZ#

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sld b/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sld
new file mode 100644
index 0000000..70dd74c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sld
@@ -0,0 +1,9 @@
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="st_splitter16:st_splitter0" name="st_splitter0">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME st_splitter16 HAS_SOPCINFO 1 GENERATION_ID 1719926165"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>
diff --git a/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sof b/FPGA_firmware/sensor_algo_qsys/output_files/sensor_algo_qsys.sof
new file mode 100644
index 0000000000000000000000000000000000000000..c4a52353838130053fd4ceb65b34bee126612d3f
GIT binary patch
literal 3221332
zcmeEP2b@&Z^`51R3fM6cy`m^6;)05xq8G4NL=iiSbOl)j6$|ky*4WU*Bz7!VFqXs~
zjjml$WBJ=PioM1XV@oXm`_0aK&e{9kyLV=1=FYx3$KSl2ciMN(ci+srXNFz(*lpVk
zq?>-!Wp>iX-H#Z5`0OKQiBX47n=wg@oH?U$+Vn|>i@hctK5N>{L&d<M0|pML7bA|C
zHhrQPylK6tAG+b7K^qRLA2?L(v7^{|+U!YUn~BqAYu`+}%yK&6!1`S_so#3|wi^%G
zc;w*iw%H@oKC_fok2!SqwAs@qP0Vbb_1bx*ev60wdeuQM9y{j3>*u{YHM4xCL3{n&
z{kzUT{G64iaa=m{Q}bEuvGaG^={PO*IBeCl27V|UqGW|kkDOX$gnm|+S?`<mGHYkV
zih*~t9mk22W=)%N=(wrlXH6Y&(6mFfX7}H%`K$R0#*TR8Ie4Eo_z#mancjGs>C`Th
znR&$Q#v^8ro2>bpwc)Huht8UL__*=Yr_3C8*sP;x4LEq>w9FQ>rcWH#c=*hNCry|=
zZrY)fXKvY5h%IsoJlAJ{6Eh}mGH&9uDU)W+9yg@^pkci?88~#KK?4VlA6h@Yev?f%
z9yDR_#6i6`%tmjR7rq6s!^Aon&c(z@M^2kCX;|-;3)5RPj-NesSZ|}$Su-d17DvpQ
zbohjs6LnnuoNaRwKoXd2Q)p&Zt^+iQb1^lSfA+Xpjnk*io;~UCfrB^GEd^)wy~Uy9
zXJ`bXYtEvJA3qEH&zN-R>~TkqpMJ!oT>dOeEp1}<q&c&P_1=AtefAi)>+oH+5qT*G
z4i?)F-(%b!yNw#T!>-%zCI*V_w%K)?(Zl!LVYgk!?Xa~Nxaq*5LkA5WICzuh{;~iY
zwnPZgw`d%HxUO1vGb_6Sy3!4UmYY{3IMX4`Cc5PL*Ug|h+jXOp#auUeFxirW^HlO)
zAjjwbIB#;MZk6n7^KYFq8FD!cm^HI;0<O@^oQwap|9-Px9kSwYJ{UXog1Ilx?XqO&
zksI#x;gE)XuYUcvyWD-j+%Njxo|$px&Xb1j_tTF%{&m@&v$`*J^*g5yzP<miFZsOJ
zM;~7N^t|=gIDXe&Uz~L9sRtZ>(b%pFw~!AVK4a%?@A&?NXYV}bk3aAI)R>LmzWnid
z^Zq;a<I$bET)g15dmi0+=En_>^cb`F=r2w?{gSC?p0WA^oqv17Yd?(r@xZ6Y&RX#A
z*Irm@>YcOO?eqK!eLr8iYv21eIAN<_ZTVHd->yEVq1}|G!<U-(r_9vX{`BQuA7*ww
zWpumy*8gFt8*l7=*GmgO+4SV+UK{bz-xj=n+^EHC?6~PpyNwyJ_^|nXPN_Sp%Q`py
zYxBq2&wu%#<(J>$%LkU*WBZ{K&+d29jor??@%tS<nL77{sYh-;`IZ4oRM(4k+5PKr
z-*s5J+uB!-_+9<RBW@l2`+r^W;0m*k+jGnt>wW&_xIdo%?_C!5y!EsxgRl5*saIZD
zbM_W{_S^Q3x0mZZf4?_x9Q5&5>ppwQil+^Ga^@AopPeyem9tOj@X{48Ty*pU2VK2q
zzfPBrK6BVRH=i-<_0`U*|8V2`y4|`<r)O4uZ~cBJ{QTs#A8fY9$#>p3_mCGizUA`U
zFS_A>BS+ow!hPqDzVh20hHdmiPc`LFOL}~|<8^cQSakhan|}Vr^NTOrc-Tto%sKmi
zUtfCl3tN5t!heTP?t4wUZ_oSpb{EJ^?>uR*|Es_C-qC{(xnaW}#@+GF!|$Fu@$Z}L
z``NGd+rQtG!H<mi=%kfa9=7JM$4r=V;k2RWobl7!Uw(DwUZ3Co!sHJYyt7uHKP<iR
zR_FZdzZc%P>MGOjp7hkXmyaBL%mXVQ+_cn@lRK}zr|h?Itv!Ez)Q)HM7{215=SQqH
z^{Lrg>~rGJOa9jF#I;Y@Z1h(fFBmy}^ZJ{bx|}!ajiYCrvcaqK)?RJ1dpchD`Z;Is
z^yI<=|N3<A58l7-*6A0F7<}OQ>m0HC1&zNxdgX_^_x`ry>yNC}`Q*nN>u!B-T>VSu
z9(8%&M<3}j>OT)|xBAGzU-X!8-0wTjS@|D*I*dGe^k)ON?>}JVI?wFT{fJKg+Wdx@
zN3J&csD}S^I_1xud#^J7ft5cy{fAk9fA^vp|9Iu?OE&oIm0Q=D&~3*DzT0fneosB}
z_wUd8`MRb1Za%*6w37xtv&rhCU-<8j?=9MJSmRwEfBXEatIRm(fcg7oZhQLRYp%TQ
z$aZ}fuB2Z4{HXu^@%rB!u*vgJ>_2S8tgnu}<<R5axZ(JrXJsB(c;AMnY&>HA89$#_
z_xdKw{`1o>&m3{z%r}oX>eS1Rn%3d|6+Z8K_Pr17&|}MEckeRjjQaiVx%RW?kDRi?
zb!T3E|AE&Ya?A~He!A+H8@+YeiwA%GpRvo2S?||Z-gfLGKi+cWocgyeKX8Y=j^D1`
z_Iuv4`4g{n`Nx8<7XIIlZ|v~SzWa^4_RvLpZhHQrDf1p2+x?1>Q!npv_Iq1wyWxrb
zAH8k$T@D<z<@;mTdrsclci6HA?l9oM+tqbXymxfw$BX~A`c3`UnEd!LqxZVtp3GB+
z4eNRPah;#L_K7QY+(7L+;@UYkJ^1MO3(pvP%W=QG_v-HZo-${twby%Xljlxce(*<I
z{O5P$R`_tpEq|-ubgB6>X1}rR=QECYbMVhI{yAy2{qOwv!L|R~Z?%tK?0NdwgZDc1
zj)xj%yfWjH2gWU4&}YJ9Ki&M|*5|IUV5iUSx$^!Qr}de#&pA)4K41Ut*$G3x7{A+;
z<DS^=SKHii!kVvt(RI(0`YbxH-}z(L{MF9$8b-}H@4Ba-zI&UI&%CwO^jrQi<m(g9
zSa9y)$9BBp-7(i5GGwKfMAx~8v|n?Z)eqXe@9#Ig@5sI<UHZYkf7)=%yVu#`s1M&b
zZ}P5BwA=sT_n$g#ldA_DHg~sMwtMW16K;8Zhcy>WSo+e<Z@csH`FqUow&8ys{`tNq
z);vVKw8@y4ZoBu~17F|g=6mKh^!wv$f4P59uj4LkT(#@wy&Dc%ew!!0-*4I9e)rs3
zSN3nb_uwU4O#0hxnRO?;b@`G9UikgKbGmmKbknI*XG|XYW&fcEj=5=r>-RY2;Zv4*
zWBgLvUAD{W`%me<#plnh(0PT0uS{G#`OSf=O?YnJi|;Ic_3qbSU1s->pIdU)zkYw$
z#-|*-`KDiwc;S_$<_>=7`3d*GeaLxF&)N91(Knv6_wSG0Z042|)_d!$wYIL?`uy9z
zzI)unF}p5#`qiHQe&_JZuHAjdo6fj;(4JercE)8t+}Gpl`)}!Y?2B(t8TgmUfBaXU
z-9B66u+jhgvi+Ry{a@;L<W74{JYf5CZ`=0|z4n_qe)ORC4t#yotRv<g+4yXqg*Wv3
z+lx;RIQP;;Z!dlFzlPnlZvS_>&D;Li_4@2}(q}g;)BBt2#+-io>*JO?_r^<iK3Tr}
z#_!H}{^x7&dg73Ex}Wsx;h8(PTz|&Znf))@x9?hYgO(RZe4!7Ud@y_4b`#f@I5d6L
zs1JSS^vjwrSzC%}>vt9hUvk6RP0MX~;I|)S-u?8o?bU<*P8+#*X6TPwZrt?N!Mz@A
zzx@$Mu26UC`m=_t(Bs;_p4@fFh|}BOsm&`7YIyY1YbLk<{h7-?_Oi-9+<Ehu3;t5K
z>T2_IhyUGNw|JjdGVk3pU7a^zu-u{hY6~v@<Fcdv@nEMte>?my{Rdog_Ery!p515B
z3y0je+n>}bGauXLw=;hj@?5*^-@az^)9Rm`Jgd(=Blei}%t?2=*z3TX2h3e>@mFgc
zdCsz1UZmgFFPZgR<NnJIS>e8G{=8`PZR`It^WXh%d+&oQj(=>%o*i$yf34l;tb1S2
zl`eR<=R5s>bN>I1dGU)2y4<_;XIFi&c%!3#cf{Hs)xAIP^D$5U^}CY~Jou^JADuUL
z@Ds0I_V!gTj=2B!cE?<`!7~eQU-z~bzOK9dy#DWX+-LpgzwLSK?%yBq;mn<eJ-qJ4
zNB{Yp+rBz`%lo%F?)h6!{%Pcsw_La5z-NDd{fh6rdC`sU|I~T$bJwl?hwKf$Z}tYi
zd6!J)uyJ~mz2U5*51l<#Z`<{=U$&V82M?Gy>7XN~<lXV#9<s8&<IlP7H!sgUZQe%z
zoIPl#jV3j%y=VLJ^&egO{Fb90Sb4$eGmf4(bOqe=pXxLCrK?vsdhr40AH3fm&i=<y
zXV1RstH<yB=Cw0E>HGBj4qc8NxA?++`>p@XEjOQa&ntiY_k-8YJ?wy=Za8q!st0EN
zd3yU(pLz78^;U0u>yL-aM^E@%?6~H$izdCd)X{_2-@n6(e|v9}3pQP}*IrjQjF|uR
z!XNJbe(E1S>9g>go6cBz;aR6IJ$3Y$w>CNd;}3rO@6V6ieq_7fbw1(k6Hh*9{5kF3
z?bmesa+4M|?LL3gm6m_`lK-yp-rK#;J$B4p|GjpvEw4X+{W1Uh&-Hu#c-!a$j$O3T
z?q|2(;EkQ{-{awjkNmJn)?ND4=3id1?(o+i=zP)%lX^^e<`463xMrREhd1qf)oV>t
z&KV*WZoA5sf8OuqF(*8@SpBNu&4d1W`IQg6e9WR}-@W0Ty>8p-*%LRN+iBM>pB#0}
zeUsk!Xxv$^PTI3+jaTL`m@@UHYnqm7_}8Gj-aBVO=Rb|Qd)FNvyL9cNMy%eo$K9u2
zw)Rnn?bdhNatCa5<{x*Ozt3qizB{x3ou_=c+ZW61*?G=JFI;ufK5KT|`uhKDIcDEu
z{`bz;k52yj#rjDP{a>d6hp+tTf{#Bse(L$(EZOUi%boqv$f<8G->}Ae*M9uUf``uf
zO^=;c>~qYV_77j$Z>4d^)xY}0BmFMk;^XZ*9nopnDW^R!;NrSN#`ivI*)Kax=-h6@
zj%$6i&xl_A4?6PGO}adG<wrMvvCrLi-L>f87j`@RsRb9zTeoS|2QtrX+w<M$yU%*<
zqrYCT`iZan;jZ?>e*58x-*-H(-^~pRw*6%F<1Rn=nso=vd}qz0U;6kr4ac8;=ZZhf
zeB|c;`}=*vp38iB<z-XrCO$a${zIoc(_zISbG~{1(k-5t`tIf(rXIEYR<|u#@#upd
zyk*0+Uwz`jgWI2a>9UU<^umyn_y6l#pPabL+`Inr$zO+mxX&4L-`aY>ecyNZ`SIJ&
zo_pl1CztPk!5ZH+9^CN2-&Sv!{GWTaeX#G+ceTI&xMkJ6jXoWB?#{EiwtuzZ%H!YY
z`qh?y=zI9(JDl*z2Tye#pV{v8)&A7|PuF!;Q|>x&*U2Mq{p&4@FF1X(4bM6J>#0kv
zddv8SUmtYf^?g2`KKYA#9_l>%r+qJc=Jab`*r4a$9d?=1`-U%GfBA&NCf~5$v)_!^
z=i|o~_1OE0S=aXXZtP?Imz{C)jC=bYvQppv3#Tl9#nt^E?B4f_{_BjK_|CMkU$1e@
zvJ-~fJM)~+*VuO6sppDS28})Iq2Xf>`Nu2oUGnSCUir)66aV+Y`SYHu|IP8w+<nP6
z?|iq~|89Et@=s5`{P8aD+`sW7BS+30_WszpZ=LYNqOG2}Xxv%tC!cU@=0bg0&7A#h
zyK5io+SIe#=cj%@=DvmJ{O7o{SHJQ5?~c7@lfS)o)A3`r&3yUHRx8dsv&TbAp591p
zJ7wb8ou_X%e#>uu_3i&2eCD<@#WDX~V~1WpuDbs43m+f4RfoTv(etRU&wY00XK(JZ
z{i?fMdDk<8o_zo2je5?wajBm_xp&w1f4XSfJ_{$D`9{Nkz8ksG79W4H_f1!AbomN(
zSDk(QH<Mpl>f%#>dg-ShzrFX&2^;)x<MI0~`r8I$=WaS=r@f9j`mz81{^E7d`0B-h
zJN3Qnz{~n=_wS=W9(vFP?|%I5USD>cwXkWGH9Ggd<>LO&eSg(sgZ62+??K0mns{<I
zvBUXe{;+7hr+z=`H`_n?>YAfpeRA?XtBic`xDU_%?({)VPv7XOZTd}r_2@57p0#w-
zVJmNN=x3)*dik?^Zg}IhkM2F-r`Lu)ar>QL+}3@gF1v5G$qhr_{otz?&wG5chTA8d
zyw&3i7EXBVt(ym3@z|=*ES&Pj<4bOT=)9v=J!h-T`kVEA>)8pzzPP;Us_Bc@{Z*ek
z&Rw(dxP{N(*=O$wFYdYj!&7^le&X=Izw`Z?`+dGw$K6l9@7!HJIPQfr23#@XflpUD
zefhC}x$&^EJI`DDKa)C*c%XZq-;L^f=ufX)-lId^?LAgI?)Eu*y#MlDeV*+9L}us9
zc9`?x#SPt0Jz@OQ4L8>f_-gCjhU~vm=l@${>)$Q&*ajmv-DSd%^Hw=(x&E`3@BeV)
z=9}#O$XQRXFkr&?bvx|*Zl7llKYG#d1w$U_*Y1OhI{jnTp?B=HWb6K0ti1mg7hZMp
zrYERQ?YF;h=_g)!z0b_aFI+I~wuyUBm&4mHHRSyVE@}86v&BpQe(3%^4}Sl@v%mcH
zvqS&gsp*(wHu>h?7hN=bME&WzPM`bR$2%?h=j+e!w)h|a`0$o~z3a~EH15&6N8a-N
zu;VW|x%=Ywm)!B`?mN!;s>ALbcE4uWEnjwD_51;Irv0OCzX9D(|J6!IAMoxOqt4y=
zrgvZX`&xVTKYi{)NAB^>K|gl<`|HQ_>+#j8H|@FX?U^;ydpjO<$BH}bwd;9*erej{
z*L}b8zt@{EaFsjW-T&J)hi&%J^3M%A@5WEx==j{MNyq)==6RcUzjM+T8~^s!4@SRz
z{xkE=KjG53hmIM%_3AfvdGp3gcR6|cm+!yis~djaVeZ(CHaq8}OJrur{Jn19BQs>}
zmHTh6PV6wh+kwN|ZGX$ItE?@Dw_6d1A9|jBVu#1({juxv3q;+!YuEMOVe_GxOF#K^
z?Ydou%o%oZ`yPM)ym#H%*NC&n*KPgnsn28{z5cMS-No~-?AD>zO;3Kgv%G3?xAm5E
z=yUdxc3XeD`D1F>-!Hpp*=M>AUeM4!{~)GZ`PY0+xAE<7J!(?>Tfd#ue&f4d&g`=K
zV0r8~{a9o0f+JV$^TZF&9reJf%U^NG4mZB>(B<0=z2~VDM_=*Xi|4F$gZlL6M-F<l
zalsQiUes-;y<fU_rIk+l-H$V_e0rT12K;VupYcPk?zHz8Z|?Ep5tqMu^3c&wE<E^?
zr;q;ePp@4&>)?6YT=Ctm#|>O>;N$%s+2_agzWvvqmm9tMabsUU{X6;3BR}c#+{k?%
zxo6XXPkg+}G0$DN%`<&wPXEJ`m%Y9HA(v0xx8LL|ZaApxjHeI2{`$41_t|@KuYJ~k
z@!J)TUGB@Hzn^)?Cf|R%WS>93*>}oHBfI~&(gSBd_4Q@FZ@=i^1CAfG?|pk-wCTQg
z@BY@$w_ddPgK>v0+H~x`cOQAdq5~HlaOiKIyZ6BVZgpax4NqMzb8F|-vKx*}X3JqO
z>(35TChN%MRmXLjI;5<vR<_el=}(IF4%0<C^r+i9vz*i)GIz+-HUH3Iy;T=vXs3U)
zJ1u*b{gF+Z%P!i%9%^!D_~8N@;%W3c*#YQUfR}~UX8nwpHJ{2Zbt6;{;mApsF6~ZK
zLdY&X+MSeH6F+pSE?8jEK_}|bqeF+f;WGCFX>-|?UWwe(?2p_Te&p8@_dLYIrLkrv
zfF02c8yCfTW`G%B2ABb6fEi#0m;q+MGXu(Pit$_}!!rZS05iZ0Fayj0GvJkh;GZdb
zErP+B0cL<1s8I$~jrPrLGXu;3Gr$Zm1Iz$3PyhqruhA9|!>-H#Gr$Zm1Iz$3zzi@0
z%m6dM43v!l$6w|sHNGd<Qnyi|eE1CsFeZWL{O`x$h_6nSegwbqBJtcX2xtS4tSiw-
zm`e<clr=62{o}W81fDqk77Q+eV4WnQa;qZn+%V9^k6(2JCyG04Vj4EaFwikZUuLx@
z*fMv;>6rm$fEg%|0ac)XiQGNGmZ*A8!wh&~KzKoI-l_Y6ZiA@CKw|9y(~vQzXq`l)
zVGz&;Aas%{Y+81Q1!9ehLjQ%0t%wNLN#X=csYT#m7|7U)KPF8-#R!8CY!xHBju40<
z1}IpV0cL<1U<Q~0W`G%B2ABb6pavNrlR<7$vD0A8DLO<V%rFRO0}wh%6*jgakC9#L
zq+x)f#zmq3ijA%2x(MK7)tw}`JS4oa###gp!~g{gGr$Zm1Iz$3P!kL^)I^uuBs0Ja
zFaz!kkjWr7GT5Wt=0`F&VMwKu6pyWTqKouUh$HknC5pNj1R@Os`L>nERws7Zi5Xx9
zm;q*>Z8IQHKDi^>`kAlyOA=0G-=xpU7Kq$a1>Ea04H<<e<W?RA!IC8Iut`~J#AZ-z
z?|XWkxqyfw*9KYg5F~1?n=gkF!rD`%-=mjqaS7Vg{|o!f5InKUGR=-nSjKMp(U^+}
zG7y7mudN{nT&X4q%H>G-;S8IQgH7=a;3ellJi&VCw0a<wpHe)*`f0WxRO60ljjq=o
z#;sH9Bq9xifHnY$*)1W+D(<k>RH=3V*Xb0M&bGKKW`G$;9|Pe;8Q%R|dJI282=1f^
z3NlEX1O|nZ5Cof9stJPNW)(MBYnmExFz9#cIb5f_RZ)mE3=-M^#QYRP!Hgg$F|z9@
zg-Bw6f`u7i2ABb6z+eEMBeF09%m6dM3@`)fW`Ilv7z>@mZGJR|R8x~TAlZ@KVC{L*
z?-5Lt3aw&|oh0gFP>3`P650TS$5ybx!VEA2%m6dM3@`)CKoSE@Nk+CY1I$1&1I9p-
z?5?d+KiuX=b4WEc&SR@Ptgf%-C737`m~a|f`{o=4BJx&6;oP`NB(wpDc{wPUOAL#Y
zEX)8izzn370jIaj(l_r3w)Bl~MrNRL3}Bb!K|H~F=+q0O@PeB01nZ~SR-+mNiBm=o
zV=L-%gLUd4<xaswsnDnMt|aPW2r~$z3g%gflK`Zru`UYc62l@TOQ8(l_m4e@Cs+@i
z`hmnt&x3e^_0TCpG6T#2Gtj0PQ2c&f`1*;$LrM`*0IcK>E}|wC`zjc73PK`B8U;%T
z(u!|ek;e@dp0zH)M5#c8)BGrMj`$farGBb#9xh<y8k_491|c|6gti*lwNB{=H9)~q
zC<7}N8c-U4Pq3vap0h9m%m6b`G6p<N51wF4MjIz;B?COR7D1pYBBlf(o?uH*xsMc4
zBSUf>7(LzQM{`IuHNhN|jH#{eu+~&H;86J33R0pj1{G<L&;}s<Z7bMdVFs81W`G%B
z2ABb6fEi#0%ECY$f7=>4so2T(Ft(y7H(36V@t28Gfi_H|PEzF9YOad{T!~?wI$$Se
zfEi#0m;q)W4Gbv$_kd|wMo&HPx2>LtXV@|`5H+dTA>HOj^Sf13<NR$aigJUsm!E!*
z;EPa&R!clTnyX-F$^nZ`SeOB3fEi#0m;rALC?J!4ldTllReJ<G9SQH;N9zL54MW~8
zNsq0@tvn1uaFP@No0O(DY<Z+-GQz3nn>#i;k_FU}<l2bd8%Y2}uPiKy;tZRZrACa6
zx=)4wIT-%h#uELoOMT9<vvwV#A5B<aEnx;?=%y_pNY<5T!k}!5q=PeTQWCbsG9Y6u
zWi@z$Eo)CzpFDSat#qB9U@P5b;dsU!(VC)3dl<J)M3I|q^c}Q^c2n>zCoJ-_q>urA
z5vOobxg};Gl?<5oI+r#DoXDM2pBr~e2`_SsH8o)nd~G7&V1>11sReuF*2mg-<i$W1
zFkCLO3IdslCJ3@Z!odyJDHS_01Iz$3P<sq4Q+q9Q$IJjTki-DKH)LT3QpZ5#$YAYK
zz=O;w`aF812?iL25QziPgh8;_M8LrcYs*p#b{<=6VU@W@W`G%B2ABb6fEj2@4B#Ka
zu`mP7KyeHdF}CWtQ2@+3KT3F!A=T8lkFCzIK&^Etd~98yDT}-q$O4ATMHXLxZlVc-
zU`Uh&+Uf?In1+qa05iZ0v~dRTPUt~A!FuSFA(?@aF@VjG2PpuSzilmieN^EgrHJqZ
zTZ+;><cJ&@taS)@kU2%4M~^hY0HY8haUhy72o{?NI9OqAS!%&v_}B_oA}@yM<;q`$
z27%ywO}NG|Sj7$2nuZ-B7-)>pRY2tlwgR112LxW<9>f!@hfW!i8DIvOfws*6_GB!D
zF`x=_FO_!zum!l5s=8{+6FD+iixlu6bBaC>Cs1M_Q;$R((S$*;*hIjAWY_0mhQI))
zT9?AdR;4M6ycnXFD<E5fX@LXL1VJz)iqcj$*u*q!jA39@jK0ijPq1a~iqkU#%m6b`
zC<C58?ePR#C_C(5HU_XKV=0gU>|H&GCs+@imH;wxWJt^_wN=1_%qjZZm>(s)f&oV1
zMB+d+VGt}yBDGP#!3qnfT9?AdRxlQMF+?v{{wg#G1m|nQHHN_|Zm`xg?7$2#1Iz$3
zzzi@0%m6dM45X3)mCCLPYASMMux1eOAaja74<}G!AXAS-9MOb9u-HVvfn?X`VTQl}
zr&^baj;$F1x&!(pPJ%VYbE`yNgFyy`aI7&)DjATe?24OW2ABb6pw$d?YIO!qP`eCZ
zPsYLwq>h2ek-^%ffCrgV^tmxVN_dg+!_<U9@U@A6gB8}6r55Zww${QbbC1jbGr$Zm
z0~KX}Y-yZ6QSGPe3wJuf21e@?>NX4#+8jtH^MB*3U@kE%Qr5Oev`<#n%16`65eulJ
z%sq9m<PtdnLU*y{f(1~GOB1N?rXP*^p`8AJb5qW-myTGXADPZL<Ygd+A=(mxWL=4-
z9I)AH_)sVVxDq^wCs+@iRu817UytzwTRptTRbt)|<2*yXeybKZ!OJK7G($g6+$}ZV
zkEM2_xAHIumPB!eP0Yf^w#xv&h}-VkaplZFZ80FxZejDI4p4{+Z;H7cs(F(p_ukfy
zt?sZWuEs^6e?q?tArek4FNSdQL=0r{72=2{41&cb5)LH0J`Xbl1~{=W1Iz$3zzi4+
z)EgRBFayj$O*4Q!84ELzItC;<3MK=E6Bki%B6Es9=dl&6REG$Z!DDN6ECyG>3@`)C
z05iZ0FaykhW?&g+ff-;1ie^9}vaqpLkE;q%6&_pNVNqO-i$MPcjjc*w1QJm#F9zdl
zPX#Zs_@*Wdf^U+z!zN{68#BNRFavF!0qLg!Pq2QPWmIOMGz{Q-8V^zcEOu!u1u}pQ
zum|x3>!H&UKuY9jIjLClDtM5|MW6Gxtze}(M4*g<##RJK99mus;RH$y`HQbkKwQ4&
zmw)05i%ldPNOpa0z`}{8PzIWC5ma70!B)OePl&<~t|wSO%`z%8zzi@0%s_21fSsrZ
z@dWFk(-J^R<Y+lESo11)kU2%4^VkYjszU_IC~R!i7lA}n%ZtI79~HdF;+vW<2)>Ep
z44asRjWG;JKVz#W*ccL6%?vOD%z!Tjgdbo}uzs3lRA!(w3}El-K|H~F=(Gfo5;<B<
zD#>~EMp(gvOfLGo%wwxNEQ+gf5$M0Lu~i31M76va!U>cZ@)w`KZ3S;E%m6dM3@`)C
z05iZ0Fayj0Gf*Z5B=VAh#05yfDSvXod6~ynji3NyhlN*-i$MRC8e1dQC7g9#)<MFl
z<uw>)2n;Tn*oPTl2ABb6fEh>!13lBx26w>>Fayj$sThz*6ifyRCoZDkWS<|&+yoFh
zNtFv0Ks7D`{S*3K2$67Vxhlr|sNh8w-_(Rb@U@AAgB8}6h3(7$Gr$Zm1I$2q83=D~
z!9B|gca`=qKh@XDAcH~*a!<{H^vnpD$gMmGf+11dVH4BThS8wd-u8YG3#g+cB7;Rz
zI5Ae%)JXUt$S%&X_EhQj=&V~Dq909I-)>I*>i>x~92@mR>F1eV%~4?nVpsxW0Frej
znlK1%$>I!~oQAD24B$oRK|H~F=(Ktug`ZM9!TM>o5L5|ga!0gA>%X<H;6!en`rO<`
znKy1j69yq;qPW8*rePy9zzi@0%m6b`UIvVNof90n7w2}U5|M^MKpTM2yD|A31a4L_
zvg-(mC}M!3#zmq3mRlb?C&4;NxPntH0tdqo?ufFBPv|cfEb3rk2ABb6fEj4XKvPQv
zpECo@05iZ0Fazmhz!*rJS~TVq9VHQI7zDHd2%V&OYy~%E5rwSfnjeidPFQuP?t;rh
z!W-GO2pot33KnL78DIvO0cL<1U<TSM1NCjSaITvfs0IeeWRM#flIy}3ZRX^X$w-75
z1_5mVLMN%h##VP&AlA4j^k3N6+Eqsc>m(7LyBGwX8-|j7+v*OBI#`$iW`G$;D+73+
z^&p;LJ#@;D%s{CakflmgSRPNXg%#O`y)l+}5KpikIxPjHF_1VVHKtP?B@t;D1hfGN
zoumpITam}eu65EdKvCnO(0^fLD<Xn*k~jg`S_BS;fsC!4jCBcv5Ns7AyN(cuA_gc}
z3S|Jlf9yd#!FuS_3#9Ubn(+kdr&&g22ABb6fEj4342Yr%_cT9xf-Q<7zd>M%Oa{40
z#a@*$r|1xgFvB3A4M6B5#bYbDDT^p%Eo^L!yBGvg1q&!~Vyv;L5%5EhRor2%sn{Wc
zfsPTn3aC86R-iM6U<Q~0W}pBDQ~|yvboB&V!VWkUGf;5`M8y%afSzFeG}~%aV<53+
z#5811E}3$Vt?sba4pQ!*zX?@nv9Pff5m6U|h&1rGt)Qi%f&rg}8DIvO0cL<1U<Q~0
zW`G%}IR-F$L`^DoB0P+(D9R1iUVgeg^n9bxVa3K)b6o`RoxW`i95IwhoM4T$2pq`8
z2?Yx?zzi@0%m6b`6AU!eM3>woGr$Zm1MUov$sji}*rVO%M>02MzbrB|5?CdMwU?iI
z4}}g1*-kA-T?_(|hJk$B%44e&yRCHMZ(CbQV0DJ$Rm#E)FavFc0f9ov9nn_#e7(bw
za3cFAeNH~CCHGVT_qt3&M&Sv$m4`vFB#Aq0QkELA85G<5o?d4zAfm{%L6$rOiCXLC
z%b|p@_EhQj=%rg+f;REjHiqDdRrLSF8jej^#%}u2n2QK95QA#3tsw|psU`@@<w*G9
z44aUHP4NuiCFemr!FuSldLWgbQar)>Y1S1Lw><NXXpOGd9>%Rx>m(u#gMc=;?Z)hu
z5M&j1SZk_uJ2<hKZVI?NW`G%B2D~y5PL$!@&!wF3BZS~iil88a#7SUKI0-?pnWdT_
z2yRw!gSDoq0SAMAr=G)g%3BqMNW&nZ4M5CKF%--QauOrEj#7vu1}IpV0cL<1U<M2Z
z@Hrw2Gr$ZK!2otLEU9Av+gO$~GC(E+jD=3(Hb0s}s;S8vknG5Au=YIZ_Xs9Rg;ue~
zP7-x7C`1|t32gwvV=LHTVFs81W`G$;F#|l`q;hd9J>N8?l0|Nc8K@8g#z11lmD<B?
zel&+vQ{z0gy2DyKr~!vyqEzVBX>9GAa}<ckTNQ<K<0_HR1|a6;pkOXBEK;&C1Iz$3
zkX8nq-ZD$yyeHVwH^Ld2fyyyZ>0vk5nJ3uF@meyZqL>mTgD)tNC)k2&tPW?T%P<BK
zr_wx(t*FZl)~SP(I|UP^LZ8mNlBkOz%pi~|m}ezU0+61@x+s`S42zU3g))HOKlUJ=
zU_Er|2NEwm58?^dL#GVM3@`)C05i~b8Bj&tu7sb4J;C~EwpFNLDr!=(CpG32ghY-s
z3YHM072mcZj~gsJYh8kgQh^Ak`BCH?@iSaX{Z!#RT)@aRHrFK#LU5u8Z8frMozf3#
zfP$q^239OIpfvuTU`taxXJH1I0cN0N3>39}Zaumu*wz=$8JGcY3@AUyo?!hn+iKLP
zks&!LMo+i-(Hv4uO)v)~V`{5AtTk229i;BB@Ua!7L|qIj(jcJ?K=|8Muu*Oi<p$vV
z%m6dM3@`)C05iZ0Fayj$H8LRe%osJP*lYDLwxTFESbO>D_P~H2Oq2?(VvU_7>S9oc
zGz=2j0K{Au1#@X(0mhO#26$Ohx1`(<Gr$a#h5?0-^;wt!W`G%B20{jmfh4pfJ#m{K
z&F@xCjq|syD8~&psqk8{1rw!0!=;@cBUZs!mvX?OlUf#0%gv{^cf2LCFayj$TVX(<
zP_l2bRW7?~k6@=G;hp=mPT;v=$lE39vDLVhhd~HVk^*3p($t16kMvANIQ4vU$7V;e
zfI5;~8_|0s34rL8g(Xp(VH2~|h_O-ksqjAs!(ZE2q91mt&pCG1u0!;r3G1sR%s>p?
zv?T<|x)MzolueOzaE47v!nRljWUQsE22ZeM?WyXM=Wef+uG152rQ0kBZxp<ZJEAp3
zllCxforoeg+vq!J5ACMlTTWQyuVDeTEX)8izzi@0{unUtbuP6CIFUQ4J~!@`5?<sM
zYihzE_}WCk!3t~3QVaITt&g?w$cuq2V7Odl6$CO9O%P;-go7KbQz~|12ABb6p!OJ8
zruJIqj+uedFo5k6OX?Wl51CT8q`8J7M+R%N0v=>e(dW@4O)$VHgh(8SCJchbCISvt
zSX-7_u=Chj3#-gMG6T#2Gr$Z~ih;hB0%Dv>GJq{<MFsy5j)fUu28v^#h_O}AjRIiS
z`BB1)45_BZeQb4x1!}EJ;bZFpO<Cl{Ko&4uF0%LnbQ4Vw1Vf@M&{j9t#58PV2ABb6
zpp7$tcR~;13D!fW49N_Xi~($hJcuV)51qCavM8ohYf+1f_XJy9v3{fUa1l8&SgR87
zAaja7j~;1)0Y)K2;y^TE5G*zkaInJKvebgT@Ua!FL|zQh%ay+h4FbXWnsAL_u!<Y3
zH4QsNFwhvGtANTAYy~>24hX!yJ%}e*51le3Gr$Zm1I$1hW&nR%sbEnBN0cPM6KqLp
zuWS-96*)3k%MkD&bBaC>Cs1M_Q;$R((S$*;*hIjAWY_0mhQI))T9?AdR;4M6ycnXF
zD<E5fX@LXL1VJz)iqcj$*u*q!jA39@jK0ijPq1a~iqkU#%m6b`C<Cqdw5JuJ*}v^o
zXsPVa4AeLS*t>cVPp}?3EdgZY$dH&<YO8<;nN#$+F+WOp1p|!2iNt|u!XQ|ZL~5ge
zgB2D|H7%N<!pBxH7I`s5FIWC5GzbLeYr-{#!76UB)-)-1P?hdaRvM7;m;q*h8DIvO
z0cL<1U<R0hC<Z#lOe#^nL?>`Y<`jJ%PN2j<rk>%5BbqP>7Mln-knH+A%n%shRLdfD
z^A#OiGXiu6^h=xsYmDbs;jz_95j!vg%m6dM4Ad9{oocM#8fh1sRu*P}87Pi{$dSRC
zO2C86Df--)A0@nk0Y>3O;y^TE5G*zkaInJKvebf|$JW%XvPxY?+>mBKG7HQ=2^heQ
zoTVZR7#kQXYCr7}?sS3;jMgbc8U_h%4y2R$3ABP4K~`~xwWdnFgG7g9WvwkYtsJp{
zI?CKr2TLxI6CiXKTP|1t)wnc)`fmEss2|Gd4>&jF9DC`ACHj%+j6+@qVi=+=AxPGh
zXvzVbt%eVUGJq?=gLs1V&}sERw&quBTG53k*j7|r{!oeQ-@GGQf%RLpfD^*QPc!uM
z#N86^$5Q{Nh1^raAXpN`88$IX`i)po7G{7MU<Q~0e+)=KlY5;@EecNIO)<AaHE+`7
z-U|?VH!c?}fNER>`X}_e5F+8!a#h036ETp*SBN8;FbEc#NH~z}`aH}K7~sTGNd|JS
z>q<g07Bj#M6vIG$F+m)|3@`(^Pl}j`v@uZe51FuOWvKuI5*Wc`pm5?M3QlBB(dRt2
zf|cqJfiie(t&YXuDwqLgfEg$&1G22yIe9Y!3z&#BGEnhxW0^Fv$UQLw6=FaFr?9bA
zkE;q%6&_pNVNqO-i$MPcjjc*w1QJm#F9zdlPX#Zs_@*Wdf^U+z!zN{6TR9luZ(Ga3
zD(7Sd;uw%|hVtq?!Irlv&dv;!mw}3Znb+KoC)o0GS(fa@F@+7V2k`{!q0`nv>fu5n
zN6SgYnpeStOfLG|;oH^@WRfZuEQ+gf5$K<g?LvrzQ_EEeCs1O@Uwm}};_@}W{1abT
zY$D-6vg>mL7EUaMGSK8__Vff>C_8P|U-+rq6Re+R8I>7e2ABb6ptcymPSk^Vg7wg8
z2_PkMv>X|%c@;d!oTASi##TB>l?xWd)wl@sU)b2HS3@GI<*FF-qk<P%d{Yw!!8cKy
zVH2~kF@^!@XKeKZ8$$xCnE_^i8Suq`C?2>Kp_$gi7GE((G6QXz0qk8ph$mPNot6Mn
zB1g+fB{{F&2rGDy$wi-+d2DruMR7GQ0{vrRai1Txv(yjcVhA&kt0aH%`P)|TmOjDt
z!@>+O1Iz$3zzi@0%m6dM3{(LF5;c&4#HA<&r~JtU=MG~l|07`#RRIyesMOdR@hL_)
z>$>zR;neaP3^N1<mrU%#3@`)C05iZ0q=SK;>1czypbTKI%)$&X1H~~Q5f)4a3MVe2
z;8eueN++pu!Mb#iavy>Icx+AiDsy|x05iZ0fC0%gREmMZKT*9(mu7ydua#sAL^f18
zke(TVw#cnK2!bI|++h>b)P~WZ*xvSj5eulJBqD=FQaCYI*3?M&A;>Pyu=Z5x_vox!
z9HJjhSl@0={p$aTH5?oDL+R(4Ud>Tq24YwOV*rwMC7Lh@Zpq>do1BKNF$~~E=s`Te
zdg!!zAcdb&Ji+>Dwh&YaXL3ihM(e+|ui!*(o%-C|Mzy?g*G2D^ve}R^QQTn@)1=)f
z)7~KW#|$t7%s|yM(DLr*Rxr62=XR(Pp@u;~8-UQeG5H(>ZdNg}>j;S`Vt}H?MWO$e
zTOT_o!8%E}f>SL52g5+NQI!62!J-b93Nny;T~`p1p_l<?peP2Kii+YOW`G%B2AF}8
zFd#~jg_GDBFa{EPi1r|3B9E<3oK@0E0jyl}qq+EoMgSj|mXkzXg94Gn;FOA;m;q*h
z8K^x5oZoG0j~ecn8K^D>>Z_|9u7(+CTMUrNAom4ZatHXL&6rcPP9n@O2xtQkI!P7w
zZL2#h5Nli%`Y&v3?W!Y!b&?3rT?_)x4MWMkZFPr59V``OfWK|6AlVGX3^c#bdf)+X
z?<~v!Gf)TvvJmIe`FesaT?18~31f)|@dWFk(^5bh1Bp{oV>;DQ5|M^MKpTMcAd^&K
zV=M9)*|km@1}JJ=6#6G*I}sABlY}?O)*^5)3}kHWWUNaVgkY-}*>!|K6fr=-QYZuX
z{bLW}3D!fWULchh)Ql%sKg}{KGr$Zm1I$2MWk3{FxTpEi6Kqiw`3=JCK_-LTq++ki
zm{W9!M3`X^&;}rMlH#!y+>}KWvKBVBVl{$wk_gXT3<A#$0~uQrRvp2K;trdbhK(@{
zbd1rLS?vk7%w2JMW`G%B1`1?A73g0gcTcb-s-Dv@16~*qUQjchVEr`PYE)w&v1Y_H
zWK5@8ClP5F1hfGNoumpITis!SSj(bEN`?Ll8(R?(tdqov``F6gwt}y63tlcP%m6dM
z3@`)C05iZ0Fayj$%`w2=wx)8)^?akySjEQHgbyp62zHs4vmH5QW2ZL6055ABS}ZP=
z8DIt~%0NR!(HM*wU<R0h>SrKoWUyCle5tBKB*F}XfHnZ3lT=~fwjz&_UF)P_fTG4l
zq5o8ktu?-&x_$n(HI>%@UZpI|05i~57!W8l*wRRx*kr!mxJWpW4U9e~TOjg_Hv;Z;
znTCi@pu-@zB#Aq0QkELAk=>Hpy>@z?xqx7cTpMJ`Ly)MocD=<r!`8^kCAQg1TbIBC
ze{Ew3o>)cyPpskCgk|ieAC0+)AOkU|_SzbPz?Eu(pj?iGAI`7|IoK4>0A6w)#1pKC
zPOAq}`6<N{te<9GQM2=naYwX9*J}^s)~R(8k%mD)8-UOcKEmA+f~?{WYfY7I2PZbu
zO#yeu3@`)CfL8{>i88$Vxs*e0iop&w$RLp+`W6dU1#>xJk-yf(px=p*s8vyjGz=2j
z0L1(hL&1z7Co!_?D1}I3fP#e?U<Q~0X24(opChs`1I$1X4DhEBMUYngA(%*5(#Qar
z4BWnL)im(fTIJV5Fi|Shi8XeTsEa`%(lAJ90}%6aP%xJm7AaYn0cL<1U<Q~0FAVT}
z<AwHegI0RJX)1R^oSzv;GXuszVr^Dx4-aFjJFK;X8gK|EN`+pX=EuG{M}dgoi*x-{
z;oP`NB(wpDc{wPUOAL#YEX)8izzn370jIaj(l_r3w)Bl~MrNRL3{-m9&2{DpwsO3d
z45=ulM9JU_O5_Q)pc<>gS?My2fyAja4`VCpa)Wj1AmvWMM5)lH^R6W7VhA$`qzdL)
ziIV`Nr?D;y<`TmqB}<_U;P;O`h$mPNo%(^qOV5LNg7wfTLox%*05iZ0v|R>NQKgHb
zqFNo~3AWXBS3ZH%kWrJ0y%J+iK}h6CqhJX^_;*`DM+GF9C>5}r=0}lp#LsXk^;3oO
zZ~-IN*!(yl3_@_C2yHd8Yn{>$YJh^JPzF{kG@vy8o?uH;JZE7Bm;q*>WDI!vw8s-{
z$!Oz5%s}NCP?d)Sq9<5C&9)jfYGg=GiqX@<*y;|OTz>kkQny(6*a}{vE(R58kkAGo
z{B0}PD7T1m18{z3fEi#0m;q*h8DIvO0cM~Y8IZcDs7b|MtB0`_MY+M+%TKq5(Cq~i
zr9!J%V<(Ba7!)E6gM>B!G1o=GTw++HWMKxF0cL<1U<PV}0aetm=hXx?+$1x=4AdwC
z#z5l4gWLRQ{*z!+6a1^w62dyAO1V=oQ7ZIV;`z~Bd_z+XSaed$B5Jw$^!ARoL>6X%
z8E7jEC=^QeO}5HqSM3q(bR@iSf7T*!FbsLSBt5noxAHIu!AVj8Y*L!qu;r1STNi8J
zH+PI!KpjP{jp)6RMDpmBg(Xp(VH2~|h_O-ksqjAs!(ZE2q91mt&pCG1u0!;r2`^AB
zVFqI8rY#{z)|F_&plphygEMSW61K%MAY(0MHF$z8Yfn|5Ja>Dobe*1HE8S*6cs<~4
z+!3uQnzV;;>qJ!2ZYg);2Bd;-Ibo5%h6QWG!VEA2%m6dsj{);u=TeJ+6S<S>bK`C)
z;YEg2QxgWk*CqlER#;n>TChiMeXNZ~UJPUb!{s8YAds18f*>m-9Nb`?Qn3>=zzi@0
zwa36RwbwFt%nX!<0sb_iG(1*W7VK78(#SyM$Y5<$z=O;w`aF812?iL25QziPgh8;_
zM8LrcYs*p#b{<=6VU@W@W`G%B2AF|LF~IXprI@ZLPQ~XN{6jbvW`G$ej)5Y^Ry{Wg
zfLZ592`@6Fni}`9)fpD3wJwE^tqU||krxA5z;L<9;tSACG(ivyiLyXj-Cz^bu#p*H
z2AF|1&H&yCJ%}e*51le3Gf*-HDn9HsSMCY6WVBT-QBh2(%GH;T<Ow#vgtqcr4;PUm
zgSCDE4>G6d^XQQ#7+@4aBo0Iq2Ek$z0S7CrElVxf3m;p-O60{5y<GXL&>#?;uL;)}
z2CKNiTGOyY1Otr`x(cW~!B(KN>VWX{t&b<z>foHKU<Q~0W`G%JD-2-kTCk{sBT5qB
z3AQA)S2&5DG$Ka^YZ(F_WKPlN;RH$yWa^QKBbqP>7Mln-knH+A%n%shRO?ds*s3&T
zkrzYsas^~dFfDK(nji><L{Zx62Ai0MjWG<2iqV%@?FqKbU2%F>1{B^6SeOB3Kr`U!
z(;iQ-yyVP4TV?=zR}bO|)<dTyfQ%d&67x!J74RT)ias~yM+vWBfKfP+I1o)31WS@g
zZ4_{@!osPhMKe_R*b2rXFNWyl%3p;Bf#7^ixW+J8#SPY)Cglz)<^6Gc%m6dM3@`)C
z05iZ0Fayj$Gy{6lh#VQBz4NpJ&&iyk&%+6n7|7Hk5l1v(5G*zka3I<Bd6*$Ez^Rr+
z>E<gswq^wA4(OLS3Dy|TtrB?+1{oB>vBoUS05iZ0Fayj$?J&@(c3S05nE_^i8E|1B
za%8Xu3V4t?MV}k<ql6b3KTJ&+1Yes7I9OqAS!%(~V{7VGS*5NcZb&mAnFVHm8E8uk
zkS&eVC#wB)d*Mze*uZF=LfeKxLYo8WWPSpzU@kE%Qr5Oev`<#n%16`65eulJ%sq9m
z<PtdnLU*y{f(1~GOB1N?rXP*^p`8AJb5qW-myTGXADPZL<Ygd+A=(mxWL=4-9I)AH
z_)sVVxDq^wCs+@iRu817UytzwTRpr-R3f1>?}!neRHfgl1vGg1gr8>U=ZU+e=KHbK
zZuC|j2Emdj&ajDD(r*;0ZINHZsa;xbj2TE70}}ldHb3eBg{bhRnA@S6H)(S3ZSC0V
z4vXSyTm<?j^t%uu;nebC2scl}Ko(yij%dOlSZpHUK(g!eFhgK~6ALrI3@`)CfWbh$
zp<x9xzzjGsAe_9|sf{s!iG(GM3`jH;Oa=-kE~4N><`jL-V=Gvx4iPAW$JXjt46cG1
zU<Q~0W}wY8AliHf(GAFGb**SCKHn@;8D=ZqS7q9&brk-W5fYa`VPmTvR~4cvJhr;S
zX1}RJg|#aJtrs-5Dt!@1M76vajITWvyvX94nlK2yN#YKhl!a}~05iZ0v~>ogp9Va^
z`e~L?nSs(U;AtrI1X~);Dw?G@rmz9_Af8}7blO@-JzPlSXgR4^^D20d$wi;zB2oH5
z4dDQjT^2G)l?xU%)VK)rPsny5M8c`%s*nYYTw`?t;>hI?2Ek$z2?r~zEeqSD7-+&p
zP<inLTlq#kAqqdZo?!hn%c#r%Gr$Zm18tQ7>_Q8d?4VM3SZgCZ!M3(+5Am8Q30N=|
z4kS?6M8Sc~Df&FjKn&pklU)`vNtFv0#nre7^iRmP5~5c_!l~t|kOhohV}-crRfi=}
zoM98QurY=K>1S;91RFyFtC<02fEn<`fbawC3D!@ujLHm@hJoUS-Bx3Jf^Bu(UJ^*4
zwwzRwE72Qa1rIW(==122hD<$lk}4N0imPSO3nS2fVPmTfkceuzDr5m8*O<R;1#e{+
zEDQ@Xzzi@0%m6dM3@`)C05ec?4CwhrqUn~Cij@cjj|z{i8qpCJ#nrOt<rL_@Qe$hx
zx`eZ?%Q{FnwY&zy41vKV6Z^C^2I|{d!CWshzzi@06=I-gg>V=qeGEALe-G2wcB(t7
z%P4H?Yh5G=2qpuC6Bki%s?M>M7ZqzGaNw~OETl&8DrHF>1N?@Sx+Ud?Qq4f&pQv7?
z`7r;Xl2($P7uitdKzc^p%7Y*)$?mY$ROxphyCt`K?S2spsELvwD_A6j6Jupfjf7u`
zVUe=drL!hrh<-F-eY-iap~rnVHtL7M=-;b3D$GC(OJEE@vaUoE2Ei>^oMDsGur-DO
zya+vrCs+@iRu81`Q;H{8Kh3(L;(b@bncNYfNEH3I_7xn+ty7<y+bHwKZD_(EWK0xy
z*u*rcH>%WjC{o)QH^vMw11V#`xYs%LNAAVB9jZj6VGz&;AoOlbJ_muDRgCO9LL!P7
zpr~<C=)dLG$IeNxP7<!*RExmDFoZjz?BWyp%LR)%SeOB3fEi#0S~AeoQo-lU05jmm
zfO2zVueQa2Y+L1WweAcU1Bp|pF{kJ#iAcjBpbbFiB*kMZxG9S$WG&bHXsmI<sylTT
zTpkkM$gV};Knzf@Fayj0Gr$Zm13nl~K0q0>+zg0v1GLOv-%`Qn%m6ds&H$MVaw9`>
zG`?svCznh{BFr!dXaf*BNfkD>y2Apo#zmq3!p7FFIwDvniSXRTAn@EUl<eD9cUaWH
z!VEA2%s^Th!27HR@dWFkQ-)*)O2vRIRieW3c!Djg$g1!zjwy^K9>f!@hfZ4yDRcs3
zAaP1+Os6_ZBGNDjXaf*BNfkD>B9D<>>!e|TqQ*s`|H8&rL<H+3aRRcn2pkLp8CyFU
z>k<Yb*eXVL9U%}!3{bEX$^d@<*n@b2_0XvoNaY1J;|bPJvy93NFayj0GtgEU5JeU4
zX@2wsTNFipgD`uL$sjkW*sC(;6dfWFW*7vt0SKL>cx(kXWf6s}g^jIPjbNQ5!gCjc
zz;nYu#@2*YM{uIJ!zQL-V+;cwWAtTKdx9-<SDc<1U<R0h0vS*R`j^Pv6Ksj9=QPZK
z7Y2kE)Ql%sKh3rp)fh;u88HnR)2Y@;L>dMGZ2&?islvuqcUU0Svgnagq5s0hRzw8r
zByr+Cw(_^F;H%t%mkSFszzi@0%m6dM3@`)C05ec?4Dh$Dsa$eB-zYRzv9UGb!wM&Y
z-KOPWj&@4PPHlz(9>?3vQgNZo05ecY1{x{}##qb%Gr$bA0S2N*27B4Ym#R8MBFr!d
zXaf*BNfq{OEAklGwN4raC~903`cK=~TH|ZV<6SB*0K7_Bm;q*>tuP=^Xt1S`II+om
zy>XFnA{!WePPRbg7jFdI>oN@ypFoE}a7hw(*rY5qVk5gHw|njMI&%TR7P&Ual7}Es
zYu$V~*y(nLwWmtIM=#yt610iGwlM@xtfK!X)^KdXGIrCC##}^@ff!VKZ4E)-N;N@H
zE=R%-XV`=sY>H<9FF6n53D!fW)dQ*gl;R22PqVJ5+4;t}BU+>DwTE%*)H;bs!yupy
zK<Eb_;cf{*R&j^5rb@Si6Ps<30@W6a=9-xSW}p@s2q(($?&rb+xhV!a)F6XIhUi-?
zTougaghl>Z7lVE$LZVhhA<{5NXaf-QQw#+&f}F(2uA>wpi2({0W`G%B2ABbZ0ep_g
z!VEA2MKF-gPb2g<0<|reNLbRy0GSNjzHQYs@Yq`A*FrE+D%6QJc9N)zK_SvGNN58P
z^Kwuymlzf)S(pK4fEi#0m;o;gq;tOULS;39R(if^s;1_-7G|KWF<=ZN)&`{Z@G!Qz
z!&*D20f%6sROr=de(alb6o?4EIM+`V&W)=?LK}dXmxF@2#IQ)o!VEA2%s^ThaC*xu
zee<4ROWz1*WCkk7K&6M>TxXtOE5~cekcwhTlnlP0M4n&^s<Aqpl`g{=NSsRZFt(yD
zH&~|*QtlK?lnQ-1?@FRBhA@Lbs$ia#I0-;{8tbB9E-@@pvJ}bye*f5mc!KrNsUJwZ
z^gM_sSPz{tBs0JaFayj$+hsr%Rk|oDs?|ZBU|U^x<r7E^88xZcD>3F2ghY-s3YHLr
zf43EMR6v4>QUS|peiS)J{0x^;KUFvn7cg>-&5skpAOt6h&{iY6)+zm<1}InxWnjfZ
z14`rX3AQxFa~5WR8DIuV#(<|!dpyCGj5bch3{;*0Re4AtdV=-SY^zbDMuz017(G3V
zt?sbN<)_~&b&G|Mt>7i<Vo;F=32gwv-?oB{a*HT80Ow~0m;q*h8DIvO0cL<1U<Rs@
z0jZ0MnpEtydKg<#lpCzQ{B(N=-Ci(JDzu6<c9N)zK_SvGNN58Pb6ph7C5A;x7G{7M
zU<Q~0W}qe*P(}TEUQJNLO)>+_K#ekB3?xoGxXq8|KM6K9!M{2!A*@rXlsg3zr9z)2
zo*&J{H#FsdMJKf^qL!OaZ|`_ZWMKxFfwsbcLZM{eWUE|u)gHl4N5UKTXDtE;!;rU2
z(qpS}D-VMZoFoOnCZ(wjTOR4Tb+Pt+bH|7U)KTQxh~67XB#&NMSQ5n<HZe<$7#nq;
z3jcF3{I!iG`eB#)oMUJ0Iz&I3@B-BmW*~-c+7g0fU5O?P%BDy<IKw6-VOuN%GS*U7
zgD2Rs_Eh!BbGO$@*Xaqi(rp%m*8|?h9nqSiNqZQ#PDCZ`mU1_4Kq~l_6BhYvSg<zf
z6n+t>b6vSBW*~hGnD;uD9tE7pom8J2cS{K`GNhWCFbKXj5pb}=+OpJwJ#y<~Z9MW~
zAPX2S7g+^?%tR9eSs~%z2J4iHotOb;fElPg25SEQR$hBc&K;MEf%JYFQ7VSoWFG8R
zS<=Wr<j7!cRKSDGDf&EmqzMKXg%F7Y(S$*;*hIj=3Tw+!3w9n`YhjhSM`nN-U<R0h
zN-@CmO{JKwC{D%a8~j5!7G{7MD2{<5##TKy3V>PXM+q-7q?#J{vDFzCsI@MIkF5(d
zWsw&HS-^0)$l?poO*BCe42iNpTisw2)3A{lU<R0hHqHRv2|b7>SPz{tBr{Ml1}Z-6
zHdpQmwq&$bE>TfTsmj%tkK_q9zl65(Tn`tKBZIYm0S_{#==122CKzB8LL?4E69&Oz
z69ES+tSw6|*b5(9!Aj)C5WQUatI!}2oUaMj7zV4j!CKR>Lj(hj5xNSfJi%6=v+98G
z^sSF4*y`Y%t6&D00cL<1NHqh>Pj{YR{WRNZ)X0&+npMDq%qjXjoIr_zOg$2DL=y(V
zViN%el3kyN83F^GYF!E+Ta~6P@?wZyu7GR_rUec}69mDKC`w!1U=!1@F@}LrG5RvA
zJ;9c_D^AZ0Fayj$p$vHXw8s-{q3p0fGf*A|unR3*ii;{7r$vM(*cMf^g;PCgM2-xJ
zwM%Uk@E~)FJ~!q^39n#)Q8<w}5KR~aOOi-!6mYP@!l|Z3GgSE43dSNYhUn$WUxfyN
z;CxNE#xPjL4c3|_<qj(4{c(HDKzbO!dm2mX7~o}1-I8)c%m6dc#u$hk8LT}Bc#t_o
zpNA7DF_5W8B93UnAXsc7;6SqL^DskTfK#nYMaR~R0Nnxo5+}hL<GEELufZULLO9l#
zg&9a810sbzaZAhqGf)x+I+Y{~CrM_2zn4zthpo&&RWT4bGFU4V@E~)FJ~!q^2`@5!
zn3^yMzBUnXu)^B1)PkMI)>>F)?vWW_2ABb6prQ<rEsfJBs{M3*;Z7&mz-XO9-G)Iz
zn*-@&{=+E+bBSS*vW7*oDbYSzSt}n+D@QD#jxzVu!IDel1PI;5mJ1d@wJe&~CQ#o^
zKN|HzIsF0WrkrCh9kE0|GM#bA%Rmf6v?T<|x)Mz}V6)Zmp-={JC3p}|upT;XC1eSS
z^7JvJC)if<Ufytp^yVGW3aa0#1)OkIgr8>U=ZU+e=KHbKZuC|j2Emdj&ajDD*vJep
z1Iz$3zzmd^0g3d5&5t@jAu7Bn<~CmDO`6<$TRXP8!=ktv7lHl>{Vs$^IJLYO!p##g
zki}PsBbqP>7Mn;oknH+A%n%sh#KH_P1I$46GaxHnVtqvcRi?M<BHEosessySQyHP(
zx!Y-5_6^)#lg#v}+d5OHf9M-X_J@wiOVpgNg~pz?TppraiK`@U-Ei5XM~4pdN0+)0
zs)y*He`Ht5rPMWLb`AB99_>!b;7m(%1|-TYclb1m;F6bpm;rYNFp;pdmI2w?1f`DG
zZzkEAg2_O+0%RS@oT4LZb!-I>)g}T3@z`2z%fj_A1I$1<7|8C6GYiU*nsZhG1ItxG
z4O~J=7zp=E*q_v>ER(*zgVmJjYmGY!7{H|HUGy7>L=lCJtvX5}3U5CGPjVM*na5Ul
zSkzQe=?XN^q431J=;ahB0_zffX$eJ=C><r?(DGskGY|t=e1$lo34>rs5_j07EG4#~
zQ;2Hb4C`m%ldPT(ZH)mDEGaFVKaQn*wBa*_+64|(A*!e<WKmJA4)O%+Qnzq%VxKn1
zK=|H^je}<qMd61X6ct@`kSAE@da><nXx<Mx$5fMJ^j4wl6?%d#dtYS%kjM(g@M2K<
z;Uo%PWKPlNVFqFd2bk=#kV&dsuqdwb(osW7^j8fcPy`{{r78)hma9S*FmjF635bhc
zby#d7;b4WeWnp_115JLeNKdd)45U&g{B-3B)=#sH>W=}H-7WaTXJlr88K_MLJiYb!
zffZG|#)*|ll-+V<fG$xKtYl8n=aD1LFJJd%mxWAH6@!hh41HL|7~BwHbYg1aVI?w<
z_6eEJ-|a<KhTH-NQX&+IqRWwRAZ6)u14F@!)N5+OAowOqD_}zqQZg#DiqIaU1?1AA
za3BU#6Avp8O;|5oWk_9wNR(4~@dUeK<vVpmtlr8T8(=qPfEg%`0a097Yok2D;+|KX
zQoWT`CttN$Rc<R->E`{ws!F%%j2BZ`vsxkz*<3@BD0(BT;6Qfw`rKhkOW4yRW1_SI
zHome%L>Lij%qcJ!(}}5xhn2`cSSMsUUBNMxWm9Ja07!{Y*hIpCl%>y&?iIZ9>#fYU
ztp;pDWvI|9`7LB~=?I0Wd_z)igsJ?XGE|1uW=S0bPOtRTb<GVi18tE3yvMVojsfhG
zSeOB3pv^EKQ7PGfyOgfrL^kUB++j+ilT^iE<10fSRxt)QM39*fotT<<SP6g9J|WY2
zGaFeMatj<tiBQ-?!hw{f&kYO(FH*0m34`Ek6A6bRU_%fR>%6xhEg+W`g#$5|ns``&
zXu^8wDnn`(W`G%J0}SNeP1-=ETw--I(6hSBYgKh=?yXhCaBvA2P$kI0DXNqKiMq(<
z+NDqhC$hWO=MGa^!k!)(ZKB{%1Z;d|HpHymm{XuNrV~>W4=a&@uui&i-t|OQhTH-N
zQX&*Kk#Hbo>2m`^!Hd*uYQiA++C;*k2-pyW#G*1MAuS-67KH;bn3{N4foQ^d=_*5N
z7G{7MU<Q~0uM8MB0Bbc@X%BNZpq0k`K_FM&Eu?3}tvm>VYoZhnn^ajMq&7<Yh044Z
znsaHL(2smWQf~^r<VI|;Zn_{QNn$HQP*lZ9$+T_12%5B7A}m-Wg%hI@QzPMrAiER~
zE0H|9GAr!O9gPLd#uU<<`5G`-H(iRY45>4j&iXM#KbmmbO+W0?zS*%+dn)}r)2lfo
z%s>oFU<^RAu0#_C!7W*ehYdl@%90_qwLX(s0;iybY%YC{rkChPXfQPiup}E;FIi;@
zH5DbeP(6qrSm~itH^@p<CfrIXwU;MYx4TBEn{~?9quER12f6Pw>l2RpZ|y6X$?Zj-
zBcsv}Y9O0~O#Dp+fr-)z*!ap45n*i757I)8H?tE{6AvqOR?0dd6M$A}(jI1IU8FUT
z9hd=TfEi#0%FBRpuXBPU_hQ@?v`8EbgMc;wNxJF6&n8B89Uu{87zDHdti(yQ3oJGf
za3Hz#xp^xzG!k*quq0cw3xaJT;6QTaA{2g-f^vrBA0!pZ(jss$3}n}k&?JJbVr175
z0#Sy6z{a~E)+%N$9b&A7sS(Ir`O1LG!VEA2%s>PKO%b}ZsM6e9TGpry_u=$GMjP(0
zMoZ7_Uu(4cl(%i{zn%IuclVi$M5JL5&;}rMk|G~x!p$m1b{!!RWf%ms0j$JHv<oaY
z5pW>6^f{Rcvu}KcMj|d6mSl@|L9k5(97wK=f~xsQ3d*W&2a*b9X%RRW1~T&{G>KrV
z7}<4%K$Kx1u<<U4wThWbhZt*NY6LP@zA~V)Fayj0Gr$Zm1I$1hW}v<e*KR94&Ar)r
zXM2ShF!tY8Tx|Ev-F+q_5os6%v;l}Y>`9mrWR+IHN+gf2%nGYZ7jOz%kT}soW<oDx
zYjkBQTV3`@O3bR04zB;kJ%Y&?Zb6w<S^+DNoUBW*##Yn?+5;Dq(vM%3Qa=wega%V1
zv|BW67!>b<*hE>Ntr3-}#2_{@1I$1Q7;t*aEPbDTVDUCrol?D(RVQDyS(WtDwkKHZ
zCaY6oDs!4DB0BQ)<+~qP6+u9CsFEu)w*5{;o4fl=Mk3NM2xtS4UnYb=BVl&Fz>MrV
zILu&f_6-oz1@JZza3Hz#IhhH)jIFu|p&v$N&?y{9iBMRDG?`l!fhfa3nCxV%OBjS;
zs~FjJgg}&GAh7W+h_#BDONSVpB=m+=mw+*X1hkRG!(f%j%B)e*4)}Fj58?;5(L<+h
zkR`56xuKTY%M+}hJGu*b)mxcM_3Xn8Fayj$S{V>UHRkC(-4CoPilRyc#aD*yv9Y;!
zD#_TW>nMpx!yupyK<Ffeg_1BM$VrUsI!YqaFbHS^Sc#Kp7g%f};6QTeb21ZVFF8Xa
z5f=?hvPHWf*d_uFBv&Rg9O)Dcq#!5~1wD{d$fHHzU>L|`mCz)D6Qvcf0*NClOGJcG
z=?7^+Xa&Sr3sWQD7YVCiA*_>29Dr6)+9R?uYh<)T$7prAwSHhnmAkE?^H*<WMYqI(
z%m6ds!hmvdD!q><*z9Jg^xc#oWA#>6g623yi5L(i%2Qw(Pq4XNeu2eS!acDvWB+Zf
z2>Wt#cb~~fL>dMGZ2*$6r-xgjv;tNladc&gklHBqL+D4?g2agyV>&T45`NLJ0U-%4
z2u>2IjRFoN7ZiHxQTRzpgu*H$6)M*va4-yHvP$?y62Vq6vg-(eD8oQt<6RJI6*HF(
zF_tT#H)AGMz$C02F7U8QL}jx1FI!qe*`ZA_Alg*5Tr4xd3@`)C05iZ0Faw?#!1maf
z44i5)cK13;BGNDjXakUhJw4p4Vr1755>bXhKpVhHoJ708ViN%el1rZ((}}5(h>M0L
z*`i$#Y!d+ok_!qwD=GXWB|>2pk_u&M5jYqIGFc@wiD0W3*>!|KlwlyS@h*t9ikVA?
z7;9l_1Tt5)GL=yRh%C$iGr$Zm1GU0HLy8+sb8jhLHg1g>@Xmm-|8}a#+}&p~5|M^M
zKpTM2Ns4?G1vjf0*>!|OlwlCi2Cxz*(JrvqM8JXM(&uC*L?@<3LK_WBvIQ;+;2-A2
ziA@9?NUmIj!p|@jJe-82LRne_4u*lud<jh=*eXVL9U%~97zk{<3u3Ke=F%a-S}25r
zKvN^2t$bzK|BoP`S<=IR$X#UV>4-bg4B)MWC9MnyG)8U!wod2k+lqt}xxMIfvIR14
zNOhTpj6xi_m4`vFBuVkGNtGobW^MiS(I{B!6s&oM21AnsD-casCuAb8RpKf`U|wO(
zWmvOirq`JZh^XW$1ze)mx&pBAm7%CaX<9jAxpaitiK&T)HCUG@f~+hQi4s>?HmH|A
zF2OVWwT&ToVio;Av4&$4s_v#Ajk$;*12L%f+8Tnum1=^ZT#kevt$+<c%*qn*noUhn
z1#6SpiK&T)4GD>NDY`OiV2neL7=4-5o?vnDR;N^;GUcapPq5ifAN+LefSSEA8#e%J
zV7>Mrw}EV)sBM&S3o&oy5^%_7l~%w?BsWSH&{{>`L<F1&Px`!&-tb1F^ur92(B>*@
zr?AZk^TLuSag{l-nV6Z4C1yahHeag~w6*|_X9k#of*1(j$%9*mQ*`(dLU6xARFFa9
zBrqtPgdp+v7`R!bSlIZ=tdQD4!6|G3xwM#_n3{N4lFjH!Wf2?>Sx1s92r}po42eHU
zs@%5F#4zeLKg9@x65#@4k+30%Kq5jm6gH7?AUx^wLV6QOKwwEWqbmu27m;uxxm=>y
zhZ$f7YL)?fj+j=dir!>e+2y{nH(RD5T@2{0TyC$PuD)u#8*HmvjAOY;#ZHX5yVo%e
zJNWp~&W@=)iiM4@%mr4#i3}n7-0Z~E#KV$oMps!tfZ9aCf#eDz$k5Zg(t#=ACrOpN
z7!>>sgM>B!G1o=GTyEG9L;#JD4TVi49D)`UPP7<nVQLiok_kz0L9k6E99mXp3t~Gn
zzzi@0%s@FAz`HU_>KMT0p_0;6Nw5lIRZDN!kF%td0b~Dd?Ne$Gb9b+mWN;w6?hqt?
zv@0uYd}UTxUAlr(*h20d&g{h0#KV$o2ANqvfF?>@W!WHu{=`%;_SFxgEUi=eVHzZ~
z0f>1yD43DWDy@K3NN$uYp|y$9rAs&kEhwC5G1kJ=DELLgl5Ei~2u_mN%94WE#tbk6
zDPX|qEwl7}`hk_DZ=^&StGBWeHOOg7!9Z>+Sc+7I<nRMqy;ER(WkoS13R#QN`FeuI
zmbE%1rm_whrRy~|*G@f{yL%nxFr~$hc4dW)ugnEj!HMvs&&^IuO*|~gW{{Z$1gK3E
z97wL_L9E3%1`j78sZf>{g@a*`&<0al&*%=y4XaQ?bY-yEM8Y9xLE%J;(MdvY0s)1t
zF=A{Y;n1=&TTqN0zi#V6{J=J0HL6ldU0KX~dbxY|11rkiR?+#Zx3Z#J;y`AA8DIud
zz<?^M2T@d1tAjkj`njXKuoYXG)X~Pa-zB5DyGNA64nBUgD=Tb#WiGG^PJ}0YZgyg7
z;$cZPV^qol0@Nl74lQ!ww8hZVtjg-+4?>$-q{=!g91Vkn78e$}HZKPSZMk7X5CJqo
zHWZ1XOP6p6T2MIAVyuO!QSeJ9B*6v2i4s>?Vo<zs#duRWEq-7nE`q9*>aDCQ>Efc8
zffO--yNn0%11l=qDel;gBBJ~vl~InYt0V*dmPJ*v&0nxQ!4~lH`K8v1JWH(1*ne9~
z!k}XA?zNH(4rCq(LE=Zdvckq!W`)(E3Ql1Qxt+1uiK&T)CD{xzvw#3il(@<=QimDz
zC#DLFMp@dRU^EO8+5jZs8%elX#mKHB6rv1+gf@UxIEi+F#U>ICB$qxn)*_)dfdqxF
zF=A{Y;n1S8x{QF9B~=V49%oavp4?1ZU;uY&7G{7MU<R0hHphU}6&u@rr!I`$J)#_T
z@bRNvSz+TVbAeTGB0TAHvlCMj4@<HcWM%;YY7+$qk_!r<A7to(hm(+0C`*gN!7xZ@
z0}ylAQ!tksHUtqsBV<Ei6A6c)1%(qW##)#f1;1oM5?l~$6A6bFm7VC!rY$?$nE_^i
z8DIw500RoQwUkPA^d?ivF1N)Dq?Z9>|LxSOxx3e4WN;w6?hqt?v@0uYd}S`M3Ql1Q
zx%-IOiK&T)CD{xz7XZ*j6r4z|Aj+UWFeLsYsd#L~ik4(-RUN`LPUJsll=w+j5GMj!
zmQ*pIa{tOcRZVd-k|{_r0}8#7Tcxd8*;RWOy8*2eh%^j&I|)@sZv+*BO{xqfC(2dY
zn%6=umsXNnn*P%&Nxg+P%oaiAsVuJI#6B}OcZ^s-9YPi<x)F)Y(XGLfD6N2vuPhNU
zYuqoQU~P~vl1@xbJgj-07_SE8PnMX<vO$gdsPI3~!e851q91mt&pCG1u0!;r2_<O>
zGY~^JZ3#iLu0#_CWm6;_S^*n^7?mXfHrq5eM#0)*c4BJcVM9XVU5c*E9vJN*qt)fs
zdV<AEt~#X>mErx!gZP0J9y)c0>;YHf24IbE(jLaG6H&(f0RRe?5X963L2yfyCT%Si
zHUN=8Aa_J45@nf|E#z)FW+$d59yTN-%B7uhnmywx14%6DVnB)9WtXnDxEp35wG5c|
z1D93>oXA~4pC{ffns2cZapcw(2Ek$z0f!=BLl6?{yxTGg)>TN9LJX!R9@b>Nbd{m7
z=sif*l5{Z3(%z)W=#~VM8XX{;lN1XZUzroEQLv5@h$IG66Ax?b{1nm=&Y-XgDFARR
z%m6dM3?wk12d&gfntMy_qP3;Q_|u5Cv|4Vpisqe{n=^a06$YB8ipY_{+Jb-w*<9;$
zvOSO9!ArzNZ~I}fiGV{9u<@1I5VLlpV6By~5QC|Shc#IzT_LZNkOBY~h(Ui~Nc?G*
zrQHn-fgGe>QxgQi)hflp1|SLuglsD$97qeurA6RC45lU?)?i&BU1=&qCKhIZ8DIvO
z0bdO8eB+Dxvf}1%oyrOnB*#C5ORH2#Z!)d?a$hn3tT~w&y{i}SAiH~gPPXUKJ9vq>
z=xskNiP8$#_{tIyVZ=yf6s&bpKd8af#KW3{8X*&aR*9=D8)(pPO}9XMm}P0D(Y?@0
zy7;Ch2!d;(EYQ|sVFM5a1VT0xiQ@k23j%qJ)iFzUbV;lV#<<F?f$YExFavFy0lckv
z5Kpjp%dAeR-pZ<zuiC5%TMiH62UdFM)D1GevZ9z$Zm6a9@&sGGpTosertejH-*4`}
zUDiXuiEPyMIT;*`xk({J;t)M;z+w{thazC(E3+YH?MA^`D`6o9QxgwsvQD}}UMC?1
zG`~o@WdA382K`Ry%(8TtfgzA9zupEz69&Q6Dn-JEAPNYCY%3%j@>|H}(mK)7kkFfg
zFM%~!H(d~8m8i<BLD3G4(du$*J;CCaoU2nxTv^O}dbxY|1FOp2R?+#Zx3Z#J;y`AA
z8DIv|z<~2UI=@+!e^R;Uo?!jl(OqbbuS{=`BS!{nRsj#Pxz^_nJ9vq>=s5@$n+P}*
z0UKYL4KZss3f5W)3o)3QcvzEl(iQSL2`K<@J+cd0%<s0UY;-1rpT8`ner{k0c#wKc
zO%MdvL{ZvmvZ0kh1~~ju4}pz$K}@3HHDTn^I)Nx+Fg5Y8$SU<Cp?FvmC9bl>pm^h`
zcvCqoo?ttcv!_<&uHMR8)fNXc1I&Ppf%qMmEwWX1Kd`D*HJ3BEdMhhu*POdR2C%>L
zAbwzlhfduf6Dx}x84~kKZOx`6yL+v4n9>j%v!{n8Nu)LkI1~XJUl|f63PO!JMe8J@
zh{4pv!<wv<uAHvmxXQ8&83Po`wTfAm4k1lOw$vby+2{b-oTNzDgvy*?je>QQKxDq5
z!O$eY8mud%Bb-5DmHYy-a7d!8VeHW67-+}iY@1s%F1QvL@H6w(0<)yYrN|kdFayj0
zGmy-H-X2Ge49QX2D&Rpj*ZQ1n&!czn5^>RU5G*zka3}&czA_tP)@~H6wGtL$Fg5Y8
zChMdt<aH8K0N@}>KMeX|u!>oh4lytU@{oE>O%McEs}u_xfG8jkvaOJCAT1!57J);Z
zrZ7jK2s9CtD)<sugLTsdF;+1u>yqiRyfum)tPJE<Ir|c^I<o^azzi@0UK!}*6}`OR
zrRxnh%wnZAvBhF?oD&1sT(K|%CIgWpgXz{nBXCYO*ZSOH2QLv9J#D~Z69I=JVB;&Z
zA!hAH!CEU}AqK6Hbwm>nYqCzdLKY`6;DRV)fC>zWKh3hVyMZB)gVbwkf*`nBrC8Vi
zL;-=2ZH0sbX#u&k2povP)WpLYtSh7|O=X#EF63iL4+HHoGCj?3CjkR^2Vtoq21F@q
zF>V0X<o&b<xeee>p+(_f7$megkWRq|sG;VUAh;z;@vy&u2q2I<Vj`qA&ex?&I1!%o
zdCS{lQf~qY2rS7K%^6~nB(^dgBoRn3ph%Ral_O}<5$1lzXe6PvL`WE00UKYL6*V)x
z&RD=~P$9iVFB@Uqa4EhrL^h$kZu-%vAIj;E95>}0d+CTJ`jN@~U5YRRF$~cTAxPGh
zXu=>QN|dJJVM7q3vP8tJQUA}yjDlf6)5KtE;$cHV;$5=fiHEq#5`z+qxDq^wAJ`rq
zI(37rL}j_#t6M>(^YR0$O4mRcGD+mbnkzgB-`#PNDEh5hzyU9xaO0q#hZ%^0+(M*w
zqqp)f2$n=?1#AdnRF;ScW4(Tm7LZGe#DN%0O+2j0dY$I9OGf>Y7x@#VUi*^*a+Qh1
zC^oi922RW^ZksHgi)IFDj{%96$s4o_2MSK)#-Y!nZWnp?UVzZMam8TcD??3I3AYbH
z!H6(#(uO7;Rw6@?P2q%)>AVk&tPJS{4x}I`Y$D-6%F^cshJqKV*VKeT@U@AALlLkc
z2#IyR2ay(#ON+vR7)(t(tUxqjy>yi!H48Jq3@`&x4Ae&{+rBRQudUJB_HDlx?x0#3
z5Y<{3*HttFs(B(QI-Ucok^z~mDtjcGYnNgboXGB8pF2!x343~Ew26X45wP)<*$}gK
zV@`qAm`+ShJgh_p!aC_HH$%ZGSt2V#h`@oA2!%}~97tLE+`v%qBK4Y@FbKXjk#Hyi
zHUuHDsLV-73&^EK=|{VKLkDPRxACw7zJ&GCRfg0o#WNuCLuLL6KW7G*0cOC30pa4r
zK5dNw?9?hM`kz##R;s19;n;k!lz;)Jf2~;p9QPCwu4Hp<jn%t)1*iPoJ<c7bw1ho9
zG9*eXVB;%GM1)c5hcTzXU`!{bCLR`9DeHvH+zbV$c#+x^Ss6kE4x~gVl0@l?K*FKr
z#b974c#(QdO&A2<Bxwz72trCmWmf5{JxB}4rA6UD45lU?Rv?<N9#pmfmR41U1T4$|
zGmv5iq@UhA!8*MkdSRq`EAv7JgGMq?@nN^Q3Qw@u*Hov(R#qHS*t2;MKd{0>r*4oj
zmC5YXqmSmK0$rjgSjp~QpF2!x(R=!AHe|Gkf<qCo@s-&Svvy-nf!3H#OietjM229b
zQ8*!8<z^`8lf|e^W<)k3dn6?$Cu+7z{2*oNa|1)cE5BZKLQBmrL9p0F!l7{3UqDDK
zDsz(j7P7f?ltN^_A*nY5Rv?<NZn(h1D)|Kjm05$L9hy*1<;4>$e#yByrNos9KV5o)
z#jB_~rFtu?PQJJ*W`G%B1}ejV^FErC<LN!!53C@qSJO#+WqNxoQ7IS;XDldeqToO_
z*ZMrnKn!H+N!ZgPqfHbXNOpbh02}XugjOLfAQ!}#PE1WatV9OFI_b*!<rYzyoR8cB
z2T~#wiK5Gqa3E#ra|1)ci_~js!XWr2N-JPP5K=NKvx?9jqy^;CqHrJvQxgv>5KUMw
zQDxc0NM5i=lv8=}1iND8J9R{?-pU*sU^ixf87PhcQCwJSqddXlo>!exy_HobU$t3P
zZYx;n=Ka8`O1J5ZmspuZ8nU^DB2n~4Siynp?)ACDl$NlkN5({H1#Em}iHI;F)R<FX
zFs2hz6Avqqfv`@<bh?6LE5pJF0FV-)u!)2NDNCOl-79$I*PHZ>Bz$cm;ZQhiLS;6@
ztUbSlY%Z-;u;d$(dLt$02bG~Rz1o0dNf!f7uk>`a%-t{pZHWPXiMFNH;#!#jW+2@R
z=&iOyhh+cl(z1dR*{JJthbfItQWb-ZuMB-y#TeWWL1x12L}6&+VI?w<_6eEJcgo1h
zkXQhK6a<A$BpgUt`rN=!@FMk^nlK2yHj!{B0yYF8v8c>RNDIiNMd3gUrY0U%AeyjV
zvdXflk)DMaU<Q~0W}qe*=$Ya!)7)E%myKIv27EIhQ2^OoyHup$M0WT3++j*f*wZ7U
zO%xo8fQ_%rhM2V*a|*P^bYg1aVI?vU)=5{n846Cx5?L8S1P-J`C~P9(K+4kR28Mzc
zsn^tmLGZPSghLUqAqa^@Wllm`KrSr`2VyWa@vs8Xg!R%@*31w9Skl9QzLs#ku%wHD
z4qemL4|kK#fN=xJH%30cN^8yCfL0p!2Z8v!TS(7LOU*Aqa7~orVSfQpKp=O-L`ZFv
zxcKv02=811k$Hxs-V}TZtiihJf|w+UtqehVg@qL-CDXS3B52ZTiLm6AO=u0l$x=M5
zMB?bmk|DMA=8h4UqShOWWNIXmN5dMdN4`uDA1`s0Wg|N4;}HF50#diE%68CyI2VqM
z`l0YgbaQ`~BFsPxOSD5K0Li)%O&A2XWGNmt1Tia1hSb*jOlAq3f)=v5^f{XTfA-!r
zRI)5P6WbAWGb^f8Dn(_dN?D?$*;SnqS>=&^Tip^REX%9PHFCB_GASY1()7UGl1Fwk
zZbKSm-1yJzER~v)5F*uXa4{ak9Z?=cduAvb{SfwmLwMS>hsLx(eu5!oJjM?UGRzNS
zjO_KDID6k%vGyxYJWkxmy^=T)XT82}t$iMQN5qYM!jE9knhdPSrkdI1MeeMmm}P@9
zMjWUk$T+YxLZx+(hhS#wsO;KnBv@Qok5_QrCD0Q$04TD;zen%jAZ{<bKj(+zhct-E
zfl1#~5SW!MVAIU9h%herAxc0lh^j<u(y)XKD_x(h_H5n(!XqmSw)V_sAs6c$Kbjn0
z2WT5g80aRg1FZwsrvv&9QNw-ZuCTn5au6X<87#COWc3CT?hDHxxD`cZ=LkZSGFWIm
zEMX_^0!v9O97HbO7xRkl!lyKZxHzoH7I#5#Nh};hF6^*4Yy=@FiXu{h7K_D38N{q1
zQzU|mqOx;@MU*lK*t82`i=uOJh#Cv6vB-RQW<YJyI?y`MIuPl=BBDDL)hX9@Dr0o5
z>u}eaeIp<3z|>Gw-;~$71CP3OiJE^`)ud<lW_ge(gGD|MB3Dx4jn;j_5|YQ6)xcUf
z`4R{_EMiS~Jj>Q4xwdTW`;dET%hp_Xnyq!9b)a>ibzrpvZgr=<K9vs8p$j=bG~fa8
zj-|G<=MGqOgF0*n#BvNvyP{yauhxL9BSb2Lh1P@U#U8=DZ`c45U8#UUT9~?p)t5ln
zVHtnf8f6BWEDjq%5sIwTe#bpB#+gyiLc+KOtVO&S7k~7@kd;feMh^y`!66(C%+w~{
zcG20u4Al`okYxgwqFl0v&Q%O+4r6toJ4nU?Z@8z`f&TJ+=%U7ft-2l_x)mK>l$jlc
zN&`LG4$wHvMuI)w`&^RQuugTKK^=Z*$ANW+FSHUd#cX0MXTTjx%)fcREP8f-H9e2a
zx;=<oNgWK9P>`Z*p{)@MCtm_#hXv<~#S3rH8iF|v>w_{b2rh|*gUDqZRLiZP*r`h!
zkqXRNEH=s@R#rFDMIyK;DmzD5L@9%SO}ikrC^{F1s7f-miQ`vii;^$0f`iUg6&7{E
zpWBWg<G?-~q0&0Y9W!%vsJr$W33i-2dQJ0=mst(_=F>XRI?y_BsvWR{3LEK~J`SuK
z)S^QKC77`q(_=NcuA-!7_Z&rtR0a#J2gxk$;8qlsog)ZQ%3z`Ou!Nns3oIqEa1gn8
zU#tncLr!T3adB9YE$)Kgl2|y1TuZ<q%U0ANQh^qW#YP##$|_SNg0r#(tVQA|vn(Qv
zjvt}~%L<4Z3$3y6i^4is@`nLDvf|hpWtNRf8*ijd`?QP$`(U3XZI%0YnQc{83vL}~
z9Vm6cl^phC9|?Ax`FBkVkC#~u`{r|)4%oxMtfPzs+t2dX*&M-smYJG=7YSotu4nhg
z5F(YqLhC^?b9%UCWeZqB;yAM`BpZnzmLH)6!VZgCooEfgFAnP)l5s(BPKb>b4k8y6
zyy|gy78Ic<ibw_KEEXGO5G$+9Cz1#*iptIr7E#I|VAC#$EsD;?A!@iXwc##EfKfpf
z+9-J#iV|T)%kM-KLz~03>VUmgY#Z6uf!2Z6f!2Z6f!2Z6fss0Z>9LwzS8-7jb&euL
zDuadAgUFSXnD)c1C@MQg5Tca9LhE4(J8>6SN@C$4a`C=c6LxRoDGebm4lA<7T@YLn
z3kQ+QP`AEuFbG0W6h)*0Ef$N7GKiH`rbq-AMP=s*izsCfuxS^>7Deac5H%KBW0Cpb
z%mCP=b)a>ib)a?Nsp-JQ30Hc`wVm*=wbEJ#M(=={e^)WmvwMRDQ)Jq2q4gkgCDoR#
zxt^hKC9!bu%_Z#g;_%#-t$jD*PuFYN+CFWKkK*;#+T~e#y^Cn<*E@hqOOsRWfJI@k
zyKb`J$2?ymSo!(tPeAy!m;&h=(!^XC$8Pdg9)e)W$#B>lvm9b)dxN)P?$N!gZ&W4O
z+C-;RHUf}xfif#8W(ZOk*-V}BOA|eSFo<JAv9xfBjdkrUehb(%Gmy&4;$<~}oxiR`
zYtpc)>x87DXB|pzlVaAzyvo}rc!givcndFz!vBdi92a2yB0nDX5k7-3xM$cJK;SAh
zKB&);dD;TjgJ@<MyrpRoBg`gUiPofHLqpOogP9cr6Atr)e$VQWU~%vsryPKp8>jM-
zVEfzaI5ihhafR1+#A4Vvdx+aWm&X`Fq%v4&{ar@i$_Zu!6=e%pLh?AXA}rrTES!7^
zgdG-jd(;|&UmR9si@P8=D^X^AO{?l=Hghu`TL<Xa2sJ*f1FZwu4(K~X*1b1|w-EeY
z0s4yD1tzl&zK4ZPGXs~BI5-Hxyss<Knl!A)rkdFS0<<I!4kDM2@Z%CZydnE6QYGGX
ziM+L=-^DlxYyhz+N;Dgak`Nq3pLk!5h1NL4sZJ5JB3s-AZY3c&h+L(JW^Wy69eAoc
zfcFtkRZh9KQysHwRTplyO-`!=Je9+ou*qq40MqKo{JW}1J-g>Hv2YNx?l6N-FYWdU
zn`Tx6>);eh=uZV*iPofHMK;yU4iKOvac~g1e1vMhH)NkhD$rta*eC-*>p?P0JGd1^
zW#<ToC}kjMJ*>k{+y$1B5FA7<-dAIxH4brcSdlI6g5Z)697L{CM6<UJv<|cmv<~dK
z1Gp+TIjs)Nj5~Bei$en*5bs!Ovj?oXK^?dQYI0q~C-%^@dsbGg($Y)2y~3uM6=AtQ
z4o;#^yss<Knl!A)rkdFS0yHZrW?hh2^Z>0W_t-<xVx2>zG7z*LL>~?g=6%Bk5DPTX
zY$$T#m^#71m*B9&qQ*jN9Q^VP$+#dmCrM_xpk`|wXdO6#4pdz-cVFi?u(bO^c9ijW
zneC{+mSz_nz?5SI83z{A+vAipvq7D*<5W2kEGEFmDG6q0#xY+t|E{V*&+a))EF8po
zAb_Noc6)_QGpm7ha0(^#r-H6TYtpbHn`&kU2+)!^IEY-!h1lA13?5Y?Qh^qW!$uhh
zT0h2j;uY*0)`3Hu87w6sIQSAAc34y;nc6G@HXUQcl!V~0&a4!au;b5dN04z~7yZdO
zLcs;dT{FYcF@lT(Ye%TG4)S=J)$wm$tplwCtplwCR~@idFAw=@B-nB8=rxT^Fk7nC
zw7({!p4}s=Vg{dH+U*rK&8!C2!AbOq_jM&&lZF-9)KaMf1ZYVd97L|=!fS2O1COFu
z_7JJ+m#zA6aDdx4Yyh!96U~MqD}3-19B>kZf#cU|EVRb4o9+}rE3&C(b}n$sN{U%F
zC~dr*Hto|g4lLmyI7&HQW=GksMyhq-ggSux!U!@BtUYX{R1bGxX7$9Hr|Lk}<WWWK
zLg99iWb+&&!S=KK&H3&<BFjuou8VXq%h$7eR*Ho~d<Gv@2#1ADGb>ihp$<-hFz@S1
zv?dKJvZ-cvfB?-(idh$=+MiA3jfxf<9E{39(0Y)}Cz5b0iptIr4pGWL(0W*howy4u
zB_TM7T)eNwB2$}1f=$O5F(n~5tT6*llT+(}JGFvZJ*@++1FZwC1FZwC1FZx5>VTT|
zR{^QnJ)$aR@ad)9USZSBYG56lM4xzHSE4m(SdmRNvjYTZNgNzRuH`7KEqdTlB_b7Q
zu{dm$fuQv(E4|orFz*{SfLNf3W<yaDf`c!?VTVPHh1NLu<r|W5L2yY34r|P+n^{WU
z?5zW>1FZwC1J|Jg4!5-vl~b<mM2D=E)jDt#9Z>V{Dpq=S&tYQWAZFbGB)zoTD{Pus
z4XlGxD51ZP=t{IE4J)##W_Ex8Es2AJ$mJtc`@JFiEK;>)D@JrT%hpL4<81$XBjH($
zU~gzo$JGIh(N^NNif+M2+5tLJUX9i+I^d8*+$u|1>3Q~0vjNswL@L9|Ou|j%jo?7A
zIcA`om5<rFQbM1LmExAhKdq9hE!;5Ig7(8K#W-81`Q%1q069bqQoImC=6GqaWMvE3
zG_x#XXZ%8hFdGO)QHj>1VfAsM&IaVqOM+P!^pLj>|A7{MZQ}_)%5vU2KFh9e@nZo>
zEFpt1yvUXS(zyyv2<lSgHe0|35XCG9xU_L^6k)dLO0*^o8yb>!8O*F4826yKdf(cS
zU~$SFryPPAu16!tIIwnvN;ia5H-KXNf<4r&6H)5^FlVKMC4gv+4}x1(7Hk~~>p=(z
z;*JPKR$f>yp}*zmO0*^o8yb>!$+Chm%8ZI(&EYzBpg-!aBlX6)b>M02fW9Bpbiu+&
z+!c7g;&wrZ6SuYy1WQRQ90tG!5D{BF+fsy?1%Zk%XiXYccYSxvKrB87=`6X8rp4Z(
z$aqN>NmT{NRwYAW)6A-16=9CDh!h5`NyDm{pF=v)GboB82mr20>p<&3>p-RhywEyX
zIpx|;cF<a3tpj6rz>W#tu=mx0<*FjOWGF&fc!<e0?~Cbqd<IX5i%<JuDT#%{0N6CM
z5@Kgpgjq|l2!qz7VRhF<RmfW<f&k#WsP=n9_F2<ncZFe*L-5ra9|YH;42AU|4hW*z
zMMyY^5|E3<Vj~P%lZI7YcSyGzX2{f}b)a>ib)a>ib)a=%R~@jsO0+>9d=c(c<w$CC
zr`q3ESK@2U`Nr_9-oiu7?s;EK&*L+ALR@^>4@*|IfK4;YBEpCzl_JbK;)gV7O&V4&
z)I>7@Sd<jAE>N|<nC_B2G%Z%D>Mbkf;A@Q!f@@YT**X-~gE%0FW<!yc`afT=$fHI_
zQ?7K$vVt+itQgoFS_fJOu6GA;Ss6h_g2g5CIOTYm9cRCuPF9$5j3DE{(g>B-LGGBD
zt3%zj*GRBfC>*CGm@V&Bdj4HggoTrssPn#9IH+}#LkM9LUv0or5(|d`uxVx`#Llh=
zvzA~H2CYfM>aL5bkhe+%f#v0FIohiIRp~S>4pSHwxmNjJC`|~0Yf%Qm1`r1X(d;55
z99B!{a<R^?8#1*y_zGCnb?t(fqQsaLgW?Vk<LZ5DM}oy4IUlF&nA!3yKX|F*z`BFi
zSqpf)%xWuWeyszo1FZum*@5bL^lJ5Pb?0!eM}i&aj$YH&1T$9i^f<a?C}y?r5R+@(
zub9CT;^ONdSW05yFaS2qtc2Lv6=BvAEW)5QX;|HLQ5Eu5i68*De&IFXZ(AM5YFeyR
z7?zcC6tu<%!8I$6twUiw2y)1y4~nedoQSpDB1#yvCJl?M#E(qRV9iR3SvDwbe2_Nn
z(=rn5jeXX%Rqo?uwpCdzxOJd)pwt0e(?^hTVBH9n)<GUGvpW9G>mVJ#{B8sp2iA^I
zX&q#iS#-&e%}Z?UQi|C<D=SuMh)vAtVaW-x(ZXQ>Y?>JoW(A>Yox(aolrU&b8di5*
zR8@5Zr<ipeQVS^1EsCbaA)?4=Nf#EGRRzdaB?DnI%&K4&VUDthTs2%MO$JtV-65Um
z85BiXCD6eki7SRRhilh?sx$rCRn-W$4zv!m4pemDxeA}=(mK#O&^q8dz|-UClEK@P
z&lVOjx#oQ_J&(`e332gt5G*CJa2NoaW>!M%?20gJ2^L|{nl!BLx~K|yt3(h0oL}Fl
z_E)9Tv^Y#*SmY9XwZ;d*wJ1YjJ%|H>Xm$}24x$9)VzJmvjPoB?Td#@yIJ1MVfK^@B
zE{G{ggc*9&WZMq(qs-&mq;;TmpmpHbJ8<*Z32wn}ceS;}?-s+*LR$x}TL+>`hGG#G
z9%6FM`xP^ILR@^c0ZU0N90tIqnUxSbyCTe5f<+iuLldD%!|JY!s*t5h6r7Jz3n*{M
zK5JU+t}rZe2)<h5gWy_}p|Bpr0YNmo2nh#K0&=lfY=l8;(y*%Q4(WEo%yhYsugU3j
zU~1@eifNVj4&VyX<WxJLZUDtX-(U}M8^E1{#bKii1Z@v;)4zclG*>}z%gS)rD-a6=
zaYxKTvhgufCpd{d@&5YlF;|;K0s$+s#e0UBoFtiX5Ft=tK#`Tj%aJy5gr3i+LNcXg
zAz|DCHqESvYQ8j41K0&^Qd@l3MAwzeaAt^HfZmJzc*qY|^&`iN-tkqAc)}0U|1L$y
zAPjG@LjdVqg(d_cQC1eiVFQR_mPPE0{GW>{!Z4s{VbGd1Y-mW@r324yQp~bJ86%E_
z5o8?L`3RNPK^}rxe|xPXv^%eHVBPKt*h3~lPK>$3i*R+vPFDC*ZQ+2^Crljpb;uwL
z;ub>eCU4~-2$rmD0UJORvn(Qv=ll>QAQuZ^BMe%ThSgo)6|;%4VAkZcI?x|=r&Uy|
zrgh+SJ3uH++#zaeb#M|l4&JZ1U8oyK2tvk^I5-S|4Im=6dbSm&557;Jp(@duG%O*5
z&*reRLuN>4u@MxZC<(zq(Bgeny@QwFt2H4Az9k_z41f(FA{NZ5M3jJBEDjrC(3&)?
zMYQPp?wBEUlh%ROf!2Xo2hL;4>#w_o5>VUy>t9Q&;8;6gkCj;CHMj$Axgr@H-vW=a
z1JtqVwqkN!L)O7b%<g%=VwIMe(<5U^92^F~rkRxxJG)w^K&w_KT9bw)WDs2!RrPBq
zIOQeE3?UX9K@p0Q5F7+8-d7k7UV^XIgdq5qgy1j$Hh_p&Fsl+#0&=l9eoR*lXVA!M
z)36r4qU*b3hSW`lcfhWO(&|oo-8#@Z&^l1l0bAqLe6Cdo+z9I%{z}!!%CXdjxmS~2
zbfD_nn!5n1&Oz`Llj~wA&*~kVR%iFvuUMsJ=Jd#rl`UY?%(93u5<k>B1qQV`(V8?Y
zvdXTDX7+0+IHiTy6lI1Gi;bWNMNS+a1O$imgF#_9cnQ8*6N2EIlWkxFh@cE+MY+cw
zq6Fk(ao7lh)}&!AqD9wt#|){P9A5|Q@lk4wu4@Nq9O5IvR$Zw_>B#Xi8>Jl$G}-~o
z??#Z3U@@;bPDwHw)+x-{Mv!q}?Fg0DK_-|{x9Z`oUa3Hr6$h)B-Sd9MDlIdoN5+yk
zI1GSIGb<r>cC}7{R;^C7CJjr-pq4ZiTAvrMixOdGyP$6CQ&Fd?*mRD976&N|hfJ%Z
z;2y1Ou7Y4G3Bh4=*eehbTRr7iEuqWBEF7q;8gjKMSc_=Ub>#w&qO20|%!)yAhXv>y
zUPgk&A2}bV?3kGyr^=CFaTXn?951uu>{nyeI?y`MI&hc{VCuTLjC4&O2i9)hp94jt
znep_PKmr{LYb+>A;@}`A*SsGx2!mMlWajk9SP};Zk)8J|VAC#0SQJqLazWJUL~GKp
zgbbqVqN?iCEy9c*Be%syP=q2YOo!kgXz{+naPSg*wI&3?H!EAf1`t6R%!*>!LzIAA
zEDjrC(3&)?MYQPp?wBF<03pyhyo>~U`|y=kA|5ZZ$^x2O>p<(kunyQ^VcSNH1dDs#
zamw*BJI;QM$%;k;@27%?#vcdP9lFeFyeu<98Zo(sA}c%*c5o20d)}{DrDf*y$e5Ka
zVAIU9h%h2lty5r7s}rqB!xA!xu8U??9l=Rv7#IrxK@p0Q5F7+8-dEK-c&+lyeIg0p
zk`Np=hs`i6A$IoF61rThb+D`&a<vJ{t3i8U#-k0mCa2Ybsx$qxO1?hTxa&i;F>M`a
z9cUeB9cUdm`3~?@n^2^ff7ev);3OvMykD_OlPjr%!KRs^j-sfA8zRJ-uv<|mO&XSv
zL6k3=Sv{GJGDBhu06_?fk`NpOE#6lc4qk$<)`TGVmW1Fi05*V#STL&+Q37(YIBbML
zYtpb5(W2`+Vn)W^NA4!A1FZwC1FZv3O9$?paG|@at@@sS!reT<(lCK;(mJ3!Kv0Rv
zwf4~(2bGxJ^M1uDEi<P_#*#QV41i5DD<O7vwN8OntxmKi4NJ%%x-P2f*HCcEOOzQx
zEH;876eS@z2wJ?aFdV!DU#$s2@GS|!VE}9Z5wT!aC87l6VsY3AgVv;BEuux&SC~=v
z3&rp#3KN)Gc==pi1adVwtq$<9gfVV%S{=X@q{)eOAPlOy0Tc`Um_77tfR!uvhqe1o
z4|2y?WcN1$!j2EZ>#Piiy#jGSK<O4QYA#mveD5gw#5&85)k<=;Irs`#kxe&qD`o&g
z0)YW#UcL}%6GsrD{2)2(s6w=c;D?~H42LBok25R6esV(%U>CDVZSi3fUDqyynRS8B
z^7bu$EHJ(=cB;~be>fM85BcHnBf9<XQiKe`@Pr+V2kBgeCIrDPFT-I2h-Q|DWb3&x
zPvGQB=yLHsihjb6V9=TjtjMOC+2uv<tfZJ_gEB@Os3XWYurxxYb&!W(X6vZz+G`}(
zy1T}%i>=Lv>n_1r+;^bJ3jZFxgM+xe@cx`1jvvw>ZXrh9%0mzWv$6$j01=eItSAfi
z5G5cNL{*|SX;?xA(e)K(^9~RmSy`~PXLc5HvCi?M$?<i7hEtlES@++K4$sgcTL)SP
z4%-2Jhp53<cLfe21S*4t)`R43y6`KB%FY3VAZ4)7dRW3v+y$1BSU8AWyuWfQT;Acd
zh7cEr71^RLRrh@h1d$607Ke?X2t`puD$ruF*eHXTHDroJa8Xotj<ASQ1_7IPL2OZU
zE)G#+p*0qn56=v!O<D(92U-Ur9auzkr=mLL+D>JRu5}&mTC;EDqaBzUit3y4T6X|5
z@5ubSswO?VH_L-W8SE;ETuF&HTK5S{NFHZa18d<V)+xL%)`Z;}Q)visaafTp?t<Ww
zSU8AWeT2iaAk-W3Pa+j)u~=-BL9F>QMIyK;DmzD5L@9%SO}ikrC^{F1sIkx*i_C{-
z2Gl041FZwC1FZuib-;~;+hBLy0o?tAP<VBq7v~4U83X26YCC&wjOrWaK{}x3-$hiM
z@OpM{3?Wh(EVLd(uB0|wwr&AS;1Fj9OIDb=g@Z4Fu)`wOgrh85Q_R55VIwF)k(Ju-
zxJNpf=q*}Slr3N_l8bTiV_ZbNWDgurjvrTj;@3VyFldcsw>WGF>Rp`wqS;km#AfA^
ztx;y#sAfE52XK%yX&u;o2dXZarvi)1+;PhBGCR(GJ)Nv*oU%uP#cc98CCQ8i@$Dw_
zgCe&I8VA;G#d)8>DP|L68CFgEtElMNy)lGHWw6kCkgFAf*AUFr(?FG-gF^;A*;gRi
z1@I-Ya1gn8U#tm7S++6>%MZzH;-Fevj)8lXh$8z@v4~U#(aD=?TtX0ni=wh~ghiAx
z2-vg>VvC}4afqrUQyWH|0HcB|v{CXf6eY^67!`NGpWBWg<G?-~q0&0Y9W!%vsJr$W
z3HHEubX(uH12d~9);v`QtkN_^>p<(k>2|;lDs7}|`Z%y|P>T)`#LR3Q2h(FUxsJQ8
zY1KrX?F1iXu+VxCz1Sm|5mY5AJ4X>BmBB*mVF^2N7g$PS;UIGH{xK|D&tlBpMxl-$
zk|GpY!D%CkL>?B4jWURpRid{DD#{kH7RjT`il~k~L<zPJQAbIpHc%(TsUQpOj+r6l
z0J$+BW(OhTz&_Xk^ZleaUS|8Lw`FY|XdUP~;Ku31NU&qfzxiHXQEikNrU6ZkvjZ5L
zej0i>g7$Dwt4Jfk9=yG)HD_OEnW@QjHWiFmu&IeU>xduPV4?LOawR3E{cy|57O;fG
zin4{aB*YFDPQC=f4h!g5yzmCCA(-Q^J}BdY;G7T}EgVEHDEu{CP=ui<A{CgkSZtI5
z7Ze8zKr)|5!lfuGJ4aYVDT9DbyCAkGIv0ni;mXt|j$fTEO1{Vn4my{i{&&Bs;+xZT
z>43d1L>tf6f!2Z6f!2Z6f!2Z6fiXLP>9LwzR}oUPdyXPRDuadAgJhO=a4U++&Jlzt
zWw6kCSi(-+1(uRnIEY-lFV=+J+jvSth>OFDY;hL^m&C$B<bs0PI6MnNP!vU^0xcGc
zjWURpRi;P;7e!^~2#Y9X5U^<%#1=*8;t(|!T4Ry<u*{rs7Klw+2U-VO2U-W7mJVE;
zaG|@c&7E+kp61f}Y3S43f>yigfSP|RkC;Nw?u{WhDuadAgUFSX__PXcMN!!~f)J$)
z7FrKW*onKqQW6UXk&E}mn((-mt<28xLsEpID56L-jKyN33}Vff=q-Y(L}lkFi%4Y<
zuxS^>7Deac5OtJjjYZ}vX6{TJ;tY5nu|<h8tNRZJi@BS_?mBR}bt=0&OSjI`5*$?r
zZ~`|uu?|>YPxnIH0K6sj{FrYm1f#gU@c#P!LEX47lx8Ie8FMlmb_GOG#;m6(Z?Fd(
zEj)dn_@%@CiXmH@g0+bD*$6wz1<I_Xm?3C|*s}U;rq1}Ki5@^0@+>V}^ex^8!J3yX
zU_A%{LG&*V$=1coY5=<!U5VDDVO7@&Nq57nqxULrpWqdKZR0JxC<^~4)^J>a^^5#?
z*hlyb!r-1^YXE_()cBx2N9Jh@SP!C^W$>1!MT{_;bR}Aoh7Ao#y9{Pl3`{u86Z$=?
zM}oz{dz^9rW^SCyM}qC%eHf?W3RGO-^&PPoc+MW;HqhlUh7hR?7FvIo(YJDf89_za
z0+x_G&a4Q_HxUabUjku=Mcp2?hTs>671`o02+m51SyeZ)nVa$0I$)2DP~+1&&^nOq
zfWAXy-Fu^Y-vRoH+XW`G4!(zlO)~?Rk~laB!o065(V8@@$flav0RprnAHYH6@)7E8
z?G4#yk*c2-Iz%V~LF+;EyBH2;1XYR3&QT7L%0SS1Scjds3oIoeIEY-luf{@a9OB}z
zB3s-A!6hMfn2B7ah-PmcXdQT}JAn5QPgPF2wo@ImYgHF+woOi}13Z<(1iZ;<bpX@q
z$o#viNIkpfu!>b$dTF;;*fg^mSO+Ju2;qHQiPofHMYi>3UUYx}Eyx202a(H1h(!-P
zszjs$Ef$B3G7z*LB(t=GTTxVYj&O)l27=bZI_$(<U?~Z~LFD57^|6R(9OB}zB3s-A
z!6hL$h+L(JW^Wy69cUeB9oTaRa8+({aveDI`et!*9lR=NhqXPp%DVY0%*UIYXb05f
zx>zT%ho0TDvSO8%UfS&yHqERE%l&b15`E%*U5VDDVMR98%nlHsSxGVLg2bW+Xhpfl
z9*P$093qv0p!Fd7aBwj18#aJgpowNfkrT(%2@bvlhaDC*7Fy%rmv2bM1;IH<GRp-u
zTkAmUzzKAq>XNzpI>&*f-50W>jK|AtM+LStyXXL>93#j$u*bU!OfwtQDLcZDGUQ0G
zm;fKAB$%BU$9&cNyQ&5~yXP<*B+B5BFMy<%c5o|-%8rN%*tAO#k{ukJLJ7#lqASsw
zG_1&`s&XAd#inx<xt0sDwdEK*szjs$Ef$B3G7z+W&37kW!M<S~IK-L3QWAoLFTr7l
zMOBii%_3maF-A;D2oCGaN<j%b{@iv183%UJpPVBUT!7p)v&1#Mz+!9jIIwnW-up^$
zyv+7ham(8}&^pjMaJn6^<CHcM>^OJynij{HJ@A2Q+V2h7XEnQrcf|}oy|l~1dE-#n
zG&7$$_v~O4ed2vxiPofHMK)Dc2MExTI5>!0y!#xK7;`}g%B)znid3M*;;>N$g4ToR
z#h!y1K}E6bp|Z2i@k1L3S`X{6qhbl#qHqp^lgP#UYAm$IAubLpvc+8xoRuguBpxQW
zhlOn$H4ZEt?XvZFnQc4LExvW2bs*n?;g|1x-hy=;SX*GVV>8v~vrE@I^%2c;tPWuI
zG>*8Z3bvo+k5h9NHOov*uCu9N#A-;-?pax}N)sz7%P}Dcud}iZY?@gX5=IVncou!)
zeO-yxq+vxi)yxhMpjk;V>w<8{5`?m;yiw6&gM(2S2wD%4`9u<KMN!!~!XZi-2wD&8
zuoHKIr6dFgk&E}$SY&FmNU-S`Bc>z-hc#xvX>w{EaHm$#N!3FqRZT0V?*MKYO-`Z%
z{;udwqMBAj-vK|Yn87w_9nc+6(|+v|(Wu!yd@5$}VkKo)gYdd2Lt)d*ijeH!;3WFQ
z`??aXNyCb4s;UkUparoG4kDM25Q`poREbChS}YD5Wguuhh+gbDnD-4EKrGNiv!N&n
z!NHf{u*0IpLTeoS@(szjAh;w1hc#x{ZPGf>I?y`MIxx5c*KH!~a9cZ3Ipx|;bjS`@
zRzLeZ9AHDbP90G5?<(?ocF$pA;UH$+0VKV&+be9ESq-d%Qz)UokLXIYCJigHsb+S7
z04<4wgUID0RQtUl`z%uR7Y>IAWguuhNM>mVx1y-*9N`e93<Rx*b=Zl!z)})|gUH4E
zYAm$IAubLpvaPyILS6)ygy0}@l_Hvbln!8wwi35hbPGPx4$$S15^J<}&;f@Wt5^48
zPI{hQ)NFut7NN?pGLvu<c_TOwY>pWyXXRtIu9VQ{Vx_pH@lUJdY6~~awV?elOEJ#Y
zX+F6T89)vZgA^}>kU3r&ELqtCHq9)H*crbNA<PDXQB<NeX;^)nsIvk2^O9iJ1wG`g
z!+)TKU)y-XkFuQij?c2|Tl`pn5=+P+3@@@JfOM`x6N0)Fxy=@^0Yov&0WNLa8%3Bc
zx)QBP!-j^WT?R8N2gW@puHLtHBv_ns$0>(khU?J?G7hXAq0$W@)eWE+zhDn_>qL~g
zKg?O_U<n{v<AdOql?7Xe!g>$_g193>k(C$LOXzPox)QBP!-j^WU9zlTOff44Hiv81
z0e9^fH^Qw0Pj?6O{h+2F7Ea=>!21=q3qqW@wS^#9N@C$K05*V#*y`DqBFroZRD?lm
z(y+SgyJH4o@i|Cm$!#<(_7+9POR`9+DnPa>848<bRt2jFbCgA-FlbF0R?Ykz()B%i
z+~tL$D1rdsnzRnI4zvzrI=~C9la*7h?PLe771la1W(Vw;;0=3U9ayd^qDzJ%q=ko=
zT=RZ>Nh2otggBuIL9mp>!eIbx01>g(>j6cWSrDiQgVv;Bb=P;t48+>9wd+ED6KlCe
zh%ji481+rZ82O7L2mr20>p<(k!8?HSu*s=)z@Az`t)6Sw0elheROLu&bEn$hR#)O{
z&H2Xg&D_F6Os;vqVg^r$i%<Ju$;uY6X=YhO7_q=qgjq-YkOr+u!|r0)nqmfG1D36q
z9HnWoQdMtRDF<I`d=Ol-a>>@AupYz#K{OkRtknPcf<+#2sHb7GpSCWuWLd$OVpa@n
z4x@AcW8S27U?&~Gm2d<Z2^Lq?<CNoNcAWisI$2@LF@lT(OCwZT2f1Trt`2qAUL(OC
z@AM_XY<aJWE*XkLV&Ng?^1Lq=4)Ga0Auc}chovMI4g+A*%u0xzT@hw2!6FP=lZMq@
z7gZr|l?VdM%h__YRr{;bX<8hnFf4Md^1V=+5Cqqv41^6J4hW*zMMyZTmeA#5on1F%
zYIE=vu&V3Y1u;d5F)Iee9UjKj`__&Gi$8KcPT4WD<yn64QpbUH2d{JaR$3W$3}$6k
z%_G?X+-jP%4zvzD4IRKo02_<jIASLOBf*YyN3ZEvk{LP`T{0B2T6l=bHSbr<;0bZ@
zbr38iv2Yjwn`Tx*?Cgp#YY7%%(3&)??z*T7d8<SaSi;TkA`)Xxc;P+pIxCK?niea4
z1~??f*utbLsG1@;jvNY`W(Gc4L4Oos)>%XegVv;BRo5NTiNgSjtfZJ_gVM$aY12L}
zBf;L-XH8q>K3-;9mDPe<2U-V89l$kx1Q`d`jZi7>*ky5Lm*#Oy9l*@#@Phf>2r>?=
z9ih@X$Skwyk|CRy*xIEOvwK#G>3MtxkJ!XI2$q}>8!a3Lz^0iYVO9{T)+wwbL<xh|
zq+xZ}MO9TtaEe*iA=Q4+EsCbaA)?4=Nf#EGRRzdaB?DnI%&K4&VUDthTs2%MO$JtV
z-65Um85BiXCD6eki7SRRhilh?sx$rCRn-W$4zv!m4pemDxeA}=(mK#O&^q8dz#job
zmki#Xe73NN$u;kb>3MtxPl$`JgJ3C%g~I^YG_w+7XIF$-ORxxo)}&!|*F{yxTP1=3
z;2^{g)qWU?qG@r6!m!9A_-c(0f@@KR!g>$~1kvmwBpgHu$i-r@nHc9AXuT%VQU_lF
ztGcdT5L1*0Go)^^Z3p^M=J9RPI?y`MI&kbAxOwaZx8S$C+He<c(mK#O@RW2Qx@0KU
zZs8#&*SudbgD1qrR~xXD#KK_!Y?@gKv9l|}tR+~4fi*M{nl!BLx~K|Sszky0D7Ap{
zhU~MZ#qJ8jB8T9sH9iQgMHvd~K^zc7vx|^$5G5cNi^WD5v?dL!y6%vUncd<n+x!PO
zNbLC0<it8KHFRPXwQ{%vkNV3=YsM*dK-~a}MZUov;s({f3+WK43<PZta?`(o8Z^rr
z0fLG$9QF#t0!7>rOR$fbI>AZwiTBrUkGa|`5(rq4E#5Q4<Rr<Ag9w2F1B$FHUXHYh
zBlLVm6_P0}3kl;EuxVyRRP&{Y8o(}SliK3LCc3U%hBHIt0`y+w$3uR&svkLC^p3A`
z#1np){&y)t24Q%M9Rf(_Dl{PoiL$a74jVuevn*m~<o{eu5rzRp3xn3AVM9aGE**Gw
zlVX+)${2AZj3DE{&PS-U4)PGp`rB(Aq1}0n1M7BIz#cLYj(?1~L-KHS$4*xGQf=XY
z@Gx=U*CB&2h+7D;o4l2WAXu`p1#AFO%(93up7TSLfLttujWB3U8di6GcgzlP7Nhtk
z2kgN6{b6@N$OhFq&^j=@1B6g<hp5Tr;3RGwykB#>P&beegp4I|a2Nm^KtycyY%5G3
ze4ju=RiZU%SV9J$&0%MU%#hAvBPc>q5`u%E#rvvy2QR@_YeEowOG0oM02@F=ESOb^
zC;_=x95%wBHECFjXwmf*W;Erz7w{;GAkZ@_1~rG)f!2Yiwgcy<S@|uLh1%|)W__)y
zW9WcA1`>_KPCMY1E0Ue&Y{|y$z@;(NG3d4{lj}}d+&FlM$u;j+tkRNmdgLpMgUbNe
zG_x`$d#H5^qSWd{YtpcU45I6zs_K<Wlo@hcYy?FpN<wfDw0K`(ICu%ZS`&icTM~l9
z0N4N`V!^CRL<z{n;`o8(WoY0TG_u+>tc9=W`i_`&iIKd?&<@zuKw8~tuUiLH2XO6f
z(mJr#fy=f1wtMY6fV+Kv_di@M{FSPcm1C(56R{?{=s?xCHFp72orB;hCfCJKKF=MT
zR%iFvuUMsJ=Jd#rl`UY?%(93u5<k>B1qQV`(V8?YvdXTDW>#HAkt50sxh*z=A{04s
zd=L;E)(-}S;ov3sYE1}&Z%(#>4IqLtm=)z7dx#Q{i^X9h3|f<hwTKp7UtvaFUU+0B
z#>{3TnsL+)V7!M()sZ?Zb&I-|9iVYoj|6+X$N%v%8|MINsId-=^w!o$u*2_jvEJ=c
zmt;1qQ<$@jAmhN=5i0HH+6CkUGwN17ywxie=(6Hq6|;NZuUMre=k&-|76+FBuxVyx
zO!iRg6hx`jiPofH2^m(FG_tB`-MDg!2s8Ttxh*z=A`~SdI0#z2uP_|ER!6}-TGw0!
z!BP@}!{)G8AR@MU%CTBPmy20AP+2wPYE!Tl(W2|h1s+9V0%YOka}^_!4hy6>yo>~k
zKXN`!>6zh@unV!fNV0j3kzjEa9jC;Y#dOEXzOmY%1Gp<RIkpbWd05<h0a}yt#Wmd7
zkFAWxXSD-&c;|Adn7)2)m#@;>yXFy$ySnb~Do>hl)G`jNjdIzO^7oB>?ZcUw(!1uO
zc(U5F=?l~?W+H3|I&=(a96zeW!7E$?`k8UaAPi#F6XxNB1P6mnGXssHh!T(s;#U-e
zo$ioRnlx+(5-#U|X=3c#FU&u9?w6^25?=EE{P5h*&&*mbddz%`#YPZ<A}d@2!2z`d
zTKrm7?^r1ZUu!}Te6z9zYyc6Iar70%vWGfMS?Bm64O)|iwTKp72eXep%Omy9FBp6F
zncfVylvv9I-ki!2OgWeJ1UiS8kzj8hu2T1huUIqXI&Xe>&zkN>iF4pzW8>_3Lph&j
zJCY7e%<Ig=63*Vd%s-et!xs&>H#y!8$m!4Pi%O>D@vlo{>)dwjH4^Nux>nVWx#1h!
z1h?|?jEOzEyW#UynVZv?9l#_D??X(#TK*8{-MhE>KL_mQy}O_c=n-TbSa--u?@q`#
zu5<FPdH;J$!0yv7eM%FeaiLjVsX&(&KJ^`}xK>!a=&l7T8H53&LGbFXW^fgngTMw5
z#SFx<f>1>m5vmfcNy8E{h^~X#`B#lIpMHLB?)@_C1(};$I0UYm3pg(pF9bzz$vqQ{
zf)?*93<s~(PUb$5gl|a*4x7Vfn3WJa`)UbYF4j6&Rt>q@1m)Er!EFA~&rHo?@jX*I
zd&@YuWrfZR-DXG2UQ<7U%abb`*Nlhjz&S%*{^2WU_ss3PhGs9AIR+{#d~%Xm{?(6L
zam2~h<oG&pHaj==_U{&nS@VO>7(2H`$L2742VUTl?EzSn{|7=hC!DXvi}mO=J;elg
zrNT0wnKMUt)y*Kf7s(Cba%+?3W;lutOuC!tg1O*RSMxb+vNBzm<-w5kYQ`};FnQhC
z2`^h`4{y3}(#12sGbv7eoH?I9cx@J)S`liQ@&k(=$B!y;@WMsi;zgf0WDo|hBX|Ks
zuA~kIn`Q=1MG+++7X(EMgVv;B2^m()x3@oI?qS*bAN|;;&GWN|)^;v%%ZR)8^M(ix
zK9_g4cp)fyOYWIq^r;+nSVWQWk{tZvqYg_+2o3{a)67bUom~-Tt%F4vv?dK}5xv@V
zdY-==`q9taG>Z>DV=j3$YF>j&LC$!6Yb>0ua@qTZpk_W?2j-ahE?!~4yZmV@uSV(p
z3h*;t-!?hw4$NoN^LyQxPxxYo6EH7d!|zq#zZz?Dv>hNrJvaYcq{<)Q(OJ0L72Wsd
z(9PWUmVMmBgKM+ky<DkSGduI2wsyZdohykw`Aw$IqkLlL5;fbNJHW%r7vDK<v&B*6
zDexVhvMoRfQ@19^*#Y8ZtD%QCt$F+6nMuuz>GGWiiSv|D;*=j7U7{VL#O!`GgD{9m
z{>nU@0}cioYE#TmM^Qux$OS<^g+Xi5u!Ibvd@%cw_xP(0|NULg`|zx0BK%-B`*}VF
zR&(Js#9|{TLQxWegP_IxqR4nj4soit1Z|BFoCd(Anbn|b!W`ugDJs#LG^|Cm=sK$U
z8~i2VZ{C02Om6<fJLY4!<i(nsKjGvE<^!7bfE~c_Lf&7zLS}Y%GBuZWIq01_y}3KN
zyqKS_*>Nm2Iie0&=5onneAbQ3hh=7+%lZTySCA%0)`1tE=bH>MDO*7-ynk`!8wM4J
z20`!dS$LflT=n&>la)S$LpT5|UhwhfZ@YJt<|+uTSs4y{1>%4pm}Mc^Nca-&N(swc
zth4-BHRNh@@D;GC>+HfGwG#XB!%gR1hj}k8U<OCu+`tSWF~;dso#hLWHnD+V%#UoQ
zGz8~mI4mJ?oLL@{t)JXb1K7o=LCVyo&jHo-&IQ`LO!NY|u#**ccI6n35+Cs_zu->+
z%mQiZ-d^N4BH{Ru9}aIy_P<LJG6=&Hb}$~Ka}}Bp1h>2lhYcW_Sss$D=f*sNlP{sm
z#rr7w2|t2CYcjARn{TFh#v$+D=XV&+(AR?SsCAAaS0N^6#(_G5i~~y}R9Xl5pw4Y8
zFS}Lr;NX#9aY5ggV6=!2;UdPI9UV3?At=RtC*~z|{1Kmn0;i9~i~csy;b31F!ezhX
z30I*BK?uys7O(+CG0P&txZsB(41=mfYtpcU45I5`wm5Ufna5Kzv)C=j!rbf}34T6T
zA*Pwf>A>8)!+$D86RLopUz+m=>wdHHM+EC3ZGWE~z`5-&eCCCUZ#@vMA{Bo7B;9i7
zI?!En@7y$&zxFbn{bqkx%SFKUJUe!`Hsz@A5XvQ@@K<sNTYnoMyjBJatp~~7bm3PL
zm7N0!LCRpE^{|AUxC<;Lv2YN%cppVueguQo5X^B{k&Rutna|>d@0ghXh0ngveAbwI
z6)PNf&W^W4F6^*4Yy?FpiXu{hIg7<c8N{q1QzU|mqOx;@MU*lK*t82`i=uOJh#D@f
zvB<muv-|EDJNfh*{QblCoSF4qMUI5f?4$S0?>sVw@WX4%MkHLDdb|$2zhLagXH(-|
zoZh=%=JEKBdvW=P062D<9BBt|pTx&81b!8NgfZ{tSa2R!7URP26@3S_J>%ZxE9q?3
zUAUK<EM@+NTGrl-$I$`)8yr3XodcWaij?SmIAV>{<cK@)X3vf1Kl8h<xiZtQy<%qf
z)`zt`(<&!!9=q$n+??H-xyg6EZFx0nFEF<)$gdb)wmw*MT3(m2#efs6)gui@G41Dl
z;zyT37%a3NM6RR`220?eC|hW2#KOs!K-ggkD++JW8iHRO)(5S+ko)lF)O_Wi=N}mO
ztZ@~$O(J%@RLp?tun`oYD2k%R5f)L(AjUXTB!Y{gvU7w*lrjj|v<qU3qH}SG8ZND|
z$h--&f5h)VeC3XP{Ly>-H3<Y~<@LGy8}FTUBglUU&^IC*(TpQ>;FkHn_zfoF8|$MN
zpELJy+~mZOx#NEOr3HN8Yw@DVF?Qf)N9qrG%kN2)r2C61b6!5JONp9&-yN7d&u<#y
zjid5ghnC;yXUE^&H>H+;+YT(=?tTQs@fEc^TKDF-t-9`H<>4Js&PT-FH}r05v!FRM
z^XUggzEkt>@E>-lPg~E*Z(|fwH-{Z|U^;W0?VNw?j#s1qVlnY;K2O;(F3@kbe#CSi
z_j57r=Y8UbHdtsqNH=R28iE<win0YPA-SS#p)Cqiw{Y?$5O!E_?X!5{4O&Am$6<Yt
zbeX(*W^R9ZYVaXyStg6l@rKCNhdDe8ioGHIRQnzGNJ*I@(|EmQ3s{R3qI%!#K6m=*
zl1<|HwY{&;;INMdc2igF8ifr(mIDK`h2@FxSNOZXAHDa^yD((s@^$|Ey7%T&2d^-K
z*^p)&rvtxbc-i{?nfvXEi7@|p-CuSun#DLwpBhx0mV?FikzEqv9fzwyNpNkrEIHNM
zx8h$5qW#8!MduDC?lnN25tlkI4(r1^FLamhgRyHsLp$)818*D0+x|by$Rzs2^^O^z
z4NSCw?+#r@g2i0qU}Bd@Gjr$Gw11t(#vjY^51H2eDO@^@x2%6^>-Bqn9tYO#xvG`)
zbADrii@awnR-?bTVu`+VGkZ6-Y+c@~u-$Cg3J_fQ#ay2Ei67cvq4gkF^Kh>rn2Wa&
zI6(%&QZ&{=TO$@uf-vug6@@ow4IxfZw$S<@!cOl(?jC>Idi%}ES>3XAZYQ0i$kkn!
z&2lR!0;nh=RX-{gQOY0&pJ}fh4j~A^MN!!~!Xio;1Z>&`u|?6jI7C%4RT_)T8!-DR
z^HVc?+RDpTM3#hqh~VFQ&z`*xzc7NOptK!-B0GYN1N-oRl{y?5#3STh{Pi;I#RoLw
zWh<3Et2|tl*Up_rf<53JoyW8*^6clidAE2kFW>Ag1j~@TXS0sk0si*NOZ<^I|G&w6
z;ilrSVn&23e3NU^0msu}Tf_ApJ5@Q>Bx^qV?ZExz(xeQ+Q@KwfUN)jDs}6X#StT<L
ztXrjUu-C~CQCAo+Gs3bJeW4Zoa;1T*bFh@J=Y2dJ#k8OI2{vW0(0Y)odAQdQ%=?B7
zAcC?5bd6Xz3BtS|RutZ#HH5f)L*gz!TJ>owPq6f|bz<HIqT`1o1VvVG5cpaMp8cp;
zyjBL$$xM+5&dL_B7Kx+GvWPG`euxq*D<EpPw8p|O3hQ7|2L?flyu57v!@j9d#l`XI
z_|bc33w~b7g`Ht?V_4X>QRBcq*p~K?c=zHnIF$18fDbwM;%nvqGBTg0Sr63#TMI<B
zj?M1~IzW8kuKM!eE{D~PQ}{@*xT7ChoKZjf9HG!ND_^Z6u}w8X2kvx}v?^eW8QD(6
z?j*~`Nk)P#PDnQ{q#VFM$>hqz#mvr<j%xm0M8&)u#foV^?-M_?!9wdnGIM&kWn~Lk
zLSjYPLR%7I2MZ@(0%3;*bSz$YgVqqtaabP|clqI(Wh+8I2S<^M_c1UI&w?TpMG>jM
zoW)|J3}Wz4`P0@+ZMX{(x>GsEAH6sI<G!hgO3O#@-IF88pTO3>@tDrqEPLqyxfd(v
zLHupvb+PM;wtpNQaK}NTvDkG7a3^bWY8`OP*-lMa_CDrCO|C}=$W;6^>GEfL+L?Vl
zhLl;>eA>!xv$!LsTWUd4RlAy~a}*&`87#COM6RU7v>$FoQQ0|y5Ty(jS`SOuiMzm3
z5(@{Bi}%HvuzMR%X$Wy~SdmS+)O|^q*Qff^RzNZvhi5?uilQi59AOcq3}V@uDH6d&
zQQ0}dB1#zqY}y5}MbWu9M2&^kSY#f;469M(FA9GwJ8|&38bSWW#9~-;IAjMf9yo;f
zLsauutAKgg`h!)D&1w7&Sf<cj)@!KTu5oHUN6-P{)3$n81>Z}tcc`6<LjjF|vvqCc
zNnc(X^MT(fJhN+)<L*G1>dg3mp{klO@kzb>zk83nu<OjOo9pbP0Q_yMtI71mDX(ua
z2iAf^1lMtbsqzqs&F)t+==FdHS(%43+QDE$ZJHUXE{TPMFM+Vba<!u1o$f}cGz34i
zRKtpF>n>AXjXK1ZB=RNUKE&Z!5b6#2Cq;|hEkcw*l$0qF!9`KoIl>}J83b(F1+hiZ
zxj1BfEFv0<%yrBr;t>DnoPRu`M(%vxEDr!bf(}vLK~@vqeD>S{d6{%~mj`PR)O|ef
zj++%nyF5!*H0|Xz?0`HV`nNN#VI5BaWxjA%eMvae3JaUK0c4yz6aROyhVTjpO1SUv
zYjJ-F27lRSkPCSuI23G-8S2Q&8*E)EA>6qfqE-wxSDWb6N>H4cHTY@AqIAs2EU(vo
z1p6q3QOst(wDOmCo-d+&X2Om)IP3(F*jR@~!80RUz^0jH@Rp{<%aP$?ldeQ-(y*Z+
zahKGpMX&`kgo|9><5hm~1UvY(4gOus3gQ1D0FDdf#P2*k>|=ZeVQ}~~IDo)aYJ5<i
zBlENctOwD|GI&eVB1V`^s*<_VgqCX9(2yuI{sjF_ky!WhmCrbHCUTX-k{<J<Wv_;j
zU~%vsryPKp8>jM-VE4W-?0(;=rll`MoN!e(7;`b#i8xBtIq#}lC+i4q%3z`OAo50V
zFjxYII5SwX!Z#5M2VVkVheh1dx^Y$-f?pg~WYaFt6or`)oJ20(uL?$BlY@3(__$1r
zy?;=u4XnBY!zU588lyQLv;*CV`sAhMe??V9e)1^cqV5L?KdBZsMSpOKOFZbo;1C!<
zw8jU)ttdlbJqQ6oFe^f`gM(8j0l8RoC0dh)71>bLJILvoE&jCo(L<>6!j76*7vfVn
z>;bJx6fKT&h*SoG)`Q5Yndk%DilVY}ghP}v5VRiFVJGeaOGyY0A{X!LBTQ)=;^MF(
zn{s)lTiGMJAOyR}RS0P25j*g~Vnpx;y{8WF`@!#5rN$e_4xasu0WZf8ypMRQvdh{W
zuFG}e;1-6Ju-D`yJAj*QlcVc^H5RkUvc$Z2;ug-`a)#z{unt_BckjjqEKb0#sh5{;
zHMw5%itnnqJlrZ)X<|uZSA+1nC_`b>%!-ig;NT?s#QVAutx3a*Y^zndTb$eR{~cKM
z1vLj^A{Q$<5sMypREbChS}YD5Wguuhh+gbDnD-4EKrGNiv!N&n!NHf{u*0%C7Tp+Y
zje}plAqkg9mD4W*0y8`Jhg5YZ5!mFw9avQ2-CXzU&#-lM+dqO1@ORUG^Wq42Gzuej
z0QVFrxL-6m$_`X~lPSqt4|LLXCx*pNvK(iUW2p_3rzS_)fwLdw?^tdnYW`i!M(m+y
z_pB5P2eBRqAbuXMr~P|{O*1RPGIa;1P(pu&)0JpV8dhXe&2-)OP)pQO%(^(${!%vn
zk44vt>?hR@k$JxQa0o#N&dL_B4vFK;vXE?a+#iCI=o9a&vCtZaxHzoHw(erd7~3B`
zND-GLv$%WHj@^MXwHh6pQNzEs9l$kX1Q`dGMyRw7@_3om@qg;PFkra(7G>M%vH&RF
z%!T*PcE*7nXBBAY{WLVwy)?5yow6CIJ(@;>tvYLVQ?}zY7|ppk`-O^(E6i4p0sc>Y
zIe2|?U6GGn^z5FMI7pPivGNKey|jZ{QB-zBRKTWPijeH!;3WFQ`??aXNyCb4zN$F}
zinEY&l~ZBI0k=gizIu26316S;iaUFjMWg~P7Ke>85VRiTj;|nS9Lxx+5|y2!93qv0
zp!Kj0J8>6SN<wfDxp-eylBvxiLERX47vK9Y@!zc0$UATn%&;>|@F%h($T+YIjK%>4
z2cMaIIDJ&a1hdY&=vn75{D7#-pYR$7)+X5OQ_YoD6gvj9eOCQ6<fi%}4}3YPC)PZD
z2R_9w?!1P%?BDXL(zE4D@h-2$CA?<etOJe*XWIR055MSVp%od(n6)1na1~M7#cI_d
zG$X-Q+~jsty)zHKkM7*~1INFg^CK0*>Y0(5tzL(_|6Wc{`>RN***&6=Tp1iJxJX#M
zNH6VREsDyHhzi)WOA(SC9GpT4$i<>7(V8@@$mXk>yz^)L#n8Y1$b9riKe+@cZ5<qL
zKk1vhWQJ^OiyojA#j=N@#X83iZ6IiIV4>>FsKc5S%hrLg4vAGPL0c52PH^%iIP9?a
zu?PmOaqx@7ifqB<@4jKptN+_y;I|`cz9h^!7C?Xg;rmwy86byA)tAkOrOri-155qM
znPavy+yBa$7C&N~TU4Y3Gk1C4{Lu3BtcYkXBX!{H(S^CdX@B#*4H(Sq2F}fOgbqA%
z{1X!I8{XE5oAVX?ew}Z@3-^T)WE@y~xJqaI#o#j@B0gE&2bV?Mo*6&=q<J(kR19bi
zqjccW#Jvq*_nfiyza&hUmF?h=cYr>;xWhvNkx!k2iMz*dFJ1Egee&StZrP9rW@Z*1
zgcJ3*ehn|LBuuU+tgEU4h;Sr+bcczj;4=t=gI557tJL@)xMgJ<SPw!#z>ytzK#>&=
zb#MqJAQwx>5DZ$Ah7Cc|<-7Tv!*Aa(?v-bIlqFVt%Pt?la{CGY7~X%$D<U65tQ188
ztx6Ovj&g`p27=auWImCETTxVYj&O)l27=bZI_$(<U?~Z~LFD3nbzo;|vq&HZkQL%E
zcpWak&cE6+`z3RC@z$>`|Epanb3$yKPXCIfkPA3A7t(Bp>;R6MJMQPq;=zB*WBYf`
z?pA}JJ$St8>sEK#>+w6l=f9&1zO1;ZnfME8mKKhMPO5I6-nl&=v;+P^iZNRING8GK
z1L%n#VSJ%za$Fslo7bJ=VZtonvWnUnP5Dkbtva=<5;mv3bl^???@Fc^)>>(o-`Y-%
z<VRn%7xV8n|Kr)>-r3)tSACz<@@#stcx8<+@ji|W%a1Vs#_OWs7$JD!qK<n41eXG3
zaIgdrfBU%7_#n6yMP)~X&p_Dmd>nQHY}y5GC2?>Nxp-e!qBUt)k<C~2`gc4q=JD6@
zpVxmEAj|UMy?2fIpZV`KEPMfnt>vxi158Cxv^c^cN*M@R50V*mxD`cZ=Lm-=Wguuh
ztiw*+1(uQ!97HbO_hS(ZTH_EGhZWg^%X{B9H+TNe=iXU-^)C{?yHFN_%dP)n<se%E
zmLr?T!8&l~lbd{Oe2;PFA5Lc&>pFQ{?^>6zdF`|VxB&E5pUK<HE9y@3w`8Mq;D^oZ
z@jWyDkijedTFz4>|6;UfcfyC@#<ksBABNfYb~obXIlFF5?pxbMCGE{Hat9t6L+8fa
zdzU{EzhBA4T56M|%3dAL4HM!O`4`?bH-3-!OKLw*cgmhGeubUam#s(`CfB$=)+Os5
ziJz}#_x##t5C+GFE0FZk4sJyOKZ2KEAK-NbY}y40O5)%k`o#OX60J$Y`fT01e!i-U
zcm5oIN%%i?#{J0;0kSOaPhPa<ukxRFSoi|Yi*JyFqI#z6X@#D0aL8bJCm0Aj9wf80
zgIiGs!a5{Yu>@_65S)Ao4m&J<EP_F69Q@+2B3ti5<~R5YgtLdn(nh}|{Q4U!2N@tO
zHcgJE10SB57v^`&7x_Eg8^~k+j?9&~<rrTn+N+T}fK#}CCwTZrGBk1#4Su}?JPYPq
z_WZWvpXpz>rS~ana?pw!K-6tTN%&uqaC;WF7v8u0(1w+ngqwsrk%RAnU~|ksBP$=X
zb)|$p7c19pkJ;Kpr*yW^OvicA6u1-x%+PN~{1jRVU4rq_l-hoBBQk*O95M%%$RMgG
zr3pc>WMvE30HT;>5j*1-)=EGw7Q&{sHU%3W*?Y(f->F@_TLLL2U`7~09$7Hynei)Q
z9`d96<1GBz#uI*&<-B)%mR;ZC#{x`PLIz=Yku3qFa}}Bp)TPL6wtx*FidhbDY2y!4
z6k)dLO0*^o8yX^9!Z{7VvM{snXRkRw9K4Zh3!yDyw+I~xcJ&<Cf_-HuAG^l+le-YJ
zWQO0yBY5^F7hdj8a1|Iq#(}l_taP*Ci5zt}eY-1iN3-%6;p-1ah3f_S+U4PApMm(b
zyzc<qLL06aLF0p9&B}tULt#A#0l`yt*eMF14GvC%Fz>HdGE<tWh6rY7oMUbo4%(u0
z%m_`f{EuT0)$Q|hlVj?D<u9o5vFoZi@%LlI&qj1(TOHjTOC8w$cEI03T39|?d16~T
zIIg?&l&CfPs2%w0bDI7*UsV4TSJNt)Pp$b^BcAJbh=@x>WuXIhxYzM(aq|fVaU&yk
zlee}I1WQRQ90tG!5D{B_dWjN{i-oWe2CYfM>aK&?@BM$~^Yo9OF}Hq~Kgg+)oAddf
zfBe~%o4=1z?e~W4v!=!FqR4nj7Fktqk*!LG!ls#3!79QWWf3V1T9bxVU3W<L(|0-V
zH>O`TKXkK823=l$hCjdi@MB{xUZ2jp{^#ABb&L+!>1^U&nNH2O@M{n?^2Il2hHlM_
zdmTqulOyeb3&V*sy+Ww-c~IfGM;E*ya;g#rWWxf<`}5e$yDRA>G?nT2k9BaKa$_rx
z1LSUU$PQeX`Gh9s9mYIcR0BUYA9nA9Tm|69-Q;LGFy)WX=f=8sCvN_@niWp#l{3{=
zpXk*H&2c~nR?e;ehd+&e;Td!L;*O!(OmFeB^>W1-iv|70=88k+rG-t*?s*@Fjpc_l
z;6MVD<HwS$(1akEOJd<L05*V#Sn#M4MVO-qk;0%gY1q&Z>GIcSbNW@z`*Y8%T~+}W
z6DDBWveltAqLZ;+DP8Pfu<#NFtr4RxV57@cclM@v&Hh6s_(uPICSc^G`@YltJN#X7
zcmb}-(RE->|0aKU^UB-i_O~9}dUkZHJG|-xn&&|~VEqY)i$If8>A*Mf20QMSD5(C5
zst$scIoPSR<~r9w7)<{36jDDl&N#do;l+-yzNz}Fc~9_~J@2NrXZXL(zG2LF^XQbN
zbDDH>z~Jn{tM=kZI`9vsug`edI^$*Q2C}11TlrdUfr@K-n5gsX@(liJ9<JAI$e5Ka
zVAIU9h%kaEZgYY#?-M_S!6{8mLj<!|f7#gke~r`fvb8Lp*^ZX2my9Tiv^@n?eP<AZ
zuQfiX&yjw*WYbVs58{wsbP|fJ)c^T{MIKRY8aA8_t1kBAH_gO;gR{Kxw^3<9nAr`$
z@v?P7@I|gBN7n(OU!6a2uRQwc+uy36F!6Qc*3ngRLWC;LuZn7al6`PFIlSzK|HiyW
zg2iR-K(b&Q$5+xz;PGs@AfB0jF1R=INFA7&*>8So;>`0rP=BF{!yUe#x($}NxuoM<
zBSyM3QLYm^w&ApUoj*uN+VZuD;MPr(man?qZZl|r+*SM`UyTI2$=qe@cKp~oZ<`mM
zaW|_zZ3VN%Z;@I1k}w|+d>zM8;rP*=3>GhH#KH+jRhX#rYaAq&AJVWogEs`T(1ajZ
zN@C$K05*V#Sn#M4MVO-qk;0%gX;|HLF#G6>=9|RJ*4gjYe%ks~{@tFnW$W@d4CCS{
zf^JbXEe`P+9Kxd|U09e@Z;`D^2Et~TRlzF49Ay!?YOqR^fmL01h7XjRm-9zhw%)7#
zwAD=heSZIfKW)7aHt7Fwc{n_Do5+!1@kh>wlG&SP?p}HB(ezs%+A`*|d}!S>(`V_H
z+j2xZtmRo=hTXBpIIwQVRpip~A3%2h`Pj#BDxP|-ONEPK&HSo!Ynw4T@YtN6J&)nU
zV>w<08WvL{z7yc))Z{oj;Fwl-Ng`u@vznrNpZ~XpYVYQFunzdUi{;al&%E>3w?!T_
z%5GcKVeuou`koIXy;&4}njT=;I<5M&wPzOj+t&W7+;uE0NNT89IB|4awqC9K2|dAy
zf*YOVM|_Q!ak>9TkIcKgY&E=Wt&$6dqqSx0{4PQ<=7blX5MF1+u~jo?rOyC|L`fDV
zaX9!O7_#EnIuzD}ActfIMOM%sMVNIKQNo}#X;{^D$JwU;;I%VnzcHVhH-7M(_Y2~g
z;cr_BzJMDp4~B<s6FCxW`E!(Qidv1O`4e8@xL5d0{npH_TH>!gGrEPNy~(k5!1AU0
zo+nrNrGD?;o{zQz-Is*HZnGi9onQxoYx)Q>4y-$1rSI`yseT9Jy@mJri#JNo%q`ct
z2jtnHHtB%n`71vR|CdH?^7bZ?XPY>ue2d3XDsVgfIIwm*(wjy9H?P?{{3T&iwQLQ{
zcJn1+VyazAT+?x7Bz{0}%vih-28;$~YK|XESD^_(Fz1BWXyG8T^M1%63~><Uf`nN?
zc9n~DgeYOqnvI$LbNv4<@Ur!y>Py0&+1j#|X>pZdTs%e4ElL=tz??&T28ZxqSncG6
zg=tk2f?z1hK-d7{fFPI^A>p71v(By?F3$f0UU4W_O*!Loc{#V=n34I}A0)6W3v#Xf
zZR?qF<+$ci-+>?6c2YOHXU^O!7R%NN2CPo#7S5+2Vkc<Zi!D0fhQ^*P2V;Kr>pYzI
zhGuDTd*}dPHtpcF7}f><F6n>-_2>0~<Sk@sH~4Qk*W2}i3m4B1*%o%z{q#OBTkGz_
zI<#r(I<UcL$b^gK|9NvZJLfZ=XIb>Vw70#{I`B8QxEfA)ET88Q#iy+XpSFIvwhUVP
zk}$_H4?X{`$!Fn&D#G%JU*l3>`5_HBfCC7@EHohqmXcUF41f(FBDVU}QiPcWfr>C(
z{8#ImG;C-{?_&AC3*@QN#cvq?NhVwUX)6fK)w0zwk1#HtBJ0YsPOFRX865WFC0UqM
zZ;`D^hQg+qRlzF49AyzH4Cn9huQv!y8di1v@;|&iHD~uY?>EeJ`m--j_+^DmUNraa
z-+9Imd;zx{(C$Us4DW#Rp_j&d-oGC3{KD7y|8xBCi|;(gza)Idza(tya!mP+#`d?Z
zb-fzL>vdc>9k2<fe5K5)uXL3Oo7-9kaN8LyJWt}m{6+q{%Vsj`;zl0Z%|0F8tiZ9o
zZ%%1Ag|ioyCn^q&clq&7eJa;YNbCKZ=Y}1i4gIg&9bb7d+nQRe8u&lM?xtQ>_WY}n
z&(%D+Yj6FV6Wa6=dR6m${s9l|GgB;Ezg_idYlvO_v=uXKNOZ}tG-b9HHZhmyeOy2+
zKcoSb1`vW-XhIMyC9!ZA02@F=Z1or@!pwp|MHnuAl(P#>8a6b<ySN*7%-eS^tih+P
z)7mcycW{q?rk`mc7Yc-6cnL2&A-pb%qJ;>b!C}Yqm7`!`QoTjCDj5o!W>y8O2y>K0
zq%fR+m0^S?4Xe8D&Yv}O`+~2+-{8z|d}a3Mk-sPm=YHekl@UaQD~2_P4Lb1o;r*PM
zk0$1)%>9d*dxfW!{F6*LKI(*S*;U7>q1D~?dixG6woHM)LEhkPA{T>uglj~Topk`W
zoxyU)yw9;8&MuK*vw?}9*T^C6SxB4}%)e2Cg%^_c(=Ug8WguvKkem8e?qII!$Z%K_
zKrGNaWx`HL9y4`<ljsxguiqYXwOJ$(up%42e573vlanMf4k82!3@Ea)csbH0ju6L&
zMG94j)`TGVXJrf60D{BE0>v}K>%4r4|9@QeAb9yc;kC~|*nz=J_#GnU>R?f@1g+2J
zuydOq7B423IAZ)C*Fck!z>KbPdEW)-y~vM;{BZofaak6<<E!lY1n&JWW`qpF@D@7+
zkj_<TLJ$&VWicE!fGB2J#Lmbc$|%AxplD&}hDB)7u%RKrC5-&DX2N;<>tDwpwdt7=
z?0y7OzBPIr2_wiju=7nStr?AEJ`2kRMXoUGt`^C}TNt(~XgKaTur5NF_*y#-n{_hG
zBz8w!cT@X(skTt!$U-H=4@kI>2!ptV5d4HD1i_M(EnowPVwOdO@thxuFzbjP(%{e$
z<!a%lU~#57SXP+f&OC<}zq?;?gm`9_xrAJt((<Fpt~xMtD_6x$lb)NK7~pO&F<e#R
zI<KikWRv}LpyKq(0OJd4xAFhBvRv}xF<w-NtMF+q+jQXJR-YyRAN&pD$>h<^#S459
z{Z}e^&_ljl$G+}JNFeS9H5nb8aOzvUm|zpTNy8BCy#VQ4g$9SGgQZ3soCd%K5D{B_
zdMU!7p=xtK#`k{Z>fozj3EI`J+Yeqd^GkE%1M?ogt1<g5>=iQm^4!qs*ByO~#S1~v
zTXN3?<0>ueSCr)77cUZ)k`NpQz^0j%5Iegf%vuM_s$sUc|Gd=HG$b(lEFXIF|9U$8
z+PBVLGiRSe<_hTu@aIO|e+h|PO?KRYxw-pji<Ga<oVolxd(Zq^6Juw5fYi(9ZScig
zRZVu(fpBUqwn%u+v961EH_SYw%w@dH84qX!^;4DQBz9<Z7v_vd(!S2|Q+`iy6RA1^
zHc8lgS359skw06jz2AM#e9*ZPGV-`OJl6>E*C{aDSP{GOy1m>%2QcH7vet2FT-lrO
zv=yh_cNz0iZ4AQCK3qwHmu|TtS<|-N!5!FQ*~(+_zt8T?+~l?Q++Ul1&Rp>S-&(_i
z-es?qW$PvXibNMj*y8ZOf#&#8B@SLVxGY}u3_=EBz@>%Y)g6Oy6`BwPmy$R*i0r%{
zG6+K)M7bbgQB*EOs7kh4woX5|XUzY!n9R(-_MNk{I}a;=^Lh5OZhhIh91N={LQxWe
z!}`IXs(0`boz$8T1mBVn90tG!5D^PzRU%42E*8g+i7+fadTFiNG_2)ld0_n8|Cx2S
z+)L(bQ~ntDh0oP}6ogrpvG4I#9Arq|WN-(TC&n_IUN%2G!G&X>{C7XV1N0^jkekp2
z|MhZ}e6jQTe0S<p1vIBY9l+T$MDE`)Gxv2vWch0J0Us_y6Ab}xF}V(GajGKieZHO2
zY%%2zad4~Xuk|^=-lmQKTM^V;4$=WWLGRu(=R_03pBEU~02Bv-kS&idk*jKF!?#bW
zavqCQWo?&nzEkrlVhf+6q|Uy0#Hx1n1Hre|Ft2*H*YzFPK_lId^St_{@0^*7-{$-4
zgL-UZ{xovECL{nYoVku4W#OaA!3#%~#S6ZGKtcv#04BlQ)ecvo2|;kl$`-HzL@~=E
z!btp3gke~z#Fc7Ou*lj41!gb&+01-QkIb!4|Ad*{`Qmf|kE{?|J7!<zSAGPcgjj4=
zC}KA+j#Cg^d@6?>7FE52R+OYQAqc)X*#<U%2+CkqlzZ$UN<c0ahm9~iTGfP)KM7g|
zYoYDC?g%^I{~7)&+@JARUEcnlZrKW5UapvZ`poCbM>Ok}9dH}Re`sd!O#WFu0)GD&
zIJR=xigVp8x}#=ez!p%|0jl!KJ5iTp!hfcL^Se&?obMJyb>3+&N}Kj+840%PO1+D^
z@g^|g3je9fY-h`f)s#=yCP&+WnfU=@E$+7v*KG?MT6$mX<k0Ib=mo$%m`8&3ecnSw
zG9~{k9{*RJ`1`2ajOnB?wilSunsr#G>M#3iaNF&U18cV<T^&vMv&YNl4DlBueu>}e
zFN^gqH~DzD66#hYyj`1rLs1e32PCt2(H}NANF4Ts0e1_6wi_0>3QY)tOGz9YM0VZ}
z8H6DYqFj)$C@L2sR3%zd$?R)L_tXFAzWH01Z%=18{+>0n>Q7ralFaun|3hBD^&@gM
zE`fVzENlpNj8kCFuR{i5SnZ^Hgt%4BRS+yCAvlQaykCaRxFBIs6k(2Vh*~u`rOCir
zM2iFC=YC}3=6`G^zxg{ijpI*S;ZPL*y-SSav%eE^6+@B^3(z^dj0B56az2FIdvo^Y
zYhUMs^e?}}AKKO|TVFK}#C~bf9X?xgv|DEwlwc%STpJD}j<2Ug#=Jh^kLD^Mub5p{
zcsG|ZI&i^%EB7nQWh>zACL9)<I5*#sI#6?_jzq1&4(`Bm>NPlgaNyN7eQ=5)f#bm1
zAyl`BvF^Jn&(<t60tIwzb)^DbRvfI$$u+;|XT~9eFo@+x=PEQI2pLP_;2^T|e#jsU
zaS-K#ghf%g5P_nFL2Cvv`_KQ<GH;O;90UQtd9ipQD0)lsnGXVjas6OW7!F>dlUfsk
z;G2~#U;~Jt3}!{K>>)}(E*6K4FlbF0)*@PTJurLwUt0dj20XH24M_q$vuse>Nd3u~
z_SlPMB-n%hwdn8Hw)f!7_A;zbO;U>!x5-I$z=fI0q06#|23+Ee1be)v&hauE=Kwiw
zR5!1^x$d@(?Iv7<xr_tr2J;;lc==CMP0;(PcnXAI!08;;SWskz4<-i(F}vsekU<#4
zBtJ2yN4BDD0h?x4L`A450SX9CDPho>G%O*5=z8ecr@v#~<%LI9lFSfgu@MxZC<(zq
z(BgejWVED{{<QTGdJ;xQv{ZDe;PTRq%4KU54$3A+*nxlioWC9%A-P6rcn5GgH#xNq
zw3GGJMzpKPo@7-|dr|bXH{cZOr`hwf%0GV2mERp3V*Z`;_BMwXVxrFb(It&s^~jaf
z!C=$OP)AYJ!VM8>0i!i(SV9I-zHjDy@_oydB0P!`Wriq=ji3lcNeB*t7Vj$z2QSaJ
z1JRlg1mBVn90tG!5D{BF;S?nx7mLG27_=r0YY{EF9+<UdD|&Ns(w40!H>6!bHy@v7
zT~B#cXSg0;E4g#6*ltF4C$%}o#6+vfX?0-Ab1_V%nw(Y#p8S)vgMzvoVRBuY(7{p6
z?s>mrm6n*(BU_C)I1PYJGpj+>3pYfm)rr=mVF?*T*F#mm_ET-yitY?r93l{%tdh`j
zKa?Eh5Gf2=vjMa2cUro`;NQ5}K5a#BPeN>{;upVj*1zEqRPDtnbl}>pZ%(1<`>nz8
zpDgbLLEQj~SwChEJsV(Ud=B7mNMy_%W7#b}w}2rl!(nsGvXE>f{H^~=3Cmopv;0^!
z<Z5&96*pqlb?t(foFthcD8@LKjBQ_tw29S(u>8noN<(m7hQksP$C>3J+4{*1HGo}=
z8l+5Z`W#SQ*DiyZb%FdpIGDHiu>cZ&=cz3G!_;tm$Pb4fsqTL<BV-VUC+uK6Nardv
zAqZ}H84epjG_yP;ThEPo0w-TWmy7pN^b>vrgVtnVMK;yUE-!LtCB-ZolriE!9YMx{
zr4cHvgFFN?TSsNrUL(Qcf_~gWpeOD-MZWx%3<oE1d*S^#KO8@#K}-%z`lf=wtZV_B
zW|l>SalsE!0&+oAC0dh)C1em?7tI7<Q5NhGWmb%A4hQT&cf9aWSB>cbc{Ql5I?!F&
zr{?YMtluhA3qGC>I8Zq=Kk>mXDCs*yO;&YR;2=VvGFWImNbaT!zmllz96$(C1`Dl+
zCG5mqU@3`(gUH4E`c|kkgt$1Y$kw}9hhl!~SB<d<tPzV_zsS``IXnwOy&?Z3Qh^qW
z#YP##tRYh*f{UWEbA&~dG6>kT3u23+b8(0oF0HZ1yeYGr-|y<b9T8;))FwyMf#po;
z+b`oJYjSEGuxB_2uahjU6WI;9?yR=6?rOdvdUJ0bXdM`%0}sXkZJ7J*z$bKf2LNjR
zU6oVM?hP-wSd_s+>p|p7O1zy3x1y-*96^Xu1`Dl+CG5mqU@3`(gUH4EVoli1VU>mu
z7l#$uR$R#3{)4%B4S_Xc;UsePQ4Y_7P;baTiBzD)VzE&Mv9ih(iQuBB>>Obcr3?Z#
z?Sj~%=v*AKG8W4QYK=wa4VhWaTmO3?QD#7Ga$Fs-$3>^H*}en)RnI)PeX5q>Xgc6L
z6I{2OoLC23SI<uV`0hZRIX@827%<z{)_-`;|65g)6Y9WnSnus*RMq^u*eAg1*}XA@
zNM*3ldJwsi+HBdn1uTI>oEa=xVd@qRz68P!i&zuxY}slqZ~v-swnHdwQp^zNun`oY
z$V%;Z+#{V#^cF2E$`-H|$;G(%F)pHBvIh<*$B(N%@oS$U7_`Q+TO2k7DVGP&fA0){
z4*9ck$<`>dY*aIj)Pe6F3Ae%SrvtcVjwn@^%-!=F2NsvP!^+v)b?-(Tp4nmha8hVf
zL*vx*bip3*%Gg6q@79g$j+ym~<~r=%d5r_>c2_`6CTH9~{q}i{r^z!@)BdWQdUkJ?
z7Y}8y$mc<>RtR20Fe9i+RCbOcL@I-YR)Gv#59nN+8|R8JXbrK;#>`%L^K6+H!6mV9
z5LNaO4$p#OZ^%E1RQ;$}geZgP<jr*Z^LV{gWoNyGO&J7i+6A#i(YZK8Rg$SqyzQd1
zP58{~U1-uTTZ^PR2c4@fF6M<lw;e&ofqi)3O6R6_*}7w9?!blia3jHvaYx5r_m^c1
zW@T2*W4!}kSt>qQ*SG!Ff!2Xj?SLIr*hts(abVq`79Aoe!Hm_I9;=l>6(u#h=O{v?
zGFWImh+Iiwpa^CJRf)>ZQG`fku+Vx~!cN=;mXcUFh+Moc)`Z<5r!<7PIIPIF>T(&f
zAh;wJ4kB0IOb0_q1&^Yj29XN1SS&WmAXZkHA`zUGEnqDYN10_2VRZZuC0JHKR>z`i
zpw?LUMPVH*qU&7UjG(>w&)5zSue0LV8fBJ^N*iyaP5ZQr1N&f~CB<@o`=*VlweH}|
zG=-+A@4z`u!6v8H0bH9$5H}oii_q>SHyn9zWH%YAiQcBRn*7SAnwg4hiZMEHF$U;z
z!h3jRdw577_Otwhf!pd^YnGXse-{hDwO`NfjUhxTgN4?Es5$*r5Ztn|1uP+PoLLr<
zjl>Vjk5B?(hXr&jUR2bkmmxlgkU=v0GA;AMk`rR1g@eci1;aT!3yM$_MWg~P7K@EC
zh>|j&NFul>DmzD5L@9%SO}ikrC^{F1$gyBWrZ(IKi61)1LMzCB<(1`X6o#Tin9&G7
zmx$x%RAooCeftL<bREK24-q>gsKxBL19LO$FMfLlYUvNzfvK78=(Im1>xR`j&^pjM
za3USB=k|QdQZPLhlk4i6wVK^?CITB}u+VytxmZbwX+PYGqOx-YAxar6v>ukQ6L*27
zBo+=L7w@Y|GPUVth{(3ejLvG8tsrHw5xLL~?yG}AP=ul=A{A({SZtI*l$7W#f~rJi
z=O~LvWe~7w7sM7t=i-pnvFIA8H5QpSV`e8m`SPUh(^e#pF#}+eW9z`Te`Io<ehK8*
z+IO^k+|e>?#0GcZ>>4gxF9uh8{DC{G4fo6IC3L;$j>Gm-<G?o5y>{U1b{FZ@{JSct
zp4}TPm?G1D3#|u{E2-03wq|P6%MjlXLU%+nzxDUXSZHg+!b#-nqa2>wvbFC<{7H`r
z`-!nY1GUCNE1Ir?(k_TCN|agq&*_SNyM7LKd6r&3;*D{x17pmiaYbr!hz?kQh#No&
z^)cTe2u|Wo!TVwgq%Zpua}jw5Is_qOPKLwgnB@>V+Z((Ua}N+^aoDUFvbBj$tpx3b
z*&4AW29$aE(nJp+BE+!~FC;eB2Y^j8%U8<Q#mi~{yBJ-G)}&!8Ms_f>F7Q>}KEW&e
z+QwUWQ5619tl_u->lgX)u#fN=gu&rQ5CRBXrN#&KIWkXMz<LnPEQ7Z+En<Y(q$|;y
zG;C-{+GQ}aVqn5yp3v`EJrXPq-s6-5FmvNnJ`!wydmX3dA}X%%`i@u(J7*7d>tr1v
zQW-3?{axm4b&jz%U4UCwhQsEVWg%hYn~248U&1mM@2}q;bG6|@<M^S1cF&BVFa%AG
ztOK*{E(LUC<up2d2eup5*2bgk!2i7yR_k|&x}-Ru2(Gw{<Hi9IHy>|sumq6wJqB(?
z848<bR)k~+2d7X1a<S-2v?dKJvh`Kj33_(^cb+|S{9GjtULuzdQ|<SL?6XMKUo;#d
zl!2i2Ao^Vl2Qz}IL}lkFhe%~0Xg#dMPTU2Sk`Nq3F5cHin9?}J#bHG@;quDAZYG4l
z8X-7|Ts2WU_wncT&J!O&!rjzn&A+>wL`Tq(M&WvQ0PiE7s_d$^^OsJwLr-;G^l01i
zakFi5R2|^IZQYI!hxc>!?ec68?KbeeZmzqk?LXPDa7?3DWw|dV*VPA#n#&_`#VRem
zv|DACd_5F4%`6GEVsLmZ`o#OX60J$Yifp2)^Z)qfqyq$KNgO*&L@pm87CrE&5|OGu
z7#t#%fuQvuda>tV-ZyLju|N~ehN2_{2Va824vQFzZb_mv4u1KDC>IJ@5L^<1!#cB4
zP_wrVv<^JI9jLzAUc(k0Pi?p=H#xQrOmXucEPQX?Dt-X)VnEDw3E5d~TYiXcuS>(8
zE}nnT&8oMpS<SzT35h+zEZk475hWH5-r!&fAnBzY+_FM!9SWOfmW70osk{E!SiI=3
zaJmw$NyCPQD3|m9;hD;1Yl<02%0&;*igJ%V6fM>{L@EP8>&IA+i-URJumQvZO>`29
zoH(XVaPTEK?6Bw~Olcha@(ocg^v1&;5WzV~GRp<+$A$y?RApDSwV!x7nIpvcOFLI&
z!&it7TVB;AbN7_Sfu-FS63e&>^HSY;zZw!t*>p$L0o<U+5llHoka1w^&Yaz~gNN1C
zWlJ*~)G1qsx@)hIU@-wcuq^6^CBf{hJ1lU=vfzze)mH#DmtW05*b(ai4?;M?9L!#G
z5ZC}hfELW4D2aoEAk6!!l1y!c1OirMQ_XxI{x#y@ByufrB4{<~WUBsP&=`vE9i<6D
z`-BZ37AXGsCG6A)!AXn?@2g5OwOJ$(up*lnm)S$(2>vxfa1yy{qT)XIbK4PQ9M}a$
z<B&4HV{8@Pu9@NJ7(vE?wIfto2YI~A>i9oZUgu_hD?P=1s#<XZ#nLlwKD%RXVJ3#l
zQvIcgy6XEIx9fJ==2$u~;~Ogf_ha3c2zfF_b63ZVNcdUoIczo-yK%%$0!D(ZKW(<F
z(i$@6&rRp=f4%k+3}%ZT=uyA?;mj`n<#%{*ibT<sO7EI^QnP#b_7{RKZFdz>OFO;T
z3qcvME7MTeG_$MR=~oUWu?XS)O==?~z$oaT!0f?4HJwcV3QceQ@$~GYdqAs@_y6cS
zUtco&asKn4KY0!z=urf%)8;mojiSh9qUE`-41`p^B)!;kFjo~}dq+I49t;lqdDx5#
zg0sTZ2@bvlhaDDugei@KUnR4P|Mwa5+OL1t^z0tlZ_;i1|FidgA(n0To!_py-L2M@
zbSa5Dnrm4JOCH6vGPdd1#&c)zz>=&u@?<b=Ljti3X&leQNkq~EewaXDmJ~D5O#E;$
z4jGIe8jmIsaVAl~4rZPziSrO*hz(&NkcWN==phgDke9rK{671fz3cqyxBk^Wr_S27
zd;O%d>+IjZ@AvoJ=bXJ(Rdrq93U<is`9B?o@Mn)}-{`T<@5h|??`s3=c{`oK{NK5{
zeE0g(uiqd3G{_&8xg1|cSzN`;{k|K9zjY?ASz0})6}aGy%{%_9yun}UVEoMAxUapu
zd4J=Wck4~B{_Io=xMBFF^a^9Yu;g9GZ!2E>@si3Bb9a~7KfUXhiaSQK<uSF%rp16O
zW=si3@$+<%YZCY>=3b6pat9|t-q*7|9mc;WGN1P+%@w#Bo_|3|$dwuXI-jKe?u_J*
zd>&)rnBwKNjbORiox^_m;<x<p?dQYruKfL;s^3wA*_&_r9l8JT={v*ApAEYcIr27k
zobjn#H3Kgu61_ae^%@Rr>fkxyBZ)we#|?<}Ohu$+?HJez#Dk!iWg!VlY2d5UNzUyg
z){}-+-9|D0%})$pej<zg7xI_3!ZQ#{2D5)AZ_%;WPs`c=vVXsNsZ>LfQDugfR0S$c
zz~h}jGCz?dt!SpZR0OI_z~h}@11IqmA|>-As9thzUf7x091Zf<_&b09;+w<&`&WnI
z`#(Gk{@vjb=|#K#zR;5YU%mMKPlxbJpJESqF}Pygi4%B1Z`F>Q?P9omfB5d@Ke&AJ
zNx7i!e73UN9}VLh+l3z<E-rqOZ!(3g>ia<FdVH~D%_DbWF+cu);1$trZ3;XezQ~=T
z{tfqmq<(8Rg?l8QzWu7M?UD|!xmgeY@vyryhB|)ZtAJGbr&w1{LuFN6@1AwM0?(zz
z6>rns8_r$fsIq<Hl`NdPtxkdOUVY_yB=uWztlG9p-lI2PaPnpF7yr>GhNmxomV4~(
zF3a24al*@F{2bt<WM*|w!PLQX!i$I1T#&~wfq3JYi%2WlLf9F^gP@odAtfP@G>tI!
zl5;ajW;Ra)1*^I-)%8z3d3y1C()3T|SDEUztx_f1*2|IEfB)<gmlyxiC!F|p`x}EM
zk+K<DQW7XL0grbAv75a>n4&5(-K8o}X#yVa1RFSsrw}QbCqea+bNdQ2o<Ln3R&^ug
z`9J#9aQP+Kt$hCn{P5-7@|N<veeECr?9)qnjX!PurBCscZrxU*z&k%Wxc5K#!SMbY
zb~*2S=JK5yVwb<O`ww{x?k~Dw_{op+%Ida41-Oy%4JKd7ZF+BBJ9*cBk?L+MQa~=x
z%g4jupv0x()?Hy?;6G`IJ$-sPT(o(&h7G@(j+^b}rI$-H1P)j7Ex_vQGgeI7B3Ujq
zu|}|Gnf1uoJR~1`{wtgB3_fsHVg4{D9G>*&D^TEr-@O?8ONhv}Rera>(ysr;?$i3>
zZ-4Uf5dPPjDn7>@r@Yvz-})qadCbdxo=+V-CoHwi)-K|iil`~tQrHQ^gP@odAtfP@
zq;!(=yUgZkpkP%urh55P!tod7$)7zRhL4_6P+{TEKII-sFX#Aa>wo!!ey%ZSb0qh~
z(30dpfeCoL6NugH1;P|nndvT7fl3qbcqiDvNj!x}$vg?Fmz>*InDGSa;;^b4DL?sJ
z;`)UbS08-;2ZrbV{YURVp}1uJzy8XO*^A%5804p|yL?wF>+y3baPf0txMaur=C8}k
zqiWA8$>DdN@M4lDKm74a*|y3L(L?njdMxaRdsTqjguGupAVD54cv4}%x6kqZwfuUq
zbnz8Mr%vJHW~+A8Y<^!I?x@a9zPu*J#m&CK7@(=c!HcG3@_ROs<&pRtm2^nmWrF--
zhlK5F<9=at%%GgL??}`V7U!)=va_WGIi8s)7vRq~rrhoWnbRm^0%`l+<G~T-TFiXq
zxq5BP0X4mswA*^@M<bH8BVg0avWR2w>k+~d@C0jTQ%b3#8)mN$#3ZF`!i+cAcm=88
zx6>wjB~Jo(X#U#98+nxN`9ASulKP=Mu3;@UcTj=%Br=1Hsme1KjV*GABVcC`!z>55
zi-|Udute-6){};v1({O@$M+%jFBbsICd~NfS7R@-d5Iih{)pNmN*lo*Db^hZW=nG=
zk5E~&V>W;APM-pm)pcogpBr_(?vT|6*4=?&ZR+V>KD;#S9kIycS~BL(i^JDQ@fLD*
z^J-)YCy!w&;(6AtCAtju2E>CfQ4X9GP4<$3Bt=-x=l9h<@PYB<U{yD!3Ss<2MWG=7
ztFiI7PyP7wR@#Y>;pyOaBGuIQoO@T`X&B#Q!}MSGyz8fs=kJM(#@nRZ$rQNjg@^(F
zi%vcT9))4}0&l+>dwjjm^1m$qJhrx~rgP6Zfda3d$j7k!4Cmsn$;;zqb;JLBcs}O7
z_;bVX`ajrx>f^Y5hp21lNSkhoo)a-%Dvl>Az>9bW@r0FUE+SGgM}q1u=W_=Yh=Z6E
z8Wzp;k_u0i3Ruq_n1#PAyOpoW7RU2zE5BF!y~CgXOTY0$qqzUx<ICai{>oP!tgz@B
zWEaXD=j${xmt-~M98gL+dMeLUM4)I(VJDCPf?`&LB*73CpECjLNy8e|ufO*0;Q5a3
z7yoVP^QGadv@hE~{KW1%OV@uOo1>ro^W}nj$?*5mbsbHQob8L>l-~(`^E6!lg#7Ba
z{QhB;J$myQw@du5zWQkR<A33rmu$E7D8P3jp6wqaE8fo)_U$Q$Pn0VT4Q$+KHNZUw
z<Z*8lZZEUR?;qCM<#hR-R6J5$YFqTY`%~bld?P_@ye{&r@^|_r{q^_`mDkie^XqE5
z()Y)<cdl39k^Ea4S=L@X{jz+sXud|JdbdmP<HAmUgd^wGwY$>ek1P$hYRAmxylh*C
zAis_D8QHd8y_DxwGKK$Se>Z*pjvIy_<7D?a%rVGgyu^+tHRed73Ga6=4~!Ry<B19|
z?F`}xE6-d+q-2f+)m_f#4k{1_F)1`Gn&~AKo+=fvo_c2Cqy4sZ_^NDMFXi_ScUK3H
zoc)hK;dkQxs=O+G_uuCy={uXR%S3SsWWUbWX=X0zQ-?t598gL+Ldr805h&VH*a;+n
zpqLdQNic-P=S;wQ(y&JLKm85)UhsE@cVD_ckrnZmJR~dZ4?nkiXMOD#KQRn{?ayDl
zsHo{F=TqSFix*e!`Ahi}_?rUy$-4LIF#Ou(GdRBf*6;lNLAI?t@3tZZ*tTMBJj%gO
zPx4=%@ri(W`BR4<H2QZ{wJ*XQ(}#6DYPNUx)qxM+*9^|bbjc)nx~gIP&6nLDkEkgv
zweIngDDZT6`bD{^`V0AnKYuWb+j-fphKoR!XT{*;$tB0i`?92;$b|D|?a0|Y!f<e3
zknaay{6gJz9j?Aho%|#($T#pV{@yTz@w6XSp}@=iwspAp-oJ8(pSE8A=KgKXPg?{3
zsg=F)nI3q~JJ<1~X!1I8B=LIUW8BLFn>(lgAO16lCr^3iA|hEk0(J&5%(93Cp>7C^
z&&xvvg7MS{GBF!}+WKt)@>lN+@BSXmO9r!F`Rra?`DyDX|M*9C94MTxi?poU0>9oT
z2Kjo!T%J!IbU-QTBu&2@rXm7ado9uV<uR#2#nd5iG6xiFI)$37)&KJaN1sYqqx$tf
z`1Doy&Cd;w+`o45^b5b>Jk9b3vp@Wt+>_<2|Hn@*hM)N~=nc#_z&sb^k+c2yMfigM
z)YafWeR1*ePmV8-3g*A|nXBE;#D3?|qsRZxU*!sSJE;PEk}Nm2trx@9_{{}R8$Na_
z>?t2an3HYm(_`MP$MN5hSa56vdyG<dn3C!CP(IYvjp^Uo=Sq#QyouIz?^&l&;9`1z
za-|-PD~4iY`91ORbNBku5PnFqU9lpaFu|uY?j_O&*5Au4v8J!Do(%4h{ISE~Umk+{
zYAi+hJij9oreCA*T+++0j2VlR3S;Tn4~<~YwFr6r^Iv}9<v*(Nxy#Rd`svFWbz%0W
ze`znv^S|Kbr>%T<N<Pgm6I%v}=FJi2vz^{v9vCkY#}gG0jGKMQmkBG+TtuW~js(?R
z&gTv)5C<_SG%T9wB^91370AqHV7Ze9I?UwX5hb7g`WJpkwyoiv-y>9GKl8U9?Zn;v
zv=wc3ufzGeOcZOn-CU=cmXu8$0xjmi;YcqXp+nDHM4)I^4Jj$ZW>SifBpAZtbGHM|
zcrvg?_3&L0?2}IZUhMz(g~9zh%v584QU0#W*y|6a;#dCMS88e!Ij<7_dv-U1<sUhp
z!@QT*?AI>e{h7Zbzt{g)e!Kz_X213e`@~=R%J8HA`{6%DuV|oCcJFfSJHuHU*l>o)
zfRH!ag}hat%C&uT@mN0ViobYxi`jTveX`|W*FDpfI4R8M<cD#e8~pCx^+=vnS~$$(
z#@B5n3d|ovUjEsQ{LpkhUkSfXW03;#xvQ=6U*G7WW6#2|4VKk6f<5b7=SM}FXYvb#
zRhD43bMsOOw3#;~oRrLwpqBk|K6g+7Sqt23hrFC5mi<IZ=15T8<-7tmokGK+sS)TU
z<~gW<^`v2~>P+?RfBI<nAAb82pC0?tzi5iUj+q;axVWBYQwGno79?tEiF4{eLPBgu
zNL`nyh(OkYM3=%&AoS48aAXaA3}Nv(s#L&w(y&JLK)c`kvEkDF{5ww{)3<0TX2rsI
z!i%{3zP*iLr*FC5?|59IVF;fH-hbn=>Y~cu2)|!Sz59t2kiXNy=jh|<551hIZEw?7
zfve%E<BrI!=KQw%z&JZ@8`yBhIXzgHUJf-DYLa@+S`-Ljzt%o8A=Y;dtPQL?=cNC<
zfAmy-|F8}+%Zwg@KD<O6PfF$`!I8v*jZa1|4{YwB0$hz5#FM8ya}kl8c?miaRChU_
zJE%Y$#H7$LYjiig#OJ9}0qeOlv;R$gg!AL_PXp*%v=p<kaK0`R#bP@W=Ib;w7w6O=
zkTC}im3-+49eU;>0!3R0JA(ue6tf~E35Kxv-0eVSwm`0eHL8DGGG5EJb$IzdKfZbg
zz$%L{1E<?c6yQ3`wpA|E-+1be;#BocKMJ82-%)|rgO@)ZQT<-MWA~okNP(v=>~3)N
z_`W{1XWpLzA>G=`dsQrO=(ZsR#zp6&XB(QRk1`BD`h`=e5Zy8qn>#Yp;#$u0EBHW(
z=P<q`<!j(%F5;wQj)VoUGl;5%N0k}EQst>s0qaS_TGe6p?SEbRzAsJbTV;~?BdXU<
z(1UL$Ocblysa9@ZGIa=?$47F6jJ9;EvZb(TW>v6;uv9rJRls`Eux8sDX!pneuJnCZ
z{xTDNt4t99?yd{2DwLjdlmg%Vxv$Fh<|{|_=*8<(z{_7&k~i%7h;>HCD8R3NPydAG
zm_BE&o&HSNnPJZYcl>OAT#%fFYzH}~0{$aG>-W}kN`3~cpSZkydYXSi6WuZtCvaq_
z#kHKrw=`;z@2OLsxrj)~90?0xXAo5jk18{SrOH#O0@jm;wW`DH+y93Aw3UDIb`&$I
z@7vZ<gu)^AVsO-`fc2=WUU7|O+j`~Ry}TUz(!XemK=q5E*tRE}Qi1P&{GCVP;*uA@
za_bj&xpwzd8OCkv-J0LNjJ$!ntxAF2w)Jk567Owu11NU=l4O`Wh4=!MCgAbzL7v?F
zLfbiEbIf3uvyX(RCqWUG^V{Fm&CTX$VD5wQb<^CJnw%w>Ns*`UHe-BgyZ&rMCP^=_
z1SB(B8gCyt0yfR8h&p^j{)~fUc`_%Rcy2C|^`v1v9j0!9lij<)OW!N`&3-&ZOEIJH
z8hY=^<CQ!@)gL*&-Y0%uD&ELr*#E_hxq}LPC<!yjn5sN;5sk8Ty&QH1G0d`vV^Fq{
zhA;t!Rsrit!_I=J6h~jK2Yt(yVpgt<XMo(m+Q43&b<zMD@7xMI2eZ1*jS8}NOKAfe
z?nbgjHrITlx%+glp&%dCjy&Ez^L<C2&mB}i-9o&i#cnFNOLhconpp{S{Et(s5$Gl6
zIUEF>@l*+-m<_{M(eugJm;PCMF3|%5`*-=pIo`xsUOgC7;QhOO0^QEuzv^P0yYKD_
z+?Mz59ps}=-hAPXg>6<GcO>~1r#~J3kBg6A$|q~_Z>N<-@}#H_=yJ{Nd-4ADVsFys
z7OU^ZXM;^Ms~PrY`7jZt>MpaX`zP;ePlu^n;6zfc-2W~A6-d6-Q~ky_y=a9w4vHd<
zl6evoEjc$Bfh;wW^~^=&mdul|0ComZwJ@tPH3GfF0tXeao;0kZTB#1R=l?|dK9eU$
zF{5?2H7W387Z;D7oZ>ThO+$4qVgFH3sf4S{yYDnv4s6!Ae=j#agXNAG#xMP_Ed^eW
z<G5`N)u&;J?4R82llYcu;nsOSZLYv8`QzQk-lzOH#duW9{+i(eNosX3=jqL%Cw;to
zm^J-eL`um52@7Cn5LH|KrXbM+J?X@AGl})2VLctDZh;e+z5MmR@br;vTitQYXy-U6
zia1K<Nl>)p+)N+HQc7CSTtsfkJP8Y6XAo5jvno>~>?IFWs(|&RVI9><bzv5M@%MjF
zwyplr*q4l=DFS<D#iE{YUIoGr%l8eR+~KO8mtIF(tiT70D|_Jz71-Sn+}GR+xphh>
zQ6L=C<*4F?z^C~)Lkq$0x$G3P@!!++?u$n;WmVX1O$xk{|5V)fF2{}Hk+eMZYS~|G
zD7S$?61M}#6Bg=X6}vREroSoL^~fBLfK4;Y;O#<QzL<Rqq1(HYVf^FzCN+?&luD<(
z{G%^C9ln0?=&EX`;-#_a1sdi!D2h087UV_XNx1!DFc^U>HIntrMdaq}7}yy^QHEL3
zo=JupfnH*Pg9=zr8rD&*REOD%-ySZ5`;A>+GP0IpmM!YR^D7Yk+pFQ-PxD&owiX5a
z35a+;1U@sqjZe_+ZY})X(odD$2==V+9se0w1%&bLR+jCo%*u3nMnZw77jE!RgKKlW
zSXMT$MzE}F&Su`<0qR2D*C#aAYz?dptUKqVf8fH!YyK0<HI`uJ$J+6TV)NE+bQcbR
zIOvWi`xo@wK?T$z->&KBA{vz}kf6HD`P@MT6l^+$hD9^Is4%+|>q*0UIvlG0dL;jk
zr0Ji%d+`XsDvL04W8rvI6l?l<k`8HcZZHDgL$Sj*Z+mWvh?LBeaCg`n5LFAaDmxru
z>?Ku!%ELe~o(!y`TB#1R7r%eu!(aK7tN*V79uk<C(RzVhL+AX~2$p~3d@c(=9NvBR
zdp}nRcVcF)686MtjbM2fozJfB@YB}wGCQ9J+e30*X8M`m=of5zm$pyT6}Y8<8<#!R
z>u6Qo=p&*HtW%?}=_Jiemd75ZC^ql0aFi^NpcdD1K6g+7wd=8K`niaXB?}~|?s7hN
zPyq#-PN8AZOfM?T?!<c1u$~S|bwi$vqD7dEe~fr=lq!nFUP8x{q-e>x!3bn2zSc7r
zk(;$6U}q3T8D>RulA%VRmssGS0@jm;byO?WPsfbb3(Q03{MHDTKkU0sTQ9S9>eX3w
z1vaCAYcokBSnhf2wDmGur(SO-tNl{&+{3ql4d))S8ZXPt(?%_>ab!&v!hr;}x|j2c
zU0P;MPsgks0h?x)MI=b6*{2XNyA$h4!+JU>)s>i4uizvzE{p>}QN&R)PlBQ)=Vtmq
z)*;_b|Frd+x2LTTB$Gn7q8*Am_8MP@{ia(K?!hHgz0)7uRGn~FpexW7Sf>JEqV-~W
z(!Xv%fv|xY`UnLDSQ)eT@O-_!Q^A+DKvXTR<-B5-rgu_jgH1DIj-r{38x?9#IPNHn
zCk^ZApvG5XRxf66GYj;kvE!>Egrj7h1Vu~EZ(|IBEXCJ)<|1-S=1EupJA<fNm{pk?
zfnH*Pg9=zr8rD&*R6iLr_ceNV>k4!Qx&mE+w?%<F{KEQ!lVr=YJ-Ca}33mk^jshO4
zYH?k|J&>eU_i|pbOUtb3=~%Kr!UEVdvl8MMH~SR4W_MyeX;@DOrTXDib$^nH7Exvd
z90x@aN69=1ik6%kj6l{Q-@$t3B63USNmu|ogQ!}VRhb%rUSffR3Rq7X)={lgKOM83
zLI8Bzjso&p;`P#PLkhgueS&OgqCSdJz}x^-G<NbGaoW{@IL-aRQGRd>`Cz#1xhWzw
zYs+D8KmrKrj+lj%py$8Kcre0z=W<jY1ah+lauuvm-KJ2Jvm`T$4v5W+bIm07^@vR3
z_LSwXY-Tiy^R^t;(>Ts74=K^_J&wE-#cwW>^>~`cVU6n1w+Z!WOEDWOJ|@Qx<#7$t
zd!ws#kpGA^iLc}l<oU4wyA*Q=6?h{F!vr#>D$iU*THcn!&LEaq9#W#uhv5xL(+FcP
zIcMlM@|XkGlYv#;jF@9zdS@-gEL)Tb@<MH3ZD4(aN$Vib!OYcBIdxVeSUy?TYkcl{
z=&2h3j;zVwqYosg+l!oE$s@=^2h`$VNZ(W_%-RvKX=YhOg4gm;BhU*olUPq0*3&_$
zuEYeeXxEYvV-|{)J>kJAQ1yy<a8q@{U4iW?VDAt$vzoht6nP3wz~P-hayMP_N@luC
zfv3m>9Nr1ma}rM>QZh$^>Lus)R%kq)x;U)rwokbV<j-9=DVZZd_1aeizRs=4s4~?G
zT4Iia38+;=W=M*QX1Ys-qsjynY&wP7qS;<jVlJ2UI69w~8ED-$r@;Olwz;|9?tz{)
z8UMNo>Ultqo-J@I?A8@XC=e3<?tZ`uTn_#Lv+vXs3hdUxX8oPW)^5AHA9gPi6L1tx
zAbKaIzMZN2C(cZF$@AozfWte%dQRdgL`vpJP`%__?Fq;4*BOteE)J`@#ZxFQnIl2<
z+E)a=Dnk1}{)=h_EiuQz1k|1{GbF`DGu@@aQDp)OHl0Fk(QGd%G1tO+9G%a>EX-FB
zv~CYvf%zg%PrkN)hduDQI{mJ|+oC{tTLyi*=Je+t_xZU2&xm)z*`_<?BKG}TRf}X>
zW6{SADP9?O+ds10x2yYM@boqThj#***Wt6r6Rujm9RWLo&?Cs>h6g8E6Y7qHX#~%S
znA#II*|w&b!7gx66mev&_IKPP*En<4vycRjfOXWX>oUFi2xRTGM58Z;sY9R~0W-6y
zw~g&~6tnQHiGbrtx2`}};0y{>-HPsy2cH=YtPLz5ndi0_Re&v+RT1k+D^kF>;nE0p
zTnx3DxPY2uwoIvUF<*eZhj1I%a1WE5re%uR#oz?MEUv3S?dpCQJe4Nk@J=9lC#9DC
zq!rC{mkLjn2{^nHtmh=2LZoDl1l3E<)t+#C$r+EQE)J`@#ZxFQnIl2<8Un7}Q4t#5
zrGsh(EiuQz1k^6=Nqho|s?2nkDo3RWDA;rgwMDbNq{K{;nN7WZZMOsRVeVUGMS|^B
zRTfR+pW8ODHn6W6Oj-wdVrHQZ_0(C7VB6f$Ys8B&`(jOD&*=(u1)3{xef87LIdlRi
zSAYeSm>Z9GJ;XlK@7iNQejC`Zfa!TkV7A|a>;Zr0T{k}C>K-hvZ>R0EV_(ebUXnbC
zCgAW+Aa=9o32SzE5@xzfo+sA?9Nr1ma}rM>QZh$^>LurDPdL8hjK@<KhgIF;DHNA%
zTp`W9e(?wA{J=9sXbz>GFvHx6Bxs2_4ko}$ClCQ7GbGWh9RcfT9A%b8BpBqOMsVW5
z%(bu{M_v>*5K*c#oyR-%<$2bEM4$hY194yeI#`SC@#4y(3fsWGIEwRq7LUw+?Bd{3
z{_^<FxlhdA`#cH+K1pW#f}5ZACl6Tx7Y^9_;fPPP!$t=^@B3*Z*l{s*-?J_1KQdGA
zR=226FIt}hR|9`WbZ_p<)3XI%-GZ7Elr)0fukueYz^PlvzfC?|FNMoT-@ehvtiOxs
zEVrgrcp!Vf{_;FG0f%=2$*k!~%i0mJp2l%zSx5<bc{q8@BX~~4pyPN_F`L~WO+}s#
z%bC6Yp~p{W0{((VVgeWVswm<pnxQ2Xjw%ySBV~RfNpaCkcd2kxnSg>#r%+oo+e=E!
zwaCn7_M`z!rMgKWqiDkHYk@3!$+q=1&&OZoAD{HY78Lm9%l+GR3&XtSGx&q~kJ#QE
zbm>nUE8qm5JH+1ncrTjH`q%X+aM%By<kjJoe7##|tY@0eWT65tE<bxy>H4kpMvRC2
z?7#ba<F}f|!|*HbT*_a(-+e5bok7)<W_2%Bo=OvNcqfp|nx3?xneI~IsWJhFcY^ht
z#8Zfr%#oma$+_8`SdXVJ4y(GwQz$N(`+4~m)5Q>W|2p}1pX@HL90Qe#VyV>_H?+j-
zh?s!d^JRvlxM-%kR5+?kK*6R{s4bf9B_-xsSdXLgy)t|Le}<O<6t3XQKRW!L6W(qQ
zRDu8IkoPb166&@A1$H05(;ycIo1Mwmzdk?(UWeW7bfoStKHX%5mrYR51A3y_xJh=~
zngZdD13f)_8N5FHj?*0*_4E}f@ahK+$h`USn-jDCz6oWX+133pc=Aoa;hjMAPKvvN
zCrnY5neI~MsWbtHcY^ht#8Zfr%#oma$vN*5CyzN`J)UqJR&|S~P+YQ?fAr4HPg}3Q
z|72b<1u7NAQmZj;Xo=SmF#)yb%M3|z(M)%#a8#Lqf=#DTTQu8CO3bye9!KZ9F$;4S
zYKx|s{mq}*6&x(0iXD2wITQ%Tfc(Vn#Wuc6kLlBESEPWvN58xxI-SaC6i{p8$gQb_
z@{!zDJW1;IBIjxeq(AmazZhN)fhX!#J{J+m*>cz%vmD|W`;r_DVeti`2Z5KylY@0s
z=Wn}YWG%&vq61<(8re=`@EaHQ0usoxbfm<t^%-E(%pjGu>(53mmsHqEtS1d?RQHg$
z{WiguwjHy}!z)PJoqb-uyx}Q-ZR10p6it4lN8&ZC-;>9yeZ|y41p>dDJcE#`JyX%X
zN9M~BuoH-7mciSFu49BHWGAtnH0&%$I;DykNpml*#}RgQMC}o!jbM)y>xh9%r8{Q4
z#b>*DyUwnoo`j>S7Z*2zUH8UtytZ8PdD)^aeM;=-5>U5+{cFTiU;+;B1af#II3uiw
zL!23rtjSHpkuZ(mIT2%M$CG_P-Q;e~#s^Ix_jb|X@h)d3_xOv6fHZP+8r$);TUVef
z5LF;Vy=QfLcUHI#b`}M~zq<QK2h4ofS20lc;%SAdZa(qbMfx6dudr!mHL!ssrIVc7
zNvtOgtGXF6M?gSJ7D$+T{ZIegSLOmE{~XCZnOjZFB{@)F0v_)KqL*e$2hxgWx=Tf%
z$^<;#2{v#NPa#q=PlD<t=jK{iPoORitGdNgC@z`*+tO(6^=qFh<@fl*P~fKzY5u{u
zBtG=?=MPkYukc=-j8Bjj#`h7oYTS;_YvIw;aD(`9?rGgNp+L}6xbgJx4Xoq+>>()N
zhSyimZ-`#+KatP>xpBjxKRbZ}&;K)j)8);7dUIkH*EeaIXLfZj$<tnEY(B5L=`w?;
zEsY~I74f`iOJOGv4}xM=gp`Cp(mcZctzajyo;0lLW~Lee0WDehFXUgg&b|K8!B17y
zkYrTZ+-hPjRe?$q@OUSX%+`*yqM7be5vVc&k9UF%oWxUzl+2T$dda!D7S<D}i^HmJ
z@f3<n_O-)p>qo!(QzOe#QID@(fs4a!>*b#eZta9Szd8l}?qM2l`)&_kfx~U9e3Lrt
zCgKym+k;lX9kSnF&;6qAFmkWYukW>c+vaU%dwF;XuU%USI{Jwe_-BuA*1qohpJ0o%
zGqbp!0?DslB6f8zPF^@B5X5=2$WL$WNXwd+sOe5c1#CKn23Zq*0tredIX9Cy<2eJf
z-}~vS%ZZu$@?XBWshSNGGi2?VM5k6WbMXbLOu*xvK<sr1gefZ85wL;gab_jhAk;lc
z(+GhRG5ZQLo<Lq4R&|S~P@J=o+2OV|{OZ9U-O5$=*xD61+_nyX;?_?00rIQ*$T|63
zyzOUubPR`MYG(#_f6@ll-<{~0Dq!|BeB}o1X1#Rd>(3sj0{ZQG#1Jei8(16I^}Yox
zv+L{KWm%+@Yj8;gvJtF$GqjmJfohn&`NZye1}Wf<<>Ya=Q{gmkW-U)TO-&#WnL*N9
zJJO0~x>HdBn@%Z0N<tuM9)VtBb`tAJ!>Vp(sxTr{9LB`C*FXHw%{5$eMQD!Xp3JQ#
z=8_yJFaeKu0{I|50Yz12x=U4{(gZx-2{v#NPa#q=PlD<t=Vp?p#uKQE!>Vra6pBmc
zNtk>6_EFnb{)ub@YXf_|e{(h%xBzLH{Q+;!#m1|nfwh5k4JNIFj4=Dm_}Nfb-m@Nv
z0!O`9AIOYv4b9I?lX8ddwlxL9JkZUv*;VnxRpi`5N+Z}dck~+l472NhYggvwi&<RP
zbhN8`s;0e;=LAr-Z*q98XDT9EG_!@EV(Q>IiNmH-s3}<>LFpvtb`tAJ!>Vp(su2*-
zk_8gxUjNs}-{th<IE@ZCv*si^x0;xXFUZ3NJl+Y!z8nH!x)sey#zNRYb5rZ_7EP#o
zlBN*?Ct~JWSWh4?4y(GwQz*__gqhD4<b&_$!}k?!1M7L+uF|5+R?Bvk5_VEufd{Gp
z_k{-52G%v0v<`B;%<A~}taB(3&H-XE8o{#QU8iN4nZ<Q+2DWE*buZ3ouj6SEU%{uh
zcGP6;7}zwkEF?iG4SZEP$+?}xdeX3}n-Oya1T<?YW`mb9BY(El6g0FX5D1!p$2);+
z`KPU!*&G_&^%_%CGEc%JZrDA)7@R!m_P`Z5{KGk6|K@t&BX#;+fv!MTpn(F}m2Heq
z;I7(j<qEK->edxVDB#6!HYAB$?KV3t!WAp{^wv)IPn<1<O*2aXDR<yZ=_KcN66;CB
zs%~bgZvj|ifh5%nhm*(Qrf19`P&CzQe@_ThnSjSTf!Ob21i}<mndvT7fl3qbcqiDv
zNj!x}$vg?Fmz<kxVLgGmIIQXxPocPEo&?ovcUr3J@vcBupexW7*o*>!HN-~kG_$#l
zs?*2n3Umch3Yf)pDpC3E>R!SXyR`JyPPI>+EQL)oOCcTl11Cx+Ik%HoPa0NrGgFO#
zfR-$fpn6ReYSTkTm8n+H5(^wmz~h}jGFv;+ie|b?MWD(AJl+X5a1u`;QZi41>Lusq
zT3An@E)J`@#ZxFQnI}Q@!r?e{+mr%f_d&9$nffq;f89mct^$G4)TeuCR?olQF{=Ub
zIVw%yU?mYQ^o`(5usLQ>&f0e*dN9JimpIie?a`2(&D@9sm}-2JLPpk-%%m#HINNRb
z-s8vxl#)ElKvU1*mL4}k5lq_=uxVy#xGD1W2w{nN;%XA>NyA#z&AWmAc}p-Gi(bhw
z@H<ZYwT(CODBJUW;>RSF|2W4rl*Hx^D)62}W{@#edFG<AMec9}><nU<<p6gv(Z&##
zh@HfG(y+52>6FFH%7yU^A9vrkw-GFFxpmq(nDKekz}mpN29wr9UXf~U0LA)i$%x+I
z&HVv@Adedm>zRs3%i6U>m%>gU9t3qq#F4d6-X39p%dwMKPa4*!?jdnGxSPdJmKDJi
zvva(Qi{yI3Vg;U?N?DM*{mah8y5pfKz=s$X#$!LMO#!Y?xD%;)aWQ|aQ*Q4EHBB8!
z>c%1Gb6*uuH!@G1^2|j<O6EvV-Q|4lpaO9alS0FynO;)isZs&!IV&@d5YxLhz6ODE
z)}k*4HDr7wM^~dQ-KuOUY?@gWtRXB_j!G4<o;0jk`32f3&2SV=5df~+78Q85#i8ED
znY<c${t#B)`#zD4)@H5MZ2b+o*_V_atj$|ibLeNMRlx05UZ-u^yR}wex2uS58H&^#
z8ESDY=W2P*2Z5JI_12Euk~tC<z^0j%5XZRLr-;`RQ32~o!&=qVRP?PfMF6<TjQmp|
z`_<Btbc5mOq4-+QR77ggmcmXT0R$y>5t0No0=>i>2NkfMG^|lQ&~6d4N7C!5r+m+h
zr`;a70v`Un+`DxJx&r4_;Q9n`e8P8Il>*@eYz~)BCumo0arno+%GnPqV<ofsj~<q6
zoo!ix`QtabWysgds@{>IR`+tQmgn&myr(X{>?e}7BVg0avWNuH#}F2umxm5mPa4*$
zuEea`sl=G!8_mc+1(IK1OT^L=r<vY~Q(t`RnTklw+G~j}g`GeG2uf@mS*!o&3ywbK
z>R8H^DOpwoQ_PBmJ)tYm6=<S>I~D5u`F*N}b$uGa@{zet+c67}<0kWrC*8UNS^<_E
z4Xh2UZ!l>cWSZF`r9vI*sk0iv&Kto~&y()w)1kvif|=Z_<RjUxzYj}O&m94^P?vMH
zaWMO)K#AuN-)#^nnImBVY?@gKaf}<n;`KySz<ScKR&_NMeXC3n*u6=2SKG*6)y~qA
zGK1mhb;$Rn@ytb}7HuKy3=%+4VizGvI2>W@B|djMkeMxzt6+`lHiep^#h4X~;t8+f
z?)&yOg5@7MuhSyT!jCMcx_g%|uU}Z%1~x2Yd;ewYWp@9wcZ9CM3KVc~s9rFwfN-Z!
zqd=%hD&;JCS)2s9#LUJU!M3@h+wrX@%}kcZ(Jh1Ram(X4SBq;ouUNr*>f-w#A|-Pq
zEPzcjD<O_?Ls-0?hzeLw8rG_=rlN0^DFVRB1^psNuDR#Ql)>|?1&LZ(;+#5=khsQ<
zkePsPMGKO#6gJJQ2#Y?3u=pI6DquZnSfhHNoq8GI$Xbe7wkREZkq+Hwq!H}n`<&^h
z-s@#{)L6Z^E6^1vDZpoX18V~t8cbRT8D$oA*7fUIn^b`HT?1<a>l#d22bpCS-7;kR
zdWnuL)#_fHYIz=C!Bd;q2NB7cm!KnI0c@HX4YNk6*{6ulQ>6mdlZLgbA57)OzVy#p
zirJ`;kw4pN3R+qcQA0*Ydg*9zFu_d`fub#h%`huMl3)mn&)p7WW((v-1-S=i@&^xr
z>$WWgcyo2@3Umd!0$qWwKv$qE&=n{sAPe{CmZ4A<S>01nv4Z#H#rHu(O6EvVyA3(7
zfK8{+uxN&`RCuaXz<ScKR&_NMeXC3n01gZCIP11`aDu3>%S4Po(X1L$GIa=)-&IL!
ziWZaHQKbUb(}da6&%mr(SD-7<73d1QEebr@@St0sZNrzXkJc49Mgf0J@xC^?WhnM_
zWT@4>oLB5EJazG9Kar9-5*EOwnUxU7xFIZFPecW*Ck<;=S5wiq$`k?MChObQNs08=
znB<Oh6|f#7`dw1!Uo=HvdNG7zSx-2(0$ix0>~io&)%W66Dsc4cVwF>MQac6A4WKB@
zmn6fi2E-SrGy#uy5Awu*2RaZwyxDUewdJrmW>KgE=SM=_bFOrf^V^G(+-!~pyZc~>
zbc<_7P0o_cq{vfvn=!t$U4J$rlcd+I?#wNIE=uF=BS*l_AV$9;>hO&Va{<R9Gl^b5
zDM<~ir$s(x1j!y!%qY5s-h1+RC67?`M~<)eiJzB>H}V+vf0ttJpaLIC!VEH|D$iU*
zqpV#ohn+zTvn=8ml>fMxAxwawRls`Eu(KfPlo338NHNP6WrDmC8dw|Hs|J(SL7syd
zcbW#)1~xR9v>wuv$~6x>nQs7`WKBM*9SOXB=7obipF604x`lX2OWah5WbFvpG_x!s
z!RPW&BhX9Cb5H^6NyA#zjb`-ET8f#=R`uY6RN!0tm)(OT-${1`-aZ99Bda?^jRt`v
zb>oopn%jlBfy_m8ELk970qhK-YO7aU^YUTR2^wY+>q*0UI!xUHCnsb^JI6s$#8EO&
zf}$noX8J&u;%hx~5xFJvBrJfPK~ycws!WYQFR{Qu1*|6x>!?<$pN<)=yLAP+0$qWa
z0?%X4jrg`a+eR+Y!ydyuZ2FyjM1io|kwhZh^?()dBlq#B7S}Z+1(MY2Ud}6aX_+-W
z9ZMESSOA-5Rze)(W}kxB>`tsF4eRNkR992&_fRC|Ey|1%$3aoVQ8G`0q9x}BBao%|
zTF+cWZpl0e3t(puRSUB!QzOtzEO1Z(>q)~ps+H=eV@B(4n^K_v1ISHX&OS_Q1>C(8
zxPOFuAE5(S1z4$_)#O*IHfyJu?f6T=Laf^g71*z}k74F1R*UOmH(AvOlGN&6&MS6l
znKeBfvvve*npqZ+pqGc)rw}l^6YELC(p9T|AZ8c=$;g_QXp|XMj)S6zBWFQg1fGQ3
zF9w4V$U5K~dpXQS<mT)c*cn7ohFQ^`NroDMUSffR3Rq7X)={lgKOHk#ck2pt1<s;C
zI19>c5P#cop7TbqRiD(SRbc-yUuxQbS&34QuTFvEcUFr=Y6Q!=W}TK~woED3Yz?dp
ztZOi79b|%;A9p=+v^y1iSqntf>R!$(c4?V4JsnFHNLT=yW>!KR<7S_N*X&NLCk^ZA
zV74?4@6?y)MT;<VFQ{@HrdFPl8uKJ6T5@hM0$GPwA$;?;=cb5A$vg>nhrIz&wbe_G
z!x6?_!XiNBFp!(gz&fgx>L!JZq8$<#nYm&~D&ZPB=eI_%{3GWx8gKAQJ25j?347wS
zMzFk#)@kcywobhsGONlh??WE3bMFeg^$IllOm740R(rX#%sjMFY~EwxC|MvuEw1H!
z?w|r{*OOV()3IcM1l3*6D`3+pG%T7LfnJ!|omfvA*3&_$uBNKKK}MO;+i_47ab!*C
zcoGyXIX4)AEXCJ)<|1;lb_DDUqA0_xXihTJ2=o#Q98|!1(y)$drTXcZ(RzV-=$zjg
z!M=a~Nh=Z8%dB#Mp4JuU3M^B=Eh{^=su3*rymi`onXOZ=x0BU=DR}PT+rWl%k6DeE
zW#(z47S}kkCJW&}f?D0ndBrX*v!<tG){cNpGs_|pq}1$F2$<c8^`v1v9hB-y%&J%L
zp4k^wFZyDRgQAF|WS#^?OU}*ofviKmxt~aqTQX0=-C;A#N{D0paD=g!cmt8cKyEfg
z`LO6dm_e*tSD-7<73d0d1-b$!QNVK(@75LQ3anTGb~4I5XKMYe!ikfBUoF(-ykeK8
zcT#7AO*3PTqM3~w6>3j7e)btp8rIW6jjzP4+P2bSVs<h0!ihN!iV%*Hc@m~pffKO_
zLkAS!K%Vl<MMO&GNmu|ogQ!|~RGA?xRe?$su%0xmqgttcI%c%)))nXqbOpKsZ;b*U
zY<SWw&$i*q)<^3Kv{t}FKrOCo7zL8l>R!$(c4?V4JsnFHNLT=yW>!KR<7S_N*X&NL
zCk^ZApj1~=0a#_XnFUy3j)S6zqhy{0MN7_aV+?^T#n*b~B63USNmu|ogQ!}VRhb%r
zUSffR3Rq7X)={lgKOHk#ck2pt1-b%Vfu;(W8$glGcO=8E2E=LZ4~||3w~!AaxALio
z)T}Ls%`wYDO3=S6hl3Gzy~O9_aTv(W7RXgMVxziEp(bZZW)#I3=bB0E>k*m6?J1is
zQsBf4Vm+QbipsVe*3&%BtO)zP$L0c#HFufKz6XrzHf1rhvG8MZ{7@d(AiX!bN(cFm
zSd;il9zmWD`@c&ucTj;hk}ymlW2*AZMWp3zIqVE#ndKoR`g|DPkTi`j_L6gkej|@L
zU_BXF)y;@G_N8~$Qp~bNnIJFJ2G$1FH<+{z@*K=u9hFmOHG-|XYn*!6yY%xUtNTu|
zTK*n=AW7X`<orq=K^{7w76(K6rb1!Xj(|-w%OVoImWLXFUYME0deX3-4oY<;CV)k|
zmW(K~Vr5V03Umd!0$qXoP=Fi5X!Z^<MRH%wT|tsP1t#F|P9V9PE_o$0-KD@&WC9NF
z1nW78rw}QbBSH0&b9*Z^9#35yR&|S~P+T%cg6g%e2z*t9_JRBt)e2f-j)MuPRYPV-
zii>8tONFD#1QcvKh1#OoUQ%MNh4nZ(pPw11-MRu@fv!MAf$NBGE3V^bd%P7X`W#(>
zu0U7dZCAjozpDhXtNUT_RGNUpJAvq(l=^liX+<;LrNUEX0uJv4>p6+15Gk1>LG_Yz
zwI>|EgKIpVx;U)r7EhtLWR3*YYhMxgstD}^`7f#!w8R_-6Ht4;%#aip&2*OvN0kXE
z*mMfDMYFx6#9RyOadbXEGf=yA1-b%Vfv!MTpeyiz6?p!DxtFM)W;S1f>G8K&0ki%t
ziotT<uI`7yQ)vPY?*yWEQg_?79s%p&5NAdtYeL<TFpc0j5mS4@Cfn8&GuQ<ViXx7z
z)&7oqM9GA<NLI8XU>(iXb(yYl5%slX@PZ2RxY0?TPaWof^*Bk3!_GzN6l$~fTB1>A
z*{UAw3Umb?z5-PrnWrDK4J;pX>$LSUTc=)cCoA7(>_)JxCf8{vW;QP7&p&A!*l_+q
zD-rX|%(B0#t6kj>gQwC29Nr1!W`{6&JYkBe%ygG3Po)Vsyar_1e!%vU-fB<SWZNnv
zqRhm9YdeMxRb~W}Do3RWC?%hy<)^r4rn^))s!Tw^rc<abn(ZYeW|GWoTy+nODROwD
z<Ovil%B)xwPvD>1Hn29ZuNq8R2YF&<p$_%bS&d-Z+|g^qTQ9R3_C2R7&=u$kY*m5R
ziw0}-ncfCAERyIPMQLUzWfs>}l*~e1syvk@;P6f$cC+URQ&eT9yHt59O~B!uU_B@C
z6e1;aB&c3;zS?aoM3-z^Q!fTbKQ+BkGNJ9rgzB6f0qf`+WtIaRV?mD5&EZ{UgSwYT
zW_*)Ede(wOqs+2Z>0qOO)zt>}MOuf(k@YfbEKG;*3T$10&}P6!u-x<3Y3pUSPQBhv
zR<6z1jbK^uuG6y2%(A~Y0~<EGy02Qn+s&Q_E=!OE><Cy-y`k*zmds0nBT4Bb=gqgR
zUPw5395QpTWY-h;swm<pni_I{RUB0&pmtW7pGX!Vqus^nq5%b)PNBAFwwIKcS4n0z
zvnLH;D%DL28AXdQ^Si%nSuE`d4@v>|;z7~vWV-@gfv!MTpexW7=nAw^fHjlZkW^7I
zt9z;PRGNUpJAq`@^rRKdbe9TGl?gb!6RhVXo<gK#js(?9&du(`dOUS;Sk*0_LUG9)
z391(kp%(UE2gegKs!X+lmYCyU0%~WK8It0nneI~Is4@Wsn@*v&XttM>m}_A@j?VYZ
z>}ddHev$1iD6Vb~Spj!Qo{!&dU4gDZS0JUp%T!<k{w>e8fy>iJ=nAY>0ki(DVrp0S
z!{Dhj0f%=2xmkx#9#5E}Dl^@s%2R0q4zB@;?o`Oknj@-u$@#pam;%=0sXHq(2O<_Y
zD2h0WHqGM6gt?gGU;;|X%#aip&2*OvN0kXE*mMfDMYFx6#9S`xadbXEv+=(p2z0mY
zDByPQ((Me?CqaR$XI+QwD&QDR-2h6nek8XQPm;R5$hrA#oIuvWjr(QfRz4Szo3rJx
zIc7P;G4>@n9*i*mo=_lq5XjD^lsYK77iPDJ&5ZG9>>C&M0+Oy?8}UKx;$tex;O#?4
zz)m2ZR*KoaclyiqXCp5~Nw<?&Pa3x3%BCspBPnKM`15jn!!!Qc#)mv9n*2wsNxX*j
zd-8a-ub4WhKzK)@GYF~LGZpQ7WWF2$JAqhc8N6NSI!0JRb`tAJ!_I=FQx-ET7A6v|
z68?L3H-hEGyG}a;v(RSpMzE|0)@$!W&D;Qre4k5(x<PTL5c3>Nz~P-h4%ZmBmJ6h1
z?Fd*;<2bV{Btf}}IKECJcuvI3?a_KXd2v|PEuKPg)>6#q-ECV6xNVKor|Al8UIBZD
zs2O?w7Q%E_ps3<@!D2R$dtTTyGq{v2ke~?5xt+v%(y*$V5px6tv}Az<)oZGluFIS;
z1+rgNtNpTY?%*hmj%2@!F&9x&w1u#N#-`TetuarM(n-$EwXmK*T^v?*i>FXrGEai)
zRjTOmu0U6yi2{5guEF>|;#RG}Y<zmp#((#z+lCe3X4`FB3dmA!EuYQX61MF$kH!yU
zv$(DzWmor77TwYW`pqEetsQAaTMC<IR)my<K+-(I{;gmqv7R)n>Sm@I0Rb&pAVKw-
zD%7Tjj4D&Dpd}VKn1IJSfn>IJq!rC{mx@4@33$8{Y~UoGLZoD#1l3E<&9$(eKwTVG
zb&ID^Try9B^z!pds#MYA4^RR3i3do!Q|=19#R~Kd?8Yv>XP&^}oOXRqurp(=Vz#jR
z!P1#W?{Mc*z$~tdz+N)!>Ry}`yR>;7eqPu#v*NTuG?1hS%ekGzdeX3}n-Oya1T<?Y
zW@C}rKxJDId?pV=OMF2dHsJA2Aok@D2-B@-N5BS}8_FJU$pV`~lBN*?Ct~JWSWh4?
z4y(GwQz*_^l3A{($GQStfp!Y;sc{mk`p7&9l4{Zh)+-KcI@vRG!fF3>7&z(H6*y3U
z^<4vN1IzMuot9>{NGaE5%0{p(S=VU^W{-v-e9hvzY6iQymoi=?CJ^X1gQT~1q!rC{
zr=kKjol=C9gh0|f!v3vbC$XM1tm<Z_8UX<<Ss+36l8xB-AK^0_s8Xvju3AA$EO0OZ
zk9Pw3AU**_Rc5+NRiM%YJl+X5a1u`;QZi41>Lur9lFV$526w&2)RfGVaGP1FC=utM
z+cvN^u-E%HXM=$Ykf&zGtD}LnfprZgt%F=IvpW7gt1Ix<DZrAU+vXJ5uU8M|3X5)6
z?x4dNpEiPBB+*%9Nistzv+S>;WLEc7RjlCCTf2LOO*5;34J0X@<lIhTJ!x3g&4@Vy
z0$Q>_g6g$9y|w8fqi9YtRIB~RK%mkDJYHT{Ol>!N0q=do&L9pnB{q(%33X4xG(zA+
z%v=lW3FPGk$)r%6wG^{#Q93yOX_$2Qz9Ma4JuiY)T8vrDw@UJzR9B!YaD)QfWg1u;
zSl3|EI>_}htK;9Z&Y?g!2Z+UJ1iN45TRzP_S!QPaU8KuK#jftfsWuL3KQM!&w|4gm
zn`TyomC``cJi>luY$vgvG_2}o#2f(u&031t;HAvSpKUb-4J`=-f+pbcP9T||NRn1G
z(_Jb8RVLu^POyQKcnXn{c@k7FIXBlLGn=EqU9T}UCG#X4GLs=M28XxXh7@=@guZp%
z(Dm%2bOpKsU4gDZSD-6!ZwjzxGRyudG_$&=s$vD7-rC(OY?@gOY#>SLB<FS#>q*0^
zZbr-z5YUnZ5>zi75INlRj2Q%qrdmNuEO0OZk9PvGo4r7oqAD}pr7BQq0v_)K8#sxl
z5Gk1_LG_Yzb1keVP#1?)-Qp<}m&}u(dJV(3XxFVP&=u$kbOqiP1p;e`joOxH+vp|h
zV|4{qp@3OjSFy6Idnv2frKPua_X?Y4Rs$PIQaZ`Goy2<5u&SF8a|8smWPt?LYpPJ2
z9x|#-wd&heuIO5}t;67|E@4l4ND74gZ`nU2&Yf#f0bk7M2@h9+0Cjb%EY0Hi1H@)E
zAU;Q>2^_2>!iE0+<(Xh}%%GgL?@07ugnch@-ddDoXNxb2)c7VP%Zgx<nZ%-u^BuqU
zIC24{B+oL?)N{C{$Bj?~({==GnpqldihMmnSYn>In#6k2uvT^RZlHhO63oV;S8@#e
z2ekNW8*k)Mw&(lAk4fr>^0<bQ*xW${-jm1-GNvleTr{@G9gcvVK@77T;4UWG7{U^<
zlUPq0b`~U^vY1)9FrMM#?)&yOg5@o@PCExPK93q$8(7z1(t5}jq?#K*vHn^zqBnSR
zf4Gv&Adedm>zRs3%i6U>m%>gU9t3qq#F4d6-X39p%dwMKPa4*!?jdm+X6JYpXC>>w
zlPeJ1{$+Ra&b?t*pet}63fTKW4T>X4-8kgD;&$PwQ#X*gh)BsC2@7Cn5LH{f+A@TN
zg@=j?SWg<(s(w0V5R0!t#z^j9X-T#kGCq={shNOoRkjp1&8!O65SA)Or3zS28rH1*
z0_~J$IEtnS2wb(2#m+rpMGCkTap_bZxB{{T+^lVRw#{C&hcp;B?rz&s!0lFE+Zw7*
zvs(*Cw+uyb<Rx)ybuZ^?c^+TEd+OrLej+7vB&apLoL9i6Q)pN;Ls%+2RVrXTX;`be
znu@+vrU(ExnUQ}AWWQQkl5Q{@JrrN-nTkj)+EUmFB!HmAE<%!^Mxd9N<Ddf8lZG{_
z2ih%ScBy*NrrQP-*uTs+Fi9VwEAaLy@a*jy`E8i^>>tbgBHUJOCA0aDwkmL+YsoJO
z%c|a?oLb$>xmup9RrkCv@zlka{Y0{M1Z<jF7Lg#-4Po(ldFX)kq+w@4(kb-MT8i0N
zWaQ7bBKTS!mX<ip^iG`m;#<#DL~7PvOLQsh1QI|{O5(^`{XbuD^iePMG^|lQP<$F@
zbn4a>=n8CD0X_*ESR+_IRo7`dX4mT^*IBJZ0dDLKtPQMhFlilRn%N?yLLKU<vl_v&
zWL>8vn903L7U0n>LvapAhFZ(ZxmupbSMZ*?__Ci!$s7p_VAIS>h-2Ik7Oy9w0@jm;
zwW_PB=v!rq!0t`DyV^$ns&<x^lo<?1uS32sjb|<*wP*`rXOIAb61xaV!r=&GFY&qC
zfy``yTm@@Xw<**VEyk=^6i;{+ci*?S5iI}6d7Tzx_G~%T-Mf5w{ldyNuwfzF`!8EB
zv-_XDBXkA20$qWvDG=HW)CjiC9lb{4EVJmAq1e@tp%&M2Ua^Ar)W!EfL`vpJSOA-5
zRze)(hOl@&5f!kWG^|x!O-0`-Qv`sUjBD;WnKF2uwIESTOPo^&5)#+g5i%3dt!P0q
zmcpi)6=BiG5Eh@KQU$Ch4Qo^nv{Nqw99c^-%NC`BFVdm=j5LCMe4jHN)qB0njvA{M
zcLllvB?b6QZ(wa;LxV}{AlJ*Rj(^WOivq0g8dw`x*I?2*$SkwymLc2MOLT0hR`=pm
z%k%gOp4!Adh)B-71RV(rVAITKm^DhxK1F<<DiyGvG^|x!O;z;@PBDYndH*ESO9!Nx
zfFY~Qsv%`c+q)`R1#1XPm80@7@X~l1F@spQu0U6yE6^3_3Umd!0$qWwz}u-nbjwhb
z!jW;fy63!NZ{f*{Z%Bxg%#pAFHqESrIK~ZO@p>XEU_EJAtGb$szE!3O05_TWuE7+@
zezmkD-C#I+D8AM+6_HxBrLYr706~degd{<YKrb=JK?STQ4Qo^nv^xzmI(6#`bOpKs
zU4geofhQZDbj!1C__FoUx&o~gh;A8*q#PM)buZ^?c^+TEd+OrLej+7vBrJeUGb<sE
zaYI<Vo`?!qPa4*$uBM`Il_>(iO=jeu0@<&YmZTdDM-Ro<dZr>$i?$SY0tp}}v5Sx-
zs1fKT<~XQ;^`v2q>VbBrVMeEJU4gDZSD-7<Q~`4XD6;vIWT@K!cM7q<!2~?sJ;)RL
zi&KFxMMYZ<n`2gj{Ya>Ll9Wzze*5;Ao6XTc-H27UxMtMkEXhoYJcSAaN7k-C8<9yW
z?0Uuwk{K-vN$?2RG_xY=@Qn*|0mq`d%oe|FN_CU6oEeqZ(0flFujCP`{>bt5KJoKX
z@kSoQ{_j%E9aP{$Nti*#ROOkAXq2_<<*+k|VU|T4gYq92GlU5+v<g^H8g>>Woic)F
z4=HBZqD+uiLIZ09d(~jlI>>V{+uvU62%Rpg4Qx2w0Qc32Yd+GPKi!K+@=@(b;_Wjp
z9OU`jK?T$;#7mmKmCr>)vUUXQ3}TpN5eYt*hZ=!iVxEHvSWg<(s(w0V5bM?z=n8ZN
zx&rMK@Ib3OL=BfflDcuodCl#@+(70cI+iSuumE-jQMJ{pt$Fz{=>!ckiS?vmJsqZQ
zfs+$5qn+cRDB>uYCqdDYb2EJ)OYyayxrp47c@h@D&LFB5W>uy}pqE(SpaRyDhILdc
z)lbKa*4?@SU4gDZOo8Vy=SF;6o^2zSsE^SV=n8ZN&ZK|`M=h>vfCEWtbuZ@?yR^)j
zo{l98BrJeUGb<sEakEdsYj!8rlZN$lP^zn`_IoIj@)l)AiQ}Ls;wYIXLD7<PgAvG5
ze643LBDZ9ogaxoOh^mEIm8lWvB^EfSfc2zd9o0(p(=nrUx2`}}pexW7=n8ZN9<l=R
zD^;7dEzh>ui}t_<^YB%R>*4^ist+Wo)xDfo?9wu8dOBw92-q~UEFwWK53^4pV0I_g
zlZK_MR$Ym?-$Rj<HZP$lGfEr>MG;5Ng1iVk3AbMi1|yKA_*&0gL~hQGft^7VWtbK1
znPjLD=p`07sDSmPVI9><_0ut<b+@iSS75^m_%^dOg01?bZlcI~nKhB4gGLo#eb>Mm
z!LqJdr=6G?Yqkc~2G%v0v<@=M%+o_Hu5pwskf2uga$d1Z%dF|?Sh7IE0@yUO65<#)
z`xLxpcVazhSWgF~x|(XghaxF&QD&4l4vHd<l6evoEjc$BfviKm;hVQTH$_BB=1I6a
z><x&jg;|vyjxhF;szBvoAUB(VbyO?WO$r%BJ0vhMD;C8QuAy^&YXr+ba$cvMn3-!c
zWg}SLMeDTnGFzu!omE$$E6^1<j{?sY!8H0zZv*QVNpy~)G&51k!vMwRJr<6V1rpTa
zTF&PVDxh{fnKeBfOBP5_-Q~OjHl0GlqNx$+g_+%n^`v1v9hB;7Dgdi2!px6_j-#SD
zx^suri@{(7x+uQZGZ&GYwIg6>5Tj%kk)V@@8i8J7frAQIPa4)ytyDi9Gg>b&51sQ{
zBiQ%PKWQc6dYM%Y(9^mCU4dl^xMgL>RyBg<p0`e0FSB*(^>(t_F9pv%d>hzs?lG(J
z_RM^=VDzfRbu{hJDGTAixmw-JdBrX*v!<tG){cNpGs_|pq}1$F2$<c8^`v1v9hB-y
z%&J%Lp4n5?i@sbK$5%xWN69=1ik6(4=>u7Zd~-jMB)4RqguBCLn3WL6_~8iC&ol#(
z!$58}MftGk9+=712Cmz-6nNUVv)j6$GR=$4P1FbK3Umd!0uM(4&)T=!HWiRHlV>uu
z{;nA{kfavsa$d1Z(>tlN!KRrpN72m2jS96V9CsAPlZN$lP~$5xtG2DQh%$qkBdQ4D
zD48cg(UNn65y(<}t!FMGw`87#1+X)Ss)bpVsS)TU7C5MY^`v1P)k^h~F&kUczFSwI
zE6^3_3cM8xe6Zmuw>;a1FIyk2E6_-R*AuSiiCSDwk=)lnP_6FeykeJ@S<}<8WPyYQ
zuxVx`#4&F6DR|B9#Cp=Oo(@WNHPwC(MN;0P%qVdj6h#~*^CT!*a&9mJS&Faq%thpu
z%#*MHb_P+kFsm{(0=>in2NkfMG_0dqseU?UJB0w~wjBlJwZ!YC+qM*V^zOFi>C+r4
zU~T}1!RYhvh}W(L#A)sij{1XJ$Opr1&rK1jSz8W!0}?<`cf>5D1U)bQgAwLCm!t9^
zkee-#t6+`lHiep;C7DrlKx}55YbLR;M`RMWr!0SEGow+Qx8<;&#&KqONQr*$apa{a
zeshtm$J0CxYgCWEO{h;>irHB4F*$xHk86<L8(pP?{70-wd?k+{&xifrrI<UYz#B;z
zCXg{zdFCS0^0pjy2C>ZYkP>}93~xx9Mi_g^IYYmZ#~iSp46N#A#2ow5J8LOs*`iF4
z7it4*1M3@1S_gR!X0DFPsk0iv^2xehdo0vE^wbRiN7m%;(FYRL?M2S7<Pqed18Q+F
zq;Dz|X6*>rG_x!s!E1S_5$J`PNvtOg>*=6WS7HKKv}?(TG4sXBp77ulc>0+KN4XR3
z3cS?{*gHgx9OkYdMV>+vaCj$>+)bCfl9}#O;3+Zzhj)VYoWxUzl+2N!dda!H6&jDH
zE)J`@#ZxFQnIl2<+E)a=Dnk1}{)=h_EiuQz1k|b_GbF`DGu@@aQDp)OHl0Fk(QGd%
zG1tO+9G%b44AgF2fv!MTAfmu^#J3gKmS@|_HG0r<ga^&OlaDHJIryl*J0G+Hth^)Z
z@2Z*X>VDY0NKC*Tg6N%;`gZ1h!g`v=nbp8LlGHv$&efi9{0^@1c<SP?s#`pT;*vQM
zRIhzS;Hx6E59Gh7R?rf2985s%`7%RNTr|^NDjZcNpkUJ})E3S5k`i+*tjE#${LDb@
z))nXqbOpKsjT8v`n_?sQ4tqZexch0F?)p3(dhn68%*OJ!+eQ^I>+j;6Ecfl|ei%HJ
zCgAW+AbKZtw{7bYupSO^W<;_k)Ex=a2%Zx$wI^({ZA~$QUErW7;>cR<@3=>lOlXT_
zMLPo4(Og}Z=^7VNUrPors34CUo#gq{VGdZ2le9SOT$E0sHfygX8fBKP>cOr+S703q
zJUfC$)ko$L{S&2aVELF^r>&RSI`w)xS@||&H-cp~xlT(m^NaY7i}^*BM-{b!4M%al
z&*Bubi@^!3S@u^^v8(%G@Kl<B!#jc8><}i8CrnY5neI~MsWbtH*MKbB57=JPTkQ#(
zY+Hpygjw)R9ps@Y;wYLCOe!2zCZLpjl9r$1qM7be;ixhJ1)ENxwrIAOl$c2}vvJiu
zFs8`ijglu&v?#M;RXl-zZri}xz`klQX&vN=nT0ykQ)e}TZF5Jj5pTWBYS{Oju0U6y
zE3j1sUN0J~(Pw%a*sw^Va}=eSp_Ex%S5Yzxb*b`Hnt;PQf#{tS@SZS5Rc5+Nm8a4K
z9Nr1ma}rM>QZh$^>LuqZ-L_tgM3-z^Q!fTPy-_luEs_=O2v|pRbzLTAMbsb}(aqu1
zfrRlIXJ%8cU)$}(%pkPD_|q^AtPSjo29wr7u9sOI|DM$q=n5=UAS|pqvaAs-x5ahZ
zdYP?LueXzxYcqBuSQfnNv<R~>Gc}9rIg)z9hRv?-hrv@|0uJv4VmEu9aD*UkZAZX*
zI>ni3414Cq<#10UcuvHcZ(F^PaPm;hV99<g@KsU7Q8YE={;D{tOhE0@GCz?lLPoob
z(?tUcHl0Fk(QGd%F|U%$Z1=Klg?5CQ-~DAvqTRNmfP1l>S^6Yhfwd{nH!5qpBAriH
zpexW7Sf&6g<AF7k*^pHAGpl>4@>H6D!#jcKos?SklU6j-T`D|PCgAW+u%4563XzgI
z5>ziaS9`+o?r1!ox;U)r7EhtLWR8TxUbKQ**nb@yPspgU!&W16sd7}BfZADQhNQS?
zrn^))s!Tw^rc<abn(ZYe=2}>fqw{?;dl^8PUs6MGAa?5tbOpKsU4genftMQ|bj!1C
z__FoUx&qA=FzfFsMs{^S44z68aCj$>n|1i)@q{U=GSgkEJe4Nk@EVZlPKC^@IijkU
zoX<OoDPTRGy7MywHE>WAaTINu#ghqhF~`9Kl#-btDK47nE)|X{6Hu_}6l#lRdr678
zT-M|0e12x*e@77LZrf47?cSx^8K_T!0(`V|+o}SN!PE_)H0eijTk#~R+l!p5@7&uP
z(#7yHax0&U=$NzRusLQq#4+|IIjXhC_+5RwD9O&Ilrr5sKqdue)>6zUG8oxTWAGan
z_5u=6uMNY}krKPswZBkx1Z<iaq_TGX*~m*#D(ocIlZG{_dq^nFaAYmTY%Kb`9N+Ma
zzqauqPl_i05o;2!Vf~&wUhONU4k{4dk?0IUs`gAp`yQDuN5D=XmRSaG7rKrSmXMvq
zdeX47AnBCF%!-AHgsX)Ap52XLdGW5(&cH0RnY<C~{`T5t<|69*WSAR3vFy2IsM`Q{
z3Ng>Y1RUN8#NNt1VTy`&1gxidoLLc8ZX%APX#~%Sn7KV#k0&n<d(iD^B8B3trI^vX
z+qM*NU)$C^eVVSo))laKh?<G#Zy`)K4vG$L7pXf6i`hW#d12Gc;8L<cf+8&Eb`tAJ
z!>VpZ%n=aKk_8e}uc>0XE_22d$bMC=_RGS#gQGM$lKn2mTtrRL7QzM^n_7>z#ym+%
zCpkCQ!g>OAaah$Yo<ecSJPE2-siMcb0$qW(S^>U~xK-QoY+Jo%4{9!Mw%xX+fGp)$
zt#;d%0xYW|>+h-|?do32qFb6kzj+0p-rA8?w570VW<^Lz2qeuT?B5D@66;CBs%~bg
z5fIRl1rk)RsX}df$fz>a3R+@;g9&)N6G&!jM_SQLcc}<enSjST!3Iv^DMU)<Nl?Ay
z+*}Lm3Dm`5RkwHw#U=A39QLABx6LWAe}`>uu0Bv#V517~A1>~;H3h=C2f98t;2H7O
zG8^mhZW~p=EUt@lddaY>dvR9m($ZVIdxcFiE5eFCfh47qoZCsPCk?B*88JsdK(m%&
zHWnRjdPeTqRs^5P!_X36kcSO;yc39hIRwIVE7}pTf#!y?$6K->)ICYl2!RtZb1keV
zkQawl-Qp<}=Pb!ASJY!&fv&&?6sY>hJpG()VEyR_IZ?+wv*#yj*V}AU0oHd7tPL#7
z+jUx+*&?M}n<*Q?vSeMSC73-Lg77tq>#7;->R!q!c4_IY-Mzx5nbp7sl9WzzZYQyx
zG_2}o#2f(uEm<Hz^^%R)_#fdj8>mvNF|JxcODu3O0grbA`5-<4MO9|HOI4uK1U%je
zHgFP8AyP6=g6bvbW|GWojs|zV#?+L|lW?0^sVEWWpW8ODHn7)RjaAyInepmqU~OPs
zgGuWk*UPMqf6wX)bOpKs+f*Pdx?Q<8Vl;wXB+*$EN-(<|P|7U(t0<Y(JyjJe`1IE9
zUSZSBYG4CNN+&tDlUPq0R&_ICj(~ucERdjj?KWPwHa%n%%}Iu81ue0_!2~>BURX?R
zH+uo^eZ$Tm4m2e;j;slFPr@`p;6%(^3+oBw<ps&4P@J_Cvusg1IR0svbojm^ZD2hw
zf>qjjnXOW;PO2-gAqBY0G_W?XuEC^rkn3eu$G>NtLxFG(5R1_WcE8HEe42Z*%*^_`
zNSBR@UEPaQZ5-5oU<OHV?d}ye&8!G3rGcb*g#F6cPGUW2Sk=vlIRXNjwG^|#OPP^B
z+iD6LS`r8ZO~B)wKr%m(B&}$syHo_KOu*xvU;`)d6e1<_B&c3;ZmvaUHb;ZIUSn!X
z=1I84>|$_uyKPE=u&HVKFkOMJKv$qE&=u$kbOr870e%Evmi<*&W_3?h#R@*XwYyi?
zG_xAmK$6l)&g~@DlZI8@jF=-Jpd||=s9szJh^S2u8C9lQK}#%fFaeKu0<oLDK={64
zXAlRP5*tU!JPFeXffF%vEvzSymlq_HLUGAF3AdP4i&<*k<6VKSKv$qE@DLOT+}1W~
zTb^yBm#mM~6<CD=X8m2o%C7FEOl=(0s(S`WZ|&|CHqERCHjp%ru)mMkNvtOgtGXF6
zM?gSJ7D!ONrV1nf6v%#6t@^f=E4r3#>oB<NrR%|ms6g2Nmi<HI-Z>`~@X1IIJbVQL
zBdA+tX(rDfAU3N3@i{6@;9w;YF7)>=&jg!e2IZ`MN1_KK?0bpx)}kakTYOQZ#y2Th
zRs@sGBo<|y@A$pPkqam#d6t2up2ICYZiFJ3wj*HE%+hdE<m(Z_67$5>B-WFLwW^zU
z1O4-sU^W)Ll4IaMpv7O?cq5OpJ>MsOOj19T$2FA1<_;?Go<wGlF;#iyqOnEpa0KiO
zVwmLscQMh%5SECY#Cp=Ovmoh|#mvfu@eCh#-?z6BEN{7W+Bul<dDOt#z`6#L)<eD^
z)!YDz_1BUSy}_IN!<A$PdE9_l&s0QO)~+SG6m|mfAgDVcj;ww1_6Yl1j-AAM(y&H#
z4~Y{nlRoEo7sIyO85P*S>duJRp}GQHfg=>K_k)^djwE&Ckn@V$g{My4K;|MMC37S!
zfSo~9ZS`u)5Ed35Dk@+-X;`cJ>6k$*z6Kd1xr3!8*=or6NRFmv0=iY%QrI-JDp*5U
zsvMOnU_EJAv+@hHQ<~u@nj!#Px2`}}pevA3K(>IJwJp!K*^Bm&2II!vZCeVs{!ONB
zUC`Y$yIn<e%TOFwUJ|!f_j0b5=kXQ1r!KziCsHy;f?Ctdc?E1bg@#2lgr&k$r2^KI
zhPA4zspwl}iU4qv8TqF`_N%2O=?25mL-Dnqsfg5~Erp#x0tia%A|wfF1bT@%4k}<h
zX;`CrpxtSh(WzTkpexW7=nAw_;8`o+j(cwkxZN7(-ulNH^NVm>wUx{kwyJNRYtb(W
z%c|ZXom$<?xmupbSMZ*?__Ci!){cNpGs_|pWJ_fTi_gnL2dpOzYd302OaP0PVm1~U
z`HSsdONON-PBXm|r@r{sGZm4Vwbv3|3Oj)W5R}+BvR41k7aV=e)v=T-Q?jfGrkE8A
zdqP*BEAX%t;A5qMHG<_MbDg$cX6w}J?PSH0qk*-7^$jMigG@79q*SOwJ#|(iST+jl
zv;;G`SIN5HuD@%Ba3raPx}2+xgV{F)N<4@7Zi7h490?0x)67bUW84rHuP34c){};{
zs;jB!TV;yC?oGP8+D87Wc9xcu84O3SL%uJKXD%YOXbWLykN|=by9i0b;Rs_d@wwZ9
z%xr;N1#48dDby4##;jNrPk0q~-?z6BEdR)PopxeoyLb87M{NTe&OT=?;Ch+WPSEqZ
z0$qWwKv!T=AWTor`?V2ln>%`qv<YTAcXZ28?CQu+i)%TrSiyVh;`<;XC37S!fK4+i
zA&zlFSiGKy3Rq7X)~c?iqHmQc0>JGzUJL$hYmiz?OPmJ7iBn$%>zRs3&03J?QrHQE
z9{SaXBWt|)W0E_nRKR-DuypnE$Y@41Ybj>gqIB>@I&`0rMzD|XbEczuub0_TWA);$
zKv$roz;3Bk$~t+x4Qx319H(lyUS_A7u=hEE0<7;ESQ}W^VA49sEVJmAA=}qWbZn_s
z_u{PBrBRz$(-X;=m!KnI0c@HX4YNk6*{6ulQ>6mdlZLgbtEsA9!6{}CTd-}V%F+_2
z8ZtW4OGmMpfNoW`5H`cC3f2&oDo5pE;HB|oU{A4ay-i?*+r7C6b=#BzRqymoP27j+
z3Umd!0$qWwKv$qEuuOsImZ8|nk#V@X=RCTl(TjXfUVI-!q-2hS1+ZymCB!jq2#ePf
zQ32~o!&=qVRP?PfMF6;Ie`7XKRqZS-DKi+3UW%{vOhu#?Z7J*o5<pO57a>VdBhX9C
zaZmy4Ny8e|1MN=242`;V1-b%Vfv&*Yqrj65kGkdAHhkIoXkCHU3PiUIMN*CowYryc
zwLFin;5~KmWj~RUIT9AYrkRxx$G9OZUQa{?tS1d?RaaBdx5^X&;3hNjPl4=LOH0xX
zhNFk#YdupDsYP1~JAnicl-NZ`64VIv5_23>z<ScKM)g3u(=ek`x2-9#f7xwqthaq0
zK0&%|RRMDYC=U81$xyce?i6Byg9&)Ndypsg7pDSYii)-zHpi?4`;k!hBq^Qb{PyiJ
zH=Cn@x)G~xam}d7S(2F)c?uN<j;vjOHX@T$*!7GVBr{qTlHd`rX=X*#;Tsp`0**y@
znJs?Vl<FpBIWsD+q4%CVUdba={gLDAed6b(;*C6p{okdSJE*{ik}!jesme1K(I{)z
z%VB2_!z_z92IW64W(X5tXce%YH0&%$I%NdU9#YJ*MVTP4ga+0I_Nu|8b&%&^w!gjB
z5jtH~8`yBV0q(04*L<Wof4Ucu<fGb=#M@_HILPz4g9@lyh?g{dE1!#qWbFvp8N@Kl
zA`*Nq4>bb4#5@NTu%0xmRsB@V=+kX;3hZBXo13c-)D_sM0-m|l9inE?K$5y~$a&4}
z!rVaSB082Vkgx!D22r)utF3wYFzEyhGl})2VLctDZh?~%GNYa2peW)fnI}Qfl5;bC
zAWQMJp1FwJl6evqz|J757G_nZMxd8i;GhE5lZJIvE7ecOjMm+{0$qWwKum$>G3Q2n
zTb^wrm#B}?6<C)7VO?}Oo6{)Z$2Q|pEv{?22a?q4Ud}6aX_+-W9ZMESSOA-5Rze)(
zW}kxB>`tsF4eRNkR992&_fRC|Ey|1%$3aoVQ8G`0q9x}BBao%|TF+cWZpl0e3t(pu
zRSUB!QzOtzEO1Z(>q)~ps+H=eV@B(4U4gDZSD-7<73d0_N`Y{yMtA5Vzf!eXTgz;$
zy}E5v0nb=!ab28KR`r1-wYrz{id|Y}O;5+H9RZtWmPI7!<ze<I1kCQldeX3T)v7Bo
z_j@Rk(&i-;Wk!kPpeW+VS&$cjC*k&s!C(Zk6kqF^i^$E{F|ad;q71X5J(CPI0=>in
z2NkfMG_0dqseU?UwC>gw=n8CD0pDh}MzB?%)J+swFS90cbkL{*tnV6FBUsio>$DRy
zW6jpU+Q7O7lh#2dnEA1KJgUX@=q?-rakaXa^NL+sW=&7Wk_8eLz^0j%5XZRLr{Fca
z6YELCdO9f8)l~aE6iIoDFmq$YcvKYgjdoGb7e!0X4MrgAkZ<_rZO=^+k&<~5?hbnc
zqH1AQWrrh-y`(Boc^JseW?&uFN_CS$M$rxlOw5W!@q}yWoZlM3@{gR?X(wjp+DzF9
zmUq!QZN1FasaI#!73d0d1<s?uvqdnCKGWO4x<wM5qbR{l+@h3+0gBCgEF2{ZB&fx;
zoX;IpK<#=mYkE4CERdkO%XtNCI)#QsQzOs|GrJS(NyB<NDAm<e09ILqSr`i)M@4aT
z=MJeCgTV-NQGBguE+RK;N5IY?M#(H9K_?G20=>in2NkfMG_0dqseU?Uv|eByI_I}W
zu<xIL(n`ejGOHY*r*#Fo0?QO|%gT<eY6QzYZ=JSYX6w}J?PRrI3Z8rTHn8E`V^-s3
znR(i%#Wjws$wD}gpjP*CUa?Edtm)~PwIg8D%(93CDK+~P0%mt&J!x1^2c^0av+5O`
zWX6SY04Rz$O6EyWwB+1OAILi7oBN3*xh3-?+#NQ<tb{nm4@a1OrWuGF26D40%7;bw
zz)Y?-aNV}0K-D{aTO;>rx&mE+u0U6yE6^3_3fx@*`4NDpO0B<Z+60o+LS4=)c4>Mi
zbvD>EGv+9o*|<@m_Jre(!g$iKo(^h!C1&+vHo{Cmg@^+{5yDY2PlBQ)=LRE?rTALU
zTtsfkJP8Y6XAo5jvno>~&`T_EPyy>n!#b*!>L+97Y2B?W&=u$kbOqiT1wPpDq+6bC
z!<Vg())i>2fQNuuT-PuPB&pTCoLB79GHZG|mMoC405;96ggC~{J_WDYomfvA*3&_$
zuBO`Wp-9SGlo=(CgQAF|WS#^?OU?~OAWQMJp1FwJl6evqz|J757G_nZMxd8i;GhE5
zlZJIvE7ecOY^M+a-L|8Eyq0*qbla8!)t^Dz8v8Ao#@qmkbALxN>}o)q=KkR5b#M#$
zV7TqMDIzs%%VBRo0to7kn1z&}e^(9%Bg}U$N992vH(MZA!5Y<V3N<-PGNb5#*vvTB
zOk!V;$Ruu0S^mmqMx!`y%V9l@<IM7q68+xe$V*ZD<|0{-r+FOKs2+WrP@lFGv$5i1
za{N#p*C4$&x=IK6k64rVN*+O;5BtAMF?UdbH<B<+AY-cX%tfT-Z8_`=VwvS3CHj0A
z-jFnnF!qvjhJGWDIbb~*Sk=vlIrgP@)>6!}MVTNk)CSfD);E~64)Pq#Tpg8DXElQ5
zlXboJSg3jEsT%-}tjXV_4<xADi=1D{BgjJs)Z$=B-&82f+7Ym6W?4jn*YZ#!&<it@
zSWg<((?O}O#00Qt*OFnGJ=$H-Vs%e=Pzp@1x(7wNlkEz;#R}LvM2#5ct{_F8LKAR!
zCy?Atm%Ngh?o!|>G69Eog7uulQ;3wzk)V3XxxEz{kEbpUtGdNgC@z^JLG{{K1imUl
z`#}DSY6UGZ$H4^Dsv$EZ#YHpSrNU8V0tz;rLT%A(FDWtC!g?H?&(93hZe4+{Kvy85
zz;(p871x$$+sZY1&~t<b&AyY5DsVaYsJ}ZOv;wTWBkS*~ne6I**u6+hz#W3<os{}^
z=6%9?n#Y;dz&euDK1I&eo^bpQuJL&4;;^b)JcZ(tITBQ_eMR7_BD4?Wzo=Hw5_23(
zK<)W5LsDEc(_JbYRVJWd(<#&z&GwQKb1kgL(fRz$K<(BQ=n8ZNx&n<92>Y92Blr$`
z9|~OV7901`I@R-eDzE|nT4t;IwTcbs{Z@`(*55@HSnk`^{V;ecO~B!uK=e-PZrj!)
zU_Bh-%!p)7s5=s-5j-biYERf?+nQnqyTCzF#F4ey-*Jy9na~!=igpC7qq({+(={%l
zzLpGLP(dCyI?3~?!yK?4CuwomxhS1NZPs2(G|DVn)q`DuuE4`rpz0&@^kcSx<zsH0
zwq9oI)a&hJ<=c$i2$t34IxWe}FXG#1yW0jfERyIPMJZ+%gA;hO?60C^SNFr<sWbtH
zcLKTDAxs`mn4&5(-KEM?X#x(f0a>;mu)U<W+7mX}whD;|vmox<+c9*gG9#E&IVw#+
zDfuKVKgC5e-KD}&WdaH|okDHVY%eJ>lVoP&s(WBek;5A$PoQW~X2q&_0{`5$fwh5s
z)nL*($P+UQb*QJ#Y6RQnj$R|)dYRR*?>Sw8u0U5{s|vhcG+3k0^fs_zkwoVxN-z^Q
zN}0uV6(zG!mnu)C2{^nHh~4aY!W31R=`K~CN)vE+Cs@x(JcUTf90{tIoUe7;x)U=%
zSy9B1wbYBjQKhCgN+z_WsAxyPI+{nB6;Xp^L^p?bnGNb*9+~k?3h7x35{)v;R;7dd
zX_yAq2KGgRN$Vij%dC!n&*}<v1r{n07S<hE)(Dn+-a2i)%+{&b+sVqc8M_fI3*L2F
zmYG@h7iVBMWLNi9D|o$=QfvDAg!MExlpWrZc}Z|2DV^k8?Fq-vL*wz(#bH&qcnZZi
z^AdC<s9rc^*Aw`v2;nH2Y6UGZ$H4^D&MNa0Ns5bRx=V$l$^;Z_I)&Pz*<Mm&u0>`x
z_4>8lqU4LLNU*&IzxyUrRe4W(FbcQ_!?Y9a3Umd!0$qWwKv$qE&`^OFf^8PpRea3q
zUaCBmCgAW+AbKaImi?p^&2*OvPn8Kcyc4YFB%VT~WR3*YOU~7vu*J3&QjUXW=0|FQ
zfTD<_XsQ*0i8&4?pmtUXZ7HfU(_N|@l_sEI(<#&z&GwQK^D40(N9VIM1F&0HpexW7
z=nA|w3cTF#q+6bC!<Vg())i>3fLVW6F|w=sVenL%fWte1=$%yGw&pZLw~{#$CUHF{
zdkcK++t$4r@h=Z++uDEH8o!DU+v|4k(uX}nXMbA(K3ckMRRPCfvAb?^;E!Zk<cX@~
zk({d~ki8*Y3@?X3ow}9JMMQG895%-+hd9Q*Bu7J7e1Yge;HB~8U>(&;btNW!i<V+W
z;Q_JQd+j$a>;<G%o~0utcCF6<n`Q>7tX+RLa=E0!PGUW2Sfjd!gu1dgvX){t7JXih
zZ+OOE+xU<tMU(%CHHp`-eor2+_7zhH6$tN0bOs?+d#0j&kIa`NU?&jEEQ7ZTUB?JZ
z$WCHCY1mnibjo68#ll3wRl<MI?nbb@c-LuXU>4d;-UxR5p?RB$D^TAj$J_vlh0i5J
z-3InIcu%DXIJ^^xy_I{y6cz0VSWojfvm&hAL>x)e2%Zx$b9=NNPu?w9AL({0We-Sk
z)}qYhGYzKQwxxjI);N8duE6FMuy=@>k>_tAOm_u})XirK1R^sCi&^cNibyNkQrHQ^
zgP@odAtfP@G>@>qaoI_%Ck?B*nW;uVKuZ=#P`#!KH6$5TrdsWng@H;F@OUQ>`(2Dc
z_`YFh5C@tP8%N1J3DXFH6ESlwtS69{7bKHHamhRhx0#iSdb}&p6?l6U;QNSMwJp!K
z)ob>k=Hh1CZCeV+Qf|Li-_~4j`82y-g;{@BsbW|6Ql>TzYSlf1q_=kW3Y%tD0~<)1
zN7%m=>?GEchE?5+m?I#dB?}~|UQ>mUe+p#3s#eev3mi<q<DEb<TRYN<X1Ys7pvnY1
z-U&8v5>FvgGEai)CFkZ^SWloX4y(GwQz$N(CqeZpRrGjQpexW7=nCAk0{n-IyKPH>
zr$adRK-cF6JR{y(W^-qpxkH^<0kgO+;(N)kt9x-)?9$R(yL*LAGb_T1K7k~qlbqX0
ztS1ety8Zv{-93*iS9%}tzIVx8dO@u2LhA($EZ~xyP#Iy^05g~6g+pTlXG$12RKU=g
zN`hc0Fbw${tN{fM_ajW`FW{UX!HEF}hUxRK>F${`r{37}Qhl4hXE8lf=k0mUuV<!C
zUGj1p%rRk-F2-DC<D}}LC)rlx%QB)VtF#T7*>v=2Jtb+s9fowjcG`22F4-#VG%UqX
zO7An^w1puTC7So5Z5cAI0r_28tJRtzeTJ;XY-MW`^%EfQkqd14mHF~}+$U}S@*8=f
z6|c9l7uuj@UP2&8jvZp3v^m~hXUtc2kyN+OE_X_sBkOg>Ol6-OhEi{HxZbpf_H<vS
zRSyo+C;0hCyH`y+U)h$lLk3k&<+|NT+cKZFTCKqx6DH|e3>i?Zb^quz@c^~9)YxAw
zm9k0<d1*TOw4UDMFQ#{pNt>csz04Xiv+3y5dP+OwVtPn=)}qgVYOQkJ>||kYT^9JE
z?{Vg=MV|prD_fg1)1SX?yF=`g_Ac+nRmMwKmhX-oVxP3#4m;hJ@_H-VR=-gM2oShU
zf#IUtRkshuPH8V9dK00U%HAI$)g1dbmDHT>Gi$>Me*V$!RnyK_wk7S5L6uXvZg<kQ
z%%`nZYcR)zNxBw822^X^KX^TP=*fuH=*oy{sgzY>$V=1Fr#0VL*>(G{H>CBo)1H%b
z$yQ;fVKGYSeFmJiFyx{{^Io(qL&hzGEDXuy#h9yXangL}_@9QE?|!YGebV;%Cb-JD
z-pa0$OHl-FNFaBa9b%uf-3~k5mhyTl+g86(Zy_+eMUpnhPHB&){I;ImTNW#8&flx$
z=0T-B-IvDd!J&E{I47BZw0qUG^OdcpEmMaKI&a~4GH!R$w#=ukR%<ZFgh{#>bCn(X
zGOgiXT<X->lvO&0bT%D*T2Dz9{)uFUtwytYnK5Km)6u8(ly=C)^pNzdMV|rHTIITV
zFBbOJWq}|19%s&4^cnD^vUi6rt>UHxhMU@r%@80!fB*pk1YSuX{|KNt_HWA7obEGg
z!wG)=(e72#&R4c2?T|s0Q@L(;(zeW}tyXI=$An3`7DEP9Yvo-?A=N`qMr?{|sgzY>
z$V=1Fr}dPieb^h){n}~INxEdKu+y*>eFmJiFyx{{^Io(qL&hzGEDXuywdgb8NoAWc
z*A~}LfB*pkAA`V<+uDuBE${6{-!j`Ga1{d0`Fm4U?diTus~#MxQ};Q^{G;8grk$^B
zOWGlW&RaO%N7|jVE%Rxs)f&t(VUn)JkO9?Nrx^|ZsbleTwUo!!yrb9h*m^j0i*KFI
zk5OPa{#*7RW9@3573gPsbbR~*L$*-eD%bYZ=RZK)oCZo;mzhn+qm#t&uKx4OH%hxy
zSxR1ve<;0=ws2glG(I_$EbeXkP*iQd8M0VaI%g{@eUlY0ulR>gC*Hs^Wx2{Bi}rbW
z;_(2L&iQyo+WE@n)17+$Vxr*E*QdYQN!v1?wpDL_8nXU!%v3f``nJ3d`9ILge{JKt
z^06LY9S8ob4E?%%+@+)v=M}1sUzDD6l5uF&a-K9UvGnqcwC5yEWlIU~`-)9daOr7x
z(zeW}J%h{-xwx|RiPIzc>E_pN-6?H;<gPQ`qO$xx+9CEy+wHK^?J0kkq0J3ob^cu$
zF?oY;?hhZz$f0~ZBxzetlQL{E?n>{aX-`S|WT@_lX;_TUpKjrJ%V~Ggw#=t()cX|i
z0+p3@-r}b?)rvP1IDXf?VMeJ45O{__dq3E+SeHT7jiX#|xLx#_SKUC)lhU&mT?Sl`
z_MD`eyZN-$6kMw4Q%cp*w#=t()nBf%6gGVZ8GDvq+Oo>%YLnAj>au9FgRHhGE=@aM
z*`~Bj!DUvLnN>&IGM~0N`3+gFGE2j1R0SlRAV7e?f<So$yxF+rz1{4a_AzZNH*RrT
z0-Zl(x~(_#emD0|6_bw)tJ^K#5>HO|<+?haPoLoX%$q*;r)Mp?45-fZ<$6Qf`5{?w
zHJXCUj6Sofj<#h!ZL41GD(h~Fs(_?BMZ<sUSp3|URfab?x~x&v+qRr0W$0>Ln)Z}r
zNQMe~HDv}=TgX}^y1Y~!ZOeSxMt#U~FH>1o5(EekAh4IfmwP3a_tgZt`!mj~tv|JJ
z{zbT3jVsyPaI3!db<w{hTu${}=&I9wxvq}q(<k^o^QMpe=~;|tq@Ay9F=IOONYxZv
z+WPWQceE|@Y1;?23Nr~;W3IAsV#B|>-0#bXwye_F?7l0F^_$<eoF--HV*I}JUYhol
zWJrbzI}MAm{jV={S*Lk-+LAX8S*$9ZbCs=5G=Knsk6R$WR(6P;(&ks@b;k8pcAZ{7
z&Z=_c*dg{w+wZW`Z7Js~yGUx-mi47a?UXhT3fCDkm6dx{Irq2c?=73?GN?MJm+R`m
zp?Pi^GNsSU^wUOq)}qUR3)0S4ww7`1ZwfB0eR`^nwq-tTt6uFY>u!pwfcqcP`**wH
z-?Us?R+-l1=(5)1dcSE}&XY29H7-nhPBJ7zg}s_G10HW-T&uKoPdgU&He_s-woz|~
zWX@_#Rkk{5dce2S&9B|MQ`-C`=j)6YuI&D&{LQzzPuk(l_qjFU^;WiZ2gVT~K;R|?
zHlL#(?|yiE@pfPDly;vx`WDvt%F6M0@{wV6)h;8d!*#jdaDwkMZ~8eXJ!{crzy)dN
zD_hGr_BREW);>K|N82)=wpFiom322oRY20+zoD1>-PYkaH=iHg%JOxSqsxe@-nQj5
zDMJ@yD7~#lX*{iv0T1<5Y3GMz&SK<eqFJl7b(vLlv@P>#vua;H7K%^rV$4;xIBCA~
zck^AZ*|SsHPhWFS&szI>D|^<qOeR2JO<?{6wl?!w{rjXHo>lW}PQKpCUUS#h{(%BH
z-|Z0lr0sUt>9&-Ml}$b}EUw#^-f_w5bYB`bJf&ss%$YttOVO9kE(0z|J6~BAT#QU@
zo>NL&pIKE$+cKZFRj+on={tC?vQemcfJ(Wm(Uw)FRGXaK(l=dJZg!B>HpPW$7b@G7
zwkf#G>N4|j$2U#OLfS@s$a0lg8dl?R0b{x>GOSKB;G+}R^ppP4?MlG}2oNAZfB=CP
z7AVK#$w!9OG+jnihwE}(9nYsv@O|b@KL@2}ExHW2Ankl*YZ=G>rr^@rr>E*@TjtZY
z>ea5Y?xv^;NV-H{J{taXtVUZ_nbPFwvQAZR+j5$ep{sFe+EbDt87l16lo?QMA#0WB
z@=|rQE%Rv`^&!i>NM%`C5FkK+z>i1Zr#HOSTi)9ZziqZgU~hrRM~2m+x{Rn!_vN}e
zo=>0P`^=j@_NQkpx(v7=?R;fx8OQ#n;L_Tsr|M{1=F_(7)vmJcrl<-?x>Gd#r;f$X
zZCPb_lcUQTRlRM?X;Ox+#-(XbNrq&ouvb%NK(&ReRievF)zP-hr)|`SEcY^%9mch?
zp12)>_lN#=He)9zfxkZfIyqhYd`kk&4PbS1e^y3Rw}IoILJpbPbo6OGCi!XmC(uK>
zGifz0PkVp2nXYUt?cbNu`wXg_%JtLR<I>)`EKuEutJPk(vXZM$!YW4^7US;M6HH}B
zd!A`Fvaq$ql<9m%+WE>>vmXBPUGoNxlYYqFrr)+oy%}<OWtn-G@_tc1zAYcarvJ$C
z-ErV=%8c*I$Km+jr8uupb$ne0oRf@0tCsVmEVLMRm!~}^X)0UHIChr*bFrr2bY#<2
zN82)=_6#yVWK6#JGFRE+q=n9WC+raWr2VkNPPe6ei^`6-*KGy8+^Buh4llQXS6Hdf
znt9KMd~yEmo{PmOzpA?o$dAwY;84CkuTXVVw~)RJt8eA!N$FXPXQVwRX)0UHn9i@t
zN415lRie*J)zP-hr+upa{xRk!<GNXYG3F}k7H8?)OCaz0#ql@CZ@Y^ZFp&U(w-o4;
zthz&N$v$LIb>k@4Pj44b?!8I!_y+QZY3D0TO{;M}KAfB~qrFKtE%RyntZ-Uw$VG*@
z`5ZV|S(fYaQWcbjwdgaTDyv*KIfjg?>TO%jlQMQK`V6=r?Kw#`ck?}{+CtVUG32G{
zXj|sfc9~tNzg%TmS`Z*WU`pVtsm2>=yXC#z$XoPrZ=?IT%UAt`z;ORWGSQ>yBNph#
z+Q--GaJ^+qLk3l+`*OYEDQ)3QpB2|)$bbvd&R4dUaqMrNQ_|WzowP0UY5S~DsaLx?
zK0{^Da!gj1DP3Nw64S62eFjuzmFp(QkWp2=ZOeI5#;!%50T-k_C#mM9vQ1HKA#0Tw
z@=|rQE%Rx+%&yd5sIqb4EG`HTAV6Rrfo`9)vbF-pJ9gV~LCZ_7wJCl1SE_C{u4QjI
zh>6=2=(DZraJ{<Ea;hIPs5;%3>kUt73upSQxERk!J73vi#&q`Oqj^qANAq;jw#=u^
zs<nEBx#_oP)|jj;Yj=66N=(C24CR}k&w!`j3{8$9qpEt_mh+^HU5e+VJtwJ3PGzg{
zWf@UzA#0Tw@=|rQE%Rx+%&yd5uCgpG2oShofqtL8?UZ)YZ|Yq{uD7yXI3%4E$oX!E
z*ePw!HP;!lm0c#4GusZaPugyWoo-7xQ&~Sg^_184NhNKIF{HOT-IwbPPiYHh`mDGX
zLk3)scD}N;jAMWEoRZe&>7;F$PupjO=8>jL>uKG5y&4mhb>pP*^|Vw!Hf?wr2Uca3
zNllI+D?NS}hQEH=@-QhqYtd)G4^R7$q?)_=$nkg!<65PPA*DR-SlU~Yw#)2Fy%~}b
ztMRyiQ)R1@rU%@moVSmi(&jHYUuV2<W!*lz+$n8-imo%Rx3cT>`k1TAZ)HJ%z-<fc
z^gDf@wB6Odmy4D4DLZ24XRI`=#gGBj;ksO(SExFwr=Eo~eO6qHAp@$_%k_q|^Fy-W
zYE)auT8ZZAq-~i`+h>JJz1me0Zi>muGPBD|Rbm<zqm<KUKvh<`ZgLD6Rn^<JoF`@M
zVmu@5IZ0J=DqD@NjHtGdwMq<msXE%0`LtbTSL!cUS(d&a`jqqbu~XV#z5Px%X1w0Y
zHg3Q$0t7A-=q{V~+*v!N%{}ir<9aK*POl$lRmY>?TW@}!w8L9(b927M%K9u*9j?=`
z808>5WI%PgFV`EM(iYD2S#dF*k#@ea#f<69)aE%Q9nI58+cKZF&kB`#g}LcFc($^v
z-Q}e!F%4_cXFyd}xo&npWYpt&m;Q-l#;!%50Y5zLLS<_i$NtA#7}qMTLwX)}EbXl-
z`SGOJs4RsE0t5&UAV7cs0Rlfxfj--=&fi-ch776>>g9UFQ(FBb^=4`3E6YAsqj_-4
zjOv*%J84_y)Aku(ZNI|Y^w^puCM!!vmzS!<G^|CR0aaP$y2&wQR8?==a-Nj2Ytd)G
z1!>Pos=29bQ&d~XS|x_OR2^;0eA+IvEA^MFEK3Ul1PBoL(FlBT!#lm@z1{HJW@`lY
z7U)wzb-3PA(U3va>AqZVcuHG1(`UuC7&733wDXm%WgPpP=ajTIPbY25eA+%MRO;2P
zj?YjTv>cO_WlEQqs>C#`MV|pxS>?LPF=SL#Z`*R7l(B2kXTSw%&q=DescchJTgX}^
zhP+fAZOeSxF0(83m#ZvG3jzcP5ZG0qxdE(J^ABZ2dm1Q>&HbUvT90laUrgM}Pm?lq
zF)mNLRM}$6(%JvKygb^%{aU51D<6+Lmi9JeY;_}U)Y~DMvlO$HWztl|ON*7hznEYu
z&3&ew-lQQH%|_amKI1ZJJuXk%XYuLER@46B)8-8v=lqbpwLb%mdOPIe%EpO5E3aRd
zkGo|0#n`m=QvOe@Gw|E;F_f<l$Nw(Hd4;OuyE5Q#N-_?uTF#R)Y&kAZdrs0;ww$u`
zeswr}mqDj3jBAzaZ2G(Maqeha7SdL$HJIbNS$i?&DqEbi(3x-49b%uf{SG_bmhvqs
z>$a8h(xY}tyX~&=(wqGu>-8C2-FH@Jm;WC9kU`b$rCfg~A4B=5JF3IMVg9C)iHq@!
zwDXlMW=!W@`KY##wGz!v+LrmWeO9Q{E6gNZjk_{pva;2g1`r@XfWWH?w0DRt>6*Jj
znbc=u)6u2%lw|3qn{jK=tX?McnbdT2X+5Rwb1^+6J!{crK($u6Zf}K6OP_huX{*(y
zhh*|vbQw^sb(}Heb5+o>WBF6HRLUyR<)!JUP7Mp2%;eQ*RxdNU%xXHSwDUtUcQx9z
z%9Q54Xj{6h{PvY4s~|vtz=XivMBA-2-SXaU<vp?w0t5)WkwA0)-jugJ-5(BpW;PvN
zT2D#pC#mX>Gc#;8n$^pUKC_yRF0H4ueJ-Ylq-QO<45-#B*VQxO_$RncOP_huX{*(y
zhh*|vbQw^sb(}Heb5+o>WBF6HRLUyR<)!JUp7|CwnaQistX^hxnbmYuY3GMz?rOAa
zl_|}8(YAD1`Ryx9RzZLO0RjXFe8d7@eZ;k|m43^6Tid(-Hxg*h->Z3Z+;30!heMy4
zO-Gm3Q<C~g>W4kHJ|k_P8m22t&tjC)y9_vOq0dE$>X~qt$JV*ZQr(c3s>C!b#@2tw
zeL`}^He{>ujI>=Auilr_d%T+U_hm%Bp@#DD;8eaot#IyWTe>oAI_-JV{E*CDjNg~u
z$;uXI=_Ekl;}_WUEA!>Ixlh{sn!C=p-pa1i>&IDDzt6UJN}JQ<b;b)<HXi2Rey97S
z9o~MU8#69f)*Smct=gXM4~IT8n~pB6rz8(g2&a}l-I=s0n$^p!J~Nw+F0D<H%bo|?
zwaVJnGvO|et)+;`%1Zl_$FVqUiUzFA>N2zGs3d<n&!5Sw(X3u(beYw3RB7jjWbSIT
zYn3U@P8Rl-cfC)VW>S~d$>P(o8k3c+&YB*Ozizuj?34D}9d^1c<qKCfY|Hx6qjpNW
z&mDaW-t|_trFvrs5FkL{vA|Bh)Ava`Jl^?LeZ5>+bGY7Advj1Pv--?zI=Zx;lC%$d
zeY!JgQ#7lWS$$?U9bH;aY5QDE4@u8jbQw^sRjzODu{A$7)g}X0qRUIuQ9W7B*k;md
zJR@zF#V0FU%{r73)fT$rl;*o+VQ(qD&%9<*m(~}qEK6PxpI$KM1*Yti_IEE(`Rgok
zy_LPreyvJ?z)@h>M`EY6`<%bG5MOU)TdFtaZ3McvN%J(zPHB&){HN7i!S!Ng&Ea~r
z;5@K32ldj{XJ*sUrS+7gec0>My;xudB%YDB&;04i(z6tO>FhG#w1qwwC3b&o?Mo3|
z`DiLj+mM&4#5Al%waMeV(q&fDQ9bi5{1eI5l#{EM#%{8sN;^L!b62BXt4wLWOBVL_
zDvzxxd$O|C{TM)i009C72oNAZ;ARDy2a-)YZBF-PR-c(oN0-)9lKM%iI`(JSYBZ~t
z8GU9o9bH;aY5QDE4@u8jbQw^sRj#XN!tsysnwCEErqfodO%KWBwdgXSTI)Dt$mgn{
zW5@ERYN?b}qRUIuQ9W5LY%-HqqglPo=rXJ6sM5|4$=uaw*D6z*_o8j-vhv$kmaKvR
z0RjYmECS!$@J4TWZ#Vq5*&2b}1)B5sri$9r{o&AOX4BE7^^~N3lJeNPWEQuz=rZ7h
z+vnmKLq2<KJ!(vU^4L1<qLlyv0t99Ry0lN-b!WyO4u4;cMSXg!<59V;jzH}V>D}R*
z!;pE^t^7PGJxg(U+NH{tGLC(JR$iNeOWTm%M;+fZElX*;%&ycc%&fZ_bCqS{qr&dX
zSY7S#m+#s)Fte7c>@sBPy?%qV^OdEj#kl+R#M@P7v^!~A=F>LneTt~w*)%N1TxH{=
z-;~$y@>Tw88(-&()hPcb)){!0s((>FzCF%3tx$CgKPkQEBpF(_oF*ODSorjew5KF(
zWefT4yY8k6E?w<T+LrmWXOQ_J7gx4Aac01Wnf6z1-YIRqd9O3xpt50~o$r)({D<cI
z?09R|<_54j@vAbTx(ys}@O@@B9bH;aN!nX^pYBXrjc26ov-osnt7*$kq|2bw7W!P2
zXl{>fOP_JmX{*(yhh*|%%v6@8#jOeSx3(esA#mFQ?Hyvve$Rh|aJnmG(uUhb4zokX
zzHQq1%2LZ(3>i=rT&~-lv@P>#tJNCJF=3Lf#gGBjTBjMO_vJj|)Uo)vTIzT#Jg?AY
z>g1N%KgBpt%AD1>Fzt|qo4I{jw?v;ol~cKH-ix+n$h_&a)oRm2GI=ff45-#xo1vco
zfgiO%{v7dE<Cgb!tM8e85g<U|bp)Ej^`<oK>Ap;xe54t&-Z{zqqg{rr#-(ZJD_c!j
z1`HW=-a^(Y(e9*enNM4-*6eB+Gi-Pn2UcsHCRGnT8L=s<rBYUjAumlwpVm{7g-5##
zTa9M*GGoZBrlU{mDeaJp=^^P^i#`LYwaRt#UbHPk=1r%qR+}D@$!pPPK(*G|4E+QM
z5FkK+!1W8<U4MxeS9r^NyBNj9mlbFZ*Q?9-Wkh?rFO3_X(&iuSUN!A}Wvgk6&yYct
zQ@L(;(zeW}tyXI=$An3`7;}}4ld6ZFWLu3d%ZR3|(l%sf)6u8(l%)N37}EXPY0pWz
zWUH{#uoOcnz0ZKt7KU7uXx@vqWyrW?kcA<cycDyQEltu#fWQq1Z2Fb?^84H;ZU6Ec
zd7%}rx3U-7pk-b{AV-cJVxP1*-d<<CaAn;-yWA;l4#3wLi<LF!?@fDXPxob7_25uF
z51f<CKia)&+WE@1q#ZKoyoKX0jdmw(%Y52uwFYxcn51hlWI(mnX-30;>R9|-EtRrL
z40&lf`m~;sd@;R)OxhI9>SflDnN3HZ)>GOc7t=%1vle{@RBM&%W+w}K>$1QPeUCF|
zE&2?2TG`s9ng0BB+Z|$`w0FlJ&K)+qlJcc1%Xh~Pu}|7=hn;RqdA*fwtKTRB1PBly
zK!CuHO5n>I-t8^#?S|hrTO&Y#009D5D9~SFO)pi_E${86jI2X|z|I2Q&iP+6{Vnh9
zHQlUDfB=Cv6zJbDmsA9vA<$p#zZUe2O&zD+^4^}WV+8^qrN9mU#`-AV4@DCoK;YU0
zh7X5NK704)AM%$^KKtzb-wa*%_|xG}`p-VR|J!5Z;ZF{Kdu%y>I;1~Wn|9U@AG+i_
zrY)Zihmzqw?P-PKRKz*SSj6dS9Cn|wWZn|zl!s)_RhiZ9q_jNj=D4Z*Paob7=f3f;
zcx=hK>zKbgl#;vmc~{>3_VCO8lMjzSmH%kQCx>^Z#&XpkTh5=}rGLEIu#L~Uf|7iP
z`?U8&pWLS{3w4JNeUW{X@4WgkN%=HJQvNoXH^njKpC<EIK$+F-BrT`ij7uLggy5IQ
zzJEOq*_6|uqre|`|LE@hAAhsY-{{!%E__mc05%PL)}SvApC5jGUf~aicZcr<0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1YSwtA0K}6^TRRz
z>UW33yTkC+;qd3(=ZE3LslEODN&oGCKTo^w{&4uW`Qo#@ywA(ueg5g;XZd3IA7$O{
zpa1Icn_M0K^xu>mr>1dKnucGNu5UgmFJHVXFPS(tjT6g7Ss^c3{$bRZ@x0bJv2GeN
zrz;=#Yo)HCd>nrIf4={t;oblH{wLoI-+zDj;=Awv)yAfYQqN7}w#Vh`BF=R^6mf1E
zB_1}^rMPUUZhC@qUjAWJnw~7bZI8+Lu>AOTr0Gc!_3}doOf27}{rnCMxtfiM@1S2D
z4*z)^|6l*x;V#R3mG|rOH2tJ}+~te%y*b%5PW)%3?_uKDG=2}~yJ}pkFJBxcMjcKW
z4<G)?&+m(v7?ri2EPozVer}G{pPR;vb9F6^s*5<Bt3PjOqKJo4pJ$IhNvZi_^tz~s
zY^cu?OQrsRJsy7hpWZL7H4;u#e-%w<!bATbzC4WY&=8@yc;9{f??0_Oe_nn+<ab~7
z1M<H8G1}OaAIXQc@(X2ZVpj$|{CJO}>WM=c@P2F>e~;!T?mVjgh4Q{DeGg6fRWVMy
zZ_4lYxry8McwYXS(_P?U`MPP`_W0X&%$SJ}zpsXJ@lfhGacnx<k9U;w#0Q*lR3sjn
z&Kr6HefFyBdcc`jzV;d?j!k1-)vx@q`f)?&J(j9wV*2-JpV8;vefK|E|LgmIdicrz
z{r+cnhws0C_to9^e|7l$1)C-^zJ1fh8ybH(t$JO&q5o3ejYn_Chky4U4|UVm8PMlt
zwTNwdoLFmH)A)<-Ttt4q|BFL@9{;F({LAsH!{O`lzx)>aO}S$yJ{!MJ|M&m={~kQA
ACjbBd

literal 0
HcmV?d00001

diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.bsf b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.bsf
new file mode 100644
index 0000000..87ff5c1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.bsf
@@ -0,0 +1,200 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 384 496)
+	(text "cali_ram" (rect 167 -1 201 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 480 20 492)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "cali_ram_clk1_clk" (rect 0 0 70 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_clk1_clk" (rect 4 61 106 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 160 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "cali_ram_clk2_clk" (rect 0 0 71 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_clk2_clk" (rect 4 101 106 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 160 112)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "cali_ram_reset1_reset" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_reset1_reset" (rect 4 141 130 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 160 152)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "cali_ram_reset2_reset" (rect 0 0 90 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_reset2_reset" (rect 4 181 130 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 160 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "cali_ram_s1_address[8..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_address[8..0]" (rect 4 221 154 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 160 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "cali_ram_s1_clken" (rect 0 0 74 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_clken" (rect 4 237 106 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 160 248)(line_width 1))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "cali_ram_s1_chipselect" (rect 0 0 92 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_chipselect" (rect 4 253 136 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 160 264)(line_width 1))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "cali_ram_s1_write" (rect 0 0 71 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_write" (rect 4 269 106 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 160 280)(line_width 1))
+	)
+	(port
+		(pt 0 312)
+		(input)
+		(text "cali_ram_s1_writedata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_writedata[15..0]" (rect 4 301 172 312)(font "Arial" (font_size 8)))
+		(line (pt 0 312)(pt 160 312)(line_width 3))
+	)
+	(port
+		(pt 0 328)
+		(input)
+		(text "cali_ram_s1_byteenable[1..0]" (rect 0 0 115 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_byteenable[1..0]" (rect 4 317 172 328)(font "Arial" (font_size 8)))
+		(line (pt 0 328)(pt 160 328)(line_width 3))
+	)
+	(port
+		(pt 0 368)
+		(input)
+		(text "cali_ram_s2_address[8..0]" (rect 0 0 107 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_address[8..0]" (rect 4 357 154 368)(font "Arial" (font_size 8)))
+		(line (pt 0 368)(pt 160 368)(line_width 3))
+	)
+	(port
+		(pt 0 384)
+		(input)
+		(text "cali_ram_s2_chipselect" (rect 0 0 93 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_chipselect" (rect 4 373 136 384)(font "Arial" (font_size 8)))
+		(line (pt 0 384)(pt 160 384)(line_width 1))
+	)
+	(port
+		(pt 0 400)
+		(input)
+		(text "cali_ram_s2_clken" (rect 0 0 75 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_clken" (rect 4 389 106 400)(font "Arial" (font_size 8)))
+		(line (pt 0 400)(pt 160 400)(line_width 1))
+	)
+	(port
+		(pt 0 416)
+		(input)
+		(text "cali_ram_s2_write" (rect 0 0 73 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_write" (rect 4 405 106 416)(font "Arial" (font_size 8)))
+		(line (pt 0 416)(pt 160 416)(line_width 1))
+	)
+	(port
+		(pt 0 448)
+		(input)
+		(text "cali_ram_s2_writedata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_writedata[15..0]" (rect 4 437 172 448)(font "Arial" (font_size 8)))
+		(line (pt 0 448)(pt 160 448)(line_width 3))
+	)
+	(port
+		(pt 0 464)
+		(input)
+		(text "cali_ram_s2_byteenable[1..0]" (rect 0 0 116 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_byteenable[1..0]" (rect 4 453 172 464)(font "Arial" (font_size 8)))
+		(line (pt 0 464)(pt 160 464)(line_width 3))
+	)
+	(port
+		(pt 0 296)
+		(output)
+		(text "cali_ram_s1_readdata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s1_readdata[15..0]" (rect 4 285 166 296)(font "Arial" (font_size 8)))
+		(line (pt 0 296)(pt 160 296)(line_width 3))
+	)
+	(port
+		(pt 0 432)
+		(output)
+		(text "cali_ram_s2_readdata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "cali_ram_s2_readdata[15..0]" (rect 4 421 166 432)(font "Arial" (font_size 8)))
+		(line (pt 0 432)(pt 160 432)(line_width 3))
+	)
+	(drawing
+		(text "cali_ram_clk1" (rect 82 43 242 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_clk2" (rect 80 83 238 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 107 348 224)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_reset1" (rect 68 123 226 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 147 360 304)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_reset2" (rect 66 163 222 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 187 360 384)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_s1" (rect 91 203 248 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 165 227 372 464)(font "Arial" (color 0 0 0)))
+		(text "clken" (rect 165 243 360 496)(font "Arial" (color 0 0 0)))
+		(text "chipselect" (rect 165 259 390 528)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 165 275 360 560)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 165 291 378 592)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 165 307 384 624)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 165 323 390 656)(font "Arial" (color 0 0 0)))
+		(text "cali_ram_s2" (rect 89 339 244 691)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 165 363 372 736)(font "Arial" (color 0 0 0)))
+		(text "chipselect" (rect 165 379 390 768)(font "Arial" (color 0 0 0)))
+		(text "clken" (rect 165 395 360 800)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 165 411 360 832)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 165 427 378 864)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 165 443 384 896)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 165 459 390 928)(font "Arial" (color 0 0 0)))
+		(text " cali_ram " (rect 344 480 748 970)(font "Arial" ))
+		(line (pt 160 32)(pt 224 32)(line_width 1))
+		(line (pt 224 32)(pt 224 480)(line_width 1))
+		(line (pt 160 480)(pt 224 480)(line_width 1))
+		(line (pt 160 32)(pt 160 480)(line_width 1))
+		(line (pt 161 52)(pt 161 76)(line_width 1))
+		(line (pt 162 52)(pt 162 76)(line_width 1))
+		(line (pt 161 92)(pt 161 116)(line_width 1))
+		(line (pt 162 92)(pt 162 116)(line_width 1))
+		(line (pt 161 132)(pt 161 156)(line_width 1))
+		(line (pt 162 132)(pt 162 156)(line_width 1))
+		(line (pt 161 172)(pt 161 196)(line_width 1))
+		(line (pt 162 172)(pt 162 196)(line_width 1))
+		(line (pt 161 212)(pt 161 332)(line_width 1))
+		(line (pt 162 212)(pt 162 332)(line_width 1))
+		(line (pt 161 348)(pt 161 468)(line_width 1))
+		(line (pt 162 348)(pt 162 468)(line_width 1))
+		(line (pt 0 0)(pt 384 0)(line_width 1))
+		(line (pt 384 0)(pt 384 496)(line_width 1))
+		(line (pt 0 496)(pt 384 496)(line_width 1))
+		(line (pt 0 0)(pt 0 496)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.xml b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.xml
new file mode 100644
index 0000000..59707a1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram.xml
@@ -0,0 +1,343 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.02.15:49:43"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK1_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_CALI_RAM_CLK2_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="cali_ram_clk1" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="cali_ram_clk1_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="cali_ram_clk2" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="cali_ram_clk2_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="cali_ram_reset1" kind="reset" start="0">
+   <property name="associatedClock" value="cali_ram_clk1" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port name="cali_ram_reset1_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="cali_ram_reset2" kind="reset" start="0">
+   <property name="associatedClock" value="cali_ram_clk2" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port name="cali_ram_reset2_reset" direction="input" role="reset" width="1" />
+  </interface>
+  <interface name="cali_ram_s1" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="1" />
+   <property name="addressSpan" value="640" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="cali_ram_clk1" />
+   <property name="associatedReset" value="cali_ram_reset1" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="640" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="true" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="1" />
+   <property name="readWaitStates" value="0" />
+   <property name="readWaitTime" value="0" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port name="cali_ram_s1_address" direction="input" role="address" width="9" />
+   <port name="cali_ram_s1_clken" direction="input" role="clken" width="1" />
+   <port
+       name="cali_ram_s1_chipselect"
+       direction="input"
+       role="chipselect"
+       width="1" />
+   <port name="cali_ram_s1_write" direction="input" role="write" width="1" />
+   <port
+       name="cali_ram_s1_readdata"
+       direction="output"
+       role="readdata"
+       width="16" />
+   <port
+       name="cali_ram_s1_writedata"
+       direction="input"
+       role="writedata"
+       width="16" />
+   <port
+       name="cali_ram_s1_byteenable"
+       direction="input"
+       role="byteenable"
+       width="2" />
+  </interface>
+  <interface name="cali_ram_s2" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="1" />
+   <property name="addressSpan" value="640" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="cali_ram_clk2" />
+   <property name="associatedReset" value="cali_ram_reset2" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="640" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="true" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="1" />
+   <property name="readWaitStates" value="0" />
+   <property name="readWaitTime" value="0" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port name="cali_ram_s2_address" direction="input" role="address" width="9" />
+   <port
+       name="cali_ram_s2_chipselect"
+       direction="input"
+       role="chipselect"
+       width="1" />
+   <port name="cali_ram_s2_clken" direction="input" role="clken" width="1" />
+   <port name="cali_ram_s2_write" direction="input" role="write" width="1" />
+   <port
+       name="cali_ram_s2_readdata"
+       direction="output"
+       role="readdata"
+       width="16" />
+   <port
+       name="cali_ram_s2_writedata"
+       direction="input"
+       role="writedata"
+       width="16" />
+   <port
+       name="cali_ram_s2_byteenable"
+       direction="input"
+       role="byteenable"
+       width="2" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="cali_ram:1.0:AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN=-1,AUTO_CALI_RAM_CLK1_CLOCK_RATE=-1,AUTO_CALI_RAM_CLK1_RESET_DOMAIN=-1,AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN=-1,AUTO_CALI_RAM_CLK2_CLOCK_RATE=-1,AUTO_CALI_RAM_CLK2_RESET_DOMAIN=-1,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1719928182,AUTO_UNIQUE_ID=(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=cali_ram_cali_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=cali_ram_cali_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)"
+   instancePathKey="cali_ram"
+   kind="cali_ram"
+   version="1.0"
+   name="cali_ram">
+  <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1719928182" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_CALI_RAM_CLK1_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK1_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK2_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_CALI_RAM_CLK2_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/cali_ram.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/cali_ram.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:cali_ram "cali_ram"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/cali_ram_cali_ram</b>"]]></message>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram"</message>
+   <message level="Info" culprit="cali_ram">Starting RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cali_ram">Done RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>cali_ram</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=cali_ram_cali_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=cali_ram_cali_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
+   instancePathKey="cali_ram:.:cali_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   name="cali_ram_cali_ram">
+  <parameter name="derived_singleClockOperation" value="false" />
+  <parameter name="derived_is_hardcopy" value="false" />
+  <parameter
+     name="deviceFeatures"
+     value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
+  <parameter name="autoInitializationFileName" value="cali_ram_cali_ram" />
+  <parameter name="derived_gui_ram_block_type" value="Automatic" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="dualPort" value="true" />
+  <parameter name="derived_set_addr_width2" value="9" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="derived_set_addr_width" value="9" />
+  <parameter name="derived_init_file_name" value="cali_ram_cali_ram.hex" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="derived_set_data_width2" value="16" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="derived_enableDiffWidth" value="false" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="resetrequest_enabled" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="derived_set_data_width" value="16" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="640" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="cali_ram" as="cali_ram" />
+  <messages>
+   <message level="Debug" culprit="cali_ram">queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram"</message>
+   <message level="Info" culprit="cali_ram">Starting RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram">  Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl  --do_build_sim=0  ]</message>
+   <message level="Info" culprit="cali_ram">Done RTL generation for module 'cali_ram_cali_ram'</message>
+   <message level="Info" culprit="cali_ram"><![CDATA["<b>cali_ram</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>cali_ram</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_bb.v b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_bb.v
new file mode 100644
index 0000000..bc874bc
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_bb.v
@@ -0,0 +1,40 @@
+
+module cali_ram (
+	cali_ram_s2_address,
+	cali_ram_s2_chipselect,
+	cali_ram_s2_clken,
+	cali_ram_s2_write,
+	cali_ram_s2_readdata,
+	cali_ram_s2_writedata,
+	cali_ram_s2_byteenable,
+	cali_ram_clk2_clk,
+	cali_ram_reset2_reset,
+	cali_ram_reset1_reset,
+	cali_ram_s1_address,
+	cali_ram_s1_clken,
+	cali_ram_s1_chipselect,
+	cali_ram_s1_write,
+	cali_ram_s1_readdata,
+	cali_ram_s1_writedata,
+	cali_ram_s1_byteenable,
+	cali_ram_clk1_clk);	
+
+	input	[8:0]	cali_ram_s2_address;
+	input		cali_ram_s2_chipselect;
+	input		cali_ram_s2_clken;
+	input		cali_ram_s2_write;
+	output	[15:0]	cali_ram_s2_readdata;
+	input	[15:0]	cali_ram_s2_writedata;
+	input	[1:0]	cali_ram_s2_byteenable;
+	input		cali_ram_clk2_clk;
+	input		cali_ram_reset2_reset;
+	input		cali_ram_reset1_reset;
+	input	[8:0]	cali_ram_s1_address;
+	input		cali_ram_s1_clken;
+	input		cali_ram_s1_chipselect;
+	input		cali_ram_s1_write;
+	output	[15:0]	cali_ram_s1_readdata;
+	input	[15:0]	cali_ram_s1_writedata;
+	input	[1:0]	cali_ram_s1_byteenable;
+	input		cali_ram_clk1_clk;
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_inst.v b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_inst.v
new file mode 100644
index 0000000..a82c29e
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/cali_ram_inst.v
@@ -0,0 +1,21 @@
+	cali_ram u0 (
+		.cali_ram_s2_address    (<connected-to-cali_ram_s2_address>),    //     cali_ram_s2.address
+		.cali_ram_s2_chipselect (<connected-to-cali_ram_s2_chipselect>), //                .chipselect
+		.cali_ram_s2_clken      (<connected-to-cali_ram_s2_clken>),      //                .clken
+		.cali_ram_s2_write      (<connected-to-cali_ram_s2_write>),      //                .write
+		.cali_ram_s2_readdata   (<connected-to-cali_ram_s2_readdata>),   //                .readdata
+		.cali_ram_s2_writedata  (<connected-to-cali_ram_s2_writedata>),  //                .writedata
+		.cali_ram_s2_byteenable (<connected-to-cali_ram_s2_byteenable>), //                .byteenable
+		.cali_ram_clk2_clk      (<connected-to-cali_ram_clk2_clk>),      //   cali_ram_clk2.clk
+		.cali_ram_reset2_reset  (<connected-to-cali_ram_reset2_reset>),  // cali_ram_reset2.reset
+		.cali_ram_reset1_reset  (<connected-to-cali_ram_reset1_reset>),  // cali_ram_reset1.reset
+		.cali_ram_s1_address    (<connected-to-cali_ram_s1_address>),    //     cali_ram_s1.address
+		.cali_ram_s1_clken      (<connected-to-cali_ram_s1_clken>),      //                .clken
+		.cali_ram_s1_chipselect (<connected-to-cali_ram_s1_chipselect>), //                .chipselect
+		.cali_ram_s1_write      (<connected-to-cali_ram_s1_write>),      //                .write
+		.cali_ram_s1_readdata   (<connected-to-cali_ram_s1_readdata>),   //                .readdata
+		.cali_ram_s1_writedata  (<connected-to-cali_ram_s1_writedata>),  //                .writedata
+		.cali_ram_s1_byteenable (<connected-to-cali_ram_s1_byteenable>), //                .byteenable
+		.cali_ram_clk1_clk      (<connected-to-cali_ram_clk1_clk>)       //   cali_ram_clk1.clk
+	);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.bsf b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.bsf
new file mode 100644
index 0000000..a9ae241
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.bsf
@@ -0,0 +1,38 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 64)
+	(text "sensor_algo" (rect 13 -1 61 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 48 20 60)(font "Arial" ))
+	(drawing
+		(text " system " (rect 45 48 138 106)(font "Arial" ))
+		(line (pt 16 32)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 80 48)(line_width 1))
+		(line (pt 16 48)(pt 80 48)(line_width 1))
+		(line (pt 16 32)(pt 16 48)(line_width 1))
+		(line (pt 0 0)(pt 97 0)(line_width 1))
+		(line (pt 97 0)(pt 97 64)(line_width 1))
+		(line (pt 0 64)(pt 97 64)(line_width 1))
+		(line (pt 0 0)(pt 0 64)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.xml b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.xml
new file mode 100644
index 0000000..f2d4ad8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.17.13:03:39"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="sensor_algo_0_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="sensor_algo_0_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="sensor_algo_0_rst" kind="reset" start="0">
+   <property name="associatedClock" value="sensor_algo_0_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="sensor_algo_0_rst_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="sensor_algo:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1721214219,AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN=-1,AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE=-1,AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(sensor_algo:1.0:)"
+   instancePathKey="sensor_algo"
+   kind="sensor_algo"
+   version="1.0"
+   name="sensor_algo">
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1721214219" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
+       type="VERILOG" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
+  </childSourceFiles>
+  <instantiator instantiator="sensor_algo" as="sensor_algo_0" />
+  <messages>
+   <message level="Debug" culprit="sensor_algo">queue size: 0 starting:sensor_algo "sensor_algo"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="sensor_algo"><![CDATA["<b>sensor_algo</b>" reuses <b>sensor_algo</b> "<b>sensor_algo</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_bb.v b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_bb.v
new file mode 100644
index 0000000..a5cda4d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_bb.v
@@ -0,0 +1,5 @@
+
+module sensor_algo (
+	);	
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_inst.v b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_inst.v
new file mode 100644
index 0000000..2b9006c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_algo_inst.v
@@ -0,0 +1,3 @@
+	sensor_algo u0 (
+	);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.bsf b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.bsf
new file mode 100644
index 0000000..e1d44a1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.bsf
@@ -0,0 +1,294 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 688 512)
+	(text "sensor_recon" (rect 304 -1 359 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 496 20 508)(font "Arial" ))
+	(port
+		(pt 688 104)
+		(input)
+		(text "sensor_recon_0_calibration_ram_interface_readdata[15..0]" (rect 0 0 236 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_readdata[15..0]" (rect 394 93 730 104)(font "Arial" (font_size 8)))
+		(line (pt 688 104)(pt 384 104)(line_width 3))
+	)
+	(port
+		(pt 688 120)
+		(input)
+		(text "sensor_recon_0_calibration_ram_interface_waitrequest" (rect 0 0 221 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_waitrequest" (rect 407 109 719 120)(font "Arial" (font_size 8)))
+		(line (pt 688 120)(pt 384 120)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "sensor_recon_0_clk_clk" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_clk_clk" (rect 4 61 136 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 240 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "sensor_recon_0_csr_address[1..0]" (rect 0 0 141 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_address[1..0]" (rect 4 101 196 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 240 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "sensor_recon_0_csr_read" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_read" (rect 4 117 142 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 240 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "sensor_recon_0_csr_write" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_write" (rect 4 149 148 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 240 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "sensor_recon_0_csr_writedata[31..0]" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_writedata[31..0]" (rect 4 165 214 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 240 176)(line_width 3))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "sensor_recon_0_csr_byteenable[3..0]" (rect 0 0 153 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_byteenable[3..0]" (rect 4 181 214 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 240 192)(line_width 3))
+	)
+	(port
+		(pt 688 208)
+		(input)
+		(text "sensor_recon_0_data_out_ready" (rect 0 0 135 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_ready" (rect 519 197 693 208)(font "Arial" (font_size 8)))
+		(line (pt 688 208)(pt 384 208)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "sensor_recon_0_rst_reset" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_rst_reset" (rect 4 221 148 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 240 232)(line_width 1))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "sensor_recon_0_sensor_in_adc_data[4..0]" (rect 0 0 174 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_in_adc_data[4..0]" (rect 4 261 238 272)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 240 272)(line_width 3))
+	)
+	(port
+		(pt 0 288)
+		(input)
+		(text "sensor_recon_0_sensor_in_trg" (rect 0 0 127 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_in_trg" (rect 4 277 172 288)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 240 288)(line_width 1))
+	)
+	(port
+		(pt 0 448)
+		(input)
+		(text "sensor_recon_0_synchro_ext_input[7..0]" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_ext_input[7..0]" (rect 4 437 232 448)(font "Arial" (font_size 8)))
+		(line (pt 0 448)(pt 240 448)(line_width 3))
+	)
+	(port
+		(pt 0 464)
+		(input)
+		(text "sensor_recon_0_synchro_serial_rx" (rect 0 0 145 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_serial_rx" (rect 4 453 196 464)(font "Arial" (font_size 8)))
+		(line (pt 0 464)(pt 240 464)(line_width 1))
+	)
+	(port
+		(pt 688 72)
+		(output)
+		(text "sensor_recon_0_calibration_ram_interface_address[8..0]" (rect 0 0 230 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_address[8..0]" (rect 401 61 725 72)(font "Arial" (font_size 8)))
+		(line (pt 688 72)(pt 384 72)(line_width 3))
+	)
+	(port
+		(pt 688 88)
+		(output)
+		(text "sensor_recon_0_calibration_ram_interface_read" (rect 0 0 195 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_read" (rect 443 77 713 88)(font "Arial" (font_size 8)))
+		(line (pt 688 88)(pt 384 88)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(output)
+		(text "sensor_recon_0_csr_readdata[31..0]" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_readdata[31..0]" (rect 4 133 208 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 240 144)(line_width 3))
+	)
+	(port
+		(pt 688 160)
+		(output)
+		(text "sensor_recon_0_data_out_endofpacket" (rect 0 0 160 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_endofpacket" (rect 486 149 696 160)(font "Arial" (font_size 8)))
+		(line (pt 688 160)(pt 384 160)(line_width 1))
+	)
+	(port
+		(pt 688 176)
+		(output)
+		(text "sensor_recon_0_data_out_data[31..0]" (rect 0 0 152 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_data[31..0]" (rect 498 165 708 176)(font "Arial" (font_size 8)))
+		(line (pt 688 176)(pt 384 176)(line_width 3))
+	)
+	(port
+		(pt 688 192)
+		(output)
+		(text "sensor_recon_0_data_out_empty[1..0]" (rect 0 0 156 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_empty[1..0]" (rect 496 181 706 192)(font "Arial" (font_size 8)))
+		(line (pt 688 192)(pt 384 192)(line_width 3))
+	)
+	(port
+		(pt 688 224)
+		(output)
+		(text "sensor_recon_0_data_out_startofpacket" (rect 0 0 164 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_startofpacket" (rect 482 213 704 224)(font "Arial" (font_size 8)))
+		(line (pt 688 224)(pt 384 224)(line_width 1))
+	)
+	(port
+		(pt 688 240)
+		(output)
+		(text "sensor_recon_0_data_out_valid" (rect 0 0 129 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_valid" (rect 525 229 699 240)(font "Arial" (font_size 8)))
+		(line (pt 688 240)(pt 384 240)(line_width 1))
+	)
+	(port
+		(pt 0 304)
+		(output)
+		(text "sensor_recon_0_sensor_out_adc_clk" (rect 0 0 153 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_adc_clk" (rect 4 293 202 304)(font "Arial" (font_size 8)))
+		(line (pt 0 304)(pt 240 304)(line_width 1))
+	)
+	(port
+		(pt 0 320)
+		(output)
+		(text "sensor_recon_0_sensor_out_adc_cnv" (rect 0 0 158 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_adc_cnv" (rect 4 309 202 320)(font "Arial" (font_size 8)))
+		(line (pt 0 320)(pt 240 320)(line_width 1))
+	)
+	(port
+		(pt 0 336)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_clk" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_clk" (rect 4 325 220 336)(font "Arial" (font_size 8)))
+		(line (pt 0 336)(pt 240 336)(line_width 1))
+	)
+	(port
+		(pt 0 352)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_gain" (rect 0 0 171 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_gain" (rect 4 341 226 352)(font "Arial" (font_size 8)))
+		(line (pt 0 352)(pt 240 352)(line_width 1))
+	)
+	(port
+		(pt 0 368)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_rst" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_rst" (rect 4 357 220 368)(font "Arial" (font_size 8)))
+		(line (pt 0 368)(pt 240 368)(line_width 1))
+	)
+	(port
+		(pt 0 408)
+		(output)
+		(text "sensor_recon_0_status_out_status_out[7..0]" (rect 0 0 180 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_status_out_status_out[7..0]" (rect 4 397 256 408)(font "Arial" (font_size 8)))
+		(line (pt 0 408)(pt 240 408)(line_width 3))
+	)
+	(port
+		(pt 0 480)
+		(output)
+		(text "sensor_recon_0_synchro_serial_tx" (rect 0 0 143 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_serial_tx" (rect 4 469 196 480)(font "Arial" (font_size 8)))
+		(line (pt 0 480)(pt 240 480)(line_width 1))
+	)
+	(drawing
+		(text "sensor_recon_0_calibration_ram_interface" (rect 385 43 1010 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 347 67 736 144)(font "Arial" (color 0 0 0)))
+		(text "read" (rect 362 83 748 176)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 344 99 736 208)(font "Arial" (color 0 0 0)))
+		(text "waitrequest" (rect 333 115 732 240)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_clk" (rect 122 43 352 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 245 67 508 144)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_csr" (rect 120 83 348 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 245 107 532 224)(font "Arial" (color 0 0 0)))
+		(text "read" (rect 245 123 514 256)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 245 139 538 288)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 245 155 520 320)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 245 171 544 352)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 245 187 550 384)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_data_out" (rect 385 131 908 275)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "endofpacket" (rect 329 155 724 320)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 363 171 750 352)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 354 187 738 384)(font "Arial" (color 0 0 0)))
+		(text "ready" (rect 356 203 742 416)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 324 219 726 448)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 361 235 752 480)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_rst" (rect 122 203 352 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 245 227 520 464)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_sensor" (rect 98 243 322 499)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "in_adc_data" (rect 245 267 556 544)(font "Arial" (color 0 0 0)))
+		(text "in_trg" (rect 245 283 526 576)(font "Arial" (color 0 0 0)))
+		(text "out_adc_clk" (rect 245 299 556 608)(font "Arial" (color 0 0 0)))
+		(text "out_adc_cnv" (rect 245 315 556 640)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_clk" (rect 245 331 574 672)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_gain" (rect 245 347 580 704)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_rst" (rect 245 363 574 736)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_status_out" (rect 76 379 302 771)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "status_out" (rect 245 403 550 816)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_synchro" (rect 93 419 318 851)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ext_input" (rect 245 443 544 896)(font "Arial" (color 0 0 0)))
+		(text "serial_rx" (rect 245 459 544 928)(font "Arial" (color 0 0 0)))
+		(text "serial_tx" (rect 245 475 544 960)(font "Arial" (color 0 0 0)))
+		(text " sensor_recon " (rect 626 496 1336 1002)(font "Arial" ))
+		(line (pt 240 32)(pt 384 32)(line_width 1))
+		(line (pt 384 32)(pt 384 496)(line_width 1))
+		(line (pt 240 496)(pt 384 496)(line_width 1))
+		(line (pt 240 32)(pt 240 496)(line_width 1))
+		(line (pt 383 52)(pt 383 124)(line_width 1))
+		(line (pt 382 52)(pt 382 124)(line_width 1))
+		(line (pt 241 52)(pt 241 76)(line_width 1))
+		(line (pt 242 52)(pt 242 76)(line_width 1))
+		(line (pt 241 92)(pt 241 196)(line_width 1))
+		(line (pt 242 92)(pt 242 196)(line_width 1))
+		(line (pt 383 140)(pt 383 244)(line_width 1))
+		(line (pt 382 140)(pt 382 244)(line_width 1))
+		(line (pt 241 212)(pt 241 236)(line_width 1))
+		(line (pt 242 212)(pt 242 236)(line_width 1))
+		(line (pt 241 252)(pt 241 372)(line_width 1))
+		(line (pt 242 252)(pt 242 372)(line_width 1))
+		(line (pt 241 388)(pt 241 412)(line_width 1))
+		(line (pt 242 388)(pt 242 412)(line_width 1))
+		(line (pt 241 428)(pt 241 484)(line_width 1))
+		(line (pt 242 428)(pt 242 484)(line_width 1))
+		(line (pt 0 0)(pt 688 0)(line_width 1))
+		(line (pt 688 0)(pt 688 512)(line_width 1))
+		(line (pt 0 512)(pt 688 512)(line_width 1))
+		(line (pt 0 0)(pt 0 512)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.xml b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.xml
new file mode 100644
index 0000000..599a86c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon.xml
@@ -0,0 +1,529 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.18.17:04:57"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP"
+     type="AddressMap"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH"
+     type="AddressWidthType"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface
+     name="sensor_recon_0_calibration_ram_interface"
+     kind="avalon"
+     start="1">
+   <property name="adaptsTo" value="" />
+   <property name="addressGroup" value="0" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="dBSBigEndian" value="false" />
+   <property name="doStreamReads" value="false" />
+   <property name="doStreamWrites" value="false" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isAsynchronous" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isReadable" value="false" />
+   <property name="isWriteable" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maxAddressWidth" value="32" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="readLatency" value="0" />
+   <property name="readWaitTime" value="1" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="writeWaitTime" value="0" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_address"
+       direction="output"
+       role="address"
+       width="9" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_read"
+       direction="output"
+       role="read"
+       width="1" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_readdata"
+       direction="input"
+       role="readdata"
+       width="16" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_waitrequest"
+       direction="input"
+       role="waitrequest"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="sensor_recon_0_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="sensor_recon_0_csr" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="0" />
+   <property name="addressSpan" value="16" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="0" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="false" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="0" />
+   <property name="readWaitStates" value="1" />
+   <property name="readWaitTime" value="1" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port
+       name="sensor_recon_0_csr_address"
+       direction="input"
+       role="address"
+       width="2" />
+   <port
+       name="sensor_recon_0_csr_read"
+       direction="input"
+       role="read"
+       width="1" />
+   <port
+       name="sensor_recon_0_csr_readdata"
+       direction="output"
+       role="readdata"
+       width="32" />
+   <port
+       name="sensor_recon_0_csr_write"
+       direction="input"
+       role="write"
+       width="1" />
+   <port
+       name="sensor_recon_0_csr_writedata"
+       direction="input"
+       role="writedata"
+       width="32" />
+   <port
+       name="sensor_recon_0_csr_byteenable"
+       direction="input"
+       role="byteenable"
+       width="4" />
+  </interface>
+  <interface name="sensor_recon_0_data_out" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="1" />
+   <port
+       name="sensor_recon_0_data_out_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_data"
+       direction="output"
+       role="data"
+       width="32" />
+   <port
+       name="sensor_recon_0_data_out_empty"
+       direction="output"
+       role="empty"
+       width="2" />
+   <port
+       name="sensor_recon_0_data_out_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_rst" kind="reset" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="sensor_recon_0_rst_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_sensor" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_sensor_in_adc_data"
+       direction="input"
+       role="in_adc_data"
+       width="5" />
+   <port
+       name="sensor_recon_0_sensor_in_trg"
+       direction="input"
+       role="in_trg"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_adc_clk"
+       direction="output"
+       role="out_adc_clk"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_adc_cnv"
+       direction="output"
+       role="out_adc_cnv"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_clk"
+       direction="output"
+       role="out_sensor_clk"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_gain"
+       direction="output"
+       role="out_sensor_gain"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_rst"
+       direction="output"
+       role="out_sensor_rst"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_status_out" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_status_out_status_out"
+       direction="output"
+       role="status_out"
+       width="8" />
+  </interface>
+  <interface name="sensor_recon_0_synchro" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_synchro_ext_input"
+       direction="input"
+       role="ext_input"
+       width="8" />
+   <port
+       name="sensor_recon_0_synchro_serial_rx"
+       direction="input"
+       role="serial_rx"
+       width="1" />
+   <port
+       name="sensor_recon_0_synchro_serial_tx"
+       direction="output"
+       role="serial_tx"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="sensor_recon:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1721315097,AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP=,AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH=AddressWidth = -1,AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN=-1,AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE=-1,AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(sensor_recon:1:)"
+   instancePathKey="sensor_recon"
+   kind="sensor_recon"
+   version="1.0"
+   name="sensor_recon">
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP"
+     value="" />
+  <parameter name="AUTO_GENERATION_ID" value="1721315097" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_recon.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/div.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_recon.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_recon_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="sensor_recon">queue size: 0 starting:sensor_recon "sensor_recon"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="sensor_recon"><![CDATA["<b>sensor_recon</b>" reuses <b>sensor_recon</b> "<b>submodules/sensor_algo</b>"]]></message>
+   <message level="Debug" culprit="sensor_recon">queue size: 0 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_recon_0"><![CDATA["<b>sensor_recon</b>" instantiated <b>sensor_recon</b> "<b>sensor_recon_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="sensor_recon:1:"
+   instancePathKey="sensor_recon:.:sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   name="sensor_algo">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/div.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.qip"
+       type="OTHER"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_recon_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="sensor_recon" as="sensor_recon_0" />
+  <messages>
+   <message level="Debug" culprit="sensor_recon">queue size: 0 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_recon_0"><![CDATA["<b>sensor_recon</b>" instantiated <b>sensor_recon</b> "<b>sensor_recon_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_bb.v b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_bb.v
new file mode 100644
index 0000000..bb59ac4
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_bb.v
@@ -0,0 +1,62 @@
+
+module sensor_recon (
+	sensor_recon_0_csr_address,
+	sensor_recon_0_csr_read,
+	sensor_recon_0_csr_readdata,
+	sensor_recon_0_csr_write,
+	sensor_recon_0_csr_writedata,
+	sensor_recon_0_csr_byteenable,
+	sensor_recon_0_data_out_endofpacket,
+	sensor_recon_0_data_out_data,
+	sensor_recon_0_data_out_empty,
+	sensor_recon_0_data_out_ready,
+	sensor_recon_0_data_out_startofpacket,
+	sensor_recon_0_data_out_valid,
+	sensor_recon_0_clk_clk,
+	sensor_recon_0_rst_reset,
+	sensor_recon_0_sensor_in_adc_data,
+	sensor_recon_0_sensor_in_trg,
+	sensor_recon_0_sensor_out_adc_clk,
+	sensor_recon_0_sensor_out_adc_cnv,
+	sensor_recon_0_sensor_out_sensor_clk,
+	sensor_recon_0_sensor_out_sensor_gain,
+	sensor_recon_0_sensor_out_sensor_rst,
+	sensor_recon_0_status_out_status_out,
+	sensor_recon_0_synchro_ext_input,
+	sensor_recon_0_synchro_serial_rx,
+	sensor_recon_0_synchro_serial_tx,
+	sensor_recon_0_calibration_ram_interface_address,
+	sensor_recon_0_calibration_ram_interface_read,
+	sensor_recon_0_calibration_ram_interface_readdata,
+	sensor_recon_0_calibration_ram_interface_waitrequest);	
+
+	input	[1:0]	sensor_recon_0_csr_address;
+	input		sensor_recon_0_csr_read;
+	output	[31:0]	sensor_recon_0_csr_readdata;
+	input		sensor_recon_0_csr_write;
+	input	[31:0]	sensor_recon_0_csr_writedata;
+	input	[3:0]	sensor_recon_0_csr_byteenable;
+	output		sensor_recon_0_data_out_endofpacket;
+	output	[31:0]	sensor_recon_0_data_out_data;
+	output	[1:0]	sensor_recon_0_data_out_empty;
+	input		sensor_recon_0_data_out_ready;
+	output		sensor_recon_0_data_out_startofpacket;
+	output		sensor_recon_0_data_out_valid;
+	input		sensor_recon_0_clk_clk;
+	input		sensor_recon_0_rst_reset;
+	input	[4:0]	sensor_recon_0_sensor_in_adc_data;
+	input		sensor_recon_0_sensor_in_trg;
+	output		sensor_recon_0_sensor_out_adc_clk;
+	output		sensor_recon_0_sensor_out_adc_cnv;
+	output		sensor_recon_0_sensor_out_sensor_clk;
+	output		sensor_recon_0_sensor_out_sensor_gain;
+	output		sensor_recon_0_sensor_out_sensor_rst;
+	output	[7:0]	sensor_recon_0_status_out_status_out;
+	input	[7:0]	sensor_recon_0_synchro_ext_input;
+	input		sensor_recon_0_synchro_serial_rx;
+	output		sensor_recon_0_synchro_serial_tx;
+	output	[8:0]	sensor_recon_0_calibration_ram_interface_address;
+	output		sensor_recon_0_calibration_ram_interface_read;
+	input	[15:0]	sensor_recon_0_calibration_ram_interface_readdata;
+	input		sensor_recon_0_calibration_ram_interface_waitrequest;
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_inst.v b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_inst.v
new file mode 100644
index 0000000..900767b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/sensor_recon_inst.v
@@ -0,0 +1,32 @@
+	sensor_recon u0 (
+		.sensor_recon_0_csr_address                           (<connected-to-sensor_recon_0_csr_address>),                           //                       sensor_recon_0_csr.address
+		.sensor_recon_0_csr_read                              (<connected-to-sensor_recon_0_csr_read>),                              //                                         .read
+		.sensor_recon_0_csr_readdata                          (<connected-to-sensor_recon_0_csr_readdata>),                          //                                         .readdata
+		.sensor_recon_0_csr_write                             (<connected-to-sensor_recon_0_csr_write>),                             //                                         .write
+		.sensor_recon_0_csr_writedata                         (<connected-to-sensor_recon_0_csr_writedata>),                         //                                         .writedata
+		.sensor_recon_0_csr_byteenable                        (<connected-to-sensor_recon_0_csr_byteenable>),                        //                                         .byteenable
+		.sensor_recon_0_data_out_endofpacket                  (<connected-to-sensor_recon_0_data_out_endofpacket>),                  //                  sensor_recon_0_data_out.endofpacket
+		.sensor_recon_0_data_out_data                         (<connected-to-sensor_recon_0_data_out_data>),                         //                                         .data
+		.sensor_recon_0_data_out_empty                        (<connected-to-sensor_recon_0_data_out_empty>),                        //                                         .empty
+		.sensor_recon_0_data_out_ready                        (<connected-to-sensor_recon_0_data_out_ready>),                        //                                         .ready
+		.sensor_recon_0_data_out_startofpacket                (<connected-to-sensor_recon_0_data_out_startofpacket>),                //                                         .startofpacket
+		.sensor_recon_0_data_out_valid                        (<connected-to-sensor_recon_0_data_out_valid>),                        //                                         .valid
+		.sensor_recon_0_clk_clk                               (<connected-to-sensor_recon_0_clk_clk>),                               //                       sensor_recon_0_clk.clk
+		.sensor_recon_0_rst_reset                             (<connected-to-sensor_recon_0_rst_reset>),                             //                       sensor_recon_0_rst.reset
+		.sensor_recon_0_sensor_in_adc_data                    (<connected-to-sensor_recon_0_sensor_in_adc_data>),                    //                    sensor_recon_0_sensor.in_adc_data
+		.sensor_recon_0_sensor_in_trg                         (<connected-to-sensor_recon_0_sensor_in_trg>),                         //                                         .in_trg
+		.sensor_recon_0_sensor_out_adc_clk                    (<connected-to-sensor_recon_0_sensor_out_adc_clk>),                    //                                         .out_adc_clk
+		.sensor_recon_0_sensor_out_adc_cnv                    (<connected-to-sensor_recon_0_sensor_out_adc_cnv>),                    //                                         .out_adc_cnv
+		.sensor_recon_0_sensor_out_sensor_clk                 (<connected-to-sensor_recon_0_sensor_out_sensor_clk>),                 //                                         .out_sensor_clk
+		.sensor_recon_0_sensor_out_sensor_gain                (<connected-to-sensor_recon_0_sensor_out_sensor_gain>),                //                                         .out_sensor_gain
+		.sensor_recon_0_sensor_out_sensor_rst                 (<connected-to-sensor_recon_0_sensor_out_sensor_rst>),                 //                                         .out_sensor_rst
+		.sensor_recon_0_status_out_status_out                 (<connected-to-sensor_recon_0_status_out_status_out>),                 //                sensor_recon_0_status_out.status_out
+		.sensor_recon_0_synchro_ext_input                     (<connected-to-sensor_recon_0_synchro_ext_input>),                     //                   sensor_recon_0_synchro.ext_input
+		.sensor_recon_0_synchro_serial_rx                     (<connected-to-sensor_recon_0_synchro_serial_rx>),                     //                                         .serial_rx
+		.sensor_recon_0_synchro_serial_tx                     (<connected-to-sensor_recon_0_synchro_serial_tx>),                     //                                         .serial_tx
+		.sensor_recon_0_calibration_ram_interface_address     (<connected-to-sensor_recon_0_calibration_ram_interface_address>),     // sensor_recon_0_calibration_ram_interface.address
+		.sensor_recon_0_calibration_ram_interface_read        (<connected-to-sensor_recon_0_calibration_ram_interface_read>),        //                                         .read
+		.sensor_recon_0_calibration_ram_interface_readdata    (<connected-to-sensor_recon_0_calibration_ram_interface_readdata>),    //                                         .readdata
+		.sensor_recon_0_calibration_ram_interface_waitrequest (<connected-to-sensor_recon_0_calibration_ram_interface_waitrequest>)  //                                         .waitrequest
+	);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.bsf b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.bsf
new file mode 100644
index 0000000..e56f5bb
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.bsf
@@ -0,0 +1,213 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 480 304)
+	(text "st_splitter16" (rect 205 -1 251 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 288 20 300)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "st_splitter16_clk_clk" (rect 0 0 79 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_clk_clk" (rect 4 61 130 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 160 72)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "st_splitter16_in_valid" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_valid" (rect 4 117 136 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 160 128)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "st_splitter16_in_startofpacket" (rect 0 0 115 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_startofpacket" (rect 4 133 184 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 160 144)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "st_splitter16_in_endofpacket" (rect 0 0 112 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_endofpacket" (rect 4 149 172 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 160 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "st_splitter16_in_empty" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_empty" (rect 4 165 136 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 160 176)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "st_splitter16_in_data[15..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_data[15..0]" (rect 4 181 172 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 160 192)(line_width 3))
+	)
+	(port
+		(pt 480 72)
+		(input)
+		(text "st_splitter16_out0_ready" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_ready" (rect 357 61 501 72)(font "Arial" (font_size 8)))
+		(line (pt 480 72)(pt 304 72)(line_width 1))
+	)
+	(port
+		(pt 480 192)
+		(input)
+		(text "st_splitter16_out1_ready" (rect 0 0 96 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_ready" (rect 359 181 503 192)(font "Arial" (font_size 8)))
+		(line (pt 480 192)(pt 304 192)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "st_splitter16_reset_reset" (rect 0 0 97 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_reset_reset" (rect 4 221 154 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 160 232)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(output)
+		(text "st_splitter16_in_ready" (rect 0 0 87 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_in_ready" (rect 4 101 136 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 160 112)(line_width 1))
+	)
+	(port
+		(pt 480 88)
+		(output)
+		(text "st_splitter16_out0_valid" (rect 0 0 92 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_valid" (rect 363 77 507 88)(font "Arial" (font_size 8)))
+		(line (pt 480 88)(pt 304 88)(line_width 1))
+	)
+	(port
+		(pt 480 104)
+		(output)
+		(text "st_splitter16_out0_startofpacket" (rect 0 0 126 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_startofpacket" (rect 320 93 512 104)(font "Arial" (font_size 8)))
+		(line (pt 480 104)(pt 304 104)(line_width 1))
+	)
+	(port
+		(pt 480 120)
+		(output)
+		(text "st_splitter16_out0_endofpacket" (rect 0 0 122 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_endofpacket" (rect 324 109 504 120)(font "Arial" (font_size 8)))
+		(line (pt 480 120)(pt 304 120)(line_width 1))
+	)
+	(port
+		(pt 480 136)
+		(output)
+		(text "st_splitter16_out0_empty" (rect 0 0 100 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_empty" (rect 356 125 500 136)(font "Arial" (font_size 8)))
+		(line (pt 480 136)(pt 304 136)(line_width 1))
+	)
+	(port
+		(pt 480 152)
+		(output)
+		(text "st_splitter16_out0_data[15..0]" (rect 0 0 114 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out0_data[15..0]" (rect 336 141 516 152)(font "Arial" (font_size 8)))
+		(line (pt 480 152)(pt 304 152)(line_width 3))
+	)
+	(port
+		(pt 480 208)
+		(output)
+		(text "st_splitter16_out1_valid" (rect 0 0 90 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_valid" (rect 365 197 509 208)(font "Arial" (font_size 8)))
+		(line (pt 480 208)(pt 304 208)(line_width 1))
+	)
+	(port
+		(pt 480 224)
+		(output)
+		(text "st_splitter16_out1_startofpacket" (rect 0 0 125 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_startofpacket" (rect 322 213 514 224)(font "Arial" (font_size 8)))
+		(line (pt 480 224)(pt 304 224)(line_width 1))
+	)
+	(port
+		(pt 480 240)
+		(output)
+		(text "st_splitter16_out1_endofpacket" (rect 0 0 121 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_endofpacket" (rect 326 229 506 240)(font "Arial" (font_size 8)))
+		(line (pt 480 240)(pt 304 240)(line_width 1))
+	)
+	(port
+		(pt 480 256)
+		(output)
+		(text "st_splitter16_out1_empty" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_empty" (rect 358 245 502 256)(font "Arial" (font_size 8)))
+		(line (pt 480 256)(pt 304 256)(line_width 1))
+	)
+	(port
+		(pt 480 272)
+		(output)
+		(text "st_splitter16_out1_data[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
+		(text "st_splitter16_out1_data[15..0]" (rect 338 261 518 272)(font "Arial" (font_size 8)))
+		(line (pt 480 272)(pt 304 272)(line_width 3))
+	)
+	(drawing
+		(text "st_splitter16_clk" (rect 66 43 234 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_in" (rect 72 83 240 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 165 107 360 224)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 165 123 360 256)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 165 139 408 288)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 165 155 396 320)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 165 171 360 352)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 165 187 354 384)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_out0" (rect 305 43 718 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 281 83 592 176)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 244 99 566 208)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 249 115 564 240)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 274 131 578 272)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 283 147 590 304)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_out1" (rect 305 163 718 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ready" (rect 276 187 582 384)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 281 203 592 416)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 244 219 566 448)(font "Arial" (color 0 0 0)))
+		(text "endofpacket" (rect 249 235 564 480)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 274 251 578 512)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 283 267 590 544)(font "Arial" (color 0 0 0)))
+		(text "st_splitter16_reset" (rect 52 203 218 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 165 227 360 464)(font "Arial" (color 0 0 0)))
+		(text " st_splitter16 " (rect 425 288 940 586)(font "Arial" ))
+		(line (pt 160 32)(pt 304 32)(line_width 1))
+		(line (pt 304 32)(pt 304 288)(line_width 1))
+		(line (pt 160 288)(pt 304 288)(line_width 1))
+		(line (pt 160 32)(pt 160 288)(line_width 1))
+		(line (pt 161 52)(pt 161 76)(line_width 1))
+		(line (pt 162 52)(pt 162 76)(line_width 1))
+		(line (pt 161 92)(pt 161 196)(line_width 1))
+		(line (pt 162 92)(pt 162 196)(line_width 1))
+		(line (pt 303 52)(pt 303 156)(line_width 1))
+		(line (pt 302 52)(pt 302 156)(line_width 1))
+		(line (pt 303 172)(pt 303 276)(line_width 1))
+		(line (pt 302 172)(pt 302 276)(line_width 1))
+		(line (pt 161 212)(pt 161 236)(line_width 1))
+		(line (pt 162 212)(pt 162 236)(line_width 1))
+		(line (pt 0 0)(pt 480 0)(line_width 1))
+		(line (pt 480 0)(pt 480 304)(line_width 1))
+		(line (pt 0 304)(pt 480 304)(line_width 1))
+		(line (pt 0 0)(pt 0 304)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.xml b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.xml
new file mode 100644
index 0000000..d7f08d2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16.xml
@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.02.15:16:06"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="st_splitter16_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="st_splitter16_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="st_splitter16_in" kind="avalon_streaming" start="0">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_in_ready"
+       direction="output"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_in_valid"
+       direction="input"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_in_startofpacket"
+       direction="input"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_in_endofpacket"
+       direction="input"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_in_empty"
+       direction="input"
+       role="empty"
+       width="1" />
+   <port name="st_splitter16_in_data" direction="input" role="data" width="16" />
+  </interface>
+  <interface name="st_splitter16_out0" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_out0_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_out0_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_out0_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out0_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out0_empty"
+       direction="output"
+       role="empty"
+       width="1" />
+   <port
+       name="st_splitter16_out0_data"
+       direction="output"
+       role="data"
+       width="16" />
+  </interface>
+  <interface name="st_splitter16_out1" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="associatedReset" value="st_splitter16_reset" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="2" />
+   <port
+       name="st_splitter16_out1_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="st_splitter16_out1_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+   <port
+       name="st_splitter16_out1_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out1_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="st_splitter16_out1_empty"
+       direction="output"
+       role="empty"
+       width="1" />
+   <port
+       name="st_splitter16_out1_data"
+       direction="output"
+       role="data"
+       width="16" />
+  </interface>
+  <interface name="st_splitter16_reset" kind="reset" start="0">
+   <property name="associatedClock" value="st_splitter16_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="st_splitter16_reset_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="st_splitter16:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1719926165,AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN=-1,AUTO_ST_SPLITTER16_CLK_CLOCK_RATE=-1,AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1)"
+   instancePathKey="st_splitter16"
+   kind="st_splitter16"
+   version="1.0"
+   name="st_splitter16">
+  <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter name="AUTO_GENERATION_ID" value="1719926165" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN" value="-1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/st_splitter16.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:st_splitter16 "st_splitter16"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" reuses <b>altera_avalon_st_splitter</b> "<b>submodules/altera_avalon_st_splitter</b>"]]></message>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
+   <message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1"
+   instancePathKey="st_splitter16:.:st_splitter16"
+   kind="altera_avalon_st_splitter"
+   version="19.1"
+   name="altera_avalon_st_splitter">
+  <parameter name="NUMBER_OF_OUTPUTS" value="2" />
+  <parameter name="USE_DATA" value="1" />
+  <parameter name="ERROR_DESCRIPTOR" value="" />
+  <parameter name="USE_PACKETS" value="1" />
+  <parameter name="USE_READY" value="1" />
+  <parameter name="MAX_CHANNELS" value="1" />
+  <parameter name="USE_ERROR" value="0" />
+  <parameter name="EMPTY_WIDTH" value="1" />
+  <parameter name="CHANNEL_WIDTH" value="1" />
+  <parameter name="READY_LATENCY" value="0" />
+  <parameter name="DATA_WIDTH" value="16" />
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="QUALIFY_VALID_OUT" value="1" />
+  <parameter name="USE_VALID" value="1" />
+  <parameter name="USE_CHANNEL" value="0" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="st_splitter16" as="st_splitter16" />
+  <messages>
+   <message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
+   <message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_bb.v b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_bb.v
new file mode 100644
index 0000000..30904bd
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_bb.v
@@ -0,0 +1,44 @@
+
+module st_splitter16 (
+	st_splitter16_clk_clk,
+	st_splitter16_reset_reset,
+	st_splitter16_in_ready,
+	st_splitter16_in_valid,
+	st_splitter16_in_startofpacket,
+	st_splitter16_in_endofpacket,
+	st_splitter16_in_empty,
+	st_splitter16_in_data,
+	st_splitter16_out0_ready,
+	st_splitter16_out0_valid,
+	st_splitter16_out0_startofpacket,
+	st_splitter16_out0_endofpacket,
+	st_splitter16_out0_empty,
+	st_splitter16_out0_data,
+	st_splitter16_out1_ready,
+	st_splitter16_out1_valid,
+	st_splitter16_out1_startofpacket,
+	st_splitter16_out1_endofpacket,
+	st_splitter16_out1_empty,
+	st_splitter16_out1_data);	
+
+	input		st_splitter16_clk_clk;
+	input		st_splitter16_reset_reset;
+	output		st_splitter16_in_ready;
+	input		st_splitter16_in_valid;
+	input		st_splitter16_in_startofpacket;
+	input		st_splitter16_in_endofpacket;
+	input	[0:0]	st_splitter16_in_empty;
+	input	[15:0]	st_splitter16_in_data;
+	input		st_splitter16_out0_ready;
+	output		st_splitter16_out0_valid;
+	output		st_splitter16_out0_startofpacket;
+	output		st_splitter16_out0_endofpacket;
+	output	[0:0]	st_splitter16_out0_empty;
+	output	[15:0]	st_splitter16_out0_data;
+	input		st_splitter16_out1_ready;
+	output		st_splitter16_out1_valid;
+	output		st_splitter16_out1_startofpacket;
+	output		st_splitter16_out1_endofpacket;
+	output	[0:0]	st_splitter16_out1_empty;
+	output	[15:0]	st_splitter16_out1_data;
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_inst.v b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_inst.v
new file mode 100644
index 0000000..45a2827
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/st_splitter16_inst.v
@@ -0,0 +1,23 @@
+	st_splitter16 u0 (
+		.st_splitter16_clk_clk            (<connected-to-st_splitter16_clk_clk>),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (<connected-to-st_splitter16_reset_reset>),        // st_splitter16_reset.reset
+		.st_splitter16_in_ready           (<connected-to-st_splitter16_in_ready>),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (<connected-to-st_splitter16_in_valid>),           //                    .valid
+		.st_splitter16_in_startofpacket   (<connected-to-st_splitter16_in_startofpacket>),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (<connected-to-st_splitter16_in_endofpacket>),     //                    .endofpacket
+		.st_splitter16_in_empty           (<connected-to-st_splitter16_in_empty>),           //                    .empty
+		.st_splitter16_in_data            (<connected-to-st_splitter16_in_data>),            //                    .data
+		.st_splitter16_out0_ready         (<connected-to-st_splitter16_out0_ready>),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (<connected-to-st_splitter16_out0_valid>),         //                    .valid
+		.st_splitter16_out0_startofpacket (<connected-to-st_splitter16_out0_startofpacket>), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (<connected-to-st_splitter16_out0_endofpacket>),   //                    .endofpacket
+		.st_splitter16_out0_empty         (<connected-to-st_splitter16_out0_empty>),         //                    .empty
+		.st_splitter16_out0_data          (<connected-to-st_splitter16_out0_data>),          //                    .data
+		.st_splitter16_out1_ready         (<connected-to-st_splitter16_out1_ready>),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (<connected-to-st_splitter16_out1_valid>),         //                    .valid
+		.st_splitter16_out1_startofpacket (<connected-to-st_splitter16_out1_startofpacket>), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (<connected-to-st_splitter16_out1_endofpacket>),   //                    .endofpacket
+		.st_splitter16_out1_empty         (<connected-to-st_splitter16_out1_empty>),         //                    .empty
+		.st_splitter16_out1_data          (<connected-to-st_splitter16_out1_data>)           //                    .data
+	);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv
new file mode 100644
index 0000000..c244a3f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/altera_avalon_st_splitter.sv
@@ -0,0 +1,422 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/main/ip/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter.sv $
+// $Revision: #3 $
+// $Date: 2012/01/18 $
+// $Author: pscheidt $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_splitter #(
+   parameter 
+      NUMBER_OF_OUTPUTS  = 2, 
+      QUALIFY_VALID_OUT  = 1, 
+      DATA_WIDTH         = 8,
+      BITS_PER_SYMBOL    = 8,
+      USE_PACKETS        = 0,   
+      CHANNEL_WIDTH      = 1,	   
+      ERROR_WIDTH        = 1,
+      EMPTY_WIDTH        = 1
+  )
+(
+   output wire                    in0_ready,
+   input  wire                    in0_valid,
+   input  wire  [DATA_WIDTH-1 :0] in0_data,
+   input  wire  [CHANNEL_WIDTH-1 :0] in0_channel,
+   input  wire  [ERROR_WIDTH-1   :0] in0_error,
+   input  wire                    in0_startofpacket,
+   input  wire                    in0_endofpacket,
+   input  wire  [EMPTY_WIDTH-1   :0] in0_empty,
+   
+   input  wire                    out0_ready,
+   output wire                    out0_valid,
+   output wire  [DATA_WIDTH-1 :0] out0_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out0_channel,
+   output wire  [ERROR_WIDTH-1   :0] out0_error,
+   output wire                    out0_startofpacket,
+   output wire                    out0_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out0_empty,
+   
+   input  wire                    out1_ready,
+   output wire                    out1_valid,
+   output wire  [DATA_WIDTH-1 :0] out1_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out1_channel,
+   output wire  [ERROR_WIDTH-1   :0] out1_error,
+   output wire                    out1_startofpacket,
+   output wire                    out1_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out1_empty,
+   
+   input  wire                    out2_ready,
+   output wire                    out2_valid,
+   output wire  [DATA_WIDTH-1 :0] out2_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out2_channel,
+   output wire  [ERROR_WIDTH-1   :0] out2_error,
+   output wire                    out2_startofpacket,
+   output wire                    out2_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out2_empty,
+   
+   input  wire                    out3_ready,
+   output wire                    out3_valid,
+   output wire  [DATA_WIDTH-1 :0] out3_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out3_channel,
+   output wire  [ERROR_WIDTH-1   :0] out3_error,
+   output wire                    out3_startofpacket,
+   output wire                    out3_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out3_empty,
+   
+   input  wire                    out4_ready,
+   output wire                    out4_valid,
+   output wire  [DATA_WIDTH-1 :0] out4_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out4_channel,
+   output wire  [ERROR_WIDTH-1   :0] out4_error,
+   output wire                    out4_startofpacket,
+   output wire                    out4_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out4_empty,
+   
+   input  wire                    out5_ready,
+   output wire                    out5_valid,
+   output wire  [DATA_WIDTH-1 :0] out5_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out5_channel,
+   output wire  [ERROR_WIDTH-1   :0] out5_error,
+   output wire                    out5_startofpacket,
+   output wire                    out5_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out5_empty,
+   
+   input  wire                    out6_ready,
+   output wire                    out6_valid,
+   output wire  [DATA_WIDTH-1 :0] out6_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out6_channel,
+   output wire  [ERROR_WIDTH-1   :0] out6_error,
+   output wire                    out6_startofpacket,
+   output wire                    out6_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out6_empty,
+   
+   input  wire                    out7_ready,
+   output wire                    out7_valid,
+   output wire  [DATA_WIDTH-1 :0] out7_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out7_channel,
+   output wire  [ERROR_WIDTH-1   :0] out7_error,
+   output wire                    out7_startofpacket,
+   output wire                    out7_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out7_empty,
+   
+   input  wire                    out8_ready,
+   output wire                    out8_valid,
+   output wire  [DATA_WIDTH-1 :0] out8_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out8_channel,
+   output wire  [ERROR_WIDTH-1   :0] out8_error,
+   output wire                    out8_startofpacket,
+   output wire                    out8_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out8_empty,
+   
+   input  wire                    out9_ready,
+   output wire                    out9_valid,
+   output wire  [DATA_WIDTH-1 :0] out9_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out9_channel,
+   output wire  [ERROR_WIDTH-1   :0] out9_error,
+   output wire                    out9_startofpacket,
+   output wire                    out9_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out9_empty,
+   
+   input  wire                    out10_ready,
+   output wire                    out10_valid,
+   output wire  [DATA_WIDTH-1 :0] out10_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out10_channel,
+   output wire  [ERROR_WIDTH-1   :0] out10_error,
+   output wire                    out10_startofpacket,
+   output wire                    out10_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out10_empty,
+   
+   input  wire                    out11_ready,
+   output wire                    out11_valid,
+   output wire  [DATA_WIDTH-1 :0] out11_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out11_channel,
+   output wire  [ERROR_WIDTH-1   :0] out11_error,
+   output wire                    out11_startofpacket,
+   output wire                    out11_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out11_empty,
+   
+   input  wire                    out12_ready,
+   output wire                    out12_valid,
+   output wire  [DATA_WIDTH-1 :0] out12_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out12_channel,
+   output wire  [ERROR_WIDTH-1   :0] out12_error,
+   output wire                    out12_startofpacket,
+   output wire                    out12_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out12_empty,
+   
+   input  wire                    out13_ready,
+   output wire                    out13_valid,
+   output wire  [DATA_WIDTH-1 :0] out13_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out13_channel,
+   output wire  [ERROR_WIDTH-1   :0] out13_error,
+   output wire                    out13_startofpacket,
+   output wire                    out13_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out13_empty,
+   
+   input  wire                    out14_ready,
+   output wire                    out14_valid,
+   output wire  [DATA_WIDTH-1 :0] out14_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out14_channel,
+   output wire  [ERROR_WIDTH-1   :0] out14_error,
+   output wire                    out14_startofpacket,
+   output wire                    out14_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out14_empty,
+   
+   input  wire                    out15_ready,
+   output wire                    out15_valid,
+   output wire  [DATA_WIDTH-1 :0] out15_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out15_channel,
+   output wire  [ERROR_WIDTH-1   :0] out15_error,
+   output wire                    out15_startofpacket,
+   output wire                    out15_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out15_empty,
+   
+   input  wire                    clk,
+   input  wire                    reset
+);
+
+
+// ********************************************************************
+// Module Wiring
+
+wire   [15:0]            OutReady;
+wire   [15:0]            OutValid;
+wire   [DATA_WIDTH-1 :0] OutData    [15:0];
+wire   [CHANNEL_WIDTH-1 :0] OutChannel [15:0];
+wire   [ERROR_WIDTH-1   :0] OutError   [15:0];
+wire   [15:0]            OutSOP;
+wire   [15:0]            OutEOP;
+wire   [EMPTY_WIDTH-1   :0] OutEmpty   [15:0];
+
+genvar                   i, j;
+
+
+// ********************************************************************
+// Module Logic
+
+assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]);
+
+
+generate
+   for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT
+      assign OutData[i]    = in0_data;
+      assign OutChannel[i] = in0_channel;
+      assign OutError[i]   = in0_error;
+      assign OutSOP[i]     = in0_startofpacket;
+      assign OutEOP[i]     = in0_endofpacket;
+      assign OutEmpty[i]   = in0_empty;
+   end
+endgenerate
+
+
+generate
+   for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT
+      assign OutData[j]    = {DATA_WIDTH{1'b0}};
+      assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}};
+      assign OutError[j]   = {ERROR_WIDTH{1'b0}};
+      assign OutSOP[j]     = 1'b0;
+      assign OutEOP[j]     = 1'b0;
+      assign OutEmpty[j]   = {EMPTY_WIDTH{1'b0}};
+   end
+endgenerate
+
+
+generate
+   if (QUALIFY_VALID_OUT) begin
+      assign OutValid[0]  = &{in0_valid, OutReady[15:1]};
+      assign OutValid[1]  = &{in0_valid, OutReady[15:2],  OutReady[0]};
+      assign OutValid[2]  = &{in0_valid, OutReady[15:3],  OutReady[1:0]};
+      assign OutValid[3]  = &{in0_valid, OutReady[15:4],  OutReady[2:0]};
+      assign OutValid[4]  = &{in0_valid, OutReady[15:5],  OutReady[3:0]};
+      assign OutValid[5]  = &{in0_valid, OutReady[15:6],  OutReady[4:0]};
+      assign OutValid[6]  = &{in0_valid, OutReady[15:7],  OutReady[5:0]};
+      assign OutValid[7]  = &{in0_valid, OutReady[15:8],  OutReady[6:0]};
+      assign OutValid[8]  = &{in0_valid, OutReady[15:9],  OutReady[7:0]};
+      assign OutValid[9]  = &{in0_valid, OutReady[15:10], OutReady[8:0]};
+      assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]};
+      assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]};
+      assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]};
+      assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]};
+      assign OutValid[14] = &{in0_valid, OutReady[15],    OutReady[13:0]};
+      assign OutValid[15] = &{in0_valid,                  OutReady[14:0]};
+   end
+   else begin
+      assign OutValid[0]  = in0_valid;
+      assign OutValid[1]  = in0_valid;
+      assign OutValid[2]  = in0_valid;
+      assign OutValid[3]  = in0_valid;
+      assign OutValid[4]  = in0_valid;
+      assign OutValid[5]  = in0_valid;
+      assign OutValid[6]  = in0_valid;
+      assign OutValid[7]  = in0_valid;
+      assign OutValid[8]  = in0_valid;
+      assign OutValid[9]  = in0_valid;
+      assign OutValid[10] = in0_valid;
+      assign OutValid[11] = in0_valid;
+      assign OutValid[12] = in0_valid;
+      assign OutValid[13] = in0_valid;
+      assign OutValid[14] = in0_valid;
+      assign OutValid[15] = in0_valid;
+   end
+endgenerate
+
+
+assign OutReady[0]        = out0_ready;
+assign out0_valid         = OutValid[0];
+assign out0_data          = OutData[0];
+assign out0_channel       = OutChannel[0];
+assign out0_error         = OutError[0];
+assign out0_startofpacket = OutSOP[0];
+assign out0_endofpacket   = OutEOP[0];
+assign out0_empty         = OutEmpty[0];
+
+assign OutReady[1]        = out1_ready;
+assign out1_valid         = OutValid[1];
+assign out1_data          = OutData[1];
+assign out1_channel       = OutChannel[1];
+assign out1_error         = OutError[1];
+assign out1_startofpacket = OutSOP[1];
+assign out1_endofpacket   = OutEOP[1];
+assign out1_empty         = OutEmpty[1];
+
+assign OutReady[2]        = out2_ready;
+assign out2_valid         = OutValid[2];
+assign out2_data          = OutData[2];
+assign out2_channel       = OutChannel[2];
+assign out2_error         = OutError[2];
+assign out2_startofpacket = OutSOP[2];
+assign out2_endofpacket   = OutEOP[2];
+assign out2_empty         = OutEmpty[2];
+
+assign OutReady[3]        = out3_ready;
+assign out3_valid         = OutValid[3];
+assign out3_data          = OutData[3];
+assign out3_channel       = OutChannel[3];
+assign out3_error         = OutError[3];
+assign out3_startofpacket = OutSOP[3];
+assign out3_endofpacket   = OutEOP[3];
+assign out3_empty         = OutEmpty[3];
+
+assign OutReady[4]        = out4_ready;
+assign out4_valid         = OutValid[4];
+assign out4_data          = OutData[4];
+assign out4_channel       = OutChannel[4];
+assign out4_error         = OutError[4];
+assign out4_startofpacket = OutSOP[4];
+assign out4_endofpacket   = OutEOP[4];
+assign out4_empty         = OutEmpty[4];
+
+assign OutReady[5]        = out5_ready;
+assign out5_valid         = OutValid[5];
+assign out5_data          = OutData[5];
+assign out5_channel       = OutChannel[5];
+assign out5_error         = OutError[5];
+assign out5_startofpacket = OutSOP[5];
+assign out5_endofpacket   = OutEOP[5];
+assign out5_empty         = OutEmpty[5];
+
+assign OutReady[6]        = out6_ready;
+assign out6_valid         = OutValid[6];
+assign out6_data          = OutData[6];
+assign out6_channel       = OutChannel[6];
+assign out6_error         = OutError[6];
+assign out6_startofpacket = OutSOP[6];
+assign out6_endofpacket   = OutEOP[6];
+assign out6_empty         = OutEmpty[6];
+
+assign OutReady[7]        = out7_ready;
+assign out7_valid         = OutValid[7];
+assign out7_data          = OutData[7];
+assign out7_channel       = OutChannel[7];
+assign out7_error         = OutError[7];
+assign out7_startofpacket = OutSOP[7];
+assign out7_endofpacket   = OutEOP[7];
+assign out7_empty         = OutEmpty[7];
+
+assign OutReady[8]        = out8_ready;
+assign out8_valid         = OutValid[8];
+assign out8_data          = OutData[8];
+assign out8_channel       = OutChannel[8];
+assign out8_error         = OutError[8];
+assign out8_startofpacket = OutSOP[8];
+assign out8_endofpacket   = OutEOP[8];
+assign out8_empty         = OutEmpty[8];
+
+assign OutReady[9]        = out9_ready;
+assign out9_valid         = OutValid[9];
+assign out9_data          = OutData[9];
+assign out9_channel       = OutChannel[9];
+assign out9_error         = OutError[9];
+assign out9_startofpacket = OutSOP[9];
+assign out9_endofpacket   = OutEOP[9];
+assign out9_empty         = OutEmpty[9];
+
+assign OutReady[10]        = out10_ready;
+assign out10_valid         = OutValid[10];
+assign out10_data          = OutData[10];
+assign out10_channel       = OutChannel[10];
+assign out10_error         = OutError[10];
+assign out10_startofpacket = OutSOP[10];
+assign out10_endofpacket   = OutEOP[10];
+assign out10_empty         = OutEmpty[10];
+
+assign OutReady[11]        = out11_ready;
+assign out11_valid         = OutValid[11];
+assign out11_data          = OutData[11];
+assign out11_channel       = OutChannel[11];
+assign out11_error         = OutError[11];
+assign out11_startofpacket = OutSOP[11];
+assign out11_endofpacket   = OutEOP[11];
+assign out11_empty         = OutEmpty[11];
+
+assign OutReady[12]        = out12_ready;
+assign out12_valid         = OutValid[12];
+assign out12_data          = OutData[12];
+assign out12_channel       = OutChannel[12];
+assign out12_error         = OutError[12];
+assign out12_startofpacket = OutSOP[12];
+assign out12_endofpacket   = OutEOP[12];
+assign out12_empty         = OutEmpty[12];
+
+assign OutReady[13]        = out13_ready;
+assign out13_valid         = OutValid[13];
+assign out13_data          = OutData[13];
+assign out13_channel       = OutChannel[13];
+assign out13_error         = OutError[13];
+assign out13_startofpacket = OutSOP[13];
+assign out13_endofpacket   = OutEOP[13];
+assign out13_empty         = OutEmpty[13];
+
+assign OutReady[14]        = out14_ready;
+assign out14_valid         = OutValid[14];
+assign out14_data          = OutData[14];
+assign out14_channel       = OutChannel[14];
+assign out14_error         = OutError[14];
+assign out14_startofpacket = OutSOP[14];
+assign out14_endofpacket   = OutEOP[14];
+assign out14_empty         = OutEmpty[14];
+
+assign OutReady[15]        = out15_ready;
+assign out15_valid         = OutValid[15];
+assign out15_data          = OutData[15];
+assign out15_channel       = OutChannel[15];
+assign out15_error         = OutError[15];
+assign out15_startofpacket = OutSOP[15];
+assign out15_endofpacket   = OutEOP[15];
+assign out15_empty         = OutEmpty[15];
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.debuginfo b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.debuginfo
new file mode 100644
index 0000000..95226c8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.debuginfo
@@ -0,0 +1,1513 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="cali_ram" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.02.15:49:43 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1719928182</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="cali_ram"
+   kind="altera_avalon_onchip_memory2"
+   version="19.1"
+   path="cali_ram">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.CONTENTS_INFO</name>
+   <value>""</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.DUAL_PORT</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
+   <value>cali_ram_cali_ram</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.INSTANCE_ID</name>
+   <value>NONE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
+   <value>AUTO</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
+   <value>DONT_CARE</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.SIZE_VALUE</name>
+   <value>640</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.CMacro.WRITABLE</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
+   <value>SIM_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
+   <value>1</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
+   <value>0</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
+   <value>QPF_DIR</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
+   <value>16</value>
+  </assignment>
+  <assignment>
+   <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
+   <value>cali_ram_cali_ram</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.param_name</name>
+   <value>INIT_FILE</value>
+  </assignment>
+  <assignment>
+   <name>postgeneration.simulation.init_file.type</name>
+   <value>MEM_INIT</value>
+  </assignment>
+  <parameter name="allowInSystemMemoryContentEditor">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="blockType">
+   <type>java.lang.String</type>
+   <value>AUTO</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dataWidth2">
+   <type>int</type>
+   <value>32</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="dualPort">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_enableDiffWidth">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initMemContent">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="initializationFileName">
+   <type>java.lang.String</type>
+   <value>onchip_mem.hex</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="enPRInitMode">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="instanceID">
+   <type>java.lang.String</type>
+   <value>NONE</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="memorySize">
+   <type>long</type>
+   <value>640</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="readDuringWriteMode">
+   <type>java.lang.String</type>
+   <value>DONT_CARE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simAllowMRAMContentsFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="simMemInitOnlyFilename">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_singleClockOperation">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave1Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="slave2Latency">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useNonDefaultInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="copyInitFile">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="useShallowMemBlocks">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="writable">
+   <type>boolean</type>
+   <value>true</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ecc_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="resetrequest_enabled">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="autoInitializationFileName">
+   <type>java.lang.String</type>
+   <value>cali_ram_cali_ram</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>UNIQUE_ID</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>MAX10FPGA</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="deviceFeatures">
+   <type>java.lang.String</type>
+   <value>ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
+  </parameter>
+  <parameter name="derived_set_addr_width">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_addr_width2">
+   <type>int</type>
+   <value>9</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_set_data_width2">
+   <type>int</type>
+   <value>16</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_gui_ram_block_type">
+   <type>java.lang.String</type>
+   <value>Automatic</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_is_hardcopy">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="derived_init_file_name">
+   <type>java.lang.String</type>
+   <value>cali_ram_cali_ram.hex</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk1" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="s1" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>chipselect</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="reset1" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="s2" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>1</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>640</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>address2</name>
+    <direction>Input</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>chipselect2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>chipselect</role>
+   </port>
+   <port>
+    <name>clken2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clken</role>
+   </port>
+   <port>
+    <name>write2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>readdata2</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>writedata2</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>byteenable2</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk2" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset2" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset2</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_onchip_memory2</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB0000019073B558AF</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.qip b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.qip
new file mode 100644
index 0000000..60aaa66
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.qip
@@ -0,0 +1,69 @@
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "cali_ram" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../cali_ram.sopcinfo"]
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name SLD_INFO "QSYS_NAME cali_ram HAS_SOPCINFO 1 GENERATION_ID 1719928182"
+set_global_assignment -library "cali_ram" -name MISC_FILE [file join $::quartus(qip_path) "../cali_ram.cmp"]
+set_global_assignment -library "cali_ram" -name SLD_FILE [file join $::quartus(qip_path) "cali_ram.debuginfo"]
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "cali_ram" -name MISC_FILE [file join $::quartus(qip_path) "../../cali_ram.qsys"]
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_NAME "Y2FsaV9yYW0="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_DISPLAY_NAME "Y2FsaV9yYW0="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcxOTkyODE4Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsxX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsxX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsxX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsyX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsyX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "QVVUT19DQUxJX1JBTV9DTEsyX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_NAME "Y2FsaV9yYW1fY2FsaV9yYW0="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "YWxsb3dJblN5c3RlbU1lbW9yeUNvbnRlbnRFZGl0b3I=::ZmFsc2U=::RW5hYmxlIEluLVN5c3RlbSBNZW1vcnkgQ29udGVudCBFZGl0b3IgZmVhdHVyZQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "YmxvY2tUeXBl::QVVUTw==::QmxvY2sgdHlwZQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRo::MTY=::U2xhdmUgUzEgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRoMg==::MzI=::U2xhdmUgUzIgRGF0YSB3aWR0aA=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZHVhbFBvcnQ=::dHJ1ZQ==::RHVhbC1wb3J0IGFjY2Vzcw=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZW5hYmxlRGlmZldpZHRo::ZmFsc2U=::RW5hYmxlIGRpZmZlcmVudCB3aWR0aCBmb3IgRHVhbC1wb3J0IGFjY2Vzcw=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg=::ZmFsc2U=::ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "aW5pdE1lbUNvbnRlbnQ=::ZmFsc2U=::SW5pdGlhbGl6ZSBtZW1vcnkgY29udGVudA=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "bWVtb3J5U2l6ZQ==::NjQw::VG90YWwgbWVtb3J5IHNpemU="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "cmVhZER1cmluZ1dyaXRlTW9kZQ==::RE9OVF9DQVJF::UmVhZCBEdXJpbmcgV3JpdGUgTW9kZQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "c2ltQWxsb3dNUkFNQ29udGVudHNGaWxl::ZmFsc2U=::QWxsb3cgTVJBTSBjb250ZW50cyBmaWxlIGZvciBzaW11bGF0aW9u"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "c2ltTWVtSW5pdE9ubHlGaWxlbmFtZQ==::MA==::U2ltdWxhdGlvbiBtZW1pbml0IG9ubHkgaGFzIGZpbGVuYW1l"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "c2luZ2xlQ2xvY2tPcGVyYXRpb24=::ZmFsc2U=::U2luZ2xlIGNsb2NrIG9wZXJhdGlvbg=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg==::ZmFsc2U=::ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "c2xhdmUxTGF0ZW5jeQ==::MQ==::U2xhdmUgczEgTGF0ZW5jeQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "c2xhdmUyTGF0ZW5jeQ==::MQ==::U2xhdmUgczIgTGF0ZW5jeQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "d3JpdGFibGU=::dHJ1ZQ==::VHlwZQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZWNjX2VuYWJsZWQ=::ZmFsc2U=::RXh0ZW5kIHRoZSBkYXRhIHdpZHRoIHRvIHN1cHBvcnQgRUNDIGJpdHM="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::ZmFsc2U=::UmVzZXQgUmVxdWVzdA=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU=::Y2FsaV9yYW1fY2FsaV9yYW0=::YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::TUFYIDEw::ZGV2aWNlRmFtaWx5"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXM=::ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1::ZGV2aWNlRmVhdHVyZXM="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aA==::OQ==::U2xhdmUgMSBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aDI=::OQ==::U2xhdmUgMiBhZGRyZXNzIHdpZHRo"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aA==::MTY=::U2xhdmUgMSBkYXRhIHdpZHRo"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aDI=::MTY=::U2xhdmUgMiBkYXRhIHdpZHRo"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU=::QXV0b21hdGlj::ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pc19oYXJkY29weQ==::ZmFsc2U=::ZGVyaXZlZF9pc19oYXJkY29weQ=="
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ==::Y2FsaV9yYW1fY2FsaV9yYW0uaGV4::ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ=="
+
+set_global_assignment -library "cali_ram" -name VERILOG_FILE [file join $::quartus(qip_path) "cali_ram.v"]
+set_global_assignment -library "cali_ram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/cali_ram_cali_ram.v"]
+
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_TOOL_NAME "altera_avalon_onchip_memory2"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "cali_ram_cali_ram" -library "cali_ram" -name IP_TOOL_ENV "Qsys"
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.v
new file mode 100644
index 0000000..0d19a4f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/cali_ram.v
@@ -0,0 +1,51 @@
+// cali_ram.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module cali_ram (
+		input  wire        cali_ram_clk1_clk,      //   cali_ram_clk1.clk
+		input  wire        cali_ram_clk2_clk,      //   cali_ram_clk2.clk
+		input  wire        cali_ram_reset1_reset,  // cali_ram_reset1.reset
+		input  wire        cali_ram_reset2_reset,  // cali_ram_reset2.reset
+		input  wire [8:0]  cali_ram_s1_address,    //     cali_ram_s1.address
+		input  wire        cali_ram_s1_clken,      //                .clken
+		input  wire        cali_ram_s1_chipselect, //                .chipselect
+		input  wire        cali_ram_s1_write,      //                .write
+		output wire [15:0] cali_ram_s1_readdata,   //                .readdata
+		input  wire [15:0] cali_ram_s1_writedata,  //                .writedata
+		input  wire [1:0]  cali_ram_s1_byteenable, //                .byteenable
+		input  wire [8:0]  cali_ram_s2_address,    //     cali_ram_s2.address
+		input  wire        cali_ram_s2_chipselect, //                .chipselect
+		input  wire        cali_ram_s2_clken,      //                .clken
+		input  wire        cali_ram_s2_write,      //                .write
+		output wire [15:0] cali_ram_s2_readdata,   //                .readdata
+		input  wire [15:0] cali_ram_s2_writedata,  //                .writedata
+		input  wire [1:0]  cali_ram_s2_byteenable  //                .byteenable
+	);
+
+	cali_ram_cali_ram cali_ram (
+		.clk         (cali_ram_clk1_clk),      //   clk1.clk
+		.address     (cali_ram_s1_address),    //     s1.address
+		.clken       (cali_ram_s1_clken),      //       .clken
+		.chipselect  (cali_ram_s1_chipselect), //       .chipselect
+		.write       (cali_ram_s1_write),      //       .write
+		.readdata    (cali_ram_s1_readdata),   //       .readdata
+		.writedata   (cali_ram_s1_writedata),  //       .writedata
+		.byteenable  (cali_ram_s1_byteenable), //       .byteenable
+		.reset       (cali_ram_reset1_reset),  // reset1.reset
+		.address2    (cali_ram_s2_address),    //     s2.address
+		.chipselect2 (cali_ram_s2_chipselect), //       .chipselect
+		.clken2      (cali_ram_s2_clken),      //       .clken
+		.write2      (cali_ram_s2_write),      //       .write
+		.readdata2   (cali_ram_s2_readdata),   //       .readdata
+		.writedata2  (cali_ram_s2_writedata),  //       .writedata
+		.byteenable2 (cali_ram_s2_byteenable), //       .byteenable
+		.clk2        (cali_ram_clk2_clk),      //   clk2.clk
+		.reset2      (cali_ram_reset2_reset),  // reset2.reset
+		.reset_req   (1'b0),                   // (terminated)
+		.freeze      (1'b0),                   // (terminated)
+		.reset_req2  (1'b0)                    // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.debuginfo b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.debuginfo
new file mode 100644
index 0000000..048fabd
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.debuginfo
@@ -0,0 +1,1312 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="sensor_algo" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.17.13:03:39 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1721214219</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value>sensor_algo_qsys.qpf</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_algo_0"
+   kind="sensor_algo"
+   version="1.0"
+   path="sensor_algo_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="avalon_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_algo</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_algo(rms)</displayName>
+  <version>1.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB00000190C05CB5A1</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.qip b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.qip
new file mode 100644
index 0000000..eb9816d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.qip
@@ -0,0 +1,26 @@
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "sensor_algo" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../sensor_algo.sopcinfo"]
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name SLD_INFO "QSYS_NAME sensor_algo HAS_SOPCINFO 1 GENERATION_ID 1721214219"
+set_global_assignment -library "sensor_algo" -name MISC_FILE [file join $::quartus(qip_path) "../sensor_algo.cmp"]
+set_global_assignment -library "sensor_algo" -name SLD_FILE [file join $::quartus(qip_path) "sensor_algo.debuginfo"]
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "sensor_algo" -name MISC_FILE [file join $::quartus(qip_path) "../../sensor_algo.qsys"]
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_NAME "c2Vuc29yX2FsZ28="
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_DISPLAY_NAME "c2Vuc29yX2FsZ28="
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyMTIxNDIxOQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfQUxHT18wX0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfQUxHT18wX0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "sensor_algo" -library "sensor_algo" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfQUxHT18wX0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+
+set_global_assignment -library "sensor_algo" -name VERILOG_FILE [file join $::quartus(qip_path) "sensor_algo.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v
new file mode 100644
index 0000000..d429c4d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v
@@ -0,0 +1,42 @@
+// sensor_algo.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo (
+		input  wire  sensor_algo_0_clk_clk,   // sensor_algo_0_clk.clk
+		input  wire  sensor_algo_0_rst_reset  // sensor_algo_0_rst.reset
+	);
+
+	sensor_algo sensor_algo_0 (
+		.csr_address            (),                        //           csr.address
+		.csr_read               (),                        //              .read
+		.csr_readdata           (),                        //              .readdata
+		.csr_write              (),                        //              .write
+		.csr_writedata          (),                        //              .writedata
+		.csr_byteenable         (),                        //              .byteenable
+		.clk_clk                (sensor_algo_0_clk_clk),   //           clk.clk
+		.rst_reset              (sensor_algo_0_rst_reset), //           rst.reset
+		.data_out_data          (),                        //      data_out.data
+		.data_out_empty         (),                        //              .empty
+		.data_out_ready         (),                        //              .ready
+		.data_out_startofpacket (),                        //              .startofpacket
+		.data_out_valid         (),                        //              .valid
+		.data_out_endofpacket   (),                        //              .endofpacket
+		.in_adc_data            (),                        //        sensor.in_adc_data
+		.in_trg                 (),                        //              .in_trg
+		.out_adc_clk            (),                        //              .out_adc_clk
+		.out_adc_cnv            (),                        //              .out_adc_cnv
+		.out_sensor_clk         (),                        //              .out_sensor_clk
+		.out_sensor_gain        (),                        //              .out_sensor_gain
+		.out_sensor_rst         (),                        //              .out_sensor_rst
+		.ext_input              (),                        //       synchro.ext_input
+		.serial_rx              (),                        //              .serial_rx
+		.serial_tx              (),                        //              .serial_tx
+		.status_out             (),                        //    status_out.status_out
+		.address                (),                        // avalon_master.address
+		.clken                  (),                        //              .read
+		.cali_fac               ()                         //              .readdata
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.debuginfo b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.debuginfo
new file mode 100644
index 0000000..2544563
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.debuginfo
@@ -0,0 +1,1318 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="sensor_recon" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.18.17:04:57 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1721315097</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_recon_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB00000190C65FFB67</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.qip b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.qip
new file mode 100644
index 0000000..9e04da1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.qip
@@ -0,0 +1,50 @@
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "sensor_recon" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../sensor_recon.sopcinfo"]
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name SLD_INFO "QSYS_NAME sensor_recon HAS_SOPCINFO 1 GENERATION_ID 1721315097"
+set_global_assignment -library "sensor_recon" -name MISC_FILE [file join $::quartus(qip_path) "../sensor_recon.cmp"]
+set_global_assignment -library "sensor_recon" -name SLD_FILE [file join $::quartus(qip_path) "sensor_recon.debuginfo"]
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "sensor_recon" -name MISC_FILE [file join $::quartus(qip_path) "../../sensor_recon.qsys"]
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_NAME "c2Vuc29yX3JlY29u"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_DISPLAY_NAME "c2Vuc29yX3JlY29u"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyMTMxNTA5Nw==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DQUxJQlJBVElPTl9SQU1fSU5URVJGQUNFX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gLTE=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "sensor_recon" -library "sensor_recon" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_NAME "c2Vuc29yX2FsZ28="
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_DISPLAY_NAME "c2Vuc29yX3JlY29uX3Jtc19jYWxp"
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_AUTHOR "UWluLExpcWluZyAxNy5KdWx5LDIwMjQ="
+set_global_assignment -entity "sensor_algo" -library "sensor_recon" -name IP_COMPONENT_VERSION "MQ=="
+
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "sensor_recon.v"]
+set_global_assignment -library "sensor_recon" -name QIP_FILE [file join $::quartus(qip_path) "submodules/div.qip"]
+set_global_assignment -library "sensor_recon" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rms.sv"]
+set_global_assignment -library "sensor_recon" -name QIP_FILE [file join $::quartus(qip_path) "submodules/st_splitter16.qip"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/stl2sts.v"]
+set_global_assignment -library "sensor_recon" -name QIP_FILE [file join $::quartus(qip_path) "submodules/ram4bkg.qip"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/calibration.v"]
+set_global_assignment -library "sensor_recon" -name QIP_FILE [file join $::quartus(qip_path) "submodules/data_caled_ram.qip"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/algo_top_cl_cali_rms.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_interface.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_rx.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_tx.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_algo.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/bkg_subtraction_pipe.v"]
+set_global_assignment -library "sensor_recon" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/cluster_locate.sv"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/data_caled_ram.v"]
+set_global_assignment -library "sensor_recon" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/st_splitter16.v"]
+set_global_assignment -library "sensor_recon" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_splitter.sv"]
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.v
new file mode 100644
index 0000000..0062804
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/sensor_recon.v
@@ -0,0 +1,70 @@
+// sensor_recon.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_recon (
+		output wire [8:0]  sensor_recon_0_calibration_ram_interface_address,     // sensor_recon_0_calibration_ram_interface.address
+		output wire        sensor_recon_0_calibration_ram_interface_read,        //                                         .read
+		input  wire [15:0] sensor_recon_0_calibration_ram_interface_readdata,    //                                         .readdata
+		input  wire        sensor_recon_0_calibration_ram_interface_waitrequest, //                                         .waitrequest
+		input  wire        sensor_recon_0_clk_clk,                               //                       sensor_recon_0_clk.clk
+		input  wire [1:0]  sensor_recon_0_csr_address,                           //                       sensor_recon_0_csr.address
+		input  wire        sensor_recon_0_csr_read,                              //                                         .read
+		output wire [31:0] sensor_recon_0_csr_readdata,                          //                                         .readdata
+		input  wire        sensor_recon_0_csr_write,                             //                                         .write
+		input  wire [31:0] sensor_recon_0_csr_writedata,                         //                                         .writedata
+		input  wire [3:0]  sensor_recon_0_csr_byteenable,                        //                                         .byteenable
+		output wire        sensor_recon_0_data_out_endofpacket,                  //                  sensor_recon_0_data_out.endofpacket
+		output wire [31:0] sensor_recon_0_data_out_data,                         //                                         .data
+		output wire [1:0]  sensor_recon_0_data_out_empty,                        //                                         .empty
+		input  wire        sensor_recon_0_data_out_ready,                        //                                         .ready
+		output wire        sensor_recon_0_data_out_startofpacket,                //                                         .startofpacket
+		output wire        sensor_recon_0_data_out_valid,                        //                                         .valid
+		input  wire        sensor_recon_0_rst_reset,                             //                       sensor_recon_0_rst.reset
+		input  wire [4:0]  sensor_recon_0_sensor_in_adc_data,                    //                    sensor_recon_0_sensor.in_adc_data
+		input  wire        sensor_recon_0_sensor_in_trg,                         //                                         .in_trg
+		output wire        sensor_recon_0_sensor_out_adc_clk,                    //                                         .out_adc_clk
+		output wire        sensor_recon_0_sensor_out_adc_cnv,                    //                                         .out_adc_cnv
+		output wire        sensor_recon_0_sensor_out_sensor_clk,                 //                                         .out_sensor_clk
+		output wire        sensor_recon_0_sensor_out_sensor_gain,                //                                         .out_sensor_gain
+		output wire        sensor_recon_0_sensor_out_sensor_rst,                 //                                         .out_sensor_rst
+		output wire [7:0]  sensor_recon_0_status_out_status_out,                 //                sensor_recon_0_status_out.status_out
+		input  wire [7:0]  sensor_recon_0_synchro_ext_input,                     //                   sensor_recon_0_synchro.ext_input
+		input  wire        sensor_recon_0_synchro_serial_rx,                     //                                         .serial_rx
+		output wire        sensor_recon_0_synchro_serial_tx                      //                                         .serial_tx
+	);
+
+	sensor_algo sensor_recon_0 (
+		.csr_address            (sensor_recon_0_csr_address),                           //                       csr.address
+		.csr_read               (sensor_recon_0_csr_read),                              //                          .read
+		.csr_readdata           (sensor_recon_0_csr_readdata),                          //                          .readdata
+		.csr_write              (sensor_recon_0_csr_write),                             //                          .write
+		.csr_writedata          (sensor_recon_0_csr_writedata),                         //                          .writedata
+		.csr_byteenable         (sensor_recon_0_csr_byteenable),                        //                          .byteenable
+		.data_out_endofpacket   (sensor_recon_0_data_out_endofpacket),                  //                  data_out.endofpacket
+		.data_out_data          (sensor_recon_0_data_out_data),                         //                          .data
+		.data_out_empty         (sensor_recon_0_data_out_empty),                        //                          .empty
+		.data_out_ready         (sensor_recon_0_data_out_ready),                        //                          .ready
+		.data_out_startofpacket (sensor_recon_0_data_out_startofpacket),                //                          .startofpacket
+		.data_out_valid         (sensor_recon_0_data_out_valid),                        //                          .valid
+		.clk_clk                (sensor_recon_0_clk_clk),                               //                       clk.clk
+		.rst_reset              (sensor_recon_0_rst_reset),                             //                       rst.reset
+		.in_adc_data            (sensor_recon_0_sensor_in_adc_data),                    //                    sensor.in_adc_data
+		.in_trg                 (sensor_recon_0_sensor_in_trg),                         //                          .in_trg
+		.out_adc_clk            (sensor_recon_0_sensor_out_adc_clk),                    //                          .out_adc_clk
+		.out_adc_cnv            (sensor_recon_0_sensor_out_adc_cnv),                    //                          .out_adc_cnv
+		.out_sensor_clk         (sensor_recon_0_sensor_out_sensor_clk),                 //                          .out_sensor_clk
+		.out_sensor_gain        (sensor_recon_0_sensor_out_sensor_gain),                //                          .out_sensor_gain
+		.out_sensor_rst         (sensor_recon_0_sensor_out_sensor_rst),                 //                          .out_sensor_rst
+		.status_out             (sensor_recon_0_status_out_status_out),                 //                status_out.status_out
+		.ext_input              (sensor_recon_0_synchro_ext_input),                     //                   synchro.ext_input
+		.serial_rx              (sensor_recon_0_synchro_serial_rx),                     //                          .serial_rx
+		.serial_tx              (sensor_recon_0_synchro_serial_tx),                     //                          .serial_tx
+		.address                (sensor_recon_0_calibration_ram_interface_address),     // calibration_ram_interface.address
+		.clken                  (sensor_recon_0_calibration_ram_interface_read),        //                          .read
+		.cali_fac               (sensor_recon_0_calibration_ram_interface_readdata),    //                          .readdata
+		.waitrequest            (sensor_recon_0_calibration_ram_interface_waitrequest)  //                          .waitrequest
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.debuginfo b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.debuginfo
new file mode 100644
index 0000000..3f4401a
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.debuginfo
@@ -0,0 +1,899 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="st_splitter16" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.02.15:16:06 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1719926165</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="st_splitter16"
+   kind="altera_avalon_st_splitter"
+   version="19.1"
+   path="st_splitter16">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUMBER_OF_OUTPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_VALID_OUT">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_READY">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_VALID">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_PACKETS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_CHANNEL">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_ERROR">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DATA">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BITS_PER_SYMBOL">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_CHANNELS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READY_LATENCY">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_DESCRIPTOR">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EMPTY_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in0_empty</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in0_data</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+  <interface name="out0" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out0_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out0_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out0_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out0_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out0_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out0_data</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+  <interface name="out1" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out1_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out1_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out1_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out1_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out1_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out1_data</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_st_splitter</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Splitter</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Sink</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB000001907396921F</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.qip b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.qip
new file mode 100644
index 0000000..ff332e8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.qip
@@ -0,0 +1,52 @@
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "st_splitter16" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../st_splitter16.sopcinfo"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name SLD_INFO "QSYS_NAME st_splitter16 HAS_SOPCINFO 1 GENERATION_ID 1719926165"
+set_global_assignment -library "st_splitter16" -name MISC_FILE [file join $::quartus(qip_path) "../st_splitter16.cmp"]
+set_global_assignment -library "st_splitter16" -name SLD_FILE [file join $::quartus(qip_path) "st_splitter16.debuginfo"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "st_splitter16" -name MISC_FILE [file join $::quartus(qip_path) "../../st_splitter16.qsys"]
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_NAME "c3Rfc3BsaXR0ZXIxNg=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_DISPLAY_NAME "c3Rfc3BsaXR0ZXIxNg=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcxOTkyNjE2NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "st_splitter16" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QVVUT19TVF9TUExJVFRFUjE2X0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9zcGxpdHRlcg=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFNwbGl0dGVy"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_VERSION "MTkuMQ=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIFNwbGl0dGVy"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX09VVFBVVFM=::Mg==::TlVNQkVSX09GX09VVFBVVFM="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "UVVBTElGWV9WQUxJRF9PVVQ=::MQ==::UVVBTElGWV9WQUxJRF9PVVQ="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURZ::MQ==::VVNFX1JFQURZ"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1ZBTElE::MQ==::VVNFX1ZBTElE"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MQ==::VVNFX1BBQ0tFVFM="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0NIQU5ORUw=::MA==::VVNFX0NIQU5ORUw="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0VSUk9S::MA==::VVNFX0VSUk9S"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "VVNFX0RBVEE=::MQ==::VVNFX0RBVEE="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "REFUQV9XSURUSA==::MTY=::REFUQV9XSURUSA=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MQ==::Q0hBTk5FTF9XSURUSA=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MQ==::RVJST1JfV0lEVEg="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::OA==::QklUU19QRVJfU1lNQk9M"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "UkVBRFlfTEFURU5DWQ==::MA==::UkVBRFlfTEFURU5DWQ=="
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_COMPONENT_PARAMETER "RU1QVFlfV0lEVEg=::MQ==::RU1QVFlfV0lEVEg="
+
+set_global_assignment -library "st_splitter16" -name VERILOG_FILE [file join $::quartus(qip_path) "st_splitter16.v"]
+set_global_assignment -library "st_splitter16" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_st_splitter.sv"]
+
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_NAME "altera_avalon_st_splitter"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "altera_avalon_st_splitter" -library "st_splitter16" -name IP_TOOL_ENV "Qsys"
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v
new file mode 100644
index 0000000..823c35f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v
@@ -0,0 +1,179 @@
+// st_splitter16.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module st_splitter16 (
+		input  wire        st_splitter16_clk_clk,            //   st_splitter16_clk.clk
+		output wire        st_splitter16_in_ready,           //    st_splitter16_in.ready
+		input  wire        st_splitter16_in_valid,           //                    .valid
+		input  wire        st_splitter16_in_startofpacket,   //                    .startofpacket
+		input  wire        st_splitter16_in_endofpacket,     //                    .endofpacket
+		input  wire [0:0]  st_splitter16_in_empty,           //                    .empty
+		input  wire [15:0] st_splitter16_in_data,            //                    .data
+		input  wire        st_splitter16_out0_ready,         //  st_splitter16_out0.ready
+		output wire        st_splitter16_out0_valid,         //                    .valid
+		output wire        st_splitter16_out0_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out0_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out0_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out0_data,          //                    .data
+		input  wire        st_splitter16_out1_ready,         //  st_splitter16_out1.ready
+		output wire        st_splitter16_out1_valid,         //                    .valid
+		output wire        st_splitter16_out1_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out1_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out1_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out1_data,          //                    .data
+		input  wire        st_splitter16_reset_reset         // st_splitter16_reset.reset
+	);
+
+	altera_avalon_st_splitter #(
+		.NUMBER_OF_OUTPUTS (2),
+		.QUALIFY_VALID_OUT (1),
+		.USE_PACKETS       (1),
+		.DATA_WIDTH        (16),
+		.CHANNEL_WIDTH     (1),
+		.ERROR_WIDTH       (1),
+		.BITS_PER_SYMBOL   (8),
+		.EMPTY_WIDTH       (1)
+	) st_splitter16 (
+		.clk                 (st_splitter16_clk_clk),            //   clk.clk
+		.reset               (st_splitter16_reset_reset),        // reset.reset
+		.in0_ready           (st_splitter16_in_ready),           //    in.ready
+		.in0_valid           (st_splitter16_in_valid),           //      .valid
+		.in0_startofpacket   (st_splitter16_in_startofpacket),   //      .startofpacket
+		.in0_endofpacket     (st_splitter16_in_endofpacket),     //      .endofpacket
+		.in0_empty           (st_splitter16_in_empty),           //      .empty
+		.in0_data            (st_splitter16_in_data),            //      .data
+		.out0_ready          (st_splitter16_out0_ready),         //  out0.ready
+		.out0_valid          (st_splitter16_out0_valid),         //      .valid
+		.out0_startofpacket  (st_splitter16_out0_startofpacket), //      .startofpacket
+		.out0_endofpacket    (st_splitter16_out0_endofpacket),   //      .endofpacket
+		.out0_empty          (st_splitter16_out0_empty),         //      .empty
+		.out0_data           (st_splitter16_out0_data),          //      .data
+		.out1_ready          (st_splitter16_out1_ready),         //  out1.ready
+		.out1_valid          (st_splitter16_out1_valid),         //      .valid
+		.out1_startofpacket  (st_splitter16_out1_startofpacket), //      .startofpacket
+		.out1_endofpacket    (st_splitter16_out1_endofpacket),   //      .endofpacket
+		.out1_empty          (st_splitter16_out1_empty),         //      .empty
+		.out1_data           (st_splitter16_out1_data),          //      .data
+		.in0_channel         (1'b0),                             // (terminated)
+		.in0_error           (1'b0),                             // (terminated)
+		.out0_channel        (),                                 // (terminated)
+		.out0_error          (),                                 // (terminated)
+		.out1_channel        (),                                 // (terminated)
+		.out1_error          (),                                 // (terminated)
+		.out2_ready          (1'b1),                             // (terminated)
+		.out2_valid          (),                                 // (terminated)
+		.out2_startofpacket  (),                                 // (terminated)
+		.out2_endofpacket    (),                                 // (terminated)
+		.out2_empty          (),                                 // (terminated)
+		.out2_channel        (),                                 // (terminated)
+		.out2_error          (),                                 // (terminated)
+		.out2_data           (),                                 // (terminated)
+		.out3_ready          (1'b1),                             // (terminated)
+		.out3_valid          (),                                 // (terminated)
+		.out3_startofpacket  (),                                 // (terminated)
+		.out3_endofpacket    (),                                 // (terminated)
+		.out3_empty          (),                                 // (terminated)
+		.out3_channel        (),                                 // (terminated)
+		.out3_error          (),                                 // (terminated)
+		.out3_data           (),                                 // (terminated)
+		.out4_ready          (1'b1),                             // (terminated)
+		.out4_valid          (),                                 // (terminated)
+		.out4_startofpacket  (),                                 // (terminated)
+		.out4_endofpacket    (),                                 // (terminated)
+		.out4_empty          (),                                 // (terminated)
+		.out4_channel        (),                                 // (terminated)
+		.out4_error          (),                                 // (terminated)
+		.out4_data           (),                                 // (terminated)
+		.out5_ready          (1'b1),                             // (terminated)
+		.out5_valid          (),                                 // (terminated)
+		.out5_startofpacket  (),                                 // (terminated)
+		.out5_endofpacket    (),                                 // (terminated)
+		.out5_empty          (),                                 // (terminated)
+		.out5_channel        (),                                 // (terminated)
+		.out5_error          (),                                 // (terminated)
+		.out5_data           (),                                 // (terminated)
+		.out6_ready          (1'b1),                             // (terminated)
+		.out6_valid          (),                                 // (terminated)
+		.out6_startofpacket  (),                                 // (terminated)
+		.out6_endofpacket    (),                                 // (terminated)
+		.out6_empty          (),                                 // (terminated)
+		.out6_channel        (),                                 // (terminated)
+		.out6_error          (),                                 // (terminated)
+		.out6_data           (),                                 // (terminated)
+		.out7_ready          (1'b1),                             // (terminated)
+		.out7_valid          (),                                 // (terminated)
+		.out7_startofpacket  (),                                 // (terminated)
+		.out7_endofpacket    (),                                 // (terminated)
+		.out7_empty          (),                                 // (terminated)
+		.out7_channel        (),                                 // (terminated)
+		.out7_error          (),                                 // (terminated)
+		.out7_data           (),                                 // (terminated)
+		.out8_ready          (1'b1),                             // (terminated)
+		.out8_valid          (),                                 // (terminated)
+		.out8_startofpacket  (),                                 // (terminated)
+		.out8_endofpacket    (),                                 // (terminated)
+		.out8_empty          (),                                 // (terminated)
+		.out8_channel        (),                                 // (terminated)
+		.out8_error          (),                                 // (terminated)
+		.out8_data           (),                                 // (terminated)
+		.out9_ready          (1'b1),                             // (terminated)
+		.out9_valid          (),                                 // (terminated)
+		.out9_startofpacket  (),                                 // (terminated)
+		.out9_endofpacket    (),                                 // (terminated)
+		.out9_empty          (),                                 // (terminated)
+		.out9_channel        (),                                 // (terminated)
+		.out9_error          (),                                 // (terminated)
+		.out9_data           (),                                 // (terminated)
+		.out10_ready         (1'b1),                             // (terminated)
+		.out10_valid         (),                                 // (terminated)
+		.out10_startofpacket (),                                 // (terminated)
+		.out10_endofpacket   (),                                 // (terminated)
+		.out10_empty         (),                                 // (terminated)
+		.out10_channel       (),                                 // (terminated)
+		.out10_error         (),                                 // (terminated)
+		.out10_data          (),                                 // (terminated)
+		.out11_ready         (1'b1),                             // (terminated)
+		.out11_valid         (),                                 // (terminated)
+		.out11_startofpacket (),                                 // (terminated)
+		.out11_endofpacket   (),                                 // (terminated)
+		.out11_empty         (),                                 // (terminated)
+		.out11_channel       (),                                 // (terminated)
+		.out11_error         (),                                 // (terminated)
+		.out11_data          (),                                 // (terminated)
+		.out12_ready         (1'b1),                             // (terminated)
+		.out12_valid         (),                                 // (terminated)
+		.out12_startofpacket (),                                 // (terminated)
+		.out12_endofpacket   (),                                 // (terminated)
+		.out12_empty         (),                                 // (terminated)
+		.out12_channel       (),                                 // (terminated)
+		.out12_error         (),                                 // (terminated)
+		.out12_data          (),                                 // (terminated)
+		.out13_ready         (1'b1),                             // (terminated)
+		.out13_valid         (),                                 // (terminated)
+		.out13_startofpacket (),                                 // (terminated)
+		.out13_endofpacket   (),                                 // (terminated)
+		.out13_empty         (),                                 // (terminated)
+		.out13_channel       (),                                 // (terminated)
+		.out13_error         (),                                 // (terminated)
+		.out13_data          (),                                 // (terminated)
+		.out14_ready         (1'b1),                             // (terminated)
+		.out14_valid         (),                                 // (terminated)
+		.out14_startofpacket (),                                 // (terminated)
+		.out14_endofpacket   (),                                 // (terminated)
+		.out14_empty         (),                                 // (terminated)
+		.out14_channel       (),                                 // (terminated)
+		.out14_error         (),                                 // (terminated)
+		.out14_data          (),                                 // (terminated)
+		.out15_ready         (1'b1),                             // (terminated)
+		.out15_valid         (),                                 // (terminated)
+		.out15_startofpacket (),                                 // (terminated)
+		.out15_endofpacket   (),                                 // (terminated)
+		.out15_empty         (),                                 // (terminated)
+		.out15_channel       (),                                 // (terminated)
+		.out15_error         (),                                 // (terminated)
+		.out15_data          ()                                  // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
new file mode 100644
index 0000000..6492c04
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
@@ -0,0 +1,352 @@
+//module algo_top_cl_cali_rms
+//combine bkg_subtraction, cluster_locate, and calibration, and rms
+
+//tested with algo_top_cl_cali_rms_tb.v
+module algo_top_cl_cali_rms(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // 3 + 160 + 4 = 167 words * 32bit 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket , //         .startofpacket	
+	
+
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+
+	//for cluster => will be in register map
+	input wire [7:0] 		CL_THRESHOLD,
+	input wire [7:0] 		CL_SIZE,
+	input wire [7:0]		IN_ALGO_THRESHOLD,
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest
+	
+);
+	//avalon source for header 
+	wire [31:0] header_data;
+	wire			header_ready;
+	wire [1:0]	header_empty;
+	wire			header_endofpacket;
+	wire			header_startofpacket;
+	wire			header_valid;
+	
+	//avalon source for channel data
+	wire [31:0] channel_data;
+	wire			channel_ready;
+	wire [1:0]	channel_empty;
+	wire			channel_endofpacket;
+	wire			channel_startofpacket;
+	wire			channel_valid;
+	
+	//avalon source for result
+	wire [31:0] recon_data;
+	wire			recon_ready;
+	wire [1:0]	recon_empty;
+	wire			recon_endofpacket;
+	wire			recon_startofpacket;
+	wire			recon_valid;
+	
+	/******************** merge three data source together *****************************************/
+	reg [1:0] avalon_sender_state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_HEADER = 2'd1;
+	localparam STATE_CHANNEL = 2'd3;
+	localparam STATE_RECON = 2'd2;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			avalon_sender_state <= STATE_IDLE;
+		end
+		else case(avalon_sender_state)
+		STATE_IDLE:
+		begin
+			if (header_startofpacket)
+				avalon_sender_state <= STATE_HEADER;
+		end
+		STATE_HEADER:
+		begin
+			if (channel_startofpacket)
+				avalon_sender_state <= STATE_CHANNEL;
+		end
+		STATE_CHANNEL:
+		begin
+			if (recon_startofpacket)
+				avalon_sender_state <= STATE_RECON;
+		end
+		STATE_RECON:
+		begin
+			if (recon_endofpacket && to_udp_ready)
+				avalon_sender_state <= STATE_IDLE;
+		end
+		default:
+			avalon_sender_state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	assign to_udp_data = (avalon_sender_state == STATE_HEADER)? header_data: (avalon_sender_state == STATE_CHANNEL)? channel_data: (avalon_sender_state == STATE_RECON)? recon_data: 32'd0;
+	assign header_ready = (avalon_sender_state == STATE_HEADER)? to_udp_ready: 1'b0;
+	assign channel_ready = (avalon_sender_state == STATE_CHANNEL)? to_udp_ready: 1'b0;
+	assign recon_ready = (avalon_sender_state == STATE_RECON)? to_udp_ready: 1'b0;
+	
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (avalon_sender_state == STATE_HEADER)? header_startofpacket: 1'b0;
+	assign to_udp_endofpacket = (avalon_sender_state == STATE_RECON)? recon_endofpacket: 1'b0;
+	assign to_udp_valid = (avalon_sender_state == STATE_HEADER)? header_valid: (avalon_sender_state == STATE_CHANNEL)? channel_valid: (avalon_sender_state == STATE_RECON)? recon_valid: 1'b0;
+	
+		
+	
+	
+	
+	
+	
+	
+	
+	
+	
+	wire [31:0] wire_data0;
+	wire 			wire_ready0;
+	wire			wire_valid0;
+	wire	[1:0] wire_empty0;
+	wire			wire_endofpacket0;
+	wire			wire_startofpacket0;
+	wire			bkg_sub_on;
+	
+	bkg_subtraction_pipe #(.BKG_FRAME(4)) bkg_subtraction0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(wire_data0),
+		.data_out_empty	(wire_empty0),
+		.data_out_endofpacket		(wire_endofpacket0),
+		.data_out_startofpacket		(wire_startofpacket0),
+		.data_out_ready	(wire_ready0),
+		.data_out_valid	(wire_valid0),
+		.bkg_sub_on			(bkg_sub_on),
+		
+		
+		//3 header
+		.to_udp_data (header_data),           
+		.to_udp_ready(header_ready),          
+		.to_udp_valid (header_valid),          
+		.to_udp_empty (header_empty),          
+		.to_udp_endofpacket (header_endofpacket),    
+		.to_udp_startofpacket (header_startofpacket)
+		
+		
+		
+	);
+	
+	
+	wire [15:0] wire_data1;
+	wire 			wire_ready1;
+	wire			wire_valid1;
+	wire	      wire_empty1;
+	wire			wire_endofpacket1;
+	wire			wire_startofpacket1;
+		
+	stl2sts stl2sts0(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data0),
+		.data_in_ready		(wire_ready0),
+		.data_in_valid		(wire_valid0),
+		.data_in_empty		(wire_empty0),
+		.data_in_startofpacket		(wire_startofpacket0),
+		.data_in_endofpacket			(wire_endofpacket0),
+		
+		.data_out_data		(wire_data1),
+		.data_out_empty	(wire_empty1),
+		.data_out_endofpacket		(wire_endofpacket1),
+		.data_out_startofpacket		(wire_startofpacket1),
+		.data_out_ready	(wire_ready1),
+		.data_out_valid	(wire_valid1)
+		
+	);
+	
+		//from st_splitter0 to cluster_locate
+		wire [15:0] wire_data2;
+		wire 			wire_ready2;
+		wire			wire_valid2;
+		wire	      wire_empty2;
+		wire			wire_endofpacket2;
+		wire			wire_startofpacket2;
+		
+		//from st_splitter0 to calibration
+		wire [15:0] wire_data3;
+		wire 			wire_ready3;
+		wire			wire_valid3;
+		wire	      wire_empty3;
+		wire			wire_endofpacket3;
+		wire			wire_startofpacket3;
+	
+	st_splitter16 st_splitter0 (
+		.st_splitter16_clk_clk            (clk),            //   st_splitter16_clk.clk
+		.st_splitter16_reset_reset        (rst),        // st_splitter16_reset.reset
+		
+		
+		.st_splitter16_in_ready           (wire_ready1),           //    st_splitter16_in.ready
+		.st_splitter16_in_valid           (wire_valid1),           //                    .valid
+		.st_splitter16_in_startofpacket   (wire_startofpacket1),   //                    .startofpacket
+		.st_splitter16_in_endofpacket     (wire_endofpacket1),     //                    .endofpacket
+		.st_splitter16_in_empty           (wire_empty1),           //                    .empty
+		.st_splitter16_in_data            (wire_data1),            //                    .data
+		
+		
+		.st_splitter16_out0_ready         (wire_ready2),         //  st_splitter16_out0.ready
+		.st_splitter16_out0_valid         (wire_valid2),         //                    .valid
+		.st_splitter16_out0_startofpacket (wire_startofpacket2), //                    .startofpacket
+		.st_splitter16_out0_endofpacket   (wire_endofpacket2),   //                    .endofpacket
+		.st_splitter16_out0_empty         (wire_empty2),         //                    .empty
+		.st_splitter16_out0_data          (wire_data2),          //                    .data
+		
+		
+		.st_splitter16_out1_ready         (wire_ready3),         //  st_splitter16_out1.ready
+		.st_splitter16_out1_valid         (wire_valid3),         //                    .valid
+		.st_splitter16_out1_startofpacket (wire_startofpacket3), //                    .startofpacket
+		.st_splitter16_out1_endofpacket   (wire_endofpacket3),   //                    .endofpacket
+		.st_splitter16_out1_empty         (wire_empty3),         //                    .empty
+		.st_splitter16_out1_data          (wire_data3)           //                    .data
+	);
+
+
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire has_cluster;
+	wire no_cluster;
+	
+	wire cl_last_channel;
+	cluster_locate cluster_locate0(
+		
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(wire_data2),
+		.data_in_ready		(wire_ready2),
+		.data_in_valid		(wire_valid2),
+		.data_in_empty		(wire_empty2),
+		.data_in_startofpacket		(wire_startofpacket2),
+		.data_in_endofpacket			(wire_endofpacket2),
+		
+		.THRESHOLD			({8'b0,CL_THRESHOLD}),
+		.SIZE					({1'b0,CL_SIZE}),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+	
+		.data_in_last		(cl_last_channel)
+	
+	); 
+	
+	
+	wire[8:0]		data_caled_address;
+	wire [31:0]		data_caled;
+	wire				data_caled_rd_enable;
+
+	
+	
+	calibration calibration0(
+	
+	.clk(clk),
+	.rst(rst),
+		
+	.data_in_data		(wire_data3),
+	.data_in_ready		(wire_ready3),
+	.data_in_valid		(wire_valid3),
+	.data_in_empty		(wire_empty3),
+	.data_in_startofpacket		(wire_startofpacket3),
+	.data_in_endofpacket			(wire_endofpacket3),
+	
+	.address		(address),
+	.clken		(clken),
+	.cali_fac	(cali_fac),
+	.waitrequest(waitrequest),
+	
+	.data_caled_address(data_caled_address),
+	.data_caled(data_caled),
+	.data_caled_rd_enable(data_caled_rd_enable),
+
+	.to_udp_data (channel_data),           
+	.to_udp_ready(channel_ready),          
+	.to_udp_valid (channel_valid),          
+	.to_udp_empty (channel_empty),          
+	.to_udp_endofpacket (channel_endofpacket),    
+	.to_udp_startofpacket (channel_startofpacket)
+
+	);
+
+	
+	rms rms0(
+
+
+		.clk(clk),
+		.rst(rst),
+
+		.bkg_sub_on			(bkg_sub_on),
+		.sig_ram_last		(cl_last_channel),
+
+		.sig_rdaddress(data_caled_address),            
+		.sig(data_caled),
+		.sig_rd_eable(data_caled_rd_enable),
+
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster),
+
+		.to_udp_data (recon_data),           
+		.to_udp_ready(recon_ready),          
+		.to_udp_valid (recon_valid),          
+		.to_udp_empty (recon_empty),          
+		.to_udp_endofpacket (recon_endofpacket),    
+		.to_udp_startofpacket (recon_startofpacket)
+
+
+	);
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
new file mode 100644
index 0000000..c244a3f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv
@@ -0,0 +1,422 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $File: //acds/main/ip/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter.sv $
+// $Revision: #3 $
+// $Date: 2012/01/18 $
+// $Author: pscheidt $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_splitter #(
+   parameter 
+      NUMBER_OF_OUTPUTS  = 2, 
+      QUALIFY_VALID_OUT  = 1, 
+      DATA_WIDTH         = 8,
+      BITS_PER_SYMBOL    = 8,
+      USE_PACKETS        = 0,   
+      CHANNEL_WIDTH      = 1,	   
+      ERROR_WIDTH        = 1,
+      EMPTY_WIDTH        = 1
+  )
+(
+   output wire                    in0_ready,
+   input  wire                    in0_valid,
+   input  wire  [DATA_WIDTH-1 :0] in0_data,
+   input  wire  [CHANNEL_WIDTH-1 :0] in0_channel,
+   input  wire  [ERROR_WIDTH-1   :0] in0_error,
+   input  wire                    in0_startofpacket,
+   input  wire                    in0_endofpacket,
+   input  wire  [EMPTY_WIDTH-1   :0] in0_empty,
+   
+   input  wire                    out0_ready,
+   output wire                    out0_valid,
+   output wire  [DATA_WIDTH-1 :0] out0_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out0_channel,
+   output wire  [ERROR_WIDTH-1   :0] out0_error,
+   output wire                    out0_startofpacket,
+   output wire                    out0_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out0_empty,
+   
+   input  wire                    out1_ready,
+   output wire                    out1_valid,
+   output wire  [DATA_WIDTH-1 :0] out1_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out1_channel,
+   output wire  [ERROR_WIDTH-1   :0] out1_error,
+   output wire                    out1_startofpacket,
+   output wire                    out1_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out1_empty,
+   
+   input  wire                    out2_ready,
+   output wire                    out2_valid,
+   output wire  [DATA_WIDTH-1 :0] out2_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out2_channel,
+   output wire  [ERROR_WIDTH-1   :0] out2_error,
+   output wire                    out2_startofpacket,
+   output wire                    out2_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out2_empty,
+   
+   input  wire                    out3_ready,
+   output wire                    out3_valid,
+   output wire  [DATA_WIDTH-1 :0] out3_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out3_channel,
+   output wire  [ERROR_WIDTH-1   :0] out3_error,
+   output wire                    out3_startofpacket,
+   output wire                    out3_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out3_empty,
+   
+   input  wire                    out4_ready,
+   output wire                    out4_valid,
+   output wire  [DATA_WIDTH-1 :0] out4_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out4_channel,
+   output wire  [ERROR_WIDTH-1   :0] out4_error,
+   output wire                    out4_startofpacket,
+   output wire                    out4_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out4_empty,
+   
+   input  wire                    out5_ready,
+   output wire                    out5_valid,
+   output wire  [DATA_WIDTH-1 :0] out5_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out5_channel,
+   output wire  [ERROR_WIDTH-1   :0] out5_error,
+   output wire                    out5_startofpacket,
+   output wire                    out5_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out5_empty,
+   
+   input  wire                    out6_ready,
+   output wire                    out6_valid,
+   output wire  [DATA_WIDTH-1 :0] out6_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out6_channel,
+   output wire  [ERROR_WIDTH-1   :0] out6_error,
+   output wire                    out6_startofpacket,
+   output wire                    out6_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out6_empty,
+   
+   input  wire                    out7_ready,
+   output wire                    out7_valid,
+   output wire  [DATA_WIDTH-1 :0] out7_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out7_channel,
+   output wire  [ERROR_WIDTH-1   :0] out7_error,
+   output wire                    out7_startofpacket,
+   output wire                    out7_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out7_empty,
+   
+   input  wire                    out8_ready,
+   output wire                    out8_valid,
+   output wire  [DATA_WIDTH-1 :0] out8_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out8_channel,
+   output wire  [ERROR_WIDTH-1   :0] out8_error,
+   output wire                    out8_startofpacket,
+   output wire                    out8_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out8_empty,
+   
+   input  wire                    out9_ready,
+   output wire                    out9_valid,
+   output wire  [DATA_WIDTH-1 :0] out9_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out9_channel,
+   output wire  [ERROR_WIDTH-1   :0] out9_error,
+   output wire                    out9_startofpacket,
+   output wire                    out9_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out9_empty,
+   
+   input  wire                    out10_ready,
+   output wire                    out10_valid,
+   output wire  [DATA_WIDTH-1 :0] out10_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out10_channel,
+   output wire  [ERROR_WIDTH-1   :0] out10_error,
+   output wire                    out10_startofpacket,
+   output wire                    out10_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out10_empty,
+   
+   input  wire                    out11_ready,
+   output wire                    out11_valid,
+   output wire  [DATA_WIDTH-1 :0] out11_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out11_channel,
+   output wire  [ERROR_WIDTH-1   :0] out11_error,
+   output wire                    out11_startofpacket,
+   output wire                    out11_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out11_empty,
+   
+   input  wire                    out12_ready,
+   output wire                    out12_valid,
+   output wire  [DATA_WIDTH-1 :0] out12_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out12_channel,
+   output wire  [ERROR_WIDTH-1   :0] out12_error,
+   output wire                    out12_startofpacket,
+   output wire                    out12_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out12_empty,
+   
+   input  wire                    out13_ready,
+   output wire                    out13_valid,
+   output wire  [DATA_WIDTH-1 :0] out13_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out13_channel,
+   output wire  [ERROR_WIDTH-1   :0] out13_error,
+   output wire                    out13_startofpacket,
+   output wire                    out13_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out13_empty,
+   
+   input  wire                    out14_ready,
+   output wire                    out14_valid,
+   output wire  [DATA_WIDTH-1 :0] out14_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out14_channel,
+   output wire  [ERROR_WIDTH-1   :0] out14_error,
+   output wire                    out14_startofpacket,
+   output wire                    out14_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out14_empty,
+   
+   input  wire                    out15_ready,
+   output wire                    out15_valid,
+   output wire  [DATA_WIDTH-1 :0] out15_data,
+   output wire  [CHANNEL_WIDTH-1 :0] out15_channel,
+   output wire  [ERROR_WIDTH-1   :0] out15_error,
+   output wire                    out15_startofpacket,
+   output wire                    out15_endofpacket,
+   output wire  [EMPTY_WIDTH-1   :0] out15_empty,
+   
+   input  wire                    clk,
+   input  wire                    reset
+);
+
+
+// ********************************************************************
+// Module Wiring
+
+wire   [15:0]            OutReady;
+wire   [15:0]            OutValid;
+wire   [DATA_WIDTH-1 :0] OutData    [15:0];
+wire   [CHANNEL_WIDTH-1 :0] OutChannel [15:0];
+wire   [ERROR_WIDTH-1   :0] OutError   [15:0];
+wire   [15:0]            OutSOP;
+wire   [15:0]            OutEOP;
+wire   [EMPTY_WIDTH-1   :0] OutEmpty   [15:0];
+
+genvar                   i, j;
+
+
+// ********************************************************************
+// Module Logic
+
+assign in0_ready = &(OutReady[NUMBER_OF_OUTPUTS-1:0]);
+
+
+generate
+   for (i=0; i < NUMBER_OF_OUTPUTS; i=i+1) begin : SPLIT_PORT
+      assign OutData[i]    = in0_data;
+      assign OutChannel[i] = in0_channel;
+      assign OutError[i]   = in0_error;
+      assign OutSOP[i]     = in0_startofpacket;
+      assign OutEOP[i]     = in0_endofpacket;
+      assign OutEmpty[i]   = in0_empty;
+   end
+endgenerate
+
+
+generate
+   for (j=NUMBER_OF_OUTPUTS; j <16; j=j+1) begin : NULL_PORT
+      assign OutData[j]    = {DATA_WIDTH{1'b0}};
+      assign OutChannel[j] = {CHANNEL_WIDTH{1'b0}};
+      assign OutError[j]   = {ERROR_WIDTH{1'b0}};
+      assign OutSOP[j]     = 1'b0;
+      assign OutEOP[j]     = 1'b0;
+      assign OutEmpty[j]   = {EMPTY_WIDTH{1'b0}};
+   end
+endgenerate
+
+
+generate
+   if (QUALIFY_VALID_OUT) begin
+      assign OutValid[0]  = &{in0_valid, OutReady[15:1]};
+      assign OutValid[1]  = &{in0_valid, OutReady[15:2],  OutReady[0]};
+      assign OutValid[2]  = &{in0_valid, OutReady[15:3],  OutReady[1:0]};
+      assign OutValid[3]  = &{in0_valid, OutReady[15:4],  OutReady[2:0]};
+      assign OutValid[4]  = &{in0_valid, OutReady[15:5],  OutReady[3:0]};
+      assign OutValid[5]  = &{in0_valid, OutReady[15:6],  OutReady[4:0]};
+      assign OutValid[6]  = &{in0_valid, OutReady[15:7],  OutReady[5:0]};
+      assign OutValid[7]  = &{in0_valid, OutReady[15:8],  OutReady[6:0]};
+      assign OutValid[8]  = &{in0_valid, OutReady[15:9],  OutReady[7:0]};
+      assign OutValid[9]  = &{in0_valid, OutReady[15:10], OutReady[8:0]};
+      assign OutValid[10] = &{in0_valid, OutReady[15:11], OutReady[9:0]};
+      assign OutValid[11] = &{in0_valid, OutReady[15:12], OutReady[10:0]};
+      assign OutValid[12] = &{in0_valid, OutReady[15:13], OutReady[11:0]};
+      assign OutValid[13] = &{in0_valid, OutReady[15:14], OutReady[12:0]};
+      assign OutValid[14] = &{in0_valid, OutReady[15],    OutReady[13:0]};
+      assign OutValid[15] = &{in0_valid,                  OutReady[14:0]};
+   end
+   else begin
+      assign OutValid[0]  = in0_valid;
+      assign OutValid[1]  = in0_valid;
+      assign OutValid[2]  = in0_valid;
+      assign OutValid[3]  = in0_valid;
+      assign OutValid[4]  = in0_valid;
+      assign OutValid[5]  = in0_valid;
+      assign OutValid[6]  = in0_valid;
+      assign OutValid[7]  = in0_valid;
+      assign OutValid[8]  = in0_valid;
+      assign OutValid[9]  = in0_valid;
+      assign OutValid[10] = in0_valid;
+      assign OutValid[11] = in0_valid;
+      assign OutValid[12] = in0_valid;
+      assign OutValid[13] = in0_valid;
+      assign OutValid[14] = in0_valid;
+      assign OutValid[15] = in0_valid;
+   end
+endgenerate
+
+
+assign OutReady[0]        = out0_ready;
+assign out0_valid         = OutValid[0];
+assign out0_data          = OutData[0];
+assign out0_channel       = OutChannel[0];
+assign out0_error         = OutError[0];
+assign out0_startofpacket = OutSOP[0];
+assign out0_endofpacket   = OutEOP[0];
+assign out0_empty         = OutEmpty[0];
+
+assign OutReady[1]        = out1_ready;
+assign out1_valid         = OutValid[1];
+assign out1_data          = OutData[1];
+assign out1_channel       = OutChannel[1];
+assign out1_error         = OutError[1];
+assign out1_startofpacket = OutSOP[1];
+assign out1_endofpacket   = OutEOP[1];
+assign out1_empty         = OutEmpty[1];
+
+assign OutReady[2]        = out2_ready;
+assign out2_valid         = OutValid[2];
+assign out2_data          = OutData[2];
+assign out2_channel       = OutChannel[2];
+assign out2_error         = OutError[2];
+assign out2_startofpacket = OutSOP[2];
+assign out2_endofpacket   = OutEOP[2];
+assign out2_empty         = OutEmpty[2];
+
+assign OutReady[3]        = out3_ready;
+assign out3_valid         = OutValid[3];
+assign out3_data          = OutData[3];
+assign out3_channel       = OutChannel[3];
+assign out3_error         = OutError[3];
+assign out3_startofpacket = OutSOP[3];
+assign out3_endofpacket   = OutEOP[3];
+assign out3_empty         = OutEmpty[3];
+
+assign OutReady[4]        = out4_ready;
+assign out4_valid         = OutValid[4];
+assign out4_data          = OutData[4];
+assign out4_channel       = OutChannel[4];
+assign out4_error         = OutError[4];
+assign out4_startofpacket = OutSOP[4];
+assign out4_endofpacket   = OutEOP[4];
+assign out4_empty         = OutEmpty[4];
+
+assign OutReady[5]        = out5_ready;
+assign out5_valid         = OutValid[5];
+assign out5_data          = OutData[5];
+assign out5_channel       = OutChannel[5];
+assign out5_error         = OutError[5];
+assign out5_startofpacket = OutSOP[5];
+assign out5_endofpacket   = OutEOP[5];
+assign out5_empty         = OutEmpty[5];
+
+assign OutReady[6]        = out6_ready;
+assign out6_valid         = OutValid[6];
+assign out6_data          = OutData[6];
+assign out6_channel       = OutChannel[6];
+assign out6_error         = OutError[6];
+assign out6_startofpacket = OutSOP[6];
+assign out6_endofpacket   = OutEOP[6];
+assign out6_empty         = OutEmpty[6];
+
+assign OutReady[7]        = out7_ready;
+assign out7_valid         = OutValid[7];
+assign out7_data          = OutData[7];
+assign out7_channel       = OutChannel[7];
+assign out7_error         = OutError[7];
+assign out7_startofpacket = OutSOP[7];
+assign out7_endofpacket   = OutEOP[7];
+assign out7_empty         = OutEmpty[7];
+
+assign OutReady[8]        = out8_ready;
+assign out8_valid         = OutValid[8];
+assign out8_data          = OutData[8];
+assign out8_channel       = OutChannel[8];
+assign out8_error         = OutError[8];
+assign out8_startofpacket = OutSOP[8];
+assign out8_endofpacket   = OutEOP[8];
+assign out8_empty         = OutEmpty[8];
+
+assign OutReady[9]        = out9_ready;
+assign out9_valid         = OutValid[9];
+assign out9_data          = OutData[9];
+assign out9_channel       = OutChannel[9];
+assign out9_error         = OutError[9];
+assign out9_startofpacket = OutSOP[9];
+assign out9_endofpacket   = OutEOP[9];
+assign out9_empty         = OutEmpty[9];
+
+assign OutReady[10]        = out10_ready;
+assign out10_valid         = OutValid[10];
+assign out10_data          = OutData[10];
+assign out10_channel       = OutChannel[10];
+assign out10_error         = OutError[10];
+assign out10_startofpacket = OutSOP[10];
+assign out10_endofpacket   = OutEOP[10];
+assign out10_empty         = OutEmpty[10];
+
+assign OutReady[11]        = out11_ready;
+assign out11_valid         = OutValid[11];
+assign out11_data          = OutData[11];
+assign out11_channel       = OutChannel[11];
+assign out11_error         = OutError[11];
+assign out11_startofpacket = OutSOP[11];
+assign out11_endofpacket   = OutEOP[11];
+assign out11_empty         = OutEmpty[11];
+
+assign OutReady[12]        = out12_ready;
+assign out12_valid         = OutValid[12];
+assign out12_data          = OutData[12];
+assign out12_channel       = OutChannel[12];
+assign out12_error         = OutError[12];
+assign out12_startofpacket = OutSOP[12];
+assign out12_endofpacket   = OutEOP[12];
+assign out12_empty         = OutEmpty[12];
+
+assign OutReady[13]        = out13_ready;
+assign out13_valid         = OutValid[13];
+assign out13_data          = OutData[13];
+assign out13_channel       = OutChannel[13];
+assign out13_error         = OutError[13];
+assign out13_startofpacket = OutSOP[13];
+assign out13_endofpacket   = OutEOP[13];
+assign out13_empty         = OutEmpty[13];
+
+assign OutReady[14]        = out14_ready;
+assign out14_valid         = OutValid[14];
+assign out14_data          = OutData[14];
+assign out14_channel       = OutChannel[14];
+assign out14_error         = OutError[14];
+assign out14_startofpacket = OutSOP[14];
+assign out14_endofpacket   = OutEOP[14];
+assign out14_empty         = OutEmpty[14];
+
+assign OutReady[15]        = out15_ready;
+assign out15_valid         = OutValid[15];
+assign out15_data          = OutData[15];
+assign out15_channel       = OutChannel[15];
+assign out15_error         = OutError[15];
+assign out15_startofpacket = OutSOP[15];
+assign out15_endofpacket   = OutEOP[15];
+assign out15_empty         = OutEmpty[15];
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_master_translator.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
new file mode 100644
index 0000000..2b0d90b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_master_translator.sv
@@ -0,0 +1,556 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts an Avalon-MM master interface into an 
+// Avalon-MM "universal" master interface.
+//
+// The universal interface is defined as the superset of ports
+// and parameters that can represent any legal Avalon 
+// interface.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_translator #(
+   parameter
+      // widths
+      AV_ADDRESS_W                = 32,
+      AV_DATA_W                   = 32,
+      AV_BURSTCOUNT_W             = 4,
+      AV_BYTEENABLE_W             = 4,
+
+      UAV_ADDRESS_W               = 38,
+      UAV_BURSTCOUNT_W            = 10,
+  
+      // optional ports
+      USE_BURSTCOUNT              = 1,
+      USE_BEGINBURSTTRANSFER      = 0,
+      USE_BEGINTRANSFER           = 0,
+      USE_CHIPSELECT              = 0,
+      USE_READ                    = 1,
+      USE_READDATAVALID           = 1,
+      USE_WRITE                   = 1,
+      USE_WAITREQUEST             = 1,
+      USE_WRITERESPONSE           = 0,
+      USE_READRESPONSE            = 0,
+   
+      AV_REGISTERINCOMINGSIGNALS  = 0,
+      AV_SYMBOLS_PER_WORD         = 4,
+      AV_ADDRESS_SYMBOLS          = 0,
+      // must be enabled for a bursting master
+      AV_CONSTANT_BURST_BEHAVIOR  = 1,
+      UAV_CONSTANT_BURST_BEHAVIOR = 0,
+      AV_BURSTCOUNT_SYMBOLS       = 0,
+      AV_LINEWRAPBURSTS           = 0
+)(
+   input wire                           clk,
+   input wire                           reset,
+
+   // Universal Avalon Master
+   output reg                           uav_write,
+   output reg                           uav_read,
+   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
+   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+   output wire [AV_DATA_W -1 : 0]       uav_writedata,
+   output wire                          uav_lock,
+   output wire                          uav_debugaccess,
+   output wire                          uav_clken,
+
+   input wire [AV_DATA_W -1 : 0]        uav_readdata,
+   input wire                           uav_readdatavalid,
+   input wire                           uav_waitrequest,
+   input wire [1 : 0]                   uav_response,
+   input wire                           uav_writeresponsevalid,
+
+   // Avalon-MM Anti-master (slave)
+   input reg                            av_write,
+   input reg                            av_read,
+   input wire [AV_ADDRESS_W -1 : 0]     av_address,
+   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
+   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
+   input wire [AV_DATA_W -1 : 0]        av_writedata,
+   input wire                           av_begintransfer,
+   input wire                           av_beginbursttransfer,
+   input wire                           av_lock,
+   input wire                           av_chipselect,
+   input wire                           av_debugaccess,
+   input wire                           av_clken,
+
+   output wire [AV_DATA_W -1 : 0]       av_readdata,
+   output wire                          av_readdatavalid,
+   output reg                           av_waitrequest,
+   output reg [1 : 0]                   av_response,
+   output reg                           av_writeresponsevalid
+);
+
+   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
+   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
+   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
+   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
+   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
+
+   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
+   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
+
+   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
+   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
+
+   function integer flog2;
+      input [31:0]  depth;
+      integer       i;
+      begin
+         i = depth;
+         if ( i <= 0 ) flog2 = 0;
+         else begin
+            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
+               i = i >> 1;
+         end
+      end
+   endfunction // flog2
+
+    // ------------------------------------------------------------
+    // Calculates the ceil(log2()) of the input val.
+    //
+    // Limited to a positive 32-bit input value.
+    // ------------------------------------------------------------
+    function integer clog2;
+        input[31:0] val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            clog2 = 0;
+
+            while (i < val) begin
+                clog2 = clog2 + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+   function integer pow2;
+      input [31:0] toShift;
+      begin
+         pow2 = 1;
+         pow2 = pow2 << toShift;
+      end
+   endfunction // pow2
+
+   // -------------------------------------------------
+   // Assign some constants to appropriately-sized signals to
+   // avoid synthesis warnings. This also helps some simulators
+   // with their inferred sensitivity lists.
+   //
+   // The symbols per word calculation here rounds non-power of two
+   // symbols to the next highest power of two, which is what we want
+   // when calculating the decrementing byte count.
+   // -------------------------------------------------
+   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
+   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
+
+   reg                            internal_beginbursttransfer;
+   reg                            internal_begintransfer;
+   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
+   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
+
+   reg uav_read_pre;
+   reg uav_write_pre;
+   reg read_accepted;
+
+   // -------------------------------------------------
+   // Pass through signals that we don't touch
+   // -------------------------------------------------
+   assign uav_writedata    = av_writedata;
+   assign uav_byteenable   = av_byteenable;
+   assign uav_lock         = av_lock;
+   assign uav_debugaccess  = av_debugaccess;
+   assign uav_clken        = av_clken;
+
+   assign av_readdata      = uav_readdata;
+   assign av_readdatavalid = uav_readdatavalid;
+
+   // -------------------------------------------------
+   // Response signals
+   // -------------------------------------------------
+   always_comb begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
+         av_response = '0;
+      else
+         av_response = uav_response;
+
+      if (USE_WRITERESPONSE) begin
+         av_writeresponsevalid = uav_writeresponsevalid;
+      end else begin
+         av_writeresponsevalid = '0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert byte and word addresses into byte addresses
+   // -------------------------------------------------
+   always_comb begin
+      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
+
+      if (AV_ADDRESS_SYMBOLS)
+         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      else begin
+         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert burstcount into symbol units
+   // -------------------------------------------------
+   always_comb begin
+      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
+
+      if (USE_BURSTCOUNT) begin
+         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
+         if (AV_BURSTCOUNT_SYMBOLS)
+            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         else begin
+            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // This is where we perform the per-transfer address and burstcount 
+   // calculations that are required by downstream modules.
+   // -------------------------------------------------
+   reg [UAV_ADDRESS_W -1 : 0] address_register;
+   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
+   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
+
+   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
+
+   always_comb begin
+      uav_address = uav_address_pre;
+      uav_burstcount = uav_burstcount_pre;
+
+      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+         uav_address = address_register;
+         uav_burstcount = burstcount_register;
+      end
+   end
+
+   reg first_burst_stalled;
+   reg burst_stalled;
+
+   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
+   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
+
+   generate
+      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
+         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+         end
+         else begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+         end
+      end
+      else begin
+         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         address_register <= '0;
+         burstcount_register_lint <= '0;
+      end else begin
+         address_register <= address_register;
+         burstcount_register_lint <= burstcount_register_lint;
+
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               address_register <= uav_address_pre;
+               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
+            end else begin
+               address_register <= combi_burst_addr_reg;
+               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               address_register <= combi_addr_reg;
+               burstcount_register_lint <= burstcount_register - symbols_per_word;
+            end
+         end
+      end
+   end
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         first_burst_stalled <= 1'b0;
+         burst_stalled <= 1'b0;
+      end else begin
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               first_burst_stalled <= 1'b1;
+            end else begin
+               first_burst_stalled <= 1'b0;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               burst_stalled <= 1'b0;
+            end else begin
+               burst_stalled <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // Waitrequest translation
+   // -------------------------------------------------
+   always @(posedge clk, posedge reset) begin
+      if (reset)
+         read_accepted <= 1'b0;
+      else begin
+         read_accepted <= read_accepted;
+         if (read_accepted == 0)
+            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
+            read_accepted <= 1'b0;
+      end
+
+   end
+
+   reg write_accepted = 0;
+   generate if (AV_REGISTERINCOMINGSIGNALS) begin
+      always @(posedge clk, posedge reset) begin
+         if (reset)
+            write_accepted <= 1'b0;
+         else begin
+            write_accepted <=
+            ~av_waitrequest ? 1'b0 :
+            uav_write & ~uav_waitrequest? 1'b1 :
+            write_accepted;
+         end
+      end
+   end endgenerate
+
+   always_comb begin
+      av_waitrequest = uav_waitrequest;
+
+      if (USE_READDATAVALID == 0) begin
+         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+      end
+
+      if (AV_REGISTERINCOMINGSIGNALS) begin
+         av_waitrequest =
+            uav_read_pre ? ~uav_readdatavalid :
+            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+            1'b1;
+      end
+
+      if (USE_WAITREQUEST == 0) begin
+         av_waitrequest = 0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Determine the output read and write signals from 
+   // the read/write/chipselect input signals.
+   // -------------------------------------------------
+   always_comb begin
+      uav_write      =  1'b0;
+      uav_write_pre  =  1'b0;
+      uav_read       =  1'b0;
+      uav_read_pre   =  1'b0;
+
+      if (!USE_CHIPSELECT) begin
+         if (USE_READ) begin
+            uav_read_pre = av_read;
+         end
+     
+         if (USE_WRITE) begin
+            uav_write_pre = av_write;
+         end
+      end else begin
+         if (!USE_WRITE && USE_READ) begin
+            uav_write_pre = av_chipselect & ~av_read;
+            uav_read_pre = av_read;
+         end else if (!USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_chipselect & ~av_write;
+         end else if (USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_read;
+         end
+      end
+
+      if (USE_READDATAVALID == 0)
+         uav_read = uav_read_pre & ~read_accepted;
+      else
+         uav_read = uav_read_pre;
+
+      if (AV_REGISTERINCOMINGSIGNALS == 0)
+         uav_write = uav_write_pre;
+      else
+         uav_write = uav_write_pre & ~write_accepted;
+   end
+
+   // -------------------------------------------------
+   // Begintransfer assignment
+   // -------------------------------------------------
+   reg end_begintransfer;
+
+   always_comb begin
+      if (USE_BEGINTRANSFER) begin
+         internal_begintransfer = av_begintransfer;
+      end else begin
+         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if (internal_begintransfer == 1 && uav_waitrequest)
+            end_begintransfer <= 1'b1;
+         else if (uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Beginbursttransfer assignment
+   // -------------------------------------------------
+   reg   end_beginbursttransfer;
+   wire  last_burst_transfer_pre;
+   wire  last_burst_transfer_reg;
+   wire  last_burst_transfer;
+
+   // compare values before the mux to shorten critical path; benchmark before changing
+   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+   always_comb begin
+      if (USE_BEGINBURSTTRANSFER) begin
+         internal_beginbursttransfer = av_beginbursttransfer;
+      end else begin
+         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_beginbursttransfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= end_beginbursttransfer;
+         if (last_burst_transfer && internal_begintransfer || uav_read) begin
+            end_beginbursttransfer <= 1'b0;
+         end
+         else if (uav_write && internal_begintransfer) begin
+            end_beginbursttransfer <= 1'b1;
+         end
+      end
+   end
+
+   // synthesis translate_off
+
+   // ------------------------------------------------
+   // check_1   : for waitrequest signal violation
+   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
+   // Exception : begintransfer / beginbursttransfer
+   //           : previously not in any transaction (idle)
+   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
+   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
+   // ------------------------------------------------
+
+   reg av_waitrequest_r;
+   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
+   reg [AV_ADDRESS_W-1:0]    av_address_r;
+   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
+   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
+   reg [AV_DATA_W-1:0]       av_writedata_r;
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         av_waitrequest_r           <= '0;
+         av_write_r                 <= '0;
+         av_read_r                  <= '0;
+         av_lock_r                  <= '0;
+         av_chipselect_r            <= '0;
+         av_debugaccess_r           <= '0;
+         av_address_r               <= '0;
+         av_byteenable_r            <= '0;
+         av_burstcount_r            <= '0;
+         av_writedata_r             <= '0;
+      end else begin
+         av_waitrequest_r           <= av_waitrequest;
+         av_write_r                 <= av_write;
+         av_read_r                  <= av_read;
+         av_lock_r                  <= av_lock;
+         av_chipselect_r            <= av_chipselect;
+         av_debugaccess_r           <= av_debugaccess;
+         av_address_r               <= av_address;
+         av_byteenable_r            <= av_byteenable;
+         av_burstcount_r            <= av_burstcount;
+         av_writedata_r             <= av_writedata;
+   
+         if (
+            av_waitrequest_r && // When waitrequest is asserted
+            (
+               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
+               (av_read                   != av_read_r)  ||
+               (av_lock                   != av_lock_r)  ||
+               (av_debugaccess            != av_debugaccess_r) ||
+               (av_address                != av_address_r) ||
+               (av_byteenable             != av_byteenable_r) ||
+               (av_burstcount             != av_burstcount_r)
+            )  &&
+            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
+            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
+         ) begin
+            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
+            $display("av_address                %x --> %x", av_address_r               , av_address               );
+            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
+            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
+            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
+            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
+            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
+            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
+            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
+            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
+         end
+      end
+   
+   // end check_1
+   
+   end
+
+  // synthesis translate_on
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
new file mode 100644
index 0000000..2e65068
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv
@@ -0,0 +1,482 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon  MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator #(
+   parameter
+   //Widths
+   AV_ADDRESS_W           = 32,
+   AV_DATA_W              = 32,
+   AV_BURSTCOUNT_W        = 4,
+   AV_BYTEENABLE_W        = 4,
+   UAV_BYTEENABLE_W       = 4,
+
+   //Read Latency
+   AV_READLATENCY          = 1,
+
+   //Timing
+   AV_READ_WAIT_CYCLES     = 0,
+   AV_WRITE_WAIT_CYCLES    = 0,
+   AV_SETUP_WAIT_CYCLES    = 0,
+   AV_DATA_HOLD_CYCLES     = 0,
+
+   //Optional Port Declarations
+   USE_READDATAVALID       = 1,
+   USE_WAITREQUEST         = 1,
+   USE_READRESPONSE        = 0,
+   USE_WRITERESPONSE       = 0,
+
+   //Variable Addressing
+   AV_SYMBOLS_PER_WORD     = 4,
+   AV_ADDRESS_SYMBOLS      = 0,
+   AV_BURSTCOUNT_SYMBOLS   = 0,
+   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
+   UAV_ADDRESS_W           = 38,
+   UAV_BURSTCOUNT_W        = 10,
+   UAV_DATA_W              = 32,
+
+   AV_CONSTANT_BURST_BEHAVIOR       = 0,
+   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
+   CHIPSELECT_THROUGH_READLATENCY   = 0,
+
+   // Tightly-Coupled Options
+   USE_UAV_CLKEN           = 0,
+   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+) (
+
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input wire                             clk,
+   input wire                             reset,
+
+   // -------------------
+   // Universal Avalon Slave
+   // -------------------
+
+   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
+   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
+   input wire                             uav_write,
+   input wire                             uav_read,
+   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
+   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
+   input wire                             uav_lock,
+   input wire                             uav_debugaccess,
+   input wire                             uav_clken,
+
+   output logic                           uav_readdatavalid,
+   output logic                           uav_waitrequest,
+   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
+   output logic [1:0]                     uav_response,
+   // input wire                             uav_writeresponserequest,
+   output logic                           uav_writeresponsevalid,
+
+   // -------------------
+   // Customizable Avalon Master
+   // -------------------
+   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
+   output logic [AV_DATA_W - 1 : 0]       av_writedata,
+   output logic                           av_write,
+   output logic                           av_read,
+   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+   output logic                           av_begintransfer,
+   output wire                            av_chipselect,
+   output logic                           av_beginbursttransfer,
+   output logic                           av_lock,
+   output wire                            av_clken,
+   output wire                            av_debugaccess,
+   output wire                            av_outputenable,
+
+   input logic [AV_DATA_W - 1 : 0]        av_readdata,
+   input logic                            av_readdatavalid,
+   input logic                            av_waitrequest,
+
+   input logic [1:0]                      av_response,
+   // output logic                           av_writeresponserequest,
+   input wire                             av_writeresponsevalid
+
+);
+
+   function integer clog2_plusone;
+      input [31:0] Depth;
+      integer i;
+      begin
+         i = Depth;
+         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
+            i = i >> 1;
+      end
+   endfunction
+
+   function integer max;
+      //returns the larger of two passed arguments
+      input [31:0] one;
+      input [31:0] two;
+      if(one > two)
+         max=one;
+      else
+         max=two;
+   endfunction // int
+
+   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
+   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+                                          AV_ADDRESS_W :
+                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+                                          AV_BURSTCOUNT_W :
+                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+   // Calculate the symbols per word as the power of 2 extended symbols per word
+   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
+
+   // +--------------------------------
+   // |Backwards Compatibility Signals
+   // +--------------------------------
+   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+   assign av_debugaccess = uav_debugaccess;
+
+   // +-------------------
+   // |Passthru Signals
+   // +-------------------
+
+   reg [1 : 0] av_response_delayed;
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         av_response_delayed <= 2'b0;
+      end else begin
+         av_response_delayed <= av_response;
+      end
+   end
+
+   always_comb
+   begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
+         uav_response = '0;
+      end else begin
+         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
+            uav_response = av_response;
+         end else begin
+            uav_response = av_response_delayed;
+         end
+      end
+   end
+   // assign av_writeresponserequest = uav_writeresponserequest;
+   assign uav_writeresponsevalid = av_writeresponsevalid;
+
+   //-------------------------
+   //Writedata and Byteenable
+   //-------------------------
+
+   always@* begin
+      av_byteenable = '0;
+      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   always@* begin
+      av_writedata = '0;
+      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+   end
+
+   // +-------------------
+   // |Calculated Signals
+   // +-------------------
+
+   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+         if(byteenable[i] == 1) begin
+            return i;
+         end
+      end
+
+      return '0;
+
+   endfunction
+
+   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
+   always@(posedge clk, posedge reset) begin
+      if(reset) begin
+         burstcount_reg <= '0;
+         address_reg    <= '0;
+      end else begin
+         burstcount_reg <= burstcount_reg;
+         address_reg    <= address_reg;
+         if(av_beginbursttransfer) begin
+            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+         end
+      end
+   end
+
+   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+   always@* begin
+      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+         temp_wire = decode_byteenable(uav_byteenable);
+         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+      end else begin
+         real_uav_address = uav_address;
+      end
+
+      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_address = address_reg;
+   end
+
+   always@* begin
+      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_burstcount = burstcount_reg;
+   end
+
+   always@* begin
+      av_lock = uav_lock;
+   end
+
+   // -------------------
+   // Writebyteenable Assignment
+   // -------------------
+   always@* begin
+      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   // -------------------
+   // Waitrequest Assignment
+   // -------------------
+
+   reg av_waitrequest_generated;
+   reg av_waitrequest_generated_read;
+   reg av_waitrequest_generated_write;
+   reg waitrequest_reset_override;
+   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         wait_latency_counter <= '0;
+         waitrequest_reset_override <= 1'h1;
+      end else begin
+         waitrequest_reset_override <= 1'h0;
+         wait_latency_counter <= '0;
+         if( ~uav_waitrequest | waitrequest_reset_override )
+            wait_latency_counter <= '0;
+         else if( uav_read | uav_write )
+            wait_latency_counter <= wait_latency_counter + 1'h1;
+      end
+   end
+
+
+   always @* begin
+
+      av_read  = uav_read;
+      av_write = uav_write;
+      av_waitrequest_generated         = 1'h1;
+      av_waitrequest_generated_read    = 1'h1;
+      av_waitrequest_generated_write   = 1'h1;
+
+      if(LOG2_OF_LATENCY_SUM == 1)
+         av_waitrequest_generated = 0;
+
+      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+         if(uav_write)
+            av_waitrequest_generated = av_waitrequest_generated_write;
+         else
+            av_waitrequest_generated = av_waitrequest_generated_read;
+
+      end
+
+      if(USE_WAITREQUEST) begin
+         uav_waitrequest = av_waitrequest;
+      end else begin
+         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+      end
+
+   end
+
+   // --------------
+   // Readdata Assignment
+   // --------------
+
+   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+   always@(posedge clk, posedge reset) begin
+      if(reset)
+         av_readdata_pre <= 'b0;
+      else
+         av_readdata_pre <= av_readdata;
+   end
+
+   always@* begin
+      uav_readdata = {UAV_DATA_W{1'b0}};
+      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata;
+      end else begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
+      end
+   end
+   
+   // -------------------
+   // Readdatavalid Assigment
+   // -------------------
+   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+   reg top_read_latency_shift_reg;
+
+   always@* begin
+      uav_readdatavalid=top_read_latency_shift_reg;
+      if(USE_READDATAVALID) begin
+         uav_readdatavalid = av_readdatavalid;
+      end
+   end
+
+   always@* begin
+      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+         top_read_latency_shift_reg=read_latency_shift_reg;
+      end
+      if (AV_READLATENCY > 1) begin
+         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+      end
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if (reset) begin
+         read_latency_shift_reg <= '0;
+      end else if (av_clken) begin
+         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+         end
+      end
+   end
+
+   // ------------
+   // Chipselect and OutputEnable
+   // ------------
+   reg av_chipselect_pre;
+   wire cs_extension;
+   reg av_outputenable_pre;
+   
+   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset)
+         av_outputenable_pre <= 1'b0;
+      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
+         av_outputenable_pre <= 0;
+      else
+         av_outputenable_pre <= cs_extension | uav_read;
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         av_chipselect_pre  <= 1'b0;
+      end else begin
+         av_chipselect_pre  <= 1'b0;
+         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+            if(uav_read) begin
+               av_chipselect_pre <= 1'b1;
+            end else if(cs_extension == 1) begin
+               av_chipselect_pre <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------
+   // Begintransfer Assigment
+   // -------------------
+   reg end_begintransfer;
+
+   always@* begin
+      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+            end_begintransfer <= 1'b1;
+         else if(uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------
+   // Beginbursttransfer Assigment
+   // -------------------
+   reg end_beginbursttransfer;
+   reg in_transfer;
+
+   always@* begin
+      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_beginbursttransfer <= 1'b0;
+         in_transfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+         if(uav_write && uav_burstcount == symbols_per_word)
+            in_transfer <=1'b0;
+         else if(uav_write)
+            in_transfer <=1'b1;
+      end
+   end
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.sdc b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.sdc
new file mode 100644
index 0000000..3a7710f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.sdc
@@ -0,0 +1,30 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set aclr_counter 0
+set clrn_counter 0
+set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+set aclr_counter [get_collection_size $aclr_collection]
+set clrn_counter [get_collection_size $clrn_collection]
+
+if {$aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+}
+
+if {$clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+}
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.v
new file mode 100644
index 0000000..bee20fd
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_controller.v
@@ -0,0 +1,319 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// ACDS13.1 - Added reset request as part of reset sequencing
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+    parameter NUM_RESET_INPUTS              = 6,
+    parameter USE_RESET_REQUEST_IN0 = 0,
+    parameter USE_RESET_REQUEST_IN1 = 0,
+    parameter USE_RESET_REQUEST_IN2 = 0,
+    parameter USE_RESET_REQUEST_IN3 = 0,
+    parameter USE_RESET_REQUEST_IN4 = 0,
+    parameter USE_RESET_REQUEST_IN5 = 0,
+    parameter USE_RESET_REQUEST_IN6 = 0,
+    parameter USE_RESET_REQUEST_IN7 = 0,
+    parameter USE_RESET_REQUEST_IN8 = 0,
+    parameter USE_RESET_REQUEST_IN9 = 0,
+    parameter USE_RESET_REQUEST_IN10 = 0,
+    parameter USE_RESET_REQUEST_IN11 = 0,
+    parameter USE_RESET_REQUEST_IN12 = 0,
+    parameter USE_RESET_REQUEST_IN13 = 0,
+    parameter USE_RESET_REQUEST_IN14 = 0,
+    parameter USE_RESET_REQUEST_IN15 = 0,
+    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
+    parameter SYNC_DEPTH                    = 2,
+    parameter RESET_REQUEST_PRESENT         = 0,
+    parameter RESET_REQ_WAIT_TIME           = 3,
+    parameter MIN_RST_ASSERTION_TIME        = 11,
+    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
+    parameter ADAPT_RESET_REQUEST          = 0
+)
+(
+    // --------------------------------------
+    // We support up to 16 reset inputs, for now
+    // --------------------------------------
+    input reset_in0,
+    input reset_in1,
+    input reset_in2,
+    input reset_in3,
+    input reset_in4,
+    input reset_in5,
+    input reset_in6,
+    input reset_in7,
+    input reset_in8,
+    input reset_in9,
+    input reset_in10,
+    input reset_in11,
+    input reset_in12,
+    input reset_in13,
+    input reset_in14,
+    input reset_in15,
+    input reset_req_in0,
+    input reset_req_in1,
+    input reset_req_in2,
+    input reset_req_in3,
+    input reset_req_in4,
+    input reset_req_in5,
+    input reset_req_in6,
+    input reset_req_in7,
+    input reset_req_in8,
+    input reset_req_in9,
+    input reset_req_in10,
+    input reset_req_in11,
+    input reset_req_in12,
+    input reset_req_in13,
+    input reset_req_in14,
+    input reset_req_in15,
+
+
+    input  clk,
+    output reg reset_out,
+    output reg reset_req
+);
+
+   // Always use async reset synchronizer if reset_req is used
+   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+   // --------------------------------------
+   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
+   // --------------------------------------
+   localparam MIN_METASTABLE = 3;
+   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
+
+   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
+
+   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
+                                            MIN_RST_ASSERTION_TIME + 1 :
+                                        (
+                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
+                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
+                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
+                                        );
+
+   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
+   // --------------------------------------
+
+   wire merged_reset;
+   wire merged_reset_req_in;
+   wire reset_out_pre;
+   wire reset_req_pre;
+
+   // Registers and Interconnect
+   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
+   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
+   reg                                          r_sync_rst;
+   reg                                          r_early_rst;
+
+    // --------------------------------------
+    // "Or" all the input resets together
+    // --------------------------------------
+    assign merged_reset = (  
+                              reset_in0 | 
+                              reset_in1 | 
+                              reset_in2 | 
+                              reset_in3 | 
+                              reset_in4 | 
+                              reset_in5 | 
+                              reset_in6 | 
+                              reset_in7 | 
+                              reset_in8 | 
+                              reset_in9 | 
+                              reset_in10 | 
+                              reset_in11 | 
+                              reset_in12 | 
+                              reset_in13 | 
+                              reset_in14 | 
+                              reset_in15
+                          );
+
+    assign merged_reset_req_in = (
+                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
+                            );
+
+
+    // --------------------------------------
+    // And if required, synchronize it to the required clock domain,
+    // with the correct synchronization type
+    // --------------------------------------
+    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
+
+        assign reset_out_pre = merged_reset;
+        assign reset_req_pre = merged_reset_req_in;
+
+    end else begin
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
+        )
+        alt_rst_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset),
+            .reset_out  (reset_out_pre)
+        );
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_req_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset_req_in),
+            .reset_out  (reset_req_pre)
+        );
+
+    end
+    endgenerate
+
+    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
+                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
+        always @* begin
+            reset_out = reset_out_pre;
+            reset_req = reset_req_pre;
+        end
+    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
+
+        wire reset_out_pre2;
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH+1),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_sync_uq2
+        (
+            .clk        (clk),
+            .reset_in   (reset_out_pre),
+            .reset_out  (reset_out_pre2)
+        );
+
+        always @* begin
+            reset_out = reset_out_pre2;
+            reset_req = reset_req_pre;
+        end
+
+    end
+    else begin
+
+    // 3-FF Metastability Synchronizer
+    initial
+    begin
+        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
+            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
+    end
+
+    // Synchronous reset pipe
+    initial
+    begin
+        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
+        begin
+            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+    else
+    begin
+        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
+    end
+    end
+
+    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
+    // matches the early input.
+
+    always @(posedge clk)
+    begin
+        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
+            3'b000:   r_sync_rst <= 1'b0; // Not reset
+            3'b001:   r_sync_rst <= 1'b0;
+            3'b010:   r_sync_rst <= 1'b0;
+            3'b011:   r_sync_rst <= 1'b1;
+            3'b100:   r_sync_rst <= 1'b1; 
+            3'b101:   r_sync_rst <= 1'b1;
+            3'b110:   r_sync_rst <= 1'b1;
+            3'b111:   r_sync_rst <= 1'b1; // In Reset
+            default:  r_sync_rst <= 1'b1;
+        endcase
+
+        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
+            2'b00:   r_early_rst <= 1'b0; // Not reset
+            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
+            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
+            2'b11:   r_early_rst <= 1'b1; // Held in reset
+            default: r_early_rst <= 1'b1;
+        endcase
+    end
+
+    always @* begin
+        reset_out = r_sync_rst;
+        reset_req = r_early_rst;
+    end
+
+    end
+    endgenerate
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_synchronizer.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_synchronizer.v
new file mode 100644
index 0000000..01613ec
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/altera_reset_synchronizer.v
@@ -0,0 +1,87 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+    reg altera_reset_synchronizer_int_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+                altera_reset_synchronizer_int_chain_out <= 1'b1;
+            end
+            else begin
+                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+            end
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
new file mode 100644
index 0000000..3c6d33d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v
@@ -0,0 +1,287 @@
+//background subtraction module
+
+//tested with algo_top_cl_cali_tb.v with bkg_subtraction_pipe
+module bkg_subtraction_pipe #(parameter BKG_FRAME = 4)(
+	
+	//clock and reset
+	input wire clk,
+	input wire rst, // connect to rst_run
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  // 163 word = 3 header + 160 data
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
+	output  wire [31:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket,  //         .startofpacket	
+	
+	output wire				bkg_sub_on,
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //3 headers 
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it?  26.June. 2024
+);
+	localparam SHIFT_BIT = $clog2(BKG_FRAME); 
+	
+	wire rst_frame = data_in_startofpacket; 
+	
+	wire data_out_ready_for3header = to_udp_ready;
+	
+	/************************* Frame Counter***********************************/
+	/*
+	This is a frame counter; 
+	frameID +1 at the rising edge of data_in_startofpacket
+	if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
+	*/
+	reg [26:0] frameID;
+	reg data_in_startofpacket_last;
+	
+	always @(posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			data_in_startofpacket_last <= 1'b0;
+			frameID<= 27'b0;
+		end
+		else 
+		begin
+			data_in_startofpacket_last <= data_in_startofpacket;
+			if (~data_in_startofpacket_last && data_in_startofpacket)
+				frameID<= frameID + 1'b1; 
+		end
+	end
+	
+	//**********************bkg_subtraction or not *****************
+	
+	reg[1:0] state_bkg;
+  localparam STATE_BKG_IDLE = 0;
+  localparam STATE_RAM_RST = 1;
+  localparam STATE_BKG_ADD = 3;
+  localparam STATE_BKG_OUT = 2;
+  
+  assign bkg_sub_on = (state_bkg == STATE_BKG_OUT)? 1'b1:1'b0;
+  
+  always @(posedge clk or posedge rst)
+  begin
+   if (rst)
+		state_bkg <= STATE_BKG_IDLE;
+	else if (frameID <=27'd1)
+		state_bkg <= STATE_RAM_RST;
+	else if (frameID >BKG_FRAME+1)
+		state_bkg <= STATE_BKG_OUT;
+	else 
+		state_bkg <= STATE_BKG_ADD;
+	end
+	
+	
+	
+	/************** bkg RAM ****************************/
+	/*
+	for prepare the bkg signal by two RAM;
+	one for data_in_data[31:16]; the other for data_in_data[15:0]
+	the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
+	*/
+	
+	reg[8:0] address;
+	reg[8:0] wraddress;
+	wire		wren;
+	
+	//data_in_data + ram0_q
+	reg[31:0] ram0_data;
+	reg[31:0] ram1_data;
+	
+	wire[31:0] ram0_q;
+	wire[31:0] ram1_q;
+	
+	
+	assign wren = (state_bkg == STATE_RAM_RST || state_bkg == STATE_BKG_ADD)? data_out_ready: 1'b0; 
+	
+	ram4bkg ram4bkg0 (
+    .data(ram0_data), //32 bits
+    .rdaddress(address),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram0_q) //32 bits
+  );
+  
+  ram4bkg ram4bkg1 (
+    .data(ram1_data), //32 bits
+    .rdaddress(address),
+    .clock(clk),
+    .wraddress(wraddress),
+    .wren(wren),
+    .q(ram1_q) //32 bits
+  );
+	
+	wire[15:0] bkg0;
+	wire[15:0] bkg1;
+	
+	assign bkg0 = (state_bkg == STATE_BKG_OUT)?ram0_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	assign bkg1 = (state_bkg == STATE_BKG_OUT)?ram1_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
+	
+
+	
+	//data_in_data - bkg0
+	reg[16:0] data0_sub;
+	reg[16:0] data1_sub;
+	
+	//data_in_data
+	wire[15:0] data0_in_data;
+	wire[15:0] data1_in_data;
+	
+	assign data0_in_data = data_in_data[31:16];
+	assign data1_in_data = data_in_data[15:0];
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[2:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 3'd0;	//waiting for SOP
+	localparam STATE_WORD0	= 3'd1;	//sending first word : 			
+	localparam STATE_WORD1	= 3'd2;	//sending second word: 				
+	localparam STATE_WORD2	= 3'd3;	//sending third word :
+	localparam STATE_WAIT_FIRST = 3'd4; //wait the sub result of the first two channels
+	localparam STATE_DATA = 3'd5;
+	localparam STATE_OUTPUT_LAST = 3'd6; //output last two channels
+	localparam STATE_LOC	= 3'd7;	//
+
+	
+	
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					address <= 0;
+					wraddress <= 0; 
+					if (data_in_startofpacket)
+					begin
+						state <= STATE_WORD0;
+					end
+				end
+				STATE_WORD0:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD1;
+					end
+				end
+				STATE_WORD1:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WORD2;
+					end
+				end
+				STATE_WORD2:
+				begin
+					if (data_in_valid && data_out_ready_for3header)
+					begin
+						state <= STATE_WAIT_FIRST;
+					end
+				end
+				STATE_WAIT_FIRST:
+				begin
+					if (data_in_valid)
+					begin
+						state <= STATE_DATA;
+						address <= address + 1'b1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+					end
+				end
+				STATE_DATA:
+				begin
+					if (data_in_valid && data_out_ready)
+					begin
+						if (data_in_endofpacket)
+							state <= STATE_OUTPUT_LAST;
+						address <= address + 1'b1;
+						wraddress <= wraddress + 1'b1;
+						if (state_bkg == STATE_BKG_ADD)
+						begin
+							ram0_data <= data0_in_data + ram0_q;
+							ram1_data <= data1_in_data + ram1_q;
+						end else
+						begin
+							ram0_data <= 0;
+							ram1_data <= 0;
+						end
+						data0_sub <= data0_in_data - bkg0;
+						data1_sub <= data1_in_data - bkg1;
+					end
+				end
+				STATE_OUTPUT_LAST:
+				begin
+					if (data_out_ready)
+						state <= STATE_LOC;
+				end
+				STATE_LOC:
+				begin
+					state <= STATE_IDLE;
+				end
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		
+	//output 163 words
+	//assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready; 
+	//assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1'b1 : 1'b0; 
+	//the output data is be reversed....so during transfer without signal it's FFFFF, the software HIT-DAQ will reverse it again
+	//assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
+	//								(state == STATE_DATA_NEXT)? {signal0,signal1}: 0;
+	//assign data_out_startofpacket = data_in_startofpacket;	
+	//assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;	
+	//assign data_out_empty = 0;
+	
+	//output 160 words
+	assign data_in_ready = ((state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) && to_udp_ready) || (state == STATE_WAIT_FIRST) || (state == STATE_DATA && data_out_ready); 
+	assign data_out_valid = (state == STATE_DATA || state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0; 
+	assign data_out_data = data_out_valid? (bkg_sub_on? {data0_sub[16:1],data1_sub[16:1]}: {data0_sub[15:0],data1_sub[15:0]}):0;
+	assign data_out_startofpacket = (state == STATE_DATA && address == 8'd1)? 1'b1: 1'b0;
+	assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;
+   assign data_out_empty = 0;	
+
+	//output the 3 header to upd
+	assign to_udp_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:0;
+	 
+	assign to_udp_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_valid: 1'b0;
+	assign to_udp_empty = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_empty: 2'b0;
+	assign to_udp_startofpacket = data_in_startofpacket;
+	assign to_udp_endofpacket = (state == STATE_WORD2)?data_in_valid: 1'b0;
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v
new file mode 100644
index 0000000..c217881
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cali_ram_cali_ram.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module cali_ram_cali_ram (
+                           // inputs:
+                            address,
+                            address2,
+                            byteenable,
+                            byteenable2,
+                            chipselect,
+                            chipselect2,
+                            clk,
+                            clk2,
+                            clken,
+                            clken2,
+                            freeze,
+                            reset,
+                            reset2,
+                            reset_req,
+                            reset_req2,
+                            write,
+                            write2,
+                            writedata,
+                            writedata2,
+
+                           // outputs:
+                            readdata,
+                            readdata2
+                         )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  8: 0] address;
+  input   [  8: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 320,
+           the_altsyncram.numwords_a = 320,
+           the_altsyncram.numwords_b = 320,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 9,
+           the_altsyncram.widthad_b = 9,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v
new file mode 100644
index 0000000..3cc17f8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v
@@ -0,0 +1,172 @@
+//module calibration
+//tested by calibration_tb
+
+module calibration
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input  wire [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input  wire				waitrequest,
+//	output wire 			write,
+//	output wire 			chipselect,
+//	output wire				writedata,
+//	output wire 			byteenable,	
+	
+	//the interface for provide the calibrated data in a ram // one clock latency
+	input  wire [8:0]			data_caled_address,
+	output wire [31:0]		data_caled,
+	input  wire					data_caled_rd_enable, // to enable read
+	
+	output wire					data_in_last, //....
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 * 32 bits data  
+	// channel 0 [31:16] channel 1 [15:0]
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	
+	//for to_udp_data
+	reg [31:0] first_data_buffer;
+	wire data_out_ready;// partly mask to_udp_ready 
+	
+	
+	
+	assign clken = 1'b1;
+	reg [31:0]	data_a;
+	reg [8:0]  	address_buffer[2:0]; 
+	wire 			wren_a;
+	
+	//address_buffer[0] for read cali_fac, 1 clock earler than channel_ctr => address_buffer[1]; and address_buffer[2] is for store multiply cali_fac
+	assign address = address_buffer[0];
+	
+	wire [8:0]	address_b;
+	assign	address_b = (data_caled_rd_enable)? data_caled_address: 9'd0;
+	
+	
+	data_caled_ram	data_caled_ram0 (
+		
+		.clock ( clk ),
+		
+		.address_a (address_buffer[2]),
+		.data_a (data_a),
+		.wren_a (wren_a),
+		.q_a ( ),
+
+		.address_b ( address_b ),
+		.data_b ( ),
+		.wren_b (1'b0),
+		.q_b ( data_caled)
+		);
+		
+		
+	reg[2:0] state;
+	localparam STATE_IDLE = 3'd0; //waiting for startofpacket
+	localparam STATE_WAIT_FIRST = 3'd1; //after startofpacket, wait the first data*cali_fac 
+	localparam STATE_MIDDLE = 3'd2; //nice pipelined
+	localparam STATE_OUTPUT_LAST = 3'd3; //write the last channel
+	localparam STATE_END = 3'd4;
+	
+	//assign data_in_ready = (state == STATE_WAIT_FIRST || state == STATE_MIDDLE)? 1'b1:1'b0;
+	assign data_in_ready = (state == STATE_WAIT_FIRST)? 1'b1: ((state == STATE_MIDDLE)? (~address_buffer[2][0] || to_udp_ready): 1'b0);
+	assign wren_a = (state == STATE_MIDDLE || state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			address_buffer[0] <= 0;
+			address_buffer[1] <= 0;
+			address_buffer[2] <= 0;
+			data_a <= 0;
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			address_buffer[0] <= 0;
+			address_buffer[1] <= 0;
+			address_buffer[2] <= 0;
+			first_data_buffer <= 0;
+			data_a <= 0;
+			if (data_in_startofpacket & data_in_valid)
+			begin
+				state <= STATE_WAIT_FIRST;
+				address_buffer[0] <= address_buffer[0] + 1'b1;
+			end
+		end
+		STATE_WAIT_FIRST:
+		begin
+			if (data_in_valid & ~waitrequest)
+			begin
+				state <= STATE_MIDDLE; 
+				data_a <= data_in_data*cali_fac;
+				address_buffer[0] <= address_buffer[0] + 1'b1;
+				address_buffer[1] <= address_buffer[0];
+				address_buffer[2] <= address_buffer[1];
+			end
+		end
+		STATE_MIDDLE:
+		begin
+			if (data_in_valid & ~waitrequest)
+			begin
+				if (~address_buffer[2][0] || to_udp_ready)
+				begin
+					data_a <= data_in_data*cali_fac;
+					address_buffer[0] <= address_buffer[0] + 1'b1;
+					address_buffer[1] <= address_buffer[0];
+					address_buffer[2] <= address_buffer[1];
+					if (data_in_endofpacket)
+						state <= STATE_OUTPUT_LAST;
+					if (~address_buffer[2][0])
+						first_data_buffer <= data_a;
+				end
+			end
+		end
+		STATE_OUTPUT_LAST:
+		begin
+			if (to_udp_ready)
+				state <= STATE_END;
+		end
+		STATE_END:
+			state <= STATE_IDLE;
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+	//output the 160 32bit words to upd, first channel [31:16] , second channel [15:16]
+	//output  wire [31:0] to_udp_data,           //  st.data
+	assign to_udp_valid = (state == STATE_MIDDLE || state == STATE_OUTPUT_LAST)? address_buffer[2][0]: 1'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_MIDDLE && address_buffer[2] == 9'd1)? 1'b1: 1'b0;
+	assign to_udp_endofpacket = (state == STATE_OUTPUT_LAST)? 1'b1: 1'b0;
+	assign to_udp_data = ((state == STATE_MIDDLE || state == STATE_OUTPUT_LAST) && address_buffer[2][0])? {first_data_buffer[15:0],data_a[15:0]}: 32'b0; 
+	assign data_out_ready = ~address_buffer[2][0] || to_udp_ready;
+	//output 15:0 as calibrated data, this should be change to if calibration factor 1 is 3 bit, then it should be leftshift 3 bit
+	
+	
+	
+	
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv
new file mode 100644
index 0000000..e95b857
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv
@@ -0,0 +1,186 @@
+/*
+CLUSTER LOCATE:
+if there is continuous [equal or more than SIZE]signals above THRESHOLD, there is cluster;
+The STATE_FIRST_CLUSTER find the left position of the Cluster; sig_ch_left
+if there is more than one cluster, the STATE_LAST_CLUSTER determine the right position of the Cluster; sig_ch_right
+When the address is 319, it goes to output state:
+the has_cluster, no_cluster, sig_ch_left and sig_ch_right keep for two clocks
+*/
+
+//the interface tested  by algo_top_cl_tb.v
+//the detailed math precise tested by cluster_locate_tb.v
+
+module cluster_locate // #(parameter THRESHOLD=54, SIZE=4)
+(
+
+	input wire clk,
+	input wire rst, // connect to the data_in_startofpacket; to reset for everyframe
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence  320 channel
+	input logic signed [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+
+	input wire[15:0] THRESHOLD, //range 0~255
+	input wire[8:0] SIZE,	//range 0~255
+	
+	output wire[8:0] sig_ch_left,
+	output wire[8:0] sig_ch_right,
+	output wire has_cluster,
+	output wire no_cluster,
+	
+	output wire data_in_last //.... after this, there is has_cluster of no_cluster signal
+);
+	
+	assign data_in_last = data_in_endofpacket;
+	
+	localparam CHANNEL_NUM = 320;
+	reg signed[15:0] REG_THRESHOLD;
+	reg unsigned[8:0] REG_SIZE;
+	
+	reg[2:0] states;
+	localparam STATE_IDLE = 3'b000;
+	localparam STATE_REC = 3'b001;
+	localparam STATE_FIRST_CLUSTER = 3'b011;
+	localparam STATE_LAST_CLUSTER = 3'b010;
+	localparam STATE_HAS_CLUSTER = 3'b110;
+	localparam STATE_NO_CLUSTER = 3'b111;
+	localparam STATE_HAS_CLUSTER_KEEP = 3'b101;
+	localparam STATE_NO_CLUSTER_KEEP = 3'b100;
+	
+	reg unsigned[8:0] size_ctr; //the same as the channel
+	reg[8:0] ch_left;
+	reg[8:0] ch_right;
+	reg[8:0] address; 
+	
+	
+	assign sig_ch_left = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_left: 9'd0;
+	assign sig_ch_right = (states == STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? ch_right: 9'd0;
+	assign has_cluster = (states==STATE_HAS_CLUSTER || states == STATE_HAS_CLUSTER_KEEP)? 1'b1: 1'b0;
+	assign no_cluster = (states==STATE_NO_CLUSTER || states == STATE_NO_CLUSTER_KEEP)? 1'b1 : 1'b0;
+	
+	assign data_in_ready = (states == STATE_REC || states == STATE_FIRST_CLUSTER || states == STATE_LAST_CLUSTER)? 1'b1: 1'b0;
+	
+	wire data_over_th;  /* synthesis keep */
+	assign data_over_th = (data_in_data > REG_THRESHOLD)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+		begin
+			ch_left <= 0;
+			ch_right <= 0;
+			address <= 0; 
+			size_ctr <= 0;
+			states <= STATE_IDLE;
+			REG_THRESHOLD <= THRESHOLD;
+			REG_SIZE <= SIZE; 
+		end
+		else
+			case(states)
+				STATE_IDLE:
+				begin
+					ch_left <= 0;
+					ch_right <= 0;
+					address <= 0; 
+					size_ctr <= 0;
+					REG_THRESHOLD <= THRESHOLD;
+					REG_SIZE <= SIZE;
+					if (data_in_startofpacket)
+						states <= STATE_REC;
+				end
+				STATE_REC:
+				begin
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket) 
+							states <= STATE_NO_CLUSTER;
+						else if (data_over_th)
+						begin
+							size_ctr <= size_ctr + 1'b1;
+							states <= STATE_FIRST_CLUSTER;
+							ch_left <= address;
+						end
+					end	
+				end
+				STATE_FIRST_CLUSTER:
+				begin
+					if (data_in_valid) 
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+							if ((size_ctr + data_over_th) > REG_SIZE)
+							begin
+								states <= STATE_HAS_CLUSTER;
+								ch_right <= address;
+							end else
+								states <= STATE_NO_CLUSTER;
+						end
+						else if (data_over_th)
+							size_ctr <= size_ctr + 1'b1;
+						else   
+						begin
+							size_ctr <= 0;
+							if (size_ctr > REG_SIZE)
+							begin
+								states <= STATE_LAST_CLUSTER;
+								ch_right <= address -1'b1;
+							end else
+							begin
+								states <= STATE_REC;
+								ch_left <= 0; 
+							end
+						end
+					end
+				end
+				STATE_LAST_CLUSTER:
+				begin	
+					if (data_in_valid)
+					begin
+						address <= address + 1'b1; 
+						if (data_in_endofpacket)
+						begin
+						states <= STATE_HAS_CLUSTER;
+						if ((size_ctr + data_over_th) > REG_SIZE)
+							ch_right <= address;
+						end	
+						else if (data_over_th)
+							size_ctr<= size_ctr + 1'b1;
+						else 
+						begin
+							if (size_ctr > REG_SIZE)
+								ch_right <= address-1'b1;
+							size_ctr <= 0;
+						end
+					end
+				end
+				STATE_HAS_CLUSTER:
+				begin
+					states <= STATE_HAS_CLUSTER_KEEP;
+				end
+				STATE_NO_CLUSTER:
+				begin
+					states <= STATE_NO_CLUSTER_KEEP;
+				end
+				STATE_HAS_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				STATE_NO_CLUSTER_KEEP:
+				begin
+					states <= STATE_IDLE;
+				end
+				default:
+					states <= STATE_IDLE;
+			endcase		
+	end
+
+endmodule
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v
new file mode 100644
index 0000000..602d42c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v
@@ -0,0 +1,243 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: data_caled_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module data_caled_ram (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[31:0]  data_a;
+	input	[31:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[31:0]  q_a;
+	output	[31:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] sub_wire1;
+	wire [31:0] q_a = sub_wire0[31:0];
+	wire [31:0] q_b = sub_wire1[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (data_a),
+				.data_b (data_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
+// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
+// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
+// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
+// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
+// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL data_caled_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/div.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/div.v
new file mode 100644
index 0000000..5d50d2d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/div.v
@@ -0,0 +1,116 @@
+// megafunction wizard: %LPM_DIVIDE%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_DIVIDE 
+
+// ============================================================
+// File Name: div.v
+// Megafunction Name(s):
+// 			LPM_DIVIDE
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module div (
+	clken,
+	clock,
+	denom,
+	numer,
+	quotient,
+	remain);
+
+	input	  clken;
+	input	  clock;
+	input	[29:0]  denom;
+	input	[39:0]  numer;
+	output	[39:0]  quotient;
+	output	[29:0]  remain;
+
+	wire [39:0] sub_wire0;
+	wire [29:0] sub_wire1;
+	wire [39:0] quotient = sub_wire0[39:0];
+	wire [29:0] remain = sub_wire1[29:0];
+
+	lpm_divide	LPM_DIVIDE_component (
+				.clken (clken),
+				.clock (clock),
+				.denom (denom),
+				.numer (numer),
+				.quotient (sub_wire0),
+				.remain (sub_wire1),
+				.aclr (1'b0));
+	defparam
+		LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
+		LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
+		LPM_DIVIDE_component.lpm_pipeline = 26,
+		LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
+		LPM_DIVIDE_component.lpm_widthd = 30,
+		LPM_DIVIDE_component.lpm_widthn = 40;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
+// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
+// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
+// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "26"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
+// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "30"
+// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "40"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: denom 0 0 30 0 INPUT NODEFVAL "denom[29..0]"
+// Retrieval info: USED_PORT: numer 0 0 40 0 INPUT NODEFVAL "numer[39..0]"
+// Retrieval info: USED_PORT: quotient 0 0 40 0 OUTPUT NODEFVAL "quotient[39..0]"
+// Retrieval info: USED_PORT: remain 0 0 30 0 OUTPUT NODEFVAL "remain[29..0]"
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @denom 0 0 30 0 denom 0 0 30 0
+// Retrieval info: CONNECT: @numer 0 0 40 0 numer 0 0 40 0
+// Retrieval info: CONNECT: quotient 0 0 40 0 @quotient 0 0 40 0
+// Retrieval info: CONNECT: remain 0 0 30 0 @remain 0 0 30 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE
+// Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/frame_counter.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/frame_counter.v
new file mode 100644
index 0000000..2df7a6d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/frame_counter.v
@@ -0,0 +1,36 @@
+//the frame counter
+//count the frame number by the sensor_interface status_out[0] rising edge
+
+
+
+module frame_counter(
+	
+	input wire clk_clk,
+	input wire rst_reset, //this reset should connect to sensor_interface int_rst
+	
+	input wire sig,
+	input wire [31:0] data_in, //for connect in qsys only
+	input wire data_in_endofpacket, // for connect in qsys only
+	
+	output reg [26:0] frame_Num
+);
+
+
+	reg sig_last;
+	
+	always @(posedge clk_clk or posedge rst_reset)
+	begin
+		if (rst_reset)
+		begin
+			sig_last <= 1'b0;
+			frame_Num <= 27'b0;
+		end
+		else 
+		begin
+			sig_last <= sig;
+			if (~sig_last&&sig)
+				frame_Num <= frame_Num + 1'b1; 
+		end
+	end
+			
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v
new file mode 100644
index 0000000..d4e9c5b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v
@@ -0,0 +1,214 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4bkg.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4bkg (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[7:0]  rdaddress;
+	input	[7:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.numwords_b = 256,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.widthad_b = 8,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv
new file mode 100644
index 0000000..148674d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv
@@ -0,0 +1,398 @@
+//the module for rms
+/*
+if there is cluster:
+go through the data three times:
+first time, calc Xmean;
+second time calc Sigma;
+
+if there is no cluster:
+directly send it. 
+
+*/
+
+//
+
+//tested with algo_top_cl_cali_rms_tb.v 
+
+module rms(
+	
+	input  wire        	clk,                    //                     clk.clk
+	input  wire        	rst,         			// the reset should connect to the int_rst from sensor
+
+	//data for sig after bkg subtraction
+	input wire 			  bkg_sub_on, 					//indicate that bkg_sub is on 
+	input wire          sig_ram_last,				//the last channel is being wroten when sig_ram_last=1'b1
+	
+	output wire[8:0]		sig_rdaddress,             //0~319 for data. 500~502 for the 3 words head
+	input wire[31:0]		sig,
+	output wire 			sig_rd_eable, 					//eable read, get sig  next clock
+
+	//the output of cluster_locate
+	input wire[8:0]		sig_ch_left,	         //after sig_ram_last, if has_cluster, catch the sig_ch_left and right signal, and calc
+	input wire[8:0]		sig_ch_right,
+	input wire				has_cluster,
+	input wire				no_cluster,					// this is not used
+
+	//the result
+	output wire 			overflow,
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //4 * 32 bits data  
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	);
+	
+	
+	
+	
+	/* reg results has 32*4 bits
+	WORDS 163 [31:16]MeanXleftshift [15:0] Sigma0;
+			164 [31:16]MaxY; [15:0] STATUS;
+			165 for debug;
+			166 for debug;
+		for status register:
+		STATUS_BKG_SUB_ON  0x0001
+		STATUS_HAS_CLUSTER 0x0002
+		STATUS_NO_CLUSTER  0x0004	
+		*/
+	
+	//sig_caled is the 16 bit data after calibration; right now choose the LSM 16 bits
+	wire[15:0] sig_caled;
+	assign sig_caled = sig[15:0];
+	
+	reg[31:0] results[4];
+	
+	localparam WORDS_TO_SEND = 4;	 //results[4]
+	localparam SHIFT_BITS = 2;
+
+
+	reg[3:0] state;
+	localparam STATE_IDLE = 0; //when sig_ram_last, move to STATE_JUDGE
+	localparam STATE_JUDGE = 1; 
+	/*reset registers; If has_cluster to STATE_CAL1 => WAIT_4_CLK => DIV1 => CAL2 => WAIT_6CLK => DIV2 => SQRT => LOCK => SEND=>,
+	if not to =>SEND*/
+	localparam STATE_SEND = 2; // give a start_transmission signal and start the other statemachine for sending
+	localparam STATE_CAL1 = 4;
+	localparam STATE_WAIT_4CLK = 5;
+	localparam STATE_DIV1 = 6;
+	localparam STATE_CAL2 = 7; 
+	localparam STATE_WAIT_6CLK = 8;
+	localparam STATE_DIV2 = 9;
+	localparam STATE_SQRT = 10;
+	localparam STATE_LOCK = 11; //lock the MaxY, Sigma0, and MeanXleftshift  
+	
+
+	
+	// channel_ctr is address from sig_ram
+	// arrayID depends on the channel_ctr one clock ago
+	reg[8:0] channel_ctr;
+	localparam CH_NUM = 320; //channel number, 5 array, 320 channel
+	reg[8:0] ch_right;
+	reg[8:0] ch_left;
+	reg[2:0] arrayID;
+	
+	assign sig_rdaddress = channel_ctr;
+	assign sig_rd_eable = (state == STATE_CAL1 || state == STATE_CAL2)? 1'b1: 1'b0;
+	
+	// registers for CAL1
+	reg unsigned[12:0] X[2]; 
+	reg signed[15:0] Y[3]; //only Y[0] for cal1 //Y[2], Y[1], Y[0] for cal2, pipe 
+	reg signed[15:0] MaxY;
+	reg signed[31:0] SumY;
+	reg signed[31:0] XY;
+	reg signed[34:0] SumXY;
+	wire signed[36:0] SumXYleftshift;
+	reg unsigned[12:0] MeanXleftshift;
+	
+	assign SumXYleftshift = SumXY << SHIFT_BITS;
+	
+	
+	//the registers for CAL2
+	reg signed[31:0] SumYm1; //SumY - 1
+	reg signed[14:0] DiffxMeanX;
+	reg unsigned[28:0] DiffxMeanX2;
+	reg signed[43:0] DiffxMeanX2Yi;
+	reg signed[43:0] SumDiffxMeanX2Yi;
+	reg unsigned[25:0] Sigma2;
+	reg unsigned[12:0] Sigma0;
+	
+	
+	
+	
+	//the wait_ctr for different steps in each states
+	reg unsigned[8:0] wait_ctr;
+	
+	wire div_clken;
+	wire[29:0] denom;
+	wire[39:0] numer;
+	wire[31:0] quotient;
+	assign div_clken = (state == STATE_DIV1 || state == STATE_DIV2)? 1'b1: 1'b0;
+	assign denom = (state == STATE_DIV1)? SumY[29:0]: 
+						(state == STATE_DIV2)? (SumYm1[29:0]): 30'b1;
+	assign numer = (state == STATE_DIV1)? (SumXYleftshift[35:0]) :
+						(state == STATE_DIV2)? SumDiffxMeanX2Yi[39:0]: 0;
+	localparam DIV_LATENCY = 26;
+	//division with 26 clocks latency
+	div	div1 (
+	.clken ( div_clken ),
+	.clock ( clk),
+	.denom ( denom ),
+	.numer ( numer ),
+	.quotient ( quotient )
+	);
+	
+	wire sqrt_clken;
+	wire[25:0] radical_sig;
+	wire[12:0] q_sqrt;
+	assign sqrt_clken = (state == STATE_SQRT)? 1'b1: 1'b0;
+	assign radical_sig = (state == STATE_SQRT)? Sigma2: 26'b0;
+	localparam SQRT_LATENCY = 13;
+	//sqrt with 13 clocks latency
+	sqrt	sqrt_inst (
+	.clk ( clk),
+	.ena ( sqrt_clken ),
+	.radical ( radical_sig ),
+	.q ( q_sqrt )
+	);
+	
+
+	// 12 July 2024 I should change arrayID to wires
+	//the sequential logic for arrayID
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			arrayID <= 3'd0;
+		else if (channel_ctr>=9'h0 && channel_ctr<9'h40)
+			arrayID <= 3'd0;
+		else if (channel_ctr<9'h80)
+			arrayID <= 3'd1;
+		else if (channel_ctr<9'hC0)
+			arrayID <= 3'd2;
+		else if (channel_ctr<9'h100)
+			arrayID <= 3'd3;
+		else if (channel_ctr<9'h140)
+			arrayID <= 3'd4;
+		else
+			arrayID <= 3'd0;
+	end
+	
+	
+	always @ (posedge clk or posedge rst) 
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			X[0] <= 0; //For cal1
+			X[1] <= 0;
+			Y[0] <= 0;
+			MaxY <= 0;
+			XY <= 0; 
+			SumXY <= 0;
+			SumY <= 0;
+			SumDiffxMeanX2Yi <= 0;
+			wait_ctr <= 0;
+			MeanXleftshift <= 0;
+			Y[1] <= 0; //For cal2
+			Y[2] <= 0;
+			SumYm1 <= 0;
+			DiffxMeanX <= 0;
+			DiffxMeanX2 <= 0;
+			DiffxMeanX2Yi <= 0;
+			SumDiffxMeanX2Yi <= 0; 
+			Sigma2 <= 0;
+			Sigma0 <= 0;
+			results[0] <= 0; //Collect Results
+			results[1] <= 0;
+			results[2] <= 0;
+			results[3] <= 0;
+			ch_right <= 0;
+			ch_left <= 0;
+			if (sig_ram_last) begin
+				state <= STATE_JUDGE;
+			end
+		end
+		STATE_JUDGE:
+		begin
+			if (bkg_sub_on && has_cluster)	
+					state <= STATE_CAL1; 
+			else
+				state <= STATE_SEND;			
+			results[1][0] <= bkg_sub_on;
+			results[1][1] <= has_cluster;
+			results[1][2] <= no_cluster;
+			results[2][31:16] <= {7'b0,sig_ch_left};
+			results[2][15:0] <= {7'b0,sig_ch_right};
+			ch_right <= sig_ch_right;
+			ch_left <= sig_ch_left;
+			channel_ctr <= sig_ch_left;
+		end
+		STATE_CAL1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1] <= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			if (wait_ctr >= 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig_caled;
+			end
+			if (wait_ctr>=2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr>=3) begin
+				SumXY <= SumXY + XY;
+			end			
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_4CLK;
+				channel_ctr <= ch_left;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_WAIT_4CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr < 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig_caled;
+			end
+			if (wait_ctr < 2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr < 3) begin
+				SumXY <= SumXY + XY;
+			end
+			if (wait_ctr == 3) begin
+				state <= STATE_DIV1;
+				SumYm1 <= SumY - 1'b1;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_DIV1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				MeanXleftshift <= quotient[12:0];
+				wait_ctr <= 0;
+				state <= STATE_CAL2;
+			end
+		end
+		STATE_CAL2:
+		begin
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1] <= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			wait_ctr <= wait_ctr + 1'b1;	
+			if (wait_ctr >= 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig_caled;
+			end
+			if (wait_ctr >= 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr >= 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr >= 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr >= 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_6CLK;
+				wait_ctr <= 0;
+				channel_ctr <= ch_left;
+			end
+		end
+		STATE_WAIT_6CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			
+			if (wait_ctr < 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig_caled;
+			end
+			if (wait_ctr < 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr < 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr < 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr < 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (wait_ctr == 5) begin
+				wait_ctr <= 0;
+				state <= STATE_DIV2;
+			end
+		end
+		STATE_DIV2:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				Sigma2 <= quotient[25:0];
+				wait_ctr <= 0;
+				state <= STATE_SQRT;
+			end
+		end
+		STATE_SQRT:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == SQRT_LATENCY)
+			begin
+				state <= STATE_LOCK;
+				wait_ctr <= 0;
+				Sigma0 <= q_sqrt;
+			end
+		end
+		STATE_LOCK:
+		begin
+			results[0][31:16] <= MeanXleftshift;
+			results[0][15:0] <= Sigma0;
+			results[1][31:16] <= MaxY;
+			state <=  STATE_SEND;
+		end
+		STATE_SEND:
+		begin
+			if (to_udp_ready)
+			begin
+				wait_ctr <= wait_ctr + 1'b1;
+				if (wait_ctr == WORDS_TO_SEND-1)
+					state <= STATE_IDLE;
+			end
+		end
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	assign to_udp_data = (state == STATE_SEND)? results[wait_ctr]:32'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_SEND && wait_ctr == 9'b0)? 1'b1: 1'b0;
+	assign to_udp_valid = (state == STATE_SEND)? 1'b1: 1'b0;
+	assign to_udp_endofpacket = (state == STATE_SEND && wait_ctr == (WORDS_TO_SEND-1))? 1'b1: 1'b0;
+	
+	
+	
+	endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v
new file mode 100644
index 0000000..616096b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v
@@ -0,0 +1,139 @@
+//module sensor_algo
+//combine sensor_interface bkg_subtraction, cluster_locate, and calibration, and rms
+
+
+module sensor_algo(
+
+	//Clock/reset
+	input  wire        	clk_clk,                    //                     clk.clk
+	input  wire        	rst_reset,                  //                     rst.reset
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+	//Avalon ST transmitter
+	output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+	output wire        	data_out_endofpacket,   	//                        .endofpacket
+	output wire        	data_out_startofpacket, 	//                        .startofpacket
+	input  wire        	data_out_ready,         	//                        .ready
+	output wire        	data_out_valid,         	//                        .valid
+	output wire [1:0]  	data_out_empty,         	//                        .empty
+	//Sensor interface
+	input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+	output wire        	out_adc_clk,                //                        .out_dac_clk
+	output wire        	out_adc_cnv,                //                        .out_dac_cnv
+	input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+	output wire        	out_sensor_rst,             //                        .out_sensor_rst
+	output wire        	out_sensor_clk,             //                        .out_sensor_clk
+	output wire        	out_sensor_gain,            //                        .out_sensor_gain
+	//Serial synchro interface
+	input  wire	   		serial_rx,					//receive data
+	output wire	   		serial_tx,					//send data
+	input  wire [7:0]  	ext_input,					//SMA etc.
+	//Debug information
+	output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+	
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input	 wire				waitrequest
+	
+);
+	
+
+	wire [31:0] data_out_data1;   // Output data
+	wire data_out_endofpacket1;    // Output end-of-packet signal
+	wire data_out_startofpacket1;  // Output start-of-packet signal
+	wire data_out_ready1;         // Output ready signal
+	wire data_out_valid1;         // Output valid signal
+	wire [1:0] data_out_empty1;   // Output empty signal
+
+	wire int_rst;
+	wire [7:0] cluster_threshold;
+	wire [7:0] cluster_size;
+	wire [7:0] in_algo_threshold;
+
+	  
+
+	sensor_interface the_sensor_interface (
+		.clk_clk			(clk_clk),                //      clk.clk
+		.rst_reset			(rst_reset),              //      rst.reset
+		
+		.csr_address			(csr_address),            //      csr.address
+		.csr_write			(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read			(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		
+		.data_out_data			(data_out_data1),          // data_out.data
+		.data_out_empty			(data_out_empty1),         //         .empty
+		.data_out_endofpacket		(data_out_endofpacket1),   //         .endofpacket
+		.data_out_startofpacket		(data_out_startofpacket1),//         .startofpacket
+		.data_out_ready			(data_out_ready1),         //         .ready
+		.data_out_valid			(data_out_valid1),          //         .valid
+		
+		.in_trg 			(in_trg),                                //                  sensor.in_trg
+		.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+		.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+		.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+		.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+		.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+		.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+		.serial_rx			(serial_rx),		//receive data
+		.serial_tx			(serial_tx),		//send data
+		.ext_input			(ext_input),			//SMA etc.
+		
+		.int_rst          (int_rst),
+		.cluster_threshold		(cluster_threshold),
+		.cluster_size				(cluster_size),
+		.in_algo_threshold		(in_algo_threshold)
+		
+	);
+	
+	
+	algo_top_cl_cali_rms recon(
+	
+		.clk		(clk_clk),
+		.rst		(int_rst),
+		
+		.data_in_data		(data_out_data1),
+		.data_in_ready		(data_out_ready1),
+		.data_in_valid		(data_out_valid1),
+		.data_in_empty		(data_out_empty1),
+		.data_in_startofpacket		(data_out_startofpacket1),
+		.data_in_endofpacket			(data_out_endofpacket1),
+		
+				
+		.CL_THRESHOLD		(cluster_threshold),
+		.CL_SIZE				(cluster_size),
+		.IN_ALGO_THRESHOLD	(in_algo_threshold),
+		
+		.address		(address),
+		.clken		(clken),
+		.cali_fac	(cali_fac),
+		.waitrequest(waitrequest),
+		
+		.to_udp_data (data_out_data),           
+		.to_udp_ready(data_out_ready),          
+		.to_udp_valid (data_out_valid),          
+		.to_udp_empty (data_out_empty),          
+		.to_udp_endofpacket (data_out_endofpacket),    
+		.to_udp_startofpacket (data_out_startofpacket)		
+	);
+
+
+
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
new file mode 100644
index 0000000..db40835
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter.v
@@ -0,0 +1,212 @@
+// sensor_algo_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 16,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 0,
+		parameter outUseEmptyPort = 1,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		output wire [15:0] out_0_data,          //    out_0.data
+		output wire        out_0_valid,         //         .valid
+		input  wire        out_0_ready,         //         .ready
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket,   //         .endofpacket
+		output wire        out_0_empty          //         .empty
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 16)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	sensor_algo_avalon_st_adapter_data_format_adapter_0 data_format_adapter_0 (
+		.clk               (in_clk_0_clk),        //   clk.clk
+		.reset_n           (~in_rst_0_reset),     // reset.reset_n
+		.in_data           (in_0_data),           //    in.data
+		.in_valid          (in_0_valid),          //      .valid
+		.in_ready          (in_0_ready),          //      .ready
+		.in_startofpacket  (in_0_startofpacket),  //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),    //      .endofpacket
+		.in_empty          (in_0_empty),          //      .empty
+		.out_data          (out_0_data),          //   out.data
+		.out_valid         (out_0_valid),         //      .valid
+		.out_ready         (out_0_ready),         //      .ready
+		.out_startofpacket (out_0_startofpacket), //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket),   //      .endofpacket
+		.out_empty         (out_0_empty)          //      .empty
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
new file mode 100644
index 0000000..fea4720
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001.v
@@ -0,0 +1,227 @@
+// sensor_algo_avalon_st_adapter_001.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_avalon_st_adapter_001 #(
+		parameter inBitsPerSymbol = 8,
+		parameter inUsePackets    = 1,
+		parameter inDataWidth     = 32,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 1,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 32,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 0,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 0,
+		parameter outUseReady     = 0,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,        // in_clk_0.clk
+		input  wire        in_rst_0_reset,      // in_rst_0.reset
+		input  wire [31:0] in_0_data,           //     in_0.data
+		input  wire        in_0_valid,          //         .valid
+		output wire        in_0_ready,          //         .ready
+		input  wire        in_0_startofpacket,  //         .startofpacket
+		input  wire        in_0_endofpacket,    //         .endofpacket
+		input  wire [1:0]  in_0_empty,          //         .empty
+		output wire [31:0] out_0_data,          //    out_0.data
+		output wire        out_0_startofpacket, //         .startofpacket
+		output wire        out_0_endofpacket    //         .endofpacket
+	);
+
+	wire         data_format_adapter_0_out_valid;         // data_format_adapter_0:out_valid -> timing_adapter_0:in_valid
+	wire  [31:0] data_format_adapter_0_out_data;          // data_format_adapter_0:out_data -> timing_adapter_0:in_data
+	wire         data_format_adapter_0_out_ready;         // timing_adapter_0:in_ready -> data_format_adapter_0:out_ready
+	wire         data_format_adapter_0_out_startofpacket; // data_format_adapter_0:out_startofpacket -> timing_adapter_0:in_startofpacket
+	wire         data_format_adapter_0_out_endofpacket;   // data_format_adapter_0:out_endofpacket -> timing_adapter_0:in_endofpacket
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 8)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 32)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	sensor_algo_avalon_st_adapter_001_data_format_adapter_0 data_format_adapter_0 (
+		.clk               (in_clk_0_clk),                            //   clk.clk
+		.reset_n           (~in_rst_0_reset),                         // reset.reset_n
+		.in_data           (in_0_data),                               //    in.data
+		.in_valid          (in_0_valid),                              //      .valid
+		.in_ready          (in_0_ready),                              //      .ready
+		.in_startofpacket  (in_0_startofpacket),                      //      .startofpacket
+		.in_endofpacket    (in_0_endofpacket),                        //      .endofpacket
+		.in_empty          (in_0_empty),                              //      .empty
+		.out_data          (data_format_adapter_0_out_data),          //   out.data
+		.out_valid         (data_format_adapter_0_out_valid),         //      .valid
+		.out_ready         (data_format_adapter_0_out_ready),         //      .ready
+		.out_startofpacket (data_format_adapter_0_out_startofpacket), //      .startofpacket
+		.out_endofpacket   (data_format_adapter_0_out_endofpacket)    //      .endofpacket
+	);
+
+	sensor_algo_avalon_st_adapter_001_timing_adapter_0 timing_adapter_0 (
+		.clk               (in_clk_0_clk),                            //   clk.clk
+		.reset_n           (~in_rst_0_reset),                         // reset.reset_n
+		.in_data           (data_format_adapter_0_out_data),          //    in.data
+		.in_valid          (data_format_adapter_0_out_valid),         //      .valid
+		.in_ready          (data_format_adapter_0_out_ready),         //      .ready
+		.in_startofpacket  (data_format_adapter_0_out_startofpacket), //      .startofpacket
+		.in_endofpacket    (data_format_adapter_0_out_endofpacket),   //      .endofpacket
+		.out_data          (out_0_data),                              //   out.data
+		.out_startofpacket (out_0_startofpacket),                     //      .startofpacket
+		.out_endofpacket   (out_0_endofpacket)                        //      .endofpacket
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
new file mode 100644
index 0000000..66deb05
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_data_format_adapter_0.sv
@@ -0,0 +1,99 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_data_format_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/21 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Data Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_001_data_format_adapter_0
+//   usePackets:         true
+//   hasInEmpty:         true
+//   inEmptyWidth:       2
+//   hasOutEmpty:        false 
+//   outEmptyWidth:      0
+//   inDataWidth:        32
+//   outDataWidth:       32
+//   channelWidth:       0
+//   inErrorWidth:       0
+//   outErrorWidth:      0
+//   inSymbolsPerBeat:   4
+//   outSymbolsPerBeat:  4
+//   maxState:           3
+//   stateWidth:         2
+//   maxChannel:         0
+//   symbolWidth:        8
+//   numMemSymbols:      3
+//   symbolWidth:        8
+
+
+// ------------------------------------------
+
+ 
+module sensor_algo_avalon_st_adapter_001_data_format_adapter_0 (
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1 : 0]    in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1 : 0] in_empty,
+ // Interface: out
+ input                out_ready,
+ output reg           out_valid,
+ output reg [32-1: 0]  out_data,
+ output reg           out_startofpacket,
+ output reg           out_endofpacket,
+
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+);
+
+
+   always @* begin
+      in_ready = out_ready; 
+      out_valid = in_valid;
+      out_data = in_data;
+      out_startofpacket = in_startofpacket;
+      out_endofpacket = in_endofpacket;
+   end
+
+endmodule
+
+   
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
new file mode 100644
index 0000000..402adf1
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_001_timing_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_001_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      false
+//   in_use_valid:       true
+//   out_use_valid:      false
+//   use_packets:        true
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        0
+//   in_ready_latency:   0
+//   out_ready_latency:  0
+//   in_payload_width:   34
+//   out_payload_width:  34
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket
+// ------------------------------------------
+
+
+
+module sensor_algo_avalon_st_adapter_001_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ // Interface: out
+ output reg [32-1: 0] out_data,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg [34-1:0]   in_payload;
+   reg [34-1:0]   out_payload;
+   reg [1-1:0]   ready;   
+   reg            out_valid;
+   // synthesis translate_off
+   always @(negedge out_valid) begin
+      $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+   end
+   // synthesis translate_on
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket};
+     {out_data,out_startofpacket,out_endofpacket} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always_comb begin
+     ready[0] = 1;
+     out_valid = in_valid;
+     out_payload = in_payload;
+     in_ready    = ready[0];
+   end
+
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
new file mode 100644
index 0000000..ee7aadc
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0.sv
@@ -0,0 +1,396 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_data_format_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/21 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Data Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_data_format_adapter_0
+//   usePackets:         true
+//   hasInEmpty:         true
+//   inEmptyWidth:       2
+//   hasOutEmpty:        true 
+//   outEmptyWidth:      1
+//   inDataWidth:        32
+//   outDataWidth:       16
+//   channelWidth:       0
+//   inErrorWidth:       0
+//   outErrorWidth:      0
+//   inSymbolsPerBeat:   4
+//   outSymbolsPerBeat:  2
+//   maxState:           3
+//   stateWidth:         2
+//   maxChannel:         0
+//   symbolWidth:        8
+//   numMemSymbols:      3
+//   symbolWidth:        8
+
+
+// ------------------------------------------
+
+ 
+module sensor_algo_avalon_st_adapter_data_format_adapter_0 (
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [32-1 : 0]    in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ input [2-1 : 0] in_empty,
+ // Interface: out
+ input                out_ready,
+ output reg           out_valid,
+ output reg [16-1: 0]  out_data,
+ output reg           out_startofpacket,
+ output reg           out_endofpacket,
+ output reg           out_empty,
+
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+);
+
+
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   reg         state_read_addr;
+   wire [2-1:0]   state_from_memory;
+   reg  [2-1:0]   state;
+   reg  [2-1:0]   new_state;
+   reg  [2-1:0]   state_d1;
+    
+   reg            in_ready_d1;
+   reg            mem_readaddr; 
+   reg            mem_readaddr_d1;
+   reg            a_ready;
+   reg            a_valid;
+   reg            a_channel;
+   reg [8-1:0]    a_data0; 
+   reg [8-1:0]    a_data1; 
+   reg [8-1:0]    a_data2; 
+   reg [8-1:0]    a_data3; 
+   reg            a_startofpacket;
+   reg            a_endofpacket;
+   reg  [2-1:0]   a_empty;
+   reg            a_error;
+   reg            b_ready;
+   reg            b_valid;
+   reg            b_channel;
+   reg  [16-1:0]   b_data;
+   reg            b_startofpacket; 
+   wire           b_startofpacket_wire; 
+   reg            b_endofpacket; 
+   reg  [1-1:0]   b_empty;
+   reg            b_error; 
+   reg            mem_write0;
+   reg  [8-1:0]   mem_writedata0;
+   wire [8-1:0]   mem_readdata0;
+   wire           mem_waitrequest0;
+   reg  [8-1:0]   mem0[0:0];
+   reg            mem_write1;
+   reg  [8-1:0]   mem_writedata1;
+   wire [8-1:0]   mem_readdata1;
+   wire           mem_waitrequest1;
+   reg  [8-1:0]   mem1[0:0];
+   reg            mem_write2;
+   reg  [8-1:0]   mem_writedata2;
+   wire [8-1:0]   mem_readdata2;
+   wire           mem_waitrequest2;
+   reg  [8-1:0]   mem2[0:0];
+   reg            sop_mem_writeenable;
+   reg            sop_mem_writedata;
+   wire           mem_waitrequest_sop; 
+
+   wire           state_waitrequest;
+   reg            state_waitrequest_d1; 
+
+   reg            in_channel = 0;
+   reg            out_channel;
+
+
+
+   reg in_error = 0;
+   reg out_error; 
+
+
+   reg  [2-1:0]   state_register;
+   reg            sop_register; 
+   reg            error_register;
+   reg  [8-1:0]   data0_register;
+   reg  [8-1:0]   data1_register;
+   reg  [8-1:0]   data2_register;
+
+   // ---------------------------------------------------------------------
+   //| Input Register Stage
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         a_valid   <= 0;
+         a_channel <= 0;
+         a_data0   <= 0;
+         a_data1   <= 0;
+         a_data2   <= 0;
+         a_data3   <= 0;
+         a_startofpacket <= 0;
+         a_endofpacket   <= 0;
+         a_empty <= 0; 
+         a_error <= 0;
+      end else begin
+         if (in_ready) begin
+            a_valid   <= in_valid;
+            a_channel <= in_channel;
+            a_error   <= in_error;
+            a_data0 <= in_data[31:24];
+            a_data1 <= in_data[23:16];
+            a_data2 <= in_data[15:8];
+            a_data3 <= in_data[7:0];
+            a_startofpacket <= in_startofpacket;
+            a_endofpacket   <= in_endofpacket;
+            a_empty         <= 0; 
+            if (in_endofpacket)
+               a_empty <= in_empty;
+         end
+      end 
+   end
+
+   always @* begin 
+      state_read_addr = a_channel;
+      if (in_ready)
+         state_read_addr = in_channel;
+   end
+   
+
+   // ---------------------------------------------------------------------
+   //| State & Memory Keepers
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         in_ready_d1          <= 0;
+         state_d1             <= 0;
+         mem_readaddr_d1      <= 0;
+         state_waitrequest_d1 <= 0;
+      end else begin
+         in_ready_d1          <= in_ready;
+         state_d1             <= state;
+         mem_readaddr_d1      <= mem_readaddr;
+         state_waitrequest_d1 <= state_waitrequest;
+      end
+   end
+   
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         state_register <= 0;
+         sop_register   <= 0;
+         data0_register <= 0;
+         data1_register <= 0;
+         data2_register <= 0;
+      end else begin
+         state_register <= new_state;
+         if (sop_mem_writeenable)
+            sop_register   <= sop_mem_writedata;
+         if (mem_write0)
+            data0_register <= mem_writedata0;
+         if (mem_write1)
+            data1_register <= mem_writedata1;
+         if (mem_write2)
+            data2_register <= mem_writedata2;
+         end
+      end
+   
+      assign state_from_memory = state_register;
+      assign b_startofpacket_wire = sop_register;
+      assign mem_readdata0 = data0_register;
+      assign mem_readdata1 = data1_register;
+      assign mem_readdata2 = data2_register;
+   
+   // ---------------------------------------------------------------------
+   //| State Machine
+   // ---------------------------------------------------------------------
+   always @* begin
+
+      
+   b_ready = (out_ready || ~out_valid);
+
+   a_ready   = 0;
+   b_data    = 0;
+   b_valid   = 0;
+   b_channel = a_channel;
+   b_error   = a_error;
+      
+   state = state_from_memory;
+      
+   new_state           = state;
+   mem_write0          = 0;
+   mem_writedata0      = a_data0;
+   mem_write1          = 0;
+   mem_writedata1      = a_data0;
+   mem_write2          = 0;
+   mem_writedata2      = a_data0;
+   sop_mem_writeenable = 0;
+
+   b_endofpacket = a_endofpacket;
+      
+   b_startofpacket = 0;
+      
+   b_endofpacket = 0;
+   b_empty = 0;
+       
+   case (state) 
+            0 : begin
+            b_data[15:8] = a_data0;
+            b_data[7:0] = a_data1;
+            b_startofpacket = a_startofpacket;
+            if (out_ready || ~out_valid) begin
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 2) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 2;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         1 : begin
+            b_data[15:8] = a_data2;
+            b_data[7:0] = a_data3;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+            a_ready = 1;
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 0) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 0;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         2 : begin
+            b_data[15:8] = a_data0;
+            b_data[7:0] = a_data1;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = state+1'b1;
+                     if (a_endofpacket && (a_empty >= 2) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 2;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+         3 : begin
+            b_data[15:8] = a_data2;
+            b_data[7:0] = a_data3;
+            b_startofpacket = 0;
+            if (out_ready || ~out_valid) begin
+            a_ready = 1;
+               if (a_valid) begin
+                  b_valid = 1;
+                  new_state = 0;
+                     if (a_endofpacket && (a_empty >= 0) ) begin
+                        new_state = 0;
+                        b_empty = a_empty - 0;
+                        b_endofpacket = 1;
+                        a_ready = 1;
+                     end
+                  end
+               end
+            end
+
+   endcase
+
+      in_ready = (a_ready || ~a_valid);
+
+      mem_readaddr = in_channel; 
+      if (~in_ready)
+         mem_readaddr = mem_readaddr_d1;
+
+      
+      sop_mem_writedata = 0;
+      if (a_valid)
+         sop_mem_writedata = a_startofpacket;
+      if (b_ready && b_valid && b_startofpacket)
+         sop_mem_writeenable = 1;
+
+   end
+
+
+   // ---------------------------------------------------------------------
+   //| Output Register Stage
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         out_valid         <= 0;
+         out_data          <= 0;
+         out_channel       <= 0;
+         out_startofpacket <= 0;
+         out_endofpacket   <= 0;
+         out_empty         <= 0;
+         out_error         <= 0;
+      end else begin
+         if (out_ready || ~out_valid) begin
+            out_valid         <= b_valid;
+            out_data          <= b_data;
+            out_channel       <= b_channel; 
+            out_startofpacket <= b_startofpacket;
+            out_endofpacket   <= b_endofpacket;
+            out_empty         <= b_empty;
+            out_error         <= b_error;
+         end
+      end 
+   end
+   
+
+
+
+endmodule
+
+   
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
new file mode 100644
index 0000000..a9417a6
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram.sv
@@ -0,0 +1,360 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//  -----------------------------------------------------------------------------------
+// | Lookahead Multiport Memory
+//  -----------------------------------------------------------------------------------
+// | Module Name     : sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram
+// | Author          : kjo, dmunday
+// | Created On      : 2013 Nov 21
+// | Description     :
+// |   Standard multi-port memory, where a read on cycle n responds with data on 
+// |   cycle n+2.  The lookahead protection means that if you write data on cycle n or 
+// |   cycle n+1, the data returned on cycle n+2 is the written data.
+//  -----------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   memName:          sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram
+//   dataWidth:        8
+//   addrWidth:        1
+//   numReadPorts:     1
+//   depth:            1
+//   clrOnRST:         0 
+
+module sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram (
+  // Interface: clock
+  input                clk,
+  input                reset_n,
+  // Interface: read0 
+  input                rd0_address,
+  output reg [8 -1: 0] rd0_readdata,
+  // Interface: write
+  input                wr_address,
+  input      [8 -1: 0] wr_writedata,
+  input                wr_write,
+  output reg           wr_waitrequest                                                               
+);
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH           = 1;   
+   localparam  DATA_WIDTH      = 8;   
+   localparam  ADDRESS_WIDTH   = 1;   
+   localparam  CLEAR_ON_RESET  = 0;   
+
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [DATA_WIDTH-1:0]        wr_writedata1;
+   reg [ADDRESS_WIDTH-1:0]     reset_count;
+   reg [DATA_WIDTH-1:0]        mem_wr_writedata;
+   reg [ADDRESS_WIDTH-1:0]     mem_wr_address;
+   reg                         mem_wr_write;
+   reg [DATA_WIDTH-1:0]        mem [DEPTH-1:0];  
+   reg                         rd0_bypass;
+   reg [DATA_WIDTH-1:0]        rd0_mem_readdata;
+   
+   // ---------------------------------------------------------------------
+   // Synchronous Stuff
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         wr_writedata1  <= 0;
+         wr_waitrequest <= 1;
+         if (CLEAR_ON_RESET) begin
+            reset_count    <= DEPTH-1'b1;
+         end else begin
+            reset_count    <= 0;
+         end
+         rd0_bypass     <= 0;
+
+      end else begin
+         rd0_bypass   <= (rd0_address == wr_address) && wr_write;
+         wr_writedata1  <= wr_writedata;  
+  // Memory reset state machine
+         if (reset_count > 0) begin
+            reset_count <= reset_count - 1'b1;
+         end else begin
+            wr_waitrequest <= 0;
+         end
+      end
+   end
+   
+   // ---------------------------------------------------------------------
+   // Combinatorial Memory Control
+   // --------------------------------------------------------------------- 
+   always @* begin
+      rd0_readdata     = rd0_mem_readdata;
+      mem_wr_write     = wr_write;
+      mem_wr_address   = wr_address;
+      mem_wr_writedata = wr_writedata;
+      
+      // Lookahead
+      if (rd0_bypass) begin
+         rd0_readdata   = wr_writedata1;
+      end
+      // Memory Reset
+      if (CLEAR_ON_RESET) begin
+         if ( wr_waitrequest ) begin
+            mem_wr_write  = 1;
+            mem_wr_address = reset_count;
+            mem_wr_writedata    = 0;
+         end
+      end
+   end
+   
+   // --------------------------------------------------------------------- 
+   // Infer Memory
+   // --------------------------------------------------------------------- 
+   always @(posedge clk) begin
+      if (mem_wr_write)
+         mem[mem_wr_address] <= mem_wr_writedata;
+      rd0_mem_readdata       <= mem[rd0_address];
+   end
+   
+endmodule
+
+// synthesis translate_off
+
+//  --------------------------------------------------------------------------------
+// | test bench
+//  --------------------------------------------------------------------------------
+`ifdef RUN_INTERNAL_TEST
+module test_sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram;
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH                   = 1
+   localparam  DATA_WIDTH              = 8
+   localparam  ADDRESS_WIDTH           = 1
+   localparam  CLEAR_ON_RESET          = 0
+   localparam  CLOCK_HALF_PERIOD       = 10;
+   localparam  CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
+   localparam  RESET_TIME              = 25;
+   
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg                       clk            = 0;
+   reg                       reset_n        = 0;
+   reg                       test_success   = 1;
+   reg                       success        = 1;
+   reg [ADDRESS_WIDTH-1:0]   wr_address;
+   reg [DATA_WIDTH-1:0]      wr_writedata;
+   reg                       wr_write;
+   wire                      wr_waitrequest;
+   reg [ADDRESS_WIDTH-1:0]   rd0_address;
+   wire [DATA_WIDTH-1:0]     rd0_readdata;
+   reg [DATA_WIDTH-1:0]      mem_mirror [DEPTH-1:0];
+    
+   // ---------------------------------------------------------------------
+   //| DUT
+   // ---------------------------------------------------------------------
+   sensor_algo_avalon_st_adapter_data_format_adapter_0_data_ram dut ( 
+    .clk              (clk),
+    .reset_n          (reset_n),
+    .rd0_address      (rd0_address),
+    .rd0_readdata     (rd0_readdata),
+    .wr_address       (wr_address),
+    .wr_writedata     (wr_writedata),
+    .wr_write         (wr_write),
+    .wr_waitrequest   (wr_waitrequest)          
+   );
+
+   // ---------------------------------------------------------------------
+   //| Clock & Reset
+   // ---------------------------------------------------------------------
+   initial begin
+      reset_n = 0;
+      #RESET_TIME;
+      reset_n = 1;
+   end
+   
+   always begin
+      #CLOCK_HALF_PERIOD;
+      clk <= ~clk;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Main Test
+   // ---------------------------------------------------------------------
+   initial begin
+      test_reset();
+      test_random();
+      test_single_channel();
+      
+      $finish;
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Test reset
+   // ---------------------------------------------------------------------
+   task test_reset;
+      integer i;
+      begin
+       test_success = 1;
+
+        if (CLEAR_ON_RESET) begin
+            @(posedge clk);
+                test_assert ("Memory's wr_waitrequest should be test_asserted while held in reset.", wr_waitrequest);
+
+                    wait (reset_n == 1);
+                        test_assert ("Memory should still be in reset immediately after clearing the in_reset signal.", wr_waitrequest);
+
+                            wait (wr_waitrequest == 0);
+                                
+
+    for (i=0; i<DEPTH; i=i+1) begin
+       rd0_address <= i;
+       @(posedge clk);
+       test_assert ("Memory location should be 0.", rd0_readdata==0);
+    end
+ end else begin
+        @(posedge clk);
+        test_assert ("Memory's in_reset should be asserted while held in reset.", wr_waitrequest);
+        wait (reset_n == 1);
+        @(posedge clk);
+        #1 test_assert ("Memory should have in_reset=0 immediately after reset!!.", wr_waitrequest==0);
+     end // else: !if(CLEAR_ON_RESET)
+  endtest("test_reset");
+endtest 
+endtask
+
+   // ---------------------------------------------------------------------
+   //| Test random in & out data
+   // ---------------------------------------------------------------------
+   task test_random;
+      integer i;
+      begin
+
+
+       // Initialize mem_mirror
+        for (i=0; i<DEPTH; i=i+1) begin
+           if (CLEAR_ON_RESET) begin
+              mem_mirror[i] = 0;
+           end else begin
+              mem_mirror[i] = 256'bX;
+           end
+        end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         fork
+            begin
+               repeat (20*DEPTH) begin // do 20x Depth writes.
+                  #1;
+                  wr_write = $random % 2;
+                  wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  wr_writedata = $random;
+                  #1;
+                  if (wr_write)
+                    mem_mirror[wr_address] = wr_writedata;
+                  @(posedge clk);
+               end
+            end
+            
+            begin
+               repeat (80*DEPTH) begin // do 80x Depth reads.
+                  rd0_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  @(posedge clk);
+                  #1;
+                  test_assert("Data Mismatch (port 0)", mem_mirror[rd0_address] == rd0_readdata);
+               end
+            end
+         join
+         endtest("test_random");
+      end
+   endtask // test_random
+
+   // ---------------------------------------------------------------------
+   //| Test a single port
+   // ---------------------------------------------------------------------
+   task test_single_channel;
+      integer i;
+      begin
+
+         reset_n <= 0;
+         @(posedge clk);
+         reset_n <= 1;
+          
+          // Initialize mem_mirror
+         for (i=0; i<DEPTH; i=i+1) begin
+            if (CLEAR_ON_RESET) begin
+               mem_mirror[i] = 0;
+            end else begin
+               mem_mirror[i] = 256'bX;
+            end
+         end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         wr_write  = 0;
+         wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+         rd0_address  = wr_address;
+         
+         repeat (200) begin // do 200 times
+            wr_write  = ($random & 1'b1);
+            wr_writedata    = $dist_uniform(23,0,256);
+            #1;
+            mem_mirror[wr_address] = wr_writedata;
+            @(posedge clk);
+            #1;
+            test_assert("Data Mismatch", mem_mirror[rd0_address] == rd0_readdata);
+         end
+         endtest("test_single_channel");
+      end
+   endtask // test_random
+   
+   
+   // ---------------------------------------------------------------------
+   //| Test_assert
+   // ---------------------------------------------------------------------
+   task test_assert;
+      input [256:0] message;
+      input         condition;
+      begin
+       if (! condition) begin
+          $display("%t: %s ",$time, message);
+          success = 0;
+          test_success = 0;
+       end
+      end
+   endtask
+
+   // ---------------------------------------------------------------------
+   //| End Test
+   // ---------------------------------------------------------------------
+   task endtest;
+      input [256:0] message;
+      begin
+         if (test_success) begin
+            $display("(sim)%t: %-40s: Pass",$time, message);
+         end else begin
+            $display("(sim)%t: %-40s: Fail",$time, message);
+         end
+         success = success & test_success;
+      end
+   endtask
+
+endmodule
+`endif
+// synthesis translate_on
+
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
new file mode 100644
index 0000000..bb63968
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram.sv
@@ -0,0 +1,360 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+//  -----------------------------------------------------------------------------------
+// | Lookahead Multiport Memory
+//  -----------------------------------------------------------------------------------
+// | Module Name     : sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram
+// | Author          : kjo, dmunday
+// | Created On      : 2013 Nov 21
+// | Description     :
+// |   Standard multi-port memory, where a read on cycle n responds with data on 
+// |   cycle n+2.  The lookahead protection means that if you write data on cycle n or 
+// |   cycle n+1, the data returned on cycle n+2 is the written data.
+//  -----------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   memName:          sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram
+//   dataWidth:        2
+//   addrWidth:        1
+//   numReadPorts:     1
+//   depth:            1
+//   clrOnRST:         1 
+
+module sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram (
+  // Interface: clock
+  input                clk,
+  input                reset_n,
+  // Interface: read0 
+  input                rd0_address,
+  output reg [2 -1: 0] rd0_readdata,
+  // Interface: write
+  input                wr_address,
+  input      [2 -1: 0] wr_writedata,
+  input                wr_write,
+  output reg           wr_waitrequest                                                               
+);
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH           = 1;   
+   localparam  DATA_WIDTH      = 2;   
+   localparam  ADDRESS_WIDTH   = 1;   
+   localparam  CLEAR_ON_RESET  = 1;   
+
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg [DATA_WIDTH-1:0]        wr_writedata1;
+   reg [ADDRESS_WIDTH-1:0]     reset_count;
+   reg [DATA_WIDTH-1:0]        mem_wr_writedata;
+   reg [ADDRESS_WIDTH-1:0]     mem_wr_address;
+   reg                         mem_wr_write;
+   reg [DATA_WIDTH-1:0]        mem [DEPTH-1:0];  
+   reg                         rd0_bypass;
+   reg [DATA_WIDTH-1:0]        rd0_mem_readdata;
+   
+   // ---------------------------------------------------------------------
+   // Synchronous Stuff
+   // ---------------------------------------------------------------------
+   always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+         wr_writedata1  <= 0;
+         wr_waitrequest <= 1;
+         if (CLEAR_ON_RESET) begin
+            reset_count    <= DEPTH-1'b1;
+         end else begin
+            reset_count    <= 0;
+         end
+         rd0_bypass     <= 0;
+
+      end else begin
+         rd0_bypass   <= (rd0_address == wr_address) && wr_write;
+         wr_writedata1  <= wr_writedata;  
+  // Memory reset state machine
+         if (reset_count > 0) begin
+            reset_count <= reset_count - 1'b1;
+         end else begin
+            wr_waitrequest <= 0;
+         end
+      end
+   end
+   
+   // ---------------------------------------------------------------------
+   // Combinatorial Memory Control
+   // --------------------------------------------------------------------- 
+   always @* begin
+      rd0_readdata     = rd0_mem_readdata;
+      mem_wr_write     = wr_write;
+      mem_wr_address   = wr_address;
+      mem_wr_writedata = wr_writedata;
+      
+      // Lookahead
+      if (rd0_bypass) begin
+         rd0_readdata   = wr_writedata1;
+      end
+      // Memory Reset
+      if (CLEAR_ON_RESET) begin
+         if ( wr_waitrequest ) begin
+            mem_wr_write  = 1;
+            mem_wr_address = reset_count;
+            mem_wr_writedata    = 0;
+         end
+      end
+   end
+   
+   // --------------------------------------------------------------------- 
+   // Infer Memory
+   // --------------------------------------------------------------------- 
+   always @(posedge clk) begin
+      if (mem_wr_write)
+         mem[mem_wr_address] <= mem_wr_writedata;
+      rd0_mem_readdata       <= mem[rd0_address];
+   end
+   
+endmodule
+
+// synthesis translate_off
+
+//  --------------------------------------------------------------------------------
+// | test bench
+//  --------------------------------------------------------------------------------
+`ifdef RUN_INTERNAL_TEST
+module test_sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram;
+
+   // ---------------------------------------------------------------------
+   //| Internal Parameters
+   // ---------------------------------------------------------------------
+   localparam  DEPTH                   = 1
+   localparam  DATA_WIDTH              = 2
+   localparam  ADDRESS_WIDTH           = 1
+   localparam  CLEAR_ON_RESET          = 1
+   localparam  CLOCK_HALF_PERIOD       = 10;
+   localparam  CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
+   localparam  RESET_TIME              = 25;
+   
+   // ---------------------------------------------------------------------
+   //| Signals
+   // ---------------------------------------------------------------------
+   reg                       clk            = 0;
+   reg                       reset_n        = 0;
+   reg                       test_success   = 1;
+   reg                       success        = 1;
+   reg [ADDRESS_WIDTH-1:0]   wr_address;
+   reg [DATA_WIDTH-1:0]      wr_writedata;
+   reg                       wr_write;
+   wire                      wr_waitrequest;
+   reg [ADDRESS_WIDTH-1:0]   rd0_address;
+   wire [DATA_WIDTH-1:0]     rd0_readdata;
+   reg [DATA_WIDTH-1:0]      mem_mirror [DEPTH-1:0];
+    
+   // ---------------------------------------------------------------------
+   //| DUT
+   // ---------------------------------------------------------------------
+   sensor_algo_avalon_st_adapter_data_format_adapter_0_state_ram dut ( 
+    .clk              (clk),
+    .reset_n          (reset_n),
+    .rd0_address      (rd0_address),
+    .rd0_readdata     (rd0_readdata),
+    .wr_address       (wr_address),
+    .wr_writedata     (wr_writedata),
+    .wr_write         (wr_write),
+    .wr_waitrequest   (wr_waitrequest)          
+   );
+
+   // ---------------------------------------------------------------------
+   //| Clock & Reset
+   // ---------------------------------------------------------------------
+   initial begin
+      reset_n = 0;
+      #RESET_TIME;
+      reset_n = 1;
+   end
+   
+   always begin
+      #CLOCK_HALF_PERIOD;
+      clk <= ~clk;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Main Test
+   // ---------------------------------------------------------------------
+   initial begin
+      test_reset();
+      test_random();
+      test_single_channel();
+      
+      $finish;
+   end
+   
+   // ---------------------------------------------------------------------
+   //| Test reset
+   // ---------------------------------------------------------------------
+   task test_reset;
+      integer i;
+      begin
+       test_success = 1;
+
+        if (CLEAR_ON_RESET) begin
+            @(posedge clk);
+                test_assert ("Memory's wr_waitrequest should be test_asserted while held in reset.", wr_waitrequest);
+
+                    wait (reset_n == 1);
+                        test_assert ("Memory should still be in reset immediately after clearing the in_reset signal.", wr_waitrequest);
+
+                            wait (wr_waitrequest == 0);
+                                
+
+    for (i=0; i<DEPTH; i=i+1) begin
+       rd0_address <= i;
+       @(posedge clk);
+       test_assert ("Memory location should be 0.", rd0_readdata==0);
+    end
+ end else begin
+        @(posedge clk);
+        test_assert ("Memory's in_reset should be asserted while held in reset.", wr_waitrequest);
+        wait (reset_n == 1);
+        @(posedge clk);
+        #1 test_assert ("Memory should have in_reset=0 immediately after reset!!.", wr_waitrequest==0);
+     end // else: !if(CLEAR_ON_RESET)
+  endtest("test_reset");
+endtest 
+endtask
+
+   // ---------------------------------------------------------------------
+   //| Test random in & out data
+   // ---------------------------------------------------------------------
+   task test_random;
+      integer i;
+      begin
+
+
+       // Initialize mem_mirror
+        for (i=0; i<DEPTH; i=i+1) begin
+           if (CLEAR_ON_RESET) begin
+              mem_mirror[i] = 0;
+           end else begin
+              mem_mirror[i] = 256'bX;
+           end
+        end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         fork
+            begin
+               repeat (20*DEPTH) begin // do 20x Depth writes.
+                  #1;
+                  wr_write = $random % 2;
+                  wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  wr_writedata = $random;
+                  #1;
+                  if (wr_write)
+                    mem_mirror[wr_address] = wr_writedata;
+                  @(posedge clk);
+               end
+            end
+            
+            begin
+               repeat (80*DEPTH) begin // do 80x Depth reads.
+                  rd0_address = ($random & 31'hFFFFFFFF) % DEPTH;
+                  @(posedge clk);
+                  #1;
+                  test_assert("Data Mismatch (port 0)", mem_mirror[rd0_address] == rd0_readdata);
+               end
+            end
+         join
+         endtest("test_random");
+      end
+   endtask // test_random
+
+   // ---------------------------------------------------------------------
+   //| Test a single port
+   // ---------------------------------------------------------------------
+   task test_single_channel;
+      integer i;
+      begin
+
+         reset_n <= 0;
+         @(posedge clk);
+         reset_n <= 1;
+          
+          // Initialize mem_mirror
+         for (i=0; i<DEPTH; i=i+1) begin
+            if (CLEAR_ON_RESET) begin
+               mem_mirror[i] = 0;
+            end else begin
+               mem_mirror[i] = 256'bX;
+            end
+         end
+         
+         wait (reset_n == 1);
+         wait (wr_waitrequest == 0);
+         
+         wr_write  = 0;
+         wr_address = ($random & 31'hFFFFFFFF) % DEPTH;
+         rd0_address  = wr_address;
+         
+         repeat (200) begin // do 200 times
+            wr_write  = ($random & 1'b1);
+            wr_writedata    = $dist_uniform(23,0,256);
+            #1;
+            mem_mirror[wr_address] = wr_writedata;
+            @(posedge clk);
+            #1;
+            test_assert("Data Mismatch", mem_mirror[rd0_address] == rd0_readdata);
+         end
+         endtest("test_single_channel");
+      end
+   endtask // test_random
+   
+   
+   // ---------------------------------------------------------------------
+   //| Test_assert
+   // ---------------------------------------------------------------------
+   task test_assert;
+      input [256:0] message;
+      input         condition;
+      begin
+       if (! condition) begin
+          $display("%t: %s ",$time, message);
+          success = 0;
+          test_success = 0;
+       end
+      end
+   endtask
+
+   // ---------------------------------------------------------------------
+   //| End Test
+   // ---------------------------------------------------------------------
+   task endtest;
+      input [256:0] message;
+      begin
+         if (test_success) begin
+            $display("(sim)%t: %-40s: Pass",$time, message);
+         end else begin
+            $display("(sim)%t: %-40s: Fail",$time, message);
+         end
+         success = success & test_success;
+      end
+   endtask
+
+endmodule
+`endif
+// synthesis translate_on
+
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
new file mode 100644
index 0000000..df635cf
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_avalon_st_adapter_timing_adapter_0.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/27 $
+// $Author: dmunday, korthner $
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Timing Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        sensor_algo_avalon_st_adapter_timing_adapter_0
+//   in_use_ready:       true
+//   out_use_ready:      false
+//   in_use_valid:       true
+//   out_use_valid:      false
+//   use_packets:        true
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         32
+//   channel_width:      0
+//   error_width:        0
+//   in_ready_latency:   0
+//   out_ready_latency:  0
+//   in_payload_width:   34
+//   out_payload_width:  34
+//   in_payload_map:     in_data,in_startofpacket,in_endofpacket
+//   out_payload_map:    out_data,out_startofpacket,out_endofpacket
+// ------------------------------------------
+
+
+
+module sensor_algo_avalon_st_adapter_timing_adapter_0
+(  
+ output reg         in_ready,
+ input               in_valid,
+ input     [32-1: 0]  in_data,
+ input              in_startofpacket,
+ input              in_endofpacket,
+ // Interface: out
+ output reg [32-1: 0] out_data,
+ output reg          out_startofpacket,
+ output reg          out_endofpacket,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+
+   // ---------------------------------------------------------------------
+   //| Signal Declarations
+   // ---------------------------------------------------------------------
+   
+   reg [34-1:0]   in_payload;
+   reg [34-1:0]   out_payload;
+   reg [1-1:0]   ready;   
+   reg            out_valid;
+   // synthesis translate_off
+   always @(negedge out_valid) begin
+      $display("%m: The downstream component expects valid data, but the upstream component cannot provide it.");
+   end
+   // synthesis translate_on
+
+   // ---------------------------------------------------------------------
+   //| Payload Mapping
+   // ---------------------------------------------------------------------
+   always @* begin
+     in_payload = {in_data,in_startofpacket,in_endofpacket};
+     {out_data,out_startofpacket,out_endofpacket} = out_payload;
+   end
+
+   // ---------------------------------------------------------------------
+   //| Ready & valid signals.
+   // ---------------------------------------------------------------------
+   always_comb begin
+     ready[0] = 1;
+     out_valid = in_valid;
+     out_payload = in_payload;
+     in_ready    = ready[0];
+   end
+
+
+
+
+endmodule
+
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_cali_fac.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
new file mode 100644
index 0000000..942da48
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_cali_fac.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module sensor_algo_cali_fac (
+                              // inputs:
+                               address,
+                               address2,
+                               byteenable,
+                               byteenable2,
+                               chipselect,
+                               chipselect2,
+                               clk,
+                               clk2,
+                               clken,
+                               clken2,
+                               freeze,
+                               reset,
+                               reset2,
+                               reset_req,
+                               reset_req2,
+                               write,
+                               write2,
+                               writedata,
+                               writedata2,
+
+                              // outputs:
+                               readdata,
+                               readdata2
+                            )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  7: 0] address;
+  input   [  7: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 160,
+           the_altsyncram.numwords_a = 160,
+           the_altsyncram.numwords_b = 160,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 8,
+           the_altsyncram.widthad_b = 8,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_calibration.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_calibration.v
new file mode 100644
index 0000000..ccf8a59
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_calibration.v
@@ -0,0 +1,126 @@
+//Legal Notice: (C)2024 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module sensor_algo_calibration (
+                                 // inputs:
+                                  address,
+                                  address2,
+                                  byteenable,
+                                  byteenable2,
+                                  chipselect,
+                                  chipselect2,
+                                  clk,
+                                  clk2,
+                                  clken,
+                                  clken2,
+                                  freeze,
+                                  reset,
+                                  reset2,
+                                  reset_req,
+                                  reset_req2,
+                                  write,
+                                  write2,
+                                  writedata,
+                                  writedata2,
+
+                                 // outputs:
+                                  readdata,
+                                  readdata2
+                               )
+;
+
+  output  [ 15: 0] readdata;
+  output  [ 15: 0] readdata2;
+  input   [  7: 0] address;
+  input   [  7: 0] address2;
+  input   [  1: 0] byteenable;
+  input   [  1: 0] byteenable2;
+  input            chipselect;
+  input            chipselect2;
+  input            clk;
+  input            clk2;
+  input            clken;
+  input            clken2;
+  input            freeze;
+  input            reset;
+  input            reset2;
+  input            reset_req;
+  input            reset_req2;
+  input            write;
+  input            write2;
+  input   [ 15: 0] writedata;
+  input   [ 15: 0] writedata2;
+
+
+wire             clocken0;
+wire             clocken1;
+wire    [ 15: 0] readdata;
+wire    [ 15: 0] readdata2;
+wire             wren;
+wire             wren2;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  assign clocken1 = clken2 & ~reset_req2;
+  assign wren2 = chipselect2 & write2;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .address_b (address2),
+      .byteena_a (byteenable),
+      .byteena_b (byteenable2),
+      .clock0 (clk),
+      .clock1 (clk2),
+      .clocken0 (clocken0),
+      .clocken1 (clocken1),
+      .data_a (writedata),
+      .data_b (writedata2),
+      .q_a (readdata),
+      .q_b (readdata2),
+      .wren_a (wren),
+      .wren_b (wren2)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK1",
+           the_altsyncram.byte_size = 8,
+           the_altsyncram.byteena_reg_b = "CLOCK1",
+           the_altsyncram.indata_reg_b = "CLOCK1",
+           the_altsyncram.init_file = "UNUSED",
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 160,
+           the_altsyncram.numwords_a = 160,
+           the_altsyncram.numwords_b = 160,
+           the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 16,
+           the_altsyncram.width_b = 16,
+           the_altsyncram.width_byteena_a = 2,
+           the_altsyncram.width_byteena_b = 2,
+           the_altsyncram.widthad_a = 8,
+           the_altsyncram.widthad_b = 8,
+           the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
new file mode 100644
index 0000000..903c0aa
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo_mm_interconnect_0.v
@@ -0,0 +1,163 @@
+// sensor_algo_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module sensor_algo_mm_interconnect_0 (
+		input  wire        sys_clk_clk_clk,                           //                         sys_clk_clk.clk
+		input  wire        ST2MM_0_reset_reset_bridge_in_reset_reset, // ST2MM_0_reset_reset_bridge_in_reset.reset
+		input  wire [8:0]  ST2MM_0_avalon_master_address,             //               ST2MM_0_avalon_master.address
+		output wire        ST2MM_0_avalon_master_waitrequest,         //                                    .waitrequest
+		input  wire        ST2MM_0_avalon_master_chipselect,          //                                    .chipselect
+		output wire [15:0] ST2MM_0_avalon_master_readdata,            //                                    .readdata
+		input  wire        ST2MM_0_avalon_master_write,               //                                    .write
+		input  wire [15:0] ST2MM_0_avalon_master_writedata,           //                                    .writedata
+		output wire [7:0]  calibration_s1_address,                    //                      calibration_s1.address
+		output wire        calibration_s1_write,                      //                                    .write
+		input  wire [15:0] calibration_s1_readdata,                   //                                    .readdata
+		output wire [15:0] calibration_s1_writedata,                  //                                    .writedata
+		output wire [1:0]  calibration_s1_byteenable,                 //                                    .byteenable
+		output wire        calibration_s1_chipselect,                 //                                    .chipselect
+		output wire        calibration_s1_clken                       //                                    .clken
+	);
+
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest;   // calibration_s1_translator:uav_waitrequest -> ST2MM_0_avalon_master_translator:uav_waitrequest
+	wire  [15:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata;      // calibration_s1_translator:uav_readdata -> ST2MM_0_avalon_master_translator:uav_readdata
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess;   // ST2MM_0_avalon_master_translator:uav_debugaccess -> calibration_s1_translator:uav_debugaccess
+	wire   [8:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_address;       // ST2MM_0_avalon_master_translator:uav_address -> calibration_s1_translator:uav_address
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_read;          // ST2MM_0_avalon_master_translator:uav_read -> calibration_s1_translator:uav_read
+	wire   [1:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable;    // ST2MM_0_avalon_master_translator:uav_byteenable -> calibration_s1_translator:uav_byteenable
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // calibration_s1_translator:uav_readdatavalid -> ST2MM_0_avalon_master_translator:uav_readdatavalid
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_lock;          // ST2MM_0_avalon_master_translator:uav_lock -> calibration_s1_translator:uav_lock
+	wire         st2mm_0_avalon_master_translator_avalon_universal_master_0_write;         // ST2MM_0_avalon_master_translator:uav_write -> calibration_s1_translator:uav_write
+	wire  [15:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata;     // ST2MM_0_avalon_master_translator:uav_writedata -> calibration_s1_translator:uav_writedata
+	wire   [1:0] st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount;    // ST2MM_0_avalon_master_translator:uav_burstcount -> calibration_s1_translator:uav_burstcount
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (9),
+		.AV_DATA_W                   (16),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (2),
+		.UAV_ADDRESS_W               (9),
+		.UAV_BURSTCOUNT_W            (2),
+		.USE_READ                    (0),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (1),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (2),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) st2mm_0_avalon_master_translator (
+		.clk                    (sys_clk_clk_clk),                                                          //                       clk.clk
+		.reset                  (ST2MM_0_reset_reset_bridge_in_reset_reset),                                //                     reset.reset
+		.uav_address            (st2mm_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (st2mm_0_avalon_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (st2mm_0_avalon_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (st2mm_0_avalon_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (ST2MM_0_avalon_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (ST2MM_0_avalon_master_waitrequest),                                        //                          .waitrequest
+		.av_chipselect          (ST2MM_0_avalon_master_chipselect),                                         //                          .chipselect
+		.av_readdata            (ST2MM_0_avalon_master_readdata),                                           //                          .readdata
+		.av_write               (ST2MM_0_avalon_master_write),                                              //                          .write
+		.av_writedata           (ST2MM_0_avalon_master_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                     //               (terminated)
+		.av_byteenable          (2'b11),                                                                    //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                     //               (terminated)
+		.av_begintransfer       (1'b0),                                                                     //               (terminated)
+		.av_read                (1'b0),                                                                     //               (terminated)
+		.av_readdatavalid       (),                                                                         //               (terminated)
+		.av_lock                (1'b0),                                                                     //               (terminated)
+		.av_debugaccess         (1'b0),                                                                     //               (terminated)
+		.uav_clken              (),                                                                         //               (terminated)
+		.av_clken               (1'b1),                                                                     //               (terminated)
+		.uav_response           (2'b00),                                                                    //               (terminated)
+		.av_response            (),                                                                         //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                     //               (terminated)
+		.av_writeresponsevalid  ()                                                                          //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (8),
+		.AV_DATA_W                      (16),
+		.UAV_DATA_W                     (16),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (2),
+		.UAV_BYTEENABLE_W               (2),
+		.UAV_ADDRESS_W                  (9),
+		.UAV_BURSTCOUNT_W               (2),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (2),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) calibration_s1_translator (
+		.clk                    (sys_clk_clk_clk),                                                          //                      clk.clk
+		.reset                  (ST2MM_0_reset_reset_bridge_in_reset_reset),                                //                    reset.reset
+		.uav_address            (st2mm_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (st2mm_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
+		.uav_read               (st2mm_0_avalon_master_translator_avalon_universal_master_0_read),          //                         .read
+		.uav_write              (st2mm_0_avalon_master_translator_avalon_universal_master_0_write),         //                         .write
+		.uav_waitrequest        (st2mm_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (st2mm_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
+		.uav_readdata           (st2mm_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                         .readdata
+		.uav_writedata          (st2mm_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                         .writedata
+		.uav_lock               (st2mm_0_avalon_master_translator_avalon_universal_master_0_lock),          //                         .lock
+		.uav_debugaccess        (st2mm_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
+		.av_address             (calibration_s1_address),                                                   //      avalon_anti_slave_0.address
+		.av_write               (calibration_s1_write),                                                     //                         .write
+		.av_readdata            (calibration_s1_readdata),                                                  //                         .readdata
+		.av_writedata           (calibration_s1_writedata),                                                 //                         .writedata
+		.av_byteenable          (calibration_s1_byteenable),                                                //                         .byteenable
+		.av_chipselect          (calibration_s1_chipselect),                                                //                         .chipselect
+		.av_clken               (calibration_s1_clken),                                                     //                         .clken
+		.av_read                (),                                                                         //              (terminated)
+		.av_begintransfer       (),                                                                         //              (terminated)
+		.av_beginbursttransfer  (),                                                                         //              (terminated)
+		.av_burstcount          (),                                                                         //              (terminated)
+		.av_readdatavalid       (1'b0),                                                                     //              (terminated)
+		.av_waitrequest         (1'b0),                                                                     //              (terminated)
+		.av_writebyteenable     (),                                                                         //              (terminated)
+		.av_lock                (),                                                                         //              (terminated)
+		.uav_clken              (1'b0),                                                                     //              (terminated)
+		.av_debugaccess         (),                                                                         //              (terminated)
+		.av_outputenable        (),                                                                         //              (terminated)
+		.uav_response           (),                                                                         //              (terminated)
+		.av_response            (2'b00),                                                                    //              (terminated)
+		.uav_writeresponsevalid (),                                                                         //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                                      //              (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v
new file mode 100644
index 0000000..66f9722
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v
@@ -0,0 +1,784 @@
+// sensor_interface.v
+
+
+
+`timescale 1 ps / 1 ps
+module sensor_interface (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		//Avalon MM slave
+        input  wire [1:0]  	csr_address,                //            avalon_slave.address
+        input  wire        	csr_read,                   //                        .read
+        output wire [31:0] 	csr_readdata,               //                        .readdata
+        input  wire        	csr_write,                  //                        .write
+        input  wire [31:0] 	csr_writedata,              //                        .writedata
+        input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty,         	//                        .empty
+		//Sensor interface
+        input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+        output wire        	out_adc_clk,                //                        .out_dac_clk
+        output wire        	out_adc_cnv,                //                        .out_dac_cnv
+        input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+        output wire        	out_sensor_rst,             //                        .out_sensor_rst
+        output wire        	out_sensor_clk,             //                        .out_sensor_clk
+        output wire        	out_sensor_gain,            //                        .out_sensor_gain
+			//Serial synchro interface
+			input  wire	   		serial_rx,					//receive data
+			output wire	   		serial_tx,					//send data
+			input  wire [7:0]  	ext_input,					//SMA etc.
+			//Debug information
+			output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+			
+			output reg 				int_rst,						//the reset for each new run 
+			output reg	[7:0]		cluster_threshold,		//from registers[3][7:0] 
+			output reg	[7:0]		cluster_size,				//from registers[3][15:8]
+			output reg  [7:0]		in_algo_threshold			//from registers[3][23:16]
+    );
+	
+
+		//Very important globals
+	reg[31:0] 	transmit_buffer[162:0];		//Data to send: 3 words header plus sensor data
+	wire 		readout_ready;				//pulsing this signal causes copying data from frame buffer to transmit buffer and initiating transmission
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[15:0]	local_sync_ctr;				//local synchronization counter, it increments by one at each frame
+	wire[8:0]	global_sync_ctr;			//global synchronization counter, it's simply the received value from serial RX.
+	wire		global_sync_error;			//RX error in the global synchronization counter
+
+		//Common generate variables
+	genvar i;	//for generate loops
+	genvar j;
+	integer xi;	//for normal loops
+	integer xj;
+
+	// *********************** CSR stuff ************************
+	/*
+		There are 4 32-bit R/W-able registers. They are used for setting up the module and checking its state
+		Reg0 is a bit different: when read, bits 15-8 (the status byte) are taken directly from device internals, not from register contents.
+		The bus can be accessed 32-, 16- or 8-bit-wise.
+
+		Register definition
+		//reg0
+		#define SENSOR_REG_COMMAND		0	//8 bits
+		#define SENSOR_REG_STATUS		1	//8 bits
+		#define SENSOR_REG_SENSORCLK	2	//8 bits, 6 used	divider for producing sensor clock ('4' MHz)
+		#define SESNOR_REG_ADCCNV		3	//8 bits, 6 used	time of conversion pulse in ADC clocks, should be > 500 ns
+		//reg1		
+		#define SENSOR_REG_DELAY		4	//16 bits, 12 used	reset signal delay in 50 MHz clocks
+		#define SENSOR_REG_SHUTTER		6	//16 bits, 12 used	sensor reset ('shutter') time in sensor clocks
+		//reg2		
+		#define SENSOR_REG_SERSPEED		8	//8 bits 		synchro baudrate, 50 for 1 Mbps
+		#define SENSOR_REG_HEADER_ANYDATA	9	//8 bits		any data transmitted with SMA state (8 bits SMA + 8 bits anydata)
+		#define SENSOR_REG_HEADER_CMD		10	//16 bits 		command field of the command header transmitted in packet
+		//reg3										//configure reg3  17.July.2024 Qin,L
+		#define SENSOR_REG_CLUSTER_THRESHOLD	12 //8 bits	 the threshold for cluster locate, range 0~255
+		#define SENSOR_REG_CLUSTER_SIZE			13 //8 bits  the size for clluster locate, range 0~255
+		#define SENSOR_REG_IN_ALGO_THRESHOLD	14 //8 bits	 the threshold inside Linear Regression, range 0~255
+		#define SENSOR_REG_RESERVED				15 //8 bits  not used 
+
+		Command bitmasks
+		#define SENSOR_CSR_EN_BITMASK		0x01	//enable operation
+		#define SENSOR_CSR_GAIN_BITMASK		0x02	//gain selection
+		#define SENSOR_CSR_ADCK_BITMASK 	0x04	//ADC clock divider on/off
+		#define SENSOR_CSR_RESET_BITMASK	0x08	//Reset all logic  //registers[0][3]
+
+		Status bitmasks
+		#define SENSOR_STATUS_SEND		0x01	//Sending over Avalon-ST
+		#define SENSOR_STATUS_TRG_WAITING	0x02	//The trigger came and is being delayed now
+		#define SENSOR_STATUS_RESET_ACTIVE	0x04	//The RESET signal for the sensor is active now
+		#define SENSOR_STATUS_ADC_ACTIVE	0x08	//The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high
+		#define SESNOR_STATUS_ADC_FINISHED	0x10	//The ADC waits for reset high
+		#define SESNOR_STATUS_TX_ACTIVE		0x20	//Sync port is sending
+		#define SESNOR_STATUS_RX_ACTIVE		0x40	//Sync port is receiving
+
+	*/
+
+	reg 	[31:0] 	registers[3:0];		//main register space
+	wire 	[31:0]	reg0_read;		//reg[0] is read indirectly to include status byt(bits 15-8)
+
+		//read logic
+	assign reg0_read[7:0] 	= registers[0][7:0];		// Readback of control bits
+	assign reg0_read[31:16] = registers[0][31:16];		// Readback of payload size
+	assign reg0_read[15] 	= 0;							// Unused bits of the status byte 
+	assign csr_readdata 	= (csr_address==0) ? reg0_read : registers[csr_address];
+
+		//write logic
+	generate
+	for (i = 0; i < 4; i = i+1)
+	begin : write_registers	//Quartus wants labels for 'for' blocks
+		for (j = 0; j < 4; j = j+1)
+		begin : write_bytes
+			always @(posedge clk_clk or posedge rst_reset)
+			begin 
+				if (rst_reset)
+					registers[i][8*j+7:8*j] <= 8'd0;
+				else
+					if (csr_byteenable[j] && (csr_address == i) && (csr_write))
+						registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
+			end
+		end
+	end	
+	endgenerate
+
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input and reset bit (reg0.3).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	//reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset | registers[0][3];
+	end
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+	
+	//localparam DATA_OUT_STATE_PEND 	= 3; //the pending when sending data
+
+	localparam WORDS_TO_SEND = 163;	
+	
+		//registers to drive output pins of ST interfaces
+//	reg		reg_valid;
+//	reg	[31:0]	reg_data;
+//	reg		reg_startofpacket;
+//	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			data_out_state <= DATA_OUT_STATE_IDLE;
+			cluster_threshold <= registers[3][7:0];
+			cluster_size <= registers[3][15:8];
+			in_algo_threshold <= registers[3][23:16];
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+						cluster_threshold <= registers[3][7:0];
+						cluster_size <= registers[3][15:8];
+						in_algo_threshold <= registers[3][23:16];
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr + 1'b1;
+						if (tx_ctr == (WORDS_TO_SEND-1))
+							data_out_state <= DATA_OUT_STATE_LOCK;
+					end
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+					data_out_state <= DATA_OUT_STATE_IDLE;
+			endcase
+	end
+
+	assign data_out_valid = (data_out_state == DATA_OUT_STATE_SEND)? 1'b1: 1'b0;
+	assign data_out_data = (data_out_state == DATA_OUT_STATE_SEND)? transmit_buffer[tx_ctr]: 32'b0;
+	assign data_out_startofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == 0) ? 1'b1: 1'b0;
+	assign data_out_endofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == (WORDS_TO_SEND-1)) ? 1'b1: 1'b0;
+
+	assign reg0_read[8] = ~(data_out_state == DATA_OUT_STATE_IDLE);		//to status register
+
+	// *********************** Detector gain logic ************************
+	/*
+		The gain signal is simply derived from reg0.
+	*/
+
+	assign out_sensor_gain = registers[0][1];
+
+	// *********************** Trigger delay logic ************************
+	/*
+		Individual trigger delay settings are needed to synchronize multiple boards.
+		A 12-bit downcounter allows for delaying incoming trigger's rising edge by up to 4095 50MHz clock cycles, i.e. 81.9 us.
+		Note: A further delay of one sensor clock will be added in the sensor clock generation logic.
+	*/
+
+	reg	[11:0]	trg_delay_ctr;
+	wire		int_trg;
+	reg	[1:0]	trg_state;
+	localparam TRG_STATE_IDLE	= 0;	//waiting for external trigger
+	localparam TRG_STATE_DELAY	= 1;	//downcounting
+	localparam TRG_STATE_ACTIVE	= 2;	//internal trigger active 
+	localparam TRG_STATE_LOCK	= 3;	//waiting for external trigger inactive 
+
+	//localparam TRG_DURATION		= 4;	//duration of the trigger signal
+
+	assign int_trg = (trg_state == TRG_STATE_ACTIVE) ? 1'b1 : 1'b0;
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			trg_state <= TRG_STATE_LOCK;
+		end
+		else
+		begin
+			case(trg_state)
+				TRG_STATE_IDLE:
+				begin
+					if (in_trg && registers[0][0])	//react on trigger only if enabled
+					begin
+						trg_delay_ctr <= registers[1][11:0];
+						trg_state <= TRG_STATE_DELAY;
+					end
+				end
+				TRG_STATE_DELAY:
+				begin
+					trg_delay_ctr <= trg_delay_ctr - 1'b1;
+					if (trg_delay_ctr == 0)
+					begin
+						//trg_delay_ctr <= TRG_DURATION-1;
+						trg_state <= TRG_STATE_ACTIVE;
+					end
+				end
+				TRG_STATE_ACTIVE:
+				begin
+					//trg_delay_ctr <= trg_delay_ctr - 1;
+					//if (trg_delay_ctr == 0)
+					//begin
+						trg_state <= TRG_STATE_LOCK;	//only one cycle of active int_trg
+					//end
+				end
+				TRG_STATE_LOCK:
+				begin
+					if (~in_trg)
+						trg_state <= TRG_STATE_IDLE;
+				end
+			endcase		
+		end
+	end
+
+	assign reg0_read[9] = ~(trg_state == TRG_STATE_IDLE);	//to status register
+
+	// *********************** Sensor clock logic  ************************
+	/*
+		The sensor needs a clock of max. 4 MHz, which is generated by this module. 
+		The actual clock speed is configurable by a register with a formula: Fs = Fi/2/(div+1),
+		where Fs is the sensor clock, Fi is input clock (50 MHz nom.) and div is a divider taken from the register.
+		A 5-bit downcounter allows for frequencies from 0.39 MHz (div=63) to 12.5 MHz (div=1).
+		The nominal setting is 6, giving 3.5714285 MHz.
+		
+		Important: The sensor clock is synchronized to the rising edge of the (delayed) trigger input, 
+		so that there is a positive slope at exactly one sensor clock period after the trigger.
+		This positive slope is then used to synchronize integration start signal (sensor reset or shutter). 
+		The synchronization is done so that one of clock states (0 or 1) gets extended, but never shortened.
+
+		Note: 4 MHz is also the top speed accepted by the ADC module.
+	*/
+
+	reg [5:0]	sensor_clk_ctr;
+	reg [1:0]	sensor_clk_state;
+
+	localparam SENSOR_CLK_STATE_LOW	= 2'd0;
+	localparam SENSOR_CLK_STATE_HIGH = 2'd1;
+	localparam SENSOR_CLK_STATE_LOWAIT = 2'd2;
+	localparam SENSOR_CLK_STATE_HIWAIT = 2'd3;	
+
+	assign out_sensor_clk = sensor_clk_state[0];
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+			sensor_clk_ctr <= registers[0][21:16];
+		end
+		else
+		begin
+			case(sensor_clk_state)
+				SENSOR_CLK_STATE_LOW:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIGH;
+					end
+				end
+				SENSOR_CLK_STATE_HIGH:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end			
+				end
+				SENSOR_CLK_STATE_LOWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+				SENSOR_CLK_STATE_HIWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+			endcase
+		end
+	end
+
+	// *********************** Sensor reset (shutter) logic ************************
+	/*
+		This block generates a 'reset' (shutter) signal for the sensor.
+		It defines the integration time and is programmable by means of a register in sensor clock units.
+		The leading (positive) slope of this signal is synchronized with the first positive slope of the sensor clock after the trigger. 
+		An internal 12-bit downcounter allows for a max. integration time of ca 1.15 ms. It can be further extended by slowing down the sensor clock.
+		It's user's responsibility to check if the integration period fits into the trigger period. If this requirement is not fulfilled, some triggers will be skipped.
+		Sorry for this ugly code, but since it works...
+
+		Important remark from sensor's specification: Rise of a RESET pulse must be set outside the video output period. 
+		This must by guaranteed by user by means of proper timing. First video comes 18 cycles after negative slope of sensor reset and is 2 cycles long.
+		Then 2 cycles pause (here we can come with the positive reset slope), then next video and so on, every 4 cycles.
+		The minimum duration of reset low is 21 clocks, and 20 clocks for reset high.
+		Our logic requires that new reset low comes only after all channels are read.
+	*/
+
+	reg [11:0]	sensor_rst_ctr;
+	reg		sensor_rst_state;
+
+	assign out_sensor_rst = sensor_rst_state;
+
+	always @(posedge int_trg or posedge out_sensor_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_rst_state <= 0;
+			sensor_rst_ctr <= 0;
+		end
+		else if (int_trg)
+		begin
+			sensor_rst_ctr <= registers[1][27:16];
+		end	
+		else
+		begin
+			if (sensor_rst_ctr == 0)
+			begin
+				sensor_rst_state <= 0;
+			end
+			else 
+			begin
+				sensor_rst_ctr <= sensor_rst_ctr - 1'b1;
+				sensor_rst_state <= 1'b1;
+			end
+		end
+	end
+
+	assign reg0_read[10] = sensor_rst_state;	//to status register
+
+	// *********************** ADC trigger logic ************************
+	/*
+		This piece produces triggering signals for ADC framework and cares about counting ADC samples.
+		It doesn't rely on incoming Trig signals, just generates them internally by counting clocks.
+
+	*/
+
+	reg [5:0] 	adc_current_channel;
+	reg [2:0]	adc_trg_state;
+	reg [4:0]	adc_trg_downctr;
+	wire 		int_adc_trg;
+	wire 		adc_trg_frame_ready;
+
+	localparam ADC_TRG_STATE_IDLE 	= 0;	//nothing happens, RESET is high or initial state
+	localparam ADC_TRG_STATE_WAIT 	= 1;	//waiting for the first video
+	localparam ADC_TRG_STATE_VIDEO1 = 2;	//capturing video
+	localparam ADC_TRG_STATE_VIDEO2 = 3;	//second cycle
+	localparam ADC_TRG_STATE_VIDEO3 = 4;	//third cycle
+	localparam ADC_TRG_STATE_VIDEO4 = 5;	//fourth cycle
+	localparam ADC_TRG_STATE_FINISH = 6;	//finished readout, waiting for RESET high to enter idle
+	localparam ADC_TRG_STATE_INIT 	= 7;	//used only for reset procedure
+
+	localparam ADC_TRG_INITIALWAIT = 5'd17;	//initial wait for the first video
+	localparam ADC_TRG_VIDEOPERIOD = 4;	//video output period
+
+	always @(posedge out_sensor_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_current_channel <= 63;
+			adc_trg_downctr <= 0;
+			adc_trg_state <= ADC_TRG_STATE_INIT;	//will go to IDLE when adc_trg_reset is high
+		end
+		else
+			case(adc_trg_state)
+				ADC_TRG_STATE_IDLE:
+				begin
+					if (~out_sensor_rst)
+					begin
+						adc_trg_downctr <= ADC_TRG_INITIALWAIT;
+						adc_current_channel <= 63;
+						adc_trg_state <= ADC_TRG_STATE_WAIT;
+					end
+				end
+				ADC_TRG_STATE_WAIT:
+				begin
+					adc_trg_downctr <= adc_trg_downctr - 1'b1;
+					if (adc_trg_downctr == 0)
+					begin
+						adc_trg_state <= ADC_TRG_STATE_VIDEO1;
+					end
+				end
+				ADC_TRG_STATE_VIDEO1:
+				begin
+					adc_current_channel <= adc_current_channel + 1'b1;
+					adc_trg_state = ADC_TRG_STATE_VIDEO2;			
+				end
+				ADC_TRG_STATE_VIDEO2:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO3;			
+				end
+				ADC_TRG_STATE_VIDEO3:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO4;			
+				end
+				ADC_TRG_STATE_VIDEO4:
+				begin
+					if (adc_current_channel == 63)
+						adc_trg_state <= ADC_TRG_STATE_FINISH;
+					else
+						adc_trg_state = ADC_TRG_STATE_VIDEO1;			
+				end	
+				ADC_TRG_STATE_FINISH, ADC_TRG_STATE_INIT:
+				begin
+					if (out_sensor_rst)
+						adc_trg_state <= ADC_TRG_STATE_IDLE;
+				end		
+			endcase
+	end
+
+	//Producing internal trigger for ADC framework (see below)
+	assign int_adc_trg = (adc_trg_state == ADC_TRG_STATE_VIDEO1)  ? 1'b1 : 1'b0;
+
+	assign adc_trg_frame_ready = (adc_trg_state == ADC_TRG_STATE_FINISH) ? 1'b1 : 1'b0;	//trigger data collection machine when the frame is ready
+
+	assign reg0_read[11] = ~(adc_trg_state == ADC_TRG_STATE_IDLE);		//to status register
+	assign reg0_read[12] = (adc_trg_state == ADC_TRG_STATE_FINISH);		//to status register
+
+	// *********************** ADC logic ************************
+	/*
+		SPI interface for ADCs. Triggers conversion and reads out the data on each incoming int_adc_trg.
+		The ADC framework and SPI runs with full clock frequency or with half of it, depending on register setting.
+		The ADC works in the 'CS Mode, 3-Wire Without Busy Indicator Serial Interface'.
+		The CNV signal length is defined by register and expressed in ADC clocks. 
+		It's user's responsibility to ensure that the CNV pulse is longer than 500 ns (required by ADC spec).
+		The ADC clock can be selected to be either full or half system clock.
+	*/
+
+		//Clock divider and selection
+	reg		adc_halfclock;
+	wire		int_adc_clk;
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+			adc_halfclock <= 0;
+		else
+			adc_halfclock <= ~adc_halfclock;
+	end
+	assign int_adc_clk = registers[0][2] ? adc_halfclock : clk_clk;
+
+		//The main state machine
+	reg [2:0]	adc_state;
+	reg [5:0]	adc_downctr;
+
+	localparam ADC_STATE_IDLE 	= 0;		//waiting for conversion
+	localparam ADC_STATE_CNV 	= 1;		//conversion on-going
+	localparam ADC_STATE_STARTREAD	= 2;	//prepare to read, conversion finished
+	localparam ADC_STATE_READ 	= 3;		//reading data
+	localparam ADC_STATE_FINISH	= 4;		//copy data to global buffer
+	localparam ADC_STATE_FINISHED	= 5;	//wait until trigger low, then go to idle
+	
+	always @(posedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_downctr <= 0;
+			adc_state <= ADC_STATE_IDLE;	
+		end
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_IDLE:
+				begin
+					adc_downctr <= registers[0][29:24];
+					if (int_adc_trg)
+						adc_state <= ADC_STATE_CNV;
+				end
+				ADC_STATE_CNV:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_STARTREAD;
+				end
+				ADC_STATE_STARTREAD:
+				begin
+					adc_downctr <= 15;
+					adc_state <= ADC_STATE_READ;
+				end
+				ADC_STATE_READ:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_FINISH;
+				end
+				ADC_STATE_FINISH:
+				begin
+					adc_state <= ADC_STATE_FINISHED;
+				end
+				ADC_STATE_FINISHED:
+				begin
+					if (!int_adc_trg)
+						adc_state <= ADC_STATE_IDLE;
+				end
+				default
+				begin
+					adc_state <= ADC_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Reading data - this happens on the negative slope of clock!
+	reg [15:0] adc_buffer[4:0];		//A shift register for SPI acquisition
+	reg [15:0] frame_buffer[319:0];		//The 'big buffer' for whole frame
+
+	always @(negedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			for (xi = 0; xi < 5; xi = xi+1)
+				adc_buffer[xi] <= 0;
+		end		
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_STARTREAD:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						adc_buffer[xi] <= 0;
+				end
+				ADC_STATE_READ:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+					begin
+						adc_buffer[xi][15:1] <= adc_buffer[xi][14:0];
+						adc_buffer[xi][0] <= in_adc_data[xi];
+					end
+				end
+				ADC_STATE_FINISH:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						frame_buffer[64*xi + adc_current_channel] <= adc_buffer[xi];
+				end
+			endcase
+		end
+	end
+
+
+	assign out_adc_cnv = (adc_state == ADC_STATE_CNV) ? 1'b1 : 1'b0;
+	assign out_adc_clk = (adc_state == ADC_STATE_READ) ? int_adc_clk : 1'b1;
+
+
+	// *********************** Putting data together and letting transmit it ************************
+	/*
+		The data is sent together with a 3-word header (6 16-bit numbers),
+		which is compatible with v.1 head structures:
+			typedef struct
+			{
+				unsigned short marker;	//must be 0x5555
+				unsigned short command;
+				unsigned short length;
+			} command_header;
+			typedef struct
+			{
+				//unsigned short channel_id;
+				unsigned short local_ctr;
+				unsigned short global_ctr;
+				unsigned short sma_state;
+			} sync_frame;
+
+	*/
+	
+	reg [2:0]	merger_state;
+
+	localparam MERGER_STATE_IDLE 	= 0;		//waiting for ADC
+	localparam MERGER_STATE_COLLECT	= 1;		//collect frame information
+	localparam MERGER_STATE_SEND	= 2;		//run Avalon sender
+	localparam MERGER_STATE_FINISH	= 3;		//roll to idle
+	
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			merger_state <= ADC_STATE_IDLE;	
+			for (xi= 0; xi < 163; xi = xi+1)
+				transmit_buffer[xi] <= 0;
+		end
+		else
+		begin
+			case(merger_state)
+				MERGER_STATE_IDLE:
+				begin
+					if (adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_COLLECT;
+				end
+				MERGER_STATE_COLLECT:
+				begin
+					transmit_buffer[0][31:16] 	<= 16'h5555;		//command_header.marker = 0x5555
+					transmit_buffer[0][15:0] 	<= registers[2][31:16];	//command_header.command = reg2.31-16
+					transmit_buffer[1][31:16]	<= 16'd323;	//16'd652;		//command_header.length = 320 samples + 6 sync bytes = 323 * 16bit //16'h143
+					transmit_buffer[1][15:0]	<= local_sync_ctr[15:0];	//sync_frame.local_ctr
+					transmit_buffer[2][24:16]	<= global_sync_ctr;	//sync_frame.global_ctr
+					transmit_buffer[2][25]		<= global_sync_error;	
+					transmit_buffer[2][31:26]	<= 0;
+					transmit_buffer[2][7:0]		<= ext_input;		//sync_frame.sma_state[7:0] = ext_input
+					transmit_buffer[2][15:8]	<= registers[2][15:8];	//sync_frame.sma_state[15:8] = reg2.15-8	
+					for (xi = 0; xi < 160; xi = xi+1)
+					begin
+						//transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi][15:0];	//ADC data
+						//transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi+1][15:0];
+						transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi][15:0];	//ADC data	//CHANGED 26.11.2019
+						transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi+1][15:0];
+					end
+					merger_state <= MERGER_STATE_SEND;
+
+				end
+				MERGER_STATE_SEND:
+				begin
+					merger_state <= MERGER_STATE_FINISH;
+				end
+				MERGER_STATE_FINISH:
+				begin
+					if (~adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Generate Avalon trigger signal
+	assign start_transmission = (merger_state == MERGER_STATE_SEND) ? 1'b1 : 1'b0;
+
+	// *********************** Synchro counter update ************************
+	/*
+		Just increment sunchronization counter at every trigger.
+		The counter is reset by int_reset.
+	*/
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			local_sync_ctr <= 0;
+		end
+		else
+		begin
+			if (int_trg)
+				local_sync_ctr <= local_sync_ctr + 1'b1;
+		end
+	end
+
+
+
+	// *********************** Synchronization serial ports ************************
+	/*
+		There is one TX and one RX module.
+		The TX is getting triggered by int_trg (same as for the main readout framework).
+		It sends 9 LSBs of the local synchro counter with programmed baudrate.
+		The default baudrate is 1 Mbps, which needs a setting of 50 for fclk=50MHz.
+		The RX puts freshly received data into global_sync_ctr. It does not need any triggering.
+	*/
+
+	wire tx_idle;
+	wire rx_idle;
+	assign reg0_read[13] = ~tx_idle;
+	assign reg0_read[14] = ~rx_idle;
+	
+	serial_tx synchro_tx (
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.data		(local_sync_ctr[8:0]),  	//  data to send
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.trigger	(start_transmission),       //  pulse to start transmission - just AFTER collecting data from sensors
+		.tx			(serial_tx),         		//  tx serial connection
+		.idle		(tx_idle)					//	1 if sender in idle state
+	);	
+
+	serial_rx synchro_rx(
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.rx			(serial_rx),         		//  rx serial connection
+		.newdata	(),							//	pulses for new data received
+		.data		(global_sync_ctr),      	//  data received
+		.error		(global_sync_error),		//	bad start or stop bit
+		.idle		(rx_idle)					//	1 if receiver in idle state
+	);
+
+	// *********************** Status output ************************
+	/*
+		The status of the module (== reg0_read[15:8]) is available at the output status bus.
+		It can be then routed to a scope or whatever for debugging
+	*/	
+	
+	assign status_out[7:0] = reg0_read[15:8];	
+	
+	
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v
new file mode 100644
index 0000000..cc1f14d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v
@@ -0,0 +1,84 @@
+// 9-bit Serial port receiver
+// It's very simple, just single sample halfway of each bit.
+// If start bit is not zero or stop bit is not one, an error will be signaled.
+// In general, this module is prone to glitches in signal. First of all, any glitch > Tclk will trigger the reception process.
+// RX is high on idle.
+// Baud rate is programmable via clk_divisor
+// clk_divisor ids internally divided by 2 to get in the middle of bit, so need to be at least 2.
+
+`timescale 100 ps / 100 ps
+module serial_rx (
+		input  wire        	clk,                	//      full-speed clock
+		input  wire        	rst,              	//      reset
+		input  wire [7:0]  	clk_divisor,         //      defines baudrate
+		input  wire 	   	rx,         		//      rx serial connection
+		output wire	   		newdata,		//	pulses for new data received
+		output wire [8:0]  	data,            	//      data to send
+		output wire	   		error,		//	bad start or stop bit
+		output wire	   		idle			//	1 if receiver in idle state
+	);
+
+	reg	[1:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_DATA		= 1;	//sending data
+	localparam STATE_FINISH		= 2;	//finished
+
+	reg	[4:0]	rx_ctr;			//counter of received data words
+	reg [7:0]	downctr;		//counter to generate baudrate
+	reg	[10:0]	buffer;			//internal latch/shift register with start and stop bit
+	reg	[8:0]	reg_data;		//latched received data
+	reg			reg_error;		//latched error
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			reg_data <= 0;
+			reg_error <= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (~rx)
+					begin
+						state 		<= STATE_DATA;
+						rx_ctr 		<= 10;
+						downctr[6:0]<= clk_divisor[7:1];	//wait half a bit
+						downctr[7]	<= 0;
+						buffer		<= 0;
+					end
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr 	<= clk_divisor;
+						rx_ctr 		<= rx_ctr - 1;
+						buffer[9:0] <= buffer[10:1];
+						buffer[10] 	<= rx;
+						if (rx_ctr == 0)
+							state 	<= STATE_FINISH;
+					end
+				end
+				STATE_FINISH:
+				begin
+					reg_data[8:0] 	<= buffer[9:1];
+					reg_error		<= buffer[0] | ~buffer[10];	//high start or low stop bit
+					state 			<= STATE_IDLE;
+				end
+				default:
+					state 			<= STATE_IDLE;
+			endcase
+	end
+	
+		//assignments
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+	assign data = reg_data;
+	assign error =  reg_error;
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v
new file mode 100644
index 0000000..ab1b607
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v
@@ -0,0 +1,115 @@
+// 9-bit Serial port transmitter
+// TX is high on idle.
+// Baud rate is programmable via clk_divisor
+
+`timescale 100 ps / 100 ps
+module serial_tx (
+		input  wire        clk,                	//      full-speed clock
+		input  wire        rst,              	//      reset
+		input  wire [8:0]  data,            	//      data to send
+		input  wire [7:0]  clk_divisor,         //      defines baudrate
+		input  wire 	   trigger,          	//      pulse to start transmission
+		output wire 	   tx,         		//      tx serial connection
+		output wire	   idle			//	1 if sender in idle state
+
+	);
+
+	reg	[2:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_STARTBIT	= 1;	//sending start bit
+	localparam STATE_DATA		= 2;	//sending data
+	localparam STATE_STOPBIT	= 3;	//sending stop bit
+	localparam STATE_FINISH		= 4;	//finished
+
+	reg	[4:0]	tx_ctr;			//counter of sent data words
+	reg 	[7:0]	downctr;		//counter to generate baudrate
+	reg	[8:0]	buffer;			//internal latch/shift register
+	reg		reg_tx;
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+			state <= STATE_FINISH;
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (trigger)
+					begin
+						state <= STATE_STARTBIT;
+						tx_ctr <= 8;
+						buffer <= data;
+						downctr <= clk_divisor;
+					end
+				end
+				STATE_STARTBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_DATA;
+					end
+
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						tx_ctr <= tx_ctr - 1;
+						buffer[7:0] <= buffer[8:1];
+						buffer[8] <= 0;
+						if (tx_ctr == 0)
+							state <= STATE_STOPBIT;
+					end
+				end
+				STATE_STOPBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_FINISH;
+					end
+
+				end
+				STATE_FINISH:
+				begin
+					if (~trigger)
+						state <= STATE_IDLE;
+				end
+				default:
+					state <= STATE_FINISH;
+			endcase
+	end
+	
+		//tx assignment
+	always @( * )
+	begin
+		if (rst)
+			reg_tx = 1;
+		else
+			case(state)
+				STATE_IDLE:
+					reg_tx = 1;
+				STATE_STARTBIT:
+					reg_tx = 0;
+				STATE_DATA:
+					reg_tx = buffer[0];
+				STATE_STOPBIT:
+					reg_tx = 1;
+				STATE_FINISH:
+					reg_tx = 1;
+				default:
+					reg_tx = 1;
+			endcase
+	end
+	assign tx = reg_tx;
+
+		//idle assignment
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v
new file mode 100644
index 0000000..a3a89bc
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v
@@ -0,0 +1,104 @@
+// megafunction wizard: %ALTSQRT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTSQRT 
+
+// ============================================================
+// File Name: sqrt.v
+// Megafunction Name(s):
+// 			ALTSQRT
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sqrt (
+	clk,
+	ena,
+	radical,
+	q,
+	remainder);
+
+	input	  clk;
+	input	  ena;
+	input	[25:0]  radical;
+	output	[12:0]  q;
+	output	[13:0]  remainder;
+
+	wire [12:0] sub_wire0;
+	wire [13:0] sub_wire1;
+	wire [12:0] q = sub_wire0[12:0];
+	wire [13:0] remainder = sub_wire1[13:0];
+
+	altsqrt	ALTSQRT_component (
+				.clk (clk),
+				.ena (ena),
+				.radical (radical),
+				.q (sub_wire0),
+				.remainder (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr ()
+				// synopsys translate_on
+				);
+	defparam
+		ALTSQRT_component.pipeline = 13,
+		ALTSQRT_component.q_port_width = 13,
+		ALTSQRT_component.r_port_width = 14,
+		ALTSQRT_component.width = 26;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: PIPELINE NUMERIC "13"
+// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13"
+// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "26"
+// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
+// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]"
+// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]"
+// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
+// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
+// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st2mm.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st2mm.v
new file mode 100644
index 0000000..fbaeb81
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st2mm.v
@@ -0,0 +1,81 @@
+//a module bridge the avalon streaming interface and avalon memory map interface
+//collect data from interface and write to RAM
+
+//32 2; OR 16 1
+module st2mm #(parameter BITSIZE = 32, EMPTY_SIZE = 2)(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [BITSIZE-1:0] st_data,           //  st.data
+	output wire        st_ready,          //         .ready
+	input  wire        st_valid,          //         .valid
+	input  wire [EMPTY_SIZE-1:0]  st_empty,          //         .empty
+	input  wire        st_endofpacket,    //         .endofpacket
+	input  wire        st_startofpacket,  //         .startofpacket
+	
+	//avalon MM(Memory Mapped) source  writelatency 0; readlatency 1 but no read logic here
+	output wire [8:0] mm_address,
+	output wire       mm_chipselect, // only for write
+	//output wire			mm_clken, //only for write; write enable
+	input wire	[BITSIZE-1:0]mm_readdate, //do not read
+	output wire 		mm_write,
+	output wire [BITSIZE-1:0] mm_writedata,
+	input wire mm_waitrequest_n
+	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE_WRITE = 2'd1; //write to mm
+	localparam STATE_LOCK = 2'd3; //Finish writing
+	
+	reg[8:0] ctr; // count data and the address for MM
+	localparam CTR_ZERO = 9'd0;
+	assign mm_address = ctr;
+	assign mm_writedata = st_data;
+	
+	assign mm_chipselect = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	//assign mm_clken = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	assign st_ready = (state == STATE_WRITE)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			ctr <= CTR_ZERO;
+		end
+		else case(state)
+				STATE_IDLE:
+				begin
+					ctr <= CTR_ZERO;
+					if (st_startofpacket)
+						state <= STATE_WRITE;
+				end
+				STATE_WRITE:
+				begin
+					if (st_valid && mm_waitrequest_n)
+					begin
+						ctr <= ctr + 1'b1;
+						if (st_endofpacket)
+							state <= STATE_LOCK;
+					end
+				end
+				STATE_LOCK:
+				begin
+					state <= STATE_IDLE;
+					ctr <= CTR_ZERO;
+				end
+				default:
+					state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v
new file mode 100644
index 0000000..823c35f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v
@@ -0,0 +1,179 @@
+// st_splitter16.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module st_splitter16 (
+		input  wire        st_splitter16_clk_clk,            //   st_splitter16_clk.clk
+		output wire        st_splitter16_in_ready,           //    st_splitter16_in.ready
+		input  wire        st_splitter16_in_valid,           //                    .valid
+		input  wire        st_splitter16_in_startofpacket,   //                    .startofpacket
+		input  wire        st_splitter16_in_endofpacket,     //                    .endofpacket
+		input  wire [0:0]  st_splitter16_in_empty,           //                    .empty
+		input  wire [15:0] st_splitter16_in_data,            //                    .data
+		input  wire        st_splitter16_out0_ready,         //  st_splitter16_out0.ready
+		output wire        st_splitter16_out0_valid,         //                    .valid
+		output wire        st_splitter16_out0_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out0_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out0_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out0_data,          //                    .data
+		input  wire        st_splitter16_out1_ready,         //  st_splitter16_out1.ready
+		output wire        st_splitter16_out1_valid,         //                    .valid
+		output wire        st_splitter16_out1_startofpacket, //                    .startofpacket
+		output wire        st_splitter16_out1_endofpacket,   //                    .endofpacket
+		output wire [0:0]  st_splitter16_out1_empty,         //                    .empty
+		output wire [15:0] st_splitter16_out1_data,          //                    .data
+		input  wire        st_splitter16_reset_reset         // st_splitter16_reset.reset
+	);
+
+	altera_avalon_st_splitter #(
+		.NUMBER_OF_OUTPUTS (2),
+		.QUALIFY_VALID_OUT (1),
+		.USE_PACKETS       (1),
+		.DATA_WIDTH        (16),
+		.CHANNEL_WIDTH     (1),
+		.ERROR_WIDTH       (1),
+		.BITS_PER_SYMBOL   (8),
+		.EMPTY_WIDTH       (1)
+	) st_splitter16 (
+		.clk                 (st_splitter16_clk_clk),            //   clk.clk
+		.reset               (st_splitter16_reset_reset),        // reset.reset
+		.in0_ready           (st_splitter16_in_ready),           //    in.ready
+		.in0_valid           (st_splitter16_in_valid),           //      .valid
+		.in0_startofpacket   (st_splitter16_in_startofpacket),   //      .startofpacket
+		.in0_endofpacket     (st_splitter16_in_endofpacket),     //      .endofpacket
+		.in0_empty           (st_splitter16_in_empty),           //      .empty
+		.in0_data            (st_splitter16_in_data),            //      .data
+		.out0_ready          (st_splitter16_out0_ready),         //  out0.ready
+		.out0_valid          (st_splitter16_out0_valid),         //      .valid
+		.out0_startofpacket  (st_splitter16_out0_startofpacket), //      .startofpacket
+		.out0_endofpacket    (st_splitter16_out0_endofpacket),   //      .endofpacket
+		.out0_empty          (st_splitter16_out0_empty),         //      .empty
+		.out0_data           (st_splitter16_out0_data),          //      .data
+		.out1_ready          (st_splitter16_out1_ready),         //  out1.ready
+		.out1_valid          (st_splitter16_out1_valid),         //      .valid
+		.out1_startofpacket  (st_splitter16_out1_startofpacket), //      .startofpacket
+		.out1_endofpacket    (st_splitter16_out1_endofpacket),   //      .endofpacket
+		.out1_empty          (st_splitter16_out1_empty),         //      .empty
+		.out1_data           (st_splitter16_out1_data),          //      .data
+		.in0_channel         (1'b0),                             // (terminated)
+		.in0_error           (1'b0),                             // (terminated)
+		.out0_channel        (),                                 // (terminated)
+		.out0_error          (),                                 // (terminated)
+		.out1_channel        (),                                 // (terminated)
+		.out1_error          (),                                 // (terminated)
+		.out2_ready          (1'b1),                             // (terminated)
+		.out2_valid          (),                                 // (terminated)
+		.out2_startofpacket  (),                                 // (terminated)
+		.out2_endofpacket    (),                                 // (terminated)
+		.out2_empty          (),                                 // (terminated)
+		.out2_channel        (),                                 // (terminated)
+		.out2_error          (),                                 // (terminated)
+		.out2_data           (),                                 // (terminated)
+		.out3_ready          (1'b1),                             // (terminated)
+		.out3_valid          (),                                 // (terminated)
+		.out3_startofpacket  (),                                 // (terminated)
+		.out3_endofpacket    (),                                 // (terminated)
+		.out3_empty          (),                                 // (terminated)
+		.out3_channel        (),                                 // (terminated)
+		.out3_error          (),                                 // (terminated)
+		.out3_data           (),                                 // (terminated)
+		.out4_ready          (1'b1),                             // (terminated)
+		.out4_valid          (),                                 // (terminated)
+		.out4_startofpacket  (),                                 // (terminated)
+		.out4_endofpacket    (),                                 // (terminated)
+		.out4_empty          (),                                 // (terminated)
+		.out4_channel        (),                                 // (terminated)
+		.out4_error          (),                                 // (terminated)
+		.out4_data           (),                                 // (terminated)
+		.out5_ready          (1'b1),                             // (terminated)
+		.out5_valid          (),                                 // (terminated)
+		.out5_startofpacket  (),                                 // (terminated)
+		.out5_endofpacket    (),                                 // (terminated)
+		.out5_empty          (),                                 // (terminated)
+		.out5_channel        (),                                 // (terminated)
+		.out5_error          (),                                 // (terminated)
+		.out5_data           (),                                 // (terminated)
+		.out6_ready          (1'b1),                             // (terminated)
+		.out6_valid          (),                                 // (terminated)
+		.out6_startofpacket  (),                                 // (terminated)
+		.out6_endofpacket    (),                                 // (terminated)
+		.out6_empty          (),                                 // (terminated)
+		.out6_channel        (),                                 // (terminated)
+		.out6_error          (),                                 // (terminated)
+		.out6_data           (),                                 // (terminated)
+		.out7_ready          (1'b1),                             // (terminated)
+		.out7_valid          (),                                 // (terminated)
+		.out7_startofpacket  (),                                 // (terminated)
+		.out7_endofpacket    (),                                 // (terminated)
+		.out7_empty          (),                                 // (terminated)
+		.out7_channel        (),                                 // (terminated)
+		.out7_error          (),                                 // (terminated)
+		.out7_data           (),                                 // (terminated)
+		.out8_ready          (1'b1),                             // (terminated)
+		.out8_valid          (),                                 // (terminated)
+		.out8_startofpacket  (),                                 // (terminated)
+		.out8_endofpacket    (),                                 // (terminated)
+		.out8_empty          (),                                 // (terminated)
+		.out8_channel        (),                                 // (terminated)
+		.out8_error          (),                                 // (terminated)
+		.out8_data           (),                                 // (terminated)
+		.out9_ready          (1'b1),                             // (terminated)
+		.out9_valid          (),                                 // (terminated)
+		.out9_startofpacket  (),                                 // (terminated)
+		.out9_endofpacket    (),                                 // (terminated)
+		.out9_empty          (),                                 // (terminated)
+		.out9_channel        (),                                 // (terminated)
+		.out9_error          (),                                 // (terminated)
+		.out9_data           (),                                 // (terminated)
+		.out10_ready         (1'b1),                             // (terminated)
+		.out10_valid         (),                                 // (terminated)
+		.out10_startofpacket (),                                 // (terminated)
+		.out10_endofpacket   (),                                 // (terminated)
+		.out10_empty         (),                                 // (terminated)
+		.out10_channel       (),                                 // (terminated)
+		.out10_error         (),                                 // (terminated)
+		.out10_data          (),                                 // (terminated)
+		.out11_ready         (1'b1),                             // (terminated)
+		.out11_valid         (),                                 // (terminated)
+		.out11_startofpacket (),                                 // (terminated)
+		.out11_endofpacket   (),                                 // (terminated)
+		.out11_empty         (),                                 // (terminated)
+		.out11_channel       (),                                 // (terminated)
+		.out11_error         (),                                 // (terminated)
+		.out11_data          (),                                 // (terminated)
+		.out12_ready         (1'b1),                             // (terminated)
+		.out12_valid         (),                                 // (terminated)
+		.out12_startofpacket (),                                 // (terminated)
+		.out12_endofpacket   (),                                 // (terminated)
+		.out12_empty         (),                                 // (terminated)
+		.out12_channel       (),                                 // (terminated)
+		.out12_error         (),                                 // (terminated)
+		.out12_data          (),                                 // (terminated)
+		.out13_ready         (1'b1),                             // (terminated)
+		.out13_valid         (),                                 // (terminated)
+		.out13_startofpacket (),                                 // (terminated)
+		.out13_endofpacket   (),                                 // (terminated)
+		.out13_empty         (),                                 // (terminated)
+		.out13_channel       (),                                 // (terminated)
+		.out13_error         (),                                 // (terminated)
+		.out13_data          (),                                 // (terminated)
+		.out14_ready         (1'b1),                             // (terminated)
+		.out14_valid         (),                                 // (terminated)
+		.out14_startofpacket (),                                 // (terminated)
+		.out14_endofpacket   (),                                 // (terminated)
+		.out14_empty         (),                                 // (terminated)
+		.out14_channel       (),                                 // (terminated)
+		.out14_error         (),                                 // (terminated)
+		.out14_data          (),                                 // (terminated)
+		.out15_ready         (1'b1),                             // (terminated)
+		.out15_valid         (),                                 // (terminated)
+		.out15_startofpacket (),                                 // (terminated)
+		.out15_endofpacket   (),                                 // (terminated)
+		.out15_empty         (),                                 // (terminated)
+		.out15_channel       (),                                 // (terminated)
+		.out15_error         (),                                 // (terminated)
+		.out15_data          ()                                  // (terminated)
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v
new file mode 100644
index 0000000..a846124
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v
@@ -0,0 +1,84 @@
+//a module bridge the avalon streaming interfaces with data length from 32 bit to 16 bit
+//long to short
+//32 bits to 16 bits [31:16] streaming out first and then [15:0]
+//ST long to ST short
+
+
+
+//tested by stl2sts_tb.v
+module stl2sts(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	output  wire [15:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire        data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE1 = 2'd1; //streaming [31:16]
+	localparam STATE2 = 2'd3; //streaming [15:0]
+	localparam STATE_LOCK = 2'd2; //Finishing streaming
+	
+	assign data_in_ready = (state == STATE2 && data_out_ready)? 1'b1:1'b0;
+	
+	assign data_out_data = (state == STATE1)? data_in_data[31:16]:(state== STATE2)? data_in_data[15:0]: 16'b0;
+	assign data_out_valid = (state == STATE1 || state == STATE2)?data_in_valid:1'b0;
+	assign data_out_empty = 1'b0;
+	assign data_out_startofpacket = (state == STATE1)? data_in_startofpacket: 1'b0;
+	assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			state <= STATE_IDLE;
+		else case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket)
+				state <= STATE1;
+		end
+		STATE1:
+		begin
+			if (data_in_valid && data_out_ready)
+				state <= STATE2;
+		end
+		STATE2:
+		begin
+			if (data_in_valid && data_out_ready)
+			begin
+				if (data_in_endofpacket)
+					state <= STATE_LOCK;
+				else
+					state <= STATE1;
+			end
+		end
+		STATE_LOCK:
+			state <= STATE_IDLE;
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+	
+
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.debuginfo b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.debuginfo
new file mode 100644
index 0000000..305ba5b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.debuginfo
@@ -0,0 +1,1318 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="unsaved" kind="system" version="19.1" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.18.17:16:55 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1721315815</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value>sensor_algo_qsys.qpf</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_recon_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier>D85ED36C91FB00000190C66AF154</uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.qip b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.qip
new file mode 100644
index 0000000..85733f5
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.qip
@@ -0,0 +1,49 @@
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_TOOL_VERSION "19.1"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "unsaved" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../unsaved.sopcinfo"]
+set_global_assignment -entity "unsaved" -library "unsaved" -name SLD_INFO "QSYS_NAME unsaved HAS_SOPCINFO 1 GENERATION_ID 1721315815"
+set_global_assignment -library "unsaved" -name MISC_FILE [file join $::quartus(qip_path) "../unsaved.cmp"]
+set_global_assignment -library "unsaved" -name SLD_FILE [file join $::quartus(qip_path) "unsaved.debuginfo"]
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_QSYS_MODE "SYSTEM"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "unsaved" -name MISC_FILE [file join $::quartus(qip_path) "../../unsaved.qsys"]
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_NAME "dW5zYXZlZA=="
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_DISPLAY_NAME "dW5zYXZlZA=="
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyMTMxNTgxNQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DQUxJQlJBVElPTl9SQU1fSU5URVJGQUNFX0FERFJFU1NfV0lEVEg=::QWRkcmVzc1dpZHRoID0gLTE=::QXV0byBBRERSRVNTX1dJRFRI"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "unsaved" -library "unsaved" -name IP_COMPONENT_PARAMETER "QVVUT19TRU5TT1JfUkVDT05fMF9DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_NAME "c2Vuc29yX2FsZ28="
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_DISPLAY_NAME "c2Vuc29yX3JlY29uX3Jtc19jYWxp"
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_AUTHOR "UWluLExpcWluZyAxNy5KdWx5LDIwMjQ="
+set_global_assignment -entity "sensor_algo" -library "unsaved" -name IP_COMPONENT_VERSION "MQ=="
+
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "unsaved.v"]
+set_global_assignment -library "unsaved" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rms.sv"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/stl2sts.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/calibration.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/algo_top_cl_cali_rms.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_interface.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_rx.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/serial_tx.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sensor_algo.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/bkg_subtraction_pipe.v"]
+set_global_assignment -library "unsaved" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/cluster_locate.sv"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/data_caled_ram.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/st_splitter16.v"]
+set_global_assignment -library "unsaved" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_splitter.sv"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/div.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sqrt.v"]
+set_global_assignment -library "unsaved" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/ram4bkg.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.v b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.v
new file mode 100644
index 0000000..cf1c6de
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/synthesis/unsaved.v
@@ -0,0 +1,70 @@
+// unsaved.v
+
+// Generated using ACDS version 19.1 670
+
+`timescale 1 ps / 1 ps
+module unsaved (
+		output wire [8:0]  sensor_recon_0_calibration_ram_interface_address,     // sensor_recon_0_calibration_ram_interface.address
+		output wire        sensor_recon_0_calibration_ram_interface_read,        //                                         .read
+		input  wire [15:0] sensor_recon_0_calibration_ram_interface_readdata,    //                                         .readdata
+		input  wire        sensor_recon_0_calibration_ram_interface_waitrequest, //                                         .waitrequest
+		input  wire        sensor_recon_0_clk_clk,                               //                       sensor_recon_0_clk.clk
+		input  wire [1:0]  sensor_recon_0_csr_address,                           //                       sensor_recon_0_csr.address
+		input  wire        sensor_recon_0_csr_read,                              //                                         .read
+		output wire [31:0] sensor_recon_0_csr_readdata,                          //                                         .readdata
+		input  wire        sensor_recon_0_csr_write,                             //                                         .write
+		input  wire [31:0] sensor_recon_0_csr_writedata,                         //                                         .writedata
+		input  wire [3:0]  sensor_recon_0_csr_byteenable,                        //                                         .byteenable
+		output wire        sensor_recon_0_data_out_endofpacket,                  //                  sensor_recon_0_data_out.endofpacket
+		output wire [31:0] sensor_recon_0_data_out_data,                         //                                         .data
+		output wire [1:0]  sensor_recon_0_data_out_empty,                        //                                         .empty
+		input  wire        sensor_recon_0_data_out_ready,                        //                                         .ready
+		output wire        sensor_recon_0_data_out_startofpacket,                //                                         .startofpacket
+		output wire        sensor_recon_0_data_out_valid,                        //                                         .valid
+		input  wire        sensor_recon_0_rst_reset,                             //                       sensor_recon_0_rst.reset
+		input  wire [4:0]  sensor_recon_0_sensor_in_adc_data,                    //                    sensor_recon_0_sensor.in_adc_data
+		input  wire        sensor_recon_0_sensor_in_trg,                         //                                         .in_trg
+		output wire        sensor_recon_0_sensor_out_adc_clk,                    //                                         .out_adc_clk
+		output wire        sensor_recon_0_sensor_out_adc_cnv,                    //                                         .out_adc_cnv
+		output wire        sensor_recon_0_sensor_out_sensor_clk,                 //                                         .out_sensor_clk
+		output wire        sensor_recon_0_sensor_out_sensor_gain,                //                                         .out_sensor_gain
+		output wire        sensor_recon_0_sensor_out_sensor_rst,                 //                                         .out_sensor_rst
+		output wire [7:0]  sensor_recon_0_status_out_status_out,                 //                sensor_recon_0_status_out.status_out
+		input  wire [7:0]  sensor_recon_0_synchro_ext_input,                     //                   sensor_recon_0_synchro.ext_input
+		input  wire        sensor_recon_0_synchro_serial_rx,                     //                                         .serial_rx
+		output wire        sensor_recon_0_synchro_serial_tx                      //                                         .serial_tx
+	);
+
+	sensor_algo sensor_recon_0 (
+		.csr_address            (sensor_recon_0_csr_address),                           //                       csr.address
+		.csr_read               (sensor_recon_0_csr_read),                              //                          .read
+		.csr_readdata           (sensor_recon_0_csr_readdata),                          //                          .readdata
+		.csr_write              (sensor_recon_0_csr_write),                             //                          .write
+		.csr_writedata          (sensor_recon_0_csr_writedata),                         //                          .writedata
+		.csr_byteenable         (sensor_recon_0_csr_byteenable),                        //                          .byteenable
+		.data_out_endofpacket   (sensor_recon_0_data_out_endofpacket),                  //                  data_out.endofpacket
+		.data_out_data          (sensor_recon_0_data_out_data),                         //                          .data
+		.data_out_empty         (sensor_recon_0_data_out_empty),                        //                          .empty
+		.data_out_ready         (sensor_recon_0_data_out_ready),                        //                          .ready
+		.data_out_startofpacket (sensor_recon_0_data_out_startofpacket),                //                          .startofpacket
+		.data_out_valid         (sensor_recon_0_data_out_valid),                        //                          .valid
+		.clk_clk                (sensor_recon_0_clk_clk),                               //                       clk.clk
+		.rst_reset              (sensor_recon_0_rst_reset),                             //                       rst.reset
+		.in_adc_data            (sensor_recon_0_sensor_in_adc_data),                    //                    sensor.in_adc_data
+		.in_trg                 (sensor_recon_0_sensor_in_trg),                         //                          .in_trg
+		.out_adc_clk            (sensor_recon_0_sensor_out_adc_clk),                    //                          .out_adc_clk
+		.out_adc_cnv            (sensor_recon_0_sensor_out_adc_cnv),                    //                          .out_adc_cnv
+		.out_sensor_clk         (sensor_recon_0_sensor_out_sensor_clk),                 //                          .out_sensor_clk
+		.out_sensor_gain        (sensor_recon_0_sensor_out_sensor_gain),                //                          .out_sensor_gain
+		.out_sensor_rst         (sensor_recon_0_sensor_out_sensor_rst),                 //                          .out_sensor_rst
+		.status_out             (sensor_recon_0_status_out_status_out),                 //                status_out.status_out
+		.ext_input              (sensor_recon_0_synchro_ext_input),                     //                   synchro.ext_input
+		.serial_rx              (sensor_recon_0_synchro_serial_rx),                     //                          .serial_rx
+		.serial_tx              (sensor_recon_0_synchro_serial_tx),                     //                          .serial_tx
+		.address                (sensor_recon_0_calibration_ram_interface_address),     // calibration_ram_interface.address
+		.clken                  (sensor_recon_0_calibration_ram_interface_read),        //                          .read
+		.cali_fac               (sensor_recon_0_calibration_ram_interface_readdata),    //                          .readdata
+		.waitrequest            (sensor_recon_0_calibration_ram_interface_waitrequest)  //                          .waitrequest
+	);
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.bsf b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.bsf
new file mode 100644
index 0000000..ee52f73
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.bsf
@@ -0,0 +1,294 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 688 512)
+	(text "unsaved" (rect 321 -1 355 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 496 20 508)(font "Arial" ))
+	(port
+		(pt 688 104)
+		(input)
+		(text "sensor_recon_0_calibration_ram_interface_readdata[15..0]" (rect 0 0 236 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_readdata[15..0]" (rect 394 93 730 104)(font "Arial" (font_size 8)))
+		(line (pt 688 104)(pt 384 104)(line_width 3))
+	)
+	(port
+		(pt 688 120)
+		(input)
+		(text "sensor_recon_0_calibration_ram_interface_waitrequest" (rect 0 0 221 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_waitrequest" (rect 407 109 719 120)(font "Arial" (font_size 8)))
+		(line (pt 688 120)(pt 384 120)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "sensor_recon_0_clk_clk" (rect 0 0 99 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_clk_clk" (rect 4 61 136 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 240 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "sensor_recon_0_csr_address[1..0]" (rect 0 0 141 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_address[1..0]" (rect 4 101 196 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 240 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "sensor_recon_0_csr_read" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_read" (rect 4 117 142 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 240 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "sensor_recon_0_csr_write" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_write" (rect 4 149 148 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 240 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "sensor_recon_0_csr_writedata[31..0]" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_writedata[31..0]" (rect 4 165 214 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 240 176)(line_width 3))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "sensor_recon_0_csr_byteenable[3..0]" (rect 0 0 153 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_byteenable[3..0]" (rect 4 181 214 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 240 192)(line_width 3))
+	)
+	(port
+		(pt 688 208)
+		(input)
+		(text "sensor_recon_0_data_out_ready" (rect 0 0 135 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_ready" (rect 519 197 693 208)(font "Arial" (font_size 8)))
+		(line (pt 688 208)(pt 384 208)(line_width 1))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "sensor_recon_0_rst_reset" (rect 0 0 108 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_rst_reset" (rect 4 221 148 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 240 232)(line_width 1))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "sensor_recon_0_sensor_in_adc_data[4..0]" (rect 0 0 174 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_in_adc_data[4..0]" (rect 4 261 238 272)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 240 272)(line_width 3))
+	)
+	(port
+		(pt 0 288)
+		(input)
+		(text "sensor_recon_0_sensor_in_trg" (rect 0 0 127 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_in_trg" (rect 4 277 172 288)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 240 288)(line_width 1))
+	)
+	(port
+		(pt 0 448)
+		(input)
+		(text "sensor_recon_0_synchro_ext_input[7..0]" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_ext_input[7..0]" (rect 4 437 232 448)(font "Arial" (font_size 8)))
+		(line (pt 0 448)(pt 240 448)(line_width 3))
+	)
+	(port
+		(pt 0 464)
+		(input)
+		(text "sensor_recon_0_synchro_serial_rx" (rect 0 0 145 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_serial_rx" (rect 4 453 196 464)(font "Arial" (font_size 8)))
+		(line (pt 0 464)(pt 240 464)(line_width 1))
+	)
+	(port
+		(pt 688 72)
+		(output)
+		(text "sensor_recon_0_calibration_ram_interface_address[8..0]" (rect 0 0 230 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_address[8..0]" (rect 401 61 725 72)(font "Arial" (font_size 8)))
+		(line (pt 688 72)(pt 384 72)(line_width 3))
+	)
+	(port
+		(pt 688 88)
+		(output)
+		(text "sensor_recon_0_calibration_ram_interface_read" (rect 0 0 195 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_calibration_ram_interface_read" (rect 443 77 713 88)(font "Arial" (font_size 8)))
+		(line (pt 688 88)(pt 384 88)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(output)
+		(text "sensor_recon_0_csr_readdata[31..0]" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_csr_readdata[31..0]" (rect 4 133 208 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 240 144)(line_width 3))
+	)
+	(port
+		(pt 688 160)
+		(output)
+		(text "sensor_recon_0_data_out_endofpacket" (rect 0 0 160 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_endofpacket" (rect 486 149 696 160)(font "Arial" (font_size 8)))
+		(line (pt 688 160)(pt 384 160)(line_width 1))
+	)
+	(port
+		(pt 688 176)
+		(output)
+		(text "sensor_recon_0_data_out_data[31..0]" (rect 0 0 152 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_data[31..0]" (rect 498 165 708 176)(font "Arial" (font_size 8)))
+		(line (pt 688 176)(pt 384 176)(line_width 3))
+	)
+	(port
+		(pt 688 192)
+		(output)
+		(text "sensor_recon_0_data_out_empty[1..0]" (rect 0 0 156 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_empty[1..0]" (rect 496 181 706 192)(font "Arial" (font_size 8)))
+		(line (pt 688 192)(pt 384 192)(line_width 3))
+	)
+	(port
+		(pt 688 224)
+		(output)
+		(text "sensor_recon_0_data_out_startofpacket" (rect 0 0 164 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_startofpacket" (rect 482 213 704 224)(font "Arial" (font_size 8)))
+		(line (pt 688 224)(pt 384 224)(line_width 1))
+	)
+	(port
+		(pt 688 240)
+		(output)
+		(text "sensor_recon_0_data_out_valid" (rect 0 0 129 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_data_out_valid" (rect 525 229 699 240)(font "Arial" (font_size 8)))
+		(line (pt 688 240)(pt 384 240)(line_width 1))
+	)
+	(port
+		(pt 0 304)
+		(output)
+		(text "sensor_recon_0_sensor_out_adc_clk" (rect 0 0 153 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_adc_clk" (rect 4 293 202 304)(font "Arial" (font_size 8)))
+		(line (pt 0 304)(pt 240 304)(line_width 1))
+	)
+	(port
+		(pt 0 320)
+		(output)
+		(text "sensor_recon_0_sensor_out_adc_cnv" (rect 0 0 158 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_adc_cnv" (rect 4 309 202 320)(font "Arial" (font_size 8)))
+		(line (pt 0 320)(pt 240 320)(line_width 1))
+	)
+	(port
+		(pt 0 336)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_clk" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_clk" (rect 4 325 220 336)(font "Arial" (font_size 8)))
+		(line (pt 0 336)(pt 240 336)(line_width 1))
+	)
+	(port
+		(pt 0 352)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_gain" (rect 0 0 171 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_gain" (rect 4 341 226 352)(font "Arial" (font_size 8)))
+		(line (pt 0 352)(pt 240 352)(line_width 1))
+	)
+	(port
+		(pt 0 368)
+		(output)
+		(text "sensor_recon_0_sensor_out_sensor_rst" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_sensor_out_sensor_rst" (rect 4 357 220 368)(font "Arial" (font_size 8)))
+		(line (pt 0 368)(pt 240 368)(line_width 1))
+	)
+	(port
+		(pt 0 408)
+		(output)
+		(text "sensor_recon_0_status_out_status_out[7..0]" (rect 0 0 180 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_status_out_status_out[7..0]" (rect 4 397 256 408)(font "Arial" (font_size 8)))
+		(line (pt 0 408)(pt 240 408)(line_width 3))
+	)
+	(port
+		(pt 0 480)
+		(output)
+		(text "sensor_recon_0_synchro_serial_tx" (rect 0 0 143 12)(font "Arial" (font_size 8)))
+		(text "sensor_recon_0_synchro_serial_tx" (rect 4 469 196 480)(font "Arial" (font_size 8)))
+		(line (pt 0 480)(pt 240 480)(line_width 1))
+	)
+	(drawing
+		(text "sensor_recon_0_calibration_ram_interface" (rect 385 43 1010 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 347 67 736 144)(font "Arial" (color 0 0 0)))
+		(text "read" (rect 362 83 748 176)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 344 99 736 208)(font "Arial" (color 0 0 0)))
+		(text "waitrequest" (rect 333 115 732 240)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_clk" (rect 122 43 352 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 245 67 508 144)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_csr" (rect 120 83 348 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "address" (rect 245 107 532 224)(font "Arial" (color 0 0 0)))
+		(text "read" (rect 245 123 514 256)(font "Arial" (color 0 0 0)))
+		(text "readdata" (rect 245 139 538 288)(font "Arial" (color 0 0 0)))
+		(text "write" (rect 245 155 520 320)(font "Arial" (color 0 0 0)))
+		(text "writedata" (rect 245 171 544 352)(font "Arial" (color 0 0 0)))
+		(text "byteenable" (rect 245 187 550 384)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_data_out" (rect 385 131 908 275)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "endofpacket" (rect 329 155 724 320)(font "Arial" (color 0 0 0)))
+		(text "data" (rect 363 171 750 352)(font "Arial" (color 0 0 0)))
+		(text "empty" (rect 354 187 738 384)(font "Arial" (color 0 0 0)))
+		(text "ready" (rect 356 203 742 416)(font "Arial" (color 0 0 0)))
+		(text "startofpacket" (rect 324 219 726 448)(font "Arial" (color 0 0 0)))
+		(text "valid" (rect 361 235 752 480)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_rst" (rect 122 203 352 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 245 227 520 464)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_sensor" (rect 98 243 322 499)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "in_adc_data" (rect 245 267 556 544)(font "Arial" (color 0 0 0)))
+		(text "in_trg" (rect 245 283 526 576)(font "Arial" (color 0 0 0)))
+		(text "out_adc_clk" (rect 245 299 556 608)(font "Arial" (color 0 0 0)))
+		(text "out_adc_cnv" (rect 245 315 556 640)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_clk" (rect 245 331 574 672)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_gain" (rect 245 347 580 704)(font "Arial" (color 0 0 0)))
+		(text "out_sensor_rst" (rect 245 363 574 736)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_status_out" (rect 76 379 302 771)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "status_out" (rect 245 403 550 816)(font "Arial" (color 0 0 0)))
+		(text "sensor_recon_0_synchro" (rect 93 419 318 851)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "ext_input" (rect 245 443 544 896)(font "Arial" (color 0 0 0)))
+		(text "serial_rx" (rect 245 459 544 928)(font "Arial" (color 0 0 0)))
+		(text "serial_tx" (rect 245 475 544 960)(font "Arial" (color 0 0 0)))
+		(text " unsaved " (rect 649 496 1352 1002)(font "Arial" ))
+		(line (pt 240 32)(pt 384 32)(line_width 1))
+		(line (pt 384 32)(pt 384 496)(line_width 1))
+		(line (pt 240 496)(pt 384 496)(line_width 1))
+		(line (pt 240 32)(pt 240 496)(line_width 1))
+		(line (pt 383 52)(pt 383 124)(line_width 1))
+		(line (pt 382 52)(pt 382 124)(line_width 1))
+		(line (pt 241 52)(pt 241 76)(line_width 1))
+		(line (pt 242 52)(pt 242 76)(line_width 1))
+		(line (pt 241 92)(pt 241 196)(line_width 1))
+		(line (pt 242 92)(pt 242 196)(line_width 1))
+		(line (pt 383 140)(pt 383 244)(line_width 1))
+		(line (pt 382 140)(pt 382 244)(line_width 1))
+		(line (pt 241 212)(pt 241 236)(line_width 1))
+		(line (pt 242 212)(pt 242 236)(line_width 1))
+		(line (pt 241 252)(pt 241 372)(line_width 1))
+		(line (pt 242 252)(pt 242 372)(line_width 1))
+		(line (pt 241 388)(pt 241 412)(line_width 1))
+		(line (pt 242 388)(pt 242 412)(line_width 1))
+		(line (pt 241 428)(pt 241 484)(line_width 1))
+		(line (pt 242 428)(pt 242 484)(line_width 1))
+		(line (pt 0 0)(pt 688 0)(line_width 1))
+		(line (pt 688 0)(pt 688 512)(line_width 1))
+		(line (pt 0 512)(pt 688 512)(line_width 1))
+		(line (pt 0 0)(pt 0 512)(line_width 1))
+	)
+)
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.xml b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.xml
new file mode 100644
index 0000000..ad0ca8c
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved.xml
@@ -0,0 +1,521 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2024.07.18.17:16:55"
+ outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="MAX 10"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="10M50DAF484C6GES"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="6"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP"
+     type="AddressMap"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH"
+     type="AddressWidthType"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE"
+     type="Long"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN"
+     type="Integer"
+     defaultValue="-1"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface
+     name="sensor_recon_0_calibration_ram_interface"
+     kind="avalon"
+     start="1">
+   <property name="adaptsTo" value="" />
+   <property name="addressGroup" value="0" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="dBSBigEndian" value="false" />
+   <property name="doStreamReads" value="false" />
+   <property name="doStreamWrites" value="false" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isAsynchronous" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isReadable" value="false" />
+   <property name="isWriteable" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maxAddressWidth" value="32" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="readLatency" value="0" />
+   <property name="readWaitTime" value="1" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="writeWaitTime" value="0" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_address"
+       direction="output"
+       role="address"
+       width="9" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_read"
+       direction="output"
+       role="read"
+       width="1" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_readdata"
+       direction="input"
+       role="readdata"
+       width="16" />
+   <port
+       name="sensor_recon_0_calibration_ram_interface_waitrequest"
+       direction="input"
+       role="waitrequest"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_clk" kind="clock" start="0">
+   <property name="clockRate" value="0" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="sensor_recon_0_clk_clk" direction="input" role="clk" width="1" />
+  </interface>
+  <interface name="sensor_recon_0_csr" kind="avalon" start="0">
+   <property name="addressAlignment" value="DYNAMIC" />
+   <property name="addressGroup" value="0" />
+   <property name="addressSpan" value="16" />
+   <property name="addressUnits" value="WORDS" />
+   <property name="alwaysBurstMaxBurst" value="false" />
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="bitsPerSymbol" value="8" />
+   <property name="bridgedAddressOffset" value="0" />
+   <property name="bridgesToMaster" value="" />
+   <property name="burstOnBurstBoundariesOnly" value="false" />
+   <property name="burstcountUnits" value="WORDS" />
+   <property name="constantBurstBehavior" value="false" />
+   <property name="explicitAddressSpan" value="0" />
+   <property name="holdTime" value="0" />
+   <property name="interleaveBursts" value="false" />
+   <property name="isBigEndian" value="false" />
+   <property name="isFlash" value="false" />
+   <property name="isMemoryDevice" value="false" />
+   <property name="isNonVolatileStorage" value="false" />
+   <property name="linewrapBursts" value="false" />
+   <property name="maximumPendingReadTransactions" value="0" />
+   <property name="maximumPendingWriteTransactions" value="0" />
+   <property name="minimumUninterruptedRunLength" value="1" />
+   <property name="printableDevice" value="false" />
+   <property name="readLatency" value="0" />
+   <property name="readWaitStates" value="1" />
+   <property name="readWaitTime" value="1" />
+   <property name="registerIncomingSignals" value="false" />
+   <property name="registerOutgoingSignals" value="false" />
+   <property name="setupTime" value="0" />
+   <property name="timingUnits" value="Cycles" />
+   <property name="transparentBridge" value="false" />
+   <property name="wellBehavedWaitrequest" value="false" />
+   <property name="writeLatency" value="0" />
+   <property name="writeWaitStates" value="0" />
+   <property name="writeWaitTime" value="0" />
+   <port
+       name="sensor_recon_0_csr_address"
+       direction="input"
+       role="address"
+       width="2" />
+   <port
+       name="sensor_recon_0_csr_read"
+       direction="input"
+       role="read"
+       width="1" />
+   <port
+       name="sensor_recon_0_csr_readdata"
+       direction="output"
+       role="readdata"
+       width="32" />
+   <port
+       name="sensor_recon_0_csr_write"
+       direction="input"
+       role="write"
+       width="1" />
+   <port
+       name="sensor_recon_0_csr_writedata"
+       direction="input"
+       role="writedata"
+       width="32" />
+   <port
+       name="sensor_recon_0_csr_byteenable"
+       direction="input"
+       role="byteenable"
+       width="4" />
+  </interface>
+  <interface name="sensor_recon_0_data_out" kind="avalon_streaming" start="1">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="sensor_recon_0_rst" />
+   <property name="beatsPerCycle" value="1" />
+   <property name="dataBitsPerSymbol" value="8" />
+   <property name="emptyWithinPacket" value="false" />
+   <property name="errorDescriptor" value="" />
+   <property name="firstSymbolInHighOrderBits" value="true" />
+   <property name="highOrderSymbolAtMSB" value="false" />
+   <property name="maxChannel" value="0" />
+   <property name="packetDescription" value="" />
+   <property name="readyLatency" value="0" />
+   <property name="symbolsPerBeat" value="1" />
+   <port
+       name="sensor_recon_0_data_out_endofpacket"
+       direction="output"
+       role="endofpacket"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_data"
+       direction="output"
+       role="data"
+       width="32" />
+   <port
+       name="sensor_recon_0_data_out_empty"
+       direction="output"
+       role="empty"
+       width="2" />
+   <port
+       name="sensor_recon_0_data_out_ready"
+       direction="input"
+       role="ready"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_startofpacket"
+       direction="output"
+       role="startofpacket"
+       width="1" />
+   <port
+       name="sensor_recon_0_data_out_valid"
+       direction="output"
+       role="valid"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_rst" kind="reset" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="synchronousEdges" value="DEASSERT" />
+   <port
+       name="sensor_recon_0_rst_reset"
+       direction="input"
+       role="reset"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_sensor" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_sensor_in_adc_data"
+       direction="input"
+       role="in_adc_data"
+       width="5" />
+   <port
+       name="sensor_recon_0_sensor_in_trg"
+       direction="input"
+       role="in_trg"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_adc_clk"
+       direction="output"
+       role="out_adc_clk"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_adc_cnv"
+       direction="output"
+       role="out_adc_cnv"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_clk"
+       direction="output"
+       role="out_sensor_clk"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_gain"
+       direction="output"
+       role="out_sensor_gain"
+       width="1" />
+   <port
+       name="sensor_recon_0_sensor_out_sensor_rst"
+       direction="output"
+       role="out_sensor_rst"
+       width="1" />
+  </interface>
+  <interface name="sensor_recon_0_status_out" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_status_out_status_out"
+       direction="output"
+       role="status_out"
+       width="8" />
+  </interface>
+  <interface name="sensor_recon_0_synchro" kind="conduit" start="0">
+   <property name="associatedClock" value="sensor_recon_0_clk" />
+   <property name="associatedReset" value="" />
+   <port
+       name="sensor_recon_0_synchro_ext_input"
+       direction="input"
+       role="ext_input"
+       width="8" />
+   <port
+       name="sensor_recon_0_synchro_serial_rx"
+       direction="input"
+       role="serial_rx"
+       width="1" />
+   <port
+       name="sensor_recon_0_synchro_serial_tx"
+       direction="output"
+       role="serial_tx"
+       width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="unsaved:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1721315815,AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP=,AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH=AddressWidth = -1,AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN=-1,AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE=-1,AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(sensor_recon:1:)"
+   instancePathKey="unsaved"
+   kind="unsaved"
+   version="1.0"
+   name="unsaved">
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN" value="-1" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP"
+     value="" />
+  <parameter name="AUTO_GENERATION_ID" value="1721315815" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE" value="-1" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN" value="-1" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
+  <parameter
+     name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/unsaved.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/div.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/unsaved.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_recon_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="unsaved">queue size: 0 starting:unsaved "unsaved"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="unsaved"><![CDATA["<b>unsaved</b>" reuses <b>sensor_recon</b> "<b>submodules/sensor_algo</b>"]]></message>
+   <message level="Debug" culprit="unsaved">queue size: 0 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_recon_0"><![CDATA["<b>unsaved</b>" instantiated <b>sensor_recon</b> "<b>sensor_recon_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="sensor_recon:1:"
+   instancePathKey="unsaved:.:sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   name="sensor_algo">
+  <generatedFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/rms.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/stl2sts.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/calibration.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_interface.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_rx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/serial_tx.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sensor_algo.v"
+       type="VERILOG"
+       attributes="TOP_LEVEL_FILE" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/cluster_locate.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/data_caled_ram.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/st_splitter16.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
+       type="SYSTEM_VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/div.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/sqrt.v"
+       type="VERILOG"
+       attributes="" />
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/ram4bkg.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_recon_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="unsaved" as="sensor_recon_0" />
+  <messages>
+   <message level="Debug" culprit="unsaved">queue size: 0 starting:sensor_recon "submodules/sensor_algo"</message>
+   <message level="Info" culprit="sensor_recon_0"><![CDATA["<b>unsaved</b>" instantiated <b>sensor_recon</b> "<b>sensor_recon_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_bb.v b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_bb.v
new file mode 100644
index 0000000..79dc5d2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_bb.v
@@ -0,0 +1,62 @@
+
+module unsaved (
+	sensor_recon_0_csr_address,
+	sensor_recon_0_csr_read,
+	sensor_recon_0_csr_readdata,
+	sensor_recon_0_csr_write,
+	sensor_recon_0_csr_writedata,
+	sensor_recon_0_csr_byteenable,
+	sensor_recon_0_data_out_endofpacket,
+	sensor_recon_0_data_out_data,
+	sensor_recon_0_data_out_empty,
+	sensor_recon_0_data_out_ready,
+	sensor_recon_0_data_out_startofpacket,
+	sensor_recon_0_data_out_valid,
+	sensor_recon_0_clk_clk,
+	sensor_recon_0_rst_reset,
+	sensor_recon_0_sensor_in_adc_data,
+	sensor_recon_0_sensor_in_trg,
+	sensor_recon_0_sensor_out_adc_clk,
+	sensor_recon_0_sensor_out_adc_cnv,
+	sensor_recon_0_sensor_out_sensor_clk,
+	sensor_recon_0_sensor_out_sensor_gain,
+	sensor_recon_0_sensor_out_sensor_rst,
+	sensor_recon_0_status_out_status_out,
+	sensor_recon_0_synchro_ext_input,
+	sensor_recon_0_synchro_serial_rx,
+	sensor_recon_0_synchro_serial_tx,
+	sensor_recon_0_calibration_ram_interface_address,
+	sensor_recon_0_calibration_ram_interface_read,
+	sensor_recon_0_calibration_ram_interface_readdata,
+	sensor_recon_0_calibration_ram_interface_waitrequest);	
+
+	input	[1:0]	sensor_recon_0_csr_address;
+	input		sensor_recon_0_csr_read;
+	output	[31:0]	sensor_recon_0_csr_readdata;
+	input		sensor_recon_0_csr_write;
+	input	[31:0]	sensor_recon_0_csr_writedata;
+	input	[3:0]	sensor_recon_0_csr_byteenable;
+	output		sensor_recon_0_data_out_endofpacket;
+	output	[31:0]	sensor_recon_0_data_out_data;
+	output	[1:0]	sensor_recon_0_data_out_empty;
+	input		sensor_recon_0_data_out_ready;
+	output		sensor_recon_0_data_out_startofpacket;
+	output		sensor_recon_0_data_out_valid;
+	input		sensor_recon_0_clk_clk;
+	input		sensor_recon_0_rst_reset;
+	input	[4:0]	sensor_recon_0_sensor_in_adc_data;
+	input		sensor_recon_0_sensor_in_trg;
+	output		sensor_recon_0_sensor_out_adc_clk;
+	output		sensor_recon_0_sensor_out_adc_cnv;
+	output		sensor_recon_0_sensor_out_sensor_clk;
+	output		sensor_recon_0_sensor_out_sensor_gain;
+	output		sensor_recon_0_sensor_out_sensor_rst;
+	output	[7:0]	sensor_recon_0_status_out_status_out;
+	input	[7:0]	sensor_recon_0_synchro_ext_input;
+	input		sensor_recon_0_synchro_serial_rx;
+	output		sensor_recon_0_synchro_serial_tx;
+	output	[8:0]	sensor_recon_0_calibration_ram_interface_address;
+	output		sensor_recon_0_calibration_ram_interface_read;
+	input	[15:0]	sensor_recon_0_calibration_ram_interface_readdata;
+	input		sensor_recon_0_calibration_ram_interface_waitrequest;
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_inst.v b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_inst.v
new file mode 100644
index 0000000..6ed6715
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/q_sys/unsaved_inst.v
@@ -0,0 +1,32 @@
+	unsaved u0 (
+		.sensor_recon_0_csr_address                           (<connected-to-sensor_recon_0_csr_address>),                           //                       sensor_recon_0_csr.address
+		.sensor_recon_0_csr_read                              (<connected-to-sensor_recon_0_csr_read>),                              //                                         .read
+		.sensor_recon_0_csr_readdata                          (<connected-to-sensor_recon_0_csr_readdata>),                          //                                         .readdata
+		.sensor_recon_0_csr_write                             (<connected-to-sensor_recon_0_csr_write>),                             //                                         .write
+		.sensor_recon_0_csr_writedata                         (<connected-to-sensor_recon_0_csr_writedata>),                         //                                         .writedata
+		.sensor_recon_0_csr_byteenable                        (<connected-to-sensor_recon_0_csr_byteenable>),                        //                                         .byteenable
+		.sensor_recon_0_data_out_endofpacket                  (<connected-to-sensor_recon_0_data_out_endofpacket>),                  //                  sensor_recon_0_data_out.endofpacket
+		.sensor_recon_0_data_out_data                         (<connected-to-sensor_recon_0_data_out_data>),                         //                                         .data
+		.sensor_recon_0_data_out_empty                        (<connected-to-sensor_recon_0_data_out_empty>),                        //                                         .empty
+		.sensor_recon_0_data_out_ready                        (<connected-to-sensor_recon_0_data_out_ready>),                        //                                         .ready
+		.sensor_recon_0_data_out_startofpacket                (<connected-to-sensor_recon_0_data_out_startofpacket>),                //                                         .startofpacket
+		.sensor_recon_0_data_out_valid                        (<connected-to-sensor_recon_0_data_out_valid>),                        //                                         .valid
+		.sensor_recon_0_clk_clk                               (<connected-to-sensor_recon_0_clk_clk>),                               //                       sensor_recon_0_clk.clk
+		.sensor_recon_0_rst_reset                             (<connected-to-sensor_recon_0_rst_reset>),                             //                       sensor_recon_0_rst.reset
+		.sensor_recon_0_sensor_in_adc_data                    (<connected-to-sensor_recon_0_sensor_in_adc_data>),                    //                    sensor_recon_0_sensor.in_adc_data
+		.sensor_recon_0_sensor_in_trg                         (<connected-to-sensor_recon_0_sensor_in_trg>),                         //                                         .in_trg
+		.sensor_recon_0_sensor_out_adc_clk                    (<connected-to-sensor_recon_0_sensor_out_adc_clk>),                    //                                         .out_adc_clk
+		.sensor_recon_0_sensor_out_adc_cnv                    (<connected-to-sensor_recon_0_sensor_out_adc_cnv>),                    //                                         .out_adc_cnv
+		.sensor_recon_0_sensor_out_sensor_clk                 (<connected-to-sensor_recon_0_sensor_out_sensor_clk>),                 //                                         .out_sensor_clk
+		.sensor_recon_0_sensor_out_sensor_gain                (<connected-to-sensor_recon_0_sensor_out_sensor_gain>),                //                                         .out_sensor_gain
+		.sensor_recon_0_sensor_out_sensor_rst                 (<connected-to-sensor_recon_0_sensor_out_sensor_rst>),                 //                                         .out_sensor_rst
+		.sensor_recon_0_status_out_status_out                 (<connected-to-sensor_recon_0_status_out_status_out>),                 //                sensor_recon_0_status_out.status_out
+		.sensor_recon_0_synchro_ext_input                     (<connected-to-sensor_recon_0_synchro_ext_input>),                     //                   sensor_recon_0_synchro.ext_input
+		.sensor_recon_0_synchro_serial_rx                     (<connected-to-sensor_recon_0_synchro_serial_rx>),                     //                                         .serial_rx
+		.sensor_recon_0_synchro_serial_tx                     (<connected-to-sensor_recon_0_synchro_serial_tx>),                     //                                         .serial_tx
+		.sensor_recon_0_calibration_ram_interface_address     (<connected-to-sensor_recon_0_calibration_ram_interface_address>),     // sensor_recon_0_calibration_ram_interface.address
+		.sensor_recon_0_calibration_ram_interface_read        (<connected-to-sensor_recon_0_calibration_ram_interface_read>),        //                                         .read
+		.sensor_recon_0_calibration_ram_interface_readdata    (<connected-to-sensor_recon_0_calibration_ram_interface_readdata>),    //                                         .readdata
+		.sensor_recon_0_calibration_ram_interface_waitrequest (<connected-to-sensor_recon_0_calibration_ram_interface_waitrequest>)  //                                         .waitrequest
+	);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/ram4bkg.qip b/FPGA_firmware/sensor_algo_qsys/ram4bkg.qip
new file mode 100644
index 0000000..1b462d2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram4bkg.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram4bkg.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram4bkg_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram4bkg_bb.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/ram4bkg.v b/FPGA_firmware/sensor_algo_qsys/ram4bkg.v
new file mode 100644
index 0000000..d4e9c5b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram4bkg.v
@@ -0,0 +1,214 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4bkg.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4bkg (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[7:0]  rdaddress;
+	input	[7:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] q = sub_wire0[31:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({32{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.numwords_b = 256,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.widthad_b = 8,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/ram4bkg_bb.v b/FPGA_firmware/sensor_algo_qsys/ram4bkg_bb.v
new file mode 100644
index 0000000..8f17aa2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram4bkg_bb.v
@@ -0,0 +1,160 @@
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4bkg.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module ram4bkg (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	[7:0]  rdaddress;
+	input	[7:0]  wraddress;
+	input	  wren;
+	output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
+// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4bkg_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/ram4bkg_inst.v b/FPGA_firmware/sensor_algo_qsys/ram4bkg_inst.v
new file mode 100644
index 0000000..075b93f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram4bkg_inst.v
@@ -0,0 +1,8 @@
+ram4bkg	ram4bkg_inst (
+	.clock ( clock_sig ),
+	.data ( data_sig ),
+	.rdaddress ( rdaddress_sig ),
+	.wraddress ( wraddress_sig ),
+	.wren ( wren_sig ),
+	.q ( q_sig )
+	);
diff --git a/FPGA_firmware/sensor_algo_qsys/ram_sim.qip b/FPGA_firmware/sensor_algo_qsys/ram_sim.qip
new file mode 100644
index 0000000..6c28c9e
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram_sim.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_sim.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_sim_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_sim_bb.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/ram_sim.v b/FPGA_firmware/sensor_algo_qsys/ram_sim.v
new file mode 100644
index 0000000..0f4e57a
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram_sim.v
@@ -0,0 +1,253 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram_sim.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram_sim (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	rden_a,
+	rden_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[15:0]  data_a;
+	input	[15:0]  data_b;
+	input	  rden_a;
+	input	  rden_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden_a;
+	tri1	  rden_b;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire [15:0] sub_wire1;
+	wire [15:0] q_a = sub_wire0[15:0];
+	wire [15:0] q_b = sub_wire1[15:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (data_a),
+				.data_b (data_b),
+				.rden_a (rden_a),
+				.rden_b (rden_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus ());
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "MAX 10",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 512,
+		altsyncram_component.numwords_b = 512,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 9,
+		altsyncram_component.widthad_b = 9,
+		altsyncram_component.width_a = 16,
+		altsyncram_component.width_b = 16,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/ram_sim_bb.v b/FPGA_firmware/sensor_algo_qsys/ram_sim_bb.v
new file mode 100644
index 0000000..ead30fa
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram_sim_bb.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram_sim.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module ram_sim (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	rden_a,
+	rden_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[8:0]  address_a;
+	input	[8:0]  address_b;
+	input	  clock;
+	input	[15:0]  data_a;
+	input	[15:0]  data_b;
+	input	  rden_a;
+	input	  rden_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[15:0]  q_a;
+	output	[15:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden_a;
+	tri1	  rden_b;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram_sim_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/ram_sim_inst.v b/FPGA_firmware/sensor_algo_qsys/ram_sim_inst.v
new file mode 100644
index 0000000..1097bc8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/ram_sim_inst.v
@@ -0,0 +1,13 @@
+ram_sim	ram_sim_inst (
+	.address_a ( address_a_sig ),
+	.address_b ( address_b_sig ),
+	.clock ( clock_sig ),
+	.data_a ( data_a_sig ),
+	.data_b ( data_b_sig ),
+	.rden_a ( rden_a_sig ),
+	.rden_b ( rden_b_sig ),
+	.wren_a ( wren_a_sig ),
+	.wren_b ( wren_b_sig ),
+	.q_a ( q_a_sig ),
+	.q_b ( q_b_sig )
+	);
diff --git a/FPGA_firmware/sensor_algo_qsys/rms.sv b/FPGA_firmware/sensor_algo_qsys/rms.sv
new file mode 100644
index 0000000..5587357
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/rms.sv
@@ -0,0 +1,396 @@
+//the module for rms
+/*
+if there is cluster:
+go through the data three times:
+first time, calc Xmean;
+second time calc Sigma;
+
+if there is no cluster:
+directly send it. 
+
+*/
+
+//
+
+//tested with algo_top_cl_cali_rms_tb.v 
+
+module rms(
+	
+	input  wire        	clk,                    //                     clk.clk
+	input  wire        	rst,         			// the reset should connect to the int_rst from sensor
+
+	//data for sig after bkg subtraction
+	input wire 			  bkg_sub_on, 					//indicate that bkg_sub is on 
+	input wire          sig_ram_last,				//the last channel is being wroten when sig_ram_last=1'b1
+	
+	output wire[8:0]		sig_rdaddress,             //0~319 for data. 500~502 for the 3 words head
+	input wire [15:0]		sig,
+	output wire 			sig_rd_eable, 					//eable read, get sig  next clock
+
+	//the output of cluster_locate
+	input wire[8:0]		sig_ch_left,	         //after sig_ram_last, if has_cluster, catch the sig_ch_left and right signal, and calc
+	input wire[8:0]		sig_ch_right,
+	input wire				has_cluster,
+	input wire				no_cluster,					// this is not used
+
+	//the result
+	output wire 			overflow,
+
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //4 * 32 bits data  
+	output  wire [31:0] to_udp_data,           //  st.data
+	input   wire        to_udp_ready,          //         .ready
+	output  wire        to_udp_valid,          //         .valid
+	output  wire [1:0]  to_udp_empty,          //         .empty
+	output  wire        to_udp_endofpacket,    //         .endofpacket
+	output  wire        to_udp_startofpacket  //         .startofpacket	
+	
+	);
+	
+	
+	
+	
+	/* reg results has 32*4 bits
+	WORDS 163 [31:16]MeanXleftshift [15:0] Sigma0;
+			164 [31:16]MaxY; [15:0] STATUS;
+			165 for debug;
+			166 for debug;
+		for status register:
+		STATUS_BKG_SUB_ON  0x0001
+		STATUS_HAS_CLUSTER 0x0002
+		STATUS_NO_CLUSTER  0x0004	
+		*/
+
+	
+	reg[31:0] results[4];
+	
+	localparam WORDS_TO_SEND = 4;	 //results[4]
+	localparam SHIFT_BITS = 2;
+
+
+	reg[3:0] state;
+	localparam STATE_IDLE = 0; //when sig_ram_last, move to STATE_JUDGE
+	localparam STATE_JUDGE = 1; 
+	/*reset registers; If has_cluster to STATE_CAL1 => WAIT_4_CLK => DIV1 => CAL2 => WAIT_6CLK => DIV2 => SQRT => LOCK => SEND=>,
+	if not to =>SEND*/
+	localparam STATE_SEND = 2; // give a start_transmission signal and start the other statemachine for sending
+	localparam STATE_CAL1 = 4;
+	localparam STATE_WAIT_4CLK = 5;
+	localparam STATE_DIV1 = 6;
+	localparam STATE_CAL2 = 7; 
+	localparam STATE_WAIT_6CLK = 8;
+	localparam STATE_DIV2 = 9;
+	localparam STATE_SQRT = 10;
+	localparam STATE_LOCK = 11; //lock the MaxY, Sigma0, and MeanXleftshift  
+	
+
+	
+	// channel_ctr is address from sig_ram
+	// arrayID depends on the channel_ctr one clock ago
+	reg[8:0] channel_ctr;
+	localparam CH_NUM = 320; //channel number, 5 array, 320 channel
+	reg[8:0] ch_right;
+	reg[8:0] ch_left;
+	reg signed[3:0] arrayID;
+	
+	assign sig_rdaddress = channel_ctr;
+	assign sig_rd_eable = (state == STATE_CAL1 || state == STATE_CAL2)? 1'b1: 1'b0;
+	
+	// registers for CAL1
+	reg signed[13:0] X[2]; 
+	reg signed[15:0] Y[3]; //only Y[0] for cal1 //Y[2], Y[1], Y[0] for cal2, pipe 
+	reg signed[15:0] MaxY;
+	reg signed[31:0] SumY;
+	reg signed[31:0] XY;
+	reg signed[34:0] SumXY;
+	wire signed[36:0] SumXYleftshift;
+	reg signed[13:0] MeanXleftshift;
+	
+	assign SumXYleftshift = SumXY << SHIFT_BITS;
+	
+	
+	//the registers for CAL2
+	reg signed[31:0] SumYm1; //SumY - 1
+	reg signed[14:0] DiffxMeanX;
+	reg signed[28:0] DiffxMeanX2;
+	reg signed[43:0] DiffxMeanX2Yi;
+	reg signed[43:0] SumDiffxMeanX2Yi;
+	reg unsigned[25:0] Sigma2;
+	reg unsigned[12:0] Sigma0;
+	
+	
+	
+	
+	//the wait_ctr for different steps in each states
+	reg unsigned[8:0] wait_ctr;
+	
+	wire div_clken;
+	wire[29:0] denom;
+	wire[39:0] numer;
+	wire[31:0] quotient;
+	assign div_clken = (state == STATE_DIV1 || state == STATE_DIV2)? 1'b1: 1'b0;
+	assign denom = (state == STATE_DIV1)? SumY[29:0]: 
+						(state == STATE_DIV2)? (SumYm1[29:0]): 30'b1;
+	assign numer = (state == STATE_DIV1)? (SumXYleftshift[35:0]) :
+						(state == STATE_DIV2)? SumDiffxMeanX2Yi[39:0]: 0;
+	localparam DIV_LATENCY = 26;
+	//division with 26 clocks latency
+	div	div1 (
+	.clken ( div_clken ),
+	.clock ( clk),
+	.denom ( denom ),
+	.numer ( numer ),
+	.quotient ( quotient )
+	);
+	
+	wire sqrt_clken;
+	wire[25:0] radical_sig;
+	wire[12:0] q_sqrt;
+	assign sqrt_clken = (state == STATE_SQRT)? 1'b1: 1'b0;
+	assign radical_sig = (state == STATE_SQRT)? Sigma2: 26'b0;
+	localparam SQRT_LATENCY = 13;
+	//sqrt with 13 clocks latency
+	sqrt	sqrt_inst (
+	.clk ( clk),
+	.ena ( sqrt_clken ),
+	.radical ( radical_sig ),
+	.q ( q_sqrt )
+	);
+	
+
+	// 12 July 2024 I should change arrayID to wires
+	//the sequential logic for arrayID
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			arrayID <= 4'd0;
+		else if (channel_ctr>=9'h0 && channel_ctr<9'h40)
+			arrayID <= 4'd0;
+		else if (channel_ctr<9'h80)
+			arrayID <= 4'd1;
+		else if (channel_ctr<9'hC0)
+			arrayID <= 4'd2;
+		else if (channel_ctr<9'h100)
+			arrayID <= 4'd3;
+		else if (channel_ctr<9'h140)
+			arrayID <= 4'd4;
+		else
+			arrayID <= 4'd0;
+	end
+	
+	
+	always @ (posedge clk or posedge rst) 
+	begin
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+		end
+		else case(state)
+		STATE_IDLE:
+		begin
+			X[0] <= 0; //For cal1
+			X[1] <= 0;
+			Y[0] <= 0;
+			MaxY <= 0;
+			XY <= 0; 
+			SumXY <= 0;
+			SumY <= 0;
+			SumDiffxMeanX2Yi <= 0;
+			wait_ctr <= 0;
+			MeanXleftshift <= 0;
+			Y[1] <= 0; //For cal2
+			Y[2] <= 0;
+			SumYm1 <= 0;
+			DiffxMeanX <= 0;
+			DiffxMeanX2 <= 0;
+			DiffxMeanX2Yi <= 0;
+			SumDiffxMeanX2Yi <= 0; 
+			Sigma2 <= 0;
+			Sigma0 <= 0;
+			results[0] <= 0; //Collect Results
+			results[1] <= 0;
+			results[2] <= 0;
+			results[3] <= 0;
+			ch_right <= 0;
+			ch_left <= 0;
+			if (sig_ram_last) begin
+				state <= STATE_JUDGE;
+			end
+		end
+		STATE_JUDGE:
+		begin
+			if (~sig_ram_last) begin
+				if (bkg_sub_on && has_cluster)	
+						state <= STATE_CAL1; 
+				else
+					state <= STATE_SEND;			
+				results[1][0] <= bkg_sub_on;
+				results[1][1] <= has_cluster;
+				results[1][2] <= no_cluster;
+				results[2][31:16] <= {7'b0,sig_ch_left};
+				results[2][15:0] <= {7'b0,sig_ch_right};
+				ch_right <= sig_ch_right;
+				ch_left <= sig_ch_left;
+				channel_ctr <= sig_ch_left;
+			end
+		end
+		STATE_CAL1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1][12:0]<= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			if (wait_ctr >= 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig;
+			end
+			if (wait_ctr>=2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr>=3) begin
+				SumXY <= SumXY + XY;
+			end			
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_4CLK;
+				channel_ctr <= ch_left;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_WAIT_4CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr < 1) begin
+				X[0] <= X[1] + arrayID;
+				Y[0] <= sig;
+			end
+			if (wait_ctr < 2) begin
+				XY <= X[0]*Y[0];
+				SumY <= SumY + Y[0];
+				if (MaxY<Y[0])
+				MaxY <= Y[0];
+			end
+			if (wait_ctr < 3) begin
+				SumXY <= SumXY + XY;
+			end
+			if (wait_ctr == 3) begin
+				state <= STATE_DIV1;
+				SumYm1 <= SumY - 1'b1;
+				wait_ctr <= 0;
+			end
+		end
+		STATE_DIV1:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				MeanXleftshift <= {1'b0,quotient[12:0]};
+				wait_ctr <= 0;
+				state <= STATE_CAL2;
+			end
+		end
+		STATE_CAL2:
+		begin
+			channel_ctr <= channel_ctr + 1'b1;
+			X[1][12:0] <= channel_ctr << 2; //here, the position is quantized in 1 per 0.2mm
+			wait_ctr <= wait_ctr + 1'b1;	
+			if (wait_ctr >= 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig;
+			end
+			if (wait_ctr >= 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr >= 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr >= 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr >= 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (channel_ctr ==ch_right) begin
+				state <= STATE_WAIT_6CLK;
+				wait_ctr <= 0;
+				channel_ctr <= ch_left;
+			end
+		end
+		STATE_WAIT_6CLK:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr < 1) begin
+				X[0] <= (X[1] + arrayID) << SHIFT_BITS; // here the position is quantized in 1 per 0.05 mm when SHIFT_BITS = 2
+				Y[2] <= sig;
+			end
+			if (wait_ctr < 2) begin
+				Y[1] <= Y[2];
+				DiffxMeanX <= X[0] - MeanXleftshift;
+			end
+			if (wait_ctr < 3) begin
+				Y[0] <= Y[1];
+				DiffxMeanX2 <= DiffxMeanX * DiffxMeanX;
+			end
+			if (wait_ctr < 4) begin
+				DiffxMeanX2Yi <= DiffxMeanX2*Y[0];
+			end
+			if (wait_ctr < 5) begin
+				SumDiffxMeanX2Yi <= SumDiffxMeanX2Yi + DiffxMeanX2Yi;
+			end
+			if (wait_ctr == 5) begin
+				wait_ctr <= 0;
+				state <= STATE_DIV2;
+			end
+		end
+		STATE_DIV2:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == DIV_LATENCY)
+			begin
+				Sigma2 <= quotient[25:0];
+				wait_ctr <= 0;
+				state <= STATE_SQRT;
+			end
+		end
+		STATE_SQRT:
+		begin
+			wait_ctr <= wait_ctr + 1'b1;
+			if (wait_ctr == SQRT_LATENCY)
+			begin
+				state <= STATE_LOCK;
+				wait_ctr <= 0;
+				Sigma0 <= q_sqrt;
+			end
+		end
+		STATE_LOCK:
+		begin
+			results[0][31:16] <= MeanXleftshift;
+			results[0][15:0] <= Sigma0;
+			results[1][31:16] <= MaxY;
+			state <=  STATE_SEND;
+		end
+		STATE_SEND:
+		begin
+			if (to_udp_ready)
+			begin
+				wait_ctr <= wait_ctr + 1'b1;
+				if (wait_ctr == WORDS_TO_SEND-1)
+					state <= STATE_IDLE;
+			end
+		end
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	assign to_udp_data = (state == STATE_SEND)? results[wait_ctr]:32'b0;
+	assign to_udp_empty = 2'b0;
+	assign to_udp_startofpacket = (state == STATE_SEND && wait_ctr == 9'b0)? 1'b1: 1'b0;
+	assign to_udp_valid = (state == STATE_SEND)? 1'b1: 1'b0;
+	assign to_udp_endofpacket = (state == STATE_SEND && wait_ctr == (WORDS_TO_SEND-1))? 1'b1: 1'b0;
+	
+	
+	
+	endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo.sopcinfo b/FPGA_firmware/sensor_algo_qsys/sensor_algo.sopcinfo
new file mode 100644
index 0000000..3bf0f59
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo.sopcinfo
@@ -0,0 +1,1260 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="sensor_algo" kind="sensor_algo" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.17.13:03:39 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1721214219</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>sensor_algo_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_algo_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_algo_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_algo_0"
+   kind="sensor_algo"
+   version="1.0"
+   path="sensor_algo_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="avalon_master" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>SYMBOLS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_algo</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_algo(rms)</displayName>
+  <version>1.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo.v b/FPGA_firmware/sensor_algo_qsys/sensor_algo.v
new file mode 100644
index 0000000..616096b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo.v
@@ -0,0 +1,139 @@
+//module sensor_algo
+//combine sensor_interface bkg_subtraction, cluster_locate, and calibration, and rms
+
+
+module sensor_algo(
+
+	//Clock/reset
+	input  wire        	clk_clk,                    //                     clk.clk
+	input  wire        	rst_reset,                  //                     rst.reset
+	//Avalon MM slave
+	input  wire [1:0]  	csr_address,                //            avalon_slave.address
+	input  wire        	csr_read,                   //                        .read
+	output wire [31:0] 	csr_readdata,               //                        .readdata
+	input  wire        	csr_write,                  //                        .write
+	input  wire [31:0] 	csr_writedata,              //                        .writedata
+	input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+	//Avalon ST transmitter
+	output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+	output wire        	data_out_endofpacket,   	//                        .endofpacket
+	output wire        	data_out_startofpacket, 	//                        .startofpacket
+	input  wire        	data_out_ready,         	//                        .ready
+	output wire        	data_out_valid,         	//                        .valid
+	output wire [1:0]  	data_out_empty,         	//                        .empty
+	//Sensor interface
+	input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+	output wire        	out_adc_clk,                //                        .out_dac_clk
+	output wire        	out_adc_cnv,                //                        .out_dac_cnv
+	input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+	output wire        	out_sensor_rst,             //                        .out_sensor_rst
+	output wire        	out_sensor_clk,             //                        .out_sensor_clk
+	output wire        	out_sensor_gain,            //                        .out_sensor_gain
+	//Serial synchro interface
+	input  wire	   		serial_rx,					//receive data
+	output wire	   		serial_tx,					//send data
+	input  wire [7:0]  	ext_input,					//SMA etc.
+	//Debug information
+	output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+	
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
+	output wire [8:0] 	address,
+	output wire 			clken,
+	input  wire [15:0] 	cali_fac,
+	input	 wire				waitrequest
+	
+);
+	
+
+	wire [31:0] data_out_data1;   // Output data
+	wire data_out_endofpacket1;    // Output end-of-packet signal
+	wire data_out_startofpacket1;  // Output start-of-packet signal
+	wire data_out_ready1;         // Output ready signal
+	wire data_out_valid1;         // Output valid signal
+	wire [1:0] data_out_empty1;   // Output empty signal
+
+	wire int_rst;
+	wire [7:0] cluster_threshold;
+	wire [7:0] cluster_size;
+	wire [7:0] in_algo_threshold;
+
+	  
+
+	sensor_interface the_sensor_interface (
+		.clk_clk			(clk_clk),                //      clk.clk
+		.rst_reset			(rst_reset),              //      rst.reset
+		
+		.csr_address			(csr_address),            //      csr.address
+		.csr_write			(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read			(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		
+		.data_out_data			(data_out_data1),          // data_out.data
+		.data_out_empty			(data_out_empty1),         //         .empty
+		.data_out_endofpacket		(data_out_endofpacket1),   //         .endofpacket
+		.data_out_startofpacket		(data_out_startofpacket1),//         .startofpacket
+		.data_out_ready			(data_out_ready1),         //         .ready
+		.data_out_valid			(data_out_valid1),          //         .valid
+		
+		.in_trg 			(in_trg),                                //                  sensor.in_trg
+		.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+		.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+		.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+		.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+		.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+		.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+		.serial_rx			(serial_rx),		//receive data
+		.serial_tx			(serial_tx),		//send data
+		.ext_input			(ext_input),			//SMA etc.
+		
+		.int_rst          (int_rst),
+		.cluster_threshold		(cluster_threshold),
+		.cluster_size				(cluster_size),
+		.in_algo_threshold		(in_algo_threshold)
+		
+	);
+	
+	
+	algo_top_cl_cali_rms recon(
+	
+		.clk		(clk_clk),
+		.rst		(int_rst),
+		
+		.data_in_data		(data_out_data1),
+		.data_in_ready		(data_out_ready1),
+		.data_in_valid		(data_out_valid1),
+		.data_in_empty		(data_out_empty1),
+		.data_in_startofpacket		(data_out_startofpacket1),
+		.data_in_endofpacket			(data_out_endofpacket1),
+		
+				
+		.CL_THRESHOLD		(cluster_threshold),
+		.CL_SIZE				(cluster_size),
+		.IN_ALGO_THRESHOLD	(in_algo_threshold),
+		
+		.address		(address),
+		.clken		(clken),
+		.cali_fac	(cali_fac),
+		.waitrequest(waitrequest),
+		
+		.to_udp_data (data_out_data),           
+		.to_udp_ready(data_out_ready),          
+		.to_udp_valid (data_out_valid),          
+		.to_udp_empty (data_out_empty),          
+		.to_udp_endofpacket (data_out_endofpacket),    
+		.to_udp_startofpacket (data_out_startofpacket)		
+	);
+
+
+
+
+	
+endmodule
+	
+	
+	
+	
+	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo_inst.v b/FPGA_firmware/sensor_algo_qsys/sensor_algo_inst.v
new file mode 100644
index 0000000..1c6b22f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo_inst.v
@@ -0,0 +1,42 @@
+// Copyright (C) 2019  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+
+// Generated by Quartus Prime Version 19.1 (Build Build 670 09/22/2019)
+// Created on Tue Jun 25 14:34:30 2024
+
+sensor_algo sensor_algo_inst
+(
+	.clk_50m_clk(clk_50m_clk_sig) ,	// input  clk_50m_clk_sig
+	.reset_reset_n(reset_reset_n_sig) ,	// input  reset_reset_n_sig
+	.sensor_in_trg(sensor_in_trg_sig) ,	// input  sensor_in_trg_sig
+	.sensor_out_adc_clk(sensor_out_adc_clk_sig) ,	// output  sensor_out_adc_clk_sig
+	.sensor_out_adc_cnv(sensor_out_adc_cnv_sig) ,	// output  sensor_out_adc_cnv_sig
+	.sensor_in_adc_data(sensor_in_adc_data_sig) ,	// input [4:0] sensor_in_adc_data_sig
+	.sensor_out_sensor_rst(sensor_out_sensor_rst_sig) ,	// output  sensor_out_sensor_rst_sig
+	.sensor_out_sensor_clk(sensor_out_sensor_clk_sig) ,	// output  sensor_out_sensor_clk_sig
+	.sensor_out_sensor_gain(sensor_out_sensor_gain_sig) ,	// output  sensor_out_sensor_gain_sig
+	.sensor_csr_address(sensor_csr_address_sig) ,	// input [1:0] sensor_csr_address_sig
+	.sensor_csr_read(sensor_csr_read_sig) ,	// input  sensor_csr_read_sig
+	.sensor_csr_readdata(sensor_csr_readdata_sig) ,	// output [31:0] sensor_csr_readdata_sig
+	.sensor_csr_write(sensor_csr_write_sig) ,	// input  sensor_csr_write_sig
+	.sensor_csr_writedata(sensor_csr_writedata_sig) ,	// input [31:0] sensor_csr_writedata_sig
+	.sensor_csr_byteenable(sensor_csr_byteenable_sig) ,	// input [3:0] sensor_csr_byteenable_sig
+	.sensor_status_status_out(sensor_status_status_out_sig) ,	// output [7:0] sensor_status_status_out_sig
+	.sensor_synchro_serial_rx(sensor_synchro_serial_rx_sig) ,	// input  sensor_synchro_serial_rx_sig
+	.sensor_synchro_serial_tx(sensor_synchro_serial_tx_sig) ,	// output  sensor_synchro_serial_tx_sig
+	.sensor_synchro_ext_input(sensor_synchro_ext_input_sig) 	// input [7:0] sensor_synchro_ext_input_sig
+);
+
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qpf b/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qpf
new file mode 100644
index 0000000..df8e4b9
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 17:05:04  July 18, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "19.1"
+DATE = "17:05:04  July 18, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "sensor_algo_qsys"
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qsf b/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qsf
new file mode 100644
index 0000000..c3bf083
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_algo_qsys.qsf
@@ -0,0 +1,133 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 13:54:15  June 25, 2024
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sensor_algo_qsys_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C6GES
+set_global_assignment -name TOP_LEVEL_ENTITY algo_top_cl_cali_rms
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:54:15  JUNE 25, 2024"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH algo_top_cl_cali_rms_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME sts2stl_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sts2stl_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sts2stl_tb -section_id sts2stl_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME stl2sts_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id stl2sts_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME stl2sts_tb -section_id stl2sts_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME st2mm_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id st2mm_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME st2mm_tb -section_id st2mm_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME bkg_subtraction_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id bkg_subtraction_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME bkg_subtraction_tb -section_id bkg_subtraction_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME algo_top_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id algo_top_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME algo_top_tb -section_id algo_top_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME algo_top_cl_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id algo_top_cl_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME algo_top_cl_tb -section_id algo_top_cl_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME cluster_locate_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id cluster_locate_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME cluster_locate_tb -section_id cluster_locate_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME calibration_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id calibration_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME calibration_tb -section_id calibration_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME algo_top_cl_cali_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id algo_top_cl_cali_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME algo_top_cl_cali_tb -section_id algo_top_cl_cali_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME algo_top_cl_cali_rms_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id algo_top_cl_cali_rms_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME algo_top_cl_cali_rms_tb -section_id algo_top_cl_cali_rms_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME sensor_algo_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sensor_algo_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sensor_algo_tb -section_id sensor_algo_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME bkg_subtraction_pipe_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id bkg_subtraction_pipe_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME bkg_subtraction_pipe_tb -section_id bkg_subtraction_pipe_tb
+set_global_assignment -name QIP_FILE div.qip
+set_global_assignment -name SYSTEMVERILOG_FILE rms.sv
+set_global_assignment -name QIP_FILE sqrt.qip
+set_global_assignment -name QIP_FILE q_sys/synthesis/st_splitter16.qip
+set_global_assignment -name VERILOG_FILE stl2sts.v
+set_global_assignment -name QIP_FILE ram4bkg.qip
+set_global_assignment -name VERILOG_FILE algo_top.v
+set_global_assignment -name SYSTEMVERILOG_FILE cluster_locate.sv
+set_global_assignment -name VERILOG_FILE algo_top_cl.v
+set_global_assignment -name VERILOG_FILE calibration.v
+set_global_assignment -name QIP_FILE data_caled_ram.qip
+set_global_assignment -name VERILOG_FILE algo_top_cl_cali.v
+set_global_assignment -name VERILOG_FILE bkg_subtraction_pipe.v
+set_global_assignment -name VERILOG_FILE algo_top_cl_cali_rms.v
+set_global_assignment -name VERILOG_FILE sensor_interface.v
+set_global_assignment -name VERILOG_FILE serial_rx.v
+set_global_assignment -name VERILOG_FILE serial_tx.v
+set_global_assignment -name VERILOG_FILE sensor_algo.v
+set_global_assignment -name QIP_FILE ram_sim.qip
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/sts2stl_tb.v -section_id sts2stl_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/stl2sts_tb.v -section_id stl2sts_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/st2mm_tb.v -section_id st2mm_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/bkg_subtraction_tb.v -section_id bkg_subtraction_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/algo_top_tb.v -section_id algo_top_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/algo_top_cl_tb.v -section_id algo_top_cl_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/cluster_locate_tb.v -section_id cluster_locate_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/calibration_tb.v -section_id calibration_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ram_sim.qip -section_id calibration_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE ram_sim.v -section_id calibration_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/algo_top_cl_cali_tb.v -section_id algo_top_cl_cali_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/algo_top_cl_cali_rms_tb.v -section_id algo_top_cl_cali_rms_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/sensor_algo_tb.v -section_id sensor_algo_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE testbench/bkg_subtraction_pipe_tb.v -section_id bkg_subtraction_pipe_tb
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_interface.v b/FPGA_firmware/sensor_algo_qsys/sensor_interface.v
new file mode 100644
index 0000000..66f9722
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_interface.v
@@ -0,0 +1,784 @@
+// sensor_interface.v
+
+
+
+`timescale 1 ps / 1 ps
+module sensor_interface (
+		//Clock/reset
+        input  wire        	clk_clk,                    //                     clk.clk
+        input  wire        	rst_reset,                  //                     rst.reset
+		//Avalon MM slave
+        input  wire [1:0]  	csr_address,                //            avalon_slave.address
+        input  wire        	csr_read,                   //                        .read
+        output wire [31:0] 	csr_readdata,               //                        .readdata
+        input  wire        	csr_write,                  //                        .write
+        input  wire [31:0] 	csr_writedata,              //                        .writedata
+        input  wire [3:0]  	csr_byteenable,             //                        .byteenable
+		//Avalon ST transmitter
+        output wire [31:0] 	data_out_data,          	// avalon_streaming_source.data
+        output wire        	data_out_endofpacket,   	//                        .endofpacket
+        output wire        	data_out_startofpacket, 	//                        .startofpacket
+        input  wire        	data_out_ready,         	//                        .ready
+        output wire        	data_out_valid,         	//                        .valid
+        output wire [1:0]  	data_out_empty,         	//                        .empty
+		//Sensor interface
+        input  wire        	in_trg,                     //                  sensor.in_trg // This is the frame timer
+        output wire        	out_adc_clk,                //                        .out_dac_clk
+        output wire        	out_adc_cnv,                //                        .out_dac_cnv
+        input  wire [4:0]  	in_adc_data,                //                        .in_dac_data
+        output wire        	out_sensor_rst,             //                        .out_sensor_rst
+        output wire        	out_sensor_clk,             //                        .out_sensor_clk
+        output wire        	out_sensor_gain,            //                        .out_sensor_gain
+			//Serial synchro interface
+			input  wire	   		serial_rx,					//receive data
+			output wire	   		serial_tx,					//send data
+			input  wire [7:0]  	ext_input,					//SMA etc.
+			//Debug information
+			output wire [7:0] 	status_out,					//status bits - same as in reg0_read[15:8]
+			
+			output reg 				int_rst,						//the reset for each new run 
+			output reg	[7:0]		cluster_threshold,		//from registers[3][7:0] 
+			output reg	[7:0]		cluster_size,				//from registers[3][15:8]
+			output reg  [7:0]		in_algo_threshold			//from registers[3][23:16]
+    );
+	
+
+		//Very important globals
+	reg[31:0] 	transmit_buffer[162:0];		//Data to send: 3 words header plus sensor data
+	wire 		readout_ready;				//pulsing this signal causes copying data from frame buffer to transmit buffer and initiating transmission
+	wire		start_transmission;			//pulsing this signal causes the Avalon ST link to start transmission
+	reg[15:0]	local_sync_ctr;				//local synchronization counter, it increments by one at each frame
+	wire[8:0]	global_sync_ctr;			//global synchronization counter, it's simply the received value from serial RX.
+	wire		global_sync_error;			//RX error in the global synchronization counter
+
+		//Common generate variables
+	genvar i;	//for generate loops
+	genvar j;
+	integer xi;	//for normal loops
+	integer xj;
+
+	// *********************** CSR stuff ************************
+	/*
+		There are 4 32-bit R/W-able registers. They are used for setting up the module and checking its state
+		Reg0 is a bit different: when read, bits 15-8 (the status byte) are taken directly from device internals, not from register contents.
+		The bus can be accessed 32-, 16- or 8-bit-wise.
+
+		Register definition
+		//reg0
+		#define SENSOR_REG_COMMAND		0	//8 bits
+		#define SENSOR_REG_STATUS		1	//8 bits
+		#define SENSOR_REG_SENSORCLK	2	//8 bits, 6 used	divider for producing sensor clock ('4' MHz)
+		#define SESNOR_REG_ADCCNV		3	//8 bits, 6 used	time of conversion pulse in ADC clocks, should be > 500 ns
+		//reg1		
+		#define SENSOR_REG_DELAY		4	//16 bits, 12 used	reset signal delay in 50 MHz clocks
+		#define SENSOR_REG_SHUTTER		6	//16 bits, 12 used	sensor reset ('shutter') time in sensor clocks
+		//reg2		
+		#define SENSOR_REG_SERSPEED		8	//8 bits 		synchro baudrate, 50 for 1 Mbps
+		#define SENSOR_REG_HEADER_ANYDATA	9	//8 bits		any data transmitted with SMA state (8 bits SMA + 8 bits anydata)
+		#define SENSOR_REG_HEADER_CMD		10	//16 bits 		command field of the command header transmitted in packet
+		//reg3										//configure reg3  17.July.2024 Qin,L
+		#define SENSOR_REG_CLUSTER_THRESHOLD	12 //8 bits	 the threshold for cluster locate, range 0~255
+		#define SENSOR_REG_CLUSTER_SIZE			13 //8 bits  the size for clluster locate, range 0~255
+		#define SENSOR_REG_IN_ALGO_THRESHOLD	14 //8 bits	 the threshold inside Linear Regression, range 0~255
+		#define SENSOR_REG_RESERVED				15 //8 bits  not used 
+
+		Command bitmasks
+		#define SENSOR_CSR_EN_BITMASK		0x01	//enable operation
+		#define SENSOR_CSR_GAIN_BITMASK		0x02	//gain selection
+		#define SENSOR_CSR_ADCK_BITMASK 	0x04	//ADC clock divider on/off
+		#define SENSOR_CSR_RESET_BITMASK	0x08	//Reset all logic  //registers[0][3]
+
+		Status bitmasks
+		#define SENSOR_STATUS_SEND		0x01	//Sending over Avalon-ST
+		#define SENSOR_STATUS_TRG_WAITING	0x02	//The trigger came and is being delayed now
+		#define SENSOR_STATUS_RESET_ACTIVE	0x04	//The RESET signal for the sensor is active now
+		#define SENSOR_STATUS_ADC_ACTIVE	0x08	//The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high
+		#define SESNOR_STATUS_ADC_FINISHED	0x10	//The ADC waits for reset high
+		#define SESNOR_STATUS_TX_ACTIVE		0x20	//Sync port is sending
+		#define SESNOR_STATUS_RX_ACTIVE		0x40	//Sync port is receiving
+
+	*/
+
+	reg 	[31:0] 	registers[3:0];		//main register space
+	wire 	[31:0]	reg0_read;		//reg[0] is read indirectly to include status byt(bits 15-8)
+
+		//read logic
+	assign reg0_read[7:0] 	= registers[0][7:0];		// Readback of control bits
+	assign reg0_read[31:16] = registers[0][31:16];		// Readback of payload size
+	assign reg0_read[15] 	= 0;							// Unused bits of the status byte 
+	assign csr_readdata 	= (csr_address==0) ? reg0_read : registers[csr_address];
+
+		//write logic
+	generate
+	for (i = 0; i < 4; i = i+1)
+	begin : write_registers	//Quartus wants labels for 'for' blocks
+		for (j = 0; j < 4; j = j+1)
+		begin : write_bytes
+			always @(posedge clk_clk or posedge rst_reset)
+			begin 
+				if (rst_reset)
+					registers[i][8*j+7:8*j] <= 8'd0;
+				else
+					if (csr_byteenable[j] && (csr_address == i) && (csr_write))
+						registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
+			end
+		end
+	end	
+	endgenerate
+
+	// *********************** Internal reset logic  ************************
+	/*
+		The internal reset signal derives from the reset input and reset bit (reg0.3).
+		It drives all subcomponents but registers (which use simpy the reset input).
+		This signal is registered to be sure that no glitches from register bank pass.
+	*/
+
+	//reg int_rst;
+
+	always @(posedge clk_clk)
+	begin
+		int_rst <= rst_reset | registers[0][3];
+	end
+
+	// *********************** Avalon transmitter ************************
+	/*
+		The transmitter is used to transmit collected sensor data together with sync frame.
+		It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
+		The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
+		The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
+		The transmission starts when the 'start_transmission' signal gets pulsed
+	*/
+
+	assign data_out_empty = 2'b00;
+
+	reg	[1:0]	data_out_state;		//State of the state machine
+	localparam DATA_OUT_STATE_IDLE	= 0;	//waiting for high
+	localparam DATA_OUT_STATE_SEND	= 1;	//sending data
+	localparam DATA_OUT_STATE_LOCK	= 2;	//waiting for trigger low
+	
+	//localparam DATA_OUT_STATE_PEND 	= 3; //the pending when sending data
+
+	localparam WORDS_TO_SEND = 163;	
+	
+		//registers to drive output pins of ST interfaces
+//	reg		reg_valid;
+//	reg	[31:0]	reg_data;
+//	reg		reg_startofpacket;
+//	reg		reg_endofpacket;
+
+		//Helper stuff
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+		//The state machine
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			data_out_state <= DATA_OUT_STATE_IDLE;
+			cluster_threshold <= registers[3][7:0];
+			cluster_size <= registers[3][15:8];
+			in_algo_threshold <= registers[3][23:16];
+		end
+		else
+			case(data_out_state)
+				DATA_OUT_STATE_IDLE:
+				begin
+					if (start_transmission)
+					begin
+						data_out_state <= DATA_OUT_STATE_SEND;
+						tx_ctr <= 0;
+						cluster_threshold <= registers[3][7:0];
+						cluster_size <= registers[3][15:8];
+						in_algo_threshold <= registers[3][23:16];
+					end
+				end
+				DATA_OUT_STATE_SEND:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr + 1'b1;
+						if (tx_ctr == (WORDS_TO_SEND-1))
+							data_out_state <= DATA_OUT_STATE_LOCK;
+					end
+				end
+				DATA_OUT_STATE_LOCK:
+				begin
+					if (~start_transmission)
+						data_out_state <= DATA_OUT_STATE_IDLE;
+				end
+
+				default:
+					data_out_state <= DATA_OUT_STATE_IDLE;
+			endcase
+	end
+
+	assign data_out_valid = (data_out_state == DATA_OUT_STATE_SEND)? 1'b1: 1'b0;
+	assign data_out_data = (data_out_state == DATA_OUT_STATE_SEND)? transmit_buffer[tx_ctr]: 32'b0;
+	assign data_out_startofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == 0) ? 1'b1: 1'b0;
+	assign data_out_endofpacket = (data_out_state == DATA_OUT_STATE_SEND && tx_ctr == (WORDS_TO_SEND-1)) ? 1'b1: 1'b0;
+
+	assign reg0_read[8] = ~(data_out_state == DATA_OUT_STATE_IDLE);		//to status register
+
+	// *********************** Detector gain logic ************************
+	/*
+		The gain signal is simply derived from reg0.
+	*/
+
+	assign out_sensor_gain = registers[0][1];
+
+	// *********************** Trigger delay logic ************************
+	/*
+		Individual trigger delay settings are needed to synchronize multiple boards.
+		A 12-bit downcounter allows for delaying incoming trigger's rising edge by up to 4095 50MHz clock cycles, i.e. 81.9 us.
+		Note: A further delay of one sensor clock will be added in the sensor clock generation logic.
+	*/
+
+	reg	[11:0]	trg_delay_ctr;
+	wire		int_trg;
+	reg	[1:0]	trg_state;
+	localparam TRG_STATE_IDLE	= 0;	//waiting for external trigger
+	localparam TRG_STATE_DELAY	= 1;	//downcounting
+	localparam TRG_STATE_ACTIVE	= 2;	//internal trigger active 
+	localparam TRG_STATE_LOCK	= 3;	//waiting for external trigger inactive 
+
+	//localparam TRG_DURATION		= 4;	//duration of the trigger signal
+
+	assign int_trg = (trg_state == TRG_STATE_ACTIVE) ? 1'b1 : 1'b0;
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			trg_state <= TRG_STATE_LOCK;
+		end
+		else
+		begin
+			case(trg_state)
+				TRG_STATE_IDLE:
+				begin
+					if (in_trg && registers[0][0])	//react on trigger only if enabled
+					begin
+						trg_delay_ctr <= registers[1][11:0];
+						trg_state <= TRG_STATE_DELAY;
+					end
+				end
+				TRG_STATE_DELAY:
+				begin
+					trg_delay_ctr <= trg_delay_ctr - 1'b1;
+					if (trg_delay_ctr == 0)
+					begin
+						//trg_delay_ctr <= TRG_DURATION-1;
+						trg_state <= TRG_STATE_ACTIVE;
+					end
+				end
+				TRG_STATE_ACTIVE:
+				begin
+					//trg_delay_ctr <= trg_delay_ctr - 1;
+					//if (trg_delay_ctr == 0)
+					//begin
+						trg_state <= TRG_STATE_LOCK;	//only one cycle of active int_trg
+					//end
+				end
+				TRG_STATE_LOCK:
+				begin
+					if (~in_trg)
+						trg_state <= TRG_STATE_IDLE;
+				end
+			endcase		
+		end
+	end
+
+	assign reg0_read[9] = ~(trg_state == TRG_STATE_IDLE);	//to status register
+
+	// *********************** Sensor clock logic  ************************
+	/*
+		The sensor needs a clock of max. 4 MHz, which is generated by this module. 
+		The actual clock speed is configurable by a register with a formula: Fs = Fi/2/(div+1),
+		where Fs is the sensor clock, Fi is input clock (50 MHz nom.) and div is a divider taken from the register.
+		A 5-bit downcounter allows for frequencies from 0.39 MHz (div=63) to 12.5 MHz (div=1).
+		The nominal setting is 6, giving 3.5714285 MHz.
+		
+		Important: The sensor clock is synchronized to the rising edge of the (delayed) trigger input, 
+		so that there is a positive slope at exactly one sensor clock period after the trigger.
+		This positive slope is then used to synchronize integration start signal (sensor reset or shutter). 
+		The synchronization is done so that one of clock states (0 or 1) gets extended, but never shortened.
+
+		Note: 4 MHz is also the top speed accepted by the ADC module.
+	*/
+
+	reg [5:0]	sensor_clk_ctr;
+	reg [1:0]	sensor_clk_state;
+
+	localparam SENSOR_CLK_STATE_LOW	= 2'd0;
+	localparam SENSOR_CLK_STATE_HIGH = 2'd1;
+	localparam SENSOR_CLK_STATE_LOWAIT = 2'd2;
+	localparam SENSOR_CLK_STATE_HIWAIT = 2'd3;	
+
+	assign out_sensor_clk = sensor_clk_state[0];
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+			sensor_clk_ctr <= registers[0][21:16];
+		end
+		else
+		begin
+			case(sensor_clk_state)
+				SENSOR_CLK_STATE_LOW:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIGH;
+					end
+				end
+				SENSOR_CLK_STATE_HIGH:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (int_trg)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_HIWAIT;
+					end
+					else if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end			
+				end
+				SENSOR_CLK_STATE_LOWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+				SENSOR_CLK_STATE_HIWAIT:
+				begin
+					sensor_clk_ctr <= sensor_clk_ctr-1'b1;
+					if (sensor_clk_ctr == 0)
+					begin
+						sensor_clk_ctr <= registers[0][21:16];
+						sensor_clk_state <= SENSOR_CLK_STATE_LOW;
+					end				
+				end
+			endcase
+		end
+	end
+
+	// *********************** Sensor reset (shutter) logic ************************
+	/*
+		This block generates a 'reset' (shutter) signal for the sensor.
+		It defines the integration time and is programmable by means of a register in sensor clock units.
+		The leading (positive) slope of this signal is synchronized with the first positive slope of the sensor clock after the trigger. 
+		An internal 12-bit downcounter allows for a max. integration time of ca 1.15 ms. It can be further extended by slowing down the sensor clock.
+		It's user's responsibility to check if the integration period fits into the trigger period. If this requirement is not fulfilled, some triggers will be skipped.
+		Sorry for this ugly code, but since it works...
+
+		Important remark from sensor's specification: Rise of a RESET pulse must be set outside the video output period. 
+		This must by guaranteed by user by means of proper timing. First video comes 18 cycles after negative slope of sensor reset and is 2 cycles long.
+		Then 2 cycles pause (here we can come with the positive reset slope), then next video and so on, every 4 cycles.
+		The minimum duration of reset low is 21 clocks, and 20 clocks for reset high.
+		Our logic requires that new reset low comes only after all channels are read.
+	*/
+
+	reg [11:0]	sensor_rst_ctr;
+	reg		sensor_rst_state;
+
+	assign out_sensor_rst = sensor_rst_state;
+
+	always @(posedge int_trg or posedge out_sensor_clk or posedge int_rst)
+	begin 
+		if (int_rst)
+		begin
+			sensor_rst_state <= 0;
+			sensor_rst_ctr <= 0;
+		end
+		else if (int_trg)
+		begin
+			sensor_rst_ctr <= registers[1][27:16];
+		end	
+		else
+		begin
+			if (sensor_rst_ctr == 0)
+			begin
+				sensor_rst_state <= 0;
+			end
+			else 
+			begin
+				sensor_rst_ctr <= sensor_rst_ctr - 1'b1;
+				sensor_rst_state <= 1'b1;
+			end
+		end
+	end
+
+	assign reg0_read[10] = sensor_rst_state;	//to status register
+
+	// *********************** ADC trigger logic ************************
+	/*
+		This piece produces triggering signals for ADC framework and cares about counting ADC samples.
+		It doesn't rely on incoming Trig signals, just generates them internally by counting clocks.
+
+	*/
+
+	reg [5:0] 	adc_current_channel;
+	reg [2:0]	adc_trg_state;
+	reg [4:0]	adc_trg_downctr;
+	wire 		int_adc_trg;
+	wire 		adc_trg_frame_ready;
+
+	localparam ADC_TRG_STATE_IDLE 	= 0;	//nothing happens, RESET is high or initial state
+	localparam ADC_TRG_STATE_WAIT 	= 1;	//waiting for the first video
+	localparam ADC_TRG_STATE_VIDEO1 = 2;	//capturing video
+	localparam ADC_TRG_STATE_VIDEO2 = 3;	//second cycle
+	localparam ADC_TRG_STATE_VIDEO3 = 4;	//third cycle
+	localparam ADC_TRG_STATE_VIDEO4 = 5;	//fourth cycle
+	localparam ADC_TRG_STATE_FINISH = 6;	//finished readout, waiting for RESET high to enter idle
+	localparam ADC_TRG_STATE_INIT 	= 7;	//used only for reset procedure
+
+	localparam ADC_TRG_INITIALWAIT = 5'd17;	//initial wait for the first video
+	localparam ADC_TRG_VIDEOPERIOD = 4;	//video output period
+
+	always @(posedge out_sensor_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_current_channel <= 63;
+			adc_trg_downctr <= 0;
+			adc_trg_state <= ADC_TRG_STATE_INIT;	//will go to IDLE when adc_trg_reset is high
+		end
+		else
+			case(adc_trg_state)
+				ADC_TRG_STATE_IDLE:
+				begin
+					if (~out_sensor_rst)
+					begin
+						adc_trg_downctr <= ADC_TRG_INITIALWAIT;
+						adc_current_channel <= 63;
+						adc_trg_state <= ADC_TRG_STATE_WAIT;
+					end
+				end
+				ADC_TRG_STATE_WAIT:
+				begin
+					adc_trg_downctr <= adc_trg_downctr - 1'b1;
+					if (adc_trg_downctr == 0)
+					begin
+						adc_trg_state <= ADC_TRG_STATE_VIDEO1;
+					end
+				end
+				ADC_TRG_STATE_VIDEO1:
+				begin
+					adc_current_channel <= adc_current_channel + 1'b1;
+					adc_trg_state = ADC_TRG_STATE_VIDEO2;			
+				end
+				ADC_TRG_STATE_VIDEO2:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO3;			
+				end
+				ADC_TRG_STATE_VIDEO3:
+				begin
+					adc_trg_state = ADC_TRG_STATE_VIDEO4;			
+				end
+				ADC_TRG_STATE_VIDEO4:
+				begin
+					if (adc_current_channel == 63)
+						adc_trg_state <= ADC_TRG_STATE_FINISH;
+					else
+						adc_trg_state = ADC_TRG_STATE_VIDEO1;			
+				end	
+				ADC_TRG_STATE_FINISH, ADC_TRG_STATE_INIT:
+				begin
+					if (out_sensor_rst)
+						adc_trg_state <= ADC_TRG_STATE_IDLE;
+				end		
+			endcase
+	end
+
+	//Producing internal trigger for ADC framework (see below)
+	assign int_adc_trg = (adc_trg_state == ADC_TRG_STATE_VIDEO1)  ? 1'b1 : 1'b0;
+
+	assign adc_trg_frame_ready = (adc_trg_state == ADC_TRG_STATE_FINISH) ? 1'b1 : 1'b0;	//trigger data collection machine when the frame is ready
+
+	assign reg0_read[11] = ~(adc_trg_state == ADC_TRG_STATE_IDLE);		//to status register
+	assign reg0_read[12] = (adc_trg_state == ADC_TRG_STATE_FINISH);		//to status register
+
+	// *********************** ADC logic ************************
+	/*
+		SPI interface for ADCs. Triggers conversion and reads out the data on each incoming int_adc_trg.
+		The ADC framework and SPI runs with full clock frequency or with half of it, depending on register setting.
+		The ADC works in the 'CS Mode, 3-Wire Without Busy Indicator Serial Interface'.
+		The CNV signal length is defined by register and expressed in ADC clocks. 
+		It's user's responsibility to ensure that the CNV pulse is longer than 500 ns (required by ADC spec).
+		The ADC clock can be selected to be either full or half system clock.
+	*/
+
+		//Clock divider and selection
+	reg		adc_halfclock;
+	wire		int_adc_clk;
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+			adc_halfclock <= 0;
+		else
+			adc_halfclock <= ~adc_halfclock;
+	end
+	assign int_adc_clk = registers[0][2] ? adc_halfclock : clk_clk;
+
+		//The main state machine
+	reg [2:0]	adc_state;
+	reg [5:0]	adc_downctr;
+
+	localparam ADC_STATE_IDLE 	= 0;		//waiting for conversion
+	localparam ADC_STATE_CNV 	= 1;		//conversion on-going
+	localparam ADC_STATE_STARTREAD	= 2;	//prepare to read, conversion finished
+	localparam ADC_STATE_READ 	= 3;		//reading data
+	localparam ADC_STATE_FINISH	= 4;		//copy data to global buffer
+	localparam ADC_STATE_FINISHED	= 5;	//wait until trigger low, then go to idle
+	
+	always @(posedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			adc_downctr <= 0;
+			adc_state <= ADC_STATE_IDLE;	
+		end
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_IDLE:
+				begin
+					adc_downctr <= registers[0][29:24];
+					if (int_adc_trg)
+						adc_state <= ADC_STATE_CNV;
+				end
+				ADC_STATE_CNV:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_STARTREAD;
+				end
+				ADC_STATE_STARTREAD:
+				begin
+					adc_downctr <= 15;
+					adc_state <= ADC_STATE_READ;
+				end
+				ADC_STATE_READ:
+				begin
+					adc_downctr <= adc_downctr - 1'b1;
+					if (adc_downctr == 0)
+						adc_state <= ADC_STATE_FINISH;
+				end
+				ADC_STATE_FINISH:
+				begin
+					adc_state <= ADC_STATE_FINISHED;
+				end
+				ADC_STATE_FINISHED:
+				begin
+					if (!int_adc_trg)
+						adc_state <= ADC_STATE_IDLE;
+				end
+				default
+				begin
+					adc_state <= ADC_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Reading data - this happens on the negative slope of clock!
+	reg [15:0] adc_buffer[4:0];		//A shift register for SPI acquisition
+	reg [15:0] frame_buffer[319:0];		//The 'big buffer' for whole frame
+
+	always @(negedge int_adc_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			for (xi = 0; xi < 5; xi = xi+1)
+				adc_buffer[xi] <= 0;
+		end		
+		else
+		begin
+			case(adc_state)
+				ADC_STATE_STARTREAD:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						adc_buffer[xi] <= 0;
+				end
+				ADC_STATE_READ:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+					begin
+						adc_buffer[xi][15:1] <= adc_buffer[xi][14:0];
+						adc_buffer[xi][0] <= in_adc_data[xi];
+					end
+				end
+				ADC_STATE_FINISH:
+				begin
+					for (xi = 0; xi < 5; xi = xi+1)
+						frame_buffer[64*xi + adc_current_channel] <= adc_buffer[xi];
+				end
+			endcase
+		end
+	end
+
+
+	assign out_adc_cnv = (adc_state == ADC_STATE_CNV) ? 1'b1 : 1'b0;
+	assign out_adc_clk = (adc_state == ADC_STATE_READ) ? int_adc_clk : 1'b1;
+
+
+	// *********************** Putting data together and letting transmit it ************************
+	/*
+		The data is sent together with a 3-word header (6 16-bit numbers),
+		which is compatible with v.1 head structures:
+			typedef struct
+			{
+				unsigned short marker;	//must be 0x5555
+				unsigned short command;
+				unsigned short length;
+			} command_header;
+			typedef struct
+			{
+				//unsigned short channel_id;
+				unsigned short local_ctr;
+				unsigned short global_ctr;
+				unsigned short sma_state;
+			} sync_frame;
+
+	*/
+	
+	reg [2:0]	merger_state;
+
+	localparam MERGER_STATE_IDLE 	= 0;		//waiting for ADC
+	localparam MERGER_STATE_COLLECT	= 1;		//collect frame information
+	localparam MERGER_STATE_SEND	= 2;		//run Avalon sender
+	localparam MERGER_STATE_FINISH	= 3;		//roll to idle
+	
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			merger_state <= ADC_STATE_IDLE;	
+			for (xi= 0; xi < 163; xi = xi+1)
+				transmit_buffer[xi] <= 0;
+		end
+		else
+		begin
+			case(merger_state)
+				MERGER_STATE_IDLE:
+				begin
+					if (adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_COLLECT;
+				end
+				MERGER_STATE_COLLECT:
+				begin
+					transmit_buffer[0][31:16] 	<= 16'h5555;		//command_header.marker = 0x5555
+					transmit_buffer[0][15:0] 	<= registers[2][31:16];	//command_header.command = reg2.31-16
+					transmit_buffer[1][31:16]	<= 16'd323;	//16'd652;		//command_header.length = 320 samples + 6 sync bytes = 323 * 16bit //16'h143
+					transmit_buffer[1][15:0]	<= local_sync_ctr[15:0];	//sync_frame.local_ctr
+					transmit_buffer[2][24:16]	<= global_sync_ctr;	//sync_frame.global_ctr
+					transmit_buffer[2][25]		<= global_sync_error;	
+					transmit_buffer[2][31:26]	<= 0;
+					transmit_buffer[2][7:0]		<= ext_input;		//sync_frame.sma_state[7:0] = ext_input
+					transmit_buffer[2][15:8]	<= registers[2][15:8];	//sync_frame.sma_state[15:8] = reg2.15-8	
+					for (xi = 0; xi < 160; xi = xi+1)
+					begin
+						//transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi][15:0];	//ADC data
+						//transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi+1][15:0];
+						transmit_buffer[xi+3][31:16] <= frame_buffer[2*xi][15:0];	//ADC data	//CHANGED 26.11.2019
+						transmit_buffer[xi+3][15:0] <= frame_buffer[2*xi+1][15:0];
+					end
+					merger_state <= MERGER_STATE_SEND;
+
+				end
+				MERGER_STATE_SEND:
+				begin
+					merger_state <= MERGER_STATE_FINISH;
+				end
+				MERGER_STATE_FINISH:
+				begin
+					if (~adc_trg_frame_ready)
+						merger_state <= MERGER_STATE_IDLE;
+				end
+			endcase
+		end
+	end
+
+		//Generate Avalon trigger signal
+	assign start_transmission = (merger_state == MERGER_STATE_SEND) ? 1'b1 : 1'b0;
+
+	// *********************** Synchro counter update ************************
+	/*
+		Just increment sunchronization counter at every trigger.
+		The counter is reset by int_reset.
+	*/
+
+	always @(posedge clk_clk or posedge int_rst)
+	begin 		
+		if (int_rst)
+		begin
+			local_sync_ctr <= 0;
+		end
+		else
+		begin
+			if (int_trg)
+				local_sync_ctr <= local_sync_ctr + 1'b1;
+		end
+	end
+
+
+
+	// *********************** Synchronization serial ports ************************
+	/*
+		There is one TX and one RX module.
+		The TX is getting triggered by int_trg (same as for the main readout framework).
+		It sends 9 LSBs of the local synchro counter with programmed baudrate.
+		The default baudrate is 1 Mbps, which needs a setting of 50 for fclk=50MHz.
+		The RX puts freshly received data into global_sync_ctr. It does not need any triggering.
+	*/
+
+	wire tx_idle;
+	wire rx_idle;
+	assign reg0_read[13] = ~tx_idle;
+	assign reg0_read[14] = ~rx_idle;
+	
+	serial_tx synchro_tx (
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.data		(local_sync_ctr[8:0]),  	//  data to send
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.trigger	(start_transmission),       //  pulse to start transmission - just AFTER collecting data from sensors
+		.tx			(serial_tx),         		//  tx serial connection
+		.idle		(tx_idle)					//	1 if sender in idle state
+	);	
+
+	serial_rx synchro_rx(
+		.clk		(clk_clk),                	//  full-speed clock
+		.rst		(int_rst),              	//  reset
+		.clk_divisor	(registers[2][7:0]),    //  defines baudrate
+		.rx			(serial_rx),         		//  rx serial connection
+		.newdata	(),							//	pulses for new data received
+		.data		(global_sync_ctr),      	//  data received
+		.error		(global_sync_error),		//	bad start or stop bit
+		.idle		(rx_idle)					//	1 if receiver in idle state
+	);
+
+	// *********************** Status output ************************
+	/*
+		The status of the module (== reg0_read[15:8]) is available at the output status bus.
+		It can be then routed to a scope or whatever for debugging
+	*/	
+	
+	assign status_out[7:0] = reg0_read[15:8];	
+	
+	
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/sensor_recon.sopcinfo b/FPGA_firmware/sensor_algo_qsys/sensor_recon.sopcinfo
new file mode 100644
index 0000000..62f4229
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sensor_recon.sopcinfo
@@ -0,0 +1,1286 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="sensor_recon" kind="sensor_recon" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.18.17:04:57 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1721315097</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP">
+  <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_calibration_ram_interface</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH">
+  <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+  <value>AddressWidth = -1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_calibration_ram_interface</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_recon_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/serial_rx.v b/FPGA_firmware/sensor_algo_qsys/serial_rx.v
new file mode 100644
index 0000000..cc1f14d
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/serial_rx.v
@@ -0,0 +1,84 @@
+// 9-bit Serial port receiver
+// It's very simple, just single sample halfway of each bit.
+// If start bit is not zero or stop bit is not one, an error will be signaled.
+// In general, this module is prone to glitches in signal. First of all, any glitch > Tclk will trigger the reception process.
+// RX is high on idle.
+// Baud rate is programmable via clk_divisor
+// clk_divisor ids internally divided by 2 to get in the middle of bit, so need to be at least 2.
+
+`timescale 100 ps / 100 ps
+module serial_rx (
+		input  wire        	clk,                	//      full-speed clock
+		input  wire        	rst,              	//      reset
+		input  wire [7:0]  	clk_divisor,         //      defines baudrate
+		input  wire 	   	rx,         		//      rx serial connection
+		output wire	   		newdata,		//	pulses for new data received
+		output wire [8:0]  	data,            	//      data to send
+		output wire	   		error,		//	bad start or stop bit
+		output wire	   		idle			//	1 if receiver in idle state
+	);
+
+	reg	[1:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_DATA		= 1;	//sending data
+	localparam STATE_FINISH		= 2;	//finished
+
+	reg	[4:0]	rx_ctr;			//counter of received data words
+	reg [7:0]	downctr;		//counter to generate baudrate
+	reg	[10:0]	buffer;			//internal latch/shift register with start and stop bit
+	reg	[8:0]	reg_data;		//latched received data
+	reg			reg_error;		//latched error
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			reg_data <= 0;
+			reg_error <= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (~rx)
+					begin
+						state 		<= STATE_DATA;
+						rx_ctr 		<= 10;
+						downctr[6:0]<= clk_divisor[7:1];	//wait half a bit
+						downctr[7]	<= 0;
+						buffer		<= 0;
+					end
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr 	<= clk_divisor;
+						rx_ctr 		<= rx_ctr - 1;
+						buffer[9:0] <= buffer[10:1];
+						buffer[10] 	<= rx;
+						if (rx_ctr == 0)
+							state 	<= STATE_FINISH;
+					end
+				end
+				STATE_FINISH:
+				begin
+					reg_data[8:0] 	<= buffer[9:1];
+					reg_error		<= buffer[0] | ~buffer[10];	//high start or low stop bit
+					state 			<= STATE_IDLE;
+				end
+				default:
+					state 			<= STATE_IDLE;
+			endcase
+	end
+	
+		//assignments
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+	assign data = reg_data;
+	assign error =  reg_error;
+
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/serial_tx.v b/FPGA_firmware/sensor_algo_qsys/serial_tx.v
new file mode 100644
index 0000000..ab1b607
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/serial_tx.v
@@ -0,0 +1,115 @@
+// 9-bit Serial port transmitter
+// TX is high on idle.
+// Baud rate is programmable via clk_divisor
+
+`timescale 100 ps / 100 ps
+module serial_tx (
+		input  wire        clk,                	//      full-speed clock
+		input  wire        rst,              	//      reset
+		input  wire [8:0]  data,            	//      data to send
+		input  wire [7:0]  clk_divisor,         //      defines baudrate
+		input  wire 	   trigger,          	//      pulse to start transmission
+		output wire 	   tx,         		//      tx serial connection
+		output wire	   idle			//	1 if sender in idle state
+
+	);
+
+	reg	[2:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_STARTBIT	= 1;	//sending start bit
+	localparam STATE_DATA		= 2;	//sending data
+	localparam STATE_STOPBIT	= 3;	//sending stop bit
+	localparam STATE_FINISH		= 4;	//finished
+
+	reg	[4:0]	tx_ctr;			//counter of sent data words
+	reg 	[7:0]	downctr;		//counter to generate baudrate
+	reg	[8:0]	buffer;			//internal latch/shift register
+	reg		reg_tx;
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+			state <= STATE_FINISH;
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (trigger)
+					begin
+						state <= STATE_STARTBIT;
+						tx_ctr <= 8;
+						buffer <= data;
+						downctr <= clk_divisor;
+					end
+				end
+				STATE_STARTBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_DATA;
+					end
+
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						tx_ctr <= tx_ctr - 1;
+						buffer[7:0] <= buffer[8:1];
+						buffer[8] <= 0;
+						if (tx_ctr == 0)
+							state <= STATE_STOPBIT;
+					end
+				end
+				STATE_STOPBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_FINISH;
+					end
+
+				end
+				STATE_FINISH:
+				begin
+					if (~trigger)
+						state <= STATE_IDLE;
+				end
+				default:
+					state <= STATE_FINISH;
+			endcase
+	end
+	
+		//tx assignment
+	always @( * )
+	begin
+		if (rst)
+			reg_tx = 1;
+		else
+			case(state)
+				STATE_IDLE:
+					reg_tx = 1;
+				STATE_STARTBIT:
+					reg_tx = 0;
+				STATE_DATA:
+					reg_tx = buffer[0];
+				STATE_STOPBIT:
+					reg_tx = 1;
+				STATE_FINISH:
+					reg_tx = 1;
+				default:
+					reg_tx = 1;
+			endcase
+	end
+	assign tx = reg_tx;
+
+		//idle assignment
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt.qip b/FPGA_firmware/sensor_algo_qsys/sqrt.qip
new file mode 100644
index 0000000..01e42de
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sqrt.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTSQRT"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sqrt.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sqrt_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sqrt_bb.v"]
diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt.v b/FPGA_firmware/sensor_algo_qsys/sqrt.v
new file mode 100644
index 0000000..a3a89bc
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sqrt.v
@@ -0,0 +1,104 @@
+// megafunction wizard: %ALTSQRT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTSQRT 
+
+// ============================================================
+// File Name: sqrt.v
+// Megafunction Name(s):
+// 			ALTSQRT
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sqrt (
+	clk,
+	ena,
+	radical,
+	q,
+	remainder);
+
+	input	  clk;
+	input	  ena;
+	input	[25:0]  radical;
+	output	[12:0]  q;
+	output	[13:0]  remainder;
+
+	wire [12:0] sub_wire0;
+	wire [13:0] sub_wire1;
+	wire [12:0] q = sub_wire0[12:0];
+	wire [13:0] remainder = sub_wire1[13:0];
+
+	altsqrt	ALTSQRT_component (
+				.clk (clk),
+				.ena (ena),
+				.radical (radical),
+				.q (sub_wire0),
+				.remainder (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr ()
+				// synopsys translate_on
+				);
+	defparam
+		ALTSQRT_component.pipeline = 13,
+		ALTSQRT_component.q_port_width = 13,
+		ALTSQRT_component.r_port_width = 14,
+		ALTSQRT_component.width = 26;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: PIPELINE NUMERIC "13"
+// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13"
+// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "26"
+// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
+// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]"
+// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]"
+// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
+// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
+// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v b/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v
new file mode 100644
index 0000000..8ef6720
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sqrt_bb.v
@@ -0,0 +1,76 @@
+// megafunction wizard: %ALTSQRT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTSQRT 
+
+// ============================================================
+// File Name: sqrt.v
+// Megafunction Name(s):
+// 			ALTSQRT
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module sqrt (
+	clk,
+	ena,
+	radical,
+	q,
+	remainder);
+
+	input	  clk;
+	input	  ena;
+	input	[25:0]  radical;
+	output	[12:0]  q;
+	output	[13:0]  remainder;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: PIPELINE NUMERIC "13"
+// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "13"
+// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "26"
+// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
+// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: USED_PORT: radical 0 0 26 0 INPUT NODEFVAL "radical[25..0]"
+// Retrieval info: USED_PORT: remainder 0 0 14 0 OUTPUT NODEFVAL "remainder[13..0]"
+// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
+// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
+// Retrieval info: CONNECT: @radical 0 0 26 0 radical 0 0 26 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: CONNECT: remainder 0 0 14 0 @remainder 0 0 14 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v b/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v
new file mode 100644
index 0000000..f88c492
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sqrt_inst.v
@@ -0,0 +1,7 @@
+sqrt	sqrt_inst (
+	.clk ( clk_sig ),
+	.ena ( ena_sig ),
+	.radical ( radical_sig ),
+	.q ( q_sig ),
+	.remainder ( remainder_sig )
+	);
diff --git a/FPGA_firmware/sensor_algo_qsys/st2mm.v b/FPGA_firmware/sensor_algo_qsys/st2mm.v
new file mode 100644
index 0000000..ff5ff6f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/st2mm.v
@@ -0,0 +1,86 @@
+//a module bridge the avalon streaming interface and avalon memory map interface
+//collect data from interface and write to RAM
+
+//32 2; OR 16 1
+
+//tested by st2mm_tb.v
+module st2mm #(parameter BITSIZE = 32, EMPTY_SIZE = 2)(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [BITSIZE-1:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [EMPTY_SIZE-1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon MM(Memory Mapped) source  writelatency 0; readlatency 1 but no read logic here
+	output wire [8:0] mm_address,
+	output wire       mm_chipselect, // only for write
+	output wire 		mm_write,
+	output wire [BITSIZE-1:0] mm_writedata,
+	input wire mm_waitrequest_n //it equals to mm_ready..
+	
+	//output wire			mm_clken, //only for write write enable
+	input wire	[BITSIZE-1:0]mm_readdate, //do not read
+	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE_WRITE = 2'd1; //write to mm
+	localparam STATE_LOCK = 2'd3; //Finish writing
+	
+	reg[8:0] ctr; // count data and the address for MM
+	localparam CTR_ZERO = 9'd0;
+	assign mm_address = ctr;
+	assign mm_writedata = data_in_data;
+	assign mm_write = (state == STATE_WRITE)? 1'b1: 1'b0;
+	
+	assign mm_chipselect = (state == STATE_WRITE && data_in_valid)? 1'b1: 1'b0;
+	//assign mm_clken = (state == STATE_WRITE && data_in_valid)? 1'b1: 1'b0;
+	assign data_in_ready = (state == STATE_WRITE)? mm_waitrequest_n: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			ctr <= CTR_ZERO;
+		end
+		else case(state)
+				STATE_IDLE:
+				begin
+					ctr <= CTR_ZERO;
+					if (data_in_startofpacket)
+						state <= STATE_WRITE;
+				end
+				STATE_WRITE:
+				begin
+					if (data_in_valid && mm_waitrequest_n)
+					begin
+						ctr <= ctr + 1'b1;
+						if (data_in_endofpacket)
+							state <= STATE_LOCK;
+							ctr <= CTR_ZERO;
+					end
+				end
+				STATE_LOCK:
+				begin
+					state <= STATE_IDLE;
+					ctr <= CTR_ZERO;
+				end
+				default:
+					state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v b/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v
new file mode 100644
index 0000000..0e2264b
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/st2mm_l2s.v
@@ -0,0 +1,80 @@
+//a module bridge the avalon streaming interface and avalon memory map interface
+//collect data from interface and write to RAM
+//long to short
+//32 bits to 16 bits
+
+
+module st2mm_l2s(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [31:0] st_data,           //  st.data
+	output wire        st_ready,          //         .ready
+	input  wire        st_valid,          //         .valid
+	input  wire [1:0]  st_empty,          //         .empty
+	input  wire        st_endofpacket,    //         .endofpacket
+	input  wire        st_startofpacket,  //         .startofpacket
+	
+	//avalon MM(Memory Mapped) source
+	output wire [8:0] mm_address,
+	output wire       mm_chipselect, // only for write
+	output wire			mm_clken, //only for write; write enable
+	input wire	[31:0]mm_readdate, //do not read
+	output wire 		mm_write,
+	output wire [8:0] mm_writedata
+	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE_WRITE = 2'd1; //write to mm
+	localparam STATE_LOCK = 2'd3; //Finish writing
+	
+	reg[8:0] ctr; // count data and the address for MM
+	localparam CTR_ZERO = 9'd0;
+	assign mm_address = ctr;
+	assign mm_writedata = st_data;
+	
+	assign mm_chipselect = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	assign mm_clken = (state == STATE_WRITE && st_valid)? 1'b1: 1'b0;
+	assign st_ready = (state == STATE_WRITE)? 1'b1: 1'b0;
+	
+	
+	always @ (posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			ctr <= CTR_ZERO;
+		end
+		else case(state)
+				STATE_IDLE:
+				begin
+					ctr <= CTR_ZERO;
+					if (st_startofpacket)
+						state <= STATE_WRITE;
+				end
+				STATE_WRITE:
+				begin
+					if (st_valid)
+						ctr <= ctr + 1'b1;
+					if (st_endofpacket)
+						state <= STATE_LOCK;
+				end
+				STATE_LOCK:
+				begin
+					state <= STATE_IDLE;
+					ctr <= CTR_ZERO;
+				end
+				default:
+					state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/st_splitter16.qsys b/FPGA_firmware/sensor_algo_qsys/st_splitter16.qsys
new file mode 100644
index 0000000..1394a71
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/st_splitter16.qsys
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element st_splitter16
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="st_splitter16_clk"
+   internal="st_splitter16.clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="st_splitter16_in"
+   internal="st_splitter16.in"
+   type="avalon_streaming"
+   dir="end" />
+ <interface
+   name="st_splitter16_out0"
+   internal="st_splitter16.out0"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="st_splitter16_out1"
+   internal="st_splitter16.out1"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="st_splitter16_reset"
+   internal="st_splitter16.reset"
+   type="reset"
+   dir="end" />
+ <module
+   name="st_splitter16"
+   kind="altera_avalon_st_splitter"
+   version="19.1"
+   enabled="1">
+  <parameter name="BITS_PER_SYMBOL" value="8" />
+  <parameter name="CHANNEL_WIDTH" value="1" />
+  <parameter name="DATA_WIDTH" value="16" />
+  <parameter name="ERROR_DESCRIPTOR" value="" />
+  <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="MAX_CHANNELS" value="1" />
+  <parameter name="NUMBER_OF_OUTPUTS" value="2" />
+  <parameter name="QUALIFY_VALID_OUT" value="1" />
+  <parameter name="READY_LATENCY" value="0" />
+  <parameter name="USE_CHANNEL" value="0" />
+  <parameter name="USE_DATA" value="1" />
+  <parameter name="USE_ERROR" value="0" />
+  <parameter name="USE_PACKETS" value="1" />
+  <parameter name="USE_READY" value="1" />
+  <parameter name="USE_VALID" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/FPGA_firmware/sensor_algo_qsys/st_splitter16.sopcinfo b/FPGA_firmware/sensor_algo_qsys/st_splitter16.sopcinfo
new file mode 100644
index 0000000..0fe7f4e
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/st_splitter16.sopcinfo
@@ -0,0 +1,847 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="st_splitter16" kind="st_splitter16" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.02.15:16:05 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1719926165</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>st_splitter16_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>st_splitter16_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>st_splitter16_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="st_splitter16"
+   kind="altera_avalon_st_splitter"
+   version="19.1"
+   path="st_splitter16">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="NUMBER_OF_OUTPUTS">
+   <type>int</type>
+   <value>2</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="QUALIFY_VALID_OUT">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_READY">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_VALID">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_PACKETS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_CHANNEL">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_ERROR">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_DATA">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DATA_WIDTH">
+   <type>int</type>
+   <value>16</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CHANNEL_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="BITS_PER_SYMBOL">
+   <type>int</type>
+   <value>8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="MAX_CHANNELS">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="READY_LATENCY">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ERROR_DESCRIPTOR">
+   <type>[Ljava.lang.String;</type>
+   <value></value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="EMPTY_WIDTH">
+   <type>int</type>
+   <value>1</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="reset" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="in" kind="avalon_streaming_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in0_ready</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>in0_valid</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>in0_startofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>in0_endofpacket</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>in0_empty</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>in0_data</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+  <interface name="out0" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out0_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out0_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out0_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out0_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out0_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out0_data</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+  <interface name="out1" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>reset</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>2</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>out1_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>out1_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+   <port>
+    <name>out1_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>out1_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>out1_empty</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>out1_data</name>
+    <direction>Output</direction>
+    <width>16</width>
+    <role>data</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_avalon_st_splitter</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Avalon-ST Splitter</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Sink</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_algo_qsys/stl2sts.v b/FPGA_firmware/sensor_algo_qsys/stl2sts.v
new file mode 100644
index 0000000..a846124
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/stl2sts.v
@@ -0,0 +1,84 @@
+//a module bridge the avalon streaming interfaces with data length from 32 bit to 16 bit
+//long to short
+//32 bits to 16 bits [31:16] streaming out first and then [15:0]
+//ST long to ST short
+
+
+
+//tested by stl2sts_tb.v
+module stl2sts(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [31:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire [1:0]  data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	output  wire [15:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire        data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+);
+
+	reg[1:0] state;
+	localparam STATE_IDLE = 2'd0; //waiting for startofpacket
+	localparam STATE1 = 2'd1; //streaming [31:16]
+	localparam STATE2 = 2'd3; //streaming [15:0]
+	localparam STATE_LOCK = 2'd2; //Finishing streaming
+	
+	assign data_in_ready = (state == STATE2 && data_out_ready)? 1'b1:1'b0;
+	
+	assign data_out_data = (state == STATE1)? data_in_data[31:16]:(state== STATE2)? data_in_data[15:0]: 16'b0;
+	assign data_out_valid = (state == STATE1 || state == STATE2)?data_in_valid:1'b0;
+	assign data_out_empty = 1'b0;
+	assign data_out_startofpacket = (state == STATE1)? data_in_startofpacket: 1'b0;
+	assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			state <= STATE_IDLE;
+		else case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket)
+				state <= STATE1;
+		end
+		STATE1:
+		begin
+			if (data_in_valid && data_out_ready)
+				state <= STATE2;
+		end
+		STATE2:
+		begin
+			if (data_in_valid && data_out_ready)
+			begin
+				if (data_in_endofpacket)
+					state <= STATE_LOCK;
+				else
+					state <= STATE1;
+			end
+		end
+		STATE_LOCK:
+			state <= STATE_IDLE;
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+	
+
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/sts2stl.v b/FPGA_firmware/sensor_algo_qsys/sts2stl.v
new file mode 100644
index 0000000..f0f9739
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/sts2stl.v
@@ -0,0 +1,108 @@
+//a module bridge the avalon streaming interfaces with data length from 16 bit to 32bit
+//short to long
+//First fill [31:16] and then fill [15:0]
+//ST short to ST long
+
+//the number of ST short data_in_data has to be even 
+//tested by sts2stl_tb.v
+module sts2stl(
+
+	//clock and reset
+	input wire clk,
+	input wire rst,
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	input  wire [15:0] data_in_data,           //  st.data
+	output wire        data_in_ready,          //         .ready
+	input  wire        data_in_valid,          //         .valid
+	input  wire 		 data_in_empty,          //         .empty
+	input  wire        data_in_endofpacket,    //         .endofpacket
+	input  wire        data_in_startofpacket,  //         .startofpacket
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	output  wire [31:0] data_out_data,           //  st.data
+	input   wire        data_out_ready,          //         .ready
+	output  wire        data_out_valid,          //         .valid
+	output  wire [1:0]  data_out_empty,          //         .empty
+	output  wire        data_out_endofpacket,    //         .endofpacket
+	output  wire        data_out_startofpacket  //         .startofpacket	
+);
+
+	reg[2:0] state;
+	localparam STATE_IDLE = 3'd0; //waiting for startofpacket
+	localparam STATE10 = 3'd1; // collecting [31:16]
+	localparam STATE20 = 3'd3; // collecting [15:0]
+	localparam STATE1 = 3'd7; 
+	localparam STATE2 = 3'd6;
+	localparam STATE_LOCK = 3'd5; //Finishing streaming
+	
+	reg[15:0] data_buffer; //buffer for the first and then fill [31:16]
+	
+	assign data_in_ready = ((state == STATE20 || state == STATE2) && data_out_ready)? 1'b1:(state == STATE1 || state == STATE10)? 1'b1: 1'b0;
+	
+	assign data_out_data = (state == STATE2 || state == STATE20)? {data_buffer, data_in_data}: 32'b0;
+	assign data_out_valid = (state == STATE2 || state == STATE20)? data_in_valid: 1'b0;
+	assign data_out_empty = 2'b0;
+	assign data_out_startofpacket = (state == STATE20)? 1'b1: 1'b0;
+	assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
+	
+	always @ (posedge clk or posedge rst)
+	begin
+		if (rst)
+			state <= STATE_IDLE;
+		else case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket)
+				state <= STATE10;
+		end
+		STATE10:
+		begin
+			if (data_in_valid)
+			begin
+				state <= STATE20;
+				data_buffer <= data_in_data; 
+			end
+		end
+		STATE20:
+		begin
+			if (data_in_valid && data_out_ready)
+			begin
+				if (data_in_endofpacket)
+					state <= STATE_LOCK;
+				else
+					state <= STATE1;
+			end
+		end
+		STATE1:
+		begin
+			if (data_in_valid)
+			begin
+				state <= STATE2;
+				data_buffer <= data_in_data; 
+			end
+		end
+		STATE2:
+		begin
+			if (data_in_valid && data_out_ready)
+			begin
+				if (data_in_endofpacket)
+					state <= STATE_LOCK;
+				else
+					state <= STATE1;
+			end
+		end
+		STATE_LOCK:
+			state <= STATE_IDLE;
+		default:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+	
+
+	
+
+
+endmodule
+	
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v
new file mode 100644
index 0000000..d6a7923
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_rms_tb.v
@@ -0,0 +1,177 @@
+//module algo_top_cl_cali_tb
+
+
+`timescale 1 ns / 1 ns
+
+module algo_top_cl_cali_rms_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire[31:0] data_in_data_n;
+	assign data_in_data_n = ~data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	
+	//for cluster
+	reg[15:0] CL_THRESHOLD;
+	reg[15:0] CL_SIZE;
+	
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	wire [8:0] 		address;
+	reg [15:0] 	cali_fac;
+	wire 				clken;
+	
+		// 
+	reg waitrequest;
+	always @(posedge clk) begin
+	if (clken)
+		waitrequest<=1'b0;
+	else 
+		waitrequest <= 1'b1;
+	end
+	
+	
+	algo_top_cl_cali_rms algo_top_cl_cali_rms_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data_n),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+				
+		.CL_THRESHOLD		(CL_THRESHOLD),
+		.CL_SIZE				(CL_SIZE),
+		.address		(address),
+		.clken		(clken),
+		.cali_fac	(cali_fac),
+		.waitrequest (waitrequest),
+		
+		.to_udp_data (to_udp_data),           
+		.to_udp_ready(1'b1),          
+		.to_udp_valid (to_udp_valid),          
+		.to_udp_empty (to_udp_empty),          
+		.to_udp_endofpacket (to_udp_endofpacket),    
+		.to_udp_startofpacket (to_udp_startofpacket)		
+	);
+	
+	initial begin
+	
+	CL_SIZE = 5;
+	CL_THRESHOLD = 2; 
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	cali_fac = 16'd10003;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 'hF0;
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+		
+	end
+	
+		repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 'h600F7; //output data should be 9,9,9,9,9, SumY=2880; SumXY=1843200; MeanXleftshift=2560
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					//data_in_data <= 600000;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v
new file mode 100644
index 0000000..52ed3bb
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_cali_tb.v
@@ -0,0 +1,158 @@
+//module algo_top_cl_cali_tb
+
+
+`timescale 1 ns / 1 ns
+
+module algo_top_cl_cali_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	
+	//for cluster
+	reg[15:0] CL_THRESHOLD;
+	reg[15:0] CL_SIZE;
+	
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	wire [8:0] 		address;
+	reg [15:0] 	cali_fac;
+	wire 				clken;
+	
+	algo_top_cl_cali algo_top_cl_cali_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+				
+		.CL_THRESHOLD		(CL_THRESHOLD),
+		.CL_SIZE				(CL_SIZE),
+		.address		(address),
+		.clken		(clken),
+		.cali_fac	(cali_fac)
+		
+	);
+	
+	initial begin
+	
+	CL_SIZE = 5;
+	CL_THRESHOLD = 2; 
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	cali_fac = 'h3;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 'hF0;
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+		
+	end
+	
+		repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 'hF3; //output data should be 0,3,0,3...
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					//data_in_data <= 600000;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v
new file mode 100644
index 0000000..92f8ffd
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_cl_tb.v
@@ -0,0 +1,160 @@
+//algo_top_cl testbench
+
+//testbench for algo_top
+
+`timescale 1 ns / 1 ns
+module algo_top_cl_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [15:0] data_out_data;          // data_out.data
+	wire        data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	//for cluster
+	reg[15:0] CL_THRESHOLD;
+	reg[15:0] CL_SIZE;
+	
+	algo_top_cl algo_top_cl_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		//.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid),
+		
+		.CL_THRESHOLD		(CL_THRESHOLD),
+		.CL_SIZE				(CL_SIZE)
+		
+	);
+	
+	initial begin
+	
+	CL_SIZE = 5;
+	CL_THRESHOLD = 2; 
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 600000;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 600000;
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+		
+	end
+	
+		repeat(8) begin
+		/******one packet*******/
+		//start packet
+		data_in_data = 7000000;
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					//data_in_data <= 600000;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v
new file mode 100644
index 0000000..b919314
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/algo_top_tb.v
@@ -0,0 +1,136 @@
+//testbench for algo_top
+
+`timescale 1 ns / 1 ns
+module algo_top_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [15:0] data_out_data;          // data_out.data
+	wire        data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	algo_top algo_top_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 600000;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*5000);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					data_in_data <= 600000;
+					//data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v
new file mode 100644
index 0000000..5fbb7c2
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_pipe_tb.v
@@ -0,0 +1,143 @@
+//bkg_subtraction_pipe_tb.v
+
+//testbench for bkg_subtraction_pipe
+
+`timescale 1 ns / 1 ns
+module bkg_subtraction_pipe_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [31:0] data_out_data;          // data_out.data
+	wire        data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	bkg_subtraction_pipe #(.BKG_FRAME(4)) bkg_subtraction_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid),
+		
+		.to_udp_ready(1'b1)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	//data_in_data = 32'hFFFFFFFF;
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*500);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data +1'b1;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					data_in_data = 0;
+
+					//data_in_data <= 32'hFFFFFFFF;
+					//data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data +1'b1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v
new file mode 100644
index 0000000..45db278
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/bkg_subtraction_tb.v
@@ -0,0 +1,136 @@
+//testbench for bkg_subtraction
+
+`timescale 1 ns / 1 ns
+module bkg_subtraction_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [31:0] data_out_data;          // data_out.data
+	wire        data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [7:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 163;
+	
+	bkg_subtraction #(.BKG_FRAME(4)) bkg_subtraction_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(8) begin
+		/******one packet*******/
+		//start packet
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+		//end packet
+//		#(CLK_PERIOD*163*4);
+//		data_in_endofpacket = 1'b1;
+		#(CLK_PERIOD*500);
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+					data_in_data <= 0;
+					//data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v
new file mode 100644
index 0000000..609cdde
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/calibration_tb.v
@@ -0,0 +1,217 @@
+//module calibration testbench
+//data_caled calculate: address's square 
+`timescale 1 ns / 1 ns
+module calibration_tb();
+	
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [15:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg 		  data_in_empty;
+	reg		  data_in_startofpacket;
+	reg		  data_in_endofpacket;
+	
+	reg 	to_udp_ready;
+	
+	//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram
+	wire [8:0] 		address;
+	wire [15:0] 	cali_fac;
+	wire 				clken;	
+	
+	reg [8:0]		data_caled_address;
+	wire [15:0]		data_caled;
+	wire 				data_caled_rd_enable;
+
+	reg [15:0]		data_a;
+	wire 				wren_a;
+	reg [8:0]		wr_address;
+	reg 				start_wr;
+	
+	
+	
+	reg [2:0] state;
+	localparam STATE_IDLE = 3'd0;
+	localparam STATE_WR = 3'd1;
+	localparam STATE_LOC0 = 3'd2;
+	localparam STATE_SEND = 3'd3;
+	localparam STATE_LOC1 = 3'd4;
+	localparam STATE_RD = 3'd5;
+	localparam STATE_LOC2 = 3'd6;
+	
+	assign data_caled_rd_enable = (state == STATE_RD)? 1'b1: 1'b0;
+	
+	
+	// 
+	reg waitrequest;
+	always @(posedge clk) begin
+	if (clken)
+		waitrequest<=1'b0;
+	else 
+		waitrequest <= 1'b1;
+	end
+	
+
+
+	//the ram for store the cali_fac in testbench
+	ram_sim cal_fac_simulation_ram (
+	.clock ( clk ),
+	.address_a (wr_address),
+	.data_a (data_a),
+	.wren_a (wren_a),
+	.rden_a (1'b0),
+	.q_a (),
+	
+	.address_b ( address ),
+	.data_b ( ),
+	.rden_b (clken),
+	.wren_b (1'b0),
+	.q_b ( cali_fac)
+	);
+	
+	calibration calibration_dut(
+	
+	.clk(clk),
+	.rst(rst),
+		
+	.data_in_data		(data_in_data),
+	.data_in_ready		(data_in_ready),
+	.data_in_valid		(data_in_valid),
+	.data_in_empty		(data_in_empty),
+	.data_in_startofpacket		(data_in_startofpacket),
+	.data_in_endofpacket			(data_in_endofpacket),
+	
+	.address		(address),
+	.clken		(clken),
+	.cali_fac	(cali_fac),
+	.waitrequest(waitrequest),
+	
+	.data_caled_address(data_caled_address),
+	.data_caled(data_caled),
+	.data_caled_rd_enable(data_caled_rd_enable),
+	
+	.to_udp_ready(to_udp_ready)
+
+	);
+	
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	data_in_endofpacket = 1'b0;
+	start_wr = 1'b0;
+	to_udp_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2 + 1);
+	rst = 1'b0;
+	start_wr = 1'b1;
+	
+	#(CLK_PERIOD*2);
+	start_wr = 1'b0;
+	
+	#(CLK_PERIOD*400);
+	
+	
+	//start packet
+	#(CLK_PERIOD*2+1);
+	data_in_startofpacket = 1'b1;
+	#(CLK_PERIOD*2);
+	to_udp_ready = 1'b1;
+	
+	#(CLK_PERIOD*10);
+	to_udp_ready = 1'b0;
+	#(CLK_PERIOD*10);
+	to_udp_ready = 1'b1;
+	#(CLK_PERIOD*309);
+	//end packet
+	data_in_endofpacket = 1'b1;
+	
+	
+	#(CLK_PERIOD*500); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign wren_a = (state == STATE_WR)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			wr_address <= 0;
+			data_a <= 0;
+			data_caled_address <= 0;
+			if (start_wr)
+			begin
+				state <= STATE_WR;
+			end
+		end
+		STATE_WR:
+		begin
+			wr_address <= wr_address + 1;
+			data_a <= data_a + 1; 
+			if (wr_address == 319)
+			begin
+				state <= STATE_LOC0;
+			end
+		end
+		STATE_LOC0:
+		begin
+			if (data_in_startofpacket && data_in_ready)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+				data_in_startofpacket <= 1'b0;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				if (data_in_endofpacket) begin
+					state <= STATE_LOC1;
+					data_in_data <= 0;
+					data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC1:
+		begin
+			state <= STATE_RD;
+		end
+		STATE_RD:
+		begin
+			data_caled_address <= data_caled_address + 1;
+			if (data_caled_address == 319)
+				state <= STATE_LOC2;
+		end
+		STATE_LOC2:
+			state <= STATE_IDLE;
+		endcase
+	end
+	
+
+
+
+	
+	
+	
+	
+endmodule
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v
new file mode 100644
index 0000000..1d92e5f
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/cluster_locate_tb.v
@@ -0,0 +1,172 @@
+//module cluster_locate testbench
+
+//algo_top_cl testbench
+
+//testbench for algo_top
+
+`timescale 1 ns / 1 ns
+module cluster_locate_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [15:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg        data_in_empty;
+	reg		  data_in_startofpacket;
+	wire		  data_in_endofpacket;
+	
+	//for cluster
+	reg[15:0] CL_THRESHOLD;
+	reg[15:0] CL_SIZE;
+	
+	wire[8:0] sig_ch_left;
+	wire[8:0] sig_ch_right;
+	wire 		 has_cluster;
+	wire		 no_cluster;
+	
+	
+	
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	reg [8:0]	tx_ctr; //counter for how many data has been sent
+	localparam WORDS_TO_SEND = 320;
+	
+
+	
+	cluster_locate cluster_locate_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.THRESHOLD			(CL_THRESHOLD),
+		.SIZE					(CL_SIZE),
+		
+		.sig_ch_left		(sig_ch_left),
+		.sig_ch_right		(sig_ch_right),
+		.has_cluster		(has_cluster),
+		.no_cluster			(no_cluster)
+		
+	);
+	
+	localparam HEIGHT = 2000;
+	reg[31:0] WIDTH;
+	localparam POS = 100;
+	
+
+	initial begin
+	
+	CL_SIZE = 5;
+	CL_THRESHOLD = 200; 
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	//data_in_endofpacket = 1'b0;
+
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+
+	
+	#1; //make sure startofpacket and endofpacket start after clk rising edge
+	
+	repeat(4) begin
+		WIDTH = 20;
+		/******one packet*******/
+		//start packet
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+
+		#(CLK_PERIOD*5000);
+		
+	end
+	
+	repeat(4) begin
+		WIDTH = 3;
+		/******one packet*******/
+		//start packet
+		#(CLK_PERIOD*2);
+		data_in_startofpacket = 1'b1;
+
+		#(CLK_PERIOD*5000);
+		
+	end
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	assign data_in_endofpacket = (state == STATE_SEND && tx_ctr == WORDS_TO_SEND -1)? 1'b1: 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			tx_ctr <= 8'd0;
+			if (data_in_startofpacket)
+			begin
+				state <= STATE_SEND;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				data_in_startofpacket <= 1'b0;
+				tx_ctr <= tx_ctr + 1'b1;
+				if (tx_ctr < 60)
+						data_in_data<=0;
+					else if (tx_ctr < 60+WIDTH-1)
+						data_in_data <= HEIGHT/WIDTH + data_in_data;
+					else if (tx_ctr < 60+2*WIDTH-1)
+						data_in_data <= data_in_data-HEIGHT/WIDTH;
+					else if (tx_ctr < 60+3*WIDTH-1)
+						data_in_data <= HEIGHT/WIDTH + data_in_data;
+					else if (tx_ctr < 60+4*WIDTH-1)
+						data_in_data <= data_in_data-HEIGHT/WIDTH;
+					else if (tx_ctr < 60+5*WIDTH-1)
+						data_in_data <= HEIGHT/WIDTH + data_in_data;
+					else if (tx_ctr < 60+6*WIDTH-1)
+						data_in_data <= data_in_data-HEIGHT/WIDTH;
+					else
+						data_in_data <= 0;		
+				if (tx_ctr == WORDS_TO_SEND-1) begin
+					state <= STATE_LOC;
+				end 
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+			tx_ctr <= 8'd0;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v
new file mode 100644
index 0000000..f85b5db
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/sensor_algo_tb.v
@@ -0,0 +1,171 @@
+//This is a testbench from Sensorinterface to algo output
+//This is a testbench from the UDP generator
+
+
+`timescale 1 ns / 1 ns
+module sensor_algo_tb();
+
+
+//Signals
+
+	reg         clk_clk;                //      clk.clk
+	reg         rst_reset;              //      rst.reset
+	reg  [2:0]  csr_address;            //      csr.address
+	reg         csr_write;              //         .write
+	reg  [31:0] csr_writedata;          //         .writedata
+	reg  [3:0]  csr_byteenable;         //         .byteenable
+	reg         csr_read;               //         .read
+	wire [31:0] csr_readdata;           //         .readdata
+	  
+  
+	wire [31:0] data_out_data;          // data_out.data
+	wire [1:0]  data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg	    in_trg;                                //                  sensor.in_trg
+	wire        out_adc_clk;                           //                        .out_dac_clk
+	wire        out_adc_cnv;                           //                        .out_dac_cnv
+	reg [4:0]   in_adc_data;                           //                        .in_dac_data
+	wire        out_sensor_rst;                        //                        .out_sensor_rst
+	wire        out_sensor_clk;                        //                        .out_sensor_clk
+	wire        out_sensor_gain;                        //                        .out_sensor_gain
+
+	wire	    serial;
+	reg [7:0]  ext;	
+
+	reg[26:0] frameID;
+
+
+initial
+begin
+	clk_clk 			= 0;
+	rst_reset 			= 1;
+	csr_address 			= 3'd0;
+	csr_write 			= 0;
+	csr_writedata			= 32'd0;
+	csr_byteenable 			= 4'b1111;
+	csr_read 			= 0;
+	data_out_ready			= 1;	
+
+	in_trg 				= 0;
+	in_adc_data			= 5'b11011; //11111 with out any signal
+
+	ext = 0;
+
+	#50 
+	rst_reset = 0;
+
+		//write 0xAAAA0032 to register 2
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd2;
+	csr_writedata = 32'hAAAA0032;
+	#20
+	csr_write = 0;
+
+		//write 0x00040004 to register 1
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd1;
+	csr_writedata = 32'h01200004;
+	//csr_writedata = 32'h00040004;
+	#20
+	csr_write = 0;
+
+		//write 0x00060001 to register 0
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00060001;
+	#20
+	csr_write = 0;
+	
+	//write 0x20040032 to register 3
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd3;
+	csr_writedata = 32'h20040032;
+	#20
+	csr_write = 0;
+
+
+
+	//#500000
+	#1200000
+	$stop;
+
+end
+
+always #10 clk_clk = ~clk_clk;
+
+always @(posedge clk_clk) begin
+	if (data_out_startofpacket)
+		data_out_ready<=1;
+	if (data_out_endofpacket)
+		data_out_ready<=0;
+		end
+always #50010 in_trg = ~in_trg;
+
+
+//always #20 begin
+//	if (out_sensor_rst)
+//		 in_adc_data = in_adc_data + 1;	//dummy hay to ADCs
+//	else
+//		in_adc_data = 0;
+//end
+
+
+
+//always @(posedge out_adc_clk ) 
+//	begin
+//	if (frameID<8)
+//		in_adc_data[2] = ~in_adc_data[2]; //add some signal on the third sensor array
+//	else 
+//		in_adc_data[2] = 0;
+//	end
+
+sensor_algo	sensor_algo_dut(
+		.clk_clk			(clk_clk),                //      clk.clk
+		.rst_reset			(rst_reset),              //      rst.reset
+		
+		.csr_address			(csr_address),            //      csr.address
+		.csr_write			(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read			(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		
+		.data_out_data			(data_out_data),          // data_out.data
+		.data_out_empty			(data_out_empty),         //         .empty
+		.data_out_endofpacket		(data_out_endofpacket),   //         .endofpacket
+		.data_out_startofpacket		(data_out_startofpacket),//         .startofpacket
+		.data_out_ready			(data_out_ready),         //         .ready
+		.data_out_valid			(data_out_valid),          //         .valid
+		
+        	.in_trg 			(in_trg),                                //                  sensor.in_trg
+        	.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+        	.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+        	.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+        	.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+        	.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+        	.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+		.serial_rx			(serial),		//receive data
+		.serial_tx			(serial),		//send data
+		.ext_input			(ext),			//SMA etc.
+		
+		.status_out			(status_out),
+		
+		.address				(),
+		.cali_fac			(16'd3),
+		.clken				(),
+		.waitrequest		(1'b0)
+	);
+	
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v
new file mode 100644
index 0000000..6db2781
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/st2mm_tb.v
@@ -0,0 +1,135 @@
+//testbench for stl2sts: ST long 32-bit to ST short 16-bit
+
+`timescale 1 ns / 1 ns
+module st2mm_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	reg		  data_in_endofpacket;
+
+	
+	
+	//avalon MM(Memory Mapped) source  writelatency 0; readlatency 1 but no read logic here
+	wire [8:0] mm_address;
+	wire       mm_chipselect; // only for write
+	wire [31:0]	mm_readdate; //do not read
+	wire 		mm_write;
+	wire [31:0] mm_writedata;
+	reg mm_waitrequest_n;
+	
+	
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	st2mm #(.BITSIZE(32), .EMPTY_SIZE(2)) st2mm_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.mm_address		(mm_address),
+		.mm_chipselect	(mm_chipselect),
+		.mm_readdate	(mm_readdate),
+		.mm_write		(mm_write),
+		.mm_writedata	(mm_writedata),
+		.mm_waitrequest_n				(mm_waitrequest_n)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	data_in_endofpacket = 1'b0;
+	
+	mm_waitrequest_n = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	mm_waitrequest_n = 1'b1;
+	
+	//start packet
+	#(CLK_PERIOD*2+1);
+	data_in_startofpacket = 1'b1;
+	
+	#(CLK_PERIOD*2);
+	mm_waitrequest_n = 1'b0;
+	
+	#(CLK_PERIOD*2);
+	mm_waitrequest_n = 1'b1;
+	
+	
+	
+	//end packet
+	#(CLK_PERIOD*5);
+	data_in_endofpacket = 1'b1;
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket && data_in_ready)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+				data_in_startofpacket <= 1'b0;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				if (data_in_endofpacket) begin
+					state <= STATE_LOC;
+					data_in_data <= 0;
+					data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v
new file mode 100644
index 0000000..122b395
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/stl2sts_tb.v
@@ -0,0 +1,126 @@
+//testbench for stl2sts: ST long 32-bit to ST short 16-bit
+
+`timescale 1 ns / 1 ns
+module stl2sts_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [31:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	reg		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [15:0] data_out_data;          // data_out.data
+	wire        data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	stl2sts stl2sts_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	//start packet
+	#(CLK_PERIOD*2+1);
+	data_in_startofpacket = 1'b1;
+	
+	
+	
+	//end packet
+	#(CLK_PERIOD*5);
+	data_in_endofpacket = 1'b1;
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket && data_in_ready)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+				data_in_startofpacket <= 1'b0;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				if (data_in_endofpacket) begin
+					state <= STATE_LOC;
+					data_in_data <= 0;
+					data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v b/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v
new file mode 100644
index 0000000..6b24611
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/testbench/sts2stl_tb.v
@@ -0,0 +1,126 @@
+//testbench for sts2stl: ST short 16-bit to ST long 32-bit
+
+`timescale 1 ns / 1 ns
+module sts2stl_tb();
+
+	localparam CLK_PERIOD = 20; 
+
+	reg clk;
+	reg rst;
+	
+	//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
+	reg [15:0] data_in_data;
+	wire 		  data_in_ready;
+	wire		  data_in_valid;
+	reg [1:0]  data_in_empty;
+	reg		  data_in_startofpacket;
+	reg		  data_in_endofpacket;
+	
+	//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
+	wire [31:0] data_out_data;          // data_out.data
+	wire [1:0]  data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+	reg [1:0] state;
+	localparam STATE_IDLE = 2'd0;
+	localparam STATE_SEND = 2'd1;
+	localparam STATE_LOC = 2'd3;
+	
+	sts2stl sts2stl_dut(
+	
+		.clk		(clk),
+		.rst		(rst),
+		
+		.data_in_data		(data_in_data),
+		.data_in_ready		(data_in_ready),
+		.data_in_valid		(data_in_valid),
+		.data_in_empty		(data_in_empty),
+		.data_in_startofpacket		(data_in_startofpacket),
+		.data_in_endofpacket			(data_in_endofpacket),
+		
+		.data_out_data		(data_out_data),
+		.data_out_empty	(data_out_empty),
+		.data_out_endofpacket		(data_out_endofpacket),
+		.data_out_startofpacket		(data_out_startofpacket),
+		.data_out_ready	(data_out_ready),
+		.data_out_valid	(data_out_valid)
+		
+	);
+	
+	initial begin
+	
+	clk = 1'b1;
+	rst = 1'b1;
+	
+	data_in_data = 0;
+	data_in_empty = 2'b0;
+	data_in_startofpacket = 1'b0;
+	data_in_endofpacket = 1'b0;
+	
+	data_out_ready = 1'b0;
+	
+	state = STATE_IDLE;
+	
+	
+	#(CLK_PERIOD*2);
+	rst = 1'b0;
+	
+	//the next sink is ready..
+	#(CLK_PERIOD*20);
+	data_out_ready = 1'b1;
+	
+	//start packet
+	#(CLK_PERIOD*2+1);
+	data_in_startofpacket = 1'b1;
+	
+	
+	
+	//end packet
+	#(CLK_PERIOD*6);
+	data_in_endofpacket = 1'b1;
+	
+	
+	#(CLK_PERIOD*200); $stop;
+	
+	end
+	
+	
+	//clk
+	always #(CLK_PERIOD/2) clk = ~ clk;
+	
+	assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
+	always @(posedge clk) begin
+		case(state)
+		STATE_IDLE:
+		begin
+			if (data_in_startofpacket && data_in_ready)
+			begin
+				state <= STATE_SEND;
+				data_in_data <= data_in_data + 1;
+				data_in_startofpacket <= 1'b0;
+			end
+		end
+		STATE_SEND:
+		begin
+			if (data_in_ready)
+			begin
+				if (data_in_endofpacket) begin
+					state <= STATE_LOC;
+					data_in_data <= 0;
+					data_in_endofpacket <= 1'b0;
+				end else begin
+					data_in_data <= data_in_data + 1;
+				end
+			end
+		end
+		STATE_LOC:
+		begin
+			state <= STATE_IDLE;
+		end
+		endcase
+	end
+	
+endmodule	
\ No newline at end of file
diff --git a/FPGA_firmware/sensor_algo_qsys/unsaved.qsys b/FPGA_firmware/sensor_algo_qsys/unsaved.qsys
new file mode 100644
index 0000000..69154e8
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/unsaved.qsys
@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element sensor_recon_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C6GES" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName">sensor_algo_qsys.qpf</parameter>
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="sensor_recon_0_calibration_ram_interface"
+   internal="sensor_recon_0.calibration_ram_interface"
+   type="avalon"
+   dir="start" />
+ <interface
+   name="sensor_recon_0_clk"
+   internal="sensor_recon_0.clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sensor_recon_0_csr"
+   internal="sensor_recon_0.csr"
+   type="avalon"
+   dir="end" />
+ <interface
+   name="sensor_recon_0_data_out"
+   internal="sensor_recon_0.data_out"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="sensor_recon_0_rst"
+   internal="sensor_recon_0.rst"
+   type="reset"
+   dir="end" />
+ <interface
+   name="sensor_recon_0_sensor"
+   internal="sensor_recon_0.sensor"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_recon_0_status_out"
+   internal="sensor_recon_0.status_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sensor_recon_0_synchro"
+   internal="sensor_recon_0.synchro"
+   type="conduit"
+   dir="end" />
+ <module name="sensor_recon_0" kind="sensor_recon" version="1" enabled="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/FPGA_firmware/sensor_algo_qsys/unsaved.sopcinfo b/FPGA_firmware/sensor_algo_qsys/unsaved.sopcinfo
new file mode 100644
index 0000000..b4cffb0
--- /dev/null
+++ b/FPGA_firmware/sensor_algo_qsys/unsaved.sopcinfo
@@ -0,0 +1,1286 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="unsaved" kind="unsaved" version="1.0" fabric="QSYS">
+ <!-- Format version 19.1 670 (Future versions may contain additional information.) -->
+ <!-- 2024.07.18.17:16:55 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1721315815</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>MAX10FPGA</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>10M50DAF484C6GES</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>6</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_MAP">
+  <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>ADDRESS_MAP</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_calibration_ram_interface</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CALIBRATION_RAM_INTERFACE_ADDRESS_WIDTH">
+  <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
+  <value>AddressWidth = -1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_calibration_ram_interface</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_RATE">
+  <type>java.lang.Long</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_RATE</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_CLOCK_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_SENSOR_RECON_0_CLK_RESET_DOMAIN">
+  <type>java.lang.Integer</type>
+  <value>-1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+  <sysinfo_arg>sensor_recon_0_clk</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>MAX 10</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="sensor_recon_0"
+   kind="sensor_recon"
+   version="1"
+   path="sensor_recon_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="csr" kind="avalon_slave" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>embeddedsw.configuration.isFlash</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isMemoryDevice</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isNonVolatileStorage</name>
+    <value>0</value>
+   </assignment>
+   <assignment>
+    <name>embeddedsw.configuration.isPrintableDevice</name>
+    <value>0</value>
+   </assignment>
+   <parameter name="addressAlignment">
+    <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+    <value>DYNAMIC</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressSpan">
+    <type>java.math.BigInteger</type>
+    <value>16</value>
+    <derived>true</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgedAddressOffset">
+    <type>java.math.BigInteger</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bridgesToMaster">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="explicitAddressSpan">
+    <type>java.math.BigInteger</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isFlash">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isMemoryDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isNonVolatileStorage">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>false</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="minimumUninterruptedRunLength">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="printableDevice">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitStates">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="transparentBridge">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="wellBehavedWaitrequest">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitStates">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>false</isStart>
+   <port>
+    <name>csr_address</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>csr_read</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>csr_readdata</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>csr_write</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>write</role>
+   </port>
+   <port>
+    <name>csr_writedata</name>
+    <direction>Input</direction>
+    <width>32</width>
+    <role>writedata</role>
+   </port>
+   <port>
+    <name>csr_byteenable</name>
+    <direction>Input</direction>
+    <width>4</width>
+    <role>byteenable</role>
+   </port>
+  </interface>
+  <interface name="data_out" kind="avalon_streaming_source" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="beatsPerCycle">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dataBitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="emptyWithinPacket">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="errorDescriptor">
+    <type>[Ljava.lang.String;</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="firstSymbolInHighOrderBits">
+    <type>boolean</type>
+    <value>true</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="highOrderSymbolAtMSB">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxChannel">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="packetDescription">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readyLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="symbolsPerBeat">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon_streaming</type>
+   <isStart>true</isStart>
+   <port>
+    <name>data_out_endofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>endofpacket</role>
+   </port>
+   <port>
+    <name>data_out_data</name>
+    <direction>Output</direction>
+    <width>32</width>
+    <role>data</role>
+   </port>
+   <port>
+    <name>data_out_empty</name>
+    <direction>Output</direction>
+    <width>2</width>
+    <role>empty</role>
+   </port>
+   <port>
+    <name>data_out_ready</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>ready</role>
+   </port>
+   <port>
+    <name>data_out_startofpacket</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>startofpacket</role>
+   </port>
+   <port>
+    <name>data_out_valid</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>valid</role>
+   </port>
+  </interface>
+  <interface name="clk" kind="clock_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>false</isStart>
+   <port>
+    <name>clk_clk</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+  <interface name="rst" kind="reset_sink" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="synchronousEdges">
+    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+    <value>DEASSERT</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>reset</type>
+   <isStart>false</isStart>
+   <port>
+    <name>rst_reset</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>reset</role>
+   </port>
+  </interface>
+  <interface name="sensor" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>in_adc_data</name>
+    <direction>Input</direction>
+    <width>5</width>
+    <role>in_adc_data</role>
+   </port>
+   <port>
+    <name>in_trg</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>in_trg</role>
+   </port>
+   <port>
+    <name>out_adc_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_clk</role>
+   </port>
+   <port>
+    <name>out_adc_cnv</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_adc_cnv</role>
+   </port>
+   <port>
+    <name>out_sensor_clk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_clk</role>
+   </port>
+   <port>
+    <name>out_sensor_gain</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_gain</role>
+   </port>
+   <port>
+    <name>out_sensor_rst</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>out_sensor_rst</role>
+   </port>
+  </interface>
+  <interface name="status_out" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>status_out</name>
+    <direction>Output</direction>
+    <width>8</width>
+    <role>status_out</role>
+   </port>
+  </interface>
+  <interface name="synchro" kind="conduit_end" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>ext_input</name>
+    <direction>Input</direction>
+    <width>8</width>
+    <role>ext_input</role>
+   </port>
+   <port>
+    <name>serial_rx</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>serial_rx</role>
+   </port>
+   <port>
+    <name>serial_tx</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>serial_tx</role>
+   </port>
+  </interface>
+  <interface name="calibration_ram_interface" kind="avalon_master" version="19.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <parameter name="adaptsTo">
+    <type>com.altera.entityinterfaces.IConnectionPoint</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressGroup">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="addressUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="alwaysBurstMaxBurst">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value>clk</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value>rst</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="bitsPerSymbol">
+    <type>int</type>
+    <value>8</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstOnBurstBoundariesOnly">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="burstcountUnits">
+    <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+    <value>WORDS</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="constantBurstBehavior">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="dBSBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamReads">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="doStreamWrites">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="holdTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="interleaveBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isAsynchronous">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isBigEndian">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isReadable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="isWriteable">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="linewrapBursts">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maxAddressWidth">
+    <type>int</type>
+    <value>32</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingReadTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="maximumPendingWriteTransactions">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readLatency">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="readWaitTime">
+    <type>int</type>
+    <value>1</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerIncomingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="registerOutgoingSignals">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="setupTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="timingUnits">
+    <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+    <value>Cycles</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="writeWaitTime">
+    <type>int</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>avalon</type>
+   <isStart>true</isStart>
+   <port>
+    <name>address</name>
+    <direction>Output</direction>
+    <width>9</width>
+    <role>address</role>
+   </port>
+   <port>
+    <name>clken</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>read</role>
+   </port>
+   <port>
+    <name>cali_fac</name>
+    <direction>Input</direction>
+    <width>16</width>
+    <role>readdata</role>
+   </port>
+   <port>
+    <name>waitrequest</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>waitrequest</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>sensor_recon</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>sensor_recon_rms_cali</displayName>
+  <version>1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_slave</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Slave</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_streaming_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Streaming Source</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>reset_sink</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Reset Input</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>3</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>19.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>avalon_master</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Avalon Memory Mapped Master</displayName>
+  <version>19.1</version>
+ </plugin>
+ <reportVersion>19.1 670</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/FPGA_firmware/sensor_testbench.v b/FPGA_firmware/sensor_testbench.v
new file mode 100644
index 0000000..613bc3f
--- /dev/null
+++ b/FPGA_firmware/sensor_testbench.v
@@ -0,0 +1,131 @@
+//This is a testbench from the UDP generator
+
+
+`timescale 1 ns / 1 ns
+module sensor_testbench();
+
+
+//Signals
+
+	reg         clk_clk;                //      clk.clk
+	reg         rst_reset;              //      rst.reset
+	reg  [2:0]  csr_address;            //      csr.address
+	reg         csr_write;              //         .write
+	reg  [31:0] csr_writedata;          //         .writedata
+	reg  [3:0]  csr_byteenable;         //         .byteenable
+	reg         csr_read;               //         .read
+	wire [31:0] csr_readdata;           //         .readdata
+	wire [31:0] data_out_data;          // data_out.data
+	wire [1:0]  data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+        reg	    in_trg;                                //                  sensor.in_trg
+        wire        out_dac_clk;                           //                        .out_dac_clk
+        wire        out_dac_cnv;                           //                        .out_dac_cnv
+        reg [4:0]   in_adc_data;                           //                        .in_dac_data
+        wire        out_sensor_rst;                        //                        .out_sensor_rst
+        wire        out_sensor_clk;                        //                        .out_sensor_clk
+        wire        out_sensor_gain;                        //                        .out_sensor_gain
+
+	wire	    serial;
+	reg [7:0]  ext;	
+
+
+
+initial
+begin
+	clk_clk 			= 0;
+	rst_reset 			= 1;
+	csr_address 			= 3'd0;
+	csr_write 			= 0;
+	csr_writedata			= 32'd0;
+	csr_byteenable 			= 4'b1111;
+	csr_read 			= 0;
+	data_out_ready			= 1;	
+
+	in_trg 				= 0;
+	in_adc_data			= 5'b0;
+
+	ext = 0;
+
+	#50 
+	rst_reset = 0;
+
+		//write 0xAAAA0032 to register 2
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd2;
+	csr_writedata = 32'hAAAA0032;
+	#20
+	csr_write = 0;
+
+		//write 0x00040004 to register 1
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd1;
+	csr_writedata = 32'h00040004;
+	#20
+	csr_write = 0;
+
+		//write 0x00060001 to register 0
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00060001;
+	#20
+	csr_write = 0;
+
+
+
+
+
+	#500000
+	$stop;
+
+end
+
+always #10 clk_clk = ~clk_clk;
+always #20 in_adc_data = in_adc_data + 1;	//dummy hay to ADCs
+
+always #50010 in_trg = ~in_trg;
+
+
+	
+	
+
+
+sensor_interface the_sensor_interface (
+		.clk_clk			(clk_clk),                //      clk.clk
+		.rst_reset			(rst_reset),              //      rst.reset
+		.csr_address			(csr_address),            //      csr.address
+		.csr_write			(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read			(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		.data_out_data			(data_out_data),          // data_out.data
+		.data_out_empty			(data_out_empty),         //         .empty
+		.data_out_endofpacket		(data_out_endofpacket),   //         .endofpacket
+		.data_out_startofpacket		(data_out_startofpacket),//         .startofpacket
+		.data_out_ready			(data_out_ready),         //         .ready
+		.data_out_valid			(data_out_valid),          //         .valid
+        	.in_trg 			(in_trg),                                //                  sensor.in_trg
+        	.out_adc_clk 			(out_adc_clk),                           //                        .out_dac_clk
+        	.out_adc_cnv 			(out_adc_cnv),                           //                        .out_dac_cnv
+        	.in_adc_data 			(in_adc_data),                           //                        .in_dac_data
+        	.out_sensor_rst 		(out_sensor_rst),                        //                        .out_sensor_rst
+        	.out_sensor_clk 		(out_sensor_clk),                        //                        .out_sensor_clk
+        	.out_sensor_gain 		(out_sensor_gain),                        //                        .out_sensor_gain
+		.serial_rx			(serial),		//receive data
+		.serial_tx			(serial),		//send data
+		.ext_input			(ext)			//SMA etc.
+	);
+	
+	
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/serial_rx.v b/FPGA_firmware/serial_rx.v
new file mode 100644
index 0000000..cc1f14d
--- /dev/null
+++ b/FPGA_firmware/serial_rx.v
@@ -0,0 +1,84 @@
+// 9-bit Serial port receiver
+// It's very simple, just single sample halfway of each bit.
+// If start bit is not zero or stop bit is not one, an error will be signaled.
+// In general, this module is prone to glitches in signal. First of all, any glitch > Tclk will trigger the reception process.
+// RX is high on idle.
+// Baud rate is programmable via clk_divisor
+// clk_divisor ids internally divided by 2 to get in the middle of bit, so need to be at least 2.
+
+`timescale 100 ps / 100 ps
+module serial_rx (
+		input  wire        	clk,                	//      full-speed clock
+		input  wire        	rst,              	//      reset
+		input  wire [7:0]  	clk_divisor,         //      defines baudrate
+		input  wire 	   	rx,         		//      rx serial connection
+		output wire	   		newdata,		//	pulses for new data received
+		output wire [8:0]  	data,            	//      data to send
+		output wire	   		error,		//	bad start or stop bit
+		output wire	   		idle			//	1 if receiver in idle state
+	);
+
+	reg	[1:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_DATA		= 1;	//sending data
+	localparam STATE_FINISH		= 2;	//finished
+
+	reg	[4:0]	rx_ctr;			//counter of received data words
+	reg [7:0]	downctr;		//counter to generate baudrate
+	reg	[10:0]	buffer;			//internal latch/shift register with start and stop bit
+	reg	[8:0]	reg_data;		//latched received data
+	reg			reg_error;		//latched error
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+		begin
+			state <= STATE_IDLE;
+			reg_data <= 0;
+			reg_error <= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (~rx)
+					begin
+						state 		<= STATE_DATA;
+						rx_ctr 		<= 10;
+						downctr[6:0]<= clk_divisor[7:1];	//wait half a bit
+						downctr[7]	<= 0;
+						buffer		<= 0;
+					end
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr 	<= clk_divisor;
+						rx_ctr 		<= rx_ctr - 1;
+						buffer[9:0] <= buffer[10:1];
+						buffer[10] 	<= rx;
+						if (rx_ctr == 0)
+							state 	<= STATE_FINISH;
+					end
+				end
+				STATE_FINISH:
+				begin
+					reg_data[8:0] 	<= buffer[9:1];
+					reg_error		<= buffer[0] | ~buffer[10];	//high start or low stop bit
+					state 			<= STATE_IDLE;
+				end
+				default:
+					state 			<= STATE_IDLE;
+			endcase
+	end
+	
+		//assignments
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+	assign data = reg_data;
+	assign error =  reg_error;
+
+
+endmodule
diff --git a/FPGA_firmware/serial_testbench.v b/FPGA_firmware/serial_testbench.v
new file mode 100644
index 0000000..b7d64f8
--- /dev/null
+++ b/FPGA_firmware/serial_testbench.v
@@ -0,0 +1,77 @@
+//This is a testbench from the UDP generator
+
+
+`timescale 1 ns / 1 ns
+module serial_testbench();
+
+
+//Signals
+
+	reg         clk;               
+	reg         rst;             
+	reg  [8:0]  tx_data;              
+	reg  [7:0]  clk_divisor;              
+	reg  	    trigger;          
+	wire        serdata; 
+	wire        tx_idle;     
+	wire 	    newdata;
+	wire [8:0]  rx_data;
+	wire        rx_error;
+	wire	    rx_idle;
+
+initial
+begin
+	clk 		= 0;
+	rst 		= 1;
+	tx_data		= 9'h155;
+	clk_divisor	= 20;
+	trigger		= 0;
+
+	#50 
+	rst 		= 0;
+
+	#20
+	trigger 	= 1;
+	#20
+	trigger 	= 0;
+
+	#12000
+	tx_data 	= 9'h05E;
+
+	#20
+	trigger 	= 1;
+	#20
+	trigger 	= 0;
+
+	#20000
+	$stop;
+
+end
+
+always #10 clk = ~clk;
+
+
+serial_tx the_tx (
+		.clk		(clk),                	//      full-speed clock
+		.rst		(rst),              	//      reset
+		.data		(tx_data),            	//      data to send
+		.clk_divisor	(clk_divisor),         //      defines baudrate
+		.trigger	(trigger),          	//      pulse to start transmission
+		.tx		(serdata),         		//      tx serial connection
+		.idle		(tx_idle)			//	1 if sender in idle state
+	);	
+
+
+serial_rx the_rx(
+		.clk		(clk),                	//      full-speed clock
+		.rst		(rst),              	//      reset
+		.clk_divisor	(clk_divisor),         //      defines baudrate
+		.rx		(serdata),         		//      rx serial connection
+		.newdata		(newdata),		//	pulses for new data received
+		.data		(rx_data),            	//      data to send
+		.error		(rx_error),		//	bad start or stop bit
+		.idle		(rx_idle)
+	);
+
+
+endmodule
\ No newline at end of file
diff --git a/FPGA_firmware/serial_tx.v b/FPGA_firmware/serial_tx.v
new file mode 100644
index 0000000..ab1b607
--- /dev/null
+++ b/FPGA_firmware/serial_tx.v
@@ -0,0 +1,115 @@
+// 9-bit Serial port transmitter
+// TX is high on idle.
+// Baud rate is programmable via clk_divisor
+
+`timescale 100 ps / 100 ps
+module serial_tx (
+		input  wire        clk,                	//      full-speed clock
+		input  wire        rst,              	//      reset
+		input  wire [8:0]  data,            	//      data to send
+		input  wire [7:0]  clk_divisor,         //      defines baudrate
+		input  wire 	   trigger,          	//      pulse to start transmission
+		output wire 	   tx,         		//      tx serial connection
+		output wire	   idle			//	1 if sender in idle state
+
+	);
+
+	reg	[2:0]	state;		//State of the state machine
+	localparam STATE_IDLE		= 0;	//waiting for enable
+	localparam STATE_STARTBIT	= 1;	//sending start bit
+	localparam STATE_DATA		= 2;	//sending data
+	localparam STATE_STOPBIT	= 3;	//sending stop bit
+	localparam STATE_FINISH		= 4;	//finished
+
+	reg	[4:0]	tx_ctr;			//counter of sent data words
+	reg 	[7:0]	downctr;		//counter to generate baudrate
+	reg	[8:0]	buffer;			//internal latch/shift register
+	reg		reg_tx;
+
+		//The state machine
+	always @(posedge clk or posedge rst)
+	begin 
+		if (rst)
+			state <= STATE_FINISH;
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (trigger)
+					begin
+						state <= STATE_STARTBIT;
+						tx_ctr <= 8;
+						buffer <= data;
+						downctr <= clk_divisor;
+					end
+				end
+				STATE_STARTBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_DATA;
+					end
+
+				end
+				STATE_DATA:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						tx_ctr <= tx_ctr - 1;
+						buffer[7:0] <= buffer[8:1];
+						buffer[8] <= 0;
+						if (tx_ctr == 0)
+							state <= STATE_STOPBIT;
+					end
+				end
+				STATE_STOPBIT:
+				begin
+					downctr = downctr - 1;
+					if (downctr == 0)
+					begin
+						downctr <= clk_divisor;
+						state <= STATE_FINISH;
+					end
+
+				end
+				STATE_FINISH:
+				begin
+					if (~trigger)
+						state <= STATE_IDLE;
+				end
+				default:
+					state <= STATE_FINISH;
+			endcase
+	end
+	
+		//tx assignment
+	always @( * )
+	begin
+		if (rst)
+			reg_tx = 1;
+		else
+			case(state)
+				STATE_IDLE:
+					reg_tx = 1;
+				STATE_STARTBIT:
+					reg_tx = 0;
+				STATE_DATA:
+					reg_tx = buffer[0];
+				STATE_STOPBIT:
+					reg_tx = 1;
+				STATE_FINISH:
+					reg_tx = 1;
+				default:
+					reg_tx = 1;
+			endcase
+	end
+	assign tx = reg_tx;
+
+		//idle assignment
+	assign idle = (state == STATE_IDLE) ? 1 : 0;
+
+endmodule
diff --git a/FPGA_firmware/tcl_readme.txt b/FPGA_firmware/tcl_readme.txt
new file mode 100644
index 0000000..6d068bc
--- /dev/null
+++ b/FPGA_firmware/tcl_readme.txt
@@ -0,0 +1,3 @@
+The design example by default has Rev C pinout in the Pin Planner. If you would like to change the pinout to Rev B, go to Tools -> Tcl Scripts and select RevC_to_RevB.tcl and hit Run. 
+If you want to go back to Rev C, you can execute RevB_to_RevC.tcl pinout.
+To find out the Revision of your board, look at the back of the board towards the bottom center. You can also refer to the image on design store.
\ No newline at end of file
diff --git a/FPGA_firmware/udp_generator.v b/FPGA_firmware/udp_generator.v
new file mode 100644
index 0000000..c3b1535
--- /dev/null
+++ b/FPGA_firmware/udp_generator.v
@@ -0,0 +1,396 @@
+// UDP generator
+/*
+Takes an input stream and generates a valid UDP/IPv4 packet, then outputs it as a stream which can be directly connected to TSE.
+
+Remarks:
+- Both input and output are Avalon ST ports, 8-bit symbol, 4 symbols per beat
+- Start/end of packet signals are REQUIRED.
+- Empty signals are discarded. An incoming packet should have a length of 4N. If not, it will be padded with what's on the bus.
+- Backpressure is supported and actively used during transfer. Data source must be backpressurizable.
+- The transfer is performed on the fly, without buffering. Input gets backpressed for the time of sending headers.
+- Size of payload must be known in advance and programmed over Avalon MM interface. 
+- Longer packets will be cut. Shorter packets will be padded with zeros.
+- UDP checksum is not calculated (the price of realtime approach) and filled with zeros. IP header checksum is calculated.
+- The Programming interface is an Avalon MM. It's 32-bit wide and allows byte, halfword and word operations. Block transfers are not supported.
+- Source MAC is not programmable; it must be filled by TSE. 
+- Two leading zero bytes are added on front of the packet for 32-bit alignment. TSE settings must comply wit this.
+- If transfer is disabled (see control bits), the input will be backpressed all the time.
+- Maximum transfer size is about 64K, but limitations of the Ethernet must be taken into account.
+- The IPv4 header has the 'Don't fragment' flag set.
+
+Register map: (byte offsets are given)
+UDPGEN_REG_CSR		0	//16 bits 	8 bits control(LSB) + 8 bits status(MSB)
+UDPGEN_REG_SIZE		2	//16 bits	payload size in words
+UDPGEN_REG_SRCIP	4	//32 bits	source IP, last octet first
+UDPGEN_REG_DSTIP	8	//32 bits	destination IP. last octet first
+UDPGEN_REG_DSTPORT	12	//16 bits	destination port
+UDPGEN_REG_SRCPORT	14	//16 bits	source port
+UDPGEN_REG_DSTMAC	16	//2*32 bits	destination MAC, last octet first
+UDPGEN_REG_RES1		24	//32 bits	reserved
+UDPGEN_REG_RES2		28 	//32 bits	reserved
+
+Control bits:
+0: transfer enable
+1-7: unused
+
+Status bits:
+0-3: state of the machine
+7-4: unused
+
+*/
+
+
+`timescale 100 ps / 100 ps
+module udp_generator (
+		input  wire        clk_clk,                //      clk.clk
+		input  wire        rst_reset,              //      rst.reset
+		input  wire [2:0]  csr_address,            //      csr.address
+		input  wire        csr_write,              //         .write
+		input  wire [31:0] csr_writedata,          //         .writedata
+		input  wire [3:0]  csr_byteenable,         //         .byteenable
+		input  wire        csr_read,               //         .read
+		output wire [31:0] csr_readdata,           //         .readdata
+		input  wire [31:0] data_in_data,           //  data_in.data
+		output wire        data_in_ready,          //         .ready
+		input  wire        data_in_valid,          //         .valid
+		input  wire [1:0]  data_in_empty,          //         .empty
+		input  wire        data_in_endofpacket,    //         .endofpacket
+		input  wire        data_in_startofpacket,  //         .startofpacket
+		output wire [31:0] data_out_data,          // data_out.data
+		output wire [1:0]  data_out_empty,         //         .empty
+		output wire        data_out_endofpacket,   //         .endofpacket
+		output wire        data_out_startofpacket, //         .startofpacket
+		input  wire        data_out_ready,         //         .ready
+		output wire        data_out_valid          //         .valid
+	);
+
+
+	// *********************** CSR stuff ************************
+	
+	reg 	[31:0] 	registers[7:0];		//main register space
+	wire 	[31:0]	reg0_read;		//reg[0] is read indirectly to include status byt(bits 15-8)
+
+		//read logic
+	assign reg0_read[7:0] 	= registers[0][7:0];		// Readback of control bits
+	assign reg0_read[31:16] = registers[0][31:16];		// Readback of payload size
+	assign reg0_read[15:12] = 0;				// Unused bits of the status byte
+	assign csr_readdata 	= (csr_address==0) ? reg0_read : registers[csr_address];
+
+		//write logic
+	genvar i;
+	genvar j;
+	generate
+	for (i = 0; i < 8; i = i+1)
+	begin : write_registers	//Quartus wants labels for 'for' blocks
+		for (j = 0; j < 4; j = j+1)
+		begin : write_bytes
+			always @(posedge clk_clk or posedge rst_reset)
+			begin 
+				if (rst_reset)
+					registers[i][8*j+7:8*j] <= 8'd0;
+				else
+					if (csr_byteenable[j] && (csr_address == i) && (csr_write))
+						registers[i][8*j+7:8*j] <= csr_writedata[8*j+7:8*j];
+			end
+		end
+	end	
+	endgenerate
+	
+	
+	// *********************** ST interface ***********************
+
+	reg	[4:0]	state;		//State of the state machine
+	localparam STATE_IDLE	= 0;	//waiting for SOP
+	localparam STATE_MAC1	= 1;	//sending first word of MAC header: 				00 00 dest_mac[5:4]
+	localparam STATE_MAC2	= 2;	//sending second word of MAC header: 				dest_mac[3:0]
+	localparam STATE_MAC3	= 3;	//sending zeroes as source MAC msbs:				00 00 00 00
+	localparam STATE_MAC4	= 4;	//sending zeroes as source MAC lsbs & packet type:		00 00 08 00
+	localparam STATE_IP1	= 5;	//sending IP ver & header size, DSF, total length		45 00 length[1:0]
+	localparam STATE_IP2	= 6;	//sending IP id, flags (don't fragment), fragm. offset=0	ip_id[1:0] 40 00
+	localparam STATE_IP3	= 7;	//sending TTL, protocol, header checksum			80 11 checksum[1:0]
+	localparam STATE_IP4	= 8;	//sending source IP						src_ip[4:0]
+	localparam STATE_IP5	= 9;	//sending destination IP					dst_ip[4:0]
+	localparam STATE_UDP1	= 10;	//sending src & dest port					src_port[1:0] dst_port[1:0]
+	localparam STATE_UDP2	= 11;	//sending UDP frame length and (unused) checksum		udp_length[1:0] 00 00
+	localparam STATE_DATA	= 12;	//sending packet data but the last word
+	localparam STATE_PAD	= 13;	//padding packet with zeros if incoming packet was too short
+	localparam STATE_DUMP	= 14;	//dumping tail of incoming packet if it was too long
+	localparam STATE_END	= 15;	//transfer finished, just wait one cycle
+
+	reg		reg_ready;	//registers to drive output pins of ST interfaces
+	reg		reg_valid;
+	reg	[31:0]	reg_data;
+	reg		reg_startofpacket;
+	reg		reg_endofpacket;
+	reg		reg_empty;
+
+		//Helper stuff
+	wire	[15:0]	udp_length;	
+	wire	[15:0]	total_length;
+	wire	[19:0]  int_checksum;
+	wire 	[16:0]	int_checksum2;	
+	wire	[15:0]	header_checksum;	
+	reg	[15:0]	ip_id;	//unique identifier of a packet
+	reg	[15:0]	tx_ctr;	//counter of sent data words
+
+	assign reg0_read[11:8] = state;	//state forwarded to status register
+
+	assign udp_length = 4*registers[0][31:16] + 16'd8;	
+	assign total_length = 4*registers[0][31:16] + 16'd28;
+
+	assign int_checksum = 20'h10511 + total_length + ip_id + registers[1][31:16] + registers[1][15:0] + registers[2][31:16] + registers[2][15:0];
+	assign int_checksum2 = int_checksum[15:0] + int_checksum[19:16];
+	assign header_checksum = ~(int_checksum2[15:0] + int_checksum2[16]);
+
+		//The state machine
+	always @(posedge clk_clk or posedge rst_reset)
+	begin 
+		if (rst_reset)
+		begin
+			state <= STATE_IDLE;
+			ip_id<= 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					if (data_in_startofpacket && registers[0][0])
+					begin
+						state <= STATE_MAC1;
+						ip_id <= ip_id+1;
+						tx_ctr <= 1;
+					end
+				end
+				STATE_MAC1, STATE_MAC2, STATE_MAC3, STATE_MAC4, STATE_IP1, STATE_IP2, STATE_IP3, STATE_IP4, STATE_IP5, STATE_UDP1, STATE_UDP2:
+				begin
+					if (data_out_ready)
+						state <= state + 1;
+				end
+				STATE_DATA:
+				begin
+					if (data_out_ready && data_in_valid)
+					begin
+						tx_ctr <= tx_ctr+1;
+						if ((tx_ctr == registers[0][31:16]) && data_in_endofpacket)	//last word, size matches
+							state <= STATE_END;
+						else if (data_in_endofpacket)					//packet too short
+							state <= STATE_PAD;
+						else if (tx_ctr == registers[0][31:16])				//packet too long
+							state <= STATE_DUMP;
+					end
+				end
+				STATE_PAD:
+				begin
+					if (data_out_ready)
+					begin
+						tx_ctr <= tx_ctr+1;
+						if (tx_ctr == registers[0][31:16])				
+							state <= STATE_END;
+					end	
+				end
+				STATE_DUMP:
+				begin
+					if (data_out_ready && data_in_valid)
+					begin
+						if (data_in_endofpacket)
+							state <= STATE_END;
+					end
+				end
+
+				default:
+				begin
+					state <= STATE_IDLE;
+				end
+			endcase
+	end
+
+		//Driving bus signals
+	always @( * )
+	begin
+		if (rst_reset)
+		begin
+			reg_ready = 0;
+			reg_valid = 0;
+			reg_data = 0;
+			reg_startofpacket = 0;
+			reg_endofpacket = 0;
+			reg_empty = 0;
+		end
+		else
+			case(state)
+				STATE_IDLE:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16] 	= 0;
+					reg_data[15:0] 		= registers[5][15:0];
+					reg_startofpacket 	= 1;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= registers[4];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC3:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= 32'h00000000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_MAC4:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data 		= 32'h00000800;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= 16'h4500;
+					reg_data[15:0]		= total_length;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= ip_id;
+					reg_data[15:0]		= 16'h4000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP3:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= 16'h8011;
+					reg_data[15:0]		= header_checksum;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP4:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[1];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_IP5:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[2];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_UDP1:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= registers[3];
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_UDP2:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data[31:16]		= udp_length;
+					reg_data[15:0]		= 16'h0000;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_DATA:
+				begin
+					reg_ready 		= data_out_ready;
+					reg_valid 		= data_in_valid;
+					reg_data		= data_in_data;
+					reg_startofpacket 	= 0;
+					if (tx_ctr == registers[0][31:16])
+						reg_endofpacket 	= 1;
+					else
+						reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_PAD:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 1;
+					reg_data		= 32'h0;
+					reg_startofpacket 	= 0;
+					if (tx_ctr == registers[0][31:16])
+						reg_endofpacket 	= 1;
+					else
+						reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				STATE_DUMP:
+				begin
+					reg_ready 		= 1;
+					reg_valid 		= 0;
+					reg_data		= 0;
+					reg_startofpacket = 0;
+					reg_endofpacket = 0;
+					reg_empty 		= 0;
+				end
+				STATE_END:
+				begin
+					reg_ready 		= 0;
+					reg_valid 		= 0;
+					reg_data 		= 0;
+					reg_startofpacket 	= 0;
+					reg_endofpacket 	= 0;
+					reg_empty 		= 0;
+				end
+				default:
+				begin
+					reg_ready = 0;
+					reg_valid = 0;
+					reg_data = 0;
+					reg_startofpacket = 0;
+					reg_endofpacket = 0;
+					reg_empty = 0;
+				end
+			endcase
+	end
+
+	
+	assign data_in_ready = reg_ready;
+	assign data_out_valid = reg_valid;
+	assign data_out_data = reg_data;
+	assign data_out_startofpacket = reg_startofpacket;
+	assign data_out_endofpacket = reg_endofpacket;
+	assign data_out_empty = reg_empty;
+
+endmodule
diff --git a/FPGA_firmware/udp_testbench.v b/FPGA_firmware/udp_testbench.v
new file mode 100644
index 0000000..b6ed7b1
--- /dev/null
+++ b/FPGA_firmware/udp_testbench.v
@@ -0,0 +1,180 @@
+//This is a testbench from the UDP generator
+
+
+`timescale 1 ns / 1 ns
+module udp_testbench();
+
+
+//Signals
+
+	reg         clk_clk;                //      clk.clk
+	reg         rst_reset;              //      rst.reset
+	reg  [2:0]  csr_address;            //      csr.address
+	reg         csr_write;              //         .write
+	reg  [31:0] csr_writedata;          //         .writedata
+	reg  [3:0]  csr_byteenable;         //         .byteenable
+	reg         csr_read;               //         .read
+	wire [31:0] csr_readdata;           //         .readdata
+	reg  [31:0] data_in_data;           //  data_in.data
+	wire        data_in_ready;          //         .ready
+	reg         data_in_valid;          //         .valid
+	reg  [1:0]  data_in_empty;          //         .empty
+	reg         data_in_endofpacket;    //         .endofpacket
+	reg         data_in_startofpacket;  //         .startofpacket
+	wire [31:0] data_out_data;          // data_out.data
+	wire [1:0]  data_out_empty;         //         .empty
+	wire        data_out_endofpacket;   //         .endofpacket
+	wire        data_out_startofpacket; //         .startofpacket
+	reg         data_out_ready;         //         .ready
+	wire        data_out_valid;          //         .valid
+
+
+initial
+begin
+	clk_clk 			= 0;
+	rst_reset 			= 1;
+	csr_address 			= 3'd0;
+	csr_write 			= 0;
+	csr_writedata			= 32'd0;
+	csr_byteenable 			= 4'b1111;
+	csr_read 			= 0;
+	data_in_data			= 32'd0;
+	data_in_valid			= 0;
+	data_in_empty			= 2'd0;
+	data_in_endofpacket  		= 0;
+	data_in_startofpacket 		= 0;
+	data_out_ready			= 0;	
+
+	#50 
+	rst_reset = 0;
+		//write 0x00F00001 to register 0 - size=240 + enable
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00100001;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+		//write 0x0A000711 to register 1 - SRC IP = 10.0.7.17
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd1;
+	csr_writedata = 32'h0A000711;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+	//write 0x0A000701 to register 2 - DST IP = 10.0.7.1
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd2;
+	csr_writedata = 32'h0A000701;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+	//write 0x01000100 to register 3 - SRC port = 4096, DST port = 4096
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd3;
+	csr_writedata = 32'h01000100;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+	//write 0xc705aa63 to register 4 - DST MAC lower bytes = 70 05 aa 63
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd4;
+	csr_writedata = 32'hc705aa63;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+	//write 0x000018d6 to register 5 - DST MAC higher bytes = 18 d6
+	#20
+	csr_write = 1;
+	csr_byteenable = 4'b1111;
+	csr_address = 3'd5;
+	csr_writedata = 32'h000018d6;
+	#20
+	csr_write = 0;
+	csr_byteenable = 4'b0000;
+	csr_address = 3'd0;
+	csr_writedata = 32'h00000000;
+
+	//Start transmission
+	#102
+	data_in_valid = 1;
+	data_in_startofpacket = 1;
+	data_in_data = 32'h12345678;
+
+	//backpressure - ready signal from receiver
+	#40
+	data_out_ready = 1;
+	#20
+	data_in_startofpacket = 0;
+
+	//finish sending data
+	#480
+	data_in_endofpacket = 1;
+	#20
+	data_in_endofpacket = 0;
+	data_in_valid = 0;
+
+
+	#1500
+	$stop;
+
+end
+
+always #10 clk_clk = ~clk_clk;
+
+
+	
+	
+
+// UDP generator
+
+
+udp_generator the_udp_generator (
+		.clk_clk					(clk_clk),                //      clk.clk
+		.rst_reset				(rst_reset),              //      rst.reset
+		.csr_address				(csr_address),            //      csr.address
+		.csr_write				(csr_write),              //         .write
+		.csr_writedata			(csr_writedata),          //         .writedata
+		.csr_byteenable			(csr_byteenable),         //         .byteenable
+		.csr_read					(csr_read),               //         .read
+		.csr_readdata			(csr_readdata),           //         .readdata
+		.data_in_data			(data_in_data),           //  data_in.data
+		.data_in_ready			(data_in_ready),          //         .ready
+		.data_in_valid			(data_in_valid),          //         .valid
+		.data_in_empty			(data_in_empty),          //         .empty
+		.data_in_endofpacket	(data_in_endofpacket),    //         .endofpacket
+		.data_in_startofpacket(data_in_startofpacket),  //         .startofpacket
+		.data_out_data			(data_out_data),          // data_out.data
+		.data_out_empty			(data_out_empty),         //         .empty
+		.data_out_endofpacket	(data_out_endofpacket),   //         .endofpacket
+		.data_out_startofpacket(data_out_startofpacket),//         .startofpacket
+		.data_out_ready			(data_out_ready),         //         .ready
+		.data_out_valid			(data_out_valid)          //         .valid
+	);
+	
+	
+endmodule
\ No newline at end of file
diff --git a/FPGA_nios/.gitignore b/FPGA_nios/.gitignore
new file mode 100644
index 0000000..97d8c59
--- /dev/null
+++ b/FPGA_nios/.gitignore
@@ -0,0 +1,60 @@
+.metadata
+bin/
+tmp/
+*.tmp
+*.bak
+*.swp
+*~.nib
+local.properties
+.settings/
+.loadpath
+.recommenders
+
+# External tool builders
+.externalToolBuilders/
+
+# Locally stored "Eclipse launch configurations"
+*.launch
+
+# PyDev specific (Python IDE for Eclipse)
+*.pydevproject
+
+# CDT-specific (C/C++ Development Tooling)
+.cproject
+
+# CDT- autotools
+.autotools
+
+# Java annotation processor (APT)
+.factorypath
+
+# PDT-specific (PHP Development Tools)
+.buildpath
+
+# sbteclipse plugin
+.target
+
+# Tern plugin
+.tern-project
+
+# TeXlipse plugin
+.texlipse
+
+# STS (Spring Tool Suite)
+.springBeans
+
+# Code Recommenders
+.recommenders/
+
+# Annotation Processing
+.apt_generated/
+.apt_generated_test/
+
+# Scala IDE specific (Scala & Java development for Eclipse)
+.cache-main
+.scala_dependencies
+.worksheet
+
+# Uncomment this line if you wish to ignore the project description file.
+# Typically, this file would be tracked if it contains build/dependency configurations:
+#.project
\ No newline at end of file
diff --git a/FPGA_nios/hit_pat/.force_relink b/FPGA_nios/hit_pat/.force_relink
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_nios/hit_pat/.project b/FPGA_nios/hit_pat/.project
new file mode 100644
index 0000000..784fbe8
--- /dev/null
+++ b/FPGA_nios/hit_pat/.project
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>hit_pat</name>
+	<comment></comment>
+	<projects>
+		<project>hit_pat_bsp</project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+	</natures>
+</projectDescription>
diff --git a/FPGA_nios/hit_pat/create-this-app b/FPGA_nios/hit_pat/create-this-app
new file mode 100644
index 0000000..0bd09c1
--- /dev/null
+++ b/FPGA_nios/hit_pat/create-this-app
@@ -0,0 +1,131 @@
+#!/bin/bash
+#
+# This script creates the simple_socket_server application in this directory.
+
+
+BSP_DIR=../hit_pat_bsp
+QUARTUS_PROJECT_DIR=../../
+NIOS2_APP_GEN_ARGS="--elf-name hit_pat.elf  --set OBJDUMP_INCLUDE_SOURCE 1 --src-files alt_error_handler.c iniche_init.c led.c network_utilities.c simple_socket_server.c tse_my_system.c"
+
+# If script is launched from Windows through Windows Subsystem for Linux (WSL).  
+# The adjust-path macro converts absolute windows 
+# paths into unix style paths (Example: c:/dir -> /c/dir). This will ensure
+# paths are readable.
+uname=$(uname -r)
+if [[ $uname =~ "Microsoft" ]]; then
+    _IS_WSL=1
+    windows_exe=.exe
+fi
+
+adjust_path() {
+    if [ "${_IS_WSL}" = "1" ] && [[ ! $1 =~ ^\/mnt\/* ]]; then
+        echo "$(wslpath -u "$1")"
+	else
+		echo "$1"
+	fi
+}
+
+# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
+# This variable is required for the command line tools to execute correctly.
+if [ -z "${SOPC_KIT_NIOS2}" ]
+then
+    echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
+    exit 1
+fi
+
+
+# Also make sure that the APP has not been created already.  Check for
+# existence of Makefile in the app directory
+if [ -f ./Makefile ]
+then
+    echo Application has already been created!  Delete Makefile if you want to create a new application makefile
+    exit 1
+fi
+
+
+# We are selecting ucosii_net bsp because it supports this application.
+# Check to see if the ucosii_net has already been generated by checking for
+# existence of the public.mk file.  If not, we need to run
+# create-this-bsp file to generate the bsp.
+if [ ! -f ${BSP_DIR}/public.mk ]; then
+    # Since BSP doesn't exist, create the BSP
+    # Pass any command line arguments passed to this script to the BSP.
+    pushd "$(adjust_path ${BSP_DIR})" >> /dev/null
+    ./create-this-bsp "$@" || {
+        echo "create-this-bsp failed"
+        exit 1
+    }
+    popd >> /dev/null
+fi
+
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+  case "$1" in
+      --no-make)
+          SKIP_MAKE=1
+          ;;
+  esac
+  shift
+done
+
+
+# Now we also need to go copy the sources for this application to the
+# local directory.
+find "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
+        echo "failed during copying example source files"
+        exit 1
+}
+
+find "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
+        echo "failed copying readme file"
+}
+
+if [ -d "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/system" ]
+then
+        cp -RL "${SOPC_KIT_NIOS2}/examples/software/simple_socket_server/system" . || {
+                echo "failed during copying project support files"
+                exit 1
+        }
+fi
+
+chmod -R +w . || {
+        echo "failed during changing file permissions"
+        exit 1
+}
+
+cmd="nios2-app-generate-makefile$windows_exe --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
+
+echo "create-this-app: Running \"${cmd}\""
+$cmd || {
+    echo "nios2-app-generate-makefile failed"
+    exit 1
+}
+
+if [ -z "$SKIP_MAKE" ]; then
+        cmd="make"
+
+        echo "create-this-app: Running \"$cmd\""
+        $cmd || {
+        echo "make failed"
+            exit 1
+        }
+
+        echo
+        echo "To download and run the application:"
+        echo "    1. Make sure the board is connected to the system."
+        echo "    2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
+        echo "    3. If you have a stdio device, run 'nios2-terminal' in a different shell."
+        echo "    4. Run 'make download-elf' from the application directory."
+        echo
+        echo "To debug the application:"
+        echo "    Import the project into Nios II Software Build Tools for Eclipse."
+        echo "    Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
+        echo
+        echo -e ""
+fi
+
+
+exit 0
diff --git a/FPGA_nios/hit_pat/hit_pat.elf b/FPGA_nios/hit_pat/hit_pat.elf
new file mode 100644
index 0000000000000000000000000000000000000000..1375c4b466bec1628c093079352ab673360cb590
GIT binary patch
literal 2092301
zcmdSC4R~B-nehM2%$bv<Nv0<yCuh=+>5Qe*gqD&*sm-D7oI)xevRYZ$tslEvMPJMM
zu2#iemvy%%IDsjYHDFnT3u|OSii!pWsa@C{B&Bh!OVOffX>E$SfQlj%fqu>ZcR%M$
zGEGy&>wT~P_5b(ca8Ay7KJMp!?(gS*p4qVK(znE7F;)2&S07XI*V2TlUCe#{FJ|jc
zi&a*|Rhv3XrS<oyd@c9dP2V@vZNEsW8hL4{@cS-9{%V#h%m3s`a>@7qKm9YFFaOk5
z!2vt&jo1l)#5RHvJE`{Arnkqg@%PxZ!Jex->Xlum_S#dty>`97*KP>*+KuWdJLNrP
zPxYU&t>7uU$=hR;%fGUx1y8w)>eQvmZ_6i?m5-}zFkAU1$g`(;2b}WYvqrh_oVP&v
znYgklbsXwD@*P;NULR|7fX4wI2Y4Ldae&7G9tU_FU~z!O0Tu^X9AI&P#Q_!vSd7zx
zpSrdFZ;jU&o5|Rc>VUx&eA@EeMM-5J9UOJI>@wG}!f2QBm3^Fd<?^V*-CbWy=bMz}
z92*=x+-q9*$F5OssVD91do_AjTX~mt_HVV^Qk~^KyCUtDVoJAvgtoY3%(}f&kEPqE
zJ^He2?&i-6O8N&MqnV!;EWaDrq<-nmqfRUU55OE}9Bt}V;|Sw07)OG4T)=$ru#6+B
zzipRc?X00){&vsdy^Q6a{$2SR#=t!q*FoplhJ(PG23E_AE9Letr@!Q+eKxCW)HzVI
z@#>(}a%@m7Rzqg93VwQ3>>9KA>o@;+F*s@d**C4LV&7HGA9^jFPXv}N<zv3J<XG7X
z9-Qi%<$^Mf13Tm4+X1)KIZ}juf)3}88mr7hy$Y-wkC#Vp;NDm+kJi)Ajf}U*Sc@?)
zCUf9l9rr1FF#1~s+4!mZISO0};ED^L)q$?dZ&5eWmSJ?OM%ulxTsWz1>B}uOT5r7l
zXuggY4%*;eXu)Cronz(EeB6g#lFDp?FX+px7g{N6dJtMmFut7yU--uo`qZ=pT$+Bk
z3*GcmCi7we`itgJXeJiX%<mXqit#n_j?4Z%FdQz7+OI+HGS*jUYp1UoUuCSX@?Ky-
zb~%R`<IScu#5_qK?r={Qcr=YWznAeRo9Y>Zz~&AV(>CR$Ts2&l!1a8=lJdH2xvZay
z)C>PEG|4ximGJKk`tRb{--FPSKjN0Awt;W@uTL+I#bd@_PtW-~m}7yF`3}yT;|r||
z51V<VbeT^~&jov=OaXcqxS-2p<<XtxLB=rEGU7h80yVub&$o|KuTH6<cu12I+Z7q1
z$HiTqFOqR3;VIpJz2z{k{)NiV|CX`R*RD9<4P|LK{xO8ZL@At9{z=LMcR0shlRRHQ
z+u&3`e?~tC`uWlDJ>|=ziFlCSSqRe7?*(y{+gVUK=ywnNH6r-Z{azp9NMx3?{z1!`
zf?RkFT+0>li7Li@gE3V9J=7kk#n!dz-j2sDhq7*|#*)9!UBusdywTrhKW=qB`)FA9
z9KOjsGVaPeOPw=$Zyy1-(6-1y!+=(z_Kc3t^4yc|ia}pT%Fx%2tc=Gk?Z_r#;rQk<
zXHrk&p1VA2TK{#yDnhpr|7m`gzuz!V9)l<1@I*}b1fD2EBj@(-D#ii@ox_iHmUHgt
zE@MgmE`d?ng;t=yI^``ASyIFI@SDwDp0_YRqQ^8ZV=V}5#**w4S{A_<#*)!p=vT`=
zH@l1Rs7dAf1X)B|S^M~ggCd9OxkCP<@1^uzfph8TE@ZJX)_hCjb5dBPJmavrPi$vl
zJP2VnL%CCF3p%3w>%clu7nPZ3F^rZff1(^%e;E1o^_XQq-<n^2<!hOCD5U?8W(KXb
zm)~OLzZ|n(x1Ii&<{6Ru!pp`nXa~6<?RwWo?Y<y<SRNIAs+0?HSI=1M(t1w#c7w<-
z+Q@DWtjq%{eUaR=DxEEIzmmV@o>J+x2KP%;x+M1`e>0DnC6t4nGv_JG{B%rZyTUSS
zyLk5w-u+!ntu68H<J6P8)RXq!OT7|huAt0EsJAIBlkMf*HN3krruv6@S61m^xzm4k
zi2E?`$enhwecb<z`)$6J`37~~OJDMB7kv!#?f~!poOf!Ml~J*DN$%4BPRhJMJ)_&o
zyiA$5(U*Lyi={_Zua#*9_ZP=P`FTquKchKQ=V7~@AAP$u{3iSmd=(j6U8XZC^TqKp
z>h1|;I-)Xnjh6`?oKR+7ROYK;nJ%#xCYH%WWd_FE@xC;n9hh9p!*7qbb5faxsLVrE
z?QEXVP9iGvXjMBC%N&M>kpC5WhAu-L@L!R>I^i37>$b3u#u&P!8i&uGqMaX3Y^SVc
z^SzfNf2n^`J3l@}J9{UzBRX8{8Rf+mTV~97=hU3q8q@Q7Qk##QqRr6>ZE8JRkIkZD
z{zIo2=hsis)-NY-OX%&CZT)Mc_YYO(uu*kQ7!P9{f7dZJ=UqNwj<1i}c&#$Wer&9b
zs64WJ{9P5EME+<V`TMAi<Kt}@@e}bXa7=u6!u+p`+DOg_ZJ27>cwh9bKKcetN#Fk4
z;m>zR-<ra2{z~3mehM6?XM{G?7)^$>H22R>K}#2$qMh92?R@Z5?JS}l##52Y1IXaa
zbm)H!4zbU~&J67gL)|EUr$wF@RglJFOYba~(`SlpFjl9mpNq6L&U;#ChxTH72&1;0
ztNI?}&n3|qCgUOOHu1;IM0AgZ_cx-yZR{B>dsc<>VLW?*_$Nv=#{CMP`9aLrW&R{A
zGv)(S>3gxIDtIu|u+n4aJG7{MJ<+!vtHC2afVzb_KYp^mb(Pr77cI<rHSPW>{mTjV
zhrk~!Z}+|KdA|6GMUlbyY|cmVDUTLH+4h$q+$tIO)zp|jR3I#}p~c@0Oxo{z8Cz=#
zwpJas7MHYX;{)M)W9wm0eZui=LlJXOBZm5CWyk#yZG+tKEz6GiBV93ka%|eJSP;XO
zjTtw5brJK1AIf+xHgdrS!oJkqR_JF=v`Z@eVV^ko%iaw!zv3@TTteQdPmRBubY5R&
z3^k0wWDH!@W3Z2u56b+!c{TQIM=|onH-z*4!HBNn{;2rGGEeRk_~;4WGQ<}C7t=b#
z_%Orqp{|9-@nM9nv4;<>4Bv|#<{T}LF7|vigiMvcHNAW|#JkiHU()@tsd+#@|In}+
z0{AFuQ@^{}uzsz5wXh%k?q3Y;ySYEE9k2U;(#~$iR=|(>zX20t(0<VWg|@`j6dJ<s
z>p=G6OV(#K4nG>s4}1iVPZDpL5H}LuWbQ}JKa1q-r@}eVZI!B?`@(j0*;z{Yk48QN
z@&#Eoy8Q_9DtdnO$e{M2XJ(;^QIUPf^6yvlQqSnb?`dcSTTa(+5&ESaO&8qdS<8gz
zd9{=s#aF_wl{Pgzr-$-a;F#EU7qqt+U!wTQ+qBG0Kv#mh25jwoDx}{#X;bqLeT=se
zSTnOh+88aTHH{;$jYH6?$N=Q0;7#M`%OQ?T?Q2W|>mKZO>g2bC_etmExA39`FHVIQ
zxfr|VIT@So<AJJq*k1Mg<M7$T!Papx;LpEPSw-q6e}^yG;;U8Mdwy3K-OiPKu`oIW
zZ?1X~IFAgf9`4fDcJ6xapwHw>;qxl)@~tPjZ|4qAtK^}<(N%}Sc6xY*=hb%ZQa1T=
zcwZIWd!qaH=$^!%mU642dk^>Rzb}OC;_I$@C2CjVH_-2P?z&y#IJ#bR?}_f)xoiCF
zpON$aX{s-=N8!`_Y0RrD{vm!Pe@jdhnKo*G3tM6Xwa8!M0223bl0Gqk@<HMN2c07u
z4mwBi*NGvD3=N93DKb`M++@5oQHD}S;1n7eo4cP?&DTql%-6ZV3XG7Hz6-4n;j<^9
zTX|pP@2(@|vA>7pdpY`B==F!8jFfm&r4IT99xBsj*hWb6p$wDuBOcH)P1+CtCMH9F
z(td?UoMYgOxJ5$j6N$|*K4Kd=%!bM1Gp|H4;*Z3c;Mj1pPk48Y>nw>iIqvAL#i|E6
zhM#|)#CnM**Ycj{Hv?yd=KBZ#MaL=p_g2-vFf1o{nL}CO`3gN~ywHZ=Df|}VNpMs7
zR-Eun@KpIWG~t`ztn$r3mQ=SX{a3zqP537L>u=ya#QFbwb973YehFFBfGny<7IE1x
zW7`~!<WPmrj=(ou5*yO=E_}q5X$0rI*E|OA>ew7SZo{V%XJd`Sa$becUW3nwVG5sB
z)+;hO>Pj8vn0Zio9YJEYuaq@UyEmcN#byTAPMLSmWGaarG2y$G<KR=~Qp*GS7dmcv
zeo)JC>QSF};NC4=7rw)Gk=T=_CmDy<LG*##(zXllCgp!^mw_iEw4aD=p@(ZalJw7W
zIw^R8M=SIv_G5x~`J}QQWef=^N1R#PmFN%sH};m$>7$gDwHo;*ZAkgKz&>W@R>#99
ziT!E0XwD3MEorM%qolr!y$Eik4``fs;E;Di(Yv9V@pnSIQm%{nI5R3o9sSN|9e*b@
zuiI-FuPd~ELZ49?L-mif)un<lm<*W%fe9T`fvGEc2OMMXiWA<A;bY>ul3tr(ZYr@*
z86$Gjj)ypqzGZI5>R03Q57gD|#KLy;b0T~edwA0Jeh*L8!Be%s!)3o(IOr_v-!=4F
znR#g>&R5Tz6Fd3AX};)FO^3oW;A|B8I8ztJ-CLshjJ`=7_2oDD4($a`5ZjRV%#VS8
zU>w$MXK6c(Bj)nxGQM-QG$`Rip39>eA3PT$d^ksF>$7>EdZ90rn;H7lz^m=JIn8`K
z#aiCC80V#o^R0}N%l<a9qg)u(V}14HvC4XleYh}sKlEj6`4Vw;_zj!KY!rVqjB6C}
z&(z)X>67@i=)0Rt*5$%AOZ$E2=ye3>b4(YcemAJ3zY47OgY<EXHnX9xUtQn1;#*dW
z11^LQtJ-zm_btnKP~Z)5=ik@ipIqi8%}Xsc@XsXmHB5qUzUgP~@|^l9@bO+`%uuv8
zWBwT5mi}ZNBeLoB_@#e`IKFo`b9a<6up%#V_Vr*5ws!dW8pc#r&RAQCqhp8fg--aU
zVd5^&sb3B%^8sL(;42RazM%s{;M{ncZ-ZBvPjd=zFop^oC$#@0?elGH{5+=)4XUfe
zSASc@SD$=c)_4W_sfB)OpdT)1<Df0NLU;xHZ6dD}p_@h-19)?Pm>k#f@;APr$krSA
zF7vO~c_z;BQE+bPH8ag4>KpU@R1(}((U0gia}MK0e^th-^$;{7aWu_?+fS}nlzIq+
z>U!09()_C1#7{*IL^PeXuYj%?vzFgyO~!ktz}-Z@4qMGWy5S%^72@ys$@n{oZr}ec
zYeeMD1RUt~pVJx3L^`KD{-@BSww(nR!FLvn$r;_&v`BU>k7U=RZA5ac>f1zIRpdy8
zuQmNmW|L2pL0iGYgW%!Y5gxuX2_CjinA_LG!)m4MhoPrQ>KG48+f_1Sk}{ev;46C@
za_K*~9>Vsep0SO0p+7&)`^a(O{rp+b<RooX_ow-O?&Rh496iYRzr8`?Q<nGlr<kKl
zqB)wRFHPs7YpTAzkvTFA=%$LFgq9|?r6$N8^gu|r<w@pC<We;+YdVZ*sOsB9_}&m4
z|6j4`Cb1c`OjsMvkzx9(2Yp$58ULO85PDDS%`R-ERosin^d9a*Y5ZvU8@s9pd9(d+
zLB{}+)ak<3SS4-9H)Q7a*P?HfgHF{deGl|{_*~Y`4I_M(b#$!<#6Cy9W1k@hqS$t{
z20nz|c4Y2Y184nv^fQOc+J~&zpw;@pqQ2x*Xx%SuGKWTFFX}jPb(_bl+I+35P3ly5
zOX^qJG}O@8dVW{*tk>|-2|6bPnPW)YasvE%4gXkGUq`C?qK@v1yU4`e2>w&rMb$J_
zk;`TJClN~U=SV;JHsS+r2X=WU?T7CpABB39$%-$oeZ~{Y^rRmJFO~O2v4^DHa#`#5
zmj4+<zeP4%wVityeH-PEVPBvtkdp$}n<BW5R^SS(Brslpy}XM1XSnxpe^lUQ{CeJ|
zl52tuscp1jff@c~ECRF04sDN+Un8`TI93kF!1t5p>^EVYOlWFs4A5xHQ>Pfigd8l*
zBUgqzqMtt&K97xmqMtCqcS1g8li)7Fl{d)w%7!$5Zu8@ote1@aZ9i^FnV#kSyFSB3
zzDiSg7h1Z`GFF873FB)w^_Hyjof3{od=A!x!aS8Y>sR#UN-VnaF7Y`1Ofsi>JlId<
zed)1)W6AeQaF_AiKs%ekt>l-<c;xS9cuoGk0eTUBJ2!TUwyR*Q#?yM*%bQB$qYD~v
z`>svvb_8eDYfII%_s6yczE9cKBx9EGYPc-y4_V8wKC9_T-iI(2;R)h{jN5%-Xu`J$
ze(QDmJO%ukW@;mv5txN$Du08IH!^3y)h09uj?<06D|B`OO~LDp@SxCJf;p4eRwm)6
z>v=C@J(IQb$@+0(Uha{5YkaXaoo}4oRQcNgfArOcKTQ4*d9iWwP~%?Chy{DFxh?PK
z#P0cKB%=H~(bc*vd9-oLCxSg;o8P40`YgOlebwY0Ho|&FSPy?T7rUu0>OU;YJ7hwg
zCGQPcSF2U~+)_?tMw?yd?UQvjw=}0M*c<n|lxnh*tec^m7L%Jv4(|xEd&Fqjp9XI7
zFY%oX>X_t=CCD9P-HmZ{=i}t>q<mlE!u1Kitw9Z28B?X5)}U>u{N`A*Dp~G&v$c_L
zHtz&}`uEkPHGZa^cslyg0S*Uv9N;tR!|_NNTX}m(U}T)$9`o6P(*DAs0{)KpsP$RF
zbL<Ckf2Z=Z`K+>PqPy^qtUuN;kNLDpiyYj^bLL2a7?;;{Xs{d`8Z37rFWaxm_Q%|g
zOJeT&x3n7B{zdNkYg>s4q(w$bSt(QbF5mL671F{h(x$YZIaWx!!^mFpZFRrT6o3so
zO!99Z2IuE9@5|MGds(p0?o|8iq+<Ls2lI$$wReEeJ@!icF)!F}7ySM93U9xCp1;p_
zy?ts>#x63i&axZ*5t%3Qs7J<dzBev7@2kRj-vpfZf%CqGIC%I1b7BO2`9782WcpTL
z9Jz8kGPs?7XL4m&Q=P?C%T>oUMUA+nrmc1Z&rMvcxw@q@`@!)*{tjiWt%ENXCV?$C
zAh^zdPQmlJUeX$&CBL|)4%{3r5c~W0Tk`*+N=}A+>{-6#8?JIo7tR#?+46VH>$3S)
z3p|+~;EAjAfpbLKk#giOkL0ga7JuJNom*Df0!N+9KlD(JL%%$?%6vRPp73h&jz`zE
z(D%Qp^tN8ZTCBdy_Z{RL-jH_Jk!635s_i&CybeY8%HP%ZoqT&J`hF+(wbAoCxvMvD
zRk!te&&^BOPw?gtp31$td|UKQ-W^&p4tsT(#hv5te@%PU-(K&zxLDPKAl<+8Etlbj
z?<)0Ph}yoNzORytzt>gXMYz1G3a1Nrmb`oBr!S~U`k6~>G>ukhE^|e}`Ybft@;+=4
zXg@65*sseUF<9I8N6ga{d6m%3HHDJ-v4WB^#!QhL^?iO}iZAOFLYw9%`Idnn41BW*
zWi(${(9{C-5N$f}p#z^e@R<XjIq;bSUpnxm1HU=&n*)Cu7gXfW9L1XCsL<7&ac|R(
za^XR@bVakg8-SlO$bky2<v&=!{#Lon-<a9_Q>+EfRtJPmyOfvgVta=%TkSJ%(HlOl
zs8Rkm&36`%P3l2(<v{-we>AhQ#tPdNd3`2)<f#0g6gtAbgLj90e|}AM-{z`<Lj666
zetMd<;LDn0>I&9_FEf`H-~|;Mn&QQDU!CB{^hcyD@~m0pTFXz2lFhqHU0v_2f_kS?
zA$$u8if?U|HD;-sA@{OUUfMTm$yb&Ba#EJDf6L4+MlKuK+bz4nA8Dxd*XGxgdr3d^
zYdbO22RttQUaI)U`i47T+?%=EAdieZ_0Pt_cD`t4rEcc_ux^79td;r#cjhCpbb}SF
z&3`eO*6^1%+=~nq-dE;^m>#F#-2v5<Z_e+4o>J^TsZmc6>s^z%Qsh<R8j&4ZznH;Z
z^%u21bhy`{j6>P{hfHKvd$U`b-{0~|vY&qTnRyk$_O}si8^&SNaFH{q;X00t75&H<
zrz&sO;h(f`K^OG599I(iS#yEyJ(cf?SwjcPO2+Q4A6c8}j#-({#DHn;TA6nl4{~&?
z`575cFjAo-^Z+_3VBEn-a<=H{kgh8A7~{w$<$o?8Q|pV$ySE|deNJR9>qzU|;kVz|
z^55T$U1-BA5}!uycG+qV^rv;Bt<*}H(@-9(m1FYwNL<Tf>a3SKMd}o*>J%rdb2O}z
z&UzotKOUp+sejR8emB<O`MsG>gE!j22Af5nUCdjg1JtUqKL0$dPY%ImXr$L2e&3BP
zb;?M^yc?1ATO4@VEv;&{xo1v~r$uLJS@5nE*e&tIYD0Aw=g+!A`pL{xS;O!RWW#=R
z!&=k8UOZYTUPKwuGuSLyfx$4qt5O$Y=V)Cdc&Nq3${#9ZD{=>V>DRL7xfNEWjfzf_
z{_(N1=pm68&{)k(jZ392Ae~gVX^DROZ)DyCIhA>m^>F6N+!687o@7Y>&ofWZ(FydQ
zQ6Zf@Wt>3&VsDs(5siL7nRQIHM|cQ&$!4BRSPcgJ)IpAqrLM>?G}cPHHgx0|T)->#
zu35Jtr13|?{+kVTMP_FRgV4CpqR^($HvBkC_jw157LR1c?5O^O(tj|rn6)VEH4DC<
zMISR4A3cDL)!)y%7;+$u?#BMA>xCD6ax?bYDfWiJgV-JW?K<oq`tdKH>W6#@e^MsX
zlCY#5X`{Nnx-fM@xm3ev;GssYsa(2`evt#?<<#DmrwvQ^(VB+*{XTX=EN&R-S;e6P
zgND2Q&JPSByNBR0;Yr~w^WP)<{$mw>{_#Zo2wnv43g4&VV*h+N=?2CYWJ=N<zNf#d
zp4bn3I9e{R>8ke<BD=^d33J5%Nu~RlkIb9nLPJ|apRC3|ysLK0)t{fze|T40|IV0q
zuhHOdaR<(5-(JRVAE>=|s9cztdAX3iRH^sn`&AY>O@0k@O@2_i0Xy$sC2ysirk<jX
z?+!n=HIy5<w0UJTuFhmAzh{ig?@TYW$y^Hk$k;0KC-e0<w1f=*S{$D_l)>ip(fren
z(4MBB3r@sOHT}rA&1uk2ZA3qxU9RPwz}N$RjEwjp@z{2r!@k*H0B+GQS<x@j)@Jlo
zk#>xXsu4LUICV=iROV}iw4TQS6B&Ew2QoLt(wXlh)@1HpVS%F$=C6tOYh1MXBSUTI
z<~H#a{BNdb_^b2n2}@u%KfGKu!!KHgt^+psR(uh2P6($HV{J-s5)WlE@K|Qg3Oxql
z4f!UtU-@qSMD%cg+{WLT_-$7~Wtvp~mbkwqGZh=S!Mk^Rn}^JryS57&6d2J*Yf>@w
z7owMh9?6^g@JwW^F}mTy`R*0#x{&$ih82pvmEz+uzjLJAQ^3_{PYw3cmWR)=PHc7B
zfWGFW;SKateW|GTHW6gHt-%K`<Q)`>m2XMq`<3th`3-*Ng+ggd+`BjPo5GfmH?f;^
z`!o8GgYfgberWw6f!+LJLG`x!PiKCqR<rkV4|^}M;X=NQcz#56z`H5rkns1$P(SF{
z(!5zYaK$>1md%svr*jgazt94W)CMChM!@`{XRs}_O#KM+f#0O%bUi++^1V?1?8qXQ
zX*1G4760SDQ1>{s&_%h>ochZZ#+Xi-7wMEwB(ipmx6d$C5}FYIIn*oYlZsx*uS-<v
z75tl6sNYVZS4Op7`P1bZ<`6z?+h5~HqPJ6L9gjsYbQUWx%u`w9**^Br?z1g{#Y-^f
zOW8xa*GbC!gL`9wu4}H=b?CX6cY)~KQ@~WxFfCj@sjid$GQSpmH`Pby^<p>ebAZE<
z{((vGiqF+Lt^<Q{o8kw^Hf#a|e5DQ_J9%t#Cyp(^$IC5!<Kqg>|AXUtb=fJ#6~s>%
zmyAiq_J_vwe)cLc9`mtKPE>3L!D0R<%Pn)?vXgz7pDeSS7I=a=(DuVE@htI=Jwm_O
zhE4fF=s{@rRCHT4cbN|)veLiQuh2C3&x(yDbY8Ko^7qi@MEm0b;D}%_?*M*i-<id}
zR`{-@`A_}Ai2LW~kA(Y4v5`F8uI^v$$FAwmFNj<0sUBfJHT|o*B=?7Mt10)6a4yt-
z{QLe)tMHe9neHQ!2f%$9x_lb-?jDm3)1b?#J~n~a?$`yEI-unQ&tju9AA6y<r=Yiy
z{6T?BA+L5!#}<_R!tb<W!DZo?)iar|#AFR(by2r(BLkZ(rwKUI*g%vI@dT`~5LPQr
zowdtHWzAk_+iV@PD?7*R%K6Z!1^-Qh|4tMB3lesU{p?e{r|f2twSN@7{$W16^px~E
zfe+co4h#-3Il$onqXUeu%a6Mw+I{sz8nrF(F5_WbS{BS7rxW(dGY9m;H*;b=bOAaj
ztdps#!+VGK=4<rRpkrWL$!p)@e%|cY>lja*u_YmL<B2wGMD)+VU(XWVBYqOLjre4t
zPFapjhi_7Su^2gT$bD(6(`uR9olQ+qHIaWYTWGYx3(W0>6&}d!31xiCikRfgjkv>|
zPRpuTjpjvYKh@Hm4f)Qi(ia!DA}>$Y7i-7$g;RrWBMz8)Z>(M5Ni_gVjlfnjTl$A4
zy5TF@4E+IUHV6If!OzHL2IHE4(eI<wMecVxsljD6k=#ExCil;aSL+_+{0X|}8T^`q
z`HuJ>qkDWkxA&iSlJ3!ZG*N)Ji2KgMCfBkA-iPmj`L4`v)elcSV;IQ2`303aqa0st
z_-h2_%&T!rV76=E59|@j7{IzF)R*Gtwy!gj=qF@>adg9`iwwV%zdj~>d>6cgFXqF;
z@Npz#M0VhdSrxg8Z4&CtYk?csLiuHDoq3Xc`^Ru>B4f?JTn10KEAzm4+~*FMzjV3d
zYi~jBMe<1O668=8-PTs|Nlx-Zz7e;EUcrZ7|JbO+73>=P>`UX;NRyw=AIFB7;*T_Y
z{s&qP%ComWnNlPDt?cQTicfk~%<6B#=lD3^pg(&WGR{&@t!ctePeM=Ad6$5$>o^y~
z;f}nPSi6CZV=H(|$KnHWV;Z;EwZYzCMbdY;GY)HnKHz!eqKu(^O(qc+duXlPot9uk
z_Xn)b^k8I^{@h{wRP3gF5_^gFtMMn;B59?P-(6EI7oL&wtJ0D)U$E^KwZG-><NZTZ
zu+Nd5y&})o#4T*heM2+ER?YQ;J8f@b1A3922_AFU0(IDsUQE3j+L!V-e#jR6?u7=w
zwl(nS<DSe*#MH1q`Ig0B*)lXk_@}84K0*ge+w=Mtej?sFlvaDhH$q+zzfd_TFZya|
z2KYTZnC_a1{gy_r4zIFh?YB!mZ@26w@X2^Z{-fKlf7@I07l*pbE#1>EwlzE`cg46y
z%tB06{E_XpI#BU9%%3B}3~vv9ZPv!7Kl~HcQ&=m2W}D16LsP?77~-p#X`!>uY|Gvi
zHRjJ&$k`^n8OeVa9b1tXtCf})rkW(q`QNV4_W_}AW4_wUSf6oA(D~a}s0)b6iSGn|
zK2V9vh4DZ4WLx7Q+Mx~20~g8J9i7SyR;U+Z{u-f^{CP3$|7zcYc$YDER?)ojyh=P}
zT>jL@vdrB;#r7mtS%SCmk>`v;r`qn6@oL*s+rz@!YGeNQ6K&7ewTDBQ^w|*RYJ1oL
zrxLFaoI6G!{9u_+bz-w%M`?Wiea`$6`T?G)$O<jrK3!=`;y~c<z{z%6<`Waje4jGJ
zffmQkj~Vm+q8&U(zKG}nFN&3UW42Z1I&5XJ0dG99?UVHAyT<3@1U(9^oCNpVTzCh$
zwPS*ACRU=y^_Hr(cxRq|o|3)hVz=a<KQC?m4fV7QS*^=<w2kR9Xd<-#y{62MRGYw`
z`p9zP0P#fa(G59~;pp91=8{;O@Hul`BYY0clqTpN9aGCMi%rx$TJKi-7$=R<uHYSA
zEMpbF2l*gtUG&3P=1a_YA2LA4XU#`NW;^sReg}3AItISD8(p$m+ki^_sU6vWV&9>w
z4rba5z=f`gt7*)?Wo{52Xe~iAk!^HxyiV4m^7~!OJZHI%c>xP`h_n6Tys^Kb31uEU
zPrVVDJ)|O;9m)HNvRmY~TY7F9@djVycNRIAc@J_Kxi7Lw^i#z?#%JFW>J9Wkt$Iq^
z#@sbMQ8%+ufwv@nc(PgKx-IgCc1D`et;qCzaYY&%dL(}xvWV}ZBiw<ZX{p9XROWZ0
z3xrSR_t&H-vjO`$idji4OvVp=7>0w4SS<1_^8fIWn72{*Uua_h*`R4b+duFT_JhPi
z$L+B5iE{|Qd}+C=v@h{6bB1oSdTwTq`;p`I^MA|S>^zY#G*5JQp5RxReaqD{wbqtC
zl8nckwSu!YRMLEO1+dR2q~jutyglYk$dNw+$N5`B+sGZ>KFtQV=D!fbiLF?J9*Udg
z6J>yg>pkOeRb*P~bIY>k>66I))s(Hs>vt`ml)j+nzZkO%unEBL{$hp3s_cSsdjR{O
z$sf%hSq^Qq_n051Uu+GdLB$q+vS0(ZWn&j$mNm)yB}WRj`OyNC=0TUt`xVG1Xh-yC
z%bO(5LVWnI)LP+BbS7=i=eycJ)T(MGU9+1pKBiO-|LQMg9>CT8li<n{TuEQ!{;`}V
zWWHJWcK#ZX2aI8j8HntsT)pVF=d?Z5k|4eYobK><`oYmJDBs`Ws(uaETMOY_Z;$4D
zZgf8<x}z60E&Nq<e`|C<FZ$jc-7k#pv?Fo^dhZ7wU+fgo6VSY@ZwS5Xb&WCk*Rm{o
zlKgve>4~;?YMI2%SuBI5o>;2w52GRI-;T{i99|_`;b-g^^9SHf<|7)rj5GCE0XU%P
zA?6l;Tx=haDf(MO^lb{?ruZW*v($L}n>>BZ)6?PUf~%kfY?yn}!ZTv)nZ@N|yQ~%2
zk-49E#;-(1Cq2;*<{c}P<lA>eYn|qc=wJE{@$lR<bF>i3i&olhqwPqRXkO=A5gDq-
zb1UP~`aPH?>kZJ<8sY+Rv2(<hl6BD&?3~2XC=X<OkFMl{to(W0mpl}wRn5O45u5>z
z&cK#F!+84mPmSqnuc01M_Vn1kOIe#hm$e~FN9>v1`|KGj_t~=^As#R{ORma@-Kw6t
zF@b!o@%P$w-d^T&uWfL}!GDs=R3nnR!`xdb_GZ!N2r+Rh4=#B2n|Y=kz9&l#?K<?~
z(1%0cM&=QHKAZH7%<K(*VCu7=hRPcZ^Z78p#reiJ<*XXcK=by|_dfcSSYuXTmbFtS
z6<FlFq@}Nhxaj;kEB_|eAC17zx2ZJz*+hO#b`$iNIg|29-$!2f`FhFIAU;id4sAQM
zZA7_8VHxGaYog<P{BGJ0WDKeyt6K9f7P8G&kZ$Ci(5U$vt*b4Gi&w+JxpZmP46^yz
zO7;S0C8jNKkqald^)n-U?^jJ(AK&*$i6hq2M_oz%SJ;k}H6PbBrX+^!G>~UxVxL&R
z&)iB`Z>E%0-FAcWrTozE2l2;h#Rm7W3w=2!uZ!Fwe901Xq5IV^Kf+!N$%RT_Qvf5^
z0y{cy0G+&_`QC4v-hP`kL)!?zJNS>OeJxk{&D7t#t#@Isk@OaD&4ssa1b@V>etWN@
zg009K?DI2$FDGLf1<o|EjQHgSpYP1|JZs4UH5)qznNh#REuE&270QSayDOJhV%xSG
zF|VC7hL*ZZw>P`HYnSqTHtU_!+}+b8Ke5SO`n}W1`)zegpPlaRHapzX#cy(VC#77@
z9lnnD*QMRf4RYp1Cv~#!z<)2Y%jI@=cTIZXFA8_i$5zR^GRlKn7uNb)=yxkLn-+f@
z7|C@b_X*yRu`W3>xCJ>xY^{EPvH1SnI=^ME@Op5Y_@5!{-X`)<H#(ej1>Y_Ljx2D{
z{~&lk{_L*J0%x1Md#bDzHQ{ptBk*rF_*TRERaX<as2vNR-*D%)UbB~PTYxbg!I+L<
z<eb1i1Y@$#(RpO}OUxsDzu#dVk+=JykA05JH*@JQm*Y8R*mEyJU(ko~G&C`j_@Tp`
z+st{hLLQL2H3OQM4o$Q|6KQCo#fKiSr^(|JUxzvEaI)h2%<0J2Lg!6>4*W2$oE_D7
zEpa2iiL#b|cdd_~KibkA>w};D1xLTw$6BV!U;Buxk<wOWy|TU}_FSfwwq}RxMbL2C
z$zh9~p0J#p+9P=uUGr{7W`9@cJ8R6lJq<mF=UxJ{!#Et^Mvw1zfZG9XhjF1(_c@Hs
zVQfYw%yV&K{yt+G^7Y9qaG_&PlX2BE4~@`h-DvRMIv@REWk~pRh$T9w$yjrniw)iW
z>RRY!Y9eh|Dkl2b?fY^c?Tr+TShqV;+r--Bt=>mvjiAn2T-*>tCxDl?wn}`@MhD55
z7axB-7W`+*KlD^z?9iddV_hS?i-w*%*eP{@Bdz`{<zF>&N9@q=9*+$z_~s(x`ltC8
z?E|TAl(xCVPneeu-apkpG;gzRXXu~)ZPAeN#0l-tALXVZ|LXc_qt6fP>wd=Cc(=e?
znTxO-JZ;I^amzMYyU1;RHt7#Ah8|f5<($s}o%izA+i7PzIfFjAp8=Q5DRW7^)JKVv
zkW&XwJ<xJzydT*zlKPwY0P>a`N_2_g?+1Uj&EMRUVz09n2%KlC%$0Ggm$k+WeZ!Y&
zWH@-siToZJ6+XE=Vb$_Ie>HIo-eu*PI)ZCt8Eap}G(YqiWuucrJ=#bdM2%Xe-{D|K
zWqxG{KO=)=Zh9;usmMX9PxCIl@JL}1=d;SbmQn9^=vVZj<&Qp_@Hc0UtKR%Ek-fxX
zA4|lD<!0r~Q}>Cp@E^$oits`H!d6H5)6g~3GVf2Mg+7?8QjzeVtm9JFFjn5aIX_ix
zMbE58rd)KX^1mbVfAy}jcvqj!8>)jgZUV12A!Ca|6Gj{uUM}$62Jfe(9UW7y?_=(0
zW9mizT|ygk`8F@@)WJKZ*r?Fk(Z`9M>70N*J*Rou`;5N{?eM*qy0kG)d%8}|E~!Jg
z`n1rDhPwlOgM5>`Oz=38{~LG{n@wVT@;7nw5z0$jy@94FsehIg^~1BKL;5364*C~Z
ziKkO1M-0r{2CWEf!Q<n&1P4t{A{f#1#oVGtE<&ad7Yb(O??}*Qom%|r+hfexUKzjB
z;O}u7g`Y#%!+yXA-=&>syna%7)1xwdGB&l8HCftixkzZD5g0WOgFD)8RC}eJ5Z@Jk
zs_)Zv_}22aqQW*ASu3>pNo1JNOe69$B|atm(IEFT$r1DRnYBuVFiHMj72bu{<``D~
z{r<zi#Wy{#YH{7Jn9RMN6Q21d_~Y+(#y(HW3jR)qW65!!YmMW6PK5hPoe*~EAN)NG
z&NtES32<yLZ+IxAp<G&MWg;$8yU6EZzTq_s9tNMH(}_(Z>m72m&^zK!ZN&yaZbKuV
zXHUKgZ1Wb@l+;=SdvBAw{{6Rwa&cY>`Rj{L5Z#cu`na{2Jw&1dgcjWOU+x=vbfd`o
zkcS4o(wAvgTXeg>Cocv%fp;up(SFYRxklN{uW`=p^c##w9rIK4X?Wz#Y-o4aU$Rkf
z$9xjkDilSolXo*>{wuaSaAw{T59zLhToC5Zyps3Kp~D<vi=hMXAHK-k!u!Jsa*S?M
zX=wEXzQ-<VhS!_5{As2vJkc`ESDCHIP%X2yj!}z~;ha(yI-M#yhwsRJXb{{prkrXy
zMywn;2F>nwJMK_sIi}zN^pNoQRG|T>*BA19IRE4GerAQ|qOwu@nvSGig@)@iA36z-
zcG**71bc}64zLDQ64;@UPVB)w(6yG2$f_*wZp?J5j%vCD9$*gpfF>DBds_5){!=>N
z6&gvFupjW%h2EaGWWR5PrYEb5U$sfszg_TF8E;)5WA2}Pyz^gYyyIh)`a=8A{a2v#
z>uFo_*EsBFl`?xa+z+pAL3YElV|DfXgt~JK9{nyH?;JgMEwx&9RB$fvhIY-8f~-kA
zkY8LFc(h#D=CGH*OprgGdNj-5$f2{u&+{tzOKVg5OqQ*gS0vt|&WE3-n{%<*h+E}<
zj=zJ>E1|3MzmAc6=?kwkJLu2U_HKPgm+nKS_PV8e2ZWw99kN#A;KPM6fANv$rA7CG
zYmq6V-u_zP&RMD2z)00dd^_3Ka?c}o>N>-B_ema?*tj-rNMCuOZ{%^FHJubFWvtY1
zq)*x^OIu<q>$5~hrConi-kl{l<9#SEu(7sETki0U&6)SbI!=UTuGR98pLEdutXo+5
z55}lFM~U3X3@XNzw0G9<{wvt^?1vH9R>xFp=J%{C*2v$S?V-mD?0TIef}Jt9eBM{=
z%Vvz4ANvKKph;{h^bvY9Gaudquc^jvCHk!*>twu{Z!&Ip5?Bq#4ED)92KUI=<}+79
z-_mB?mS9#==M{;ZWvynb(0Nhk9EIa=d9h5{CdSmR1Sj;N=K;TKZwQNShwt+(@j*DR
zV{7Vtz?1Mo+WEU!JMXgKRC3?aC(=&gJ0b1py?vC?ZD|>u|J({6+oB)e;!fW8kI#kn
zM|By=YZKe8Wr@;uo6wusYs6h68||LE@}FPMctd*&`jhyL0j(N#Txpw2_ErcE#qOdX
zZHt*-S+3S%tAP{jG-#O^f|hZH&?ReCQ4FPGv$fp(u*`SN>|L(<k>_@e8p)KFYg<m*
z6xge6G=U>(L)(G+Z{U#j%+IdSv_qcdNb0@I`)Su8R=io;pRzu>M&fLB1Cgx)UaEAn
z$g&m7#Xo$&T(+Fp4)zJYh}IJah{wWj(3<!N$|R>8*r0Kd9TmEoZ<$x%gVzu{e>eA9
z@f|j1k^duZUu~25(lTIEhIygD&^SPST{q+-Xc8Xim6*m^ArC;4z1Xgn?DfDN>qYN0
zshzcc$Ok=XbE$^GAE!Cs&@`IUIV-6d=t^+X@~yzgERLZM=J}!npl9qXktb#Hj(2Re
z<!|O5*=31+PQ0A8PjI<F$rz#Ox-HoCdxbuuzen-?Mzk%!-Qk<gOOv^NF(&hVV@opD
zFKxO5&-UZ9a&McJSF!$<HfS4|kagGR+gFl{E;y|4Oa=b=jJNVGq}O~lD28Jbd#UnG
zV)8jFd@uTF4zP~%CC|Vsd4OkX-U8>;4S7WDDm7ombC%d~<Rz+a=7-3|2*=C#7%#St
z(7wa7`Co;I|7Fd0o+U9DnXg?kUvCX<fK1~GsoyK~ATV~t{8$7t?*)#z8je)rKjH6S
zq^p6Lr`SAN_5`z#D}oPQKkB<AwpV6a!8gAsG!u?Z<{|Zj?rT!qNqe%ct>xI?p_}2i
z)J@%*7R>*`-l-LPB$Q7f?LoI+kX)e1&gvMqvxcyf%)5wRGS8V?S7^Hp{=jA{mNK`j
zuofKst4+w7lB0Eux=Z9GIJ1P`%zqAfQFu`3(8kU&57ECKZ)jI)82?=3UB(^BQ#DO&
zYmu4I5~Qc5nFF$>k?c1wm%G+M%w>h|a+Y}^yfA!Mv$-N12Y#2VMK?Kh<Nm6hBG%dH
zYyUxf0nv>+6T!nn@FX^%<nZh@Z(fE>Q6uJ$!q~6O{iW#U%)hSi=szuM|DVxvUhDD`
za*^Sut@&3AmU%m4oB}UAgbqhH4K;K#|L9d6v&Kh3j%fT$r`$<&5aPw$B;)))^WCTq
zP9y&UTQu}-g8leS+75&twnC@iQS3_bC-DWaO<R8Bv#vCHYxrHa;cH)isjRPrcB^?A
zG$FKkFSJjb1zc*s*L)9hQfTGz6KN&?N$>*gVMECL{Xsn_cuzg)tF<X`|ETi1;7{lQ
ze@<b~<@(Gna2NBsg$6`7086)#@VHb{QTdCu^)_@M4=n$~nupQ3+K!I&Km7Z!uD{>>
zo~*MW!%Sq<@H3YAz;d-F<$L)rODvEzyr)IRw)?uzsno$2cN&S2S>9f;ZSfoS*p0|f
z{+78Ex>`frDyjWWi3irD^Q=eUztBdq7aA1(kp;IW*rcJI9NPEbnEAk`8}qH_RqS5c
z(Y|$w@$|wQ_;$f<GOydq<%crAEIb4a(|$OY6<Bp&uRb1&?Al5jy|m%$`Tis_Zrq>N
zezvqpy%WnyyywAX(SGW)(mUV-p?STYdxZJ@1h^z`(IH2n*vLE&Z>PSdd&WC2J4W~K
z4c9~R7m92O_NVSRDmEH)IEIs6!3X$feq}6S{EP3vT&1ro{_-R-453Xs73>#TC2@<z
zRWS{77wdg|hsHz>mfYcQC}KQYCyhxE?;`HAHJqOimi#4ZD{D&eB67o6IqQ7!_eI__
zXW%U7ofP9qst$a*Zb$juVmpRo3)m~7itIhx${C5B)GLYqnZMz@rIj(8r4UYNKdxme
zFq^-}hR{4Dyx>CzxxTJc5Za4>CpseH&ksSXjJx88jMc}E$(*VE6fe`poSlIlqnyO;
z9sHHCa!<0d3?GOt&-|=lwahLg&Do*O8%Dk(^R-^F4dTXPcNORleJJ19Kd8T%qsx`x
z$ow<LK_4fy|M0TVzFHL7SJ%mUW4)3!@+^D7GE<kQjj4gQ@6DR!iZz%vL(aoU1mT*I
z{Ps^=$E)`>#AS_0*1P6qGX-RBENJ7mdSs2NEp<7#nWC=AFH)YPyxSU-(PS$Ht+98q
z#_P^pCiy!7@}ZIb@jahi;f-)sLVk^`KLx(jm2wThM4XMbRkzc?x)J%1tW}X~AkRYQ
zGXKIa<85S?^IfT1rJelSRCaBRm%~nK>rbj&eu2tDgZ|F)F}>!5y}{a!PwdI-wt<tp
zwQx-+uGfV6WKGC!P(CsQ+9eJS9>6y-f9yF$%sUyyyjk<f|Gt2&=q=bOdYEuL`%O1x
zT9DI8_Nm8xza`=6wK%tQS8wW98w`9Q)^|mgN{mALc7g}u!T(-rVeLua7aO~>K4u;e
znhDxk?kOwtDUpw?H9W_=X5W|GVvRS0^()4-v;2?jkC!p2?gllK&hIFsZ7H{%@`^p%
zUoNEA*5J>jRJJb(jvGR}kM$+%y|gvfj>c2e*8S{PC#Od6rD6CEHn(0^RMDDZF3TKc
zi9KfJY_qA*LuQJ|;>sE!c#GBtX=7|ZzLW!pGM7F!ENh8jxs_iv!GC=gpDKG5wvw#L
zKEnE@e*XH|O^X%zRBwJyd-ok$*6V%pSIN8Yd_=#K{n`#|hQ@oIO50O|tnnXSZb*Ej
z?*v(Uo0qe<s%(<=>Q!7lT-&*lY5wNw;o8n+#3-K#tgBQ!4s6-0)OTZ7scX3C=VNW>
z8>MGEjV)Ui8H4NEuTox|wO(j|i#!IKwN>~P+l-5tF*ZK-zM5uZBe7=DWY>F5#khBg
zo$#hpFHJpi-MOH1>ZO4#4Qy#(O9NXP*wVn32DUV?rLozv_e-Bi%EK#mO^~Mj>9pTU
z`>nL!S~O^XB1{QyS~Xns^SU^g3~uBW`-A*!bXGxlMuD6+0e=t|TyXkyZ<ELi<YSvL
z%iGA<_JPL(!G4*moF()jwnK<3znL*Nk^4j}v0i!qEPj6y-w9f%=DFy63ZXfn0cq3u
z`q|CWr!91o@~Jl`o1ahHTU8Oc1U>oiQkgSIS@X*&{ONLfq+DpFFAF;%I~5o>TOfO=
zTo&6meKM|s6Xx&_;)*@7#I?njw#ciJb(E9W#*sUcCo6c6GX;h2{hye=tWO)^?<1A`
z-<VoHW#9{VhOq`E;k^p&SJS!XH_4mfoQQ7P(Q_haNJLkKcQn7e>pkr&`^L`}(eJi~
z?<(@1-%}&r5XyQzZ^%E9_r^WHh41HPgHiTU#{E8IVY7jpa@XI1PS0%`I+7^5Kgxn{
za_&Eu^=nnp57$a`OrbYunIim+F1T=Jev0T2)-zs|^?=uxvF>m^aWKkKU(TwN_=X<S
z2fiivC5AR<(>o<bG@KJ!m?__+y#0Z5nx%cARr49ab2S|5R@RT3EW>Nf>@T!kMQ)}u
z@bUI{3Jt`9Ecw1o^3MLix7y4n3o8G1^g~q+h0vMcMCeZAqg?JTf(w3Y&c|0<3JmDD
zjcMbaZ!7{&IVY~pHp&~~#LLgfe}H{7yt|Y*uv>aZF4Lx#at6~i$i4HyJu!^yraN(O
zy7ATD^1Wx8_(S<igNxz!>BL4ZvE$xl`Hv}&F_WX<wc6OfZ9a62j$?l({z0&aF=w~!
zs%ITd*5rtb^j(yrE!Ms~)>4Oaz}W;pw$c{s%4!kxMcgGor`MGx((EJPkTzEeyyy+a
z28^XuO#&Zq=758|pqtY9%Yt@nj+~uP?X;T%w&}p;nIqsHTGa5CH=vtBc=Njp*{gq8
zYpnwpnZ>GY+Y_}GwpH$MZ)&NL@__g8Md;d2VC~GG&z-%xf=hS(_3aDeUK2RYaSlr-
za)Lf(EQ%{w%5&EI0XcMkf(?@J1@|)cHr+peQ*M#qP46ut9$<dAKu(g(#j2)Ejm$;4
zTk;|pODp4}+;(skj_E4)kxDzxeP_$~q`!_O-z-2Y=%?R)oOpg+$)CdB&U*`LUDC_t
z>r~r1oAI@(Hup!h*3gU~SDfMLG0Hw|>C^l=eD4Igp_b@9c_nr-=&%hgJub#p!R6-*
zig|4lnucD^cKa@2KBt_)_eJJ^(&y#$g)MWKzF3#f4b6(${F;1=$+zsb-Qan4kTYgS
z-|nLS<3X%A+l!fZ$k`3!bY=bn_CVb4$bT<9lgE&Ar^(H;6Ug)E{AqhiAp5L|V|v)8
zf%w|{Y{L_~anHD|*xr#p9i3$aZIWBGN!GEHcV~Vc@9L1#HLO>uwfH6Tz{y-?DA^0F
z<42TJd-yHPUhJjbg)#qY+_zvarBh!72l1faElC{xu3m{vBe(kVS0Hz3Pui_+BlBCa
z(}GRd1e=Vww@GAzw2fTw_4y))!h9=%OW@1wDUkaFoN>QMx$835tMp<us*324#aPYA
z35n@tWo@0fmYi8UlK0eB!c0y1Ud8+Qy-V)*A8N?Pn(}k8i;{k~V|e%^>N`KjXLg4_
zbkHq*@AShzIlTkh@TRMG&1H;@y$j>&CXur|XB$+vMO;JU0605Df9ALIH|>OD<E&VG
zZg8S=#fA<XM;;GZ&DkhtY<T--xAfXF=A;NciCuUdZEpon)S17PHn!020CYR*{{wzK
z?;ZRm=3%SEcihsSoJ(1bYmj$m2`%)q)^tC<J32eKlRT9^$=Bk2h@+q&YxFlFFK*O0
z{tuyX<U6$Da89`ctziG|cc2vqI&z>F@Iw9+b~Q9*G=_F{%SVFyDt2->N5oFVM#eu)
z<;2(h>eupXmBck78u-RT?(p5W0rO1Yy)*wba~;8y&#69WkGe_5dS>6kSirc>lr?tW
zNe0~ue_n9F|FYE6gSUVSa3b-<#$JsNCHM$w1R2r{9(<i+cc5@WZr%{G-+U|_tJb@k
zj_2#K3*IsZ3g}B{5C2Z^!f)812OIl}>}8?9t#Woqz92CWA3xw%wz*sEaNl3jq#R%@
zE}0rU1l^7-TpZZQGojf&#eNre>Eq;Od)*pW8cyQe;3+jSNZ-V0hkyH!d9%PZPk84c
zJ+I;T=)Znoe9jdzk32ExQD_4?>1Ka+h3>*J^V^3aD}{c9cFgrv{3CgXxAT3QeAlsd
zjmNP4KxoRR-T=C77VBp=v?KOSk9nh%uiI*VU(TBGfr;2C`Okv$;HwfZo@!;@CU8I>
zn&vC{dcI$=i*_CuBnBvTSf?gumv(h7quCdo^R*WFCTA#$O_Rir6(3ssTCp3kA&ss6
z>G_Pv7k!SF#JM(u<IUKyn_3!GN$6Xi2bdeqBa<_SfUC~eXMSVjgYQ0fU`s!?Nr}AB
zB72X3mz<L43$&T+XZ{X2^ogE2(T6lcT9>%1`7$ud*}wv$35-c(>11%`1kQH!^t>#%
zIuX{?1X!`LLs)fOzOM@2es|z2TgKq!x0^J)zt-?>ap>Qn|4Cu4slZHb@F8G6mH#Ja
z!^C{fZ6hAUy+!gi`8{TAY{^?_OMpwK%GVQ~v8#N->bj}lo$MQSr>6MQx9DA&N9P+K
zhc{KVA6mjLF6p(fn9QGs!;j#=Ce(2F<8aW1&_d*&GQTB#UR+h(5DtyYlWZgn&$7@T
z5}1r<2DCk1{cQY_`JJZliE?e9O?d72<$BMrZR>p84)|kfi-ny~Y8(mn*Za_(*mC?f
z)itU?9ZhG|Fg{|?tMiWW2OR1V10aV2*lE{j3Fk)W6<qW-Wbttfd?8EoL`meZ<S63a
z3y*|<lXpw}pe^JN@Td6$xLCJB2c`v9$@3ku0y%fE4ILtLDE3KPNZ0gFS@>n25z#X~
zGxDi%L~LXfE4;#5o5ZN)_g<J|!L8O~GszW~-_m-|jGV+U?5PSr5!gj8D~T6+dz!Oh
zjxhSm=M0`Uci^#J$r+YhaBzrDqOG6R`}yZWc?_J4J@DTNeMx>WGKKti-ceub2yPmD
zbo(yyhM|egl#@DRWvM$>9{a4i4}md{+;2eti=SZb1DA6CFZ4GQ_ZHZ~yV36l*foK~
z>B#-9;$!HGd_V9$H=CKEtaXOhp1DP}iT_|2o?)22DzYvs{#WR0^`J92f9g2#v42B`
zLW>T0$_Bow=y)eC<L}|U*zTcy8u>34c+tL<fh;#S5EMK<NS!-MEq|{{OFrdols?=3
z3H~@IW?lV5qm;h}cxWeM$I{!LFiONcn-2F*=`d1i+BiIKy%l&C7{@oXV~;Hmcq*{C
z!xuK!8pM^JRoT>YlJ{GVnWjQMAuHDpk*gbhALaW&iCrKkUo9*^#@vQY9XGyu*7^DW
zP3$ig(5ApzOiLY$HuH8YYbVtgkcVGLO^K!3Wd43gp3p7>y7F#?9<6P=>LkaFwNPw>
zJ_9>^M<4v$DmlTx+X_8*+i{7J`F-%lOz?I3wp}$HUD`Jq&Mvu3HE||mmUxxGuD~CD
z#?B6TXON4WAs!RH3;#xcQ*J~2aBnkw>u}xj1$5PF#<eW}1GOw1ch|IV-1wNasx7rM
z95?pc3E#C3`f8y~=2qqu+T948-IY1zthgd{benB>x4n}w*)c_&q=y_zbv<Lc9(q4<
zzR8`4^kA>Hy`V{l-?MO_Ne7xdrEH%P$`8ZmJT}XZ4NX;X(?_o+R5NtBDDzi^=IZ&%
zY%W|=!6D=AbNhy~3%}0qYRA=WGKbJgkGuYB{Yw%a_TsAhYYpb@&s19bN(15VwmZK)
zdzSe0Zt1H%=(QX3!~EVt!nn&&4?zQ4`ms^CLf>E3j<x^)1!XPi^B&gi5CecdnXjIH
ze0AoihP`&dy_G(6`B8NA@Q2C&+p$I7+aGwz+8I-W`EQd$F?`mb5ocW|Uc{zMVh6TA
z%-!BuzJUF{dd*hH9XJoj%KRJ}7~anNEA2|(c09P9Ik}7eY5Tjh{Vj>%J)D0mD7G2F
zK>ji2JO<Am-w;Dz4anJ``13h@a5*=oyGzG=zUSNcwKhI8b<&x~bsgZ%ZIw2i-@KS!
z827;&?f>SR`tCf>yLU(Lp8sar{BsVgKqugn_(Crt|7h<v=m>dJB?~@X09TEkoV6$P
zX8vY{x|-jnT1Spgeuc`eOTxoftE}O8t?+-_PzyX%g71<2n(yDw9o}Y4t?v5a9KH(k
z4a`T%(684jbP)0yax|_MK%+Ay$7)?Nu<}b)dYugoTnQe3WR!+x_)WzbYMRIy^M7RR
zI(RoR^fk;!r>vQn=O~$1E#Jm@L&s;v<lPBlTUAhpcQurdc_s7fvYs2(l`<8%DDfaI
z6J32qA$$f7=HXL6VG?`rT9J2p++yeE-x3ssmW7T(nFKu!uex(d+`CiL^1pLlYlK^^
zTNx+&?3=(@IHvpb8qMmV^5CM(dVd;Y>p%`)CTE!<=la|ZBPMcOWD@P<mMkhX<vR*l
zEr(8!H^I9_-Y{=#Wbe0OsJqNgi38MSyO4LZb*q+n14G1v{66!GGRH~ixJOM!$N9HO
zTi9=JV_t0LJBzRSBa_$!@!}cL_^*+80dvK^pu^0Skzri3qH+DhiZBidAHh@b-Ak4^
zhcoBOiF-1+LRN4FA3Y#^0e*X=AI*0IFWN$PLf7WS+TO=@^S4U;W8LMz(MtRZIE;+f
zN?+kTV7srooZpNlhP`b!dTF-bWXz7>co(=hUSOY0``w&F1`jf(R^~wK#kyWu!x302
zyeji3=S!@+{E@Vr%e!qib3U6npB?oD{TRo|Yn|;A3qkg+l=eM&j+raq7s2f<jFb2k
zvc4_PZ^ALR9r;$(!FlhJFV>zhgAO?_p7;DF5He$$O3SzWG`|&HliSHNdN183x^}8c
z=UE>K>w4|^I*B#)(2mzBc@MfC@kyzdIa)xcC3PH)dsh3HH#f9V_KZV=gK_rAEOH0l
za<;p9TKcMNHa;{sc$qu!!;6e;_I!9Z>%Q>VMQ-WF>2Akk$koTtYv%OKLD6A@mcU~0
zdvUTyD_URbkTb?Qh(AeR?D<N&17<t0r!(iGACH#LcAscjgRIqf5WaP9lE1(ACWh{U
zCl@{D8U}f;N=;`^kIOtyM;=Y*U7EA&r)OR+XB!e~kz4xy89Ni|?EIUc!BSnD<lhS{
zocH}E&URW!Jp2;kfbHz-xdb>n!QE1$Tv)knS8bMgSTs~F6YEsDZN0VBm-YYpc64<|
z=!4f}<vYBCo|pLE<KWUGzi*IS<v@P3s};G`DrKddj7R)1EgyfUc__PZikzviv3+4J
z_Ce{oCS+s>@oj!vkF_N1z@$RA^P8H|hTtpQ6ITOW(C?d7rC<6xso!=D<G{6T8n5kw
z*A3ux8uK(2Jjm~PG4`9}?{`cCubqNBu1<afpq1bF>*V)xTAkzEk8>|`XI%rldLdrl
z8sgOvyq-pTQ^Biu3ATABxV^+3{@zOP-3ngaHktcZIiIo$uM=@9{&^LiEc1Ke-x^n}
z846tst>pP_dOh}Yn1fQ2j3X<#oV@GA|3t29oPhhnbmp&>wd;<KnCi?h|2qrd`sRjg
zhoM~d`z&Jb8GFte77=syjH3nDeZum9>wNbn%cE_HEz6!LVz7Rz;D)iZW)AD|camq+
ziSGwYb()^s;U?yvI_zy@yyqi>J;vJ^(oxV^J>I;bmWH$<G_s*JbF92n&s9k89p;aa
z1*fsD7_E0f<9cmN?0;k%ea>l<-z?qMYnG6Y;`gSpm$~cpu2$?=(O;79I_dgWSFInD
zb)eu5&a*rXzlY!45Z*Um(lXO<`#!K4+K{-B-xc$3lH409D{H9O5ya*EX7hj0Up1-?
z-Owhm0t+&qJrmf9*o*p%5gC&qaS`^j!JB$-qQH)gw?KRp8(+{!;#aWe4Zb42!kD2I
z`et7tG{5w^R{5<1!IitTr^(%Iv3C$$m8MQ(Pu@~@cZ%m7oY`N_w!BbSK&)`7gKj1#
zN#OP+&l0?|C$NY83PBTiA$ONOt~y>4oVd>}@-3a1r}rCBeviNr<sxk~5+0XoDvsqM
z&C_vF#=D0Yd<i_1z(el@JkYO4%xg|xDEGMUK?hXgFwCpqL405%t~$Gj)!CJ}5it_#
zEv@)>#A7-n9@iTWN|{AU=i&;^7(dTmd&{vw@Q+TC+$r)l!7XFQkH#jZPG2TRow$b$
z{2chm5!Y139kQkr<~DPtb9lz7<Tt{rccS;uvAM6Mrmz-2{4?-&Mez^R+2p)|xK5EA
znXY(XNPdC9FKd#&W*?^b?(XK=tie8#1wlDWUPaoynZM({wLl#W|GtU8WAgV4`friR
z%!kEq1!os13%Vg5!E?w<&@=m!japyJ712>UWxpBw9xsJoGVJ%=Bz%)o?A;3eI_6y0
zMc1V>Ht_5=k%zuQ2ewL{2fwkJ7I=1Ihw8td;BVmBDKeVx+h|ANxm5m6sJ5tG`ArOo
ztBk`H?n&2hRp5*25;qCU;gj>*3SlgV`IWVR12VVFLCj7n&J@Nj4u8XBpAnDzD&e&#
zrU#Fm>li^8Gmto>#9efIbC8*HJ6e+Jc4TKi&-~rq2dyDb$z_cDy>98?o$$d;>}zip
z+LC^^^-lARq|Z8B&1$#wr<W~Ec$d*0;}6nHj%}E}t+%CbTd&n`B;k{!f0JAK$r;GQ
zvzM5`8Rklq_U@VMk-_VcJM0_wFI%{b{qD-24?ll`9LrB}7Aoz|0tRHCQXk{`Fl9f?
z_Z%_k^O%e5&T`>>@V@BTg1dCb40m^WZMg4PXt!nt7khPUWllcf?p}dS@!vUQ!<9>Z
zRrok~{iyUOaO8hlSPwnWpY+*EpOS+&Th((Wt;iJmOuI`r&XN8N&ML?5$Z^eaH)pcc
zyHf8H9(e3iw7rhsN?A+!^N>~a4@?5X?o4{guM6*|&vljYE*UDHk>YG<_Ap<BUw;X7
zTG_{Zk?dne=NIKY>y5;R*pH-T)Tv{-#wl{A(0Pm}$3^bcnb0uvyKPs_$A)B2talsn
z<&t@pQdi5nX5JB}%TJebbA&H^elvn+*-xu;llx@<2X%X$n7YY1E$EYa6<dfoVr^L6
zWOHUR{aBnw=_6lzp}SM&GevFFK6{{Oo4UwIWl0W_v?20Q<o05GQRamU{dUgntzq6Z
z-%;Yi4^m&~QsC~ojTjtpFZdsMM|+HuHcMhtXjvP{RN;rKpP17Djkk$hbxY4|()=QE
zHF(2De!*YJJ>iM@;IKUlAGD{4PoP7@UP8_mc&_W0z76)Drs~L#j(MB5^}dNQiM{$(
z&U4o`Xd1mvjvM>tN*A9FKi+I4gI@N&+ykF@Vk;nfI*eK`?hb$MVi~K0+<@M4Qs3>n
zzTF-8FYM9{*s2>^-I2GQvE-EkHc61n$Hab^2b~1X=-|rS^iMV~Z$u_bf6|BaE&Xwx
z%5?b+6UXqg;H*vZ;jodgHyYB6IR}qpvt9>J+|X`vw%Nj3a-ZNC=(ipIXoaTQ^M?mJ
z7bg5p{1h$cL?+ApjM)U>oVGjYV}YK7ir$lXfcD+tU-U9Y=ApfVKIII9#psBNer4Ww
zlyu*hON?-k{l@%0J33x)m_NLsbKw+EWCG=q$hI7FGp`?7fzR8SN8b?tr{xt{kC=<!
z<=rat=@{M@fawkcImaAbgiKq5?ZSLFU4uL$Pq{`(pX}pZ3hhh&=SFb%4$cYy7vFC~
z4s^J~-{<@Qa+Q%+?(RC?v4>Hgbx@H_-X`$OnUR+Wt~vLhCcWfW<?9#Piau=SmA$Y^
z$@v7AadAdL*tWadp<OKl!TpZu?&c}cnFLdWM&7aH#lqR(`h0iTe&@Db&8xTdHm@dT
z=;EsoPZ_)n+z=-~?%?O!hBxgG$rsVhf|H63fzGicw$J{6_Qf4#aIm8-6%V*aKI8BX
z<vv-Hu1%s_u|F5fy5q<W<}dti94WL8*Z5h%p`5`YXRf;=#8D^G1@jND$QmIzkpAi0
zdb1L{V!dDX;^sC(r$w=mm`B>KD+#THduWv8wPfLs{^2<OX1QF<&&K9CR<;(Vg3aW=
z_<4L~{F1CY($M7gJzaA9hWL%#4c+d*wHw)MonBb)-Q*nO?~z(~&uB7hl)_er7axOu
zlCmFL?-z)kBRlfcGI~gGFubwN9WizLOOnB6!E0C2=e&htNn*!xE{P*Bj7(`aUqfEK
zD)zF+_~vxjrrK|_?xDx}WES~`9gqybg}=|P5&LlNQkkR02C-E9^PS}wwjFD->+jfz
zjNm;va^Q|LR{Fu!2r_QJ_e1EMHJ=PQdC=J&WL_V0duwKv*p!|DZQMpKf#1~_sIHe*
z(B7APy(f=7Kh)ohyoQI8oO6hb2R`VC`GS`#Yc#cyEfVdOVxJW9fHj$sYthFS<)klc
z8TNLOEBdnn_7b_PPcv?Ew*|I{-efI%1lvetuECi5GEWuIJ7%f)(tlc4-z2h@_&c$C
z;OUk5m)utJ(Sgxxme@il_cb1&6VA;+wpVZmj<SMR|5AQyiZvjiBhfw3S6bd72R70+
zYY{%@q+Xm8_^-zHbcb(%_b$$*QqbBh5)a6o4!=@Q=kOy->V3VJUE9GE@Di<SE<U;;
z<}SS$d9fpFz5tw&ohSBPtttGG%gUN!L}U21a=!Uk9zE~Fb0+X>WgZVOhhz5N;ofX^
zv8)a1^9*v$$R{atQn?|{Sh@O%sY@B>B6zF=oOf;`7Q2nSDD)R`h{tma8_45ApCN<z
zZL|XC9EEX}B}e33l%DpX!-K4eh=1jy7sN-~m|aMo6!VB&D`b}(!)}AOp^fa-Pc*h6
z!*i(yzlk}d?2hch<{(R)0G(0R@?xRn&uSTt{61P}tLO^KcS!lvOM@LdYlva}j&%(D
za(AR_k>n<2Uf!@spTkFAf-|jO#BXMPkrR?vIG!_%4s*ygf>(%L`yDNMz0mI<#)96^
zco5%}SQ}&3zB9Ouazbrr0on?4ig^~AsBSBT5A6_}YvHUTX)A0~x0UY4XCUuOaD^Y>
zOZ%)(iElpMeo<rv{&w~ImEHBe!~k?`GlpFJ2DzwlWT74xd8l#hw-h#;tbJqCMB{3U
z#?=N4LIdD3^vTD^<?X|s8ylPSJ2tj(Tw`rT<7#UmpHkWi+tlmp;ka0bkH#fy?&&ZO
zvQc;ro~n#zygwNe^xP)nHD7`L<$NOpnRcpkjZTOi%<IVCAnVt1ZqfYg5V2QTXM91{
zZZBgUnl%u2{n~EP`z`NK{*u+i*UN(g*d;OI;`eiY0W^K(=2T};Vok8dxaX{An1iRm
z#h3E`tX37t|8v)Gf;Vsc61=|%dw5ai?ZlbZOKxNR#?<$NHr`p8OTqW?@_mNbHp7o|
z)(5u6`s>@!70B6-Ze$(lJNfUcRjJPfTk|W$R{QA2mI7yskUQukeBz6P8`ss5Bbb05
z&{g>4%MHF|URBu+_z|AIFY_y6IK%{i?Y_1epFBNcSVoL_R`(eOZN&WtkjMCd>OOSE
zR?!7EXS&LF@FO|ie8UeLPHrM@D7O8g{Ke?9fladZ2h4uIUc=$eJZ%Z{WakaYnyO*&
zpAo2q1LdL-=DTb`W-2ZB|HyNT1Yh}2i9D<C)BWiD?0HsR_Af9u#d3kUDfhYSWlgoG
zH~%5g-GU##BlEY)s^EiICvAu=S2GZeTh=M{+E9o?ony8|V)B*oNF0rRJID#+H~Z8Z
zI&0|>fp4H;vEYchn<E?%=koiFxY)gQTPk>yzRUsoi0FfP>2CSELCVbC4Bo}}{&`fk
zSH>!J!Q+77#2v^sBPZ_{yqovPo(Iu4!GNA?)^0NIgP!BT0Q1}@b850)1nu-gL;Vx!
zXN<1m#5JL%3SDJBTA`<4AoJHkPtaebj|B8~wa5+n7^5e6obTiG#NT{}o;<;^K8LY9
z*oT~E%tOq_zn6rc%nynUQ@$_c1qCl$k~3G1!%KVc>y<ZE;4<H(=SA?*C;3}uFLHpK
zjF!cNTNxuUyx=4r0T;_M@2(op<&%u(e@#9fbgLdmNGCPRn45=q9*yRP^-~`nt=lp-
zFEO=D&&vgjA?^=k>-<H`WgoB&For&S=nnWp@Fq6Medc>)JnSW%L3#c*Oum_{Q;H3d
zRQK7~JdR1ZcZ`i2JrL{(^Zx?uk2Aq#$iwC|-IizGHdfX<W!ai4_?SZtUy?g85WngG
zhNZyxfcdgsCk)4NLOJMST2;9Xy6-;ozOlahs{0mNr_Bd!6S-6_+=qR()UM$fd1dZn
zElYoc#>(Y^@EgzkZk&1Lso<plL{<NvtF%8!8=Lr6l^@UiNqjVmewQ-_!#zR##w$E4
z{9p2u{QisRdnNXd<mo8R@(Odb;I(e8gD2TLp?^0Ao1C&r^pogb+SI?_sdKO*do6sQ
zqkqoR#tySzINS0cWm6n+Yw;Q2qZ4d1z0Ur^i)r~yPH=jXO;)i3Wjs1}i~9aCa<s4;
zoMu^b=Nt^~6Wf)Xp`GO;de7O!ZxwrpoTTx+b`t9le+s)1y?da+3&5G|wG&*<?La;)
zmHspA+uB+F55CF%OudJ!BsomZDPlXZ&)56KXy2XpV!bbUP?Fmu{>@}#lQJ4twc-9S
z*+bT>h9(`y>y1%hU3q)G@3b;T$(54$=VUoj5?`nqdxQMeE3pOk?I9Z^W+pO<J*~<+
z7x|XVpU(T3&smA;Yuk36K9HZGdi7c4#0{`<i|DV<Qx;o8pFP(X{HR{%YeHww<T?LE
z=m#C#kB;IzWN6`!$d3V@es}$^AHdEgk5%iPdo%l@HJV=*l>8p8j?ctd4~(hw%8n`c
z$k-_r`*#<3Sf~!z?Toq2-)El%eV!TYw-@;P?fKq*`wVb2&)a9`mDrNVAIbHUm{(`V
z7%zQW|6Xfv)$g_TPWZjnUb{8uZ9p&NH$(46(3`)x>i1edkN#?*k2<b;Rr!rp&OhK;
zsgWAR`M!5Vzs>rLoClU0m6(jQ!E^tGO7m>b_;0h$znkA?-Qv`<ADL}Bv~eMR!Imy`
zDSOdIpy^dM-)hCyE{g8toJ#U_r5*MIamFpV^VjO%X6<K=?q0>2DDbrs--@`1{B94=
z^4qMOz5Qz0T1Q?AXGLXYJ%_z{G5EaIdGB*sewQ_U+ZI*3^X~BKt$MD!tK8S|ZB6vu
z<9;-%^8)wV-oRC9=MUZ2e0?0AKUDUGdnYe@dQ}^T?wP#IWNr6;Rn^Yqs{VF5^{d}m
zQG5HoqH6Ewc^Own^zPHVle){IyF3qrE9M4%<D9FS<o`q6yT{2<mHGeGGu4$zCKGzX
zbh-nv=?O_Qkq`zq#-SCaArnowC@N|I(Qr{&_3M{ae5v`aOU3laAVdc?%Al|tRQ%!v
z9e2@X-CfgsGm*HmYgB|mMJ8SV*Bc;m2}%0*{ybIHQ{B@u38=gN{^(a#SDiYS=YF2&
zIp_GfS*~*7hp+a6vw(AdY3H&IFL(=cE~DR$iKu+(-NZD>?ex0v)9r$0HuvA+y^~nw
zvF!agoB4cLZwa0W&t@I6vsn>G$n8{P8MUjua&r%|XP$CK;iU|`m4Tl!@KXkU%D_(<
zcr633W#Fp}eC75Aeh|?Wu{GvM&O@Ij_Qe`|`r5rn&qiCIv8RcPhxAssxL>&$%W|J>
z?J4}QKZOb#7o85+e#L&$om;uzdz8(}@^;qSL~u5%KSAAlwlP1;RT!hyTUi+F_j$Ne
zIHSKWXuEV;(DwJ%#@qG=bT+F$L2ildebE)1&6*0%W+hi;j<2&>CzKC_eKC$alz*G)
zh(EEQtCbwV%Kg!|I>S%<=#ZDAv*;$g<;3m#E4_>I<P}U*$y4Dhk;irZY|s|t;%ru8
z(fW?O9UJ>)tv&MnyLry?b~(?ljWbkFN4~HZ1M-%0>ipoGI{u&G@J?~U(GT95d!R+J
zH}Z4re7uS5k;tXq)@+x~$73Jq@O-=p51T1G$8W-OH75K_ET|d8cSH^nYuGu*k9)O+
z@5A;gwR8MftB;-LYz@!x6JE%_S!-wbosr-Szy759QM|P0O}SHAvbm1dwYm3Mtnp2S
zFSm@U4V@1-mIjA^lL*H8($*fGKbU(P^EzNVH-3I>M|e)_;jPvO{J^YNIu02{T$4Ow
zgVoXyR!2_4D)$x64QJhdSl3eX$M8S*j+Wp&&bPOq*MqveFNO7_!+vnK#*}_M6`tey
zYtApFkI}ctUB_cRn92(l$Xd?5b<%|&wA@Y}#@gJl?EwdTY)$0t5DfcKb7p3OeKyXQ
z50d>g_)lMdQ1~rncm0~Y$74r{IgTpNit_h+t90HY{IIu0xvP`sguazC9bMpdrOtNb
zoX{&;HmD!aqWZxvJSX(cI_Ht^A8rZYJZExz;FdE^!?9W3Y=!Tmvv7~Q1vrl`xXaGM
zUAwxCvv6leXW^EEvv8A~g*z+3_?B%5_C^+Njvw-7C5)ybzNIe~BURs$@H22TK90V-
z+9`bs9ezofGZ8a$7-P5dsZ6k+mV6Gq#FaOY<2$(Ei+4CLW1k<lrBcE_*gL>}^VEgE
zDm)KYXQ%O9dQM5_G%e$t-n?v6Vi#HXY#HBWIbZ&gGT)WM@5&Cb<c9AGTN3%guM>50
zFx|pFI|=89CNuwqeIn?m`k3K4{s&HYtw=`E-_9Wx5nNRGsrvl4XD(QL3VL;LRDDAK
zu1P0+bhJO7Vjiu0W#W%@?O6Sv3ihF3o<B4<;oJ;=Z!7Nl%R$yvBso`?{Dp4zT&}>2
zoP)tN*PlTDOP6;JdH==v7u?%-Hzw@6d7nrmRo7Xra}#nUk)bcSx3kyWru)fv@{{s+
z01tx?@FwS`|K_!nEo8KhgtLq?@(C&r=y?Hrbq<!_&Hm!Oaa|!>hIzn!HimZ!My30r
zx&$lrVSsirl*#>q98C7X!)_5=<j1hOIiK!?+&B7r3-73hztwqu02lF`(e(0wrX}C(
z><wsFG%a~1IU!n>3^RFgcgP3bv2RM)x6^z>KOOJR@SCGz-xTY=QT=LX@4W%P%v*_#
zT02AbR?d*Ub=3CIN1jSnY9D>oUAXP!;0)Q7;Tf{4HE)|`@jR}#v&L9w$d2yay?pep
zDQCzIafWR5dE^r2$#cE{|5`rMC(<K!hU`n6R2g5g$z1L2wCmSH0lyue^^Rf>OAq^*
zvxNjJ^+)4~>lJT^`LbjQ@?Y;<ct`xJdAheZcqh0{`EDb7OuaQRdW+6Ry#yTUY}B;k
z%*!^=PExWT*|v6G!aq~84m?hti@HBN7xfwC6(2vu9R9xW%sJ%YV7^#8b8h)4<Nvqt
z%(>f(qvcz5-Z^7r@3&<e<bS0t>{ZEKV0t=p`CaD>&O5Tdl{3#S5D(<Ol<0NeFZ$;U
zlYsuaUF>D#1v!HK7p+AP6&6{JQ9h*qQ;^%M1NxVZjgS7Z{+>GezX<wIR_=>rywU9F
zNzAQ~@u9qk>K3ok$L<W})d%T<+|S4rZ7Hn=u7|@Dw8xngCeM8Mjd{*boNVEB^?V^+
zV(om4cBD_jb|ib^GHKqA|E7hpud}hQj>hhUV=u+Ve)(yPeJ%MA$V}o90q@89GR@e@
zpTHk+U#&mytnZJzFQ_*dcZv1l8n@G$dr)I`PSKwE!I(>@24j{Cuk_^JX)!s;CgeqD
z-ur@b*ey-~ZjpERH{&=EEDHa6a!Px71vD@_DEA@k-%IOdZ90ie5A<;$*VoYJ2v0G2
zo}rxKFu{3<|C@7A6l3GOlQMjh=FGPc&d^(DR{BPIfc}=e_lu4fZu64;&RK40p~1d2
z(G$wuR>fBF7aYy_MR&c#IkIahSI9fm;df8M-jC5i>4YhCM;=#t7O?lw-;HBRF(#hZ
z#uc^^;GuGKhVN*nH9p4NL_a!{JuMRz`Q1XDTKOUPcrW`O2w$f%#`n?Z_j*TajI)7t
zg)?oz$A5CRU`<C!<|nnDciem3$xdNYJ^YPsALh(S^n~<72uFO!)bj%N@r-oZ%XJRm
zagH}|l2iB#>F-APJM5|LB)prTg#d5hBE<V5+U=`vcM6Q|R38F;9>4|qjN|+#+JkD@
zgm;4afqnCBqrnrv@g>3=-(2Fk`2OZr9NEo-#EByt*;|E-RXoY@^OB!+XU|o2b`l9u
zwLUZMM`(+!BPe^n_d~Ten|0*ajo28$8C&v`a>f?6q3jOm@(13nCt(+12fW6~=GOPC
zPxW=)FF7w==<^-4fXx72$v0B_j0c~C>IBB3-&>HIqh-s9JdFJnIa8FqFeCeC^2}-E
zZ&)_T85L1^ojD!!3!dS-4BzJ-?nfVR2K9r?LqBF~P{6HpNpdv30G~_-pG>=dzu@5Q
zILX;S-^4eC6Hm^H-&Qkc3eL`R9*XNZ@B1&-nRsjI_gbBUSWfs!cnn+TSbWsZ{qEBH
z|IK?d_7Gzi{lHV?TCx{n_+R?V`%i;$R=U9ZF*vN@BBY-WBS%7d)Aw<H_c&*K4fd$_
z8r5;^TD7UZc<aLF_q`-||BLYYq44_M@I81T=dM@sKx;d!t_9&cH@w~+e)E9Ivt?HH
z%lhs}a79d6{eIWU=BqV6%dlUa;ku-Fb(*=vTKRSaL(!Dx#C0$%zc}>o)}PChIAxCf
zm;Wv2@;J1G@9~d*E|07Hz?i=?jo%g+D6b?R`1-mheSIfm*Lgl;)|x7v(L-J=ay3It
zhCPf@bDg$@%;UEfj>gX}-*wVqE&pJ4-ZG~Xx{!|FgiItCqqK>91?_*b3BFi_e)kK@
zg0=FBtzgTiMu?*nmdM^q5<9_{LZ3496a8Jc?-_guTv&T6{}1bU)i?D={ZN0{Qzy^4
zNt?P@vpiOP4{_VI-CDP+{;|i>rl^k#?$x@MurBrxU|o*I1dJcPgD+LKV8!AcL3`R~
zU|jy&s;j+|0zbdSvn>W-F?nJD^q(Ae<>s{aGA9A19ewoI_6<UJSUjMzWAPsx4`>!=
za6a?g>n-+Owal$T8%`zMD~t7vbAd^9d#8)fn)r7w*Ap!M%KS|6SLIAIUg8$$T4W9Q
zwg15S0r<?$hvJ>qC1w@B)Y=5fU^6>e#m<N&5HBM);J1SFY<M@?gKO55dR%DF`#JGY
zVkoYM|3&+1?LoIGr-QtQI8AH)K|s&37|=1cFPtCv_LkCKau^zGx(*_ui<0dF#~O0d
zcjN=iu-}DfPy1XfAWurM46Sv~v0t0^^DD6b4eM9^0y!5d7wzT8Srwbe>z#boiO`%i
zi?!d5U*f9u+@iO`s82MeoLALNtiZLk^bh0DjO{_8J&EJ-r&GR2K8V&1C|^Q(5#(^B
zEw2fGK6xSVHFT()$?o3LBkex>mRjBk^^ZJ^&rNxGjCo|IQ~A+=!?}WUh-G9djJ0EA
z3_Z<QhAYRj=Lb2Gwyt%hlPWB8wy|9+?~Zm<9zE&@xh?X~`^=4XEnPi^or4|Qwc>fs
z7S=8imk;+u;5zRy%Z>3Dq$={E*1l)`nQ})`+vJ=0wXHw2vv<{x5_uxpPeSs#@R0bC
z{VK5;HTR{z^l`F`_k`$5Iqb=8*n8|Pfqejs&;`gA<ce}#!u%`2J38;oW4#Oido9KR
zon;nQdb@}V5$DpCz1sZVJHCF1IXJ`~sjDYe7kgG(UAn3+@FF=fo4&WRH>YSa>>D{o
zYDe$Vz*;nt;i|Li6g!(LYZ~OtmOni1*i6p&H$3-x@iq0@d9?K3{owh^o9IPGK(m&U
z)mvIjeAXiml=!MUc%$+T>f)vL?Vx?<t89UD)nOyQz}_do!`3QA-zw)z{h#&w$vrUw
zSO;<2Q+@#so5FFb%=SO`+{dgwWPU~;F2UwT#v(U+SR14@dwuks@%ufx7AvmyeXO0U
z$DaSa8dLPF9LAmxwa=A*eeU`In$4fl;-}X0lYUk|1kXFZ=UMJqI*JvCvUiHS#U~`)
zES=1^S@PUMy*z|oeiD7M%g(dI7m<=)MrQeQS?kE&X?gr~o#^)bT-LG_Udfd{<jC{s
zBG=G#x$F;oIrOo7m(HW^M*h0~Ch|OOUnR+DU|N&a)<#0{zN9nnMHTsQn#z5X;Sb}#
zXprITX={73rm3Safy|m$vAWQezH$uBR$win;hFtGwMQcI%TZk1J?zqDrIA@auw?%b
zzbts>?iQ^Ewuf|#x4YiXKrb5X(3O7LV{g^{)ok1r(HVpKFL@=nsU2jwqqUL1#3y!?
z?P?45A+hH>@cp!4r?aLa+HcjK{~PU&4zM<uKB3Q$!Ls9ea$S|w<J&K1E$`*5fqmKh
z%UIW2>@9<{a#rhl$;p~8n(&r5PVQ)En%qvl%WF*wb->eWSnvCvlpkYn3(7vReIfLX
zja?y@6vTY+RcB{W*5r7rzfd|v|8wm=wxh#3*GeA!q4%}3FmwinaL7Abdmwt$`}qHe
zPF-8`R6-v*KN4QjT00P|k?hO-bTlO%lpeQS1NPp)CS|WA<Symi+Wtr#PFXrGEXSUh
z+45q+(P3>$2y@o!sx51S@712#Qck9x!56)1k9-O7dp?psChw#6+2>})_N5!5KCo7L
zN*^8xX;1ASW3=~QZwY&=m3?J_sc2EK3cmC6!oB|2V5MA3uXMlJ4UPGh=**g3VYbAv
zjG?<H_W|WE9>Y)T!<Ob(oa8UNTlJEIx#DKOb7jeQR`qS_E#BjiZ&Yzt8Y~90tyk)d
zxre%l?=h#}*@ewS&igjMIR4-liX)%wEslKpmg4C08;W;7e+U?jvbGEVW&16aq;$LO
zi!n;ODV;}2KUf=B7-22waItUJr}24?tVmX<e+}nc_HSCnn$%T2ckmxOoIT&e??-~V
z<TJ4PMy#%_%SVfSpWVh9zpcg5Pv5p8>98l;%~xaZr>JM^s;&h8lRB4@c4xsi<zDYK
z(7&tv3Uc@HwFG@SIwd%)cw?!{VDPv<1Pq2|f<f*Lz~Js4_A<SoOdM^?fKvgEW)Eyb
z#*7F34gNPD`?^8+Z#)>k){ATWmj~njrT&x0v+EemceYXQ$Yh-c1A8_JgSW8<NdN=Y
zxguE#;n3e{aM-Q?$-KcqFd&}3s<UFaU-7(3fcGzuH+PTM=Xy?J67TnOu8*&n%R+q8
zqq$c*qpNOqUQ#R#epc`d{4Ky0{(d%jnWAH8y^sBjQmn%y{}rDX>jro>l>3A|V_%Mn
z>us}Vy}1wDvtE0~*)7oAP;vZMWurmi0Gcye6s(}d5cZ=6yV1f8qPYOi$LlQ6Eyb;Q
zANm_9_Wk-+;P0>S{B!{S>g}sGm%3Jbz)zRumj@@rJ$Pq07!B%$e$^h&0{Bx`-<7wp
zUg(D6=tOyi$9#I|g0j)z+e_sYZ*#QQE8kpDE^hURUvz7YO4hrKag09&?|k^A;`ndi
zrEkDPPwgq*y<~!M5gVI*J8cXXM;9+Dj@<IXa7@9o7%$Q8M95D=#lG2#jGjEvPcmcl
zbf%M8afZ`bwzUWBSrgFIa6L`2FS_MY9B*(ky4<?rc3^ciW6KstFZ@@=btQ7+BQ~y;
z&PP`Kg>z*vuA@I9cvAKz)=F&?Jn55ogEil;WUcoV{7&cHyb^owQpd}%E$-x;+0Wj@
zzN`x`g9owq^=+2x3s<!{ThLR;59sTyz-X(-nw_g}MW*0eo^`~Er>nil!j$s)SVKil
zB((Et?kO*s>78%)eT>iX&b0ep??3SE-VHyy&{Vs9r<_k$aWTFd@;sFz=kq_pEBkhc
z|Ge9DCC>CWoENP&$%nA(FY%olJlAx2_r&fGN3T4txh*<{^#J5BJ%I1`f%NPO`<?on
z@r%6HI-q35*8Koa<`CWa+@+Gs$MQR-7Z~JMoEXXF<9k+J=XXjk<c>~=SKxsXzCr1z
zNG`uE9mwT3rIE|S@W$1}@wX0gChAJ)rd%9-#}|rsFCP&-0YiA9J)~pHvA$jY(twVi
ze+w|$#@c+Jeba7Xy<ZkQEn1bRELxS_#9FJ*^FPST4ruXcXgc^Ge9t-_z6JNtz&D0g
z;3Kf_TPlm#OVaM;XDW`DS%U{|$p@G!hmQ&5@M|i89R3Y^-Q44ixZd<*&V8OSYkaJ0
zhX!v9`!p2v(fWsc2>IXmUSnL7rjLH}KHe0K({C83KRM1d$lLy#i=*C_75~0HtNrpN
zUsrTgu%l-6kk`iEr4D)O74|Om*}JsFURum!!8<nZ<oc?)!Mx#a^5*s3iusl9l_e*!
z>Q?fu?@1wxOUPo&S39Nk%I7V0ITw!H>zm-=8#yyz1lj(QRX^J<{~f<?Us?38@Y##F
zPriuW5^D@buwA}OJuRh#*3UynBjmw}jz&aB-sd<Yy@bxc-Vb#?&n{ss<L(QKBmeo5
z;&|T{*4ABJ9Q_UZH7viK=aNek2IG;Rtwb(#g>or)7SR&xsGx(}i(5rgE_89_!s5sT
zv{=3cIf883nMO99u*$EbS6nXH#C|k9BgaenZj?4|!ERSPJ=CMYGkm@=`P4TN$fqkL
zpMI91{0grEu7A1(JEC*dTPj;tyty(Ye$_M9Sh9{YHH@CTrZ_sJ^_|_e_FF!`zAYyr
zqgb1MSdsp+?(<ISdButJiF2=KFGfx=KTxcWwO)76!G3WWpZYu-d=GZ6TIDP(tYnX?
zUGR>76F88*oQ2%ZKd(4G)`e`BT=u>90o#$!+)y09WQ*}=z?bMOc(%ruv$q)x#JBj8
zMRP{iTj8&}(I0(-w*-7W9glqq`qdh^h|f)5+5eD!(N}}gSHzuvvIQOx%&uP5Qn?yF
zwR^3<^N#CxR(xwaW4XDj=nulP!q1g?=zKV!_gTH({gR)ZeYE9xuVHNL>EXK2+N*RA
zjk(ZMC-+0MM!du98FH6r#GS-1-pBQ>qsQB%>z#|Vuh)VjWN#nl%+nqXyG~EM-uB|@
zU|zu*mf7TRV1w%3W9=?$K*8<l%f<}HcV=1Zyi9Wx>ULJOlujt_I+J~l#%xcBjl1Xc
zu#Zc&p!L@5b!E2nuG!4_Dhc`K^o{paf31D>kC=n?A=b9a2W^wL6SfT<gl&`mtbHQj
zOV-t`>9jVVX=syr3;X-~yk}^$uKkWY>xP#t=)xZvjZrzY_+Q!Ip{H(~dl@Hf%{0#V
zT*3Ox{;L|(io<DRzO@mIMQz~IjkOVsM{Rh`#}n3_*VXFAXSdRIS`?>%_n2$We?EIg
z6^q|@`{XC$jPIU}_b$k9ytk`&@4a(+_72ZqyO&(tz4y*zom1&YTI+gObrWYNpf8Cb
zq=_LEM_+X=GWsm($i2f^_NHF|Uw+gtytT4y-Z_3t;jfj?waG8cN~BgYKV3V|KP&fZ
zC)L)*^=xtrf;Fp)iz5Zr7naXu?dmzKTRoyU`k9epWkJ3;`ryZlyS}%UImX3B|C<+s
zi*?KMoJDd4eyn_{1^IMZ@zRSI7rw1r@!7-9``8QaKsBuQn|apwvX9y>^zDNq>_4<@
z!PlKd*mjEsh?~%dp4^e@gXT+XI*a2kr7Z1^l=+VJXBFl@&?S9<ueu%fG8w`D&0Zw_
zNM5;Y_;#6>UtjbeTCP2ou?u>vZx?EPo>QJ++=5x|UG#P0^5|^c?v2;EJsYnDzPqXa
zdu=_m(N+9tp0&dj`C6~ud)?w8?6)j?dNF<vne@^{GsSIk$2w<WQ~6heo7_$C+UT6q
zsq={3>l1#VC()C83;TgyS6I8!*+tw=^^Q?*d1UYI`D?wC9B1Auz|)ctPd5s#A)a0w
z;Hl6GjGn5Voo{nqiJV--xbwl8?jHqj!qq+Nfz^89%<FX=wOx3R?W1;9VPQh}e^nu$
zfJV|OPwQQF&F;#5#_`q9!jlf`9xv}MT%PC|uO_++pGqKCX7_kEh4s8CtOr<IJ*&fd
zSZ~Z+_rl^3wBgVG1m754<Zd(AyTVoOqx~tt7<hAr!h9R^MD-3|`<=lD;G@60cxl@@
z;mG#a8{KsT<DmUxJ`vQpZn5E$J+dQw7J$!KHGzItycSt>4QCR(E`t9lozOP;bWbnb
z;t;FA7973j2=c1d3f6@;Cf2WX+MrqSp1XK?i?fbB2|AGxI^!X`yv5J6mp{0|mcG<|
z0X)^meiSKk9pOnA{%V`V;b>cDZCscBJ8cehGGAF+cw2(8Rh*U79pHKwK8b|uy#?M6
zX;82!?%LxkewRC=KjnQ@u$(<&yyI2iP4wjP<VYVNjyKYFJ@9b66DSkH$6M6zOr@u>
zE{zdBIm`Qua13sC{T$qgXO~_B9EWutEOd86u1mhA!)dddA2ANrT}@Y?&WtpAc|%Aq
zhbIDhSsv2MXQhW`_pIe?iQGRsJ#B4Vk09rz4Le|0`?BK5o7b`Tzy+*ZzMwchA9#P}
z`eJ1c@Om@jdKu>lKlE|>$Ud*g3hYmBbH6iQJ*AWL26~V$r&+!42<!d4<nbZYyNh~v
zJ@k6&eLa0=9t9p%_jkxec&fjgNA48I^Gi&Aq$GP-|E;q;Mho;!GDmY^(O0+4jmm_K
zR!-QtvFtPOq5Q_(?#SNjJl4flZjfx+xLY#h!A0J^<P#X5`e!lE7N4f@w^IK{=TGu!
z8+`iU67TcmseD%WKu&zoXb##MLOx)JU5fle?wNdeVF(Y-N)bG~o0&Tuip+*DWt*&Y
z)+WF$ercU6J|I0WIzcBIO!8X4S9m`%hqgCf*G4&OzgK%fMCH6L(Z?LlXJ`v~)}@{@
z@-wJM>mCDolPm~y1pMlH@5X)^oqswoUF&_K8I6T95Za!oCOUJo`=Nn*FNF8cGr2O<
zzHaYz1@@F$u-;${4uRdry@#oH*D>c6cfI<E0LM$$X*}K=$VEKP>5&hbae%+0`5j);
z7^fSbtvxhe`Bv2TWhQf0ft$KEX4l%Njp;0n$!m_ceWHcSyP>u2;`nLnpoLy&0iKx6
z8h-J?`U`=}2JwN`G}L4i?LJo-CHW*dRns#jqvqz(H^LP(g-?rlIJmt&cb(3CkPHz2
zH^MU*tKpD5r|EF7vr(JrfP&AtnKgbH!X||l{tsuG*3mcnfc&HCo(Em64Ry2Vv)mWZ
zRd?RIEcj+xy8P6$fbq}ceU-eKz0P~Jo+aVAK%aOAPIBBwi9LSb?Mcse?%#WF4|^s#
zKSEczY1W~nXZf7N)n87}!~W{PUqKENdEWReu*E#tXPbcOQsAA(9yxwn;Yx@7O7BSJ
z{+|6_hv)bk?`^|ATQWT0T+Y0DZTHH&zcipx<nZ^szDOtDRlNiKQ#es}A965@9h1%F
z9rogG8`*g8oZh{|sontxI|6%(b1iPcUcmMtF~Ie&EI#toO`K=itG$^xQ;qQr4rTu1
ztL8hu`+leGk{>y3bNLPbFud|C`mcBT4f9Ozx5a+9@T@pGeEop)H@C86q_kCML!p<-
zvh&GRV7$oK<3<>N3AvfwhCP(~>qKfo*MCo>Ht5<V-R&@6JMs2;>l3mOhI7{@kaKf}
zmzVs}0`hWYC6cpW7{x^R!Y*vMTu$<F$>_#w+eU%0UmU&o8tk^b=VGH!mv9)!>!nWd
zqwJ%F{@r_B-^8R1_d#Ig9Ywie;#&`7z+DD>lKXH!xrm&dg3kdQX25R-JZ8W-=Qdib
za;&<kR=3t43I@dIN`-8KvEpwI=HK^8cjFJdPxI@6{g-zR%&HK_?$=)B%<0=c&fFFs
zX6gm#7WC1Y^w_=<{!;uq*Q(Ct;E%m6x}8yC#mwjZ`wG8D-{L0^>h-C&a-V!q1N-}_
zoAne2wtu0x>$oqoXI8m5K7{|_)A%3W-aXKY+}rgw>Xz(7f3Xf(^<&qJf*bAQ>yA}V
zNtVTv7xHfCIL`bCo{j05`2{JLC}CqA%N&wt>+Sp^!?(?2-qi2hZTRo(9TWa9uz3yh
z{uAM){%&M1ZEP~T0-I{IfKAMG1U|5{m$8km5A@7Xo^PO=r6uJhtojH4#=@w7Bf9EV
zU_*c5i+kplir1o(uXRhn13dm@rQ!*|iJV4%oH@1mmw}JnGah(wcGmnYTRr(#wgfSh
z|I0jnEVY9D!$KeS=!!ih?#Y4V+#S^;eA?VUya%`DSFySSU&hvA-?wf@Mh&lUnY#wD
zn1w68rFz&0ZEM>oF+%pwVJ<WJt2}Lw;?M2H2lj&E-34MWKQ9&gzKKuw@Q*X^AI49z
znD6lWe)D>KCr4aX^PLok#dxe)B33bU40h7Zi&njneb3IP@4Id;+nF-{|1GC2PZYYK
z|Kh8{S1aJieAI!@J-jDxCK!kE`M0*=b9RS|eGlDkG=-keP!B#K#$d6fg{wY~Z~t?Z
zuCnGT=G&iyPue9nlzP(Sb2o=o=?9_T2Uz{@uL)Ke%4U>@%D1!=#t{0~t@;S<e7Hgk
zL9tk32-@FEd%=%h{QTnG^M`@kHO0R6#rT%+J9VB0%zBD_uVBB2*#@^2Ee<eqpgZ<Q
zyt^%g8FmhP`N)61YEA{)zS4O%=f-G{@0ILp3GID3Mtj@jk170!eG`$B(C#&>HV{{P
zKi_?-0)Cg;enl%jxt(*EL|=RGTixkX_agi}$g=9_inadGs<(ohOSIqkaar#===c@=
z*Y0I42X^A{-s|$i_&P?3yY+Zy5Kl)=46ujZ+F9g`x0TYO7vZ5WhuFN?`^&EppL!kQ
zP4Y)Vc@TV8;=2kyj@gQ5-^aXJIVATLes*$}Z@Zbp<CEy*Tt3SWb>Usv8%vn;=W|~@
zS#$n;?&ajo&f0`;?1RLD=3K*Edzihyz6{J4Do2BU4ofbF^X%ctdA2`X^zm^GU5Tt(
znlc;dEY0<>Z_QSw&)cL=PrSWOW_|*j?4P#}W!QIX)j#!bQmkOb%FFR(2DIh9fd9EF
zw6^^#q5;iq1ozyvRqanSo*S;FWCzUqRzLDcu}Gimt+y!$R`W8ga~1D-uVsx8>sGV)
z1qyFFS$=_Q#&kXheMZ0Zc#qM}bpalOw(4=|En{6D@o?V3bL*BBef*q5XD*lD65q^y
z+RJv}DeB`qMCRexbotxZ$01)nOt2gRze}zuR+bEN-OBo%Ymm3X6MN_LO!^6(<*jFZ
zQP@Yl%YCjtweeavkA1~n@og!c{nLa-Z`T?K^=;L?RqBK$|Cup=Kh+c148Fts`Bc#~
z^K<64*W$C4{eT@MAChbc&p8Vl;t1B&os}cUztHBdHM}WKKH9a8ebCPu=NtL`;MY#}
z!cFC#+}>SqE6Z4ORKi|dXS5NEs|W4R$7X44|6@JuwQp_TRXydjz4y9(<OZnzb@&|n
z*mIuxy3Q#&hn>aVhHHzXBMWn#&IZm1Im_T=eVTU;I=>Iw$-XI$et2Q-2&a#@4eJ24
zx0CNMCg!2wBP>sSee9{)SJ=zkmS^;vy7}&R_z=-8>?v{Df~PJ&b=4!)BMP%C>sS1&
zy1wvRt$RrJSb6g?K+Aj!4cK+n&-+hU@q_K%wtu<7`#FsF$k=%2h2x#ecsm-#3v6t>
zhv9cszh?t0k_wBX^8~9touOEm8;%{?ipE|R|Iz2dGvT<O2*>?6<A$E*wK}J1tyF~X
z1-}OdzX1j=Fn9nM{CW}ws~!%=yI1t(_1HdD#OKWZRXmQEjM=}IM}a*Y#p;OHD3)h*
z7uvtFoeQrIZP&k&?doFx=COYlGasnpQ`_dR%xj<O<KW-po7lfguz#Q5SKwR=vwz8h
z!u}neV*d_3G_o@9Ba>wRI$th6a>mX07Oz)K=WD}lqoEC)&wTiw%?2(%?6i$M82q+!
z{dD*%@jUvkdp+0xKJKI6dhW6RR*qHgxPkLFuz`JK)>6l8;0a(h)Nu<o3;cd`N%2r@
z;M>Xhk_~)&Zk^e{w-?5pl=^D64K^A%KE1O0iy!rvd-r$my$%_CX`a~kH+;pvq0gZp
zX8?P3rWjd!m|HixcvImda(F_$QFyqS9mziUW}`anLv=a+SmHG!8?YnW&<7W8WuK-c
z1FcmTyFxn6@FTrOjC~XNXhZ6|+rrwu>K!g)PiikC!G--nN`;EU_&FyQ{S?`*j5oAf
zS^IvVAKwgqq4Cq02e(}t*u+bi$J{wWo9I<+;w{>X=8hVS<R3$a8>|OpZw?C9N9Wzv
zpbul}!~fPZ`o)?M%}XekR9yUS`!2Lo-=i`e+q~<|UPX^+AB=u-5H81Fy(6+$ea+jj
zSBG=*aR)ZTR>{}mrQ7@f$48sJ%3jRGntDpud8Y<3wwJvgTkb;Qrk^IplP&f=?@izj
zJK~xWw#q4&nXbI?Qua#5wn5MIt>gERi;I01{dMu~Bd{O4O2nA1q%Qno=e-?!hySmB
zRk3g9MJrk=e|Z@(7>l*t{d^zW=mW*R<IW`(_sL@4y`SUTOXv^w=Hg3uhwl0|c2fG4
zTrVgNeFB_aaYV82FK?!vV$hGz65q{STkN~}3)og0i+AVOV?*^7w`xDcYX;~a@YWu%
z%b25n<fLNXIqzT5;tvGhUcUhwPvbt9dfESZ=lr7oQTn{*aAG{nZ*Js2`_~W6em8Jn
z4EJ^yect&uy;FOD;on)x`*XBcH8`V<J)1UOyBJ#U-n{YJyubJRZR_`b-$NH&_#yP;
zdcN6ItPs~5{mIbsQU$*F<WS*U#a!GW{BZsm%tbct&hz}jE|nRpR(j^W5MMrVy3mdp
zirFzkMgJn~81hVr8#3>-{P)Ru=Qf|S;Ch&MW^->qKVRqidv`A$Qol^Tsg3XDeZ}iS
z+JJs)w6V?mU!pPP{RZ?uY3o(YW-FX5JCE`spYAnV?UcwSlx?TDT~N;Kx{Q3lD!WZG
z#qo~71`!RhH}Tqe<dOdR<UGFOPMz^mo^=Yo)|axU>JWRpo_1w%d>im^vFR4~;G6Ec
zD^bz;;Mu!cE2%uWrud_@Mn6T&61d;wL#Ns0`HIh;KUxRM7?^vhO?;ZzT_cKt<2%Kk
zyfcqaE5&@)*Pgc6KRwuxhLZqCV?)?KUD!V+C-$;mrpY_t=8ehzsid;BulhN^GrRFx
z&)<06Vjq}hWA;xCraF5@a4vp-exKm%5<4qiI*g4W`^M{GE@FE-6~C`|S*o=0-U2$t
zO>Mk)G4rlXoa^k@_I;YDp7JW>HS?;(a`H8yuk6S74j+-1jZ_@{*wEhLMZLMda@JZb
zb=Nf?D4bhaIPaZK3+ouMUx=YCuo&98*wdxl0gKI)a&L&@S4n)lpIpzrx9=>D+;Ay5
z0OyJpi<L!}La$d9cfm8eE_!>>U-x!w@(av<)_gc$LH3Xnb?Jjk3KPx<v=hVu@Ertx
zUgkRNrE5Nfk;Nav=d*CZx19mb-WY%uN^Q_fZfPP5-9Q(__{Tp4{%LpQ8^q9<UmM@N
zbRoQfY_%9#6P~DuCwRXOJ$f{BKzwhb#c@7>?uE}2r{=DvuQi`uIgc*}zYTnG-Q1LX
zG0@n`;zv`Zl@>$ux9+`e$uQ%>4y7NX-Vx}s8DnVkUI3iW2;uy%2A2TN7YA@IWE2Ct
zd;r=j5hr~8q;FktFC!y>d1W!M{>hMcj^h+ZKXl%JbMgnU8+(M$!V#5)xn)iXm<4gV
zYtX}^FTDtR_q^O|h|?XJ$mT8vzvc&DydmIe;5Rz3gc#Na#pzU*Ju~H7E)|YaTrF{G
z;kZNzK2CWXwMPMG={#6nnEP9`Q&BtF+;YXB1}@4yO+4ydx~IMODjw)=sQGCPM)LR5
z&e629tMhE=v@dtP<Lg`YmI&HBKWy`9>_WA<HS7~{F6)!U=;+faVV}MvS@fy55nI8h
ze%@8!_h{jk*dO+wBmdh_?){3<36F}=74p<eo8=*F(UQ(6S~(e~yIyqQeULgwKY5<f
z)zC#(LC@4X+v+X+vS0OD+%<qxqJ?+#A?bMUm5)2ML1QfZ3;3=1d|%ov-;ij8I2?Ux
zThIS64u|Z&^rg&cm%^VPL}nbLI2^vzwvpQRwKyDo=Nvfsc(9$i3hQcdIDAc_LyN<;
zXr4Gp$3r?FV~9E32XZg&PkG82CnrR9i|aY_;jL03$9nZ34tJ%=!~Ep<Ek|w_@KyZ4
z`1+XZf$vC;@zIZ~bM5`ezGJA9x$&*EI~{F(dWLs*(H`_rcm<Q;>ZY>_w~05Li%bTM
zg)-=A;!GApHyN}6dGS_w;*#Qc>cT(<A%oGGoT-Su{uDSH1ZUsmTnl1_#80hW_^ej%
zyTf|FdWiMzqTXE>U51XojNF&?R_~n_YdbZMe4-zVP2Z#{j0Jr&BEDLDWgwf7X+|UX
zD$gTt5W1Yi4{~O=hmN1aUat6?kzvGv7|Vsrm8*Ej^57<PnE2@CkdOXNv26I{f{>5C
zpqQFZ-wq<fhpyk?ohmwRTR+LWclE+A-O%-V`7)4U^zVlAB3jR_>A$o-?%~e&UPrn2
znQalP2mi3e{0hKtX`l9nf+w54_g*HN5ZxJHqfgcyEq?ais(4CVuIvKNisK<yl+QW(
z=8J&&h_}`1j>(@`xn9NMkXtFy?v0`BSo1FYAbIj4QX6+Ky3}xhk6(ICXB~q3ccIhH
zEBbE%{|})<=>Hk`eOk%sIbXc4*rK;Skg4VRadt(tKlQ!&z-*j5L;jlGX}XE^H<N9i
zFPb~r+FUC<U#Kw-d21TSC_NO)*e69h+e^?Ux}>}zq)p~Kogc@C2G9K9?bLCJct&UH
zHMV82J}in&HR<<1$Yz=<cMI(EGfCTFT<q^=sE2pp@5;h&*xzF7v*<H<y6EA+u0Zwx
zcgOqJc%N>B|F1mS`)fV3_?O9Pk1=W9k8daR>)gSdRDLD-lRkva_2EA0fC9Fo@sB6|
z!M9~TnA5uPy_jz%`2XP(@fihYe0_gzkL&`;VQjJ!c2_GWU>D$<BG=4w`i5t1>a}%o
zoR45MGBjvDnW*luxtqYjM>_Fe(l2aRa)1V&`8x3wbi();ar<(XwQ}U34O(BuT$LXr
zpQxO*^98hrD*K))hbm2;RpD?akBq|ZTby6et@|L(Ql6E-zP&QPtEG}+oZYO`%8s@8
zJloQXUA0ML7)bi)TJ(u*Uh+OX*8zr#wMfrt{~6%HKKaTc!fqw5x%~v@C_}(+8TmH+
zzR{CuvIi?VDB<0YjlF+6_Wp-_*}Mh|!Cm_EzmQR^=TrZg+uM2{_CU`|S54`6TK%p7
z1KES$psrFP=r_J`tw*_ZV4>Hdeyh(xe<S>W7vz`6+$}j}-_@XRW$FuX8SICQ-2N@|
zY-ns%yQ3WJyzo=}Zd=~<l$ZPeXyeX2Yh&>32Y6Kuhwx%KwXDS}-a}dC-r}!PuBl6Z
zy+;{uZT++JfZIa6^+5j~*WK_P&ga`xD!s_(+_?$Xa8Ix%NNc$#GOhT2y~%sdnApRf
zy?eC2$V;$}momkn7fmp?(z;9P416YTjXrpmpdG%kda*~WUYB~4llM`b#i0aa)2~UL
z!WHd+FK~6@c;=XGyR~LX*Qh`4soXdFR{I!OjvxJL4aS|`&sYv@pID&rab3bZN^7v(
zBmMz7J($(_gv%OCSet8ocl;E7BhCHl{%2HQ1RJe!-oJgqB|nWmQy=t}bR6eHhxz8a
z>9X~8k_CVKvFiMG&RkD-F;;%*Ujh4Hh2!LU&~eVI9~VAuY*3&02@3Jo!gqTrL!A}Y
z3uk__eIn2LWUb57_$njy<1=1phL1l4ms-0XtXJ2$e-EVh_wPyXyL?ajneBU^vkAf7
zaLRSsv4U^myda$FUO1fvPDS^z{~7AcP`CI)G$vZmILkj~UtZnA^JBjZ?nN8(poz+7
z0vPDO<R^X$!*fJOheDr{BmQ4!{K|V${s1wj(tFZ=dhNE|wfoby?RKx)wmVH<g_|vm
z^(uaRmr_~Ln8uNIDk;a$_^jJVxZk|-1X~aN&GVNjx8MEd^Sb@_zsN7Ge3AdS&bR-?
zqHgE2r}~+JZM!pTCU$3Dn*R>Ixjgu0o-jLw@G|+JK4|X<(R$_cr~0np16uRI#a`gV
zsTFDZlG$IKD2u*zM*5}fnaDGPfwyh<82xg?cWM4-Jlfl<{$G(@>69H8d=S?({z~to
zE`F**{Ni!IT83{l_Q~%CvsMo<hYlvdo0S&~4BnDW;aX|;0q7?We;ma#e(62Pz@MpH
zduptou`SN{YksnQVl_X}wQ?mkKN8$q|G`7~Csma<xRf4F`#XLbyf>LJi}6&e6FJtQ
zWL_qmvF?_u?Ry{`+P58iE8R9b<$NX$j*$nH5zVCeUNSI{Khwy<X7ZKqi3_FFCUCMg
zbuZl^xT)R@?Hi4Zr~Mi0{~<710*sCZM*PzE!(;H)>eILF7ECrUCeBbzu~%L_+<pw)
z_!-=KfgAEh_l7HIw*2FIxE+jEu2Nl$C8u$<(f<R$wGFtg3*pMuU>2hhZ(g96>ga&B
z2dwQTa917BNt*f%?yZvh2Z6uNSDFQUp!taIr@-fEbhdbby4CM;oEOv{xYjt7A8TVU
zo&lcFxrdU|JHw;;r*fRZY<LtLL?^K^XBb}%uin)0&xq?M8A}^unZ;Q6rJn)Udy%J4
z2lBM_bpg&zUq6k!!B$Dazoyf=X$xLsy|(E9^|vPx>UNdI?^!FmAb_jE#QNR<6P_7N
zsIT1WQ$KnJdE#vB^mht|8gmRr8R|zAr*`nJsZ7;A?%^Kp`29>arJrV8Pc@9o1^!Rb
zW;iZyIb%W=O&L>IE*g`!I5r;ZSHpOCX5)Dp+iFuV2KBWU+d=!vOu-?27;6dOWipOF
z2o4$gY;poP*f+qZCg1o*FlajdUo-ys;I$LH@=HI~zbE}D<9}p3^(Ff{eoOzJ>7U3v
z%9T1YkA?jeU4l>1t;asd;*AIv+rYcdB%cVck^{CEQj7MFj^X;HfgR^H@RIuPLLUZ~
zSUYMX_jC5<h|?N%mg9AvkZ@W<`D3)GHd|wDE~8EH8+4I*x&aqFlRVhDzki~G-_CuE
zyV-a*H5u<q!tt^Xk&PF9;JrC0*WLo%L-U0+@M8@6FCK{WZ%0cdCHSIyQt3yl6Osec
z$&&XwMKkCXd-sT*vyTJMc$ezn>aBO29q`22{NKsdJ3D9-HJoC;m5P6>da=RTTZ#7Q
zM>@g#8QQID=j5QBtx-G0$#&Avpm^ab=4dv~CDf~DF8Vv+EYy8kXUN((I5+wcY)vQZ
zM_A6v0~gbWdIl_l?}Dr9uEC7=Tar9K)V?1U^t}t17>r~afM<AoLOgADM?~K-8rAr{
z8!0;zJ>tjRK{?z12-#cX6V?AD_4Bj(saHH`bq-PI`fa;g=lZD~`>GR~M~ip$jJ?b8
zJ$xgdoXhz5zh*9Va&7-@bz)09&)`r03Ct|j|9k4^r}`^z#(yljeu8IDG|)BAOwUoz
zYTA^pEnu&YfXkfrnc}(Z+CT?k?@Et0fo(LlI=aB#*Z1P<HDRAKkA<>mL8mV}*y@ix
zlit*`T3=e7)Hd}6UFbcZ^3Y}^OXj6~XE*eUeUcql8Ns80AH4Z$V`6t5ea#N&%VeZr
z^*C_hHzTf*)tL}aUW)sMcJ!_s$`Y?_n)jh>j>eb_@fYC{{b}${OSS_8@|{zL%iqyI
ze(Im#+f-IJ%!m9p_4!V*)32Pw?~G0kv+nf$U(fgbHy!R*E=;po7XRPU=c_MG>$APt
zf_ZXevqk%OMKX3mwk`P4f61IA*IIpXd%1D$T%EK7t<K{PZs$a8YQC;}@w?iKo{Lr^
z*`7m|mfqFrx1Kq%d-a*JJu0@>f8j9pZn6J9X9aqx+rqWzne)GrO1~O9*KeL=EA+uN
z^NP?$<m&hJ1-cXXYaSw8)W+KAyD%RKI#Ygv#<4Cq^s&nBj>c4jHTuh7&DC^yv;M?k
z-)Ltx_NV6%`V;BQg+YG|_B@OFrt^(zc<`WEWMbUTlKiRJ)aaoMKf%wN4WFp&Gd$yG
z&)o2t<UGF_;oLy;5uK9972+Qm3BC`8^EA9xI%Ni4XoTT`{)x(kl$T7k@ifR(o|(Kn
zC!`;)rc-0Miu!8w|4Lx?a`+usc<ZnURj<LMp<bR@y_CDEJ=CYnp#($yujxSkn?8t@
zW6xkKC%qyWe^&=`Ub37rt;lBgv2dQPc|Xrg$8e2gxBL`(ZnDb03F?_Ey)4^>XPY}J
zsn*vZ1JGGXu2whgXdk8lJ=eYuIxCQ}t9h<DZfl2lQ*r-tUV1Jnhib5L8FahZda_Ak
zG-2(9W64q`_YaDV99))_UxrweKPk>5F<DouBmTY-|DnGK8@LxctuHCsC08S<{(<Ao
zz(ixN?RD`VH>P$n<{kVp`>T{4%<gDXW-u(HTnX8KoB6Mt<~3Yb^P3{GfQjg8i}0xX
zebou(D|RnDtBzLnt+(u$4<+>J7;Y)wy0;2GC(Da244<7reU13s0lp&q7#^uZc+~Tz
z_}d@&y_|OD9qL~jG}jjPm3y0?;TLnT1?>HP`ai3Z(pa17B=cDyS3|$E*$xMSZ*<>k
zwB|E@`eQJLhGa`Xm+|+qp`f*FRBorvsHA_JTY_?%sVA_z0w365_+0e|c#Oj#fOF6e
z_aUqeCJppl55ItaB;)n1wW)7~Gw}*OFY!=QdNh3s99;CvKI~<_k8B5{0ph!ov5j*i
zF9#3*so@0frk$Tnu$NufzUD4F!1p9QO#?^DG|Gj>??kuH3660+4IQS9Ug3)xp6mHl
zxDlPK7JbBcYKPG)^kjV<%!;1$EczetI(?i2u0#0{)m6j0e4MJE_oBC^c-J0t_^Vy{
ztigNw8Tbo4TYvdZ_o{C&yjMTh=w5n5{m~CQ&F1AtGw;#68m|QKU(K_+vFU#UuQYyV
z@Sn}tjE91HHaFCxcg9EbVOsk5VN8a{<!>BM$ld@(0W8OmqZ->zbh5|3tQsRai)YoE
zZ%6i${6F%YJi<Nu>NSUNgPrQ`J~eTh{M^4hq1!pH)0e&I{_@KPKf8aDd&aq?O52Ci
zHuY;Br>k(E);yK_vBN6PU~6!{6Z=)qT;#Lqa=y2Fu2)&#{nQq&x_@LIef=+ZCRVS_
z%bV0$>)UH%GNaKhjp@1cIr-hm*YP`@-z)RG*Kke0g5MeW<}xQHdy}up?-t*x|2s8y
z!JT`9JM<(Ni2e=kTy-D8ea)G)$1nYAe(R@ct3lt6;p<3q?p3<g8Fzi|Tm120ykBBJ
zN`G8&PGThEZn6Tth*SL6m&s3RcXVE!dxY0rxp;w(Z3G>6pp#EcxE*g;1`j1l_bl*h
zeAWo7Mq2n}DWHXaS!uN3ro;c|zi^T^{^hnw+PH^%aBA@B4B%rlk({K7<l({n8u?;?
zpL=ACCUnpDjc~jaKShpp5h{-?u&d}RURV0%`P~K|_2;Y^=plwv<|*>&^>k2gGd^nP
zx$H~5*L|=zW@v9s$E(ztCf+MM$^23Btw0~pMK-cy2e9+hb}Mr(`FS<JwRX7bp0y%}
z#H-YS+`?|AZ)&65#8+OMqx?C|6>ScKOee-Iy+57Z7}$if&DM(R%*OKAJ^3Vao*G?G
zhnrB}8GQ;b`$N0{^MIGZ3uPj_#OYA-H}b*c9-Wj=Dl^5lj?)<RS$ke2F9Le6s~h~)
z>PAjCt<&^i<pKPLH5;ggfAycS)Zw3JrvJ_e=VM$m^fjOr`pjI^|I0pKITP+<=-3YG
zo=e^Q(8>AqllZ)!kk5NIXBy+Hd#cJfXXQJ7U!CZ{Z*)j)!-r9O1@c@4W1HLX-1>r!
zj^@Dj?#Zh8d3E1PdxN2!ZayQP**uJE&Gv7t)btIxEIMZ*Xaj#=8hb+Zv_DRN@w?hR
zecuw^?_|E*imx-w3%B=4&E<GTE++gJ*gZR=xdL{DbiU?><lF>y3-u4m&gQx!oR>Ae
zUlYDJTa|L==h9Vnk*=W)kyieI{)e&k^kL!ua9)yT?<~D<lzSQI%YPew8m^^t4>CUo
z{~90bk*KRWA$cj@NuU3F=He5(t^H6|r#;$Zer~xUTva~pRjdzb``={lOaEk-i9aX#
zHJE3}E>j&d&3#*68Txs+8hvPP$uIDS1i2vg++r2M^D_R>rt>DFY3Nz|BRmnvd2rgB
z{#|uXhkV4EyNZqv^y43<-`GgP?*{1_=@@*E!euQE_xFy|3M~=4wRvS=%i|jcPOa2)
z*HQQaxgzHs&0Q5cT!Va8J+ciB<~LCtI)5hjMkhO@D`z+q`tkq1$8juvL>y&8cAVlU
z??jf+XT?q0p=r&V0{f{t(azX%9e#E-eK0=@bRLxzP0PlL+q!zEc#C3A>Z`jb7_-qr
zj6c0MOxGqbpp8FDdog@_r%twK{iW|3+mx}k$Hv+|Io7MHzy+U-@$pP!jM0*}^k8iU
zv4GlGpG$l2Ule08U!ZuNm`H}7=v;QS@Gy2{M0*LxaMtL*F?$jECiV<1=hMVHJAj|$
za-{R4*t6?Kb-_c&hQ79$bjG<cxvf3R`LFm{T37lzkeH;A_Pxm0P}bJj>EScxh4{Sa
z*FMI`Ph*T?(2>oRj?tOkm18tGMYlHSs))CVXY5HrAIuT!#}8kPwTAtL4!pk#a6E<I
zjdx?^-V(ye`qrRZd1m9GK8q_dzY*WdPa?jTzHg;3lARX&JQ|)|%iNRq>;r22X!9e%
zh&l{LTqP$m=T7X_Gn+?o?GXI*U$6&$b^bv5tZ&HWn(!2V)cY7cE50)@e{xK+tv&W-
zQ+<X{aOq)}Xx?CY<eB-t@EgsSb+0wpD*v4O8>4rP-(*sPd@uat>R+w@%KcOSW4xgE
zV-c+h2J~Mxo@}wEGXGF>7bM^5*Fc;v@C}%Zo{2BuuR6Ms?rx-Q)f?9viU;yt8Ch+<
zKk^#tax>zz&$oidw7D7DLq6O)-kptJqptK**lAC0w>+a7-@Eh+IF`fldB-2Z*r1!b
zvB_uII5z5x#^xQtxSpCJM<YHiz8ed9+MCOF;&I@Sq3`l@2_Du~O#Z9?f<?`yZ=9?C
z1Xw%|n{^Q~kYD=YNXP43yjgu64~a&S`Q(Fk&3618`Z>@b8(JE2B~Cv`uEc6+@8JeG
ziI%7*f(var-ig%n;54=Z{V`jCYop9KSPZ0<Z_GxxHfAGSfNc2}$EmXsj_27|firzI
z8{wg<=}pZ?+xKH50GnLK&(`=+bR3qIzO;C2%-5%PCgbsA>idrNN?-@Z@dXToFMaDh
z?KtfZF^_ui@;&Xq-Tg%syWSsXe-v`agWSjr_$u8S$eXy#@~)k(-^f#R(I4FBm^_MN
z+t%m1o@Jk*&q!x`Z<_3L%~lcpVVBjxJRO6%eBcp&fN9NEnGV*H+5Aj@#$o+;&$8d>
zrHt88#3EmGuzmw`;#@VDKifVdziT-L@jj!2pA~&z56LFd*exFvy_6;oNx4XRrradq
zGP0QrpX346azM!4$UNGh!<FA6T?b9q@-7yElkmUtVsx)Lr~3=qK~7cX9PaB`G#@1=
z%yN;UJ}B>K#KA_F{G~tT)<E}aZHE1C3I0o_Ss#(hs;`|mrs$*w=WgZ{@cII5g<;JF
z<~rFn?5~{WfQP`Rmj5vWZPj2%E?b6QL{ky`OooxqVY*hZCSP4S>ruIg&ztJtc$@}1
zXvTRD`Xw6w7U6>b(($I>!Ru8#n_~a{7P+57?jMHS=a+swlKaf<9%XJPI?>z?+K^o&
z`m57xlGotAPF`0+{b=&6flhd)KDAO`&7Q;VHyBg5<g3X{wHue2yt8?g{GegE_TN<}
z`8;~Bd;sc?%RuX2s4oo{BiNMaF4bdp8*tLRQ1II9hVxd@$!RgYARTaCgI+*>dasT8
zQ!)MC&i6K_61`KO{$I7P8srb3?Psszx!EoFD}C(4HT+-A&+ND}Lc13{dBpI8aZasQ
zbre=R)H_36FOJpK7u7}I!uVj+w`u!&+(G)fG*<uOgV%3;=4|O1`wTyt4%hg}sWUvr
z^$T=X$5VxXr<4OG-qM`guFM&X*MPs--n#P3U4iW_+KA~I*@kf&+W5<4dIR0^%y=oJ
zy)ClGR99S&&_D6=RlIA;%keb|QGPQ#EuY;Ko`O&6c#0gfgYrK0h<}>#zHDae8{?fK
z17dSuc-+>pz=PO*_$m|rM8`8#zL}Lz?!{KY)|8A<zK5<|ZTQ^7d-Eqs{yvRgP&N(s
znSE7!bKFC#?bKtwL++I~Feu;Qdgf>RH~%8=w7g9HhyUz3a~oYV`>CguXI6%}bBI&P
z5aHI^QLIew)u!&%PyA#-+^%}?IPn3Evp#=h2hS#bZ-H!hPI2PKSkRBc*w0nRPR4$&
z`ut?<=VRP6mP3jQYTgT8ZQje(MgN&D=6k#6DxU|uH5nH~F3lJhjMZszAoYzov-qkh
zZ8!SUp(A8%Plw?SoIsb6?>h1~w}Yq1_7y#iJsHa%VjM<STq8eqly{U<PAShDb4&E>
z5Al~a&L1+2K{kr)i0Q|S-c&3deik1``o!*mw~d+aZS9EOxAIIhsvoo!#dj@_ivG*z
zW4WKAX}uR8@Z9K}Yo;20qq+oB!Iz)>-!<IC<25>ur=33XOEbTW;t=WISK;&iz@9)h
zWZ=iTcn8m{?pNWvQd?ZD4_s}Gx~g5t1Ab=9P|ke4$jb79$TnmCrnL-DQC9tbsv6kc
z<kpCXWmDK3HX578tLNc=v(dw{f|+R8;HNn-u|&y*RgY{Z4~K7%y#{yMFu1ATx|b}_
z{gd2F=0x|BC%S)v=c0G|Eg7k2Gs;NTgUCO4NHH7WNW3Ri=%QZTCqkOg_%v3YS^vUv
ztU;d4OBWnM{2F|Lv-OW}BN}P+^$lbu;XY*yf5;jefO{zV$4$z9`yW~}(;fEF_^W}Q
zd1gA}*{p-fhVu=@Ho=d^mI3c|J{HlB=tX{5Xk7SdDl4YZ{RUIf!hweVik`v0(Pu=n
z$c|N<BW?U)V+`6YXIK|2yI6e@t&65aTlx=Q*XSQQ#HO(4#s>}bCEIuk%{0juIwZOm
z-9~Ncs{bJ$T7UFkJVzgm_w+yHN7M8AAC9}$SA)}}tcl8tzqBUa>Pl9Cf0J=EtT}h*
zt`2fB-m-jB|Gwo5W>;)EfJ`D6NAo4gn<c~?O$YK`YeNnG8Vm4~A2&&xx?huY?CN53
z2zSx<vd45^%f%7gW!E(MK58e8e67jzMqi!rF*052$s(U+wcq4$WJl(aGbW3n$vQjo
zG~#aLyel?m@eJOV<NnoC4~2&UJ5y_Mir;n3zLE}*?Wt#~dz@dchcVi7a)T=|-Oe-f
ze}(U4r)>`7y*0m0R7Un8_eL{eIoV`tW0lrm3YMZ3ei0A4xsY%1#oK%F0l(<IcvQOH
zQ_hjTm+a*if8Ugb8vNmu$*1wTCe=US-w4;bIML|`hifbKH0I|<dmv01<D5x3@2v!<
z_HCQ^+o_8~lgnkg6#BCq`-V2s=fBYCuuhLa6K)hI;5%;-aH1a5UAi{Hj51Mq^@BaV
zQ+I<O&Eut)o5r)m>%0qc*_aD2#b-^sk$!6`L)pWhH5Il;zr~?{AJ~}b-w~@~UM5>2
zgASj<1Nagm9?*M_`F|a*cwdWY>HTnsE2E1Bxy&=OKPb0Z^v*bC7m1$g;#KrV&n;ec
z95&shVZ162Pw=hehUN2dZ!q8*@sIHo^eq2ZoE{8UlrtE;7QW!#_=2m&we(;3k*)&|
zHM@-Q=^Od$wVu!318c$CXkPG%;##UhIDa|ixNq!J^lVT($9toRkiXcs#N@enS?kUO
zo7@~fyIH&`n*bZR^13cRn6Dq^xGsCJC{_j@{r_Oi8TCalRc@I6|H<JL_XR-LabJLZ
zq&2vOdui0o_eD1mpU_vq&HN5_ZL)Vrqp$6EA^kqOeNTt{Yv4z1*3qvEOk@5vwqBW}
z-SAx`zb#G@t+R=~YYk=L3z)Ylx6SCHfu?z8GJ>}2@GTo7dIl~{rXNFp>{)|M=b7<&
z_^zo;kIG1<b6+RZ_s3*9@Jq+(lkwMNI$I-{tsldi;3GUKP7?Lk@|S7D=u@=H&*(C2
zXT?9FJ4~NcQpz(X$0obti#(&8`3#`x9nVx_bN`CjFv`1;&&>Fq+>!b+q0FNWD;N4N
zRc4A`p|0+jUqSs;8=;>rp2uI4F+Gfva<-<@WE8SyF?b34uD;3ci`Iyk9B$}S^h{$_
zdHR<PzPUoV=d7un{664g>ZdL7XY_5YpTNVO@m~4air1?zJAk$2oN*uN_ga1!&y*jg
za`p~;C92nQ#CRU{O|rX|BgS*f5#zcev>6)TD@Uy6`&WK|+TdB;x}sYBmHON&p05Tb
z8RXYYxmDitn&3cw34>8MF5xlCnF(Rj97p7IS-Zh^(YR}COhR0Mmrmu)TfQ0ntJCxH
zbwxfo_R^Z-lY1=m$su!`2a&bnG0AU!(gC&Dj`=ei<O9!4KG4SM5a!Zt+Z^OOa>nea
zhzAvq=DrrI(K=SX%ls~!H)$P@-p67$dT%ixu8|KhJquX!zn0&JK9xUQeQjzRG}vZo
z`8wh@SqnNkfz9_0`h#q#ld*ayd+;p>x6$-%os0yI(X+wu-sU;<y%5dSz^(ABzPk%)
z=ga^mqWj2}%_T#5bU=I;?CBz1DgU(aEgG-GH~oloWnsAkOk(<!u}hyu{b`3M>+Em7
zHCb(ALH^N3jZVXNdKR}mGRkS>on*G&so$$+h4y!-|06nbbBwWzF``f7wzbii;`z$q
zu(th4J27lGXan5qTl7+7!_@5YLzxTh>z}m6!EIT1AD~U@Yl`=iLcH5J8fc$qW_$B(
z9PcKp=<}fFf#JL8*&03L-D+f-WT)v(_(acy$0YA<EhPVwng{azW^knUJ2hA4{}^)C
zc#dbXH!bH`ehA<Wtp>U8JZD&)*u712tR(|&&BSBaQqW%<7d3dseTDHgGUUHfrYA`o
zk`<Ck)2>_Ny<}z-uiH@-4LA7FdDhgA&bOPRZ<#N|^_{gF>X26YA>9$rC6@ls^Y}B<
z9btb3`#RmgbJHDMo9YgpOLwT<Df)tEfn09T7d+S4g_oK1h5FenPq;S6kK-X8kBNMZ
z2l{P}8qu%G-lSu+Vl)Na2&di&AuWUN%)SO%77fr}=_s>{=#%CGwS6^Mo2~!yr?8fw
zGXw0?F1COJEka9CS@~U!)+uZIWY{;rO;_kPr#+{1FFxRE{u^l8Y&19E!?9U`T`CzZ
zc-PH8X={of%KX^O{Ww?L)tT~72K3osx~ad8-wh70I|MjrZme-}HQ%=8PVlVFp_=rm
za0+r(HniZkw*j_1GuWO@of<p8!m+@U{{}x@RVQ!|e@j*xjGnBTOl@ZzUt`T~hX3Yc
z65J#cRF}%M#_rwVzWs^nM2CD&l-VL$U@T?H7s(LrZBD51?GM_}v)X)$dz*JE4$a)#
zau_tH<hj}9x(XiZGcriBNqsha@vf;3K3Fd4{(kfQPoZJ-dPKwW_j~Ven4j~$Hb2+<
zcOOJv3uct7>BnaCbL^hl{G2_)yw`;Db8LEjTZ0q#1}Cnyxy0GPNxURD>nhyxUi6(2
z47oQLa;@c?3YNmD(N2he#-(r42bh<0T!6ig(}&;^&C69MxbR-c*rn?e;oO;Ae49J-
zJ{qsho%#PK8$*m9YIZhytS$#tV~Xa?@wu9C8O@o)G0iw<j{BeSABg@AB@SV@0$!qD
zlS86o@lgD~_=x`z??iknI&Z2Ue~15RE;1;Jr-d>IJ9<wfhcb+H3VlOs5q+C%@*C)z
z_YvRP`}gubn#YT;^?hr=*Y+M?(u^?B7zOhLvP`_duO{O~-+K0^knw`C*-#;U({JMm
z<b}5y`o<=%%~9AVYRVktiExerTx)Zb7(dkJD8@t6$Y0u+GDn#Of6I2_U1oNu%fh~C
zPZ5)8!a)dQTSuU>PfpHRYGqm?JOq0T%{XtNj@o*p7|%$?HkF@^a~O0#`0hde20mtZ
zO1gUreNlHEef5R(VYqLA6VD<WAd(k_rH;+n<-0Zi7i*^!UxX$TH913HBxl6$*q>$#
zM*aZv4{#Qh;C8TYB3_UCvrTR=h6w&@!{(HY^h6oalX&2e;5SWd#B8T%&Ier@FHHw4
z`V!dZp|6+x#Yp~U@cn0K!{jgJ8pmY3dTe0t#O2Xd(%FoyJxQImclP$lxL%BZ%Cnfa
z9Le|M=ho0BJ5WWAVUs<@Rr-f_;%(u?Y%>0vO=jN&?`t-hp2;TTYO+v$HeL$&^^XeI
zHGg8b9`^^rRsI{nBh&%HkJ+tyCc8^8irz_9DlXsf?4UR}RQOJ_4gq}hCXwSNd*IDF
zzK`hlt<Mt9&m$L>I?sS!lyg$^#bZxo;`B^=k$jLnF>Sd9x>wzE1<TMLFdjJN55yI7
z8r6HX`W&uv|6}0IOC6lIGOY*UA!wp0{~apsP3AMF(fX4pKWAUR+1pL=eR7Cz<J$(=
z&NGui$jQy3VPLjXSN@MNFEhE%GgtS>yFb{cK)oi{LYY;wF+9iOK(a9`2Y@yutIX$N
z_rZIUgZ%H1Ornl<$wmHe(SO<1G2LI2P4RhhV@}<B!<@Qz9X}b<e;4~ZfFp~mzmI#y
zZ8>%FQ}W#AM)Xbht{1|HGIr0kY2IA8UOkO2vU=49bAZ}hzR^e3#D>*)Bm7Q4*V^CQ
zcqMxX{47|3!zi!7_QnsN)#m2>Hy>XEe<}}Q%G|nPFLU~l@8EmMom!kU>fh2s=pS<(
zqcyHm=G6`T5!@|q$aO55yK-;2qM}{y>()Vr{8$$^rc6_NU<P|Vskz5~_zZfh!$Z;u
z?Cq#8y!ZasRC|3av=#Ne)~n2Dk3&Z)7s*q>1btl}FQz}W`DhPv8T~0c$ksRVZEY^c
zy^Wn~68f|GCigbq<ZAOx{g39G;IWqb5Zb&p-+U4DPru^&-{u+7d{cD*R}Vcadx!o8
zv07|%vv+tOjmPGj{D01UjPd!D`DDD$(R@;JhoAXScwd`OhJB7~%%(KaMAt&^JzDeE
zL7k1d)_Bte&eS~+(u8+mj2^;w<>(!21Zs1)=(~_syt6|(0j}~F*5zA@&cU~A&B)KJ
zb>Pwe8ej9i#@C`Neg+5nCwlN+3|^UcMDwh(wI@nrem1tF<!58N+B{1<8KaZhJPR3|
z+1Jod$z}DEHm1z87_ZswQC}ouxsU96%URUCD$1c#EJ*L4&74Yot+QF1#Mz(aJj!q^
zz6bvij!hQ-5$91g{&^PjsF}WrXuNUGp)o}8e$Ml#hP{*0^x60VxYx<b$Oc_;2z1T2
zk-R8`bEwAgneQ=1(?*B#X|rd$=9&RtR8!iksW2BGbNGyUg1Ha>YrJ8!8}NqV66Ub_
zV{~4g>o=cAHp{Qu*KfSpbo|WmO#WNl4gA70!x4PDxus$>X7M5ZkD<ejmxMFMAbG33
z!Od4ut!kcaInvUB1B&wylW7h2INAZ6H125Mj9Q$BdKK>z9dyX95x)W#!D?E+Ry;SA
zJ>g6q?nNG|?^VW49d+Y&;T7tOc*TqIZt3T=a*gt)uc)gg-&BwOKT|cl*|_;1(TT15
zi@#@mkF^`=D9M5ty-cxd8uG;$SDra?k8;Jh&nA_F0=x}(z%BE11MYaH`dcYi9}E3T
za2^rw;=XZr4)gW>$bag$m>+sxa#C?#wW;Tg^+f!ubFxeyBM&7Lg{uM8_Y1}h49qVR
zmBCh!k6C5LQk0pXP5P+#*iLY!d&R^Cx!=K0cvAkv8tym8{wKL_?2~fLg7LDa4YI#3
z=1e~n1KTNj5}vpp4DS^KTf_a1z16xn-)jEX@@24V8sE!jv6}B{u|t(_j2$-AY5pc)
zu{rv#A#SJ`;%aD0G3_MxjX65{--<7p_s~OqoKoYmyc+2^eg)S3?a&yj>Q}JmYGa@E
zUu7(ZCM;*U8V%oBzh{GI>J^RayV@9{92(w5dmO4vG!B*3cX}tBPWC7GAB-p5lQh-`
z8&4ba=96hxW8>azbMdMZ$REWN{(n72#^OTnjpGu$a^DPM->tu^)^d@Af5ncChPk(x
zF|ZM=Ek4YBEB6))7LQ|N$~G3i)$O?)^Kmq_HGf0App$q(iupZ1?X8mj{pEYKw+iy7
z&*V?FKafAd4g6MT6Y@;@p*9B-|MNd?tGS24|D}Nc8)ZxGh4^|*b~VW#Q9Yth(XGWh
z4%2$mJsJ9!QA}w~pD%do`*e#l&Kzu<`L6aHaM*Kzx%1_Wfpea&=1dV_Bz+_qRtFz^
zHPYc)n_x2bDcXCgVT?SpF<L(-_fxOsB|ptK{M1LaAwQJCASNdzcbmfhSHS;p;6ESu
z^Q(tHYa3fCoZZAe3*<y~kRR1SUXt|PjB~j|!N;0u@WJ_(hl-DO`U0#|&2dtlXy=>;
zl}WRYC40az|KrNOa_L}Sh&=vc&I>afW&f;k)DYK~j<&fuc&O1mcBU&mcN=g;?`83K
z%U@C!?SCnxt(o|TZ>H#Do~f=zo{40L>Ei}oGhO?)&>wtJ)5i^bG@w3xC@3RcS-*GN
zq>o<uGSYeCBh}eh9#XeGr5m3|wwSF$<-5&MT@89rbxM~NG`9)wEe{(zvTi@^=smij
z_CDHAdk%6HzLRZI0Opx+O{D6J)^S=4jQ`5ri{`%5o;6@HAmC^JTPc4=+e^F_#X+&9
zbgy}El52)B_^<Etwa1-3<JyQ%lOY<n2ffS+VF2x<B}esK_w2nF?cbnsnFCdxb9O_r
zQY&N6Jf3+xJ8Ocr;k)p?_D0oz`99+Nr#8x{I=Of-y<t9zAkU?a9~x<&xxU71w9UST
z220rn=&m|F!n0`3z5`m(dT8sP@k}UNdFCAx@{;L=hB|m=a=IDMg!ED4nV8Hrp3&Mg
z%GB{pj1G)vlqX6V!EvW_v-m0|<AFmU<KzC{CbA=1-<mYN5|bgKar!<G?%|~Ryl8$u
zlkA|LDYAoSt^B5y9kXexL3XI^u~Za0rtR=dD}zZ?-ryeKV@i4DOoAi#@Q_CpBiET^
zg1y>`!Cc>Jt|fihR4+F8MMY!jC$LM%V~FBSHQB2<8n#b4gqs(w51R>Q;B5-bc%~T6
zv@mOH0yFvcLYR3=g7F)?qOx&##mfq|*f4h9888qW>drfh!;0?)qBhzmVVnUTlFPNd
zw7|FK)Urba55c!7Y@5(zq|b~$g|Gb$yv4I=c}u*?uf|(3o-KExYtD$lrHOrL{HNRt
z>S$#isyT?xXDFNqyzLq5?)S&m=JCw@g|YIsj*tJ*c_F!@f^YxWIg&=lF`U-POk$O0
zOOj*INbj~Eka!@5Bjaz7WMyM=#06$e@z&rM7Ec&29Ow`1!Rh3x;1toj;2+KRd4_)`
z@bRn9;q%rfgLN*sRzF*NpKvJG-<&^;UPAoSR@`QH=Y#)M)J>V1Y*m>UeH;E2E2oU?
z2<^kPV_*Fo-R73OU(Nf-CQ%vDf0VN;Tcq(jo6kzG^6j)Xh}wnjx}dqJoru2T_-gd~
z3x7@V)Zp7S*+twsT7!8|9s@R0WE0O?`AsXEBEE|8p7~~UE*S8x!M;J}8|=Y7d$K2F
zi)V=MmNrb?n{V2&9zt9$cLICFL7N3~7!Njf(V)=)eOCT{gj?B@h8y13(Ew$p&_Kg?
zH5w3oNA%NZhw@H7K8raBMlm=VPecFH#!h2<7GSsi$ek7J&q}{~>2qI_x`1Dgd|9G}
zB=Uo6R{PY{bQpH)KpI|IioHbnCFLD<rp=PWH0~?1t@h1ecF97gtDWzbEF|CK{rvWp
z5*oi>o$KTK@gqC9c()tuu>);uy>s;3)<aXi(wp%W2kCP13Ef9m#a?BrMsZuk&4hb$
zOCDq{`ap*L+cTU4@3w~Lmro~?LRrxp&4c78Bqnt*{LiR=o6xw?@3YV^HT@9P6_e#|
z7kxZ2;FoCL5b2}ZIa0t!ajUv>q<9v|3;8kE@ZRzWcy4Qj?3+owmOJuKsGFdT$QNOB
z>oT4udZ($}dbazxao(5BMO8m^CK+qC2jjK+<92YoZv6K(ABKI`+}4oqE3GrdR6lh}
zjs<?8Cg(BO{`>e*pikBX=sdbT?vf4P$#8X^{~~y!Ner&ZH>Fj5zI0w)J56&XXe->8
z-(6UN2Rj_C6JD9}5^nae?$YNnw3(>oKwqZwRpxWP%2yWocHeeFcj<i@UvN-+(fAg$
z_)hd+@4S}>_**h7*xy0^-Sj(y_3(Ai-o>-o%=>`Vl37k?%_n{tYoelO&i`}VRb$!O
zyLU(L!o4Hj`4xD5FzX&Ru{*uLT9bhp-7DWkxN^7(FS^=)-+b`3_xmWzyVloh{|0;m
z)^@!9E3!*ko$gv6zWV#HEPGhAI-M(1-*8;#uE{?B)8zY1wF+I$=KD!lByWFVr`iH$
zsU%mmr+b@AQeHH(;7i-H2J@Ey|L;Bz_<z93{GUftcKz!wGv*F{?LnE#PUx=u=BS{|
zbzzy2hBCuZ8F2aq>bxayxNb^gjeAZ(`{)FVm%K29rToG#l77>=4Z#$6*UgQ2rt$c{
zf03{8MYJ*_jW)(d@kONfGk@B*o%58cwhxrSXbb0M%V(l`xfi_DALT2kfAXi|TiA1%
z^MQnW)!&_v*@umQf2FieJT=WeTjKQ?AEpzfJ?R#I5BZ#oJ;u9ks6*ni0e($mhX4oq
zN<R;PL-oz*ExfnftMI-BI!xdrRT;Npx@wB-X~Y5jPcx34*v-acno~h5(2d11A8+*?
zcX*h+N&M_e@$Jf7cjdkozr1&QFees{fRXZDg*W9X=6>6sa@|rQ1Ad)F;3+CYJJQe2
zg1nv0y#x3but#;3AIs{0ajx6Hv&Bd6hG*GNV^=oVTImp{!Wp{R@^$26HTe<vSRM0&
zgLm;w>3c`{!TPwsPxc432M(;AKW2OJwSC}7Fmzi27#q!p|J{~d0c}b?D&7k2YdjzO
zX09`2`(EgMYV68X?)Su5!uO&p(YI`yDfH5CmW%O3)DP+stwi%t<00`3@Adq-*SUQ{
z^N&NW&v*tMq_bCBWRGzbT|?7$rU8Abn=5?rE2&Huyu$c1UC`@7aub@AX-x-ZTGQqi
zwmk%L^TM@qd>74+g7^9#$WEi<GXpxd`wIe|Q5%LEuC3<<d-@3W3+~;X4gNb_?m{Qw
zfAdu2$!wih>xa4_oBkrQJ^ZF|EIJoHdROD4_r>@qhaKJYTXY^UP+MB(9QHpi{_x+{
z<~RRFdNDY&PHm~I^TerER%1)jPV}8@=V@)_*xEDJ=ln?L?r4o*<kw0+j=W<|ZgWoj
zW9etW6@DC>ix8JL9%vzcA{^pJXhr_m+y=k1@glaLoj)6UXMXkAf6coUpE4W`1voM}
z(Awgp_d+}S6VB!kZj18FFDAC9Qph@;Ic?u;4ZdkCBRIN=Qo_o7I>3YaC_LG-e+<5}
z`+tkI`*YT)P|oZMZ1JzLFOP6Dwf<QPmmKbNN@ruE<kM&W#_~tnkwcATwO*mF>}!Iu
zR~<^(*ZyWoeToORwp8lsOunvpxz!Ej)=X1wb3?hoY0B+rD7SN(a;>cm{aZgx{~F4z
znWo(4hH`_`l-tozZs#=RTG{U*j+5j$-~{^C8OBBv-=2=HLLK>o7;mqKX2cuto@k}=
zgBD+WxcR&Z*_?|O<(;xS(O=fPNUkh7yka(;+0W;$=xn4J-kUwB_nC9QXlGb9mZ`~^
z$6|eX;Z%O9uPYd5(AP=XVf}}%o>TwNJ4pY}J4pYNM@`xrEbea{XI=l#3;S<<o$P<(
zH;U(w(^ZG#j@R=obA=pnpT_d>HU?k6V#fFB^H-#_S3_eRnSJmjxn^;?8l=r;<**U!
z%B9bzZ|I~PKIX>q@xCSBaFD*e@gVOv9OV542YG+tLEc|<koOk@yO%bB9XhxXcF8yV
zW(q9K{%(Zb8>cDPfdBM{Y05RojPwQ5lxvU~=?kYRM=Uf>1L=#VDMx&?uH41Y0J>Cr
z>`$cur*o`Yb!z(NO;hWP(@FZx)6nSts&rd@yG`oKs9YnQ-yHCsi=H=I0A8}S3S4Dx
znq2@5+cU22ES_=InCux>E5}vilZ+hXs{7;|=6dK`Jq!Hxw2y7D!1+4+B+cOOYn+4F
zd^YfH+FVL&#IccWpMZUuuOm;@27NGCH?s$_N7?+!?2x};t*dO<0`=${2YZw;#qpLo
z8~Ju*V86z3u;X=KG<&EJwXr;?*YwLtu{Ly$O<3mu{<;Xq(uL7;<yJ+{rTg^UV8yi+
z*valPJN6#-^<}*Fj;qcg&s4E*zrNkz*wiP`u+OLFamp2_+>!M)r?feM{8m3a(r@~G
z%=S0CzcvqSsDpW*{9l#1i<;NdFwZgkDIcD3L~wP1wc!wXk!u0wyt5qn_?RPjXx!{`
zEIb};P8Dyf&bI#?^OPCdS{>S^2IFVb*1Q1cwpK3eyJ$3`&$>3Xh9fpU;a+%Yg^msH
z8t1R38E4}<s{Q@g@BFIJ^x~l2#_@_bjOG=q*<YQAXf58qC?1i~Jd=Ldd_?wB3;cmR
zh}H>4G%DVy^%r<9_(eUP*1_=yF<OoLY~%BBXbibf+iOR1<wfFa;M7W6Bi!f09D&+A
z7C5c+w>z2>DZf@_l~bVd7LS_a*qpg;F5T=KXj0#3E+M?vm)}ksK|kbkFB2!W{5x=_
zKC1k*bMj{~KFjl_|6R@|8?*9pYU4<T{i=Q)zi~LuXWN&Cn7rnN;F2>yOtv`MCu=jm
zGmwY!9T~jw+m$J!^XJTuG5QUAXRzfRe!MB~<m&@2Q=X3tf4sY_uD&rFD}IH5hM(cO
zw|`>i)BO{J{C0%Am}CA~nK(i=xU-XI8Tu|+7SU{OZ7@ImpB~G~d_X6H-!_exJp^>W
zLHE#>?lqQ`%rV_F{@(T%u=_K)w>dM<U%@@NwdZI3J^PGRq2)@J@9-7kUw_pD+2B3*
zXFq@r=-?O5VO|^9-KLM;5$Ge6rwd!mA8hMX_akfIXVU}HCAx=>O-IYO__eIR6Fr?F
zH@x(ZS%1*(`Hy|Bay6g8xql`wPX#c4ywyp#!>R5{C+F5;cVy<1-@)AP3i^NN)3Os{
zaJoEzQ&dj$RDAg4fbWo@SFk4RzZZvx36IF!_PpWlny`P8XP*n_q9Odv){#F0Jm%K@
znczVA^z>D5yOVWo|DCYIZ$GXaVc^F(a3TCY6@%Zozz-Uabd|}jS&m?hE`;7MKhk&q
z>ePhp{YQ`R&A$~ZZ*ma56O}K0LN-(ItzW7CHmax6ail+vPWrRKkNEq~2|u^R@befp
z3H0p3$FfZ{XVgBl(y59KVLvCzt>L;`a8&u&LSMA6yw%*X)A0AMp#DDx{k9UmHM>MP
z(_z0eS!B~vbb9Q6hP;?a21#aXp9lFwb#Hq~K(lraE(_>U>0{}PG3irc6dJ4abXhtQ
zJ)^RU8%eM0{_Wfs-Z>4t?g`-Ky>+sWo6SEz1B`$A=L6&07@NVk*x3I{4aPgd@sy#b
zP}Z_PA3Xorg%&r9a1o4q^1IdrflV$tZ2azj(q{Uzk+pj#dAaFavSAKra~;pO*k)u?
zm`;O6MW>PjviqmZ?`E*2EoYti({%N<?w`R%kMBLA^>D0>M85apH??!Wbl#VqCC!H5
z{4ad<9m=JY?bK`>@U-^Uu=y5wZ`wP9IbiL~sk0fI&Q*`*VDhIZk2-UJIn?9ZvsYD-
zf!Hist7zq@&)tUIML(F=VJGY~_-sK(S>3&5M{_khQ;xZTp0|@<8P#F$)Q50wos}C6
z%8BM1>%MB=46ur?2{u?IfmN7;hRuac$}0zvYgW1EGr>sn)d)tyyI>?9*1ce4_rM0Z
zW<IAljGFaZG-EKK|2FpVL4$?HWA)qk$<c|=KR1y_@HfOb-%n1Deh&eUg%#jwwjx*7
zc73?bzwL$_oq<=6q|&@!dE}5Yu<#S9G-qL6_R6arcix9nY0mPzjCIrlXI!01{}*-q
zk{|ihjrEMBwmNC(27jBQoIT0vHCzW=-x<_@p6}Fuy$3gC=22_7-sUhbc;lB14(@**
zq>sF>_3_*ED|@{&aQ2O<^lqNN>SK=Ewl$Uh4)-s=hI{({UGC4^67>Ch+b7a@gO~5~
zyNBPs{Kom+$L|OHe#q}f{O;%XV}1|to8Y&npB#0@_LH#hKMlvm)yAg(8k_!WY(ERf
z#<ey!o$33P=3`rV{>PoN;LrQZvY&9qJ^}o{O24~4%owgorT>X~7{l0H#&i4jiS$4B
zPq<&BuEVC{U?nge!*)o2lRQM`ugQN8`@+@w%5@C9?9_j*$!~>Y;p*N{HJ_d9Z6mhp
zNFU^p709X}w(D*V-yb#2d+5h#>fwwpJl5_RSMC0W*!||o`_^zSJiUyCj>DXo$+GRl
zoX9Wf%Ue7~`PJU}j&rB+Tlnr}!8<*x^BWP**Vyd)Go~-2SbweDtEMkE8P5;vJZJi{
zt3zE~t9QfnWdnU3>%&{7FT10$-giu2Hq!gGK3q0^+0~(qP%FDJD64#KXvp>nyt9g2
z3URpL@1xv=P|qDC|Ihp*l9&7XC)S*o->tkN@7jcO=Ygqy)W|0y-BkD>>okxjw*GB1
z>vpYuY#TkJUy(gyIQD}+yU8F|BJNKQzKg;5>Y%Lo)88G;uXdn+<-05p>rnl~W6k!`
zKD<`{$Mfccm+b!kxO?+Bxvuig`*!#3YFRDGCEKOj-pVCgE=$IX9Aw!vCf%TRfD9xg
z!<&%Z5Fii|mKg^Kn+mIhl?XBBg_k&F6XXqKvM|mY1IC#d6{r<CiNgpmAP9k$A(MnS
z*kIY(x>fW2J?ETTr*7YBNe-Umoj>YR_n!4R&wie>+%Ol*@%4MIJu7#YD_6M$UygRR
zr2Xw~E4KS*u6$g#w2ytR54+bA81Uzk9JaWP1FpU8!tq-6SEe2x&{B4!PE0Z2<MxwX
z<krO%tp6`Zc)1q5sLn#SchBHZQr%CT+o7A{!u>ID|4pr7@TPkB`9{MOe1><{Ulaq4
z+sJYFP}FzT_e~pH0$p^Ej&EmMNb_yu6B{ln6>v_OfE&e`^v*ORubb23<-N2(`}&KS
zUogJV&mtZ>;b6R-Sa1IrT<pVeIJVYwmD&h=V&A9dd)4+m`r%}vxtcq6xFbw>WDR8~
zUGstKay(q<>i6Y0OY*t*F0X%8Nj_)slusOPD1H9#ENWl-48u701|HqnKmI(Om>+N^
z=~F*ou|0d<^nrf)yWYVa<8K5zWioX-^{4%~nZpV0`m-E;`f#{B!Xf;i?@ix2^epiA
z;thuTf9Kl>>CHkqadInvRUsX|*`#)!|1*8<l;TL=L-%}mYW#Rx@gokdQ18@u@%3KZ
zUoY^f?oW*IyogVK!PQ%mPv7WqrF9=a9@mcV`*xS#&*whxJ)wQ4A7mr)wHWLKF)jPP
zgwi#~G*~0Ox#r9NeIn=}yH9^1x})R|9y9%<x;HCUZuMMDUphx?C5jIyMyE1*7K~xd
zam~-W_1RKC<Dc=D&%w`FjjznF_6U2+WS16**`qIO$M_xPcVx=GVc$0&W51csWQO^j
z-6uhP#hCZ8_iP`wt@255>C5b$ck>W?|DazBdepb^yS=rc?9s02o92IMO{8Oq?eo(f
zG_5t8uB2^^uTM{Z(Ba?g*M0O!S@mak#?!~W@2(h+-uv0n>is$&!+fd6x2Z(u$<Mg7
zecU^s_xsVM+j-u1oN=FE3|G<KiN(H@{G^Qg71-Hh-)JoQTJn$fe%qgmn<y*8zCz%%
zGuI{U%YWQE&sYy@ti5=$$@QPO@j~xp-|;=}USZl0{WTvM@qS5mf;s4cJrlYIrLOOo
zS%0is<n2bb?vt)fYyY!rbK7oh!gCq;%60PBT-m+gDNp;ROWPKwJ?7FfV#t|z;}0%q
z)i*gfWD9NI;!)bhuIXI#qWB>3XT=9+681^+tk`aNR@^o`TikZ`xmHFoUyW1oM7x90
zKW7>5<Gye5a=4RAoqdYR>71=%cbVb>T6Y+ez8@Y+S6%Ax;?qO9_HZ)P`m164u1%0Z
z;n<$}&mM8MPdq98zj<=c#0>KdoudkQx>I5QN%mo!+nUh7&c^PC*K;^8a&YQCDe=U9
zY;Lcv#$z$_2Ibwkg!O)0UjDMjy!=7SQe99ugNW=Os&NJ}UdxkAhz_=n1W(<}yXGJ^
z?|+KquA9d}a{cFd(qadqv+$wc>W=Nl4EC&UGUC^(Xgg!=s`W<`t()}>PiIHF?o5gJ
z<pj@_PW5*3_8;%gJ)67S7(Zi=`1#px{LsLiSJhd3@M`?bzj!3{ot^Y@g8bKSN|=`;
z_t&4{c;M&eI`~Ut!>?<u_0OyMR*u#VbVofg7F&<gm`-DSilaLi!4>Ut@6OU={?Wpi
ziC3A;UTWNbj(*U%wH8l*HTX_=&H3&Xu1)FIFo!7RpW^uuXkzPeqPg^ke&PlCvUK#U
z?LDHL;Y4_Yr;WGtO!?fOxC)p^+dtn0u879J?s=Rx(^jj>c|5nrK>R}e+^=BWwzU3-
z7uOeWJ;0iU)+@AjR9f#(%j!)XO4<K4`Px5ksIINAmz^Oi?8TA%Z09GQldQEq#wPQx
z^Ghz^?1i&Gi{|p|c`@9Hj|=O#Zf_T|^Gepf#$0UR_HF@hdmQ}gSKleWT{Jn_HQDHs
zThWY|`t+wSXl<j6WM@17YEQBh<Y&#pj)zR&k*~RN@MmOy2I3+*2aBz@@6FeaV=GS3
zuk3^1(l79e_Bd%hyT~iZRp*`Ow-kF*-2j((STZ;LZrPB|&@A`8n#~|h>jc_MTuR^1
zJN#^+y||6G&f9QTHRDWlCz0Ar!&;VLFk98jn;C8qQ(|q==au&LcdjqdzJdW1-_kBJ
zBbsrB09m|dWv3j@Bjs?KAH@FG^f)$#^>e{F!(Hg{*qeVhRo>>vWo8eHV;@MvqTDl9
z(NKP5PDk;nexjpz3OUc|DE`vE1f$)l=~#-xvmMO3vr+tF_=5*?{GC4le;2rVneiMv
zf$w0tdJtb+Q;r+MH+uwQe77UMFkbu86lX3<=<vA#ba;AsUjyk-+-E5|#554z^%D(*
zYw#`_+$_3ai;M<(7Ox^p`|SA)Wr;e^K3UK;UY0aJStLsviN|QIo<4>9GW=+dk=Y(c
z*P&VPIy-_ts5;27(HNP(8JSUi;k_(>yU(8)kiXC8rvvi!eLJ<U{$n}H`}g_kzbt>d
z&sYCt`TIis;qv^^Vb}l6fc%?%zThuwUw14T`~&Lmi}KsUi}5=;;_*xUvizHUzQM=2
zo+5qpU1;^6s{fMweLkNUerf(_>iZv%f3wdwJy+8HcJgm8<InH&IshKplDPPc_|*LU
zAL`|8E9U(~FK=%#?`6Hbk)cAHuj%D&DdzohFK=5hZ(A>KZ!vFIFK=YH(BH51^0pN7
zKG4hCR?PduUf$kf-bY<t+s}JS@w%s1e`KTpQ-q%_#k>eV+lqM+e)bmg?vMKO@w=Rk
zU+Cp+Ddx@f^0pQ8zUlJ9IEy+gLnoE`!o|6i%}>}1%bde}--_44(!-3ye7Ue!&)Y}o
zW1YRtsB8Kd{#4zOh}V=S-$v`B&8riWFX<Q4f8<F&Zl|8^#|{39$*1I7?c%S<x7@$b
zrA)~j>aZKX$?YlHHMu_BcE{G4k5RdZz59Mo&>*;&*Cl;EzlSN*8`STjdKb7pb<eEX
zA&<L(_O$5NKp)E5oh&xT6AfdVDtj4hs_5qDGNXE?u4pLVS#|qpDBCL<0#|d3qv34O
z;pB;i;sedmVj8B>acUPDj*<85ZkIA8G`z}<TQqE+qFv$gwA;O@*RFWZY|a39rPEKl
z-5>P4ab-Vml+|BEV?WlIH%_abA4{k=2;N2gc~~_!GM@6Z9LQ6JyKid5QjDh*(~xcu
zPtlh2O0F0DoG19r(hKIlQCB>rc%SO_@swgT;wjo~Zg4!61{#rPJcTY%TrludJJ3k&
z!c)p)yjt@+l+ABFWcKhSJ(|zTj{CS=S$nd>hWn-3`z23n)_wx+i*N|%WiW*D#eNo*
z_kCzCqS%|!37CYR)236{TMu0{_uGfu>wmld-$&cE<5Lzd*WP2(-HN50WKO5EL+szt
z{D(Tdbpf7h;MnW|_B_P6o5W!PUYCk@2AdSxH5)=)GVp=s^J@<6;hW09@PC~l4CtXu
zIBH(l(z?^W6H|S*$M)O~lisCmVhpievi-HnTOh8%PrSJ|A$}zu#ny#=OVVePubp+@
z+#_$>kSim*?#gg~tm^vo5p1)i`}@t6x5eje3w11yd&{AVwavfEZ5wuN%l7xR?bBuV
zdu?-nxvww!YA>c@Xzt7eYlNPTrTG33aS(XH@Wc54o426v_rnXhFS5h){1x0!4h}@`
zHoPR6R=M=J#SHu!yDy8K)R-J^L}kw}Da*a2f?sFaw7)=YwvpAm|M&Ygp<5|@A9ne&
zQ>DJmBdi&n&6?3F;x#L$zfxPly##tb%zX1v=Kb(WkcE9mp+D(1w*(G->psM*EEcFZ
zI=_4kiCA^Udd(WvNA-UI8PT5E+g10`J?KjBm*4GS^mVhxyLM*B=Hc_`62@KmGJHv#
zT;nL0J0F8k+mb`cAheU7Xzr(frQ!FQT#^>#%Jc`mlJtkl?gd8a72DgZa^5$$vq!vd
z3Hd2)^1jW#YtOHANH~kL?=jlqSFgIUn;a<)0et(9cA-TS_q=b3@&8xFr<kV}V_oO5
z?nC?HA>sB-2UzzaE*<NC#+GQ_CjGB6alUMPoL|`reko&cvWLQS7Ikx-B^-q{8lJUA
zW9QkZWAZ_r(B6`DQ1t3Y`!wS6;dxOX7V~!FP`h!t@GMw_BiW7sw``cf#eL?6C#{!3
zFRdfFJxQJXJ?uMb(*|@AT&w|lyDFWbHRMy&RsUsmCFfcLZE}}p92*(bUf9=E*4}pL
zE&b=#vC(V111s>dzwIj%t=o@IePjR8t=~vfg9W~c=k2zhw1e_3v;AN5dc)3+p$ENO
znJ<D|k9fY$=CM0#_e|Ul&x&q#ZfeZ&oZ%O~*F7rItL<UO|LD9V;KKU)C(qy1&uun#
zwe@MvyB1_#eWWM3YjA|S28X$8aA^7~cHdyQE2{MDEOkEM)(Tc|)<xeVvwr8-x%EAC
zy!O#bFQs*Nua)JGUf!2~17i+*e^q`bzFL~hC6jmkc|&)KEV&La2(CYKaH(DG9Zu&t
z8_Ql-y&DY6BN!;FG7oS*KJ;g0)<k9Q?r(4AYrXbl%Tn^yhG2c7W0W2%wG~fvjEx9>
zKgRPo>;8Y#7_VPE#s|0$p>K>cQJE#^sD0z_ZA85Iq|=oBBH{k1?v%xq)4TlI8$2bx
z(s`F=irfQRINvLow|CiE(p64pVVbh{yyyGGc{YBE_jZ?@I}q;%859og@BXKJU;cU1
z<@m^b{<!V<ECO?Qi<_f|(|h{IbU$O#dCz!E8iUeJw}rfDe9F5ss`p-=^ReS!oYvTj
z_t6nss4Z-@yZO|=`BK6szjS%W?jDfuV)M6o=5Lgh&QHcKZk5XEcd7m9>j$(yKo1Ot
z+us{AJfOYkUaaDsSh5d!yRsEy;2T=*!Y9;Oi5c^y##xi(uAjeO4L;mGT{ZOI7JM!9
z<<>!C)x|c*CzO8Mg+I8HpXyD&q2}t5r+Q|ap=*AQ3mYk4RQH5fJ7>`jcG%jXkDdJb
z+9A){@wU3yPSIDixd(K&Jw1Z6u{W{%G(~^rLN?z-UrMKIp3M6p_T>+ySN-XA*<-A)
z>K^%}?qe+S191)6`#d%w9v0v6OW`xgpo>qqcW|1h?>Jv;Pb(Up-{Hp$TiJQwqL!ss
z-|pnVrzih#5%?W&S7dRW3)pHWXb)PLe1>mAjnF?ZOAhMiu>VTW;sszfIslLUbsi(!
z$*wumPQ5R5=Th_l^3w=@ccwMVUpuE|?SNzI+FmlliQ4A<28~(I<V)VN`7U(cJ~6sH
zS#9avuG>58%PeXGSToAl{dp=g)Tz#zy?%$mZ#4FO8J%gLGH$Pe_sdR8zNO=c=?M2(
z3e5V~eyQ&RPkOGjs_$exrkm(*MRHrUd0pblMdbthhF{eae&NBk<i+Dz>x+H()%!{C
z3qJes3qKfs)ee29=+F#00H2-fo7}O#F>*ogEUAOt(Lv>EX=~#Cv)x$i8|P|=HqNX1
zG;nEtd1xP88{Z0_evI}#0;>n!AC{j4-g(dOs*T28uXtREMi1*AheBD60Y0!Xcp44l
z>Dab`huX=lhr*o{E0Q}*ugvJ43csJ*Xa=6`%<SXQ{)*V9oz$JG%+pDm-0`%7*%kh~
z#r$h;o93PAv-ExEl6#K-iMr=e_gw5ezuLEf>5;96Y7g%@RQp!<km5dyD`npjZ`@Ix
zOqfeD2R0qR{y+O38}hj8I64=d*=C<)E=QUpeyG-}oQp5uc*N-v)f4}J+sVv`WQKin
z%xkK(N0i1{J)SdP&hegmuMP7LPh}79nOnsjtgehN3k~Xj$6Y4$RcCIuDDQel$NE@O
zogS0D8LQ4RFJWHX`<B5*VnDiUSM#aIy8U<Ul4f%t!6klcc$nY|>nrd9;|j7Weyb_g
z!O!l$R$a+XWFuzh_9QoBCw3i~>d6mt;GIXib6bv19ol(h>!DfpWNQA79C2>X&Mr-4
z#O+!)pr<t6Va5wi>i2Musrta4ncX>v{nB`tJ7td+#zWc@8joT-{4^emYtgsyEPN(d
zO8M+b<WY^=bhGDCvsc1_Z1Jgh^98`HvgpL1<8t06Rw$XS-vHk*uI6Y`ZC%&TH<f33
zet~`&^lIY^SbS06Ss|?tztv9~ZA{0g&q4em-+*5qzhL`K*TP4}FZ}O%tiUhC#<pPZ
zcVhQT`9<?;@r(NQV{87syZZ+p#`JkCha*7-!HwBC_}XmT1<0$~kS-pD_t8)Fk9fWV
z=V#1!r;C?}@3M!x<^xaOw;lhkM6a2iMXyD7O{eK8?tCw<1ERlbet(m6U~Pfl{FKEF
zC2w};^L6kKJZ3zH{+r~E(%?Hi0DbKl-pMvP8(}^u__`jQV}8a^y=6Rto{;Y+eWA5d
z@tf+zcI#fn@w~0HeeJSels`_ozKJ7x#OaFrt?+ct(<!5PXLGnU(LRiwF<)Z9ozn5$
z+tED4=1h`@6nKFlz@6iS^ErY);2~Q9k4O)SpBQ_#qGk69&7P!x4k#%tW#60GU&@ru
z+nxw*^lcf@MtEY(YtX6cBfG9e%(pvtO|a{mTEy?W76+E>YCJ~UCiN+2btsd^)A*i7
zpxNaAU8!!G=1%aAzsE{+<7aa}J*&T%_M{o@Lpt;kji1NQ=9T!Rc^&e^FX$zF?AC<g
zOF9;OmGXSyyI3`BNBEvt?Xj+#>ke~Au;4;}7+$2Kz)gmJS)+Z+q_5FAAJUr_@Q=-F
zPVlcX!W%l~n)Be@@P35%s(%MZnr~#JP2RV^!B6)N&23&rKL2YfzMX(?`ZRn$-{boS
z{5l1?PjZG|XlJg45BdAe8uk6N;r~R}_+L6edS0~7P67|SZTzQq@jJX{WrXw47Ct~M
zzr}j#F<)=TuS{f*@oYHfzQPl3Z9?}!XI;|iLpssPxqlZt!m)64O~+tXnT$4VuB3GF
zgr~jyZ;Km<_EDZ_FP)#$UOpl4%U?Fy(MSDH-8WcD`5{`rv2`10Q^Pjs`>nM{yT%W-
zV^edYvB4{UfcAy^+6mI(1(R*`ZZ6wD0}SFFXry}bDRO^L>xf4#ZUwowy5Ozy!_*ND
zRi`LN;IFcUb)2L0d7R&oDWg$y3%Cg7@7s<(p&w+k247}JX^XKpnFlCcylV6n?)0p^
zz>Kx^OC_*e3oO<ybfNs@eVpB7%-0OHw0C*JzS)P|WccOTVcHh&@QoeGN6q<PlymnL
zsgKU>C4H<Bov17R7BA3#Ht*lXE3|2FD_`%7MSO&uyLBnS_tX}#hVI<vPwbh<*CUMw
zOKe?HH~KjrGJ*Z_bUr!d@G2WaUpYMuR>me61lRFykDloKn4Vgf5#Eib4KK32Zr?IE
zk$!Y*BPJUfTM4Ws@dnuwv#o-Wc5~R;;88FkD@vO=fxXaLl+wP3wCjP#=jX8ra3oo^
zIf{RtJ-(;<ijhvWenm22XSWi&CwwCN#gA7fUy)S*;cthQ9p;yOb!gcNeiQs|8t_|3
z`bK`lixT0i!hC_X1NY2#%F>2^W=~5x?Vnly<;;RBvySKF?e2N4o^Nx{+(~cadv<Tk
zl5?~FC1cu+PZsV}Y*c#B6FxnMkFzj2OxW5SCe8<2e>%$}97=beg!VTEekD!%exW;8
zmz=4Lc#<+Ecf7M6>}aBW56bU$=W3ffjwY0=J=HxkuS;sd2UwX{n<`&hMLy;1S@U_d
zVfq1{QoiQ%{L7zgy-0rd06)dzM9g0+%wK(s2%F~g8$2c6Qad?ciRab6$7^;?%VaH=
z#go7!-5}YN?5f<glp*~Z;Uc_)o6Yj0^zDz>kBaB!g)<<)a_I1ID@pJCLz@fhz8UEs
zttneOtm)4r?B#!Kb4zPAk~iz)5&Br}?xc~P2=~hbA5s3pE&S?_EMX7+C3CPiZtmk2
z;D*@Vo;mTT#rBcW^cZkz9anfG-Sh)v$YX@wf6eE|<VkkLXBlfEc{%3tmd1LQ(sJ6z
zxIGh?_}1)q3#M_u26r`Zi9T%)>o%ox|Jmg}eb%S%Eu^R3Cm$!?r8S_u9iP6lke=H7
zD~hus@8A``!1b@Vx8Z7R30xIz1bZUI<3R?tab{9FQ|I$VQ^f^ESJ7{lc$C>*#v1Y@
z3)a6ct1(H=m8S2dTRFxbbeOe+{_bnX=l8Xxw3chf+875WV(S*ez;4MV_RX<L%Vm_Z
z(m~8OuuEr6*tt&l(CjVpZu4p2&BrQx7LC=`u1dzJb5q6foX2?0W~zQ+90Oy2@q8+h
zq1t@c<S09*qkFLCHhUd25@>>4nQqWt1Hre@b#o~_&+|M)Jw5ZSquMaf_}ZJ2IZNZa
zO69T>-<?&2Mc-aerw?VL$)T*m_mjq2b1U&BMwttb;^VD6>hICg*aOV^W(@6Q=e8Pr
zOQtc74|RWcYVG8XT4QoYmTX?#xu8DOdC}&xTj%tZBPQX>t)|?$$>y<Xm3z+S(S&mB
zHSjnv-4^hG-8?NkfD?VUaV0oVdELXcJv<-l&h7Kh;~G!u%IN;BUH-W?nm8O*_>XZq
zHUOu^Gxl*T_2iV<A=CGYorq_Kos8Mu8~D>=Dp9(=(`b3(d(|PfBK|iU6yBk~?1Smu
z{|sJ~J^^py2P>Yq6CZOnj>$q7#bkqjU~+YgI^d&Eu1GVv3a}2*caV9Xruc1!Zo47z
zdRwxFPBGi5_!lwVrskB2OERaFUg+62zG?hm+k6<?i|_-NukHM2zK!MK4>6>+?B0JY
z*gfmN<KmpsnUA<RnPk4Tvfiry&#9`u1+M<>Tfg+*yg0#TPR%U|!%LTdfjNxUopak;
zgn@W@h!1quco-@@dW7*1XG<zmK3%#^b8WSy_y;_yIL&$Jd($o8d-h0AXD%6+mc2EY
zoX*W@C7Li_)0|EEuX3U9JMItK=KVcd=#M#J_Gp1ONE^r->MxGd2`2b4j6b*I#e0*M
zlARM%Zf*$ub|FXkIAi&V$M4f~`9ZeQH{yT8)7qn(^C0*(9z@QK2jArAZ#;JpdXsPT
z=KqQGX>}yC^T_Oj#94(4y)W?oRsSwoMMif$j;unXK3PRKN>+{T$a99C>XT8@Ox_~8
zr^~$U^l6J^R5E!9JSUlyOn}cmnFu&x@1Wu2T}#Nse=5Tfe5}6DL@rMS!|yBs!>dmL
z!<oqCPk7mo4wk-?ep{KG4^8k}{=A`mN#^q$2k(k~@RLl%JSm?^K9zjnMSK=;de;);
znJgPmJP!mW_*i~a*q<Wbzy1y4@7-QrQ#MO<h-6RoY+q)?FM{_xzxToTY>>P&W@|6t
z=7jhE2JxA2^hESP(N8V<CfH$p$1p>t6^}ud(7P+~2e!I>2G6WBPb`T$oMF4HvuVEI
z;y}RAd7|x(cz6Z3;FYg;I_(x?cSSsm;G3oRW~1`Wrtr=1VW6+Rr7b^a96zmANxp;+
zbC5OigM16{U~QQGPl3PI_Yc6|cL$z>!1JYA3M?bQR02;C?*rla7VFllS>LHL@8?Gh
zssG!cDL(8dK5PX%je)0S<vwh{*9iC;Kf3kM_>n!}tp(nu1?QJ?I8Q;xfpGpyeSXgN
z%P%;k&yTO5a=?qP+QI+7BmcHWJ{K6|x7zn5z~eZ0EW{4sFK`GR$H3z<@OTz@JjPrA
zT#aI%R<a(jQo2y~S91aIv{`cj+R5hv#7PIv1>$m#g>ofx0opH}3uyffT_C@>b{75X
z8UC*&{&|Qw(Q^L`UTm(UG9x@|uEg^=zVAwKqvw&M%n`yfbAf&Sd0gXM=F30E9Kk<N
z?l>Rc=0ak4Q(v!jw|+f4*|k`c(Lwr{Hf!V5Lsl2jM0v!$a-S%UZJbJ9oq`{ep-a9i
zda$Tpzgz7V<$Pefr<8N}aumL-ETIRNA;)9roC-R}^dWjs_#5&1P<lwTkX?b#q^AX6
zY*(ho2jKI&1K&a5`x5#Z_<%883?J**2XQGD*^hy6J%oNd7yWn+a?Nj%eykwZW61R~
z@OKvYTYd)maajv|P77Z2q=y$fWcW<^7d}tHp9A5JV|sqgSv1LGw_3m99r?wN#+ME8
z*9~4z$``_)k9DTx%kB%29wlG8RNt$zn2P2@KHdB_&Xi>MZ=wCXTols^F*C+!bK;Eo
zZ~Z&0AJeYtn(X^FE&eH<0^Y%L4vlmt&T(wmG5i>85#wzbd_M*}yoWdnYdQ}SFM3dE
z*~s+T4BOB5hc?*zIPb*2S$ErDb-$mww8<HXwcw<odAa8K(v5}__O68djDG3U)w`*e
zF1`t6CU-c!jE#7(c5>^3x~J2@ru|4~YpvFOms@oLY!zVByN50B<1*@6xnymPF}N~3
z1HZ<U&2Lrw-leN8>;yh;uPu0^KF7P^W|aQNY^@mFm@UZZpm)(kI#~3<M{@M>&!i8g
z3-ZI7LReRz9DA?EHjd(B@jNjqA9rDD4&85hzK=(xPw2O@Qsdm?_I!zN`E5!LSlqED
z+oC-9$ao5#u{A*Pj-``NJ9X|{ircXB<70`9XH#;QxAX6?GHSDu(r2-ssO=Hp)?Oy@
z{hQvc@0_t-3f}c?@*Ee%`FZghRK$^((}R!kjq(HZJgW8OfDiI>9_AjUjCZ4_)$6C1
z?GMy=&jt@g9BExB;0W5;GjS7}_v&4?Uis1Za@;|uy8pIWCi)AP+8-G8HNxDxIS7~Z
zy$F|rC+cg2IeWn6y#beuaY<a3?YVpyez!Q**p2ehN593Lmj5gsa{MK{+CDeU&zQs8
z+{(}I6yM%;g7^XB?Ta6Xro<0y-d2g{knZ~;WphNGL8`oubwa<s`J~1N1;1iom%)pA
zj$=}z&=@>tC;MYyqFp#+Vz5EK3_q<eE<)PC_>}qq7g@LK)-T{U#Y!`N79W#dD#9`p
z!4k#C)JDEG0$c`<d|~{<K6pqwBY2{CU7(%CBOdiI`!U$M*<qJ9!rsSb3Lb?YtxfQ6
zyek;Px(jI|@KlpK@>DKApAy<b4=EmC>-<sL?37>EkzS#_8NbKT<c@Y;NF96jb#mP5
zJ&HdJ)Gg6n3AJUMGalod@mbhIbbbvxfNt4{o<T0~Q}8QBu@9ziux+EqkP~R9dr{=O
z<Fm2$<MdhUEtj<Ny<FU-Dfyq=u@-%ISu%2>%RCvnIA2e7(0wa+$j(fE@RHV&=M0}L
zcy~QX@Rpp(kzPs1*$;^wou0m-6=<n%8FtQ641je%zHI@1OkbA9REl@sK$qI_t@to|
z?2Ja=Ivcu4a+eM{UeX#_=F`M;T0gFzAcmzh_)z@b_UnmxS<jy<s*B624TCx2b(00f
zw&2mY-JCytUz$7O@AcL(NY7!{o-7Y%s+gwARyq?YYqU4`bq~WMV^6MR{erToV!G%R
zY<c3oYa+gj&JvL)A1vcP18(uCWJ7xhW|1wY_pnv;Z9e}Af2QX{_gt49+iL!p&h$vW
zEk^sP%WduC39mb%W6eJjp5}ShUJX4j@QhB*+l}X^MV`V}!zV;8qgdR}42UHSsEb{t
zKIge<t8<2R<9=K3dE)&Jtouav6BqBi#2(j9ARou~AR}GdpCX+U=q+0){#vDdsp7L^
z;v4o2LLdB>iB+1j$UfuH%LmC6*MQ%w%&{*2UiYCFZGWQ5Tnm3`o!dVLSu=YC|1~6c
z@SpaU1|3i;>$YzTUwE{qmun{&M|aA6S{nnfm<>{2;vwFR&+VOlMv`jEUIO)Fez8w~
z!LZBI*ep-$X5b~XWqX5#C&>(T4ZfHc2b>c#*h=ubCgAb=JRXH3U^5(D<K)ryM#*m#
zjO>fB{lSb!arfM&Y*s#U|D8szKb0pKE1IXOE^VXpa{NoLi3V3CH?7{(XgS}VyG*W^
zo~8X&L(qbJ?e#Vq<!!WRqf2|}9@ZhGduZc)$>^qw*zdqO^y`J67#=;J@UZ3W6k$nL
zZ%W$za0DC|=KxEb#jG9n{4C!~bl03H_&vNEZxcgXwcL%<-tm(huPYz8C~x~Q@qcq(
z*SGgnKhQ|eF^zUAe*g{Iy}CvN-_BArsJzVUVEKf|hxQ%Yea<|qjWqZ^@KrY7wK6%(
zLw*k_eudE<-^})oB9E#3OMh-hw!q0J^(mY0I~&Ho(ffVuI|B#WTNq%#rqUPXr4y7d
z+p#1}>|0iQrbBMWzZq?;ir`C+`nJ$7%-tP-8obmy-s=aL(f{KOV7}2{j`GBhIqY#d
z{f03Z?WCuG)$|no8lM(uW<Dor)9Kn=mUK=_dcejCKI*^Dx<2R1WsmYbu{llYBY&2R
zodI8en^@T@=K3qqZ~WMUe5m&LR`yEoVXt)8={VN1#Mid>85(8cbJ0XU>22}0^tQbN
z3qHK@1@&THmRwYBgRaNA#v_w9XGF)ZbZxA8quMCu(VpTx$gnTp$X3bUp`QAERaqT;
z5W^k){UrTSPPkn2{9akfLEgV~2l;uMTTWGuJ<&EscoE*t#7`P);4!5M7oxq&30BJF
zHi}q(>#v^G()T>99DbUOd*1wg+q)I)k@1GwI!k511MOf74rZKbplyp4<=@|ghc%aL
zUIYB-vHDfC@6(JYfid8>fBdwKJPS_SFCqBRPxh`kou|pbI^a$`Zt)w*W|4+x(?0UM
z=C_DHKu0Ubzm0tbc_+zxQ?%DR;O@A`-3h_s&ax}Eps|(O>Aty%pGS$G7pC%k{k7vf
zALDm&YEFEd!h1$To=wl5pV(P;J)6G(ZA=DzzNO)V+rGLutwGue+KAJpNn;FsX)V$;
zK9$?(&%KCF;H^Pl^$k3O8}X*&8F=SNm;K0{3Fz)%`yT(#9%YlWyu9Xy+Z!|3$C~V}
z>iIn5!Bxp>>vw8;bx3!8d|)DZgmXQ^tyX`!@0)#{A+DR#PVloQ+Rp6=et4jvxyc~-
zH%0JY@8Q>eXPrU#*Mfg@1V6NEK*NFX-w?rnqlf>7e`WZe7QqjnHQ={_@J~kYKi$JW
z`L7KBO%eRaL<89v2>&x8_`lb~|BQcS_|aQ7UqlwnuerF<l6_9Q+|xA7Jx!dyWV-T|
zbfoju$@R(6binzKd`~<&Ab&<CwD)$#?}wLu(7g?k73Rr4K8TLjyyEMA?x6F8(#2kP
zng8~%_Qnj*mrpi4el8Q>SwRe8f?xex|At^11}1)I3={T4cE#{bycYZ9_Kf}I<#y+<
z=3f<^1qJu(Mmp8I`Hq_D;E#ROY;9fsQk0jHZuS=XD&6!f|06%S`+)YQXI*UML(YC`
z&N{>1$VxL|&PYFgeJ*^L&-!`cx13+AId16dT-|-e_uO9i5!V+y)z{bZsIPybFY@!g
zd<-!g#fAXm2sjg5>&^wXg)aOrUwXW%&kPNWbr#QqFh{E`Y_)wx7Rx!{aHsayZRp{w
z_Se_jSk`TzZ~F4MY}CHVx1}iC_f4wTe!Lodr|b$BM`P{VWFUVZ>%C`hojXv|eg<%z
zUBSQg&AhdetX4nir;IL*n(kZhWekU(|GjDre@|(|!;;WOn;4(IU*pQszut%4d;3kF
zOl+S9w6yQXUdOkCnUAY%ElrHZmVVBTD(lIl`*JV-)vD{?zyA>LV;-I>*~8}BuU+Zj
zFXH2r<I2bEaPG%!^vsAywdzAHhZoU4!vCin{*5kz)$w?v_Lm_&ZVx-JajthT=6(cy
zm-=#cUWYjeIussvX9Ox1Pe`uE50aiW9Ft}~nfP2WRMBWe<q9!WpC0@-l`W0!73V|T
z>uGY1?;P`F_D#M`Bj4_@zccu6JnxdW4L?q@VZPCY&{gH|-(@2-Pl(&8eeU|zAwPY=
zfHDt6Wp)oJbKv^bl^<g5>IKQr^zs{#!ScTJU9BPv+2=l5W$&zq&G9|*+^BsHIu_tn
z+55+wzFe{|U@q<JfdPFzP|_D=^S&mQ7?;LgHm(B$`Z`e37iB|VMi2N(IGp~+OIqfy
z<DY16h3Toe%k6$d+h;H~%sv9>3r_O#HYbeAKNOWe0pA)<jhD?XIC(=p)K1d!^SrHx
z6#phZ5$-%u`xD7W`IcIdCVQo$fc5XVGh2Q+Kiz+z`x0zE$NTeW*Y@p})YV$rY;vE;
zmCe!RM<AEXBk(i2b1#_v6&FVxP}gKC*-@>3hZu#O1!RoWuToF`iQ(+1!$BGB>R)XH
zy)D1R)|I<nwuYMS9(}>pWzI{i-P)|Vbm47ec_eepM{4uf=M((+udKsP@?7y}AN%wp
z-<{0x{iToMZ$hySjofzmJ{@}2#*OYf5$U*3_v+QCFF&Ba-H%rDyF#g_JE~R2^dA4=
zyHVLZc?ZcWj^XUY=?#l@xO2uC^DB#$icd%v-n8yxd_!LPw|gwV^1KomhevdluKngu
z8l6k&KrAO6_Iv2dXw6)G$$aM0OXdUfY_dfAigAGRj2Le^@9q^Xg%esc?!n_g7Ofr5
zR4&;LdV0xrm>+HOYj&k@kT1Ty3OTcTB0QfUH%V>_|EfgSh!#($?bZ^wAm7?<(Ka!O
zGW}NjtLs@OoE|b+xY)_UjPB2RFwj3)-3QD4k5xBu{(6=+P1cA_nT@IqX#f7G{p+Ll
z|I*|z--{qWWm9X9i=*qF0&K1AIir2M+hIApOqtnmmQuF3td92kQfC5u+P%_?>ac&v
z!(OqyYNu{9BYvfIUHJv)C2zNJYwghB>FPc+2X85Tr2~LL{>Gqu(J1%*pYQcine2>&
zHhT7T<UVZ96ne$VPn*Aq-Ce)M(rK6bbSCfG(J1C`3;FLY&)*yJ-=}=PzETELS_0Ew
z41mef159o1{dKxVu=VLZ{BQZ$;yd%Zm&%tPUW98OzD|_Z^F{5R=H%{#?=`odvtjzI
z#$r1-dm44Wxwvkx57s88FKt=8Zvnm$-<HC%GJ)p&DE}Q|_LR-|X&udE@yD9({$$ch
zecPqhMw!paP7sgB_F}W1ici;R+1j9N>YALF?{K`#nt*tF)3ldq>Sn|6l>S$NU+TQc
z;_UbrtiP&kO=mHVceP%vJ!})LYw>Zy7={zO&%bg$?NV3szW|T^StBTE+t2-8Sklgz
zYsc&!?WxT>keT{lE^$`B=z|k4ui<BNkK3V4=kKIH6qjDlm}&2n`?M&d`GCc21p{_Y
z_rn{le!5317t5zT&NbzGNGWf;Jl<hW!M)+k2U`EYo)Ou6wS`TSUr>{d2=86qhog7+
zytn_Iy^6jZXA>seK1k@IH6g{eeV%km#+rHS(^<>r8QA<)x@T4X5Bp3E_Lq5mBU~VJ
zI)ebL6MXC1V5yB$9=ZmfFdvunY^ZZK^bF6BcH!6k4eiU%)3}Gi+SGj%z?Qd(p0>3O
za5ZqgU);yfTA+Lt(M<L+`{R%G)_Iw;+1|91UE7bMeI{DxWp10_i=cU(e&#ERzxnB|
zRr_W<v4qyvOCA0clc1d$VokA6m)?kff^T5;ML&L5aj#?j%EZQ|Z(W=1GXK}N2d^3L
zis$%k#3s~_GS3v9Jj^Nmh)2v$2uJ57=GSMR|7caVM|m1=?emXSE5nI@zTVnkertMP
zWd-vrZN@N*4_f>2`L&+?3zxP6-m(SOz7zv!>26DWf9^We`k?W}e{ejV&u@!s*~K^v
z`@W1%{20ym4S3c#`Gq@et^Hp*Mf=6QQLJ0lPE5@`p#43f8*?eco%ob@JJX$~IXTsw
z+wQwL)-~N4<Ar&V(~YmgukTJ7e9J_a?@6lZ+lGdwx2$iO{P?;rl|Ez)n$x!NfdhVP
z$@FSlt3pNwmC2;5kRu!S8@;X&toV*5b1S@j@IR}&P+o~_ouXg0nW2xQPt1l$pMd-H
zZO<Iah;>L09G>Eyl;pj=JCQ~hgKxK=ufZW>%XK_+CU9zd(4^;?KW+?qKDiS8thoa}
z?bXnJtI9LHp06Zs4H8@waV_2mX@X%=_kx`gmdGX)`)n+>3APXBoyZk^nY{6@XR{S=
zle~GI_bXoKK?BK|c!~R4?O(EFye0Vuz5ugglfrqBrGfgYxR(Z<EdJ8Ba06f2ULWwC
z#{%B(cmkM{%8iWc1aQ-TxGPq+VG+HcwWF8c%TQ9s_>po&o|TR;TXQCL%J>brGk(Ly
znBAH08oq7akbYyGSCwq-S;AhItRqOSg@=rG7mZ(e=-PmT6#Xfk+}64VeOuiiUuQwn
zF0iSNPcs{JR>yQlb}sq8J@p0N)-J*sZ3nuU+{y2ShPI|jf9$=2H<(8&O?hvXPWA7j
zz8}TMlwWcGYNxGsJ)d$fj^*1qIe7K%q2ZzQ4>zw(etmr_z=s_$n7MP9{s!FpJz#&}
ztwZ>|yI*c+K$53jfqolsA5^hEc0+KN`RMK7qmv)UB(r^rC%H3V$V_7PMgDfNoaV9c
zhG=JW8<3x&(`LHv9C@&j1L46}8aTF+eTcHj%ite(9vogio4ujfSoN9w{Z-(p<UDk=
zPr&wCb7mnsd-nm;!TM($742^mFT#7q6M8<%v-m;JW=AT$b)DB9v2^1P<;yn!2D^tx
z?-j=@DZX2ZULh_q$Gs)yi$^g&V&v@qylkk|tR^Nq(t&n{6Fp+j*cpp$D19Z*3(UQ>
zPVue}R%=heA0S<H9le&kqh5~rH<$yR7?WsO-%s3$yiyz$bs=!o;A{BZ<`9PSQDD?N
z>4JOubKssk*9=a7X3z5xvf;`k?`f9Pr0A2JMt_~=jjc+>^;hht^N9hpFWdu`-ZnJU
zx@cWX@kX=pe-!ES_+GQ34^_m^ynGzSC|v}t<r|pJVSOn>R~ug_559o*P7g?DC=LEi
zrFVEXUi0O0{i63F+Jx5Eur6e9-h&;a6SZw?9em@-d>(wc)|<JXQ+zN)o6uRj+V=U#
z@`UA6ZyaA(^LWKuck{D23H4IJI1CR-U-3S}J1((<RbvC*=2-uG#`wcNq{=zaL@=u?
zbu)N9t0d>!|H!oaPjycfdv>{_U2@lEoxAm@bS3cLy1u3N=`Qc&mGWniU%U@1*i07z
zcP&lO(XL$=F9IgXfN(;)HH`^AQ-8vf)g!(BnDaxFAK*A`eeLyafTP!M$Jr0jIrQyi
zqVs7#Zwasq24d+0`z)SE^LzF(#s0y$jl)0Ze8_xl4qDf>zlrvB5Ao#2cUZj5?)1;o
z+DTJ)+ERY<3l+D2?Xzihh3@#hi@B@PiAz1i`d0q#;!NzxooAkVPf~vx^?m=wlbnrf
z{qSWi^ZntAz^}7Y&i|c$7yKIFeG0sFIWYc9`mZ_oZ9Y$b*xh7w2)y%r^AK(G-_AP8
zcGB!yD3>r6*?ZFWk+uyzujkR>PIa$;zM1E29{C2>qF3c3@VH>cUgfY8m#(k$W0!1!
zqdD4EEHm(->c{-8JB}*9!8gJ@pQbC|d*&~}udr`56zW)P;$5ze$q2ljX?)^&=@kCc
z6~y1fYlc^!R|)SLufHcYqDyw9>-3Mcht80!$j|iesrb|T^67LZSt<R%dpg`ncKK&?
zj>EOmdA?b2>6!Ao{B!m={q*6@l`(i-djs{B^qBZ2!-g8)03Ur0EN}X8B+_S;mp(H%
zJ<MT!k8$|%DBtPRTwh|V+rq8j0}t@9>D#`1;amA-`j+~s@UMJ$V^Mv{AMLtzFZZ0G
z)1)6OXTxjC2kva4>vXC9wNA3a;4nSf4mwmeAl9KT-hE(3v~>STsXi@<)hPa`dAQcl
z<P(b*6n{uxPTU4~Do^)t32w!j1S4bDoJadjUwb~hpD7)g`Jd=G@}*PFKBz1(HP2pL
z&t!4+?gMLdcecu*(?Xk7wK?qSIQ{L~$&Po~3+2k2|K|6^SRczN4-e<K6&=LWw0n);
zM<IE$bphl)Z=YxN&v{TAZ`O6|f9Z!lR^9wbd?##%$tUIP>;wOb!KiJmgDSri*Twk~
z^r}g>2*(;P@13WkFJ-6n6Mid<LC@eUTj<)^{|sAWcvU)Sc?@!%XYnfOE5}?t_$}}>
z^e0{<ovV6`sV02r+5el5`%}9QXb(CzI!R}rJ9Kx#eCE2d*G})hu~j3lqPQ;qnPi54
zwJBU_uFc++hT1C~dolJ+Y$)(;uKQ?5X~F)B9@Brlz9l`GAx8!$Weje;OP-m-1-o9H
zo2BGSN5%e3F8{v1*(Ta_^Fy!qc+d4Hyr1hlJ=31)Jf5wsA@HE|p!4+H@;Xm^l)8M=
zdwQ4tqm1c1l^x}sbj_#QMctx&;aTv(vle$M(=p(jx_N!^QJ*h(s``Ql{bV{y{aL@g
z_HtcEnYQ>#`S2#Z)vpVc@5fuJ3&~H#YpOp;7iyfeZRfX)E|lj#%-IbO<Y(v>(~&{m
zRS$Y+$GYGOpA-JhhVVJ{ANic^pew!qr+4GGpY^(u|5E-f`u*4;jiZkT{d=(C##`uw
zR5TZjfpHPel<#?<&A6arKTee|oKn9nelE)w%?9xh^#jit?(kKb7ojgL9e+T+UU-iE
zy^t3Bd?Bsi_chViIbOj_Y=hbf@v#}F8+XE^ns-c0xA2#eYIcjqIscjL`b#cr87vyF
za0$NTuNeQ~ub7T~iLb+dpG{J1QT!s?E;zwueZtuVWYf}0WlZxl@mGa1s!u)B>F~$&
z!<V)OjZ3i#``#9HO6|l~_AH5$QXVVXVsKI;ZeaES`bs|ge99uO6^DKfc=#FcIUm{L
zp`=>->BfQVr};+KSW?x$*^^*9c{jT*8^&6V*&yLUzodolf{ne}+hpNqtzYN3^W)VW
z<m*oML3onSYIb?8rw{eb=6ZXn_Jh3WxqjTu!DRRIcqi#i#vofT13y`N{*IBF#sY3?
z8gmz1ffM=ZRwmVWTw3dKmp0Ho6>YQT^(UvC{{uhu@!A!BEP@MM<a`tRLJJZ8M^(n#
zY;Y?7CBOe;6#V+Kx&L#P$2I&P^34AkaeY~R;SaqJK63k4%7>r#{z^(+Z?BUt%a%9L
za|2?LMOzI|)Q*8i_|N8*j3LlFx81-Zcoa)eo^-0sSN@+Q3Gd3scQv0Q_$j%aRUUk1
za%knyg&Lb=*}tda9m#=oU6_aHdDz=zo^zY5^k9>*^%mps^)w$bU8473t2MUez($(c
z>iFI3U;1&hhGs=Qt#_NBV0+ES0&ZX#SYA3R9a+LZ5ggKi{H$NWI>1M0%O)!y{4BB$
z8awi-cFZ=bTnYRZzl+NZ=qs)GzRK*ka0U$KZ~JHYs`*?-X^c5L*>yHr|AXc-)Qjy%
zb~<yJk{Gz;Hp6c>{ieM`@X{>bJ*v@n@b}H9g{Msy>7SosLDDx%$E4Y(%s07NE3z1=
z+O|E6tH3wU<M1zc-B-2#*<`=B*^Ema4B~C|XR#S#zLs~P%gfV;eL4cK_MmOGw9Rne
z(iOA`-R7XL)~QS{`Lqe>rSV!n%u!|%|4r-oOnD);M%l(nulsTwM*dbl_d`#OFF;H5
zuWYr&_JCI~n=R$PQeg~59RKr~tt}ZXUw4nA<+;8+aFWmOc;-$w(}$Xenf?xanjQg0
z_+R&%nLd8a)#h*5+)Fh7rzK)<Mc(R8%~f<~81>55G(?9xfk$_MmzH7Aqn-6Fsoy&<
zP|`MY(n0m`6Z7*3i(t|k+DqpStU@P2*NNIoWiLzG2d?a8QMs47a`21cJ^MMoMn>H=
zovy8e)c$C*+xPHCkGuCj^#6bC)Bo7N{}=b4`TyES9?$)T)&<1A;FEUn$7A04AMBmb
zJoIVjtevi3&YC&6-!}mF;Jx{V0XQd5bnoL&$!d2`Z*TE`^XtrIxIvcM2{<0Zetd91
z|6bmV_VRJd+PSjh)0Y{(v~HQPf9{3a!;|O5YfOc`btP?%z-x*-Uev$_%n|S1JfQCw
zJ|BZA^2*HlK9*O~PkOP7?FHX=QQZp$*KO0T#RX}1Msa8#J1Dk+AJkBcwhVXshBPj0
z?3>rM%JL=u&8H6-yS}+vGNwExZh6ZCP1cJhx?{q=*;7_;V0!`fLR;LYZF{WFs4eiM
zc>N&Qv_FfyQu(~0Yx=%)u2Ixy*jwrAA}xd)`>t$R9=NuBSR+YwQ^%i0^fqi!J1V=8
zGk5T()@%=JPY`fhjB`-i?Aw~4j-7Q3?c?{#F7xd{tFN)!99IAF{8jJy+;xY=6DQwS
zF}r;49R<3G#;mV~GYqGRuet2yyARkmfEbUh&CR+s#6F)R%zLoOdCXHXh`efUYxVx3
zr*pX1)nJ_AE(h$F>}eH!HK8-1d4H9}XfA&sZ{vV(16&#}@Gso-`80pKgncW<H>6{~
z<aFFj(n0qt2KuQa``aUSC(rb!uP{9foVI><x8L{B+U4}P(k-q69Qj$0F9M_1E(IGt
zLq6{VALiF9oiVksHMUM6U;1p;Xf<B!w)Srd7Cr0kri%9KDIMO*)0ew^wQqaSS0uTO
zkuTckQ>rffo!1o){3dOBI8tI2;Vehct1n`2i}r=NGW4ag!-9AFM6v8GDx11_tI_#y
z{rKgJT!}nTul`)x(z|$qce5MP-4QPGc>un1u@BoTt~D%t_nDG>*#yC+xQpb&=9rY#
z+@riL;<-z=WqZKg9`!apt=li-_P;O==$D=BLf_6rwoGfi`)w?m@0qMeW6gQ@>yCG2
z`)w__K&Q$L?*0?uWPF*6AvK0O(hC!f+um;LY_dnlN|M)q`P1>;&q~CDIxidNO~321
zUfv~Mt~euLdoQ9sgfCkspX%5cLf;y@;qxwy-^=hndHD<DTjlo$@;_)?ZvH)#n7&|7
zY<=Al@>%i?b;X5N!QVQ|Dp}vGbr3x>2K&w{`B|55<>>w)Jwunxw(bFaRL1;Zbg=er
z@a}wcm#6RRsLj6hj3wp@(p9wuVg$5faYo6s^pAc)7MBf{MOzP5>?+iU&P~c&edNOC
zG{{nTxB1Kl|6cVnOkei>JoR~Y$7rVcsNF}TypRSwHczckKlDere6FfFPDn>i96u9N
z7GG;0gZ|56$_2i)xt8WBp)K^3zIkWwV~k1b@=M^PeUx~f#mR(Mbl2VD+md}vMO!Z2
zt$8M6UbnGh{!Dt;$8tQ}dq>ajtoi**{r1}JX^P9q7fR2;KfR)3H0UpnpM)Hk4fxPz
zxA%>{bDxCgDte**H^laA{=oT(AGxVj<5};{KCr$x|DkH-7T_k$d;>q%T(YnK*X<RF
z%hX<bgTc6{|A(fk$ye964r?y)j>~K=F@4QCn|FvN%@Nsg;HZ4Ks=c4nf7y!}>Rz_a
zy31RZzmk0Ri6vu`y}EJ!dE{S{B%K?WtBCf#ZPm}tVGWJ=q0M13N23^a;W^V@hyinl
z5Z_5()%Z;3%9~okUEZ$8S3YjTHToI+ulc)fwR6Mf9y~F;7Xa@t<9YE-@YjI-g=Ks2
zUa|YY9mq#+-`8H@>^tcO1OFL6@sae9aHqLW?bVOMF9Twag??1uc;Vt6u6#Qa*{lE5
z_|9zWI{Mx}+|pQu&$vv8QxwxR4=k3iz51z^#vbWhf7K5yp_dCW6V}by1L|W=(B0^)
zGs@B#*ajDSK(ET56K^EwN&Uz2!h8MEDd!tL#o=@yU83{yoCQjB)}i*Q-3K@?=bnGT
zt&`;O8-F*&$hB_1Xy*Xo1=l}wx2v(!sl)Z?)h@kujr;HOC3TkvHbt?-+RsCyS1O+D
zd1om*5%6>C$Ib5&u4=cUZ{+LUqq)7qMSX%kWlPc3f^{D_*~{;iq+@nJ>{~ONMcvNV
zp3$<Hy4tCHZ>z#MjSg>*`g!{i+xu?(M0`j*nA>LR_4$UtaXPv-_bXoM^jPk5a27Y_
zgUYn0_f^g=%BK;|h12Fnk6&b|8F0<B;*=_ruYF3^nv?|(BUd~6NiQkx)=v3;>dP*7
zYh-#Kb?;Wz)7t!D|E)`W-effG^tYw`611&v9iLbIF!<r@7&N{{-)1D;_<?`p2gYkM
z!he`I*?7bcfrk6x5w#b1oag#~@8_F<uYvmDtK3t!mV4?N#9H~mV~yGz-(fjqaqMLK
zgY4aUaB40io~1SAeelc(dFC&m8})oAFiA)4B~NoEl?ilL8ZcCC@6~)1f8tqtJdB2|
zh=*E7s+C)z9r=o7n{PhHv;5xW;1l0j^isbE)vxID3v&l79ekT?sXTlf()5o%(OY})
zZJTU?%hK@xoA9mi2;Xh+U~69Z3wk#FE8LS;Q{0{3$RX~HR=+&ooKQc&!MpAM=YJRJ
zsm{A;9q^0n+1=QN53nJY*U_Crb_Za(#@4CXmw~)#Pl@4xwpnkmbvyoz$A(;5*ncNG
zVEoJ&(_vz1e%#qH(wWo2FLt+`(Pz(OE5~D?#m<NpJD~+OFQ;)R^UkQuJ1K*IYi029
z6c;y|{%Ta_SC3#vPQ$Ol2Qz;5ICs1a%;;O&gCyC2&nj<lvYpH5ri5|zWYqfqp<@mX
z*?auL$uBsc%<RA3nR~dsmpd9(K9pnb;r3t_(*2oVlUXlwYSY2k-(H>;wUwvk?QEZD
zub5^p!dcbM=*pJOk!^hNFlSS3JYL8A|9w1?kzfx^M?yp4BiE7WIFl#-2kNP!4_@Sz
zVjteW3p`?Lbo4m_k7~}I+hzD>*5ldrJ-}}&p1srAhNH;6bQFEtvt&(hppVsu&cm%Z
z8{S~gUhq>J!^p^(myx$cGV-<~Rqk_5D!=A=yU>Q@T5*OD)7eSB?g5t#mrfBrbvH?f
z>jd4hk}~7--MO9oH#JYC{7&Ar$IAF>YXrkq55wz$fpQwhKIu-LEuI$kvLK&5`C;#J
z$j|vbO7nYJOh-~~i`qnY?WNrpNnc!r-QZnz*8W8|bfLw7gjeAd`EN3>Hh6D~;JwYm
z%QtDPuJ&M4x2e66qD{s5HaWeA(Y?a4?qH@|zOP#L*T&%bs)xR|M}2MgeQ^h~VBam+
zW%GD8`=@gyp$&tZe6<_(laFCr)b2LlF6YA4mf2PO1nWcg4PMc+;Y#ZX9)}u}^SiMR
zKl;5bz2|(jBWiz#Z{Pf}0dtSy-V9{Ra2?ilpYC`vm8}tfo4?~?{Xwoxp1{Yg_?zi9
zZoXsB*M6A$=Iy*>L+29gyw%2^+mO+R&Rg}`^YKK#kKW1cw5=xu8Sd-j`lyc^J`7x4
z`BnH+jnCAE_=XgBxpH;|d04sL`g~fiPx%OzHq%QJ9DV-x-YF*^_|e%b=g>=M6N_5O
z_&6_ibFZG^>6bJ=_jx~D$a{U1_p^n(H$-`_DdfE|%Db(Q_sd5dY;RH-8>7SPdkW>=
z9JNtw|1DA8hYI!H8s&YwkcUrTW5x&Q>w9mZ9QHrQ$rlQF=)FAe!9pJTD9`&=ArIfs
z`ex42*Z1*4IrM^+L(cljt$Ibycb1QQ=Y7=+dGCnwo>IuWJ<9vuLLRc0xA}vGymplL
z;zHi9M0v04<>hm};yJ0}SrzP2?Z{T{n8v?D_oeLHmHm<3(OA>4u5bGUkQLIKx`V06
z_ng7+%{P2G;+|R)Vm^}S&ZmsC54O*Zvm~|;g0|Wt_?i{YYO4%uR62vlSrgV*I1d4A
z)1Q4xe)huRa+)Wp9qBaMk?g(J>r}nlT01r><jF@?o8Z=B!gk){Rrtl|!&2Y!QRX!(
znAh<AN&5z+Kg*;0x7F{HiXZNMD8-9nEV>hdvFZ#>dbDe272`2Y*RSfwlkh`X!;S1$
z+Dh#F4QY#TqVqt)3GJ#Mn<xAqhM(4@|C{hrwjKbV+g--bg(f^dr-9AA+&wSD53HZ(
zo_EN{dyac<;49Ui>C5XGKSy=v;DP!U<}x$zgxXb|8(iKkdS;C(+#%4ATquU2KK1O|
z*r7g|`-Ja8*ge<H-urz+?P`5h=$q$@-E(7_dfGQbdsRJO=ALJ}e^&i{!Ns?{E4s^s
z{2imz!w1pxGCdPdH#mlQ*8Nt?UAf)9oZ>>#Sz3!qhuNFV-l=xNKQTJy(uvOP+5ec^
zBc(M)E62Rr(qlg*j&l{y7PAjkdv`fwbf|W;YkS3?G?|v%+Wt)WT1_XP!!7qM5&kXK
zfSj$;U8dlvPZzRoCLJXo2)X1tjOZWW&Vavj3%o2Jo}YY4)+h0`nWrZmi&d2BHQ`|y
zdTk87#;+FeFx)!Cy#L9?1Mzfd#n~lb#;?6oG#7vIF5j>Q?55iokDbGY-ro0{Xpgps
zX1iO5Y}_+f*>{EvSED_<(Kp`I-|bw8R}=5GbJ8|%J~80TbMd><k?yx|FC3kkds1z{
zQ=qx{L-D>5zA-V%e~~Y=enei+7QiEXD>j^6&-g|JI-GA2z$?I?++NUovY+bXOzgvO
z(z6fry`+68?v-Ca-sX|F6Uf_fU{l}E!ycUvjTxK9S3QpI5I>N|ui9SGBHzV0bPs-5
z%bvV(`-ILuiH3GRK0Zk0I`E-3bPg?QBYi7v93Rj|l&(2=rQzDRL;5pr<H2?{?ynDy
z2tI2Az2)F1M*F~B=(6n-cXJnD`ui{55a5mLw}*SMseT5Ip=l!<>NM7!-(g-NJI%aZ
z@UaFY|H#U9!QpY}YiHZB+fy6CPf3idxL3SL2g%-(<?HFZxra}B&&CaHSB)~RB0r<g
zg*Vf4;t%*FgI~1n&_Uiy$7b_R^q9W?G!K7SU&sNts+~kenfFT9*!nqXZS-QT+x7c?
z_W(oJ;a2=dIg6L`ujf^)?+8Zi57z(W1KOL>i^B{`H#lRvQ;a*Ie`>^xvU7JI2x}yn
z-bru$b<?d6`1j;)?QbrjY2mJfCHFx`>rc{swq6Y`X0X$ak9zT@u!rV3%i#aV-FI!o
ze@m4$pMkQDPk}Wadr=2?8WGDeJ7YXOl_399{+qPjIm0!04l%HNF7$ThG}N~_KlCt|
zL^poxgWnH5Wmh);^B&@5w5fY#p?BP-))w~jt7?qsRXy8TaC~DuYwpq>ZzXxZ+s>fh
zZ|rgN=yp`+xbOcycn8>GcntrfxjTFY#0^VgD;kgLj_}hxm0Rq8di6H@Z&mkpyQH%h
zV2JNvyV!}{Rcx_`?XTFNeE{uu->|mzrDwG?w`;#!bH@@sE1{o!ji8fT-4(h2k)GX)
zMccSk&ZiA5C;AO4SBct#E>_N`#qBj$U@sWAY@gvpe$qnM?%J~P?s&xpTYrA*Q*FF%
z4U&1IY^&<2{7K3$?BVV{Vl(e5l$T!WlFzz_<-eyt|5nY7->P-)68x3=9{#?pJJ;KK
zxMUX>eyH`+HzDf-c)-@M(Q_$!4t<D!ynYnC*}Qxg_v#xz!0*Ts<H+O3lb=beoI?jT
z)`uu#YfJnG*$VQ0$0}r@0zQ1+Ec1+Fom}2R`^+7_+ij0Arm&~zIhyNuzh_2z`($@+
zWZtij0fWIKzJP}I%)g%RP(7_-+IU@@JOxLK^m05uJ2_?RMy8MaS&br&xX{nywd!Mb
zoV8hCD)wEhQ|J7I;8@hRVhhXh!Sy}a_}j9?IV=X_eQ|8sTzUomk;ch<-PSU(X<Cag
zKUy&oi)j!e(Oncb-<;ngXLkTlR&jToE3vqW?oOgy=gY%+x#|_<r_g?(Yq~RDBQPKN
zwhg(AtDUxw;q>>vlK!_MbLi*idl-0DKgLJEziL^>?U(os_+EQVNt3<JpsD&~8fWXR
z*-&zx>~=OheV*ELZO}fx0PyT!Pl$tEeZ6BtOZ!}<^V5@j+hv4ryKvrzbH!i54t*u9
z_&Gpv4~VzH;1#-idHkT0N5NGp%SAox{V0{s_1&oV<&Lgs*_;?&$<H4mFU`8*+vu3z
z#XbN-h+k_BDC>fM?$l(AedlxPL+nr07~!MlVaHDgwJ!}?!1syf&(@}FPH2;|2P=;5
zRwkYk7vq3M|1iu4kAWNcPqd}GCfvHQqfvfNNp~u09x8r9cBP~Fj%8x=_m_|dUEH0H
ztWk=Oz?JYNxwbMtMj6^S`Q=~FMHveIh4yO+2F-WWrubESgYI_o5T7Sq;b85!GlZwp
zzHC8B-}Ohl4|Iw)Cge**`crEuLAR=nvbJqsh`|iJ;Azc$_$*y?IPnkZmF$EYUlAYH
zm*h1nW3t10PY-q-E%1W|@^jHIeNE#)=l3{w%2*AK3mhElDw11l+(Ul?&2)DpdojkK
zCFL|O?SnJ>`qB07Ze`$D2k&V<U#us&H$CLfhUM^{$38Upf6dqTOtil4V6e7{6~%4a
z^Sw@gSUXGcb#Z*?_|7lh*pfWdUPFJ}&&vKCcxdHB@MrX0`n|w!Yh&<ec-}n>eI<w3
z>g*T&S~LH$zq%{8$-c$u-(1(Kd~+&EOKiU8ZEb9PXCwE;(sy%y%Jv-F`>TC>{3n0N
zy=lj2qu}3%x&!@#lCj1-Cz>S>t!eFJY#Nh%AN@C0Gp;d@<NxaDr!g9y|H9#UV4p>u
zDt##aeTL_o5w|{UGTOMu;*8?ib-FKgL1z{GUc<)Ge1Ej^^7Knce+&C^sH1OH>c93D
z==MgBFa8;q?H_mTM*Xe5hi?a$&=!6bZSNF4wNCsx-xmMHHfopLXfn1g8b_^hBQoIj
zuq!U9Iyn#XT-ADO2YL6f2Kc1EL%mYlQbNDh9o3fMb6p8OFS)1MywK@@7`_ZVOCQ$H
zbNK4Z11G>>_Yt4&ShHXD_~E~FtY3off4$1s2KcQH;^$n9pK}qutA5|ugS?GbXQz^(
z<kBqXNBJMy9@#Uu9lUMhSHb5t9{g)(lkNG-fgcB~K^J6Z#>?A4*d7M9DzKdmT>NU^
znR5R9SFxi!n{EC<@t9wi{YEd{?CnFnccaq_9G&|13jY+}BJwt`IRm|T)*5tE@qC`Q
z;hT#e+mB8intjyxwE=!i$96uo#(X4KMlyqK^yO97&+91f*Tm<0@TjcfXU$7pKk_e{
z#N<PII>g)`S+H0D|KVLaL-w^9?s$-2vVbkYFUioKllSd!+<RbbV)DLyZfy{IZ*5Y}
zZ1Q{;AI;+{ePxbE?Ey8MEsN4jck?|O=pD<@3nW8-j0_>)*)JE?%~$m5XVL|)E96h~
z^5tKY%35(9fPHkeV_R7R*rR#XjVoE(lfJccD)`*#xaLBB{~`EMUVd&0`($UnTHuWM
zyYcDO8_W*Q>aLG>z!SnL_)f<=<_Fl`I;9<jhN(--h!KQ44a~Po-Ml5!-hay4oeTI1
zO?0)jC%OP{2Hb*8Yj*kf*OgZjUi^1iAAeRWtBH^C!Q`h&zWh0R{AJTsrlY%lZq-K*
zXb%oHA9i<Ch>x&M{o^3^k`B|3;0)uTT;O~1+*}Esyjeaz|0}Vj`X4{SKB6J&^1MrV
z^z}UP->A#Cc1aU_=Hu`@17E-CfMRjXd9XQQpHi4-*xgUUuV6jF9&zy~G;R&+yb<$Y
z-i-#94&H$o-1u`zTMtQZw0@g&1Ngp5H(K+&D$rVT6==Q5(OQ18)~C!Lc-AL+`=+1e
z_YgieN_*}x`WwKTg?LLgF?S$aBia!=0^WTmrkro~M%GbQ;!nt@#&?we*ld9_Xt$C5
zV)Czz7jN>ss5zT>k$l_he>}3kzXOj^zb2edNY8VZ>9yF8^U?i7j`x#a-QaMia-x^|
zB(M3h1U)k4_{q}91NVY==3GyA-e;g`@E7fziRLk(JpD-j^wsh0+kPRQ`}+KT;5;9^
zC|!KVTG-t>+xRy(*tr&)CuFAq`y{Y06kvxB`{3Z+VCP>vx(IgqIV0GmgR>IY-{)ZO
z*M(j4;Wuwb_MnS+SNv7`8uT)r@bB+GV*KRJ*YOQ<Y^Q9V)<x}~by54z^{t=pK68V`
zpX5iE>d6wH#PAM1buP{3Z)@QxjfXUyZ8QGo&LQz%poyI~h3~Xy%F-BXNYi-pxun)P
zc^6;l9t1m=$h*m^{!?(L|BCx(p69>WD4LbT-b(ya(a`LhVupG?3mztxGX0P1TL$}Y
zNBiD>`$%>AVZUePEx@Mo;y3uUelh!5LY=>H-?g;$?rzukq`nIIS@3v%p2M@+%Io}A
z)X#54{b<fC97taD&#(SXd@Sl#u8d%S@A_bP-zi}Dku!kdnM=Tc-N?uA8_^hkBN_wi
zaL5EPeP~V)#_%Sc!8`j{;k90DKg^MD(K+0h4!;?-{hLwSnv>EFJe%v2HGjXS*N4%_
z>5}5S`Lz2mIT@gz%VYw-X!-{^Qyu7~{fEFP-kR-B*>^dK^PPVeG;R9*9XTJ_dVfKG
zg>y&ZHPKmjZ4#pjvZH(J<+sH$UCRGm{9D#yCU-pTpm^5G#A`Ff^W?;F<lD&aiD@jm
zW3mBFWYg^#{uO<L%xLW5QPr2dG+*x)d@<TIKU%hSp^KbGdmvvK<qKcPPGA1(d-((H
zWeGh5yWu~UA?&r_Go7XT4@9fP@uaO`^A4^Y-KZy>q&C<G>e8_JcGgE}qKn`S|7okb
z%AdapY4R!5pZY1KO%ZM%j|{LIECwU6q`;u(lU<8*NsrpQ^rTPA^Cf303%nKw<JsW#
zX~Ho+--N+yX|B9<ti#WMdE9{5r@<?k183p^^98hbLH$7U`eou>d=u<}!4=^=ABWOt
zBkUzG{XfqfR%fNvw#KM&={e9r<%NGs^Z$VkQCdz1U<vnqn;)XFdzb}R{c}#o4&pPV
zuX>4MyDO7-CY=WU-vswOHQ@KP>`B>hIQi6YdfC^1{CUarm2WyQzW)A^)|L0(ao!8?
zAAiXH@B6hMpL|8~qO_W<%^vBlMF-wE+4{`t$sN0%nSHzP{++`6qlNdwh4;q_?~fPW
zj}+dI7T%8)-j5gFPZZwg3-1es_mhS9ZvT5azjec^|2DOr_~&!RlTIHlCLdVk&g~07
zJGO7^dyn(<&Gy24|5o{cw>f`Ty0KL53bDEDm(Z`{Ni|LG7}A+4n+N>!jV)kv{`0T6
z_S_mBHjVPx1-lQ}9F6%vYp<J6iHBC9GfcmroAq9!9KPe}!9iKu(<(XPS+XR*Ol>H3
z823{;u1MG0ewsJX#_JmgYHw{A47L9t{qJ!S+kmLvsq!=0P^>q5Jw7jcY-;>xugCYJ
zuQj@}fOClEE9)KupKj+?C|BBcwEkw_iIYx6*4y$&`Szo}iDo(&Tx9>zx6QwvZ6CjM
zwD5fEfcB$(52|B6gRgHom3qNutFKZROMJ+EC#P%<Cf&290Sx>vL-*L;NS^!RKR?ln
zLo#257l^|u#>`mrIHcAd7>D6bW99b(?Sl$DxC`HnxVd5|p`OK~zv1>-i#JPoqG)6A
zQ}z*`6;9V^?-&0DxAr;lT!dS&>f2>`%oyG@8N0*7gP-L39w2Mq!v9!Je631+jbH7t
zDeXtI`v=vw&0YO?wRh3levfP0$_*#y^vbh$+w%qg;7h*3&I!vOu^5{BR-T@f|5(@V
zf4KKRWnvbegt^0)IQMrDn{iNeqkRz@(dqiuqG&VSc_}e+a1ro4u^c*RpR3?@{Z!lF
zvCTdC)N6zoi(+**!xvUgw#v#Av-9=Z?7^!=`!H0`#``|T%b9q4{)p2x751Qo{_j-(
zqL13i+a<0s+L0}SXMH<gh}wD7x5IoYw4-xA?%BgOBp*4df6kTpT(EKx`YRuAul%gy
ze{RgwJ!@k63&bZ?PWT)RWA^{pR$Cu0z}?qp!}U4H=BB5Rz29dHr84)be_Jvq*)mwm
z<P2E<#d21#X*2S{-%xASwxTQf<+8ONe4|I`FR^^qzqAIH=U?mcEtbvR?a+?klTM2D
zL+vMSTzpR(x-M^PvumrU*Q(N!|2T!ONZjRAeY~oq5Ac=u@r?35Z2w2-qwZ|+x{==6
z&{FF<!b=!$U!AoMmN+eAJtc=_rW_Vq5BeJ8eM{p&ZeNP)?~x5|kKtnw>#=`gJZbCg
zNlo#w2I<TN4=1d{-u8Rd+WTbl{2X<lJuk^G@CtNr`wsu$(tQ3}YD)@n$r|&zn)aX*
zgHtSYlh%iuJME4Vd)~0y&ClV#*?H5I#ET;Phd*v>tZNd-3x3U8bCw$V#Oz<NH_vmp
zHQ!2ew^OufwvqK%$z2AVc9-M=&(zChjs9h~^Vk!yGGe&sw{c<#%;(?585r_QaZ#K%
z&w~r?J0%93<KoH)7ZVXK7D{kIKZXm=LYQ1=|1k2_hl}6~{D8xS&eR(omT1rL;P)S8
zz-V`=#5fo<z7igpVgGUluOu&39JnObR#Hb}5I#cP&aJ9Dz*i`#Z?t%VeTKSA_F43g
z=*#xy0=MnU1$O7(a2Cbi5!H8o^yr^dZ4DScyAylobOCa3l637EB>iBVp8kLST-<=z
zQqkUdc!;^!H(;$T_&{+*(PH}D8(Q)e)X#3&!U}mj-y$7LEKSc%&J^1{HqctIH?cwa
zn8ZV*3wG@X$kSQJ$e))Dh#^NXl=8!Xc!Bs^eXbg5S>JXy5iu6^r+9(p7j5j9t-bM{
zu9BbP*WRFu@@zeZ=UjG)SKh6;->=^2;>wI$W4CXFiwD6=-X?g9?~pN_;?E6a3-~e1
z@L%XRoL36*AN)tdr`AX+1ZUKK)-^xUY@=cp=_=~dUx-%|XK{7>fBsHvNaYmENWatd
z?fSBs)6jNp%>CPUA@p7$f195J@t?;7x8LaQ@}f*B9f~}T4`(sE+wZBafd=MxzQEfq
zjfs6s#D?7XcsBZIe&X{qCox*-z0#^yF7xa3FO1qC-R4yxW+@oC11z_dFY1-8X-!RS
zfj{m0%<1IQMEjUtS=-}){~QO<-M-}sPD^o6qFX99M~4^ouzn_5@T;F#;tr{$_Q<g=
zoAcs_;0<izno-6@`l<={Z*zO}doEYH!xDQToaAZ0=F-F$woa*b#yhNUb+Kc>sPy~%
z9&)`4&-z!nhgjdUxb+ZwMW;;0EdI_qq4fhiM(dw+xHrCkbLdZffIHf@eg*fCt?$^H
zqw;iTy6wePf6z*??OT+#mhmYKUdiUSVn3PRez=Fz=1-C@{A$mS%8hhfU#tOS^SLdw
z^=rMG{0uu^E&J>}*betx`|MG79{U0I1R<ZgLq&XC<GpgV9|thxK1K|~Gdzq2cSmhb
z)XoA98w>xyXYob7r~Y04dLQ-g`tO6EdzVyC<0-=Zxd`shdAL7cfLrg!7_Y`6nu7D%
z@hPL5Vo%bMreBbI#eb}?lS-qU@&rquKXuo<gEbKH6(f+14ZM&c@16f4yStRlVSeuS
zmDix5`VKPDd<n1s<C;s+dzu%Dmhhp*ym_3M5C0*}#z9$wahQ54D;W7VJ85-0j(+!f
z{6T9gXLxjUwfekQW?X;GXVI2mn1jc)zun<1(Yl1<%~oISFn+Bq<?&tmHeAMV9G)`#
z<aKCcvtm~RV3U5!PBKQ<r)%5eC*P;(``&D80F<RI;tc*=t9#F77Z|NCj~6}Hxu-3s
z@i1eJ;I;f?F3ywtPO-mlx()j28wb$Z{6}oIaA9i^v}HI^n@Ur^`sb(fJ!;={X541c
z55XTco3Y*B>#s9i)C=uo_#4>*{Ge~5sO{9zA{&)FBIo4g_n2zm33dBo@A&Gbn{Mgp
zrono=H&*o(_|)u&=GSUla^CII2Xc=72>sdK8Q-_%583&c{H}s>JPeQx<30M)czqvv
zU+|0R6XgL%o}NVf$g|}U(<!BEfd<){xdUzwfOPcs>MZqz|8%rP9BAD6Kd-xSt>!I#
zY1rOHY1m7p8L!~W@SSD1j|9HX_~mx`CEiYxW_DWt;!pi!w=#Ud;CBW4J0rM+V?Xva
z|Db(CZm&u0T}P{}-`Ug}sEdm8D&}rZ=lV8jS9ccm-IE-rad*%p_x<j&zI*$~wJ%L~
zC<)&t3&5Y@2PP|~frb4*ypO}foaeJUn49PLeGJ<oJ-*HB@lKT1Iok7AfHn40?2aJr
z;1X?6V?$;W;Th?XzWZbg_1fAqcDa+0uznrj7pyxOoA%y?G42Gnw%<u@pMcjCBMf$m
zG_y~7mrUw?*ypR9-j%L=rRzP|xr*6R(!kT`b%SYEyhFsFlg`*fCtcGVCWg<m@q|wk
z-`f3T;uB=md>FwHV8_0g-hf{C4etAJ!~RZRJ0G#1c<uhiH5<I%mhDhmRu8)(`pe(Y
zzol86vw?3iVRu_tS?c8Zku6f1d~M2@&y7x%k7(^P9>H$9@QV>2d=Xntdh<t<yv@7l
zx6a*)l^^!@SbIa&wqVu2bQHhbpW|*s`FX3PL+#mO5l%0@6gdnr;-B|2>Bp;mG8uc@
zv@i3Tr#ZMaX7kss_wbbTIl;WDesz=|@Mrro96k((A>GA_dpHbZ3HhNO>Be))7f*$J
z-BYPNOY=C@yYl(f#2cy;<M;~^j=$h=T>prR>ok8MVPD^rtBd^F`CiGj=VOy|_*t@T
zZR($&Y+gRcAir;Z2@fhS?DvyTKXU=+Ykn8n8Gp8V`;vGM^E~-ux-U4FJN0FI-1#r#
zKeZ*AsGQ}4o6w%}(vm!%W;R##geU!<?9NHPn%W=ldDZyyV1&Da;EuBOFM_+!H)DtQ
z&`-U-bG(Qa;?3gROX;zW5lo~RP4!<%dhP37W1M&Jg)%m7wL|;%duih{*n`#ix6@za
z`P-K<-N0QwiX$29`abar+ExAtIKcPSJj-w<9FCF4`^;*;_mJmBHX}~+HY3b?OqY^h
z)V<j;Z##~vzsPp*zEXIg4r?+7qm5heL0i@^T$;)dBWw@(y`{{l40psn>^vSmy5?D{
z#(3xd&g1TUm(9~OS0&B)^aK3(Xsr{wPJD>i6YF5c!wEbb?`c}f*OL#4U6(8taS&wn
zIrw$WD}a+eY=5m}nDWAN)&)=4C&MRcVK1)QQd&Ci)^=ZL{1u%^wKg1%<-cfdZ~XUW
z7l#eHWK#16c-i<#{4XA(uJN(bc@J}+QXjH-r;|T#Y5ast*>_4rJ3W6k-0%60i9A2P
zpD>gQ_Y*Q+D<{AA3l+zsdM>u3v|>9-3+-rJw4IKHZ;3_Ug(#-ej`=*&b>y*b;J-iC
zU#BnK*U`O>s<Q>!DE=Jw;!QxC=BpEfe~bJgotGi4erZx2#~;u=kj$YId<{EWo-K5t
z)yjrwX8z!>6OZ}WwC$gk%r<|DwxoBMpV!3q{F*=R(}*Jk8CIOmWEr{9H!GX}Uhmk7
zRo9zr%w9;J*yhR$kq5!;VY7P;zn`+d?bh=vYsrTv#%V|QR?1&&YHsG!^sak{^lo|s
zx`lgKd$iiYcu3Fb<lp_>t99+$qyA3tqPsAykFvYa_?}DPN0qnp80r`P3b@z?4r2T(
z_T0Px_`p*bv!2uC@QC)jWA8ifz1DD&p3|SEdA7~}iQ(Em^DX-y^Z%@K*gHDK{(a0S
z*Zs&t?8mB1sT>vd-ekA2j(83*^KWwi{*hm|r~a+@C~x0=K=b3)Mrg_Y5Z&uiBTZ$@
z-csK7XYe2JRoZW1zMK7qr+JuH!V|KIb=gDktaymg8Jq_FrSAsjbC6gU7SDx5x<PgG
z@rZuQJ9bt<b6?XvO5>b}#u&zAzQd0Q&(RzJo)TXvj@nm_yU3NE9mT%M50;(LKWXNp
z>wVb2%g*Q>U1$0F*L&*URZj2#+lpjIwSI2m%X610co46JIfe5fd|T)p8;kn%ZCjs8
zm)=#n+E!oa8S(F~V^jD{tz;$kPko9<Q*0$=(FyMS$@KnfTj9<x7f*-B@TvR8uRX86
zKIzruUU#o&&hywb@qDP0)33Oe8lCB?t>XN*&UGEeraij#Q0+T=4rPaXuuG<10gmdQ
zV2;AG*0;63YIBcI|526wdeyi5>F~1j?%`$A{L*`S|3^RJ-t~XqN8PjX<KIik)6e?!
zw6L*#<R->}?E{wDx!_YU`G31#`#YTT0H0y3dxcMxW&a5K42RO^KJ+y7EpXa;>O|*f
zZ)$ON$;yW_OS1dzQSAOU$uH|yZ|9s9cxbKQ4n@(AUtZ=-D&yr4o}Yf5;B&HTb^il(
zfhjNlYWHsb7kXH_IM4ezpNH;k2)6-_7cbHOkCO-fwGO3w<J6vfL)Dd!Z+E!(w0tkJ
z?v=%+*gBhR3w)Q&cinxIdZ#V(9eJ)FiFB~uX?NxlaB~y=3K!Iq%;_6MeSI&`w|uYA
zx9qaYFHl}`z`NGdM4O$<xVO^#Hi5RgNOO6u>U)7FPB*xHy_vAz&GSU4=XjreQp38}
z2^v;`_t6N~D@t&h0uN^iC10}_GR6_gh<5D%39!gky%TtZ2kk4U9A}Ig7c{fEjPC6-
z*w7WeY?HFH!r8;*(Vog0eMj8-h4I=y_`DI?5zb<~0e3dcy$-Y+^iq(8Yetguv<A|y
z)BYD}!^-yX)hqA5Gd}&>@VoB&<R?8E#%ua^KlPO-{iSv^56jyt!~rawa+Eh6>+xpw
zMdLB@pt1SU&!!*Y2)@*PX*S0SJg9i9@gU_x8GXOK$cMU5i94G6>T0cD<*sa1?cAHz
z!}NXy{fzdW<uBO!ZODgyIe$M)y9Il$HtO7A-PadB!IEuPe1CD<+<_JBv9%dw=NCPm
zPk^Ti;}%_^yT#k>nKa>b+~;}yr!~G@*KpTp=W+Lao}h0k>wUYlWpfMd9}74YKJ1w`
zNjG1gJ#IOT1ixqxuFO7%GTPfg3_Cyn=hM}O$#UB1!9@Eb_~NpWx;IZeYG(nleE~+<
zLGAU`f8{B%@5tr``iOO;VtA61NEUKks69!8ba6%=a<eO;ed?zvKJReH?9)NovNgDX
z1In4+N~xnXmGfx^6Y2TdB7WX%)=JVYccct+N6HX)r09N>5r02Qah(`@Tf?81O;#M=
zbaM(!jCsBE`cPQ69N-@o*Z=*z68$ZlI=_(T%;uVkF<wnPn!fnOz7am5oo7?J;tQ%9
z*8lJ23}^~0rGDaf*n7H?y{9XP-}9@%YqiJl0S?nAJi<KGonJ=2B_npXvFIs(5&zM2
zyZm|5%$De%Up>CtIF#d@g79pxZW3+58~m1h@F^{|V{s99t-ca{3w?lj$lLC!#pYRW
z2QKSVxYqe&l@mT}T}b@O^UN^wVzmuzl1HO^KP4CR11)WSWN@%X)5Eiar*#Q9mTqAV
z=hg&0E=ddLZ8I;=)`rau2E-eRv3lC95#LY@Ima#d%5kf)m@nQnJT}YbN-=J`zFdr3
ztvk_X-~;n@)F-?(eK}(T2RVQ6Y-1AL7P{2IK8u%@8q-p1{NU(G8`o<Y7yh3348B0d
zJn#6i8V|zfX0t_W(%YjEt#5I7*~$D`_L^l4cdtL?w$z<23v+wZAEeI?NA-zK2VSu?
zP4e@$Xw%lsNSnFH)d@H@d_L3loic|dy*mAS?w+DW{o*IsIMB__zjrZQ>1o-EzV=wl
zPt)n4nPI<X0v*NM+K&^;shvJvZ#WpTi?NCD-;DOEiN{~fyn}viZShtgS0vxXP#xcN
zZsq&p_?~v>nED#&xEO@d!tIaFbaq^KVk6UiaswPo>Y(DDNiQSJo1R=b(VmavZhWSL
zVtR@<);U__G#(<&^VRId5nsH#pRdG!X5VSg$sl&`r~1oizG?UIS)Y=*kGr!R@@+{o
z-<E%)JvP*M$j^P%rs+7r&bpZCxIljoUmxASx5u}^j!eJp>X!N01|zieebp~4j9GX<
zA1l8P5Av@_3wQ|fP~`8vI`TVwKf0ewIy;W7guFTUGwds~`NGK(+?4QGAFh_tUxhW}
znz!NT#Y6ZJL&%Zcbte1KX%4tgb%{1+M^3Yi;&*PKWeu7V=X>(++5Y#AAI;|C6HUlh
z@%z^T&0;;8HX?qX>G9Jb9VA)?9t`@(c=&qPZ*~-0GuCnZFx=AJ&9cq-JnSn*uiIW^
zbdc<1J)9E`{uTauumk2}q4VTd6!nhHwU|dpFRFd-Pgq>g^c1$l{KkYiZE;>u<S*a|
zvY*XAK|2}gwc4@nldIeQU5`ehh0z(?Y<tl(7l+4k-S@_8^84nR-1T5`=zW1c+HLl<
zy98cgZkMt~qq9l59=W9B>M9?a4CH}zw1X{~K%d%PT(jxDx;Kj+6RylbbZJ=`ote?S
z_iE=(Xlrq^+&6GKGy@KQx2t`tu5T<xZ|B!(4p8bF7yX?7o%G{wFv075w{p65IuYHj
zT7qu64<X=Nw3iMRjZ&T^165>O_`HyEKF_UnKojyUPq7Z#FnV}<U~R}>u`)?j_qv4o
zE`A!-Pu+MlCow&sxu)mKK$n4ZDC)@~9e~T`M966Dd#e3hm%$^pS3TIrWsyFUj)-6p
z&eP*vTQ5~CQD^P56FuED{g0>VL&IajS=Q}p4Vid%$$5a{z7Tw<+A(avQEb4GE^~z`
zo7bB!MqBy#&}pS}2GUP!&Y*JfoI&gIq)AT%zDtiz9b#Q}&gRMv4-M%JbTn&=%q4^e
z>1fT16gT7F{6c@%emKLHg}d;{r|oK=Zy59{eP{FC-uy$j(_H=J6UUu!Uy3hi{V$%s
z{%8+h!rS7tsgCUF#2j)(OmRXnsk**f22B~4-A9#aed-f@p8<P1{iSEvoYVGy3K!U8
z`G~?-LL6N4QNir&9P^rZ4y(De=mfs(yBO4O*CYPEiu_@|A+W;xjU&^1Qy_7EW0$`8
znU1Aiu-PV~#9#1@9RE4mnLaA;#DsVv>u$BV{PcS~Ptaylu^;(Rwy)ODp_igJePl<M
zp!c_lRjeXbv65H?zZ(1*zQa^|3|aB8#xxggN_Bw78tZ_cU7DU|H}QE{mtie8IhfHO
z@sUGzmoIR1-VYtw!<7Ca=g{CU^=mQE=YRwMti9kSFW_K&xtoJFr^%1rRoCt#R(uZL
z=lq9TPeRAaU$$5w&)|GcJdw-lvF@D3`hvbX;`No}R5U>rRMuibJnOuR<l~kL;7jRn
zo(~T5Ed40jDGj)#56muT4Cur>KA`v;FxZ-z;5p&wCYVeQ9N}GijET==k9RH2_Hb!j
zUH`6p@gHe*z5$oVPf07)mH)<KDV?8o_BY2XILdv*g$P$m%|(jwKWv-$A?IQEp;XV4
zep-57<zhXrI526kp3f8)+EQZE!o2fL;HRzH!dAXtBL4IK3-1}@3g;bid_iZ$dMySk
z-vOM7_biUfznc??k5(cBTh*RB|3F?Tf1C=J&?jZBM=};*>%*<SuO!~2TwVJh_}84$
zWK#Z$U_y@@&+=Sn4x5j~+AOi}MISPn<4Jy+$QQEb>;ZYx?{{ZHD)>v;aqy-z&adTt
z27LX1gNM6SES7aqvYWd(cGFhZ_P7~NZ$=-j^?R0qPjt`mO-#V}AfbP7Yx_~y7p?ut
z;}`8d5Wd-A>piNAeA}K^o_A^PZ~Daf+1qtSL}kF8(T-=^_pE=-0|G74QKDtv98WkF
zzL|TDyq|ujh&OQ7HM^62o`rd!>{qTMXj^*yg^WMUKU~ZNe0`5%8^m0oS!=(}aXUCi
z8xGD=-YL%KJs)da?F3tTs=2Dh$nQ+so-JuRtXb#d_ia0SiXHHGdnt}*>y^MLTfzOY
zjt+Xh$Uoypyf<;rMoVzLYACV${Dk)%L$m=;=~=j)8EXA6>fSw0va783-rZeY(@9TH
zIxsc6bF1_ulV)<83?w9B64FgFL4+U?5hEauuL1D@uQ?vBL7am0K*BJbpn!m&qaRQd
z5kw9MNK%jv#6#2xFJi)*K#yGI8m^gpz2Dz&t+jhqb=AyZ#Ls*F*q^=jx<2b!&uu;H
zvZ0I4;<jeEx2|u0`kWK<7^^P+rKWJwxn8S#c!(=c3ce(dzw83}9ib2VA=7vAL%wKf
z|8C=?P(JM8!5(@ydwR$}_nZy9={vT){cSNUIWhOO%R(CSoGOj5(sUPoiM>+MJZJ7I
z+LPXU3$#c5J_pQO`4ips#YeAR5|4LgEw@Yk3zG4%y$KJAo-DUDW|AcyJLo_6=@VD2
zfxQtvl}=?G?N?;)kY$77P7eKP{}#U4_$@wd?zwfU$^(t4&s842Qy!J+wOeiHz-LO^
zoM=;Z4^s|2SF}kV?V|zb_H8N;<L|xQgwyyNX89DdxRulu&d5OnH=%blZamFLgnYJr
zr>Sf0@^aR%d0lhVH52lUBM;=)PqNVegkles?GVwoWGZF5e3V&ThE?~@X&)B(b(gFC
zn&c_jKW5)|%wNeJz9n}oZ<uHI+cTy%jT`OzB79VM#Rf1=MkzyBI9leTim<59<}>)(
z^Me@Q3u7r=f^1a1ed%}rU(XLm`KNK}rGv;Ped{}nOilD5xU02?mqeb2{^j?b&-Z%}
zmwe)zhkknUxZ*QpqSk@yrvyEj;C-!VT>K%v1sCIddo78#?P&CdXj=BO_JMfZqF;nN
zS|6Mq>0NuKEx}R27IEo2Fhnm8?S@@^C%9_tAIagG?*muG=Sc@^><7_J?;3JE+oJ!!
z`X7LuS>`IU&^_&9H+T;Ou%@|?_6XQlJI5Xz%@;DfnyzI-D4x47t;^wuRqR{zKA7_<
z!`yad8W-h5R<7i+Pq1Hov?o}COdl<@uhz1GyfyCYvi{Ke9N*)7C;rm@s1#T67I`L4
zXb1S};I|%OCG5En>7GOFWh@A%u@Zb9i!pElzt+Fkoi17A`-~`)<HP;b7*5A>U!t7m
zPsDB3xT>x%5C=|-JLN5ylS=;mOlYIRqw3baSbS4!65QHfm&I2&qP*jK$A<dLgB|<n
z*Ki(8vTE{~ukgR-B}2y)K9fAL&W-v$BYao5n4_=L#AzIn;l8Vg{9Wm4C#G8mKu0rg
zhsTCvpWhn#HqKad$qnjB<CDhLdnSpm?1|T%*Q#%wW&Xk0*=M$ju5l7<{n~D2ZNL0M
zw!MY6CFAAq0<K=2Y~PXAJoa!dBAt<w{NeGqpBQlv*S9@y+7oQ;lD!<FXRmiqx9EBG
zbmXImoB9grt?{C_?(#>Su)kG%E{eAI6nTFu-wk~qVBCS(^LpS{SY@nlwPy$z1Y?@d
z+0N9rWC?WIlwIh$xl3ULybJ#yOM4ICYxvS*4V>cX)iv5AY&$m5H@rMgS=+AALW$p@
zp>xVA1Faet^3%vag<P`DLffvpPW!IAJ-M)7=Pknd1=TP6t+8*`bgg@j1@BB9A4NUt
zc;*&;bv^YRH4TD?VAG>BbgqRq`s&dm$=8Fx8T;!q0>}f`%Nt*n`Np!~F$J<M+heV9
z;L*5vPv8fGES2m@w77Ys9ds6B(M4A|J|!D?{2!+{p0;aMKVy*QU-o6ixGEi+QuB>C
zFJ!-3+(Q7Jlt0R7N%fM?bcfAR-A57Io2k)H!9ZW!C(aY--GyJ$>o3<nEYAJc0?*ct
z7kqI)hQ^NXW%8c5E_r`^JJ1b2yryhh;lAD@`-KzYE&HDm^jam)B;y_*&U>af%X`t8
z>H=rEU12>Tc`x`MLtUxQmvq;m{VZLw3b|$ZsB+Si?q47I82giOQOQU8C)^a0kAI7d
z5^R&uhQ^RbZF$eg%a-P9-tQjyEA>Hro4K66sT_UZLjQd4PW*-@Lp{GsJ?Z@Be5?~b
zcX`$urRU6xDrdU#zLTQV9PP7l9nv)44s9_ewsTGoW9_|;sjT+tYkZC+uj<vB7Vol?
zXpC?y?|AV<ojk&U@=UfTeU>uPqG??95$`-1o-}^$`+mx;XmcK5cCm3_cCr3Pz?E=9
z{a!PT-;4TA_<eQ6Mb2Ba<-HN#jdy^`$3dKJWWk7E*LJGIz=V7bYf!-#;&p<aw2CK(
z$&Y?rmfyHrN~`jZ#5nx9N6pIxW#I8HebQ5Zk{iuw@+LYMExN{5xU4@S;&BCIB-&HI
zG_I}>8qUZ1XvT|w&*kG~e@ou}zRsdym;V|()wSPFZ3z$R(~Zy;-##0X`jq;rc;Pp}
znBw_1EqY8CJL&t_W>`0({u5*UsXzLT`RxZHEP1jT+Dr5(dhojJfedEpYT&SLjWmTl
zZT&m*bmV4gS9TityiTlkM8BeYogqRWB>uh%TDANoPuh#$x^QDF&*Qm=?ow4fL*!o-
z!nNUU{Zh?4qOPtVPR}B@mf3p!WEt|WuU_q)PeB_Ee4!dc<_DE;#{C->E~3wg^hzdy
zpJYes{DJVbFckYlSaPb%Z$cfiL6TkF7p~rUGix}~ZNjbPnRJ)hh2AUO#rHVhUAimA
zRl1As3FJ>neeHSq&{U=ehba&5RDU>Qgp9@SRvQa@a*d04_h0gn3&#1A=zCpl1b8Le
z-JZ_j5oaAvx^!^gzW1*6=j-8}S=(*XEo9@984qaiaSE>u;Ty3fw0GF?;Jx_=Av_Je
zH6I(pioYU+cQVG!H{eg(AL!ZtPrNjihmX?!h-qw3`87R9qs{4QzR!*I%@ID2v~R>Z
zM&~D+K931(3QKQMX6F!LtpyUkL*da7Ug&&u@?C=C^VD%(tfNNyd-?vC@V%(BY3~mC
z$A$=NK1@AZRR3%U?^Jj*W$uV|DBo{~wCUnz@1d!GoHW_!;KT9(*)@TDa2znqs9xgA
z8gbOW>3!J4e9IoLe~_|HYmwGj+_dqN*vp@Eey9I+X!n`|I7UJ};)}Z0EGZ}2E%$UZ
zkC6YL2fO0W@c;gCusu!JZx8Ts*SYK60Wa6z9Lig+f$Idf<=X308ut6GnI5D)r{5In
z6Fl<=!@uC`^C3>Y*VNy>bzgskx_{gCggsPykqf`WzgFRy`t$m<`5RfA^?)1CXNo(P
z@b}Eno^T)bf@Zk?rI6M;FSM^#eH+C#RNGICbuhlx&B!UQIg9UjgonyEba{ZO3pbAr
zaTRVTGd_+!N%X?^#5iMeKKYymtcNnZr}VP}97lwAZOA8jOuit)D;>_$1@9X2Djxoo
zJyrEt_o0fW8Bfy&c_yU$c^mfP6-)7g9oe~AYk<NR>m8Cql7oF^QSUid#<{^9oHgyR
z*8p8+KRvWnzleH(V^Q?~I>wmrnD~4{2wR4<Lill#C(?!FnU*}dKE^979wgqf={qqG
z_-X$4f_3=N#+c;X)X-#oG4y>JzG(httV7{ghvnI?$2z8o|9R>-Hq^02a9$VEZdCYx
z#C$FCJ(YZHD>r<SMLS~M3YQ^ldG_ZaY<ZU2RG*&`;<qUL7V7$Tgmakh=Z3UNg=70$
z6jna@vV=pmvpVD(lU$2+Z&Cb{Li|pJ(E;_(#WIqSsjrfKe;M<s{A<W}C;5<R`FzX#
zPn_t_=ORTnjH%|B^-sj}XV-lwoRLcLe@{IMi?>vkv0OP#IletNC2kzuq4m>~3%1qr
zIBkeJ-xFZ4e5IehyFc3PZu6ZneNCk0)aD<@_*FgeZ;9~_?TP>W7!U6zJJ9v-i1Enc
zuJ~8Sc;t0g{3}9y;Nv#;9<--wi=8lU5{_OP%hi|gCY&_t;9K&M@DXLeb7CEm0mu*A
z2*)hRgDx5HE9Av?4SQ!gOJgPZNL$;ZA9g~pJvqjqLo{BFlYAuKZPd@c(B=KPGM4f9
z#q%Mx!sWeYqk1nTkH>{RKFZ;+cF!K5xz9x%Ao)l;rVZ`$@2x}fG1aj?<UJyunz2sd
zNpet+@Fbng(}gGb{i(l8wrk%9`6Lt5dc`uhu(d0=(A$!el92=D<AC*|%@;-+5V;!W
z1K5Drz2RK?0K0EMU7F)=M!r_OLY>m>g2{Rte3)jl__V$!yLF(Q*=zg9wG^#UOE;)~
z{ew#WvQle0`5Bqlg!wpggrQRN1^QN88|>-c{;HlF9?1gF+w(Kf#JNvS%g#V&@!~0!
z?X9b7PcX{HRvz<lI3M*N#d()r&v0v;CpnbGcfqATCm7<m8xNK{4~7;p+7&)%$MATc
zBz}zy9@9;Z<E}Jpnw5vA8^ilx`Y>P)7tVWSvIm(r(v&=ERrkuIJ9=*DiT`rZn%wuV
zW6<Qb>FalmPOf=+d$QW!L;nQx%ryZo_WR<at@b#uuSc@=hGPQnc+ZaHE%xSSud`xr
zQr^CG;>RP8P3X<H@SM*hO|L3H9O|=AL*-)q6MC;@9bI*f6P}J?)|WKLFXcaG9-8>Z
z`-D{AXsj>32hE=~ud4QJ99x9_LeQH1`|yDH!0Uh1IWisU9F1??32z^8wExWGqEmQW
za8)>CUx;~I`#(l{%M3U(V7bEn)DiZlQm6b0I#(ok%1&poaT2fqlh^jZjmBQSh9tvA
zn*rAHWZsnVJ|6OU-b|eL2lFjD%FA7u%AFF+>7B|EuH;~TkBj%q0qZER9st(;jEQ_h
zl7SJ2mWAk=%7@AR5zpyV_sQhbm>ujas@#nJzo)Qp&-$$QM65%9kjM7+w`YUBO?~!P
zsjT`*U1`6P@Ug&t2IGTzgpa!R<tcCMQ`+Yw9OQY81GRNZVH`WZzSV}_Cly}zwXL7y
zVW93oPGH}qu}ONTSGHBS?Y(2=aP`7Z%j!K^`Pk<UGx>g24=>dzKTieMQS{a2GhJ#w
z5#!SBU+S6fk>1r#Z~uFBY~%;gNAgwKF9`omY@6Oy+ctfdeN9fMtz7RDXPEM`z-ziB
z&i;hM>HA)Jobx9A(3nb>C%=UKlZt0d%7a<_Z~<P~TR65fcMS9p_NApcrPkB>&M8e3
z@SN@;PWYf5^EYz@;Rg9Wd0nwfcLy+kxEWd5!I#{cg5N`(M;uRNS@cDEAExRbp>E!~
z2ce>i-tp?i5jI7GzKeHs&sO^9Vp-2@q*d6#$VS!ewI97>xXHiKtF)|)$}5e0)J^@g
zQ+(yTmj0`l@Yff2hl6kZ0Qi_YRxrRL$+i=$h5>xzlM3>}{1fkQQXKuTjjaA0WDMXb
z*QGN0*1QMYRQQmLsTYb1>&-{oufv>wuGR2WP_J>1{cbr5?FlyPUeeP3HpgXn_Py1T
z=ZUWsmafr$5Ab4HFPh8ZC6mG!tgy`0nr-zz(4S#Haen4pFz{%eQRTTT!Zy;v2h&+(
z>(dDnMRELg-b_D_A0Og-h;QCIc#jYBJ<K=n9lXc6$996dXtwk3%^i_ueMVDuhT-Jx
zzS9q_vk<4bt<%(ZjSY{^BUNLiagXs`<KAHm)0nDmeQQirKXuK}uM{@jfd5Dj!S9F8
zOmtiE=8<?R^1N(<y8MEI3%awf8G7-$HgWYWF%3OoKcD<X%FDNXLlaBi)p}}7m(Shn
zvae&FlGamyKg?Oo%Z~{Cs$}pqeLa^rXvs7cVM=zW?%I&8R*uZA^}ANA-E_w>XKuQK
z`$$if&ZnHl%H`v@sE#AuEv#|N+XC+%%K>oM#>{b4Mp`>eJsvOBcPNZ)B@5!W+P4iO
zI1>GkKh3wAf1o}7M?YsZpVE(nTdy6luJ7@9Qy2rSX_>BU_l5aTF&@^AObhG<PU*UX
z@38-y?cIAE?Ks0Bn$F}wCCef|)GsPH3o*M`e`J6s?IjmK8{RiZnh}n~6M9lv`7QJf
z?TXJgJQO<cH)D!@=QUTp)7~G`hvM_KQNgFNOZoZM_<P?Xb*B2gzlc1`_+RUwu}leH
znRhhS8b858nKl1_Z+0cHrnVx?hVO7?$yf0|eVpO$D8XZ&q3Y^%mSn{t!nqvLH*(}Z
zJZ|jMZJlyfE7;cTbzIR3@JD?EKClDA9bc`Xvs&(39A}MZ`Zg`;tcLnoM;=DHvn&)I
za@t6;j=rY<9prm0d_E95@O~Q61N8~#-nS%t6pSNy&+&TL{`cx~<cn!m<Cnwr5Vb=b
z`1QCZovZc~54>(uWA3;m8EW2E9-ij+kHAO2edr5~9UuQ<<F!LytnoBneA({Ci+*=^
z<At~EZoJ@-{r$B|um^AJxs&K6w=9b*Uwn(#)@w?83_hY4|L)QrycdyHXB{S_O*)-+
zWOsUx-V3wzSGGd>3$t|XO@F~HLFY?mQBQLvIQlSe&4c&x)|iuL75k6%);v)@Kef@`
zShjSx8eyO1^xTR({_l=xK=o7ahKXQrPHf|!df4T<ucmfMXHjrNdtSe5J!4}l$%PsH
zo1>af$8(0@eT~)&5<Y}K@FChQ!LR$9@DbA7U#Gt)rYC$TJ>tXZFO2E5(brb&T}R%F
zEvvPggR|aygYCUo*LoM_tzU&R!q%-ZEIdlDix0&+^C^sPRP{(NsLZ;@w8EOG_JiyX
z^yaud9rA=dB9^n@U9wX6)tKmRQKic!E3t!31J`YAdEd^Ue4Gh$zP~|Vz;~+0YiF@e
z^R{3hKFy)m{2RV<;B;Qz3hyGl*+!;OM_>H)o~4678wbE2coQGy=Mz<jaR^;2Y#go)
z;h8ItJIR(|E+v@?9EIqn{xt9b-105iC(XMnT|Ru$HP6reV_kWEHssO1y=wkTnF;*<
zb**s{uJ$`CET5k2-zng8T06XnpOFqDF2SQc9!V!k&WvM6SHAPnP(I~dS?huQ^w4&i
z8_vCkJ#_Nnt4*D`?JYmqQ(iuN<wX|yY<&#pcjG8+5xAtUE1W{7Di{31>}#amM5len
zxp(f7#(Dp(+(pyz+)uRR@k;+S8UbgFv*Me~4@6J0OKrm{obqdJ7Fw+A4)TcplZ{>J
zp_pIm6V|!BH7ArWPkL7L*4%w7GUw>+umn@DU%DIv_6TqCox@L4_MJOEOOO8Fls>Ti
zUR?(4nm1d<JPaHhqz}|B{_EoTL!HGY_h0&qQA}6f?tH)_+q=8`bkKF(Jk1)Fb)@ir
z;Wzo840uy`fwf45RVM6N%*w?)!t;gya;xv>>q{qx@#UzE_0X^Nkm!`}&CK;m`qyCI
zr*~JMXv?smFLYjMAYOA{YK~JTl!wJBzDM!HVf*@B(Npx{=Kho;^iz1+p#A0asb@?q
z$K@MUpYTf-eermhJq6`na5vGK6fc=KSR<Z!Tj9Mp!l`*sd+(ryQg#sOk^x~p-wN?D
zpWsw|O`TzjdfDZWVddV=;>;zHZ~0C-+;vj-c4SJh7qG9hHY$7cOxhwo<<nTKSsnic
zbX)d6joaeCfEM-`)|6j!0G+#T5WjE+y5QA1qlYeK&tJGJ0{_}yX^gje&%SNk*q+*|
z{+mGDj^Ts{-Up@20?bLqB)qA;@>3aXpNg>EF#tB=y|2{$4{hY|hcO7aPkUEZofXC)
z<tq<xe?yuVX}k_Z_`q?3PkEKE>Jw@1QwLm}Cfh#hd+dDAi%3s>O5-VeKzWnx5&S*K
z{&OhLT*5YbqK8i}rw7|pTE9M@HWICf7J=;!=t+BA?DNF`V;U8W2`|_;`kv7p{|Qej
z$Nq(x<p19k%TU+ds;gdf(Sqg^u6tw5x26xSsk0H|uYfmX3us>5ke(3S>L>3C2ZANR
zh&-xvG-a({B2Hw}C0$vv_F+7}mo=cn_3Lx`Pgl~fOKYqpu=M5kFLGzebo+~qQ}Oxo
zG`@^(_!7F|;B2r%_wjy!=f^xhif4vDmeJ|QBAsr{;<iGwU#5@v*b?ui`|96^9b_DT
z8Qy`0S|0~Dd0vGXi}l!I%4fd#L{|4Fp!+9}S(c>#!8E={nN-L9F)TTv=YHfNHh}#F
zZ;k!}@{GiB+H_aV<0ZY<_%3C6HsVi`&7yGmJ$Qt<hT-^l2FJ%^zkB{IHvdaOUes3u
zBV|>G{R4uL$2KqRn}<ldPHmkZ+VVZg-yz?3w(dqhg@279GbA?z&-~M3-3Re~euuh=
zxBo(Yr?2Dc6T0*bzxJWR|FwuXsnLe+rLEVXrxXW%tGjCD3#C4tanZfBqBGBZoVOix
zHe+JhMV$AID{VMSldnT*ilcvt56tr#6X^l{OC^Orll_w=#Z~|4V68XB`9B@u+cHV<
zE3&#2?yXC4y>%%ruWLnsb31!ftV^gPjZGCt9r`Crir=9%WA(ej^{tar;6?vaS;A|`
zvxFn&$Unxu$#7%8BmEd>T<+{_J>Gq-wfx@hxLdJL+68MN{x1vndu?QF_*dHa^au2R
z<n&(__}qGlw|FJ#_WEm96t(9@S~(wDAw9p_N3^t%($6Lxxi6lxo&LO7?%G%mnz9@N
z-Xy1lZ{bXPlmvSf559~`aMt)XbxQs*@6bGD<{WUuUg_56^L*Ej(%jzvi0wU&_Bh`n
zJIr^&t1Ni7ogw(Y)CuPg6c3KxOg`_WRvJ8B*7yfx4S2r9x5i0tV7Cn|+9aRo$M_P=
zqvRoOhv-0cKnF=r8uy}O@Zz=FCO!v+RR*53-znnE^UBdecnE7n_&4Wf&c`=43tZHz
z`juCEQkd5@zC~Dl80TAi>lB6;Z6h&;A&oLwe9(EE1O5Sdd3-;{4`zcOO?%2zzxL!&
zfB6IC9cw1&EdSHB(Lnb_Sf{{e^M|y-oaavLINzyxKi`5g>VMVK{3c}>znOn0O=VZN
zCd+Sk7Mov*bsg6Z@tP+t5+{5@KN|by(_?)-{a*FCR?&qI%DT_Hh*ulhcM#jU@Y7M=
z-jm7Od(bILXRbXX|3{A7Q$t-oBLe<gKYxD9^7@~%^8Xy=^)BjR3@RH>-{9KotKSN;
z&%W-ge(v;wf1{lu81${T`mgyVVXb4<S0G;%56ye7sj%jAPUlTK>AdzzWbTaUCbn%G
z2mbIpPh+q3-UFS*@;K%vdaq(%y8aFL8f2kp?56Wu^;g%saSDw!e<zL+{GoEqm*nGv
z98%q;y<<W+(B8DqS38Y)k=`*r(cXp627dLYK^yq-jNdym{N5>@pKui6drrM@zRzd*
zJ|D+X_EJVS)-A#l@h)>qR_2yCcDGWtr;PG86c5Z^3&*ag?4%gig<ELfYx*k+_ec8;
zt9?VX@BQPPp;cd%_6G21K8<Ms2N4%*z!mZ338uek`_jJ2x5|P)%R<)5U7q+=k{_{N
zrFrdz*>#HRg(Jkb<Nl|phblNCj>n(@!2thlDcX|ZQ}%DY3wnGJa~Aa%zL#COa7&c6
z-yRL|(5Zb@x5oH)g?Rgwlt0DqCSLqNe&M#b<t*PHvAG?~-80&~?)nY#@<_hdJ|6Sz
zq7KPfWO60Hr4z_kt)HqKe9`!K-aPZ@K<$fF*fO3qSM3iFEaSo@@jH~RdV#I+72Yu%
z)+=MVq#M40&B;8y{ffDkWr*^Ar4#m)eFM3{zgFfy8R30Lgg5D(m@eKc-l2crBD=x6
z|6wTnuY@n4sm&+O4Jl8%_DKG1GP}5NSFG=5>XYsmq$@a&Za>tII;J1}PpCcu9lj>&
z9=;X+>>uA!n9g3abC<`YPQ2il3UB{^NZ*t3JH8t_izhhayOCsgd|SpTeM-KOSf_YY
zaq-=Vx~3n`DBpr?mZ&%9&mhbg2?yrqcV_(jPHgzs(Kq2g;a7AjdOWW1_*QyTd&kjh
ztLm+8Sr_#O>;FaV-iYHpwIzB#hI&$+qUDp8#%2D#nE!0XgglAfH-90<pAq5>&#G>C
zDm*3pMZLbNMn2&x>V|}0?{5+B^p4Y!@N7D62V4j*C2~C4p0cH9^e?dNyF7L&Z*wJi
zRX(?i1RFGJ`itQzeT1^a^&QuQ!&7N5>z{qr8kZAVLB{`CHokurWPEK18W26m?rSn{
zm418a`4#W@9L$$*MP831!{Dn=hBX80_`2E)y4-v~+ZBBopOH=pr+GoLLCOOi^i+Fl
z!#O>=Pw=C^ESF`A$rm6T4uco9$2YVFe=%=Hm&vbVovu6@zbqX&I907}Qm5qsuy|g#
zzq2^+J*(Kk;Lr5`4;g;`A?maL4W3kI@;B)__RT&~;BDx9fa7@UyF@O0dN|1Zs6&&F
z&HbUiRX4#ak*;S>reDCbIfEy)VLs3C7w1CnL+ANS3u&4QReKou)*Q(5Na|d8Anbeh
z9FKOD&oHPQIQ1QU#IMo5%PQ_x`}dj;Ck_~;19b+;I2z=e%gR=`lFu%d_t<55G>0hn
zcCgb!8`gjKjdbBrcCO%U{_720uo-^(HlO1Qy!Yb`om)2Cw`XH}dmP(O_KdB+(La%{
zsxbvWwtav<r(?li`P@h|U8#?ZhtfpD;CE_6!flN2Dx<NIEkl30#!B@`K4KrGxtnbf
z$rSMjV|Oz)gU^PlO^+r2-qan+;z|DFskxH-{^_jmpWZXMxyD^S_)F_=90~GTe3R9Y
z?mkQQUYTqt^U$_w$@+?pe=W+E9^T386E4<V80QO-e-gYEttftfJQJ<;-q^=C(=Xo-
z3w%jFr+E}UpNhvmfUkaG_G9oku<70yo^#sZW2l&vPb}f2zUPuqhQ2hfSWa)v%b>LZ
zv}9cN*wY$2$M=&H4_0o)G3iTZqW`$J)w~Vv%tPlb;cheZw;tKvJgb=M`rqPNH~D{y
zcdQ#3yPM}*@mYVy$e12|>n++_I0^j#eP|uT{d{>wOD|{4WWS#n@>uo_M>+B5S-w9f
zU!=*}X_59G3GKzW`O{<EM&c3;V5ik`JB=}^ogMRi4cV&xqH}G(o*Uz*RcGLh#e#m1
z7E`<Qe$LR;9ipRWbKdbBcujd^1Bj+p1lwiJAlqdu(sxh4=N}&1To?{``Ong=rgO<X
z=7GRj>6V_k`WpBy=dtEBaokt8f*;^1k>CC?8;5_?IM8S8_h{pG`95aSJQ=xDm!DpF
zky(|kiL457?a3Q-zbiiU>R(4%3sU~$u<^gnTjAAl?uFj~U&r)@A@Ap(x_(!jPgV1;
zxDTnbvbE#;$TA+EXNQ*N;cLaIKF!y*e;=89@wO@JE#kZ{UvKP3<!Ll|dt3vo$;JzF
zy@*r$F~Zy|!CZb_vK(6pTh(!VtL)}0<2c_G^m#+L`E1y?UH?qLk>c_;<#R~(uzBX6
zvN8B4>}nP)y7Fg!C+9y}p9uXuT3<_7d%$PkbHp3ExX>NjNA!)TJ)P_L+R}JT#If-i
z4B|H&+nO3@jK+!AIF(<EzG}vHJ-$EhM`u5>$|+w-8OiMHio4@p^*4imaDNi?glzF%
z3(e#32d#>C!<DNU+n5&YM0|(pON_5QWGP*CqU=EVi`-Avb$tFsa!dZ3+@GZWsSeue
zt+%mf);__b@(tzm7v~x!v}C$E!dygpeUbTd^Tc9mOtM?P0_piWba!D<Oe^j*;v~-=
zM%=@pLHaavR?%fE=nlN#yMoRy#;(69&QYc7>F4I*VE5OxA4BD3gAzX<<0YHtp348D
zPx9TT!FDFy_78Ie)#-nysO)hn8*Glv&yM`^G5i{R%GUX3t^B*1FZi9-3Zp!qxjev8
zRyK8%&#RZmH!q4ZN8@dr$GqZ4U@f!wrsf%n)A-^y-LRf-$|O6)XQ_J2$TrQ(utsVA
zyes49yP{0R_iFkR91+L8vb!O8TwjZKXR$n;`H$`hPi^pSoQ}+i{AeAgaeONM5v<5!
z(dEpO`BoWd;6~BG&*kaSe~7FMe06g*Pq01NV`tW%$oMCivo<Q*uZ*&cHTJ{h)11dV
zsX4A-E2HdR<MPvj#X1eXv!6r!D>(#RtDJ1y>dqm)eNIYq(T700)HkxOJz0zPe)8*#
z5*P47TY??l06){Rxi4fdf#JbM@SSFpw8K2MydV2s^<IW=mbrmpjlPpI^>qb(RUcx!
z=X1UE>h{8T$Oh3^**<?7;e2f3*d>~f?b<v)j(O2C9Wd<<G{9I+iPz5#b@ZFhRB&bO
zr?K+-Ht}g)Pw-T8+n<uJ);LUfMFz+}V0#oC^o3vJKHd&EO7n``H~Ur6g}>88zsP;Q
zSB--o-j&WjtsUk}$(Jo#IG+oqvAC>fEGGEY*z4Y+LGY<<#;CG+5^XRxl|6lCk3D^8
zyY1<zjU!`vZsb`X-wI#M^E@84xjFh<{BJ707t;6YK#M<-{9Qqrelj-6RGr@+U7{t)
z4%6tf6&LKE`mgtq!_c67&b7aYvi$M1lW;u{Z?V3o#Cbx`n!Ej~;uH3vg+2DOi<WPx
zt@p&Xbbk>vT*9|qe(d+g^oNn2bj3>QQ(oD|%(WUrt-EVO*fR0|B|al8ewS|gzy)FN
z3uRvmUsU#QJ&rZ?q`AF$HPts-)rY=f?LDhcYoRj@U=U4lf4c8*lmB>lsh<_zlvnV^
zyw-ipsr+Uf{T_|)9$C|OPsq{k0TVr=qpN)$3Pa1@k9;|}WG_(K_mSq2Gqb=6o~{8;
zl5N&U_$qB5lArI%stoZZ&#DVr9v83q$`47L?#!BL5{3?wOfv3IB93~rH)MxoKabX{
z#qSQsHGQRN?2<oHY4)dho)Y4<_NDl8Z-+a3*atZPhvmVJ;k569F%o=b2b*910$>q+
zuK9b;dGz4EWKWRjRpZll9D4V@0&jzTK&;2}-wpZ}b@l?h=e>820Ox|2F;M#()<r!v
z(l$;Ek6_cdfj_T#M|ejH@({jKdXM+Wx@=vHZ|g(KZq~j@w-M`PUZeJ*U!L*llJynu
z9f@#MdU+VR%DHyIm0&c!gdgRFSG>=Fu;hcraMhhld-lD5=j~ztPG4O0?s3(gRN&Se
zM*G9G=aFf6m`}euv$5WdjTP_HS6;z1zjAI!@}b4N!ut<Y&ouP58MwfKeMT|vX6Vdv
zFn+tggxOPNJeF(mr76$llvN(St2}GLiSBEmPT^2~6z8F>ecYc=;m37TA2_i-&g&=d
zni2SeIP^;4c7?l$L+bEe_SClSWss~+ez>v&ozmw-rzJ3TwWDvf58P{x&)N~}+UE-F
zYld4z;$wa9i~TSxd_#BUKh@KS^?5F>?-da*^y4GD(8;ka(Q1G-yQfI`$09t~bT<mG
zwNQRueJ9OwM0JpUHFes4;@kfRCA}~0<Y%6tU-iNKft{Q7uX#_2Xq9@yo|5>#ynJtN
z@0kSnRlGK%K1QDN8eif+>bH%m@6ouY1zOcVy6R_uTguP9ki8^om*?u|zrwWae|RY_
z)>G|~K^~+%u(FRd&MUcJ%x!{$v?g8GT|3#g_p?;r*!a}FD*j(6l}Rx4#oyQ2Ls+th
za1DD1c^a&hYF)S5D~yb8?4R|Tu-6}zrnzc?uLVDk_WLyU#dOVOQ@ZF<{#JdjCZEPd
zVf+NP-}q)-a4L_hC0i}#y#XBOz9jdRv@YFK10U4e5H0Dg@d9S=!8oM-G{LvzHi4(&
z7r`>z<}BhXk>A^<Mvi^I+e%|#eWdv!He~I_@Sl%T|JUPet=E{qQ~UQWsP@IKB5$KJ
zyD0iIT?iKOvD(pGU*8cwmCs3I6>*S{mHAO}Rb^F%e3l)q3mG2!2i*3#d;RiYX6r%^
z&I28}-^vdz)pzd|(YI{vEI#cONiy@Q0+}hhIJV{UU$kG*CU)4&vq?`d8aCp7EsSZ(
zr+S*tBp)!n7QNN{l~_h=+p&z{`sJ2w4*wTh?P%=bfwI$CoWW-)o653UX^B6m&+A9z
zDK)l?BV(lb{nV<T4fXfZQ1i;z{^_mB>vzR{gBpj&M0nyDX%1?*9!-AH>dC+-cu$D=
z!u&PtFC<-SH{O#Oaq2a=tRKJ@#)7?^tInbh-u{P-$3o+@<m<d2IW==S?MB?s97|Yj
zkAOeXx5D7x@{_P>9(pWp(B202w|{FGn#PyHIUm2%oixYAZ)CsYndkb=zJI@uU~l>i
zC3yD!Y{AAlxYv8Y-^?!-;VzXu9q-$g9b;aTUCCp*+e=usg5Es($625|d_wwWO~(J2
zQ98V-avD>&r#Q-b9n0y$89GN}Cm!md|B8p8JJa&m5<W#!_OJAm5e$Yq)f;7p<tMNh
z_sTN@Y<g=h0#Ds3UXi`;@)2(0EBNwyO3plfKi)wj*g5ZE-_d;^3OZ3TBj!nRd*+eE
zsr~a~8_>P%KilCOVq71X<Oh_ksefWXU&Vadmn_}GBRQ&bw7#GJSMfay{-L(@o%iZQ
z9VPvVeKOVH9r_*f)Z+JO{MMU3S;q>8l=mJ2;|$%ay|ju0*1G0v*MbYlC1`))aIjq*
zeC)Mju@giWf(u?KuU*`=>Bdi0b*k-|<BPyI&?euz%lMCq>JE3cUypS_PhlR6Eax8y
z6)sL5E);fs=TaX$)+<NS`DKqmJ+5tiII~SZj6eU1pqnhi#j{bStXdiKe=y7c!MOJP
zA#7UuA$c#lXz(pxu4&{0S^f{i{Qs*bKi{@LXfMf0(|>~T@3K1nj=U!VBRp~^G$mQ;
zcK$xg^Y`SD?JxLyWVZJ8IR8ho{2w7db1lbzG>iWzaK>@-URZ@`(~tJOrhWc@8u$5Y
zoV13Zc2_b^(5mMVe;LzbJoJOT&z_GT#JNl2_v6C2B^+o?u#%&hjQ4tn>SBG$wmspb
zrxoXY?=ih=uX>7OPWmnEAm3-4;?iDq_WPRF6fb?DJ@hHeymlq)&{a95_tvGjye|1O
z=-+E4Z%(IwlEL86XDAd-cIb(ukxzYYYEG@a$AoL&>_AuXe&mZTX*J{{;V~^MEdJKJ
zvXfaq`CjNlU1!4x*Io|~!avp**j}ES_0ElvIWzbwYjbl$mCWJ1gw9ihy|sbgEO+$J
z35_##D&6?f_jfxEhdmIUAK|l<Ehe77eG(G0Y?JKuzmrtIWWxSich_#*a+l|T&mC*2
z&XRJL8^ERW6d#e^e|^;b;AV7;w!xR>HQ!h2TlgH0c_qta0|-XOud+=Jb=c3{nra-H
z4RkudHb~`qZ3o#}<`ZPU=DDgz_I--eys|uj{$7lXQ~Q~&2=jK}Isx01^)%aU<dMyk
zd?qU6@8~y4{j(2UbeQ;AbdJ8NY@A8H)o102X<hZYtn#oAc`46y-?l_k;8cE|)jSCX
z;n;hTR6g0qf=4nO`B?s_<9SnV(=~<vRF~`v!I;L2dX~v(WQO6ZK_gFyVfxe1Ii18u
zqf7Dj?NX2VpLEO3@d4@NlWbW{-3eFPe;n|^JIZi<FUgabp7g*&T0yQxdF1sE^4ssB
zcIDepdG4umz2AY3Pi+So{g;_+{Yzx4%0d7B*OkIa#xYl$(VD5^MAxcsB-RJ)x`)(p
zwfJ6v9fzIh{Hi1CN2R~m`_M04@F#n&@$K0##|0*zn}GL>C)c-as<IJSQ}sSz@!P4w
zC9<5kbL&~0In+56on_G8Cf?V8w`x5OTC#sYdIUWl&VK~CV%R2B7yF%0VXcy~wm0-<
zZf^c+W%z4FUHZ3K+~0yz@!YD|SNZ$-uI6E3Z6fS#6>fXdz2BDjacH8J|3`&5(+Tst
z8SLHq#!Cy??0x6vz2}9Ke`7lOTYyKt9r1|#Ew&dG2hQb(v%Y*!)R)FP{Hk>H$P41U
z_qLT`-ir)@e=~m#`Ftiv`Jof9CyGY+o*zaBVEfr$6VtDjuTK2NcdZ%HLtCv$-zhFW
zQ{ENPuTEI^+DMP|?R&5Pw9nlEm2O8C$hYpf&#BNZv}PSCJt)6A`&M_TZD>WlrqQBp
zTZB2nr1rV$dpqfs+;qMcIws^>Am4Umy}rGU04`M*Vbh&x-gAHBxX*u@JNQ`eHEp`_
zQFqg3(P00#Xt4H{zk`=QQ8eEAcVQ0j)<B1ix9nNMOYWl@<R^vJ)4W}_QkpktzEV3j
z{-aqi^Hk?;&je3=H=sei%OU!zZ}pjXt+>4iXN5_l?_~}9Uvfiv^*zEjG@vov&NwQ5
zVl;e@$L}5bR-N@Cyn)AcuLkFmMWkJ+c^Pm2_gQru6TjoTFKry<Kg;}|8_5;$Bb!G0
z+%hPSJC-<f-x|%a^LWYf{5$3g@{RLc=m+MCi~2uoZE|jCp=bUw^G|Vogg&{?Dxc4Z
zpdayRS`)2oVQiJk7Jh%=UD>$hkGJ}N-S*Ez-}1ZF*e}xnhAucq11<Re@R1hhfN4h$
zv^owBq@#WA5ni1aEi!)f;i7=X9d=&isbpume@WwK`lg<04o3Sr@94D{!amc%+heY@
zeXP4^{QI>nT$4v~#l8TAMO(a0Q~KW933`hDdH>>QoSV#NGI|~vjUUB!wcfc+t?%5P
z)_1a{)lQxE<TH{@u6JHm-+5Vm=Ve9T)KN=x42&LI;%qxY8(sEN`lin6Oe%S8hv_X^
zXB@mnb}3=v?DK$jDm}^k-+D6Q)AZu`@9p>oxL+gf7a{EV^+VwADlhOd*S5VD<AC=B
z^Rw_yoWn|kCQWa9;{L3cVMD_QLDvTTT1S{AnzOBz@rlpoWZ%6yUG_XW9@v787wu^d
z5%d5)tGGtpm+$+?zuFlC<eS#h%zNM?%C==P?)e`te2zhKNA{NTA0+<-I3e7a4so@5
zyU^N4jkOx-k^gz9W1jYUhRVQK)p`csUF#V!y;{%UyEaXIW1)@O=aK&>h45!Pog&>Q
zTy}s%wln#U3K!T04c%!0d`aF__P}s!(swe6??`W;E49|AbBMNudiLa2^Y?dUy!I}5
zO?^2CT;d(dYcF|U*m~~`<W2<XWWkl@DZ-g$sN&JDg4JsqY9oHTJ>-^U(P`L&qEDsA
zIN!|x9aVQwP*;<?SKJnQ&}%2EpRjE~{hJ+F{Ev3wL41c@;eBwz$J6HmKK>%>_g_dC
z53tYrtvwwR`XV@IkXd@?{(g;hW%J~^z0Z9#8Y|?oaVGieJvEBMPHTt;4+fjWb64b-
z@kx7|GyF}0E8S10x;7hc*e8S9m5s$5)NL^jRT;^_WLs!{)S%6@#$N)1{j=m#KbN(u
zdks~`jXiBXfIT$En$rr_oOsGpckbG!I~;Bbc2V_T``-yLm>#5WsjK&27WThgE_x=N
z{v~}k^K9ZoFT#arAf|iW9NSy#)-%6aSg+O3q8;>=`XGGg_bAOs1`J5EzX<!Xr`)t{
zr~zftJw^*PWI(i&;`%%Ih6ewH`HJABFXe&GV)J6=ZvAlk|A1TdgFDkbZzY`WE|<<o
zKK681Xy3cA@yp6qTgdOiCT>D-fiLZY{ZFX}o-qG$hqh#keMh}MBgQw$hUP2jTkm;E
zZ073R#%rc`RXo&tCvFc<nwI6e62J6}FKW#Exr}aEm#FH`d1b(yM0Do61l~)1gsls(
zuN2nZ*8blSVV~{&Um^Z(=&ZSqu;?23?0vh^LHcG)wJ&!K{vPp0*St)4LjKmjNuS_X
zpXVX2{<S!-eMKg_UV+S3eJdi3sI0~|#$AoB_dN`J*G2+8S|7Y8tK&U;CTpi~{*tzQ
zE|$Fd-;wkEb(Zh1V_Va4ZmKrcYTV=8RQ%_5m(M*lHr+m~Y#vG(>q?c)^(^0AdN!t4
zdY11>&pIvi+jfq=!HH$#aRKMmTyhSaNKYycI^S>ii9H?o<n>+cgOF@czEvS#@*Ac7
z5lIir&Rwbh<gJVOb^bx+tP7UTKcsn^&q0u${EYI6z&}&o(*g~Pj^9-PCwhEdcDv%L
z{2jxTYzps<tkUoe;w!YRN?fotkU6@K;Fsc<zBe1w_i9YTx}xew&J^2@RbN9H#ccyu
z^~c4s@5{=*FVX|FJ%%isc|`1cnu`f1q|KZW;|bqLKL2l#di{Te=JZ`9IsqD*Ud4VW
z)7;-=ZTwAaW2IoC4F2+k&TPQ#DuvlwHB@j9OK~^%uz<sfY5Bj+H|+cC%UjG@>e_SJ
z?8A3TOKYdmPBl#L&tQ80a(<C45qy1ZrQW+l(I<_)>=WB_t97wuJhW=vE_n}*l8#IJ
zXXN|PKkMpmq#ene8aU-`T?cK{S4dWbxxeKhvR5{@%S71LkAnN(;-Amt>pBzm-Zyy<
z>&mCISC!`tJa_Wco-s0Z)vt_<&GGz@XZo2VW9RVP$g^e3$k>~Czk}x)ze+scm-1Xd
zKBZm7V>m~O$p!9_^&IqBz%F0S$_rbS9(WS)sL!GmcyQ*4;XBP^(>|!?&xCmSohGoW
z>sL^hcmkU8{w>-mxvy%jd10&m1f>PJS$|x>mwf~D-}A3g@-p|){G`2Q&al)k8>;YS
zST}`o+Zh+l^E3`=PLs+=e>P7CF5nQ~X#JsnYEQZPfN~|}5)9mTP~qdDst<llcNkE&
z?=Vnbv2m-l%s-y<nyz6zjyAz-t2{5*w(rPj^&RjJWi3a6&*3wGb(FB~E>Qgs4dJf4
z3)G(Cl^%WeUQ5t7K48UruaLfvi{J6>Gx!<{WKPwuFUGn3^%-o}vyONVeu*;D$9>Rn
z8pF>MW<Ff`PedbW{8km<4%sjJN`1nXQvZAx1w0{pM{%A@%g(~aD&@=495L2oJuO`v
zzZVN|yJG2E^4PxBkK&)<4t(*F<-p4__+JM6?*mS7Kev^A<r=rMp>5%YXXYK$m*Jtl
zGxkri_)k@ie3FOIZVi9C$MS6<-sh8$5uO+6PPwd}61uaW{B;4|Ja21eW2=56|6V&8
zeNGwa^ZKjP{F{9v+hV)&vx^UaLFX?-<11Mc@;ag55<kwxJoIH`9eG#-wa*oJC07jZ
zb?Vbny4F+FpM~L={v6V=Hxqv-tT8P+oy9BGwWs87)mW<D<}-jN)^#u6)?s{WZ)^P*
zBiz0Cx;n<|9t!#11UojZ{e7{2rsEjzwP5aY)_hWHlkUT8s3XT?+c>8#>HSovYy;p)
z{GdKrSN0p5*mhp0#zy6>Pfw%G$p5W(&V{>ulRS72-&(T=FQP-!)iW4Jl$>euw%{|=
zn!WAp2f61*^wd{x4VvSFYwrOTZ{ctC9mmr<ca{9FOZ(&vGjs6P+qp}O{;JQ?UwYTi
zmK||9cci`K%#u9qCnNiM^9VPpo3Re^1HSqp`|!|P)^R!`PI{tS(VX?A<J#T-^d`<e
zxH$Ju<w|72ruQubnu&S5R*l|N8}gqF^a%`Fvx#<(`vXp;n`9SRheuzE=}qVE)aRu0
zqF-v6&Vz=mb0}-OoI1UySA4xeG65OLJkT;i|LY;2<&WCtG0xR*<jue__FRg2`VjMU
z9&88Cbp`vokeAI9dd|Ci<juAfieDcYOV1QxJ?nV{lYLLr<9Q3;IzO)X`Jr~uk+tw$
z8xG&Lok&mnZPfPFJeE(yCmUP+v>%7KzVzDDm*NuqNh+_p6aCqyJ4#>AAMM<w^4=Gr
zdg?9a%*@xhn^bjr--6;re|q!ie;XCu<nzkjGaH;OXgq)of*)07>6`D<R~@D7Z|Oeh
z!}Afv!DsUSD&Jfu?&sqCp6Fw9T9=699&D8?-xc6nX?r@sPpY~{XoEP<mE2bR9*%8G
zS1P?0zZI`<*$v9Sf<8+wx-R_5hp@vVe~yEXUf*~X7yaWq&;#?#YbK-*=%47gwzsoL
z8`^uTeooGPivN3$6`|cBy`d?e$H@A&GSX7ygYd8U#1}z!hJRRwGS%4h`V<Dt`|&GP
zch<Yl!XwXf7#sh0nQ)ga{mQqPKdyTA$k;BPmA}C~3q0w4XZ+Utsu)&!{=AlNJ#+Uw
zx>e2NWQz&E@$G*i>O0v)%yAQKv_A3ZR+<wwI1ly1;uAx)`aO?|vKg8I7iR>yt8nWF
zVIQ35nwn!=DZ0W|5Z%ZpaLJNQQ{~}YL~2j^Y3|B7U=4M->;;rXu2%Uss;&%PWShpi
z<h+d9D7Ip^KP;QGtRp|RTvdL$PkF|sJP^zO73IsUyyka#`;&djXYJ2@iSo>$syS0F
zvzd??vQhiWoFCxlT#5V~M}G2f7w_%{>v-&o-|h7;Y#s9nyi)b$Pk@E>AIZ6C(GjxA
z^Rz!CUUygv-{K3ND(wxVu}0<j%ag$!_2~?i=O)r0<lT<0(YNP@@mp&d^0|v99M-wl
ztZcO&p2sB~6|EC*8x<HE2WA)RYeISJX2!=h@t=Lr{#VaI!MXOKmj^ohrvy2vZ{UQF
z7CjyhWcz{R_-tl=Sbv84P9Et*`q6v{eM<6I=U9*t>Yvu=-Dlky-RT%dGsxo_d$;RP
z2>H6?@%QjE3Kx{yA(=*4uu1OKFAIH1cswjFB<FHm90V7#6=GbFeaNR__S}J&igpFp
z8RW~xL;Daku4znin3lnM5LhLHRelfat&+pwY5Q1vav}deEpfJUoR-~-n8oL|!azBg
z(R1V2;@)L6o#-=-XN__CagfUk`rq>>=__>VJv<Q>jhE*QE67W^ap>NAHB<-VE!@@D
z7lnD?gQ0xI8_Xpto_udi%XrFkD7nHoq;U*qEtkFzJFbj{^?QWNw3Ybr_h~PO*F0OS
zmR#O2!dw28CVjq%e374}kCB6ut$%#<5)WrMvW@w2@{10k!5|~>6;|cLIX&u_@;(5^
zlaKtSgNSRF7j0;+OaJedkK$(nel@?+y$ls^LXWn=M3=HHgm>lP-w~oy^Gl-HAH$#g
zXQr#H_KGR}tZ;9-*MIf>FzOhk%@~$_q_vtVop8kqtP_b}JYTU57W^blZ27LXB%cmf
zcRjY3*ZqS`rchSAWtnn%#IyLlPQRf?_gmxPFmb|b+6ThkG|Nt<u?Np-_#Km;lME5=
zlAI-7wu;iHiq|mS$Oz@NJ|(;gIAkBC{Uo(c=d0y#`->%ZHmd4g{PADdw7%Gb-SY+D
z`(lIt=+^WvUG!lCy(ZhkxDdS~|7>3-+PsLqCEW}S%O<IGg>)@=$o(UCQ%AD_Jk(S9
zN+^^1Qt?P07xh4zhufc`wnVqoBY%qhs6BOxzr{y+omJeRI%`XH4wOxO&hIT?LxwqG
zXYq$4+%<Xg&C&loKKa92ilN%{rEBF=*En5JOb_8ZuD(m{PtX}s$qydgqr&`WQFg=y
z#m+*$Wj)P9=n%&KC#xS{1Y_VcL%fBr&7xV})?2i<=BxS_z>(^W_2AP_u!M7+KUujo
zhx9*@0rMXJ4;cDmzM}nW<->OF^8B8+{-GoKtz9l3eV=`AefDbzmp%)`dmXg$0_}r4
z@%`}0w)ig*_Es4W;QWL@lafKw1vBDrrN!?O+cLo*_&wIL7r%5-OEkY~1^Qw9BE}ay
z@r~a{cK`@ih3pZP(RyUcvw1c264M9w2R^JV@nLzeV|`w&gVQg;uX+XRNkxDeAKudV
z0?UPa7+><<$y_PTKb2Q9&~4}Q!+dW5eQq3r|2c=K^2_o*nDOf6p(tzAj>nw0bg#}g
z&dmh8+Sdop=J$b9&YLN(ZKw`%Rq{ZO!pMU#cD#x68hIK^=)6i-xR6{OK#x81_zOfo
zzxh_<HlK5c|2rY);L*fa&imiqI=SJ;NB_U4|MdC?;aGAY$pFdj&kwgO6TnsQ>yQra
zB@;APD-Q<$Z|l>Sw<OzzTie(Xr>W19GtK+6{}J`hZF}`gMqiBso!zv_c(m?jOnvsX
zg!aUDbJuG8`|!N$gGcJ{2tK^VKJsIK37$<GBahOD`E+N`b*yQK9-tffOx2G~Z;tn6
zzZSWo{}J#mdG;wU`I6nRiSIxseR$?S3yzKR@FVg=uw3^ageB)+{1gqwZl7>LU)^W=
zRP|Z?r=3mh@Nbi4{N3v-+DCn?1$e!X^U2~v)oc4iyvH+!?9tk@@h>_%(1U;CtmnwP
z@8&V=l8)zYT6b;S%NkLNe;|v$k9h1C+jyi)hnB!H_j4Du>dcQ-CdIX%dQr<TY3yWQ
z@@VWl)&pq>os(>yh%?3=y9YYle`__jZ@nSbO`rWgNZv`WNG6vje!olJbfujX)1qwZ
zN;^5G4NGnXol?o>ULNYzbL3AldSPpO2tH=LW$SMH=TCXW+SYGh)KWZr44z{AiA(X$
z4~;ngbci3=_Jfi4J$q#|W|A=%@PBxP8}!{akJcLo;8ilKd0g;$cH{5;lR6WhmrHtH
zGEDPw%~6y8*RoD@J0n{Hej~i$-!i$C>%+sWnM=1z?`+=B+p=PIv9@l@U8c>sC0YsV
zTiAH7xZJc!`-SBS?arJjxEb@`BTYEr@tqvP33b*rcOabloBCzi-rHHcpt#xg;il{O
z-vhKRJX#KGK7>pxZUPSKkt|y?8F1vehy0ns!AMIyxLb3GQu32BU3QLO7-k(W_EGg1
z*YJsKpSf+(<{`ez=D}7I+<oP?_S7E>&mDv8=CQA8cy4!Nq_vy5<?fpF0Q_Du{}C_O
zf2$}yMO|Ci+a;f}!pv_bTX(|$TGt~FvJLtP`vq?&U3q4HGvvLdU%97+I`5vMPT_*~
zIG@4)z&e?qh%r+ePYQXbbnfJWK6%kO(mP&1U0Dpd%;ngsD;Q_tkNKwXX8VBm!bscS
zl^mw5<nT<K^Y%|?d?~x>ZuElY>^$#+f4rtcxVEx2seZdHz8AP#IN>4TDu==2_!Z`>
zQxOj*Q<vsty?8)g+b_Y}I6knnCo|o<TGdaUv|lr&HRbmjFh0%KEX|jf$(+$RC+)Gp
zkP)^CTAv<n^`)%`Bcpol6Ktbu{tNDpdM<Gqcoc6jK6fIswn%R2Kdp)*EMK|L!e!s(
z{th&at#tq%q>tjkN*=7hNB7SI<`!Ca(6}FqZ#CxG%=}Yx3+cux?nv_u;|+ey*50ap
z+`yUSkLMmIKf-<KiaYTU{pS<8+^1jCRb@wVE6i(cfAsFzwcQFV@<B)*$$o*hN@%ak
zmLtx(UUHA|5ltJv2RrzR<30<;4S{pT>0SZkg!A$3d4S6iRy_SoI1lz-A6u_S|CVQl
zwYl<jJ9k;H@UCwNGRZbJW21UUm{V%sg8e$=Np|!o^2~Grt(31@+;!n8LBFN^tb2xZ
z$>|P#80G&y_<2kphCRp~(M<cB$g1e0E{EIhXIi(jUH}fq)4tCAs9o8Fqw;wGr*TOe
zHTu;2=Ub;*@0o<h2ArAe%a^_5ij4l>mk+L^cYbmJ-eyb}n5SOP|Mmhrw=Q1K`ROn&
zTX)yS_}|@o(Uqz1%tzAPTJ}u|&lV>$Cnp^mBdyQ8A#0a=bMCEaj!oNFJR#gCU7bJq
z5o<B$GnP9TW3>ltKOC7Gs@;6`nU;C>=U_jOw&~(Ou@5s(Z;wvU_msYEDo+c(pl#Oq
znoE7QGdtAgpXTKu{3+NKqNQq{&)Dd^#)Zr!HBR<vq5qu!;MUzg9KpYI^JMfV(H?MO
z4}0x0z(8L5B0LTB{r&$zZmx~A9_8jtE;H*rGL!Ek$;{&Piv#|_S(j~+$;^}|mzh=E
zkz{6e){^;RQSnM{KQf0ZhuGhC&GcQ!81HX@7w^N?xvx>1yN`LtefV7OZLDbB+Zda>
z7n|r_Y$NuOwrASUytq~V!t`A$p19?%2Ia5hjSQQ?cYZhT;J>9VY`FVM>ME(Lq%PKn
z?=7jTR9&=P8xOj4)5bH3`Oenbrt7YK1M=-=)eoK3u6)AI&(^;(ThxknU9$EmqCL%-
zxXTh3<UO@v%A=3ezgo|E3h_;YwNus>@j;JX>~-{g$dEYau03#z`M7q>E0}|D77IBw
z_d3pbA$w{cMeguU{+Qao#Ba$irGGbm<GV|;s&OVZ8vapz&);@uF>!WG`@uJg9Wh+n
zu~1B$6XXAIZ?PkWYae}}m^e4a54DROF}yI$p1lnrKFR;u50>^3$hMO1VNA^HHTFP=
z_Ns5KGj_taeK-?;qO-ovoAUIPLp?gTFZ~=%o{SFr)^Vit9^P+#DV>q)BRh{&*Mm(z
zn*L@wxG}8t3*`5q*~Ri~&F7GH_YAi@pZ)AvYZY$)@|l&su>TVs(PGi4*t2da9viDf
zmb%<m&+=YNhrdObysclJZMD98S*!8vX`iPqS!>2tTKxfhf(rZ2Gqt^c2ASivvjD@l
zLtU+B_J_edHE2Die?P<7J9JL3t*!kZF906<A|C&U)zTH(D`K4V!gVmfRh|=YroE+y
zg(b6%8#Qn)+f2L<-V+X_BfZAVTey*4%<+OvdN+IH(Q&teXZGIJpL=FW9mS&_W__K`
z&Ltc=&qPn2iSGV5&ty*?<d^j|{g)m!PXkNy9_Au1SAQqK6YW1VD|aq3`rMtn-hu9k
z`}g@5FnLbM^8C+8UlEs1KO;-ukkx%o7Ed4BUy&~Q3G^>;)=pTuUv%9Gf~yZd_V8|b
zGq#)Nv%KAR-g9qT*U~rsipd7=!=8Ix#(&W_p6j&bw%_91ZwB9n<g(UI%sUsHZT@q3
z)7j=D;oxZcQH-A5YP}!*_um*7aG|>u+dp?kt9*U<_8Da1XdiO+^`z_kl5xg(^IiTP
zYe(3IdMDl0x83D?C>P7$-??kmW0^yBW*6()lS`l0jkdi$Y~DKg!;>=?Qg?6sse4Ud
z8_tYAs=UnfhbNn-_bJm1Ws;q~ZnQXF{6ss`4b|s1isNOcSMk#+K8GpAEtM}%`LKDP
z{@d2i`_Pzvlx_ZsKj^b;Pu=^YHXYAf;j5WHHE%i0TwV5o){is0x+a?%A5jCDYG0~w
z`KbQ5Y;H_=VgCUzRQ)`8sZY|sRs1Q$!_V`>fj^4-wXVv2BgWMdP8!We9p4*Q9u>Z`
zI)o>1V|)llSsOLzK=hE-LYCodA=`u5>&IPAci!LU^X`4xNb8DC?VHHb)qdmT0HgUE
z7{z1De4Ui>IDUOL>|@b6%z^Tx@&kDMo$v7cALRLE$UN*j%k$@FvheaO{{PP6AG;K9
zS^D^;@5+wp#hdm=j$%hcU#79-qZ!6`IMVhy<rs5qoqeszk0>3;W8WUM<vBUH0Ed-d
zf9|&~Z`GL-95z35DwXj%18ufj(({=-u0<aBF7QnP-*M3YD(v|Qbfv=F8F%}^s4E}&
zVV|QFJvSZ+EpxAw{IK?MC|qNVX)oz_oe^Gn9P<AT#u{IT^P|_Xxfjc4@7(3Pd*!=R
zxWzn4d)7$1a~6K$t^E&o&d!DKXTw@giH**E6grEN{vFPL!zZRoY<bJ;Cm^q}3Hrey
zUNqg|XDoTN-)RSaLxp!}4H_7)BF_7$_jbY>40Njg+%B6Si(~29`Nccoj#Som_JZGk
z1;4C^O{m^f-za&rvbP-!XVS;_bl8)I-Z>4~C3yJu9+89__8?Wbfi9F+W#n(uc)Gv8
z5c^A+*9vy&4#up#@{*Rusk|^7vkUif77{<N_N(eHz!$Lpif`?QuI*u+VMDmzvVsGc
z(pV<HsQ*KB?6Cidc0sb)e(N3Hv-^}cuxIxz;due!=e%)b>;O-SJMj9Y@cKVszx$g<
z#^!mH{x%-NduaymrO;Tyh3?==bfWt!p%4F`op+#<NHeCBNHd?q{}OCB(};Wv#@RC?
z&gh@V@ux8UmV2(Zy+l_7=s>ipy&H?#D|0G+i{HL?C57RI>Mq0-$6lc7Ud0sWJ6PtY
z&M6MCM)h~ajQ;=OG~f`A%KvaIxJqH>h@w~4kf)p4Z<^vIuPKLY3U|<@I%1sb+{fGz
zp7*#tJ{z~k?+tO6XK|NDd7&~ZA}rLcdJ>IQ@<Qi?fJ1E?p8cVn@&{XYZx;Rj(WaLE
zxmEJ4!e*;zWF*>ezY**=>ywub+5RXWox$>G!GgSh`K7J;e~;-GW$71@&e-YxpsMck
zV%^V+v_skz@S9}S$<xK!+T!e5??D8=mRTxGIM8M*>`&Bpl4C#akd9BZTb6Bvx1rVX
zY18QoV_Oe~)~`?S;$xIt7}|tyF!p&<*5^$budM;652nqnvCTd*X^{M>uZl2TlEHLI
z90&HpR^uQaioT8Kb``E<KuimGMh>L!L9*bc2&?i9Y3yR1guCk0cakkJ@1{X@{(e?x
zo%y8m&#g|p<$3LSXP}2yguBv$j6$YQ+_=!$iofZYR{K+zS~mBS)%Dxr{?dyxTwR=v
z-^0O?=$HGP+$K8L{St2zuKJa}Q@_&ppnm;9?3e0I_>bYL&h(w?Oy7g*-1#4%l^bIJ
zAC>k0QCa_!9C&At1EQT?-8hgApBL-CEUWvnK6Sq*)(xKLSr_#=Ov17w=CSW{TcAr9
z97&G$$V|)Dt1?)w0v3&vWaClD&e~|Z@V;l2sbud_%Fz#Ga`a)$fs!sx`2AQ&ABao#
zL04r~1)5B<KG_qM9dp}HP6zV^d&gO?*SmIzy}={+mWSCJJcJKf`-78h`$KHoactXT
zvAub;HrHU!0PE503F_=NjObtc?Xj`6-qq!ky802v%a*fT=N)JrnXYh>=likC4kyd+
z3;j#Ds%^vWx?+7xYekBa4W{{#?0>`40-l8DZv;G>7Ou!>;flSJ^_PaZsqOGMXYe?S
zKJ*P-9)Hapu+^c5Nws6$syO;x+usRswUEYITiEX%%h)FcUSxmBM^X|N4ouhB#iISR
zS71Twa(p{aTtm82-{jjdL|NY3qmOw)?}+ay<g3rDF!w2sAztq>WEFFVO`qYPE{uui
z%Kg%@gJi!XczjNUc9<7U)>g2uXzy0$Kdk9J7yrHB5Rca2QO$><y<U|Stn|BfOynEk
zKsc1m(#iNne9TkbQ{FQ!9>Z5LhU{IjF26sFq2_BI$9{aiIUC!}d+F~H?t1I9&kdVr
z{U~y%qG@~-E9k%UxyC=xE`3Sg;LhuE>>&il;onC`$QSE4y1a=$_H`t)7|S~C6eoyA
z{r!7<^UuLe@B8F*&OgT4-Y64*HOY-+Bi5kX+Zmh0Pq%5Du3g-vd#`JwfmY04@Ib|1
zgnwfG`W5&~d<0I+2f~~91UfPg8ISQ>@iDLYjIi^h@{wj1h9i$ielssLe-Ji*@HT(&
zHh=K04Ttesh6Csun}M-3eTVZdst5WOJ~S^4e8b#SzTBMFov%$k#zAn#KDlrD7QG+J
z=p9)nd3V(Ge#|-cp&pjrugvKE%A=t7Uf&Zw8}G|_13uGQF<J5!%q8*iou+VW*IC$F
z1NH;-_@QgV#Zc?ybuI1LGz}gf`mwn{*PMZ`Wp&Hzfgcze9;!X*QERm(I3InSjVJBp
zp3}DZyKyyodgIPr>*W8?`pPR=M|mUg@n~P2>u!d+YwS_;y?$?8+_hB3YcU07r_{#g
zybbPfkql`(T{s)ymmY8)m;4)%br+9HcilKTH6i+imaQA42NGQ?PP#$*LUD;c#0TOv
zp3TQcIwm|0KkpbKFLc#)b|rlW8I6q__AO2*Z)~G0e;(IU#=a5S8bKakDV|VX=C8?D
z=KoqiyJ232>;=!F?JJ^8AEk`-6m@8v^sRLN8;&^fVLFpgr8}N_c<&gFwjK1<#Y;|W
zGZq7A?0eWBtFS*Nus?VjoI&$kaRs#Txq3LmrtoL7IlktPiUSAVlJ0vS`{+{Ko2>7u
zIezm`nYSyA^<D4JiedQ-t*@(Z`b$`6x$0|?Yl^20*2bZQrGFlHj8Z-fDX%B!u2lLd
zyGXPrKU#U+hbGIjX+!Ha%hDcLYO5Z~!b5>}egi(}a3AY8*%u-h>eNxAju=**P0jOU
zZ_bmZJF1mdV?L)hFk4r}aL`9B@^nZ;$9z^grcK@8c}1~y)91#f8^gstna>a&m{_m-
zg3X8P&*{FS=4qK+dRpc))7inyXSVPFeET@g;Tev01;1=s^X=7_F0Ip^6#Jkt5?!hc
z;VXvRmr38>P8_n{_cICh_Ae}*h1EZOHp}-R-yM7HEPvj8;o9OY++~pL$CiB5ocq7K
z(Q^Ib)hM?|&=t}J{x?v>o4yxM1=sZmk7T~m7!R#~Hpe)#lG^O)yW~#&nACUL!58B-
zr&zboQ>HOxyqtc~(a~Ij;r|#K_*6KTX?kseW9^L=9%@BKuS>KW>9tC$<`9W~4>ymv
zIM8YdzCEYs9qOYkh10xS;X!lm$HY3Sv5w=;I5i&@Wl7+%Kp&^Y{)jF(!>T*!n#aU*
z#RKSLGwU?<SA_9SG!1QryEm#b{pncwOy?Oro8F!u=?B_eiEi3dj85K;{+ip$JPMol
zHo}4{(U0zSvn(Sm{o_u$Li<beJk}o`FZ!o3z%N&hX}==(Mjzs?asFlQv&t3R-EzQv
zeQZ&<{W)|*l}|LVyiW6|=6=k5l-F}V!dm}cD%;)0g3gYe3*6)@kr~}^e#-MG+nP!r
zX$KsPMEVo1;{Qu&d+A(sjeO*{ZZ|E&?|LjRd7yOOgWxjF>0HYm_D6kjT{zbw+EW}d
zLvdZ}O=-<F+n1p|8I13AgEgE{>;=z{uE}KZHP}*;W5_elRSCPVilc9~Q52{C#C*vn
zsB9F*-S+i)y0b7lTbsUfTZ6o|Pe`-Q;_Z5AtE+5m-*G+VZL7$(I1p_WwLe^7AGQk3
zTU;MJX8o^v6wdX3ip%wXitE+?TKiU-bc<we439u3Ra>%?WH0g9PU78VC;1!v0cT|=
z5!U>`b`t5flZdPAq&(g6(LQ4Ryvsf!&HqWj?=pAprvCKMb6&;tz`PY6**ywhGp8%I
zfw#W2AsVHPaIRNy23<Ebikt!;H&CtyE>u44AyGd)w!DK47|Jv`XRrKsQpe1SP*!2d
z5$Y&(9$9OFsz>XhC9*~Qb^|uyZNy_2O>57l_eGFqI#nKMC*<jn=Tp=EC!5kmv#x{j
zf%b0z-?5&lkMO^e)!Zp(8AjSD_Nnaaqo!l>E~DcJOBWsIaXB5Ut=Q(szDUQ4%jsBU
z6CI~;PRA)Or{fgYkB*g==s1QeI@Y)7SoF<fI_BL)$Nmm@s^}P)D>^3KbWB`D$9cNr
zi)u{dOE7Is2HD$1ThNDSr*_82Ik!NY3PWek4}EApAo*!J<E?Ni-~86><hFyei*@!;
z-vHf6&&a0MdZfNpW*hGt4hDMA9_kx1+SvE6b?7488*EwIZ+<@vOsq){<hkDYG<@5a
zzr-W5CE*L%`Q!9a^y529lKf=MO{eKQrz6TNqeJ43G@mMgXCUmodv@^UafcQ-MDGwT
z^zXI^Z&T}8noBU2N%q-x0>72*q;RsG6dq(dJvP`*wnsQ$CVYgwg4v#mq~rSRITrus
zxZI8{<-1%WK2%?#5&63G&!X3gztpd6-Z?>Eb)UvK?-}-($v*L3lqWq;d;AOUWudMl
z^Fy83p!7|&72EJWqjc|!alyD6H<Yd78B5Cxe1w{}jdMoDK0EpH@ZH&;m&a#5z1}&O
zVSGvkBk;^aPvgLpWRl)#e7e#qI9}_$USUqtb|0<)k1CV?Q55PZj`w#}?#Aiu_=kkE
z=16P(3z)~&w*1wk&IvmFYkxJ_7;fF&7-FtiwC^^o|5pYpIMLW?&DY~jIM5GxjcJuF
z4?gVQ?6&2-55e{Rc2B*sEmFONyXw_<@}sI={xg*OO4;|hRPT$s>-D`&$bo^riC#Yu
zazu8R=u~HYOy}1^=ki;n?=5`44WFCVba>0pP#)+kHjl*)(RUrWgPgTY)HnZV^M5)N
zUe%hcUrl-1X}$l_rTMY!c4(oYJiNQ=(6`EQHqr7)_hm7L_DigzF2d3aGn!*7%>2M>
zISvC0ec5zB{*#zbXSbU8<>3S5HfIGo9rbs&)?Njd)?N(<uvGusr9bLplJj-_LreA1
zcfq3Zx11Lp@ZJ3UY}f-4VU-`$`6qy_9^sq-wuC3j=qy}UovKIwrO4V&{qJj2XZx;e
z+FOnsG%lf^@?Zyg#P6;*{JZH6*&zIn8F(w(o^Ulcp>4%`ZX!4YGwUDrm;6p91G#s~
zFb~lejT5{qImLW~`s1DKT6duir}c${`3vc`l~jjpB7N(fXhGkiD}6H`ak}1okB^0K
z-D~ai(U>0JeQ}ko3F_>M*9Docuotng%uH*YqH%>=j2k|fIImxw=8wWx+iUsR-uW8?
zemqt`pUq=_o_UPsS<<D_18L5Apo6UKBUAJEOr~x)h5jY@^7TS^$m8?+bL@Lp9<O_k
z1h@_B%D6A=$r)Tv&V5{g268`__lCWaaR%l}CwwO81k33>zLK?^_Z8i$kNe>pjV1Y#
zZrj8;Ir*Qap_k?<z<0R*yy>UVpP!5Uk^Yqr9N1)!<S?eSrgUz(+UF-35!X_*e{lOg
z#*g>RH1bcl;M?<^!}aOyKZQPNy*+DR@=f~?Ym9;XZ?_-9-sFC;+u$Yjt+d}4KQ1!N
zwDE`7Oz@M^CChXU`?f>qd+Ly$zwmqEKAwSR@p|TP4Q$V9Zi8%bxV|JWH7D}?S7{1E
zQ`H`~6bC(h3p%m?JH_?R8yes}rj>`nTJK!udu`rZ1X(=DuM3<xz0ZTU`ia=?t`oWi
z57sGnF16#mdUrrCc^-7s%xx)8EXVrK%q=}}x+na@#JS#>5B=qRcsfu2e(FuMqqBqx
zOa8?B$Aqh7qb0m`*$&B$P52sQ%l>I5r=IlTaJT<N#MLin^5K^=`Ot$a`@sJ>>gA_o
zWuAhpqy1o`aThZ5)WnZ(nb=deaX11VG{1vBygxC9rJrl<PYjU<oidJ2VLj}fk7`vq
zs~<e?h7Z!XP><I#RUdXVd;QUIOKTmL!|;s$@nYDHl1AL`*JtfehiT->Y^)V0nz%fR
zOMO)QrNry|0P<0~O<~5i+}r8)L6Tk`)1KO}CfNB$#Me;!sPSdr<*$Z*Xsoms-}5-|
zXTJ~cBhJ&1pPrvE7WM&hkErZTt)=-r65nY~Or6`2`^nx<?NxE`yzVsGf&SRev$D9+
zcUf=WAI=yrbY9IlPx$1#Vu??*MwIwO_nT|{ZL7DdaImQ}+dbzK+46(<<gWvtl=QFK
zSN)8P)}ImgyFN3Ed*)!Cv3$|oQM7yiC9S^pNsoWDvgKquNN(^XUApCXcuW8P&El?8
z+-P^)M(*{ue>}^lakI_vq0mRu!ve6W4e=!U!2FZs(OT+Ecy5OJ!`utJx{PEK^Pw0H
zIBzX|r+Ex|rO*6mqt@lb=Z5K)h<Dnv9V7jWO{+0b{h{5~<j$h4f4EQGq4!8J<$Eiz
z+jJ-D&LQGXDW<N0uXMkYdHk2Mar!0X6m`x$l=~;4nfkgY%lhPLJ#cZz!zFZs>S;gb
zjF5-*(m{FV9v|*i*Zm}e@@Q|e;IR*h_s)a(ThxESsJniJU;1P{bX6D!>jJGO$Fwee
zn&NVOn&Nu&>5TrT=CpROrzMjmuO87SUi$5vKJn6VGsMeYw@lCKQrfAcC7L=8_!CXZ
zo~7+HwiSKead=utv|8zp*sk;k`!j~9vrB&%@4uMQ!7pa~3O)4N14qlF4c2C{d#gLo
zwTI6*kp5%*JfG%l-rT>lj*D#Di5&FYO7N0LYrC?=Y`-wp8gI`R6-GX@55zRk7-kLs
zZ1$t@<23IriFtJg#N2mv4x05@_N!EF)Dj%Ae5|KDfbM}u)DCs~{{pfh%X4DBQQrFQ
zkWX<6pUwEyiz@8-UcC23esRvv8E*B*=TVpswsxG+5?pGhFD`ridDz%)3;f6?HNMm~
zI9TA{j!F{_oQJsP*}x+lo<n}x2=}UXY}fmrCBl#TLLT*_`i~|)LE*r8RKN0&SNHU%
zy&$^xMs+H_`3>gdYA4|!hUGWVo}=XZH4ao?!U5@X?>nQVeEPR$7^4CEMeLVluZZUG
z_&^&6w}yFq>YM)6CwQp4JOu2+@DktkxX+>s-a-FUSbi3EcloBckBWCSrm^1*@7dtL
zIkYJndx3msyE5O|U4I2_vllJ-2tE_}mGXVZyHESfIf}*~?A+B}2cDpr_PZ}{G1sX6
z3qJbR>0OOC^SotxSLM&j&-eA{On6{gxWmTtop__j6?n^Q%ggxY*doXv=&jm!dtaEN
zsZ83RtGjKD`-AX9<QwylXpz2-Fdn0khDz)e`!s|@?WwJi=MNXbE%X)nuknZ8vr*OG
z7gv4!I;kIx&g^1I9j3c6>4i>M<74jzGH=mz%UiUP?1rZ9>q@p5X<8$b|2XwC-Noaz
z#8eiTy>}{o)296MqUBVsFYLW@Le`1J8=S$f{(XVG41G`=S1r+Y1G~~Vh5x*FWd&nI
zo)O`fGC@b+H(`F*yeRO1d`#Y7Lq7am!FMLz|L~ZOtf<m8W@>wc^s{3+Vej9dpEEj(
zrT!}JWWvDiJvp+|dGzn})c2In_?Lf{IYx<nXPJPENaH2hp>@SU^B4J|%?FYl^ugmg
z$c_d-m0Ws1a!D|+&S2)8++pFPKmFj-za0|{TA!L{FNb7sKb=_ur|isR$4E9S+^}6W
zfcJZ4J^HqR-V<)5-{#{TEbg1?N8Sh*UW?;h;qKbNOIin`pOgLe`_9OoP#xm$IF{Zo
zK-j#gIOxOs3KS<E<=vN-`^c;c7U{TbZ&)Rtdd~s74rDv$6eQcr6W}BI;d`z{v$S3H
zcYnH<H^P(4I{WRZX9e{@XIhIEU&&7|ywx{FKEn2zIX~b}^HcMh+L8Q$hV2)J2Q;73
zek-j>>W(wbi|gF6C;mu#6uRt5#pkx9zM~yk9_Y9}^Di_id77_jYCPmitLENcWzC(j
zzwKbyYooBw+XAQP|2Dp-#^?uQS;;NZYS^Bpk*<BS__I3fEo|Q!@5;uHLmjrmScg#9
zYZ1IX#yL*=tk*U6qd)ecKlXMkx5U$}v32&7iC!z4?z7-3UnAMYH~qBz18$n91sSV2
z<5Ta?Wd1IF=lImO@p+^7cKoDckoNm{9`)6ri)|DBWq{K(axG!gLMzxn$&ZGQ#Qq53
zOJi_MpcV0^zlXxxI!!)z)v=#4$HwqM!mC2K{yN%7_~)%N9Wz%Hp$xR?IjY)F8c$=4
zF}{Q{=u6oc;_Z>Aa{fkb(AHAi`{e_hmh8XqyrAn6-&khqf7Q#%P>*5gUr)MQ&gJ8M
zuH9`OzI<~c>JZ^e?RfuL+za}-b*<#*P<*o4+;8AKEG@q&+@ChH9=r)h>X)8_OL#61
z5Z3r0OSK-6kCkQf)w=T`?7g<#OnGE=k?a$PCHqpmbgbG)w4ktT7>ze=mGE_!>_DeU
zcbUfcub%7Cd}0N5H2xob*M`Ek)&uozx>CIv?HG>n&~{%LJYc=jJSzDIT;6*+Trh8#
z4K@pRE>}F8^XNIimE`4VkzSxl->DC8+x`)Jt6Jc-v)D}hAv}vewWcV!C)r8=8N(s;
zK7Ga3XV1RI3OyR^F0E@Kmo(34ylr}yaAMzBvcqWSurzRYpn<+P`4%?vL)%|$JOq8f
z)A&Am<@>-r66HNGCSOrn(-6+ZTS-QzJstMfr1f`jS;Zrp?61Qw=k*ZPFM8R_-pbRV
z`!tuA?@i%3@F-iv`S1<pbs_hvHU2z4Yoj)dKQ8WBv<&-UkYT3fXJzyDXW_r0zpelG
z(cun*-$UM0r+kTCo7uxSJ{35C^D4%|V+u{{Tm8qh3NWq!S2`mJu4E7B?Cj`|W*0Zt
zTE&$*zZ>D)L6|$%*s~DsaPc~j_=@x$l8e-<F|XE&puK9X2zt<d1nCT|GkV{LVBN!d
z5oNVj?{%cJGJML%mhgF!?ts|3n>xby0y8r3c;lF`#}0W|exLs3``|?nefGf{uZQ~h
zRmflYIS+^Hi-c=v{cj)L65e`gOk*g!G0*_GA-w4h&h|qSwzEv5F<xi>6+gmvq9xhi
zsqeDCmEV2FpBTfT&lwJqe=*^J{TG6fWv{h&^6!#zANVWg&b+g;^~}b|+&zu#TtLZw
zL*r!Sx#13x^#3gBO!zbTr)9r~Z(!B<G2Y$>1K%{?7<9lmeHV?VyyL?mZ`kL;o*CtR
zZPXXgTQw&UPsP49UqyPP$E5#7n_YH8O3!VF6xZX|Yn~h1L&o|31j)A1_T&!>=JNHo
zOg7ITopnObcTS^^F|2zKb{s&KmPN50xu?Cy^YmG=L_DOqWhvSh+|;doAOrJBc1HMg
zH-++vUv{|OfaC4x7vbl^FJr?!u18L$zRAy-!pM_q-7v)+1wLjpM-~o7GW?7FVja!(
z@qg;Sp2?eE59?a;vCOb$RL!r9OYne<FLkej=6~=}@BGU1yEvZ`KZrgKC)1Rt&KX4O
zib3;0wG9rFUC?|=+%p2L*gvd$b=)WV7RSi`+?9#GvUvG(>wV(!*)|_SeB#YIbtc{%
ziTe)Loa=oDhwBe?Q`FCdpHe-?W%Xd+FY%Msq2k)aDUly3Q>_C;8CA(2^Gwzc-Ek88
zDj)EIe8Br}UG4+EHXGY(mvo8X?5k_Ddy;fNl6*|qRqOS?!U^wt=S-dUJg9$<0hd~r
zlK!X_4;lY4a$8}`Fl1H?S91GDoo>1Pqb0dL&c9B3<rVmuv%Fdt@KgC1R4+8mnRvHt
znHuA4Zz>FJRPy;C?Gk61482u)l5mMms`Mn^wjt4B6XJK?<H&*u@wCDZpvN4JIzjEw
zSKDJ6XMIaPK=bl9mGn<~JMqxG&Qtviv=Q@pz6x#I4;$;!Jm3Ea6wUMK3`N4D?2^%a
zQD-BU4U_Bu!t7yLuCsyJI-7n;25GOQXs%>lo^*EVuk(>V=>X3)_?EruG{GmFYtAlN
zrl->h`pmF{BjSW(^T)F@x_h?PpgK!q@FULM){1b?4SbvMBOdNclRbAI3NJy=Wak|6
zIAo*NSJQmJ<41bXW8Gz{xSlc|XVnRQC96flslF<%r;KSv?er;A#r2dCZYy6(K3C8B
zJpT4@repm%uR!-eXWXZFXXlS6Cy4J#Lr&?tMn0ug|HnKo>G!tND_xEpRDRJ$o?q}-
zZ{#wUa|0o7o4ojQbjMl_@8Nu2!{~Hu$lUKWpUx10FYY1;^9^*Z=)bR@i~WqEFP#~v
z!E@FH(5KhMsKe(G_+IjPQK#Z%k0~Cy)VnWzWj=WMt7;EOHuv=JKf^cHJGaAblRl8l
zupOx|JeK&Y*WN4-bbvqJH3zSx^eyxaex2Hh%xhlFJoUM8-SveZ@_L&1vGGFAt4iLb
zHI~Z*O-QfKTmo*vm3?N<WsOAZqxuGx<|Cv2W^bSQT4!SMvvKCM`y2iUHp-3DUHPE*
zu)nD%KG<&4>3&VYp*j=YE!luKPFHbRT~%CF&$g-gm2u9({qCD3r|E;~;Wy(sC*HY#
zt!o|W?`N6EVgs&=xO-8CyBC2w*%$D2d2s9U^-Js|!vnr%#Gh`LH|=S^NrSg>^5U${
z7e5f%V@<<p^I6*b1D-!gmx&iEUV&b6AM8MS?pY^la4yO4i?*m!<r3{w^W{U4wnQU5
zO1~X`yNze3=xbFmbw{MLEuynJbjClFcaD;_qL^C5Uew-;x?~OQ&8_E7X7J$u!SP*`
z@tbt__vKlCUk)xh;6CBvrY!BIhzsiK!Uc79;lk;C&L|ARg?NrKKPg^J1FQjBPF;Oz
zEAgt=QoxmXW=7{RsC(pGbO-ZQ&wV0J^}SQL(!MwH^Pht*I#JwcE%MyUGCaKOfl2Lc
zH12*Ui~k+sv6~(L>MZ`%4<N&i^6rEODTl6rR@5);IT!7~d&TIvZS)j=FuofbqD}CU
z48E5<Fgd@nRqOyy=%3<B-pL;?9P6y8`}ESR%u65ex{dR)7VPxvv-Im9n7k4?(wHWg
z@^eIL>k1yNYgMukUa0HrllX#u_-;&xfnTx^9l4z{$!?n4d|9iKA<D;CCZ1}3hjmBY
zBS8DhWQFqbh!&RBm&Wf^SzlgtnDOg9*MvWgv0kq;Gf57OA7YJQB$MM8(`Wi&nI36Q
zdcTrQ{|Cr-^@(w?jiCQ$<T5_kPy_ZGczqe)Vf>$ncuevw$v)Y%VJ|S_a~XIdJ*~yn
zFAjQA`SqX9E5Y#<JX_E&l6%vVe`Cc|b2_XkZX?Y;V$L#)uJ!G+6yV-E9)1YAj`@8G
zSGp5_Yl^FMT^46u_o}H2hTd7ozpnZvU)^5xNo!06>pV|@WvI9T7|M=thwT6y+ViY9
z-92?XZ|#R}esXq6UgUONpS>D8;4#r~_gxvmzDVasn)vdSPyDbvFE+&4@ESb6JZ-6-
z`gAC(K8bg?(}$9M8oF0Q|DaacWoe>$aM&o&Mez0E>QA`#UZ03}*)}EkX?~qHir|-6
zW(ywSALz0p8hd8L*#PNW=t<`UY6?p>@ZH3BTw4?OHYr_k!_d%)jOou}e>-0%ta*^8
z{wR-S>rlH2Um3$bGt2yZfqit(A+CAyQ1>0S(;x92wr}`4ch>Su{`<(-W}dNcj*OL>
zzk%cAEBD+lwyAq7HMg|<Lr)aXy{uL8?e#{@O&Le!*Z;I72kXP~nUdZC-aQ@nOEgj6
z4<FIai0m@z9tFnw11T=(kM{wC>Y5*ob$vIbhcfDG{Tm_9K6>WE6)&Z5&PypS=cN?a
z<2#&zZmM?gq7CIk57p>Hk~v50`)x(B;~+G@2D%eH9T?z81aI~s4$31OML1`;n?ZG%
z&YeHZFSj3zKE$tN>%ibu^URc{^}gE45tnZZFipw!(0EP9_&3GA($DP&XTQw(-l5dr
z_F0#<Waq?ww30s*T0FitPUGNup<mNMi+UqGg57gxzBS+Voqo{5Pjw8p9DWSDX!aN5
zxM@FtXd65Bzij-zG<f`)j9<l9tmO@YNn_NSy|k6niDe%&qBzY#v@dU-Gg!!M^yjCh
znd@<uM{$*(ds=*&*OA6A(Ub2piesueyT-Iu6boe>`?TgqUekrv$q4J5yX-{ov6H`y
zxO6{|<1}}Q^?UuG&bQ>C>F1b9?Zwi!Wg)VrHt7E>`Q8!c2@Tdnptb6bz-0ID9EN6P
z3sUEz!l#AsH42|g7#_53hn}&#<DKYSww&Ow?=Hsk|0nwxgh%V-QvwZI?~}*>gfuUQ
zd&TPD%<}|zLb^!zAGn<6P-<KFOXUb#_LC=-yF%rNugZaUjlnW~)oU+mUk>nV{n9#`
zd4=?3d1$%3s%VS!q-#~ya;6hy5dW5zPciJ38(@R=+(T!-?uOt`54KyMx!V^GeW9`T
z<6mq{4}G!5)A+Z`cF%wPkoQg0KL4J{`4t7Ss{0%!-^F|}H#Cobsrd7=Tgf)Jj~2cb
zobCPRAlKr*X3l^9nI-k=Jo#qIXip~nEE-?CWwG|PL%Q#vkbj*s$WxMyK0~WIHlI`N
zk#XHC`qaH?sc!hpXVn^eXBRh*>@2i)E4^B)S>771;=RBN9f%fOXFabot`$5s_`+W>
z^va>y6W{Z2pS8YvsU73>iR8I$w$=E`EsLHbeT4JGU!^}^p+Cb}e@5JPVVoRIf38_-
zXYQXK)-nvw8UVwy{tIDv&Hxym^Irpl#`g9v-?F&y<wN3;ieBc2e?t5|cL~3$r(c~5
zKWUvWS*p`C$hyC2B#jSx*!1XlXey28wxx3R&AbYk^l<sn+LMikFYXc_)@oV@jC}Nl
z=j&dEsn$K0w?Z0t;6HUW>W%zU%yU<*Yzx!dTbKA}74v{)eEG(u_T|qsUi<Lm{OJ5o
z#*=Sfs@MM|dO3D4GPHgHXANq={H0qKMccLe=^tVD;r^vQ)C&JEFUY(9kG*$+kLtSa
zh4+k(M#Fm`3?poq9N91k8)Sir4P!tfB!O^vD3Y9z+EfT>Kq`7!4-BbWj}y6-V>=<K
z)6ibht2j92YhHY*)6mojN`hmOI5(tqQrU)BPMz8}@lD;-aj=c8`~R=K_sp5m2<)cc
zz5RZT?9HCp&$ZWHuf6s<Xa3l;2Hx!%*&@0m-<tlP%-n(NfKTxG%y}sl`B&Q4_BYC=
zgzmw7_RfJhpM^}9!IqUeyf4vt5%3w=L^&w3;Q!6cA^sPv?YeKDEPmwK^%Lpyt>W&4
zXKbSnM3>^T{3h*fJVW}_TaiK4Z&e1J^1wiy^IT>RCY8fK$n>Fpz2qIhC&$h}wyE%Y
zf2p4Xc<&cO;ZNc|<x{47w<-Ss%0I>Ub~C2;-0Y2mg?}de27QKk+IjAIz-MS<^rv^M
zOT=xi3W9E-lW8+ZJO<AWu(c!>$b9BKrEL@OkLdFS+VJi{e!qr#=hboXoyAvcKSAVm
ze8=8O3<PY0G6!dC<fL2agF0!0xyumu#kMbiUU`n?=XC6-tL+)WbPvuSq~8T<IOHJ7
zZ=V|&t$k?UoxbC8*kR-&)&pj)Q(zfC2|VE*6ZWgT^V-yFSaIKj?_sVHv8@r{RR5-H
z9{a-U7czSU{fk)b@$|Dfd11o(#7^ULD&Q}{C*l%m7Xf#!+-aa(U?8q??~=Se70<kH
zhCVb7a_*+Q;{guJYwnST3%PfnNhhph8EAt0c^!O7u;=kixRyzI_lb8Lre9v16q<T}
z`rSL)zb<g3<Q|Is1t&sNIcu1}2YGlU_gM@0Bf_uTA@5M5&xJhe{N!``E)BL7Ws^K3
zhFtu2ID1&y8bZt??lgo>bL$RGLmln8JpD#lhx4<{_4Ch#0`~)FdD<N|?MM^QU7GjM
zPCg^g*C+Zz{fxuRf|O#v5cViN*UOlT@4`3hB3&o`3cu|~`a=pO(3X4$90$754rP1?
zvW-o>*t`NOo|z#`>2{c3o-@T-3Cm%uf#cV_R-yg$p85aXbL7HZso|~x+?-R+gqZWL
z|1alUr02Ygb9&Y^0jJ~*!21Z=6(I2(YiVho0~|r-IQ|jXemI}uJZ0OImIH6L-ZAxv
zjg|HR{XO#9xWr%Db7Nlpl;;_#$m=Ga?*rGCsF(39*&E~heP8l{&-uV#uSolG{-h#h
zWwO4zm_!HW@F3~ou>#O8a(*5HZ<8MRnZLcuSTBA)H3K>%SH|VubwgH%&9er?qtFxH
z_u#w^n6cN9*F>gk-#*~AbCM5PZ~Rh-pVBg4<S!hw!iVbfq42eG$1A^=k(Q&m&!*(U
zL|J(O@&j{+UxmyE?+9Eb)*u3!*KqL67&B){e14L@$*N;wMejkkN8o4R9$+2j9gLIU
zc#^ZYjc1Yh<t(Y?7x7DZZ0*B~?q4pAz&;9tM!2p)h4(IlHpy4y@m!fVOnJq1qkeF*
zda-G--+AgqhR}aQ8BdroH_xDgCw#Zh5?VMW-6O9qv+x6^Ec}SAZRWvzncvUAp71+t
zWN-WrV|nu0RdP3sd!Ybg%0X9=SM`{<4-(%Cbqf8t;nyJZR%lw!#ha{~dIT^=E{sFh
z-vxi|xcFq)*Wz1jFSHSvemUBcPD=BS83J#~Z-oGFx$}wMnx_4eN5PL4zq#!Q2hLuh
z`+yJ95ck~jRBqeox3%8Mg`Y4^;Oksl6weD0Pxf7*c5HjMCULKjjp;Zm_~!*?Z<%Mm
z7%xlPlJ`B7k-6hVUeP!P&x)-&&C&61^j{5<Ptw1oQY3dvQsx<-YntKUJcafW2Z+66
zJTAYBZE45nej;&xc~%RbaZM}zh)aPFV=)GieI4wDjj!W5*v8k*0RE@Fj`2ZTF}%l?
z?@oFgwpJ9j^fc5_F4Oj6JHp0#!uKe?i_a1B^0_hk_}D(LZt%S8OWyMZxd#5idnSs?
zDc5EYr~EAhj4yGUz>~ad2jk(rI&*|)urJVQ^8Q5qE<VI>a=srqp=qy;k4=O8j`$Ok
z$7mLnNlZD`F3%s6Cera|wEux4;Q{3I9db;b1EP563+ot9KJ9`jo2|>_uG-jWjOUC1
z54<;#HQ*dU{K#2zUYW$@a&A7yOxY56hn_Pd!-4A`SA?8k&ie!?vlz=toY?WAdB!Wj
zc-RX$Qz4IxkK^nOU2k+?7_s!SM$m|?2kVo#Nv;j+n&BUja*6jq8P_5)Y5a^m=kxgN
z2b*0#n}*NTl-WMYuFUh<dG|k8?(-~yy^DdixCf*$#-j#eywA+DKZv{GdZdqu8Mk|t
zg+K3e)qropbJa5qjtVg^=9hRf;7agBn@7qZhlne{c*$q0bJu0`fio><53xSnttyG*
zAP!##J`KJju!-cEE|fbd*joYMnL2SC_Vcw@rMRbDJN47WbrPOG!ZWSu=UUk>n31Vr
zAJ)t<S1!kx$d_?!yT(a;;(31GD2($A^^lBBeDO1QgLXcB_56NMkv>C<EyjBA2KSox
zmw|TR8FDkW2Jj#!4_R4BJ3`{qC<pKvv>>s@B9Bd3jBy3H%MH8-<DiUkTi?B7Ogyh5
zd`-A8CwWGGZ;0Q?zxYm`7G81;4WJ!k+DU_uo7ztybK%{k+$-)+=C^KL`tM=4!qx`v
z{w9&)x_E~fxEAnmt>CMOZ={&KW8-i*PIL+81CEFr@D107`z`Qbk(y7K$`xW~3o~t4
z*7K7=ZO@{gqrR^0D;i0U!TNN}uNha$j4l!RFSysb1p9A)ua`d2tTo8*+jHMQXPjeF
zI?FxZ!ln%4?n>6peI(6sPT;x}cqL9{&s%{T)L9$J`c{Sw-Uk^|aI<b>^|0&*_xUDW
zPI}-w!no%W1I0a>3VI3XGKq_@_gml<#_9>3)MWaL|Bd_1aq$iqjzv0&&cYak9dkI?
z6MHU^cNmj)kkatb&SDwnro9rN+%V&a{ld?F?30X#duZf(O?Sxe)mh%K`vKmDF4XT_
zB28q`6z=Km*b-Nbv2B0yme3*gU}RS!CGD_(BC`nt=vL^kK*NIfTMF)GTx@^y#1K>F
zTb(eY2zVk-K(5?_M0yh&1vrgRw%nXZrR~_<v&|&3lDLGQURht1$OFvb=zAx~eT>Uz
zIZ-y~IV0RdUO<_RgO~Nf->>E5B=YP(7=~&2V8CyzT@(h9sgTqB9Yo_F5<BSE<IjNp
z#%7#{F6R3p->8uHKHi7D#B(cSw2e+tK9TmwW8fX3zwMwA;DL0JwpkL!KEWO_{*QbX
zTL;;Ap#r)DeL?f`E>*<i$k`wAgEphwGfdUvu}$RH<9PQ`s#s(j+KRpBX)9xa?_)fd
zL6%P#i}%Ew4{ai^jE_a5#+CxC_drgPeq?;cHK6~5@iCW_`BT~!mUHj8@Z-#xdMuGS
zXlL&wW8mdLk&cVv-8boxJSsWvpP36x27ll`!DsaIo;U~aEcu<h%Xn*xZ_*g;;>dqD
z@!H4(m!p2zd`B*PkFnGI2U(<Lfhj{=1MLkxrmjnW$N2J@vV%64?Q6!f-zS`T^7uu<
zN9p&^<E!^ROCW7>{G2&5AoA(qGcUrIM0|+d3LDBP%(ibBCl`5O><sZL@H2k^xIkZ_
zE99)pYa8Z^fBs911$yUs=W#sWQwE(cbHm1kpGA@GB`2QnnYb<sVPEiF{1brZC7fAE
z6SCjb$^4Ax#HlYx5BhyOu*0X5CXkcvDNFe~aiFINlGxH7Si*mab)Y=&I&%FckXyV{
zA$+tED90o|gyR8Dxu3vz={?Gom$`U>y+QvJ?c>B#iPWiC`29?jjXb>}MIK47=POtT
z%2O_Uufz{h>_*HFeA=_B^$U(J#J)<*0pthd1o?3~WCr<o@RbT5=MmgIsFWH@r0@P&
z@4V)z{{-fwT*5wB8jS=%+b9#co@eeI#h8a@8^RcX3@Ngo(T`<-L+&XqGKRp<-=atR
zu<6hDSMWR6GdIOC;B&$E`wI2A_aGkxZIBkS>M#%Qar5D6cmZJLGn}|%6PY^$?MQd9
z7b4gb;@duF$~DV=bG-MMcHm#J4bUh0ukdB$!H3LIi#d)Ne#^yiHOAt8!?)K%n+5fQ
zuY2}jEqKG8JBUA|3Ht;aHESPfJDD>;)_(H&P~0U7UMZ_E7Vi-WoA5Jo@<A>=jnPNP
zeaKT+96=rElyz3ua9r>)%7m^%;-6&M=!la20uIwOMSOy9PkHDvFCR{#<Ewqjm$(}7
zS+8Tiu;$cx&@=Xf<*DmXj?a0=%k{}pXG1qfAm4-*cs7Ns7CwKoXH(NY`Yy;U>T=*9
zt-n?SM_e~;Thg-mY-JK{>j+>Vy#>lKH|o>8>!Qz9rq7fS-Isg>e^q$`_`lNBk>6bN
zS@;aGYtI26pi9zbY`$&h8AHDd0?)&1|F*zoc-;G*mDIn%7A4G(x%w=N&p|y7-!~F~
zKY}vPo{dNYeC9y-$<i8f?zJuhZm3JF{DdxnKPnVP?j0xZ-sR}BFvdvJ0moZWnX>yo
zsT{t@7~<P0)xMa_IFtC*bLF|mw~zIRP9xqZvw1&5yzrbDhD?o&YyVm<za0iG*!OD*
zPQY8_ubH@q=02$f&;gWFNOJbUyA!>5hj}D;mpbw$=K>5oV>8!nCs|Lfz5`DIzu?zA
z^FsfD=P!QuA$a!qFD!rY4x4MBoB(|3_xAWK&3I(1ylXL!&69g>#e3HTR^*hYlt<!g
z__n#PJg;Rs<x!emtWGsN!spBEo{PTy&W05CF~D~@vkk@!gSW%411FH3vaggC#4&k{
zvI2W7e2-k(Ge?^6en7}n>i4|!RhjuHFR05oH_xW9r)g7DkEZn#@JJsU+oWX%>L*>x
zvYfV*FVxwb!|H7LJfh2{5Rc|JCnyKJ^Mufsd=A|qv`QU98b!=3_k#Q<wCA7=Xpb_L
zwj|{RWu)jI%AUR8S)PL)gf6nOn|lNNlTPx=f!zJaIAIfW8$LgtkqMv&)d+iPD_}Se
z7(jE>p>`gzg*F2oQztT-XA;kMYjeq&2V-Lo;2!}!VNPo!*zttN-r*S!IGr#be{=Aa
zao_`MvvDt+&p(ox7yZPZ1n);KpsnBm?*%!J&+tV-{uY<v9G8ZZ@)&KU4|z+*OHmf+
zxE11=zZqiZk?|0>g738F((rR#kfV%Wp}e-`#8cjV_$A(xGy{Ih>ELsu@UO8C_zhUT
zyCM7%aP^YLzxZ1GkQYy2?TF74-Y0#}1g<^bt!$ICD*Iy`{-$gM;|i_~KLsAmjFUdc
zd?Qn4b#E3=kXA9*;464Xmooyo#u?#D=<_mgikL*%3&A(|)vt8@=TJ}D<v!xPO&p)X
z`xqT{LhMZk?@<qvUw~igTd_aUKCLI&&&-SWA!g?NxEYr^)#`QZbGT?k^9nz6Pi1c8
z+*`iS2k=|J$^^R?ZLN)!Wh>{FyX0woZ)w|eeV7AyzJuqHkkATn66iEIC2a~UhAu(7
zkyn8?feUo`IzID#`h1StQ$7J#BEvMU!lXr{y!fFH#IBvW*fjEcFrZmO%P3FpFV-aI
z4R4=Z*~L2WPkL{_gBJIKue^A{y2+<r+>>6RrzhY`%F#Y|uRQn=Jdt-9yOu7;z5=%N
zew%%_wD6YqnY7H<h)bP6so!4*uVUZBuX$u9KFiur7eSkm2P@y4U40RIh;l^R>P8+{
zDosy0@>ulkI<xnv6L~x<(^m8#<r@>ugV0BS6>!4#vhu;oEb86BRTvBWDRD){*DOA2
zo-t95cigApkn^qGJMIT)UY;c<-H`rs>)>Y)8YP_8ZszA8pH<=>n7BMM7WJWpO=OQp
zzH;4p_bm79gLO{8<%-N2yt+nkNnJzuEiQ=z&-b*vCI3%`!v$sx;=uL|V2$>(@aA1^
z6#B@n&s#@-Ojdc;I9i@~bxk$&#GAzhVHW*<O=ew`-LiJtIu=Ii8ro8x?`geWlv%qx
zH*4EacH6P|J3uVYf_)+m`1~{HPM;&CPYSj&+d|&>)qHF7TinwgqAfTn4dk)Q(=-77
zOikBkf;5i78*d(e7di6-b_=WZFUgr-&XVxqU!U<ui7zEj`?UWcPo0bfo11tQ{{eEb
z4Z*k6-{KF${!Z|R@wsE#-&m)dtB}*@Ks%N6kho%ciu*<x5eT3ya<RpkBSrts^W1T+
zjJy=C>4U=<m&A3hEQEa!K}xJxqJ4O)4E%8opRC`&my2`3p^25ut&3d`TAv2LA#66{
z$@&z;E{6@l^@>eM+`@-0?QlLKe&sw4T+7_ZDKB%!PtT3^xYGhojZS!DLrVOND36Sf
zqt3=}a~$&><7wXj>@519088%p;t$C)Z}h94b8Vh}e3tpm!0*yWMcn0?L)M0O42hnQ
zdxS}B+{w<dJo{no?9VeS&oFuE4fCh%XK#%CC1{Ou?M>0zMf@4uZ;_9MnKKXff%dgm
z=1wYm{vBh79qbKcn&pwavMBq012jbX%DK0YHaJ@VXYrvmqmd<eHwJwg$i-KNJ##kD
zXOzd*Va!+neepZ!4ifIkbS$Vpg?OS7+BakKD0`4ED$wsPb}suO_USJ3j_X2^;e;!8
zHQK>e7*n7ntc{;t$Q$}a15r)a)C;TBAq70j?<fVX1Z@74_62}P9N!51fuI$PA$o^<
zfIg>Q{{qetc;5oPi(N0}#y$sKP4^$liYsIru^r$~O6}W_q8&e2h_kcOdWZL8w!C_7
zraTKr&d87BrRqG+BR|GD=xN*q>)*wI?2KGt<dTU!q@Bz20DUT6xJmP}R^Tg_r$?s&
zH{yHJZPI!c>nDD5+Y28WAAe+$Hgd0EaHHkR4A{)(tnyvRA}jAj#sRm)Guwkd9jqz(
z*h#r>%EE*FP2oJU+IbZ^9BYi+1AJir_^wWQujU1=VFt$1x<-9E3?8kJ_jqy-EiG}K
z5zv#3_g_>1{g1OAV~0`ahA;bNC=wex!#*?Vn?oLs(I<)=^J-abWHZWG9s<us@m_cF
zs{k(UOJX#f;$GxkS2mByz183wClSXn5{k}O+3#w&=Y#UDhK{S8Ak*!h#P9v)ySLt3
z&i4E+G7xsH(5P3YdgLB(=i=E`v|-H36m{pen$)0q#_-OSRroyOW8K%ws~BJYW3&f-
ztFyR=f*dGuQ}3xs5s#72<K5x2Qf>@>L&^h;l}dbkqtv0l{N`2U3oB<=9^a5^^QTH<
z^|<5WJL7zbv#0!tRgeQ`5d-%$<kh*bKXsOKyjYkTiVrPuqljff3^;i6fuVV;)zEd<
zr|vFwQW&$Ol)qo=ICyl=N!%G9dgn6CdwAqrQ7S&PI20=fEc`w;3*V<9O*!PeQSmXp
zJBGidi)VT7jGr!a(C;Jho)4BfZ``poe!6IR5O>hAW$e4O6nlNh8Lt2irX7m+IJ5aX
z292;E5nu92(9SSy`PrPKQKeSkSwX(X{Sad|;>S;s<_{$n6r~`0j-uVLgS*yv&nftl
zYUYNp?|2UpXczGPa#o760&8%}zJ2m;#<D?%9L5^3CxwS1z)J*pi2z5C0cRt?Sp@iT
z0$O$ew(_sbnx`!z{DeF3g9`M0=TX2F0$imszdyleG!JX|cFzUwj}pGXk1HgO9^<&&
zBaWqcLw~PCn{r>OJc_vE`0?tJ$1o;;>oB55T<~^jG=ld`jGtUliZ+f<l{mh{(&+gL
z;CH+nKBaQVn59T=bXKYyGzr~2;>L&WcDZJhQwA+Xnf{%VKx%e1-d`MjrDDG5X~;&7
z6Zi$zbNa5?A}gOI9nLNdUj}-)eB=rKp2JJPEoGqd{*ht_WmwB7XbLe|>PgVlli@=A
z?lpe<TCJ)|0q#*u4Vf_Vw6nm--+z)ZAqzNW>WT1zktc+%fe((&IqdkP=eIP+LOln5
zH|{FJ4g9&V6>AwILcGLQs!(iusuudAmUe)YEl1gn@CEX{&cxlT6^PHp{(aObCEi~;
zIqr)e|6pnS{&}URPL8j^ZynE%AAk3I<1c<^M||jeOXKC=Qt|Q|eL`<NH?HV+hyB>Q
z*^WD0kGt79jN5atR~!p{E|dOw`mqn&$6l(?utLwq7Nu$tH@qPLnG!2ea|k10j$Saf
z750oaudD;-lk^&1gMBBkpY)wNc@od3+%>=7-Q^Ql!55CZYiYcvdbT|CVPQiXThF@K
zD+UhewDi2M%e*dWBYr%v^fAy9XvgL6;$gm}FP%K;$9(nh8^z=0r+t{yAMXjw$9y-&
zdp2V2Gk8zW=lfTXcEjW2E7(uBKLZ>FE@QjcuPZ>iiKX8hA1?(RuXqG>iDz?*7r3Cg
zvGHQie6hfQXK@3+s!-VD@-)97c2anVzXc3jVf@nQijffcCbnFadtjU+@Rbj0pQgZA
zJ%_YHJBIkvu-$c8y!;H>ICFrPInn6Id>QL9RStb3b8&yUo)~^(y9jd@VNTHSis%f;
zo{%bMEDzQJUc9e_bQhaO-b?XpF6%^l^dlaogktB%c~*Au{+?3GK)p`b=)gJ0<@g*s
z_A|u!VC@d$umXv5;X=rB2eMt^H|M8<x2CA4;afWwE=rvX7eLPY6VN5<EaW`o`O@<E
z(ABFkUnyw|Iqo9VBH%l<O6%(4Zw?#@O@|#s`LYA=*QOpBLri#dG3E7@*!MLm7E{Mu
zCv_~kon_09tx{u!&=atc#=i==a2(^FpboH~sVnp|qO;I`8s;rj&P(G%$KW48jEZ~e
zU+_6FQXDM?UVb?~H1qPr!m;s+rSO%y*Ue6?j?GG~j<3G^IA{ZUqHsQ79{lF`9fOov
z1u8K}m<F*9{AT(wcY10ldL3d5{Hel0f1)rjTA^mXIDQDa$QSt63U%r^GnXH8{cL<_
z-cRpXI0|};%~r)RtN}7m#r$eGTBb^Ie{(bfoJN3C+(Def^PJ}*z<C5Xj{xVmBZ0nv
zt^j_WX<7z>c18z-+7^Wl90pDRU*U<s3mR6yUPM>}pRZ8Ggw+u~PCa%#e#?3u@DAI~
zaZ-hWzp7AGSQ|g1J#wt&L5`8iwEZ>W?XgaW>--DqBh2#;%&!Rro~clG&a5(eW>&e^
zMz~nH^HtE*2GG%Z(AHYeRiT2cC+%Ea9uAB=5v~M%B|u*lps#i6T=)jiSR6FAMx9kB
zi&Ee{?D3RPct&be?C5E!(P;&#!_!^RJ?&N}bvX9tc*pEgjIjVIin!i|NI|42NK@4)
zWcUf(v5baiBRTxO{21u}c<du8v<rUj=*xV@rQ|rzU9tC5$Cn)11iXN^26s#u2~n2E
zPk-uTvAfhzBswx0S(sw%a7}z@(*m>!h56l=s1BnpNLud)&i!fw_H>lvupM}6G&Z0@
z`2JD!`B+Vua7+Pir$JAR`@swNJYS*iOQ63xzH6jy9_IcaZA~Y%%J&V_KMK3|zT$YB
z3f+Fa6a4ITI`w!y+cKNiqHeXRcafhpea;}i{Y@l0&ZYA5bxyEut%k?u-adotGw?1j
z?Y#B;T<2*M^nA{3m;2pW;{*?_*7I|2rlA{jnQhyT@BF+9`AcypIE?&$Q&x_?tb5Ue
z$7A>`d;TXCLxJ~KDDdbLh-(M!PCKmHYf^m9opcrWBh*DxqY@jJ(?;kN_q@^NxG!>2
zqY>~y1oR#Oy+=Ur5%5F=G#>$9L_qfu(0v4S?^Ibk@k+=wImdkIs6TP<qvI7{jt{lW
zW!Z5*XycWNVoN8n{S~msR7v#SfE#<NVyy7(>S@wgwNizUbA`^^)!6{v9X8ihEk!Ez
z#Xzz`;kfr@*m1{)r>4fDn~OqvT-wLW!2=N$``wCi(&JJ8$nWU6Kfc2|ci`QWAL`3^
z4(TWGan{fEsTODKWPM;;1?X7$PEAetWUd>5qd;nuZ6hi%7kWE1?~pSTMw#s^{Sp-l
zwz`IIU4=qjsr8+*Zxl9-ZO`$YV8SQ;R<bSDemvk(?>O!!LgDGDQN-@;iXHaxoe86`
zzr(P@!;o(w&I_A*7v%@^{e#iHPH0fU|MZ&D<NSHRW#8yg-FLb(vWxu*cl1wv#nVG0
zyJDXyEEf33D;|U_Bj2jP&!O)zHt~-3T<6@_oWfLiChXZF^%Q>lU<c=d?A)RC)|3=v
z;FD@6?v{~9&?bVmv9<u@&DC?EUytE+e#ek2%yl+^SOr<<?FPONWZ)CnmKfL;`-(B%
zDB(lM@xoXC@#<m7@?-NB`}pqr9aZ7PQ?d8^LZ_Y{S6qL*XLMKe4}GC%$_Ka>@8aHb
zO^|~p0x85HU@S{ZkjJpQ5VMQ2!ndbDUz)aTKdf`~UX}V2=)Rsor5>DKlK2zKOz5Gu
z_~}{q&HMB>e4E1H7ud6uqt#*c1ZWWU3-(2+O75$cr>Zh7PyfL$@)Uh~*k=%Z20eW+
z&%{2D>psP9Vqfe#KFqy+=RDsxeE1!pL(zl48^(cLUWhrXWo|9QYtnP}>i&2(=6=x0
zq4?>N`{qqi4))_d$m-z;_&GjQGdGMp`gVUYb&kk`_VqZM`3vgs;+g8zWi6a1x<I*(
zlX4=3iF1(cy8;f*ju$EhYte>!BK9`r5(dX%EVSAb_N7FZ5D!7WnhjgtwXz2~<Cw@F
zoZ0OdRwr@(=>Mv4p-09z9?mBV1eZ!x!Df>&L)1_I19p9mtcpIqKE!bXj~ZTjrcm?1
zzha+2M_D{j3sZwUaBVgZfW{Q>424GjvCxeK)Dz?*(2E=W<ATt12RwBac}TUyo-EkK
zal@dah=T-p`Mh&r{(8uz)EA2{Pu0a%Iib0ZY6-;GtGVbSvgCSv4w}!a)(dUo*>-go
zXv&GE)GD9f_Xs{mK=<GY;Zeu~m-2u#jn_Z4462lJqN<2AJvKhRBR+JwingiZQ%|3C
z;>S0FAC9(0U-cD7L(Y!q+6p|=kx0gT1;;qgBc=H5j#9`{#1+drKc?|SIHRA|xFRo-
zXE+~ukgy1D{>k9>L&VL<s6C^?-dl+EFIaWqX`Ee#VdI_jK~CW=jOWBDhaf9b;aQL&
zGe<;@z@|ADo&q}wW2bJKmC|wp@&j$6PxwO|hhupAt4%Yr+RgkveQER|(U&B13{y^J
z+Nme!J>`TbD?)RiAHGBz#P2x83kL;Hz|kq_mQ&z=$_w&6-*+K6+2X;;?_}eIxFFnC
zCe3^bzNgbm3*#fsaQyVX!uaXW9IKv&_e*0Bxi{6*5(S`T6+2u}ybJUZZNz)?K`YVc
zeWdRb`rJ{Jdi6|j_<bLrdhFFRR~>uIryj&!4abj{E`4MizRTma51tyYSP=bHg}X(m
z=GcDaLXV{12LZb|6uT8R{`h#Y?D6=?RQ&YMPiUD|Qp{(gWL<L#wSKugqhF$J;2Z2E
zX`5@avN77^2c1L5?DQj!T<eIy?)B+$$QMF0I46=1^3e>}O&vSeZ|MENI-z%#b1vw!
zg^pj#;=mT_Snv^OUf?k0pute!PR%Ez!3q7=SE%T0b?lfwHO%L}5Qp^OBc%#*YVj`0
zcG5cZ&yJbC#7^oX?lb%v`xZd1I%9Y2iw&-CtA?Bpynnq4&rG0g3Gj9$+dYN34~J)s
zJc+Rqu=(3)Ut<jH8_#`HhC$augW|h{mO3&$1>D02Re|%3t}9e2<J+92QX6nD`C<jn
zcn{*e-NTyZVK2$}mmh}g1D`B82EF+(VGsO$g*r4p^^@q=R2|M+Pei6BV7qC0H@q~e
z%E1#efiv<=tJVpWAI_46CBQMx+9Hqh>!kBqKSbt%zk?&A^ZX-x_Ullr%^!;3tRgab
z8qUxvmC(B8Q5P~8W0~`UJuCPN^jRSYxiVfccV^3aC#^qL8U3-kzzr8A&N?`=L2kp3
zd!^PP&>dC>#FiI$bO_EOzJ%zqNp#4V=#clU6Pd5!gDv|4eRi|%o4M)@pMhabwS{4c
za>Fwrb7rZt;gG;mfW2NFo&&j4$bARSogBS3*Q?i{(|n04>eoqN8WNaRuFI>}u=axJ
z3)F4&4bMM>Jv$o#91+eBxQJJrkLG9e-AKlMxZe*Mvwf!ne9atxed5{{=dNu8=dqI2
zZ+=}P8!ox73u`A?*N8uBU0f5_cBwU0_=Ii(--S%b(dDtT>q3FCwF+@xIIF6sNykG%
z&xxNp{?vw;-v`=;Pr;W;(Eib|C(gk(I2KzEKEN3}GJ|$m;&Y7MLc2P&dzWp8Gw!kI
z)to<7FLN0F0)FeEbLe0ELYmj+V83Ujpu1=TLw|+T)53T7Oj{Rs5Km$spTa(l#-0}+
zA^88%%V1CO?y@oL8>#2Ku!Ek9KIt2CoK)SQj2}*b=R=X%fU_8O1lsdGx!|`t@R`6G
zVxJGML#$KI+3nBP3f+sn_Q&fK=_$~bw%gXE?Y65y7a`F69MJsRNb@5F;DM*Yvl35*
z=Tfe{B^tRj?e|SeBiXbM7$Sfn0+=FzBLes$fb*g}@HIm(ZZ^GyaXTsN!I;8-^%>km
zP$%=CE|A*~au@Pm_o?ypL3sq_ffCF!oxYxu6L=@laQx!|oMRBv^@Gyk0`lq)t~w^N
z{&?v^%6U15F<#xuZ|KU%JoUuPHlI&utcYW+3C%0K)15h06=|7O^mfuO*DZYSgY9hP
zs!z++c>y1P^J_GIdQD{Bd|wgA<aje*hEJDrdRoFGqc_cmjG8E;KW$_^`Kbtc<aFWe
zndLtCS=WSSP6sRk8(_iwSnr+SIgF|K3cOGP+I#}^TM~WF?}`kfUl2Y<!Zh=_wM9nO
zK9iQU{eG{!hiuJ~_s`+n@Jy`T|5oIEO7`}t8z#tm>a6I6^;#Y*Oq>(ADHjBfiO)q}
zSI59_&p8h64;I1qdF8mj&PnYc%+YHKLWDV71RjCzM;iyQ?$A1l=g6zucxOa8;as@m
z-dZO$6#EcmPvUdnC7g9q;BWA_=!C>M$`#&Qc+NUnPkjz>12*c^_)u8%)C8VBs@Enw
z{YPuT(^n&&g!$s*fh%s9AS0uPEiQN_!<gR#z2(Y@59hS`+w~X^XX3vDZ5x?KTLQAq
zg<dMP_IW;={M4^;*6#V%7<~YcgQL;i{?I7in-Y5f_TSXh=-foAbzT^@18n=knQC-+
zKH?u{;q2Jp3k}bP{rxV;WzaEX5oPF8J7&XXy&80R8OjPkms1i?I1%Jn1Mkfo*d_2c
zKMC1AI;iAMco=^CCr8#7reLp7c7;YUM+9R*e&GAnJEBYdv|)BJkIWkZtz!(pihH-w
zG0ca%$^{r>G<GXt85ymEZ5{3Oh30j9eFxi$9klKn7z1aaKL0M-dN?mbFE3S*qQtpV
z^HovNOq~5A{*bltd3FeN1D{Uf37mo4Fl^XY|8WX@<q6)|&JKJmu4t3<eD_FLJ#Ei#
zfkW8a(=86q5`m^0urF)ed9SW73KUc*q3IybxL$s(R>H3Vm;O4ObEiN*QZ86Nd<A_G
z8wcAnML#p}LAdEFI;(9>^<>~%hK@oBAMdO|zlX#0KmQT-Aq0I|m^vKT8Mo(u4?p`{
zjC<VLPw=k|Ik4rxE7VP5I}v`dpTwpkuc*6YO+F8gi~V#ln@;oiPvR4JoaYOkuZdfp
zwLur5Kt&w(0c4@bvx6n1|LD$&9o1^YAGjGf%H@T}FfMc~apzpEo`hU`PWa~S;2ZcU
zR{1u-Zr+J|VQV*2jwXy>CXunlZq#}R=Qx-1bFbpZo!PMm!D}LqC$X7DMreOX^d_Ik
zQTDg8U+aFzT-exF2gJa?0hP_y6ZGAmYJ5>{Wa+zi=aCur#6c6Vll?h56z6i0uOIM?
zg|fiz8x+s1v@c@yYl{QN*5VFEeVP6X!2Kob%M>4`5Brge^X|-efnTpxFZxnD$fvQ{
zJ~@knK97+;oy7|W18)bs6ZF}mrD=VZ#$RG~w9r>7dgu!kF6DUe!W|`)<Iugn=&im|
zoZTqPiy$MQv#%b?(Ldt1inVxYGeNwI?)BRC6V`KsUQgC}V`%;mXwcX$6a7`ZPl+wW
zK7NRHS_H7b_J^(k@1l?T0(48A*o#UvSX+^{AoT4s(QOsrALuT>ngd!51^U;iHzO}k
zS$Sz>ZLZv;%#08Hd=C6kDauaV5r(3)n;~=KL!UWD-C*rsoN<S>%!Vuus;9*EMJ}|4
zzOf^a|B&H0cl*i;6JhXQ2r&(ecbLuc>t4Gf40~fP<!zYq40DXmhVF#yiv7j<V%X24
z{M}#HQ+6YcWzNjM8&T2Kl+n~}OOFK}z}Xx!0DGxGcPdbMgBl#Kc#iU~rdU0VyUcKS
zUgF%mkE&y*rb5=jo<2kyf4(n7S~zt%{Q)J%pzGvJk8^gyoaG_cN<iOJa86J7)Ome|
z=XdyBhNbMq>8arSkrZsbPa<}h{*@5wT=-gsF)r{l`!M7y&pa4=$+5CUzWJw$)f4pV
zz)pl;Se39n@KSv0a_GZXPZn1%NR6H<hAnWqFbtcrxLQ6x5(>}OI*4ZioOg<`-ubbA
z0d8=f;l2<TX@5HXRky6CztC|a;GY|BNaIL+b?4)tH*?O!Sqy6$gN!CG9EbcCxeWi)
z+cW1)kL`(PmdRg%RykXE={s-xSTY_8{AjJRI*~rFyf(|eHJ~xbZ1A$kq0eW_HjzQQ
zbK2CeQ)_XI;n;=Hy@CHpm<o>tey>6e`f$(tzt+RomUtr2yJn*N*`688^6bn9*1LgU
z=9#w|Z7p1QxeE3R`uQ`(oR{<z*oPPc&~vV>0v)k4ZLh#q39H1pLCb$0dnIG1z;2nH
z8jJmK9q4Y~U9?G~cgwl45Mvbvo?8cJcLKBoyW*xiGW@a(oHJipI~I6j9q<61_ZQhR
zU2r*z>nBZRaE|+YH!zDhT)Km@m-09;0^E@|r*U6?E_T{H#Ds}`ar$qM0j{5t_U2s+
z{(=n@_}V&+^B3YeZ(XDFFPiV$%=dQleWA(UZ_0bj_a!FBIG|P1CTRTX6!{5!4*bad
z27LdCY`dX+y*oiRKfXHKZYW)kduhaRI@r52t7R>AeZoiIs~|tAz;|IQycK!(H~OrB
zn3OqT;5P8r>&3ovrjHzZ1atyFs4AQfSqEMYOcz^j7iC>^CS!)czuoKfyq(xD;cNZ|
z?a$`~&I1nE(R@F7+GmYtbA`Vz1Ao^;zoNay3)<7yHB^|O-V1aaIWQmXYU9~__`kp>
zkeLF{^PqdNrAFq^Ukh2X1O5&_b-I?X%NY|VccG%wrvq<=u$OdvApH3TpSQ1ujffb`
zFED0$Rw>U95r2Yli6P&|H>OZlj<QmemGHas)A1kMm^tu0V}c}Z4!UJj;@{p(+}!2*
zPMP!C@zG!62P<oBOeo@N>v1OGZ|orEIv7-!;Tf+4Vwv2p911}eC;aile_sn2=7g_E
zRYrEFW*>%pjvwE$GK|mR4I`CoJE+wBuN(@B%!W?J8VhHKVb4>pGXBVENEL@MPvD=i
zXDw=W{CNEp;g-Z4iKhXMqzz)w32V4$<Xq(QzYK?QcNS)>DPk(2kDms<b=)apE5nGb
z1Z}vWeZ+Z<I9S8O(20j|uW~<h+u*#ZY6yB{@GFO0;I`y`#O54}BvPr^tV9^~_u@`;
z$bsJ(_vtt@;EtYiV*Ci^jO2^soT70V@ud#IuD+A|5ep~g0*+Md=N0Ag!yAtPH<&;5
zF}_!Y&yyp@ww&#wqbI|F??mjGlXC+<<oeOhRd+Iu9qmBNjPHg28|?%CRskPf;{L$T
zK&$-zFKF*il{<WXn|PQ4JOtq<1H6I{izCM4rtz|*Jl2T$1wSRFfcG7^16T^$T6XH`
zKP=?$Xdq4@HQoI>;sg<YSD3mJXR$kh$3xE|W-flZy9D+X?vSqlO@8X`_no<N2(&p=
z<{v>$KmLs3>3CNk<NN_T+DsYd*(g>98j={_87D~Bd?pt9GQ_zM{}!I>;=YfcPd|eD
z)Ne1u{tkwn5uB-ji=itIK_{U7HHR=h`cE56{XXu<{Ua&BekX8n7-zo)=(jlRM?dyC
z{oq{mIf8d}5bqD69bzS}8FKuoFU4M~I8^qnJMQPW98>T~I6pH*VB&j5HLO#H8DBfC
zU?gRDc6e@Rq<99t3-9{XVc5BcY5OoIJx8zy&<~fUnW>s)u>Ml#4EC=K`?d@;d=+T=
z8tmh8?BUgkbK#}f*HY}?lEm3?Or2$%6ZRT*(o)EY<)Do<<+zV#JV|Nnzrn{f4{doD
zI8E7Dr$gWq=utIVq@X7cnHZ;m0_;zTJW~|AQ(~NkHYvt9B|I@sOFkSMREH_&DN8X1
z{8^7KsD>^H^Sf`PI*dBn<k3ED<3tdj#&OsV=gQF-VxRDx{Py7*#9(3X6!s9h<PQ4O
z@tHABu*uJlhuY?;`G{|VYzg2uGX03fn=(K0yFYRf-&B0dEl%*>n{}%5e70paFGXFk
zsaMD!HhqpGzvWFNJI<x@)6E%pF4gw_N!sr6loxwGUuwMPci|ZVByYR6oU%q!KNtDq
zO^EH<=>&U_*e7K2Gaft+;dA^n_WS;d!+{ULHk*<HjZGWI9vm0jCrEyteJJq9kU7ws
zF$epd(+0FWj62Ry^bZRdBRd)a9Y;Xd5zsPzxBOfL^c(?wM?ljN&~yYe9RW={<(d~r
z4~W}@KTth))UO5~#d8`cTfnm8h~<Plb}gMCz6p1>h%?_*P>T4bP$BN~Nne!rpy5K;
z59b2!@u|5wzG*D5hw)9RF^v7p@YIn|bVmW+ug!5s=F`^_A9@?(n^x<&6F2I)|Do19
zw~lX0joG_m6W<gHY-fB^0`W~L#y5=x-U%Gh2PZK<BVn9d#^(J3&-@gOoU?sl4}=1h
z>G-Cx0PbB8i(GDFk=Y0FO|&26UYg@O!4%`0LV;`97HgkbP|7$!$34gQsUp4!F&K*w
z>jV7{K3ov7_rdtSMWGHcsfcIzMD$L7@u0%FZw>FUF;1|cRN|Wu^Fz3GY{!ViWks(r
zF+~52m=@GMHa>m?dKK$Me?EtZGU6TcAs#9*H}-x13HUT?qg}XT8=6t8`F+X>AmPcd
zUp)mqq~n{ANANv@^4KWv<9?2_+Y)mgTcW}RiL-&{fIuDFF&20kwiebQzCYO3>DUh1
z*;p&=FM&^DJ7A*{M(Z0Se25(YEQsqU_93q04#stSBHpvRHTw66>-eC*HhNO&xQ-Qm
z9oGT>;;HZm&bdo!ao4?-uw~tI`&1if?Z~|<aSvjf+6M7?dWpJ+yaAu>6Nqox6+ivx
z;Jk;wt~LczygMs#{38j(Y?oKdcgRqcsstW=VPC2;jDF#%3ET^$mPViPm1DdT$4OO!
z{~+gQ7Xy#0p)bo}$FvRN{DJ+G_^3g~I?>0K?yr_ce<J=x>4$ljV&39n@Ih>z4=^=s
zomX24*?ZS9$mbgDM~&@^`?0059-lkim$(<SG88}kPlNNOBoN~?f;+g9!<6lSLF78)
z!w`3Z?~n-+<Ma(*os+n`I`NA&T)zW<CY~WE4d7XC?dwn6O*ru0a@b^uYsd3fn4kA6
z3-$cG6G@c7-(TvLE6_1di2RZGCi+1WcUv3-7U=eoC!#;EkTE6x3Uixr7jRsxsU-S+
z$c-FXCGkzD51cl<^iIF#fiFOp=JG(7iEk>&<^k&aK%42m#$O6r&cru;(x>B_aL*?3
zO%MBaaa_m%(kqgQZ@Nt4o5qSS9|^@?@D(!#BydAIzG*D5nlU2a(S-)S4`txvnS=2!
z5_?q-TMc8AM`wW_5KnU$@Ex0n_<Gp0wN*jH_}zzRrgV%SXdf|tI44K%QQ(U!cTxV4
zXT%=bK>39jKO;{8tB&zQS>be^nY4Vh{j}@?j4$}KJi0t1kD_PclOkRuW^!bagJ&8b
z3!aG98o9F3S8QcU;74YyXMM645)boUy<V=BFcC(skvtFHQGuYr{|`KU_#5D8ldq5L
z*=uH=Z+ZIgy>gyD9G~-8JkI<)?;@Xb5SIj7(-W5j`9s-~j!Sxey^c#-Y2uQOQg0R=
zGI2>K5SMf~6PGk{1oG@~{CLd9C4B<t$A#&*qzCfEC4C|*F6jj1<{`Zg*AxdH*D_M<
zP{8k%|ADXRx`@OBL0*CvNsGW|D6n7eH}T1JXZ1Uddw{q37!Pzf3O_US>XApnBRF4O
zxr=l_85#H++=HEdVsPg3>kDuf*xZk}O2kx_SFioW8pweHxyQIr(NYT<aNq}vU4~~P
zGBThNGN39W14dlPfMPGdh6_h<hh=mJW37LRI2Gy+@UO@kGd5*W1Z_Dd*6<{r@6_}7
zDMt(62DyN_;0_X5NqK`f#Cg7A%0#S%^0^#il+QfzhrH9=EbCZi*P+Zh?zj=_sFii_
zd6KMkWRE>z9e%6>aEUy72y4LS%o_B#vIews990l~UY=J1Tng~l%+c^CHfZ>%EAR}`
z0m2|M9yZKuH*h!nC%Llj&oCF(EOa=;JIiYhMI7}6?%@w-?%`vHVRM*!csyrw{GS)#
z9{vRG;XlDRYtY%pxaX8jx#P$FV0|c%(!R|AVz!Al=z{sw1&)&{5It}O^}u*B<oA5R
zT{KG%U|&+6eaWK-ihw)ZSA`1`){fAz2D`B~lxOg$=MX%i59g1dkI)O=*c$zb)fMm$
z`$iIiQ!hOX;5jn-YUgCHbHcpUm>0T+^E&W1V-HGXPS0F{xjAF_0lN=Af70-(N&2G=
z{1i_G-o|~xo%Kg>N0Gaqi}UvlOl6-d#{!??JvYv^XW$c434M<WUeCHmy?rhGY$NIs
z$gjI_hih%6z(d?e*lT{+Yk(tj_qhb;PT1=x11_Hoq_DQkz2|V)Ne#z7j5C40_Z$xF
z#C@vBY3O;(O`Qi^hXTKAV3XLtC6J9*7h}G|uy2kHn%KW^0P!@1v=<G&(y@Si{!6zd
zZQAyX1=Mf>cjy;EfA9`u*2odafWv{h?DNcoz5D^<Rj`lT&k1{Y2>3W%;$RKu0={+j
z{%$BXw7xj-@Os?erN;FAoqEpN>SCkc2>g2XEzS3TgSqn24P-&!@H*b<K_6dT%jcr$
zkB5Dad*LO=h<j)8xvvJUz}*e-O4<-zR=Y0!o$@<SE&EqY*-O8C4Q$Q8mx=QwwH$+E
z2WFe{7uV`~(7Lq4*pe?dIcyL4{tW!n9Oq@z{t@&2uQ}HY?q8|Q_i5uJ#@R1$hu!}K
ze4`^__(p4a<|n?0OP;y1@b$(G%F%w&<KkQ47+q^s<+J{jlk?7yns>Tq_?*6eCjs6m
z0slwOi&x3}GmkSLuTbwANcJ9V@7n8D*4Mdvx_jNlt!4Iqx2&uTud`OHN_O@49&}r}
z2Rd5auI_$!cM`1!x>}dHJ?M@9OAsuduI)|sb$9Gfx?3x&O5Db_q>F-q4)*HkzRhj#
zb9<Y+TDv>Zr!JZ7Wiu8oE?;?I(tiL*)%LAhE4NiQ)otFk31FqaSJ!N~X;agdn(C(Q
z8#m@J-{x(PmJLnSn;R-OY^j-0Ub9V#?OcuZn>TH$sZTf0EjP{6u-NtuHH}RTTPokp
z33B_eZfj*jV@-Yjy1JVB&D*Qv*ovun`!;Ug)~IVU{W<2Q%FWwy%f0aEIh(3$wp70N
zV(kR(>}F{=sw>|$0T(RG#RJRgYY0`<_M5h0sSO!eS+{Y^O%1h8)s>Bv+2vK+w{6_K
zsj038$gy~9*s}dSRgLvqni{rM)-}{_Z}i|)X24jOp{cPJGuCe3Vo;aqPbf^AhRwfI
zle=~qqjJmU4fU0co40Rk+E`iDxV_%3YHRN5N_K3nTioi}F4<#F?9-9#+S}h|T32<0
zX}UYy{<hv^bE{JEc-&2wHTUgv`}&)E`;!<Q6<E{euJ-=+=KiEx)!fm(ySKT&y}QfZ
z*xb?&wp`)%ce~fFEO+<xc6Yih8Z;?1pIL`7rZ#l9>`V5$4awg9;4GPe>^;!K@p}gP
zS=675yX6NKm#^+PK>n_-t*Ucd+xwb#cO+ZO5D<VC?Je%+I=8a56`b2A%$bo3>{Hi~
zZ0<`^EMS&{-2=Vun&qwSd)qO7vbVjt!|fXA+@0(#1NVco@qbTmJKDCoSW>gAR7W#p
zfeQg*yKign?sHp{`^((j-OatN><AIl-rLvjUJKwba-ZA12e?e4x9#8Dn{+E1Zge3{
zq$X=_2&fK-n?BUE_mxd`mqT1D;3Wecfa#!6>*{ZA@8aw&?VSMK%*H_hcvpAV^7kcs
zyFsVTT}%2Q%9{0Llv>ROL9#1?27%r!<(yb^_iiBdpxc>j?&?$hZO#1}S9>~|``X;w
zn)}>jFVNV!w9I`^(!H&{qr+|P>ucZJ#b&^hcM5=mb#wQyH(km8+q!!}LCOApY;Pa8
zL|p^)U6VY}-z38~HSh0e>P+HYnp59A;Q8QCS#UrjyqDWugPrIF7+El4%@pGC$^MzD
z+^ep-%B|~70_l6&_YQz4_F@rTeIW79?$&{hBy^6;b!sxkhLVgs+WY#GUCCahZtm-A
z0`a$YB%7LBT9Q5eJKdI!?miCF4b_BUyOJ$r9E_2tt?mOd%rwM?-a3#3naLh51}f37
zuc;ply3=iF@9gPFy4g&np^+)O+@9{<ev#CeFKKYnbX#wGe=-A^XR_9TBsn?R+uM!R
zc>9p9F5N};xU+9>YiDy)|AD5KK8)fm>osM9=LSt3V1D<e>N<BXQP>P=VsN|&e{Ow^
z7P&XoL#w(Q>o!%El$5xvQrs$|CaX(0pi-{=E9Ia4lF5fc*?&&@&y-inpD)j!Zm>cA
z{CWOZ?-FJImH*P1{;!IE3cAhPHmdfnJ!)I!Hr3VKrOH>Vymr+)uDgEqn#v7T)ipE$
zJ!Q?iTUwKQSXSCK(9r>3e7P#m`AehKd{Amz^ET+qJ?&7*csdUc>><HLtNsA#;k!pa
z{>8sPvi91)JodvYU*5cC-Cw>`{rap2SAOE-_kKV4m75n=b$_<CG;n$<O!(^$ezUSF
z(pC7SFP-?4jlX)O;(r!wU%hqZ!tz&YZ+rjmtUcLx$GPp{0St-17xA<l{}v@AQ}5Mz
z;=?*0`lil*@4V!x!7^A*N}ZY0BKhDyeq8e8_rAy6Z5sA(K>qyx+UuD=aQ|hU$P+(3
zQvLw)L(x+Y{|Nc2*su0Y=TSr8RKufpy=T?_Ds_6>-p;Rorb?~*$gXF1JX4jp_e%#B
zej!|4_b)&B(X*Gmv-+by+#2})i>d0DZ+zxa|MD+YKlF(w4ptrbS#=Il%X6_>1wiVy
zH*DU49A*YQ@_v5-{;Z5B%=rsk;;-m8{0shH{u8;~n%q6Gw`l-|AQ7VcNChT$a=zo|
zk}g^wxJ3P>`WO9%{eRQ>2db{w-mrZ0W_L5xJFt<9ANdX)+tlC3>PhXLeEP7m16CFE
zekF{CzP@B%x_>@h+TGRC*4|^xsMhBGW~JU!S-*`6GVV6+aJM#Ws@_`ZHnw*ry9fF+
zb<G|9O=djUX<e<bW1Cu&eJ#E1J<z&MeFwW*n)-3{?b`#JriLZ}?2y(ZZE+gnnK|le
z-|KF_X|ovV*Bw~q^7~e_>~Ob<SuGVfEH`)1YB=a755Pcj+q<M8tj;~{9m%PXUv3MH
zbePS3&7Dc9<ft@kCya>BrsFbWcEh#>!r0JQnc6_b$$tPQD-c*yUyoyw3!L24#j^tq
zn`W5YEj+`(^6ZAkfG&lep0<NcX7HOAx9+42&-C5gwI9bFcop=@0IWIDxP3h^$oI4-
zTT8s{4F=Gzv7yFoI0(zIlXf^@O&(}TBI6mMul;?p@aEp$=7U-N8@x5{I@oT@ELO9}
zWEDa6z)E|(PtVxb-#gIKKY#<sx^?cho3`NLjm(<N>8J<BJa?s~yB8L3KWs&wfqFHb
z`boy13Bun5`1!FE+Q~bPA+*V-{12H^Hi^J=Hn)IY_qVqs?KXMFzxW<c>|Q2C)>6&h
z^WS8wUOBV=J8|8V6iRLCY;Esu>T7G}`9qMN8E<R#=IySja{C5)XyAjWb|1v~a8EP6
zSfuH#_|U%GQYz>oYu~E7#YxuQ)zUEl{+`g7L_sPgJ#7K&Dz&0qshhg?b#>p?h0o<o
zC{b!7Ocv&~%^hOHWZ=AcZ?YfE+0X-$-|6;X?_^H#%IUKV&naYn)-}Ok>b`kri7V|%
z_I>Ww-93HF-0A_Ga1KZbHfgf)4MhV5?OkB>Y+}K&MN@c(*h*P)43q?i;!bzDD~P4<
zQ13x&iCaI=)x~2J<OwCAJ`sxBLp+a}afqi)z1;&nq|3ZRWtNq@BJY}juM9lfx<$B|
z!x^NE2R9Q2$-t5|M&&?%_wsGYz1?)&&|SmzwRH2)2%@>jh?9&*Y0Dw>E`mx}kQV5m
zgGu^XAqtTRS``<C9B0ve>STR5G|)y7+v3vaGXTGAaxahCy&zCfd1q!#fMI_-Wo$-I
zh-`!{zMXbnoRDU4JLz_8lOf?`sjgdn?dnyl$v3~rUql7f6wd&Uo%RJcL&$cxbu}BW
zFTWnI6#k9>+TZ&Qnr8A>{cT@x7>Qg<-tz2EpGR7hHg@-8k!I)mM9nNU?sQeB6|}pp
zyKM2wRw8ez;yBx=q|F~(h~m^?Id!)E(~i6AL<X`hZ55Pp59rienXap+Hx23%Ratdr
zuj}nzd;95)+W<eF{<DrxBPG%mwtP!_*FHC0%6XtPK^Ymkpq3{8E^akc4JVj&n~4)L
zN1k6?H)KhIta(JpTBof=7xQ)Qdy``CWnjwK5LSYl4r!gAX)9u@0jdJTpY@k#+>5}l
zt=of>%=}!B46eoFTbmzaX5{r-z}xcm8I>@>9?OyK6u7P3N%}$isR1GW={*yJrsH4<
zg@6ZF+-Hz<rE!a9@U>28bG7XC#P-!<bYxm{(<Z{fxu_RKak&j})pn4w^330OuqVw)
zdQ>Vr-TxX4kvjs%WjRxMmTQwtPx1k(J@eF6HOM+^wB73g+|H9(qix%;X)BI4-X0U%
zk{Tw$j^S<792mT#rGc2F?Zo->k6Weh7V_+4{yp@z&)&z$_ArARu6H7>2wWM_;8`=<
zXU}0)J=s)mnm>3%5fe$9D<l=qyp*&sn6y@g{Ni`748u_jx`5E7trU!q(bdMXlYVb)
zkjxmy0>iX2j8{S9+(n3tw#k9pt38OVb*?#9=2>G}o8aok(^jjLoN=LD+WTno7-43{
zT_G&)X<OOT(;+v^fE@Q*-CfX&gf`3GBl?6vGqjPfpBRc0I&-fwaxiNbU@J~A^JLu_
zyiRDJK8Ko#c%eYUM~gsQ7GMFuIPLeYbX%iGyhllPr#f7gR!T-`X4Z%%8Jnr*Ku<?|
zOM5@>i<*0SFePWnwzNfBPtu>ZC@r=Y$i+(y;h{|f!w#{lF|XWfXu}5c6FYmF;ZA@t
zyR~^A4%R&Ka_wB6<pJPkf@+X6PB!#AartOY&CA3Kk-;BE>mx~IkPSq)!!v*zM&cpU
z(qJ09=)pr(Lk5pko~tDa-|imXdT?2|VS-y^vVLr<g(TbAQ_7oeZ!b{2_I8@K`T*X}
z9JQ-8z9B2RRF>gB)cR3+2ej?qigSeAX9123&1TUJH$sjb%{|ha$J5+%33_L(+e>%#
zxcq|qaYCPEaKt2A_7QQMq63zmwqPfLBX>@BW94RqTEGvL|BNu9eO+Zk!$sOxS!gnl
zOu8m9ONo?&xS{0wcH=PIMik>dTUOi5lUrBj<YtWXN!BLgWujj^BWBZw7q8MMyXB<t
zR&npzJ8;=x4;45QWbh_t$p-lHmhW)s5%3(^;iAgljvj+cw`+Wp<2AaM7|#{(8dn*G
ztTUJ*x$x<B*~_4LGg&+Dw3D}MTzRQ=82DCRVjZSg)@WjW<-lj#Wq~&VzAQc!dZ+`Z
z;T9Gl9_bCoPJ8Ks=BdVIHj*aA5ggK9C?>YcJKO|VS7fI34mY7))|x6?aXsJP-k0p8
zoQ4w5P--@1!G%mQE*{kky}tReydb^hvAjUFdDy};&|84XpmP=7;{TpC<=u|obgbV9
zKeBI^1j{35F12szu_goSqV^gbjDX147=07;lE=U1m3?VlOH~WIud2JV6V|DAXwdSK
zLmzqVqP8NOckI?Djx@R|Iy!jBoxG2Ay=8SocXM??Xfp$9=FEa23zztkIc*!~v*s!7
ztc72ZH#&OwgRZ_g@y?JfOD2rn&{)}cQv-OK$E#Hb=&A9_o?IMOLe*dlc(ydDduI~c
zHjUG*mG$qg*|G(NawetGKn?4*^mh04bwfyCo=h7q6N)(5?<wQiL#}@IYRgxS%N(H_
zwy;D8C9}q;)&Xm7y)?vK9Os1X$B;YkT)E?F6YsY6{x;m*F?gtDA1=1~+l=jJtrBu}
z_S6@FRbaRVGs$(8%Y#0;S9u`Mtlga1^MkGWai{1Ku;x8<!@k4q>`S(|x3$3nN4yx$
zPgvxh-el6<xEYSu-2;1gl}L-P4>ydggmohqk1)vX#UnTQHy#&pWl2Qqwf;wsn+@j0
z;Y3u`BugZ^i4mdai>}p-k!Lw?ehj-0Kzno7LAM8pAzbOJU9gE<000_&b`oNOS04AG
zP?gO+ZQY=LffZNAIGr?^TWz=?;CZEz?CDMR$OR$qbwq0-4qMvFwI><XMw=;nMof3c
ze&3vD;GO2q83!V{c1ho4zsdIX_U0Sy;ngJ!4e!x>?Cu8KT}j63wLnC{SBg7V+R|~i
ze#bSKNW6z8#MIEX2mqMfZf84U9)Ukf1>wgEw`yxO0*4t2ye{Ji+WyXE?tyi3pw3sV
zZuTO=EH>_L?&5af0LU9^XaUGf#NY|XH|}WSL==jdn~&ZkZgsod#sdv)?R)xHT&Fvf
zxrhsVtK-*SWc>Px<4+|<d%FAjmvbi(rrQ2Kxh+A|aNhM|4-iLQ)wFrr=0+P)*xP(t
z6XGdb-KxqhIDEO43<^g?AGS={y3(aKf`PlzydTGV9vpc#>KF9l(2ZQ^6MHVIkNvTY
z4UOCD>T0S%UxEvLyUXh)q1>H_R_3*bL^sCic@a_7(<~v$T3FGG)(fJ*c$18QDKkQW
z8Ua^MEO1M)d#wohY+DMoLS_Ppb`J00y$2xgjOPL3upigz%P1ESK`bG*h+u%@0-~$~
zWAus(o6k7Jy~l5RH_}f}vJeY5r@FUYt1^}B7c|G=bW4)|i67xVSv%<rMg+oRX^aq&
z_{ccbBydmvjKojavUoa#wS7->3y2h=fswU~`{Ljmsl*c$Pzvz96WX4A{jJH)fdg?D
z_m1$4KuM#>TTcJ{Ko0^ASnO%P8==daWe!=_;ttv5%y_KFH&<$niJ(-*E0LzlB%{OS
zwgV9+oFmf)Hw3LB78#&Sww9O&PRdJ|Ogqn5SS+gY*ERPda($Az&2{<vG*;EI529lF
zo7%d&_u(_bdH5Bm2KEWno`Eh1)*kK+S518P^!KX$xG>zmQYqq|ZXg(r1Mba>`*ym(
zBPCW>ziQqs8QQwN{k@qM_>Q>leiz}yy$4Zzz`Ysw`N%;5oag5H1MW_D^QNtJh>q#&
zYu<}nmEM;9t!UaYu*{{}>P3mZ6qiECoOB<IUJKdaZcQ?<z7GLPE+5`$H-osPh)~$S
zVmW~pUrpaqGsMNms82G$!2^hQ&IvPmTLYB?BDV!_eCujSc7Ube;<Yn-*Zij7UwH}m
zSGt=dh`A$c?FND3dtVNNUtei^v6BWUgU^evO;{ex$7m+Fd$~1v#@N5o-I8p^gHAGa
zo?Yd(tD76`zE9Sk^kf#{*<Oq6bS*~nj5U!S@^rWvVP=Nrv>4VqtwkCMKmEi?$AHl2
zrP_;6uy3H#U_*~z=auj_28?$DG=JbQ1~UnXZ=n1k{cop9uPt-&)@E=k^QYTQ*u!Nw
zTADHJYSS!~f#0?PzTX5<WN>ux_8MseI!ecEd8NMT%z<Clm}e&m>ZM1~@R(~AoP;?V
zAj^^&G78TL_4o(4tn7dv2Ci-|_hr`Q+P%kU7JiZO0#L5tu#0&s{k@E9`^)oup#Q}!
zcm{>}K$-ntLG`$;%?A;Gw79h`zPPm$iTVMG6X&vCDfg7&aEE0|DJ<xgGS$=E)!u@M
zXhnDRA-WJ+W>0*BJ`eG{xd)H_a6AkO8?%hEyHC{8zNC&yM0jG-Ev;#&qH(?(_QXC0
zXfQ5$GnGLn%np3k=R;hoK#A~?5My~*bBlUfT2{67c6V)Wa4YLJi;A(753%0u*5m0%
z9P1heaBi0~R3k<zQH}3x+TOsAx?W8_hDU3*LR7TxIp`7?Sas<!$SH`vvSZXY0vNG*
z#J#9^Fvgk3?So(g3-{fCd(@6*Xelx#aA@4NT{Z*-2<<MD0pue6HeCG-^uQ0$4^Ce$
z!Ik<W?k!*$1J5hofoFdtn#K4QmT}1C%a`L{)?WwTyZqr3I>2s|0YC)(&G_Em($mz}
zk;I_~UUs+=;V2QEh+;jrw;b*FcHq&fjwWb&Qw?Xr=B`$WW5Z0D;V8PvCo&-7Y()3-
z8M<u<pX0MTFk}Q0*a$71Jv0#blozao?iRx~06(h^@))tEEp6Q}m~Z8yL#XfBCl+wr
z-3{@i@4^&jppm0(4va=&2&)rudvc65hj(pgqd#qB^w%W3xCbE6us+CpwB7A{S$iwa
zg%@qt(cWR&A-HFtqq)}(r>#<~6TVsybDt0erKFioYXOb(O$bIu1*3%bw|8rWj=k0T
zL2N!8ZpE^f(q(eO>gr?M7&cDAe<}KPhgKYld*F@hLR?y(W;2O`B~CXs;mOO5TMS;x
zl(=HH)iknhpeyrD6N>BzVyD{S=fE|IK|S!v^MtVG6^r|>a7)<&!UT3UGz%_N#p;K9
z$D-5NR};EG5G|Ew+rat<Aztx-9#~h@oqlLf<{)3l{Gd1PqQv)Jv37S~4~V6|ZT&6S
zarC*Ruearvwp+UJP~*y5+9igxtnCW7c`u|2Y&iNh^Nu8s5aJRRaEl=&x1@YpuCoWU
zgJ<vF!uoYIG=!c#;AN)lz)8JBKqn+7yts6GLld5~t!Zd%s>1`w;`m=m521-XfMqFy
z2R(=id8AY0LWW!BVjnzhuGrFj8+gM!&?q;PcF9-JpC~*4+9m{B+u<jyGSUBBY<Cw8
zZTvN2rYxE3UQ?RYT2nT|=&|Y7EakC_N})<05M7}O**Q%ZdY6^zY)dvn;vn=IR=;Ng
z&Pk<s>tuDwzIKFaTPIFdPwd+yHCkR#Qcc#Nt4Gs!R}UE&@M&pqYZEw=Fm)R7K&|cl
zZhR-GhqDsmoZ^RFS`iDtb`XS=L8_|<pW?W}Kd_~X`gWO1d`%U(3-K85gdkYng@4co
zXC)NjS>d>w)};EuNj{gU;p^+RB`gDl?sp~BQh$!?<E4I80CY;a4Ng|+&)4eD?R{WW
zeeKV>-Q4~-mtn@3>M3LWo{oXOHsr0n-8dOi(6{rsX7uIf9-M{&eD@y8FH?r^%Z(`K
z84nf^o;s#|VDye&tnRNr<Eh9UTSX3WOqdQJ$ks{6kVjhUZ)&Qns;a4L)EWSh7@%$K
z?&lZ-eTbO5)jYGpBRgPYoNDhjiVK&TNLU04?V8PX%iR6fmaU*--3)oS-i2Pr?)J9t
zZR>YetXXs2@|ES~s~M8+8KMyysjIuAdoNCeWv~Z3Txkz`AE#D4MT<wOF(+II@(6fu
zKOPDd-qA)Bj?xO6&<1qCPDH$uv9BnSYhkINyQ-^~$M5kRSG|1SSYIjcVrZzZQuIb_
zu7Y)st~YI~uc@r6t;8!9bTGPDYM5VpI9ivZjhQcwj|5Hi4eSPV`s-e}W^RLh!fq`C
zz#YRtV1+@d(>xI60!rb{3LcAr!0u`8h3x`_YLiA9_rYb<F#s3(QhASsY2U_Ew5Pd1
zX6lR{^wx@tM7?`s1J5gXKv_IKMrVmnpr;8^4;3_DwY)OcQXJp0AX0)giTRz&NPou`
zE8+}}q?;EH>@>K_7|NM?YU=~ABk_dwssngHL0-1e#>40CWD-J;*Ex19W1JxHiaN|1
z-LSqnoUvtkldRS@iS5T7gsZI|ECTrn*PA@mLl+qP!4pF1ngI@_`l0DeQ3l>VnDKCC
z!9c>(R2Ny796{hPZkI=7sLZox0AJ=TLF0>t-2v<^??YhDc{&jWw|O^MIlEN%;~Hgu
zv60<aU#C4-nSEeA$A;C>*<;O&iT0nj2@pyAX#0`<8Jw5yYRU(?^mFT0u<5-3Jtz_+
z`vac-?iSu&;WGpR^F6)IdwI96tpQq5;yQ%P73|V02wO}HOEV9xQyRJ8s)<{fgGmc>
zmdz_ZLyfB{v4zFn%^eG{>Gj(A*u!lE;@lc}3=5W-I8o#YH;_*5E?S!N%#qa_^>yOf
zeiMG#*0f*N^wCc1Y-3*IO2jN+$GHM_ToTFyG6OM*V8DHlJw4Q(6QD&Xlz#UE(XDyN
z^p|eJx!LPm2K<Q67VcaxcWefy%X@O<RT8p$*&Q)D<f3tz!$^UuqOpz>?KN!x4T1v^
z{>xk(@9alYx(cQ3^d*WQpwkmdRN+++d;6~G-m`};7}TI=;}$c9r8hfJ%RcSbp?oP_
z+y`qIGP#$h?92)%sYwc1g=h$T(f|PtOW}9SoL9Sd^W7SDJ*9wETVQAp#@8Nfz1U^M
zyjUjfd&D&1n9_#E0KL+v&ng2>Bmh;%1_})6_LP(WKiyuq9%JyvgEFQwd4uGhrE$6G
z_LlGR2^YX+{O^PeyCs$i+~p9!nL0vD3<G<42FbL`$OY3{;2<niD7;=^C@2OIN~QW-
z3_nQPdk$8I*FySa(UzE#yl_nR;C$N+F_NTj0}8%L7$FY%^m{t8Ro@^q_jcYO5(8V?
z0Xpe~<t-m&Y`i}rZCnbcSkE;a*KMuh1Q#ICuDWLHO*?esjK0#gi>R)A;#$f0Kv`ZT
z2yzhd0aYyR@F=go?1m3~cW-xdtG<Mgx`D3b0eFBJu}c|h*daYWeEHC_0>|?8Uc$yZ
zOQ=9Q(G&WQ=oLQ>r7f;{<ZUFlyU~(%881?S8`{q>==)g>*Bj~^w&SfwH#O8$R#(?g
zYz+MOH|@s#NWPJj!dnc=-cfd4+4X35BOVo{6z}A7hFqSz7uyC4-q=w&^Fr)l%BHO~
zTQ}fUOSPcM36SdXSCp+Rqv6fDWHx~*YYiA{>rGo4H&@{mRZWx@d4|eecUGS*+qdVP
ze;Y1CthRvAE2W14N<Z1YpDQI<ES+?{i}gN0xAk{tW3SungzQt!UToXGZNrxBRqu35
zSLEG0o?AF?{t-9QuAp+JNlIc8>7+Lx2mjdj%v|Mp=gP%#b^UfA`eGYq>CRpp>V3e|
zTxse<oQu9lGV#%{eZ7C!TUv28c)D`{WQ5C4n5uj!QgfHP@*Q}xO+i%fniY3XwuN~E
zQfc|}H8@fCA|wf3l+rRhos0l(O_mr6=Qa`UE8yS3JDSpMFeG%?{#EJI1k5eC2?;*#
z0^r+e#Q_tZ(6}Ji%Y@JY<Ruj0A@t0rZkR2?op?r;atO{$^Om2qS4W<J?<=$Qcuif}
zi$@{IBc@jjs{MQ997$y*Z>ZvRpniZ;991AsAWB~TL+cAt;8HKQxKurn;`uxBT_@;t
zI>FYE3W|VTtt&r^@<fjlJQP(yd9KlvtMWuK9(7bqK4d=mPpKWZI>8R4@o|=-%|-sk
z@ptx7A4mBw@z?QHywe|P?bn?DlxyaW@o(m}-}}s}Ii3If!jB8pG+p%De}9XC-(ukZ
z5C)DyJ}`aOq=%3*J#5k`<V=s5^f+>+vnD-@oaqIVUP8`v!6fG-WIfV!ljb64T42&5
z<V?#<T7{fxtx46$nYNhJh@9yblUk88b(qwToauIx29Yz}YtsG5nU0ur6gkspO?n79
z)59j6LeBJ<Nsl9EI&0Fi$eCU+=_TY$7ff<SuzsZJCe208w7{fA$eEUzv<f-XT9c}g
zGi@=c5joQ>Cbc4G>M*GvIn(VX4I*c{*QEQAGaWJMC~~IHn)DEIriV>Bg`DXzlO9LT
zbk?M2ku$wu(o4vhE|}ze9qUJ$Zqi)jObbj}gq&%aNvn`Etu?6{Inx%C8j&;IVp1z|
zrVf+(ku%+H(jaoCdri6@Inxo7jv{CJtVs_cXL{JAQ^=VfGwE^UOlM7c7CF-kCcT85
z>4HhlH?V%B=_buZ&a}X!MaY?!nY0Qy(^`|Nkuz;EsS!ETEhe=hXX-GiA34+QCJiEI
zy4R%pkux1J=~C~Y`2TzT`EM%lyI7Cv-F;5b-4ERKUpn29^+%htvY~48=8H(>OVv;8
zT7AISX5aM%6W_tRHITfm+_m{_T5CIb+x}<x+-lbYVD5d=7wkXl3qJNEUvS4i`hvHQ
z%G&0l%K6U#>%%`x!&B_86Fh6U<X>Po50Y=k`o=tak}{tQF0vpObxeLFdw$_Z{v9H|
z{COtQ)#@ngHEdEcZ03`(Oq<-yMFG>lXTB4j{d=g$ADr&@2S<_m3;e;ejvut?;*2#9
zqyOjm+Xehs436Jnwk@U9__*CdA3pQ#eEcg?<9AHcpHtIN9u{OBcntFX0m$tGe*6S9
z{>u4}QU_6f8s!}a{XyAdQ|?m%H68VJp@QJt-zf;5-&_z3HWZ-mY`niv|D8w{q<OhO
zji<|>|040I|K=+HoKR@??Af7^&ySy6a})Zn7Uy85;?HEC-B$Nz#^eZz)0z6oKAWlj
zQ)Z80eP@tHk;agoM|u&d^b633NUM+%NVQ12kkpIgFMek@l{#)#^Zc(0f}xiSf~%13
z{dGamIbRSgM`}bWensO7ui{&|HGB0b{nbUr1fTx5o!}4>+OEjoHiTA8y6r={?K@Vi
ze5aI|e^NT<_UbL>xMN7>%G)$!=BD%)m!IV$+g>A|{_p*h`U-wM4vD@JN|4jv0sSK#
z`Dvk)vAhv7f+F%+lrz0x(o4vhcKr;$7x&*B;Un_W;iFD4iadqH9IOMr8y{cG&u=e~
zvIP7*f6DK!PKobg-<d$)Ol;3;=C`1nY0+mu7f7urPau)MxkJne--Rzb!PS5VAAkGz
zTMYab1HZ+<|1k{ARrtN^TKo>$`IDh}ub)(_)CM*8e<XtVjardMo2shfZmD^qam5-0
zJ8c+fM@;y2*W>nNbs3|dR+g_=Q@(1&bprDu{3~`z#&n*$0A;HSRIt{wDwg@x75JAD
z5Hc6_M`y@K`A643h?@*uzi74!p2}1!U4LPVt$!Z%hs6=E8|nJ5<7(E7f4K@Cp};kN
zy8ags<+^^sLKR%?k-#+m{i^XBwm!Sxb5Ggw#>Fbws240v^tc~_4$$KsTcUzP`lHnA
zalf_5XX@>^i}1m(-gm7nFJGqc^W?xAa;?pEOWnV)!nVuqzq;0z*P>rJDi0vHR}*Zj
z=efPnwmWX-If2}JDWTilu*<ePgZjtN|H$%ec=UP~ciMKJMg3t;Wd0am;a8vBZ|kee
zRB%^`Qb)Jz`5s0-VjCmZ<NfkaZTs8n(B89e8m?bFVC&Dm3-AE{FEps&X^*+D=l$iw
zw%tR&r-G$uceVrLVV<>}`0kmv6`%d8=R3B2E9!~=4&>93A3)v)IG*o9j_-BdDtH0;
zmL3)4p6o)-ed<B(AWxa{`%R7_`P1-U`;?vM80r^b+*7w=ya{ylqvvhAk$%uW2R46t
zoKwHH^@9h&Kd38xp9(%?8zI;2ZpBZ)>CR_Se>=)|{Jshv^0d?VdIYG{?Vd+H*Z(4N
zuK$9`Z5KW6G}pGrptA47$k%%IOYi4Lud(gU{(%a<RAfi7`~A>*TYu&*6?{HZZRlaR
z*4Cf+Bgmx*<3IbJbp0Qz;Iawz(Y?0**&!8t(KG&M@!79x_uKl%@78!c@Ie*i8jm2y
z?;@+?_h5gKkKC)oj$3q}3LZ!O<H%Pb4}M4mUqJm!9|m0^U+@u)haDeP!5yeSjvU0O
zI__7&Tk!ofatGfZ`xxXR^0^;Z!DA?Y7<oVP^1~|Ff&2(^ez$)b?+^Z|g*WtPnlH~H
zAG3{+YrN0<lx_F$p93$jXYHRJXZIIv{qw_mo?AYdkH7!mYqnhn>bV~Kw-z7#Ds|e{
zpF({j%8DP*^y4B=;rlRhuKR*1$4B|o{eSi&+u!*V=mRz9ky9RpjsottfnUF@zc(Tu
zk)HY=y^cLE+x~M;XnfxCx0)|)Q;m;te}SRz9@MwmO60nJ)eKwzIO@IY)b(>Cwtm@H
zRPcnSzlP(+D{cL=s6UVTvwxS3&t)j{tI~4Y?giA>VgJ{DRnyxp<hOgqHS?~w?a!iq
zm#2QNjF-64*4rxGuf4&Rul-u~dNdrHciQ^<QQw2k4*ZYPk%y3TZ2PCjo6%+4FG9T+
ze|r5_9<cR8W*qu6tL-4j^*GH#w%usnaX$P}TfcS$@)7-ZAb$*avVVG<j{k1kE&7HE
zj@nA(8lD%9+4>8p??8FmH&t+OLc7C%Yumkmdaj?o*m6%hJ>N&aZQGTeg1jrtG|=_O
z|K8S*d|L$*6YAHWwe{-zpq~lr`SjDa{=^v-9G+m$Joi&uzvD^B3kqoSr{|yc3tO-L
zN%LKH{a?Lk>r<%r%0b=#UH@k5d!Ef#fBsjte%DV`@LrER(f#Y*u=Owe9Qd99|3~mM
zu#SMV<5yZvWWyIMvh|-ueacoM*W+I`#nvx-8Tx)g{mkjM{w35O@ziTR`RPnsZ>#jU
zzZ<gUhkl(8uG%@a{#n#NY&#>@{pXh2`r-4?0~6{y*V+1eU&$w@zg=(ZJ6_d##txy!
zPwlbwx4)Ke{`T8#{pt%^FJ<?C>W^&w^QedMnf}w`cOSO()8Ei~%r?;VYd>S_&yRyH
zFSoUJ{U=Y``oov|f+ygrw12w)=bp9obt`<q$0zW`FJH0si>~(t$7b2ycKiji3k}^k
zn|#4D6Y76-m92mL-M-*~33T`Sm9~D%E?;nDPVV^c+iB~k_xZBybq)W+J+}V-+kC;p
z6YR9oBes6o`+TCm><qep{4Z_2`}@A2yWQ5>^__Xz*7I(Kc82}a{lhQW`a0adESiA7
ze+mW+e)`Y&f=4I7w`8HMFa8H#uxCR3z7@892zL#0J;5z{{(Gxz{gE+WaBYc&&cgqR
zE?Yn9gU@)v{=D<fbbZJl9O4f&nLj;#@NaGXuK&&6yMReio$JEY-PO&SS=CcrT|M2^
z)jcykR|XhhxDQIqh^RzSQBhG)5Kuuuh=L$$#5-Q1q9(c{NlZjT)Tlc#iAEDmvSTi4
zF2^M5jvDV8@7HXN694!8R@Y2V#++p5obx}=e|~u$s@J=|Z{06-d*`ju@sGGq{Q1L?
zeLL*K=kNCSBK!Sg;&L7vn*Zg+5!L>g(G!>J_o4Q4rbqT|us?(Ajp(1L-;;+&_Ralq
zwQyMfb#996&&-UgtvrEL|C#i!e<`wW+App?h#tJd$Jl>)Ph>y!z__}qAxa(Dr#~Or
zb4%jtKZJ;8d`$XJq*b+j53h{Nbw`wgv9E85?7v<WSF?ttzj{_=&*8no)?xE+?()cf
zE8Z_G95(-U`)p))PDlD-{o{TkvTr{lu6l=E|1Y~QvOl~T<1;M%_{SrA|AldN#jyGv
zG+_VjMRB!kSo#~@h|>365?9;IDM-4=^v~{vx@!MDdU;&+4Qt<lyG8cgzs1#Ug{XI<
z@%h5K$o{ii<7)n}{pWl<nlOb{zK8bL+^3rIC;TF^&;4~=bq`x#UGGNr4R6HNrs4Zn
zbA2`ccM}PP!5a8y@_%n;WMAyy9YoK7xjO$o3w;$+zbpC@YMJ-9_BXx|+4=q`Gpv1Q
z-W%EZZpj%ozF&GRvhy9(@?q&G7In4!Q<o-G|6uXe`nBy8+3$k=nqm9X#6^*P;p&8%
zKWu({WqD-3Z4K%-%-()#WWVRr3AJHZ`B$G4+4)|pru(Y(JL2ldz6|y!hNb`cb&-A6
ziHRZC?`C}Vzdo{W`y0EtZh2(D9%XIP&Av5CXRl2Rxt}-oPyINuUjh5A!`gl1uOj=b
zlM?EgD0BRp^ez7x*}K=H-8Jdi2XX7E*CPAcn7Pk68^4@Mo2$Q3mL@;@^~nDN*lVxf
zOgnFlIn{YEG~LeeD1P3Cgu=ssfqy37*Bc}I){Us=FnePmvj6N<ymuQ&9kp{#C9=N@
zdtXgEP5#YOBYW>>Fu#VSe`R)L-wgZYVfOh4ME1L2-!?4&KQ4>xi#H`c;(lq`@sWKS
z?8E2hZ`Mcl@)>x~J1qZk=STM5Gf}@`_7Pu>?90wd$a9aV38wvrZjbDnVgGex#ILcR
zK471Jc0!#!tpBh4UX=dPa}(;f!_I#b{utSBy&$1*b2#wN<p0o)$liA`*8hMtD*yRP
zx;k$j{z&^f{gHjcC3pv(8O*@sKXYkhUvmxY!>(VG=SBAA-@*6{JHKz(9@%gDQ9|7{
zto?WYB(g963EDqce6{~R|5Rk3ac@GsY_?+YGWA;-YpAxb`#$Vn!|uC|YKiQVf0Ix@
z8&<#X?H<`bcntgRu=<^`BC;=gBBACC%m2xXBm1q-Vf_s|zuf=tk^S9QF+Ri6@BG`y
zeihz>ZyPqgJ6??JGw?3_>|y7RA8EJR{(CHN!iLS?aBO6s2Xey0!`fHaJF@pA@&0^R
z{jXjf*>6kZJ$NuUK&Jn1zBsa9(S`T9gJ!%h;XYV*ZDg-tUz>-xi}1^0P*-`5vb`D~
zB{lhu8Ax|K@~wT&ZS0vlqI`pHTd85~j^7{IE2GfvD0BR>j&bYgKSuU<VZRD-{}CVh
zJkgYM$di%ZrK7?58<x*IFGluluycCdTK$b&O+F939r@h_JNqX3XY9BBHL}0{H{}@n
zOguw3liwaQbev6l8XF_~RXre~AoK0j-=XFFwmI^<9rlYNBYsUjU+#|Vv&Mp>i1@4U
zyR62~)MwF@$nOK%hxLE!CnNjf@k7fo=^vgQ*<XhJgPQ!=H*xEv10wqiy_i>+x6UNP
zS;*j*)3Cex8znXQuEL+An11S~y*08%?fdPSk$wI=@Hb&zi{F}Uui6i<TpanG4f`DU
z{TjbD)4#eu9d~u)_X6yf4i;Cn?{-~e-*6Dp*YuO=??Y~h?3W&Ft9xLdJ0JYUVb__R
zKa2d<tT6o$6=m8T|7~Pn3w!PSB45KSd%LD|OKwH`VT)}#eH7ox@zU9j@d<?UIXJ$D
zOY!K{<7#FROMMr%cuakpKk?+HxEGAaN1On^xSf0tSDtZu#7^kRxJtfFq()$lSP46c
zKl`K&GXjzJ5x57o&%}*Zd`kLomU&+vym}gTW%&0nCQguW^3Ui5`>0rflP_f_u21{~
zfe~k8i%e{HKF{#u^!~cfcsvWo;dl67NB@LXuM*eRy@#NF7B`KF>qf9FOW#i84asZq
zg9j@=K@o`?6HI2G%kV9w6A*T6`)-`+lKJ9npmYmb6C}s0lhG~uv&bzu!DrZNSah6~
zoG3ZldMvz>6E%xb`i3ro9D$=};;KG5u|$w*ShT@PPSU3%dCqd}7W^t7hfDBZYL4=r
zMYtn5O=U4`I)+1XdY!5Lv$(%X?j*q0=b-14I}1>{ht--Pz|rfm0+OE)kkR9E0J{jt
z=@NP@`AGqRK9-<gKw00&talYqu`*lH%PN-KOX2mArLU!J?|OzUeIAA}Ij4?bllMF(
zL2}=Ew!n&cd$QB^7lgT{JjCMll4)0qmBABw>(W^AaCHMSm5w|j%dn+CWF;4+*h*Ws
z;VhRtvhG$`lx9tmOPbjio6%v+Pu+t9|4WCpAogB>Y`P!CtK>TM8j$|Q0;D_1W7yK|
z-vU@~vWGjTN_s4&;PT|tYFBht!=g1-@|mnSH!M2AN<M1_wPDeEEBTy+mEMhQeZFoI
z5<B{vm`KSN1T-`(T5`0N{FC=nl$FshvMDc0nm~`@(7#d7o+#_drvbdx^b@R~ik|Qp
zfOnek_{!?gH*+N3O$WF<=+^7b1bDA*B0x{WqIFBG<Oh;<F952!L#o*afO`H_%9-Ks
z!{Lv`ygnrA_uofx$#~404YXTs(Mn{Ij7c7|{A;JdreczAj(;O-Q5UPnk2TkS6MIS0
ziDeg|OXm5<Vi!qfVonmd&G*-{glw#VOKPFtkIqZ_F_|vQtVWI-6XoT=*5<#3hUFQL
z{yr9_0!_ifiD<5!d@QbL_rD5WL-LPtsf^`s<G4Q)*V|BS+y61=*)#DRk@62@@z2DY
zi5&kg?BnO+iuq^!pK|3rkEa*7tjPIzAcy`pdG`7nrUJbb&))&tWPb{){fe>m`3sot
zwRrt6V4LBO_#V)kaaq~@J|3rItc>R@zru8H8{2IEVF&1)c<$FoH^)Doo&B!yoa<l2
z0e>%E$L7uRe{m2{IWgjNc+M|!{wFI5pHqHztav<&Z%t%5rRT(oM=@n*!g&(DkH(9W
zS;*)_<|s7hiFolrv^3e1sDB04m*eQuJ5T`j<R9Rtz_4p`BFjkp39x1)1Xf4l9=bEa
zweQ2R@d9MaSy$uEsA%B+LLVmOWE}KC>Sjd9mdiON>kyYuTvziWjQZY)Ej4*)EPMwo
z3>z@kPI6I9eF+}Eto|co9)aciZ0r&<DQ*9CqNOpJ2Y6&^vkP3C8Hd+nQZyv-r1)uO
zaut`&sj)19<^Kw$Bu_Ia<sZ%6@iVb3C2Sl^@#ihLRjXRMKe;15g4dz`n;hv6<H0g`
zSpHO2*-B(Nezrf4V;f6k=&1bB^o%D8+^akMEv#iC;j(*X`<ppG?L^PPKy&;@m`gGd
z-hdM4`D?jxq!M{9on`(A&g&5dt@Lqwf#qn>THj+6>Jpg%<(=w3!C6<I$aDjp?Z3lK
zSex>;`gmQ1rE1b$;~&cM(gtn!UtrT447$}%vjo?m+x-{WqKrZJ_}6g#c?nrZKeH6)
z5sQ{iDjLkf1&=V8R3O0xtMqy@pBS+S5&m-S{KZ6x!19k_*Mx~+HP8l2_G1PmS(AA?
z$`w(?<=2z%#}iz<P23)m*@WguH9f|vmJ(XXM^d-jqC|n!ybT4pHe*`2er0kZ;%<ap
zn`h@1E~IE8KQGb0$5C+}?La_Ek6V>1fs;2SWPhq$O7M+D(@_{|dk-8^hZK5HlHG;g
zPb~;IjqDfDYpF%~Wem?|cxhoa!itOQ0IcFxtFR}2+7_W3Mm$+&lzI)e<Be@8ZDs6W
zs=0$vZ9nG8wnf&N{S%Z^H!6@a*_m}?CGYkt;po~o<JfWs4tegemi-`h%=&$e_eg9f
z_4`S<@DsS$c@$Z{zo~KqBI*weSk3mQ5RTh+aVCD0y%cN6J_otgA0kV@{vs{}^)BTi
zCSTe|o=W$tT>&)ibS=GW1H+a+2+8zJ0X8a@Mr7L=nCH%c8CJC|gZ4QKiq|syO@<d`
z=@UMSbiL_wVwqn8`Fo&+>2qTZtgq#-LTl3J#TwW)+t1;c-W+TAJ#5N97yXjHz<AdC
zzsDL%Ul?m(CfaX;NBXi@!{a~=mSScMRtH${s}XLol6NrUD`JV`5SKg*bxvOw^I1yx
zO*FSB{f$^=KLq>=mQniVm~Sd))A5#=Zz}g2qFZDB`^ZE2w_(<#zZvscYQ2>_k?^)y
zLLrxM406e(Z;xf}W}drYp{DOJxmf;xF_-T}d9Fh@rSCLI`7S;0GRW~?#WYKQ-;|f}
zbGQ#l|G?BNi&GzRPX9QTSjh5TN1l_@PsTFiG5h>|Fon}k#nLie{2#HqpEk($U%_~$
zpNXY8AC!L|yYyLu9Dg}Wf6kzce*#N?A(m$Qa#r#jX7ge!aX-tu42K|{i)X&U@~(zQ
zx-p(3u>2Vq>~ub!`xcPx-;1bp!64=H$~PSt<oFp5ebJzdzlynp@f-&w=eHnrx@1ru
zb8QB&YqLek`RuZCJi(}NCN|HN>3Q+Y;b@ru02WpHpm?6Z@^5BO&yUNpvHcrZ_Myh6
z{BN=!4vXj6501Z<jav}Uv+RuTvL*`+%KGPWU>C*nOOYby-%YgGpuoR@<t>fpxuKW+
zFJSGZkBR4316BM^mUo;fy~FRt0!y!n=hwm3?LUNL`h<9%GpWbd9NBfIym9{H?Dv!6
zdCtII|0W#M>kXRV^HpwogFzGh_t?`L4VvVWL!UmypvnGeM5h@v#lM{BGX_odcW_M3
zF=(1!=4?6N^hBS(UY49eGyDej%Y_E@`^VDrBGZGj{6BD|eAd`z`#tpB63=tC%)v;-
z@QX`y88xm$*JdAKtH#VpmRX(4;|ZE8HqIjHAID1^i3%PJTIqY^B|0mn<2cEh-r1_i
z2Jq8(>8mtywf-tH`c~y`cE)}2(%p!wJjnv?kC*-g;M#PpEap%>6fdz`D?dkk`jILa
zjasDtPz7fZJX!@mK*IDNtKePE)+gd6Za<YzvGLEvOWc+#kF!5tsJiXLA$l=hdKJHl
zy|4}y>)>hQ!<bdMij93aURs98%CBHezZNfD0^r)Gu;N{8|LZ2I;?ntzDi}xbrU8m6
z@T|-9OwOtt!`^=@Ub+i$iW&VWGA6CcYNmWUUU~#^71<5mkCzhYA=l=1p?D|)M%}!c
zE%+c_szY4mHrCNflqQM)9rWknQ;|P<{#4|fjwMRd>Hj$QkYvI%|2N3##K`kQtFV+F
z`*9!&i4qO<-3^^}yyn*v(1M1pG{csD0*8i?X|Bd*{X49<hHe2B{UwyuFiLi>4s&Vp
zAW}%pn=JboYz7UZ6XzgGG5)p4R%f+sW}XwnKO(B_F>DO(ss_2-+Y8}Lp(yA0GTy{z
zDssZCY(3wyyys*2*+|#+BV?RiRgc%AR@-G*$=Tygct3P)cC`tY8D3+;pT}IuuFG;3
zS9sZhJ5q<2jBVe*7U5^yGtf(}&GOrxK>7X$QkOP1*xzA1$HT?nArBMU@R$$bvgB|J
zvhhDOK6njo<+kT{WzN6F!p(hMt|#O+>m{U@eu-Iae?k><Hx>TCu{jaWc4M(V%QOD7
zD6lasGRzA77aTf2y~b*63K*3>{~DxgY|WiO-x$WNvAsT^uYLk6qp?GPtv8+x&{@yw
zDg7dbtFcP}o=IS;G>#O2CsoX@u{+VutZfvf@*V11%=%`uFW*(i?zQw=*xvIa1;jM}
zcrV|b;qtMuNYUQO`I+ii^qE|l<Y(m=w)9%ei~R0s8Bu)zqVjvBnMmnQOyK;UVsUgI
z#wb5qEE%0*L7z&q_i_ysG|cbizlOL#Uxzm2_fGq$V_9FkJHQ;D6QrW+QG@(Gl0k=_
z#d7u)(A}_N)oLrhptu)G=+QT#!}BW&a{+oe&}d{AOSq@-h++|X0cHlqgJDbm5Kk=%
zkJjIh5w!K}n*bhjUII}1gfjr1bn0<}aP&`XfTx`nfQ-HX9aDHl+;X}Or<%gE&U9D;
z{Rj#zJn!rWP}cWipDO%G2B4xpk6IO86wsl^!CrVt+Ssj+!f+N|mM3#PdJP7x@QPS^
zHSYlnuL_u~Ph$qJ3Fy-)%-+K50%qtX=;gv20{Zp$F`R`rrC(+>tXi?eD!k==1{ImD
zd4*hfJIzN+TlErV{f=CvT%#vp01JN>uuZ?r-2Nif+3tJjyh3BleE=1{$=@FXP{_yf
z%Ybh6$6*8tO)<@xbDO`4ebN!rI|JSBe~XpvGPb)g2y5UQw&5^8SQS$oC;vcHDp(zB
zlwt5M$Cw0bVlFeY{U#I}eA=L-zX8PtC&b)#*i!yqu}cRh#)7Zm(FyNW-@!1t_Ggg7
z{t$zd-&o|VY{OexD}SxedDwOlXT&xWewb78IupJWS>>;naC%SF-zf&_Uerw{MKP3l
zYw0hZk1e{CX2a};70aw*IZr2+eLsF(`!XUPp2B}w_6;Z#eOl}+{tra8aknjw%*YmU
z7|JP*D>7wUBeE=xH(^e|Vy_AFPppd*O!zBkUU8xcze=A;CR~qQu{ha;??EGrQ%v|;
zOvmC>6E34ui_=WFg?aW#IDI9$eqLdT`Xchv8&H$NGHITrKZRTiM^%^d$;h^Fv{;nR
zaK;@Yz|lE$Tw%F@j6MXdD6B{`vz%_lvMn4dmO$T5x8nqq^>nVFl>#dIHqN+J0y^~n
z-~u>aK(~ICg{~IRqpxOl)(Gg;;B#7qPYal=dG%5_K|r4_(d|S5GxT>*kHT63{d#wn
zvrfP){TAI$5-?kXg<}=g3z(z#V?{Rzn2Q0GN%#fEof6!F>@dC1V~Q*19{g{$+S<9w
zPRo27NbZv#ML<SAVV>S_2Z`>4X_Hd}cal7(yLnW{sfn!Lh|Jtu^0K44b_QWd!)+x$
z0-Y)e;ogae7Va-{WgV6A$;h8eQ`RS3k3~3q1icmnd&Cr%uph@Em>u(HvuuAh7uKAZ
z^B`hv|8p3iV4s-FdMW=<bXKshL5}|;dhQoXvu83sUMO0@{;`0C@tOKT_#H{b=fap+
zfeox2%FY{$oq~BW`yKdS?V!picof#gGOr-6;>!rdGCa*yUg1<aJtixqvWol5rYiVP
z4%c~Ax1Vy#UK2A5_a@Aqxk0NsJj7(?eNWIP18M0LEJ3>fTknN#4mt!V{S-T;Q-Gs=
zloNCb$mk`gcra2xPH#pzLAQWFAC6iFqXd-oB&>#Dw1A3!iiM65(4qI`*3~1RTOY;@
z#tP`shp-0Y1oZ03?9lN7ChPN<rdL3p-hsgmCJ30J|BY!T3h38ovu=|F%+hDEI+F#=
z)(zZCrwEv1wY|Z-rx*9e1yy=?^udf^f3*{MvYI6B;0STE^!-e;NY22vzJoPbEI{d>
z5gaMN(GL+U5s=Z(5iAvu(}!Yg1G8}inmm=@D6y3F0T`^{XaN=dDh4<(8%KwJ9qT4A
z8%MW(hq<i~H=MOu>0{*_)T^)K+2B+;2Tg8Rar7E1I7?2~eU`ltC$8YKU=Oqhw>22^
zw#V5=muJ|*wqLXJt}wg%9Sq;uAn{*hW54fnlC|x^Vt*jvt`%#nT=1YO;9R1QWsm+=
zrntE(3VtUbrt6vF_h~M}xIT@e{g41#AIWAvEFh&X<D_^*(kQ*1>*qfO)ah|_`-8aE
z>m_X5qjI`-^q-mAV*)Z(cp9r5fVR9574mOnQ_HbDf#qB5pr)9^3nSZqfs3`-Amx9H
zs1mEc0-lb4EYr2dG;i25{_i+z+RUk#i<NDat%c6{gE2$Rqb=9ogow(SoFgM+Aq!Pp
z;NL|+Rxa)~`20P1&YYJej|Z6t56Jit{G`wRcRV=_XR4NF^eCTSg|m!ZlPMVP-nd5v
z)z|fCcDP4je*mSALBEB2%hj8se}qbh`^X&4X#DAg749qZAg9m5L<;v45a<KY3*lS=
zWnD%S!~N5fP>qT%-~=BYAfQcumEb@D9eOswyfmM=cIo}#93CWKq<#|p7ao@XK?~mo
zeUn)q)<Q5_|Cn`KkRFd-S+2KWriII;JuCIY%wUCpHTo$GPI#<<wfar;X?UDuy+L1s
znHR1UaI(ILZmR@r)L&yC93S#J^;G==b6YECo=sMzkJI(#SVIqb(Y5~r9b1{eae2i=
zRep`BTG}(_b4I3b{0i=I%O&-zsLRVuKEqZ6v~jI+bDCppYd%pgx5$N|()vJvO7+6L
zwF1y8Afq>7%*t)zmeUtwFv{(cTcGbjeajsJ%6d<XX1P=Pzk({xL3!!pQ0o~@2dnGR
zbNXsjt!ch2ZcCp?aHs%VUx_WL=`aCGFU2xxS|GsD_h5jU7FNf8CW>o1TtH4=kF1-_
z&J}3<0jJfpNGxT27zU_mv4D!c1+{8AQb33P3d>m{pj-cr<t!D@qeo&GnwC}fnj^6#
zH610E$$B(_x#a1y+OA-ImKT4A#<guhmpAX1l^*{Zim8NC>UTxQ=?5%~+%%aXxE11b
z=@Ve<uOmq~U4YUfQGswL0gkTcRNh%YM(=`phBE}@^j3^g_=zmXFVMT<%oOe-v$w3L
z(Cw1~nyuz@uI9{O1)2}v%HSLXyH8yGX)D|y=hF02G_umttnP<FkHgGuX)&jL{asjE
zDn1Ri+<UdO%DtDPKYt!9Z8Bjpx*Kh2F{jU*eggGsF{jT!?!8(%WjiaIcTkTaFWDrL
zmRgGN%Ml)7wH?ahMwRK(_C2(yWrkc9v^6pRPnhr_Sb#0NnDFgb^evy1aQZ9Xz}&9%
zt1Yc)L_OMEnJKHs(yzf%*-b!9|DIr$R4A^K7`4jo0<h5#>>(i4ungOMWzWoJoGFyf
z-wey_G~d3It@O7s@XISFt2f$EP=Q^yQKp2YL6@{DrwFk1?ikX_sRERqg?U&xO@O1n
zgBe=+jDU=O8;iAax`3Qs$l0<<K%jq)y}5FRfU^D}b30Q&MNh{NRn8L7p(m#S&KA(E
z|H>MiBcMnB5<OKpS3s}6g5{hiV6r|PGpw>%K%ZX8LeCd4LqCZPpmKqLetkW`g#u>j
zUZ%N7z---*0jYdez#RQ^Owr240_N%m*wRY`%+q8ER4x@TU!TS_TLdiBUuE4c6R=o+
z0YhE6T);A`?M9Bn=ZhT2mUMe`;$aALmn8GHGKRf!wbz0u*WQ6)NFT}UTHDojMCp;J
zc57#zVM{-TcDHs_hxmBZr*)(mV!a9G)@}hx?@!C9>Y4Uh^nB}RbEegNeBC<U<tZ?y
zuOaA_?I6%cV;EW|xObqOGAh!E-%-4AW5j4g+>GD!FVMD3>vR?CKxL+4$86nM8fxiZ
zvYIml*m^ydZ0jckD7`nqE&?2@Z4>==E#8gX?59|>-OFrRn~yfP9^$8waoe2;w~aQ8
z7?36{r@f?(hM@tv;Z}Q7_4f2w^hJAf{W=(Ieg1lY7O^OEmS=o)f@fm6UAYheS+1vB
zZ6R9U-kv{&wy)v9|6&W!+6e${|AE%FcZFBdgAaLrKIqZ*RV<(Ok(oQ_w;bKn(eCpC
zrR|GYPaPLG@^O=WDkgJhlU&rNU%DLIRA-wyzY{(8U35ZchtDv24mo#rW-bA+^#@4a
z*_B~w7)Dym?X#ob#zgAumREEceLM!MbCjgX>8AYwM$6->K>G=RF=8p}9Zb`c;q_2O
zUxMm&ns<C1XyJRPxof||`j5obPUqAjtJ8Km#-y{)Tu5GEBRoBvjauTFJ2vL7qf}!T
zs@#b|={nlxov(Rj&~=P9Pr;743zp^fc8rbEZ{7;9qWV;hkI1`@HBaUACgj|8Ts_m|
zthPt79dvD!r;F+iRH6rE;9m126xnr3Q!7y0Uzqwzaj8#@EZ41LHFm{zHL}^`Lo!Pr
zik=(UA|S5oz6?+i0PfZ2U?16<n1wWBzK$`89T|)9hAx?)vh<jn7_}^xXVJ+-<qn8R
z^`S<wvtlV+whO~8wsq{m=*!sgu@pt9FG7Z~t$#s&<K~*^fPEa_vS$2tnEPSwU17ye
zj=5K&nD~~pmNj7x>KD5yHMb62RMb1Rb(fJKJA9Ej-JE3@sVBaLbs4)QJ4@ioi94kL
zZ<QNUX5!jxwrjJ&lb*$J#;$gI5XK8_brUn%`ZXk+{5n%zJ)T}jHCgh!dViW&#7>yF
zu`dSS08AzpKVYkgXJLWHz9i?JWa29H2#R10gvs!I1Y}jX)};3_ZDZ$4kq(NyN{ZCo
zC{lfomPrhwNYknd1J*W~xD+{>GA^o?agiy5jh^y7bWm(g>RlV%f~gzZdJprHI?tJC
z`eE)=oW5e9exb$jEsH1aO27T8aN$&R^jzUv4V1jU$CBe)4xaeXxo|zKk$JN1$8ii6
zR-IQ)E2k{sTW*J$*({a$72mSl8jnYBYChV>=+DHt55~7FW8W{WKo4XoHilS#lF=Jb
z@lE)RZEYNdic5k0ZKlAr(^>KUDW>9U#^Z0EWNt9i-G#mv-?9NyqnizynhIcEELrW0
ztV}2NRhx2xHHF{6iH%F$nlR!Qv8`)ZpiH1~?Pdb4oVs=uO6(m-v{NU}X0guHCM4>W
ztgQpvvCmkf_g5*H)3EwU!Hm>hzB2-i{g{IJF$ELz<zosaI^kmqCU%~WDVXYG3a0fj
z1rz(h#}rIl2mb$tf>}$uB(-u6T(E+6$+x0HtsK$Z!6>0tj;K;ANvBj*Iwd)nuDub*
zmUD10x1>U+tgE3@)>Y}0Ti_ye%DNglWnGm{NlxZR&?)O`=#=%llu55JbjtdEMJA*?
zj;`Oefnh_Zte+`>bjnBIEp$qKV1`u{I;CDvBp*lUlzLH?K88-|fKG`&LpO9v2Xso-
z*U%}QA#_Rybjq*7X6Td-=#=y{bV>(wN@il{ln&^WHvoZ7Nf!p?egh<L;_pScN~d%{
zr<{g3p;J1bQ?e98r*uH4Ea6^8=#&oVl%{f|Q#wQFln&^WKSdsfPU(P7$x^FyN(Xex
z-vSysr2{(Uh0K$5N@ob2(iuXhbcWC=ogs8e2Xso7XXum;=#;Ekl}_n^PT7qT44u*e
zo$`H_M>?f5gih%Up;J1bQ*u5SI;8_TC6S?1I-pY$89Jo{IwjjzrBgbfQ(ndLgih&z
zPI<C}@<^w2K&K=ybV>(w%F}@iozelFlE~009ndL>44u*eos!7VDIL%$IVgrs>3~j2
zL^>t^Xt9P)>3~kjC_|@oK&KpqyL_QjI-pY$7&@ghgih&zPDz`gQ#zninwFDJ>3~kj
z(hQx_0iBY_&?z0zDaRw7p;J1bQxX|Er2{(U6d*&VbU>%v8OYEnogs8e2Xx9^VKa0}
z2Xsn~tf5mnpi{CuL#K2=r{p*rI;8_TC6S?1I-pY$89Jo{Iwg^zQ#zni5*a$B13D#<
zp;J1bQxX|Er2{%8k)cyMpi{CZ44u-sz#v1XbU>%1&Cn?w&?(u2hEC~#PDz`gQ#zni
za<-68`2b?U@{m#EI&^LJk!y272%XXaoswpuQ#zniG9RH+I-pb1Sux#b5Rf%prBgbf
zQyxzvSL@Z0u}Y_OK&QMAaYCnbK&SjRfNRrL=#&oVlx(!nDIL%$1&~hZfKDlZbV>(w
zN&%!(I-pYuAf3_yos!#+&?z0zDY-2RozelFQrt+VbU>%%!wJP+*cG?YL+F$a=#;&D
zQcOCf13Kjb0N37=6(^n20iBXjLZ@^<rxZXsr2{%8f#QLGRw6x9rBgbfQ*Ne_8GSo4
zR_T-u=#<wXPUw^l=#;+#aBXfEiU$(jqi*K*?SM}CJNlDO>3~l8q4=MJ-cdY|;3xi7
zI;8_TWfE~hr*uH4l;(dCIq~l)#S?VO@$?{_(gB^4hWhSwXWb<T2%R$Bm1fw|PvDRq
zndW*hbjozM07IutkCGj#!#tM#GEzwXRXSyQbYg!*DaPL!*{XEP^u+K+L<ya;p@vTB
z*3c>48aidBmQLx_&?&tdI;B@br}S#*l-{~5XR**JGqrTeY{uOOXM`F$WwwS+nXREy
zW^3q_*%~@!wuVmW*U%~b8am~7QH1nMl}_p3RQMXA44pDptS9eP=#;sz$S^DPWBhi4
zPMK>8gcf`LHQ4fUtvSB^7dmCGz5W^c3Y{|7A;8cnbG3BJTrHh4H-t`^>rT9e91NYZ
zu|u8CtVySAtff;n*3u~(hteq<XR4_<Ez6Zj<E$LRhECa7OQ&qCrBgQ6(kUBj>6DGN
zbjrrP{5$dR*3c;%_fG#2)iQL-##%aMV=bMsv6fERxS*KFGBtF{#uWuJY)PkNBMqH0
z|A=A{LZ{6C!DHAw1<yZPe-$2y8#-nFG3UDghEAD(()m4rp;P9c76zrEQ|6x$H$$h)
zKkFp%G|tc|^Upga07IwD*U~BTwRFn-OVUO|r_9&VDf6$0#n379uL>}9%KU2r44pFn
zx&T9`%)cSP&?)n^bjti&-d=c0Xy}yrx6`Z99z&<h*U~BTwRFmSEuAtCI_1BiL55D5
z2c5DP$j~YCL+F%w&?!kgFm%d%4V`iZCW@g`7C@)uI0>Dy06L`%gU~4pL+F%+A#}>Z
z5ISW6bjrRa3=+nd?<8G&FTS@Sow9Lbk+V|hl#MlX%ElTxWn&GUvayy<83aO$6gp*4
zOQ#G<^155-ltDQ!1WJ@jg1&1XfurK#X8f0BU!_w9oy9L9O6Zh94V^L=S7b_|QwHNr
zm~_gZ*MwuZA_^v$FzJ-RL=z^RGMHq-q*DfyP52&6<Y0;klTH~-HDS^zgJ~vAI%Uu&
zVMC|PFHtLypU^4u%cOaRPMNQzQ|6Bri=k8Ij}c(#l=<ZX44pE+BF)SUoicx{SPY#q
zf1ChAr_8SuVCa<jRRRp1GJm`PL#NEI7GUU<`85IzoihJv0ftVQKS6+@Q|3<;VCa<j
zwE_&CGQUoMp;P8h5@6_*`Sk(}oie{czz{lR{*>SpGz-%UD@bwWT!jBsI%WQ}%o#xP
zesVhkGV)bAC3ldB>PVY#kGPZMIo*fQDZd|?g@P$Ns%sBWFuASd`PT`O5H%tDvW5H0
z5IQCQC`iiS(v<ZH*Qp2_I%NTLN-klcQx=BMDGQ)eei<f1rz{MiQx=BMDGNjBlm*Z!
zSr{2wt@sr>Wgc`&Hc;r4`G`)*?0=5`)eaImWgc|OI}j&y%KW-mhNn59Q|4>wl=)gZ
zWgc`&aU-2FAJHj=Hd1U>o4_6v+DNgMHd3tkG#J`Qu~p77hBi`cOSd5(LmMf!%itT@
zNU=kJp^X$f)9n5#ZRAqqCCvbBq=4`>5w6lkilfSO5!y(xhBi{Hp^X%4Xd}fcZA3Vs
zg;w=yh(?eTT4<9x7*1%x)Xs213#N946I$pLH^T`nbO|t=(85Roh7(%o7GOA`g;4?w
zC$unHfZ>D|#t1N+&_a&@!wD^n6<|1_g>eE5C$unLfZ>D|dIcCxXkmf?!wD@+6woi6
z(844Eh7($tEWmI=3sVGCIiZE=#YfSbh7(%YU)={DjBr8=M~Iu@gcfQ!p@mvbXrY!9
zTBzlO7HT=6Ad~Z~WjLWAlkbY{)Nn#UCMPhQP>{*#W;mfBlM@(DD9Ge=Gn`P6$@xy%
za6${UoY2Bqa?MfYgcdFf9zuIu`!5)C;e-}0&#;BU2`$ucLJM~`NIW^Ah41@Z0>TL`
z{6NCO2`xORw&NYNa6${UoX|ooC$#W;naqY0T6jo+;e-|*7GOA`g<4K%p_UU`_=C6^
zPH5p#x#lpO(86N^B2H)loKTH3v~WTT;DizwPAL8a!{ODP;e-~z2_-U|&;mH2o$xfA
z(83T-XrYD^%C^dWN9R1(aYPyM5Fwn<0yv>8RB@M@jexA%Dkrp1%L!e^Jb1uh9E+c3
zazcgDSOBH*RK$QWj-yZ-3!pSI$}qjce)TSZFulTBrdL?Y^a^KHyPZt0aQAAr*Awhv
zx?PxF;hvcy+GUtt;ZUYmc(R&LmLi#6;l}FhC(|oDMSx*?g{KNIOt0`X0fy-nenx;{
zdWEM8Fifv-lK{i?3eON=m|o$T0u0kDJWGIKdWB~TFifxT907*u6`m`=FulU_1Q@1Q
zxLJT<dWGi;FifxT0s)5U6<#R7FulTy1Q@1Q_*nsl=@niqz%aeSO9U9ES9qxa!}JQb
z2rx{q@G=30=@nispvv?LKVRfHwyZ@To9V<5#{Ck+3ezjR+B+9fuDuLL!}Kb(E4P9%
zA=9hWnP=EAy-HoxAtuwSG|~*Q-UM^0TYzDDl}1(951C%2(PsS!)2lSz<-|5juTm}3
zt2Du_pd2#2E<#1R4@ahq7=?&N{2HcLX}VetAWW~4p=}zbSIN*e4b!Xi3F!jE^eXKl
zpvv?r?ON<Y2Ez0z?OtZngy~f}#9zxWnO@~urdLx*Jph9+y_#y7UQNyQk1{7=dNmDU
zdNDp)woEKnQg0$4E49k>YHH6vMO#BFa>swMk?D06Vuk6|)D`}f9wa684tfaFt7&AW
zf~dCT7M69p&y7ZyUd<Ob@=jQoUM;muua-9TIuZ!etEIzd*f70XIx~L;FifwOTBcV^
zEz_%|mg&_pO41mnS4%C^t7VK>4AZNnmg&_p$n;u_@?3i!j>7b6nObCZgz42%!}MyY
zWqMVPQm3||%4B*~j<$JGZtig_wM?(da(gY#UWVyasbzXqYMEY@Axy7ImFZPM{+Hu_
zmFZPErD-#eFuf{<=_QZe?n0z_^ft{JeJJ+e*jRld;*yD;UxK`~Z6CxeHdGvZerOHq
z8QV(oV$Wq_5z!QIe|oMKSmINg_?DGD&j}o5;PSEiGUKIneEJvPvfdgulXy~!oS1o%
zWzSs)F(%@9nFLb?5?DV3;|PB&iWOL;)jWgKF=;i?N0IpV;8j{pg3=p_Q9&Pa{-3Fw
zCHNjGF}83N{A^a^BW2H$A0>O164Kj<ZAheW7P79x|2nJw3(O=YQa<%JAgmW*>#uvV
zOmjjm-|N#G8K!Dla*7GxhkB-Z8qi@@f~sk$6C~_VHEje`)6Re)ZKtkJw8pTusG64A
z?!1Y}2CAl|zV0*Ld;w_!LN5IiRz{_+tvd+Vdlqvnb=?S-Yk9Zhkh&rHA%1KtLDjU>
zjR_`8P&F-eOX-)eWbFi1(^S65uJJ`RO^sK-V{VlDQ4@TItsGR-)I`bI_NbbsCTbR=
zJgTOti8%tto5?vmu|$x`K{ZWH()czIZb?%1Dfm^Zad-*;rRFH_S%f>(G{tS%qiUL(
zUT11g)ikw}0NbN#n%Y@_@~E1oW(aURs-~$=2*`L;O;fuF$ay97nEIrEz@uuK>K9P<
zsG6pB6;QDnjcS_OOMQ!V;2-Fzz3UmaJgTOtIdue^@>ESz`_{7sRxH0KJ8geKR87MN
zqpTmpP1@CBH5%14b+}4l3{6KKk!9HOsG6o0rPxZ_qiUKuvd)1;c~X-l&FqWK=rHD|
zNNMK(YQ`zM4WQtQYMNT7_6G8(nx;<j7`8mBrm6KNdt}0e;g7`>T&|v0Uqol+pqi$h
z$%=Chs%h$3GpISJrm5#7tURiwspsoHiNuaa)im{jfQB4Z)6}0ld>F>ccvMYOFG`xg
zqiULZqn<rc_9mYO@K#eJ7IDR+YMOedX%;|-N7Xd-ZhARDw@1}9^<LeX06jUXrl}7k
z>s|m<bB9#34*>Q2tCTY%*oVUp)wIn>)E~T$;uKWVt^(SvNYyk2)ihRbRzTG>sEkUw
zIRRDE6jamx6OEc1P&Ez8*;$@8=LJ+v!*>dtBaz$ufU0Q<s%czO3xj@i9@PG1x-7$$
z9+ERrNe*mn$wk>R<<Z~w!c;HkVxyX-pqfT|K-Dw_)ijyi0aeo!RMXyu$quNR0F)zA
z0aeq0nu(l%s%Z+UX-t<1sG6prn)Wufvs|zn{h^vhTW>(sH1$$Ee+kg!fU0Q<s%f<K
z1q+xCs%b6;X+}WRGzHZ(uI&DRs%Z+UY4n^GRG1E`X|&A_sG6prn%0PPbAsa$r=Xff
z&$$6r(-c(G*t~fGRnstANBjyko8QFwub`U7DL*^bMAb9})ih4&IkBdrm=daKUHE-8
z-bB?j1=X}~BcmtcO%Eb>1=X~PutGI0W#52^l+DR2y+0jpHN7v8HG&WK=Xyq@>=KUQ
zbHJQwHSUax25T?+FexYCpbt{x0}y7L<-C%$hnMJFOWPxiv7u6$f>PT4Xk@b}r70+-
zy$X*&woWLe5#Yrr8wjN|7G(!iN>flulhH<5Y<9|K#?7LXrl6EI3G*Z1D=h`3Gy*H2
zQksHN8c`~sQksHN+8!`LDUCn7!BDMg%l!&UY4b4@0hQ7el+w<C2OdMR%1}z<nAyQR
zjwh7T=%|9x^n_B{ONi|VsFbFll*T&G4ycr-pp<qZ(42ruX$nede?czu0xG3ppUZQ(
zEDNZVrl6EYv@%%1bWlnoS{qO)O+hJbIm$aVc!DzxN@*K_&JL)Qrl6F@^0o$4N>flu
zW4dbsDy1nXr4elpsFbFllty%GkY))`N+Y^Gpi-KGQX0`c0hQ7el+u_dl+rklShRE!
zl+uV<xL~l9i8n{MV70uipp<qCA_6L<DJZ28;4e|xHBd^s8wjU3Zlw%LHc(1C13p{@
zRa|*pK`D(3wv}6gf>Ihss+CG<3QB1#(Ufgt!b_sSYU4tc8HuUE_>}!S__uMzM6<U?
zqDwd`P9C0mC3W0tr#za1JQ_EmcFLnE$fNy`<NHZ~W8jG^n1%S!lr*bv?qHOrq*;AS
zBYP`B88!U5F{gZjGHQB3um{7GQPYd^Y-56a9=%kqsr;XY*q)re%%72wcN4Z+$DF$@
z@0<X@oV#srA>15u?pEGe1m@h0cdE?6*(H7(GDuL)EWJy)0W-uGIkR-XnhN0Y&q33>
zHZW{?lru}u6kwx+;)qOq4W%_qYv$i+`V8ORaDZ~K`*>eLmJRco=wx|R>}WWsi93bz
z-aG~1;HCgxj&~ByNDYTH%>u}H6VZ-_`At;U$azz6N^3Y&Hmkt<6fK7}ZH1-mEu>{Z
zQv;?&#oKr)z`~|SVCnEi9R_fC6VDRe9{-Y};fSV<s6dZ*C!V4;EE3S`?M|?`=>lXh
z+1q#kz>!Um(6?^05*MRa8u|(|*tUHb-Zkt%)+u{5jv@c<kN-<@U~^y*U;c4(!*1?e
z@jaNnESD`2Un?=0neFa=S{(RSM&j_f$U!DqNgxv<+pA&fNF<nSw!2-D-5e$3Y01<<
zLJtBW#RKBR8IiJ?Nn#Zf@8v!#@h{;hWwPH)Vmke8!HIuoqJ3QcjZw<3;3$cB&KOK&
zB^ue@ecgWX+9UE}Ck}d*<ZR7Cti&|>&vmJllCn>V{5b-~e;&OQ>;47A$+{YWM+w;K
zAUwp~GeH@@%)WBxkr;`#WcHJA{WsyCpp0K;f3sv7kV)pifY;aduV5U?J4>8{$&ook
z_Ge8oKJUN`3)d9m^A;2rGfXi)Z&8+$x0&38-YnQ-XJGjS6ywW+J;qY4fMR@Eu*cX?
zJILXf1$*qru&IDzd|9x^=vg07iz^HE7&FlU#rU#dk8J@0dyFm&R<{$uUx{!F$y;y-
zd#o984#oJgV2`nsW)b7df;|?;LJcU!mj!#wRF3SiEZAeFaunmsf<1OK@=(ET=+P|L
zV=T4aawx`^1$*pHz-AHS%Yr?20`nw$EDQD+bFl)7@nyjtGkH>sFAMe<kqTUTf;~p$
z1g|2iEZAc#FB4FVFAMe<YnHW~=P`a+u*Y1K&@5tnS+K{RVtHhbWx*aZ<xzes3-*{P
z?-e*?!5-tNs(@mAS+K{5oPc6{S+K{5G6BW-vS5#~eL2ga7+)6bvC~<eu*b4sk1fW?
z24s(A!5$;90*div!5%vrzjkmhqOxF*5vhP;d|9x^h@608d|9x^h%&({<^uK@2PGG@
z;Ftw_j3|%!{u+u++0ri*<I93Q#;9fy<I93QmO<qMit%N^9wV><it%N^9y2Yc7+)6b
zG1^o>k+&?^W2WU~k7dCgV`-UyVtiS!$B424#rU#dkL8gr7f_5Z3-%aM5KxRS3-(wU
zs2os?4=TI)HlRw-$@0J+W9c0M#rU#dk9EV=9Z-xf3-%aCwkP0ww=CFWEN@&uF}^I=
zV;tw+fMR@Eu*Zld1Qg@Tf;~nwF`yV<7VI&iNdd+9vS5!9O%5o=mj!!_XbN;9fWRIj
zni}ljn1DS-G%cVQUl!~!_C#MmF}^I=V?;9oit%N^9wX`xj-@BqW9-3M0mb;TV2{x@
zJD?a}7VI(3mN^)yR}q`CPeu(>HrHXwW*?<&E(nKWd|9x^Xl|z%AFi@X%%`1Vd|9x^
z=&YFTC<J6p?`*Zp1_1WhK{Rr;o*5Z^tDRzeS+K`WKwLY;__AP+Z3Vzt7Ow4!IaFYe
zvC-{6Xa9peCV=d*EZAcL&LRMNOaR$qS+K_hkUf?KdyLypJH`02V2@qT+#Y9tf;}c~
zWRGRR9{U3<ioMW{k?%YME)e5u=NtPh*kc7mwv#;uk?qn<fRsIs6(@Tv3-%bJ+9}4D
z1$#^Y*<)F-#|RV;q@+mC<g9jz@nyjtTTLS~+8P;?Ry)P`vS5#0gt&Iu4Zt4z4nWH0
zcA<E<Kk`R6uVxFt9=nVFWRGRR9-{_I%3g_1Ry=$V`J?A4#+L<q>}C3sb(95rOq%}#
zG`|arP^$T%Ri8(=o$RqJ*kd$gy8X_&lMwJI#^-mX8MeG9aPUW_xgMH5it+i~0xBNG
z`210_LxDYZ1N_cK3dz68N>Gf?AD!q!lw$l>BU_!NH#5(P;bn+Q?1e+FP}~Di2@3G#
zDsrl8rvP6g7-Kx|X$tV=SJj`5-q4q!Y5C(#m;!wH)h0}OP=1XGQ-CkOF3XwQP656~
zFvfV|))e3?WZZ6STPd68Vf_TkFMJ^9WK99S!Vcp(9%&0Z<hhh4Kd-Q(EIHhQYziM5
z9}4gV+w=P{XA1BIUze+2xnsW!MMz)7EKLEv;HJWvi1JT_vt2CK-vQu}AzloN46{OC
z!fzKCW5uR`QU3YYpg)SOxgwh8QGl=5UVk@zJqqv@I|SGs1^9}c^{k%qD8N_j5`f2B
z7`5U^0U0a7?26rqUodMC;0rqx^?^Jx#=@>TcCY18fG->=Am&kkFYL~6$=H@J0(_8G
z@v!3LS~{GSW7zU2z=!u>a$o3CfDiA%m`HgP;0yN@i{tg7G`t6+CF4<mFZ@)Ry_d^T
z9xvR>|2%uqqX1vHcbZZSWsd@U;T)e6q~cM4585oupu?j8AGBErx^ooZ3l|j0rs(k~
zz!$D4{1-qk`jw3wDFS?@M-+?jD8N_xgU7JBoG(3Ee`1J6dKBO*J?2~npgaojm7a8X
z4e59k;43}t+zXKLD8N^GM%;2<T@2t^=LuK>j{<z9=bb+TlsyXYmHs3HQ1K|hS9(!E
zherXv(o53DZci?(UzUfwJsvMAORtEf*P{Sm=~V%fJqqxZUK7ygQGl=Xx_}wp67+KE
z4FUZg1^7yDO25p?QGl=Xme+};HQS>AU+L}iUZ~qvj{<z9cjQ{+8jk{er9TVU=23vJ
z^cShl_J9I>B{0U;;*$5KfC79aFvc{{tpNr2N??p}=G+!gfUg9`82{${_J9I>B{0Tl
zy9<L*Kvy)20ACr5F^*F}0lqRAV=@c@1^CKfj4^>7P=K!t#u!mDz+VAdWiZAr1xf`J
z;46bMc6T!d30ZGNW+}T99iJd$EZkV+tkiLIWO%L5`JpMm7j83Q3h;&3nJ@+T!s{jM
zivV9!pjKgM<Q}gnlzD4;6yR$rrP(k$w_=&qRL;|hWuJ)Ols%n@hx74YmVE=tM4vWw
z7EeZ$rT`z_U2SAtD8Sb=uE>;{PsW<Yn=lz;O}!>e##qw?6DDJ<X`%^}G1fH6gvl6d
znry=NAmgSfCQQay(^L~CW2|YK36n9_)F)wI1o%oz)GSN|Zv&_7GHIUWQGl;>RCOtz
zjBHCsi$!@9;42*?!0{-+S6VJ0;~j!llvbpfS<a&XU+Gw}1Re$WO2-K(dlcX+trSr4
zD8N@*C7{Ej0AJ~N0o~rKEOfPi9*+Wir8NS2JqqxZJ}qFfM*+Ul2?F{&3h<Rq6fnd4
z4mzo{RzSbEJIh%oV3tP#zS2noW_uLiE3FqW$D;sWX@h{d7*I~T1O@m?rvwM1S(si}
zL5eHq82raci~@Y6(=vP{AtygRj*yX0m|INlAkniH+T^~IJ4uPt-8}W>)I`=-MP}|T
zCD~C^_IIO5ZYw2TKTATm-;ank?k_cWq$&Hk$e&BI!~<MC{4|RIUm1)sF5!Rzd}T1k
zj$+vX1^CKfjBSL;4nBtgDuXe`dZ~Z{d}T1kh@5}|d}T1k*fW`c0(@mK##jzt&wPN=
zyD7j|0%ME~Y^MNU35+qxi`j3(|7r)dQ-H4o#@H2zYo`ET35+qG=GtH3R03mcBMNP&
z0AFcS6;Ob$1jd-Skug>RV~n}`LbfWmD!U1jnPe--M{%uM9tHTy?E-9%0(|8T0m`EQ
zALOIx=6Dp~D|ZRVcog6(j}(yeD8N_l77%z8;46<3Q1&KaHIzpSsCZAY&@lo!JPPoY
zdjxcQJol8x3h40;VGYI!==CVTR~|25vPS{Fa<70sj{<z<2?Az#6yPgQ6wvQcfUi7B
zz$}jfeC5dkW_uLiD^C$H$I=wwD^D-JiSG4xM<2{6@2{R@?_7iSmX8oO%cB5ad6Arf
zZI1$c<;4P&M*+U_kpdi#0(|8q0x}*iKFdo5<h(=C$7Qo|1Re$W%14Q%>`{QPe6)ay
zM*+UF**H2p3h<T9#?kFjfUmql+;G-rrH_?!P_K6#&jzQ;IcRc@0(|AO<aFI<B`CmG
zzAShJ?Mc}g95n^_%9m%@Lj7xY-W6tdrvP91&IXAm*{b|~pR-4kaaI0-gqub2t_*h5
zWjLDzRJ<#L-9%soRJ<#L-NY*qJD}oS8SEw^6;Sc640h8^@N@zy-j%^_;vHrNvVA~c
zH*u|Sb&Q9PtbaO}cA&PhbYZy)5$$JkP{3|tp^7Vt;#;y*a7j<ayE52K%uDikiFxpV
z<Zs}|7sb2gnQB@E1I$O9&9m}i_co!O&AT@q(T3`K^_Zj0dlXgxD36MF&3nt`lH*bF
zu6ZAs6d8|-cg_1s$LBmM-Zk$hAn>So*F0B1*`wlJ^ZseR<Ewa7ylXx{K%4hff&&F~
zczlxDJTH9%+`7E|aBMzEz)0^&^k4H~`QNu<<M60>*L+wD!EBF;cg+jZThZX<9u@DJ
zmrHwAdJi*$6#~|HRJ?0GR=`@1ig(S&N!A-YD&94(6mYUf#k=NJ0ycV7ylXx_<b~m>
z-V4lat!(w1tad8il|c`iRbj_IijHlcz;OXRj8W}Wyla8t9d}}16z?h}^*k)n<&`F%
zVJk<)yGnDKV{Cg0V^?XBD>3C!@vc&-UJ19txzZ{i<5BUh(k5;>kBWDdcF8U9?m>Mk
z9RkW874IsY(*G4yaT&7kMe(lnVD$s^oJYmG*7>rUERTwJt%nM*Ju2R{9wtC}RJ?0l
zAi(kN!2q=`td9Lm6xVvVfSgCgyH>MR1RfRdS{I3>>{0Qqb+LeoN5#9=BL#GLRJ?0l
zBB0x&;$7=f0X-fS?^>5t7dI8}T8|RTWRHq>t>zk|&(c@0KFf=*pmCatcWwJ+rN>3_
zu6auRp_snj0~SVZn#>T~d!RPWeFAKcig(S^1t^b-cg;Hqa6BsBHSa7S<MDxa^9%tw
zkBWEApU86j0*{J!&AZ6#EqheFYyPBwW@`i$?@~4^FoKGA7y$%FQSq*MgPfHTqj8PU
zK5Nu@i1)wE^KAQx>S+LZebBzHb@25;`$=uQSyCP)XxrDf(#!F-5Nv3ZO~m^zf|FZ$
zBFuRm%z0xg&!d5rc$}t#{MV2uWxs=C_#=4P?bsN2K;$Wi)cmx3`)8%p(L6!NR@Tjf
zHJP{ux<8}a7_+Jxvkft0{)%j4XT*{$a$bnHs2KFv)*Z;PXDhObof&H*h;NxQ_UL6+
z?Ce-uqJwbRxS!B`POOd3?BiSJja$x~&W%as<6GvAn@;<Ak$vsBt6BEu$i8Om@enPF
z(8_Voe+SkJBD{S30bRKDKz)#@6}vp<^=?E&e9Qda<K=f@?^5|)%!adpDVy(X#@xqB
z^vCMhH@5|rx<;CF5USksJ7XHnmv0~;nG$El(sYG-(YUeb=h$wsG;;%I$r{6p^;q8I
zwW$CtD#`0B19|0RqlV-a4CeJd+g=>ZYr;xK+#%KaS)-+Hm#jv2;xVE${LZKr6D8$c
zQ6(lG!F1oRr)OfzU8hgnpZEv98H1IR&O;~kqiUcgSh2sRd%s)loEuH&^nO`>m-SvD
zzsoWCxGV33+~ic#VoiR68LpEVF*#?+mt|vHH?d+;ll9e_teyA_9XHg|6yI{p6sRbj
zECdI3mE?M9l&iw?Pde`=lWIm51ORESjY>={a~AB@$|;MKQ_1U%%?fG4m`wc^)9qe`
z%cmW)-iqx}Ma!mkaDevA^HouNi#730`tDV4hHEV*0MF5r52jPMluYs$t+B0~Ow;%<
zAl9Ada$?Cc9lE0tG{Z1D8V0NH0puP(c^a2Rg1tN)vp>FZ3OjzMGmnIA<7~dT+KF%F
z;-~b;`>UOQi^jzlnnaS|@Vz7f-)_c_=x1g-@rEhBXg1%I?Zo$c@x>C4T?JiYTf8o)
zlGrXoO-W+gRI=1o^x);#-9Ofb`uOvlaZIC+wV}`nA8SM5!s%meC|t^Y{CUn49#AdA
zngHpn2S5D!p<qmqk3Y|e&iMHAoUh@$u^MYdrp5mSpXdBnw4uoTS2dsAjC7*-&egTg
z#j%Bdh42q_qNvL8cXgtu+cA`{BcI*;8=a^(;5DEV#cyy%I#CP{=tL1vCyMV3Bb_K#
zHPVSXg<&#%pc6%(L7k}Uky1XpNu4Ox_wVUMQ8Z>yCyJhfI#JAIP$%j;Kw$dNg~4dI
zA-*@lH9AqdA#Ok?ilq$dM3MV6pc7>(_t8304<e62ohX)CqZ36k=%7v%pLYB&>qN1<
zL7gbptVSnlGD;ZKi5h{&CjXR9l<2s~XE&)6MKq`rMKq`r#rD<cL~Ubv13FREj2Y00
zA{f+(x)5kkCyHoLCyHoLCyHoLCyIkIs1rp*ov0jq{zfN?QG+^B)MOdZi6Z!WI#IL@
z>O`5AM><g~ZBQqQXiz7L>Q93@QAC3}QB;2#)QJ+sANlO&aGfZU{s(oUII@E}Q7msz
zCyL`ds1rprs1rprs1rprs1rprs1rprs1rprs1rprs1wDW7}SX(8q|p*8q|qm4-V=?
z(Ke_P#o0ogDC)zx_LpSTxDN4s2BdOrE{Fl0D4GX!qL|NsP86LL(_Mgotmzt^sEsso
zwSFx!*62iCiMRoss2>8jHeCmFqS)vGohSih`cNlI0GU42i4s7j4|SphL^@I2eg<@+
zxGfLpM2TCZ6Ll{vioLK8p7ssXi6R|tKqu-L0N3VUOAP2lF={|3N<gF&MWA@thX2wt
zIrG^~>O@^ZBQyG8WUSGN`gg<)=tTViz_qzuC?4L3{L#(a%Bd6eB>f|uD2+#>t}R@8
z9$EpV@EV;c4{-xJQPTXcBd5J1Pv}JLOpiz>iU!e%x*CB<CyHS(VQ_#>6xYLmP87j_
zP88=#RVV63q>!2n>O>umD8=}nMz%qnsP7``|23T`&f<^MiQ?Y@{2$hdqUMwI%b-rw
zw-A*+5q)bzC+bCjNGFP6R_Isw?KC=3j543ygiaI{a3Y<k*XbMSL=pVAb)w#9*24OM
zPSl0W`oF6aH4~52BAqCP|M%%c{S;R%13FPJVXpjlb)u*jFrX9F4M3eJHgZ5GibX^^
zQ4A00L~Y}X8u{!dbfSLDOG5eVCUl~n0vOPV;v1s@ohZ5u=tOyVYB``2#Sb|A6FO0B
z<45a6(K4VDMKGWfMKGWfMKGWfMexx&Q3vCR;ebvQg>U}bI#Ji5L4!I`Gl2ekI#IJR
zQ3iFQI8FmPQ8Enwf=<*dyyc}%)B_ks*FG4d9O*=HR{qO6Q51IihdNPoV%gj93vCG^
z9=?bFvg`+SqHaLcN9jZ{Wuy}&;i^uQgsVDH60Yh*Nw}&LCE==0l!WiWM21e3gsVDH
z60Yh*Ntmo3=tMC*pcAzYQ{jJ`P82iyzfdRYJTwc_3oA%*<xo#<P$%lMK%#DN8v-)&
zRh=kq4UtY1ZK7$yog~lcK13(#=aHFvOI~(V*M1?2<hGKhyn!S{P54H+h5O48ou~pL
zqzo?2JP&Z?-^>r{L~#lK9i6BfVft5eqF4@fqQ>HPKqra~9I6w=?D=Y?+Cc+4Q9nW4
zfKC)obN_@+l(>DQPSizs>++F0Q8WzbM6q@QI#Il=`zLgw*!@+VD8B!cW<V#Z9pRfI
zJg5^zmw#C&ikd+m>qOxuM!p>iov0Vkn*%yg)K&WbwoVkM-=I#^(`b)tr*MpPqS(TZ
z(utDzs!kM_K%^7JaHJD;8{YW-W1T2Y<^i23f&rZ<f`39Mif#isQM~3D(1{|b)rl(L
z3_YL|MKGunMb|-{D561~s0r}=M><h#tL%4l&T}0{f-_Bs7|@Agp^CfIJOpIjew0qs
z8s@<R2ID0B4AqI+j2PEG62}3ZC`JwFMA@JS{bQXd)9qEADAVm#oha${NGGZj?fQE<
zQ4}cpSSQN*Kcy4JactRyJ~q>dA&mRg80ttT>M}&(3-UM)=tPw&7?Y|_6vG2LQD%s%
zI#DvjdK1jhi6R)#i8AY_suLyaC(?=H#QtcVs2-F<ov5o&5z&ca1a+cX@jIXswHDxi
zNhfL|GKh4d*tAF|Y7@hvP4PE6QIEjzkvdT?FsF~uiDG=TY?)ZDr2dM4tkglBs8?wV
zTX8Xi|6-#~)HcLMI#Km7h)&duL61l$ss~Y#P854M(uv}o@JH%IeSid!P87ofI#Ka9
zwu4^;{O5I|nC7E(qG<V_>qM<Y;jX=y_2&g2bfQ?Df2b2h)uu=%iWlYPcIIz&qBh|v
z&cCJ;)r0)MjQ@i=QC9%f>O_rRiqlxEJp~Su%EidGc?=$7?pwgvHa_A4xytG}onAqT
zT$atKW^AkR2wJNiW7dnqIDQ5L^qeuD#uJ@bu#15!$I7SG!a4&_v8*LyFg(_qcx+fD
z%kU17WSKJFZ1v&xXB18o|1w!-EHaD#ta(3F)cz=eCsAlhOi8bRLxKuTc2C2u3{#;A
ze`CpTk_t^pC^W4BfFi^7iQgbFf(lLccIT@MQ=!TJy3cs?*7ivR>gb=a>Xm(MT@wAN
zsnBF!H-cqZ`gR=b8<My1$0#(}Hzt@&6q@W?N?;mUj-B`l&Mo#sE-NBxO{u*3qNk`e
zrN*l*%$brSsR=&AP!>4ON==kfY)!SM)I`l9m8M!#YGRJS(UgoxO)L>)8WwG^Qj_$R
zNX{FBY4}xRaQGVjODnKLJ&SNhYML4yM|o6hN=>h0Vl)f0HMNrfTT`tmwX*=Fsn(R5
zA;8g8Yf61WKt@xoDYc7$oTge+>XQNjO|_;}zksr)T2pFQ0TnB=6+NzEslC){)`4nG
zslDqNHYA$VoH~L{9@Uys`_{7sR?MSXQ)+)fRBLKNEI)NC?P{?yMy)AzxZ<BFnvOgo
z%dn-X)|6V5Vk>P;wWidObw7heY1SmQq?vuO86C#_)WbONe>G#*ejFg17PY3-I>@3R
zN2)cYPVyMW-=KU8V7<v6ne-qoJr+;Om#3aqhoZ9@pw^UnCM(Vji%zgo&zeDPfLc@P
zISDIGwWiebb(4_TkZ4jb2xw@aT2tyz-XBqmjHX&s>P1NtXsR`(-l%6!l=bA(0N!eP
zEQu>6O|_=fJ53H=vv+8!HKpE7_X2clsx_tFtJ@2pr-5ossShOUUI0{chg7o<0QLN<
zlrzKUi<=bGn&u)=zyCgpOF^w^G0<)~sx_sc*2L<~@~PI8f?5;1dX7)ErWDkgE&!VA
zQ>`flwI<G=c|O&eQc!F1klTEpYE3DqHF0?@^!w3yDX29umt|HXf0!sQ2evkUA6l7b
zJo@`gm<lunMy)9YwI<qqsx_sc)+ByD)tXXJYq|^7wtcEK0p*C4&({V(%|wn*wWbu*
znwT!*lT(<2TGL(F!g4;<no>|}qOI4bT2l&YO}~L{vQM?96x5n%>+`ABl!98*Q?SkO
zsn(Q&S`$}xzfZNM6x5pNIm@pw9n_j=o9$DrDFwBr7m&`7Xi`vXqUT(nYE3DqHL-c~
z{9had1hu9s;W@v^`JaMX6Q}&_SdnT?DX2AZO3#TEk77!wHN6MlN8?2*Z=|5sbQ+rT
zM7;PQa!*06DG4vAHM#b0P(W1}ufVWtb0W(~#E_(BBm}Z{@Oc=X1xC2`(+D<x9<iKt
zHSUax1}+PeWXZ`m=!4W#5h0`*&M{esRT9mb2xB8Bi6#Z*rZg5|*nqKiQc!OC4m^C>
zMxoq90Pz_%7RpVmrR`I>DFx*w8F`e&F2H3aj-e<wrJ&sOJ~N?mQwqvW1eX6R^kWLj
zO++c5%1tRKH|+!yl$-dYF~6!+E#04ja#ICe?Nhla1?485LM)%kO(`fhar|t59>zNb
z<t92Re>6Rz+{C@Q!{>{p6qK7-XY+xz6qK6|2AbnjxhVzZrXQgyhD4Ksaub)%GM~y#
zDJVA)t@Nqfl!9^-(ORF%O(`fh^`g8}eZH(uLAj|P=xm?LO(`fhvAnH5m77vfZeqG?
ze7><sLAi-&yHDk&6qK8YZuQeF0m@B8xBFCXN<q1a=pLWSO(`fhF;6HraUQW~=_DvO
z5wmc?P;Mfg8{q=}sx}4XruB&MmviTbaub2&AH%MJa?^Q0P;TP3%AjO}OAYokS40(;
zUr#}~iHo<1+d~S<O&qDF$5>S;H?c%h_We<!z-r!xNY`de3)inqPDDI}Fx~_rX$u!p
zG?71)=vQ%6oJag?QYk%dRVd<=f`}9Mr^=-S5OF#UAaO0W!x8NT3V<a3h%2oT-PyxY
zYI-K(oe`52ufp^aT=tBZQqQleS$ZW?Ol=qs0QoP9JE=noJ+O$llUfjP8j84+T9juu
zh`5tlDj&&KT%0!`DL&TrW&E^Nr7jtzMxbJRYYE$(v{ePA7$qNagP_z3=C=q<)YT8U
zJq;sNwsCCXeKkH=K@SS*IOaocBB<k3Kjh}Y1@i(%^C7oH0}?vb54nwlaVSAY1a+K4
zWZ6VQQb)nd5Og3U^;rOU4F(}8h7CanLQ(`I=p2e)A?P$5m|<0gpwqCR_!`3`=rk<K
z(#H^VTuAYR*fE8m<AR{W`Wk|c3n?D9&GvaM?LvyD4K_p2aUsP+PeaggA;rT?3_-_*
z6c6>CK+vHJgVjkPc&7+g2|6yMc)kliA?Ub};$bO<pyNV{hr&%l&~YKfV=702jteOs
zQ#nfUxRB!66OM+U<3fsurB(?#E~I$o0UCmi3n?Crg(L(W7g9Vjd_JXkTuAYlJSoNF
zLW+k-`IO>uA;m-F_>|&tA;rV;3_-_*6c1}wCFr=2;-SKnA?Ub};yH!oQHsZf6pty7
z;u|iccuaY(U^8(c#l!hvKIG<tphIK`IxeJmhzvo;g%l6lS0(7Ukm3nYf+6U*km7ld
z<xz^qg%l5gA?Ub};`tEB5OiEf@emn;jteOsB16z|A;m*v2s$pLcsMAApyNV{hlm87
z&G2z;wjoI=9v4zPj4}ir7g9W5N5h1m<3fsuzz}p?Nb#7KQ;Nrh6c25NpyNV{$F!UT
z9T!qOEX@#fTuAW{8G?=rDV|%9&Jc85NbwLEf{qI*o^Jygf{qI*o;!iehumC9@v!s`
zpHe(7q<BafF$5hKQal`4L(p*{#l!LpLC1v@569UMbX-XB5E+7w3n?BVL(p*{#Y1EW
zIxeJmhzvo;g%l5wA?Ub};vq5w9T!qOM24W_LW+kyVF)@dq<Dx7LC1v@50N40xRByu
z4;q4w3n?Dj3_-_*6c1+$2|D{A*0r;o!8X^SYqO7Bn+rk+IxeJmXcmHw3n?DvBLp26
zQap54O!rp=WKDxPLMa{>QarEH$koc5Au(17IxeJmG~$Gy<3fsO3ILvP!Bq%4E~I$a
zXd&phkm3<Qf{qJ<jsOyLTo7~wkf7s&pd)|;9T!qO+<t_h<3fsu+p-XJTuAYV8wolt
zq<D6MMX?vimFeKA0#ZB`O7Xam;<=Tzq!f<}DIP<X`6*f@1RWPrJd6^8jteOs0ek}N
zLW+k#@erUlr14dPjthd0LY!hoQzBy$gd3)W6i+AOgrMU>if2Cn*XDMicsMHZM>q4V
z=z^eg5dBHeaUsQXy7(tCV2X#&MgCQSjteQCbLdYg9v4zP()=bQzB}>+LFX2Fkf7s2
ziid{!?o4MLH$5TfWV+G}8-h+|WSZ;25Ogx#0t`VXGfH+S5OjDs(}EPz4OJ<g%;>~#
zkh5a^&XKK3(8){;#~`Y6guMpEc#9Rq$GTp}m4VguF3$Y1t|d6et@M0c6J)$2GB?1k
z`B27N+_fjdmVOS--jQ<KWb2<1ERhEyO2?7LTPhZ)G_FNP-m(M>5I#_LRRga`MFq$=
z-;EO$Aiw6jak<*>#x<_0=RmYk1*q|O6Q&AK<7yM83Q*%36Q&AK<GL&tjqrhTPyt$j
z+O|;zD4%ih*Jv1QmfuDdp!^3?m$u&{|NIW)IUW_w?~vymZH?%^{Eo8Za0{}@e`tKD
z0#vB^Zd~E(a>*ihg4d%68HOq!sBlx^^N2EhprBa)0D$m;g0RRiEA&nLjszblXbKo*
z_&`BxZY=63e4wDc{z3W*A1LS$VE8~mXFaQ@^ozKx3c3W~u?c2!Fj7EO1t{oFJkG3z
z4^-?>$1`j4fr?#q>|RS#1*kYuKul8wsMww1?0~Ymr~nmbs!q7bg-~%;j$y+GD(;?^
zdkjq#pyD2BCQ`Z+bGEprSR73ipyF(?WHeQPinZU3EAHi!J7M@h#l6$N#1I%hP_g#A
zam9TkgAPp<pyIv)x*MnhR9sL@;!eTvfr={%8i0HtHnLk(fWk)<ix56g_y><+^Q<&{
zwEjFia5a3O@G<9l0K*3gpLF=v+VFwGr=9-<Fnpl!8F4dwpzvAeZCDH+D16?j$6HLp
z2MYfr15nXa0SaFf(4naU6uu;FG<=}&Wmz{pnkqoyD`GKxpzu`zh7T0JCcyB4!q){D
zK2Z3E0K*3g-;{ot)j$=X@GWmT?zIdbD11A81j;sipzs~J47x^B1t|QpfNh#8K;d7c
zI@^7!0EJKi;-3^7K2Qi1pcWv*2MVDA#F=xOPZgjLDnOS5neWDhPywRtE)2pL47cF}
zK><N=oP-Zlf(nofgYbb$Pyu2B+ouXp2`WHDNuMe}C8z+A>Ynnc0#t$u5bspT$+;E7
z=-SgU%Ax{P+*stS6h2V#TA%Z<jVeIJZ6-_=pyG8VOckKw^%73+iTXR`K%IfQ2_L8&
z%DlBSRe;K+G#e)0jVqV)bYj`(;TLCjA|Cj{R+fF04^-|feil)}2P%)utYBTJ0#qJX
zWJ=)!mB*Vf`9S4f6DA+1Ji&y?2P#iAVe)~>lT4U=pz>rBz6TkXr<gGLK;@|>Og>O~
znhBE+RPK|o;RA(B)O<_@;RA)sq<QAMap6(brF=574UZO!`EFczi~#f9xNx}u^WC^`
zMVgrzK2Uh9Sj>0h!s7&(@5Y5I1(@%~g{uUZ@5Y743oze}3s(y;-;E2`2r%D`3qLKu
zd^avUL4f&gTzH}Y^WC^`tpM}gxNw~S^WC`cBmw5Tap8Ia=DTs>1_AtT9H*VA0EMRn
z$D&!7Ug&wnm2(RISNTBUX_+-Za^AfX0U3GlfjG?EL86;=+9Z-YNuJZ)JWb@(MAkP&
zX6`L{*->$JiXyqK<bTA|k*pKfegY9K++XBUIx6EYkw2HFtWV@j=_11iDnSK^OIY|o
zr6J#qD?tV5Vwemcs00-t*}8qI0F|HuMCABX0V+WSh&_|>sRC4j3J?q9WB&|(M^ObR
zgbEPrDSV(1DnODKv%ekxs~seKpb#oR+Yu*xpb#oRJk1FoD1-_SyRbqPpm0+aPz5N2
z3Xr&w4-{S#GYeN#fJ&_@z~zTfX-aJ}kmi$XrFH@4lWV080p^oyrA`6nlWX|W57)Q(
z<Ql&8L-7Bw_a$I*ROQ;$-Bs1qQ&rPFQ$5`?)3fx<^dvKr$-XdwkW4~=2mt~_7Fhy>
zKmq|`2uXkh!fHSe0;qry5hAiFkwrm3Z~>9!itGp|2uS3DA_N5l`QP{Zs(N~WT+!?O
z|NlPE%=2_lz2}@d=hUfF)n|FX?^Ve)?BEip<QkNI2vl+nN<RcDxmFk<Kqc1-y#iEn
ztuRu6O0E?~2~f$k!e{|1xdwG0=BAQsg|Pxua;-2<K)*<?6~+rt$+f}+0V=sxm?$8m
z(iA2)*p2w97cW4C-JQ4DI`jfmI8c(Q<XWLpa;;D)xmKu@Tq{&ct`#aJ*Wf-(TZdkN
z;67|RZk$T4!F?EkO0L0u7?Y{w8r+8wsN@>lhcTH-uEBj6=Z7k}R#+v!K@+O!1*mYE
z{9K1#fC?AX$1tKyn{)>tRGPwt8D61KX$lwV+nrv33b$8FIN!{LI|KF}q0$t7B*$Hg
zpwnA;)OiHC36-Ysm~?R+6%`&A5Ob^ebM%DI$55#>g(n3lm8S5N0Hx9to|bbQ_i8>r
zzZQ^kN8zdp&qy+*(iEPRpKGPk6rK|hQE3WrN;DBaZbGFgz$p=dQfc6H&*Q*IsWb&R
zB_dKPO`#a8+6^g{N>hMSBDQ5Fpi`m(oD%WT<-^KrmDdpy=je4zSJKkvHV6<ZO#x1c
zSg6AXd?^m($qlJA1vn*QUXsU`m<PX*@kRLOi&LWJ8P2c4u8>h;^GuC**Ps!bx3Bw3
z8>;WpDN*wd`ELR^E}arJ?<}J?&!tnM=3S(RWL!EWYTi})LDr>HqUPNM)Vp*_)I3K(
zlS`*W&Aa>KrN7ZBQS%-G+TAM%_7qTZXA#WxIZqnq?uNw8pA|6NrBkBj&*iF7oi3M7
ziJCvxN-)c%Q=;bm{4d~w7rJyx)VxrxXR-SfGgu^GiA$$M%|{4W=F%xq^O2JEN|#QF
znimT=-lbEb=A#6h;C`EJaC9TbsjJ*g%x#(c@~lzKx&oXMy@FQ6CLtPDxJU&!C1Q|&
z3;Md*@)@TNln{4YM7Qi5%t8)`nuOb%Y1z}+n^D&w9Xv0wVemRcOv_$AM^SP2X2$HD
zdk?vp?!JuK$LCtPV-)G}s0AL6*xh~cc+?7yN6d~+rdr|g2**Y>Js!2T`0PNYOOHpb
ztupF#TzWieErz51wjw~AfQ-9_8MI5XtV@qat?+n+-0I!C(HPL_B4~2y@u;;^Zf+6R
zFG_9V@u&!oN662m$D`st^5!sHdOX4p&U94DbZPQb{G0&CrN^V<egZuAZruIi{$a<W
z$D`r_0<tbW9u@VqSntx~QE{HcG`aM6R6IyP(WS?u;=uw+E<GL<4-wGi(&JHazJOkr
z9*>HLhA%RDJSr}bm<etVfsUv8jCOiFD#GItuDG2ZkJ@&tl@{N)0XMMi4Cn8>&~M;2
zwS6JOduF(A;5M~=(Psp9r`V0F(MRRk^bKD;B{fg1T8A+AA*65KO1drPXY9j$0!){l
zlA0$Aa9nyyYTjCa=h9PB^ELu9E<GhRPZ5xH=_#oho{~`2dY7J(nx{&iYI5l*sd<`!
z7NdoplCWEW3bfEuQrcXP!ybA{YF;V7+#}3b`@X5CSi|#hG41<FS1{a*3HJ9HVM1gH
zmEVLzxw2_S;>F7mdqCnQ1o@&8+tK12(2hJt;d$(+REg~<28>YlZ%3QVD3$%&(Jnnz
z*}ok+D9F0c<H9<0P@pQY9i8%$4%xp)Aup)}*uR@m`sxUW?B9;=CMFT~Z^slF?6fzd
zu{*Za<Gt}(>6og=x8haSF-?w@N?7W5+B<L&RcN%*40$IQ?w`H`u$_RI`vk#EsZiYI
z+FEIQ0eF29>>$7vDq(5I%ywu)r4p8A$)nta_XK*}!qV~1sU;Ld$;r|Q(iaVP4?F;+
z69uT`WNDQEm7FZC7NC-orIQ4x<Yeh&0V+9JS|dOuCrhUYP|3;CsRC4TvUHjNm7FY{
zE<hzGOJ@jB$;r~00#tIc^aTMbIayjOKqV(jX9-Zr$<o;ZRC2QPMFA=~Svp6+EVmyw
zq;#$Tr4p9DBtRu6OXmqt$;s0B0#tIcv`&CZPL?hZppuiN3k8IdlcldT@IJO)hBnrp
zQy!u7-^Q-dgxg;FTFpiTrOhwlTd9Pd9nR!V+!Im>J3DhcRw`lVu<#a>O4vDEZ?U@u
z(VblaluFpy9gZJJCG70c@q<taJ4dJa!>&}q&N1>Hs&@~=lhQdhy%WkImGJwhNbe$K
z%7Bpwn1=sKCG4E+TmT?c!p?2vLRE6IbBX|!ob23IfJ#nwP8ASJPIgXjn1c)wzhlj|
zZ{np1m9TT~;4&VQN;s^NN;tgW{1p*GB^=%yPP&i48*g|^l|76v^|Mw0v`UPl;|_*L
z!xo+_Z^I@8%HtYR35R#&JOnv?_~J+6NG1FU>+v(Z$A%AU>|zQoU43pKg-{8H56|p`
zAfXa=bp#w}36-$xOLbgCORU16qq{l7R`mb#LJS<b+nvVYXt^KYo_3c49xIiwyE9V+
zP%2^funbGXZNzuCE(&<=W<1c{m6DU)-Exjn3A=k_5w6}1(3`qPNQ_bmyL&Sn<rUrY
zP`&N}$;q=(^R#&q>rX0S_oN0^N2r9|eL6fo8~35RQgX6qfpZn>Psz!i!%WWSbtR<d
zaF<m!-NWxd%tCWB?u}9jdlrRjjd$^!BXq6NU4xu^j;!K2S)=_~{NVJQ;IW;Yosj>X
z_=Hr#o)epIWVPPo*<Y0;qwXAsmFHery|ofo!#$nDW#_*lncP0?3EhPkU2IhP6$Dv{
zH4mB2XdfLuHYUbVsg<}M=ZvO%(AfAK%d--Fx0%kEop@Gz%wjzr#A^9k{Ew|))P;?t
zXYjj*sCq_$cQ|gr(xpbM6q8+3icyYF^W4A6so9Rmb6dO{J4<rvU-LXOvF@qW6G}HR
zWl8a4t0%lAXHF(%AhGV@)uSFDemBKmx5T>FR*$+9zwfd4gvo`HM;*Nm@NXIV>rSkD
ze)TBlhrsWL(aR=E#r`h!O04_sYGeGvJpDPTnAc9#I>7Y{%N2Vryrjiiuje{hulTx!
zTCL}{X0_<XPm1~N;9_0~FaKC${0*%19a74}MeysTl)K8M+|i)f9yH;AeVA~V!u?0h
zzZvjHc@9!hsMh}O6!(STJ<gc)D6_pmvYmr$*Pw2(^|2mo*T{8#uS!!MyVWwp_91rS
z{DnsB78w?jPipkNz#LZC=eHQn-BPJraQ1{bC?K{1Q>C!YrHxMzG7f$GNgJOiKGEar
z_Sdpjhqc;IZ_sH~dV?NYJ^3-@JriZGVZB)X8PZL0vy91It%h?x;?_rTUk>9I8(Y1G
zxPziPUm4bUA?nQOXl#ysHHagd5FcBgAAveQAfc^1hJ(XVoJGa<ki{KTdE(*)aFn>G
zJYDQ1t?b-$bK0&4=@sl1-mZCg?D@cK-ORSx(Z=45Ge^qVu3XNJ!?m21#x^H1RliNf
z>=a3*HR*4UQW)o93TPTfV{90*Y)6)qWxGGB{4cX>KZ#Lmp2{0H(f=$eVv<oC@2#H9
zV=`*vOXb)iqc#CX?f!^>tjJY~J8>Y4+W6Jpmv~G@ZTy;m;f8~{8XOC!n4XN<_?4+Y
z<4_p2@oyzrmNIJN*IHl0v1yppJdIzM;Ati`PvbWfj=-^Jn$$csa}E7KzOZP`(az`5
z&4m1EjtzJ$ELwA%<g6@ObDYa!ltpWf%MvJy)*M$L5EiXD-d%yyIYZCmzvJTT3;0OQ
zQQpfqE}2_7T=x|gtvNZxla)nlZY@ArwB|MfltpV!5uhwub6Ww*qBW-qP!_E@O@Oj!
z&3*yOqBW-rC`K$=b0=pv)`2WqbLT1^D~r~gogz>ct+{IzuOMX6n!5`ki#CPOc}OPL
zRc6te2RK(SQ}XD{18aG#ELwA(&8t)vt$A>Y%PPvEH4kZFTaZP|{G40y#ZQ=V+WZkf
z$f7lmgZw3OB#YKuUc+N$(V8nXdt}0{qAXhTMTaiy$)Yu1s+GiK(V8#oO(l!g{Jk72
zi`IN4g=Z^d(VCkCD2vwoL(N?%OIft$t8$LAXw5%Yu_cs6YrfTdCw?rIMQgs@{2G9=
zXw7&0jLk&}vS`hBQ#}C6qBY-_td&J;ejwFU7OnYrDMwkfCRns%aFViUO|WSDfs{pS
zf<?>fDT~$wi<V8TELsyR+T}pXqBX&y<zz-#v?f@zA0SRyv?f@ze58~`Yl20~T)?8`
zKc1A6FJ5i#I$T(e;b`we5S3?C$f7mDqGi0WXiczaC7rNnO|WR!quR=%1<DdBix#Mb
zNLjQdShPG(S+pitw4A#ti`E2-mT}6WHNm3&9^#ZmYl20~IAzhAV9}B&q%2w!ELuL<
z%Az&FqGd{D(VAe<GEP~vCRnuh;XGy0nqbi~rLt&EuxNRC%Az&Fq9wUdS+pitwCwUB
zi`E2-mR&kz(VAe<K8>^?i`E2-_5fUP$f7mDqJ0^$!lL~i3W!*=JjTWa8d&bc3xE}O
zLLh60G`Auu&w#Ya<*qt(HG{pbA~}Pi8}}yD@KkojfiyTfhX8ryvX9Agh;@n*QqGAm
zhGS&Wnqbksjw@6atqB(GSCB$jv?f@z1j?c{!J=hR%Az&FqLn+3ve*P^lNl?E7E001
zGt7i6S`#c<0%g&fV9^pOi`E2-7Gq2UEL#5iPeg=OEj(y~MT;dcWzm{o(eh_QS+p><
zsO9}r7Oe>uEfXq>)&z@|?`mbynqbkg&dQ=S!J^$2NLjQdShQE5L}k&MVA1l?Q5LNU
z7A=voXiczaiIhcaf<>D_dCH<S!J;h!DT~$wi<adni`E2-mggyp)&z@|NLjQdShPgS
zqBX&yB~lix2^KApvS>}PXqhKiwCqPLS{ex~T4EM17_CLjl|#W~(VAe<?u`Ip(VAe<
z5-5w-1dEnJSzyufwaP;|4Z{z%G@pnNH@#tkMJo$WWYL;n(eh3Si`E2-mL+Q0*GDIn
zS+opk<?}0@6TRdII8K{<PFwjPMIHIK68s<dcG!>J#(|U`vS>}PX!(8;7Oe>u?EwHL
zS+LgLdG_iy3Om|IRkK?ZDO{BVWu>3>dIcfVQkdBo`3d;fMtZB$QesdW^-`Tyd4Np%
zqDytxGc)sW43kqM>e(mF{X1~nTPLF*Qeaaf^USw{MqDNtuT{J1NyA+n?<U82dPEYJ
zbXB`+F4YLA+OuBHq!XXPj8}0<SGBivar5i7_(7c7G~klX?RV&TPL_P#>D4?|#;ZF+
zK;)9H?G&_uw`YbmYoqw2w_gK|2HMDY^(tM``Cz=#os%$L{Xs72d@x@5`=E?hAB@-U
zA`4}_`e3~B%9QcygYn8tl=13=@k$?9l`iSnkMP#vDRgNiH#B6t`e3}4UDEkrys{K!
zy!v3gvMq)2>Vxsh^C6doi}S&F)yk3a>Vxq*;F8V<<F&#ioe#z<S?<bs^}%>8yQK5M
zcx5hzFkXEyUNuiLUVSiLiInl`gYinFj8`9w*8!JwJ{Yg8S;%<x!FU~TN#}#{O7~L2
zc=f?})$;ft_+Y$hd1So$V7#(FDB~3)%L<otJ{YfzQ^u<g#%qO3Iv<SJ0he?>7_ViQ
zbUqlb11{-&Fkb0sP8qL07_UUic=f?}B~r$#55_BzGG2W!UU^fL@#=%|N;Ke-j@KZJ
zS09Ym0he?>7_Sp?VZwOz!FVN5#;Xs;t6n)7uRa*Bj8n#|55_C6)eFdY^}%>$Y07x@
z!FVN7#;Xs;>wrr-AB@)lmvlZDuk<~oj8`9w*8!JwJ{YeoT^X-F7_Yk^r7~W9FkS~-
z()nP#vOHzH`e3~BJ}cwZ2ji7U8LvJVuSCjt^}%>0QpT$f#w(FBUVSiLiInl`gYinF
zj8`9wS0ZJ+`e3}WC6w{%gYinFj8`9wS0ZJ+`e3}W1(osYgYn8ZWxV=eynbqzbUqlb
zWtVh57_ZDn7_UAUuWZl(mvnrlL&mEQ#_M30bc_rcuRa*BWtVh57_a0PSGc6}!Fc6G
z3**%X<5d6|uYRRVI=|8-onPsa&IjYQ?2^t0<F)LP&IjXFawFr_2jlf#{2y>h$4W+w
zS09YmvP(K2j8{6Ct8hu@gYha}=+bq_3XE3)WW4%dyb=t!q+`Az<JJF|OFBk|j8`9w
z*Ro4GAB<OWW<TnZj_E_jt6%Ao&IjYw#ZJOUUD7dq$awX^crCl6^TBwP%fAL~urp4S
zmvE&^Iv<QzMpSiGcc#iN>8gkM11{;RD_zo6cZq*GWxQ5*%Nq)7cpQ3M7v&$iq^s^p
z40cJ!TBeM)wfI*(u8}V3+Gw$sKB_8>>a~$knm$^O$tX=9qsL^FrkCh38KvptYS}4;
zQJMs!^s~sXjf~O^bR}yLZ*myWMn-AoeHjw8J%Ri)A81N4N;4nG+`p|3b;x|sBstuG
zY%(8e8Zt_2uFmmSzm2+*HP^@}L1sl4;CyMun9)XE$r|WNBB=2&Y~Ze`Jv81xwoLHL
zqwvN$ES}*t8^PI&feu$>27f;sXrUq}2o?e@QsiZ)&)mzXJwj0?7|mRcRFn<=)(&)(
zqIw7u0UfQVDX@r+QB(}7h?XcS1qGtdE9wf0L`xO*2ES?pI#$t`pp$XS6io<vh>la#
z7mOxau4qc|JD#^fQGc+BXr-c=!5@i^S2Qc&b{&Lyr6pzu?-8A-Xik7(nNhn+(cHi$
zTCHfG0L!S9>6P>L4{C`{R&-EMPqaqSp+O7LDT)>bC8ARmEe?8!PE)ib7(;ZrqGiD(
zqB9h&3}$20S9_+SRYu2UxTn@A+|$~%@dR&a{nwEI!{4*x4PQi;$nLQ{?$kM&-UzN_
z>zu2|4BR5nmlQdH#azx)<OMF#`HC{ZB}}<aQ8p;BbuLg;ADqg#3l%j5(=j%!y+~0p
zSiqEDR#Xb6@Jha-s4K`a<yRH;1~2luE><)qxPj;rMH2##xm>EKFSw62`<kLD!J|a$
z74-*CVWqS7vUuivT>8wQ#1g)tar*=T^SoTq{=w@!?+Qf+1%DyBQqiHo9!$AG(Zb*^
zmi{e8i-Q|@4Ob~z65Pd<-&V9Nn8TD;D_R*G#kyRhXjO1F<E~Y-Cb*xuT&L*tfO3Vk
z*DG2ZP;RjHJBrQ;sCZcWT}9^y3)$8;D7q+^&0IDrx;UU_VeR)6tq-VeSbL+Q%Yz+w
zeK#rE5Kv64_GU#_2j6BrZ&7r8@Hdw5eMK9C*I2?26x|#Q=QZ4_=+>Z%DQ{DBNAP{3
zA1b;#xQ_koc11r6Zf6O1D7r7GVd-}&dN4SdE%+lv4+qCH?k+`-1y3@UyA?eZe21m~
zSkbe=hfMhsMb8IMFz#oHUJABm+&zjm1#dBzdlkJF%x22_6ul8FV$FV`XmjvaUc>#0
z-U*)PwLhTf{f0A`@}YR<a<r=vYaqp@_LuSWQao}-yx~Hg`LMz@@rK1b^$|VQNHi=X
zd{m*CXgGn1A5-Wg8a`zG9#`lk8eU?~PbkbJ8eSuOQeigHa15L4DTVckh82WQD{M+M
zyvm%PiDx#VlEsA4aWZNr6J^#~eht8u;Jcm)1W!|ZcZ9bxtn*mnbMXXUA8C^@b<6O>
zB+ls`0z%-U_}91=^`0F(63fiTihq#AvlcuW%W__41pDF+1dk~)gK22<;BiGxa5>Qv
zv0#6s^n%|o<&%p1U^B`No>EjD%tr~q(~8o;!?@Pq*NQU1O2$2-s3us277m_OR2xh~
zGX&2m3WD8Pv)?Gn25rpc`B=ao-}>M{p7(;HreFil`&}%%5H%|Xm$EJ|>3QuzBjaAy
zYbXUjXX&qKTvsrfd2Z6U-rymo{DYz~!33s!RndfCXU4szs4uvV*Z#VqDZ!h}<&TQ`
zgG*VnH(~*serAwnE`N^I@g~eNtmSONw_*u;0d&~>Yw(f#nJ_wcLE3DpZV7^{#2jp8
z8hq=U#y<F|2)ATTMw8I-$=pt;9mNe}M^xnBzcmw|=pSI9Om592)Y*w_%_J(EotW5~
zITVRtJAPH-9vsNlOyX+qD?H}bOyZh=;c9LFI1a?Y54UC#SEk+tmaUn@w~{PNw`LO8
zT36yY+?q*Tm*8o#HIulZuoTDP){Ir@;KUj|q!NU#pj$K6?9|=>x;10%S{1|)qYh52
z-34)LrUs#hBbnTh^45%XfO9PZWoyPd5WjiMlnzd;dA9Tiad2WCoZ5&O-I}ouX{iO^
z)(rD=?#35CVa93mUVw0G#yZaV6Oe4pSj%g8tXnhI3e6sw^dd~RW~>*T>85VYSTEH|
zVs6b?FH3hZxiw?`UXFEZ#;SC1VpTdgvHno=bCji9GuEqej&99Zf39Ln=+=z&R`Wf0
zwdmH2^>*`S0Nt9g-tp_PYN%T?*1IW6cI(!R^}b}STQk-NQcc~OvHmXQ=+=ydt(iWY
zq+2r<wq|Al>DG*etr=ENw`MGC&9JF;YsSLX%t=7HHDh6GW*(YEw`MGC&CnNuZp~QO
zn&Bg*TQfr{K^Tb*sRW^q$#aNBQa)EhDna4ajD@Y4YtcAEDnWd$4ygp;cWX!`DBP0q
z25rfBgSKS6L0dB3Cv3@ZKv=mYLp-Dsge@5kGt7WnGTxvqnIV-R-IDPJZOM3pwq(3P
zTQc6DEg5gnmW(%OOJ+zVh%<g}jSi^<mA7QP$}Ji1<6AOb<(7<Bxh3O$Y)gi3w{S~l
zNF@mDEKJ=#x+TLV8d3=|g6s1`DnaxLQa8(Imr$=Db(LO0>UIj~LVrjl2rP)#{r|+q
z;gCvDI*&C}^$L=QSC9@M^$L=QR}lJure}^Jm7w;!@kkA+1o@-UKh!HoZkYh}3X(fc
zfO-YVEf=6(L2@eus8^8ON&)l=!ft0?>f=c~v3^J;h?_n13X+Fc5VnkZ1<AuJ$dF3V
zkV;T~v^+NI+9W?lfVwuxj}@S<P4eRe^owhg{CENC+9W?gfVwuxPZThu5|qCv;6SOJ
zu1)f{R}ZNKp&8)Xgzq03P7SF9p>v37f8&Yr#HeY1<0=7a+TXZZfSUF<o+Lm``x{Rd
zpr-weYXqoif8!|v)U?0xQ~_$*-*}n;HSKRaU4WYQH=ZFtP5T?q6riU4jb9L;ru~g;
z1*mC%<5>dKw7>Ce0czUc_(cI~+TVDN05$DzJXgSwN>CA7mUsq+RDy<7g3dOvz+P$E
zUtHk)f1na{P6?!glKm`LDi31iJGOpr5Lr|MsML52-r+EP?p?q{T^Wiv#@8LzJ3Rr|
zogrl;zV49Td5rA|;ejJp4Fll?Q6*$FYLO8e73VfNjl)Mi97atGqeh2OON`M|hU-~8
zV_X;vs_dA>%)HSii)JmdiS&sY2kR3x4%R1XjP!{{i9S)&fIiWLPRtjK*TLBeX*w?;
zf6{cWM)_+^1h=EEG5ZIg6vSiBE&La^&PV!qJh>F<;->X3=z?)Gxiu#KamU(B<Rm8o
zCAMfmJw($<o76aPNOCz3AKC53Dx_FYTU$A#ricZ#H95uZq88NF)&kUm+S*2dT2Nb4
z1gHhIwXFcPpthz8Pz!2nngF$+w)zFA1+_I@KrynQwsvyJ#t{o@Yv(E+57BhSqY+ex
zXo#jG-31oZ?49KH<m8LHg{mYhy%svuh{`i6w4k<NL46b6B4R;p!Gc=Si3PO<3+fFZ
zH>d?QP?kt7sDWCD)PmZA1vSr83u+4%)EhvXQ44Ad7SxPW3u+4%)VCo{EvPM6P%};~
zs4ZAf-;X%8ptfK^eLQNf7St9jsF_kNs4ZAfGfpk2Em%-LjPr(QI=CT2G@W2A_QtJ2
zIz&S>oqBR}U_m`Z(}AxRGNwbC4h^WC5u!<C(rDTVb%W?UF>PLe?^asqsRF53QKwWl
z$fV_OD%1_4&6-$Ir&Kq{tVTd8)D5Cl+b392r}nNt6fZQfqOO|S^Z`<-ZctUfLl^jB
zMO`($n#XEIT{S}ht*B{pExJMOp5o_Gbc5Xe8t8IVbc5V^wM?VBK_0BAZ$vg?MeV_g
zn)OxPAP-j5$|#|35Ggw}sZ=X!Qg)b9t*A-aVJ2!tP0G$sfM7+<Bs`4XJj9PgxPr2?
z8^T04$b%I%OHnIo4_4IU(UxLG?ZJv#D@QA84_4G#Ia*PBu%iAg@=)C%4_4GHHPj9A
zU_~uX=tp1-ob_NueI@hU4r^W>tf-lbT2XtjqSicVMeV_gnn<mvJy=l_sTH*cD{7Xf
zx<MYSs9CenirRw}bw5f_-5?KE)YNYiD{2o`)LI^`sJ)L-cErjtcmU&ZQg(<`H^_q(
zHIZ6Td$6MB^@X}Y9;~Q0vb+oMRqtiv8EUVIZjc8nY68^_@?b^%RUoyZ_FzR#q*l}(
ztf-09irRw}HIZ6Td$6MBO;Iaq4_4Gfw4yE|P1@uYi50a6D{2O*Zjd)Oo}r1OSW$bh
zq9#x)Y7bV_Jj)DdMeV_gnsI7H?ZJv#ubfuYr0lRXwW20vhe)lcN!g)owCV<tvO}c0
zL8R=^Hd?KyN!g)9qUr{HoU*eo;?#=TgB3OJtm+1Nu%c#pYDMkAikkOXt*AX%Q4^^Z
zwFfI|BDJFSU`0)&R@5G>sEO2y+JhA}ky=rEu%aeXD{2o`)I@4U?ZJwgEumJ_9;~Q|
z)QZ}J6*ZAsQG2kWW(%qnwFfI|#;Fyx2P<m!7U~AQj8ORVlDo#|5LyE`D{b<D5ZxdT
zR@96Z-5?KE)XYb$s6ALwGqJ<-zJddJrb8=g4_4G?GLld0O;KcMMeV_g`bva}Zjc8n
z>W2W*@K1%HgD@TUU`5S~7AtBGR@4G$MeV_gS^#x}JXlc+pl*-{D{2AM4f0?`&DW3U
z26?ce7Q^Y^ptE_fqLyT|qV`}#{RsX$Y=wPcI#S|GHnO57WoH%wMK_3)onryu3W^mU
zhD|zBb{HhOL8R;mpcOSKI|L5DC_N-CQ$g9eoRQ4vp(rx6qV`}#eJ8?1H^_q(^(z2r
zldlVhUmry2Ln~?zR@AREJ#~X1gHy=kO_4Ug&h-2m2`Gh!R@5G>sGAWcx<MYSsO9o+
z!R7BArGyprj!Z$_AP-j5jHv4JJ5%4rf#?SL!+aha?(_Kahl{PW>IV5;0@RAy@0K?d
ztf+6pl!0c^Qj^e%8kC(y2yz(yXcRX<*`b)J2>DbWRm~ZPxf5RMX%+G@o3M0~t`PFc
zR0{dj996~DdJ*!eIa-ftc3pFf9@Ff)W{Dot?7HT-TJ~ZwyUxJuniB^R@~O?F7vL8m
zZL)k3@~M4a>LNluwI66onqAj^kd?D&c3t~HlN{fGY-&H$G&H*oDujH3Yh>ajQ>kC#
zd})_Z$On|2yAY&8KG}vUx}y^zpKN0Tk6EE-@V^s6KH27a2C0xwwk^9CeXPWA-?AN5
z?=!6k`D9B1RLCdWS;gw9kWY4)02T7d4i}Iy%(E^>4qb^Pa#JCnx{~u%X8m1UU)``2
zo7WH_pSs}!RLG~UD<fl+P{^llhO;Z~nT$;8W@dS;LOyld`*KG`$fs@xA?B!%Pu-3Z
zqe4FaC1vN)O3Kb(Q7sknsjC$7soO=eRw19dT?MF+Pu+eEd`wlyr*2Vx0sw`4c#*?I
z$S3!-!y-h;C-+PZkJVFY?%67uLaLBY?m6$593Hw$Pr<L>3m(-|RLCdyqL--0Z<KpB
z?ndq<Nv1+RxtG0W#Hf%@?iFu5fC~BK{vbC%g?w_a3Q!@R+<*GKMiuhOy(UI-D&zyo
z4r9uc9Rd~d$^A)URLCdyh5!}v$^BV?3i;&Tly*@epWItDhhRjcLO!|8J~;>~<db__
zMky-fllzMR74pfwC)H6QpB#jIzK07^A)g$Cd}aZukPn>c$~Kw``Q#wvL*9f6`Q#wv
z!(K%ppSkELD&&)gkPq*Z2>Ik8<RiC1gnaT4^5F?8<dcVx57Cw=J9C<GlaTe(xQ%cN
zhr4Wkh((RM6B^hnMaZY_O5OK72P2HS4SGx=pSo}9F@=2Uu99OF@~N*^siz;q;a`2D
z^jj73sV~TOkqG(JH;JeU%T^Jg<+vP&U-#l8k9{cQQ{UO}eFTY+PyO(Wyh14CQ$MPK
zXNr(d{b)U=kWc*>J*JRP{a8JwkWc+MJ!V&|AFs!BVpu;xkMBlD24zR`q>xYjBt52(
zPyJSUOd+58J~>t)pWGqNDacQRd~%1%<*ATQZbA4cACGKvhe?bI`Q#24ph7;mg#uK_
zC%4FFW-8>9J3?Yq$R~HC02T7dEf%0cKDna=sE|+YXaOqZlRHL$3i;%g2v8xP+~)<T
zkWX%@02T7d9V_79PT9E-mxb<yC&=NGvjLw_$S1cta|w|A5Q^nAUz8B?;cey{B*z1s
zE4I@-=IzU|yX$fslOy_ZgvvR5x8&rFnl?8_fqbpxNZ^wbkvxTfR=!_kWF3{!fdI*b
zkET4INV+SIRmdj~As;@%BIJ`FB;=Eakk1bgr9wV=2>GyHjtKeWA>>1}CCUy9;|BU<
z{2xvspB#jIc!471lY@|t<i+e?z(*d9gdsvcISBdu3SlDTlY@{Cf96EUCkG)Pww4I_
z<kp0MLOwYN`A9Mf`Q#wv!`#)ie?yCNF~$$#+P|UFwSPk~V1&B%Z)gixJ9X{f(C%-I
zeAKmnLx=Ppb?x6!5}>aA8#;wQ8M^kT_K;i#T>Fp4vFH=A8lh|dhVCXN5!e0=Q{?i+
zwSU95dQ8V~4O8`)uKgRP$+0hLMEN$yF5n_=!Wb{#E_F~fqP*5l)rj(1J5?jfcS<r<
zBgzjGplU?<;Q~~RDBmSO)rj)l0#uDC-y=ZPi1H%@s2WkeSAeP!<wpuoHKP0|0jfsy
zKTO%#jMh{&qWtd8i)@|C@tcr8P->uRMEOcJqI{(qQNB`*C|{{Yl&@4H%In*&-lZB*
zzEX`SU#Uiv*SDXl5#{ymr)os`N;RVV5%NQ-YDD=}@<Xa>METQX%+Uu&eORW=Ur_%i
zTo3eJ@hxgZ`3p0=LQy072xUjYsYaB)GvFg2YDD=T$?>p77&PV|b?$CL>l}gpoqtTI
zbvm@mKQ2Jki1JTJXI3?${F4GyjVS+=097N(KP~5|8d3h&0#uDC|BNJ4HKP2pGUiY<
zqWp6LA~m8s)QCEo@y5B1mkKo^0=Ru5^$%)99MY&7Q66eUM5;!VFUG1UOrvT<d8iR_
z{Xo@-Dk(d>R(ansagNWiuFs{-ZUl%LQ66eUEY#s!>L47*bBiexHwyAlBjVsf@>s<@
z_=THsD*m<5k9M(-tqn09>Jz0+x^WRPojk;J7^G?(jr~prUK2!(qj84MIgzSyG;SwA
z)i@ewhRsejj>hf7W~UlQ;||*FqQ=p<V`eO_OVv0UXZiK0Xr#u`c)YU&3zeeA(Rf1G
z`>Dn;MA<<boF@&UY8;K{3s5zV#&rTzjid1b0jkE)c%gt$jid1^4ZM%7=b(+XJMjqj
zoo;bNjid2vHJ2eMZLY$%s&N!LoZ&^>6RL3(I&(Z$H4eza@h97Ksm1|WI0D;UgJ{UY
z5vUpmWZ~HJJ(p@6kcA`2h#E&>bebJo)i@yW#)m-FI0|FaeJF>Noeii+*8#|s0o@1~
ziT|p`QJCzk0T4Bg!ZvcDs>V^6B0$wR3fl@$HIBkm0iha4VS2+<WMEQ_qp*DwFHO`q
z3VR3V@R({GO_gdK%?0OWM2H$kb8|RyrW!|cOVwuPBx)SZtr7z@4%VCD(PPV#Wh7PA
z7Cxz=8b@<S?mfm0LpVS36jP03BSJ-uqj^|k4iPf(o;8p{)Hs@lXZjE%Y8)*c0b5wq
zI9k3`$C<E6HICM18E>c>M{B#|w4>#IfO`sIDITjDM{8%M8bH-JT8Cvg+f_A=Rvp=^
z8b@oT8b@oloTF+Stvxc6RyB^+5fY<n9Id?>-e6VZXdO`FSc#ga&Bd%g)i_!wHLyCO
z#?jiRGnlh+A3jRixrp_r8b|RklY?@d;}#Ehb%IVcj^aX--d0tOqqrzsFrXSo@d#Zo
z5H*hCkySh=RO2X~APXN(AM(ErpHPjXcw+PAtQOTcieJ?vWaT`HK)G2lqi45H@M0QL
zKShw0*a)SK9%yNRG~>)iLM!oIgp7ESA*=2CMi|aQR64f4w*#~JHlDdU&vfy1D|;bq
z0XSS)Kg)~}+cNq%dlgQaEhp`clSWea;JDWC9AiX`i5A-q5-pQNXENu#B(z>rEmIoK
zk}B@{pde#J7o!*0cl1O#Utd0HK~x=M#JjBYf%cMesz=JH4y-Fz;9{oQ!_Fer{!#%O
z0aD97+6I+BSEQ)p>rOC6+{$xi*$;N(2TacCML_R8651Zsa`fxOQ|*~ZwN_H?!Bo;{
zQyappjWO3V)g;?Qs(wi|BG0Sqw)?vb=Vub~1kd{#etlxyt=u7uuUp*fNunM;su1EB
zb;xmt8L<%|iE7E%xj1({qDY4t>1v{tW7i^d4nvPHVq>H;h~|bdZX7dfwMk;SSW48=
zT8moR5-qKDgl4pO>>WtBB+S08oc+%bD%lHbs-vbCDX6uAzm4dBrtu^EYMZg^hU2wr
z<7@jaL<~cke+ysAys-}#@sy}YSj;vyD^~wmR>3h3#DcADo&}KHfUm`|_>E2mPqovC
zD#UMgT~rV6sObQ=xZ49f?`+o(@B?=lz)Q{*XrK6PRm^RZb27mX-81m^ea%@<aC<G6
zv)@Q9n+kBJOJAm4vDCf1v>&-=1NFpGuQB0Wf_91-Rl`ww0Uy`!Sdq}dyH~`qKMx~^
z#0yP~_NSwr%&Iybi<X8}p`~G0Xld9LS{kuXOQYJfuS$FsXQoe2;QFuj7V?-5o9t@>
zh8tDrSjM+;B)$<7MvY@%nR)=&c^S2~LoE&GR;048wT?qX=&;GYF2U1GYH8Rv6lUVM
zR<$&es-+Q#mPT^4vordub1rgAjtzKhWak}eBttC?XC(F!lA)G{b1fPy8ER=bGti>R
zP)j2_Z>5nO@9vJ%v$&6cMrl=KejSVe^@~ZrU)W4YZspK8)rsLN8ER=bFXJ_v47D_z
zGtdQ-p_Ycz%W8#M8qNw6Ak@-uMq#9$47D_z0$MB?YH2t}5QJJ9&UMT>($Yw-M=Qgt
z&rVJ^52&S)+_{R!Se?LcTXJ@aU`^^3EP*9=l`Ak}sU7iSmfT$s95z+Gi0hb)WO7}t
zM)KJ^4dZ;c3UXF4Q)$QpYk6!qbl8*(wKSY|4BnFmr%q)mhc!ta(!#b_iw0wURn*<&
zC(PJ3F9xU!`cb@-JkI$skV7qv<nkIG8&1bf0Fjo4Em|7ENDPY?CSP;{i#KwKk$kCE
z5@+GCDH&>MWZ|$W8ER=b+wodMEe+>JbfjdcrIDR?$YDnE4>gytO3tgilu%2<>E^Bf
zv$RB$GhsErTg_j@(^hoGo&@lA^DO`+=exWU@AyvxbUD=0NWPnT3!pbU@3=#Z<olBK
z7ywlB1F2>o0O}cPX~^DW5)PZ*#Yz3SzoFriaM+YWLvEL!w-{N#VH2x2Gk4`yh>Nr|
za@VmIaM&~lXUxgHiT8364x7fJN#^E`m;eNaO-~|jpWF&|FgR@DBej37AB~qRYiY>4
zi6=G47w>xm-zg1z%iyL>L6pa+MmozcnMp9g7@xZW!=hxQrIFjf`wk}90{k~~+{6LO
z5;?Nn3e-a6<=$f(M_L-WpYzEB6Knw*JDb}M87CtxjoivfKwyHMhKfwcO=PtrEsflM
zJP%ATIuV?bOX4>_2__hy?EYMek5Htgkt^~%Fu@o%EB6#$YDqA`&cu1Mb4TN9laZE2
zj>DZKv^02mb948j0g}+t=tt;21@`|Wv^3b|XT=Ifvv_D}uuIR56<GTuv^2ho|Ja+H
zz(Sy<F$@=s4arAQ|0J|Du0$-fG;EWvSKDOgmDaz3%{|ci0>jql``I?vAwm8AIAkZQ
zNXek+KHbhVJd1sAAPvs`Edt~X%Pu94U0iWPgfYINbVd@=89&DbHC5x*dPzuU%tMNt
zJnWFpATV;=j7&z-8M!xzAe|vM8fEc{ZIc-{U4=eSorH7-yGD-E8A(WI5E!{%;$9>n
zok3*h4&%$PES*t>Zf4w!h_I^74<;d<@e2p1y~!IJNoV9HvC5Fn;O#PVbI}$_NM|si
zlj~thNN4cXT*{I6kc^}=awL8wBk7FX)650_nT|w>b92l1o`7@)pOiy$Np@pMXAmvU
zE#i5Q&LCQrtKlU;I)kbYt8&k?lR-Lz{*zD7z0G%SB%P6a15KKQbOz76Jhv~)gLDSb
z)wxZ)bVz3qZOr*B0n!;nx8`2OcM{SWM0e*d=i^qE&ZuG+V$sq_4TfMAE;y<9-3aH6
z<~Nd%&M2Y-<`&i=BS>cu7`emQG?3011GLhp;#-u5l1;Nw#i1x4fDpI5k%V*xdwVP2
z21!U~@J_Wp$Erd)gC%O&$3-XA8^tv^mL7?&!EoE;vsmQA67^ng)7vuNsAA{22~diR
z8*N|3?M*^2gAYjC`2^6**b2a>Muu}#wcP)E(X6TcvTUn>gQ32v1Dz3gNS!l=p+*PE
zGi^904F@<_fax5>m_r0O&d+g9)qDY-a}2?u0y54iOtwHk);WP0944UN*`G0o3utm~
zC0Hn+=v+atNI=P%*adKe!#mdHOeQ!|K(})&lPwm|<Gf68lz<V=I|N4y=ylFzb&e4*
z(wW1UB?3k{-OTOt0!BNV8M9Qt80RdWbF6@|PA8Ks6EMy>hRKc-Fy48AV7Y(^&TN7e
z0wx;40$i#SpX}_(R@{v2;@hP8YQhAG<I5=mOv7U<`|mS;Mv-ZQ60(^RpXp3Q*OGRP
z?+~8Ic8%|-CrZ1<X9;kmUE`k-;7Pm2cM_11c8%{WAS>+}pDmzX+BLq5fF^0z_^twq
z(ysB{1eBy*<8uUbNxQ~(7ohDL-$TF{Y1jCk0wzei#^(y?GrU82g-Ntwd_e~<D!2~U
z;l&SkPUID`gT)s~TJ2!*BLrv%iytY#F}xj+*gt?Ru(X{g22bMn{rECx1)l8eQO6u@
z#FwYJ)&LV0mbF5_7^jFgXMAP)9K;;tT#1_!KVHBpXAw(2LGr)Yd4}Lb0qdO$304WX
z+@Vlue06#~GT7i;LU5AAT<_e+a!!_VHj02|e2v6B@0`POP7&}@cEQqvjrgeoHaYt-
z<}?AXIkn8~bOCQTOBi#8fX&VeywEcRykmIh;Cidrd3Y7_V7rQ0DZ#el>mwX9{9BpD
zrLAn9;LFH66JPJV2jJ|<f-aN14d*dd;Tr->XB@%h0vxA>;F|(G!@Ct{`jZ)SZ3lCa
zH)b1NxLUk?x9TtGG=%CeC|@lN$KaMUFbr>~r{z7x)8x1I=yFOql3(um70G!j-gZbO
z#c>WM1z~{A*TJO`ZZ+Duui)-)TZt!^nodVAkd=7i^QL2b0lm*OE~>}3&ROF<SQzNW
z3ly32?;YMnwb@CS$!Yk_N~k?gLT8)_o!2JR4k)2^Knb-2f~^njfN&n|fD&o|Br`nN
z`k?*GE_pfSj$HEcSkw~flD8M&Q@G@vg=CN8lVbW$aLLQEKDA3;-)unp;JSWfVT{3J
z(NBbv-b0Z~TIPIk()&e3sBhV^0gsIg=6u$;q+FNFIiEGoB~blDYh0E<^%Jde1%gZl
zb3SXlyAG#kL5dlR|4t{qzKM@q3(Au@AFO{$_*ILne|U1)`iG!w{X<Z;{vjw^{}7a|
ze+bIfKLlm#AA+*=4?)qW;Y`bk!TM(r>%ci5tbcf1w*DblQ_DFYob>Vvj94w_d~niB
z6glZV9?9goT8$c=^TA2)9n6%&Ksf2;aoI^POIQ6wIO(PIMcGL&+hQ#mjQKf_;ESIy
zW8ZuVAV|xc4^DbxsC?w4m&au%y^=jLVdqK9oDWWV_r%aHgE=3Z^h)B4I_Z_P8FkXj
z<Fb?9-2lqgKLpho&iUY^_i5Ck?4+0Hd<rMMf3h&3bUEjPlimQYhq9C2kpR6J&iUY^
zmsyViKs7&*YW4xZnegAG^G(U_!p6j$Z#+)w&vMR3C%v5hY*)uQAD#3vkC|D{`RJsV
z^_!jLoUiPpH~S{$e00+Lc{It~Ea!Y>C%swD`N~duvz+tMNiTCb)X4E4Ps+<z4T{gx
zq>U?ncuShA5LL~n3hN)bD$a7wN9!L+m*wc4)<54swaqN&e6;={a<Zh@()x$U%W}>~
z>mQz%$#Tv|>z{8p$TG`|ru7fw#$-9?qxH|th?|h*oR8K&jO)vC&PVH?dk{Az%Q+vd
zfB0ngXF2Di^$%0d%yQ00>mSC=%5u&}>z@a3-s~*rd=}<>OgSgZIiH0&A1{AymUBJ}
zbG{RhQuPxp%=y^mL;XYxb3S(IP(RVaobOqr4fPW(%=r$&<vbs6;GECGoNp6iG3WD5
zc3WxpKUjm>T_Ed%H2h8Q%?FSmcQyjpy(;bygQ7e1Hq-Dd_PT*IIJ*G>vKq{Gl?M*~
zF=rv=o)JdHINP%@+oMXe3ME>Y?OlQtS$WJc+amy-noWn<9*Z)wob6ed?a3`hS-e(U
z8NO90(ZX!+H_U{yJqxov0wc@Wo`u;Sk)7pi&%$hPFGN8ok^laPh_I@K2QAF@5@@w7
zXL}ZAd;G;PvYhQ%nC<aKnOV;EEX?+p(8+SPXJNL-mvTv1?iOZytn;jFWae`u(CjQ{
zdo=U;7D}9(<!sNwZ0}vf9h&8A&%$hvXmOUaJqxovqGegm_AJcy0+hEZ%h{fV*<J_G
z=~>S9EX?*;-uf(OdlqJUJn!->XL}ZAdqh`fIoq=^+aubT<!sNwY>(*HEN6QbW_v_;
zXF1!mFxz9E_Zbd<;#jma5`+?oS-9Y&;_(rtP@;v|-scdI<!sNwY>&Xma<*q-ws!;&
z%zXI%<e_8(p+vScyMBn9-moy+<5Swq*`9^j9`BS0C0dy6u|zHVhUlbFDA6|=(#i)_
zIwyL`4{_|9d>~u-#6%tWcM|+7d^_w%@8Cd64}}sfO#JvF5}`y36F)AGM&gL<3Zj#g
z%%pqp9Q#m+MF@40lJ8f`F?EuXA8?bxXd_`a`GNe#i%wGVgC+^T0g=fMB~5!WHjCG^
zG?u>=XLh{b1=R5xzGEHV=)o|nV=BHA9d9DUEX~|)u3>c?hY-61yE{g*<M#-6I?ljx
z%CLUZ4X`?vSd5&inO&6o$+3J_6>~=dqvIH)j&<CN<9NpjI8Jozfp4>evfx(7MugiP
zUHDFRJR-T@gX2_38sAkNe?^GfaXXGZ!+HY$oO5G|`%@^71w`eY7t5~!?5INmqvHbP
z8|&B`-|>zZLJ}PgzRiwH5Mp)gjBmSRCccv$w;<fX4<-Ly5=(4dg?yQjb5F`JuE2rZ
zsSl0n3vgU~lgYjoYhZ-K7x(>93RluOMm4$W#YU!EAImY?ITv4Vek|RyO!p+O_Uo}c
zqdVvIptKJy-mku1!@-k^&A%!5Js3861P%|7pFljL@;7`IlB`Cg(e(fdOT8MC6UQLb
zL11h><GSU<J(}3N8W4)-#OPt(j2sc0n|LcW7eDBSqhNkgn_`wh-l}P|fPWJX#V4Zh
z8xh-w|Ns6WI0Va^QL9L>9KTIE1czWbkIRDPC4f&MSl*9h58;zy`cDunXIY<GupInw
zJZsSqoX3%bIhTxd2o4GJ(-5J`+hYSB%MctA=5k#!1c!t<L0Q6_pe$idAVYANh@6Gf
zIRx*<f2SE=m*6AU5)Hv2Vcvv35J{NxWF3M-!knNiVNOt%FefNWm=lyG%n8a8<^*L4
zbAqyjIYD^{4heIvIYtuZJk}vNB+LnP2o4EzUO_knhlDv1hu|sv|2&e(b(M$UkTAcQ
znew+866QQEOPI6tvV{2$5mS~hXIpRx&itJF@x@P=v2Q*M5Dvj1Vg4>qBw@~D9fCu`
zT(U<d{Rq<`I3&z>#xuhqI3&y^F^AxgFqgC(f<wZb$7Kog9RYL*4heGt9fCu`{8uQe
zEMd-bK81ui6>!TE<}Q9T$`a<C06GMRggLX;Avh$=Sxp^+L&BWp=n$L|<|A;D4#6p5
zz73EL!6{+RJah<733HyOL-4YMxeUQ6VZI1WqC@bqgt-jC%M#`?1gC^KbHNat|9Dbf
zzIfmBF25L#_FjglYDQH^nBR#DmmxSM%q5)+!6{+RMN%DtQ^K4`hv1YjC(<D}CCquA
z4#6p5{#CpXbqG!gbH?cqoD$~LI@TdLCCnM8LvTu%--$RKf>XkrPqq%hDPhi(Is~VL
zIpcH)P6_j$;yfLKQ^K4nbqG!gb6&m<!6{+B6e$NJ%-Q8DB+S{RD<sSxL)r=nbLvin
zLvTu%KaW@$g0tI7yHk+7qTL0uE@=09RKgdn^4zHiVE3v>$)M;Cy^c&IH}<-LG&s8k
z0Zu=XvNOp8haoue&Jo7TJJKru5SKEbRnDCr8G=)*oIr=*)GB8MbqG$aa=FDQi`VL#
z%y>Yn{0U|fX_XV`5S&`&L^=egR{5@o@(hRnevgQ-s;X7~H%#ti2u`i?5>n_8oLc3)
zQ91;tRyh;u5S&`&d@1V?oLc3qvkt+jRX!g`hv3vI|2j(4A$VD<T!!Fft#TQHm$k}e
z2u`hX7q?S~;M6KF0O=5%TIDQHhu~$cav6e`waR4(Ue+p?A$VD<T!!Fft#TQHQ>&bL
zVhGNkI2J99gdsRF3m1$bIPr)GM_T23AV7xT)G8;?Avm?l4*|juoG&IGN;VjRv!&Vf
zL#$fmd`e{qPOWm@sj^l%OVqNz9i3Djf-|I*52|!d^pYEK?3;WbTlvI99r@Q1Ec<5c
zM{fX1=@nY#d=Ztk%8vnPy9%QoD?f&>DJ!w&ho;lc^Q^=j_v7#bIlL8zMn7g8rtu0E
zD#9VtcQ91q>Lpk*@^=X)9smBJ)6nW=Ct7!C^)fcJdWoN@Pb)F@&#qqf;dL>vdMOfP
z|NB-i>7Qs|^^#~{^^#~ytCt(_lH1bi<!y-D((2{?i2GMoFU5D!r&_%{86|w$)yo%<
zwqo^i0WP>=_40MZ{!^=$ja<&GSi-DFegn&s`Lpp-idKH!<M@ehDXQBIq`}!O2#_U9
z_NZ_*NH7OGg2VAsw1im@!U~r#FGGs*5+=cxmN4Z$qby#qj-m=eSm6@pi_9ci!Xy}2
z!X)~{CCs-F5mvQHmN2>0@TrzCnebm(!W2QVe_;ue79#^om|Z~s*Oo9@v@}w<gvr7M
zhfA1!5zZS}d&CmvJOq@NFbM{hFhfs8T*Bm`WD_o7vj2y;S(Y&QsJ28)n7mUhB&=`=
zlO^gBCN~`9q<W)u0|I@MAw@o|(GuoeIMyZ1A|IQmBflcSPvF~O2j$>LG77mX(GsR`
zSE40Ma}$O^c2}VTD@yI=5&-j0_)3nd&m*KGWVUb#v*SB>PEwgP-B#!VX9pKJQ@X&}
z!3EBgE^u~mfitBGoE`K?kkSRt4lZz}bb+&^3!GJ0;Cu#WcD~<*xK3H%?34x0PFdjW
zlm*UVvcTCX3!I&@z}YDaoShX5oK;xhJP$clGrK5vEO72z#oW7@yDV^a$^vJnEO2(p
z0%xZzaCXW9XQwQ1cFF>0rz~)G$^vJnEO2&KEO1s~f%A2i#{#1Au)ujG%aaApPFdjW
zlm*UCS>WuH1<p=c;OvwI&Q4k2?5tSetil540m!4889AF!!aX>U`-lb3TX5XQ1<oog
za5BQ#2Vbv8Das3+Pcj`BIIFP0$!KRIzUtgCr*gUvnT`vbRaoF;^zgcaaQFWx>y#_8
z2+7fLZ2dP8({<QU%Z%8hA~zoU5xO-#-91YeAh1uiWsXL`VtjfIUSh;1yWObz7XVMe
zXT*|aOO4ppvN+ni0ojhgXnbVsvs~L88QUwq4r_Iz{>py$mM)QU;dBg6gnv?`?2^+9
z1ul_-GHcw7k5;FtmDTwz@YDE&)oGFH_~^5oAWC&wr8>g^i}>^|M)q4t6=Zo8RX|NX
zJ2JL6Oa}~O^r@%`KUKf+Mt=qW`Kfx&Gj4Y|hd3RkOyL~D>(x2L92CyKzmFQ4Lkuw>
z@U#svAchzakxcOr17e5)5&rHDF(ByZ^ho?t4ly7w{1{?DVD!le!Vm-Ee-8s<*fn^W
z#dVl|E5^~_17n!JH-^T;<{PoytGSZ0F9z9r;xk;h4SUMC{|mrp;M4UmPWm2_ckB2c
z)1?@O(W!Sd%Z-S|#1&aG%`h4H?<nMm%W(3g_^_B+!jkzZ&|S=u_0TM3Jg+%}n$UxJ
zguzehZLlVOk4Mfle%DqWzTbctZUL-8dHkC?c3}8U>)H5IdCq@KB{Q2!W;T_~Y$}=A
zR5G)vWM)&z%%+l=aURLcW~gRxD&|@VB{L@;K)z;g^&;e+cmf<XbEzB)lOhf>GmEuN
z^Qy$JaFC?As(H0{1&?X2YF-mCTooQ(z(I=X$)qr^Oj&3Um*%SGw`3lqObYW_i?eU+
zn%#rRxp`fJrzL2vYTi%)m(%b}-&Fpsl9_p&xC>+ykeQbtzD#DOp=?BE7NgmJoy`1o
zWJM;$w)pRi#n*T6k!y*V6d*H?!N%18Yclh3tV2j<=5d+KOi(5>^9lyY%tT~TkWq04
zlF4<InH1O#xR03%%kjWk9)B{K`9Ba-CNr}w$fRI?&TsI=PnfYUI<y01W*?m<A~W;&
zV`OHqiU!Ecbg>_jnI-W*A~VA<He^yj%7CCuW_}q}`eZUQTcXLO0ju>^^RF;(FK-9@
z4WLYBZpGSFnan&HpiE|F)@3p?tGNX-^E8|^upO`)&;Xg4d2ETyd^WCQPMOTS8ci}l
zX6Cl)KINf2AF};FiOkHC^76&2%~PZ!TAo{rsA@)4keS&ETOc!EhiVUO2M`Tx2M}#(
zJK#FJJ-4(Sa5v(%v>ia|<G^+RpX~l@3bp+>nVE3|WacMv-j>MBy!-(&^O;CFupPiI
zUqNPOm#!c)Z$jFN?SRF&;EL^l&4`ul01=JgFAjOg740sN;doeR!s44xB0=se2w?ZB
zNXek+4#f~9I|1x<18HzJsTHEa!_FiR9ES3IfaXOQ4Hc1@1N6)RGV`~PqP!D8u%(><
zxy2}p*Xo<hc!13ODl>_80tg0n0*D570uDixXE^-#9wNf3Dw#QrRx9rW@E2o%%*-1#
zKxSsbft>)pl($4?UV%&ohVtJ-i34P2J|hEUW}*QyGtmH<xfSIN>;#Mk+R{z{&l?~!
z6Ah4=i3Z5bL<3}IqK}c8I}ymDrID}`K+M7gV<&)kT7)Aq^I-@m?*tGG>;x<a0+WI-
zCLT&Q*a=`uv+IXg$;^C8%VcKWsWO?FC2HBXM<<n;6bxzQgDRa9z2sgT`z9aARz5LN
zNB*M(KZkFJ{m8^ptdw3sX6B2iOlCd}Ao0>Xbfg&>o{;`4Mn+Du-q{0Zy59syHdOQ2
za5oV&%6hbkqW3{yTlx(IddVi|OH6(&Q#9A`*l_0%wAg$UO?NFptDNiLTvDaQ!!m4V
z*#X7pF?JZPN4PKgM&k1rI}8$AvBS__vBS__vBS__vBS`jBySdmsIfc=!zI~aD9H{(
zNp=`Yvcpi49fnTXVJOKCLrHcRO0vUH`p6E$A5pbxW*6m-9foTq_imI`k{yPU>@bvM
zhoK}p3?<oND9H{(Np=`Yvcpi49fp$ZFqCA6q4bd*hS|uwngvAVVTU1(adAm@7)r9k
zP?8;nlI$>)WQU<7I}9b+VJOKCL+K+s40kYJX5{S1+T%d_2X+{;I2H;ucNiGq`~WFt
zM=4xM2MYBhri*qM811C-wd`Z*4rID$hk?<<u0=1f6FS;oKQiJ_--D>(#~QH<vwU~c
z2;n7sx~@k8MwKTE!^qRI-__GOm3R;hA6tKehtp-UuvY`Sb_;$^a`-UIz3Z6e0YIO{
zr^kW4PV93sHa>X-<`Vl=AxGm<L|ueW?{SNcF=G4I?29{1t+qwSEC;Q-hWW?W9XjGL
z>}?#Fx(nz5B)$iqkqdG5=?ECLAM%MEkznzEL&V$oj6R3;M`U+wZhQ?Aj=`hi{0adV
zhk>Uc(V<9$?S(K=H#bD~L4)%7U`f*CutPOl5HR-0Uc=z0>cRBb3-F&G>~4%b5&!u~
zc6i20Bs7inC48%?=6NHL2%n2l1^#V2VQ8j<8Jw7H@-;s+(?NgZrUfT7Lo*#bA!W18
zp_$ImOb3H|aK?vbI`T_2G}B2m4$XA_7teIsIApTBWgf!uB?m>Z^>hf-ek^$^6J)$N
z8q>Jp_;l<JvxL~BG{=w&faf#p@5muGxt8ag0K5_(jL*1EYV1<v*z3!~%44r1M~5U4
z{Iv4#lu7^9*h^eB#^I__rcD3rl5?UPg(Y@tI1A-`Wcm4L;HD%tHF7qZ;8L_%u@r6f
zRxf8bm!hqua{Q5{XzQxPUywqUqOGgFpYxbY(bhEq!wu(PeAyUD$t!|O(bkoz9$;CD
zwknsRt!u5vkT_h5wysO?G+BzaZYW%d7%oNcgs^CU#$y?v**Uo|U5d6xJ9jXDuAtgu
z10IV}pIzx!!>;tJVORRquq*s(*yG)w;B+oUAA<kRUif+hpYV03el_f^98Mo(DcYVa
z4h+<&&)!;q8ui)R2vDOwdx`)x>a({MphkW6Q~_$#XHOHLMtyd_05$5frwb?>_1QZ)
zoTtbD&EC0+$GQ}4&rT8OQnbBm6|W#%inezb#HHvN2)!1`<hsgB(e?q(>&#Rd^1xai
z>r%8mFPyj2m!f@e>Mg|RQnY<Y3)_NA(ag_Dp#Sp|X6(Z}rfk$_ALon%lBH;Sc@2+s
zDcWA4*&~yK5vE3c_KVKxm_KnT+J3245_2iqep%*gCRru+@8wtrX!a{9&cD>C&)y_J
zm!j=I)KsA?U5d6}m2=dn&;D~2TSAwj?YEl$f+t&-qV2bvxzeXg(e^w3X8?35+I}}R
zA3&F)?e`^XU5d6pkZS5uv|Z^}!-i4cBAld4(Kd|wjtA1EXd6a-te!4K+k^aS*zl!z
z11?IJqHP%UU4bUirDz+hl1Zq%E=Ak$rO1a&m!j>#el>VfUcPv>`I-FUO9k!y9Yj?#
zDqM=T;Y*RNAWPBqAio+mjQSo&wRI^PC`+VE(LgOkx)f~>@~dIPsPAzsK<QGnJ;<+y
z4Wm99qw7+%J;<+y4Wqu*h|{HL8%BM6vUMri9^_ZUhEX5mbSc`#0PQrKr%TcHAio+m
zjQV)_x)g20sBa@`rc2Q_{A#evhfC2m{A#dEhfC2m{Ayf;T*IYk8-6vuf(s6pqHP%U
zU5;2;ie|T!#p6aKsAzYAVY}~+N>nqzH{VBd=WfT{U>~bU&Y<WvjX;!S$*wn$24`~_
zT3)&AQS#JbJ^EmrdRBzPQJM|s8hz+zx*lzVnf^<pko9OAmVE@e9&HbDu3^KnPwq3y
z;syIAGuHKJ8_e`9-UzZDZNs?+fv!i}u<Rq!^=KQGea9dQ>(TsILPS{A!h<%PYfNVM
zpmPlymVNwP()DN?mVLZix*l!AvX2RMJ=%t4AK%Qn9&HbDt^wyyz2_qnU5|zXtHx(g
zXI+oB;ar0cimpf7aIQh5>(MrxYY^#rv<=I?&!9YAkG5giw=a;cN85v(YuIqE!Si%I
z+J<utB3+NR;ar1A*Q0GX*C5jMXdBKoh;%*L9&oO)69QSZG!oXMiCMT{tVa_siZIus
zZ7|c%M}VwH+pz2-(Di5=mVK84VLh5JQ65S*;d(Ute~6pju;E;TkE*Ok+pz58os#uv
z8_aZ;sAaz#om6ksY(U`RSn@`P&#~Lsh2g->?snMih9b;#fLq+v0MEPI^#lCCy&m8t
zmu{nzw^i|B*yPe}bn=HT@APXfJtZb@uWj~V_E$@{e#txC8*xrotd?%0lRt8Q0@M?$
zeT@n45`^aPP1dP}?+bZ65U>=-zRCAO3m@F*QMy!u&%(FEp1ctUa{Y0ml@_cv+<WkS
z*h;^SHr#t$4Uix=-sviE;khW>_yoD}sZsUxY>~JZ1FEV$>b{DrNeqMQ6?eaScJst6
zxJ+^9=g;CX*VI!pGAt6ycNlfG$%40cR5h<VL1&Tve%T%z%i?!+CcPaJ`6gp!@w@tc
zNhyMV)k?3I#qVmR*URE}wbJWl@w-~-^;j-G80Dw2`28zn_}^drPJ>>526C!qc2VwF
z{GN`r+0y&nDC^(5_?-s5{zaC@0;2M;_<ae>`)@3Mr$Mi$bI59D<opIDkkl<*0gK<)
z;kcFb`ZN~58R6`TuNR{f<;CxZn2w9zY0&E#?OcT~7rj?<DyMs!>A3iv2ECrqX?FC!
z%z@5)c9JuOVSI9s{4^OZU4mu~7GSz`37R=XfaCrg=Vay!@LamC%p58p<DSA~3j}0c
zx&+M}CZOJ>OVG^W0-D@g2^I<{x>pb^5>Rp{qHdWZ<jvCMP9``~K(|Ympqa%2dfb-@
zjuJ4!eTU#^0lh9=f@Y2pFw&jFm?Z*6x!ug|^8!Y@n;ElIz!>)|o^z~#v2G`mEfX-#
zrAyGvaRSD>FAyvjFu|QoutLB@BfS8Z>fra|i)_Ws$S%1}nm?<CEANge0!*Wtt=#@T
z<7X6^HeEtCQ<5{W;e@no*W?c2iEP*8j(VcBYjTzVN7^;{83CTOYjP(68EMz#&H}R1
zuF2T~>ZM(iy9j`o94;}rtAL`kYjQUMC27~>906U@uF2g6XuBr&5HLpCHMysN3DT~~
zxdQr(YWl5gPqKgo9lWTtxCBie?ojboI#_a%q}2|VJVJnWu;h^fu$glb61USOXmV*g
zPfS0F<M)%xoEy?;cDe*jE>GW#V~AL>tQ7*rxO54cT$%nE{vG7fC1~<^0jpfP1WleG
z`CsflLvW&i^)6k4CRYi#-1P`nryoNG8{A6>PLi1G-TPS1$x_ZncPD1OMq-|K=@K+~
zih!3gbP1X~Rlp{fE<uy033$z|Wp1Ync*CVj(Bv5cHoGtILeCWNj#2$HT(85<!>iE8
zS1~Ik*jD^fgrSp4m!Qc@TiHBmaS57S?~KDQluMVO$;%{f!+nfZ_=W(}9Y=7v0LN`1
z_@)5QsD1<4v`=QxwH?ewy7|61(BkF0RY!s=5UL|V{zT-b;g;kXhTn`4c$xVoPm?ht
ztq3)x9PtXpM`o0qr@{yysiZjmzDhxuCvu?iNQ7Grhe<a@*q2oEjQ0N=X&5zIWtdP>
zSokp;CXrCX`5Pm*$!tcXZYI~(JCl(>Hj`@`s_Ri%-At~HHj{N1xwgqUn(4TUT-#j3
zW8Fort=vVf9oR*#K?-p4=A#Ww(`=Z5Rhw-_WAtm{78${zar+7+=z3?AVVqpr7T<Uy
zUypymQSpvb5#tomFh9h>Fr)eg{A+K@VhGhzVo>`}F?7nd)-k8<CvcKew=VfEB6<!r
z>MpEW#-l|>-9^<5gTp3#rE1H~2-XM!Mm&y|h&|@S2x3Pfx_8MK24r{xdl#(4hT>z6
ztoDp-LcIanm~<4vpKxlJXcSDWo^a}TIQlot?MWxejPypG7?o%nW9BbM(&bK!Nn^Xg
zI&b7#aCm@_EC)9uvGGYTk`*6W!1Vz1v9OUdkrrTk0oS1?##T5oG#j};>$Jkj@xprN
zFXXY*Z)EBl644_OBDb=_>61Fv9)_6X9hu#awt4>Xj_@@{PsKwWJHc_}st&;wo)BK)
z(&Y;XauOkODXW~iC)uiFX?zv?AR+BHbCls6)CRnMatrKr<>Ed_H1p!VhFf(mKI6GV
z`}ahe2}oah7h&T*$7}sCk>x{h0s<G~GoEH@hM9RbWf(hIhVc}_CWwt&+>~ZN#=$-*
zJ`;G=2~*taU4_Kw<1+!GJ*EcHPH!4M6OLj~EnDzC{L=pgp9%9(gr&JH_c7bXXQDK<
zt><oo$K$7I1n$mON}AFzRk#<M(ApEkwyxHccBH@5hwz!$v@cQy8u)W`)phtx{1vY+
ztATswu>B0)<|Mg|b!L)Jb7I{uPMXN!Myy#2nOAQZd*d_F;;AjBEQWp)0hcgvHUnGr
z)ITBM8GM?YSka8rf#z0=3>*s4cPqAb(JZk?850lTRTRyhr;zBE@MU&9K9fGnyxO&H
ziFFU2H1QG!bZEeEI5nZ$tx4@X6`~I8*NJtHpEU7Ers~vGO}Ll8L#m0hnW{?zuV}@z
z44;W3m~xcqo{uW5DH_IM_;e)AKET*$Gx=?_MdxnY&Bgc3?YBdov$o&Ih#M0hz{Vcp
z8_q!d5$IF<;4|@I<~2qO$hX6)kb!k9b*u*7(qR~1#AjmZCIpVtKz5B^l$esIkJlD{
z2(5h$K7B$cm}F-7`b(^P>7+iP6l`T?rs1*@>n=Wd;=_EX`^-kZ?EZ*H<Zk?k^vNT&
zwVB*aQoV6f-!UtV*fwVJM)aA)y8BO>{7n|tuZ0<tCa{vT%<M5p4w0&5rZef!Ot4cF
zbQyxSe&zcJI>d?HJ=Sox{@D%y2RX5;0k(OWb?C5S+kAm%m8{s-Utf-cGn286laaQX
zp=%UOS-1dIIW`%aFdi}IGv>Ku;_|HxXWOgM=p!)~nkZa|yUjQs%_(ERd%$OEJ(9eR
zTQ)5=*Ic*uBpc7y-8kWJoG=0X=zyfWa=whD=P~(f$o^eT9$$l#J{ub|Ew-1r?i@LD
z6V5!9owb7%=yW{3J08S&Kf-6*^8qZx@<AP@uc95tq6^^Dzh+0nv5JQA6O@apXx{PD
zaJ(1qkI}zswkDubPE=PEUy)?$oLw}@Cr2CG&O-TzgynCm<=2nHQV2f%ug%bNXCVHQ
z%AdOGzs`K>tvmmhg-_>C!pxc2&^I1NHDX_~Q}5zQoUs|fYf*t^_{?|(z!?vdRe<fD
z0hsY0_*#yTgYcR0V}OPU`0>VP#?1gH;^6ZH-v)RD2R|gZ6yVs2*cicQ#<>8ANqFS~
z%w);i#{$FH10l2V*`XRBvF_oMwlCn|9E6;N&-Psaui)SXCYc~fo;_*D={V@W9+yyy
z`*a2>KhVy5$Hq;If6*}4U38L-1C#F*{CAi&{(Fga&*By?+)2;<@kh=b|Bug|`ZL^q
zmiw_X<EI;2EYUEgr*Zw+?b+-_tRTj|Zm0KcMB{Fa;29(F)xH%5)A-D21Nb@)*5Nag
zX}8}IA=Q2O)j-JhdjR|b;0O5ZZ~%Z@lF`2wzkaQ#*HOq-`;F0mF~UY5>@*EC*IkW=
zqkk5j=&ca?jVKfkn|5HMe<kAH#Y^HBAB#i(=M~2G)<>*=JyP;HdF_)@>XX9v2$Q4>
zmCaT8r1aNM(j;RviIgxX!NM@Xo?Fgi$rR0FS(wK;sO6wM%xyKnm%{|7d^EwcVS?{(
zDZ#9%n#0puuEjxNlJ~cqWK)==6~nH9?lY*W=k#kq{hB2Hv8raKYl8V(&SPen<jgH6
z*|44F^6jvgk2TqSVS@X&oX6=qXdbU`Imv@zk_>*Hw{XD^hOgW4TTb#um}IXlC)sC~
z*5&vuCpkS#vVO}+HiSv;+H#VGpV5Li;Ml?yosJ}Y=>DQf@B?D>&k27s8t`a+@@Z2S
z?y5O|ax^Am9)^()=QI4xmzh+!>N_vO!wrXf2>g+k__R^YxLNd85PMSx$s2Yv9Q?9i
zkj%$i#=~zyAPUDbCgaB#9~}?BrQ_jc2sj!a84qtx$awfF;LGtDEnLaJBxLjKGj||k
zPAc&1(QyNRF5xu+?+g6f3xnuY{2?B%m0;Str4rBL7ku12jcVd>;Md6b5f;d?<Ag+>
zHEY-!(?xv7%K&_$)@&{U<}i>W^+{T@<AIOEM+e7!2^kz;fq+Z#ne+e$F_RNXHe_Pm
z+7;m-3a6qHiFI$R=<k}N*Kkibt~ixfgP#+<n7#C3_BN(2LAvdVax3Fe8r+<NaY-D(
z?2K2l@nOQ49kDUf52j}yii_kY*PPmA9RBkY8=kOsxdR9Mcs(&^_KP^+C$l;|JK}HV
zx>K{4AdH{dlDCVC!5lxSpTcbI9V{Z6#=AZERx;-;h@siq`S|7F-(Ti{Q1EZjj0~kA
zP4WZax$XdDE>3?Fz17osOnyLOsT`MeHx5O_r_kNNbY68gnEn%VH(1uE*4>DFOw7VL
zex$N-JRS_Sry3jZ7>|aiY{*qaDjNi4l?{Tj$_7EET2(eq#_3te*^+ne(D}`I_=r9%
z%6l2dB^ajFqWL4kG@h(%0Bh?ML0M&kpscb%P*&L>D64D`lvOqe$|@TKWt9zrqLC@9
zZ0yZCgobH6E*qv1tf>iAHh2X_tR__1ATqJaQ-lA9Bbi)RtC1<IY;gZm8}dNe3oRR_
zvGlUa#zv$n8>X=>)}q0fpK~|9_z5#koA(0L`jN`UpMWC6G#-}?(<FOj!mi>+DjU=B
z#;8`64M|+BDjSlvT2(f9T&8P|2Pms-5L8!(DjPpXS!KgCp7SYGHa25nplp~{j|ofJ
zFpbW_daFZ~4Q4$CKvXtZ%{~B8*<d+Sf?cXH8vz@j4=42pk;;bnsmn$x8_Z*75UFhN
zyxGAZm5m@$*`U$W++dK(MleWaBk0HTOO*}gf~6|{6H6)i;(gEEgbT|t9PNDs^2;--
z!Z3~TL8P)F>4FVOWC}I_J(ih4q_RQe1bgxV!3H4mf=Fe9=VgLOWn+VbE*@-$6ja$@
z+?XIz*|-gH6M{%(gK>R9q_RQJS5tyWWrI(4e-Ig_G3Csl$jb#AfN`^eNM++;oHsj&
zR5qA$PH+y^Zm6=s%bOcSDjO#w<$z%tyMKjY8oP9bVcMtiQ<pYxLjj?PZJx(zlO0*^
z1U=K`2JVDF)(&azMpT{wX%XM3I~$?wbrs1O6x}#_u9Ga;83)qf>=pz#e2&C(-Jv)D
zKY(~2M1(K0vb`D&6$b3pE<=joT;5Oc0|<;D@PNP%U@grc65o(JkFpjZO<Mf_4%n-`
z$V?)8H3B2}B}$?A29X^^;v4wYCO?4x#B-fiRqfSi2OdP?8;mf5NPL6$&kQ2*4JLGg
z9yBn;H~6kD1?yO6@B>)qSwSSefnf^z#M2mJQGDZCRAp{3NPHt0B)$<065j}FcnRPK
z)T6vr!Sn2O;0JU8ogPHu8!T^qFi3nO*q7x+;v2yr@r}S|OGn}x!K<iyS$rdi#5b5H
zJpZyEv1qw};0F-1aKRWU68A+ovR9jjfFKgzATWYRe1i*|;0N%1#Y4#k`~bEzpNJ5v
zy&50hvb`GbRM}pQC2HB?xsGRt_G)SIT-VCyS2`zp$z3>3n|w}N`5;9dnV##?<`eiH
z@Lb1?;t*#<S@c}T2c~SVwgA8k?bX<$MTjGLR5iPWLyurv<2i3P^3+La<AT1^QesdW
z7xbN0d1geg1J-8q5uP@ArU-Vx+Dwi^Ycn>z2zJ1qog9bOW^#N3BH_=D$JnCg<3($;
zKO@8c{)RjK*?kK+Np?~0*l<4>z3zWv!=3)@63AN$h|0r;`)w@mzp>#?e|E<*UuNX|
z9ar=W4y12=XyhNjaoO685zf*0N?^n*DO~w>j67Y~m95Pf?c9qHDn1TQM;CTwYcoa<
z<B&Sm8RI=#g)#j>=z6jB4<kmc#X6hWv3`g5&lC6z=aghvJ)^hT2GbvWx|ZPa_!a`X
zWl6Iq!Sv@KVl6&BV|F*3ClG0jSc#+G;pi@Wda<Z@3cf!ZUxShQ2E_ca9Lml{*NUT}
znFH*&MqP~&JwH|dkskd9{_~R@MRVjvbadlfOl!ii|B+b0OksiZa@2}{XU@e_qPt&-
z3YQh}&}GHOVTcBqcs7z+D$N&HPH{NYA3Sfc7b0C;eObiSmjzs6i!fhEEdDYRs9%eC
zg<lJhiCKjBwE&s;R33+9Vji1+!5c90YmqcVGO<Iy79p9~sU#B%i<7M2Do(Q!aCaV(
ziM^Nkw)|F-WkE?1U;mIy?3>j>CJuj$ZP^W>Uki|lc`<{?#2$b5K0+pDS*AykK9GqC
z9Pe7RD#*kHo=0JJkckPz&2^bfTrFhcR7570Ye9K3eF(|KUJSPpWMZCdcwBA<nV7)z
zD9jErF@fVzm>pzd0?(uJ5Xi&?8IQv3AQKa0JqojfOiWPk9YN49pvj{!JIKV0DMliF
zA(`0Y^dTY>dtb-^d>S%wilkBwmE^iUN+#BZ49UbEh1o$SX6dF^NhbC<ktvgjtA$LQ
zipa!a#?_xdCiW=I9+8PX3bTVuEZG~?Cj0O|A`?s6kW9>D$D=Si$i&M4JdeWcAQKY|
zCKG$F@={)v4p{GX^VWxCVsFA~fRIe=QJ6g<6MGcti^#;@ad;j+J(-wwQ-zR!j!ew+
zR3YTQLndY}Pzd2aF5D=aV1P`_aI`nc#5Uu%L?)JWq7d@Wk%@VpDujHTOw2e{2>Cdf
zm~pBQ@{h>GOsNVX|A<V?l&TQ&e}PO~Z3>x~WeROW8eiI7Aj8q_TnMxoQ2k$%iNoYV
zCg$;coHB4Lakluh;8Q~~u{?EgLteq8Erzcxlg=&vDKasOQkjqeGI6z#iL3urGVzJX
z(lb*0M~Z4#)qf+Im~~c}5R!@41O3mEiCLb?g#7!+#LV+PBgNl2l8L2}8WfXEEI6r{
z)Ly}#noOLE$i#A5vo1oDOdR4*MJATIk+>@-eUwb>g=At*y$tWB|HIywfLBpuZFk?>
zw{PFv&dp9hkOY!IR+5mg8rfA;6jVgq0fVy3CLp4+y6?-lMa3O)<8x4P8yS}wN0}KH
zbksoxM|5x*Wn9Kx|MxxBU3H_x;dA`H`Tyr9&r_XxPwmy!ee3i&b<SYygzih;1hB;)
zItbu_<O={>{Xm(R!`<emD--*HGBGu2wKDN5C}Wg~w*eVtVj@ge>if#XDN!a)r707$
zG328%F%~hdiBOqXhVo;|#KnOrZAz)-qjf|nD|J!IN~}2nWu*u@-Bpy8O45{-5>Qt9
zE1RRT(r(C7YPnhXS4`d}qjM=q#pG==iV9ehC>AG`VzE*=^^ft+#umn3(G8bC<<zIj
zsUN7E`cygf1C>*ss*!%6a_Unx(hpQl{Uyv6sGRy#IrRgTQ=clQexP#dQ{~hTR8IXH
z2?CW<pDL$*pmOT>BM4MZeX5-Lfy$}>7D1qL>Qm*^4^&Qls+{_P%BfG4Q$J8S^($Cg
zpmOR{<<t*UPJODJ`hm)+U&d^K%BfG4Q$J8S_1_=}R8D=WoccddIi;C7KV9Y2Z>4hT
za+Zq&l~d-`DyNtFD44EtD)SnuoXWh0DyK59p~|VuYp8N6^BSt0%Djdur!udh%Bjq2
zsB$Xv8mgSiyoM^LGOwY^smyDraw_v0s+`KaYL!#>agH#KIfTk72c=a`U*!n7z(SQ%
zSzw{csVp$9a_ZiU%*BDqDGO?q)0Z;ws~@PGzJ|Ev2P&rob$+07`YymYKTtU(SmdXx
zoce!eHv*MYKV9Y24^&R+di`eqDrO5*PW?dTl<lnX(^XFWHdRjjbd^&-UFFnIS2^|H
z!1~iFr|!ELZ-T$v?6|x+k_xj^f?b6(@MaPWm4bDw;_4z!k5)Myi*!F-<<w7CIrY<3
zPW@IYr*1oxEbhnAuP$LN@=iWIY|fQNp>jF`^M5U<-&Z*$4X?mHc<-bf7L%MCbWVxM
zW~CY#3xn(frO@rjCC%}@8;nly=OHe#%0$~Tb69*g?47$cTbX;ysgZ7zt;~H=q~Xnr
zOC@4K4GzUXnFH<i6Yzpf@axSGB;q~U2mgvbuSMcHb^&Qcx!|EQ&kexy1m`J`I1zQ8
zj4UWNgE@OM@dCROY27Ko^B}?F8~pu4EbnP>Xm$&gjFf%)dpmHS_BcKZtVSq5w%M|O
zDaSVtZL+L`5Gq75a;-2bHvykYny6vkC$#(aw5&@JDn#e<{y3|?Z~)G9AykMq-vdJX
zHSog-<)SsYE|EmOkAeS=P<acwY;O_<C35kostG-TQoN0aVfKp<swVUTDVL<T2H|@J
zLiGe_Uv83H7`b?KRrBN%0C!`K=n%{L%U~3O%HO6UQVtyoeH~D1pko4BSJE!r+p^{(
z)O;zla?(!P2Oq@{YQDwS3VTxz(k|N<LMenANAmR|ZODE&se@281-Y6?nXo@(0SHx7
z>OmSv(#5!(icmEbl%b@|JOITIs;1U~v^Pl?jD%_vLe1}3`|B~%hC(#j525Do?8WOc
z5qAKeiBL5ibMtx!W_#)&C_W-oO~>54zB@^89t;yd2vu{Ks|!hY9)j<s2vyK{vR^MF
z$vG5?qoYy(JyL%KX(jl`97CwtEd6LC?JeM!5PD!yY;MPe-lG}yZtlQn)x?>wQnYz@
z#*aA+J5YqG5tjXz4DgCp<5)ah2sIzDx;Ny`eg*s<LKXDz{+i?$hN*|+Y#2h-1k2v)
z=d{N{1UgM9n8vNyBn>|j><&WBHdeK@fV64A$0Jltp9Z@}TX!ezCE&}2HVOBAYb9w{
z9F6@XLe(Ll)RD5{SgZzws%G^5EqOlg9tRUc2vwlGEk{f;C!k;BNx^-3JCn~&=J8mr
z6Y+KJ4bEBnNUZJ|MqZ7?mLCVN57q43OOeP$M*@6Ga7ff{JObc+W*ZQR&Yc2lp`skS
zf7E{ESfm`lY#pM}^^*baAZUulZbnMa(W5PIatD6qhaLew%bf?Yynm?W%>(TuO>3a%
zhtUnt1Hdz5^~^ua@|GdP**b&Oa}avKif+=h27KRJf$FSdEbk(uJd&Pb*IPYDAmLgh
zY)VgvEJi=ZK&Qa!IS%Qok^c1#(pm9Lq_fF(*yO3chfSUrG+CRT!X_<@`2iFenVx{g
z*yM7or6#05iS(YM5Glk>oE>Cbfh>ngug(jqpki@)tEhr4v>^F;)NscS3gUabboZ%N
z1v${KgOtCtN<n{mdgD}?FIuH6M#?&*@E+viQ=RUHU1#+iJ6;X3F+Bk{0{wF?ZaLkx
zdR~ScocGbKa;Ql-1Cy{G>6<wTTM*%FENPWdZjjv{Yl6)+O;F>#Cdi{E>P(a#ffU}J
z`&yM|%1WfL-d9_tNEdazj|6$XX_cpS+Z%&CUD~D10klwgE5iP5LmuA9J%T*uMt+VI
z-l;=drEqS2JZJAA<)l{istH<#bU4VAkzLp-9V2UOLW-=PnL*@{R#~J9yH_xEi;;&N
zc)3*vxFA*q4Q&5jX{+axL75DEl;mwU!`T$H*ds_e59xdW(<dXlS>5^J-^+trf)q~E
zgdf!V98&nmENxXrZUm+ptLb=^enYEt)h?cgn~}^xKKz4<HzI{A_>a1v)pI*&pM&;J
zKwIK-5Q}}Qmvw?_Mz3{95Y!`Qr5yf*q~uU&%Hf`;_e#DBOKs9OLA;P10c<%A6_?}v
zUz*3)^Lo5y*CCYSg<V=q%6CAYAyiQ(T7E|coPfFzYCdCq-R1XY3Gf_*s*^#<#oe-A
z2l_K}ZDg);`Mvok@OI{!1xhY|fl4P~M~P5%GG6}W1tg6C9756r{7zN)?B5!|>l6ul
zj*1-8YA0i7f>1Sw*$PRz3h+`zVzy4CJqi3cX$vj8O1k<w(4Qn1ex|CWUmd1Ekqn_~
zA$n1r#a<i=I1-^(du-Zxt2o8HzlTQ7ka=aMKF8o!gCX;H+v_tC5r)hecCt?fA`F=m
z0mdT2kU1G(Eg}q=Qvs;9&X73;U?8XrnI{4~h6qFE2>`Dl3q$5?+wId8REA6(rS5YZ
zs0^92>}2035P1**TY`ny@jKQZ0RkCNq9^V}1-K+I{QRrO6ttG(>`;WG#Wt}|uvHGF
zH-S({$%}UBf9=x$I@;T%|D_F+@6!K@!5R#<{ZJd(rT-O!HJDxcU%T|bsD!mk{|mb&
z<GGZ&Xa70<FVXqxk$|d}Rak<5a)>+Lxs)V1#2r^UU!k>eYIud##*O}0Xl-0l)AYYW
zYvX(khStU<eh&z{^uPYKwekO?{?|JXK;HItjQ6W)I;{ENzuj^fHo&6mRc3c!`~t8C
zOA*RPA<NYuEJg@Tj#oB=I2N055Mt3y(=0swN{6c|S&PbXMuW98VVu-n=A(A8MINy`
zQeEtQRJ|ENnvB}*+2lb}Eo&cyYWa{AQ_8h9+rh|D+g8~UFSJG5>=tCZ0-?4OI?{}e
zSd|<Kn}Jzz9>u{o@?l^K>=~lxwie&V%7r6juj`~IGdi&&sc9&TP)9wt6Qv(>0gp$h
z2W3`A>ViH8w1E_`iL=W%v`>IOAO+S1=9H4sWjZuK5qipL_PL1$(Dnr$h)}Z*l?=>8
z;&)(e?6W-<xDW~FBJ>=|exC221KKZv??R|~1qHtIktoNFZWgumzan81g4Iww6^@ZJ
zWvpPxVIAGBtH8IJdaI!sDLv9s_`#-e9f&hE5o}*MZVb(@OIdv4LSgXMV0_1*D-0RW
zXZ23g#_JPm;Ca-*dn}vW*FP}8fcrWHQF31%=97P2XHX+9HhIQeE2_AtsM4^DDo0UK
zbuuTa97RQya$Qs@*F^*6I;Bt-RSI?C>6<cC9-hA86o#j77}uw7ssVQ5^v!T&dkH~~
z`S0NL4cpr3(>Iw;2fX_+E-|0Zcz7PC8MSCfQRgBdJdeY;Sm%tTTjz|WTjz|WTjz|W
zS?7#3BrisBTIa0Ce{suk10pgOv=^SoDa9%Z&*P}^P@xXzabzNsRH%!kTjz|WTjz|W
zTjz|WTjz|WTjz`olG^ln99FFr>R>*7GW!sm$6;Kb$05*;qG)m6vU7v;I7H!joRg7F
z#-$bN;3(=5Rw^3#$K*1u&*P|pQK2q2KJhqG^m!c41+8<kKJNuw7=ns39X@ZyQ4~Fw
zhv#t^*XMDhdQ`&2qZI05Z+eGd*$0lIB=f&=6a|5dIgdl29Ywv0Ug+~UZ0p}YkCPpo
z$6?jlQ53t`hNGyyE)J9Aw>png5T3_j9c?*^It{%wj-u$6+Bk}e;dUBFQC}eE4jo0Y
zkoa>i%t3)d9?A-B)h$9&is@<Rah{6d2?)>QaI!2>sMF_h@>`w9$!~QYCqF!o!*WWY
zE(YtIavmptD5iktahRqQ>SD0YDd%zW!}B;yQwnu4Sm%`UIQiju96s4?If`PMaTF!z
zaq`3SIIL4C)bTtHhi@E3@$`W?kHaOOb{>aI`oDV~C)44w6|+b@U6VHN0@)X=^I~)&
zMM9>WzG=tbsP>qiwCp5>w~423q)MK?F?mp0PT%mUk<&MPMMo@;cr0=TuPuH0CXVIV
z`t*(V7A2=|^0^=2=^OS^Db&Saol~8@$&}MKaKnR&Tc5ts-lE<_lJOQrWV}U<K@v{i
z@E^}~NY^5kIenwOMR5$qTa=t2%x`u2CchFB%+oh~Gq>d}3VWD9p-!K^$!~S~Cco9`
zoBUR%Z}MB6zR7QO`X)a-eZx6Y3Ux79=j6j@yhRZiZ&5_XTNIJ;7Dco^KRkWII&u1j
zzjI{#WRh_DhFDJDaBgt=hL~qzBt8A~jrJBLr*HDVclw5JCpmq?YH<37|K#+I!aH~R
zhHVS?#X{O!6e)80MiwX5B~RaEI(#bS^i8;sdHN>vd#7($QN*0S;oC@`zM%s8j!xfj
zS)`r5NwszQh7;Q5Z}`<ptdavjT{hx(I&r(0*^<+?r-N;iX|$~_?{G@*EIbh;IkA(G
zoplA`nGRc%6FV7SrzB2}Ekl{eloLA{%0#9(n9WcoGP{st%g`n=hXW;XVy7$vYxdvv
z50%7;ombI^6syAt8mS#8b}pCNE6~=@Ya%m=6FZ`S!v@0kaAJpNW&WKLJ4u|_xeaxs
zSdrHg7kYM*`vDV~-vP^sog_?TGQqnMls;jOq~wE1!7iZ4iJc@&WHQ<N68Vn(LB4&N
zk0vscFp<gRta5Cy=h~-ww9uK%!cN{kEt_WyVOe$^!08^3&-hliyU0oOvTZIWtJ{2{
z-T~_FqYitzZC^GMhJ%r8w`@Ue<*NWM!G>Nqxh*ru$#p-D1t;3}Vx2YVBP&bltmFW}
zb-m22N2xX{k*P{ptE21!0xU^(ta=ukK3HY4N9kM#+j)|!W*F1=w{5%TGgh}3V;3?u
zkg+Ei>xY<}53;|s?Tb)FEreNLcHl#3)g6U_*dN*>ba!7shI(E|ityy2{f}tRzktv{
z(D)u=y~ZK!I*c5DJ#J(h&)fFrNT`(|JTDG*d-q}2UQGCybM?!{nEGW4M#v(4X0iO0
zHc6vSw7jp8+irOVS^Gk}<x0ul2~1HoLO(K^S0|WtI^blIz*b%(KW3K$ol6STjauZW
z>1Lpp5&Cbq9ChAf-;C<_Sb)OC9NH@!+6}R_XsKxhhy^EN8;h`KIZ~^#6o<GNz1g!b
z2<#Bqz9qcdb|d<IKZm!>=CA5D-1|w=Z|;=X?`54iz166$9HB2dxm;dIhX5Ubz)qgA
z8*{G!Ivrs^HhQ-jbJ`okfDz|6gC(D!2aQO3Kvo)LjXrw-rgcno$u=~a>CD1C9N3B7
znTOMHD6Ve9JhemyKEae`JIX!3N@)&K{>rI82G6HXIVM+b&7e7RF^HbF{i;ss=`&@p
zaOe#=d`bq(1Jo#SYe*eZxv;UaG5?>S+|VH);cLPWuBK^7!apQ&YMZ#8?!~C@Mvx^{
zz5p4xr1Uq4A-q$hPQt6%ZlNX0p}bG_=wTd53sRzWyoVKb^hVZsHK;G4z84YdIV5I@
z(OkJbF4{yL!grCf4WVg0fHl*yz9m=-&<-FU0h@GAAQqe#9m|rHcJ#X}WLgYr6*5#H
zNaf5DTg)u8RON$^G5|p;AA`tf0#-f^ktql;#&kH~B38bVC9CXc)A67zLE`BMQZbWb
z>zTYzRs0L2;QgU0z7vtv1g!XRMAjqVPiAWz7HT$t-Lee-WL3Y4<d+b7%?wtxwf786
zA`zc|yJerlu{;=(&t>fse#1yUpEdmNSR4%TYTMg)3Np}=7m8kwC&96X_a&QoM|Y66
zgU&;Q<5(g7E}CmTVWb@*{Qt!7b-M32ZA@eZmT>s-f^pcO5Mv^IjGWMz2!S>xLZFR_
z5QN4=xZk2Nkt+Q6Xi?-E1hL+OSHW9|)0hbT75-;FUKnE{$FUE=#|y^w#|r{&OoSt_
zv@sDPe!QT!<2lGC<4QLsaz85#K3*`s<Bu2Q@$|<F&IOH$us&}CE(}4%Sq{Hs7-J%I
zv>1N8VElU@FS4A`plM?w2VlVm#zZ7@U`#}AYG6!6-BX?hjQvd<TWez?P>3|fL|#N&
zJN|glwwG%QKRnu)NGX6eCNcm(8xvvG+L#Etsf~%SZ^oF&FcdPzL`DM*)y70vhcPC?
za>kg*IY6VdF_Ed55@Sq+-y+6pV<P;Nag;VD!dhTVg#TEmom@EDc8|q^{Q_><JR}t|
zDedD0)3q@XmN&xWHR!f6CPHM4i4YlMA}nW&iSW#kF($$^V@%{Jq#0u(Of$wrXk)+_
z6XBC>jEOL(F($$^V@zZd${AxK%xR2?aCpX;$hpXAK3;Iir+vKOl1}@0@pt4+^Kv~4
z1Ktwp@FHrD!L`U2NQG;WEQcR|0%u5tjAuDq$Z{v>l`8E{2rNT+<k^6vLK3pX`E|iB
zK;^1S%TAJf!ayDuNm3;jqsfDmN)W`^HP@IthxnYq=c+lx=r7L)#^7v({H*z$K?@t&
zm<WL}Cc<7CV<K|r(H5s5%VEXlbH<0PBs3;MV2p_n8Dk<7kc7_}{P!Iag08C18Tpt@
zZA=6|g+QS(5#B#zOoSPYF%iD2jWH4S*%%X<4`hsq+>aKGF%dpG&Dxj<(KKyLglMid
zCQ^#_j4-(o$QTo0d&Zau%dOPLM2J>tV<JRrv@sE)b=sH+(Ryu6gmvO`2G<drmPx|r
z3}QAe7@sqUhlM!&oG}#yZA^r~7!x@K2*yPCzG76W!RHLlG@pn7tIrvHc(pMR-YIQN
zge|JJ*N26)F%eRV`25P^#433f@hoQrMpwiKDO|`O3;D0Oda^*llu7GppELM=(w{T9
z@AtmKaKA4=cGCpNuCf9yLgRRL)?ug=)=W@HgvRl&QxfMVh<KWpj(D1vj(D1vj=1^+
zvD*iY_z|#Qi+GLTjq_@N>_4kdu~yz_qD=}pc^4DCu8^1aE;exXW`+E`S-pS)r%l;;
zk22>Lm6o4(5z!k8wa=SL^jC#C<sCxwrb5Mehq9Kf3YA*BU5UhO`#r}ynO*xM8~nSI
zSB=|a<(2*t=mUkE{NurReCV`iJ}-X)PH1dbz{d=6T(SLG^T$qS=7<etqeZR&?>tb%
zyET`IZCl0PGW8HQ`zj<9-$L+=%bmVe{3?6!Yygg7jnBC<>BUt9&j%?dv&;(tc%9%y
zxBXSPEv229ZMz>ULv8#H&<X3tZfU^&xGYyC<#1U<X2E_pTI@D+JjS)%-<?Aq2x32k
z?u+}O(5HT4GKeREFqOok*vvl_@i7n{B=LC?Kl2k@7axGIjl}&){9F+`%*N{(q5K&V
zzw~oBOe?!$Bl@-oJN93LN2~<@x)dyoKMQVaKzmKoD#=k=6~#!n90{~95@sF|WKLjc
ziiXV5#a5A3u{g+1KRZG8s>_1xIxFh6swo4t_sVdeMC#XgrtKE?NzK$=8A;Ame{{YY
zq1*I{FnzvPMtklBt^?r`gc|VuqcSp2$9?<^@I8_yVL}hekTrDR9K1*oYUV(h_h3a^
z4!nT0$<5FMJ|rWPcWNUDe?aJd0k|i7w5l;@u4R2g;%A(?Lsjwr0`Urj?n&OwF^V|p
zB<x@iY9<_qg?X4N{v-%%Nj!c&dNfuM8|Pt-Aas9<bsnx-zZrzf5GuA}8aM%C5I9jw
z@V0nzwwn8?iY9XSs!!&C7YuF&GFi0~P#uH4pPgAZv==sM2;Nnx+6E9A@GU6QdKaT}
z;4p!|^TMKCg<O;}UxbO~->8LHnm>z;M<?L$no(=IzHc<m-lLOd@6k!K_ec{iEay7T
zt<mQZ5r2@*D*r~tX~M<1J&$zt9s3PL#6Axt&dyB<{t$^jNaq%%Q<z+b9M0<4J^W`m
zPvzj>9Z?o@&S3nWj+C_dPAFd<4)iZsG?A5uEE<7k(Fin)M)2b-8b{g&i^jtL344z}
z3ya2a?G%f~QEGdSJHeu<ig%htlj`v!!8h!`V$me;f6v}yD;ACAwS4)1kVRuVKZQkO
zxqqKUV=aNbN4}xWE?%){OvZfwOBPM?X?@?FXVF-$Ef$SwZLw%f+c_4EId_glW6u9&
z7A-I_mCmBE7dv9nNXMPnSr#qGE-V`3J7&@N90`lY=MXF!vFw0}e+rAnrhaA?4Mx_;
zqVb=wXsW9_V9}({KY>MKpACyP2Izm5MPqwEH;cwP(^)jmMLLT{oX(;V{{$9|#R7Ye
z!lEhs-(=BPXy;ipjtuL5M=TmE`Y{$QlsI!mXF0vFrB}WbVfK-GY~kPz0JX#_q)9eW
z0fyN}l0*eKF#8y){muhDje~>PN6o<{z7dm-JEQhnYRo=5*y@&v5V`FAa%}6$uCK&^
z$_C&XE&B)*r`xcRqpeukNuao8GjWZVy$!lowgT~l728|^;WUKE>(I4ARu|R|A@W?n
zGV!xmb|P}yWxqk@NZCTfqh$x<>Xa?UHCDC;bhoS=*Lc|rQu|YgC(5#L%_#c}lw{e%
zi2GLTWs)F7ZkK`f*g)7Ggvc8J%f#$s*(IpgE;|g@NSTcy(J~KLr|c?FVrBc|>Xr?|
zHC}cf=$;jOhxI~;d`1T9Wkp^NE*~JsW)Nl{>330^ePn{S1ebQ$H@7zDXn~^5J~G*R
z75N7IAYVE2QHY!YAu^LQKf}w<OSbnG0Eo}AWCzhlP(H_!yCtS#xj9zmcI5MuoxHo4
zZw^3m_Z-Hp<S2s9E?2CRJd2=63VB#IqmZNfDWKVnqH()^E{?@IfGzZ-r_4b#cIHoT
zCwwIG5y~kD?N!L+ivgFAq#OekFX!HW0kmvEtC%(slE=Pz?A<k>oqzxVmff#Ce?{Iq
z8E!ieD#U|O|BmeF@4y&5hEOpd-ho6nxA7DV9iak3<2|~w|9dThL=vH5#x$Ia7nbyN
zz>^UwUjn0H?<w2y`+--Jc8SokSv2=lbPl0v;_TU$onhOX=HrKD0Y*kQrxkPNf_g?i
zzxpghuGt8c3t0M0QR2N9_-@i(C+$L^Z3cc0p=Q)P%R2{SPobh7&|^N=a(k#V=rzqq
zx&ldEC20)L;np;r3{?Zr`k3ri?Pw710TJazr?+O+NtX8r2=x4zR_S6?a3?B#8cEAk
z5=;TGxifGbgJZ;2-3W~A>hxk`B4?u5BOtTbL#>LPDaF8>*K9=kMx@g)%lBF=#|N=D
zkn~AVl!Xqp`?EoesBSKjlStO3#_&LD%}S8jV3kU0)lW{u(@1B7d#4x0Az~zL3zEkF
zAgR{EOtDtZlp47j0$Rj^=Anr!hYw4Ax)iZzcnmeusy`jKkRe`cd-b7;G>w!tgq{nM
zrGCRX$id(jC+evkA8N=qgw7HC-4oXBKA*kKd*Z6N-M3JJ-0n)OEB<u{>%2>+x&ZIj
zb{(2AAG>s_cj;8~_bd=gj>MACVo8EsI@R*=pI`EgBJM7oYOsU(JN9v~OQ#y|)?GT)
zyL761Vjbj0lhl6KLP%<HD}C;@h>1e${~J2hcY#L;JQ}3wM}xK1`q5x*%P_dmqk+T=
zvQa8cKN=@mNe?uNe}0b!DLP09YyV&HXpo}Igs{Dz(W61?K{Bq|qXD=<3;NMN;?aOP
zw0`uDcr<90?}r`@sPbp;DQeH<3oUOgYPDNlCr2u}ynBiw>mUeD8WGBidLwy2;b%y{
z9Qb^M3i6_Za{mF+9{@Ly1g>*%HgEgifZiZQ&ZQ2{Bdz`EU<45=paVN(H|o#s12hz&
z@-p<G3M|DktBQt<kXe3-S-1KnW-L&R&UDzzZd6^gOQiqH!Ia#Lbi3sWumr0ACGGh$
zJ{6TuL?|y~|4R#RMf&x?S0G6LyGj3F0eqPx^uN3G{~ti_ks|%?F8%L{esw}%|I4NS
z2LT;`P`MR7VE++UJ!eCOL8sX%iz?iXwdWwstn@&S$gF&hZt`#Daxg1Di)b!g9JkB;
z+AjBN|KGb`qbnb+F`0+=j@Fp00ni$gJL`U}0fmglBu_pXjmiIK+^=1aZX1nBBBL=$
zWHcs^#>>fw<F3bE#%N43&4}Z;&oLU4Of%v*YEv4G$&(?%HyV@7X~c0%Ga8fB&N3R4
z%xT1Nw6I|`CKn>7(U|;k_iNO{Ow*VghXJQ)Om0J}XiU-^NhpqEeCOS-rFmZCf-_##
z<Tz;Pu!>(}#fuczp~-`GI)EUOH!d&vnjJ{u4hb=KoT0L0YtL&}A%|9$BrwX7oIWFo
zlbepVIQlGy6&q#A&8#F;mLxFBl0-&XGEEZq0TP0)DoI=v^Qe_2n^A{RmgKE7%96}z
zlqGlG^V%(F(I`vuyrof=Br?j9L`GRM5A7Lc$r2!=EXg@Ck~o$#%92DzS(3;oOA;An
zNg|^x$vOkiYiwF3se|%%#>NFh62~Rh5aLi0cLWGpS(3mgOHKj8r&?OuU{tCJByoHg
z0<0u)d~UU}B=3~wQ`n+v`<}3nmc)@##78&uy!H^{f#)?oL*YWEnq-#qJgy$s(dURr
z>uHiW8V=FQlIfn;SRmc=nw-z{va@<)f1l=2%}evB<|)yd@E=~9M>X%8PMm5vpXn)&
zYF(9RErIiyPm*B}(OQX!)=EUQRwAOcl8?%<AWKEGRwAOc5)rMHh-j@OO|+JPXl(&%
zlIp_R!GAQ8JrL1aiHO!pM6^~SqO}qct(Ayqtwcm?B_diYc>%3@B_diY5z$(Sh}KHd
zL~99%)~FCF4TSB1|De)iiHO!pM6^~SqO}qct(Ayqtwcm?B_diY5z$&nnrJNn(c0dq
zLn`u~M+<iY$z6kJ?K;Fow3fj6OeT1Pad|n+p*^atXTIGkP!Q)cne0*L^4lNe+s1qp
zttB8@V{%y~I1cw)v3WE06qr87eY0EWA*~zvisp8Vp1K&Pni0B-MVI46y!0CIE2Py{
zp~MNfTvwj~{{x}?6@W`ou)BC!n=E#3x<Lw1j8O3in(2>ic%XS_Rc!-dZy|^$YA&~2
z%tQ4FmFU{Gz#b1c69}`=Hx}(CywR8rZ1iZ<ITAtodsrd+`#9h_1l8ZerN1;W>LHY`
zLz!~aq55`&^sN>NT@Y&Og1%W*oD9{ez$TA&@s`+-ReJ)s1_pO>BqpZm9qYXzSh-37
za#$bBT8z|eyh!->G$c=<0EGH_(N_v_wSp5_u{GU5f?KyT(v-CsM_HS}F@Xp8hE~>Q
z9A$0BQPyT0Wo-tP^asoDw07UdszUc|^B51@w=pi(W}?vjV;@|)Z`+KB=>El4`BdH$
z-M`rFd8Aw3cw9a}5VdRS{=t1)t_|ilaNowZl(iYSZ+irB$BI(-FLp<i#iG>xi`~=l
zT*Q4R)9Hz#!SRO_<8ojN?%Pg9x^~}oGwbI$Be-v4T&&Hw>DFf8zKsnlZ9uqhBT(9a
zaNkA{x^G*J;<PqH7dqYmTpmJ@v7o)T5HE%Mwml<gFL2+c#uK=2BT(L-;l7PPd4Goc
zHUj1S8SdK%l=o-2ZzE9NpW(iZKzV<L`!)h)Z3gb!2(+~sxNlp^J_PRD7*_|j;J%GO
zS(|YW%-{$DYcuXaf*c&!ss!~CWRr1eYcuZA-b<`hCi0kE#?^r>xNl?YN*mA}pZGIU
z)PXIyZ{u9h+6?RS-ou3<s5sO42S8wL#y!c~4d+ATz!u!MF|H15!F`)lk4naarrozq
z!=p!QGw#-0$xLfA?pw+fM&Q1U<&<Ou?%O5-D9H%iw-IRfZ6Bc*>cAG<x3P@U288=I
z&P1nV;J$5h3{#v8+_!o7fm7@U+_zN&DE0&H+x7;i7Hc!^*Ey_OS(|ack!~t$Gw!$2
zj&a{M0)>>d88>3*90fE~tj)MFTk25OW?WC1`Y`U>u0U^<wHep9bI-w)C~Grrw(WOD
z=asb?H`h+_Ayd|7TzG%xDB-@1|5&I{E*x!PH7}%NzAr~oib-ki+c*niZN?3b6)0;n
zbl<iP-FC#<3{XCiC)Q?wIurR~ZN_~&;<0|?zHOa{D#hB2+sfJu-M5XzySq`W&A5M8
z2M~<=wsA;n5^FQ=M-h3lm9-i7W0ljmZ{t(1tj)NeM)HqGxe;P*#{FF7H169td?gui
zJ4NG{qGyWzaEqgPT=KzzEw@WFmrFW0u;s$~=X}%}upe$^H2Y)>IAA|q9N1chRIneJ
z4wtRWdjuKM=3QVg@BPq;OlK=*y4_8fDK4+HoFs*JD1{`cjjPV&L1|i^k+&@ulRR)>
zHpZjqv=9f(20gbG<7rbTv)p5C?_T5(Lo+ViJQIL9#BZG2N+?3lZE}mz7RQQ_;i{Mo
z_Y~XvjFphta2MIR1j^8i3pdY1%Fv8^nw@(hlA!j-fAP5Ps`A{{i7SI{p55;v?fDC%
z49&P!G?zEZ5koVs9nEG&PYlhtFf_xLvNAN|!p$=$)p%}O4rDyH{R&+fErw=XH`<QR
zNV6E4apMY26GJnur_fvxinws|T#fb?iJ=)6Zl0TfmW!boH>uh)p4(WbGBo4D%`=fQ
zG~=ceQif(+xOrxpGBo36E2Ip~xH(aIV8CqjL>4wJ_Y=$pF&h^QW`lS{h{<fY?V|BH
zAc&zEw?niefhC4!+})z>mjQv<;QNzNsU|p?#ibu$<++VdsW2NZgd)6C!fd!5qe-@?
z+I~7Lq&>Gq?)CTxC+WE@vNri1)Lme#V=%yd$uj&TZ%Gav1n@v|G{Dv*J-0<36o(<(
zlJwjbc__&{{eF_3+aeF=K84DZ=eEeB$s<rE@Z1*pRdNbY;JGdGm>~R0XFBXtXTB=r
z@c`ja#4{bf5<2sl4Iiabg***ck1P37L}dJFp4<2;EV_uR_pa#fJbodb+n{C0E{bC{
z@5p@KM&(#7ag3M51~R##8>$+YU?wX`$7+f30-Pirt0g7~@RGm92ouK%@RM|`mS`4`
zom|3f69wca=~yjsynyyeI#x@ZAfQun9l<04#mO59CJQJ{_QLEZrpWRrPxd32Dxe}c
zhuNkHs7$^^FkL`Z@^gY20;-dAtd=-YKuvNKQ)UY2k*r{Cvjo&8KViyj0d>i<S!Rxa
z`eYfi%@xoyc_Oo&B%mSr2EjZ5jmZ%N^9A&>vL<4vUZkJbz*+nR)kXHm;(O9c(y>~k
zNq}ReILqQ#Ei$B-d6i?e$S|(}uPvF^$lgIg&TC{JRZ!+NGF*Ts^BUP#fG_hJ*-t>W
z%xh$S0r@hokr4vg%e+Po5YS2HHFBVUVwu;-NCBlXuaQv#%4J?72MJK~8aY@%oy=?G
z5CM%cuaVIL`dX=B9AO-D7@1hYK`F;-krTWlIYKV5$YjZ@7FcA80JXp(Qw6~APB&y0
z$7+$;U0F~$R*TH_4#Q(9j@2UbvW}8RbOYO(FQ6_-$7+!US<{d*E=k8~k&^{1O46}f
zWTDi5Ws;87BBuywNnT2@NWjXZPjG4$k4fE}yo%s7Nx3sg$7+$&rJXfNI#!D;mXs|?
zI#!D;5wJCT;_UHOWT}8{Njg@GEEDj4GMBY27qC4^$7+!k0zOH;!CQTXfX`vx6yx={
zcsL4qu#*b2Q-WQE&kHfm9Ij&(R~K=5lw-9>i}xBpl8)6P*Gb)0awEHNy#OcKlVGI)
zFWH&k1_8d6x)LSDv07wx32TvMZsV<`nwKjatD#M+2vqfR&bLP4K#&Sa!;9-dc~7yJ
z<UCO4l$dNIs?)NwXr@DjL1~UJNoffCeEwQ23~`awr2?F0;@qr@K>8XCD<%vaa;C#q
zZr3+^AnjC1+pg0dL(Y<qJ0V-|BEB18AEvYsmDsM$O6+%VDf<SztL>KZSD+hT;<lH=
zM63HOBt$;3nGo%sk7AK+3X~5ectL?KSbN0|2^%}{Rc=+VRdV?Rc1z`RY-x1WCj7f#
zDYml+_%%Z*$C|Sju8NEP6>6Ylt}e!8%R1s5)cCI@b5Z&>kBsav8bx;OB%@|`q&(f3
z79hYx)6{G1B$as}IB9Xb4i0?@NrBPVrT9_;r|8TT{S!7du}-PMjNiq0v5G&-xH@SU
zJ(}^}SrCm{(FYmt-<}_6qgOJ%r;6W?;l=h<@qE(9<_~9{XBcnJevI*eYiC<7ovxE>
zXTQYh`hhkUNZ@pxhC4#1>!d3^hhq@SSi*{w)Agmmq0@DaMLS*RiZxt2i-lbKHOQ6e
zMDJv0UsjzB+^utdQ*_hU-mUdg*jR_|))}|5U|<FOI$P21)(Nz`bpq{fogh04-a6oJ
zJs-vMt!!s4dXZR#3$35ZD9~QWuiwV@0)Cx^wYzl!?QWewyIUvF?$!ykyLAHXZk<58
zTPM)&)(O)2b?^pO=x&{HD|EL`p!s!<!0_ut;MWsZ<3A7L%DB?`^?}&eh3?iFw?cR8
zY+bus-wP>T=x&{JaTX?w^(78P3PVtFwsRyvUTRPQ3V>hdatYn7Gj4_M)}?w>!uL?B
z2Frbt`=<9YUJzM|Uzf~TieHz!S;x+|+_&WhYj^8h@7mouK`QIm3CCORJ2^+8t?ba<
zI?HQ!>zs*Bp}X}X@Ukxs-K{SNC=K1MuL39!-K{?kP@P5Vu;ABObsYdcD}0m7ZuSMh
zcZF}IZ-!rg8ifqM{tA%c*I9?**V#YAuk%4P{Q4)D62q@wfX*9!osXB{*I5hrb^c?a
zLb-6Xg~QQyA?cX!?~oK@QX0R`bj`0zKJ9M3F^*NB`E?@0uM-)5o#hO_-iSB0;n$gF
z+^z46G{dhm&G73-AkFaWe6kI{&YXr{XPV*Hxp_DII&&I+ox?NydKPjTew|A`jbG=I
zPUF{SA#WPL{wXR-<JZXz;L*!=4g@_A7seRRcDRt`PMijqb|(a~cgS<7<Q#`<J1SVM
zYMqm$@SdH+JS@d^Xlg?pcY`1rW?WwK2*UR|AE|92#*3WdLUQouV629N?}59gId}rY
z!LupjdtGii+T!T59ad~O_&Ka3<lqSm2Tx=;cqJ}O@ZT~d1YK1e{FV5X)*Sp2<S-mO
zZ=K=bnbC0Yd`%k;o_#hP`~)Dw!S_dthJ)u*V>oys!@(074t^EdGaNjbTf@P#J;TAX
zoZ;Y!3<pnSICvt%!4nw{o^`_aI+qZemPvx|bz(Ly7{1quxy=zAa_}F5pgDK~!@++C
zw7^R6RmG?jgYWev$is&rz>0(CbE`Rc-YLz&vqjbRu&_`dF3fgFDdM9mixaDa8@6nR
zk7yB}p>QFSm(F(hZ7sodbUq@|dPJFub?=Ny1tKma|NJE$qv&5cV*gQ|I~mPKU&UU<
zo0WeX<M%K=ui%%Auful1yC(NT#y60DS8g0r8$Fis|H^%q^oJS0FZWN3U(NV~xo<Mw
zj`82;e#Q9RtmlQi7M6uWN-HrWn;jJ~WybUrm!p`TO|EJ;82QEYZ1VO3-nax4kHrs}
zjL24|XOnjpjsz*ydlXiu-_aX`?Tep@2L0VL-o)rF|3HGy8P5Vl{8ECVj5v3Hel<aH
zG7rG>2M~10_>eQ^?@rJ)<0}B)|0_X>)Ryu;!fg1Z8Gk}bw!arsdS=`PknhhVXh^Wv
zoqUI&QBsQig#^7MrQH8DL2pT^_Lmd%k(5UN2273LH}f&n*4O`%pr8LsfF}O}X6r9w
z8)QlD<1x%|8mLv8nVmHoq-;kfa7!L2U#rQagfsISpA#rj-OO+DB~Go<%x^kL{2nA`
zekXYXIcN$}U3?Jy_oTWm4@{;Y)m@9O#aLZfJEXcZrFLYnem1GD`!d^uR5urO$JjvF
z9;CWYv%Q}t)pdDbG6kvbQr63g5}CNXiy-&lJ1h1Y;v&^eL8{Ay#HqOCg1?j;Nx9<a
z<=4zdscs5VT_z`90;T^C@|A)jQr#4!x=b!xi8TPP8oXcj%^)a&>0zC@(-1-FSdZlH
zhce&c8LJte$oLWQHHeqL!1&Rbl(^zlAmqDQQ?c%`Vv6uD+c`_(ti5s-xGlTfUb)Ef
zn(&y~E#wrHDcy2u?t!J2bq_)n<;fL=Z1!`&4-l$BsmkS^Xvi{*3!z5rn^w!#Z4vMS
zgdSp`s3wDrMlPPzL;Bf6vP3SPR%@MVc_UEiVQ9Bb4i47gMBcfG!wc{<tF}GT$7ewY
zRi|6E&7jdG`00jL|8zi8b-;ZID}~J2yAti%Ev%y9XppW$m##)=m<;e+L>?oU3*at?
z$emy@z+M1*A~f>jgyr?(mxSoWt4{CDYG<Naxzw@l!|Z*-%1=XyMF>*GFA%wmfR*2Y
z$n6Adc0D4$Lg>SaSVv#B(wA-E%wJy+7otXtgl25ibim|Mcor}N7DfACfma4Y*2RAR
zUbx!~Sr__NXB2d-M~367*znN2=;DA4Uw;8^L*OB0mw8dEeXQ17ffc;Vyy%(ujfjm%
z>@qKE#kPs9(Nv1uZ|t3%R<>)(@QD6z*sftaKgD(p%l-SdYgo%J^P*NPlvd}Rm%!5j
z-zc<8VU%TQslzDC?lLcGG-h|17sYyk5Ict77Nap+iuGbNW@+KmXw34FGa9ojXEbJs
zjK(aH(U>JN8nZ-3W0rNM+pfVTp_T0#;&j_J#G%IQRP;`3%n}%l*<I#E!EKP&+GSq!
zr<)fo74xD4m3h%v^yXhVUa1%vU9Aj;#-dL?1Cp2;y(1(&@+?SVaP(efa5NTO&s<`5
z^u93HI_47Nqw7M_T9U*B>BGtdX)Jot?;Wp<n`*mbB0(#3o4`VRf{!$IOCK;6-NX=S
z$3!+Q$GnN%`iltN$O<8Ur)oS8qgKG~2SWFE@!Z(m5@KNUzd*Qx#1Z{K?4A${o3qcr
zk1|5JSko*|h&9a{&V<z$gz^cKabT_@kx5<T%g?f`GZDIvW${W?=ldYMOX5G+P*oyx
zGFq=X8y}!ZY+%l6Rp(jfKz4!9J#!X_H3_j}x)FpYNgT?YJyg!7bHUsol#AWXTGh}(
z5N47n7CP$`@hK1<BypBy*C&$fW$AffBN57HOt9<*HO95TD-kL<dD%-K+O>wq&|bTY
z*ezgeDh~#^YA;;+oR0`XHIr+O0p&uVB?vWS^4>>eE5QPQx(o26A=In@_&p+z5nKY$
z>q0bzP;))Ng@~L>a3{dyh}=u?AVA|qr~sknHvkVKay!9`00&)cSpyMjwgCJQktYy(
z3`fU50O9aVm<t6vx)j$#Be?TDo(xjvv`WF9?s497Rp$Kfr_?Q40Z%)q&D6Bm!>#L4
zdYa|MvoNi?gw<maX!)T1-q7l=4D$7uwpb;;YZ7~$wN%l*O`|n0Q?y*&sMX`5fY!~>
z>b3?n)iH3(9+$?EUZ%~#H^|aI(ktT9Z{$5b(rc_n$9qkf4a=?Lyi9I`dhf<E<2_m7
zz0W3?5P&HJ$9bZ1*<0-FHV0+IX79ux+XQAi!IS5v_acHxL5f8%IVe*>Fx_j%9`qIi
zy)!&zptnz&4cES*863N#ljxgn>9ubw>#p1I-gd0l_tzZqji^3Z1M99B6aW5s#ZTps
zV-%|HteQ7Wyp|!msCmQ0>kP&zFoua&#zkOE6R+|cO%ty#gDMh0XO+)SwjwZwiC5CC
z1e<;vA%poTFoucO47}7tU<?zlY)c7@Vd8Zy;(@>zCSF-g1jaD&itir~7^fU+rUq)>
zF~&o`9Q<gc4dC#@u1Gs$_41Lol~Yl_CW$Rjpyutb?na>0ynUL4`<_$L8&Orhm2!sQ
zf1)=o_aewx(B4~!(=SJ_2->6AIMz?}X_eSGbSmnnI~Db-v5rHhqCTCZg-%8N9{B))
znz!E(Gafn>^`{U7YTo`Gg#h1E^M+H=h3rFM0EclUHU{HNpq+|x1cBH%c2EWp#l~In
z{~TnKacQwJoQnRQl~T<+c1$kgN^Bep)V%$`sVMnSB{q&t=*+n|3lqlr5^v(d5LBFU
z-T^R9MRTL5@fj#g#OCENuEfT%P|Z6femS&L(Pm6m;8avHx8+pS4-DXpV}<^`>rnl+
z1c5ey^DcU!#Ky5e&D*cwt^Y>`XF`dMV;}GSG9El7HjaI|yXA&r<Jjk!r2tB79Qz_M
z06?jE$G*;C)!L~jyV-_Q(P1cLoQjHH4((Kwb+qMF^g@ioI2B!rDKSn(+oAKusVE<^
z9Xb_dp+dQEw1uU-$Wxed&gXh$Qkq{5&O#ebMaAf=b}A~~8MISTA|*DCwNmq@Q&I8D
z(S}n|@ypSMQ_+|4Bc;T~F{pX-DR0ZEDASBn(M>3)#KxL&&JP)94&NBSY0Wru$*1|{
z;FA9D`sGMDT(+X0MOUC{^DZ!$_j+_9<!nNRcGQgF@=D7|Qh0}4BuQ;tbtVr=SArmK
zTP`Mf;2<RC+qXHyczK6sO50;)wsydw{fP>P+=f3<xy5LU4mdC}T+NwMdfCwaM8yF|
z{vR=6F{pWq1CIRT+W|q%`vmmKhpsCAeHV5u^e38+JEi@J@)yJS6XlIkLgE<IyqQr6
ziRn+2FXguUiBj00gv9hGDh@cbKT$p-N=O`onm3UW5|cwFQbOVw)Vzg5*8W6=LvF*L
zD9agtqD01@D3KBp$Drm-Wc-N|eczvGq7p<lE%y^bVq!Kf7(!y=VIfZEkhMQi;gGdI
zQN<xA_+nyIs)3N0GtH$R;GMGWDs8V13k5>rltYR*;E=_MRq`wdDTfcFIN%5u^2b8v
z$<hSZQ3CH@X+2{6iSk9H&y=18(51Nt*6{A~d-WW)u-njWyX6%W?RpvaVuK49ufGKQ
zc!ZMUV2DIc3>^n_G(y+J^~g0;R41+nz7U~w&TQn{tNmY4GI1$ZC_*VL{_mZ`XQu|J
zJ3`sDtbgC!w~%Wr@EFo)X2jkvms^h$fu|yrPPXj*vpJm?0-cY5v2RA9ZYc-9a{$b3
z4dQ;viXO<HU$Nx>VX)U*iB|ysZn*l#_Ih%(FY;55_PO)Wzz)v$eQ)E(T;ax#aXH`D
zYUB4NsNu$sJGXG-M>;gyarqcQ?rN~{E5s_;;l}UR$Y?fxEEaD3z!q`iSBsKaP7|)d
z?$2dB-2E*@rfg9fgxKV6B!s&^#;u$*uWUQH`^$mSAY95*S&&}YM&o~CI4(~j$bisZ
zxcl1&Z@K@>?k~3m&#`A?_jexq5bXXK*SkN0#d&|r!~HujgCnr)yuhVAk%QeIr?v&z
zWL!m7?xsh<bKrQa_ZL<g?EV<v@$T;}r0Crr=Yn3@SYP5(To{6ivm9E0&CeF4!PrS&
zDLNnS{uuw>?k`IY`DKgJAY97R9(@j!24h=uC36mx24le?zZ@tH#@-fILMaWxE88Si
z81DWEQaORxgxX&_-u-bV^zLsP9!0(T%f%~7DGg%x*Be0Z{zd^*=L9b0S#=!%y7`TC
zvo8Sp865H}IDlJe+s+w-LW2rIm-5F04Q&^?lxH2o3T}c7H5MN7E4bq{poE>#f^m#0
z_y~H|F&y%{3{x_?U`itp4*8X!^J5F<vjrUT<CAt&!61ASiRnXr^6F)w_HyB9+mi*5
z6T-M@*CWYgQir2@Vz^H1^@zt=C}`zUzToCKD#al`s;M~zPh<<qC-MsD`V?uMiTr|A
zF69e;OTG)czsK>;&o7|m3++<AU_oyn9P&FHugb=PRxafWj$}Ewl%ImMrh?F=JfG}A
z1qt*v79R2|DCTfKiR3YDc)=?^5DxjxM7a?KGeFb3zk+c0$Kj7I2+bc}i=K_$jq5*#
zLw;QH!|mN>uz4Kv<B}d>?=}&&#c;@P3I1=2?AFLeaL8{NhO;HI+l#nC^vXt^r}ycV
zP24DyaV;W4+Pn)S9eIYL6Isp&nCZe*AaHr5<s>P*L+z0ycaf{k<U#2s5agB1#Uu|L
zc7NkhbY6(jv2gcSiKne2Eh_sl9P)bvISS-4$00ugtDu!P`GV~nBM$k=Ek;`$D@KNE
z$6ImtQ!yO!v#}@&LW?2<RzbM?BXSGE-QS5w!tRg%a*z;owbO>!H<5TZ%zpt7`NhIR
zeg&cXHDOf?_#Wo&j~Ts!O6J7wk1yrYf{WS9@Q`1@SzL%twEAqcGos+t93breo<^TX
z7lhvA`HVCdgx=(drWJ(V<ca1Mgx=(PqrF81Te!S%$Zv0;<pr(0$rsRxGQG*O+{%K(
z*&Yu05v?lN)(!}V{D{^RWU^=2{SmDzco)|g4*3zSFIb6t64QtL68wo{(=tie{SmWq
z!Pxx~j|p+1g>4%S`JD<v!K4CIghPG=Rzc`Z{(K;)2=e{Os8kc|{<!o5y!-apSCJ^6
z($0Jj(DEVgROi>xS`3H$*rICtg|JY2EB9s)r`hhk9v@+Uw{qO`wMm{$v3wr#bMH&;
z0kFj%ItbtaIh426=OI5gIOON^ke~Zdl6U%jpXWo|hjago%C_h6jF<apawaM$xAT6}
z4d_=%y6&yC^WJC1#{}(XV_C9KMSNAr;{n34h-W!`B^2?Q4Iia5g**?}1XuF4h{*WU
z_Mdze>iy@{09nrC$d-Bl7wuMn-3<@?@g`=o=Y4VDkG{?Q73eDt{4tZ|2M7LSDf_{J
zKLXDW4*U`LesJKAAlqNU3MNVg`F?QVk16f_;J_b2CqFpwM^Nks2mT03{a&~eIPk}%
zQttO7m@1&c4-Wh>rP6<k?M#=HDnB^z$CPS6IPgbM;|B-+2zvMxtZkN*sr5f$1+xXz
z`DbGeaNv*G>isfin=7EFe<HJ;B%r~6gJ7P3Mn5?4$1=UFY&r1f_VeiZ-RFTncaJQ-
zGc8{hLz4i<ayiRgzh?T7V&=^*MV(FVFs}-)1DRKM@1P*()!j!GlzDZB3-DxK-F*f4
zGOzA_0<vXZ-TejR%e=ZH1hkiVbq^5GN#@l(P(ZQFt2<Iasm!Z8N<g{Ht9y_DHLvc$
z0_tR5-9rR4%DlRx1@yJtBRIl1=Fpv3!a-%<fpPfm3EnJ@kPFP6EP2%ebEgP!WP!O;
z1$dU*gv?!!<_yg4%7WQ{Li}rYt~VX8oSf+=&am8hS+fzhd>;67=L@LwdEn1okhK&k
z<9r_Yb59nq$e+xX7fStC`aJOGo+6;d=Yc<Wk${yx5B#~OW?g~`ZuWWL&pl02?(})!
z&pln*S>yA-pSxI6w)i~o=PnVjHHQcO+@%7x`8@FFE)(#+&jWw%ask`@nM_$B;1mB1
z4)hEGpQA9wo8aQ%DC8keD$Gs^b`|D6N3d;m<$*u<>LN~0_T{KM+imf-1Nc1f=Uyju
zTmD9N;d%j%&jWw%N&%kF1Ap!f0({H88zsB;BWZOBYmrxXA>LrBdASy;pY~p$s-Jdw
z&IjU_v?mR3pFiToljX3OYyz5fPKn8uqB<=*i^8TEa!GT1VFsfUOpVH*;S!qg&nOaB
zVBHx|BE&-oX(R4^>1Hy%^}F#4)v8Nz4-rb6px|%!?C>bM^8)a1Nb5sdgRs_nT?Xcu
zp_w|KL*(T({Bk^&2xY=<50!bj8u$`~Zf~-UVF|YPSKy7LRk6Okvi1aR<S(G}h=9S&
zlPhhySiO<rSlvdEi4h)pFiKEfvL?o4%ew#CT|6}QArPKigxR3*qz`Ul$UZZk&OU45
z$?Zr8*=NT84dKZ>C{E$YNc>N5m-`rkEIHiEkbNG4ef58aea_MB^O@{Jz&<ms*=GVR
zJmCn8@PsI2pRYi+;8Dua?DK1^G+>_@-!c2V1u2?+=3G#C!uk^1abXB5PC5SsFv61}
z?BYW9nep$j&#5#UIbfe@E;kUKNalYfJekA_Td~jC0sH(Jda)Di^P6}IHT#_Daw~E-
zo>;KY^#GcE-XA~<Pgu1Up0Jy32u}_|AtO8)52ViA#b6_cb+jcs5%xJhWS=j@lo;Vj
z32vtmo^U6(L*WSv70QL|b0J@g@-D_r;||efQkw9Dv(Sd{<WY26ow)<UoKK|A+>w1I
zYD;+XsD~=s5T1<28(E#Xi?y<mL-v`Bs}Y{?$!<${!Zag1nTm342~RkDBRt{3Eu(eF
zC7&id;gU`ho-9JGX(l>(VlFsyNA~$Fq=J2hpaIh<;*K~nq|LiP{6h1KDos~GvWS^(
zw+aL<ue6*bg?A_qNm3hEoymjJeLxU)nTtstxPX106=E#ikbN%0$~3~02arPxPYBcr
zyB|6ZkXwwlI94S>F~XCtSxLw~6Q~n*6rK>N6Lu7yoQR}=efHzJtI8l}7p{y}>~ns|
zKJ!Ky;R!Pu;R#>LZ3$1#Msr4Z@&vk~PT0j@BZtq35uOkk;R%rup46i~b;6G9^I#x#
z!Y<azMvi8m^INgc`K{RJ{8sF9ek=Al|9k9nA9R9E%l!oVOw7gwgMB7GD8!-gWB~|T
zctW5~*u`KY=PV$w&wMd4D%Aw+GnamVmGFd5sW!;TJEaYBvPISQ@54gcMh@6#KEfgU
z{26wNntiUvc1^R-;{bNdKJ!j%_L+7cm5m&*&&Q)oU?T_Y^E{xyMh@6#BCyXXhkfeI
zSA{$tAn?3j%Hb=aGoRV;QCccwp88Ah5xEi(8Gm3SCx$bAd=-j~oEXmdi2*TZ9kLaN
z)<D_Qbk13u$|)qz7jVwZq&a6<#UbZRpgCs(%{dcj&Y3`S&IFosCeWNSf##eEH0R7!
zqB&;*%{dcj&Y3`S&IFosCeWNSf##eEH0Mm9IcEaRITL8knLu;S1e$Xu2u<aHa~{Z9
z3^-@LE;Z*&0M41S+$G?gnOB+00q5KW>{7@%tAYXNECoZ(nLu;S1e$Xu(3~@Y=9~#M
z=S-kEX9CSR6KKwvKy%InnsX-5oHK#uoC&}=(*a+XfOF=cl&KtW&io!0a?Z@FIcEaR
zITL_$?upD@0?wHQm8l$X&h#E9rgFeJPm(7!;G79G=ez(wbIt^sb7uXTb0*N7GlAxu
z&q5i^IWt9b&TL0>&P>sqGl4Rd1J0R1bIt^sb0*N7GlAxu3BWloz<3jkv*Yr7gL5Wk
zrv!s@Cgu?_!8j2caL$|_Whw`p^V<L+=gj<?b0*N7GlAxu3BWn?U|*Mjb7n2_*5;3Z
zYF@5^sT`WNQNQYZfR(8n((wLzN?uniCcpnQ7p8Jbj7=3*BV%EZot!f^1;{1M@$DFl
zPVgBaF0#7Pk6lKw;+)TfQE#+tx71*#TXGsX*k0M(C;kT9>*EL|BBt)0x)<H~1b8cH
zB9!hUobwq_@f(LwDxC8{36A60D=q5*1SP0GSZ?RYtME&PP$r!7Aqlp3Kk#bOgmWI9
z)c{(%t1-I>7|cAm3g_GnDULPdU|bdFd}hEoug4yWf8VV9pW~eWO~JD`m8SvO(5d`A
zj0aBTNmr%~KR`sZ8Um;CG{qJ=m6vT}=v4j@WHf?j77GQ>=OW&wVOhA`<5X&<`DWHH
zyk44N*;u+^*-+y!nXYk|+=0g7YE<>(hGn5~s13`88iz?5mJKxylj$0V$#jjwWV*&-
zGF{^^nXYk|OxHL}wxMxI`>|qJHnx8T<I1osG!6+g)6CtuVVa4+G`C?`7Bc6TSgA~8
zx?$N+<1iU$92&#2&^X*_!?KV$)4rh?mW9S4<I1qC);LTzEDNSNG%O35vt(|IX%1cP
zO+tm*<sO07I5dW3Lyf~^pmA7<8BvC1p>b#o%R=MO!&^!FwWtQrel2L?Q!~xRuq<TG
z>}DHG^9U3&O!HAdhG}LUZ86Pw9i?d;(zuslnmeQOhH2(QwnL_wg^WqkA2lpXnX@)5
z8*61)mNMsc=(b^+i44<B)E3jc4%^zcm}XkBXp3n!hGnU7$fvw5rkQDmX*Pyswai&-
z9P%f^FwL~CX_#g%|1_pK&9E$G&NQr%#x$Rd0jDv||Mwb}jkPi?OPTY%=(=W_3EE<s
z<rd@PCC8d>Se7zpT94ICGl5~6iN4P?|In~3WzMu0+XmAt=F7yeEM?BjXqe`Qa1+~N
znwO&|hH3s4x?-4SJ|l){CNfMjkztyRVOcWGwC&m!)68;4<B-T`91<CgLn5PbNc4S;
zLoo&T-!d#qne!Y@VkmPaFii8#8kVKZnNO)^nzdnB%A9}9uq>EnKEh&H7BXjJSQav8
zV^|h4XJc44lsSuGS;(Aur<Gw@$eg)X)J!w?hlXiRGb{_HnFvht&t_PbOfz4VnrYr;
zSQhu?f5EUUxMgiv7INkYUnOE#*8QPjS;(1<VOem?+ORC-%&K6(EfY9mSQc_-0%ceh
za%KW$SQc_-0%ceha%KW$SQc_-0%ceha%KW$SQc_-0%ceha%KW$SQc_-0%ceha%KW$
zSQc_-0%ceha%KW$SQc_-f^@^OkTV;@vf!4rVOhwTnO7N>g`And5zEDpGZUm6mW7<z
z7?uUMtPRV8TQ-JeA!jB~hGijVo(3>Z49h~!OrQ+QLe9+km0?-PnF*9(S;(0Qlwn!O
znT=st$eEd<49h~!%yyJvS;(20q72JI&P<@WWddbb7IJ0+Wmpz+W&&kc7IJ0+Wmpz+
zW`cjmuq@=v#;`27Wo=j%a%R@849h~!OrQ+QLe5N}49h~!OptC^7INnQ8x6}&X#ls}
zMO4SPo@II4F*duU1pH{%>6YCsi<{x|!LOc;Py)5=?xMbJAKDcMQOkuxehevhAe7Fr
za0-?0?IUqK;t&L?Ue}1~^~FFJB9#5}epKHhhn(7K;9E)i7JR;4o69yg0zZvFb?-VU
z*$on+Qc8(39pRJ@FUEXZQ%2*eIOVtcgRg|Fygly<{+ezEr|db$p*At_8c{A-U?7$@
zU!67GkPJQT5y%=-#%)~2Bg!31U<bCf^;vg1Gbo=d5#^Hwc5%MIw=6M18y(pJ!?&~v
z+ITNC6b&rNvhL77%bAP^mR=cmXzA7HZ^J*!SD=QLUN<mKHX8m}NQW{IE=kO<eE0|~
zz4BW|Xz7)0X-luKA|9~O@Xx|xp{3VVNTKYRGT^{^qRY6*p5dQ`gVFw3e$D#H{lPyA
z<05;8y;ruS?Y$Ccd#?oA-YY@qpXIkGPTBJb_@6iump>uMSkRuxp5dS62yC}Qd#^04
z4(_@A69n4cD}lE6N}%n%5@gH4J@{uK(Dq&lw7pjXZSR$!*a~FN@XvBR`w;kNVO+_c
z;h%*-+k52*0yY}{S%|<!C-%Yrdyp;o3Kqzo;h%*JotnsFav9h5UfH^~_xd?fw7pl(
z1!d2yFX4fYWC$uwIVpfZ_6&QkeSkuHuZ%0%GyJni^{9l4NBd_v8+)3-KZ|4z{If{j
zz&{J)+TQEQtWadn@Xtb^{j+4DEp6|WWwgCl&V;u2`W3!oDcQ68>FzuirR}}asG_#_
zItf7gXJOUaKMT95{j;zgWAAka3K@H^l;s(FudKt^du2Ie?{zJZvG;l#ro`BL-2<IB
z_Fnmr8GEm+1@>O~kA({5!qFD)%M0n4?|YHtGAYg8D`!F5dzF0J-s@}Vwz2n0WbC~X
z8GElRXY9Sc#(lo_&%!ig@0GG3WABw|#@;KXMaJGMpKN3Al{t;QSEd<zuapBDd#}uC
z?7edM#@_3F=$Wzi$|av>@0CkB&ED%(s5Q;r>opi~z(&(Q%PmM1*)x}|%zF_sq|LiP
z_674k2Ayz8NI|a#+1G>0HI|m0r0_P?F%OG!>6ttz%|m<g%H@iZrw#&WK1COV7<Y^U
zXqtH46YI>Fc-@E`!b{Uh3xP55%BGBoSGmt<ivvzMtk{@%?En#_Ht|YeOuP~)UYbr?
z79$A)X#T4}LeN!Z;&lL*2L;eSbkf4RWlX#>qcQQyH?uME%03$tuQvc06R%s)XJg`(
z4~jAIN~CycI%y#?CSDIjd&b1;F+j$|E88<BURlnVcqK9>UWpVhO(!ix#>6X;G4aYe
zVd8Zph-_LW2?A(hHZB+fXyO?m4o$pX4uUrEN?=U9-U0*xG~Z5)N;QE1n(IHn%ET)l
zRc+#xcS@UhWs9oqcf&$j03E;A<8v$m==j>?4Ez);0d)Mn<SGCqfQ~<q{1bo@K*t}<
z;BdEz{&xJKB=58mK*t}>9S)Uw#Y@K@O}>sY0WTf@Rr2pZfdD%Gm>}@dDTjUP%=d*n
z9w6|eSIXggp)()c@KL&6$QR(6;7Yy^5gC7)lNP=Yg_ow0*}DM5NsBi<#V*RuGU7NL
zhCsfwM=kef97du!;?gi{*Ux*vj$_H5xT2Cf@h>qwQt~%8SBB<jud)<R1^yLx%16_k
zOGzqz0=FiksDL$zXghgiK39ekZTrV~7hoGFl1G1Bg1u0ZM}NEkC3*BG2vDMJ|2P3k
zwCy(wP@-*rq5vh@_Kz2!MBDxe0+eXmpCmwuw*AQhlxW+Z;&J^c(Y8NTfD&!{(*!8d
zwm)5f5^ei41Sk=#f1&^-+V*D(P@-*rmH;K%_Gb%FqHTYU043V?=L%4wZT}<zO0@0I
z6QD%f{(J$UXgl7|yPva2(RO@~EWUh|Xgl5{0HSTqvUq`s4=H9|CEAV;^RD!fm&*3>
zy@P^e*5muAf+E_E4;P?B+wpw`DA9I&KLJX#9p7Jo5^cvv2vDN!_yGcxXghwO043Uv
zj})Lp+woBXlxRDCkN`EW@q+~@(RTb00ZOzTA1wf)ZJwnnrf54pv4n$CqV4zz-e!)F
zx)brql2<LT_!I$ZfyJi^fN1-6WEL+l@!4HjP>HtVbA<sF(RO@Z)?YF?!4z%B=L=Ax
z?f8PM50Roo+wqeHDA9I&q13NL+woHbDA9I&kpLyyj-Q(K9V$?w?f7YuqD0&A)1@6H
z+Kw-llr5qZ9$z9rG3)WA0+eVwzD$4;ZO4}jP@?Vl3IR&A9X~?=MB5)?ya_HIjzZoX
z5N#8)Q-UGdCeFfpO0ccGz{IaEB4@2c+wm6fXrzm1JAR$itwh`L>jfy$c6_A(CEAYP
zAONE6jwmT!VB)JwSd07~EDxJ=rBR5sM_~SM1Xb-9_|{OOZPM^&Y{Gjd<*=CKd|v02
z7)PK)+d+0E+P)jPq&dEYgV728Cd5Tn*~>lfE1fwkUIezVTeFq9w|L{~HrdMDCq)|G
zytvdN7S!PI2yW&;yS*@7JiD_G67imF!oQ-=Yms=4T|in<Zau)c0eGI^JOvVSQRiu@
z*c|5U&BP1rPNa1|9v6FUG#ZOmpX7Mm4<~#ynu<jo!V!e)2{+Akyz*zktlR&L+T@m6
zuCzSXY`4q<zgz*+LH~^AGCBn8{s4pu7!dj_Dh$jdzzGPI`0DV5BDDbi0->sS57hBR
zRG7UNKzN4v7FhO|(c~i3mVGUz454yC9cfvl4F?`3w0hF=*qs@`#|y0|X@#WS4tyH|
z?k49H2gX6HevN~8Eo#?c0Mldu9(I8h_&D-fG@sQ!jv|jBRG_ziR=xcY@I8bY40BU7
z$zj@KDvz6J*_%~2bFV{J5!mz1(QH=J9k5JDl1-{^0`8As_1J^M-Vn9%wzM9(BAm(*
z>`C+F6PT38WqLR=k7OnDEc*{pSuQsMUM+Pz!I7M+>c~eOt7J6sT+}h1335BWMAnZG
zc!$o77P0I7u7@rZLTxj$T@Y=@C0g5z^b4Z9F<yx~cVSe%5iCTunFw`Lk@do;Y)m2-
zH`h%??hB(Sb`hqY>zmN}h&=2}(Epw=rnL;$Lt)$5Y8Vxykh(;u7f-@(<V37N`=f}>
z?rgZ+@_2OGZrK}EREW#qk0R~3+1P}pUqPri7GIP;j)*NFdnNQKNW-*#5{a`+JxCP@
zjon%8r;0cOgh>dsDEfIs23d(-e-ZK7=&eY(8lkco)qEL|!Tu9?J8Agv^<^Z<!Ij^D
zoeKh|<jaVR_ZYx~Ny4rED&q52KL~giLfy$EWpSBBE*@96kSJH7=6dTFFrD8Sn@@BY
zvq6i`m?XR2s;@)J9Uak_O5wcKZwP2j0qx>utCxeh{1W-FlBI9MxrT0y$QpY3GRwmU
z3`}APc2B(jw??u#(1IKBYDM65-5P1n>DnJ~C_?1|WLu?%a2fDYMZ<%(Dw4x-W!{9}
zD1_SiB(>v6Dlx=Wkq(RwM#>%tl^Ex$NGFo!0!|?b({;O=)ZYO<fWX_ZTHS`;RqXiN
z5qmD~e1n4vN2OK>W?>_j^#V1lX&BZ~7_r^5h{J*r0i=jItwA@dkA<}$EmZZ^VmJ#U
z9b^fQu<TPJd1s>NTx6VtV3prihl)zoqFZx`<vk+vb!<CSEQ_u*BEJaFBJ&dnoWwG<
zTC#4zb{2sTQCXw|=XDI=fe4lSs;Y8b0C)~bSU=@z^lJd`Bxyb>E04(Y^E~h$g@)S7
z)uMVEcq>BHXY6A|B!fNAxYe@0WJb(+MI@J``5?_fkXu)&Zr!!Omn$0XaizL-FM;r)
z5Yb3wq>#6BJMcC|lZ>56th|jg!x}M=%1Bqz4g%hjG~C&0)tBc1pGD}y>3Rf{=WdUo
zr?q(2K<K*&7YFa32twak038wG;p=|P*8faU_8>y&e<{Ghh#W|;5?~%8a|!MQI2Vz#
z2_6JkiO6*XPXauE$S)C~lsWuT^(-|Uh4sOQicb<|ZjaY+vE7Kx=fi#ug_<z$u6h!h
zFcWTMciy~Ou6$2TAL3Z?o|?AW1<2&7=|Wr*WSVMmPZR2%)=ptmZlzT|kZ+u4Y<ZD&
zx;V70->E&;ima(;><)a9ZAQOeM&JT^#x7?ccE24DCjx&bpRsG%<0Ak^BX9w2u;ra}
zHsCUnrsB75gDtH-0Q^hR@B_8MmY33B0ACW4WXoY~^{erNg-|&GwBOtE+B*n%Bx!hR
z{$R_?YZ_p)kdW;Uw)}Rj2EI{fSSWw63%Dq@0B<G@i{cNqya7G~{1{=+%W(_7#^`Nc
ziaGaoB$~t|^t~G??eD-=3Zd_f05ynIAy^FykXPNi(X_j0m9OPo-lXR8lM5}cT%ONg
zcL?Y5Cc7i&as)~bLf~B9WLI)7?*hDvB+TVac0EVm^G@us5M=bXsL?M5UPRi=UY31}
zox`HH0$-<S82>GHI}*2m@EVD@5x1%vQFs@&X9#sO>rnVMJO6p~D;9kY`=UM^{<w?q
zefK#&6A#&ri!>SfStzj-L56-mBKIO#d!B^%-F6g+@KOwleXrf+1QxmsDK8_>Mix2~
z-~&Y7M;H)h?SDO}vAa<Qq2X&(5Kf}}>f#3lx1POu8TFlsV1AI7B0dH`!&dzxLHcd2
z()j}|=?&YEK5BQC9pgqfV2o~0xId`F6dZ!;Ids{fMl6@Nr~GoH*!!qE=UrfV@5`Oz
zDAiN2k1cQ3?&xs|0^h9r*xfkO2LcW!2{&^eyMd%r0Z&HYn{{7x<E{m~h9unI{nY)q
z7jO+pe6#MS9*o}tKP5EOwx4=3UI+fO&`{lecJ2uD{|n%MAXIH+zxTJ3{O#KN9^706
zzHRrn<!9Sn14j`gVae}r7ckclkoqI=0UDtmpt}KA3JE<Kp&p>bf8ib>;605eXoPx#
zDnRHiM09V2-H}h#0N^G?lZ?eA9s<HaLPVcO*xg8*2YkGu;jJ{nt|D<02(OX25WC(3
z)i^!{{t%&8Gj0TzhPB7odJMBk-5#4ejV5_FHQBPsYQiFKvWqw|wdmLYHRV?MfqS4-
zhAr>X((^5E4Kmm*{Hd<N6lK_X?14R+_r$leS-kvSd{aW;<Ye0UoUes|QxL3yUD=6k
zQrr6TEU#H=>(>d-GIDS0$jsZ2aTCH|RQayd*z`-RK?G|^8GG|<dC#sn*YdKF-EQF$
z9VBD<wG8D9WIYXG5QLeJr^u@P4(L%*W;A2ko)C7VXe~r92%uT^lR}ygcp^zB_p|J$
zL>#mh@NR^`n3Lbi%kyoZEu>(=o|d<Bhx@R(LSToVmUr_>Kqr!dLH$mC#cu{$NeU+I
zcbR8mEKdVHj!>VCdEg!DB2OA^&|3AQK;y9bYZ{(GyT8@2JV@Z<EDth>*1*R&tCz~O
zw48%az%ng-AE{}%RDONFLSr8z48l+@lc5Z_AM=VZ2vXw9Wd<$-I*$}A;$H~mWuQMG
zaJW~>a0?!Q1QTKK{ANt>l``OCfe#}M1HMXrP_6~KoD>ZBD%lLb1oWchK~>kt)Al~#
zHj?mYT_c&Y)}eBQ!Th<pR(jb4*cV|a2eb%x-R7l~E9U`c3TX0<Jq9_BU{3zLoQB9E
z1iS)~m6LlKf|@g{fyIXvE4<7nkFvxEFL?|n@hsbB_Pt~|oh9$9y})&yC9f%KU<UJy
zmx<nZw&mT-PP80a6i)Q`_WWtO1}$HVFbL~md>1|ve*=0QfzxxGOk&l8c-tWio{id@
zWt_tR2O!ip;TDcW|N5X_ZfP3%KK8m;4U>Wd4rH+;)g#GS8taMK*qhU{06Ao4TIQqh
zKAa1C^gjIgwGXxS=Bs!kp5aF6_S48AKQ6P-=yU}6*|`#tOAzD-=1D{zM`(B-r8qBW
z*|03u-rNR`#WrxPRLD7%ZQtuC@+Sn@5av9DJBlFNzoCc>B;fXMA|m4nxcxg5k!1wj
z{@sDdEd<>Dy^Y9b0&f5MKMV#B!5Yr9^$#MXtbOb8R$%aIY|omGd+Au8pi6;r!O=*m
zsemd8UIhG$qi3yk19qqupj824pCnPhQyKwE+aORx2owz*stH7TWgd;n9XghcD#x-8
z)dZrmQ-eVlGj9&;`!)l(PW0C3Q|!v}C~~awf5AA_1fsX+k&XioxV(grV18=bM{i1e
zfv9NPM{kL<EqPF^=;|04D-79rDhFBbh_aY-2IKd1oQ=5eICKIF-TL7`nV~(mlkt)W
zb?X_oQp%p2j3OCW^Cj>?-FgB))U7ATPAPkCr=vLSxfS8RN8gJVB1q5CUU(oqH-h#8
zYrZUup%kK5{SyREs9R6qg}U_weyCedkR9sQ6Xb`w^#tuh-Fkvfp>91vF>J?Rmc^di
zVeCV2Af0ioTTie!C$Q(n5m<IkV9$*RJhhjD|0f`ujH}4X)(6s8v(ocZ7|Suaj9ba?
z@&S%@*}4<z)~`W|mt;?%ThF<mJvY|pt;dBSs5r~{4M1*YXwU6KpisA-ajjb~)uR$F
zmCVqd+hB(`QtY`&=9IGMCV5lJo*Uy{s9WCvpmpmBv>Tk?qOI)YyBx~9vfQ*A9L|K+
zt$!+pDNfd(hHRhi{vm+Yt>>{|ty^CMP@M|wxv}ax0I}!BZuSKbdv5HTaf8!<LWA<Y
zLUXZ*oih|@XnttVjdcvm3+=hFoN<GL&RC=J!UO5YVoFBmh4$QHsBLWCeBLhDbK@g*
zR9<M$jkUlH4*#)GJGpSQ?S6@YwIdz#Jq1aHOiDYD&h)&{o}1*$3+=gGk8V48p*=Su
zFE6y`M&##(_S{%5J1?~7cD={1L>x5jxiPISFSO^j7HN%np*=UI_00?IxzW;ZQ(kD#
zjZgNVyaakndv44*EHAX@#<byip*=Sm6djQl+H+&hQQ8d-hiBa2EJRMDThAq*rd!V?
zopvC76Y{3%){nz*(sb*$Ayw?TJ%|PZHKszwVP6GZmOCLQ(9N9?$lf8(ddc}Lt_A0S
zAm`9cPLjfV_9^qQ6xX4-uc)H~2=cb&Ov@t}QTUJ$W9q^q>NLA(j;LRS9C`BKLqmYT
z$_p*Lu_-4nwD2Z39c^*+Sq>{UN7Og7lJJN+ftB}1w8A6mL~dSa;jKTCe9Pm%50DUa
zRUJ`}VjlCtBkIk_VdaHK)OqWiywJiMGkSTITn@1C#@BRdUTEQseIA|{T6h}+G$QX+
z{EX1T+bw8ubY5uTjZaN;UTEQsXj)!q;f=_6z{x{<#sf|Xknw=S_KXJ{mNOo3h>Qmu
zBI5yv$augZG9GYPCp_SA39)IJqz($Ral!C_!}Nv_hey<p06}}eAut|rrT{IlJie+J
zm1=fZ+zTIu0IMVFd~UV2J@1r0qRtjo+xLWp0{gyM4k<-^bY*d3l{|!amcvK1h|f^C
zkZIXB%XuDGkL&1jM5OgJ`)Ygww0*US01ln8x<j&AAUq|`WzmJ+MZN5--U-$z6nYo+
zzD`M;9&fyFd`_u&7xli$mpHwPdf#-CIM`y#`%dx%{x}oxF8U-&mV8}~w37F6wM(wA
z#N%Bu0M}^AN1!;R!$yv_VkIYm;+D+BHD2;I=w8VR#1mF*Gxlo<co$uOnxwk0c6b+U
z%wX-v@bh^WjnTVk0^UVAW@#X758g%T0p%xp7mdBcdf{DkZ`2_bdC#MTyMg4ceP<P3
zhq!nbO~AV-6THE=yd368N<PmjT+e*;E}DRMQ6_s=;qvVd@@-?jKVdEt@Gi>ava#6z
zx;8A&V#YRIWqDih-)>ohO>H-PSXh!Iecr?PJdPmVMwb>c@y~$IBXsw$_qJEaZ%4@^
zSPKZ<YpXyzBbQ5U0B~=F@>j6DZbiZFM`A}}pA}`|LL|&as2Fjz<sF8dd8M!}_~^0*
zgyTTK%FD%+lnqBA_fyr&Z1i%2^pZuCH`F;DSl@cobvFWgK3A6AfJgCDh#);bNqT+(
z;Bo}j^ZC;Amw`7Tl&?cC_d>0zmkXqqUm@WggzA}Sm`z$WoG5k={UyT#S>4oX%VJ1u
z$g2It9*|oixKkoAYdH4pj&;eAxGHVt&<E!#4>jTMd~|r156+pG3C(=0z<VuZJ{S*~
zk1|A^koh3c%m;yHJ_thQ<6IOc^HGKW9yyR}5af_@8uQT^Z|;!!U}4RC5NPIuKr<f%
zn)x8m%m;yHJ_t1PL7<rrg5oshgRVA1=7Vv~d=O~ngCj7^2N9VM`m36QY%;EN=7UZM
zL*|2V&3v$R&3rt96wQ2aF35baK5qjq3_-;(^a)^?51N(^nGeP_^C8uv5<D4(`8WVi
zXuy0(=79N-yaDsUxMn`^$Qb5>Kr<h^d~mj-Gp2UD@9pS)N$e|NzQyn{lhT+ErfcSd
z6KrYbV-4PRhWQ{e%m<NSK3L8$AL2?xGapPd%m;TVhWTKcVLo0)nqfZpWE<v#ISuo{
zG{bywi({A%<}}O)hxdQjI}<27s%r1oy|?bY)%W&1q&s6L>CW7lAqh!<fS_Rzf{Z@K
zFwY57Kx7^SL6j&8`XVAAG6@PIVG@*4#U~(&1NcA!1Q2Bi2+HvN{`*wbsZP=mhNpgO
zrPn&u=YQrpb*k<@d!N0x-+aiQg5P|s^}*?PAZvYavR7H_gEL>y%bV^%-r+4zcOaXP
z6GUR!+(FE~`RNWsDdu6szC3(t#1Lo*^`4rCk>m^XiY03w675afH4tysP-X|B?^C)1
zk*&E%N)r<(IV@=J;@@x`?kx@JR?=`C?k#n;>7^g89Z9*dVMo#%LcRFIwIeCNS#NPs
z=WBg%esCY0L(K>0w$2CVQ1ia|bLTO0sQKOeMGVa2<^#^-=1}vs`Cy!5UN#?!!DH({
zsr=gc*X%xVUBDw1^Q?I*w7o2A<d%fc#v{zV;3JhLEsNuSjAV>3;x~}blpmsBxQ^R7
z;H5-!xA{nAJY;t8+dE(Z5Jt)&;h!u0ls4$6oG|za#QSBcy{uxc1RL*!v?pWKqe^_r
zmHhr)oa`cuTBgKjT*>S2hKeGLdQ5{|?n>@<FF#p?QFp84vz0odweI796k*gCVHD<`
zch!&h8S)CksH;@+FO^meY5LFEEf7Y1cRv#U>PlWf!U;;eUnT$MN^brOem4ou*XK*F
z<YOc}qD1rc`LZk7c0WWFVWj!xT;WRYL&CO7G!LGyy2PhRc!)6iCUx}PYQAGh5RKV`
zm-8RBH2OoO9#F08VW0>760Rm;jEw9(sodM+Ts@>m$hn0u>Y_~I75~HLg~0i^i-M>^
zv2kqQPUX6N{&OUcSzbmQU6*upY_)0~{R+20gfXM(XiMc<N93xbW#rsPa2>^oKYD<t
zMF_?&|5n;j@oablQQB7{eLa-+^|@+|`a1SOI5LDWJCVCI?TcLX^)@+wCb+)h#0MS<
zf*%rsvA6cw*SWMNyZUYdFRB*R*LlBYTS*vm2f5wKwfiDheGPb+rAe;qD^C17iN7ZV
zWAC^yy|2s!_5}YOMD5hxn&vdOr?Uy2%OmV2ZLdt)_eq;f+VN?c=H*mMb2K*EfSmJt
z<?wWRI>=EwSEV_@_<5wMojWXTd$zVa1U<*aP5f_KkjBfW1SbW<VVd>a5x4V7njMVY
ziK$cD@tFBoYlbGsYL`N;m@iMr`sAFD^~pIwUU<zD?|`soLe`IG&|V9@8g%ZaU5{Cx
zewF1Y;oak`CH>vXJH1wT7l|*J?4K1+_RqT#P4~|N>Hb+D-9HN?`{xs>zE*g*R(Lmf
z1>{yLyzAiSI~Cqd0laVF-3%&u;oV%&|A)f6OBuG`KMVQ&vyk6E+bfj{?=IzY)tB(@
zCi49LS@rz>`RC;M{j=U|zkgOqzkgPq-#<S<J->feNxy#<GvDu@Po$*ZKfk;1?g`3f
zgm?RJ!x`b-3*>%C;a$6=dF(W}ngma)&P(U|oyC15f)DxiGzp#-qc214AtaatPirg|
zh8W%{!R!lHFTuNz5~&1Fpf3rYJ$d@l6f}ft*h}!9R3nK5Prys?gjOrTdxea6s7`_x
zF_~*5!BfExBEb`P;Dbo;I_S?!@I=!6%OrT}+9s*LlbWe>!?6T!MuHOw-tHu%5<CGf
z!CL@|C3uQjGlQK3Pj5twodi!WZ@PchlS=o`>d}ow5_qeW?w^&?srNUL;N4C<mf-0{
zN*3}nmMlhDq;>Qb5o;*3f9_L)rwWk{S**O5E@$@A<xYD~hCjy68LeEs{<g2KX>8bw
z4YZT=*}l5QN&1FsUtQxQeZwa<DQ=R!;ga;#I7#2|Yq|3pC+X`d=S1yQko3Jo&2E$Q
zb(^HG`&(n7&$><0*KLx%5hm&DHc4N%N&31?($}4l^i`1b$v%KJm$Z(gZ+=CskD;&b
z1+<&%zK3|e`&i<I?oV+IyHDa;?EXIKrS8#O%iRx+=C-@<CSKFsz_rr-cT%d|w-B!l
zOww0D(pRX^pE^kTL(+E>u)B?NLHCzwH`l!**L-)5ltOpJHSGR6DaGzBxR$y%;acv#
zf%GUaNnZs?-w_qsRYTF+H3-p&*waPQ_Y2}C>8l{=Q$}<smqIlzkxKerP&rBZDoFa2
z9o<99xK+xvkz$g*3X(o$kDM@@LC?(T^S{ftk?isxl^JqI?YoeS{)*oEn;`fRVf4Y2
zIE92UIc)>B)52(H#AElH#=RYoH*w+eixQo*JcRiuI}|x;pqA&$G_jmuEst(j%NzWb
z-!;Oxr7Y>^N$4>_V2_E|&LZO^!uWY~tHy!}9mML1jbYz&vWAgAiR6iioUMYK?OCXQ
zg~}Zb!8;5t3~t|ptJ@mP;%=`S>tx_m3_gA@59=rr^Ish>8C-B@^{|X<MuVJfpfCz|
zW8Z>Vi5qz@!d!HN{yDQip)(5<I<r8%E$ZfV#t&DnYB;Ymeqm4j0gCI4UwF91d%1Eo
zi@NMRgT$il#fs~UUwB1}(u0UO51t?x`z*GoTjXawv8b!Q+!?>{%A(%CFv#nSUwBnP
z)$%&yhZ~v`h|8kx2&%?zXzCTu$EW@llAl`CJzwqHnU%>ciYIPp)K|K35J)!;0_ny<
zz)S(*#r2z1mqp$6`5(!o^7jaKFZA~m@op^YPC{su2;NjV6}$<gf;WLw@FtK7-UL#?
zn?Ndf6G#Pb0;%9lAT<Sq7uTaShWON<;;G<GAhoEgI|y>k@u@$dMDTVx#q7R11Mi0B
zJ~bMj`cpg=ys7t8@b*9Cq=Gli#hFZ)+Kc|gMImmuE?friZfNRYiY9_L#Z$qXHBTd2
zJkAsl7IpPT#%^e=aBNZ6%E}ZFUR)J_7r|TNhDL5@(^G${lb-q$TP!{G_aJXgdg@Qi
z-E`y7$xl?eaaa$KTGUn3sT&#%GqtFzew-;Fd2!v4O5URG)*x?DS8aHUx~k_)0m+N&
zSs-T$NM2lzXG*+9T^-`{7IpQKd5gMg1yex!r%LU1(cQL7`r58^=39=k>y?!eylECv
zH#AnxOaaNF?o|xiThtZu7IlTZMP1c%rhw$d^(wxd-lDGZoGBoAaTSN&ThvvaGX*3!
zG&&LF-O%XG_7-(j(wPF17gyzZi@J|c&%2>fNoNYE_(r})x9=_LevXoU<Dey<IrXO{
zojLWloU)mX!@=BeX5+AeTs97Mp_Z-9yN>5&=G~yiLK)ejs|z2YK)<h%pyib*sifoy
znWZ4r(yH@is4deX_O;bwvKNjsetLm+PjF_3(89{}XZ&>VEw!jC;H&`24UM{TR)FNi
z)gCc@>0Y@ru6~E`oEk}X2m;=su8_B=yC+$k@zcM5kP#2n?GPH6wLUEB+9`q5qOJ;h
zi@N$KdyBdnv$FyuFRn*}yhYs~(4)7gt9Qg()D`j;b%ne|-A?-RZfGWgyhUC0=d1w9
z4UOt~i@HMIqOOp)s4L_x>I&VFx}i~<obek$qPn(8Vuv8C&JD9e5Z*As$qr#(5>ku0
z0^XwTA`m+SeV7!rX4oO{Qy*yQ$Jp%<^p>VO1U;#AhoBx^-?t={;vGU=sFY5<sJ1v+
zCHD}o3-v;F>WxVj@?S0aF|Lu;Q3&B<y=Qg^`VgfOwo?Iimao*<FqXn~b`XD<Bxj{J
z>$NzBiNY_vRjaA9vwWquS}iULzx381i;Kc2z2nMU0xLb&Ve#P~TNlFR>-G8~ie^Ny
z0;=*g8tgK9u&2KU^IK@U`w89CM1ziR96_nhN6-K!j5vHB92QQr@5#pCIfRiXs@x<K
z7cHYL=KyEa7wAAukG5l1+d~|xTwFGgtDP_yx))bR0^UrfxWf@u^tb3|kUfs<D>$;R
z;K;s$Bl`-D>?=63ui(hOf+PDN7tI=ESf0tG6r8?CqS~R`NmM&TUMH#@7Oz{M@{8>b
zQZ)~4kW9_vK_ZEo$Hj`rY930*;sKW@2qw&k)jYJ?6EzR@o2q#@5-?HoP_^D_9*zX$
z9)HZ&(n!EW@ndhwz9$K2_qc{<uNs}=$2S@3swAN9y$=%5-Os<?slrD>0_wijhy-*q
z89P;20}{|Ryv8J;HP2hF#q(Yypp}hDK*duMaBD!S_#u!wRp><ms?NWH1XMpCgalMQ
zPXcNy^g&2KwE_vKe@6Y;#gl+aXTIN)1hjG=fCN;%zDPjj^+f_IZ_P+Rm0U9tP$mD>
zB%u0S9SNv(<~>6KipF1w1XPmy^{8{kB2{bkB%odxBLVfoK>`XJ3Fy99DU*1ONkDb=
z5tD#B&?F?F{uv4AhPoOO(8ip4B3yG4P-FHa;6b4OTM|(HebgkN+RT!Gnu{z6D4Zn$
zg+BlZsA`aa`e!7d!|#&>RHZd10d;3A`PGqtYUtfaz_1=Vq;y~N*C=NyALWf3wYrBr
z!+C}1a^pV_d$^tW6?WLl4omL_<z&PM9>$)H$h*3IE0T<ygkijhc!r#WVVshaFpM==
zBPU@PTRdhMTU^u%3}cIn6<s;R>Y`Yo*RBflxDl4xhgTD+!aSD3Nxhm&T8DXjlC?gD
zzPgNg+-1z;E@K{d8S}Wyn8#hlJnk~)ahEZVyNr3<Wz6F)V;*;9n8#I^$HQs6UL7R;
z!94z*`ZMNnmobmKjCtH;%;PR&9(Nh@xXYNwUB*1_$}o?sFps~icGXZcn9Dy1_H5n>
z>YpQS%;PG|V`W6=a2XDl)k?V2FgOaRCB>M>RhY-hj-I02=Bt!jN97(F&4Yk>tn3k|
zi6B2Yr|0$N#X-bcfXu&>9H)PA@&NrPej3t!d%`H~GjgZcrr-qdv4qiLGM`qXDwhDi
zMHmxa5=84kwWn$nb)jmG=*Lpc9g;hXPA;OeU97WXYm?3nu|36ov~U-}b#|zA_6qn}
zrCrT$eQrUcTA2Mieg+AnN@{hXExGyNT?sa*!<#jzF91(bl5IzhXc4jSYw&}FaZ4G+
zrhcGfb35p4%-GzH{M(TMU!mFA%4TOMMNhH;PiL3pW@js#otJ6pX@VQ@);8cz{GM$n
zVdS1i?HlCgwd!~7Ebs|R!*tI!!!+Yhf*v8*aJRML&iDgA`~-ICx$UY$n6>d|((^V9
zayb3QGrH11$6>)MzK<PplNf%Eqc$VX(cm|=!FQ1F9_?8)GT|HhDQA!#ZEm{>_E0}=
z!_I9#(FTl3LTLQl4igXFhr!OZ!7?EuzO5!lSd(|LXA?6ew?t3c&Bq9PfJZR=1q3%A
zBdy^J!RHa&e2lW@p8-FqG`bjVUDW=Ol}oVs7;Ez}9XMV|_V~uNYDP`~A4eGXC}Y^Q
z@5eXkErzR5dv@)l75rDIJ+EQX1^id2y|8K0b^KSTJ-;b92HOZ>@TYyax}D}h6Wva8
zDQ}bhety5-X<j#jxbsjD3mb}whXOs@@WV+S3U^Ild%1i7oum#4)NJCAV3FdnLjuKD
zl0x8+;5kxl3tGIq_7=sp1;rtO(t~I|mwyn9#h@){@sb)jAhRuK@jGSp<+h;3D~tCL
z_YMhEEpbS2K5<DQoGUuF1yww8NN_y)sY8PAt9>!gaY&$e;*h|m%eJ7UDOCX{g(yw2
zpBE>EC`}otoWvo)kEpIKs7!`On{&B`VE2-2L2*d18SF`uLX_4s>w!)RfkOh<q5S%l
zW*Kl&h|+8WP6|<4-++@s;E+IdoD`z8p#dj_D9th8q!6Wz45U&B91?s{V~`Z0v_(a6
zCxyTvfk5hzKz9&JA#g|_Bq_u+{$EHjyRUQ$ibH}Y)TmA5Zq152DMV>^GsEnp5T*Gw
z&yeG!5T!kbXf7m$P<zqexhTX9*M)BZyhDPKFvCm=QCifbxRXNQkih1RM&^^2IwUxT
zuSo2WzzW9>39M}FkU(*_1uZ>Ovp>LXL2*bRkUAuIn^8C^MCmzOfNl#~da0tBa8iiU
zD}$da@*`%p2XIKxA5zCjAxf{;tq*Wgh|(K1I|5RN1Zp~UNT6Y+4hb|i?~q_uDtU(l
zhk(380=3~C5~!YcNN@?rJ0$oTQ{o*GjAiiNA%R{p?~p*P#9L5RYPXB-wta>!%4WX5
zO;)|KG7bqe3#mf_E0;PX_!-0Y4he+3Ljoc1kU;gkLxP|26X6{aD9<}2*n{t`cSxW-
z?~vdy^1MR=z1iL&fl7LZ1j_Rc31p1iJ0ws^?~p*Z?;R58Y=)CUl!g{swB$1m3ACg$
z4hiJuAmfnWEN(cKLdYS(dE}ZDLd({+{`C~d%)3F2g?ZnULDVauE|e+5ej;wQ#xli~
zlsqPFQLRZWJzs{}vNB+wT&*a3>+%jCpWs*&A%_G#EKl!{;7&@U4haODD58WYLZkE!
z3G6x3mu?u3J6yd(f{499>X1OdJ0uYD4ha^J#XeO3I>?BJ>Kqb`*Ya4sLjpZ5?~p(R
zy+Z<hnY}{-joCXSI1S_-68wrWdxr#iQM^L}A@7ht$U7uhpZ>f<f=`0HLjv{Z9TKRX
zcSs=Q9TEt6hXg|2A%Tz+MU<Kfk=kS*x&evm+9rv8sIWRW%sy0j*92=HTEe;CX(Xf$
z2?V@Dg7ZL#BJ_1q)S8J!5nBH-b`A;js+uUG)Qqh~o|K6qN;vmZkFM|ECzY}e3G^PD
zb3YssOxID7>h&8z8{AMm4DfjMV{-sERxbi9t6t2F;*dbMyWE`n;gCR2+Bx^bAwd(Q
zd+LzjGU|AT1U~|KhXg|Ws?~)W(-3_x?DZf)zCG(geHVu4#Z6wNFIw{PTqCXIONrS1
zXB-mfdzd;TSOO?4A4l=g1Ak88q2WS6;cr}OCUpFml)^m_RFzM)oz2}8M)HGP-MK@{
zyf7DvxVl%nD3yXtCe&=)s4nZmW{AFFcAl#Ckb2#>IU%UqxmByd&Q{eoHcY2bU8r0;
zTUGz2m9(=}^=_+dXRGSnR@u&0)xR}JQ)*|c>fKhE(@674YG8YOHw}LHvsDdjk3U08
z^=d9@o$c|uRkc2bzCPNsRSj&9A5nkmAnA|o@j2?xw#OgrY*ho><4@2=y&8%hqK9jV
z*ivA7{4L_0FLO5yY>$-@ZOrA7q(s%qu|58Y%IR!X1KVR|N8jM`&MM`eRXJ^s8`vHz
z+qs%(+|3;BRZkzuujL*!df3iwU*miOp}FmA+|xi*y_cukxR-(2s$3#8?rosa{1-Ov
zW1zKq>?m^fHPBJrMNRK#U{H0b!2Sk?RxcJfz(99(UB=dUpnX|JSJx9b$iSHD5h`}D
zfw9%61P(DUuKK#bp$44)!o~####iSlXQ2V-7qam%0~4z&lykU&N!8Em7LG75xjI6f
z9%*1ob%BZ<WngOc34uih)~RkOaI}GptBDi!s;!_oTuta_H88)BxS9|MgL?Vx8~&#9
zHy*08sjG?kY#MA{aW&y8#;zu;qRlI=CIp;cNL)<_IKPm%nh<b)A#pV!;QT`3YC^#I
zg~Zi_fb$E9s|kUjHm|sv5O97WaWx^}{6gYtLcq-{t|kPWUr1a{2spoxxS9~aFXXwp
z!!mP-s|npy>T2S<x<f56TurE~TVS}F5O50&R}%uP=ff#Hd{@oW;louibv1EG1NV8z
zf<psbO<YbqsNS!>jyB-@LgH#-DLH$XUr1a{2spoxxSCM=&MzdcCIp;cNL)<_IKPm%
znz)ZTmsY<%lBQ3v9OoAjR}<>g`Gv&Qgz7lIkhq!<NL@_`IKPm%nh<b)A#pV!;QT`3
zYC^#Ig~Zi_0Dd8ta=(${8o0gSRfjbw!zG7*m*8A5e5vN@8=ab-)YZgDev_)(@)F`|
zLhU)fkhq!<aDE|iH6h^qLgH#d0KbsSXlD3&BdK|1ms+u9{z)RPd%NOlf<A+TNOhE;
zz8cQegwpuUkc*qTP}QvDH`0<8Q&-N_L|lABt8_G_tULXpT1V^?MQGfU;LadY(MJ<p
zXQg%zhCe?(2%4rhs-Ts4gUCqBJTVylPi4+(TuxfU-+L(0+!2j$VotsdXzpKM%V2}*
za)ANHdJKbx7eTengQ7iE?g(WKZc;p`&J!3C??%rQ=(I`^H(aCy$1&yPF?0@tMmdK;
znywZc27QeJqs?JZcgA5*3l4)8krTBtG1m|o8Ps3GKhr609n!5N(<yFsI>lqAiYxe*
zbCA$@DeQch(YYn}41_FsWsqeJ76ow|e5A$VC5esscA-H9o_;h4ZYGTVuL%@<r_id0
z@ycUxs|e%fQ!oe{AAqJ<`X}~sgr0p5;iyACY|=yC<OygQLeF0N2f0Gnp!=HqXMPn4
zJ+Qh$m-J`g1xmsSYZx}G)Yp~;!MTK<z38IoT6+h4J7N4L8h^>v{pr(CiiGjoOeC=!
zM(X#h<rwoJ^cbhCIkf3N=vin|!uUa-reuptT>m*nLm2;{?yuD)=AOs&B#9HQ8cAYX
zSk|g4EPmpI@#9o#LRdYGArAZtaY9!)6lW?oF)YjX!-%av1}|{LCYyc?_Tb!2cS2$@
z{ueu2e*dxL7hhlksW$!rwKd80co~UD62`abE+)Ig=l=?8mN35idJ?C&#3g^jbsJ%P
zo2pNB_uKhm5d4$GiANo<AjnM%8?{~wi<g}+@qh(bSDhX<-p{ivEWY5x@ei=Nb2GvL
zTAg>j#BwA!M(511{HT?B@q~#BFw;6KEMLYuP+0uu6DECIoy~Eb1ryfMAm@gyZ&Dl&
zDT~5r!b>W!d6KjOrzw-4`4LHbM!8+S%i-9&J`UI;%54Ie@|4EVRm@E}L$$h#xyj#z
zZ<qUAId|k0l&x3lNe)cie;<Z&L^=1s<>Z{JoX5(AtFOg`>pWK7&sv!YJ7j%FnAaMf
z`5FWgVcm5oG7=tUu+B-8E3~l~SV_B<jcT9uchr^%(|&j*!=co4PGFzG73=xau_wFu
zt`kc9Mx8U5UpfYy5B8^xT&WlyO*`u?C3!xzKTTNgYQV)rE)@6{;4UI}5N4{*th-5h
z8uVwv?1uo;X3${k5ZC3Y>Jlr)^r@%CXxCStTT&#nEAt=Z=12Kgl74GnXNyX(e%B{5
zOF;d8ipV^|2CA)k*7ts->_c#U>rwRGx83i&tL2~ba@}t^3is<r>$=}lY2&j5>-R1q
zcL=E8r-}TTFjIA`&*%-lX9U;h!8G_DeJ-^=?@*ufqQW1OJ}1$}XoB^57?DE+)aO@-
ze2Fkqb*#@DKtCY3KJS0;K6m<_?(=u*bGs<qx}BDFpZ`l6zadzklVR_UB3Pft5?M%?
zsXEr@?Vy_ouFrF6u<!e{=lX#4sVmFY`u#=H?@P4vJi+=M{!hp)g7rI{$hw3Ll6uzn
zmZWS>aD6X(*S_t!?(}`#@9VnXY7}nRLF>BT18HLqg7teVk?RCB$Hh1KrT}KDj`g`Y
zDVq>npBK<z-}h^MF1J2A_`Ou0*C&0RKpTq)*5~a+ZV^zQPY`*GFjIA`&%#@5PDpWm
z20wVuKDVPtA(*5->!ZS`{<N(798Wu41ncueB1Z|R&-;k{m@rdytk1f)A!i8jbA8u7
z?YX{5k$j-5y|16fRB_VphP1Pug1!?Ai5x1ReorTIDq(}9p7s3=QZ694zH6_0&-?AB
zNFkV~`z=Oc`v6+k{r-qHt|3^ze<$*afcowK4r+vinW|%bt`C|{aD8s_-hDny5x$A)
zGZ%$tCw(448wU`q&%24-BA`C&MJ5nts*d%!E$EX3*JsD|?|Gk>QY0UosXlqG?<9Sm
zK^rF$tk3(1+$EqspCj@#VW#R>pS3v%M1t#c>3jD%=!cryi{kq{Vjy>;xm|}gdI;9%
zQA7?CP@m@$`3hmC>R6w*fo>qUK4;Tl-|x(Zk6#7>+lj>qdeSda^79aE*vN<bbA#|k
zxl#^49QiL$cE@n>{rqH2TTTa?(}Mdw6Hy&7l1PN6e%p=2EjudtF9{xnycGIIKjxO-
z5Y#Jg&XDz)>z5tXIQzyR;`N1U)F_NVe7Vpp0`Z^R+^YmfAim-V#PRuDFp6LV;);S1
zh`WP7P1wk+DZW-PmhHyd(eN)A9lwLp!O{=mE4l5tA^z=v#Njyo;!kyhP}w_d5XUjs
zV|RC1gY>ii6&gNU9g1{ar_ipEJp}%_rHLY4*Nv>MfOl(xjcl45*%a^uf}<8^6pUKj
znS^bX@e2_v>lMnH$im_?kB*5YoSQL-!r~W?-o(i3Egdg(eG)efHoPOgt$l!c7W#>o
zBQSS=JGlGXF_;!D<)Bmiypl3Juld}i2!W5!Ao5Nj_{0?5>pRXDRIYvqd}BL#{7&BP
zey;91DAen&=Nbu^D-2bs&GtF`@BmFeBfK|Xa1`?}q>$TUGouQtg=P_fn^Cv6P^+ER
zX1FD&a}Q=SlXllRS8G~FqA0i2m~^0Fg*}CP=)so#e=|>CBDjwYk>>^Us%(qw?h^!i
z7cM1o5#f`fgD#+%t^P=420t&i($cI)0r!yoQ<Z-f@HCNS0xJOT5P3u39l&@_2#+C5
zJCj!Sisw&ni+ODc)?GpJ0+QW`UkACxD}vBQybYDNAlQgcC33ugMtlR2YYAJ6atk&N
z*)GLztXrR2rmRmp909?V=;}4x-!N})9+E=a;F@_0`LEF2T|4i~?D`bi#?)+6g>+V^
zxieRsx5fI{*df%t5zYH71r(aQYJ;!VGR?vM2Xb|?_gyKZQ{Ij6;q>>%$C0<YliYcC
zl6$QIe?DPrZGfyb;ICCszx$s1qL17p3;C%k->&4O=eVT}m#XshGT^_~21xOLotb=Z
zLsPaN*4hB!qg)(YXxxX%h=u4ygy=6sCPZ%tWl{Zu8Sr0g10)};wE@ECX|-1TJ6K?5
zKw+&7kl2d<S{opIY1Y~R;f28~z^XPtwue~G?dEKN+ywPbx!jVkLOGAZWd3gLq640R
zz<+{ZwmWujS7!fG4)-a!VDv)j{5J`)Rgf`mM~W=S83##>-m95bc5lvO^AY?wIO8Cr
z%{a(5w6rNfU5+thG}nMGREqX$W39^p<y=rt7>6XJr%??a1lo_#vz*Q5XxenV?MY@p
z<f~+So-kn!BUFdM#K#%HiNrQ0^fDqcv4=8ele){wIg{qaIlamUlaq}MMn@(mo0n>L
z?UZE0QewjrOlDYNF#C{nWAZiTS{6t~#~YIgh-VV@(^U@zf7o-tu>}&zhwSWcY=Oki
z{>Bza3Q|Q4GpeY0JdSA>ZPrL0Ba&DnxkmBW8i~@~5$+d=7#AeAMj}Enu|}ePQ)?u*
z5RcCRV~s@B>>O~$8p&j;Ce}z4w{yVwAX`Y;R2B6SwI5p}QQXb}7pJ)MZ0}DM^$M!%
z9PnoRkJjgM6T$9<{+=Q(Yb3KFi4$ui?tY$v1&t3ffz%p_Kx&OdAhkv!kXj=VNUf0w
zq}E6TQfnjvLxZN&2ieIQgU$gLx2PzdS|brit&!*syfqRbcK^{B{x7DO-B)@JxVUTd
zuo{i6ktm*8BT?_EHIhG&lUgIuT<9FI+KZm!q7XOCDMx^}M$(^?Xo)ov#Zzk});x`D
zM_Q_iDm%ZiH4-ZvTO+Zut5ZeYnaZgusz9oW`Vyl^w=k-oZecVN=@#a(B2%3BAS*+m
zrq)Qt0a9xun*vg6Bx*XfMxtS+)=1QkS4G`|O5PgD&LD4%L~VF$B&z3CQO^Q-Rn*Tj
zCEgl|G)uiT61`;J8i`to&jG7ayIpj*?Q(FDoQgY-ta@c-tdVFIQfnk?CP-CLZ)Dis
z8i|m%Mk3^`k*J<mMZFQ~%UdH+o>xV^pFD4kM0s8n^)d3iH4?qq-WrKYdR0{Ad21w3
zQqNl>QAw|gs@wP0NWM%-Z;eDtK4XnUOFCnXMD|89)<}-whBI5301lj;1J<&&0~j(S
zl9_jd8Vl=O;`O@l$s#4cMuL`CrlgXRCsaq4wWd|)%TRkV38pZk#bhrWM}YML9h6|c
z4T-(NPFAM3Mj{g(sWlP-Z;eC)^s1=#i0MoBS{JHeZ;j+NHF7}%og9~I7Vy?cgjQ>f
zq?A1ZTzo5E9>|>bVU0u&${hhN<_e7}=&h0HqwKAbXv|&}^=Ob+MZJxocxxnjN4zx>
zA#aUD$Xg>BM}OWL$t;k!Mxy?_Dyr&vYa~M68i|m%Mk3^`kqCKfBx;i*z>`T-*Y-U7
zJFLzPBXdyx770#NQ4c2}wMHV~t&yAp;s~%lOp01F@eyDx{TMq{RK2CCH4;6k)EbF;
zbba5OR7zD*mC~sf)fOkK<RRj9p<c*Ny)nr`{)Z)-Zm8B#Bd?3~o)3ne4=!F^um)0V
zBwyk+O01Dgqi~&h=1HuPXmKRgNHlecH4=-*)<`UVEtyy&vA9_yX|?!pX={})Y`U0i
z(W-m%KeuEUl$o<eGG>6jihqGn{4=3zUwk`{wR6ksMY&)yq07|T#x<+TBJe_`?R6-!
zfgUrHei`^;Lbn~BnNX{aeg?jmFk%Tkj;7*BXP#uFiEVZmX+-jly46u+jv77X1U%&u
zO0V`09%Tx`;OGTh9XI>Im}s046OFq*?TN;Jnaz?_?UdZjeI|BF^c_p=lqlV4%KwIl
z9o~xVlyFX9^>#`wA>-ZL(bk3iSp|um62(_*r{ruh65>$t4?!F*rn-njy@h5N=-Wi>
zUNXdCH@_PHZsPC&jUgru6;Fvnfs{BLq1i}H)d`6>Y~ufCC}#JSB@X5NDIpFOUp;a7
zQ*u(`P;(*TQ0+x>38fG>To?Wh;EBT=->8H*RD2cUa4u;nakwq7XG|Pg;rAjAx2AGR
z915hw;qMv6>WM?mL`od?;%~o)gWAT}L9Loji9-#u58`ktA3#qWO1H-ohiaoQ;*f7c
zhB%am6i*zoG0zZ(ddXHx9I8^gU39nY@=~09v5zCGURfF9P_xhnariBU?TJGnPaF#M
zMI3&MABMh&!yl5@7jb9~YFiTrwR*GrA`X@3iNjyeW?#giZr>A!^2zCmLoN9Xai}Go
zAr9BbL2X^AWozV|ELLac-QWlw5--b822p3mtoxlsLJM=3DXFC72}uduS{vW147H`j
zXm&}onCyjvIGjt>Z4;a!4$G`ePaJ-o5-D*g&=+xNkC?vppbU4$)f0z*QX>g*DBy`h
zAx|7~JVE+l`uA5d;-NZ5c7gd%iNhXB1gV`8^QN7es#8Hv9O|Ro7jbwHjd<elJM`#@
zL%k!OI27{4p^zsITj<Xdhh3n)h(p!$#G#NU4uw2%DCCJlp;d@O{luwjn<R)sVRdd8
z;!t>Mf)nEKzeq@lLjg}59teUs)Q3q?YbLf+qNN{WM;z)cO^HK2sgyWWkFM`)lS(OZ
zs1$QYYYUiFax)2ap<YOHN1H5Uxq+%%$sMg8c!oIChbScuj|L>fp%nP*LM@1dIJEe0
zNyb#2-l_LZ97@H%e74nn7*cH~+Q=>WH4VnZVVef?G?d(<gbZ;wu?9XQ!4Z8u#((-0
zcphQI3R+SdG0_Ksx9AjTM?#5Pm;#G248C`meuK?pN#gzU+?c*QXSt{E{w++wl?(!e
zmlYmlUJ^#&#frZ#v&8nbt1hKpYL>WgH|Jwwv&6j_fmycSTJN7RWw+M*XHa~mW>vOd
za&lp<_s_N7Kfk~iS4N1}djHH2eEP-r1mBhXny21N1ibeWeWSyc7x`_HZDRBLiU{v8
z$~1&~bM*w@-_%G#@CkVDB|_eN$)03E@af+>WW+omNAR^m2Bh9gByS2@rtynV3<}M9
zeqqaY{K|_PsDj>mi99uTw=C8u<5QY*Th6QpCANuMey>)Fg#kaJNAJBvTco{P%ADCO
zmYr4MgIf+zy|vyy*Lwd9%8qL|;IHc-`^o(wAFTsZu4OzZ_s6`Ec0tQ_LXSEWwk#HU
z%%P~|xv8K(IaJ$n*t#Ijgz1fHY`IM(A9tv=<y@gB9O`IUDD-EC2DNM}^rS;WTeep#
z%N*(s23$a9WA6Ddl4gF(uhiiSVT%aopvBbP{_0TJDhB4?!VZ;-TK7CC$o*$}|C~IF
zTR6Jb%sKbm9B{B3yhPsoocGV8Ya1nAIRJWkAA$^h9bG#}H~dB5St7G*H?Sr~D)D*}
zt|g4(w7_w-=H>HI;KNGV>xg56-0`(GTRoLr&_Nibv=d$0FTwXJ?T~#?s64&4Drs9(
z%>{YF=($kk{~(O%r|zz=HP4P4k~3Mk3(0woFzOK6BU3kU9~oB@g0V}vvB9L^9Wgfv
zJR3aP@OC;KEvJc`j^^b45PfEKA3X>1X!jsQ!T7Ax!{8583xlaga&^0g5e!FXoFAZf
z{gs~gyM~XBD~tmZ`(=n7nCwbNX33i41B%;Dp~#T|jopq6+)X6eDWqIs9GED5HC*BF
zk{WG*S9@gO5;9`0Fgpb?lg)ZHM+OcjF4JM!2Cu>uF7@lbH~FdQu(K&-%uGy&DQ;Zh
zQufHe8k-JVO!ar?3S&Af<qH2BO^2miVN8d4t}v#<JXg51RVBj}#&p=bbA>S-mU4wl
zyES{R@XDscJXaXgVQb74E*)jeiNti6F?y?A*R!a+>9Dzas^j^t?O%E_O1Q$MWzAOj
zy-bIBt}v#<JXg5%Y?J2-uWUNZbA>S-=DEU{4)a`LOoxeWmzoX}e=ap0=DEV9w``bw
zm=2ptC2u;+bA?OAoDHup(_tqtBi?kFSQXxMnCA+YnsfDf$yRGROqDV`M=?|qR?W&>
z;nHJy^90_9=`b+~z3DJx8MbZ<ja6EfA0pJ3=`ha~E<NXd@4V?S&lN7c;PSlbFwYe(
zy_~l<yD!sWdh5OEFwYe(z3$rdro(jm-gKB)W8QRFhAUheR%p&}g-as}wHdB(iBr$w
zl*UH}WI9aF8tllxe;ij>R>M43xU_pNO1Z+N`MD;~6<*b9m_1?`aw~I%OP|d}DOb3}
zkpa&YE*<ZXw;I+LSGdHHfs`v;dMDqZUl_*~F0o0_gYs6xJXg4sFSL8Ea4Fd&v}%)p
zcZHsVXvA9$^IYLlsnAdFh_@Oh<gJDYd8=WbD_p7+8a-FIRCTIj-fEcYd8=VU-fEbT
zw;Cqot%eD$Vm0i2bA@F!OpM^vYM6kx8n&if;nF|zg_J8St6?cuSXRUS1zh10M+Q=^
zaOr!6!Qu*=#p?XVjS@!;lfCHjA@#-&{$3GEqp`sqC9o7ZHi_PJx#AW_8E$cuu|yp?
z^IF5MWtJkhDTwVg*I-^tHlshh_30YSYaK&N^=d9@9rIe+b99+`t&i6FbPeXUbkFtb
zAn6bDT3=9qAHw={4d%5zP8;=VD0+|{t|4NQ1k7t)NZhPX*I-^t8PP^uew&m?txw;f
zax$+~gLy4wM_=di_A2Fcz}Ku#*I-^t*&}Ly2)+AMQPk<9x5S#{OSXm>9;p+<r}S6!
zl-gWy9AVU7D6u^WqZ8MKm}q0fV+KM*=kLf_E4lM2;Iw2n9;nr3%CR47S3^Chg>Gs)
zy73dte8%PlmEcIRT3rTN|2iPI<U*+QN&AtslwPkPOgaJ(*5!hK04ARRm~s&pSqq!`
zc`jR#^>M;F-)DrX9jvPsXMlpGL^L>S<8u@`g<!2;PUKR;G!>buR__PhLzun^HLs+d
zjR^R}$)Buy&Ywh+yO6U@ni@<$4g4eUKAE%&;<V5Bv~?~b?N0DImlJt_$a=qvOS$$L
zb1*YG4qbD9!^};vAgxeyYs0L>S9^Ivt~BdT5*2C=0DOsvLd}63ms?)PECmN~pex?p
zoEh(KhSHz@-r>Y>_MmiORqM%xxw#IlhL7UZbm+D{?`ko*ke-yrV)CEp*tR{z%WL)Z
zNGv8R-RUR)m58yxVvEVm{DQ64V)CsN^cIs<EwPw<HgRoxrs&5ncG{!(YAq&Ts`g`x
z$%=o7ZO@fd*S2SK{+q?9n~B)HK#)I0yqj&$`g!`xarrlHdrr|9Br;*!qj+jDSs=BT
zEbBz^VHmbOLOKjHmj7R-nB7-;7=~@nZ`5dPF<J4|TTK2VIjO~D&4mubsJ-ZUE(&qO
zb)gOcdyB~f;Ls-99>w3?V)DU!bz+OjR`|WPJ^Rz(>MbU}%qUiGF<CQ_T1@^EKc=b0
zWF1jWEhg(!YP#*&0+4Qd)O2bwS;OpO+p`Uo{I+L4$XiTS8+~ni&gZ85w&yIS#BY0s
zFnDh<SufdYw>_%VZWrBcdyg*qc<|7^N>;tHG8U6H3w>;RbnMh`dxX5jWTC#cJ-3N2
zYt>$F)oqUsR`z8v`APD;#bmwNeQkS`=eIpNkJ*>SWZk~s_FO<ozwObI&sa>>lFnF6
z{s(0<7L!llb~4+Z62Gyw?a{Ke<12XzWaiyqJn!o<h<YX9){5!wC-#rlSf;p=lE<W7
zw>7Dy=gUxgItkHyifTpKTNhhQmNX;&Y}s*X?R|!_JiWzaoq|p+CJXdsG1;Coed&hl
zOibb}CcmjhBp}h=N5ET57V>+a1!N&0v47d)(%SnBV`BTTn5?Je_dY7<Ehg*Byk-`Y
z?_?<6VzOQozxNUHdmkac_nAz8-eU4bpuQ|7tDfKc2>HE_kl*_V`Mr<ODtn(PB&utB
zew>IAR_BH}5hJ`!f)k6$$B>ZjeFXg8=S&bMV)S)V)S8KpOKbhd*jY^0tD0I&u1$_h
zYwx2TUEjY<Dy1i4l+vlU)fOkK<afmDLcNupdTo-0EOmmq@Nc9<TA=-a)_Z&+MtdK9
zjqF5>_CDtVqKJ~SC^;;spTxi6gIb|EhIA{*Oc~<RU9Xi{C5|?3RKsSDxaN?0Egv&M
zTxo1Lj`Gf3mYE=~yy<eaU#MhE5LYrLh$|Tr#Fbtqh~=TD0%`u?O%TgNj|?x@tGU=D
zaFspMvDW$+ZtSBqK`akFgJ`>69VGp+N0QOt4`YH@9(uGrs#il%JC_v%d%EnAmJv@q
z^e7`bgUcYOc`K2cATE)TdgxJh^uLtbWR-FgR4(z*qwJ9<YkTutB!YC0+k)sg{^yoV
zfTSLEG>VotHf^YcdJGb=b1+5ArIB)XAZaVY=!xUVzqwh<?>z7q31gPi@b3ttZ69=N
zL78`waT{Um!}M}9wEQ@B9w*Uw&pI@BCW&E0BzIe7yc8^7r08D=<Fy@WZ9uD&Fn&|O
zCPd~CCaCzt{kTlJkJ^V5L0BT035~L1cVcl&mMNJ08+La&m6&2Sey$j(5lztzURlu%
zPSJkwD!Z|%Y~#LH(RAQWl)1^BkrUAFa2{_(ZpnPc?(|a67@%ejWGs6UY`)I4=B@yK
zTS;p6^VaNg;NygKOjF?ONUh`-@3$`Ifxb}bp@R{PxuBD<u2~8Cf~gJc1fEBj)^TeP
z-9wG(^N2j8$x|>RNZd2+jKfUNsif>!IO$P}{f=UPqR8giV!4?rbrKucH{<N21xt0`
zsKcmXOACrj4`wz~+s*KDOZ3d_0W4-j=Me1C{D{bP0(xkFB=QKsp2~V!PMUMS^Q*G+
zJBT?|sM)+Ya}WM2<QGP>qy(%G9hfhgo^BZ2aIDB~JO6ekrKA))NA2-<)l1a+a6VbX
zF%xNHYttRYuj@<%|A~Lr@q@{^ZwMl`Aj~MphL3OxAsl2<t?+w_4|VaZ<ZD-@Pixp(
zb#GF9W{3Ef;RTAX@8Un2PJA;LZ&mtEt$VA?&lTUh@fyYDe5X$dnp8Iv2^ud+de%<q
zPJ;GHV#a8Rm2M9MuU3LKkPI(DQ?*2bb{1{bhT+v3>~C$bb>TP3Po!yzn~nw2G_QbL
zniw@e|0UZ>#XrQhvW@E6R^C8g(G^@qkYM+f*;Zbz{{GF|$`>?-cw4D>x~&vQx0SjB
zzpWI~w(|4*mx~;`uk5yR4wOf-tyFyV+scoVlWr?D7ur^;y=Vt=6yk>K!d(D<TX{Mt
z*;XpP%C>SYX{j{r5x#Ztw$ci}*S1n`K)S6INFDL)N?)trR%#~FZRKVVB<Z&D2tc~6
zl!{oot^5HX-BzmUbX%!m_OY!L-R`%Q_k#SkQf>6Lt<<aOx0SClC4O6ZJcIY!O1*Ha
z-BzknyIpj*?Q+zel6mZD>Xnt*R%#ad*j9EyX8LWVkl$7c^|h_+;+L_nZKX`d^|h_s
zj6A=s)SKPcwo-Y1Te&s$`r20N_Wic<Z75v7t<;jwY%8^-Guz5NXf?B~T*f?Qwv`8y
zYuidKTiXL3LV?V@8;rM=qPOe9ttrqC<A#BjSEi(rk|*>Tl~FCNI$ws`-y|W@3!}wk
zFI=o+@koL>3Lynt?I_RY&isyYFwZL8Q3~|6qqIj%U%J=2P!0PX<(_IJ*-;Ak9i@=p
zQD&rRhm#Qx)%oB#gZWQ)ls&ZJrD=Llen+W-en+W~a$h^jqiMuT)5g%F-%;uv@jFT(
zzoQiLJIeFv&+jO|3+ih}sd|1#DdcyQLVian<ad-ptL!NC6Q{0ilGsrSt8>HbD21gc
zYdG0a{)vQiM=9WUl=8sJj#3{cMXlOk=L=R#KgMoHskb!UQR+#hK6uol>w79?tWvt8
zR7$5_R9l>^k`0L0g?b@7^~NL%**V79o|H)INSi!sD6^x~hbY}q{u2=X??6b6(ak5&
zefWE5mFTcmo!<$sReVv~#fmS5T!{X=`A>@9uk`OVzoz)^ivOVbX2ow&{D$Ux6#s_e
zH#I+`ct6E|+5DX1*QlL`OlF_>jUB+2rY_V%G~EvT##&rE(f8vwR-S7s8PBzq*mJEK
zJB==E9%9e6m8;v2B&lKAJU&I$fzfB#)l};kW_57oA^HufTL}!Q+ziN9y9GKcuK~hp
zkHFAsp88RB1A$?cKao?Z4i*?*c@9up{j)%qwN_t!nd2<g?#eynG*&lN&Xmg60Ik)9
z0#j>rqH0i8*72+BSkBPuu>$K_&gkk-1g2R|PxUl`>6Wuj_1jEnbw=Gav^Jyq4}tY+
zF9yu6eo@6{+P%%e<0U<u&21*rV0zL6O#Nl}x|FQ_lEoi|y5EDMxh4If$(<_9q&BUY
zQd2H?lU;zR!b~<j>1|2cg3!JF`P7)wqAFhmpG6p9I??Nx<m?CFYY8L69|ut<g+@7@
z=uu85T95x+rgQY$YzGvoUo8eBxQ8%!hmC8zR|whBX|M446+Dvon48-w<ek&Zd=%~m
zb^U&<eU{f{dtiHk+`4t$+;%9MKi^Zoz2c(P^M_m9PP<9$!xn<m1o_Jfw-GT~J%4%a
z7ZsOYO#X@%r3cX*F25wysJv+P{3SK)Z5*wh|4vzbIRiQQD~tb4Jf_w2R~1yvX!ZQH
z0}muFu@7^XSj?+e-01VLU;kamcc<OLiP5QK7+D!kZc*Im^Kgpw6`FyZa7tAjJ4cz}
zlvV-fC^MWgP@u7K_hW)^YE>kR=<_lBj|Ox3I>GKGq0htV(I7rPMxTf4)wuhSft+xr
z0cRj5oMpfn$O&f~a0YV1^$j=!Ieg93fHRO2ZfL+6$O-2da0YV1jSQp)a>C7{`5J@h
z^Kgrb;*LHKx2zFx^m({dMRyR>=ixSnM4#7?dKks*zEb);+%@{48kN{5+^t!0N1ung
zmo!LcASaw(b2B-PJ`eXCqPY-#uJ)pzb5V#Jt_vRk#PoT1RP+YO=<{$<lj4p(507@u
z)5sjs9DN=>8Ep~jK`so!WzAMt^m+J{d#Eyy6FzNm=O{CLrsfk=cJz6;+<>Fc!)Kcw
zq%TLGhtF9ZXCNnhsiK*1^m+Ko;M<^99ep0YI`|oYqtC<F>#F>sIQl$%qh<ua(dXft
z*0iI~!?$dhjy@0Hwtk#}oG_Pb8b>8ZpNIKe(=3pq&qGeTX?Tu452Kvba|Uw4np|ZO
zH|6N_ur}9x08`@V^RO{j`xbeQJ`XwVrkBjo=V%Msa=}23o|`JQ+eLTVUe!hE%=eLG
z)hjEe&qGeTX%>t=4>`|m<;*}%xGY~49qH(EP^*xm&p|_k9DN=>osU${8ORBr$w#6%
z9DN>g+D&=xv|IRmzTeg4Ir=>0w43tWX}9oi`HFbZjy?}L?WQ-|(dXeSuB0=N6RvQ1
zjy?}x&9~l3Jx8C1oOV;2?zCHori^ai(dXfyLRscS9DN?*C{s&5rq4r8yJ<<s^m)i>
zw}&Yk)8`?l-DF`frq4r8yFE^>(dSyWHt$a`k(qfnsIf5b9Sou_ypsa`P9Z_dD^pTQ
z$rE}(WmHS6&X=Kf6AAXU)nc+24*Gl!B_$h*zgR|}htTKma4U{J4>|3&m=Z>xhn#j3
zaP)bIk4$yt4CI8U#MmRIFWqZhsD>SV9&+04w`xT6d5FYEz|rR+r`?1ceIA~WYu<`1
zBtH80G#T+w2j0(?zWh%}7o*QZPP^$B!_ns)1!&fTa`btKN{k9R`aI;cn?A~pJ`XwV
zrZGDMIU%Rr_5wNjJVYf%yBJ5Ghn#lPJL2f`5S17qN1unN#0WY1Jgg}+R(YI`J`XwV
zCi6UwJ`XwVrvBV%x3JdLbM$#w=a8e%!+M7teI7PA<mmIT(IH2lhxo`;n;6K^Pn^28
zNrFBXR_BJH&xOY&SoC?wX}3?2VDx#|zc5h1(dXfSLdTvU=yQEP6}4ud&o$Fp`Y|5#
zV#sMXy`@H<hn#lPlQQ}|MB<|!UEj7>Q0<gHS4yW|R9l>^lIw`qg?d>#^~NL%`45&X
zKb(=)(ThZ^_n1Bpk@)CCWb}E6#AgA(PPi2hsn=2%F0!rER@6il3wQh?jAElP4@14j
zgwkd)p)?OdOMg2<sDDVN>Pn1MF;DXu^?*W;W0;CyDrD3H!c;w=a9QDQhGGO$;qqE-
zFV-53ff|Hz`PW($Ow|LhDCpG#idpr5VlVZ8;(MtFU{O%#qm5uHX4M0VS<m9d`88fW
zp!h!21Bw~-fa0PiuO3iboq9mgs|OS_>H)>4Y#$P?&Z6Mfti`oPV|b&B5KJSOjM$>!
z`%n)kX4L~^6kW}Di-KM~pa{X_)dN5o^?)J-lj?bkf?hqK*h@X22*Kpl1B$)W1Bwt#
zUOk}LOFf_n!K5C%MZvTAq&kAB2*LCVzQ${f#xOxfFco{L2NbjF0mWYG0mWWU#ic{s
zmwG@ks~#YWf?hqK*h@X22*I=i16gY{27<|}2NWTgym~;<I~9N5>H)>9dO#6^$*Ttx
zA(+-wJ)oFX4=85U1B(9|^#EBEOw|L5v3kJ&h0&M}$0<91I)uw&i_eCawG(SJYcytp
z8IAcL=+nCh#wnX<oU(RKHnk9((U{5h8JY>6K^U<ME%i1UvoR!`LJ20}9b!=hm6KEY
z?h9m`G%X1Bi0Qj8yzc2c8I1{7Js=%^ga@RHnFG?Lp87>hfti&q9d7Z|S|B5VQ&!3x
zkS=8oNSCf?5ii-D*83|FJDng-S?Q7*CdF~eO5brmC1ydUbY<~Y3dRSdOIH<C%??PH
zt{r$b@jeeom;3cUo_xnCD^H9h7&3aLJh?@2<CK-NdZFbhRsB*pPFZ<MtAOK_m8T4}
zUnz0Q%2TUXQvKZzNS8AQq|58sFRUZ{%2`v=<yn^FIA!J81{|lXyuJa)DJySaz;VjT
z8yaw&vho}Qj#F0N$Uw>|D{mg92c*l{1JdO!Yy1J}@>X^vI_8v>-|K*MIded|yj!zB
zAYIN9e&zW!{(y9O&mn7kK)QUC9nmvRS$R>DKOkN9gx`EURnrSCKN%$lq|3{i(*x4w
z4B=OP+7^@Jl$D>U+25Y&bxV1pmm6@LvhuS{I)UssW##9rj^mV-U#j>6(&bkM`vcPD
zR|oq8(&g9dCbPG5oU-y8HQMMoPFeX)Yua(j%5T{)9jC1Pw)NvUWo0;J+fd1I%F1xc
z`~m4QoHBnvx(ugGtI=`F%5cig2RTkz8BUoFGC59J8BUo$AYF!2rkBid%F4Y7KUMOl
zYTxyMbQ!`gJs@4~MfjEBl<BCf<CK9~?cl8Gg@T3%IZj!*7vWciQ|1pymwOR@WeC6R
zkPA3YS-BVCSBCK0M{*Cd7FdSx)0;h~wT8PX_agktaLSbD2){Cf-$B%KgkQOrUT7Ik
znLi+1hEt{kqK;EmhEtX~AYF!2mN_6@hEpctTg)jd!zs%gkS@b1JCof1-~-a-UI(Ph
zP=7b_z>Hm1hWZn5?6Pt%>aPs-XU`et$I1t!%TRym0qJtD1JY%vKYu{F4E47_FXw6w
zNSCt*q|30&^fTkwWo6i9{(y8Dc9}mQU4~ue4@j4LDTkI}mz_o<j$KxUUFHu+mtmLb
zMRDx1GVC%T$1W?wE)#O>vNG&4e?YnnyUZVuF85LnEyFHTJ;yF9!!8qY?6NZKG9kw<
zD?|MWId)kY>QBhA%gUbmn?mCIIv`z!`qP<cW0#eo{sbJmtPJ(HrU#_UP=DzG=`z$`
zdO*6|*8%CKOX=v~T;aM%?{Rg&Xnw(eSna4MwR-(VfE%ix0z6***c`x()sq3ssu%N(
zE8Jv+)bi?y0ykInr2kS~B5+Id%QW_4^O1-S3%6Czpw8%A^F1R$Kdzn+8k=kWiwfRu
zX!9J4Q%AIi=zEbI(f%*u?uhmfy|{@${S-?+jH?~dzJQ2PD*2#OY~gZzM7#4`f$S0O
z+bB6SsK1VX!*oPD8q%$#VRv#!AaX~vjj<OW%P!p0ga~=(Rz2Vb-PMfzZjsDBS5N0Y
z@_X2KD5#z=3NYV5SlvT8dm4zU_fjXnmx0>q0)f2^G*(Ymv3(4*R*zK!`x@w|?xLLi
z3=FC+71-av(CWnk2N>wCuFF%(A86<7M_1PqILN@5>Jch-uz|7Frvwf$Fs}N#z@Y|u
zs^@4p3k-~}&Qs1p0~4xa)Y@SNCRSG{=Wqj)s-IV#BMeNgj!>~94NR#nP_d&7Oszg4
zu*kqV)hz{%Hn48cun)Hy71oRP&@8T?xx%alDVYRSTPU*)gh9P#dDxrE-*~9XHgwa>
z?7}9Ie8t$j7Cs(V)Vvlx;VRm^7Umj=Y+ehS8K|{+Eo^R}(dM<Vg@IO^*TR+tI&5AG
zpENMY=C!bufuT09g{=*A+q@R$85nKzTG+;bo7cjp3{0|lEo^IG9h=v}b_Ql(-&c27
zW)2Jcbm^uVuHrsw3;RW9>JGKQ3I|wOx4;Sq8gL7&aFBs0sNa^t!*<mS96nqX8y+G4
zX5q-_G<edDhb%ZWC@gCDJn^7<zxq1bz@+L>afOd*_&PazR4?J76h33%xatAw`B-cJ
zg6bayK5Jk}^(z9$8MvrgD{y?n6*O>Z_3HvBSkBee`_#{g*3b8=o2%)QEa&m+7X(f=
zu&i;P!{-NuQw%Jx?yQ_s4g96rtkzC5@M3kLa!xm}qWXkx^m7JY59+_p{YF|mx(jzk
z-(d~PaLM7D63j`HrE20EotmD8uhMp7VM$cxb5z|{9bIT`2i1o)gl`!Lt5XCnG7wdV
z2z=W>ZBTzV%?w*lNmq8M6<g*Lh`8?U+UZWQZAq%5;PjPjXTKP<D~%7_(|m*KLRGW#
zZl6s{TFjKPdNRdT6~Py!tUG;7ts}(e`qlYvf;)pqN?g~0`RFNm*zQbO^@%}B8nzKP
zTw7^VJW`WS5wUja?7Dj}?D_F@G`;axNr^m*W~gPJ7!3QTGG{fuMCR~^sGl2?E9=gR
zg}ab|3=i3q=MK)b=$l?FT>aB9>bj3o`7^9g<L!vd=rgxuF>Q7~uljq2jXaxRTfVlR
zBy_*Ub~?9LXgX-8lW-zoL^l<`OBH9ie>-QnpMxQz;&bk5A*2lVN#mpcq%M!ME^|5y
zG6p4q3v)w6O^>xszm+q-!C33;qFk$ei^jDw_`>p>ehv#g9}{@Ufg1Mx!*pwfhX?7-
zg7F&6dGHDrT8B51KVd0JH!|2C5GLFSc$UbM0uKN>F@exVn5dc$Q`0WpRA->yOzQ7N
ziTMPp|5+lR5m5cF5Lrx^w2Zpy53{!UlQbd4LhB-APr;<6tLAiA&g9dX4~6>fQqT;0
zISgJqm8(1Wzk&=M<~d1|$KN0R$(TOe!T+@~D!vWHEUTiJVO12TRu}Weh*dF}|7#r^
ztaWU_3tr5cuqwV$Grp9tDvEEK`6<V$C}vGq6|=00BCLw3RC26}BCHCjHM>JS#a<??
zioIABMOYO`tYcP15mtq`xQ<m(gjL~9SQUGjuv#ml;-kA(M#aimE2Huztctx%Sjo<<
zq(qKOAv?E1j!RL5OW{pe72#5N6IR7uT#6!G3e|I5iXvPJA;+aC!le*$T#Dja8I_3S
z2YEB2ZTb4WPQ*@G$A^0UWiqPR>(z?cup-WD(C1Yo?B4v(EvbP5OT1p`Q~Q0$y2}VA
zqjFxa-U7a=q=gHP2y)}<)WFPEbXy7CrS)m0$5=22g7+o36W$Z-JAMxMY{JNS^r*gi
zpYR@)c)c1uaSqzOgwl6w0_kRk!JN;fRN>}i)JzJ3b7QKo=544#iL|i!Gnvsq;%%rp
z-ycaFk=CZ96=SN=odGYnGvMel-dLneF1kVg^2Kv816IhF5AVmnu=oc1;ojt8UPqcR
z{i7E1Is;yGlC8XsG!>m>D|`(Wjn05;D5Y@CP5;=?k!%$+lC9!*%IeFV0WT(!t-O3A
z6rE%%|2f5bOSTdn%_)#@`P<tVMpm+gj%F&^!s2Nv*}~$f`f_K$v3M%rBwM8^tpZN6
zRhlwTz|Me|`jTwvUf9mA&h(EeJIPjQW{rS5174bCz)7}Bvkf@OR%v|$PO??nz<`r%
zl{PfsBwM992ApK8w2^^SvQ^4RwmyvMAKh1a2K?Pj|F|0)US{sIk}WKru3oa`8eU`5
zKh`{7llhD%)zM5OTUb0zC0nJZ+(Xrorqa_Ecap7AR<eb~)BR~F)zS2lEi9g@FDKb5
zWhGl!JoS<-ES@&=O-pq&rvXwO&3S-SM^jBZauJKC8fL1aseYVfs|2~Y1C_jv=Dr}W
zqv<7ECCEk9bCRu6FUeM^mt?EdOR^=4r)+;SI+|*QBTf3ZI?0yOneVUiO?+3=KUU7p
zfMeCP`csDObu@*%j;4^;(NsNmq^X2t>!<uScpXjUd5fo?h6UhtG?nKqo*qb^*U|Kn
ztrC(gm2^j%O1&goB_vx5sprT=Sv*xqZ}C(d6tAQCO-AN*G&7PdSv<{1wq)`2WLnMW
zXr9UqXLK~rA=gW`)TcNd8Hu7nr8Dp18X4PVfKoH|f3(mtbuOWFdt9f3EPI|>f4&U0
zXOj@=)zPx5(W@8R|5=n^9$TWVIg~Xzu)dCmCEKUBQX<vX6!6-b>eihGFCpI2<BjM`
zcU>2%;enU&qf{^3r#U_gskWwo*VYvB+L{Z<ip5(^WW+-qbieHXjMN%=ne`~!r}n)y
zk65yOsz>IvHC51SYkKjPY@ce(?lib;pPmNt+M4$<X0NTOx5aB~3VCf!A+N1DjsCp0
z=Ep%^TT}gc+o!7MwKavjwx*ER))eyEnnGS%Q*Ck@d<u!`+9oNs|D(<g$M%1ANN{_A
znkC|`<4H)hH3hu3<~g9){*R*845z_0(|QSFJorV~KGpj=WEX4|%J!+A)R4y*jqLxZ
zM>n>Il1d#xEZ)jr7wKg-@mBta)xq#Bop>vMLv=@h6K~~jtey>U;;sBm72U2AZ{@S%
zt^6&`chZ;>Z{=^RE~ZW_-pc>D`fX4w-pb!@$i!P3Q>Q)}_Ij{RcPAcOAky2Lyh>+S
z@*=L0R`NHA*!^epMfK54^+jcYD6zPz#ppy;(QZ)<B$Y`LqO7PY%8II@tf(r=imIZl
zs4B{es-mo@D$0tgqO7PY%8II@tf(r=imIZls4B{es-mo@D$0tgqO7PY%8II@tf(r=
zimIZls4B{es-mo@DoR9Ec?th&obb==I}K$vhX?g-lG{jlSQ*l-BoiK1I@`2ToOmn0
zUbK&9UgE8MR=kx@#arvEqQqPIjfbkN6K~}=i9R6)y@?I8;;npEyp_+2xAIx>Rz54<
z%4fw}`K)*=pA~QAv*N9MR=kzZinsDv@m4-7-pXgiTlrMHwMchZ9?c!@)1{ko;;sCC
z(K)(9iMR4u@m4-7-pZ%qt(_=r;;sDQ!&T9Vw~#tYq-El*{Gx_05_jUQ{Lu!Scq@NQ
z!-eEH@mBsb2Ap^+pA~QAv*N9MR=kxzzTp}gaN@0eR=kxz(fV=Xt$bFzmCuT|@>%g#
zJ}chJXT@9jtavM*innBb*2G)73;O_69oC=>$KtIYCpZ>w<-gIX>2cz%{F11a&yk6@
z@>%g#J}chJXT@9jRJ`?bnlbTK{>m=3VxRq~L|pfFMZBe@zYVGGXJ4P7cAWreR~jEU
zeTM2nRkM;Or6nz9ga>azT3l5JD61~qm8<osFRJwx%ea1!;LadY`Fj&wXQg7<Rdsr!
z3R;O}M21^tEW4`CYWy{6U9;w}iEhj39?oN*yb1qvOO9cO*^PCowxRmc=C&KLPzJ2}
zb!b?ZvZcO=(9MRty+gy#?a+-slnyg@o7-{ZVHC>s@2|VRpK?DXj9OQ{46JIb`NhYL
z##{9uqsN=uazP^@=sJ@U<wZq}<4nfE!)F}*AYw)^j;dMF8biSm3O1VBuFuiKR^ZK*
z#%Sugbl~j>&;q3}rg|IG1)%c?V{Bv%HnRNUV65&JyHv676aH<F)hhn&AmdiA<aQiK
zp~B*THhUxy%P-IA7ql>560!V44wy77|L`FFxbdr}9eeQ5nOvPr>C1DROzCpn4}Xsb
z_;HE31OFChiiJ9uCgEZ`O0ueB#m5+8V(jS}#bd{cN)Mv#xV%6x5om1esflN|T4PVQ
zP%u6gi@Ow6>+M+4$$S#K!IJ-ET`js}vBineC2C)K&&A0tircZ+V)j^UF?%fb-DFKy
zP+hX7&G;X!&*dh9-3uQJV;&TzN3*3il;cv&9*h0g>O-BZF~qJG6;GXL3#3l8bqDdW
zSoEQULcR`T_`jH9c3&y;0DY*3)u>J6Zq16XUe@#na#APSnhPnAtG(zsE(&qOb>WKu
z??k&l8y7nki$0X%PJuk552eN9m<Q-X$(K^>MB55Wf&AU{p?0Qnst+aLm<PpYn_glR
z?pSOwdn~s2QbjY7I?;Zt2*FsL4EwP7>fkbOv|}D1YZ?b|%mZXio9bOpoM@}*RMw<n
zI_AMDvL>CS^|Gd&L0;CRHk<<as<NiDxDR(MR<fqgGbLWuG?>9V1#-!n^pd$_u`9`%
zRH@xAy4&_~y6Crrhjt!W^~%aP(bg=O0{N=?P&z#6m<Q5_5^~G~=|c%Q=E17^P%;qX
zm<OxsL)}lFV;-!k5A_&%j(H$`D81S4SnR6$P|EZAP_kg!m#j&*@0bTgj>UeNl8$*$
z<XEhhe8!2kmUPC6_6o|z%!4AwVvpg5W9C7TW3e)cYRm&ITRWnXqd;cf4aW06gF)1V
zPcqZ}zQ%*l^2(G{Qu2iKV`Z&r)%h~i)=_Qy+G;V`3kS<UFVH~=W*v)VAbqG#R;Kr<
z_ybB9%Ru^20*+;{sy>uGV*1j()`e==`&4{QjYxr9`cMLnWgvYhA;&V1KGdFM!7|Xl
zl2``z`yM!-ic*d?mO-)CiCFnm)Pr&?1Nl@`LB}#Eaw1kA<-VL~A5A}wWgwr5I@9Y|
z29h=D9dRrJ$(n?`tVzhrnxr%BSO$_c%>p@=!K$(*)$_6@AunqZ^0Fo&$1;#Ul#pW?
zWb~mXlV}R!nj}~T!s^^64VHoM770$AXdh03u?(aSCE!>F(uX<)1j|4lCPl3oSO#ic
zOFzcWiMHO-)QPs9RO&=qJ-WW{O)8}d<Vxw(i)xFLRq_z=x==4<r{0)kA<KMlT_}s*
zk=9Y8HtcRC3_Tw#S(83Qwqch()RzE>KGZY{*M(XTi4$#$|CZzr>O}iG$(qh@x|kdL
z9TeW){Ld{J24xn@n)+)ncR~-|M99dR8vF74N$4`WspD$(N&O`F6H43bP-xa3GnINg
z_%j5jH#MPF9bE*zkT4>=BZ$;j>}=be)7rtE)7lXc)Vjw9fkNrF{=x4d3d0~eTff|9
zdi4G|oTwVZw<o3+>kCkePHdESVxznh8|9tY2uf07BP<U|Y?YcEG7Cb8ln!9bu~nkj
z4w0D^LQ8&EhHPeq(30Os@mNb<@l;t#69=R2y|m<eC?;=sH7YNvu#j=0SNKj@eL0a*
z;mYDA#ACBUg^UxuLgGZvj0hF`^`A?*)ZO-Hcn}E<sCZDn`$3#4vX-3y2^vt{H~|tg
zpnww~ao$Lvu^!bZ&KsRb^;Vo4cJe<$t{8lYU?Zo$ga&NR(_c&jy3xlv@d8eORGej|
zuABg=INN{|AQjg)-~>p;4GcH|QgK5APJmRLW55ZJiW?ai8Z<89ZH{uq&7&PPhL{Fa
zJf#5zPHK7v*&#adx`QCs^a-SH(11ds0rmOWk79OTok1h^vx0MT(12H}(U=BQJf#8M
zjY)unPW<=DNohdM#hFZ)+KcYsq7XOS5Z(i5uA4*m5jydI10^(|;wcSi&Brb!>r6EY
z8gL`t!g`Ddp%ZU~>m3bfW$O_j6`!^T>;y=-+m?yklm-;2Puy+aOJ6AssQONT1P!Q}
zNNK>k`Atq~z!iX$1{Cu?r2(e^dg^ySYR`c4MrwKzfMLF6!<+$tR(;#XHoN7M+L<6g
znn9&GE&rrDoi~~b`dI7k2h#-Sjnu{_Etjxq6b-2HZP{{_DADA+QOnDNK+u4@GbP)#
z9JmfBId9Z*w0cO+8@0^g(;^yBt?V7N>7Od~vy1Mw-}RzAl+Jt~NLIVDGBlv_TP}vN
zAsW!iwOp#_jsWRWh8?!t$)`j#pitBzmwBQAg=$;=(F#H}O7$9B?&aH4M1XWDU;fq>
z9kLP)sJuxn$8dU8I`KD=w@%Bt8aAp?%A3)$v+AK5^>gxOx0JEdCmK+1_MDa)Mk^Xn
zB{yjqs(J{JlsC8KcYGG56aN79wrn|6lZ^mLCFivy?zVM%+qL|Bd-9+GPo$)$0kz~a
zG@zDrh6a3svKbn1A8sc@1HM2mG+;w`6CLnP{xSdB6>kW&knKr43(PzTgBl%W?oe?h
zG=#t4+IAMHT6LM?N=hEwKU79lwHSRFY7ZeH(kEAI%-%ytL*bng%$+Bs;j7%CCk-#8
zMCxu^z`NU4SKi&WJ$d@l6f~HHAx|1UsYVjgP{6y}7V_@4XOabJsDH1J5f9aoh7psQ
zy4&8H65idmo}YKOt%Ba&w!YQg-L}T;-EHpx+A?*wEob81-L{Sed3W1F-rcs)ku6P3
zl#U^F(BE+_k89OI8jc2?*79mQh+|0VZ%NCGe4x`~NG+ch4W1lBYFXY7lpI59sneU2
z97Ae(POCLhm2bI7?;pxiY7=Ra){(llNrE&KR_BHx4TWbUI3W#pC!uA3efc2`1%eh?
zs26Ft00e2M&#I!<45XoET5m**9cieSHzf`Aq*BsQJ-WVS*upBsq+vs-luo_Bwm4ZO
zw-av&^`3U>MM@U(GnV{Yu8|h#TSTm(%rPW=pHk9rAAot%D{X9Myb`&NmPI5tr!yf8
zhX?Hw`DaoHRG5^Ms4!_l6C0j;k=_uhW@5wB;vy}v;b|o&O2+Y)kqg7x`0mxbHOSJh
zrJ0&{tPK7a^m<kBCh-zAKfE`I3f?5XLrd0N(mLKG=CkU$&Ewuj>rJA9HwpHzfpw7d
zhc}6v)Sr3W>;CdssEF<zx#qibW1!-?Bd%fh*GVaMZ^5<Hy$RQH_YI^+LGfAsRq!Tp
zL`7dgF45aH*yJZ-Pxqam{TIZ|n?wbVd&-Co<x=3wZzZaBje_<UR8AiEDtO#ec61LZ
z<5nprv6Fd|sNiu=*(0Bw#h}OK^t^VuBZ%&2>E)Je#v9-~CX5@Rg>^eL`Sk>IkI>Vh
z?2h(aP)iuS6!0Bd8e^^_CKXivFf#Tbj6L`#LG(Ea1mhMGV@DCJP*G9KxkKwje%wK^
z9}{}MK!Gn)^f3yImm0!sh7(M<oMg!`#-pEbvNG}~QEOsEa+oFuJ#)eGkk^q(TT0rE
z;3;WZTz$f$<lMD#DyzJm>7P{A;D*?YXb2D$%!qEn?tVyv?*0)*{A<Ew&6(Wi1yd4d
zd6oMcrhJ+^Q>Z-9FeP!ESGl!eYSwYy)apb?J3{HsTye_fL=-Cj(=g@P8&UQkl%6h{
zncpyY^c>ca+uZbLbk*@3MO3H!ttfd`_($g<e60zv5zMWfms_h|!S7$P-H|!4bi1P|
zayC=fngCm?UcqnNS`%P<K%Hf_JIf)|jOG0w=OKKp39!~9TUfGd)hnDr1N)jDKIg}3
zXQ9Yo4%_{QngEmLX{o!UU!U%u2GQ^MpIh=7D7WE9Ob&9>+r%FTFhKk|^x5zurUbbe
z^-9{9q?v@S`IP!tvnrefJkF9RwTUHN47`v4H+^rK2`*<l69&KeQc8dA0{taLhKRkV
z{&ueM^jECUAf|ojXt83V&tSimPLUyWiVVo?rN|IEj&$fa(xKx>hmIpnBc@0ZIaYM6
z$e^bFLwy)eXX4D+V0<8<K?zw$#*Lj&_Z?_6TtS8r6=*Xk9yGy>Mw`Lr$t>EV%^;9!
zGYF*G3<8Z!Fr(3CxR&ZVkgzrXqmOa9onVp^$|Twh8;gh$Gx}fd$hg@tqtRwKLt}_N
zPAQ&xoDw*xMa<~ZRu$brkZTb$8b`)LVn&bU|M?WN`|1pu9Wxqj1|2nU6S-Tn;*L5i
zW$kpK&G0xmsmCeJg$^XBy-4Q|6yk>K!q)(;jmC^F9TiC|YRu@;q9(;1GrH8<PFJHb
zqf1XlQa@^f8I3lB6>fqVjW&Zl)F!9R;GXHnbg!$^W@y@d&wYc^vrT_z6pk5<HiPP{
zUYkJz;?(2RduTH>i5Xpb)0&<HV3=>&FlPW5XRQ3%CT4W1&Cn)hbO~m(X*2W_Gr9yb
zTEp9<P0VO%GiZEUwuu>?YBRKn87*xFN$Iw06Eiy1W@r;LI@M-q6EnJ$+UYWBpel9P
zMbEuMXW=^32@mZXWHl(Ozs@dqhb8QEX%^bVj4ma1y4u8yPPG}@#Eb^D+5z`AF{434
zglgNwj4ma1y4u8yPPG}@#EecI8MlcUU4j{{<6G;ri5Xo=>~yt>8C`-IZQ2ZNVn&x>
zM(fR<(<WxLv>9{<o3x1;Eo}zn&21AiI@M-q6Ej-c3@SOVP0Z+0VyCN3%;*x#XdUF<
zX@J&$i315*@^f<o4psMPGiXU~nHwPMKVF+*fZQUMIFN9vQD*~wP3t8NB&6C5TDCUt
zI?|GvcZ2b~Z@|zRlz@nq>2AM-MyB;HuB7BKi7RbQN|C`gN$uW>3{Jos&8O-jO2(fp
zV?E35)CgX=-ii!u5<HbSm0*etZ7sUB#7<Y+i$ZIl$j~O%vm6<lB17A+n6(n85=@by
zZD07WrQUYBOp(D2)hjZzC5jBn2->E>1WXkf+P2e^<W#~)o>tU0Rx5y03Hma3w=LEv
z6FXgPXX<_uMTWNDs})Wqm?A@)NVF0pnv@6jZYygQCw98p4p6<sPFI^)&m~yT)9CNG
zHnE;du%4w$a9W#K&!t2IwoR<(Qevm8O|0iqVyCN3tmjf<r>jk@=Tc&)tL-`6QDUd7
zO|0jVx6`HHIdyH%57x7=IyVgKS$Ky8XB8RR#Ck5ldOn`qpiQjj60GM~kwG6(Q)JK-
z$EOms{;k=;!I~*DsBaxPuu2_4^QE+PaPHj{8Ft~uSFgyRmtpma41ed9d$C34mr_NB
zmU~8m5=Dj<+38xXB7?miyctfBLEnW=DKaFl(&`i$+*-7A5pt!h?_sLQAbl^hxm9+@
z?v42!ITy*1P7D2k#)k(Dzv7=UziWncE6JGOHO_ul;}Qltqq1A1BldRAypmOZsAQEN
zDp}=+N>=%yl2v}dgrUCU&Q4b)tNc*ODnC@R$`6&S@<Zi7TSm@KSLGlB&Q4e5U<1xh
zSLF}`&Q4e5Py^1MRAqqyXQ!*O(15ekRXNOnv(r^M+<>#wRXM_dv(r^M(txwmRXNIl
zv(r^sWWd?!svK=#-JsFzbgiVwpl@hkcDhhx5D0^Yl@%EpyIDE2^Su=rTt%~g_6b+f
z**}|Wz}e|SkwL|roh}p^1e~2N6d44Zoh}p^1e~2N6d44Zoh}p^1e~2N6d44Zoh}p^
z1e~2N6d43!`)8jr;Oumv$e<i&rwc^}ff+%=%8Cq)W~XZ<MFy3P4Z$5~6+>qT?jQqE
z(6AGqhpZw)<0CB7H)BPHCfVuwfQk(2+1cqrkwL)O=|Yh~z}e|qS&>0G&Q90LiVVte
zcDhhx5LnhEJ6$L;2sk@kC^85*J6$L;2sk@kC^85*J6$L;2)rINm?DGXrpTZV0E!I4
zrpO?SB7?9gG6?rpWN0)yT`MUvsJye&g(8E1v(tqlgMhQsg(8DMZP2iaB7;7y(nzpR
zYss#i?q^@e_TA6E5pQf+gAS$fnY)p1O}*kyo584r)6?P>Q-2*jnL4Up7w$<Zd$mlF
z!QG<aACM9EZbrCFkwN*rjBq823~J0NGN{N(iVR=h2m#dsV+QPhXAqr6iQJMKAQz;l
zFm9kU_I}R(_zpt1v>AHLe|G==xuAj2y^vDlJERGBFmN}*i0x@H=XQ4YgYQzB`5>Qa
z#Bpf=8)(8vJ1@3Qq`vZt4;*zVy?>MVXfsST+BpgzZJGt!kIwCgFen)F0A<pADv_Pj
z-dxY+ZtB{c)C65}SzTUeH}xhggM;m+PJ^82Ht*t<LHYriz#zI6xP@w@$94>8p;C0C
zwRWR71Fut(ZnUmWkMV8b3WB@Q1|weQ4$K8}2=1mD)0^sMz=zXsI%ug&xSQG`xv4Gf
zrtlG-+|Jmn+QhiN)h1r!j>BNRFKfqW2jPCQ5mUf?42^je57w^bRlK`7@ijHNAUY^D
zx*+f_YzmnZ@6+gl-as}M37bNO2L3&4il&rJA*<mDn?muFO(Bpv#@2o)$Ti1o3ZaBe
zA&v6*W7L$gDWr9tuqhN@J)6Rt6YtaLf+nn!Z{bTc;vHklC_%!eFgps>uIu?h=*^~h
zFQW_gP-CMD?wR(<rf7`W6fZN1HDFWpGP)oVG&Q=QGwP|)g)IPUV01xa^F|l8p^`Vc
zFdx*H(FN7}@J1KZO6*7GEWVmvN&j8ViHl94S?I$twhp0tqYGwc+RTZIO(EosE~tBN
zbm2DkHQwlg^1RUn*<JKT7nJ9XE_id|VpCko>UDY(DVw4-VN)p2=}m}D;mwJsY>L)i
zY>L)|O>qGuTT`P88FS)dQ^>k@EJPBU;y>J+xY!g!dHuY1Z0SU#_7()Zy#+l5Z*Re#
zGw-r)7zdkNy?5+4)kwmo5b*XEgjQ>BK}M?W%accWLiQG9B|NpaV4vDP>@BEZU-lL>
z=DzGL+{sWrh`j}GPF!q?jp*ImTTp)=wY>$k8QWWUU*^PRZ{ZkCV#1~n@b(tY1jY6i
z6t%gJ*%Vs;F?Qau^{S@cu~T#6vbV4eIZi?Mmr13py#>9;iM<7HP8@p+-kdo07EXo|
zOYJS_c301)@aDu}Q=CB^Z*SpzkhixWwE0J9PF!pXeJ{<Nc<J5DiI+3x#LF3T;xP-u
zSR1iL0cWEDHbrVq{6B(Cp-n={rVvQk6ap!mLLg;R2&8NZfs{=lkg_QRQZ|J^%BB!V
z*%SgPn?fLEQwXGN3W3C&IBW`;2!A(w3#mEreAb*eY>L#Jc>e!$dkd*KaqKO4bK<Zm
z&V=)@#`YFcbK=-rP{q{VLTXMNHie7}r1lmBQhN*DoH+It1m3T`g)6ADdV34%=l|B;
z!Ur}dj=cqMP8>ExnGethv$v3%6UW|yS~1%P|3T)&#ecYsaoNwq${dRCYQQS-2O>kQ
zi04rJjI`lbZN$c-C8uxv>ui<T-@>8TjJ<CcCJtI+Qwv>e&s$A!mfODjX4PoxP^%bO
zIE+Rx!XT^ZxgAH`qP&5XYsou_4f_d%VEDI5jE*U)i@(qXOPDSmqKlDqQ86nD=Tq=2
z+Tn{^U>)5GT1psY-PKxmPk<j&nsr)dot6f%3nz@$=*Kw231f`CvHcilIAM%4oWQ3t
z-ude%u#oKh4I~B=^ot4EM1B}tf1WmB^&f*=evnJ&#(ahE3Ze^&LGaZE`izeetfbLa
z)QQ|gv8}oZ@v;4;(q?!s_45<k_8?vi_vKoe%jGCSSr-yN%QXr=r8?6Z&a|X2axL|6
zxtL((T;ZA@F(T|8ZAWs=d20E`jmHs>74j;N5Wk;L4QhYFzhd|#*V+fU#9AV?j}ot0
zO3lK=0V-MZoZ_2VJl5_Duc4Fhv;B}h2DN1#WN$sca5^ImPioNc!fA@1?C$g*s&-n#
zOr^h}`01uloDakP8fjE$vVY-TtblxDp^d6__fakiU&wKg8g|~n3vk!|LT<oFK+y1C
z$I`|NxlW-lXpF)Yxf+SSnvMv<*K#d~D|+z3LHPHa^UBry&PEh`Jy%d$wJK>!XipGn
z(W7{WnIPW!M}`r;nd_&F)&~Xhc>`@_KyG9)2gQ;;^W2ilc=G+Q-!Zb-s*J5!bfXCU
z_Eu7-l5Rvp{(M5aitfT<VUxrsGB>(d>G&U#?i`W}ZYOly33!#rlLAWtH+JTNa|r!a
ze!w3{8Su0&FLN3AHkWmW!4f14tUx1A8%{OCz<z+iU9=-G9PsV#TyO+o-~_-mBQRY`
z7&sH~B9T7}d>pVdbGbcX;HLnKiJT*_E8un_*AfOC02p)>mz@~V<p0Oso50yom3jYl
z`_{d;Zr9y%Z}sgx>2x|PA&?Lt><I)2kc0qX4<=w(WrqMF2qHVk5K#s-D#*UdCIgC?
z!4XkVP!vH?Q5FGZL>2|v-tX@@Ro&GMI?RmkJMaJhrazx^`~04>pE^}_>UW;=oGjHi
z5wP~ej5h|?eHP#xJZIs&p3j2LCf?^2@AH655wB9bs{!}nxkuo3Kr|`i<#FBr3OEMO
z!2&-7+>7T{fnNaDnT%-^T=#Q;Wq9_$c|F?ceGLWOtAgGHtU~-5#S8da`5B&{TD;>y
z4->E3rxQ;Cbe+Rb_r?6YPJ|bf;&Q<5Q#jZF*L^eK8ax*Zd=t>emftR1_xAxi;n@!7
z^*jc8os734<L+MqK85%U#d`tpT|ED4@tUAMo{2XoUbhk<eo65r0cOC5PQ`Vv4>%Cd
z-U3?!?!t46z>a`7@w_Oo1hDVg8E<!7_rZW`@LY=XdP4@8j-BW(;dv6#6N=LTXqlGr
z-U0Ls0AwU*mIl*gz&3<zj_cMU>zQ~?6xa&zYdnt#ECNhlhiicA-UqM(&;A030G`G3
zguwBDwbzBM#d*DFfL5z6=i=EP(Z0BD9Ta{Zo=*x~0eB40qXM@8Uc~czfqMY?>12cJ
zdH~S<7(d&A=HR-Y0i1{D9Gv})p3H+I^OvmMrCIGY7{kr^mu&m?L>R+O`Il_Jd5`9N
ziN9p0DMsJnM0q1S>OrFPEho-jWB<{-iQdeHdRX)=U)RgLm2K5*wr@GwZEs~O=0Duz
zb>}yE)A><%dn?;z{-cQVcAWMo;=CQF-OtOs6N~pdO#ZS(KmK?x^IhMnGgkLd|A5*w
z&G#*I>C$}%fj3q|zyDf2nKpLe{a2(xUMZ81Od4#J2Aiiq-_oVjB~Igw)sS@+*d|?p
z7<glKPq_*#^=%U5Dv$uHKmx1+39t$zz$y>}SAiIKV|8!20+y#+m;fsv0aic)tbhbq
z0Woj|#K0T-`d|ysO1Cfu-dNpBBssy$eAdtD5_seK4&y3b=~wN79LCkX(r?H=R%6{&
z_U3eNB)}@00IO^Qtg;EP%ErJ|HU{3<S5&}Xb%}3@3wSpTeBPLYA;mOUpi7*jxh<V$
zUOMEaRERe=ue-yVe#c<b4c-$&%_4L=dFR^f=;Igjz8pR~TKzpQn9U<*UABC$nH~NA
zcXqUwMp2iW9VOQst7tr)nky7wv!k!`nEn#3d7MNxJGzJa<}0{%9(p~wP=o2Z^_ZdH
zI+XfV#!rj)67P@9=v-^(=7=66?8mrH9i7oX6SHi%&Pjl$@q8WErTE?3BkA5vKl}01
zb2vXsHpqCJ;(9b~nZXifgzGsI(3q9+el756z(+R9cpKq*wD<V3jWgcoa6Q_p`#7GT
z3fuw6Y?ATb5RjJN9Kc4no*w|tz_S9^{Wzfa8GbsL*Un{r((?k~MS`AD+`j<EZOS4#
z&g;$bB$`LO8x^k=urcBda6RpSC3yA_7yz7v=R|?&fR%XuNnmrpO?a*l*a7ego)-o7
z0Q7H$2j}(v4z!Gdnmz^n0k8n^4hnt)Z~&g=0(l-bpTKj9fX+R*7|&+}`T)1!xmI9p
zz#s8EBd{@G#^#)Wg!6h2AiEPNXmb_x5x^dZ7vXwN09=6Qe2X`aR3f4eP`m|zYY|_j
zcsg18H+X)jc%u&j&3w=cSl;!{P~5{1WVgt8?<%<WW1!V!a|aKco|6Dm2%3QF5p}u{
z&pcf3X8_L;txeHB2RIq&@rrg8;AT8m3ET$oW@o&Y1y%!=0(QsQfl`;_xk%vWgmlcw
zc&)e|?IK=*=P;bt`x<Bxb^VwM`YYgi#Mdfbf#>DDc<vF10MFz3oxoVYJ9ys0bx#9y
zZ^BQ{JboHmX1r0jo?QV`@JzsYqh){g?jN{L`MgRx9>Mkm%~S9gZ7#m>hhES@YkCd>
zEJeJJg1o*nxeD{BV9$AYjzxAfuICcKIe5;(bzceSxs{(UfmSK_TY#_OxkcbXz~gux
z5qKPsN1eI_r@yhoW@Az^>mQnp^$*R)`s3M{VvI}8#>S;)W8+e@v2m%{*tpbeY+PzK
zHtz7D+1R+lhh}5rQnRsfsoB`Lq1o8D)NE{AYBn~Y8+3enHa2e9Y-~WoeSCU0Ha<NY
z8=szyjZe?U#@p*Zo^y>)&&DVqH5(hy^>P)6Ct$7u$!u&uH@2%lJb!W(NI-fv<|>ec
zSOpT0o{hN*#39~*Zd6x5Jb!WpBp^K-a|I+JRzL#MvoTjd9O4b=4tFh#Ct$9H$!u&u
zw>YBIY;3}~)NE{AYBn~Y+s{=to<F(DCLlc<bCpd(tg;D6&&FJ3;}CB^x7PUdY;1gb
zHa0#z8ylaVjg3#w#>S^-W8>4avGK!ZV*|R+UDK1<*aQdPGaFmZ3&i(UT%y_7KhK5l
zh_-fImG_Vr+{wN91{=-)p1G#1CMqrc<ptctY?P6CrmWbUmT}Exh+<Ps+2s-qSghQq
z@Mn(7%prKm!(On2|Cv=GW##!^IjSM~R2~ZhxIDMoQN5BJ09uAC^ipFbYgx_HD056}
zuqA?v3HdZG*Z}Z#Ja-680X&K4F<ep6TNfhfnaj%@*SZ&AH#|Gz_{*K3dL5EcX|L1z
z<^0dA`XXT=^*Y4rm07GB9bz>)iDbv&tVT-Ea;a)`sH@Qpgj|EO8vPj0g955icI%Ay
zCZMS3R--MDY>2ZOos4G%PBq$%i;>ycYIG_EoM1KDr^WTu&UMxFUZUQPQ@wWXkz~v^
z%#m=V!}mWBGq>dfk?jZGOR}T)haugyRq?(6{v6Kg{~5CP&Q|@G6|F~aCFCZY)&EgE
zKNe8^|BB~TTv5@j{%dW^MlPJye?L6SaQx*KsQw#T{WYFWMV48m3z(-zH?;bnMAYMO
zs{e*o|C>P9;9UJTviko9{4>d{{u^8U$IqiwoYlWW^*>VepXchoDIv3PR{#C*ED=!s
z{|V1|xT2z4{l5mf5oh&(3C{~S{>rCmMD%1tlV&Q1ui*LG(<V?^zCUlLo__hOhg+oS
z>gL*h2V+rfbSQbvsyfE}p0^p(H{UzqbA$KUN!z&l>`sRArQEJ>qlgFZYoum;s7_1`
z$NSX8rnYRKY3@SaIbFZRdYaqY7Jo6tM%3~PiEs+8uopk?dbuO`7Z^#oX;bpz`CJ+f
z)g6x?>t;J<pT!d%CgJWCrSbc~#|ZD?a8&Y3`=4;6m)+ChFyn{UPau3RhcmRVd?c+3
zvhxci`mb`pp*#x~wq8hX)rr%Ixg@s=zgJsMwwZAm1tiVSteTOBhh<odt4n^&c1$R6
zqZk(BdL%h;e#YAbSASTk$7e;wdW|_tQ3jllRpMyQQpUFPcQ4F%4=vz6pR;uTM0VvO
zI3!%#AC<v`>_()yV5f|C2(InEA=%+OGgxqqEtU5~m-m*++xauQWV}BS9&M?-o$Oj<
z=iu62RX!6f@5>fLVBy-{7?Pc}8}mY3w6pS_WO-k?I}=zOGRknWQF~;(?>HG{IN4A4
z!bBgg?J+tTnd-mIK5%qPko|H<cKTA-Ia~xMHQ9Q9mwhwdPPpciHEw$zAMLADrKxt&
zy=EV~E^Zl=t{qF4A=Me$9p6*d)3Q(gn2F&Jo&Un0;(x^XpL+!VMapkl_SGM;y<|@(
z*Y&xGLO+7*Je^3C?MXEyvUl<{tN+LLqfI!k^9f><h@q!>I>v>BUSKh1{@mrES5`X4
zm4seyG47{Y%HzxtF}_adofhNl$6X%RjEM0Np+8WJuIFfWI`?Oh{#GGg)2n;lwmEv_
z0oU4Dw6<fZ^FOB^`Kj}tB>77WczWbQ`B%Fh8QD9VewYtZT<3*9bG6d9PrB?`%lW9o
zd7Vd+jas&BM2rQ5?qD$%#VtE+M2!6iU1l-*9(8$KF(StCgs!j{^B;5dxNk&^3kf~f
zVl0niJU1f7YC`X^7=3hvu5>FMm2S)9gg#<1yf}}kBVrWy=UI;Px^AYU+um`VsbMq~
zX^%n}!31^Z369jK>)2D^GX!0L>wb(J+pl*4dLp#nqCD2IyR7}^DgW9oj_#oLt%m&F
z+5+6L;kk|tPp|uXBPBh<!oALb+d}P?bu-sqm-JpLv|4rUE>X&`L?g23T|^drWYPXn
zSH)-XYvz=;gX!rz+V}dtF!%!b=C<wyvIn=tH3Vvv<R9<?@n@26%fbv?4FBB*XnUKS
z4^G}DS}RQ6CX&DBZSo4jf85)ISL5K@<cs8-yiKmf@730#!n{oskn}}nRU19x-X@Yi
z!-e=M&b>_}Ir#v-ym9aQHc{gC12bL@#~a4pDw2H$e7cj_TSc;&2QfBrQT$fvK^7dG
z@t&0|eyd3K60!$z$y-HfpF1Su{RD^1-Y$}z_z~_`95Q>mNVeqAjJF#uir+5E?;GHY
zB#YlJl09@7PeNQHe!D2`9}cGs95Q>mNVe*TjCU#ynY~>kyY5Ktaa<I?U6kJqM=>|U
zMe*B3veCz|m;Y$e+S^54nLQR#1!>#a4c_OxN1E~5MT5X=dmZVcNTVZlou+10*oGuo
z3+J`nPbfAy;xub#U79D6w(1dWY1Xzh=Mn#tmZlcL+i+7wqvw(1w5+Q2Jwm>Pi*iG<
z+6tz0xabcm*~Qxmypd#A49UI>{-k8*4aq)y9P387XwxCt=Et+@hKuS$vTuN|#kDP>
zQtRufXdm^iu$d=7yx=1Hws*42!RJV3-;_>v$Vb_nfs5=*-^o^kZ<oxzFrBRP#Eci>
zBKy#Eva`S+!|{Y+dg^4)f*-|kNvPGYRV(}SbfJfSjM8wCeStbz`J{~Z7s>2H)X8=~
znRg2=vhPtRyBd6%WcFD)Eqf4G_zCdClG)d(lWqEO%#Gn9`$%=Nd%!nKX5Xq#w%`;7
z0?uoDiJHDmP2H2yl{WfRs9l`b7PRpo9efnK(CrA>)<Ul#?M5R)mlLwYLRS;|ke<$|
zD{}=Qm*CP@<{j|AOP0Da7knb)orX(anWw=&mn?N<Ha?B-Rb2YY{0RJAT>8pP{3JsK
z=e0liYcH5f@13lHoVq$U5PAtNeRVEA9m^QF^wpVlCd?@=eRVzxK3=la)%g<me92N*
zr~51(g}C(9IT*ZDveebN9efRrDJOmSg~9ij>;LfVjF-iE9erG#^mW@B=~fEy+TZ$(
z7jS!e50khvezWR+^}2rh9?7dCC2h0F_?-eBw5#qo_qJa`#(Utp&LE(<P`CR!_JC+^
znDXzR^8a=li=$$je;x97EhmHFbvkaOq<dJn*M20;(cAuNBDxl@V~?MYQ=ya8;;y?!
zX3_P)dn8)-AC_^~A4f_?6x`GCgtL9ujOPgUoE$kv(A3`d?&2dWCUZVZFO1oe`ab18
zzF(U@NaiG_v`2hh&L?tCsyBc4>vCHnh>R%g!Vh1U2k|eN4@jQO2R@5Go|C-iBU4HJ
zzM+py!>Nx<!>Nx<!+-N5^Bi(ZrUmXJ^CXRcaha(EB+bvPx{w~SX~8HZ$S=Og-}NHj
zW(D0Q*zF>J_lx{wQebJ5PfR6EJ~8FLh|9eamwaMMb|d(DT=I!20|@tmS4$R81|<6#
z_@}sJGGKYflK}buK-deo<P%e};2au{OFl7`&m`~!$>K?XWLtnY!RhmFQm7^@1?_`t
zF5-4tpD6D0Z>{)4?*ybf3`*mV!Va-a?Wd~`*Unl$bR6*>$tOliI)|kgIXo{Xy6?^W
z(%|s?c04>!Wq7_sMJKQK|IYCI)6notnx9#92|e^*9G*&=3{Ux2aKVq!Fo+ot$<76z
zjZ22-myvxL{6)#);VIee;9GIY@U*<+;VJ)53HvTC8J?0&J(o8=E*YN6XAXD^$>QND
z*>2#)xaQ#S%<SBL2}5ul0y}Kx7!S<$)kwD<l*R+Ib9YJ71GDqsk&><_N!j+s(BM6S
z0uNS2!tDkJ^yT2s;dnv~|I%{9^xiKI4%6`@(o^)vr`<69mzn?X4AWk9n0tyQ&HslE
z)91MYzr&@6={w-JaOq*%IFBg{E<H>qfhXYp)-c_UuuX93VR|X}OStqf{Tlc-$x_4g
z`{4U=!-i>qL6Y|l({+*l*M{jLQl^LLQxy11RU|b`+s<d(3+_F`ba9}k>7vU9hw1m@
zVY=)YFF2p6)Z7girvH6L`Tu)_Kxum$v-&no`XaMxGrDVt5ZIR<U4R=R1bRQkiU2No
z_pe9lL3&w<e@5VUa0wwG*}@Al-dr3qBLpN{4ZaGO5CU_NUHMNadEyd6K(bRW<TDJH
zj9#TZaV2y#4w(@Gl0650!pV#fkZjqf(T%_*gn;tvxG3ZOS+aN(OZGalU*Qr$KxuFK
z3|b$!gb<Ld^|L6KI++myk`*sTu@ZSg2q?dokllw%2m#6Jmp};oGx-e?0=FUgDz5DW
z#`m2(oQD$vk0DJH0xIkoqW=QtwOvZ+dkKM;kfsR%rJ43QzPWIG9b!`GQAT`onXde_
z><)ys^&#97VRV8Ms;);6{V-hgnIYMk;L{{)8<JfGzCyC;L$Ysz@4~gsCgc9pH?=bU
zB>}%sg7}+Sve&^cNfv)oOSZ-5c_iVIuQth+gZGmx_0{%K@bQwRzS=GTpD$VJoBDF_
zWs;@7+U^A3f%DpyQPaCe)bt00JfIY*n*J92q-3d@z5#wsviR#?H68s0xGr2XRnumw
zhUuEEN4)8{bj`L0Z-evNE}>>0(l_~Ed9QNCl=~rs9HbPfntcL%vSg{6T?M{EvQ*8!
z0lrJJRLvd+{}A`LYWO?Co>H1r-xXHD`r*8`hpFM~BWl<~NEa?$!|C94BumwB9(b-~
zsTv*vJ^=SY`tE$<ovrk#n%xAx4##NkK&3|m`(VABUEe)S$b(9;U}(U;4E}eeXrD!j
zbnMw*WQ7Qqj=d*%7aY+KB6@Qdm$@E;?H4Nj8&04*@2AB3k<y<uBzpt=nq-#`$$G!U
z;s!2SIV9TwyqRQoI+?EgSHV}~`0JSUg8RaLofalv*oyNa;lEd$PN}<f#Z-bqyw0AH
zlD0c}UQ8e?O&s`NCN-|}MxrOgftr&L2j-871M|nkfeJ~81Nl48A6Z`Kmqtpuht<&Q
znEQLztcQr0Zq@`UG@y!g{$^wrov*w{lB4ut8F#jil#D32=l*Bi;=<n}4tmup<M!cP
z-AeUKUm2WN+{}>D^!E=m;m{(QX`BB;<`wC+h5u_;s(-E9$*oi;%^$f^eGXS|BiztR
z_4KcRaPK>n7`amYPnVM%mrQ^a{_>S@_PAsMtaYk~u7YUBB@<xDp12xD6_-pQEbn;g
zVE$`SNxX)<Q!CYPB6|^+On{ZoCD$>Xz$Fu4$*#QtQXH3FslN0^CeOI^N_FWbcxorJ
zse{VB?Pg|Ixb#Z(ez(Ep;?gVC{vD+K8u{7O;X-cZ3-06{hil%+Bj>#<)vqJHg$act
zFp`z(JG+LjR6qS9Yp(H1wf86d@k;fDf5acJRL>$#dZqe73cU)~If+PO_(rZ&-+dPf
z!#LKmiBTfP$d&3J5&DqDnE9H^W8_NpvxGivF=kOM<#FbSb?7$<eZyj0`l`!g<Vtnz
z>lv?t^SUN=^L$IKrB6gUP9a`%cIWVw>XZIJ%j1>mJ=7!dO7&{V<CW^4$RDp%kL;aK
zlI>2oPVW_0tC1_!k9>nS0?zBaoov*yWtw-SYWEzW&svN_<CcwFseYT#H!a46aqo;=
zsjlD6f;rCXd@ioX$d&4~2_0`SyttH+E7eC3dYHvH`z6<wkt@|_6MCA(I6p3B<Vy9O
zgx;YTU9Z#8>6PkVAbmg~UUL$oa^y<&R^R01hx;E{sh-b}*T^2ZQhgK^Is*3rR;oWk
z7JX##cUP*9;Rf}+ORgAvfjk$#K=$CaSWN0)?ePB&f6}=FFOYs?p_ArkRvknS>07iv
zI*0B^vC#daO^{}x2ORtASm^OtC3Rn*gMJ>n&hNfB$7e;<p2-D09p}C{o$QO?&*9wb
zVuH)dUKh^aX0Hk7{}%DSfos~5^90M&eOWsH?+JTedGY9;Xe@L4Y@SDDigsUnQyjb8
zek9UygVLDV>ktdwG!k!W%r0;H9?6~~C7r`kjHK;G6W#Y3R}BukIdr||EjKXiPNkp!
zFn?&+nbPXKOnD>ZvDRvQ(r7l(v)hxP+_wD0D<Mv+b%#vzFv;Fm=}v<idv9JrQCJo^
zjep6qh~&w#$XD^Fmqk2ozC>F>Nz=<BhEvNThEvNThKDVSOdz*J_wI6XOO{3M!0**I
z)PQt^UeYm{RSo)119DtL3E}~nOkdPTgG`8GCN#7B-aROwF%FXHi)3BMI&jJKr3=}5
z;I$=-X=cd|1~0|w^*=FOMrL<_uERCYX4L$acDNTkTATR2j#niaPy^P=TCF<&z_p!C
zP+LkWyT%QiuF^0SnkOmK_db2~;0QS?9wAfz>;?A|e}{!@Mu=B?SRFi&(MU)-CbLRb
z;zk{eylpD-t?1qjarIdJQlSYiCjaLNyBL@7Vv_w3d@nBH#hySmdo>DfxP%vz>;mwq
zxCY~KVykNLI_S^1wo4fm_YkFdxvDrh+rAn>bh87?h}rS4Ob~Ewj}gFTFfUr|0ySC|
z6EGj=b#$8Y*kl_+UFQ(3)0D<0XI0NmQyPo?rZg7&O=)a$R(0$&r7`F4(j&QUGaV=J
zx=tJ^=@=I7b!lchOw@JbNXdvKyq#AuN_%KW=SR1u_3=G1a*RJhKEBs;?cf-Hf)3DA
z@KsW4Vf6JKhsOB(D;UowR(c88j5D<G;9Ew(`#<>fm^=elP!t|~EBKc@_#{srd|$zz
ze(=2lP9A*A@TVVqhEoqd!>I?K;b9NHPOfe8;JcXIk_R81!Go_xyBO9ANctkP>VCS*
zhINOQmsc@5&c`LgTA|6XmcMu}><}&)){?Cco{UR|^+U+627ghq_+cm6E8ySZ+^|+H
z7JM6{0Jyf77_9oL864I%E^{)hRj*TswL&o`5%4ChOop}Y#Rm!aH{8&$mbB|6GE9cG
z>X{5{^T)&5{PD0>9g|@#f7jmpBx6(puj{aplEE=*;a=ATBO`QOI#Mzs3B!8+U);1b
z8P*yT?|F2upnbk~)pdizIx(qo;Z6+ac-zVQ9k}PqhDv5ibAUX}hDv6gww>_j{N4G@
z>$z|MuAm=;hw|%esAM*%e$+(bCi1=fT!gcDF0$EB$$X>E&FE~XWbUcyWt??K$h7K(
z@=Y8zRBq*8&i@I&rF;3wx|4QGKfrG`R9e>QQcSa<(z2cTi6doHv!RmxSo3<NeO+nY
z$uwD~n3+wC$e3xAtTT<0b!$FZXBwr|r|Y)ImDL5<F4-7=MYc<_*e+2(<wpY8E)l3M
z;m5zVrJBnQ9Onn#vx442%8yk_20Nb1ruoh$JAZ%+fDs!F%EXAxp7?YAQhxJu_&FR`
z&=106`5iQ3^9d83#jl+&^aVT?&qYp**epPt7_rfVC%FI*<Npqh3-ERR<@_i3Eq$M#
z<O2K@e`3T&F%u&;@~1BVMr>|FRPyMI;TIq=Vl$rL#E6Yr`av#CiQEpsm6d=Cvlo85
zFfuBm0J|_UDkD%GJ)ePmZ%al+T^M(MW>t;tZTGg+*CIyk-*_70MjgFBn^69(r8ov*
zeKwDbhHXT=uO+K!M-b)1ie?)UV<CCo-=-_Q^$ohx6Dg~7GCyp6^`54%yZOKVE`R?@
z$2}Hz|L}f7+vtsuZgEE_#l7R}2&FY=Tk3+YIomRm+b6i2x5b*XEqPSE*86HMF-x3#
zy{zMFoLS=B8$}VU&Ma~6tx=EDW9!y*dQ$G~dM1mF9>CFFE<QaeT7Y$fTqZMW7Kxl$
z;vA<Z>6mqAmN>`hNy=kxq|=jf$>~XvPEX1eGp+pd7DYNeDaYwaI+<s2q|=jfwM;3;
z!(@+0rzhp=naUf)ToTRZj?N99p48OPw&Q&4XA}wA8~TwP8?z^oUqwM3?)0P_W{JN;
z!_6#lE;&6Z(&<T@W*J^VwVhdFooy);m|0@bXd!2oIG3EB6zTM&-0xa~D_GrdW{Gnz
zxYLZBS>hb0C*4JuGfSLHPEU$-dQy(llXMjLrjbrh%3+omy^Po_aV|MM$;=YxI6X;W
z&Ma{bv&0XRZhmw)vRra{l9?sWae9)Pzu3$Y=Quq{2bVju#5qn+((s>`>D1{-IZjXd
zC~$tJQ^t{V<FlpT5ci3ePMw~V!z{7Ru}__C`68h#o0t6$dbXvV!dLbmpu3yray2x@
z+J`QaM9F0mVQ809LvJV!g^flK%p<BsRB<Yv7KispFqOTY9aZl=;8ON7%q($^(~|_8
zS>jxBdQzm*lX9G%WY?Lp)ZntOjGbBH+{ZG(Q_4ivAab0ZB;ZAwism>yNywQc&T)Fu
zZUmLQK>u_cd|cJ;2XmMumVUCCCC<IuV#hpqW|lbTW$U_HezaIulGBqE(U~RAaeC5a
zNCzUFo|H>YPl|MUQjXJ;K0-P3Bb}a<<Mbq1194`F|8oai$_Up<(UZERFiSiM<jfN1
zlGBqSot~8A^d#MUmqt20DaYwaLf1q(Jt@cONkTVAIz1`J=}AI&MlYyEoSr1KI@0M$
zxuMgO^ckh1t&=!CNmzv&=JX`tSqX0Ux?jp+mUt-wGfSM~^dtdimN>`hNk@P%ORT4p
zyp~OTz@^52jNJj3x>e0Aaju>Xb)|ZLsj6a@SS7l$Z%-0+c%!dCSoS3uqr24xCxUO`
zFZ;SH$LO|62J-Jr{3ySH#?jk&tn?Po&MwMf6j*nFon4f}DDd%s;E#;{e(u4sUPUIr
z`g<Y<*60C=`n5kY?~DTb-$7xZFu7wMHS(8?!#}lcANkc8g|*w4;~%#>iTp3Jg)P{;
z=UDvJ2KRap%nnuo!V9=Y!JLZxUbrixI@r<x`)Ykz<EVa@C52jXR_$rUzJX_RapU56
zB4Z1dg|Xr$2K;ad(TbZI2*OVaY-XUu1YBtImamY3e>G`ZHyr(za+d$j)}4dZ47Ttx
zD%iTXS4Dc^zwQm#wO6OC1>wsd1MJrOAhAl}ai;-x?|mIm3ujQ9);)SVX-^cce==at
z-sb=v;dTnyt9KEgCtRYCy?gHk^o1v$1X$AhDZoHDc`v{|y?RGX3X3RTwtlErZJQc?
zqZ6>yz`Ehq0?T?g=eC;}p13n$-(H<Ef4k>jK-*epwZEjcEs%ds*JISJ?Ei}2=F9xZ
zwcC%HLx{!QhR^TTt*SoNDEqDa+OtkAvACW;Q<-gD9d8lVN+N8RM6l7-ZqP0UXI~OD
z;AfR=UUi8j+b>D>vB6~KI}1p$pRh=}u4P}D_=hR+_SMgs{LB1WrPOb(0g5!TVE+~+
zT2TF=CHhH{NS9$Kk>|Imy$h={G+Ormn#58k4#jG>ceORg-%#-vRR@Sr_NVY`RnZl2
z@inNuKy_b;EPhJ(FV1K1Y}~aMqH4$|+N5wn@JoP=u5e*(Xmo`;)`mt`xTv_0$B`Rd
z;ZDU518O#)!kvq!0U{e};V#9?03G2vv&nLCaW$YPd}njOuEl2nec}EW0Cp?-+*AWz
z^|Mrm^Ga)V!fMO+Kh6v1mgHxEtD;+%Iskt7n!q+CH9VlTYEaqVLL=%pg>0Ku6RiF7
zh~I8Ms=T`t)?d6838JU?wU}yx#YDI`5vnOJd3r*0a1yM>jmVwUGLdOns<|#$MJA88
ztCQfL4+hIe!YBDRdV@vs-j_sD$E5Pm1t<9T1pALL;VLb3kFtpjkkXFkuQW;GH)(EZ
zrw+YJ{R%x(+NHyuZ8~`=>uj{f41|9Md6ss!cWVD98f3pqO@pOh8~Dn5cgiM8|E=;b
zt!p@RJ;O6^-O3r6+B4)8ZNr1Ja%RR#^`gV5Q{}8oMfLQfh~LWDnaV^W2GN;3dMoF;
zn61&HEOJ)P%T$y}81<5I<<ptUYoLl3s0s4M&wax=iZwjO%iX1nKa<IxMx5MU)VXqH
zrlC^0ZlxopR&LDH4j_8e$J@1XQ>LN((EU=xuVxyqaz7HfIn$`?5gy5CY30^TL#4KQ
zxnl%x&t%6C*tHh9M3p-;wMUibR=mF}cez}==r79U>q(v~=%&gy915bUV&3ggDf)M=
zS>>Cqyjm3TD6ib(YF20dOSLQC&SZ~Kc`uRY%*t;vwQcC5XaTRc%5O7eyY$h$>h7l;
z@}n22ZRP1qSywfP9#EG)<4`F&NTomPP%S!Ir9YP`t9_A|lU>8g3z_UwD(}-2-cgBK
zYX7G4zQE(R($*3Qu(6T|m1axyeUKmBhp5u-P!Nf^sB}0~ifX#_oetHa!<0)`OQeeu
zMPs-hE8Pw?8Na)bTiI8Oa(k%DdRnp)b?KDdLo170YRB?&i+;d+yRvIbQvfYH_4FPs
zO?UOKQ`vjEupqis{jgU{Q~gkij#cCKZfUCQT2xg{mN-<8WE!rrw555X3W&ZXw9KK7
z=sK16;g;s9g!M$Syj3}{rFkZ(FB-4%KH^Frh}K0`IkKgBKL000KU3*Pw=^}9rbeNz
z><U-jwCGpr_v2cc8iDIZH)xn2@6hz<1fdfgni0LBo<7l`^&*e%sC>+!nbFBYCp)x$
zbdk`<9oiszTi4_ahc=9QG+NGaJuxdf-flUEHjOIkm-8H&9UY>W=er)98~s9e%BNh|
zylARou54*)w9My9>C}j_|4Yg(`??RyzWS)_>xRhns5%$5WEI@!!%tPd-O{Zq(I=zo
zmHS${6**A4@8Pj~coVPB9su8M>Ap*Wx?7)30vlf6x4@MLTDl)a*7q9~@L)@~#|S9<
zirTkKm+EIN-RjmpSvape9s|AlD!+)qCk38}!9BXiejNiD39UTY(yhl&-*#&Jvn}1N
z0>4s!J{Lz@piA^ZOZOIp1nPzJsl)iGM0q#k^=U&)<qs|0A4AypkjB{`Te`2ZT7Fs;
zpP=@?<V1Z{MgCI^rU|_4K%f*);jCvOukS$h{wpork01+_5qGQ$%z1rBDCMgy-Fis$
z+0)?7mhLV+o_#$o0{yI;#HX8&Pz&B_>Fz_;cf0E7WxKbx_zx?-ewHQi>G_k?^O<b7
zc1rjCO3#p7)-}JM=AWCye3!AR7(41hv}d~&&^oC)zW8%Iq0URGPAJRog-`NRomkf0
zI6C|(cU*OnfxhrdlvSN<Pp<*@)$jr-tQ&eg|7jiu)hXFkhyuy;wA{jqUjNz3b4J&n
z6{Z(?FJWV`)H<I#enqto>VHT6^X!$?|26qnI{%~v_%F$5O!j|C^2@3_&_@&6kZ0D(
z=oOdC-v50+nD{uMna%R^Uw0fj`x41_(gB#c+ia4&Eh~?u*EJcRe4nCDuSzN+_8_X4
zSv5to^33#UntHUXJaR2fXfo^7HMLbzZ&zab-sLy(>$u!)sRCW%T}p|6;Qt}J{<pbY
zfATuK@OSJylI%wCx@-3$x_|U~gc!%`uV2<Y#sAqX-PDzR<iAn=KIeZx{;AHtkNg`{
zcT}9a<lop$H7=2VGv~iUT-A2YA4$GPq$!C1efgKyXtw7bAV*uCxj!@5^807nrxK9&
zb5~_I<C$AHodK4+rc{ytS9DJ9+J@wgz*vCKhD6qD4RV(kj{=9frE^yn)D|zilb_sm
zxo!e{&;JfZ<gU*unSZAIU+q4Z2qoXYL6v>fRrXt4mqOFJtUN~V#=<(m+sgS<<Xo8E
zke`>xN4$bNq0t>`SC|p1NO!1RVMZjtT$bTfn9(gzt6=4>uwIyDTt{Bjznp9Wwq$tH
z#;{g!6F&nUC~O#9jLZ(TD{K^hJU+v-yx_hh{qPK)SOxbb8H7_+E%zl^3iUNya9@(O
za2oeVVROqM3cKmO!WITP!b1dR8|VqISJrb3^m#RRs9j<E;1{aH<qF%ORepD<U15Gv
z;M7sS;|Ww)*s2zInNd2_uCS9K9}`~eJM?}}G;7xwujUT5E9?_Y<9fP|{7_wfcc@)q
zsjVIPVL#91!oJ0sgan~#QrK^_`r>RlO!)<Kk;%mwSN-h)_3~_r4+<-SV?cJOUE#P<
z@_TluT_HKtuIkT2R$iN1@Sws|!FTiyTzaHec)D(pD@%{|3eVWk@heM@_X^LNKL~ZG
zUEy~{jrUS`D}$==oPkP3huRgMAGHHzxkK#=FIbw6aI!A_pIX%uJ>g6~sSB_4ZpY)V
zFPzTDcHy<&69Dc|yTa?`RRG5x7v3n!ZpPHg(iQu8g|{s0bpcfKZL8)i0QHR7<A&Jd
z0_^eKB%0mO!gB%k_(9NC(b7Z70`^$do7)h3Tu9jChS=i*?D0)BYEeV%F$TfvPthfd
z8)A<Ou*WBp+a3+E#|7A9-Cj!?v+2CTAbZ@Vp{+zs`%!C~8&bA?0ddj(ouGCF#q4nb
z_E_PKukhF|B<yiR>~R71Sa$RM#<zJXfg+)xv5Sg_Jr*i8{;DyZu*VIt#|7BqNpyD9
z*ouq`347c)VFM8C@n(e0Y^<+pC+u-U>~R71cp+h%HpCtmV2^cY&u$c{Z6RTg8+}R#
zd#tc|jmJtL*kc_iGQT1AxR9{N4IOG%fIU|87B_ULT><tui`22l1=wQ^`ItQ}z#eNz
z$Lw(d_E;=(%pMnDkDn)_m_06VsNGS7!X8(BDgVc-qwVrneGO#05{Cg(SHhsK5OL-b
z)Gk5Q-;v+87Amh%mx?Y?a^XI%I7+I)I24D}UqN7evc{O*hcTc0M1u8{<?&kJn7fbC
zV0X-2VQD7N?cK1)D15Sj*J!9m6F#{iKDhv&Y*(JL)CE;v89P3?0H1uIG7+C#fKL|i
z8sd`+@X12?#sPXd4(F3));_Lk_k#ua<nx)LG+x$~PWa@;2C6cAvaX-s5T9ItPgcaB
zF-0-qll80~XoycPBz$s1d~yLk`FLtFzac)k0G~XK5*Ig))q^9SZR*xp-Y95X7aTgY
zaj?<_4jtPVr6v@!wN;dNQsYUDI{4%pK&Lle(?dAnlN;ib3-HOx^U{X+<N|!M&@~P5
z$p!dip_?0Jl>nbCbZ0|+asfVBXm#UK-G4)Tvc{2$woZai7FOYg;gf~$PO$jo0(|mQ
z2pT%(t^l7b;580Z*T5&suswXT9;@<NHZh;9J0iwCFBRTw$?E1cKDhv&tSe=FasfVB
zCAzX_C5d7_x#~+YM)$7`PDaUA_^ZC|(=ob{l7X!AC#(Km{016FpTJ|K$9!@DK3UHv
z<C6>U$<G7)Uqhz_lj=MoJ^yhgEXAXui{<~S{KvI@MgBW^oEE=O*9U|DpyW5!|1AGf
z`ERN7O!540$p5waee!=^{=4cwmcJ?g59%+-f0Oe0u`N%H{T;1uy{4(j*VvzM)myK%
zd(a-4n=mG<=GYg1o{nj~p?xhxWl=`+!tP)O&$O^i#$j*k&uFC=E)*Eu`Yk|9I3O^l
z^-X{uP8H}23#1Ri%>~A`K1E1t*elTA`bR)1{H?$^%dHZ=d>de(^#MX^;noV7(fS2I
z6dozCUQxB~34MW?76N-Lu)c*%3jbAL0}GiNo-VMVh0F{uqYJ`W<=e<@R`^$ejY?Mo
zHVrROw2iH8v%NqiY)LcYZZJB(l%n%XDLTKjcDrW1{d*DL==}2LJ;&oO8=YUC9f+_s
zI=?)pBEO^a%Uc@o88aVIN>QYhjk|79N~1_C3j!_g8AV!ISW_fNz*lyx>GA3a_{yT<
zmBexsX=SJ4*8z?qt?XQU9N;L@$}Yv%0gfWAEH1WlS2~KcvTJcefTKt&yA^i>40vUu
zNGn^`4ki@_PLJ~{b4&6&inOwI=?H+MNGl0NTJ^7_l2u<lXB25=+pL;kL+i_Un)WmJ
zvPkZn6$DlNPb4wb1dECA`b4Ovxa8@#{^}%HjT@0WsehdWtGO;%Z<?gscaq@ggTeBV
za9hS})$avZ-PI?l<eGdCycyDQ`|?vYmVWHs3z(p8RXxTeOZW{$@9E&U0rp7nZ>&~}
zs-p)a8mrZ!YJ7y`<p?qhjc7KywU(k=YmRPhzl%6Vx7Jd0Yi*Yf8+(ru_&#)N&C#u6
zMYoRHrKS-&R&?vAy*m$(Uv%rJrF9K0N4M6YTlJc0h;FSzx2jaHA-c5=-KvKB4biQ2
z=+^HO7Bob+)}dP!v$Y|%r4HSyOu~lf);e_SB_QZlMUgjtEE>Kh!7<%hhi)B@%;?rS
zbgN2nbZZ^DwaDwZA-c5=-RdeQy0s47>MAF?wGQ3-HS!1=qFd|GttvI9TkFuR_W~W=
zT8D1^sPYuuT8D16YugarT8D0Rd5UhWL$?YA4biRaJu*~kh;FSzx2n8aLv(8$x>Yrc
z>DD@QYm*Wj-CBokeO~2>ZmmPNy7EM@)S+8lc`uSz9lBLlHE4)#twXm8l^UX3>(H%2
zwT9@{I&`br7t^hE=+-k;p3$v!=+*<tpdq@o4&5r?HAJ`8p<53F`3=1_>d>u1LBkZq
zpj(AX4biQ2=vJXxLv(8$x>Xk?YKU&FL$?YwxeIj2eN|S89Nk)nZk5Q<t##<ucF2&1
z=+-)PtAN)K-CBokbuAa&T8C~`SkMsNT8D0REf?Kdhi+AAwT9@{I&`a0y&<}_4&B;I
zx~L(#wGQ1X)X@;#T8C~O2kL2vZmmPNP6qWgM7P$VTUGi%Lv(8$x^*4?Pily6twXo!
z%1&*FZmmPNs=R3p(XDmpR$b?H8=_n5(5*t#8=_n5(5*r<8lqe4(5*u2HAJ`8p<9J!
zHbl49p<9L4Z-{QKL$?ZT(0E(d1iDpd!-nYAI&`agVpc<RYyDh@Hf@M*twXmeY<5F*
zYaO~(Jvg@^y0s47s<3&Dsfr2Rs?jo^EA<-Es(&iwR(;)vRbPEn^>srS-CBokRj|>m
zb?8>*V{~gBx>b<_r8^Xl-P1AMT8D03qCnlP=OlqK-CBok{U|b{TkFuRmjkN4q8i;=
zhi+A)jc%<&w;B-LT8C~mAiA{<-D*H|YaP1PfaumbbgLdeMz_|XTW?funmyH_TP>RC
z);e_SZwU$13+pfnhtaKd=+@B)jc%<&w{8ch`s=IWqFd|Gtr8jCT8C~mAiA{<-6|01
z=S-aSOiZ`dp<9nrpfb8V35@C1I&|wr$c%2SL$`htz^4g46X-`gZPLx6TkFuR-&TCl
zt##<u7cKrVT(CetSsq&!Kc-tz3G04E@kO`Rp<Au_BG1=OV!rFO_u@CYwGQ2?fYwQk
z@x_zz7~R^KP?q1(t&NFg-4Bj#ZA>!Y=+?$$dqP3CYC``hQdmu5y0tMSy9J^^@@tc@
zqBr(zJrQPfeNJJT6s*QG;EfgC8m*{)4K!ACYjmEyvc`&TjaEAUqy_jd!Cp9VM7Ktl
zRTnZcCfF+QXLEY(KLOo&GygNIw&XfZyzNeAt9u%M25UO$m}5Z`_5N>JdFW)=*Ot9Y
zny!dKow5<RXBKtnWiQfnQ_IEMgKT{7W%7)P)%}Uah4RjS!wa6&|2@_at80i=BRt`Y
zd1|jAR@V@#yusHHt80kWHN+~9!!^X}8e)}iNAaS}bk`88%&XTBtBeKHlU_rtt|3<S
z-L{5UT|=y{Ay(HAt80kWHN-0P<r-oY7V>|dSlx09xY3=BSiK**^9o+nnN?d4601Ag
z!fAHpHK$0EwPkTN=29n1i=buKs#aLDD{nYu7`H0kH0D-s<4XJ9oZAMu)e~cG_0Yd!
zA%x|coA-uWb#^h5(@C5)jM$XuaC1+wJ+Js&%;dO}#BP`WAy`{ePR*`g*4n=>B~*WE
zWsdw(B=wiqOh-eS=>E|rH$~DMilobll=uCsvOmIOilqKEC24M$BB_6ELvk;e%Fl0b
zMa7pQsegGfM?*}J)W5Qza-AZne_igY_+v#<|N5+wnIftG)$XJ5mwYyck(Bn|!+KUl
zep3y}-&jAF@am073$^NY$jiPK^r|{UtMFFE{ExDDP<Xqf0;}t=7EpLQGJhM328FkK
z%&!U*-nBTj3oRQH@6A<Ujr%Jm(UwYITC72{a~|<WnHFoXPEbL|$doUG=?(c=oBN0t
z%&;apEmjmQl%LaL4Q5#RPKz~|(XEhL9WB;iy)YtqL?dpetN`n!-T(sYLdttaIM^__
zTIFT<2{tlC4@b5J8yj$1tidJ*oEB@asR5_O8f<33X|V>I8*o~z!4?Lb7HcrufYV|P
z<{0Sn8cvHf*gimG&S|j*JG9F0v{-}rMS)WzX|V<iTh#(D6G@9T*vXKzSbLGaMKo*I
z7_Z^9Sc83nEm*sB9r>ZU{7#ECSejQCIW5*;-{RJUI4#y-ztQT8v*|G97wk%iT%2*)
z-y6_2%CuO66@j>U(_#&d8zsNfVhxUW*^`OJ>?qS>4W0@f<tx387HjZy-6Ge~Vhx^g
z7qyNSYw)c3ofd2GyW)Bzc3P~#a|SAPX|V>+k6J=mPKz~o!O}P_*5FUA>ItXC8obi0
zedJDyHF&M}c!1Ml4PGzn^eLys8oW{b8enQ&TCBlami4*-s`<86a~6PlzGLNV+LRV+
zfEMdFNHn`CE!F@n)(1dawM&aNK#Nt?o7<EYYk(H3x_W+7TC7201EDD`)&MQmSLu?)
zO=+?6Oe&2cw>_HDVhzw@)xEu>Ih*HPfEKHAS?+b{pAvQ2k6PQQTe4Gf`ukmiDhldy
zHV^`|Sk((nX|V=qv0A*Qv{(bQSSRw|Z%T_56bS`QX|aMv3zeGEVhtc$m9Ey57HfbO
z>qH&^QBzv10a~mITem4K)&MQmO$nRXloo4%7OTQ$HKoNGpv9_n(@mSwVhzw@)tx=N
zDJ|9jEmp;x+w4<1v{)53uPH6o04>&CNH@PJE!F@nR>fS@loo4%7OR@SxG62x04>%Q
zq<eI0{0C^UYRJ#abjt=pfEKHU^!!Y>l<oqwSeNskRbXitag=lIIhw=L?<3?Mpv8J5
zq1<|G9-@NQ?}rj0)$ayX7maf&QIUXMp8R%Pj8tPR6<wm_GM%hAN~)nZ6o=H8A+RUC
zMwH!k=&b54`bC0coz(!H)pKcHPlYR63eZ^{%LQvnXEi`)RlsXXXEi`)RYmzt>8u9m
ztlD*^EH$|7E90K47y^|5oz(-BiF8&2s8s>4DV@~-omHWHQ#z{wI;$HKgbf7!(>Z5x
zReK){&{;hXJ%OflRs(camlMNlN@q1dXH{3rZ%SvCE&Me_44P9E6P;B(nFpHESq;!x
zRh{QGwGbbmv$`8-ep5QD0XnN|Q{v*LbXEg&R&}E+Z%Su1Kxb9x(57@&19Vn}j%`Y3
zH9%+e3zT<K^GS^{bXKnio!*qrYJkqF%3IZx&T4?ps?uHBl+J2^&Z^KgP3f!#=&TCe
z+?390fX=GWolWVi2I#B`t!_$ZH9%)odEU=hL#U#ylh9ceR^f)xSrz_9g4?~`mjZNF
ze~X|goz(!HRROOloz(!H)t5oM-1HEY*RnxpRXwfoALG$41?a5mRvn{<L4eMxuGE-c
zQd)q{s!DWaZ<r+N@cOPmSoS3utGm?(Cj#vcDf_xB$Lh982J#^$-jm-z<LFd8R(gxq
z|Igq6omD-J`Y#kfXZ5eT)JFrZB<47;@_GJMrPWp(Js?q4T5ZKK&enl!Ahb@l4Zmgs
zp>=B89BOCWUhCTJ^Y9P+T!~`!Hyh<&WC1_iyeG>w9%TxY;p{-#r=~y|&Z)@n6ez<j
z4agqCU&zH2C`%i6ZKjl_Kv`NaWWk`cu%<{(fwHt?P4~J}pe!vaPUrdJ6evqO6}JI6
z1<KOS#r*+JfwHtq@pOPwpe!veUJh^yl%-vZ_XC^)Wofsf_Sg=1qfCLav}Nrz>Qk2j
zWod3ney2cL+Pd^6z$s9cwy}AZ_LxscSoZH#d$h;Av~6}Z5_{Ij)<CEI3_iJ%%a|dk
z?3ekqm}-K>M7UuhR8w5?^b2Qx60F9J$eq;E474oOTo<gXl$3jJ68z1<VEIV+ZT|JS
zJ?7UYk<>A%JoNG-rtA}#(qnm{8!8hKly@|LMP|ZG>9M?1haOe7$Gp6YZ9pGrayzxS
zJ?60)N!w#y-rb&ARVh7IcB$D2lhR{l@6Km6+NAVYSz6a{=&?QKRg@m@C$FZI9;+xl
zs#LEjrN=5tkE*BNl+t4rrN>s?!%ZnYR#AFX%+{uq9;+xlDwD7&rN=5tk9zr`^r$HE
z#`l%s=Mo$%JyubA+#i`KJyubAR4F~S$GnQt<90lbno@eKqV(u0C#A<KN{_B`QhKbS
z^!OUdf~J%nt0+CH)L7}Uiqc~Xx%Ai`^D0V@(t~PB>9LB^qg{%olpd=nJ-R%l^jJmd
zQ7C9i>9LB^qfn_SrN=5tk1DU$6gO8z=}|R{l^&}oJ?^IRY>#;rrN_xUZktkitfKVj
z%9GM#6{Sa4-it)2qV%Y%8Z@Q!SVieksMM6wV-=-Gp;}W)k5!Z&)xKEiv5L~8Y#H>J
z(qk2+$E#JIlpd=nJqmbDDLqzEdb|<jH}6AKMd?u}XzHG*qVy<KYD(#`iqfM{ttq9)
zDoT&KC{a^Nk5!Z&g|x?f1LBl@wZZn7S5bPDsK@r0S5bQ0ou)LU^jJmdQNU|T>9LB^
zqiea89;+xlDlBM9>9LB^qiea89;+xls<c{DN{>~P9);>nDLqzEdfbO}QBz8fRg@lu
zI+{{?tfKVzVNg#~N{>~P9uEffHTAlxqV%ZJ2bxlPtfKUI1Ywh!QhKbS^r$O4wJD{?
zDoT$kZ(37Ik5!Z&b)DC3O6jqR(xcGyrntE(N{>P_no@eKqVy=VUQ<esRg@luW;Uht
zSViekX#J*?9;+xl3T@DQTh|1oN1+XyQhKbS^r)Vg)s)g>6{Sa^O`B4BtfKTNG`o3-
zVxsh@9-P~h(qk2+M}^I6O6jqR(xXO;_L#5Fe|FQ_RnvV~_SHvaUpIs)JyubARB*rc
zm{(DHR6hMuldGcisK|lR-GImL=}o+TdjO#HxJrS#TfdhCHoSiAF|VTZco(vM?J=*S
z^!OD2%f6!aYma#qrAIZoUwh1}C_NgOLNQg89t}w8vC4GUfRrAqC_NgG(qomGuO2`B
z+GAct>G4J7CZ)$JN{<#z(}5~VkNrdo)C)&&SB+mzly@^;zxJ3{QF{Ck!hY>BucGvL
z4xsF>P{pP6SViekqJHf$ucGv5KuV8QlpX~F{oIGMo{7AE?J=*S^mvB?mC;j4V9x8;
z9`h<nkB=bhx2FM0k8cCYz8)8Wei{tVq?@JmSVieEi>zNtk5!Z&*9MgR+Z10vTP5-7
zdF?T;qV%|);!EifJEpGrIhuc15|cgV`zVI?m{(DHR6y&b+W6u(@tD$MZ9-Xor}S8x
zSl0dElpbr73^=97+GKk|!OiIw`vEDe=CRUaZA$hOM1kbbCt*ciDr8)n(e=2(^dgt}
zfpK0{N{^#fR9{0}mD1y=^X!#XmD1y=mCi4v$5EGLG$yN3dK`6G^@sG)gmq>^-dtUr
zPA#s1F8c|YW>#HFzE0_J8{7ATn&YG+k3HIJ*`{9+TUH)4Y5Bo|Yv~o=vU0g8LCy;`
z<v>Al^3fmmTDA*a)FG8faYLfyV%qK*E~)Qb_%(hr6RA<@TB^up@J@Qu*$r*`&<CRJ
zvhjZM#j1+46FP#zi?@}t_1#Ns_79`;va%=2Uh@@1$i{ok=g1%LH8+2}*WCQ^Ui0-7
zC*EtWDMvQmYi|B{uetf-z2@^2C$-l+D~d3eq6oFu{3IfMfW78ZiDrAv75{zqnyW1%
z_L^r?d(E@M_L^toz2;Wgc(1v-^FQ2cu2Kf~nhOl>H5VA%YcBBj_nNB}l=lonWaM6R
zB_33X6d2rVE-<*)TwrjoxxnCFbAiFV<^qFz%>@ScnhW&(qxYJtT_0$#xk~@f>@{~8
zf8f35mc3UsmhL~=Yi@Dlz2@={?lsqVAKYs$@cw(vmFEA%UUQYRX=4FT^8egkbETXA
z-`;DkT$X!n`X`;Fq3y_Sues#(_kXz8+~WNg_L?hQ?QiTgSJ=9LW3RcwW__T&=88G@
z1MM|e%tila_nODc8R@;|s)g+rw9BDwI!%L;b0t3LUh_D*?KPMG{r8&d@%tdt=%Vh!
zn76aN=I%lEpWkb)qWpjCUUNOoW8Tj8n!BpL&t7w@^M7Hlx#~P`aIg7(p#Qyl%~js2
zfAC&&<q2=6ttYnETzvs=Cv1Doh0}Y@h5rkC&6Nz^PXBDLxx@d-z2-{v!S|Z0WsLjx
z+iR|j{@z~mY`oX}VB%#{d(E?{z2@1}Uh`~fuX#4L*F2lrYo1N*HP5E@nrGi<uel~!
z$zF3cV`#6rYW{!gUUSv@{r8$H<o)-WE98UkHCJrgYaVyQFPW#84y$OJ^H{CpmTOgQ
z+^za1(K>GVEf=bF-16Hcb>>*D<Cfo!%&&Fa^4mS;|0;pycP&m<glxqTvRN6WtvEt9
zE2FfPwc9m0?7y9&vLa!toA>+(zuU!Loo&38k+9V{jvzCmwAC#gM@RL(qm<gkUfZ}U
zERoVk*xG{N0)XveuPv-8k|SYj>0Ru#Ma6fC<w)4tPQ{3?O-I7kb}p_5a3pMPm*UO<
zN5a+?7mors61KK$aV5Z!u(jQaHv^Jg?6oax-zIb0#a^3RlHZZAwXI9v12_`4wvBaC
zKug}Gl2w0|+9MLSwry5Tuvx(yc$)Sz_!?@epNanvK~?`3NlZ1tVj|4px8!PyORkHV
zr0hz9)wmJ4lX{~hSj~08Dl$pEM-qJAV6c27bi3G(Pr}tFspNW@66v3j+D7$%#WT)p
zzk`3aQGL|t0f}s*`lvBh{j6+()*Vlq6;E4tJZ<|6L}c*<f#YejvISb-rNf3)fyvx(
zo;G_1W!HD_(1^Fq>5W}#8hExjy|H)aYWc;}HkQ^kV%+BR2%h#X^0Lk85j?F*b(_<p
zVVlz<c-l7!bDPs6cv{7Do6{qBT4mxkr$_L#qFmr<6-D0U<uCkrf@7XGf~VaLnens{
zJgrJ`o6{qB+Ku`0v(4!dJguvoc-m;#=JW`j_F3|9o6{qBT9q2}v=Kb*D?qn7J%Xpb
zPI-!_jfQPbkA`hdkA`hdkA`hdkKk!lp4*%r!PBZ{F;5%8({4)%ZgYABPus<_!#1Z!
z!#1Z!!#1Z!@U*(BZgYABPb=g$r$_L#LT+<<1W&8>#XK#x#<TyT@{FgA;At;WdE#j!
zcv=CsIX!}>{SwG+PLJSeh1}-!2%c8RZBCEiX@%V8^a!3-7sYK(kKk#Av^jkuaZ);z
z5j?F#ZgYABPdkr?o^4K#;AsWi=JaUT=JW`jR$*>)dIV4FS}vY8f~Qq!ZgYABPb=g$
zr$_L#3rXiTr$_L#LT+<<1W&sd<Tj^A@U(k@+~)KMo_1(+dIV3qj4-!3J%Xpzm35ob
zBY0Ys=QgKD@U*(lZgYABPb=g$r$_L#LT+<<1Wzlpo^4K#;Aw^2=JW`jR>*BmkKk#A
z+~)KMo>s_hPLJSe)e~-WdIV1^<Tj^A@U%j1b9w|%s~&Wl(<69Vg}Ke?5j?F%i#DfE
z;D6P>#jcv}!>X@7s`|PijHiv@X%%dn(<69V<zt)EBY0Xx4wO#sGP|ea&FK+5?WYu|
zyY=fyV7xg!f~UO>nQcyw;AwvXsQQX(o6{qBS~c1>r$_L#2E@}w@U#ZR(?;;L2E@}w
z@U#ZR(?;;Ldi>bt^a!3-q`GZRkKk!7nt0j>p0+`>K)tYxXUKpamGHD?3p9eK-4UT}
zPLJSePXtu`15|PGv=Kb5M7B9Sf~Pego;HG~6$te6FF5O&cyoFLPkXfjmC;X<z?`!M
z8o|^48#3FR9>LT8JD}?8aS`ap=V_gEvv}GFp7vG67f&0((~c%W)xSdV^)oYxA8$^N
z;Asbt+2-^Jp4OWGXIk^2Bqp2F7b=E$+6bOj0j-nT#usnGV?1r!gtGjOr)`^9*8Sjk
z+O|ms98cRe*`83b4&^<hu$uRJS=j<@o02^eQ6RZ2i&|K`IlXO0*Y^>P{n-K@D(loW
z$i_Y(|GMT6GzTcs&*R*t_4XCjcNAUxZTorlDzi=N?JJ#s5=q-H$yhexZ`&`cUc-nP
ze*yB$>_BgMY=l1G2jl-)k~x7Ug1PL2lKfVZEn~^UNG4n=$<FzNY0a#<mzqorzK(R)
zg7RW3`y|O$!^N_)<7E!aPW}bBW#!?MAF}^Pdft?~$);uF$x4u2>zMry1I*O}X(}0c
zEt}XwhGV+Ku6lp|7k(YlyWT>sFEM7l<#yT6+xG(zz3)%%#%B=@BXs|!e&*lR$@~sg
zN^~+WmS4s_(aDtDY3BSCkMZ=ePNt5*cwe2&%Ly3L$y735gzKPAroTH~kUy`cwZ!+)
z&x|Qp@x@hBl*HVpj9NM?mD3w$;Iih-eVQsnxHeZCbDsi(6s*7?1uI~OMPcsqi)1B5
z$<6p5h^6NkcGoV-ODNcN8Q+PyPbD6tU<C##Sb;$bR$!2V6&R#o1qLZtfk6sZV32|p
z=<`N7MM=zku23CfbD#1Ln)?(uwH}-MR13UJJvR3#Bt^+l{6B+ecD=@UqXx}=>hMC>
zksqqd?-V65_o>ncDcBzpGHC8oeIZ3j<rn;lAGtW=vRMUgR1<TbWga<+xlj2A&3#(-
zWHJ?5H8J<O6zZ_%%zawqnltxlacj=pr~H41g002oKA)jVgXTV!W{`qaPYjy-{1G#6
zrznZJPmeE)L35u2fI)Mgn*-coQJDKw*6y$<%zdhw?yxA#eX5*I?XW0Ou%g)9VNo*o
zxftXQi;}rd<>3yClDSW%n{S6j$=s*ZrQKmsGWU5hUE&UllDW?um3N0l$=s)IICof-
z%zY}C<({ojDN(!qsI~37ui6z%f1gcIML{WZpXvoWEK24+EuI|~C3BxQQ*C!xl+1k!
zxx=Dl?o-Ge7A13^N>{VPqGay#W=-p&#N4OC++k5N_xT;d++k5N_o=X1c370med<&h
zcUY9ned^Ah9VO;I6?3i~7A13^3Uh}=$=v4?q;rQw$=s)6F0#X-WbRYVcZWsE+^1CU
zhRl6x$fwMGYDlNded;)<l)2BNXmHBh=Np8YqNIkc_4{jdWUAi{sxBJmRH7n5+5Z{8
z&2y1zjHRMWlw77fL6)V4-cTG;PeEXcks48U*TsbE@&xmyON@Iq7@kAMJ#~VT9TrtU
zQBr_eHSb*+_f#!?J1k1ZJ?%PEmKt34mGO{q&p#@Y#JHz`J1k1ZJ%!w1Q8MnCB3$1k
zAg-z-TqC;94vUg;&*kLd4vUg;PhBl{Sd@%=Dxy0qO2$3)WOj!|$+)NLJkJh`l5x-7
zK<=<88TS-V?GB5QaZlYS%OfdD%DAV{q0zxi5M|s`=-4PR?m0kt?yx8s_nZlGhegS_
zr^;JphegS_r_#B@qGa4t$Q>3X<DNq9uqYY#6mo|}$+)MGJ1k1ZJ(XvyD5;{YlVU|l
z6>d0Il$@L3gmC=`0y`{9#ythxVNo*f`7scRl6pGHYuUt#k{bUpc7&^L)j{K)x>AG2
zJyoJxl3$%98aymYk}<klZE!M59>8DrbytqjZIcXS*%mGPQsWG4fHK3i(o=-1o<@Vl
zJwFKu-sBFMMobQi8pl67EGig1Adwvw6~u~?$1rbb+0Hhe^uNXIt2n)?;bU3^hg<so
zZHSWDsQh6i{k`US8=HUJ6v;QWZ5_Gn!&s9aIAv2LbM0ukWGa?fC8fym8(4_7h}HdZ
zckNEZZ5lF4-?H+AapRTKw)T`^o;YE5Qp{s2*F)cBwkzj>6B9gXIS7>iG!2yTDx%Rb
zUS`kSIN;>%E%Z=tiUJ=@0?)|C0S9^BT6MMf!XT?srm7+>7fw}0ytS7q<mf;kJIz9l
zwJLJVspeYV>C8go8Rxk~)r|8wiWs23{<PnJ+uG6y)AehPB=vH!QTZC%adPX0E9qy=
zGN&iw^D;a|&3=+uW^Thkir_ZO%%zRW=h8;yb7`aUxwKLFT-vC7E^Smkmo_S&o1HQ$
zpG%C&$Ft1b_QAobgJzkz9a`mgv&`K5qJW!a<`%Y&r}ptIGq;nWWR|J(7Oh=_v&=O|
zlJYonv&=O|l9m}*iBb7AN0P2Nl9Wf{nj=Y*S>~D}N!_bsaF%&H)1&|KBT3UokJ=%I
zTFeVlmZpRFV812Iy=>D(kg_x##0UF*R1>rJ9_$x5OVeimytsMK&BSuYnHFaUj{$7u
zxHzXGzuUf3+|q!y?_7b<js$GorKXzMk$|mxcWM%7M*_Aktt*aO1`JsS+@E=)9SIn+
z45<3LBLTx<M*@Z{10F`0I}$Kt8Bj6Zk$@q~fXc)j2^g{rxB|p7prXiY?|wc>h0jQE
zybKt!4A_FqmH|VS0ac1y1`JsSe3l?P5-?;L&{a;$fZ?zs0YjDnKTSk;Bw)xgph}IG
z0YjDnzYKKCfFa9(yJ;ao%YfmqBLTx<M*@b!jsy&c9SIn+45;$lk$@q~fT~%%3>dNu
z_=?K2?HVD=fcL39ZPy4{1{C|^*^z+Zup<FOmH{;$+>wAG%YZ`eNWhR~Kp}S|V8}9{
z+7~YahAabqm=fGFAbY%7mM2ilfFa9(0`5q_kY&K_LGDPvkYzw2cO+oQGN6z<5-?;L
zP{<t#7_tngi{g$13|R&g(sqqUC^mH@V8}9{L|xzJV<I2UY^hyLCeb%R;rcCQrSj|y
z$#BD#vIb0xoi7>AYALJ#a$fEhMcu3=yASEyVq(Z*;>H!y{ebV*ki|p+cd%f{VxoG}
zkF@C{WHC`;?qI=?#YESC$MU!cSxi*v?qI=?#Y7=@uwcky;%pUQ2MdNQCJMQO1w$4S
zw*k3>1w$4S=Y!nAf+35ED%~9{7_ykCqvqVff+35E8XxXp!H~s7mFEr?3|UN6Yu&+u
zA&ZGZ?qI=?#Y7=@uwckyqL4dSFk~@N$Q>*gvY0634i*eqOcZhl3x+Hv3b}&?LlzU&
z6YgNaki|qHcd%f{Vxo{cSTJNUQ9bAm77STTRG2$hFk~@NV@{hsE<sxMFXs}$_afsE
zJ5rT>-Bz}k7_ykCU|UQKSxi(uwwM^Qn5f8s()|-2dosj}i6M)LrzlYO{0&K9yqFlW
zn79g=EhdI6Cf)}q`-*Cdi6M)LYP2mThAbu;m_jW=784C<F)?H@(SQ~cLlzSaXfZKl
zF;QdE7864j6Bj8rZTbjVOtfeVkc2EIp27b>y|6Q1%mY)2@@~AC7_yi+2caz{hAbu?
z3gBpURa}dSA&ZF;*<xbIVxj>pCWb5~3IzJO7H2&ZFD8a8CVozV%ILl%FkVaySxmeG
znJp%UEG9k);51qq80hEENqo9li-{qNiO(v&7864j6Kil_Wq%R96X<6G&<c+i6GIjg
zo5*Z2F=R2(ny(}G79}y+^f6m8w3ryOn5cl(Nu}|{OYzuZVrfEIez%xdnrP1gx0qO(
zWWX&ZmL}VCj>SYBg?=+BtS0fMkJ6Oveux6eA56mHg9S@7y6#3aUW<vDX`u#LF8i2P
z@;<o`$$EAkL@xUiSe*$6b|Kj?kq~F%6^e6E{)V@`U>UW{tXhw^!z5N3G6xOl+;Z8i
zp8Sv^ZJrlH@^2Q&B5dBT2-%fyeSFHXAKs63#a3OU?8>uGnecNZ*s`jJV0Ptcr%c)Z
zXfoWYsIin?`H54e9L%YNbM4?U<!=XV`ra?@9^_=6Cp{O+E4{<fg7ime|NkAF3|3mk
zQ%GW^#aQ2X6;S>`%Pbn_W|`$Xc>eY(;5<TY6;SctXBALo4O(Wo9RJ^21uXj-2eEb6
ziu`6GCEx5^PD;1(mtQB4?G#(E%1^fwc~~&|h?h?v^p{T`^p{T`^p{U@GWid}$>dX<
zOg_!Y<kOr?KF!JG)0|8`&B^4`oJ>B=$>h_VOnw9>lTUFn`7|e!PjfQ)VVq3<KjLKa
z`viB3==l`mH~*o!{BGqhpFZd>zi;tgLfpz<e!tP;r?m1XjwkprKXP{0jzRhuAYS>)
zufWOyIewpAM)~7L$?sPF^2tGeWnY8Gt^DPm3U=YX(#l`{X^ia?pq0OTe9)g({_^RA
z{_^RA{_^obf41_Me}2^C)WWU&<<kfK<^R;GH@I8*%fHh5ok30}|61>>0Jrj&f4$rR
z1@2b<@^2Jp0Nl!7{w>Set^DQRwraYSzkGbqpRN4mS^1kqBDeCFXXQ_3NZiU_o|QjU
z&#nCBlY{<j<u5;M<uA|5pB^=C<u5;M<u5;M<u5;Y(4QU7qeSiYqt>=J^ka8n**}S(
zih|;mzdR;V)C;!qmmkK-<XQQ<f@-^!KTss(R{lVvh1|+to|Ql4?^gcuto&WU9L%l!
z<&%T{BAH0Zv+{QrVQ%FwpB(gOD}Q-b{=QF`Tlveg@~6Apt^DPagZ^ygFVD)K!raPV
zo|V6cN#|Dn^2tGew(^%}<xkCbD}Q-b{!SsLTlvdlB1J<!Uir&oB1J<wUir&oBIP&4
zjaUBim`D*t5wHB^F_EGL4qN%tu(f`-)9Z)&eef`QZi_xDQIUW(5`JyvPh%`~na-sL
zlgsp1#Zi}P=ncgo^=Jfkte-}d-F19s%_HU>3FZl|mA^bDQVQHfZsjkJiIgu9!&d(C
zto#YMmA`y)te>s?<yrZ&>r7cAIhi~rQl3&KTKUUkB1OQh{N-8s6LKqm`QgX<y+S}-
z)$RxLm`KrrhpqhOlVklNnMldA@~5liR{rv={3)Va`OCBNC$`+J{N-8sQ}?))zdS2{
z9|5_QzdS2{TGw<dfB9i6fB9i6fB9i6e|b!#bWomK`OCBNHwolc{_@GOezx+LAGY$B
zAGY$BAGY$BAGY$BAGY$BA3D}g?>QB1oy5wYunITK%AfG81Z(9lkBJm961MV}XXQ`8
zt^DO#`8xu{%AX#h@>({m{OJX)@gL)!m-3iM(XDDLe|b!#=t|kjUmg=FD$$iK2F4Qo
zqdA#8CQ@|6*velX6Dc|vH~1r?zn?i1D}U|$vz5QX=mCjr<*(ol{xVZ2!P@Q1spdH2
zWa6bjjSMr2QB3hO#h9PbJl6P`Vv3(B#{7(Cy6?l!6jS_6>*hUo6U*^4t+Rut0mjd?
z&Z)@n_?gx%4Tzr+n`8V;nBr%`6h9L#tt*b>XG-uhM=?(~ex?LJqxw32rZkM7DZ$U^
zGt2QaCHNV|bo@*Seny!%ex?LJ^9d0AjH1YE7n28v@X7?o{7eacrh?4)nG*brN^$&5
z34Z2ff{dRj!OytLiJvJA<7Z0nGhZU2<7Z0nGb%OaXG-uh*8?3tQ-Yt_kFOTvXG+8P
znbI(RrZkM7DGlRiO7Jr(&+#)Q_!-qK=4VRqGw-TA<7Z0nGe1^&;%7?3_?gl$ex?LJ
zV_!az%xRS1XM`L-Q-Yrna{NpQen#z!`I!>@%n_8}_?Z&?jJ~prpDDr52snPG1V6JI
z$ni5J_!%L`&y?V2gd9Ipf}as`{7eacMi<5LGbQ*LA@MW6rq~oeQ-Yt7$ni5J_?fSe
ziSaWf_!*^g{7eacMgzw2GbQ*L^<T`-l;CF$CY|GFO7JuK*fM^m1V1C-_?gl$ex?LJ
zqcF$Ml;CGv|B0U|!Oy64$Iq1DXM`L-Q-Yrn>*DyC68wyi<7Z0nGh$sFKU0FAu`lgN
zE0LvP{7eac=0n7E{7eacM&rZrGbQ*LmFM`G68wx>>-d=x{EU#}XG-uhLXMv)!OsXe
zex?LJBjos*68wyi<7Z0nGeVA^DZ$SOIew-DKck*-{7eacM#%9qCHNU3$Iq1DXVim^
zpDDr5D9rIQCHNVQIq@@Mcgy})xkP1OcXQcSAC-OGR>sei;Aa$U{7eacM)?>&Q-YsS
z<Ur}ZfXAK;F+Wp+pE*x~y65jq0$~Ycl%oVca}6@%XG-uhKL(V2MKyk=1V5uj8$VNm
zpD`eQrUXA@K>SPze#U_KnG*br0r4{>_!*5!<7Z0nGe*gXpDDr5STyl7CHR?@{14O%
zvP3$JpDDr5EI?@dObLGG1OVDhs<`->68wxr#?O@CXAFp+DZ$SO1p4_J&Uz;1XG-uh
zS1M2${WuAX`I!>@%)Q8rpDDr5`~gt*_0S3Q(~>Y5F+Wp+pLtpF#m|)BXL^WG_LtB*
zfqrHr@#%RP<tV|=^dmEVrUXA@%|DjrFG*s;&&*d0@iQg(83nXXDvvM9?uzj<<q2i^
z9Y0f^XwL%2&y*(_aQsYpvOVWwe&%jcSU1G{OnFN7a72ORk0oI-KU1F3bw8r<Qt*bK
z(ICrZpB&_8X2xvHV}tz6tXT4d_?h))lIocJ)OWq$L28*<b$`Oo95Yc9hL)AfCj53G
z0VlBe&FGrRx1wdenE0l1^YQGlB$$%mwZ285>D)}d1mEdI)8r=eiNZ>vO})}W5A`hY
z_9XC}+)YD)2YG8N<xdFYl6aX53UMlC9~1XeZMVpaw&~+Zlv$;yMiy-`UbW4x{KLnm
z8CkStt42(A<?A1JWD&+-$u7I{<&RG@vS@Bm13SC&PamHqvS{m=EIQIPcH3c%J(l9E
zv3q9srMxK#jvIR@%0#NiYNA<Vm*zeWjH{irCkb4h8*0xwiGq>3blq6NNZssBj}?pr
zvNK`@BMb3P>E%V{ec@aDI+gZlkt4HSr^_zopysO&{6H%0wx2S)cKe<bXY|1P>$q!U
ziobc!iNwm8r8|Fi@D)J*0{YjVQ<2}x@5=4sZ)w2i^zXxw1%6Ss&2qcc=7EZ`ZI;`+
zbFuu|GnZRhSFG0e)1fz`DEalvKO{m{#!m{)#<3YKDLA7g;hz~Z0Y*ziiIx1qRoM*~
z5oK8`EL>A6$S)oG!nF;_*+k0EHu$QFpY>`%;qu}k;QTYRqi|(GWqJ8K`6*nNlNmMN
zGovMi>$6H`MoS7`?S4uT{Iik7W&lRXpOw~pvDvA<%$e4Fah>3=1ms2e6sI@jH}k^9
z8CH^?m)3l7MyO(g{B;uqB7ss~Mi7fLx&_R<aB;oR<9j)x+)K%(@)>?=2&^TP_Y8QT
zxM6S+vb@X-7dI*@F-=3UsJO8KKYs=$mx`Mh2=Y@afK3gQ^7<AiZf2mCpT@N*Zf+pT
zchiH#Eev$z4-uGcpeKL5vYun0FEKA%+&&O1m6twKafep<z5H2vT+J^EIP=2Ag{^9V
z=gbQicQS-NQ{@_j&k@bqHE3SAxKFSa*VJ|7hwAcs`FB;xrFpf|&-e2VEACsIPDqfK
z{(f=4(dvt{=`iJ2nS)F&&bZ)j3uw!k)_ieAa3m-%?yPv+DEYnoxZ427yX?tCLnmii
z^Tnrvd+98h7cM?sx5zRtTztk|RGAkpK5PCUzZHYO7@HT)-^#!$rp*f%pC2`kvTFGk
z)RY%2O-FvRF8!Zc)e}AWnI{8Y>7B`^Vqbnbit5GJdOr*p$ls(Z@p}0zz@+?&(*SQ2
zWzyA|7cRbKSv&K>#kZ}R&b)B(9V^F~7cRn`T}>iqUbqN%_Ael3UbqN%rs_HK!bP|<
zb+t1uT!cIOBWRJC7cRn`JxP~1^TI{Av*Wn9&b)9D?o79sGcOE3WWxpX!pcmEI_*cT
z?L3Wmos!evzb9yvf@1T+MYuEdf|(aC!kt+>GcR0(J8N+Loq1tUB;?EsgGLKE^TI{A
zGo^Fpg^O@!4LaMI7cRn`Da@G{F2bEnBFvc=F2bED%$XN1!kukIm@_Y2ggeun?aT`o
z;m#D(nHMg?ohi(j7cRn`>C4%f7cRn`DW)?oT!cGQ^PPF&BHY=(2XvvC7cRn`X~@Us
zg^O@!8q%?O;Ue6bUJ6X@WL~%kclHzdiTT_k<X(h3(^L-btl(?dTEC0FO7*)z)rC0!
zL?uQ^Q1CbAx8qHu8e^&G5+#@EV8u~V4ZWc_r2Z5Fd*EtB*<IJ-@OKl;d`R3`5$^0b
zn&-?57vavzTre{)T!cFlaOQ=JaAzvYnHMg?o!ND!EH${`D`RI~xCnQ)vog6vHwoOC
zfHN;#ggX;*=7o!cTJset&+kV-T-DwOi*RSha}mtEa1riIFAZm2xCnQqtL4lK7vatn
z(U})6!ky{K?92-n;m%ZNXI{7ncXlAinHMg?opn;8GcR0(JJXHg%nKLc&V-zK;Ue6b
zkTWk_ggZNn@|=0$;{Rgr-Q%mMuD{{Aoy<9BPELkoI3(nD2qAYMgaAQMqoPKQ2pTnF
zl!#G-28j?MDpqRMdO>THTHB(vii-D3ZHuiJ>aA93i&hJ^v|8(}7L}^CwrYL8-?e9-
z6X?(P>HB-%&!@lV`Q(qB%y+N7*IsMw%gn63_8$1oz5%3;7mmSq#`@Ip!ZG;HSWX=;
z9E0zSNF6U6gYS$;9WNY%?~F(tFC2sKjA)Y_FC2sKj69z<lDyBcYB5rg!mM1dtMIKF
z^LXJHd}qHvf*da#gYS$$9WNY%@9g(LgGQ2*C@+Ogsgb0m+5baawlfCb8HcJIFC2sK
zj4dU{3&-F)V~whA#;!}D@OWX@Vahm;R_UDRB@AhI9gfOz95%WmA0^5A<2T8E)Q1aU
z6do@egYS&9ksL1^gYWDOfaLMW$@hWr#;A+%FUI4A<7Jghit%{ic=>1=&JJB=a{Vhv
z?hQMaz*FZEjCu-%<Xi%8*trDW5ry(-_D2x^i*pIQqoq@-vthL}OU{O+Gm9M6*|2nG
zZ2(Yb!_t|x6*P4=ES*`*sm_MYIJ4wz*sL>4vhWo+G>Txp#tJTHtPdvH(3#~ez-^Dt
zEY_mVhSkn2IUAPFEG3+FW+~x#Hf+Y3C1=BComt*;*jhWY)Y-7wnI&h#(wRjrhMWyc
zXO`m0vtjAXB2s6=(wRl1&W6o6v*c`8I<qKQzTxo*VC~FOXTxe|mYfYsXO^mur$N%0
zMdYO3Ndm!{#THX%!_t{Wq|Sz=GmA)_4V!glc^8sR=*&`Q!)j-ioDG|CX35#G8E01N
zDQcpfS#maP#+fB&!)BaWayBfTS!@(_HY}Z4L@5jidahiDI(VHlS?J7CXT#DB1&^jW
z8<uV;0(CYl-B3#N+t~x)h9XU!4NEta(p<ZtSerT<mTo8_bv7*BP&p{4&W5EMib$Oe
zOE**kNSzH!H&i~5IvbX5DAumdhNT;-5Hxi*Y{m^GXT#DB#ro9QuyjMQoz>Z}bVCuT
zvtj9mB2s6=(hWtV&W5EMib$OeOE(meIvbX5C?a(>EZtB<>TFoLp=b$pHZ0vxMCxo<
zx}k{F*|2m&(Squ1Sh}G|Q)k0w-B7N>pgz~3r_dEQl<Uw&uDGGR5<G9y4MlP#&xWNN
zihLsWhj`(y<O#8KMzKi5_BT7xB**dzfHIzE8I?RImM*FJlI6~yMxsf2n=a5<3XDqa
zm>Q5Q4R=SPl{_<+?y1`)DGkQ1IH@YTF&olJMUzDA0E9}Oo<LWXN_vfQX@`|cdWT8c
zZKaZSFiAVFR8oSxhP$vLb}o~6x-1=8Kav_>XF=`GQUyO{l6GpnC%N82Qj(Tsn9u~?
zg%EmF$@6CE+Bz1A5&O<Zp(jtBrGx7#Nh%aQ%b-uCc5^Ah$E+fc#o_EyNe*SxE-#g|
zleO~l5BL-N2S(*7oDSgldQNH>coFtz1r7`>St3T|QZk17>qE)1<9Wy>a}k_ib;uU6
z4Uvmpuq1yNM5LRSp-OaxHA=>H_o1wIh@C7+Q7KE0Sdu@hbXl~!c8m2%#?23-EKjVZ
zb4;1B1Z9)YqlWu+sn3m3H{x2(t)+{MgsLCn$E?CZx6LczggRj!&}uiz#(AR9jJ|+p
zD0AI-cphqohJ-YhBx|U%W{1jJ!*OB_b<`ZF@N|Xe)zX=>+TD-C-5P4IDVZ<D=W+m8
zLq^Rv4-<SmCk|`Ksa@JX!2GAF{B3o6GXMFm&nAHztM1jgz!$jw-BNy_z8B7yPa&bW
zgD!C+>!EyuPMCNms5q|{JIChYs<p^e{-Dd<*ki~y=~yB67{cYsu_2e|-PqgYq7y<c
zy&;$G;*iVl+*lMA3AuC|lUc{0roQ4vLP{5=w(F_pA9CDYhzbm2(v4Fyf!h5cXROk`
zS84ZJ&Mw-m*4q6!Cw4vxHRyz_c2e^L$cKJvnD6Ao!kYUrjXuVjAIXuX43MQmYUioJ
zHCxzJkL1V^!U)T1>O1Ll!`zgUP)&OdCNN%2`6oGCuQ=Q=#*7XKhk868)YMb{>vM|9
z4jdH6>vL)q?pGXd$a0+Ov%u*&dClO1W`P~%gHO|0hIvL#uCBLnf7UoB$L&j*(WfQX
zkC97R=fK^pgDlea?KzPfkf~vHm=IbACJ^fcs8Fo4AV;?g>TiCLCaBMG9hB;onrz%~
zm0tDQGJ{I5`kWfAXXW>#*fiBk`;F!csF#=H-aA@bcvgmwms6z54c16GFQ;0S8!)E*
zg!TU>lD9c9qpwN*Uq-p6#fG^(B9C>}(8{`3nCW*BnU**P-XQ+H#(l=LcWJMqB6)4#
za)EHUja<a9dQ2p2&y~j1h0Hf4lDEA;TmR*-wyC<dbLwizeOe?L>S|0sfx6{J@@_z>
z*}{F=@5pGYlea0~jJ_gCEtvl(_HP|uDYv4okBqiEK5uLkdqC9CxX);AXTlF1w-a2H
z@xKHvHGfgb)w<lntn5clZfHc-@`w|5mX${H$IO1I<93fSqaTYb4(>KJGI3n$)T@c3
zuO^3FE_3Snyn-{U>(;W^<&LlLV4c)@g_drBUGi&=ue#*&x-T>LkjBgERuNyN@fk+*
z?PTBQxcB;I^j?wT;EWV~&IBdJfYNP=Ga=NCwJdcq1FrcFvfamVd-Kd_8y?|s`Zl?o
zN#^@FwMy1LCHsE6$v$Tn+4tA7EjOCyvUoWxl*AYiuD>Q%(YV|huVfL8$7N-yp3i3A
zYRkm2En!Cax@oRE9j-)Ga;qJd?5i2a3bxu)Hb8OMwsy(#(}?#}*6XR6LbbNqZ3=g*
zN&O{TcW7GSH@5EXO@rt~8m*|4`^|QZ&opLSOS!&pyBi@>S}fgi1(R;HW9)g?W|A9Y
ztoBgb-4-{an?(A~LQEslGY+%ETgrf%Ryyo(((RX<!A=yBY2`RO@;9j5pc8hx8B}`V
zw6f5Sj0W>?;_WkpOB<-dWtE+~C#VfNA>`5%PEI|LSth3|?A*-l#F)8^YI(NX4`I~!
zXuOCjy=1v-V`g-_C_lMK&y3rxUG5tjkwq$h)r$RymFtA;%qVw7AKaz#H?7gzc2R-%
zvl>l(+Zz2*mfEZCsIxWo9cxqoK|<ks)SNp{Q+Ha!)M}nZ9Ued|6a-u&I(##u!w<C%
zgJQrMt;54s>`Tbhpc6tJ20{Z4BA@8+xHatF*I31Vd7<SNM$PC>smVq>v}*8+bxrCS
zVm7jfwXU#YZ?PtwkhPZFN8Um{sp&hJns6VPaXxEWY`L3VGukdS%{-k+b(XsdNzfQ$
zr+PD!noQ}ZTTC;0C&GQqb$`MVQB9yoRceU0)=XjBH<^1A+d~hXS97*XID)|t_Rz-j
zYEB=L94E2U+d~hWSF=RrI8)7&hMFas%~6WwfSTc^nWOaF(|?9x&M-&u5fh7wbxkZj
z(;UTTbZcm7T_Yvh!yKii^S-*viD#MO8?lB?Q&!y59HpMbdZfLcz$Z1uiszV-Nl>dn
zCxlk)3ZJ32IH46EH1pe$FYGs+s#i5eLh2J{?9?o^Ls75P)GcP@;w-h@5DC_SDiS<z
zM((8qIw6z*Eg`-Bp`5Ue&&)Bu$Z}~@J+}*OCas*Z^wYu|!`NdTN}E4)w-{#BkojZ-
zs+y(lSL2jfyJzi9JN>XxwL;e{X_X)DrC{f5dB%EB-&gjO$Jrn2al03vW?RrPM1$>-
zGw{Db<4^(gw!P#*6WK(>mt$8TTWG;vV{a1g)Wp}c_?T*1_hkz&kqMnkliQ?IGP_b?
zNrh6ON2#!6ijuiosjy`4P$Q+n(p^<JV;2>AVIWcAsz@`~H)tHH&}%3uHz1p+uvSY6
z<@V7_u(ZX#;SwzSn6Y2D1WRDg3724nV!VwObnvQzU$q4L6jaSanQQSlz7Y=<FD)Bc
zf*o0cMTZz!f*o0c9a(}MS%Mu|f*o0c9a(~fi*FL1rbd=v`I0lT1k05uy`NxY2^Pa*
z1D+U1mSEN5>Hj55u=06My#y<t=hTa@vg~>!{4L?SoP3^>%dYz)O%`02X=3<!PVNL)
zgf#g)Czo2+0H{S)`8=myWR=fz>gCmn;R~x3!<SSmhA*a83|~f-&vWVpRQWt7cLLCz
zS}}alRF+E%@!nhcB04UXOXc&NTrPEyD4*x#LTM9#>u?2AKF`UW08En4b8>N1fL<0Q
zNb+YX{=x-O`8+2VL>H1sMr$-N{5&U@Lb)_4pXcOGfLj1u*$E)apAYH$_zJ3C{=Ad<
z^};8&<-4*IK$bjr==|a5Ik^*HJM#};?388B6x>-NCYCvKaGhD^Bw@mZhr<POmgC;p
zXhzq=M&`OJkz92rJtJp1l?+&b1G`#W#H*YF>W%fo>P8m(l2gF;#ZpG~cbWe@r$FT&
ztX@z0YK;esn%^?Rp-w)XX&Wb-(GR7r9htfgbsAOKzN#vgJ=AICE}cx>hdFtw?*8iQ
zNuTHBDZkuGqxOFC_8fQHB)$03Gzwl#EQ=I5`N~_jqWV0R8tde1iJv1b))@ZjWlY#^
z=M79Wqdnrx+6XRHqUm<KE-a@kv)$fHOFIW^Y$!H2l(uS`VsmWh>aP;7<aT?BlA~K$
z=J$3GTB;7N{+I1Q<z8ttyiHxMwLP-i-e5+r6+0c3uO+$Go}eV@trADtwRRJUIES=a
zB>9%@D@j&Viz{uNcH<9D{1tpcB~VTrQFq&sStvJ2Cro|?R9P8rd=OXjkWV~O_u7#u
zPYJ1?{f}}s*;EmcZLFxj7At26pD@?)b4$uv#df8Vv8_sEDz>L8ndVHD)$C%sRq5NR
zbSSplsRO;b)za}w?XV*asKzd{3shq-uU^2q%Wc`>XAPZPEu94+sH%cf>z4JvpyPD@
z#mWfd?E<>Rpq?1vX~--_m~KZ}A@wAk5E`Ky$EVT=?RB9M_OX-4BVTBUE=3K{I%1;b
zcK)g?wNp`hHT5hz@~tej!w?BpgDMi7YeycV1Uey<03LH`h6gm4^D@ma5AMTzXoOcS
zX#gL}Kwvb$u~@oPo!~Vqv`5$p-mpUbRVPSm{r_x5T2W|{PS~vzbReH-_>MKK6Et1T
z+8b5vgX7Uf#cBT<R?t-QH(JvC_RzKGsrGNQr2Xxowdbkf(P&8ru!pWZPmPa8>u`<_
zduYvhs!KFli&VEZsu9}+$G=s;Eo}DCy7N?%Pt_{+sSh(WTM`-vKYg_<u1(YUwCYDV
zq^4V87h0*hM2j{_zcfgDW!NAKtjG~?k51AFp-JE^mM&pT2u*ULm462Eg<YasQQI`N
z*UJA|mKt`L2Q+oLm48>38g`gZHFeO+e>O`+hhbOjs|xGAz{>wqmO4*SAJEiGtb7;d
z3Z-gS)O2-NcCD2^Axmvj)Lu>frj@^6mO4jKS83{ZtmFw<YOCtTH-IYL_!cX2DX5cl
zf>@2?S(~jU6yZ)QcAI9yMH^MiCQbgCmH%{>{J?o?6uhO$zX<!GJ#;TP*CyE!H=Ax>
zg&9rAjQtE&CRHcgY>roRP*;_#KWsJ|Rfp<S9c;6?m%<%&vI6l79MvXM#B$X?wwT(1
zFa2W!st`@zFeA%R$t0bS9Wv5RuOXidnYYZ?5b}jBfh|^S#S)Abp}uRz?#WVnl$!H2
z^#fB6Hw^5i9%{M9lvRo~<MbWw8Z133P1l&=Y}>6gU1LsBnsq5n*O+^Unk!AO*iF+b
zchz(=s!(leMvmk9rcT&R)2P;TgBd#q`7)Zy#5G4#@5<<cA=FetT}sV7HcfvyDv~g&
zN3gu8bSX8fRjbWYcZyPTs%n*XrAw*SrLDT1tjf*IsFoW?+6-?T{nbyBKF$oEQ2N3f
zff-JOz0#`NDFWxtnP%i52r)?~>^ABL(qX$DZ04VWe7lbNwVFED%)c;84M%+?>?v)&
z$V}dprFN<|@6goK%w)*515r48Q}``nrol2D#jy-awbSH=x}{3p?s}%lGr*Q+)xh1;
z<zeOd@EK=dx;z2Akgx82gERO5@Br9}%CAOdf!`#JLyd8hpTVBm0L!SJ8tX*1P_#ay
zg~T>Z{7Wp;>PGWNoMyY^p2S6_SEOl~eVRzsRi#?CL#fa;O{p+%nmjOd?HjhU(x|IL
zY1B4d?(fHkx3jaS%SU(?hEx6W=`yu<hkf8IrSGD!i3ddAnvzi8b0hVTWs=6(-YojQ
zf^4Gi#mP2g%cv#9d8Hw7ZStfnu}4|z2~GTN^875ZTM?UKZDD&?@;g~#S7=5}yk9qc
zr(w+0t9@*&J%+FL%^JSiH+z@WzI|{<aEyC@npy2T;s~|cH*X3;6>)nWyJ}>$Z)CL(
zGu_B)-^gm;$ZFrnYTw9e-^gm;$Z8)PS|h7{BO5ON$8Wg&BVGp!6YrS*zKC^AO~k`}
z;$1U$1D@xM)R&3gQ^-lR67AF*JSPzSMQ`w2L-fAh;F(YKfkJ`dZABG{4^25EEW5#T
z6YJw?^4#D_U}QFUJ_Y1tHh2<6GaEdK5}6I2ME?I~gXdw$<L<h;$fWEB&wh9eQalHq
z8$1cVXoDwd|D6q<D^M=G!ILPv!E+T*c7x~nKwq@M^J38cPv7843;uf>JYSMl<K|4)
zp^bLi;7Rg-y}HQEvby*rE_PpC{62}?&iSe)4qIJ(9%-4?#ZLkL)2oXYV@2#=Ru@-t
zB~EX{yb-{4co<P;b&*M#)kOh%b&(*+pO^8s`|9E^NhG6BHF4PLB3A@6tBYLQ8@9UG
z0I1EZR~NYrH?z8UfaKqd221j%OXnZ9y4cSA|FXJxk<N+L#TCq<&lw|O!dOf)=GRQO
zbGjKG-t`M4SFL68x6LG_#4fpNtkkVjyZ)`AWk$`X^nUdykLQ)s^p3YKtj5(!$sV&r
zmF%l^$*ISjOd{3_)!A65XpiP#T^&3l8^A(bUIS)iALOgo2@Nwq#p)%T)IP4#5K^2q
zXCqd>R7eA~A}8INgIN(6(M`3j88OtDfy{Nud@a*7bF7l7w|14vTE+Pp>vBq_mR)7q
z2^J#L{$}Jw%A^xQnNV>ZWokf`BGZ9p>;vQr<?2@w4`}M48HxL_0pyz$;1kzD9WRKO
zTOekmnC_EOC1rP`c*Q@dBgq=-Y7|G}CoKwgP7$B@XWAv+B#y+-wMSg6+Nw1eZAQKU
zCiOZY)Bu8r2CI=zG$=G<-$%Ys19-%#-vgRjn$ZA$VztgV^}WNP$4|uMT~o~{?P;##
zQk&A{CuK^P9;M4q>Xq=_N|&F^3{_LQJie<gPikG7*+bTWyR^n{Ba6VkUgJ=eUidI6
z>~>@mReq=Y2b7$?oYuZfq`S7s3_lOh7-%Uk3;RWn66><+P|7ChCYSrvihE7P#9s@=
z8Wgea1v?Szy2#%tmd4qB+f1<nE!K^(6sipkj9ri<Hf!Q7T4rc7y_qu4iqn2{5vrYa
z%-(q71EiEHsn9JXW1ZTZ+}XH(2B|Fyb|{TzwJD9}HAxTK(+|giQgAO{Q3sn&A*;Q8
zJ`F(MDH!vuzGBp`l;1a0zE70zhg_n3SL7pTRj+ZVJbH=f_W-g<o1CEa>xK(Ee=aJ)
zXEE8hEyJCtGlx4-m3wtS{Kc4+upr|Yb<bv;s82#*%&A7@40y9~ap39^C+dh36&+&4
zi8|s$9dV+LI8jHOs3T6)5hp61)<>MEBTm%+@lMna@Hp=#J~w?HM4I|FUVRd#`qY7u
zx(Lty3Cof*RP0ni2as#!GUn7ty@_&(sG>zur;!#@D97;jA&jd}D`efK_p=7=HYLcq
zO*aB%-KIoYw<%H9ZA$dNbDQpiJiEC~nUr;#G8jMOHYNBXw<&4=9k*#O%4OZAL|M1#
z=|EYxDGy@%BDd+;p#7ijHl+psJ-6wz(rU_WN*nFwHYNGLcAGM@xJ`eE3+>O7o{UWy
zw~|P==?j`T%x(Gv(lTz-cLDy>Zqu{zLj5mp)5UaQYPacH0M}Vf!S%UyOv<=T1!%V^
zL6Sc_k#2Xl=}$-`qjxoNnA?;`uxH$+QOpX%+@@uK+RWN*nnYU0ZQ3IFA3=j9`7>AN
zALcgQi~0Y>Z91rP!fo2i9NKM4!UPkuig}Nfw`zZV%Fq@hSIH)fd#pO@2^UJ0oCI`_
zHC=_y^;aYE{XR7_SwrU-HMh{=veXj)S>qfW!y+NFYv4t!k`p?XT4{DDem|j@6)v@A
zkO*%e9kORwp~vi;S~(VNx#eFa)PY(#<ZM9W{#tQeovn|L>8s1bY&wVv#eH+R6*&Xt
z>UBax38-+@!s+@~g!*<vMe*N!8wZP6LJ|icCu!vdocvqrQKj@~*%#4}qQ{l+B`Q6t
zta7DCXLbMLe#5NMk}t0n3)O18Oi5a=B^?k+SA(TUI?IX_(~+qYLP`7J$fTs(kWVDt
z+ltMkBU4G+tEe0I3#o@%xkqQIJ&O8*rp~u=&&*Q0l?{B@N;r3BY|sT)+=JBn3e(*_
z8%N|xjJ+3Vov$#<l+JTh0R0u_M76;r+){CcxhGpowp55w5ap}7$<o^Ik?)Ykr&r6C
ziK|RM+)q<0-Rx@9SKX|)c3>XzuQmO!v#^_eU6(#Zne-dlyWKA)?b<Um>HTKp^a7Yv
zCxj-2c4E@RUZLVYGIQ4;Uue=!MQza3ht1sEv(yen?cXOXi)iVmv($D&Bv=KiH0oc?
z2*34IuM<KEpptaI65Xg?#`JCQpik#`u*?KiF4+TzWl1nAHwLIKXPFhs8tqeLM~h`P
zD(kkXIAzP6tp>}ST8UG3vevC3>xi~yzv{9%+McJWF6(N1s%nj>ZjByg@3^+N8f+Is
zMA0^FMt+YzQm+$2ZM#Ezx6cY~Hr34k6!}7XcPWeZY3d9!e=JnpwKWFN3#F4DVJ3OD
zT}Z|L1P+e%n%ZS1LkdjXbQqPrMa;Oa#f-v%3J-oI@=ukKdCNFuwXUhM{BX-8Wwg#_
znV&X<J+8l5CYal`%YGW?m+fFDDnAt20%__s&JNmXl&fTBDD@+;cd|nF8bVy9iBHAi
z$Q#PtV@zksJ2mlHJuktEGmfJ|9dQm7x`hWtA!eT{B6o}r2Z>Usqe&^$)goi?sBj3b
zR0?%!XTK<P0oaK`r$@dEe)SrM3iZR^&3am(w=~0<xsL#bGQ-(VVy7k!=KeNI>{SX4
zYT~(CAxyNHaAVr^-wikZ0m9fF<GEjCJmr_cD!3;Z&Vgoh3ofqv>WHU&#8ZwAG2$s7
z@sy8v%11oqBcAdRPx*+a951vZp7Ie-`TuxN`Bm6yU-&=b`z~ci!Xut2w|sinQqSQv
zBaya(4S2FNQd^0}sc*zMD!jNtp&aGiue5?Q;0_H>v6^7XAse3I{fPzZ)b~e5Jmvp^
zFUX8|%KzUSU-W;Ir#$n;mjAyz<&R)2n+Mx&!%;duR6OPIUmtGghDZNY^`9}tFpscv
z>8(e&FK`o_I2!jE)z^_rT%GK{vjZP>5Vy{^;XqX<`^W7P<=5$|xl3i8Od`Ja0$zrh
zuzkh4w+a>K+PgZ=^KAdSk~wso`x=Li^OQcJr?2iiaI91w8Tx^$?8s`AtJet)cY=y|
zVt6ij%771z#St{kj!e2rNZoXqbEXU(=O0kkP0Dfp;o)ZV(~RR>skO-poycA4g9V$c
z22QO|t5Lj~o2(Y)pX(4cAG1O=L&2ZO`q3$P^AVxo&sh=r$Ln=MC^-G-6nrD{iQvDn
zV&W-R!o!bFY82)dDh}xvPr0J@D5bY(>icllW|W@%B`SKBQgrQnoQETdE{5M%DSDP(
z=?E1)%bFA_DvF)6n_}ngs@P_56wlnHRwSRkWSy{^VudiVh>jEU8|jhWMX@eTU2DbW
zW~rfKFKFs@yD0VpDmF_gHhZ2K?G(lK4YXpjtYY0U<&zV$tlHs<?YWy`d+(~)062<b
z?N;Q^R7@xArr0Lr6UF9Pu^8&!RWS$V5$aJ^tU5~#6&ujh<9AUkiW|H6p$ez}bgmg~
z6~&Tp(W(~v(9~;Fsw;kIP6}Pc>Qw&^%{|nh>a2aa1FSyM4)c}DLH@CJkoU`=YC9~{
zG;T#+gpBn%VK+^8AfM<`Y{fpv>VjZ(_RT=sA)V0$qjB;I3UGm%f7Z35_sL?xWH?}z
zE*F?#BXy`x6kK4|shMe>(&YlJOM9&};zgzo3YXsbRWlrReM+@Uc2%wB&``CTaK1n6
zSFaO7)q2BW_XP5ZYIooxx5yVZA{MAbHMD_Hzh_2vWT{vg;LuKkDjntfW+Z@K^*SM}
z0~3!JXuIa}OGNXl-j5?Ksz)CQ17VGeE$G8QYcR=}>mJG&XpR|9uf3x10b1b!rEr^8
zcu-A{;2^>rX(~^7Wtfm{OA%%@l0~Hj8DZc=pK=RZ>jhboc<3N}n@Ae#H}HNpi3k6M
za7qjhpn0J|b-VT^S)q8LMfJM2W?9zxwO%u8mQ|gtdck5E?+V-WO+k74f1{(@r_-V}
z2Zu`RjGTnJ>opE_K(~@+c@5b_2gl6+3i5?U?N(IhkdPWR^S_&=qS4r-8#J}lOg@^W
z;<zbNw`pn>7Hm{g!7x+)N$Z>?)+ubmiGVUJU%~M{P4nlHQpT@s;Hzd$^5Lel8p4jO
z7HrN5^&b%ZSLtr6^#4+*f4}J84(8H`7e!72_j--9opw5<yb{?&|H~rhBU`4=3XdB!
zkIQ4Xk%z|FPANQI(>#W9pUU#+GG?%XYtaRyf}3))9k%7Cw8EaUrGrZv{MNd;j@eZo
z*|Stlx;?5>?Af3?MR&6d-@U`pJ1ACY)%Q$gg?;rRmS`{s%*6^Fk<-AvUgK;}79l@H
zHW3ng9P~XUyK=+s^zW|RaAnCcmOh_Zxj7g^lPfnb;AvtI!}Dx>VHux|{~?x}Ei?Lk
z{<9)i;@)6c?lKg%oXFpK4%<S=V^17&42n8!_^}*!4?bN*BOiinMcrvYHb3d+>{W6$
zGDHfH9(7uyHv;5bfpt}9pCqr1oFgHCv#$ULk1nSpE$YO+j7lR%_+%dQ16&_lgjO+P
z_w#yTK6AyL$l}unSohviw{tu=+2`Y(FK1frFOb20wgnGE4at3YEeB{WlWXrIJXl3f
zGRM3KLc(!xv8SVnb1%U5Qg=gQWaS1{8Ckg*S-BZmxfxlx8Ckg*S-BZmxfxlx!Sm6`
z%FW2iO{yI4e~DtX&XU5gco~oN?yd*7FsbD6xp;<5G+X|SD3E#>C^5|vk8HU2Vusp#
zVX3_rE#dwO!@G}J_uPGT=71!)=;L1qzGxo<Y5$#l4DBeF-N!(b-N$e^P<9_fC(sw|
zV>lkP|I_y|(1QQoK8AbHw63G}G0;Z4?PDPMzuw2d%(9Q++qlpH_Ie+~Wh8PR!$wUU
zwvS;0(lYxPcoximdLIK{IsauJ!=Xsb>|+=NaGf3suJ<u8DYK73fZoSIkmS$z@wfXv
zhMP$wqvtho*gl5Gke1oUz_Vb6?PIX;daTW?_c6TB{QBb(JPT&n$0eF{{$cwVDv<WC
z`xr6@#b6(U91x@TF_17}H64F@TJFF?GyJ$_6ffQ?gnCb_nB9OMlQ<DC@yHf>MZ*sp
z>}gGBW-NHrNceB7_FWIw@~H8RU@5MX!>!0WsH;vV)PI9+ilG6Vozjo1=I+pUa-0>J
zc&?E8sVm)jllG>3pD4%V1;^`8;y#m+@e{L5$=F?0qq0sV5j!N*2hjg%`bx$@^?`J3
zE>n15G8Tdyz3*VT(jZ4`(5Ey&g`xpIsd^8%)@=+ELJfLD4LYGIye)=VmeBz2LD%8L
z+IR}ZdNS1DIQ<pYOW}7>R({ef4K+|QJgt4H14;%I5gA@IBU4eRZey4b$^cW<(uxj5
z6B%AIWAl+Ov}B*6wrlFkW^8Ge+N)ZiM^j%lbqhfL#xp4SY9;xcF1-S96udr4^3`TV
zD0#IkMy=K%_TjPStIgTU)}1x70&sq21wd(ff!4HNG`$j4h^E(=ky2DrrxQX=`$A2d
zVF1zeRx>sW`9e)YUAi>&&f&UD`8steGTrV4_-MU23p?PYQhF4bB}$JjwNs<WtXEFc
z@F4mkbC%MhL&;sD<yI~93RsHV({WG`<<<$iwNT@+q1-cZP*7Ixu!UA>>b_=V6hsTP
z>M_JN7lSHw%rPS~L9NpXyY<8x*idW(k9x?V8$QwFsr~u{wQTQ%w^Tgp-J^9({Q9)g
zzoS{&aecUuGf#!cuiryy-#$$|>bGc*`ZV#V-|DNf{nKO)xGm#Dmni_1iP(=u-lNnT
zL!6a*I{R+NF`?93@)Hm$qq-0WH1UP}+AOi#5aP$0_(t-8ED@e#vaLbGh%w$vhAcZ_
zi%X7#Eshsk3>>W|y|+-fSthyT)2i)zrpaPM_pa(K$~cFq-g=Z5^-hg&y{1m%Y=;#&
z-a<B!W2tVFUhEQ>N;#&;ceUx-y@B(`I*P6KDNG65q<5x>HPu&Qtx#s37RoU=opLx@
zj(sCX0oG}p?SLXjr<UVDEeD3w9{M02GMY8~AfDO758~N#m($EY!O7>2QTuEBs&5y+
z4`pz-GTJehZ^Haye|^MBJ>sNBhZu2Ek2tAEoYW&u>JcaPh?9E6NsV{H|M2z#*V%;E
z>T%EFr)UH2&xZXg7vGDWTiC$sYWM}c!{mAtpEvCk!VA3lg?o^gM1prjp#&6sh-=Gn
ziuT37sB<D7{p<_zR^=UC_#(2FypDv%#D%8MmHyNLc=%0Rq)v}DQcF-@;;UwowL2*W
zZqRG}78qtfX3V<dDn$G;Gf5_1suXF7tIXt8KuIIXEW8w_iKXz38kZa1gJitcw98p|
z0baKfH=6~lrR07n*^s!)^le<E(s=Am+-(++pOJEy@g7sW$WH1xqI=DPd%z=_dLRer
zezSnJ#tm;d;RB}q5MW6?xCDufroWs#_k*t>@u1>jr2a-OKhiwU#CuTU#|lMLdCd8c
zLW$J7;m3?wpP%`dF(u14yf?u)@wjRG_+P>e^UaArnEoGG-=PjjubR2ipsB}b?msHz
zq~5_hU*a`0mn{}eJqtff;&p`*sb1FphC+U78Eb#b%%y%fZu~;BdE2yCv%buJgA?G=
z$ef!)kUcl&6rk+6IYilWbBMC%<`8Ai&0(Vi8Lu@Fz1BNX?QULcCS`X6jDlhre>1@s
z`I|}0`kQHoL~4M_9c!gno1e;q#)&S4@>3VFVHaAdF({YyHxp(3&80wDfAe^tFY-6n
zf|m6+vt=7n9)g?_XR7)prG8Jludq^V=f>2Xly9X%Q&J50Nen8K{g^Rx;+u<X%X1X1
zIdv}4xe857T}|{Qg{G%IgK-iUDl{Wi!rpR;m7*nDQY#U6mbg@**{LM$a+yM{sZ*JA
zjg_JWv;Jn5YfCjS=a7|RZ)rzM72v<?oQ;-+-%GA(BiG@8@aViuTy5DTXZ+3Nllho2
zGbdT@WL#)RsP;D>MIuM*S2S^$zj-;*GXCc409=PzGaoaiu`(Ys7N9?7EI@zESb+YR
zu>k!sV@^Mr-2j|8GaoaSZ2Duym=la7tx$`}?_d1Qg-Fc!oA(27oyinj`<t1R@iz<5
z{$_$Ce^%p9EE5=+j~VxqNJiIb;xK>n<w(o;n|}!4I-D+&{Q0@gKkQ@14>P~^H@_+Q
zm!QFt{P|4hALeg<hxzrnIifxf3$8|6i<s~?kHK~3+#C`nY`YR}j*sjpO_yF~Mt7iV
zn(GQM5vj9sKC+8Rg8#PaM|6;UWY<!61iY&c9Di*43inrwzv&-3G=HGxH8>?&!BRXj
zF(>j6>Z{cWb$<a>KAv0i46bfKK6GHi%yVMDLB9H}Lhdz$`h=zyII)kj)E=XOWp`+5
zp%V$qbwjg*jsm;8lxBndh&2{3<0l!-?y^gjW*ybvr)KxqK0A{&v{Gqyuhy(@B2Njj
zLx<04O3&|UJ^Mw^wWvV!e9VrlM-{a?A=DG@ThXNQj8M;?+p))xFC(u|+cfn#JN8PJ
z+NJc|sj0uQwVv>wO_(_Z;ZsV_O{e3Sb<wjNHzd`9DZ51JIZx?TsPzh4Y^>Hqwb*vB
z5KSuW$m#GL)#`-ZTC8$us7bXQTZ4SNwpg2{*4we$v(z4C1qarW)^4^(J)Na?D{2F%
zxGCckllG`LveYg`ZPjIG+qrx?2<z=sHtN*W){Kohuxio7zVM9Y_AJ4<Kw_V%s6pB1
z87s6;hx!=kGgd8$*3dk4FwHa8429b#$`S9It*|F7RrdV3wd)A@rCzg8_FRuD#h!0k
zkw+kJtxgE-*&Fr@2X+^myko_-XY~p#)~KoPTd{v+siDPsHT7dFRtVWcn}q#lou+<f
z4eK|q!(K6AE4%(VmW=;~J~P^)tTS3$=Nu~>C7sGT=U8>h8Xd|y=U6SFwUjlm5hR=s
zl(oK;wU*2et9P|dKdKb#Tx&(PL-Jaku$y(ZAfH(0dg!0kFtm;V8w>R&=nv5|qe|w7
z*_yf`qkk9nAiPe^XDH2`)68g%Xnq79996%Vk?9xJ)90}_YE8oVVULWaYDSo?H5-%}
zVK!KbX6;t&2au^&C+wzKKk|v}bFJ75S=svx;j&tDnQuitB^R9#a?$h3)0#_%6&ni`
zG8T||WrwDATCtWaHS8b0wry9&KAcx-IA+$H(ld6Rf*~oNEa#Vem3`KmMS5P556RwY
z7Vz1MtCMmZ)@^3NE_a4I^oL~CxM=PT?enM^`88y!)d{=VXD#xHeV#O9A7*6_TYjUa
z{>+T!L$qD>er<7B_H8rLn5A|q+wKHaT4;wE=>)Y_CxjB9lSu#Ba%#xM$k?X?_Hk*S
zHf5jolXc*K0Yb~G{(QBND%9~{^QtDy2R_KG*nnBh8fvfF!TxlxS;6NxYp6}x^ANK_
z*>g_g;vU0nH!JusYz?(m9mwp5>g-Nc3E9mxEBL@>4MnTIc^L3vnteiT|Cy)C^Ek7K
z{mXI2+u^3K>g%6)(z0dP-DhUzF&UXhW>(Rp=Uo7m#5xPj$O=3k*Xo4b+Giv3N&B2&
z#?~TV*aCWFqT>kl6f<^zmWp|cPY0_&l{yB@+~2Scoe<X18P1IxHJ24;?#Ed!VgKEt
zsrU#<SUcKh%6B-vw@UZj+@lZDIuc*zZIb5MS{k-aleEs(8DZlzN#kriAZ(i^IdyBR
zd~4krnln{Q`I5HeRI%i5v?0}oh3$GxY8rL?5Os@=Z$utO->B6%YsP7Oh^aX#G}K$M
z-ymDYibCwy#CKzV%M!Z{sbCw3Qo%>LWzeox<E#yZN1)s3<6M5lIIN({n9kZ8H1X5n
z7Cf3ge5zQG>qx8d_F=AL_NKH@!j-wUreD(3QzwVrSM6+>?(-D_Q3cIw*?n7lzLa4r
zX|qfYv%<SXZ}Wa+H9NH6Da}74t35+_a`RYH_X^>O&8>v3Av~%1DQ4a$ggwn;NZmJt
zi<<8wb-xgvpxWjTy&Nj08-P|~x&@JApjNHMq3ODCfEd+%0NJDycg0o!hNkOOMCXK%
z*b}=tOYBg@8cpnt-J2!OQ%1iQJww>uqK)1@>^mInJOA!?IQGI5fn!|zQfB$@URVN8
z=|*BXPQygAU47li^54kvA3DUy^54kv-^lXc$nxLF^54kv-^lVG9I*f4<-adn?PIX*
z7q0fnH{kw_)jpo(lv(W~$1hs#<CA-KwU0Tot9@jWUG4iaz3N7iS$L^e`-mCUE_m2#
zUy_COY9DLKuJ*kTQf9SJ3HM*G_Fa#R+0{PQI&8J?4#4bc-y(R@|39zxvA*nTA0->M
z+V?r@%dGZ2&-(tI)jqaZcD0WvyV^&TUG1ZO!&dv2qK52h-#mE!Gpl_B+0{OtGLT*E
zBg(G!5oK5Vh_b7FY?SP3AJPBQ9+iC&soIz5Ky*Cb<}#~&1Yfk;M_P8ZPid}K`&e6c
zwT~#f+LwcJ+0{Ox>}p>ED7)I15A;Q=eTAT9SNqtq+0{PQmtE~+J7-t>h_b7FMA_9o
zqU>rPQFgVDD7)H6lwIv3%C7d&64}*0qU>rPQFgVD7R;{pk(OQUV{hSVpN0RfvluO_
zcbCvcyX`I^IkVbFKAF`%W|rM0N8&=pFqWb8YTy1Oa<nef#9^y_JeVxA+P4PaKfSwz
z3w!^v+UFuMv)b1L;5ua#T(9;qDYM!qK(F=@B>A%xe`1+ot9=VeB%?K&IBd0V71A=R
zeYXG%+g<XI&OdCm?@s2|t9^3vf|EJ>i<?uV@?ooe+nHal_PvMJOg@jFlpp5AYF`en
zGpl_hOt^*~62o+xSK`baj9GKtjYzJ#?h;8ZVxOS@_SLz-w)O`O)>Om4(1s%7D~Xzs
zucA<`PN-`JRXzz^pNp$O<P)z(+>A7g7197g$k(vuKgL+YwiQ@}k;;p)#x+SQe?9!J
z>A)nZ`%N8AJ(*R%g#uFbj);j8wHk*t_hI0&=0aWbySn0j4B}O+_*OYcCvhe|sVrXp
zF<4eop1oVkIV^EJ%OvHr_Sx3ZM#*u9cIAm2vr%5;_+I1^%As*qj>(kc0%Q{l{2+D<
zvV}(IHH5f96MqzYJWK3R#4Vcmh%EnwCA$^z23SGZZjODHE!m}X->8YdjD@A(JDt)?
z-MiHxLIXI=OpJaRbzdQrQl)!u(+vXa6zpl*AaJIF-BXt=2bY65U1Awnwb!CV*jFYU
zcQfiZF`=l-jOMe3fE!$To*c0?P0}Qd+z>7p^i0Eo>ZI_<x8=&xjk{VJrNz=SV;?}=
z+Swt_T3TBCEhLLcTD8`_m~eFfJ-g0~;Q{n53(>EwWzoB#i9K_d0Q%l~deA=Hp7Ef)
ze=Nok?6nr1>RR0NKDhxNwC}+89Es;nLAtFDQgPHlDvmnD#fi#!Dvml0#!;uiIO;SQ
zN1X=asMBCjj)%WE>eLsDAq_Zyg^aE60G7qP4i8}AbwnS)(gKjf16ZEJg&Q8gawD(#
zT^{$g0;c0oIQ;wpe=+8_jd;|(DHcJ4c&}r=a&LB7m*H*1k9&LM9{h6*>&a0-ci1du
zUBv5qiob;Ggp=z`KvC%R2;$F@ytW=44c@6D3^60G91kglvB}YIkpJc2ADdFZYr|i7
znh|S~x*TsJa>bfFRvh(iuObKt65hUOkXTbOf$uLIG-6XdI4toPl<Vw?|IsP<xeI@y
z3+j6v*Ojpu(MB|kXW}O|GsePD4(m9vJp?%3g(-kp0-|06#hNW3;jM&EG`6Pz-<uQw
z>?I)Ziebap-U14}QwdrHlz4ZL^*#d9#;A2z4U3wwgQI6shMPz`B+hHY<Lnq~j}ffS
ze-oWBHaAWU3^V^g8g0HH4320iQZJ<VY@>2x)b@vQev=tHF8VZ?iXo5B=e6N|P9YcO
zP)o<FK*(O~gxD`YiF%YIwy2D@xEKZ_zv%Dr!@rPmuJal|L0&7WkH*f7=AwxA40?EM
z#VB4I-uUkUtW@m5gq<gEB06Pn?2plfFqXft--x}IFPZ&?%Z%9Ts!{!gD~;G2avk;d
zqpokpz!z<LKe|@zEdfb?;i8j`*q=td4k>)^ZL0FNlqvLT+4O&j(-I|K^SJ;Yls<<}
zmiDHg>&5<BY9RWn(z}~2@o{b?K#h0i`2c^9?FG=_FFbRR5&KkFHv&M+&qT}?0Lb}I
zsb_X@D4X9jN6kT@*5DIV7qiS!9YFhyUf2f~xV2EcIl)acK#Q7Eu06PeQpC*orBG^K
z@IEG`Si;Od7bfWlPHhJA&BQ2h>kL-1hI}*0LDm(t!g#R)Q@Tr!kz%{C&=~olwqwfq
zBfU1)p^rXEQejsU)OBLNv!b*@a3f;TVlP`Fj1jD7yT4|6_d;wZc%1$0H7g*B21l^^
z*Q_$4M8Gxj*c(=q{Qcmk9C>eA(R(pj2El&F5qn$lYzzjc1O3@bJqcQKFpXlrqi8L`
zu`KtV75_D8vjg`>K<`^JvRi`~q>X)`a?T0TEcc<JwFTSopc(tC6>LYj_TY3V8v9t~
zoENNNga6%%QT>kK8LZL7N^JKs<m@bB|Bt2Z0(SW}v*>hIKhDl)mu@$UPGZRkcH$l6
z-EI}}b62rC+dl*9ykZso3Yx|m?D*e7-C>~*v)hW@{|ZA6v%A31?hOzk$%I^ID}Gbg
zfC>B9u<T6I&6ER@uw>WE=0WK?B*>J@9wnpBQn*KB%;0y70__-cYypPc*d(J2W7w#A
zJ8}dv)=w};5g0)MRa>OGpcCvQI?<F?kD@Lroa>PB*jvyAlCg8l=zC;xEeFXeGoQc+
zehI6^&Q&NUIGJ<dm(2V{ASH|_|9y^Zp{T`prm)-qrVHL@yMAsJa!N9S=@i+p^VwQX
z(7~2O#49sKgF5E4>@l2~D}y0QY1?_UY+G<Kd!u7FtORNgULu!>J@yBvu_GAZG?4@6
z2FmpWE_<=7P+zc^<)R7=1f!@z%=Rl$->Tph_OZC_Hv?S|{FPI#r|Mf5?BpbvP~~n2
zj$wUpZ?T3A!CO>4snESaE^EkBXk+j;HS!hO6x_hkHp-S!^RyA2K*dm*7^z5MRxa38
zc#g(njN+ZKl<l5|grJx6e34yDU<3@Wjg7Sn&jA`VWcKByuqid7v^4vFh)Z_HKCx^L
z)lyCdv3%QOOO^hPq88g8YgBb_(uE3*vh_&Jb(m7l(JGx23D4p>*WtamoWn+U<PRkI
zRs2S!gK}h149iG=gT3NTTNtFTBtW3tSJ2eaPcTC0E*obg$Kzi`3Fer1StXMy9*6zo
z<)hj7){|%%uePuQ*W(WX(c;N>-o!EeOz2|5fyW?WatS*}u5%tz$}h#w7*30Z6`p{1
z4N~&-33!hHc;N|nyf(b>1Uv!<OjtgiNbH3>4v62yGh<@!TqYXcPjEj<wB~V?NAYyE
z0B9fk36QLJ+Hp_bV=UZBMxJ*l?kwh^(XRkVd2_CxEpHy?OL_18b5LYn>_g;Acq`5a
zm>-K_n)1DAxObU{$7%oquL*Yz^N84i0EOP<R)CJ!$p9tZKlcJSGIkk2+B@kAfTLo!
z15_G$UxzpetY2>gbHC@L6*vGi!E2~MLHAEQ0^oRmB{(2KQ*$<85J;{gc3wfsfi_i;
zS?XO}jFF$roTod$6CmX}TXasUAUTov51mL=RPo`rsyw6$cPh6Vca)x_$y8U7DXFga
zP)%kOyCU-n1uw$CG6q`ZI(<454Ks{~^p9L;2&omHbRy?GpGg%j^LoB7U5mRXl5?f=
zS=GpxJWQ^WFW}nZ?uq35LQZ~G5_U@-Q7E1AFCaR~pNdEL6ETfi7lLu}Xqg2oc&=jJ
z5yHQM=PKqMThxov6+BllZ(%;W$ynK8;bVuzO$l@W?y&H&!-BOM0e4vV*kM6ooq#(m
zeC)7z9kgh`&*=J>s+{qFE*Bp=EXc$QxWmH74vX&rC5<SV@iH8#f*;qo+=y_8g^wK;
ztw@W|=jvmJ1#1~AJ1l(cu&BfY7jTD#j~y0DIQm?D?66S6afgME9Tr=_BN}jrg^wK;
ztTk>#xWmH74vXIbj+Gr2K6Y5FB~R|K@Ug=}nke873m-cy6i@E3@Ug>!C>n5wg^wK;
zM2UbqEc}O6eSQ!W0zIN6%Qqr#LUtcJET$mSSn;{~*kR#d0uShO^|8Z3)yEwcK6Y5B
z`rbhXA3H4As?mTuEPU*+AW8(itQ|Wni2Q&%EPU*+pnic7;SLKQJ1oA-`ecWNA6WkR
ztdCzN_D5R*ff39`5Ajo$+~u6$DJ1!06p98MD}JFuiNI&m7b)ZiOUPxc6|hl)fae1F
zI2VX0g>KJ?qg;nNL^^4*63b@NSn;{~@VWAgk$@-q_(xhP0wcJamhQAtO7q)U_c4kV
z4em!_e}R=!nh#Jp?66>Me!v|TK6Y3T<p<nh;bVsdk7N&mM~S)>DhzICeJ5Heew4K&
z_!dTxe~Oiw1C$PUgY-{RwO0m>n05VrD|IkvHNjTazRXIoCp84zVc}zk1?!s>aEFDD
z9Tx0?jRAL9_}F1VG$r5;3m-cyh?;`G)6)3f0uka&!P&<S3!>(LJ1l(cuppWiaEFDD
z9Tr5>gU{F|*kM65Bj64TA3H2)iI#vnEPU*+AetR;hlP(F7DTN9cUbt?VL|K83HU`o
z|8hlZ3%J9=#|{hjmUgt1kN>$2&*RB;I1Y0i+9=oIfQWF1g^wK;B&Qub4)~8-#jGR!
zB$a>4DrV*=%gOs<3k05Jq-6rYmx))B$kDnU7c$@rjP#>4#<N!OTBN1_fFFOeRs0D4
z=Q_-q?q*YMwTh{9`e(HNOCjJ63;(wv_zJ=H5O9Zu|8fYp!@_^XD!vIh(g#ubH>~2P
z$?f;F=UZVm?y&IRwu(OkB}ywCj8Rod4L&!G^tDuWhgCciiRoXmpS@=l_W<NN^C&od
zuKrGyl+I)3zl4B3SO0wlqAbBff<^hjNS{LMe_$04AuUQqk7#1VNH1l{53S<6k(QR(
z;1jEO8$hnZ=_1OXcXfW4nJ4=ApIXIqpQh<^^$oi?ivFAH@F^q8pE5vgdHQmF(=JXT
zEzLrH#8&FR0vojHoSz%X7UtlIKK>ZHn1p!Es0p!aap6sY2BWHSd2M*F;Ad2IF2_Te
z_aa8zs2Txj?|RfVs#a#GO7)z#0VPC|Qp4hl{HQv60g|Fje?rq@M#aVC*);Y6B;_r~
zbIykRZ~A9rg7BWjBT)Xg1DPzn`>q987w~TBc(0OjUBKH})Vqe@dI1UV*LX(D|Be9P
z+d|3>0s?OiSmxg>3<|xk&jYx{W-l!9u4A^_Z1(K5_xaHPcL=ET)|1;^!KEl#<NW}#
z<=-u!*N7gCx|uE-?rn^x#MT04xyRl@RdT^-OF^^$I0*7wR4_fCPd$cr2AZj0M#<O6
z)v!)N?FB9Nw^{xGjN{<wF&)TdRbjjb$Ev&jTj+ej!W8?e)yC@+<*_u^iD1T^Q1LsI
z9la#UIovuJ*Qqf@@~}`+gzL0CETq?6f`^hf%~U^lR6K^}C|nZ%CGu8W1z`(MSJ#K3
zLl!Po*Co8}SJ&5IgcY8dFBbX?{b9^|mORN-+=Yp?$j@5?F>)Q&U-1ff7JVwRRQww1
z7Ja62PDb}D`b<1$6{BJ4qR&dEP?US{Q}nsY^CqepyCJoh=`TS2vA4;id6bMlLKR|b
z)2R3pL>PPLm^YA=w;Y+B;-Yvd#PwcBg~elwcuj#U{I5Er-zY9EWK!NGH^6ko<AQUU
z*F<kG9v>giydK9xaisvqJNp8F32}-S_1;D&FRl^*2OMUN;%WiDVUb;Njm`0&=Rmz^
zNoDjAvc8+$swzhF8r}zxvZPvo=|xd#NsZ5jbd0>;Lf__+eWPb$&XV_pk~smd4Q~LW
zsbv3LD(-lPgHOo;xhxd*CScf?94M58$ItVYv<b!ca#+zpxwKy3pMKJSQF3s>KVZc|
z?`G&wa!76&Gk90*kKgtJc966ehXf^u3WG`+AtiGK)cA{+EHz4wEjqFg_d)Lt7`$Zh
zm}3DNVOJ_y%^Eh9z7%B@-m&P?rN14;YxU|<x;?&iEQN2olP`gZj{u_HvM&StAu+m`
z?;%g3vzPucQ3v3Am%=cmuSvGRi$U$u*AsI<DfC`KWu<Q>766oZPr*8+f071Bd)Gj!
z(zgXvdXpeq>7PZ%8t)`DXXy@cOgDJ_XtdIIgwp6W!4#$M3TXDuC4=__w0Jq_%B4F6
z%=Q++%B6o1(CR&m<}7_*>@vq+vUrhE`oXA6Ftpmd1JU0~Kg_)w%B}Mjk@a8YY3>GZ
zDjKl#BLVBZ9pv^85obd%3gfMGw3)XJ3f&pZM+20m%+yk#dxJ@6>C#fuW6yaYSVEgr
znjTMi+8BI~!d5BTLuiC^V2ZI7Aa#~urwH3A;4YA|rRHd9hTv-64f@SIGIN4bR9kk2
zLXlt))s`(Y^L`6jPVi4mDP_ye!tv#3B(OHXEZ4aNhPOUPBbA(8#9mop!H^|46||s@
zE7q__tXJ3D*d=dP*H?m7$t`l7cOc|Xlov*y13P)2EgviW*6_HlQeK=(#T*~o2FgoP
z%*494O5N8H@#h`<$*@nNPS~`3LecM#RIwawQeN%L6tV#Ilus&R$%@fvk@CsvdNX=s
zd84|<foVqh6m|VwjDzwfb^R{$OjXx$%!=jB>UtBDET5*XZ$fu0pRTS;VAS#%>bjgf
zTjV;AXVG<(E{bkISMUbeWqU+D!#fCEOHT@i@>yV8da_WWp3fe4ihzU{z;LC#0(_4*
zm(s<#WEObiFtwDPDwINRBeR_*pv0TW5!5Fj?LELAw?sgt#|V$o(*@Lc@3PXR0vfz;
zQ=EPQjov@m!_E-U>^;SCvP?jWSIlh71<dw-03($S2x#^8XFX>MnB#rGY%2t`d4FLK
zT`8d5JB)%33YdpxWhb=0#k6w@e+0GAy)c5J968V8Z=6vvo}=tse-n_nu-?Rlw7jie
z+&P2j_i@tXZJsm97<PB%mu`WkVEw5kb8Z<UGit6=jB6>wX=O}4`hXNf_C_R>bAAz5
zj;`Ziou5N<41bXIO#B=B60BBOb^s3j0tzg2yRtU3pr3UIZ5&wbX5#lCIl<S_KxK!T
zd6X*}90OyO%~dE7JjR@dnYpx#AFM$iE1Pc?vK}rVb>n}{-2FR@(t1<mOdmtzO*G{p
zAWHUJY77mOu7x_K1E&8m($fXfLZ;8#T>2e$rSnV~Dd{Dst8{e;e#7R%H)kZ<PuXQ}
zFx9}l6TN3%*|=zLDLOOX8_FuAAq_7Fl(O*x9PeP*y{u9|)O!_1DVrc5;T52svMK?-
zw+MolRSO8bi&0NmjetV$I7nSqE1<-iiqTM3Cm`*;%1Y}6RC;qcbu|d6@fMK5L;(%n
z(Uf44fJU#G2AwRR+50NXGzw_(xbR#yMZj$Dn=I2Lpw+v8vP~5*$NLJ!X%^7tB{`Q)
z6VPr{{Dr({799nX=j{(0%r2WB-M<XhxdG-aJ6^IG-e#6rD0g7Tdyo=z3y6A86PzF*
z;cX>YB*6E$RkZ9x0fBc6`bn9ZI0`-PX)HTQC?($EXsoi61*E-q(ZFSD;;8g?V%(Ie
ziKE8*E4eL}Y`AMv=u_n$)ac#JyTK~C2Q~YPPwqF$z9P5l7Q^bojjQac!uilA*BL;Y
zSNxtfy4t6P6<cV$wQ6>Mkk>y>O8RwF_Td8do{GI#?IUtM_FUvCEGssnAE9(`2YHv6
zDFSqCN>pkl_$1;4Z*g>#DHIL9N0c_>K5jyZ;8d0yXL@}2_k$PNOcm<h$I)>$xXD;%
z<}oK=1S&5qhCV3i^VulX=2%u5<%pV!Y%)~vI=Y3Hd_&y`g~ws!!5=U_694ipxDTHC
z^uEz=r_sQCr%KOB3Ef)_J=6P-eyjrGdvWy9^Z{dj4iNQDLGMi;B9BW6?=c9SK2$n|
z?_Gs~k)A7t54^9S<<f@<DD)18rPA{Rlz1gjF+D%`ScsAK#^8>cK3qVBcO$_O0xG>W
zf{t9eFsi)6nE6Nn)!rXqzx0CC9uTL-yPvEVloPahk5jf|bGfG5>kXl4)4ifkpSO(+
z77OV2UPa@iPZcoWy^m&1pC+say|1CE(|rQY^42ih5&>s>x6%fukL82mD(@|F8<44f
zwUOqI&9WUhpe0Siw!*OKDQuT_R8o2i`oOpY%>vHEd3Sslui_QO(L=_CCa)+h;59rm
zrwtetWw~r)$79$;MY%kQMLq8bfOPmIJPx%~j1%B{tI=i^6_PFRu7Ig3#tXMXZxiIL
zs1#7*9f;Pfm>~8~L&T@SBJVUvJ$w97(F$13<EQ_|cgkqOK`jKw2ynb_U=A3+KtR+x
z(E>PDK*HOE1{&WLw*9`SZv1fq0`C^E9<Qc~LT?468oy8|CEfxw(D-fvY409LHU0zv
zmELz*&msXe-ixf~L;($6HJV|3PdK<wz#K6CB%w5Wbp+}eqs6FLOL=;W=EIm3Lojva
zVfkY5TiKP<)8Y?P(VxT8=^4^P@b1Cx(jvg|ZbOmuOaW1^8Um#E5RmZV?8>tQ_}*TS
zGd){C;H^U|rT5Hd`xScopx34MlHOb5O=Gsb1(X?O7k-;Pg94Ntw~m)j<Fa=7(ld<o
zpxl+LIy@sxm{a>_r00DfJ)mU5^5}u%AuyLpCY(7gyVNmZMFn4$q8=X@C#)RDTnTT8
zV6Z|a5$|sVXN{WzT?4O@oX;M|`)HwI{hp*F3ywgcT;~}4rY0a)FD}OL2Z=93go=w<
z=yIvm`oqx}fgS!?=+e0ky%Ke^F?Rd?s&D%Ls0<~nT345qu<H7HwHR|NOWsg_5f~@D
zUv>iAC;)d#%>PyE1q5CL*j3#kpwPQw0l<cdtf$2LGby(VNP9Psa#tNGmEM(PaF2i*
zZwKqSukLKr)8O4p@V$CkqS5;SEB(G?YxY(X{IHlyF)iL3M*%!2V5V2XdVX9&*0Vi+
z0jlbeG(oGknqX5c!5puP*&Y+n=4~Z-qGSmu?cQ>-eyW75JG_S}=+nabNN*eKd8UpA
z>GU2Tx6MN7@;X@N7Xps+;sjd+9Pjl|g<nPJgy=TvY3-^P#;<{Pe!QgmXR$IgnfO_%
zpB=~6!t>^>$Wy)9c0q|Js(%qX78hR0SR`(#kaqPdAXN2p<ERMYQy@q6^W!KkmfWgP
zUG=Z*I+V%#Da!aYE&gp}aOamW!>V8%9B)(zpn`QAuM62~RIpCe`wD>y)=3x^In?ZB
zodO2dtteAFqwFW-%<GM{het203j0iLM`^at)E-%yUBIh7s+76Z0$%OWrS}2&vSwG?
zS^7LcAgg(`$CQ4nnj`NZ$XUCf)B-5+y0Feydu-_dK-xQd6+l<%-T;+e?E-+~@YV?d
zz1VjEjxXgHY4Cnr1h7y*qqjdncj-=)Y4*-O9N>h~X8;~BtV5w&?LK3NAOaR`@te8>
zKl~dbKU4vf?^E{!ijjA}yoV+4<IKytD81x0tY$LXKkxUF;WeFsN+@Q`KIU^wD(X4i
zvYEdvFNqAfPJmxwI5Cr7u4V#)JXJEW5px~#v6is#!Fh*B`h5IKVH#;zWxLmS9}69t
zw^|BaqzlpJ*+PcJH<Q}AdACTeJ9REvESqcC`-U}x`RC>RTJmq#`Dt#IpIy|5Qg%2E
z)x(Ty<dtB6Y_FT-Ux_s7{B?~5w6ozog}z_cl*?ipy*tpe>!u2L$m9G|*DPR@cK{gF
zO%w2hw~A$^3wYYQfMAAz&EDxO(;{Gt_bIu}6!3zVvjAWZ0ox3V^3=_;DdH#>3=Fe=
zx_@JBC|v!_P`H=Dp?-D&ExS?VsozuFybpOhNZCs$o4hA6OVsZz;0bRLSl71-c-s3L
zYOUW#z-I3-mf2Up7Vi;e+fTp?-e+VmN5D33f9O!Zzku!DH3SC;c*T2)3=S0Vn)ee@
z+627iT}y5U3E1KFGuy!ec6!YOhY0x4I|QoMw+r}K%u|1;fKLsJR;ZtAuY*M@z6#dX
zAtu#sxE!3VxhB2C5j*{a6OD2L+YVF7gQ{yxyc;F0!_3V{ir7!T7>Q1NP^Iuj7qPcL
z<3t<&N{;hPHh;w42`&wbF!fpUP2Phd_Le7+G69cX*5P4F>r+U1fu)Wx*)9?LUZhMq
zn<>3H#-JH(u+VDjHr3&*k#@jdR94YUVNZ{6W~``V*3%=*&~Tedm$5W7&@dIP0+NFL
zjkD_!(*zbR(3i<a0$W49Qx1~<eMpURM&1HW;d|_)L&@Q|oTm}K%2MXK9OP}{LV$JL
zIF5Sk%%8dlX|IG)(^hxHXzqkaX0J>L418^tlB|82#3S@hWIO^&R{XOa8BYylf}K7J
zbvX;_Y_glNZ3V#r49u8u%0sw5wnQQ}T3$jfgtgd4(nG2-?iKv1!>Y|L%-^W0;cPSd
zA^tyfGh%I3e66kGYi$)@YpeKLTgBJfD!$fM@wK*!uSHz0d~H$1*V-z+)?s|DGcA|n
z*<pNbq#=16uNhw(Sti#KUz>vu95#TE<3w(;pTvd4*G4uZuHiM~Ya_Q6Fx`l@;pavC
z#h9P*wUL`*f5)Z7*G6vUtrB1(ej>L=Zo)sua2Q`3xx;2L=OSL;Q@jk<jIS+1?|@zs
zU(0KU@wINMs0VZvU+YeeUIv1Mg}PG;crEd@Zj;od;%nU|j}@!<TDK`6Q1P{HQ!#<W
z*Sb@^Ar$8eAOlmyOY~h_h%Tt_bzE1vGoqE~!4hBV&WtI2ULOOg_7I@rYu#A_RD7*F
zTY!qMb@vpY;%nW#1gQ90cW(hIzSeCOpyF%YeFUU+e64$MbTMUMe64#(oYyM8)@_dw
zsQ6lUZk(@iVSKGSUl8MK8JKw%vWZ@q_*(b4=tE@6m^=6Qd|s>gT6bX%wN&x7?g=q2
z?x^@$cTpK_aWM==e$nUg!@rPmuComwjIVXijB-Up;%nU%qj;_2Yu%NKJ(#fbsQ6m<
zkI^IWzRCDn_qBY<%=lXOb=9bhuXW#$YZYJXz8O0Vg;jj5`<4I|U+ey9)Ju>;#n-xT
zOBoek>;5H9OQ`r-_k+?WBYbvYe69P}(hmVte69O&Zeb3eT^L{M{yjzyzlyJQKNZ$0
zzSjLr#8mOM?mwj-6<_NjzP1I0RD7+A_}Vrg6<_NjzLw&t_*xh7wKTPguXPb$3t<cu
zU+W^i_6(Rr#n-xsuZ=)>6<_NjzLtYb#n-xsuO%16*YY0=jgcQ}JEnj?OozQ!fs`aE
zjIVVOUrQ@Ue65T4TFEEzwJzdo*F$U-UkelvsrXu;G9ndU>mt6E<y3sFi}>30QLvQw
zS{L!Pq^bB?7xA?Zf~MkYUBuUtrs8W|#MeFpnu@P=5ns!Zt>SB4#Md&Xim!DMUrU;b
zuXPb$OAm~SuXPb$%bY5{)<t|R)mQPgF5+v?LrxW6>mt6ET|SJjbrE07E*-|#x`?m+
z1M-IPwJzdoPlCc>e65T4T80ryd@Z}J*!@qDUF<H9vcT?X2$5t0A`$VMx)iDGW5b$>
zNxGT-!8|O=u9wY&(q%}HDVIG;Mjhg7+mN$UW6rFYQeDK?x)^dQzSc#2?e)kZ@wG1E
zYY9|*t&8|tR;A)=UBuT)JEJZtoa>OWim!DMU;9TgVSKHN_*w!LU+W^imPp0dx`?mE
zbCQAhTK@Y0gizGt%`W0=>2#6!S{L!PyltrXS{L!PY%LXE>mt6E8C86(i}+g3%qqUt
zMSLw~R`InsSF_<XAQfNhBEI%^)TrWXUBuUNps4s-7xA@3D!$f5d@YfRuXPb$TZsBp
ze65T4+8Q7gU+W^imi4LlS{L!PET`gYUBuTCsrXtK@wG%MzSc#2Es=_^brD}nq~dE`
z#MhE1;%j-IW7T3L#MctDa>0nNC2rA}@wG1EYZ*)`@wG1EYY9|*t&8~Dr9g<U<s`~W
zVT1TuTAKYo#3egj#Mg4DN_?%0_*%A<#MioruVsy@?gw<COnfa<$~ju4bE20#itAj5
zqq3aCMt9^lC7FS^QT8LQ^h@nwe65T4TFyoiU+W^imitkhCvlUD))uy*dWVWdCywdC
z^*9FGI*f{q?N!o>YZVn6YmG8$L)@ydeUiLZQL(Xo1u!bM8Hp0T7(c?7kX=SE#*ZzU
z%ydRC#uw%@PxQSAPAtX6cq4fgX$<Z4$|{*8p}k)DXttTNd@dgU4wC06iNH+E^EuZ_
z1ZHBs)KOW5r#bVOob`B^!`m^QJP*dh*91O!n#WWzH+I)e*jq9+Qz&dWtXjMbUw>av
zt6=Yhk2;Zg!E^<Cs{aNCo52qL3VbQXu5s`HiHA_U=AA$`({uUYI4E^JnyG7ggQ}~y
z?o|kF&MHvHeGSyVge;vXP{IOp6E_1kXgu+4AUTz^nw%~`HZ%kxe(jpgLg_b*NqT=7
z8BGrNmyx;A81644uqpJEaF3Z#o907U`?y*f(w;mT7PgPumn!1iY&?=;_t~rXRZql|
zF|IM$7->vBY25FhxfM^uxAa1`8hNn}pMWLQ+Nv#_LzcTd4O^%1U8TP8cv8aekavwo
zQp4yon53SPB{JKZIOY;0IW!<1x4A7XeB72eZEJGLO{AzN>BugR<vFf%A8E6#oE$W)
z`#dykjXsWFBON`AbCVgZTZ(^HbovtfbD~Xs_!o`-oE_Vbt|w}Zu09q2RvVhzAy!T^
zx&0H#rt2+6Irm-^kGcchDCNF~^t2H>xeSHu9;?X4c#r=Q8SIlSpYj;-OTpMaMIk5t
z&r^VU6^h0SU`BhfLJ4o5IY$}xsS5e=$>egHLP7kK3ZNwl6~-|*4EuD2O5zcsr3$6v
zaiV^OD&xgOXDCz?PZKRus3HE`IH2VUHO429HlR>*ypHHhg<9g1iB>2yJN_!mtyHKr
z{ua@oLUZEp5}l<`Tl_<!vlVKO|AXiph33T#YP3qBj(83c4(z1OI^zi<9M?(I70)L+
zPoeI3A<=4udg5h7Usk9$UP*MmLVfW%qOT~_A8#bOK%s&7bfOCt8jQE2huRk@w90VU
z<cUdWQ~P4eW|QV#hYW^eUuqSNb1@wqzCT)OjmmGtZ=!WBSICKbX`m|<ipC@4@->AL
zagXRqh5Yz8nR7^?AYM%CT%}N9{Cv``R;VPtPbJV=h0^hpnDgrjRmNvilWP>Ji3iO2
z4TT!wf23a5D%2Rihv=IMHOCX=@-2m0;!jhuZ!0uA{wtz&3bn?!VfE0y-tw!U`kZ(r
zYxs_$b;b+G^9F^w;_tBBjS6+gxl(7}q)<=%aOPaEP;dNE)_$`>eerv!!z~K+#~)?R
zTNN6J&tuLF3Ju1WP?p;iS{1*PwA&S09e;*g?ojB0IKv?9I~BS(&M*f1E``>_8A)N^
zt<aV6UfTK|h1SN~$>m;!u8lJm!oE+Tb#cZ_*!L@RL;L{h_dSKy$FC)NK%ousTPf%F
z6}mJ232XR)LifgZu!bKh^gz6tI&4&EW4wkrA5`d}_z#GFq|m1L9qea6R_KZNk6FV*
z3OyYk#o8ZMXmk8LTJRBtw#3gO?NNnZh;JpAO$u#`-^JR0qR{sE=gj$-La)SsP1+L*
zy%yhtv?mpMEB*nwJf+Z%csp}Gt<cW+VoLTig+7e`jXFG|(8uvtsQa@DeVV+GIe%{X
z)6ugGGkG52FReTV)L~b|)hxM1!PQo>k42wXMe)Un0m5G?=-A1#nfV0;qjvIh%J-sz
z2|M{3IsaNg-%joz+^S$;CzsM(+Y~IclPd{dQn18MzD>@*wfqAhWZE{I(U2~WGZUqj
zDGE`4#LOUgZ-tN2c!rVq8f*NWWpnxnT}QIh8lIrrQB-zX!xMA{uR~7|uM;1Q!V^6_
zLF7M*o}h=pAfG#}BO4M|@H+GaG2O_UgP)({O2n{@0(ycN<`8hFH9SGA%Lq2&2cDpB
zgAneth9`){WT!PeL8sz+v?Kef;rHP!IVJn5;rBTM14+HYOex^CF$Vjp;rAhDC*Zzn
z_<abX0ryqI??aFXxUU+19|C_2_Ep30vy!ZgLT3#A=Xv<~D*i-r)TjMEag+<VuNr<I
z7KSPqgz)<iI05%n!|y{74Y;owejkEFz~@-_eF*%3`>NshAqWEQtA^i)pfKRRYWRH!
zN&@byhTn%EZ4{|})$scqMj1lC53h}Yaq{r{5Ud`{HF)@asDWXQ<-Th8eTd-q$&2Ct
zLSz%Y$_?39dZh`!&y8dn`h9q91l(5*zYlA70`9AZ-)93T(SVY`??YQ$41<wh-bVcJ
zFJxTk(6w2dl6}?i`@9Jha9=h2KD;&p?yH91N7#c2yGly-Rl9$T&P2P7QGOrEJVyC_
zB<~pI_u+Lk;J#}3eGUOg1oxvO!S6$m9K(Ip@cTSUkpk|khTn%}3Ipz|hTn&lC<(Z)
z8h)RL6EJZQ`h9i)R0iBv4Zn|{i#M+z^!wBSG>qZCYWRJ~x)A{Gsn7B$W(xrPQ~#8D
zX2%a@^TY4ch(fJ#?yIKXrxj>FkNc|W_aTotaqg?8--q(G$GNYXexDUE`MfyyRnzZt
zG)&SF=e}zCeLe%NGtPb0^!so~b;VobK=AvJOOH{)e=JlgKh(DL4k%X2bl98cL6wn|
z%dM1^4*fo)$GNYXejmvf=e}zAcD!{+b>iGt4HOVX<J?ybR7RADb6++6J}l?Qe+tg@
z`>cZ%gE;q9)9*uCW1Rb{>G!!0wB|VXRnzZ7T1%Y!s_FOP2Z(3Kxv!djACBzSIQLc4
z@57vP;%SzH--ooeIQLc4@AEXuwa2-yntmVVoEPW5YWjVsUPqk!s_FMxiJYBD?yIKX
zhh4tSOmbf}{XXo{?Pikus_FN633<0$N$#tr-{&|e{EC(Q6}Z#y!wqim`xH9&fgXCQ
z%XnSrup>)L`~h%SO9-TN$g>foGA0ztUYU~fVRH7mVcD6a8}5DN6qf9a**qwnLV`@W
z>|-(xErsW4jCRtVAja&)WT!PfLDwKhTt+`UK?Fv;0QJxlL@Ay4P9k`Mq~%c;O;G5N
zaZGkv(-ZVtGSQwO0=#>0ri3SmC?|e0XGeH~jt41W<niC1K?p@H7f%ph?&92OO-~SS
zGe&$mZaVY?vHhHQ2ix|4vG?Y2a#U6OcvW?EbyaosbWL|n(n%)CB$*}4OwyTTvJsLA
z1c;Cg7)XFX1~R|^0}L=gfGCI{i-<%~Sq6#9E(pqw=!+5-F|x~|Am|Gc0w{tgNPyq-
zoLjf2I|c+_Uw_}v_sbvCQ%~J{&pmgo>eJ^r7nUGqbbT_dX$j(9UGI}=O-m4UUf`2y
zO-s;sffo8?TGJB5`Q71@X-!KImrj>YrZp`=L_I#4*0cl>_4#C4(-IV-zBT^yJ`gNH
zbwH>2WLnb_#QOSuGOcL|V!3rbnbx!f5nbhzX-!KI(G7lvHNX-?beq44ErKP8=q{g3
zYg&RR^L{+J(Ii$aois#YRxTL7&N98I@nB=5Sb~<}hEJw7EkOi^Po_03K?eh^HnQBW
zcqw9rs}}^Wh#1$2C5Vf66t@Rjf;dv6o~5d=1hGa{H)AtNp@K2`GTbcKyfcRDS0*QJ
z+=}ah&2>743rSDp=j8T-_{?%1y@d-AWEu5jTGJB5{i&WzYg&T#1rYX%yKL}$)YL#q
zig$Pwr$s%fCqAer_=m>f&Rh&>BU~-<uOYVC@Kyuq*s$5Kcd-fL&X~jTF`WCOVUZ#m
zEEc1IP-KH8ay{Y%WD$yNu&dY&gd!X4USMtZH;|Z66j{7Vl_;{oGMT<Y+Rn_W{Uve@
z64G|2-F*unqSs$$UKOv6h@|bzb^_oUZ~qiG8%VCL+C8N8p@HV9s(pr>#%r3Vs#fNh
z#}jgGmdBT2y7@bz6<LsLsjuN5j@D#Bu4UV7Kf=&uL9RU;X|7LlZ5HHO=Jb7X>#{t)
z3_{ZWaLkP?$hBVusxq?7!pnGY1b;{4kvu&N*?D{!?gb>*W<joHEuN5Tvpl{GCOV(w
z+APSmN;#5ivmn<h<w&m0^7t~yaD9?%vpl{G$Va4ZLLOfR=n1(t%j3%^ljPbg$h9(j
zKFPINkZYApl54Xd*Alrt$+cOKYl#A%<k~FAwX84nNv_R;TuaSzMnH0HmdBT&22aSf
zSsq`;`be(Lf?TWWBb_b_a;>WGHH>E#<XX-L*C)9azZMD#e3EOkAlEW2^hvJG^7t~`
zjf{Zg+ANPRV|_xd%|=$ZKN{ncT$=^CmcZ~yuFZm6doYmg--}yWkZXxtpFh}VL9QhV
ze3EOkAlDLwKFPINkZU<8kxz1M7UWu@L6~c=quPQk{X%kW7UWvq@`PNQ?XbdXY$QI(
zwONpB2@Id)+APSms^!<PZjfu4=K3VpW<joHTLYiu+APSmtS$6OuFZm6OO*3TuFdlJ
zGL(yal54Xd*Af+cl54Xd*A54&^)G@IHVbksnN)T1BW4!lTGn3g7oltx<l1pa8|#x?
zn+3U+BirngT$=^Cmi0~aNv_R;T+4AT`Xtw8L9Qj5?5`#Qxt6HaC%HBYaxKvmpXAys
z$hAaMeUfXlAlDML`6Sn7L9Qj5=D)`=0lAiFx=(U#7UWv?#0;P0+APSmM6-R8YqKEN
z61Dpz*JgQq8QL)4C%HBYaxK#q_$1e6d3+gKv=Ae8Gwv2_asdlA*I~hC9~Epah=AnU
zERQckay`klS&(Zfr=H~6EXcLYoMpL#a3O1Y8>9XS76Z9<PbPA;enBVZje3%6vmn<V
zgM0PAV@{B3F99gn%v#^cp#r&<jjkuTHVbmC0FrC7AlC{Yxi$-OtpJj1vmn<BAh|XR
zaxJ%?dXj6iAlGtRuKz9j6XaUSwunOnaxDY%W!VekkhSRt$nt?{)RSDB1-Z6>oAo5u
zW<jpq9-v@PqT(diW<jpyt$LDcvmn<B5ON*JwFFsyoPs~;naHRoxi$-OEss0TQV@O8
zB{6B#A4xGF*M1rI>SZ?ox%O6og3awB%a32`{OIN**#eMjf6V+O*JeSkeM$0@Hj(AW
zdpbXQp5)pr$hEIAKgqROkZYy+r=$5zm{6k02gZoOxUMI;HVbks6Y^uj29HxNnv52N
zjTv4W(ewBSn=)JvBO;P(!?6PDB9d#vak4`p;s#$U&Oix~ACqgt@rjwZmF0bY{ggD%
zXgHHHTZeuPw;JdeP<^<ch5QDxKC6#V*Gte-)kmspvOcSO)%7<p^wr1aI4SG-TaXXd
z=QWVmK-On2%-UGM1)Gof2C_bLo8@ueK-OpOJ(Y73`X%?Ce6Me)LA|;6<n_4WdWgw=
zpz@IQnZIh#QIt&9XZ~t=1ISYF5vW3%Vj2xELxudcgZINN@xF~Z!W9rXHVmU>-aWV*
zU9but%L87+8S)5x>?OdCesUPV-s#mya3i|EB1jZLfCljYxR4oEjQe5%^^L8oi~79f
zLvTkV9xGX6iN^_uB_1D3TzfF`u2vGG^Y;fhK|mPojW3MRiRs;_QPg!1K2H)bD6&@q
ztdVR5rP5~w)EeX59wdEk>QhjrE_N%9E({+Vio0}tj{3**{lbVCBPROR1b#npqbrvI
ztee2b2NB(hqwfd^Bf1qwmkEd>x)n!P2q;8!D~_&eSq)*e5#5TTYXsCqbSsXo8_$&b
zh;GHv^#aC5bSsYFR*ZU@Bf1qwH%{PYUsR2_S+Y%y=vExvI&206%!ue#9NjKpW<<B*
z=ts2_Jv*XXarBcqg7%1R#nD~k2<At0D~^69U_nH;;%I&CH<7Y1qFZrvZ|w|#j)-o>
z(fuNNkBDx?(F5bzA<HAW6-OH+Wkp1{;^;vE`$j&&!vgk;=vEv(mgFq&M94-~^!S(q
zhhQEIIuAbyMK!C!NyG4;KLyrw<#>%jJQCo*d>eor9fHxXIY@vTt-|Qn9Gp|baOS=M
z-PNm6B*aXkm9JoP9IfU<k#b1ld0bCWKS$O4+W8j5H9rk$*yfDpC72-S6{Gonxl?B}
zzkLYrghul$OmvL7(fqLFv5n>~)C93c^RaRV5B>OeshWc6{1kHCVcjrpEKSYF+zL`Z
zL-kfE%ShAVxh?KceCtD&KX&4MH}x|J8pzUUIv%VY&8K6X3`WhV(+|L#f9lQyu`QJ3
zw3yCBW;z3XAekOTCNI^}McuSMQ%z@gW;z%89I{s%>`V}8q>e!&%~GaqP3KZ%O8x9`
zrcFUDX6nz#VWk`tOQaU#+D?r|YBIGg7P^yq4wZPR|3b}v>gQNz*^;b<rt>0YjYG+7
z>ILMkN`Z5VCa%ON2C0Y9ndwvq`o&KTg<LN+3H|J*W+9JLlCqcSOdk#@mmw{inui*y
zQqM!LOln(^auMXFQ#+ww{nX>g<E1u17dQ19<R()V@+4A6;d-D;4>g?wDe+$Px|jML
zB)X{sP%@Re8Tp*losgI;)xX+wKF{3W>SXQ_`yzKK?Q^Dc3DYcS3>_-Q<TTT{hiOlu
zud=CQ@L82Q9yMlC-@)Jn2-F3YqngXjaLownUXOWsg&A?m8vb6mRdb~oar?6Uxubxt
zQpoYw5#hA78Ax;e-!kVl3VHrtP-6{FPGg$yuNnh%twL%4;gLYsDHQmtnT9VO%$f1m
zj0VCN527l6ZXFQ5co1d%U8&g*6bg-CeJ9`#%>*0gy|*u#Qgf3T{)}xH#Tsrl^L&69
z{(h8si$b=48D-w8+Ta?&TFkwg+swpSDCa$lo^WgKFvGu7%0+AgzM`;p!yn3WcdCA|
zjo>o$am|m-#6v9Cf`P8B`7bkEjf(yI*rL01xk=RJXK^|Imy~k1LaslRIoB%`_`5Le
zUWG#cdk|c6pF)xU2BqAuP{9Zato;Eqk-}|n=T2(9!3=L;?H94Nzclm60hDD851KXn
znann7d6SpJWfLpdED?MMeOL34nK&K5I}-&K);wy4i!i!sGCZcLjVHt73dNJ*R|>gm
zGCZLg9jM9hq(T`r8J<$8N==5R70Rl~@N0!aH5q=RP_>#2&nT2rli^u~@@g{tR-s4@
z`15Lr3u?fBr%<gL@ZYNeuTz8if+{y!4eE=k4fSf^UQ%geeHploDy>-!+{+3T)xd31
zXsQ~xR~4F}2JSV5W~+hwqeAU!a9&q~GhYqPpVi<jz|qZIPj8xuM>!5TOsTG#cg*lD
zjsu_bHJeSJz(^l?>>)<Y2WDn9z*7J6RY<d}fYY?Y-wQiHO;Vvf{3Efa)VK=m>0i1Z
zP+Fm7{tj6EHB|~N_b+13YK8Xl^PDy{Ru$*U3V##JHCfpRQ>#<GeI{`!uVqUNd5$wl
zPb#Jbv#^iWjI$DZLu2n+fLu)rB0)i}KNMSB%_LQo;a`hQxu&R)>F<c`sb;c5mfuXJ
zS`|w8<Jr)u3fX?)0H8L7lK%UhK+_a*{8uP*x<V=c6)y1^3c3DTY^^mj74rP2m^Mox
z-`{^F(6$Pt{i9gJ9EAek<C1GvDC4if)?71Bp(_7}?4a!w%KA^S_U#o4{e6h$D^zU+
zgW04VtV9z!$=eGx)YdGtTvEaO@8DL=B9+tdzrfZmwuZ9HO#c|{Of^faq0ES%|EcFv
ztKl)A0$wPFQkaEK4r@9rmv{Y9d_UPk3p<?6+|z1!8cDYQAki{w=yO1>KbKv%+-eN5
zz4C3CgsOr)S3bE3cnzp6s##&V%;EnAQ=(>HEm$<!&uSQiB$~!vM6oOtXv7VfAPFP*
zDZ5~QYb<33$L$YrfHjuY1iP{uS6Snv7%SU%pjg8q<S@Tmy9l?kZ1)K|4b+IW=nwOX
zL5JX0GI84zphnc98Hkt8Rgg^7Z?N6$bx7o2tVY3Z2Wa^KGt9gux<pD|#gbht`MtPg
z14_1h0W;LRHoo&bXciNHj}bN_&*PF?_jA)-hyP}OTLV0)G87nj6S<|rMXY!cT5AsS
zWOZ6=R~PA#Vh+~0&zRVZQ8yEw%guN`WUUZcN0nqHyfI2v-{h|S`wTPbW%&5D)}Clg
z{BP{l<|bG4*l@r09{X{r>?U_og&wcCB|R==qh8gx&uBdv6UKbV6+NE0&vaiGJ>DtF
zddO{zWhp%#bz?n_Gg@C?g|fG*vTxsOx-UrCwnp6_w{B7P_Oh~bFrUmzRoSRi_NY?X
zOWlTwdcR#(_88WCwko^k9)viTdao;$J=?9XD0@y>*|8kM_fyi|4R@LD4K{H9H=Cd{
z*8q}caJt}N(@A$?l>+a=A;RgIlMlh0sT(NNUA&vAmMc51wf4y3Sr|bxq4DD40a#yV
zQsX7XuTklgJD62jYrBeEG;q)xe2L)B;zJx6&z1FvNcF|<adHQU^dq(JQ~V+GXEffs
zI0UQ44Bcwg(vIS#9LQ>|-%>0?uD*gj1)r@~cOmg2)#@954EMnVaR0tzb*nGZt?pne
z`%`f%dy84tdPyp7<?+RfInTeP@sY(Vh%eRnh@$k_w{`jM;v1ai-__{{t5#p0Dz#dA
z<%(3?D=SnhuS)4w8?8@rP`Z`o?w$G|^mnMal<iJURz136(t3OcMAkW6{W#)%@~ZuD
zaO@$v?p3Pp9$j}|QO5i5R6&h*uj=vMl>9miH%g_;Q5tuv9`4h)%V_;OJ7<#8?WWsJ
zx5EPN|N1zs+oV*h(yd$RHYqh%>DHxmD{9@2SGrBny7egCrf#9zbloq<D&1yi+^2Ng
zM$5z6Je~dat|RmO^;=DMy-D3BkJq}r>r7F)bt>K7b=s9~E0k`Vop{U-Qo4QM#ADX2
zbThWlEunQeQt4)Ee7w>vrFA>lXdTC?d$H23>xZU$PLjI)xTM>~&P2URHgn?kJMnz%
zQ@UKLb&30FofD5?w;IFmI`RBDO6hW$#z!k%uGDQi#%R5g%XFpE<(V6B;HdP|UK4ab
zA!>cB%cKLjb*yyeu9o@LSv+Db@cvuq)}?jpRsD3J)~!eB)~$6pOzC!r#)m51dbDnb
z7_GZ-OBkbcD_pO~@U4<=W46$3%z$pPyEJND;<?_Wb&2QtcwKj_%LI*MT_%=vQElB`
zx3$NZ@;ff<H<B{Hg72GdApN$e8HRf7Aa5q)5jcMGp@#VvjgC`&^4DZ(&553WOU84n
z$7uZ>x6y}`+!wCZ2b=#l<W7>j4<#p7?3j-v;~lf7D9_+WlktuixB0Pwx@1RvLhBN@
z`ALlrojU(IJPt6n#W!oA!!yZHZS|Oet(WhQJEtnGF1yBb+hwI+(gLky7dbWArgo7P
zYF9cnxx1P*%h?;JB}@CM%;(cJ?kTS1u6;(bw7<$z;4IyyZZ+S}*8S6^=Fpe5&a2cM
zI#=TZie21~zoPN}M(Yx4{+cc0bioxECmXo`fr(o4*X&8uJhAq+lZ%h?rR7g{tnB>a
znOuCYYmCK5;eWPcWe=OouOQ}|cKmYDUgVb$^DinrvG%`CF7kVb`If%%latvQf79~1
zijVL;<{d3>RZ%+U?>fDw=y8s1w&SUEjCzE=Z<ihxG9f;&<H@sJJwgrLc^&EzY3T{E
zR4uTi?)-(S^IY9oyBJeC*nq{Vvy63kv2cL<TPLYWy|knWC-trx9jzwy?shz>d(@zH
zXubNBUVGT_MC~@F9F3V}j#u>*zh$})%i>uP*VC*eA8$;V&o26TLWZyVVpGo6F#CUr
zoW*U}JC7uW@V!5=_WYBJ`*45yoxX9y=Zep8pM725*znn6jsy6<zOivl@d3)HvSS&i
ztuZG43g3*(D-!Z<dBH_c4GY5TKe(v(!z&W;bEA9GVeG9d67h4RYtkL^I-Xdno+F);
z3~panBs$~gN-@FwS0&>2$0LgSP@Ah0`rVY1<C;Wir<c|Iy+pj4dyR?rv(x%iSM*#6
zhO%^8^<=GCU!wH170vn*`e~~)>q{)D(5x@9GS+O8Ecm{}G3pI_xzhCbEi_%N@rl&*
zge^2Zu}sr1^S$5zrD+6BmrEb+ThjCZ-G_aX_;n9i<38+FQ+Ab>wc40?4fn%6m8=aH
zm_i#f`!6iX+Os4}m0dPaw)Jiq081uM$GP~P;6qmb>Q?la^zIc_oql_ix7n-I7dmV0
zG3sshYK@OBx_6-HHCAbK<lXC9D_)B6l)uiZd`I}c6)%Y{wFItL-!`qaooXMu(TbP$
zO0^Vk(s;k(T+XFiEit<#6HWL&rkeMPRijj1ZcIFZU2~{v-u++3YlL+3`cm@_wI-;%
zeUs$n{7`F#8t~qt!CBs8`D%wpH}Al;v!jx=@f_2AUSx$+bXV<Yjn}fIt9G=eSIAmW
zChLcs=gn50&#79-+90x4mt-|tQ<bc4PNWvysjIoGOw=fTd`;3_*sFGxqVD1zW8$Uk
zqhU(tbzjnir5~~$*%^mfZR%0k$9ihDWVH4QPEcQ!oQjg@4NQzzSyCQnzBOGv&ZH!a
zMWud9azFaJDO2kHvvtYFsVGT<0+OcDpa6ms>wMQNm2AzhS6)^nPeI8AQs>buDU<PK
zbF%7{UiHQ6Wpj?IHGaw4WX6*TUs|u_cdy?nS?!S3F0#H~lJ(n?EVVa3S6222KICpw
zWjCK`y7Ofl8Po<nZf4_dGq)u`gn~(TE4;fJ=`ObDcHN>rj@BI-^%lRzo%Bv~NUfCZ
z!51%H6>OT*Tfabk8&sV$PQi<u3*4WbhB~EOquH#=bxis#pVv+11SVQ*mrh#8N9b6y
zrAF|=NfSGP$C=H;1TUEME+_7Ivt^WEdHHHq4yIgY_p#GkG+v=zktXTdmKP7>6e{Z4
zx{BxT4m?@c)?Mspt6Ft!XeH%M(Y5syU*<$=Gjk0XfMlW(%M?wf^}S%zdX8UJNAmL?
ze72o~;WRhP%sK6IrhAk0`+iV+T5mUwRNLG}^A5guO-DDsAJ3a!V@85~w^52sMX{wa
z)Zaw0nKErQj*ZvlELqc=N=tgi8GQOZDFvVZEWVsc!G}u)pKPiq`1C-*x45s|E(MpP
z;F(fz@N`|{?b^67OTGa7NKf(Ut5#tK#Hi0``wB<yJQ1^Tjp_D^nEfDT+Tm#7+QGbp
zsc7a`xl4a_Vwb?4S+dif@2fd?JUVY1n3M`Oe}`^6o=sXUB3GA0{y>X7p(OHNR()cn
z$TcOAZEHENcNQ@>z$x^8(JX};MYEkJD$RP7X1mN_3YLRv?&7$g`jnzeVyVYK#a|Tg
zBkz1JuW2HCDP(tw?4z~pX;YQ#)icxe$TxlRYNTVcn8{yK%^5|t;(KTEw^Vax40~qs
z2UK%b3=wKR2eD?OLxLe*Ot6%u9dtNsWQ~LQTMwqtY{Qrr(H42`AMmMIiR(~97Ma^0
z02dQ;Z$Eq^w&GYEB(H*rxGj?HW_(zRj%cai99B$0jDvHK-3r<vR*qrgw`Idpv_nfp
z`LGn#FhR;|VovRskRd5Pg^70eMgWICg^77pyfz&A6ehM4V8apiWZX;Hzrd$^J3gQu
zLu$C|ah>3KFZQgV&)_;K=e^jA+?8mDLtg-UamccU!`}$(B_T_@4$phBmwHbkSK#ox
z7kgLlRe;dpc`x>E9vx>Rhv&W6yL&u?t>8>*2k7vY0Mt4>@5SE3>jS8Bc;1V>r}uS$
zdLt?4z1Z8~$PO5X8DGVoAMhF~P|+QNivVng=e^iF2I~OuYq9+>GNh!7{g{i%V_)o@
z5^PDDxgNn^ARlal6qFAX1C11)H|m^hiR8phI=xEqG_+I2<%$xK%nroSt~wK2x<wsG
z9*nypgKbyIEUs&xrjr@ELnTW@kCc5RZe*rmV@lb3=uBTLWfB>LMwOkiPs9Z#4E<cK
zI3CQYK1Q@H!+eQfV4*n8Rl6Z~f}|ejXt~ak)RO|K=VBBOZRd)_W?WR0)Z<(g{F2us
z^*C4OdEdx!A_qv!Gk?N}T<5!9k(o*AaV}3uw>Y;Umvc?>*T`dosD&z=?<H6)!SF85
z^~0`aX@+uf2MytLPYR{So#cL>vgnKMPR{chhx;97xUC}Bc1Y=QTcs;qhm;<-HIiO%
zNa=A~hY^GxC_V0!^i3#^fS`5<{^u6pV?F*vZ`3E09(TICla2aF>2YUzN_SFv+*tx_
zhm;<78v!nQ4`8-{z#*l_-Bv*8kkaGM5fC|~^tf{c6dY1|+;#!A4k<nEJOOn^jiU6p
zJG<vl2l`aGyZF2|98!ARg&x5vgI>x5EcV#~82(A=ad#DDn?{bq-;Zq4u8~HKIx5lK
z*L{vcr6c#t@!D`m>2X&&Y^Cjx(&O&$y@(Xo5ls#l!M->X9Y%S%xA4KgSa8aI7hrHw
zC_V16ZasDnhm;=oxN2S-4k<nE@k%^|aH1rI(&PTOdz{08>^0mMa+28trN@0y4XOu9
zkNXF?b{$fBKo^>i!hu6dkGoMol}AdC`*QVWXc0Q3^thX(Ou-?g$NjU<o~U(5>2cp2
zz7fr<b4clN-x?lZTdj9U>2crA6amIM$DRuC4vwjWpNL0FkGok!7XhH=d!ptH0O<L?
z)HA!Vh{F#`&r%d>FObsXg3{9owEYlLdR$O?sNVbnDLpPIJ?!d*1yXukP<n2Lf=dge
z^uVN*J0D%rQ6QxU&x~L;26uUZlpYt99xkXAg?6l77nB}K=~DX#3kC8ayFmFybSaWt
zCJj}T9v74z_CkS_2N#qciZKeL^thn(+zGYq0x3N}5s_OUr3YvPQBWYI#|5Q_<-!6f
zJuWCccS5PCKuV7bN)OYD1yXukP<kFg+SCFmJuWCcOq)?4rN;%O=l8ffyFf~h3rY`H
zc6))89v74z=A2)sV>wWIn6{umN{<Ul&qmx`SRkdx1*L~Mmln?9fP>P*=64iG>A|lK
zsc$0Z@?o6+E+{>m@(avir1ZF;^l(ZqG>4JW<AT!j4)Veom6RSAlpcoZhX?9o=pYxA
zo+Ju^(vz||ZDq6J3@YpQ((?m({)i4u{}h^VVwL6LExp0#kR)<A-v;ua^fcU%J(bf)
zmYSt-uf}+_AZy1({Fd=pXSG!r&H#^R_ZH+R$N~pzhrlS1wc~=d!)~$*WbL?M?a1Jw
zF19jdQ*f=Yc3iyUyh|Zu?YM~FLSPggg5oY%J48-_tQ{Auon4R=81gTTPK;F@zQINO
z7LHtjtQ{Au9X=O~0$DpQSUVgdyU@YmgG;>(abY}jg0;i#xV}KvjtkZfbzV>)YsUp^
zhc9mn3uNuMVC~SkwxdASjtkZfS4UTYtQ{Au9ipBBSvxLRJ4Ag2zI?b~?G&Ndn!@w=
zbivwb$N$p`WbL?M?XbT7!t2QIg0;hP>k4G;;21(dR~5+GalzVQ+6{#aYXED9=(Yk`
zJ1$r|M0XX)+Ht|!q0IY@+<GX_s-=^LD9p+QrxaeQ@nD<@;Ua#^@wibSYsUp^hrlS1
zwc~=da|Y0AL$)MdikRUzxCX7{q>u54*ImSK;rblO9l!-^ha)wTFEB1xJFHRFy+Ic$
z7@5m(GiCEm9hay~PTY7B*D0Gzv5sp+Pvj5eHjmEBaURuRp-AnPF^a4m7pxs_L8Hjp
zalzWT2>)~cg(_wt=V-&7gnwg5$ni$h^VS#=a=ei>?6?H^H~wOIRZcV^(O)9h?kZg4
zBud=awXh3hC92RYfA_+nxVCvpo~8IVc<UkmCUH81`O9P?jv<RCy?eM9vW_8(CcV#)
z19?prO?qXHZ??6<q6xsFX+?h*$f60rqG7E#!Uj48V9{{9wF?m>2Vl|kA<Zq2MH7HU
z!<>GBPV@m-G!&99kVO-KMZ@^aRYs0kco}z=;N3JHNfHaPgGKWY@@2`Q3BaOZEw#d;
z3BaOZl>7o&H26s*uaqN;CV(@WQjRQ|0M2YHk<l&Ogq{z;qG7E*4zVEwi>3##R#-Fv
zSTtiWZwqA6fW{+Ii~?CS0a!FjCRsEAT-1o%0$DTxSTsaI;g8&iz@lM&VSy}~04y46
zmNT+s(F9=8+{OBYMH7HU^EK8-7EJ&a4W$?bF6{s;8dcwGSY!cMG#pj8Ko(5^77bBQ
zAd4mdi-ssHkVO-KMZ@+*U|moQSTsf4t`!zd02U38i7Svr6M#iSU=+xr3BaNm3}hGX
z#jOA=8X~tq7EJ&a4N*`aizWbzhA6~YMnGWEa8RNGSu_DyG(>~2P=vN;vkh6YXacZk
zc&m0h-02CxqWLMREs#YMfJH-K6v(0pz@kwtCyOQki-u`#fh?K;EE?5vvS<RZXjofV
zAd4mdi-ssyAd4mdi{?I*iwb1X1Ypq+6$)h01Yptp5~#L77EJ&a&0|1yg$C9K77c5!
zFOWqOfJH-w-q^yEtQ{;Gj%;%w&5;F*hV@M>kVO-KMZ<9}7Ov$q2aASia)B(G04y4!
z)&f~H0a!FdQwn6!1Ypq+O)Zc`6M#iS)K(yiCIE|uXj<VtjtN*aMAHkkoGoC{uqS2|
zNMi`Vq9K}HAd4mdi-xGZa42(vMZ+GPUm%Mn0E>oc3kqb>1Ypr{wk*VWU5dLYdpz2i
zvbhdZHv1@Lb3tUuq6xsFVe%-lXacZkC}$K|GyzyN%$#GnLC7j=dK+VuYye=<IJlSN
zYMr7J^TsH$XacZkcm~NRvS<RZXcpl=zI7t&s7?+QSTt<(D6(h*uxJF3MH7HUBY-TL
z052{A$f60rq7gtAO@Mb8Za<^Qq6xsFA%k+%Z`q$<(MUG3XacZk&Ou6!z3?=2sOOUe
zESgbd(F9=8+)pjZq6xsFc~i6`Uvm^$GyzyNyfum}ngA>s0c6nxV9^ld_))}am7a-=
zQDo5sVA0g!UXFqm>BOWliY%G{ESha`Z<Oo?V9^{5kg~a5<oLl8A9Od9MH7HUb2#&p
zMH7HU^G(S=9Q~H#$8|bCdY&wr04$nIn4c_~04y45{*h?@lRD=IhI=1#kVO-KMZ<(>
zY^K3$!qRZaqRBL7cx^b(<0I3Q;d&V1kVTUjE1=FHizYKpcBp#wsGW`yqWN$m@dA1|
zGd}S$B<Fa4cb(=LW6q?^)}h<uR#J|rtGY1sut7K^1yo%eahVzpkEpBakN7mR9Uf6v
zbxFj>nd|U~x~gvp2pk?!S9Pg?(BTnvRqF&q4v(m-x?BVl93D|ubwz@+u-4%bbyZg<
zIJ4^<9#L0?C>#Lw4v(m-x-J@mqGKH%QCIbS0o_J!2I}U0Y2jSMrp5^#QCD?+VkMg*
zN7QAfhCE<QOgY(Uxrb56aCk&rc6#jyN;MKZqAoilF&?Pl`6KZ)cVCmQ1jaA4RrVW5
zX*{S42@SO1z_{5Yk#|=PX9~=Gm@cfOVLeN4Bc<2D9M=gUX8#+y^ftQm*uUPwd~LTQ
z9ag=uAAFr~9xH`CQpw)7BzxTHl-ep%Y2;H<MW5FCSRW;^bt2z*OA=dWRY;s#l4v}D
z$AoP>u@Rrjh<I2px&YcNMVt8@`K$MqjEEm)Gu*m~P+7n#twB22@4l!+2m77J>o~*<
zuS>yxy8u2$u-|56`xX8?=HE)NU)J>rgZ;*q$tngp)WLoiK*~Q2_ABj5$3b5RO2K{!
zO2K{!K04Sh+k*OZ&=&@{)xmyQ7?F(e6hhD!0y`ZCeIY0X`z0s^`z0s^`z0s^`z0s^
z`z0s^`z5IRcL)1ryFOO1U)KIfg8eGNA3NBuh({DgPM&`j>{s%}!G3vN3idk%pcL$v
zVC%ttS>`_x?3eZYE5UwQ?tdQamr@Yym;V?(b09*j3iiwU=<hX1`p96vlJ8##_RDe~
z7VMX49~SJFX&*1xFLQppV86`ypAPoRI$y??UDodcc^~~=hn?)>1pAG%OR!&FZ#~#A
zSB(Vw<*Kt(6j#Pll`R-MxDN4>!i&tu3iivY{>{ODXF()_{qmm#`&FuLCD<<${*_?A
z)OjG-@18*ayTN{0Uw`yEy7b={?3XgjgZ;8E%7gt9mk0YL{uhG%vKWH>@}C6zRrnJI
z`(>ezAMBSc!@PfqFU@vkuwM%Ls9?XN$kleQ8pM~8QRHg7SJzM+?BIy%f>(c;=J={Y
zuC{ya;7Pb80fN185;=PGF1*3tQN5PId~FylC-3klQ-4k^&r(uRg8g>)+W-<J*q>L$
zYZWEf-%bFd1Rsu@5&`&!xIhHpEAeks98HF|M#a%&s9*i#xRJ4WIclFpnEl&l{~&iB
zV#e?Cd(+~8sWz=#nZ=^4O)FPsiCkCN_$p)5%9Yu*z=dPe%9Yt&!XA$vg~UoLmrW~I
zW?6w9Ix3D8!={dkW5qD;@u)af3>z}E6f5R2$cl8V7}jb;I#x_IWZDs}T#OY{gETkN
zv0|9hkN72*v0^AB9qCvx{|!_HyDk3lQpN~d6Y-lGk2I1xR!lGMC3UPA)-qJAT#Oad
zfgXuy<zlQDrJRlxqm<LJVhm(-BU-r_D~7fD_~t|iD^~`ILrbw@)>EdA6+<aTq+`V>
znL1VsksHy<#aJ;!K}0JTW5uw(Fw(JNs9DZP(#pkHG5fQ=Qmh#Msu1Z|F{(a(uVt(l
zRUfTfj1|LCbt4@shA4=1tQev&(y?OLzQ{=GSTT>VKCyB!R?H7spN<tnU_`WXF;)zt
zi`mh=xW!m8L~cYY7h}Z`1(A*wLlj0jRtyIvifH9xtQev}nBDV$GdA0h)UjfCYp7Vc
z7%S!gG%V7wVhD^#$BI!c*Rf)l=0-YJjB2@#6~o%Xh*mDfiXqBHI#x_KD~M?2VyqaV
zLZoBG9061t=~yv+Ky?wVT#OaN+Up}7E9OL`jg4sKVyqaBY;!~_7h}b+zKM~J6~l2Z
zMznG<Rt(YPNXLpHYK?TP7@{c=tz3*1Lo_wgv0{kYqOUOxRxYAx(R&;dSh<L%N3?P=
zRt$S$Mno$YW5p27j&!UTqW0)e=7g1tJvcwov0|9EAflCvv0^w|7Gk9Mn*$CQkWu40
z%-HOsjLij+)UjfiT&H8jP)?nW6~oLf%iW3#S<~AXb+Q4#%5^0Zxmq9BiFu<=$BJ2x
zdv!Wi%pU<VHnY~z%EeeQY;>KD6(c~$iV;977h}Z;(6M3!=vXn_e(H3rn71)Jb+mFZ
zR*YoRv10i1v&&vM5$mCWTP3VqbvjneA-GvbD;HzMoDYz(Pod&ERt#^|(aObGF#>d~
z7y_3ckKj*wCNk=1<zlQDvEWh=4^frGq)|sJ7h}cHm!eK~16a8jxE;ah(OQ=uBLH<b
z>sT>WxL2oR#mtcWKVg1;EY|ta^R#j?Rt(RstJAS!r1>ElxLW7@z^LkG4jn6o2|i=R
z(BhYlW5w{=NI#Dc#ERj17?F-+#Sqk`Y2`w!7|xY?{91*j^%P2o=EDt}RxZSfVT>7<
z_y3~PJY&?El-WA;1>DMtm8<%~@EUBlX<E6eFOIlOjWn%X)%}q?xYM+9RbLYEaptCJ
z<*NRcfFMmPSM{X=!ZfX1)$0UAa?E`7<szVvrj@JuiUen2ZJJiD>Z=o+*>!1JxvIY>
zpgv72SM_z#9nfZMnpUpr?+fTQT%MK9`_jU>#%OA6)5=wSeZs(XV@ofrL*q?4u;TPr
z?GNbSoula(@WjTOGk6WI=2+U_fZLgqMk^eY00HB^O#u&?r#uMaC%VAwKMDEAv+P4t
zRneXajPqhX)XrXkg{qn7F&huTRUQA#KX@&>0b6U2YS~f#AKfxb{`XDPc_!^AH&Br=
zE@E{TnhSr4ldPn=cXV|Z#?^JJ>Mo3{>nfg$9y2datJ?dd_H`&OwO^NvYd<`${fM~s
z-ibO-Tzd~|?_lkRWp3DDy8TqXe;0Jh1fB?B9yXpc0L?2(YkTARdM2|gjvlVMqOZu=
zVjknEyuC*2<|Bc(Gif>Nl=iT5r2Dp;qRMnkkb@Prj|DCrF9$1Z-=x~JP)Xb&me^N(
ziN?VlQ)-lYryK@xXF~W`s=Fxtd+6J8rgZ0_Eo<a|&qSR*>3q3?*)-)!T-}diMHX9}
zP64*uC8-Cr+$8_IjAmvE(G`+uNjlE3cbs7b9wR%VzpQ=6QJDlaY1{V*-q?XNx{VXc
zS}}^xuxUs3_8B<Dj62};1CKu1uvU7!Hm0tngjq@gkEU<CLvAdPYmu<c5K2&`wpFDv
zHY=EMCthX~aoK6d9C$dud_G&-?w~%~$n%oVB`gWUeHEX|n)y@IfNjF)!*aL`JHl%Z
z{BKw@owf|SMXZ^r=BjzTrZqElv|Nid(}iyvcYeoCl^tD{Dm%I?rH?M-Y_70orpk^k
zOI<GWL0L0X6-Sq)%8o8eRUTdT57ta?(2xbFMp-kxvZKqqvZKqqR;f!JUFNl>*+^y0
z^jaeVWzF<jhY^T1)BCWa%h-0*C)P}_?C3IYrWi1lHPb7%W_sI5in3;Uvjr$?rnjvC
zWzF>F2vF8cZ>|7k&Ggy@C~KxSPe7fvX2R!+&W&<(nOA;vnOA;vnOAXinYWdr%h;}x
zHPb6Qy38v-y3AYY$P7u--_0vOy3G5qqsx@w3TviUc66Cnesr04yb_O%oRddcGrfVM
z%e=Cq%e)uWpwgP@{XwpkHPd^^n}Wj1n(1v6psbl*`O#(GCMlz=nO^zPWnTHwWnTHw
zWnTHwWnTHwWnTHwWnTHwW#0QzkFsWZ@OPVm*KKulnOAXinOAXinFoJ2cD1r*dKE{P
zc@;;Oc@;;OdGL382j$e!WjLNorpqU{W_smEmwE7aqcVs}#&NGWx(ul7=rW+Pqsu(_
zyUCJ@?!$iQRUBRB!QYK(%9`oH-)-RNG7tW4OjFiOuj1%3uj1%35B_e<sjQh^#nELR
z{M{bLTckR=%!9uhb1G}5S8;TiS8;TiS9x@qS9x@qS9x@q2Y<J+qszR1IJ%5={vTz{
z^eT=n^U9Ad^Wge6aCDgm*EedfteM_N99`zY^^NC~$<bwA#nEM6#nELRT;FJo*_t)e
zD?hr-gX^1YwGmz4yo#gCJh;B`yd-sWnOAXinFrT5>a47p9$eoBteIZL(Pdu6(Pdu6
z(Pdu6(Pdu6(PbW7-*|eMI=ak*>l^D+)=aPB=rXV3=rXV3=rXV3=rXV3=rRwkZ<P73
zSTnuyqszRCqszRl99_mP-kLSjD?hr-D?hr-`^TfpDCFO5&GgETF7x7}%fy=LmsvCY
zkFaL?%9<$_$35|uKia6GF;iO{d8^#wC|1uvSv|)bgG8}<2FmI=<}}{msbuzN<Q1v@
z3fw5OPnz4ynGG46mQS%y;>a&qJ0E7Be1Z}`#6CIZO(cG}eNql-tC~|g9&e+{{94uS
z?gk*{*Q$9{yjJGds_g{O{5k?R#j=^*J!EslvYFjy$a%b`Wiz`n$2`ii8Nz?>IUuoY
zhVb8`zRI#0!het76_jN&gk_WQ&y{5}g#R9MD$8aF%O-^=%Vr4wy*~lLvdJvGl&^rW
zY!cHKQgCe91Yaew2KU6W8Nz>$wJ6JG2+L+C9w=hj3}M++%F(hJ!hcUGN6Tgi|GfYi
zm1Q%8Ws|kWmdy~B%^^rsmdz0Udk<44Et?_y_b5eKHbeODDVelvhVb7bQkKoI!m=5{
zvdQ|CWiy2T9yN<Cn;|TlhqFGhY=-dPYY$KZEt?_y_f&nfWrP)$%@CGN&Ie`L4B@{=
zq%4~u{P&2IWiy2T9@`gNHbeODJ<IyUvKhj%Nh^m~HbeOD5h%-M2+QVrAZ6JMVc8^7
zmdy~BO(JF44B@{=q%4~u{P#F0%CZ^4vPneC<|5=NvuuX&-{UQ1*$iRXq{Toin<4!7
z2$W?rg#VuEX<9Zz`0p`ISvEuX@2Qs4vKhjEkF_bwW(dnBk+N)t@ZaNiDrMOWVc8^7
zmdz0Ud$d<7%Vr4wJ+V=VWiza>Y=-dP`yz5G%Vr46CP!9THbYo8S)a0OhVb9xI4jF$
z2+JmsvTTO%-y>3%%@F>3M9Q)m!m>%EESn+x_lT5bGlXT6NLe;RST>22Wiy0jlRcp<
zn;|TlM9Q)m!herQSvEshHra#9vKhjEk7>%X8N#y3*+R=^4*xUulQL>thZ&oFl(D%W
z#IhN}e~-yx*$m;oM>%5I4B@}W%r48_jSE@Bv1K!aW%EWRa<x9M6JyI}2>-o@aZfCp
zA^i9L4v?{#RV<q!ESqe!ST;lW?+Kt~Glc)109rOfST+UFvKhjEPXH~OA^i8a{fK2V
zg#X?Hlt#;D2+O8qqh&LM|K11q@3I%Zh_Aa9mdz0Ud&lCYST;jgHrD}U>~p9%Et?_y
z_jpSzn;|Tl0%+L`;lD@V^5a?jNzcTV%@CGN`h&R?^mm;YTQ);jHaFp(ST;jgHlvVr
za=UQ(F&<ENGcB7T{P%|9o>(?R`0ve^{0}fcKlax7W6Nd;%jV9^Ps?Tq|2=8`?;+_l
zofDSLKIWihGlc&h6a2B&4c_Cp5X)wDV}{p8`gwd*H)XgUlx4GetN>-%tR5#jRBYL#
zsZunLEt}Qj6W_osm-lJ=leE~fS=~DHb=+2#&D@3IEl3y3X0F__nd^__;VhQT+$9ko
zXUejf`<4J@+00!kKv_0(>jWsvX6|wkpe&oYD-xWA%CeceI>DK(EStIS2~d{J+;!2t
z&_-D{bKe&L%jU_boA;#^bB!_7SS*{l>k|R48}mouxxU8ai@^=B<aFbUyV-vv9#k}J
zT5G28GO_l~lbd?`U~gKpZ63QI<GnQX9C!rqjx3m1d(+8c__RJNZ|8}%H=I094gftl
z|8*z;bKkfO>p3OQ?C_l%XAyore~hFaKkg+o$~rYp?HzwND%}ii@QaOMotOA7jF%G_
z9^6`cz=X%;e^;|kZ+TU2Y==2Wqu}~S)cK~?Pje5TShL10(~xMbU5IR1TooQw=bKvV
z-IpkxKl*|(Z;U?{(%O+Yl~w=Jod`JL8mVE=3Ez_cdrkPN{NH=R7v=woW}Uy~7P+x~
ztjhTi11gwd{XVk?5}GxRRhf^?nyPHns=Szp)mXr#^$U#7q`&lHx7%r)bTT`oNXuYy
zryV#WinQw`7Yye!pxCw>u0J!BJBWl^O71+2vwt$Jgvo^-?;Dd|g0#erO4>Up+$z?-
z9p`aMNvXt6LrbL+pHZcz%!GZ=Tw37kC2f7PA<68Y%A;WI^V|gcyvVV(&uivb8*Mxa
z);`)LNKBKIKA8pDhM4&i(v=Ny0%id=6{GMNDDIef>mK~nhA1A9pV|;VwIP0LLkyC5
z*es8Z$M*E84G~?jAbJX~PM_Kk<wwaaJt9A~Ax5OneriLEUv~fRwjqjbFukQmWO_@F
z$e`RKGAQ$i49YzsgOA}6nHf=E@`%ig6pzgc>*Moy-K(@dz9DyhgU^4kK30`^M^?q&
zk@R8_>tj`!cVt!U9Z5fztymwc%Df|CL*#G$+J;#2j)V<yz&r9EY>2G&!)%Cje;KeL
zGUq?BAu>z34Uzbt+7MaGhu9F6a{njV5UJV!+=eLLOX3|#8zRww4Uy>oKN}(kWx$3=
z^uK9CR4vywMAkN7LnQi7+7MaafDMu3JYYj48n7V}4cHKg25g8#12#mW0UILGfDMso
zz=p`47_cD{4cHKgKFo&5w12cAF2vnWW<#W$|9}mVjV{>`1!x<h0Bu7Qplyf(wrWEZ
zhe&Nhlx*6DI1}}_?1ld~ZHUtRS~Q=gLa~5-avLJoL&=6nP_iL%uKaJ>5cxE-wGDB=
zI}$cTf|3o9pkzZNDA^Dx;NM|Gq<3VQ4RQ28*bsN4F;CeLJ7CF~x`hpK>J~P{`Sd*~
zvmq|}XEsDKENDYKjP+<6V(++f@x2f>MCIYvQ)xr&6C2_M(B`9Th&p`>8{%J3ObmC|
z=f#GoacsC-9@`KXJRaK+Z}iG+h%1y0u@{MAL%b_pW<y*Y+Yon+ZHT+YHpGr*oqr1(
zV(_b2m1mU=QR6Lah@HrWpP+E4;s4x*$Q?x65INzs4UzXho(-{73N}P3rEQ3ONu;gs
zBW#Eq>yizTpkzao6k|B7wYHIaqhv$OAFXVNXQB%tm_o-r3L9b^A5g{0OQ_(AIJ|j3
z7#neb`>mXRDoSHQMQKc^D2<6YN}~$Om{8Feg;kws%QQeS@k6wmt2krD579nauEh^A
z2|vVUBsjKR=7(sP`61fc4-pn#<%h`pWL4W`eu(zvDb}U@5bX*-M7zun(XRAEj1Q(C
zU{yPVhR_W{`5`)Geuz$)AEMJLbtykYr&U5KD?dc1HKG>E57B8IMj(EO&WHISvMs1j
z{1BZoKSXDyr`khSwKGeAVpTia2vB~A&TIk757F6Hfbv6h<_J)Jh|XLA$`8?L7ohwQ
zop}OEeuz$)4bdt0Lv+gh5S<D?L}x30h-_EM578;}Lv+gh5S^6{Td7#pPPreV^I?97
zN^pfAqEqIF=#={*I>#&Vc%k9sQGSTdfFGh$=7;FKs0NjOh|VA6TKOS5FL_H)SotA3
z8wDsoM5o*j(b*(rlpmr~?uY1<`yo2zeuz%FAEHz4hv=01Av)!Lh|c>`kMcuwD*O<g
z3O_`r!Vl4bA0oS2`5`(Leuz$mAEHy?hv-!JAv*9wq!joe^5522)x3}X-jY@Al=~q%
z@I#b*;)m!|_#pz7`5^+8`5`*+Lu5I{s&*>;5FPj-GEMm*Iu(A14*U?Aru-0{3O_`r
z!Vl4bA0l%qKSZa(57DXcLv-MW$ehX#(W&r5bSnH1ok~AMr_vA6sq{m1D*X_hfAB+O
zom=xm<bCve9Za4dhgBVC7gjZ|x6Z2Osu5N-R~;ODh{cAewk=^*I~9J2PPreVQ{ji`
zzz>mCDL+K#Bm5AZaz8|;!Vl4@@I!Rqhe*dj_#yJ2u&R}+!!|hOeuxhI5JhM4Lv$+q
z5S<D?M5n?J(SaW#byj|e4*U=g15&JNr@{}>sqjN|D*O<g3O_`r!Vl4@@I!RqhsgSr
zAEHy?hv-!JAvzU)h)#tcqEq3A=)ez=GRyrC*%#%kYT|NMH8EM$PPreVQ{ji`Y{d_e
z#b86^KVelXT>H9H?uY1<`yo32=!eKcAKwp=EyKLu8mpRuVpg?N?uY2aeu&~zI2x}@
zql~J-_&1tAXs1Th^VVpxm{TKbC|>M_?l|Eb+Xs)t*TV?~PB(kS7+g0iyB^8aZi{d#
zviA+e9_7sle*i)0Yr#+gkwElJpN=<c5D7$TdIhq9NI>AGzd)cK;DKRNf;Y!H5(30c
z5G?JV<GRGs{xc=>T^=lLUYA(f1auSpG5-5OdX6^?Z=h*LtWM9(@Ft>if+v)2&vFxS
z@p85|(7eRoSnf(_XHFk61x2#FzRldt{hKatb_^dVZ|*T%%BLCe+T3$^0xyw4nh~$f
zWy2ZHFibPZwYhxwQh+GU@Ym*E!%3Yjq(8%yy@#KHl-l$PrtCBP9e}#@iE98>3?~z_
zK0OYanfnf>BiY!rcPYSr!`WBO=^qUNSSg^G-hrTV_^}W@HGSf40Q(PL0&tUIpNn2J
zXAEva6YNF2o;NfL(HWZ&8V8NT2mc1k2b+Tw$-Cn)<lR2IjpUujysVckk-UaImBMz&
zu8<4|=nSXm41<|{us~ix>=%(V#!j%<g6!9%*oC?nS>8$qxuWd?C2o^UoIx3zLhQp?
zc;_sAxez`8pQ04|O%;|px2V|u0Shh4Cea@mJB?2%#9<gHWY{%q@8awP$u(K$VkZvd
z8q9H!h8gyB=3koKNAmBl^K%4L{#Bf3E_FX0_q=AH6avWMJK!_H#IT0$Rt!@W6!YwE
zBYp2am_0bJ0tIeMe-9+FV2Xe{(^tYtBA6=RuJn!&5VQ$cpI*Z<(*)d~K8;|yfDP#*
zSZ0QRhtr!WZKi<7)6U)ivjjY4*wiQ3CP5WPKZ{?1GKW{uQKx>*G1xZVwX*yQA3m>7
zIXMAZH@wL&)9+df3E+{_$nyxS4=kUWBluS1Gx%O*83~^r%GTQB(C2Jy(;620sWp@m
z`<~MTzjrC|Z6@7q)y5JVxLa83t+bNZ-N1Qo-J@|=qiAryHA3ZI-S`4){JAA<0(G*n
zK;<8>0#*f$jIr18MvWzO&AMmxk$KCobu|1IlLJZHDp}o)>>g{dZcSe!``apL+|$Tj
zwuWd7*}tapFPcfty1r*j_gefn`yZohY1d0;#I=Q<QtjHP-X39=XqZp6UN+O5RXChc
zwR4kB?`+I6{WUXgN1tl<AI)J(SJZtz8~!;}_c^~d-Hi}r_TP;!tE%pkb=^x<-KS{T
z3mfLM-JdtBxj=F3q^kQ=ojzaHefk!4pJB#*zM}EFZ1!1Z+~>WGhf&wFHSTGgPu0Gp
zard}G4C@??y2f|HO44`+vs`9Yt6^T=_y+Oi2%0Lx*4g*~tGGg^cVGwnK64nVy=$Jr
zi3(ycx*A40)m}@tcX@*dPw4h^G+fC!Wox{&frl?y_;#S$zfiT`(dmZL-_siRsrLCA
z_p0`%HSSSklhOUtIidY&byig4Zq#|KZq<s$KDKI{#@&q%GJU+p_~PAM&#t^#Ce-pL
z5%En1bwo8NqB5awo~q_kSBtdq=J}j?*4oaAGF@)fvt{Bsin&b>&_r1@x5wkxGw}pg
zdq<qwZA@Cs+-FLq8=lbXy$_WZ5n9hWJI_n3t(H^w$Nw)y+@-O!TKE*Q&hfclV}?(Z
z)%2BWrQm8TeLgvxJ6YGxBKuAlTX+tJ+5e|fgLZDw4N6GHdGQ2LEm)|RwQ9klxCOlv
zd1Q&TI8N=ENLsM9ByN4TG5Ln0P|GaYtZCt)NzLqMW6W9Yabrf;EW*v%kv!6k%mltQ
z*l*!eIhp+&T|y_be(Zm<N5QA_seiYDX#GSu-)$VqXM-4vKw9NsYSL=SSOn54uS=v=
z77)_vBe+QMKn9Rjzr$+=5ddkG_tiI*-{C?YJ~S4Av`WvIG!J9|X_a-ANUPW58qMc{
z3?Qwtn9TzjKw3q|8iB3d%V-+P$dL@7sGd$~3^WdkDzA+y9LWHRs<c7^?t!98P@<?3
zlqjkMVHJ*K07dmnD2`~o_5}QQ8HnU!{E6nMPfSCgsE)vbmw<bqsIqX0qDr7lL-Cts
ziK411<dF>Vn`Mcj%9IjCm7qjXB`8r;3F?ec9mxQS>MH8MBN;$Z<+YLKkqn@y5}Z=a
zBN;$ZWeW_mnnyB#qDq7#8QkIce+;royGFv_`^ScH9%zm3EfgvpxnGXgMw&-5fTGIU
zm1zhR)jN^mrl|=is_ct1(P5P5ZomisV!>JaQGi@Vj${Bu^<AJek7NKvmDfg^M>2q-
zD&ir8Uuxxt)NW8zN#m%(kqn@yO6DpY$pDI~<gHQ^RbH1Us!IS$6jg$%DjvxIit1yi
zD@^l922fO4rbJO?Pt>M)Bm*d_k0klx%Oe>;Q8hrmt55St22fP%0mi0zBm*d_a{!vF
zcq9WTsuW!WfST`#nlk{PXKWhEFXF6(X=pwQwdZ*x11YK<K-)(=l7SRe%9x+$kqo4$
zQon_H9?3w8>e)a`^E{G)6xGAfB^`Ml$v}!KAK1(D+P#cRYDJ#0L`YGklrBTQGqKPh
z`Cw}Y{TEs(ub$}d<B&9%Nd<Kz11YLZ&+|wIQdB9%$ZLw~4N%+8^GF6#REgX?k7OW4
zl_<#bNCr|=SuV_Lis}vcLKfwDBm*g`Oe^MjBm*g`_aJR*zKv>Y(@>sAGLWLm$Xv7Y
zJd%MFRj%yzJdb1`MU_(K=j&JwrXi*+$ZPkqXHafoo<}l}qRO00^E{G)6je5_BhMol
zNKyR~axNdj`A>=}r~CqQ2#;hSMU_)}p*e&{GLWMB8uC744PhV@QdEyZbDp<`JO=5c
zsJ??#9LbQi??DBzF?%qtvo<HPjKo`jWg{W50p*cr1Cj>wM%I23pEcjWUCz3)?7XE1
z&Owrh<YXMkgVN)1LySY5W3mooV^NpJ*ufcsj}B)h*02h}N7Cvw$dQ-T4`UI5k<YWS
z+E|q5c?~43%E+TGc0tyr;GuF}14*lYq7a_fK+-CKk>`00B&`xTd7jrm((0Z_ij74d
zAR$(D*anhTBXnk-=QWVD%Eye6*Q8aBpPldE*uq%EjBb8BbHZ4}y}CZn^BPE6Z9uUF
zd7jrm(&}MA3-dg$fuz-2P-914JDhRpbme(o14*kyJ$atjK+-BvU!LbRkhEHl`qt#1
z=d6RVXe!WYd7jrm(kkog&ocxcNvkZkF3<BCNLnSjD$ny8NLnSjA)jFlFcuNrmfwU=
zl2(cC$}=`QNvo6zV-e>OtCmiJv51(J3x=_Xc)rFo7Ll}i7;fZwUIR(11V*0cHITG=
z5)e)x;<n055fdAWxFTX)`#MRhT)e}%J&?4@ksAIiRfVyLHLAMr(uHDUQP$?2kzBtr
zIWbFqf$OZqgd53)q$l#5a{KrAbY+5at#QC(V-ZQK+@I>s;}n6hh<0xK-iffN>{f%<
zG-DLME~XE!l4)@dMgoM>1-LK9p&&L6(I5ogX&3H~-W@gAJMpXNq*~4i_g(beNw_)2
z7~G40!e)iH7;g!i72aYE6vzmDpom_E`x!aZ3>47~0GcAo>k>tjz(#v7z<)o;&hh@r
zoV5L9=Vo|Q*?zL^S+4om_LH5Lc$DSHicNe*-odhVgt<0yBt8al_g2yQ!o{kMP1vZy
zC2~D@0<wtzS-7jRh%q`}xVuokM=wBPLY+Z@pAmTmg^WbFOcs}LSgUsr*)`&SR=v-V
zmAod0wR&Za`YH}<4jk6MLsouA^k@zoR@Q3d8J#Z&4l6aZ^ASFC;IPg{nww{Iz8pBL
z%<1PDoGS+oD}|)<!yz~a4y%uLfWs<Ta2Zbk!9z8UIjlKwSb3y~a9DHTu(B5Af0hG>
z^(17^*I}9Ez+qL&(f=$54y#g*9M&8-tn4~B&**$Pa9F88%wf%e!#WjEaaeQUu)ac>
z<gn(zVU<D1Gdf=m99AWh9M&8-tVC{}(fM-Vuo4A%M(4|c!zx3SXLP<CIIPqx_CL#k
z!+Iv`6Ao(*99G(L@_c6Gz+qMOk;9q;hgH@08a9p`IIJ91H_zyNIryIu1$jp2%Ynm6
z6y_P7F9!}Q+ZS_KbKtPP&H9AHngfURY1YT+d^vDf35-0W^X0%{eGbUZ--}y0a9D}l
zJYOPn;II+}c}C~Ufx}7^<`1V7a9BAgQGO)u<-lPj8id8r4V<;v28qs>1BaEj6o)kj
z4(nNHSf0`Oa^SEM7<oqL%YnnHT22mY4jfjdxp_wC%YnnHTHeP#0*95gh50Ns0f&_+
zmuGao95}3BL5V2O=zO_Og$j8_=gWb^`gNq$<{6zY2M+7SKy~>B)&~wNYp>5UI$sVP
z)^8(iZ2n1n=D=a)$TsI0oi7ItE9;w>XLP<CIIJA!V*XlAb8uLRCg)cZfx}AFnrC#r
z95}2*Q}T??mjj2DXlkC(`EuZ}61C+Soi7ItE77$4dmIyRSc#_R8J#Z&4l8?NMxN36
za^SEM&CWAAUk)5rqW1iu%n1%FdvJc9(fM-Vurh5yp3(Vo;IMMGEW}71jJsL;4H-4A
z!>r9d%Gz8I!ePbPZV4s}hcyQdE9Hp)Sq>alW_DTbx44is9dlT7;IKZ(M6T9%bz;n6
z&4I)E3hoJqH3trB4SFbRGple|bKtPD(c*uW1BX=r{m*jXunM66Sq>al0kjF^z+n|Y
z|Fax8tlWNt!<qw!m7A+@Saaa8N;dkR<-lR>K#I#=_%?K?Z$_7Y5J%_Bfx~(pZVHDr
z2M+6xL`%jT6b@?+99G^E4r>k^RsrO&=D=YkaQX2z{-kGO4r>k^){RW0pc)LgBqmjK
zz8pBLN!$|-E52(Cn*@-xxm~#Y*g@w<H}ltu95}3P%+Kh2IdE84O8ys_pC8BS{4s|$
z2M+6j%ufz$4jfi#{&W<+ROkG_82lCHAcr*v4l5J<vH1q?Pq+{cYrZkVYsF#BH)XgU
zl>b?NtbjU+&X*r2I~4rS`0DZjN=Qp%4r_jV;s?0p^8PR=BWW>*HQzckja!ZzP4_;7
zi-u#TO*Nt!=`OUm;n*pyMl>_c`-aQMnY@2B1DUWR9EZg}E762R`*+K5-4RwnyT&k#
zmU%beZu){%xVt>ywUJIA0kD?<JN=Wx0QOE(q?^74#@J{d0RaYpH=9CcSTXJ>6b&2e
z>Z1L<eX(1le}5uw9}r7?lVDZ3#I9K4`Bd$|^iGfzq|faGI4HdhKvjAr%N#5qo4(~(
zfNsearXM{X;1B`1^wCT?R76MV2TlMuOh7>?+avYV8chL{4j*?n)U2bLecmRjDGfhX
zGQ|x)PC(r7<6||~9*okf1qA8y_XjvZK$xc4D>_k>iPBvM0h}aYP}*Jzutu`Q%6wJ;
zlyQ5I^tq{rLW8=-_V(yhk6c*QXI}`|twvh<>@)$fGN(&%H@yr$P(@#qlvtTF%9S~@
zT$!`Vl{q_BMmqgVl2WTW{T%7%5vtR_EMTPS^m8R!o$B<j2pFw8{XEg2UUm9f0b|n(
zIci@O(45|piheE4wiVTIoG%*8R#S8{?#l$XjHcgl7{5OCZ|ITsv9n<)=?$X`!{f1S
z$h%|IKYrldG5Xd7d3Tf_W}<ZyIBSFSL!6u65fG*iz-w-FnSdzW3~|vF0t)GK_XfDC
zg?(I`euXL52&hZ1W6E{onNpuVj{>e2FgE=v*US&bABcLI(>D;@IDrqwxKTGtwyEh;
zsKKqnIDKcN|F9>(?E+?|Ygx~aYAJeldN4)*q>i9HeG0){;|S)bS1{Yp1T08DNwB__
zt9xPk7>d5PmZCe-Kc=Ghi|9SlPqCf{#<N3~r*ERP4U)1V-N7;s3fMR86Fe+nzjPOy
z@K}<MsZOJby&XM1#>2Z@IPNU;c-C&f1e93W_yO`_xpNvmH5-Jf<9~^TYb`f9D#^qP
z57_R6{jqv+tcjSJ`%NqM6?_*3oB2bVl}yzT(1?8&R<Pxy8q7h&y{M5Rowd1hOn7cJ
zZa(XXoX(P*?U7Z<`K?na=Q*c=iAoM#Tqit7@jp}&>Pr%M8i<l`;}#Nba!Q&^n8H?k
zRh8Xn=vMr+RQ79Ils$i-_K7bZgR)0E&iN?Ufle~}hYZ$r9;3^xZsByY`kW!0PwWlu
zs@AbihLeCceIei<=cGBsVAMAzIao(l&T(FS-*m6SO|$=olH8orq<XchWmlDLs*=;$
z%s`qbw!OkD>SV|wXAsA%crN>>MpvrhYFdLFF`q$+$v+&AS%G#G(GF{&lWBbjH>|aX
zw%#rOv4Kr^=_K5FJ6X;8&xdMg22^_$s<rUveI!lfw1l)NG6DXc)B|TsI12lO^{b=|
z@(b^o?hR75yP&)437xm6<*DP4^~q$BiTKs7<=ZU!R5IXVz^`^KKRXuxpVqju<-ikw
zf35L~mIs*r8;zG^nsMWq@Fi-$UTHA3q`{_=2KQ{C!M({M6H6N0rzOT3+^=!0!Ou00
zHF!W{YQSgDgb7r%O=(d7cl<7ccMG%s8$)#;Oj8;#h(pUl=AE9b;&#BO4XPJrD47h~
zpt@nEzH#lz#lNwE+a%*@)mOZOc(%s9!u_|lP1aa=6~Htr{)knyC&hAOt(`x04F-A*
z)Iy^TYo}!Lz9D#Rzfea1pw=(T|L!)OVcO+#V|%>4{}opcqg*Y^ElXzqgmP{A#<au)
z*0uuqo<Y9)cVqYG&SWx!hPS>fVmg(S9;Awt-ekTFscrg3ECp*!q}-;Z9Fz2RACR(K
zN!hHWoSKYIq7;22ma-7vO{mL)&9N@0C;eEDr5L51S3}{)ZJDW0y=}S+WdXJh!z`DX
z`71k~nakD8d%})qW`~-2PinlhnC47=+Kxvg?(tvSagTQuf6fv5wLOOKZs?=pQ^dc~
z^81Pw_oiob`CenfvmCOoE8Xt@oBn0*`z77JVVCBttcq`HUAmNR7iiq6bh}8)?ooAL
ztjouB_v`dtV|qOsvsl$#{Hy6+ApJ5F<E8p#i9MNsE3}SkF4gVmRI+!|c(s~&yX$`F
zRsFEL?uTxy7q0#3gVsRI7*%8YTc-QE>=`|!8td)J1l&@k#s;l@ud1<0<JDY&kT@a3
zv9*=NGyh_`w~564hU*oWwDpdqBsyB>-WI-hS}ENhJuQ6S#VM!p*mk$@Rn+n{Hd^>P
zXZaf2E#gy=*4R}Kfk5M+h3{xq#?J7~n0?51W2>q(UM+k*wz3+pXyF^O73%!UTlkV}
zRcqW~OxT_`{*sV+{Q8?1FKMekLbvs;L}gq5nuzCh+}6J(^t@GVeOu#h)s}ZOHdI^w
zuCcA!@@}HCEt?bZI_Xrpzo*kz7!w|0V_#6ZE`_e^MAutNy1uxDu74QNRr>uUU3ZV_
z_l+9Iy1uM&tm`I?V_jd-x^$_2esw@s>DSkEI&>Y+Mf#x9_3bzGQ*bmq^wi77LtE(j
za3Wrly)FFmVLhVj?os{tsK(u@A0N{g^EJyszgyL{u2k2#rMlK{QP({Kb@5A`b+48c
z*L9!9ab5RojJm$VwQ;MeYeA_lzfQO7wk_(qeV{IB*Bx3`Pm9$3BaP!RxKrbJ41TP!
zZOr&S+j&wV;G5=6ubb}qvbQ*+blq!o-MwmEepZivk6M?X)3UnNTs>K1?0a07r)V6n
z%g<{Zugg<4j@RWEG>+HhX?pxS)w(=g&yN*qzI;*R<!Wx9q4RgBb$O=7ON)0=pR*J3
zGoa6yk>xtwU9~+#+b@&3e`=}i9lGtSRonN_{obeM)1F$_Ue)i*G>*r7xyEt7@1?PA
zOjyUdTh*9%{|PUfQupG~y5Fbhy5k*oYC^v_tGe3~Rs1rBw+U7EG>zjipRVhQ>z<);
zyzXY|eu?+HS-KxPRljbdalGHn*7@W8Zd;A9-(AW*WVC9_Q-3tw^Q0}CN^KdlMO*5(
zXiJ0EJ?^(gt!uninlv`l{x(+E9qT?$>)NU2z<8aGJ>yw!?)i9am2~^!7~Rj&7P{38
z=q77v&=$H4*1E*H6*P`@8=~uu_p_k`y2*YvOs7M)4(j%vrJfV7>HW;A*SfuLRX!&^
zu=Lk2H3x78c*PtrHIC<iHK3b(@kwZm`F9#0Vt-b3Ur?(1h*I5eY*F`{Th#p*t5ml<
zU*EDy&ts|UuNq^2JBtf%qpGXDRM)Rdb-lbrU7H5#k}-H?i@IL18q^o9cnn^#+7vd7
znFsS3k+oz$oAEMUGi|=<@71XLG*orToBm1Et6Eh?u4T(9T$DLWRvKUZi_(-xH>FFx
z$k)J$(nrR%oyD=7`Ga(NUr`)F2V3#u_vm7t=>?tMQ><dI*J|7?M=V%%8n2Kq0<$;8
zUj*h_$%nBm$6o|?i@ykTwCN06d=cnCIlPk@)_g1bHp;c>8}ZBc^7s}0)mP$|?~ASE
zAoNT80=`ha!r%F7Eaewgb`Db8^o>}`{P-0<#5lr~kN0)UizO^T_b1u?`<T-Gn_q-8
znS9ZDze#uh3R9-^K=<!!%A6kP{{74?y1&zmXIA_@YJaozJxaR!05k6H<5YLA()qhp
zcOR^AmvrxWe~7#H1T#4add1zlXWYHZ+jNF4y7vZ@lkPpm%q~N@Hhm-Rm=$sN+AqZ&
zbC#JrmhvmUXRX*6OL^MNUqUJR#=tiu`JQzF@=5pp#`JzPAZ4i<qzziiCLH=jDf-41
zgXD4naFAX#%LZviz05*2NLRf8A7OdsKQLAg(r|N#GIYexy%B0i__i<a8zaql?Z?l(
zI*sG~dz9|+_}MdB<M`P#MvqvxdZyQ#B@2VRYd2^d@8^v={|fa?Z_;?VG3zqfLuJ0z
zqABOdqi6eZhOvzpLf+RcnJwQ_K8QEaxFLpCJZ^}oaoi9~D;_r_p|NdjyC*k~8#5RD
z-gHls{(AzI&K85xjiZ%4sdJ9#aI@aU=l*^%%G{!-?_4nq-KuAIJHO2@|L=Hy{3drN
z<h5xW4{VoV%;Oj63y@6)_E|ly-G(u15y$oO(ic6yQ$D$7{|IECO}~2U)OgfZ&!z#_
z`a%r*RM(uQ-!F_=pXK}Lfg<NAIE0=reR@zy&Ow!O4z85bt)EfGc5zfh8al<XRE-TI
zEZRGc;|phkrmy*ouxRf%k2caB=wWZ~G?c&S?8vx`_Gdi)T4rp|6Ikq7suX)bm6|o5
zzoG7M2Xffk$nT=YPK>&kK-5Kc=MEf?#Cgr!uZ;zax|lfHB}jZmQu^|eVq60wk!`Gd
z2cOCz_NFy3lA_F0uxavQ*$e+}huBl8MVS-qr;O>fSVj>XsVC#V%U{L6jX(L-0%P$a
zuIoQ#O#cktRLU*(Q^xeu=!;@Vx7be^(})U1x7be^)5__O?7l6}q2>bzyGtE5l1~}a
zmhmZL8q?vfh)%GdGN#c7|2D>S88aHe4q;OtBXmno(Jd8O+Mf~9VNJ-=emPm%FDFa;
z<z#8Uf-LRNu?~d*ahOfdsa=n2MV3ytyRT9*$<pb0RlHUXv+3;wkSu*0Zu&tm#~Xxq
zFmZYa=4N<PIm`wXWa(gDf>9bZS$ZOhl*rO==<*;-50u}MEd4%mmB`ZL)A;RQlcje7
zD3PV<245me(-o~mmVOPOM3yE|_>+>Q4}s_sS$cbb0kZUHD5uHN^vTQEAwCDyOD)($
zc`-O9OH1CEEIm!~&SqY2tZa$oEs>>{NrruO1~y0uWA?%1tH$i&m?eFN<o~kHe?=+3
zT#<wa-L92PoH~^(X)?$&_5=77ZP;ODm2FvL%#tRTI%9vJ3$gzP3YA#WbTCC__!QCX
zy@6a?VM&ulow4`O`Pua<KS{zktR0^x;GVqKri|*;KDcXUriCYCBNCc)W@erpZKR*u
z3zBB%sr_x@fRou)&W61+{VG%DNXlL5d-epFD`0*40DQB{v<tXD{kOdV<_Xx4Ucxfl
z33xdD6K309z~kxnC}6&Tr_wv%3sYtX0nenrL9nBM=hOF6z)k{QNdJ^63j}OTUqES}
z5%6ldm)Uj}@OpYG!7c*+lHLVP%`6n~wh*;5iv(;oZ1zHCae^IF{|3H#fhEfIluWz|
zcbA4Q@=j6N59fzg{Dt%#bXcRXFk7u*1n?JV5@KkZ75i57H3?&Tn#Mg%X|S-Y=^FQ9
zq}cBbPw{r3YPcb*YuE>Sh^nD#iyEr6gt&&B#&HdKjeCuTYbkr9V)E8Owz7`jT9UoV
ztknKB&CHEu|54*u_MbEcEBXYu#93#U&MCg-t`ke=5`0-zI-jNGb~Fif^~<GlO^l&n
zoonW~oUFCWn|7m^ujurirYG3pAnS4Ju~!de`dW><noehvzN&F&Q;z9h(|Co^Fp4)O
zt2W=1vV^mT0}(>#CdA%WGvdZ#t?g(O2K*FLW&%!^XcV^gR1@x!Okdb2*5x*xzCexe
z46|D4)<?GWOpSWS9ZD3->S;Qjdd||R%bU81x6!z}$)TFFHSTJ9k?r1A<IX0TU2}9l
zt{A^R^RF?@1?X;L!XeCkuUPM&u`Ty0d>t|ShvP??W@+R7x{1v~UjDgmVYBeFABf??
zW}#>QB5v=3W@+z+IMry83H^|s&n=?S!|{aaY7y%BBXMeP%lT~IqcQAkxs>WY7Q>#F
zSxkLAhTScL2!EAPu?v<@T<TcvT^R2sVQqs=s5*EB?DxAc=NF`*eF@9$#v8QR|AkUR
zPmdegts45pSobca`&n^?eM<MUW8HgOzDn)Bq_s09%^==KYI(}C;!}|~q86cL@0;f(
z9Gsekmc3uZ#{z!+YL>aZGOt+L-Kx$5VyUZDon5hlJZYMb><RU3&@8DcKvf&iY_oq2
zY(Q${W|tZylXF|$pk|3;Fh@3FSpU^fsht--B&zD|Dx15#ZtlbjP!TMwM$3(C=OSU=
z(B-UxzD;w}RM94;Z>vW4Y5KOjWEi(k$1~elyBVL#TD9ltv9$`D<C$37hrU8<RcbEQ
zTSA5Tvs8RPxJ@v=AI{^wHOYVO&HSh0`&lZ!pQYmaq4+Emw<_cNHAA<58sCo-=aa<u
zWB#qg_hVh3FuvbEoHP7!<NHawgv5>begviXegviXegq#K-;Zti5Nj0+D-t*2`w^7l
z`w^7l`w^7l`w^7l`w^7l`w^7l`w^7l`w{%x<NL8)A1l5eYyTwi{gmL39p6vHV;L_%
zHUBKWpX80>`|<jd#`j~H|3rL0*7L8#_hY&Ld3--gL3}^{+gf}--ba7`)A)Xp?_Y@T
z$8sMQ-;Ze@7T=F)A1}TibAG(|e$4rwj_=1hw`Q&4ef0aswN}O1CB7f8|4Dp5uDbI0
zerntL<njGj)&FvQKc(tctW~1(zYyP#I{zo*`?0=%cYHs}ERXNUz9^6HM_eA?kN97R
z@5f@GZ1bPQ_fz;2#`j~Pk00NUEyKLuT6{kW`l$GRLeowuGn2g|z74s{2J<;#Hx9=2
zK8mrt5nuP*mGV{IUcl>BLfIa5T@v5P!z?Mu8JlszM)5E`Z?nV*8^yEXy!QesH);~z
zL%sJRxfc4|d$n?XJrcbSB#%T8^vg)%epv)Tzbt~F9}~v!fqWs1`-(7bUs}Msf}f#a
z30wFMGK?{*{)m4<9uG#;^OlgugON4NCzNjMGg2mFkHvfLNJjP(6NRF5XUZtu8Aa)?
znu{#@Kx5be44ahhOibxsfyAvGDUw-M;8@r@qlc;n50PTEc<rpJ6DD|F|5<oAzhn-=
zuhq&z7tX1@4Wg8VE^K!h+dwRI;k+tdD+^t?od8<suEkBw7-!#T#`q(=jv3?3Gr$<<
z5xsKiF&X1*lsd75jB$oAQKuf0F}@UO>ckQ<#+g%{SVG1)g{V`H$r%4E5E$dk!b|mH
zuQ1J2g3B1=w4Rk1<E&+XG5$v+$*IR=j4S0dV_Yex8RHirqdN7NjB(al#u&d6aDXws
zUjUh!F-|G!)MGNnl}ybTCsL;#lQB*dM4B<q`qZh%WQ<d@GRFA3tgplve~|TQ#<;3a
zGsabYnla8vqfR|0W1L8xSVG1)kvg%2jB&QFj4^%~Y8YUQFT~=MQ;*3QCs3yzlQF&<
zkUI64jBz4$>M<GPMC#OIGRBG2smElDb5PWYC1i{f@x+qfpxUxikI5M4tpUdPW|(T^
z)MGNn3Dl{_WQ?npYsNU!)Tzg0jH{Mw#yD$JCzg;gPNYsOA!FRaS2A_#F&X1T>eOR0
z#$6zF>M<GPRX}xe>M<GPti3+cjPVF*>eOR0#yPU;)MGNnS)V$wgp6^HvpTVajBz4$
zVhI`JMC!y6GRBG2i6vx=6R8tR$QUP5Czg;gPNYsOA!D3KomfJ~ID0~!SVG1)kvg%2
zjBz4$VhI`J>_K(vF&X1bQzw>?G0xe-Q;$!=-Hd%8MmA$}9cFCyQO4$iC^5#FTw;t<
zPKhzj%r49AiVIo8WsLE8Oyp`kLMN6n#`(>;#27ylAY(IYi80Pbml)#$G-F(VW{m%T
z?7az?997viT-{w=T{G1^T|HgZRo&Aw)18?lGs!?g7BYbll9)h%00{&MYeE)CAR7=M
z?2$!-BA_5{sK_Rp;tS{tvgJcSMHCcK6i`-KWM5PS<h$?Z>8c(y@kQVFyT1SbE^}S!
zIrllI&VH(^>psu@2#74k1w<C(y#2%$<Ggpr7UPmFvKU{E6q}>q;Rkvz@5Dnb##4xl
zEylM7$e9&3oL-M<G0v#iVq8FEF-~Cf;|Tnhkr`q!egG3$(8efnh{gDN#KjilmjL8U
z-Y#r@+!W;>VljRt^G6orKbQOq&^((T&qeu%Sd2f+{E@}DbbmK=znx#i(tV>XiEwN&
z&IGX-UyMLxG0t#oG0y!ETZ|LL7UNti4UZ*9;R-3gX))f5D4X%;L}^Wn@lz00=lKk8
zRcjBwr#_1pO5SP>?};-|-Wm;88D6X53o{5G)6PX%d(XyK<SR*i%6JwD{*|SJ(CGRv
z@ciOmC13J3A59z-EDcK-_2+Sse{Jv%E58NLJf%_U(ZEE69rW4@kk|PZ#xEGr!dAiB
z8RrCokpdEqjq{m7pDSPIM*b00Iw6>0=kdiZ-_OBJk72`EhXw|-a;)8S_Ci#!lf1#Q
zo#7a;U}s6mI)mt1Fk4bw$6`gh<k$tzUA=6b5$syL0CAynxrLP7a_8exSVhkQm{a6a
zM9pbM3j%#P*6YxDZ?K1y*5|HRwZ;ezD8GUN2Apfq>tIFj7Qk36Hg<A2YuFV2+GZ6F
zU)_g~6c|=gFMPE1&lpD2nSCu%9?J%Jz_OjAJ_hhac3Xg~b2o-Bd@8#efa`n`0~0<i
z**vEO-4370E<;M_{2F}>pUs{KP<8Gp0X*M2AdSBetqNZd(Cci?%zuzR_BqS2v%?qV
z(QLq3i(L`EBq?JZ{!j~F7BIm%nFYKeV9>GB0Iv#|;w;8cg|7*i=G=zq3}2UVndz=t
zvDgUTC|r$(%odyR@Xg%)=;=kyVix^Yj^7d&JL55d;U5KD=Df(#{vyq}(ko!_LO+pz
z8x6kJn}-PqONr8XK;QQ0mL=>=I9xe5daF1ly$Px1ChrC|c7&$gib?R1w=xVL3(Bh?
z(S?!s_C}-1YZAUpgLgjWq`WqfXJMw-iE7J7DoT6nQEmCCM1Bm?Ebp(l50sBigcC<&
zl2G)QP*~3F!4>BFn55u@GFN3iiGd6*mAA9?v$-NJ)9}Mwl9y}vJQNjNAz{8sH_S>I
zs!muG&!DDCrOYr3pM<|7j$CV0IzvX~&$<}xuhhNknKyxsS9)3(Ft77C=CaZ&z;sSH
z17NsJx$V4w0k4b@fH!z(TxFyH*DzUJr7yLFMemH#vK^uQI*X?HZbwD7kKugfEPxI<
z&TP6XmKq(^5;JiK{*1pl^L8SBv|(iB7SLwY&&Jet3@`r`(e<OTG&)AQ188V{f7H{l
zb(vSzee||tjE3*S>gX7&;RJ@QV;c>B9i!YaPQx!V&v*^D;-1zqLBpF+aK}UqUy6m*
zv8{%ynA?s?8t!J9gA&ev9_^eTF1CM!@|^W(Nw`$HXE?i{)Nonjj&eMT4G)zR+i|(@
z4-=4eJj`FXT!8D46AD-4SeWP3afb^Jmz2=CiP?@2P<1AABd-)tb8h6qUnQW|`8oID
zY5{%D%dB*bfC1;rY|dH%W1YWpp&uz=f^!chGCWGapwq!@M+=zZd>8Eq*9n;B%wj#q
z2$<=-!EDD0nC-mAjdGlTInJJJ=z0Njxu(%0^Gl37F?<BY<xFm5n;V$c-91LVhnxLm
z_X!}oj1i}iu*`f)U)u3TCN6bwEz{&p9&cy?cU{0cwi4|*volKOEiRB7d(NB^Me^<z
ze1cm?wrkFuhlp<8=9J~;nnE2%MEQA#2>5}>3-PD&YmQoZr-aQriI>Djd3K_>l$Uw4
zxxeQmvhO3-^gf3PD({{UH9One4}(?SLs8bdlR5WH<Tx^}cQ%?|o|gz&56^~v41Y)N
zF>AgNj!sBBYx{BVwo1q^dYi@f<Ckb-fNK31f^c2JEhDa0lo?96+|sp|xRg#!$WE!P
z!rdg?&;Y;TbbX?c?FU@47b~NfAAKq|UbQQ6ElP9#h@D^UZe`eT?jooOu$&V&0MuJK
zl+YezKW>ehlvde9+IM4We~0p_`<0p6mo_=Roxe#WW^|wr2cSTse*#KM^xurnWPcKw
zQ~kG|hVkov>~uWp_J0R4R{x0~!>gYDTkvW3ABvck{=JdEwSOvNoc?x{lkJ~}_+0;s
zAfDR#_d$HV|09TZ`?p7YvHx3VVr={0!&QF&dnmcoe-Yw?{+}Qw><<wx_n(7srT-5I
zclW=DHYEBxQBJb|I9zM?e-5SD{RXae`=3Y7TK}Q=oYub$Qa6k`5BZJ6sL$X65c^};
zGjr6n{9}*$5lS@NQM=<(qc-YYMot^`Eusyh??8KTp)vYiM&m9xx`QP_ziRXgEX$}F
zqkkcRX~yVNd5y8b7@gR_fRPxzkwv4%(R;~NhB@$gHV6OK8<j)55bRu<EEhV_`TJL4
z=nqZGW02u}awX7VicIgXhXE~DWP8QsKr0kw{pmA5YIGj1$o0mslp_>*-aEs9Rw)WS
zOt;awT2a+Y6RlBH^ID14D(dw*h>ld$=hcXgQZ(TGtPXUvqOsm^rma&n!5c+%jG{qr
z4AHTQrg%^Cy5kg0^PVGGuV|+CGSTshW_xcEouFur_ZOlQ70vYw_UI%<^F52`WJL?S
zEYT^74)ofIPF1wX3yC%;TIzKXeN54Eub1dFMJv5gM5ilS>y0HkL(w{KTcR@+t@q}1
z1ASc4Nyaelne^6})6R{_6sI)&3NjdG=O>fpG3bQ9*DTD`*_z+*F6HQaT9N5FHK218
z*<PBZoU177IYj3vf=mu`enye!b#Qb(t0?qNW7_$Os^0WopbHe$yk*S!IYqtR6!zpo
zMSY&foS#=T;625DeL>M!?>eF{Dw^PBS<06b4SGLh%f75=iuWMVMT(|*4`T#6znXL>
z;EI`EFKhUkrY(SC9?->#4)k8)b(bhw<o%K8QbkL>y_oYdMa#WASo`IQR(jX54_7E!
z>)pYe-%zy9o6DS6Dq8QYVq30KbdvW;rd_RQgLf}Wxkk|$9=~-vuT`|s<F{t#Hx-@j
z@r%3jTZ+!}mUFDHQ*?nhhoyX5(HA^^^>+S;qKiC!MR#7W=wfdt_U{Homw8_xx>3=U
z-Z$9J?<l&~dxtfASJAh<7g@u9D!S1d$v)hq=q9g^Id4{UtM^@^?<v~kUBh*Di=w-{
zTUf)bihk%7So>{??(<IN2;Q#f0q=OG-J$3g-mh57CPfc>-(>CoOVOj=`^<T#qQ|{o
zGVLx!PkY-j?QTWSd2g_kdlbFs&0)?TDtgsh!Iu3<(VO0%*oS)+{n>k*egCndcgtro
z=TDOEOk8gy%BK?EpUju=7rr9S=ammA+>k7<<fT8?ON~@{9pQrt%~bgWX8wgjJ5_$4
z?R!XJHdTI_CI3>Pn<~FZ_$!58s=S87^{~P)RX&dJ*9xnt@(V2ak)%5xjjW}NVLiB5
zNDQ`G9t}*z%piD2#Y-bR$w;5e8Xrrhc>543x32jv&*kMzzL4IkR_j{Vl0uI}*R1Op
zhq0<_)^)4^l@jYZPJr!D*Q{&30F@H!I$nV4nsuGvd=mwzu36WK0#w(m>m<phx@KJ`
z3#b}f+xU{|I%UG?XkBfLs(5vM(LDu&C<j`*E*i!6<NEue>#L(lG1_v7u<PQ{C*vYj
z@#?xnfU0<PT_!+Pyt=LspekNnS8m1bsft(E)dEz-tLvMin4&6PUDpXv6|b)U7<DA-
zQ5CPQ8%FbIsH%8%eMhpXidWZvc6=QLsESwD%>q=#tLv63i&hn{uG?z_(?rFqYg0dg
zs(5wXDL_@cy6&oys!<iMu6wF1T2;Kdeket&idWaYqc|X{;?;GZq^OEl*G~ngidWYI
z0#wDT>%lbN(kwEz=4f~QqQ}MLyZQ5QK+5Z0;{Jvs|6`<dFKuVoa86tUu&nqvfa$Ej
z>~|k3z;>1#0&rNnPQ%870G1cnAs35_OE7109?gNnk+LH7DTGTmBRPTlcpzot7!x8Z
z8}Tux`{xPwwBcw(2FcwICOnn|Q9*3}?q4V}y&X|%_d|+o?_#1~CW;)LtoK{y{FS1d
z_a>Ho_rr?Xyd|ii8>XtvnfD&RHtYV4BG+5bv_}*bypu2*-H$42_jarSJ*KGW&11`c
ztH|@}EamY;k-tnr?_gf{grcf<8LxXX;c+k2yf3jWPwREVyb9Bv(LVHgKVa?8YFeK+
zhGjmdX#?I*nDco>W4#H?`GTSe-fm2LQPH4x4g3C*qAA|%EahcI)4VUSWv?cR9D2M4
zV=1pCd``k_BYiA~@Qp-@gI;Mr1V<>k-%hxrMquRmi@y8aL@R;euQ_Ig(fxiR$61-{
zUA_cq$z)d6rMKTwptPcWyfudc*@`~ueeGZ%N726Cti?cWiWYcZV$Oo1{k$Su<|o_O
zvID&rc-_ckeizifNPjVIhoIc$_B2Xt29u(7#I*EwT%7&M)VWwjm1_aoySGZZhmAyM
zDl3pQMyoQsYw`5kJyub|+X>IR-P<TidIN_7jZ>8JMzNz46q#Pg=1)|V_WrsEXj?^=
z_Xn0aNm0i8!x2D(ifoU^<GLp+YVjUs+IEUsy+alP?V!l<j${o}6=l7aWkAyu<-8@U
zfu<{J^RDLr%}|v09%k(yQRI3D5Y1FnFwz0LG%J}p5Q9|N4>eS~=Ok^KV|$kjL(=Y=
z)9_AbZ}&)6IAjU$XztrRlNHJ6b+Datlf!xVFT~c~lZ7QQ$Zq%iq|I2b&O60EQDLjt
z&5tIBw;{>&eoC}&vf=^R-i{o)1<4V!fU+p;f1$#hxlTTL6Q~SFZC>|*Nt-#mN4TI5
ziVBvN9Go1!8w<u|6&A?`9Dx6gU(D%w9IPeDekSI5K6q}qZlBPP``Hay{16-_Z!QeS
zLQ1(ufa&athpck10NZ&o1u$Gd)+yqLb$NsUe8=PfMhftpjrd_*?h_C?2jORWxnDrl
z8J`9iC7|X!$x25H=ymqsE5iW+ea`+YU@HLw&c1BH)&j;l6EXl}1Wa%~!E43}7<Asl
zE2Hu@0;V`$<Tc|2Omog)+r|r+>735yOb{^J;hVPdL;-V*`fDtEa(OvNXBNg_N_n2W
z?<kDU#n@QogC(2c+{bGc%A0S~xtT3kB*1olNN|XNtn({^#R6RC_XJA>c+P&fb(Hl@
zS?CPnMp<4aDOG1L8{kj@HRok~A(iz_S+DadUKEw}O<AAw7E4<p+3>cUjXqr7{f>1m
z$D6wHN%HP@g1h3-wMO}Lc}+eD|ArQlJ{vAUf8fFnb6)=~$LM^QJ*+>#!Mi};s@}}-
zEo~D26?XQvBHyair?T4HC0sd~@8`-LFjOCnrFad?t|m$Zc$32xbtbZ808H;W6R1m(
z?cG3BOSBF{&a8JhudA!$FxPvC(=<%qIrDW8rSRm17c&R%@P!wjGmz4Th}vnKl#z)F
zE4BFwX%+&q(u+pz0gmMF^#!z)aR|%c2QEJhfAVMi2V5`IX4u~xzy#Bvs5Y}C>COi9
zvo_2B#nx!P(~31(+bQ@RfbATH)mz(5Xo{?JC)!fmT^5Dwd=?v{wucP7=bVn2tL-Tu
zboRnX)#eJQI#qPBHZQj)no)BCj8APZ0mGb22=*4x>&zyYpW_?B5sqZuN5Dwu35;KD
z|I!>Zr_Z^bMepBDFx&Y)+jc;XYL3gD&tPh6%cVanorhW53IS`KCows-!v(B!`2M+e
zgcQBrITur1TPfgp=WJ$MCEx_-8ythx6%sNhInS}Qb@Fa=gHapg`gk$X_C1VZ&fE(F
zTib^7@{&f?9>6vAofAdAFUw!^bv#TC>#z^nsxjolI*SY&?%E^P8N<4AoMY3W_`$Gl
zVL)uh*&CqNV4&(XfVu$J+0X_sOtN{-IT)&8JyKfeY(jg7^$MsuJ7YG74VUq+p^3ji
zL-R+V)l+&tYEQt(IbX&o_AHRyWH?6?>?go<KJNhRF96SVNq_?cWSvduPS1gjxu1dR
zdJYocIai?Q9=%nB&ar4!&q7J5I{RaSdKL+&IoF|8J%<SBb-vDe77OTe9%4O91PnMM
zF%3OS8=LzO+yi=+Ny-Fg6oI}}A2jM0uszGmOE8%A&tMRH_iUFD{|1+GZDQ;F?C4K8
zbCYC+fb-*W85CeTSK*S{WC6A_5)G(rCm`#zaw%^wz;&jgowX?fJm(_JQf-HJ&R^(E
z$5%mZs;u6sGm+VL6wqaKo%v<13^t(apo<v%4T58jUUQ^TTQ6^G%~5zoI(%mTdx+0}
z2m81>{Ahc>F=#NoT?{{_-u$gI{Mcc9u(X|*kZt&Jb>_-CpCMR3jQ0lD`4hqMb<8q;
zZ}qa|6Y6|%92(|tnY2%F87{(`ZhV%W#8N#0fq)-~d<{*g^NjuQPfM+>myH<La@1Hf
z<*VmnD^8GAWPp`3Mr<4YzK4tTArv}da$AVe2%R~Yt`Xa{vA&wK^9F$J+t`v`=Y=x>
zrU>YBsfjUSsuVWh@N0a;Gy!9s$4>+J$XHf6!8wQ5%oH%_?8KCv#;!-o6leJ906Pnq
z>705hz-%dCj`Q#-0D4Spu5%Kv*;P{JJMPB-cF%4^0Snx9M=vu*%oT@?7o*?&scW-R
zrphf8KEAjazZzqSg`1HFSoL11voT<;*^xhOc?3C}Y6UOu9~dU1=nR8l+Q^^P`7nyJ
z;`p)~`SUs-iE;6WeSscKU5#sO7X7EF_>{2?o0Qn2?O8;nQ}(aYw#{dr@;33)OMQ0?
zcw*0L3!=tNSb*?6o8_icefOER&4%pU%sp-t>PqZYn}n!z>fv9e?fU5}5VLol*Nk6{
zp-G&SN^^G3=ug^@;&0-juOst>D==?J650hODHD%u13o3C3frGqXN(Up1c^0z?Mz%d
zO|E?m*KWIZ#Tq76xE7(Pqh+m0^{^V0WlXw@*Y1<D{yZ|-P(YnH4t0*iR3o}Z0Gq7A
zW$Tv1`EJVJUhv9^S7Y)L3*t6RT*6}ZOJzAnEH`IzICJK4Si9r@%FN@neVaxkZ9ZZo
zF1jYJXMAd`*0Xft4lHM4T+YP1&IE?q9Dlu{9TV?a3Op$#YY_G<gDZ^0VB890{1<uo
zOGz0;yEkdylmxzL+woD4UP|_9O$TbpIRBs}ubW8mt;DNIdE)_H&WUHU=GT&$#z;*(
zjkEB2gjWt8wZurkX_qE1nz)KJzZv1>#-ss8+?TYj>`B^-WI|41GbjXu=q{a*l@n#4
zf0`_4v(`=gIoHAcQ8}2P8r$)yq~#7vHl$eJjLZ2{RL&wT=hMlema|sNIVUN<1UZ2i
zsB<IK=<K=4Jof}UyPDJe*<@o$tu)3T&MBLr139~vw0|g5R-K3?#gh+6s_>=)ler1B
zC<7kB8zCH?PPm#qn30@}%>q1gaOJYqMq*~NVd1q-25weT+<3#RNgKX%vc1vpLEOs{
zvy&mK;)H*j4cR5xK1}e^iBIkUylZs%%E^~Zg5M`J5REVrbCTxW6Ch0#MQnc^Qbm+_
z@<xR2LO$FUu?v%#r;u;T=OlT7A*mPD8>vSpGYQnzNS$x&z-wQPQcq518Yy$Rz<JYE
z>)`QS8&I^TW7gN5v}-bEm!c@$PF}KKJGp#<^vX+4YxHVc86z*bK*wy6F2+){7}x1y
z4B}NGV;Dwor7`tYF19CS+27?Q?WOqkO<Z)<wuZ5z+&rF?Cr(Vxw51SpPdwci{B_g6
ze<(6O(|~iQpLHN%Uf1-T>2w5|c&2gRnLlkkKzCz1Os9K<#P1tduAIJs3+OqIub(j9
z(`R$hKHq=~rhkV^;)ODQRbt9(OBVrdn`q~aulD{bfJuoiwsywZVNw*szX&k#T8`&-
z2|3ijrSJsn*gnEbjgQP6hi{t1!bFZQO>hUl8CUVYd^MynE&QoDtH`$8Zq32CtVgcI
zMb9A1PSnau+}^7VUT;j@hU@H8GJ>^sEUzSUZiR{8k>9k5Pc=qx?T-A3ocPo@?aRt(
z{7sYibc=3=b;i_j?CQZS{33rC_Hnai4V=bu_??tkDBnrw%``0YL!w*wbUra8mJDY;
z+&!mD9ZTg`IF0sjYLwq4l$uIHYKlvKHt!?J^9D+oX=4{kO(l=A2~xXC%DSSY7`Nfe
z+%%pr;4DOq_a4P)<Z;cSQD_|g9`Q#Q@BI@7dg(XuFx9Zri>&?B_OD^>C;nEG6ZMJp
z$Af6mK-+XwWd0J>rjC-Z_**rXCFC%?Wu~r3-HjaLZ#8vg_Cki~Z#8vQk@1GCvWF08
z!QJ1W@m}iEmbVcUf2*m>GkB>9a1#@+PG5>Y4S%btYf`+-q`%eFbsa|`41cRUte@Uj
zmbDz#PahC&$6P$DpI)fv$az>ly+jW5=geI&iIK4%!+9Rxx7_?82<Oa?FowtXt#{ib
z%y+`pds#Lr&*S^nd!B@OeBXMnD&gypXuU6a#Q$riROW2B;{P=>#%{s-6St+AZHf%T
zY1t7*W}NiY6w|@XIEN*v>0oA@RH3GWnQ<LVaSQPOni=opaXEjzUWaztJVn!u2pLJ_
zc?P&QGs(V$^(F9;ncTvQ)pRhkod7i*%xo_}O$Rem1gPm?W(NUkI+&R%KurfTI|@+K
z!OS!PYC4#iE}&+#tN+)`uJ*HR!=(Y*uv;s`>i;z}r-fick^WyZd$h6#MxsdnubFv*
z=>L^pr+-2==~p*=CEZ5<ubG4F?NTV`(|BUa9Nf;Z`hU$VwAf2E9n2ikG7Tvzbd_1$
z#j)6k0b_agT%_=Squ`wRQ2@^s|F4;2>{Efn|7+&h0>kS6HFKO6k3x9AbhpCBT%LK#
z{ux$Y0sdbzPq$0v0{p*bp3zAy!2fIJ_Yzjq!OXKQ_@c+piR-bjGtUWVE71RI=J~?D
zs7w97W?qnM)O0ZOS}R9F{l8}3=%j;E_5YfAtMe!T_5YgrbM8U__5YfAyM^8_2MYB6
znt4}>9t(hGz9-Eb1VB6gD)mh9cjsWjVw(;pr}^)ox(xik-UIZJ68*ns;Qy7)o9Wa4
zYX<&bIn;A}`hU&9|116&bA9@M&A|WbD;SdbKK;LD;Quv^(iZsi|C(t}v~i0c=ugAo
zW#Ipnr7Sf9{^3QTe6Y76cU{PMjQ3xV)W)Rpfq1^`H8b%4%2Dv?|1|^uuaeKF|JTgZ
zNoN@Tnm+x%0(nHXPyeq#T|`-*LRXpJCv9Hm`ai(kFY|2D9)>;c`7AgC|F29N>(l>h
z<`2ozB&1F7>HjqY|F29N^bg>5@c%j+X;Xaqf6c)ED|hxZpZ;Gnc$8$$nSPDe!T&4M
zX8ZL2nt3bf?Sbp&_^UbC@c+u3bN#asmx2FRc7MK4|F0SNf91K}1r@IU4E(=x$<Izy
zR<nBef8~;%lc+4?mGJ*c`=dvb75ab8!2j!0=+5KG%7Z991OKl_AQk>!b0(LqjQe58
zFl5{XvMtCn7ma9R1a6o33_giiuCXE685K>_dgkG!TzbtsxcVYQ$PJ$>N_HJg2f2%W
z8DZR+>FqTGZ?9*fdmU|<*=z>hUaOceU-tSTi2{M)Q)VRtZ?CM%^y%$218=V~&!~$X
z&Y3K@L%h9aPE6Q`u#hj{+b08WuLOpFKSnJBZ?8m_e`pB^-d_2gffHB!b0iWPO|9OS
zfw$L>V-kFNd(FVx>r&(}e0qD$7^!y7mg&#uOv2kMGur+r=7hIb-kE!SdV9^l+bi2V
z+uz952yd?+1)Agknx(+oYaeQy@6+3B#!8jAQI`7j_L|8kTIsLgb@2Aev~_-gU4XY&
z9vVK$f1GO!-d?W&I>V>8*9^S9vc8M_S23g+czfk_7yI;Bk%6~YqAUI9*mZb&CHl6X
zV-4{3N_3M?Z?746dnMZBQ|KxKZ?7y9ri1*}WYscAFdZaj<$_^4Nc`Oh2S)YP47|NQ
zh6tbDUNi9aN?`c(_L_mWSNdCpw^!ao8I)pRI>?dc`fuRQS2OVT%B|YPn?VNNUO7`;
zkFlxn_R1Qy?s3Q?7llUmWr)m~jHz+A%Hl-C4hZK=?#ddsO|+1?m2&2MeA-+`Cn6vP
zC5`&$fin=g;@zlDZ?746dwmNa&*S#?m8I#ZDbM5f_EkOy%I4a*Eh-^l<ex_a?P~+_
zlX-fDg{qY-ADY6o24#6_p($KzO+2R7X$t4S6mB*PTZJ0anCM|f+h15f6*n>%@-Zs^
zeGD87`B<q*1+Cmx@~G3pBM0V#XkFVL;Q$lq3bJia2{(=R+UDs46OH%U_Li!9Xvwe{
z<Gr?hW%-M8R(@)gZ{S^VHJhJi-vS^ny7SZ97*@Ny{0sr4jO2~s$Iw@IZ#fK+chLp+
zfU>A!(Js$jC~p-zp22n<TYx9m*=Vl66FO9g?DBkiaxFx5dA^4cE<|>DK0Ub>BD*}F
zo?HvC%VQyq--*r@V3)UmBcOJ83^pcL?DUpLxM7!9xFC^w1|1Q*yaGJA($=GcS|I}k
zcyj#_0zN&t79zVmpLTf#cyi^}nCa6luK-W3#~`Ea)01lfc6qF|VV769F_AhAuwyhz
z@e1(dIvE?nr(IqFo?Kaq;nS0AA+pQ!X_r@kCs(G~K0Ub>BD*}Fc6kMOa%Fw4@8LH{
z;e&R01$c7(CF>KryaGJAUd8%omsfx%SFMkBd4;DGnf^<-DHPzzmFvOw>B+Sa+2#4m
zS$kxc=O4w|VVB4LHSF>V@Z`D^YUubZ;=+QLbVnkS|7Da_fL$Je;nS0A0d{#?0h#_i
zh$_G?kI44BIlZvUBg*>p<XV7T9+B(QlWQTe%kwF;RTyHI_g&y2c6kNZ<uR&b1~&Z4
z!u+I5=cqnCxfWoTM_~B$<XVXA@_gFm72wI0X|_*Ku7$`h&!=5p0iImBAY7lGTnmw1
zo=;D%1=!_1hATXuo?HvC%OeW?t63lH@}2^!`t;;lfL-46KsA3j>x=C2eA?v|;K}tB
zr1kl1LjiVqoY?{2;mk&Mc|JY479zVmp9*1x$S%)cPZZhZ`Sj#ki0txwdU7p9c6mNM
zxfUY3JpX*6$S%)+k8={)<@xmFT8QlOe0p*%M0R;TJ-HSlyFCAJ=7e1yTR+pMC)Yw`
zm*>-yYXNq7TrEwzylLo5&g4GCmpQJ=ncNU!msfx%S0>j@e1jC=$(1Xzem6T0Pp-^t
z^SS}_QTFuqMqO?I@Z?%WoXy?3OO#kN>UVH3;K_9|{??yhf8oiMey4LLv(^`Js^H0$
z#&h)_as1)QRRHbs3h?AAfOdHWcybj$ySxHCxeB0NUICt5dHbpF!p_5!>v)#-TaG6@
zxk|R(IYsc~8r$W)f;RLnMHblQ)xW^b!jmh1KG*N(I)f+I7PK~JzJ)f`X_r@kT^^(A
zd1i(uR{^xkE5MU0fz6Md@Lxv8GwO$N^x?^MTPCugB~fD9sITFb@Z`ET;_7lYfG1b3
zkDSTdh0PBxkZ73c$+ZAauBS6U?eYrn<oZp?KOW7q`N1c0$&Zmg34JNRlj{x4PrJMV
zJh{epc`rpd-#6MGV-9+9Ex?m26I%P)hqvs2OT;d(eMF97!+9JZ?IUyCjcS+I-X}oq
z^4k05?ghI%K9=l`E2Je2yS(;MsrON`&G;2jT8ok2$TG)O_`sCE6E_Wbj^-QDJniy|
zt2Io!yy6-S(=M;LR>QQ*D<0F%MOo+bi-Y&l{BCxS#)s*ZTlv^0Hbh>f%rM9HcKjU<
z8zQeWWR!c>#khZXb#F2%6dNM1r}cNtD>g)4uK=|n@`ks{^M=?Ec_Rd<4UsoeK*NT}
z>r1`BqQ$(=@3l{0(KPS#N3^hWYToCM6rkpPexJ*=Xd14V_xUsIZE%;AuX%r_$FQ3B
z`LlBJC?n>5{!Tewq~?A8&XS_$eg14oQS&~3m)vw@^9p<g?eALrF238;ywBe)_XJjz
zn)ms0ihMFs^FDufDL~Ep{5=Hp6=>e)A5bn}4%EEQUl9ZVV==Dm<OnhEEB)GL6=L33
zdZfUx9&s!^+Il|jV`|=4dMtZApW(#3uk=LrX8>y6S9&V@djK`>D?KgQ)V#0sOcn$n
z8c*}S(zDqTfSUJ}o|g%zIec6$y&yo%`$~V1KB{?N=|y?LrsjR6mn22a`${hhQ1iah
zD+1KKuk@+_HSa6ECP2;mO0Ubf%q-Bnuk=P?7VbW3-dB1vcR0GB=6$81=6$81=6$8V
zNOP|AY2H_YdEW)-(6v6z`${nH8x8brpXPn=JMM7h-00K1uLSeHNkBLGH18|HypL%#
z@0*0Y9b(=Wz`T$1<kP$_fO(%xgHQ9m0OozX!1QU}7r?xaDDBg{FMxR;p9U<S=6wOo
z`+nDfNkY-LVj6SiEL<Vxef|k$uF8B8cPal;F(As*ywAT(!!+;nFV`^5`}`{;?227o
z7}}pk+r+LetjM}mySlI=$BvnW6-$k<T4E;FeLnu?%>9V?aTWf{y`{~_)2=QYUj8DY
z@<(Hfg(F?=(fs}xr*P{sugue~E*zs_+SP?)HB7s@a2pNNt}Yy>VcOM&<26jXx^RMq
zH=*EgqJ}R;GsA5)OuM>pl7?wl7Y<6;6}!69VtXmd6T7<7Qt6)B)s>btw({{PwsfeZ
zs9jy@Fac^;S6VJW?dnP^ax6^k>Pm-8irUqcju4=Bb)}U8)UK|yN`Ttcl~xN-ySmaE
z0cuxQS}Q>9>PklnP`kR)Q3BMiu5`2jwW}+w6QFi=rDFuBU0vx|0cuxQI!=Jv)s@x@
zn2QOOMM%54(uv`*=oXe27OTyj^9lSPX5@P?qotGGlYrz~g|9hf=2Q9_gm;kWCneM5
z-3ad_q1@zntJL=h&=Zc5d2b2jj+!%n6-CNz<sq&U*(W)ZhJ7{OUqU{vM|D_;kUF?E
zLw=yq+u%>fuesg=*wt|h`?RYIU{^OA84RCxbph<^zJyrQr(InDyE?gb`?RYIU{^<!
z_3va(*wt}lT>or*2C%DRJ$w~i#b2?jE5WXg?X1(Tt^~U}DT~G5h5wBKs?)Bn1iQK$
z5m%>OUFjJ7^1%kKzl4sKU{}YTQm0*AX+s122FteuyE@56ySmcFY8~jxF~gv4_g1i&
zdCV{vCKIX041*p4ddx8B6`;oqgW&@7m|-wNfF3gpMhehlhC!bIJ!Tm63(#YR!6*TG
z%rF=&K#v&)0|NAzVX&0|J!TkeEkKVM24e*1F~eZ206k_HY$HIA83yA7=rO}!yZ}9B
z7)%hL#|(ps0_GTb9y1Ikm)r3s!Ifi%!8|*GyQLg63=WoTddx6bDBr+(%rICaK#v&)
zhX~MPhQVS1ddx6bB0!HB272SrV}`*pNzr45!Jz{5m|>td4n1ZV=#4{<83rpPn;tU^
zh8{BvPLl7S2?bJe!RhjK-8g0#d^XIXKRI(O<~+}1hQawRdzj}j!{7qFyWh<4Eo~Cd
zV}`+PMXsJaj~NEHOSnUh83s6Jcs;K6dCV}tF+&2w=P|<o#|-%-V){I07~q&8k?r%C
zVSr<X_aSH2=P|<|I%eqem|=iphTJRM9eW~=>`i74JF#|U>mubQMAT11fdP&gvQnEn
z>J<cJtKeCg#|#4;Gh|s(hJ*L)AwO_=0e@UMW>}tK@7sw9<}t(a%#x(bF~jmK{}fV&
za?G&2Q*ai59y2WOCXY*c%&@$>EDAklSl&YhUXK};_Y|PV49jx`=rP0cyxe#+LysAj
z_Y$DT49j~9&|`+>`8hsz>oLRfJ_7WZVR`=&O~&+?VR`><0zGC}J|H(5*XS|B@^a~q
z9y2Vj5TM5l%ZCflV}|7;q-Z^6SY9bWj~SL%3D9GP<<%8F80s;@@;bTIZ!qdSW*Fd@
z;ZlrZ&U}~i!efR3ju|ql&SQoZ95dvd*uCcK_=VQdVQ0`_8S;+KBE$H>j$?)$T{+IN
z9y9FdmM1YiX4p|{JPFrpxG~oS=rO~NVUkUc8FutYX?o1CqgQ|)Gwc{H<6lD)&p@kO
zIc8Y>s7)gbIc8X0AiGJA8CLfbpvMfW`wP%xhSdWE=rP0UfsMK6F~jOX0`!<+Rc{q~
z%&@vpQuLT%b&&u)W>`H$fF3ifE*7B246927=rP0U&|`+xWs;)D46FK#F=*s@%&@w=
zoI`)|JZ9LrXS<BJ95XCWY&{;!*ZB!Xx;#l%h#oU64+_v@hULiu^q66JI{|vku)Mth
zJ!V**B0!HBmUn39{OK{n@>E&9dd#rAqkt}>TaOvC0o{7c@C*d|c+9Z8UcQz3k39{K
zr(MEpMQnWHqEUw~#i0lJLc@72!*~Q!4+n~=n85G+IQohnT?qoe7mNO=w?7ntpW<uY
z<W|9cxYXpgc`Uj60Y?8TxYwnoR!=~Nw7jQHO|vfnuz06PO>bk^u=YU%QZodYASYHM
zF7-9siOkmAjR@Nf72pq?3rL-Yxk^uz3@M%qu=HF&isu3>Jr~gON8ExlI2UjWN@+E%
zD^gYT&^ZH-B-WMLmk{aj#fEiNk@1FT*9;((WB!!UW?PrGkchILL2IqcGi;1u-NcWp
z(|^Gq(@5QoDy(Z#ye!3Y0oHXLKSE00%$REt*WmeGhEsQ7U)rTI$1E+(ygkN#lI4?R
z!Vg=9g_*a<NnNJ36<*%h;~W_U>*^5%9zoWcfjfacu7g0Bd3(I`94^P<baNyAW>3P$
zpYdP%g8GD+w<p;r;<?HqGjC6B(f&Mx?=O2h0j6~(A2hcYU}Ho9rU=Md$Kfl--a&wC
zZS4U}72sJN7(;tU0iks`!88F?>lzk4T|mst+q>GE*akk9+Pk$fY*?S*E08%Y1j@|Y
zd$h6#4QAe+CkV`Zb~$1nKsM=D%*@*d*+tH(4CKM>4C6cm8@bS8FHK80x<gvZNU<$B
zBe1xOW3dqf#`3cLNa6oR!5MQ5fR`3#-af`&0A$^J0Ioi^z_4NU+yHQ#7LP&(5SJEa
z-hRry8iPe<-hR4WGLxCNpV3JrGjIQ1!nXAhJY?DpX5Jz*Zx3bW?dJ<)QI~7Iz^=R?
z*MwF-r~b88jzra(a5BIfomD&n)U0hz0eGu(H-KL2TbzkM=hgu9S;w3P@OH~t0LskU
z?@H0i%-iotGnJXQ|0?w;GjD^LKNlA%GjD^L{~C}o^EQ}yHcy#(8_Yb1TA6tp%=|+@
z%FNqf=6{GGQD)u-Gk+i&ugts+W}cf&nR!S=$#MZR&%$_7C?D)?csM^8kMVvGNiLHb
z%)AX|o}(blybWev@(D9<gPDH^Ny^Lvc|^+019cH8GjD^L=XJ`=;|PiU4(@Zx%-dk*
znWoIV4QAfOL?|<FgPCWVGV?Z=`8v{+nYY2rb7w0vZ-bd<PG#n8F!M}PX5I!fKN8m|
zGjD^LXHI42Z7}ofzB2PRnE79#Wy;LkVCK2x8_c{7W}ZvB!OYuW<_A$~gPFI%%-@O*
zH<)=F%=}EGf|<{lT(&aq(~x1vxC>-kkmoow!evCp9EQ)}3B+=Z4av@^Xqx6R4=?4?
zYv#e##~?y(xm;1Q>ynDEi!h!;$;{he<_|{ql$p1|%)f;k!pz%X<_VOUx53P_DrM$v
zF!M6csEZxWm@HVCc^l09c6h!PX5I!fPoT`a4Q8H5nRz>A=Cj)&$F4|dG_`u44Q8HS
zgTl<)VCMO?q0GDuW}dU9%)AX|o*9*yx53Qw&aBM54Q8HgR%YG?Gk+M6GV?Z=`2=cI
zX5I!f&yAwYybWfaNSS#X%si1Y^ER0IHK<RSc^l09sX)ri+hFEdpEC0{n0a2O%)AX|
zo=BN_8_YbBGV?Z=c_L-zZ7}mh%FNqf=2_+sjqF-PvT7NmvSL;)IHUO72$Pw&!OW95
z7iQiDGcPQ<F!MH;`FoJG-pKMM%Agd}X=FLlT>lN+`Kk?Oo?BIzc^k|;XG)lP8_Yaw
z)Vdukb-Ad)%x6r-)VNz^ablH}5YCv~l{IdgXdzFP=&kUX<vJooF9kK2c^k|;??%GR
z+hFE@3Xt6iIgdxqVTQXJe|kuow{-O~s)wX`OSjK~OYsb0tDYfDQSi4_&k&|~hOl*E
zNuEb|hOl*sJaP4qy?0i%afzkK-e;A)Pm#UP)<QmE2z#Fcdry!WLc*tpknnB_Pf@87
zh`<I3pK6fsyvXF)p%0SqsWVX{NO(4=hg5ogZ+AAsq|);Tl;<;iJ;Mvz`532Ex(h1(
z=O|04bQe@QYc+&QcR{7|)@}-w?t)79kY)>&?t)5Z&Q_t)T~O&PM5%NaRQi)ZZAO+^
z7;MajU^>bW+-<bnjN)BT>1z<zvOn7Ff=XvCN~OD?()Y$=mQd*~sB~={sdN`qx;E}-
zM4-~&$7M>TyP(opYpc<6G$z>vm7YZ@N~OD?(!b9#Nu|4>(pid9=`N^rEt6Eb3o4yR
zsdN`qI#E`rbQe@Q>r*P-1(nX0wHqzZqGT6T`XbgRRJsc)eLP<{lS+3%rE7g8&s<RH
zS|6!&7gRcDRjG6w*A$c$D%}N@&NNr3bQe@Q`{x-gXR;Vj=?}0zq0(JY>Hop{NTs`=
z(g~DGcR{89Cy-L<E~s=OrP5tc=|oDUyP(pEluCC&rE^j|q0(JY=|m;$#A(QrG1-Tf
z1spO^>5Nh;-366?2s$QIx(h0uK&f;WRJ!*3YFz7rN@to<=`N^r_BAV1x(h0uwJDYE
zf=VZ97b@Kam3|nmQ!3pBl}@Box(h0O6_8TtE~xaQfs{&jL8Y_yUZK)mQ0d1bO{sJj
zR61u?sdN`qI_uk7sB{-pI_G(;Q0XqHbfRs9N_Rn}6O9up-366SG+wB57gRdY1fkMh
zQ0YVyg-Ulpr4wx{RJsc)ooJF!=`N^rj>Mo)=`N^rqA5b9yP(pErU{kqf=cHIDwXbn
zN@v<^q0(JY>0B*yFjJ(JGv>WAYutw!lVg-IxglDrc+hu2r88NmbQe@Q%MmKw1(nXs
zSzh;D1Y{34sB{-p`V~y%ZhbIHY*6VgsPyk6PN;MjR619C#$;BZ(p^yL?6gqnE~s<?
zq|#kb=>kZlyP(nqkV<z!r3)aH?t)6^?MJ9|7gYM6a1R$M-365{*+`|kpwb7BEz40j
z9#7!Cyj4b2x(h0OIU<EhcR{6}50EiWWy49OyP(n;B~-c#DqR4nbQe@QL6#p6;J=Ja
zgGzTnrEg*)3wkL^Y*6VgsPxAWCseu%DqYU?nY>+O`O%3PiH4a}x(g~jhd80qT~O(h
z05axn%+HVAqx=mj-367t1M`zgcR{5~_jxAexG3lQhI<%ukV<z!r8A+euQ0sj2MAc(
z;Pz4&kz?4f9>+&vWRClx%X$bm)<U0vn)Oxmq0ldPs9yap{}rx~mUkMdr}4a77?nB;
zQCY^n5v8>lJsVl(xXM$A>LHchzN+;?egTt8Z(prpQt9n$G)yYJeXWK`rMDl`&P6Fy
zdJa_jjVP~&XZDM3em**#G5I~*!!!HEcjY^|hiCSS?`ck+*)P5)KihkFX21AeRZ6%H
z#T4JyJUqeY=?T6bp5XJYlIMaf3nnoy-AougJi+H(8+;2<>7#MI>6crd0kEDyg?^>X
zFdK9){*ui1J3~gL&$^g*u)0T@(n??&{GQf7Ft7DE7P{Xnz_cg`>JM*a^K6TPp#BH}
z`1OyO_eToAnqYB$Uy83+(n98!dhL(1Xp;G*5iJ~E!=hGiX{3OJMXlaapUd4~8fhW(
zOEc^pFlO>Ds5H}K*s!S8Tbh+)$4!e`y``O`^R`8;-qOyJlC=ggN2S@4;#w9f8cODu
zb}inCxX_|jZ)vyOZ_%Erb<Qk+2AOYBtGBef6wqr?tGBd=044KF2bB2|b-<!lZ)ru)
z127ij%1$boAN<;86&AI6gGUMs8y3}5f=64wh8Z+1YV`(>WpC$u4vSj7!4uiX0J7HI
z_?8Zy%DxWZTA#$g1W!vg&uT%pgJ-f?y!;9+lKH{2*<k=x>mI%#eqJV^W?hI@1uqEb
zwW!q_{6YHIXHly+cv0Sp4OrCb4PKIzv6eVhd0D^&>tq)2ihx0jTD`%m0;X7tG0MSf
z0;XBFVLF4?Wn7fZ58f!uLqld;J7YwHH*;hsFS4lB8@wft85djQF@eD!1zcvm$kP5I
z%~3Kx0GWR=8mwe~05X3PkdpZzI~=YYCG!K2`QHOlGCu&B&$L@H34CXwWPS)TpYtSS
zeh4yOra{R35M(|tP%=LRnNOr-eh4!E5+Eh>Ly-A@=)feQ=pSMlGv++Za*A5Lr4!0r
zl|3Z$OP3b8cza0ZmoC#V$^6pg8YY=vx<bNfA@j?jP4-<DMY$sD*08>E7G79%<k&GG
z^UKu|GqLWk;cv!VhR-ZNzJvcV@@=RSV_F_wz8q0KB=gH7-5c2!lKJJW%e=COWPW*!
zhDqj^$7+~let8=WlguxV(=f^W@^}rC%r8&S@Fo;oo~U7x`Q>djOftVbNyFVNb5O!*
zA@hU9_F9x@Q6v|f9J^;&yP#BXa=Mj|M+`VQrq~uma>2<FWG#y1f|Da~EsErVlVf3?
zMUh-^a!d&=isS}I2&h^V$qiNts96-r4OR*0wWzfhtQOE`z06A22pF)w%;u~WFxH}6
zUvQ*=2^K|igQEltS{=-Gw16oV75IX60;X9M$qkMXFw>$^UvR8|*%sygg5w0tu_%%o
ztQRmB6Ut?mBAFkY7@mgWu)MH?vfMd5^fS!pA(<bX>}~{--_O?}ATtj#pVQ1cNc1a|
zX%fjhNhmitj<3FY$e4FU$-K9Oa!1XWPeqY(TlqOhQ}#*5q^Nj}_m_~5s!<*7yrHmS
zZq1M%X!H*Fqhx*vGM`&m$ovpwK7T7JnID48zXC~0=7%8jxn*o2^FxsNL`vp|AoDpg
zO6G?k^H~qyUiaazkof_~e6~}_`~YOWT+QMi!2iYo37H>&%-@7KA@c)}`TUv_GCu&B
z&z=aGAArmkKr%l7nJ?K$<_942S$bN?{IG75*tJOJhr?td4U3vVVUGaQqGnLoE5Np>
z859l|khQ286pj$!TGR{*M+)#PY6gXU0z&H`^egNaP_?KT6pj*5vz}z7qXqO@)C>v-
z1oT<d3<|drFkn$LDBN1WSc{rL;TQoEENTXYV+9Oa?_mdp+X$FqQ8OqUCt#XI&7g3+
zfSDFGgTe^{W?R$@3MUGfWAu>B4=0zq$`~CX^TT;I$#09ALE*uY&9JB$6gJ3w>t?o~
zLFQZ33<?`$zD3QTutDZqzb9yr`4-m@)U|c1)1V*f+S3tNwWt{cb!~#0Ma>|nYcpG~
zMa>|nYZLTY)C_{UHnZVdn~gqPzJtbE)C>wwlJ6iT^TX5S>w3^g9f&Wk@UzhQ;R>IE
zIqxBvAD-{Bhdm_o!wdB8PBK5drA^{V=7+Zxxq5m?=7+aSSjqelWd7~ATFCqmWIlnC
z`Ou=z@<~L={19Y5k&^i#$oz+qQ_1`gWIlJKD`b8MGM{^eyW;@lk-f>xVLz7yGa}_K
zL<pH5g3M>7S?;KJ5Rk3XAoD|z`7BGy2uSAh1DAK=Pg=<Q$_#r6*j;%ntIRA(y0roQ
ztjzL13DVKDTCqkeI|ZKuuq|o^Rd$odrL1))+EUqFro^?V8C2Or2Hvx%8C2O*Kxk1j
zs4`bT)v978RvKi!Ma`f}gUq)sA!v~K7Bzz^^K*Q`IKtW!ZLaJiV5CLOpvwNGBneTA
znn9KQy9s7n)C{T|koy)oyxgK@P-VIFXQlNp3s@mwt@R|9OXY9@>nv&pRgRFN*IU#K
zs;m@nyhY8R$|?aTSkw%vtgi6E@FeRwmbOlA^&6DT4?*Uy#VBS>N(l&=AA-zhl#uxy
zAoF=AP79e|?XZg=fMv+5okfO~%&&IkILD?%p@C|*%%p8mGpJf?JPFrp0CfSbwE=6r
zI!v;8);SoeYLAo_TAR?`YOjE*Ma`h<a2fv^ns^>sl@>C;^P~0)YzQ@jIvZrZMa`hj
z2AOYBGpMsc=3CSZ>THnt)+S6)=Yfs6Cz;=QkO0r3W>BZzDng5zL7fXFrD{<#sB@8k
znnlf^&O-$BTGR~cTr8l^qGnL%5&;7iHG?{rHa0gkgF2T<$^?s=L7n=HF=+H$!1gRJ
zm(iadlKEYGw#$eMnO~XMdM1{L^%KtABv~Q&?ZM?TD8RI?!X=f-0&I(#L6z+UWG!k2
zRkj!4TGR}xOcCH&)C{WZ(9Zb_Eouf;8f3mj&7jH$$o!1S1_+st8Q|I_nO|8i-%2TJ
z26fNuzX9=S(G2Q7+RkI9EougJA5&kAcI%^M_p!tH1Yld#4C+3v&RkiG3IN^fhsjOE
z`V+zN^&4@CXHhe#`-D2bM?)h;&7kgmiXFHpW7hE*T!~y`5eWH#$ZwztJ=6^9{<PHE
zzb)buGZX35n{aPFs^#NA`=wcSbc7&r(dfyH-Ct^ii|zr@DmZW$OT;OJfxn!I)Povu
z?EqVpI9OUlpU7j;q{PBH?~M>P7`TC{iyCn0R)-yDBo1kyMFYLKy(Jbm>N(Ibo<(C#
z;|kdQHuMQ*pdpwp<G#^JdoBL{?A;G_ykYaF89s0h!MuJD4SZNM2Zm}Dq=sk}m_xJ*
z%pqC@$ylqvydw28G)uG!%qz2(Fw8Rv=2b<;tEuV}2s92aw%X>UE$E(V6_`V{3e2n1
z*CAs=tH8V_#mhviz`U;G6omg3t%7|}RistGaHLhR3Sk^AV@yM<K*GPor2Tib3ViIf
zNUMNhIT7)%X%+BUo=4zrK|Ag1@G%+@GLrail@k%rD)<)b<B5p>i&_QzH4$kQFdS<Y
z5a@{rXce#rjS~^jDj=d(K_~vE@Kr1Qicds9t6(QYMp^|7Z(gfl4pL&R0*(c>3Rs?f
zAU^oNQE<*&4A9gn_!Lm2Rlx8+)+%@mU(yY&0?GWZYZWX(U7Ob`;7G(;1$*MzF4ihI
z1t8WcxC9{9Dj+i)YZb8QSgU}|+=5oYow!I(L{O{X=Ri%Z0+z8Qt%6Ttl$u%v?_fxp
zS_M2#-P9`J7T>H^0WS*WgT2MiD101*VlioakJHAaAzB3-g)L|mY>n^Hrd9z_Q>%bz
zOIih6V~=l1tKcI@+mcoR8Pld#0eAM6v<jHk)GF8?*KJ9wfZcCu6|^8{Q>%bWeu!29
zm-G;=0;&-V(JFWa<1|F8;5ej;Rsol-9DF6oH)PxeHpZQ2S=tzpGxxz~a3N-cYivk%
zMn%(f2J`SzF1=<RTzw@X>;a^3MaiyfXcaseVLmVxaHqnFh|i!uO|1eN@W)yO1Y6Q7
zka<R3>~PLx!A-3K+BU~p1q4m40;0`o6`YKOMpIR*;InuJ+JaUAXRE1Iz>H0;0^XTF
zoK^vU?KZUvxKWx~1w>7)0-~l?!6m4#sa0@2(3Z3ccwJMgfT*ceK-APKAZltA5dEE2
z0lzg_wG0xp3W!;`U}zN(lc*IOX%+B2f2>tN(9|k;8wgqjygM-{mo>Bsxc(bhwF<aZ
zW32+tRIF9N8ny1J(M7RV0b^?1t+F_=N_IgQF48bVHEx?|As;Exi|}c49en};seOo6
z0q;h!RzU*yr!8s~aBci3Dxs-WKq;<Bt3Z~|hteuI9?dD>@gG_R7XCz91&rFFRsmH2
zwy0G=kB#DJcyn3>v>pB6F$wcb^yY803ciM1u~xwk03xjdhGVS)0%{dd*&yH0DiD1F
z9<YE`!FG(lp5cY<%+u5=n2%o=u~q@ws|PHoRlsiwJzznt0yU+Nv<jG04_HvEfQ2-*
z3YG#vtAJS;Y)r1;brBw-Rqz_}#aacdrKwf$5VFTw1=_est3Vsa0~Q4wu=p4<Hnj>^
z>kzGia{!xK1+(xIGuA3#DNU^cEt3Z<s8vAJ)G8p-0~XXOV0}%k0=BH-Lzr3xPqMyP
ztKd7VFVZT|`nZdzRiO2ea;8>+*b>KD1w?wlf?5ScdccBO1?=Att%AK!LsP4OcFVC=
z0YOu%U@}lstAMDfRY26#Dj;fV6>w7YfCaS*i0DK3PE-s3Y8aO^4_HvEfKg4Y0vZy>
zS_K46tpe@&)wq^g1x#yd6==^Rtpe88)G8p-0~XXOpaMZttAMDfRX_!Trd9!s#r1#%
zwF+3f9<ZQR!8=H6Y87y1n_2~|PY+m7tAO*Y2P~*nK%@sOs8v9u2P~*nK%@sOs8v9u
z2P~*nK%@sOs8v9u2P~*nK%@sOs8zs`&;u6KDj?DW7St*r(gPOMD&Pn<wF;P~2P~*n
zz|}&n0_vFL%sH4@sOKXNU*@<9MuM2MSgU}^a=?OG1uQ4lDqv=t*A3!#rtIk<S_OTG
zv$<P&CSMX82P~*nKmsJzDp&)MGnqBkDqyE$tpWi&U_q?{0g+aLfJm!AK%`Z`+fS@j
zz!Ma5z=B!@k}c9IScepwqwo&e@ON4TFR+!7Rsjk3oS9%$q*cJESgSxlq*Xv*^J6dk
zm(CB-Dwx4U7PKZx9HLdQ5OJ|q0S_VMOx`YReta#;k716q3eIKz8_@%572GWOcf^F*
z{J1~L-#B1Ft%5t4Khi3Y?(d6>-;Q!ZtKfO&h_nirAX){x;9)V+DqtAK`}lxX0rx|!
zRX`AH6>zOUtALLs`{4>1hNf15gD9Kv$3$sOt%7BUinI!7D;;SSNVuU@AmN5qfrJ}c
z1zePy*DB!og-EM_VUBHdya8GTjEc1i_)0#~Dv;w1kyZi0Kdn{3;|;M^0h#|utAGuU
zwF(Hfq*XuyF48IxGEQ6(L#sd@Wj3o-z?2W6RUpitxFUvD0nJwbS*-#&-XN}sp;e&A
z8{jqpos6{#SVg2&Abg>ir9-PgjyH%aVrUh}@rFpNK#n(vD`IFB$ngeoMGUP1W{b57
zgoli@3gmc$xFY_CS_SOm=Cul#5^EI@#99Reu~q>=tW`j;d94CD-XKnbp;aKq8^jec
zv<moTqppadRY0Jwi2qKjfZS+PtAHd-Q>%cBrKwdwGwh~T0n?~e&^+Eit%CS?1GNfd
z8e**iUeMGkAZltA(0;M0RiMWka&o)@u2C_|kyZg$<-e>|z>^D+Rsq*-tX05{MOp=V
zydfvY8{qjKm)Ozq2D!I1wF-E=VRKpqJl+s#6-c<DRUqMpR)K^YS_KkrXcb7fp;aK^
zO=u>x3M9<q4bUo(a6_v=!aUvptpbK)tpc7%h_njWy;!S2xAO6bfmQ)iVyyy#SgU{_
z)+&(W4dMeBS_MprwF(Ggtpb8rtAHTZDj<lp3J7AY0)kkpfFRZ?Ac(aJ2x6@Qf>^77
zAl51%h_wm`VyyxKY8A*LY-knmcmtLf*dDuiydlym;PD3eR^br_nfZoRfgEpWyh@Sd
z4GcGrH*kEzrHDe&a=d}b&EpLaYC?JPK1FUTw2#)~4RAY+6g}R+?Hc`TmE#R8gj-XO
zH$aXL;igsrx9}FU3Yy0o{wu8lj!aXlfR*u8bbP#lS_RzCAJi&{jyE(0DAp?2gv(>C
zg7|pDKh`RUk2n0CRsoMUL|O%$$XKg@Al51%h_wm`Vyyy#SgU{_)+!)~wF(Ggtpb8r
ztAHTZDj<lp3J7AY0)kkpfFRZ?Ac(aJ2x6@Qf>^77Al51%h_wm`npy=s-VkdQkmQfF
z3YhJGPOE^WeF&`rW{b572sW=(z(uVtk^WYzfa|KMRlws7aFvZY&+~W#v<le6&1n@#
zd_${%t0&SbV7RGO5Fc-#RzdT41GNhHz1q|&AZltAG><n>tALHy;|<g*;9lYGkmC*9
zo6X}5%*d^eCdXO@tkmX?;_(LADvjd})GA<EazAJuZ@{lxu<)@~0gpFCS_N{vA<`<4
z;|-BkfgEoTmq^em;MZ`hRlq6vKcrQ_$L?6GfFRZ?kmC*F5(!!ba=bxYB0;Nw%0RJJ
z0s9kc6%fQ)1q88H0gH~c3J7AY0)kkpK#n(vOC)F&a9}qywF-Ea0bbitYOGZdA8(*m
z0q?}IRskvTNUNZEya8GTa=bxYBK@safj$Y>Ygl@9d0^hWR)LW1;t~m31q6SmRlws7
zu~q?(H~e?B3Uuyg;CCIg3J7AY0)kkpfFRZ?Ac(aJ2x6@Qf>^77Al53-&CTNt&?;a`
ztW`kJ)GFZdhDfVGMm*9g;OT-$tAHyc)+!JoDRGGetpb8rtAHTZDj<lp3J7AY0v&N4
zZ}^8=1@ZBQT=RGXv<i4H>7RHq9#3y8AB1K_%zQ(uV0+OG#wmeOYu6oRB({g6HJ$@l
zJ4$?7Y(M-6TtX)X#>+zWznY1u{)HdMNFa5}K+;~0zYo0sZ>s;FaZA9B|8J`Q|F~O%
ze^dP*-Yvnuss1KE{BNrN-&DW2CHObhFK!7)w*Q;zH#&{~m#BWYroyj=VgDNAAA-5)
zG1_wY6EXgb+7jd6OP4BJWc>GH;t*j3vmuNy8&8(KloI%_8UHJgD`xzE3J@{=49AQ=
z0U7@<;cvwFvt^NYg6Rx57=PwzGX8V|6Eps7@0J+<B}h|A1$rl7&L-o}LYj>K5kO%4
znT0|5X^k^T#3x302;=`}#K(+3YiTn6k0N`__-o@f&-iad#wO#>T8A+Hp95?%{&VoF
z>%YzTv%V(d&z22g{GVriG2?$L>-#W_Ki5OkI{{IX@h56B{_Nin#(zK5&}96#1N#><
z{sc|NpVIS9#-FIk_!Bi5f1)Pi&q--A{zPQ_e}roPhVf@qlktB6bX?5%6Ksj`XIhi-
z*Pcg=KWl3;{zOg2|5aSqWc-PmjQ<~jnvDOuKwDz`llZ;YWc)d^O~#+~H5q@-bCdBW
zYBK&rO~#+7$@mjB8GoWC<4@FN{E3>3KS!d;_!Bi5f1)Pi&k<}g{!D8!{#-3&{Levb
z&fFU_n=`o&b0)_KX8<s1G2_qVnDJ*hG2_q7Hm}<e<0X4~2;)BnaW;4Bfl=ZR#(xgt
zV#fbifSk#!G2_op$Be&#i18N?G5!J~#$Q0h`1AG?GyXfVwBKT}k@1&oyW`t{-U&`b
zip^0-;)Td?vH|#UUyr;KyvA1Ek5qampuz-ROED^9{23K9{sJP#pTOqFe)umVGlcQq
zg^4Wa*eG!b<9{gPV#fbG04RZDHf(;-`BOB^5#xU$^GA&TCdt1OCd}ps9Ysj~A&mb$
z%pWoS(*1+cL7W%RoM8NE{uVR-Oc2I@E&>tb&v4B6b3eq4KS9j+bFDNO|3y*xO~$_+
zQ8wdGiqe{l|4KyttBgMv<>ndx7g1`&_%qD0{Tcp_Q11kciW&boc$*Y4{;xA{#P}2Z
z(~LjOC1b|_(=58-oq(@CKNRCnC4q?XXE^pwpfn)`4gS_UfxhRYpus=%PVghV(~rFq
zyor7B&ochKs3G=FFbaU)3E0Vzk#_=C5i$M@$KDC90BsO^C%79R_D=9LK<u61ZGhN2
z0kg%7e-ZEMWA6n003X6T0sFXl#-AxM<4+JX{sb}OPY^Ty1e<647l5yfy%U^_R>$56
z`0DY)F#g{_hnkH4RG@#3@#mS=rgs9)Q|z5Urr}>;{9h+Sg8984)0i_CV3s4spR4j;
zX8bQk+x|<&pP5+q75JMoR}%5#R{WQ{T$Ay?7EzmH{CQ=>_)ECK_)ECK_)ECK_)ECK
z_)ECK_)B;b7BU!r315mC1>-N_2IDW`2IJ3g%=pu_(Ek|Y&%$Ew1bl=4{|4iK7P^Jy
zMaG{y=S%qC6MH8(7f2X?swl|JHyD538X`8HX~Nd=P7=yZZYbmb<0zT;mQe1fIrD`m
zQf@2HVQ0&QXvzCXsqy{-TWfrfUqEab5mE=YX2=gj&cvT4<IgR;1;+oINcwQz3HUA1
zWc*nVIn6Qn+qcK8`34z(cJPCYKa2kr{x=3FX8eDExR~+h*W8EjP9WJf>z!cIzZrk-
zx+dd4d?@4Z;cof=Z^obNs>%4*&>tKm8^ZXrhnr*kCBDJ<bM-`wKf_JN|886zdnX`J
zK?5@W{9bJ`{zOg2pDuEm-U+xP|DN$*j6AY8nK>Mb8?bC$H2=qlh#7xYYI8>=!8b?G
z%8_>h?mH=?3yC2=aCtBO#Ek#ppnxOBU(zGS|1)F}BgX$CfY>_$zlQ(sGX5=SPVAk4
zAofl`IyPqf*`Jv4Cx{t;f`69r=YwJFoqz+op~?6khf&O#d6XJ6{)~#f6Yx$PGyWA4
z?UZ?kcLIiE?*yFV&3h;Kkc>Y|i@g&N{2k-}d9*5K{9j{3C}{96dMDt0!*%|@!}!<G
zpNR375sw)Ev#~_}&oKTv;{PS%&jvKS6MP=Q{)Tq~-b+S}I|YpYTf+E91U+;D=$&9{
z<egx&F#c0(bh!Y=f3z_EQwNT~+7ZToK`$1Lv14n@`0xJ-j093I1LOZR9&7JPCdpv`
zC+y6U3Hv+zlT4q7gk&;v6rNF%X8LWsZ}<?#{X-4<lS2&pQ$q~;Q$q~;&Dfwnbw%oK
zG)WBlQ&(m$WS9p1sjG^NSNqO~5NLegx7w*oTiynC=wu)@)Sy3gb^1~yGz|Jv*Q9uv
zNhbrT>pG4?7zX`!U^AslWxkcpiA#a>82flESh4#~Z&PI0Xj^!MkshZ`s~x%&NRM+4
zLcHzJr9gU|N04>sQXoC9gTQTDxZX&QcTUCS9-JBQMgVDc!#EfJrRAva8H9V&lk9dF
z28scFda`(*Kv(b>mflW)>CmM>dV2x3Lze>SDFWaj&;-~)fa}nuKzgbG&!J0!^o{~T
zhb{%u(*#r<x)exH7f>@?5%N!@ceVFr8|YFXy<028YCxZ!(?YPJ@GKTVdJplAXe0_d
zbI|4qq5(ZEuMa~u=~p*2KyNdQ^AhQU?5kPmr`h6z+Zk2^`t(AJLu88E@AM%p-$sfW
z(5Dx7aV$1sz*wI6IoO0iqu{)G4?ufv8mhO`$3P_>CEj}gia!=Fu2?)>3Z#$I;!(%|
z;&S3rApMj*9fQ@jaIKMkx?M82!KFa@8J*NNxD-hLUc$D+^W*7;O9AKln*bUv1=<!a
zKGaA*U-$v)QUm(*3vx~9^mFQ8Yvo9&0e$+7&bzUH)PO$yR_B`lYCxa<b1sB=r5ezu
z-)^C<;6U5LV-_3fcctjD0BGiW(#$~swDYf0&y?cs989<r7{o=>itnJhGz{ox1AW9>
zxDrLcr2v~Zvv}zwq`{>Chk8!&8r(h7a4CR4#@yoT_y$VDrNBZA$^7Es6M*1SfP~<J
z;&H42E(N%y4lGW?tF1I#3b2%=hR;8|s3afkZRrMdti*VX_u)tim=w~#cdwa-O97@A
zFTqQ?G+YWuzT#ytq)o%6z-4H*S)^-GAdko{?#=4qQh+F1{0rAKTng|yxA+6@yl0d4
zWjJ2$6+eO;X}A<%+SuayZGrxfEZvN>2}SZhX}A<%+F+6INYijBa4*uP6f@rgf=dDJ
z>}kaov^EWw0?awHSmSkYDZsSZ#fSNJ7%m0)m^7!j8gXg36kyJ|#j`o#a4Ep<%`e`&
z4-i}mP^o=End?6dmjYb!vlHdjtR5}}xTNPK%Jfj4hD(7bkoVDKc>*heOMzwR&g04Q
zgD5=>mjZO74g>nUc{3_#oGJ<!&YN7wG84}O4w(soY#s7!LQ=qpy!m5%`kzEBSKW~8
zjEW}iFU-SBxfq*yaCH|V#H5~UO!i^Jq<%q!(O#O=r(sh67J67|!(3<6a5C^!<S5GS
zhm!#UqgZ5T;beeSnZ;L$;AB8%9(8dD@+J$e@C|TV8cqhDVj*AP4Gc~O2#n(Ws3i?2
z14LHwP~IJ5Cj<6&$ngde8cprEFAXOH6n`qd&Y6ajfu+b{6t`uQ;begGXBOvkZsBBr
z8SUaI=7f_0-m80ypJ6NEWPoj+UEIj^2`2*|1)5X*HA{h$fvZvD{Ng&^IN)S}TW4vJ
zGQnv$86a9&T*2$$WPoU0vA{0C$v}wuPAWdmRR<>neL!av-{MUeP6k-tMa5TPrk;kA
z0bX};k%nVwI2j<iviKak4krUd-!A4@1Dp&H-Bf&mJ%W<~qD{q%x&Po~fMx#Bu(^&{
zwG0wW>WNvoV3^bs4@Niup_hh}frW@DF6W&eP6h~!;$a*bI2oYB0+`hEw#uLs(=e&$
zj%eWOt7$kH;O6b*?I8^(1DvVO$JkUj8DNcC_l?m-q0x02BJ(C=y19R4aU$Xlg!3l%
zX*V}gw2+^bXnHoVxsK?(S87ihwa){m;begKr`mZ0a5AtAz@+m42m%hECX>zsEOj1W
z(qVwLB$$o(`eT^e%&In7E_~f+tHS`34g>63$UL=+&O&W)7(igZf-$5D#xUq?;!mBP
z3tGE+8CCy2CbhL&Hk`?kbheU8dM-es5bD`ILTL>>4P^I}aPS{YB%z+27jl&gp`P7a
zs_ywI5;sGrXZMxmZqkiZZfZ4+g_aXHQn_h1zZd2AMQ(Z<!%C><W(Y7bxNozmG@)<X
z+hxn@G@)-hpiJSyItlf*h3(8!c?R2aY#u%ezK3FpJE22)_$Xj|;dL4J`aDeN`CVZa
zJ$&Y2LVqXH>>^F*^B~ljv$aSPCl3>P7UC2;5toOLf_s5Ls51+LjmZ@Jn+P`u^*nqO
z(5h1i^*nqOu$Id87{Y-(d=zYtK(U4`lZTH2ZJdeD<>8}18%GoRJWS}HMHzPSMy!xL
zd=#+O2BDsZkAgP=E2B}0mxqsnYgi_I6y)KffTbA4Kd}_}D9|!#LZ62TJ&|3^Gbel$
z5M_%mV|nFaLeKi#qKDt+dH5(`%Nm4w9wzkkK3)+*Jr5rR9oTS166$&QDA4+7LZ62T
zz1H^<ZUT9j&~rW5#UFD>;iG^kTU^fCVM0&j7LQ`>FrjDv8iaZtJ_>GPed41a4<7|z
zWPS8ekcW=~0;4zulbwf;g0BIY#d{EyhmQgxyU3^9JbV-oWs5GS9zF_)T)5u`f{y}D
zidXDLTplL$L?x`XK4O!75EJ@5Oz0U^nSoo%$~=4&?1GLJe}a9JhmQgRqxdb3G<+0j
z&uK!RhY3B??Bewt2lyz^o|90|!$$#YbBlSl1U?Fg+KV6OJi~;3Ph8;@?;wJY0-~^Z
zHS2?qf_;Fh#V=v+<>8}%iq*B^aMlMCde+`s9E%N>hY3CP{rif)!e<^n3OKU^MTavB
z9|f#$>*8-Y?l7U}JdZ72i_bhv=!v!|t|x*CJ<+)0+Z<__&=ZX>8k|d*&=XB4o=gN2
zdZLNN^NC<WPqc0EJ<bVC=!qs3t6VKGq31{p7Wo=I4-<N#DaAI93ry&VrWFroPMFYh
z1ZNf>;ZA{%0;bI_4lpN7=($?(4$!1!O5VI)W{vwWZ*q+CCO3o->UsDmU~<jGH%1;N
z^em@#H#-j>1<Y*oy00Q2dwP4LCN}{1DBwE}o4fUvD6weN?%-g+g#H@D)t+E~;iKRo
zfV|19wMCpN_$XkfYd>N<d=v;Ep`M2cy#NyGdH5(0Kteqa9|ZzPsORCMfVZF8F6=yf
z6kN{Ie#`L$p)T1-sOLeb{|0|;j=~{mSY$$9BcYy$kAk^~tdUU9gHS(_O*iTFqDDeJ
z4<7}Ls^ys(J_-boP|w3h0fEhroA6&o#xrV%arEJ%;7TU4pogNwv{75bE8(NyZp78(
zZU7$zuK?st-Y#r@q%mO8Fq2Tv!$-ke%uhl+4-@)sj;MJ#^Yde3lpiC15{rTf{cyz9
zNT}!Gqd>ZU8%m<#zLfkv{0lP&P3ZIRQNV=OK6iM_bqENd?vBVYtc1EdGROU(gu2@&
zKnZoXU+z#K)cF`f!+j~gL8!Z<Qb!`nX8a>jT8mNNh=Sd572fgc^ifb))f%AuI(-xr
zR%@6h^o2DVrU`vvt%hkrUpS_ni?Sw94DeCFC#5=l6tuhfDeSb#ul_o<`r6->$ACJu
z`r6;qob*x9{+_%Cs8ax;{k^J`a2<+ie_!*^M?q126x8XXpm>!$0mv_;D{#GZ6Q?pL
zS5&+<xDZjfqjA0Im0N!T5K;OJvq4m9rH=v_@iQuS*2TDkd3A3qbUC8*A7tK$(kJ+*
zDSgg3T-9R8{a$-Di*8W*9A3krj{<*W3&GzQ@#n-xfj`3@jxmcUeTHL7Umm75YsAl#
ze_+JlM#A0SwRkluk174V(S#36>9?&|wZ`xdD5tRsVoKiu7>jXbCu1XiRuNJ949Ao{
z9f`-3KKcEa(kD9?Q~JLFh$($$iz)p#0b)wO72gpbg3@OnH&5v^C8qQVVoIMNrt}G7
zN}u3^lz!W)6^o718->ZZ|HYL4!Dwhq>GSI@rt}FuXvAMEVDL)tQLqsmy0$nEOTGjj
z1>Hd3E^dv<hvbaI#d2eD6>bzI_$U|ybW`yLEcz0B6fo^pOu}g7tqjA*0vhpio{D>;
zQ8eP0X(*nL-5S700WUC%ov1c|j{>4}aXqRH;G>`i$SVF7H{Ad}3cl5eNkY-z#x&+l
zx{{74eXh!S68Am-QgJ<9r;h^vG7Zy5fq%J%>7&5ELc%%mQ4ogq$I!Nj(&xI3jriFy
zvu(vvBdnH~iFJPhfAi+<MEv*){>!#+GwSqF5DqVY8c}unC<sTY8+H092)8ct$~t`%
zgkv<^p!6laLFr4lLFr4lLFr4l6?esOf?m4`%><<{@eN8}!VOAa!rd4H81XZl6CVYo
z#r6U$g^1E;_hKV{-O9%!21fi$iH-OPVk3Tn*odEn#gsl%VoIMNHsU9Ujra*-BYuL|
zh@T)f;wOlW_z7YoeuCJDpCC5kCy0&s31TCDg4l?kAU5JBn2QOOMc6RnKOEh{^1@=Z
zxpPj$|6xX*J_<@FyA&>v@3qe(ATyuR7caauL_cDgCSMJ_la#pJ^)1^{3@?hlHcIBb
zr6hM$yyb}^d0Q#byNFzf?2jX&oA(!aRE_HROO&5mQ}!pa4oA51Yp%BdJ_@*ni%EP0
z@KG?Ebr)xIW5GwkIfyljpTh%VY{XyO59=#{j{>$bTfCDw;iG^f;}*}xjUs@L0#?S?
z;V%A)j{;Kq>|kv_?5q-e6!2=B#ovVgjRC6la|qz0;7Y{Rir6P5_$c7lT#Zj)kr97w
z74I(_60&V-^ifcPj{?c|11#dmh+p1j74Wkiv+}!BVS~9}*#gQfL5pjZF8kvE&ej;7
zO1Jjf`A?)&YDFfP^3_wR%U4g<x$qObOXUhE-gWx0`71rL`aS1yRA1>85IQ_|Q5l}&
ztW@=F+Jz`fdY6X&EW%erID^v-tggSxEcNg4$|*7`^-h+*gNFCT&{w8v_$EwPWk(6;
zzKRA_D|79spst<Yv32uYR*Q!Rg1rPJop2+--Yy@oOy{+a1I!nYb}~%aN3vPY8+cD#
z`KZgnY+bf{ASmrF8o7}uu~u1{_*q=nvY~YyI<&6ChSs%wXk9BBb$yPlINW7nwzD%E
zdxXm`DAzFvR!WNJe1l+>q+lr7fhVFSrH!1pp9t#q8(_O5eFpB)Sf7C))@LAy^%)3a
zeFlP9pMfCOXCR3683<y127*|hfgsjrAc*xD2x5H(f>@t{Al7Ffi1ir=VtodJX%5{_
z1mk6W#rh0PiS-!><`{Llp9m(GIY>EiKM~BcAHcLmr!|=Ee@>r)rF{r}24;)(83;D7
z&%nov59%|ttvGb85u9G&Eu(o_<5Bb{Z@$mt4h?+<_OMR(6Tt=g#eFlwx3o!o<Fp2E
z40XDn2yQPjTsawe!T|0kKK8%ad-E_iihFCgTWXDZrdw)hx<^t=ni*+4w#W8(W^9ia
zz<_ORn1BHj4A{Y7W5zHBFB4;f6Ce<lu!PN!9Vani319+*5FnQ&+=T2QHyisB2wOtf
zw@Y#%yyyI?yCvTjz9jeNKF|9-SAR&VQ&nAiRky0o`4t`%-0j#2pnV1c&DGe9U~6zh
z8txys@ZtCgBGdgA5ssg@6ftf07+wea3@m)cy^q}l`wUzLx$t!$jx6nroa4G7t1?2)
zf=A^vM9bs&31(_?vAhe8V7^sCwg%IZG#+Le{KDl=;HQJfPgG{{F$t$9yapfK7w}z~
z!enuJ0=-hFU<P@mthu-Y9sj~1;1{^ga=5YShPhwzQgh)ptjjSUOKs|2p5BPZ<x)-n
z^zCSiQa*JUqGhyBUYg@2$c#yv34CqBM~ZD|)i;q}sWZO{UOltm)~8DjiFohN4Rb<2
zeRguML}(&D03XNTdf4-0WUue+aBw8zgN)h6n7bsHZ6f{-P3PZ)i25F>M0^&)C*DOg
zA80nwPl*-)%^|v<XiuQ|L|kn3AvY2K!b1sj(hE#?o}n}0U+x++Z^L~|-?|;|-+TEt
z13_utk78R^On!E<L=~z`Y|FB~Nw|IJ^9_qnKX}95S7A~Mj2th9>HWTW#CsYod=7vj
zzwcjJsl5z~{f-y({fl>3r)BqbqUH5XhW|~u5cfdG;7aQlzeiCAKFVaWhJMfN7!Cr5
zduzIa(jBqkXnK2WeB?G|<0x#K8#y*5Gdr1?d4}xyBeTA(#BE0FkVIdjO}dUAd&i~X
zL%YOqiZheGgh`Jci;C|ZZ&L*wp8P|WVDESr2Rs@=vRW9AvXZ3tjR#4OOj)%7mIwAz
zuNzp;9u#~LvhDjW(>WpTsdU%Co_vx%cf_O+PtS^(!_xX@H7vv(F()X5YTdhHo@(7S
zQi$)y!a_`0wQ)q#?~b*o&KT|Yc8Zy3R!ueT1F@iSN6?_ZV5a-W^zIokdB?18{bH2i
z{;{mea9Q73Y@h>TL3eGOvU;7Se>lv4WXk$YXru!}JluByqc08%u%<7?PCY2Zqy2Z!
ztS``K!vd{9EBu<5mSQ^lu4j78d<W&$x4wx&sirT*3aaVXs4-cJja6fEq%Y07w1>?Q
zbaO{6=!=coq$ip7Bf6x0$F!KaM!I>lD@^+l-LLP~$Mmp8`=;!JD<2Q>sLJYhAzssW
z7PEdL#3O2iJ*fv-4{MYD$_QCqI(MW$W-i7`sc$`GOxU?uJ!tF2s+w87LltF_%FES#
zHJV4%RP*#;str$(soAE>qasJUOg;S5RD)xMntFLXn0ljX>J_jo%hX#_HuO&2=tW7U
z9;xXSJ<UQ*U8Ct$J<T;o>)VfI@6wwr1mFmc{+p-P_ueP<U^p$qipK@{Xhf40FRo2H
zpO?O@ztI;nH%dotMd0AkchI+6RcN$FroyY?*wUt5&x?Mfufatewffd4qKkeMT(m}A
z^po(Sp10YxKMmlhHvK!qo20p40Hx<t>FEXC*c6rty(yz=KQe<$#isG9D8oInjGYin
zoHaeNYHbc%Zl+A;j|I!fMs3yuEa)MU33)?9Qdn&c#*?94nu@qZyQ3C(QrFI&6El}#
zQh(TLaElt;q6W7JPcIE_5!QtUx2VA_YQoL47h|EpEn*`yxJ6hS|F>|9{(y~vrsc9}
z_uuCkosI`k@Qg?w2zf^I`aqr$89X1zGvZs_59Ar~z3<=V8S$Kuh-b7DK*%$qJK`A;
zkY_|zQphtBZc)H9A~z!B88J?cXY@m$h-bv|eh|-yq=OpIh%swCBPLSg8Ql*Ao)M$a
zDUb4CIubt{;yRuY_1_WCh`H2wMtgx(5b=yu;ohHT^g7b0@r;;j9nVNZDm9+btxWU3
z%QIqrHJ%YmR>w2q$pJN<(RjQI`@48X!UKqSMnpB95mAk2#QN3ojP7B65zmO6gNSED
zP~#bG2deRmh-y3|q8iVLsKzs5r_^{xMC2KfZTp{iM)a!jj7S2Act!*t#4}=8jc254
z9`cNsTa9N#RO1<uJyhcv5!HA`WDnJNM#32R0G`oW#H{g**t0dB5%a6@jM&dLo)J-v
zXGB!v84=ZZMnpB95mAk2L{#G$5!HA`Y>67rh^WRhBC7F>*n%~l5yNUcBaRmGjL0u^
zjJu@QI1e3zZR8l75E0La!4c1h=|nsuMmBlfwQ$IsuHzYfiGiH0KMDiuct*FvFX9<J
z3E&uv8u5%+>4;|}AmkYd2zf>VLY|R;kY~i@C*m0iwdipSHu8)lTF5hc7WtTLg|+xI
z{eSU{XmTXt8Jz{-7{{^TA<u|j5zk0K$TK1^`E?II(lT{CBOVBEGNC8Kz&f7MuizK)
zjQ#__F}Pfq{L11jXV}c^QE2jvbofO)qe%dc@lD3(*W56E9nWYA<A*#WsXmXjIyQ_6
zp3$L<5%P=}AUvbn;Rty~bVocR&WDI+L=f?eI939l5s5=m@*2;G96OW#&xK(%p3wvF
z`mgegI4IwjXEcNt5dXtGBXWkMnl+x$*WeZLj7Vq?c}8@zKzHFc;2F^?;u(=a5%P?F
z$G9QSh~OXQ89mRWL!Qycne;!(Gn#^Tr6JFV?tdQ7=oY+gig-rLF=+l#o)P!mBA!tm
zfIK5sGU6FAi;!nTcf>Qg1n&+ap3zMJ5zpvX01?mVS%8RV#Ap%E2&WXI@DCx=+;esg
z;P2oWv5xQ0Gh#@@Ga`t1Mg$Shh#=w_5xhUoXhA*Ch{TD1m}m4ERH()?ngsMgJfmGu
zivOEuG?OpbBc2iaDdHJPH~bfPMigR`>vIRX(J^SQIpi5}RQ{KFMkEHkFVBb-3wcJ2
z#Jn%TuVXAF;@36!$h5EVjCicb`|*r;WymuUcfd0ecfd0ecfd0ecfd0ecfd0e_uUxC
z;2DWK;2DWK;2DWK;2F^!@r;Hs6hfX6tM~pqBZfpgBZ7!$L=f?em{`O!Vo1a@B8YfK
z1QE}OAmSMjL_8ych-X9)@r(!}o)JOBGa`t1Mg$Shh#=w_5kx#Af{15C@Sk}`JRt<b
zi##LF9P$xsJfo9<gdIUir}TWlGvd+^a)1~nFOs>E<T%`S;2GT(26Ju6$%^V24}_jv
zR&sn>BNw71FCe6o>&p&2qb7Jr9-Nvvej(}<{M2|xoWdW#Gx`#O{wq8q=EK+RW&B1w
zBUW%no)MG32cMvUBA(IB@QZjxyv_X`JR^x#&ohe1DBXCI8<J7jkr5e%z_9j4yXCu6
z1Q8j9AR?m>L}V0#h>SuIkx>XDG73RNMj?pEC<GB1g&-oM5JY4Yf{2Vl5Rp*`A~FiW
zoREw{5Rp*`A~Fg=jf~QYm)a2-MJH8<fBW-?OB?+2$SBP8?;xWvT0}-6_(#bo99K0m
ziW~uA@PL?*jKUhe9~njb12PInPe?|gyGBO230FsC6oMKVh4<AO8HK1uM)^5n{w*@f
z{)i)UlaX^gp(7-t+y;+`jKWM!&Zw8+kg0;F^<SFkF&q{Wkx?vAZgTv>w9DcrMKa16
z{yg&#kWS>W%%88qL(?H~yxxvXhok`_(;>VKN2WvACI3T*g^)fL9Tq|m9Tsvwh!~OS
z5Q4~b2;UAzrbAfY$aDxnWIBW(G9ALCqr*Z7qQgQ6qQgS?U>KPWVZ)wUWAhB76&>Rp
z_Djg-p;yFOB>(4qS&IyaSc@F05o?hh9<dhL$`NakAYv_YjSpChuOKZM0AMYi0JjFZ
zg5Vl!kx~9(*5bEOEu-`y^AMzG?TQpi`zY!q#u-Xn!eJ;ZMQZzHn5yNH`5fa>CRA>B
z>DJPGzg_M~u}aD`O1U!y8V!b&bs(ZuQe=hLR<#096`&47DR)UU&$<Bb%FAOUHDwy5
z+$}(vMk$XKx>E&RFpT_C$KtL#yZvDEE{qH@jnckENKKk`9R9|%FAX?UpT~|t`$q(r
z){%G#-hQY6+qxV7{@a(yf~QQQv>zrw9fs1bmO^zHO8asNQHP<luMnUPLuo%kfI1AN
zeWd_(7)tw*0@PtB?ZYAt9I%eSpVszO5~2=6X+KK9EUo$(mS@C&5tXZML6djv-zqI0
znnqcQh6_!j2tUHwhz9j%2_?)34?|%{bQlUjbQlUjbQlUjbQlWzuV8(!X_VBNm*O7P
zIn(5FVSOH~g3g_CbmOiepsLo9Zi1a9#I)8E%*oA0+O~B*!CV0u>vVz-NpE`AWP-f~
z6s(UC?31EqplsbjuuwpUwTxh2S-dLN41)b+2z3h`v2*_vpCfuOHrPrXhi&CdZAJ-u
z0{bmo&?o!~arC|<NM{cx%!$_^6@7eMUpy~nUWB^nThGJ=lSprbcPkSFrK|V2^_o5*
z?r|{z$z?K!ygo6+YbGDWR3^nGfAFldK1+wk8;VW!<GC^OJW2ZBkaYhA3nWOo6<oDm
z$?C0`sj}MGyGqmlJ=Ss<E?`OnM>FZ$RZ4HniJ8BZlq|43P)JZ_ZjS}IZtg$wW{KKG
z`8P_bP5B|Oy)33PY0^K|$hG}<EAMQOhbqD4Q3<dQhwd`8Q!){UB!3Q?5*I&>R@#c~
zqB%~3L(<@oG&m#;4oSm44PKTs?9(*t(=_bUH0;yh38`V925r!=Pt&kZ)38s|uup@(
z-_!*+?9(*t(=_bUH0;wf?9<q^E)nrY8un@a-?UHj8@vS}ccWpSrg}I2(lqST$jg<8
zH^R3j5pRSb;*AhQyb*$kH$w2Ac_R(`G<YfW|FC_Uh&NKG<BhN*Bi;x>#2X=qcq0T6
zZ-gM?jSxh<5rT*}LJ;vr2qNAHLBty&h<GCe5pRSb;*AhQyb*$kH$o8cMhNDFyb*$k
zH$o8cMhI%Wk*0dy$eV1PfH%Tu|2*CZQ~Nu3Ba9aDMhN~<-pGzdOvnat4044+-Uw^>
ze!LO!|C>fku0nbdZ-k)68{wPX8gGQC#v8dCG5;2CWDmp<-UuV_V8rA)ctpGrW-3NZ
zo`T~8c_TF2lH(U@pTK+09gUde;o}&uAUL8u&`Z%C{0{RH0HHnj^~Rd~ipu~+d+_Ux
zHTm_%n*4fWO@6(xCVvNGO_w9BkoGVU?r()Spgs5#%8Vkk2fxl(lV4}7$*(ik<SS!M
zB7OV|E({D&6_@%i1NFSXH^n=*B;wcMO>xh!iDm;0!E{N_?}&B<T1fO~qTPWO0Zn*?
z?^h2BUfJ%8m%n@&y!BkrDJF{i|De#6#^@xm=W%c>#lGju;3s+Ml2~Y{M4S8&J^Erg
z$MrDMQtzmL$h3~!IE6tO2F12)2A)b>R(K;`LSKh#SLymaABvgV;w(cSUhMWu8IFdb
zVsJEQ6l67DBai4QWyoSpKTQwntM!yJmNL?txdE3Rqs!ZQyjJcP`yR*Y^5#9ZWmp?{
zj%9pTe|jipK7rw*ZzVNjioDl;FSHBM`;`k3qUoU(6m1}J4m=*zZ{90r4oCxi5m!z9
zHPd=9Fzhlq?cWI>misT?Xb-+ie6TW7f_Krs6gw7ER-?^=H|86s;Qjg1==HhwFkZPE
z+E?A^RrXwD%U9W_?hor8Xp~)ZjaS)?SJ{nM*^O7(jaS)?SK0FP(>Q9SanwrVsFlX6
zY&=&tUS&6qTB(^p-~lQ%69_~#69_~#69_~#69_zDp=JVssBzSaIu@m70)fi=nh6A=
znh6A=nh6A=nh6A=nh6A=nh6AI%xfkPh-xMfh-xMf8b_@}CJ-7&tu&5WX&kjuGl9@J
zY9%s(&^T)4Em3g&|L3TcmDtB_yvmkiRPM%q`^Ky6#;a@$ga36$tu$U`H(q7KOu!|X
z|H`ZEajS8(UH&)bukrHNItH5L{BPwnA!QgUf1d!|YJs>mf4`iq6SGdn|KI!r0u1X2
zyxz+{D4@x@7;@$OLvoF2T@9sb{$T;lRv)81BGFo`l~CB`AC>o_w)GZMdrUy4&LYEf
z+}xr!>jZz_oAvz>^KZRbXI<sZIwSA!W_=fUL~quask~X=0LKTuS-*g3@C$FyKZBng
z->hE+AICTa-_e_OdZjM=251fb9J34WdaagAA@ZJ=qLl*8dKn@99s+dheuDWyv(q}K
zzaVJ#7J@xhv!{pAiT++0G6qa5cRfOeQapLOtfjsUHTsDEG4nLMf3@;S1btlY5}Ng4
zw7Y+z0K-~<p7&1@U|RFhSN_QYZ0i<?@cmB+$XIXSf3<&#0MA;6G2x#opkVz3R)+mg
z3MgCu%G6F1P_cFbE7Ct*K({prgRK4;0(z{!vIJ)e=(T=<x4r(S1PoX_2-!bNz@T*s
z#*u%vfLYcWW_pf*+18VI$?cyjV2*Va!KVexw+494c>;#4ITX>KFJPhd6TBbxFA%WE
zx|cP*P{3mAMqYD~fF;(+yk?7lW!BeNwu=R<u)YNIQvM|ZhPCQ;_QU6V_G9N)(8g*w
z(S?5h4!XKp#(QZ0((H}!a*PY`ojL-^Rf=QGooLr!Jc?Z$o1<H^9z(s0<AN?;hw>E1
zt1h-qMR2i4fN34TkO{&3xg0HDoT%oHH5*M@>~}b@J!>1mfIQR|tfSBk#VO9-$ft~g
z+=7Di9EL>cF##UC<2UtF)Gbro$-EfAnt@qb+(jy?S-)U0XA3Z_6JT+nxT^ru+J|5_
z0k&2>mGS2Ki;#fvdzNfLnN_R0sB`fU_bbfhNDRYDsl)87AQzqiR;s6!lqxO*6s@FG
zPb(?a(@IM9w31Rit)#RAt)w4mg|w1eko)c-4rnE%31vnRT1lynR#K{?m6YmeB_%~G
zsg9n5hFmX4WK};;_oy7BWAaGF%fme4+Qjn_rtg%x1YU{w-Qb!`;+bpuY=FlSX78m0
z`+{7um}ll3$;kW5S*3}%_A|qjgHv7$lS^xp`xxU{=l7D_ZTA}H<jM4TP6+6U_!6Yj
zcR77})PW%Hd>AKGXuw-nR6!5fb5Md>13Jh6$Q2WHG0p)7#(=OoCWXg+jA~QPWJ;#4
zFGMOgN-Cd1Dg!v7r9}@p8QRpPjP<7e^Z_w*L?T^>NYjpKrf=)r7^}kWn88@fbeaeu
zJwqKqGaZDE!$U&Hbd+X!l&p62II=swk&D<J@1BP#gbYqPFlK%MgY)af2D_ud?r5+(
z8tje+yQ9JGz>T3{sGwn};D4{7g2rJN>BeCf*a2{F#{VwoCf#iuc5x~GojYwYuW{G~
z+TrL}u5s8!<FJcT<FE_OY#er>wZ8k$F<Q_#>|z*yJxpsX?lo<D1txH3VH>n<NH*3o
zRui_v+dd>VX}vU$)NR|_rH$amVHemhe=$Xq+Kt05#Kw2R-Hg5Q{07~jf!rqduXtUO
zKTa>K!+t)Q9*x5;LZbzZ!!D@vz6CE&avR0GbY!%EX2m0;1q6}N0)ohB0l|MZTF^M`
zf-jH1$0@kKE-$V#F7>_n1N1`UunP>B$Y=paPh_-!ATnA&5E(5Xh>R8xL`Dk;BBKQa
zk<kKzIib-4g2-qAL1eUmpk}n7ao7b$>Fw$Nufr}vrpM!d7t=#D>mk#FAYytD{2fdW
zMvIspyv0XM4}yB8$6VapBBlpHjp@OtH5&><H5&?tBIe&>da$m-^kC#2&feGy9ud=n
znabH4pMc{7nI2za8vMeIcpHAAvp1e4iGx<-arTCUhi7lxTVcDk;5EFzXMQ$bivB-z
z_Qp263y;p;Ab9_?H&~zO><xnG><xl{=GhysqZJ+F(?~U<%Frt%$5s?SWLCjgkYg)~
zI~-e4+~L@YQpx-#<FPkN?JnKw*osp9u@$BIV=GFP;F-OO-YV4}TLHcSAMMq#6{Rtf
znmV?k)Ga_ATLHcSi4+x-o+cR7u@&Wm&9l*{a%@Gp{@99g{jnA0`eQ4~^~Y9}>yND{
z*B@I^u0OV-Tz_mux&GLSa{aLt<@#eQ%Js)ql<SYJDAylbQQqO$it>nmD=H_)R<!@8
zV=Km>;r?fitziHC?PDuCW}2L7a%@G%PC2^Ou@xOVRn-*au@xOVONctQqGL|332Cci
zD>~*1P{&qu)E`^XQGaYjNByxC9rednbnGkhUL9M}QGaYjNA1`Owo;16Runqtn_LX6
zH_roUXwTF%6c?vDo&&I#fS7g8rvZip7}g66*~d9t){ma^0hTx?1K?CbCa}yQ#Uf)}
zcrL&S;al)fuHPWL`lB&Ad3}xzn&XKPh_N3$WN~C-QUMh#lLkkyz&CX}vNJ1l%pU+)
zhoDrIx$<13Sw|4e6QElQ3HFeKJYv?>1oP!@ouLU&rm{Z6wOe>Hl~ISc?o>Nc9<F}g
z92kR?w*yqaXfi;va=5;FsQ|-TiYivO3NWp^8STpgZ0iw5`>KG9r7_wz0XT33Em6Hp
zK*8F`kgo|STMsbgasd@<6;r!H0ElUf_H_Y0R)R@iEuh!hL~xCO0V}}-t`#t7J<kNT
z3z%hH%xKpMm~DNPseMDh9P3D4bG?B1){W@Q>J0*hta};lMga@01x)Rm0v1`P6Wk<V
zu~lFK-xjdM`WExKMZhv^3c;-cR%jD0MLfMtP$IsJe4<~W+w{Ddh_9gOnzs;J_ua?f
znTY=q?4yb7R=w1mhz~P-0g9uyH?yk}@e%k;8bhC(V+pQrD-MsDH-pQjZ@mj$);qcy
zr>5K->&WV2XlAl-hi<8zGcxHQmZnQxd&Z$L^HGdaed|a!uVp}q#|Xu?ESWqC_M+Y$
z%P<H`p}xyecYSOuG$zx>F{qD=wXT!!HGSV=!sBB$|02h>9MktEnpE!z@kpPX!7?Fc
z@ocBqmZSUr!tjYPoAruqS<&|}j?B_0h2hIF6L>_IW1No0=)aALzp6JGDDkPNwZ8Q_
zmU#8Lwe+6Ae*rM7qiXxQ9-ix>_5YaHZP%L~ToN;TrKV3u*KOCw?{M8W>aP10`(&ox
zwCv!Rd6Har{a8FROC4tF1=b<H<(*Hc0?gD0m{5Gn+n<<>Hrq+JR2z<{HriPa+Gs`J
zRJPeJy06RtE$jOV@oYWM4TSiXGfq*BzN;QI`fy)?5q1L=4F4$E2`xBbN#9+!Sep2j
z(@yD|aT7e|gb_yj-eHC3>Om{7*Gv}mF2t7SCtaH|lPUhN>4n8Ha};Al-}*WNr%FTq
zSdJ(}HdAHP{3K|`QEl44aKN1^<E@Mfe<?jMA4IT0)c4eas_vTUtw$l+X+hq{P2B(+
zN2dqlW#f!h>xMObn|=qb*Jd8e_T5zyByDV)B&f38J;-)5{Df*2D@Iha`!2wUfWNmg
zX5Q1HY1^v*4XW8>JjTR++_68>GmOOQbsM#qk=z}`+?Z(`j$Gn@n1rvM5?WMC7^4I)
z<ICtPd;&i4(~y5+dTKS@KbwVz@80xWy6?xOO&i4B^cK1+xk}HEA|PorT@`;B4)Y95
z*QTrOyXk(Mv9EFIuQm7L>pgs07(cFAX4B=(W6(+VGk9)lx-!YUH2XGuHC>yy7e9s;
z{{gaS+8*a+@lVlxLkTxCNa^C2;hC-J0Y?h;T})~-=MNzy-D%-wXZD*nFy-@+vN^@2
zTXU8ltC>?J7sH;6SmsoVS(^5>=m>MFM_}9Ynh8n-8E5%s&75X^8<%@p#yAMS%^$+o
z5Acy%Airne?lxzdLzqXljxTekW?qbHVN{zt3oz_6d6?%e0!+J?#hNX^wofnsb`_AZ
z`!H3^-2`}c39V=DE}&o^Loi1`+1}2i=L)E3*{x`CQ#bcE&u1BU^ryK`3*DN17CPKq
z*i3M0>vLd<n)|h|2AbZw7aQ#WL58k1?*iX1BbwB!Q_DVjr>0#5<67nuOjH{3@K(At
z`#lzNc@t}C*j?DTFpp?{79plBC0W_Qwm2IN#`K!s!WTb5!WrWo05?5{*_)fpu_(O#
z(?bD{&(f{gW4;A&f=V8VaM+|LV>phOPnm2iXZfgRKHVyjo#h)e^BL8t&his*BD}aw
zdk@z2xn@4**!E2rROTN9q@Cp}kJ8LPX5U3AGWPSV%JXtf!Jfdbf3<}zQMLz926(;w
zKN5JZu%}>7m~XaEY(ih#*Rv<yPVEQKV{bYQ;Lpt?0KLxgO)E9?9Z7ls0L6S)ia84a
z<@~GUGuzvj-LLD}b+~Ab_aDg4jOp1=0PWGXd<~LF=#s{K@A8=lGj+Lcp|_o-Xx3Y<
zMx_>cuVDh1w%+<#G|6J`m_eY7ZucX#CEf|lp;b?FdM)$jpz%ysm*Fz3<=Ah$C@){E
zZT^p_WnM;Y#@L3S0)zZzQ&C;Rd@N=%-1}Mz$^0%Rh0(k#*zZrrtcOu-!}~tR+0!wP
z$n*|m_D{z;h-~jKY~yERCezP&KjO@LE@nP#B1vx##(!R=IpA%c0raO>?q!4xded3#
z7gg9S?@(U%a;!x|C(ZVf{{r+{OlI~RuNkE^Uso~bdlg>yh6)?<c#@9!X3T5Cbql?9
zZ0xsH%thXL@H77$Yi9Kpdp|u0s2opz8@Vqja{QZ>xXU3wq!-sQ`)a(ELwccJT*WKL
z#%<nz9*q?TnaRX>=2BGWiCFPBsHxc-Z{fqj3o(r0mytnCZ@LRV1-df^2eR};CoZY$
z34yC|J>tB@==8`KI=*u^!<VD3E;_x!jvHVcUdq8(i-W5d!$X!|jxm{sF@-M(F;`hE
zujW#{I0=)mlty3M=5pQqEn;{w`;XAG1TZ_n%C1y{((qm(I#QQ$U?MLzLB?RhrK>O~
z(&mY}>0_*TU*NPkNpB_4ynjPGnkOsN<Q>J;@e_LM&Iq!#X8ue-w4kWvpPTQ-lDl!h
zyvCk>FIM0!MDu2_$XdLW{bzWK*|&N;!-%FgkuhWOJlE=OkLHKWc-&$040&gBd>ZlI
zgMk)$Joz3^tHmc!=EdGdE*wqq9H-8(m*lukDzwI1&Ff5sHhNiBp*fz}5BZ(sJ;71e
z63-kCbcXjP7hy}~x7B-v3$(4S+vY80ekp~n_Wr=Crxm)<OECvWq1(LYS)+_XcYE77
z|FUtJM?cn@IgXgMG?K3{GZ&mxcwLC|TKN?-7f*f`9^MF-UO!$U(7dDBG{tz~N}$bJ
zGnZ95C7E`unJvv35#aV$%>RhRIe9y{JeaL<i#^rx7>inpTg*}A{d{;)LF>E%o*9Ea
z70zE7obY%P9vOpo=L#oMIFQ@n&KNenn>miA!6CWF@MjL#ye=*YR4*d<M!fw}bah-T
zd5+2Nip1hProFkR^)Td`o`+@9ZXPtxM=JKpb_7gsSqisiuR%!jjP$+$7({y_k(NX9
zy$FeqL+`a5THr8@li=2}JjZ5;57B*OehBWa$1qN;wP_B$_}*~ad0*m}Vae966d0$v
z^&C8^Jg4Ufn#ZEFe@0$ow8BgH=_+GcOm}qCtLyt{^mJ$2YG$$=jp9s}OuBOzRPo=S
zeKY$Nq-5i<3}yBgcVQX>bI3n)fGTPlNo5X{th*N>FlHG3JbB<d5_2zpCYmO5h)kXM
zms>S0yIc7z#7etd+Ol)Z8vtzXVP)s0>DKIna9MVq00TX8B0Rf3iMqBPm|@Afcq&ip
zp?(+LH_^Skm2pbX;JN|#Og%FjNqc*uLhh&ZG|Q`bYf&5bEIrNpj^TOucF)$+^ATox
zpF+F4=c<@3-u;++?x*!M6R|uF3io0?y$~p^H8U|fgMlG<S%^EertdJ}&*<@o5U=SY
zD6@N|?lPCsO^DU&enZdP35Qp~^mDJ*T~#=P5pU34Rk&Xf-Ke{(5z+KWaC1R$lU%i?
z;|O8O=y(K{CLtBiy-m+d#$@vLzyx={qf*hle`hNH5~jHc&E(#$km)&$d51!__Y#Je
zd#B1T<9P+3yHv?qwWjBgkNbT+{!`}n3ep^OpVTv7W`6r(=(@kxQ!KUSeUHukltPC0
zBKp&PT2FC2nBLFWq|Yd1dn3&KS%os*2Il?;J;nNYTGN?K=6OB7Gjb?h48MZw#WE#C
z@<?!VL2x6`yxHh%Hy87&K!*22c)59nOs|u@P*BMBGVFR^p^UedsT5-#JH_)lk&RnY
zD2K6jEpWzQjhdFQ$;z=fy-M@2=&o@W$1*=d#k_klZ`^}oIReeQo-Ms3mQ%fVE%RQg
z!c6Zbw!=qaIktoCZDi#Rjpdkk#&cMbWeT-=pJK-@kL7;F47~3Wtx%}oUCaEAjO89c
zSlRm$=AH|J+haf#Z!GgWR^{I94Pb(~qp{pm2<!0}-`x<)aU}J67JGJ+%CFCRob7&m
zEXNTz;9bXIeu6?%yv;<L6`Jb(nJxWsg{I*T3DAiO4SFXNovhGw?-HU<C^W-+mwj@k
zLNmQGN6R^?C1!ai$dprPwwGqRd|IJ7-Z6}Mo@&AQ-XokT=c}+Gua_~m#Bv-h3(-^S
z*^&m8mKlTdFk`UJ8G{p|sm$VB5{omqYT)kUem_=XPgH-v%KtD{V&rCCS3w<RPVb^s
zWdZn6tdxOYGiU3rVW6v3zstt>S*$b}zttz1!Ovr*LjW=cqgGe2s~(7z*sRr`u>Btj
zz(fwUM*?s<!J`4V3m3Y-3&7hPtxv>CTz;w_V&$KWmBur*$Jw5L2%_=!;XWTLEkj5%
zTj42`VeBZPyr*l`FR-#N#7e(rDgO<j?#r>#yHd(OqD<9stp6*@tLiZFs{!aEcuj$3
zUa>RkC@te@)uY+^ug6Lg;n&QB4haJjT6I0Id?Qxc3w~8u4gMom`X~VYkfFBC{Nn$@
zu$kAh2Jgg5CoulaETa}LT_*9zqj=5yx;2cCmOlxFarJoV>x}<6*N{Y9ReyI}%&w4>
z-_r`eVvPOS5&3wD0alMUws{IJv8SL0-nbOqn*9X6yzwc{#t!>F%s8({K*jzF^71Cg
z>ea0tE9T+~Nxxl-KaIt}n;3r`DL2#qurRDy>pGihPA%>WudeSQUfbFhJ_2-IjEUK{
zPPz9-OSP?6?lRq@%KbTXecPs14$A7gC}`^Cn7tb5b$tUfK9_OsLZTUixBjjtu;%36
zk;j0p`;mU`T@|w*QF8Cfo<dg}%9ne$EGgW8WODDRIL{%Q{MEU+O!>E%hxu#d2|)gi
z^q`nhO<n8yBZ`o}E?<CG+CaKyq1#*yU|)}f3*(wuFU@`(%Vc4^0Npmx=!KrlC;|*E
z{RlD|EX*@2D6HJ!3;34=w`Old`xX|Y<N@0LFuV$Trg)KQlUY{SOG0d$%(B9egk)?o
z%L)Or%ptR^u(x|9{p>5zb%lLW_n|yxo4bjHg)Se8Ds~G>P}o-z=(guGpZx^%IIGvL
z*9wRF8gl5hx1*+o)%hlX0kkkHIgUBp?LTBP3;R%XiT_BJZq5Ez>>BuwwlrfoHSD45
z03Ne@08D$sCjp+c_X4o(A7B~tpR$($WbAX%F#gjL&9j@aWc$z9$0MX*KZH#E=j`(U
z%JvU2-~B(fu*)j;=TIvDc>&#aAHw}VNgaFaRahJR7i5>L*B-^Z@?VsY0edQ%!hcD?
zpnWnEcv-+Ky9vX_e?`D-dnH=ge^tO7`%ZMH|C+SRe1|sE{nxX%qaZ`}UT9JOjnoqu
zBwOv3O!`f^+i$a{p#%N51YBXiz|{UC#ktzcqVaqjhtq-w((Akf&;fo<&s~P%-{|$B
z2mE&3;>fw#Tgx`-)-9U4yUqI+3p-AQ-GNRRhq$FKd@U)i)lK%3cOVK?T(7rDH+Ywz
zPl}_u!^8})9oZH?s!+lsv#bba*%uMk<dIoc1hecQZe1Yh?dV3_G;l@yJ#<px<FM|J
zxe!A`7A|)=4!h3dh`2(zALNj{Qn@ceQiZF;ojwi`jgsGTB+6z#gPcl5pKc~Tgx~QW
z9mRXu0=?4bY(x1=Rqy+ZtE1wjF)gbZ*M0(hS?U&G*dIRwV61exX+Mt!FO3s`?K%_=
zw}I76U5hihQcrv%limxd+2sQMAL5r|vs{$vquF0R2cVQ<`x?&bVXa)wF%p}g8NV6h
z-*A01zd8YB+NV)<bZvR8@4&0;I1G*Q_zZLH`UvtV_xZfCs|`t(`<46W7#-yS<wi$o
z<tfU28CtnKRk>ecoN3D4f>p6RsN8oW;qr9lz8tfnJVUw5=-cv4<?dvfv&5bLJThPG
zuQVS<diG`%+#i<eY4(SZs=q2&Q9g!b{i7trv@;y|M+>lR5B=wl2*}unpcek>6ch98
zDpolE7zruZw=vqW0?PJIoXBegRP38M@Yf3HwtvlexK2Qi{Sq@>FQC`Hl*JhpFkt_c
z1O1}{2JIiBBmE5mX4xf1J5IoCn*=w1qkuW~0_L+xz<m34Mmt`>ko_tr$_WA%+WWJh
zn*}UFhjK2&zeK+i3ojtKjKPWA%nAH1K4Y}5F`VotXI=x6zw$mNru2MVZQ^ht3;z%^
zOm=p-pyfI1)Q%lz2$JTKB*9$b^0KgJjD15-u5S6CpgeLRqOXKUh09!?56WR4Cx!93
zLge{{s9(oV=^?aQp}41RawYL%@G1`J?hy0#hB&_$>UIV}hR0pQ;=a1Wa+%&zG*)px
zg=~)mw;~8`Y?+Klf?E*;H|E2w^^5V_v)_Wnnm<XGa#okJ@h0o?$Ge%y?~G5-K-CFo
z0)L~PnFznCD?OxVIHjvEawwgm%S@@R#cJZ88UXHD_-6&te#9ZWO;_v3br?O1idFMV
zMGWR|VOSKqq$4%E2_eNX0t|a^bXBoifNB38jZz#dz_wlF0}C3Q-x+%)3Jwbz1fG31
z@__{nf`WY*N(~Dd1Z8^~W&<o}5LE2nGt)@|y6yeAg7ymNu|L8DCJX4b4`B)V1Ps`N
zY|wrIgZ5dxW<bC!`(4bS;uHb1?Jx40sRHKMXRvJ31kATjXK@Av4B2T6&*F3e3$?CS
znf6Zp*=XMM0<^*G;sNFf*i^B%p}57vC7NdcoYyQ*%|&k;_IFr<6#`8A#{@?Ru<Zv3
zRtm`2&k`Idz_XX)%A#603id1xiB%F(wm*!{Djp@EV!wnAE~<s2+kOS}rl=N<9{WwE
zwpya$;emxdMs9@z_LaOTog}xyL5DB=il@s{!z?Yn49j`(;=<{uPsX?kectsr+vt)E
zYuNQmHr{8{P3Ajv-<}qKp2}0a)8!!R+Kt)XCGOJ6h*Kz*bh8IHHE%o9F6%i03~ZLD
zUAOr_WO#qz?C4O)^u9$@(OYDH$~%VFRdtIqGUMIHZt7CEV9t&opkOk=898sG2r_jM
z(g%;~Y3!8odXbqnb4IO#L#7Iz)_=*Cd{*6$C5=xq4SwPBv+$EX<D1yAY@cV|i_I~4
zI&7bxlW_Y~)U$m-+g=rRa0|w0`=0p^1DN*F7`^TL$Wxnbe-DLj-&Y1j#=aO6qkTVV
zc+Wl^J=ea!fP(#Dv{d^d0cE?4Dz+aWWRr@W$Bn)H!vebOuMr$5pxYiISe)Ws=Qw+R
zl)3#N0psl_(SGe8$$b}mryiSfkoJ#s5)9ejXW0%-U5Qp1vA3XW+ef56YwQP^z-j@b
z_V3X-?Z*h%XupOwZ9i6$-fUlpu5Mo=;A8fAjJ8(5$L+7P4b~O;e0q}o2d1`Bmikk*
z>MV|r7xeVQXvK^{>rK@u?3WjnS6Ucl9Un5y4z%*Fh}01>%BsJ_MC<^gjEi)7`(@a#
z?kt&KU_9=|b+)^7YYtD@>Fh|c`wiPfw{~{Qv!ZER2Le=rXZ30Ypei6^pUMQfB${Vm
zfPU&6BdHbayHS<SZUJR`FLZS0Sm~MyO5cY3(#N7gvnvOi>(Qw8rD)(vz$mkiBM2B}
z_UExYR02kseI%CrO28<y??&HMmIcFN9<r+(Ccv|=LedqriWKbQQL4&v2`SqjLElwY
z2&mXMpj4G31a#Y%F`tzJdhGj{&yfOp?eXZL%5X66kHGR!StTKZHvb-1)Z@o2t?M%^
z&xlVmNnKme<kkIKrNwW&0zFne)4YKd{VJwf^{fn^S2g<;_Tr~g48RK$4nmGFnOP|<
z{dE?veR|70G`M{);<wL~L5F`;9D%b081^;Ds(mK`rac}7Z{JyfZMSfC>>?mz?}qxd
z&lcd>ThY7iySB353-(;xUD|h(2~oDEGurL~I<(F+FXdok0Xj+Y!d)NE3CFGfsMfw&
z?uQc%y=!UnIV|CYs7%+PG88oX3k1tj3^4HDS<|#H!YMV|U5h`p4WWm{hv7Bp*bDHo
zczsM?jX3Wd3q}oo^{un2_`7x-14_IY2Te`x+K7PBnEd69Z5f%&Ct&@fAs+5sKe|!V
zH^gM+0wZR!e-pwt#41cUwnghZ4%D8FF^?+`&yea}6EhbfsBhz1urN-D87csoOd7``
zO;$zPcudSZ8zV^HdJl>;dAkad+dm8SGo*$StlAjJLgg9WAL8N3dlC<Xc*W#(TY#s;
z%0HF(THl(D$7}kun6wZXDjP>p>A?_>qQ%*68H4WwC*8=z9@3?$23E&Rnl#h5Uf!je
z>LJ~qD^*?GyK>V}ID<-W<7yw<vZ!~>Di}9<ME6xwES$_g$oivttHMK*TbS@;dWA`$
zsU{zwaPKvO4QaaH>0#3iG&A@K-8+lpcFVGXMZ{0)^5O{Grvd#!;NORMP5&^;T5IZO
z^jcHn4uLfAM;ry8^kpXVJzeK!!8;={a}b{T)`wZW)hPe>^o|#?tf7^(Nk=g1!Kx)}
zM14h~9zI63#KF4kd7x;M9Y#Dv7wQIzHbttkG_1<Vz?}^Lh;CmbEjK(cm-x`I=qvhX
zBk@|%4-bpJ2E~1iQDKmZWjBtF;Waw&R;OE)p+^q}?ywrT6ZBx<u22JaVu+Wifs4md
z)mux{z@4Obsn%BmcXC+d(SfDRw=XQ>nm!nt>JQOK{~$_IEAZ5?z!=t3@8N|HNO?D|
z!ntfx-XWBCnoO++<nE1Q*`~?NdN6=E!tCR`aGPAXcsOQO<ig+M!s!^S+sbpL?G~%c
zE*ql;(V}TOuez*X)nefcPQS~;AvCkXz$?NLG*ctIG8{lNWdL0jz%~7+B2(6BhD_CK
zYQtx63a?uwB^x|4EZIq8RmoQEShAybEZI>zlx$?jlC9pcWXJ4SvSXu?tw5%=lC7(i
zY}UCf*?`WrA>B%~8QW_hui9(Lv?Fgulqnsmy%taVEU%a{QMK11X|HKfskWSrz`>|g
z(m>OLRbx&69OO_d#;jT~v>CXE7}_4~5eKY-xry6?_8^wOxAFTf?igSW+=@9D)6H-5
zCziMf>q9J-+<@C?%t-thw*+vzxIY{-6K@ci$>~7x_v3vTr{Ojjn=b5egUqhDVs;s1
zcEuI5D?w(L0cO`QO3-A)uZsTwjwG2~@vH66(M@Jo{2G`3pgQ2|K753Q7uQ<M_~p%i
z2DY9_Bi5D4!{FAe+wc{?HgP$A49y_3E51F>%M3ER;y08wz-=1_*<1<5=1K{ht6^@e
zVQvgVB4Be_WOF3~HdmT#uEZa+KZ@ZtWs%L5cwUBE!J5zv@M;UG!extWuEgu@KfwH{
zSY&f0-fVvZpxYvwEAe)!fInb87TH{hKR0vpwl_^SSK=K>dH`TlOT63qGV+-Put7`w
zRq~nb?u#*=0Gn$TE}G;12eM0m%{2tHhetM70&Ff8Z@x=5R|0G<PKSjq*<1;*x$vVc
za>?dOfX%hsz{Z+OHdg{{t^`tB;-0`9z~<tVTIQ0?l>nQIsSGPFJuk}17i*iNwZoju
zImh5TygY*nip`Y(n~UKt*<1;*xg?%THdg{{t}9S%!zG&w$Rjdcvblgdh-{Z^t_0Xz
zye{LC&6NO~>k2%udM?>q39z{sHsF%Yl>nRTI|v(e$>vIc&Bd@;F4<fOu(^JUu-Puz
zTnVtbK8DiIamnUNfX&62^IfvJ5@2&NY{(^>D*-ka|J5#Z$>vIc&Bd6DT(Y?mU~{p0
zi(Rt05@2(kf|yHuvbhpqb6ty$7}9;Rxe{P=9Syip_xbde0GsPc#C<g8lg*U?n`;%S
z^F+-54N^~l&GjNe!RCU6Rb&vbx$<;7##|IxR1JJKs_O}XEFI$9jUd^!bBv$C*>)~`
zIqK@7(<|(_zc3Cj<zTGEK|+ng<Qj*`{VzI9u1cm=a&4N^x<W>k88E6${vqd^u`Vq?
z8$VSts+v2x=~X48s<~4pkU>UOi(*ub8AhN%MwO))RR$SVmSR-pKgmEcsw~B*GScv{
z6r*a)SK!`}QDvNo^~XA-FpODhkWpptR=y9hQo^XR=a}#Ea_-^SbJKKd78zCcJOKu#
zGWQ><WK^XN%&=r~I9%#bf0S-As#42kkD~Ytt{X^$QFShsLzj%IG#FJZujZ0bl?J1V
zYro-=QI!Ux>SBbME*Vv6Fsc}{#U-I44Mr6cv0O5$(qL452`H_Zj6$b8#Kjc8HpHD;
z;yX+jj4Dzf5@b}R!Kh*`MPXE>!Kkv(mM$4pX)vl(;mD{;gHfdlM@Cf|jH+9ahB6tJ
z2BV6(wrB}5s?uOo-2+$@MpYV&suP(e8C7X8s+fxAl2Mfgqe`VoMpYV&Dk9S*qbdzX
z6_M?dQI!Uxiuq++GOE&GRIy~OxNRZjG#FI{{1$~#l?J2gPt1>usx%l?DnD{4(qL4n
z{K%+EgHgrtV7g>fK?5MjcFCwpgHgq>j7vsU8jLE|&(jiQRHebFI-B_kqbdzX)oR>q
zTr#TCU{n#P!{O3kRILY6hr^}8s3KB_!==HfB2tILrNO8oQisE(!Kh-VsKepXU{n$D
zaJaXTtz)nb2{NkEU{ukoI1l&0HEA%ad{oROqbdzX6#<BGY-up6RL#k#N`q0wFw-TY
zDh);z>uS4XRHebFVs06ijH)ykRYa{W8C7X8sycCn=aNyC2BV6o;F3|52BT^$P}wD;
zDh)=}B%q2rmid8E#oW7HGOE&GR82uxk4tVw8jLFTY_Cg3RT_*c=GW(vQI!Uxiv2v`
zl2Mfgql!o!4wnX_ibx#}mj<JXNF5HB2BV5d9S)ZUql!o!4wnX_ibx#}mj<JXNF5HB
z2BV5Cp$>;jpR15M94-w;6~olwaA`2A*n;z2GOE&GR55JGC8H`0MiocPLiE&~@O6yS
z(6f%gdFU8yBgf!`NRUyL2BV6>6*8*QU{o=k3K>;tFsc~Y<aO)dkU71JR*?k&jH<&K
z$l3boFwoU1WK^ZWs5%jT6|!~GU{qZR;24ZrA)_h{MinbvA)_h{MwI|Es?uOo2_T~?
z4Mvp!GOE&GR0$xXDh);zmmfJCE)7Q2CZ_f{23s18Dv7o)e9~Z4U5j6ntuO@z>*gX0
zMpcE3sx%l?B#KqYs7ixTwGV(}%w)mIs7ixTMX!p($Y4|nAfqY`Miqg{ue0%ymhrR-
z8C7X8sx~u_30)ZmCbY_WUI|9kXW>_o)c}ktHkV^?xiI;4Ul<?FOh#22jH(|nJ{eVM
zFsfdb_?yr=CchGBV96XUPexT5jH)*opNy(B7*$ezzAfz!W4@>5JK?U7QI!UxiUBP>
z&e-Nt;IPQ3a>k|ThOif3&iEAPLx)91mD3}jVv$khOpq0-TQm9idLgcmlC*0E8CA~2
z_*{6I^xqzaHEY$gnda2urSPhL5AiZ<Tk=T1N=8*?opSGwmddPGZZfJeqsmQ2Rc2Ew
z2W5qfDkwRWAuuwkvKhxlr5%H}`05i_bF%Nq?Y>GzRkqG#SoU3ykHl3ns<Q8v#eD-j
zvhS(X$f#;njH)UbRjt>^6M+2VIUZR^H9^ZGqpJ0~{88{4o4OENH$8zVdjsb0$6a{^
zd{*dWE}gVCW-i9BzV%+j9Y4Bp1486Zi+#?X=TIGeMVUhrTh`iyCMLDBT*&<!B!dg5
zp?TDWJ3Cy-ur1wFl!)!>!jZAE(=^*-OziJXJZ=+opS!jWNwOQqN-n#F%2YHH3#L`Z
z;^v@z1q@q5AHNVw@XwH@gMeS6$Yj!8Gx49jb40~ptf$03tV%IxP%#+qD{O#|>?;{{
z`$~zreWgU5Vz4RLS4tX*tKv`LN>L0ZuC{NcoBK+MYh3zkB3XGIjuti)6@!V(oAYQw
zQ4A)6eI-#0Caz8VE8+zEN{Q`pUMBlWi5p56!JSh3O38YaV6xx*JX1R#-I$!>(k&{%
z<W%`bsZ@f=sTPNsQVAxf%J@?%!Q|8uLqsK*oMwF)m-A&U6$s5!@bwLRq~w^b&%oWC
zoN4li5K##xcalHwN+p=wS%6XrCU+5_RD#Lb0+dQHxvK!B5=`zUK&b?iy9-b%!Q>nP
zN+p<_E1(jp1e1H4n^*>_1e5!;(5+O0$%V}XN+p=wuZ1-TRD#I^1W_f}58pEpP3je?
z1e1rEKW3uRkcYR@tyF@^<xOlNr4mdY(fkX9D3xGxWe3}WDnX{#{5Zb&2@=l8N))IB
zlbaxyL5frfCXdh3tyF@^6IAj@q!)flC7685<bDTLg2|^_B{Efl$!AojQYDytR@_P@
zn5<U`ChJv#$v<YFL6MY7Fd6JCiApf}Y71LJsRWa+w?Bo2OQ{5tZ??B$xm7B`<lCtk
z07@m8{B!dn0HqR4z9UI1m0<E+DW*~hCWCz?Q3)oouXHdjQYyhD_LYtTQYyhD_LW#X
zr4mer`%0n`Ok!VYD_TUU1e4fTIvGu(RDwzDD^c8}RDwzDD{)FGm0&X3SCVZAUX+(F
z);9ku)H2WhM0=l&paO#em0%M4N(>j3U^3iS5|v;Q`%2$Kv6V^?$RkoJL7)yIr4mer
z`%0n`Ok!V&H(R9=OosbPq7qDEU+DpaDV1O{+*cBnU=sUEe?XX02_~_x#F;%uRD#KH
zUrAJgN$e{zOsNEu*jIW9*C~}?GTc`Zm0%M4O01qz2_~_x^ku|UD#0Z7l{n-Bm0%M4
zN*vOGN-&9irS}jwPzffnuXH*p9H<17*jKV}lM|KT1IQp$3DTW0WKWMRp2Q_}Js~jY
ziN_JMKo7-8&Rvb@9CdZk=@oXIY&r2#4#rv>Ts<2evgC4%$vg~Hg2#s#F9WC&OhP5-
zViGEqU=k|9I}k%uf=Q?Z3GkecXPhKdg3L;(1d~t+O3x!NHbKT<!b&BWgi27y&0AE0
zNvH$~lu9rOl^~H)2_|<`31$%x6t(>GBvgXq(A1(5OhP3%j5L%=FbS0)`%kF^lTZmV
zqEZPap%Ua;tyF?Zs03MNr4mf;pb|_%CHP~MS*Zk*PziGCD3xFmDnTNp5=?>xN~BbR
zNvH&8AU~xNOhP5dfAC5rn1o7@`6-oP5-LGnr&NMTs04|WN-znPAdylDCZQ4}QYyhD
zRDwiGC76UtkZD3C$Z^E1rIDZ#BxdG<p%NrMIK)&5CZQ4}Us+UwNvH$~lu9rOmEie6
zPziEbrBjlDN{}th84=+2SCUW(a`K8wFbS0)drDM-NvH&wqssf&;YE>3kUka8Um2Vj
zC6B?KF+PvlRXCBtft<j!$rx|Ir&-1kpyVE?1d~t+a(xn&U=k|9(*X>s{7j|tGpO=2
zmCDbcvd^qj_BF3f%W$ExuSF^Q3@ZCt>Xdy}sO(E&NPHIAL)mvOeni=4cXZQBlzn#H
zK2$1D_T7X)*@sHk?L(ylW#7Lsko!>Sx_zj0pzM1Af$y^qm9E=|a&{|^;lB>qhjQk?
z8UR*U?n60q({w9kpEFMYm3<^&iLx(qV1^|VWnbn{|1P?@50zQo$~a2dm&HC5x!9uY
z%VHmj<yFeQEcT&zuTaXqEcT(EK$ueYWw8&%m`d4~#Xb}hQOdq7_M!d&1Z5wi&>3{5
z;I~5@DEqS5huQ=`QTAoA55-)RvM-B$sHONnCd$4n_MueaxDS=ZK9njP_o1@bhe{x#
zQubxB4<)%OWnUKiP^}15%Dyc2p?<<Nxet}aJ`__?%Dyc2p;VgOhst6fibyH@ve<_r
zQp&z8_Mw=cQubxB55<xN%Dyc2p^jpHvJaKTKGaTFKSkM>#XgkEkMk*ueJGV5_o1@b
zhvIlp%Dyc2p@@{SFN=LBBBkuhVjqh23zU6X>_gqp{A3?0i+!kDnIHF|ve<_rP|Ch6
z_Mz?sQp&z8_MwQBvM-B$C?cio%VHmjNGbcW*oR`LC}m$3`%pww_U*|y2J0ZozAW~k
z=%ti>S?oj6Uc4y#ve<_rP|Ch6_MueGxet}aJ`}^0vM-B$C{=UrLuIiK#oUy#FN=LB
zBBkuhVjpTPGZ1B87W+^{O4*miKGbnQO4*miKGes6l(H|2eJJLxlzmz3L!E*!rR>XM
zABsJzlzmz3Loq+4?8{;wiv6sVeOc^75h-O~7W+^{O4*miJ`|Bs_GPgTMWmE{S?og*
zDP><4`%pwm*_XvW6p>Q)Ww8&%mQc#REcT&@l(H|2eJCQO?8{;wiY=&=eOc^7F-$4@
zve<{>XrZ#t!f(d-rSux-Va8w^WeiRTQTAoA55-_n_GPgT#dJj3m&HC5BRBK9JK&Hx
z9Vq+oQnYj(136nC3IhXWUl#jN++q@CUl#jNuLEQZMipgW7W+`Fv?%+s*oP9peW)z<
zp#*RrDvNz60o;emVjoHX_o1@bhvM=h%Dyc2p}x=5xDS=ZK9oe`K2#R_P;cY6nXPaN
z{+o{Foi0@NWw8&n4xXay%VHnuivajT!-8`kDvNz6dWo_xi+v~o+=t3yABv!vUu0fL
z%LK~4EcT&($Ur9adKefe`?A=FqQtN&s{!_*QrHX07+fxz`9)np*v#u$1MEY&@DpWU
z7W+`UO8oCLKEDnO;|I#VEcT)HV0`XFWw8$>)qeyjQDQ17L)o{MF}M$v#Xb}Rte)1f
z&G*6~%D&cdDY})iuXTKi^Fb;5T6+X2Wnb$AS)rip<73EUxI)qo_MuuQ#${`Y{(la`
z0%c$8)Z!oECCWZ`ZOe3|FUmf5opN&@%3ZJA+=p^Um7Due?xt1_N>TP%!9J8I`@D?v
z5mY*3@YXNNKJOiQ3=n0Xr}m+`sO<C9K9nf?JhczibpsbFwGY+BeW<oNWnY`xhmyY#
z_uzV|W}xhAyDon-yp)P5=ePU`KvYb*qE9yqL{j=VsF-r?1$rqJQ?BamgB>GLG3Caz
zyvn$uV#;+3P%5U}SUKEKshD!(1Sl0#ZoGhuW}LGPOLI^B9VRUT!+f`S9+SQvZJZz1
z%;r@B!~A#wN?@4p$#6D=0>k_~lU8@+K_frkqgx3K^9xe)FeL)R{GMXpQV9(6dr62A
z80G`h^&&9L*9#2ud%Hiz-Bk$;^ZTSeit;FdVZL5qnBP~DRszHPegc%hFn_2&2BSa;
z4D+k=696bMWF^Ooz_9R;$t*-*Sa>8$w-Rv`9&Nc24~j})Sa{67hfj?nFf2T2KLwx!
zhJ~l>w*i#Eu<*1*Qv$=nGj=OpPbh(5;W?2WDuH3)kJ153U|4uwfD#xM{v>r&0>i=!
zLe^3O!@`Raq6CJ8mjoz*Vc}%~N?=%cMSv0*7G4#g1crszq+OK2u<&~J5WIv?0>i=^
zsgqCzB`_?!DUTUSU|4udfD#xM{vyRu0>c6XhF76>N?=%kz;IU}B`_>NV91f91cn6&
z47s8zfnfmxLxxdc_#q4wB{1|MFl0Z8z|e=lP`W_`hCT#_yg&&IeFzMRl)%u3z;G^*
z5*Ydr7@i6?4b^qOKsRQLL(t2{dwBBCf86J&6oFy>a+iZw1cv!5l$$q%{FTa0fnokC
zaVuqCv0#1`WfNszu_)tKDf^106e}jmzG6AYNX+|6{AP?}@!ia?+wqZUA1M2ZWBu*$
z5@la;e1?D5MA=vD^LeEx`-=U_O=VwkK)I>xD^5{vD*K94m7B`G;xy%^vadL(+;=14
z;&kPvvadKpxvA_c&Q$JBra4R8O4(OfY0@maDEkV-Qaz>YE368p^2d;D;V21F%D%$U
z0+h0^Fd{%H`wFX5OiU^J3dcx@QuY;&6`+)Tg*5_{vahgKfKv7q)(KF`zQTF|O4(N!
z6`+)Tg^vnQ%D%z|0ZQ3dI8K04_7ye?P|Ci-CIL#>S2$jPQuY;25TKNOh0Ow}?2|!A
zWnbaM!r7=6h8Jc~GiMH^R)MmwaB}7XAi1x78xHAtDErvWTtUJ=u?!PWt|WO5ceTsL
zp^2n_8U}N1$;*n0U7paB%SxWyCAkpM|B8@`2nYG78s<?zG|7WgGtVzX-2*>L+2=#q
z$0;nzK7R*gpATi<bqG?*J|D_HmP;x7d?@>fl(Nr<vX3pJlzl#weawg3;S?u|vabLN
zH7h8}z5<keyt<jm-;YnwK%(p`K-u?0_=&Qwuu0GGHYduy0+fAhLQ(b=P7MH+eFZ4{
zBpQ`{1t|NNdRmlye$|`-m6s^{{4VK8rR?*^2vEvCzgvJ(_W5H4C}p2NPJmMO`QrsB
zWuM<8Kq>qD2?CU|&z~qjDf|3M0+h1P?-ihweg0$tO4;Z42~f&Dzh8h-_W1(>l(NsC
zB0wqo{HX$zvd^C;Kq>qDK><qH=T8?9DEs`K{BG=JC}p32fayZ>BFaAhaEYdreSW>N
z&#zbZ`Sr>^zh2qr*DL!V3Ff+}lzor{&qa?YWgjHL1WMTlNid@+WgjHL1WMTlNid@+
zWgjHL9MnqLhg0J@43x6ZKV5FuvowRsKL6rEC+Y)L4EkJ@ef}jG)=-pv{%6$cPGz5e
zds_Ud?DOw*IeJ9d=iepn@vBEQ&;O123R~wG3|#-WGQ`zWk$;~6-EP5U{{1OV!<c<C
z9;p2X1Q_-aD6apYfF}E5JW~1($u*{ZHP&bUVFAr{AEP}Y(OT@4Se5-p<#uh`Z!xvU
z1Y|TNH1r`fJP<cG5gPgs8WLch;dv8!ewz<QN@(aqXh@`lhCYObYZ22Hp`j0<A=^?3
z4Sfg=IdwT%Syx#q7&+gMsg!3#ge--J2n~G*4Vh^(C-_Bh$jo)McEf)}H@*#zj=L^o
zC6w8#j-HEH2|f1|lF=rtnYvOl{D*b(SBTh#7WN<46HEoElhf%#smQ`eAzp-ko?poS
zb^LTvsVG7_A40oCJN+MrzX<Jo2<_;VzU&(qOr<&ICjso1OS!X<;@=C+ei<R9Jp}0X
z{RH!aeoNrSUs@3KTMNOSs^6Splo6IxjzGhhcJ6wF45hfATGrCv#>4SQ>0{=T9Y{Nm
z9w>c0m_8py$CXYLVAu;VbV?@)Fl|bLN+%1j?OQPLN}mvrvEM+gOQ#6%>}42KrBekI
z?4NL#{F4I8_P;W<(*#uPov_}QP8ZN^)3{FQ3;{j%Us-}P1@zj#FaSO!V8H$i^Epev
zpnVDkV(DxFv+Om@^c(@R?I+RqrE>+$v9BWdw1D|GU)z<=6EI}YLBp2L7qHO&3I3Lr
zE)cNDzLzz<P{3mQMqYD~fF<_Hyk?7lW%k!twu=R<u)oA7!Ak@TYhByf51;edkCk`P
z#%es$g?=x<x2w#T5SL~h(I~x$0C{~;0mN<icc-A2milc#=_AoQmG%zvvjBD<TCKfP
z3E1sh5z=098DNMpllH3o*Rbu+orRFD6emH(?m?N`)$PKwpFsb&tJ_6EjG45LmC;gG
z`Co~&WKtx6;r@1rlUmnOW;dbCC|&=8+P2S@+hA8a)8AFO4?&Z(@21?hp@!|di#vT3
zrd6iHH>Xxmi5~!Tl+;tGvwqV?t)s)*2LbXF+EEqhiD@sw<m(vMvVvErImI}laM|H)
z9+Q+Q$Cwg~CO!aeV;AN#p}Ya^jPWXqeLITRF;N-YU4Z4vhFJAG2zDs&>ue7mjE})E
z>+ERxG1IWmIRT(kLQItp{lle&7t4dv<8VmBouYLWF@QVA<bJ`hzu=1>2`iu+X8?5F
zgXZfTSA3o^`1i70jbe0t4L#I3K4Zg6Ql1rtWwnW;sF8kdOAovf@jV|;n3MLW&owE&
z7D>e4xEChO&!f-FL7YLv>HQXc24f~S2+GGpo1+77{dXiXS=4-kF`tEqZ5i&ncwdRy
zb(luHqVEgp(#ebr&0GI!O`jPW8sFG2+P_&L9_e368{4rKmDuROtGsyUn8kd-96{xo
zZ0~e*te%VM1oJn=%m?wSZ(Y)b;v7#K>A6^z3pcLl+kCA=Evn*-^dC8*>4lj5*`&@=
zOse}a>!=E&Z`68sW6}@lV!c{J((@(huQ6%JqaM;*=fVRqRlOh5%Rx~mOHCfq$Eu9h
zXuT~=X{j!Syy&>lB6t6ou#ijjR#nJFeal(RrFw@-YvGiEE9h~kE@K9bIG{1DWqMHT
zB?Cv@0(@AAhgCHW*Mn*-8>le;5xRYb6n3#T)u%_Nt}_P@g*i#8bqosAm%LSi9F_UT
z{v*)^)iCSL+O$1+>1%T3-5&)X2o0-m{VuK?6ynZn@@5fjIk<#{eyyE%8?^j%bo3iR
zfj3X*9M#_p>a$Us(a%I5)Hfr+At}l;NO0!b<Bo=}Y&x+sX3b-Y*Gbm1Mq}n2$$EA-
zvi^4oDf3zgTPIz8Fd|+rf9-MMq-_Fa-9W)69WStRSR${{W_^+upD)SYu|8~zjZAg`
zcXj>zqDppjI_`e@g&E$}S)3Vv<aHzZ=5?XC^(kC4Q-;t;M)l>$;9KmPk+OorGi6we
zOjdcXn8X{oevJGhWI><93ZfsIRiUHPVN-ogi)z31+O&@`yZxk??|{{$x-2yo#q`*E
z`(;#*ZPs?$&X}`gq>=yBD=n&h6HRJptzbI@9H|Ys%t4s9Ic9D}TmBU{vxd6Pq_)N)
zc_%SNbT(k?9;+n+7L-L>>4|^^Wzkl8B49yT^RUP#0v1#nw$c;RtW%H_PXYli4IE*7
zU5Jmo9tH<XSWt<XW-A^CEZRy>1S}|vw$c*;3(BIc^hCgdvS=$k5wM^vT1`#_EGUb%
z(h~s-%A&3GM8JZwXe&Jtu%Im3N>79=sEo3ep4i(wgk>NLDzQ&PU58d^sOzvUG}Lts
zbshd~$^C;0PFc91h2i~VNr*97$bw3M1@$Htk)qg2Pk;sW6~u6583hZ9Ky%50N`x#Z
zm$uRqU_ptl5{o1ShK|96i()H10T$F#OoX=56JS9RXfAD~C%}RtYI12SJrS{>Op<|L
zM?g^2($5oMLD4#lOIzuQkOk$^R(b*~C~~X~m(MT>u%H;xbSE+<SWsN6yWNJm?thWG
zPFPS)bu6eR#e%9=-5F#-nRP5EQ?Z~#jn`bS#ybHI1W@Cx!H=l%S~|MvC2G8uIu?`_
zsPVWN;TYTT-FXYXMCqewQFa|I$`0gt-$N9kMcH+<C_9kn{SJZeLyNNOXi=%%$~0T9
z<awz%=57EY&r8is)2-xrsd)k@&*M&z$n(+%W>{2_=cNzzx6w^nRC;+U<0yHa16tJ2
zfJC0>fELB_DtVr>gFMdxE$TN2Q}R3qv?#_@@;nE$C?=xhc@Ah%j{rfQ$0&4$OA_&)
zLLA8R9MGah;3x7t2ec^WqU3oFXi>D)Eb=@Dv?x_L(xRLl<arKgQKV}qd7cAW6mt#a
zc@Ah%WV$GMo&#Fc9ZZw7C}#(Gp0k5I&)Gqq=j<TQb3lt?eoCI_fELA)1@b%xv?y{u
zlswM?EvgqwsL1o29prh=4)Qz)v?z`TCC_s}iy~6;JO{KWA|=mrK#OAi0(qVTS`>LL
zN}lI{7IiK2yA&}T(4q*GJkJ3w>P8?X&vQVFB2w}^2ec?6CC_s}iy~6;JO{KWc8Zec
zIiN)mQJzQcMx8v*0WFGNN}lI{7WEN42#Y+=0WFF^$@82Y<arKgQ4CY^JO{KWRddp!
z9MGbeo08`_phXcWd7cAW)Cydu<arKgQAA3f=YSS<6p)hVIiN+Y0aEfj2ehb~JkJ3w
zY6HTQJkJ3wiao33c@Ah%%umVl9MGcJ&q|)>fEGoh<arKgQAA3f=YSSPq~v)HXi-E;
zp67rTMWp0;4rozCN}lI{7Dc4wc@Ah%YzZaLb3ltCQt~_pv?wAa&vQVFVhbvHo&#DG
z!<0PF0WFH7h4Q?=!q+j#pn(XC<HKMZ;k0xNACc!dphYoQ<arKgQA|hVc@Ah%jBN6{
z8{m*R9mw+>(4xM|K+e{mhk=1S&jBrpJSvgrIiN*73*Z=xD)KxBv?x|u<arKgQ36Pd
zazKj`a5@2KQ36PdazKj`Kw6XoS`?Qbk>@#}MR8dcd7cAWltknE83(keKjGJ8D{R2S
z$`0~82ehao;3@Jv2ec?!vUQBjEI4UV4ro#I5_z5jT9g3Nq8!ko2uyx)J6T#Lkmos|
zMSX{XOz7D#Fp%dtphb~KCGtE6v?!X#cML8UCckokVKb8!<$xB|1V54IIiN)iNc>wE
zpI>{1@dJ6D16tG!#wRVx0WC_Z{|lrv8peb?Zv|tJ7Uh5z#ekNc%-H6;;ShOVW?YJH
zCC|%@PjNmdd0wVRfRg8BCddjE$n$=QE2QKBEh;lHej2<?`o9o{1@gSi)Z(M?5_w*>
zPM(*oljmjY<ayaTd0uu?D+i^>^P21Bd94|TR@Cd{d98Kwyw*B-UTd8^ueDB|*IFmf
zbL-@JZk;^uR%9X74CHz4b@{KuD|H;&%kcabw!8HV8q6#DbhAL;$M0CsqP+G3y;A3F
zL$Fu%XrI&4(GA|1mZurlqH$-hTYzEFxU(0~qAVJB_5xazMdQxi4zwt*C;l>%7FtwW
zw|NSaCM~LMTr<^=nnk<oZQ}*#7VWOLg|w)Y*j;a%XU@P~Rvt9k=6iH&7VWOLEs!&S
z4U2Zy+X7mYMZ4>5dj+Qh)9!j(K#Q`Pm{CBBN|UtIwzqpb{0bKBuD9)zIuPY4TeQ30
z7SN(B+Ffr8Xi?UD<`dAO(zLtYcBr324!subuD7kulPNcVc4Z}%-Syl<CbO_;cRlw=
zmTt|W{juDmEnmRqiDA+1dhRj%RshqY-Sym)_Wb}jC>H-Ja!=WR0?1gjyPkVmqInkW
zuIHYy6WD7kShTyId(JKalr7p_&jqw7>vJeoE}%tOV&wQwQpX-^6}mGQ(4wqSbXx93
z2^p}&TFOfT1}#b#axV**Wzp_>?iB&EE!thry((aibtk$r7to^8w7Z^rJ-aswGGx(|
zMDC5$dQ@SnwGyqIdsD0cY_n*0J@=M?D=gYw&jqw7mv+~4phbNV6}rx)-Sr%3QQTL(
z(WTw>9B5G-IXAm&*(RVx^#k4J((ZZ=v?zw%flio>xJ9wMo(C<8{p8Z_dLFbW=?3=_
z^hqAHC|+Q=w7Z@MEs7}N((Za5v?!iH*5uOedLFc>S?%Z~B+ZwIj<Gkc5L#5*$9;~<
zY77n8rf5-B+Ffr`w5Td+QEiGARV6K|P0^xKV(`3BFfT^gWKa}}GHx}C2G0wn6f0(=
zR}X82a*mOhH}%_&aX1mbuE$5FeOjw>(JzekzXGo+4W1ViEvia`=Y>9>S617QWT9WV
zNsB5BC^u<Qg(=EST2x`Ga+4NSn5NvMMHL2>`)&;6!gS>(Evhg>xk-yE%v5gDq6)Lb
zof3oRxs~Q>q-SkLNpizdJ<X!Q^W3UnDw7tKJ4!-Kiw4hgM+>km8a&U92*_B6pcc8+
zDJJGwG<co^yMZ;cXz)CDtbnpbgXg(50xA{_p6AvI=(c{%39wE;kM$BWT`!>5qQUdr
zsDJ^B2G4UJ6)<Sg;CXI?fLRs|p68AeFx#TR^V~)ObF2l-XOn>W77d=~ju$Xw(cpRR
z1OW>z8a&T!7O)5%Dua-;sN9K#6OkN-7Y3`znR6aKU0RjI<lM=bPXdYT{AxI)=i|!G
z5myj-2Z?JLCdzHDBsmUuWz=dIHAV29VKCR0oUEvh@o4DDWhEywSLTUhyo!)ct}pVa
z8s<Tp5t0X|rp!;IJOl2c7(CB|7R4#-(%^YMq(!+jc%BC>>Z|ZI+|Qze@*yn>hYbOR
zv?!Mb&-0)~v1KwY4W8#gi(+QnAFtwfJPn@bK#O8IVNe&v2xw6zlm7`mK?7B2@H_`v
z)OX-lp~3SUXi>b)RbJ#!3TROk8a&Shw5SScQ900}BpPW^xqudxlGovWhj}VkKo(zz
z`@!pQi?73R2m=EQxySfbxyRTRUx$M|)rE927GH;hJ;fpGSx+Dzu&31c<vj-MDK>vu
z?VDYMw4@pd?jb<h7UCqRV9ahpnNg~I9qy~w;Z?p4_toq0Dqn~D>UDUPufu)yIy@!Z
zu6)&e2|OQ*R@?J<S&wWri&oq7s&s}$tL=GJI@6-n_WW3hW?Qt{o*yS5W6^4Re!KwB
zqSf|%kAQ+jtL^y-0?O7j6f8ecK*jn!Go2)$+oIL>e6N5Wi&oq7lLhozwA!BU6EI-W
zYJ0w4z@SB|?fC%#vn*O|&rcCB+ai@PKUKgSi&oq7(*(@7Xtg~*C}7B<)%N^!0SmP%
zt+wZP@*hQOrWT+LX6Fwue+J@;#r=x>;Sx==Xtg~baJwv8ZO;eXE{j&%^8vTZqSf|%
z!0obVwLKqjyR4;X<Gfn^3Kp%l=L2q+MXT-kfZJuggi)GTt6#VE3MPMEt$sZgt+wX_
zZkI)??fGNmMmk_!$y-{$?Ml;Xd;WBJ<_Nf5`HKq=pgxZA7xa0RR@?KJWLU#03G#Wx
z?W&U7mA^eL{^WM$?{ql@s{G2|CGK(LcIAI#UX7QL7P(#d-v%el3*-I1;DmW{yYlzT
zV2)YjcI6)sU|8gK<sTH#WRcsIe@Lz|Epof^4-06v$nDBMBGFnba=Y@6$}@*;k=vDj
zOh85}iV^udxLp?R&@PS0=fUkF&|Gr6^5Ayy>CSLzL_QC07m?}Gh<qO0uCa(|yEG!7
z2e*rV$TKdD$mhZB;`+lChjo?pj*)Ym$7;I`n-1`(oW?N%ZWl8(xk?SeA@dghfJn{C
zgPO&(B#mLF!7n6y41PLD&8pA_dLGoQli=eR2jROig~@`NMX!`lvx;-fw*f3tvx@Ul
zv_PU+q-GWO5TIM6W)<fL%}#1oaY4}Rve~w$YW6g#S;f6FKI&y!q-GU|QUw&WtfhpS
zRs5K_1cVif)U4vigV9fFR`EmuhDB-?4hi6@VOpeS6;BpmTcl<cKOrDvk(yOJMSy3K
znpHeiK*1t4tN2L)Ws6T$#nS{-EK;+Irwiz|NX;sqA)v=1HLLi4*!%LpsH(f|duQ$p
zmz-o~!i1T*lSwj@NgzOg1OkGh1q+IbTg8fsf*2GOA!1ZiR9wLoQ0s~n>qgbqrM~V~
zTJ5U#t-H2Zm%7!ZT9;OBwcqpn&fQ|6F16p+_x<LNOwM!8xo1D;-h1xzd(J5W+7+o;
z`BMdSC~h(4mka1pq-Nz;2pFeG&B~u9V1gnwD}TCxiHg*${22l!D^j!aX9}3ANX^Qh
zC19H3yLA3+0lO$tv+^qiOjo34<yQ%qp-9cjuNE*<k(!l1N5E`FYF7SS0o_LFI(EwW
z4*RjG7j3ME6J6-{mGCW*nw7t#_EdN!t#16*?1$uv^<_I*M4t>svFlqibQ|g!)VqF=
z+r<k}p8CPMi`6m&*S86<)vgQ~;?AEd(DL;|_54v2(4_SvlN{J}YAr#BEGRj30J@>R
zGg(AF1r+2=6r^n*BubAV@EC~yHNQmNQuX8Qc>roGW@-HvQc*+wip88Dz*0wINv+>f
zfUR~Q*h)aPQCh}$lbk_Fz<Pltn^IuaN@>)&evfo7-Q-ObG;gX#cvB7a_Cp9rkT=!P
z;66E%H`UNswSg%q@}?S^Bm@U9vE20crY$d)C#iSfkePbCQ6g`up`3YvVTlq_$Df4d
zP}>XPTOx0&VNm`P#^A@Gjvz*fys3u4sUo~e^9)Sua+(WG=~67;jb{(!o3OPMgSn|e
zXxKHcpNsZvYPR3T1?o050!|d58!d;Fn_5$U2C&rMaCy_96mvs2GDJVwSF86hkeb@$
zu+x-Uh|X#nBG=TZhFt-Mih)s1QEi}Un1mG6$GoOJ#Z|7TR-#Bvu1z&+I2-vTt?BqJ
z4aOSQG}d8pO2?y5n#KwBw{$xCp=rD@TxxhOdagLvUfPTzx1#5Z2UvV4*RM0h1C@L&
zQwQFSka^ZsXbM}sb0fff;q_FjdwI=40#a%jNBF^2yatwh8?YP{j}~1ayNLA9#UCDn
zk3g2iV;WWfl|JIt7f6($++Z*dGGoyt4_fxH?o~jCR82xrV$lWkSxKKmO|HPP=u!0f
zCVdWb<MhC1D6=px%*3KM{tSqfGM}i5MQw;04eet3PsL)<Uc_v_nAd*YG#4D@5xgdq
zLCZ?7(B5oY5`NmRVm!w*-veQ02?}GbImwR)Zym2^L>-bDhv1QO7egSaWcK4uVPrLi
zZ^t^O@S-qt$hvt>66pjr>SdQ2)!PY$^jBQaV;FC>V8|HjTYb{bHmlL6xa>w`G81ik
zUsr{+Q<223kan;TR7g8m7b>Kk3TX%T_X=qz=1CW&SKz@S=1CW&pT?~pH~##!Xr<}t
zUOfNBAYJq!rcQUdUkV7)MMMkI^LZVli->yDwRlvCLAr=9RZG*);jt?Q>7q8Elhg0x
zDJkYj7p33E^H~hiMZ9ipdQavD=^~<a=~wY86@zpU(T(XE<^bs;qT6x4I1r?Zh}Ngq
z;>j}ROBczbEwh%#S4ThUGIPQGG#=;SETmInkS>}9kMuk|iN+vZM1T{z@kktlbkQQ9
zB~+d?3_2y52E*<~oZ|yrcsmB^BI?;UP%%FS=_1mr8lGWMAzj2Ab>6pl7v+q`E8&^6
z=+i_=d(mr$$GvbTEz)b7s4eepJ-#B|PvF-k`Rijiq%;vc4Fbm?T}0)t;wl127tI9_
z>7sZ@x~M|hsgQOsEYj36s*rZ@I$j~|R7g9bsa+xM;O)CY+QG6|A?*a3+7;3czFkyE
zJ9uudkai5CLfXMQQiZgG?PN<Gg_pMqX$K2Kg|t&4?NmrRczCXmc0lQ`kamm;X{SQk
z!E#U`?IeqMTC9+EjOq$$=l^rkPR)%Vv{V<*upa}xMtuNK)FeAY-4CKl@oaq#r`iB&
zRB>fO?ELyLeM&Fl8nYzER`z8`<S+OGF{p&A&E~=zKqZ^*vOd%79!76TlB8I=mj12c
z9@<U!wl@7^(WM~ulpbQtUo}kuLnmpGay0BD#(6}OZ;tgus~$vnyJ+@2QmY9(6Nf{a
z=rNI01nXyb@BVWP^YI#*V?f4e_+iihdZLClk&qG^aTk+((v3TB1Z{!Lr)rpHWc9Yg
zh5z$(ji&!>qra1FK$v{qDjFj%=hgR{FD{MP9eC?9*9?1{g}&Y<uW1Q<7l`j>Eie?l
zdv}C<U(wnxx_ZU&I_(>(Tx!vXGnv#4Nez!MI?g9vZLU4WQ^Pt4iFE#4d<VEhrQzTm
zo$H>Y)@yWp!n~)O(~pkW)9{VXTywpD$#nOU1-#^&-X*#Wd$?sd%;*@)<h$a}ftu7S
zC4UYnv~Sl9&n6Pd&|><Uu|6eg<Pp4Pc${=5-3G?bK})oZliGaBlR5`oi1Z-PXRnDE
z#(v`~l&1>isX}?eQdgloVO^+Do+^|la6>ATrwZk%LV3bDgNMj*!T(;JA~~&XW3ogy
z;n8)IvP4vf_-t7s8aes0M8g3*St7c9St0_;5`Bm?KTDQ~aROPQJ8`8iOT_YSN|uOE
z(}64zV+OKBOeByc`Xvx#i5P`Wm%k?XHy#ej672y$UzUiu1hPb1fV<<%66wNiT$bn+
zq!GvxG1rhR5iLmqS)%Kh=D#XS#QXwTB9<&9OEi^?BRQ>&vPAXZ7=A8UB94bZmWU{j
zB_axBiCDjoEYa<K7)}>4KTnp3Adn@x3@DH#A_`=Qhyqz6qCl32of60r5mA<?4RJmt
zOGK|gmS{V?p82vw1e=m2Vpt$cq-*ZU5;3<xmWU{jCE6L+1+qj$fh^JPK!Gd~MJhHW
zOSB)t0$C#VY#>X-`~q1b_H!UhL=?yp5e2eDM1d?3Q6Ni16vz@01+qj$fh-YQB9J8_
z3S^0h0$C!qU?5Axut1iGqlL0WGzU*wH%qT^9>NS0S3zS9!^f8;Vz4hu#B_XFB1X1(
z-M8V8IUSNE;t7&AXX{;FU`UqeI{5jrM2`a`Ek^ZaiCAf0mPmjnOC-RPB@*Dt5()5R
ziMaguvP3k+@)=GN&66ei4MJ?T0u_k<L6&G2c>1zL#{eWPo`L7f64A?-B@*Dt5)s(^
zxgCGfG9g)_bqr)ek9&b3S)!l7&zB{73m|E6xv=>YO9jom2!*CB(ff>l3;PbTL`{g0
zw60=&{*3YBhh&Lb;pfW|N%ikRO0&F}kR{rgF+5o!28b-t4RCm}M0ESIM4S)4ED?b(
zOT@9_$`aj+E2J3$S)xPXWz+w+URWSY^Z>lRtSk`+<wj+RCe*TVXm3|~4lLMz2gB)V
zWFgfIWQop)moH275P&C3L^lg`Gyc1>MD+4yiH5_9*OMiBlyN;-B7!e0OC*X%o-ENq
zCjCWaiCWQSo-7gFU!5$`wXl8smt=`zV5j)9L<)eiM69GQOT;WZSt7c9S)%1(hSSvm
zzAVvC0DM`Z-vIcsM2zOk61@lD%Mw+=iu6B7mS{YTDSTO?eNoUaEK9Tk6$)gDnt;BT
zEYUCwlt7k<{p8CMNjH26S)w_#;79-7h;D=sB6``ACE}?3(y~M+plqMXaAG9py&V6O
z){aE{xfFjg?E_h&v*5KcSt4HP$r6d%l_e6lD@!D9SC&ZJt}KzbU0EV=ug5@!ERncf
zSt4<}vP9x;g1HD}iRkuaiDqCZd}XpkOzeN5EYU%z7KRsQkj<Gxm7+kFs0T<ajxK;h
zdft^K;?m&R?J!Kt@VSy?INbZl5?${Fb8X4Uikh?@@I1M!XjvkeCrRr$cr<Z+=_5<@
zkr$s+Gs7Pgx)uKdSt3s1O~?|Rji4_hOT>IA5|YAyUzUjF>?=#e<Zs8H+d#f7(K`6~
zvP8VieGXY7iS{!LVqccXQ}oGI6n*$rFHrP}JDBR8qR;zmo&V8_J{(tpqK_$xJ}n_d
zAJ%YViaz4+D*ABrc#1xBdx}1fAhrJ}MV~Rax%rAd1fNgQXJ^FxEJYvIRhA=0&eU=$
z@jEA`@fPs#6@8eg%?Z934w<<dQ}j8TY48V^pND^a6@9LT4|E~%>nr-utEPJp(soAM
zb_1II{nb$C8sjSZJbEd>SXa^KO@?eHIxdk!&-`w~8RyEqJjsypTJFW=8aWf~Lzx@}
zf}F5GkP{XNa>4>ZPFNtw2@3={+orybX3_#dPG5l_=P3JO92zD9K~7j8$O#Js;jBT<
zMlBHJgav|}ut1O#76@{}0zpn#Ajk;|1UX@WASWyk<b(x+oUlNU6BY<^!U91~SRlv=
z3j{e~fgmR=5afgff}F5GkP{XNa>4>ZPFNtw2@3={eFTD>^BwkM6Axz7qmwQSBMuf3
z2y!l|{X4vp)-(8R+kl~9IwGGEi&jIkWXP}RGeYPK-j{G3yo8VCLl+_;bHo6O)8KTd
zp>n9uND<1x30p&7;&mPFVMsHE9*lQSvr~`0)zgQ8&M>-$vjrdL+yBa_T`rxWdl;lh
z#-y18h!4Yhc>2-U^iKrN8~!Rj#?M5)?U8eE%{K;g!%dMCl>ZKy9vo=KuBeJ-d^FVm
zmR~|_ywMx$PQdqmNKvhyQ2CZ$`IcY#mS6dnZziaFQ2CZ$`IcY#me0NLihM~$zNGRk
zA1}wBI%25uEx+<DpGOQ;zUAXh3P%i8zU5cG<>QE<%D4Rb%C~&HK$UL5&*wQ}sPZkJ
zTUPcLJYtBu^_6e=*uwm(j~M!2`7QrZZnk4bwDK*#v>ubK@-1IJo_ys;3{}46^Yh@w
z)k-Sg^6^#ZKlXH<%C~$R2y<8BpMA>@j>EYccN72PIl<@qc)lJnKkMT;Ki0{|b4Kp-
z@%(yt_#e-iseC;DJsg|-c>Z^$!5`fDV)z!=_v3k1z7D>PVE^Mez1oJs$L#8l10J4@
z*=?H<jRBhRJD>)9pENha;SDK#2yGieG!CeaXbjPKpd8U8qRoK{KsLW?@+-a+bqiz2
z*ZHk-OZzx@!Acw{i^2GfUW}+Q<Tl2bW3QDM3lL-Ix%7D>8rui;sap}T@5g_0%_oR}
zPoj$$)S&IDyW4vh^^Z}-t0SxD8N-j1{32C+(tK}u#4gIUBc{{)W-~q&Ue}A)4)_Q>
ztmj}Dp5JT^bic-q#OK#rOwZWb7~0LNrkGNY_fC%3(_sp2t~uAga*CPLS1uTdFSXm6
z?pNL3kp~&(cBcDLx5pTI1=F!iX`C*kvtCN@5Yt&OcOirF`eSYn(~08*CA1<x?RIRz
zE031~@cZqVQh?3_PJ-_VZmij(U?F~@`?0yVb0)7i$%XSew<kPV4q=L{K5+E)gs+*^
zC`8v1wAn;_Egpr^US7+_#s_I*%qn=(>t5Gu0RnzDfFG5sah#N84xWa={UFleN9Cu`
zJ@Zhg=O<M@Dpx)#S3W9NJ}Or}D#I%3DSl3TKT^kY>!zg_Qo8?xNIx#IyQI&=(_!qx
zNPn7*Oi%xEcc4PFA5Q?7;cU1Es2ELOizRic=`5ttR4F>(K)`9HGnZGkMyo01zaipu
zF_WRu)LeYMeJ<iWiqvE6(W*BQ`bLDLAY>3R<3Gf|EZs?KlI1>g`~gtT2+-7Dfh-;3
ztY>t3fI5udfv3Yaha5uD>E%(9KVlqSDhD6))BukI*jV|f%nqu2RQ~_tqjKpP*owG@
z;Kenk;i>%<Gcy$v!+r}>gy+#V8`%l?S1Mpbvwvd?y-N2*;ck)%WX;0Ft<p!ymAerr
z2H$F@Tsso624g8uJBvGe0s}KhRqdMFoPh~=sNHhRt^94cH)8Ou_Q>%O)4CK-a@AWE
z9!D%~@LfI8{+O53xUzauf^Kc_UA?sc8hrl(o?`G_vs;QKE2U6{n!TMKx^Jd?)&R!Q
z2H%NO%+%>H9~6V{#HnV2<<$n?iRGr2r%KmhO-!sX6XzgI8+<2D*D<xhcj62)!9=vd
zcj6o~aWN1KzL^-E@`4f3_*xIU2H%PE%;;eFiNSZ`Dl^Sow83}cduB?ZEydtF@qII`
z3rB<R#0_Se?-lw;i^Pp)`ZlDY4ZagMn`!3i8hj^iF{AebYJ=~@?Pls2rb&bE#2q>n
zBmEbqd8e1=;b^ABT^iZxBxByKQFZ!{ICv&;kIqjUd?$XWOXeDUC+;(&Ipm-Xz7sI`
zex3R4h~+l%0$w}Fx=#NX<0tWZjjZ&W=+DH9W(~)KHuz4wq>(oGPQ0v<Huz4wYSyrR
zuEBTWH8Z+``JIEGT%s<Lnvb<i489WsBXtDY;5(6t)GY$i2Hy#MBqq`Z--(<?+Tc6k
zXrv9k6ZuFTJ4G9OC+an#!S@HqF=X(aC`6+4(gxp&>5-I!iiyE@V)safKpT7~W<=!9
zW2LX<(AranX@l>?UXcvjp*l^2@5J7b4D;3o--($TX@l>?tVpH_X=;P-#B7bU!FOW+
zNQP%LYJ=~@fsxEGAZ_rSI9TW2lJ39+OW-4MC&IMBcVclQ!;z#7z7vP*{ItP$;)qCw
zBTyTBCyvxe8+<30Xrv9k6Gv;L4Zah{Xrv9k6US<#4Zah{X`~Il6Q^jT4Zahn>6Xw2
z--**T(gxp&Gc?i$--$DI3u=S!#92B_8+<2LM=~5OH29{iZ_+vuy`Ho<4`D2XnkOwz
z2r>9hoEwQUSPZ@s_eJX26Jqe4_-Uk`k!@bL5Ds_Kp!fs`(}|x&>i1<JXX_bWplk4*
zcpy@L4E)64JMmzo{wjc^#i(NNop>@*&t?^a@5IwCpuu<Iw=ST;cVdGJXz-nQ)&(^9
zPCOT>=kg;4--(wa^@lUH-(j#NUUj3<;5+eJr2bm`x7iAvcp>g%@SVU%;vzi7;5+eF
zq<#m0q_r6fK8REPZS5rn--$oDfCk@*cQmkh#R~jM%eV&LiFYIQOW<cSp{u+=*Wf$x
zUZnn8@DqdY#9t%z_W~p>E*Ca`d;@XV)zjcR0fTQb5U0U+0tVmOK>TpDj?Ew6K-@L>
zPT)ujF%YNuZz2}e)jta<jr5GJVes7qw-|gUve9}5RJA2r`yUU77<?xO)zGaCzLSG%
zI2*OWcd|`@Huz2sk=4sJ_+E)Cq#0a;@8r<vBzW2Mzs?JD4Zf43@|VC%48Bu`R8ico
zbPgtFYN2-Tj5ba!((VG?J=%Rfx;}OI01iqq_{L#fS_JWXxZBpIlGUhm$l$y7Z=(BB
zdIIU!eyn4TM3mZ(>-b1q8i+E~eq0du4e+S_yN>e;vKg>0Gl_8?gT38=@5&Q^9EW=Z
zu9s@M2Hyj&&mI6TZSb9TsxAc(gYR_Sp_>Id5&voMoo>j{OB;NrOLZSJu8BvCbh+vZ
z#ubC_bc+CO@SSdzlTU5+8Xnivg9KEoBhmBe!2(i-b=q2>w&?ef!l0jF<HtP9WNH&n
zkJtv*T64|5XxhPt!aqS5Ocw^vU4V_XvvPWyZeH6TdDY5(yb9Y|Z9gJh<-#6RfCU}$
zEPW3*SDhBIZ$w$mH5VW;CVNCmC)=x&JyPy>+^ZV;2VSzh90SXpsN3Z-Ub4MglAg8~
z8D(0vn>C-pPzGaR2e-29DG_7h84>%jGb8r9h=-|SOk^6%cE!EhGES6Ovf*{uxjL9p
zyYV`98!pAm)omCT5!3!J{)@y`;i^ca-(r|}My%L}m~IiP-{u$u5j*xCk=>613Q;RI
ze_=1fz9wPTzR1`*5fd;vMm7zt2gbppJ;4EDJ;A`m;*R|p?G&49X89-=x2&t9KY^p)
z$>?EgUG@2N|BkW0o2I{(=Xx9t8BbB8%C@fPPs+D?2?N}^N?u3}#a6Sfja|WihV>I<
zVO<yHW!9;5-%!68?rO`r7ZW9(arl&3(}ddO;v;PyEvL>xYVpoA-9}>8!A5+Pq-?3-
zh!r2DIR0&Q?H~e~7}aWP%$WG7dWNJDvz8d~(du|yP7}~3{I}EiS&2U>Ir4i6?w0sw
z_5d`!GVv21-=7zwDwsd<%>`KM6tsMN3jwxjXR#&-z=+19QhZARDK!GmV)3m6)Tw&3
zSo~`Oa_S(0i2@4hIwn0yK+#C8K`Yy4e0zHjmf;G9?GW1Vicjm$fMvC>U=YN2s$vZc
zvvylH+OC2u)37-q_%<)~YBExM;a_FO_p$lLuN!jT0dyPc?=0l3IBRLCW~><T{rdB;
zbX&0`@i~obixp@vrf09m5C7bRlh#iG2GmSM_ICVmIdo9{a&KIBL@f^>G*tNq07vTN
zkw`oIYAEnDFaCR*`vi$uJx2V+0TMYeYq1f3Nq1^u){#d1WpUf;>#S>75i$O1|ItV(
zk(f2-03-f~+Mgk>lzNR-c}=d#sUht8KUJ|M3aaZ^fOi{yg85TaoyP&Z-|!wli~2r$
z;)5D)J+!IAPXzd|Kld2g6SEGVW5oX^Np}FCm>)|q#{r<6pGZCv(mS&IaYXbuTr@HL
zS7aBDn6*=ZzFs$L0g{NBlE&op6`LW<Hs!i$>FZdE{$>^aVYlWT?1smy%>mrmn4UhU
z3n*n)$B^2L^pVVAKzPF|o;GE;bn874*$(mdM6|88jM}7i5Ym%F7IQr1vBio%6OrXV
z{T)0Q#GlohMMnBc_WO$wbtQ^zrSHRX0aQn1r*~uaFGd=Ps?#5_jbDz)$BR_@XPkMj
zL~NcTS(pAgV#Ht5X?CQSj0Ji<lDPw6UFk9C^Z1)OY+QP8UiVg{iib!}NcX!F=$(kn
z?1}0AoI>yFn3K~*UiY33(;Hs#J{w-~J{w-~J{w-~J{w-~z8hZgz8hZgz8hZgz8hZg
z|A`x3@jcD_`<NK{1p2x<KFhSfjSfo7GP<8xOJJnaxCO`O=s{_v-zM7MlyN|M3-|nz
z77y>tUyVVLh#zCxzh@#Ba@s642M`$P|3)tHV>ODW58&!}oH>Ad2Gxeme>_@LmW+r|
z|6u&%NIx4LpMHlu{r8CM7#QiXxC_LM=m0s3K0Tci$&98L(M}I#%t$oLwYnv}nx*Ws
z;T7+52yDF1A+Yg2hrq`B90D8fa|mp_&mpk!K8L`@`y2ur?{f%jyw4%9@ji#Z#`_!s
z8}D-nZ2Vt11U4Q%1UBC15ZL$^I0QBxJ_I%%J_I)Yf9DX`c=!<5c=!<5e)<qt+3>Qp
z@}X>a_5WuZUR9wDud2|7mkMuq9kvsmk+##1K#yYO+nCxRUo|$VcF1?Jjck5Zhc>@z
zwkkZ2Siag}f2?Dk+9BP(+93fqzqnQAsU7;8U$BtyH@_0I1~5*bc6dIn^wkbo-c6|;
z>b;p$@hFkR<`-iIYKKfDP&>RD2%BGwLZ>@r1>fr7klNvB`1xvw%q37e%wmQ2)ed#x
zHm-JfAJPca4w-96?eN!tf!g76rulU&6UjcCU&%h3U&%h3U&%h3UrB6!F~30VkR=PL
z9kw8cK<)4^%#WL2$v&H3$v&H3No;<}yLp=0UrB6!5d~_8M1k5N>lacxJdgRw=2sG%
zUwjev)eZ>)wZmh80<}Y;K<$tyP&*_F)DGDxf!ZMvH@_^z32lBQvH3->K<$ukroP%C
z!KTy>85XD=>Y96Mhs-TdJ0uF!4!NZjs2vgoYKPp?3e*l|8zbF{g+JM6^NSV|TOwwl
zcF3L$)DD?npmxZ94%7~b0<}Y;K<$tyP&*_F)DDRPwL_vn?T{!?J7h})YKKID+96S(
zcE}bC)D9UIs2y^&aPy0s-bw3h={3&7q{TLZniGbPuXe~_U+s|T_-coYZ1cLK;gC5U
zQae0|ft;-uc!BQbR}!0F%i-s%9o__xv>4S_J7lGOwL<}(+MxhX?NETHb|}D8JLK}?
zs~yT#8aKa^*!+@cJF?=~{JItYZMMRec<$)4`IW@xS35j?wZlCClGfK*aBhAjvH3+W
zU+qwUr*=qS^XEMLNz1sKUrB6!oy<Tcbdwk8Zhj@P`E@z`e6_;|0FoA$3!6XBd-2`P
zFRC3r%=n(#;a?^G3Ft7JKebpmBy)H3i|4tT@blFUrTQ14`dfH0vH3NOF+8<H28i0>
z8E|-Nhji=Buhd}K;_}rFIXQf_Lyi@9^NYJ#Qj$RJa7TFA^uNsu3)Bv;f!CK+JLI6;
zsM=wU3;e%V?T{N;Qq4f^a521EuR0g+(!+%Y6^j<ZGi&`eeNJ+H&co>=trO{Uvg@;o
zKC|g_itDqCK0DFpM%U+L_zWu1=Lb1%@5Z7l;4?TypQp_C&W_lV(M{%>p#!j(71LPz
zRz~>LYnU7Q4H*s`S-k`sRCh4`FU<20f40Ow4Dkom)AxaaOc&AGHb?Zeh=I3B!+a<|
z)N>EpR?_K(cl-Bv$))BvM4KrIwa=i>Iq@8PirQx+eU`_cJ1b&iiwK1qzRN27+gCJ7
zR>5}{@qH9U7_tAn#fCXsDoZZe@XdMc<`UCJ%oP$dkw#%xGGs!Mucoo+nP`L&2jc{m
zEoJ|YmyW!U5xPune&G!m*>()r2^CvqM_IAXJN6)GXJw61vlz12CWwxfklwU}7#Fni
ziK=I`&mt?HhY^Kq#-U-a#O?g8ssD~mwMb}FEgITXi-tDUEPqoi8roEghBnoro7_~3
zhBnor;Z3z@pG~!BXj3iPXHzW}-c+lw$U>WHvGAr^tk0%e?6Wr2Vxdj7Sa?${7T#2g
zg*Vk=Utm)$7TQ#cg*Vk=8{1Ti1)FNI(56}}w5b*gZ>m*}8L3E<R9Iwq+^Dd~xT#iQ
zkyVZv@!4hn-eX1})sH8)CcfEdCg&#49icM&CU@eVMc`-e#AWc7>F>mC1>o(((e3ZV
z5pXB23je*Gxbu*{(9k}mRl+#IPTT`P{!SdryQ!VHM-djBJHnX3P8<^ncH({ugq=7>
zp;O*gKtm&b-NT`sxOwpNcjA~!uoE{8Z>0WCoG#qPcj7)k8o^E+a}Djp#gIy{6L&Y$
z{8xA4m|w6H$C8D1;`U^I{<$OVSe!oBP8`QWaPA0EuoFiV?8LEtp`Ey2Fh74M?po$|
z31TEcLn8=w;%)>AcH)SFoj9UkCyprCiDRb(J8?wZi5rhNpW2C|SFjVu^C<nDID$>>
z#4#+`iPJUrcH)>@uoFiV?8ME+b-_*?QLq!oQ$2&7xCKC)I(K9-!h)SR_H3{d$NYkw
zIQDa}6Gs&6#1REMaYVsR98s_nM-=SD5d}MOM8QrRTO!zrBMNrnh=QFswqURm$FN{0
zj-!P;ai739Y27Ei#(9{u*hWc<6T;t#W3ayy$8`LiI5{Sj*WG}tWKM^6;x2=q&Dr{(
z7Z}=!yBmJ~PTb1?NsCeaoj6w7--#38?ZgT2cH#thJ8=TMoj5K({!Sd1W&hj}iRSIZ
zy^au@t*{tx)c>#($HPecoj4w>nzVSXslO9PFMlUafVUGzVDsk}_>-0i?Zn-|KqmCE
z7Z}=!BXPywi8HVx1(pFiz~)Z|&}(Mz+>to^{GGTCiGM5O^Jg0`erP9dEaQ`gmIMt=
zs?Xy=dc2s}iJQ$B-cB3?WG8Mt9NtbG-TqD-=Yzi!N8s<oajdvIalghDQu1IY?nHRm
z^nb$(3wGi*!0XHI#Boq=bSG}dfB#P0ZU49vcMZJ!b4S?j-nk=mvv=>qf6~zE8glgV
z&mGwcyHVb`BQG+pckT$m7e067EhcT@#~#>XAJ3$}=(!_fv1jF-J3{wYckaktAYuGV
zS|u6qb^LQj$V}w9Bdnx<?g+E+&K;rKKX>Fpd`7g?)ax<1o~gbKz(0572>}1xk=FtI
zb4M7>KX)XSW8t4hrkPi&>jD0Q&K=nv)CK?Ckwqx=7e067B2*|icccU8i=8_%0RtsC
zcZB`qpF1Mm@FmV28P|YLLjV2<-I%ntM=yKlj&M|d>2pWULD@d@+!01%-WTG3(%P4Z
zKi|intZu=%Bj1MC#?Bq#mEO4{;&#s+5x0Bph`8NzN5t)(J0foP+!1lF$3TWwiMZW!
zN5t)(J0foP+!4C{b4Pf_^;dT82ow8Xc<u-f8o}_w46-?M&ct7E?#Ky1a_-1FIHc#@
zb4R!|ct(B<6NWNZk_?A?pL0j<@q)RwWMoB6S{po1E-U)n5t%1R>rV)2;`*YE4_!i>
zf`{b6shQyq3OyG8f^$bWg*S2T$YlunGUtvkACgW>`0t-P!gBUKcZA9R0)K7;`R9(@
z0YCrT5#HuL$GIaCt<Sk5`-AFIbQ<ktIA%kQK<hY7>8Yr{p>9KnQ%p0!N-Uh)YdEDe
zOINMVUyhLGnr2LflxhQG(kYA5O`UoUpQxM`0Xa1p3yISz((?t)2VRA=q#7}NU50zD
zhx-|&J(=B*0;81f<dqXL-6%$>f$49l-Fx6WjkA?@-wq<G^EGkTc!#I_F^_Wp0FP|h
zW+{WA;&>d+>e5+idsHv0OJ}PWaDBE_qE)LjGRzJVkWzE-g*ZD{K%H8FN@m*x<kUW>
zes+j}f*Os2Wrqs*j}=_mfY$U6Pk8_$8~?KpPvP(j4o`U!^+{SEq0dXdW6z$OVhuNT
zc#8PDho^7~c!#IZ?H!)74xdN=qYh6|xI_E;F9e@Y|D_c%KTH3Gb(Qswku#jfp5b&Y
zJbe8ZW@>YlnhJ-^Tf70$tUUX&nWSBdq|wbZ_=C<k2><%(zbu6h&f&zbum3`?n#;e3
zx0?J!`vU+u?Ia&Q?Ia&Q?Ia&Q?Ia&Q?Ia&Q?Igc#%0a#KX(#!<r=8@FvS;8V3pwp1
zA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6Q
zA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6QA3p6Q-{-WG
z{P_<1v8fkrtcMd_==YWImD5i0m(-pLucXzD-<tifju-38cCv^*8I0jq-<qM@P|sjg
z)emyd$5{vlas6O@K8{+3;QBTJw%U~;Luz(I>}qudc*ONX1*Fsjtp4>QlN{J}YAr#B
znC#@#0azpIJCjA^Q$Rt^L_ym2L89~+0*`_CU-L`c2vYUq?RfxdEZ%|Zw~!UyP`_d^
zCkU|Ak+`kYZz;f5I}mIopxP)cW4uYuAS7VDz>-ZVuxh0=>Ri7^x|i;|;4Tc+)+|$y
zNp(ZL{SX2Yi+XyEh6Xvy1&a}C*U(tCfhnoejs$3u5L?eX`g_xs7t52>J8;NMJ>Dqg
zQTv8+<^_f&N=O}l5|%@4FNAODe$=*MQ2rCfAj7&Nh*A0u=6S>5R1sdKc?PC+InCxS
zU5ZVG#<K_VP1stBJ7rTtimh1l`nhP&re^zXT%c}4BQ&+7=|;;T<)+rup8+iOH(cH{
zD8<~+jSLwq*H<eZV%^l1or+6RY9TtSX^31?ry6zz7@F!vNKU13-)<TvAqDj@uW3)w
zo};K%qDW1e(%XU>&PIMoYdU^QgRzD+jdfU@((&k%rg3Q|RyrO1&@?{JENjlfkjfS3
z+Dn^JWb*Hd2UvV4*RM0h1C>zF)q!^-WS+${cy0C0jR5mqyS00H%|Y63O)W#p#e?NM
zpE{$o0r#!q(PDpR7m@zC_`_rH5y-N5Ov4JGng`H))y0$T#{kri0g9)JnTnzAUk$Ka
zfF-Y1#TAmSZPeVjiWi+>_b=n34*-gKlDik3t?k{_1}3*MA^VI*=_8i&0&NVq%XuKw
zv<;9D{&XTC86rue^aQRlhYcvf%VyY)URca1ZO!Z22W-i(%TVI^URa$m^le@@GQB6f
zV$o$#_Zqs0u}6!EODwt;6rZ7|(PuN43w0%YhRs5Qn&YvXc0G`^!aZJ^X=7*!ZD4+F
z;P)iWrOzQvn?4iW6xK1#dr*IKl1O~Tq8HNVTE^Mh^;rX-Qa9tgRy&EE|4q8z5qJAi
zmghv%oOf=-?nR)vX7?7u7(QQn7dSv*^Ecv^TM=}!S;fuI$m%1poy`a{O!Jm=BK9qE
z-KG9@Gfelo1^T+Zyz34dF@cxuZ3Y~ted+OMp-1(uir5n|Fw8Z{R?NtUSjs<_>5i<P
z)+r_Uphg$qu+B^rp&!<8lNwy9Q4?23>;)*sh?m(1Ia3Xk%f2ys?qblf9J5+qx0n-y
z<4~52R>YA$Z!)_6&g*_;z6Va!GO5m9EW?@Y^mRDR(F(c@_xX)5#$@5IF-fGt<RC#y
zF1RMEFIb>2_^x}wVVzR@YyHX_RY=}4mW=hOS?YWg5GidyZ;Xp!8QSryqGnk)k3$`v
z5*x;d{l#n_BR)+FwvP{^c%JR!cj$I)AL*~(b)JVqn$@*^q}kR+Z69wy#K88Emszgu
zBdx$(+s9ASv`%4aG}?)Ers;;s+`&dHZ2K4s+djs^wvVxp?PF}TIs=#UHFOyM+cbc@
z1b<R;EK4uJ-4ff(Zp4Tb+s9bg_AwT=eT;=|A7f$L$5`0*F&4IcjD>9<V`1CJ*r#kC
zW82&NvkbI-jO|cGx1pA&0H*aP(6*1DX|V=|wtWOmi-@+54fuZ;qPYXzwS5Fl>sBTz
z4Y}_Cx(%^?{4`DLZiHytN6@s`7PNh2diI0(;h&pu(s~5IwS5Fl>#sm!`v{sA-P-nX
zQ#38n)PU_HXj&4PwvS(qru8WD(zcJWu<c{)PgQIQZTlE|x8Y&TE^Yf5d%ppOR<7-1
z?1P#X0B!pi`>_930NVC3_P1Ilt!*D;A4@T{?PDx#`xt}m<78Z<Z69N>eVh)YZ69N>
zePkNi_A%DS_Av(A$J5bD+V(L9+sA`(Bh|K#G1xxxMz3ujW3YYXl-lSCQoJZ5Kdf!$
zUewatPC5cXSq8bbk1^OjGF)sQV|{ENW3YX^5yjTFk3e-q+V&Bskx1J<#`@Sk#$fw+
zqm4-=wvVwswvRE`KK=w@+V(Nl$M!J>+s7vmrfnZ%uzlpr*0ztaKDLiB*gi5W5c}GI
z>oz6!#p(rOUuPg@Aoj%}9}@fGkPeA`QO+wQ_H`&K91{Eb5TPRWMGIO_?2B%kC5;A_
zm&5k~Lp>pow*|y`5J6dbB&{d$I}nRL%&hxFr<d1paRf<{9E?GdxOyl&Y}`W(jxm{s
z;6xC2dl;+4b+!0`?IRTlwC!UIwvX2$hS)yFVEag*Z69NOY#(E=eUzR@UTgxq#Nb!k
zKE`1C_!bkP?PCnKj|AHGF$UX5B5nH^>udY?cLcaat$#2E+s8UIrr18l`q)0kVEf4a
zv&8l>2HQtQ)V7Z?*gkTt*0ztIMbo+!IZjXarcq4TK62`Gr~7gJgzY2Ig7kdePGI{;
z)SIrwP>8|yu?6`pO+SYR?HFtyyMRtkzt2UukL_a&wvW7SZF)~OG;AM<)}>#~0KxW=
z=*DynbAat5(e3Hi@Ee2eBhmWwTD(id0^3K9BW5j)<QO(FGZ)-X<H;V*8uf3-VEcG5
zJks;<?h%9SBY}}Vuo?)qkH-KlF=RcaQ<7;g>~6&2jBs(`?HFtyIe8ms8Xbe}BYUdh
z85R|`kIYf$z23VhXEa_3&!k14CeB|OobY%6?xb}JE^XpO@&@v|;{5`CZ5g0=mXzEh
zcq&I;G1xwGeJZXZfbHX<0M<76iEG<OYY<vLzPDE2dKIk}pC!AX)>OLpmlr5c5KM;7
z_ULnLx6<U+Dqus<E{a-LU%Sb_qJ3AQC=d!e8UI8m40e<B5}~k-*-c)LKzw<{Zxg?M
zXSmpE<*<zzPyPl`Hc8p~3j#lzvNZyu(5GyD6TqWv(d|>V2uRs##($5p#iDwYt=s9Q
zau|#!87H7@{T|4tY_YrnWs7yQL^&)8<uLi;pZ1I=88e`4F_D0>^)3)7TZ}@d+tY%h
z*f$UyqHHZg9G|kqTms5gH=_HLEnPT|vZV|6F#0(O<**bY29z!48lr49ATXe8J;pRW
z%9eDWD2LH_Qm0AfFd9!1Y2`2)PZDY6Fd9!XzkssEl7%Q+hcZ8(vNajA(Wh+b{C>>o
z0OLuW-<wz=XgtaB5Ky*=0?HOqK-psbLX@rNnV(PD`Z4qKC|d*pW$Wia0cDFQpllHZ
zlr5rwvc*mbC|g9NZ0(9TNsD!e&0v$kc#>WLWs6)WpRz>|P_}f<sT`Jsau~w`%9gHq
zFWU&pVazR{Y!L;NEiz#O$`(;T**Xp=plqEC6i~L9yH*aP@#N_U3n*Lc*?_Xe`~u1r
z`#GR&5e1YjqJXkR6i~K^0?HOqK-nS+C|g7UWs5BlP_~Ey$`(;T*<uR@lr4q@lr4@H
zQnpC`Oj^H{UgJDWT5O}F#R=h4wixVFwwR7j*<xgy*Zm9*nZqH<)@=;rY<<xS#J0Ie
zVZnIvG5GnEtxo{(G=Zo-Ws8;eDO&<O%9a3+vL(QyYzgovTU>s8$`+SppRy&<JjzxS
z(QLND>3DGY2g=q_@boELR{|uhRV=t?JV`H~vL(QyY!TS}@$DT$lr7pj+DzyZIHcKP
zPy)mKn#PlVgr85@%Hhc*X>qx*`7;90Yi5tK)d)YIvNcuW|BCVXv#%E)Ex#1$(s*(w
z#`h>&QvH|FIxD=GplmH+43DzK0HJI>1&2r3qT8ozaX$EzEdrmi#jyg)7N1#O#T8QW
zfU<QlylncDNF-qaW$Qh7dz7s*QW52_+J#l(rgB*ABJCzWr?yACsT@{&_y7*djZ(Je
zBA=wiXMxglxJL~5TSDAVApHR$<*)%E<*)%E<*?5>UW$qRw^x<Gc=BF&$xe5j-szU+
z_=^`0`_sj5;fa1;>J@m^WZ`Zfc$|F{zQ}2M)UpiSdiQnU3034FS@KDF;E8EI%48G|
zJ|B2ehHuI_wI$va2A(XRt_x~sf>Q(()d9BxoGPG2jb)za$jzn=Z4yPQQm&P7NLQqc
z(nHwK8hB}e+1IRtyKdkW_G<vTTvui2#%Jc+5$kFxq@`YGve(qHD0ZTEzXOed>jYFQ
zZrBa{uHF?!hL_-4E5_no@6cTuOZUxboA++(ZTQr@i7Z<NK4Pzim(KE0hi*gN#ezMS
zxDLQlmov-96L$mH>Jfq`671b-wI#um0#a&QrvFsp?+B?=H!<YtL|q+QYy`n?5<>tA
z>YD_=O>6~FL_uhoIgn*yUi$r+y^N3x;L*fPGYp2uP53A8Wz1Yh?M8q+l6rA|?8RX*
z#4|IAaojh-ml;eC7R<XQ2DhZk0(zc#&yxj}%us@naF=d657D1#VndbQVP)Qx&nu-_
zbpKV{#fupyX3F=5;$SvRo2f&dyA@!l4$(Bjj8nzKzl3I($vbqjwkz?UG{a0oj$WE(
zm?_m&4MbeNTV~2tJpM`33^OePG|ey*R=dlD)$THV)b28EQGVyvG{bC*y#tdb%`iKt
zKbHYRy^G-NU;(DGk!iL~K8{#M&2O<3bY-`;BN@b_tZsI49o?E{n4MC?ZnV@l&`jBF
z<e&z9BwBV`38_}&kXv@DgrroQ8Esc1T_Y5b?Dpy9c>B;a!|V<<2ctX%b@miQn<lfe
zsH#wc?2eK^i_F*TP6FBz^AA~MWcPMnKmwX(n4O<}6@WBDR#MXpb5GmMLTHA$-`3LY
zGRihob>myVrWxj*sXhrn(+qRZSAPdU(+qRJuf7dH(+qPjN;FL~%)M0oFhVrVF!xIJ
zD*&2inEQiF(4smY4_dj`1hl9T_-d4UUFz7T=He!udqd=5+Eov3F}XJ-q(e~{EcZtN
zUFujS@RopaDvq|!y)9sZnuB|7?oR?Hs(a9#xp$;pCMOP=KgY<uTbseFnWh=$-mBRH
zWz#gn-21XxtyQCOAItq&z?JF^ruLB(XI;7$%SLXXnVbvygQgkgGG^v)NJ7&La}B2A
z$hjqb2nI{8#Z=UPzCHZ|7Iu&hyBnQgW1wi7p>v37v!8@!=qxe^N;e42(CIOgOw39*
zAY129jbiB~=yzwanH-6*c={8(i#msyIje|HLegg;F+6plmxX4SJ=)=@6q;f73jHze
zOq3>jrFK7s>SeFe?o~)Cd$qW0wnh1?^ErE8bd7uq%jad>8tT&1Q1*KL;W#nB+sGF(
zjKsXV@gKWHMEp4#f3noOG{bzWa}d0QW|-F>BTIWBpZo}iR|?HAKT^9%Gt75rH))3X
zPVFYmFh5GWNi)ok)^5@a^Ih7#9s@Z)M!QKf%#YP>(hT#PX*X$x`ElabG{f8+dkp$f
zXok6Nsh**>;~j6VJC%<@vbh7?@8T(rxB~@Lt2#7XZk~XY+5_E^n_t7kG|ez~kc8ya
z?TmJ?fPxy2eTLiu0Y!BSN8BL-TGS()01E}QsXsE)MFQH@B`i*lfDZKuN7$hPy3|iO
zPZkRpr|KE)Fai2Vv|O)%iE0Y-Ib6VG^)90wAz-Td6G!Ng0;Z{*S<oc{c0q^AAiS7<
z$K<v}wJ^N6xxtw;1Ai{fFn4TfM<BV$_rf7P@6rspf_V2JhRN-QD@lgKJ-C-4>C?Pm
zt}Pi^QIpm>&y&kahF>t{LPWm@9!*?dWKYD)<4G?*r>4wLM2%q5YMP<5jcIcV3(e4(
zYRV&vk)FzlHO;I(7(tq5=<H}Fd5^Wzd!n(Noix%%qB%R8HEfww`b>;5XIC@F%=mrh
zP5c*{VQ!e2Wd((1m>X`&t=eYt-@>2UKteOj^_r<u;3qW0+~H=5w>hC1=8ku7qle&5
zl3V72->|!uyU|E9%&j%`#1)!heWN`M&ul_7tPj%+>x*dyXqsVtN$xS4W?0``!}+9X
zhV^CXd`&Z~ZxNtrhV`vAY<`z!I1_0}H9#}u(NzmP?9vSDhZGn^XomG6nqhs2W>_Dh
z8P<nshEB=8vjLSL%@8C=uB4h~2ofZLrWt|+NuX(lE(uc83?0pG(KJIxvs*OH(9!G`
zO*3?cNCKK>=nNI0X@<@)0WE4LuD|U9+SFcXZD+WEcC`nZ%o!n|Lv?Zdj1<tNmh+kp
z0pk>vZ=Fs76Vye#W|V-5>SRnSXS9IH>Le^~PM3hGDuHF&86#ktQTh|p9`BG(rfG)G
zuJ#3uXppt2ytA)FGt`5;W|llgSn3XzV735T{hVMw0oCeBf;j?G>Scoc1=OiM(Z-Hm
z{c>s?$MswZDX4E?#5o5DC@Q`|I(qeMQE%fG>*&?5O})?5=1Vj@da%$3$&Iu_U4_-x
zSt>WuuEhKUdJN|zdFF6whR!*;D^MRunxfBzX6T%oVhx36=$xl-QFpK*?@EY2X@<@{
zY0ea(89F}{x6lloM{N?Lgl6bGCi7H3+BuI4FjW-``h*PTh&q-->`4KZ+K<(KN<dtl
zgLU3{TCTCxIxYgg5zt@Zm@LEjtwgI*b6B|z^2|}K{>;>#5s)(UF>_A6X+Mbq3C++c
zm>B|1GjtlT;&3>pU&SrKY1GJ0|A44yR{aSvHO<f|nTnf8sr2I<HO=~Yf-4T|Dr+hu
zXE=}b7ID&g1|C8)bOxJwW@^hSRdnYq-r7ksbU-uYS|(|9ATYxpBs>=XYEHfhpCSrd
z+e=GmQ9kMxChKsu42@WrGVrN3&c-TKyRc36_W-s!5bajjK^{S?)sIo=!j3XVQ|cVt
zw+cJSIH*%6VIUQD7LZflK<5^A5l~PCRI#vY&1e*(sIquUDSSgfv-%FfZUS1=RD$U>
z+yEG)c1GmF?g9p@=h1$Jy)wI?IBn`?CcRe^!Bll0%eHsT7O3z%wHl38m?!mFpq^p^
z^9A&%7chDY2MOp^?_iV_4wj^ssFfIbg#`kRQfD&SAp(w8*RTy1=J~L_RK3d7dgb=H
z%qWiIaDBr}oQ75e6}^ahb#m^$sl7B$vtgngYep+qU4m~RTT7ybdh2@tUl(AiCkQ6H
z<2HucH%xKIEsdfZw$bA@(LKM%XxKLO5+;!5X*Nu);a8r5QS)Dzuk#v?vgekOQ5L0d
zINDu4zJby=93#L|Q?M8{EEQm@$>_m`V+B;JTTzpS;{>GCd#FRh@dE19OpJ$yWdd^Q
z7yO=cf`Ede^-IHv0*Y!pny29;0WGQv9o=xUfHw6BOK^&ScJ(XtV8f{bIuuR88<q>`
zQpaN=HmndZPAy=jrwN##o<~15oGxIZx|-k&0h3h+uQ^k|R5cMppy4b5(-dtU8_pK6
zi+YGPT`6F?q7rk%DgiUpvAkxrfSKw$EZaE(W~+;FYi>AKK(|r4j{R`H!+vZ!0d1`3
zBVFkCHRyfeX*OI^doH~2p%cHFr`cGx3oYmq@-!P;Gjwa7X5%2Yi^<b$9IU%oEkkf)
zn*hzzY#ib)K;&sQ4%G{g@H87oCb=?bo@Qf*tjL<D+1QyJj(o_|ya)vmo+drW(`?3n
z&C_fgZyydIJk7=}q@tRq**HOf=4m!=DM0fy8@CeR@-!PKIirz)@H88z6j(LkX*TYW
zK7qLiH?yhU{uO|5Gn*RR*9~$rn;NU0;nl*;Y-*Aamzzm{Z>{6S!o_SVXSmm8{~aFu
zlSdSCF)v~aaxt3*<==u^2nnTDKZbBI!IP|omvAwQ<uuo3;bIog9?0zi;bNA;T+C9l
z{X8xZE@r7EO}FM^mReJ<0B9~|X;6w=0-B3i3Ue__VJ>EAh+Lz&n58fmvouUXG#9hf
zp5m=Qb1_Q+7jswSm$atfSGbs^u?~wPT+C94i&+YDF`MVwhYUiI$;E6wz~Y;We&=gG
zQ0ZL^axt6d$tfV3i`g9JVm61ln9T=Q@fw$l+3a#LYmxrR_;b0K&Brtx1*B<}&1cv@
zVfLg|HtRX5X_d`qCs;>IXqC+?6Y?!U(<+-at+M!QbVzwyGtFnxn(HpdeqKwxz29J@
z#`{!DLz-@!)PfU0TN>p7*HTn>YiW`#0USHB8$eM;RJAG<0ZIZ=Y8ew~mS}bAY?Py=
zEUD$xdMr{cEdmN^TdY1Ut#Z>UqUC?bY8{LPazg7j?Qyu>s7o*sTW81<k)aMF*i(R|
zF2IXk>s|tEMQT;+-U6!CdMqKWGi3s$)YizZbsqtB>S`q2svq}q>Ijsob(Vw_)Lv-y
z*4YAz>IRgmbw2?u>T>2YM?jl;ocZi8pj{2d>fhS!KA`P~`$Fqn3F%Tp3G~bEIHPnP
z%QMe85RF+{jV2$o^8jh_YmiN`FsABJR`emXbYU~Otzr`lr74UPV5#rolEQcawi=8A
z6gC%7t*Utc-$Fo2ZH00cCJ3lgYk0HTasc};rzT;_7PgXGenE|4w66(hG#XFAoib^$
z0FC>sq4Rfe4n1tqp+;eeyhW8(;AM62StWje7P3n95E+Nh9*^a2Psao*^?nOXwmlNE
z(Z#))E_k}HXQi`FL)f0_7I+Pti0(5Nt621Qa9rDk(|efWu#81-fsajRk9Td-XcuPh
z;c7O#aQ^P|I2V^O&hcWzjCSGo9-&T@7}qn#DvY38yclVtB#hi+3s=IcBwXC%gi$>F
z4wiX$Q_jGRMQ=p*BhEPwUdto#$1aT66VV&yntnrZWJ^ykIH}7cb(~BT`s;Xt@lMoq
zthI>SC2>b1ZfDC6B*;Cfw$~VOEwh;yF=zW}?(L^JFCr6E()<nM&54+t{Ox|4%l$Ox
zL<V#t8^#^6f^j#CnA0wZ*w0DcANpx-7LkwMIOezWJ{EJch@7kvS=~MA1zt8jqIe7s
z=&_n>yG5jmpW7m<7j>;ea?_FADB-<MjL4A`%+TmKkC*n-rJHzu#I8nDm}`z7=GC}g
zL^D-ack5jHMM~T<kF1_OT3WBaZY&&nGU_-cRTb%fHZJx{QR9{3;I1`DeuiI)x=<+w
zvIBTo=3s<ls51YKXIaY^O|967YsVqTT(cfQoj+k#FPdpxlwM=ZHuRWgN+ZAet%zNe
zxMOX4-zUCn;5$uxH~WAIpA{#!cfC}19F7oPDMtrLqkMf7)>h-k<9#-8)deUNuC2QW
z9BVwHZU2q0iVYlQ09S+>|Jms$U;y*PkN?*UVE^<JFo5ay8Nk8mCl#Sao_-PwpMLUb
z1~5sqJ_DGqs6GQYIQ;|+;NbKVFo1*8Prv}?!74rjn1{4%f&m<yenJLtaQX=uz)WLP
z4B+F?vjGD*IQ@hSV3Gv`2JnZ7xlso27dZWd3}D*!Y=QxNWgP2~oPI(EFj2q&CfXDO
z_)0t}Y>ELKoPP3;4B+7O6Ec8#uF<9#zzho*z}zs|6a$#m3mCx1BWAz==7B#U2JnG^
zAqH^exZk(&oJ$6<^gQm4pFaJB3}FBC6Ec8<(@)3%CfX<ixX<Y)WB~i8pZp^OSWM4+
z25@lt2^qjEF$z8(1DO2gfC0>@6EJ{@0tPTqzyQu+yaWv3HlR&0fO%cO0453;z(fH9
zm?&TX6a51Nn8!vlYkA@Y1DKeZ3kCz2c$|kl2JkF+_zYlzfC0P+2n=AZS9D4;E(4e|
z!o`{a%*pFBfZ0<%1DHALyl?R?@)^MNY2y5q^Qtjc?u9#Pah^7DB6;6|UJ-9ng>9aq
z^D!Kfdx!zd^~+}f&jt9h3}6{LpNj#^qk>PuGb<RtOYqNQ0Ml!e3}9~aZ&IU?55$`!
z{L0g@WjR~pan-i=#{-@)r9X9AN^KS1Thj^+RWs2Z4<IklHIou_`-EQt5`MYw=n;Nd
zGLP^p<lmd?gz(Ea0pa(jKtAD@<qZhGyh{dzUlQp8jYh@{2)|4uApAZ71i~+)(CK!p
z;FmodBK+<TKcDc+Tmr)Hwy3vH_|=8;2*0{;599rlgkO>x1HvzJ4H13~q!JK*Z)2Js
z;g_lCqk_NKX(`MvApEjqA;Rx;=I0ZB2V?d03BNi&kMOJO;1PZ~9s<HIQ9$@53JAZf
zUx@H~KlAemzgICokMK(n5Pq)%3JAYM0pXV@Ap8;qgkN?_K=>sh;kOHMKBdt}uYmBo
zJ6@@M!Y@HU_|-M{2)_&q2*0}K9^sd{1%zLsfbhFFt_ujiL;>M<KcIl{dmvCi_+{<^
z;r9@P1%zMrY(V&BegWZ^{TvW}i2}keQ9$@53JAYM0pXV@Ap8;qgkPe7@XMA62){%D
z;g={N{IUfD!Y{)D!Y@Y)3BMo0H);J)dX4iiX|aux7AJ&H_+_w9_+>gi;g^wZUUw}V
zGN(g?--{W@+3K@_Lxf+lfqla7^8iVUQGLQMEA1101$cyC0UqI3fJgWh;1Pbg{P=|5
zo0!_~FxYrnibV4Wza+cbY=uLx*8T(GcP2c2!tZhbm^ZTE9^sc>KH*n@NBAYM`Ex)1
zq-8>cUouE+Cgih$Lxf*B{X|v+92KljKjCs=^T$8^1kLObe&zHN@3a&ibOQ1r<MU?{
zpky8*{C2|6C;UqFd05QBUQ7^v_ht-_@XG)p{N4qJNBE`NC;W0g_=H~qpYY4E;%YQL
zfGeaV0pa&pc-i!S#S04vzfZ!;Bm8EOibwbrw@dgHw@dgHw@ditpxh|ocPcgn|IMeR
z@YAJKGa&qa2VTBL<I@11MkC!U&=2vS<Vk2W(o2&k>q>Rwv0v+HG(O9?o<<|V7uINe
zjY)eNjYl)-FRIbliTkQNXbhZONB38!(ReE!LVS%zVXO#wa$uM|IWSC~92h1~4&2+R
z9q5rK2hPuC0Z5)?C4G%XX5ncx(yhOlWHwZti@h^nqw!_{U!(D10AHi=WdL8Jk<omO
zMgwd(U!ySt@HsRZSw~Ht%!J94nK$JFp(ame{wP3`Co^ve(B#R?+X6IsGV><^nmm~a
zlP5Fp)=t6pxUbQ85K8@pH5$)Dg#wMnVL+SGXyg}qO`gnvJjn@3^5kY1D1k;J`^nd6
zly3ME8jTA<t095$ZgeBQo}rgLjYf{jFRjsd7Rt6!jYd|?B6%`b$S@M~J{SL!)}BQC
z`7Zus+6Nkq7r|>|8jZZt(`Xd8tI;TKSEEtfu12G{NfOD8cEs&!G>UsY1~N1n#qDY|
zirdv_6n7KeqjKXUj<3<!jr2T?MpjRgCo^+JNXJq~!6$Qo`w58T$;^T7Cm@n1GxOX}
zKzrcI%={WA=4&)EHBFw(94yf^c`~y=fF@674iTWqlbMAAG<h<!NPs3!W_ko@@?_>v
z0h&CSSu8-4Co_i$(B#QXuK-P+%p5L2lP5Dr2+-uo%#i{#c`~y^0LhaawHC>fnPYNC
zpjsGSm_asY4yl1Ic`|csYAKMsYEyVYdfp{Za%u2hXc;CX9j+u94);D9jkkNjTw5}-
zqQd6e^W?IUp|p@(h?2a4kS4A#eKZ>5@Q^$>H8cD{)K2^hG#WXDH=)sZF@nB~MkDhf
zm8pRLzD6S}*jJ;G$={DZw}E_(##`X$Yc%pU_c=5gC0ZYiMo-?b1)sn@c|$#zU3o*9
zxSqTrfiG`J;L95l`0|DXzPurUFK<ZT%Nr8-@`ePOcbILLp`>|-+2H~-?=U+;faV=$
zM+(rq!)%8D%{$C?3edd6>?i>fg?E@8EkN@Qvt0r-?=U+?fXh3~j&}w)xYbX=)AWSw
zuC@uLrzda7f@<DjHq1NBhIxnCFz+xM<{f6kyu)m_WU6_G*)Z=g8|EEm^}?ZfhgrRF
zXx?Eq%sb2;Bx+=ucbE<H4znlKa$E)ShBc^9(&|8;d-8^?;l|_*#ov`T<meIJVfKe<
zx;=Tr-?4QLLI&B#YB>2_laj{;Xx?G=3DHo~yu<910yOV1`;-99JIp>U*J$2h_BR4F
z?=bsYiKcmn*$r~L*1W^)GXgx`VHUi@Nw~TB@`ePOcbEn5kPi)-cbEn5kVx|mv)~=>
zjhLS$Z^*jJQo+cX2Hb}{owRM?;maE`Q=1d~I5=eHy1c_a@`e{P4gR1r*5aS$9Xeav
zFOvmKK8G_|hYRn}nKJO9B8o4(LuZ@pgc4^Xd56vp^7N*8ht7^Nsx<G=3G)t}Fz?U_
z^A4Rb@6ZYJ4xKRX(3xJttx?T8baoe@d56wknYG|sY2Kl;R}+Ee9Xfl9e4XYUI`gDH
zns?~T7od5E&Orh+@6b6|lGeOKXMq6CJ9G{apm~SR!aSc-HSf^rl{?Qe%{$D3cla(^
zF=?HFhV}I!=~eSz=tC>Nom~P|P;CjH{0^EA4{9hzaUSd%-ZM12roP_3iSgJQ^$lsd
zHM^$1v4-8R*){cHc1?Xz9sxAFroJRVvui*(CnZ3$YwF9Anr7G3w+PVe8c@#nL9`-D
zKLYt_c1_`%_6jtruxkooc1<D7t|^4sHK2S>LOPmVQ<&)v3$kkp`v}nNn!>*BGDLPw
zVU_^Rt|`nGpxHHr{RC)sO<|4z&8{izFF><v3f=B9M0QPKu7qfIO+h~mx$K(4Jm)r4
zPS`aKI}eZ+7j}&^rm9>-MaiylHj}}l*)`5M0h(Roj2EEUHO}S&G`q&pvWl8r<7in$
z&8~5_9Kin5>>4M`u5mneO%2&K?Twp>W}>=a1>VZXXE^Jy{tGDSDcC}=xrEqi5y8Yv
z9BEgpvj`>$NU4(u^vU0KYB<66F7@{)f*pieT~N0YOcT(kW)kcuv!STQ66_>Hs6{yB
zjXT%yiJ%Q*gRN9U3Q(?TvdzUny?-ViZ?+Ml5MFdo1K3tTM4fg9z*GU2dV?W5B=>IN
z`q6e4z>MV40C-Vj0yC5A@gXCnR-O(pdjJ8SQyxWjZKN4FOHy3^HGj7_(Y}pYlfPRG
z>#P>TI;+LW?)uL?^5PVC{U?97xQ$-_g}+<eHnlS*r{?b#`|7L~kFvAiYYKn2c(e>F
zLy^B*JVt=#?-rK|(EQ!vu>v%Iw|JZY&EG8^FF^Bmi^~LP{%-LE0h+&CJW+t=?-oxI
zp!vJSlLcu0Zt)ZWn!j5-Re<L27MBaq{N3UT0h+&CJWYV+?-oxNp!vJSGX!Y<Zt+Y3
zn!gJPMm~LL{%-MX0h+&CTq!{FcZ;h8X#Q?-wE)fEEuJGl^LLBq3UK+m#q%BZW7BA~
zvA(a-g>K&ozQW%vUQ#;+UKn@y)%@L3+5Q!P@OMkC8M-xpw=~G@V)A!OgLN0HWe6^{
z3DErA(h&DXPX2CbsJ@X4f44L;$vdp(@0P+ktEJB5v&e`1-5v0M2v<sa428#I_^<i9
zrSbM)jA-HSmNeZ?^LI;{Zm0RXr7fiiG=I0Wl>nE&Tbks&gw%w;Tbfc})r7xW+9OR~
zZxbg^hO0@2(~*UNhddc@Cdus8!E(pImN0y+9WKE8Pgfl~vF07P>zcQ)DZi-xz<@1f
z0Wj2xivhM05K((G<ZCs{c)8l=B7lhkY&D)CTgx+2wOWAb*F04~jfyg4=M?Q55-NrT
zqInkqDOJ7{U{?VHjMDEf1ebKX4AU-6!Zj`Xi~Vxx2S}`Cg?7J>I4!4X_g*Mi%jw#E
z4C9<3Zs8anh-%1#4%%-NuQ|)v176mh$i8)}G^<>4Q2f@fYxhr(U+ZLX*K}Qh1F>7T
zvyTGxQBB9itvfiE!)>S|38o3K)WLfJ>?rG}t=_sGV5gdE5UpB$gu=Ayhns?0jZ(Ji
zhnu2$oeAtJ*R-hrV#qh7VcXOJ1iQ)8#8CBfCNNz>+SQRP+U^;aphKO+kZ-0RD&k9n
zn#5~nrr2QP)M>2EJ_07FPZ+YVfQjm8)_InI$?8Oc*#f2}<{x$#SgHc1sgD>kCv_N_
zX%}_#`2gJlrmOF>1al?Y40SP+K0v_C#Qeob;6MSh)mE(BAp*M9CoImP36^c18cfhz
z!=x9e*-ZK<0X^zqhMXV`(yKmXK6;H?qHbZxNiw*WsvodyCrh+tY8Qf21e~lMV5X-^
zYAaL<<EeGIfHTz;MmtSfbd@@T?RL6=)kaMU7qt!A+Gd-oodE_-9{97N?BRU~rVKn2
z#pX?hLqG_7x544Q^49EzVm{aUSk?D%g*uV7c|xYDp`K+fPYSTq+pNG-?u@>Og?U=f
zXmv5m{2Ku&wV2U<E1*tY!PGVg$f--1+A{(Q%HcJ?6Hrv!u@9aV(4wlD^m78*)aFd>
zc>(R}F<$e6fDUy!qy1h$ms-h|eo??U6=AfO1x!%KFzHtWOjHXAUKKD|UCyNcAYiI0
zFtyhNOjFC4!0Q5bQBN}38v>@Q67zXezzp>$!5;<8RNv(_ZwZ*K-e67tB%oWJ#gKOd
z%u`=u$h!g-s9zJnVjPpVM~!3&-WSlTBJB7-3s|Cl%~JnGz*6-KM*Bd(GIcpaJ``}W
zdXC^D0V~wgjP_RnXR6283x5-^O5Muhd@SHRHHY960T-$ii}QB@YtqwLZNn6_Hhm?N
zGc~$0-Nu|E8m&uzo6Qi_==$_(UT0}^W7=WNm`1mx=Q5Rk8r_~QGdo+OyVE~p%>Ej!
zPydM}uF~lK^sUUHTBDz*6?3T3=)v@xOf#X;uhY9R&7?+;rBCE_DUF^=-_7f4HQHbd
z>)n5j(OPe2`IuMa6lg7&1x|~axk#jL&^Wt14D(?z(jT;WhHgVek;I@a1XyZ4q79lL
zi<+(WM1cqCJ4}_@iq~xAKCliz#Rh#%Kd@p3a$2_Y)yV9qibWqJ?VIl%<`$_~^eND_
z+v~BYn9~r}f&=S^?}?<$ol|@`j76XO8GPbM&)nbj`G7vZK&i|nu21UcmR)lQN@JVv
z+BdNV!%;U=k1|8Gqr*)-$}D5}90vW_It|fc(fi5x-Wrc1<_7>M%JBIN{xHSQGO=jg
z3-D>><sZ2|ZScweUa|sFx~U!e0DO%zFN~xKjPx}J0$rpLSsw2ppONRF*~~HV<W$6n
zMejzY9WSv0W8*?Yk44wRt8*J>G(K+ba%03^f|%x-Q5}qRWz4j{7qO>C>D4+MU#olQ
zIe_nqk<~Ls_jC(x<<nJU_4JP2@PK4q9h0pHkgYqe!jq7BjfZ<Wj>QXrxh^ITO`wQ(
z+)4ah4<FPue<9MlHYPVHP{z9sTV$Bm#pL+|T<)%3gkB#@vmlYxGsoP&4X$pEn?;m*
zEKO^>dJjPiE1u*-jgX|F!-5VTbuOCCY_QDS^%47Rsb3E((+fs*gVjJcso;kYjpQQ^
z%YHapuF3M{my;Hs<~KW>N%gaY@BQ3$9^d;rNMamMfI!edt}v0+ON{XyOk!44;?B4_
zVy}n+ui0w^;!=|bL5|LC`nYSV1&`qtKxFkUU2|XnXzmwH>9Wo2n9Zc-L^He?E#F0x
z7<2!q(mm1Lbx5aSc1Pv48x`+5WE7#BdQV3ehgNsA$*o)0T*I6jb!#@eql&$MfQRQ{
z=<o(M{yJuv)1|-iN^r_e;584T0HY=MTr}n8-f<rrCGTZFPnW*lD}ApneZedJg02N~
z7ox4B?l@R%j6aT}?cs>D)Qwj}?DwRT>PDhZ(MOL)yk6*dl{vi>k(~$hSr_{3<%nDD
z1;*w-UW?#cB4!uTSSo4ELmH!z+bxkK2_5WbwCpVrN23KDuX4`cs;3QltwW~Kt&svJ
z701x#OPJ=jBj)|ziP$}o=31t?-{J%5Et>jl@<j`}4RfuZjxm07w%-vEla1bvYthPR
zzt?cB?)@VovbVso_Q!J&v?S7x-*Kh;4D%?jRz1dMce2v^>ehMca&0AHu4(B&DNz4?
zBW^$U>UN#&wbl}2^DVf1B_d{St!G7Wlw5@-NJIwe;m|W$x+4*3*asy<aoDISFZ(4O
zuW*&A^%Cth#&@%`E;XfM6EBU}PjS|-Np|YuTx!az0;cciMF$+fh;F*Gbv~DxgLFPK
zyB5wd%*#w~&~}`cMLL(6{-}LH32t^rZO1e==vq$=e%_epIja9^njc&iv5irSh)y-l
zzpaVblclN0xFtH(%<3di_8+sichhD6;1V$EWKb`1WA5gay{Drd&jhf~@d{^*e~(RB
zqp$3_7?WA9`~|KYM_nHTCEfPZ^{g>nA^3T0&!m@9kDj_I*n-Pc?=`mgIlK2^lbaq_
z!gk|9DSYiH?ACva3-80VI^Et0zdw!8ZO)zvlI_F8++2+<V{D&wk`8S^R!KTKjdk*F
zgQ2A_TIU+&U^u_tjQ1Mj@GX5al4+=T5|{oQtLhA_WFO6}n32Rr+9aoXLh^L~3qtb8
z<8r<pP;=c*<A>B_c|E}6&`WSrNWNl5f}OK982=EGXIrd5gOPJ@a|e%q(qK*S{V6~o
zBv0D1CnQhzKNpgpWU(VfNM0g;c_De)X>43bo;R9`83{IasTAE}Rm?~#W+Zr`ppg8x
z@p`Z+A^D0K3EBuk@)a`@toi&-TQMUs$`vz`Gt2~e+!ZsDSMYL_yw8kQ%t(v{$?1_)
z#f&6{0dY(uLt}=D8423r!AO0@jHF^l(v4@#iWx~QwiZrXi+zWR83~vT6*CeN0I0!T
zF(c6$+*xRFSIkI^T$eT-S&v1tVn!mL<11z)SS85*##U>^j0AQ8Wf>M)zB=0?pkhXX
z;UV(X6*Cf;?PedfD`q5IFaEEXk$k5}HYw$+VMbD0!gk?*ju}ZFW%JEQ2>$1pk<^R@
zRV9_*&E6k82KC)~*p%$<lJesS$$!)3_TIvfJ%o8>sXZAoqlU6X_9hHb-eq#GAqw4J
zogoTS^9@l5{=pEX2cEtm$}j(y8KQiM%Jnfsx$#PLV8bbP6~>>s4BgbQTu9S~dK=vY
zg>44lC}8fgbBxND)f%J5Ghn%t*F9wX8w^-<Pf;Fr;|46QJS+>KZ9^I-+nnKI8`2oI
z4QUM9hBSt4LmGETj+RA%wjqr(lHUN(wjqsS+mOcDzHP`lWEZv#Y2x)6mer%jm*FAw
zcqXRl@e<4*EPLbOJ7g|+6z0XkXnOT#@WlE7uIXq7x1X%GiyLVw7g;@ZD99m~q<LXv
z_2i)o_XAwx!imGc)B3hced-w|q^rwZ+Q=@$4x0~F(^`iqf_gV>E+{>hXK1PidRV&<
z@4n;l@Y;o!cZCb*wYOmh-MmsP@*}Hf4eKG-?5fmQNom@!#d8k@iO*w)4dYo4<~3C`
z3;?GGwIiKUli`MJ#X3%rI=0*tvF|ro$2(a^DeM%ny+C<}50!|`nsYV1UHD?#y4CC%
z#s-<{viy2=#kO;p4Oo673^d*}H0!YW^A;H9ygKgZfTRR&V<!_GZnDlKtIR}zxkg%d
zxZAqD!-Nqy(ruR|AlQJfV;RmwpYE~*iIDD6yfb2VWI%VBQ=z+5=q?r2RD6AYrT=J5
zjB0iB?EtR|NF*w%sc4gmYAS_i&%~Fe*oTq+71dO<!*$qUkL_vZ-;dxSDp7-Z6Psn)
zWVocys?c39XDX_xMuSmNO|7V=8p-8mf=|K~)l{sR$-B)o8>2e?M=YAjd$dYxMKzW0
zSZtTr45)Y{3z29=H5IRE$)h#FrJ|b3#&{r7Ur|l1sHTGWRZ&f?sHSe8rY>4VH5EIu
z71h)M_)v`_=c!<)kDSlq$a!k01ay~Y@g;!Dr4`lG(t5m~R_HDjx(kK@nJyK&3ndKn
zY3&udOGPym-;+0?nyQaSr%dV1xSRMgr39Z(ru0F?{4AML>Tbx_Rz~h4Q+hi*e3?>a
zDl(;S!6DzUHzrf6@U<|*AHHAXpD$CoM*~K@D^n`ro=oWx#Sp*bC4m1Re#v&=F8KTs
zf{pV_SRY@el)#rMCHN|3O1sgDN$YRy7aotE#qsF$@?}cTVJm+QnbKx_{q@)(bbod1
z5T@p{LkRwX9da29EQbI?rj%@o|4lNbZK%&i*&*XegV`86gaIx)gd^<J?2rd}-M@t$
zqI+u7>=0kxlrz+mH>KN`H`P<ul{Y2u<xP)7AN%sA1pkt}DQD3?mp5fA`SPY*M82TB
zX}=N+@5-AF0{G|hrc04S9|{Yv&#*x~3d>&*Ll#vgCJUktW*p4m8u*IBW6@Q3+|NQ4
zA(43(0z8RKy1zP!Os?)5m&kk&`A{Nr9R7<$COs&T`6K-IB{J*4JNcI+G9N)|o<t_A
z=1F80k+4WgHisl7n?sV4%^^w2=8&Xhb4XJ1WF#U}$CZ?9KFjHamq<#MLz0r^kfdZe
zEGb#u&OW~dHKe3uc?ahbxV5BYd71z%DOnCnN|tx3xg627q+~fPDOnCnN|wWtlI5_Z
zWH~G;Sq@7|mUqvv1X@zE{LM5cmzI<)&rG$W@wB95c^?5<QnI|S04*t5o+Us_N|t8}
z(2|nn{RC)9$?}}kDm0Uplq`1((2|nnxe`rFN|p~0pd}^C2MW-VlI24LXi3TPp$V2v
zOG=h|YnZf_lq?@5Kub!N!;+Hau%u-9q#7omB_+#YNy&0pQnGxiq^2b$%gY65Ny&0p
zQnKtxN;XnbGHJ1YMKAIuIApLy4Xqbheyob(prRL94(mmh!+MeBuwG<2tQT1h>qVBs
zdXeR@USv6}7g-MLMV7;Qk>#*nWchh{Z`68`<*;64Ijk314(mmh!+MeBuwG<2tQT1h
z>qVBsdXeR@USv6}7g-MLMV7;Qk>#*nWI3!CSq|$(mcx3H<*;64Ijk314(mmh!+MeB
zuwG<2tQT1h>qVBsdXeR@USv6}7g-MLMV7;Qk>x&mk>x&mk>x&mk>x&mk>x&mk>x&m
zk>x&mk>x&mk>x&mk>x&mk>x&mk>x&mk>x&mk>x&mk>x&mk>$R6k!9#b^1dm0k!9#b
za$2;1ZAZ}jW@`byyZ<|4pNDnOT$67zjNykdATbFZ5EmRlR^c2g&3iNWf+K_pxW9*c
zM-KcpuIskk1J!$sjzRR;!ZLXW>_Eb2O2WNNShU`@um))UVo#^Rs1rPGzy+P6#I>b|
z=Zye~^J`X`2~k0=eLSOQb&-311tm5~`AN6PS*tEwWXF=bF@)+y%w4<~vU*;!3r3xX
zYj?r5x-JctrR&y<R#|^3viOS@>s#|s#C}Y&*nWs^mA^!5-7JRBTXZBN=J!Da@HwTG
zK8(7p<YxJirv<oR)cr^+$nxW8D9bxfMV9BgSv~*>wg~W=JQO$C5$8umuAk)3Ifp|A
z?t-Z3zJsbdT;%31jEV#=v<^Ebga2z@<l$*jq)Vc1D=ZiR66_kUK(j~w7b|+HhkHjp
zK>TeF_l(?|ZGD-CXO6s!;cGqIJ!<-c;CV_Lg4TL#G{f>@v~c;o1$Tq?ZF&6&U90PV
z0l7#Mc+ER*twuysx*=!lT8;E-HB;BB!^>!fu2rXprw{MNa2yrQFr~<9qjNFKHQEcd
zq|#&jO6zKj^@6+gP}t1F^G5z?Z(KeuD$i^fW1}{ps6jt%;q_Aw>s5<6)V>Sr^`X`f
z?D=`bo*?ylV3_W$4<qgXaqIO_#O*D&UVruE|J-{0&BN0>tIkHkA4mL(?MnPfq>4#L
zR_lrxLB(ERy-ly+Zp9)&#iakD9_|@+J<1wXEbdhdV?Jr^gMMtkm<isYD|X(`BK8Iu
z`FpkNiro?M)&t#PcX}1;)*W`2SCQGBFAqmTcYAoI^vI7QeJA6Oz2F79hwk$*X8Af6
z<WOCZ>YsW7fgigCIW&@Xr(kC@3U4m<uI%oVzC6ssv-N7z>#0M|)T_<mUbrCzTk@%b
z9pwct7&QTT2Q9WV5}LAqU=eX|V8czj-;;z~i;8o~mOoX*7B5Y=h^-!Wi#RBv^n&OX
zad5<4Omz{5e5!~;y~`JjT8g}bA`TA~v1261=_95Talwxx_H!~$cN(FK_=xGwzwXZc
zZ;^<tdP2?a{1(UEBW9-_cQZR5VO<|Fw_;tf3Q4OyX8PTUCHisGU81qZaHW01mzEqo
zXFrH}R!2-51s$~p#Ry9Kv>9s9ek|?1y0mSGHdzMWg>Gr@HQklHSC{r)bBHc&k1p-K
z<``Yt1x9-hQ@TN?^x}`alwNRCy5UnP-SDZDZV09HXI6YCol@_;&@7d8dGScyf;)LF
zI8T>pXVaaz-MUP>c#SYyTI?G^i-~Q*Zho8THagEVm!h<z)*_>zjlLObqpk+l><yEn
zzvUjplHyc%;CNe%xi^w}R&@U#_P#tms_Jh4ZZmU}n^}^X+{utYCYc~xLP7|usGz8^
zf}&tW1=)gv28|E}>jJOhuC1t5tFdZb>aJDmQmyjVYOPC)ulws#cP(zX7OLp)dA{e~
zo1tRGE}!<-_x>?6=Q+#w?B{;xoacVeNa@day~4~MDc$*=w~EXd#fSMve&>ynqI~T4
z-smY53-KSIj-%u`|EHjjT3@=yTkz*lMzdcZtoUuWK{e1HlA$)`ZvUA{1F0<8Lte=i
zj691C`mpyxM28gR(V!?Ya(?FpcD62q92P|t<FTL^THB?Ra;{{y4(}SwmT_H&*AbZ6
zx!x)@MK!~DUNcNm&2YXqui90`FYs3V1*4YC!OJ5q*LOTuf$&J{@sf5+IWO|c**Qwe
z`D3|=4v+oTn!Ae2d8t><E;P!sEay_`t}c{w1uCQWEJZm-{se!}^`(iK@PT$RQk0%$
ze$7Y5%Mf~`2T?RM_EBE$u)8{sgJ3V6Z&|Q;^qvunuvb4%gBjUy3&TCjuqeg{Sd%Pm
z-VVWg8ZSTqI4|0iHHJN~PSbW?6uzeszNZnsr-AeR@I4Kz3p3K=OUZT6OSnFDsJ+eb
zJ&o`^4UC5Acnd?e(=b57_cYKL)6(7e&mD=H?gmblbSwoFQz(2-BYaN-C%55y8sU2y
z>dg#0oeba8$ovj-B9pGgpPXd1A;`rJ6ko~+-_uxzwn<_~il#?f(;N6|LinBr9<1OW
z-OI)Z-_yXkX84{4l&tVQjqp8<@I4Kj+BjW!a)$3|^bOzBs2ZkBj$WDpFSAv--^;>1
zT)9heUJ#lkB_V&bQ;oK8mxS+WK(`9t)6lZ@G7`e~G;&~p?&yT?X@I8sfA~F(1M)aB
z^zDE?3Gi?9o(4Je!Fw76;d>hBpz1nd8Ks;R34nUJ)HUOLA1CA01v%Ug-_wA7&fP1f
z;^7}(elbRL-|v;mdm4KJ^gUV*+coDHf@1_&y;eK##whz2zn8%o>A#mjcko_@nyTJ=
z83g~b_cGW@!Fw58G`{6~8GMZ*crU{RFX6Ahm(hvno4l97^qahw@g_Xvy$lKy{=_El
zWo$%n@p~C{uYx&Vw~JeY*njss3M(MwFWyn;g4eftN8v171@6D2a30*jI|>Awe@EdW
zg#44<QDCOQI|>|V!8;0Uu;3j9g5Vtmg5Vtmg5Vtmg5Vtmg5Vv6(*c5a6bOQM6c{ad
zM}Z)CM}Z)CM}Z)CM}Z)CM}g9UcN7S=;2i}D*n)QyC@pwLfnW>XQDFZH9qD>F{_-7#
z%eF#)A9pTZPzm2r(86~VFb*_b{-a!yzPtzMKk6NYLEZD_YJ5k5&ye691x|~>5%}o)
zmqg5g4_o$-Gst~AJ)$>$pez}KPL6rfNCMpHk-X30ZyI(nqTQ(85-5Aeu=6m-t@qqJ
zz>9jL)kj60F?0}P-sHa*Fun1JIk1fUGt0Y9ep>UJw;}u%KfJr8;XT-&#!|chvW6k*
zgH{d2g2bn_OnTq2I}!FnhAlh<48qSW_W-PvcxPf*H{j=%d%r|pptW|dQ`gw5i2Fyp
zh#eAfR>X@qTh7GL1WD^AEGkX+v;Ge%O8tsA@nVI=ik*VjAEXT)G`)(=Ru%iLPyU|K
zDDPc7WO@~wt}6D3AKtAfs25xM$8Uq<dH!0%z6mv%1;MI-d;2x%k^)ZmYtpH;wj%{b
zq!;mcKjH$3xYCc<fqjNKZ0zeyedQa5{W((TJ&*b&zs@gt=ddNX%Kip3!ywS{hk??0
zqhHJ}v;&p4rpwq4-&gJM&g-fr^`68auN}T`R(oTiQC`yczFF|7mReJag}B`#xxa{u
z*<&n73hxp~6W(rkNv92+#F%#&6%5166+=I&0lw34Xr$FxHEHPUtAKxDl)4h$K2%=5
z2w3piFz}*(Y51?M43k$i?(vD+U8)1_^>JtOb;m;5Y9B8c)&&|hIP+AbV7t5dAQt9V
zzPOI&6Nv-P{Osm)h=1)TpWZg&P~g`M{jEP3cH0HGE?Pgv)UQHQp$YjmjiUTF9m|Gv
zRBN<73ofn9lv=!SAg$pTS=Er!8igoaW>l(IalF=u8%e)4EEXVPBsXb|q~UQ~wdQlM
z5vi9O<=(42Y@G@pbv1waLxiUN;&(Qm-UyuW@dDL)l|J@{uj}KE=DS#rtdD0j7g(Aq
zAJ10J(Q4@HQAgDr=NbBVbidYg1Czd>NZviq_+#lnzX@K@J!Y-fWq<Hl-QJw}K-X&^
zRBIZ`Ebs7W=T95<9Wugi_T}86djqRWHRYWF{aX!%y8^jd)9+ZMi<PKJ5Cz2)V|1f0
z>SEoS=ANia{zBAGibS12QQudhK7Y!m3=c%}N(X;m&jqXI;jF+`Dr(ykhW((>%WwCi
zZskYqPz4?s<kI{!Ga2Ob!MmC#Qqo|(q8;VN;@9>G!<Xv%btpjF^2-1g>H0K)*4g+P
zk66tc8Kq12-eg(;F896^@}b`FxM8PsID4K)Nk($1|FFt0^QhApX^l|9r~Qv%uaSl-
zfblF5*ZA!;T8QV5`3&nZvaCPu!ES9-4|Bgu#H@eJw|{?-FXk>Uzpjxo3GVjU@=DA-
zftay<SehesmX74=tEAW?I}XKIKQgISppMZ(_CB&o!P%n~*}GoB8C!QP#)IOhjGFe{
zTeG@H`>&L#{M6r5H0#!j=V|(}9-)1~IC;_H68$QaAKBxvXlbAA6p+4udkN+|T4x!a
zoGWltvhb*o^c|AEL((_cnjz^M>q1ES)*_!6nKf8DC#4U;!W~&}#JDJj#`#0iH^;=Y
zU~WbtW}j=KA?aJQ--m8^DCUZ6TlLj!{Jqnb_u|kve@OZcN#7yqJC$BkivJyb6wNy%
zeJf&jOZqw-LnfChG%OvGzLUQ(sxQFFwY{^WX}^I(o+}~g8>8eSqxx3-aSut~$AqMB
zC|M!tJ0yK$?=~cT;|Xe|L(;bvlD;t;E+m_~OU}nzoG(m(!vwTB50n8c77&uYlUB6K
z<3xp|?~wHU0gk@2V{#QC>08U*mC#|6>Hjk6`?gxL3QMtG=61^V&y$RKAlLx8U32A?
zWEK7jo8r02vXZ8pv#`eIc9YZEjB`BxpX8KH<SJ)R?33n{P2?J<CJwMioR=Txoh-Hj
za(fD>cYZ=JRX~H&PB1NgC$ihh*&UH{dkGleybOX%ZeMpO$`+8m3I0t<-}yBe+*!M`
zo)(_*wU@$9TXnS^>jy3$??b5Wo2L68XMvy60%kYCS1j<a><d<|Z-M_s7UV*7P|b8P
zDXKY32=)<RIp^Wecg?;6Y-b)GsWtlvD05b$gKB1YeZM`1NX<+E8RtqDV1EHs&Jh?Q
zHM0cNIQybEYi0|`J2&FUxn_=l2Io@dGgrVs=Sk)>Pe7wH04q{Whme$7oH_WzS2JHi
z+MK}z2M8Fg)t$rgEXc)CpUqm}?}s6>SquCO@GS6i7|Aw6yqD?yGp2i#18`Kl85*YM
zbaM)f7GOD7qjz&-1lZ016g)RpK$%m@DX_JGl(Q}Bmm4P_<Md!xJhx4S>Zz}{z~AqL
z3;E}c1yCgFeiLm@LLpK2+es#h=Dc)@ruExdfZ?2S8bG@M%Xx<(yC!!=5=El!H$8a(
zfFe=%n~_|N;-;J*oQi0(D+n^kj(odKNYqU4vaG&w`%&-^5;cV>614>L3j!v?w=VZ1
z&>p6z`C?t&{pZ2Gk8(eKG2Hv6d2`mFA6x?W5>sDbn)aDUs`osBq=QNJT4L7H4MxKd
z5G4*bWsZRQHDu8tggItKf?d*LmklbRq+KD&Fl`M3PVd>S&XcsOS)(K^7z|0fnnP96
zjv<FELOzpwC3h)Y<B1+3<gDF%npvkd=m8czY3es=rhSKGa+#k=(#-jpNV23^r^p)}
zEPi=!CM<rrU;NHSE&zIkAKax4(pi!9hTe!gR%)!sLw+9XjXo-mZf(%5jCPNqPx%5C
zS*0lPdau6s7=68Htna;s*K%Ehk@IRFb!ts}P{c`!<<<SUFXnh(%t?mV0SgAtp&i7N
z4VPgsZa8>Ri>9CAOPb9Jp5~+OA;{%4!|$F(p>Un<Q?5GEU7w=k23^CJoMGrapBeTu
zQp-pEd}kPSs`y=!&rDykjDuM|LK9re@^5SCpa0pg;Y3TN$PMM-+198IWDqr}F70ID
z#utfrl*LFH`b`iqNkokDMWhUG)O2e@cV<o-6bEWHqE3;hhxt)A=w8%igXe*Kvq2xg
zK~KxnO?{d2IhFF64X{}&DW8&*An`os)4#f#?_^P)S8QI4>*mjhU+{5fix7F<(DioY
zKWsV0zNYIf0NS8VqH}e95;8blGAL_cLm-25eNtGrw9C1Av)3-#pnI9Yak~D}dPPvx
zdxlFYG~aQ$H<-J%)|C{#Sl2H{v~ePQUq9Mn-5Y4jv_bnb+Dw!I(WXnZ|MJT)Q?K=z
zS%WTQrjvF3<3IV)uJWTz)&r{U(8DRMRyEr@pBlC;BfPx7SF2jT**XUw#&{l&b3vof
z3F~~yS$E@44}_dLKmTQFw$<qaRe8F!)_a+eq3h$3$#qif?;;aLOEmmkmPu2Zfmmj0
z`8>BSZFrhO9u<OD`^Sd8UJ83F<g`h79`z`Gonn&n_rA@}5hQA@@rYVoBc*>o)CZy<
zqojM^(?9+My*qj>o9q^S<wu77YboKgkUWN+drQ6FuA@h=2p8$^eCX2xzwjenR0tvs
zV5Fn;w?Ou?q>QcLgNdZ0ydLTrD<wY0FQc|~57Qi|lOWb5xl8;5gRat!LjPIX<=+W7
zWmT8r5rC-cv8FG;WA47=Lrz)9DGNDeA*W1FY{0q@a>_zZ8Q4;GBgR5I9P)1q|GtPr
zL!u$4?7%Xtlzq%963Lc@oU$71!`k_(cFc}^&ncKLZ|W|A{eDE#j>rFukW&_N%0f<A
z$SE^inou2@ei6It$s<BenP$I%{oreS+St}w{;3pNCghai*>Mv7p#K^l(Y-QS{y;oy
zLr$6Xnt|Q$!Dh%QgMNXX+Iw&e)c>$9Ez`G(?>WRzxdi6}nYzpv9NRd$2~a5g0|IaY
zfwPTFg8<9<-b#S}^8Taktc8Z3*-Ai}vlOabW`KZ{W{J3g=30uj@MTvv*x#e*8!%5R
zw<_TYf#!UK)0N5r0(8elrj-Lz9SDFWp675b)K<B@Jq)(?<s_|gVuo&<&tPm<?kL8O
zEN4%6RqiClk8Gzu)`ZHPC8W$5T?x=GAt@)yjCPTutxV#O`Q2J&$SDgsWqOjsFyxfs
z0TFV_LQWYLR}Ew_mrMrtHmsO<OuPdd4z(_Qd0U~}fCk@?Q)V~x!K3IFJo7?BqIgn=
zoU*z*q2+{}vdV4qMVzwh0sf6RWxVS#;FJ;kn{vwHKL;_<>a&Y|7N}g#Hu&nZYnuCl
z*e2X8-HaA?e7YIk|2VoCr3G{|g0IlcE-t2<ZD2wEgXm@hQJ+odW<SM$n0#(T={XoZ
z{~X$wYVoh9jm1eDYwS15=1lVqgwh=t2qmx_&p;@_zsx`=TPZLQ%EjPY8VF6*vG4=W
zfDSS}*$nX44TMfa4#nKIL6)B1r{p!}`vVy0$?qrs1~un=f*ElJSeiXS)3lG_l>L(J
zH0#w%5IWPm7hbh2z$O+(HFyX)j-~mkg;Cla9X#Pu&?;8zato|hX4<ng;GRPfG-M$I
zD)<+dY_}!&BMRJ?L5l9iay0(=62!k;5oAtxOuJjs--}31JN;aOynCEI376~rJPAV~
z|4O}#JVs;HGOhU)N;*T=s{$#13Z$H&d)MZAQqIt8{Bks}Wx55r-d1YbuSxFPfWf75
zU*M<fQsrOZr|V?y2kE6M_in9u#-)%lMb~dFG3^y1Wj>?~5j%NP^lFYw@~D~}#v82b
z>ul3w!MwoSgsn1I@2lc<4(V8e)*7O_48*1LO%{_i`c$2crrE?zy7Qid&mJoIH0x<E
zpOzyT-mKRsOmg8;EM2vX?$Qq)ufjd-K*sx>ScbA=ru~)<*z+B*x>}|6e^)U9aY0>d
zl{?RWS2I)Kg5hNCtntV-U2Qh{K=;j0b!)?Rr_>&i`e4Mg$BWeGDRmbK$*RVm(Yi$7
z00pNHUkFy)kINM57=GyCXoDY@D>%DtYsS6Uw?@?_<-5d#U2RgnOFh`x_TeRn{1Xo@
z(1x`#@mOU63v`|}It#eC0d}~U=h!qeF;_jYWQ1h8bzI>!OGeCJrs?B6_{fqG-A8Ep
zHl-8L3g)T@m$XUww{s}ST=m+KZBo7MDiwZa$?)z)Xs7W)>&2LF+Y1Tx34Rr{k-<zf
zH0{hLPS7VO2lS&eFGVjQquH2MZH=0C{V5^+D5M{S^rMh|6w;5h_VhDl7zm+BtB`)A
zMNCtyPqwE|#u;hEG8?~($7X2KiW4NHAKBU5SPTa%q#tR0UWY!}k~~3AJ%Gc*^iDi0
zKT%KcGFC0U2s@j}lk^0)zO8fy-^r8p1eq9i`b2DuCr?!|OVh$WI89Gbh?DM%7|FBr
z#8W^C&89FqeKI65=?j8uwaA?me2#9;gI{D{9B3x5(9_JN&&@b`ZA@OTr)VT6oyUuJ
z$s6>vDxAfLH!5<Fm41xqCO!QTWZ3CjaWI>_Sx+<9QZ2HC@Kzk^LQ0<@kdjH>p{H)A
z%pI_6nS^0tR#8j;iBf*y%RC%M0Li;T`cX(f3h77K61tz<s|SqgIe4Om^rK2N#s@|<
z$wv911Rp98(vPrkH)uBBY=0PB7g^-{Y9ajy&64SpBi9InC8QsvdB9%fT!BY(<*xBr
zXq_5|cH%21rKy|col+<tm6K)1y20T^6P3FO7?@ay9kj~*#70A-b1gKM%7xi1reF)&
zl^m<BNN`&1K5H`zXFn`g?sMgGp6~qkegMyxo(<*2a@wy0c%kfO0NYvoUjQ$cJqCbH
zb_?LuvNr%y&Z*#KxvxpIj8g(V!F|1qJb^0bS!C+ISw?z5jq?EX3ipq)k(YPQMXB7i
z0vep5qz}9;bsXr-ht}b~BW5H*lU7?!KRN_Q7QD#gZt7&#j_76UOLS7@_i`k~)fxC>
zQ+Zjs10$#IbdHG2mHQbefR$G$_nCNpRbDCX_|E9lvZ^Zk4D_H3imE<Bo70?&PC?IB
z%l535SlFRe)wqnrywApO(%OfJUsvNJt6Ktj;xSOwKldYe)h)rQS2ZBTZSlH&kx$i7
zbr*3Z#&}h;azBERRn?;0I?5Z;k3#wp#!E;)l4+CwUoM{~=_!(N^S{BQa&h4cCwKfh
zET2=dbs_y|ge*~$w7Srwm8|+(KtI}QA?V)O$L$xvE^!XRgCzSzT=B3;%FaG1KzB+p
z=(116$pSQ-WAI?fJ}tm<=HTI<eMUgkISUGI_E|||J6GYfF8jX%N}QpL_MAj3b>>3-
z$UZL*|1#%ON_#;-O6zkBbit}@wQf(q!!3O+G@)#b?h<Hejij=^dKncXEBzK8b=iIj
z+38z|@_Olhh*_3Ci0SHdhdUUl^pkkVW$Sf^^`f~O)>Y2y8QJa2sU%w+No!|#<c~wN
z>;SzFGqq_T?^rnGp$1FDycr_<h9U`zj0-4(Ul4o=e&Q>CrfDm4+uLv8AX)e~xrr*=
z;e|W79V?S{RJ1$`TYUijjo47H)E2R!2sY1#VtqTEXHe<fLaAJr^9njAcaVT?=R>q<
z?qD(Awaobel)zl4fFqsL8Euh(?>Rq3*XIuDLp}9q=PgR>w%AE4wESo!%D$r~K0+%d
zt<#WSei-}ZUF8+9q3TF3+Jp@iABo7RK2z;^47wV9-DfY)Zc-E>eZCtnK#<|w%8<R?
zC}LU8J`9;2uR`zIU&E*Rh~hl+U3CBB_*9e@@TmyC!l&wjXJEeTA#}@s5}%6vu+8$R
z=I2q-M>#D1(Pp?*i*Es+igVTHQ_&spsnjI)_*4V|pNa#j%sJy^SlF5%qbubcPq2$;
zCa;O$I|8blBMEku5n1EhMleZ0KW7HPWSLKSXC%RHqK!8s79P;0_1isu0am7gm>X=R
zelvSGO)622Vy=_iYh2rwp>?A8hv#AStKHhZi&gp~K<ze?mFAp$0l>E2wAha!+r=9Z
z%W`JIq*v{D0k$)SA=}G(UgmUO2+%Gd?wAbOJ;iyIa3Uy5?Gynir*IL#9s(*fxmr2D
zi%Z#ZwQ}7&^^f2d2&+3;xj#7{?o+&f3Mg3Jsmgs6<D4dLu^f;FEk_pRGOezaY0k)*
z@RF;Q>$g>w$7qqPeurL*Wc3rp9dEl#)6S{i#qQsLrkIAr^}FUK!>z7XuAd}8U9DU{
zS$fKL-oFmfc8gC%G<CIdy)t!J<E%m{>y@d)yz@4t?ICFzoS!pfPifeJ&H)5dW#t>}
zJc!!VPm_>FXDOPmelM3LP**G0e>cq`rLI=4pOIpNsjHRiX9`ePE7$KYKwYg|KTCkR
zTDg9<0Clx;{Tu=6YUTR5saiCXx>~uuLx8$kxqiMxQ&%h3A0R+otz3Vg0Clx;{UQPC
zYUTRF5-gj#TDiVEPSKst>~m3{BL%3dmFxdY8l>CVz?vQ>TG}$_R`$;EGPu;$%JnNH
z+6re1hEV+p0#-T?vqeu7Y3gd_`jZ5xtCj0dkrqAEIgKrPs(@8mJcUF93)|alQ)hR8
z!o<oY1K7he33jX;jbc+5;1Cd#O!MH7@nmZ8sVL@4^-q-UgA{W6a((gb%k@vIf5Of>
zR^S-{w(}#F`B?#F&IK&<{|ZPsiy7@X0U75qw$1Ybs+<d1<`)FiI60<yQ9$0=g@fe}
z0ven$ihfDJKxZtay)2;7d4g$P5zykC%4n|&XmftRmVQmZXvbi*Hw27xj-u!{1&ntN
zA$Uu`MCVe9{-c0)r-stj3Yg@qpn$gpOmUuOw08tdbLyDSy8@;=j}yEnV1{!w)4VTW
zw(|~a`hkEB=M08?C}4rJ9Ya16(CMrp_*g)f)65clBB0wbu#nV$DqxwjhNb?KfTNw?
zGTM3pE1XLivO&N~=Ouza3pm+%meD>FaJusZd*O2dXF9jBI2#3=<IE-aLcsY>ipBX-
zKu>xStF0;fZ0h#q`b}<Mt~XTJRp}qI8BB$)ORr)&OQD<6IhHA+(5>nDEL2RPJJJPa
zXDf7f`X0tCQD}Ag1D3c{p<kzOV-95sJ(zZwLtLRp((h7cLZLP3sg#*i=!x`kOqWvV
zne^RESFX_Wn%urzkK32$<AEZ#FW1-THJldl`4EyRjJAKz`LG!B3u9fnHOGXA!qx&T
zXEmY~#>t{)JNux(1@(j}b+%=iZRKfL=2W0!h3(X%5i^j}a`3{RfbqA3><vcDCmylv
z!7J#qYbm$PBjy_VY`hdclRTfnxCeUhhxD18<{XZg<6eo_L;8yxTL_FjqfC1}3aR%j
z9f%`SQZaY1b5vc)6kW6gR|@ZF`y|6AVTSHx%fbr|ViRv_-q}twDR`YI=MGrgh91it
z3rhYp$Zr?<clh!Pc8!wX-NdJ~-ru(Qm=@mc1QzYdm|iu)w8t4N)|X7ie4dQedik`x
zH4Gt7$2==>-A#+TLGFCU$6Z?U-V}2~On+y%X*cQ=bJQTOb~nTdUhNvYLA$*%CXW=@
zZ)}9Y#+zbkYCXoP*-i5ffy|p@e$|Jyv?*hpP4iHeJ7Z~em#=DqU&L~L6KKtgnfLmr
z-qC8>CrjQ9gS{%OkM>jXW;F7i(+yECx9L)pKS#ZyOp`o5kH$N)EK7IOp<O7;#;8}8
zj+Wfb$l?nhcd4>|>Eq5O_M#Tcc=c?x@%NzR6n09VScT~ItLAFj@KG%2+xnE0X=m!;
z?0KXSk5iQE?Hn7yTy^sDHtC?Z^XwmU)ym}~y6{g}e=o(DDA>qVCnMeaX=-!ks?(Q`
zV2ge#wJ=xRu^e<*#Qu{%T1K$W>%A&>ju3;O8>CL=sxz05tY)P)i0)#px_kMELk~Cr
zSYDhnSKSKPko9M8s4W=zIIHuS-y&i|@N>}v(RU-Kux1;*z!@WJ1*T_W7@DiDT0Sx>
z*rOj$ANd?bZ5+a2W7V{gWeokoOFU)7LQa7%g{6y&tXtk@WGrxeh?}dfTRuvz=zS)t
ze?H8#N8QBGlXQJW8sIbvx+bb?47r0LKQ&`kEx>Amt0H>a5P$~=ejL^BZUH#rIDi#a
z>G}qMA5lOws=wA`+M}N-H|<AIL=8>fvIGmg-l03HN;fUX2+{QUdP)tLc5U>pD^0OX
z*blLrmI^J|a3)9%Cu(EXVS0~Y$ea#Pkk2r@M!$TyHoB#cY4;eKwpfDMVTLyvE?GWo
z4FYe1kftS+SYp=x4`P|CdX_`;TECTPzl5+$;nng6>tsc$sP~ww&R?#I5Q*f}=-XZ!
z_RK(4z@~Xiv4lj@sy)wH-ZF9=lD0?ED&}}<?7LU<n}1@*HnB-MW#uB3c^!7i^`15k
zjm|#a)N11(T;xrq>04jLq8#Flx@jX|q_WEk>y}Y-m^W&=Mxe5by?7lX<%04h-YA$o
zZVb)}^k3?B63deG_|y8)anl~N8ZEiJiOg@bqr4^0b+Gjrc+=}DQO~fFqG4uZ6|l59
zdjy>9&rlca{%hxqHti1V=nO);8+!D1Earx8|C~QY<V<927_r4Jeyqp_Y+@Q#Y%F%2
z3_J2MksTWWWLlAhSg;VborGEYL$Y-o4l#@oQU>ec(TLTU;25x;LZG==+>uX_vo&AO
zb|4^XnOB<k!x3AFhBdD$!{bSdy~x;Cr|GW<f=|NXX@RA-d0EK@VCQvgSD9DHHK3Yv
z2Yk$HBKQY^DqHs>3-el&$*dFUzOi~S++~(^FE%wIZmu0DUW?jPg`Dh=lZ_z}UNejt
z5t@VyIoa5v4^2XboNO~T%f{Kx0zNKtW;KD94oyN@-+^`%a<Z|ZJgXuCT`%NhL!%Bk
z+2FC)>S&27BXeyTPkK`^pqxS>Cp+Y1W9u^HWMfLK^Jv&fJXb?b_LERHQv>6Ce<ttz
z7=QXxgW~@S5OT7yXAxflmCMTHO3A}^UPrTpoNTl~Xc98yWS>o<TGzKR2^n&-wW>D7
z;a-hprD}w7Uk0VEYNT@4pi!$vDR(XY?p2Kzcl<nT1W$A4+T7`Pmf^YOcF57I=Inx9
zdw0HP-StR_b=4Jswv)nEvU{LJD|0g7`MC=Oq@2C6j=2lvoGIhfVP$g<l8`Fr4n{jz
zK#eoT0_YTwcW%X#!CfSv!TBF-+Pa4b80fsmOb-<hUNg*oMRSBEAwy2KHr`o@>69HV
zQ)8lYJQ>7o0@|GfCUiFBWNUS6u>54tQE%LYoNPP_{_Qx~kLIBQ`<(1&0RD|Q*_RY^
zvI+kG<798%LgmkJ?CmqE>HfztswpjCR1<uKQ9Tr%0i*il|1d`N?Wo*l8Px@h?0*iU
zTDABVFseDzd`30h0i#+?L61>Q@GoOjvz0tX_2Y1UBcuArI@IDD8P#hcDqvI-`~w)(
zb{1OhDac+p3#Hni40s9o8Ko>y#2ombWeexJZWoss3g^1Mh;v<E#JR37;#}7kajxr&
zIM*NfIeDDx`ZIE`!b>>Ug(A*%p@?%`DCS%jcCjNM>j~$&uxqXfZpFDSOcJ0t*M(xv
zbz!$Suc=j>>q0T-x=_ryE);XF3&ou4LNVvMP|Ue5?B%iqigR7~ZkmHmajpw9Qfx5A
zxh~8Upg7ls{RJq_bzznO#knrb7N9uSg*gHg=ejUA^(C4~ajpv;0u<-EFkhl6&UN7c
z0g7{7I8cD%To)DzP@L<+VF{K^ajpy9af())>%x%&6z957%(*TUbFK@=$0<N@t_#JS
z>q0T-x^SXMQ=IF<Ndgq-x=_ryE^NxVZrI*tn+oT;VPfS}VTqD+-LPZjr^uC@YYqV+
zIPL()CY<ZS6QyI2LO9ojV$OA;m~&ky=3EzwIoE|^&UK-fb6qIrTo;Nt*M(xvb)lGZ
zT`1;U7hd-M{gHEBDCS%jiaFPXV$OA;m~&ky=3EzwIoE|^&UK-fb6qIrTo;Nt*M(xv
zb)lGZT`1;U7m7L8g<{Tip_p@BDCS%jiaFPXV$OA;m~&ky=3EzwIoE|^&UK-fb6qIr
zTo;Nt*M(xvb)lGZT>vGKFR&=ibzu|Ebzu|Ebzu|Ebzu|Ebzu|Ebzu|EHTb-egW_Bl
zHsM?sHsM?sHsM?sHsM?sHsM?sHsM?sHsM?s0?zf|?s;>y0yx)v<Ot`w0M0e1h2mT{
zjJ9v&d?4q#VXRBH;#@auEkJRu8;UvC4aJ=6hGNcjLoer=(^8%t_ru}Mz(F_v1Vq4D
zr9X#P#C!&f>mhY`n&>Z?!bxo0MUgc1o+$%8&hJZR4c(vxHj+8~k~v6`G#4}p#qcF_
zm?EBb2>1FWvt6-vXAc#A>?@|nAnYD0T<lj(^#;<a#aJQ=^|+M#5f<oPQ*UWE?axtj
zz2`JP>wC>wm37xp@Q44~^w^BuTFYxpbhZ?k?86>x>F7N(K~Nk<D&^VLOlGdSWO*x@
z#6R>HlG9qHNay-uT7_47o=1)CY8Arn`CjOx;ZnWxg<6Wr4}bGE<Z*sZF;=fz-U_zm
zkJ40#z>aJsW%B}g&KRpE4i|d!g<`V<yzJqRAH&jla;FTxgk|sX<jx-cKH){4q#47n
zCj4=Q5<GtRYC_-6@AS4$2yfS)L7hkJ^fS0|Km6)(rady>SJQ4A1n#;pVmo!O)!VgE
zQ?@s4EM}UC)=`#`I}Dc(L6Ve5k4CzoOL%8_r%}OIZp~GfFCRUHzCxWo$;c?~^c~>H
zYNOUc*mZE!L)e(#urRk7l`Jb6&f2IIJDT=DUDGBo_&Elbm`Of{%vCon*T$~f$+RaT
z^-y79Pd3x+F*2HQdL<-T?TjH%G_+f$1sv0hFgVe<+IkGk6pCkD8FEZRj%mm-4LPQv
z-QUpeFCGj@t6#`5Eu%6Q+WieVrqOxXc1#LuBGjhnB5~Kf0FG&FQG)OLZ8_ic2hg=}
z1^G(+)Yag)r?g)Kz3T2W;jR^%C>ERBX_8C|*CEh)Jccct-KrW{f&mWPyNf&fTL!ww
zzif}Hu?$SWqim|&eqMM3Zo{&2+vCT!=0VxBPJjwows%zrqh3^jze(HH^ex3t8Zzzp
zczZ_x*;0;ANYJf0dm&kTdjS@fgmQS+{TJ$;n3`hA>QbmeV!zxSbl*((tO~~I<(vKw
zP+$X?<^4Jvz$6s)+5l$EUK_v^(rW|w6(HCEW)wQ*5166whdwT{0emR@0vo{0rPl`V
zRMb1L0jvsVp>kif0sJLo^x6Psu0=M0%OIuK2Jn59`S;oYW`3!32Is`dd-OC*R)Ke4
zAUS!TZq8<Y>rl?N<jZ<$IM%52WD7yB=y7Fp_*WP|$yXJ!((i&WkbF&#b3E8-8qiF>
zu25Ne0gl#^Zzz;XFUDD9@-02i`en4p2^6zdH`g$~v+z}w%owSkF~18DBUx!=2(<J#
z43ea4WNrtt(htBZnN_HlZ_2P<z9~^J-;|w_N!P+JS#4y9T#U8x#1?B5nU0Z_tT9Y_
z_1WIQj$Lw^k)qYu^rM(J$-NAhKuh1i-kWZSK_V-C4bmp}QDJuaX12q=hRb#+OLwz!
z`x!2COQn;n&kThs(kJ4<mz-s|2O>o#eJ{~$g{somFu!?*y9i-5=?gITk_Q^@5}<s#
zKl3|S<=&8P!30Zo8Saq?8<>6?-^s;>%bsmaJM7uRRerr!kh7m#(wtYxrG`s1EWM0q
znL@4U4Q%P}DKtE-u`iEOs4dNFn3KmSG$MUA(Xk4ROmAeLoS@LCbPY$#DXJw#r<Z~-
zk~~$Rap?rx<urxHrw?Mx(^U&jOh1Pc>EszItUcYxn5ztzqh%6$iahhA^^o)$=V8)f
z8zn7Hh)4~KbGBhJIB$_vd7n|uo(TA+jBGRAZE(n(F1mvJN(OSaKJEv?nAE*&jE9Zt
z`{0*<nHfA{RLf|$7&SkeUG=n4&4$eX7Lk(AdSEaM`J4xiCwSfi_aI^N4<1;LWjFbf
zQO)HChF1XIFsf-PJpUrw^DQshWOmV7qxwVq+H8d*QLqLsvR~?2{(M&U9iw^yJoCS2
zyS#5ypUt9M%USTPIO)JQrB~kPn+ou402A2!T7!?YOwkqOs~Jc^@A`oeEq^HU{Me{|
z0e*Q|4L&ofV{9Rd%Z1IazJPu+AIchhZdAwNm%o)|)XeHp691Qs&#%dTe6;-0kek%a
z>TMYRMXn(cQ&s;-NLuR0{8Gyv$QZk`BeG^S14;*``j`9$4rds~Pim_;-J0_fzET5(
zRoc(-_@<ni0pFBk#p9bkjTBPyUK_xtz{{rpM}AldOyW>xYoAx)Rrf0_8s&>hdEirb
z7A9u-A<DfwTB`g|<*uQ-OS#WQ*Own&!9khdh=P{9Z<Ni1yt?Z#<113hX{@xxM}OT*
zSaT{q7d4>nDafzbsA4uFO2x*Eq^d+2DmKcC<#jhgOvRTf&YQ?4eU&?blApjlOkXV;
zfK9=?PF$*~YjuA_5z^OXZ-7_8H+>zz=bO^a0zHIZ?+S8y1y_*Mx~YE!`P+=^UqMdr
zt*;>Go58^q<R?<}x4nXV8?>1y8n}X-?tk1B<iEnBBCr8`FuLR0+5o0OyTAr;0f07u
zS;@c#FthM&0Mo6^y}}0Y#puDn2Jk%qfeqjn00JAp9|8n6fEg{Y0bGX1LSO^99$*V>
z0JDypw*kzM7N-@DFZaDTL7Q_7#*zEJfYDAAgUnqgV4O1-v)=tcz<B4E7_RPzvd=m(
zv1s93&Hbo+53GOf&dw0yejGmnrS5U&QuHUHbX?*L$C}`ND&TVG9ZLJN?3G@XE=S|J
zm3s0LROq_&9vJejtGlCsZb}bD=evECalu>Di?C3*4Z6bvi#yV{u&`UHu)EO-J0NbK
zdVEdKF4ArGQ+g^2l|59ilx|3Wd%o%S@H#&2@IFWd!`cG{^=$xiRQ}C2fN8Y%8*KnH
z67#+ozpz6_#IK*@Bh$Xu2JjW|+MEqwrmXX90E^qR0W5CM2C%p<<)moMiTgctUDa^q
zF2$+{zNz@H#y|$&RNNllRNNllRNNlll<t6U+68(4Fuo~;{Ri?*k3+REyf9d8&K%kb
zuh;4doMp$PP6iU&_BX;IJ#Q-enp_(E>%kc&j|Q$JE{D6zXM{^F1EPQJ2Xk$4Wkto+
zi@qn96_;lak`U3?Bczt=%O+QlSHMH^;MA1)iKyGa-RD`%%c|^7y3Hw^Ht>~g*VFCH
zJKc`?oSmeXT?t<+{X-~>*~xm6<+9WJV0>kFQ>ZNcE5_Vi7pr%v^yyHRvwP@O%#6p{
z1Mxdxw;iWx?hrl83g-7A)3`~OI@%P!1|P41@`Km}-Fj*@{PJn8J%{TlKIZc8vZBj%
zIS0xw;`*|}1HKJliMClAz%6|+m~Vl$6J9~i&Ki^Jm%~)w5lZp6>>hR;=2o0b(7f6G
z<-}KW9^v{sOU#>C&Yfue>}&zH^B}<-0cFn91ak$XoHq#O3CKA6V4P$XQN79;%^@*g
zLTa2nvHE8Z5RiA?LkDLSQN6)ghk27#MD>BrCzQ5OqT#8{LLVg0pcdx}=x*7g<r&l_
zRv)v+mvdZ=)~p$LaAnV`%8B`yap?297cnEUXQx=h&GAje{~}iQmuZfkx^0>5J>vFl
z0Iy~1e4`CuPQ$<ku$bcYZ2%K&fem0r3v2-MsUFw>CMdQ6JQ)wSzy>fuuMJ>E?X>|+
z)N2FyK*ane8^ElqEESCG4#M-mw*fpA9)S&DW@>YSp9+V}+|AhlzLGNdg;n4>`~)_D
zKg4ONXo;`^EaAQl;Aitxv`R5gb30|*>yU|aAXdZNt~qK2WzMfKkaCk{jHaBkuz2Nm
zlW~x7j>kaCDH>FjvnTY}oT5S1I5k*pa(jrW+q{#7{*v2MK)v%5f~f);oOXg~VkmJd
zXLpo2x0iqc&dXT(a{Id1fejhlh)%G1zA5Vy*Z?L7YycB{TN}XCQ@_pz@Rw-Cq;(#o
z1~!1{71#i7!YT8nHh=@ZDaTs;+Dq}ztGe3$CF6M(eCZDOrtE&pu`yq(Yei?Y9cL;)
zUS2sVbL!Ar)pY_=&I-)R>UxQmalVg!sxG7{E#R9He1&g17M=m$R4xkt54sWkK2*-<
zn@WrOH=;MA;r=;%Q`O>Iz&GVg^ZBN92YgdC1wFngLBKbyKy?BOz65`l1z*mF&0FxL
zMnDU`Y^C5vbS?(p@<#N7kR-Sfoovv*ek1xHke$zI<)fgM>0LIc%MzhL`@%yOM+%dL
zO9e9yg1g`=riJsxriJrc+x_ZMb`oLp#ioVx#ioVx+r@vt<YHPlKVE<$!sd%j3+IbX
z3+IbX3+IbX3+Fd6Eex6~W&hnY*CS93S?hagt_Q&DThUxkZa`Dev@mF{H^CjyTnRQ$
zbG;2A|0J3#GYx329P0til?@iqTnPf2D?vbWB?xG)1Od&JAfUM(hh_?Bt^@(imC*v4
zD?vbWB?xG)1Od&JAfUNYT0nCp*aDg>1#AJ$mC^#5E5R1gT-l~R&Go4P>|u}QdLeS<
z{{apGp}9T)ho|)`)54&+-i;I?%@reuriDYAE85^cnC2>`g-LVelP;jSa#{p5*VciU
z4<5~x?ttb>umv<%^~|PeVbEOVnT;99X*qabOlW=E(umnelfl1*mp(onG0%j#;K7`Q
z`h--(?4a@B11|#_V(8qwJ7-VR?nW{6o@-G6;kOPkD!IEu<G|o_HW{9c-epZo=EL;n
zP@|Mvi!dFl4Vghf6^72}H4wB+1byras_+GMH%ih9qmC<;Cpcqxe9&du&^;*Vb6sDv
zhiOj|AwveCG-7=AbG@1?IgRLcgW39po@N+L4JWNDQRn8dO#GCt)BCL{ru~)(IFACD
z;3>V2O3=|n6T`a81&z`~`m=gkN$(PqyZ@_;8UVIy6WFcK;l5d@0yO^Fd=zuJMddOH
zx%5abFZ;RNqUTgDU5)b>FJ{a-o+nTc3AjJ^<#ub$O_a1qNgBVqX_x81J&l9?3NO<8
zsv>ntg%9;B+}-jWrtH#7hl}LJ+OU=MxJ+-~6&9dPN*O*x(^^^U%W70{rU^0ka<9@;
zTIb9=Sktc%bp*C>TcuyF^kBOp{QlJI7j3v0UcJg|1FKEU`(ESmYP;Kh$Q-ZrVAlwt
z5?|-RPMTu9-fz9O#VqFyULiV0J~9a;S=8YR)OiFt<=L2T(s*RqWEGS{MHuv4DMzWX
zYKAsy;BK%Mi&UNkW0!R`R!yg-wjciGjy{u_9IUf@$A8DPZE4nH{RTO>uWFD^Wzu+&
z-|Zt{2KNwuOlV_P{0Kt!(n+>$M_zi5R)sFMv_aDYLau%}vP76Y6@3?jE^}Q-$PEd(
zAt4v!fzaqH)`igMYiRTp+t#7c*N~7K8hyn{i6Z3wZ6w^|q5Oe_OKzP{!ll>Ol5lzE
z^|d5i62iWggi8+7H<NHlnGHy|V*q>-F5LkMmw+T(Qp|i3E=%T<aD|ZTk#HHOmxTKO
zP(Z?EdB2W?OA~*+BwWVqCE-#?FA4W4Adqkwg-+R^0STA*4IdYgaOc4<AmK8XUJ~xk
z4vLe<*;?`j{4qk1mfk!G_an&YCE+sHA`-3!DZM1z+bQ$!CE+r^UJ@=#Rz$*`#{2>j
z?f@J`Z4n8V<Dr*?OVmrkCF&*NvVKJ*++Q=lfP{Mm^Ycl#1id6&8g}g^;S%+da6_Z7
z7-b;gvS)iqxEzkXBwY4$FA0~ZmxN2yOTs1UCE*hFl5mN7Nw`G4BwV6i5-xkamxN2y
zOTs1UCE@OcqqANTF2j0BxEw7c;ckF$(z*w|p0qd*lNO25NsALAAmK7NAmLI@K*D8Y
zo9V8BL*{f53HJg9a<=})4=f_#-VVQjg!?i8u7gF?fP~9R2P9kpJ_%QVPr?=8lW+z2
zBwQ{(0SWhKl=dQqJxRC{%_rds%bl&T2!E!(Lc*N^&wzw`5&$mHV!?e9F1-R0t^l8e
zOJMWs*Z4@w6p?Ug`Oc=Gm;JyZ67FO03rM)10VFLh7dF4jL1plp*(c%Z@C!(|LjaN%
zY4$e1CiwA-NVvlo-zVWp^+|X>*pCSk?tYBnlW-XzB;32;@JYCI2P9n1hk%4j5Rh;=
zRzjn%WWO#!dxb_{dA1t`rKWNhMdt~PzJ^9$zdZ@}57=fU5%zA3q@=|&b)SSg4D7wX
znS^@=Xer-F!eu1peKvlR);>i1x*8u@mwQRLr0Z^ugv*pZ30K@630K@630K@630K@6
z30K@630K^!v8;qfUxm0e&bbZeKW?{x@y?ETaJq*JnCN_D030Ep-TA-<SSnzWvpYGX
z%LGh8hw^<7>jL^6RYm44h8Ib=2f=v~KD{K|qk)8kdl?+k^BxKJW?-L$%P=8!JVwvk
zFkCkw;oji~zrkRRUF7$)?-?3>Rg7GpggXZFJil2IZbL}I<>}NUt?mPy1A&BFQB1<s
zNi+TbnuN=V(@Vl7wKi#yc<qyLS;NhdaK+yv;d1o&BwV`t90RSaDqF4FHzRexdL`&(
zy^>tl%X%g1WxYOvnBT;D<#m%X{~6gO)zoLb-T{w*^~y}`Ayu08J{+=^Y>xHnfY|2p
z3$-uDPr!QJyNLBF;Xdni+dPWzvtF+U2w1P>D9XQ<^;%xcdL`IA>y`BhSg!;D>y_Z!
zvR<>O_SdmqJB0Q6Is0W8Iy(EVo}gF2dOeG+ybZqk?5bX5&;r&gEprE~*Ls}P`>a>G
z1J*0M|L<bGQd+=zCHM;K^<ozIU_7wK)qL09z=He-v0ewFK0fPJTHI&73cdGHv~+G%
zycu1AcLT}o9xcFfuEy$-8zaDW20#(WjTKPlltM+wZ7m?>Y>Ul@+&BRlrw1xRZkr0#
z;#<Ia<xKNguXG2jR|3oNSg!;D>vbvmDqy`5{9UY9&W6piUTHLptXH;Dz<T9k@GV)d
zzn8)fJOc#Q>B;v1{yOV*B4YTgSFX3UOz*NmU6u$1x)&a@I8vA_Y$}*>5d0*3H_LiG
z9^9R8X1#vQ<UZ?_;2+3(rMSPF_4*vDA!~gv>-AxHeJj@My9G3b$9k;<-y~qY5^SFJ
zT8)r@66=+j2CP?(^?>!t1`AlP1Oe-nAYi=`1guwrfb~icuwLIpGX<<yf`IkPXaVb$
zAYi=`1guwrfb~icuwE%GV7(G-0qd0lwt)3YX#wk%V2fC<Y*U~0x;5By0qa$R1hQT^
z1cVtk1Tnq;Apz^P4k<#`Ysh-VL$N1436!$`6RcN0=>pa(r$xYeJ&*IjW4+QHuwDta
zfc2`L*&gdvp4pgzoR))0LKoI+3t6u}CE5-g*fyeDh{gjwPb05f_jO%|0gU0W7e0hf
zGyNvLBx1gV(8h;I9xT`Oy}?Udy_acEvw(YugoIhHSJMqT=g`;iBu31_OjHBR(B@w<
zWm@-0lU*$z5nrvxp4i8<hgs82`%FYshE_ZE6!j!>XHk9!<kjJ?F!lz$16j^MJiX@!
z$fk`9&JA@c$8O$2|5?D59r+|vEY-<AoB^du@2MPw6Rd?uab%i{Kgu-fcE&j}r(nkj
ziu+z#iJMJvM|tA9N06L)bcR|CXt|^Q%ydWhQLuBwlDV3Gj7#|-V2-|zfv@Q`C@M<N
zzYf}&2(q+;_Y1g@TV0NtAt1A_X)i!kpZHnGjSRVwAvZGQMux^pLt~|QFoecR8`7)5
z4+y!DAvZGQMtTNHLvAGa;>lZeGvr3%&jSsVhTKTB!&eNH(#T=2fzps08FC|yYBC)|
zZX`}|wu*<`$geR_dNYpPWsADkK<Q6HZe%5n!P>>XQOJ$NLEzhQ@+>xQpp+qjfl`9N
zKq*0Bpp+mmP)e|Q1Epkk1qMpV@cPyUO3%SbX0L%#GC01SfznZ+eDxYAB`G5?P)g2=
z_BR+P4Y`ptP#SV0F&nB$dR!vZ#*iC{rr`X9jxr2Cy#`7-g}=r?DR~Nii-A(+!=u?6
z{00U}IiEK*P)hN?#>YFf4Gfgt3ctWWsgNGO*+8j83%QXKo#WBW**1^po4^8}9ifQ6
zAvf}zbO*+N-JQ_5vUer^uX7_;<ay%jSp<C_;NOTFITdG`fkjY)|Npp=@sT*nP4$^-
zKLKW&b2V6%efAQAsG1W+NT2Vj%SWAC8M3#_vvkYZhauDBRW^F#YuJ??Acy(vO1l4X
z>`F=t*p&odVOPG4LI&*0t<f$2N$kplP~*+AE1zOT|0(QB)#6*guH;<x*_Ct$>`FC>
zJ$5C*zl>eURtngaTu#0vyRy8Fh4<K%EdYO=U3nsM*o0ll^e!9JXIJX*5OyVnDR!j<
z^9#C37QUNhSKg0+Z)R7HWOAQfN$?M3S5n;H&93YVQi~{7z3j?3yuKB?vKiDNpIx~(
z+yT3iVDs$CnF#qOu`8Krz^+_@{twudY_Nb`Nf59r2?BN{LBOsg2-uYb0lRV#nkisc
z5(Ml@Mhn=L1OdB}AYfM#1nf$JfL%#x0lSi53)qzuum$W&N(<PP1Y5+eWSjcz%438N
z=Ghe89=TG5=MWHf<svvdMLl3w&O?fjT^X_~vBC6zh+WAiUBIs7v<TRh&vHI^>`J-=
zb|t~z%C6+Jl-sS=!hzQ>=Ufi<-}v+&fCi7iJlEgQ!K@rjp5+9>Hwni94w=fByBhj-
zU^3n`*R&r&iS!;KvB$Zq(T{GDAd}W)Bpou53Hqx9ug&ojEcX-iH)>S^WukL{Ax~AN
zA5zVfpXxffn2*dh?JAvFeZ-U`Hh!w(wg6@Y)1RO~uGiB_P^Yr}xj|2_z<Lhi<50QU
z{?9&%v%7f#iZKI1hi=ClN(|4e<pMkk4yMoEk|kM=ci`w&?>S=-tdB6uy}cY~4}$^B
z>1jUo!JQm-$Q;0ZJUG2oOpos8<-R}+cFyq1);(OxGSlaiwl1dC)%`u#**s~cX<vns
zH7!{P%aud*T4s$JQn}!(QrbJHlBMmnf56E+76m3J^XPe|Js!V>J3>xo$jJ;jnIR`L
z<Yb1NOgs=mPG-o-%xcx^B5ugZ3^|!0ClmJTLVK0GG(NOfiH9RDjpz09Uw3JI$jO8r
z?Oz%n+N+dH<3mnnXs;4_b=_aPG(O~HV#^B0SN-v{t=!qWfO2%m$y_TteGSe~u#rMe
zCMYwwG(O~H3a>J>S4nGo1D*G<aJYvGy{yr>&;aNX(Bgby0vslw&3OQ?S-Oh_gq+Nz
z6~%%g#01hLLrx}#5;##XK9()W7_pr1fQp`N5MVp6U?^q#3n+8a;EQLs5|DD{#sLNh
z$T%nCiIp8Fpvsv^667EOHO_F@Ldy;okau3eSj-L)(BSL_vs~Fm0Rx?VDWFL}qq8?l
zFjPQ`(-s407SQIL#564eMmrlxB^)MTobw~5X%#TuS;?{u7Z7qXL2(Q1RpOj@<<B&2
zWo~<WZyXN_hYz>3^ITNhti8%z@>I*bTiQc=mEB^Rc!ic9O;Yna$~a}x3hh;vIjf<%
z*UXT`Cgp686|QEcfQ)k`+Nx%M0aeZsIFzrMC7{OH7pr2;Yyo-aMl5PIa|ARvmtrZd
znJZwR^CX_?HS+{CIs>o})^x<nA*aQeg9{L9=1WMMGnn820i(6Lb6B1QxzJvvaC~c=
z+fK&y5R(M-b7l}smU;ip_A2|$?BUw^m$oE@9auY0%tP1Rav_XMo~+!ToDcUY%Dpe{
zrma0yxsPI;)5I;;q5TwVOEEjJ_Ke(l@T$x4*3H^9pUHLip9gnd+=GrF*J7A(EqwNZ
z-ZOZ<rVsZGSb_G}pL~alX9s)-=L(cv)3m$6cen(Ds^zYb?-24GLcT-DcL@0oA>RQH
zhLG<N@*P6H115sij_rc*eonm1HZ>L6pbBkJg?tA*97DcCct2-ytx+A`&#Bqr{hV6G
z#xlNLQ`d|$hl-6EaaUs7tzu)1xNk&Y#g{5h$ak2Sk=x{)ZfrnR?kKDV%h?mBN0mE?
zrKynbfV0Ox%I00(IoAdV`3}>wi*!4*L8WX*RbmUcs#&>1zC*}&zzPxG&*?7L<qRdi
z2u~7sg$Kg>IYYifct0mt44^V7KEsyY&za8iy?D<C)o}p-Mtq0U@S1;MgNh)uL3Qn=
zn$}QVZS!UN&<52%fidwF8&o&p+&$Iz1p6qAKj&ibsQR9iDhOe29VT1f)8Y&;)IHoB
zqjIJn*W&)opb5;We~s;`ekXu(khE9;WfrR6M4K~Q%tH0s$uoua(kUQA>@2`=PB{&r
zU4Z4h!;oE*m&>9+vrzq}C+`DLW}*7cNUjDmCFT6!RD{f~AfUOL9Aa!@7K-UNF$;AL
zJcNBoVX|7OV9zYnHSpc)@QyCcuI*zxbtv!S=z`jsI4@k)oDT^43NV~I3Hk}JoSzWX
z3W#d)ITl`2sx8>xr-T7u7S{H6>DHVVAg6XKFVP_=cI^O_$XS8l+JORWXAg!95=+2k
z&SlsUt{p5O<%|Qrr?xrC3zaj@B?K+P$f<G;00FUfSn^`zQ-ii(=?8IZfF6V4aSndt
z4?%ND)sC@w0i!b#?^D%oEwmlY`5lWnPJrbs1z)3f8v(YnE5Wt`U`=WT<4wq20Rh%4
zEZL4VtXf?fb*|kz{Sn+lu0?C;2_wSn+YT}9fjV%{5%r!ukc3h1U2WDV200SOaAlxl
zL8DmNNEq8NCGCZXb&Zr!#k4RrGW0o0E;k%z1A`%`)>(a#;c9xX)Fs2!2bp#^SfhH+
z@Pe1&O5MwFS|jX#tkk{irl{;s&{Hb=Nll=%oTSH8=F?T?C+lA3vsLD&=w9X>LyrNM
zM?Y0B<CHX3EgpIWnnOQLcW81MSJX9i9o((yr|YG>`54wmnid`a>nGpWW3+sV>*2H^
zud>(`s@UreH0?F$cD?5dzt|PM#g=xe=q<RkQ-wZG6?Kv-YUVGBTIm;c#!w4n9NqPC
zw<>zpFZ#Yif5EC$`Pi#UE~v`TsVrF^A1_c<srIYVp*5e!s$4D<p*!ZA_GqceoCeT-
zXpZG_&m2o<3)=q*&;H7S7OB;h9_$z<oqJW8>f3H*aph`{VbrBHH?R)VC5x&KaEfG5
zJ;^Mjp{Hk5J5L`z_##Hklc;8_nl|jda{>4Da_MSidG?d3j{(&x18hc)qlgA#e#dIe
zOj9a)5X0-Yc?{tV^c}CWU}Q7Rz~Iz-q+;W}igmYkFGA;T?-hQTrX7qyU}-;^7x1B4
zP<(7hX)_Kr?dd4mZ~hy6C@Zq?kZ#SiV%uRa&$J^SW3HLDwLc=7di3@Pf9#+0$B3MX
zxoaA+#US;WR%8QXTCuT`E;a%`)^Q--86)ETk%{&2XaqMVI6kbWC~dL0BcEdb(3-Dj
z8xat-%qz|N;fSrod@-*oLqln?7a9BNH2pQZ9bZr4Q^NSBR%)A<m2801c^zwqc}0wQ
zY0e!Cye4uPek{$pA6b~!noMS$NcWA^i{UP_;#LmzM!oKd;H-~s>t0Nah@0y`c(N8X
zsscmmGz2(jKz?Lcnr<yM>tHR?DtTE>6JkYL9cFAh*K9?QAt-aUM~g>Vs|ix6S<AG@
zaAy^gXSBFA48L}Nd|ir<)CKvy4tGOjl-+=_>gf22j45GaR1QmNWUK(oIRWh**;;_@
zG_qLZ1e7^TEr4wVq@1B3okzA6ka4QfhLP<AR5=F`j2BSjTuadt1mv~y9<;lyN4{e(
zWEn1F*si5?YtBjN(a59{f)y2SqU$5Om9hp{Fm`66?IFn0HJju7NJNu*)oSI>{}MMs
zVo|a0rci0f{VV9!oG)3(Sy9#!_g;d}8JSb^D}>k%OA?vek8N=>8jSMn|G^hOp5VCk
z3_v<L9@*QG!)@G?qd5=lhjd4j)2%s$TL6|S@esnnlWfAETo8HHo{Gjw&Fa!3uT@Co
z)U3r?<aO1lsaZ?4$Q$CeogG-$H%oR$;xgxE46Vpp0urfNa}UrWe=L6%rARqzS(UYt
zrpg(_uK%EvEm7mN9Ru)D-}@tY2s^`$1^A@z`v48j4eW{a@if-yfzIK_0c<E~0%%Ol
zI()7c`CLS|0HBx~rI@1uP|hzTpK+PV?0#J@AC5%hGoK;5h@qG70JKBptWJoC=ptic
z=CV-;vvo-~DRV7LQKFaPN1KxQ5XxJmOs_Z$O)@QWP#aK6FN;9h^vqJ`P~kD8GUL&B
zk+d$ur9*SsZ%mYxFV;4j<`@0Z-bW)S!Jw)ct*EXQdBL#R3YnjPUl93&A%)R0m$Tnr
zGn|W2Y%6mg$JuK}hRDuLW%jQb{fNpke`XuMVc3+P%KU~i?@hzL*oMdqD;-&@WVU3M
zjRbnzaBoFeTV@1{{jLfdo!O7+-Zx6`N7%Sb>=!^E8ZxuTXG&1o$VV#X#7v&)K2~Av
znP;HgL_RSx4<p^A%pq*-^(y9+%<1g#4Mqv8KP~gnUO+Ww?0bkgJ;(7M$(v~o`F1^b
z2(zy<D>$Sl>ACq#+21UC9&w*Ha&63Hu$h{T>bzv+9!E_hjb`av2z|#un{wDnyZ;dl
zS=8<Vy>`!|5OM2aL~u_<dJeCmnDp{{=o7|aDvr9|I7pp?hpe`2SDA3o>)R1?s*h2y
zYq6R}_R;&qFx&bh(5YpSS-Slr#K_1rpQD!(Xqhx?HCK&3E3=Mho-Q43BQMq!HN$tG
zE7ALj$WgleB88mK`Ej&fL7-)Rj|Phzqfj(+0GGjI^@{Hzs7$l@^B$skMXi1$veAg)
zMp`ZNA-nWTqpA@xw9H5rSu-oxQC4OeJ5e`NjA&;DGp1o?xhOYe{OkDGJnfm2IS?(g
z@nE1ynP({_V)mhiH7(Q46(VZ7d=PbHVjRFRg*r0}na)<IJ5$aol$fbB@;f^75{Fl*
znJNIS%zVPt)-jXJuP3vP>tC5lcS&X+<`-A!s?1xgdP1R_GI8dRROpV(TGl9~(CW-3
zoM`2yOqd5Xn~ykVEsc~@n3)TXDLmZAJ{4+Tcw`oEiO-qU1X|`mc3>Z~>L8$HcwnHc
zbc&e1noznq^gUd&F7laSa+dbxIuNNa9rje;7g*G4(_xM(?;HI@Ra(Ex;TgB+Q_G1e
zgA*RVfIDvSF<i?T;}7Il#QQOP+Z;#h;gH-7Eq@+x<T_IX<j*9y-t5aqr8Nt&qD|Qj
z<Wx8B3Ovc$5*#GHLZtW9AHD>hL+A<pxPTjy$H|%nMXg~UCfLS<oejGXZtGNFHuHag
zb}Yt(rCm5bP`8dm1Po{G)-Ka7L-CKf@1H?GH%Ev`LQ%J@#>50<DC(BASlps+MWAl6
z&QZ%MQn#!kb<6VAE!O-=d^}UDrM6Y1Zdq5zKNF>HS(~U^R*|}8ZK`e=Me0`a`Ur}V
zN>Uw)Tbz=~m(Xs}&lBQ)3XK_6=gdi-Ge^}qbCT!GQFYFoypa`A=gg^PB8Dnva=*#w
zjvbPxiq8^!i)I&dbL|K%7tJo#Y=4RXQAlFL(sXMT(ClKZQZ1#~#abQ8Q<`0@RnEDU
zW*2L%W=N_6nq6$T^Er}Jv+KdHeI~xjFx92mke_IFu~GI9;3t}0Y)lCgE6px8R)Es%
zVp|JPnq6$10HxW*wh^E-yV$k@lx7#(PJq(vV&erU%`P@UKwe8L%`WyG`w5nTnq6$y
zQo5C97n@W<up&dvF1A}KYoO^FYId<b1o@iXYltTGs@2j;vy08N2VezI4Y_{>-Ac2I
z&5E*?O0$d2DQQB8((Gb$`>`#k*-@Uo4MO<w1jnr%04mExvx^;WcLIrK7dxVyZl&49
zmMZZO!f{$InqBNw`yR~g3TSq**D54(1vI<Z>#9>LpxMRV5Vz9oVsDlVM`ESf#oiK-
zsGw#S`(yb;<fSyb*jh=WG`m=_W*7UYZwnR`rP;+k={pNRX?C&o@#6uMW*6H~auGmd
z1vR_a=OVfV0L9!W#T*TQa(*HCjB}~k#h}?;hD76CYIZSbcDDfSkfml9gJ#F#O?0W*
z#h}@-sVBMA>|(xV=TftaL9=@vO)|};W*74{JC~YW%-8H(YIZSbc9hbgRq=<3a`HvZ
zF2^aEqd(gFO#~$v)JJJ{F=%#d1(%v#44R$9bE(<IpxGtyYq`|yfHFk3OU(|bA5oc0
z%`OJbj_Fb^HM<xzyCfEXj7tq92F;FPEiN^?7&N;EgtfWU>|)UD7&h9aW*38IHv(bf
zTxxbPXm*_0<6UZYF=%#-InkwN7lUTUuy&W4T@0EX&s8V6)a+u=>=<*3OU*9kYj!R*
zyBIXPwRm()ujcrVL9^qKZ`Z4-*~OsQaY#?ntEt(=pxI5r@AF1AHM<xzyEUlJOGfqM
zkRF3(Hyxp(*>TuPyH7)eqIMU^vY_3m*(K-^w?^W->Qwl0j1@(vm)}kE8HY(Z^m^kU
z^(pX>=QKx@%sQxdoJIHf7|%(ncQL4Ui&4EAQSV|<?@G{NF4emj)H?#rrFs{GddI9R
zm+D;%>Yem6@?wSK76sRcdKZIww;P2}y^BG;BhXx`cQL4UL{XROT@32oSOh`6<InyG
z@QT{^kr>pwCFlf~>Rk-#T?b-lF4eo3uim*-?_yBz7}0hIGbYqKuFMTC)w`H!CRyfo
zm+D;%>K)a{NiNm97}UE;<T%ZxdKdH6JD2KR%vbMRs&_G8y>qGF#h~6DkNl2ysouq)
z-klA!(xrMAgL=pOdR(e^F<-rNsouqW_0FYw7xUFSm+D>2SMOY^cQIeRbE)3Npx#lY
zr`|DZX(Ug*W9EWA_3knsXSKfTVzBJ@5IkI}cQL4U1e#0rE(Z1Pe}SOhaS^3c#6Z1c
zOLP2txZk=M)H_bqS}q1LsCVqCTB>(3sCUd!sdu%ABZ;cC{N?bBTlA^pY?Z+YkHK)q
zEzZh1P8)w9?<w9B@NIJ(Er3G=8CpHnyBO3vu157|5<tCs1;E}H;0(kpXo=(SldQoS
zWA|&ISMom8$*z^1ck6!iOvxbme_+ihz};9m0i_f5u%s#54tK+^nCLPzx4xTj+N_Hz
zU=42Dnz!L!p2oblOUK)3bhsQul}<>|tvP#PgqLnFz(T$LfY{c%lMpbr4-MRuJ5W;w
zI+N|InDSDHbaqQIlIHw3_A#8@Q=IFz^WjkdQ%Z8kr_4FxIDkD$h61FV5yt@RSuz<Q
z<FsP!cczwf0#rH8;{m3XoCZ+ie6cOSUL`jH<emB72l#Hu?*SUL@*ko&&}dRGpa>Nm
z^N-M+iDh)72rTH1Wv>EQ&L;#rN!|IEEeFrIbq(ut1VeT<Sp`{Z*cv(c3RW(^8~-S&
zKJjC+3KA2dL?z=mW>r-3;s;I}d__7d_ZQNUda57H>Z)MM^7CEn2VW5c(}jfB;wL|H
z3Z1L`NNkuQ8GQI5_%`@jk7Hn$?WTsx0C<$`F7Cw340NH)mhDl+rOHa6Wy+>j$=LY<
zfre$}w#Scc&BKtePJqm^y=Bcx(y(HDYDz{}3PUu$U+#BEoxGXuSrr@(HLoL4O9BT2
zH<e+2?t~eYI8m2eHFpuplsHLGu$-2g!FS?hJ@FwjwcQgjv=gVQn5FJhSh^CY=?MyP
z+`bT;I7?5g21;l)t3anWuLQ60ajh1)lY-CD&B^eK?29rduF%uWrRHXQH72gtQ^PPn
z+&osV#0`3y@-)|C#2fXrD%@j4H|gmYAj5WV#n?{Vtf!f)XIL?T%dXb~)(nA^OyUkb
zbtz@;fb}tPr;?(%f1;FM_%aViGbQd)$aa&AdACAk?t4g__@&A(<z}jY?olPHz|Ij0
zn7B_jw?(9yb&%PXcv(-CW4U!FWBEwDqRT;+=KhM!{i;Hi`z|6RUen|3Roi`-P5Qb*
zW$psz{)R#+*q8x&OOLaD87*=G#jMrM8<^i&NL`i47^xpHzY8%V5-_Ytpt<AF*$G^B
z{X-zjeE?pGtU|V1%U-BbsLV~V>vIaF+(neq$H=f#GHxw$O;ju7V*K`lw7A87h)idb
z)fgtdYPQESt1~gpNO8yCeH80rVlTrb(A*o?($fuB_1-nidmj~MyEh|oVqe2$JCwQI
ztlWNv%e+%=k|mj;P=$LU`+1h(?g*I~_g<pe3RSt+Fu!?*yDP$K+zT*+5_r*I51_o;
zpZWQhUArw<9TQ!KyEnoHx=%Cr#fHm~)aW|w*~3+SL){nI?nf9dM_`M49f$c+g@(Dy
zh?XhT>TY05e@~&|t_I18qZDd$k0Clnp%L!cM8_&L(%r~DIYFUOZVgAvDXJw#yGv!t
zDKySauw715XuNw6W1g;BaH9JhXUZ8Wtle#7%vFZV(J~1=)fc~U>niCr&cnFHHi}!E
z5Mo#{akgPHxZc9UJ8_>;&7P>gpOt^WsAgoF>CS;e=JeKDy(|E~F{)QGkhAq?eqdUw
zzn6{iuu**}{OVuESK<+)n&TVC6^L3tn_cy^QO#zp|1I19Sq}_GHi_pva6AFjU5R!N
z;wJv!f%P1%(0sZ4)bGN|zhP8ANog;#J>T-8O=cJ2MFaA1Y_`JQm{t8d5aml<t3RKW
zeaEQY37+-8=Qw-cs6GrJZp~!Dw_^R*DX;n@BY)t5p#&c)U^B%H_(;oSwE6?t`X3q9
zKZc)8K@a<Z5v~4Eru^8bz6*Z!vKoA5RKE^@`Gj_``SqC}AI*FyYw)>I{Wjy@$}(zZ
zbtT4c+`5qQ`85PkGDpiF&6d~A>T3AazlcPMh^eaoE?Q?VKjxQOVn@c<ogI-is~J!_
zFxkK43OJl$s6le8INh4_626iH;+&2BoF_5kk^=?gogX8w<RDqS8kAP{bEJ@x^ws3g
zcyh3LAiQk)Kjw#(Xvvc)v$fBEGmH=Nx8Nvf$*U(}#vh)10Vw$e-KWVTEBSM}S1I?v
z$#9>qb4(_GO#e%hx1o);Is<!R#&|g;Ux#h6HON8lIT(x1fW;Cb+buZv9C$#7W^C_J
zsle9Tpr4+I-yLLQhI?&;$3VP3rHb1>++7<dVzh4LU}<X)40hnIf=tw2TYZ>mFT?M~
z`?qKZ&g3?s(UhHrB!)WRG}OVUVaquuJh@z2>g*JccsVWQ;U{+Ex{%7`;itD7XY%m#
zFL&b>B9iRJJqCvyequN7Cv@}h6T5NrSO3pmhNFb>dH9LlxCkmOho9JuV_v~-+>LNs
zn#sdY?8Y&f$-__V#z9Mz!%wcS{%#!ICJ#TOZjKdIho8}A`#j3$zrE<NG~IIe8Euuk
z)D~H^)nUeJi!9ojAy8Xn(bj4LIsA+ccP>J5Zjo(+Uwat7uE$5}g8W{GyCFKtZo%V7
zw#cGmN>qJ#_!%85Ky8slw-%tb$fDx}s4cSSHUiWZS#(<gYKttoodC5(79B4@ZIMMM
z2*~?~pV9BwhqDaaB8%=?O1Ih~i%u#bP=}w<-AY*l@9;Cahahf|^@Z;Vh$i(44nLza
z?FT7T8gl;%y44n0bXJtLR9j@xIVHbCh}t5H&h5vx;1(I>*)QUYA5XB_IP(raqlepZ
zEDEwk7CoYzZnZ@gU8=-GNF)5z;b-(!dlnu<Jp7ElRw0pj_!)g&bt(@(qi={?ZIMNb
zx5%R27MUD=M*mp;I*O#W$f9c{joKoMeo)GmP=}w<kNQ4_C%f7ri+<AgGXS+k7F{2&
z#p<NC$f6rc#sH|p&*<kOS{;5yH%c+p;b-&<$wwW2MzKY<9TKU-&nULYb_Y_2pHXa)
zv3Tn6Gm0%THnlqZjAD!IR3LTu8O0XaF=!HX_!-3(88set_!-3(87J8cIsA-bi;Plm
z_{kq8%E}jOo27P^r9ayHWCSG`<Q;xSu|>vKki*X?w#X!&9DYWzMRqNUtqwndGDPa|
z6R01NI{b`ci;U^i;b#<EWY=PGQiq>WY>_cc9ezf!MYbAY>hLp)Ei#6w!_O$T$aqwu
z4nL#VBIC?fho4bwkujz^{ET9YjA82VGm0&;r;$z_enzoH#+d5xGm0%TR$m={MzKY9
zB4Vn;&nULYIOM&<&nULYIHbM9&nULYc)aNyenzoH)`<#xho4bwk$sF%*&^exm3HU3
zWl_5eWLY@QQHZ$pG$Od?!h^%BC?>u99?}sc(m3jR;~;f^c*t%T2a`-VZ+C2#kD-Hc
zcPxtCu{36zI{b`ccZ?^3a`+j=?ihhO{ET9Ej0IGOpHb|NNf#q8)-`TXusZyVVs~sU
zg>ZK)irp~+b@&;@?ii6e{ETk8JN9P;ctx##B#Pa!Bw9@lKcm<k;}b(2enzo7#*R{l
zpHb|NF`_#BjAD0;i?TZWjAD0;WmbouAm=pB1yYBfQS6TW3^}U9&nR}sI7igsXB4|*
zMC$M}irq0Hb@&;@?pQ7IQ-_~X?2a`9sl(4GcE^~XI{b`ccZ})O;b#=PV?^rkGm70Y
zB6au~#qJo9I{b`ccZ^6Kenzo7Mw!?h>km(6EsccTF=A#e7`tP{+xeJ>pHb|N9RLqG
z{ET9Ej6fZJMzK3~1Q2$|xPH<pVz4{Lmgdm+aLu|XcE>nN<?u6#-7)r*9DYWzJH{MU
z-go(lg2PYx)N-QA;KV3-0PeWO30cb-;}7Kb#QOz&+Z;z$iI=-~_!-6S7#AWr{ET9E
z?0A5>7ocXv79}_o>d(6ZPqLv=Uop~q3VZBEpMG4`pkg(2&gZ3KP3<Tv)Up0J2yK<w
zZme3?fBqpInm*iv-I_)%!qPS_4D_y7Asu5`8@<?+Np;U}{%)d~HK-XS**(Xu{R`4r
zQ(uHU*l##Ogn$MetUujPQwOV21hnhv&MUX4n{m6yno0kW$=&I`lkTxq-=+I}y0=m8
z+eX2?i*je^KRwgII1ka?k-C9yPsgLo;KY^BU(xZlL7VzIUV?5<$D_ZZSWJdXPOm*3
z?=WCr$75Xr9j_Vz9>EPd9+O#~j>l(PnPpwa!ak)6>uGmvvbgNFLA%>X$)0vcH~yy|
ztU<ez787b4v^#=8yCVp+JAzaK2cXdIOsweSJYNPeqBW-BA+<n$ufvnt-MR4dwL2zO
z2cXdI2m<YnAkgjz0_~0<(C!EV?T#SO?g#?yjv%k4)Bz~8yZ^`DyTHp;miPW^?^$c+
zotd>}CbMRCCii_yvJ(R21_>dABm@W;LLlKHf*?f!K|~1PT~t)6Rz<B^O}!!lR<WhF
z;^m0PqjCh)s#WW;N=2@%6{WOj4gP=M=Ur>fYzh`n+yD80{wMi-viAGD_xD}zTJx;u
z@_YUlbI7<m(gk-1apepYpyKX~*BzRH0#w``6x`kK>+j#InyqU=(DDjUad!v6er4Pp
z>4Ljs^n$xvt&)PfV=u1OhS8rhRh~+-j+^1JBHD>5K*il%Dk|shNEh6lb+1l%G80pP
zio5%gp6`a|?yPddb9Yv^;ki4~1$W1J_X<#PcMy#R3Q%!(Pt#ZhcSoCoyJIH`?(P`9
zbqen8g(3>>ZjXq9yZZ|f%Ni&^#of{MauH%e_qLhlS`p$xGt;*8IKDZ=-F;S#Hl`>*
z;qLAbbwmdRDBK-=Y)Mgo!rd{yZ7B*+xH}%i9VrS>xVyWxCA(4-pm29DQ*WoHC_v%v
zc)U(eQGmkT(aSkOmp?Qbu?wpmS);MdSW5f-k1Co;(ExWxd5QuQ?vD0BiUJhwZc2Z{
z6a^^U9h6H^fWqBD#VHC<xI5alQWT(YcT;+mchV!&G29(x%TpAfaCe8PY;}qP6z-0)
zwJ8cvxV!BtTc4r;g}dX)-k72Qg}bBXmJ|gj+#O|GQxu?Zce~VXTZ#e{?v9!}QWT(Y
zcPwvLiUJhwuB6;PcgK+*;O;om1Kb^o&;jo50d+LM-Mv7i;_jN^Vam^pac7clh8$$O
z6VDSla3_ppcB->QMKj50hHz`$VNIS>H&C6d{KmbUIyB`l_Uowi2bJM?jyPlX9A*}8
zKgj6;rtd{saG&YJay7N5UrZlFkfIWW>0_uceF#cSpWS(l#TGO}I_@)l=h8{e^g#qE
zDp8m|sB(%*6sC`#q|D;&3Ke8i^-SLz#RR0NL}B{)$q7<aqA-2jzc5853e!hLmoBBI
zm_FXs9{dZYk2!BmQHjFzT_I{)ib@ow?*NUsD@7#=)5oK8PKrttrVr}E6qP7UAJpy?
zl_*T#9*y_X6qP7U-=B!ODn%s<)5mywQdFWaeYAUjib@ow59<09l_*Rf)F;w}5ybRC
zeJVvI3eyL5Yl=z~rjI_w^l^?D+BQi{A2fp-Ev66pvpJnJeRnG(MI{Q;2N9&GL}B_K
z7A2;S_Z3O&CbM|siO6Wr^zrZ(OdofuVEP!*kG(c;lreqHkemfPzjiovN{&#v8S<Pi
z;6cg{GWPt<@HAZ==jfG6*ysaHAMdAv>3cv#_#?ULRHoWUfWp5K!{T1hc?ap6NMGLl
zAn8x(b?V;JMkX8HLH@_u|4jN!(tq04J0%D|L;92LFOz;Z>08?0Bt1g<&h~?(KTbd2
zG`rd{?7XV2<^tXRX2?Mt!_KSv>xQMV^Q!KRxn+hYQr&A7^kdk0Rrk)d{F_u*{f(~!
zo=ENb5!kD-Z|e-zZm=iX(b?~72-}CDVC(^HbL~%NzDQZg!8>%O>vP<ddPCL|O|w3)
z_FauDjVr|b+UG?K*C!zs)c#dOSYHM)TCb?Rt8ai9tKF@VT74eGc<pB*;`)yvCakwc
z{TDZjn5^Bdl2-jlN><k1BcfBk7-CgsoE1W>wvy5Miy;oOlBxO^AP%;YW%a8d)>z5v
z`UkY3^|i^(>TPZPR}hE99}%&>{wAuev$bvX@zLL+WoFypF4eZYNA!3wlk73{;PL!P
zvc}MZ#|v!xOb?zcF`cF9!INcPKYpgRG1=cfHYUEIMyC62Y?zC1IzcAu8XH|#4~Xf$
z8=D%Wz3#iQ*@#eg9esf5zMJc2FII)bbl=V6+>NwE_ubsyqLSBrH;-@eQun&==8ozd
zJ=b3M-8`YXT!hzsH&3h{FT(4-n>(u)iSWAb=C0}=i151a=1J9$iSWAb=E>DNL`(*W
z>AstrTR+ki8tA^8TVm2)_uV`)zDI=DeK(J?v*)yuIm&E?pJF}ezMDsvSc2_gSN)FI
zrTB@;pVz;)R{xUMWC>PNU5zPi%~^_X&QZ==9-J4mxX1Ob)+gn~EY}zF#N@4a=fxi>
zib<*AAKKISw!EA@8E6j6qe?d`*VNvv?fzt-_HG?->6vKSOzqt|!GB|*_HOO$U96@P
z|Ej{0S9{BYs8D;iPO;ymG1T5OcD6WBW2n7nJY&`mNTc?iab}y7Fx%ALZK=IKrZ;|i
zl+IyWYHvmjQq<mUslAzJn4<P>OYQwLmAMqPcUx+2YSvP;UTvwp>7<^b_HIk<{W(!m
zdsBsE_U<(L&YaHF-fgM9k5!(jz1vcIGs^5g(+rojrS?9csp+8hZcFX$Cx_a*Ew#6w
z9BS{j)ZX7$A1+1h-Im&$Q8Tr7TWat7M9wy~cUx+2)HEq-@3z$5b}LfU-fgM9eV?ek
z+fsW&xfHc`TWW8pI7RK<mfD-~S}AJpw$$FtEK_^8rS?8lBg{6ncUx-jhW02$?cJ8z
z+mDB$t1Y#+AMdB?t1Y!Rch#k+1=~`4L&Yg-@3z$5P^}cTcUx+2)|aWh+fsXfl=0rG
zJ?pil_I@Mdq4sV|?F|v6sJ+`#d%smwn0{GVZK=JXT#A&UEwwjPoTBz_OYIHSN>O{a
zrS|5gbW+sbZK=JXMs$AXs7^Cv4W{;POYKe8Y*Tx;rS@L0H&1$}UW09^y&-}WwRc-;
zZ@+TX-fgM9DRU`m@3z$5e&wjW+fsWoS}R5E-Im%Ls-2?tZcFXGS?xOM=b@zbhU%rL
zz1vcIZxuB+MeW^|+M56%KAvD(YHvoLOi_EcrS{&Xzf&n{@3z$5+}UL*YVWqx-i&vE
zzrRv@bDx)|sJ+`#dqb^AQG2(g_J&%SqV{e}?G3dmMeW^|+8b(hirTv^wKvp3DQfSw
z)ZS1Br+c|4QhP(KNl|;ZrS@hg)~2Yv+pqW3`V_TyTWW90Hm1*|rqtf-;Fc7%cUx+2
z%C@G<s42BKr)8V&)NK82h9B0r&5-9%pSEh%40#|-?cJ8zo8nQ_-fgM9>1PzRcUx+2
zDm&U;ql7)vhX$ke0+8DKl@#){empNsgHhDpZK=KAtGrRv-fgM9ZxhiBsXB_<yDhah
ziylSo-Im(h2-MzfslAOr?cJ8z+X&R&ZK=JDK<(X@+WTW_JBr%7Ew%SI=?xaEEw#5*
zL+#y`+Pk7^j$PQLQ#iRyRem!RjH32#OYMy_+9+!8w$$Dii4Y6O#8G><rS>Lk6t#C-
zYHuS@d$*<bhHzXys{gh#onRETcUx-j_fSYjx8;RVFpAo{Ew%Tjls9T`1F5}#EJA+t
z+9${5(Y(I48MSv?YVZ50kJ`H}wRc<Zsb=^t>T{VAX@hI$QG3g&ZB9>lqo}>xQhVF-
zAJl42%xnH8n7Nr6sJ+`#ds9%GN*7i?sD!D#(?tnsul7zCCp-^c?VU~;;nm*h5_>~Q
z?G4w@?~KhPQ+uaNOXn!dk^i;4tQw46t&Y=`v;P}q{D$A7#CR}<+PiaE^ZTO4P<waY
zU_V)7sJ%Pa_%v$o&bx*<lVhm8J0EEN51ovKd(~*@kfErw@%GS-edoiXHn-p^7XF-)
zE%m6hRV9lK)D1Ybs%p1|ZgEw_(DS0wPwoia!Y;(+E-LL%y@gC^=+&amQ^lz-(%&}Y
zR&t5!(4HmIpbu@Ef;ExMcFD!NFA=#GCIyAMiFdbcf^9J8m2-9T!eH5jg$TEHo$jJa
z&yfiCF8#gYt4~RF{)FoC5~h=-4Rg;|KcTUYrH$?y5z(7;>Pwp%q=N|4$<k&cLVbtA
z>{sG&L-jKh!Y+n~o2yF@VJaDJY*OG<^G^OkWV&tlWu;5EpQcKiO7B#<dbcj+@Bv+G
zUT0s=+(mwE1w59SPJd9DA03p?#FY7E?^<KZ{IYkgiScBv$h8J(LlTy+E6LS5XyD0Q
zzCK<}8bNRQhLrrExlET!m1<GHBqQSThpLDfBRrYQAFeP~5PeFQ@{Q3Z6=cf%@<&TF
zGi84Hra3L8XN2X@7Kw=0c^?;VQ0WeI^Yj58{Q)nP6)9=+ad9iH|1jEL=h3aKGnk8R
zTm;d9h$Fn0-O4!-=Hud4)hE=vqn-Pr#%%tjE~}Jb^VjT5#Ov0$zhFGPm)#*%8f!uN
zX>jX|2qV0g-JwRf2=8UL-iSEDCCeRVL@UC3*=;bQ6XCt=4mY9~;l1oO8ZkG*d)aL=
zVl?-0amTuUWe$jV-P3BMg9z_sx2+1{eO%o38Y>9AkBd9OD2aHRHz~KSn`Y}Od|cca
zZo4x5Mn1DmT26&b^2{=;3?sxo?pf7cDshnso6nxlUR<pWqrc`ky6`{ixEwxLL^m`M
zue;2>O;m*Uvb%f+=^(;;*<IngS0@~p&_ulMZg&qqsS@$JpR}zqJ}&Mae^c>sarau<
zMf_m6Oo1Qaz3c{kT-*aQE?`O#-plSmYtxJHUUomPu@iG6yqDd>^G+%26&&Hc>>io-
z5)qRT-plUM<b5KhBD|N~FRQnR@IEf?*VeW7adCTXn%>97J!a#09~UPPFT9cWad8sy
zeqEIJad8syGCl9(;w0i_tG$nllZbb&Cb+|VT;x&LE{TisJ}yooUepk$nvaW<h?fWJ
zbn|g>67kZDd|dcLqgi%gwX^<|3;EjbhKd|TnU9N;0-s$l9~UPPuhlaj7bg+#e!BnO
z$3;{J%KNy8nh)iDT%1I_wDUeLP9om@s(Pr*$Hhs+OPTj^aT4)vRGIg2aT4)T=6zh8
zM7$@c%=@@FiFkRky^o8Nh?kn)$Hhs+OPTj^aT4*KqITZL#Yx0VP4DC4B;sZHyUfSM
zNyJ-LP4DC4q`>FMXFe`Y3Ve=q=Hud|z{etA+z&o3P73^g&^~28E=~%3OtB>5Er%Ri
z+jmaTz`pak&iDNc74<-9;b0BaAuF%*O6o9o&Rf5ZMnL6m?^ceHJ!%py^XU92r*$h(
z-8-r7|457QjxA2A`-Qqo=GfvS#f9*WElyHghVqUrPEuUExf+XAmP0!BjxA2A`{&XL
zQd}q1J%o2`agyRfdB+x4sP3Csi@#U}*;MD<;iS5Mv)D3oY;ls}^84T&Tb!i0+@jDN
zTjX}zqM~<fagyTlI`)n&PEuUv>>XR&G{+Y43A0ydMDN(*B*o?FIL91YoTRu=7n);>
zlN1+fw>h>rNpat&@w{V;lN9$RQQon|Ns7yO-m%3=ic7oqn`4VK<VIa@jxA17T*^LS
zjxA17T&Pc(V~dj%7wT4XY;ls}(&ueK^UM0f(6&jlJk8)nS3LdsoW`-mNp*j(GR(2X
zNs0^M9b25Fxc@Bbg+Y@yCrRsOUeIKxIrJGl{~`U5lz2YPvBgPs&z&;I7AMs`Bl@xN
z8?#24V@o+CXN*VG4yR7ZQA(FX9>p=9mHZ%IWZ7rv+T<KvrG#~qIkq^d?s)~7V~dmO
zzAB>m1&w=yYEA_1z4}u}pjVwgNmd<!UUfnD0adAI{wky=ANjDDnyHBN`^CgvtG`2g
zmWj_>h}>&<YAI>y_7{Ecaw@Ka36szB;;qX5CpB0Ly|y%UhE=<G>ID0{n?-$7MN1A5
zuPYnOyOoAX^fs7FXNc=6owl^JAH9}NJBnWSJNL6nKVvRwtyurV;O$a5g+q(C>DfH(
zI;~KdTP`iRv-J10JH%=ptjwX6tren6;Tm1TXrZo0=zlq=Y@>7)%J`tNg!F1lyUnE6
zmGhp4_PkOxs>i%dx$9e`#rvv1ddlX}eSR^IE7h2JT$|0~R_5_edVJD(e2~&rsm<dP
zq*q(oT~2ykIqxZ(#|y|^-+bIW5bKA*JNonZoT@R8MR#iaaV1LOl&+bzX$0pQ9nn10
z3g+or_SUFnZ=zcE)~IEV-Bb41J!OyGQ})<BWslvXc3}6Ey-jNc^VOk)5{9Z^A~C$I
zaS3Tm8-_2jw1eX<iR0a*f@(N?UFrKu)ZloBua7@U8jg4PhLrrk>~$YhBBp*RNZjy;
zsu(~t;CP2WTw$!B@hM$~Z#2d?3@Vtf4u7;nvkImS!#B-&ozl&)6ds_aS{K+oEz%V;
zJQ<nwB9(g&@9;naWop3vhAYzdtCDfQ;Yu4TY{317E9(sG8gRei$__-_fcp(s&VexQ
zH(XV}PR%>o{iF1^zD}3F(0^Nt#xw3WT;mSW1Kxo94G*dM^}zjx>x>8+aKCyt_yOU5
z!}UhQ4Fe=N%!pP4?pL2WRO>Y0e#66!=r!Pe!;MDFZNUA8n~W&9-|$%Xa^?W{8$PW@
zTHZmrvEjBVgy(+4?KM`AalhdSMv42aFH-KCRL#~^aKGUh?yu<7Hu9Nm(m@06S9WVm
zGHk&8hR>>gS0%0i_Zyx)pS`$R8%BTi`*h)d)^REPsff(OJG@NqYxM~C8(uzxbkKnN
z4X^Oss}sKeyoYyqw>vN6e#4)%tuowic#prSaKGWbmUa!e-|#-OZjT#qzv2Bxcn|OJ
zff@g(S+p8(zu|+{rq_V`4S!x^C+0Tbe#3|7eP4%cv;p@UJ~FRb*88*p_ZvQ%>@Q-f
z0rwmJvU;=#&;5qKwyr(*8}7AfdhR!T%*OHDZz%5fI5qOzZz%2;?#FY#p}1eB=egfd
z+%H@0x!+LSuU=yr_Zy1)eXX{{bHAau-`SeH=YB(RzYS5I`xVB59T#!GbVj3Dc44)%
zjKd;d`+bdyS`=m6Zz%4UT`=x96!&ZOjQf?>Kpj5JbHAcGP@el0H6O}zzoEEa+Ij9b
z6!&|J(-AlBHx&0vndg3G6*KZRm3i)0hsDY~_Zy1){gKK%_Zy1)<;nKkZz%4UUOe|3
ziu<L^bHAau-+R=~bHAauUut^pHx&2F@;&z(iu--LYI^QB6!*)K&$!=E+%HEu<9<VN
zzc3LQ_Zy1)eX$mtalfIs-(ejnalfUIV{7~Vm^N}?-;HE0s&kMg(ITT1-lc2reahvG
z4OAy<R#v^KBI}Z)*RP}2tCV4{Tuzidb;F)U=wr0*5sYvsMtH6sInM}(VuWv24P%5u
zF~Sg@5e~%&GpuKXLovd3pEVW>E`@aL8R1Zj@S}7BBOHnmhVYDVC`K5{Gs2-5;R{q0
z2X+29y+yLA&buQNBRo$VYm9IxMtGBIct%*FkT!SAGs2-5VJdn?I20qyo7pqMp%`K2
z>>1%ujPRAByoYxvM)>oZif4pFF~U43o)Hek2t#>BI20oc<r(2njPU*%&ojcI7~#W2
zc}7^D`Zk_tghMgHwDXK`C`K5{Gs2-5VJOcChhl`GJR=;65r*=Na41HYHQW}|4^SpU
z$D2gY@-%}RUGemBISnHmiV;RhVT^DnMi{~~!l4-9t3<s}zM#7OB(0lyL7m<?{~101
zp-_x4kE$`kp%`KAlrh4g7-2^AWB<>*QN{?DLUP7<TJ3P^lzdz1Qpi&|#$%Ho<X>C%
z-|JfE9D$=_qi2k8C`OpKkuk!d7~waHsE4Y#Ml~mb)-wHxV1&!_C&`Lngv$%MQ<_=?
zBOGmyNlzZAOJ$ipf_6!C8tg@o7+faXk&ONPtLr?w749y%x2WnVUlZH)e-$d?AO@m0
z6#XqxVi#(Qo+<_+hN8kie1&d3hN9^7B#jAzH|xJi;w3jVK1vvfZM|Us&tM>ChN8ki
zJcT*HM+pOwv^NwL1|ozv6cq*{D-Z;1hJgr$q38_#Jy+FiU4@~jFc5E~Q~0RpnQhYE
zQ1tN_h@VhNfq}?gU?@s|?p9s+pLN^}zbqm%6cq;I&qU=Ih@`!tXn}z^XecTS#7%mL
zFccLAqE*IFG{->1Q1su&Kr};9VIY1*WBslei2tPDw*mvPr$@QKKwK%p8;S}8k*>X=
zs4x(jrZ*JLF%ZpA6b!_*YUB+?!9d(9${UJ;fk+?TP_)26G(*t>1JMjc!9c{t#2bnh
z7>H&lT3{fWp=cii(d;(NFU2n0_mP{mu-yCt-RDe-1~3pQH$%|^1JMjc!9cuL)Aoj<
zU?4(yLs2jgp}e7Jfq`g-qF^9is~4v?6fH0i%}^8!L|)w9P_)26G(%A^5CQz~hN55~
zzDTq8hN1-qq8W;Ufk>G*6a@qE8*1kbMGFi>GZX~_k>z<qQ7{l+p_+XRM2`Fb1|mm#
z00Z&wRCfRa@!4AN00!buRVqHJ8Q!7+azjzl&5(m^cj5t&BmFyJ<U&0Ls&lJ~W|Gk~
zXvFU8mCLCcs7_XX<9?-@)+L9rUq`LyE5i&$Ib-%5W`?4t=Cqz}I4htLAJGc?(1`C<
z4Koyt#92XjL(u{n(F{d_MzlMxvDkuUNXLC>#JlMP&I)Km2yZ9~G$NEY6nz{t;=?M)
zrs|;)oi@`9MGI&|GZY0Hk^AQjMS(`7qBj%;8j*K(KT7OEjqMFZ3ur_$6a^abMvdqV
zMGI&|GZZbL5zSDvfJQV!QJ@if8t<iMC<-*<lqhc~T0kS3p=be(XojK%G@==b7SM=h
zC|W=xnxSX`jcA6V1JH<^BZjt3lA$OxgBvYFQRuZfokJs@sSGm|1sV~;8;Syr_<T_^
z6y<$I(z?kEMR_7J+CwAq@D|XB+^GT@krDmaf1Wog3`NOV!1HT|Q>WzfN;gBE(*-<8
z`9Z$VvcIFN;~ec(!bTtNLnHFQ6wrvz7Gbu4<pEp3@_;R14w-nM*etUJtZbOOO=)in
zSlQ?h_nR$XWmAK+w*{<hHUe9~jkE*@$E}<FT3VVdpgYc0YpRTL*KKc6$=d?D<6Atp
z-WJg9sJ>XWye*(Rq55VK-WJfESpB#NZwu&lR__$yZ2{e`>OY9^wt()W>I}(!ye*(R
zxw>3LZVTu(w>GGv*#f#PF==lL=#GrHi14<6u5SzYVokCc&SX8<0=lD1EWzFzyOkKR
zOYs)UZ^^MLYKAB0HCckyROXd=CQI?n2Y*hm*|XkR+~ayzYpgD;nC1H7g<3*B?zi&d
zvexX2NvUD1Kl8DXZHB+dE3q*Heelz!;+e{Iz!z^)LMEjL>(4|cfhKDrlRz`B84lJ4
z3<qnO;ox&s(F_M`1BQdOod$?A_Bs_lf#G1y8xBrjI9T7=;`B{mI9PwiETrud7;e<h
zY;$b9;b1Jo!9!v_lSk>u$1)sbRBt#K=Xg10I2g-t@FgnqhJ&#T2dU`|2V)ry(up@5
zjAb}@j3^lnQiWvpEE)auoX!jfV;K&9NA=8bFqYvUqj<x?ScZe2R&_HRjAc0JCx_u+
zoa5!B7!JlV9DI%{dc(n3hJ%cn84kuW9K2MdHyn&*IJi`wI%YT+=Xg10I2h-6IVpyN
zagLW`hJ$gAmt%&5u?z<p&l?WLG8|-Pnc-k8!@;jGo*53tG8}w2<6$@$=Xg0Orb2O!
zmy`ZfylyPRLGG$I9E@c+2;~h2V;K%YdBee2hJ&mxGaQU%IJib5c*DV1hJ!tIXNH4u
zcen%L4F_Wx4gzQ64F_Wx4nldu!B~caP~LDbmf;|jHyn&*ILJ-$hJ&#T2ca+=#7I_w
zgLLT4a4?qPAX(mUFqYxqZTbZ^!@*dFgAm?uFwXIEQVa)U84gnB4F_Wx4*HevW{+ez
z$Y|bhFqYvUls6oVWjOdXweyC9u?z>Hyy0Lh!@+Nh@`i)43<tk2${P;G7kIQDZ#Wps
zaPTgbdBee2hJ)N$Z#WpsaFFr5;b1JoLGH6R9E@c+2;~h2V;K%YdBee2hJ#Sva4?qP
zAe1*8jAb|o<qZd884f~u!@*dFgHYaZFqYvUJK+rnV;K%YdBef@4W9CbgRu+;*+FkO
z7|U>wn%;0Qmf;|$1;fGXl-mqf=*~7np2KFy9yLQA2s0dvWjIK&84kuW9HbvJ9E@c+
zNM%R6d6JdeGo2X@#xfjCl;?O_(U4eS>J0~D84fO0o*53tG926`q8U=v3<qNw4zg%7
z9E@c+Xat6Xu?z=|z;G~@@X!bh2V)ry8iC<pEIA^tA2S?`WjOdudc#5~mf@gP!*DQ`
z;o#d;;@E||G>2)1gRu+;zs@W%9E@c+_$!;`y;`yv4#qMZB+Cp3V;K$_f#F~*!$Ang
zWsO)`TYP3X7|U>QvGN=p?aB)yZ#WpsaBz$A%y2N4;owCgnjx<X$K|TLer7lr%W!Zv
z_4x^lWjF{DPcxj<4Rc)nJg={v$8a!~;o!B@$8a!~;h-)5axI?>o2Cp0zeWuV2V)ry
zQc#;p7FG`sgJFh)$)bd`HylhBCp-_{a4?xN!W#}IOY99L!$G*f4QgTiXNH5x($Yif
z*^!S4rIl5KiL2FdvU2vZ%5wbRzd(ucU;@Lz#%0ath?>A~u<-`_$(q1$uyKt~V>sA&
z*AQoN0>i<^2bvSQ%M0(nPNIf`Yp^A`d}?UVBJAIW4xWI^K!FSUG<5K47%vpK7}X7}
zHC9II&M7nXJETT;X6o08)mQMoOA7(m(I3&iYwB;80PGWbgB|~k{|W(EI1m;@W?*P{
z%xgLt2n$j!!h%EtIMvYrPIZ*yRBu)Lzt(@-d%UKj0i5b+Ff2$k4W~L9z^RU=<5d5f
zupk1DK1V}%WE_D<7hypJ9$kb55qPvQKIS_u@MwqvJQ|_^kA^U09Dzq)qkaDEVL=2Q
zO(={UJetPdcUs`l5CwQNL;)TRQGiE76yVVi1$Z<>0UixefJZ}&=Eyh#k1oQ32t2wU
z7DV9D{jeYck6x(d1U@W?z@wpZkr*)#>>d@!I0BC@!h%!=!-5Drn$ZjJ=zds`%I^>s
zMBvdwdi-<nXwqIJCh%zMUZ$EH9*>Mu>4yaoc(hdp8AssJRu^O(fk%@rz@v{BQGiE7
z_^=?A!LT3#kEYENgGcwnf(ShNpQ2nOCh%y469ss*iNq`{h`^)&M%(C-aReUCG(9qo
zz@r(*BjW%by;ePVWE{YwO(bSvK>&}Y508ukcr@)iGEM;=ZDBzGk0yeLN5(0@qb)2*
z0UmA0IDkjf%kLf*1n}r0EC}GybmPN<03K~3F$)U<c(e&dEG!7%(IyhJupod()6OH~
z03K~3F$)U<cr;}m83*ua6Ny<^5Wu4;^T;@WN1I5@!h!%E&6DksaR85|rbosBJeo3(
zj01SIiNq`{2;kAw^vE~`c(jED0X!N3fES4Y9z75i1n_7ckxV28c=Uis4Djdykr?37
znMmxZhXrZyD=`oogfrHU`!VzNnspvh0RfnOICAv*b=3MP3%~%6?#BiJJQ|so!Q%iP
zZ2~Zh4FY&HJLchW0FU+pu*3vl$$$V1@Mxr529E=Hv<bj0HVEL+CIGY8Ab>}otS&Q8
z>1hHmz@w3C89WZ)(aTiP!{Zd-(H0v7@Msf&S!@u%qx-Qz0FP$Q9v%nq=nF)7cpSi^
zO#o)GK??9_iw#nMM_X)=0zBGcg8&|F0x*jW0(i6uz$`Wh;L(id;c*J^Xp0R}fJa+w
zkODl~VuKXm(H0w|0FSoVAb>~HX9gZUC;*$K!#yYfgPtY;13Vg;m%-xz9u48)aR86b
z1Yo?Keyacs@aRGS26%KK00TVQ3&0rr@dB_UECgVAY!C!sS!@s<oBSXn087Fr6@URA
z%`46XV1P%PAvzL{aWP3_f?Cv{aU>i9k0xsz35UR=*|;1e8qQ$ia21A^ZWm{DjK`dL
ziFm2u<60Q}B_XDM3tptlOp~NcK3#=FXH{wR=w&4*Hcu9LUl6tMgqKn>Nr_mtMdx4g
z0+FjcdGX@2Xm@tv$rmcD67){9hr3YyywUo3u2@9h&(2X_^E}_r&I3Jp&eX@n>|U(~
zr_<o1c**BQ%Qs|cp10puE#u;4NHF%_o7JAH+NERS?dsoZLhn}-6NxQdFm<=8eNUZo
z6iVAmOCGX5E)*3^Ud=?e+C+aM=JIOg4eh}J#7}hV^oedQCi)^(3DoDQG&nY1@_Os@
zg-i3i{r=E0E?)Kl{k4fwViSEv{4Y#2ryn=bZTUpcnl{k`CYb1Yn<!lH4x1>m@Dp7>
z=C?4rGwYXo^5RA3Un;Mf^_x$(`*z{NnRIhlmAfrQeBl-ebA}F^>q$XRJ#wA4=;S4w
zq7wIF`T6IF-b80BPLrik>D0~+rN=K+H>Ib~d79F}fomYP_(trtHQKVd-{`1;Mo0Tb
zE885&x407baMdlRKrEx{VD*`lTq2RGdR<{9yHhI(KCOKVgST8>d>7oLk@+sza(T)9
zM1N0IB)0#2#dwa^G>FRdThWxhq^aa+O79?z$zc({W~*|heHT0~ehr&npecPw={}kg
z&B6>#=@O-%G+dw%GkN+8#LVKmK!};ecfs$7sYJLyVJiLm-vz={D!vPZnCaJ(A!b7S
zmtrbq;R1!JRD2f*F|+?&AjHi6cY!dK2EGe~sr1{w3xugud>51lzYBzz=@*8{p%63s
z-vvU<WG_I>go*mC;R1!J#4l5hsbs9ag$op7rgg7QI6MVnW*#n3h?!P7L(H_g8Db{s
z--4->BWA*QKQX2fuZ99sssCLd#LWJ8fe<tM-vvU<?0**sQ;Dt%#7w4HAZ9YRK4ND7
zy8uk3{&xYGO7zi3%%oi(F;j1)0mRJycLA76ktW|q%p??AA2E|&e)sPJ5HpMKf&x>i
zK+Noa7l5hM|1JPissCM2U@CRKqPHKIO8xJG0#nJt1%j#6|1Kynl`LE!m`eTc0x*^O
z-vtGxl7$NdQ>p)50H#v^yP&{SvT%W5Dq$|tN6hSh7l4>K@Ld36CP#VzQ)%G40L09J
z?*b4r|3Cg+0BmOey8zhC;=2IY%>H*lfuLkD13^%FvhM<5GmGy6U^DyQ1t2K(zY89R
zpfv5f0N6}emjX6(nGS9rHj}&6hs~s7A2zf9T~Ht>S<FBXlrB&web~(YcL4}W{g{Cu
zC_(jMGokvhnf>nq5R_oe`>>fjV13w3+Vx>Gq580yP<_};s6K2aR3A2zKL2;V3xLfm
zz6(H5>VFr2p!8I~3xLfmz6*fOEWQhX&HR7iy8zhC;=2IY%qRUWs0@4;R0h5aoR2N|
zM4tq|Cypx#&)0PUf?EGc(EOTsELUC8+@q}e?9WM7wz@{mpbl?VU2D8#7?^?`fQL+!
zHvU7ks~%FK*~Gh*9(tNFuQ{tWv<FnAN&BpL+PLRd&su1o6;E5?$<r4a^ZK+SPEjAj
z*PJ?O%<Hy{dEGT>%<HzCd0lkL?<o+DeX-jIihRqD&!~$R!@CacNa0t3ZvT*mzEV6R
z{P@smjpvJ8lG95+AxgZlJ|UQ)yTX4s3_UAa_6{o%W3_+Iz0%PE8Taa$;f#BQC@s&p
zS1ZXdNH@wBA~Wl}SGxlDI;9~%2wtpccmF}|bsq+)-i9|ub9gDrU_>gAeHf&<99;<W
zygv6~kOtzHFBKyyGgCvDXIH{~7^M3!NcEAi4})|c2B{2VmWKK+lVp7#1}R?~`!GoP
zh1iEd`u{HsQnM$H2keRC0ej-uV~dVoF9D6&6DJ$yeo1L>Pn>LY0F9bGak8mF+S?N+
zn~lJp_!e4XPuy5H`!}>Sd*a4%?p3iWV-VBW-lCGXCvFU4i#B#tA66}IPuw`6>SUbc
z?TH&FRu_x#_QZ{y)uTjsd*a5f>a#_7d*a4P)z^sd_QZ{otJjLi?TH(kTYss}&7Qci
zB_{3di5o}8pA+Hji5q=;;)gZKX80D?gFSKM=n_jXRnt$E7_kcua;BNh?RvkcqGtH@
zye3Pqn#%lTp2<>t^FeIUhH|ZU7WcT`)q4NDnC1FnIJkV=ZF%u4iege~=&?mF$jjN2
zf#yIPs?r;jYv{C}RAM5Sd87UqI&E|QBw2<|+sr<w3BCEdVvvr54fq76#E-)u<>2KQ
zq<>BtQ(|F|a$@#jkjf-=9|mb=O1uw)bRPz(EMfOyknY1E{Xd04%5Ob@pA%1rLCQ~7
zjzMZ^Oo<<dLApnE76#W#9D7pvdy<E~R6oW;d!8+G??o-k9f!d{u)7HI<cz#{(HzKA
zGV;P;@p9;O2{P4BSRcgc99lO9lOp3{Z<xGph41acMJ7XDcPI>mWWI~q&!P2Eo;+vC
z^Dk7}^|?%0cGy%4UiA`0xT$bu&YLF<rUpccyHWp#uDl+RWAJvXVbD>#v*Nd?D*s-t
zX8%DU@8g0?WkEeninY%~VV{Y@J`;r^?9)CIg?%Op`%Dz}nJDxld+sw)ka*+2)O7hj
z%|yXWmy_^hY0?)wOBZjCVD8)10r%~yci(P2PgTr)yE@>$UG?tU6R$@d|8L{IRK5GQ
z3HWLo=3?mF#Q4|MHo6Byn1HXgsX^Kc_-dPt2xTboNo9^_j^7w8jAxGDX#2-A$8YNN
z9ltM^wLs@6C&8W^znO2)A!1D7_}%G928HAI%T?w&M2x}lo0_!_0V8nyrjvSyh%q>R
zzgCnSzo|mfj4y=z0gbgnW{eTtLdSCaPL)?Ueltqn@f)M$4iRH;{PvTZ=J?&o9lx=8
za2+DX;P}m`1CHMqPxKwX&(&Ubh!|5ies_o%Q#gKira69hh!|5ies_o%gX1^jwK_zM
z!SS1!4LE*>8lms_{awbJ=J?&2=J?&o9ltpbu0zC_SdQONafgU8IDSL5Iz)`Y@tgGx
zIDYSDJc}5E<M&DWsOS(e2FGuRphLtM9KW9-D(rk&SvY<}xen-3IDSLL9U{iy_zl(S
z5HSYFZ*EGbL&O*yzoABS)_$U4lj)A%Wc3}tBY9MIh!}(8H$>3+I6Iv?es^-mZ^~SU
zh%q>R`<3U8-;CDkG?|GUzoFV4BF5nOU1xv}&~!L{L-jgDjKT4HhN!uncSoY+_&rn9
zXa`H$!tuL9#26gE=c#O}L&O*yzqzx^Iz)`Y@tg4u=n!`V$8YZQ@(u<?IDSK|=nydm
z$8V^W9U{iy_zktHL&O*yzoAxlh!}(8H`GBLBF5nO4Rvs5FZV=_-%x8hM2x}lo1IwO
zAz}=U-%#s2M2x}l8){<*)Fd3g*}*LxBF5nOP1)8C5o2)t=Co|now`A}@~+TbOhTSR
z-8;2PLLP|1@tfkp@tb}M$8Rb-+MT9^J;U-ywikdLzlr+fcv^`SYK3w?CSnYZ-{&f?
zaQwbTL=sZ9aQtS`h2ysox#PDHx#PDHx#PDHx#KslpThB**K*<bZPkub4vydN&|k+c
z%+tjFjpKK$%);?|jff<iVB$oK!SS1{!tvXP-0>U2aoMf^w)g?Z?{g@mqigcQsPFjw
zO63)f-voYAKz7{?$K?xoeQopeS%DnC|CIW<<M;ov`p?o0b6kF&*VoSHj^BSr{oL`}
zmXBWzah+_MzX=+3r3=Sz3e55Q0wr?CZ_<V1H_t=i_zh7wesfmj_|4DwOVq;p?>m0)
zuPjIYJM*$?Fn+Z<mg6^|yW`(IPQMukwmD?ux07COX>aK_w8q`7N@nRdw61237iQ@<
zv>~_j`;5vT&ih^vEX2}p=<pKFqSD28M{dzM*DGg7`PTxSyG;WR?YTzp*2TN2cXHhu
z_w8Q%&R2*$B_l7MQvB{yGvdM})Nko`OnWV%O8h*LOLKa^_lhzDy=7FpSk*LgF!aZb
zrFlB5B1^qs|6Q8P@O}F;YUu!`F#LcG69lhQaTxSoUKr%PUsZJ%gFlnKxdOHPrCw;m
z9-VsFqf-xibZW_OeyLMa!iaQu|CuMy&qiIIFtkjBuguU?dz&gmrTY~rCwh~{8CsU*
zoC@UQpXyy52B-I@@|W3EcD=CVw(1jR`1_jDQgu-Zm+Lx+v^{i0^9U<I0`#AVv|TzV
zVJJh|4wp4vOgeLWA#F(8k=)^r5m61p>q<XX!jQJZ>*JeAXKpX#2lZ#`@(cZssSnb&
z++Id>f(>aq{BVV_Jkqud_-<7?L)w-BAI%JDJG^Pmo0SG>`(QQAk+w-2(ze`QUa4}A
zw5?F$*V8}1hH`r$ZAja4d$BDvq-})~hww<-<&_->kF;H0IS0a!w&nKnaWw~Nd%OPD
zH|z4>^xxK^@$ONYP~w|(rwnOZZZ9;};`D=}P~s3CX}f%=5v~E!c6q%K9%;LLm=PXn
zyS%{&kF;Gr+z5}fEi*oP^GMs}O-797ac1Q9@>=GQg%T(2k+$Xb0^yOi<@Uk~0v~5a
zZZA+EZ6Bb&gaEg76-e81d%*$2Z{#x-YK%@n+LqgkUs&e$@*|aaq;0vquoob0(_bCP
zG5%*Amjrt(9q)`hl=yrx5{9&0zI+C0kF+hf7wcY~aCkh@wnB+ttRG_H%*c$-Duc9L
zzQ^BGkhaVBTG}IRm+z}ysKy>?TcN}uJkqv8iT|@^;gPn>4_X_Kv|avrjh*mF+vSJn
z{a7yokF+hfml<M#Jkqw@UJerBk+$Xba=ZwSv@N$6y7oxh3MI}oJ<_&9iL)k;v`r}S
zlhnu~ZR7TW%Y;YT#_feZJkmCy#A)Y|wh1Nv9#KBd457r|q%HAC+qk`qYw{jxn^59B
zWT#u48A6HEi;%YYL!()CVYRcC+eP`>?>|yei=qr^8@CsB!H~9*DbYSKq;0vj)W4u<
zd!%jLUZ6bEHf}Fa9%&o57utEGZQNeIpckk|+Q#jLGLN*4+Y7$29%&o57s@=+Hf}F?
z&w8Y7++KLHJ<>LAFVyr%+qk_@=8?8>d%*?8BW>gMLQRjfjoS;$_ek4>5+^>hN7}~i
zg(IIKZR7UBk<O5|%W{W*Om#D)ZQNd7r3Gh5+qk{d^uuFF+Z<cl_p&Ms?7NZ7Mf-l3
zCeb3J6yC4x?&+r^;EWAaCu>$#eWr@6OO9T@j#?k84148rqU@;?(l$@gWjU>T1Rf-A
zFOxc+9%&o5m(Qq%A#LOK0^yOiaeHA{kF<?U$?mhpV!@@5jy=*gZZAPa&GNwE5FTk8
zw-+dnw2j-#r79BAHh=7ch+l`{VBQ_Ly)4wm8qzj_!zu7c+XN2hZh53_0*6!4BW+`}
z$D7$BZR7UBoITPuZZB7h@<`hR4*!bg?2)!{d*MOxNZYu*KzXEX0*6C+q-_F+AEfa-
z(l%}{M~d=D+XN10Jdd<Z;BeY`q-_F+LwTfa0*6C+q-_F+LwTfa0*6C+q-_F+)2EQO
z4^}2a+x-;MHZ+49Eu?MelX4oQZQNd7stiNg#_a{dBW>gM@<vfY+UD&<(z+4SHapGv
z&*=FN;r7C#YDn9-y>O=tX&bi}M)YI<Ro<vT+9qd=r_~OpPRS3HE`>amV>~wbK@Rnh
zltQAH*EvVCMcU{Y(l#<B-bRMBjoZuHMbu-}gsl_O_G<kxq;0vqkYz~Qa(iLpDqqrX
zuv^mO^jA)wP<mO{m>JkNxx>6t`I9)j7$o=5_ShN`5U{#o?jI|EhKYo#8{L;gG{7#Z
zZfcMY8UzHaZZ<;r@8LDdtYGt1TQ~c=v^1Nq+HvkQeKj?(`KoPiQ7LEukW@R~o^{vw
z#Y;r&sNSwxapUq=i8!Hpmxxy5pqGg_vHBYkoyJOevD9`}=Zp93H4fY;VpsJr5px@l
zZ4hx%^=uKNjc30}#L3lHikJ*${Gp~3*EY8RbZiq>r?w>~ttl|kBV){>!p0*IN7>pH
z(kZ-MlPraJjaRVwsvTWo3HGk}k`lA*QoOnH+lVNn6n-SH$r7xlGXE;iWGTM+;1ABd
zc`=K7T<>ZfDc1&Pxmjy1As=@#FFvIxCZ&dF=+7t^lBMv7yb>ET&<8($Dn3uS6%4xS
z+x<~ltc?2cmTtX`!V$fZ>nHShRaF|=nflJ2ot;mpu<V743T;DB>B?)=XZ;j=XGMqz
z<DD%#VTcIhXUw`%ts_K)@tJLo!(0n0od_H9>{!nyBEm!>LPiZn5D_NAhGd@M2qMBn
zBEoA`=0*?^CK3@+vo?Z+Ad!fWPU<6w2os42FA>!U>Qo__Jy%9!$7l2c!HChZM1<HX
zy3;i0MA(pwGS`AiC&GrjTh&Jp5hfB5`pF?8OoR>TCx?hI5jNzTRnd(gB1|MAWYn5B
zs!N0oxkuz&3o4xm8*-;U`9}~DCNk)<TQP!&FcCJS?-LPWB5X(~H-d;T5jG@LJc5WY
zk%*A-S|f-E6Nw0!Sz7@H^(PTF<U@>S*pP{^A-~9YhzJv5L;CR$5hlWh^y48SOoR=|
zU3DXf2n7IdR6K%+Fp-FmvepP9!bBoM*4GK#Yv@MUkY_1-u89Z}i3m5TyAhs?L?S|n
zU<46iA`#)yqQa3cD=U$R5Xy}pB1|MAgo;Oa&n6NPLbXN^5hfB5a#K1ZhzJvj2%$!F
ze!rn%eE=eNDqALONV4WyQ0YY2kO(bC5D_L45kdqbhzJvj2>r?t5hlWhq|A*VB1|MA
zWUcWCBEm%2kc`$EK}48HL<rR$c`f%@BEo-ByUqwA!bBoMsNM)7!bBp%y`tuhAR<g8
zA}ncFM@JA5CKve8Cr1zwCK3@=RW>z(h%k|ekUP6<1QB5(5h3FpV4<E9i3qvR%SR9q
zCK3@str$T>m`FqjwQ>XzVImPB)T$9ggo#9iP^(7}5hfB5LLD@Mh%k|e5bEF&M1+Y%
zgivcn5D_L45wa6&M-UMv5)neJA3;QzNJI#=aRd=zA`u}wxMc(pVImPBWm`uO5hfB5
za$2_OPJLaur4Rw1I4I?nLiVT>@<6z`Oh?#|6ps^BIuSM`{frY-IuSM`mFu)SN>%L{
zJ~SA&7l1^B2P?16)B1aPVH%7hB1|MA+^M{Af=VaChGZ8?Ayvl-DxC-$l0}abR5}qh
zq!EY+6JbLd@oEUMyG9@)OoR<-1R}yjobTE6Mo{TQ*pRQIw;!^f!iKbJhzJvj2tTWm
zI=fKSQ?>9IRr$?OFiueEMA(pzGRv=X&V&s)p&F&INfsi)L?S}6#tAB&2piG}M1+a3
zAtCBq&eDI|nNBc%F1s&m$Q=~Y(aZ9}C>STGbRuj>#7yJ%HV`)CJ4KX2UKe#PAIs}&
zn-LKv5)u9}^$`&!!iM~c)jv-AR_F4!d426XBEm%2katoa5n&>1NL&8<wET(=zD@Ht
zLF-?r0XAeJY)A@{sm8+UDM~a}Xa$W$3F)A57nj8e&%^x2U+al$Oc^oSc(2B4EU`D#
zr02@c&HJAh2%b!(OG~qqRVV+|d091xuBOkGvoEEL7uLI#m<S@UA)A*q-z+Ku8?yNZ
z`^kzvN%|U}#-OYDt|8831U6*z15NOS7QxpHpC2t(&s$$qa=Y}v5A8WmFP+6Ve~OYh
za1g`SoV6G;tl{$)QgQg2(-&igHGKYZPo6qu(Eu+nu0<AL7<3I^7{h@KUvtiq_r6(w
zpJ$&YvhP}gr|<AZ8F}H7uU;?m`5Ad$u=E?y8;#9*i$rUhg=X|#jlLhfZd~Yl-7RV4
z@a8%{*+L%*mSuqim#Q`bx%Jj67}IjX;CojV^258-xwatK^I|#lYNx;S0}1W!-%p)P
z%~_%RQg|`M&$#?vZ=rI+p&K-TRYQ4;p*@c&H+s(Vb}P3>dia{H<;pEu<Iq91HAZi9
zR|G?AX86MMoV=db)+D@9&2y{EU*esbKc<@Q@?hwMSuHC$HK?AhqHies-mK`9iJ4Zk
ztMWDN^U$doxuf!kRx$MStl?QfZS6~S=V)|kFm&0R`PS%kosqDvWbA|8B}|~<L(;@P
zXkR@fFIc5L41>46ve=|pD`t~!Q@7mU**|<r!qz90t%@-`|DxT<T@P<*1AJV;5QDhk
zgDenth(TP*2gWum&yo*}9T6rll<@K#%|PFU16ZD=0W8l_j^(*b)&5%ltJDX}vowI^
zS^9A03}t)Fp3*cd&(Z*vXDP?>%!Ao%Rhxe|m<>G_!E7Kra%Z%%1L2W7qm^?YTE8`z
z4KvqxCaQc~FdG_s<j!ba6~ZI*M28yTkvpUHMtJ1T=rAKZa%Z%`2#?$u9d3k2?u<4X
z;XRI{O-76c|H;8@Sl3euX5$xzs4{w1^%HtL|D9kqzT>AH%*MKxXquyv?5`tu-jfHj
zvAS6>8`2)3C(1%%*9i(3Wg)SjFqjQ(JaT9B^I9LFCwh2ZAE76DWFB~NMKGIGui7G*
z&Hf^uLNFV~SziRRS*1q(U^YjHda__PwA=O{4rW6y=LB8;SoD;B2o;MyK)&`Hp6j;;
zv$1+bFq`*j+WlZQQ2k&wQ2k&wv}+Z?Y~JU@+@>s=U^bL3FM`<s`qvL;L)qFQn9Y||
z_GH0qsOde9|7|dv+tscg%!Zmfo+Oyfi&gWf2D3r@G7!w>EG=gsn9cnvErQud0Y(_p
znZQeD!EBfXSe^aIGb2WluR6C{&D(XgI5r%(fts&Zosq2OBh(?yIqcU_AG4I<c!bz#
zd)rFA2fZ_=bpxI_j?EvbMiIvbq94bGp~51LjooyO#p;_O9rxqd{E$xaI5rUdI5trI
zI5z84Bp6Tr{G$r8srooJCGBGo$Hv~fPZGz5icc2DhB^1+*qkhCTM@_R!y55_Cyq_3
z@%nLWCPek)*f8Fn|KvC}^eMO=ju1oJCS`GK7~JSAj?Jo^&g0meri>zv4MabV&2vR%
zacoFhH;QA!PV+Eiw2x!Mb6do*;Z7BCY#7nc?WVj@5yys{1w6WW9Gg!ooyD=?8Ojgx
zk1ZQ1r{f$ws)UU`{9EGKjE%$dtsJt=$(W#_J>%lzR?Z;LKr6qdPm(aW<kbb+v?gPl
z9#xCAVyq6AvhAtpsFxflhUNHKFmO-ILhV0K6>gg^ab&Jl&e*BapNV%0zc&+CjEuD^
z!CFNJC6_6y^j#H~=QcKx{ut>|pN8csdzPzo2I+&FtEh7e>2*Dxn9{pQALi44A-1-B
zj879IyL@VAD|Nm~`kdCMNuzfzKaO={UgfZSUFjHYhrunDueTtx2DezgAtm3xJf5yp
zmHM!5<quU~Cc1u)zS7DcuCNx*x|MH?7OOylT!3TBA1%?W1l(fzraA9WtvD?G36uSf
zpX`t3Xxypx`SklYnyh<4=YyngB7J%H<4Pyto$4cdl{QG1GB@%Esd)!AKh_>5|4h<<
z+Ws>6pCSFp_BTntoAfR1ACev+eP{chNq<~3ao<ddP2c>O9<XYwd5D;rB>W0Fcj=R+
z`s;?Jzf)CuZ_GlQ2WmCdy&X$;#WPp;&b9PSDy;s->Xe9CT^q3@(^{Y}%wFw4_jl^r
zLIl=Uq@?AFdO=WIX}jmy)7r{9J$d%Dw$g_1>}hS~97<X<1Rz;kWl@&_mVcePaWB#3
zU-aMZj_MeDT3h2@tZ!fgmaiRBrLkvEYwL{g>}l;#BRqRrTW^GCPiu!6;n~yL1|vLs
zT07hb&z{yc8sXW~+9o4LgEo<(-B9gV_j%@kCcXBw8fhPEv9_%Wab<d+wz#&v#tMR=
zlvs<k6O7V#kNZR2gs-cbt!qKh{=w&h;4MS7GhAEjir>g*wn_U~i?uV$tkMI^*Pd1F
zsl>CVwX^557XV1opPNz%|Fe#h@Bk5=mTA&!m$_3!8GvN%@)@K(uzc+b-@Q8Fx3p#K
zY3*)zgU-ziY0_&yX<OwP(xlh!@i%pbH0iZ_E$!LU+8}#c%h=NyXP*6>p!UFw12vWh
zkgPpuZ9IEg`+1F>@Bosvhv&@^_wBtiYLCo2R)l9yYmX)uiSX=c?U&W7MJ$_f=4EFG
zwO?D;%SC9Kdu^I)MQEOn**NRFNLy;sq`ygxHg^A2!_}lof3K(`M$WuYT}YG8^tN<A
zq(`PEO*&h>t^3iJi;^at7tD_CFXoDpCjBegl3m^Bt`;RtI!@uIb}_W8Nt4cN<Mi%E
zy#p0t(~iqI!Av@%QO_={w#QS~BVYUdO%*jLnsxe0EjO%5lg=)5KPaJ6O`3G8*S%I*
zHEGg+rN3eKi+VCeb)Z~#C&NpV4i$HQCE;#OnsnN=x?j=rS(7IHS9-=fU6`ht*i*`u
zcVBq0C~4A>)~@az#I&VJr)+Ka8MKooeN?&YyA|z0O`3F`?2X;3HmfF0IyJX+sZo<A
zowBXn@5Q2|NnfPgZQYBs(3&*q)ZEd1qvlYPCY|N)>VEYkQPQOUwQ^6L&H1lMlg^Rf
zIyCzthL<LtBfV{C_OodzP5K)3`h(%ws~JR^^v`I)cMZ?}mU^#AlYWFs#h%K#Qrl_!
zez+<O?7NZ7MRmTdNi@hv!ZBTEHbisA2C9>l-=-bZp(#hNUq`KXE5kTYPLw@$8Atl@
zoX$AXnl$NWXnAwMFNkZ>r2ms@bpL?6Crvs;&`nvIH0cZ#c2P~#q)E5?tg%>d64LRU
z>vRMfHEGfh5l_*DBdrNQ5+dk+UALkpO*&M$`<xL`(xmglnsKDZs34o_+&gO0q(4&|
z-2DajRho2u2!rmy`X#7Ilg`}=yNKp$(xg+-b(d08nsnaGlih2Wr8Mcxd29D-)+0^&
z*`l^}|At<qNe?vQuI_GLiPEI=pq$gKaEhf#hq|zPKJBDQhuYnp!4jlNzewY~w0jq4
zOqz789Ixs=!YfyrbjI7$eMm>7CQUl+-rs#X<4Kbab$$1KmM%>?)F-+LBS@1D^{MWI
zy4Ivghq|@<ex5dI(&<wiDZj)FZJQ*H6q><}7Do#GrktKB^-)clbd34C=XKSQH0cmQ
z_guC{nsl_m;z)UklC*Bbk+RdA|BRmZP)(Y29@Y803~JJ(bEoG2twyU!lg@~K?3y;j
z8ufw&*D5m!$r<HYw8N>4uF^@!Q#s0GlON>6EPI)*j&rnA3F~M$7<(sg2WirI8;!jM
zLYnkDMKteI&HD8tn>14M+uHs54P7?MaW+s7TMt7)^8wAa{wFhEqpTK6)vfUy_eMR+
z^+b$GJg@e1)tCMhVt(y!L=4v_Ar{oSnrB#F1~FP66XEI`AjWEYRjpQ^2Qgl&swA%e
z7-GVDYt(;nvxvzWj6th@Bqb|r9}>~2UktITx=CZst%ne+tz@+RVu*vRWUBrJh=Z+U
zS^X-AHCD2^{sH|S#A~Ho)Elw>D~LlB=T0xg`kSb>&epauaEyS1a<&cQV7ezEJJfu}
zar*H;qIt9BP{$pqz5E|aOau*_otuF4C-W!CY68-qEU>*TVU^HWVo@GSSS2);bs5Ku
zN*nvngkhh=%Ct$Ka9JfVTnVd$=7zcBI(Ds8g|4~L9V@~dRhpX`q`jj`bF&dRs*EVJ
zgjGUo-R#qqZkbg=>p1r#5r#z5+TNm)N1|yR-{QULBU`q1RCn+?t7DbWI>8`jJQ7Xo
z#OhTl@klhSomHmkk!V`Gs{dVtN1|z+RQ<7t(K=QMt&^)mdPpaOmRTjVHn%z|n}K}4
zwIwF)k!V^+#<N9uB%0PywsxnL?9e22=C$w=Rtc@6ODw_O+sCSY&o0HUK>kRKsz{8F
zu2vJ+7^|twlk-fL;+qftc!L#VZESJVdspk%=fy17x8^S8<KB=L|DY%)rG_8S1C)ff
z<>l<jKy!Eq72mJo5(Wt~w)<0pLBfpVE!{}fq=Z4jj1&CFNJH<A89RG+Y?iBV*c&A1
z!wrLk(reV`j8p8@-^3uHy|ZP93xkCAGiF8F#wG>{?K9h)ggIuAkjfz8$Lgz#K|(5n
z1V#<I7$l@JNMN2}x1(z+g9M9;*2N$pl|ceEYhCn_LY{8WNxh3fLMnrVUx<>=5>-fM
zuP392HCLmvV3ny15?-M?=ChQ_Ac0Zlm_b4+g9Mh=#ULS-L4uzg1_`MQ68z*aNJwRn
z&{Rd&#ULS-K?0*@K1-<#66UIKju|ARGD!FqeIB8onN$V|b}PCVB&0G(@O@&Ckjfwd
z%5^bFNM(=!6?ZX6NM(?~c&#o538@Scm|5ntl*%CCV#YIrgj5CzM`(|_7$l@JNbuvK
zf=p$Q;K%!^TBkBd;I6tZ1_`MQ5}@KP1_`MQ5};aL3=&cqB(T2BXGsBuOLsAz86>1K
zNcaNdq2EhokN^>MF-S;dknj~zVfV|*N@b7$<+>Ooq%uf=in|yjq%uf=YIQM4NM(?~
zP3d$oNJwRn0EN%e4%JCQ)?mRZQyC<XHOCARQW+!=e6EW@LMnp<h@gu>LMnp<zj6!`
zQW+#r=DL5Tep4AF_?2Ujkjfx|(OO+t+*Ae$Q0*=T38@Scu28#9_w!IPNPy~fF-S;d
zknl25bGsNMq%ufA4?5ai$apeHVD!l@1_`MQ5`JHQr@9y<q%uh0&Mxa>kdVqCf$<LL
z;<J>>Ac6b5yo*6XDuV>56<rJxQW+#bt?XiukjfwdYE>75gj5CzP^-JB;!_zUKpoV@
zAR(1O0@T6Xz1$NSBtWg{Vvvx^Ac37&+r=Oul|cg3`Yr|usSFaJHg=y&O&KJxgIl^7
zB&0G(ploXwgM?HD37i&umX6ooB>cX{O+uc-BxH}0kO#timQoocP&^iP)lvot^fQJ*
zLMnp<Dm&VJSqXcF4-Llb1t5cjzo3w(_3ped4aP7?NM(@lE#-}2kdVqCVXuh9-dST9
zBnV|=4vQYcAVGGxp1>d>l|h1)V33f?Ai)R>5>go?7=b}TDuV=GKVujqq%ugTKp;&?
zWsqRiFi1#ckg#4Qj$QbDox+9iZZb$1!yqA*LBb1_Ifg+(DuaX%iAX|p;$s*jq%ue#
zYph9S86+5iK|(5n1PI5)gfjHo3C1u;NM(@l4GQUKuM)OxQ84y=TFM~dr^*|%w}A{2
zX6n6@guE^sm;FWN+l)a%DuaZ1${WKVA(cVG(N_OX>T@|GudkiQAR(1O!g18cAR(1O
zf-Qf6mjAlErhJyJpaupBsSFY*s7-YiR==x+`7Cu7C8WL2QfG0(^Wc4!I#Wh?pQX+c
zdqc@*3C8+9wXm7b3rZLybe5L>NLh~jl2&eI)u4GbJGFB5!<6wGK3ioIK@)?7?qyB3
zx`{zT_YL-w)x;p7dyP*|9jElWhB%W=3=+B@Xadr==ztsa%XngRnR;IRvXc9?{toT=
zjC%402`8qMfDnH1?n_j00dE4i8d-$O;S=|JwUwT;1Y3b!G5mmpwM#$pTKzrAm=wZS
z?w45$z$GHBU2lT~w`(q8@J;;?XYk)o*IaZTg5@vwVT9iL<3gfq%;E5op19B__CPX@
zad=tx=~S5Rjr0O#g=blQWu5N(u#5glGZ}W3gG3nzS=uo7t*Q_i2U*(akbso2Yb|YR
zkPgb&wU#y;Avc^*3)J<Sy1H9+$>f>tcBPH64A;%RTj|Ic%kVh&9Bo?}bJuWti?%@-
zbJy_r)~!mrGG-y+j_MCpD=x!Wh9^`X7SSqW?i!w0?Qtr~n7f8Mt7}B`$_H)~v8#Hr
zh`D9VUBi>Ah~7raFqZNX-y>o&h>WoeH@DuS{;DvR;g*=Rrl4~W9vOc?L|A?V;;8r|
zB4n!`epeMLCL61HlLF%}!=p>Aq)x5x>3?jOTUFN@+C|MiuA)l#>AWT@v6{;KNuJr(
z?0j=e(W8plz)JYbyb>#Y+!!jJuUwk~Yxl)8&qqHjFP8ILR!m9_FV~-h&$LQ-dS2<>
zMJ4M4Qg$1a@RdqTH>1d9{nRUEGJTF)E{iAK#EhaMGl~zYc?(&5Nw10-SLq^Iyx{DE
z8Tf!n7EgZA<~*lLrPMD49c1xqsGP~-ZClEpQZ32i`LylJ;%S!4;!)n4l-iBV;<!g9
zrFI9pPtq3x7q=oM9aJTyb}K9N8<zLiW8hZWR=V<yiy%6-3+2svf4Y@(AX-&Psokpj
zXVko-oqLA<ws`^GuKzY~jmO96q+8>*>*uvRq}jMbs($YHd%1N+gyq-hC&wLXgp)=@
z#Cjv*@)c_64l|-vK7be81|vG<IodCGxDmbbb0IbwF}M6ty53~OXwdaiYIm%A8*@NP
z?VeU69h6_E=iF_pLR>k5l-g~tv4UV|1Sz#U!6-?o+uZ&SshX{8LD2P5YIlaamriXX
zpV=lIl=1g+XO{g=VnpGdRs9E*xU$XU?D_1))!H!nYyVmo{%0Lm!eKF5Gb58yyUW~u
zqRL;@E5ThpgLF`yxLL#%zI%1TL5WOC?e2CjD{~_+4%|=LR=FxEwY$gP)T*S^?p{l~
z@)4}{zUtv>9G5YoaQ7S0s3N6y56mcOtXBC!mhzyr>6Mpo>wjKjC+3z{>-FOvp7%2?
zZ?wEZuOIiwJQSCc<&SeG9!=JWm?~fPDiOb|o*-gb6)Cm*wROE*gr>RIrny#x=J}Y7
zv%Ys6w_j4~Q`Bf<4=J^ilo~GJh*?Ofout%EZ%Yp;wUd;Zt=`r{O6?@22Gwat4=J^i
zl=?l|l3hKd)J{_BBXo05?IERhl2Y?Po!;9hF2G4jO)uy8_Xmw)yVzS`@I`c;iX26m
zzn7DgnqBB2rFN21+v)BhrFN21e^Jv8dq}B8b)Z~tC&Noh4Hfs0QaeehY1ir@rFN21
ze^Ha_^pH|JNvSDY-a|_5B&GhI%2xM~QaeehDO=k^O6?@2en7eFdq}CBq|`jw8+%Bp
zout&%+|olb<|L)2Y-<lGwUd<kXUg5yLrU!=rKaYN9#U#2DK*RA)k8|{B&B|@YI=V!
zCn+^YKJ)i-l2UV|Gk-59DRrP(iQhy@?IfkXN(;{Xy_}@fu}USSu7n(0d)aV;2KN0{
zjwf?bokz5x_1iQP4%R>&vhq5!RAl{d-uiXa`Y>hKJJpy;-l@Z$zCs1ryQ+z?gp+7`
zg$|c@@^TVQe@-=e_JB(?4H5JZO*@IEnOfLGH0>mswwtT5SY;)oWAEhUB$^)9R`w80
zJBg+tf*zu2C($%ixrb=lNi=;FOAhQ$TLm^XoV=Vw(~Gt9Jw($^qG{F;^bk$U38l>~
z3VVpA6&S5WMb|?#?IfD!bv)TaH0>msX3krCh^C!H({e1=ZAUciB%1!8n)9w6qG>15
zG*8Dly$VNHqG_lLdx)l;MAJ~adx)l;MAJxBU)sBiQ6-u_T7R$VA)0m)O*7t}9-?U{
z(KPMe-$OL*B$|f0zK3YqNi+@hiC)485=}#Ws)uOWNi+?0YY)-1lW3YgZwuPDYw`?j
zn>5SQ3~qGA)2HM#PF_x;>6a^`hiKYKGz}5-5KTLYrr#v$g@L`2NLn}Zf;KzNq0i{~
z4>^gZc|Og_%SklNoiZmcC($$``mw*2H|hn+waTo7<c#u&+Tm2j50$QjJc^?{EBQe#
zE3G51!nU0wkv4iJnsyRR^9nN2w3BH110qZxzDYI519!0gOdw9J&YvV}0&!|}L6?m)
zL0N6Pam*zIWwqli?VhW&3Ce0G^f-nk1ZB0Iy%#7QzD|WtASkPyVh3>|1NS*gRVOlV
zp9@K6;6ATa+I#NA5|kaH{q7+s1KfvEgI*5q!|OKeAt(df=Orq0y&T+!nzbI^$$<ON
zNxheY`y3;x5wxj7GTSVppPthTg61uBEI}DDQJZ+~#1fP-iuc@!B`Eu}s`n6-0q)}`
zmxKHG$ss6<B`AB2D!LwmGQfQpwH7olg_NM|Qjy+sCzhaWsm^T=K^fpa^b+)Pa39}i
z4(<cxdO5fcRNTwKeHgFR%fWq^SzGD|{fQ+g`wHWkpe&Z4?A?r)gZudL_%x0sDD&g}
zR1aA!K^b?|^$?T+?gJI~a&RB0RxbzlVSSyTiRVr%LD?FO;5~N$_vxv-9)dE!eISA!
zf-=B;=8Fn@Use|2K2WZQpbT&ysJMrq3~(Q)Ru4fL;6B`xP7gsD;66|zdLlleVJjhP
zXyUmOOHf9Z_uPpkD7#I=_Hu9^h@h8)`}mb3D2pX1qs;XXlmYJJSDu6WFj}jJpbT&y
zsCExQ8Q?x&Q@c(NK^fpaP`zFb?(=O?b9*_s&-X=*_7Ic-?!)Mly&T*JIpb6hK^fpa
z+}UNl9NdTT4(R3JKHTT!Jp^Td`#`Pe<={S0D|<P(57eq2f-=B;pjP*Ca383HdI-t@
z_klXNhoB5_AE-4w1Z9BxuoG*0Ik*qh`d$w11GTY-pbT&yc5q8C2lt_DYY#yg;69v|
zZMsv}DYp`?&^jw2&tWBGk18P#L=(@QSb{Q&O;8p~P)0u{D2pX1qjH;e^HkNI=}b@-
zOHh_5ug%lSr@Iwqf-=B;mMYH#Ww8WhyF}=#Q&mk+7E4gZqD@d1OHgJ6g0fhGG9wU_
z#bR8HKu{J-P-a99?!)WH1ZA-VWzVFyAF`hklv%YL+y^(FHoI__<}k@GNiHahB`Etk
zvqVr9OHlSJo8`S)vI)un_aVy!Ww8WhMj$AQB`AYvb6KOeiY-19l*JO1EmmHej&|jR
znV>9|plplsOi&g}P<D|BJx{tDZ7x^k^|j48xX*6t=iolz$y7oU9dr5fynZGqizO(#
zmih?FVhPG@`Il??CONa^2kvXs;43SZpo{_uz!p{ykPM`Z=T5RHAsv+O(j{4(@I1^f
z<GGVe88KSMb0=A1@2g4wQ@cSeY#TB`S+cbBka}*De_CEv4JNLp&y}-}RaP5e1k&E|
zU;;r|<Fe*+L`@(lYrLWTTGgCDP}aD{rxBDj-ZjLToIp_4_&`%R!NOy2(C6Z^axR-1
z+Or54<z=(^t;HoKI9Cs^oL^p7h_fzH3-uCQEpe8<OM(j|+RH5oGdGP~5*0pE6`z9f
zVqvgoqO07mW0^Y7{W{Jdjd7s-I!G6O9ScP~1;381s`l6VU#0#N_;oPWQ}*jf!ddK&
zx0`N|&OJTOQ7=9gb9A74g9^+7EE<T#9IdR_y6OliqLp=s!qWqy@brLa5sNu`vRKTl
zMdO)}LY^LzdOppRE;_`Jq6$wBKOjO1d3yK(5mLz0!w-m%LY^KrU>zZaJUt)^PY;N~
z(*vUL^ne%*vRKT~KrH5HFcxz(7>hZY7K=H0f>_L~Ye6u>3n`+3Sj^F2EavFUGNXG_
zI(d5hcP+p0^k6UkZ7gQraT0z{rD@ZI6wyE|=IHVnLwc|Si^UvW;k%b8p2Oo~G0W2<
zkHs7f#A1%_@i&!N%+bA;E<8PsSK~PM^nhqsEavC|3wG>H>7oa%&41j}qlJ(n8jQsp
z?X{56J{EKIn2qCOF-H<otkQdFV+SEcBq0Ug>qm4EQbf~YF-H<ou+=^mb0i^!WEEK~
z=14+{ek|rlLW)Se`B==6gcO8z^|6>E2`T7Bv6%ToBMWhAaGx_%wVFx3_WPwOYEa%g
zeWiYP!e}rSb0i^!)w5X4k%SbO`G*~Z6rwt2^xr{9A!<HU+(AeYNk~Dvmc?R@B&0A;
zj}D8*(}S|*7K=HOkitAYItVEu2`MOBYq6Lk2`S9eql1tlnih*Wl8}O$TPzkco*ujb
zwssIwL=sY%r$+}NMI<2wHFsDn=4e_h=14*cjNAL39!P|?4$Z=pE}9;TIg*g#DS3J%
zA;;GC9Y>CVeK(T1Xx~RQwIsx^W90S9NVPKqHOb2F5Pluj8-5-AI%;ix9Xv4XtG#Vy
zMF+hzr?raQucIG^Ig+RXSB?&%ib$dg^Xup!s)!`2V1l8AVU8rKuv@IL@axdZbe-<k
z(V6Dg(Lq!ZNmOBe9UVj!kwg_It4mqY@yGl+csC3OeZLM1!yHLeL4gm$97$BcIrU+f
zBZ(?Xx=}t1b0kp(8i&aaqKZhO3g*1k!Z1hE!Z1e?RhVB#2T?^dEevxsEevxcQ3cPB
z55pWuRDp!aV;n~kRZNKTVVEO{Dj3g)VU8rKpq&rH97$9G<-;&X5>-I?FwBue6;M75
zb0kp(ln=ukNmN0fSr}%9w)-h7I)3sP+-O<RL9fc`LBEa;qKZhO3iIpeAgYKYs>u90
zc-fj?2U{#FI{uhnho_&KUk78GUk8mczm6m<{5tG#>XhKuk%T;u3wUDkgN$EC5>EH)
zprZl5jv@?ml!aj)`&-?&^79&Y6u_3L_)yE^e*iDFWC%aKoH-iWLkQ&ww2VVb#z>2)
znz-=U7l}MzzLC2%f%BD`G$(Co4rPm+X%4?|gJ-oqD^}}T^(sNDSS@pfRcr`cVN0IX
zDtV9ClE*SEc`U<{$1*H=EJL}_8kV7V+AVo4p|M)wK?zGXRx4U&?3J-v(EzJemhOkc
zP!6L37usmRg*M7vXt%1Gv0BuJ)rtmOXrm8XkPXjjMblhpqX8G%D0iXttd`b=i&~%6
zs*KD!N4<Mit1`f9RR&nC%1Rr{do5H})>))ywJIw+5T4bltegX3tXAd8SS{9)vs#q_
zR;zM|Jp-QAs;o1@do5HBHNtx>RMs2ey%s8m8R5MaDjSUOtXAc4BRs2B*=U4kwJMv8
zC|Iq^0IO9QWVI@TtX5?jt5tadR*Q8NtX5@!)v64#T9q@)Y>{WRDub+6<?Q)S%xd|L
zr?Fa<0amLr$ZA!t@ZIY{;P7}>tI}t+Dg&%m<sN@iVYMpvTH3Q(mHVoFR;zNq5uVkm
z46<642d#}~wJL*7wUt4q+R7vI`Y|Ock0w3+$at@X$}g)cMJzK`t1`%HRR&qD%40T;
zXSFI~wbrVUXSFI~wYG}#tX5?jt5p%J#a4S(t1^w%s!U_GD$`i4$~0E1B36rD#A@;9
ziC8W2wcn3twJL+GRz<9q)iYL0m=g7CHEqvoiRwT(W3@!hhw`jeMXVO>JgZd^t97m3
zk{x5UDq^)L^Q=}ytkx|mTWzdXMXVNOp4F;|)%vQ+)*Gu;nZ{~W#A;E~vs#sDtX4&=
z);H8{o3UCIv0BvhtX5?jt5p%J^$OMWtX4((paE8^GM&|`h}HT#)y<r0E7AvnxR*KA
zR-_LCbI`mNjMZYyCt|h8*S^DQH7Fn8w>V>cUTUWCTUqsAsixgZj$XfxTF+O8@mHKE
z<F7M*>(rdqPcHmcMXI4bzf}>x^<LF5eybvW3qpR+u_}t+Vpz{_Rm5-Eeb!hkI0@<4
z^IH|EhVG^l_^pamLlA-STNUwJP-Ww{D%1I`hgFbGb<Q0XsfL`k&iJj0_$_<Yc2Esf
zrtw=9@mo~%{8nWezf}>x#hg9ARhh<bRm5-Is1bJ=zg3yWZ&jx8Ta{`2Rz>_)Pvd!h
zt0I1DN|fifD&n^o&+}WAY5Z1Y8oyPU#&1=o@mrN?{8mN$7JX*?7DL-6W&9R{8=di6
zYjYZYt0L79oQUyT74cgTf$>`v@mtRqC1VHpEt1xa_$_vt^PkakAF4<-#G`6{v=ym_
zxKrjwTajvr5k0TR*O4_U_$_i4@U-Uq*5{SZ_$?lrnXF71_gOZOpN@01R|)GV<F_hO
z4Hf)WCF8do@CM`Jkj8?>O#K;0HRR?`k~NNM$YoJFv9zydabDSgs^`llo~DZ7rQ5}O
z9pgEjKbE9Swo$;o_%IN%joKr^tm|bPMcP}}%QgxE>w180n(w_qOlEDp`?(0SsIP5E
zC<yAW&_rs7*BQ&z|KSu78x!eN#AMv4Hnk(=k*GJKA#B%<HiYd?FhXrA`H&Y$NVgVh
zqPDX|**My$+B0UILK<yU?aVgAg?HbeArGDVLDHCx#{+>f;w(_cW_4_VGU9<i8F3aU
z<4hGkL7<G-2g>lFEWoMzsp?rM3vlY_(TB1~WEKve8(Js}aO!YC@u4ihsiUS3WdTkd
zo%m1|;MDCEC9`m<kj(DC(TTosjn2%%!Kr(_>X=zLICYHTLs@`R$0xCcvH+*fPcFx)
z^OMVQ>Sn8=4`l&P9iwJu;o#IQR-q4N0Z!cy=@V@iICb<ASSSl{>U^I$P92o9P!{0S
zLB$rz0-QR=^Pw!jsbglDSvWX#h=hG83vlYT>y>MvEWoMr<Du;Wr_PUuwhNp(?wAi{
z0Ztv14`l&P9h47c0Ztw3%gn;Tsr!4zD{$)WV7wfs4#J1B0H^MoqI@U|aO$9ZC<}1v
zpnNC`aO$9ZC<}1vxG6rA1vqt3n1vJWVjz?SICW(CP!{0Sy;KXcP!{0SLHJM>;MDn*
zqwNBxjxrz00-QR(a<pCG)G?Y5WdTkdln-SAPTi{*z(QGoQwQZkS%6cA34sq~0Ztt@
zkv^0KICYFZX`w8@se8N1d?*WW>bSE$lm$3-jORmHfK$hP_Mt4mse|&NEWoLQ@}Vri
zse|&NEWoLQ@}Vrise|&NEWoLQ@}Vrise|&NEWoK_CwwRiaO$9ZC<}1vpnNC`aO&7W
zAIbupI?8+~3vlW<EtrL4O^}55*j?i}OhWc333(vQEF7FVibpXE2d9pHER+Q}b!L-6
zyT4K^dxj77p)3+<yS|`2$J6?cd12~9S%6dbL*-d03vlY3SP2ExP*n?M0Ztu@won$}
z)ER-c3!FM5&~|}SX9U_VaO#Z6aq4*eSSSl{>JElL+XYUYRm*YeE>MYM7v8QpOfFLu
zX}d;qoVr&l(?VH*Q-_sU626;>=Qwp_Sttu|>Wo0!1x_7=<MQ|VZ#&ZoMzQ1pr;dOV
zj*gtZ=B+UDp)A0udsKy^_BN2VYg`qQkk^IdvNo@;ZARM#PTiF9ER+Q}bthVVvykF)
zUS3~2k6Ac4b*EAv9Tqrsw*2i{{#)~!G7EndHPCi}Q%6A!oVp(?VP@gNsUz*p!i7`E
z^We?Gg;NLN&BBFK$63ijS^PpRY^7N!3*ppVt1L%;LzA(xER=<C>K;?Jg|cWK*yfN~
zD2wKDOD`;|+o5IEsPqqtx3I7cwW=MJ9)g+=wQeXXovz3WiyqT2=FlnSQ(sY%&7G2a
z-mjq+^WYCXy+K+g-HY#|(rFpFd-2VXr#JW|maVvUf2q2h`Zl?n%LrxmXzfFL){322
zVof)X`JT>Oe8qN^Y)MbIrY~H2p{m@W1~TglhK`ycaO_~eoL=@KQS=`yrKf*VwXIY;
zx-?(p{zqEr#lZn5DzTpFQ@FLX|Cv^>I|vT^sb*9<e`$#t%g_BR#8Jk>9N5-0hTq~!
zjKBOAaV5iVS;m}#6=za%iGwJuw36L6TQSPY3WGm-V<Co`b)z^RwK?m`lG~!c@4A1V
z#&4g-PfzU7K8@c#jo&_v-#(3>{b23W`02NCpT_V1CXHW3oYBzKP|g?)?IDbs*Y-_~
zlLq6>hc=xIh!qzG*Sx9Vt4_}Ns%ynp$<it~<iWmr4@|b<@69|++2*bmd3|5x^?i}o
z_eEac7kPbO<n?`#*Y`zU-=}u##6U-xSKzC}z$)Gs(m3<=QoOH=NN4fBNSE>T8kW9~
zu`9&;`i>F~UoXY``Uq)!y}}z(@`LKrb-7pnYt%0Vb>e;1kcQyvrFdT^`HSVG6DZ!-
zpYzA#t|{IZ&CJ(J@xETIbP_hgrE02mq3^S_`F}+tvo2G4VOq6^{>@ZiMM^qo$^T2H
zRg4wJnQ0Y-i}C*wh%Q7NZ`Lgkh%Q8KTJ=FS@5nW7v;I~Itnz32Z)?$bxoOowG9ifZ
z|B`7HjkP$*8U>;Y5yqKm6@-g3(<+EK&P=NyT5)Dt1<{G|{}PBUL@&nwOCY)sb7TC!
z1fmO3==;QIy_h-R|0UBZ(m{;>mrSc5u59D~CDSTa5Dc~P|B`7Hl>EP{<NEu0RkL*!
z`aYRf-ASjmk<V<C4r2VjWLm}OVVr^JeoG}T#{Vlidp>({wKk0Ys(0(c|E%Li_<)GM
zX;oWIV*I~kT18rDFE@+G^?i+y!&8`6og*8Smi)hDT4j}6^8b=)l}#lxts?DW{J#XE
zdlntW8Hg@KVOpgJN&AiemrSc@(~I%{5{NE4F*nBlOCY-6iL}Kr{$B#o4J41AjQLKF
z9!(}iOvU(rMZc_W5aIQGGOeQP<x>7>ntN@Ug=rPz^i8X_s8QdvYL}?KX%&5J>EQo`
zX%+4Ird4kiwWEXo7p7IO(w6M%;Qxhb)rcnFH?86!>zh{5OQ!Fm(M-Fr+L@DFDArB;
z0~Li74VYH33!VRmy>}0gqo}vXyLWmgovoej+3D%-dF*CqHk)LVY_gjtK?4R15Mp>q
zkXL{J0TKuyLXgNqp7IjWfPzX?6hyCpAR>aI-~$vz<%)<RC@Kmn0`gFNpuclI)jd-S
zLDB2|eZBYgA3Iy0s_Lrhs_IvLPMyR3UxZdkz819VdNjKYt)iv<eS}ugYD24dTpL<-
zJ-$)3zmL!=rnR9}gimRIAE8xDYeTE(7|{McLaTUXFDi5Y7ok<m*@jjztqrXrq(l4r
z2(4nyHnfVTzr4)-UxZe@4LRG;Do%L=TE!{7%&wB9jL<52^b8W+H{yg165T%_75+ZY
z;j|U!9KCc#zl+JXAkQo`!gC%(hUhXxaC#Xz8I_I@newGH&boFU96b#Ya<}DVk_)aw
z+pAI=H}4c$Rl(I(6M`~AtLXn~L91wJS0ABOY+xH&B}0t5c&<1z{I;Q0PqL5{T17*<
z`UtI}rCoi5Rvm$)ZfiXM{S^sGQ#G`zj9zO&tN6rdL#sGYZD<uUwxLzLDYv0jY;*fX
z>ttBV%G?D;Xw^-qQM>vGt>QJZs?1$rgjUg7Tjnk>LaS)Cp;d#ZuMMr53#$#SVts9B
z6_0B}t7x^MRkYgBDq3x56|FY3ie-My8b1w@tXev$s%=&-_Bd@XPVE$0brd36&?*|*
z)kkR6Nw79r<9YvNP>SiZ#<Qn6^%Gk|t9X^RD04YdEy`ThsO!ExJt%SYc@AUxd7;YW
z#4Py+!k)tmvY%H>I+34|XacOpa~_SyMJ2U&v?+6WBWk=8iG)_23nPVAaViKw7NAvp
z@DFUy7p-abMJVLT<Za2`Ol#sG9w_#--eKedfy1C6tw!X5hb6U18+hEDB3`EWDmG~z
z&AExW9<6>4ikNJ1N1tO|`_9&z*;|kg4+5+A^qkA>T#x@6Z)SgAD7J-TAH&4(vf2fB
z5jy~t2=EFoV%ssCyofO@7<US<u7UyGDFb+g7qLqaDFnE95xWCn?asXqf$_{w;1yoP
z2<H<5T)c>}E)BfGi`W$iJC;KNT)c?!Foy)Vco91m;cmyd7+nBT;3cpM&Ls3fig#z&
zc{ft?KZ^)~6H?l7MV~CZ1&6z%gp_vNpFIhaly=+;-K<<lX~(@Ff(AZGX~(_LEAiJM
zaok@ek3+{T#M)SIk#IeS&RPhxQA(~Q&~^_Dan_FC&SO|RYa!4^gU(vcM&ZALBbBB2
zi6d25bQ4D^^T;xuimI$mtI4VncO@PJ0^C=#z$b*165cM=Z0SIaCR4K&8?Mo0%9LnO
zi9|yQz<o7G9gf4vft$yF_m8NMTn#cns88N5)mGS~jQaR?skR=k2Z?W&%9LnOrbL4>
zB^s0|(V$F;2B;siG>s-xi^R}qGL=d+1e#qyEp@lW4MR9^)$6(#)*QHM*?1aSO;+vN
z#WS$9nylJGEC(F8^q1|5Y;s;LHCc6lyNQMJ?NS|BVpwzFs)O=umqwGRgU4Tr6b;;0
zhfH8!5V+6s+>hdie@Vdw=UNzvnyfnB{T?jgz*TSRVORtA)d{+I6vCT=R+CjfbB8)P
zkn1h=NJ%nNO;-I}4=UAU)h{Hh(PYZxz*PwcZi(yy>X$vAKwTQRuYM)RXf&BJ(PZkG
zzW3qA)=+%ARL}L@1w(V-s^<&8fuYf4>JQ_`!F{jQWYwRgXssrzUXW&LHCgo+sYk2H
zDxk><I7q9>Dxk^wU}-g31vD9(r`2Q?-Y(hIT1{4^XtIcJmkMu}JEBXpnygCEWD(f~
zREj1OHCY8T8B2khEdTMKs{C-=tGvjoj7NX(fh3Pf3A=y-nvA_5YO)G%my%D^WEIe4
zZ$`7Vnk=j`Ev+UCYXU8;CaZuZ<8fL|7Oc`P_13kTtiszR)3lnb0-B7}np#a(;q8)X
zT1^(p#9bdmnpTrlc)R44t<_`|-Y%I_tH~;$$(W|qWEIe4AHi{2O;+LUk~y`StOA;h
zr?1sy72YoCI??O`3TQG;`Gj3S0Zqm!ov;fiyj|Xeya~I20-EeqIN^j{KmkqmC8P?P
zjMG;7{R`+wqu<43TR6|r2#*m3=W_g3&POcgn30`P=`ekpd3Y$NUONwtCf-M2L7Y)?
z)d5Y$t7t}Q<FUk7Oa(OAgE${eG@$T`c^q<xnydnvjD}W|Rd~f@Ra#9}0Zk_3jJkNj
z1&0M|q5%ao+0873ub2vGG8$S<R^b(smR6Hhc*T4bk`fNwuOT66YTw-oXtIa!1Q9h^
z1vD9-g<4Hk0Zqoy(rU5_XfkHhYO)GwGTxcBnydnvjBVCxvI=N2?h?>yvI?)5r=mu!
zCaY33S;SXNm7>WazGA8rO%{=8Kmkq0w<E14tAHjW_DQSBDxk?&pH`DqDVi+eYl%wH
zWD$u5REj2x3alYTlSRM6d8rgl7LjN`0Zqm-fhOYvn^j9E0Zm3*fLH7rpvh<#Fx@1b
zL<0(Fvbl&5HCY8T84ax_tMH1s7#7fEyooX>hb5{Eod1bE;VA_)881~K8c;x!aioN3
zKmkq08g<?0r3WQyvIU1RO<t`sIWbG#g)sJepdXvOY|@E*t3+RoUzhXfI|xYaiJGhe
znv8cNQIl18#asr%{R-yz?~xO{t&iiM@V0hO7-W?2ws!Z6Vu`@23YwAAAw;N<Fmg7!
zIEPSDK{IkXBpN8}Sy_VfDQ<(ru|xyTTiLyP%S6;90v=#hRDc!vPY<vvmZ;@Fy%bg@
z@}C}HRkM($<v%^Zs+d#De|msbu@Ei)=>b;tLs)=SF$;r9M~MCF)J|Yk9$;0g5ht)J
z53nlMqDcfiz^azvY(@Ul1FT9nj<6~ZY@590I}u@39!Lb9$6;Fj(*vxEwI;AC53njq
zxoQ#t53s6RStemsUJ9!c`A;u}RYinVd0^XQ4O;%wOJP+a|LFl%#rm}Trw3RSTb978
zJiw~<Wqm>--~m=O+>QE3BH*R4s)#@eFNIY_zrh9M0anEk)AFAlU{$oV{HF(46)i3Q
z=>b;7^Gje=9$-~>u|9!Sc_0z^IP1F%IXsXE(9rUq9$;11!_xAf9$;0pwEU+BSQRZT
z|LFl%MN7+ndVp1NP_+D~2Ury?!m7A++kjPhfK@R{lL&Z#RZ&V(<Uc*Ys%U8WPcMa4
zMIT2Gdw^9jP0N3JfK}-;-@rZstcta1`A-k9Dq33p(*vw(C63ebpB`XUw6y%E2UykN
zu(bTA2UyiwSPhZ?^io)r$bWi(RUL~oE&u5OR>hIk@}C}HRjg0Te|msbah$dMrw3RS
zEiM1)0aisz%YS-+RngM&pB`XUw6y%E2Ury?E&u5ORz*w8e|msb(bDpt9$;1M2`&HW
z0aisz%YS-+RngM&pB`XU>_IL6=>b;7G%f$>0anG?LRi%b{4Y3PmQmw%Sa8@!1&0@e
zz^XjJs+c@LSd|A@70VI%PY<vvW_EepbqL5coydQBfK`2viM(3xP7@RPPY<xFTM;)v
zwoMPPs$ak;ILs>YpB`XUJZX{t^Z=_8gRm+OuqrVKtMc%EA_ieq9$-~s5LV^kRfV@7
zk^l4nt18nVtjYtdO0p4F<$-N;XQa67g=6ttALKLVuZjGp2NHpU5h?PY9$-}$z$iEy
z*>J+DJdg-5O5{I1z^cR`tjYtdiiXRdyYMGHlgNL1fK}bXL>5FM0ZB~cKRv*z_>C>{
zpB`XUq@2JT6wcO_dj`z3n+dD(0ISL)PUJs5z^X<i|4q!#pB>ZuiTtMrSk-*yC#=c?
ztV&LwH0|rtoPbrWWDdfrJiw}$&^6>w8h<+i0;}>T7Z}#CDt}6W*Mo*t`9or8Sd~9j
z?ofbL@ezIxj*ylouquCA?hHh^jDI{$OV~F3*|i4|HR;nI#~Z*?^1YNUb=aGCL(3;0
z4-v=(y|Yj*R#m3F|2%y5ZKL=lO_<c#xc}SRCg$299<U56CAiyK_HMp4^>P&3vF8kC
z&sq0jyd3NCi&~2-w;~lIV2z#u0s&;{dEyl<uH>eUptwxo2&2pu&rIP6vo2FO$`p<)
zYjvh@geM4AcgX3RDI8@AM_S7wQ#gW{z%;y+WC}-kk(HN*OyNknAyYU?x*=0IA`yM2
zaFi(=;TttmI0AGpQ#i^LjxvQKESqHtN4Ohg3P*4j{(CAM-NQB36{2vo77MA*bM4ho
zI9egP+%1Kp6_Y7`)KWNFG5bv9@7Sajjt(5FaCA^h;i%wz5l2lQHiVA2XuDAAvUbH+
zg=6gj>7<0N?15xqch#9WcMy4w_-%VX!@rKMtizxy%NcZKFJ^`vMhpHCW?1Im0yFF+
zME`@#urHx2!}bOGJzCorxG=sYW?0sx0cK!^rO{%BrO{%BrIBu5*o2}8Fyl(SxB*B)
zC_AW8-_H>qd=WD&4{kBT($I8eV1}ik>B_(iOGDF@ff<&DrYi$8ER7a3ER7a3ER7a3
zERDv$ni-a3WNu#|Uz6@gldde?zMzur3$K6~Ru?>muIz6y!}8<^Go;VIwSD1bm|-Qa
zxqU$;+ZT4j!LNWBmdC#WX4p1e8MZHwN=gIFuzjITSN1oVVOdXm`@#a0(B8h#rYn0X
zGc1p5Z(jh~&Dg#`E}!=Hg-%Sz_VxurQ@6N%;UAzYdkHfv8)LP$FI<U}Xm4Mj)!x29
z>*cmDTnR7u%WYq1)0Mq+`vM7&+S?a+mA~Bf1*WyPFSO~(Ub=mO5Zm_l1=2OOw=WoU
zWm{l|HR#GZ$I_K`{`=FFb&jDc;~s_&V8B{?7-+oQ9tIg_T%0eaE9*4r$~wo;m2nS4
zo389d^sr;-$~sNDGSb8H&e7h(z|m^&VQABpy_6o7Gqt^k;V4+`Jq&HSvVV*owoO+?
zde}By8R=nJUwaP&FTVC323qYs47A#N7-+TkFwlDO9tNR*{fFqvI!(GV(!&z;-QL6S
zO6kfvO}es9ldi1u{~x-tPLr-IrH9=jU0L3sE6Z!TvWb7h>ykZ?Pv4g8&EWFKOPMtv
zAa%$7z|$Spxp<M<=d7F?UadXmi;!-gRt6y6v6f1%Da&vd`&E+6tY_hgIQUHV-t`ah
zbMV^8-n-h{MhPcLf&FjBgp&8k?7d4R+eYu`Oo9E_Hk!S6y>#1X_TFV|8#QQRv-d75
zd+*BLyYRC2U!#frFTHok4#R}9e<Dd)H9trH!3b&|R)PMz2BWH*FsdHS6)!^nU4v28
zO&C?rN8%P3Rb9=fnr>tKB64ZY+3}0qU&2VYF*4lR#z=$f3!ldSln<6oP5EGj8#dX-
z$UK^_RbgYno4W8Ky(4;9VPgT?tNB`0y0Jj`S`{`Hyaj2RuT^1V0ds1;R-igP7NYrD
z6*d-}4GS9!n1w-k8Njw6+Lxquvavv6V?ls8*;t^kv4FK`zE*{e1;0m<@U<#zEYOYP
z#sZaYEGTnhfx^auE09t1wJK~ZV6Dl<0)>qQ*Td9&tqL0pjsP@S_*zxEu|W7*Rl2dD
z%#8&q-B=)ett#DEAbhO~8w*&U=4(~hSiqJg8w(UR7C5Lu^R+5$EV!Tbabtl>Hx`t+
zu|TC83(DMBps=xk^Fi~qDr_vErTJPFHWtv*e60!_3wVCX#sY<n1shnOY%EaNSg=<&
z61lNJVPgRe&DW~1v4C`{ny*!1V*xGA*Q&6wfR^TKRoGZSOY^lVY%JiQXuej3jRmy0
zvEUI@Yiuk~*jT_Q&DW~1v7i$tCVZ_58w+S?zE+iPEGTnhfx^ZDrfI%bg^dOJ%(<~Z
zVPgSn(|oN88w+S@zE*{e1&S32U#r5#0$Q4{RbgX64=l~ss<5#jhNbyhRl2c2_*xY<
z7W5%a^R+5$Ea1p$zE*{e1*}i=wJJEdIL?}{RbgWREzQ@eu(5!a=4(~hSU^kjwJK~Z
zpr!d*6*d;o(tNE78w+S@zE*{e1++9@tHQ<t_JrnZRoGZSOY^lVY%HLq`C1h=7O)33
zU#r5#0;XxcR)viPoGsi~@E?c;Qz}Nb;P5)c*x{&x!wW(-7AR~iV6yPFDr_uZIl|Yf
zu(5!dT^`3x4025;e60!_3zjmGS1WgeN+MW8Zv$vsVPnA&h!eh6g^dN9U=$o?6~0!5
zjRibu;cHdcSRe*B7AR~i5Q7^F6gC!!!Hosj7^)3!EKt~3z}t`TwPNdMowsG-YgO1-
zAjj;27;OBklTXQIFZ7{dWB6JXHWqXvQutc2^RvDcjDj<f4d=!Jg^dM_624XiCzlx9
zSb&Y8Vz`XifIm6;gs&C*MC+>%=dz$pX=115YsI$F`ss)hzE*5~t6vSH;P7_g^5=_b
z{)DepVPnB3nV;%}*qbO!um$H}^p4A)-=_J|^W<yAhQ<0%n4cR9unSS2KKIwv3GN@p
z<%o?13Sr@ERoGa-gs!3PN#l<~KsFY1PcAU5Hx_hHDe!vG8w<LJ#LycHx~Iw=D&cEA
z2}elz$;N{2X}KAQav6VVnwIdjcF(Snm1y9atFcniEb^H(=>rTunZNmL?G>^&--jHN
zx7mZSz3gY|3{H6mbNxF19^`7Eh4$tt3mEfgeq%dkh%pc6_i4opeUmZw<cAT%9>7tj
zG3MrccPr17;~4Yt{Nry;OP+KXV=l>m4Kegn*_)3*pXwG}(wDYq(sJf{YyQesuD7>x
zy|t0%nz|!%?KGZOEZ1L_;T~vj?!gkx<X>ORlnI&!Z1v>Er)kdP{x&$?CVx$iTg>A+
zHm#g?%=!&T-Gc+tv1!Hh2bsFF$8xaYV)(cXM_KmL#9TZ5Gfdqj;6k}37~_>~U4nCQ
ztoz^F^2hCVjb1i-5Pk7oY&Kc)+$-8>@ei_Cz#qqrrm0fnb_^#<jSLHmh0|iO$Qdja
zIfKO__p&S&IfKO_XR=u2#;{oA3>J%Ai^bwLT+{HrEkQ#H{R$5h=rX<;BanLE7`8l3
z9wujz>N3)3dEaQXyl*s$p4MeN6^BDtSXeJyuKm6Pf3gV&^`+i7s+*^}j6AsIeWTIx
zzR_rT-)OYFZ!}uoHySPP8;zFtjYiA+Mx$XBHN6AK!}ewy67n#HHN6AK!)Tn=laPn;
z3@p1RArGUKt^yr_Y;s=xR<Wha_;D6WdI#t-GOXzx;C*B5EnUXzk<!v-WM7<%4r6)l
z?fBteQn2sb38Pd<bs3+8CG-v;4`aBc%P7U85MJ?x8Mu9}hA!iFxEMT59wwPRO&%tB
zJ<Za}a7&kQ4vd!fjfUru-T}IdUqxLlT}B@BU-!Owi7q3H9)%&~VQl6C7$7-I=pBMx
z*qNzVQ1B-V0CgF~`&LeM8Ck~S;EIGijO|+%TulnIl-?mo$-@ppmn;ub@-Xqf1$>~l
zbQyz1=sfB&vXoVp?0e=xk^JyZ6@3a{I}wx7-$x=TW|Bc3#`GX150iYsm3WL(mr+)M
zf>f7LyfQ(m%Sfv`NOc)`Trv16u21SRiuWxbn<&Y{m^K=0oDb{QiC9pO>M}BIL9joM
zOT~hMafvP?uk1xZN*>0Xi)F`fC+HoRwj@Y(8O8e+q`HjExqEN{Zm6B0ci`zQ4^r~5
zvEDaMd4oKRQ`#U8dqv(i-?;@9B+NQ7!@k3bEF(dAAY&xNWb2UUb|l4&@I|gMJRh<2
z`5M_7l@1)4$fQWRg4=m;^aMo6lT+k_R^gb0@PX<q$&IWf*NDf5!6`-;Tp(9}DjyW2
za*b@I6Fk+8K5WSc`QnfB4f&wd9~Y#YV)VdS!M9OM%O4k{a*YPzgZSfgQ#Gd;-E6_r
z=r;P}m|z8z529Qn$Il6t^Fm7HgMw+y3Bm{7s|SNru90nC5|Ch?a*aax5Tu-9;*Sf)
z$TbEjrx-nAYlD<ijMj#Lgb$Q!6n|XsFfX#y9~V4F2FH}}A$SUp<(6DyK*EQXTw_4O
zhn8GpP+-ea!iRu_4=uUIfP@c}YvehA@PYG4{Bi6H5I)eRGf>78gb%bAq;|?FMi*R=
z$~B5VE=c7X6Mr1<S0W$8ViUp#UJ+7kANJnA5`P@)zA-&0;S}>7#)y27Ois+p+YsS9
zyiWUhA*B<U@<F~cRz8TWF*wC|e`;}x9R|bM5kL98MZVCPjNZ@hU*T+WmY~=2hYHh_
z@Q#f;+LP(B6pIjUT$Mb%RfHSD?a<hK9?tbqJ6eK+#mRR9ZW04lycYkO)FkSfFvzGT
zHHo?s776yG(sWi6$ztI<q^syBi-qWnwB&pEFcY2$$oDWDlL01`?~%5UX9Ds)tbXE;
z5#9pN1mt_z9kSR|*tR#q%qs-AJ-UTO?zS*wv8k|~$FN>(Dr_%?gNAh>vUxgA-rKXt
zrZ&l$<?Ua+oMA3Dc?Xr4M=v({35!L*#U>w%O>D0f9F3d5pDs29<WBRk*mN(_+~90<
zzK_Kw=Ijc-hpzxXWw8kQ5a+j9ESQBm=w)u<mPGr-EEc}WV&P-4iM8m(CO=`Z2pYJC
zd@MHU#&NO9PZyg4E;jioi$!oFZa)5477IUNvCxZ6e!^lAkj27J7n_3Lvy^nPDd1w0
zpDs29K69pvO~DhGZ+^;R5tJ*iu-L?wC5ugd!eXHpoBV{uBH&_^pDs29Tx{~w#irml
zxGVTrY~p-ygKw})vDiebJ6O%yvDieb7#z#m$Ff-X35$hZZ1NKpi-3zwe#&AIEW`(z
zpR!m4cVdkFl*J+-osOTfSOi55ead1H9L-X&*u+682mN>!_*iVB6=ANCvch-xhS9kX
zyDVX`(2Gre!eSA86Bm-7vRDM4U{9xuO#v61{FKEaxPkqE#U_2`Tx{~O*u>h3fzOs;
zv58hGIGf{~vRDMS(Mnk?f{(Mll*J-=A8u8C%3=}FC+eq*O~EKW%>0zaBDkNmrz{qM
z;>cpLiS^A4e#CyqViU)CG`I%8J{Fs3%?dWs!eSGx*})&!(^zbxH76i1fse%|T62R_
zXkoF5*1X_iT3BqNH9vTPV}ivdT3ZFZoGn;vVoxjxPLNAZTMGk^{es0NrY#DNWX_bu
zBKRS%6f8C|ZAmc9oGlg$-}wt-ePOZi9bSjNuvqwQ77IUNv5>_kAB#;aM;4p>mtnDJ
z$PM6SSS)0*$xm1;WU<LlSS);Dv5>_kAB#;qX<2OYvDhRA7n^)6Hi^N-CLfDUVsNp^
z$6}KhTx{|a77JNy^0C;&+p;V+`B-d{Y+P*evDox${CC+4CX0oL1NjMyg)BDt35$g<
zEEclZ<R>f^ve@J&EEWweHu*2ZVj<!{{>!jfG>+ks35$g+Hu(vQ1wM#ywl8L}5OE+s
zVX=_KCO=`Z@SQEOSjb|NpRicSVv~=>COQ3Y;q(m_i<m4Hve@LeSS*SLi$&37u_#U{
z@OsdTO~oNG^kP$Ss@$Ql*u-~(7qeItx6ESEJQtI`s97wU#CP@_-4&z!=0&(Ld)Ddj
zZs@6=V|2Ke;q^Lv35LGs_!6mA8bXBiWQTB1Hm^kkN=1Jc-Z&k;3p5|bJ*V_%c`s;w
z59OCMlVx)RSxTD8vPmY(l4i1OUWaCtG?QiXQB)IrEZPoH&F|tm4E{sj!Ce;o85}Rq
zHrs0c64zRAP5e<r6^=t@r(ErlMZTY-!g8(3FdOt`{Gas3^;WsB!l=S|mm|5{EN_cb
z#_Ax9iCvE{uX-30y*wy}qfR^v#-uL38@lROxZjm0i-Gk8OqcQ$F^ZNW#SP`2WYG?O
z+;Gr6l|_F7=NC>M&+fI<Gq_uaQ^c^ra0X+jxC#mIR{ap?J2%|kosT|~7maXnnPE$D
zAvN5gAa7Ud^@s|0Ebt&#O~Sn-+(}Zp)dGxBxI|KlD$j~`F0l8?-nzp!SmDy(bBL>`
zkKi1_*A@0edwSJ{JHS{L@CB)%y3m4f7b##+EoMEtiZSG^Ir<nY+`k&3hGBIzIy_tx
zb4rY&UwM*~S;Oto4_sEE_Q%YKe%QmXrM?LI^60^?_h1Aawd5KY4|RVAhO3S}9mY?(
zzXzjR-GRGl^t0|?!zilr(J|2@lC2EdMHoNt?!;rEqJDr%qer{zFnZOUxaUT{lmTd{
zOVFz5S7HpRnMjX*E$29-4#RLpkIO3Cuv(8ni+&?1qe{N#o)BZMI)w#1DaHbo$0UoM
z5@Vq{1ic*nR*XgJ^BB(PY3Y~6-qC9gv7%>smZBj`)K2Kp=-I+CIEBsX5cG2NoM;eU
zuI69>qu+^frFxvD{ZX3pv4AU-QE2<`MT4&i_P_u{ksXb~x;~hR5s3P1#hG(sa5Vd5
z&{iX`ZVo=h#!l90w_*?$B5!Q~Kl{W-+b+i`*b|M4kFi4;hTvk1Nxa_nS(p>_q1yP3
z+Ug88qT2Xa+n<QEeDD`MapU9c%5HraBozHc45RNX#SzY5F-YNwRnE$02RbsmBH%o1
zUceb~r4E0eQ}QD^{7w`VUM1nePH2C3rQ%+Mw#lTZ)MVaTitIR*dVweAcxynD*&8tv
z>!x~~?;J>rKcB##T=pL7M4whBRX>2J=5ZL4%9J9n(dK@rr!uq3Bby<Ltc>XJ-58e2
zs1Dm`Z)KJae~1^wY#n}rdFJSF7w(FcxjKA13a-r4;VUp5EAw@@7oA$!N{9Pd<^l;9
zE=AWbj}CFypggq^Es0ji=~-%Llo}nDT*_}ovC-j@;;JHN+!11Qt1>z+S}jIV?TxdD
z))ZJ+Sv7HMiH?+%in^KEjuN9+ZOtoatr!h;BWK*vVhpP9@B&yT#*lh~l^!F;u)2)R
zSue(@`U_{+8^xHb?&NiHtQZU6=7e#a7z@=+Xh*a`j74e()^ofVi{ama@g^~rsNZsi
zo*>3DwHq6{QH<R&pfU;H$GDR!C!sh@FZ7tpE9V0I4Oq>Iyvj}~o(@Z%Yac^EMn0!k
zVt5BhziOE#j|SdJB2IU`?8d2yqCcM|^WGB49o2UpOe1+)iR8+a>%@0{i<ExeU*!8T
zt%EP6QU@<hxjs?ye1vO1;CzdBv|V1pK?i=~C3dicbq7m$VJ)+}KZsZ-csB+p-o^IW
zE;ra0ofYq@t?uAU%(<IgV9yi-XvbOc9(IM5aecgr|5J9|VYwAew_~=mu`fGsh8;;+
zEdDP1B^}h5$}ZSo7jHpaBajiYi+s#Ae#5DBsx4Pa<7nPrPD_jjI9%r>*}lptd$}za
zt}Jg2;5#0p^5avnAhK^YhE+HeEpF5%xR=6EGtp_aetp*JGf1g50wy@}=&3d3(bKIi
zIfr+t!T^ddsv%7H+C-TXW%V$suMLV(kw;H$Qh}q=tC!b4in8SFIxTl5!k<a)aaMC*
zRyVbmS(=~aZE&IVO0$pUZ==I|qw8zi>hR4Nu-a=RT(|~T#_n;`?X2S@K7}bC4@es<
zl}AdfTj!{yIK5c6&Q(9f@$n?d)~y0m7*7_Xs1CuP#8bp5t8;OZ@sJo5bpS>ro+?JK
znuCVL)5K_~pR&^FVhpNXd0QS9V@U1C0%nLYtoCLLW{NSY=HiUw5i#bfb9l_C7z@-3
zxI4tN#8{}_%VTDXu}Gc8w#^Y^u{x8@nJdN;<?%T&PmE<&^S3N}>*_P;&B6}ogN5-P
z?oZh}T*inGlx&u|o5vg^Zx@cbg)LYqhO53t<6tqm)%`RM5u>PnLE}&{%4%O+1F^m-
zR@4Gc_roNmSG^uHAwFD;hI#^%H`X`BLG={w39-H@4yor@+8W7*Hxf4bNO``Fs*mtV
zcd|TR=Xz@nUvI@{%B#o%%UOYka(q$c37ikUp7GoK5&P)kBG0gS4?FK&`pI<*!=Ljc
z{{1}J&j-AKn*52sAmPbt@GcqO>)u8-=p)&q-<8W(zwyQQiD9cQ9`QYy%pK|!j`sax
zI3W6k@qID!>LN~xAILGT`WWvG4~Q{d&1AM8O13U_2v6=oc@^nazhh|+iBYs_r=ZD|
zxNf@xcyI?-^Hh87h=vt_r`C%5>~6mFIl*JR5lzsR8+?jZ!|qy$oZZ2ZJg#Xgt}PUU
z`#5U`^lJuhL_Aly4Kj1Y>sYVC`OXj`8fS2hOtEXM)aA|VAOz&Pg%_TFg7_EuokPkv
ziDmEy1)q+86VCc1%2>eOe%$shMvU*Q#cyL4i~Ws`Dtzc#EIZd1x&8!nd)H;~-)~>w
zmye~ML`wa&V%X|?G!`e_-iddT`VL9Aa}BP(qwaQZ6$Y`sQ*jjM<*MitNLf<g+HbE_
z_%x>5>iV1AWBO5cj1H`yn9Tmyqu=W%iQ%XnF!J@2#c<VP^jiHCF}l@FIFtHY#3-s~
zaSruU#VD&4m=pEW#Hc7zo7YblqgU}|tA2(U4Yf5UXZ=hu2Gv{)Mg1%>hSXo!g13q>
ztiFW-te-8$sN%|F{Twmos#7tK>gS5FKvBcAex4W$)lV>V_4CD8q^_dzHZc~fQ66)F
z7)#V5bZq_YVk}c6imYEK#_sByJkxiGv0TwdS%0S(`>0cR%qB5bs1LJk7m2Y_y$?6b
z`o&_bvYJ<O94@JH9Q)sfKGxHTA&mP~824r`?zHvGdftyH-#H1tg@aLCqj#b^xq&g6
zf@b$liWs)kLpbl=$;l9}LwkCs=pk08A-Q)*3|H;Jl&Q(}a|L?7cbdL_)IxM=?}*Qd
zT~?RV7?m4JMIDY|=$++ng?f6?kSoxTp#xATBc>u^82<}j$GH`Iw{}m3q2}W%?R~YJ
zsHMKeW-b)NQ77P*+PjSyu6iAfZN=!enx`?}cGYcAfb&zfY=>T+S~I{o_wF6Mjp5HB
z+&4}8<99$M-4p8WBS`Rwf0)phyigyBzL+qf>lv1$&N~4{zofYO+GTut+45j{!5ZI8
zuGCYlW({XQVPf<LrcFXT|KuvJ;B2o$Z1XEP+X<6vArj<!e5ZDf=7(|lOqf#K3Q^6~
z76x}>z}rsq{kWd`FAVvC?3|3r+~||nkOFZYLyZA<+yHv+Gw6iIV8AeX4l}7SsaSyF
zs6XTI#^fSDf-#It(J%bn>RC*r#*mi0Q0p*Qjj3`>S@rD!W14(mS5$!6)R-<Qz3K%X
zGhF0duA$z6CN;E^VGw6{0$T1nN3s1=_y#q<%H}jr#h5e}=*PqPoQGT2mY|hT1jl{1
zd6;`KGO0-zl;+_M-_`Y3PV)$*zuT!R++6LD4Bu5xUk_uAe5`h>+jz{8VieVBD7kr5
z7mq1h%?EKiXr3smEACb(|Ks?>dl<Ran<w>s5LWY#Jo-|}GL7Hb_LDLqow-$zZJzeR
z)rfg2iCK-9>3ib5?B7E2`B{iOPrsr8>uFePnfsD!U_B%5?9SYJ#JK#f9GsX8f6i*W
z{XFDw?Wl}6DRsLvvC|qpkB2YsaAzT|GdFaX<IZpxb-!L8>dZZlDrc4%734a339UFk
z=Pt*8d-En7Gjf<^*K`7LIimsYSoX6WHghgO&OyofdE}hcWFgOX^zk7>{L}1{8Sy}e
z{n&XqcX!D*XF8+q=&<==c|D>RNc7Bgj6PA9y8F2~cO~Y4y?GW2pSym|F-($+1DpLv
z)>!t*T0H?Mq7lAJ*r#^5eBGwr^t^d2>97v_E9d0g3#9NPq!dPmd^qB$x$9TqsKYvj
zcw^&H^S9?wHQOev=rK8p=iO_|1YkW!A9sXh_t|pE@(An0xJ5cv@%=4i(#KH*ZpPO2
z=#+DFmUSp(KmPUlIvFx4LndX&B;1I#@J#2HcmXnGQaM8=nX-md3W4xUhD^fSQie>*
zMSs9!`tl5!q+xToEdJLblVsOhw;_0w0+Bw6*Uy&)BGD)O_kl=Uzi0uGh}cbmNDQ}t
zNHhpU`UA@Rdq5=SX#<fyiz8b=B)0eEfJpS|w}D8^*#;u95Y+-AeH|8dy)g@e^7#lL
z672_4JK6O{AkyB5lU;8FBC(b>5b4$UN^Sv>bmO)RM0yluxGf+OYfW~&5s1W(#5NG=
zYL@w51tPJ&Vhf1GmKi{#C8(hdM5=eAzE=W7;(TZWk!ZDnNVM8OB%WWg>y1F9n^~Xi
zdLt0&y{s<<BGIr~K%@`Ca#}znT5b!7M60_6M50w}0g*T;Z6FdY0+EK0=S4syMzw)R
zJLB`T1w^7@y$leEX>JRMq|ZDBBC)nM5Q$bBh_oAyE4P41v??ti(q6E7TR<ebr5i5;
zL^>F0LoFZ@M|QXcL}GnyAQH#94Md{V1|rdF1CeO8fk?F4KqOjiAQG)M5Q$bBh{T>~
z1CeO8fk?F4KqU6y;ua8zX>A}9XUj5-6dgdmbAyZ;uS4Hq9|2W~=_9+|2t;CX3y8#W
zT0kUbc6r<f5Rhv++4bfFh;$(nd9{8nO~k4%cfApabT#5yK&1O%_zttSfJi*)77$5{
z6o@273Pchk1tN)&0+D$8X#tVA%F+TNNwyS-^Z-&^_5zi2QaPO#5NUTrwtz?{vFVO%
z*W<1?0+ATi0wRf#0+DFA{J9x_(lceN1w{H76IsxGX=1YLjX<P35Z3}CJqg2ic)M`<
z(}_i|w3{iXLm<*~%+FnK1S0h#gYSHV`S~+1&5xevt~UaaCLyi`M3U40JW4t!&G}dO
z9hrl2Is_syp=$_0r0WonU2gy)F$`P`egH(`_0R$$(P#mYI9C!N(rq|GTAu8B0}$zr
zh;kYK!!&KYl>(6nz5Hi^NSu^g1R^cOy54^?5a}vZA*a~}B3*(gS*R^13$@3g+nli4
zML4`7C@HK}8D`_Yfd2#~g?$x9X;4zwEN_jaF99Wm6T5!QyaGxJ2gT5!q|gK<g(fH|
z90N)UhjPDS(E>_}2Hg``G(ky`2}+7gP*OA&loW06&cZsNymUm1%M5E!Qe=XXA`_Gp
znV_V|1SLf#C@ESR+=L}g4N8hkP*P-qk|Gn76q%r;X#Z*t7TPo@DOwZ9FbGQGNor71
z`~#O&2q-E3VGqN4Wj21W>tZa^YEV-AQ1=ZmG$<+lN%w!k(4eIFXWhSmp+QOUBa%&n
zlH#9tTUZLzprrWG?g)kkCB-HvDK<e#u?b3wO;A#7f|6nrloXqwq}T){#U>~zHbF`8
zGd(-N{iH!j@w0^^aS9rg6q}%=*aRiTCMYQeDCu1|Aq`530ZN(<OM{Z&Ni;x7@fc82
zY=Dxs!bH)aqzXVu947%KRRBtoVGvMKWeg~(G6s}X83RhH0F-nk9d#JrTQQ8jvjaw1
zKuOVwRnAHQB}E1(DKbDwkpW7IOi)s_;=Ubi6Hrps1SM4sP*SxwVkXvoG5-6`zO?xB
zANZ47KmtmtPO82aQ36V;8la@=%qou*P*Qb7hY3omj_NQ$N!3|8Oi)sFwhj}NRGp*4
z1SM7H>hSHD$kll|Oi)sFz77+VRNYF42}-Iikgx_N#fP}7P@aI2692mfCBgr${S<FT
zvGBih(OiR)692mfB_;lM4N8LlorP&o68!HxMuU=K6O<I2prqIYCB-HvDK<e#u?b3w
zO;A#7f|6nrloXqwq}T){#U>~zHbF`87C=eyNtHL@v@pGJ1-ZO(&cR;-N{UY@o(xNT
zX50`eBcFhhcn3)VLrfDdH}517r~4RC(#>fy?=6wsQGMtBG?KR!4N8*h#CIM?N<Z%}
zV?arHL`WUHH0An4qh}$kK}i*Wl6VOVD5)|AlvDvI>3vAjprpzeP*P<KD5)|AlvDvI
ziIoux(2M^9N{RtWVmk$t6sMph7XKCeB^@N7q!^&28xbd<r1*Hd$j6+3l428-6q}%=
z7@#D{Mo?0mfRbA1qmzJB*&_Og2`%&yTh~G#^`V@941M%AlqIJD^ic`n%Tl|IK4O-C
z4t-Q<y1%U9B#1t$nCPR5i9V{B=%b2>KB}1Lql$?>s+j1biitj|nCPR5i9V{B=%b2>
zKB}1Lql$?>s+j1biitj|nCPR5i9V{B=%dOQ^igH&>iy_VjXtXE;ob>sj-Zb!Ci<vi
zqK_&j`lw=}k18hmsA8gzDkl1<Vxo^KCi<viqK_&j`lw=}k18hmsA8gzDrd?&M}j`8
zTvYiE&c}D2!<Y;DsB&?UXDH~Sih(|=e9n`2qK_({4|oX(`l#{+32V4d1#q7e@JJN6
zPX%xv8XE3X83XsJjDh=90QcF1oEq*^83XsJ7;v95^2iN_nIm2}DQ@5tL<roc0=N$=
zb$MI35dpbS61Y#rg!|mXGWdhD{~rFe;XW0>eI7#$u*UcmxK9OeA4U~UJqLH2dXKvl
zxD569-T;II{$2=Usp(u8WkG;B>WZ^rg!-xFZ2(%m9%)>KfZFS^z`=@EKM$2H1*nWg
zx_?3?M<F21cC6-esIT51?~kbFrRTv@J5kUUL&3EOZ}69(=FZ%o;m01zG3HIO3%@gG
zebaHLvK-sCi}0O4(&<jS{2G{Dwz%dya}IJ$zl%|Cu*IW&`P*~udr+LcIS2pl@FQ=R
zq+mNl!3#VCzUO^XpYR52`tNz<JlkgSh6_N~AztePcqDrTNoAfJjvTJDVe{;1x}>$k
z>?qjtwY{1pZ`Ce&=J!}~!M2CqmeOxrj8d7)Z{?bH_q&m)nA+>Dk;i$|*)~1U8|5Ud
zZusRL>x&<3d8rqo9ry;d7F?KfFUS95UdX)E8GlAs#-9P2hVgT7L1g?HSjEctGw_YJ
zEaT5e9>E!ZM#i6^`Rp_P49m&*Gcx`R!)<*lJZAr8xApUQ=(gR~;!MR02};iRGum!z
zvU;}M)-+zuZOyc{+nTHm-9hTMz86;8ZB47~wqA+j+HPxFZMQXd*0<f(Yhk^d+xl3f
zwcXYn*|yu7^|jsB9Ot&%npWFwO{?v;rqy;^(`vh|X|>(fwAyZKT5Y#Ad!p^Orqy;^
z(`vh|*@JDjHPhN|YjW7oZJqIFpj$HjjEp}c<Ik`%{)~)2<9`Bw#sVzIX8ak#!*M&_
zpECXoaY$tR8F0XG*B;*L{!j2{XjgT0f_oaAn&PUinnW4ZM!*E^s;-(u8C8=gqiPam
zRJAi$6J=D#5M{g*Wu>m_7~#uPJ8@N4r}i?7xT>oLQAX7u%BUJd8PyjNWjv9(sxzXD
zaeyOiU40O}*&@pLM(V2mUqX~|zqqRZn7XP#l)*FH5>bZ4{~e-?kHOXYZ$*@$@Puv=
zWzcwKL>ZHi^Y0O5@La`n&dg(oGI|ivBFbQ;LX@!t0n>9nhA3kd%is_0nMdMZ+jCB$
zjFS-q7&m@fL>Y|IL>aY3?(;B&D5GW)Wz<ZfjG9T5Q8S4$Y9>)eZKq-t=cS1<YGa8q
zYHxP;!4793%BYz{88wqAqh=Ci)J&p`nn{#VGl?>4CQ(MsB+96nL>V=cD5GW)Wz<Zf
zjG9T5Q8S4$Y9>)e%_PdGnM4^ilPIHR5@pm(qKukJlu<K@GHNDKM$IJ3sF_3=wJ}5)
zwM(iT$NmlIV?CW1!nnT!u|kwlyR7GIMETAt{A!|%`b5`nU`$AqQJ)kstcfz}CQ(M+
zB+96pL>YCHD5Gu?Wz<J}PHat-Q8$S)>a+X?>LF3a1!#y6WiWz786o~_qKx|1?rIo9
zlu<W{GU_H#M%^UJsE;AasBc##Iff8r)OYCRsR>a=eeYlc!z9Y+HHk9%>h3p@AVe8`
zCQ(M;gsul!k`QI|jUmcld<uBs!2<ew8UeXd6QYd1iP2A)<~30|{v?e=8Sg=?5M}gD
zuKk5Mh_4)N=MbWdzA429qJ$`8f<crq!63@$H;FR(2i&J{fDmQ$4+actqKy7Y#oxiu
zL>c`iQAWQ>l+kYzW%N&#V>D4lze$wQKV4EZQAWQ>l+oWN%2<i|d}ld+g(#zcewED;
zqKtlnD5Kvb%4i(so($RwA<Af&L>Uc}D5GH#Wi(8pjD|^+(HKLN(MX6g8YrJ+90^fI
z<D|ZGVF^)2Llb2*SG^PHl|2PJ)O-WOZ;<e`S%l7v*!BuQR!&CG+M9okL#GQb#E2dA
z*hJWDu!ft=w^kEVAgd;(m;oAxbwX=FMhdG7WA0dUKHS2??3dtSzMtS>K4InlkFhos
zob}VuDP)xIG#KSO6Gr*R3Wz^QnAwC~zEiWyd(Lj`cRT+DTtGg<qE4LGx->=6rOA)D
zUqph)spMw`3|l?WrOD401q`iDoS&@@K)lwa$<Hp+(7H7F*>xJl9_Z5K=cupZ@UrDO
zN8rD^KYs4VpIq3;Bf2#Ct=#=OP@j#T{MO@nu-2u?ze)_POOt=K7+RMmzfcUVOOxM5
z46RF(-&PE*OOt<%7+RMmzeo(NOOxMDjD}Uxx-|Kv?g!ZhLXGpU>ta~z(&U$or*T?9
zU7Gx^T|5I&uIz-zKz<LgQeB$skWJ33-zsTcn*0Io(=3$A6!`;73~ODQys1l*KY0A}
zNYT19`9mhKFV01Wu{@Www){&9_8bpJxhT3c`QzQKV2LhG{!Kj$Yh9ZB30n3Bg$yIE
z$jz*)^FMRX!(8csE=~TCl4S0IE=~UDdQf|yOOyYFgtabB-o(}99}|#`*F#;J{4aZa
z)TMQ4^1qT}v@T8lw_Uufdqtf%|4iSXFv%Kf)?0A;&-G2iE_TiSkbl0gD~us^{2563
z!}!%OhI^<>lmD|6JqiQOd_kJI00!Eb=+cC{urqDDXB`e&6jGNa4_%tKz<O;&U7CES
zEoCeYsY{c0ZE4@Kkh(PaRF@{CE=|7ME`1bTvOJ_NO}=P%i!Mz_U7CE!_WpprTM<&1
zCg0Mfi8(uYP(^-tww0avBeT|XZa|XHr0R;<I9(_IP>0K22&qex|FPDP0lzCgc=FJt
zc>v9JLh91MD${a9>e9fPK&v~XE=~RynmDHzQkNzVT^ce>mP6{&<WpUmkh(N^=+Zoi
zw7DU5Y4X3(^(_dgOOuB#jRn`o!jQT&`KLSN%3c&wmnQ#=&bc^j@Hptw@Ty-DQkN$G
zTt_*N<CcZgrO7|9bM78emnIKg8lL|0kh(Pa-rTrPqxOAjod5YoF5r}3V%OHO`ev@g
zDZR|D9mXRk<+@4G`CvzFE-RUqD_(}vdAOr?FM2pXoa-WkF4!MDhtpR2y&oBjeit+8
z_cx#sJ|jHG#&3K+3gH|xvNI|jrcvhMp`3c{JUDteB7~-sGfJ+y1VwXUYU93oHTHnz
z_qA)=;4-Lt7}@UpLALu{<Ot<jKiKY}VTA!t?GQZ$oscRtd8p9HIHN9}u;;Mg`c;?$
zUj8K8tzu?`RH4bAY?o+Q;kVIi`BSu&52-?ve~Vpu6_UCwm;a_BThi3tyYnw}jN2B2
z5K@IEpQ_M=RH4a3g@&W$gv&XSP@!Q)H=M?tP@&<Sc`&33O+J_N**!}_s?g+96`GLy
z>hhhr+QVq`@{lSt`Ml<3SQS!*CO=MFYr{1>&ehh2kSa8JsL<?+`c4k1LX(FI&4IAa
z3aLVqPgQ6_s?g-S6RwAFU)ER9*2hAs(BwUBT^|-$L#jd(QiUd8)M>YeRH4bYRcQE}
zW7X10P@$pC%Eg8X4efQQ9Ya1QALYiq8xbK@X!6xuorV=sg(hFiRXzf1qa}A=2Bnxp
zg@*G#vHPCN|EVL#OLYQo2KiD>aik_Z#HQABiZ$xGf0Z6ovHGt>q~|cE!K+m!CnBCh
zgy-<8Z1A#4Co;84Jf|DKF6Yr41f=#3Ag*EOugS%{8#Uia<Jw%`wJ-+A20u=-!4HrP
zeq6!^&$)4YT7qp2kPUv^H8C$&=P|r&xI^^-S)3;sKD2T=;s?l6KfdU5ld$KofPsfG
zE5`rXlQ4Pe$7?^^0D0=iYo7W6^3;#lJoN+D;e^L)p8A1@aBSDna;!t`8)azUD6M_d
zr1njBs(mvF=QR=2X(Gfw@Na<HH-!m<j2fW!O~KH<@shV~-qD3&!Z#Qud@Xh3AHYQF
zD*JnAX&w)!;A^Ry!4r|V1%?UVkh&>u+xto6DvH!iagqB27_!;3xShwaW|$~$FNT9Y
z`v@XMSGi};B3mZ9%02s6moZGKo1TM8%v1k4ZVIC%NZlNcyJ<+Nn-ZjM*j_87)J-Xs
zx(Uk|h7zQ1)*;OeDRonV)D3fXg;csILF$HusF2gA1gV=h!2-hsvoM%UA+gU+?Sx^X
z1cr$m;)G$M1cnLLQojK)!zD=F5d0ES>ZSy#8{IfEOq5cooA5trLF(pWWOTzDF@7aT
z-LTe#VWI?viOXTur=yf|2~szE<FX6MFi}dSZbC}klv1gikWx3LRO%-5nKPBT2`P0`
zg47M`D~6Q1DM9LnElU_CN|3sFmi0Y_GUt{cb@Nr$M}~<~Ds>Z5>ZX)R-Gslvt)~R3
z8_owe<bLZCq;6<+hm^W0LF$H9F{IQ@2~syazl33;1cr%KsG%+l6D2TA?0`%m874}Q
zx}jl(l)5QF>gIK@obXOWl^}IP%MB@YQ-ahDt?rOgHzi2j&?<&UvlK|(a8Sx&KdLD~
z>V{T?x%OSyUR&y>1gRTF)wjp(d2I<&H_ze3LQ36~Aaz5-3Mq9{N~LZ>O5Kzob;C3_
zq|{9bQaAd{3Dqe<>V~xyLrUG0Aaz5l6jJJ@1gV=p;fQj08!brP(5i%#x+y{G#>P4K
zhLpM~LF#54tVT$wn^G!u6H@A?1gV<>(uP7x-IO48!;u{h6-O3QH>_`FNU56=q;5FQ
zqamekN|3stH7lglO$kyrv}T8tx+#IDkk*`#Qa2??-O!pFQtGAzsT*4JLQ36~Aaz4)
ze)s~%1X4G&whAeAQ-ahDdtyO&f?RUiS{Qol7f9VOZBck6b3*EdJ-9fe)J+LeH%wa+
zQtGAzsT<CgWf-aVBGz*b#JPA5uS2}tptYXE3qlwsN?@2^a?`<cssyPUmeah0Cl9F`
zW_EepQUv6heznz<8vqz4Ud2RStw*GZfz>3#L<tNNd*greCp=$B-JA}?bC|Wcl0yZl
z8=iFYF7`j9Zp0wNL<v$iVvu2?1gRS_$S_fY)QuQqm?%N&hPR*Q&OCWY-R!~Ae#HKS
z)Qw~#!$b*EHx!t5*$V}<Wzs5S`76i)=m#x9>gLaE<+qVqg4E3v<nSCav^U8xQ3AsR
zqnbW5L+VBhGECq*ObnMXtMDg11A@>a*!z&WS&lfD1)ZKIc3MqJ-ITyELE?p`+zlXg
za~TZJ;qAiZ&nMIT=w>oZl)y0YA?7E;L<tNNyi<729%!D+A9k=*j-DsOL<tNN|H=H+
zR4GB~MoxbX4pxYeoPV|aKQRXxCQ4wKU_#eWFlqe$2nfSOFuB06W|#=36nH&ohKXQE
z49zeROqDwn7$*4gb5vS>!Y~m`%k?43W&Am5TB55Q%&wh)r~yjdl#lMJ;_v}V-QX@G
zVM^VUkI`Z3nv~b;Fr{wF$Co%Mo0PigPNZ&%$Dy_4bof0=O*tJHW?wys|C2SR1EY%P
zU5-M)>998{OgSA$)ZXHBpz#lLI=CpUm~uM2heaox4m=@Cgl53$Ktl`7v^X7#A~XX|
zhuv_OOgSAGZgD!u`?d(pyqMF0DOzY|i<}NUlz{=K!*}s)YjHaK6|+hU&HQ~%haL*e
zfYV_FW6<Jsm<MAN{mPS^B0@9ZbYK-Jrvt++PKQt8KGx!NxCcgy)8R=NElvjqx84?~
z1GBX_9VQ^9#py5?#w*}-;5llcnHO_9FhvW^fYX777McO40}U-S15O7TT4)BG4m7mT
zOv>rdL!lXPIvk3-Pm9yxT(tU?ayo<*njxpd4LG4|LJG~0(_v>=*M}6EA*TZ;%Z(w0
zX2|KV4Xm3(3eAwyfoZp55cWdex(LmX(}Cj@QfP*p4l)cOg=Wa<zyq9+LNnxapw$^t
zXoj2)d_v~Kzu<O4PKOuZQ*=@E0~kinITS~voDQ6o10A?aC7cce6q-pm9R?^glW;l=
zP-rIMbSR3@3^*OGM%z+O2hLk9Gy_fto|x0KW|aj_2WDd3pTvL9Ie`{`xYu0nU7j^S
zp&4*GkePabLNf`c!vKY5!0Esv2PiZHP6r7moDLFBI2|OMa5_jh;dGF2!s#I4+tEyL
zI!HL-bdYeu=^){R(}Cfl2+e@g;S5ZLl+%Hy*Wz^0m-3qt15O8~v^X7Tv^X7Tv^X7D
zSc}tvDJ@P18d_)uoDMX!&<r>oXlS7sa5~V?LNnlWprM6k!0A9k3(bJjfrb{E0jC2E
zEi?m82O1hE15O7TT4)BG4m7mT3^*NVXrUQ!I?&KUGvIWfu{#D-CLx7p!0GTVoED}R
zCacRU=Og%=Xbn(k2AmG>gC$RuFCri#pVNyiyfvgBu1u2^7~V-La+72KYRz2Fq5O;_
z^WIXCJ1V|`(@43kJcD^62cjii$kpKer6MbG$)eC8BBT&rnic*a>u&g07oiz)I`9$>
zDKyjKbO<RlLr#aA5$lBS#_L*((;=kLOpDVYq|gjG9oRF)kU}%$bYMMP@O~Bk4^e1_
zoDMv}CWU5NoDMAhr}#@cs7aw2ayonmaZSE`kkf&Wxh5I5Qci~^g=SJthbGq+$mt;2
zOiqWQh_QeUVSC^WQaS_<q!wcV9Rdw4#sWG78d{76bO<!G7z^kSXlOAO&>_&!Vl1FT
zprOTBK!-p>i?M(Xfrb`i0UZJjEye;m1R7e51#}2Bv=|HM5NK#I7SJKk&|)m0L!hC>
zSU`tBLyNJ14uQrZ5n}-z0u3$30y+d5T8ssB2sD;i0~BKc9l|IuCPfir0UbhriZKBl
z0<&o`mVX5u0!!0kEPs;@f!VYe3+NDNXfc+*PlwP$0(H<Ka9*|P5T@gNJZD#o`2fXO
zK!?CH9H1CWLWeML3&WrDBtD@-;OrTo7z^kS7_N)@3F#2-!O<brPe_MA!wRW>LOKLK
zSDldRC!|B5<%U#0Asxc6kh43a`bmopA*A{V=@59W@ai}kdF0w;=E|#a1C~n{Dc?gx
z^9)|xphIA#F0ZHp7VPCx!MifmPe_NrvZRcuNUZP&hmYW2k?JRB)wXw!@57jqORu&#
zl5}+%PO!E^xEcO*M|I(GSlcoFC=6E}fe+8x>*RH*TYU*d*LIO1DXNR`bgJztv<GE%
zCN9m|Zemo_>(QIF-Nooty*S0%9)&q*MnlDTqSjt7#(?@TjXlK}R7+?qFYvW{vf2%q
zYkP??Mg0W*SKBWt)7P(VVA1>a(^#Uu%(m@cn1y3jt4$c%+G;tUwd(sUV2v2-)lV@v
zwIjvYpq@sb){c^*H>!8wR$W^w#+%gz%yzUGC#sLK57yQAVtBH8jHPXmTm5NPlkzd-
zlQ;vt=s7iXY;zXJ1$+{WYTkp%SKrAFcqcAi{UJ={-nu&pga^{)y?p`0kh(l-gVj5s
zz%h0d1=4%_Me@&8YEKxAf_@WjHefWxfOG@Ktam`NmDPnf?cRw}T1DNC_Vx~n(W`dC
zX!cH${%@d(A4aQ+N1@dV``+OGnGLxNz1X);VLP<LQpeHQR}4p8iZ9T<{lsw9p}4R2
z?Jq{Rx*Y@5w;~z)?NMFd0b-QZRVcbo-zqBVO=wl$L6Xv|_QL@6trVl7u0yN(4i;lj
zeTelOBF2!qkM$fX#;}@#Vdz_xC@md~XJ_AGk}_9KqoLn17FYxCVtZCsr{jDEHlfQW
z>{gN<|0t?y)aG?viYcPLi4&}CB{Kxy9-J-<#BkJq;E>wZVz_Dw8c=(c7~QIiQ~A|m
z6xFt9XKkSvWwjZjRNJP+@vErq@W`ocE3>y(&11ILh%v$Hf9qwO8EioR0h<~8FoIK$
zJLZj6ZKFJurfs|#X%7f*N9wD$H&6c*V(qO&v!r9ws^LSAUInvu0M4Of)5;k$sh4SQ
z-OW*hXv56%J7K=6`|X%!P?E5$od+<JtZT1qp#iSF7HhP~yzw15_j&Z)_j3Q&&;a7a
z@6=xWf_U*Wc8rW21K)|J7r!&{;(PSscmA^HtGF3xFMg-##qTt|_?^%6-GRG__TqOw
z*Y_-pOv8b9Dl4EDzY|`3sx~+Qz4)*)4F`JhtM{UVI^o67G#o6i6Mp@lVUA=P4vAks
z({RW%9Po)~c-XtOhkfF=_>Si|)$Q@mbq>W#o%2?_XLlPO_QJNknT7*B>^?l~<YTvj
zOvAx0WEu{b5%92Q8V*Nd8O4W(J=1W=G#v0wo~#;X8V>&dI}L}zad=EQ<!aYAu>>bR
z{&KC#Fs@XGE1lGBDECzurF9$1&GHPaZ;6k;JhAIu<`vzB@}L;n$6q#e8_K3`LwSsD
zLwP7iOoi5M2nXGDESf(4(9~@RP2GlYtZqZNy*ml3QnIocE-o{yef*)R+Yp+%4WX&q
z5SqFTp{d&tE)718B|7cn4^7>M(9~@RP2Gmj)NKg&uXbW>Rr~nEHL-$0-3Fed)@_J>
z;Iazw@kc-GVOYC!qX)al$F6<+(L>!=!O%Yb=qKHGz|cPa=x5yzz|cPa=n=`Lef-hS
zyPrjh_VGuLcGD53ef*KB+Yp($4Uwta5Sh9Sk*V7dnYs;;soM~lx($)3+Yp($4bd|_
zTjMoJ`}m`03kRa1+Q%Q6x($)3+wc-HjB{~9TDKvBkG~(5)@_K!=r%-SbQ>Z=w_!Ra
ziq>t2;p68xiEcv-AHNKP=r+V-bQ|I^x()Fd-G&%G{zI@3Pcn?_F^s-LGHdbihbLA!
zD@C^<G;|w6L$@I`bQ?lbx1myTPe<Ft$6qmZ8!CowL!~!jCf0op{`<}@wD|LW{K<Vb
z(QT+qs#4)WbQ>y$ZbM~el}CzhLuEvV>Eo}A>M(u$m03DWAAe=G4%5e9nWMw>@mJ>R
z@a>q$Aj6O{>Eo}=*J1kjD_iL>ef*UL64ts6(IM_WC{KL+k!CK}KK{tmZHP?WhDbA)
zYaf54naj10KUz~@VcN$ZnYs;;soM~lx($)3+Yp($4Uwta5Sh9Sk*V7dnYs;;soM~l
zx($)3+Yp($4Uwta5N$!XAv&o-u?9>pTtP0coRjdE=r%;B6xYL&Eu5DkAS0jXHt-IT
z>NYS<Hg5Ay5^=hZ(QUXUP3FBNk~^yJd?StIZAI%g$aUg74<n+V_m?rc4S!7Y^U{>-
z6OEpPu-0ve;p68eEV>Qx7~O^#KK=`lq;(tOF}e-$7~O_=jBY~=A3rOjZbK3OMYkb>
zkDu)n-G(UDZD8^A^Cul7x(yM0{2xP{=r%;~@$)e!x($)3+Yp^*i+iL&AAbZNzhtA2
zKf2r&;q-#|_~WKqNqzhoj|3KE!6T7}kH5tuL2&?)Joq2WBf)u<`1s?CDmFagzB7ok
z63GMbNQnFaef+T@c@TfjllX*3g0n{?58^Kb3{PHz_pSI|mjVj^Ry-2(@NjGKNYHp?
zJQBMh=ilRz;JM1}h?%1vUP?p@p*LTRh!&3oD|LB+AB#Zx@j%GI7#@iWSq6V__`C3L
zERV!hi1D3M@!R5&U{qn%WRzW<<GOHEtLHWmpjNmA9u-U7`+gYn#jw?Hn6g!2CoYD0
z>(>BXw?GU>-OrS*#mFbL6xBuU8(CZze6dxNmZECXQdCV^imFLVQ8j5Psyh{5i*C}i
z6x9|j#VK&G4p#ScA7Di{UVw`BO4|Kxq*ULKwEH<4d+T<qOKI$rwEG1b`|5Uk8!-8*
z`y~~1d;%%^7b@uBUaK(fW2|VcJD<+`M|se?q@pKi9FtUZAC2`%MHkU{V_{G9mZLsK
z<JhF^kYyj2mi=kG@2{@D*}a7R@));@s>!WUHMupaCbve_<kqN~+!|GrTcc`nYgA2c
zjjGA5Q8l?WswTHa)#TQwn%o*ylUt)|a%)sgZjGwRtx+|(HL51JM%CojsG8gwRg+tz
zYI18-O>T{<$*oZx!>v)hq{^Y|zX5%$FENI2EpWyQw?_4{p06Ov7pTAx$HJZrm5=X2
z<zwh(T2tN5oC|>u;duBRV&od^w5EO?Lu(&wd%r+jXKvA5jyvs3jGEkG_g<cJm!lqg
z^J^O97+_?PS2!33rmtTm_C&S>njY4)jXdhxc7FK%Irk~NP1>8k$fGbT5j%llpb&-+
zf1Bi*!t1kR(~22L{ZCuzLf6mOu+g%=V+UWA%&TXt=fU^dMSbvEDt>&|b`P+4=&GqM
z=AnI`7JBR0bOKJE7n$$yx}CO}t$DL;FMnUo{l2tjT@zn(>u@ZhLr!aABo^b2Z=Yy)
zYkQ@%_N27J6~jMbDJR>4nCaNG&vatD?NjV7zJhdYve^1l)7Ed80l39!cBDIGt#173
zX;~tdaz-jovf7$?K8s!?1PugOJP0_7y?N1qWsRWFMM*a=9$kCbI?LWZX~3#k(*D<`
z%^j5vTAcLH>QT@;>=3XF^z5uposSZC3|=L@wco7g&V#vAV(v3~EE>CWw4>x*HY$U;
zG->+ov(9AOmW|hAbj&EaeV3%ym(N~uY0mu$%ABztU18Z(JyuKD@wdqRnRhemwu!iH
zSf_oo1t#gmU=d8R9&_q>OrgV71}4eCBpH|lH{A?Og8RaXfZKF4sTI7iWl}3Zb;#>U
zCbg1Dtz=Rwu0hw}YPyC7=^DnTbPZ49UHSyP&<<GfTKsF0uAytfAfuY3Yv?lQ8kDAM
znD{Ov3SC3DLD$f&=^A3<AB3(U1Cv-TJL3U7o8*p^&^7p=YuKC5tNq{`@Ilu=X^EQ9
zHTa-wcs1bMK?WwV3j`h&1JX74plis$B<P0>OkyajWMGmEOp<{~@cGju<5Q`afk`qj
z36^*>Fp2d)8%#0<YoHmJL;xhW<L;J$N&b73RWdLM{nI3j_%{WU9EzqjpsaEXuoGKU
zR$)R*S%r{<Zgt5y@SzSA=n^ZcA-op6Qe~A>QC8yBa|zaXM{2i~RhZ?UR#tfkzA|CG
z$Ph7{aa&ivf!=H(Vm=Gs<Nqc^%$?#({UydcMa1w7x1_8h@qY&qb17Vd|5k{YKcYb`
zL=25rhKMQS!T$FUF+5j6#4z(1M2v-q79xg~3L<7J#L9IWSdEt;V)kSi{DFUUU;G=3
zh&c)|zOxv=Ekq2XTFNSq!uXddtGH~iir~n7sj|vWKmlaRDxi0|i|h|3`r}`stio~Z
zKNNkerxQaM_qQN6RaQA3QNFV$eus`<1K<8Y&no2U%x(CF<4)zB+a3fSWZ};{-Klru
zI<}{Db>_N(2bubPT0^ilBImTZ7+w27kiFySv+&b7cNkDEd$ZNh@Q(vK1C7*JJG>4k
zg_WHtaAR0t3I}&4D1i;uw6j>yjgC#E#QIO=+`FZqBT>+db!ZrpdNk%@^^DK!tW72o
zlL5HFO^&dS0B15xN*?<&PC-L1)(;=M0ro9Ufp;CySn#B=$T;&gEaWuDzWe%|d!^t#
z?n@ednv;MjRu2nY;tZ$AB$j<BiaOINKZ*P(YD6FsXE_N*V*Q99D9&=K8bWa_s^TRu
z?MPO&mt(WuAy&up**pdC5`AiWIe|X4wIh#Qgrt3(1h27vWZZSI_jO!-GU%pvv8>N_
z2n=NHbvgG|DeGXAMYzppJHiARqnmzfN7{62+P*w;afhgRJb!i0-GGIDdvg_lju}H(
znMP7fN^4+lSkmH-L0!^{8S`(D)KLPgfoaht@0gandU(TzwE&8AD1Gz^BcEYKOFAmt
z0D<8dIh6L!Y5JQ+DsP9qv_k;f00NCX#Prvt>Bn$5m!;M^YuYE6{FE(c{Mdiw+@cKD
znXPvJ)-LFpSF_zu+wvmBX(5C6tey10dfm?FTJRs;&fnRxQG*j>bSKvIC8_AUAI`aD
zJhbi2+W?p{3k83vru$>}*>^G9SCS!GK6`}boyo*rJ+x-s(U$#Hfk30sA)L(D5-`q&
zA!*TFNrP6+{t%D+M$&JG&i>slFz;3)G6?HuZ(!;-lXCZ&{TR(}B}J{6^Cg<w+xD$j
z<y>p-cW7<0mwYJalK;%!d`;5oP3iSFi}*!*Q$H_qu(!;UA>TAz_uQ&^CrJTY3)FGb
zO5M<l)44NSM)X}tN3FN!U%=eENJkN#^L?3v)-jlbj&(b@i5+{&GCcN1F?k8$S$$K^
zT?_)B>0t)p$sjx#geQaWB&seMgr^g#E_{X0AUqj_2YVy~>bztSo(#g1L3lu8cu?sN
zco(jT;))N&mCxccC7|Mp55*OtY^;EaD}JiD5>Ro)hvEvsHEuw~6(5Q#%-I!CaKVS-
z3JXyI6<2&Ht`K1Y#T8~@P*zm{BBY%`c-X<zSnyNDm4J#XJ``67({TgpDELrZq17Ew
zam9z?N(SLUKR|JXldu#}aV3NBfFU|K(m_vTd@#7nWDuSV!h?Hj2I0y0VCcck_+T<V
z7@?AAQu8I_gMr&1<AXsTWPC6HO=Ns9=!7YP2Gg1^@sJo=^Cg}thSq$Er-`98U*hRv
zXw8>+SPZTC63-ArYre!Y#n75B@rW2&^Ccb?Lu<aov&7JvFY#<K7K!FdJVy+z`4Z0+
zLu<ao^Tb$YHL3ZM@xe5y`I7O$1eBnOAwfgeBgvco4ftR_bS>#l7P$i{`sKfiz$N8A
zIfJ|^8TW}szx?aDPdJYKA3z^#^b13nXk?p6xlgV~l<!=K-@?IImuS=`x?2MZqo&~H
zqc$mG*isK+hSnx0)H&+_JE%?3)H&)jB-e(-aMd16nOY!(qg!2p^`6=^F^Xy-oZht&
zpF~Gxbvcbu(V3~J!?8A5o8>P>J-ukiO=!r_0VtFaQxWkR{4abRdj*TNt=)@YsQFlW
zgGvn10ham}o4HU7N1cGpgSBnMaMkN*Y%4~$)jW;)wyW-r0-T?+Wjplp)S3a#xwd!k
z0fyI~2l=35ifn%KQij+2tYlh~(34J$G;wbOYDMrOm4-%|bawQl$R0s8jO!>e33!g-
z!;U@HvfYj@o)17XI2+Qe%=kS)1HTpc$*s5K++_f&+M92~F*AX#_-#Ewn~Z4GMpD>@
zk#!&qc`kv!tRG#%HvKNa+Z;aYgg3zanr%Pw`J6lZat!)=P~5N}FdVx|@+jgu=G=^w
zxq{l5YnL?AX64*Y7B$cIG_qzj8n`=SRtTzrh=t{HzH0$$U;|h93H(Dh@W7;jt4Bi~
zbx_izLv#yQCgy&lHKrb%qBceZ^>j#Lt{UxT>Y=fQ3+*%dG<#@OfmL>FT0R2k$YG^n
z>BQqkr!ni{30#UGCN{@<EzZob-g|8ea<LNGd?Z}+B|w8PFIV?wkc$j*kwGpp$VCRZ
zfP4M>cm`*X3;6E%SXq)mE;7hPuo~|Xoz+|hxyT?F8RWt)UXAak;I)J@++qj9OB?*2
zlr5jtmJ=KgkB$F1ZMlKZoVRMLJ9q+18~*3*;88evi$NLRAO07#I8X_!Z7A9QvYlJP
zFSMsn=3M_LcCn5pQm_kM<39y*9r%?Da?v4tz)k=lx#jPx1!Uad20~Bv>xeYiWCLL-
z`)iOzG4Rpf8RP;RZ~~A0@;2Q|8RP<e@o-0-h_4KCkwGqSZ~ZrbTsU}QxaC3jQT!L}
zo3g2WQ#Q44%44-}%G<ji0B5{t-;@`Z8P?i2WmEg6Y--<>P3@bqseMy6wQtHxgNb;o
zY3-Y`seMy6wQtI%_D$K;zA5iteG3ZE+BfAj@mVmaeZ!NSL=NQJ!ymY;La+|u4|^Ea
zGAE&_eG{76H=(J06PnsLp{acnn%Xy^seKcg+Bc!8eG{76H=(J06PnsLp{acnn%Xy^
zseKcg+Bc!8eG{76H=(J06PnsLp{acn{!z9vek|z00EeONx3zD=G1@ob810*IjP^}v
zXy06ka<ukM1nnD+lW5;W(7usj5bc|2jP^}5M*AijqkR)W`{rIO=#s8vDhkueQKEfQ
zKC#MKDcUz>L;I#|Xy23#?VEC<eRCWpgA-S~e!>~@b1Xi`wJO6b{7(Fz3|XqUufixT
zOBFZE+u^%KWU1nbU5_%a$Wq0FVrW^a*p#J;O<AgVj4V|=lzW;*?}QcK?*B^?JfR`M
z6Pgk{p(()=ni4#rDZvw(5<H<P!4sMiJfSJU6Pgk{p(()=ni4#rDZvw(5<H<P!4sMi
zJfSJU6Pgk{p(()=ni4#rDZvwN0df)kEeW3RpOWC=Rrfa}c;v>uMF}3cT>nW4p2(Eo
ziN;9qL}Mg)qA`$*Xp96;G)96a+L8oM2nimxQzUr8za_yFni4!ABzSm9iv&+-O7MiH
z1WyPF9?3=to^Xr=Ph?2&L<5PVERT<^Xky|hTMDOJG?+Nbeu|4dnxq|ND!}JhG+B(I
zIs{*FkqNnoOvpuKLM|c`auJ!3i^zmrL?+}SG9ed{3Au<&$VFsAE+P|h5t)#S$b?)(
zV;~oiDZvx%;kG1rq66hjEp<0krJ{oh+wu0RZo!>9S}BIBzDDC<F}l_LG!7A?sD44?
zP%+ACUmTfWwJK@>zSp4L#nO7!>+vB1?JgP(^#oi}iFVhZdJ1o%iFVhJdXA;7k!*N*
z08RwjUHl3jRUg6kUUafN3g>#<(;uBFZw-kAPxKNAp2(2ki3|yz$dKTPJ|A%Qhy+jc
z1qs(q!8=MNs@v{Wc&G`(N7QRaG&I8pB<5tVw-Y>u&-7@5w%p)Tv>JBT?Z~MaKB6Y1
z9nkoqU>qU?<3I<fFnlm`bUv?t`PTQHYY-s}AJG)M#!7|Z<7WuSUX+C4Bl?By6E7iU
z{FP<!2T#XNxR%=tAJOBs7bC`Zo<g!Pd_=#|QR3#U8gAaIcJmG$PsieyZ8}SxJ96$S
z6l-rjAB9Xk^hTyc+F`n3>N0MJ|8gUtRhYKsXm~~MNcOpJw5DIka?Y}!|8malMjzOl
ze~2=)FZQf{?TTGJ4Tqea9I|1C6nIWi7r1uDqc`EGa}y8edTZtxEO3T2jNZ&;Qs^Q$
zJckcPF*70t;ojBlnlYL89Bgc#y0;uQdH~J?BmmRI89Wl|25iukjJ7J#ToBg1XsTnq
z=K7W!^;0OsM+vLZBj3gUd5z4Cnz>OkH)`fa&D^M&8x;=(-<bgKY34@l%;kJOYO|f|
zc&*IbsQ8S^+^CrwHFKi|ck&?-ca%Q}|E?SK<KxAzXsbIYlC+?ztzvLAotL$aGWUy@
zgMQ@q>)ML&m>Ht&@ME!aAAI5Xy&XA5)wTz?bFII;qew-B;G0;?@b}WLQY-ibE<=Bx
z%#AuPxR?wDZ|R80=P*Bbfn)MkZEY3w(&>Jlc9kv&P7tyPZDnp$LKS}8QD?U`p66`M
z+^ClO5nOlkGB+wNqJIN7s<@2G)vj;SjY^kMxmINubJe+lUPri$%6%0^X_ryCS*GH)
zxQxmZyY6LPaT%2d#n3LJvgtA^n=YgB7?)ADb3NO+UN{iXjLqs0d<g!}7N1DHx!3ar
z!`T{FiFk9v6RVT(CL!M3(D3GlhBr4fyt&!Vb$kP6JJ-<%TX3UBf6I*;{ZnpK-huvx
z8<lex)A<{?NX2dPEWLjuxQ%!qQXWP`e;527;){v6jDgrcrupeI5MKo%Cm~$>0ba5z
zvFS#Q$GB1BF>cgs=Q{WKnr_r==Q=vXbfd<m8#UJW3++aYO*d+6x=~||ztC>fSmQ6W
z8#OlFsIlorjZHUdd}a^lf8s`sU*blM4L53RxKaPk&UNiZjZHUdJjRV0k8z{MW8A3m
z7&mG>#*J!j6(8$H<qpV~xKZQ3<wlKPnHx2JsT(y;+^9nv-VLv0Z~iLWB|39O^5N50
zYfo@Ha}8Qua3$LP<2rK{T79${uzFz){Slw)_7d3_+nFmPX4?DctUNYfyc5Lvxck_f
zr+=L>``VAe@i-(g*VBzETWa@BDekQqA7!ply;T)CPm`Q8?_k?Td$j9wgJpdOyNVs_
z$2YXxntj*f4u`x8QQzbE{GBv0b8BX9&CIQtxivGlX6Dw!gCTQk4hEaB%$K<}bK?#I
zf-l=03YHRQDZV5#w`S(n%-oupTT?zb2ZK>8lKSgAqJ!~CHx%5DU;o&Si2Htr1BJyR
z|9HJOb!PA*?g@UAb~=s**I@n0KS5iwf{nB`YHN1z2Yj0OCu(a>V9|AXlD6gsr_ee@
zTbWxEUdfg8c;BD6DDPtb{~$4@;rZ?VFfq=g@nB+nA#-cqNU(vGtM_w0IrL~|ZcS_a
zlO5e$G|AkWnOie+YyPisYaW7?Q*Kht+?vhXad)fCtDb`u^X3)6l2zvGa4#O5m92ER
zAK!bG1rjb?ij85*BV%`H=GKI-A#-cOfi-4#Xgp?jXgp?jXuPG}p%He6@)j$*L!-a7
zJ2WzPhep^PO7xEG4voy+p^>>eG{Wvs$;REG(U{$#v9UWelcNWuFC*m62)WyvRZTDJ
z|9e92p}pug9SS;ggY=@#f!osFT`NF8{Pmo>1Wz-2bFL30#lNE?baz_-9^e|DE(E);
zx04N?8?E7`Ja&<7Z^m(p<+!OhZU%OcF0#v-(szS3^9{_^utmlEk-Kv4&64v>*6>=L
zRN@B$wwvl28}<ZkuhumVq&04!2K7X21I7&qT*%hQci6z|#8Z3ESD`5l*tWg77mnFc
zWV|j>>)r?I%rHM$WCC`r&N>X%4beRG0#0gn$R>O$F;~w1HH*A4G1t!$-|(kXX5iU>
zVd_nZxq8m#ujSnJX!@-6vn~6_$r-QU#~+>Pb6pm_(JrHDx5_ym#-_3QjSXG>+S!LP
z&xx(p97Xe_w0djak6GbPHgnUj{Cz2AzUWKuRMz^^>*sGe7nzoXdN1+X`Nz@RIWbqy
zuYDfo(tteKIQ#j};J^L4GG}MUCQCYFm$Z7zdJd!FSd(vRd9|-ZgM8FF^bKr11{m*z
zDVbM0^J-^a?aZs4d9^dIHXaO_S3C1+$5#ER&M5P0Th_Rvy-#Ic?ds+5y)|#ZQbZ;*
zopB!XA(3s?&Ai&qUi2h8ydXMziwIuak-Gs-(uRZYdH>5Db+S)4?x0Km&W<`WyOfFl
z00KhS^=hjjI`d!cs9(s$SEHcMrHSD3x((l{{x>@6S0k?R6IO6{NBuq+zQe4USG#@(
zdZ;0y^MC57KgsTLNRjUHrxP8PcJncWPW-u}{v7jXUTr+fF2SO1&+#Qr%Ek-u<z!xM
zKxmxvF2~m3q1=zS4_K&|!$Ef)_W^$blPNT*mqU|!IUGy99B%J&JDE@~hl|UywM=cm
z)C*1O<<O*F4o&Li(4<}tP3q-vX+VF7rd|$B>gCX+UJgy_<<O*F4)?Ei;^w5Om%}x&
zf<fwKp5$bqUXFg?W?t?8HD2v(v#wQ{t3B4Y<FzgGY73X^LUj|jx0;;Ck;!=+nViRw
z$$6Z4wXqQ{^J-_Cb%padHaU;8&AOWN_<!tX-G14ci|w~Va3j0)MJ|DBQ9dDDYw8o%
z!_C;}T7am|+&*_<JMKM<8K)i1jeFp&g$L5!{5@otzUwC?DbOCw)zdFMRqUp=S53d_
zG_j{^xA4m0V>iHuI^OOg={9`0GxpjJ>0Ndrio1T8jMlcYWiK{GYG-z`f-`OAKl$!d
zZFdcPog-59St2P6g5wdX`K^h$YQ*PpXD8;$5oyOc$xh)FBjScVH!-bIY1R2@qh>w8
z^L<-lt{;^)UC?UM>_0Ji8)*`KtIMS~M%Lk}Yj2Zu#7bS{YYO^2H_p11$1F<B4YN+C
zxm~JaJL@8v+b8C+v+khz+Vsq39Y=F<ME5?rWY)tpcSy`t*8j)emj*~tooiQhS3@zU
zyQ*iZr@DLAZWv%-hGBpaP|<*bj*5a2BMJtDQ4v`t>~RaOxF$h~CW?uBTu5A_CPpQ3
zOQI$wD(*%Tw-|RciALl1JnyNhZW2iJUhnti=IbBRbDp#BRrS8ld5^L0AS!;-Ka3Q=
zSu`E*;6~T4<Mz++ec04qQT$dEzZJ!AMe$ov{8kjdcra8HzZJ#r|G$dgSMW{OXO@pQ
zC&TKddv2DmR>fx^$^6tx;1luk+~3IZ#A2}l0?VqV7J3!$!a2OEX5n92JTb0@Ng)HM
zUbP;ENIJPsuAMa)4E;uOinz14Gth?;I=OFd2L?LuNbZ+o^#(i%cg(W#yWpQ~&BY6z
zbu!*OlLzFaB^N@jncBIb8fur6hdk}nczb&Qk<F$iICL9oe<VxoBEZ5nkbr0Lc(mKu
zFD;7SG!?%y@;r_iDuEfN?nR{QbWb+Z_X2slp+W8`ro;Lg-a@p-U1K`rC0ZW84ct>r
zhZ-T<I|b4g_jDbz$`c*X8K%Qbl-GzD?%AfZ3CJ;QW=5xchQu^}Da6f20`IqmyUvWy
zg<s+z)Y-k<^jJ#W4QOt=`#m$gI~-mCXEfaJo1U(m#faC2m(>26=sMHej67`bCXgcC
z8%&R-RvC$<gg2RS1G&_-A(xDMtC_xqdH#1VzGZo(i*H%8vWsu0vApQw+rfBY|3nwx
zaz5DJ{b^MCMKeW|^yXCqy`)jvTS9%@D`txA%NU81Icl$(@w-{x+4#x1nOK@<9lZ+>
z!>x^F2n=r=2HW*xnQMTo=x8%h$zn56$zn56$zn4HrDU<0h!&f>5a;hKHq)zQv6&j0
z$YL|Wwk$R?taS0MZh3g|ElVq1d`nd0ox*{g74v5xUB<hUXtqW<?`ocxovRNlH+bh`
z?YW1?{KFBm;0@%AJ5t+=E*))Nh_KSpW{zy>Xfw+z9c|_~myR|Qm5w$Om5w$Om5w$O
zm5w$Om5w$Ol`J+Bl`J;1CrTEZiAolmiAopWvIi%6PjRK374sR^?X`1ytd04cEt4@)
z@59%%?vPRAI&>`_>UJ$Ih)4;{;7AF~d?F<<Bil@OH5{RKGE@Se&p@u$`@+C7CGaiq
zi<H361GpBWMoM5dx)2_177!k777!k777!k777$u&=Jpd^d@Ht`pT%TzUy0RAw7uEz
zS7Y@r;lIsZScvt|!cF#L(<pqC8t>O)^)umF_!ax*%~<^!t{7`6D?W&e?k(+Aa2fgS
z0CW(%qk+v7cjHfbCSw#1XYX&0)!zg^n;AVH1}2QcVy1jIR{v}GMM~hm0=O2p3!6XH
z*a*UI4wb+r{30cA8+QupddBC^gfKpO{upLu#_LBgK2?HlBCebNb2R_RFy_Zbb_Qci
z;hM?D>lskhnjYBiHaOG>v>-hwMK=rx<0m~h#r4pn9>t1Fw+bkzZ=<aA5ZSL<4Eu*z
zaNNSA=8cB+0?q-XhsJrV-=_b|VOT$-cq;Q8S@#&cia$lX>V;JlT@}y9ldpP_c27Z1
zRWH`=2D*E-J5U01Qf^fV+|5Q?<bM^P!!x4hL*arIHzEI;kMtqv;fPZ6QHFx7VlC=W
z^HGDiuZ2g=$2!i-coce9`V$!E5j^_5tK<#9X2!I>EX_2H;vdjg-iGWY@JcO3WD6FX
zp8yCgHq*@t-GTps#b$a%7Mp2{HniCMTgDA7HWPemi_Nbx>re@N6tn)cO5hRbvrq|4
zx4wV(vrq!xT&@J3h2dyWU!4T~@+VdT^TbJ{1kM6b3Cu=DN?;Zt_wV{oRnx8S-}Rra
zItL?YsqPJUem#@C0l-#Ejt6)?`D=iry2k?eeexxMv^pJ&!hb=cWmG>rIs6xs1}t9W
z)DtMwe>v#`G^l&A=lbRM@A~EU@A`jCv5l?jP;7X9`Te{8>k`tbMq)AfZwTm8$6_A&
zZweTz`e2gzZwVNu=3r;?-xe@l-Hz$%m*2nZZ?2w%igYWn`}%HbKAP~UEjF)1gEn~k
zV#@otf42?jI<EtRkBb2n7v@dgLiP#n-`x@DR_{huw(S1hF^H@0-_7FwU5=C7znjJV
zyD|)N|891R`**Wj+`pUM;{M$%?%!Pmku;As{}{vQT9Yu!p~Ys-%Kx&(=Ce>Y^^+MG
z%(@hpvY{?K4WK^7hFQ)LJw~p<XC#(=4*t8=fkgbd3V*Wf9iw<A_P*S}{I}p$T#7Nt
z4Nl7zauE6{*O6z+VlA@F4cG1mFf6%F?KaVSxe?lZF&D*1?S6xCMrn5yc10+GC7+F`
zCX~S94vsd9J2=`b?%-%M-O<tJ9^|K1!3Rg1**rt-fn0HarI2IQm*Io^D;Z*|G-ur5
z0+K3&2OsXQWJp>afM48S$;>jUi2VikS2850Ze_G11vIGbxq=o5C@4Pq{DlHq)Ni-|
z771uoZ?MqC0@~FDtWK|hPW3m=urCSdQupGq<}VR2R@F1wQUQ??m^B!$Cb6955;9S3
zX0#Ooy4Bm9p(_PUR#RBfRRX4BKslqW^XYeVZUvf!>4g<!bLFhTUw@-GfUE4-^f5s4
zT)Pww8Tq(2w9FkOw5H53c{Fe*@j2bMu-JTS7|gxJmmSr$9t%CWt;qG0k`Og{4I$0k
zU$(H=+y@>~2A8I+PedI7cgbQim#`PZ&p%phJ|Di8_YDltr&9v6unY=n!2iMfOqzz0
z%`6+Z<<Vwle>eVu4l3}*Y#wdC34R4nM#xO_G4~0MHcPav9&K)c)=1rmX@R579DGCZ
z;@j*10hZ#$x7ii}w&KON*?|I*a`A0;kN|!0Ei5)OgN!;AO9K|0^<+L6wayL^(4a<P
zHDrehD5&4D&^7@rY9F*C+b*D09mEWV320Xbum&9hI#n08((G^nU1|-}bP5=&KEevh
zju0?TeT!*E3K*|W!i>z05-?Gn$m(<n=vEG<XLdUQla1or%zOKMO&&{q68d0Vc3<0s
z8c^}GKl??ArZ2wDmS23EEx-8olPiIB@9^T=e`>Lr(ISh@1fSMoGv`&wVsi@Zaji~_
zdGT5H(K%_hu=o%=Z%d2K;(sAK=ys2@M=rk2-XZQmIC7fFK5ReB-kHxHeI&)juiuKY
zj|wnV6~||j*3qeBIogj2u+$-J_TvKjsIxgKo{%)Qx)PgB_DKQ#R0pFyCDE$X9K4uj
zpO(jUQvHd!JtH7(lnh8uz{5@M;iUm-0(}oJ4M_8)p`?>0()aMvfb<N+)c5di+kiCN
zDq963`;FZFDa}D|?hX&RhnEJVS*XngejFUKa)Wz#w=f`mKJ(xYl3#>>sgtfZjFa-a
z*e^kAD{qPUi8@@ZMknSc)t)~9)mK$$c7C_)<p8!i9Q~HxE6=xrr1~l9lHXhAXj+|(
zb(-HtRJR#*B6f=W6ahK)c?@)Zs(=R7fQ6CYH#G{?D5xynhVq{m&|h6bu%Cby)lD!h
z#qW?oY6>Ff_ZKi&J&&y~e~@2;>a;4pyyp*UCg@gov2HVjUo=mx#Z1f3llCl7k28ZK
z1oW!kVaes^3s|P!K|}IKO4h5?*D&+)3j};woylkm1stWm%RX3C$M@7@)GN$wnLK$`
z8-=l)uCTzp8NKLQXP{%{B4b+MrdR6X?_n|3jkg!$q_V2IfRYu-)KG6Cq;6LMrrJa>
zF_^a^+nW^3+bVQL-EMl`Iz3ngb-SmhU}D(H|2{&xQ#m{y8;sNs@SK}h_htK6%_t~~
z+SeTwY#*OT?dy&fV5v!1I(5egu+>D2VBN6-lImu(r0zHYY4t89Yu#4_WYkQ|hq~1Q
za_Z-J)2%yRK!f@Tb2~vmL2ZvduRBpdi|WEa*PSGwRsD@MI9Wiu`XxrN?i2x?Y8}g2
zBcMxt1q-q6Q~_hv0v39jfN|=1^nBgv0>-N=2+j~NQFSuSnF6}icuax1vjj|5KgT4j
z`>KGc>Or>jYXYXJ>zL;20;a2DnP#nknd%bO?Q8+F)%koAK1V>0QM`uZaBiOC*!)NI
zv0jgKVch$`x7dIsP<KJ~NAPm3r|>&yc~396;C1$-0><Rw%M7EwK?c%LZxb{I<NZT|
zreM4;A!yd)ZKMvdFrn%P*gs<qgVFH%fj-@adImjLKPX7F2ra4~tP`o#2(E7xV5@x@
zG9=i-F2&f@57k?k8izrtAMSE*$*7A6I^{C+oH`5xSwF&k0_8NIDU<NOm2brK7y^%9
z;(zKF=$&-^_I9y|%8bTFS-+!nm7#vgYK{|Nsg-!D)$b(0R(lcbEFftVS2Ny({BMz)
z^*h#VQUjYdsCS-`tl!;U!;H_tCRM+O)Ywpa5$q|zQu`6?CCkTF=Mzj8&`-4y>@DrD
zGKwC0u>JsV7;-B-gz4I_yD4mt)HN4lWj5B^1Nx&Jo_}a;^yoI6-XoV8jZG<TxR$c9
zyc(NRJqWOs+7F;0FWpI1L}eR`0@7+VGw3hTGU}@)zyQfDr#7N%8(Rc4sNFHE8wbi}
zSU^u+gj%JJ#KIfb^ac9^R^)<e$Y!R?74wE#N^qb6OPz<#YdT1Pt>$7_n`Q_|s*RYM
zO*5ri(`pwK*L1LejJg6@H|f`ioLYfeHO-Qc26Ygoeba0K1$8ZI)pUq}7IiVpnIoW8
zJ<4+C3TRh@v8y!o1UKFvg8ioHPzmW$LkaZv$5^Adj`f+BAA<H2*P_dtr__*ml=?1;
zDde}S`UduE^&mPlKSs7|$R)UUj}>64tB@qWy#QMcMg{Ua2uP|bEb07?0@7+{)H6R$
zKt`>{DCKvm;rQj$1We8R&hjW}P}?!u=L9qvO($aqb}d$*>EQKrUIgdRrHj90<X6dy
zZ5!vaIUt>gpZQ|KZeN1AWIku6S^q@59mK3*SJ7)y%)IrP&_>7KkVgjyQj=oUoHHO$
z8N+8VR(niLX{<xc7Btsf-#L%oRWXzC9)CJCW3d>aBVJr9L2^MY2}SuE1dBKeOsbJ$
zEF>8VI9ba^qQF#4=>mI=QLCBr?@g06ZAH%4Nr4w2=aI`6BJPW3l4~Hgc9qd}2IJmq
znq5!D?RO>KU5MAwyBzWEHERhN&$Z$ONM?3n>>kZCyXf(_y$(ZSuK&_N)cM#`B}j%h
zwszWxA88!$%%-wadd%Uvj*~}9{)d@qoqzAh-gyW=93K=?ujwPjtjIhw&8*Sl_Dfjs
z5vF{Nqen&_YMApw)YCqap+}l&zE`o!U5k&!?Y5`)Sm}2%trlR;n(IfSps~T=j2|QA
z><|>wGe)Ylqo->%dyLd-Tu`ZrW9BYiWSBbzeYb4vji)2OojvLSV`~o@``&4Uc@3A0
z-4VlTeol6Q*xH$6P~q{xcrDoefo~w}k-mjZaeIe{@M<vjDAx3+dA^gO?{;_veq)Zn
z0Qdu>Mf1lTv2d|r-dEJtS*D^y<1WlJ%Q*4J5vlA><bg$De26JF594yys0yj9LMp3}
z%CK9%+;0>XMpE5yE5IuP9B0;?!;Hiqs_(;6Nvl`!ph>*im#;QCH3W+;@pctIuo_g?
zu>hMJ@4;iKphg@A@LuD)04?hKSZ#^Fq;hy)X;sTl0C>M2g}?32tmSiz#D|h~CqS=}
z_^9Shlrt7!iIMo5lrzrT8!rk8*lrq&MB}}`qPRrNtnLQdH8X1gvPhVc$3*YaF$l9w
zNjKTMhP41i7ypc@-aFVd5=paWmIc#?-uy10w3$pGx9Q$WmQYh6l~qV(m?{-gS%p+q
zA(devR7hp`8mo}X@M&5hl~qV(6;fG+REBr^3aP9@DyxvnK9yyW3aP9@D$7+!Wff9c
zg;Z7{l~qV(kPlZ#WjR$Ll~qV(P)Yo2QrUwAk}3jH**GYE|BXmx7lE@Ak;(}ET}fp>
zfTG)~+rut4fk?3v^u~32dEJn4;)|9Pm%1$|F7@^H^^8Y~OMRn9x2Cv&azxF%rnrD|
z)Pn#`aj7q-xYU<ZT<XgyF7*Q>H%)P=ZxNs=F7+jfO9#r+6qklC*r%dXh2qjsPH|}{
zr?@nfQ(PL#DJ~7=6qkl_ic3Q|#igN~;?ht~acL;0xHObgTpG$LE)C@rmxgkROT!iv
zmxg)yThKV6xHSG9#brR@e~RM5@%v{KmlP>3?M-8Bt~7NX2pLV=`*ed;ETE{DU<<(x
z5@M^x1mk_u*plijf(ZiB>O_J)0$%4Zf;|IX=a&igN|CJ4pl&9ZETBovB-mRhmIXDM
zU>{*gwK%ld(=;VTnt3Z!Q|zS_c{sV|i8eO__1>AF3+*Os9h{y5xuSV@0Wo#j835e^
zEcF^g_Hw@{`$y|p0Mp%L0dV?<8O(GyLh+hbUjtdAd3Fr}$?p%NxYjbRPczf|>`<RI
zLX3UjA&gsQCJoTRvS?hZ2fnG>P@G*DZ{Gu;4nVC669OjkAq2YwOytP~yGoD5)RhDi
zHFM1<_M-NM#X?*uo=11DOPY165jpo1&$Bzh@=(_R6u)INz)(KY7cUTCsRPl(;(7tL
z+Q?`Z3P`G_80|X((#l}8iv(oUF!V(6VgWg|j3Ji@Xi$$a<Wd0zbtrSYOaLgHjP_jt
ztt!E+uN2U(mJ?hhpi?E7!PNq~)T_+k8UbU~*^IV9z&Q0C=Jq`S<JDZI`M!XO>N<2m
z@mc}h>On@kPQYX}iMd@bV5&Ni;06KHRE`<^K)`f$Bg?s2z)UrQ;1&V1(PxNf?jqe=
z{1ZaVUF)8~xDC01+?#0$s{TXjjJf_t<br`IG%c?gOS9WJ*5(&H2H>inb|DTO;B6E*
zul<Nc3k`F+oZ$cgsckZ;MhDuQN?<FsFPUqY2L(49^<r+Fh;lVY$(RX(lV!YpM?~W}
z3S2MJczT|T+mk^B*n3Qc##5p3RA@XPvQ%h1*cWDc<EzjYp4pE(R*!y0k^AGz4@pb<
zq#A><%gjemmO;6hBf(m-63@isw6k|f3fcTNCY&O}y9_&4;)R&H3|o%n-31aaP=?6%
z_9Khvg;*0&())l^sh481ou$3|6wu2t`!X93R&Q6tNW7}^?DSTR2Kr;n{~^M<yzN-+
z*LB!fZwAx78LRpQ!p3=he+2YS%=<EGKi=zy+9o#Zm=nDM)4i+1y1mDfK<~ve4<X%T
zZxP}r{-R?}_0GftGVy+_9}hxK^M0{EP(!@$R}gc0{^{F+3UTjhya05Y`9&<g7_T`T
zaI%>{lqm<slg}gW)3H3wUL=Ob(}$ut&&Bc&qazdT@v7Gm`dSQq%EKrzv(Fv)m!;da
zCZNjlw(tkQvXKxNjKoGpr-y6ZkKbB6j|`H>%A(UNJc0ND<1nclD2@gfshg0<Zbt~I
zVsgp{)>w$AhZyy}rW!v7nsx7?g>??bI+>Vd+TTVD?<|hzA!ap!;dyNA9L+7Wytjzv
znlcY~Se9MjTFkia3QP(oakOdwo|$};?6+gg8Un-n6-r4Qt5F~CFmTNi$C)+c!X^!y
z|2899P}TYe5+B9-l1%Tt!;$_tCI)g0Z#1iH#B1art4FJi2{WE%MB5w6n6Y^FYw)em
zcq%j=OsNWu2d}pk8V?>16&g>4##5p3RA@YqpHyf(6&g>4##5p3RBS`}f0E<5m#NqA
zhU9-BqWUYn>KcGr)2-NslJm+H+fdXhRBS_4Y(p8@ea&3OHWXGvg~mg*a)riIq488`
zJhaI0f5SFZg~nr4Xgu4nR8yhxRA@YSEve9W3<ETtNoRsu)2ta&Lg^`#QF@A+((?i-
zJxfiwIB(gDaeEw;hUWT*gwq4Fc?cR#0BTO#XwYrU<)#?Ig`uOicH$Mdl0m|I+dSfx
z+Fo*O?aDSW#k4BKE7}fb_?JVx9J*4P9>T5Y7_s)hu^yAnJ`-Pv+nrK}Obd8LLKd2A
zcJOVRSL|)l(RS3vetM0L9hvEKLP<L5cX4~8Bs~{Nhokb(^$#dXokB_aT@3?3Ng5%P
zq~E7?%jR_o2kC{7gVZU7yqMHwtmrJTh?m3+bZqVN5mKd>1O8G-QR?Vnq!m(+-si(x
z1&x8a9xDdudi3aetP1L}K-c5TK|OkPJ&p?Mu}qhAbWqYfW8_qpF-FQD<tZs`Wjn{z
zZIS=>Tjsw*ls~PFn>z+AIdTNKR^tM$)iT(p?@xZ!D?f?&Rhv*A`Bm4w6t}yfTJ9KE
z;a64oRTX{}=oJ-y750S+zpBEo0#~WRuS&$@Vt}&SJC%GfE8hMEERV?^?>R{%;&oS}
zm!^5kU|=)RC+@$GupX~3d4qj5THqbQbhbvzylPU!`o+^UQhbc}9F!7?s(88;=p^qw
zn3+u|UEX@{tvFCpr@P2IkmaQ`y3%`v)G|k->%0_8a5cKsdll~viL^!=y^F|itd7g8
zz|XY7e-<qyw7kYFTyS5F$A-AVuflLv_*E5tRpsuz%H4aFyZ0)0?^W*JtK7YZ^9Yr@
z_izHUa`&E5xqA;Rs{d{Ls^3B|UAcQt?$z6f&zs8Kd%}RL+`WgTOic`wHkG^ga6++i
z_g>}hJ=l?eoNX(2@0BjQy8%y==(0P4Pj=be1Bm&rF1w=!RZhM#@)nof-3pKBvO5+k
zm)*Syhlue!qwWr<_w4MKO}h@v9q$dG?9ryni(w4!I-+AVvS1$v(!MS3#T$(zK7X(k
zjKjakgwY9&c<rOn9Ndd1;o-e_M-(6?3r!e34)AYe!f0H%2_u57n=oQ~qI>ZOqI>ZO
zK1=S?*U*c&4;{Hi_u|nj6>^_$XD@#O6GnT(N=s<Mi0;qMgb{O#Oc)XTg9)Qwu)=an
z7fcwn{D+w^+7B(>stKbz+0X~k)1Ub*UAo7&eM?uwed0<BO&HM~nK05zFfd_65ScK#
z1Y;GMFe3PGnK0sN_~#~!*h`TKBW?zt(uC0mQu)AyQNGB^|1%RtixGVb6Glw$vqM7@
zMz6v{_EBag8<!4d9IQkGzC-TCo@icXn#<mZ+b6->T)#iOhsu3Zmzjg~g;Tw4xQyxw
zQ(G`vyTWMykg1N;_ki`h9=FpbQ$B~3!-jlEf-(mqGu+&T3)L8N7`qQ7m7yyRSwK9N
zb}C|PXSXd|2D~uj-}H98h)S4?LcE}3?oGgp%@p&dWgV$luPOJA>Wj&^w+}y?6*@t#
z`nvn&xP1|173TVN;C^&UeNG6fGi?N`b3#y?sUxH|Cj^z5Jo4q6k?f@4ny%haX!OZJ
zn-`7z2}?M|XP&svYoxGi)_A<%Hnw*9D5=(|L9OPE9C;QZpO!ygBKM4xMw~8}z@p9Q
zdOopSi=EqbG4tKWBpoFqz4!uaEh+ZN1s9rW4$VFT7!+HJiuJ5A%&9@ujzUgiv+78M
zT84Q~M0M%D5v5=l{(`Z+2->>2yHuzy6{<^x>H@uRh3bNRp+a@3P+cli7aBaOP+j`Y
zvhjsH4{s!ie7v5(@D69!)Wvg)fmRtdZ!n}&KD8SSy9aS-Tr0p0ZzcX3i_;ERBQ1?3
zYT}AUpBkURTTP-qu1K!YG@F~kL^-4BGI+WceVS<sOl)Dn<4(9;i{`+ZX_G6oiS@F0
zZ^ExllT;tUA*IKR!g;`n4RJAbR`@!>_u`F*T6iVe4L^Mj$hM;-YY>P=eP-lnk;-}n
z1ff2&d^V#(b*WHYDpZ#W)ulppsZd=iRF?|Xr9ySFkE($HvqE*LP+cHFtWaGbjL+rl
zv+#MOeli0}qB^<7z)%;S22fuyC4@P0xb#BBlu*T#P{ovxksT_lp<+si3ibb;ri3a~
z7wT+{km|B?0b;U{>aqvGzY*2tW@z4{+qww;_fcI^?Cf;ie)h*8DyXZVAFkU!xcjIN
zLh8N{Tpx53Lk{psXTbG844Izdu||6v_kDd0y8e(XL-%J#mSJuYS%%;r$TCTIMr4`8
zFf9K`_kDc>joX4Oa~(w4>Bf`oE7;KQV3-=$q-kx#P;X(F8qY{E02ejz!U)b$5nQK?
z)OYcrRmg8wwLR9<{|w1SkJPqFHch-I%(Ym7CSJkiS`*<c=av+2gABcCXuccGNlgL~
zF4<gfuSX<jaqlvtxiNSfo{#1>H&tDO085>=5};W^Y)wO<zfa-^N?>B?il4wCUGWv8
zSO<ke^8o*PhCPEH{z+I4DGmoH-i_nN&4cP5WDH&t@o^~zuCYSc;Pjge8-sZD#UORu
zD4vD)bhE=(@EVc<EyA237Dw9OjN1#KD=^pZ1@gqu-Xp*cnUQA|<7-#1Y#Yg#2iK99
z29ihH(E<l(*xfck;1I(2+FQTUb|&!`6>|b!*>*DVEOi^sM90^jzp{O)Va`?)454te
zgIjWlI#|H6w$+Szh@;_xwiN<}vJzjrZe`mJ#B(wvjl|cUxw368@!Vt<y&YeB#>%#d
z-vRECYyZHw8KxL)ndS@c#_f(DzXO{pP~5Z)q3_RXSVkg#%>9<#v3_&heh9Fw$e<Ub
z`1snBFl>5cW}+c2)Q)@{H-^t+oZb77O40={bG>l~7^0T(o%<rX$*qV&y2&@+i`$ps
z2=^_!Rp=%ax=Dp@f(2Khn_yq4&`m0I6Fh4xmQ^ZrllcE9bdzpUOy*|!+FX3bGmO3q
z9lo^|*5h^5e%bUHV802U{qQc=-^h03U$Ft4;(kpn^eWzk_o#l&LgKba%BdPAnGNVg
zp!G2B>{I*XgxE3|7uu;Q;?ADMKp(lPeKpg?frr{J$I=E|4R_44^1I-lZOz3Cn{_hY
zchv!M37d5xzDANeH$0D6DGzzt$?<kS*y@pQ$m9fvZbR*lWXW9wSa>ym6tU$ds?>gI
z)~uLD6H+ts$IyKP-Lq;Kr|w0h>vT>w)8`@^Z#Oi^ImL8XU&C97);McShi~7OM=rE;
zs_A?iVYYV)Xgkj7I%bu(32)TS8K%Qbl-GzD&e^7O1(0Ld%#6-}7bN)R5H}l%A2Q>0
zW_%R<5(i;SoXbs*rPSSk=C(WEGt*f(yaHZto$s5TuAIe)*P5QL+^>nQGrhZzhwa^j
zP0hK%^jK<e6P0t58Gi_{t_`_loLkNG8s@nxOc^;p)VUbmpP9>#!aSFwo1EJ;vOSkE
zf2>i`djr$Rxm}l+_A)rE=-i=eR)cp7<m}vK##`{e?k(im<veeu|IG6C##fv3J5%m~
zFub3#yMM2d<-LxtIOhd3#ra@+_p?i1)F|oAW9ctxl=hae^jFLj+m|sCCo`K@&G<T&
zcQ$@<P9~OKj!!r50>p4?V;KU&8;8Mm{8;8_Aj`WKUQSjc+iT`1<TOfpX%2l}qqMh>
zxzxon9F&aLjMPrOMn2}61q|vu(kG^~%Nk;Fde!ZMkDLY0v{-r|8s<HSb>r+G^9c;^
z`|RoIG5PkiysKIEfjZ3gZeTwg6!X~+NpBe&HzVe=?6l{yCNnjv@lN45&x-kNNRjdG
zB$};J&bylB&5ijZ5T<XUat@FAV}J_YK$dr;F1^L;!~%1AWByJEYxN$(ud^iPb0)QW
ziX*#Rm)GGv%YI)G^Em@My$$$vR%$fDTSc@=qmkbG?CGO48s!-r%cC{w@{T1sR-^5_
zbBK=9Xtehc$K+&<#&`{!EvM<880)Q+C8yCi&tbouq0xA6K4YG#dvK!n6j#bwI!x0?
zoV78Zvt=?y>gTAbYkgHljq4DnY|&=d;(|ytusY|&;tVcW(5^Xm#p*c{g?rfedt>#C
zY%|?aaLAh8(J06Ua9^x`J_EU0&kF-Rqi`oX<NjFv8u%5SX8{ky>aPcIEk-TO=1@Hr
zt7o?sehz=<i2w{mEu5zUa3aCe0k{JRo!<uFFPyE<#p=2J6!u`_Uy9Wq&)lA6f4&k#
z+Z#U4tFii<@!w`I?1YNx?`hL0e3OlREmq$S&%&>elk;Y*{r~{i+LaX_#P+|Xy$UWP
zza4-Mf_F5qnPMIOq-Qcl;c$-A=2-nn@UxlG^<iKF_lz^;yRrI<;a8B|;IFaz`vF{w
z+l9@a=fn8u=EZEmhq3x!GyYAiqY<zFtHeJZy<_vI8XYW!qvwx7kYmQ{P52d_<sOoV
z>*jw8Iqew6{Mg90F~$@QL^fW}fT~t^V81iqP$SR+cTkFMT>Fk6cW{cUu}M9O73a1J
zD5!6<8bf6FYSH3~3y?x;(r8#OU^8%s#`lJoP5)cMuzp7IROUId?z`|R{uJ@j3#%we
zDV~jmnO>ybQ_xfC#oFCKcdvGzi=j_1ui>ODkbDYGY?2a{;`i{htxmf+G}^WJh!;yK
z)nzwPRez*o4o8&gk3_grtVJEFKWdO1u0=N0AL}?TqnMg2{RzzZ5v;?StK<zpBwi;V
zy)@G_ihn>AYBpq-z)NIl-wwkdODlW>8{fS2SK*b)!rks2XBW^!d60XneY&+W+dIB$
z5P+p7Vw?0%@JNpJ)n*7Sy%T+sesgN4a{*2g2~&fbLU6Kxf;#MGfKvptsL?F*Y<b+Y
zq93jf>opqLOP$k3@xgV7b72FEPhAOj#=F#B3!v+DxlgyDZoCz-u8>Mv>W|F!yBSu+
zc9tD-xZzzXAgOp@%ezVrY^71)E=X%7SiKE-x{IUfzQMZ|Zr3^wzp2+zWQ+G3do0?j
zi+ngwx1nxh#U61!4`8W_S>&V6TmW1BhG3Jk1|X?+B6v(dTJ6sKA9t=mNJd@HkSCnm
z0CK8>;7R8pfClvif~TAp0Sc(d4^WX>)`?~5%bGc55VA8onpvpNV0cW2TgIM+>!_5-
z328Zub3_=2)eujaIU#5IECzEbv0`DG4PhEqF!cOM=*fyoVW`0-xQo}bZ=PvpM-|^;
zV>XK@xHyaMzlytXKI0_JG-q>RFgvEz)FIE^3@}uO4BQTKbF<T9A0*;EKeud~(}a(5
znIUmw;3GF8#@=2xyb|$K5o6#R^jRws+eCadWS4`UqR&bC0AlX_xZQ$6&GlCz$>0}t
zklZ576M};V-Gs0n9e3Ja;`ZGV_g%zoU2#|sgKF5@I9NC2sxKnyVK{w=C^&66WPkLV
zdAJ#z2t;0u%xjuyvOhbKmoB$Z8|F1F%nNZ1#@$7iYawpCl)E5`yGs;z@P^|gY6G)H
zxr1vC6Wq$aM7@kb7qC%7bzW!wIc~3#yne>K<}5#qL1B9bx9F&apbdjR(0I7Uy}Hdq
z&7F0d7Z^j&W`s?0cCzbFaeKN6xPGz^!LVe#shX1$g5`F}c~i5_sHa^r-qfMt>^AAk
zO*`pqXAZlZxjr78QCv1mdiIF`E*R#qZ=S5_4%*kzkN9pgjq+QhX-inXWO=tNUykJP
z;f!^o$s%5XkhxW2UW1tJB;}Yl1~pyPF8z07ldkwOqjLi*vtF7=>GV`dX#AvrrEZ-3
zi%5dKEAq#4#TbVfbrSaAz4rX9B-qvsW6_6?XQi`j>x(GGIss4A_;zwHn{_{et#*gw
zZ*5}W5^*Q~gtZYn)Rc66EbEH+uMwl~NqBNvS0*o^`&q`m%A>y)tvnA$u#~E7>(YJ+
zjHh}LPb}+leb>9f-fCD^C$8l`!@37WSl7gv%sPecYwIx^jihDWiRqQ_wbG{<?*=(Y
zv*lY+E)XB#(Tz9aBaOsJ$=OoF5GyfK^cuFhdJus;>5^&}JYo|g>p7v*&a72NVw5@q
z$urnt+VJ1z2f+pSlbU0nei81L#2C8?o4zvflh|G^yhl^;Kuqi)z)~k;@Dn=<uvI%6
znHVP^sa9G5I|)dujts!g0y3%|J(l>KfSj67FkV1|x`tU#5Ku7E>(R@$nb^~w%Q{@j
zu)V72Hq;tCxD%865v;C$*#p?8iY+kA>fPCC`wFs5!)}D{Qbdz>H5+N(L;rO%aj<<e
zGnJ0~Vh!Df`k0lR)rVbVss5OLi9`DR7$LS|O%ijO*cYdw!<e7_0DkxvWb9hM0jNoh
zNAY%Ix&2ol^$V<u#ENRV4K)C3AhA+sk4(55rG{Y&&P)8>mJh{Qy+-1N8j0-8T4E$#
z)Pw5GT4^L+61S~(Wn2H5H2Yzcl~%8^DX&VJoEpNRf4ho3(V)7H1=!s9Yiub6H3AbY
z@m`~W7rPeqeU8LmQY`?jYWWEO@Aumopxv3Ze2$U$u$ozS0-%~7Nj1j;pq_t|a>jXk
zbNEfOdLj~y_x_6F5;3!S8qltpSqqRw!jwEFdY6ttn60n8pX^=3TJ$rkPDhVS_1?jI
zPa<j79Etfe&70o^ls1$6-kk2OWC=B<!zHy<X*Lu2^265pccPWyV|WFEvJA@cbX1F#
zcqV2u+`9yC`ibAhq!EU98OQyFn7R(tw!FJI&t8aSh-_~^7XL!5i74rPz&?H{Ciacf
z-hEtoFURcb@Jg8Rc14WDt2)n4Z`Ej^KgRrf5Z2{whcQpQuEWN9GnnqpSQXDyjr02c
z2<V-dtnBe#Kh!p{S;w5{6`1Z_9oFqVj(7jWd$G*ZNH^JA#LoVUjycsklLP*KtRI^<
z&HKgvKn?M}XCUVEJm-I+5cfFcyUqL}7GI3la7s@$^M^9!z<Ba?#C<xJ?_wcC<LNJ<
zInTxN4`YB5?eVJj5&BvTbNC(<5HtJSfqz-LU5gW0-k073EE@@dTv>?o0Hf2xwI0K7
z?YZ#ftSgI7uW;b{AV{+0WGux&>Y?zEr#k1DtV5{xxvqLbjQU=KEj4kVS!ZGm*EtyL
zWMY<S(|EQgtN#$Qn!xZpHg=All$Q4v(OgsJ0gbk?3tWpC*Ij{0;UtbW?KhdpH@R$%
zF>446?^o!@#IYLn@ebqec$`_oH~OSu^WVpa7F4zVfy76#z8Q3;_YOz;<Cus54R187
zY{Y9gewH_lV{69KjA(m988a5oa<6Xj*0PrW;_&3nD6wQGoJ*%<C!DBcC!DBcC%gsa
zmF$Ff0d31pIMbEvgcFtQgcFtQgcFtQgcJRPop8=07A>6wJK@AETrli}6Hg3rXeazg
zctnRM2}*}2j|RfwNp7ojN;bjaNv?<h>%)^=ywTxFj#PAbk|pZ0H-?F#!;|!B=K7V%
ziCJ<#+^$G<o4Js}iM(07e}`XNCMedLlwNjtlKWG1c=AgC+dMp3CfUZSLsrH9fq+|P
z&7OEp*x5X1oYjzryCBkM5q$Rx1>b)~SDucf1B~of@UK4w-&IX5^y*K+cU76-TWP^}
z%Xbkdg70LR;5!)zzVBur1>eas!FN&%zFR2L-iqKmStj^S?c9*VE~f?GsqyxB0QpEv
zO>pSeg74HW0x0-S!n6PJXsfednl<ZB!M8Ibe<R%#d^@vh7)J}fT?oD(1QNlw3&A(*
zs|DXK1mApQXu-D&!8hgQTJY^c@XeT7@a;nI%}li5+lAo!86XJ08HLVZOa;Fl;z022
zLhwBwej@mGA@~-lya>Ks2)_5hZY+Xt7lLnHISRgA2)=dYDEM|E`2GNSXu-D&!8c0{
z1m7+M-+hsb7JR!9d{cBLf^QdsZ|0%}-!25-I!_9|T?oF3wBXx?;G0MbzFi2uS)LYr
zyAXV{W`W?_h2WcyFfI6YA^7gVmL!627lLnH9z|U)1mC*6*YOl}A^7He(1LFlf^Q-%
z_;w-qCeng$7lLoLFA#jY5PaXy@<j0MLh!wT<x%kMLhwzX1>Y_N-!}kh!M6*+H<1>6
zyAXU6X~DM(!8ef>e7g{Qb5OM4+lAnph=T7O5y!RI1`&L_5PZ{13%*?lzGtFgBKUS8
z_$JVTZx@1Z-Es=PT?oDzrUl<F1mC*l%h*Q{e6uty_;w-qCeng$7lQ9ONT&tgE(G61
zTJY^c@I4Pm3%*?lz83*$!M6*+H%r%oZx@2^WeC%PZx@1Zj;t1ZyAXV{JT3TkA^7Gv
zYr(e*!8ef>e7g{Q6KTP>3&A&$7JR!9d=qKGw+q2HkrsTr5PTD9!M6*+H<1>6yAXV{
zC$!+(JzXO$_;w-qW|$UyyAXV{2eshah2WcErE`;<EfjoXN#OS$88xm$*J2;J78isF
zzFi2u87zWt7lLo*BZ6-if^SB)nU11sS<{fnQt<6U@O?1@xmtf21_pv}7lQ9Q;3tA_
z7lQ9s09=bvMeyxH@Xbbx;M;}ZTL1;$E(G5KDEM|E_!hv*x)6K|py1nu;G5fz2)<ni
zzHeo2&tkIi+@wU~)4+w``*r-c*$d0?iZZYVQ9cd?-!25-)I5sd+lAo!s{pP=5x)q&
zT?oGEC4z4kf^Pv7e7g{Q6WIKr=vsOv5PZ83eBZ`EX7oxJn9zc67lQA{;U|J`7lQ8?
z`_kfeVe=;k7<MxS-!25-HvB~J?LzQ9QsUpr`26V(;|GFo7lQAxj8DP03&FQE{~_eG
zB#a5c_Z-Hc;M;}Zn*mj=>4E)z3Wo^3(}PlUYr%JVaEj|e3%=8>0<_>eJw$dW2)_9?
z@*AX(ng@dK^w9W8@UrRuMi|!5=zl6QPLHg67GC`+_^w`9MSg033cjlsX*UJm)r+;8
zg74~H?WW+ndU*{er3k+J1%mJX6nxjD-6?Fe#Ycbt=kScE`Op#fCgfkE1>gNC_^#1{
z@BS2g*J#0a|7%gL8ZG$lPr<jR1>gNC`1S(9H#7So(n~W<qdx`T-iGW|@aj)$Y9^qj
zE=68eZNBO?1gIBLcx_#tZdUHs_&?}Ny+&<gj$WzLE<(E6VrDX$ulROeJD}<v##PT@
z($}^Ku+&i}0SpugpsilTJ6Y`@0gy0Y7Ss+7gwGbUt8I;c#H=m+*nW$B7PICVN`Fv4
zO$FYJhn+uIfT?U0>bIu3GAtwY6x!b9?_yI5FE1Vb#0=er;`;F?rR2p*iOhI6kx<%d
zAXb;ZyM!dwSd5q7Eg@;uhXw7Cnt=2fXVIa{41Z7W=kUv^%h3jZuhe1aod(6r^Zdyo
z@-L_=)WF|cGH4NHfWMD`R)^-z{2BQcl+doOLFfBNWQPKDqF>p_!7O28_6eIss2P|g
z*{7=M)*6QF(^XesG%eM=0U^&M?*XvYlH&oMPrd*EOLrK>?C+EB1EkgI=$Pya5-p?p
z;pvfmG3n)4`6p0l_T}UdfChChK5w#rkO3&Db5X18s{&e72g0*|ls2}iLouA$*F?_N
zu6i+O+1DkcQ;kGdWZw|brH*9=ZweTz`e4Fk-x4rR%|S0`-xe@l-HzeRz9aoI(OG!J
z93#8AdO9l7t#(I`X5UR6izcjBbC~se^2%|M8ifJO{z<@P>NV!}fmG*8uNs|~tu@{6
zqQV=zeK7!8-}H9|y3Xss;Ab06#hG)Hw~&3(Vk%xNd8>CLD?3Ps{TPG5_wBm=_?ezt
zXxbbnZ$DHjx7e(eVernunB;m*mzh~!BZ|#^Nuz|f3dQD@nC@_d_3{3OZ`9mUGxrYY
z#{Ba96^0Rt2&Aw+#vu7e<vA<+$Iy}fr5-15|1&uwF4OMEIVCUG?yn;&{|a%Zc1Qh_
z`J8<b>LzC>^K~+B^%=^1*%``wgU?7T`wIMbEsD%-{`?q!vIRIO6MdQ=nBM@e{!1|?
z`N5)j=zkE($#>+LvVScalpn6$4`5jGo!V`pzWEW_eKDGsAF17MFwQ9LuEGwP@6zs#
zXk>mn?Y<P#F+W<n8_=owG1}eCJjaSVbsoBYT6T_29lBbDnq+(AIGCaKK(5(CgQfgs
zWSc!qLTr`hj4MAwnVlygX>|Zvkv$^C%rdHottC5OLUQU>^l$b^0S#(<uAl`13hE}#
zxP<~*)Ni-|771uoZ?MqC0@~FDtWK|hPW3m=urCSdQulJ5ED<nP)ic^s0oq)6cA0?j
zY7)y?E?}bC%xEhFbgQ>HLstrztfsJ{s{~BNfXXC1pMFQ@PD8UWz0hMeSI+tP8({Pw
zz*Tl^`fEV)jJp{Q8Tq)D#c&4+ziSyL0vhflKBv1Dym4wG>-)oC?k&FTsIK*D=*exx
zKL|Z62@(Bcgfw%1k=NF+j66KF5QrgMpNKjU|LUGVujO*PnKqZO7sF4k+Z27M;dOIi
zO*WI?gRkX%0|S)X+jLnk+dB}QmD@+7r1w+CoT4pkroA&U$8!6cIhI2S`EdMi-DlD?
zD9+6+8(27yoj1%BJ)q6(AH!eJL4_fRkzHn{?}J~#lMyo0e9RU2PLlmfprc#J{bh9k
zp5$<?38LM{DSMHr7w!hko~gN_J*Ezm`9@5OTz?rzL-j#OuH0OBu0=v@^*eUTKmkeR
zp`6?x0ckY{70(S8kWr_ioLsAboH`h_&J7XJphjUe<jT)b=Gr8rMeW0_t6e~=I*1tz
z6VR>>z{uq~1azt{cIa>cU1|-}bP5=&_=L`l5HL=Ci)ls*7_UxZ-9`zRs7_>cx&(A9
zhkNOE0wx>%-)7$1WAnkIeiHg%Ty9@GgWXbHgzn9KQKA{@0j8NHPhd;^kTsYsz*ava
zI7C2FJw`A`Kw7;-FjqiE9f*07(;J6ALzz2NLK@WPF<8071QgU87~q`VI9k+OST{Mn
zakQ%UnA;H&4Nq-WdcHh^I@RTT8XP0fpf2Z#!+MR}iSoD}YgjY!;L4qyE1*4~qF~JX
zKg&KkC(Rc2e~6v8PVeq~A<Nz7h(FDR=Wh2n$@=fiV($>QK0}$SH|=|nTFiy#8cd(S
z@C??d(M<A9#PVL@>S)r)_HHC9m{q*9LYoWE6-~tt$+Y(<hpE4Q_HlL0K^$3|jO=$}
zO32bh$o=pTbK$wcW*rN)xuRl_@XJ!cn>%fQ=U&neLdl~Efj)nbyaoT7PP!g>jAip)
zGaVk%b1fIYV!}H2y7r1pSoa`gOB2@7xxOnHw6$}6eCozjaIS9;#EQ=KQ4Cpju8+G^
z|FxKw^;2r-PRWV0`jhRKnKe(G)vrl2H+|x){)`j@Ad==s!k^)kMyHG+=iUTG)$O8v
zNW@QqI(_Io`izOW-AH`q$2j7HjyBgH+Xx*jZ(@!OqPQI9d)wy%ZXZi)xT?KprD5(6
z3)Hyt+86ZB!BxyLkHSt|uHC-KFvn>H1(e$DD-3g|n7nGn)-ExIJ-{;SVtooIZvo0R
z*Z&gbX@kFYu@(ZP>Nt41L>oroJyhYtyAiz;?)IfPLe&(je?;P~;<((2HbO>@-_E7X
z{LflnKJ#y(&cCw>4O+Tv34=0xokoTo7tWQaLv?`*hChestteo`T;}mNGbmvha{UT@
z9x|op3`CnL)n0*IJ32A35Hv{V(mT8r!Kg@(%Ohrkt|xOjletVaO?KijABAR@KVaPs
zfhvEhDc5eI|8!qWHJkZn2?e~a`c$(`SG}i06!KHeF-M{x7#5b%`Mg;bv~2j5$b3BO
zFq<VFV5a%*h(3kn<YM}46ovRJAI9x<h-I!{g;R;6ScQ#24d#tn%ImZ@7J}g))w6UN
zU^~|#${U_W0n?DQOA7e4qx0|Wx|6y8Mm}uNjO`9xf*yZZz6hoC(N8e^a+C9NJxZS}
zrC-9*#US(LNj=!BjFHbV<|!sK9*dZKbeiiwWK0>xQ{+jHGP<PyPnE3~WpoW5frzKc
zTRO(L>s4m+)il4Y6Y=CPE!!A*6TNmY*;iEee~2k-uHR6AJZL8g@##h*$4Fy#Oy3}I
z=9p_3I!@l;a3*j&E{L52w5)3^13xDpAuRU76@cRdIIoXoPO#2GHe=DJyQXiY3&yV}
z%CHz+!Zn%HXR(yi({&HC+AYX=0p>NgNz87;Ft+FWQ}D1irWLVc7{7ZkA~6_0Ks?0S
zXjt|-4AhSxZh(^P7EX85{sI5R5?{wNITq_nmPO1;ypM-i%<8)Xx+i8Q-X*g8ZU+>%
z5=Sgr#<0&xSc$k0D<dw%%ZLl{GU9?25f|cD#P30sgt!pDGI=iDBre3S^60O%W{<)V
zw5rOEU)t||U?DEV%ZUr|s}q+ZARsQpuZc66MdCvI+WIAMZ-cl%TasGeKEk8>zd>C1
z3X=1|Lyf=f;pc1klbT~wei3dG7iut}{$CRp4qzPu;sV_fae*KrF0chgL|h;uae*4|
z!x2r|RZd*EnwbW~1-iFRT(}M)5pjWiLE-}Qvp3?0e?i8sbuU1PxImU)NL--%pA#1*
z;61_7#081`UnefyhqAU#TwqT`#0BnI5pm&NfQYz|!;4cyT%cqjA}%oNh`7LNZiBcm
z7Kuv4g>Ik{ae;Yki@0zcdZ|QQn1wDW5f`ZAED;yDq_#?2U?Q=-Dja!DG~_0XL7R^t
zv8q}|Tp+P(8^ndnQ0)?Nfv7}WAlepj;WE7JY>T+?LxgRMxInA1CE@~C_O^%%3@Z^A
z_~y4Q;sTpjA}-LzZHc(RDPKlh;FK;SF3?zQ8FArIG`NhoKy9oL7ia?@BreeHTAax8
z0{REQvXKxNjKoF+W$A%8Tm06Zj`88FD~nFA@SF7m#$i%U#!?)lZi0sp6*$La9R|b&
z8r2ny=VVA+cn>Ws5f{FV7!h%SU|Ylm8F`e&F2MIaeoMrK-!qetxIj=ME)Z>%xIkON
zK~*(z!A56pgSf!)D-jnMu|!<pUj5043#4U~hzndgCE@~6iMT*iA}-JzM~S#lx!@eV
z&pCb*x<v*sA}-LUV)fYw*$cPht!`WFg#k|@@L#hRsv&%h*bCbOgzN>nBlZFT*$WB$
zmt%WiFHm$L$M(Qp;87zvwg>hC<CNG7_X0)i1=hF3Uf@%*#9sI%!b<D~#w@WHm`RDf
zun7q41xBGW+>MA|3UL{GVJ`e4_5w@M$M(ox*d6b!5qm*b&cbUh*$cXIA$wsn@+h$v
zSZW!2!9Xr0_QEa9lgIYRUSKXI_JYncWG@hv*b77@_5#Z*u@_jgGWNnWmM6#d$X*x>
z`C7zY(B*~f1zldqUf_Hvu@{I+>;<9{dx7mMV=vsz@*?)a<t#5`FA$X23)cXZ*b77@
z_5x9fy+BlAFK|#w>;)pS7f9tRJGMvm0=-J?h5aFtir5PTCH8`DdB|R1Sc$!$TOP6(
zSXzm_KvZHcP%BkpFA$a33x@!e*b9dPmDmd`y~JKvh_DiSfg@XDFR;84dx7IzVlNPt
z*b77@_5x9fy+BlAFA$a33q&RM0#S**z@8|v7l=yi1)>srfjwAaFEFgcUf^sYd*OZf
zf~z2-#&zgg>?7CWf{54)435|f%qL<mFtW{bSHmG|x{SSWJ_EU0?+XJViQ}<7vKMZF
zU&LN`9>BF2HDWKY(Ghz=K*(MY5V98pgzN<YA$x(_PsCohp1D1X$yTxYT(SC$mz2r{
z=Xf?(tUgz)K4UljUuX4s5d`jJ4g5I6r^Y0xp@gwedsKb|-UEwdEYxboLXnJxTFqD}
zlCe;$84E=+7HZ2G3l*!+`26<|6*GR8`ZAuBemP^IV)fZr1NCTsqhj^BV)eOV^%>hk
zKy~`xYV~>05xqtx`>_2i)ahzI9wgaEQZx^t--@!23NTd_9xmBUDcWd?sbleA$v!5)
zQitGkG5ffHKI&||Qf8l!G`6}DJ8AYw0sT}5qdg_jsuZd8*{4&y?KP?X#N3_{kTyz2
zs3+jz7Tvc_pa~Qp2+F;(nm~~Sfr7bc0!0=CiW!LcukKrCTSZXJ$XndEzB@dk`_@^g
z+_!!l9P&+v&o+wDx41<8eCEL)Jc2L6zvvS6mm1ND!6oVv9$J=874V=AElcMB{*5e4
zpA1!VWLcVE>z1Y2p6C*Fg6I-;g3t02_08x-*E$2aMwh75tMCw}YTfRp#~GQr=3<B}
z>g(-u!6}d~uW$6|{_KoDGq=e2Gr>O?fA-)R8Gl}gp8HQS{=6QI+rs#BXvEpZ^!=YP
z;;ego0$ybEJBwlP2DKgJBKgk=XfgsL&a6OS#My(h+=#Qa*Leu*%8*QvdI#=I(~kBJ
zS>Zo0U?(xoV5n2i2iQ3<H$H<QpGyrzEK42yEr9U?Y_&Z@c9GpIsTN!S&@CXP;tZK0
zwyzzPSPw8&Kw1sB5MW;cHO7$bKvXb?nVhj31Fiz>Fc-xRGguYFvUKCF?Y6n!N5tWJ
zvt2vCZ4lFS25?1N6X6JXK?UccZ5ZLmlxW!2E^d2=G>TC{<T-8c6Ltk~LHjb4vt4Fi
zDW?bPY6^Bj*BXu18t-FOS;o|dB3{K@WK3Sgw3uZ-&X?l-D!ht{dE<(CW5|R5nL&sO
zucD-Sukb1=yow61qQa~APrOaL%pgR$sbe{r_Af0#&;;^Iya&Pr@&f!56UeXxK`$|Z
zycJ6j1J)sMo0cG`*V`tSf_mD2&7~moA>vXD0|>bkbVpnY0&*#+FAcdAtXasV5MD)K
z34(D-T#6qdWyGameYeG>_$k6lTnff4aVeNdiA(VdAaE%dh0c&mLHuNh%eWK=z%Sxb
zu#^&)Vn=*hL|h78xvg_4UPc}zE(J?1<5Ii}SmIJ#!#w}HTnd&~;!?0?Wn7AGlu+VQ
z)I*T+iMSM;4<#-IQHe`IRN_*wePvvVTUlPjrT7-h3%L{oB`(ExfJ$5nq7s*asKlip
zDsd?|C?zfh5xEqti1T+`3VM~e6nj9P6mcmCw#B7jScyxaTOM*LSXzloK~&;WOhLL5
zmx8For69YY#HAq5Vq07ak_1Xz3XW`vOTqF=TndhJiAzCL;!+TmxD-SsE(KAEOF>lP
zQV^B66htL11$&~zr64MCDTqp33ie=$OTn-bmx8l}Tne7Lb1mBVa4oJw*J2;J78gXs
zrC@NxrC>f0mqG|HO!sZ1`g<+~1!^`|>uq6R8JFT3_(fcbM*(0(1W_X{1sff4DFlRE
z3IQRPLO{r+5D;=Hxcx+2ip!bXvzTn;Qb@GD*>G5bAT`8hFC2mo=q*ej(-Oo~ct(~W
zjs^fxoE4`DWLkotS7Zr7Kxheqz~;}b_>-O~vjlM^1DVmIVPKghh<o4{S%P>Iz_qwt
z*!)T0s6*Jzp(Tj-7@sDPX$hhk5nPLGDVsk$C?WCD^E81>OArI$7g>Uk=97amD~t(C
z5K|Z<v;@Hbu>^4~9HAu$x+6;vTn~{Y2!hBG1m{X%0{Kp)keZY%L3{~bHvOLp!vYh?
zumnM)?_vTOmLMqO78A&@1R?Ig5`?$|OAz7?EJ1KmZea;ROd!J&#5j`WN+ytD34(0g
zVwoj~VwoifF@YRdf+${#_6C+9ie;7{!~}9^34)njfg+@tfeB<-f;bmmsijD7W%5-I
z0*Lj8OkJLCR_F%&9|-FYnZ_KwwDpHfF*6K;e6jwJ8Bp~w<BIi%Op5?*{UK9s{UK9s
z{UNi3^@mJroVGu-^@rLPdl9q#v|NgT5b(*1M(xB5-P-y??W8~fOY0A{<<=i+cb5=t
z{h_wp`a^BG^@rL$y{jQ1*47_t_Ywh^w*F9CZvCOQ-1<Xpx%G$I8TmvlHfXW_P<upH
z0nqvb8#zd<Klo4BEJCb5_)k^Stq=P9PghY#s;xix&m?IILR)|EpBEbs+WLe4`{a`d
z(bgaQ7bKdt{@}lud>0|w`h)*+vI=MIwDkwS-1>uGZvDakqqI?5fAGt#Klraph_?RV
zzac<dfAHTFpshdnZwb)WAN;okXzLGtx%CHsbM^K(M5V1i`0u8^h>B|K5B_^%2wPi!
z_~%@TQ_&!8{lSOzhh`vc{Q>7#6&Ibh{@}y<1CMuV>kmGxKQN5eAKEZ0wDpH9tUqv^
z#QH-P)*oaT#QH-P)*qNaTYt#H`U8=+{*Z<B2OcWZ)*rI4{_rp)q2y9rhhfCkfEeYF
zOTk(BU*=LAkGgI325mOXa*pURat%HsvFtVY594w~{J9W+vg{qBNb3)|fq7oYU8MDg
zoVNZ@r1ghfN1iE*wEmDAuHCf$kn7ZLT7Srm&~93P$c@x)T7Srm(r#LR$aQJ=Moi?~
zcG^wr54q9WP3sT2G1^V*54o}8*47{VIrenqC)OYQo|Hb8OY0AR&!u39w*CMv1wnL!
zHi5SO;2)7<X4?9LKVPD0>ks~s0<`r9e}MpP{lQ--KwE$C7YWeTAN<7vwDkwSSAe$u
z;D1Sgw*KHR5umL<_)7(7>ks}i0owY5zg&Q}{@||=pshdnD+Orl5B@3vwEiHIkk%jk
zqjU4oEKDz~Ae$@aX#AD96um%lbl^NVWaI<u58Oe*Q!We><)xT};B+sUNk`Tj!eH(#
zzU-)FCLy@3_&i<f%Q|tb=it%I{Y9UHIv7KbOg;!R;nI}#3D1FWYwHhLSbyLW7V8h$
zEv!FeVg2E&2-4OcvRhbx$Zlc%Aq(pd>=|wSAq(pdER4qt)A&D_)*pOWe_%bu`hy=@
ze_-~v;xFhRvHsx0`oop*6YCHDax=}xoLGPG%dJ27tIMoE_^|#U(P;g_zo^{$L$+w=
zLhBFN{xXo-`a^br088zO9?G@|(AFQa0|jX757|KiwDpJVU;*0tL$+0bw*HVEB0yVz
zzzy150MQNF1lsyTwp~KB^@r>*0owXQwnKon{*WCmKwE#vb_&qeAF?9^XzLHzkpjkx
z^@r>z0owXQwo8Dv{*c{Hz+|IH>krxO^L_Go)Qk0p?7sGU>>YmUXTK=XwDpH<x%G!^
zx%G!^x%G!^x%G!^x%CHdDcI~!z@^Z=L+cMP8$+P2Kfr9v1k7M<{Q+iU$Ys~oAF}1v
zAF?OP<2tbZkUcwRiXN;5tt!&`L-w3BTUey^hpe{#P^9&T>}`(t)A~d9c8{~CNb3*T
zJH%ZgFI<8ABJu)3iM&AdUx~axR3a~IM9hChUf30JWc@R;U(LD8R$|?3fJa1LV4*fw
z)bHVtrLr~h!pF>mKS-W{j=g04Aq(pdS@^itTL_MH@AOI?g0p*t`~drV0BSI5kRRyN
zZK!9^ocy2^cNj}8!tS3RETE5Cjo^H%09)<LkRkGlkyMxB*jaw4fV3Ki?~D9!mu<_a
ziwHVp5OeA<j7xrmdk4yCK&^)2zg!nUk0J255&u)az_U7?-`?&6Wu_X9=T&~kV1E9R
z)f^|lQY-OMnBPf&t@a|=SwPY#u4cRm`MZ&u^*h#VQUjY-^w8$~0bUI<9@>N-v$0<y
z-ua+qw;lTfpi|6g7SyC@q`CeW1h>y!3}X<dNPHaEAGSXuotk8F9M>N<mGHCx_8J`r
z5fAUjV5(aU^pClII4ze&ir)ppCo$3p=|UJs82&lJkpb)(UUxg-s4DgxO%?Du6DWQ;
zHDYUxPN~l5sQkT{c1%>hvAPA#H8%eyQvQA)5%9`kv?nb4R6OhN{z66hTT%X2l)w0Z
zs3?E2FH{cISMIjO)2VW({$Je&P*MK=Cn|qm!Pk7BSz?XQ`fn?OPsH0Y6v4dWGE@Z9
zYnzH-es^tC5lpfBHWk4X%>QdeaOF^a0pEAL5`dj)cw1KlR}R%jir~tjdV^O2P`z7H
z1Xm8#R}R(Jzl06MCJkmGKBoUc5j+!~ks^2v0IoWtnlV%a(<@R03kVg#1U7%}#-B)c
z$`rx0g={mU=x*CGMX=m$D<(E@CBR=1)3s=W!{$$Pw=HZJEJmeyC4k&*8!Cc%jjd~4
z&-nbA02qpvLPhWh_(h6fX+Ez4J~E66Meq#92o=E$5Jm89aD<9rx+6s})xD7-Sa<?*
z7cQ;@;L|Kn1XHssH7O~Ac@MNr|ChtCk|Ovqc>Pxu!Cd8ARRniKK=?nb2&Ph3npsi=
zUjna45&Q%|s0gN;6}kie14S^sB1JG&T%jWPw~QMqf(bsgBKTEiE!O}*5quQ0{<Ml<
z9$5|*!E}Fiir|~6^O9=-pa|w^u}`ZArjRvK1ZM%L2xcQAMKFs96~S~zir{k~wTu+O
zHvmM6;9mnoir|+3B1JHxMT%epBHTz3>;rrPMKIgAbww~kB1JGkqzER66u|_MBA8(7
zir`7*iePHCKD8ov9U4?p1h)ZgOA*XNJpZT&9)pQeQUr6HB1Nza!+${$Ory$`L-psN
zD~lU3k)a3{cc2Iscc2Iscc2KSJ5mJqU@C-)V2+!<2H@`%!3>EM!32>am>^OFGqXq$
z%#cVCOb{u82_i)>L8J&Kh!nvDks_ENQUnu3ieQ3B5lj#%f(ar;FhQgUCWsWl1d$?`
z;O`Z|E6^<1Y@i~TE2na(zDyC!eSnJK2K<i{!CcQ<DuT~P@ZI>6Ct}=)6u~#aFH!{a
zG4}}+!4hq&ieM@Q<r)Aef;o_pBA6gj1QSGxV1h^yOb{u82_i)>L8J&Kh!nvDks_EN
zQUnu3ieQ3B5lj#%f(ar;FhQgUCWsWl1mi<RFhQgUCWsWl1SLgqO}QeNiqlXL%xIsT
zBAB^-0!1*R>1zOj`$ImhBAD~4qzF!-J+9SRrU+&Wx26ad|3DGU*%K;)=`JaPZ$Rou
z5lm201oOFCQUnu~6u}Q5=D$(|^X#T5f*E;>Q|!0GBT@vjP&vi^CLH10`ahgvS5O!F
z{6Xuh@h>{XegIUG@>-UksKdik?5hi${#E!4$nTbY6X4(I6#IVVr`QR$eu|y#jZU!>
zM5ovZKFd?=J?KT(`jF!?0t21JJqq-S?ol|Ky}T2C>h{uCsTk2c3bdoY)q51kUyJTh
zSczECJqk3)T6T}Z7DwcJaFScb6G!Cf{_Kv(Gq>o7Ji$L4k$)bQjE>0f_#bveem+{f
z)g$to*w6>j)A=z07hxGVz4@^L7vU=GKl$wgF2Z0EBX-bS1XYEv^MJpQRy&iWp!o|K
zwH^bU->F9T__mM8r%t{A4~V8QHrJ{;?^Jw9Z|~EMEn7fQFX9%09VEn7iwVa2oKQ)1
z7QqAoX>}sO9&(9FMhzp_Q$S9AnP4wDLf@cnCYUUsNzEkKTXv3u8cnc|@ON9}7M7+d
zDL%wou{PLCse{*J3N=r(xt*x@&IC1WH#zN(Z`0ENb{7y+r=0=NEx=N*F=Q{dy2u@<
z^(=ttZYKb~t(d_~cO&{Vt-f|T!0Z|VzFM4u63T4_G&8-=4)s|h#4zC@+bc7Z2IyeM
zL2wqnLq7ZgXcRkEO@L1#-UTwqkZ;pxT;MYnK11K6&*7%I8YRwFmOV|l9i#i>_KS6R
z@k3A}gK*hM+fww8InN9(b(r1u0FxeJ3N?my0oF2nei%NzZNkmKM~30k+IZKKxxftW
zU$EMbScK#Li%d`FziQZ>*CBk7*`V>VVaGDR#bNsS!+u2E8{&Dx*0B69h57Xkdx>~S
zh!+?g`>_JMndZ|~mVFXB!CZeF+BICtg>4R9PVewVhb%Nq&;;3aAj9A$6L4epH1mwi
z3o=}b`(H;JbL%k8=}~SEM7edC&0FL){O@ubQOd2Oj`=j0=7;^P;Kq`7qkI}nne!~Q
zGs$?rk~={fY|DPmWCNBCz*!q<z^|Hgi9I8v{tpG!pFMI1ru$8B3Cyxl(wc{Z#`Jdm
z1zC+nUyQu{`-t|I%LhB?IwS98=e?~syU+)CSL<drCrI(hK9-%10j^Jih@*=?G3dV8
zy7-fV;%AOpx){VFnUKh5q|Bi;L0sHl!md3vs7%jD8PU_UZHu)lwtJX$xYnH3*Rs1d
zqReAh&ok-y9a+h+CxJ6UYw0o1yb08w=`yI}qe{&S=4!9hVt!DIWyY8%nPyLEj8KLo
z-3V57&qh8>k@Hxo>Rv%r7mSil-aCNHu%@sBSjK*vA`a4}=pbx?#!V><4!Z65nH3IF
zg@aV#AXPX>rt?1bg$f6$!a=HVknjOs;ULBP&axp|nOBR>$j9pm4DWDuO<g><7-*GY
z^CBWT13jVKt@f1?Zg?y4*I1ml@-)sIiG($A#Vc4EpTTQkqCT$1BIN)1#U9(>8Wq;#
zBglT)^t)L{8kgWVKR89*_$QpAeoZa(5>8RSX8EqM*h^KzvP?6e7lFblQv2lE;b9HN
z_okX6?(A6%^pUIDH@5==9eAkya+30DxVOS7QU~OE81+Jk!;(8UJdaq~xI}Wi-4ExA
zMFx?a;Lxp&OC)y@K;sg;240Lyr1nd*W@20-H6wov-83$dnpML%+PH*svY9>?*@$ro
z=M>XneYJ53XN~EQ0<SOXa85OyZzD__mvBzkF|~0C=M2+fCfc}!bGGSR0R-a`%#2Q%
zHn=v3_~sA?#wDC}W_%R<#JGfWx#_VKZCt{^MIBl6r5KlRz$wy|Bd5r@w)~<F=Q`87
z3wdbc63z{#$5I3163$I#{2@SXT*A54Os`>{G%n$6aZ!i!qcBfi)ZyHwk-n(I`LRa&
zq7LVFU7j{B;oPBX78sXs?lR*oC_x*SaBxw_pIP4C7V`X^DW?hyk1PV`_ZnFqFY0h!
zFjJfl+PH-CqDI=dg!7U{+PH-CikV{j0^<_St7d#1%M(tKlZmC5WATb{38yxeA<)Jp
z96y#h8b}+LaIzX{;}T9zBW+y5$!nyIOE`703<pIUmvHJeqHzfexs@50aBxuvy|i%&
zXId;h5DgRK63+fHpFkUzaHhxP;Em<+q7LUk9j1*-I0wai_CwO6aS3Ne%xBr!xP&uP
zBW+y5nHBTfkf$~-;mp=Z8<%jvDH?$=%_(vYkNIPOv~daNNL{+VsKe=v`8y#@8<%jF
z#C*;qZCt`xuFKQLC7cy8pEFP!mvB~Uq>W2Bt2ENaC7h!)(#9p6qczgTC7fe5(#9p6
z<22I7C7hEr(#9p6({xX0;}Xv48foJa&KVkM;}Xu9x(Bs!3Fj;wrj1KDYhylV3yn*V
zPU2c$l~Ln5bS?G~4$orxh;a$$oLHQ}VqC(xD^|~u5aSZgy|H>mwwdlIIAl!+7j-!I
z#p>rXkgN5)FfcGK;ozc<HSiPT63zoK_W%GP5Tc543Fom`J-bzmOE^yifW{@9rvgCZ
z63){Bpm7Q3w*jDW3Fo<3J+~h*F5$cst3RH(J&Vcaz_^5Dy*GRu7?-#i|84fdPWU+9
zf>Y$cxI{ZVg;V6b8LK}40GArG;^Y)LFfKta;S@P<2Y{R+=N%1f2Cu`P^i04hayG~6
zPlBJ#jIIv@15T0iZmj-d_=#}|2b`k&0bGmQh0ULcgA{Oz9B_(+gG5e|1LG2!gLFK4
z$L3GOK?;mZI4~|D93+|=a1wFd{BNQ8JBGX-aEjXC7EY0qjn^}vs?{CX?+iGEQ{)ax
z(XBZ}?%)(xqvjO3tpc=h33rI>UIC}*0;CAu6|5KV?%)oM?+q`T{<nl-0jJ0vS@&Id
z38yGsW?Uj&W?Uk@SR0z4afx)VcGI{-dU*{erErSyk|KA(igAhRw3|bt%Q!{VWyU3{
zKhiO2T%!7;%)w}$7?-I2s6pJ<!lU|Q9f!sxYOeGrFwP?oI@VkzZvZxpOPql8(#(KU
zRI?$w1YU9u`P*UGSBzre8`${frN0WVR2J@b?>M`Fhr2w;z12S5n)c!yUo{B8Qj|w}
zC&&%RzT$y2??j((VL7$axd11Ls-r<oAvjq;K^+F6k9UfI7B!k>o-L0X%80KH>opqL
zOP$k3@xgV7b72FEPhAOj#=F#B3!v+DxlcC~xVIwK6;eq{{gK&zH^Zvf&ay)eH@qta
zB-P6-{VEZlrcvN7NNXiny$yM~i=*kj!Mhf2*E$cssn=0ti}xFQEZVAzd^k_Hp>AWv
z9&u>F!crHr$VZ*I0Ji!K!6s)7KvL~Q@R)$K+MW47?p%S8jJlp7PdK*$<WvX2lg>i`
z4eAR7PdP6F6i|^Lpdz)b6U)-4!8x)B*%=<qEYxQ(Jf_1fW6#1%2gilU9>zH$jKgY(
zr_7x20Qy-B=2T+E!ZaJgG^}9g`IFF-6_vtJgH3Q3uV>#p)69-4zQe|B&hurmIE(JT
zio0+=<0OIu+k@FLt)>on?q-0YIwZ9_EFdH^IeUHveg2af=(sx3Fc|8>(*Wv4_$iha
zG7UZ>k=)aZ|FC;Y#Gg~}C-W(=w2&E?UjZ+%w2&#Yw2<k@Go@Hs$PCwRT3X0-YBwz{
zWJYK=EiGh5YBwz{WJYN>EiGiaw0k4koY_vhNwCR`)@~APGGny6nR$*C_du>kb5d0z
zKK2)uJ?JBJgSlrFhdL2I71x>%{3H6)oZ=_q<DhvM_-CR6-9&sEQ5^L#4+fe}<PyzA
zPLqimh~^_~D$%8wDrPT^w~i;`S~Hh=iTFgKA&j{i>AHaifA1Ec6@B}R8x)F)pRC1O
z$cn>y=$+%7qojSvP{y0ySH#254Gg97ef%))^uE<m+%ws#9d+DqA};5JxqgC<3w_3p
zVcg!KysLYszJa=9nbB6yVg~4><B?QLuaAwA4v4DMehZ@x?3>iZt}=$4z+zwPW3o4w
z4Y2G7FdXLkKOpTePAUY|Fo<`;_hs5Q`p7Ip^V<7d4*X__=e6I?tlkQ7Z~KoK|Ls0O
zJr@{53fPRyd-|B%v)WOXZemL|EbE@Itlpt3(Bk|0$i5{#xt@8g)k*FCmfa%NToff;
z+b6H9xj>Sh6D1wWi@VQ_DrF4$Gjr<gBV)3$7*^sc<fO;1w~wnkNB8rRu>Kg%r<gRM
zlm4t=*?*BC`Z!9O=p#D-)DuJJ&cjvceWSD;Nt6U_f-!W(VW>~Gk8A;=b{O&zbG;{F
za%=f<vt=ixY149Hh3-kDb%hpmq)}*Bl*<!|AeUt_Bc4p8nT5`D4l`YykXFuXg7!@^
z{dtt>>L}A;8;+Bxbvp69VKs*d9>k|9hP~r%Bp(+Qx-QYk-3x;vg?=NE*716w7F@?d
z57vd+NHrU&%=KO1&9u&0j_c+RPNel9^$wF8?GH{g@mm@FHSB{MCFwAY=jow1I5AGQ
zyhqBKm58SNkR*#*YDxQM)>-xj?1tw0?Z98rMJ=_mx~OTosHN6Go%K{*)KaTU<H@?H
zrPi*xsP6X5S(UF_)j?I-=N${Y)(Z4qv-Jp`Z3T04!SIVv{8%*OHMA3fOAYf1tD(G)
zzH3EFrs0$8E&E+Wu0l=Q`OG&rS+!gT=xL*)w*eX-fc7~INhE@hneB^-`y}Ko0=Lnl
zuTNnId=QrocqE6z>N3EuL>=%!+zr;P?tl;Cjk-azbq9P9Z`XLH?tl;CJL(RYt~=nv
zcuI#a8{U<-?D448gUDPr(6_?*D+80Yf=K|?=w*n!noYRsi>TlpmKSs*s(ch1u}4s4
zKRoS!7RVvP_F!xFi2J<s812)2yjMKvV?F$n<Kgh@U2NYlxVQZ*CjWeh7qq`cykCfC
zx64j8Bd&Ch%<I^gjaDOu>->1onwkHHy*GiAqbk?NtGa9Ls_O2U?yi|6lgwn6WHOoT
z3kifUS%3fmf&_@N1VVy@HHHxOfNY|;5U*Deqq6BmP(cI*QNe}f0*VR(%5sAw5cWU-
zK?(ey=RLJGWDxH1|GxV<^ZQlJdCq=LojQH$dEfIMd>{UbNqh3v$*3SO2G#ATAo>We
zZBKqYr!LNYGLQD=(|PpkY+NyK@@?ow+69u9CMHz>7W1-t!rR${*}I%~)N6xT<v^DB
z_na(B7u5{scari5EE~H~xxeRR0fBd<`<UerC;vS+RHZz!n^pRIt|xv)knPr7+(kVr
zm#xzDw{!9<$thvfCKmH@PAXVNF>3PtB8!pVt(SAMl;UhVau(x0k+bft8qQp)&QFqf
zPvoLW4)IQ6y!~=|xnej!l>xZR&^W*Sa?$VLp{lbE$VHvCs@J#)$ri<U#n=@{t|7U4
z?5E`hsa`%t4SRfZbH&Q3=psaHLw(dJ{9G=2Zb!mv)I!!}T25zo+}0RB01DXE581R_
z^g^sqGu*UXiy992#o+Ju_Bl`WBp%6f<~2)~ye=r=^_JPiff!%qHA{~kN;F%}(mSG;
zO*LVT9*tc5kR6YwG*_49I3D8ImIl@JstH%=@k{}Y&xtIxN4KV-L^XW+SmNs(Sv`7}
z>V#G5b?(u3P_xDgZNdwT@OT5mR}>BBE_q<rA?ZY!Wgj1>VlJH|Ijyg#jE<bt!^iNK
zXr5a&>3(MOmm%tXT`~5j$f^%nP5Ki3{}xR}$3RS9V7ec;>@5wEF!SRr`7_F!ERFqP
z)Yetnlt-ELQW<jV1NG?ibyI&y-_KhVZ}&>tiTwP~KR-kb?2|R^0IaqQ?TSAoBJs&6
z65rR_m$2aK#Q)xp4~WDEMB)P?aeM&{nB~BHFdz~i5Q#%*IbfD!KqUT8A`;J@z3^T!
zI1SN33_b(@Vlg<q`W1sOMPR>TaEfI56@ycx@Q=md6j~=@@T~x`7@Y1z3{F5XIE6g1
z7@ReW#o!_mkHp}NlZwGV1EESH24{Wy6N7&dVW}9LF;g)(GfBnZmjFQw&M0&WO$sqM
z@zpWTh`~p~FA;;YlvE7vK^&Bb!Byq9Ee8KF@<_$tEHxtr|21GL20x8?{#V7|EH4#<
zvt}7Fcr!{!#o*7eybmG<=XglP;6$kyoG2B8vwayc_ysI45rZ#>NGuV96QpAB<AG8!
zI8iDFCrZWOM5!2@4<!|Y6HyHQ28w-`7@S_I7<>>o=|l`p(4QEbVW}8gwLBJsv$RwU
zPLztlTS<CXZpF_R#o$D#7@T7FR18jmd4FPXiqcXsIG=1P24{Jx7@W^J6@wF{VsN5V
z3{I4a!HH5aI8iDFCrZWOM5!2@J&}sRiBd5*Q7Q&!52j*phNWU~juwi+X_}^FoQ)?7
zxfuLlpBJf0249Fo49?(049<KKF*qYTOm`d{@=j;O;D<1fZ|j9|U`7mn8vGJ5__qK`
z2BRioa5g#-gA0ho-~wVXxPVv;E+7_zbNWfd;3qP-$1&I_2A62D7+myB*b5WzLHr&u
zcpE$uG58(;B}0@aVlg<q5;3@dSPV|!@OA+%>6wfe{A30)qi@B588P_3!Y>hn-wIGN
zI9)irC1)~Z#Ncu!Lo5bYXEIRH#o^5?M}=p^;BqEIEC!e6Q!ij#91~*jR=5)}I0Hls
zekL5T7@Y1z49@o<5rY#XVsMU?NDTf3q>yfiOlv?4PP-ot{jZ6`QZYEC<NsMPI0xl6
z#o#{VUjM^l@YN_nnwg5hkAT<kTMSHeJtBA9rbxV+6^U2Zq$2TZRwQ1{io~l~k$5#L
z60c@O;?=B3yqXn>S3iJAyqXn>S2H5<YE~p(&5FdUS&?`(D-y46LnL0!h{UV!6^U0f
zBJpZgBwo#m#H(46cr_~$uVzK!)vQRoniYvxvm){8|8|jhH6s$QW<=uEj7Yqi6^U1~
zBJpY@67SlR#N;BO8)KqSUpHczrhiQQa%({?f~M4R+BJ`mTKws9@VfBWKVldA5T>8?
z1Vp)p_A`kwaz54*Yog$rKt3J{n)>*oJ`nksA2m+X@_P?j$Px{EdrS~H$9xr&V$QL7
zmP~#O$m#rD!ysnW48vT0+$zS~N#YrYU>?n%jh_T#N^l|~<R6;GAGqQyy1z$vn{wYn
zcdv3EO!w5%B*wX!?(IcyHGeVPJ1X~&wu5^&<*w3yQI-5~{%*RLmcLK;gDBiwDS4W&
zV>Yms=}o62z%tBl=XXRG*yp0>%&Yt&-H$W&cPjK(U*LPf<uZO=D>&vA?k9k~jhN)j
zZ`o{%=G}ywd9^tN0fv^p9YvVe<e4mgKHb+2`3xfXM*h33?1NI-z*sRF;WSfXcQ-Ca
zc>YhQvh#`Rm+8Ki?$x!+;Vv3?BBz{g{T$My65aWmkdO1VM*g7Y?`6#IHNH;wV!D6O
z_!GKsq5H<hJLtZI?wcF`KzB&@ZyKMa`}@r250wj%XZd@`-7S|Ufp#w%zo5^02u9tv
zisI%uIPO-T%`H<^$=zBNcMXr%-P$7VYZ2(aBXRP#*6^zp%3x_|#TaQWjB_4A*52pP
zZ-ogJy0yl|M{9+N(uamO2C)hgJ?7+iSC1f&B7AQ)$}UVCB4so#K3OYF@}5BQD(d-3
z{C7^o?PXl@jG!&G5tZ*OZ0D@PL-lk76sEgOjEB|)u)P4oJ1+#-L4f1+vRX3)_})qQ
zu_){)pzMtWd0&_*pz005*eL8IpxHZ$pie-HcMY?iC7?~KtV7X`UfA8anRU2=VS5zl
z*1S)l#|raZg0remql*iB71#nzukOlD+eeV0YtE<9j(<lqX;-UOdGu$Rb`iF1IzH;B
zI`WW4x;5_|R&ue$RvKPA)Wiyhxs3>MJl3SJWElJ60(2PjgTetmr*TCY7maR!T0<X-
zcM2yu`v7@&<25d<ZlGK9Iv_(XoTRcxCcW@$;0c097M^sjz_@8#yh1B%Xq3o}i&tue
zjq0H`E<Q;sJSA?&o5Qwd>D|I6cM@_cHZERrgjRT_VHC<Ld(W~d&q|tRZxkQ>%LVpC
zi#PcUfGtC7XkME)VGY1*L+1i?df(@hcq2FxpxZm~Y=Af2vjKV=7oWI9E4(FHj|V_C
zw@Njq0id35OF1*bJ^A=`z2O2R>I?sl;tDyv;bNdUO^c5~7N#zF%nh%=D^qZENjE>d
zhP80@!uQdR1>q}@Di(ab@fYZlh2c??fy%mn269^zp2QLw^&%&agTg*^UZJAPaKYIz
zd~QrMNN#NHAii~j=#T!s7eOTk4d#}HPNVQx&S5WvmqQ!0@E<v;j22!Aufm3$_bUDy
z;jcK(Hsq>APPi|N-;f(d<cEJ_A3v3In14CElW*SBIp<Y$b~T)XFSo+8D$nuZ$y0%z
z%Z1eMpBzqMwO>$S)4~Ip?xkE|Fnni(HfEi|D>-?y`$8Abvam(PoEx?=-K#2WUidH;
z#)a2%Rr<~kk3&NXZ>X3H!q4)7znOE{{DtA&`vJA&?fc-nXb8uDp)FtGke{ayIgZ5-
z&o^>N&)0`6W6G|)KLNQyKX)<<>B*OGM1!G}dp}xQ=*<^)MCkK5^eKm}^!s!~$n?9w
zsNa8!N|fkPG=|{boCD?<%S5MF{FruU946(^OXDE*aqti_mm^BvI#4fsi>`_>e=#tv
z7Cx#EJ^;;YDdNfcg~ht_B4UIxX&$CG5NKhAO<SUdpb>5+I$W2h?w~9-xM(ormTzMS
z6bq;6&LjuPF6K*ey52~jh4*n@JVPNXJc4uK8ohCQ1o@i7e{&Ems_M{t3tMycB6M*0
z3ZLscxn}+xYT;B?S<5%_X&E7vateCB%!p3d!<e~z6KCema4l<@&zIOe^TG=_8jXDK
z5}^4Z?b$&UZSdbv=Y`=aP7_u><cqR2v^k1xg^mfAGo7Q*s<44gaP#FOQQqm{dXBL|
zzD)bO=Z3Fw%Jo!v>%z^P1bvn6((t1!FHq>Ja1)zeROq@eU<oCKZVI1ei^>Y!7GBD?
ztsyUO&0U(qUt$(5ois>c7B1LU_<|TWX+t*`!n}PgJVNeoDqw#TffjOqQvv&%ZUw^r
zCQhPsN;X3^+1$<XAK_t}3)tVpSGARsK>_=l_@r97zo~%zO)OEBZJ<LWQM1-|B|M7;
zeTMUGmB9&*65K_Dzs1A(+Qb8SJMkWYyTfs`CmfPdPHX=PXNT|Rn>ZV_UqtY|{LniA
z%2ZDFlyY*J%E{h$YJAuZ$Ho`p9CWSx3~K9rx9LoHHB4QA(clkp&d00l1z4E)LkrI#
zzUJ*kFsyJtK+fwVXf2dbPs8gaX!C{uINnTx;f24l@!n8^_Cg*ZzV{b`4#}<Pz4AkV
z&cc5nTG`u~ArlK<2dH{02qw9+P-cr~5KNYkHt$q|DH77{{eobsg!Fpn5^N_SlfBFE
zd*DwCZbWX=yuT4l_rC)$!}~m=Z7*%>(;SxYWi(SdQrGgEMuS4`9`Y4L&A$Y9acnb#
zJAQ~;(O}P&58M-rf;pwz#pnCDJ3FC|AB3Y*E8T;CWh#7@hIP`b{40#{QmgcNo@Yvx
zN6D_Q{6QUX_ll-(o?FGrW11Es_bv~^u6zZCw7!>GvT=)7!^{>=oDCJ0*3jo11R&gY
z!>l6Rira3OEx<rUd4OyFh51+lY(MxoxEnlFy1Q{t=VbuzGGy7fSDBHNQg7qlWzMIL
z_sVGqS>P@~`M$UMY=C{-lK{%z6#U9Je#HGUK-HUw-`B={-5UX#y>Wd23*83*TD-Ss
z0_^9$3ee^)`#iw@ZUrxIr`GVVsE*$_yG)X(ap|(vTH{=wZd3swjXV3j0EYJ(!7kEv
z&YMe6$)d3Z4bQJ;$gX)dLFV&=5Py)|l3$1TRhfvOqA?S9iOD8NOn4p{d$K7idG<&B
zj5wH$dspsAy)F)Bb5$@0MO^MJaqx>tFkMK<lYEQDpW|@$NhUeh76|?ug7f#|NmSH6
z!94c~R@6Sh68W1v_X$?iKEXWq30C%PmSHm+f%O8C{CUW;a)A6Kls}2tySi^#23HxQ
zvwGm5CUj$&Vvg$KMvjD*jrbuNU&C&{SCLn^3&vy(yZu<I79NW_)v()-^)$jN?ltW8
z;}Jkkcs@pT4ZHmqvk*RrUxpfX`!N$Q9EvK|u-nf--Vk#z3Z2okCAb>nNX${gZojpN
zCt{8ocKflEmg~_Gy*2FiI}y=CS`e>cx1XvU#T+&4_EVMnJrQ>M4M#*Lya97z4ZHnV
zY9!{UVYlB{z?RX-rCP&oKejxin4^Z>e)1?nYIoPL+fU`m-F`Lf_9Jq_5@TYwACZqE
zAAzvjkL8uaYBLaa`>|$`n4^Z>erL11&B$|d4ZHpJLm!0{bJVcgPnE~rel_g&Q{}yY
z)HUq(<5P9Qd)TGe?MLK?N3wM6_9H6eR6QW<_G9}ZF-Hx%{a#^tBIc-Jx8MCNj{~rV
z-F^gGI0F%C*zNZxAS1j3UN!9YBXYu4K3?qhBl5#CA3b*a5tYMZnG1IN@u5`1R*ah(
zcKZ>97{5ypr)aPZ_})hlcKgw*Wj5yiV`|v#cMfKr@HdzeYuN2apoQOOPh+>AYB_iN
z)v()-VNQ5G@~vUFpK3Y995w9rV`=4(Kaw@<_9JQx&*yW-Zof|>T{WbbqXsbtQFC}T
z%foKJF95ZKm*5SmVYlDE0=0!*EDyW=SbAqT9)30K_WK(CcZUzLbnN!ylkE*XK3VMc
zV|io4$Jy`L?Z@XlKKw3+Id=OIO$fQ#sA0Ds(Zujg_B3|;5lsp;bVm)l{fH)qw4z*t
z<{{CP@L!0q+mC2!xRuWYyZwl^3tKo^u-lJ4F)chvUO9zkghloXcKb1`FFcAdvD=S5
zI5&KRZwhw%F>GGg%b3{h$I&t$Pm0!-i^lUPw`lM^EE?>iqQMtJ#2hv3_G56nfwfT$
zyZx9?`|WHzcKb21!*mbBA@B4KTDwdD*zI>01NpYT76(?ecJlT$?DpFTzxF5CUhMWO
zVFci}6+!KX@=;;89~<5N@3_^l+fM++95w9r6F@OX4PO%iDCVePx1RutIcoT@;PlhJ
z8yk<^ew6sMKhFMym_wpb%u&N`zr7IRuou3DI*j1z`5j$rznG21ZokjKv;97fGwk-e
zQEJJb&UXH4)v()-UhO4D#%@0W6m!(D+mFEE?G;?oGgYnq<LrIx_WKJ1nGv^%NT8{;
zAJ3H7?e`7>+hsPuZa?k^DH@zE9Nu<{<D;98XA7{~ZyfyEDdwnQx8Fx4{(mq&Z^y^+
z(etz*Uc+v`#f(oeM-99Er1_NTeKn5xj#m0KW6*+l4ZHmqQ0NZ3+-KkrF-JHepj(MK
z!jS>r2PNhRy9FpQM>tAmD2O?@Ab%4nq@_c(Ja_wrJ^5?k<<P%|mP?qcl`lZX;l#l_
zbJpQ+crP5CTKPNkVb$-%(r}>i+jL(jKUw7)>0Ybc-Fw1)vCc7B{s#RoE4_n}F>=*S
z_+^}Jo`{@ZrCuj$qp$lda_Z);wcKoBvv8){sKbw43OI}rVGgWkG}Lu-bA7Hapi$e)
z-FCU1{aF%vWN-B%z+L>yQ37@9$4p1*`hsRI6G`CCKs0@w_97}{XrmubG)%vUBJm)!
z=5E7rP?Nik1<9*O*}NiU^NPI9JBpjttsi5)%InUJ{FgH?LN)R^dnHD8-Z0-paY#qf
zH?P=UgJf=QO3;Nu43f6_-r~V@lWfhe6t|GA2FTW41XxD?+xgq!5VAFYmH%bBNw(&{
zQ=z{mI^2JR!)1Jut@$flT8I&{HUBM}Wht^Xf3<l9+=gb5Y|USjXEK9iYyR3HE8+GH
zgA}A04q6Hn2nG2*8m7_;p&-qP9)Y4D&52b4MM0VqhY*yDpdigj-kIoCnxNy4m{Y;+
z3%I1_C{HLzb33OILr^G4bGpmKih?w^7oaFea|Z#6f;49cP!y!OqX0!gnll9`3ewz3
zfTAGHJ^_k?G-nBD)5?m1G<SCnU>!(7ntS}`HB9+LTD7vGAkBlFtC=Zj3G<Lfx)lX!
zF1FZ8MM0W}xz`~?QIO`6VeE?w&|x2^=WV$0k`8Ny?;QY*fl!d<iDKkKC`fa)D1s{r
z(mY9JkLdGIOdu4b`J^)ozeGh)kmiQQmyiwID>ZYY3>Tva3etQ^+=_yPhUwmj<9pZR
z6)`snC>BXUn$I-ciR6lcG@q3;ih?v>F3|jhq9DyJLvJ@@3etRS=&JyVf;8U<nz0~I
z6r}m4I}xC_ND9(?OR^phfNE})YEA<{J>QmcW>ofMXM%#9hD3c8QjjJn$az3>s-z%I
zP>`(N+zKg36BH!7dVYlzqzMWV|Fi`aQjjJn$i?WAg%wheCMZY~xh<-Yf;2%v)*D@7
zE=#o<|1nW0H?~&x1cdZQfAhz_i9yYZf;2%va*sfT6r>3XQsPxeL7Jc-uSB(t3MojS
zDv?tm1qn2a$ghxsG(kZ!UAaOE(gX#0C4RZ86;hBUC`g8luaJT?K|$V(u*nrtkR~Wd
zhE1!Gf;2%v-i@#s6;hBUD9BS#`@RY(ND~w!W6rIRY&1bZGHhOj6r>3Xk_L3=S4csc
zpdcA@L4_2g2?~<UTUa3lX@Y{JiJ3)%IQ~sgkR0;!^g*N`O;C^=()0B}q##XDkWV1)
zqq#x+k~Tp>E<<zH=LX%6+)YrBFCY{YWXZT01>}`jr-|;8!GSDKf*Xf2PeNc9(j(4o
z2x_7S&V$Ci_8Itc)McX6D}Hc)W1KE{a4@EEka`$AWXk0jllKs$<UGV&6l2tvq@)Q_
z@-?(@u#l1_NXc&?Mn&F!kdg#ig`}hjQj$d(6_S!BNJ)9}D2rWyUCX!+7E;m#DfuKb
zAt`BslqAq9_n{OMq$H75At`Bsl-wUdASL;arhKBR4!PF^De0gyD<maNkdnQKp;bsq
znjj_l{EP}oNfV?bBRUn5k|sz=&efe2l9JRgWu50$NJ^R@C65N0Um+=Jf|UH9IQWg_
zt*elfG(k%8b-c7fQqlw|Npw|(q@)Q_lIXfhz?y-SB)X|WQqlw|NpxF<q@)Q_l6iuZ
z<T#?;VCf`~lEmFH1}RBQ6G#%?qz&0@f|MjJ^Z|`7v5P@U@*m#_$z~|NI6supC8loH
zhFyt&CF2HU)5`Z(1}8jjg}Y?%J#FQS6c6O5#rr|r9gd@|a6}`ajijUrQj+si8%aqM
zq~tOHgG87$N-P{1B*LuT)Mk=3rfDf^Fnk=|TCs0r&up0ww^Ho1`<zt(LVnq^igYXT
z%bqQOik*E-N%G6te(?EBDdd;4r?QO1g}1X;nUNIv<?LPNd#lJVXMuYvrX)pvIs3Sz
zNEP|ze8l}efFi$~ecj&xDDul$=spji$S-F<w*k|SBEOvd-SGgOS|H??GrK$!5sM_h
zoVh;Tiu`hR_U8g9^2^!9??M1K(w~Y-Mkm~p{Bm~9Q{W@>#ws{Mxh1nu{7803P|4Uo
zj>#rSOn9CZd$K7iIp4=P<-f+kY}~tYM{4=ZVBOeU6-*STzCTWFq0K6oE+q8vZx~tS
zlJQC$i5-*4gFkHurp*^Iu{8@0=oU}KzYg-LFtJ6i4)UomvBh#lmAJ5%8b)Nw3VVyY
z=_t5GmAJ4^Gp8r9s8!fkOlA%L6aw>xF=#gaImY3b=nOJtg#%=s>L63*?OW#P>mXC+
z9XN<a@H@zqd5ar4Y?MN<52kFok2jP|nGdFnr7DGBzs@d}52lQIgGwRT2UEtFN+H+>
zQ^rh`La+~}Y&Re<WsE{+^ezehXpAGK%m-6Oj#-#8A50lbQ3}C6n6jTBx+nzuV9HeG
z$dvhYcCmagWk(>QQV90Jl(E!^Df7XUodBp5f_*S$J($)+A=t08i{;nZ#q#UyV)=D;
zv3xLPEKex}`(Vmgvxq74!Ia&}@`Ne#!IWLX^2n6=b#}4*I=fgtm@+<9r4a0cDI-z}
z!9JKWBBc=QgDGSCBBsm-Q??ySPzu35n6hR}>7o$qgDE3W3c)^@vSC0<A=n2~Mx+#i
zeK2K2N+H+>Q%0l|f_*S$d?-pG*auTaM1|mgL$Mi!U>{5wy_7<*52oxc3`|i7_Q8}9
zD1~6Z&MuY@ri@`qA=n2~rdm#>%m-7((v(8552lPrDFpjq%6^M<N+H+>Q%0l|f_*S$
z4*)5JU>{7`pMjJ@un(q;FRHSO<%20(k1(YW?1L%elT`}AKA19=rxb#HFlBtsN+H+>
zQ%0l|f_*S$L`osp2UA9*6oP#)WkgCL*auTaq!faEFl9taA=n2~Mx+#ieK2M038fJ1
z!!8z)QV90Jlo2U~U>{5wdr&C^`(Vl#rWAsGFl8JqR0#eyd}CW!d=E<o`>15_g%GC9
z2U8}7hRBrpV9J<}C<Oap${5*Ux}jKm%R9Y;)<&kx2U8Z{zr(kc-|-R{DFpjq%6i}@
z3c)^@vV{O8gHc5x*auU_MvFqQ52j22nKB<tnE*0nKA18AWXgOnWdg{Q`C!U8{fI)a
z52ox8=0>K>2U8}|$dvhD%Kil*4trre>d@JXC}7Ik$dvhD%I;$=$&~qE%Kj#`d<sn#
zyI4M$GJ1(Zun(q80GTo$Oc{a0+jdxKN#i4hU>{7`NccI-Xki>^;_N)81XDH_exeZU
zgDE=>pk#2maCkd6j*o68Q|5yyTgCYN3G=~}(bh}J=;T|>+YNF2NFmq<Q+6felPUAT
zlu7efqxtlZYC<9Sw~Rri%m-7(fI@fB<&MPyLzuE)L_oJ<%7T#r-v`B%1>FJ^Qx=Sp
z87fi;o{1Eaf20r`^yD`qXNUeDi^E*4;{s$HOdPyByd3`Ee*%tnt%FQi@x;;*KpkYt
ziWkaHRtK4~;#%b<Q&zlK=a}puQ&zmJ#M3UiuEv+QKDEGQNz6|{u~DoVOzq+-13cKs
z&!e~WX|i^~CjRbYmcb(W_60dDgXYZ-#V?GZ?YBN*yzYt^ueMQ!^DyfC;_?3zj8{Ix
zco`YS%g8WZX2N(G8OF=VFkVK#jF*vNyo@a4Wz;cVMuzb+>KHF8%XnGi9Im5<sIex<
zw=c+%qcv-y`c4zZ%gQodR+jOyGK`n?K^QM9!+2R)#>>hwURIXzva*bqm1VrFEaPQm
z880i#cv<gaysQl4Wn~#JYrab=?5qYV-C27<{R*Q*Z=lkhwT~bw-SJn4pY!r+B#f7p
zVZ5v?<7H(TFDuJ<Ss#M&vNDX9m1VrFZ82U}%6M5B#>>huURIXzva*bqm1VrFEaPQm
z880i#cv)G-%gQodR+jOyvW%CNWxT8`<7H(TFRPC6vg#NwtB&!q>KHGpj`6bU7%!`i
z@v`a|FAGX{T+)Ad#>>hwURE9BWz{iWKpDmhD8qPJb&Qu)$9P$FjF(l%cv*FfmsQ7j
zS#^w;RmXT)b&Qu)$9P$FjF(l%cv*FfmsQVrS@n#URnK@?^^BMGzmf5>>KHF8%XnFJ
zjF(l%cv<hmcv)G-%c^6%tUAWadLPEi$}(P79ph!yF<w?3<7L$`URE9B1+h$q@v`a|
zFAHjTWSN#$sD@`j4Ug!U3f1r|sNoT<s!$Ejf*Kxar_(Fz@uO}*4UeSLxfQD6Sy02{
zE2kJQtB&!q>KHGpj`6bU7%!`i@v{C4jF**VysSDi<JLCJjQ67I+hV+|teJ5uYi8Vf
zubFXX^54yPSy{%*iWo1UG}^Jq8m=`p;a@u`4SQH8z1m4>*b${cX3WVjV@`${a}+by
zaR3qtGv>~0ApxeCF}KfI2O!LtJF7^yV#eIr0?3R}FH)GX!uEr|&y>Q974~$fW+-Z5
zg}p>?Q!!(OEHhSE;9ibciWw{H<I1*PQ41@4#C;GUiWw{H>%In{n6bh_w~9rtV#W&l
zxzhm@GgjE&T?7y_V};q}Balj%vBF%RZpDlhcJ_|}P|R2%WyUT??Muc^Y!8{S!mfEX
zL1>|MaD;Mu4>PtBK_z2N9Ft9unDD$R_GD93@+>p<vpATIdspsA{b(G_=Bi-6TQM{C
z_c(ZL5=<8oPR75885<0zG=LqG$s=OMc7kubd43+!#x~^XP8l!QkWUyd*pMfa+QBc;
zZ7^Q2A<yyOPR7gMx6D!1PR7eWaM0m&lkxHwH*(A<#w*A&UO^q>71S|aK^@~2)G=N`
z9pe>zIL0f;GG0L);}v8Xub__c3hEfIppNkh>KU(~j`0ezj8{;{cm;KgS5U`z1$B&9
zP{()$^^8|g$9M%<#w(~}yn;H$E2v|<AlA+>UO^q>71T3cK^@~2WEroZj`0fW7_Xp?
z@e1k~ub__c3hEfIpnt|IsAIf>EaMf_F<wC(;}z5~UO^q>71S|aK^@~2)G=N`9pe?$
zF<wC(;}z5~UO^q>71S|aK^@~2)G=N`9pe?$F<wC(;}z5~UO^q>71S|aK^@~2)G=N`
z9pe?$F<wC(;}z5~UcrZ9yn-y_6=WH&;Qbh{;Qbh{Aj^0K?`6D#EaMeq8LuGAcm-L;
zE66flL6-3fvW!=dWxRs-WxRqc;}yJ@@d~nxSCD1Ag7;&*g7;&*f-K_|{A0!|$TD8R
zKW4mwEaMgYL&hse7_VZ6@hWB+uVR+*DrOn4;`=gQ#ceZQ?HAz3su(d|{2?dfHC$^a
z<5g0OS34Q6(uMMq)lSB%v{t#vc$F06)lSB%bXjQ+{H%37CXAQKpX!*O($`JE@8JlF
z==7<Bxe$SV*U07Iyb4SL&TAwMBTpBm1|~1NZ(<$?<{kjQHHt~+!O@Hi^}c-1?!dXV
zNA=K9ILNcnaaiyE;;|gj#ykzyEVs)j)*(Okgk{G9%px^6?zpuG*mW>j!|}^juGDh7
zxnyKD?FDclhW6ZF5{_-b&1ez=#t&mK3|FrFU|WYNV9u$12ix2_Y}|JX*loi{dHG5B
zm<M<mMV)DV>8B{gYKPW^Zk6E9S&u`<BX4~fp@uaHchf4t$Fgq5-L`Iqk7MnI_^!1H
z{Z+6wB4^J!3U}W+2lv3*2QiD*)yS=6y#aUGYKMP=bt=*}TJzzqSOMHsYcfJ>*8PYX
zYIdYN_bvG4_wQtn8lw<m8#7t!LoEKYPC=+<eII$~TD18&|2O27U(zLdVml+!QMg=^
zPcBzfa)TU<O`OntI=s#NK`_eg8T-KPAB!UNTXc5G8+hIqBZa>1yFkGYQIvkm3}(cg
z;Ke-|bFRevH555kNz9;6e0x|D#zjdI?cyo8s`Pc{u}fqM7{lWd3_L^o<CA>g*NjB*
zpJGpr$5@LVxN!nWRoT=Htw7o09q$1bHA3uC{;`Rolp0}9sS)Os8X?pVsYaL#0NFGi
zs}c61g8xvBkVE&ws1eFgf3F%L%lg1-gn==LJ*?Dpigafc3rn$L;e`lL`fw9uJGE8@
z&1z1xrCqUNAwi;8NRTKN5|qnIv2ZQ2s%n8T0soyY+%Cf<q!mW&Mz}knSlEe=?pU#q
zi4(;_f<&>9AW<wNNE8bR62(G-M6r+{Q7j}#6blL3w1z~na5?J`DHhVL_BNaIU4pY3
zNwb=J71#nzZzRoX?jtCsSx-SUX;-V(kSG@Zl$l0~g>)y1g)BW$Ec_)x62(IH#Rcdv
z=I8tYH(pW3f$=avr4%a`>i7hX6$|N36bmJLWWraY6e||)3xRN1DHclPvQjLRxMihS
zNca0F7M3H$!at!FiDDtsd;rBl9srgo7FM9vk|-9A0q8A9iiOO2Jb)+`vYOKXM6r<N
z%&5kSg_Dq|uNo^BQpaviEmkaK9&@X)Vj<JbuhuCRR%6A&PoPT{R_hcCt96Qn)js@`
znV?yj%Tg`mKPGCD8^1A|IA@7YF#7v+1Qi*SQ7oi-Wi?hTWO}U{D;9ne)i$cJVj+=J
zjTH-t{A#RN$aLlEotSZ`Solo`nN-<mDi$(qd^J`qqz2ODYOGkuuxZr;nGQ7T?FgGu
zjTH;|miJX-#X`oME4!GfSjez>)mX9c9;BOJjTH+Sb3rv$EM)T+R%6A&QxP*&EaZ^S
zC>C-^XA}z`Mcj;H;h|_wMzL@cLZMg~7#z0J@8l&i{VtGoL7X;JA`lJ2@H6n>@XExb
zSNw!tLne|NM_n2RsRzMBGzQtP^1?+Lg!{%AofvBn+8CLs2H{r`qZ(@v5<o@3M{Mw^
zte{biH3;Pqqb#-+EyF$4Abgye#2SPIS~b=nB(kd8&>(yf0Z~<z24Nn(R*f|XyO0Nt
z?|>YX8iagMMm5$TWJISLYY=i$?ySZdgsk(tYMlmQHP#^f7D`-L<+f%s=2NTWQ_Yx9
zt&&eQV?MP?KGg)DT0wcISIMWE;8Qz*&aIM9HNmH{ymi$&4Z>=j24S^MgRoksL0GNR
zAgsn3gv=8fg#3wP(b7rKAS7ntf}uf3%q`@CV-3QO!K2D;%{;b|K&!^bHXa3pZOxpR
z=#*sOQ`yrT`Vm$dgnUbrV;lLTl4BcX)4G&>ZJa3LQv-uOt$a~saAK7F1n$7#3)#vy
zCLYLt5%1sQ?r<Ev0f&^H(-I9rPDF_YA<ck@T}tcNB8Niz2CRl`gEhBJYYx^*9S_4t
z>$sPTw~k-op3^!X!#`_3lf8LSkKusZ!isGzB6l4D3HG!yf1K|6wXXdV*N7_-gJC1}
zh5GoB`hNK>`ofX={&XLpW8Kw#0&?SJ2d4J8tj?OBN>*p?&(Q+JS`@9$-hq{mfz=sD
zp%Q`*tj-2jXL#Ag^2|23eGIJ5I86<#&IVRz1FN%v)mgkA`d_*_n}gMmb)YP~uEVm*
zmxUK?&33F<h11KX58^!c23B3K;_ARzMB5knK{WJsT^od}^QTBeGu&PJLN3F)WHq*5
z7gu9lSdDFu1)#wqJ|;zQ<)(^Y8fG`K!t7=vtC`G>b)cQ_G&|<AKl2%}1uHsU*7eqi
zt@zK&`hle}zM<{7DOuqi6s_=9L@PY+q=6OQ0RM(HjgF1I1N<8{_HqF;u)@P9PpsxR
zz`t>0?*RWM)CR`I0RJ|?zx}_#zsYIpcDdApRZ?J(ksH1qtg8K%uyey{qS)T*^9Nx#
zO%&T(tKz1KVtZ?gxUWT^{f@+G{}trJ))5w$eUoLacpEb4IO0O^byGaX{y3I#hjS_S
z0HQGPT3lGp<<7!=KhSd{HY4EP#1k~$9$2sOa(rv#FOfelyV24<k4T1gEQr@guzGp4
zusbVS*o{4f3p<gh=C7XyBJtrS+%-eVS`8&+HI%IuLkU?8C1f>}kkwE^Rv6x<kQM2+
zN3)H{GB<6tL_1gVwAF&0E6b6)7{<oV6}rV%OAb3%Sgd7W=gRNl5L+$SxpFz(wAF&0
zEA-c#g}6O|%Vm7pYQfGG6OTk}wY+=h3cEcrjE$WuOeTi0v2$e&+`bVQT}X;{(ZqF;
zZZRMY8gB){6B>`k5@R7N-La6BjI1&s{g17;L_$`v{)kbuBeHQQY5g89X-h`PIv!MQ
zEM#RFiI7zlNCVRUL)KeTAuCNo$3j*y6D<a$A!H>;gsf~qDr6-xu$N^h{-1|v(ypwK
z^)6-_30dh*gsiGzG$0M@Ex$!bB4lM>P{_*soX2tF6=fV4G_{lpSp#tWv5=MSM93=H
zBNGmuM99ir`;m}UB1b}2i5m%7=}s1T2LdG4TL_9VjkgiCNQA6RlL%Sa6N&Yf-<u%$
z#eg)dxBML-5wf=8ry>!uP6tSYtjszQva*_qkd@`6Le`y-C>65q4U`I5nMW#QWx7<z
zN`c#gM96vux+E2{Qf9g+5wh|nJ1AM?F&79~`HzX3<i^%EQQxGA{^;)u5L9GPM##!u
zNQA5sFA=g{gKDQjR-#nMN|Xv&nJyKwUIPXp6|yoc6|&xjuvEy(uvExOkxVLN<(r)f
zSs61GvN9|cvOa`#sgRX1Qz0vxp9)#eN6b{n$|0W-vT{gggsc>!W`wNApurg->#GPA
zA*<NQVVRVVX8K(q{n78es6=2qgb3l6;lbgRiAk^c3F!!ur^r#4#zE>Xc*tza!6Yvn
zgsgml7RNZV$g5yvrb1Rq9upxeK`LZr1ydobJYtl^wgv_>PKB(`GLu-yN{|X!iBci!
z5(L3a3;+EM0Z~<zkhO$fON6Za#Yly$d{C*7l@U`RD<|bt$jUmWLe`Uj<|jf{kS7@-
zE8mf&iIA1(m_*1*v?>v@wxYaL$T|)v6|%CtRLIJ7mnK41qN@@iE75g{kd^4BM94~X
zTOwp-o)EHj!IMQxCqc+c%)$jj$V$9ZjAJ3|5%5TatOTi$bu|zcd7PN&lx#rbv8Oro
zBdmn1d`lA{E1y&%WMzq}>|5eQiI9~(t$a~saAK6)0e4{Vg>2;;6A$DU#rrYb9gZUd
z3m+*xBV^@7ln7bR0f>dH9187^V`XITT;v?a<y93`($}4bY&xDmi0(IXX?Ef5x^^C}
zj;HAth_1=cfPaju(->_yOrRJ%5PAE9&)W~Q+m{iUm%V#YyU$1Ev@brNtjIP`LQNq|
zy=WNn$6wEB|I910?D{LQo_8LeNxc4|TlNw|$xSAcSjmkbQF0?ll-vkn>v<H;(|X=$
z{CD`=zlKW&3P#mNxT)ke3={MJne|s{J@0VVArhm~ohZ2xsJ+Bca$^gky~I#*lPN7)
zf1QA6(ynALF|6nPh?z#~FS@tA{-Q2Wvi@RU(0U&8bMD2BSCnzdpi)6<J@4;8@%oGI
zcdfrlvi?e}=gBdMO36(k|0C;p?_Gbz*7NR1Ss!-&rD2jt)?b|f$@*(1Kw>?QStr)>
zSj~Q{=gmc;)Oy}RpwxOE^XSido~*wT>v>0GQcA7o$@(j?o@e4wr{^<sOh<c(nJAPS
z=dSQpGx|lxLtBlYCI)5JUkvZZdfs)Yc4|G3D7BtP)Svad>oDu~XFZSlG5uN3qfxEY
zdLG~G{;cOQEVZ6T<(mGi=dpRI^}GuaGhKgi$Y<7H9MYNf7wzL^)?c4MgEQ-|HxY{U
zSIMA~VD!b<M0d#$L)Tq+AfmCBJ_&*JM;sod(nODvEX!(KgK^Yl9vr=7DTX)}f@G^4
z2V)usAwBSrWf;d;^b03=X^b<=GAci%%d)ExBe9-G(4X}@dGaWWT~IQZak?yfiJ8R9
zGJ@249#LvNZwZ2;W!XCjh^nfVWmR-$Vm(imWr_7XKEKp@9wVmK^Eg-cXFX4rWr_8?
zAECsBm00(Uua4SFOx-skwU?N>Z$xS@F?HWMQJ&gMOx?H1Kx!{Bb>H|TQ|oz5ms-yw
zO0DM+rPlL^QtNp{@3Ef8am1pfldvo!X5oUdEF+#9<9JziG&~aPc?4P|)_pq-2+K0g
zS9D4?(XxzhM1<9{j4yApEaQ_(mSrqamCcVRNtEm*rcW#1Um2VjCHKHx5<_FHe39aT
zyhXgJ0q4j7-Nv$vFHEv5qpZ~7xA9oS#9m_BU6H-S*04@`$zEbh?ImvK(P7}_xUm!F
z`vBS_UQXN*FV}@ev`4(0xFcRp+z~HF_uv;N<3~XMbIzFz)~YfFNPk4x=F}<+i5^wR
zsH`P=Od+T8EEaJ3;|lqePfP)dtTdD>KV!`GDy&+$i0BE0nky@a{-RJzWnZEv6>6*O
z$6Pij)Ts@=7=dN|Im0=HRlAP`zF<_iAk`|JKLmPFA)^YL&iYG6GvhhcB}Z%eW(9oo
z5Zh($!JM}k!x+Py!$Mmv0nTUP!y{cg_(JNs*7i0-_qEDjg=gEh2=2B*5@T(DVh!$z
zz#+`>cUF;|-Zq-x_fg0xO!J2bJVtQ8)%;aFtxm3n^@lx|zgS#0e+mEfb>G0+xT}#l
zJnS`cSiE_=u04aR>#r*QFgE%4J9KR^uC8m(mYCz|xigG#PscUlxFvWrp6CsK1NdV4
z9gFAV1+3q10Pm#N3Opn);9)SiyL9b!dM#Or?pm+n?GMidxJGW+0cAX)Vx9w!GwJyl
ztN0gBXx=N}aTz^dWEG!Oo;ShcNAz4Y9iAIh^84U%4?SN-2kRTXU^(jj8a!UY)qNy-
zf$g7)YZSQNb8z3!K1=(g*4|Opx=%*%H3-^03D&w_h2KrUOA|jN$)Quan|lrCcKDv0
zglIhn!H)%ePW-6xxxY60OYmeCszj`NUYLmOSGe@ShTFRYkBpbTyB_pz9)}MjT>21%
zOoA^jeGfg*Zov~ZH2bCGlg7Fg(*-_hE{#5Ea%=vXKWPR?=42-i=h^H|o&l2i-6q1{
z`;jw1GIP`nkjw)l^8m>#x}yAo7$BMdcaqG9PQVw-nBXcbyULi=^mRvI?bM-Ty`*0i
za4|gQ-?2c%)p--5d>ergnG6<r@2iovO9<+Vlk|+D$mq+<y~uGf(tecbS;Y0(^dsX1
zoINoZ887qfo}zXqVj0@Jmy_k&Y*fb^gOAo|`8MRNf#utPjzDt4%Ycr65<Cp(2*BRu
zfQ~@25qm&K0KY#2Is!b(Wk5&Z{~aBHHCPQ<!(__mn(VW(Z2KA3Ozp=`(Dbo2I=_Gw
z*M+#+kDaLL<BIgU0q{C{Ve|EP(Gz$Q=#RKMPC&X@jntXg{cc^Gfve*Lq?;{X*8qNt
zUWXypoW@@xtH%Hz5--G>D_(_rAm+sdO^9D1MrUA<m(_j>D$me%*^(^f&O_zLjDqS%
zw3Ivb>~tyj&v6`IU<^YyiKcFJ=2eLv+08uV*qF{m2#ECz=++vPF&z>RA5_n?K^fEe
zGLqAn&Q$z&dT{$TE*S=3@;AawJ%dq@&-|a!GiXeV=^V#8M0y5vCwc}1XH_C&I&6Wa
zS0ZCNMAY--kN+A(lXkUgjfpXxUog{1&w%c2>lyG=xkS%^eL+1>=I1<w8?Pwiz<3Ox
zT8@qBSa@|}Jp;PmrDvdw>6Bw*I*TAkXi$0v61gFBN?*eVI;F26GN$u5YO!rS1NKCs
z=Xo~-4T+xTn*fQP!BB|T5<P?M0D2oDV>--wJb)O}VKt`#q^I=N_N1u}*eu@>iTY}>
zF`Yeu=7g~^9p*8&78}#ypq*c<Gp19Ejp<M?U}3G!m`<(Em`*J=ro&v8DkUo>YL**Y
z+e|(9W(MP-eG)+>1`SG2>0>X{Vq-cIuNE8A`3|aW)M8^gL{2R>rbFb{Vq-c?SFXjz
zbiM;IVzm|<(_z^7T5L?`=Lnlzi;d|pY+5ZgrgI;{X4GP1I()PHYOygL#++MggCK~;
zbQm_T78}#~Bht;U#m00Pb3v`nm`*J=rgJW0E*c!4(#Ih`Pahng(#Ih^UmqNw()SeN
zKAIaGpVD^}8oWL?_<rQhQ~F*(sOWie*ot!7i)LNF3uIl;?_H>Fksg8ZJKUQ-17D7@
z%wwWg{FvTh946(^OXDDQ2Ry{04o8%{b&*A#gJX=^#XEX@49_9SnS56uMor#zSSTmZ
zYOzHf7G>08i#qb0Q5G8<7|eJ`awgv<W)f=^5NNg7q7IQ&+lED*HxLk2wMEY43($47
z*rE=}5Uo~cQKuGL)L}%Y7F*Qe%-mUvE$Xn&^J;Y#b!xFiooi9z!dk3V@Frp|t<_o7
zsnuE3sl^s`hN8UFYq3S0F+k_mVv9N~Z(Xg<qE4;OqE4;OqE0Q~L=amj$4Tfwv4!$l
zY*B}KLfMnQb1Ygq30eijEL<?O3W#@%aT5>IgN5>?@TkQWbqH{lI93%VER?STf>r@%
zCpsk?Xce%hIsPL&RL<n%t2&I6fe8!cd{V<6V^v|HoF%HVd9bD=YSvn>glAyTr;Tr`
z3{H6b8t%a0TiM3fCLYMoi}xeAI~+$jEP*7WoHjf@laI5}@QV=0Gx=!j%h)s;1F3sR
zHzKziD*%j_aI?oYx4_5Puo&*yWoFm$SOpm?+dCc9F>uSJLl8&p{pp~NfvfiZbWq2@
z-RiT$JE&veZmo)&ItK367I9O@z<o#JblUnnpu$SM>3O8=daE0#>v`Puu5b3BAzd?Z
z&v(57A7jMay%*wG&lBNeb*;eN?s^LTPS<&GyPEm<DCBg8p1%}1m6%<e`<Z&vK?UZH
z2wK<ih^=?s0e7zJRJik9AHm(|ItzER>pJ*bUER3bU4M|=Z-?9MD&bz}`YU|Au3O;t
zHS<AweNNB6?V>yu5SRA_y@{s|b=43->-r+{)w>SBJ=dkfC*S4ZZghPWK4#Y*xLaLw
zaksl}gujE+Z}G42RXu-P0r@f`=S^4BXr)}9DGuzu1McCkFxuDjK@4z~<MwtO!;^S8
zPH+?B4Q9M`ddOhs7r2eUz9fl}#4E#R_(N!0;p=)6gGa9U1uE2{i=otu#~991v_xO`
zG=jQM;3ocKaK<_YVF#AnLveK<aqKEhKQ`C;Dn`eC@YoyIsGgO};CsB%+BgS3pTyO3
z7*q{b<UA^`Tmt-MT%(WB^pkVW_VCKD{p^{&zrZS8KR72lC;uH~j?%_#LM5)pdp8ym
z{R?pyRpPPw0lBqDqPl-V0^80>b>|}HLa8p}cZ<z|Ik^^&|DU6*pWsq$n425KHf)5)
zf6!Cfu(N7I?Ot7Lz!kM&SJj4T@R^EB+AvSGVQ=6)aIp;w;x=4V-v&`J(8ipbv_T9T
zWSg?TG-VZ(&)N34{o2pbBZl_qYsvS^a|k6By*~PWS#aKm`F=6xp<h10nc`;VOmQ<h
zQ+x@Mn$el!bX%|E^^VUJw|S=c-SBnJ#bk&x#lJ>(bf!4{m3h@a!%^V$nAbd>DgHK`
z{zgpT@tNZOO$@x+ybAve&5X_zXEHN7Q=CjfU=-yeCi;F6w;7!>z8vAnJ~hshzWfwV
zkd;i`J~e*~MpnE}&A)mCflOAuKO5a1pE4fpQ&ZnBMfrYl<L?(~3(CuWzxX;<H}NUs
z{>CPN=*%TQyHCyU<?mK>=8{hfXYncH{@5x&bmo#jqy!M1x#S;3&?m1&i+>HXj?Y|5
zIcR>S_}T9l|5KQIu}@9DUt(jR>iZ=&1{!_8xFPzBi!*6gcApv-aH=B@X_W65{~cB`
zI&;a7_NmGDi_b49oHDMyUyAbm;>O=EQN~62eo6PK@fXy;8=`)kGA^Gae#Z|1;xm_u
zGH#Q7YFr3L`_v?IfBV$@Irw3MxhYNtz8{@3PLS+V;|D_7f0j*&&Rp_G@zK9rU{AF8
zlg|LyGE}}_{0VCSqBEEL@AFASXD<0Co(&M4xfB}%W!A|)HCD5qeQMM2`<m`kn+KHc
zQ)3?e?Nd7k?MU~jadJ!dsTEN9be|euvTg2DW1=Rxv9(RjyzvKGE6VqaC`)Jbq}dDo
z>{GiE)lT=R5vBXoi2B>7cBO+X6Jww(JKd)yr;I1YKpB?qQ@b1K(tT?3{gN01Wz2M+
zntZ<`#z5ti@x&M?W2XDm*!*;#+L<UJ)st4=FUcw6d_^*P(jVxQ@uI<DD_WrZKFRdE
zK-LBQF5fTm=@Nbc9?j^xOiX&kPl(5fOKv<)JdJ}qhQY&~ho~G(^1|g5UKC?Y-q}x=
zR3Z8sh>`45Bj|6Rnml5ZwG464GTc*z=qH&;{OLlF?o%U5_o<0$kLL2<76e39O^*{#
z_Nnm~Bi*OQ2bJzqbMT<jeQNUQk{APJr>6VVNC>9;)Tr*A8Uy7!lBy68rTf%~(tT=j
zxKd&av>T=Ow@;1f(tT<~={_~0be|egx=)Sh-TTyBewwgo>7+q88yT2|3$_)W7UNhU
zdNDkbeQE^hKDFb4PKIrEOiXl2Hbd2_kV8MhN+FtWX`&F#CzU8fvqV+)4RNAKA-b3z
zCoY2%qvTdZDaxmd948(RWF9A8G^jc4avW`qGs^5!;~bSJMDx>S_y#P4tPY1m;VrIC
z@n2teBc|?la>?7(_)eXKMcMJV+G)z);#jyD=m)rHBx?I+Mt>7%3w>bVe}{&7h%@##
zNP(;KD`z6lnGMU~cRKLNxH^u4Pe`9jfi7XJw=p*Lof@g}`Fr5s;6iKmMwFt#h}sVk
zVrb9&HCe%py-ls)HV<PkPQkt4!>r)8xp*@UMm~9EX&|pG4Qy)#$5`<Sj_!dKTr|)J
zR&f89ui*GTB`Y|2xnd>IffZc(+dr^^8(6{p|GR?QpYNsS^54J;ZeRuXVODS>Z^Hs)
zgsk8W9T#g6T#dz2`{Udqv|Wj7yDeBwy@acM28?y;(?qh<^jk1<xH^`e0CI7*%XoVL
z&!OK5JgI3;iOaw9fX~F$`6Tn3>oV_KfPX;0(adk>(sl5A8~80;Sg>(XR5X_29v#5*
z`kTqJ?I_fj#GBU2V66H-lP=o^>_lPt8S!uY%1Zb*YJkQ119aE%Zy(T3!GN78*eMvW
z6P4%>4A_Y><1^0(>_kC;miKA(CS#{yz)lo+o|u1o7L-cLzY(SU+Y$r~*olJbfQg@`
zboEB`ZvJh+PE^9biJho_yA1<rw2*4gWA*kHMv}hnD_p$^{}$4)N5_3wsNrg-F6Xo&
zy}k+fFZ6;A=yVZ5zY6psF46AXt&v%D{SGo^TpfoY-R|PG81O(`ko<9dp>3h)QF{qm
zUy&8hAE7?nU|o(@XS;n4tFyWz5c4FF-~Sv$^Hm50bBaHM`A#`hQR#%5T;b&(Zd#5!
ztm{U=Jx_1u>yuN4K+SK%Z4_G8;h$|>j=OUuZpY}k>zz@kwmY~Rac}To?h4?CvjA@N
z&IMTS&gldAvG+rO4esS&DRVa$nDZw0OoE?yU&K56yt|Izmc~wq?>84#%>?+FcQev-
z>xDZ|pWM&Ae+TN(3(qs+t%7#fHLnk)PsZhIc~&GkJ~2NX?qIQxdOp#@V4(}mDFI6s
zfv?qD+=Xrme65w@7P>GG!=&tmqG5eIe<f0uDDbte@=v6j0$=Mp75Zypx%CFP%8Z}a
z8XW5i_hDd{0$=M}Hp|jn3Vf}r&9e~@34E<<@=PWIU+dZ-`@r33h<Miy2jN&(ts?5F
z_Bdxz4jE9qYfq@qtyQ6(YEP7$4VU6wd!ol;9GBu<dt#NqcPZYrCk`PfSD~J2Px1~y
z@+zL)+bGR@1vg4drRFG4#Jl!(&dcy~b=>Uf?h+(MQy_!2w-;cz6z|$Q2yk4AckLMh
ze3#-~dq)9fm*QP}rhuwT@vgm-fM%ECUAs>}i%apYJxf5F<|y@4dv|9ly4$6A*WRN*
zx8_p3YtMHH&MHtn)!wVX7HE2b>Z$fVf}o!2ZHDhIh$ii7)f}asY9H);nwd&R9@0oR
z)N@$L#THv>xD@Z&hq+%sh~u&*_L5=jiwn?U%+LEKZoHz5ZR1-2wTh^x+9x`{1#&6g
zwO2RLt+^EM+9#>(kqO_;im0dBPdaTTALI(n-q0wKt58q1H>!tPg?g&}l(-$2;$8b`
zF~j1!6z|%b1Qe@OPqm+E_%^HLQoL(FD`}ctig)do3+#y&m*QP}%g~GQhPAmA@7k{o
zy%(U<rFhqVBiIbk?NYpJzv&jx3%ymUr`m5x*5d(C&8<?+X#l9_+fvSqa8EvdsHc{Z
zs4t{?s-4pt+JNRXQ9ac*b;)CHNcB|P(Iwsdkm{+ns}~MNiUlFnQ*B>woQW=37*aje
z#ulRu2wN0VJ=KP-dA?Eyg;Y<qan>Ur*iudACMFsrH@0>V=aE4SMt|>ypge;HEA>?S
zv7E#3km{*6mX{JQq<X5oA?KZr|3*mlRG=!66H+}DXc&<nQa#mvDknB4%OTZMZJhOZ
zIy$==&OydD&U$2?<3p;a+Rx=ePL-2Gs;Am7sIX}v)l+Sp^~hg=86nkE?N@U0X7`0u
zPqnwGm~%s_r`k|Y<y${5q<X3iTk~H>y7}R8Xs!K*in$=9daC_q&Smo!hEz|rTk`e+
z@Le>7<KJ$}S2*P7=|iZVY7fsha!AkDhfqD$#`5y}_>a@Ysh(>0<jXsv!8lU<es(0(
zQ-6X`sHfTnr&QbE;FaG0DZ4xEeSuN$b573FqlGuyAZORS9G)C*nKbl@pV%K5hv_*A
z(>O@|IznWw<=~PRFsJbN7-NE^xYz!uKKKDNZK!Cf+KY8(HDZMF+Cx*7Kntm<YUAuj
z7G;FgRJ9M+WdJxRi*2_JW;|3hRqfMs=N4wd<)(eQ-bkQ@)Ks<4P{<0YscNs$8+SsG
zuX+4;528g?9d@t1HD|BK5<aA+s{Kx`c{yTeAvINPoc+iLXM_vcyL!INh)zgNRXdk&
z;w0S}Qd8B==S!^fypWozP)F*eSb2U(O;y{>4?Y_uE)1!uYUAujzB5ZhYO30>e?@dm
zNKI86_OFOmg$-;1>|bq0d8dceRJCFM3R;HRxgj-GZP>qJdFw)Is@lFvcWFpXRXb4V
zs*swhc2S}0!hj`Uxycf43ZKQ@hNddfZ6P&P?S{O(KzC^#2NR2yP8y^z3m0rFT#j**
zHf*yEP1Wt-5mHmt#@UYqT1ZV*8=9)S0-daRoKNYLY=&yya>U`Q5aHI%_TO`PzO`+f
z7i?&%@=3K(Q`Ls1Doa#l^R1FZ%}_9fTSg?hUEVf>Z{={lHu31a0d5<1$&s3a=WaM8
zbxv!idaC{1d=p=lcB-e^P*0r;;QbQdCB($iWdr^NEtq56VV(2}euaj(tu;P@fXb<b
zV~ZRo<{jvM@4zbiw8ACRH2)BXN2t5!jX*|+$}FI{YeoVbCctnHWylf%j(aE4_=gMd
z-Qx+C3MjjuWVB@hs_v=G;0OWD?m-OsxPTV-CW0dcw7HiPEEmw}PU!|X%HfmkcBc~@
zEnt*;0;3%xpvT=vaIApQ?i&Qh3Fvh{$Lbs}V2rzfAu9xobw@F`PY4+2zRHl50>-<a
zW||WOOmMpxZIytD?(vLvqJT;669lUTOm^oJoFrh1R#}FoI=Si27uk!iBD>rUB~DwK
zE342M0$@^}y&Sy7@Y!vQTj@kLGjemCRTzTOuen{KgzVSct}3DQYi^zZNBT9ln*d+>
zHMhHfvh-_i4*^x_*W7#o&C;*AJq5H#zvlK5&?fzw+gm`V^lNT`fNts6+&%(Szvez7
zV7&BeZeIbDrC)Ok1x(ZOSFnXP`Y^YwgN>?O!_Lip-1!Mx$N`pHE^*ZW%N->^4Y1tN
z0vs)W9wG+^vj<kTGhyW+xZldHa(;vvpnB}_$7#9MrCZ?E+<RHpNdm^ZZJ1$mCztL)
z$f52PcqqA31f1?JXUV5Z{ujHC5S%7po%=5Yrwh2$^$E@>J%S9bbiYclMnb;p-o<jx
zlya_fcW2gTNyvKlvjm?Mu%Wta<zZUxYyq3x0~vCTfal#t=60@t&F%_@oG0K__X#%i
zd;xE0`Fqe_kAsJ;kO{z3n3WQ2Dg0cFbuGAwSzOY}?y3AM@-FArInyzdy8E)AZ%E#n
z`v9x(O#y~Gk>FARjysItG69%L{)%jZ>GZm~gSp5|dng>Lc)7Q#U)nYBRll^HS_Ykt
zM>2?hn8}*?dtfk`{3d@di776&P|iz;qcf>(d<L<kIDV-~L0FP=I`~tJTeS`zKvwvH
zwF^>oPcocl{MXm*iD%ylot0<W?nKt-;6wNfT%DrX{A_h!gx&~zEv~M6@Uy2sCkyMR
zfuF!Nq7NB;1QTO=tS!wj<6v7cd4`&?eJw1cW6NzQ{%2BrIVt{`sQACMv-m;3*R={R
zRs3JJWAS?c?~F?o|Cc__%Vz+e#CXRX51Gu9!A0=<9`JW?jbPjQty1@|@xzR|9l#2)
zKdzSw`ACD`ee}mU2=7`v7S4x;@OR@6$nv+ix^}?|S$}vCtNB;pE%dt<P164)z0~pt
zU2Ddrs`+Q>rCGo`;u^vBsw#<cw(2bO5*5w&SDkf0_m@=77D6Tc73O=sz6)zK9KG8k
z6*^xk)FTx+e;O;&BNg~m6Z@%09?z#b*gvDCUp_UF{nCqv`{_33(tFt9=&jGlcWy6S
z7s@JQO#T-r<+IB7xMd&L^v{WZ?_tNC0=EppF>kR#pBu`&@k}S-KDLT)i`*uiYwi5F
zIRt-DfDH`{dOXl_ITMU$pKcm&IGs7<vTnkqfUD3gOK?s2F2HMWY$Uh|;Hdj`Z4s^s
zd{Pg?@gS~=?3_uz!%cfY*EYjv(w_lV0W8He=_!Dh;P@lKW`M8!QP)0)YtmZ)>*08i
zz(Li<J_u`zxF%Hrz5vI0xHRo>s7x8!-S|e2XrH6UsolJ{wILLLcddOtp`1zPCI{vQ
zGm7@1PjbnRLSgy62Ys4}>rZw0HHKn-(_nB!TArHo#*~0X$O$iIZ*eu<BvQ<k;(pf&
zFXp%NuOo(>@M2!&-$^%#6!SY3`fJW%xLIhweBAPc7xN0yK$jC<%x}p~Y|SH)VqR@N
zfPc{mFXlCQCX*9h%xi~Sfe@bX0$K?Dr%rgGTO@Z@C=FARJ8PWtQv`_Q&YDo6TO@Z@
z*21_o(PJZ(g>fs=ocBnrSQCdZq)f@3HOc!Wl5^+p68v}e#|@)MwFQikP%GAU&VCqn
zvh&xPuFlKyNUd0r=DbI0#o9qa9FNqB6=}|Uq*kmQC8X?;TCpO{d5_eJ6=}|Uq*km*
zbKWDhV!caq-rC){gmoabV(n3&TkZU{=DP&ygcobC0$UKB@M7&F2-J!*8@^W~nmnUK
zbKW}Gd4ZYo8_PPRk#4o~*NQafJyI*yVeS@$sGYyol40x%?)+tbP97^=UQxz@;Q~aO
z^VW&ZL?GGuYprgeTkZU{V$J!$I1GMDbKZK=ITxKp&3S7>qeQ0WytOg4-eNr^Zgs+o
z^|X5=5~~wltW5%x=DhVxLjh%}oxfJ3Iq#8Lv0g5)C)CbgYs=8rO?*Dc2`|=bL%T2=
zs-3^q8^LY>YUi)@rh7PmI^o57OR`p)^VU|WrqZ0Z-j=$l6J9J`Z&;2*N^{-<wQ>rO
z(ww(It+0AZbKU~A!qKQsc(FjOTnnT$=Pghxm!nIR=DY=JWhyGKH0Lc)D?LC;bKU~A
z!d#*gUYMv!ZftGST;3RrhxR=L6&Vz1&Rd{X*bAaLZ`DceEKn<dM75RXJW!QLY0d);
zBT}047N`~GuTFTeK&@~muF{;hK&>!LY0g`qR*u1gP$#@tpjH^BH0Lc)D`y}~Y0g`q
zR`_PC6J9J(D~zc$=Pghx3{xk(SfEzUK{|E9iv?<hF_q@L1!{%OSDNz{sFmwbGo?9i
zfm-2^k1UK^pjJ4fBh7gW)XJBTYb3d|K&^Zk4UQ~~TcB1hMd<T6^eKm}=(-O^giOB+
zWL*$vA5@}9kHC1#MD$zW%Q2RTPOtbejYg1U$)T6VLF&EXAyY0#l)QD=`Fj|WemcgO
zXUV5n;8UhyoGJBr3w+9bh#~6p)?s=Bfl{Bhz^Aa5>X;V`e2P40l*I-I1~XRb^A`A&
zDrN)`-&x>O2$cBF0-r*p#CI0>l;aTu@g4tlA|R^jkb5ogDbqPT$fsD~Q~0~2)aNbm
zDSTQ=ecl3}!iY+J-U6S(nOPn4Vu4R#ot65$1wQ2>Af-NUflqk^byn*07WfptC`x_a
z0-r*p)aNbmDMU(r-U6Sp8_HA1yjb8<J_@AN=dIYDc$IvL1wMu8l={2{K7~lB&s*SA
zh?M%g1wMsHiSI1%DMU(qXMs;)8?f_tcX+aB=_Ks@C1&A*vGbRBd5oz(Z-Gy_2p*z7
zZ-GxCQ0ns*_>@b5u=AIbD4mi`WKW#qKf*1WE$}IPRYiT?0-wSsCF=7Q_!O3?%H9|!
zYStRAgy%83eZ9l?*rVjgzQLP=C6ea-a2CLg-Wgmkd2{*ze(Z5^w!x$1$iBJ2=5F%N
zB>0KPC;hxf8pOV(aVWmMHaGH{-Ts+(J<@dRjdzRy`nmT@pdP)Ek|X<8LFkUaV4a3>
zzL3`g9xLGv49*L~_~OQ|(k0^kY1|!-Wa?B&`*T_=$sG&i4(G#Gk~<d2ovQ%y+<WYF
z58-y<Hrace=iXy?Y%{r`{2f?O6+Tk?3R;sNfgfb=z-A8f{5*WUd51TBnr`k-c4wDa
zButuM)iu1GOpt$Uk?qct2?`FZ_P{M>(TnBM97GBXhKgDA;#(54opmUxEz4pSy{NV<
zw{y#KQEgdn=Wj+)ZCUQH^}~Ql*s}b4WY{TNmOEw3a;I!r?vyRdow8-QOSUX`%9iC$
z*|OXzTb4UBTb4`MvV0zLDl)q`cWhan1-_y4tx+heQ?@L3%9iC$*|OXzTb4Uz%W|h|
zS?=scOuJLIEO*M5<xbhM+$md@J2P9BOW3mfB+Fv~ae3IX{8g4$lk#NCa;I!r?$qIv
z?{siCI%Ugpr)*j7lr77hH^M*KvRuNJ<$aMykr_FUql8=FkfHF7R=fu8)>ja_ge}Vq
zaQ4FO$vB25@f@xA8^+_7<r20mGuZhyZXQOj#7N@3#(3PaT*8)R2A72ID<9$<&Ot&t
zrhKUUG-)3BzVcxL43B(Yd5HkWyAxx+e7FGLBQI56DxmC<?<+48Q1!_7m5&h6?2+#)
ze_TL|N4~Foq<}V$d|!FFfKHEmU->ARS-L&)edVJCjPl6$m5&k7<8353R={YFd|&xE
z0lgmizVh(`#(3oW$}0qn^~m>?KOtb8_bNkH3K;KwnrTiDFu^0=S6(GxqDQ{3e4>C!
z9{IlVY5|iy@_pr#1WeIN!uR3#<3jc#`96Dx5`R`TPv(vp0t~IlUT!DfXU}e9+>-Ep
z_FR|=KwS2#y-Spk{c7*35=y_?^8`53ul8;NeCbzvcL8PTS9=cuRq0oIzJO-wS9?zZ
zEz+;{UIN;rU+ujGbV|S43j}mazuNl<Q2lCuM8J6IS9@Oplcitng#xB&#dT~U`96DD
z2OCuqzR&)+Ls`8HFnhVgRRhdEN`M+*_R#_`p2--slkc-vwliVrA-LbNS2@>~(Cy^=
z?A4_k;MP3yefCKL#(U)Z?2}8s#=k>7@_qIx0#5hH_t~dP{ug_X5S%7pokzaUK3%}2
z9{E1|jM4+h;7X5tpS?yxzU$q^a?X@;uJg$E*=I?}dXIdc{Ye2E%H;d(vjuGO$oJXj
z2zcHj-)EmIV6#WQ&puDUs~-72`+Na!XvJTny$%NtTcKWGg;^=Vmckoi4Al_wefA}-
z?4FYFefBzMBBo-Ge4qUd$y@UtU=_Y8!0^cT*_R4%Jo0_^WdeMyxEa~Blkc;y?qDu5
z%s&c;DqilbY9)9QeAP;jKM_roQ#H{KzZs)3nFR)u$(oU}FBMZ<Y++MxCOVS_1{oD8
zj=!%`5WW++(D*})A%bVrO)(B6)?%&wxiPTNv|X7IC5DL~vk?+_rq=#<2JTRP6@jI{
zqFAS~*_n<A-emxdgNh_4HE$EaV9~KLw9;lEzp=$Rj`2=l(9j0DHE#jIFwx{OybB0g
zBkK`?(SR7>+zv+{8ip}wHYmg$#$okq;1Ow+r8(<zMCg8FtfrmWxg+kFk-v+7m1A=q
zXCuUEL&y9CjuBe%TKtn^ORB><=_SXORMoL1qaH*er?%F969GLq#OYrOtLR#;)xK1u
zpXNYNueps$H^R^lJVyT!J)u9~=mh%F2<}}mo*rdBz}{si!_dS7j<7vrT2OC*;fy*K
z{tr40j5HQ1<PSPEI>$ZE+#YglW~3g}X>o~`HvaI{h`QR*8CBmK3ym>bTHspkRJphr
z16eh}7*>4D5VQwi8VegU7jXf07H|zlqJEMiOS3Ttu}&vBAsg0v_>pu={l>W8lz<)y
zSaKo^OPu6PlR7pYfsj)id0gWxra#3ILn`BD;-%J4bsTBc614EtsD&$6FCz#gVAZh*
zIo+u}#9o~sW+t}grT<70HxEZ1>(&p&rbKDn*8EU5?$03Kev50;5lH-YzQhQ959!)?
zToXUWw!V|E@+G(y9#`O+L=zvHQGV3bv=bqVdk21##kxk$kZ!->5nVeQ*JQRjZ^)O%
zbB}@=#5EbZVTSU03WCRTaZSc~C5F++9-O#d*T&+Sd^n0QquhWO;F=;`ZK<?hdJ=O9
zt||Mlmuy2iX7*Fy6>&`#!z7J{^yAQ{byx{N%$AQLW<`0v2#=r8^Y?6DRe65m8C`3_
zHB}yC&9M14=hy!Gnkigv=tET@7d)qHXW^P+GU+fJ4uX2$4Ub>ab3Q#=Rnq3?(Mz~m
z9KFrRQHNqX>{V?uifrk2?CmzAlOsx-vV^T@GkP9Iq!*Foa$HmQV_xm5ZuzzMu9@;x
zdUPm{$6wO5yKzlzXVOkX#&v$}AJ<Gdnz6c6tgmj?wPm=b%xA1_<@xuQb?q@+Q${o9
zSi`#rRru2@x^^qB4%^@dr9RHE{|&O{uD$0h#C`70bCBn}ofm02ZHlnm<BUP)A^cZc
zu;l{Rl;1J0@v49ouVUojno?t_6O?E9bzR%=8a(9ypNY!zw7=@wI9yX|OpY<iVZ8sF
zXcn$%CoVr;)2A9`PJj8e8`ex)e*9`p-_9sMg&~?>d-0i5e#e)3nlYG@-N8`98TU6N
zlUHhc!+u?2ZC*3&_>-~y*RZe0l$u|A_nPUKv9LZ>m^O7XD>=`ohM=F#{1Z1B&eWF~
zVfWbU_wd^O=^w#siKEY$3h?V)01kEZPJkUYvJM@lzQd=Os?*fB|N3e;&bRePcR<`C
zea}*0#*xcVl@o0Jy6q5h5knrc^VOXUXUA!+I12~gLX$Bp4z^_mxh$8{zK(0=k<$!k
z2x_;JoQb{@&qUuz-``mK*)@18cRUm+_i4r;>R^6dj?X^)4bt6;Ye%gOd_D8UdpAPO
zEW6}$+6Y{I*X?dNBa!b~geQ6D&VhS>cDL5oy^o4;gNk6Ry<m-n;xkcZ{w|7w^xFv5
zcDxC-n}FJ}{2f*Kz5$vDSKqz6sO%dMzOC|SzV-f@&%ADd%AlXZXK{u<W}e~bS|7SW
z|GeeiHAvHDzY6bDQGp|I&3+o-B{(+Xn)3+2?BC*cu$j|##WnjE0GgH4UMIK#U<tq?
zT(kcT;AS{3Be(?MV|GrPk8Ael0G@?oJ+8Sdd1oEJ64RX=#2-0rmm)xZ?eEs?JOqvt
z;j;|a&fNfy!SP2%nJiHrU9;;fIQkwy6DH$1EkxzhrXHYA+zGaljJ03FL&;reaEicx
zhgsvlpI`eZ9-+UNN_)|}(oXuvX=k2`?q|90DKmGT)^CZLHmij8KaX;C?IL#j*R4|b
zV9>YQ!+Z7^+&bKx)_`mFaDZ>X@kLy78F%Mh;ZrK)w7<e<=Z^r~4R8~#T@D72CTV?V
zVWOCYdd)<xaox1Oi{QH_dnxw43a>|BGhR`S@sncT_YC1azS4|xN&itU-d;tyMMYuz
z>t2JtO;Lo$`_JQ1%s4FOohXmbzB`W<vs8q(A?kJb<hvuxo2??u>Mz0#QG}%`!Zu#W
zz6a*0JU-Qblw;<qC|C7Y%;qS<J^km=xwFdS#r~t5yQ_*)!a@sAG54PSxGIV;QAOBR
zYaWiG?AL#kx1uN~_aEhr-PFkWY*dr8@XobhZu}^o)>ZFH=JaWO&K|1f_q;1CGjpzw
zqP*CD6o0<Tr2#)v@hE=RsOpWPOzuC*=~0ve`j0YyPgT&V{YUw1G?9M2|0r)oQEuxu
z%FIn4Q3Y+gHTY)o@$KU9vx7g)^1&04vle<<@JP+s2R~o@Ef!qTiVT~#6u)h}!lCYN
zg<pU^#HBx&Gk5zbJbC#&x-;)dICz!MD9!sK)@8iHQSNT>@gIJ#?r1e1zdqVy_;HNH
z%u|rp7*JBb!vw^?)@xER^FNEx=t1c8$lh9!?ySA&WWVQy2#EK4(*0l9@3|JqDK(ye
z|FZk$GB{)@jrm`s#;_ONiFLyN8GF&Gy|v}61Et319tFA+d(i|+YK(KKyVx6gY;TRo
zi0nn5f@spNL~4xvo;-0{b>tz9bZ^^U^e+*T*o$UgP-@Kl93Df>E6O-99tKG5t??M#
z*j_Z<+q4&**jw8d-++<5HHqAxy)`egx3)JjR8nJelS`1;Tl*7g@d4~b^K{o_zb7q9
zCibG6v7SxrMNb4!Qe*S224<buTVpl<6ZY1aM}PL#)}S4!y)~Z7n%Y}4@i<d^Yi}av
zHtnr3QIp&nkf5o;8^84M&}h`C$e@h9HTJ^)mG;*7W-F<&Stm87y=aChsj&&E@$Z~i
zYHZd?jZH|6+5G<Ot#Qa_&ZXv%{;>Ae0)xX==(=ank(quM81;J_DlwQIfpHJ+;b-tP
zIL0#3=@mbwdZTN}qeSXqNF?^6X>?8Ay2xJiq8MX>h>fn<7@n!UXsZ8z2%~F(7+nj*
z=vrzo`blOIZ~7!iH+>SNn?CnP5TwTZw*>)FRh7MH2al^CqicLx{TW^3%&erwW}VcS
z2Y(!ma{4p6#up_ux<-^5T_gI>7+qt!)aV*fYIKb#HM&NWZu%s8&!$iQ&NZV?q>~^u
zChm?g7AC|rfhOUxy=dB5dtak#4reDCU6W*yy=WR;i?Fg6eI+~+d(nJSiM?o+sLH0%
zHA$4%i>6N-ts}|+#<-->wZPz8*+w&k@j#~0wZNd!HHQO~M%N^xjJ;@%?!;a+wX9-$
z(H&s*>g`20!Dm}GqW6UVf2)n?N08xvkB#UrAg3a;i)}VT;JODEpZ`-fqF-QnEFdlq
z0@o{8o(Nq3^ERRnMjl0G<ZMC-x5FXN5dzm6;ZAHsGr(Dd+Y51w*!FYrA;zP?l{TUo
z>|BRi4dPYFDT((E<5A#B8_^6N+5QWNRYoeK%c~Z~2l#y*L6Onr7LK7=9!Mr!%DnR2
z)|W8P9tpgJek6)_E{{UhF9G}#u2JVAC(3hsbkW1@QI?*2Vr}KoV_53zV(EDiqT=%j
zoHY}u0w#o<&hJG|cf<uulmgxcd;?eSxY0;4xsi42^>bPeu2HPMDwOKJ3sq_RVbvd^
zG+uUV&eTqo4};|(dZG`5^AW-igH3Iy1^!lk@1O6(fR-o+PLmOx(!?6`z-cme7hZ?|
zkG(g6v*Rl7MC;zVb^CVr?M2<U)vdj?@0%rAvMq1&s%}X(2D8OP5weU0vMjWC0c=Cd
z0z(p(Kp^2c%e-t1OW^Ss7D<L+0z)7(10jTDlJM9=GGRg_CzG&*_y2!quUq$ax74y)
zQt7Aeu5;?tsZ-~C`}xlImGW#d@F^ATAkQX~XOjU&Y<D8JXba4)A#B#u4)Sa=Q39V*
zO5}MqnLL|Jo=xV$&nELqO3>?+ra<|A8*sbu<WH=ouznUpeBS^`{962|>?|83Im^pY
zzMFO8K61I_mw7kJ?_?ddhmGA#B=ad0PvB>%ICfki(#N+@{sw-Q!GGp@om=J|k1ZFc
zm+f+z<1a9P717F*7||;s+OJX?M>;KwI*GXY5q`tJiQe%gJb)c(d;%X+!(A|w)_@=5
zegA?VHQa?V+?5^0Xfb|dxQk@CJ5hWQe%5>+J#E4$@J{L-F0BnpFwuyIjvjFI=lIT2
zv>dy?TKo76M#P{;(OmrCU(1IsJ?(>&o^MN7#UtOAP>M%ZD)NclmY^BKZcFq+jI-Mk
zD^VEtw!}I-<kG<0fRalCbHQv&{1%4o(!j9f(!j9PC=JYS!Ti`L4Gb-s>M&ap9A-;!
znC-K;=hDE8eOuy-cupN=8*N+SRcPtbz%<{M_#3qK!chJKKKL8OX<q?hW*W=y<L*E5
zFxyzSCA=L8f>(nb2}aeEO%6hxYlHVpLxt!V1SW0VmGW~<+0!|=BjM7({5o3L9SIg1
zrGb$p#=H2f_%i%<X<)w2PRx!33vNe(rOX|P|BV}Zs45Lij9DAgjszRJG%#b|k@!8l
z(WQYAoukIMKnc#VvD9csq8IN|=hzaQW1Ejsqckw=WkPo(_-dIXy(7VwOIhzotTSbk
z2Ij@6usaegxHK>?M+xWHxFf+!=|=BJ5cG9frGX)q+B7g+DVqj{Z&W)HA2bi?G%y_{
z*32QInjMMbxK=w7bBHl!N8(#j{bl^F5RU#07xMOEG-xtd(qe1FP;y6NE)RT_RbI+@
z-+2lWkVKMeNy;}sR+|5psEOwPDSj8`e+Iv?xlwo;g$>gW;>LnQym6yAKT`~&k89z{
zFXO?5Z@!6lrqhJ=tB}%u5kHIWfqUXjt=v;b=!{(l5rW}nN%#Cc-29(xaCcO=MQRE!
zSn`RtpxM^x>}+#qG1`QmrI1yJW|D&3jnXgR2eZIE`=}d+^-}a^xUgxtZt!V*JLI}G
zTCRK3hbh;!Tnn&_by&)Zj#XLu`7V4{5a_abjLVh{=%u97`>nv+OFF&ZOL(o*`|(<W
z6fnIXX94Fwe?R^#E+j|+()+!W*E+o)>lLN>DlSB@W{?7;_ao>_kOHLl<GWOl0;Ko*
z9bA{9l1}f($4WZAA6JG!3Mkj%yFQt~xXkNuxtqv$negH)s2~MM@5e$_f)pUV9}5zs
zAX(R*?QX(vZ{Tjihw*Xr`?yj7wIo3blB=Ykf)pUVpL!vI73uxtg%YFy>HS!!Nst1h
z_hVr|f)pUV9}6>$L79cYXoBTBe%F}XP5Abb1Sv>%wT{8vM0Gr7cN6IzcyKFTGn%`J
zwAFGQuT_u&r1u-6T*qeyBuD|$`_TczrY8^FP0m`b<9k$)0;VTl2U<2ZxsK1NAO#76
z6r8EM341}10{$VnbP|DbH(@>IdsKH5X=lTWk6o_gb1Fzdf*=K<T*rGZy<aHT@t#ZX
z*G#TsOPAg+bT<j*I<|D_{X%yWGPiRf*YTZM?k23qybl8GMv?1uOOfk%J&IgMgwviT
zBG)O36?mGANv`9oRD6O2@d?g}T&ISbA=k;6Ye8o6+Ve0|3E~qplj}HUm)`FcC^=7)
zb0OF9eNRe!f&}piCPuDfpNLOD7AJBY=faokSoY;Qmd`-0<71HP_($YARUW5Y$A`u)
z*YV2$>{)UhI~ucGCnDRFf^;{3_>&N<wih0{69za;S>eeR2u};{`9;>s5zIG1uo}V7
zLWpDA=abC;2}+;F&mst5w}}8&>VnvXpT*N5Xcca+v5!S4&tsj4ZqJ$Dfw~<i58-DK
zM87+_Ie-UHI>;Iv(|WFmH19^~9ju{z_`EjChhIhUf8b}yhWpX|&lQ(;&qe=x_hUr&
zN^baKcQN`8G+6eU=a(wW;n@DTnkov1S|<Dg%!{SyN3bMnnb1VKdMo<kza9U@+4}0!
z&zxPPtBH<o^$!@YiEed**E+ft>s4r#AK^m0xpj0a`V?eFxB5I9y69GX%tW_(7p^Hd
zUV}$XbSqw)=vI&5zKw46A@={voe*r-_VQZ%l+P@>)kpC-{gj`NzjC_wbGVRiF@hta
zTW!V4p6}>ZZ{`?ubSqxl=vFM)=vF+@=%QP(L_g)r@%J~;Ouowsj)-pcO?E01`SU%z
z&W>*NcerDtTX8Pvr_BB;{|CSLqdV>>{S*Zk-D(l^QWM>Z*Uh6_Jp_SAN4Jv3XCB?^
zKQM~y=vJHw8{O(363FHzx)tp$HoDc-DA?#$FF?UYw_?{ex)q1nAi5QIhFx^4`%rSx
zt=LDS=vGv%Ty(2<VoF?et7RCxi*7|E%ZzTthx+9gzqWr9f01Nk(f$)|b@G-M-HNl&
zAiC9`VAw9Y6-zF<6-$kxTm1>dvqsUaegR5#qv%$zq{3Ze;BZE_B4#&=ZpC{py48bt
zu2FO=e!h!tMYl{B-HIUZMYkeId(o|)K(AhOt2g0;wLy^4t=@sVVh|+QiV3e14ZL}m
zqMrAgFo;f8bd-LG>7M#QtOjAsYtAaOOmlEcx+LhiHh7xGz{)N(B}56<L3(8Q5mScT
zWujZH0C>9SR-Zu&8{LY9M$xTgo$)Sya7T$9yXaPx7Cc6)AfsEc;G$cxlo{P>05|kd
zRdlPB1dr_KR$MI?-HHuebSqNkM$xSv$4FdsE5`0}(XEImF1i&<F1i&<F1pp#c%O@I
zwH>8K(XIHLi*Ch|i*Ch|i*Ch|i*ChIU39B!P{~)zBtd#)nJ<?zq(_!tV#+4E)#IqJ
z(XCi;(XHNr60CxxPP~+EbaX4izb>ojRzy`B-HIz^qg(Nf>fL{39`d7G5syuDtBo*9
z+2~fUM8QV4VjR-!=vG{58{KM3)r)S$pd2o`)kjfs(XChlSL-NoOtVQZ1U*o353V~(
zqzki&xCWKpEY%EyRUst*E-vKzz35h?hc>#^lPH+zR*Yp8Mz{JTYD{!12(6jXtthFO
z=vI7XN2v$GsEuyL?>5n`2n{B>)kZYxDDkd|ZY9@e9^HyQ!xIzT>S6TM$?i<FDL7ki
zz^?bXif%=h=1#uAybsRSzs&cEv-N^Aj&5}e`sidwl|RE9K8One1vp#(7Orh{E8eJV
z!LP5G7B*_tr`gU#x8m)}yYcI1b?yG1?M!ql-nP-LUeEzd(b28Az&5%S3ndfXiUk|p
ziUk|piUk|piUk|piUk|piUk|piUk|piUk|pij>7hw_?FYw_?FYw_?FYw_?FYw_?FY
zw_?FYw_?FYw_?FYw_?FYw_?FYw_?FYw_?FYw_?GIZuJ;vQAf8TTa8R~D;5ylinDB@
zTd}Q;ZnX<agNbgX9@NpT<UteNiUk|piUk|piUk|piUk|piUk|piUk|piUk|piUk|p
ziUk|piUk|piUk|piUk|piUmZsdMm$BN4Mff+2~e(z%L|#A-WaY+UQm+C;&rrD;5yl
z>L41M=vI8tMz{JMuy_;Q>OHu&(XCjp(XBp?f{kv)f{kv){%v$C7Ho7Y7Ho8@&*K>z
z-HLZ?bSu8cMz`V}8{LWp8{LWp8{LWp8{LWp8{LWp8{LWpM7R1lzPG|_4qOO9yDD=~
zQbu$u-v3KecG0akJvO@4BJd;=-HPpPbSoBYbSoBYbSoAR-HLIuOmr*uqBuV;)a&K9
zj&Ah|)GA4k2&|%8u?{?A4v1MtX*&ucGrrrllq<eUMYqz;ua$=w8B1PAjw&yLo=7bF
zoGI(*R)1s4>F8E$DABF{9T(~7R*Z>dqg$=Sfp8PuiYLSyMYnn>+v(_5ylx)dib1uS
zMz?w=8e~VedH{DSHB8JO;sVjFeg}U{bSqW`(XDnr4UJkyS-Sm&rOF^06rTL=Q$Zh1
zlqE_KD_|8G#LsdaWr+=rq5Lp@mYFC^T#Rp^;?LMnM_Kw3WQunoU(HqcSz)3qagpcL
ziqTJdQRzil`d8F_A3rN#uF_GKey6V(y#zliT$H67`w@HvKPz;UCHD4ilwXP;70^mY
zS(-ns82#M<DovCnwtRAWF?tPtR`^kt_RT0p&%@73Kgv@7%wkl)&q_ba(x*}J>-bq^
zqAU@r;<tVC(Um3~5ry^7&MHRl!;cq^Xd8BeGr|$AG~tMr;r<6_BV-PKR{G(HZl6<(
zX5(k2ACBnFgT?4o_*v<PBbq(87<J=kr3pvG@BIx_Jc6IqCL9srmGN;_n{Y&bj<sYs
zqLn5b5ux+cykhhKepZ`sMBkBCKYVnx4oCF+z=8N}-+FY72}i`2MXO9Wq7wHW<H9FO
zl~pDjk*fM<gd<vO!V%5<ITTDdq7n+1nQ%mxnQ%mFO*o>Dyaa7cI3gC-nQ%mJy$g3t
zIHDio&iZ@jM$um*7}W}xRS}MeL;L52#pnn4*>EcwJO~Ts<*;qO0lyKB=yHZ5`r}6d
zz8nAT#idFs#{LsL%@(g`3)n!>M1l%!<dE557Q#nmHh5^KYH&@X2A|grb~bA8_-@t1
zYa2DV^={SRKQ(Ib5#8YFMh$9vR1e>7)ZneUK?%#A`I(h_R1XUqHMmtbxVce-$9033
zHEQq-8XUz+y;?VT1J<YZvQp(OsC$dl-C3+$7j67=)Nx5Z)S#mc*WIfcWPJ#jO9ZN2
zA;Be#3%Af}=`*IhII7UdK?s)ni0i?7n<S3M!$on^cq{DXe}qQxyT$mHOa7CGi?c{Q
z`xX_WF8m1fd{wcN)bkdUuV<a$<*SQ>eClCT9Kz3veS1IxA1U_GuKz(){2nVGj0%qy
zB^=#PQT%6C2@XG2oKBRzeKB?f@I#<~ZLy!!cm%~);b+~Rg9oF+pB4+xya3p79kAoY
zc-x9Yhf(|XVlQ>+r_t;repWuT0pIWr71I5mQ1QQ5`M0cmQdQ1a0#7mgY}|y-xE6Eq
z!>J{f+*y1bR%sjVJc-&3a_9NLvuNWtQ1=HYZ?&zX4IIu#TshkCOQ`s?RNRS(IzT!;
ziX|e^x`Gi@_|rG5^$HUorEh8Lm41Abt3I;^ajoz(HM;UK44OaH)rHEHKU@uo2|v|U
zh4K||LM?y#23w=Qf&x>DehxfK?`FIPERp9X--Bu5zjdF(ZpJvgSo}<_#wA8M$moQu
za#p#xWCpj<6NxWfVtna%)c_q##Qz0JI>hIN{x3+<aXssGk`7)=w$n2FU+zYsrGz9M
z-^N9S*-n%9R6oLNy^X<o<*RfW7j0}GN9|0~(O<x1d>3LOl63H0QT5~ag(MxH#vkqf
zf+QV$O#EMvq~oo)?kI`33$mTwic+V^cKR;%Mq4|wo$@;BQrS-BE2=u%DGQaV&UVT|
zwW_n7ve4b7vYq}09<N2+rK|C`buE5<06#KvyzjfXUVv<;YhcZ+7Vrz%PWdoC1;~kP
zr!17JI@>7=m8#Bm%0jhDZx>`cWud#Ovz@X~tLkj0EDThck^|XJS(sVX*-lxo-Y&>?
zdW2)(rUkN{@;a*OY^N-!O$%f@<rnBp3uHTG37ZzJtMT_3n#p(BO$%f@{X9FBiTwE<
zUPo1(?UZjXRhg0l*-rmE?o_He+bQSb2}~IKYyCQY@ke*uUHT3Ry`3i8X$L^0s<WN)
zI;!eyr_wz-A;sx5*-m$2vbt2ZQ)%3#vYkrXE|u++*OjWycDjxoR&};h7CO6hw$txo
z6x~&w?Uc_9RC%x(*-kkVGpjn=>9=7&9<1tYryZbR3#vNX=~@()RCTt~VH8$$>1?O$
zdJPJa?UcjZgo0!{<$IL33$vX*2M?)D3uZgrg_7E|V762Cp*Ag;?Uc_cZx?1eeG(<L
zX~Ar#k6=pFrUkQ|&d1=@rUkQ|5~b9p1+$&97kIny4<G86U;NtsFXJowS&#XC0=EWu
zYnsb;%KNfu!EC3}PP|=Okdosm3|nnlpj2Z?ZCao-n<cer(Snp5d`@}0Fx%-<uqdic
z3uZgzJ>~7fY^Q&Qdur2y*-m*+dAl&%>9=uDZCbQo(}I|-HZ7R#lr5FF3$vZ_p4zlv
zw$s1Ib86Fq*-qI~dAl&%DL+qbS}@z`uc74&r<-i21o>MF)AxfYGutUadRt+-$#(i9
zwEdgnbd&9r65BV5)4zh=neDU;fWoFlcj;?*0Vp>8^9Fd`T_PaMO0?h+ZzZJ2(V@-P
zr6nC?roIOi1URoHtIV49;+FJAICO2$$3|3$iyXmAP_U@VuQX*4Z<Ft|7qF@#tuWu|
z$IwD{Fj|nGg9WvN!F;D2pz?oVzEfFryo+DoU1G;7(hBpP{)C<U8fh1HFj!DK7|eId
zlG?#wzSApls~WY+ACMG1)R~g+bS`FDb}*Rl^lmg%`8k;HluM^}FqrR@4b=_?^PQ4R
zs~rsHJLQ;_{|ob-J|88ugTZ{K+@Dc97|eG{tWi4{%y-I?+QDGHQ<l^Y2J@Y+#rxC_
z2J@X>kCNKKV7^nnPx-$v-zlF{I~dG&%97f_V7^n9)D8yoowB5MFqrR@CAEXWe5dU5
z^HD27h_9AOnx@Kpxs+Q}`8lS{NGr^D`VcB)2ZQ-eSx`F|%y;?(N)JV?BvrhWZe~TT
zoM|G1F3*yDr^H){w8DI+RjiamT4BCZzEQpVznO=0q?PUxYX*tB0-S)7zr=NS>0S7`
zLE?}B<OmqkUHT`~v=WY{q9||Ikye=cl%z=_tuXcJQ4~tdZ4qzj<^z({0zvf&7Gmme
z?e2P>^eHvp=tajrQFm$T$7xAUsU)&!{b^0EnaHB`r!(dHgZ!eONgEi)$%)#K$l_ag
z@~lk#<*zSAPe^3(PV_Xu?o976_1^*Ee}YZ@<-g$jkjUa0zK<_3?}MrTy?o!9nfl9r
z&wi1};%@XYz>Zp(Z}v}dA*=SYXy7ESZCn-JXx)il&zKhN(ykH>Fad^*tHRr@AH%Pi
zpt{n+wkxB?##Q0%MN>bG)knM$F4%#+Ch6f9aBHy`j5-U1m?O{+UWuP2v=?<2c>CQb
zzEi61L$LDB0!i<uP(HyrT8lahkE74;p!f~^sKb&qp?%8^<3(RWAMi)wNyO!HAo0%S
zD*fSdiN5jzLh>3+$BK6@k0SoG{cSZGfZkAwzT89Me(^StystbBi3YD>kL&UG1)q1W
zN)s0?F;+SD#C^TAqLXta;(O_!T#Ng90`Z+7UM`h9_w|zJzFzvzy`Mz`&wZWk>4k)B
z#nyej<mcEc1@7ym_r+hu6C%EsJ~+d7U#~lsh#Y%&qpkHqqVuZpLgMvVcp<$Fk2jB&
z2rncXE%7|&*ke#c<Aua)>xIOE^+H<6*-+6Ekz<dg#?cbtg>;ggYA+;SXL}(z_jTmh
z8*{Wo<k;is7~_S+>pCx_TTy3o?3rkZ$gwAlNAp6u4G-HKdo0)-dp!4-?S(W2Gh)4v
zoclU*?73)($g$_5B_hY3i<XESd+geJA#s=uypT45f;cZE#<p`_NbXo-eU3fnzRnzb
z^h9@FNC^h-ypV`wnO;a)?&}ND80vA_eVsY>Y_!Ds9DBcuVLLA*mYf$7OO3pc=<CqP
z3+WTM*T@U$3%KXJkciohypVX$c_F!IiS;@5oclU+>^+7zI4>lEyyu1VFp8cR(l^o8
z^FrE#5B9u}et^5<I+oZ;>D}{TCyaTg4BmtVGOiO75G|28_T1S-=Ggm9yw7?evCzm1
zN!A%7<p-;1iOvh@+w6ogJiU-ua9&6(IWHs%)%DR5l^0S4Q)j)9$TnP#Jr^yJIriAl
zc_F#8iS;@5UV%=W7t(t%6z7FRL~&k7EIBVEmYf&T0N&@kkd~m-$P0<jIWHuZoEH*H
z&I^ep=Y_;lofi^)*!gNv&PI=xsB-M>!~@m~i3R6{#1M)4Y$7kE+xlpU$_t68YQ2z7
zW8SP6(kAvP{`EX@BAr+tcGk=xwwkkvpTf01n@F@VfZRA*qMS`+hC6#Uks0o20ITpI
z(L4xCbE8hiN0jZsme~tfCEJ57D)~)`A6;1~X2$u~;%4b9P(fOE4BU!wmli`JYrRdb
zJMZGnspz%!IRk{tQYR`}pDXI){D*NJs~kPC&e(Gd>(Tmx0YYZ!H+mqfT{Dxp`MP@1
zXQl1B%3q?;{$|({+ph2Ab<}<*FrsaX6iS!}`Z~>f9TbfA=XP^s^SZHP)BbbQhI##A
zUhnK-o9W-hb8D){3f+4k;nr@(2UTBRkntj;J-(*;hC(M<R;gCQ@9GnU&in9KrS^Il
z_Ns4EE!%2;0X3!ii-k^h(q5Z|7S&%VbRI#eGpg|8c_|ABmqnJ3nev<{`2;(DM<Fhv
zE_pG=T>ZU5FW)l#!}#14)ejW9zlU43LF@}u|FF=@=c8JQ4L?}uRfGF7OCKuq{t6ma
zY99d<RX<$l<y+gL<PeJ=Da5~p;`HU{rB?lTq5JvhymkX5;OZw-FH!CPu$SYe&m)+o
z>Iqe<)VkR6q$*Ww{~InC)u+_^x@$Gq<g1@lBkMsz8uVQKOd&qa_x%ukuCIQx(ET~S
zZ#%%N`mI6-M;+Ck=5&8sl}fcAU_GnfDRdAXDzz_iO24a0)!My$`}b6-yLOOo|9+u^
z-&c#0W9;T13h{2dVfwG&*Fd#a?7p#zoBtPDRQrlG7NXi_EOvEju{MNKsrETkRr^(`
zQk%n77*M5Zt(!|fO_jQ9_pz7h#Tpl-R-1#Tt20z-Dq!s^cq0-{;rZl+oU)n4m{rra
zfSK*9KCjsQ42E0#Z;(`~cNV9z5Y_&WGyTHiRJD5V<-1>`?p10Z<~+Q(IF<8ItsUma
z{akS>-`!p7;z;gNrJmaBxv)EnQ-8!4)IP=1FR0Q$?Y(^8?&4HHU^KJ#Zs1<^WyPsw
zlm=^*N~^C>Z(mSb0|cucC{C^7-jdqa`1XUvsf45zwRW!T5%s=RwXbvDA1F>G1g@#Q
zpW}N_mDbiCV(B4Ox~%r^oatAo(mI&yQF^s1t*<c!X!Q|Q+E9BtOOLA3<+Y!3O^&J3
z#@b9m%Nx~9Y^psdD5pxBYn_~zUsR>*YA<KYUs5x8W9_erDZi}l-CA40mTxOgCA4hA
zO8pu}+EIE5R<WZ*Jj50sz8S|LuxQCl4(IK~n70Q@eJFgUID;!O_*s7Z=ZZ7fxWebQ
z;zDrxDkOa8WB;`{;|ks+w%%iI_C|xB;$(cWIOF-K8~i3){%LW>Yf<PZvFYG1aH+ml
zoWW@w{1eny|4J8@5!C)#7ml*<H@fgi47U3J>B7GeTE9`8LGm-Wl^_4T;*8tb+t)dt
z-`CByqo(=~#Tm!&x58PdVqgnapvlh)(crJ~WB;)@<HsE3|3FXGe=5#cgcfk(WYr>m
z{|{BwU>6(zvo5S+;gl*=_{47f$jsED!IyFNPZwuA7j+eO^jdQ>i3acIlg|`q96;Tm
zP=g;AXS^GQjuOd5g}**z+GCpU=b(R5oblUi{}GNcif4R5+TV`Zsqoh~Onc1yYj9mH
z#52Cc_FpFrNn-W+_oAmZEQJgcUXVXxi`%#m{qYRmXj{^;u=T~bXs2<nV^IgMqxNs$
zSI6QGV&iPdh1{`33WM#xi5@zZ3iVo`xc19U|Fd8g12O1W78ATGtbe_^*BZ@xf_+{#
z{Q*?X``UK!jMY5^vUy+RHLw%c3!ldJTVZ|K7$yo&{s^rXoqU?LwT0-Q__o7~S@%|$
zE<lA4H!5Bd<BN-LduXYtTSg*YxC3{We-2L;*Ds4#u#4jQtJuZLgO^3c%e#4rW>cc>
z@}1?lb4KUF&R&oY)D&>l&YCHOo^m(PvA7^=Z@&gr;NbcalLfDUxbw>PtJ<$<-wHaH
z=whOZ<^Do@ySmHFK`k9Y<4U2hwU_m+bEB=jtFiuVy+QkSzdhqm0f^i2r=zzJclsT7
zqG831f(^UakOS(LrimNFl%P+1YfoRacp5gwbiIt6UDR}+wxX}Euy~ppFvJ^n-oHrx
z4A^&|Ex%`4&==k@-40l{n4v#Z7ia2u(#2W+^8mhHOxtFRaSlho7Ywdf6N&a)d#|0w
zdvoVv+2-kbSq)V`e}jy1flM)m0xu0WRRAlDtm04QVtrq_29rRKc4k$NOZ)V)Ed#@d
zmWM+rqHe{i=-O!l73hTEbKSr@w_u1XR~20S;%W8{zi3tBeGxlZ-3}P+0h?Q+M<4^@
zowc?bd}h$eW&Y>0={mnD7cXeOUcXaji_JHL&4b35`xC*&8`S_g_)Xz+<~8ryB8zne
zUSp?_PhM%~$NzvF>vF8S%3z&Av84c)XqgYz*G?k{EzgEHpc&zDMH;YI`aSUZRpIj%
z(nklvklvRRbx9mUC>zS#VyKo+=0V~W&20Bar07aD<Q*L$?;wfy7)_U986faJ`3lK9
z$as%p8NHSQ1LrtLhP(^%6Y}~j71u4M`fuC>(%G*##eh$p`6S6b5nL9J71JH3n4vhu
zOxrmc@$~_TXXmr+0CkHwA&VFcS;Sm_5Fq@9GtAfXDq~Uex?mAjb)ljEi$eOp7_SZJ
z|B{gYFGYWrc&YxHf+OBrM`sN<%9sd!1V=kz0*?NuS+ROnVXYAB7q-7Bc>$($O%ko`
z<(+`~8%nF;zMlSj-L$it^&#A+p5NeqEMInc8j&`pX*o#00ZV@Ope$}c@j>tXUZUu#
z^dqAqokOo&-h#@XMy88N-U=yy2(Fe)lY%Vwp^Ct|BC9cE5QlF<>)3QO`94MD9r)$)
zJ*R$B!&|9vO*?fTr}8XX0@lebdn4Nm96+{D)BdF)?I)p6(f;LNN}e*c!a(av0@W%_
z#Vwev_A8X&vc>{w7N=ONVcK#EQuKgRj8~%fKS3zEeZPz{z$h)z*U9riBd~9l2?kgC
zeHnd53;iJSTGzpQyn7+;<$5)sa+2%SAq-R1o<~)?POlEzjfKiOvYK=CoU1F<t)8p<
za7CzE=?D-Bt|idC=Zq#}B0nT#ISHElB<LKO_6+kLqme<eLCxQcPG@=j%Cu%w51d&r
zsWrDX4NPKdjTP{+tcOLo^<~*J24-ippk>*Ua4LZj0HD$uR6ucWGgj<&E>l&RH#&T*
zRcbTN1o(!EF25hxsf|5jN@&j*yZJ&HCydcTBq-V<`tcqsL9t@M87HPG<AkzK^P}+;
z1)CXqY^oD{qcUI6lCN9L3XK!9L*v98|9M!ejd5bGo)zg=%?d2mw`ft71PtbjTSU$G
zSM|>RDFuIJvF%`XAg~#6et4$=m`=6cUDkR7gy0l*>uDGK;Iw01L&)mUlcZW;l6%z(
z(lA9smzsP$*{8d*6;s^`_Nx_~92#*w%+K?b5e+%>jWV(T7ZqwH3q#a4HW^K57Wusv
z`#-h?TTzSOI8unF6n=Hfw6&P(CH8r|!Wp0R^GgFYSv|iD&qIpW&o6%ydMggRZ42N}
zwk|eL+uv!Hps~E3L!sRco3v0!k|Gp_7dc6>6l7vZ%0}5)#8#%>jMW$pW+9AD7iWdM
zVYW}+u%&5s37RqqQd@338|${vOl{q+Cou~RiJ{>`NX%kOBJgA#iC7YdE{a50naIi4
z>IU~aZ5;@PA|<3lD?K{m_E)lK(rQXOmdapAIdEQ*{4NVN7G(hA;tU?RB;a97J=j|o
zKo{OII&@{*dx3DzlD#*VraYNX(Y3kUwafD7sHb<7q{O~U!YA}@k)?N8AhtLI#F~JU
z4}3G>7#2`KEs?G8sUn#ztQ2?lQxFb~!it8jc0_ZHxn$e50pyN}F6NLc9#oS`0<*xE
z#cbzg0AIk?HAIajt>p{<tS-D!;pb>-0J>s4&jyWjc6KC-)|160$dY#Z3hy9QSR&*N
zglB2Lku(8Vyt7Pe#wgMq4^A;gZF76^G*nsp2j~)tR=ZZz$-8SdtmNz9bbt=^UDu&=
zKnQ57aY69=*Py)4AA+u1uL-8SN!QW+z>ZDV(e2FDfv|4$tpV7o3i`qQEBptjUSHW}
zd!PsURj!ERUnuAg<h`p6(Z0q|<tVz=lPs<?)tvn6>05C};p1D9JNuQF25Yy7pN1my
zH}D#PA=qma-L#$_9O}-^a*fg6!V4S=vm_&!Q?0^pRj<|R`cSyafmL$Yc)4t==Oo*M
zD!iw;Sd_cDA_~AHbaU0<Ehw)|h@>3z$0rtLai&bM$Y2EhpooX^UJb=GBf$(s0AB86
z#tIK*R+=01xvSIqLPc;)Fqz_ex+r7>;=0>XEGxrgOK5ct%-Jwz8{2i8F+aD5=I5%`
z*5$Kl#_S-mhpW1g*e`a&XEVO%gM=2^v-sCM!@r#AlMuTw&CPJ=!nZ6qn?*nqHJ{0}
zS!mu9z^Fe+3g%;z-h-zU%?|c+u+`}Eku|PBKC(7sE0-A@AcI)vA;)@$KpRXOINgQ*
zaf-m}&)yi|kRZ&apem>8y+l*v-70i}6_eb_f(UW;%5F2NE;FGCx3BCHCIjn<0z|Vn
z&{QxnTCen-q4WChq|U3E1$<c@qU#~81;$Yl^KmzHXH{6ZP7RNvCiY+#gX~9R4{@iC
z$7G<)Xu6f=BKhXpBs$*XQ{-{WJ^EpRM{xuU!8(wkedI`?Mksj`2I;Qi=}&M$HQI_(
zm{t-dUG*TSku#4A$||qv)jnE?@|Ed9$Jeekx<|X{9^%@4nbJ1aDQyG#l|c-*Q)rYa
zK{BXPb{4V-2b}WjFp|nu8cU6Sg+4^Tsv8;yyxCKWu6B59^(?lz*5`X_O0Gkde&6D0
zs_J?S%L<~<w^o4w1nVbS7dicn;Yi>{&$rxER~tn)ufk;6PN0?5Q;}PPDgYAB#0FKU
z7>%r?L{~>;o+T@@-KfG+aVqjtgN;uO8bx}6#SyG|-OkxU4U9gcGaDFwo!P+f>v*!z
zS~h0F|6!@Y3$D#FPfWDRmG9#&!?7^SN5WGjT4+^$3O8q)424TvkH)?km)iv<r(K}Y
zb_pfR1@*>(G4ByK)3-9XL2x)q%XZ5{b!dgLDOlS8A#;@n@b&v6Y!U8`0RE9tCQX9Z
zg%zV2xpE(t$?wB5Zeh<->@2A!)5ztE6dGoObAP%{yG=pr^I)|Z)6Z$;<fN6F^8!B1
z9?nEK>Sf5whVRRpG!!i{<j?Z^Om43gaCfLp7=Fq*kQ7ua)n{*AB{4kTBC0W~ULtO#
z<Fu}lxf$grkVRoUYD)Fy2NVvvkrQh*kyOf+k!J;75gfxu6zoo}vZ|NTZpHW149Fb*
zT^eX)fNfFzl;zcKfQ?2qv*8dBnkch=IkfwqD=U9mW1`c#)qiPL>^1<KyEiMH(%JZp
zFHW6%vjR1vCTUP3U-r~`qa5kG0XGIng}@$YLB=8@Pim5D?38|87!tyn`0XHQLa>4;
z<<B)9*I#RNHOioA3k3GNEuf1XhT0uAx77ju%dG)|<HpW0tT*i5oxW72n=1lQR>WNi
zoHBM*Z88w_GzR51hcVb3e9M43HtdinOAH_`SyO_Bc_VtD{Z`|4V1gO>bxRF625t;O
zw8gw>Az9Qmu`<}IRR#+PzpFj;uwHG@+MI|2OfkbW);zj~*pb7ekD_NzHSs89yfE(j
z^Fs4wovlCI3&Ue)W0ZSVIgQ~X7yEv)ad&ST$}1%ADVdiJbdE?X!cF<c@@0(x3ji(Y
zx`n<#quVW_<)oQBGA=TDZoLlFiGx&dH!r{(qyN}%rhL*P^w&GjXTrP*D`ecAnmTpG
z6A=~>`6Lh0SyW_2zdLm`p!{N{+0KD!BmvWdPSE*To{cc#aaOpuM)t0zu(Kcob_f%8
z&J0Xsz{v#yB9{swF|d*4kV)7uXDtQLwGF8$Y=k<JqAO#iArl50p|{e6#fvmRk*n2)
zlz3n<w<%a;`fCU5hU#<%4awp)&ESN_!j#$@D!I9H+eF75YDPnR4sZ^f+w`$-Fiz^3
zqaWe5tXOj>6PrjxV_iqrHp|0xUCMqKsLCc}f$9UpaBc~xat0>71w`j?I}E79evuzx
zbz+JFmwDQN_SvC7f(be551Y<A+K731=tsBF=qAd|LGR#0YOxv!<PQ2)Un$D9qS-F;
zkp2i|Z-57aKl-a}*IEnLonK=DF2Eb1fw7IBcU?dM)Qhjz6XIJL;GU4xi=NRN(u2^Z
zfE&Z7)Cb(;zmh%+X|uyE#?Th}DnN7#Jryu5%>~|k+u|bKwg|A=#24_vN)ruZJMbZS
zEZY{&(}>4{HBReYUcH}jacooMRxOXyXztj^h4m~vX#x(Th^zrkpMfk1xyDkn!KU|X
z<$Qw2j_i?j5^^6pSq|YdCzUWBQu)vQsRuN@%yb}7c2G^?0&i-|$+Kwhas#Q{ph(-a
z{JmY(KLI&(-~xeez{*2S!h{QgDXa9XyB%I)%IBCYoc?-`)i{whQjOV|WnmEDLaBbU
z1W9KQA?-fD#G{T&>#gd|v{o8N9Yp1^s3uDs#|!|gcLE&4W^JG_279(fR)qYRCS7Kq
z$(J9sw~MBcjoe!`$Cn2)m~-$hsGNbzJay1<I<t<;w4dANdbwe6mbqM-*<8pe80P4l
zAEdVwG2qHtE63hvof*Y=75HMO@hb4^j8}nQXCi>8Izp|6a$7-DiZ$Hud<qW`>I$Bz
zxXcxCfDi?3hT*;SMuzasD2}vm^ho<AV{QnxdJ(MOnp3V+=9H^Ea|({gQ|_?#lBAKn
z#Jp3?BiR$IMJO6d?C0VLhk8;|h8z4%;?&lkvx~^oDL!@+W;D9lXc@Pp->i%$w`wg{
zo`XTeUx6qZa#I>b!|j;WZFSa_?VJZr_>OiMUQ}$C+c-~LuiNXH=5vB7ytjd%=9s79
zqZHCY@hv|eLZF&x>+hHZwYgZfb9*q;XOd0No@qlOK*^bAHAZC~YBq$y&?Nsw^xV+)
znb60{U@>S=0Kj-S?QTCROy}J7g7L1mR1@o52VG<Ku5iG!$YVQ;xgEQt9-4BsLbwsl
zD-#os(pn|aFA3&3NV2Cnw~&%E)>}36_36>V2B0&3s0lgevv2LNi-6DLBIFK_V{mx1
z<R^={8K-o?7Oiy}P1LWWY1r;h>UM6|LPM_qKqLEb2y{?Gg9`M}T$IaAA{PwXJ4YrF
zMa;B96B^gdb}*obd{${EM&lHU=z<F9qR}&T5s@XaP2m$_T7}b_!75*z+A~3H4XSXL
z8G&$}r{4J?XpDMjciZ7|s}#bGhCGv^ZBhkZUSaB)45-c<_o|?3On7s?sdsLx_Ehsx
zHuma~r&%CYKyRI3nYowZL$;>kqweU1kSpOZ;M`)(8mkl(!|p;n(9Y=^JzY3MJwk<&
zh^8UTL?azg#xI)ag>sj6N8_okDiqpX4&=}}R){}!$VxPFd*>5_NzSftevAn@Ce>q-
z587ueJqI>$1!<Ws%#JiK_LQ+v^e{io$YgK>%AsgXP!s|d2~w_Hi=>|`*YJ+Kc$Di)
zj2txEE2CjL>x_dY1p@u*?BIN>U26#^*wZy$1oD8Ew=}?L2`RAUQKXm6n{;2k6SKaj
zBq=5!vTC^;2lqFBme-#tH$l`ymQsDJtP`15dE%WU%Vs2I1R(QI)cU6o162e)=M?fH
z$vDy!xHB!+=Tv~Qx!OWa*6i&;rZVEVAY2%-IQKA69tIPVSjiAibK*x+L?*D!qMM|r
zqf<)fg9RCjhDleUL~(NzTZoq?r^aVh)#1TR|Cj(Q(MVe-L4?DALrBr)6JUmu1bH-7
zG%1Zv+d|-c_KoD17#|<gPID;3OP=NN(>8RHhRBJL{w9Mmm~X9&Nf{JMc8-j5#)Ldt
zIsliWIrO&oED<(%1kBgURzZt0Q;ukN!a8%I4ke+*(p2m}igaQ0KM?%UDPe9Vdsfrv
zjENF9C3~6YaWlx?Xa<l;!vb|o2NgJ?J5A#*p@<F{3~;<cnKOrK8e&7=FqE0&j1aH1
z`#Wh)utTRv5o1i%iCHGUl2%MdCoYo)#uRW}?6GBx#Ge%sqLI0zDXj_BM*xj6mRLzX
z>yW?kO$bzgK)P38>YV-3VdlpNc{F;A-EMD0?=oj=s}TPd70#tXKdsh!EX+>uZV46G
zERo3gxrmxYv#Uw)ZY#RAdaEBWluhm<QjJCyUF<apd1`t<Qm-~m`s|{i(n$&0eH%%e
zoV`hFVEtx;(0V@OoQ7vXnx-}gr>hOZ8Q%W*Oy})8OI=3M?9fG7nW*OYuSL#xO>gw)
z%xy1ll8h&*uAR@Ve4kO}OQ~#=&6d)iSiQUh8OuA(Ti)qvd1YOrXr{NkdQG`Dv$?!{
zJqvS80V`>i9dSa8<&r?BmfeUWW<~wcfnKO(H&jA5S~Qkr&*mNQElMo(gTOfG*Pg&-
z4Te7PX))8|Ws9hI)6=S^r_Gy}_MjV3zN-E(zu%5fR;S^i(|-;$07c7*5iQg2<V+x6
zPoN0`YO;5=7-CVu3+($8v1kn^vMtQ-)vhB}$!E2<ceGdANxPW#%SsEbx+9&k$`Czy
z+>tz8?9N^(4ct@wsnUSl<By*Q3wpyDBQdn&($Dny&*-|TMo;VaZ-VCOgCrOrk1~Ml
z8Gtt^q5u|DFN%O0yqm96{hT*nC%p)Ua|tw<#WD*sHC&i}w-N&i8>jh8jZ;@@VP<e)
zusWCY!e~+#A`oa)^Hsqic7ICEg81t&8uq9)0M=ZxIC0LWK3F2GDG)=QwHojjN=O&^
zv?g2Qm!U2SPLi*NP8b(O7cyTzGk(FiSKt+ffrBauLih-TBOn34m_>o<lBHd_+!b9A
z^6}YFH7opk>^&_o*Na}7!;FKyhsFxCflBR6M~%KPRg<%s`t&r9OE0lgKQ_VkBAxzG
zD3qPylwLR{{^2w~EmR5jfFKphRZh<s+e+yDGeCaYujPV9gh{><zPY#gakGgs_ZkaJ
zrv?|1pOuBBD~x5@Ocp=?W3?t3d_Z74gLO(9WaQH{PEFC`lvWpdlx|L|3^|S8^2|Rw
zBxdE@32Y+5%#3NHc`jsOW0DsujRNTT8zk@X0`7+_G=W8eTu92X)@7*2!;7bpU|u(%
zDMy%}9*Qi|B4v5bqPg>lRhA+&4&ynXVzNV*-3`JgPz?zTqp}-h2$9<1_A(N1AIOSr
z3^3HAG7^|f1%hPk;zEl-=rdLYSo0KM&F2SF5nDh2bP(1MLO7#5D`%&PCp_vQOw%e0
zMX4=p3!gbS<=|8gPHE@~UAzErX9iA_!Ew;g9+Uo{9y7ZQN~%0=UP_f7e=CS^(<`*j
zBVeRU7Bfk}`V;|U1{EtM@X3DNm8EC{ZVw*Ym81wNxEec0BclC`pc8aH(~?@<VwT>~
z(#6@~F8dt+d2D7HzBt!7OBntqgVOwuWNCq-Rg;Z65uCyuJzx2Lc0?(=0y(oY`BSqz
z>NT?yU@}sa*$EdOrKG4uA=|TDN|>IHslxQQmCYt9Zyv-d*~b>@6gZA@Guj00lb0cP
zy3awI^T5eSw9-)5t*ME89m&fjkb<(2z@7$^y7Z<Bs<e5_1eB4PBUCL4p-Ldn?6Kmk
z2I2^yk%P3bHQ>zmgHUcEDOmFkXeif_x(FVVUBFMX&>R{Yhc(jbV>6nU2H3MvB`w8-
zh=zWxm5@N2gO$iNB##$NjI~BY?wo^FNY_XOml-MugM^}jAZ+SlW!PE~v;g)Hl*q`%
zCfz5Z5}7JWyNJDFiiRv+=3_>4_{|Un)f6RZ;#Af`uw|7khMZM+k?r;BEZgm&SXm7%
zbRB-@uzZ-EpDtrEg~g-YQz)h=!}ukuSLg-S`UZ)V(=oIq8SBJ)M-<W68EZWYn^mtg
zgZ3PM@jR(v&|<j<vpU}svf7e<;tZvMaCNdAkIS)gEo-8+oK5m$uv)rHOmSg^g0X6e
zgHTP}kdNkA*J;R?#;POTbiEaa>+fx-e@air<@&Tj_>9hxYbL>%DDfsl@v<lR<ry#1
zGQxU=_w0u<%2!~;w0AfKSNX`zkKC-k+R9m1>jkkD*LVw}b6;H>Rw30^_)0TS{o&X9
zBt*$xTl{fEkqIb`ml`5-qd$(E$XtZR3oCnB;0ZB<@M?}~;|`7q0bb2HZCin~d=7U~
zfamP_Ue6jRjTmM-G8%%{RHJ(;Kc9JtzUwntO|THlj94d8<P|4g<6(@@skMejBjL7B
zuuSKAl+3*y5G6-?G_C}MX@ieeoGz1&+hVh%>*F&nsl9}pcU2@U9?MtwdZphn$cW!U
z9cL#Yu|S&RtDTCA$Jp2uUp2g%9XN|sVZc{F<mhQM194zkh&ZGP$jGFy3qd#Q<y^ro
zCm&es5_D0>qQ@Etx<nSl;0!ghK+t6ihy)Eb2syCz-dHuK+z?g)A+vkXv}B`?R|@k0
zKR#XsxT!D?i8cKe&D6<U9M`$hE-W*@hk1_IDOlEklgTFo#xV-sX&AD2J7IVy>@>yI
z5J14^c>z{}F@_w^G01@9c?{ChTB7KB9~)SaLO~+x<!P)0-euvnp4?4ox)2~?&LFSC
z!f;wIb*<S$(}v(}&bV7dYoI`D(4zxEzz@xiuYLa9B5E2LoeG_Wj10&dAfpjq(O8M^
z_1KxltrTt&u2M29_2Openq%kI-qkRL<TkBdf3LhLb~a?AX#`+cun-|VUZT~%42x{o
z2$n3P{xwMFuE$fKh0H>J7GHJPDR%?DI$k!aKipz2qh|-WJpqWC#(h|>%sY%VIxtwl
zT;;b=;%{KE$`wz$Mi;%}nGz~9Mc@EcmxNeI)`F<@#1gSXD_s%}3F=}+*jlX5p=6rE
z-2mONvEs`BW~>^osd@&|xx?JC@zpfu)bmwu^ja59AuJ8gb?BCBo4FW!W{fh;7srNd
z9+ZmV#%*0%{0R_3<4=%Ug-V{k52V4}H@Tw9-~I`@)QaR7WY=&=0lJ5|B`_e^dD5(G
zqc0tc5bIhfR(6HYV;iut(6P?MtmWAr7bfpn%0+25XpPHedP_I=euCB$9#^oq#d8ab
zu$JTkB4c4|1M^q$ccGW)`=aZCSNTL=b-PSW`4a_i?|QipA-DslIv=cvEkU+P<>BXe
znIK01+^Y?ftVb!sEbFmn7T73zF;0NkxbVR}cmcO9>_l*YW5FIPj#5-?fGo~Gz#s}N
zpym*qp7tDBC<vXG#I4E|#CSK$diWY!6M9?k9+(E9#U5)B@()vr66~-m=pZqGL*tAf
zBOx66&Ip>VWH=-E{V8i8bDmp4ye?p>YQx<IuMPAwQ#4!PnU;JXyWwZ;h<-^s);O3i
z*9VwwS%Q}`Xi-Hj;H%zhsW!+AA)(FpMyFF2<1blZl@(Pz22GbbqzBI*o(GGp;7v88
z%lO-L3;jbEQ$qh7I@)-10r!2M4u;PAc)Cw{1WmO=$AWR_#;Pyt$B_;g7B$U|Q8%6L
zzma2{p$-JhbngDMl)L|I<qI??bm1QiUHIqvpNs=*#)W^rap7N}S6k*x0eQ;Ln$e^e
z(XVW=VG>LD%7C^n^;chLdnO0))?I(@3R!ODLgQvSP5Lo7=fY!55E_(a;KYd_5jrc(
zwwZ0=ObtPY#$s>LS{?`x5Q)-RhSA<O!Uwo9=`Jo$Bl||5HF8X&SO|UeWb<GPjTPA7
z_BRC7ATcAbK;Ujum(2;;V^c8K3aGMtk?`E+kh|RhYE=PhhXJ}yg&tiYnwrp#8X|%t
zeK^o(P}Bu=43V%ejX~z<4EozDr$PG_1`YVAz(JF>1oY#aAD}TvXHGl_pedxAM+}?q
zlU`MiV}7ujf(|SUSKcV@8uDmluq#49G5gyx3#>2}dt2e0P*4?s^5}5nmOB?(K+P=(
zVnNTF&{7XO=Ex{PYk@hW<{Tz1Kn2uLlUI{oQ9#s(A6wBxTuB2X57SsS%FcWnmIy)4
z?rbQnBwS=$L)R_f8oF*P99<Vk4k-7!P~76`q$GYN^#mSD5cK^|fJMru<C!XQrcC67
zAR`ZXu`Xoz2>KFI!~6)pBHD@;Q+?Dp_3R`h7b>is<(puPz*&j}8;r4FSx<3&6eVc;
zd!$;7cV=FL2+p}U1Z5bP(xN$`JMbQILXd{GbZXKtP`SmN6q0BZNxu$g;(t-jHnfvA
zg^LU3#E8FwS`<<6KYui~kt2b!j*bHfn#ZuoIRWU`c`^79)U(Vzw1(n5sIeLZQZk9H
zG51)ZsNT;s>uD`xHE?~?BE2!I+P<-U&$x}w&D08TS(pfkDwMhE_a?HR*Ml=#ftH<N
zE6{Wp%tLdsKN%oCZH~zU%w%S<^U1!|I(<zacAz@T&*D1E53ECRXWBkwWU0WCsmwe$
z-;lK<t+9ZIp{<fmnaRMlMGLn>fGY2p67e&&+im3=5tKCNvmLGV<SW_qgRrD5vnGSP
zZR&eeYv-B`MqUFuP)|AMO&ORG7d3vt5>!uC^gZJ#7CfgXB=AK^^+~6czzVQAO$4s?
zkvN!+YcL(bv)B5P0cZX?Z+^72dVN?GMOzvQlyyg`xCS@+1CFAb{NYB?&Hj+0=oWwM
zN+iA2uTtE2t3T|?Pn(P(INz(Zdy;dTa$|pa6#;RUu`GNUgZoWLfC8+jXTmxbCSJuX
z2#$DV@n90K!0r)ja1y87i7Y#apreUp#xw!vrn||Pv@V2cN#B{tjKNuhjrjCNJ$SL@
zm9Y4F+bsZB(%YqGn{AodW?ODHVAM`b2N-M}k6%^C<5y?!c-rYK15uh}V5w8c8XR3x
zRqpUo7XGf+ID~u3Roggx+6rT<vlS`E8z8hfGhrKF;ju8y%C9u6{3^rB!ABKOzdCFk
zMb~8Gt!CEOrU}4x{v?qAT<@<vE4HYYbG2?@0CscUSOyFh8NN?_o2C*s<85{Y*jE<E
z^hXp$Tk9F<kUyg440JNm6Mysy3NQA&h-Q0jaMbN3ZP>KJy`~qU;)!q{k{8PMK0Wba
zS50lRJ)~u6XdKN%?o%0f!>GZICmx4mZ6<M(Mw+&8S3gMH1h)aR#n>Se1LIw1xW(9|
z_AR^B=BLR$C$mOVUyl$&FQ}i1KB`(^@2;kHAZZhH{s(xHTa|W#*;T*WJRMM*r_MnD
z-$J5b90cUk#6dvOVrMBwlt1xO&=1TCJpyL?gFv#fu|rQiX1UGDvxlTGe8;ko%o#lg
zWEC=(Pr^v%GX2N`LO2@eImnqD`<eAqof9!w=%^T&0Lzn<h~<!UK@c<=cGU)lVl!@6
zJfvi2;`=%Z>AIi@ljSYoW#m4&=`_=HIzfafuocksU@MfS1ncQ7y~;70e9svl!0H2=
zJeO(=mQ(!(5hd86bEvj3EIkJrlu_#JQ<wQtOkFIB;8~;0iDbk#p1nU^<om+~a>8V1
z`Z;cS;;_;ujANX@hpIYPOg}^=CvVmRJmpQx)Qr3tR2Z|KMTyj&ga?+yOyh-Zo2TMV
znC4oocW3ZqZ04@W!a0mz6uBKHhJX0H!D;4cpdkbr-P}T;(Wz{O(Wz_&!VqU|(`gt@
z0enF8n;aGgo|_#zZ80<4#d3)H6Ffd&Bsw+-J(lAK{hwh}xCnBeOay-PA%7)de<?u5
zhWFHrhG2v+wF-eWiTAO|5O@ofDR}p2ayEen%my4IMbiU(Y3k0JwtX}M{<_1TIk(8M
zf!iq98`1!&;h$Sh6R&Tif!=r^S)S6=JwrpfZR}76gHCY`6C>B+r`uDK#wq-y8WO1C
zW>3jJe>t{!bqj9ux*esUJ21b|H%L-uZD$}#XjYD~hf>x}<Wr-lCA3yow82)!hI4Vo
zTHR)>)$O6Ry6U$l{qIobYZ$fZm!s52QmHPjw@Jrr*lnB<&TTdbWk#PIhHYP#Q2Iu;
zRS0tz?7W(-5xpp5IuYIOZ4pd_>K-r@r@HG;a(F|2m*Ob~AGGwwa9GyV&|IV<;M5<B
z_NfV<=Xr^s!v^QxavAL+m(kL2kV@EN;7|+yV>m)#wU9I+CScOLFre#aF7V{ES;!Tr
z2q*TuY&!a|(~LHc(_(K)x&F2+msJ1Nq7GQF!$WnJR=T7H#28_I-9|5;uUCQf8yZpR
z;5CLy+d*W(e!XcmjSQ&}zk$xd7%&0mG$z=D2N&c&7)nmgFLH7oq8hxxv!x<|YA6|L
zmD^XTnWol?2x@yH70*5Z(0aFT<D^xOTiJLbz*%QrI&%&Y3hn3W+-6#6&o|)C*#=x1
zTGQa^WcD=CBS|#dZMdiW6lpUGNUBkPZHv`5Rf=?I;avi=_}g0c4qwDT)E05bTyhZ3
ztvb%CV?jgFRJRY11+?4;un!QH>XL_>eE<uzD-GSv!7c|o3wAzd&oU%hmK+GSTJ6i+
zU?o^u>3F53l)>|2e@mI-16nz5*&slMdaI&7`~hU3RS;2u?(8Q?#@R2P%*-+3lEDZI
z&skKp-i+bPx+JqHsvN+qb45t^Ef5xUm(d)i+!>t<JA2_=oI~Bk3w1u+D1L4Zm|K4A
z@-zszC{WTC13%WSgxPU<hz%Ea$vG{F4g0}?pr*i1sWuREn@Y7t+Av|%17TLo)UJg(
z&&jj5mMZ7ao^R+YsUX9;;J`$oirvsx89~QqUC>ZxB@nk&nWoAV0D_=9B=EE|Sg2*i
zWd`Bu&yt7e74U+Td!)UW<3WxGjq$*eV`Vi@<AD#F3R8@Gi$J@oYARK0W3fe!2L6j$
zyf-x7HaBNLZACp!7;M>Kxe^*X!@CIn$Xn|hNz7i7+)HiPdx&EWfLaEc%TE`t{4`E`
zH83NEJ4=mGa2aU0wT=kjD&&HF#MgZdCJA(DOfoIV2B?r)%~stv@eM6DthI10Fz>;x
z+r<y>kOi5PR<;|a-r(2RiVb1tg3FcC>M%w6^stD%;((zWFFydGNwVBPHLAN5&)xvF
zFq#ToYhI+E%!*W!h23bLGryeqS>~64vKB(KBsJstY{~x^ES_m2=@^1`<S?4UXfqfc
zm91DH4ydvwmh}z?X<8rf8PaWtXoiqGF-mt=FQ6ImYn^t3#301rX-AcXTJ>&WX~YS_
z=yFt>)QiYz9AlBbJ+7AvXt{u9HyY{$G#~PnNY?z6qy;Pjo!PVneCthH3*lLKm+9AI
z#W_JU2hhgV!1nD-04b~r<+4UPKgVlA-B|ABq_-@LG}4=G9wc(&c%8tOejd37eBR2&
zoAtQSl++-{%N#Eo<7J3Q0oEBA%wmR-!EA-ub+#4G292sZ29`2b7}Y{69`(m9L;PDC
z;$NncrMnvaSV3U)t2=;`K31ULtPv{Za~I6n724)vQF&~sL2`8|_sFwGfb3&GI6dMW
zOmMr8S%_A@Qy-#v3iIln_Iz$lmg3Cn^11-zGYlif_K;>)<c*mJMXfo9FRM>RnntS2
zdAKI$Y`N~%On38P*h-vkw?|p^oU>pS9@Wd8ey4=hQCM1tcB7z;(dHn4(oH4B#Da%2
zPsRmE6hyn{NH>P;(^u(?e@s&;Gp!_2%G6vmmooDc+{S{P&Afm%R^n2KXU+ft?M#wW
z;9^7DM?EHLc$DV_6Vs^KlxJDQ%wkbAv;@dh?_uVDknpS!8?tQpWPTf+-U$RGmK#;i
zeus@}n(J-3-qu)e^P$~xH-C$(0cX=1QawKT9cFMg#eR&cX3-~$YmO!m2AnL&bj0`8
zA979OTD`jFuu3CX!winvl$tsiWj`*LDRY@}+%jc=b$S;WctK!JIWrl(tKt4YnyJ<A
z4}?<OS}QZA(Kl0i)aW|~>Cqy%@W%jS>ko~Gyf5clIo~=HzNJy70pHRnGX}n;*@YFT
zT*!qGs8h&z20~vB={ck~hV+KeHlYC!^5d;gtIkU@I$tbR68O1_ff;%sSh&iPz0ZU`
z+77dH;rje?{&!QxsaKBErlJPH&mfI7m$xTFQaTfBDNp=l?KE>60t{lmr%fl!l^)nq
z7Np^4vUAZi1o-1uc;9W(=Ba>OUhJ-(bnLEP2^8RM<S^=^HH|S(M4w7R!JHGU7cquP
zS-<YeRt&f#6w_1^3YCnRoud)WO*4W{&^dBW=-^_y#jG$1#q2N%#T@_nC>k_LDCU|J
zCMFrD3`$K#c3`fCAj4tuAfBBAl9V9q9V>#fs;pSnFoE4@;G`KQXdSnZN?x3|XNQ%h
z!O5-&M#RbJ*6S<-<ielZC~p=XH9$-jRvH3~XP}v%29^bBlCv;Pa+-m}WZ*Gr5Xggv
zj6HaW@!D7R796|0rS~eJ4r#<<b5BT0m_f?}C>*v7IaD)nVJfW@1xc@7qKT$O;Icva
zmM{WjMMYR_HQb}k(W3TxCQ}W`Q%4wmk|1MAC}KvM=#$+h`s5T20!fh4)a6oPNFhB*
z>Hf?Q9SA8V8>OtFz>=3xPLAj<F{$R3HsnO`(J*VmbF?^@;*+ihqHhRXu>qZuk_r;D
zu4RT=ZmEZoO8A|D;jYzh&X39j^z$`<Zfu4X4Jx?rb~usv!&kCKS>FX#wuIxZgxJy=
zVoO_yE$wDjs|H&-LQD;?i#$1%YAj6xE?F!y6ju@8O!#sOYI2-n_0CT^uk^Czd^eh_
z@+>J!Mm@s0OmZQe@#rZM6#8UNGh#ysmHT#`d_UPC#gO6L3gD~&<UmIM6F#Z+Kb^fY
z8$k396dA4+R|q16nScXBcne#MD@X<t!ZKL;%8+eSzj7X17<8SBGMq-tYk5zlFAr>B
zQ5ZBJ6%0c?5bR+~=8Le?2CR1yk;WY075I6EjfVNovmsq?SW!C-AiZAJ1f-7(^a;gF
z&BibMs8q`1<sqocp&4}tPWfgCCZ3BqAtQJz?!B&sisxdSICP82PM~vEUJtK61y!_p
zo}$glL}xQ|hVUDx4E3zshb7w-7P~b4ro}FRYCsTTV%=HJj)-+<|CEAg067hmWI$7$
zakpO?cLxN-J>%|qvDA&i^es$<uqPb837FM0`!w_{4XGPR;4(u3aV$v@x)os~35k`a
zYe96^kPrLtmtp5oxRcUC8>-Q{CaZO9;h^~jhK~>gn!q?@)F&++o8vped)atJLmN{j
zUk*(nVoPEEno<)COw#nbO#4t^VB$b3X}oN8u9s~FAKQ)aSas%^4rS}?bmTpA<n94u
z9Dsd3Hx5M6<e>f`02!!-q?@tvJKFk&Kzjc7;d}&D(o&ww9m{I?*o18Brio0QkQgNS
zAi-HaKFa6Oj}&}q?w!^X%DyF-T&l$oFS9$7-Z1fZX`GN&RYF>a*&**_H?R|jX6WwF
z3_ZnvIre6Z8M@b)p=+TTy3dM$;0zRjjFW&c3OWz;t8IdTH1DOXNNL<M<8$sRU_1m&
zs$fr%9<OoH+pDWH6OBe?9KSg~T*N?AZa8#?!+J_PFPpJwafmzqfhxIR17wqCD?b@F
z_4Adlw@8d#d-Ts#q>_<Ys{<)uz2+E#lBFGDGy@<7wzy@X!pJtujTDR67TSDfc6wKZ
zty5+*XDYU@h$1AzG;dVqWaTdDwP*&$R6=tCCfR@|l@VlA0v3SinUSxQ_@dOO#K||$
zQZiCQ#k$ghQ|_k5{iOzsOWXeIUDeX+GhNjzF`&G=Xf)O~8EJz55n6Rp;&$#28%0fx
z?Vbuv=2Iu$*0Z-+;7TMfFKmC2N)-?)NOUtAjisbWi{mg!sI8o<Txo`;7@0T&eA3j0
znvxX(siyU$RiR#Am!c|EQ>sv3S{0(s6sSV|PKz5*THNHwd3?S#??r&5aT*>SC>gnh
zX2%fT&J&QOA?i}(Uya0X8^{`V1e3Ad9L^b69-Cb6Dp1TPDW6mVYomo%T)L4{SD-s(
z>;wm4{cU6H1!uvN7>QH)lv3Q!#2d8R9*j2_NJoq}XxRY8rO{ZOBS`0m3Z<z|?qN7~
z&wj8CyVekmFqM^d?`YLxeP0ZV06KF>aw)+gup{e8U!iYm5V}&eFi8QVM?#l#6+>0M
ztC$8x+q^+~4Q<7$kKSz2M0&S6BO`wq)Jne>zGT`MX5Z@K(1zWR2)R_!;k_JjC`0n-
zT_6eeIZ1G;k_7ve-aR>X-+XGQ{dq{(=clRoI1wl8mT-@48L__sXjnAJWI=B95Dlc-
zwz<i$Yb$_PLf27Y#0{-6H%>~HQ~DfWb*zPu(p!6PJv13V3JZ8H9FIu4M*a|4*FdS2
zJ|;WFQH`cshio<SENhn{R{6GdwqH7FC3cQDQwxos+M<wFE=~&>OF|(d*soS3*ahMZ
zKuW~j;Jg<psfo^DVQeKTqrfGN%_ckK<x*|^)>g<x#Wp-K%-P=wBm4!d)j{7_sGr{c
zvgFW^JX_%e-ZU^%nq+`>E0GgU=_4LgG)||OgLKZmGeRX1ij1@gkYh0g(uPNC0kNK?
zYZ$aJTp!H5iG)xeU(Ytq!hp;eVS$B$nRqmYW@O^AIv&x9d3b_n8zf2;R+8gSjz41%
zf5(q4P2ru#gaQIjd<iOoV?spVbe0YiTYQ}gcWh$&TXf9<`{D)cv^1TTwnO21Nj4~I
z^BJRb1k{pNi2xLxRYFL2Kx^v-Z#*4z*Ie|;q4eT~(oh8))z0h#j<Orq2{6Wb>%pOz
z7{&*o+2|nBKyZAMR5ypu96qgh9cYXeiokK*7KSFO+;P*=stU|dpW!QfJ|L>~=`F*?
zDPhFrW5^P%gERIbNTlhzNk@*S)nFk~a6EFp-p@fC4AO0nq~EI2^aV^HN245#veBrX
z>W{9c2AE~GuC3tPWVbO5smAyc!0H%`FBTnx4uuuvke)+&ratLYU1i}0Pw+WPuyIa8
zoyz$bP+y}!TBvs$d})3pxsRLVtgqic*F&{^yOam%zKK9C2(jE%!_<6mG$s+~8THwb
zed53wxgt!6fQ&xO^pm4pj&hc{IMr1lS?(F7oiRkZqj!dc*yCoM+RyYtCI`nR>FV2~
zTz!oTun>gY!9zJ<q=G4@p)HG28b3UlN76Inhi5C?KDs;~ko+e0_dpEM2K~%Ur9jXz
z3AzO`I2@PxH{D@QWOJ||JJ<(cn+f#f`;CC!Xt!E~s0Vv371-xT*MCE>Put$>^<Q6B
zBVsraM-U?radPP+mp-07>0@QM4Z6x$YMl5F2(|c^lkJO{Z2Q`gGMKvq-6B4uD5=Q?
zVF{;+EoUp5xWS|)0&0H7X8`w<;gGvQ0j)K*7~3MX8x&B|26SBWfi>25I~YoCbiv$T
zh)~W`a9L4qC&-)7f}z5U21Z2<TLzFVBGeldt;tU?D}Y<GX=I<yNQ@^>8GO_dx^e2V
z&o!36iEWI18`w+CmcK==`uweS)M=byha1z_y2)1+VQpd9oScPRh{zSPh6!|<bP$+U
zcmoL25N>3D3!z5gwG{@@Y(*|k=i+n&`?+r{AK#9@j}Fx5Qc{RVmz6WFWgcu?w;z;)
zXbz%{H9jBK#wvRd-mDa0NTRJULbR=L;ESsCK`$*O*v9VgWEO=UgX1keC=@%4&bcAn
zjd5op<waHr6;UHw5D}jn7@9++A;+(a7r(+SPh=HyORtb+v4xa+*sj-C!^R#RC(s#3
zMvDrLX-MCuxmE(|_g^(&+UK3MMWFy+;?T<*ukH~+%6#`3^FA#cU6zLXb^dIK*)ffJ
z8=C0Andp~m#}}w}?1O@mw6k*{XG54QJCQ3O+@PyX5(SW6j}oZe1$}rHW6flq#H^p5
zJR%kjteeP22t0zbnCeL8B6B3uQPwO$fV4Fbd+V|{E`uyAJC*@Z8LDX&xRqhtEGq^y
zHzZ7k05|#RO9cYL?-bF=vzA$$pc$yjqv276B!)WKGoYSAKpuT2YM8_+9YiCWV`-Tv
zGfrPXZ<d5gM=E^@ggz5gHY46_eau+nMkmxOrTeEe|B!yA)9NsKB+ffnXhC$g5`g5I
z_I3y$(C###Bumg{W=9m2<pQwO;+Sg1MM-H@QBvAMK1Z3*<$%bZNG*DHq{(?_c5~6d
zy8PGhCB6oh^`&mi=O_A8I?!PnA1}oibp9G@i7^WT=NrIVkPQ$Te!^sG{U6%`Kg&gL
z94X*nz^`tZwiYyR@tZ~pQE}jHTL3Q-m~8X3{hbB@auD)T0x(i0X_)X;vXRM}gDL}r
zngU4}fLQ^_f&fSsdO)&>%4-fJ%B7MavaHpQFmdq!$r}pOtk6&4C=AvdK*?H(=okQr
z0v{nT<AWD!5Gf9<*%Wy5v#76f%hUwm&G}MhRKih-iWQ@Z0k~++6Tr)b2PA2r$d!l2
z%7d|8IAKMstSL*XNqQ^{R)dVOe))AK=(k_D#1I^ks-+&gTIMk_-dk=OO7LcnlcBff
z;!aMPCTH;8QN<m_#<WD-gpFm=rA*Vm?rZUdN40X5%M;kNajYpHn+FZtSuPYGn-7pn
z*DatUTr-7xGMGl~>Ti@Ve|bPeSar0L&8guY1=rTfE$ZHaQo$O4z$M5<78><?5iTk-
z!8x2+9!=^334~jo3W{tXW~)?cp4U9cz}DW)(>R2cj*+eM_?>u=TlH*AOwGyHC7nhm
z6u|RTI-ZV)<8&%FAVY0yXqchX5bEMgoyAZWXZbo}6wNj%5a*Z_fP)(3(B6RK+=-z{
zJ}hhC8V8BWfnidomDNHB8I&bhdXY03)ENLnNC!*~+FTLWn0;O{%ufhqXhsFN2cl5l
zEI33LV|md#ENPZt1dEDj#ok%uR!#imIU2~?f(lU6c9Ye$%H8e`A4(Pb?F^H`cKIFP
z^t0%e=op>@e)@wR4k?Oy(`vd2YHtVBr!09URjd$U4zwTdv7DI|18!eun%dVHLy}k}
zXw9;t(2z4b<QQ{8jxne|QN|KQa}A>~=PaaNP0swL;IJS=cr{wKOn}j{JtaA{B|y<)
zZLe$(;0(T@G!$@DLPz?BTk?}SO9T}g%V{NL$SnTq(tp=Jt2zu)Mw&OkHA|)Rx^6(W
zx!~)F#FI*fg7Xz^jBvTKRn0&<SK*&^72d$^9KG}&><${4dv2pcMD>FA0wZ`+0vEv>
zjxhk)V2?~A*%E1sUD~Dnsg3?+8n-nygF~T_@El;9kcb)ygY(NOCb^{!09*g-#GBC2
z4%eY`BSe?14$SMujZj{vq1zl4^6Pk7$i7&&<AEXKpx^HDpbndR8-02fMVo?taQ_Pb
z0ctc?hG$f-a>XdxjDj8o!}wlpqL^Oel#**brQ|wOO~vJUris0y@bN9lo&Cttm%KnU
zsx2N?-=MJiMim$4CJ(u9Hc4l1;YAePT5o~b8dPCQE+DmBvE9j^OH^?+s6E<$2D8kS
zof&eqSs_=O9dflfMh_Y^BqA#nx*-wgRxS5=;nIK?F7u$+`5mLZLtrh3haPl_J;8~N
zY+7%qUs$l1n}{q)Rif6s^8kyQNc-?<+~HLn2zLOM#yYeDHyWFWni;j%1n|E$fMC2c
zr>33<$c4PyA4p7CSQ7AYcokWh->49QssZR@m;x*M>qbkojN!vGgB7IPHIw0~p5~5g
zlP`y+zqFcQ`c;%DQ_5-}|58;=!&IjCS_Zh74PhUwJO@)K07{b7d%+-?9#?M$Yq`F7
zY3hsCr~;AA33}SO*;qVq58+ajpch7-P<6)k;kPpe5Wmi(w^DVWoF<8ctuRR>q=JZ)
zP9ou}X3VhSsb=eqYPP}XV2JDNf&WHRP5Qqn`@^+_dqur0aAi=1@kP;9LDeYoLUUqn
z1g^BTF*FEPv|b_DA4RRkp4etAgYBVZu<Ey`VXuSlfwz}cXEZmYrO|RGHtc3YI)<rJ
zN}idsC+HJa&EB){4^&#<<VdpalW=Wu9FtL|DIl2$MghIf5ElZ`0A~UM$<(LeNW<>w
zS?D&DQpsriGjWq@EB->!`7L$;%SkKF!KNoIdB(;qu%RKY`PmcesH(|SeI{-ioCpK3
zHnqP1uz}rpn2SMaAs4V-&KRp2V+zFU7f%~R+aMN}vS3@9fZ@IZKgDPv;jQpvxBwRL
zj|Kd{_4;kA4;|bcMY|6kUbE`CtiwJ^5x;8j`wE2}!^3gU(C~1vgojYSDUK@fTZ)Ap
zJGRABQ9m3XEes8B8{W1Zmm7w5NV^+a_`2VWGhWA6?Y{D^z55UE*>}%@m+jiQZ|~tf
zcdfl*)!MuE@4f%fWqa;Ebk|Gw?!W70`;Xjp@5+ZZUB2`3^(*h&yZ>bmuDeXNScwPm
z{O)~6?%s3Pp@$Ehd3XEvzVxn_?cVKmyJ^)r3`BQ+<{itI_~XPL!s>hX9^QFi*WsNn
zJ#=6-CmnBTP`#R8mHou(0|)m$kiK{44Yxga>(;Ce_wL`j``$fV-_`e~pYrdmmJv5;
zq3(0Y(eC^AA3k{hzE!&kD*Nu={fbrhVzHy0haWz$=a9NSbolPO_uPYPK)}I0d-fkz
z)n1F;yhd#)iuN2lxc`3DVAsCGwi|G#`w#8hec%Xg;hMMh?b~~ZT>%qV+_i7l!TV4I
zupQZrwtM%Y0HUdvk7L1u7z@@J*Lc<b17--VXm;Sh{Ri1yTNE9B#m?Or1s}nkBm425
zyK#-rI=uHjJ<eCEoBQ`1e(4c@8yezTUF<!e{vJ4Z|2=#6?K!AQhcG!0?9v6id$(?N
zpX~rudJyQ1%}s~94(hghci*S4j@)gk_U}A$c<(+v*!%YE=M>@jT?Y>AJOE5lrNg@p
zab-|{{~`Sj&<V46_eNEsIWhXR#OQ^Eq<A_h9Id=MDOavZij@zbbh`3jGUYT1*Pu|j
zrt(nIRk=DzMv}IpN&DkTaVVKNoRm)`?MIX8QL$8fEyzZ(R5+freljTx|4Y(Vxq3L6
zvMp(4k3&fnH{;=C8UKvnY#RO?Pip*A*_`z7?@&@!f2Q)!R@2>OpGt}&$(2J%@p!UD
zeh<m-xs~rF<!6%0a1w7jnG6mk=&y=*p`Q{uC~Zr+`R8b|nScH%iSY-c8^j;9oWVb*
zlJf0I>Ewx|Eq>)tQaP1Oi)-lnb;-J6{@yOXr)|S5CF|t(cKO{|`A{-tB&ne3@aca!
zar*R$$`N)~9^osBH};fIa>}l*ye7G-a$Qn8o=hn&=t=rcCdm+IulRV<b|RT_B557Q
zOjWK=7NNt9n2ixMT+)+FKbcHDo|K1@_Ti-U@ucT;(xw}B{Yz5Wf$vSq+c3Wek_tXK
zZXe;QR6eEa=c2w1WlU=^#>E<$t*&P{e{uY#Lh(ARcKol8V!}{5<y}|4;}!fH#WiDl
zB>wkDhfbW>cH*e~Y)}0)^~q)15`e%0KokD7o=AEyl;IP}8djsS6+gOaiLLsssoEqD
z&(#l~Hq{%YdN5VJ{RCFwYK%tzDK6<fvF#+vC$^s$PBv_>d*Pb;s*deRc_fKXBsUb-
z_j1I;0&3S){xB(F_<%S)*i!r*PU;g$iPK()-(DDsd$<Z1!O5qRuBV6wgu-~cg2Ku-
z4U7wHemW_<Uhwb)*nXk#t014n=*A13jb?MQG_%nx@ho`X#EBK@vH7gB*}XBc(dfQi
zd-tCm|7^fC!Q(8`#I?^fH4imR6Fk&0O>j_;Y2rc4G{H{KoN40W@iWbH#rYJoTQCL8
zZe0O{uf4JvwDq<m8BW?>m$U*e?|5oB>ApQ_B?*5jDLf~MEB{Z@{RG-}6>lsg71k^H
z_Bza7F?vfQ#LNcxCXhXmlIFx=!MPQ#8%)x9kZ(n*g(&yn{RdwmlGWbBdm+h+d`k?v
zXWy<v_d=9{G{~Y6A+h=f3xP3O5C)dn21@u;f-nHa2*Rk&kbY5XI>x1at?f*|+=#%s
zC_~$M_nrsT@GRQ;bO7UIcLwpBNXuwBUS#L6&y$3VZ&Gwwe?O#Kh2!5RjxQ-B9hD>7
zl9rRnl-DQKlMu7wUa;bR$c%lEV26?f;$d7pm9!p(OmO;i(s8nQYj4t8ytO+4!^hvQ
zq+<vE-q;BVs}+(FdgwwA9jB94$X*a@Aw(pdCrLX7w<WWOl6mOlcrvGQZPI-_SwV7v
z<~@%m1Gp^44?!+w-SN2nc+&YeAA@Y%U0mOjK)_sjBAIr)^8I8A#30rF$dGOi+4Me2
zdGjGs497EM2uG7-2j1RwGO0YCOh0z?=<xR8qsNlfki<uZlNra39y^Ni(WCOSU0){y
z$C4_>_;{&^?!NPAaX|rcVhJ-9|2Bu(do-!;u%B7E8ZX&q-qCj~nR1jfr+**g^|GUs
zf>}9?-^Y^H*Cl<JmyaiXn81%EeVD$FCVjUht^XzI17VF{bsQSRN0RDxzND2OQn`9Z
zQaO>VKbp)qo>cBg`W{buN0RDr(u*&9ebWDU(swH9hp2ptujz+6G0FvAJo+H2aa-m6
z9K%$MVQ%Gyq-}drIh}MJO)AG^ZvNLJSZ|q{De*gtr;^Hcj;#A=(mIk1Y)fXGqD<XA
zlFS)SmJB7cMv_Hb;>VJHSzxtpL&>T)98KnqB&&v#Ij>DBPb70OzXZf$4Z_{80NaYu
z&G=nslDUv<B-vy<EhJq^!rh@g`w!iJFc<H#Z6fDZynF2okp6)}(p6jlQhuDmUCU9i
zXB<fiC!mQ#6FVuYAl1Rj)u&P9Uz#^W<ytM0-AeG!bB&ev?b?0s-u-(fQ1m;u^4i47
zl?{kPgX$(?^JvCU3U(>_G|`%zvf1rCwCCUhu=<I}2yx_|T}M1Y5we<=4ngd#K!<CH
zYf3r<xEbkCnn0p@VAnp#bSN3A5SK=5gwSOqPt^J{DWKQtf4Jr?BQZkm^Tj~uW={Wu
zk<ios@L>2^Vj{J&CEo6&L<n8hjtYySXGg^yYe(g0C@B#SQzgVrYe!Yrs#0hMDm*(X
zO3seTw%U%0OKnHRm9wMj=3+<H*SmM^<6NSohz~BbRTWpts>&*7RYgf#RdMB6RZ-Gb
zRa{xCDm=H9+&Oa=h|eEI1=>uzPS9RNBPa^JCz2ZEC{!Jls$yjetgH_t)nhc<#gCtW
zOm-|O(L&h!Mp^~&XtDATpGV6US~PbgJ$Qfu+9zq=TsWM}hv>4Ta+Nk}#;qftN~*Ac
z4N*vH!99q#1Ehkq0?vb+#^w}K9x-On@|%*<(WfASeJ?3N)ErJK96)(ES;}UW_lgY_
z=F&JmKwH)<7;v9S+D=h8M*9SfV9aIPxbi;T_E^#`gT5B3^Fv9k^1x9H`~Ar@^bJXz
zhRtMqQau4F3q$;lE|iYJ5cq+lR5|jDJdPgm-Pd9UK9o$yM<*D0{CLuFBI!o|{IbfC
zBnB1#01TiXNQ#j7@KX2G|C@R$dHry*h%?cRXKRpQA;m%5qksnk0Ka+aHkqC_^jndB
zyU=gTwxkow0Es#1{hG=Hl@Gx1$9F10?(cx##ps*(UB@yej%Hq{wB4t-+19biuoZSU
zHr4hVJS014vKOl9H8!{`y~eer*H~*quTgC%v}&O?n?Ug_T?BPE<Qh$Uat&%|$u+Kh
za;>TN7_@dg=#gEJa!YnOHbr(7o7i)3*UmkM@7;O$(4L(K_q>c7NZ9+rTX|y_IL`h1
zc~4cd(R~l^#8%|tJ@<jLf#gM>KtH+8a=>igjwXLh9QvPYF$P@lWqWdyG;kKc4;1p`
z50uWW&hos45F4g9)LF;~uTHv87T5HW+g1MX#0m0Tz0-JIPdQyo-A@W-wVU)F(4k^<
z6HvI0Pvr&&?U&(sQd~gDE6xCC<&I(a6BwJ%p8zqIKjGTvPnumB{seaA)QL-HJLx@(
zfxB}G5KFHXcL-u8gh~E6p7in$Op5$-N|j*7WeJ`J{4<<%s(bVK=TWm2T=*kMzwMNO
zu_?7Jfj<JaoU4`ZQn(k#h~cE24=8&wx)vXbk)(^2Bg(H~tC8~Ab@5|f*RX+{#_rY$
z_;!dOee@ZM*2SaA>=96x!|G1)8M-fAhcUp1gQ`ReniXNYJb|i&AA1ra{-LC>?O(Er
z-6!dP0N({ThZLdCR9=}BcBqzAfu2g>+aX<5@KsZWXa=TZ1U04;VjR6uWa?|OWa`x~
zJ+gP--K%%Or3r$`fz?-R+^}xl+KpFSw)*-TZhY>}eGeX7z4yTCL-!xpy&9_9YWR_@
z-g4*GZ8yr*t;VD5!0wg%_U=FO&`REi$hI1OU`jrv+tzCF1EV-dCo?i%|3AH{_V0NR
zPpyQv*s3+Uz;1T079E|<Awurjw<kKQ;WmBK8ISJVk4bDcPF$v7yyvi*5b#&5s<C8%
z8Oh~NRD-~1u^Y6-iru(2qBbtA5dsfBxcgr5t-_`4+V!`a{Y9Gvj=qlp)bTujMRDD9
zs`1*r_diS1c2)p$X7GJhuWUMT21cWo?Kv#VHGVE-mmKS9H5)9etU17jz{TZJ5Tq<I
zYgT|P{~0VX^Wd)2o3xb+P}Y;SDMLa~#OrMnoBTDJ;C>J8&nq9xX!;WLUW{Il1wZF}
z(gcal>Mdsm4dX!!K~0Odm?n$2YFU(d6SHn`7}b04J8<OS9%z(6)@YX?=;^Ep9?v*(
z1Z~Xo#)hEqyV!sD9%aGSWEe|hmlM~RW3`-EH?y3ode=evoTA!8L|iIMNMp2BxOyuQ
zab}@ROJn(HZ!%a*mJ)0Glh$$pex6cUDEAhtpy7hL5Ali1@dRwA<rBT~$O`qyd|-0x
z$OxYr?uF)~p31qvSfre@A~j<KvLnwX7x)n2<nti$gAKXB$Jyk|J{Nf0asl`RYliV-
zAyWS_35e90QS@`ZvS-h##tc8&FUt}mER7~tpg)#ec_b<%OZPnR;6WTXv2sH_jY9iC
zv;bWsb)z&X)aOeCnXeIKYNRk-Nhh?aTSk&j_zi>T^wyHT^3<f~mTgJz)}&`R>B7Y=
zN!NB>_r|Z%q^TE#N@&y+b3q|w5Ki5YN6M-W=WVbRQXb;(kur`_tMVtLc9_3U@fReU
z4m_~tI5uhK2<<~{G5&eFq8G(XRFpp8LcgYuFD)dqMC^fBB&T)cvz}au&w4v3tdW--
z_+KaB|GBdVe@^AuNzs=${2w}eaGx>LjuQjYVElfr_j)dOU!Mrba7Sz5nSwG71hkY#
zYP`CcPHOEjoaJPnjGKdm*Y>S&ddEIonO^P{RJ6j}P<}k=#3i7yHGVk`IpBN<ngcQg
z#$Gv{g7m9^T<2R6o2(#Y{6U@_Vm)r*nkEe;(@k3A28OryemBl2df*;ks`U}3&PPL0
zeIA$sp|@-V*GAICrEkMfwg@HoDj`@jP?$k?au{;r4Ud?uK|XB+Vze=)3tCOhSu-^8
z_>NqXO`(aYhFLXWU-#`gOt)mTFy>qI@xVQM_w3no5BD)Zut6{s`$8kdzHVFvynk&4
z(lhWAyW;XM#!=bc-sxax@!f@FAfAa$dz@{mVc#Byuz<!jh~m8Ht)X4tfIQR(Uf0_{
zy%zr~aN1*4L*OtqRsJ~nQ+XSID^|4~M57>wyugi$<u^*PSdMGQYos3Xj-*@0rbtZ@
zB&l4EKmBMSSr$Jul=Q`)f!JS(zl3u(<@mr*{Kt5x6wl$4@qHjWy~&igvyk+okA-p=
z3rD)(oQk7V{pBgVT(~vqCllT-R1fu~^6>FfLj|1hq1~2;u6TGXf#-x23u0bPZdXMz
zaMkPyRgd?eFY;`5x{Wg<BoWv6+l`Y2TW>AL-9utzsDhf7hs!wGg|6fH|9-6aZ$+*H
zJWx3=Jf<dU(Bp+<ws7Kh=|0|o^`H?$kF8KX%9iC*^3{K>wt_JJHq@4Ba^+tdh0A^X
zRY+#4KdL^N!xCx>C*cE8j!(R*vRQp|0V_?vjzX^(rlCHGxw^1bz8#dkg*UgVHYDyW
zq7ml{%g|nqfBfhOzOGb`Pr|XK1@9<vZpb1q%kaok7x;T?(sFB3+EI>=zZ#3Cs^e`i
zbK??+sanW(7K@v9Py8Y-^&&LG=<wD~4huuVa4-~9w3oZ#&n>TgE;}3H%O2<3w!*`u
z93PT5@cs@NQ`^m4^!P=m%!?mkH5gjk3HTtF<4@vHR~vw3%88Lv@@>^JrL8JJlz%Wn
z&I8txQ;hF!eJ$S@KR7~ehpOUn{7O#oV4J+?$;ZfA!6otfo6++11A1!W&qln1!+Yf?
zk}kB6vzMH$a``kqt1yH~jNkKEVMJc=OF#nu4aZ0DO&keWuZ#!}Vhw(XZ3A-Rq<n&X
zBrSJfE`d6w@^gCS#n@0_1$66{=WyWv_!^8L?#2Mi1^D)Wf#008<1TnVr?&(-w+(V`
zOME{;JpNfc#JP>%{VIZf{Qcy($e)BwwB}k8xi|u~5+Zzd;r1ZL+J(FP(<dmvZ!VRO
zRyH3O{NsEQ#@Pb+M<gLypj*?zV5qcEeMk#-Sw0%RLFy<x^WC%fSHF9ztRvseH+0Fk
zk7EQRG|ON+AhrPFbn|4Iz`3DY*rvdE8hq1Sd7FZdE?6g|coI|D4yUjh=A|3grJE|>
z87hx}0^@e8^n{6*YXVLyhpc|FGG<*2R3AEC#v~PZw@n^uBS~$OvixG}c9OjIa^?M4
zo=39ak)x0IL0iF`v=FLx$Vvg<T0yX=l>n}}>a?Vw&HSO`@(BFiJIW9gZ^0wmx!%}(
zIxTm;@Q6j=@<=&89Z@8Vt3#)XD}cx)^Z|e#I)$AjAuRxG(pB~Kh00-G!%tVJB_I$U
zad>#7SD;@8(gs@58vhC2Qo&)Z_#;J5VL85m1Dcw&5utX-fcP~h1;F{DD$ezCuZ`%c
z$~Z%-%Yw%7--887P5dr&&Z8OdpX0__wH*H)amYLkP{4X&zT$_mRYjSXa8m$v5qju|
zB{$#-qMoUzshP2At9oFYDuMLL<JcXOzrFZ&vOJ(0clSV0TFTfD!yFGC7ov6tri1jT
zQvM{x?;);sQGRi?<tiB=EhxuF8ZOhfU*nc(s2qO)A4uZRw&Un6+mrU2l4+RMwr!{c
zS*98*h^($!%N<GA4m6MdBN`gOSYu#*=j}K>17?W7iUwy98udA|%JCOK=mzn+jjCp)
z`ZFDHhFVZL4E+aS1f-Hl`BP@`;|J9sF%02p#rP+W$R~rxbi{vNES!q}Cjk-Dy!Cke
zQ$U`&BqDD_0ll?=2olpf*g4ga*YRCf4AFR4iJua6JpM)kibjrD0(63aVJceUw?8&C
z0-n$nuT`hgAsf9M&v4{$CFCDGKo|iK%hqcl?$gU2zd|=Gvr3=>ZDqCTtWki^p}_E0
zF=F+}*d=C*a&bwmayTT0d<?{p@JSj(=8bQ*kaFVG@#B<T7Rh}KT$)RPQ<V%2p+j7>
z2+e3Akx-YdA~uYH@(5rZ7%2}86*u*q8Q~(a8{#P1%JMr+xj-4=|9T5(#UN;O9~xIS
zpDB@)cgYK~sU$EN11ZE`jN~r@0I*n&ZyEvF)H0n~ac|ant_K)H4u(Iv)KWfr{5W36
zPwE12P3K=t{JHm!!(#l+*Qj5L5*5H?%9X={tXOrxSQ#A^z<>A<xT#ukUQ310NZ4q&
znEZtoCJT9i=?Z{D?(#Sp=m$Jm$+EYXj}L)sC|?9(7D=J*mV;A0s&1uA?ApgC9wkP`
zKZ=HmYkEe8&SJ?c??<N%xRqXq@(ySrJ!n=y+=(&-(w6uQkJ&}J90<aDy~30&#z7%r
z?N)_<mdXk?HYlZNZu~G@G0O4Z0s{eV350-h`Ho)EQc9eT5*Jndk|IzH75Y=S7W$I4
z(*)3_L2+V1$t}~kbkpKqbS*7F-uag_7(gQ!OV??)hAcp$$Ddfbqf0glAXcwXq@zSy
zB2^?WTzJ+<6Aq%pL8+muZi2B2)&YTKrl-gY5D>dqQkT8*abW(a=@oG9Wyk6lD?9jn
zNBPuo<y}&MeG?VnR3NmFyamJ*=_!_P#hoHC`27O@8FYu88M?!vH;{O6CkEH05CztA
z6I-^IAyrR_zx(J&vM_$jt0^7-5)=(g(nlffP>BBy3r|O4!V+d)giJ6Uk77u;^?HgI
zr(^KF_?N*DOJKc)`1>dq`+94Tb3tJ-$vdb_g6xyt;v{DbJ(XrJ=xJNXn)qe(i2<uD
zq60pIQ=g)XRY#!b#ZQBkb&DF&W3PGpsEi^0^sAxc;F5fkWM5zzXpbUUR;heP0@Bk`
zjz2>``}nC>4?(mo#2>>!&0?*08hA4Y7ME|6r_rrcU>dd#4PnCI+>YazF~p{lh*3O&
z00SNCz!PDqgOH9FV`h&ImH!#5PEBAHh{*!<x_BsAjyprAj$^!UL<Q#SeHd>AN>`gG
zUHEMV&Jkli$VvbGH4x%3%^;*-hx$Y@irA{E5G^JsEB__lCp;H!;!D1dHJyhVu(Ekd
zmwTfUEFok7+{^KQO@_dN6#t9+3WftN#TZ~4FGGh_ukXb5``P19Uv-M#54mxxf=!I=
z&q~BFAc(@CHi()iYayBs{ooPMn#CAL<r4rdh*Oogo$rs|UK|2Pf_WY7&kBLi*VB&_
zlDX<z=St^aEdq&TVAIs_h$4mZYekU1Yeb6#fLBxl7k0BPrF``j_^$rSX3T)Oe@Nj<
zWivI)_)U);$27zT@g~63uT!cd(@GX$YFfDbrywGr!wgIn>=bn68|#%43hwb|uyT;H
zMOkl&fA=xK4jQ+?Xd{Ynn>WL(=Tb>kIle>waz#>VOdFt}BmN4-@}s!;2_-uKQT)~7
z2-X&Oc$jbp@&nQJ7C}PUH38rP8d}P|#B6*V2SpU8j7574L_Babw7*RR?hrYL(Fn9d
zA*YCEZO7$Fd}13WnmVsy?uGJc4B3+c@z?^>_NWNX(2L(+gxIds<oG{B)kw<6ddrY&
z6w|Ji<L}0t)EYm(CRg$cj0PMx{?*q|mxn2ygdUAYN}Q{@#&T2cfU}@bC{Gcv!2ACg
zTT~n|rv!hGCyV2^KSE1FfBazt+1U(Ak(5u1p{$D9C3rfPuWv(i8vx3?;BAOwGms_-
zBQlP@@@<%Up||hEPEmWgzq0YRksru}%6b$LjY(~29pz;6-T2-490_9tV+@8uf`@QL
zo!CMc8i_v-y9DO<ZFF#qTfr=Gw~Re~ju?x~j|b}iYf%Iy2r^Vs;%~l2j|aCt8V^Be
zz~skYd<0|zHSc>&QCD;$-w!EG##9{v_7-o)_n=ci=RXz&@B~&l^9lsX?b=xfR&yNh
z`h$n*WDx%W!YqNBaz1%zh}#|VDNv3vReuBm2@C*tgy#DYRWMAqEXODLb-xDt4?jBr
zE8<@$x#;p;kn|K_itvA2u~blda<%uyP^G^GnhL`!w^Hz3GoiC2wC5Fo|Imn^q?A<t
zIH3ebw0=K<g+S)=w;#q6z@G$aaa;MLNl*MzF#c}iJn_4?!T$S93!VWV;h=}$#F<pP
zJ=ds{Z1PcbTcoj9>;qkps<4#_;~T<I#SaW6GvbaRULF(;us}_)LII@^zXHnurLc$z
z;%f3Q<|8Q6HdF-e&cI)If3k^psm#CIrgE;-O|m=9X)$w%xgh2LpS?2yu&b!@e!o|J
zU%%eF)17puvp_Z=fe=6tlvNRubf=RLXXbOhVMIt+g4rMmdlK@x6Bc)6#?f)X1(y*S
zafR*xBBFld%qZYDE`!cE;)se19Z*C+{eJ&*>b`fo(+%0opwf_f_tvew&N+4JoKvUn
zYKLKJgZYRfhy2a9S`2GXw<(=oi&Q^fHMH-F%jd2C#xkhgJ-z+qs7^Mn+dJc;)UvOv
zKS9Zn>O0W9l=UZW2w<mXnQ&KjT(cBNJ_J}F&q{!<ekcjsghAcNTP3JukzlP5RRJMk
z&Yfm0wqFnzI(3LK#pISO33g1}sFoDtzbT<^DH=~mDO6y6DVe}30cDe<VFDjzxy@Rm
zQYBLanvEzdb>2ldQ^USjte}XLpjySldoB`5&l{WWf}TRBWfc>vn)9^Vf8txz+)|Er
zjOK9qT_p#Od8z?OMkEkEq!1b*tgKkeMXjh=y_R@8r#i7Imt=vCiq(MPi8n=;V3<`6
zM`^Fl&q=Z1@6ONJyX|U)!H9JY|Md%r$`>I(A8Z#sKEzDzs}dNqjXzF9g6Fgrm{C8V
z%HOIL8`hrdRO9!cymiwb6r-c+Q8OyqtS)x-x=YVr?z+{JbP!>~+?8uif!sub^YB>^
zoSC+`N;^6pq7yCyX9L=R<P4(*#9U%A^1f5UacB^5Aw25Bq`j9A(T1qTr%jQlttFqY
zOY?%r$V8DNv+FiO13IE#H8jkPcV(S$TG5WeQt8<y3*o(xHMi7-&=Rehvl=AYiZ%*B
zEA)(vUq9rWYQNYE>6eoz`dN@1YHtc+X4<W{Gs^jVyVq_T?=&C#OV473qkYv|fW3;9
z>9x%cukd4WB5}BICV&80k=OcnTILD7Uifo07J|MF5xR-TA=n7jh-%edl`X4iwp0O9
zO^NGb|09}d6j0)B$$!HVc-3$uRN3lW?3Ii)tmVdeGvg>bNz9J2jTR~srSJB!t4xi2
zke0jaX$qEdiFep3Zf=PW{rq7==u|r$ngt_<#<~zef&GiLuOiF!T61iy`ZZQcC9Zj_
zq0%DBVf;tn&Of|m$cVUEi#_&o;QS6*i-j4vb|4+QfObj-;KSl>G(YgL^VpDfFviiK
zO~Wmv(j0bZIDuW5O!I}36;@5^Nv80i>CtMH6xcJ^JB|<dWuaz;?$oR*HC_R<S|Z$c
zJq0olUYNZ>;gRvEC~*ha<QVsUe^f0@*`A<)4FwzvcsXG%+I;O2(Y@5bFH6dyjZkiD
zGEG0F<V5{+Col1z_-0A~Z8Qz0d_>jCrbWp(v^$KiHVXQ+H62Zqe#Z|av)R3#%D>s&
z$*J^(aZPaUP`H*h_0wni$twLgZ^$&n{K}w!C)>F%GC?K&7uf!8WNF2wb)g#`z=bf%
zNR7Nx%bc}=`=757whgJbu>i2tEl{bJG?uQG_8W4fTP1yHgKIDT7oS3-wBeeX&{RAL
zV{1LL(|DYz5`HaQm`tYnYvE+X#7~sGtf$>7IK;=0krg#dRZ95LBAxgS)8N;kvy;vV
zDVC<N;Zu<!xM+q!5Ojui8rY)!e#@EK*woI~bIn%OrK-TFGsV<7K8FUzSZy}cG_gl5
zOpo?bU3_T-Ff}>sYxT{rK?5Y0kkExXZ4#>sIOSD4r(ptM;&dR~HZnLnZrn;mCi+UI
zg{zQuVI0EVPTQS&>M0iR4*~SDRYv=Bt#FR0Q;2F2#lf!x2^&!HH9gKNE<Jdy)20fy
zWVVIWqlj9JH3FszNeBx`MwnI(*EK$Fb`Tml;fhMOCj8ux<v;TSm~a9nsJt{vK8H41
zfSQXb=<~bSZ?=-E@lHty8yzRZM4LafR3=7QnoI_>o8~8z(d%zvq!<D~sitt3m3r)!
zr1i7OvEpZ2mok}!fG@Xkl-Ym`O@zleTz0S#FP75UCL8h79JY>SFAIFV9sk5?CY9Pw
zPD#89(`e|Etyz*lVBaBdv6ab9a!ivVh{Gw0xOK)#<^m{T;dXB`K!Q3m049hCU&n$-
z1IjL%Wo$4;Yl@jJAf(nD)D^W*Hsf8zNJJ0zA(|)(Bu3~ak%rnq3_DpPN(eU)KTA-h
zJ`%~B>CjfVd5Z*fqtr(Ua_!e#2y5WhRfoz8;~0*xMnLEl3D5*Et$;zp<D_uuhK)lh
zc>x{PAx<e+*(B8cg2qYuC+{zb$#WUzx{|MVj`$i?>Tc39peLuKMMULsy})+KAef01
zn56<WOvNOrn9MkY6?9Yrilq@p0&*agW(pb2B2EE$jl`&@M??~+1*?@x<i}fq9SiR%
zir{Fm=}z8EfFK;gH6rOKOfn|OQh>55LqLwDg4k?{Trz=RC>>=-cO20#W-yRRi{W5n
zV>>rVN_;#6+*R5L+Nj3%bQ-A|*-X)BrBqJ!hIQoRSgm%7-hj}gr-5z+Bm9N$Rl&ct
zong`omxkbQ2gMxi05T-_5KT_N*v9Z40J0|hH%-9YL;dPeC(>3bC1oYs$t8mu&1g;G
zENjP&Kras(W{qRS9hF|g;oI={*B}UQrdCmGNkictnW#dcO9V#q2RB(K6QOhwX<U{R
zC3uB9lhA)z(!7*!ct$t!&%lQZXu|?BSaFaeXlYWbR`*ddNiQBsT9=XT3S^lRJsZ(3
z@|h@PXNka&;2g~rHLzENhKhpJhriUs-e41{9$J^A##h%|{<S7bdL-mxEu`<DO1J~b
zGkw88M811?`nkl$$WSF1)BZb;02DCNlkKlH=trrH@EYW^N=e0wD-a}gUe16>4`3B6
z;z3dy+T35^^@8;bC^(|#(Od%^Dm*NVgZY?<V6|JJ?f*aH9OX`b+v;!5#zoefGNb`8
zI;h2<5h75;EDi*1c5xw3#={|ubb+c<A7^E4r4r?>(aK_`Jw19dMubL@nMqSii+3k=
zo8?I!SDUCh2)htNY638)VG6rQQ;ntKBAx)8LO9aI36x<p6)CHR(9p$^cZOaOF56I@
zlw@DahH^FVD8d}JJj^)l*Ww#laA4)<RXG7NizXxbG}s_=gAiU6N1RzwT+egl6H>fI
zTC&3=p`zr+hF_!A%PvN!Kaee}$FsbFW;lU6el|_r$Yz9QVi+R}q6)*WHc=EXd_Rx`
zE<^qw1d<vD!h6wlP~UfqZE%q$0{$;<W>kp&AvP{_2E1gr`jPq4RmFsF&=pCB8cGA0
z92)OnqE|GTuN-o04ez9tGif1J8mJn8mZ6k|q)W}$N@c$iQ>!K>^bIs>E<{9hjol$H
z_P`1fV<gQsv$0$WoXCNU8dr(OYcLYSdjM~vvPCldv)L)0EMk@vf!Me_u>SgDM=jyL
zDq7M2qQ7?wh^bCDgjIsp@L!CSjXk0<Gp&?$m}<v?u6zRs7$i^M%A0d2<M@?A9(4~}
z=3=22YcOa%Bmz}}0Wda7DzX}az(UWmXc^I~*jSescPh{`+SWq&5Ra;`2y-ZYkM@M`
zLj|gtR}};6R_9O;B&IB0-6q9*rR2s6wCfCNJ0<DDjVr*|C4*CV{}GHCj^60HHC1ec
znyk7-Vfu|gimj;A=B1Ob;zFBY6pb>_HKW?8w9(e@@Z~BNWo9ogCd8xSv=TE^j!_C+
z(ON>GjV8yb0!)$+ryZva#raA5Hs*PQRh*oev|&xhj@|HyiI$Q_h$mZbWcW}W&{ll8
zTLoeu!Q~k6z8Hj87Y1p6Ls$u23LWxHyppT{eJ2ZoGwR4SCY_no7^7a(TVBVUwa=fa
zrfTn*9{_58Q8fU;Ny5JgpfxA*$ZkqzMg=U~L=9$&CF`49xD6C}p%suESuV#gh3sJ4
z8k=yz4jOt&Yemh-1}c&9Uh7#9mj(b}h&eqrJjh@LTp#1#R|;MO&F%qH9sC3-^Yf|$
z3H+YPF~;xxtO_R{E?Bh@@9TTzHy~9VWYh&&Ey6RZ4nBD?5{{qQ$xyiEb|Y2d#-J%E
z*b3Z}gYXLYyaAknh7`128^_+j7Oy&|QAYruY?UPe;s;ck&}mfDd3hM13VvaW%ZkIw
zF7BcTKMUweRDY6XXoee?LV+WM6Ba^Zdu&V9%C9I%0TI8L%WAR-?@g$LT@%$pe6W*`
zvWz0EZZjJ>jw2Q!5y~PG6@P`ekP0VXLL7Q)C8+hnFYJ<xp%0uB!5bt7r?mKdC-8id
zrb8l(ImjQtUJXtVJ2b~>8Y4m(@V%)9#jTriHyX`h8NJ*YSk=sK@2W;d9Hob`gkW-|
z_w_76+EAJi9$HYRBb*L-n8|_&eUe4UH*p1tcf^=B_byD@7O2zWgUf`O_PLJ22@8Cu
zEwb7hAa>EpXU3M25nQh-jZ9$XHTD=9!J#kb47AxQ*0L}e?>DEJ)a>C^z*HY6K0+J&
zIwWfxSwZ~9Fq)|q%RAE|PCj=7y5y(}y4*VGx*!I^)&r7YF^S+%3uvwv=5>BXe|yqu
zs=39gp$e0LiuD$0&9U!qrGE<qXV60I{TrH%;9ZO$JYQ9}A9OR%drBF@`Oxm^N-tQs
zW(CK$_KDzSsa%HmRc>k+gY=E2(pVvAdeET>voscXxmA!l&tQ6$K0hEya2uQ&2gxdM
zmI28tl<HR|FD3<og)p-_oGl8`4{A?H#-sh{lW4ZLEpYNF7e2*V7gZIO@jF4%!$Jp)
z_*IBZn{H%H{~>%`b9fsIIJO4Oh}0yO(XZab1GLBl&IJ3|K3$Q6OB}bDBV`_Iq76}V
zm(RM~Owxqm?@L63zom|b0ktPI>hUFMiy#E8x)WfRdJ?X8Y7LLc8nHRNo;HqKyf-!f
zyVd+<)jWZE@4&Fdhr%n~rGuDfjN`&G?<0=2B){3sPJV}~+;FEqa5$W9ugIJYe{>DA
z*H4nbLZ~C}Gq+2G&GBHw5f*ADU9>3SavR%`R>_%tozkxtjsQm{8>I^PEL}^{e`iIr
z%7%C5a#(j-16XCppGCJ>N77#wTVHg!nulsc&?NJa;sE}%MthVzi;M|A>{ol$3cDz^
z4sWoR+QtM{Z1~Qm0y}s{jsn}mYiLMUc+y}`FsIFY<03Q)5{|SYCgFl08+Lpq#~zLG
zi(P4<4Fbz1=v){3!4n+DF$-;c=F^RDinVBm#mBI73zWa)X9~hUFv})38}OZhOpO)?
znOjW?KT^Y73azD!{u}8wJY2Mnf&7^bB&EN~3eVu<(=4S|WRky1$)C35X&Zdy2`|7(
zN(y=_b)AyknJy)5mFlk5hwuAR_Gh_pWJLR&EH9NrH!0CiJh!brTnXr_%?{4b=BvKF
zA1rhJXe|MB2j~IduUF$7eeLq-x<0FACsxOyF`+6Shvqpw4$Wh_u<%%3PBJOjK)Dgl
zhXe&X;hV5H1II-{07Y;L`Ic<ShV&@QF(`Og20oj5L=;8lD$x03yOWc<b@8K+UhEOO
zLd5UVHp!%A7QaOk<6Y71%9LC<93wPPZv}^c`C5a_9Qcz&hP!Op;KDd<E$Mi3?Lugi
z1R!~|+Y3m{K_fnb=ERYDHT!CN8cb&MOXgaVh)1ty<&wd4eIJVLg{V@A>8pVL=P#kt
zUuvh**lWi>mv-m0I>GXdhqq@Wu<j2S&RNgeFsg%d#->grvqOt%6p`y)Y$v;Te>6oN
znM|GMOe1BscP|nfPfuaUb*4@&m1qS)N>Vf59_t{^#qI_6xk$2_LT@)2x~P-`m89pm
z7Sj<Xz>TtMMjaZY(`86@R3K+ECG?kyHd$0A2!AD8t1w5l=t=ksiZ<N{rHflN%S6fZ
zyn!Z;Gv<~ym<UAd_ENQIiW<=)sShneFj;9)WQN5UquwCwvV#*{_6RK{=HM8rUDFjm
zU9mGPcBUR<0J%q06??7`t3fJWlo6-Bbc#a4pVXYGW>|wXEc9!!v@?ukI*`5;nF5IK
z>M61mSt7F;;wh&grdoc?CZ4I(8ztB)n-jgVIOu1AeWDcmWd`HBXYrB&a7AO@rry}O
z&qm~XmzWSllfKCMS|^YK6E+TTt<sbd{$ChU%Q;!QyUCVlvWh^tOW2~F9=Zj>Ha&7>
zmW}_F>_;3T48|X_-9p!MV7KsGb?0$_$am@x!nO;0M7~L!%11`qE{ve+sSgTP?6k_^
z4kjS?qwO9(y8$}*LXgO5pp(FWI75PpT-YE9UxO}}HReoW_iYfN&_M)JMG?C&LECyR
zQf0a549kG#(4<@kBT)fBb9Ue;5+UcDkc8+1TX_2(U+=W7b67+ivUYvK39S;sUny*{
zCIp%_6_ZV!b9UXtR0N^u>X5WwQGy!aTLQC4k*{i<^o{13LZI}~%L%VkoSFE?!1|_c
zS2{&GsEJH!&=|hKsin>^v>6PxE;fd1p%&Jaa3^AIafOn>Ses?p04u0bQ<EjniRxMt
z`-r$A?3e~In<3uy;DF#5gPU5tB&cBy)*2`wD_5&2zlem1g7n!tUdvR-*rS#-T1RTJ
z{vYC-mP^K83P^3;#?4RKQ0OXGTy0!4A0s4*Z(qcPDAH&4xO6GXU?_)C#oTQwD_b1#
zsZc~@Vb$UGEi%uKHn5`Nc?(RKG|Vzq0^QTZKKu)3&Nd9$B7a^gN3#{sNTQo-P#<fX
zMvC16wV#!(TN0miw!<q1>^NU#z|*nTh%2jXJ`k_DEUzu;tZ3s*@3PQ^M;gjSPpJ1&
z7c_6>)p-;-SYX9INXv*o!VNMS!Y5JZSYH5w0c~%?O+Z2OLO|m`c&!e%*gBjY7^C6C
zBdEqs>GQi2C~&PJ<xHdXzK+{Cy~4-oSjD>ji8R0@YlajUhY(+l-bO!aw*6`v5aW3y
z8gLorVfw333x+-wgx3OwVu7n|H1i9G&%8mri7C5nlwAmh0ksSsmH*4=iBteLCGvJf
zscjbkDw$X{A1*3cr}EaHyOI3?vQp+c?^ED-X?KM2ao7!93n^LDCJqdFo;3A6@FNX6
zGh$oPGoX6;s>k=kw&Zys*uDwDE<bnGtA8&tu<}*~-X*iB`BtU>N>;0AzAJ$~Z0vez
zgc~vD0qNUxAW#by=U)I$G3#Kl2&Z<p$wKKeC4j&`kLji)e67=akH3<Db5Z0XF25iV
z+5xxrhHyY{?Djn}w-l<?7S@^~+N}#Jn~TG)qM4`oqB^{pkHlu$!Mwd~=GHxG=7!Ol
z`Dcbm-+vyF{-@Pv^1HqN@aP$l=V3vmImT?`*n6&EC#S`3Nw3idI|e})a0Al%G3^qv
zAz7|TM5G_m*ryhRPrPnZpv@bqS<iEZeKu|@=2t|TO_|Wr*iWyXq3!yauOK6he#O<a
z^byzXsi6r=19t6%NEjsfDqzJG#1(Q<Xdhe7Do;82!X^uMr{(Ik9mZiP9NGNWL$&f%
zKi^lpGQziycN6@HZ@hd6m#<xOnWI<MIUv)sr&}>UjKU@=J$J&RSAh(!EJ}M6!0pst
z3X_nZA}asuTpLaSSf#$R8ThVFrM5p8d~4G+fpi}y-GxdQKCzjf5gC85IahJ4{Tt=`
ztl<UeKJttie;PBMN8|EU?|KeM0(M8eHgCV2ulf@Q{nh8b`uy`YMqlx}c+vzC%D@j7
z01!X3SIu*zmGs+A0j1#%GfhB|z4n9W%0;5<H=Mh{v7@{$rC8%9v{GR;xtzZ%UIT!C
z%QY``Ig><RigZE7&pOJCwUz95&F)i_8Uh@5)9lpX_Ow&3!x<Q=pi9`3u||;IcRJd@
znZ^f$rn6)hjfV<JS}{9F&2no=BEyARjHCIj9Lc^}t(xuZ911qcVC_J)+>Q8y%$yh5
zW_&75a+Xt8ax$m}`=^-Ys%$Z^o)E`qVsh;-@qtD%Y~2t6Vq9WY6n(NG5z{&q8Nhf{
zT5zpw;>{x43w3^0RjR#ibGtGgP#0(E{>rBIBv|xg;-J$6Z3VntYs)WtiyGuR+VQg0
zmMxkdr(kK}J7k%sPQo*`zPWzTd|pVR->5Mk^wY8Kca&YIk*8z0h3$EL(Wn;=#Vb}0
zlneIXzrN_<O`yZOIQNiIoyY<UKwpI*BeY9EvI?u}(5@qt>9fGSSHdZS`^5zi6StZZ
zKsSl2T!f{gLp6A_!;_$FkquS>S)oH8h{-h+-G#QT?9iqmPH0PJ_n{5qO*$XRj2uw!
zLC7GUE+<i?{YDo)Ua{dXgydkuM!uV|Ip+_w&+9}SBY}y`wxpcy++jlgPUL46D|T7m
zgnN!jgJ$BD(vSu$k%UfdScIZp5f-P(wFPay-lS9*BV#aXthAhJ*gg{#0OLUM>^LD?
zlUxd>%_zz-5jKsH=!4K(k}&OaOa19%9nN>i?8=p>2{J7K?pz+x2V=T3L2?SQvwWmx
zby;VnsFR9k7UEm~m|!zj7C+)4p9Hv>7>CuAc~_!)uI-jMM<?FK&rce4ltd>&no*D;
zJEWNin`*FNWn4t(xDFV55=uhiSx-KB0+!9#WczjPB8oO<hc+-$>lg_=$pPvK9;E{~
zdg6#I!e2c04$ItF=r6Q)FNAP*TuVE8+VFmy%%bIOIO*?OkQ^@OHJA>}#UO&__oV{U
zAGx0#TAXSre}=^J5v*#%9ejd9uf}7Hq=7o9f$|Xngq=2Gy5^Rrt2NBRBE35~MPji8
zTRedS(@3I6FhGy+?*~HcyzWA`2Sn*(i(6y3AJ;OW!{qTYct+Zeo^iI$dSGAC7&fY`
z#is5=P~929*@u97WwFDQY3<vlZwM|tgNrdSl5WyLJv)HG3<#2H3Qw9E7LuQEp3CLO
zE@K9+bv&$9$Jr8AD`6Q&G7xy!S-&_InnHo61g<vY6s(lB9GYY;!VIObqpi)swsK<R
z21Xxq#+eL?Vagz5rpD}uzh)7qw%-%`$SvI@NDmgMLQv4m^S+YLarL$+3C^=PVJaQ$
z3=Bbt1nofWLU;(_tV`Dom=2dLv{><W*k$OmyBf-<r?fn&qEg^WJ!fb?TvX}kLy(RB
zM#lHR4tU-H&I|EtB<yd*61r6A>s|<DW0JtRxy-ew86c~U8pQ3`f>+r^9O(uoYuel%
zio(_c$wn;TWAF$O{&SOjNdaQttm<YEXvTeP*_~S0w4~?oILc*?EF8OP!u^a&O?We-
zSS$NW9cF4X;#Aw-0cJMJe?~)U<0+)=H2y~TTGM3|5FX-CI!hNipaG83I<MHlof<Om
zmeQgbeeC<TAc~t19^51=Akn$W9QrezK}N?pc?ch-o4Us*N0A4OcZ>Xy_Zo?a@Rc<7
zGo56wm$@3hkx<l!GmPBv$}qf3N*V|FCz5FZI|?FTUf2s4)FW`a&IudXYLe+%OcO$w
zWIoYs^rXPycwe8{ueSJjHN{GJg)n`NO2AU7n_%MTRU_9i6vB*BVQ9#j*ow)#nwTnT
zAtYyTz#$1IcDseu2TfY=g?*J4xD)w(Ge-GS-!h%Qdih0rV`Niy;9r&je03Y_(S1>P
zRacnEX2eXbds8d*ly3)fQnq2-&*8;&DCAnqZ=hJhIA{crOsM@vZGc^gsY_-%;}?J=
zxB_np{~Id?oR)HjCuwje<*o$ShcutXR~hK3D(C$<#|J{IFkxl~7}|~Z7?y-4j-DW4
z6UH{mq41KV@eJy{&_T7;1jeIY__=3SRs3<^F|+4mA%`so{!Y@W)d2juE2C&Ey*LhX
z6vY9|_83-WSveXoUp7r(51)$0cr1&?crK$zd7FR7c2ML6EY`XSq5z7>E196ZnRBlb
z4B+k5Ra8EflC~XE5C2l99(#H?un&xO6|e{M2l0<RAPEbGLofcXQ6s~O9Ck+1h^Gz~
zfW!QI2dv+Mq$>q;&TKa6Y%sUwbYl>}%XA^0Rw$|vyNiwn6jX?nDG8OTF?2XmoNh>Q
z>b}d?o<|A}G9hAJ&J{Kqi~l*KSiSZ#U46O765`DDxqFQj*MSwsivs}@IFqgQLbTtU
z{2<eUlYq-&1LX%qMZjeQpc8;Pl!N?BHVc3^YXH2b_M7eU^w21H77l193abs12B%ND
z=_*lDDXW3=Ld}KZ%UnM{m1LAJ^O9$LY?ZHh$F(EQNLrVWYf*9px!AvA0E9k&s&<C5
zFK?Ew${Z(YXcd=R$WQRbZqw?Y`25;3)@{{U;n5$`+QKUFKZHe(Tn`o<1`g?LfOcJO
zw`?wM+`?6Cl%%fkU$rtAXwVA4i!ORWs3crMHpNXE#(}xlo)#qpubR3i*siCMqbOq1
zgoLtSCWGUn*%`CRmi>Viqg{Wqi<DffvLWOI48mW~)6jBKd3Dmc*xG=NjYJZ%OjDD&
znVn<10p}I9jy_*BuYF(J_f<$2!v1mYBKC_`X}9!OGArFPMAfJtSg(EVBX5^QZWm1v
zWcgXOLs@pvc)fV5@cwn%_q7{9>hH!qRR<UKxCvv9J-@u~v0lQVnYBMcGNIxkolHnz
z=J*6|YUN{nlvqgTo0LN9-f@z$VBsgBq?XHi^OnNe>E_}6QFdEA&Atl3B~#EZf~U$E
zsVi=zb=M<g?BMua>KA2^N$6Tk_|s#p$t|jAfZw4k92!z_thqUvebPEkUmz$&kj`P-
zM0-DPv0M};GK_SwHc}d`+}!q~9~EK0sXaP2<a$3VdamHqhRMZQ(G?w2AySW-+`>Pe
zrNx$9(a3Q111k{|8S^1|o!%>XO%q20%nTwn?<|H#Y)iVgtwCxjxgA0ilk@qJ-dry(
z-m&(?9|nWnjj{=E(5b(OTsVutv}yK|`bQ3?42<WHEu&Qb*lQTl`)x?&`A6K7St|l0
zTy3;OLrE)IjnvPf8?qeL`C*yo9;#n&KmMu(1!BTn46I+R2^pU^{nq9<IOrfWC~ZD+
zB#d^Grg{Lj^s#s{gMxH44v|}~=!1*GbRh0vUgbVkyjUJG?>}an!m#9eqeF0<HjpT>
zgY0!F17%0SKKokw|0qzXLx5_qBZ8elmP8a+?Bz(>Z%P$Jq}jB)6P-@2#Qpf15HbjL
zSd&`Z?{yb)h~5gM&wL%ty3x*<0Y0RZ_EY#3@l-6VExvfo^vB51njlvyNFRJWM^)Ot
zzdKbaSwj%}WuAg;;M8YfqB@#*FE1}4=!*iEbIeAV&psT`h)Varrta^s?)%Zq8r?=L
zzoIIzp2~1Y;*Va3l++c{QhYtxzv!a}M4P`-Xu~*p55^{3-bUq93EeC(e-(I#>Nv48
zNRmvd-P*{e?T^Oo+D2>4fq2*zLdjFr1~a<n+ibnNsiUDoLt*>^%JCDUHQIQSn&yxc
zLW+UB$RY(!km0UQ;W!DF3P79`*v*{dki~4}V?Aj1O`S}dX;cR$sCI#oe$Gq}<CurQ
zMeZDELAn((x)(FJ69gP0DI0~&^1@_{523O$dp#fG0{>=_=q2<P5BAU~%RvG5)l22g
zn%u88^CCxRv8w>7Mwk($b2gvMzV{D3hf2nMgnlYbiq%>}%jbzKO?2cs-wFEgj>R%;
zjAA2W<{tZmYJYe&Rz5cSiiNfGpV+B#C#|K6Vz(v)AlRlY9Ixv|q`cq=hMZ|u!xPJy
z3kKxL;rew7hHIu2FKtD|g;xb;pLhc>`#$b$(U}qfJz9j~l?m==ZK>Xt;&JpnY6cLt
zA~zw^lq3>J!u=B=n^Wqu(`hw;3vD1$<iXeH@U=}t#IcHe6b#9Qf92Ya%BnG&jc526
zmWi{&S2v+bknYhJV!vID^+~c;Oc_~O2jH|R2f3(}ChhLd&op=F-6Rdt-HKYM=qcqa
zBh!sK?v1$Ck!q*u05X`2ccbJWb5Npc(a2Q>X!4sFpnr-3WGKyjZFR=ypFs(_7Jy-s
z+LTC*0xCat2pCTKQ=N2PJyJiXh^w7^Kuf2^1`U{24V;gf!c7BMrU2r1qye$y=#K3d
zzDK`4vt-j*Otec*mTGAVXBZ*Y>EX`Gy6zgcltnO*a!2H4o`fDyG(3l~9{3Q@Ta08T
z^`^$zZ)9VHYa$%XH1-5G{c}<i9$jc~-LOekV`dxwP?=xL^MoKmC%j!-1WR=l-tSZq
z7tqG~tWo9G7&UTQnCq!b)+^r3WNpWa4`?=y!p0NMg5R^!g-l~3?<`UEh!Rc1tVt5>
zr3$ehEZrvEM|sMu!VA$wt^8t6bJxM7o{{BdRP8NBK9X>ODYYh<NJt)h|Cb=I(i-Ha
zcqoyQV6{#IB4c574Xe%2$aGUaeY@Kj4g4fZyGw+v7N-ng;D(ZW9ObT3fs@0$?hv7T
zPGfPj=*(X2ht*~0&4)kP(pe+1l(VqncWpK}4jX5~7|$4sqFJ#jQB;Q!jB7-EOJUB4
z9Q7$po6EBp%yFK@2zq2;mpBhR-<CFtvmCvC1PDc?XNaZh1*o^|$gk`*vfS|Z@heA=
zIj_rAPJ%#@uo@g&%uib8OA0NFpGvc&Z#3g&mivja;ObGiEMpo%;V%m5QYlPAT}Vu=
zJRRVAnH|31$=MzwuQvUITi|0MgNm13nW&R~g)FLY7~8SxCcx*Z2(|4d$wrQsddP&*
z0e)mqQ_rvx*=wi}aX2yw6HG=Qa-z6QF*7|K;|xD{SJ$3!7nF^fXwed(T7~ENk}Cf|
zVkqO6R%6=IfVB#s2~n#NQ4<tt*wQ10>Y_{x6tiAw;417SHc#LSM52Vrf^U<S0Q%0-
zXp7Y8hA$KuXR1t27{o&;kPRMA$CJ+a$)sNIC8j1s_;mLtfrW`=nn)3UuoB^=2BT9b
zYoZxx0`xs#fn;RGgh5M&Oh7t;JH^W7TB#a2Z7sBF3XE7aXZnxoWC63VyJFb;&ws;+
z{UVN7+k}a@6Orp7ENG@_(sklI$L-lHVUnMslkd3EV_7XsVW`n_3>73fdTuXwOKc`k
zr9L_IU>f6eJ&#R?Qcoh2j@q+_<`|8)RpSYyd=aY^4XHXK;|(eI;W8!NMF34}ykM=)
zITScUv=YJFJGbcAAU!~NLw+;jLhvkp-UoZJiN<DX9*loY!5Txwq+u(Vg$pDrnQdTr
zvD8GWUYq&pG<~L>2EZ7h?pk79v<)w7dwjcLqXLcXZ)I#>>lf;X8)-`F?oMDZ>x!qD
z16M!TCybLP0Vovk0t`5PP6VkMb5*Zy$OZxeF4`{yWM_v)zozgh3?6tLmtoy^sNR2$
z7y0NA0}CtcCiU2eU1zJT%?gL~YO#07Ej2?G?0kgMx#HCo3)G|jj<O!6tbALC@YWn1
za251|WC~|Sdy^@+4(QcITRn&mQsNwCoOD5_M;Det9m0qd%PfkUg(~Cp4%P8Xs{{Pf
z5>^ezPmvIG;UyLiwQ>aL#XFGs%`BQid9eadHzm1cy!n;hWq)09*;m~uRnvI#uJy6C
z2N}RJTX9RK33&ck(*L+uzjYfA*s-LRw*hxgx@=Fx_1TUk6*oeR;O>T>OVVPLFNkuv
z?_g&%h9B$cvy2KLF_zwzFr8yI2YLy#Rx!z43jAzRVGGaDZ^c*Z%o2v8%3D3(;!Wso
z;+Kcj4IMy-Gou&HxO&n?pAgbQG}|EBw1ixvpII8CTZIX1KSYW1unPL=R$xnB8ulp0
z`afp3NMRQ%(s=90QbnjZdS<<W)8eh*OVZ&*8FR1OceA8FUWJ0h{M<{k3i<fnSPhNg
zn#T`8?07qn^exUOgo%D{hh5*%?wr&sbGp2vAUlP?f>Oi>V_@=-M&Pl;SuzLxTwz;T
zJ{(1nkqmc;tsdXaO*S}wIh=CDO=*vdh|P?BamoWQzzEpM0+V3-i2}*V8)UOF4eHHm
zPCE$2Gio_uWz&*_11?{<BWJqZ64WXy!UTEDhjSnutAw}*o({{@rd>9kQ3~88IAJrb
zVll3jprwUp?26rtS+JThXf|vJ=J*C-F5eLCTIkOMc&z5N)*{)%XP<2^Si3+`l&>H0
zW@%Dkhza4t43^x?9+-~T4fGMw#VAKBQ*43%2{Yk3Y}_?6J{T2S;!nu?fky0YTR5y7
z$Bfq(8YAwfHY8&riYgBi9|oUs7>l>Kf@N;ftp-&(j@61ac36)r#v1PZ#bAEW1=%+J
z_{-Z2gR63=OgVGmUh1-#aL?xa5!Qr{$<SWz5Lni+NoC{GBTH3!%(QKXxAR>GX3*{C
z-t9QEk-^BoK?r`G(<JCW`;6nmEo!}7sSb*f7ccDsi12N@;(L@i^XV(WUa)^hJNoDF
z>xGU@R6h+SLk;TIgp5z>x1@0Z$=JYQqc<EXb{j&preGW^GFcnWrFwgqmIWz?6UE#3
z9IUn>X#qE2x!b~B97wP&VtKc=ot@t*nPup(O|1?zIGo$S<ipo&T)0PoBGCmf0H^1Y
zmojc}zm0`OjD_LG4BmtrlEY#&{CnxXI%SweNL#gO<pe<MLRF~!KU;u>=BGi?YKW#5
z7(Pbh1KX%j!-EK-5<yWmv$f#@hDkYqsxGC4xwKGga(u=MIWKvV>PMyItwC}5!;VBz
zEuKo)>uDIau)&V$`r0@wqc8v5ZeX*S4>p^OwDAuu@$0#k#mNFanw#msXg%UuSO*T$
zZm@oj-Fr*h7}k!}KJ@~om>&jaN@ifxhIkLKkCa-%?Ii+Al3KlS+{Q{OITuY_`|M2|
zS=X*5+75O*OwfKf^Nc0o^G-ST$tlOBI1_NIo2a&DV#-#WJZF!6rbjP5I(0Oa@+BTy
zKJ#2YzDc}UcKY#6XICD*8FobmH*hR|g(pkB7~mjw*(h(W#FkzAMmy-J>tQ%|BiG9c
zCBxFL8rp`Z<jCym@C>;lj>9HQtVm?feh(EQ5ikoM>g1w<R(Bq71ntXLePv%6R~wr@
zPD7Xj<n?U*d6&L=Z}{RepdklHA+&5*ze@8ySM!d1LUNp1b8g##^bte##U|R25Qfz>
zx2<I7+j3iy;{=3ap~^mP$s1LyOHJHR0BZL2zSHL^*FI4$qy2k9y3*6=POnlbHo6<_
zvZXozl_6rgfZ68-W^O<z|3K`ry4ZO@XXO917F{7xV$oBHp!PDky9Hs_8dog0sAUK<
z(Lm>WDe+4t;n0@~B|BIj9`FzHrti*^)2j=R8+4G~t~2-*mHN@hnzOJxyi!tkoG%x;
zjFYI5T%0wX%bZ|BDq`iERX(@&h*ZYD_(chbKO@4pSarK`<(x0$Xs770JbQyADl-*F
z-kT9^{zm1RtOHEcRt61UN`o8C8gUhv^*@bM&($MM&uL@Cm1|{-=(ut~trGXpXfoT*
zs;bK_SjVw}4bkOAna_bN>?fnfb1%IRo+m?Qux~s^RBKK2aFJ4?tnoi-(jzfEme;o7
z^v6ii`4mo)lq}VZaN;@Y1<2)NHDq*7tonVR<!{j<<#l3M`)o597#HfbtGDOGbZ<-1
zSD1_+%D}oPKNIq`3599o(eGb0eFo|pN~vcPj-XIWs0bnV40T~y1Ii=umsY@C(@T}D
zI`s?jC~iR9F;!+09D6+unbblI5aq26>WPUM1!c6|PpRcwm6>L_5^xGx?BYUgIn_!i
z;iQZaMa%oia%~YQh6G~y!cKO=ZEbX1;Y5XPZR6=>TSr$rR~T^yT#SJ2LSaYSa_#<p
zhsA2!nA4s!$AufJUlKERV0mm8qwb@90M)IeGU}hCANm#T&ogY};YNz#t4LP3-^9|$
zAhix*h@@p=N@j_j#rMZVsgM{GRu&#-E!60wmwyn?fDa5I`|@3_SQ!~faIJ$(HPjLb
zaS~ix>PK=sZGLg1;PHId4GkvFW4+K2NGNzG%D)A62cG5!sSIqmIvBVREdLaubZ)FY
z-TEnclAWmT#}JXi+~$sXI4;VptcmzE3BS6UY!hs<I5<)rwn|<IF#J1B&xLnkEzj42
zbb%Df5%z~UET7k-I#7^ck*4U77e5|v8dEJtxgEtvG?0T=4SDxvBO)OIDt<T8ayfTu
z-i0bkAKk1)Y0Z)YK-SRFD#Rzh-dv*3C^L5;*4IX)TEir98v|~}gn9rdF&98kwYU%l
zxRO{a8_|LL{UpATl2=lNL(PPAT=+{h@(_|qZ!P^h%`&{e3PcfHCyOG{s(rZ%Ghd`Q
zeXSLO^+g>StSJ}z(I!%ysre6o$sKfF@g_AD@oU|ndD*-h>Af!WZ5`xtEcLCytkfFZ
zRKWyHibQqk{jR-M#XWS5_c-AgJ<2!Z6YR)=_f1D1yf%bt*imV?(1I@Rn~%LH*C8O&
zs9Qv&#COsJ#>70;V%NpcmU7*l-~-2ibhk%~V3J?&KSJJR3>eG_o?KmX7~6)&@P9(D
ztn)?3du!+VPZtA6tPbzd_?r-@qFCmWxtU9_8Ll0qNqo9ChcgBZN3n3X@X)RmchQgS
z93`wsN`g&u#IS2A`oQf(1`aSoTs&P}*xnhTBiv8x1Sojy;4&#)`zpDpyW1!fcG^%%
z9si*%G9{p>mrJ%y9-mL?XaN@a#Sr~sQZynncqGjX%*~YL<0E=Epw`mt2I>(=Yf2g6
zpED^cPbc6tIlGRjppqk1)P9!AeT*qj<Sqjui;@_)KGTkd!L+Isx;C(m{dtXuGr0Y`
zz=2_eM>ol!tq^{SYgZ}rX{c~Q6D|U!&T%6kQAR_Xd6mg>Ghg+CgJAuT7%}fa2@*CC
zX_C7WgoG)9NEk&Zfm}L0g<(iaMHpn%aCJE-jT1E&1teawWwaXlhSzIxnryX5I>EF>
z;d7kg<5fb`W=miJ2$u{0n5h?5I(!-GB-x(?6zUF@x|qyY0#xW@_j{Vkr(2paxty}s
z9fZ}Yk9AYBIV^G1scMWF^iz;|6GoKbqnP%^1&$(cz3_i%3Eu826F{#5pt*QxKwuqZ
zf9jY&M&T?}lc?J85p_&Yvg$`RFL1&q!B^_+vk8=I)hrLPkwDDt8)Yt6t<(d+JWDGn
z>ukE~G>Ub~>4A-+RhC%;EMIu*CczJf6J#o6PL6RdvD1;{R|Z?7e|x{>n*bRk-(rox
zfN*Jtp`plsgS=(guS=O5K*PHDu63ay{E#KvVrYcRZ5yzovLxXL!lE>{^j2tvKmiWN
zH_9wcz?p+E+fq_lXUsC}PJQ#-Y;<gOS?C#HnDni3PQr_61MS5kfN*xYLZk#E54yy1
zpy^?ueBV_j-M7)DX^r6{Fm70tH7*<oAKp|N;$9=h&E8qh;VO)0qM$*eMX1hX&eK@f
z${2+g0VKK?2xJx8<Tf_d8Xr;on(!9roHtGSrr1X##k5kZaHV?|%UNedmOJ}QZ&sSB
zR1VX?%LxpG<etl*&}{`yTvUgDt%H60%$5@SQ*K=+<+B0u6Qcw2_T2*HrvYS0RUmZ%
z?hrsW$aP3o?O8|`9kSXYB*%<NcrvM;&!UYs2ZXFPfoAu>Zeii$BN{K92Mcf5t;YY7
z#)~GAx=@0Q7B{HDqqp6@43r8GQXgy3EQIT!Aq@B96(%f%uW1548dGUTwkZO8=UjL?
zLk!{BtHZSr;gbr*Q%Y>{nJ^ZYYquD6e!8kO#_ZK-RHNE7rA5CTF$$3u{ifE*j^)t2
zj7p38FDpr3S{+DU$RDdYtPFz@BYU@b^)E<51a;dk<8D8oP6Q|Xn#|!Lh>lO<G?8f`
z$d2$SFe1kgRo0(4=JZ^nnW4(ntdNlJ@DuniDtOD~B~ff{Vf`&TpLpJj<-tcwDSj7+
znbkaOEf2E|M})DoXIwxwD{O^jstK=!St0%Zs{(n9*<~GvKM?iuzUO-MSmtu|0(<VC
zO;v;x6o&LsGGUvkdt9aiM}_bYP?zdE3*kSRY{-Eaw1%*azG$(7#el(6{qJW$X!~z3
zA5!n2DNoZoA2u=N?UD*<XTi6h7!&yeNUR2wil(t_)PxUERC72wrKRCwzr}%8nlZ0U
zU`~g?jhe*cXk4x1@8Q)kIXCabZz^2<8&m)Q(!4J)ySnu4IzSwH7qrM@k`I`w@A75@
z!*nUl;qBgQ>?&n6=xjZC|8kyd)(@4(D4ko<f!?Ba!@Af3+N$f+ODJl22;tp%!zqU(
zO=H9spJOJfCiHFQCfdWs@eMyj1I0%$2*6zbt}A8B8$QnhYU3)0c6EhMb71E@1amE^
z1K5*3!{+sgXdB2Jzz=ffuAwF41NqOC<kJj6UK?3s0J#MXB`YEKVVg8^5*8GC#5@$9
z+orat(UUt3JX<WaJ*s#U?N!B6=r?^AOPObZ)(K?{kM$|@=sVm+6SPV4kG>C<-!R6V
zRmk(-Ws<@Hux*@XN$2@&&4f4Z@eTeG6SDumeO1ax*s^xtlrp=0fOns+^?Htq9g#(q
zeZnGVlFwI($5OeKi?&vre*y6s<x585h1hD()PuwBp>YXS`yBxF98pa!jlm)gI_TEp
zjY+sp@FRMj1NT60Z9K4s$5=LHXvAs2;bFyIXlH4Zh(+=!05=|1fjWtZEwyO2<=k7Y
z)0=|)v<zc*O73!zm4CYqOsL!tmaF9AWs9_$<g_?JaumXq>4zi6l%gkW*keS>RJkuU
zXtRB%J<bc!ei%X9Py4n4w(mSiner*u2dS84+q9&pYq~GYoT57WPKN3~Tz1b;(AJ8K
z{cxrwU-i{}MXBfYoGaJO+b6x%<(ID9aQ=Q*bgt9XBe9LQd2;{WVjvyA4|d>0kSyBE
z0<)WHPFIUR7r^CDoB}UjwRU|9E_+0S%en&)e;0-2*90y`RJ9g2C$-xIDNTzLY5Dw|
zaRy%Ih<0u9^HgG!Mp27zH1e`}U&)Irk@juLevU4t=FEBj+y9PsLE8}n%<j{jq6Tg4
zol>@F&C_Whl+n7uR*GS<<*X&O-Jw}mJSz?Ege3*6M<uKow*^g0Tdg)v6k(x04S$BH
zjJN$qDEy3%qu6FzdC{g%r9g-*%swNFR3!ckEM)Q0FRB%liJu({6&J+-7@q6G>L(5G
zey|?^??AAM`v%$1Wl~smfl;cm2PZSEU~VGKf<G+tjXamtt#F7baq?(4AR}X$ei5H4
zIhkc=3Lg=KyTeQ;V1?qTK=oaz#;$N9mz=tlx{eWY3t284*Ik_##NU@M-l|iM;TDbs
zOI{yv-fv8yooMfZ?~3RlYk4KGog$lcbA8}Ci5TTEzPM_UwMxe?fu|Jk7Q$i&W`FB4
zB;g>5SiU?K^p++U+S&M2I9ANRE1SND2kEC<O&D{VF<ko)<C3rXL)jzk8{j{uN%{pG
ze7Zbd$du~tf!{KSJN!QLg&FBC33RYcYuRvMS9BoBF6i)>z~lxUB#L%!C`4-R7Tk6K
zV-WS4!o9`-vi*?=I7r!#)B{nL?sbrgx30)BTMUHsh(tr6*{8q{cH|f8nFRU~3*hJY
zkFzDhljHqCc5?v<w0=<F`;Xp`_vj5>kd)BKj+)5NQ}tGhuhy}1j-F6=u4f2I45FmV
z5DM^a2LQ6pQBJyxu5yiyINe;E&?{FkVY|EE@HI;}XpB#4nlrMIS1I2emXD9E3Fiyg
zd=Y}|#KHuzm+Mt=LRR*ZT&shy=cJsGicfAq`QJuO$n0|FS4|?|MoFz}IJg)GhEXMN
zv^RI0_eJVkwn$w~xK9R7`(g97TT94+wKn?Wl$>0kn{47XZx@3i0AY{T#ms#=P?J>t
z!ee%k+~pD-zNc$z*^TbQLW5%rdyMgKvUANa{$uSGj}|s;@$*(f{84!Se`Q(DSAA(T
z7Hps9cDG=4pRJRhqif3^c?5LAkirxbQRcOHE-yqtT?!8#?TZUwf=Svrz633|i^=91
zy?S7@8Ql|`y8}h9{%B#KYUTQKH*B~vl95O<n49wS@?4(Y47w9trVKo%vkvRv?DI)?
zLj~qlsK7IC{||Q(Fx}S0(MdozmG6fe<BYM{$2$ynhid%sa-(~Ko<7=Tzu9|4aVmL%
zKj=tgN~0fa{~DRtjGOB$H3DKtwkK?HnHSD*+2#h{E3(IPcxJJ)2JncTYuV-%L~!W8
zNzi|@d}+B)m{j79?5iFL*yg1EZuFZxh3&ag2{sTzr+>Mo1S5E8A$%Cy$C>E+G3e|=
zIm+%+sVXips_&ujFBK_#0t$kguZ$Npve<^F;bR+8bzY0oeNX9RS@m3%)$a~6?fWfd
z&($TkYSsGl&rc5}MPLPr_Lch1)YR{;to}47zGm?_2LJUCZOT`@gm9mB7ZH*7go1dM
z{blq290h}Yhwt6NB3wh9w_)w&%g;$wLm9Hk%w|{lXC<3HEg4FvvjR}Xly35v5jdo@
z65{Oi@p{3hOd{C=hlkS}W1&)E$7XiQI6sPKC+(!tO-emcspAnl%ok+*Dfx2cS5_0+
z->2@xa@!?~zPKWaZjezz8$0O+Zf`Tm?i>T_=TBz7;K-woJZjz=bNBBTUSvJ||K4|4
zVjs_4kwWF3T>DaHK{K3bnFamEo)E#4od_QL3>@fx83#JFuUi&S=RoKI_MN6YM~S7N
z<${%~R_(>XOdEO#mCHb#+2c8-R8WI5K=Hf_)jH|3&>=s7BGQw4lAX%6uw8hI%-Tr3
zLdmrFjyIv7nTU;c_S__kcDyH=bo591wK!6?>+DzVeMQ&gvD|-eG;u0+XXEALLKN@D
zRJ%YV4xMBx2eqralTYr@5Hm2T93Ze5;M?t$xzH+ue;7{=l9)A!%*pM@ktCeRT4i$^
z;(-+oV)-kH6z$e?=;7Q<1#31+N1EEhQ4^|^T-5}*g|IA2DanO&m+DTz^iHQz#@)%A
zUHfOhb%;~#K4EuypU15WJTNC1INGIZbY#M+khd0m{5AX850r`c+p7-Kho}_GL%%Ip
z^*5Q@d=83YrD}F$GPr5FUS-~aMV(B^s;S>az~)Td)`aD@CVXMvv3%cePuiVD{f`*U
z*;XxIy>742Tx0Ke?)=8g&w-LB0F#(-xl1Y;h&FMVoJ=$Q+Ucg^BSHkOc@&`NmK3}~
zU4dhnWjZR<jP3tVF{Q-&k?iLUZE@WTZc48wjfW1e)b`GoqG3rgi^%Dy8Sw5CpE2ZI
zCmrE9w?Dkp7L(Hew&ywOb@N_y{BbXM!O_RR=$LsgIsIiXKWEkDm(JTaBdC2xi`_v!
z@w=C9SiAbXsFU6YhC0JIXL;*%X=0VK<tVb*yDUw=5r8)W;2bl>N)b`O2H7TK9w;AP
zy+{~B_-dKY2C%;bpPee9b2p-7BJBoAB0_jDo9+vnb&^c(zqQf`-tEqI0lZcj{bI&b
zaUO8deKbVwFed15e`7Mv{9uf`ha!4n%hsWs3!J~;Tua)tTeDR@rYb9JdyabqynXAv
zeYa&3|0qpdY2bL)fq0LEJh)_=_*o<F&+lXBZ8(4RA2ikp>GsDyHiKVTw98=QGosyN
zf_6hY_Oah7!zFCiz$p9Jr<58K<G^_f=i8RX-y4j_5wqqT-lph_(AgudXV%Km<SWNp
zZRL0mTj{Y^4iT>lmoJ}t!jWw4w4>vtB77a~t0XLO)0ZYx36LGje2i1Li_Tqt(S~!+
zV`&AER<2pUX72K}YfwY3*|45C8kVNMNOu+b+I!gN>GcO7N-&M6#X0#@;OYaGMy?U(
zPod0>oxD6@1He&dEK+hh?=zG-X)4;K?`^vH4<=7cCjO)Sp?W-Nu_)s|4piGO&gh^a
zdW-?l@k<(|V?>+`E3^)9;t>NjGsB@+)^m{`xJ_%qhHMk$VFeaJ)k9gtY$8w?C@7&0
zC1olv#d=HBsxOt=OV%o@UAlea$TjQmrET3Rr?{cO|84}tRo!)}lA|t2H^O;h<8^dM
zv^QsWPgRHSY|bCWag%V*7KImy?vrf}SA8g-kCgw)F+h=fN46;B@N`jUsCmIbvvr`P
zVYl&#!{(hB8ZmMf%ONnC#DAeGH@@9`YI9nHo2sTVFY|4DI+9i%dKt=kcy;PvuC11C
zy0=R;8Xp@$oq#OQoz+z6Zrj@3R(f0sm@t*$e*@{PE19-oahz(nVnSzbnpJ%=O@~7k
zSvE%7Phc(64A;v<r8;cn*l+mYmRyOA1lQMH#N~IL*s~PFkE)3KM}5E<jz2L;9U7nT
z7dEHXPDYwv6VKoO2ZoxT{Xd}Q+v^xsd8^=1f^-ev#AfaHg`1ivPQ)=;47H()ftFB0
z!)VbK^2}s)a4OvPx*TM~je*WlfF*w+tP#Q36I><VIKwW`Ygj9+Iw5Wu$k`bPD_xq%
zp<itnpi<f~>JZa=u;r-^|1G4WAVDIn9~uK?Bjk~SP6Knr0$0H#ltu@tIayIWX$0E-
zas)oH(=FrERN)hQlt#m*6uS#hhWh->79x#esYMm^rCVSsLmlzTsgIh2`_!#H#amm)
zMk}Xb6}&1ImSTkq5|i0F1d)<+&4a}~GC}N{#I|+PxdO-6<o+|fhvWNooETBp!yTKs
z)q5mSl0SaPQLBg&oilQzI*XT%=urhahD}$5rW9;I`0zFA_K{aJOFDjB9iG|@5`VKQ
zH!#4E1AQf-I%p2b!|oFJ;OZPYV2G@xEMIlb9<Q<USPm~(dEvY@E7z_+##X~)=B`+I
z+3K|`;x=~WdB@DPk1Utv6|(9ppyBaaAdzot9c<KHS*bTK=?>F9X27*A-x=ONW2AN2
zO1<qmfq?l*`!?X#PxgrC)jCx>pL?dYeFdOdN5CdsEmY*rD-xJkWmpC*w3V2;>olr3
zKegt_BuCY1zW@PNVes&2n~dm&^WaeMugbDMvJ-Z_seRp{!<>~yYp%y=v-&|}>vdrN
zjI_Nqc!*GCl{R7wYt0HrkKWMsFzDw;@p(Husf`E@N3xxu{p?D_rG$^!ElPHkSY7xs
z&{S(jbGd=T+iX{H?1!PoE6N!fZqEH{JwF+qBHXSszy)A9w&lawwmfKUxs4>x)|O`-
z!b;sfHn|{c=lbvuTU<GEf1_~VZ}uDq)~~%_!`utjrEDaAyGG$gv;1b&xhqzzxZnkG
z6YaSjKUS>Wc-|`QdBK%cYu8+;f4sqbI&XQ$SHT>-U;}hez4AX9Qu3!^6gV#vxze=4
zMu%m63ptb?pP>%+Orp>AEMyY+>$bc+fB~6z<d;PWMvJ+sP<=NhoC^I};k_1fFEomm
zfA^n9EbjZ9atPHwh@pM|fe!KQ634Lw#i@WNsoH+Bp?^?e@$*0GBtxivoVx`S>Uk#~
zX%y=D7nq4E^yh4-^!~LJ6rYB;*RVHhWJ#wiLiKC>=e0qFy;k0;%RjH@eu7Z_`cN3M
zpZKB%5U0Gaw@mN!mv@FXqTXp0jvnT#%^%e)3C1e{M@{n8M<~t%$&-(u8I{n!DdH4r
zB~);#=IT^?(w9@kRSw{{z}GDeZ@zk&hxRyHP<*74$XrM)vs5ri7B4INP<>CXQ2Zdj
zPuavh<um^=IfD+>{Ajp7?r$HrnfR2=%BSQ;J5+xvKNJ~S>k#ZICD*8U3o1Sc8q|pf
zOLT~Z^AvHEI{5+%?DWcu_2_{<pIiwn&&k$bVng+39l-d}+kNSeChb1!$iG<lOWcoz
z>R-lZef_1u{I4wLSDx)R>5snu#=dN~PHxWw8To2xwuNd9{(2NDqDfDk3ObakLvbEh
zoOK9hTd`IEA+9IDQO8dn`8400$IMsWOkjEEn^xs$8`7h#oYOp1;?pcp38!hyPO}=W
zA`I2|G_la1H9ViRKBr+!l>T^P^`OoQIbDUGZZ+BC)jWpkw^^ZYvx3G7|K5h~?|n4i
z1+0?qU6vya4bk|b68TXJ%Rl}yEGi~Y+|8cpX1TC}0Vn1b&wq<mFg!FWkVY9GlUT@`
z#;L@S&-v;FHtb71)c7u~1U58FHPmSks$a+5fE2_}pZzTK7d4K!_@k;`XO!c0Mmfd~
zV-DqeI&UREZ3s6!)O4jWO4?^MEDdeM{N=xWeE3na|F-!f9Ad@rsN21g+pUt}p>pt9
zb@3D5)DzzPN8yig=fDk*rC}uCr3SAr6%f5t!}l^hy^Jyh>lP|@zMjrfaFM9vN)7C*
zEijCGwFo&eHtMfdvMcTJO6B#yB9$Y45#hPgBGufdeZKk8+fCjFe$?!D`rEr~)wwx_
z2AMbGu}=#Kze;$s5rNzM<u)6pG*qd#S=RDrj}k!KX8GQLG>n(G`s(slo2Iwgdh+%d
z+W5ZR7niq(0dBzrvNh(9`qcd_XRZ2~P2JB7xrT;?*0~{1tS|ZMO*TxM)cR{J>9vlA
z*Gd!>>5kH!VY76GO~^Sh)YzV*kH=U<3~eHg(LkrsN@w>Fc%Vj8-6wriKWW3ni;(}5
zmDK^Ug=9kFN06Z@!$14n{IlV28paPAgz|Tr3*OWzep>9u6SnjGZm*ahRf&s{Y?#)l
zZe3%2zDCU-8Q7>@<Kc+!*-zT^7jIPsKXRb>k@YqW)utaA|5E;JjgD^*Izl~YdBzGK
zGT3>@JM)lr=AnFL<W$8D$6IbcwwG)eKdXhLif^94TH<-`wqozL{AsAPcY6c*iEqlu
z+pr)1r18AihUQ{hz%I533o_IoRKLgD%8%OgA*<NKkJ$4^`~yF#<RjMkuldWvHj)op
zE7Q>M;bCtdKgv`7@t0vyF@fT~<C(sbFRvfp^Zehl3WkS91kxxQjPF@%$)Z&x{i1S5
zd$zvb<2~m`J-^5DZ}UcMvntb21G>%n%4Zc>`SDL8Dcfvhw&hiQ`mA!dRWMA6w}V^u
zqjI(zW~E{LtW2beZ=TF*z22zI^*JHY^^R=U8wE+j%Di?DY!xDu2@1FkIIN-=g(4N}
z%fV%Oy38UkvjmqZ?NWQpEUy-+l^}lc@0?$jZ=b{K4%kKxS;yXO<X-WuXWhuL%hLtN
zwxJvGdt-brUISOi?7%597R&{KJyimxj>t-2=r=M^uFnXqoDDu>S>^;y(6DPgxt?4}
zwTApFw6t;$RH?fU?v?v+3dLKA5iAobjXl|v6>O&6V_B!BzEgeZQcAms#sf>rZRvCt
z*)`uTw_aSXvPKQ8!pkk&<+hRWRKAgkF}T1|cK3_Px#FwD(l)3K4Jx-1aOV~8EmmcV
zK4k*?q9#w)hsnx4*;YV*w-#U;L3Cw*7vGh2mIca{*PsdasacVg>g}mTb!6(bW_Y`-
z3Ent8W*TCVlda5Mo1>b%P2N0J0BZq5)6M0fL)|^yrJYKXz^oFg!Vy93R^rTy+yw<3
z(iu``CfR0sHv+_Vl!Mz)g%+r;W(%xo7RhB(#M<Fh53E~l*2PS$a%EmEkEc{$+SJK5
z;}|oE?2A%Pu)r#s03PUVvWNDlvL_n`#8{j6N`fg$HO1Zu?RQ2Dm2!qYdtk2?SO;gQ
z<Qe{$iLlt+4YC!L^UPG0GwqXaqGPD&Lo68fP5BN{aF|8ENGV1J8mt#tBVVMHnZQ!}
z7Yk2R(i4?v?7*h)#2Bi86K!%V>&eQ0vbDs+Q<dN)7FcX%&w0A4Io<M}u571UkuiY=
zI+ONg!gJqXczC9YTwsBf>r)3~ov${Sh9c_GLwg(%C~J2m&N6xy`{IRGic@5df?mb-
z8hG~FyQS=np-Sjgu*4#k4-4fbcey?;&n=XEfTyK};(C6N{f!Lu)g?KVC+m&NgI-}d
z{z@7S63({p@EEFvhid?1gbFx(L|{c7ZlQ}Ej%Bqcozbx<|FHRp&-#W5jY2)Pn-^a5
z1D^@(iz>FbDS9fSmOU%~6g971V}T<wg^J7s9%*&Am%m%4h^tnJs+v-2(+}6}Dpa%w
z%5{>0Q!Map<|$TUl)YI;Oaiw^Nfs$@C0MM6o5u<dRLNo++cZ@A#ft8=k^l$xM*`6!
z<sZPLUKSi=otdVT)2sk{^jo)my|h?=G-!O4MV#m1fbVR`?LLH6t@%OqK*iQs1M0e4
zOX^6`h63TQNr2M;t)C*4{5ZAmcq@Has2s;zpj5|e0FJkkkJtMv?eUeW;gw3{fqhZR
z_}ShSoNBE&)dqaNGIc8zDlQ9EK#G?Z_1D&%zgD~l{+@n=O@bR48c@k+7uT0u_jMGq
z_I%Y%2SV<D{v|6eh?XT$X|Q`@|Ellp!Y#VUztFRAM_~ahAQl60?<y8f`)2yc6$gY1
zt@{fVF=o&sjX@6<6jFD|ka^sh$j$gQ!n8!iELHGwylu)w(2WOf%q~2C@5b!fXCE^Z
zATD8m^bH@g7ulF)RyU2_n6EFkaelGoLFVfBDw1IwdnDM3k{kC3_`3N|ns;NB&(ny4
zpGj^4I<Yf(`Cmf(zgF~e1uH2_znAf&-?R1Z#PwpmZ-@??Za8qWv1%`8W8EXq3c&|{
zHV~otd}uJ42oFb0$Juf4owkfRFT*Bdxn0|QK-7q<H?G>d-RG;mzsqa@oaX(7Ux<M1
zI@4Wd`dhpvZaWLho^8`9xR*3?lzrm<*=lO8vRh4FIox2OP&GRJw<q6%ZipL4eI0er
zXdg@i_Us!+Ba!SGuheQZ>Yh;__ISUhQJZXQ-EQyK$Po(W4V?odV>QMgyT!=U=xy>(
z8q?j~K5DeG+ehWC>}F@-40<a&$)O&u2{F<&_BIliO5`mT#7-EyF~?dn$K=Gr#0I;u
znam_nss3tDR%qVp%EsC^Pf&T(lc^%>H6!(wwO*0+1p^R&))1I?qTLRxh;p`!iZkVs
zmB5(dCc#gWYWKiUDNUskT%)*0PgZz2hwZ9;*NsIKCC1PmRdH)2umMO@sf5-&53JmB
zwsCr`@Z=euT}dK0Z_V;VmfSw6RU?zz2Ma7+C9#*_VI|RieDb0zov|l_k#>8uk@Myn
z<BRo}+AqSmOY9-aafrSjVl=?tt%O4?+abmbdkQ71z_B&M(xfIEDZ{RGBRPK6Q)gMy
z&{8QH^B}_AlEewIONCbLJ`1I-<Z3Tir~)z*BtUMrKp)1~d|7Tuz%m)F92>++ZawX~
zbtAII?y`E;jhl))#RBX8?{5oNQfE#zioD-9FD3JMG4H@xE3Myn-rlhpkNx<W*bMHn
z$7x)}WJ%WTF7Cduq?7BHWBZLef3)ndz2coKhDzmked7~<jCZ4Ewoy6?H|e;KSUoHJ
z0wVBG{hy|^_@O=j$etgIAp|y5KV}~ub2TbI%II+@hV}Bam6e7nF=~t}KT3u=Q$N2j
zC63!8J!KjjZh0gA*QT8Lb$s?152bDKuh#{|q@k;suM0q}BCYf{`p=t!;@;$+;?G-5
zdHfdFB$r>LsUc3~zQr=V*I(Xi)&}pj3P%rF+C_GKz1K+F(|)y6V*AOl0{utv`@v2L
zwoGP9SwXrltSTRUGGZ)s=~z9P%f%D)dV&#N6EvPGTJutUeyNe*ms-m#A}_Nl2f9%G
zd4rk%XW^%8k}-AClzhfDd7rUq9<V7Ni1q>l7()2Q(^B5=TDUJ6D1OO6>`PYOgE1@&
zwWd2&+G8tsSzal{Jq--iCCiR+FVEX7<2I!Ek7O&ta7pSuH(C0PrS$N(mUpYc>sD*<
zR%`HUVrc9K=HS%crg3uVxdz9m@no%M&N(W{WPQj=&W+ekw(Nv#fSK(PR!u4)W6-2x
zxb;V&sZ(C)_6LeML*G15J#LebhWfUJibD0B)}=eGlXu#1q|g2}CQ5%af_Iwn*Ebz`
zziV^(T^o!vG(GQk)9;ow{iH%i`+^Es!0<ikk)yGO=YP~n9v)ixX_QUsqpm?t<5bJY
z=RLPWdb8Uh@gtJ(W<&os2U#N#rPlJJn#w=YBEQ+_!`NZWsO-OURrc?!hr>e+a~h+h
z*BhluL#x$ae(VJI(>4pAwvvX2%Kd3aF@EBkTFsmPDEzsB^v^wA`l7@?&x_#y+=@@1
zGe{}u(-LlWM+TR+i&-H6TtWHy>ebYluU?~wbru+o#7EJNb(U<MQf;=!&C2G1MJiYP
zqN+Aqq}uj7H%5A!wf$}0o%ebl-)C{R#LyP4@{1<(7EgVP;q52<<r6k~X{ZW5Vfo9S
zMH4<@Ic{<rq<8qr@eZ4uci39-?id<WzT4sB-S(X?6-%U___Xn();wW&_k`I9q&AgS
zz%M<S;v}Ecz+|N7iu?-&$BQZ)Zv$(><M?RlJ;G8|0)f}4hJ=EJ)TmI;*acc>fRnx`
z_szMA-2$(7Iw;?1L&!^po|Xzjwgy-c4>)Cgz{pJ+stP{%&#)JIV4vcTOq3q57Cn%Y
ziBkHk20dVOj1WR@MZMpf#E*vf{WfoDs0{BPzPN1lmTk3`jTTy4NTs$s<9D?0c57Uy
z{+R>T&umoEP#xrhn!rzdQ=#S5R>jvn$=5CKSm8IUSKk;m-gbzN5x1i6^+CATN*Nxi
zW<IMO{KPl4gE#+Cc%PxbeU?8BmG(Z*a-TJz{9+k-^PKU=lMDFP5~EOPzt$ow7zRln
z@D}r<mVMN!_wZx(T(O{5B_Ff;Z}b{(v{t5}s^x?K412M5mGjtAe`7316g+(%ZXNa-
zhmY47d<+j&IG_Dz*o)P~CpGnT2B5DqB!68RrPQx8h)zG-+V*+x5I-8KOKjLKVL<ZL
zSCoUR^>npGUTq1k)?i+(4EE{IE%MJb;vVSppVLah%%i7@q1y$a>O#@;)&rsF*|=uy
zr5y3t8(q&Uo@CQBU5Ae*Vw7Tg9`TAUoMn%+Xu+bw0*S3zC5UHR6rUIXSNM$IMVG@T
zlekRKC{FO>E`MdC@wW$JG%i?q#fl5ouiT6CF1KnhW|YsnM5Wix!a@^38yi}uNjEKK
zqacU<->w126|>5%22-}UiH(*Rdvdvga!)bfOGCxXF*ur|$0JnT5%zA6t}mahPqQ_;
zv!iGA58Lqm-2oZiRcp`Puzux=3-)4wkN5=xJW~VgFvfnoDdD1aiSN}@TcQ22U=h~y
zu>(&NLk$YY`xHKNU;}PJJOH8O9Tpg+=+Mk|#02)tS`>FS#an@YQ(SVWiDcX!c7pw=
z`K}-DR7suI20MR|2}-8UyvZi(?FVeKHm=#r>3U+6=|W7hnEvh7^i-xnqZ8-mStiHw
zj6OpG_+isx6W^h-V-P24s60osmam<K%?d}I7Zuv+s`(ExBl)WL?D@Qm;oPC@h;y_P
zdR0{wZx6u3F5VtEgjezQz<Js9Ww{Q|R{dfxo4Wg_24my*lb4D&{u0Fh9G4yI(g*$+
zbZj;?_QTW+1$jYh;tZ`4G~K0uGll$AZ^0DPkmqRgG4oA^Y#09=3tqBFhasz$zxZtY
zp`X9%f^`?3d(J8@Ydibs7ae)@*>*7a{1xlZK5ylkvoBn;@$8G{UU9+;&w1gob64Zf
z>hc#H<0<Bnk^IY7ZCr8w*>X(2*TpeqXXE4}Q>-}*Neiz!a-LdDRh1`mtW=Jlx9-xF
zm+|q>Phax#g$pfZ)w!!SoO8h{9EETv!DUW@@u9N&H#?>-Sr|qYm0m@F2PD0&TD5Zh
z2CPJIFj}c7O*1S~wU^VCU)HWaXZgB~e2C?pyXxFaSM!P+=Z(wxxN;>gH3D}VU%54j
zDe*a|lc*&0v!{;;VmNqw7<XuMy^k!VIA?A*Z*#E-_om``?n!PN;o2Zwvu*c}66MKo
zQIP;R{rEb~w*x3s!I^y3-_z$^fTl9on(N;K2&H#%>@^q}+#Wcn+<)z?fOX|*ERasY
z61+CR)8!jLH#4@&-5Vl?qxv1k#gN}+3ZP~@=4bBS0M=4q*5k_65#+44GAO1=fYU5a
z#HKl{^O821lFDEov!q~;aYhB~Ylne-Oc}wRgbwyMKLyx-m6PHfJCj-6$wa|3KJE;x
z3D}7lZNz6lb-s9d(iLi>mAv>Aj^fyzRBrNK%?bMLNefOGx|5bg3EnK5x)c1Dakb=N
zl3bT?Urqz}>?|@2IoL4d9nWJ3%fPeI?dJrB_{9=`iYW5hU+n>koCJ#0nNVMPi&0Rd
z;f4ga6rhM4ng(vpYTKC{jz5cgQv49=IgXqQcI2xb8jbb%y{{q%oDms=^+<_cB!=c+
z-+?gFWavnlso=RxlQX23=&~bVo>NlIV_G_oqP!^~j*LgjoQx#IW$GK#rPTKsn2wZ{
z8Nqa{dV2RkD{R0MSbg!fq-&W#WOV4NzabJ}psNjfi`OIU+KTrig>6aFFUW%m7x7EC
z4OYeo@jUvTuX=PeLYy)uS%%Qp)BQ)0&VHU<S+ghn_^`QHyWZh;^|>q8fD{o<*Pp-o
z9B~20`yOzHrtEi7*suofeno}nPVs95qXRP{>~ltkmlP|Xfzg4tsW3Vmh|KW!vG9x5
zu6?!G{dzAv@;&5pzUP`>gL!hl6Q16Vo7B4S$~->4i$ivK-;pK!P~%HD!0p_s8{iv4
zBRl)z_xo&1cnbrauR4Wr7w*1-GI6VA8?60^F27g0Y}2s*yh~qQ0j8CgUcw*(MSDbU
z$0o6GzUk)CC*p+PFcF`x%9*d)qla*g{seQ-7?yM=oxRDt?&Mg8zm&9U8VUoJ>i(+Y
zNu+5Acj5TEbvs<8MW0gKKx|#O81Ga)c2u^*7SO*NZKC29_fKN`e*T)v&avq;5)mg-
zgdxR8p3CcIW`QI+MMWO73uG2EdCu-yc7IJIql3Vs0)bQHm8+H|u4YIs;n{c8Z&Mhy
zCr#|PlkVhTEqkS;OFyh@+mqy}q@lR6Pf3!nl3B;)BYTv_;wj2lT&6uaj22lN*q`@>
z%Z5nO*lo++Tj^20>O;>08pGMFKNK`BxBA()!K=?*1w3S+LsPj2I6pR`r?3S)jO3S6
zzA6IM?y*k}Dh<B{R8Gw$EzEN(SH|G-?VepB2JgKG6;Fz!B!qMD_YMGbCzBn5CPWC@
zW@O`3BPL0BY00U`07N7S3t^rjY}JHwSP!lTb|wqFT8gK6)k^-Uv=aQu3uvu~sVbr-
zoDcLZ&cdL59IquN39G%fHltb8pxa?lT}gO!BuiGl>dkuunqyA+9}diBg^q%lwU@@b
z;f8@^mI_6#eGG7dyhKt52$o45&t*~vhmyiC(J86R0xUID*bEp82g0X*2N3=Q-l3)V
zkI4iak($J#Z!l@=Pm-ae{l;YcVA8bNru*XV2qAW{#jKvB(I=kUlYs-AIl54!CrpF%
zWy@>k!edGVZmq<o!85JAo3~U7{4d;aLMn@c_T`=}2FT6fzAEll9!w@9j`6w%{7ZfK
z5?^wC;a^xkSy1cpGjpM%yT31K7)(0w2|18-gjPg469<!V;mQ(iL!1M_9Av4zSRW@E
zJ#FesTFB6En^-+t^}pLxD)$ugx}?2_Kkng3i=NC_ArhM0mmF3~rtM5-4)i4l_3@K1
zC^(d#u^<_@BbmHJi4Izn95Im0!A^EsUowY;v-&DY#xF@a2bF4Ge{wu&2UNy%kh_N*
z2~C{SlN?e?I{TBE<%%--t+7AaBov(*-kC4;sk<%xgUrQC2k;+yFJm;`yY#J1!qxEs
z7cJb~mrU87H0EdG9l2Y$PMA2~@fAy!giq#uxNq51nIcR*lJU&pKyuJs$@uQ1m16pm
zgXt1IOFo-)%}?fZC*yd2B57K@Ga28jw3DAm4le#6nZcO%B*&d4kF2u>k{MjijT8>9
z^aIxX8R5HX{#1iICZ(e{=^DU)KO??4eQNC0(9qn`LM!WfE2|;=noj0=!Z<)9*|~_n
z-o=Z1<+L=nBy<53ZG)QcE?@yE;b4-xD@+i?A}L?O2P^7_R}VxGs0}w&lbFkDNZgln
z?a%|WjTc@<U`9{UUP_K0OlD9n{+y3u7W>mdFI}Ul$%TI07`F4hWk;rlflLkem22>V
zr~0IQ`)WgjT=)<Lj33#=zsVHvC<RQiCUyae06}*$y${FS)|by*?Q{R-YVj5I9{CSf
zd)xl4+GqM1-or$V*-njFEmPAY5bh{$0Lvr-4KG&Do=TFXR@pnQszA*5Sf}cJn(w*F
zy3!Ut?~F`Sm^hF$JJ9|5$}~%3D6tHV=X%LfGO169!Qf7^aB9C$qSH`fZt<f}BvZG=
zh~s-S>W2&}Jbp;{!o#@Y71o?LdcE!8JJgH3fR$+gz}O%<0f@8?4H~tY66&>Q;x3}u
zI}tOSBoQ(%b3)4i?o5j(_a|L<CzJ9sxgTgp(go=#CDVI&7)-d`hxep-dD6H;(X~B*
z!pTVkS4;PVHcD#zg=As}Tl0?_N)Dz6rQ*iqIQ=G5fjPsOsiYjo4xso^Hg3sOXasF7
zo&wlV!c!TLhr~gLX7(g(>|Qh^x^Se5dy#&VmYv}Kr<18SJWHv9r75ialPQVE$qaJw
z`>Gg{1_k0>bt_e4Xe^#II5=pv9^8{0ls^G?*K`8}fPje9T*Z2Sqaj;os2zd=?+|~|
z1Y;7o4oN?Zs(!dsgCE`Yc^9-9+<ZD|q`}Mt>8DwG1$_#3C;*Q2)9=r^i8q8RxHW_a
zN}0uxgTDSj6jh;qAhZZZcl7pv?Hoxsi}#Zd*w;ct5Y$t?H3Vc;Ap^;w`YE@k?d~3B
z0vyOx|1>PkjQq<$+~QR@w5QzUshvrExus&->6tY+Hq$yAn|Y!>bKWp*<^&p%Orf3B
zFc`oa1YaAIW)_M85wrR`lHB$%Nfk5q6S+NVAZZ^+ScuCX1p_Tl7&!mqh7?tj@F2Ge
zPGHFd^BHu~gZYLzM+_!Ysb&f*4-<=|%&Ey2H#o-MUGLQBpnD`%J9uYu;y`i?Rg51H
z)aV+Z(8+5p@WG0lZBawd9jwDi!*=k#CyXCTYJZ_5G_+wbe$j`CL#+O%sJ#qDF1&fY
ztPFCHQ~hX1Tx;=<)8=t{G74c)x34!U;ol#y<C?koH0f{IB(>y^9dBbWbV+3l-hf)B
zjxk^*?n|aSC41AQ>gV+Ecw-5;?b`<Q4gxC4%<ai^LedQ+$Mq#g@(dPtXP>#xr9YW^
z-S*_*?S1@hA53bu^;@MMxFlr>YQs0E6dDBweKPBljXm=~Nz?k1Ls=0^$%H|LhYlqZ
z7+?{jjaJCLmss~&!o5x2)O#)wWo`(cM^ztXm?tCFd7fiNOMl@gf}7_8$NYDba>ej4
z9CKU#uny=WzyR5AhE_q!U?g`YZLGY5JCb_8+vutkaFX7hWOn|jb}eG9aD9WxVS`C$
z{xFB?4g-y*u&R{I?oE>b)|n*rF$sM3oW;ortcF9nZY~y7{DEMs_+kL6>AGZ2Zzh2k
z;|ap0v6NN^!L>q`&M*N66>baRf+O%a7PJZYS{HeNeUFUs-)<>)COitq?x@G=IJML>
zIN0xW=JqWD>ZwR1y@uPIWuF@UZxys-hbovol(ZFpNCg_aSV7Xr;KhM7Y`JH1rLub<
z0FW8Jcl5BlEMlQNB{>wL+BfJt#Md^f(nG^-IoQZ1XGOleS$#V+d_2cG-PE77_cEA0
zgGu`x$&BkNS$A00*6;-cGUNEVD49VK&bEBYikK0;Vnu-JHa<8G8@a!U1N2~K=WuI2
zw%K~~i%mA}&Ed7;z~LAB)9usao8tcIO?;77xhG87wSrn7+&5<!^2df%@aeRIf2J7r
zOx$=9cT*orzdYz)y2`t$kNB7R@O8c<R`rQg-IhOg;)u!dEs{Y(cA|zsy!G?l*HozU
ze}?W+K)y>Gk2%hT4ql^an-jjsrH(My<DA%j`WkMqAigR53-Ke+A)EapG5gntW&c1q
z`?rbT6;--WJjMFo9t(JMSOI@iF5sssU>8)%6mVlK;HhB+Y%3S=+u%sxTY=8d2M^AY
z3eF}jvU%X@%6Q!h7Y{-M<wvke+5UnMjuLV)-3M&Q*!Jn+jg-TO&K&~T&czC`Q<&JF
zaGwCHA@e^I3?3(rb><QlppV+*eBE+)hL5ThG{J}as}@@yK2EIQ&(>sP=-TeGY;Vl8
z@p0P7;um)jx7*gDAv{1<;C3!}oj+pYaH?oU+*cukVMhX391H?Csd)$YA{6!J{l`^8
z*!FM>ygDOP-w(2~vcf;j%^%U8yp%0>Neeyu0yx)+u-ON*z2BD1?Tz2Y_lbk8d^mD(
za#ATdy`*q*cXAj5KO*aqy~9#yS<e(;P5-F1sxy3@R+%{A>=L@}02fsUxjG9Dc&W?s
z|LrOPb1{6Igb`gUTbm^Gv9)P-vhr@<l{AO%k<?Kh`VUPxb(Ep|rz<OT@RO7gcT_*U
z(g;d@xQSa~yo@>Q9P&r8C^0ez8Szor&vXCaU@~hkIjGc!Xr~Bp*hY2=&|^?0ded4O
zx%bfSB?;q@VV8N|gMf|Dqae$rXW8F5`k3L;CzZMM9dNlDlCI+IY$h1TE~<lN1=vUB
znWhyt8lm@|P1NYHyRgPjr4MWx0EC%$#fOP^vz_ZVk>hNHW%;T%{fUblSD(N7Im$mR
zJsSS$L<t-}Zs>Jvh5nsq90eRTJi$>tNr#ipQ$!Ss;S7*Xj0j{wO!rI>0l4qc-cAOL
z4wZw+Bm>UmF#W_YrDTTQ=DW;1Zp^^t>-w}c0G4dw>(H*{RBO_Ol_nvma=v2<d*8ui
z3TBi*uQjZA0_|$P9&wswx>CqrFPh+@1=|HxWU3V=>YW)T>bo#eh>)Tn^(B!JklfB2
zH43K@Da-dZR~m_Xe(l5Ja=$$lp8kenSO_Z1{nk`?x)oLj;i=Oc+o^@SGv$5RxvgoE
zb6DTLZfsCX_z3wBZ%u^9qTuoV@qx`oh#JD}Dzzs}C~yD58#0AHO`*t4px{WRMhmT`
z_Zu^I7&jJ{l2b|vxAs7{eJt9BphnF@N!?D3Fw=gFO}p>qOUV?y4Jn8laoM|K#yVF&
z5>iC5!Nkw?4`MO0Bj1UBVi|()eAQe2)QQE$4d-9+93>YskB407)+{ZK&BJzE6HIJh
zL9DvUI=KN^EldjV53}7Pv}K){+{co0D8I;K5Kn{n4#2Ywe%r!d`s<;Fg>B(%vO0q_
z-BJ786f4=-yLuzDeKF|WkwNXxf!eSWMGBXk`&FW1&0)GR|E>KA>fMvYsflHA*6tNn
z@8p135Gwbgevrg+zFavchj~Z~(S($CBHzdS2{y&iVy-a`KYo_6`9@|l^#L#u`I9zN
zedW#6Y>IthzZ4n>P`N7cknWx7-s;DOlZS-2X7*P9Wfb9%@b__VHKSLo74jsgSsQyv
zI94RlL?H@kf0At%62=oH&7Fl%<rvdvFce7Dr&sFva@>f02Hc0AoxG^L4g0*+HaUED
z*fz|2{#dr>P^Ag%d+480sE*3B4doXzyQe$YJ(XcZ3B?(X4j_;CHmNOevjj?7E9%>(
zYiJAaQB;32NqZ^?ISdM<NT4N=04j!=L&?!hXt#7FvzV$WVzb&2Q={#G%Y_S`xC3!P
za!j8X(U*~epJN6Tb`~E==JqAW!Tu`csV33e0TY)@8PE<v4+y*alG&(acxKVeJh$AC
z%!5fXs3DvOZwT|uvd8X+`i}1teMRXscc;QrhExd;6WKPvHBJ#L3WSbS5Pc*nh}baN
zFqASQia!)VJW8K-G(ZSJ;Oqw%C+#~WS!i6O9Sv(~B~*+Ra+8f^F8nNCGD)b^(i5bL
zk*cbh8)$_Qmh!G^DmZ>G>$}u4oLn$SB9!_~dOb_~AEte23GZWT2EtJY&>^`&2jC&(
zv$bq;aU&CQIRC^1NAsHpt}&9(7;YzTyYuY-YCFBg@F|N*I=3-YF4p^keQ5|g_@ebs
z2r0waOdrG+RC@8_t1G>D3;U^gNRv(bHxFGJ4-BI*#s>{PfsjL7yD=#&d9rCo_G}Cf
z!>l)C#ro+UE@QV5*yi162*2}|v4Wx(5pIf~P8ojiltG)qz#OzAnKC5Z7Vwn?rR?*J
z8?<-}J;8O#18bzV*eLMJ6;C!6{F}C_zTr=NRlVdnx}xH}rKtP-gk{4PRD+qB70~?O
zh!R*tjie#dL=V?Akkq65gSPDy=>hf7R3px8?%(0~X}o%acy$oLIO>m;vA~MIv{F3c
zf7o}VKH&Kad2oW#?%e)bf4ewMUds){B=1X(hV}PvjY>H)Y(!czs6}fgXoA3hux|&{
zraw8@oAeVBwcn65^qPD^sEOclShtgre8lycRs0vM;-jsVY^d2vJLms)6L`)>B3h9>
zzG;hEH#<C5<+4XaG?fJ~n|Z5cZVh6|!Kzu6Mek`_^k#({hb?-x6MoXh^0o|j{qL;l
z?aT$MEei*<x8!a6ysfDX;ckj&N)WuZ6dxVC|Irkp!c+a<j6n0l(D&T~2y5OGwp28S
zH?TrN$EP6h9A!cIaa>T|8W)t$Wfqjd@`7S|QrLmMqzx&$R+YA$Ca@l3S@Gq@n(>ur
z6o4xgjezu>Ef^#W0|86;)6ClPM(rJqMFQ|$&IY6(R6O|(f%~}a61h#HH{%@a`>l@J
z@H^@tTWUsP>q33#hx$6NW|PMP+ia5c@~U=grsfCBH8(r+`LEX$Zv~WU!zU>QUbfgT
zlr)akn*Ajw@-1P2?|ekbjb^cikt!j$QFB>%P};XS*4!HxtIzq8&}GB1ON)M*S)ty@
z3gu%FTlB`XMMI;v=*F}~5{j~0m#GavX_gW-)<7gsnD1K~tq)tTG2XW!Y;`%}^ztN0
z15qBQ4`y2R^>VAQIDrtgAum8950lwey4wo9|7sh!ap7*sHQBf`F|c_fhHr=4ShR#M
zkP0OMwb9uuaia%1eqeSw4Ono%)5>%~>mH?IbpbuB*_Mv)tyjmcU|3;9P+bYAZkTk;
zuq&N;Fe4GYm8G4%ahEOhwzu8wg+3|X6-hKk1CZ#6-8-c7rA=ssqXgxLCYWppZ$sJ$
z3c!705{~w^EY=(EY(;~91}*Si^=HyebL&0GNPNq@4WqK><!c;Fc#babU;7J|cMkuy
zJUNogyf9r%ld!<l3ZNlyJjn^eH?VYo&NPINY%wS?F%C+=$cGzBHC0OBn&nYe@1uP6
zemQDy7Gt)QY>iNg0(5f>rJrHxu?p_YEWP)Swe+Uz?qY4rXNO}etL_=T=$<gznw#dj
zBQCiAR5fzJz1`OAS=f9if2!=$rmdy;|Ji#JD66jX&bRK}ch|i&k5n;>Q6K?A^9T}>
zH9!p@$#!Bp?#2j^g^d7H6dG&`xK+g<Cvo?RSHJFl$?GKTr2RUQ<uS5qKthSrUXDA@
zUP-z$IEj-dSy^6rc`*gZa{N}m-~ZeDoO^3vl1kX>E@@F`xaaJ%$8Y?9-~N6%!#IzY
z`EnUw9!_=bQcu77l=XCj`!$#{7^->QlXAxI8teA%w=-dYzFb!9H!1c_sajt*p&}!B
zz+G-Fn~W9yT^ZN^RhaNau)-fjR`{tgtZ>x0e2x28+zqTS+8)Qx(f?TX<-bh792w8o
zKN(r!2*tn(8v?n;=o@<I#o$S8bmWY(=`>=Wt#yCE^UOiPT7qUaju!u283QJZn&4G)
z-wZ7V7#T_K!T9B3V6*cjcYS{B9I_hzcA2~M&-gNCTqX)!0{c$ODKVG@eF6IOdx5KF
z+zD5-h>%|-yl5IJvTsYzWFbC33rLZ!4?&5qgA%)T;K?@JD@sQD4~;PozFZ;F)#%ol
z3^xb)h?pTDQ%DSjwf5?*qIQjLy&kX|H=2#2(RIP<2ZsDImI1&v3~htH=|OG6-ZX01
zMLZlR7Ryg+R-x;+Wv_4XaDRL#vkUvNrDs>R$t4KrAp!R-?!!foMWimfa)#b&!Vilz
zi?SCB{?~XCmtA<GHM_D!7?lQj{ARd%5LZJ%Bz`;^Rb}{q*<iph=!DtqvP;^m1^>Pb
z0R9h9dqcC?FTZO<y3u{B0?QYxoP{gbY%uJ6@qm$m1|du^Jk(~Fw@BC#AUAxwFXbY2
z?kALsnQuXO^|ucg>1}j>6~QV0(LPk`zQ>245WxK)5!vfQ{eGj2;=T&SE!A(tXmg|c
zIuv|D{l4~8tlzgYGWOM~&&JemAT`F;Ik`nj_4{044UO(EBhmk@sK3b{Lj5pRgPeIX
z<;oIgqqgyK8Rh(X(A3Zdu~3hlMt^REsnPwPki<BV{xq038y#8h<W5Jhji^u*2`<`3
zeG_nU!_IM8huwflfmT$9kuaRq6z<X-f|<<%Ij6bBptpt5_-ZKLyFZFl`BP;o-breT
z+^(mAX%36+VxF3br4YQa$?Qu&U~~$qhfaT`w0sHj;iSC_GgL$!{ReATi+e@wDw}ZE
zX+TxuO|q&NK=|1N`<+je@ZD0m&`#>Z6#2F(NR94G5xMc7%6P+n4^Nh@%5TP}zXqL;
z-T4QJ`XhT_dswS4hkLc|r80i-_h4*VS>W*36k+wfG8O0lK*d4do@^8k+GiW6qLicL
z%l{m7nFe<x+%92^&IGNb#{D9{1O~joI%Z5AqHFPAm%%;$pR?B?U_TlR`@#AybXmuu
z|0tlb!Abw&b_s^`+sQBA4ZoE9lD`ptsd0bHFZd;mPZu7u^1fS!C;!i=Neon3_rGqM
zO{4o1noaEf(SWUJbf4xP3SB^Jv&4k0hM!_u1zo<{VmEN8EH9bH?R!6XvhWJ^zs&tx
zUT1V-{KRYVL%-o!+w$l9P1LDA8+59FFv3xI!hZX`6wvP7H$ZG8g9tVhQc0~q2hQv&
zZ^w7cd)(;02$mzZ<G(%;>HAl?*DMt8BvxDe2lmC^f5K{AaL0K#CAOg-pR*@^@_32$
zd^%sM(>U_*=~$7`Qbj(MROEH;Mby&aC!(_O6YfRi>NX;brsWY!jFZN%r{RY`3-U;9
z5Aq064voTgO05eBwA&M<uFAc501$JhZ!-skqPS)l13M{~Jy2#jPa+Tg>k5e@RqnF~
zin72e7S$<+p)I?nT@($2U%kWjg!le(%)5xx9sc$Xzox?z49zF-E8T~2=mqGvInEF-
zSlk%4s<83G1Ztl5wMWG9gk)ERjegrqz9*@#cejkE2ag0HNozh3-feLa;rlXtsg>}d
z@YEs}_<%kZNCXIv`3fvaX$JDng7H{xd;dXOY*p^+z)S8|akc27s;`2M8Ut+Z(`Dk#
zNyLx{-1<TkIgnoTLKCV%knl&##EoA@ET|2Rr_b2)8TXGBMf0wV7{F;Re<y_Or=gQm
z9IF53^SE8&1YBtcObi#^Mn1UhdwXKexUvY%tGKme>m%Eh|8DgoyjXs@+8R*0Npc1*
z%F2pQm#2Ne@1^BVdV|drrBqz}r#pcf#GjK;PcD;iO@fGHm?xw(4fEtY4fABslQ2(i
zC+~4uPG2z4>5?22X-+!AL%Fqm@0QJ5_HWs_dza<)+DkSBJaywknkS86M%OIMOA)?M
zR$T9vy-IyYX=6X5`<ox$7Jf>?s6&Iu6cw^D?Anw3pe$c|_UyKzNQANPqno$x-L+ep
zFO(xANx;GDG5Z+(rHl^zxNG~qhk74Q&%?=%J>j@#?{1~cP;+^-hx}*zx5Nv+y){1d
zXj%ZbVkP3^+toJC)vIB0!~`E9A&2_m(Vh=)dvptrmAYX2zDG9i>)9UP;HTP9LdZav
zv^ma(Qd+`CV(t@_`r+-nw(s4sb@Ru1w`|+ovu6j9#Jl$G-Muq3ru3=ZyS6^EV^7F!
z80rwBdq49S6#wr5&r~C+XAs975hw(!tpySF#}$%yGw!(qMbhf{Q-$8n!mHSRwXw8J
zz{>bkS<L0U(g#*ny4~4NWX%6uNsy-f=JPrLWw9&$k<Upmt4eZ=aL83=`!mgzLqp(v
z1@+Ag8R)9o@)dlEmQNsH$-+`Di*zkdF)_RJi78_~sHAbCA>-DGCiLFTJzLLWQ%;uT
z#S#cj*kqzbs*sQ!iqfx1$q<OK)TC^2Tjk29)ygNCR=1FErm*e=bLyHzm8x~`A;|??
z%l(m=GcxWghzAM}cRrt8-liM}tz9rn*Y^fsfiK!@_*Zi!HvSg%xv<$Vmi)eBIMdW6
zFDNl1V^}GND$mkWT00YSk&R_=6J}yhS*n6$?u5yrDUlGhz1u%5x(qFj91G5rPBqR`
zj>WV~I2N~)0>cx51u*qest-v^rXi1{oGDJ$WbVc!OUc}YGM6$Nj7^}#i)CB{a-DJ!
zRVK}08JSi}#A#N%m9R^C#adfI+^5ej_&5t-sUk$5@wZxx?o6z^h|QoGKo^C-7&K7L
zk??B3tRlhIY?RFecp4}Q%f*VX9wM2+H1?E#7w$Mq(uCMIWD&@f<lE5C_#t$_*=&i<
zET*`Y;;OSNn>`N+_lj|-+Pp0FkoU9xD1cM-8A~<ux<a>pS&<%CG^{d%{u&iD7@{;g
z{QJ1VHiJo~c2tcZ^<~{@Ih5TgA#k}<mEIYScZdtF0beAXQkS30*Onvnf-O_Q9sW)o
zxcPJ8@+uvW%5_i}ZN^NAoMgWm!a`G^cC*k^>x%yJL7AfRC<GQDiaS@YVF7G8>;Y|}
z9zW|>a=gj%<g^X@`2?E{`I{}?du4V>yI;{KK;26FTYJ>!QLM2y(L}>cfMv3RM?%5a
zE=V*76t0_Smr&2bT78ipuwaHe3WMNA9LNU-{B{DC2K|Rl`pypjz^K2X=pUGHPK>#3
z^5m%BbkdWbrTosspYA{DJH|ef-g)q($NpP$dSYz|=ziaT-g_6Xc4&g#43LmOW>AIJ
z=^+?8!*e+4?&B_4+4m8fb8&B6G3@U-DYPPWpl^jE9QAkb7m4HUlfoEs%@cR<#2G!&
zZBJ}0`>Q*r{P;V(|DKb++uncgNxyOIN&M-QKif~?WA~~eYrP%r@LebUy;e*(X(W0X
zyr@Qy%3*a(&*D8f;j@@(bRc*}2luOZM<bHF*1c9iFngDO2>-sqy1%69f^w^n8PF~&
zZtVPM7|<%m^m7|11C|1KMFrW&{hmBISLZ|ix&ePDGy4kr=6*`IDh-ASiWSuEKgRsk
z<8h@xI;3)EI{i(Bclo8Xn=2Xn`g~X6Zf^7@H-`M3PNae{(_#hW#YHOsRTX=1Orew@
zJ>0+RjrcTmj!$2H_NUkVI6e)kfz$-?g&V>PMzKOp06N|}ldq7JsMFv2hM##_24T#G
z)C@#Z1GT2lxOD}~8yy?R2r+IzoJ2sf2mB%q^nk70K|gt&L_i`9gK~OS3r-Qy<hmiH
zd*IlIBjmJq1Cf%6+QldPlq(xtZ!Hrt{@&#;cVNJ43%3iut?vh!neAZ^dKK;N6^LMI
zEepD=k~CbcUu`SdI{iw>w+MS9GEuvZ{rZEoHyo5?fU6oEHimOiyT*+sbmQv4)ZWy2
z*yo4McnpN|&DTTaVzJSI%BUk7RhTv%qb2&2SJewTvwJz6*><-LI&0LQW<AneiKSfy
z;c$Xm!TzdQVBnh#fdm?SezyRwD}&J+*Tt0AJ2V3dt$Ic70<eaw4AUpBYg?J8xu@N;
zE~bgTv9j=l?>r`I^nQ$Fu(xgt_r^T-R{LKpME$SI#r`)%?7|1YxDZ3|1wZ4k_^u}T
z>{GIKbH)Td?rTW#05<SvthQAHEVhqh<$K&}P5Yq)mb9KBGtNqdbyr=?PE*ftxbRiR
z!_4m3yDyR?LgZt<<;Iu|9Vv=ngO*yT4{)Z#p^)68%dXr(ZlSsG*A{e66Wvxi0M>P!
z*H#j*uOo>#bO0`<1D*yBaEDo-4T(Czm!KRZ<iW6S&@|&WSRZxwEi}z21{3GD7bQu|
z>hRk-{9ZdzvXM2N;^?$=dx!6_lbPI|-KCGdIjWU>&j>e^m6F)WMK*(rn5rUuOw})n
z=-&c!x^dLsiTKgsf1$%aOivlQ2tK$`V&;wTfN{Tifd8jN)9X+A71^8H{f$N6-Qn-I
z0(hI8!N}XN5HU!n){;#|W9*(E!`^t3B-TKs3j4YlsmGL@iWoCbU?~zk*^O{^ugG5A
z_U6lPIu;6Vr@BLgx}y!u`mt-wem0YF4cYJVw?6yp{B1-61D02KMJ{w-J0iBd1U~MO
zQVRRk6k~BVa6t~m1y6%AxWDbNG9JRsmE#T;5t(rxQ<@|7Ng^~1A~Y!N3y}vFvoP~@
z!%-3`jo3>DFLGVUHEOnhXv%86+F|HGcz2W|ueR?mnGtr90K1^;zA(QTy4J&TdLer+
zg?slY#%9(jv4r#vuxHjt6U}ZJ@qi?+CE+u0%TS65L<p(N2K?p2{#HVi;PM2s3`n-7
z=GGw{{^#{{(chs1lvxJ=13K_M(w*Vw<Kcx!|L~#?1kuy}iZi8Bw7hx!z2TtAoRng8
zUDhiJM;YZVu)+s%e3>9qc}n*S&+2a&oU@$zh28PvwljgsW!>!KVEojGOC|epOt^0Z
zgI{iaz+ZubeK63f!hU@*%!IN@QGOb#Tv*$!j936dtiJKPYGV0!N5f~!Zu^CmXU12U
z_J>)v+&Y1-HGzwDd?oLrFJ7wyULnyKPMKwTfWEY;GU#Wz@8Jo#62}m}q<JHn7$$VO
ze}0N!lJJHR7R}3JyvHcs27N&K5@s5)u$@#*g#FytCA#)rBNcPH{XBG2W|vLaD$;|D
z`eu{pP)~3zjhT?olHJG89`P%R3NKw?B>?!s2}Dd5Q7o5%<ptZ&;TLr?FTq=M_`6lH
zqQ6fE?pzm|bki_9tRTG)_+^54;8@l|$h!T+CFzN%=EHCR#wg^zNdbrihgn~YSYaA%
z>Gl$uGDw)V7YjMZx)eCqG*WnMXlTUGJTBC6ND3(Pf}RDVY_Ifs<;9|Mb{B?rRL{ow
zZ};L#imUaoF)6svy}Xun|M>u+WGW!hw%uQ#(*STMND?oxvODQlTLcn_vn$&J;q~u#
zwKQJFhS?iUVrLK#SP6n7L1_@*=|)mJ;0{x6GFTvLG?9fsNW$MmUDg@oP}1_MBR!&3
zsfVY^YD7I8nmG`Opazi3!q2dY6Ne$TzjdP~6OPIS{58+r<z0RufptSlz(}e-OW)Si
z=k|33)qySh#wibZsZSVhkgeMolUgN~_qP~XoXvDy!H5`+eJ+q|R=-*+SQBOh-e`wk
zkoHRV%DU`XwWRQz{RMu2Y(|lDEIDuu5e%q;Xg0pPJ7HG~(aIrHl(Ph4%K)%)2J|*9
z=4HA-Y7Ze`5+b7Q#=#!!?tw&0T%<Q5!-zVOqg%(XFTO-=9yD}%I|B*Qq`YY?E2Nm^
ztSK6J3d0LY!BlXk{*VIG=Ikl&4;P+eOvEoSDlz78xLQ3DCe3p}lshFWLybdaRb-qk
zaZ(Y+lI(F~=h75OR;vV%XRpnVDFexn>Y-?>h<-~qr#e~J58Az0w(&u}j;Gh{3SYN(
zI{ioOiQ8gjS|?P-UvJ}7%TzdLb<W*6zA$WE2YBq-!~Sa8$BdlhFg)4KNuP{2N5;Hx
z{@49*;n~Um?;n4Az}9$|UvG22or!n$!SH#cr#>WjW=AK((vU?ENUkvY6JPln1L_Go
zGKtOK_vQ+1O$*g0N>||%-{&*@EBnm7<)4Av&%wYm;+KzTHjl3|Q#Yw`;qNJFzm@bj
zGx2t<kh`rYSP&`UKy*QR742)hCX%=s<Q4$$VSNl6A<MY^5IRk<NLq=V6CXgLA``CY
zA}?X}fL=gAC2c`_P}tClAu^U~cJ)U8L1;Ot9jV6$P$3Mr^b4FE@~ema&vSAR`_^Or
zeHMBRriq7I4*5FwaN(JwXD6qSVz>)5s}{<EncB{<UynJ%RLy#_pR5z!Z;PRwzpoer
zMmP)<@ZN6e9q$R8xYOrPh2}?Ns=`S!e8z|c)<^Q2(*cw~2S9Blr;qsh!+zz6?2ju>
z`?Y=k{f8v(D@P+z<Zc}fnPisj^WvALe1%OzK-0BWZjh*N95<5Q@J+&;_3EgvLmOsx
zHgx-5credEuU^wTrWTX-H9azfrzL!&DeHv+f7`%hI@N7QC%fAQ1ELf9{LRN@X2ct?
zrNi&G6D5DW5tM)I6Zm|cd*(p)W>R0NJ?`;wEKl`ze_at&tCL)rW>r!@!%nJ|1xdSd
z?TUU@i+=hm3tu5~<DIgV!@f)8I&?|g>n%zk(P)My#X$4!3bc(DW*YlL;HdDYh8Q*>
za>$|SM^A-QFU5=H!s9CocU}DBw0uJ8quvwfY+p)?@A5ZLJRnd+J>F>P7MGpTdB(RK
z4`-$!b(&F<3W6SD*yw?-H}n!%VO~<S7q)M8Cgv>*W3`I_nT)?M1xLzDG-&<R_>Hm^
z|8&6~>UX-YdXk;x#(-SLyTcM#M~ZVx{CeXYb-|Ao!4eniD?EoIF!B81IxKnq@Ew*x
zR6<S4yx0+<5`2f_?gxkpKLyytx^Lp%yEa2iJYo$#Bw^jxm0wwczIhT6`L*z@!LoiH
zk7BlB2j4x9AG-uSn(_^Z-qsyerqqKSoz>$O&bi&z=fF?cgp6RT5~AkAWA+Xb++qBF
zLKg+MivHpVq)4WGfL5hQt1=IEoc+l>=9ko=9bZc3F*C0;k8x+0&ExRoxcQ1N8b5cK
ztoQ#RllAw&_*6-xco_svo%@&^vHN^=A6Sdk4z)-UZ?*#%Mzv1dZn#@PXLzP{Al68S
zBAY(&LZu@IvEFc9@eSv8#W!4d!-Y4Lt~<P8K7g?Mw9wt~WL(qr_)m|sax#T4Vb~%g
zF|0}g#R=uscHO5%dNHGr&a?iwoe-pd99e50;?WbjQKg-7FwWXTv@8#x1eZI;PEr?Y
zXPy760;?IwR1l|gN$@`?ExsOxJ{)gieB)gZoxafP{w1$w+>#EH=Bf~z2u$YJx(6g;
z358FS#Rhed5QV*gv?>^mR*{zsW-5St9z#W04e~_iQ-e9#<*lkG3Kg;ye;bckLTZeY
zq!Y#Y)Z9f|)UfbLq#lR08{f4(rc}!z#I7FhdQciNvQYK?a9LwV&oPs-75gV6Eu|Hs
zwV$kz0H2yBG$ry<I=diVw>ep~ftZY2ew+7h-?9y;R^)bLh)P`aW1ybOW?Ujg7t04r
zFqNcIa2gS_gaVZl7S8okf|QB0@B-*ecyU}q%jwL%Z$oD;aCcR=0&>w(c&(G{n9OB>
zEyq9{4gzG(q6Gbga;jrD!4k%D#V0j;P!?t|Ba4yx@zr4V_@rN;Wk?<x9Z-?Np`aN0
z=*2U`BC=fgrJ5CXSf(#R+^YJ3EjqT;3Ly_!-|YSiR!5~)1^TF;J^+F{OEeG&ZqJ%N
zcz{J5sET4c2C%7Tg3++3s^{GQejx1TCE}{Y$AmsR73E&wO-l0a4=b<*^<gmz`&|y$
zl6`D?$@W}(aodKM7Ha8iDwgbHd)dtVr?6(nE!1&~vus7DvO!$JQ?X`e{_#bxS*$e2
zygQLD*DA1_EZ2sO($?XEV69N9K%0ft7MI$lWTmyZ8?ZByvzNdmEwqo?@{ll*af@xS
z+37FYg43z7@+>CNGZk8N;(O%jKknz-9tebO5J7_OR^>Vn8Qkqf*4(d`Eyn*lS&V#+
z1#e$#2%7^9nOOb`;##)i`ionLQzz>FOn{B2t~r6bTs&Cac;!V2+sVp^{50WpQTUz|
zLqCq`O&<SnUPwL2)qqP))xo2G$|}0G3`8%-M;#_Y+!(~7!VB`)cG&f2faqE5i`cUe
zF7uX!3J4+j?_hH<L9*_JlXlDBgJ_!rISKkueg-xsA|)Gz=DHJ>CJsn6D<xA3X;)c*
zA>#q!V*?vF!Eo%&CP9&URh3Yov^M!;!a9a;t^{0V?tfO8k|rJY*Rhz3e(`B?xB&yh
z{6?ig>|r*lJWBKS$I>se#=c5e7F+O8Vig->_$%@5TANlVahDngEbOkLzs~j$sUp8O
zA1?o1JwSmzyfQ~E1oM7B2Y<#XKbOsP2K?etd2ZNRs^N(4R2`8+XojCX>Z?FrQLFW+
zGl<|v=pXErSo5^KRjqArMaKzfT8o1iOh;W;A0MFy4O(GcM?7=mfX`vFf@ZZG^NSHK
zP&wE+0j-0eP-KEGfAdkv?O5!vMP3P9NiO%>eJg1l4}0?X>YA8v-H;rT#R#m!s7WFm
zKBz1AZqS9CB<5bM%r8?(Ah6U?iJw$QvIUK)9aE-GwR_I5>K9NBd!{^UyrE5Bstap7
z?FFX5?86?#3Mr?-VIStSk?e{m5krpCTkmW0WbbFItn>b@-RK*Sh8M|IAsFkpS9o9r
zIgO#aC-fCFVB<7b!w&fc;NyV2;T>dylb8IGAvvV48nQ%_BvmE2+T)Wd&FA@HTCzgG
z$k2$E0l&z0ZYGs7I_6R;d`LSXV3ZZuZDWKu)8$w-hkOnbEsW-AQ{WgJ@*x1AbiITA
zzF^)|SH$SkyNIsIR{Z6~(fKhu5F1i{>PY4EZqSNzDe0$^1tKK+Y7!AMiP{x0`Khus
zMzI>Nd0}aMcuQ}YYJ{c~xekmYRhT$W;}fv2B=HG)g!?;oDcmbO6F5PX$Pyj|V@S9Y
zPmPo4bXm@Mu;!$a9WUzVM6x?a+(LL#+E^NsK=48^`26bkE<&hNGEzZkZ!!x<<0kJ1
z3b*Tj^HoD<K)R0q{f>hEe=PZb6d(nLn@s1ANkWUs^QZ*CCNhr9S?{ZkpTVm0gryqU
z;HyR`mlWtQks_8O=YFkB15>JV2m$#Q^ovrRXCaTjkJ?mL90WlCsd@6vD}4!N;%2k2
zht0XLap4Fsd6Il3fhsi~7Hfi};O$>blsq)FUnG?LlQr49TgqNAwm`C6z4t?31GF3O
zxScFJ<QtFsMKB{3GvpUpQD~^72;dgr4f3N<GE4+e*kytT14A(W58R~ghvHh-;%Zv2
z{-K5e0uVwUDEf%^sFAe$JEW<|qC|crYf(|o{V1mG$U@i;E8wEDaHsXq|MpbWQU4M3
z*J_L*3$EYo@wPS%zwBoMqUv|M(4A3U3-?ke*gpZod7gZ?^-$bR;n@@M*+;{(b@xC-
z7a~@JnGwmRx@=F~R6K3pC6NYnRuRc9?r*42Rj1wlJ>_1?g5UW@7Bofil->Mv*|Yyt
zdiG1<S?~TE;!Cah^%Z-Pb{Vr^OrOEgk7}T6a3jNghsnFGlledNbw`8@ylg#*Z$8Gb
zr~P_Y7<tb&p4P3OA|Hlx1b@V;H@I)Yi0I3^Q28HEx-a(1S$gmudJvrC*dCnxS?j?C
z)`OMGD54pC^b<hqY-|t0H!=8OjfA7oQft-;B}JxP%7;DZXSv<*vlw#|VJNtN*}~N4
z@sHiF%_!MgU@h}ZR$J#jA9HeOntX?x9O*Rq*2kj(VuY`%ue%J{FJZ&{7J^RM>5K?w
z2={GsKg&#$$=*G~5Fp7FyD~{y$*w10Guzc>y98)&x^t~NvQh(7IRb+6R<?)J;+t!W
zZ${Z$=UaS>5e`^sw%*1s!5QRTWS2TtVTZrYHh+j8Ls?W5lLRJ7!Q&g<YS6LRWThO7
zjeO6HfL;=Ai$>0{?E+(yKiF;^P=M+%UhIR5RSN4c-b4^A&??|fQb_Hb2S7JMNC0fD
zp#Kr_K}`(!nTPyr(J)Y{Oj>p-WSa-B`u##n@2sGV&exfmpyd(mc%Ed=IJa4g0ji7{
z+M=e4-e&p+NqZnzCjI(S+mRA+yk@}9-w1H4&);KJ0l2w=6=QW;jRpaFfE=bp|L!i;
zZ;lW_ck`C*9LgIA@v|LJY3g!YpX_jJ$dS_FZ=wS_{LR+ss(0vZV6k-oPw}wQ8=({W
z1(<6Z@e2?6^(06=<Y%#otAsVsenNg(?*3uPy9-&^FX}lYNzgHLWneHi3M#g{R4jN1
zDn!#3ZH$FaYzme`S~EDlHS-<*c*;Nf7eiZ=lZsSVfD$0+BzE;bGMdu2U!=Ot9hBXk
zHA@y3mH_Lyan!dSwN?3>`$H}Yt;)Zm|I$_Y(*9ugaDN!+E4u*CES?HP^XUE%FDn9j
zhL=Fi5Rc6o{~h9d_~HWhJ$5{rRU8eEpXp8LajQGZJgQC}|99c>O7{;{Mfk3q2(v)7
zvL_=DHU+Gl6c3mMcb;*^R}TNk*FhaZi|5edDzU}_O=DuO1@MEOf)@iK@eHAbcehgB
z_@7$&NfH3)mx95$P#=S=uUMv9K%mS|;j91z={sQ)(2QjprQW=0ILwFzB{oD4ZSb=m
zl*_(-1Df*?Yfk!4D94kjx$Y&#qT2nCjUlx^DcXnSv8{8zO!Js~e9jlX?5pmR1`F*I
zpP5s577kA2B2<Ab@@naU%&Dk?aXRXR>XgPj=G3f34TyT#infc>BBoGhcv~H~sVqK)
zLDLfj{0TDs<kq4wDGR33Je1mRqL1}rO+_U~$e1cVQjyw&{w$LnV-K>$XSzM0bf&H_
z(8yqh77km@a)o|-C36)k1EvTb!V&;P1%gU=R9HlYKx0<ILCER`H^dFtU<D#fv_Qs?
zDxj3dWoOdLGd7E?UBx?;w%81_L{woKqI}cX;X0u%eEqV+;!p?}{MgvdGwc|LU-U4W
z#9cjuMFh9w#LQQu1Z>sfk@8RlPo?y#zAnE6$=}rVRfi;SU(QDmZ3oWs!Ll#Z=nFt7
z5w8K1-q5X`C`eaGs0Ad+V7b`HnyA6T5r4yI@+<U*wBJ~%X!s{#H-i!dNp8rl7Et4=
z<GvM2L9lcyHYE&dAnDu#usgS8@R;`x`p^h9KkVz<RCskGAYjZ`)~A9_C4&^PX7mf<
z<52<Bu0|N8@z>~~z5ro|eBGkU!fpDyLH_1u%u#{83Vxdz4$%>Xp77owfB(~<nD!w*
z4EZ&@4vTJwgf3NV^ymE*FgEtB$L4J~W-{#^@#{zVX`cY1<VO+|pXgJw0&??Rx^%w~
zJz^1CP90a-{l_8zJb`iJ=)O(@<v#X>kk5>XXB4l~<esX+<J!_*V}b#UEv=ao0IguO
zc+V#N8z!Pb@^Eku`x{UC)kS|>r+;rz!Em_jK627uPwY{rC-b9_ieL~(&qM_0ttUNI
zA=_KSh`#gFFQe8lpi$2MDYgYK2YWCx+cJHGs6WF}TMLj4VKRHaNCHU|ku#BhfD~3s
zSi225XahQPi<uNPKQH(V3xB=nH;g6ze;`e=6<@{<e=b~8k_IW|G4H6PEmOzAOZ<?t
z@<dYOE+=H|IG=eeEiG8p%D8OO^`M4&EaA|jTPDjRb5Y)xl!;>CO3Yr&fHZr?IIj$>
zw#*`yobpg=`r?UFo+nsrn(-sr#1h{PlGg>A$SAQawFgC(;8{C%ZSLK-W2X|7a6ior
z70$y=%MHa1<&WY}mLiHPlAKt!C{C%2tZ?Jfo=lSWsdQ^h$`Eds5>8QGl5mRCm~e`-
zQo<=N^tdIQ;#^%ZCgBuD?($K7q@r#@6~ps1i=TqQ@Xs2NSN;Zs*iu+5WFEX#4XhKw
za|K3s$OueP`z2-zd&h)`pp9yG!-&}i?0p;0qRtYrvh*B}`vG}=R=|lc_?huX-|+Ct
znWx}_=2=2yL90gkAsjdTdllX&7#&7JwqIx!4%>DaLNP`xX&*&Y8XbL|_wRu7uTf6H
z6+FEX6AOpg$I*0p*;Td|0c(vM2DoxEo#;e4RHD;KRucn6OCdqsDN{%cD4r@LneNm8
zFl!^unf-EA!MWaJySl@f+mZN|5jwU(Y`UHLa4~O#BJ8>`HsQI}_EL1Tl#!JZ2RNdN
zb|d(l?YE9@i8gu<9aJ8zrM!1lcyGlf0o3xtBt{(aD+cUh$S#oH>ay!*(jTu1Wrm?C
z2X8}d0>7=qt7LOIi0A=pLF^mA2}2u+RN(2#Vkh;k1Mv+4u6oEKkpRG0hGQj!xRy_^
z;UA&{`$4@s4!6legCWS09|a*qhU(C-hXU$<&{u|=z~>BImmezh;$|wmn*5J?UwD;2
z48kfIE(<?kUOgkj2M#=s{<)8Puch}CF_foU>X8f0SZOdi25^w;N3k@A->Qfaqj5~@
zs+iJ&;~9|U%z&!CGv1vhJmfY8^U3UIGBbU_&C9-zEVVS^a=HegnX{!hWCxH#nKOl(
zc~fZkbsTR-bh^t|(re}oqgjIcSuhoSXKH2@uggZJotXRO1FPF8A-*g0MGLu%hyA<y
zmGY%<FuP=C2m$9JY)?raayFAai}XABFT!g-r+#%G!KbEc#?k?lLYkHPS;=ghL;lX^
z(p1Jdr&Pvyljs=Mya0>Ned`mJ1GC=!F5bna0l$D5AS3&70v@R-i8U+~7gJST*VnL6
zt@pW2${}0HT4K8vTP7AK*&4PKdd6}O*E?;xjrk3O5>^TQ9hM&tyK;Q)H{)}E%X4Vv
zs&xy4g`wP|!^ri>eq;o|v9hrJ;u>tqE^qd27IZe38)mwa#lUs>%{m;6(OoYS<?xv7
zWqAKg*Xr==)m7*S1Il(&SHzzRP6b_qpu)_H9;<w2*k)D}6=-o(vyCOJF6z`TGVsXZ
zn`c|0ei0wcUd+dTsc!G^kLW-epKyiAi#}e~#hSCAY%DuCWp5?T5R$p#l4`R{nzi^y
zfq}q}S#%YEn10`L#2?TvS7GqM-+f#Qv9sT^=_6}2yL@Jd-=r7&P4MS~)qFs^WUsPE
zPA3n9S@8jU*s2if5QpsV#yR3v<K4h7(C0zul6yx(gsuT0yo(mzC6bJ#61obhpn~=;
z$&*wBvmqRA)q%khQRJ@RumFUmNOEOA7X21oDQffm;r7mO*sTMLTBCwHKu!?c<Hjs7
z>xP?Fg6m1^U+YLN&a75gV4bR&y}nrv9AZA1o>#y_=s!EZs$XG2Km``F6j$N2=<o{?
zb%hN*(K#;1J!}X-=p}n()}HbUnR`QGc1-4&$cpdCR@TT7BPZMni=!0aS22lkqWgT<
zTu3GWJLH&b#kVH236%uADKx3Py^x_P6?IGPKYQZTi%0sGi#=O+?oJZYMFEy^NFBMH
zr;c1kDUnpUol2^lC;nYdql}1KIF)cYFG;3|yQySaCe-q#M6slNB(qeojZ#`7zh1bD
zmlw<AS3WFJltU`6hVyXK#8qyT$*EkGBuhOTQ<-uaB}>jql4X3{BumbNWcZ;ggC$Ej
zvW&NpA&gZD@iEGPp2?N(vt{rLwhYeD6%+Kp(li*O{*)&qoWf~0bw$0sD=pR7&Y4#@
z>7>c@zu2!SIwD+KIMoG2UL|VS#bO|m_cVQ;*t1<)lqOFCiyO0En8fLNVd|%=A}*K<
zKssnqmh${kUb=Gi{g9!NPewg0T^u~fIaRY7gk#y_;BIMg=-Ie9IDIo}SBky(oEFSq
zph|&qfKR|@YjC=Cdk}s2E-~1$YZe%#25@VbbtTWtld3U?-vA~I`^Bex(@V-oQR6-!
z2pg#aBYx?h>4<E_AD(A<z3I6RkmZ9P-n#XJrF`5sUv=G8*L;w<wX=8I_MaK{RjOZ7
zvx{0rCHiCbr;;^l;_@ozGBKWmXo-}aFc6blOp-MLIZUT2=LwS$8%k&G<co%hoi3U(
zCc~TmQ!<%vtzgaE#unxXqVq}kk0K`?6PSxb7i@*2{F6=pw@t{Jp8h-bvo=Z*VPkAd
zNo>UQ{5Mut#z(~X(tPn;Bz%O^3l_50tYrS*o<W~hG%=b7=@4wrKMlvsRy=cVlD~S#
zo}U@weCbxvIBWU1%kjqZi=q14!C&s(6Y{K|U!zE<I%Aa3eNHcmtn>WaPu5dTq>85O
z=i)Vr#PZGjRxjCd01r!vd!rl}6o=1hPXBl0Ab=owGNIr?tTD``EVHtVVEh9jidxag
zKWxUWf@<fB7$}F)#A`6{Vc+3eoS+h@m>nG$uNcmk4=e(|HL5&DNOJXtlRQ=j0uT_p
zuo)<MZVlNk$QGBwQib4!U1rF$v2Z;;vrqcAr*+@lYqIc=Li<Ho83`Cha?|$1zpF^(
z%uzhuvN~c^A|Qi$sj>!F3tJta56KP%%Q6pe(O<7CY+^d#k;8_Sy}8*pK8-b!t(4iH
z4O;|8F>`fBAG{uziSdnXNc}BHi`XuTLREnx41aOk*S?`(4NPempK4WhOwk;SFnlRL
zK+|bj4!bW680rsK{n{;(9lzPE%CdbDbHWgiOOK8xrx|~nk8p`a9h(n*MRpmCT(}W)
zeT7#?F?`G_{5{<fEVPKGS7X8f>O?jt{Z)F5!n67?M)ea3gh*C)jA%HKiT1)<nZqO9
zt<Ia>t^Tb87^N*NEm4=Hqar#b^qO^LF$8w9J5cCDa)AK~xC77_O&d@-_~M&~W$hta
zWo~#=N-5nQ<3E)g7^o=S$?dFrh^Pqtjw9VI#5--z^2cH3)BCQn!)^ke)TJd5&2mpF
zZdGLfJD5Ws0Fz||v04L%<99xaCA6IgbL+w!0Wi$s%LWzmP1iD9m<5~Y5rDocu_tfv
zH}S|J;Xj$B+7c*-HJKsHF**B5AVj(!rWnyYG?a|2j8NV&zpELG%TW&Sv0#!uLFP2Z
z3~hlq&Evu1sWHP&#rJ1vONDgU>M{FkO<{{AshF8QF`IE&cU<<fd`IC`jUnr1$e`49
zKqE1|VhEfi3tU=G1ND7HgR$7&HXDCu=+5l=CR{=`1qU=W8p&)mM7|=vT>GNU01M%*
zX3q!tMP5~R)fF+2_VW(l+b~ccNe0TzKgs<-H?$j_dOv?y&oadUb%TUubPJ?@iKz?0
zgonWZ23BhpR4PG)2%Sh;{ko#6hO@ktba^<8$T9SSdIaQw^&cYyj^;({M&+xz)7O}H
zs;HEH1q`j4$o;Vynt+zD=SqDsPE*PX-)Dw0xdC1-WK@WH!a~_$W=>Y@!tjXUHV+9U
z(l!zs4pckN&^*|5+tDqv5myryV8}-9cwE!Az|$p77f!a2^CRp#dD_ne7YnHpDsJLp
zeyyJ{Dt0bD--7NmY2*j!AK8k3gn^vHzB4V2oMVfqi??)^3}<xg>Z`6=jlB-#@Zl|6
z<0c%_63RJko~ev-adJ8MfIVBa`&4SzIl2yc<~KYkMW6$)GUNy_xL~8q4tgN2+at<{
z2|*X7&l_eQ+!HK>OoXBr7A6unzo^jDy2;5B*s+NNJOF4f&}d`tEZaaV42!fu#94Uu
zPDcjfI&k;<R270fDF+Ck!Y5z>RwMUhLPS~JxI7}4$>To>yFYRdM{-jUD-;`M4!uMe
zogyeQ_`Yn{oi{K%WGjAcdbO8X#NKv`(~do|S(@o~dSQ=W*y&m>(?No=@ycB+&i`gc
zSCWAvzct*CtguF@&XF_lt<K;A9f9R4<V4wxO?E>nMb?2Lt=Ea1uyzMGd2+4whXlz=
z<^&1S*fjFJTLg1u5rcHK?A1s`NLGkq-~<2-AO{9jgG=Bhsu_M?sz9}fNsum7Cq9qj
zq4O(|#Sl>Lw+p}`7=|Ga+BK7e<vP?KH6ar3Gj4jtgYyJYLyB7gXaa(S0A%gT2^Fxz
z@$xJ1q=<2nqj;9CP=PqKp(!F)06-Rk;N=Y5%q<+Q0iBOP%o#OV-03gp?4}NXD+lfi
zu|g{3C7o=nvqm^hVL^a*@{^Dud?9oh`PRpFS+ygISrm+?6x5-1BfbHL&>*4g=mNqN
zHnUwq5LD=tao319JT<2u#p>#20R1-DdAC;-tf9jsYBbLV%L-`90i`ei3AMbzXr>gt
z8HynY5EZ02Q`nHZPes)1zEmQk*rNN6GF?=?VNurI%79#5B!Uht=zb-4&a+hr!>1X7
z*vuBbOHg_t?9ggMEP-Xl0f5~f+G`RogFS~+WOve2@`_DY({HI*jOdF3rRl#xKS9kS
z_?gKmZJ5c&$hAtIR#8aRhcz2#NkMJT{%WRK=$xyNK*?rE_zt~*l&wG;Fc51MsGmpb
zrI%<*;f^EZvY`pxx<A8dk8LziVCZZl1=oW|Eu)6~Xm2&TKY5Bvb@=Bq>TxN^KqPoe
zJpi6u2M|!U<CWd(3%M4PdmtGa(GK!Q2u3m60KO5aEtFa7_?qAs687n)T4i{qU6igh
znUsD=D(7W~q+ZgqvkiVlN1~p=MClCro%eJy5>8CTp$iBnq=QtNCW2`nC>rcz^P-8m
z593hER{WP~=64C1-vm*2$DT*G$`R7DPkV<>GsS3a8*6;tvGvh-zjs?aN%`cC58H34
z40~`BZ1THeldp>viBN%@YS01tsciA2tTIcRu4UHHQN|PiO`<~%LJ{xE_Tk)<a9d7b
zh_f7aG9ob0phW>l>xI4_vP1BV<SqLad!AV#x5Rfr>XBmuO93k#dQSS*KB9ZM^<sMF
znq_~myV&){uu-UQoj5iaD{O&*=^*=#WjX~1)GHQ{d)Ze<guHl<cyGP~3PY?nbO&<|
z7N5e}pmm>C8_1T@B;1xk__~Zj&7uJ$<>mF*{EVw98VRh$e7_8)p=^K>_;1jY2mC!c
zB)o(`6m9!wl;*UF*-fa{=T@p&3UAuAJHci8_QD#buAbwp`r|I&f{}j=t$B27NwH?d
zY~K3lu4!sB<#?iUl^PPZZ+FjQLBEbv3fH2}toLn);~?69;@!}!wd^bWl8n-Iq?}1a
zxJAQf1n0ZTmSS(J?aq><0B;8%3dRyabDr{7fY?PWfV6<AFbE(9^5(+hz)VLZZV(KM
z<hIJ~#Ntho1Z0kq(J^<%7s%Mq(FJ+x*5?U_r5J=Jq@(Z`P%rWZ7CtBlUq{<-EDoIU
zt=MO=uMhinGr}$DSNt{_LK}NDJfK+hI;0TC{)D23*?WyjCV0(*31yk()&zy3%S0rJ
z?={4;t~eou29mjycX^2|G_Vg!<zNF$(o7*%0Tq5-27lZI1Z`uUZXNNnPD_mASL!|s
zl^^PMG%2F?_|S1*HH;2HP|;z$DL^NY1Bs+NB}Hb@sC)ugHRoY;KY|S!mkLDtlw1aU
z3+&{$6U@kRzZ7IgwREd62CT3-M}_L$!;&4@v4=WkzlNAveOx^i&QWt1lm(PdtAx_G
zs9nX|L#6dCwRy;fK7$B2z|&Ml8zMO=Fa?9&fS^Spw!BKTzFWQmUIieJ#T8P{rYCd_
zbRPj)%te;c&;T9*f{X&vkX_d-TPs`W0bLF*2ITuADwoa&nM^NYImRS2M>Vo&OuCof
zurTB7;b*hofZGngo2_`gK;U|l3duC185~9sgSsZ8t~-;~5zEOvYLj=&u{hc*hWw4R
zpPsN^XPAYXXAo=YEcLpAAegH&x~cv_h4JMNs94*bFFVMo)`Jd}g)dp`1J~?+P)%9_
zB;tb;o~^CSUOh9Kmi8oEA0b_tueE8!=Sgx6ZeOR*>4XhG>`ro1KahRcpvK1d-fxU=
z`*|4OqdR)G;#8hW-be7$BRh6&fAd9NLMQjsu~K9CZyQqTp`L9*K?JrrA;%JG6b|t%
zdp``pXS_Mzv71wLtZ3xInVdprIp+b=G=+x~|GGVbmwEq|o&3O6;%yJlGbW)#?7R_@
z$oxt{RG|9GK#S$x_Hs;OgytqlU9vCf$poTElw&CcH!^iJ2FmNri)9c+KAd{nRngSj
zo?;VuB487(jugOAu6Pb*(mhutXbBgI37gXhE#a($-;IwO<}sdc-Lg}?#Z_RYtq;LW
zuTdiKFN%fbI*kCF<gbwgHz>kj(K?lo#L5>HYtU|PD0bz@7d{a;HnTiy=9VOdp*;2S
zkV1FNj08EkfTBlase;hr;Di#wsPoY5XT+gU*70{Lu1xd-nm!d}*NiFq$hfi<SD%Ak
z)@MJLZ67#{t^ip+eAtOU5$Z*js49#^=WSIz9fk?WcHM&UsNN8HYbK#pdHRXgszvM>
z$QLi9%*tV2XA>9_bzm)&5<;I@k8}a9pb%NG;Ira#iisjj=DgJ$Gp<Mih$!sTLjNn$
zJnUTOTVX4ckApH}<O@H*sQ_0(W}1zat0=?eHPjIXhy^IzT0tJ3ako}>_#5ojY~(TC
zT2*8pVyuZsMC|S{Sh!2<OuAP{EAZO++tQ>iC;g&zGMZts)xzf>IoXO$=ds_s4b0_j
zP0ulP++gZ7sc|f&V(UkHdLNxS^(m#`5YmK#Gpgkj9O{;$$~o6h2?dAjms4=abcupb
z*hHa>f{WDe+5sDac=ELp1rKEO&vrsaN%z{y;$wSw(*8gvNl8>s_&tl_c~-%@EK-m4
zV7twMqR`ClbTg2gFmN^>KaJJ2cF+W&2dH$m;;-NCxjHSiOaQp1QQ&4<Ohpt%A`wxL
zR-%Z4u#$=>oTnlR4<{lDw-ebTJQ0Kv$|wmXOyhJ)Gw#Wh=K1m|&Ad&gbezM<l#Vh=
zB9xpXLnJSjO=&)yPH9y%2qo0*;vs+~lVh19u4Hs9h1T=UN4M|lWf5@}md>{yW$Cc1
z6<TWWluK8sCTk1al6XM#a^Q*xyt9t=B_{$un9)C`G(m9@*8`A+V+A1r^{W{MMkpZ9
z<~nW5MpPdaf*DR3cXNbF8(whGfO(G0;Q+YU1eOfH7zEHnNk`0cXkmKGnSK<uTMY%U
zx9Tlc0yaEB`zRs*qOT$EB`zP=b5c&HBJ$5Z%!zk^5ZWL+Xl}jC1G)Qr6EWiV61GST
zCmO0b{iMp$2(>UdDvVawd2JeBo4vXfrBq?WiW=rMvG`nJ?I`$yK0_laOg{J&(eBV3
zSI{r!G6b+Cjgg|Np*4VuaE&Z6&m1is^CM0Xwc4~|T!ZR;0y$;)We1qVS_v)yKNIiq
zUE*<T%_hp=@eN5IHgaDZXK$^6zI8hIzjC$7G|THq7)8JhV7HJFY699*`NtZMNdh3w
z7O)uaVNk%QlRGA4R~=qLyh{AamMmtaA@Og^Mt=o=G58ejz><oMM{R(%BID%{Yy)QN
z2D(eTB2yLu0yQwn27(+K%#F4)5(DWg49Ea5P~(wB2@(Z^AzIA{RkN)j6~|R7CoVcR
z)@iFL=WUcr>p8<#Q1dl<1DOUP4RgXgGQnXtvHF7itpA!sT(cffrzjTIoe?N>(w}PG
z<5V~%R%R>cP~jT6r<u<3S83XlDvew`8mapdOA(Kx!9pik+1ZL5f6rxBo)&<%ufCAj
zyNiI2msyr$@5;Dr7I;(o9^JBI+PVx63{0U++l57xc*sPjR?4f5nUvVdmOXnm@7b|S
zrUgpax25N!;cR!$p51s2%Me_xkHdOi$)Mw4(1jwI9|`gSq?XhQN(}+^28^XO<(|Mu
zs)ZMcAc$QYJdgoQqiA3OQPpi~95h*cB!5_sSK^7%`=}(95H#7AAs+X@9u~u7<Q->A
zTVBUpjecb;NeMO0Sp|hu5kva3KAU6V{(Bg8wt~R@=|%k5b=UrMT+tI3aVk_zd!&B~
ztN05~u!>ii0Ga6{Z)dysG%NFTVuH^PldC2(f)QK+9r%4no~%VqqMa^wWABCOvl9k*
zZD8%N^q26JNJgpa81^ehfICTQT4yq3)@@B?pm~n{Qgi+69f1_2?8mYfK|CmZaVTBM
zE3n#Mtpj;v5K5PmWMn1fX=iY`%d;*;6FE{pBVs(^tItT@6ZAbK+Ww@`7n5i<Vh_o^
z&iAmp<&>KFbm8L?koY9_8i{sMG{9_+W8*S}l{~xtLT|J+9Z5!PuN;vxa7{6?LLgBo
zrO>7q6ge?#lYl{2k<Vn%-;2S=k{DMXD*V8Gh&C=$rSD0+^j8cDDK2YY@LY#*|6e(e
z-in>`&0E^19oG|dR^xTklxI@PQ&LQWvRQioT7kJcr-Vv!jj|Y#<k|2=Y#AILXXr)^
zpg(W`SK|3(^+8Jp`cWh1icE}Jpv=;u5?mAfQHN>gWeQ<mW!^vzKv5$MXGFRROOPiB
zY+48w6p$z7BD|lL#(<58^^R<TzZ5JRx^Lx?v=%Q(-4OD`_9d`nQDzpJhd7h1_@(LP
zbtxHt#h#Du!)LNPrbnE{V2^P~rB<BJ9b#eq4}fHsk;Ve+0ctpg4)cgt4;?1U7jVv5
zL@X)tifFTAmgkO~<G32o-sL)nv$$ZXApw>63<pDn!Mnt<@LZ3`qHznG29efJ>`z~k
zZyK+?T`G6p)Rid)nRQ=1khr!<0`^B0gIK9t9oo42+yOuoPGO764b~`S+|F{^kij-q
zH>ZUF&DfQM>o}sOt4WwwqDzR}d3bVwK=1<8AW|P-7SItAuAvj)9Ew{(S?~xn#efA-
zLx414GblVOFdG!3y2BuE;O-hbhp`K_V<<{vKg@(S_;gHH1~MFr2lzO97}Ce%`0Xb=
zt_`&Cx*Zc*2AGR5$(Y1CB%yGBq59~PiMgTfX%SD*?reRK*CW(SnILI_kmWTdCNWy|
zs;)v8A%SY7fhVAp&`|<h0nGsQt9E+|Yp}Yw)(-cV=GPKH&OPg7FTbO&GkbMQXTRc5
zYmh;r{IS?f92=(z<oOBYTR_T<_wRh{e_G#;4B<F_qKoG!6z-c)xSY&-8}UTqVr0z_
z`fL20O{!U(SO(b~O$Z_)a9N#@HzaH9bVO<!_ACVU_I8O3R2J4~{m9#%(;rV7yGn~M
zZA4Ycp$w3dlSG?{=p%knpB5KLE7lj8wIMge`(o{tSYew4a)%_G5F~uCR0B$jBvS1@
zf|lZ-4Q5<7IpTL{Qnunc{+`Pc7!6cgdLG>zJb3S}0FXy#WY>L)o>-9S?CMfN@T2;p
z|GIVg*8Xj@azZhb)NMA8>upv4i}S7O9lLw39cPuBI`8N^6drqyRX#Df(fD=!(B5q!
zBeLlhaz=%H)EI~;1u-zG2aNO71BQ_*@qlqV@qmRVf(Hz_VKS!|k6fVBi%MLeA9t+N
ztK5&Px&^0KD#rZDFEX{S54MCM^70l?#!;>xz{1`|Oiq`@?Gx~=C5D(!2$wkq*oytM
zf;xeS;@)Mk2CS&$5ipSm`z$_U%Te6#Qch8j8G!f9*)$6)qcK*@jhP=gHqOi`|LQXb
z!hSCqcEkB&HbKKW2`MqQN({Hp^kWH78S!37+InY^{p~aEL`Bh-`ITlXeC>kP&HwT%
zW$NG$_-SQl-nx70*y4Ge#c?$xEA4G|7W1_d{^8=C#czvEU#tnYpU>X>X;$!m!lsY&
z6vJ2Q<pWGSBfGp^s)jk<@Eqd{Y{R?Q;r0$XqA9Vyt<zg&FOe%mzJRYOnh)V~Ib3-O
z4<Wi%viRWhq>M0Dd>uaH`?S?w?Nh#fldmO>%mYNI;WMaKYT9}Sz?%g>=eQ!+mLL^Z
zc4coSnK3>;qQQrilp~yj$*vcuYt~T--0X|ZU!@LTiVxCc<{W+s?Q|PmoQm^IT6&Hq
zn)B7-Dp5ybtCZz9zd^F|Oay@|pn=(n4?+{qFBH6KYH{fhCvS~mPp~qMBM;*)&%tJe
z{yJAi!IbHO9hI|c?}zp6Ksr)>%7UAm<DQ4h!T`=oIxd{$P6f`S#B!<ISO?zzhkG90
zu`@{>`WDDa2_Y*fW1`>iB0Pmql>}l-Sr?GK&7`DVJGMTu-7>D4udxgg6G+r|e+3ft
zOOPn`h(>zX9&v1b4felu5l|d+(YFVQWR?SBO~?{M*6y5C2jCYk$-aX5gS~fVo#hc_
zyyqcy54wUUR`8GHp^KA;g9qZtl1JlZ0a5E9a<wOvPp1#@#+|H?U&0YYZxL$l->^4Z
zOW|&QVKZia&^`?}7WS)729E&_Qzd-{I;V=}9xxxKAa0eqG#ROOlX6o~H*}PMvS@No
z=(GH)VsU}64FTIf6KO#%E<iPb+Ch4+EA*CsO8AuYQ>4$=C7+VpG<=HfOi8m;CuxdJ
z%k3+00Pg_#U|QiT8CTUoxdAoHNhQ4lWhcYC@_WVGca&}$v3v$GGF!3gJj7CoS>80M
zoIrx!8b!Nwly@9$9C!H^NM&4#)1Hn=Jso4H-o+8EG!74PSBk^qViMxXoQ}APt$Q~2
zY!{j4LGErwB-~rN+P|fAVbBhq3e>Ol-$DI82lZ3lyXuz=OLf>F6vOs+guiC=R62+}
z(Ltaq*pH=Jn?Dfzg~<ibRXE9m6N7j@g_WbHsJ+}++Cbk;?NVMacCr+)zzj2dKU=1v
zndvktZwPM6&d_hU!}=)_yCi`P7-6A($Ne?K{x;k;xQa2l0NTg2V-^>DIWkaU%|->p
z&>hSzN{eT7Dug`LK}hmAln9+eMH8JZIb5YZlHUx^5Co`}06m^LY1?nGr)j>})u&1+
zJTEO#p#hRhg|K@8-4DFrK6>U0B9D3U%Y`;ds%5hU+NUl$MpMu^`AY?ZV#;64QZfnc
zAAH%ftv6XBs{4r{BuWgOQZDSqA4?mJ(PoBrDH{5PoDJBy#2KhstDNIaY_-g97`X~x
zu^&)`F>_)1COQp1rZ7S5Q5fp&oL=LS93<&`>?TA*sUm9hDOswlW*gvZj()Fm?<+d`
zHs{DFf-M|Iqfiog@AHIU(EVgh!4}Pc1FM|DUm^x5iSM03UdB&X=+!=UF%e&ln+3C>
zvLS_@GR(;w*Z8~=1=f;^+d2tGAs;%o>VKqhOFyARacKYQU}7$Gz$+fQTNBK%L59@f
zBMRTc<ky7P0z|00R~%+-hpWeBfa{PVH3%sE&s%N@OWRaWt3an}*JsU*0C^Q$^I3mI
zVq2G)JTPEM{Dsr%F{(%h28%m$qx`b<fLEG0g{j=ZNYFFIKHD3Khj<ioU<T+WB`p+y
zb0zg=z6})CYL@X&yi<M^#!KysZI4%cST_?~6wt)-$a)|H0%oF5<(~F6rZy>yO9;Tk
z_Fqtf^SRo9$*dr3Zj>kCl;FFpviuNnw#;fKQ+`xQML0(jLi4!_8wg$v*64_~!)CZ?
z6cdg?=bTBzoRg?PS29;D+|lCo)hS(Ok^v@3Feej{4r6IBd#@xCmnn3J@y}l05<8Nd
z>+}vjSsb{?CanHC?MEE9*NK^2>X09pO5Lh6PawAln%Xe{(P1;=<-CKp$`ZVQzvYBy
zmI2>1#4U4ornZpgRX)_t?v4EAjiK0z@LkZmbu!&nJANjuC5bEPRiQg^k|}}|@0cP#
z-3tL4jetYsDjh->Q+ZYzVY#$U#$u=mwPU?#;nD%K35~Ub`cs~0{MJej#E0BtG}Zi0
zh36nd+?_L|B}@lX9);20<c18*hB%7IiGX2-ChEZvHcOv@B7s`a*^Ok0(R&(ek|+XC
zz03#_r4jJU6k!J=HvWasq4olgfe_UrbjHOFbr!JBVw{^4vHiFwLWo`<m>E?UANx$;
zG;9dEiWSG`i$FcgOhWu~dqMtM)}MdUt~9kol0mu@yDO7;dL&JdGMy=15GFpRN@L+&
zI$*%#W=sDN*gpCmVo~j`QQ+2Tt=>jr#$f_j*yBbwgEkV-UQtX(+rseNrbG7nCds<&
zeyY*RVoBhD^v+(^)sS8g2Q;V^1wTK`5-7OeI-r`ef@lpP=I&b+`uILz(m8AtS`u-3
zD~YaQe?bs1!Y~fc#$)m{JZK1K_fbL6+d9k?_!Cp^|KvQTz-f7PN)t6!?A`KMDFk*J
zI4~YK@D?Q2F;Z#}E5Gpt#7a<rbry^u5eVTdZb6l1P6)ne_MvZsQbRD<Kny~J96=T{
ztst=;!dgcmOMN6^H9iw~OW-qs=hPlyr**BqdEKJ*Yw^V&BH9bWGY=XCQHQ-C0<g_^
z9x_DkHq!U1Xxs(4Vn1tL0*%OkA{4|LYYVRk2sAhQNV}?i%@4&baEg=00M>#HQ_SAN
zCX6jn6aXOzJ!IXoVR55catGHG9e&U~yCaHckK(hKBMJ@KYU!eNAdevSRF#ZgqD?8z
zf_<aG1<>M|WHE4xEs#h9+v1I3#AxF7zksCloUcEn{Mmd}GA#fP_I2i(08;n^@4&Mf
z*+x&^eY-%mR*GkCBWNqJ<q3Z+IUOKygJc{dbsIDfmW*`Gt-@MZg)xS9wOqbbk~^!R
zsP4e1c}8NHwSeAA8nGb(i?p$Y8@bSo_X1)xK`_mru$&~FMZb_V+G=>RN1ShY{;2pQ
zfgIsg3SF*oib>XZBV3)OyVwT~%mzFgererWcUW^vpbU)$O!v4)rWG?rr|8rqq9F^1
z#HZ&1$Yci49Cf7xXK5Dd1RmGh$oXZXn+_^7Qk}w1X~UYzi`gESc>_PdE!_$7qRZ?R
z8_Zr&KW(o#KQLkn?G++$7H>aovbba>i_|`m<~}=zZ6a`v1%q&oKLyyK%@Z+O#=L~4
zwJUu-VpL6s>D-DXV=d+jYmA<ga8o)u#C#}*?|=Ec@#*-DP=S?qO#8N?B}3S1I)exY
zF9>1lC^8W19J|+IiHwo#h`}O0AxkEEv7h%#zKL(a<E$hR&r(617gb#`EW@M1@me8e
zL^%@d20eyW2YP5^5fV?F9x2|e@{my&p(vr@^PuFjC8R<iAGh1~%E_2P2coXnm*V|K
z>39wXjOsyQZJ3}@mIphP6cXk|uaK|Nl!75clT``hjs^Q%c`N7#_He-dpzoK}3w1-v
zSW-=~r?N{Wn}ANktw`@930uPhRi#s<;4*Xso1zX-Xw9av{c(-D1<n=@^cl9L*$?W;
z`h%kSyl#(lgb-7dao|L5H^wVL3DN0!lJ@5c&styVy>3&BWD>LBPs>JEIuB_!E+8RA
z6OiW0{xEKXp%UfwRO5(fWZt3s(PZgkYCHQspjqTmO{xxSiC_gn+^FvFMEf=#tq6*I
zh<b&e=eR#+<_3+tN;^iJZ>&ZX`9Q7@ax*DHBd|k0QZE6Aj=R=;A{r~he#)q0+;NpT
zNKv$@TY8Ruc|F@7qXV<?v!y#lKH*)^SX#E77I}L?)k5bxHla=?bg`VNip2_(;da!c
zC}OiBK`w6AvA+$KenWq4Ler(QLp?0!x$pxo6CftAjd4C{$)YzC{K`b&ae0OrzHqyh
z%uYjwF>M0^379jye9om1hysNvOD-Fi<~zCyuPRSgES26wXwbY3C09|W^9`AmiO7*-
zxatc}Vz+u+{Z07p;*B!S;Lyo;ZZxrvG14%KkkB$*=ub;lse%%QoHDhCiJ!6Bv1N-^
z0Ns%gE`-ZiG5N8pmD*&}gwBGx@;WFTmJFo|8;V_#8H<sR$%EL$=aHGT%#O$)M6Pq2
zzzl<SiBZQ8`fKQ1#LN?Zo(W)tQ$sA!79dl#8!_~f*$nHYd;dwdP!>yWTirS%O?r#e
zS=nc_-RuSRd?fL7CS6M4aj=(ALJkQ%W`8pgQgH^@Qy^<h{Fyv3lO7_D8*CB%jI}`#
z^7IJ{kD1CG$lj9#`p{`st{D^N*US0UI4w+Ga$#~h5xii7!T&TiPWUa@63*)VN<~RY
zkQd_W3gYDb-$tB#1937>-mAJk`Jpgmnw%&R0=K%>H8->#+0B7$iKC(}GQ?s!z*^7#
zM`*%425E+aK`oI>$cT|aXmn4I&-+2hU#}i*IVMVmbQa~p23%?=*6^bm9++@5Pi3ID
z&^YKLV1B-ejYH9fI8It6Ld9%=!IYU3qLG`_lA=VEs!80)tL9Y;>D&=>;(ip64t~O`
z0;=DnySM=lL<MD7f&~=wX+7gH&VZ}Lbeub7n}J~nrY{hS6<(Qf^E*sFmCLK)fk>6s
zi5`6|!9L(QQ{00wevH!UA+sPf{*bm~H^A_qGil9yPnpUS35H$9NDRU+c#TYU!z~ab
zG6g~okwTx}%&COkof6F8kCR1x6L*e3<geN!3&*WMGi(zd6mzyu;^EeV(!Lo*!Md>;
zL?I7@I`A+PS6VeJ>{jKr6-ldZs4(i+Evva$65~T*dG}s*!zymrR%Y5PP02%eH%JQ-
z1EoI5JdW^)Fc<{G$AZ{ksq!13^T|}$pG*bq85H`<e1x$JEO#abpU}oQcCvAhNfW2k
z^%#c8mB|K4CIu>mMw|}X9X==mbUy-L+Nt3ZXID~#$MlN)vQ5nC>P=X_CCzID3ovW$
z-xPYx%q=lB2G(s{4*l8|%N$JXMi6Rf4{fk{2O3Vi8jzfB;<i#bxkLP6>n{Fcl&`Pc
z;Byb?-0oxqv{w@Ax=Q(<Z5^-^FIrNf8epCZfp_*B^I@qhQk`;!!5X=V(-MCN!mv4o
zm;x%COSuH8g7S%wb4F^UL?Vj<4izIu3_JeHi9@PVYw;mP<KT+IKY*gN`j9-7VG3QZ
zr#k$VI>=yWflaDpc4Z3-i5X#$ip;t=%a(;FS=RE=Fc{tTBxuASEH|+V8c`{cm=`iP
znoykDM_;no=Y~;Fnfw3^;!Q|IUD0jpaHK8aL)fC`@b2|ReIV&owORB*iy!)6O=rI9
ziuu7SwHyfJp(CulOj9H&H*$c!#Ift}Z)KF0m*4Z$GpNy>PPuF)+F{xwn~u>+Xc;sG
z5@|vV(g|}4P^ND>?C0S#V?3aUrbjb?&9tn|$SISRv9fg=)GVe#^?;R;83_8~xCvq2
zn@R*&xoB{&QQTzHL-|$$#jp%SI8%9?A&TRCwXP1yH^`Jy&6$D83zpV3rJIZtkL1IE
zR!T`k*P_;V<Bc+jlwvN1(A%`5I!n!+F7a3PKLYJ&ErK*JF=OXLPceRrE?}i)4pad{
zhtd*ZX0<R~y%@j<bOn_|*oRk826c@3%PpZTOTxiM4%=y;C*Bo%B-T{4I}s`<B%WEj
znHTDU*zy);7eKWAejyai9-(SXPpAN{K(;Ytel-H;Xr_YX^<jztf8%!?X^PlyqoMQp
zR~J?#`7`(p0G!O~P}F(Q63(=1l6#SmJfq8uQK)E43Dw}fj=L;S_c<6wEj=;bNcw;@
zK0(o6p*PaK+4zj?3+^XR6`pyT8F`R_WJ=aBB@>#N=d(oOid|vmmY0BX6H;h&P1?5-
zzvV_Kd+em*hO0Eln$xzGj&gNCCDDP2ssp?+9PEmMGInXnqpBGmh}`wrm$EZ7*?~F$
zbD>EV>>~)xtPS!YGZxCc>1K%PB{_YKZst(!jEf%(%M-O`qlSOpCRygCro#|J*XA`B
za3UfiFg@sMGi2){?HI!Nu>r6gC*Tnu9P<=$M|sAOs#tG1Z1|`QjZh60#PlP7GNZ3@
zahsPFPyAyZb+K(dhtH!NvNzV*UM#Ig%7i{(IAav_J-Ac8&;2c1kJPx|WNcwI8WMFK
z5Flx$Oup=|yS6w5m`lv(E7@;{#vJySZIFLn=Qz2I++mNWpTP?$>m+Iw0vDcVR3)BR
z(yir*N8v4=qf$!grxcx;y@&JK2hZMq7(}ST0+eYRxdjLgc2X*gO>@FLSI+{KU__uQ
zIJX(Jx(B0lQ~q16TQ#B2#|;(z%gkdk=)L1MSg4w)!KP|TE>vbQbW0==b2t1PP~mLF
zw7dC|W~i~uz}xp-I~{g1<tpMN?&imTh?e&nS{_p$Ix`b8gb<qPLvz_@fz06WSRYuf
zq01yQWP!k!ng;NllBET0r`X3WiSBwK6f(;SDZeijC<p^GLl=6}FC`C23f2B1+QUr5
ziXFOEaKI%k9TS-XcQ5o0N;WDk%7>wCP#ah}JQ}eHW)1{Nf9-rGC@~f?0%3Rpjt4!K
zfUXF%L=g?o(!9JPT(B5|^UBf6yn6^7QVj}RLW9jNY#<(*5k7>hmpS2U?iJ|@wL<Cy
zZY}&FXf?JO9xxUraT74Pl#`rH&N|{KL1(S)`=nHj{3fOAp)n{$ls*#%M4Pyv;CZK{
zn9yR%4mwjSGJ~iTeXL#=ma+U=9odA64Qx;q(NBUABF-b|kVDvpNm_Rp4&-qZP+DFM
z{4v~`V;z(kaMw^&LA)pS8V6V)DR^>Xv^NQA1cy=_a1-h@Jj{@drel*IL>WmISc4c8
z=F<vF69>jbCybwsC!nQ<7m$wt2E;SUR`>6hRE@Jrh|#exAr7XG0!W~GD4I>D6vu@4
zm;>vD1HxqT4l^lN!;Zrznbszk1dRr{*mnPUAyLIaj%o&5F2#U~WNTav9b+az8YKZ{
z!OP5+lXm9W`vA!;dv{A>j~v@7vrL?lz`%;3){=`c6wrFQO@Im2Ey%RYa72r6ZdxpR
zQt(aWZzk@dLkRqZ-V;H4Bps4|L1eW9f3kSsbqFoupc1$#sh2Cs%N!)uCyzu$Vm(5V
z0E6spAjZfHMEs^6%m~RGt$nIIy(_`;gX+`Ei#B~Uw24NKV2&n8<9HbeUv$ERJ(VPb
zTC8}80)IRXd@bcxcOn<}BPTFyr~uY>COYysGZNzh6I7Fw`Gy5v&MCke1~+v(i^^4z
z?~2z?jgz1WaKmzrYQ>xoCzp#*A?T>cVFZ}bv<E6gAuI~&FUgKNJf9d2VjfMFWwZ#{
zh)_AxND)IMiBY+<Y@#Yuwj4N=ss*0u*B`2ACD5a~q&FmJm}K#N1G4?U(?GUMY<uq6
zzH|H5=^fWDq4hZhkCdfK{*iOG^N}nhxh|-Q5(BemW1*K7#L6PE6jmXY=PIq6XfI>2
zas^#ms{<QFc0X;~l;s^eYu5E)2gRhqHar7b(KF?q7jJANHgps0tv@M0n*D62(!%5L
z63cW4$!nl8(60tl7xmX@5qB^yK!KowR0u+?E!m(^G8D+RmHldnEFhbYDjS#ubzY+1
zwC!+Cx8+<TzAf@g*+(%*!Y-hXGZYZQXM!0eG2U558=1-MCkUoMZy=3LFQsxc&Bzi-
z`c(eOV7v<kUdX(xhydZJC^|J-EOt38ubi(*Ogi~4EM?Z#1u6h}O9za*;gHsbnw8s!
zY+K4JD8#y1g`i*4ETQ@9G@JzSbqV%YdM{d%$cJ1#ME9Y3ngbJY2D;B*>mb)7Q*i?U
z%(Se9DS^2o*U^W4EK_*ZKq~}VNQ_}?A~hc6`)c6GfYJG|u+lBht9eLDM9N9a8wx;W
zw;!vTniQi0i;jYc4m4SX*Wg=7h>PeXzE7f({Q9tog+k`oW+?q0($i9kVZXaErN!U}
zVh<WZVVG+yq6NO!WnRX|o25feL)I>>4k=gHbT;C**~@s*jzwM=8$<V@S{T7UqJ7Rs
z6qZ=`v}d0$Xo#f&U9&#Wh8KMPjGu3~Be2NzKzFfg4f<s;1_Wz@zlcyV1quT$wpz#w
zSq4_}7bOFoz`ac9uc!?MS6;NZm>C^rN5wiuXd7F&Q6d2%kbyb43SRQ_yW;z|cHl2i
zP!ZpliG>=%qHnO)p)nZwsz)JJkaDyic!X`TrVo9rNJO;AHA+X`?7Ri{4bq=TN`^q7
zoEo(q49=5c;2`{F(kKrZ$qZ@ZAj!M}WP>WU46?<WRR<|F&`%m@b}}?d>E`z0VDQ_e
z?}K2m_}@)N^;&>w??aUB@+)Lj=eGxCbrqz-f}o`XD3S@8-0by;(|B^Ar!Wwlf7QqQ
zEQ^_|?&x=`KwUt81wH97`l#BzD5qk6NF9TkJE~3#4>TX40KSRy25w5PL#-J;_BO^4
z%+@;mrCm+9o0$qo(n#^Bq*8uCw{YjMZ^+)=EJe0-BrwOII6N)|Px~KfuYueBP4rVy
zpyawk^31fd=QHt7#CdlNq0`VD4B@z4w6|-G0%xja{%25Wi1aY&J&HP4EdkdsCbRI<
zoDur!I`gElmn#0}xk`F1#f2e4l{w)>|8YhICMt6^J%Z&GzfW7YrYl_|!NOgK%py*w
zCpZ;r;nM8e6wD>od&Ye}j#E8`JwRS2sv+-ArZ4!@aA*?0S@icD@=Ms1+8popO;Cz@
z4CAm4hoVp;f0($X?nMZB;Wo(~sIj>0+U{46(F}TAq84C2%dK0u**CIp`#@Y+L?n`t
zcdfn)FK<zh73+p~0Hf30jM&Ofg%ix_mvy?40iT0;U>Qk3aPe`2UPg;Hb3NZ>a+vR<
zGp#Bu8r0V-3(s&+uUv!YvqAgXG6`DM;gnma2)h;l1ZcgOTKG#2J~@y4Wrjn)jCFjR
zTDCFUkxUrAPDsp5WQf~YUaUB3jW`Edouy#01lDAvEPb2)(BTk!|JHZVUUM!%df4rP
zFB#enPpZDG18!IORh0n|Pa$TAI%YVCc$O+*4*_e*BquY{e4{!fP$W8!I?ZK_k-`S$
zACe1;76BV%CCjZyq$j2g8Ar4`XeZlc;g>=loPqi*M-<R4&AaTn7T<<2N-fp<EK`dK
zWP&$Z{&lV9AS!ZSjbg}AtFPdIPm~Y|^`M+oEKF2bT^r1S+tiAw%`DWc2{?b^-awr(
zXe`uO5`nLx4h-sp8g~{D;UbVDaDz9{xs<>c%wUIej2X}}LM?gREEq9=4Mjs(pfGeM
z6~MB`B4i{RUsu}?`nFBJ=4DX>dV#5?Wb;_yAYOy!!^2H2?_3w6+ad;-ccJMR%b+`0
z2$xYHvNrQfp%Z2+q~bH={b3IAQ6>}A5#Ke1A}li+7~SYy28TMRH1jt5`6tvsR;~%l
z)G^Ew^F`vp@Au0Qux)|k7{7wKW#NZ5uWr<%QI#RcCR|0C+e}b>{w{91L;mtk#gVL`
zVwMksn$Xv?81%w!5hJVf<q$4f)I3B_QX@jRv2lt35uX`38=lEK{0s#1r}YCQ!z>bE
z18Ju8DzlwpSAxPrkg!|KJRxq!Ig93&4u4P4-&OS2V|TI6fod=t=iAEWE6e&d=F0|s
z+X?lOQ95Xknq|7dN+#B2<_RK9l8{jdLu;3b{Y~n2Ua`!f%n-f8XTt%dL6{OoWf{4I
zXd$uXjA=7tnl#g0ep0Prw(z$-yAG{s2#*d{V?uyn3M{wkp(8J{^c-BAXQ1OimYPm*
z&O)<IyGcb(D3buWMkhN1AGWmsu|Tw-5GWv>g5#M1ppO`UFn?;aOQ~KJ!Um{AsCZ02
zj@&^n%~gChEjBA+NOVFI&0T)T&&OqWz|S^}wcK*(96Wha8V!Er)zphsa@`Al)(c7{
z3sJd&urE4j&@U$v2_?mvxDbyglZ)CR@|^US(ZfT24uPI(_cm6CBLqk8V3=H3TaY>}
ztS-?!TEZ$t&Ip8(C~xR1mT~KijR6n^y|3Qn8=jV1m1VI=Bu5Yh)*v$!THgZpmFZv%
z8=F_N_9&<Lc8XeLav0Nu*dyi?Jc5K#e0`M_#S#WEtn{e*!Itz4!-<II%wna9&xLwp
zQse=w08}x{u1fl*D%}V@T*j(^PVs%sC~W5lLCaAqS#G?{CAYCHE){R5_p1Bc`!OY3
z9Db8y#V|FL+9h*;AolJ_`f2t3ejQUY{?h61(*w*4<`B#Uh4=bSV`r$n%nJP&;$s<J
z)B6qgvJ4_HV6z2W061GZ0Fq9Z!&a;V0udE?A|{ruRXJd+bs&EZ2cprnJW$<nQS$)H
zj29Wu5HqHvy)aO6NHlxw^l(|8U@ifu;2X>+o?f}ZFQqp(NJVCv(vh;HQjsQ1{F3CT
zKP<*F?p1HpKKBKf98?9*OQ-P^_c7_>Oyjx`&S0xM%Q{xgLOluIRy`qF4Yp@6b&YJ?
zNTLZQH;8@0D%xPWfk89=3yo&6TE}o|35%_42B4`i&rATf(vYIR5prO32*d`{kB$iZ
zfxUe58cA%&jc=$Y;b>q?v}kJsVT6lvo9xQjbp*t)oJoDiUjzmW1H_1HS};ZK4`;H&
z0OX>08pTkUO@)abu2?R3p6cA6KiPp4&m45$$1q^HKll`qIG@Y`2#C8TX(bW|!IUn%
zY$-7s73!z!mh9CttpCZ9B+8pzIYaD~!sXxR#6aaxX1iDC{=;Lm*?pH!vMpD>=x${r
zF02<J3SkaGJSv5>0%RlL5wm5%BC83?fq4PHgaR`yfCdny4QFQ%m=MrUD4fhJi<l-L
zxztFkHXLwMiLuc*lR*32-=VYAxqo|ruAS*V0@@_zkUpt(Tz8Dwc#0=-5>2BGNST_e
z2M4rn!pwy*TxskV@sw2$4i0+GD4Ka+@Dxcgu=d2#uk;y1C{Wr*Lf(TUJmyZJ-($+?
zC8{#>qFd9LJtClZNFB>9wE~V79z-Prdy2fs41tRylZA6?FvB6Iu~e?KlqeGVRhd`B
ztIz>V=t5Y75wXy?RANhhMP{vXHEi*TZPDZiP!+9+oX|TBmMT<9Jia>dB!9^6oT(fs
z+@(Fm7#rSV;=@~@hIG^%7+K-&Ky(pD^ztF~0Hk6bfuClTV~JF=2{qFa&?VR&?XyZ%
z*j<);RF2vbIbTfprxh|NVW>u1yM}!%{**oRvK4cu5$>1N%OKm+?%ru9!`tg*7-M{T
zxaZMQ%BBl}xKFS|edcB?QNKbqr}?lTC>LQQ^=>xMZwQQ8DTt;)JVSnB6_dY~bJjHs
z6D<dm0sI-#ioi@LmC2qgP8R)=5s|uPC(6qz253#P59l3qS(F??h4x(!dC7x9QZjkW
zOo&iIY(c2VCS`@&q86hm7(r0t8T3pv9NX7R)FTjV>B<r!px=hwjVbFQ9}8Y$2u&c(
z3xI#)OEH<J`hiGQgtVY}{4K1JJp|cG<QdPmG!=Ni^cD{0iGi$gg(R>{hd~o_5eTrq
zBVx=xC4~<b4bKK(AyL#e2)nZ1--2>cl=jUB5F&Z_Itri-D|CpUd%l6WtwTgzay{Ex
zI%qbP)5mx=GHP+?Y^T3P2P_!yVA!$pjj*f1(SE**0CISszn=q6TjBYLafCrbN*PdC
zA#gbc0xl_O>8r=36B{W_#+EcVRM4yeh*|n}%7u6X<(6t9{6wAR+OZF8@@$64s1p`S
zvO)b85;;&t1mc?#5nF@Ah7>?YE&Z{0q&QP}<r*ChfhSQ_^A84XK1iX+i`E4}3dJi%
zrI@3zIoR964gPM-dw9QyL&Yqh<XDWZj0&<{!pA62^OMHX0c064Hig-;=4D2#Hv}N?
zRk1)Y`9!dxq`*<px8Z(BMT8}w3z_z8bp@Nk9u~}MtbR0v{zd1&7%R~;2z(6$b5T2{
zI&%%~P1uOeF%r>YHXY?HE*NTZGBEI<kFX2yTb?<nBs0nYZ;}@l%EHGrAtE%|<WA&^
zFanZam=`A0g!#qvU<+}Y%7~WChnN%VWx=8xqzTk8PFgk7s1(AYVA$-Y#dKX`shbuu
zpO5;5_ago{+Jis8+I@((wFe$abFH5dZ4YZX(V4X)GT<Six4xhP5%OfFp-nCH0)2nk
z5osI}zB~LKq2f1%gQ<*+1JaA>9Y_!1F$OBAanKs3i|XAal0i9FcPP6Q_ve}}igG~1
z%wA?1nr+k$z!%(awyW8rxV72F^mK_rLc@1$9tW@zlawK@7LGiwx^%}*e5Ot0{h^mE
zt|Q>OAuG&UMymzwT_Um8JZU|lWEi}piLlxXs*O^MS&n7Fkn6K)Sc<%sO!UjUrDZZP
zd1)D5O9{sBrZqB}Rx<-pY3KvW&ABcuE>L0?x_I5N)M<n$rfA;Hg&Lv^61_?>4YWii
zT_TvE0|>5Ad8T1r7HnIXR8k+ObUIvGH?}Oxh6Th3l46)0nZdLT3eChq!=zN)fS}Z@
zgyVX<GP}N90<5kiya(oCC@7F&lDQS6OAVp?^_@s`G}DX;*p86mnG&m*H4r=NS|$+$
zly5_@YEHXvBWg#%uF^Kvo;NMnU2?&$r}v?~)5z2*N2X3)@Zto??nfJt?35OR1qL9I
zWCtv>OvoB2paCh00b<ODl(PUavBBk_7p%`dkf4}RWzK^;>IO`YGbIz?6xxg`w-lNn
z+yep}W*zo~ZVsdr=?03B)wOJEvKL^;#(D&gGizSs;1Pe>un3vND|iCGAcjx~gauk(
zbzEQIvsfjX<bi@4^DegxYsQw_1ghAts<$Oof(|ud4Q)`Sc3NUbsxEE6sLLf3P6$E$
z3Ar+HdMrLB3lfsRwYXN0HZa+pk&EUwGfv)yRKpHe+@~#l@LH&<B?_o@Poil@yH^^4
zVvHAWhh+=&5bD>xzYl%Y{Xs<s^bz|Ekqvab`}ItR<u$axa7)Y}m?)|=b!>!2H;_t|
z-W^V~>fi>7N_7(?b%u<rxCBv(82|x!6mJ7NP>d-Oh3qG0Yak^bf;SRL?TZ?4J=ubh
z5f()$^jhk-<&ivJul{5(6|;+-dMb=D)`RdNVNsFy7%4bAsy`(PM51^R%8E7<huwkU
zMjF=eJE*q~Atup1pJ0I+tUiEbt4|sF$Q~jegr3Dn6$+4%F)1L3f~5j#D4;XjNQ(R4
zHz46OC%E+R63Y`joe}A0H;jD(Cn&rdPVhRMV8I(AoutwLX(B}5OD2jIZpWG%1x7?g
zXf>j=!u9qASVe@|aT&dL2DV5pInKcwC5PiWNqA<)7m(e&Z-~_H8uS1zF`SyC4(S)a
zE1=?b6bIZ~6YtJaP9S7t?V@u84+wJXtq_H*dkC8=CrIeE?)zAW8_g1kj0-)iry^l1
zU85riv!Ww~o`m)whbmr6h-l3F*)>?lqZkfv427B!u)#0JpNXLo)CIv;Ll2_S!7RnD
z#2tAF;{b#cNgeAd%!`ghC4$+YwxMTp9}RZCu`~7=%nzyTO86ni#6-Fn)IQoG^?;GV
z_4Ek#)liG5^%4>W5x*SG4r>7}S#vNEuu!LjvJidj2&>_ic$^q2QutaPTI}s8lhh74
zM!W5^coiBk<`+H!lK{f~fYfBH09bGF@$om@l%a;!@Yhm9g~DlZ)KhL()eQWIzJ*1n
zNuCo50y4DH`b2uhA$BHsEq2}F4R#{VxrI`WplxET<|_yz_$JZaqD0?m68*HP_R`bw
z-kxcJ{_Qo@jtM&(W4C=%rrOpIK*s+ZGOpB}g$GzjNQ{AIXmLZg`v@s#$zi!N8&!37
z-z-sf)MzXh2x~kBC16>v(rXwQ!`nb=2n#i*XEoxWO0uw1wj9SqXR<aqK_PW{`9(3o
zie{L#6LFE-*k+(8_4*MCf@72{ngD~3viLa$nOpTLZo-9Vj=Jdgg9bu3fmk$<!5XsA
zAW)C&6&CGEm=hbbci?Z9hZ0l|#0~QjS_BG>jAMxSG?+5fjJ{w-#SVK|HW)+KvxO6%
zwX_JTpbGSLI7Hzb^ar0oYK6F0>+6NJ_YZ9};{-n&MUIB!7}`THl7-Q(R`ig3YnLC4
zf!M*ImljIV?Cb`S#$tz^h!i9Aiv?I)q;vWlG*EVI$-oSSu~r0Qh&ffJYU)k7g`uwy
zTI?avYB3z@D(x-b_W*AGP5kRVgWt@3>67r9qwZR96^*gX>_i9@-8U<WuD$4BOEvC~
z%#vd9Va*{EOtiN}Fp6dgmOs=GbT#wpVtXg@jP8MT8?FuB1^`3xXQ+hQ9+vqPG(x2{
zh)x8|Pw;Q)Y!<=KEQ*HYE5n4V#e`3FyZH`hrhZ~8hlwi$vL00>$Dn4fZ&wlGRd|*8
zi`5St{aA=09s|B)ii)Amt1t~^EB<ymzUWdLh_q$iw0-DpwGY8T$~I{U$*MlF6`pWS
z#<M*G3yKwq1wkvx7Q?TYZ1q>ui{X+k1`^jQ_G@}EO!;CMBTuFIfx|)=)<Sp*;b>g`
zc%ghq5N>KCo@m?4Jjow__=57s2O}sl4jdK83@!>BlJIsgZRl=rWsH!`<@w^tYKaGy
zl{iVhcrmzIxMl$zeAr)?eWXo>$7T3dVchI5kFbTS6u}17&TN}f5s?TeO^Ug}uF{n8
zY)OwigJfop2w8&*5$SKTy95YKd=?!yBpF9_N8rE-gklOeNB+Q3!wFIwci_U6uxh~y
zF@H)FM9QN=r+foqqgoHjj9===N)P-St1`A){C?M}??J4I>03krUVeE|kIByomH^N+
z%p1!o&zdM|P<DwVj97fD?JyqeH#}xvzOu=_(%Ju_BrNL2aB@PCZT&;YMa{$XtQUq>
zdvMbx<WMjMw1ALxY|xb?BR2Kc>WV;k+M2?T$Y~_TMU1E&)+ba+eXyA>x4z|DwmAw?
z9lkGbar=ltjDO{*3a5u03VO6nbIN#C#zgm&he#MY1$0%?FG$#-UlgfH!_5<nq$D#c
zo<Vc>9}>(J696$6)|Y9o)I9HNj|#7V^c7yFSQFw>q22-^;(HUv08Ic`7kl(EgBcVA
zM$5SxfRGLc9o}3){k%h%*5KQupi>`1_WMGd6zS|xYq8%B<K@(jF-y$&G2=Kgn=YBo
zj5ji2WJ_OSE3s_FJpNADsdW9FU8{TcZhgn>x|i+@8g{dOsJG{d%{@D}Z{PDKsDJs!
z*|}u1wGZxwtg)Z<470f}Vil8f`-i@nhzr|bkzU2;pqb<zFawg4AYi7i9~z(oK%NY7
zN|<M6cDHBH`!MmYQSRHza0~I9SKRP5axj$NKz|d!(S(UlAVy>>zA@RTrM<9PyQRK!
z$FS6niJPn2Zspte?%lOJ0IoDzTX*j6+0IDQGm~%cnr;Bgc=qnv!6h%Fp_Fa=niR?1
z@(F-<Lzg>u@>1!8+qUly7rT2lZ{5?&d3<im&MkX|1ViBK-O7(Uc5uNi(rik*vv*sv
zC#y<)m@QhvgMn{;We*eV+we`2yO1Z*;6)t~@WV98Lhh8!j7$&MUw1K6=E5hGA0+M;
ziUwQB6<I>`7k&DejJ-J4A~lNelo<J9R1D~Xo`sI;5I6lqk24D=Oco}F`suO1nhqJ`
ziARiT?4NA@B{MD^zjqA%n7Z9X!+hDcb<0+^u6=lCZ_guv1eH&!3!0~8bCdbXwxeN|
zh1v4b$CxcwWk7SV)AlLv$OX$7;`~!AfIH|N2UvYUtObNw;FX!fMnJx51mxfF_fnAk
zN9l+iySD$YI1@_CAU!j}T)H|7c@udt#~ynhKfI+EYLRS6f3Y)1dg}K5TXr&cAZ$q~
zoR(9;xCcEXtY_aAQ8|7;3ps?Ym6Jm#n=S)6<RT@9@wtQ?lE$t?4#9+%k;C|8B!@g0
zCiu;Jnc&|t8><rCn5+43jPh)qjPjJaw4C#m?pjAr-6DT`w-B~IO$LD0#x4#_h^zuV
z+s(woTqqxl@ehV^jQkM3m(C&1Q+~*pCv=9}$u~I-qp(e*aG^};=U_^egv>=aTTEJn
zj2_sBJC<|!5SIetLmtH_sx3nLa#>IIf4~euxOs>#vmZ2n&q|v@ckJH0b>Hs2aewzv
z*}HqF?5(DF0)H@JE97cnYsW|rGp8*1(M5b^+xV}1_JY5%%BJhG$)@W&WhRyuQ2DY-
zge+Q?PAbmRNyWrWCKb0eN0W(FMp(xDvb91}?iBa36<^@*SqJ|e*KzEEC8-F4cVVRe
z;T^lS89lvtV23(7q40EPIc<p2X`s_wB;&zIr6fDPl923kNU-tA@e*uqAM5W%U~Y2z
zjL0*CX`$)?i+ST5>OlB9dQz3!E6^+{SmUDqA2#lr&o%Dn?8SH9q_Dx+v14mVG~BUQ
zJAgADHf-BJyk+YXo5MZU%$p_R<uiiu3}o^%8m6@xCZ#rdmH^x}5Mk$56`sKga|$9|
zE2scL!6>(G2yNqzliaL!_Y`xy<sPvJvZ|Bz(xS4LHleiu!8Y))z4x7p@Zy&b*qfUe
zZ}}lTfHlyLvrZ~5FVpw`v-dV|R+ZPi|2cb~b7s#g12YKf7)L`Cbrg)mkcK2A8Fd&&
z91Q87w%h^%6e8dhMjaIu2UIk+1tpDb=?!i9r2bpl(EFze@?y}MhBT%nt!Zg5ZEQ<g
zdQ0!6h$%_A?f?5*&wlpabLKF-YE1(lJ#+Ti>v>;q&sytQkBRng84BEW>L~ETx8^Ad
zn=;~2VD_Tr%VsZIa3}lA1#ujJmMy`DlW%A}ugx%5zGl}xCV%Rj-8=VF1NWWn_ks>m
zw74V#>(OJjtYgSN3M%CBCC|~SLeb+e=P7iCm>&hk=r-VpzXihseF;CjodPxCEs3S#
zAm|+A{yU#<2R}c*(O5d~bfwLryFtDAi<TuR3IFpp99evg_XOVPQohUZ(hDq4q*q+T
zORv-4aE!grX^+)}PL=R{kKyDQIF1Q5^9Kuaezhg^45Kevl2G#8no4=6DX!O@RB;sz
zE?C;T?EdRMk%Qa8lY`!TE+QfzKXvNVpa7}x(`x<nm$|%uUZdx~j-SUHS-tWj#4E2G
z_sNgn_K7J|q(*__>BG3Ympe|UX<ayX>HNiSB@a!IE#{{lKVzxwac>CCDK5D1?z`_=
zj<`>DyT`S@+GmAf0}M5Mnn0AA)h2GA<)RN_`|;R}kP8ae5Ahes>}ZQ|>TeTC5<~vh
zBWPI!riAwrRI0eZu<J>wSfjzIE<?|oheFRpKBY5y?_9sb%2Fr8&3(mia7QH^OzQa&
zGeY0pvtTLu920X6MYcyVCR$7I7TBF<^uhN|b&D^%Gx;uRqK_9j8Gwp-xzqssVp0rT
zMh@jHA$aO~{&4HIjL$*%fIF~@LDKf&V6l!GD^{3TiRg=*bKqiy60Q_;{gpTj$gPSX
zF-pjbTm{Z;B{)yGUqY=URbB9;5~jRczr|5o{l&>@4okRVldx;!nkzklThLs_vO?gM
zeZucLrZcBOZtYMcamGp}*4kNj&YL%D>7u)rzxUb&i|?2<@wywXyM9(|_i~Gg8o0Fg
z4z~qh?>u+eoo)x<)btGxur4>`i$V1F#VT$i#Pv5#2T(^J)7cNA$8md-VdKK1oH-;6
zjeIok=4dy;WEV2r%cd#tm@F(;zEEsEBA@oiX~k<e3`@Qq4y=-0!s4E<waj{i#Qj)!
zKWSVvm6(g=UgntiMF>G^csD6IIBUpq;yY{#Zz7%$7c#47nMj7~8a4SPg6YO*F0)BR
zhP^E+pNtZ3@fzLJJ8$9KGl|c2tGH(ctN31Rn{=)^|CkxzZ$ohja$kT`4AP6=a^`u~
zTJp(I`;6BkrInaU&d$g>sJc`)PQQ&ifdSrYm@(U3wqWjj$Jz(!$1G)H_rfj`vwq}!
zVv4cvi4~qFZ=>OBVuk0s-^K|7aCiZVL~M}fH{T_`W`%LA8=q88#Bg3m8A3mfA<GT&
z$ArnJC?`PmixkBohEnPmcPRHx)<31l9qdD9C5Ar>G`<#aiZ1dYz=O0>Bnnle2&N>C
zJd^Q)C=0?vFdi4bVzClQD8sjn?<k;Q5J?SoN)9BlcM8IujIh#Pp8#o>ky?K4a-5FB
z)fjU<uEA@BH6Bf3`+!p?csNr7Q=$>a^?URhLIsW?%Z-QQ9|pbJ@(Sa5*G}YFKKiin
z%3rjF9n#zU!?J+quAeCbbIZDH!IHT>v(4okuYJ6rOm@PD_?~bomfW)&_p@^^$A(>x
zG_V>c#nxzXuF8{r<0Crmlt)7_tKHKS4sx%a64lvm;M`5Y*$IbJrnPjYD~O7UJJH@n
zKIBvcmzeRg)W@uy!!1IF=G2IPq>+R=S;*A=3V)9UthS)BI2p7f-KiyiIhVIh<_+98
zW9Go&VHexVshESK&}9MPR7zx7iTKhq9cwXL*sHK8=fRTAkC5yhS<rBFjZTxZD<D5H
zyM=2UvyXGBkxF&g<92#FIh_#4s&En>&R;`_0~fN7<f3=ZfFm_XFhc6V+81#o%p@)@
z9A}OM?Q(y`n8kfV;o}br2A;cqrYP)~#XU<MqnLdMEWk;MbIUE}tORw&=CPZ7q}U3&
zusoy{wC%wcZGrB8OBU#4G=1)7^z3-gP>QJu>12VH%w5dNBpXCxLEHwhGV|~Z-D#vl
zGxSYbqO0@84-u-|$nmY}uM|t<K_YmT9OFBS*NDg0cA5ab%y|3@LoHdVnVi*zY|zA<
z-8`QRACg|D1X6*=yA{cVl9ut<%4?AbS|qBMrmRb%?(<#s_*XF#_SzXUo^1tXDzmnJ
zA3znS$lsj|Z+Vm@{~*`wp_mgYh;F?aX03#i@akd8sDXZc5wF_Fj>eyl5JrBaSpAfO
ztT8@RM;|CQ?3UH%5;9T4)D_Qa>bDs0?er$d{RSN$q<$yU{8pI*&+llLX8k@V*c^DY
zfsTb+_bpr08%NCk=x%Ap_d^n=xTRIF?I~|+Er(jCzXU_EwwNeKcAEtab3N20g$9L*
z6A2`6<mkZTI@D6WslCCZ<po2r-gk;nI~lVT(k)mvcee5P*>^5j`d(9wPd~`T<1wtp
z@wNG@Sj5Zo#iEk&n8fPmRgk-CD8p{dI%m&Ky>M$(&r3N}mCjqcaK*WQJl%dfqHt>0
z)akfXru*NgPUBc`H>ni(p}Tu3sVe#J)~SGXb#<B7u9Y4Jxpn^)7B6Ap8A&NgpZs1)
zZaU#KJ62y#OT)~paaKwqOB0C~?^M0Sj0LFQ`wU@zprFH>nX6gvui<jLI^;sNe36TG
zK4vy2V&_K$oAMVHBa%zLsDzaq2I7u}_zM{_?H7({vjgH)VNFw0v9?+63^qGQ-3LD7
z9bApdhwddSD(ofS72WqD*RtAwZy2VIqBlWq1j2KW*j%)95dq{ngEI~-P=|WY!qojX
zYgXruDS={{iC9?nIL^kEqG9^&q_K9HTK)8nyY9NULYS4C@iW*Rd6f?8M+r={@TEQe
z1*p2H#|~+mf%gQs&L%y<_1GZmaUIibRy!n`I^EmX4A|RKu=lRn^EfIK@AMP>litNP
zW-w5JXY^|6g5FQvqaB9(?!Ht$I=Y~DA%1peJXjXzUs^P8N&GE25K2zHdwLfwjvHUH
zV5vVS)6+A%XVFr*yJ)L-?()0bx4W0e^HS@HbpPWJ=`RJ!w84$T-8i>*7prg=)`VZr
z5kb6a^&2F<?A8TR@4Hp^>a>z>gZvQDKN?g%+?nUHR!&o1LV6=k!xUZ!CP1h=IK#D>
z44e-r^_(&=A)rH&8tBiX`rx)E`xD==7zShNi|zU)zQb=j``PGT-Ffp}%c*H6y~8oc
zb@H=~hSXhxd`|M9XLFw{S6k_b<^L(>r`gp#q(=gTB<#gw7*dYl!e=NP_zb!KBo<<k
zv4$_RQ0H00eQ$G49=tE4Pmg2EPfK!nBL5+x{((e#`n+In!T^?vr4TS;RPBW9mZzZK
z$4P2l_`$SdGv~3DAu=SrBL`aTTr7{!6`mh622LrCzEyr5%zGqVQO;Y^rI0p}Ji1&t
z1%;C2*gloB7P)$f3qatW1Um@lZk6WN?Bcau#rN~4wVwcm58=GNha_r~_)eA-j8Yt~
zq=<}+LD&l$Q4eIK;<k#$n?<9;)FQck2qEAi8-i_gp^$31jv&ZOdAyQZujel=aixY)
z9vBj@>HMZ0a}Rst{AhT}xl&ZbF86N@ZBr$kR{}Ir>2R5qiYkejb%r<zcRpS@+%4s=
zsR<vn-F4}_nt;rBdwIdoY68M_$)e?FqT&7!@`<zI3~z;MF!ASLEr-zG+4$9ltJq*e
zWgq5xnCL@qM)%=^=q={oFr)JrBcDS<i_$ZXBRQ{JFS-}aI}OTo`l%zG*>}ua+PnBv
z_2>*)c#G!%O%;vWMM<%uSzY#>r)i%)wJ22$@s>_{vR#-LYtu^-rJSE){TQuT;0ttC
zlkbTI&rP-+BXRO~pNQoBc-2YzUL;{LL1aXA74fLWUlqFLUF}b^UkGx~3{5BF7WJGb
zm2<Zb&Dpl;^vz%yN_poYf0i`QW}BIADIGTV{XE#b8<tPT6gF_A&(#?-%fqc;BI#6Q
zy0a?}ENctdbA{e$cvE$e8#?EWrg^&0Q5NV=nVm}K#}<zFmvR{n=a)zUOB^IOB9H~>
zh)9K3cFkg(kbw(!I2OPy8g_Zi)oKJ~&b5V?d!&--Ch5sZK1486m9C2=Jqu3+aTe(7
zuwd3mMP^p4WU8(YCfxh|n2Y^qBh}J1D&Z$CMMPaCB@#DHUe1*<ghz2V7)kv4eZq%0
zkq=oQ`OU(txFl443_2R+aVJ+U*Gx?4)O9%5+sz$hRJ@QYchPC_@(^iiF{aE7A)|cK
zRWi?WHL2RdvZV~^<eVJIfY9n2UewiJlx^5u92Q<grz{(w<tXB=RCez6Om13TC-Fk|
zlK|JTHrTN?SocX-FbRe1W?&|oyEt_L3Uy2}82336eLkJ%s>hTRpCWWusU`_oph;3P
zR%o(#1#`*kE2wSzfX}MvcZ10z)0(Vtsq9LfU#X_6T}@Y8P1(;A_s;4ho?nwfLL%R9
zb}R84u7S}!hirvLa4F6kaukr|(Jca>7#=h0z^afiX~0rgz9cLTJ2j9IoF3qE7WP!w
zHwR6b@QJbIyF$+Lk%jZ0gzW5ks<<zd9gqG{k^d|pNJvD9L4)JlaVuPKLOx*<Lq^kt
zA?#*`?P6D>8%|2xi)vTeTy7UTHg+1Vv1VlPQam=}FuJqL0w#~peKx~%&WyL)k17!|
z=NXialvJb1<dFZKn_fUpG8i*u>dM2#{B5?w8pbt0+GCQrq$(IQ-2ELp`0tfSK<(BF
zgi1fDP;)ZwR~}IFF2!1d<oIWx-73Uq1L>8xNRl5I2sJbY<C~R!OnJJ8u}`)8UYMkz
zI?iyCjw?haV$@Z-rr>+*Lq}~lz4ax#Jnt9J%i~NKy$_&&tL(zcLwsHuS4^p&8hVoL
zoD<7E8xhOjL@Y;dLVUNHe0!Xu2p=N(E_aA<y(`q%X}^=uO!sqML@=0cx@5<uJbc4~
zwox#P2-@P3P;SQ%3(*a;@PS4pE)#pObaq^sCQ+;_HFp-dBvX9xE2J)dObkT_%HOc`
z^O1#}RdE@T5*Weu$cm2nR~MRb)e~jN=)2SI64UK!7<srfoPJ;w!lERH4JrEGgQyH{
zb|+h0HVI@r7yFtN(y<mEeVm$m;wE8TmOh4@b&nRuaK-!!+0S51v+m16LXuaRfM;$K
zv&uMyZAp%~FhtcnTD;6M&2fV{tdWVR-?4ht8?b2IR|V^5Ffn+XE8o-(?(F11wcStr
zzA5BKrU62wo5(;2W5$9-!etZ<E^zNB(V$c((;-f`!}%wQ!*s7KH)X@!9#z7?suu=)
zUa7+>T+wZ6R{Tj1kd5J`k}mYnURkbXuA|k6<Ga146ge)$dNS~uPF$^BZjxaAQk~vd
z#kDcuhN&&+EL;(%%g3J7N^yv2IH*G^e$Kq1exVe)HLmJ>YAUtp7}1k<<;~Sxq{ln}
zrK@fp=N*S=-t&YmJxARli$9H%ORqH;+bn^@y<eJBcZ0xcK|euD?RMTJ|7NHtn40MS
zlPEHQ7lFggyA6NASK+U;L^4IjC`^WJ<#1*|LQKp29j9BQ=UkIVHFzA!t$hL{*XY6V
zI-Ccq!b@np7GYfTq}p%TRU}ih7KbYyP{>HnEUh#M?{ycqVBR#tA~2SZ+B_ww7F<@q
z$t$dw61Vn85_kOW;)k~@2^ln_bem^28t@RD9Z0e-+AR%syQI3!LT)d%a=j&zlb%nr
zp5GH2b(5ZR@iaoy*?0*<(jj#GF|GQOSX-~zRh-C;)tr&^^CT%>!>K4HDcWUMEtytp
z7t)bkvx(cljdQqJ#V5?Pa==&D>U_v6I4H;rfs5&r&jyq}Fw=I=Iu9%X{!yjpW{pWr
z$}uY(!)zU@R-@}HX*#+9XNU1kDKRL+m?DQzA!r+3yfXe<491M)mkGmlD>8uN?UUfE
zLiC%AF<&~OY1z&PQ>Mi&lw_gKJiA%IpJi`P@TAz=0z4-!Xpaf#P*0-O0_3eR7k1#r
z>Sc-^l=e7G=Tf0@h9;M}U4+3emx$eHheE_Sl*CCsQd7c%VCv{iAQiWMlRA-`i`aB=
zq%~%2T;D_s@If^BtJsm*{h*iP8Q|J_SO|Cc)uSgt{P4!6u!l{Icgj&An+~$M)=yJy
z=&-a;J5AyJ{H#hX?TGC|IK}+|Ep_y9kvN$>*$Q#qgaawuV$Cj6`k+|OQC%_Ftfir9
zcn868a4-ag^gU1)gNn65On}n5+IUG!D}~wxqkO=ODleW_;@(CjE@QP{)FZe4qMjx5
z<aVFGV97mw=k>eFPW{x{k~;A3G@pLrj$imCG`;=O^vD{+DcdKdRtz+?aG65Y6kSWq
zXHE3KEPx-m2RD37v|JU8Cq=W}FD@=M&}@RTlUPmacgf&@=;ucy2>FFovPg<t7>!*o
zDvieO#yy>i=mjiV8H+i`Dr+c=o=n6iHszeSPiR*SAxCkMBDGxXAkie9(O<xJ#4JYP
zVV5)|=25yQ6g`ggy?scGkJ+aAMW+vN#|L7D9XA3qqa@ZnY4Z?UaFTSysI^Sb6_08w
zoc%J^u5srV<Q-O=tB^Cc`yV(*<SWLOfm)6sCi|&da^c(qd(bHM&PH3hs9CEnLzCXA
zRN3|YD78+B8g058_tMqFqha!bk(!Hs)fmEIVXtD8-9=0n`l7X;>P=>2^c3H5Jf%2%
zIz?KzGYKOXUgFLox2x83bw+2`fHr9gt)EMvxNiwPjl|8z&@%txVOBIBZl${V@Yf#c
ze~LBwOX4f)ltr4<&LB<Pw%POkrQ-CQz-WZbr%AM=`WN--EPCX#4$)fC$fRjR$P)=V
zWZBL{qU~^p)E_Or&(L+a6bq^T%x0shdSw)ZI>b%V^woX7VBh`c2t+XJ5hs;KVMN~7
z2W=y*Uv@o6J@@!&_Jv&aw`RUi%Y2tkl0cPo(>5KhdrI?Ty7_9iw~?u^?r}jvyO;+t
zxw`LHPZ8$1?`=>zXLw9?XT`1s=j=|JfjD<#Y=8QY#%&@Vt%w8xOeA<8jJZIy6@)X`
zTVvt*b@SXke_nXL6NKlI9}!3Qka2LaUylnAbbvMX)-5U%lbc^gOkPW_a7-PfZi(5O
zb}FzXOc7W)OSc<^lEuBwSU~F!iZwgYjZr>H%5T^6aalTvGB1|BojvSJVka&uJeTdc
zOP^vUfQAak!j>XKVk0}@!Y<tn#X&oCafl82Qq&APA}+|=DRF`PBPtC8rqZz4qxxvO
z#W)zIK}>Bxi`^Nv1Ko0sD<)%w=F}^y1tx@<0p_~O^nu_JuW;8|zKuqr*yMl@a!;Kn
z=C_fUeW>YqlV(Mern6rz{3_%+9;Ft+tlcY?yJOI($hD;Xw%>G1FtX|Xh}!}azX`cD
zQ>L(rOB6%AVz|CWP9<pVR*Tx2W)YlEp2zpM7vGo7z3==EuksGhq5Gsi0NuaACaxf}
zMhoHxXX#^bcQnqOvgeF=+$`|s%KM5gCxzFWP8MprRFLZoy$wqVdfT)j-oN1wJ8r+N
zSi==6x2@?~#n0R|a#SLwa4V8xmC2?HD2n9b%AGoAue>e3`PS6I{^E5axj2~=Qb}%K
z?{>GFZc+9f1hVFYuS`y1T6Y#gs<RAHcn{^AB;~aHbl=5%BYW;8+~v*4!=K#FJwft~
z2VsvhhEc96{9tlaJ?@~cDa7(kc{Y96z~vBT3{(U-Lf7tB!7Yv~mT`E5c6q$PKWi>i
zY+-UWqM1{a17NFR9<|~poFB58{SbX(u9Wqp`AxwRxKPUu7<E_@^w*7}eC9kyd7C*3
z!Qf|dQ2s|EM#u4#vEP8FkW+XB*MN3&qZYEzNOZ(>@rP?*6i1Yk49AV=7L!FVVT57@
zVx5?*d4=H1ma-iiE!S_oYnROOavg+=judau>sy>29UD@PU?U*%rRp|q{vE|}oPvWN
zx67g|qcm<7Gf9&GE_O3v=)v%T1!}k)e)hKkw|o7Xw7=-XDBsuZlm&*0QNFPj(NFI3
zvH*41h;bl{(3nEHikD%9faq^6PB>B=56dEe948ev4@<!YS9tdh@rFir@4Jfc*{R*G
z`=$AX7mGJX2juV~{hAFh{PF&>Ay$RgvmK|2Cv@@jWjl%!>;|e<g(t1jJzE#-Ah-g~
z(GV`@P1w+XR1Q>N2~Qvd2EL*|bKUJ-nywfTENLu<n-{*bOc>c&k?JnbC1a-|v&Rit
zHAgU^zfl|oBStNPXNC9muXdfisjREDG%hyP44b;kOy1u<&!*l^HYJ<wc`d)9mOmh}
zwt|)W^nz_2!<+Ce7~Vt~!gVg3vmc5+gu<$2rPeKTu!ko_S_6$>WO2O~IuZ+NVDFE`
z3*`WAg;^Ti%ehK*6a>5YRr*8l*Hp#Z@!8bR)&lJXjzPv8sTY^R<*=s0_V}_&o;GM6
zJ_Botua&l{U`visS!e-42?Q7<pQB-bjc9&obnq$4vw<(be;+Tl&;qB|hE0`8TDQ%W
zTl!^FFn=a70E)M=&$002M~gR_@v=UAj}F#K7{oVH$03q-2XUh3VR&SoPWCFkDmy7v
zD-Ewkj`RyLn^?$|xF|DbGu~gk>{jtY44Y#KKSZJ8d@oaH0gzK&1|oipj}3iPB_A#7
z*nZIAgc4#%KlZ=O?Z|i#A7G-DQrB7}FoQX^1tNOV!0Z4IN+aqm^N7x@$UdY%4Z0%A
zF8&JwKHLmrL#_$G@<=}_XMK2Oe|+?(GuAt?(u6CeebS(6M!L8L;t8^llZ^4T%n)12
z+7Hq(#|f@A;-f8J%j*qeN1%^t8-T~UAAyJNj`-0g0W&*VtM&lu%TznlJS^m1OtQuU
z&j}0`9p4N%ko{zXae)M}Hr7lDE(uaM4VwydzYkKi#UhTCBT+IQvDesDthO5v<@M?B
zx>ex^+~NolD=n!m2{+H{bOL$|{fR+Qe(oz*=`sO4xCAxS;=46R?1e8%{bm)KEn1Hd
zU&e$0B*X##ZaN(K@0-}HC{Bag?XM3#qLmT)9ktv7g9t++`ec_V4-Y<akpK^TRZin!
zg#1FpqYwbcH?u|Z+hk?U>d)y@B6Y{IHMo|L1m0ob1C;MJ$tWpTJtj{xQ#C@gR}1Yi
z<?7=FFDv`_FgxR7I|U09+-XMgdOn9bDQYgzb9XTNtxe5y?)q64sbBVZZVr%ZYUO3-
zd<ITt*@Djt;*$&F)04WKQtg?i8}RT&r?(ID5Zm5Kv!QRZ=Pg+Z5Km4_AO9=F^lNfh
zN0WCc@3GEuqM~E3R(3MjMB_`cj1MQZGW>_#1dN8bCkq{EBa}SYmPek8Q{T&VC8Fn>
z{CQDsuz^j(evpHd+HKBTh4ry@V1IzA!5pUCgp&XvU)lN>Zj+OX=pm;r|CR0P8_v`3
z+j`1-K#WKk{l51+0arF44$!3E76P9CIt0uCHU&#K@`ZRgL=a3EDQ%UAM?OcAphr3+
zK5uj#qFUqcSyD3tWHq%Q{9`^)6JCL~iilN!C{ck5-*x+Y{B2Tn9##A@gsjBs?84D0
z@X`SiqH{y?wYwyko8c(c1cj#c*0IGVV&bvl7&|V*_mRXXqpiRq_-@@J$eAB`<V%ZG
z+4rFY(HmkPFkBG7=or#8$B<AoqW3%YbF*hZ^&zSb@gl@RqZAQSQTr8jM{&$`c03AY
z1Xab9$T%}U+PXDvR+mm$A}$Da!r$b}TV(@j`hIb^q88<q#Qw^ZV8KO`85Q0C7*~p~
z(m8mvm8PJ5MDe24GLc;NgfvSs#Pf34ZMwX+KAgpwsqiYZ2gq!BJ?VIY-1kmu4<JVC
z+zI~k3QC$lXrO}9b9Ybgc?S3PF*v7*Z25Z_8JGOvF8`2{zR7IBwGN_o6n%H<0L>%L
z4S`Y7+z~f9j|YrF{0NF73`)9)+jf`<5>QSm%FZ_o^PIR;d?kkMPZI}9p71gY+SQJf
z0K5ye4STV8`5NL5wCSgsOLr(to6lBr`P2myFI2vr%i)eVJ*F3jbGoq8ZFC79avj3d
zQG@&QasVjTExRciPVIEDHuNkCUS<dK__1!fEFWyxW#$0>cFYR*tHzie*&QO3QjNt1
zPAqVBHK!@qr4yLX)Lf<(r#ibMKiX{-9Fx?qE8Uf39j;f&Y~jX5IrBY1r?U>xxl8RJ
z-@CcfLdiU|6vPwLDghEz{clw4DOVc8<1&3iM;zQKvuwo2PN(?p6Vx#=?%^%vJ^X$g
z4C%U7)lEd=LGk~I3@da2azwY=lUrB?sH>Hb&fAP7qpg$Jf&HS6t_qJltWd-C*pVct
z+{~HngOTqne$YNY^r!-`>e&gSiyDZ<b6m*QwD3}~PMde;BzAp`5&)}%eBG(IY(k*1
zTh%@$5R6aFN3|p77X$~tAPhzxRe*E@LDa;FG$K^cw-L0gYK^)-)dlcJe>ZSO@SUx;
zU2V5%#eZ{NXuPdjaqgbkOXl@1;HvxcTiCZ?3tKT8nv)O5{x|YL=?Jk*<zGgD<Khb_
zCW;P0IUn9hBpDZ9V6x&^D+k6$MZYWM3pbX2ita%vCYzZu6cGr^i4uakIA#qjCeT9k
zMQ#H+gIC4sThkV+X)$TOnFsC{qAhqECtzixBK#R|TthIn2`=B({1{FrE-Zp05Zg(Q
zM^l8*ZM1251~Ib1K7+O<nME5hHr7Y~$QzFQ24fo0=a<TG4129p?68i^SRD%44Z>T9
zFfNE25l79PlS&p<HfWlw#iPC%nFPn@luW$SUTc=JpFRmsQA!{3_MO*7&%!!Zc04z?
zWWf^MHFD0FN|Hg5>?bG4pva~p$)L!0rA+i06!A}HGbj#m7Y+q885GH`SUI)Dy>~2E
zIH*#e0pkezxi=x`4WvHPad8eRusL;pYO-qkppPR*&8|B_nJ6F$Ct^)nvoW*)&5J`6
zI>apo;W4HK5$TDO9Ss4>D!pkJo#n~UprUq0pF@;(u2i-uM6{jitLc=^i7)s7j00=(
z4r{d*p2D#OLFqM~Z=^cb^B1*^#K>HW9>6zs_h|e@S=cNk0|%xqw(fAA7O#ftK!xPQ
z>3~*AyU4|4*wtVSYos6GAj{NfF)eqof<f;0-fEgWS$^Vo%Eoh0GO03)b=l)tkZ7)l
z%N-Z64Kku6iOi{AFW>`PV5g^*d<OVzK3~W%q0pElJ%yf&9H+FFCZ9RmEQc9mS2pvK
zBlSt&htwx2Nhv2prpuFyfa4$(I}cOQQQ2*`((ewH^JtzS$PM~{CV;c;6fekWQTu!P
zq3Q>5sENgilMe(rk5AI_nxK1g;6hagX!%YQN~uOauck)YSCmSyz1YSd&d74ggn|lS
z0p2WI-n+?m1D9XSKX5j$(xD+7p2km3yPz!Lu8-^hIIaU*Fc0(*nT2qk#x8Agq;lX&
z&eX)AXn}>giM&{i^A5?~(Dk_6lXO{VTtp_-9SVoX5y%!9Yt_gj#S&-zH_Px|4JYGX
zM;)vg$seXL{EHl$Wlf2T#H(UgHS9&3U8bAMtpTdDb30SR@8oD!ERda23;km0P`@}u
z<oukY@Q~NBwc73`g%|O*OKIJ83-&eoiyA`UJs$Z>Y!<1(vKuHOUsFug7ZVu7J_#Po
z)f)Ylt%TSbj!JPRT*+aH{70L!Ao_Z$;s7&jlM5@+<3I}ZI9&9M-gd#%>bGTpl59t=
zNu4-mXC3xzS0H|syo|&nk-9vd2xGT1O$9nxY|eQV$YtI>hY6>1cn9a*wfvqX=S~TN
zC*9v;N(VAD(TGr4PM{IJ#rzf#p7PtbHUC|bE6=gx-MNAtzo}Df4yVS+-2^E>*7D<X
zPpTs3;JU*tqXy>!?Eub|g!XQ?SU(^+ZF4P`5wi7wzhYo{!bSgWcV;Hjy_5?GaB7vl
zWN~l5X|(kVCsAcMUUYtIaSqiO0^erGS1;rC{jZ*_`Sj^3In3>dV@3dROwf%#)dANn
zTKEpCg$v*DpCqQZphy-3PLUDVf>pHPDd{A3PIbEzLC}We-j3pr>CdCZciToFP6mfb
z8Om_sFG~q)0fgOpQ%D>UM3WvifYh)+5@OSM6p_4o2dBM>YQ?`N&A`RHRFPLBj^MZ0
zRMe9$dPRl@>;=|6R3SOJf}Kvgiq9fIwY#RRp1KN4H&Pe38(pF&T?()_YJI^r9^W|$
zwJN6Low7H0`}Qzp<XQH3Hk*z(j^mse0?y08I0tMJAOjOj17wmwm^RFSp$`4jD3sG;
zPT5fq7dK+JBG5=I<@V-M#Ff#UD7k`i2TIe%6nO#WL*-4tux8ON=1RcrE5bGd9sZq&
z6D<VOu*>f%evoQl7_!`9^0&ZqT+c+`;Y1mxLYOFBSsgsZOJV1G@K0MdgGp1A69}&a
zhD1*7<K05ohI6AyA*YT;a6=t#t|M-Hw4*3B9McC!d58jS)G>cf*jDK;@%e60a*kby
z8jt;j?n%Li@9>3j#@{fdKBb@FCGk$pdWq2m*Ezwd7SxBs8#g<}FEEW^7$=R`c;Gv0
zSj9CCOwG|^w6a(`tr$Iwj&Y#aFkMFh)R1ij;fR-D3BnX=`5b9kwh+3ei`EGb;0Mex
zB+C&`X5Q<W_hGD-q7~Ty5QoodaTJ&wXO?NO@~ev})gmKo{Zve^uyBs*qOe#G$XkFl
zhF}9Wgq%8Hfrt#ooqyRIRE&l+O%EtYWiQMwwaQO){VoH8#ajji;wIceGIcny;N>v&
zn(!yKKaL#=eqZyHt!)tgR1yYRA6|nyh<kMK7TNq<u=;!2VvX%DUWT-p8h^RO(z~)}
zV%+S2cm+nFYAK}PH!!mWxlf;jd1ID4&%DoqTbEmL6Eo*IW8cZH<(+89%^dPith!t4
z;iEr?RTpPCG^(gv$73*<j{2S%Lh+~*VZF=t>qPmGAmk-cx-NidAx_AdZX2-yh*EIX
zvPo|uG6*FIhJyLzVe*tbUcA)mxahH>yDLU~qAI!<V!)s37(fB<d9;T5P|qM{zU?ZK
zEe7H>qYDKrxH`5i8E+d7QPRD~P_`Z?LnBd15S8TzRsuaN%^c0T8Y>k>7B)Wi;=<@7
z@b$-GHVt@iBFp&GNEj7tZ8XfoI5A0H>@p45o_N7_PDLo%oERuPST&t$tyudwJ+p81
zeA|_Ldu%m^@5c#*z(B=dEklYOwW9xKXmNa+h->N_!K`Z6#{R6JbU9R-ztv`zkaZXz
z!lrQ4u?gd>c6BfzVrYTzJ|#U2`?iyB=l0@-A*SvcU9-`^guvk~J!K8-m276@%wxJR
z&uKJVZtNIbd;rXhSR^Z4UA*bh;;3$=KX{CsETeEU5jTN|s|qFO!d;KR$;02z^-q%q
z%0y$r!G2S~eorq6z6gKi5e0M{$aTi&YCpt@0B}mz19FK0nd3|g))Yp+O$<D)HX_7W
zB+U6Abj+7IGNqWI9F_U#YGf0g#Tuoh54ZDCAQz1cVO6E6c2q^N`1M@G!oZPOVyKq5
zrr~?i^c7Brs=UfH?%*M>xaXg=;IJBS<iZdq9>SvV#>*~S;p!*F$2pDBzbn<pZELX8
zPN4*eKCVF6ZZvY>l~Kq|Ix-u-02au`+jKsFh=0(5MR+1!0@Dj(%OS538qpRVN1*h(
z2-(=BJUUff+%2O$gaX-64+^2gq?4~YCsT<2S1~e?O;m}_W#DsU)!7uV((M+WLMe3v
zEl2)HRjM{HVG8u|;$^z42^Y-!IM2f|5)xc?6>r?GjMVrjQ4y|YbuniWPe%=qsi?m2
zX0i53#Xcy*X*J1}4+w+lLG4ots>3$=(Jn>zk-|q>1qJO4onX4uT@DpMT|#>38}$r+
z@TRa%U!bhpidaC=i*#qrW10?*P+-&?$xYfXa@68QCF}v|Mm!dMQ5v7o?|sG5k1N+5
zqLeXk)y|ddlF)I8=>zAQMVIP1)o>qW15PQMXkq}F^O5LRgh56t;)+Q+qEkWgC%wmN
zx$;)!T^!A6OU6X2<`jlH{R(izsQ|D@b}DfuT9)6D&Zq$^T@c*|HJ*r<<%3<)^4KZb
zvT#KXtP(2>eWLSYIgQBjfb0}x;_v|T>$RQ58~TeM;T_}vI1Xk4K;bECv<mKk^@mT~
zVvGo`MLP#YXXpc&tB5~xD=&<I*}>dk@yrzO&<;rms1z(oGZ7@~M<qXZGAP#s<OKo2
z!W;q)pBiFlqW@R+7jLj+?AMuRjbv4$cPj6evjkH~;Yk^Tld*6sI#WtcOH(8@&B{JS
z!(~1P-S~jECdXhL4F+h;%w#ej#z}Kd+&D2p_zrx4B#VeAgb|&PD<G53g;BbVxi~I}
zo#}!Qy%y0x8cgP2Tr*(s{6QkP!&D#@+=s!xsSK>FX%l^e7*InEyxcos;M6*-3utDw
zHe5otVwIDuud16LNGlM9axzjAxpAhxpf=2fLD~2UfQIP9NKS`&G|wP)EXt+k3RZef
z=dhD#r2=(k$7adG>8v5Fu?5XMxox^)=AFD!LUZtrggj4}o#APe)F8L$ysG-%lOBgX
zx2me$mGWOzQ_c7@(M=P@JQIJg{t7hJeeC${ek7!Jymk5_0SZBG0-uA9i*<aoOBaqh
zFYSW9c?)`a7u~&d_JXCo%kEDv%5BZ(qVPBu<qp^7w*&rhJ#J8--dr(wT2Q~A&$DIs
zKdskKYXW3KZD)4^_`H7o+aS-~x$(8T-Ep0S#ZR}gpESdI#T=^X6|}mL)(_wuTI|mH
zcJV<T{U4&pbj>Fj_p$%Q-zr`7E0@0aIAL$nqrdbCrkC7J<b74FWo)D;!gIF&mG4Oi
z0(-&P@+93mcQFAqyvYD1@i+YJuZR)^;K1VhTHZTX7BN?!yDW<OsC&`f4#0O6h_YY=
zJ^BEIcpwT|vg2gsfeQYn;UQv&;*bUf22lrq&H%qnbh#J0#3xRQZ8L*)n&~><FOkWa
zYw7F7(o|)mL4aL^H~N4iUCG{~sg-ytlsfg<rL@wGXj|HN5I!dl^M_E0-bHS2<m^$M
z<v_rqqKEAL5PB#Js>^w-E;rfqyA1Y(yx<&?k|^|yt2>$TJ3-M5vYzygYQxn<OXttF
zMLK<1kwu^wpF9GAbb9L$XrOf?!KJu}$0e{gy~!8siSN2lR9Ore;}U=lmqw2Tmu}2k
zh(Wb>Es7t&*J-DzBZY8%SQjVo?L92If)x}t5FD{xVn{eYPa)eH{b5fjJ$yBL6(R^~
zLiU<5mP|A(d2J{x$zK2Fc*Gem^xMoY&lqp+TmYY&@4We1>E#QS%+~TPTEu!WV=<G1
z-6c$p?+KG*MLqxGXU~-Qn#HLYi9AlR?kP_3kRVbF=Mf3qNf8OglR=~yGDai-9U`?}
z<q%2N+k{WTcxtv6oUee>2iSR(-9nky;VkT#*#gO|AM5x!jS_-EX!(IMx`!P8Pzo&5
ze*cUXg4~0Ao{+<wXa#Jni<U0$U3Skrr-zhjBu1~<>0;LPm}oAd9A?xF@s$8Q;}!UB
zXjZ!$NxIQr<UW$pnqrYao9V@3_+G+^YHs&khfx-TW15&9*!!TCx?uiAkLx&tnV|m_
zdI)lVQi&=!3!eQ?cepQIa337(+8eIB{<`t;!#IAJH_ipn<;H#Lo<)o2kDCi<?}8;g
z<38~I_uX*A_3!_{d&hnB<L#fAz4*RmBrzYi{O%sEgYW4XcjwZ3#(nIQQ@Yyi+mH>!
zi*GlgpH(Xz*Y-`karTW9uI-t3?czmC@9Dc%y<iaI?wrQ}7u~)5z1J>Se8;$n*D*?|
z4U6xYzu>JO7;E0Upl{KcoLF#kAG23iN#^YM+N)W5QoMu&w3qT&U5hotJ3+C0J~D>*
z%K4>#2Q2;Fi_RdRD!cHGJ8aTozt<MKQHzZ^F<xwA16%a^$11(P)No<{d0hBU$Axpi
z1d`o_B*`F#uv19zJ~q^&i}_Oc0AISX-#^gVuP<Q<(;%2r+FnF;FP8YqPeBB`IQGtw
z6z@<Te)huYR77Adw`A_(MRzWB3?tFRSnJBVT1G$1G7KsK-boF|JPr#n>b<0p-kgYv
z*Ni>%yc5{NJ9+K3GEC~SGgz98>YR{oqVyH6VP*d3C@qcucY)DnUKtZ3C2h`!cX98J
zxhcZZ!xt2zl5LP<owkI6DBTuvwm1iEy7TsdqFd@NA}l)lfra{Gk|)hqskvBOX}?_}
zj?f852$h<O2X12Kk}$sLMwCZ+ytS#RI7}~eFW0c}ZnOO>w7qjxsk5u2wCatir98EV
zqpVn1I%*A#Dm}%RaA>Nka0|Xhay1lztFuOktl)1xd^Oj3#NFgj3cv6OO1ve8^CPr`
zX{8YNhMl60f7S?LX(a{QSkFpROP%~bwR1|pzM4sHq~Y~DLi>Fu<Mml7+^5Xb#Ext;
zbPjpib8S%0uW92GtG_sPvKrCzdjGt8pXY1_)?iQ~pZ_UCj6XPghPQ0d(mT&?_wb{R
z7z>u@qRulx49$I3z-`lFlOdn2bG`}wb0N$P#iwbM@uJv-83)eQmTqq@Hk2BPxBz5Y
zu@-Hp9%khJN^PoD3;|JSRj@1g*LKWS7$#Aps!ILMO~vX`{wCXo<AlVv&{+&h1ZR};
zrc3>aq1Vx~M=$KbXNO&<LY-%?*Ste<7(-SMNYZ<UL$6qWVr>#z7vB?ZggExPl>6D)
z<@p&9v&&-*%c@w3AP1bf%@4qmJ8i4|T9EOp63G(5Q=2XtDGAzCtm{xVV?L`D!BZFB
zYxkvqY5<ua6L7JmNuu<EQrO2e^0!+B$U43|xO}N8sDq8!uJ1Xu^v}MfRn}5<DXhle
zs@m1s%A_@}owUoz&ZM=!W}HFp9l<nz)X}<k*}R3Z8hV;oUCuO*3wz9d<XGnL@P6Ug
ztxY50nlQkSkfE3b@)wh8DZdS?YN?~SSxP7-cru3?S}H%7ei3RFn@o??6=jcrxK68d
zPgfH&Z2?MTLnBP-3hA9_o5RI?r|1{=d-fBUY8_Rq@0V|hIBdUnt)4;{)TgB#>zsGk
zO=Je_82)UEWy8%1d>VE;3MGNq)pTnljSS-!;%E{lGdRmGy|jJ`s%c%n@$G5nG5j53
zEybQbujl?V;@jmIK4)Bv;bMtV3A0G}GuYHi@ZToGa&TfgIMVdb3OTGr+>Zh+h~DB-
zzhNChmSWL1S7O)}wNx4&Z?oJf0kGSlWwra0{~qXiN2g)bONLQjJ9|w)qdGfP;2kQY
z&tCgD6=5LBy=>{Z(lieVr9L1{b6CEq+0@Ih#EA;<hCo)ZXiR^ReQ7QH(kYdsnBg7a
z$`=q|X@^OatNSvCFQ%DxyQlC0bBxwfn@Yro$!beCUr0^ieR(n2SXZ_DYT*c;2|*N-
zCM=dBBRcVm#waOewX+#k2RjyDuO|E&HaMab-Y-7wD$C2k&w-A*@V|+Z@-QOgT5GG-
zZKEGV@d<KWpz<L1Sk{BY_aT?U=}x)RFCsscDOhLesCkD{z}b=YkW-#@tBC@7?_L~l
zwHEZc8D#^-x@MK&zT^eV9%~mkWD}j4?_N*l>pX?MxLugHaq(+bO}=m5!nwMF(A75A
z;!ODN)Z~NXp`^$1sL8sLpp~@hikJ^dQ?#RJkEK}Bpi>HhslOPy%yje+MyNjRxwJ{s
z8{#T?AjiPfJOu3YF=K)61hGEKBUuads4uc=p<75vkqZUYB!Wt%81QQWoxmB$ZnM9Q
z2!keG5dht$x3@MKjTa~!l}NMKs*9LfI#pfxDc6x<;WB9}9LZK|>RKy%#!=IY9}bD0
zjiz=&d!2*ZyVcrb2#{`er0QoCmH5i^Y%Imq&qknsduP9iv-|s-Y)C<AmsL?e)%tZa
zKdVM=I<DrI)?160;1d5Ay1d$cH+7BoA!84u(=`?^d4yvkq&5t%hM7HKa?ExbbvLkB
zf62BZXetCSzv21t&U_Ot_<ZT2Vs+N;(kRHkGe}K+KU0Lcc>u^*f&5canXihS%jo>}
z0pOpwQ0(UcHezSXe$I9`{SIXy<9ztvTW-iRVSSnme9_(F-;N`kD^7kYOz(6BO}3v3
zR?V6Y68;FUJoQ*X&nDq^%QO7e@keJ}aJ<(?{mrHw>=lk#X5tAGc1k#nXQzBk3=p2R
zQV>lu;opGRcYY>@=8k*sTegTR!VG4~+}?$J1HyA{>bUogMGF=zxI-xgsRnW33~T^7
zW<6OXyE2lSAt*(^ZN7@IHqYOS<ZGOt=XR$S6db$;TzC;p@eJ2^RZ}x?BS%}Ikxe{}
zx(LlA{0tlbmL4Zg73)U;$TS!8YcXjtKkW|#*m0>8zVvXuc(vI7NJ4kzAK6P9(GsjU
ze1$@VkaMuqvV@~9B<>3vh+(Acdu;1?L?=o|!t_U>!}Ik$Q<M~%?XIa#{0?j1ex#Ei
zMhn}QcqpKxv7L?dhkE2+!I5f@+WIQGU(q@CJMXo1rjx3)OJg;GA;$}h_0eMWl#WtJ
zVk9|P$b^F?hbI={F*i6Cu$Si7xW#;F6&2@8M{F$r(}F71E5*W<N=J%;{;JK=C_6(S
zsg>W!+?T=~4@8q(xAT%fs;0>uaFF>)kL-B$2g%}|-1Y{+qDO!<WM;Cq6#m=8{dBNU
z3U?NzOOp37BLkg)mN2X?brh>Q$ahc*w?D|d8{pKii*vGkm2ygLx<y8cY4{Ubtt$YN
zeB^k8x<!}h&J_Eh77<i~7E80AP-UFsDotIj)~0aWyA&?B7W96a^{M7&ty}mLTruPt
zen>yFZL8VAA-_`iqK;9p-otnFb7X?C)s?2|6D+d_WTXCqwESV*)hpGar71RNlijRZ
zJi?je9oEnWotdMhYMQ?p$j3*=QxkrbJKQl3GYS&P0fA+M6Bm3bmB?QUN^=G&eEyL<
z0-FY&29J^DH0oN|-tVrBt1Dq(iF?Kx91bvRSY@2A;xFd{YlZ!V()1>47z>SlK*o~(
zn0gPbpa<B%C3(5!j^()-<%V%N!$|?_bxmm)J-OQyg#QRTHMij}Ve|$S4;C@BsLN^r
z7cpN&AL@Zy2@B~R#_Lx4IE=UYgSAM1078d~CT%woax_6Byn=)TArhim58<dMhH!Nl
zgw^FD_mURuH#s%cwjxCRn+t3m)wcD)`n{bVh*w;V+f!$2z_=K^$WF?BaNtDM(Vr8H
zNgFiPtJUC$myNWvlc}sl<7{SL8u?zhDLT+u>W3==Rc$pf@%CLu8>`i2_n{x{xMK)i
zcWy5+N#>=ku|hRRcwHlC_aW$7ajn`?w3+332xTmTEe;>m`*1O#)65A6i$oGyDd?>_
z)?LACQQ5mSJ!I2&boJeb910gpUopG{B)m@)Z>ytIzcDG{Qw@I`1k{_FX{&C*ct^Hx
zMqSgzkB~gpYUg@$->OUXI-d#J{(G)-H2SDqDI6zk6tCp3x>6a587Q=ONh$n8h^Uq3
z%-b7ZsD&|xg8V8sHX~m5uqI<<vE~+@%<n=vu{X3BkUQ_7`nt{|<Ymw=W|r(cLP)w}
zbZ<EJXLFg4deyMPVZ@@Lna4C2btuhr(@k9s+^stNI#U+i24QUtTst3E7f3!W7Qj6S
z<{~PTNZvp#YN!s!yV$L5SnMycdGWI`p70+7$I$D-&r!LoM<lUPro6gR_z$A`7+S~+
zhOuPYJ8;ERf9&p`;y8H9-Yp-*3lyX4cBU<6>Qh_+Vq^6VX01QWs0ap*&)6krVGurh
zjdolNsdKxr;oF%GanPvrq6BfLkTkFl;ir8o_KSO!!h0$%jNW{6h4F2^Y6}zoE+O3<
z2Ckp7J^X(k>OaE1f+e(P(d||QJ5<DElJ<kY7;<H~s4qRLsy@)ko&v$Y3#5W&y<UWa
zNdgvNvmh?(Qx!h@NM}DXU|4uP;>Lz4OR)()_DS{wn5n-YhRvIzAMA(lt{Bh)BJ3TN
zTO~VGAQ)qK6@HuaeYV<cog9}B#x_U21DT(S!ThwkVr_BG!epMO9@)NKg8d46Psa`1
z9yGVb&Q2=i3x*thiYd6S)ut1i0;jQM>FF<Zb_NqioEf7MbL&(uYV4}<L7a+3;DqHZ
zP+BYUfX#GgH0ey4qP1nLurgPK4(LdpG%@z~h{$!JC|(l3R9dw?59e<J1UcsBUf=Bp
zqjh$&npS;qak?Ej5Mvy$O!iinzgCrqC66R5Z!K-_gkO^dK_y|EBJsFd-OuN0bk*{h
z?=OK?wc(D3CF{c<<T|l$unj&VIbl;0ZKm22NQ!t)O4CZ9rdmhuDCsD7_yk*d4Gs1D
zMvztC@Gja9G4^8;(IdG6^am0<`BNG92=C`Qz*6{EP=h&Gn9S1cO?j<hK@(E26aMyL
zkM4+2JQS@){8jjVp)LA_>?HKybcPEx<rjuc*y#-dMy0>vCabnP>bZ&^(pA(0sxyB=
ztB$1KDgooT%aL(Gq;5Zn)HOf)#X!`Ff;#28?y4EkSEB=n$!2=EH85NS+}9=}ON>VR
z(qz=qq>9~#eymsd`qB{s3ha3E1>SoA*F)<yBy(&aD0KiDh?+J>!m$cGK$UqOpst@l
z+u%)z{Ez~JXue61wIwu&;o*0YmhTCF{y{HN!k6Q{#t~JWFReuR0FPb;jQRT#N{Dpp
z1A2HlM}iz!mn2qz;Je8FiVHt3qI@HickpN7`UT`mK0L^CFtVu`^%F+O{7=(14el(q
zNS=$Z^klrt<8(H{SA#AV5r`eYae_=`E@kH<=`0iW%j`57O}QVDeAjMi71hzZmmXy2
z!B=S<V$O!;lJg;11?uDrGL5mc!?rOHD`i?FWmLqu1`#cr14Lh}98+`;LhEuM81?07
zQcj-;f0>?X60|XPKatpBz%xou{4A^^a)ieIg*iu9p%^jurSNOTPFS>)58=qf^naD4
zbQ1(UsZ*=QP18c68v8E9LKmQ4FS3<D&!9qyzD;aU==&c(c%;}um#~Ur9+jQX+cuHm
zFvsxgrOqQqupX+OvqEI*dikMz@iI3vmuW!Zw*!#b?uQA(Z>#_nFh0hd=;aWLE-LLO
z(8-1rmdf0P9;A&1f8wVqQ9UeC_&JP03GLAB#gvALQ;^M8pBj|=03G;V8_re<DboqA
zlaQ8)b+6f1I<kmJm_h%adW5vJC9Jvj^wJ7cj9RIZQyg)^Q2(SL76XSci0?lHrd-Jk
zL@%%es6mnL`>HC1KO6MB{uZyGd=;#r^9Vwnq7~>_U8q(+Pe91qZQ;?X?XTJ|+cDG_
z`MMufPfaPj&i+~f!x;MzMj@Y$<@%v-tT_lP5g5vJ?JY)c*x#KQLk4I_MtU^FAvQqH
zWX9>ENgIOk%`(&DjF)OBT4VpvfVo-Jc&lla11WSWAPI$<&R)aDm>-#T@ELo6sebf6
zUwT8Islrx|$p>G)%=F=Jz>@@6DBZ4r1E%`-;q=9D*Mpr9a6bGpmg%6m=|VOrVliRq
zHtQT5!hT>RQ#!Su-~tIUNQ7wl1=ISKHHpFKHyXeb!7i9_K|-rKOaG$vgHEqwI>u1z
zm7T?Fc++`=b7iF`-57og))O&`8nbHf>3L9z`C*!c8{c1nx*Kj{2T&|MMjkY_S>lPS
z&{-XwG?&6Jn`YgtRc_XzxevrA-PU6%93^Hj2*BPM1iQC?r!%zaY47jCBjV^az<|Q<
zLQR1jU=})arpXkW&|kPi4iR-__=hX#FLV1eUA+RK=P=l+8(F#y#IfQ!eCCkCRAJLO
ze^L#Pir#-)|35P~a;-DMfY4ys^5kxC><DZyI{AA#D(?)3_E_8&RD9+G*5RgupPng6
zsnV{Q`L7B8W(5G^D7^ZTILZN8SHAHOe3@T<>k-HPOKc!C9=L|JTh|Z63%VHwB_WPO
zff13BNQOFiS*zcWlBCoQzm`LdV-mhjZ{V}r!J1LwXA7vgd@Hi+kcqJl7-o{|hQTAX
z3DyXG98tgwM^Irt{GA82H1yrpKxYx75|Jum$;`TpOCq5n0#$$6k6OrL__sL??^i;w
zKm3meHO6hWu3`9vBGv?TBix8v7Y4vr`GUWMt?g61fYc5>Odb+yD=-@@g9VS>hV41X
zoexs{Pd^fLZ`RWgJ6z>w@D2dyBXAcVoZBG9nKLlxyYpmHl`b!FSt5~#+U$dknFAu`
z{_7R=SK$+_E<n-12pLGvk*qV6dh_g~UCzh7p3Ny*JURb)fv>BDCESG?S|BPiW;vR+
z{NcpB=EGiMs^SMy0pRA<xt2PNb%Wzl(;!&5TJ?0}qmtv45=$Kr1G`s^UZF+}b<KV3
z4+1=5NLev4z-f9iIYs<7#cG_DBljKZrG}%;ev1x4AJp>eS~3n$jT~u;2>z;c$Kyj&
z(b*8tL~}^<K%BP_9Mu9Yy$h9{KNs*T31Tn6K8m)WeV%@W7gCD6ar_;jlzXbAtJ!|1
zj^86c;zhjTN)ooFU&RO_Q))xlaRlW4hzp?FZ7BH7bHEqRqu|*w#@Vxp(_egU@X$HM
z`#uToeKW`2UlB~gE<>^fa*H=LT`&q|O!z}kzf(hRYc@>`hKQ4<P&(S|@KxrCfN<#W
zeiTjd#g|dP(N(3raXM}!+X>vG+F;4X21E&zbSfRWuK7uR5cJ-qY{O;UikxReTXLGx
z#)DLNwuAHeu(4|NZ8rk}xk?2<Ev7mz!^c1|DkB#?KRO)#o5u4|I8a}O<QP84?tB!E
z%OB!WhWOMPrzvC4N8x1SZYC+=O7FFcmVTHRoHz<+?T^E7{!O+GF&GZ<;s?#+y;T<a
zpfp`SK)hc@4ux03KP>-wxDXSo+jSO7gi^E;uy?tF2rd;<Xw?x2izv9gcqxpA$Q^AI
zCC6YiGG53PXv{~P27`sM4PAESwyL+4jsPThxD`33N8%S9ehayP%|UG2RJn&?DS|K?
zh?pdo6N@K?)Ps<nTD+WH>rGSLj@e0FIhQY&^@(0m_08HFQ;jh~S$ueL3*~R~RfpG!
z*U?uP@lr0zlC8yic1xu$lK+-MoC_nuI|WC&F@g=vVJ>q-4JV>Ubck15(5L>oUW8v_
zQ?58r|5IL0>S(j&4zjIL_e|D=$SC<iUc(fU4>uE&RL6H+U*evE(i>W^CKoY9H|%L}
zD3lKiH$(Rjkx(N`4J@0BecH;91&>kT9TM~O0;Z2N*6ExFI$@)=NGJ9a7OliundLoo
zh5y%ybdnCBNGBE-0)PzOF_BK}?8r+cOR{_^Ma&1{2W7!d&I0u{`~#vU$iH+3F(p{y
z`}1!}KnXos4Ij9~x|ePm;!px3dDDg*|8oo>4u_JJ^F*OTGE8bxs0V8y*7nUVzD!=q
z!SPTIq&EpVG>9{eheCCfS$LStj04;t=DNnw#_z?E=ROLm_q4s+*t!XWl6#vj#ZFc;
z$Cg=QHIlbI3JPm8888P1UHxZ<=&{#a{|Fj73}Eir#^V?p`49XjCkmqaReSeeKDsIV
z*26yPDEz|1L?Qh-w-TgLNbf&k5E2(*vJU@{lg~Cf1H|79-bcM4zG1ra*$K<D-aL5E
zu43WKFbp46LsX-umQxKhRObjV!c$=+W^I%=WN*x~h`H|NoQ1AbSsY#Lu)UFuBS84!
z%!>|Nvk;Ob#>{>_iwF|ct!=aZhR@{HKfHXk;qN5TGjNL29XY-#P4a=k+{L(!O}yhf
z_|w#4X_|dTo8ze<hK4#6Bq8^SI)@bcW$T^XLjA-|9Mx_;d>UgD>c}5KGeZUksQRh;
zz$0i)*#kaDd%&`(zc-;a_NYDu)yPZ4+?RRu?P%&?m%jS&8Lm;%o*yTW-0)T57pQ_5
zxWwiC={U44ajB|Jx%Djk2UtCyawJ^pJbx+Y+-1yODLg<3x}?2=KIzn#2*5spE8RTv
za@>mT!{R3~t&~{v@OE>i;~OK!G4ZC?hd%{Ha(NS(z3od#@|S*!RE0ml?-z88z{;_T
zNcu~OMsjZXO%Fh#n#3V|Vnl1iKCxCa)F~C(`J+YyGl2T-{8?G1PvzK-9WhFd-z=Mb
zeUcky(1{tGVX?c6!z+oqjPKdwI@v=wz4Ni)aJq$pCpbIfY<fM5*v^e$zt>cJm-)l;
z?6Iqdx!gfVz>Xlds}hd*%<f6DSR2d_bCO|PllPLV`ja2O?Gsa`#97wUhjDi=_sML1
zYEz}QUA|}ulME@vtHX3BtHbwXbyz9CI{fSpBJnkwE|=3%<r##1reRtTq)#ZU6H%l#
zo^82}2WF<G5<xD!`|i7xZZ}DD-m8V?p3(68g+MXt*gwOI;1yF>V_z|L%xM#MGeE8m
z1I&N$FQ3b=xU}x#+!!;-<Z>&+Tr{5V?F~`K=kpta_WG9Y`itAY)4spGK_DJ(3vde!
zuGzuWwM0Qj3hCiS7jn@YgKJFTCZ}+%ywkrv;8yaty`iyvL%zMPr4TFx%3Aex9RsGB
z32kqfl++a-4U)<{TwRolp0m2@61bo*0ZYcP3AoL!%@pqG!EoKxw968-H>6_?kCqa^
z(bS=T^BZ%~)BI%&NqxRghk2(9ATskhBdLJj%hyA7u7xVc49`U~%Ifs*`gqr4@7j{~
z%Ii`4`>5w&QcpUD-b@EP+@uk?ND`yHp*5*9+?P)vJ=}!mT(sWcT2i>)!Ek#<=Avx|
z*Pg;XHyCc^DCVcU-R8k?TSw=jjpcAF2gA*{C>OOE+=R5<x)iQ_o?4kFanh9+=b|-y
zWvx9P_AvMq4}pnVzz3^4gI`CJDH^nvs(TjYS}x(*d#gK&>z?nc&Uu)bz;q9Q5#l=H
z)7-0`=YctBFk_Rk1$)x=TVlAi@5)8Ht)E+i1dw;Wp6=F!=91UJoU|Sfw->lcR?nCO
zE^JBX(!<qVo{J)bOK~DNnASHo?pO1>Jx*l$6=skk)5llG`1MF>$~Z&Jkt(g@o<c4+
z<2}Ay<#iOyeqdg;{-*O7ZcfKlsqQf_-{-IN{3WS-rC+30^&ObWV{_3fd~a_U?eS={
zhtYfqrf^j*nrtu$ug%Q9TPMM_1LtrugKy%F@f@_q^}PyQhpR7cGeO;)hiSe#7tJ!5
zI^VB$-!Bi-15DR|dc-Ll4tkiKrvMXOlOr-zbC9$(%U9&<Spm$++S&um!h!WjCRvBd
z*GSKMke%b(z(v0M=ZQSy^BY8);-$xc@8G?Yd(3e->pPNm{#_sMCITnf^!dU<dsnI5
z$;gN;nRfNOjc3(U4lf+&;r(9TziM^2wXY4k*9D)?2Wx7+)BdgYy>y|yR^<e@;o8dm
z*ZXa}-^}~x_+H*lJHPGYefxFD;mb6Jr-K=v&#x~%TeY@k;fCOI;V%?ETYM&3R~>eT
zw7b9k&)fg3{oC!Ywf|}RpCr9-^{Sptx4H4O#r5vwc{kr@HXMt(*A`|x6RZmv!c3~l
z79Z3v8$S!QqMLp}gIx`EUF(9iD%+hI{-AOi&-0YqKb`qNWomC|>v$$wC{@J`MI&2R
zy|#u#nL`XGH#x57&?j=yo(ow2hCXJ)75#kPSM^L3Y&>x-<#Vk$X|K-ZwthMnjiqlL
z4b3y24b~PvpMNG?R|t+$(|}1G8^iBk>~*BNj<q1b901+wgNORUKeeU0CoQ4w_&KY;
z>HTir&*weUWAJ)j%(LG4_kBDsWWN3L>q{NH>J<Dzo)_|6xV|pzdM02|KcDYOSCe;I
zJHd9}or{heEd35yJ{Ipe`kuvI!FBZ@FM;!I&f(e9qTcuLT*$odEqm@OdtOoYyprc^
z{p&N&**R*XjRRcW^*rxem;=f9XM-7994%5Xzifdf#PF~D4CA!*tm_btb^-fZW}Ly~
zhTPt7!4~S)hMEM8Guy7_b5<>L){9JFpxq4<7OpR?tx1vg*(#&J#(-KYQ(&-7ZT!if
zzV_`u`}6(Z>1dd+wq{-RGtskE>r0<4{zBn%;RYI}o$|KD)ArH!>icuiCcYz&W<JA;
zt`D9K*A>^6Y|v%Iu5qi(*avdaRx8so>lr5Kv%&iC*}}Tg+NxkN9Ua6Z%G(xB&EUuV
z)U(3saroU!VTa%I6Z~$AVP`&=i`K@l>w+#Z1c7^$qJaBa-j<$s^Kp>!5#RmuVV?Ef
zKOfILXV*x5&DEpZt?;saW_!ZU`shK1n|aucz)CObXc%o&BHkw)%76}9k9L|_NIUx<
z%0)-Tmm9{mud818Oq3#n<IQ2;iIE{5PqzOyKI+~3n9~jQT>k!b-fw%H{bEf2<?nNF
znr%-wy}45PR^A_2lZy^lXkT*z8RTAj(&1T0Lu2>4P`u-rpr^u|2)6I3Tr`GqZE@KR
zJUhL5beAK_nV-);8(8@)<CH8``7NJ;j~E@dbUagBTQy6_`T2a8@HBXyMh9W2!vmGw
z{d6vxPdyr^p2z%bF51F(>CSq7jc3sT`?dD90Te&Op{nRf@1vi~MTe~I(H){Ch-w`q
zvX(<u`R@#np6U3G{ye<f$_$VT68G8R*+qeBqh+1fyIVRmwD}sC1{(99^5OZh%zP#n
z&7_~|zv|h-^Uk=h&lF~Q(*Jy(Bqy|8M*ZoWEMD()MPJVzo;gh@9@4(H)bUJV#=7GA
zV8*i&+AAtl<jcMKS@cpX*V?|W*tI@bTblW7C@vJNtWYfH=eYTEx#)RYgO>Jn1+<oD
zgJ;5ywZ&jo`HaD<;<4_eOs|!ROqQm+W}qz9yo`S?7cB<X&)Wu`RaVbg+E9O5hUapP
zzvy+fMyp$6c6=<Dk$mk+@kC|zQ|5Kb%O()ZNEP$^ERd}C59RGjPhU?RJAVn9L`Ox}
zS@<lApQ<{N8mKyJPOR#fGFe%q3>v3su`mK2y3x;JqLZ~}x@qMEH|tkZIi8&_twk5_
z7xP|tD4U0)p=6d~Y8pJ(D!YcVuTXY|E9>Y_8l{`;ZuiBN73}C=b3DH-F5AlUO1?Y&
z%Zqnm!T>TeoKg9Wz-z7(T2B?QL2Vt6+bUnH$&{bm#Qgm_eBIg}i;Pd#%1QXOHO9<_
zSP#{4j5<cEKXILnn^=E-Z*SP0Hzifl!mFr;0278%-EF;8@1!rMy1Sld@VuKgPFHu=
zJhwIHa?RU3T{kC66zqC!`9y231V8JAR8K3%mleG4;k|e=>(I4UyOflwhQya`lzok|
zr;BUC_oI|;+m1bg?;Q<=c6gF-U0bhUa{Q%yt%aj)BawxaJ7)cD?3SF9ypv*7F8>9)
ze@A6n5pU_^{UP3W8;@);-nbUrSs$z`hS6Xat^TOYq+L#aY8-l=!?V+~5?*6tI1zu*
zIF71sl$*nMH}4GP6z6?B`=&`Rp4q%FrtEsk_Rwxu16xPb*ObKPqwIdi@K$hzucSJh
zo*Q{)+3bBe9=*c*F}y!rJkp%zM!|dHwxkE>c|FhVd~I(i%&8GpblYdewkHF>?+n{s
zLD@;WWm<HyOwTiUcJ`@MmkPEFM6hz))bk$7j(Is3?c;m-d*RAK-XG`vV!k8GF*-=i
z&PpP;#}nMb-_J#>2f&GsdW;%ezuM~<4L(y&-~ID3o`vgr&aT;Hp8J3w`wDuuY+cB>
z&lc0Yk(6QE8!bGsI$WvFSE+ON*Riizo#PjZO{Uz~)f(<UvD_@LQ_roWZp{60E?UVS
z|GbjtzRdG6o`rk<{j9xCw&*!KZp}px^=;$*M)tsxRcnjA>rjfM<%EmXwSnSl(A)_x
zw^GN<zeG=pG<TCa)|Wc4>wGSB8w%NWWYZYh7*gIhJ=a~t$KR!6&GudI+jzf{_lE_`
z|K;zyc;9oN^83laFXsK6@8U0!?X3aZSM|d6#b;1%J{SA~XHlOmt&750nuE&bs6lON
zK6g{+p??CeWt(Vdp7m_7t}yGFP<#7u^(oA!#!<MK`Fzvq9+k#5hWDF!zY^H;_oA(K
z-nV@Zo07g`)B1c~)D^7G5>0uzR$y09?kMFpSUIP=1`8?Wbe=(Nsg5m_S^KY*`>MX|
z<^2KPFSI%{_VW&`r?KtW!*w0=`c`UV&iaSS`>b-~VOAR{H_7TxY}m5##<e>>BDnp)
zZ85mi{}ilEAuH9tmU2&j|K#-xZVzyqtp1sak0Mw-bp3}ZxA+GquU~M_1NWNMpYd&M
zJ#qc8pIrAPtn0tA_bMBA`B+<dzXI5a$Ne0&c-#DQv{2E`t@+<VnS+#h#p++3PY1p!
z>6nMx{C~ZSPuDld_+iWYB;BC#UEuh?=b~2AOV+3Lhq=^A0-V|qY}<eM{ZZ;W4CM8Q
zv7x*TmFuP4G0N@ZdwWCbUkbLR<vbiWc$@74n@Kv<*DJtrUFc@x`&|hfVND63uWv<F
z-uv1dTz!iiCJFAg#{GL0xGw8oLF-cAlDb1|>>9)9C~v$l>mv^KrnULHqUyZ&5&Jbx
zYV-YC56pgRFEfuj)4DudPfb3i?S%HSF8HKx`+(c+_TTAzY)qHX_wBj5e5CK_I&Pfe
z6VC0E^Dx_nfbsp>2h5uC_7)CqZ%#u#_7^7pp~JpK-`>Ju`Pg>geQjKd6a#sfEsgn@
zw<NIx3Eg;@Im7d@uAcbgggG`k4>NOwpU<S8ZV%(fwi}q&bDE<JAKML7j5WTljZI|m
zGPrmyQ&(>?m-~TPY%t0AXOy?s(VUO<uM94zuDCtluUCOPP~NXsQaInQEhF>szS_6B
z!Z(@pt8l@|=V380PR3>C;rYSsO&I0J=zZQnGDhF0jllF;-;;SC;3pJ)HIF`Vzr||>
zvk;hBR?p}J&;9(o!aH3I+1@ZQc}McYq{HRBNquX4cP{tb#jLk07t?FFN2P=~9;WYI
z9=BROO((de_Ek^MrTM6(y#3=TO?bGcFZ1}7;c*%K@^FhU&qsAeV{OTJf<wu098ad*
zzIW$iy}B=f3;R-D=*Q4_RX*MWdO9;!V)WtL>;Yym@dxb<nOKglFlp4+wZDxv8Fza_
zBF9$7Q<ltG@3r}8zV+YFS=i<2+PAmwIzJZ~9IG%F+s5V1=E7bk8DsET(ygS;&Exal
z2jbUB(LOfDitGO#Wcc--|BUzRKY;%<0`uH^^RW!}V=<|h&K)qbZpg>B%#4g%llIZZ
z3|wIXcxrQ(S^upmoXs(C`+(avaE>?nv3QuZ@AEX8@VqS^#<w@~#(eC5&gh3j$ZXX;
z_6lVF`}0wst=||wFLSc%CzuTr^U+F!Nyiczlw)4%gWy_z4EbcVk%{Ztn9`<)+dm2V
zE|%dR*CBak=;0=Q40<eYHxt9;$1uJfxjt|V6Z{xF%!-@5Ec3i6?C~&_aHjoA*6@~m
z?8iv(;dpl51v9z>T(q{wCpgO{Wx!Yjw{r@7ubgj8NasfV6kKDM*DI2>?k#U~12A)}
zt_f+Ilhe91f2!;Fw0tzVeEwPo_ia*lKAKq$H*qlB`suV=4mWu)+|k?f(Q$)Ic^Z54
zWKR5856?ihy81lsjS-Xx&X1w($34Aect?ibDy?1aD(r}q+o*X+<91Xkp=H7J{y+Ix
zU(M_V%Jfyib<G41%IEuNIv({^aC3eV*<C*FR|dni&pP?KsJ_+z&Fje-o#FLl8gs32
zyQ_cN>#UxJgMEIi9;SD8GFHzs#epmGOq=_w8TTCMzMwhG(DR%^(g6?m>U_^1I#PTr
z;}7ks?+#BZ-6>o-tpIoUPUhR>Q--E8@u3=%>MPupkNt3M9)B7K;14iui}TS$Ta!#(
zqX({u>YBd<o@8(tnwm5iZue67b$NZ6kT*XkeLdi<!DVP*&EWc4m*t~F8c%jF^lCE2
zgX{&W|MhFw&n?f#KD-R>9!Se+-zT`nUTD$kAA=2J12zm|a--n2x{K>f^^{p6sq-FW
zNO_+#adfS5o%`<f`dOl5w0m6gFca>BR{)=hzwGcZ<ut4Ix3*!UrOX5?Q<va}luW;o
z^Kg5Bn^*=nvjSYMFCVoT-KP3PSeNq2O8uC0EjaT4GSTW!%LSPR)DOXJ0&a!DW$05H
zZ`|SX`dfh|{wvq|U_OpfWBv-PN24k?Qp|anZeZpBUupi-zUtWmjMLpS{d_)c-^2B-
z$j9-;8C=nhD6{uaeFskh=leGEA!Mob&CAlD#}B~6ybjC^gQ>hfQF{{}_WO1Z)90(P
zSOUSU24<__WOD|8!>99E1g0I($L3_>N_4nL^ENRHzac7v_j7Z6O+IS3`qQ}yO$w#D
zjruY9DR{Pxr!m3JIq4J{4GC@~a2*Dh%BzJLxK`c?ZVzya4bG2!;C@Ol6Fzftn2o?V
z98Bt&?<di>)$+904HKP0ny4Y1hdBt$>(-xSP4|?;?D<)*n<Ov;bQAS?#?L`JHJbkn
zznxi=%z$t2)#v;?`F<xTl+Zx)FQS(W?9=4(J}m~O&DL+MmjM=SuEF`Xp8KVIwAboM
z<l{D9&scs}zZd>8v}C;Ec$h43_<YJNfb%#r{=ZY7wVCp%aLYj6t~zrY**{?y&+cc!
zzVy6-ukX1pum>y%t}AW&P`V%UaGQP;9JD@W^zhcSiyrR4W-k|0zJ&iVSpyGO_d9;?
znc`~s-c#ck{Y7ZX#+&YW!cBwg+rP!@*qL@S_9EZz{Qm(Snf{-lxy1wZf3<t~%f8*r
zcq_EK^#!k6XWGr^*1lbWXHF`U)$W#E?D0+i$jI*F={(CvA-Gp}W3MV`-6rE~-C%xW
zN!M^?q3+^F<F3xZmcgABU-f(Hl#i63X;IzHf8gyv8Ms%HB}{Pf*eSy8|C-kkGxhCF
z>udF6+T&$kLgQj{19(OI*S-Arw9E0LGMJ6PY@|-bpT_5a)_9n5xv2Hoir}C8hhFAo
z<e4ZwBc}wn@f6{5-|+G!9kaMhTwO)oYSR0#6;RIYb0((rShmj*+?H4Kv7aZ?Uzy=D
z{S{o-H_>a1elqx8b|yw}EB}Z&Gq|+AaAitot<00)TKAq<wpN<k#v9q|P-c>?N94v-
z-;&W(V%tA(TYy_=JZ45Z_Kp<yE7jjaxzT@m^7;ig1Gow0^*0Y)|6a<i`S!_mL&5C?
z&cza@ydXH7u8HPQaIgNEmt~0#J3y8RX6B#gqcOG~X<cC<T@T@{;8yITO&e2Y?{Ii9
z+|z%Vj}BUWlhe7~GZ?OSKYkBetF+xf7Oo6lsomDU@_a9YFB!h)$J+ZHkEe+pZ#A_U
zP5Uu4zMjlS(zjr7+GeG7Ux*UEfpSCPmHHsKeZZ}^F(v#!l#=ij!7Tn8FUvhln8<SV
zQ!vl{Eq3(sHJP8zp>MC{Kr$ZBf0Fg}FwX-s!|F<O2ix(fQ@*|9-(`Fz3o^2~WuR<U
zzb5`8K9EA03_my+Zt_2SohDsdX}z8&`F5W>MYzMK2-oqy^Km?OihHKDXK>2a=@j7>
z{vU6bN%#DLIDA~6pX0{E-d3B?nJ{_4x^D$$y{*G|ufwg-ie}fL<H)Ja+s0FbJ9dh2
z-EVj~mKo>Dbew*@4g>cbINIKjfy*qchg);h+k3lHI(sgy&(GWBHxqg7@poVOyp8`J
zZ8}=;^JdZ_J8ygbb!dL*`?c?wx1o+t`W3dNbmig3{DAt59y0RbaLT{im;>R_g#YV(
zd2Iu9qhRGg)yTsiI7N8hkM;lV@gbG%ndwgG_YiQ-4l_0#SH=$G=X-rFi1(`=PZRc(
z)O8RT$LrEIvqIGOZA|{u;O3kn+=i3DRpQNs55sdQhq?q#ru&o`DXQ7H1XmXXvF{+&
z@3a1X&5_jy+y<*J*+&kLBZBD-13Q<5&nTVmj)8b2xc!A7+GjE|qhoDL@knzixUE(6
z&EO`b^=(e!gg=5?SrbGX3mR)%cHiHJCY~C)fc5pZ4hv#_n99y_eyDo40O#aZ22PSB
z!#4%j-Z(T|r8Ro~BdihSI*f+X`bpNGG@$+pu60BZ+p^NVTGp1;8pCxp2eIuc@zW;y
zyRYjNVCLH%Ju|26=^ov~jlDF8V@6WE$cBt~xQ^B!+GAtL)c5@0F*IHtcz%_xW#3@9
z=ieQ8+gAdYjdAhqMq`3#o8d-=wx3IJ!^7>qB8Y9k8JsM$0c(zrT^YoFq|92B@j$_~
zUlp9x79_aU!0l&UbY?*NL$kc@OqRCd{$uAy@grOfPFT5=ZnHL|O1N~Ca?exF>8qK2
zYerwKRIcq~=)%_oL)r%`m77nwNo~-&^)toEY~V_zavLbOiE?gyk(-zLmhAA1Mg?~W
zxRr)inRP4kD+q4!b%8(YpU!ipM&W_rjsn+Pz8)Ed=;0QQLlzXYZW&oPp^z+`hue8W
z5G}U;rMjH+emmyi;l{o%h;8sGUIqJ;>XPw}xiN_Srx|)H^Pg%Q2PQ(lf%=!3m-c~p
zFSw2m2GNT0{>>UlZ-RSeQV_==Wcqh#aR2sx$kSV<e;InKwBAp*vv-@!JeALTS6Y87
z?*w-gxYrCWu`7sLOjp!g3TDqogE;OggL9dEiiex=v7z~UrM^zQiMgfR-oikd4Yv$j
zd%<nJC5Xn`+@`e6?Y7CF)DNq#Bk*?B6gPJ#V7B&xdu0mp%k-+unyyUu53O;1^KbRz
zO6EvvPclcU>nJc!Ti?<-A`m%gw9?oo+>8vp&Er*OOl5c_xC7HY-KYF1OZOVP;JR)P
z;&`qM+}flYHg>@s2W};02E<}XYQ-|PyuYo$9-!QcPcUazE|GQGfh2Pwn3fr=r@^Fi
z5o}58R$m2o2)Lf|_3TdPOm<?y&H8a@%4ly*CXRAeN_@ciI`_@=GCMP$8UK@qEBurn
ze+pNgze8=W25!H#osoAt)24lWbACFAwi+&_^c=2FajAShRc-<dx%pFG-j7dkwOrl{
zZo)hdH(^M)8S{sRYmM9OT>wto+<Tl3O)K#G7`0irGl*jhQ`wfyN#e&)w=js~H-QVC
zcP$&g>EVt8cQV~r?T%j*#Qvdl-(2n=5?t@6kwG?wj4W7~;!o1<U0x?hd1x?%PM|s3
zI|V&)ad5(zC)F*O6-)dcCdH$Ss#;OsXzQdb<=Uu2=le`gsc*?}XLL{A3GO&>D;%8P
zlg`i5n_&8u`uWPt!<d2dAh?}(`?^vb4Q36bOTkU-LDwpu*Ve)H_5F<3DN<gOQ2~-M
z>;}%+eEdEyOl&@WoXyL9-#k7B$v9>ESHIQ*<M_pdZsD2E;LDR6PR27i+Bnw$+rP@>
z?qP0h{!(6~ieolsd_!>U!0j`*%-n2C0kz(OYq>Xw<D*hs%I0{gMCUDC(0Sj`GHEpR
z3+^azeb$c@pZvSU_xrJ=^IfUEr>SQPu$s3Fes!m#ar{znuLE~7{Y-E(9`Jg4I*;YH
z3c+oB(9dJq|MGZr!S${1`bl5H&w>mEXubt^0Ju{bNAp8|UD}iSPPQ&vZ)G3;2>WZ}
z?<tQ9SET&Cj(%j%=cr$YDEIuM$a^c7p}ECrIS)5sHTorG2JA;RrYqs$jsoXm)iU#&
zu`7GHjwga4^RBhV{W}VrzE_Gz_jNU|3F6qxRR0M!rG2Y3_Jh;li<H}Db!XQ2xwM?>
z7u?z>y)Kf0E7L^;H~Fa`KAVuCz1P$FD)po1HsZ~m_VOg*p_!e9!*RhyKkN4@DcxlA
zV5z@?TMJybjVp!gNxNbEOmMFQH__nY_;l$_rU5y=Ett_icjEbPjoX_D%&crZsY@?u
zYdtV?3?|`=9lo_zepg#ZfoV4wuaikRcO9xUcbggH#GelaovjHrq=VI*2<|9wE3NL#
z8fNrF57)aEnPK$Mk<wq8pIr5AeFi<r>PzuFSU<Skh0hMnmnw~G^>l1pl-q5xD_z5I
zV=B8^X<Kj`J_|pye#C1ip`BSn!5joe@F$`n!9>5{aUpGQW;z^`FM^v4T%GkR<rn3C
zf5CNq&dZ4mP3}%B)O-uB?KzM8X}ekE_i%H7n`~o9;WEpY^l#%S*7w>;>Z`OaEuTRC
z{i5GPW$-9NT<WjjHUaml^*4hbn+J|xa6P}|b-$EnaJNYU=<7T7%RwBomudGv0%qe^
zeaAO=8cOG>Tu%_(<X`bN)QtSk*ic*Jag5&R@i5VO%sM9&^Dz5<)$5L)wpY+GhlIZW
zZNG;7u6#bU`-~MBU)L+Z^%$J5%cAG3G7mH1*S(JA`;_WfzP&BL94&9}wX{7Cw`mh}
zZ1|kwX}Esy{LlOX>r@mCjZgW)!Zhy0_wDuH@^s{RSjtp=o1-`TeMSa1_73h_^xNpA
zwila_wmCN4i~0Jxw|HGEkssNR!$G>c`g-t_*h47i_;xba?SA1@w_wKnF0$3;r!DQn
zrgVPVVz`6<gK<}Be%iA(^v0?(8+s+W>iu!#&2}%dQvA-4mEpJGdVpI=o7uRi^8K#h
z4g)vG`aLo2_vEzS8lT|0cY3=~y8gk|fombSF}vuW$%PEPj31~c39k1m;BUD;)jb&Q
zz)PM^QyeI#Q`I;2<x_)O4BYEB-m&R;cMl$K*DIc$Gvmm}6+bU^f8hC22Cj@RsekLg
z=J%v&yV*Ududinhel6=?hJIQG_iyvpp^b95y@TO4d;?v}=6O;&-q$O@ee=}Tx95+%
zew*^)VB=ss82`uKhM0kqniBIdKi-|dtuMz@$>tN-rBrUkPk@hmgV^VonfEmV$0fL9
z-}1DZ;*Yp)c0VY%8Gmwe8<yb4{Am!!zNB&^8~ft>H{mt>H8$@ly<|fjJ>2m>^Yon7
zS5D7rx9iV`mJ7bV1Hd_5JsodQrmL&I4f}k3DIY11krUj6zkoj&KhN@ql%M-{*Z*}8
z%{0E2fty&B%(RC)^xacyclF<Udwymd`;+R7&#8Ya{{cKJh|i^T6)r9$fWF<jL+Exk
zjtqa!4IW3^zj!?{U5^af4w4b7zYgKhN4Z!YCv+BcC*83A3hp3q1*6-{ydM}0cj$<p
zr?emC>!bQszv1_E8MsY@>+3k`_si*gX7|gj@i-=bFWGN;`_p=AOY{o0c?g)u#*p}^
z4|^CtA4mTce4x&(Up%A6B=gaAY-l*&uT8*BviiKfASsaQPU_d|z$`9nv)slYxUTPe
z-jrE`%p&_S>;rC%)tAm$b|2~cHs=Qk4aak)kq+$J7GS!{`j%-jnUCYZZ7gqdCDmp4
zrpB=0-@M%=)3<Gd;d+lFcWkZFeMq=-AfHry-T&_4()udFwdKP2jCBUzv=n9i+X9?B
z!;|5EWoLNQ?!q99Z2>7<@cQ8T7KULQOOW<28%t2GFO6jmH_e9sQ*N(~e_Pt&Y#=#s
zT5rMbA%oOpgU#@g)`4>+xTq?OV+>Q-7Va4gcQ^`TdrLa^S$m6bcWZSR>uPBi%XKxi
zJE0~V^4z+wZ**-qq>ZmN9`DmBoTv3!%)BA4uPav<#`cH|txQhWr+nU3u4OL%b;=z!
zoxCmKhvD8-C)fH2uDdaenlBfh$mHY*k6xCx;MPa5^WPiB_Ww+sWxAH&4&4yO=M~a<
z59<c5kKjhXFN`Lcj81VXY)N%c&6D6}yg&4@0`WXaLZ|dCm<_-j1Ac(My)PX_rFm-q
z6nf#rFxoIo<>sXGv|?CNQ1dCc@f~68-_EQ<nLHF++mtZgPp4zg#u=6OLt}iEa>po#
zi-mr~_K|dmMjwKi+!@AvKb@~~|B&E1rZN|{_8DDZU%K`hlht=y7~4oP^&Luvp0wN5
z%^X?ZGH@9s&ewMkxPu0l;U#<0`dZ_5_f8KzFOJt!3a49757Tmc=<V{JHs*LB53?Sa
z*p}{L68b5hXZ3Nye0awv!e~~YdCusqlLq3P;O2i4ILaVDeckQ8eP7pZU|bAEy4GPP
zhN4m*wo!NUPr{o^syoByo*Q^(MsTmr38T?@!DZ(2SUR8Thu{v(^*EQo&CP@1wtULN
zW%yhMu2O#&E<oR(2VZt`k<f@1!|U+n<ywK=NV%Pq8)^;(GkSg)p9jeBl$8T{h2XX=
z2&0L%Zkf3rovxeaLU4!gMBW(Ogru+GmK3fnhTHvVaL3s!vUY&3u*?qN>z%MPjL+ew
zYmq%~R6YkPx9JXi>34_mx$}&ynwXBSQn~$<+u8$fq>hX~Nx1E&+-Os9hk@H`a2eX%
zl0uf(-wN!cJIO!xGoHQ@+f+hdmCE!`X5upVy0ztF*Jsd>qucT_Hh#*?r_9O5u?e`1
zz-_X+(|I~sPOQR0=4ZK=j~SdkiF}+yxlLzKu9tF!Uatpb`YB!=uS}(R*i5<gl*1f9
zfR;1Ga;>}*+yUU$I5^LD5=r1;7T*)b@j=O1hlGK8m}9_nSv`KO5|D~}sP0Ad?Ow0n
zq_h~kGW6KiP;TsfVH^XK(ndC4ns7mI`+!?veahf!2CFO0-9gG7&-)y8nfjj}x?ioI
zMsMgF8uv6;f?Erm+p{OUexpZh^<6L>_rvRr7iW0(grVtp6XiBM0L>UbLKYV`6!D)o
zXJc9`jd?%i_N)kFKWvKE-RY1ku3__C=n<4V8NCT^!b4u4$;|2gw1M(|X|8%HH~wMx
z8Q<Yc9zR8G#sn&rd7d(BC^Nyz`1wu5^q_I5o&A*ANtq2+CfVbz_U&j*1T*uIq4lBi
z{;1r<#puQ>!`Oe9&TVE3HK<Q2*F(8Yl<RYSN@PpcfL-3+SYV&0T+5^A*oHf!GqNT)
zlod7QW!2^Z%8u_p`FaX&F>p@*&8+7T`fsbou>}6SDzv=ziQd`eXBoQ+Fy+2@?&QeL
zTn%rr@nm$UOboH=7Tl)CeBB;b(#k!|o>PE11dQO5J|-SnXp`U7R^8(#hS6LKrVW@j
zt0!{nS0M(-#y3P=zP-LvfO+l|V739H{-yMk&QbaN3!jcH1@|d)(8^@<1q8dZ_~c<<
zdBV$z0kHG4u$mLq+r0)^YU|pP!P9VJc^(4wSMXb&L?^R;B=b2l<sfd~D7b^bIoX%M
zWksK@q2MMyb>g}3ZO#H_hP9c}t|XgRjLPRs<=QX|ZlRo`-J}m$(lvcbaAQB?aXZze
z%j0eY*ZcJUPu%;**mY$2eV1a7mb1~Wm9?@Kf<a8%6GMq9^$$`Sj-yS~>~4~6HM?8g
zuSM>Xz~%ed{g&?+-+TRovces}%I*LwCz>5PE7(d}$?6XUOTYp$NfbbU2eA@QvI3$2
z14MuoU=k>a08e58nIsCJ#QA*Bsk-;R*N>E_I9P(Ot8U$@Q>RXybL!NoA2-f%b30&s
zj;nlc{>|fIJu!z@^dpYrdlGy<rrg<o^Zv9@o@?as@ieDJaevu3Y|-NEO~zr$y-D1@
zn-}*FelI8Dc)1z!_9%DoZyi7J@h_{~;>dZY<9B~~^uQDORhP<?{`T>324*JHna2z3
zw=v(Te+PesjgzPHd>`g^d(8K(H)H?j^!(EP?}H2FKC(9F{r_&>Wbc3SUHtcu7n6a)
zJfpC$Sa_Tw-%tO2bowue7SHDR7QV9>^L_ds91rJabG>|g?A)y2eg4OBKJr8kuQWPm
zSH9NYJs$Rv<n15dN1}XBymNnhI^y?%@)_L=y8M+<x(i<KKV<GWPM5p6{S)Cm`yWNQ
z$Zfo$T#WP9Dd_pZAW3%qWBS$RV>3nFb86CjO!?pYPm$Aai2en7of=(FP`(p?kM<ed
z0{vgf={k;&+Hno1!rlKY>VZPJ!Wb9xeg5~O4<*+F#eF6x1H7sK{CK$MJ=){u8J}o3
z3HHyxVTUr`BVP337yXithkT!sPx`)??__xQ=zkH%yx><V!Sp_5n>fB-*=2r68JCs3
z?c;k2mG7~C5P320>v3LGz7NUgcZ(JJ>KCKDqkNzIm(dO{(DL<MNJSUrd*i>lzx}4R
zE8ow^caeDR!^x&nN7}A3r9I^4PokY4@59UY&Z>UpdHI9LQ$?A{c`D{R`C+vCa$WM!
zFY@+G;=PZ6f9AhAexhZ%Wj)sgE2C?9%J=3+$4}fb*<H-@4RhI5n+)DRJRbI#L_5q*
z<`@^mJWqTa=WtmbQQq>XJ%aNQdEO&F;$wXyZ%>4E=f8_%SKztaq%l1!SnrZ&(O~6c
z*O%Ggzu0FkNIAc|A*bo_FS)zn6a#<lXHiZIJpJ<=cePRZdjEawvqHW?pT&Hy{13<P
zdrxu9xA+P3IMbWCzAm1j5zSQZ@PEY4w|vnb<2&%x0pon4GRZA$n*S-{n(34;VxOG~
zdEWn@8S70?o+;|pgKrcKK=Pgp`D_0R<CW|AIKTTm!c?17@9=+(YfyQcY-iJbd?4>o
z?sLldJTM!BrH!KLX5Y9`zEl4g{x|>V_rIAl_Db#`1&v8GdF&<bPWa!Wtr>XlAY$)r
zRGv@C6ZB<hqh{8w6i)(Mc^>^gA`eG-$eCDlP@Xg7xni^`=z)T7FT#5D|BSY0>|4{~
znfwXX)aOx8$G*%Jb%ZlR9@RZ*t`PH-$n(DCiE#4!U1Ofd|F3()8K<l2YyEY`1j>A2
zx~8DRKhAYc%y;&SIL;NugvGp<g@fR|LB18@d0U2AA4FK6lIM=)$z}Z^WeXe=^S%6k
zM}92iD=3qgFZq9>KRV~zmveBYn}pjn^1W~M7TWMup7A8_l<(v}fln=8M(eE8VxCvY
zbH;ci`s(~^#FOM&cz%RI|KnsT+!ayat6@G~PU@pa|8>Tuho-__qnTW6#`YRnzNx7&
zz8Bi}Zr;90@O!{N^^K|fuEz_1<@*u&t~gyXJS2uu&||(w9-hj+iyF@kkK4wA_pK9C
zU%F>Z`M&t(R9tV!>K*T2<-79BQ(+Cg(Ec%gQNEAAB%k_N`L6#nQ{gPZsi04e+ltbp
zK319cZbPGAnTo!MP$pv?)5Xg3Gx8|^B)^Afs65H9PJQXV7v<}b?<WSUFs>DRs1e@T
zKQk5P>bZ;*C+jia_sMs5+^&9n)CN+$KmN4{FQ@e+c#r<ssqo#uT!xRok@I}4_k+i#
z?rS&1e2@NfQ_=RzcwuLZ2Zi4i@_jf?mv{1v5#AHO9@{aQE+>H@cn9RWX7Hk~Ge2Yy
zVf~amz9+DtOUL9?uzvbD@@BfDkZ)|gUHPv4^HV48T3_H}4rlO>zk0MUPW%f~C$1ZA
z1s*7@l|=k@$mhQ9Jm2wxuRG>@@6S(t>H4wo`^m|v;G4{Oz;5p?=yB!y@n492meY7r
zpPl%NQ{fJP9NzeyRf2cwFMTz5L-P6Dw$R?f-1a0i6TIjC#i-Y^zRi5!ktVN`$LAdP
zZ^O^X7x*OWvvFOeI-mW^S)EzFqAnfR)xz~#e}nZV$_b}@e9i5b@iNM{PMLQp^Q@Qg
zx+dJ8rhLB;>}dA{|51_tli<HYxyPTFy6^slN##DJ+{u3_j#qjA6z8Lp%AI_L^X3o5
zZ$svMVmFWmzB@@<mG5)lzwYghHm|&4W}l72*7M7hdF@}Gn)qEey?=xEZ}DF7`20@c
zx#&}Wj65HZ|2^IZ+nDbO9{nz};QWGopWUP0=Xn3vzkwb3SKM}3;ZE=$e1p&P>C=3F
zFvYiC9~t}BD>+_!_y^zkgQ*`LzccxJ%&Kz-n6IB=oF*Qh-!42C+oJcclmA`bzZ&uv
z-#<>;yS!g~68%Da@mG5n4<CByIeo$~zI&Z_HG4PYZ1Y2W)AH#2NA)DX%XqK6@S&cI
z_2~H|@2^i!#zXI)<NeQh{{`{!^3RcWo%f&4z~^T3o@)KAZ|FO0(yscLW%!oqv-(ii
z<PT&DreHjBdMf)~xSk*7S#6E)pC~*R+ptKUPssnA-v0&B>eYvEy6O{Yd{$F9+<7=)
z@zaOyiN(>jsorOQk8!UwW#8|M&qJPL9~bcut}XJv!uu8Ci@(~sc6h9&Zm~A#-G{u3
zZ7P-(?6-OUDeqq+uIJ)=>6)ML{$PvpL7)8LL$$v(b>|yD<dc&B_VGXXr5~Jl?VAs+
z(7s8ZRvU-+9Pl3hKC=1Zl+DdA{^}Exzd>6=6ee{W<wbYFSigep_0QrD_V1XA-1?5G
z=pV@b&i%-Kq^-jBN5JhhbABk&LiGD7?}xm1JrKtjaF}129`viz)&6kism)~ZuU^|}
z4(Dd}PG1{z8^ir_zpjL|R~{ZoNGpS0a$$Ar<oxEzxu;IgKK1l$GU%o|-CngbOq#uo
z?(VR@T0a<G?Dmp!b=cgi?{o*l<YroL@xD>I)vG7FX`|Qe50g@PaARvw?=O~z<)qqe
zx67Scx>GOL>ir~5Tit58RZoXWw>Rw92lXLod*#+{Jy}1Wp5IK?HeXok)RI9ZtyXz8
zXb6#;Go%ad!myuo_d7spHkLc9Th;PlxPD_e(CdYBi}lt<{btfh`}OT~D4f<dm-gzN
z;R3Ay@N&oVT^elDsI<CsW3bzf&9gQ%tL@%$r_^lMmkz46L6VjSw6<MOE4vL9X|%Qn
zX`|a{Bx!YT*s6DuVYRn37?vv=YK!nlH%rea%}zV*K(E9)q}v(xyRE0HYU1jA$&uI`
z-Z<AC4!doYS$c74wWO9pm1egyNQB7R?r^EP)7_}|KxDVGJE+&7$grKH`_)08l9fS9
z)x&y{c7&harGvUvbH22mq^)PplpXU1u-2+WVF+d0m3H|cR<YTyzOY;GRCfkRcaRRN
z6-c{SA5{BvXv=z8jS&(0YV4)*!9usw(M#*?PJK9}V{(l9{cfKp(o?-?b{bvlti|S_
zTJA$r$k^+5VH<Cvh)pZnG;-KYd(F;vb*Emvk)-Wic#9f0>cf7yGuW(e50cXS=JV;+
z=F&#GIA59vF73(y-!v{0{6V$bt2b+GMG%1irn+joFm(3@ENR^#B&ziRB<z%XgB=i}
zubRE2SJ|!JfGyWHw>p=~y;7y6Zd+a_VYxG01y@i^n%nK(-fVhvx8A>%_N#j}qYz!N
zU)_NLtF7*!uKuib+vR2_NxPl2et`6q`?SKC)fjUfelGWEVsAi8l5}uu0N?cco&^?B
zhGxfT(WGU|or|^pl9QNj?8AY91tbsg1#$)L(i=&m*&hsdYdr_IFg)1Ymjt;G=6u~)
zL5vo5%AIXVadoGx`Y+Yn^R-%r9<l?V6ygOT691NIq;Xxl+ewVl6(vFT{ql|aE?p|#
z>DL?8?yeMx_qf1ba-Qk+MLg79XS-H!m2V}z8$(za1)#jkotV{R0CFmGlR}NMPzyql
z!XC9`eSYEjr4qD<^D6x_b1=uH;cl|LTAF=k%ZYr`h+OU0kr}n#2#V4`orz@~yN!CS
z*{@fT6q?a!mFX{-aACLKH#w(8y|f+06k*zF?w7NsWz1{{!--Z+-rtw#m!|r(-q~yR
zA=++d(A@6SYbTBBQUG0qvwy=Xcb&X2`<;_#pE~{2?8&*A+3(JrnSJKulkM#uDE!8D
zt6M3zc<gka+}VG!*4!gb1kuS7i60y(uzm8$wHattt2egylUBD&&x$cXr&q5w8_jwx
zYHAbUjnbv%bL2PeZ9Pzvc1LraUzxv<Uf5VqN{dV9wk|lQX{bn2$1ZKQd%OL5in`Yj
z;TnZ5H1)W)c^(R{mgx&4(t5v62V2)m^&#-^$<jf+D#9jPi|Y$(tE&t<(qHuhP#p@<
zdS{zWcjAkd@kLX*5`ZsArW_h7A0^sAv#K*;;!?TN5(8}1%Y!zf28u~^*T`bJd)Q0b
z)wI=QltVyKWy(&B2m=bhGx=?{yJ=^)own=k3VgKFgzf3bo2_QMIZUJ*Zo<-SBLKo$
zLmh+>by>QR5qalUYIwI0!#Qz3B4f(++}hg8()?;7mPWw~YGN$)Qnw@I({{50DjT(1
zK~0qw)|0jf;^bVoRc+M=o5M20GD>V=<2Tn!YfG!4mqc45eGe6hx(;1x4fD~^2mW=m
zbvG%aQFc$yIpFnvv#Tnt)7E;!D0U>ImzFLit!4{^2hEpw(MAew&`Bg_Ho6VE2e2<9
zhZbeXtM`$pntBYSbG~1%uZZllw!SxPmwQgbMAR{HN{26X#4)D*gU)MqnhYC~eP~y%
z-ICm&p4(EZw>Gyf0os~n%|(fIZ!}Fkdj*I=tFB>mA1(l4BkFRkRhP1CHr97;4Wx(|
zEYQ%+?X<DmsXDS54MY%eV0k~a;Tr3}Oa|8}#(kmF8C%6Zm@D+la9z4?d_>~8K{dTP
z+$c>$79_`1(M`1x;bItG>A>?QDup4u*6GeB{0aTEj3w2LMndmtT37MG7t8AW^2!q0
zdr)h_l5ncmFsA}$JN3%_ayvm*WW0!1AkAR6V(OI!ys+7Psh*?WWl&64))t;mH<lK*
zHa3@ETuMt4HmBwbQhI`n978D34rG2I>u>VTn`yb$t0SjIBGhhDX>N;`jP#vy%M6-M
z)XX>NObspQ>bfjF`e3o%D5GXer4{4ZmSi}k__^kGlMFD%*)6P#@_~9A#&nd34C<|9
zV|a<)XQY#1fr{IP29#w$ua`T!J&~YOX~McGV+aHKjPhn9Z{^moK7awMb%vCh?5Ue(
z!3?|fmtsIQJ7&43YIv_+O}G0Rp^@SXMAABz);0#&Em&{4lbg6VQ9@0Loa@}xwZ$bg
zcW3*g{ZZ3`)QQfru)5fV&2D9oRK<#BSP%Qnx=1T_6>aJMZQ0(tHnM`?dU-GackhCr
zh=aLN6<4IdY?oV%1Id60Oo1{sjh13>IpB-U?HwA!08qyGm&A04QHLoQkdy4Mn_1R7
z-|aIqfdRMCTg)uH&7B(^tbEfuP`ZIeFh$%H{m|9Bh!E-4Hk4pZ66Lr`Ox?6#^r2nN
z#wJo^LeQcP<jL47<2f&-!3FE3ZFU%Vil7vwvKLlRrOn3bu2eg`C3JJPFnwhz#cUrY
zHRR}*x6jj0gUGk&z~%EAJ=2{O%dUgQ@5+plRLMYAMQA`NgI#rv>8Tt+1~v7i<E>2K
zr@js&Cu&n8D5{iEC?A0|MX(t{kbSdYH<uP9CmM*|Xscmx8T;l<YS%lv^beMRct*n&
zIK%a(bYxlgnU(EVHTj5Yg=vUQLTm&ayp)(Z777R{nLL`OrNdzh0@+;BaSmGWhG`Nb
zAtQ!{ft7CcMzplO!_-FOsUYu0`g1KWDy@&@JY<lSOiHL*U0G$kFvhXw?yI>`)w;DA
z3>qoR7oaVpr1g4XUfIJSX?E!t6S7)&S7v~LyCra_Q|M&ErJ(@chFo3Q5NVi4z^4Oo
zpcH7SJIrhurK<0jJ7Het9V#edN_fu=AWf>7mQg1&3sV_U&lw@-G1-kmS3LMlG+SlZ
z-LHn;LDcxqyOaTk>d?k!0!ff0M7aXVEKzY+Boj34@nCa!=`YiC1GCo$%(QzA#_e59
z46poLb9g05Yfyo?1jA>R`kPi_qq>LrB4ho`Sr{Q5V&5&(R;j`cMOwyhU2HZNEV?%n
z2p?$0HU-fz3P{|=)@~BOp<O0_v}{yBq*<Gd`5L-PLPUp>NvsW>5R@BOjy5c-hE;^h
zELa-Sr<Iy$6-esH35}@RP5=4OuTd1{rNcl;lOT8>^q9pCyYsE>ZofI)VFI7p;0yeL
zhW|3AOU)Xix=fl(msk=E)Q4VlvP|IEG278z+o!ucvkY0+JkVAqAeM~e&Q<4#B+B6T
z&WY{S*wLU#H&Mej`kSuJrq-?}^Qlo_QQ0zE9Skmc4`@wK-UBzO*Pe&ZFpTS1aL`BA
zqm9I5tKN`qF>bQKFzAF!%=4So*{CA?ac=bS^yuT6(Z{Dlr(Z5NhbuB6HDT6}uoRpU
zg_&EJ!1ssJulR0Ydelb4bSa{+BTts3+ihtZayJw6OfZM<$^O#plI|iy)P!oJ`Wqg{
znlu<EB~5`^ad5J^p$YBM!BBRQc>rz>mOF{m?;zQ#nM^nbtA`-&ZUu(Ld!R{-I>@{=
zDEtDS+vEwHhj36E6)to-!bds?#{%qbyg;9jB4^R9I#d0~Qf35tN00O?y5j|-WX=t}
z6jMHJ?#LR69Ax^%hQ9@yV2dGqTH*HCK(=^Ewm5WdSL9d}g5_4Z&y2--%Z%B~<%K!M
z{0<>PqicR8Ew2F++*=jREo=s)L4^U4QAuX<+GghDFak$Y1Ws%Wd({?|?)uPVuZ>A$
z604W7g>1}g4$|sDS<G99bz3&>qb^swQ5-cEO6AjHQ`hM5TK&M>BdAwMwKZbDkP)mk
zoxo)hd10MaW8X*_qq=OmoNlei?pXDCG~@DWcO5R&j6^CSb5KYRxOWnXyE!A&V;4#*
z1W&6A6*f=SYhi$qTQnM;9nHFc5~e}!8KGqxyPb|qGBYZ&@tY11SJfEI@B`9P=kSq%
z!`N!4i)kt3gxhjMSux^Wy&(4ULq_V}Fz71l^qd?F$(q-=nXnv4YqW-XxRr5%q9RQn
zNAKr@c)IC+mu;rq{jN{Do#!(n5JICiHr$BUgSiOwT0;|7?5?~}bldhWmaFrDPqZ1|
zc{Bq~;|&y0X8=J)p%fyrYYsr8Qgcv~ijtX`8~GB6-LvL#T-5XoBcp{mjUQoX6DBJu
zgBxMGyo6Cnmt$7fCEVt@pnHOmyV$w~Hc>pK6HDrQ5U<ibowV7ryjXP8Qqj1lmzf4O
z%RbiwUbm021%nil#lgtpMt$4n@k~?d(sj(Hs!mHh@4Uh0M>?_0`*N+h-R}Th=uxwS
z9qjf!QvoO*&E0v_V7$vDKzv;3Lfss&2vf*Nbm;T&W<%bW<UHcP!e~c(2RoZ6j&6Ug
z(a`#WfH5LkV|&sfW0fX7mGdSg0e^FPIhMhc@dpW-hKj7=TH6><SAhg$n3`&{DvqKC
zGB$^z0n9JbZUcM6DJvjC+^aQo^vJRb9i#?pJ~G%3BM-?&1eNj<V`Vi-+A|MIc+WBc
zSQ{n0z&@4<x}YEWF^7bE22&zKup;wjFkX;xlH|nxdgtc=8a1o<XzTMVFwuZD7K7pF
zI327S!_3jP<rIjv-|gQ>cZbau{8}HtxpaDLxwi~jTIc6=$SsuM7ffqARb-P%DP~|F
zpI$~Yt3H2pAHE2gaW`hd0I9%WfDv%fs65^P>%;IaE_jh_*m^Q34$63~+f9UW!0ez9
zHO9mpA<I<@4~?3phn=K8+^P3zZ0cPzL;+#w@m3r~pPb)VT1r^Ia0X@aT&-j23%L0X
zv*Olp@=0W19wgJ?!vILC4bsAZ*Q_eG>#W7)HHT#kK)zJ(cM~~ZmljG(i^*^=g_PA~
zb8|tc0$n!Lun5?iA=eC%a=*`Hi2+uHx}BOPG#P%OIcl@xG(ZZ=wFcgqERS%fGL6?#
zIT}z!P;)4(EN_;UR+sT=IwWg7qxWFo&-K2n29zUR!=UDhAf>%nq}a^EXU>4lz>}p6
zgV};ip}Xj~O_ucVYq7RKtJUZ>229y!ZDEwCtv#Q#Yt8OVvV-<<Uop!BL%0pz!BdTM
zl_fPz(7jEY8qgQ}-JT5=g)}W@&d!}3cITdcI!p{jSx~7RoH>&W05_M;gm5+qH6RD|
zbi2u1@Y4JOul09!4C>s|&kVay&&~#@5k0U@N>|c_ON%UAvNmbsku6hXYpbecct8t!
zc-af(qPDhPvKATkGjnH#-PxyS&xV=|;<<jeTpNKnV3`T$eWTf6mId=ek<?a?E-fyv
zrSpr68?+-vy`@;%v|o))$~19#kw%8dT%olZZ84;=m}uDY`h|1_mv`x+6Kk+t!zVSw
z8%L{(IM70tKyWW=1q<~v+epel!ZTFT@*}={)*9$%DTv+KXRHfOhpsq%gxXKf&OwBk
zxzl6hW}FOT9JtM|T*9(RmoBZBelsc0GthU0_ma<6gdloXqXLUV2nXKDtjzhXm6an+
zfQ;Tr3u~7y&95$|2<-Xg3rXZXZ(H77Yvz!DsctLis;*aMme9fW9it6^bK1yfG0Gs~
z%2`MOdia=1%WJElO_GUO6xF2(T>#8x|7M}vgvB#w0=>pDpm%Z($t2?R+>A+Mp-H~T
zofFpxwLZ_9ar(m6{A#IC;TC2)3lfF)X9O&W_-O9~c(jRP2Se8VPc~AQO9xgXJjx0}
z%elyis_{oeDPZx}$`vgeMP@5#6qv9ICkE+XI%8ZpV}EDu@0|TTZGZjk(-wcm{(i^)
zp0&T<wZCQiTd}`_yggg9zjX;pY?cvBeSB18+b%r)17rS~!2B~XzbKH~2(W{-GRT*`
z)gqT#ZhBTLDM7dvwAjBXpKhmG51e1#m_)yf66Y5R<TKu-Db{9dvbFfTS*6v+wi;<|
zx29X0O~i3Rj4^tq=JZ0%z-($(-AG{V%TjGV<N|5h-4fL@*CwVQ3~tU5QRX)nHs(tU
z7st?l=4n*L+;;-!i$w~0X)G^#^}ECFm5>*K%M`Z@VKyYVtmg{DmCVM{1y}PL=nU~&
z!E?$$R}kM!y+|Vrw%g5S!eoWr5&VTLn(JZ$Gu->`o@nfNGN8hHRzrp?t1@Uam5_NQ
z?II6qzusazz_&@ijJ(Ga-t5*wnk@>-tZ;9waF)?0gU<^MTIIcZ(qb5qp|5b*-QEVi
zq&l_L7>wj{k9`^#e_qD2X*oysGp{@sWzS%MHai)LRwoWpfOc>bE{MNDjx}N1!IUtG
z>T8t-`n4<FR^rPea<0p=U<y<h>~z55Dkx&z>?PITmY<P%b*q{|D+#pOb^)$R3wDG{
zUVB|K#;P^9wfe-UG$?P&kVCiAbYOV>0Z5tUW=xGfCQ^!F+{S~#eyzSLW~)XWN75};
z=WYQ-ivbH5CI)X18z&@ir7|F4Ob+l%F{j(^cXzc>Be`M#Jqzq1Yq$;?mZ`?>0oI2o
z#rvdcIc<JwI3R}FJ7$0r{MqF`rWX}pn8s9ZMr>E7%PN0AIVjXPLRTRH8y1jw>Z$4C
zfALJGzTawAo@58bQ#0XVngn*r$&u!NQ+O(nu!1R<cKh0{27#=8C#0GH0UbjI5~%C6
z6?KL<JqFAM5f@zM_}|)wvj`q(TT1rv`D@ugTkR%p>tG*;?d<T~8zHLA8gu?@Xz5vY
z`;(gHXbyhz$%d@p?AdxVc5!4?rs#4#(??FQykqs;=u6Q#V@+3fo2}Y(S?U2N&GdJ_
z^YrP{v)}pd-1Pjy;%3^~?@u>-n8>~Abh+1?-tO#9pW9kqS+tmyebUMO6ibhTxhLzb
z##0AppGluN^W;818Q}Y;=ccolNBhIr9ExIVuCtWPtU((NMPbt%Yo&`z8_DAGh2>JR
zxz78=wbiBMx0W{6k_$_vOKXb?<~J@RFRqg*SzTLO*Te(s5+l|iyg1Kpl|R*XY7<B|
z0gubc`sMYtP3(2XU##z?<i*RvT2p_M4z1Mri!@!hm@cf$Z*Gz_Z$=i8>Q0rZ?;s)1
zMky&WKJokVzTq$(>Vf&8-1!aBPWULed@k7(IX9nQUSGv)8?riXX+PQ2&L68dxxBoH
zdA+%~R<f34h*Invon_GIr<IlY4P1)08^~sEf2y6pVh0-PK}cpLro91D7cBiXS=;Qe
zf7Kn>>||~9`iN9Rvr8uLTGE=32=yMMUhgUgZ1o~_)x6SBBdpTfja>6Jz<XK27Z_07
z#iVI=_vEOD&#=<WgAkUFaWgO@4_RpBpt0wE8ZU>f#&!S(7jvuw5C=g5Ft<wd{B<Zm
zG4K<Z;IF5C)lCXogTaci+Po=$s*FXeHA+5M7pTaz(~BlHSU6NWd)nlNGN%iOXmz5G
zdyF-pw25>1?AfQkE04<_&sE!+xyMwGn5e^e4?&Ux^g1gDLAxunt#Ry{K?LcHdFY!o
zZPXYOF&ij{eb0_@D^Im}aN6v1Ve4BTyQ5v*!HkeEjnezr9=km&KBzb!V%iP%oA6=6
z-rt`2fq`M6?;ElGJE1x)BWXt%e(qtnY;bmw9BRTYsL8NMe94`SiI&X=G&O_F@<}nI
zWvDmnEXmdev^s4xTDy3d`(RUUu_u8RfRPZ9y_2ev({t2O!5q_qQfz(1M+8%$w9Lk6
z{G=i)Vi1sdz`jM<Pe;XI@{6f{qfS47--B_9AUVwiM++)Ov$iOOmDpkX5j&^;l(}Dg
zlvH-v;l+Nb)c1e%aC_d|#Z9iYZ>E84nb1bl6pxU$Q$$57_UheA;CQ!3SQ_v5<v47!
zN`zF%$*UzfJj(S3Vy1<WN*8y@eu6K!J!5}o+3MvxlqhGEVe!cbld@TNhPes?!Om<q
zcu1>DNT{U6-pvLpGTOk0t&3;>yWWK6Tm_gSH@Rv&JYcUukZCbEomR2x4Z58oK;HJB
z))pBxk^uFUut4KG-~;-G`w)x$=B_pqFfn24ZLQwv_S^9HkQH;<o(v&4Yb@+9dO+;p
zDHj*#%_up{K@7vje!0bpwvCp^3ED;TI0y{JgNAz8#sYFsLVL$(2V3L(t!HMohocqZ
zg<W*Uw3NMHnR1oZ;$F8ZcRQ+-@q~?HHVUx_XkF}(Y%$2uI$Fw5r6jcRqS_diqM~;2
zJu+2{IN7Go*cbzrp=~4plLDLCq$^V6>rkBKszxtRyp3Skb~VssjnUDBb8$Co9SzR#
z#<G=%<2$uvr=p!P57^COLWd)#HojN<d>Q0G;C6-G?Py3$__V?%^aj%)s|ycyzmVN}
z19A4385AvI47)?7e{ys;25gQ1&wzY&XSc(tj;t;HCOb`b7%g_XEiKG==H{T)PkKyk
zQQAJk#w!daS-F@fsOD_b;<<L6MZo2~G!gAcGp2QeB~nneY6J++w(J6Y3<sgi4geOG
z80HLFQQ}6u-mB`UQ&z;Xn3GuDu*3G9-9CdRyL1?8AdHIF+wCrniB7AgeGL!TQIbbD
zrs$_m%eF$QM~oM~1}w=hkenEC{`fVJ(geU6mhGu*vxX!J7oyMLPj%RV@Ej`>N_He7
z;^Zhso(Y*e2!>PskV>PeMWY}dgyIftI)^EGH3#M4kV8VKFFZ^)f=GAF*Cf7bG8law
zCJ9CaRTy9tBwKD+tdzG%5v};bwRngC&-1of<i69MM?(N3!rbbH+^%Q9MdJWKjB(s|
z+A!{+j<hjww^gff=8I)amZRAtUgxM_h|OiO(^>3{h}y&pML5{sDQjE2@lGIxy`W~t
zk(oYqr&_&L0?LR7axw|=47g?X5?r$6gQK-?0mbfW5;cN*QEomHL)3y!QlK-F1}AN_
zePUpf1oj^x<kk&21i``V)gI7h?I6@JmMKvUf>*`laQ90zN5UH~kiWL|^t~>0Ei)N^
zK$){Cfh?jODQq0CGub3Z8%G|5FMUcfEnvM{0E?3)A;n~Y^~8R4=4(QfrgQvKYw6d+
zi}4g7sdmoUoUYut#hE!0c3Uzr*wT5+ET;#9E>m>cY(Ri_wBH{l#D2qSN}0f*G7wd9
zquYtC?)K~qSt@gy-L$%HD{4CYfV7dFu42}t!M?M6n**gBdu?$X&&Dhb?d>YV)S$<b
zrlRx)dR_yO4PeSZc0Cgq!}8iJE{@bSTP-kuKze|el(*xhn3lyK42q2-(~=>vC1a$l
zc?l;eBCqcmAX4vQF>9U}9Rs9!0*b(Pn`p@7tkc(Mgt<i2ik7xfs|T%GBKtd9NMa-x
zy+DgfZKt)|Fr3es;G7vx6|@Gu#~x~pan^lb14Z>Z7(Pe`IcbeHqV0nhH6o}e1~*56
zjl*7&any+9c@UUJ<Y_M|TE`;=qKXf3Y{k=B1=f`8eJ9!jp&hC)YJaU3+wi3pTjYW2
zc51^AK5YVqkJMiWhz;>V15K-`>VuGZ#Apx*4lM+0X1zSzSqbqh8Lq6lL;uzT)#L3o
zff1$_Nou?8wkFt|b8j~3PVIAlAgJ`9DOo>sAix0%Xg&xP96Kol!FZ68&O@#d)h?UB
zCM<VwP|x;GKNzs+iK82V#z>(ZQ4a>fC=#Rv7$KIOo00rDz5O7KUg*sA*Q&%$;)rC6
zmxGTi-Q^r`t$7+VrOn3XgOi*{;4I8P1@nBnTK%faI`9O!6YYgc>o<KlkOei&NDZ(x
zd^G9aj{dZC1X`{jw^0UOMBAu%TW!6hMH^xqceaCm_UI*Sw<vB?4eAGidLXC=bNX}o
z!I#)rWh*SSX~C_b`M!>(J?X6>h4ndX#OjSF**rYN1nl-ntRHCSU096kur?>V;>nTJ
zz2=}<(RRgKzp>M-;k!w;URc)ZW8U11MvIprg?7Pa{D5IF4K<&%Q{Y;<<RJue^!(PM
zgG$*APUCOR+AcKMmf<h*Kz4HJK%F2CVPa5go=LVgW8uCE_eH~9(SElTdruFR`*gy_
zOH5$lO~QVeMGjd?0ylu+0@wjyy@(PYc&+p6cf?UD-=Bm`0olaqi;<$|+>=fhXbO*d
zn`{Q9c5nhitc8QF);P_SqKw6?zYy&FdaBz8(vA7c=^RR@n=GC;B9R%NF-NtPWovaT
zQ&w(s>C&>wmN=$5pEj6K?N$H_V<~nzuOQD@SH_v-T=?TiuxT#kc<a)}>ii1$>z0y;
zS}e)o2KkAPz9<ROk?f>S0L={v0ru9aHhV3839D)~;mJmC+G!{1j-ypd8TWQ8PAsyq
zudh~{)1TAHhA`t#fzS){t81&v3$$_+?U8iPzqtG&C(`Fjbd1<DWm#T)PE_5vb@8%w
zln|Pbb7GZ65{5p_>vb3MBye0>;RGJ9hZnP7k${eMAmBJ0HWg2<fESZ#!3$VA_C?+Z
z@!`beLeCX*YsStE3IW*i=H~K+)%jJd`!CaBkuj_=&APw1#@yR=sxle1n4!9GX&pz4
zZBtIMMQKwpMHUXL1|ay=YOuV4%;z`QOuM<UnVw;Y!v8K<fVX4`-03u^fS9pF&Kk#;
z4U1x8^GJ%8$c`p{MI>1+fQ84fRONBmMGP)fFKw;32rNoH?Kg1<u`$PaW%4`NWxS2f
zC|ULZ=cUwjOqQNk!C|_4R>8Zk%JOK1&`MoCpeB8_F5G2#1WoOH5+95lr8Ox@+-~&)
z9XMy+(mbf)<@$<%L+-E4t!90(8m`HpF4|yX+-`DMH1zx0CBsH%@r|p(b4woWtms!o
zO@^M1V_9XPygvgCV`|WxyYG1XHSUnH^Afe}^0EB*1dcjd?61)$ipbl}X^@bn-T5A8
z+nM6b&iz1;9|6(96LVtbFnty)7ogG<a=5^a{E*;~;zRMA3c2%_;S`0Yu{R8s{Jy?=
z7OzpWTIC!KtvLGDr;EHU7O`nnD8gAUrvMR0Sq{sQ?BV2<D$^Y?;RK!@IXc!O$*|+L
zph6UtVP`v)gC^;g87nWt)SttRYD#5~b=Y)i3t_gZWCi6aEg~-e4R{won>UoXW{uM!
z;m{PoSklloDuWg)z>s3ekKJ*Q6KChv0(WIC+x{cv0DB{}LDxfAZQ@`lW{KbA#lcNB
zIdCpfRItrK3@M=;Gvc--RePM?>yLvE{$ABh4Lv&^Kk#Me><Lz?B|Y{pb0Th;9rn5<
zAY|;<ZgG7Yi%xccTsX1%s$+eroz2iu6P=w?!ZLeaxP)Lu%qlpf#_H^ps>9aKp9oz1
zLmo&&@pue$1olSVmWp~qyG<wE9QIe39fVVa>!590?Nvne8A_pkODMvm>;isL@|N(T
zm$X(~=m}_xV_L4-9!*wtB8u&dql7gYSHlhNKVvZ~wq7k)b=FojVc}e%*|VYfb2<cd
zpg*eIKyCSoZ6FV+hPm#_*u*M`;3IKI+DIMN!k+x0<h)dGTeEuHO-GIVo#QV^I`9!-
zPR$IQp|V=v$1M{){+t8k40Vs~s(If*4g*`n^1>LFbh|22<1cZM9d+9!ZJTy!gcyqr
zPM$^RvWB^~`C{1HLa{~jvh;M^R@-H{@XSu$^5#4q3Zp0@#ASrsah1zXIHgOEg^VJX
zBcfv5+Q;4qKjAs=hrj$`UF((M<Yz{3m008miD^s2wWn)m#JBOPL}l@_+sTlc26psX
zTbaBJj=loaKp>SlXIfO?W+SF_KU=9oc5!hsFsX79*m>uGEAId$Fm}I(pvZ9C?ROHz
zbv1`>lyWTrMev5Ze#kCgaZDh)6NEGVd6v~JofsB~dOPs&>N&qwVji`|8(xGquWj;X
zQ$ABmUFWdxXlDRd(qk>_X!*)Bs{S62Je|jj6{K@jaa0Z(Jj2vk|B|*xIIb)^u-d_U
zB^jB<YE-)Qzvu9dUDE}a>nbUFC`(2Wdw@mehxQ&Ow5v6tNuJHcCK5SRF4hp4wn|G^
zqDHnlGve4&#%K1lZnq-7V2E>riumrlmfFVXcGFt$Lgd#MR2N(FBhpq*m2*F*>Dd?Z
zT1;WD+VxrJXq-Q=rDcscTH!U838_Cr)i9c8V~{1E*H$o*D%8ln_MAaBx#cj*4spkE
zv=hi}4dAs?iAWGJ#bDrA6_4J<L^5PT9uSoHhGgl>ltmqewpIgTs9{bId&4r1R)PX|
zsGKyXGrFF@Ll>Qn;wc!0sB(BcOAI{H%2t(Do}AqRh=5X5%9c?zJEohvxaAPsfHwzT
zw(EhZG`w)S{Nkm}ONq|<t4l)K23Jp_#r!!SOm2~dz27h)Yt()ObR2tffxWi1cl)y%
zmN@Y)(<8ClKO3y_+DyGdbvhEu?sHTVbAq0o_w;h7gQ;USruOHT@q)2+oP+viE(SYP
z2Va``q4VM?^$4d>zf2ezkL=OG9gLzkb>|s<jYT<h!3HqhPGUu0hr-#$5*j4L!roMt
z`Ft0wyo42*Y|(mhkeX&@ZSS)EkhAM3U|3kygd<q7tQ{@&x4z2esu*XuHjqQJaNb5m
zZw`7*tBZ@LxYfeU=lsl;9R}iLk1d<A%gT?%usw(Ur;w{a<k`F}ctLeRTH6dl@0n0x
zjs1<=M)yF0GkGaa>)DYxzjhLR0YV|yT%JpZ7W+*G`amw4Q0P(C|HTnppr#vo?(xoc
z>Bw@_q?hvqJNxk@WjL%BYJIv$a*=BH8IIZ-C(adLWz;ahp5f_0V(mLPV27Bv)32n<
za@!GCKbXk@LzV>-!%4zb?;uy4p262=r_oJ1XtJm!qH=|;9emWyR61kLa%s1tBjiC$
zVlM5Na$X$ZWrm@28=G3<x8F7CLO{@dooN&HE?TiCayE!3O;uJ?hse?e(wi{BqdJ8<
z(kJ-~<V=Od*n!!W7um6xb!dSiv`-X~_aEb^z^*o5YsERDfy4aw44?%w^mld7Q|zZm
z3SnLp8{=~$c%fE|uqYwcmnsxQOS8(nYlF~Q-?F=QQj1l9&S9Sz`%1HW5*!2@Ne{qT
zM-J&a6V5=hNcv_&C;UtvYyx7K8ct9~B~`UkN3cvc7;&Mfu#S2M-RXL45a(TmE^}!a
zXg`9=1g#iTy_3f}EbtHDt8D*_Y;d$FM|cG?s1Jr#l;y6Lo&2yQ>}L8K2%Ph#9a`9k
z1#~7<cYLs2!ufH1VKZGQt+20%E7N9@kw;v@p&k|ERHsfWXO(R3Gx9LV#5~*J0q(jI
z&bRiIH~_qU@i$XDQa(E~Gjnd9loHi#tfb6?&vWGb#jLohVDQl$G1?>w580iP$^1%*
zJB*f6U~R1F4lkTH3u_ykQ!1s4OXrtYxf=o0(8w%HWi%-rT(<oV5xIaEl_Wj&pM=sl
zJ!c;svV^IG2g*30ku0vCJ$?4fS+?BiprT}O*R?{1cmN%EInevki)YU+&CZ^AI$hgZ
z&aw)&x=V*RQ5Z(^?4?lBOHa)J*cB1lqMGmA93kw|m6DxT+S*JDG`7>E28sO|x|@&n
zYi;Lm^_0u?5!}uVaE)XH99^Ou-c@Ik^`-OQnfcD_(bgLkMNVyxolE<JJzc75%@P`z
z;WWpOW*2zX4m3ud<nrIWI$LVQSa#ku@9Nbx<C=hO#FyJ=*aMyCT3&r|euXOuIFtqx
z#I6>R_t_wkv3PtT1{GG0g!5=dX6{gZu>cwb#JYjyjITmJ`$!XE#vU!#_Cz-Aa>wH1
zI8vfFk(a%Uk*s*m*l1+fWXR`yno}ua>`)}3++e^yI(EWo7yCU>nHlX@bxKkG#2_Q`
z7ugsom<%z=X~iM6r4`&%1!fAoR4f`>Kc<30MFm2{rpCh7NpzOj3k95w5?tq@`*Dle
zjKeY+m8|)Nu+f5LI4@@B;9j@d)WJl-9%1|ffpq+DYcnVcJAgl$)!(PN<XLB%y7fL9
zql~d_lq5!IRzM>$XSq7qba%>JAQ#h!vzVx;#$9|fc`)&{)<5%f>YWm`8y7`#&BrL-
zIl@I%Ax#|RJXd!PZ4?hoZPwZ`Wb7C^BMzgpj;#7LD&~!PY(&Y8P-J+fAZe^xt*$XB
ztX*1PS>iZm5loa+DrOoW3zD(fm4+yzdj?D`1HJ5P{YlT5Mnk`5GMod}vUxqbzbQhG
zy1@9ytYQuPBMiY!9;J=7m2`dWvOa#Wc6l|cTpG)d=#P{*!b0f^t5#9aGA@;-87UWQ
zGCh`F+B`>VwXn_*;ltDYvagVxHaA(jjiVozVfg6h%n&@<dMm1_=_7s9KUl<0%!Yn?
zH`s(DNERBW0UQ+NF$!+)kzwUb)`v$$eY7P((C$@FkTZxl(ONJ?8+B|}r<z!>BeL{>
zi%eoWco4-#y%D)WW#iDHx#tLC0UPLGdi07RmC>A$`@*H=Wii_bxX7PTTaL=^{VT9R
zT;uDkkFS~av3*oigyyN`L|rT<s+6c)M_6D4k6cZR5@5tMxMGZ*HC0fHifRO4<nN6o
zXt+^Ixn93W@n~v|l#ywOHO5`^J#=_B3PeR^!*$dJ634z-5OQ;3Inu>CNg@-#S%LXN
zvBuabap1{K3Lp0i>PZQ@+v)t;*6QLYJ!Bv(FV0R%oXhpQ8Gs{AE09AsTp^ZDJ#Gus
zwMWaC?Q?GVjM{0j1@v#6l$nvEkyJk8IKpTYELf}7^0Q<7H(|IoRcM-Ita2N^Miuy+
zn_|Xb{wauPmM~ws)u|q-&0tKV!r~Ts|H?@Bptju~(;21h7z5hCrMa4oI5zWO?ryqF
zqlHV$D1<Q?E}hXCd-`$Ht}K_jynp^V7y1!?(alfn$Qd<4gE$&yJ_C#WoX^d~-!{t|
zq02amb1rCF@ZcIP8{aaWm(AApu?IC5)94r9`bw;-Ee>|nsACtJ6lgdNHr?#32~>f@
zG>wb8GKxv)V+IJ@VHF<PILIB~Lm0$5F`EZ*Gl#B|6cBeR-EX!$kS8)WN6ZptwA<`<
z*5J-TBWs&6X=HS_QKBL*PP8KVoo2CFB95K&wCPOl<>WkuzGh;hrB&d}9;DAFN#p!)
zrq@or)!SnmsVWHVF1R^hz#}AxP2>z}y>DAq@*eQ!j4(q~70a7zE4r&<<YnNLmF3mv
z!wfKpT}0gN&M?83C!^J?+!%%7BIOf<F_kWAMOVSS21AUu%y83eCbJ)9lAwA=E8AGQ
zB()xCz=8UfTv~y&*~n;UOSN!&5GPR0%Zn#tf>R+Msd9rhjLZ34G@q7Q&CH!(;Ak$6
z5HwJG6zR!z*wCEM-v){Mf@!kZocSB;ixKT+_7}o3QZ<C6qAZ{EhEEJfEGzbMXa*cr
zNqOU714}o1Mgv3>WCVDoQo;n#6z52eQ8uvmL99m6jQqI59WUqDe>wU#)I(e5&n>Sk
zbHkq6VQUDn&mn!#?h}j7#yP6dcLc>)wJ5bZFDGr#hzMW7?`9rRbN#XH<=*Z&%hss5
zcW%76_oZ)}8Gq;dVJ5$eF1ztE{R2FG>f7-b2FyBL?khb0tRhdyrqW;16jdEujRvX;
z2`2kahlUIby<9EzWl%-O0Cm84V2e}Ib&hT3WZl;Z#c-GG1oQ>v%W5)`-={a^Sn<nh
zb%nC59pPc?E37v)ap7_=gJyj}4*T1ziRnH{f97zbhR1-rUxdsha}?Re-Oc6^9|AaP
z=m2u)1&6w|!>XkHz_6hrIGt6}e9aU3$!;#@7BgJ{f_JaDB1DUE#cQQ4VCcKO?}vre
z;<d)vp%ErR$mmkQ+=wu-O->%CZ19}uQz>j|F;51R38q+3Y>uX#<;O`HPx(4Jni5i$
z2@sr-O}{7MgB)O%c&*q6VbyU`PAN;Hv!5H)`ePWav)nz_*7!hVKXkqOZnsShvlW0Z
ztK?g=B!A;;awfDBdd;;<;QlbUM|QDej9N%6uCTc4$5uRy6YaQQi!D!FRL25jFh_-U
zfHuKC;E)Q|v-|Ji3hT0v8xsq%vTl_dRAy@DnXT61a#*1*n8Dp}GSwVTo67*SK2QKy
ztS>K7Fln;F6r(U8a%}kYA)~Z2RH5znN1{-?kkNr;l@&5s8^b8e)gs%YOSD-dGty3K
zq``n1tbTD59?Zk;FD}Z(GDNZI4ja|ys{;j`CQ+e)SRO?LYz>Z0u64E>Oa?&{@}98z
zq(I`*Tj=t<3&z?rO81akRIx?Wn|85hR1SsuC&0_mE+TqwM6y1a!~hekD$p%!#pGIZ
z^a^FN3Mchs_EG@N70C_&ZfyxYP;62TJS*f7M``Jt7nq~ao~%%g`h8?Iuk79}8LhWa
zRiOxDmbk?4A5YofuInvXQpPwA+k5?b*ogJf`9=ZmM5MAVnM902;VfUF{STt5id_LL
z_J$OiX*a`&=WNg@W|ie*7tO0$5di(C8$PwYu+Z3Ik-V8%mPx$Y?{>M6LAwJbH>2kJ
z5yeu#Rb9gIN0Zh2^hl0Hv24V75<(-cE62dQ^&T31G8K(mj94baTo!S|@1sD+6}odG
zdJ}k@AwBn`W8mzM5lSfqum$G0_dqtW?yRqz4<S$v>mD`Sll>-BMxB-uhAq{-vhUZa
z@;MtLe$EXU%kkj>{D_4X+NT)`U8=%`*Kr0AhxkHHY5c5}hDg--^6;K^4=+|Cy8uR6
zA<}qchecqGxV>R?`$c9EQJ<EpJ#&x6FI=e;Or0WR3?8@UY#WZg+U4ZTEod20#S%Vj
znf2p`aO@@@-J!0H6-J$r>|&|VMC}vG0gpm0+KAE440&zC2Gp~51$56u11nhay29PA
z3yvRiP%n+(F-|1_ZsTRpN7TMFuOk;IsyTVIN}YDLyGgV=0?1K5lAM{jUfwq2seA*5
z8fb64r=O0E1i+DQFy6CWNz!Oq`HBQEdIj1A<41gvu#1fQ;Hs&vZs+oUjs~o_&jnvm
zE`GuB5;I@AIKO$(vN8%~AeKs`X&GK)Q=Ymyk7LG?*m1L?orPL1ls72@H-BMyK{NW1
zf}5A|M{X{aMiL{MYyjD`7of@JDUNqUU;;yZ<~NFI3#;sI(S7*ibu4V))xSK7u$*jo
zv;rBHO6NA#<`);{H%nO+fSZ6Cs|5bV1Fno+;#jI-U~Zb?0Bt=K@#5<5h!GzN*EM*v
z&*+;Lp-(O@X0KyXMA(3H(T2_hTl>d)NRT&Jv0UC<Ffuh8x(_>SGee1UolXRK1;_P;
zrPUEKkGG}Rq3iQPYm~s3=bvBNS~n0qJ|%7+9^vy6SskIFhBf*y|3*hdV(H4l5?}lf
z*^6~WACo0UmzO^I$M;>>qZR1n-x(P1$H*$;6tDOOdLiLsx4Y%mqSVr8c}`ERZ7hvc
ze`W3bd83V$kJ&?GEzPd7F~`G*xQw#o=E~C2x^-nJV}cv^pBYE=5Aty-)>G)i`HjT_
zKS^TkOZPay?kS^Al+Y-v*HnOSFcm3x_HzPktX*2><V|1#=T{#%aIzi64AP2kN2tO!
znE=C*V`mA9w&MwiJ1Gr%iO*1QrU+JO!I*N>q%cl~P$v5Z3mMlDK5b@Zr6+Fd2p6pc
z9vBhv90PBPDZCNM%NQ%q3RUep_Z`k^Lmu-u#I6WDFV>6=8v&Ow$_VpDMG}kIdgQ2V
zTlKM)$g$GFML>bvN>Z)*6qSG9T>Knne#Q!XAI%9JA?7N1q@sefSvs3oIrI|?UCPw4
z7lJURF!}`*#oj#plv#;vJn#~c>hiZ4y)0qF`#cuPrFNu{SegrU?Gt9csggD`FP~;N
zZQSpOffAua?PV~GQ+<sfzRz{F*AmE|i=?Q^?e6w5(7<K{xAdU|QCl_ZA_xuF{^+s?
z3ifp`p9Dx7g|}djS23*WO$I;~it`0EcNb00B%W2Si71!}!CO9I8Gx`mPy&QfAx64B
zW|8O<z?|H$ZM(Qgu^@2D?KRn;&lx05VuUwwl{5-yZz@7|gBcN!kxGs_VSljwxdm;d
z*jeDiAZ~HfF;fMV<8eq;ypi;HK0T%EjdoOe8uXPCLaWIVY%45?up3tx_jJE1wXpSG
zqEcu&m*0afFlcj?&p`EYL*spF^G)+k0K%sYZy8W)q}<fzA*R}WU1%yafiE=JyUs3{
zkb(PK)rwHB-t(PMwtDli2I{xwaoMEW%$K;>b?-C?wQ3u*+?-Ao##G3UDZ-449cuk_
z2QroWTph;sp5dE>M0#z$V5*d!eYZ95Um9t{G;QRX=_Z%FDp&YCS#wa)cbqJ#VbfK;
z<SWJ6qpq0keO0WLy;T=^O*;Grzun;WGQkr|kkJb_v<A#e?9a+A#raT$0_NIuI^CeJ
z7c0@noMvwh8Pca{SeRR-??fd|XLBJnC&kI;!@_9iHG90ET^)nL$rZZT<`k?yjOVm;
z^6Hz?=}x!HH^h4FsxBa=2<U8MJu>X_iZ3aL6*9otC#b1K15OjUQ8w-?w8rwSLTi(K
zO`I2dbK0Ym?r}MVe=`&?AjEw*&4xMY`QnJaC|_kmYxoj4pEu_Cl<u<S)~w`!<2GC!
zr&3OB)mCAe%-oP|r}BRr0(<P*sf)}yVao|ECFYgiyHYP47B$97shWG21jPZfMT7#`
z5LPB0d}poCN=Nv<Xjj<VOD+iBtNSvLJ^wb}56K@RrnBtr4XqGKaG5w%hVPqrK^TOr
zFo*%zsiuUzS*P+Ws~!b{+N-PsBH)ZXDLod^GxOG9+meFCjNdGV+=>ynN>I$9&Iv*g
zJ0rrjezYP-+cpRO&_I**LLa$iRFRAZM;qa$O)=9PLZnY~wvJ{-f1osM?gsY<3?W@k
zE@NswjGXcG2nmn0B|~hibE-Po!V#9xMTVYtMC5homJ`<b*%({qMX|-B(lLSn`5i=2
zd$p_6*05?@Up19t^@ci~D6%`?0?(WJylr@+tHm=;jSZqbTtv^cvN#C2Jd|s$`66xs
zuaO?hx;B&^Z{r}!LB^$iQ*u_$L1&y=Y$Yo^M@VTxKElo|ogWc&KIGli?Wnv(PumEs
zk15*wq%y$sLpF|KD2lFSw-H~eV7P7SXtZBjW%&ih;PK^Yh05RT%E{zFhSK1?i-7cK
zfb_cTrz)kCva-_29qvI-I)blUT%)>Y*iyAdTC2iFnows!C({Ld`>!%h9@Rw8DmM*?
zXtZ?UOx2~<{>FxC9aAGsW<y0#mJ2|dbuO<VxRMM`70LJ*;sUmvZ1x4GzV5<qbC~~v
z<f>UEH}^*RIc1G*cB<Tp>$AEVevvco`{ig8gYdTYBWkA;c8Hz-LT_<`QLixYd9QJZ
zgNpE1NAD+~%1UDV_LVNI=X!kujG+y(8eQn{VOU(mJ`MZ+MON<C_Tz*7?G>%*G<!@6
zb;&mLU}2ThC3a2`kEE<5rvdo;2VXSY3c7vEp7TxqIrs210nLy>VrL(JH_Yr4*9OMF
zcI}^pFD-Cw7FLU$rRB5G3>RFs9jr)It8u;beCh{KU$E2e;cDi63`2%_JA}-Kx77L!
zKoar*K4ioAU+!?J@1z%b1si^HbwZo;#boZ)*SANqT1=^lUXCDrpwBJqmI0e)3U~EE
z*Gf1ZdV9-O;RGe%=7u+gsyF!Xo4&@%$GB~P=Keu_3Z0E$Xeym`)vVc04oaTrLmQp2
zHF3Pi>fk;CZG^L2g+@TgX_W@~@zfjK)Xt#An_f8Kg+k^ITpWe^@Ru|sFJz?ZTpRDW
za^Z$p%yu{=ZOUTGlO%_sCd5cje^73)n9d!~!cuH%4=5tdzR7D<+Q}3KP4PO*;^FO0
zdAgIEY>*#ERVT=?c5a%-PK<doxhZu~Y>_@UHC-NXhl&XE)TSMh+v=EgXqfVi6s`{e
z541l%KMX+F8VJMWMrDV;Zlf`T+n14b94@SvTSi1hd{+F7Zk%cPhnB4VO1~DR^hO13
zDd;s5b<Ve!);FmNvzS%}U~W}X)g>{zcmkc(_K5QVzEdv8Cb8V(LnL_4^l3N~jlj;_
zhoNP;WNUSWuhgci_$l#Lu5E2BEcxvYY+5#;M~KzsY;S*9?Lu6*N9Xc9XQ-)d*TmRX
z8%PbGuP$9K&2K)>RHJR{0z(}S^^YHGvrrl<!diFBvs3LE_v|$WTpNQu2*cGAJ=w|y
z5!)w=SB5PU%!7RDXZtI8r-OHBoNCWm#=LdRXQ-0zH*3^@(j9UXCd5W>GWvOX<Q}VD
z)d`eEY@v;{mK{|IA2EH`M3p_=X~VtY))Et6FOIR`cUcII581U_9lqsk*olD1xxV;j
z_FsR<eAF84TkSfIygyKf&s;o*>Kt<9OcEd#vFmzm-UY(?{D?C6`a~ds%@<V#x&fxN
z76mH;N2Gmd@I@U;JSrC&pY+W&x?1fJu|o^E6<K7a9%ePV{DMmD!esU=!Z%83?wBwS
zm|*g~K>K7v(yq8fGb~l&r+uaCbjeJIFKf%S&H)`DFo<$_r(KWf83vr8*PuoFs(b0a
z+^11r=&&Ydg*4G;mOC`<X|tbhSMEX$_&2pj$+f0c*M_8Mz2HsUVUEotARp<;GtDjX
zRn6BeKdsos%(3ob(E;NyVXUsPAdxU)l(;N#lMm}^G(!EU1PVhr^yrN?ba^n%$ahy#
zwbk~HS_N=J4JGWg>GKgaKJ(0BP|=14qv+*Aw6=E;TTAbXg%}Dgn;AvkoAwfnX%w8y
z5M+HUY;4BNYg@*^PK{$AQ-=<pnnBP6x#{m!HCk2Gw#7p?xwx`Ur;`KD#D=5s>I=>d
zTABlErcFehgHF;e!zNci89HPXvCHsoU&K}x(6^FSI{@?MT3fB0_@Y1x(9|b|GnmSl
z!PH<vJ!~cw>LQ{T#s^ajacItt>{ySzM=NlZES#F7($#5=NK?5-oO)E8R>gI4Z6HXs
zU9W}t@&NNFtH^qb2EvFHtic^DTF3``vmFi3kXGirU2=f4hA1X;g|8a2uJtZA?zQZ^
z?AH&tv&$(%*F{E4U*dp>XveaG98VGe_7=oajtBBaLf+e=Dz-fSA1Z}x`toX46mrNp
zY7oG~xG2!n(HeHU?Oi^M)u!uz+d%B<>(3&((P4L}9#eu~dz-bpjTIcrM5QAw^EOed
zvnLBLL&huPE%-O$fz>;t{{jI33=8?oHq>oq!W<+f%Nm|TajUp3+rvy|wVyg%d6-cY
zt23^0#cN5fF=TPe;FS{vfkBP~cyAD17WK2zB+%-69+)lmx_dJ8_;`@}xprjd@G2cL
zFOp|gzBIyaMVI;WX&SAVJM1CD5t;#JQGR;BLUFfImU)9FDin6mUI=M3Z-&G0Sye7x
zLDEHNzj;);0jGtRh0luooUvZsXCMK1$v?az*E`G7-AbrmYDEVMgzX47dN)DA9aj#b
z{eFvUYc1sHpU9?m1=-PKLG-EA#h2O!)L|7!mAFa`$XlinOj#>bKX64&U_W(|K5A<9
zBGHjzd{PK!q?8D6B<ku2*^5wzkM&6M_2hEKioy*T#~%i`ox~AiBM2|Ul+&{X|G}`U
z&L7LGjJlqM0Y|!3_B0>MVV+CC=atmI@NAs3`tWT&Cy23w!0F~tP{-U(bmuh=JYE2k
zxvi8Keo&qZ0Bpe3be<vJcrk*vskjU~hY=>^0%a3UL&Ne!_(4X1t|5eKve~&(1bcDq
z()==~EVQib?Z})51GJzi)w12YH0W{?2l47QDr}8{;?{IB#U>8A?0N~>OA{9^3gLDj
zGSW8r6b9%*U8^nk%|PDuZ1PSo^8s2B1QH7f2YY0|cKdUFu?m>#1kC_*xmxFgWW>S_
z^hT5GSs?4s+CAvf5nfkBL@j5eNy?U?#U2gG1{cq25(GfMTVCu0YzZr%Z2^=$7fiC~
zoVFLxh9?NdW%RlUf?V8{EduFNUwkUVho%UFp%6cI#qJOsR7~Y^8zW8{eKajxJt4ye
z`wPwzBF#ZgJvXEbf}`gkyf+XQwN1ElCX3U`RyZ`5lB1yH;Zn^ZXF$^&%iaV;H?$zk
zX$Re#Y=*|u1haGKcTmB%#1qesMQkD%hf2K;CjgmbW>TSObd!ZOL7Ldty2!Q3wVkks
zg;nm@V^+#D!#?Sl1-yX`v|^xb*VRg=%X-eOqu|{AC4*3<B|7^%aF>CBBNA?E*MJI(
z={+QO1s}l0bd`gv$tj(|z;H$*b6aP;2Lr8fjWvUpj1H<*-&tVdYgVoX3%*G<<f|nx
zOz#=i8_{yIt!&6?I{$RI4ke6LU0D{aLrY%@<N%-Xu&JobieWI%P20NC;C?RKxC6W}
z@(4#2#pVw&S9(g5WfB~=!>)0nQhRJF%7t0UaJwmCEa!r8?_Q^YHA4F+#YqgWU2{r^
z{ke_H)xA+bpuM!{!B4V-Pu8<gG}vUm>nqqvanLqtO3K^Xax;O{petIdhTWl4vBJEx
zfGlIzKJV27<Z?0IH7A@?z>?uduHdpL<3dD13S83zt!kJB4uFhUG@3iJe2~wk1`{x3
zk*Y7I?pcqj^O9k2TermvAE_ahrxeYWQ4CLW1&6n)6A#0HLU6@|I>@IwRFF9tOUsio
zF`AJFP3Ji0n#IcT)@b9yE3=_6afo9evkZATj#e%k5V$f(L*891Z}VD_cE$!ZQ!ONG
zaLE#FAmItmCGy^9w$FoUu`G*?CcMSGwYS<Api!I*n$e9RL#m`UAQQ)U4whvL>XqFA
z8+qk_BvbVk--N{OV*$;!8}Rv1i@2*H&x!<VF?!?{T_Y7R<dkrhQmnY4e<XYHMJUCZ
zJiFytR?K(j#iY@qwsvpOb+fVUSPu7m6<emV#h28=r^HKZ8*H3eOj9|4nWA$m6JNPS
zm|3ap!ge9c%JOE3JR|Tz7T{ncco{`T$p9crR4%-G5q`R;iUZWtpB#;16;k4IN)^*=
z?ccX6sLAosoj>@`3KxfI+bSurv3Zi%-6Io;TQV_`w0DBnB*oJ+8HAX>SZlK>?`SNQ
zRpaL<REa)K&zNdC0BYY5J(AsDkJmd^&j?afs#D#|8!vFgdv$STX(OUJLKLpeVs65w
zf~o|~>djM7n)WeKh^8n+wf!ta86B0V{O$-Ey$D+EvJDsbPz@%}nn-Klj?dg$he6mM
z#fE$#JzygTI2T{t@`d=329uYmh5S*)WT8V6J=btylXD8$v!Sb)(FYo`+E;urob};e
zA?GhffTFjx;1O~1C(CTkwIWz0gnYsL(tYKlIm{{}nS7%!@X)eQ$2OfDM4n{zm0S2P
zxf@S+;_=lyeP@*$BC@+2i{LcF5152fSgJV?i@8{1e(77IYP`7x6v?&`ncZ51JMzXV
z@Xw~3qi>|BU#mUR#;mZvqqr<EnF6EI&w`U{QoaJiUSS49{0SL`u30@@Yg1$$sU_P|
zL_=H$78;<9#&TrZ0{5H*-Klgm-F-2!DA&Kr{a=Qs{pRkA3>fD)aH+etml?qHyu_&O
zt4*838%hjMewnIrgaqziEj(@R7atfQ3y;f)NqqFXv%}M-&YhHS`orD0UYqUSE`DoG
zOK~|`Js1EbxWMxBp_w*su{5y^GirrK*$NJ8wb)Gz0J=tz$z!eF-aTM7j}<jGKkUlK
z%LgN{JyivM_pr(-513u<iAN1~w3RuhTwx4lHmkvWz}_>DKy&#;btjNQPOizigq7{P
z)$UcZb$Lv|dLzuo;FVyuOaiS}SZdM;@^Q)f(Iz2w3fFC!hIV6AN3#f)i)L!fElX2a
zrn7Xl+`CNUZQhR^(T3aDfsS}{GMA}`{QKBeTBH;Hcrx<oWo+X#%XL~OHiWXtr$odv
z<IL|2HOn^=3Sqw1!^ekZV?k88clxz$d_SEoU+5N@H4^T2Nadp+g$lLXiq{bm{eV>?
z%TM$6el0BY$)y!i%)7-4o7czJ9j<8^`r@B;DXVKTs`v(mmJP?MQ)TeToP1z%bjjI3
z)K--VP3mYSH1B946H=7j++8HJZ?X4k2LkV_EbO^$zAM(mp}Q?eQl$aKV-my|fZ6h3
z1{C8}w|MS!d-#tu%4iQ4vvd-a2b-N`C|266W|pe$LQJL#Y8+KtCTPuNQcRZTw7?E)
zm|o&7eJ*bpCc3f%&ZUC<xVpw^V(%b~Y<AoD<32i>sJ_UW^N6~Ptzcw!yOZzJ`<6Iu
z!ZI-fI+e9NUf)Bmw4$K(C=*Fv<~f2wFqvtAZ6X6<Q7^cp{K3}A*odHUhC4^qwkDg|
zkh2z+2<CvAsZwrz+6Y6o@y3!v4Ch&KH%VahwY!^vP=a8CN66yu!F^Aa+9D(&(_cSo
z<6ByBxM@PnaBt{&wvm)0Xoy=t#550uIIOJ?-5WSslsY%TW%%>tbiv-zp*xtQKa^9_
z?F$~_1OWPHg$|sFM!Jou0M+%vidG+6&?XJe7rdmC7zB7PVO982o$Z!-kr7D`PL5s8
zD&RJ;aNjb81hNeFwZFriss!?%Du>7`08U%mSQY!Xh-cWr1gi34YDQ_AFKj<T$J{tm
z*qo#pvu{k&8}XUzN%mmqW9+;(Y3X;_4$KBTv}(SwiI;GP?P?N|mV-$z+igRlb068v
zr!kt*Hz|!WS3rHv*$Z4Wq1VUpl4UlpbFhc+@32U{&h9I1VnoN-i4gd#ZF{nuHd&z&
zjuC7vCJHvCO}cCfNonTfSs_V}P2F~pOeU<jGEuyPa#+t?V0BgF=wP^FTNnnzORCy#
zub1;E)Akbb=?H^Lt0g9v@fqZ$;gmEOmT*ySzzQhEH3lAnW!$*j>uffrB5umy@1kzi
z!IlX=YohJ2d3|wTlD|>!^C?OAkn&*_S_ZNCCjCul5Gsq|ol0!wRuPweGoQ`0Q<^U}
z6M<9$9TwedT@8ReBykcdwneFFqf_sU(HeUWMZ+*Ctx_MJdB%61n&llIY<y;`7a}mk
zNHFiL<;MKr;#c2Uh3(}Vplr+3K#Bs6#iyoiQ1CFkBZZi--$|RsEX^?J)XV*Ic#PO+
zAVrOOFnxWLj`%&y;Q%Fx+DJ$!Vc_G3whKz05%)>heq=r)i%2IdEa1D<ANd_jU`_89
zx(WoRCCFjQqNvl{l;1v{0T7lKvc?8(^ScoD`2oE=VsU`OwC4rSjy5PK2fm-03odPA
zo&j>5Bgp3Q_7cJGfsjV%Y-JI2RSoW19E^x$E?6Z%Ts76D$M<m`gnign);uhpPd@%Y
zcTRh=wZ}LLs_Q`)L+l0Sw6%WQUC|uaz5;D+aAm&N;B(N_n~4_N5T^NwLuK=^j|4HI
z)AwvANX9X6fwmyPv7>MH8m@yQ3Ohr_gM4?#o{L+YItFy&BgkmEfUOXwha-%=AT^K;
zjbW5`Y{)2&pSDi$wP^x%dJfF`J%2Qb-^1mI;08QYGFS>>GP{S1iJj1F+QK&A>YJun
zD1nf+02t=xwmV}_5}ViHZvMT7dHw7i6_|AIg<1n~n5Aoa#-=SKF~b3)MPE*^tsO@?
zB$yy(rBEW9Ysm1;K507QA22(3Bww_Q<K#<a&10k9rn5($?MeNM6W^?!Vku7#Mf@S*
zlarfsTu`;Jv|iHJCpWj&mo{GHQnHP7ZFPlP5LY)#M=~ufEU+!=0{$$nPqmA?IhA-M
z*Ye8B(gnUMX&{PtFt0KvmS#NTRHz;SqsmGv=XCJ#$UDB6sk>z_E%BXBeXVl>u6)>W
zc~dQ;{Mu0n3-eptK(1?Q*L5s)wPX~`vBFx=P0ZtD;!GU(Q(xeQa{G3Q9kM-=NtiFr
zm*yv;t|o0Pap)3yUrJwG)-7<Lc?8JDQfX^rm8^UTa!WU)(?(W@OofcHQMIg1kN3fp
z8#*trp>2KPNT$-p{Q6|_U0UC=7uMfU@!p6kr?pm`ao?Px%lW0!!o_<M2J&tmMN&*~
zWod!0>U>3_Z9cyonl*t^=}}sZGru)QX4Vm0?8C4dTkDhA1<*MM^@20;-b_Ena@LPn
zU^;SO270)s;Rq6Tj`~Qd80+%J@|P1SW6y<o)}XzNZho^~5y2+QY4lc(Gui_EZz{vk
zf?r<P;!@Zn=#A4@4DI5>_mab%U8cHZKj)uneCnxb{_DsdLnRy6pFI84>{B!0L7yA0
zPUDQ#j&^8<!HSmSn|C--4$2<Usty*WC3+U(9tqAB?XF`J0-sv<NKzhl3*WJP5DdCa
z)vxkE<71In8(EtMU#C&ANtgg(Kk?Ur;$=ZCf=N2s6T)c*yaG0a8E~E3W&0|#FmH4A
z_p6XU^JZqHz7pYdIA9vI+;`)V2d%!@ogQSq>@-a=oBYvdMtEP;8zGB#b9LuI8)=Bb
zAe4lVim<imYqZr%0^;kH?Kq);qL{8_`<nd)1ejjz>ai3r;qH(RVJgrPGIVs3iFg@B
z6%WM4>hjnFHiavkr$b3qzn6DRjD8(}IR`u#VNG{LjUarYa$rG-?-1b*^3T56rA565
z#Y~DR=z)TM5{KgCW8U5<vgiXME;0s2@29h%E@goy5{IX>IA^7F&+Tx;s0{ifNuE2E
zoVdX6SW-#~|7J+~jwdTP%Wo?A-;R|I3wekhkp8A;Q}9O?-BR!lzwr`ph4f>|Mg;S)
zA`iXFi#PZkPkwOiP!R|8q5>7N^jJjUMG|lD18W6BW4yAM?Yd>#Qs5;viY2xR4Qd5Q
z1@yilC=XrZMU5Y5>>MiMfG#UgAxl@z{NKAIf4~m}75vv0-BR!&zj0iDoMp)fBT%B@
zf5HzS3Iub!WHHlLF;lT&g7wCe$%(i50ZYLjTXajoU4BQws*F(mnb)u2z{*@#@V%^z
zVuF1vxvnC`e=7cut@xILq2($oh{d-K^Wx=V(Iokd5?@&14FzW?^$_G&{@)Mr(E?A9
zs$9pCt(b|Z^4_uhzn^7)$YRR>pe+)q-scAq6(mn7x^a?V#-nEl7A=}d(?f|$jU^_@
zM<l9Xf!Q(yEus>?=b#ikKCQgh6+Al|J4~_f@#BSpNB?Skq1d<h@j}5{Yw^Ws9r;sU
z+m>qkxdE*zNanmO3`OiC16oz^?7t%TH3iQtDOy$VhDB=%R4b`@CB;}?;fs0mYQ^Tg
zc$hb@R&3sjhk5gA#pb<O5awcCG4357pT@&u;|UM+oVVw4Y!7PT)!VTR_V6(j{DdE!
ze(`j2;tIcCQl^Lh(uqSoT;s<(1w(#T<}Q(U?4dt(sK}4_g;G<8@AL5J8I`Im60Gn$
zo{;esBCqqyGV0-Ne#er{yUzfTpJi0!NBpvkkA5dP@oj$Kq2LLAhR4f9e$UetJa#su
zpCz(r4^*qj#rWp2@4~kHjwgeuLq(q8NBs)U#PoF{HA~-6uw&_vWJu%=zYH%uyulB=
z6#ST<;T3to9>fi&_=Qp@4)t)BAJr;YDZbM~$=@m1DZbM~&)<EtfEMIu&G?MS$@8)4
zM4siB;i!j;{J`-Of~gCNR^BGK%kOwHJaPE)GR@#e`eT0$A?249|27Y&iV1pn;`vZp
zi^$9I;R7Nc#|K4z&JUQsAb4&ilz5fMbC<$HjYum#yiVk8e!`C6qnQ5vRhoy`8Zl21
z8ODe25pjXehNvR~b1bANjPVg6`ZQByCh0TN!l0qxtVJsdp0nt61+ROm0?841r3c=&
zXhrJi5fi3{g2(wCPk#4z4i(w)bOo<ibW_3iJypRSewJGiu@JDuJa1a>H5A<CN0wuU
ziacRm*--GDMN10qShS@;-2@B;&swylV9}x_1usKdGKj(=Dp3Va(#=RE5%5^@5I_Bo
z|J0%xe#erQTJ)Mnh51_^eH&qT#{}ZU!C`{xo#J;qdG+?8BKlGEES>D!aAN!L!>reN
z5F)P{PAvs@_<b|^-Q>=(i{HNZmk;$QG{2b)ekUYF#3qCfp=9;*f5oTc$CXx0DLmz^
z&B{Us{X0PuAGKzdb2^lJq^L_DN@flfzG^wH<}|tbA<FKjrtmJWJe{0a=XWf*{3^j~
z7QOx>f{#6_;1hnwlkYuxsK`k)B4ek58Ge?o$k5ZLo~3qvWcfb9`xd>d;3uA{;6r{^
zP?1M|!*VM)$<NXinelW5*DZQkL5<%-$-$Ju5Pw<W8~kX5f;TOCUBTP@44@*Pc)Ehm
zW4a=b{Hu-t!C8x5e&jjyAwK{rShwhP1y}ePKt=9&x`MZ3x*|XEbOpb#=;ax7V~rpB
z?9T0nXTNo*hj;lMOUerVfkiJrdoek2nIHAOM({@-{hZ(nepAUX`SXWQpdqCxA+VI?
z+ZHV=_>o1g{*2%ev?Cd6Xt@@@P!jn%Yoc~ticC5z!^ik3{8^cX5%_`IE16Cy#~flk
zvE;F$80y*7nlo$8s7W#v3XZ<<r|_x}JWjo?+6wxt@hmL7&TlID!DqJ*6)PE2U*Ca?
zHJ%?!wiRd;_dJR@i(mgd49Vh1#@|=@5moSxMK=}v)KeAw+*3b5Y5a^IpcVX_AE5v6
zcMcW%%wAl78MXKtKYyXvyZnIuF~LPM0<X{fYgEJ!t~qw7$jAK1G6iRd&w#JsIg4Ib
z@Bu$YnIGM*&BNFH$o&~X>0EN+MDo4l2d~|J_%9xcrEpg}Tn)mX8V@xTXeb8m&lj;K
zOv7DQ@DV@YzIMBW)*kZ9fyE*D;pF(8;naykjmhuv%X8@IXZ)-g@4}5gG3MO<5Kfyi
zRet?3f^T{B+XSxmufI)HLvjvEWAZ2bVr7p7?MpM`h)YzX!3WN*Ul2SBw~`te*U%6L
zuXy?nfpoRCFY?p9m@K~k|0@&&zr#-&SfLNl*EA~sBaG5x$u$LE@H2E3;p2cxSK$0y
zQSc*ARq#`bR-|P=GEIB!7X)r~UQ_ToKLe-8-{l851wW4Iiu|{puHciHu1I1$e@%g`
zS6N^L5&@tnaE7laaFgJgOagH{8Qvst#;+(4^OLGTGay4s+<wtmyrLkm_<OgnWh{Oz
z8j}>wdAK50{xk3~sR~Z=Gk}ULdb)xWurpXIa4Ykg?3DK`^;+a^V2E?yH_ojna3;Pc
zefl>{dtOr@y=s+6jmprZpaN&^iUMcuYtir|Lo_?VLJTfzlT-y~(7>cBko`$&v_46V
zwkN5%<#{cagNh8$Crl2mNhChDXhng<f?^6J768iyq9VDFP>><Y1{owGZdYB4%>U&=
zqOrhP*bGa}s{o~`mDrVNRK2PIrd&5BGY;xGGfAbsZ_HHSpo%!CXS`C$`@YbHmAnfp
zvLmIGs3Px_iY$94bb(BTMpnMOk)J>14g|@n2A@~?(f6<1R>Via%}4-Cmzn(mKYNf!
zzh%}DB@}s^A5$C!k`v3McFM4@2SqNJm9e2f6Cg`h<6fpG?Li%_ZnB5i2D1_4!&eR`
z>!Pv{pRzHu{B44dJo*a)*EwZ%q)U2P_`9T+CEoAz!!%G3#QW~;d@w8L5?#)FwJeF&
z6p(_?WindMJGh+7XgTleaz4<MC8H8dAczB80L!@mmL-5LU*%lB%DH@%C0{N{Wf9nA
zrYxCpktj!^Mw2Bz|I-R%UmQ=q`A-T1!&P<0_pAr5zD3|;#MQzW@#<}j5eFu1S958*
zs!sAD;A&wAxO+Pv0<IQ@fV;QzA>gX?yZ7(aynnCe>ig=)dH=ps=-;b(|6a}e_p18W
z)%4YZn!bBmYWj~&O<z?Yiv*^=b30emS92z~nlr)GoC&VxOmH<<)K|p>+oqeZD)>G>
zgDf_1op4pbqi9@9m->Cy)bCXV!4q)zws__5d%A*8_*s52&JMq0$yEixKLBlcka{LP
zSIt**eS9_7yjP`eU*<>NaUQyZ-uXj*C<_HrJyiR4(JA)!ZFP`($KH%Xc!OeZIRpg(
z!ka}1Zx$iEdAkT<T<x#ZGwKwox_dhgcJ}ZgRMd!eJUQ{?VI0rwO%yYGh(ne=#F5G#
z;s9k2afq^qI5OEo#I87bh-v@dLs3g4dL;RGPef=xv=j|(znuKw_1iz3`oSCg(X*8N
zXila4cr2&nR_d}?S|TZbU@`3#o+Y0TC#4@w)qXgo_!stEv1i3kAde>;3v%d5onM3!
znPC(!v4`xhVop83GnS@j%}9#*qSh{^Me#1CNzP@571Q)A!|UP1+o1US;-Rb!dXg<x
zEEQ$Fm==Y;m?r7h&{#~1YM_`F2Zdr<v=54DV(0^YId*!IAy>>54ZGN;IJm@TsTN5>
z4n<E=EJY~M&WoiaC2#S|OX*4Oredi$PQ_Ajuqx(>QdLZgiYJzf!dA=^Wv-YOwNxx8
zQPeP4%oFA0e&b=3t7tz-dJyM#Gc}|a1)J&J+magbvgL|Qtz2T|Fh_mY28duBy?eW0
z9KCy6RCtr0m4AzfW{LJ7T4<hV4;tQk@gds1_9ixKTm{DT`-bM_cw^cvVqqPXfa1|;
zimj0#Djp|DRR7v-jj@tMy@(R1c$7TF<H)MGhE~au;!%DSk8-1U94!@(a-w*Y55*-H
znyD+UP~2_^MYh+A$nuJd-8D=qE+#$!%POu=b9O5nC+~U@d06qtzluj|OL6hyS$>Ku
ze3l=8KDe!j7*H=_5ByS$ObqYAdUx){dUuMfcPASfRiRk#ZS)nG+_^0y<uiUPj3@|P
zc*nS~1`#cj{2o8$$M~&4<D#WY`hU#N9z>~^ojdOs-v*-|Opg33a--sLrR(9OZi9r@
zuQcC^&v8A;o;Q9tb%h~A)2;YkzOL5`&+>BptnmC6^D(Uy#rz*bf=~E8oB(X|hf|6_
z4x8Hh@(-sJm%Sg~%Q-dV7t4R2_?^PDjER%{;``WOZ)dT!v84|sbBF7pl@BGehb^#u
znI9w;vhw09i^5O%ksQT`XznuDh&3y76b5oc1h6lB1x9~!e|&uXC82D1={RFkG?@@q
zTw%dLmsy}>X#}-HafO-*V+|_s_TV9+EuUF?t}2j5RBo|kFT@qT#*dOxCF&}o3c?KR
z%Pe#O%qetLgZI}_DO5VHQ8W*;#u2_8;^T@#W1aGRRsAro2E;5yhRM5VJXLOAk^Wbb
zSCU_w`Sr*C$`i+uU;nd*N>Wc8OX|@!`qkvGC%^Vel4W@ZVoEcUMao&6MO2<y>1CpC
z5J)X618gl#OjI5wDPp2p(v%)1s_{ykM^qjr(TwOD1X998AA?d-yJL8Yn9{)H5G_SV
zqSC?AzluUhQIV)7BvP_OpFqV(%@B?LQKFGbk$U3}`}jT&V@{=vQ}#J{T~2oiW&%0o
z{$Y#5n*<`dk`=ye{*PMpxj&SgJ{04M>fcO$fb;rWCw9J-jfVgbvA=CALp3cM`2tLB
z9oNV^<|V0pPVk7i%xigX)YKdDi38zXI>kGt_9-52Nx$F{$j?nQ@1xphq@1!os!h=`
z-bXd{(IeJJweJ(CpU@Yd(^VQL83y8T39xUI;yi!)@Dt)cw;VO~QOo+M7KcYNpQL}(
zWef%%+|K*1_9N0Xc_fPrn0I`L_~5o8KempnDRB4qrc4@lR@CB%X}u6S?pF#O7<+Ae
z4t0;A@~wLfm2cTl`J8*G-@2_G7r#Jd(T=xnE0Un7aNoDIR-pKl>8}k1C-_-D?PGW|
zK12mhq3@}Xl-{E-h2>O4>Mp81^`^bhvWEK89yFMQvG}c`Mfg^6WCii?&q&~kJ|-1H
zCzP*Q6_R5#E0^cUW1ea3Sta66863g{II)U69ECLcl;=|H9`9l;F&r&)@25h3Z9n)q
zKUT6{XNilLCd;fLDd<`Bih=`v$CHB-hl;%H504%yqCxRkaz&>8s~%PGclcTUH;HI>
z!tvzyP8=%o_xO=t=CeDzt|*XNp||heRzwPgEGN(@kMIM|qleEDc`iQOC8D)z@cf9t
z*Qv>*$fuTmMZp*R3<*X49OHmNIz_}+u)#=?Gd4nOYoKta+7$&-WnlEqZAHYXU?gUh
zN+X(k%&x@o7$3EUWob4tyiIVIpVg_zXP&O$b5B2UsK^)o@aUl;Go})+C^*B<3O`4r
z<PRqf73sz|FB6gWG~#Nl-51!Qgd#uX2O<hS<!6+zh%JJX>2V?_?Ey+C@@;<5^csQI
z)~$9$b}aph7TJAeox+OT^>hV4=4Ul1@(=yt(ZkP(_?kO4DDnkAYM4Q}pW$aUDB^x{
z_^ZW3&)!f%k+=BK3I!S&td1WM`Owo9d=%5Q=DK2I#&0RO!tZ$U5*x{gT=R!V4;A?#
zzhlX7DR|$~>1Rbg<j30hJGT8y4_dUfDi!&hAEgw?PB759DSBmvG~Xuxc@(+E57ZU(
z_!%5Ue%~J+J$#eM+x9?X6}ig~^8B3OGfM}OBHB)1#UE$vJH^j>e1(Xt6njuaqazi5
zOz<;Hr}z`B9-rbz@kb98d5#~MdIZCmewWBQ@!>rpANs?ILq+~keDgVx#FRAnK0)M^
zJsdoKsK|^zAXG%O(E(a1*s=7N9z8rD@_m0eaj3{2#W#0}Xgs%;d`QHH0%}pj9n4n>
z4(4|X4(2OzFl)kww7yqxFkgw2W*RF~;7@EofyI7G<YRjPew<B{N!yne`5C3wiPZez
z#GxX;6W_c_ME0KH8YkeYgS0=fbU5xKBED=+9cQpJ&hj(BifF%wb?0>=Lwg|G_laox
zhXKAzL}rRTDDo*kYEkgHrPC5cv@e8o1*iBKSVdMmUBPxtmqF_5omUF$op*14M7p+*
zu>J9b`3u~^ex=}GfA4m57f@LZ<7bDTHAoQ|uU4}nGGWQ|K7lM*Yk?w~E0eC^1SXSp
zS9F>QXl6=Xd4;GfUn{DJJL<0#9QE(rzJeij&5SH)r^t1)thN=%NCxDq1hSP4jv{Y+
zx@@o&3@x%K*yd;0%aQbjr{@OsZ$+0GxuZXcXdGVuT#Wp`<h_4vUE6i%cPR1Ed@sy|
zZHSEE5{ddAoeGG6$gu`dYXL({1yq0qSiQXGlCqij@P~f1W^0Wj=P_gEk<U-I*_v&X
zd1}Kp>KwIU8?{v%b;8zaqfXS0fDteRMnKq(iqRhrh=2%)fU08+MnHwS-_KfioxSfR
zpY2IA^H2HS(s%8>*Is+=wb%Y}e%yP7aoo}i3+$h4js6-r96O{60Jak^h$D~+*j%^*
z+V92l=iMz*$J2E9Y^5Hx!iYEsdU{KXfS;DDbS|!leZO|8xOO=%QuBa^wRT}nx~D|8
zC8q;y70vXYGb2ACO>f&8q&q7xcSSNEcxvp@bAc~LOIUYCq_@a{v&Jp~ewJ?ompvEr
zKXMlHPn!8l0Osp4p<RV}F8!Dk@%T|dbn3OgTLJ=7EN6EDOl<1rQgp++>Ho&ksT-ww
zm5X<A#%ru+4OQ*6?$RiBR>oZs<&w+^nx#nvA0sEWx1C5ia$}t{u-=N~E;h4IEM`A(
zmU+bVQ7%2ee6d70;Vm|98;d2V{ZisW+!R)BJcbb)ZR=>*4I$d+j@VG~4_|*rc^JXX
zuSka_kq&brjZIt<MY?GL#@on(mDa9{bPnBluZHudhpl*e=mi*YTI4A>U#VJvy^>`0
z!!{QS%RGf$w?&?U^TnkFV6Yc7=I-Z^#Xg5vIvQ1nEgj89I&+AXe|!r%NQSq?hF-Cu
zQfz1w+bC+7%(2SDx9&}Q7W+_1&Fky-w6Buibaw~9g$Ii76yRl%$-rC_NhaB04_JRv
z?ouu=A(Hg=doUi7U&KD{he`za$k@fkLPDUi5(Diyq(4K_eMnLSU-#LG?u3RzQV#a;
zjIx`fTJgj($%MmFPWUb5G&VIBMd+(f>*ggQ%M#%OON4SugkDR8N}-f4t0Op_`;s^s
zpK^l)zwC<0@2TPQLsM~EweE^oHwAb^D>e03M9Kv)PPt)?Sd>B%00?U3Hcgn{c@E|^
z7gNnehRMbAp=xS6Gp4&OCq=r80h}_n0`$uuGzwhtTwuj>fh~~^8E5U$0JlJ-gSE-u
z@>^s<S`wK^v})#dV}+(4i8M$5xA$r|9vtaT4FGuoD<9fD6%BYQ7ClczBX0~1rK{ot
z2jDGDgOE$Z9rD!w{$34t(^G%{y&CSeNLv`NEz+kOR%;k6Q$A)vQl<)U*FE)EOP;u{
z$^XZDH6{<*S>QL-5F8%zdRYggB|6Y`5Xo*w4y(~)BGvli_i8vFsq<;1+G(WDUy;DN
z2s;IvqJzaZS8JFDmOqubRT{$%c|VMB<PdXLBu&5{7+V7OMEf0YsIl#0fY<2cHOi)=
zsf{~UqXT%2>Ac3?Pd?H5zjW5@0`v`0GI1VQ6uDh+D_+pssiL6zb8E5$W=*OBqIy}U
z>Q!DnwcMd)8lbse6O+(%E;QZObM3^ceoUm92Fw^c2YkhIfo0Fltq7jxx2?DhJab9l
zrO5pNcjRBEjXB_`v2Eaq=Z3NzQG8dV4;cc_jje!CT-Hf(h2oz#Z6)A}t6bq#RlRLm
zT1mJ$>*kU<|9q+#o@!%88@O-m67Wpq{ewI4C1jR>&l=kXE_*Jp?76_*d6NbHz}Pl$
zV!<^CK5J|n*#0*yx8I~wYI3M3KOF3QI0%o}Q1QKk|LBcR?HS^{?p{81aGDNoi?r=r
zTcuMQoo)i=hDg&BxM^$)7@6*hRA11#^2Kgqq|(t!WSU^kig4C+y(n%;Bvrr-kx9Ya
z@_gXLTsL1ol03W;37D%QRX((+<AKO3>-(#Q*F?%cd|tsO61y&^+!UF}-kyJ44j#b`
z`aEob7mllE@bqw8J%p!&m<bPlWc;xj#B}np9An|bT6m0I5y5{X#9H`U!jl)AKP{}f
z{K<=2ATD|SRpIS_!}%w|Lfxb8sPIUaUlP)7@_Ya2*;DV?AV}|YN*e@;Al2x5O(Uye
zHM=#eX17N3CX~08)fmaz7|Gfg>9xvI2XtWs{YZb60&iKQfxWQ`vm)XIBVe>FpJ06X
zOWnlaFUvn7D}jL&BEZwghk=w2FjY<dP<MbW@k)upLa@a^pB7m@%(UkN48G+PvPU(&
zT}U&UP_P8is~^es1Pp<pUI4^|3F%7)hSwuOgsdnktmL7X!wL;c5F=}f4NDLt_Z1wL
zh$yi{go)SDh%-eju_=ZDwM6eAa2m)?1ighyt;y?GeE@*&0Nh$-0Cs!;ZmsT$c`VW<
z33PpXYZc!f74g^xWCF>CTdO#?>%?2DIPtJM@z(0;<iuO6II-)jTdO#0!<}_&HFMUj
z)y!G9R&iF>Ketvh|Hx!{fN5kFoD|db&#l$WKetx*xFE}DJk@1RD2jYXXtl-CagFi1
z;5)|70JlYIb7PfA`K(Cygn-KXd}9^ni6y?JSIp&rpA$(4VB@gLFgQn_s?-|+a?D)|
zs2Ti&YfOmvxot5dA((AXe7e3X29jFh3NM)^))*XP3A}@2r0YiGho;Z+gRW7U18?RQ
zA}FSJE}n}d-cFq#CpKDY9Tw>_1eg%LQG8IG`cw^j+)7$NB^oT&{^oEEH*O(XJrS^J
z4HTUtf)x?5_hd%>I_Eri$@ov#;F?Gep0BSC9sYLlc1`kyXt?;cWscXRj%eM<gm#sD
zC6bZM1NMz1e^aTYSsK#|D#8uXaPfXu8>#D-6Z%PwYSttf=1_NWySX~1#md*S*0$LD
zwuH5S9b>0}N1`FkqOTU?H9Vw1Bs@JP=QcF;*oBpwwzR)ev)COGsV9|S(byJKQ(x7L
zFu(+LR};aHMQ=ra-WjM#6TNSR$KE+mlO|YmxrkZ(!p_KE&fuioP;a9tLYd8Zy<vsw
zs3>`u)R;)-0plV??9Ejef*Y+7<hiD{%C1`Zr)zLWl&l`8Nk0>%mIk%ZR<<J_t65Z7
zPjZbhd-A+kW|EeeR=E`WIO`9#viz{8D{6r)W2b;Sq8QhhK>oEVnr=*?Y*!`VFIm9<
zLJgi$&}&$6^{Bb}7i!Sm{+XH;^qEK^X#{?uW_x)lQZ|4C4)VFg<O$uHQ05Jhj{E>e
z7KziNE28`+MJx(odt7lg>HU~k8oF1fy&@b-ndSBg2^hL*qYu;8T-7;e5@d2~vuAQ%
z6PXNi^Ri}_C(>4RbCokJr&lY1VZvA=+00=A`5vZ^XJmWW%~g(qPeoQ8=7lG=Z9_Yw
zsi0s5+O~u%SnrB?5eb+=1EuQQt1#Vj#7)}*IWw4Im^DkNeVFS}!e($k5|70&%vL9k
z%+{A|54~x7C=n2ouzUEpxyp=V{#bo>iZu~#<)C_9WCbupg`PqJM1faO3`~mDVPHn2
z{OwhkS<eRu7t4>hvC0IHPmAB2Ow(eXY0*8v+-x?czSFG536r3EM!9Kc6o%h4f0R3g
z;6JH##!4dmEkSqbrX}J)Zi(zHA=NU7X>BDjmn{+D+Jt^KMWZZmPcU~)-_A|n{t;qR
zEpM;(L}yQ^WPRUW?Fop?5eij#gzFO1mN{a3HFLyveyEb6$r0PDnIpFCP{p{Jw&*c)
z+vayRx&3Zx%=-K|%KUyQI#3+1LEqY2Z4L6eNRf9_u;c7KP3H$99YO&Pr^CfJIBn|r
z3#mt<A?4U6Dc(=4trhK+Yqno@Zgfv;3f))_XgY0}$7^=L%Oc&5<fO)_Oe{0*iAZe&
z_**Xr++5{@{Na3AdxWqPF*P(@mVEZCcV`a*@)rj%sf=l%+?WX15{`6CP9uF<c74ul
zYXRN!<;LofuA%I_F~&o@#xwLY^_Iq)gQ84g77vRC<)NRc;h57QSjenlGp!X?YGgNT
z%$c=~T(5<Hj;T>az)y-~DzI+s1)#eJY_7sEhqPFoijx^UtH2Fk2{u<@*a)<J0o%s5
zfkQfqsZ*P)Hx(X-{n);_3NvAeuddcGM?@N4`A@?;qCMf5NRP&V?j_FVDvY13E@V5!
zrd{pq_~x*=3d2sJ@#eU6LuBp4utCT~;92Cu6c%TTKzEnev|VCD8CE&l3pQ7YOv27e
zvgLm>zl7Rc<w(_C@;B`gs(Vl36v#oq>chMeX#@ZQ2JdFe|E8@D&s1O)U<e!=4<V5Q
zPmB}bS)7}Ew)~$W>bq<HX0zrW{MdNPR(^FygV|mAH4<{cOOfvK0o|R^9njqbHk-9i
zLfOi<X)7Q7GxK0ZL=pm+9+uD6@H!H#h!Y|!p_5l55w@pUdq}}MBVuNP-1|_y+p9zs
zSI_LtMA9?kKV5^*MH+#<+9GE!ve7*3wgYzenXTMWTlqe-waOXjO1D*z-9@HtHQS6`
z-^ib9A}hepUFU8!y9`p<CbQKz+Nxx(-pV(bt$dS_mGU5=V|B7kW-H%hwwfTpzs)1M
zz0T;#VWu}Xl3>PdD_G!?>#?)kE;_C$udid<b5n>bCFOJcd+jXq_^L>`OkJj^Sng!7
zC5y#hOi=^`_l#`;%vI$A_)@*SVRt>&eg5i3ffi~`X%c!U7}TT{%iJ9onLG>=S@}%e
z=C)CqaSL&nl1R9M!%A~tiA*8hY3}mG9;(=j8$N_5+vqj()O_Y1-A7Ru4q1=p>F0fC
z>74JBt=K8GX=V$P?$b0~n5PSzJ=C?mH)al)$!Ri~-PyS!>qo)FnzajpMS$yhtwWQs
zPQVYU4~MNEiwyn~XBm9fd#zM)r%-I%C$yup#@)kUkqc#(^zL%bSzm0d;9`?c7Kw;i
z^T{IM_X@AB)-cySKe=u3BjvD+OGnHm8foHTF=mo-<FF<+&a7f%4$;+^LduR+R&4ky
zd33*!2r0)k`IQ|QM}U?2_yT~BHE#FvHRhh(D)d_t7m`0OoNj!00UvV6(tetz(uFjY
zF5oz#NCL?#7m`;lB(GdxmT)yA*%Vb5lCLf#UtLJPx)8oH^O-s8BI!uZO0U6~9~zhS
z9rmv)dbUKk2RvqxG?%(Nx2f*l5+MQlDl(V4ZU+G3MrQ%KPJAF7_mo*+*OW)FNaVi2
zy)zf91=2X;xkwUeC74Sq!CVY${|n^taENAZXn@&CPzd^Qyke(dkJ3E=29LEc-y4)2
zmmFf_EGsse+#lJ#H$_9m#SaG;J{;tzww0%~?7R>~Icv|PDAKIKo1#eL6yhb)EIDhU
zNRP-nL{6k*RgE-D(XuGggbT-;Nblc^{#<TKtcwm7@1L!A#r%Dd7F6J+v2%dW9f`yO
zW%4`f{@)Wx9=N2_s)CYxjNC)i2YT)a{?OPKz+FY<G66<x5}e-_eAn0(@W|K&;F;)P
z@qt=w_F6R`<`dsdjEm=%>!OHp26=j>$#Q4)xft$@5+c}sL?dDa49}%V5GIE-7FI$~
zGruemGt3gvx~^>0#^*#jc%{sS`<OMqDep3Q2Rw_L&D>U&Ljigrf9-brpj^6uf0Ya1
zP+7KN*9Vt1pOp_>G4>+BEm!3N{$QX4COsE8Wo!%Z2gv$a#JEdavNH1YKpN6Rgp!8{
zo1P2&wy`Y$_tKhR)>(i%xiTKuvX%5a;7_Al>1p)&6Pg}8hL$Ywk+J8w#u(F>NH4%R
zNq|whX$#1C;CGB|0lvOklrd+_KQNq*rGwk1zI>jK!BuWPHj8rGSImPgpzF*e!7jv(
zuxNd`cu4kPdG~Vpm@Um0L;MrL{D?sj;(_V;us#o|C#QZjd8{Tj7##wep?PhCu*f<6
zrTk1b=uiKv^z^^P-;d1l3iu;qTYz_>N~2IR3X|5g3SbkE>jCzD+5lO(v|Y!UiEN&W
zu>&d_;EYH%_`pW00@ws3kv7GOvE#IeFnB_wl^I}@lrX>$A^|?KQLO-0KuN^Di3Hbr
zEFjVm>j>GL-Pv}O4RBRw(p{%BF%QN7{80R1hmsl1*=r(N0R2+G;wU?)@FE+WwTP>L
zFB#hc7*8Cap*-CkR*;oT*=%jx+!YHvGqwf1_FRDHAv#*eV-XD?PeXiI7y5?PCs)Pf
z@~eZ2t$f#}Tm`UeNdv&<WzN(9dk9qfhd}jA5^QBi$00x_6Ac~$cJ<)LfeQFPEihVu
zUsKEhKCxTO<vd0_Fzo7r(-Vyl7#<A^u`QCFqG2ILz(P8IRO$Rt#jx*Pq@%>KfAses
z?RhRpHhowDAJ+Lal=BSbhc;*}VAI%n;D+Y{D>eb=fmNT2Kw)Dtp9XE7LA&d@_XR#^
z^J%Wmr};VGKRE8?c|7c%oloAJ-`|__c++p6G<U{z5!LIc{?sdNaR0X`KAjIgp+nqI
zp>LDX`HGvWJTD#6hn)t`eK-hTTiQSE&z;sgS^Bi5*1Bk@s6HIjH@q;-F57v`(}nzZ
zL=^f7--8Ow&=1eKP>)sbt?G+)CiR^*@&VBnDx(W_EkCH+{Xbw$SKKtE&S#O-l!QiM
ze_lGdM@5&Q-G1r*x)Qj?TQ(wneDww&UmcgLj*Hkj1w4V)&Uk$lh9}C}y?{||EBegI
zY7N7wPx)*)eiXTQOYB3Dv_3#9M=Q=GO5Z09&p}zWfFnAiSSv7oZn+3-h;;G?{G@mh
z7_`&O`>QpKpB3i-Mo|iZ6=SD>Yn}^idM?1KDp}x!c0_9&hIby658O4j4eWR>@W^uk
zpPU!(Yw3Mp%Wn(dio*M%AYwfZ&%$34Ss~Myvw<aG)@=2i16X!t1K?Zj9N?SkMPO58
z6=Cj*Bn=!QR2eK7rg^wKro0t0>3ODY2^dJj9nZN@rW|72L|6_cMal<G8#@KedM@A#
z`&2CKR*}U6(&0C)BNuNeheh5*V9xj=4zSW&K8(NhF~`c!1hf2@X|g4jcgtrLIwDfA
z0LM)J{ec?BSEq{r57JFOo~Y|?xL%;p%K-6MU5a^{zH5RCZ<uEy<)6}~aayEjv%pzn
zF9KX*DHrJ8TD`ss!-A-Mz}dN2B6V3bP{$%^7NtFBE>0k7Gi^V1`O9r)laBk%5?NOs
z2h^Bqu{XI^)&Twa(hv)T=lQ>V^SygPblq-#5a6cf<3fB-NH-C<C*pd->Ep(qzF33%
zb|TE?HQLiHT-ye=_5Pqv3BXg4zx@iwk$9gAFRJUu-BeTpUj0H|y{uF9GFlbdQu|!h
z4_WnjU{Z9T_}VDAYYon)$~{{f-uDq$lI%^9Vq;hE+}XpbeMDquCE=uLn>sCMi{8-F
zt;wIQVJ}(9G_Y*!R5B9rMayh%v{QJXpwa8r(z%C%5tBJbqjyAh>`7XR8HrFs>jHpx
zvfHlF5p5qTyyJ4mBy&>q34NLOTi^fwCu<U?tYQl|lb4aWEYizED?=t7joX1*p6;Ty
zEL`ihoCj8{xe~y82aB(*)G*$oGTf+(wIgcagh=nF0Ql=*@vAE}%oWcE=zn%;*Z+8)
z=AVi**MP#LTfm^meoq6&n{Ta%T^DI=fh}WOz%7wU!+4v`5D^!HSx4vSsB4^wA=26w
zK008cJ}AxYPq&+~#T#nBQahJKVgcMeqV5k(e(Fjw{;u8`3w424RBzMjP6Llb`a=4Z
zW2(q_X)XciIiO*ST7C!qwuIf_cF4b>K$!egO`SVlJyl8E$$v}QMQ9g%-q;d2EArV4
zH)92DVAj|YSQNQT(wK8kmNa4}-UddDt$;C+*M$2Qte_1XH?{&k>$w1Ceq2MTk&;G2
zb6F?NC7O?j`1~0d`uaci5yn6NXJI&vaZy`*+58VYG<E@aBJwW74a*>n5pc@b1z^T=
z0ld(&MnqSll@U{20=vdmK(tcUsg*LdQl(bP)Jm1>{zzI*SmX0&1#VKd^fI|#O2&II
zHzJv%CO((Mo2kXphTy14w2lZ|cQaR0(|6^%XCf_<z;ltdf)V=hT%>FOZDdDd@JUBe
zyjHb)CO(%snAwBuVU;hq%0<D3v$N9t*zF93>Z?}FYs$PMvUjH*iGi8~1J%FYNBy&3
z(b6c=NCShHVdsERkw*jEVJ`qCjBNvFJU5iF-K|N>Yg5>w-k3@3<4feOncNhxDbjE6
z4Ad~UJfHf9tp3zd!7n=7G}dL7B|L0JRjN=?4`UB#7p1aWT1Dl7f<g*(l88+3*}ttX
zXRzkm0Pfju6+mpz#7bb&*m)po^w0A#m3_v<TEJ;zD}Wjbo!p8gEg0{LG%CQdsMm^v
z12>d6E-SK{Z#0?tXy>`<wVafjDL6QQ#ud}r95LQ#GP#K!R_3|?%09W;gF^J+02+7u
zZH>(QHOw~}(F4U_$+U)SW-Hn&jh}v{8#e)$MZInc6K<*Gk6aKq_E)Jh4@`=@4%`DT
zh-!|ha!KW9rl$fBr*i*TQ}3zD51G0-G%q^4F1X<=aL3pw;I3#$!K$sg>A1K5N}482
zutL+4vuJX2D;JA@M^xYqw-EoFiMOr`Xrjl1XOwZaKQr`zH1NkJ&<5^)6$Nv^-!`@l
zJP^4Hjr$do859f~+Xn7mvD{pD@TrZGHtw0?3JAqzofKC|ahViXp)AK2(stXlO{Mx%
zRJvh?O#xe?;bN`$YsL79@tV~4yzrI4t!@HYtDF8%J8o*H5x-^P)4&tafnqH?C?#`V
zs@AgAY9(V@7_(>!TFZiG&eHUZIjp50^z2&Evpy8XW$C(V`r0QXe#UB+XC>aYn&~pe
ztxlGRdo5!Yy)wqUa28_@nVvQ<E*dI+MIrfiy)6E!7t!Z?&I0s#M13B5^Z)teTJg4g
zIIi|5%!c-H0VZjF-VwMv_j@qbV_i{<%Ai>@sst+0f#S*_wtnQ<0A`bo-6LjE35<%!
z#^w#r#^(FZ0@ys7Y(73d^lQZ@GrLRdJ}p8GhHr~>^$6VUX7^ca$s;o8jM?`E01qo1
zmN5hi^xZ+*f*oV0!%ave=X{~j+r4#XzY?a*P$(r^((7?OjSB`%U;C7Rmh^*5>jH1E
z^FXXO*p3FJfiWSnBpdAw4A9bmuEPArb!zWiYOhS~m8rdUYOkHzD^q*tQhUwdTlYLP
zjXl&j>{v6~*~J*#F%f(?l6@$&lh1HL!P6Wv;nsZLiv9)?lZU^CE84&f5hr%=re_1k
z-t}zoxbtVg=iPkprAS(UtH0*r(MUh0M$2ea#}L}wvNlWLsOhT!n(}=n8kKlzvy3+T
z&N6wksmV@ia*-x~*P84Ax=2(P7J+E8Q>P{uQ<I(4WOF?_JTP$3F5>l&4BTho*^`S|
z<7)Xp@vDX>jMw)m3(tzQO9O3Vr-5b91t5zHAw7|BbO?Rh%6i@v0e5~Ck&Dj-FPsHl
ziBJL-*8hw2__47I^!SCbEr4F58XR2qir}zFJ1a0^?82zvgtNe!u@|ojo;V8}R-EVx
z3OHiyMc}yS0xO;y19{M=XXD+jx1(5yKk*$s0#6(Nela6l6b<PkYAopRxKFJE8zNoe
zTiA!oaM!MANIw$zfvUi}-!1^JMN|RZZx@o^F5<V3agclEV(Nd^>5FvOXHWX-?9@FX
z#Rqzh!5vg1I*!on6K5Hh)8@0eOO5;HLIJ<INLcP4m?qU-bqjOYlG@Oyz7Txgdb>7!
zU3gEVP<trwkXpck&zS|&X9aCzTfk*w=WhybiH78<Z^)PM9%1vi<BKBg1H-ezO2j$v
zgW{)a_+JreoxUPiF}4K|NE$ofnuyBaBhTIyyfAhiaCRCPGv{0YJox4#_)tN}eO3e?
zP79=u-mwdtjrAAy*BNyjkEq>aW=#vA!@4cDS`+I>MLkDSufhn?U?pPp2G>Or-4Nh9
zThyg0n|g<oB=94&@^!y=%<0ICXsGz6#$&vOzbevQ!B+xwq6l-3ix`h@OAOw__dIRT
zdDWl~cy6D5oK=i0Sh%!S1UHPGo|N#ES0G9+@2xxD2rr=7mw|;|w?^uyWKWpldElh6
zZGfQFtx$ltRm=hyp#dI?!IlJL?rmguQ9^%F9QkWHj)}Cp0oROO06z3w;I`)iyCT0J
zfO}#E&Bh;UlhP8UUVSmIUe>94I?fi0jdT^d94WYBjm-f!MfTVQ#??0~fiIk40z;i_
zI3KN&owsmCdLD@6#}E;lOB4lb*Bu+rHgH(t?g=>BlMj1q<aJ8wyte8KKvXa5R6X;=
z-A20V)k(oaQ!@v=5Sb@nTz#J>!fd*nY*>s|`#rHGJ)`c45ZU92uxRG%iWreP4%{}j
z0=7l&9Jsqy&;~v-wgUdd*b;aqa`8}I6xWq^L&UR^>jOQbRTP(0a7&~uf(D*A3%J&1
zApFGpBa5fz;Rx?xQ{4s*8(RTKL~bzL&s#woIBRSLOnWYXqx$<7O{GRk8VSv1oivwd
zJ|*J#3WmP?=ER8d$3*-3D;j(LPp?OK`kC5)F48Z#z8I+CUWoF=v%3l3T+vD|Qse+H
zMD8EB?|T98<kxMC!~FEZL{d<q;F(pafY4ReNmrS4RgJDLb4X2`ux47o8IhLIVncY%
zv+oK1PB%NRJ*d247XjSXo<(C=_WYum)&?+o|1d!CkO`K+C1We#vWPlm4Tpw(t^}xl
z+=@EDqOo&8RPSWfn*|~|Lv=TE8mO%LJP_5Vv+7L`2Z}JMzf+OlvvQ=&%z%_xg*E+%
zU*CDpVg<Nr>^$&Wo(o)ALtq|QGqw%f^jzSM$jyX%^i31*Z%R{Mjg6by5;!8#^7^$J
zh9-R|QsX6!qs<GF!U3_q_@q3z$*v-e;;vY?ySgu%UW$}^=^NUxMQ;=bZ~v{q;cH?C
zKd_P`f+c5{1$Ui&EjWAC1ZD(RoV_8q>+FQAo3#E`*95nny(e%lRE>fA+1nHbGb5`Z
z&FZIu*UlEJGE>BH>dn`mtl`H*pD5M_hsZdg#H>iwfNOc#YbA!&`$qVX662!K27e?M
zxGAr^5J?-ZSTR?$fDKWjXHyAxQw!fz=8zU}S=5LnXSI^ETFF^0ob}NB)_1EeobvH_
zU;Y`le$N2+jO{!SJa-nDRNwT~lRJVJ#&#I?>(;@UO#%JYx26Cd3>|{us7Td-<D!Gb
z*H>$p1<%JbzhP`AIii!|<%=m^I>`l{<bqCeK_|JOgC{(6zPNwC3GAcRyYgAn(J!Qq
zPSZQ@Qb|AD-sxo7bZVlxi=}S{m1}&yWD5uu{77+IJZqwLil7~qWk0URcSG-3fWEJ5
z0I~>LJ>UQsuRe*B%4)j=Fe@TPsSHn4ztxR+@(Nk(V>`vPUbazeMes(=lXAf+8>cCT
zY|UAKV9xb1j9Xp|+!ckAN8+DYQ4{J>6!D&Git!Ga81zWT$VWPcKhpgJPwy{_G$8>T
z@n+W%pZQdMUmf4I&bNuVS(}H=87;qVXW7(;D2MNwt~T>z$Jt%MQJWm?=Ymu3(^#AE
zIc?o;6Fw(h^C<xhNgzd1(_Vzj6KOnd8f`Xt6x#eaV|BAY@1*{6FBJ{5ilMKIbn}?r
z>f^yQx1(PA44rDr9@kl>iIzQZpsSE>NJ!1HscNH2pE5*iQdOd=@?HXH<;inWn_W4W
zMn7ipul_$N)u%+dGGDG?PFq`3%uSEZFWi?KAVog##MoAvn_s}WgYt_1ih!6=bI})o
ziO5gBPWQUaoZf#9srh3fz4=ma2z{xTV_$X~=F<8whcmH5C;cS>6GZHD0VavPtJZhT
zm^pU2SzD&(*yV^>2}I-W45c)BqlzA8q>c<sq6emGo^2GLa*z-(N5rE1u&J6yIWt4K
zp|y)rj@~oUd)6Ye1>7|D;+DW$yO>(Ln3}klnz)#nXg*F7O>Iieu4!CKb(g46nN3T;
zWzoT6LqB+vStizEVW7C7`rD#6iW3`JpkVKc{zCEA@TfAb>TR!|_~dv^-cC>cI0ZHB
zLR>Y1Ya-PxM!#KLE#CIJ7z8DqUY9(q%da?x!b*AXfQ<?rL?RpoALA0OGBEJF!qKkA
zXqEibQhKOu4IMoA2H#xtKy5q{X|dXn3LocIXyAk*rI2oz1Ne1V9o(>oV5AmBL!Q&)
z=oeD=O2my-Ii!YvEs~<>>6^iT-B3Jfp;*!9`xc5-bXf;N{Ol%HboiyIs|IDkm`DPL
z1c#l)+BIjRnYV)Jw&%e=YAs#>ju|@zV24b<^5&~gHUpqf_a$R4Bx5dMj5m9MW*J(^
z0@p;LCT~6C)$t=5fpr^&^MJR#Cda*<wS7LdeLmVADqIQ!7=GQS1Mo%^g-aqGeu;Eu
zNgsPurW_X?EUu2$FegQW#ntz#8t#rrgBj5&76aQNs{rFG$YNM45ey{~#4>Dda}y9O
z9q~u&tQ3RHDRToWou|SRo(lDzq6M~aPtjY(z*C{y@saXhinLb&cfN(#_XgTE++C3h
z_SQIJ1tl;e@{1ifuhGB#XxGsI>yOqxver6)H{1eViR@M}%&@6%0b?S|UlViF6Du_g
z25N35JDW|JwrGheGCxW5_2jW+`g)?<@B4H^NA0G;9vw@{Ua?lD05|EJbyfci6p?vQ
zQ=?fJD8^6EtzsLv`)%t>RLl`ceG8yEQUc2&cQ@RM7XVvL0o)xg0MOlkHL3=>cV2q9
zZoA324#vF}y;*!s&ogwd`t6$Jm~{SFll9JMO$O#=awI22Z*jMxTbJ}PksJyf7g1xm
zc$;@&NS+p<S!w0IGgy<+?v=Z&B)!*Q0c*x~fOXFWHbe)DcUNoNam(^M04`BQ0ME#h
z+}pw5S0}Uap+%0e0&jQ<aPPOm`#LPqmTPS;3}ZT@5tnqw5mi1aaCf`_pnBhM>GSXD
zBk)+|mQ4YL#Pu@WU=1_uiQyV%)Dt5$%rTMd1Fjf*?vB7sZO)+GL&3g{P16`dFP{!t
z40y}$UddX1ciCDVk!p#p)G!RW{GCR=#0W-|sVQ(HdX@~b9=HVXbRFTwqcKK-NIx>^
z5_l$Z2g1Gd0$^NfyZ~<5l$OB5rU34-7XUQ8XDp&w@M9(s7VTKW9RNG@a{6iw^UCvq
z!djXJ21ORFn088}M>W7%Q8uSYE{S^P9vO5alOwqz%I6;Gb&(<-*bsH+-mhuyk-RBF
zv(i5I$av5zM-ngnlxB5ja{TzG-WfPPp$eMgZ>v&G*^bEi3-d^%&Hzu0od%v7+f2Qf
zB)M<z$wOHXxIbIrPX%)t-c}5+a>u0^BNQ-Ui*m8V2et*cB~!_gCb;a!6B;wH;h_y!
z3DBaV7Qn-r$^gxHl%xjRH0Z6A(aJuN)QulT8j_*F8IjFtn6@Xb)Qe))MG^vNOY<s}
zE4Q)Q&-U3gPWq=|i6WcEFs@(I7-rT>mTMRqv}p{pB2sgJ8&M`B&OK4?QxoW!#$*lt
zJJf3fyT&%24s*L>Z?2%mOH<SVyz(?KEV2m#GisWqfy0r%EM~>?*92EZZ|apceHMbP
zh2%BSk10!O<!Wmo<3_LCLnYnL<}?v@K5q=N-poi+PQN2~;B2bf^idyhQ5iCOP5>vA
zNuit*GMXmQ7=x!jOCFU}w>4l^WYGarc|u<}Eas9YMrxQfk?aHLqnZibg9TlomqVKD
z!}>H&lz=xjwOxu-0T}&{Xzj{UkBm!gn^gHk@Y-2mP!;sU00ZUclU_gkq0Z}csPoe5
zbbzMLU;5dmomdi5trnH3sdx2Oz*izoa{x2RZhGQP7O8gozQlH|#uSxllfV=V8{5nu
zTBa!%HVM>c9+ZHM%}YtS5gj12=e3gD8~a)@QNw#{+3cXIXEtN*wjWc$tVqoP>&8w2
zH$1oLq8NlvT6PH_(YMMJ?QXs%Z`71(WnK|wyXt{VGP6^4tgH8aOTHJWF7T1D74TAY
zkgwx~DNJcKEWozRXWaoQLeX2r-{`)0^5QR}@q42995|X#5$RBu*NM&qj;YRPMQRe*
zG<E^FEy6498jkk$I!#myr22#vmB3A7=YXhQX4U7SnxQ%9vP74yRvTCm{dn=g=+OJ4
zL*svG;%nL(Q3T0CU|XaIqxxD)IL!Lz3JI%<<iAr4*<m|xXXiiAWEH7CfW_Xeexc_o
zjo<2kNAlx-t0O6$M(Nf65dHJObrJffYdCc5xy?o8Ybw<DcNHLlJd=(J<nQ-4D!HE*
zDg1ynV;2BwDi?U*xxnA`T)^#UhR>sFOa-$hQvsD|uvq*3;mq<X*)gD7OJ^l=*=o!^
z6+pZ~1itj_ByXJRXu7Fr(TXz*TRX~m;<*4ibj4bkvKO8Y9JKNJs=gdPRL2rWdQ=kl
zLN&+gaEiYCXsiymSV=g>N*+iapIAva$4a6F$A{OoLW>kQz`925VDXKm8ipa<8%5Nk
z)<Ko(lmo08y9jKGs8iN(XwaRE-X`<Zb16DxLKQG!>;f<;($cY9!<@1F5;$x5`s^pn
ztR>d2)G${>n!U7p$JzS=Oi;g98qa$3Pr98|+|pGlu`{*b8Oscx&rH=AW8n#rZWPnr
zva?k6e)i6Mt9wL+Crz#e&=<Wiunc0q?#vg_5AvfM+?kBF6$vaNwvc!pcA!|30f4mW
z|5y!k%JQdB1W5$ABvK@Nt-dS<KUo6Hw?z^H?t1>0>u{U$!w7ImF1sZfD%u|o>eqhY
z2?Sd{2KV`?ADO(Y@^ujhQ^AI4P{*vFso`#T!It2TvjC)1#aIo4euZXk2K=4BUJU<h
zA6gO6mXrr7+!wtLfXVwuu<Lj&J&IxAh^bouP8iz)CXFpoi>`e(2TXCP4sg<>7Ly&F
zu%mAtoR%<Bj8LOJ`CB7S`^QaUKHBezi-D>U$Zjhwb~6v?rewH{^+^hwAi5-(%Occ)
z8zPO+HNg$h8;VMO<Q(?4m9*~*o*Fv^JQH<=U|(Cw7lFfOZ*yFtO|;%LiITdnoTa4s
z)0@ng@yLoQ;EAyvfJ*l9ZJ2S>pN>TXi^_B-H5ZKZR)1E6THS3Ovu@r|LUR|`w*2>3
zY8bCS=hgTZ|6qk4m`A3$&ldXh8wTM<eUyTBu2_v}0DmbLa6Qw&W6uTfm7b5S)G#B~
zsW0HW31@+$B8d#vFvmPUtZ~G4Z)xgfSEoi1je`<@(?9e5b)7Dv+E8&%(RxS%+2sV!
zRmjfff=e_TsXj*ARBIv>hdl3A(`WI=YU)$5Z<Be|RBfVSAk&w5{eC0ath+Qq_6w1^
z2GE4wy>DVW`ZoTX8Uc}33*d;=SOg|Tz6ik0ctKPPq<Ur5OW>GE%>z-rtW)*IKvmZ&
zN9A{|atF9;?0LXjYvR=>A`M(JnbwlPYqnOzUK8bW9P5yFk@A7qSE7NUnebu14j?MH
zYK3#ax=61heZ7X6P(R)%zFFuR3YLzr+jW$VPIZezAD*XWZ>|a{JwghJqF7eBcd&^H
z71~C1TSdDf4I1!~NL$oO4Ku9Pm7i2Lff1_16&g!CvL#Z5hk`+?+fH?}ts(ilSqkU{
zPNOP*1-(bv1<z|`j+@?QSO<!fx$o)a<!@-MyM|e9VAI$I;I_!44epT_0Dod^8yHuM
z`)noAeK0jp(!jb^o(DFJZ2>nt7oah1CBTm7rZ!93d@jPSvW9zMGA+Q3X}V71geiZ?
zhz>?vwn`O7Y&lDFw4<;9o*LT$Tx(@&^pAy;vNuek^-$pT^2jmaqm9&D(mwY>xrKRc
zZj9k_HnclVO6Ihv>xMsY_P&7T`VKRx>Zl6oodkdh(HnYd_?b`EuvlqRMQQk5kt6}S
z`9|@pNWx-bw<0ViM#X6CpfQz7@gYY~0WLY9GZ9Aacy=z2G$M)@B(Nb1oq++`8dY0*
zfcIAqG%J0|&xECR04ENb_gVlov-cioc=+GfTO%TcHb4yQcZ5RhjER-NQ;DfV05!B>
z_udvt;vK}FnfP3Ev?vypNyVOFno*{k(%f~>9qMl8f#Ms@CU79jeZR?dck7)Q)p%&S
zD_}=tHzi=6dp<z(`ksKMdVb`Vs_p^&5r&Eeimw2LD!rjQiTc75*in%j2aJgh74H@H
zH8-opPyf1q;mzB>QM@f-D|HFa-y?BIrN>2T2skZb2?H-#_LqPwqV5;2z+ShKHgL<>
zFC`Z{w<V)*nf+e^?i%~c_XWqi0^oIjxxX$Q9yF<GU`+H=`}eTvpUU^^Umdo~S-q{W
zQsC<)wY6-<eF4C1?E!fIs9EsK#|5X2?Esarv%rezV6n1N!+2L_^G2>n$#v6r4tQxb
zn>|`LFq_P5BT1P}EFQ=tn}ecTZ!4%B7qR$>HTFvYqk6FT^_4me?=PjEe1V?KnmxY+
zTncFz@5wI#ZgO)7IG7pI_d3;>q|q<moe;F0y(VyV&E6Y#l#Al*zo%_oM6`jG@sl-p
zTcjxpY+LrR`kwH<XXj34t?~c#`i6>6naC7yMx-0E*3gn?Uly!5yC&Fh_L|^^vo{3~
zodq6=P?7&dYxg%a$3+S);EA&z37$LqLh#zzLVAWxZF@{G?rdmH4}8%1P-KS);UnWG
zYmkcaNz_LKJ%>FzbOqk|jx>p69dJVmv~B{oMctEwI9gOeRLc<+JEo!pj+$fz95?nn
zFypzif-Ps!?^>%|TkvT8Q`6c3sHnXI2*Wxx+_o10cSTs-so`ArLg))jdZ*F5Xw~O{
z&^v8<y?VAKpn%G^B+A`FkSg3o1gWt1E}~vd8~(gVBXU;ofwNZy*qCiEw$PZ7hgE>f
z4ix`#4W1AU>j?18V*H&qYf@;6oZ*_(OqTPe*^hcOM894Cb9Lagh^PREC8awK2)q61
zMh_Jc{|OUmg~%S0lgdwLDyKp||F~n=a^v4sb0P&Da8j)(wtzDt4>~y9{V_p@iif76
z1jbBqj!Ik30=Gnb)ed;uvjNo7Nd6flHw~?>sso_T0}Ad-B3-Bgp`p{bH}Be0vupZw
zqii}=pN{H;P5i|sqpM5Rp+7dUg}Wk+4}dyd*{;?}Z;9TsW>&KcywN=v+?BX@r2-C%
z?34j>%Bob<b{AJ+iO}j}$0LzO2=KPA=>9;XwN34|Day7?y8hDYHCHsK-ci;^mfZpd
zRjua{m_(?Bc0K$75E;=^GJQ?luNFVe<9hVO-?B=-Zf&;!??f}zap#J%Z<@p$ut$P&
z&)jEC<ALKVe-a5CF|#V*7^W$7+BMu~t)LAo8(W2e36ri8T@xlZ2ZXNDbe*t*5^!B}
zNk_ZMOvYNw465LeRcxIRTy*x5z;*Oo&g^Oj_*2^j+5ksj?@DS24zZ^uRsw|`7Ak-m
znoeU${&`nVwkUWZ*Ws7_;uyFovPZKpcSQR&Or0wt#XGPfQoJwKFj1#>$}Xz}jXF(i
zb%n$x^Yn!@jYK<1Wbvv%X(Y-d(aa|EazQ)D$+8gVTB_9D`KS}=ym9#1MtuuQ5&sLs
z&pV?-D9{r$Q*qn0w*b1@FVd^Ek_0BHuVI<)+^=97mESPa(se^m<tKVPJoX<`w+$RO
zb`F>n`LMv9vVu0SW$YYqN8~ba_q?D-za>&5C5?n;-Lg{Zb5^SaDiP}-h%!`XBRqIi
zdC;El($1uQoUoz_rMH{~e$Uu;GO!8*?G&uUpQUc-NXUcslm4(Bm^HQn7DetQxUX12
z8@Oj|1w0VB4BW040RO<)Ht<B`GO5+zQtRbOiA9rToti9Za$SUr!O)kvIMfwMUnkes
z$@F!SzTdo(>&th+cGsAFhOB9;I4mJrQ4j*N#{M&N9d;0H-}gWP)^1?TdEkb~oenqt
zpI8C#d1KqaS&_@YJ-cZ#seAw5xMW(1X|H}8?H7Py8KkG7dS_D1*{+>s4R=W-DIhvf
z)~N#*=)hr-Rxn^qL<h<m?)2ZV%D{}snt)jnxfI-?+N6M4kx9Wk@O)q=@?jo{yf)km
zkqiW0iL5rvYmrOA9X3~90478x1#{Z-fisa0bJ_EO^~i_W@O)q^@?jo&KClz{FpoSR
zcozA8woy!@*J1Py*|;nKF<_l+z!vfW>)3#8dkug=!#ABe#b1Z`i{b0o@ZC|4E{%X^
zO$|6kO$ET!?of7WxNR>09yA4T&%6M*+8r3x5Vs+cD&Tfg0C&bbw*V}O+*~-^tr`F>
z^@1POr=yDYaSQwkxNYndfERUpcShhbKSh-Pp5;yfxJm*{Oxz?E_(Nl-9tiM^a)B3~
z3*Z*z0ymAF0`Q4)fnCo9&YCkSf}gHQAo?{B%%26-J7)R8;#<pgOm|)V469T0+D;hy
zCcBvKCKvG&g)!x=Fnkb&G1sjyX1iL5xgK&c+f6R!yX0cFTYk)U<?qN5%<-rX&qOyl
z7$&;pV!nr5%y^TFIWM^hIrX&2@?kv4<^iU<<;R?t{JQcsA|J+MZytCU`7k>o>=iK8
zO;5~u<;S4KIU&+r)Yv=`eWLi5zE@D63y*<lG9nV23>>~CYBC7Aql%y=gLu1>XAo+y
z^Ng5%O%-O{ABdU^-2Eqc#u@c(LDWb@M|hpc{<_zQkuUU;$Pc+pz*u$veuOBDFK^Sa
zyvc{*6!R?(xht{+%sor!vz#ywEb+l|4f8^z^DHnbC+Vr}avkw2wRn=rYnotoM3M(^
zs>#C~lJ86i#uvb8;EG7{z>3J^VYV%y83*%+A_)PEg9*VrwS<IVj>^@#NCg-h6N*7n
z{)X}xBFl$itdtKhQXIx&#FWjzF%QTF88>AEOCqwtXPzD7alpQ8t(#)d^gzI#lNnlm
zcc_{eNW*n84cA-@S0lD3hSMO-F$mX0jW7vcS<CQ!Q-*V|iu5=K=m~NX_*-QU1bDTn
zmt1)f@8K$aJsz%MSrCgmnDJt}4rpMo;r3@9HX%F3{z?$)oC^4^v5@wMg%m$C#E*An
z0jn`tJ6mj$Vw25NG5pF+gFh96KcwLtdS|#!0WcE*5Jjn{Q*@ZQtcOeh9hchF|0&$S
zA}0aBgQVv+NUtA`tN%AdBi$uTA6V3e!jNx?xaSlrR<A@XTfMosWK%>vkWuZGz*8({
zy}8l(-duV})c5B0+D~dx_AiNa?T{OORiU_Lv3b?MwWHrUkGGyn|Gmn|S(9>Rh-M-E
z?yeyl>IR)uF1<QxVQGuNtl0iVAPxPW@4VmN;`PR2n}%+2dA+f?Ocs|ZR7;G!WBn)@
zk|)jrzMH)3jwB#wEXYd0H<oT0vFK4(_L??}=R~^R0KP8Ly`1G5h8P<vzM(tXy*KsH
za9EB%Va{&>EKfuFj*2yXE`o)q5^2T)uEmRb+s;#W<eEnoEv@IObl66)1x$$aoO|Sk
z&|{<ZNbC!dS^!>(kVu2sdfau6B-&kHh>ZpZx=bKR3}D&OwgO;_ZlT%9bI_Wa0*0-r
zuNq>Qq&a@NT~oVaF-Eyz3p$c9Q^}a-?pJ<@VW~P~!`lHoV)eFJ%sJiFjtxie=&aN%
zCbvb(2N+??Z#wE9_=t~v9OyonVj~)OuC`v8u@?ZQzxHE&4o?h?D=}QdxIq_yanB#D
zVUBuY*sP;tx@^QC$ST9!@x(|C^UxEcHO!7kH2_F8Mr#<(c}k4cFuRuchMMdCsRw4g
z{mW^{PeS%@>d`{#(YqtoqcJn~U45!ljQ6OOdi2%2M_<i*WY<OBBUMg4dROn6%C-k)
z-@Auu81GRl^+@?7p19C>4db)03B{r4nBgJ$p7XxO6KIQUJYywRK2!dsbw=YqA%#ap
z$_LJfOnzMqw*Dx=z!7p_TrC~3hA#j|tziWN43^k<!ay1|;Ed-F)-a2n@E!B9?2{1I
zK~@>&m?uVRnA4sZtzocSHLx49V1U{1#8?e;%@RL680=7-dNgxHwt0^f3^1q6SdAx)
z_o$V6q+p;&OD3dX!1>;znbadyPCZgE(4$jkp9USqd(=ujQa*`I7aFf&wnW*wlrIIu
z0}GMgR_XwQT4ZfR)85dDbw&}u+2vtG#%nQyro979h^*?8827NkCt{B|HNXR<m`siq
z89QqDu}Gr>aABp<8LVM2$_5t(k`VCP^R<?U88fT3mL#h$U>#(YVTR4VZ;jM2Twz)S
zq)W{U*bP}e%w<pL4P7x;Eb;M?5k0fWNIjZ*Ec?7iiVT>SX1N9z#(UICJyK-QBMu#U
z5kBwHRO*o`ryeOX=+U^@rwD*yEHvn;N6II$;zHv!3}ci<MvPS8u1xSNu}-=Y(}<>X
zafdz0uai3II!Pk4a`&Q05d$zP78x62h^F2(BcdWa7-$Rclg5e*Sm6fQrQu6+kv>8W
zQ)oliTb#pY9TqA~fQOc^Sb}-tiQyWC^PDzOOoc2=U@mz=pGFk3?1|ADhHj_^oq#M%
zU~YI~tcIa`5(+1>@aZr9P1x7Dh19tgtanbq05fQID;VgJch0U(ymKFT=RPu_4~A<P
z?_7)iKsu5R+n{*oKJd=1c*$rD<DF}z&V4Xir_Ozlcdpr3ypyy4shlR#AsqO!u_dr1
z;$C07Sp~u^`i@Nn--wB}fk|WMfHNYm1^0O?Xah9V_d=lSOS(#Qoie!!2wi2Jbd^b0
zmFx-b^`E0%OR`|ijA;WmjIDqzk@peqo)-WQnu0J0MA3Ils02bNe|EFc&F`Dgum3ZR
z{_oh}0E5t;5kaUhp%Mt8q@GRVhYDfnO=<eBNU;D=XK!-|y67DfErG|zR=`IhYLzwI
zOD_OIT{0{bd7GWQ&HO=BZrF4#G`&w`-d0P04u;+B8r(M^)_47LSj96Uc?wuDb`JQq
z=K|{@_aEGcUI5_deWn6R+g4NpYsOYUXew(suU>^MIikYt>Hy0k-Esrmu1;=O$FyBD
znGWEJ=W~U@C&kk!zG9UY09QPnE1ovR8zwUixZ>t^Mkqa{qCaDYnMD7<=2ROvBuyU|
zs)+8IXbHSDwgO&@JXGOE&E5(Kb-kgQ+U(?Q_J(Q_n$Csx3)M$z^v}VtCsKpK9}}wK
z?2p6IErpDTP!_EJF6;tuL*!0{TmNsoK=2#Jwt-{6XSu*<jBNv>cPtk;Y-}4?_gvt&
zJQuk7-<d4%8^*SQ=bj6^^ju)<Z<;JHZfqMUe&2F|zi4b5Sn*t7&2xd1-*wrK^TrRz
zPmU^a)P^}~9tcP2Ic?*pdHm&$DwCt;lcUPysCgW9$Xrqa?x^|Xs4_WfJ~^sPj+)0&
zFU(OT;EtLHCd^SK;EtM4jw+L*=5f@9IjRKQQTwh1_$WD}gEO`*fR=#W|H7lDQ^OrH
zFD(Idop9>Z$q5~taKZv-37}P%*?%B(6x;WYE$*NEFLh!%I-ws6-gz$!x5SlO3Lueg
zQa=^E6zNBvci!XXFNs%HHU*6SmmJnqc2dl&s4F;FlUNjKjsjOjCiq;;3rpy*2=h|Z
z)EfV<G=D^T-)gXiIVRFP1x`l(6*0?}kP4U;QKMo*i6<g`M)d4|t%)wug^9j}M9h|`
z5hSrK(&=~Pzg4p$84FB^%-BgWZO;d0B7a59x+SC-W+O_{Ku^a&n<j?(jHuhXZl@^G
z7O8b$F)t%=*~@^dc^QcfFZ)PA`%Glcy1K1dDYDkK#oQG&ece&wu}DJ-6#qT!;&H(V
zkre3n<;9Hu50*b6I4WwYA6MdJp0TFHHIbAYQULqZX&!0x#q2;g-G`f+Iy*j#fL&u3
zfhWdR!14dwEfo->`YZzz>y*v0Mb@5M#x4QdB7FzvY7H}JLAnGSHnt5+crI{EWYRDU
zn{+cuyS5@M0XSGa1fH13mVjsGv5kQmrm)p@X{2#NbCaG<$M^B+i%w+Hjz|%PNk>Iu
zX?oJx%bEsPY+mRh4t1lZxdj{*y;*GN_ZUu3oc`IGBp!dWxU$;K`T;A!f$mBnOb^&3
zANe0sbxX$HHiN5Vdo?0s@gt8-z$0e-xzvwyPc@^S`K;Q!t&kMyBbHAE&x~Ch*Di6x
zw$nx6j>x{l5$1*Gr(JY$LYsqcowL9Lks|!zdobS@4HUEETK#<=JqK)wB=X=rnAajT
zpLT`WCG83;BK<1!;7y_LpHsjYk!n7E59X3ca}&5MLL6kz;0K-4-Z8bMtnZ4{&ba2*
zXGJD0WKzmPrrWrP?AyW}k))YXr)?6Q17?k#1(rkz-xWTv?5U@M7sf6E9(O$-#nCmY
zCd^TrFz3fLbUsVYr${~@V@*g{eA<-k{rRT8$s1J+ql{h8XJ$4XmmaIl=c2*lH($J0
z!@Uq`$+@Pu-V*5w0JtNP%x|sMaNAaJ@rq)GC0a573$yEi^SHRUqgD2iNGgGs#!dl;
zZ2n#Zd@4_EioGrJhTtBFRC8Cbseu;@5Cdux@R@%x`D=;QwX!k12wXCD3Ak+R9N>d|
zk@c2kR(cul!#2hjC!68E$f)}=G8b#@P;v0Oer>TP5|(XnFQy^C$dLOuf85I2GdTZb
z35M^Ch?xxf>N?Ak%5W)a0Uw-2;P-7$odq6<d=`o+Y|v)M1#8X%K9q~VJ<kQ6_!2Op
zX+Gvtossnsn`QB3oYZt0u0=-857)DtsC_~&GNJwGw#fAJk+X%GA(MtQa*GU?kI^E)
zI7uK4*CM0#C!Py1dbWV1VO(UF{IW<D0Vc7Dz&y76MSyXXNE*&XMwKC@MS)M|MS#&&
zZko)CX%lJYbxgRAA6w?TkDYCY>o#^aU>t<BdvO->fw9r>6VD=k-?sU)h~GEN@0kNL
zSDAk}HAopzjW5tEc;)Q4y5e28{&F~w0Otemde+~plZ(-*AKb}XT5DKu2vqQh1+9Jo
zUg(S6RQP}wPB<Q162TM9uN89keu}WLn41EKIkM?IF=ZmcAG76P3b?6AA{!*gv|j@p
znyjXf*$E#b2Oobun{8wo?mzV^ti37HD|z<?mu+jUt_fb)w5gajK3A$RTe3`r>t<e+
zrb5M;#aFJ1`1ggWdPI23W>pK5#fEV|><yHV1EUZ2i|A?nI7cVO{ZPQc#utrq*`o2_
zJywsawkDj5m0p`+S_saih2UJ8{pZqReU8rgJU^G#;&W+opG!0P91-g?_Z)CjWJ?ze
zvsX>CFnjo(OVjmSnxp6N)tI^MT<(M5iQg2%aalA}od0m}!iR%Pnvq=nM4Af{=3}Je
z^1;%r4+n2(Rx&fAoK5dZmS($~P}D{_``NQB{aXB>R>~;HEnFBxdQ!bTEs8IFgWs^U
z+Y66lqCE97_0jX9r~KSFz2x``58e`K!pwF%%LnQ1$ng6jWv8)hr2%Y(rRZQxe6wus
z-s{l9nbof%y4Mo@CWWz%1SxAHO9z4J2I?#HW!$zIcn-iwM8GUC*|5kaGO-;V^eJdj
z%Cbo|$eyKO0(`&PFJci+J#IplY+|-hui+01S!UtEA0dF<S?2&^nVJ#I@Da`MG4<iY
zVIS{EHVj<x<Hfg%fBx7{js4t_f#RorvL*}9=#vL`)nz6sUkI<j^TXBobfP++HskZ@
zz;r(Cz~|{VeU=77kHHs9Kj;HZ2<U=X_Dx^In&T|S2kEz@G}0VAiMfYbYy4)wh1)Wi
zzK|V#(nB}K3*+C^r(*Skl*5<C>*w8(P@oR0v2knnLU=0wY*G`BQP{;ZeR~!`s8#1t
zbDss*$4+Ghgy$12n3fn-P+k&QB4(D(iffz|3EtOH2s5lcs&I)y_z@BJGz6m}Q*u%a
zacc<})>w=HSx&8habgl$f;EG^&JqM6PPatFk0qk#TvBxBW@I@sQ+qBm?D1lcOrDeT
zjZk*2x~JS%f&=<%#B;`TyRXDh(8zKB;f6?82%D=l9LEb?3jiZpI`n2DFeW-!EDzT(
zhdeP_!}z&thJl<ANgnt`k;$JF!!?+m9uL<rUld7*vG$E|26*g)wDTU!h;8*Vz#)<8
zIU?qi=L27k{B<!KmXQ8I%|#9fvVT-C;q0W~v`CMd^-_tLGoBc(XT&T;0)|_*CU!^6
zwn&<o;6#gzCQy7`n*q3KYtk?r%&n7?VoqCPS<Q(#;|Vn<W+@UdT+OR@qcvCZ4@GK@
zEBOh#VxK!HI3+R>nA4sZuG?ZRMFNJ4eiPdib5A5qPX*i{wmVyKOWlOHsm_7V?B(pl
z{d6mV;hwRT!2GLTBICty-@r=Z27+4QKEj$v5p;94hPx`#++zv6YwQegUt~?dJn+PD
zy({KvBw)A)VPf2WI4e>UO9JjYSbp4qP-3{|4#d?cf#G_{EZh;p6_F)i9$P|nV0^YK
zV$vyUhKUcEVwl$=wGI?o2fTxD!y-ikFeb7JFx>gD_GZO!@U#SsUn$S5i1oGQ*Y%Q!
z5`G;vlXii*bZVQ)uEQR_mv)CaHVNMhX8<+}twOu+!8{PjX5gX7ZHDvhWD4+O-b`Cd
z`mD$;7Q+n}ye+sa^15)o|4adFJnDL^eqv*t`D8FZ0<tx5>;3<?51+QR%K4VuN_UZ)
zLtghBGQdK5RHTu3`d$skva0uUfD=tYM7N8D``K|&fSeu%hmhF)B^HuI^Td|RH*~OW
zvr!_#jL8p8uI-E@&WhXyIA7;Gz-&_xP3zaHy7`$sd1hn6fkrZKwCkY*XSMRrh`d=i
zHU@bJSZWHGsn8w|nF8cwMhImVshLb-AxSjm;USD*3&KD|SO)encHpjL?u*<CxW6ls
zvA|AKzy`+dwZ~XffSfE0p<ZJ%iG?K5V=P8I7GWSF?2);#>ah>f0k+LEjU8;2D@_W{
zpK^A9YfS;$qVJH|_aF6Zl+md3N6Y<BOwlEQq^L|mvsckVQnZjBz1lNsSG156HBTjq
zf~$P`M{Rl!vfaZ|fz3SkipSd{Njw($$iV%vNCOBwZ3@EPfr1L;_l#1?%m#+c7oxn;
zY$#+7rwDJDW5i06g7b$19bmI5U|)x1Us$wPBSWDYJaZNcxGsD2j4tISMf(kfWH3!H
z4<tnkNl`nDl0Z__KNM0xZ5s;VPM4>`gedn)O#Nq)c_DJ2!1<$)4p8WD;{`lafIJnB
zU}B>HIrT7v#O^P#kR-A})58Yo;IM{)h_IjL#wLezmgD&5c5r@MZc=dm@TLP?YYI5D
zLHiD2Xq3^YyJ~X%?+Ktw0!h(6LzomTBt;A8bEE9d3|F*}6!i@uN~lfm!TVjF3a`6-
z_|}o!LWA2K8F7B!u>*{xf~FP~$j?SeZ@4v?&A=S6OkyV=iijKH>1d-Jjw7x-44i5T
z;xxE7Zcu=n%m|^(A|fkEEF_7>yo1&uWR^sjh!7hGd>jRH(^C|2kbWR?t9He`Y*KLk
zAg==)61f<MWN6<g3XSRl>I#$Ve^&%u5=e^niK3)vAt_owpBrUw=eVMUq^K{7P(p2b
z4{`wjPX&(lxmRL9x#4?T<ei24u1K8)?xq5rd^sWS9Z(b?rye2z^$lo}SV$5*1BwKv
zBMd}jN3@@@oDC*KZUr2VN@Xl?vMJ!S5A8J;1;}AxSE$d}B(abr8e_YkG%bj|t6fi1
zgR2xXSV|9z;91Q$^yeM%*~pXkvvxDM4NMtZ0&S7MJ=V-yW2kY)#Q?9-$!qk!b*G<>
zmDp*k(E+^1bY7$P6+D`u^*^*aZQ!}F^T2D7+XXjvw`YvQRH|PU=|gY8OJge_s+V=D
zUPU!9wcMd)8rb_rQxclah4#KB_&_QiTI(&~g|TzMC(QB|Fly{vZbk5edLwwoUJh;p
zo5n5xk3{YVxEEdke9zc6@Jh7b7`pbPyG*+0a@}Q}bk8N-Wv;t_wEJ~;(0$izS_IJO
z4o$ijlkQIF)-$(o0vKlLHs(udcx4Kk3oRthDhnyyRZW_kyQ=!qYL#8K@(OYOeC1i}
z7BD*ya3xD9*){nkm-c^=c8Pf;o|!~*+He`HJLs3iz#wGreZ%qAny!~~okfvqlzEM^
zPBpTnn!2e*C$G`TYGlVnYRvwR+Nnfp9QcZ{C2(1^Uz||ml8XUeqm$RzfApC&r!1)3
zz(bF3U{~ZV!JRbSbHHCVwhhp#ZeL*Xet$`MiSkP#Eu6r%u?uK^;kke}vXB}nY2=hO
zG7q$k%@)?wYHF)PTRWz;0%*j;7|z?MQX8Grkt(UvH=|2<O{6d$SF=B7P4|RxNFS5b
zKLsB$)Em}n8@O$31#F9aXyA6d0N8B`!nQz^t(jm6Tr;)>{I;=eAgcF=3YFJQtOIzB
zGOy9QEg<hg)45Q-=H8G9&B?oAVnPa@Sz#L({GX7kfDw`R9B#r3fTK-8QlqcsQ|<4W
zq7n$9ynipd`F(~U`dL%o2A=M#9-(6<R01KCt1pVAsgr9;9_t>eic?Z?Mx?h!mur|S
zmiU$B`l^`kMq)<{E$J?}K5W(f>t3Zt(lGRWqWG$R_X;}CiiY%s=k{GJ;@ct}g@8*U
zedqUJ4YMTrgud<HzO;q*Z$>H1?YxwPTc^4^O6-bE5e%j_io!mB;(t^{_>G^b)Av=@
z@b2?6JT=V6Tl6CHPd7bv6_XM@Bhsh=G_Tv=G){YBqorPqZmP%8N&SeRb@I4=L{L@f
zol2vVS?O(+csm{1p>Gn5E@pz!q{dYbjk^CjN0B`@npJHqkfngLt+2`78(vcW6_J0s
zQ4Hou9$2@0eWVZOx+nB&SYkFkF;c_a^2BHjgZ*+>*sk!=qX6YW_Cy8di6_Qt7<Xmg
z{Cx5UnwuhRO~9WTTLRBTJ~zVy2~l;(MBBiLMilP070dy@XKWjwp?&w3q^rzzm37ip
zC0%9GRfRn<TL#qxD%6)$_lMb`0Y&(h)vN9a+|ounXO$!|mn7z*eW7GdtLhok(gIxJ
zd=l?Fsd(k;f7a-WWHNBi*g4?u7+V4lMLrU6J66yJo*0|kVOo>Y5~WeStl|F1>XZQ0
z^H+`Bq|3^^Z$cH|cC@ML%~dWISJeMR;+V5-x=X-yH-{x3M`Un-f(6*u54j1*@3l81
z0-tM0{^C7zG%#)r%mYV7?p?T(UJ%s+Q}vSShfHb#i0WmXs_!|`r0N~2PgwN|i0YlJ
zdKIl6uygWp)i^1#>q+5Kmj?$;QxgFSL;FirK3%sZHY3tv0W2E3n2hZ??9=@(na(yq
zB<)=Tl2Dlo_3o2NsFMq&eKI<!H!al4OK%hy`&$@W0plWXAMUsp04JM*q{cavJvU_~
z@XFX0aL}r^fvDbVGF4rulMCf04|Xf}9WT6Tw4U`wfF)xq;EKrm0k`1=!1bme?+1#$
zXhJ0rLb<iG-TXa<jQ*kSK8UoU0Ph%E0u!RWgQ-s>DSzC>0I$)>Yvc`MCkEXz``W-O
zkt;UNRP|kDQR9ZyD1oR^)~QC{RaUg~U8~grc8slnT@g*{vr^(vqKHYlnk8kRi1OZ^
z_vYvQ3wi0ogx)_~IO+WZDq}0)lE|BYTk`^7y(#EbrN@FQIc|a_aLU*g@Ofj~Kvd67
zL=lxwnpg+$8f9K14_lXaq3K*GKf|BxHrE$Y*Oh(WS}K9Z&h~dkL7{@XBEJ70yl4D(
z3UH^J4?gPVgDA^?FW{hQ@g|xvq$%9+p-52;&{pq&_6n7`P_OHfrcN%@>#Za-oeSmO
z3I|~9OScRdyYGvaU|i%z!X5Vl;AB$}N&->#%#@YDD`Q*0L95;dqIz$?ih{~7tVRd$
z8f9Lix0A@b&~z@8cXF`XTwh3pxiczWbHjj%|AoHK0mnq%ceqPl0DRflHZbwOns_M7
zF)1!le8ehMKq%H1#w+EDtE9M0imO~<@R$EQEk00OmJPSfxSrD;BQz~iv;y>IZ?s|(
zE?6`-w1Ewg3&Oqh0^oI15FH6j8p>QlStku;uAw(*j!7?qGBkw5hHfxPG-`BfH<xh!
z(%;s_mPpls-!ZlX?u)!ra64Ae2A($s`>VTQq9x$!I=Q;CM%_b~0YY7G50h#v+%)kH
z;3}tqZOfel!q|>!e_#b2;O`kb4bV__CF7@7{X(U(w?rJ%z}qI)LgS-uHu%J|lU@3@
zJ!Rds><VeuU*!_c69w;>TpKvyRe(v6`xx$XR?r48YM-4fX)4ha)yo?0wACpAs-t(W
zPm_jDuAyTZPML-d5E^=yp8oz!qvN>Mnghb1X;bI@nNIy_&b#4zteH?fd=DNqRV~z<
z>1Km7o*kY&P`pyckq5Y_XSZPl{;|on0i@i!Q4>r;WiHg~swC9Og?hb_gr;+$d?C&o
z{=xhW701s3!=KbOfxc|`;6KvO0mGlRwEtW%{G@ys<?yqX_Hy|3tQ`JYRt|qZD~ErS
zmBT;F%HdyU<?w@Vr1s%QEbZ;Xk7woZ6InU@k*pm4SXK^yGAoBaot49HX5~NFv%RIi
zYkuy0I5_>`AbjKJA@}p=%+Fp9k8jP-Du;JJdU=l@RgNEbP2S7l8$YT%`O(Yq<AZ}q
zKm7MB?d9-|pH&~;{p966eo}ezlb84SN#%_v)b4R5u%D@i-S`u}k=esgBljMj>-W}K
z^WNNtg9{%HPD*R;En3OF)9(#>zmxU8zqkFp+hgDl&7cSQJfjDv%wmsQ_-39}9}dEA
zSo!>igG$pQ=2py8_;pL`vorb`Z+P#q>!ZhytlZP^?g5ui@!|TDM_iux&`m+L=jC|l
znWeox9@>B2dHJ}?Cq!W{Jaf%H3nY8t_n&v(Uh=rxLp+_e`d%ImANH5<BiZ{w^ClPX
zuZgs10~;c4fq%7_sNoq5ZO;)^k|MYWDCI^hDL2AMZ1_touA*JOaTSg5xJz|`7shsg
zE#39jqtb{j)s1e7rFSzT2>_L`bHF9f1ulE;vS7nmwQYZI2D2~51k(5Lre03d%S+bF
zh1ARG)XQn2<f%xnk);k#$83?Z$LbZ`(Ki^RUQIKwCoFd%b#OX{P|8wYmr@6tC%13)
zjcL;(^7F6oZVG~-o7Y7;QUasaw|RQZd{QnjW*wTR$IK$-#$?jd=$J>!#Scsyu`zoj
z5EDm_F_TN$#K5=>^gM9X*z<r#!hDK^^F#v98Y;f24>nEM(#lj)JF$DIotQw%olxNs
z6F3jxUF8CJSB4}fx093S!^zQ3imLf=dK6ufp3AOlO|a=~c=gAE=|lCoIH3P}|I!$g
zjKM3BKJ3I8u*T_10Jv#v1^kY&ZQ!owGBVdhl4T6=xY*?QDmlKy@vKuivEuFP#xC3w
zxZ^8;g-aT6{3V-$b9V)df#xXSE-jNwtK`x$xwHzusakT`0xt8}*nCtA&HN3j$<x;Q
z1zKlU)zASmX2`{)vH7IEdSp)Z&l??;q7$OwVy&2*_-gSl)}(N!uCR|w_9Px?3Q0|h
zR7f9RTPrP~kd=Cpv|7V>-&>f--y4!2C};}B?8WRo*Ny*l9o`()$JE>euZ846JDrVL
zzZUTIuCX8U^i97TrmF1ZvTv>1gxD*xn3<<QVL*SzbhJ?ChF%zz&CCc1oD~qtVw3Y4
z$7dh6QY&XgYu4HiTK7{pb&g1}2SdIzFDtiixz#tSOYaray`X=azfEyII_Fch^G$J=
zxhWh`|FzfyRQQCpkGH=6{ZH0ZTN5=IB)oar+~@C}@*arfN#L=u74X#9HsD58p<NRO
zy;ntwNWhz@B--~kDC-WJu`Pfw(Njo(P*kJnTrovc0D6_%r=>}5i~FufBEWrP7j^`@
z#<l>AAJ(^>Pk!nHg*>TeUI=(s7E)KTDcINSD~TU;D}iBSFN_Jsjh$C{&)-9(z9&)-
zV`MZ)sj0;@8cmQZPVJA_W%u9bBrqeNROXj#<(TW%6R-_0n?*g*lmzao@V*JOfXBvG
zz*A#Oz-NASSq)*a#+X69W^4&;dTvr1+^|ePBGRA$EG!C(SYMQj&MQ{C4Y>L~XG>YL
zb>ERWzi*bcfP2O+><D%}7r^{%l$Cnvg}^^Hwhef{7E-?!=$Ch<&xY3$|Aco07%}$3
zA;E;P^U>qL2dePGn;MmbH+4QWbv`xKjyjUFzf)q?MLG%H7wkIAy2aIma#_AuQ^ZDH
z$JwT48}X+m-X4{xFLO;(%CSFox6hbV2~er$q_~(iq{VKPE}U${&(BDkN8$M-em=xy
zQu9ZpQ`SZcm@)PuuxRWQ@SvO9XuX)UHj^V%u1k2!Dztz*#!dmQrj?9q>S|cBKWv(`
zYSkG*+t?O>UBkr(S}oSJT98`uLcrBuNa`;nEBk_n##U72+g=;kFt*wh+;kS}U1yba
zR+*i~vg^AM7p^rG+NnZ28PRNBs`$p^!J_y`q``eA@D02fQ5+Hyqs6jq7{6lwPENdC
zQ{lO2Z%J79i7t~4BPE9s-({N<qmGnB2^NZtx;c)hmCuQ^N&;6zycPhics77qvd;?X
zIeb#wjB*}#C>}EnE#Qc;6>!|x61e8Mp;pUW(z@qH^Q?s3rWUYnb*F$E#<r50#-eWA
zHH#TmjhghrxM0F70$4U&yx-lYNS*dVz&+Fk+{4+0&q6YJpCIIP_(fL)EE;?9vS8WR
zIlAIH=aT(%`4GV$lGG`y&|VVkIGZZ8lM&5=!)gDn1U(36o{4>F^=3l*$bkPM7E%vH
zZ|Sm^lM8Qfk%oRE<t@uOZ(D(@oI>Suk%A{w{<t;i9m+-!O^;1-F(f^L!$7^+=7%P9
z77DQ@g9Q4NF<{54P%zwO!g@_Kn!&a=q-|37%DTF`$<U<afJ#HpTW0dEWOeZ#nLiBk
zTR`v}qT*I+9H`=!$qALc%F5vfHCLh>o(($c!=K2?;qPSS@DH+bc)A+(;a^zVZ@Iv;
z8AUn#5leeH{A5=C!}=cO9RG(3zfB0=_&~P_;XiAA_Hy{f2P#iK@bVrXs2m^Mus(V@
zeB%R^!+$R;hi`nKa`<8Elh=oDe4z5=126CKfy$$g^zevm_rB@7b*4TXysEZ1EcAc9
zjk2@^A6Hd+GgSP;|BGuVdUD7{!_$YwySF_ZElI5J4^6p`_w(tb`B-;Kb+@kHr?k9c
zmUthrIrk|(+{w!Oeb(=zFi%x}#6Nn_KT~chZ>Z3nP~AMFN5`!P9*OWLBCR{X@GF*<
zywdbgn~&<dJiPl_BO`tEc+$!}4Zj>|jU4=%rKL}4cppjEpFHFvoubam_nUbSGyU)$
zm9C$$K4D|;_4k{Z9;M!1ic*(PBhc-yy3gNR4j=n3e&>Fu7Bm1i>t<cVk8)!=DmS7=
zxiRU)M$aWcr=N?I3%piL>o7srd>dK-eEFP@5Rz>4MH-?T%4MFN5J>~TM36vqWX}yM
zwUz#2KIjadx-v~yW~_tfQ&*-V_9YvGDwbZ|wyvCy;8*Tr<uF6_wTpCxK8Q_SnWihF
zX6gAc0p01|*rPkrka~47%+=mnNN@hvoI=PXlKcPY;B}EM*nko1)#72ngt0BUeZtr_
zux4xpJU4a`574YM0L%?t^5G0ZUo5a<Yz45CDL1*Ol?J|wXqU1Fk|Ve!3k;fzsu97M
zu`R;klIH>*8H>rC74Bpsk}?37N*UnptWuD)lRK*vB#Y{q{rz|_dr+3yUtkC%zuKKl
z_v=NR$%3OBiomY1b18<(SWP4_DV6TFssER^w~eiHyYBpsBubapreh{%62@U;#zS|6
z2{S{-oJN_j4QHYmvtwn#ArGaaOWHYn(Mub)VPiU`V}_<}+EyF3;jLMOZP+<%BOpS-
zB5X%(*hX#DmLCX2Km~;Ds2BnfFap94`XDp{A`}GN|8K2lJ$oODy4Rk1<^dMhf3Lmv
z-fOSD_RI4;=NyLHIx1hRELR3U)AMniHT3tVTfg(su150YX!7J_^5htvd?C`A2{vc5
zX>wnz)x0x`Q#~3-WBJfi$}5s?o5HPqF&rx?49BXn<lnL6-_hjX$>d*qJnEBhGWoZR
zT=~H+COeCnMhsRrOJ^^tx!cy{OrHkNt0|xO+wZ_inZV=e<GeUA#xG{YXfQAMbSn${
zvdHqXGU($*%Cp$ujQp+QIhEzYlXytyK3K288_6XzDU4>K?SiXTzZS)a11(2$Vhq0E
z?ZN`BOf=%7F-;@x_o>v#bZTTe`En}iS82O=e#us@6)?rZ)ih>T)97SJP|TjUQaALs
zyf%b9hHs`O^Lx+AR;iIqpt^*`wJW|S(hLldKj4?7Ss2;(1+r&-53KMFp0OPo9EG`2
zH<D51ZGkd%Js16@NX^2I4NmeX&r6<A$HG5%b?kDTkyLwWdyB;pgLmGZ9h9MVzRY+_
z8BKQ&I+#fRo~X$QPbD}yDU=PmHYEN%&w_0ktZ$3)<VjNy<`Go40!@E-h1KnPuwp@H
z(fKozj=-K7oa8B%SJdPYjQu}MV+0djqjW-q+Mu$QO=~)>Ko-0`3SfnFS`(&|g*BD9
zZKcXkiwXw>SoE5=QYOYDm!|cm>Dkz@a+$|kK2bh$7){ES3abMf(goeF{f7R<CD==p
zz2Zd8GY+4F)im*{Q4#!1<t0<v`Zt2k6NgX5m}HvMq27X`z2fsKZ>B15rny|sCM|JR
zz>ACuYoKA2<}pYV2UDI!5u6ssatz;c8?yR(t-h<UO9sba!!Ct+EAN*5)(2*7ccgZ$
zC8?3@UfWxlQE8skDY{|n2CJ|=mxi$%74nNyiZr;o#V;1xVwmZVNWP(mbEMqT5tzHC
z8m`g#C_E#W+PaZUPGjt?6@TlhY+5A4VY3Ej7sOT!PSTxyhp<)~-_g|CXliXTYK~_G
zT`DkSWvlaIUQJeDG?`a=<%6d7+)9;;vm({rkR6$L1cpYd;&|{AU(Eiq>xZoLp{Zqq
zbRfYC6PE3?nkE_9kbFQ%tn^^5rCyc~ab$=*P#nXezkVP;8Tz(yQ-xl+h35H8cq4>b
z-K2HTG@FKLR-zRXkHYR6EWPZ-*ClLN#t3Z3U>)X7m+B14ZHa%!G)8F7HJX~F(h0>R
ztDhVLW6f1~z;;{;+jXfM5q~K;Zy94S^!!7OsYE#{XEmtkQ!j^-P{|K3xsDdLP!Wt4
zi3}CDn$}d4Y=&hvJFKR%Wq;)X`*F#znwBwp-Rc?LEbAGK!nti)6Rg!$sc~RRIwwDp
z^-7xUR_7S3Dsr!YXgu$alIRbMQ){T?M>2J{(CYQVePR?)J)xghsp_HtnsO2BiovTe
zFI!Dz%UObpqHMb~aRA&K9;F^HJQ{^hx+qGcN+;mn^hh-Qrhd|Px|RjkM2xW5LxUr*
zrv|IAX9h=LM+U1fPC|-c7`{~v`s-J5m$<Cd9g*AyTNkzH%e6n&08#EdpUwTTMyjGY
z0#(hjv?xn&;NIvp*o#68$AH{Nl{1{>{8(2;rZmpd@<E~eRGdCF6_n0B$<UG6PsP0V
zrDalAk*G%wNIK>rSFcLRF4Ha=reYd{?}@YxKN9n{MxP3L;c~at_emstAj%_E$>M4i
zm)~c_<{ZKnL@hdWf2=%1N>E(w;_4Ty*CB-|@mg#vr0k**nunvTGgLH)I9jA*)U)g=
z`s>%3+v1R1RfxcqP9^Fh>WFeDdRb^)mX@p=DhddOerB^WD}y3et|sNC?JgRo?-&gC
z5~HcaXsSLN32B<m=wWBl9|`>v=2PNd$VE`Z<3sR)92F17!Gj9A$Oq3@+CM`L=6o9Y
zU>+w$dGM1gAIym(^1+;`qCB{o<%8F<eDFX^Di0pCv_B364`un_`79s2k>!JTvwZMV
z?HXYpxaC5!58P&H??1Rd%LiZ1^1(w{K6pLL2XAHh;3ru=_*s?@KF;#NT{=aF|G;%i
zyM5q=EFZj{<%74feDLEeAN)Ma2Y0q6|A6}~T|BN9zMtiTA7uI9$5}r3Fv|xYXZhfE
zef~502i~%@_ph7~@gy;LnQ=PUlQ>?~fXkTIiw-ciW|0prW0n^siorgMNq>m|E@M{t
z;KM8*T*j>O!LLM7Ke#7iPWj+rOMCs``&mACH_HbTrxvp+4}NK5=H<cVm?<ATZ$9>X
z@QS77Q{{te=3~zXFNV*R4_?di!R44Jzx25LSX}4ig70!<qDV8JP?B-t*EIB0(Z|Tv
zDNl3v-(h3+Rm%sjS=#f#zAkw__%O={`<Q!v8e=cd7+<zA^?b&-ZfVa4?_~Lm@k1M9
z&j<S$dwDQ7Wziq-f~7s5G4?U_G}zZ2uP?1Tp3k~-$<_tW2m3nY`QW)MAG~U5&u1OF
zpQU$&53)4t&<jg@{a{~*ygazmV$SoyLzeb@a6QWh&t>_nOAoX3p0KY&UOufuUO($l
z)neB3iP`lmy&=4vrSA)0v6yxJ;WCCjT}B%*o8q<<Com{TB<hnHu}}y`ya>kh7bFU1
zM1tJatvTEf>(+QmN*F9Uj9D!ygS{q)3NkLw9pdsqbz4#x9<|TB0(R6r$?4@Qhb)}E
z>ZGK7MPCJFcU<q=(Kcz;MLH3}_6$y>K2M}RPtfOek^c1(?7qP<y5DBKn}Br~oTkq+
zE``myG<AQ%V%>T%(ILiirDt@oOD=`g4307GbJop?1u>Q;>Bb5rb7XaK@gP1r4dT$+
zC(^$cxi7XWx={I2<@0*#)+?KM?D3Y;gTL7GlZ^p<FDeBjm{TfzTWnV3g+JZ^&v{mu
zZ->&ty!=!rQPWjd>Ys@&=tWAo%GoOAX*}+$kf(9`p(yk_<?xS*BFz9Ss~?fZ$sKAm
z(h(Vv4rAoh_q^)L<&>&3IPq{O5@gNo7721JyzOvBj0gOZV(x@U@P1*LV849jt{lN_
z%jUWfqMb!W3b7Ul#_>aNLq-zsg6-;3w@8p4^*bCETXPtlQGKUhEi&g#SC&_o&WuRU
z8DTpH$6-X!c|Ga+R8IrQJ(l7S=Txol<FK0OLgmW}F@2Cvxb9gn9Hs&=wxKhXamKpG
zoHY)+XmA=A&bt)0E-IP@-V^<RtZ4hrcfRwnkAA-LOA1|NyP~#Cu7EE6Kb~gZI5Y29
zq~>8VwzL<l-?AbL)@E=THsewlQ=u>i=(AuN)?*9TIE?kGPy+g#9*12KoircWgs9nk
zradbhhKdmYMU_Aw^>KB;E`K}9)Yo;Me&tsoM^xn11@DP;Kg|GEY&=GZZXe6h7%--C
z8nMwdVxv_#oB>f4uuai<4g04)(Eu_WT2&c?VUd*B9kv`YGumwoMp-FuJ4}N#`cx7h
zq|q1&3}Gm`M5>J$HQ^B7x0vro*^&<&GL78tqp(3yVIB~7%RGGSo-A)$_29vbKU4?K
zRzB506E(0LW!Kp=XxVp}$`hZ|-+Xa4l=^8pbIREh#VLs~U_FWS9brG!`Fi*-<5b5`
zMf(fFoa`bEX3+SMJnJ`j+0t$wqsZ_@KA3Tf@?Zup^1<KhsczlMdwXv_wRt`Z?E9VC
zYKoPx4_vpjmtPR(4l?Y$EBqi!gZC`$`r!9F)paVKVm~6bRxR!R+z@8Xk9;umKiX&V
z_lY769=5c%4_?diBPf~W#qpqsLk&z3#lAi$(2A>wQ|YN;O`DVsjdZ6&9x>diN_6@f
z5Sw@SLX2o;=5~q`)zXN7)=n0&ENR@F@Q8`sp;h%t%zDFVK#*5LOv)C$(S6H4B5?Y#
zGkf#EI^*iQLPV(=jb(<GxUD20Rei)I))JG&b`A42z7AV9<q-mq+Xs{%ixY(25a_u`
zHNFrlws%;E0z*<5@#yLxb_m%8Bk-gHBko*hO^68e6o?q3>4-IzCghGpDh*@xbN%c%
zLD&&)o&h4*s3?LC_ek`z5W|T*Tm^4eTzO&8>&KBHNr^w#0j-HtX@rfRPK)5t7kcc2
z$Sk3vA~*|GQWyBZo8?#uTWVcvPZ`H#R;ES8YxU_%g1pg|6vi8kbCoYFHUM>#kHOXq
zPH%`oGLPVUY0){&P4IvP+%$~X`{ByhE1&$R=o3FVU->~DJHGtUU)G_69qy57j=>H@
z=XK|<)6ubDzXDEnz}N$EGArqZi@OweES%Dq7u#}pPmG9^6t*vVL)&CM7JbA_%dFxH
zhGZOweozmz!(7SvA{KGGW6?Q&Bu0d)F@g}fps)9RSuZh(#493Y!D?kzR|D)pI(=7g
zM<gwnuZdL9)rd7wS!|zkB0YD8Es6>+#lk10dy*1&f=|T=HNn*~ex{3{D42h<QZZ31
zWb)~WOT((m|DMQFa!>Tc@~bfP_^5!GzfQ7G+1)m26}B$Yzf3Qj*&tdJSkkW&Eted^
zh?q<<0_cNf*-w5V3!Cc^Hmc~EN<J6a&DSp|x=6efDGx?Sm3bsOEs&}(54EWXHI+z_
zHkBgHzW24MxR3&o#yUt?#(F3*QTIgDWN?a^(G)Y)v|3FO2)h;tRTzWcp^30)pO3SE
zun)@RVNp$CaXrF9?Wd5arjV$nkf^4Rs4{R|XY36yhuD)J%$Aq93g(H^{<25$sg*O8
zcVH8ubCs`mH`twaT@GW|wN`Ygz8;aZt73-^?`s@(ZAjjM?HjDZo){d1`H{C8JB?~c
z8%;HBH1BlEgZNhpX@#${!ap&ot<gS7-eDo`vqiSbdVAYpdN`0?!kv3uc4E48!x`?m
zh+@sRQdn75ExvMR!VU#Sv1TRBgEU=3sE*od(j!}AMFG<zJ}B|2p2h5g5*oMf`r;iL
zk1*sH#+z{y<nCn7A<R!1BQQ=HQh;q3til*ptwyZMLpC<=aNON+NC$6=6pT;BUKxC6
zPU|GoKvEbxzv^YH_Z2j|ldrPXxA`#9;{}87#ICJkY{)IP!d2Oj*?J{SJMb98$yheM
zsyi$jOG9#oTkt(|ND@{yRbjE1Dyz770<~<N$u!B^kTuyVPQ3Y`>DQE15hv58&_EZZ
zCLtB^84-8lH2u!@5B7_w6HUKRD0Y$%mE3lEf3<rgp=KSdO=GS*KNzP>xhE}z_MzEs
z8$<h0a*v>%9CkMV47Cc<{|)m&IVsMcJFo4C+BgZY8glkz$pE*jT&D<J+GZb{sC)ZK
z_&Taf6mN9E^Qt)BxPjL!?QfL82U$M2Q$|F2a9sfq<-yaI_VQpB%*a=BZ@hS>6>nw0
zrCoZf0sgkx;crF2rCrKTc6ol2UCK{(d47{!*;^C&RF`~MUfe-o4X%a{nS<-yG617=
zs@*SaL4$UOL=q2+tvNi@*uJ#!t+SX`MN(K5+jm&Db^=^cntlF4WyNl3cZBa}X{_K8
zQ{;m=?p>&S%k-n+$ftFhjP#&Fy=s%d>tEJTG2bIU%sE5gopKFH#zWq>wX0tKgzkPm
zY9ArsAsk;wkfr{)(i^Z#qL#`xzVqP*X3v`QZp6T5HH1G^Lkw${i-*}7_!OVmC6QNJ
zSHBq6OgDM>MsB?9;40>_Cz9l{U|pmo6*gmViZHmWf;x_+p`XHfrigT54-HPjuw1&)
z0V$-=m?AV5L{eB3^C+2$!IG45nh*&_w^ReYTQTV*jNTD*sh3kS(y!P17C9wn>}n!K
zB8(2cRaveK4(g0YV$gbfvs)dZoBD_z?4iLr%)59K_S~hg7b1p0PeDIi`DlYA!J}4S
zEe3DGIt<ofxF#!;JarRK?U~}u<er<j2fy%39b)d2I?U(OO|@y4PiGGH>Dm=!d%|^a
zqEu@z(dj2^`z#x?Oj5RRx{dNB*|BQ2j3!$~v85)Ga?B=H^kO0jrj`wzGBRt*@LBE;
zO42O%bhixnc~Lxg0S}2<^|9XdGd$`dg_)s&2meSE>99A_;lM}}Lcb@9G?=qQYvtV`
zZ-JDr9BxzeHA+N>BOSeF<!G_*e$mUf^=hS9Ct?^1C*PL!Z&g0{q2piIU0M`ApF1o5
z%|WxwR2TG@`t)W1<|A5zF{+ZL!L5aJ^}lYzuTlt?>hsJ)IFoVbJ%bp2l`<|R0;o;w
zuE82?N5m(r!^u(({|bg{RW7`WGX8uZk{E_-iLr323Wi4ot&{x8`(6r92dffqQlv5s
z!!La2z@|5eKJ$z{neecmPM(>@Gv4oM`rU1voo2n=a7e%DufFq>x;@PvN7p4y9+<`h
z-qmT?LlM7`Hm_f(0{fJmhCLFgY;wXho6}v9q}yWL!O^5xmu8q?^3pUL7iSGg)xYw3
z?Q3t!8B*tG%mMY(>pE*Oy<s4tS3F#&TXmU+Jj`q!ta{jqI1IIF3QNJs)OwhTxHL2e
zCkA>?d4%%?%_QbK@k}4ev@9PKMH)OLdRym)FIN64MOaDaGZio$&QzlRQA_wBP6OeG
z$PZscI-C&ca73hI*diTXh;%qW9n&CYSN7TnIq|w6V&8wOu_nYIYKNiA^wXd6-4UV-
zIw_>Uyb(rw;R6lpD~q}+jQiX3l}|2f4WcvLf~Yi%AoL>9D`gOlbjmZLd&(d<FIp&8
zhsEk5hB`Vdjnq3$wWg~~pNN56iLu86Iv>#eO;Ky*n|kB;1wBe5bx(Am@-^+ldIu?t
zgOUa*-{7Vm3d%NWg0&kQxg)n7nCqr^>f&Cs1Bz-jU9k@LTR8Mw<?Zh@TI7vxk*b6B
zh;*~F*Z^EK`3P*l;1m;m*x`!U9fMVvdwwcBZ*}AC15=rTJrUVM)MJ6-wiV_J!_;NL
zsz{bhh~av{Gy>&g8hcr$zMJ1q`n*izaa^q<2MiCMm&f%^F*)-lx9jdJJFWDYgKoln
zRUE}vxJb3YIt^BF&LxLw>AOh)&X{y`MU3cDG1xPg!j44eD&PD{13;Ih0wd~(I3kb7
zSm5k&*0MytRNjoRQitrL1o**zn^Rv$2NMw|pI;Sa%sE@izbn$MFw7rIRcF*uo=r#!
zb9e)`Y|<)>jX}}z!_7;eY8_BT?7}J?CmY>U-;?@|l^%iN%j`h}_WQ-WUlTD@Vw{6?
z$bfO%%nn~u(Yh5MotNKmFXE^`E$gD1ZWSPaO8u$Omo(I+r;GNZWxP$(TUNZzMCrEX
z>ZzvsOwlqY<Km(w>QOPHLTrrKx@Yy-@9#Y~IGrZy2y5K2&DoKP8f&)(M`*j(VV{`C
z;YiF`9S%~Mjo^n>k=zbr^6B&8u)7AQ2|k}*_5l!&pz;+8zmO-_*<vj_vP*rkSm7zm
zt{Gm3T`_B?9*MEo;59md_2B3Q$ED1LsT=jwjj7a)I^Do%$|d8c?o0GQq>-Z^&kfdJ
zi5)wHb=X`{d*a^HYAhL4_vUL|{n@szP4BA@z6xBUJHAX_gSq!JmrsYS@-s%cCDSl(
z{aUmxg*P{jU+-Gu=1gyVG&Me&8qXXxl^P#SjZdY<M^ob`?_vsD?kQruwHaFT{>`Le
znPFHwcxKYRIYVpSznRp;%$xfcIR|QPSncT75MZ=i{+40%wiKj3-%1AE!XWysDx&*k
zi4-iiFqVKR^HTKOO1`=kzADwCJEb5@_cg^+bc44jTA<R)l+l-xT(LpCIir^6&B&Xu
zMT4U-H~nVRnsXMnk68H;7%yE|)UuZ^*+*VzVb-dx!o0C^kkeX91DN|%^p<M7uu}O~
z8YGTHS|?!i!GCLyk5-X-<(aSvvuHZ?XqvXX8|BK8w@0CiDs(|ND>Me~vr0zj%8<j`
zV!pcOD_m-&tUC7)_^>o@x<_>^TXkcw`=Ylh-=dR0(TLzF1yxy1^`#)SHI{m0D<nZt
zszv*Jo-<vTzh+HO!RW~cD&Mp(gfHl~u4sKwl*>pnzdlg;y#4GHdSO(qcc|7m4CFG>
zSS8t6zI0C6Fh-xxDt>h<BybGmxjDD<pO-dxA+z#}l97f!Tv#sI*X$R$5Uz@}>%!>a
z51r8Yl3uh#&wniCl`hZ^d!Z7Jcn_8E%a0X)krkzbidw==?@>#5?LAb&iBd5qs-e=G
zMML4i9|%x*@=wee*CVL(vDLI9T@ULdO$*R<3}VP6%_<Ybxx|Z}2U1_ZNRUb<OuanU
zY6mN?G+l0nOSSlf>+~-g&y=wwc{oEbI;}J2*)n8a|Fs|LKhSE-9vK?}IJyareu7tI
z>Kzd{It`9J0*n=%#daLaD)PAW9xA)A;EuUv8it2BpX+DUqQgZpI<1e~@uO>DRgoKA
zFOt!HCC_HR(DvHT0%e9c#2g>>Yp`Pxi!uCf*amhDHefD$cL+Y?_zL{4NE<$kJx(RB
z#P$ZJN0)8fuZ4r99X%1my|@+SaIeJST|xSJEE0sV8Jn^=r#f)-NeiZ~?9`PSs#DE#
ztEO&R_6LF2T?*B0yI5n3Q(v;Yyvx(c?7qrAunNoLb(E!ohf3fP{lrQ*L@>H5n7TL<
z{gO1oN6_scIGQhN{;rP}(O|jD(=4W!g4B=i;f#=5^hEajQ<3&qSc`|jFuZtK59<(V
zm4#gtY1oES%jHUt>Lt*A!OD!lc=xI@L+}L?S7ECLuSch}yhIHOx>GKE_goZP_Df+L
zEZbq&?B|1doexNLdM3<A)1Dj>*191H=L#kZrc<{@(!geq{HDXMbe5p{swm6?-xkR%
zI(*>prP#5<)Z81758hF?e;S6{ZL=TNsUZ%fI$Tn%cc?sPN}5`@l{%Ci_iv?0y%ilg
zjjyZrJ(2EzVRYq#dfLO@{%%!<&^kAOO+o~iq|eaU3Bok-HY;(HCLZQdN|O*ls|mB>
z2v|I%X`7<eNhj{QFqwparKPF$=vx}JkOZfv8zK%O^Ez~Z?}-$Y+hPw5j>2%nN5TnL
zF8st7IEyUk5D^~w@hmg>s!$4#y{A%m@W;c0Y9=|Os3|=9o;8Js-%}|({+`Xn2&g6>
z0ojzsqOd7O<UN~<5qi(&Vq6m6l;3?8*Knc-eJ#!6TAHu56yE8bhV6FyDyh9FYE_h;
zxb8^dz?7z9sI*<gfSl8SG{W(chkFIXiKY_HIwxn@(^&c}rRcgTMawBDSrBQQ<45!n
z94&%rvQxEzqnqH@FKTm#U60Ci%1aKro*Z^PYRZm*`JE(H-4)4oFluG%j%vYCFE}a&
zN6p}{(YJb~ik0Gf?_)SP+cU727dwM;5FgiNx#0ODI2zU>qTGuj_KfnnD6}k!PrygU
znMzlYlfN9ZZ}g*{HLi+F&FmoETL@3St&{;38XXjAUmX%-?-SHtyUttwvasIVxyam=
z6&s=0glS}bxhw%0&E4*i<b|o0pZxL8xiFh0ouy{E8++$mv;4k|)Uu0?Qi<G(MavFX
z#Wo#oi9K@oSnP?zL$Rk0pNV-BS!eK(3rnY-ucW?Yj!DAOg;uZqQiJ>U+PWl=qIgSe
zM`X|c#N+b0IIJXP@Zo~^qTxRK2@?84DN18LIBajOEt&K$#pgI%?%xo@M!_wyyAJP(
z?K#{Rd+IRker+;*|9rlzmLT~Y8+Jv_UV7c*sNX5{w#4ZIWhjeb&E+LH<(iW$K05~9
zRWtF~Fz{nb`)9|%9a=piAKYhY&j)X1`QZI5A3UoSG0KB~&C*^T%qxh<KgHZ8k=yQ{
zA8WE*pC7~aKQ-GuA6(k5{A9c5H`%WIWV`1#*{=L#yXQCAuKX~xML<parT*!}E5cev
z2kswYy45P@U=(7ESr+Mlx+aD#f|&5a;VZERs#?+>Rf;i!ZN)AjsCrLamzAC{hxjMU
za1d?8yJQ;b)qWFc>h*J;>o2Hs9~@6d^=HnNn^cGjJ}6FSv(JB#+!pCpqEqd6iv(f)
zqL#|nzdBcrTvjZ6Bi$IcEEjJrh?JYWHI38oSf)twiOAa-C>=K)gPG~dNWbho$s0cB
z!J9E@(JO6nutDq5WXv2%nKTtOszVJ7`}KK<=!O(9f7zwU{K+jzuvZGO7p}m#cgx?Z
zp+~I0fMri6qbDk65ov)jwOWj2(}Lg~lW}jl29+@^()%!2O;mm!jRgJuQ2D_!`y30R
z0dqke7rb;xzq_pi_9;y|jHinaq^17X>Hn@P!eaOeMUu}v7eBOH=j-@^C-t(DknOb|
z+duW9*OJ24M7(|HpZ0+X?CdoklQe$<v7^*|5&nV`t2%NJqf8;eIT^4lLgR_}OOeFb
zb;*peZ>thwlE%~#RAsMScO>zd`3?IlNjQXm*~SM&@XD4b()eLZjYK+DfJjGkk&Xt>
z6f@O(t7rbopr_eqz@p=_ls?npEEmH*Ey_grVP0gP6yvu7!q`j)d+|{w!ZDu~WumY$
z`-oY5z$~)lOc`X0Cx+_02lK(Hg}sudajJ#Ml45yP#2Ffn=@P>jNgZ6nc1go#K}^4F
zV_L)0KBl$k0ToL+A);b<T_iDV*2Mapa<O>kr{g!yKgPvRUsEvp_?BYVCKw6-=Ft?4
zp8AdWM;ocvQ}o*VG)12_tb0?iEm0Jpk2BV>DLUq6+rNXEQ8NB(CYWw${Yt%<k{QKy
z=De!V#Wv=X;}%nr-HFK&F5_ccu|FYCb>(~2NuQjzA3L;9hcdp{#EhV;-u0BeWcfa0
z7&5+t6Z+t%B0gI64gd5N$)ijK{GwUqm6BcRO4I_TYgsMP(@>$eP@X1IVp9zdM1J8z
zXD2%^srsbrp~$1$euvz>JVqz6SdW}wSnD6N0zH)bl>zIt!OPa8F;>4Vm%{v3e<W;U
zlU2BOi*($D4T&_t&mMn46P!d%#2~_N=b33#%ac4Eux`-3vocMWoXB;e!$i=wNShmM
z*Wk#Oy0BxtnIxv3I)ptF*=LymM<ySERjg~1ur|>LDqq#7f|l*qA4v0<mLIA8)F=1`
zB&jYD-;pLA@hT&5(<71KW3lH3M_?~RdPlR^0B~=w^%8~)<uh2n!N~!!D=w{y;V@MP
z!&TBv9-B0u*q^f%)@r;YALx($6~IF?B5hr`g@^ZoxW)Tihjobbv(|hPiq7<kq(o=-
z9MYL*4za(*46!dYW36;y40ArjV1|0$RWN(mAr^9B<Q@HC>@HOFzc}=Hr5MLIe_rXS
zw4aIO3Rs5%L~%POyB5vF5tu{!kAw6>3f5x!BM%L$B+I%gg55S~|0K2Q6~P>i!e&ic
zO?B{Az27|gPAQbmV~PE!{n<1_K3i(oN0=^KvGQS=MV>@nY$g?(NyRuN@ad%NOrY-D
zMb@B*MdPb_!V11(sw1#r(FZ;2^Y(TZ!ClMeR90RC65Td&6}BVtuU4g3%^GG&2hIA=
zMZpi)B3B$OLwLr%;&Iuk%UZc8!LA7>LeuXeo|v%gZ>xPy|Dg#>m!Gu{h2h^bmC~WS
z%3PIb!^GEMG=Sw_lP^*$Ymz=SrSdVzc`J!}_De@^X$+~*2jf@LVEjtd^|pPWqQ$&$
zGlU;d^b-+JL<|IP=)uRL?78R%P3g#l*%Kc$+pNOU1?Nq(IH^V}7i1i*xN$d<aW_Jv
zwX`C8SN66=-9>AlZ1t@D#PbysmP7PGHP9}RH!zhNn2H8$$tX1@l14eA7@6ug)yO7|
z(|k-TOfI+MozzM>*Z8LPC20_iKgfUQ(tphOt@8h7G!R!sA8XE9GL7GKy`SW4Q1;9I
z9omeFWW(iO2OpAfSj4y9X=WuggSamGSaa5wP2-DMGbmB{$16*Uj*nA~+w#+|>xM}T
z1`XhZvz4FA&O<*}n*D($olj>vpDuOYZqoT=rjs7vwteVB?d?DKgX;a6LYtOZ#o>-W
znPHc&na(HelOT?N#;{wQpWxCj+^D4we^~9LdQ%&EN{)C%)T)oI{9MnMw8h?0ipsSS
zhG%qKlYq@z%XbL1g4>N6!NLPZP9^L+%@1sk)V-IYY$1&bzMuTDDvRf2U^c6GP6b|+
zwUH0LV`=|YPB2Sn<bzqhqC9vj%Lngg`QR5>J{Sj<<%REA+MlC=_p^L3udkzh@Utu*
z{4&c2Ghw5CaLv+QKe(RdgLkrgaHj?;%7fP}?d8GSSw5K84PhU+*V67k@IaOi9?J5;
zGg&@(F3SfmXZhgWEFa8!l4u{?Yw4nW;X7GAn71|2Kk$PrAN(}S2Onqo;8uNFCdz~P
z7I(A{p3U;VmpJ|li&K9l2`=MQ&m_S$izCkmmvN|k@NSk5F5^)7;695JFAtuzwEt2n
z`14slxQtWkS9;gt#LI&@PMaT;58kr4@O*F?C&~v;m|r{}T>44*nV;0t@At)?%I&un
z8rXq|M@sBDIMz?D_Pc2PHupUXJRwpkm@f;S1>W^67&mcIA(+uoDF$W3A&fBzEykn8
z{OuLuU*BLyVS8B?OF+Nes|sO0d%YBR)w37?ZV99X^EvEV;2x2(V0_vs%mDjs!6<Ak
z%K~qRREoiSnPt5au4v*Zt3#~cA<U<?Hw&KdEZCMPngug+RRQcU%X%t&(I%YN!eky4
zNfpMoP@)#_gl8>_F_onSW7dWi_{g(hK6$-vaJxvQV1uG4H6%=oDocI!i@<ziaB?&z
zu5=F;b5)QC@bi5=W*}0H=!A_`oe{k6FpXfH5xZ#qsl!-A-_lc8`%XBC4bOw&O5M+X
zr2$yCe%5ipp+guRFcpAzsxC|8de3gTlFC);B0ZXhc|Si(KZn#o-2$Y3ewKb7xfE7W
zU*$x)JY@a+ENs}|B)#8qDeRt0>3z5L@UwJwUahMM*rMpXj(7U?CE&8<*w+>x8vHCh
zylBJrSy-Q_&<Fa@X->l24dty1eN%7T6^1NT%19NYU%k<YP@q!doV{mo0=6&WZilbk
zg56IODIO-0pC*!@Ch$|A9CTh~b?c9>+RYUcuny5%%CVnsCE<RYs0-c}>4ph5D=O7U
zY<XS^s|g%?N2C(4Rgs(far@poE>%`|mIEgq#&Z&f0}&?=mUkL>0T-25{3o|kFe5ZC
ziq8pv7euZ4G}0&SYn7zjXV>r<>#uGAV3%!y^>0gqhdhgA_?|=9jwov9iJ#wjUrSEE
zhHE!Ps+MI{9tYwVRzkrUF;+f7mNwQf!KxT15y4CH2n&y(%G;$>cGZR1z4dD^Y2e?%
z2G)N`8F)rpFm_!*EMrp@WW+o^%R4Mt)O@8kckCkH^;MVVtVqweVfPJw4z?#Mes~o4
z$Z{s>L6153bFho%;3a$72JZ7Lm=D$@%-#MuSWQ&aiU-&Q&s07K+caqZ8<D$cNny-{
zLLbN-d-@sGFWYlKWNqqm`WaQ8{UO1rC$*DXKNl0BsGmXaw~_uF?2_n$ZV0IiJm^_4
z4-NYk_JT`c%%Gwwpa;z)?7m3-fgOknCE%jP(C1)Vq9O;_Z6WnJ7&~5(16=hS80&hG
z1FYJ_{2YvMDRMM$cF|NUSrTMl`&FvUsVgxf;%!dxuI{#ydm{ZJEo@)JPyH@b{1obA
zJ|1Ik%Yg=+kyeQ`%Hza2gD5HNh3LHM(E<l#z_gvjxD`1J*A<%u<8`sS4rAn0Q>VP>
zLo*&jg9QwcuWaKn7-2Ib;<G7x+!D<;{oJbzN(-2}R9rIl{V$u3r~mZpvPysNhtE4Q
zfHh5f=Z@GL4x2BP#Y(5u2<C(EUgu66><i%NwqSAOe4itxuS?g`Fnk}6n4B$TJ?x<<
z&R?&DS%8%V>o+(GV@VDzaMiMGiRPFof5Dhjp#|RYESMiWuRRq!7KK)uW>k+T(qQJF
zEPxFfJoOC9T$C2<sVFJ{e|HB@w$mte%E8lulAqC3Alcuv_?v_;U8lg6Nb^ir@xlg(
zhOCiX@xtXbWZ|yEl*EgwM(0!5ioqI;@4TPWznyFx3HUl+pHW4GD3dRRYJFd#7lk;*
z<~ziu?+W$U6?hUvxXxSj)?teVYb+tVE@cT}RWE*Nw2a+4A?&eRCw7lTvKvO<UA;x9
z*im6eBI!gB(>^y!zPQ(6Ga_xjFkj8<Fb~joU@YNYH;53W`|x%PuXkXCt1E#xzN=N(
zYo~akS9vLj-yxP~T?(5Mc~v07SkVph5U#_Xid^TF5CQEe5OIrz@Jk|f4#xM{)h>*a
zjO&9uknKn6o+wFCIDw42;Kw3W18Y^(q5>y^C592eUS$g9@*LwqT&%N%G(lQyM&v2L
zic9a&^vkftx1*$CImSU}?3~yps3(!_V!Too<d+3*JA}=O>}4Nd&g7%8O@ov7#2`Jm
zBrInv=q9;e+i?gZ6o0t#RsA-ssQI^H*+sf7^z4V}E(+R@kN4Qa**lgq31ij8RcXnc
ztSR>D7Lt=YVow}C6(cIu6_{3qH?>VxtLP(UTKsCMezBJCjgrwO%6}VH@~<k3$bBi&
z0i}l!5veia3%XGGEuDcr-T*I(dX)C3`H}*DO3zI6<FWc}$6xL-Rk@^rCSm#4>~|l3
z%Qg84NJ{Xpv!etuWm5+IyCO9X+Yx!=T@A2D_+*>ntkXhn64osWEih|zt4yTcu0~q1
zC)bp*AyVyoVnnWBM6DqI3CK?clM!*wi<_9&esxx1QeKV~xs~%DeDl}WxRW^&>68N_
zO7(soHej$iB(~rXwjs)XR+fnL#j#36Zi`eCjHt{MBS@Qm&NYRm{dZtOQ>Ei2js18L
zzdt)D`H<(qhDBu_i3!h}5u0@gBc#<87?F)xV!j?vr@*cf*asHP_A{F-z087Gf>n+n
zZ&x%n*`7kw{>y@gXqAwJKKka6EW@_z%{uyR-U!$3_YPNS5~SNAbrwco{;2N6_2b8B
zT69^E=TSRN)OK0ORbfQx8;eC4|5$Uq7STn`DXyz2uB$1ot0}IlDXy!EIlInO_7z#r
zL?>V66T!u$+&5j6d}XDVE5E5H8(=>L)Hs>4-Rn^ZTl_`Qg^Fu|hecXj*TnoGSWW9=
zd<u&lci0x98q7D}k+k{N*l~AVfe>JujLL}v#zyU?y{&dhejYHlkHFZ`-jc=L%UaM_
z3~-Z5uwQkH1k(;xzPYNL8<e?BKCKd^OU`VTeMmz4H%zZBBE#xpU6dEE?5gQv5sErB
zV=SJD##nYEGW`d1wNjSP#hZ?5QN?@mMdh*t(M=5zhqQ1Xc-@B$cF*7l1Id{!w7{+A
zhZ>9l)?n_7ai<<yEC8D#H3QohMHcv(XW@`_b4smKL(15zKssL4;y@K;IXn5pw_nWX
zV59=Dn!ynmVNi}R@$gg>H5>~Q9FZm*W<3Iy#e8=diK!D>ae|3-a&ag1iSlth!($S6
zauyaVW%Zfxo_fzQG%p^NOTW`BJ9U$z6KRtRgPZE1G-^#kYTuIkeO;c!KiP)M1{+&x
z*x?G~yjGD^iV%D$_=;p@1lD;5Xul75#o!40hHn<Nc|l0JumzF*Tra?Pjv79BY<?-H
zAV1f8!TxJ6hckAJxKRMdUIbSA#Wf?%;(!;TGxi-OmO*VaA%u5{E{gP7q)TE04)wRZ
zdW3pKZ|SKA-ve!+H<Sy6i>q7wib!{Wg+z=dmPN0B*{ZY1(GxhK?3xjt70FkyIZ=zA
zMt!WoL|zstLx26UxyXo6op)e#P;f$|dj#sD0(=Cg3W=kp+;wNqozoM<b2hj*1>&$D
z_&n#ok698YwCOd34s?G-{~tj=7e_m{MKTSB-EMRAAhTI5oEek?LlJg`jS`)D^+>A0
zgVja+8|!KV<c-?L_V1P%pluQ75wZO;L!i96gzBRB$0`&;Gtz=~DW1yfqEMgct;z>}
zqJ@Y1B=Ck>f(_?+Bx)}BlqqA&POd>>*99Lj4Pm>qDst(bh!&|tw`s7t!I3#J?3Guk
z)cabGzUHI)mf!prQ<mBWL}<W=M6H$O%FnAWpRoVe>urrittf)Al$G$;ztCgf1-l<<
zeHI`5P}KB^zBLK3@Z?EDBD*^Ew_7B~!RiL<l(=WG3fp(7{x)3~l^PbQ_b^P>V)Cn{
zp^{_ouFF4|Ee?{LxPDY=*#H|dScg%q#~6q}l@83^V?(j5r0ak-L>eR5rpPk{?9%>e
zFN>%Qk5UU-`9S4i)~UR1Q5j|==(VhX4T{P<5?5T{VYaNqiVHkQN!)S4o5GA1v91WS
z1&6R@gCj79b=XPkwNt3D_kp@DiRc~N>m6Mdgb>45L=jS8EVQ&j3cN1LRt=?WS;3|Y
zmAZX06})We5lai&m3-Nu^!p9*vUD~?ZyY}5+107PgCbc4!|4`x%L4R3^5}@<Z;m^R
z(n!L3MII}lL6I_GLn6-r(UdY^)iOiCu9g4=|2|jmwXXfOmewtitbqN#!7<ofQFFLc
zVn@<HHl-@;!TTtU<w|2sGnV@Q&})KG@$1b||DU=N?1jO)n;w4=R({I506S-J4AuhK
zmJ+(oDRFF7jlsOc)x1Qrsd;JYoUtaVu&!Pjo`&@qtilFe3ag6T2GF==RACck257@F
zrpuO!ITvYK?YCCPU=yMr)<*q9+&~WgNC)hvE}p6U$VVDvVa<=I-(#obhox^Qj`bM&
zrsCw)MA{T!(TTA}bmC0~qbE71SGPnuD#0)fS6yv{k;({zJR|w=Dn7((o{?9p38&iH
zm8Vl~w-|K@V&ba9X7yRAf6?q1fxR*~h5D?iPi5-mz^q7X$24bPFGc#HgoOqG`}L7v
zYPjtXMrEb~@ByF6Y8Kp5*#{zd7v_doHEu}x(Rx-wT76wPRk)}8$5vT+tUPOl{=$Um
zV=pQ)CySOvY8duyk$x?9p=rYENFlMibp(6nMOqtS3!)F`qofz!KGsvz^qb^v%{}Gb
zH{~kqj|`5%c11orlHDM@bJx_Wus<+32BWUmOHj`vQ>wx)|MYt+jpa&BbG;m1oikL?
zq1Aa6b|gAi`Hhwa;DyU!t!hh0Z&<rXJH%HS{Q{Rveib%guypv@^2H5L$4{94%$k{R
zX#ieYGga#C@;YEWBKx=xpefPoO3l7}pi0~~*6rs?;=r*62v6k)JTnb#FJaznGKoUk
zEK(CFy0DB+&)iVe_pSOW?9UC>V8^1@$55j#`D0TXgL#Rod5L_ij-*0O*<s?Ww$rC&
z$!nB+Av#xi_jXe#)9bH`)Dal%o@Nhfv!*r%^AfeZL~f6sdX!36bET_U+bdF`xf4b&
zmL;!Ia#bXw=d*(DQ~KNU*UfO)k;n}PJ@*V){cl7@8mLsmpec^QqK2^ss6)jR4X~&o
z^-#{$g$1itzWPAyqLrv#E=n{-hBwIH7HMXUKDF{S7_I7q=qDPlS*<k~c4WWjLT%Jk
zw{l}Js?i4r$l>xsB09sOvz1E?IErU0gN-Pl*QMP}-X-I)h#siPE7oil=DL@WXvM{_
z=LXBA)f-1=(=x_j&qO}gKwjd+EYay#Sy{agl~i=VD5Nbgl`UKIPEs;!jUwI}=nbuD
ztygB&o>wpe+Y+fg*j<rUyTt~8>Lm9r@|P-H_*!q`Zb6?OmeOD!C9ALnk;f`%(=%Xq
z4UWL>xfHf5vb7ZOz~m#aM+U10Vn+^>S%z!{Pi>FoZI3l*d)vy5!Mv3(e5C>Ks>f2*
zCpt%^9ai=#Y{OwvPYx;;_+u5gZCX{>oJhZ!)Y1T8h&+=@H^mwyUE|H>T>O-F7LjU!
z{er<U*r3Q=-Rv7mTyiy-m$;gjNVDBbQlj5VT!ndwYk7%$aidJT)OxH$74}yRj=`ww
zG^;4l?P@SDaWyY-(ke=HS&6GKFL5m|(QFm^ou+>c7KU7FS^(OV^I=n}!YK2)wMl6#
zS86seDP7H#nr%u-*K(z1o0^A@cwhM>13m_OVQ?DO@iQicT`@QfTNcrUu?A?}Ghmx#
z2I$x_#$XtwyP4)@Qwjrq+giN}a|33Q0ar2LwpBL+3j?m20kow<acc5vYVyQ6*qSVk
zVl+B$jb4L!qc>8c*JyOc>b^mP-pmcy6O&$pJr%M3!)aCzb5rX#qKjuLw1yWhRQ}(+
z_DZEGLW-r$CU>t)=`*Y9uzrJ8m>XD!9g8&K&o%%H)@nVOSjWVBB2xjl`|HV?0u`Rv
zQZ4sHJZXU+inLR}o*Asdy!{cpLR(TuP2Qr<EjGxvVBTQ4t3<=E^VHo@`glpys?YlR
ze>);IBjUNV*q*^j*mIY{+^k91OP9j1Qg>#sZiAz+K9|D!U5cx=9Kz_vX>Twp%c>JM
z=~s5bTXF!-^7buQsH|!HuQhj=&6SRLky!?>W<_R~#k}+^Y+J;mbhx{6HfmBG*{wv_
z5+nD-OdNwf6Hy1;8yv$MT_VkMyx|RI^Yg^EM3WmT{d*#H7UmUAQPG@LG?gr$I+nz(
z&F^c&@Cuv9S1d%TuqPrNMei&D+W&qmilBaxWdR1Okp-%WEUT>c1W2un(aP<A4cn(-
ziy~jOKv#ajGGIFfZ@@Z#*`%;}gEwF_`i9jjHFq^SrGG1vcj;;)x}=P}LsuKop{9RC
zbD}>=`uR8xps(lu|Cgj*T#H`F$*W7XpVa|Zq|x6KI}qvT=U105{FT-Qi6@>1dm*wi
z7caH6_KI}IYH0xaL`A8V#-I{wBK@$)p4cOiDYpEaoG&UBNn8|Z?)Uz@DiN6?pkGuf
zZYl9F7m(N&$!OSfkr{SrK%*{_95yU6`G&ynyByZ{uNU&FK;07R2w*01`u+{sAkw{Z
zO9OCOBtv1tA)ggkHu(r_#pLqcn!sIA=|~dWB2@r;kmr%u_dM8Po=4)D=k0!4J`kBf
zokI%yf3xVsvcQU{bQg)u$OYUJ$t5qu2viMB#H)GdiDZX1ALm;e&jnstLLFJXBD+N@
z@%Wcy=07N!d@S%pR5nTCxu%iT_fp_kROZeOYif!tcTeCj5`bqSHE`)4s)Hg^dM5BZ
z5}hN86Ooi)HIXT`j;bb+C5{BzedSnP>Jnh)snan5O(~|4-vUKSJl5ObNm3}?(?Y|P
zFJ}G=gEwKX3{JuHO?WBPVKswOu;agp^d_vwmZ~Whr#l93!q!Fl+4rwB0MA?wtJu^V
zg|!&G32PUbHo%ATCTmVjq-J1q2CJ|=gR`(<8_1im36bhJ(*Q73*eBL*Loo~MG+2cl
zo9}PpZageqnESVUFojF~AHcDFg=^{2w)JS19<^CFX0g26;en>^p-tb`g~k;H=&(pP
z*tZ&l)S>8HWp$|mfX-BAhszL<5{6tfn`U8sqPHvG)Y)RFXXsyTki^Wl^%b~66o#F`
zIhz$XU&_r>{(<ORlI53uEf;ZL%vaRkRqOg>^1|eENf=Oeb9k${VLW+cd{`@D)mFu8
zkHj83Z2MbszDVKKFE-&2HY3spu-hAeEtkV~LJoN8^0`5+;v&`ZQmpT91FymQ4c1`;
zBC8Ov;Bwe%$N`%!hdnZQ4fa@cR-fd67kClg`gg1$SewB*tV3iC0ft=;n+Z8!!R4^K
z2CqH;MeRP9twLCz!8+`c$SMTPyBu~W<bZoFhaDKa)~;psvPkRI`qG6@b~Q+Bh;&SZ
z{ei)2d!K1({WFm~)~RXpQzF4bv8SRI9ce$-XwxdWDw2a?8wMv~cMXoWYf<YIx%xfD
z@~+LUItv+VSZPEap>6$gkce}u0;tEsDl~{UpMLf?tzo9%@fimUMCs*VirxIv)mH4p
zAJ#r!)3Sx^=B^BRBx<R=`(mj9dTgfEkF@Et-|H+5W0!XwkVkj@m8N~0ZOXS`og(S{
z?pGS1F3YHQXg_ARmOt-`-E#<gWN;Mr!lkfQ-z;B<wdkzp^?`cr09YRud*JY;qG?{C
zq<}fo0BniW&NDGWOs2!SJzQYhB5flNmM;HY?PnrsKNjo%d)(11SKeJ)y72J^(bOlh
zdfBn}Eqrdmo`<|$8#tS|8tEt&Jylj0WLp=!FLoeG^|C{=IVZ`W!p;}<Td`4JsGM7$
zZ)t6;X{}_pR!yv<ZMMYMVLKvqVr}V2fGt}pTUzAVmQ&TSFGqcB&R0ZIzAJX$VeH0|
zvN`mK1ZTvS9d3$kJA5QYj7uRx-8|Hy^_f-NY>J>uaT$_-(VW<x6R|GCebb&`r@m!p
z*$LQ!on_@bz)P3IJk+OP{UUuK7Upq2#oAj_tV=pCM%W9&JjkbDemb3i-4~fR0DmHq
zHtaCufWL4#tfIJg?+J9-T$q6QyqSVA15`_gm`{W$7?VL#7&k^%2ho4gLVgNXg#7)b
zfimPL;v}k~DU7Fx=AX5Qo`4OBtU|!7%V8egQ!qc3PH-yyOOdLBaiXz;aS)Z9K))i=
z0T4E8a3W$}3UN4<0#Q%MOA32x5k3X;bIwE@Mx_u(Q57TLpNk}ogQ%o&43#t;LMKw#
zPjMDy5tjlpz+-(1M!ZX!!hVX?ooJUdf?iD!`+k&~h!}tW=w~nR2(_~$cU-E9n=TJZ
zi$uS*vhaIhF=v4`Yk^}?v1+k0#hU3i8B=L!vk{u&@W|?;CRlFV{h6buSVr8tQyk{q
zkC|_>PENgFCwD*P2W=)Io6Z$=Rq?R01n@m@6gH%pX>z7$kDYa-1h{Btoe>x(22%q3
zV>>>Kz=|MSS>oW#?T;zZ#}*BeB^XY|#S&rkxd7h-KYeAH#O!5}w)8Ers+|KT=fr#k
znPl1Uc{|Buy=0Sh5>`ys?WMF;O{V!dnFeu^`N<6+jfnY-n@snClWAxt(|ns`zWFFm
zrb#x*B=b?8Omk?GIphOAnI_I;nmCh89G@bS_|*4+NhX7b{bcwu9ZN#;{o*kM_Rnq8
z>ORgG9NQR-b35V-{dl&}ui8TY%BI(N9Axyqkg@R<dpujQx0lk2J)W)D+e>N19#6~h
zcv^$Uvo&}p8`kkOtmA1|#~D^%Ysa&-c6*7n_D@B!5XQ+u;k&++R@?Ek+K#8OA7|`e
zis+hHasR))lmcNq1;RLi@IhN*$6>u9YbGtd<7q`0CqNEtWgSn8>^O&suiGhN9LAx-
z>L75ATn;Oq0c<a&<##--x#OHT21Qmht-9lBsU2s1?G$Bic_XY=Kh@IuJ0d+LfU(-B
zqI*lM4lE3oAV`ZRlJ}OPWbkzr+3*@*MGaed4O>fD4O=H_XkO_TG-eEy+TC7?EzJ_K
zlUZWFaH#H*f4YHZajWIT1hho#QkG!m;U7yp5?~ryBDNw+M8ER8g^>O8a(ski+A9C3
zHR|}bNd`3aK2UjgW9i#1?{4Z3(~-q5mod|LdY8+#lxEu5&uYzly9L~-z0CfZveMvg
zQLEQ22`LUgc`c-SPRK}edywnJBAd%%TIMq5CujUz7U!c}#zBdbP*@9|7bR;+u~g@!
zV$IHF5vR?bWm>bP<(jd!N1HLPbDfyrxr`v>=#<MyGrgm(nCiJs><^*C8bH{lK9XYF
z$V)}|=CasGqNdnQa-9h7Tt=`H=TR<VKG%s=B6OGvOx9c{CU3KkBaTnovLfE&08<=P
zc9#h6;^47ct`KNthmhSR4k5)o+U^p*UQ{nMId_*f1=?huCF0m<i7=AN!nEe4C8V$M
zriTR+{eG;Zo|ueaCLz-W9QP1vcx{OtjQK)F%oA|T4{+>TVCKWHA{z`ZR=c%whaw|F
z9UOZUID!})0Su171;-f$96<<<Qwo?c+Yy1`+{~&skCp(%6X><22t2eR=)eRUizk=>
z!uR0ttbOV|60h+$1jo7s$76X%hO95Kad(RJx&T%L&H9^yX5E6OHMU{y{ntg>)?n-q
zRx8`YviEg;i4C_n>#i@+C$>^kn<+YFiPIu0?^KF1P`o6%P|=!u<J&E~`r(Eo(vNi;
z!n>MC#~T+*>*M<KTBf-viF_XU+|SZH>^aWToSJH)_(BPI)zWHz^4l$74$G0xbDOFt
z>c1^KpQYo)N#sXQ>09b4(&*{g%Fi?&7ro?7EIs6LHgb5owkD0k9T~kL5`3l`Y=68o
z61#(>(K6+TZGWs&zFgOS>=Tt|&`nb|OnfiS@t3<r!jx%^!C-iHwq@%@%xw2Q^jRNx
zJfYJQjDDa3_eX8xarcOryGXxf8E2VbcvSFvINMT5^2#_{B^x2)?{-yi&yB~8Dn<W!
z76{e>>ykK!Q1JJ%44e#^=J07AEpF6t{)Z~xsQgghk8~8D#z(|h=yNY|R`~&ayZnc~
zQ7Kh8udoJ7g=Lu75+uA>fdv=ESbzmNo8Vi)c+PmDL0pZSrNNfO+AA2(9R;~BAUXwS
z#qg`(wixTKAh(AsyMl{ith$2i^DMf8xRsR^sTdv=<o3{CGR?5GvaCuPP6}7P{)qZC
zr-pWvZsrdNe-U$aQQ^-c6TQ;wma7>B#PDO0#PRf*AA%yT8HTqj@9I%+SL^Mrax0W3
z-e0p9D>rz*;%_Q$JkX<t$M)3WMjDeFj0um8Rcu3J;=^;JUyf%>)Ux|%3BcYc6$a(L
z!virNpBu-5YztaC7^(?_H+uATV#D50+~8$}57mt{R5vy>R4;7QZtQAn@F&Eh4>f9>
zG}Kx=6sE_FAWw!RW&}HJ*lxs*iL2N!eKc?MYY1yLnm5=@Iz-kJK$nf@4Oq9q85kRm
zs^&@Ys>4mOdj>~g9O0x81E_zWZr7Vuz&C8IcWrBZpxb-db9d>5z#}cpmWb6_Pq~-p
z_0-%}Y^`CI*)Gr}Qsyj~;BJvz4(kz_9-jta3@yR)e%5kJ@Z_b~yYIef@4jn$H`}Zg
zIc>kSo3S@6`aT1ie_JsemNtr%pO9-crK1h!ky16M&9hU=zo#bpO*K*L$(kb_+#7kn
zzfIb_sNWXp)z8LP8X#^y^_~URr=3vWM~7V!ovSRgHUI;jXm0>owLVA*_M;+G>Js3s
z+qufOS{s0$7fFfj)E^twU@RvZ$L%G6KYy*=(OR-9Qa$aB2LcZx(W}M1-xl~=H8FpY
zD<!~flh<I2A~OQ;yPjxoYzz1+UReaVFH$$zG5pa~4aO2Ci*}X(tY0#k9mDtLTI|hw
zw7VlI%a|0pw1jnw%w)iXNOIVW%Uc_O+n#7|05(NZf^CI-Ti~H5S{s0W8aYP-ES2Wb
zKD{IM*UsubU{IvGU{#TIAMk6QXm6|t_zP)uAFw7;_xHtk<7}n_4oqI-)w92ERttbm
zTbFCFUXir`__Qb58xsOEmQV|T+ak5FDYj*D)dXO%x8l4}Y_~1=9axv>T;(^latL&L
zqP+pQCejaL!S0w`;{#Y1>HY7HefWw5uOzK%zypy=!S+n9s?%w*#=CHT0WP}$1NIuH
z1{)SxJ%C^JM0;ad;EpBKL%^y?J$xkg*yO4Sz<Y8l{z{-tTbB)5uK>pkO90r|G-waR
z9-3UmTlH?VO{C)O4M4X@O2cB+kgp1?MPgH6#}f){fj^0yCjw6`A$wc3(ze;MyU^JH
z@ZQyojMw?{6)*CKO#Ykgjheu1Pqa1wUyqzs0k&f6$&P@p=V}G8FOtQue<HFWeJ0>9
zbEU+o${)wpvd6JI+2hz6k7K!&(^Py=-t4MUw)8`hAUnIi2dic8!M2y?w71WT%!A7U
z>z-(B0RAv?9tdz^vp&Rav#O1|X2Gh?1T~S>1XvYG4&&Hh-rE$|bvcZ4gvpNtjx9lt
zb%x+G5Y||~07nf=061`{TG*FOu2ptLVAT>T4tOMz5{!>fSQ`L7K_NM;U1V}VpUYvN
z3HiRjV@v#ctKIthQ|VgvRQkbEdMaJxkmGMKYL|4P84#&{tvCXMo@gx}8_0+a$v6R7
z&mIVHpmhfe_(Sd5p&;iY>BomV1p9O};>>H>>0x&*d)WP8>4_8$LkaLyqzMS)c#I!(
zrs9-r^#FLRD>-MaM-E|sE;3hfs=6eyK;s0(gD>f)bM-qMul+q_EuJDtA>U+g7h9Q*
zI;qL>X0-V<u%emnr`dWss@92VKdRO_pU#N*WI!3CTH_c9K3!(JQ@Ssxhaq<CiNq<K
zhBs`P(GwGZuPn1zv29ao1h!*v7Usw3D(taKG4q+jBQdvl7K>-i;#nAzNiWd24?1!w
zrgzwoPr?WteK3tk@jISb&dQ9wq^W1+=exaU{x_CHJ#*A&kN5;hSA&kQHmY>JSn>oP
z$Uv5hT$7glerq<}PMv5ccU^h|f0KFR=l`4Wc0nKP!+ru<5c@G+FkU4Ha=7<{`As5=
zu#z-hA_zuvI+PWGLZclr{6gjb+5eKh7eUKBql$F28EIw<kEbF{Nb^uC(q#((ZzBsy
zT6-YU`R~zE1LSYSM&gZ_XJEv0k*7euc8tKV&NIR`Phr`t$WtJHg*6hh+B3pnPnG7L
z=8(P<4zYAJst#K^bBLv*{>XoG3p&<?w*{kK!KhL&Y7;CgDnaI0$?&av)7~$>P*SsZ
z-QHET$Y*-k1H*;<&rEoS$aDbxBI#g<FP`=qa9Mto6t-pX1}6QYMb<d1DpDQymjE*^
zFD)blN-Hstw`j$ChLLZ#kRtffn}={nl3-8vc0#2{F%6PVI4nuRZ%I<xR9Y0FFYE7^
zmxwG&#8_A&Dz`+`Yl)~*T$OIAGdP{6gg6?Xa;J{#)<wvhO8ES+`=djZdn(eJ4#Ou}
zk*T3u#7(Uj=1I!n_$pART1W~o=A{(EM!~YZVi3B@YHp-zZZNQ3)&|!HvAne}$FHpH
zxoYX~M-s3ugLPPs!4cRMm%^$pg)NHoHG*M#&W~sH41xA|&>+ZC)haTTXwM8Ntf1+8
zszbB)|6FQ-cpalh@i53USRSd}Q_+B@Vmb6wG;;pJg><J1I_E#EMT3xQgI;**|5|E*
z7QD@WveW>ri1e*Z*s4h1|N2S;;6_$4YtYS7aZq8Tien_ChKkgjr=Bb|KzK-b|MyZO
z>wq+)1KBVY9eE}5TGhBp{j;S8$VX}>jZ`&_)C?n47s-CuoakI-<tq)qrpZS$N2<oK
zL*5S~;PV>4uZvU<Y(@0?*DYOb+0@2hUgBzAqWQa*USiQoT!ndwYk7(0FJkJ)pQJWt
zC91H`8@vj`$kVK%#H^`}!Mwz^yhLtQy;LdBUwD8n|FKn4g*_IX))s18rZxui61BWU
z-d0}i)m*8$)2Z!ixl;b^(+6q{o3v_RZMqOXvy3Y2&kc^jjzp(*ff7$$4dx}T<|UfD
zp!0>)4z0vhn3uSgmuT*fTSxmnV-{1es>sa&)jb0?S7v|~JR@~5Au8;)?5nU|kxuA$
z&H$qJtBq9q)x7qrjZ}O2)o|utt4jBa^h<ho&NNaHQmJkIR;OAYlAcC@CgvUH8eq)7
zZ&_7X%T)@@z`8`<f6$s|yt()o#Ve+D0~W={8mV}>+*8f2^xI5-DrqzwK+t%FQI&7)
zpDnBLR2YIs9!Tef>3vN;h{{?jq(TqASLo>|A4-Cu;ivHf={ysiuYB^W`pGdMRg*l^
zQ`TMNMp5TI>da@XLs#o!Uv{`G_S+6~^+Acq(s}ugn7g+;I_H|hHO*j=mO9wLxD|p;
zh<t=VZMQ4~_7Q_s*xbKm(!9dJsp2szzHAlGz@lRPE>l_Y3>CLq#bYq9xO_zul{!yV
zU#02?X8tUUTCn+QBN=)XLwl|2S=fYZb{&v6RNm4wH$*Dil*%vQysq`#NRrvt!fc(v
z9xe4xXiF98#{90>eUTp0J+g;%Bz7%t6!utTWm-S0&Wh~&jDU7gQL3fUt;C#2@wX_p
zndgzXYk4EEJ(1PeR#zn=s}ay4Dr>x_#7^WM2^{CSB-$ovZ*)-XvdDf*0#G%16;==V
zqQIKTM_}tFSC4lD_FN9z5BYO}SC-J%C;`Wjvo$4$iIT&Vcp#D~ut#|wi6@>1d!FZ!
zc<FhwH?^LLtPA@Bk3^*>NIbJ#84MuO<meP|*COD|uY=0IEK+T)jh6zI+vwk_i>(-(
zToqdvm2GS)aW@z2DzPt8JC_u+1g@%x__cN-0`qt!e2X-^zy#lc&l%XE!AaONgLT-z
zb!!cF_zrLu)?%}Gl6iaE;4Exjq;JuEr2*J;Iqa#yD(sm{VJ}3c4RGh#yll7r&BD4w
zQqgKF&~2Ta?JfIV{ul{e^REQbc^Y38X-A^*=MHJ4ViRa&N1=Y-!d+hlq`E$<c?5Pv
z^mb)6zSu_+@9Kx{zo#$u`B(V(Iv>cd=CAb?!Wo%0YZlg%-StP3;4MB306#K~>!}ad
z`#z`bS)}mZ6Wcd<{e{>|gOi=Vq9;QlB1LRabguH%_6A_t<*@aT0}fo?HLYP6>H7n)
z%c66Y#r6i^>n?|FoBZAVCBQS6!&+u2dL7m#I#>CU9>@!P+U2kblfS#S1i0(+o*S}K
z#M&V?B+^%q+Z%x2aXIXv$=`jl1bFIl*pY~D1j3&?US#rqT_kIEHR1kLgi5c1=@&%m
zACqgx;PrM5vxivu{RqbBh2}uN&4KBsW#CU2qh}j|MW0Qn@^;*^iwPI11$QZXl+Ube
zI?Zlqn72i`%h9*oKsz?@w;n56pNaJ71olEC9eslh<fC@$k=9-oWa+?IhP@t8r$`IM
zfEKnvTikBJW_+E4-Ek?5rBs7Z(NK0UoYoL%&j#w&zF3z$tomS#8&7w{STH5U?OP6E
z_YBU$b_`Bk(Lk^QN|!~@C;Sw{!eS_Ctcmfhury4!(lFf$&z|n+$bE0lAXG)nG`O#E
z6D(|>Hiu8ZY9cMJ`%3@@L!kpZ^0~$cTr$^BRK=b+g!zC>!aC(a6@$4WCt)q-y$KxY
z-kXHsLFpz(PA2b7;>5pj1sE%*Y};F6bNQlqbpl4jn;hWYo=n@$1deYrZ%@K-zFJIU
zFv%F;cS)1`Cz&h^fuw09CexZ+&Ykxg6y}sW+jbF7Dq5=M#P%KHRQII0&yN+81aglB
z=p=FKJ9XwW^A5YQD(h9paf)E-_$1Nhy`5YsyJ-DlbCoXpt9LQ$*JOmzoBFk*8O^LF
zkl=k5RKHz;`}#2oyQsk8ktG4vsvd&jZ6ZxN7$Jce{t*k0Q5fTlm|k&~0MomR8V!?+
zvsHoP(*ASGb$ZO#F{v)nv$kciKHDto!(zu4=5@9dkJmc!>QlT<WMZ3&VVXx;{gt4v
zru7sY^)TkNk26PJ&cjmsK24gQ*D>|bOuf#Y?lbjzHdFU(rm{L}?I)5BZBAZ~l~Gb6
z$>-$tG!d_-743SOh}Y?(Pr2*#(P!Cp*tW=41^_cnHRA%0u<L0OT~9OTIv(j4NjL9p
zU_vZ~SseE-RHp5-uG{JqhxJHv8fTtFI*!Gb)+6RNO%rBJ<g*7{$<nO;>sgxR{ZJJ8
zFN9xZ=|}Pf6D;ztsJB&7eD)Q*VQIG)jAJ4{^)mI*WzkcfF4IfSXkhq}NC&$6MQ8a?
zShtMs6G@y#Z6qy}BVnmMt!7f&{4O69>0qWKnT*Je#9`d&oN#2#VvZAnZeX7oSi~Bv
z-KL9$9rmIP&q5H>5yM%=6bLX@GsN)kDl}0}9lp-a&?Z+S?iFWw0H>YdJ!6(F0d=_h
z>Uu1eh$EK45zOG2-&VAA+{wY!k8;X2epZ=|Bgu)+g{Hl6nstUz)lVh$h%pxh(}p-r
zNcmbboi?rMv{Ox|?WsJiVN*JzZE6HLUlB_avW>k*&+TIb`TXU#{PUMBS}HIZ%`jb>
zuL^f70O#Z~b`wd%19|~zm%^;L--;aP>nAo0b_T5^kC%w7O|5E{;70$R46{T`iuf2I
z@z*W8EECWxijNV3`$XDRVErP~<K`Q8S^|eMO)L>Nv6di?h#?zcakd=GAeh)^ED?8}
z`PkbH&+A<-B_0_~AJLPCn&ajD(#@_+DQ;=+igakzhw?z|#X6qCIy8Ot0R&i=$UepZ
z==Ov@G9_?iH@P*~Uy4lWSfIs*=WDGEz>kYm6C>q&PYpKf<Me0=Fky>84YnY%dH{=-
z_>F}IVA&F%Z*ANc*o{QH_AB;UncXkuw{E%<0$euvD6A&Z9a3up@I_CwH&zAKEg@S0
z8zR-j%=0y+c1cH2zp2wlQUF7CG_AoVL}n|1yF4Y@8|wmoyQfM4J0ey3RE%3b{Rpc*
zA|`NT@~e8ZTipBcVJs!uMRFLdM`SGkxEZt-Y65d2Rk|s5*W`LolD6g=%fWyx2{oAC
zAgX@A6_>;6BC8+39i!F1CGgM^>H%O+q{g0!am#2*fVXTm=z~OE0)3WHi3tIpG)e&c
zgkIYa<Q$}5OmA%f{FG434(9tyOd~%s)Ut#5!O~O7S;DL^zz+?zsumI!Ta(ACEAPdk
zD;R68U<!Wy;|2wuFJmL=Nm04sxhBtmpV%YeDy-Ay#|(_;lK!AKuT%dcNovom#2Cy=
z)bkQ2-;AUZS1B=IZA`<Wjr3+j6JO6snErc3J1iy?yLZio2zFnD_<^{$KLzU+<x3BC
z#{y3cKWoL7TNlJPMLOM6+qS`}eX&QPvz6u6$Kp?14EwV}-0X;C;BQo@9;@_ZeNW7d
zDxa*MFCP4aBbvK38%A8vlculf|Er~Lop=C!NmYNwS{bQ}EgKwtCiWLD%?)fRHEz)d
zH>tc!&NcNPVWiM)RZPNq435I^nSMtZwqS4)M$7V32NmNSX~4XV$-M44?G2x|!)+Bd
zFM2(wlG0eN)Eq}i>1wW&LWgFP(zRSEdr3%WLAvSa(5BqM{zQ5}-)kNcag#)PR(L@a
zHz$vO?Of{<QKTp4&b7{nBE2rWDdL|{sW?|hm*|q}SQfcR|FfyL(t4?&A@Pud7Yf?R
z<lx<c9%u54KV50<7cGm{MNtnrn@U65nH+riuP41t;d`R?zg21N5=HqZpQ^OB_E%cl
zM4h6IUs7G7Ezvzu=q>(DwJo~)w<Y_<O6!%sS81IW9g3cbT0bqjMBAbVqRXGDw9blF
zM32B%D*9w*rFBqs&WL73v~{xn-oK-=q9M_+s4AkpiK4xzpL*|6?}>V_?}Z5as-lzj
zg<U7@2|ETZ%SO><(Shht^i=dr^jy^Y_baXYqDP{~aM^GudMWBJ`q-BBtM%{7x1tWw
z6VaW2ARmg3MV-G~X}v9)7e)Jw*<Gcf2L&w-r+n~=Xj61gbnzcnTKhy%p8Ufs4SqiA
zbpPK@dar~Z{HpvkD?f{BqC-*CvnISFdVE5T4)k2~O4Rx9=x6FhQI0l3XFzgjCd=Ox
z4%!!fBsvm37j^x+sh(Vh9IA=xqD4`(m+PIDKarK89CVPC&+~J6_ni7wP_KBjcSU%j
zpn4{!kFy0Wh(k}+&XH*N*PJK|Q4X3bXkL6-v|i9X@n{dc_wPA9oKN!B-_ZOK^?yly
z5`{iGD_I(R@i(0g#X}DaJr}(a^?q4(i6Z~DFf=b(7Tp&;5Jf&^Yf3{$nH>D0pkr~U
zbupC#ZxwX-TS?yjRkimut$kltUq!<!s#`QK+7um#y1yaci`GP?9jfDTmIm*BGv$MK
zzm=thpWR7m@WH>I()BfsO+mBbbD|Ydw72^o%MS%T6h9C>5gmy-zn%1`bKyU5+7yR&
ze%tBcYNZwG`462A#G%&z$m!+pXgv{iz3Ws{-Ox@!v+IgA(SAXX{u9k3QOEB(JrIZb
zHk>xaq4xhY*$0NYMZKa~(Sj)Y`CJ%!C2IN4v?hv%MUhY0!-5`U@}1w4zeW2Z{javx
z7Ez~YrJ?m-v@O~b?Ta3Zjzv9NYF~6m6!kwU%D1X)yQt$tJ#Q-aSb8o0x!MpNiSGX+
zVbO%z$!&;s4o~R6N$-W~dL`;qUBjZ9XjViYjzrHzFGTd^O3|0QS%12+a&_Su(e0xA
zllLfhAe}?ek*HUC)QzvG`zWjbd6r*2C7&_M^}*0_L6!eP`;_R4s45EopfjN~G@Hr6
zds!OX`CmG9i$hxl9g9OPzn|(I6y6XWh>kM(mAmq-sP7MTZW4tZJ%6CI=-?k~zKKG<
z@n1<MdLnuzTK?}f&Z0Y_T~X)_Z_9pB>wU$NDCE16JrcG3*NQVy$ZNvTf@n?DzN5a0
z%6#FPXhF0g>iBOpS4EM3Bw6LZ(K$voR5LrOl0oyLHPLg?OHq{TQ5}~>N9rRK@&n1B
z7otwd7ey;s{$1f+(e{7m6y>_q*8%z~xlxh9SiCBzUH*m!{>Z5+4t4CN_Q6nJL6^iY
ziw6D&aZ$8~&V<s?TqXw}WNC2k|Cq{M7KVmJ^P&~e1JNVVGf~t(AsqSJr{q&-uHW*<
z>YHd=v?GdoE)}u|;)j`>vZSHsnSAblQh!8?qC28}(V-~nLv~-ZCn7K8)G?qmR4*tm
z2OjvJlRkJoOM_ef7pHb{s7Dm_gYRT%@OnW{GC6qQVJcS>hUN;I7he|L{$C{%Mg5cs
z-Jbs~$-&228hrbIcX}=!<-xBCy119*{Zd%d&DcZHv2LoM4c$1$H6$=x(4zPedZLTc
z=@$)(hBEzi>GYm)8W3Ml-fEUVEZMT?Ky^@8UI+g!J+5`>Y!x&py*cGYUAcXil{YWK
ze(Kbx_bTn8E)h1y#SLb=s6*5#;$N6w6!nVsL^bKwMYlz?6&HEo7wX2wTsQQdNbgYe
zRCFYIA>!X!Z-_QU_eHy+H<dq4_lfk6M9)PpM6X0~F>WpDZ@;Kha;QtxEn-aKIyrtj
z(%%zNFLicHH}@0c*CxMTl02^mS+{6ebS#Q%P?&$Vy{S5>yG`Y&GcN2KDCoBM9TB>;
zjc#1nl=tJ2^05)yuqCc1(mNDA6%jxDr}`MrP5Jz;=$?pi+ZUZIf11uq>BZHnHv2`F
zL_?x0q8ZU`5jMree}b)x7DUUUxbWYB=&9(LD6Urm(6NX)P!&yx;sQf;(Y9zuv@6Ol
znrA}uQbW%;D&3-sqF&K}Xi!uWO^A*zC~ib?QKnNw+*}e3iY|-l1u<V3w*}FnXj={K
z&{%QJh~E}<$lo)fZ4v%w9$gkyMF*m~jKp8Wd(_#Z`tFOKirQpTpQvASN7SibP#O~L
ziH<~%)n?n<>X&FpG%Q*Z#f3i9E$S1+#Ur}``RhQ`e!@oVJeF-OvZ+<nE+W>jm2uq>
zVPo_?w-p<A3VJLKg>O65KDMuk)<yK;xoA;+SP_K}9|=ca!rn)Py{FkVAbXYzpM^es
z+bH_R7@X$&)9Q-YrH_nB`2J*{=nH<0zAzSfU+BZhv7t|l%~m!(VXvC9SZxz0_Buqw
zU$>}7bXjyo#Qc3Jifch&MRZ5B7DDlh(wP^n%K!VKxRxb55Y;6kFRn$6_Y?W>rHDMr
zJQ7vauMN?*=z-`^)TO>{i0+Bv+En>15$nmeXh$@tPF)rai-;R&M&(yTah;~KA-%Y^
zgc%2DH<LdUz9U=1uF!ua*|DfX-=N~^6z&x<o={v*Wy>=W<9D3dWmx^w=P#|lp^r}n
zrH2pJvi_5gd5B`{SaW(r7e#S}PM+5rnFSA>yq<35QCD1{Lp|Lh^749Evsl;WMVq26
z(V^&>=!Gc1qOR{(dmE~JOLSLsPjp&)5$D7>eHaj37R5Cuuqav<-4Vsbntxlgp)qdL
zSagV1v+;bWJm&kX^3jRwl4QjGfMn#w)uT8i-Z*n?iQ+;|+(L7rdC`I>F7hWt^P*+Z
zifC07*J*jo5$45x(XNR7_K}EvAg=e)c_zJ=qI_MBa;N2W%U<ZBh<&<GG$dk=j_Wj?
zOUh?W9sK`_d;d5o%X<I+-XGv(m}sbbl5|xnRKyil-HbXYppg7nVKp*pc6MiWcVc#C
zn3-J`!{T(Xuu!Q(MM-@)MIK5jI#E$+Qc<FzQCX7Vi9D!uB10p?!u&p8*N^+Y_ZCjy
z$LF8VJRbM%{hI6db-jOI*L@F{#=nTmf8uGrE}!RE^Q1Ig@w8*j_p$P=p`5O@T=9>f
z_{`H#oNmYQz4&c5*Fvsw@ap&&U;DDYjQB*f*U6RT+60YAS1*J{7IAIil717fuT`V&
zBift|t<5CwO0HF0Dl7RsmNi=FE@M;CsK%#x?BtS;DR3PXj<s=+d&#NkT#s-a=8~TA
zW0=mp^k;!<1D9m6<kSTE)xqWaxP|+pTq*QSE0^?+|Lk@BK30D;*W2iW`r$ts<0dXY
z#)EE*8s8c&PsgIMW7VlK2GqAZF{b!f%CWJuyRm2tTe%j|_d=}y`{_$7eb~aKzWBNJ
zeNkI}?KHRXIaMFjmgY`#rnb~Za<0^-|0ut%A+A+i@sEb)FRD2vJ^K90r#xf1#`!PZ
z|Iz#xJt{5vQJQ4oMy{Q)MCI?~N`BwWcjMjF!vEw)^@%T5aINR^AJx~+wSp`8y=1hm
zX0G_he?N{drF%MJiQ=0r%(q{6pR}5rv8<u^rk%@wX7b%0u7!Np8T)?sY4F17<T``-
z<?<h2&jiX0aruw@fFa6@A6Lif89R!#K8d<s2j6h{&&Jm?t~W4eT&-OGBR^NNxVh2F
zPXGNLXk+S$^qs4N%YXLs{dn*MuD00sexJ2gM{LMltN5>LHJ2}clzV)-5bvh#akSkD
z&Gm8lkNjbMCz@Oy`(E;WAJ+k{gIxZz@HpT5el^ps`li0Dbr<}e(xpE6dXAjWLr)iQ
z0);-dHALU*yNz5vpYFG~>z>&6x<3@dx^KKNDyRE(6C$j8{UE(A{f@h@U-$YkaF2Db
zU;WmlAJF#S>%Q~i2<u+IGVIfJuU{nf*#A1Ie!fvZP^(M7W~)m-4(RiBwDH&h*J`eH
zTzUh{SgvL+y$HnT(>oG_D>z>_g9kpY=Jdua#?RIER_2h)zc*6vc+opbHgM^!2TeSa
z?%yq<mj@o?QX9#7^=6cDT;sV~xb!PKYDe!u(R*8b{WD$t$$I>YY1FT+u1vgt>X*tU
z`{VnOoykK~TzZGYQLaYnNO6tg(%TdC9*I>v|Gt__?@jP;bkOtmdey<W1@>usU*A6R
z?B~)0{(4wnbD+F>;(ZlYBTwv(=JNTqCVE!fW8LeSa$R}^+kdZnJ@Twe&m8;jb+6}p
zJ>J5-p3>DbuKT$BL$E$wd37$v<GtMLG|eHd<(w(e5tGAQN4SE8QN9TrZtCOG={g;9
z(g~+~xVCeR&PVxFw~iU<(&-T2j_!3D#pC1rm-r6sfh1&><J*S73P8`V4dl>gldG>G
zu!5rbTekiNDNjDDf9x>=oX`3vN0{~-0xNKut-7K%->qh;0<c${Qyq4Ku+`&NDqHwz
zFd8$2lt)0vJ`KUEVo3F$oWRm%(WfCeB?8<v1g9qOs}tBvTlif=a9R*kCCtvVFI`RQ
z@^GLH!_K}deQ{V?w!pJ5-Il<g0Bb%q({(tcck_P@STig9P5!TorT-Y*`4IBNrJoR!
z<*I)#-}{g7ArJU3{6Yf1f&p!c)qgU01@&v@)c%>V0jvCl2|V8~sjI&=k^bfcz9xYc
zyIb*X_?>aoL0_MXk$~FUlECus{732C30z3vrC^;m*-oK)R{Z_oFW3C|8iU)xpNZj5
zCCYy;fxigW*^|+*j_UhrBK_M5`~$GgP>2(h{~@r>Q1tO%crX8Tp2DXe0Q--|_gn&_
zbHk6)8)G(%@GBFzDS?yqpPNX(Fo9)D`;Y2>O9Ee$!1KVnnNQ3q*0a&rYw_~Q_S1>-
zJqcV);N<!alCC|!!!)A#)Ou@=Z@a^?^BM=E^<E1;JP_dxiTeK|f#pZ|kH(+u|F;t9
z-%sElC-5T)yf1<OCxQQzz(*7K1S_&l7uCO$6SxViy)O9<nxC^1>Ejc4QUbsEAK+^e
z>DMRlyArrJflCRzG=bljz^fAYBMB^<+<!D5cO~$DCh$KR-}Xd)+1>u5`uBo29AOWV
zFEzjabBy%WFGT5oIYxTnuTgqKLY}`Wf&U4-`$4ZSMg-?3(k}r&5=&P+=8>3uf6FoQ
z?@8p}8_O@B-G4OR8^If1T^EkG2fP<taN{2U?;2B=+VAj6@b**dQu`eK7<eY>D;@qk
zxb=*v{8z#LqxQZ7-ga?a$lniwYZuj}vhca)`_V-HeF^+~@bVdT@~2Gx7Zd4?)}%2_
zs=bpE_>2TTCxKhQYnRq>)YR6m_+j%7>`Acn*)`xpVCiMy>%hBzhz;lPJHS(a6yY3r
z3z*C%e+BG6>feXK6K<+Y4e_PM|G7l^H^HyprK8L$KQed-{Dv5QERp}Y1Xj#+%dR?(
zC)xVX1J8bl@wxe%0$%ZOU222F*UM0GAN5cCP}?2RN9h>pO+Sy)Ka@!S3V78oqWOFP
zJbGVUO8&gY`v-9CH&Oo-|MDN-{(ACzepGC14|uIBKMP#=ZCz@D>wgiv?g{A8;hVu@
z_ebsB1>OYiaOpn*AAOSg8K?Sl7~J-|x|9q!;U*OM=tFg>jjp}f;H_YMXOq4{ir#(H
zUyXN9U42MDA5WxjOyF-O@XiE&EP?-!z|VsxKo4RA(T7a())+o9Vb7hKz^_T**MYZT
zFKWJ3-#GBXSbY~I^0y`M=9o#Z`M8So#!&u@2<9d7-v~ZTdvYMuUUwqBKY@o5_<acs
zONJk{|Di<s$HBW-*SlG42<`-TemKI~t6LpQzYDx7mVP&QQ!IT8*niaCcT_$$Uk|8!
z3_qI4|3m`+A%Xu4-X1F-#9~cq@5BT?4czjR`jEfQ0vEntpW5f>RWU37QTa;}_)Q6X
zbpp>z;J1S(%xXyOqEhioE|FeN;P)i(EeU)_0)H}rznH+1Pg{Au!OMqlB+?&9;Gcur
zDh;U#uD?$u(p6uUbYI_#iS$tk|K-dCenSFZmcUaJ_-zTC2ajLcklNz<H;_nQnZW9A
z$57PYJ4jyx-sZ~xpG5x63H<E@R((g7NA>+Mk^ajB{#^nePGI9W&=-9~Z)c6N_a0xE
zz-qtc{ZaduC(`F7@QvW9VU^FmR7j*R1xH^0voEazPm1OLWGsI`|2D_4`uk1rkr@Bo
zpGf~1c>ISOQnMX@9RN2X&%8W-E|LFe0-v0am#2fLKH%lyh~N{6^fSS=m^?i@k$!#x
zw<Pcz6ZpymzBYlc15aQ)a#JLq-=0YCOyIr*E+_DNz{_L(zcrEm(F9%(9`$fz>MYm(
z7ZT};@%xX~>%IiunZQ3!;KvhK^tbKxR{u$!{VtLILISUhg{;*6$OOJWflo@{r2lzZ
zf<8`9<R41lvlDoH0$-BAZ%W|lV8z16vA`N{(jUK`^xtla{Ob((r!m~0sBdWkzdwO*
zOW<UCpC-MI_@s?jH3nY*KO1ZB>xuF|NZ^OTiyZ%*0=*sr9|-D=JU^B3-944{oxs^-
zh(`D<LX10pJ0c|+q5S8XkfV)nj%GdI0@gDMHJATd@Mh>2b~pLo2_Cz;&gehYR{`r8
z2A}^uV4am+=*r&$-b*}XyeZ!pd>s79XB$$odsV)j@0b6LGsQ0dCepQ+vD)FUfM<TN
zKDF85Z-Vt~-7bgk1Fs-{+2Zg+;PQVH&!xi}-!H&pF5uj=OaC2sA@W9M$0-<3&x3VV
zH|x@00#EpKL+TLpq5hr7!W>;+pPKH{PX%v3hrI)bo4`%C*Qc5tZU*mh@>A_k1h1M}
zZ~RNucLjLtYpuU5JQuw1vS>cv4jx(_<?jPeb@te3@>jrn@2^W8a_y}Ix8lEbI($2L
zXESknhwlU*_*m4xyTQ9U8&XZokJ|qRxP42#@yCSk1K(4s=W!sL{vde6d+Jkr9R3A3
z_;1c63)eRUk1O5DH;wms@S@oGUq#6J;AHF%*IqOD&>!kT`j`)H`Al7Ew@WX8ch}XW
zHe=VSKR1KNoW~h@m;Pa}kJpP{*Mm3S(vTYG`u8R9@*mcv);WAHxbGVcsSf0v>f0fF
z7B5F}_5B!p@cH_b2wdsE0Jr|MA*C}2!v6(cd49d|e}#8L2zoxW&DDR9^ieVX`x97u
zF-<Q0D0tTib*b47pFqf7XR-?pp9-FUybtzSdOZiM=QBLLo)6YDX_|Jme+l@=4;oUV
zTz}sT*4h4<4qpSF{y<$={swSUtbe`W2_x8Za`jcgf!n{(eBK5g&w5J#i9bFK)>-$m
z%l}1i-^KN*jz-&`uYvU}U7t(e4qkOK`&(|l9|li&DdN}v0`L6Ah}1q)|H$BX;87oF
z2>Is-c+rPgFIV3Pwlr$F`qUaXzSF_`WAbPmxcPDXTgR_c!5y~~U%-yle9Z>$8pEEd
ztFHr`ePV>MhefXo!K>ceVEk9*&x4<g)n5hgesg_lo2!30c*?1qop=3N1wL@J!T9GY
z|55PHE3H2wd?)x|M}4a7@_zw5bULqeaQ*onc-J`g%N^bgUPJ%(fz`h~;0d3t59#@F
zaLdew)KQoJAb8Y|>P>t|?Y#ir#<O&u-|7(b3-2P`@zX1XWAl9`c<hE~zRv@vLVo65
zx8SKU`e_5}SxNqx`Mr{xofk&ye=YbCp0V5L(iecYHu21n8-EXYYK;Hafe(c3jSM~u
zKJ?AH)DD;bJK%l9_ke~T9|Z4sx*@f}jptY3wiV=0+5Q{?uRuN>Qv1lKBjCm(*8kD`
z)N$S-`>&C_7z=J)*+6NXOKk|=0N&A5mr|Tt`6q!_vp*>Q(|TM1=A&oINv{j80<V9l
zKJ|#f4Z$3+p0!kkD!&L^-ibbT<LL!Y_#^U#(1p@#;JzO=Sa}Lw0Uknr+VPGIJ`8SM
zS)bbO>RSsw7^Bb6g7vIQr%S&Z+>SlbLIvXAZ-WcVBK`G4@XnaL)VaFtvHAZw>3XKj
z%bQ<=N2Pd{%GLi2_)w}LwZq}Rf%SZuAMZ%cvW$t%=V{=D{}tIAXMsomC|ZvT!Lxga
zH@W$F6L@({f6M`I3GnY+dIxw+j2^RK?I|}SXEmQUgCE&H!pI}7*9X9B=Qo7*$w$EZ
zAF%$S@_z=rYkOU4i<4*H0WaTEXZFXG{%i2)^CSKGEcnZ@`9BKY^vj4oQk>yg`(O2`
zg-(B*3SM_6@nc6%XM;!2w(&XDKOWq8O<ih?8{Z`GuGo6K2|Vgt=GUda6};`OcE4Kk
zdM<eEzhF<f^y|T+PmAo6cY+JpdsA62%|}0Ys0cl{`~%>|chraUcMEt|wl1~8rGFGW
zyA$l@=X2ocqw7O?_fzn`SbrY}A82n#9dPvVH26?2<8%7pS>=CSB>!FjZ(Pw3+8-yO
zILBR%{C4f132uK+H2;&pdyb$_U3yM<Z$oH5mcV^GIe%crJ0f@wc*2)Qq{_6f@!tYI
zG@56sUH?7`-T}RdewF@7u%4k_?$Tep1p0-a*Esy|r0ZP}p58YLkA{9+`hDQ(`x^}Z
zX?-72I{eq-(titXtTlx7Jp(q+MZ59*8NBai^qI?_`X~7D_J*)OuLd`NyFS(K(wo8i
z?ye8*k&D2i-dCT}Gc{`eGVrc-b)mgF4?HEtKW_(*Xa0Quv*6h={#y**Iievo)%9-(
zTwwoqlxzQA!4sb6**an5?H%AU_V#R-{t58xBk+U6p9gPYJxzZ4_YLqK;y-@Af28vJ
zBl-O>ctfl|zXq>I-}?HW0Q>VE;)g$i_rDme$Jwueo`_FRaqXY+2Fm}K_@|qnIiw#V
zp0?YizfJj1;W<l(yTNPmr#xN(-bH^XZs=t-c>P6@y!;3_7>MNUC&4;fw$9bJ9lQs5
zA$kzK{TiG)7k|{v??LeFM<adzXO+i(+T+SMo=JK5S>sXpC!p(lh<~ni>8~Vx3i8$G
zKLdQE5q<6WZ!&oA6zoH%KmQr5=hHX2^4EZyQjvdg9e60@?-9X`;PKcmp8h()dOo$u
zl^+0SuWtzLn-75h5R;c9$*8k$qh0<rq_@TBaRYejpQHA7gJ;5TnlI7wW8g)9kMz$|
z;MQ3A=fOvQ;`}-2QHM^)BM%g&lRi8NoO*ObY7Gmh`8x%?ll@I^uQY*=uBr>=V;gwO
z$<h4wfM<`1{G}>*0{iiz=TnIItpEqFvio7`@5jOWud5I3;|<`>7(H(WZ}@OsNdNbP
zw}kUOGI$ugHI{!bxa0DMke{ChuX`-guYUv|d@`b+zk*j`@6an_-_*Yr`Fv|bxPB*t
z$6#-cG5sGIoCZGn%SgVw7JN^vKNG<RvBy-Q=JOixp;-EL;He*izZ^Z^0B&E^km__e
z3m*St>`jM@;Qg`jy$`$+eWYjlG=H~&YkTnrX;1hru-;?g<<C~|ih1>^tjm8Nc=Wl9
z-_^exJnmk`<I;ZxKKNWTKfed-9S^Op{%65@SH}*g@4ibzJ7(3VHaPzIJL&7c3jgxG
z=;s6ib%jsb{W$gSY;fu}>}^-y>%g;jV86NkOj3UAtA#H83h;Or|1|Rn=0VrgI%glg
z3;YQD=H*onc>4K~zfb}1fF85X-+7<Pv!wbXd3Yyy>=kvX?QZ;cf%g>ZLwf%bxD36D
ze%1eb!Q*56^Z<BtxV|HTpMqPkr^mVc1sHjGe<U9tBYn~2x=@}x4IcON`qXGQ{%61)
zvGx87SkFLbU41Wsw=aq8fzfBP{tfVtD}NDqN;~lbhc5+hZn687>i;xwd#t~6!HuWa
zh5Yw+a8oQj13s|4F7$6J;Qbl9zoYv81ze!KpPvsYooCUHxc;sMubYJb;qa%y*?#1!
z>)#F7H&f7;<6ZjQq;Ct`9~t}rd^m<52Je1+gqaV~*B<Z${Iv<L{L|pZ-Y8!2Jh&-~
zKjhl0Z^nPTwLaA6CxAOosSEpiHh35GGt<>K8C;94$8>PV>mvGk8+hAp{5Jw-((j$%
zzLT*hTziAyb=Y&hzW0JxJdOYB_~){#AjTo~;{r=xA0&M}^2^WP9pIg7c?{Fl_c8F4
z7w~T#y>0;SJIS6G)Ovgsyy3Yhe)J4@`vbfOMf!~X9RY9RJjx@1ZSU{kEyNRs9Dc<)
z%*TzK?{MwC8r*j$>+9N^49@;1_PNuK*MPUV^CjZX8^PO`K<{<7{;cq+kv?1uZoN73
z&ud`4<70y3=l6l*@vB?G(+3;Oc@vHAGvFh4)`#=)d9coEH@W_Q8N3a8@ceg=$`hZO
z>e3$sAI4ww@sMAF7rw6{^dFueqt3&sK8@!$q<6lOc$gdiLGZ!9!@qTQd`H20KY*S!
z)BKJ+7kTliDBds{JZ4pWNdL{?Dfpwle;0uFZn5WAG`=gr(_{2D8{CNg6n{v6E&}U)
zJYHUOfe&L}t|wjXm%)1({{dm@yBU1sNA|pq@Ezc$uSD^KyTIl>Jud&3z?+D_`tsie
zxBnRb!j1Qr;Po+kvEe-Ik87b<C;v|dAL_+kthepI7Q8Vwp4Wr-EUZsWaOszVQ(vmr
zJMBz={~4@zN=ZPgzjMH|WAgSL;3ET(eOm-?!(MDAzvRJk@D%oI7P|5u03Tf(#V0=o
z-rY=m*^TG(;648y$>%Q%PqgQm)c&`@_YnUw^9z0eTsx0fFuL+T2Y1|5ANpI5gZ0dS
zr^o%^EnShkd=88Spk$+eUIihniOtVg@Tig4e{O!>06q{)zYP4y4V=%Ry!v+)cu#Ac
z+20ku7TkVGB!Aup=1i%R&-Fnscq;aurKb@=P351d3;nITz!xBI8J?m4uY)_TBEIO_
z`#$)<7aGF;{TO`Dw^$D+4}Jw6&-sGsF8|Zu+I__L+<2Y^j|=7bh~RJF0`U*jq*=ca
zuVegQt_$P0r-RpEFSNV*#)8|BH!Dp35y1uE{ojk)YXk3jA+j&70>|yUIp7KF?0Fo`
z*Y)7mm_M`<tan^xU3<5K$HnMx9eC5fAiv#sHmLmb4WYjM0(fR~eQKwpk8guF|2f(Z
z*a0pRe^LFS*N4Dc{tErL_8tYdo*2oy-+=oXB7gWGcuY0gfA|x)!2b9VSN=ut)EK>-
z@OtKdb+o_mYVeV8{znGqfTu623;ov?@Y*)${bWmDZvr2V)ps>`CgoG6|09A0;IV`C
zVZ8TU;7zgoU2lRPCq(xBQqnt_|EaFO?*;3fT)Q0p0C?PG*n@6<?*Jdgep>F*KLK7D
z_J2h1S@7nVeZL93^%YUP@N3|`oZsBy%6|*IAOCTi!#@D;doc1Beh!ZN*S`ku+G)?@
ziC+E;-g_d?n7Hzd_{;mC&o+lo1}`MOwA<m+!3P=t3P%rTf%T5G@eZF4);o+Q5SLc{
zSArK|Pb^Y-<oUJWHvD-{kJp1&K2;yax8DWUvoB*^dp+P4zZqfDMPCEp?aU8V8+v;m
z_z>|CFV8;!?r7xs6<2-@_(;rtcnG}r-y-|`rVEDa=f_Dud`A=?dluY$Y9!zP4qkhI
zB!5RBcphnDf5nY|6nOv4$o@GEtmnr@x&FKs+`)OmR!0w)fmgn_F16K_p9^k{(ZeFJ
zo>8lr^7X-T@V@&aeZC4DkB4k*hMr^m{c+OyNE{jY{6+BI7(IUj+!D)wA9y3@H9dXq
z0dIIPipL!Wulb9Mm$05Mf&=uamuLTUKJ<pZYvgOK{{--E-UWET;mP1Fr$zCuH-q)A
z&CYXd{toa$;>kYV*QNA}uvc99e(;`p;$04Z5Ulqydi(JXaP3LX*SPuo0(kvR$O|{$
zTfvW3khi4E{<s(1h(F@j=cnNE!%_VGH{d;^B75eK;4SPw_qq0ug7qv_lWXrJ=;^=)
zzg`W&8Q|^M_gVna?{A==Ht6dfSAHz%o6duN9li*B<PDMjeIvLGeXnroSE;_3eflxt
z;Cdcvrc1w`^o{VR$L|CmjIDP8+=hKT&gCBjuO~j;>E`FX;N|GAL!_&}w}8vPjpEIB
zf>*yXim!hjyz7@yeEa+0=G{^LN1M=p)w<BW-9`F=SiJ35;Etcwhw|kKu->=m*YEe>
zL$Ut<1-ve{pLG6(;7_ri?8cM6nEqUdes=gu(s`gZT>rUXJ)5@Ot=Em<-Pc9-R}S2c
zJ+;D>uPQ(K$?xag3_d(H+W)x)Tw8<uck{OftY`7oxbhppN8x9hGxPan@Hocf@piDD
z-8|~@v$qzs5+5o!ydONeRu`r}2Oe{O6#sq+toKzObmKX30`>v%g)OGN5y2_ovFu0s
z`56l?d?hM>K6ue<c%Bn^Dt>JPuR$J+cm16YZhndVE7zYiSns%;>DtSISH80@jQ^Ct
z*+~tdJiHlv;MvH(`7n6xE9%1i^-n6D{V=ts_WvE+I>tP^Yw*{=<=Fav4?KqW%R-m`
zG4Sr#d_D=z?u+)zp962Wts#uZzNGx<U;df;Pq>Kj5wG?7;#BaczWVUI#aM6<YySf9
z#*Ou%yq*Le!awx<)&_2m$<u4Vhv#5lx%rw4Uc~#XeLUlx;Jp)~^9y-!>ID29m;Zt*
zkO#9Oeg65e*axxx43K|WZ2Y{JI?y}){QTSs-jBVz8-c9({fO%Sc%<L|4|wzUBYAr_
zc<Ngt|8X05%e{4}v5r0-M&9iBY{Xx4v8&o*{^c*ouV+?AyZPM*?i|JW8dv^*z}o|U
z9l?$7u<*N)Coa8yBKj+)um2f5`qeyR>gNyK6q7$Ufb|UZYS-R7g^}0I4)=iDWAoJy
zj{D>91#b-X?Z{vaxD)%e-If0o_;s=Q{UUfb{5Qt&`!~U3!tx`6?|}ox+v&<b0G^Hg
z?)&#MaQmMkf9GW6mEINI>Be^^cn|w+p1&@ZJiC|k0i;VFUj}Zv6#eGfp8;O@81eiR
z>x({~3m%1j+~wNOg7w~GFJImbUU3HTPuJdZ@XUX22<h{KV7;%l;L3j#e3bdv;P9Q`
zjo-yyhMp8p*aTi4)A#p+8)NhRAh`2Mp2r_)`}cG3k-MYyejKcKmU{jEB=~4dza0Xn
zV)Y#bue%F>%F*-a7UaW*X#b-L+%%s4x$(UoydHaay6gWW@I5@Q;o}Y0g2!JP*`GIp
zH*h|Bqsw0ckNSI%YIgPA3~oCb+28L6>)Gw5b1Z*-3Vcs@v>)<$@a`azk6XcdFL$S_
z|GVIww?+E%7ht_RbDK;54S4n^B75@p;88JpJPgKI4)=pommp979LdvDz(->C;%mV>
znP14otX~Uw{MnorbK|=jyzs=xAGjW@=Y7d;?8gjv{okVVVP)_X&P%kL`bGvz!TWia
z^C7V0&3nOXi7$D1bi2y$iQ@5E_aW?ovde!b>AORI8X0T^Z;j#afLoqNUb_DN9^AAc
zvge-#>z$`#TzxNqJBVNJaJYUF`eiBOp}g$Blfb*Su-=ZJP6Lm*Ir9I`0w0de*Cg=T
z7(KobeBeKkrzhC)UJWjDexTsw*>zyOb5|3n`M41ru%ETa;a*`)t@-opOPMLq$9JOr
z#Uau=U&Zq}ZoIdG^-c%K-_-YSV03mUZ|@W?V~@D}o4}2W>q7tR>tMZyekbP`)Sr97
z<NgXixc(jh>wVyQPDts`ft!fWj&toD1uwiAd)VPolcBF4MEiATg4dkI^Q^A@3&88!
zqVol9;H{iT^YkzS+!3xX&(DBY#PB=7s}4u;pmpH#iBWui1Gt&}x;3spyTC`DiOzRD
z2HyN)#BWc7^)7bL-y<$V{}id;_4gUl*IXLK|6c&F#{Tj0vauEZp3HeomwybnEk+M#
z33DE<-Sy`pu-*kb%Hhkwhl%I;{ogCWYp;vqk#oV1td8P29pL8Jd@KU%ec$_BeHmfm
z_q$ww`oRJFp(~V*J{SbA_)v5n;NQR}(O;Gu`X3pr2T#Qw80E@;0X%ztw4d-*@FwK@
zSeL$CI3LM_hrlaNL_a`~qL-(@L+n4B_Q8k1ZJd|&^nMh)h5g7j^^f$CmqLHvkM_Gy
z0`EL6I{$e-xM^l|UT89SE%kM}@>9SQ3U#SA*T1)dkH*$xK6qseF9J8RA2QXI?*nhW
zhVvS({7vA)^Rc%bz6HDodh_(W20Z2KQT*vnaC|<#0It2QF0?1V4$j8fe-OO!NOV5o
z7vMrH{lCE}&ezpk|DFN2OpngL{0+Rnjr~6-uj--SeVjM(`A-FRz6<-*@$-4$`1#!n
z!DBud@yli4O>c<KdtC``i_zOW@I7Y}zi{($1Gp9c@KmZ5{d9p>zAM_l?^pg=(fQ08
z_~_gy9``Tcot$6x>wi0VD)c$kjrVTwX3je_x%$5aZXsUn<;6}gpHLtD8r&I+-={7o
zzDRt>&&O%t<qIPF<!rFt)iZ`lM1O}*!JZ(#kac)G>Ei~SeyDE@CV^M~CE8D#0^SkM
z&&XgVcvOgaUKYGAww?{d3tK-I#rra(uZgwa2c91D7nXqaj&9$do4|VK%WT)b4}dr9
z;ryvv|2x1b{HfJ0{Z8<r8)(m^e;%xNRr~RN1$+qmbDhh75Il5Nv|soF_%Qr6-KDQT
z5Bu?+$lq;b;Wj)F*{^fYVZG6hus`%LB6uz7?XRFcr#~(L?+oW>WH1>#=0?ur$sT0>
z-vZv2Lms&P&H`^Bp4#f#pAXh=nT&Vo?*wnGM)q|txDeJqB3J@GJTY4T_k)i<-jM3^
z^95eGJ(8Dqg4c6i-p}tB!P{c%w+-BpjqIbH!mo+W+dcs<pN)Uy>OTk`9V>qn+{}Ij
z!$HZ{2PeJ}dXA;P8r<<I>{nO*Y_Q%N?&p6ZxDo%@)5Dv<6WFhr>E>q!ICUTPi{tmX
z-~#)rUfy<q*T>q+frrjx{YTjOFN5`aC!Ri5fVX}W`Qhrn4IISg_fz04vHI=;PyICZ
zpzHsagvqY~iypoO9v?ezvK_p)G0Oiqc;TaUp+0;Oyy1+xkbhJ1e}5Y3kCVZBWAw&v
zC<W`VcfGzH58eX59d`Yn48A9JKJCrm<@=)e)_m{~`-{yke<yh5pQ8QECEx<|w92Kw
zAFSU}8RhV8;MPajA93UVnDP^^)_h7neg;f1HRQLu!F{p${7-O84Bw~x_eA@#zXXr_
zD*bWtcRzS7=L!9Ik0?LSH*~uG1jw7I&qvSCoCqEplP_n2<M#Zy%Ku;#-+eQ9(*^b6
zdRzzIdIJ8W8($xI3hO!Ejjsxx&iS`JuKg3=0=>ESE9pGSa?(c~gnt~p-2%>z#vgR~
zKLXxQJh{)|jo>lR7sEC4_f>EU_O0ki^5P!w#xJ5TTz`HE-hzMAV)C=U4L<xq+H?8;
z2G+a(+ui&%VqcfP#{Q+lqrgp@WAPqvGxO!!e?55A0MF~V{Fi~3?~3?sD!6cNw7)kO
zoF(3~#<hO~ctX$+?ytNHJevKraW1_Nyr1WP)PId{3AiwTKko2KaO<zIcijAa7(8D7
zic9|(SikYH!r{+=r;g`5lf#?9D`Ncm9dJ2DZ$AWYet_}2@jVRQ5#z6?z)i98e+0Mh
zt`E-(q)!)r@xC_K-VxH*{VIAMtNzWje`a*P<TP;GRp=Yn-Z|h@j6N>{>vxj8{J8?W
z^DmLVUQl_?$NKqO4xSJj&q}a<pU20GR)c4=U)JIJw*mYJ`emx0AMgt7<so70<*$PE
z?mi!%x)(e%HvS#pR`zQ=|Lp-Ue=%C$C%|jbH@<&=1doZGR|wz_KBMg)-hTu3`r*`|
zK6ouyzeCkX2GK(ccsb7#`Svac_x&+CZ<Pn{-yHdOi>SG|QkOdD%HK@-jt@rk^da!R
z*myn)p1}V5CYS$Cu-<t%%Ha**v9bC6B6v(ww12Zz>72JW^GAR012?jN|A;HU3;fF^
z@DuATfBO+|?I`<aZvB4??uf1bVemrsm(6;y9xs8je_(&!<$u*bvmVbx`}<SDt-o#v
z<^4?X*x2~yf$xdoh2Ycz{BI{ea^U9O(Rkhqo;ojzAAcA;^G(=OuKji3&G$jy2qek(
zcR~MppIxgP?_Da-`KW~se;r(VcXWPcJ9zau(RqxA!P}sh=`R1H;60qL+2-(G@LKtc
z4nL{%!RUFfGm!t;*!ujD^uBt|f4cs@0M_q(O>ubSROn$!<nN6E?}y(dU!||df%Th(
z>%gMF3&C5SiuQA^03Rhj?#DY5eDIb?f8I*GW#+Qzyyx|#chqA~yZL?>c=P={pYTdM
ze|hlXzeMN7hrkPC^l%$E{(R5Jz@00i`T7s=&gGoH4{U$G20r++5vf(Qr}eo9JSDdN
z_k(Nc$UoZ+UKN|a-+<SHnJ!cQ8Sv`I>cV(@>Pqa9&qe2-Ukx6LohLjGtao*0sX+60
z0r={ezcd*<IySyHgC}!-<s{SIh+r0Yi2af>SmhUjx4)kFQk}&E;DxdNeh|F!iH6WW
zT@OCO`HI~x|L4KW@h4}y`o0OCy^!ZK+<I&WH{q{$y7XUxTZ_aG>uh^ZgPUXX_dIxP
zig!x7^v0`@r?K>t!27XJR=N7l25+1f&DUh`;i2d}^;^J4UlBbYG7ntic|q~N)^8Db
z3;gNr_ZnEgW#i@3d%*{Y$L?_L-3rb=VEIM#e7n+DNBp)CJf<tM=f47;5}VI^!3Td&
z{QDJ*ANlhmu-;kO=<5F&cscRisSZB|?u(888Su_6k-hpR7-bLoYJ<!FH_|sEJvKW$
zY8v((=aIKKd^))O?~!~w2fT>>dH!qx&u)*-Z@m#bJ?0Nh18@CS<bS^dy#0FkkpYOF
zdca4C@2qg`RlzmlWh)*2SMUVr&(q6C!TLQRpZ+Ou`)K6BxwgKI;MVSFKDUBf^7xOA
zKAytA?!=y)>FWO;>3hQY9vSQcZ~i{-6D7aaYcF_RZ2#sd@Ya*~Rc2TIFJK<#51-E*
zHJ$k;eo%1fuLF;UpPIm`Z!&lx=l|MW`fTvNBhmBL3zU9p6i@5}2QmJ95&KcU7q#4#
zA0mBS%wO0E);oPiyYvr&hhqABJ$O9y!SD<{e;K^~L-<>6ezuwXk-h&TVbaIB`W^x|
z^ZZPU!;gYz9**MEzg7M_8d7^twCnLZ@J8Z0yIlT1gZt3eiyW?-f&bsZ`=DI=LH3G^
z`|`C(ErXLUu9kXgOEZ<6zDSodwU>R7?y8nAzPQx&?u%z$Is4*jrTgOUO08vLDaaIR
z=}b>8S4r!xKa($-ukw{8>Ap-cTgX)=cH3`?)mmksyOu8%)48GUT-n|gYn5f>=q_<n
zDsb1etd^^$E4l7melVAvcxl_EEkR!{lcl0d+gjgvjP%Qba;AH6u9nVbY8e%{G$`h3
zOG}l->493lkgw%)RVuFLiq(>OQ!Sa?)m&xJ^saxPmK#zJiaFE0YEY}@(*4WQ)n(OM
zuAdSE*>Z2L$W3=`Svi;HrZ-pX?#rmQe1CbMk_&H4CxY@o%`{o76im6no^mB$to4vB
zovwCS5OftX#l_W$mrj~=S#VRXQlgvOUmh&2=4u0F@@8wL4F8r4lq$LYpr@xWQ0)Wv
z<crxJrKi(9<#d7JsMdTjUz=FYRB97jY{Ed%B=u(s{8v|d2A5XyHTAV;X{NB4{~8AW
zNY4~<%)lU^KeIU3HK4Bc=lZ+*R8Ti%EfY8Wr9sue9lg{|nYH47x#iM{tu2#UHFn_&
zb@Q*<RatB%y_U_Fz;x7%K3(yB4QHWcax@Dqt-(^;3DafO&|N68WZd+aJKfOKQnl4n
ztz~LTVvf_fN~Nfl^3_bOwoKpJ;pwKD%bDKvchyQuyXgb{gtqMeo_s+BSTNHZK&{>V
zn&hQWda1w5-08-YD&)I*ySpbTd%kPZMcMpde<=&fWV6|x$=vXby~!=f_9$O(&i*gB
z|NR36o1r?;Wp4(Gr3$5$xhFrA?WyK<S14s_)qGa#VeSWt4vF7-3YltOI-AqF8LWwL
z_sqYY3(J0HHe8aK2X`-)b+=k8ZsE3aI#<k^a=GH5p)kG|HRZGBU)7{p%JRvjYPuUb
zCF8sW=~)otoP0IBpPyYeJ72B&q>gD<#o>&>T(K7aq9apXJPYBW{0qAKa@o1Lr2!2v
z-d@|l)!Zo;6)ThARqCK}L7QaKjX2xnpQF1pnXjz1SMnt#F0py4K68!Q>{qpXzlNa+
zMFgY`V_C>dBbs`HEF99C9)Q_`+>l#_pugIi?a!nuL;kKd6qJhHefhFoCsmlMWYU?z
zOaURNRx0VL=vOTzzD*-RlLe~km1L6@OicGcu{QD2$&)XE*ljm2ZM|f2qL_M_?lHtU
ztbOx+G`3jJY|6{pH(ytVUfwa2P&;0N7|f0_*@TxyZe9?vxk|n}y<{MhMM~rupHT{t
z4hhLU-<{JsKvB7hnY|^-UoI62>7G(0Z7OC$(&b92x00(`ay5CF`#gF=#c9Q6%v5>@
z`k_FRO`WtW=@!N<tIZ036|<R27M`niSMudr$+kZ%6C?rq<c^ogO`vN<qqLea{SPXS
zGX8@GqQ0dw)n&!*bghypR(sr3xvs`C9XC(ZB0|1LDo+&qzfZw2%N(b}n(H`+Fyr}R
zHEq;y#xn*aO1o(<^u;Ugt4Qv-FCtR&Sv-j$3o{i-bN*V+3%WB@D<%x`J(+H?R=$kg
zVE!{k^k{cbv`VKM<a_(e>F$0>%C2fw76f<Qi>m|u>1qzuS)=2|+K}3>L6@leUYQ|I
zyw(<{yHQI@Et8^ui)%(PbDOF5r%hehQ`u56r!Ou+&X&q8=5NqbDrAGMN>=8Ks#x5W
zwd~${Y0Kq7cX>dIQX8mBG?l95Ql-`{4agvRi+R&%v0Urc@aZKtwLF5dl3D7;p???v
zQhvIn6eds_{ZY&?JNnA1a&sf~R7DeO&}yT*Ojq1ZX+U3f6|(7)G4H5`WE5P*WnjAf
zExom0s=M4_W4Z2Vg}Vl-*k6TQ&a4?<#Fsy7mJXq6%^~HFNI@dHIDjB9OK*gOzA6-0
z6ncsYq1H^9Qo0-d)r2~Ty%j=lMkq-JSFDMAKBP^=RlZsYWs$2YU*el=9>d7DRVwF-
z2w~HZY~#U9*pQN3IV_NzQKvbZGc+323E5TF<P?gLdWE&fpcTA~C#@e1ZYIe|UP#_h
ztV#|PZA!YQlJjaV{LZR$*PVg*0(efM3bC!|Y7#V3oFq*}0W_)zF#`?HTQIFQv|wp^
z!P{naOq-c*pXL)aZSxkO{O3w*&b#{R1v5JA7gEZ@zF1IO++M5ruOLp5iI$2b%x80H
z*e9Fo9~gq!`g72olHlj=#jG(MM9f<@uLi||exqt3#>MG=Y!Y&69-PeR=`Pkp`FU&Y
zWvi%x0nD6y+0?I;a=*&t%Z^g>Wmw02QK4Z?A+)Q%mQ#$ZP%<Jz%#ts|3`$P-cjMaV
zHa|_8TOQ413|-6>OTHNI)m&ax6?2)&RoLLIZ$!7lLsmMNhF~p2FVb$^vPuVgs-hcB
z0JpA>8lWGUxfca18@YsK99nv*m1JhJ?)hGkA)T=kA^X=D|GF{8KR3lNt!A7x<POGh
zAzhdV7i4feB4hsYm@(fL42GmUXzhRN3ZaOH@LJ>+NC2fn?CZItEvn~|HtKPXR3&|h
z8;PsHt|;AknTzS%P%~_&`;MW)lA5wwT0*B(D>E`oNm&msZTudXwfB;ipjJv(s}eA>
zU}Q&{#-zqH&;1#MM6su&`ije_D?nz*H%V9c%GOiM7x8<GD4KF;y+9zvOu;xJ<z?s#
z!?1zm0RFM}m=Q~b%rZ;RSZw_nnM9J7a6+z_>B5Gt)XEq_`4Yb0vLJ12f69yA4U1r|
znwtBAL3(TaEXrERZpAo`7&=m8=~@Oi1y%Xycz-fooX-pwr|0DQXJPgS9oME|a%SPW
zfn0^IdF@8$@VHs!?w;OsrMEwy7w^Nq3vxBvwwHb760%zJh;qdfHd=%ULt&d+qrMD5
zrSs)X)_k`Vua%tXwDGqB{2~b4ct=&FFg9VSr-#a{BDeAYivTllpjecumZB=7HsI(|
zPZvgBoL(ZECZwGH{xqx3-^h*%7rorKOcRbTiv203W1PmtX~!&_Gf=4IgIo<$3iH6o
zaYtyz?=qH$=7rHuL&(>1GfSn#;nb;WrcY#2=^hlr<I$pzmmu?(4CEw<oLE!{1Hv<U
z6B0o3bp@XHsDD<mHbWvPNIU-)lF;hqGX*t`_@!4>Q@e{T$aa9(@LTCW-^o9xQ2UIl
zFK@a06463WzL&0~bAwnt=pWO2l|oJ#Q^$={3<bC6yDAwI1FB>oDPvnue@}+`tAQ5Y
zy6rSU<R&ZgO|ACy<74&~80uh;QL3VJ)Fq5$+CaS-H;@T7c4WTCP38hDBr}zmvgI`1
z`T#Oh##}m|R_l;Du^KYZ2FyiHiz?uMDLdmiFhGT<@J6IMYKon-&wTrWa*oyqZA=0x
z>M~Ri*T7Uc-w|0aBQ^t(SYQc>7Ql!i100DWp@`nJ0!)@jdmv#5wG<38q<j(f$Hz6&
z-w5(*L_>Csp<sxorl3*3A!nwroU2q3OV*lmqx3->(Gb**I5FgqH?wmUPF2y$hU|b;
zXIi}zD^?k#)Jy<L<uXNhjryJRNnd5xSHtQm$vqP3nb8>uY8~TaaFN(N$wkm6p8vF(
zb*v;rMf7SclO0T7($dlbHw>8;tRJj_klgQWPBj_xlIeyVW+<e$Msy|UM-dvjc8fdQ
zlCf($Zvo^|sdXU95o{PNMzFzLhK<rz{4uN5zJXe{v=oUh(dA-j=>jR(euF&~R>G@&
zNt(dWo^dy@MoOAn6EQ`$+X<YvpdCRyGvC{%xCZ@XL16&r5HZ_>c)qe@C~2gi6%^BR
z1w-2Khr({5ZqRzz*r{W~VyTwzp<?E%g!zZ;bR+dm7V-s|g-Zg*#LO!z9T!J4h9D<d
z^)k+l0)dDK^JOcgvK$^CoRD6op>!3pF~YEiskJJN5gF|xk)*2VW|bx-(=tolO!!6g
zYu{ZW@>nD+Aa+w?k|(Wy-es77-U7vgByF$B)pT3cbXwgA=jVd5=(88|tz1R)xL`BG
zRNgDQ6`TfKceNZ0-MFvREY8tj#Cg`oNcWa8{xl!(h>aeiAM=o%4DmkdC#E)(9q2Dx
z&W3*mbEfrSGwT5cOK(neV8$8ukD~~O2xFk?Ooeg=L2YM6I)qluv|6zcQV4y+r*ZL$
zguzeKCPL;0>gi2#u0yedS(q=AOn00G6^{q7=9u%@wDGWDhIH4mbl=i+S6-GhEMrMq
zlh<Q2(V8Z@qpJ{7s*$MuT}FV39*E5vOGh3Lw=khmpi)iqa|%J5nH-#y?(Q>2f;IM?
z>48Zxy<lx3@3|Sf7Awk+47#2(YnGt}2{+?ESA*&E=3F^zZhG3x8Pl#6$8=Rn8JtZ7
zsOWV@cb{DnRU*2SoFl4j1s$r`Y!}!uJ6B*%W@t`rz-Tv!p-}D4AS#^v)CiI3F1#BM
z7nT%L-VBPSn}9NO6ZW@b=xvJKn>C2Jml8Zis=;|n#9$ElVo@7A2c%8!m^VK?WA5~H
zI=*<!G6q3x376*4mSzoQ&6tIZ=O-l@&q|uhT3t(Tl9bMfh}Yqxb;i!`V!sCUp%6lP
zX$CnVn-)WtxB;?6bwxWw-I)PnM`KxI3}w?@gzb!G(bPaTiVexZ&sNwks#xQkwIF)3
zc))Isz#7$3#&flyqqzh&5Dj7z2_YwWWKV<?iRso&<j~nQY2=Q`&~S+a3zKWi7rv7z
zC1IB@&!_unNEofuLxz`2KFgPxVs{QBitulh;^Opa1F{3KldRW{m+B(yR&&Od%4oBA
z1WpQ6oCmwe<djJ!i=y>1J4>-z+1ryA9AImrnxAaCLVtTC9z|zv!^BL#<`!~x9)zXx
zDy-;iqT&8f7<P3+iG>n_SfS+Ph4B|?+<80lbOw8@WWXtsSiry;M1x3er2Ay@+K`*H
zoSh5x3CUm-zuYMnKg+(I@qem8zqOt*Ez4LA`Esk`T>VTVb77{3n3Y%7E<WM64Nce}
z=*OI0B0}jR(4d}LbFx;#FF;R1l(GbeNn=wl^3`o-ETJn9u{CP-U#=H+fe6vesuO?4
z%dx}r(P)#L)M!RO$L$J@OOmQ$d?Kd9PVW36#h|b`9F12?`D&IphjY#_W7FyUq%Qte
z-439UsJLsAz~VMdtpwWAid|~O5f^tsFEVjZ&elA}C})F6^o20Y4j5B4TAEO!iYf8u
ztkLR}Znc2M3x%1<5INU~7w4*F1`BexJ)dFL1l=a|5fKZkq(HU}VHtj72d==kkN}2V
z4gXTbbN!yh+1kdS!GE1Q(BCD0N7Kq6H12pH(R?v%c`Y4#i{iR=oKmVbTTRy+i`*2E
zElOa|`oGgk=$Nj2uj!9w)!4yacFWd@7Dh$P-WGPA5uJWjB$%w$))*FmLTXfFS_I^v
zohK7$ldUXn5zR@W$fxdrZ;VYS4+pmKYbb>bffQx-b1hLX5~|gDsKX)&_!0RMF)=G{
zW#wrWmr1=70z^jk_lt{B`ScYL#fIjvir<Eix7Frl58@FkgbZ(4TT*<QPIpbp!jgo*
ztXD5ycRpTZw>WVUxe_ta$nfpn%(1)*<R02Si`+8-5F;a<(SQk@>o+nz&I=N>&VBc8
z=`dbV_qsFqq`id_?rqwh12EFZ2;wvzC}eANit4r8%wO%sv($_i?IKO0R6@$b0?95W
zqu`H;uW41S7h)FGla^g^+=pR;#CQhQ?~X|yH+7Erqy;n^{UVMc^cu)MCGOsn#`hH+
zakfC)>yA~th_EqMiEC}8%+Hmp^PnUz*dcur#X{5=ffL)Y_M0JAJj6pmRTBz|&pq10
zm?*NAh?-(IGgUT@=Y<^EC6C>%X}FhZS<-6FW0@_(x4OiTv{f##3XpQE2?TVZR{}O%
z6eDo1_`6{kYp)aDu+oo?xw9A2Vk~qO);61C5Vu)T7L-80jln_KlCO@Q(0#H2E0DDb
zK*U6B7#EUm!5WcPO53=E5j?XbTUC9gkg2fu1Ph5qh)ri8H;u>oA(n2;7i_c`@gkE&
zB@rADwBNlHED@#S<O`BE%}$uMG%fL%nJ{BvAS7U5L5DDla}$i5ZD;w-jg3~>u}7zW
z43>SSJsAUD#=_w`*_ayK8+A`3sN{zFYqdTWs!w6a#T?U+G>c-T#(wJ_M1^5^OhRWl
zd1tn-!YF0XF|EDhhV+~Tv*ippBG>3VX&cU<C{ac&XQfoaNH)`|3S|JA3gs`FvqKCU
z)6YoYpjeK)95+Bq!ZG<|tZW&%k&&HF_vKrRqhvM}(y)^Py{0EpXGUmvW|woUP?$*1
zo)2N2oEeEyu)9FaP!>y^pqcT=acwzNBJY%gB4+xn%j$S{7O@_85&<H#Lgs4J<!l+0
zp<KMum_#Bj>_sUKOACEch?+nxud#)!^fvp4PAW3zHZm(aVpcIb#7r4|Y__u`TZ|CF
zTPs2alnfLJ)43I>5GN?R#L%#dTbOu=JS1z{n004T(292UafWodCYavdHo2{}ZJISJ
zCC>1b&0I2CI-<2SJ_L+mc8p}O^oVM3?fo2=OG__Ru#@RNh9z$#xKxTvX%oUT6+#>~
z0N^$}0yhr?2IXK$2&y}I!s}>DD|VdYWOy?fDT|R0<*a%;7MmC@wc6Pb&-HU>&zp8_
zdhU#l^!ynM=3PI3+6)_fa>PXQicm3XGc9z>dT;E&l=4>OC&jBHoEXEzRHRv@#Y8}$
z$U)2JY}6fNH-=*tNE^`-!mw7VE@gVB$xEF*Ye5HYs+CcUm31j2c9HTXH*1{NfuNpz
zrCLK)8^U|pnHeV?kJ)uuX>2nUZmQ-@C?lE4+F&MAH5BdLO9t4+HPM4U6NZ?R>z@X9
z8Jchom+2%sHB6f|+X$W;Iqi<R$tBbJ3^OhvHrQO7LShGU$bhr)jMj98olk;^cn`9W
zRMs{{?7$pAlr3-LjcLxKbq`>+XV?if>dUX>FuM*@4W3c>nn^Vdf!S`8v&AxW%la~r
zL;4{KwU)Y}#SZ6OI9pbm4!#`<IVZ{Z1ziYV*oWg}vI5m<sT6t1%%6fN&Rx3Bm|E=L
zvUlc3txm|<CNwYaOEL@>7>T56l73M*b@*FIX<Tl_;;pHzfO@s$lqZu^?aTML-XJQy
zEBP`N^bdK<>j)q6k%y$d$w{^YX0ycFeU@I?jN#~46e%>BidDam`D&MmE3sELcgEW~
zu3T^}vl+%n{JJ=Ll6@aDA27GsJ(k+ncC6`!y65M>7%Fs1&aw3c2!_p^vtW)FmyXjp
z9Y+wNjOgvpnx!!gxAhEMK*X~AV2}B4+*V>K;i^M-71-Gjfgxoh1|?pt2c5+Pv^qqJ
zLM)%<NQ<_76m$(8RH`Hwc4Zc?3UMq7)C8DCMbQ#W!gw&g8!3jSq*5Z!Gw!(>Axu-2
zU+lRZxXO*nsXAE@9JJA~C_8<cIvC$<29>&N&VvjUp}H=@FK3Xj#x^iJPj)*bU!H`M
zXI3FPw8DrK;j|l|GFDJ3=9G{P`fCu11L6b0adSC^B%VRm6D+OtBTu@C6c^=4nKd$V
z$4TUJLA+!*i-H=qIzB8io_2bNYE7>>7y>ubf9pnvMy|0VRMX2?;rJS7_-3cu^72$6
zmKDQdT8Su;KGO&K`<DfCr_Z?R`fDH>!!1Uv8$t214O*QPc6L=1O0bmfsL?K>^Y-&M
z87aX8P|$7u{-g1PhUT#y#Hu}a&D2qmv_rUusMTQ`K;aV2<xoE{Dr0ytE_=||tjaI}
zZ}h4{E@cSW1}`HK#fUg1rL7ri=q6}jY`|()rc4Mj#$uU4X+(3h+e|bf!kqP?H@Jg-
z(*}+-hl$1DhE*r2km&&CRXWqF12P&wNYR=pZ&r$ipd}SHWT-R~HaC8{n|moKGsdJa
zHXN%X<J#B6+mUux4aO#vSfNs#xuQo-S(p;i7<{GOp_gk>sFcx~u$kL94+9}~d&MqM
zI0EP{ogF9_5O^lMZ2W6$XA&+(E3pHcU3Lu{$o3fkgs={~vt7-}eG@h^Ub>p~Mv0jO
zb9^8)Zq0mI`^?HiGh5c66pI_tW4(IR2_yE)>1=RjQn6+j#49$(d#3SfDHa)0>m0n+
zhPRtE1%7HJP7Ip3kJ4S?7`w_G3rXDg7(O)Ik0^P!XhM7TX22}Ej$&P3oRcYwtm&ND
zpJHo~&SL?n2?pq+>rQv4JK7iM;2_y?D=Tc;xve%yc<Q&R#jL0gKwHi?(b+;C#-T(M
za8g`|u%ZoeR3!1W;e#YZ2Brtl6`Vh`HWjhJ`81c-BN1---3*w?){^=Is>aVUq-U4J
zO<_d?cTq`C`wN!N*FhG#o~d@{^PGjy3IAZhg4xFX&Q-MGL=Q~Z-#NIfIDz^smJa&e
ztdt%&a7q+jy~#4l|0Y<&RkEi1aKVZ)G~}bIhe?!VoSoI}B^)8EINW45G|3?tPVF;P
zY16cM)<a{+^;>-e>9bS9@|Mk$BxzzDc*Evgg7L<dRB;Q5&KtuNf>FE`JJUWfVMc6D
zmQkgNiC$g7vgFi(l<DHGv;@0(2E+#kb>@u;cDoK5m7jg_?J(_S_*CTR+-b|b5Sy_F
zJTDOL=!XQH-w^I@Nn#J1FEbZ5Ud6b4gv0DDV758xg7&1ZLJ_SnCQ%hm2AR;U>`BJy
zm!7!B97_=*3`wPHpdPudWnO)&cuyh65hqS^u&;;zUhd84Sq?U$I0TFJLZybD%*4$z
zyUadVD;AU{z%XWLX5-GeM8<~lJ<vI1oL#m^IH+j1un{y^7Z{uzilGgiC}3Aj7LxW9
zYo*>^D8$jQr2wWw_DpzC3nt(Iyxo$pyk~_#nsWy7r^`K32<B)?bty-C%rja>70QmN
z^7xgG<CxgHbY>ailAtjiw=FV<isp-CC}9H%M#L~>W}V`6A&oSQE>MdY7k)2YS)((r
z;$6N#tfpD4$@m-nhDIalkUX%D(H=h&Zw{Ne7VH$54pE^w6G{E}j2wYMbhDz?Bu=*z
z7n*HOe3<jxdh*Q9hdC8t%@&L`nX$x@+`$>EHlSR84ht%l(lN%Evw^A9ZGD+<VG+0(
zUobu<7}&bjajBP(DZ`^^R!VysV$QEG8cOtsx6JmN*4)QQythaY(z)7|UV9|a$$j<P
z-4?rD@CyZCf*)c|%xiO++D?x>qlkf^L9v%w%xWjmxV)FJ{)#D47!i(TPHBXB{P>@V
z1Bn1kbUn7AVd8ODLz=S@IvCv5z6Iv6-#mNP&yL#Co!R3UX8+jetg%-rWwW2;&OITo
zII81Sf)#u^hp+u)<H%}BoqZy`X^tVYzfiCT6<xf`(tuNs444XuDp;W`4i2>Ooet@a
zGsZocd_lTUCW54?Q6(Ie)1Hz@oS39h!~GJ>=HZ~>^3IZ%-LF#qq^X90#BK2VS?L9}
zirKEJmP{bZ8@pys#Q|a|j2~pNY+l0?k|!o|?ZaBb!h3M{EXrwvVg}<Kz747KDXhQI
zDSrJeWlJ3?rYCPmduMiZGFJLBHHE)L52b#$Rb*mJQh6Go6p7p*DH3})%o!(shfA4~
zJ1fqerO73jrie}M{Fy}}3OJuZI%gP~(#ar^jB2@xOoua#IFRK+0BUTQ0<y9~vsY#N
zlT(unm56e$T13VvwlmE}WsI4j^6bX*K%a3hHTNdM><=T#+jHk(l+|ldJiJnO9${mw
zc)7^v7!yX89F^gSF;%H%dRTk6nIKZs-VQp)#!rfLQM(9{d+uh09!NnEL2x=kMy4%e
zN!wfI-NuYi*xANEB`fWcVp1;4=Xiicoz`L?ez0}T(PZrcLMm`k|1$J#pQM1DHKS+r
zB$(IRB0xd`m{(c${Cn6F>D7*hktj8tt#)Rfu@3BRfu5Q%j*^a7Fi9+){Ab7zX$}d|
zHt|}cYW(h{Q<G+|*KKnfgTY!+s2x0<xG0X9ogzX-_l@P5I0j{#7Ps5Q5lz&HGtld7
zzNg2sw^@1{6fk_(?IPvch*FeU3~5vn95E*|G`q;~VF1}Fw0(^~&t#%7MQsd8Mzj7l
zHXh$`GaGJJZ;H?{7wzhVr*5<kJ_Z`OoZ{~I;2~$HhZ4$XxIycQRh+7$-(}*Bnp;AV
z7z!LSHS&cx1)jlmwhe;Nej6P}pYIV?v)K+)PAFHW1&u-Lsn5klLzl}K{@TQ`K2wE_
z6Jw+xrQJieqB;0u*rCyvne5@PjukLqc15J3Fu5r*0?`Ufof%MCit}QQizP*f;|fMn
z%q?X=92quRaWKzzCU&azcXS3;hp^p#xev2Q`MFS1#DCXdgKDiMIpsqwv7sc!?>eUp
zc0b4}qN;nw8$x1Vf<_g_V=m&0Yg7%(tIfw*?N?5pK0n<tPa6vDHclpM7AniQ{w`Q*
zHm21L<Ig(BUB*0|$B8zL(Hv=umL<Eam~m&BIh<=OP0>ntHqnen->~GyFEq@oD(N!b
zpxJshM&<$r*jM8@huEeaPj^}2DwZ=NODaSwX&`lL^Aa+1?39^5G+(h9hR-uFl9C*Q
zt#Eu-1Pic=UZ>c2s(|r@u}phDN_tICm=2kpKKqm?2Nki)O*d%GJc|Ku(lHnJ_YrXP
zk@iRYBBOCzQQ0~j<(}p+<CRV0Mn`{a?7UjUWaujyQfM_>0fq}KnOqHN$fs3U5sIU%
z9^43YXqU>ZHg&SuwWCchGcVD(U3c)<99ec=a5!?2!L+N|8Jbz2V{1-5Y+xUuN5J?e
z%Q36nQCC0xMv|I?z9M&bs!6P`Ei2E+_OW?vY2Ql|@syUZM!cLP_EEf#WP=vYYV%VE
zuehgq;4ixmOI#jXgGi(ef!J+!!wc$wIpi$cR=ecGBhc!!JD_ev0PL^xeQa36DK37E
z%n?n8LZ@0{$C}ujd*Z}BiDBiTF^Zk78}2;|YZA=Ka&ZQeh+WKVx_w6HEX-SQgHHbQ
zOo6&J>=cceWE;jZ#*CRUFQPRe_82QhgEkQCv_WEKtBxHSWw&Zr?B$>SQ3#fa_n{qy
zbwq7Om>Z_KgoBjQLnaO>Ye(|UNDSCdb=vS|#_hM+`Qn)!Z{<i+vRwg1dwDa!QE*w+
zR~ac$EWroZIpRjds=8)$j0xKt@70V!J@l<}f1PzsgNfB;{c`Xo!tnNgpTDya&55CA
ztOgTt>uSNoO3B!W6Dv#Ye@^oR6GIP_0^XSOhuS6%vkh&b=%9m?yUt-uWSWLO88cCy
zu&j=W_N4<E&SUrD+dF7BUVKs)A@o6?V))vn^xzfed;&xBw~&j!6$w-cti&tyP05_X
z?$v>q0zE7b1QVA)Cd^l!Rj~&i{XrMzQb*q*>^{w_?oABV-HR<W&%Dot!@BA%_Xrbz
z3x(MG{}*jmOJ!^+bBsG}{Gf?gpq#eUwq5DnI<3qZA6}>P|Mzny8TI-f-gv9en1J8n
zXg0U@kH6=QN@2ccUKz_3G}T8L8{MsbVZzs^pZ?(@Hse!y{hrIGSF|ags?aN{xq`wx
zm&iY#k2f}&d{i@9KNZOp6!d;)_tC43^qJ13*H9^+ULndAjDC$;upeLFETF#CrB{JA
z>$gW@A75et-}!va%**le^~CZ8L37jb@+}*dZ|ZULt&ZnwJ$}AVyL@`}l0Irzuc7iE
z-}k%t!jDO5?c^I8>vP#T6Z$$=Jm1cPjlo$@`q_=rzL&`N)K5<fE<Y_I1YgHb68T>H
z^clgN2U#8W@%et8$XEC(6nU%9716-~m(P#4aK+f*sqaVmRG+Rtx&J<8{)=OS5$C_W
ze}7NpTlo63gHB(F|DGyNrBdHlC2u3&wsWG4qB(t(Cu#+npLuq$;`$&sgYOrRsQNUU
zytz#@8h#G(8@(s;+AII@ZSiKZVfp_0#M!~cu?Bp;W^Vkw>iE}#XM0{YRr<7viF~(`
zFWwKIZ*n5vYV!FsRp{^En8<hAaq`Vc<hz}Ges1ISy*-idqsPgYOXU0baq=xm<ogu)
zcnewhA=!LxPUPEooP4Vi`M!Lde0nvjuUidlBcGG4rahnb*+jnYlJ8jS@gIqN-y@%|
zLlye_FD3GQ|2X-+m&o@6@*QhE9!li9|2X-6mB{zw<K%lXk?$wuJJxzUo5=U8<K#P<
z$oJpJ$(Mp>$QpkBK)w+niqc+_$oCxiq#OOm*D=sts&W##JWv<>{lSO-+V|$EO`VUY
WdZV{39qaD@s?ZXt`Tykwc>f<qI}=s_

literal 0
HcmV?d00001

diff --git a/FPGA_nios/hit_pat/hit_pat.map b/FPGA_nios/hit_pat/hit_pat.map
new file mode 100644
index 0000000..7734509
--- /dev/null
+++ b/FPGA_nios/hit_pat/hit_pat.map
@@ -0,0 +1,5024 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+                              obj/default/src/network_utilities.o (_ctype_)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+                              obj/default/src/network_utilities.o (getchar)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o) (_impure_ptr)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+                              obj/default/src/control.o (printf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+                              obj/default/src/network_utilities.o (putchar)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+                              obj/default/src/control.o (puts)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o) (strlen)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o) (___vfprintf_internal_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__swsetup_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (_dtoa_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (_fflush_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o) (__sinit)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o) (_free_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o) (__sfvwrite_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o) (_fwalk)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o) (_getc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (_localeconv_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o) (__smakebuf_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o) (_malloc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (memchr)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (memcpy)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o) (memmove)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o) (memset)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (_Balloc)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o) (_putc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o) (_realloc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o) (__srget_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o) (_sbrk_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o) (__sread)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__sprint_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o) (__swbuf_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o) (_write_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o) (_close_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o) (_calloc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o) (_fclose_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o) (_fputwc_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o) (_fstat_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o) (errno)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o) (_isatty_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o) (__locale_mb_cur_max)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o) (_lseek_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o) (__ascii_mbtowc)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o) (_read_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o) (__srefill_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o) (strcmp)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o) (_wcrtomb_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o) (__ascii_wctomb)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__udivdi3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__umoddi3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__divsi3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__adddf3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__divdf3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__eqdf2)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__gedf2)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__ledf2)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__muldf3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__subdf3)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__unorddf2)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__fixdfsi)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__floatsidf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o) (__floatunsidf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o) (__clz_tab)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o) (__clzsi2)
+../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+                              obj/default/src/network_utilities.o (alt_flash_open_dev)
+../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o) (fstat)
+../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o) (isatty)
+../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o) (lseek)
+../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+                              d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o (alt_main)
+../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o) (sbrk)
+../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (alt_envsem)
+../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (alt_heapsem)
+../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o) (OSRunning)
+../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(os_core.o) (OS_FlagInit)
+../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(os_core.o) (OS_MemInit)
+../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+                              obj/default/src/socket_server.o (OSMutexCreate)
+../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(os_core.o) (OS_QInit)
+../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (OSSemCreate)
+../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+                              obj/default/src/main.o (OSTaskCreateExt)
+../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+                              obj/default/src/control.o (OSTimeDly)
+../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (alt_irq_init)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                              obj/default/src/tse_my_system.o (marvell_cfg_rgmii)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_read_fd)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_init)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_read)
+../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_write)
+../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_qspi_controller_lock)
+../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o) (alt_msgdma_start_prefetcher_with_std_desc_list)
+../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_onchip_flash_read)
+../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (number_of_tse_mac)
+../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+                              obj/default/src/socket_server.o (close)
+../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_iniche_dev_list)
+../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o) (read)
+../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o) (write)
+../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                              obj/default/src/control.o (find_oldest_arp)
+../hit_pat_bsp\libucosii_bsp.a(iface.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(et_arp.o) (reg_type)
+../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (rcvdq)
+../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                              obj/default/src/control.o (nets)
+../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipstart.o) (igmp_all_hosts_group)
+../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+                              obj/default/src/socket_server.o (bsd_accept)
+../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o) (cksum)
+../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (ns_printf)
+../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                              obj/default/src/main.o (iniche_net_ready)
+../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipnet.o) (tk_yield)
+../hit_pat_bsp\libucosii_bsp.a(ping.o)
+                              obj/default/src/control.o (icmpEcho)
+../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipnet.o) (bigfreeq)
+../hit_pat_bsp\libucosii_bsp.a(q.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipnet.o) (getq)
+../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(cksum.o) (asm_cksum)
+../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(et_arp.o) (dtrap)
+../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (cticks)
+../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (rcvdq_sem_ptr)
+../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(iface.o) (soq)
+../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (rawip_usrreq)
+../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+                              obj/default/src/socket_server.o (t_socket)
+../hit_pat_bsp\libucosii_bsp.a(socket.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(sockcall.o) (socreate)
+../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(sockcall.o) (soqremque)
+../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o) (t_select)
+../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (tcp_input)
+../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o) (tcp_output)
+../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (tcpstat)
+../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o) (tcp_keepidle)
+../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (tcp_usrreq)
+../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipstart.o) (tcpinit)
+../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (udp_usrreq)
+../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o) (alt_busy_sleep)
+../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o) (alt_close)
+../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o) (alt_dcache_flush)
+../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_dev_list)
+../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (alt_dev_llist_insert)
+../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (_do_ctors)
+../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (_do_dtors)
+../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o) (alt_errno)
+../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o) (alt_find_dev)
+../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o) (alt_ic_isr_register)
+../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o) (alt_iic_isr_register)
+../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (alt_io_redirect)
+../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o) (alt_irq_entry)
+../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o) (alt_irq)
+../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o) (alt_irq_active)
+../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o) (open)
+../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o) (alt_printf)
+../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o) (alt_putchar)
+../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o) (alt_read)
+../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_close.o) (alt_release_fd)
+../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (alt_remap_cached)
+../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o) (_alt_tick_rate)
+../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(targnios.o) (alt_uncached_free)
+../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o) (alt_uncached_malloc)
+../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o) (usleep)
+../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o) (alt_write)
+../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o) (altera_nios2_gen2_irq_init)
+../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(os_core.o) (OSIntCtxSw)
+../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(os_task.o) (OSTaskStkInit)
+../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(netmain.o) (netmain_init)
+../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(netmain.o) (inet_timer)
+../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(netmain.o) (create_apptasks)
+../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(brdutils.o) (fcntl)
+../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ping.o) (icmp_mib)
+../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o) (ip_mib)
+../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipnet.o) (ip_rcv)
+../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipstart.o) (in_addmulti)
+../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(targnios.o) (port_prep)
+../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(rawsock.o) (ipraw_eps)
+../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ip.o) (cachedRoute)
+../hit_pat_bsp\libucosii_bsp.a(udp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o) (udpdemux)
+../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o) (igmpv1_input)
+../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o) (igmpv2_input)
+../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(socket.o) (ip_setmoptions)
+../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(allports.o) (u_mctest_init)
+../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(allports.o) (init_memdev)
+../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o) (inet_addr)
+../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (tcp_cksum)
+../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o) (firstudp)
+../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o) (in_pcballoc)
+../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(memdev.o) (vfsystems)
+../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(allports.o) (prep_vfs)
+../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o) (alt_exception)
+../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o) (alt_fcntl)
+../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_open.o) (alt_find_file)
+../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_open.o) (alt_get_fd)
+../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o) (alt_instruction_exception_entry)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (atexit)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(parseip.o) (atoi)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_main.o) (exit)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o) (memalign)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o) (_memalign_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o) (malloc)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o) (memcmp)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(in_utils.o) (sprintf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o) (strchr)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o) (strcpy)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o) (strncmp)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o) (_strtol_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o) (___svfprintf_internal_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(in_utils.o) (vprintf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+                              ../hit_pat_bsp\libucosii_bsp.a(in_utils.o) (vsprintf)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o) (__register_exitproc)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o) (__call_exitprocs)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o) (__ssprint_r)
+c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o) (_vfprintf_r)
+../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+                              c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o) (_exit)
+
+Allocating common symbols
+Common symbol       size              file
+
+soq                 0x14              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+to_sslistenertask   0x1               obj/default/src/socket_server.o
+alt_irq             0x100             ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+tcp_optionbuf       0x4               ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+last_flash_sector_offset
+                    0x4               obj/default/src/network_utilities.o
+rt_mib              0x4               ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+InitialTaskStk      0xe000            obj/default/src/main.o
+so_evtmap_create    0x4               ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+eth_tse_if          0xe0              ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+OSLockNesting       0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+tcb                 0x2c              ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+OSRunning           0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+tcpstat             0xe0              ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+OSIdleCtr           0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+udp_mib             0x10              ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+to_netmain          0x1               ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+OSPrioHighRdy       0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+errno               0x4               c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+lilfreeq            0x14              ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+icmp_mib            0x68              ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+mastermode          0x1               obj/default/src/utils.o
+pmac_groups         0x10              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+resid_semaphore     0x40              ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+alt_heapsem         0x4               ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+OSFlagTbl           0x370             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+mbstat              0x8               ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+netq_intmask        0x4               ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+select_wait         0x2               ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+tse_iniche_dev_driver_data
+                    0x30              ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+tcpmib              0x3c              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+OSPrioCur           0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+tse                 0x290             ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+delays              0x4               obj/default/src/utils.o
+mheap_sem_ptr       0x4               ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+netlist             0x14              ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+mbufq               0x14              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+OSTCBList           0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+alt_fd_list_lock    0x4               ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+OSMemTbl            0xc30             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSCtxSwCtr          0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+igmpstats           0x64              ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+old_mode            0x4               ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+vfs_dir_stale       0x4               ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+pphy_profiles       0x20              ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+cticks_factor       0x4               ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+memestats           0x10              ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+intimers            0x64              ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+OSTCBFreeList       0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+global_TCPwakeup_setIndx
+                    0x4               ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+rcvdq               0x14              ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+global_tcb_ext      0xfc              ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+netstatic           0x300             ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+tcp_maxidle         0x4               ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+nets                0x10              ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+pktlog              0xf0              ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+OSTaskCtr           0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSMemFreeList       0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+vfs_open_files      0x4               ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+cticks              0x4               ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+to_nettick          0x1               ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+last_flash_sector   0x4               obj/default/src/network_utilities.o
+OSQTbl              0x1e0             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSTCBHighRdy        0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSQFreeList         0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSRdyGrp            0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ip_mib              0x50              ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+OS_TPS              0x4               ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+OSRdyTbl            0x3               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+igmp_all_hosts_group
+                    0x4               ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+eth_prt_buf         0x12              ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+app_semaphore       0x18              ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+rcvdq_sem_ptr       0x4               ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+OSEventFreeList     0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+mfreeq              0x14              ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+global_TCPwakeup_set
+                    0xf0              ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+bigfreeq            0x14              ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+so_evtmap_delete    0x4               ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+tcp_saveti          0x28              ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+OSIntNesting        0x1               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+so_evtmap           0x1               ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+OSTCBCur            0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+arp_table           0x100             ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+tcp_iss             0x4               ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+vfs_total_rw_space  0x4               ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+OSTime              0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSTaskIdleStk       0x800             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+OSEventTbl          0xb40             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+vfs_total_dyna_files
+                    0x4               ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+OSTCBTbl            0x288             ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+to_controltask      0x1               obj/default/src/control.o
+ipreturn            0x12              ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+OSFlagFreeList      0x4               ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+dropline            0x4               ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+OSTCBPrioTbl        0x54              ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+igmp_all_rtrs_group
+                    0x4               ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+alt_envsem          0x4               ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+ddr3_ram_BEFORE_EXCEPTION 0x0000000008000000 0x0000000000000120
+ddr3_ram         0x0000000008000120 0x0000000007fffee0
+reset            0x0000000014000000 0x0000000000000020
+ext_flash_avl_mem 0x0000000014000020 0x0000000003ffffe0
+onchip_flash_data 0x0000000018200000 0x0000000000160000
+descriptor_memory 0x0000000018400000 0x0000000000002000
+calibration_ram  0x0000000018403400 0x0000000000000280
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+LOAD obj/default/src/control.o
+LOAD obj/default/src/main.o
+LOAD obj/default/src/network_utilities.o
+LOAD obj/default/src/sensor.o
+LOAD obj/default/src/socket_server.o
+LOAD obj/default/src/tse_my_system.o
+LOAD obj/default/src/udpgen.o
+LOAD obj/default/src/utils.o
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libstdc++.a
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a
+START GROUP
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a
+LOAD ../hit_pat_bsp\libucosii_bsp.a
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libm.a
+END GROUP
+LOAD c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a
+                0x0000000008000000                __alt_mem_ddr3_ram = 0x8000000
+                0x0000000014000000                __alt_mem_ext_flash_avl_mem = 0x14000000
+                0x0000000018200000                __alt_mem_onchip_flash_data = 0x18200000
+                0x0000000018400000                __alt_mem_descriptor_memory = 0x18400000
+                0x0000000018403400                __alt_mem_calibration_ram = 0x18403400
+
+.entry          0x0000000014000000       0x20
+ *(.entry)
+ .entry         0x0000000014000000       0x20 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+                0x0000000014000000                __reset
+
+.exceptions     0x0000000008000120      0x218
+                [!provide]                        PROVIDE (__ram_exceptions_start = ABSOLUTE (.))
+                0x0000000008000120                . = ALIGN (0x20)
+ *(.irq)
+ *(.exceptions.entry.label)
+ .exceptions.entry.label
+                0x0000000008000120        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+                0x0000000008000120                alt_irq_entry
+ .exceptions.entry.label
+                0x0000000008000120        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+                0x0000000008000120                alt_exception
+ *(.exceptions.entry.user)
+ *(.exceptions.entry.ecc_fatal)
+ *(.exceptions.entry)
+ .exceptions.entry
+                0x0000000008000120       0x54 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ *(.exceptions.irqtest.user)
+ *(.exceptions.irqtest)
+ .exceptions.irqtest
+                0x0000000008000174       0x10 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ *(.exceptions.irqhandler.user)
+ *(.exceptions.irqhandler)
+ .exceptions.irqhandler
+                0x0000000008000184        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ *(.exceptions.irqreturn.user)
+ *(.exceptions.irqreturn)
+ .exceptions.irqreturn
+                0x0000000008000188        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ *(.exceptions.notirq.label)
+ .exceptions.notirq.label
+                0x000000000800018c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ *(.exceptions.notirq.user)
+ *(.exceptions.notirq)
+ .exceptions.notirq
+                0x000000000800018c        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ *(.exceptions.soft.user)
+ *(.exceptions.soft)
+ *(.exceptions.unknown.user)
+ *(.exceptions.unknown)
+ .exceptions.unknown
+                0x0000000008000194       0x14 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ *(.exceptions.exit.label)
+ .exceptions.exit.label
+                0x00000000080001a8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .exceptions.exit.label
+                0x00000000080001a8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ *(.exceptions.exit.user)
+ *(.exceptions.exit)
+ .exceptions.exit
+                0x00000000080001a8       0x54 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ *(.exceptions)
+ .exceptions    0x00000000080001fc       0xc8 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+                0x00000000080001fc                alt_irq_handler
+ .exceptions    0x00000000080002c4       0x74 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+                0x00000000080002c4                alt_instruction_exception_entry
+                [!provide]                        PROVIDE (__ram_exceptions_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_exceptions_start = LOADADDR (.exceptions))
+
+.text           0x0000000008000338    0x46670
+                [!provide]                        PROVIDE (stext = ABSOLUTE (.))
+ *(.interp)
+ *(.hash)
+ *(.dynsym)
+ *(.dynstr)
+ *(.gnu.version)
+ *(.gnu.version_d)
+ *(.gnu.version_r)
+ *(.rel.init)
+ *(.rela.init)
+ *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rel.fini)
+ *(.rela.fini)
+ *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rel.ctors)
+ *(.rela.ctors)
+ *(.rel.dtors)
+ *(.rela.dtors)
+ *(.rel.got)
+ *(.rela.got)
+ *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ *(.rel.plt)
+ *(.rela.plt)
+ *(.rel.dyn)
+ *(.init)
+ *(.plt)
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ .text          0x0000000008000338       0x48 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+                0x0000000008000338                _start
+ .text          0x0000000008000380      0xda4 obj/default/src/control.o
+                0x0000000008000380                control_delay
+                0x00000000080003b0                control_pong
+                0x0000000008000418                control_process_snapshot
+                0x0000000008000478                check_arp
+                0x00000000080004f8                control_process_config_peer
+                0x000000000800080c                control_get_header
+                0x00000000080008a4                control_get_data
+                0x0000000008000950                control_step
+                0x0000000008001064                ControlTask
+                0x00000000080010f0                control_init
+ .text          0x0000000008001124       0xc4 obj/default/src/main.o
+                0x0000000008001124                InitialTask
+                0x0000000008001178                main
+ .text          0x00000000080011e8      0x998 obj/default/src/network_utilities.o
+                0x00000000080011e8                get_mac_addr
+                0x000000000800123c                get_ip_addr
+                0x0000000008001434                get_serial_number
+                0x00000000080015c8                generate_and_store_mac_addr
+                0x0000000008001780                generate_mac_addr
+                0x00000000080018b4                get_board_mac_addr
+                0x0000000008001a54                FindLastFlashSectorOffset
+ .text          0x0000000008001b80      0x19c obj/default/src/sensor.o
+                0x0000000008001b80                sensor_command_bit
+                0x0000000008001c08                sensor_preconfigure
+ .text          0x0000000008001d1c      0x838 obj/default/src/socket_server.o
+                0x0000000008001d1c                ss_reset_connection
+                0x0000000008001d58                ss_initialize_connection
+                0x0000000008001da8                ss_handle_accept
+                0x0000000008001e90                SSListenerTask
+                0x0000000008002050                ethernet_init
+                0x00000000080020d0                ethernet_listen
+                0x000000000800220c                ethernet_write
+                0x0000000008002314                ethernet_read
+                0x00000000080024cc                ethernet_close
+ .text          0x0000000008002554        0x0 obj/default/src/tse_my_system.o
+ .text          0x0000000008002554      0x254 obj/default/src/udpgen.o
+                0x0000000008002554                udpgen_command_bit
+                0x00000000080025dc                udpgen_test
+ .text          0x00000000080027a8      0x488 obj/default/src/utils.o
+                0x00000000080027a8                swap_bytes
+                0x0000000008002840                swap_quad
+                0x0000000008002904                reload_fpga
+                0x0000000008002944                masterslave
+                0x00000000080029cc                master_clock_period
+                0x0000000008002a14                master_clock_enable
+                0x0000000008002a70                led_set
+                0x0000000008002abc                led_clear
+                0x0000000008002b08                led_toggle
+                0x0000000008002b7c                led4_blink_enable
+                0x0000000008002bc8                set_delay
+ .text          0x0000000008002c30        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .text          0x0000000008002c30        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .text._getchar_r
+                0x0000000008002c30        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+                0x0000000008002c30                _getchar_r
+ .text.getchar  0x0000000008002c38       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+                0x0000000008002c38                getchar
+ .text          0x0000000008002c48        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .text          0x0000000008002c48        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .text._printf_r
+                0x0000000008002c48       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+                0x0000000008002c48                _printf_r
+ .text.printf   0x0000000008002c78       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+                0x0000000008002c78                printf
+ .text          0x0000000008002cb0        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .text._putchar_r
+                0x0000000008002cb0        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+                0x0000000008002cb0                _putchar_r
+ .text.putchar  0x0000000008002cb8       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+                0x0000000008002cb8                putchar
+ .text          0x0000000008002cd0        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .text._puts_r  0x0000000008002cd0       0xcc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+                0x0000000008002cd0                _puts_r
+ .text.puts     0x0000000008002d9c       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+                0x0000000008002d9c                puts
+ .text          0x0000000008002dac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .text.strlen   0x0000000008002dac       0x98 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+                0x0000000008002dac                strlen
+ .text          0x0000000008002e44        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .text.___vfprintf_internal_r
+                0x0000000008002e44     0x2160 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+                0x0000000008002e44                ___vfprintf_internal_r
+ .text.__vfprintf_internal
+                0x0000000008004fa4       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+                0x0000000008004fa4                __vfprintf_internal
+ .text.__sbprintf
+                0x0000000008004fbc       0xc0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .text          0x000000000800507c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .text.__swsetup_r
+                0x000000000800507c      0x160 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+                0x000000000800507c                __swsetup_r
+ .text          0x00000000080051dc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .text.quorem   0x00000000080051dc      0x210 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .text._dtoa_r  0x00000000080053ec     0x16c8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+                0x00000000080053ec                _dtoa_r
+ .text          0x0000000008006ab4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .text.__sflush_r
+                0x0000000008006ab4      0x228 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+                0x0000000008006ab4                __sflush_r
+ .text._fflush_r
+                0x0000000008006cdc       0x60 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+                0x0000000008006cdc                _fflush_r
+ .text.fflush   0x0000000008006d3c       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+                0x0000000008006d3c                fflush
+ .text          0x0000000008006d64        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .text.__fp_lock
+                0x0000000008006d64        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .text._cleanup_r
+                0x0000000008006d6c        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008006d6c                _cleanup_r
+ .text.__sinit.part.0
+                0x0000000008006d78      0x168 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .text.__fp_unlock
+                0x0000000008006ee0        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .text.__sfmoreglue
+                0x0000000008006ee8       0x68 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008006ee8                __sfmoreglue
+ .text.__sfp    0x0000000008006f50       0xfc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008006f50                __sfp
+ .text._cleanup
+                0x000000000800704c       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x000000000800704c                _cleanup
+ .text.__sinit  0x0000000008007060       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007060                __sinit
+ .text.__sfp_lock_acquire
+                0x0000000008007070        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007070                __sfp_lock_acquire
+ .text.__sfp_lock_release
+                0x0000000008007074        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007074                __sfp_lock_release
+ .text.__sinit_lock_acquire
+                0x0000000008007078        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007078                __sinit_lock_acquire
+ .text.__sinit_lock_release
+                0x000000000800707c        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x000000000800707c                __sinit_lock_release
+ .text.__fp_lock_all
+                0x0000000008007080       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007080                __fp_lock_all
+ .text.__fp_unlock_all
+                0x0000000008007094       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                0x0000000008007094                __fp_unlock_all
+ .text          0x00000000080070a8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .text._malloc_trim_r
+                0x00000000080070a8      0x11c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+                0x00000000080070a8                _malloc_trim_r
+ .text._free_r  0x00000000080071c4      0x2fc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+                0x00000000080071c4                _free_r
+ .text          0x00000000080074c0        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .text.__sfvwrite_r
+                0x00000000080074c0      0x4c4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+                0x00000000080074c0                __sfvwrite_r
+ .text          0x0000000008007984        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .text._fwalk   0x0000000008007984       0xa4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+                0x0000000008007984                _fwalk
+ .text._fwalk_reent
+                0x0000000008007a28       0xb4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+                0x0000000008007a28                _fwalk_reent
+ .text          0x0000000008007adc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .text._getc_r  0x0000000008007adc       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+                0x0000000008007adc                _getc_r
+ .text.getc     0x0000000008007b58       0x90 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+                0x0000000008007b58                getc
+ .text          0x0000000008007be8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .text.__localeconv_l
+                0x0000000008007be8        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+                0x0000000008007be8                __localeconv_l
+ .text._localeconv_r
+                0x0000000008007bf0        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+                0x0000000008007bf0                _localeconv_r
+ .text.localeconv
+                0x0000000008007bfc        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+                0x0000000008007bfc                localeconv
+ .text          0x0000000008007c08        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .text.__swhatbuf_r
+                0x0000000008007c08       0x98 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+                0x0000000008007c08                __swhatbuf_r
+ .text.__smakebuf_r
+                0x0000000008007ca0      0x13c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+                0x0000000008007ca0                __smakebuf_r
+ .text          0x0000000008007ddc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .text._malloc_r
+                0x0000000008007ddc      0x7f4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x0000000008007ddc                _malloc_r
+ .text          0x00000000080085d0        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .text.memchr   0x00000000080085d0       0xe8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+                0x00000000080085d0                memchr
+ .text          0x00000000080086b8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .text.memcpy   0x00000000080086b8      0x100 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+                0x00000000080086b8                memcpy
+ .text          0x00000000080087b8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .text.memmove  0x00000000080087b8      0x12c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+                0x00000000080087b8                memmove
+ .text          0x00000000080088e4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .text.memset   0x00000000080088e4       0xf0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+                0x00000000080088e4                memset
+ .text          0x00000000080089d4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .text._Balloc  0x00000000080089d4       0xa4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080089d4                _Balloc
+ .text._Bfree   0x0000000008008a78       0x24 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008a78                _Bfree
+ .text.__multadd
+                0x0000000008008a9c      0x114 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008a9c                __multadd
+ .text.__s2b    0x0000000008008bb0      0x110 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008bb0                __s2b
+ .text.__hi0bits
+                0x0000000008008cc0       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008cc0                __hi0bits
+ .text.__lo0bits
+                0x0000000008008d24       0xb0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008d24                __lo0bits
+ .text.__i2b    0x0000000008008dd4       0x34 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008dd4                __i2b
+ .text.__multiply
+                0x0000000008008e08      0x1ec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008e08                __multiply
+ .text.__pow5mult
+                0x0000000008008ff4      0x128 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008008ff4                __pow5mult
+ .text.__lshift
+                0x000000000800911c      0x13c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x000000000800911c                __lshift
+ .text.__mcmp   0x0000000008009258       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008009258                __mcmp
+ .text.__mdiff  0x00000000080092b0      0x1bc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080092b0                __mdiff
+ .text.__ulp    0x000000000800946c       0x5c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x000000000800946c                __ulp
+ .text.__b2d    0x00000000080094c8      0x104 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080094c8                __b2d
+ .text.__d2b    0x00000000080095cc      0x148 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080095cc                __d2b
+ .text.__ratio  0x0000000008009714       0xa8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008009714                __ratio
+ .text._mprec_log10
+                0x00000000080097bc       0x74 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080097bc                _mprec_log10
+ .text.__copybits
+                0x0000000008009830       0x6c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008009830                __copybits
+ .text.__any_on
+                0x000000000800989c       0x74 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x000000000800989c                __any_on
+ .text          0x0000000008009910        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .text._putc_r  0x0000000008009910       0xcc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+                0x0000000008009910                _putc_r
+ .text.putc     0x00000000080099dc       0xe0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+                0x00000000080099dc                putc
+ .text          0x0000000008009abc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .text._realloc_r
+                0x0000000008009abc      0x62c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+                0x0000000008009abc                _realloc_r
+ .text          0x000000000800a0e8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .text.__srget_r
+                0x000000000800a0e8       0x74 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+                0x000000000800a0e8                __srget_r
+ .text.__srget  0x000000000800a15c       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+                0x000000000800a15c                __srget
+ .text          0x000000000800a16c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .text._sbrk_r  0x000000000800a16c       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+                0x000000000800a16c                _sbrk_r
+ .text          0x000000000800a1c4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .text.__sread  0x000000000800a1c4       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                0x000000000800a1c4                __sread
+ .text.__seofread
+                0x000000000800a218        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                0x000000000800a218                __seofread
+ .text.__swrite
+                0x000000000800a220       0x80 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                0x000000000800a220                __swrite
+ .text.__sseek  0x000000000800a2a0       0x5c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                0x000000000800a2a0                __sseek
+ .text.__sclose
+                0x000000000800a2fc        0x8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                0x000000000800a2fc                __sclose
+ .text          0x000000000800a304        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .text.__sprint_r.part.0
+                0x000000000800a304       0xf4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .text.__sprint_r
+                0x000000000800a3f8       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+                0x000000000800a3f8                __sprint_r
+ .text.___vfiprintf_internal_r
+                0x000000000800a410     0x132c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+                0x000000000800a410                ___vfiprintf_internal_r
+ .text.__vfiprintf_internal
+                0x000000000800b73c       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+                0x000000000800b73c                __vfiprintf_internal
+ .text.__sbprintf
+                0x000000000800b754       0xc0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .text          0x000000000800b814        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .text.__swbuf_r
+                0x000000000800b814      0x148 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+                0x000000000800b814                __swbuf_r
+ .text.__swbuf  0x000000000800b95c       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+                0x000000000800b95c                __swbuf
+ .text          0x000000000800b970        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .text._write_r
+                0x000000000800b970       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+                0x000000000800b970                _write_r
+ .text          0x000000000800b9d4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .text._close_r
+                0x000000000800b9d4       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+                0x000000000800b9d4                _close_r
+ .text          0x000000000800ba2c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .text._calloc_r
+                0x000000000800ba2c       0xb8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+                0x000000000800ba2c                _calloc_r
+ .text          0x000000000800bae4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .text._fclose_r
+                0x000000000800bae4       0xf8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+                0x000000000800bae4                _fclose_r
+ .text.fclose   0x000000000800bbdc       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+                0x000000000800bbdc                fclose
+ .text          0x000000000800bbec        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .text.__fputwc
+                0x000000000800bbec      0x150 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+                0x000000000800bbec                __fputwc
+ .text._fputwc_r
+                0x000000000800bd3c       0x24 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+                0x000000000800bd3c                _fputwc_r
+ .text.fputwc   0x000000000800bd60       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+                0x000000000800bd60                fputwc
+ .text          0x000000000800bddc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .text._fstat_r
+                0x000000000800bddc       0x60 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+                0x000000000800bddc                _fstat_r
+ .text          0x000000000800be3c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .text          0x000000000800be3c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .text._isatty_r
+                0x000000000800be3c       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+                0x000000000800be3c                _isatty_r
+ .text          0x000000000800be94        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .text._setlocale_r
+                0x000000000800be94       0x70 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                0x000000000800be94                _setlocale_r
+ .text.__locale_mb_cur_max
+                0x000000000800bf04        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                0x000000000800bf04                __locale_mb_cur_max
+ .text.setlocale
+                0x000000000800bf10       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                0x000000000800bf10                setlocale
+ .text          0x000000000800bf24        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .text._lseek_r
+                0x000000000800bf24       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+                0x000000000800bf24                _lseek_r
+ .text          0x000000000800bf88        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .text._mbtowc_r
+                0x000000000800bf88        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+                0x000000000800bf88                _mbtowc_r
+ .text.__ascii_mbtowc
+                0x000000000800bf94       0x44 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+                0x000000000800bf94                __ascii_mbtowc
+ .text          0x000000000800bfd8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .text._read_r  0x000000000800bfd8       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+                0x000000000800bfd8                _read_r
+ .text          0x000000000800c03c        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .text.lflush   0x000000000800c03c       0x1c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .text.__srefill_r
+                0x000000000800c058      0x1cc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+                0x000000000800c058                __srefill_r
+ .text          0x000000000800c224        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .text.strcmp   0x000000000800c224       0xd8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+                0x000000000800c224                strcmp
+ .text          0x000000000800c2fc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .text._wcrtomb_r
+                0x000000000800c2fc       0x6c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+                0x000000000800c2fc                _wcrtomb_r
+ .text.wcrtomb  0x000000000800c368       0x84 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+                0x000000000800c368                wcrtomb
+ .text          0x000000000800c3ec        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .text._wctomb_r
+                0x000000000800c3ec        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+                0x000000000800c3ec                _wctomb_r
+ .text.__ascii_wctomb
+                0x000000000800c3f8       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+                0x000000000800c3f8                __ascii_wctomb
+ .text          0x000000000800c428      0x598 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+                0x000000000800c428                __udivdi3
+ .text          0x000000000800c9c0      0x540 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+                0x000000000800c9c0                __umoddi3
+ .text          0x000000000800cf00      0x1b8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+                0x000000000800cf00                __divsi3
+                0x000000000800cf80                __modsi3
+                0x000000000800cff8                __udivsi3
+                0x000000000800d05c                __umodsi3
+ .text          0x000000000800d0b8      0x9a0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+                0x000000000800d0b8                __adddf3
+ .text          0x000000000800da58      0x8a8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+                0x000000000800da58                __divdf3
+ .text          0x000000000800e300       0x80 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+                0x000000000800e300                __nedf2
+                0x000000000800e300                __eqdf2
+ .text          0x000000000800e380       0xf0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+                0x000000000800e380                __gedf2
+                0x000000000800e380                __gtdf2
+ .text          0x000000000800e470       0xf0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+                0x000000000800e470                __ledf2
+                0x000000000800e470                __ltdf2
+ .text          0x000000000800e560      0x68c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+                0x000000000800e560                __muldf3
+ .text          0x000000000800ebec      0x96c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+                0x000000000800ebec                __subdf3
+ .text          0x000000000800f558       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+                0x000000000800f558                __unorddf2
+ .text          0x000000000800f5ac       0x80 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+                0x000000000800f5ac                __fixdfsi
+ .text          0x000000000800f62c       0xc8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+                0x000000000800f62c                __floatsidf
+ .text          0x000000000800f6f4       0x9c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+                0x000000000800f6f4                __floatunsidf
+ .text          0x000000000800f790        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .text          0x000000000800f790       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+                0x000000000800f790                __clzsi2
+ .text          0x000000000800f7e4       0xbc ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+                0x000000000800f7e4                alt_flash_open_dev
+                0x000000000800f84c                alt_flash_close_dev
+ .text          0x000000000800f8a0       0xec ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+                0x000000000800f8dc                fstat
+ .text          0x000000000800f98c       0xe0 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+                0x000000000800f9c8                isatty
+ .text          0x000000000800fa6c      0x110 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+                0x000000000800faa8                lseek
+ .text          0x000000000800fb7c       0xbc ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+                0x000000000800fb7c                alt_main
+ .text          0x000000000800fc38       0xb0 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+                0x000000000800fc38                sbrk
+ .text          0x000000000800fce8      0x124 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+                0x000000000800fce8                __env_lock
+                0x000000000800fdac                __env_unlock
+ .text          0x000000000800fe0c      0x1ec ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+                0x000000000800fe0c                __malloc_lock
+                0x000000000800ff2c                __malloc_unlock
+ .text          0x000000000800fff8     0x1ba0 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                0x000000000800fff8                OSEventNameGet
+                0x00000000080100d0                OSEventNameSet
+                0x00000000080101d0                OSEventPendMulti
+                0x000000000801077c                OSInit
+                0x00000000080107cc                OSIntEnter
+                0x0000000008010818                OSIntExit
+                0x0000000008010908                OSSchedLock
+                0x0000000008010994                OSSchedUnlock
+                0x0000000008010a70                OSStart
+                0x0000000008010ad8                OSTimeTick
+                0x0000000008010c98                OSVersion
+                0x0000000008010cb8                OS_Dummy
+                0x0000000008010cd8                OS_EventTaskRdy
+                0x0000000008010e60                OS_EventTaskWait
+                0x0000000008010f68                OS_EventTaskWaitMulti
+                0x00000000080110b0                OS_EventTaskRemove
+                0x0000000008011160                OS_EventTaskRemoveMulti
+                0x0000000008011258                OS_EventWaitListInit
+                0x00000000080115b0                OS_MemClr
+                0x0000000008011604                OS_MemCopy
+                0x000000000801166c                OS_Sched
+                0x00000000080117a0                OS_StrCopy
+                0x0000000008011814                OS_StrLen
+                0x0000000008011868                OS_TaskIdle
+                0x00000000080118c4                OS_TCBInit
+ .text          0x0000000008011b98     0x15b8 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+                0x0000000008011b98                OSFlagAccept
+                0x0000000008011e78                OSFlagCreate
+                0x0000000008011f70                OSFlagDel
+                0x000000000801218c                OSFlagNameGet
+                0x000000000801226c                OSFlagNameSet
+                0x0000000008012378                OSFlagPend
+                0x0000000008012910                OSFlagPendGetFlagsRdy
+                0x0000000008012970                OSFlagPost
+                0x0000000008012cdc                OSFlagQuery
+                0x0000000008012ed8                OS_FlagInit
+                0x00000000080130ac                OS_FlagUnlink
+ .text          0x0000000008013150      0x5d4 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+                0x0000000008013150                OSMemCreate
+                0x0000000008013298                OSMemGet
+                0x000000000801335c                OSMemNameGet
+                0x0000000008013404                OSMemNameSet
+                0x00000000080134d8                OSMemPut
+                0x0000000008013590                OSMemQuery
+                0x0000000008013658                OS_MemInit
+ .text          0x0000000008013724      0xfe0 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+                0x0000000008013724                OSMutexAccept
+                0x000000000801389c                OSMutexCreate
+                0x0000000008013a1c                OSMutexDel
+                0x0000000008013cdc                OSMutexPend
+                0x0000000008014238                OSMutexPost
+                0x0000000008014430                OSMutexQuery
+ .text          0x0000000008014704      0xfd0 ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+                0x0000000008014704                OSQAccept
+                0x0000000008014818                OSQCreate
+                0x00000000080149bc                OSQDel
+                0x0000000008014c10                OSQFlush
+                0x0000000008014c9c                OSQPend
+                0x0000000008014efc                OSQPendAbort
+                0x000000000801503c                OSQPost
+                0x0000000008015194                OSQPostFront
+                0x00000000080152f4                OSQPostOpt
+                0x00000000080154f0                OSQQuery
+                0x000000000801562c                OS_QInit
+ .text          0x00000000080156d4      0x978 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+                0x00000000080156d4                OSSemAccept
+                0x0000000008015774                OSSemCreate
+                0x000000000801584c                OSSemDel
+                0x0000000008015a60                OSSemPend
+                0x0000000008015c44                OSSemPendAbort
+                0x0000000008015d84                OSSemPost
+                0x0000000008015e84                OSSemQuery
+                0x0000000008015f74                OSSemSet
+ .text          0x000000000801604c     0x12c0 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+                0x000000000801604c                OSTaskChangePrio
+                0x00000000080164cc                OSTaskCreate
+                0x000000000801664c                OSTaskCreateExt
+                0x00000000080167f0                OSTaskDel
+                0x0000000008016b04                OSTaskDelReq
+                0x0000000008016c2c                OSTaskNameGet
+                0x0000000008016d64                OSTaskNameSet
+                0x0000000008016ec0                OSTaskResume
+                0x0000000008017078                OSTaskSuspend
+                0x0000000008017220                OSTaskQuery
+ .text          0x000000000801730c      0x488 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+                0x000000000801730c                OSTimeDly
+                0x0000000008017410                OSTimeDlyHMSM
+                0x000000000801750c                OSTimeDlyResume
+                0x00000000080176d8                OSTimeGet
+                0x0000000008017734                OSTimeSet
+ .text          0x0000000008017794      0x298 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+                0x00000000080177c8                alt_irq_init
+                0x0000000008017800                alt_sys_init
+ .text          0x0000000008017a2c       0xf4 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+                0x0000000008017aa4                alt_avalon_timer_sc_init
+ .text          0x0000000008017b20     0x4f20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                0x0000000008017b20                no_printf
+                0x0000000008017b50                tse_mac_initTransInfo2
+                0x0000000008017bb0                tse_mac_sTxWrite
+                0x0000000008017c78                tse_mac_aRxRead
+                0x0000000008017ce8                tse_mac_aTxWrite
+                0x0000000008017d58                tse_mac_SwReset
+                0x0000000008017de0                tse_mac_setMIImode
+                0x0000000008017e34                tse_mac_setGMIImode
+                0x0000000008017e84                alt_tse_phy_add_profile
+                0x0000000008018038                alt_tse_system_add_sys
+                0x00000000080188fc                alt_tse_sys_enable_mdio_sharing
+                0x0000000008018a40                alt_tse_mac_get_common_speed
+                0x0000000008018a80                alt_tse_mac_set_common_speed
+                0x0000000008018ac8                alt_tse_get_system_index
+                0x0000000008018b34                alt_tse_get_mac_group_index
+                0x0000000008018ba0                alt_tse_get_mac_info_index
+                0x0000000008018c1c                alt_tse_get_mac_info
+                0x0000000008018ce8                alt_tse_mac_set_speed
+                0x0000000008018dc8                alt_tse_mac_set_duplex
+                0x0000000008018e54                getPHYSpeed
+                0x00000000080198cc                alt_tse_phy_rd_mdio_addr
+                0x0000000008019914                alt_tse_phy_wr_mdio_addr
+                0x000000000801996c                alt_tse_phy_wr_mdio_reg
+                0x0000000008019a98                alt_tse_phy_rd_mdio_reg
+                0x0000000008019b68                alt_tse_phy_add_profile_default
+                0x0000000008019e30                alt_tse_phy_print_profile
+                0x000000000801a000                alt_tse_mac_group_init
+                0x000000000801a698                alt_tse_mac_get_phy
+                0x000000000801aaa4                alt_tse_mac_associate_phy
+                0x000000000801ace4                alt_tse_phy_cfg_pcs
+                0x000000000801ae0c                alt_tse_phy_init
+                0x000000000801af18                alt_tse_phy_restart_an
+                0x000000000801b0dc                alt_tse_phy_check_link
+                0x000000000801b264                alt_tse_phy_get_cap
+                0x000000000801b7f0                alt_tse_phy_set_adv_1000
+                0x000000000801b9b4                alt_tse_phy_set_adv_100
+                0x000000000801bc08                alt_tse_phy_set_adv_10
+                0x000000000801bdb0                alt_tse_phy_get_common_speed
+                0x000000000801c0cc                alt_tse_phy_set_common_speed
+                0x000000000801c57c                marvell_phy_cfg
+                0x000000000801c614                marvell_cfg_gmii
+                0x000000000801c6f8                marvell_cfg_sgmii
+                0x000000000801c7dc                marvell_cfg_rgmii
+                0x000000000801c8cc                DP83848C_link_status_read
+                0x000000000801c944                PEF7071_config
+                0x000000000801c9a0                PEF7071_link_status_read
+ .text          0x000000000801ca40      0x110 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+                0x000000000801ca40                altera_avalon_uart_read_fd
+                0x000000000801caa0                altera_avalon_uart_write_fd
+                0x000000000801cb00                altera_avalon_uart_close_fd
+ .text          0x000000000801cb50      0x524 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+                0x000000000801cb50                altera_avalon_uart_init
+                0x000000000801d020                altera_avalon_uart_close
+ .text          0x000000000801d074      0x2a4 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+                0x000000000801d0b0                altera_avalon_uart_read
+ .text          0x000000000801d318      0x270 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+                0x000000000801d354                altera_avalon_uart_write
+ .text          0x000000000801d588      0xb14 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+                0x000000000801d5bc                alt_qspi_controller_lock
+                0x000000000801d6cc                alt_qspi_controller_get_info
+                0x000000000801d758                alt_qspi_controller_erase_block
+                0x000000000801d87c                alt_qspi_controller_write_block
+                0x000000000801da8c                alt_qspi_controller_write
+                0x000000000801dc74                alt_qspi_controller_read
+                0x000000000801dd20                altera_qspi_controller_init
+ .text          0x000000000801e09c     0x213c ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+                0x000000000801ed40                alt_msgdma_construct_standard_st_to_mm_descriptor
+                0x000000000801ed98                alt_msgdma_construct_standard_mm_to_st_descriptor
+                0x000000000801edf0                alt_msgdma_construct_standard_mm_to_mm_descriptor
+                0x000000000801ee48                alt_msgdma_construct_extended_st_to_mm_descriptor
+                0x000000000801eed8                alt_msgdma_construct_extended_mm_to_st_descriptor
+                0x000000000801ef68                alt_msgdma_construct_extended_mm_to_mm_descriptor
+                0x000000000801f248                alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
+                0x000000000801f2a0                alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
+                0x000000000801f2f8                alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
+                0x000000000801f350                alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
+                0x000000000801f3f0                alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
+                0x000000000801f488                alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
+                0x000000000801f540                alt_msgdma_prefetcher_add_standard_desc_to_list
+                0x000000000801f630                alt_msgdma_prefetcher_add_extended_desc_to_list
+                0x000000000801f7c8                alt_msgdma_prefetcher_set_std_list_own_by_hw_bits
+                0x000000000801f8d8                alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits
+                0x000000000801fa24                alt_msgdma_start_prefetcher_with_list_addr
+                0x000000000801fd34                alt_msgdma_start_prefetcher_with_std_desc_list
+                0x000000000801fde4                alt_msgdma_start_prefetcher_with_extd_desc_list
+                0x000000000801fe94                alt_msgdma_open
+                0x000000000801feec                alt_msgdma_init
+                0x0000000008020094                alt_msgdma_register_callback
+                0x00000000080200e8                alt_msgdma_standard_descriptor_async_transfer
+                0x0000000008020124                alt_msgdma_extended_descriptor_async_transfer
+                0x0000000008020160                alt_msgdma_standard_descriptor_sync_transfer
+                0x000000000802019c                alt_msgdma_extended_descriptor_sync_transfer
+ .text          0x00000000080201d8      0xf00 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+                0x000000000802020c                alt_onchip_flash_read
+                0x00000000080202d8                alt_onchip_flash_get_info
+                0x0000000008020374                alt_onchip_flash_erase_block
+                0x00000000080204dc                alt_onchip_flash_write_block
+                0x00000000080207b4                alt_onchip_flash_write
+                0x0000000008020a80                altera_onchip_flash_init
+                0x0000000008020f20                alt_onchip_flash_poll_for_status_to_go_idle
+                0x0000000008020fb0                alt_onchip_flash_poll_for_status_erase_passed
+                0x0000000008021044                alt_onchip_flash_poll_for_status_write_passed
+ .text          0x00000000080210d8     0x1988 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+                0x00000000080210d8                altera_eth_tse_init
+                0x0000000008021220                prep_tse_mac
+                0x000000000802144c                msgdma_reset
+                0x00000000080214c4                tse_mac_init
+                0x0000000008021f28                tse_msgdma_write_init
+                0x0000000008022048                tse_mac_raw_send
+                0x0000000008022210                tse_msgdmaRx_isr
+                0x00000000080223a8                tse_msgdmaTx_isr
+                0x0000000008022408                tse_msgdma_read_init
+                0x00000000080226c0                allocate_rx_descriptor_chain
+                0x00000000080227f8                tse_mac_rcv
+                0x0000000008022944                tse_mac_stats
+                0x0000000008022984                tse_mac_close
+ .text          0x0000000008022a60       0x48 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+                0x0000000008022a60                close
+ .text          0x0000000008022aa8      0x124 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+                0x0000000008022aa8                iniche_devices_init
+ .text          0x0000000008022bcc       0x70 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+                0x0000000008022bcc                read
+ .text          0x0000000008022c3c       0x68 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+                0x0000000008022c3c                write
+ .text          0x0000000008022ca4     0x13e4 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                0x0000000008022ca4                etainit
+                0x0000000008022cec                et_send
+                0x0000000008022e6c                arp_free_pending
+                0x0000000008022ef4                arp_send_pending
+                0x0000000008022f68                send_arp
+                0x00000000080233bc                find_oldest_arp
+                0x0000000008023528                make_arp_entry
+                0x0000000008023624                arpReply
+                0x00000000080238e4                arprcv
+                0x0000000008023b48                send_via_arp
+                0x0000000008023cc4                cb_arpent_tmo
+                0x0000000008023dd0                grat_arp
+ .text          0x0000000008024088      0x25c ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+                0x0000000008024088                if_getbynum
+                0x00000000080240f4                isbcast
+                0x00000000080241c8                reg_type
+                0x0000000008024254                if_killsocks
+ .text          0x00000000080242e4      0xc9c ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+                0x00000000080242e4                Netinit
+                0x00000000080247b4                fixup_subnet_mask
+                0x00000000080248e4                netclose
+                0x00000000080249c4                pktdemux
+                0x0000000008024d64                c_older
+                0x0000000008024df4                ip2mac
+ .text          0x0000000008024f80      0x3fc ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                0x0000000008024f80                ip_startup
+                0x00000000080251e4                exit_hook
+                0x000000000802524c                ip_exit
+                0x00000000080252fc                if_netnumber
+ .text          0x000000000802537c      0xe98 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+                0x000000000802537c                igmp_init
+                0x000000000802541c                igmp_input
+                0x00000000080254ec                igmp_fasttimo
+                0x000000000802565c                igmp_send
+                0x00000000080258d8                igmp_joingroup
+                0x0000000008025b04                igmp_leavegroup
+                0x0000000008025b84                igmp_validate
+                0x0000000008025e60                igmp_print_stats
+ .text          0x0000000008026214      0xac4 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+                0x0000000008026214                bsd_accept
+                0x0000000008026334                bsd_getpeername
+                0x0000000008026454                bsd_getsockname
+                0x0000000008026574                bsd_i_sockoptlen
+                0x0000000008026704                bsd_getsockopt
+                0x000000000802680c                bsd_ioctl
+                0x00000000080268fc                bsd_inet_ntoa
+                0x0000000008026930                bsd_recvfrom
+                0x0000000008026a74                bsd_select
+                0x0000000008026bfc                bsd_setsockopt
+ .text          0x0000000008026cd8       0xf8 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+                0x0000000008026cd8                ccksum
+                0x0000000008026d7c                cksum
+ .text          0x0000000008026dd0      0xa44 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+                0x0000000008026dd0                do_trap
+                0x0000000008026dfc                nextarg
+                0x0000000008026e78                hexdump
+                0x0000000008026fbc                print_ipad
+                0x0000000008027038                print_uptime
+                0x0000000008027178                panic
+                0x00000000080271c0                print_eth
+                0x0000000008027314                uslash
+                0x0000000008027390                ns_printf
+                0x0000000008027500                std_out
+                0x0000000008027544                con_page
+                0x000000000802761c                parse_args
+ .text          0x0000000008027814      0x19c ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                0x0000000008027814                netmain
+                0x00000000080278f4                tk_netmain
+                0x000000000802796c                tk_nettick
+ .text          0x00000000080279b0      0x55c ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+                0x00000000080279b0                TK_OSTimeDly
+                0x00000000080279e0                TK_OSTaskResume
+                0x0000000008027a54                tcp_sleep
+                0x0000000008027ba0                tcp_wakeup
+                0x0000000008027c78                TK_OSTaskQuery
+                0x0000000008027ce4                tk_yield
+                0x0000000008027d14                tk_stats
+ .text          0x0000000008027f0c      0x29c ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+                0x0000000008027f0c                icmpEcho
+ .text          0x00000000080281a8      0x730 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+                0x00000000080281a8                pk_init
+                0x0000000008028434                pk_alloc
+                0x00000000080284f4                pk_validate
+                0x0000000008028748                pk_free
+                0x00000000080287f4                pk_get_max_intrsafe_buf_len
+                0x0000000008028814                dump_buf_estats
+ .text          0x00000000080288d8      0x268 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+                0x00000000080288d8                getq
+                0x0000000008028990                putq
+                0x0000000008028a40                qdel
+ .text          0x0000000008028b40      0x194 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+                0x0000000008028b40                asm_cksum
+ .text          0x0000000008028cd4      0x264 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+                0x0000000008028cd4                dtrap
+                0x0000000008028d08                kbhit
+                0x0000000008028d90                getch
+                0x0000000008028de0                clock_init
+                0x0000000008028e18                clock_c
+                0x0000000008028e38                cticks_hook
+                0x0000000008028e94                irq_Mask
+                0x0000000008028ef4                irq_Unmask
+ .text          0x0000000008028f38      0x4a4 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+                0x0000000008028f38                LOCK_NET_RESOURCE
+                0x0000000008028ff4                UNLOCK_NET_RESOURCE
+                0x0000000008029074                TK_NEWTASK
+                0x00000000080292b4                wait_app_sem
+                0x0000000008029368                post_app_sem
+ .text          0x00000000080293dc      0x538 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+                0x00000000080293dc                alt_iniche_init
+                0x000000000802959c                pre_task_setup
+                0x00000000080295e8                post_task_setup
+                0x0000000008029608                prep_armintcp
+                0x0000000008029640                npalloc_base
+                0x000000000802974c                npfree_base
+                0x000000000802982c                npalloc
+                0x0000000008029860                npfree
+                0x00000000080298a0                ncpalloc
+                0x00000000080298d4                ncpfree
+ .text          0x0000000008029914     0x17b4 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                0x0000000008029914                pffindtype
+                0x00000000080299a4                pffindproto
+                0x0000000008029a70                m_getnbuf
+                0x0000000008029bf8                m_free
+                0x0000000008029cfc                m_freem
+                0x0000000008029d40                m_copy
+                0x000000000802a018                m_adj
+                0x000000000802a1d8                mbuf_len
+                0x000000000802a22c                dtom
+                0x000000000802a2c4                remque
+                0x000000000802a334                insque
+                0x000000000802a3b0                nptcp_init
+                0x000000000802a4a4                tcp_rcv
+                0x000000000802a658                ip_output
+                0x000000000802abe0                in_broadcast
+                0x000000000802ac18                np_stripoptions
+                0x000000000802ad08                so_icmpdu
+                0x000000000802b050                tcp_tick
+ .text          0x000000000802b0c8      0x958 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+                0x000000000802b0c8                rawip_lookup
+                0x000000000802b124                rawip_soinput
+                0x000000000802b2e8                rawip_usrreq
+ .text          0x000000000802ba20     0x1630 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+                0x000000000802ba20                DOMAIN_CHECK
+                0x000000000802ba70                t_socket
+                0x000000000802baf0                t_bind
+                0x000000000802bc50                t_listen
+                0x000000000802bd24                t_accept
+                0x000000000802bf74                t_connect
+                0x000000000802c1e4                t_getpeername
+                0x000000000802c228                t_getsockname
+                0x000000000802c44c                t_setsockopt
+                0x000000000802c60c                t_getsockopt
+                0x000000000802c794                t_recv
+                0x000000000802c870                t_recvfrom
+                0x000000000802c9ac                t_sendto
+                0x000000000802cb9c                t_send
+                0x000000000802cd9c                t_shutdown
+                0x000000000802ce70                t_socketclose
+                0x000000000802cfbc                t_errno
+ .text          0x000000000802d050     0x2128 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+                0x000000000802d050                socreate
+                0x000000000802d1f8                sobind
+                0x000000000802d254                solisten
+                0x000000000802d324                sofree
+                0x000000000802d434                soclose
+                0x000000000802d6fc                soabort
+                0x000000000802d74c                soaccept
+                0x000000000802d7e4                soconnect
+                0x000000000802d89c                sodisconnect
+                0x000000000802d934                sosend
+                0x000000000802de94                soreceive
+                0x000000000802e5ec                soshutdown
+                0x000000000802e684                sorflush
+                0x000000000802e780                sosetopt
+                0x000000000802ec0c                sogetopt
+                0x000000000802f12c                sohasoutofband
+ .text          0x000000000802f178     0x1280 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+                0x000000000802f178                soisconnecting
+                0x000000000802f1e8                soisconnected
+                0x000000000802f2ec                soisdisconnecting
+                0x000000000802f384                soisdisconnected
+                0x000000000802f448                sonewconn
+                0x000000000802f640                soqinsque
+                0x000000000802f6ec                soqremque
+                0x000000000802f7f4                socantsendmore
+                0x000000000802f84c                socantrcvmore
+                0x000000000802f8a4                sbselqueue
+                0x000000000802f8e0                sbwait
+                0x000000000802f94c                sbwakeup
+                0x000000000802f9d8                soreserve
+                0x000000000802fa60                sbreserve
+                0x000000000802fab0                sbrelease
+                0x000000000802fafc                sbappend
+                0x000000000802fb9c                sbappendrecord
+                0x000000000802fc74                sbappendaddr
+                0x000000000802fe50                sbcompress
+                0x000000000803002c                sbflush
+                0x00000000080300b0                sbdrop
+                0x0000000008030268                sbdropend
+                0x0000000008030368                sbdroprecord
+ .text          0x00000000080303f8      0x868 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+                0x00000000080303f8                t_select
+                0x00000000080305c8                sock_selscan
+                0x0000000008030708                sock_select
+                0x00000000080308f0                in_pcbnotify
+                0x00000000080309b4                tcp_notify
+                0x0000000008030a34                ifd_clr
+                0x0000000008030b18                ifd_set
+                0x0000000008030b8c                ifd_isset
+                0x0000000008030c00                ifd_get
+ .text          0x0000000008030c60     0x2c34 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                0x0000000008030c60                tcp_reass
+                0x0000000008031050                tcp_input
+                0x0000000008033264                tcp_dooptions
+                0x00000000080333ec                tcp_pulloutofband
+                0x0000000008033518                tcp_xmit_timer
+                0x0000000008033754                ip4_tcpmss
+                0x000000000803379c                tcp_mss
+ .text          0x0000000008033894     0x1164 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+                0x0000000008033894                tcp_output
+                0x0000000008034830                tcp_setpersist
+ .text          0x00000000080349f8      0x910 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+                0x00000000080349f8                tcp_init
+                0x0000000008034a40                tcp_template
+                0x0000000008034b48                tcp_respond
+                0x0000000008034f40                tcp_newtcpcb
+                0x000000000803504c                tcp_drop
+                0x00000000080350e8                tcp_close
+                0x00000000080351d0                tcp_quench
+                0x000000000803521c                tcp_putseq
+                0x0000000008035294                tcp_getseq
+ .text          0x0000000008035308      0x70c ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                0x0000000008035308                tcp_slowtimo
+                0x0000000008035564                tcp_canceltimers
+                0x00000000080355c0                tcp_timers
+ .text          0x0000000008035a14      0x968 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+                0x0000000008035a14                tcp_usrreq
+                0x00000000080360cc                tcp_attach
+                0x00000000080361e4                tcp_disconnect
+                0x00000000080362b0                tcp_usrclosed
+ .text          0x000000000803637c       0x40 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+                0x000000000803637c                tcpinit
+ .text          0x00000000080363bc      0xba0 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+                0x00000000080363bc                udp_lookup
+                0x0000000008036418                udp_soinput
+                0x00000000080365b8                udp_usrreq
+                0x00000000080367f0                udp4_sockbind
+                0x0000000008036ac0                udp4_socksend
+                0x0000000008036e34                udp4_sockaddr
+ .text          0x0000000008036f5c      0x158 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+                0x0000000008036f5c                alt_busy_sleep
+ .text          0x00000000080370b4      0x10c ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+                0x00000000080370f0                alt_close
+ .text          0x00000000080371c0       0x78 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+                0x00000000080371c0                alt_dcache_flush
+ .text          0x0000000008037238       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .text          0x0000000008037264       0xe0 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+                0x00000000080372a0                alt_dev_llist_insert
+ .text          0x0000000008037344       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+                0x0000000008037344                _do_ctors
+ .text          0x00000000080373a4       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+                0x00000000080373a4                _do_dtors
+ .text          0x0000000008037404        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .text          0x0000000008037404       0x90 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+                0x0000000008037404                alt_find_dev
+ .text          0x0000000008037494      0x1b0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+                0x0000000008037494                alt_ic_isr_register
+                0x00000000080374e4                alt_ic_irq_enable
+                0x000000000803756c                alt_ic_irq_disable
+                0x00000000080375f8                alt_ic_irq_enabled
+ .text          0x0000000008037644       0xe4 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+                0x0000000008037644                alt_iic_isr_register
+ .text          0x0000000008037728      0x12c ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+                0x00000000080377d8                alt_io_redirect
+ .text          0x0000000008037854        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .text          0x0000000008037854        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .text          0x0000000008037854        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .text          0x0000000008037854      0x248 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+                0x0000000008037948                open
+ .text          0x0000000008037a9c      0x22c ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+                0x0000000008037a9c                alt_printf
+ .text          0x0000000008037cc8       0x30 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+                0x0000000008037cc8                alt_putchar
+ .text          0x0000000008037cf8      0x138 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+                0x0000000008037d34                alt_read
+ .text          0x0000000008037e30       0x58 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+                0x0000000008037e30                alt_release_fd
+ .text          0x0000000008037e88       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+                0x0000000008037e88                alt_remap_cached
+ .text          0x0000000008037ebc      0x1a4 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+                0x0000000008037ebc                alt_alarm_stop
+                0x0000000008037f58                alt_tick
+ .text          0x0000000008038060       0x44 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+                0x0000000008038060                alt_uncached_free
+ .text          0x00000000080380a4       0x78 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+                0x00000000080380a4                alt_uncached_malloc
+ .text          0x000000000803811c      0x114 ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+                0x000000000803811c                usleep
+ .text          0x0000000008038230      0x134 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+                0x000000000803826c                alt_write
+ .text          0x0000000008038364       0x24 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+                0x0000000008038364                altera_nios2_gen2_irq_init
+ .text          0x0000000008038388       0xd0 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+                0x0000000008038388                OSCtxSw
+                0x0000000008038388                OSIntCtxSw
+                0x0000000008038414                OSStartHighRdy
+                0x0000000008038434                OSStartTsk
+ .text          0x0000000008038458      0x284 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+                0x0000000008038458                OSTaskStkInit
+                0x00000000080385a4                OSTaskCreateHook
+                0x00000000080385c8                OSTaskDelHook
+                0x00000000080385ec                OSTaskSwHook
+                0x000000000803860c                OSTaskStatHook
+                0x000000000803862c                OSTimeTickHook
+                0x0000000008038658                OSInitHookBegin
+                0x0000000008038678                OSInitHookEnd
+                0x0000000008038698                OSTaskIdleHook
+                0x00000000080386b8                OSTCBInitHook
+ .text          0x00000000080386dc      0x3d4 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                0x00000000080386dc                netmain_init
+                0x00000000080387c4                icmp_port_du
+                0x0000000008038850                station_state
+                0x00000000080389b0                sysuptime
+                0x00000000080389e8                packet_check
+                0x0000000008038a38                mcastlist
+                0x0000000008038a5c                prep_modules
+ .text          0x0000000008038ab0      0x388 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+                0x0000000008038ab0                inet_timer
+                0x0000000008038c74                in_timerset
+                0x0000000008038da0                in_timerkill
+ .text          0x0000000008038e38       0xa0 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+                0x0000000008038e38                create_apptasks
+                0x0000000008038e5c                task_stats
+ .text          0x0000000008038ed8       0xa0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+                0x0000000008038ed8                fcntl
+ .text          0x0000000008038f78     0x10f8 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+                0x0000000008038f78                icmprcv
+                0x0000000008039a54                icmp_destun
+                0x0000000008039d2c                icmp_timex
+                0x000000000803a01c                icmp_du
+ .text          0x000000000803a070     0x15f8 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                0x000000000803a070                ip_init
+                0x000000000803a148                ip_bldhead
+                0x000000000803a2d4                ip_write_internal
+                0x000000000803a9e8                ip_write
+                0x000000000803abf8                ip_write2
+                0x000000000803af6c                ip_raw_write
+                0x000000000803b028                ip_mymach
+                0x000000000803b0cc                ip_dump
+                0x000000000803b370                iproute
+                0x000000000803b53c                ip_copypkt
+ .text          0x000000000803b668      0xc44 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+                0x000000000803b668                ip_rcv
+                0x000000000803b9bc                ip_rcv_phase2
+                0x000000000803bf08                ip_demux
+ .text          0x000000000803c2ac      0x2bc ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+                0x000000000803c2ac                in_addmulti
+                0x000000000803c3f8                in_delmulti
+                0x000000000803c504                lookup_mcast
+ .text          0x000000000803c568       0xd4 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+                0x000000000803c568                prep_ifaces
+                0x000000000803c5e8                netexit
+                0x000000000803c610                evtmap_setup
+ .text          0x000000000803c63c      0x4ec ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+                0x000000000803c63c                ip_raw_open
+                0x000000000803c714                ip_raw_close
+                0x000000000803c7d0                ip_raw_input
+                0x000000000803c9e4                ip_raw_alloc
+                0x000000000803ca9c                ip_raw_free
+                0x000000000803cae0                ip_raw_maxalloc
+ .text          0x000000000803cb28      0x60c ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+                0x000000000803cb28                rt_lookup
+                0x000000000803cc7c                add_route
+                0x000000000803d020                del_route
+ .text          0x000000000803d134      0xcc8 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+                0x000000000803d134                udpdemux
+                0x000000000803d8a0                udp_send
+                0x000000000803db34                udpswap
+                0x000000000803dc28                udp_socket
+                0x000000000803dcd8                udp_alloc
+                0x000000000803dd94                udp_maxalloc
+                0x000000000803ddb8                udp_free
+ .text          0x000000000803ddfc      0x268 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+                0x000000000803ddfc                igmpv1_input
+ .text          0x000000000803e064      0x64c ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+                0x000000000803e064                igmpv2_input
+                0x000000000803e170                igmpv2_process_report
+                0x000000000803e284                igmpv2_process_query
+                0x000000000803e444                igmpv2_chk_set_timer
+                0x000000000803e574                igmpv2_chk4_rtr_alert_opt
+ .text          0x000000000803e6b0      0x848 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+                0x000000000803e6b0                IPADDR_TO_NETP
+                0x000000000803e7c4                ip_setmoptions
+                0x000000000803ed64                ip_getmoptions
+                0x000000000803ee74                ip_freemoptions
+ .text          0x000000000803eef8      0x6a0 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+                0x000000000803eef8                u_mctest_init
+                0x000000000803ef2c                u_mctest_run
+ .text          0x000000000803f598      0x3a4 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+                0x000000000803f598                init_memdev
+                0x000000000803f5e8                md_fopen
+                0x000000000803f610                md_fclose
+                0x000000000803f634                md_fread
+                0x000000000803f78c                md_fwrite
+                0x000000000803f804                md_fseek
+                0x000000000803f830                md_ftell
+                0x000000000803f854                md_fgetc
+                0x000000000803f918                md_unlink
+ .text          0x000000000803f93c      0x784 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+                0x000000000803f93c                parse_ipad
+                0x000000000803fc38                inet_addr
+                0x000000000803fc9c                hextoa
+                0x000000000803fce8                inet_pton
+                0x000000000803fd7c                inet_ntop
+                0x000000000803fe00                print46_addr
+                0x000000000803fe5c                inet46_addr
+                0x000000000803ff20                inet_setport
+                0x000000000803ff8c                convert_ip
+ .text          0x00000000080400c0      0x194 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+                0x00000000080400c0                tcp_cksum
+ .text          0x0000000008040254      0x2d8 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+                0x0000000008040254                udp_open
+                0x0000000008040454                udp_close
+ .text          0x000000000804052c      0x888 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+                0x000000000804052c                in_pcballoc
+                0x00000000080405b4                in_pcbdetach
+                0x000000000804060c                in_pcbbind
+                0x000000000804081c                in_pcbconnect
+                0x00000000080409fc                in_pcbdisconnect
+                0x0000000008040a58                in_setsockaddr
+                0x0000000008040adc                in_setpeeraddr
+                0x0000000008040b60                in_pcblookup
+ .text          0x0000000008040db4     0x18e0 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                0x0000000008040db4                set_vfopen_error
+                0x0000000008040de0                get_vfopen_error
+                0x0000000008040e00                vf_alloc_and_link_vop
+                0x0000000008040e70                vf_alloc_buffer
+                0x0000000008040f38                vf_free_buffer
+                0x0000000008040f88                vfopen_locked
+                0x00000000080412c0                vfopen
+                0x0000000008041310                vfclose_locked
+                0x00000000080414cc                vfclose
+                0x0000000008041510                vfflush
+                0x0000000008041558                vfgets
+                0x0000000008041628                vfeof
+                0x0000000008041678                vunlink_flag_open_files
+                0x00000000080416d4                vunlink
+                0x00000000080418d4                vfread
+                0x0000000008041a5c                vfwrite_locked
+                0x0000000008041e08                vfwrite
+                0x0000000008041e68                vfseek
+                0x0000000008041fbc                vftell
+                0x00000000080420c8                vgetc_locked
+                0x00000000080421c0                vgetc
+                0x0000000008042208                vfslookup_locked
+                0x000000000804232c                vfslookup
+                0x0000000008042374                strippath
+                0x0000000008042540                isvfile_locked
+                0x0000000008042598                isvfile
+                0x00000000080425e0                vferror
+                0x000000000804263c                vclearerr
+ .text          0x0000000008042694       0x24 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+                0x0000000008042694                prep_vfs
+ .text          0x00000000080426b8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .text          0x00000000080426b8      0x160 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+                0x00000000080426f4                alt_fcntl
+ .text          0x0000000008042818      0x108 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+                0x0000000008042818                alt_find_file
+ .text          0x0000000008042920       0xd8 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+                0x0000000008042920                alt_get_fd
+ .text          0x00000000080429f8       0x98 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+                0x00000000080429f8                alt_exception_cause_generated_bad_addr
+ .text          0x0000000008042a90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .text.atexit   0x0000000008042a90       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+                0x0000000008042a90                atexit
+ .text          0x0000000008042aa4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .text.atoi     0x0000000008042aa4        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+                0x0000000008042aa4                atoi
+ .text._atoi_r  0x0000000008042ab0        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+                0x0000000008042ab0                _atoi_r
+ .text          0x0000000008042abc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .text.exit     0x0000000008042abc       0x34 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+                0x0000000008042abc                exit
+ .text          0x0000000008042af0        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .text.memalign
+                0x0000000008042af0       0x14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+                0x0000000008042af0                memalign
+ .text          0x0000000008042b04        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .text._memalign_r
+                0x0000000008042b04      0x194 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+                0x0000000008042b04                _memalign_r
+ .text          0x0000000008042c98        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .text.malloc   0x0000000008042c98       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+                0x0000000008042c98                malloc
+ .text.free     0x0000000008042ca8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+                0x0000000008042ca8                free
+ .text          0x0000000008042cb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .text.memcmp   0x0000000008042cb8       0x8c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+                0x0000000008042cb8                memcmp
+ .text          0x0000000008042d44        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .text._sprintf_r
+                0x0000000008042d44       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+                0x0000000008042d44                _sprintf_r
+ .text.sprintf  0x0000000008042d98       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+                0x0000000008042d98                sprintf
+ .text          0x0000000008042dfc        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .text.strchr   0x0000000008042dfc      0x164 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+                0x0000000008042dfc                strchr
+ .text          0x0000000008042f60        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .text.strcpy   0x0000000008042f60       0x8c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+                0x0000000008042f60                strcpy
+ .text          0x0000000008042fec        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .text.strncmp  0x0000000008042fec       0xfc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+                0x0000000008042fec                strncmp
+ .text          0x00000000080430e8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .text._strtol_l.isra.0
+                0x00000000080430e8      0x224 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .text._strtol_r
+                0x000000000804330c        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+                0x000000000804330c                _strtol_r
+ .text.strtol_l
+                0x0000000008043310       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+                0x0000000008043310                strtol_l
+ .text.strtol   0x0000000008043328       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+                0x0000000008043328                strtol
+ .text          0x0000000008043340        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .text.___svfprintf_internal_r
+                0x0000000008043340     0x2118 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+                0x0000000008043340                ___svfprintf_internal_r
+ .text          0x0000000008045458        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .text.vprintf  0x0000000008045458       0x1c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+                0x0000000008045458                vprintf
+ .text._vprintf_r
+                0x0000000008045474       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+                0x0000000008045474                _vprintf_r
+ .text          0x0000000008045484        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .text._vsprintf_r
+                0x0000000008045484       0x4c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+                0x0000000008045484                _vsprintf_r
+ .text.vsprintf
+                0x00000000080454d0       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+                0x00000000080454d0                vsprintf
+ .text          0x00000000080454e8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .text.__register_exitproc
+                0x00000000080454e8       0x90 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+                0x00000000080454e8                __register_exitproc
+ .text          0x0000000008045578        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .text.__call_exitprocs
+                0x0000000008045578      0x118 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+                0x0000000008045578                __call_exitprocs
+ .text          0x0000000008045690        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .text.__ssprint_r
+                0x0000000008045690      0x1c0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+                0x0000000008045690                __ssprint_r
+ .text.___svfiprintf_internal_r
+                0x0000000008045850     0x1120 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+                0x0000000008045850                ___svfiprintf_internal_r
+ .text          0x0000000008046970        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .text._vfprintf_r
+                0x0000000008046970        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+                0x0000000008046970                _vfprintf_r
+ .text          0x0000000008046974       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+                0x0000000008046974                _exit
+ *(.gnu.warning.*)
+ *(.fini)
+                [!provide]                        PROVIDE (__etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_etext = ABSOLUTE (.))
+                [!provide]                        PROVIDE (etext = ABSOLUTE (.))
+ *(.eh_frame_hdr)
+                0x00000000080469a8                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (__preinit_array_start = ABSOLUTE (.))
+ *(.preinit_array)
+                [!provide]                        PROVIDE (__preinit_array_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__init_array_start = ABSOLUTE (.))
+ *(.init_array)
+                [!provide]                        PROVIDE (__init_array_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__fini_array_start = ABSOLUTE (.))
+ *(.fini_array)
+                [!provide]                        PROVIDE (__fini_array_end = ABSOLUTE (.))
+ *(.eh_frame)
+ *(.gcc_except_table .gcc_except_table.*)
+ *(.dynamic)
+                0x00000000080469a8                PROVIDE (__CTOR_LIST__ = ABSOLUTE (.))
+ *(.ctors)
+ *(SORT_BY_NAME(.ctors.*))
+                0x00000000080469a8                PROVIDE (__CTOR_END__ = ABSOLUTE (.))
+                0x00000000080469a8                PROVIDE (__DTOR_LIST__ = ABSOLUTE (.))
+ *(.dtors)
+ *(SORT_BY_NAME(.dtors.*))
+                0x00000000080469a8                PROVIDE (__DTOR_END__ = ABSOLUTE (.))
+ *(.jcr)
+                0x00000000080469a8                . = ALIGN (0x4)
+
+.rodata         0x00000000080469a8     0x4f6c
+                [!provide]                        PROVIDE (__ram_rodata_start = ABSOLUTE (.))
+                0x00000000080469a8                . = ALIGN (0x4)
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ .rodata        0x00000000080469a8      0x3ce obj/default/src/control.o
+ *fill*         0x0000000008046d76        0x2 
+ .rodata        0x0000000008046d78       0x1b obj/default/src/main.o
+ *fill*         0x0000000008046d93        0x1 
+ .rodata        0x0000000008046d94      0x284 obj/default/src/network_utilities.o
+ .rodata        0x0000000008047018       0x26 obj/default/src/sensor.o
+ *fill*         0x000000000804703e        0x2 
+ .rodata        0x0000000008047040      0x118 obj/default/src/socket_server.o
+ .rodata        0x0000000008047158       0x27 obj/default/src/tse_my_system.o
+ *fill*         0x000000000804717f        0x1 
+ .rodata        0x0000000008047180       0x22 obj/default/src/udpgen.o
+ *fill*         0x00000000080471a2        0x2 
+ .rodata        0x00000000080471a4       0x32 obj/default/src/utils.o
+ .rodata._ctype_
+                0x00000000080471d6      0x101 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+                0x00000000080471d6                _ctype_
+ .rodata._ctype_b
+                0x00000000080472d7      0x180 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+                0x00000000080472d7                _ctype_b
+ *fill*         0x0000000008047457        0x1 
+ .rodata._puts_r.str1.4
+                0x0000000008047458        0x2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ *fill*         0x000000000804745a        0x2 
+ .rodata.___vfprintf_internal_r.str1.4
+                0x000000000804745c       0x42 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .rodata.zeroes.5227
+                0x000000000804749e       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .rodata.blanks.5226
+                0x00000000080474ae       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ *fill*         0x00000000080474be        0x2 
+ .rodata._dtoa_r.str1.4
+                0x00000000080474c0        0xd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+                                         0x12 (size before relaxing)
+ *fill*         0x00000000080474cd        0x3 
+ .rodata.p05.4024
+                0x00000000080474d0        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .rodata.__mprec_tinytens
+                0x00000000080474dc       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x00000000080474dc                __mprec_tinytens
+ .rodata.__mprec_bigtens
+                0x0000000008047504       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x0000000008047504                __mprec_bigtens
+ .rodata.__mprec_tens
+                0x000000000804752c       0xc8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                0x000000000804752c                __mprec_tens
+ .rodata.___vfiprintf_internal_r.str1.4
+                0x00000000080475f4       0x2f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .rodata.zeroes.5204
+                0x00000000080475f4       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .rodata.blanks.5203
+                0x0000000008047604       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .rodata._setlocale_r.str1.4
+                0x0000000008047614        0xa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ *fill*         0x000000000804761e        0x2 
+ .rodata.str1.4
+                0x0000000008047620        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                                          0x5 (size before relaxing)
+ .rodata        0x0000000008047624      0x100 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+                0x0000000008047624                __clz_tab
+ .rodata        0x0000000008047724       0x10 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .rodata        0x0000000008047734      0x10e ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                0x0000000008047734                OSUnMapTbl
+ *fill*         0x0000000008047842        0x2 
+ .rodata        0x0000000008047844       0x8b ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ *fill*         0x00000000080478cf        0x1 
+ .rodata        0x00000000080478d0     0x1c66 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ *fill*         0x0000000008049536        0x2 
+ .rodata        0x0000000008049538      0x1ed ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ *fill*         0x0000000008049725        0x3 
+ .rodata        0x0000000008049728      0x385 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ *fill*         0x0000000008049aad        0x3 
+ .rodata        0x0000000008049ab0       0x41 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ *fill*         0x0000000008049af1        0x3 
+ .rodata        0x0000000008049af4       0xd7 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ *fill*         0x0000000008049bcb        0x1 
+ .rodata        0x0000000008049bcc       0xec ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .rodata        0x0000000008049cb8      0x54b ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ *fill*         0x000000000804a203        0x1 
+ .rodata        0x000000000804a204       0xb6 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ *fill*         0x000000000804a2ba        0x2 
+ .rodata        0x000000000804a2bc       0x34 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .rodata        0x000000000804a2f0      0x1a8 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .rodata        0x000000000804a498       0x56 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ *fill*         0x000000000804a4ee        0x2 
+ .rodata        0x000000000804a4f0      0x117 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ *fill*         0x000000000804a607        0x1 
+ .rodata        0x000000000804a608       0x2c ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .rodata        0x000000000804a634      0x26a ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ *fill*         0x000000000804a89e        0x2 
+ .rodata        0x000000000804a8a0       0x9f ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ *fill*         0x000000000804a93f        0x1 
+ .rodata        0x000000000804a940       0x90 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .rodata        0x000000000804a9d0        0x7 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ *fill*         0x000000000804a9d7        0x1 
+ .rodata        0x000000000804a9d8       0x4d ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ *fill*         0x000000000804aa25        0x3 
+ .rodata        0x000000000804aa28       0x3f ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ *fill*         0x000000000804aa67        0x1 
+ .rodata        0x000000000804aa68       0x1e ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ *fill*         0x000000000804aa86        0x2 
+ .rodata        0x000000000804aa88       0x3d ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ *fill*         0x000000000804aac5        0x3 
+ .rodata        0x000000000804aac8       0x23 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ *fill*         0x000000000804aaeb        0x1 
+ .rodata        0x000000000804aaec       0x2b ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ *fill*         0x000000000804ab17        0x1 
+ .rodata        0x000000000804ab18        0xa ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ *fill*         0x000000000804ab22        0x2 
+ .rodata        0x000000000804ab24      0x1d1 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ *fill*         0x000000000804acf5        0x3 
+ .rodata        0x000000000804acf8       0x32 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ *fill*         0x000000000804ad2a        0x2 
+ .rodata        0x000000000804ad2c      0x317 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ *fill*         0x000000000804b043        0x1 
+ .rodata        0x000000000804b044      0x1dc ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .rodata        0x000000000804b220      0x11d ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ *fill*         0x000000000804b33d        0x3 
+ .rodata        0x000000000804b340       0x31 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ *fill*         0x000000000804b371        0x3 
+ .rodata        0x000000000804b374       0x22 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ *fill*         0x000000000804b396        0x2 
+ .rodata        0x000000000804b398       0x35 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ *fill*         0x000000000804b3cd        0x3 
+ .rodata        0x000000000804b3d0       0xe8 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .rodata        0x000000000804b4b8      0x2ce ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ *fill*         0x000000000804b786        0x2 
+ .rodata        0x000000000804b788       0x93 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ *fill*         0x000000000804b81b        0x1 
+ .rodata        0x000000000804b81c       0x81 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ *fill*         0x000000000804b89d        0x3 
+ .rodata        0x000000000804b8a0       0x31 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .rodata.___svfprintf_internal_r.str1.4
+                0x000000000804b8d1       0x42 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .rodata.zeroes.5208
+                0x000000000804b8d1       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .rodata.blanks.5207
+                0x000000000804b8e1       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .rodata.___svfiprintf_internal_r.str1.4
+                0x000000000804b8f1       0x2f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .rodata.zeroes.5188
+                0x000000000804b8f1       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .rodata.blanks.5187
+                0x000000000804b901       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ *(.rodata1)
+                0x000000000804b920                . = ALIGN (0x4)
+ *fill*         0x000000000804b911        0x3 
+                [!provide]                        PROVIDE (__ram_rodata_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_rodata_start = LOADADDR (.rodata))
+
+.rwdata         0x000000000804b920     0x126c
+                [!provide]                        PROVIDE (__ram_rwdata_start = ABSOLUTE (.))
+                0x000000000804b920                . = ALIGN (0x4)
+ *(.got.plt)
+ *(.got)
+ *(.data1)
+ *(.data .data.* .gnu.linkonce.d.*)
+ .data          0x000000000804b920        0x0 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .data          0x000000000804b920       0x18 obj/default/src/control.o
+                0x000000000804b920                controltask
+ .data          0x000000000804b938        0x0 obj/default/src/main.o
+ .data          0x000000000804b938        0x0 obj/default/src/network_utilities.o
+ .data          0x000000000804b938        0x0 obj/default/src/sensor.o
+ .data          0x000000000804b938       0x18 obj/default/src/socket_server.o
+                0x000000000804b938                sslistenertask
+ .data          0x000000000804b950      0x130 obj/default/src/tse_my_system.o
+                0x000000000804b950                tse_mac_device
+ .data          0x000000000804ba80        0x0 obj/default/src/udpgen.o
+ .data          0x000000000804ba80        0x0 obj/default/src/utils.o
+ .data          0x000000000804ba80        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .data          0x000000000804ba80        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .data          0x000000000804ba80        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .data.impure_data
+                0x000000000804ba80      0x424 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .data          0x000000000804bea4        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .data.__malloc_av_
+                0x000000000804bea4      0x408 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804bea4                __malloc_av_
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .data          0x000000000804c2ac        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .data.__global_locale
+                0x000000000804c2ac      0x16c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                0x000000000804c2ac                __global_locale
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .data          0x000000000804c418        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .data          0x000000000804c418        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ *fill*         0x000000000804c418        0x8 
+ .data          0x000000000804c420      0x390 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .data          0x000000000804c7b0        0x0 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .data          0x000000000804c7b0       0x30 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                0x000000000804c7b0                nettasks
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .data          0x000000000804c7e0        0x0 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .data          0x000000000804c7e0       0x48 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                0x000000000804c7e0                tcp_protosw
+                0x000000000804c7f8                udp_protosw
+                0x000000000804c810                rawip_protosw
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .data          0x000000000804c828        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .data          0x000000000804c828        0xb ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+                0x000000000804c828                tcp_outflags
+ .data          0x000000000804c833        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .data          0x000000000804c833        0xd ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                0x000000000804c833                tcp_backoff
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .data          0x000000000804c840        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .data          0x000000000804c840       0xe8 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+                0x000000000804c840                alt_dev_null
+                0x000000000804c868                alt_fd_list
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .data          0x000000000804c928        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .data          0x000000000804c928       0x18 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                0x000000000804c928                icmpdu_types
+ .data          0x000000000804c940        0x0 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .data          0x000000000804c940        0x0 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .data          0x000000000804c940        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .data          0x000000000804c940       0x18 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .data          0x000000000804c958        0x0 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .data          0x000000000804c958        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .data          0x000000000804c958        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .data          0x000000000804c958        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .data          0x000000000804c958        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .data          0x000000000804c958        0x9 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+                0x000000000804c958                rtp_priority
+ .data          0x000000000804c961        0x0 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .data          0x000000000804c961        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .data          0x000000000804c961        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .data          0x000000000804c961        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .data          0x000000000804c961        0x0 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ *fill*         0x000000000804c961        0x3 
+ .data          0x000000000804c964       0xd4 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+                0x000000000804c964                mdio
+                0x000000000804c988                mdlist
+ .data          0x000000000804ca38        0x0 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .data          0x000000000804ca38        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .data          0x000000000804ca38        0x0 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .data          0x000000000804ca38        0x0 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .data          0x000000000804ca38       0x80 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                0x000000000804ca38                vfs_root_path
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .data          0x000000000804cab8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .data          0x000000000804cab8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+                0x0000000008054ab8                _gp = ABSOLUTE ((. + 0x8000))
+                [!provide]                        PROVIDE (gp = _gp)
+ *(.rwdata .rwdata.*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ .sdata._global_impure_ptr
+                0x000000000804cab8        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+                0x000000000804cab8                _global_impure_ptr
+ .sdata._impure_ptr
+                0x000000000804cabc        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+                0x000000000804cabc                _impure_ptr
+ .sdata.__malloc_sbrk_base
+                0x000000000804cac0        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cac0                __malloc_sbrk_base
+ .sdata.__malloc_trim_threshold
+                0x000000000804cac4        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cac4                __malloc_trim_threshold
+ .sdata         0x000000000804cac8        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+                0x000000000804cac8                alt_flash_dev_list
+ .sdata         0x000000000804cad0        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .sdata         0x000000000804cad4        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .sdata         0x000000000804cad8        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .sdata         0x000000000804cadc        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+                0x000000000804cadc                eth_tse_name
+ .sdata         0x000000000804cae0        0x1 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                0x000000000804cae0                max_mac_system
+ *fill*         0x000000000804cae1        0x3 
+ .sdata         0x000000000804cae4        0x8 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+                0x000000000804cae4                alt_msgdma_list
+ .sdata         0x000000000804caec        0x8 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+                0x000000000804caec                altera_onchip_flash_list
+ .sdata         0x000000000804caf4        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+                0x000000000804caf4                alt_iniche_dev_list
+ .sdata         0x000000000804cafc        0x4 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                0x000000000804cafc                arp_ageout
+ .sdata         0x000000000804cb00        0x4 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                0x000000000804cb00                ipmcfail_str
+ .sdata         0x000000000804cb04        0x4 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .sdata         0x000000000804cb08        0x4 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                0x000000000804cb08                num_net_tasks
+ .sdata         0x000000000804cb0c        0x4 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+                0x000000000804cb0c                pingdata
+ .sdata         0x000000000804cb10       0x10 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+                0x000000000804cb10                lilbufs
+                0x000000000804cb14                lilbufsiz
+                0x000000000804cb18                bigbufs
+                0x000000000804cb1c                bigbufsiz
+ .sdata         0x000000000804cb20        0x4 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+                0x000000000804cb20                kb_last
+ .sdata         0x000000000804cb24        0x4 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                0x000000000804cb24                TCPTV_MSL
+ .sdata         0x000000000804cb28        0x2 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+                0x000000000804cb28                socket_defaults
+ .sdata         0x000000000804cb2a        0x1 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                0x000000000804cb2a                tcprexmtthresh
+ *fill*         0x000000000804cb2b        0x1 
+ .sdata         0x000000000804cb2c        0x4 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+                0x000000000804cb2c                tcp_ttl
+ .sdata         0x000000000804cb30        0x8 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                0x000000000804cb30                tcp_keepidle
+                0x000000000804cb34                tcp_keepintvl
+ .sdata         0x000000000804cb38        0x8 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+                0x000000000804cb38                tcp_sendspace
+                0x000000000804cb3c                tcp_recvspace
+ .sdata         0x000000000804cb40       0x14 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+                0x000000000804cb40                alt_fs_list
+                0x000000000804cb48                alt_dev_list
+                0x000000000804cb50                alt_max_fd
+ .sdata         0x000000000804cb54        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+                0x000000000804cb54                alt_errno
+ .sdata         0x000000000804cb58        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+                0x000000000804cb58                alt_priority_mask
+ .sdata         0x000000000804cb5c        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+                0x000000000804cb5c                alt_alarm_list
+ .sdata         0x000000000804cb64       0x10 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                0x000000000804cb64                name
+                0x000000000804cb68                prompt
+                0x000000000804cb6c                pingdelay
+                0x000000000804cb70                deflength
+ .sdata         0x000000000804cb74        0x8 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                0x000000000804cb78                ipRoutes
+ .sdata         0x000000000804cb7c        0x4 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .sdata         0x000000000804cb80        0x4 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+                0x000000000804cb80                mdlist_size
+ .sdata         0x000000000804cb84        0x4 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+                0x000000000804cb84                pton_error
+ .sdata         0x000000000804cb88        0x4 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                0x000000000804cb88                http_root_path
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+                0x000000000804cb8c                . = ALIGN (0x4)
+                0x000000000804cb8c                _edata = ABSOLUTE (.)
+                [!provide]                        PROVIDE (edata = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__ram_rwdata_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (__flash_rwdata_start = LOADADDR (.rwdata))
+
+.bss            0x000000000804cb8c    0x11a10
+                0x000000000804cb8c                __bss_start = ABSOLUTE (.)
+                [!provide]                        PROVIDE (__sbss_start = ABSOLUTE (.))
+                [!provide]                        PROVIDE (___sbss_start = ABSOLUTE (.))
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ .sbss          0x000000000804cb8c       0x10 obj/default/src/control.o
+ .sbss          0x000000000804cb9c        0x1 obj/default/src/control.o
+                0x000000000804cb9c                to_controltask
+ *fill*         0x000000000804cb9d        0x3 
+ .sbss          0x000000000804cba0        0x8 obj/default/src/network_utilities.o
+                0x000000000804cba0                last_flash_sector_offset
+                0x000000000804cba4                last_flash_sector
+ .sbss          0x000000000804cba8        0x5 obj/default/src/socket_server.o
+                0x000000000804cbac                to_sslistenertask
+ *fill*         0x000000000804cbad        0x1 
+ .sbss          0x000000000804cbae        0x6 obj/default/src/utils.o
+                0x000000000804cbae                mastermode
+                0x000000000804cbb0                delays
+ .sbss.__malloc_max_total_mem
+                0x000000000804cbb4        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cbb4                __malloc_max_total_mem
+ .sbss.__malloc_max_sbrked_mem
+                0x000000000804cbb8        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cbb8                __malloc_max_sbrked_mem
+ .sbss.__malloc_top_pad
+                0x000000000804cbbc        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cbbc                __malloc_top_pad
+ .sbss          0x000000000804cbc0        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+                0x000000000804cbc0                errno
+ .sbss._PathLocale
+                0x000000000804cbc4        0x4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                0x000000000804cbc4                _PathLocale
+ .sbss          0x000000000804cbc8        0xc ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+                0x000000000804cbc8                alt_argc
+                0x000000000804cbcc                alt_argv
+                0x000000000804cbd0                alt_envp
+ .sbss          0x000000000804cbd4        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+                0x000000000804cbd8                alt_envsem
+ .sbss          0x000000000804cbdc        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+                0x000000000804cbe0                alt_heapsem
+ .sbss          0x000000000804cbe4       0x40 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                0x000000000804cbe4                OSLockNesting
+                0x000000000804cbe5                OSRunning
+                0x000000000804cbe8                OSIdleCtr
+                0x000000000804cbec                OSPrioHighRdy
+                0x000000000804cbed                OSPrioCur
+                0x000000000804cbf0                OSTCBList
+                0x000000000804cbf4                OSCtxSwCtr
+                0x000000000804cbf8                OSTCBFreeList
+                0x000000000804cbfc                OSTaskCtr
+                0x000000000804cc00                OSMemFreeList
+                0x000000000804cc04                OSTCBHighRdy
+                0x000000000804cc08                OSQFreeList
+                0x000000000804cc0c                OSRdyGrp
+                0x000000000804cc0d                OSRdyTbl
+                0x000000000804cc10                OSEventFreeList
+                0x000000000804cc14                OSIntNesting
+                0x000000000804cc18                OSTCBCur
+                0x000000000804cc1c                OSTime
+                0x000000000804cc20                OSFlagFreeList
+ .sbss          0x000000000804cc24        0x4 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                0x000000000804cc24                phy_profile_count
+                0x000000000804cc25                mac_group_count
+ .sbss          0x000000000804cc28        0x1 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+                0x000000000804cc28                number_of_tse_mac
+ *fill*         0x000000000804cc29        0x3 
+ .sbss          0x000000000804cc2c       0x1c ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                0x000000000804cc30                arpcache
+                0x000000000804cc38                arpReqsIn
+                0x000000000804cc3c                arpReqsOut
+                0x000000000804cc40                arpRepsIn
+                0x000000000804cc44                arpRepsOut
+ .sbss          0x000000000804cc48        0xc ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+                0x000000000804cc48                MaxLnh
+                0x000000000804cc4c                MaxMtu
+                0x000000000804cc50                NDEBUG
+ .sbss          0x000000000804cc54        0x8 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                0x000000000804cc54                ifNumber
+ .sbss          0x000000000804cc5c       0x10 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+                0x000000000804cc5c                igmp_timers_are_running
+                0x000000000804cc60                igmp_cticks
+                0x000000000804cc64                igmp_all_hosts_group
+                0x000000000804cc68                igmp_all_rtrs_group
+ .sbss          0x000000000804cc6c        0xe ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                0x000000000804cc6c                netmain_wakes
+                0x000000000804cc70                nettick_wakes
+                0x000000000804cc74                iniche_net_ready
+                0x000000000804cc78                to_netmain
+                0x000000000804cc79                to_nettick
+ *fill*         0x000000000804cc7a        0x2 
+ .sbss          0x000000000804cc7c        0x4 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+                0x000000000804cc7c                tcp_sleep_timeout
+ .sbss          0x000000000804cc80       0x18 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+                0x000000000804cc80                cticks_initialized
+                0x000000000804cc84                irq_level
+                0x000000000804cc90                cticks_factor
+                0x000000000804cc94                OS_TPS
+ .sbss          0x000000000804cc98       0x18 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+                0x000000000804cc98                tcp_sleep_count
+                0x000000000804cc9c                tcp_wakeup_count
+                0x000000000804cca0                netq_intmask
+                0x000000000804cca4                old_mode
+                0x000000000804cca8                global_TCPwakeup_setIndx
+                0x000000000804ccac                cticks
+ .sbss          0x000000000804ccb0        0xc ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+                0x000000000804ccb0                memtrapsize
+                0x000000000804ccb4                mheap_sem_ptr
+                0x000000000804ccb8                rcvdq_sem_ptr
+ .sbss          0x000000000804ccbc       0x12 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                0x000000000804ccbc                nextslow
+                0x000000000804ccc4                mbstat
+                0x000000000804cccc                select_wait
+ *fill*         0x000000000804ccce        0x2 
+ .sbss          0x000000000804ccd0        0x8 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                0x000000000804ccd0                tcpprintfs
+                0x000000000804ccd4                dropline
+ .sbss          0x000000000804ccd8        0x4 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+                0x000000000804ccd8                tcp_optionbuf
+ .sbss          0x000000000804ccdc        0x8 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                0x000000000804ccdc                tcp_maxidle
+                0x000000000804cce0                tcp_iss
+ .sbss          0x000000000804cce4        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+                0x000000000804cce4                alt_fd_list_lock
+ .sbss          0x000000000804cce8        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+                0x000000000804cce8                alt_irq_active
+ .sbss          0x000000000804ccec        0x8 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+                0x000000000804ccec                _alt_tick_rate
+                0x000000000804ccf0                _alt_nticks
+ .sbss          0x000000000804ccf4        0x8 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                0x000000000804ccf4                activehost
+ .sbss          0x000000000804ccfc        0xc ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+                0x000000000804ccfc                nextppp
+                0x000000000804cd00                port_1s_callout
+ .sbss          0x000000000804cd08        0x4 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+                0x000000000804cd08                icmpdu_hook
+ .sbss          0x000000000804cd0c        0x4 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                0x000000000804cd0c                rt_mib
+ .sbss          0x000000000804cd10       0x11 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+                0x000000000804cd10                port_prep
+                0x000000000804cd14                net_system_exit
+                0x000000000804cd18                so_evtmap_create
+                0x000000000804cd1c                so_evtmap_delete
+                0x000000000804cd20                so_evtmap
+ *fill*         0x000000000804cd21        0x3 
+ .sbss          0x000000000804cd24        0x4 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+                0x000000000804cd24                ipraw_eps
+ .sbss          0x000000000804cd28        0x4 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+                0x000000000804cd28                cachedRoute
+ .sbss          0x000000000804cd2c        0x2 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ *fill*         0x000000000804cd2e        0x2 
+ .sbss          0x000000000804cd30        0x4 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+                0x000000000804cd30                firstudp
+ .sbss          0x000000000804cd34        0x8 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+                0x000000000804cd34                inpcb_cachehits
+                0x000000000804cd38                inpcb_cachemiss
+ .sbss          0x000000000804cd3c       0x20 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                0x000000000804cd3c                vfsystems
+                0x000000000804cd40                vfiles
+                0x000000000804cd44                vfsfiles
+                0x000000000804cd48                vfopen_error
+                0x000000000804cd4c                vfs_dir_stale
+                0x000000000804cd50                vfs_open_files
+                0x000000000804cd54                vfs_total_rw_space
+                0x000000000804cd58                vfs_total_dyna_files
+ .sbss          0x000000000804cd5c        0x4 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+                0x000000000804cd5c                alt_instruction_exception_handler
+ *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+ *(.scommon)
+                [!provide]                        PROVIDE (__sbss_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (___sbss_end = ABSOLUTE (.))
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ .bss           0x000000000804cd60        0x0 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .bss           0x000000000804cd60       0x20 obj/default/src/control.o
+ .bss           0x000000000804cd80        0x0 obj/default/src/main.o
+ .bss           0x000000000804cd80        0x0 obj/default/src/network_utilities.o
+ .bss           0x000000000804cd80        0x0 obj/default/src/sensor.o
+ .bss           0x000000000804cd80       0x10 obj/default/src/socket_server.o
+ .bss           0x000000000804cd90        0x0 obj/default/src/tse_my_system.o
+ .bss           0x000000000804cd90        0x0 obj/default/src/udpgen.o
+ .bss           0x000000000804cd90        0x0 obj/default/src/utils.o
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .bss           0x000000000804cd90        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .bss.__malloc_current_mallinfo
+                0x000000000804cd90       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                0x000000000804cd90                __malloc_current_mallinfo
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .bss           0x000000000804cdb8        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .bss           0x000000000804cdb8        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .bss           0x000000000804cdb8       0x3c ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .bss           0x000000000804cdf4        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .bss           0x000000000804cdf4        0x0 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .bss           0x000000000804cdf4        0x0 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .bss           0x000000000804cdf4       0x18 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .bss           0x000000000804ce0c        0x0 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .bss           0x000000000804ce0c       0x1e ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .bss           0x000000000804ce2a        0x0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .bss           0x000000000804ce2a        0x0 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+ *(COMMON)
+ *fill*         0x000000000804ce2a        0x2 
+ COMMON         0x000000000804ce2c     0xe000 obj/default/src/main.o
+                0x000000000804ce2c                InitialTaskStk
+ COMMON         0x000000000805ae2c     0x279c ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                0x000000000805ae2c                OSFlagTbl
+                0x000000000805b19c                OSMemTbl
+                0x000000000805bdcc                OSQTbl
+                0x000000000805bfac                OSTaskIdleStk
+                0x000000000805c7ac                OSEventTbl
+                0x000000000805d2ec                OSTCBTbl
+                0x000000000805d574                OSTCBPrioTbl
+ COMMON         0x000000000805d5c8       0xe0 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+                0x000000000805d5c8                eth_tse_if
+ COMMON         0x000000000805d6a8       0x30 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                0x000000000805d6a8                pmac_groups
+                0x000000000805d6b8                pphy_profiles
+ COMMON         0x000000000805d6d8      0x2c0 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+                0x000000000805d6d8                tse_iniche_dev_driver_data
+                0x000000000805d708                tse
+ COMMON         0x000000000805d998      0x100 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                0x000000000805d998                arp_table
+ COMMON         0x000000000805da98       0x14 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+                0x000000000805da98                netlist
+ COMMON         0x000000000805daac       0x14 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+                0x000000000805daac                rcvdq
+ COMMON         0x000000000805dac0      0x310 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                0x000000000805dac0                netstatic
+                0x000000000805ddc0                nets
+ COMMON         0x000000000805ddd0       0x64 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+                0x000000000805ddd0                igmpstats
+ COMMON         0x000000000805de34       0x24 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+                0x000000000805de34                eth_prt_buf
+                0x000000000805de46                ipreturn
+ COMMON         0x000000000805de58      0x128 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+                0x000000000805de58                lilfreeq
+                0x000000000805de6c                memestats
+                0x000000000805de7c                pktlog
+                0x000000000805df6c                bigfreeq
+ COMMON         0x000000000805df80      0x1ec ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+                0x000000000805df80                global_tcb_ext
+                0x000000000805e07c                global_TCPwakeup_set
+ COMMON         0x000000000805e16c       0x58 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+                0x000000000805e16c                resid_semaphore
+                0x000000000805e1ac                app_semaphore
+ COMMON         0x000000000805e1c4       0x78 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                0x000000000805e1c4                soq
+                0x000000000805e1d8                tcpmib
+                0x000000000805e214                mbufq
+                0x000000000805e228                mfreeq
+ COMMON         0x000000000805e23c       0x28 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                0x000000000805e23c                tcp_saveti
+ COMMON         0x000000000805e264      0x10c ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+                0x000000000805e264                tcb
+                0x000000000805e290                tcpstat
+ COMMON         0x000000000805e370      0x100 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+                0x000000000805e370                alt_irq
+ COMMON         0x000000000805e470       0x64 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+                0x000000000805e470                intimers
+ COMMON         0x000000000805e4d4       0x68 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+                0x000000000805e4d4                icmp_mib
+ COMMON         0x000000000805e53c       0x50 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                0x000000000805e53c                ip_mib
+ COMMON         0x000000000805e58c       0x10 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+                0x000000000805e58c                udp_mib
+                0x000000000805e59c                . = ALIGN (0x4)
+                0x000000000805e59c                __bss_end = ABSOLUTE (.)
+
+.ddr3_ram       0x000000000805e59c        0x0
+                [!provide]                        PROVIDE (_alt_partition_ddr3_ram_start = ABSOLUTE (.))
+ *(.ddr3_ram .ddr3_ram. ddr3_ram.*)
+                0x000000000805e59c                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_ddr3_ram_end = ABSOLUTE (.))
+                0x000000000805e59c                _end = ABSOLUTE (.)
+                0x000000000805e59c                end = ABSOLUTE (.)
+                0x000000000805e59c                __alt_stack_base = ABSOLUTE (.)
+                [!provide]                        PROVIDE (_alt_partition_ddr3_ram_load_addr = LOADADDR (.ddr3_ram))
+
+.ext_flash_avl_mem
+                0x0000000014000020        0x0
+                [!provide]                        PROVIDE (_alt_partition_ext_flash_avl_mem_start = ABSOLUTE (.))
+ *(.ext_flash_avl_mem .ext_flash_avl_mem. ext_flash_avl_mem.*)
+                0x0000000014000020                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_ext_flash_avl_mem_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_alt_partition_ext_flash_avl_mem_load_addr = LOADADDR (.ext_flash_avl_mem))
+
+.onchip_flash_data
+                0x0000000018200000        0x0
+                [!provide]                        PROVIDE (_alt_partition_onchip_flash_data_start = ABSOLUTE (.))
+ *(.onchip_flash_data .onchip_flash_data. onchip_flash_data.*)
+                0x0000000018200000                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_onchip_flash_data_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_alt_partition_onchip_flash_data_load_addr = LOADADDR (.onchip_flash_data))
+
+.descriptor_memory
+                0x0000000018400000        0x0
+                [!provide]                        PROVIDE (_alt_partition_descriptor_memory_start = ABSOLUTE (.))
+ *(.descriptor_memory .descriptor_memory. descriptor_memory.*)
+                0x0000000018400000                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_descriptor_memory_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_alt_partition_descriptor_memory_load_addr = LOADADDR (.descriptor_memory))
+
+.calibration_ram
+                0x0000000018403400        0x0
+                [!provide]                        PROVIDE (_alt_partition_calibration_ram_start = ABSOLUTE (.))
+ *(.calibration_ram .calibration_ram. calibration_ram.*)
+                0x0000000018403400                . = ALIGN (0x4)
+                [!provide]                        PROVIDE (_alt_partition_calibration_ram_end = ABSOLUTE (.))
+                [!provide]                        PROVIDE (_alt_partition_calibration_ram_load_addr = LOADADDR (.calibration_ram))
+
+.stab
+ *(.stab)
+
+.stabstr
+ *(.stabstr)
+
+.stab.excl
+ *(.stab.excl)
+
+.stab.exclstr
+ *(.stab.exclstr)
+
+.stab.index
+ *(.stab.index)
+
+.stab.indexstr
+ *(.stab.indexstr)
+
+.comment        0x0000000000000000       0x2c
+ *(.comment)
+ .comment       0x0000000000000000       0x2c obj/default/src/control.o
+                                         0x2d (size before relaxing)
+ .comment       0x000000000000002c       0x2d obj/default/src/main.o
+ .comment       0x000000000000002c       0x2d obj/default/src/network_utilities.o
+ .comment       0x000000000000002c       0x2d obj/default/src/sensor.o
+ .comment       0x000000000000002c       0x2d obj/default/src/socket_server.o
+ .comment       0x000000000000002c       0x2d obj/default/src/tse_my_system.o
+ .comment       0x000000000000002c       0x2d obj/default/src/udpgen.o
+ .comment       0x000000000000002c       0x2d obj/default/src/utils.o
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .comment       0x000000000000002c       0x2d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .comment       0x000000000000002c       0x2d ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug
+ *(.debug)
+
+.line
+ *(.line)
+
+.debug_srcinfo
+ *(.debug_srcinfo)
+
+.debug_sfnames
+ *(.debug_sfnames)
+
+.debug_aranges  0x0000000000000000     0x1c78
+ *(.debug_aranges)
+ .debug_aranges
+                0x0000000000000000       0x28 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_aranges
+                0x0000000000000028       0x20 obj/default/src/control.o
+ .debug_aranges
+                0x0000000000000048       0x20 obj/default/src/main.o
+ .debug_aranges
+                0x0000000000000068       0x20 obj/default/src/network_utilities.o
+ .debug_aranges
+                0x0000000000000088       0x20 obj/default/src/sensor.o
+ .debug_aranges
+                0x00000000000000a8       0x20 obj/default/src/socket_server.o
+ .debug_aranges
+                0x00000000000000c8       0x18 obj/default/src/tse_my_system.o
+ .debug_aranges
+                0x00000000000000e0       0x20 obj/default/src/udpgen.o
+ .debug_aranges
+                0x0000000000000100       0x20 obj/default/src/utils.o
+ .debug_aranges
+                0x0000000000000120       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .debug_aranges
+                0x0000000000000138       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_aranges
+                0x0000000000000160       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .debug_aranges
+                0x0000000000000178       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_aranges
+                0x00000000000001a0       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_aranges
+                0x00000000000001c8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_aranges
+                0x00000000000001f0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_aranges
+                0x0000000000000210       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_aranges
+                0x0000000000000240       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_aranges
+                0x0000000000000260       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_aranges
+                0x0000000000000288       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_aranges
+                0x00000000000002b8       0x68 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_aranges
+                0x0000000000000320       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_aranges
+                0x0000000000000348       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_aranges
+                0x0000000000000368       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_aranges
+                0x0000000000000390       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_aranges
+                0x00000000000003b8       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_aranges
+                0x00000000000003e8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_aranges
+                0x0000000000000410       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_aranges
+                0x0000000000000430       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_aranges
+                0x0000000000000450       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_aranges
+                0x0000000000000470       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_aranges
+                0x0000000000000490       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_aranges
+                0x00000000000004b0       0xb0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_aranges
+                0x0000000000000560       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_aranges
+                0x0000000000000588       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_aranges
+                0x00000000000005a8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_aranges
+                0x00000000000005d0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_aranges
+                0x00000000000005f0       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_aranges
+                0x0000000000000630       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_aranges
+                0x0000000000000670       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_aranges
+                0x0000000000000698       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_aranges
+                0x00000000000006b8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_aranges
+                0x00000000000006d8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_aranges
+                0x00000000000006f8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_aranges
+                0x0000000000000720       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_aranges
+                0x0000000000000750       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_aranges
+                0x0000000000000770       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .debug_aranges
+                0x0000000000000788       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_aranges
+                0x00000000000007a8       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_aranges
+                0x00000000000007d8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_aranges
+                0x00000000000007f8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_aranges
+                0x0000000000000820       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_aranges
+                0x0000000000000840       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_aranges
+                0x0000000000000868       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_aranges
+                0x0000000000000888       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_aranges
+                0x00000000000008b0       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_aranges
+                0x00000000000008d8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_aranges
+                0x00000000000008f8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_aranges
+                0x0000000000000918       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_aranges
+                0x0000000000000938       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_aranges
+                0x0000000000000958       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_aranges
+                0x0000000000000978       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_aranges
+                0x0000000000000998       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_aranges
+                0x00000000000009b8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_aranges
+                0x00000000000009d8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_aranges
+                0x00000000000009f8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_aranges
+                0x0000000000000a18       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_aranges
+                0x0000000000000a38       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_aranges
+                0x0000000000000a58       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_aranges
+                0x0000000000000a78       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_aranges
+                0x0000000000000a98       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .debug_aranges
+                0x0000000000000ab0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_aranges
+                0x0000000000000ad0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .debug_aranges
+                0x0000000000000af0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .debug_aranges
+                0x0000000000000b10       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .debug_aranges
+                0x0000000000000b30       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .debug_aranges
+                0x0000000000000b50       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .debug_aranges
+                0x0000000000000b70       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .debug_aranges
+                0x0000000000000b90       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .debug_aranges
+                0x0000000000000bb0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .debug_aranges
+                0x0000000000000bd0       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .debug_aranges
+                0x0000000000000bf0       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .debug_aranges
+                0x0000000000000c10       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .debug_aranges
+                0x0000000000000c30       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .debug_aranges
+                0x0000000000000c50       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .debug_aranges
+                0x0000000000000c70       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .debug_aranges
+                0x0000000000000c90       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .debug_aranges
+                0x0000000000000cb0       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .debug_aranges
+                0x0000000000000cd0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .debug_aranges
+                0x0000000000000cf0       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .debug_aranges
+                0x0000000000000d10       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .debug_aranges
+                0x0000000000000d30       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .debug_aranges
+                0x0000000000000d50       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .debug_aranges
+                0x0000000000000d70       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .debug_aranges
+                0x0000000000000d90       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .debug_aranges
+                0x0000000000000db0       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_aranges
+                0x0000000000000dd0       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .debug_aranges
+                0x0000000000000df0       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .debug_aranges
+                0x0000000000000e10       0x20 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .debug_aranges
+                0x0000000000000e30       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .debug_aranges
+                0x0000000000000e50       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .debug_aranges
+                0x0000000000000e70       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .debug_aranges
+                0x0000000000000e90       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .debug_aranges
+                0x0000000000000eb0       0x20 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .debug_aranges
+                0x0000000000000ed0       0x20 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .debug_aranges
+                0x0000000000000ef0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .debug_aranges
+                0x0000000000000f10       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .debug_aranges
+                0x0000000000000f30       0x20 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .debug_aranges
+                0x0000000000000f50       0x20 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .debug_aranges
+                0x0000000000000f70       0x20 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .debug_aranges
+                0x0000000000000f90       0x20 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .debug_aranges
+                0x0000000000000fb0       0x20 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .debug_aranges
+                0x0000000000000fd0       0x20 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .debug_aranges
+                0x0000000000000ff0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .debug_aranges
+                0x0000000000001010       0x20 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_aranges
+                0x0000000000001030       0x20 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .debug_aranges
+                0x0000000000001050       0x20 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .debug_aranges
+                0x0000000000001070       0x20 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .debug_aranges
+                0x0000000000001090       0x20 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .debug_aranges
+                0x00000000000010b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .debug_aranges
+                0x00000000000010d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_aranges
+                0x00000000000010f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .debug_aranges
+                0x0000000000001110       0x20 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .debug_aranges
+                0x0000000000001130       0x20 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .debug_aranges
+                0x0000000000001150       0x20 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .debug_aranges
+                0x0000000000001170       0x20 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .debug_aranges
+                0x0000000000001190       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_aranges
+                0x00000000000011b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_aranges
+                0x00000000000011d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .debug_aranges
+                0x00000000000011f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .debug_aranges
+                0x0000000000001210       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .debug_aranges
+                0x0000000000001230       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .debug_aranges
+                0x0000000000001250       0x20 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .debug_aranges
+                0x0000000000001270       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .debug_aranges
+                0x0000000000001290       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .debug_aranges
+                0x00000000000012b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .debug_aranges
+                0x00000000000012d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .debug_aranges
+                0x00000000000012f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .debug_aranges
+                0x0000000000001310       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .debug_aranges
+                0x0000000000001330       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .debug_aranges
+                0x0000000000001350       0x18 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .debug_aranges
+                0x0000000000001368       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .debug_aranges
+                0x0000000000001388       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .debug_aranges
+                0x00000000000013a8       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .debug_aranges
+                0x00000000000013c8       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .debug_aranges
+                0x00000000000013e8       0x30 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .debug_aranges
+                0x0000000000001418       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_aranges
+                0x0000000000001438       0x18 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .debug_aranges
+                0x0000000000001450       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .debug_aranges
+                0x0000000000001470       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .debug_aranges
+                0x0000000000001490       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .debug_aranges
+                0x00000000000014b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .debug_aranges
+                0x00000000000014d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .debug_aranges
+                0x00000000000014f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .debug_aranges
+                0x0000000000001510       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .debug_aranges
+                0x0000000000001530       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .debug_aranges
+                0x0000000000001550       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .debug_aranges
+                0x0000000000001570       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .debug_aranges
+                0x0000000000001590       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .debug_aranges
+                0x00000000000015b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_aranges
+                0x00000000000015d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .debug_aranges
+                0x00000000000015f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .debug_aranges
+                0x0000000000001610       0x20 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .debug_aranges
+                0x0000000000001630       0x20 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .debug_aranges
+                0x0000000000001650       0x20 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .debug_aranges
+                0x0000000000001670       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .debug_aranges
+                0x0000000000001690       0x20 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .debug_aranges
+                0x00000000000016b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .debug_aranges
+                0x00000000000016d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_aranges
+                0x00000000000016f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .debug_aranges
+                0x0000000000001710       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .debug_aranges
+                0x0000000000001730       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .debug_aranges
+                0x0000000000001750       0x20 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .debug_aranges
+                0x0000000000001770       0x20 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_aranges
+                0x0000000000001790       0x20 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .debug_aranges
+                0x00000000000017b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .debug_aranges
+                0x00000000000017d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .debug_aranges
+                0x00000000000017f0       0x20 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .debug_aranges
+                0x0000000000001810       0x20 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .debug_aranges
+                0x0000000000001830       0x20 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .debug_aranges
+                0x0000000000001850       0x20 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .debug_aranges
+                0x0000000000001870       0x20 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .debug_aranges
+                0x0000000000001890       0x20 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .debug_aranges
+                0x00000000000018b0       0x20 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .debug_aranges
+                0x00000000000018d0       0x20 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .debug_aranges
+                0x00000000000018f0       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .debug_aranges
+                0x0000000000001928       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .debug_aranges
+                0x0000000000001948       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .debug_aranges
+                0x0000000000001968       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .debug_aranges
+                0x0000000000001988       0x28 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_aranges
+                0x00000000000019b0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_aranges
+                0x00000000000019d0       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_aranges
+                0x00000000000019f8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_aranges
+                0x0000000000001a18       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_aranges
+                0x0000000000001a38       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_aranges
+                0x0000000000001a58       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_aranges
+                0x0000000000001a80       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_aranges
+                0x0000000000001aa0       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_aranges
+                0x0000000000001ac8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_aranges
+                0x0000000000001ae8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_aranges
+                0x0000000000001b08       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_aranges
+                0x0000000000001b28       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_aranges
+                0x0000000000001b60       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_aranges
+                0x0000000000001b80       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_aranges
+                0x0000000000001ba8       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_aranges
+                0x0000000000001bd0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_aranges
+                0x0000000000001bf0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_aranges
+                0x0000000000001c10       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_aranges
+                0x0000000000001c38       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .debug_aranges
+                0x0000000000001c58       0x20 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug_pubnames
+ *(.debug_pubnames)
+
+.debug_info     0x0000000000000000   0x10e51e
+ *(.debug_info .gnu.linkonce.wi.*)
+ .debug_info    0x0000000000000000       0x22 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_info    0x0000000000000022     0x2983 obj/default/src/control.o
+ .debug_info    0x00000000000029a5     0x2357 obj/default/src/main.o
+ .debug_info    0x0000000000004cfc     0x26c5 obj/default/src/network_utilities.o
+ .debug_info    0x00000000000073c1     0x232d obj/default/src/sensor.o
+ .debug_info    0x00000000000096ee     0x2b66 obj/default/src/socket_server.o
+ .debug_info    0x000000000000c254     0x1993 obj/default/src/tse_my_system.o
+ .debug_info    0x000000000000dbe7     0x23a7 obj/default/src/udpgen.o
+ .debug_info    0x000000000000ff8e     0x2538 obj/default/src/utils.o
+ .debug_info    0x00000000000124c6      0xeb4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .debug_info    0x000000000001337a      0xb8b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_info    0x0000000000013f05      0x933 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .debug_info    0x0000000000014838      0xc44 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_info    0x000000000001547c      0xbbf c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_info    0x000000000001603b      0xcea c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_info    0x0000000000016d25      0x97c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_info    0x00000000000176a1     0x2051 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_info    0x00000000000196f2      0xbfc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_info    0x000000000001a2ee     0x1a04 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_info    0x000000000001bcf2      0xd7e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_info    0x000000000001ca70     0x10c3 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_info    0x000000000001db33      0xda3 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_info    0x000000000001e8d6      0xeee c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_info    0x000000000001f7c4      0xcad c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_info    0x0000000000020471      0xc54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_info    0x00000000000210c5      0xf46 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_info    0x000000000002200b      0xf87 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_info    0x0000000000022f92      0xf22 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_info    0x0000000000023eb4      0x9ec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_info    0x00000000000248a0      0xf44 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_info    0x00000000000257e4      0xf3a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_info    0x000000000002671e      0xf2a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_info    0x0000000000027648     0x205d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_info    0x00000000000296a5      0xc71 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_info    0x000000000002a316      0xf4c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_info    0x000000000002b262      0xc1b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_info    0x000000000002be7d      0xa03 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_info    0x000000000002c880      0xe6a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_info    0x000000000002d6ea     0x1f7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_info    0x000000000002f666      0xc99 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_info    0x00000000000302ff      0xa35 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_info    0x0000000000030d34      0x9e0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_info    0x0000000000031714      0xc36 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_info    0x000000000003234a      0xcde c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_info    0x0000000000033028      0xdec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_info    0x0000000000033e14      0xc2c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_info    0x0000000000034a40      0x929 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .debug_info    0x0000000000035369      0x9e0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_info    0x0000000000035d49     0x10c4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_info    0x0000000000036e0d      0xa16 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_info    0x0000000000037823     0x103e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_info    0x0000000000038861      0xa2e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_info    0x000000000003928f      0xcdd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_info    0x0000000000039f6c      0x980 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_info    0x000000000003a8ec     0x10ac c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_info    0x000000000003b998      0xffa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_info    0x000000000003c992      0x91e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_info    0x000000000003d2b0      0x98e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_info    0x000000000003dc3e      0x368 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_info    0x000000000003dfa6      0x641 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_info    0x000000000003e5e7      0x824 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_info    0x000000000003ee0b      0x29f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_info    0x000000000003f0aa      0x2a7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_info    0x000000000003f351      0x2a7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_info    0x000000000003f5f8      0x858 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_info    0x000000000003fe50      0x641 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_info    0x0000000000040491      0x277 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_info    0x0000000000040708      0x222 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_info    0x000000000004092a      0x2e4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_info    0x0000000000040c0e      0x2d7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_info    0x0000000000040ee5      0x179 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .debug_info    0x000000000004105e      0x1ea c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_info    0x0000000000041248     0x15cc ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .debug_info    0x0000000000042814     0x1559 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .debug_info    0x0000000000043d6d     0x155c ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .debug_info    0x00000000000452c9     0x13b7 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .debug_info    0x0000000000046680     0x15e9 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .debug_info    0x0000000000047c69      0xa72 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .debug_info    0x00000000000486db     0x1194 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .debug_info    0x000000000004986f     0x12cd ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .debug_info    0x000000000004ab3c     0x1d83 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .debug_info    0x000000000004c8bf     0x1bee ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .debug_info    0x000000000004e4ad     0x1545 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .debug_info    0x000000000004f9f2     0x172a ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .debug_info    0x000000000005111c     0x19ba ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .debug_info    0x0000000000052ad6     0x16a5 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .debug_info    0x000000000005417b     0x1bff ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .debug_info    0x0000000000055d7a     0x1342 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .debug_info    0x00000000000570bc     0x2b6c ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .debug_info    0x0000000000059c28      0xb12 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .debug_info    0x000000000005a73a     0x3896 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .debug_info    0x000000000005dfd0     0x1445 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .debug_info    0x000000000005f415     0x14ce ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .debug_info    0x00000000000608e3     0x1444 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .debug_info    0x0000000000061d27     0x1444 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .debug_info    0x000000000006316b     0x1221 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_info    0x000000000006438c     0x2b11 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .debug_info    0x0000000000066e9d     0x12ae ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .debug_info    0x000000000006814b     0x37bd ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .debug_info    0x000000000006b908     0x1fc1 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .debug_info    0x000000000006d8c9     0x20df ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .debug_info    0x000000000006f9a8     0x1feb ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .debug_info    0x0000000000071993     0x1ff2 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .debug_info    0x0000000000073985     0x245c ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .debug_info    0x0000000000075de1     0x2244 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .debug_info    0x0000000000078025     0x1ecb ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .debug_info    0x0000000000079ef0     0x21de ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .debug_info    0x000000000007c0ce     0x266b ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .debug_info    0x000000000007e739     0x2604 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .debug_info    0x0000000000080d3d     0x123a ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .debug_info    0x0000000000081f77     0x2524 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .debug_info    0x000000000008449b     0x23b5 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .debug_info    0x0000000000086850     0x24f3 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .debug_info    0x0000000000088d43     0x1fcc ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .debug_info    0x000000000008ad0f     0x1e55 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_info    0x000000000008cb64     0x12cb ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .debug_info    0x000000000008de2f       0x26 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .debug_info    0x000000000008de55     0x1355 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .debug_info    0x000000000008f1aa     0x259b ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .debug_info    0x0000000000091745     0x2c0e ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .debug_info    0x0000000000094353     0x3247 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_info    0x000000000009759a     0x22ef ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .debug_info    0x0000000000099889     0x31a8 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .debug_info    0x000000000009ca31     0x2df5 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .debug_info    0x000000000009f826     0x2654 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .debug_info    0x00000000000a1e7a     0x247f ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .debug_info    0x00000000000a42f9     0x2d94 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_info    0x00000000000a708d     0x2a64 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_info    0x00000000000a9af1     0x2b91 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .debug_info    0x00000000000ac682     0x291c ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .debug_info    0x00000000000aef9e     0x2994 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .debug_info    0x00000000000b1932     0x20f0 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .debug_info    0x00000000000b3a22     0x2510 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .debug_info    0x00000000000b5f32      0x96f ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .debug_info    0x00000000000b68a1     0x1382 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .debug_info    0x00000000000b7c23      0x978 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .debug_info    0x00000000000b859b     0x15c3 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .debug_info    0x00000000000b9b5e      0xa6b ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .debug_info    0x00000000000ba5c9       0x88 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .debug_info    0x00000000000ba651       0x88 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .debug_info    0x00000000000ba6d9      0x96f ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .debug_info    0x00000000000bb048     0x1301 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .debug_info    0x00000000000bc349      0xc18 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .debug_info    0x00000000000bcf61      0xabe ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .debug_info    0x00000000000bda1f     0x15c3 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .debug_info    0x00000000000befe2       0x22 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .debug_info    0x00000000000bf004     0x11ac ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_info    0x00000000000c01b0       0x8b ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .debug_info    0x00000000000c023b     0x13b5 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .debug_info    0x00000000000c15f0      0x125 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .debug_info    0x00000000000c1715      0x937 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .debug_info    0x00000000000c204c     0x15d2 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .debug_info    0x00000000000c361e     0x12cf ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .debug_info    0x00000000000c48ed      0x96b ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .debug_info    0x00000000000c5258     0x1287 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .debug_info    0x00000000000c64df      0x958 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .debug_info    0x00000000000c6e37      0x99a ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .debug_info    0x00000000000c77d1     0x115d ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .debug_info    0x00000000000c892e     0x15d9 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .debug_info    0x00000000000c9f07      0x952 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_info    0x00000000000ca859       0x26 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .debug_info    0x00000000000ca87f     0x1218 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .debug_info    0x00000000000cba97     0x249a ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .debug_info    0x00000000000cdf31     0x1ea6 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .debug_info    0x00000000000cfdd7     0x2310 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .debug_info    0x00000000000d20e7     0x200e ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .debug_info    0x00000000000d40f5     0x224d ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .debug_info    0x00000000000d6342     0x23c3 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .debug_info    0x00000000000d8705     0x2173 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_info    0x00000000000da878     0x1d47 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .debug_info    0x00000000000dc5bf     0x1cd7 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .debug_info    0x00000000000de296     0x1ed6 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .debug_info    0x00000000000e016c     0x1df9 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .debug_info    0x00000000000e1f65     0x2655 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_info    0x00000000000e45ba     0x23c7 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .debug_info    0x00000000000e6981     0x2560 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .debug_info    0x00000000000e8ee1     0x22eb ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .debug_info    0x00000000000eb1cc     0x226f ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .debug_info    0x00000000000ed43b     0x16c2 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .debug_info    0x00000000000eeafd     0x20c5 ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .debug_info    0x00000000000f0bc2     0x2158 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .debug_info    0x00000000000f2d1a     0x1dfd ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .debug_info    0x00000000000f4b17     0x2484 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .debug_info    0x00000000000f6f9b     0x1f13 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .debug_info    0x00000000000f8eae     0x145b ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .debug_info    0x00000000000fa309       0x22 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .debug_info    0x00000000000fa32b     0x15e5 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .debug_info    0x00000000000fb910     0x12f2 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .debug_info    0x00000000000fcc02     0x1364 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .debug_info    0x00000000000fdf66      0x1f1 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_info    0x00000000000fe157      0x99e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_info    0x00000000000feaf5      0x9e2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_info    0x00000000000ff4d7      0x9d9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_info    0x00000000000ffeb0      0x992 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_info    0x0000000000100842      0xcd3 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_info    0x0000000000101515      0x9bf c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_info    0x0000000000101ed4      0x9cb c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_info    0x000000000010289f      0xcc0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_info    0x000000000010355f      0x9c2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_info    0x0000000000103f21      0x9b7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_info    0x00000000001048d8      0x99e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_info    0x0000000000105276     0x11f7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_info    0x000000000010646d     0x1e67 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_info    0x00000000001082d4      0xc19 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_info    0x0000000000108eed      0xc7e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_info    0x0000000000109b6b      0x9d8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_info    0x000000000010a543      0xa14 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_info    0x000000000010af57     0x18ce c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_info    0x000000000010c825      0xbdd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .debug_info    0x000000000010d402     0x111c ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug_abbrev   0x0000000000000000    0x21537
+ *(.debug_abbrev)
+ .debug_abbrev  0x0000000000000000       0x12 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_abbrev  0x0000000000000012      0x376 obj/default/src/control.o
+ .debug_abbrev  0x0000000000000388      0x285 obj/default/src/main.o
+ .debug_abbrev  0x000000000000060d      0x375 obj/default/src/network_utilities.o
+ .debug_abbrev  0x0000000000000982      0x270 obj/default/src/sensor.o
+ .debug_abbrev  0x0000000000000bf2      0x37c obj/default/src/socket_server.o
+ .debug_abbrev  0x0000000000000f6e      0x1ea obj/default/src/tse_my_system.o
+ .debug_abbrev  0x0000000000001158      0x295 obj/default/src/udpgen.o
+ .debug_abbrev  0x00000000000013ed      0x2d1 obj/default/src/utils.o
+ .debug_abbrev  0x00000000000016be      0x1d6 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .debug_abbrev  0x0000000000001894      0x28a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_abbrev  0x0000000000001b1e      0x1c9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .debug_abbrev  0x0000000000001ce7      0x29d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_abbrev  0x0000000000001f84      0x25e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_abbrev  0x00000000000021e2      0x2ba c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_abbrev  0x000000000000249c      0x1f9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_abbrev  0x0000000000002695      0x464 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_abbrev  0x0000000000002af9      0x294 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_abbrev  0x0000000000002d8d      0x342 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_abbrev  0x00000000000030cf      0x322 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_abbrev  0x00000000000033f1      0x457 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_abbrev  0x0000000000003848      0x2c9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_abbrev  0x0000000000003b11      0x2cd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_abbrev  0x0000000000003dde      0x25f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_abbrev  0x000000000000403d      0x2ae c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_abbrev  0x00000000000042eb      0x288 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_abbrev  0x0000000000004573      0x349 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_abbrev  0x00000000000048bc      0x321 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_abbrev  0x0000000000004bdd      0x226 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_abbrev  0x0000000000004e03      0x223 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_abbrev  0x0000000000005026      0x21c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_abbrev  0x0000000000005242      0x228 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_abbrev  0x000000000000546a      0x48a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_abbrev  0x00000000000058f4      0x29e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_abbrev  0x0000000000005b92      0x28d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_abbrev  0x0000000000005e1f      0x2a0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_abbrev  0x00000000000060bf      0x261 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_abbrev  0x0000000000006320      0x2be c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_abbrev  0x00000000000065de      0x48a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_abbrev  0x0000000000006a68      0x2d4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_abbrev  0x0000000000006d3c      0x23b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_abbrev  0x0000000000006f77      0x236 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_abbrev  0x00000000000071ad      0x286 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_abbrev  0x0000000000007433      0x338 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_abbrev  0x000000000000776b      0x34a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_abbrev  0x0000000000007ab5      0x24a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_abbrev  0x0000000000007cff      0x1d5 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .debug_abbrev  0x0000000000007ed4      0x236 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_abbrev  0x000000000000810a      0x2ec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_abbrev  0x00000000000083f6      0x24a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_abbrev  0x0000000000008640      0x292 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_abbrev  0x00000000000088d2      0x236 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_abbrev  0x0000000000008b08      0x2d4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_abbrev  0x0000000000008ddc      0x1f9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_abbrev  0x0000000000008fd5      0x264 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_abbrev  0x0000000000009239      0x27a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_abbrev  0x00000000000094b3      0x1cb c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_abbrev  0x000000000000967e      0x1f7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_abbrev  0x0000000000009875      0x103 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_abbrev  0x0000000000009978      0x1a8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_abbrev  0x0000000000009b20      0x199 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_abbrev  0x0000000000009cb9      0x17b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_abbrev  0x0000000000009e34      0x18e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_abbrev  0x0000000000009fc2      0x18e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_abbrev  0x000000000000a150      0x1a0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_abbrev  0x000000000000a2f0      0x1a8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_abbrev  0x000000000000a498      0x17b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_abbrev  0x000000000000a613      0x17f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_abbrev  0x000000000000a792      0x18a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_abbrev  0x000000000000a91c      0x18a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_abbrev  0x000000000000aaa6       0xa8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .debug_abbrev  0x000000000000ab4e       0xf7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_abbrev  0x000000000000ac45      0x25e ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .debug_abbrev  0x000000000000aea3      0x24f ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .debug_abbrev  0x000000000000b0f2      0x24f ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .debug_abbrev  0x000000000000b341      0x24f ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .debug_abbrev  0x000000000000b590      0x266 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .debug_abbrev  0x000000000000b7f6      0x28e ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .debug_abbrev  0x000000000000ba84      0x257 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .debug_abbrev  0x000000000000bcdb      0x2c0 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .debug_abbrev  0x000000000000bf9b      0x465 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .debug_abbrev  0x000000000000c400      0x3b0 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .debug_abbrev  0x000000000000c7b0      0x37a ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .debug_abbrev  0x000000000000cb2a      0x3a7 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .debug_abbrev  0x000000000000ced1      0x39e ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .debug_abbrev  0x000000000000d26f      0x3ba ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .debug_abbrev  0x000000000000d629      0x36f ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .debug_abbrev  0x000000000000d998      0x35c ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .debug_abbrev  0x000000000000dcf4      0x32d ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .debug_abbrev  0x000000000000e021      0x2d3 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .debug_abbrev  0x000000000000e2f4      0x39a ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .debug_abbrev  0x000000000000e68e      0x248 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .debug_abbrev  0x000000000000e8d6      0x332 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .debug_abbrev  0x000000000000ec08      0x305 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .debug_abbrev  0x000000000000ef0d      0x305 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .debug_abbrev  0x000000000000f212      0x2f2 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_abbrev  0x000000000000f504      0x49c ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .debug_abbrev  0x000000000000f9a0      0x2f1 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .debug_abbrev  0x000000000000fc91      0x450 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .debug_abbrev  0x00000000000100e1      0x24a ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .debug_abbrev  0x000000000001032b      0x27b ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .debug_abbrev  0x00000000000105a6      0x24a ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .debug_abbrev  0x00000000000107f0      0x24f ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .debug_abbrev  0x0000000000010a3f      0x35c ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .debug_abbrev  0x0000000000010d9b      0x2e4 ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .debug_abbrev  0x000000000001107f      0x320 ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .debug_abbrev  0x000000000001139f      0x30e ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .debug_abbrev  0x00000000000116ad      0x355 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .debug_abbrev  0x0000000000011a02      0x341 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .debug_abbrev  0x0000000000011d43      0x25b ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .debug_abbrev  0x0000000000011f9e      0x374 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .debug_abbrev  0x0000000000012312      0x2ae ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .debug_abbrev  0x00000000000125c0      0x2c3 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .debug_abbrev  0x0000000000012883      0x277 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .debug_abbrev  0x0000000000012afa      0x312 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_abbrev  0x0000000000012e0c      0x262 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .debug_abbrev  0x000000000001306e       0x14 ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .debug_abbrev  0x0000000000013082      0x2ee ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .debug_abbrev  0x0000000000013370      0x308 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .debug_abbrev  0x0000000000013678      0x34a ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .debug_abbrev  0x00000000000139c2      0x3b3 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_abbrev  0x0000000000013d75      0x2a4 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .debug_abbrev  0x0000000000014019      0x34a ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .debug_abbrev  0x0000000000014363      0x398 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .debug_abbrev  0x00000000000146fb      0x3a9 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .debug_abbrev  0x0000000000014aa4      0x331 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .debug_abbrev  0x0000000000014dd5      0x38c ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_abbrev  0x0000000000015161      0x352 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_abbrev  0x00000000000154b3      0x376 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .debug_abbrev  0x0000000000015829      0x342 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .debug_abbrev  0x0000000000015b6b      0x2ea ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .debug_abbrev  0x0000000000015e55      0x24a ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .debug_abbrev  0x000000000001609f      0x2fa ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .debug_abbrev  0x0000000000016399      0x202 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .debug_abbrev  0x000000000001659b      0x24f ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .debug_abbrev  0x00000000000167ea      0x213 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .debug_abbrev  0x00000000000169fd      0x22f ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .debug_abbrev  0x0000000000016c2c      0x268 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .debug_abbrev  0x0000000000016e94       0x81 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .debug_abbrev  0x0000000000016f15       0x81 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .debug_abbrev  0x0000000000016f96      0x1df ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .debug_abbrev  0x0000000000017175      0x22a ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .debug_abbrev  0x000000000001739f      0x2f1 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .debug_abbrev  0x0000000000017690      0x2b0 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .debug_abbrev  0x0000000000017940      0x242 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .debug_abbrev  0x0000000000017b82       0x12 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .debug_abbrev  0x0000000000017b94      0x284 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_abbrev  0x0000000000017e18       0x44 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .debug_abbrev  0x0000000000017e5c      0x27c ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .debug_abbrev  0x00000000000180d8       0xba ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .debug_abbrev  0x0000000000018192      0x1e0 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .debug_abbrev  0x0000000000018372      0x260 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .debug_abbrev  0x00000000000185d2      0x206 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .debug_abbrev  0x00000000000187d8      0x1fa ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .debug_abbrev  0x00000000000189d2      0x2c7 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .debug_abbrev  0x0000000000018c99      0x1f8 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .debug_abbrev  0x0000000000018e91      0x21c ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .debug_abbrev  0x00000000000190ad      0x23f ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .debug_abbrev  0x00000000000192ec      0x265 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .debug_abbrev  0x0000000000019551      0x1e5 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_abbrev  0x0000000000019736       0x14 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .debug_abbrev  0x000000000001974a      0x28d ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .debug_abbrev  0x00000000000199d7      0x339 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .debug_abbrev  0x0000000000019d10      0x2b1 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .debug_abbrev  0x0000000000019fc1      0x272 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .debug_abbrev  0x000000000001a233      0x27a ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .debug_abbrev  0x000000000001a4ad      0x2d3 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .debug_abbrev  0x000000000001a780      0x340 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .debug_abbrev  0x000000000001aac0      0x2d9 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_abbrev  0x000000000001ad99      0x2a6 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .debug_abbrev  0x000000000001b03f      0x2a0 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .debug_abbrev  0x000000000001b2df      0x347 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .debug_abbrev  0x000000000001b626      0x2ea ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .debug_abbrev  0x000000000001b910      0x373 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_abbrev  0x000000000001bc83      0x26e ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .debug_abbrev  0x000000000001bef1      0x2f7 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .debug_abbrev  0x000000000001c1e8      0x319 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .debug_abbrev  0x000000000001c501      0x29e ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .debug_abbrev  0x000000000001c79f      0x2e6 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .debug_abbrev  0x000000000001ca85      0x35d ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .debug_abbrev  0x000000000001cde2      0x26e ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .debug_abbrev  0x000000000001d050      0x2a3 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .debug_abbrev  0x000000000001d2f3      0x360 ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .debug_abbrev  0x000000000001d653      0x350 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .debug_abbrev  0x000000000001d9a3      0x208 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .debug_abbrev  0x000000000001dbab       0x12 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .debug_abbrev  0x000000000001dbbd      0x26e ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .debug_abbrev  0x000000000001de2b      0x22a ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .debug_abbrev  0x000000000001e055      0x296 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .debug_abbrev  0x000000000001e2eb       0xea ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_abbrev  0x000000000001e3d5      0x243 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_abbrev  0x000000000001e618      0x225 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_abbrev  0x000000000001e83d      0x230 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_abbrev  0x000000000001ea6d      0x225 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_abbrev  0x000000000001ec92      0x275 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_abbrev  0x000000000001ef07      0x241 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_abbrev  0x000000000001f148      0x1fe c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_abbrev  0x000000000001f346      0x296 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_abbrev  0x000000000001f5dc      0x20d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_abbrev  0x000000000001f7e9      0x20d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_abbrev  0x000000000001f9f6      0x1f9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_abbrev  0x000000000001fbef      0x2db c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_abbrev  0x000000000001feca      0x413 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_abbrev  0x00000000000202dd      0x28c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_abbrev  0x0000000000020569      0x2c2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_abbrev  0x000000000002082b      0x263 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_abbrev  0x0000000000020a8e      0x26c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_abbrev  0x0000000000020cfa      0x361 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_abbrev  0x000000000002105b      0x276 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .debug_abbrev  0x00000000000212d1      0x266 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug_line     0x0000000000000000    0x3ca4d
+ *(.debug_line)
+ .debug_line    0x0000000000000000       0x6f d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_line    0x000000000000006f      0x747 obj/default/src/control.o
+ .debug_line    0x00000000000007b6      0x399 obj/default/src/main.o
+ .debug_line    0x0000000000000b4f      0x644 obj/default/src/network_utilities.o
+ .debug_line    0x0000000000001193      0x396 obj/default/src/sensor.o
+ .debug_line    0x0000000000001529      0x633 obj/default/src/socket_server.o
+ .debug_line    0x0000000000001b5c      0x2eb obj/default/src/tse_my_system.o
+ .debug_line    0x0000000000001e47      0x3bd obj/default/src/udpgen.o
+ .debug_line    0x0000000000002204      0x4ac obj/default/src/utils.o
+ .debug_line    0x00000000000026b0      0x248 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+ .debug_line    0x00000000000028f8      0x240 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_line    0x0000000000002b38      0x161 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+ .debug_line    0x0000000000002c99      0x265 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_line    0x0000000000002efe      0x240 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_line    0x000000000000313e      0x2ff c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_line    0x000000000000343d      0x244 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_line    0x0000000000003681     0x1a75 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_line    0x00000000000050f6      0x390 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_line    0x0000000000005486     0x14ab c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_line    0x0000000000006931      0x4f1 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_line    0x0000000000006e22      0x66e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_line    0x0000000000007490      0x5c0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_line    0x0000000000007a50      0x6d7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_line    0x0000000000008127      0x349 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_line    0x0000000000008470      0x358 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_line    0x00000000000087c8      0x292 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_line    0x0000000000008a5a      0x466 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_line    0x0000000000008ec0      0x936 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_line    0x00000000000097f6      0x2ab c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_line    0x0000000000009aa1      0x315 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_line    0x0000000000009db6      0x347 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_line    0x000000000000a0fd      0x33f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_line    0x000000000000a43c     0x14cb c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_line    0x000000000000b907      0x386 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_line    0x000000000000bc8d      0x82f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_line    0x000000000000c4bc      0x28a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_line    0x000000000000c746      0x230 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_line    0x000000000000c976      0x354 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_line    0x000000000000ccca     0x1411 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_line    0x000000000000e0db      0x353 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_line    0x000000000000e42e      0x22f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_line    0x000000000000e65d      0x230 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_line    0x000000000000e88d      0x279 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_line    0x000000000000eb06      0x2f9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_line    0x000000000000edff      0x3ac c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_line    0x000000000000f1ab      0x2de c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_line    0x000000000000f489      0x1d2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+ .debug_line    0x000000000000f65b      0x231 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_line    0x000000000000f88c      0x34e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_line    0x000000000000fbda      0x22f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_line    0x000000000000fe09      0x2d7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_line    0x00000000000100e0      0x22e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_line    0x000000000001030e      0x3e6 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_line    0x00000000000106f4      0x267 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_line    0x000000000001095b      0x376 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_line    0x0000000000010cd1      0x2c4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_line    0x0000000000010f95      0x39b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_line    0x0000000000011330      0x3c9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_line    0x00000000000116f9      0x304 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_line    0x00000000000119fd      0xdc9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_line    0x00000000000127c6      0xa2f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_line    0x00000000000131f5      0x134 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_line    0x0000000000013329      0x18e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_line    0x00000000000134b7      0x18d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_line    0x0000000000013644      0x867 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_line    0x0000000000013eab      0xd33 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_line    0x0000000000014bde      0x10e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_line    0x0000000000014cec      0x15f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_line    0x0000000000014e4b      0x1ad c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_line    0x0000000000014ff8      0x198 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_line    0x0000000000015190       0xab c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .debug_line    0x000000000001523b       0xfa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_line    0x0000000000015335      0x235 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .debug_line    0x000000000001556a      0x322 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .debug_line    0x000000000001588c      0x324 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .debug_line    0x0000000000015bb0      0x265 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .debug_line    0x0000000000015e15      0x333 ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .debug_line    0x0000000000016148      0x1a9 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .debug_line    0x00000000000162f1      0x21b ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .debug_line    0x000000000001650c      0x29b ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .debug_line    0x00000000000167a7      0xb32 ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .debug_line    0x00000000000172d9      0x941 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .debug_line    0x0000000000017c1a      0x42d ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .debug_line    0x0000000000018047      0x756 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .debug_line    0x000000000001879d      0x7dd ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .debug_line    0x0000000000018f7a      0x589 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .debug_line    0x0000000000019503      0x890 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .debug_line    0x0000000000019d93      0x368 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .debug_line    0x000000000001a0fb      0x4c1 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .debug_line    0x000000000001a5bc      0x20e ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .debug_line    0x000000000001a7ca     0x1c94 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .debug_line    0x000000000001c45e      0x234 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .debug_line    0x000000000001c692      0x45b ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .debug_line    0x000000000001caed      0x3b3 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .debug_line    0x000000000001cea0      0x389 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .debug_line    0x000000000001d229      0x5e8 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_line    0x000000000001d811      0xc46 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .debug_line    0x000000000001e457      0x713 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .debug_line    0x000000000001eb6a      0xb01 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .debug_line    0x000000000001f66b      0x307 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .debug_line    0x000000000001f972      0x35f ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .debug_line    0x000000000001fcd1      0x2ff ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .debug_line    0x000000000001ffd0      0x2f4 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .debug_line    0x00000000000202c4      0x88e ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .debug_line    0x0000000000020b52      0x3ee ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .debug_line    0x0000000000020f40      0x6fd ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .debug_line    0x000000000002163d      0x46a ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .debug_line    0x0000000000021aa7      0x6f9 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .debug_line    0x00000000000221a0      0x65d ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .debug_line    0x00000000000227fd      0x2ac ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .debug_line    0x0000000000022aa9      0x655 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .debug_line    0x00000000000230fe      0x3c5 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .debug_line    0x00000000000234c3      0x49e ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .debug_line    0x0000000000023961      0x35f ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .debug_line    0x0000000000023cc0      0x521 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_line    0x00000000000241e1      0x327 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .debug_line    0x0000000000024508       0xaf ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+ .debug_line    0x00000000000245b7      0x338 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .debug_line    0x00000000000248ef      0x42e ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .debug_line    0x0000000000024d1d      0x52d ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .debug_line    0x000000000002524a      0xab0 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_line    0x0000000000025cfa      0x600 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .debug_line    0x00000000000262fa      0xa4d ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .debug_line    0x0000000000026d47      0xe22 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .debug_line    0x0000000000027b69      0x85a ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .debug_line    0x00000000000283c3      0x5ea ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .debug_line    0x00000000000289ad     0x127c ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_line    0x0000000000029c29      0x9d9 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_line    0x000000000002a602      0x60a ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .debug_line    0x000000000002ac0c      0x5c8 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .debug_line    0x000000000002b1d4      0x64f ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .debug_line    0x000000000002b823      0x30d ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .debug_line    0x000000000002bb30      0x697 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .debug_line    0x000000000002c1c7      0x1b6 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .debug_line    0x000000000002c37d      0x280 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .debug_line    0x000000000002c5fd      0x1c1 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .debug_line    0x000000000002c7be      0x2b9 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .debug_line    0x000000000002ca77      0x1e3 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .debug_line    0x000000000002cc5a       0x66 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .debug_line    0x000000000002ccc0       0x66 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .debug_line    0x000000000002cd26      0x131 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+ .debug_line    0x000000000002ce57      0x1f8 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .debug_line    0x000000000002d04f      0x203 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .debug_line    0x000000000002d252      0x1d5 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .debug_line    0x000000000002d427      0x2ec ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .debug_line    0x000000000002d713       0x6b ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .debug_line    0x000000000002d77e      0x234 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_line    0x000000000002d9b2       0x50 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+ .debug_line    0x000000000002da02      0x2c3 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .debug_line    0x000000000002dcc5      0x155 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .debug_line    0x000000000002de1a      0x125 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .debug_line    0x000000000002df3f      0x353 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .debug_line    0x000000000002e292      0x1d9 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .debug_line    0x000000000002e46b      0x19d ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .debug_line    0x000000000002e608      0x290 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .debug_line    0x000000000002e898      0x1a1 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .debug_line    0x000000000002ea39      0x1b3 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .debug_line    0x000000000002ebec      0x225 ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .debug_line    0x000000000002ee11      0x356 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .debug_line    0x000000000002f167      0x137 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_line    0x000000000002f29e       0x86 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+ .debug_line    0x000000000002f324      0x224 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .debug_line    0x000000000002f548      0x41b ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .debug_line    0x000000000002f963      0x40c ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .debug_line    0x000000000002fd6f      0x33f ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .debug_line    0x00000000000300ae      0x328 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .debug_line    0x00000000000303d6      0x790 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .debug_line    0x0000000000030b66      0x9c5 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .debug_line    0x000000000003152b      0x73d ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_line    0x0000000000031c68      0x3cd ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .debug_line    0x0000000000032035      0x2f0 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .debug_line    0x0000000000032325      0x452 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .debug_line    0x0000000000032777      0x4a7 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .debug_line    0x0000000000032c1e      0x76f ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_line    0x000000000003338d      0x3c0 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .debug_line    0x000000000003374d      0x4e1 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .debug_line    0x0000000000033c2e      0x635 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .debug_line    0x0000000000034263      0x454 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .debug_line    0x00000000000346b7      0x394 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .debug_line    0x0000000000034a4b      0x56f ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .debug_line    0x0000000000034fba      0x35c ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .debug_line    0x0000000000035316      0x3ae ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .debug_line    0x00000000000356c4      0x5bd ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .debug_line    0x0000000000035c81      0xaab ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .debug_line    0x000000000003672c      0x290 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .debug_line    0x00000000000369bc       0xb3 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .debug_line    0x0000000000036a6f      0x359 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .debug_line    0x0000000000036dc8      0x226 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .debug_line    0x0000000000036fee      0x23c ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .debug_line    0x000000000003722a       0xda ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_line    0x0000000000037304      0x1fb c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_line    0x00000000000374ff      0x20c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_line    0x000000000003770b      0x223 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_line    0x000000000003792e      0x1fc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_line    0x0000000000037b2a      0x2d8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_line    0x0000000000037e02      0x219 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_line    0x000000000003801b      0x25f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_line    0x000000000003827a      0x2d6 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_line    0x0000000000038550      0x2e2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_line    0x0000000000038832      0x252 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_line    0x0000000000038a84      0x2c5 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_line    0x0000000000038d49      0x47f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_line    0x00000000000391c8     0x1957 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_line    0x000000000003ab1f      0x253 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_line    0x000000000003ad72      0x295 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_line    0x000000000003b007      0x283 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_line    0x000000000003b28a      0x2c4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_line    0x000000000003b54e     0x10e5 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_line    0x000000000003c633      0x224 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .debug_line    0x000000000003c857      0x1f6 ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug_frame    0x0000000000000000     0x8900
+ *(.debug_frame)
+ .debug_frame   0x0000000000000000      0x190 obj/default/src/control.o
+ .debug_frame   0x0000000000000190       0x48 obj/default/src/main.o
+ .debug_frame   0x00000000000001d8      0x128 obj/default/src/network_utilities.o
+ .debug_frame   0x0000000000000300       0x5c obj/default/src/sensor.o
+ .debug_frame   0x000000000000035c      0x16c obj/default/src/socket_server.o
+ .debug_frame   0x00000000000004c8       0x5c obj/default/src/udpgen.o
+ .debug_frame   0x0000000000000524      0x1a4 obj/default/src/utils.o
+ .debug_frame   0x00000000000006c8       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_frame   0x00000000000006f8       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_frame   0x0000000000000740       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_frame   0x0000000000000770       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_frame   0x00000000000007b8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_frame   0x00000000000007d8       0x98 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_frame   0x0000000000000870       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_frame   0x00000000000008a8       0x9c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_frame   0x0000000000000944       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_frame   0x00000000000009c0      0x124 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_frame   0x0000000000000ae4       0x78 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_frame   0x0000000000000b5c       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_frame   0x0000000000000bd8       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_frame   0x0000000000000c54       0x6c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_frame   0x0000000000000cc0       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_frame   0x0000000000000d00       0x68 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_frame   0x0000000000000d68       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_frame   0x0000000000000dc0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_frame   0x0000000000000de0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_frame   0x0000000000000e00       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_frame   0x0000000000000e20       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_frame   0x0000000000000e40      0x2dc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_frame   0x000000000000111c       0x78 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_frame   0x0000000000001194       0x70 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_frame   0x0000000000001204       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_frame   0x000000000000124c       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_frame   0x0000000000001288       0xb8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_frame   0x0000000000001340       0xec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_frame   0x000000000000142c       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_frame   0x000000000000147c       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_frame   0x00000000000014b8       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_frame   0x00000000000014f4       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_frame   0x000000000000152c       0x4c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_frame   0x0000000000001578       0x7c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_frame   0x00000000000015f4       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_frame   0x0000000000001630       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_frame   0x000000000000166c       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_frame   0x00000000000016c4       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_frame   0x0000000000001700       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_frame   0x0000000000001740       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_frame   0x000000000000177c       0x4c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_frame   0x00000000000017c8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_frame   0x00000000000017e8       0x60 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_frame   0x0000000000001848       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_frame   0x0000000000001878       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_frame   0x00000000000018cc       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_frame   0x0000000000001920       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_frame   0x0000000000001970       0x44 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_frame   0x00000000000019b4       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_frame   0x0000000000001a0c       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_frame   0x0000000000001a2c       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_frame   0x0000000000001a4c       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_frame   0x0000000000001a6c       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_frame   0x0000000000001ac0       0x44 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_frame   0x0000000000001b04       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_frame   0x0000000000001b24       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_frame   0x0000000000001b44       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_frame   0x0000000000001b7c       0x34 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_frame   0x0000000000001bb0       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_frame   0x0000000000001bd0       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+ .debug_frame   0x0000000000001c30       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+ .debug_frame   0x0000000000001c90       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+ .debug_frame   0x0000000000001cf0       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+ .debug_frame   0x0000000000001d50       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+ .debug_frame   0x0000000000001d7c       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+ .debug_frame   0x0000000000001db0       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+ .debug_frame   0x0000000000001e10       0x64 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+ .debug_frame   0x0000000000001e74      0x49c ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+ .debug_frame   0x0000000000002310      0x200 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+ .debug_frame   0x0000000000002510      0x118 ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+ .debug_frame   0x0000000000002628      0x11c ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+ .debug_frame   0x0000000000002744      0x1bc ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+ .debug_frame   0x0000000000002900      0x144 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+ .debug_frame   0x0000000000002a44      0x19c ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+ .debug_frame   0x0000000000002be0       0xd4 ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+ .debug_frame   0x0000000000002cb4       0x88 ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+ .debug_frame   0x0000000000002d3c       0x60 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+ .debug_frame   0x0000000000002d9c      0x718 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+ .debug_frame   0x00000000000034b4       0x88 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+ .debug_frame   0x000000000000353c       0xd4 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+ .debug_frame   0x0000000000003610       0x60 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+ .debug_frame   0x0000000000003670       0x60 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+ .debug_frame   0x00000000000036d0      0x198 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_frame   0x0000000000003868      0x59c ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+ .debug_frame   0x0000000000003e04      0x1a4 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+ .debug_frame   0x0000000000003fa8      0x214 ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+ .debug_frame   0x00000000000041bc       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+ .debug_frame   0x00000000000041f4       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+ .debug_frame   0x000000000000422c       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+ .debug_frame   0x0000000000004264       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+ .debug_frame   0x000000000000429c      0x1f0 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+ .debug_frame   0x000000000000448c       0xac ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+ .debug_frame   0x0000000000004538       0xfc ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+ .debug_frame   0x0000000000004634       0xb0 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+ .debug_frame   0x00000000000046e4      0x150 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+ .debug_frame   0x0000000000004834      0x19c ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+ .debug_frame   0x00000000000049d0       0x5c ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+ .debug_frame   0x0000000000004a2c      0x1f0 ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+ .debug_frame   0x0000000000004c1c       0x70 ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+ .debug_frame   0x0000000000004c8c      0x128 ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+ .debug_frame   0x0000000000004db4       0x38 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+ .debug_frame   0x0000000000004dec       0xfc ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_frame   0x0000000000004ee8       0x88 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+ .debug_frame   0x0000000000004f70      0x13c ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+ .debug_frame   0x00000000000050ac       0xd8 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+ .debug_frame   0x0000000000005184      0x198 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+ .debug_frame   0x000000000000531c      0x2cc ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_frame   0x00000000000055e8       0x8c ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+ .debug_frame   0x0000000000005674      0x308 ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+ .debug_frame   0x000000000000597c      0x290 ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+ .debug_frame   0x0000000000005c0c      0x398 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+ .debug_frame   0x0000000000005fa4      0x178 ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+ .debug_frame   0x000000000000611c      0x128 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_frame   0x0000000000006244       0x88 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_frame   0x00000000000062cc      0x168 ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+ .debug_frame   0x0000000000006434       0x84 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+ .debug_frame   0x00000000000064b8       0xb0 ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+ .debug_frame   0x0000000000006568       0x38 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+ .debug_frame   0x00000000000065a0      0x104 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+ .debug_frame   0x00000000000066a4       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+ .debug_frame   0x00000000000066dc       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+ .debug_frame   0x000000000000673c       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+ .debug_frame   0x0000000000006770       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+ .debug_frame   0x00000000000067a4       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+ .debug_frame   0x0000000000006804       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+ .debug_frame   0x000000000000683c       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+ .debug_frame   0x0000000000006874       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+ .debug_frame   0x00000000000068ac       0xa4 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+ .debug_frame   0x0000000000006950       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+ .debug_frame   0x0000000000006988       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+ .debug_frame   0x00000000000069e8       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_frame   0x0000000000006a20       0x84 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+ .debug_frame   0x0000000000006aa4       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+ .debug_frame   0x0000000000006adc       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+ .debug_frame   0x0000000000006b14       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+ .debug_frame   0x0000000000006b74       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+ .debug_frame   0x0000000000006ba8       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+ .debug_frame   0x0000000000006bdc       0x5c ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+ .debug_frame   0x0000000000006c38       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+ .debug_frame   0x0000000000006c70       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+ .debug_frame   0x0000000000006ca8       0x3c ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+ .debug_frame   0x0000000000006ce4       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+ .debug_frame   0x0000000000006d44       0x34 ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+ .debug_frame   0x0000000000006d78      0x180 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+ .debug_frame   0x0000000000006ef8      0x134 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+ .debug_frame   0x000000000000702c       0xb0 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+ .debug_frame   0x00000000000070dc       0x5c ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+ .debug_frame   0x0000000000007138       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+ .debug_frame   0x0000000000007170       0xbc ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+ .debug_frame   0x000000000000722c      0x1a0 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+ .debug_frame   0x00000000000073cc       0x90 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_frame   0x000000000000745c       0x84 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+ .debug_frame   0x00000000000074e0       0x78 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+ .debug_frame   0x0000000000007558       0xfc ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+ .debug_frame   0x0000000000007654       0x84 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+ .debug_frame   0x00000000000076d8      0x11c ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_frame   0x00000000000077f4       0x38 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+ .debug_frame   0x000000000000782c       0xd4 ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+ .debug_frame   0x0000000000007900       0xb0 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+ .debug_frame   0x00000000000079b0       0x64 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+ .debug_frame   0x0000000000007a14      0x158 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+ .debug_frame   0x0000000000007b6c      0x16c ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+ .debug_frame   0x0000000000007cd8       0x38 ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+ .debug_frame   0x0000000000007d10       0x60 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+ .debug_frame   0x0000000000007d70      0x14c ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+ .debug_frame   0x0000000000007ebc      0x460 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+ .debug_frame   0x000000000000831c       0x34 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+ .debug_frame   0x0000000000008350       0x60 ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+ .debug_frame   0x00000000000083b0       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+ .debug_frame   0x00000000000083e8       0x38 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+ .debug_frame   0x0000000000008420       0x5c ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_frame   0x000000000000847c       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_frame   0x000000000000849c       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_frame   0x00000000000084cc       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_frame   0x00000000000084f4       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_frame   0x0000000000008514       0x54 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_frame   0x0000000000008568       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_frame   0x0000000000008598       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_frame   0x00000000000085b8       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_frame   0x0000000000008600       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_frame   0x0000000000008620       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_frame   0x0000000000008640       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_frame   0x0000000000008660       0x84 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_frame   0x00000000000086e4       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_frame   0x000000000000873c       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_frame   0x000000000000876c       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_frame   0x00000000000087a8       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_frame   0x00000000000087c8       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_frame   0x0000000000008818       0x9c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_frame   0x00000000000088b4       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+ .debug_frame   0x00000000000088d4       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+
+.debug_str      0x0000000000000000     0xc2e6
+ *(.debug_str)
+ .debug_str     0x0000000000000000       0x4f d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_str     0x000000000000004f     0x17e8 obj/default/src/control.o
+                                       0x19d4 (size before relaxing)
+ .debug_str     0x0000000000001837       0x31 obj/default/src/main.o
+                                       0x1670 (size before relaxing)
+ .debug_str     0x0000000000001868      0x2fb obj/default/src/network_utilities.o
+                                       0x1799 (size before relaxing)
+ .debug_str     0x0000000000001b63       0x3c obj/default/src/sensor.o
+                                       0x166f (size before relaxing)
+ .debug_str     0x0000000000001b9f      0x1ca obj/default/src/socket_server.o
+                                       0x1ab5 (size before relaxing)
+ .debug_str     0x0000000000001d69      0x6f6 obj/default/src/tse_my_system.o
+                                       0x125b (size before relaxing)
+ .debug_str     0x000000000000245f       0x39 obj/default/src/udpgen.o
+                                       0x167a (size before relaxing)
+ .debug_str     0x0000000000002498       0xc5 obj/default/src/utils.o
+                                       0x1708 (size before relaxing)
+ .debug_str     0x000000000000255d      0x375 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-ctype_.o)
+                                        0x8bb (size before relaxing)
+ .debug_str     0x00000000000028d2      0x1d4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+                                        0x6eb (size before relaxing)
+ .debug_str     0x0000000000002aa6       0xca c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-impure.o)
+                                        0x59a (size before relaxing)
+ .debug_str     0x0000000000002b70       0x91 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+                                        0x72e (size before relaxing)
+ .debug_str     0x0000000000002c01       0x4f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+                                        0x6eb (size before relaxing)
+ .debug_str     0x0000000000002c50       0xae c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+                                        0x74f (size before relaxing)
+ .debug_str     0x0000000000002cfe       0xcd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+                                        0x5b1 (size before relaxing)
+ .debug_str     0x0000000000002dcb      0x1dd c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+                                        0xcc5 (size before relaxing)
+ .debug_str     0x0000000000002fa8       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+                                        0x71e (size before relaxing)
+ .debug_str     0x0000000000002ff8      0x207 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+                                        0xa94 (size before relaxing)
+ .debug_str     0x00000000000031ff       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+                                        0x74c (size before relaxing)
+ .debug_str     0x0000000000003263      0x16c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+                                        0x86d (size before relaxing)
+ .debug_str     0x00000000000033cf      0x1a9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+                                        0x77b (size before relaxing)
+ .debug_str     0x0000000000003578       0x6d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+                                        0x7ae (size before relaxing)
+ .debug_str     0x00000000000035e5       0x49 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+                                        0x710 (size before relaxing)
+ .debug_str     0x000000000000362e       0x43 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+                                        0x708 (size before relaxing)
+ .debug_str     0x0000000000003671      0x126 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+                                        0x92c (size before relaxing)
+ .debug_str     0x0000000000003797      0x153 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+                                        0x89a (size before relaxing)
+ .debug_str     0x00000000000038ea       0xaa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+                                        0x802 (size before relaxing)
+ .debug_str     0x0000000000003994       0x4a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+                                        0x5b8 (size before relaxing)
+ .debug_str     0x00000000000039de       0x63 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+                                        0x8da (size before relaxing)
+ .debug_str     0x0000000000003a41       0x46 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+                                        0x8e6 (size before relaxing)
+ .debug_str     0x0000000000003a87       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+                                        0x8c7 (size before relaxing)
+ .debug_str     0x0000000000003ac3       0x95 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+                                        0xa3d (size before relaxing)
+ .debug_str     0x0000000000003b58       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+                                        0x708 (size before relaxing)
+ .debug_str     0x0000000000003ba0       0x49 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+                                        0x7b9 (size before relaxing)
+ .debug_str     0x0000000000003be9       0x4d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+                                        0x719 (size before relaxing)
+ .debug_str     0x0000000000003c36       0x4e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+                                        0x5dc (size before relaxing)
+ .debug_str     0x0000000000003c84       0x9a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+                                        0x764 (size before relaxing)
+ .debug_str     0x0000000000003d1e       0x37 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+                                        0xc2d (size before relaxing)
+ .debug_str     0x0000000000003d55       0x41 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+                                        0x723 (size before relaxing)
+ .debug_str     0x0000000000003d96       0x3b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+                                        0x5e0 (size before relaxing)
+ .debug_str     0x0000000000003dd1       0x3b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+                                        0x5d0 (size before relaxing)
+ .debug_str     0x0000000000003e0c        0xf c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+                                        0x737 (size before relaxing)
+ .debug_str     0x0000000000003e1b       0x45 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+                                        0x735 (size before relaxing)
+ .debug_str     0x0000000000003e60       0x63 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+                                        0x755 (size before relaxing)
+ .debug_str     0x0000000000003ec3       0x41 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+                                        0x740 (size before relaxing)
+ .debug_str     0x0000000000003f04       0x3e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-int_errno.o)
+                                        0x5a1 (size before relaxing)
+ .debug_str     0x0000000000003f42       0x43 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+                                        0x5d3 (size before relaxing)
+ .debug_str     0x0000000000003f85       0x6f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+                                        0x975 (size before relaxing)
+ .debug_str     0x0000000000003ff4       0x41 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+                                        0x5d7 (size before relaxing)
+ .debug_str     0x0000000000004035       0x5d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+                                        0x93d (size before relaxing)
+ .debug_str     0x0000000000004092       0x3a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+                                        0x5dd (size before relaxing)
+ .debug_str     0x00000000000040cc       0x4d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+                                        0x753 (size before relaxing)
+ .debug_str     0x0000000000004119       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+                                        0x597 (size before relaxing)
+ .debug_str     0x0000000000004155       0x4c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+                                        0x937 (size before relaxing)
+ .debug_str     0x00000000000041a1       0x5e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+                                        0x944 (size before relaxing)
+ .debug_str     0x00000000000041ff      0x25b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+                                        0x2f5 (size before relaxing)
+ .debug_str     0x000000000000445a        0xa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+                                        0x2f5 (size before relaxing)
+ .debug_str     0x0000000000004464       0xfb c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+                                        0x1c3 (size before relaxing)
+ .debug_str     0x000000000000455f      0x183 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+                                        0x317 (size before relaxing)
+ .debug_str     0x00000000000046e2      0x19a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+                                        0x3d9 (size before relaxing)
+ .debug_str     0x000000000000487c       0x47 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+                                        0x223 (size before relaxing)
+ .debug_str     0x00000000000048c3       0x5a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+                                        0x247 (size before relaxing)
+ .debug_str     0x000000000000491d       0x36 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+                                        0x247 (size before relaxing)
+ .debug_str     0x0000000000004953      0x15d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+                                        0x431 (size before relaxing)
+ .debug_str     0x0000000000004ab0       0x38 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+                                        0x317 (size before relaxing)
+ .debug_str     0x0000000000004ae8       0x3c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+                                        0x229 (size before relaxing)
+ .debug_str     0x0000000000004b24       0x4d c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+                                        0x22e (size before relaxing)
+ .debug_str     0x0000000000004b71       0x6b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+                                        0x2c9 (size before relaxing)
+ .debug_str     0x0000000000004bdc       0x42 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+                                        0x2c6 (size before relaxing)
+ .debug_str     0x0000000000004c1e      0x23c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clz.o)
+ .debug_str     0x0000000000004c1e        0x9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+                                        0x259 (size before relaxing)
+ .debug_str     0x0000000000004c27      0x112 ../hit_pat_bsp\libucosii_bsp.a(alt_flash_dev.o)
+                                        0xc4c (size before relaxing)
+ .debug_str     0x0000000000004d39       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_fstat.o)
+                                        0xc58 (size before relaxing)
+ .debug_str     0x0000000000004d65       0x15 ../hit_pat_bsp\libucosii_bsp.a(alt_isatty.o)
+                                        0xc60 (size before relaxing)
+ .debug_str     0x0000000000004d7a       0x14 ../hit_pat_bsp\libucosii_bsp.a(alt_lseek.o)
+                                        0xb2e (size before relaxing)
+ .debug_str     0x0000000000004d8e       0x5d ../hit_pat_bsp\libucosii_bsp.a(alt_main.o)
+                                        0xcc2 (size before relaxing)
+ .debug_str     0x0000000000004deb       0x98 ../hit_pat_bsp\libucosii_bsp.a(alt_sbrk.o)
+                                        0x5be (size before relaxing)
+ .debug_str     0x0000000000004e83       0x5f ../hit_pat_bsp\libucosii_bsp.a(alt_env_lock.o)
+                                        0xa75 (size before relaxing)
+ .debug_str     0x0000000000004ee2       0x24 ../hit_pat_bsp\libucosii_bsp.a(alt_malloc_lock.o)
+                                        0xac5 (size before relaxing)
+ .debug_str     0x0000000000004f06      0x29b ../hit_pat_bsp\libucosii_bsp.a(os_core.o)
+                                        0xcb9 (size before relaxing)
+ .debug_str     0x00000000000051a1      0x136 ../hit_pat_bsp\libucosii_bsp.a(os_flag.o)
+                                        0xb6b (size before relaxing)
+ .debug_str     0x00000000000052d7       0xcf ../hit_pat_bsp\libucosii_bsp.a(os_mem.o)
+                                        0xae8 (size before relaxing)
+ .debug_str     0x00000000000053a6       0xd0 ../hit_pat_bsp\libucosii_bsp.a(os_mutex.o)
+                                        0xb10 (size before relaxing)
+ .debug_str     0x0000000000005476       0xb2 ../hit_pat_bsp\libucosii_bsp.a(os_q.o)
+                                        0xafe (size before relaxing)
+ .debug_str     0x0000000000005528       0x77 ../hit_pat_bsp\libucosii_bsp.a(os_sem.o)
+                                        0xadb (size before relaxing)
+ .debug_str     0x000000000000559f       0xc9 ../hit_pat_bsp\libucosii_bsp.a(os_task.o)
+                                        0xb47 (size before relaxing)
+ .debug_str     0x0000000000005668       0x5d ../hit_pat_bsp\libucosii_bsp.a(os_time.o)
+                                        0xa7e (size before relaxing)
+ .debug_str     0x00000000000056c5      0x53c ../hit_pat_bsp\libucosii_bsp.a(alt_sys_init.o)
+                                       0x1bd2 (size before relaxing)
+ .debug_str     0x0000000000005c01       0x78 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_timer_sc.o)
+                                        0x66f (size before relaxing)
+ .debug_str     0x0000000000005c79     0x130c ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_tse.o)
+                                       0x278b (size before relaxing)
+ .debug_str     0x0000000000006f85       0x77 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_fd.o)
+                                        0xbbc (size before relaxing)
+ .debug_str     0x0000000000006ffc       0xc5 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_init.o)
+                                        0xbcd (size before relaxing)
+ .debug_str     0x00000000000070c1       0x6a ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_read.o)
+                                        0xba1 (size before relaxing)
+ .debug_str     0x000000000000712b       0x49 ../hit_pat_bsp\libucosii_bsp.a(altera_avalon_uart_write.o)
+                                        0xb95 (size before relaxing)
+ .debug_str     0x0000000000007174      0x255 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+                                        0x9ef (size before relaxing)
+ .debug_str     0x00000000000073c9      0x8a0 ../hit_pat_bsp\libucosii_bsp.a(altera_msgdma.o)
+                                       0x1605 (size before relaxing)
+ .debug_str     0x0000000000007c69      0x256 ../hit_pat_bsp\libucosii_bsp.a(altera_onchip_flash.o)
+                                        0xadf (size before relaxing)
+ .debug_str     0x0000000000007ebf      0x71d ../hit_pat_bsp\libucosii_bsp.a(ins_tse_mac.o)
+                                       0x2994 (size before relaxing)
+ .debug_str     0x00000000000085dc       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_close.o)
+                                       0x1413 (size before relaxing)
+ .debug_str     0x00000000000085fa       0x48 ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_dev.o)
+                                       0x14da (size before relaxing)
+ .debug_str     0x0000000000008642       0x1d ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_read.o)
+                                       0x1418 (size before relaxing)
+ .debug_str     0x000000000000865f       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_write.o)
+                                       0x141a (size before relaxing)
+ .debug_str     0x000000000000867d      0x1a7 ../hit_pat_bsp\libucosii_bsp.a(et_arp.o)
+                                       0x13eb (size before relaxing)
+ .debug_str     0x0000000000008824       0xae ../hit_pat_bsp\libucosii_bsp.a(iface.o)
+                                       0x152a (size before relaxing)
+ .debug_str     0x00000000000088d2       0x5b ../hit_pat_bsp\libucosii_bsp.a(ipnet.o)
+                                       0x1295 (size before relaxing)
+ .debug_str     0x000000000000892d       0x83 ../hit_pat_bsp\libucosii_bsp.a(ipstart.o)
+                                       0x158b (size before relaxing)
+ .debug_str     0x00000000000089b0      0x450 ../hit_pat_bsp\libucosii_bsp.a(igmp_cmn.o)
+                                       0x1940 (size before relaxing)
+ .debug_str     0x0000000000008e00      0x106 ../hit_pat_bsp\libucosii_bsp.a(bsdsock.o)
+                                       0x15e6 (size before relaxing)
+ .debug_str     0x0000000000008f06       0x35 ../hit_pat_bsp\libucosii_bsp.a(cksum.o)
+                                        0xaf9 (size before relaxing)
+ .debug_str     0x0000000000008f3b      0x11b ../hit_pat_bsp\libucosii_bsp.a(in_utils.o)
+                                       0x1620 (size before relaxing)
+ .debug_str     0x0000000000009056       0x5a ../hit_pat_bsp\libucosii_bsp.a(netmain.o)
+                                       0x167d (size before relaxing)
+ .debug_str     0x00000000000090b0      0x11e ../hit_pat_bsp\libucosii_bsp.a(tk_crnos.o)
+                                       0x174e (size before relaxing)
+ .debug_str     0x00000000000091ce       0x53 ../hit_pat_bsp\libucosii_bsp.a(ping.o)
+                                       0x1453 (size before relaxing)
+ .debug_str     0x0000000000009221       0xa0 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+                                       0x1249 (size before relaxing)
+ .debug_str     0x00000000000092c1       0x32 ../hit_pat_bsp\libucosii_bsp.a(q.o)
+                                        0xb19 (size before relaxing)
+ .debug_str     0x00000000000092f3       0x1d ../hit_pat_bsp\libucosii_bsp.a(asm_cksum.o)
+                                         0x5d (size before relaxing)
+ .debug_str     0x0000000000009310       0xb2 ../hit_pat_bsp\libucosii_bsp.a(brdutils.o)
+                                        0xbb8 (size before relaxing)
+ .debug_str     0x00000000000093c2       0xd0 ../hit_pat_bsp\libucosii_bsp.a(osportco.o)
+                                       0x17a4 (size before relaxing)
+ .debug_str     0x0000000000009492      0x1c7 ../hit_pat_bsp\libucosii_bsp.a(targnios.o)
+                                       0x1b0d (size before relaxing)
+ .debug_str     0x0000000000009659      0x6d1 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+                                       0x1ed8 (size before relaxing)
+ .debug_str     0x0000000000009d2a       0x48 ../hit_pat_bsp\libucosii_bsp.a(rawsock.o)
+                                       0x1535 (size before relaxing)
+ .debug_str     0x0000000000009d72      0x10c ../hit_pat_bsp\libucosii_bsp.a(sockcall.o)
+                                       0x1bcd (size before relaxing)
+ .debug_str     0x0000000000009e7e      0x11d ../hit_pat_bsp\libucosii_bsp.a(socket.o)
+                                       0x1b29 (size before relaxing)
+ .debug_str     0x0000000000009f9b      0x147 ../hit_pat_bsp\libucosii_bsp.a(socket2.o)
+                                       0x15c1 (size before relaxing)
+ .debug_str     0x000000000000a0e2       0x9c ../hit_pat_bsp\libucosii_bsp.a(soselect.o)
+                                       0x1584 (size before relaxing)
+ .debug_str     0x000000000000a17e      0x122 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+                                       0x1be1 (size before relaxing)
+ .debug_str     0x000000000000a2a0       0x8d ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+                                       0x1af0 (size before relaxing)
+ .debug_str     0x000000000000a32d       0x8a ../hit_pat_bsp\libucosii_bsp.a(tcp_subr.o)
+                                       0x1b37 (size before relaxing)
+ .debug_str     0x000000000000a3b7       0x64 ../hit_pat_bsp\libucosii_bsp.a(tcp_timr.o)
+                                       0x1aac (size before relaxing)
+ .debug_str     0x000000000000a41b       0x5b ../hit_pat_bsp\libucosii_bsp.a(tcp_usr.o)
+                                       0x1ad5 (size before relaxing)
+ .debug_str     0x000000000000a476       0x21 ../hit_pat_bsp\libucosii_bsp.a(tcpport.o)
+                                       0x14ea (size before relaxing)
+ .debug_str     0x000000000000a497       0x99 ../hit_pat_bsp\libucosii_bsp.a(udpsock.o)
+                                       0x15e9 (size before relaxing)
+ .debug_str     0x000000000000a530       0x42 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+                                        0x53e (size before relaxing)
+ .debug_str     0x000000000000a572       0x25 ../hit_pat_bsp\libucosii_bsp.a(alt_close.o)
+                                        0xb31 (size before relaxing)
+ .debug_str     0x000000000000a597       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_dcache_flush.o)
+                                        0x538 (size before relaxing)
+ .debug_str     0x000000000000a5c3       0x32 ../hit_pat_bsp\libucosii_bsp.a(alt_dev.o)
+                                        0xc80 (size before relaxing)
+ .debug_str     0x000000000000a5f5       0x34 ../hit_pat_bsp\libucosii_bsp.a(alt_dev_llist_insert.o)
+                                        0x5b6 (size before relaxing)
+ .debug_str     0x000000000000a629       0x48 ../hit_pat_bsp\libucosii_bsp.a(alt_do_ctors.o)
+                                         0xcd (size before relaxing)
+ .debug_str     0x000000000000a671       0x4c ../hit_pat_bsp\libucosii_bsp.a(alt_do_dtors.o)
+                                         0xcc (size before relaxing)
+ .debug_str     0x000000000000a6bd       0x14 ../hit_pat_bsp\libucosii_bsp.a(alt_errno.o)
+                                        0x52f (size before relaxing)
+ .debug_str     0x000000000000a6d1       0x24 ../hit_pat_bsp\libucosii_bsp.a(alt_find_dev.o)
+                                        0xae0 (size before relaxing)
+ .debug_str     0x000000000000a6f5       0xa5 ../hit_pat_bsp\libucosii_bsp.a(alt_iic.o)
+                                        0x616 (size before relaxing)
+ .debug_str     0x000000000000a79a       0x4c ../hit_pat_bsp\libucosii_bsp.a(alt_iic_isr_register.o)
+                                        0x5d2 (size before relaxing)
+ .debug_str     0x000000000000a7e6       0x56 ../hit_pat_bsp\libucosii_bsp.a(alt_io_redirect.o)
+                                        0xcaf (size before relaxing)
+ .debug_str     0x000000000000a83c       0x18 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+                                         0x58 (size before relaxing)
+ .debug_str     0x000000000000a854       0x3a ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+                                        0xa8a (size before relaxing)
+ .debug_str     0x000000000000a88e       0x29 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_vars.o)
+                                        0x137 (size before relaxing)
+ .debug_str     0x000000000000a8b7       0x29 ../hit_pat_bsp\libucosii_bsp.a(alt_open.o)
+                                        0xb20 (size before relaxing)
+ .debug_str     0x000000000000a8e0       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_printf.o)
+                                         0xf7 (size before relaxing)
+ .debug_str     0x000000000000a90c       0x22 ../hit_pat_bsp\libucosii_bsp.a(alt_putchar.o)
+                                        0x516 (size before relaxing)
+ .debug_str     0x000000000000a92e       0x1c ../hit_pat_bsp\libucosii_bsp.a(alt_read.o)
+                                        0xc99 (size before relaxing)
+ .debug_str     0x000000000000a94a       0x28 ../hit_pat_bsp\libucosii_bsp.a(alt_release_fd.o)
+                                        0xae4 (size before relaxing)
+ .debug_str     0x000000000000a972       0x2c ../hit_pat_bsp\libucosii_bsp.a(alt_remap_cached.o)
+                                        0x532 (size before relaxing)
+ .debug_str     0x000000000000a99e       0x69 ../hit_pat_bsp\libucosii_bsp.a(alt_tick.o)
+                                        0xaf7 (size before relaxing)
+ .debug_str     0x000000000000aa07       0x2e ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_free.o)
+                                        0x534 (size before relaxing)
+ .debug_str     0x000000000000aa35       0x49 ../hit_pat_bsp\libucosii_bsp.a(alt_uncached_malloc.o)
+                                        0x55b (size before relaxing)
+ .debug_str     0x000000000000aa7e       0x3e ../hit_pat_bsp\libucosii_bsp.a(alt_usleep.o)
+                                        0xa8b (size before relaxing)
+ .debug_str     0x000000000000aabc       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_write.o)
+                                        0xc9b (size before relaxing)
+ .debug_str     0x000000000000aada       0x3b ../hit_pat_bsp\libucosii_bsp.a(altera_nios2_gen2_irq.o)
+                                        0x546 (size before relaxing)
+ .debug_str     0x000000000000ab15       0x13 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_a.o)
+                                         0x53 (size before relaxing)
+ .debug_str     0x000000000000ab28       0xd5 ../hit_pat_bsp\libucosii_bsp.a(os_cpu_c.o)
+                                        0xaea (size before relaxing)
+ .debug_str     0x000000000000abfd       0xa3 ../hit_pat_bsp\libucosii_bsp.a(allports.o)
+                                       0x16d9 (size before relaxing)
+ .debug_str     0x000000000000aca0       0x81 ../hit_pat_bsp\libucosii_bsp.a(timeouts.o)
+                                       0x12dd (size before relaxing)
+ .debug_str     0x000000000000ad21       0x39 ../hit_pat_bsp\libucosii_bsp.a(tk_misc.o)
+                                       0x166b (size before relaxing)
+ .debug_str     0x000000000000ad5a       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_iniche_fcntl.o)
+                                       0x1446 (size before relaxing)
+ .debug_str     0x000000000000ad78       0xa4 ../hit_pat_bsp\libucosii_bsp.a(icmp.o)
+                                       0x14d7 (size before relaxing)
+ .debug_str     0x000000000000ae1c       0xd6 ../hit_pat_bsp\libucosii_bsp.a(ip.o)
+                                       0x1557 (size before relaxing)
+ .debug_str     0x000000000000aef2       0x65 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+                                       0x151a (size before relaxing)
+ .debug_str     0x000000000000af57       0x43 ../hit_pat_bsp\libucosii_bsp.a(ipmc.o)
+                                       0x1216 (size before relaxing)
+ .debug_str     0x000000000000af9a       0x38 ../hit_pat_bsp\libucosii_bsp.a(ipport.o)
+                                       0x1201 (size before relaxing)
+ .debug_str     0x000000000000afd2       0xa1 ../hit_pat_bsp\libucosii_bsp.a(ipraw.o)
+                                       0x12af (size before relaxing)
+ .debug_str     0x000000000000b073       0xa4 ../hit_pat_bsp\libucosii_bsp.a(iproute.o)
+                                       0x1267 (size before relaxing)
+ .debug_str     0x000000000000b117       0x9b ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+                                       0x17be (size before relaxing)
+ .debug_str     0x000000000000b1b2       0x24 ../hit_pat_bsp\libucosii_bsp.a(igmp.o)
+                                       0x1881 (size before relaxing)
+ .debug_str     0x000000000000b1d6       0xbc ../hit_pat_bsp\libucosii_bsp.a(igmp2.o)
+                                       0x1939 (size before relaxing)
+ .debug_str     0x000000000000b292       0x79 ../hit_pat_bsp\libucosii_bsp.a(ipopt.o)
+                                       0x154c (size before relaxing)
+ .debug_str     0x000000000000b30b       0x87 ../hit_pat_bsp\libucosii_bsp.a(u_mctest.o)
+                                       0x1538 (size before relaxing)
+ .debug_str     0x000000000000b392       0xa6 ../hit_pat_bsp\libucosii_bsp.a(memdev.o)
+                                        0xcac (size before relaxing)
+ .debug_str     0x000000000000b438       0xba ../hit_pat_bsp\libucosii_bsp.a(parseip.o)
+                                       0x1316 (size before relaxing)
+ .debug_str     0x000000000000b4f2       0x4d ../hit_pat_bsp\libucosii_bsp.a(tcpcksum.o)
+                                       0x14e6 (size before relaxing)
+ .debug_str     0x000000000000b53f       0x48 ../hit_pat_bsp\libucosii_bsp.a(udp_open.o)
+                                       0x129a (size before relaxing)
+ .debug_str     0x000000000000b587       0xdb ../hit_pat_bsp\libucosii_bsp.a(in_pcb.o)
+                                       0x15e6 (size before relaxing)
+ .debug_str     0x000000000000b662      0x1d2 ../hit_pat_bsp\libucosii_bsp.a(vfsfiles.o)
+                                        0xe73 (size before relaxing)
+ .debug_str     0x000000000000b834       0x22 ../hit_pat_bsp\libucosii_bsp.a(vfsport.o)
+                                        0xc05 (size before relaxing)
+ .debug_str     0x000000000000b856       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+                                         0x5e (size before relaxing)
+ .debug_str     0x000000000000b874       0x1e ../hit_pat_bsp\libucosii_bsp.a(alt_fcntl.o)
+                                        0xcc3 (size before relaxing)
+ .debug_str     0x000000000000b892       0x26 ../hit_pat_bsp\libucosii_bsp.a(alt_find_file.o)
+                                        0xae2 (size before relaxing)
+ .debug_str     0x000000000000b8b8       0x30 ../hit_pat_bsp\libucosii_bsp.a(alt_get_fd.o)
+                                        0xb01 (size before relaxing)
+ .debug_str     0x000000000000b8e8      0x48b ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+                                        0x59d (size before relaxing)
+ .debug_str     0x000000000000bd73       0x80 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+                                        0x5e5 (size before relaxing)
+ .debug_str     0x000000000000bdf3       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+                                        0x5b6 (size before relaxing)
+ .debug_str     0x000000000000be4b       0x4b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+                                        0x5e6 (size before relaxing)
+ .debug_str     0x000000000000be96       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+                                        0x5c3 (size before relaxing)
+ .debug_str     0x000000000000beee       0x13 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+                                        0x777 (size before relaxing)
+ .debug_str     0x000000000000bf01       0x41 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+                                        0x5cb (size before relaxing)
+ .debug_str     0x000000000000bf42       0x43 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+                                        0x59e (size before relaxing)
+ .debug_str     0x000000000000bf85       0x5f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+                                        0x723 (size before relaxing)
+ .debug_str     0x000000000000bfe4       0x43 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+                                        0x5a9 (size before relaxing)
+ .debug_str     0x000000000000c027       0x43 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+                                        0x5b9 (size before relaxing)
+ .debug_str     0x000000000000c06a       0x45 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+                                        0x5a0 (size before relaxing)
+ .debug_str     0x000000000000c0af       0x5b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+                                        0x955 (size before relaxing)
+ .debug_str     0x000000000000c10a        0xc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+                                        0xc73 (size before relaxing)
+ .debug_str     0x000000000000c116       0x5b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+                                        0x718 (size before relaxing)
+ .debug_str     0x000000000000c171       0x52 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+                                        0x726 (size before relaxing)
+ .debug_str     0x000000000000c1c3       0x57 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+                                        0x603 (size before relaxing)
+ .debug_str     0x000000000000c21a       0x49 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+                                        0x5e3 (size before relaxing)
+ .debug_str     0x000000000000c263       0x19 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+                                        0xc05 (size before relaxing)
+ .debug_str     0x000000000000c27c       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+                                        0x724 (size before relaxing)
+ .debug_str     0x000000000000c2bc       0x2a ../hit_pat_bsp\libucosii_bsp.a(alt_exit.o)
+                                        0xa4c (size before relaxing)
+
+.debug_loc      0x0000000000000000    0x22905
+ *(.debug_loc)
+ .debug_loc     0x0000000000000000       0x3a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_loc     0x000000000000003a      0x119 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_loc     0x0000000000000153       0x91 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_loc     0x00000000000001e4      0x143 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_loc     0x0000000000000327       0x66 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_loc     0x000000000000038d     0x3749 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_loc     0x0000000000003ad6       0xd4 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_loc     0x0000000000003baa     0x2ed8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_loc     0x0000000000006a82      0x38e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_loc     0x0000000000006e10      0x2ea c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_loc     0x00000000000070fa      0x612 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_loc     0x000000000000770c      0x728 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_loc     0x0000000000007e34      0x23b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_loc     0x000000000000806f      0x21b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_loc     0x000000000000828a       0x25 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_loc     0x00000000000082af      0x224 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_loc     0x00000000000084d3      0xd58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_loc     0x000000000000922b      0x179 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_loc     0x00000000000093a4      0x31e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_loc     0x00000000000096c2      0x3c7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_loc     0x0000000000009a89      0x1b5 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_loc     0x0000000000009c3e     0x1f2a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_loc     0x000000000000bb68      0x307 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_loc     0x000000000000be6f     0x1747 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_loc     0x000000000000d5b6      0x116 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_loc     0x000000000000d6cc       0x89 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_loc     0x000000000000d755      0x43c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_loc     0x000000000000db91     0x2a50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_loc     0x00000000000105e1      0x201 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_loc     0x00000000000107e2       0xfa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_loc     0x00000000000108dc       0x89 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_loc     0x0000000000010965      0x317 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_loc     0x0000000000010c7c      0x179 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_loc     0x0000000000010df5      0x307 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_loc     0x00000000000110fc       0xc8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_loc     0x00000000000111c4       0x89 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_loc     0x000000000001124d      0x159 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_loc     0x00000000000113a6       0xfa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_loc     0x00000000000114a0      0x119 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_loc     0x00000000000115b9       0xfa c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_loc     0x00000000000116b3      0x145 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_loc     0x00000000000117f8       0xc8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_loc     0x00000000000118c0      0x2be c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_loc     0x0000000000011b7e       0xa9 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_loc     0x0000000000011c27     0x1577 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_loc     0x000000000001319e     0x1186 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_loc     0x0000000000014324      0x5f7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_loc     0x000000000001491b     0x1cba c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_loc     0x00000000000165d5     0x22bc c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_loc     0x0000000000018891       0xe2 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_loc     0x0000000000018973      0x174 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_loc     0x0000000000018ae7      0x166 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_loc     0x0000000000018c4d     0x12ec c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_loc     0x0000000000019f39     0x1e4b c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_loc     0x000000000001bd84       0x7a c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_loc     0x000000000001bdfe      0x139 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_loc     0x000000000001bf37      0x255 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_loc     0x000000000001c18c      0x278 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_loc     0x000000000001c404       0xbe c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_loc     0x000000000001c4c2       0x32 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_loc     0x000000000001c4f4       0x6f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_loc     0x000000000001c563       0x22 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_loc     0x000000000001c585       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_loc     0x000000000001c5e9      0x33e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_loc     0x000000000001c927       0x64 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_loc     0x000000000001c98b      0x192 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_loc     0x000000000001cb1d      0x152 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_loc     0x000000000001cc6f      0x180 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_loc     0x000000000001cdef      0x122 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_loc     0x000000000001cf11      0x16c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_loc     0x000000000001d07d      0x651 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_loc     0x000000000001d6ce     0x346f c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_loc     0x0000000000020b3d      0x102 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_loc     0x0000000000020c3f      0x14c c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_loc     0x0000000000020d8b       0xf7 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_loc     0x0000000000020e82      0x19e c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_loc     0x0000000000021020     0x1851 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_loc     0x0000000000022871       0x94 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
+
+.debug_macinfo
+ *(.debug_macinfo)
+
+.debug_weaknames
+ *(.debug_weaknames)
+
+.debug_funcnames
+ *(.debug_funcnames)
+
+.debug_typenames
+ *(.debug_typenames)
+
+.debug_varnames
+ *(.debug_varnames)
+
+.debug_alt_sim_info
+                0x0000000000000000       0x60
+ *(.debug_alt_sim_info)
+ .debug_alt_sim_info
+                0x0000000000000000       0x30 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_alt_sim_info
+                0x0000000000000030       0x30 ../hit_pat_bsp\libucosii_bsp.a(alt_busy_sleep.o)
+                0x0000000010000000                __alt_data_end = 0x10000000
+                0x0000000010000000                PROVIDE (__alt_stack_pointer = __alt_data_end)
+                [!provide]                        PROVIDE (__alt_stack_limit = __alt_stack_base)
+                0x000000000805e59c                PROVIDE (__alt_heap_start = end)
+                0x0000000010000000                PROVIDE (__alt_heap_limit = 0x10000000)
+OUTPUT(hit_pat.elf elf32-littlenios2)
+
+.debug_ranges   0x0000000000000000     0x21b8
+ .debug_ranges  0x0000000000000000       0x20 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+ .debug_ranges  0x0000000000000020       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getchar.o)
+ .debug_ranges  0x0000000000000038       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-printf.o)
+ .debug_ranges  0x0000000000000050       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putchar.o)
+ .debug_ranges  0x0000000000000068       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-puts.o)
+ .debug_ranges  0x0000000000000098       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strlen.o)
+ .debug_ranges  0x00000000000000a8      0x1c8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintf.o)
+ .debug_ranges  0x0000000000000270       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wsetup.o)
+ .debug_ranges  0x00000000000002a0       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-dtoa.o)
+ .debug_ranges  0x00000000000002b8       0x78 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fflush.o)
+ .debug_ranges  0x0000000000000330      0x130 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-findfp.o)
+ .debug_ranges  0x0000000000000460       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-freer.o)
+ .debug_ranges  0x0000000000000478       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fvwrite.o)
+ .debug_ranges  0x00000000000004a0       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fwalk.o)
+ .debug_ranges  0x00000000000004b8       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-getc.o)
+ .debug_ranges  0x0000000000000510       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-localeconv.o)
+ .debug_ranges  0x0000000000000530       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-makebuf.o)
+ .debug_ranges  0x0000000000000548       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mallocr.o)
+ .debug_ranges  0x0000000000000590       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memchr.o)
+ .debug_ranges  0x00000000000005a0       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcpy.o)
+ .debug_ranges  0x00000000000005b0       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memmove.o)
+ .debug_ranges  0x00000000000005c0       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memset.o)
+ .debug_ranges  0x00000000000005d0       0xe8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mprec.o)
+ .debug_ranges  0x00000000000006b8       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-putc.o)
+ .debug_ranges  0x0000000000000710      0x1a8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-reallocr.o)
+ .debug_ranges  0x00000000000008b8       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-rget.o)
+ .debug_ranges  0x00000000000008f8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sbrkr.o)
+ .debug_ranges  0x0000000000000908       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-stdio.o)
+ .debug_ranges  0x0000000000000938      0x1b0 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfiprintf.o)
+ .debug_ranges  0x0000000000000ae8       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wbuf.o)
+ .debug_ranges  0x0000000000000b28       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-writer.o)
+ .debug_ranges  0x0000000000000b38       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(closer.o)
+ .debug_ranges  0x0000000000000b48       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-callocr.o)
+ .debug_ranges  0x0000000000000ba0       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fclose.o)
+ .debug_ranges  0x0000000000000be8       0x58 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fputwc.o)
+ .debug_ranges  0x0000000000000c40       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-fstatr.o)
+ .debug_ranges  0x0000000000000c50       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-isattyr.o)
+ .debug_ranges  0x0000000000000c60       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-locale.o)
+ .debug_ranges  0x0000000000000c80       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-lseekr.o)
+ .debug_ranges  0x0000000000000c90       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-mbtowc_r.o)
+ .debug_ranges  0x0000000000000ca8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-readr.o)
+ .debug_ranges  0x0000000000000cb8       0x40 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-refill.o)
+ .debug_ranges  0x0000000000000cf8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcmp.o)
+ .debug_ranges  0x0000000000000d08       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wcrtomb.o)
+ .debug_ranges  0x0000000000000d20       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-wctomb_r.o)
+ .debug_ranges  0x0000000000000d38      0x1b8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_udivdi3.o)
+ .debug_ranges  0x0000000000000ef0      0x180 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_umoddi3.o)
+ .debug_ranges  0x0000000000001070       0x70 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(lib2-divmod.o)
+ .debug_ranges  0x00000000000010e0      0x2a8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(adddf3.o)
+ .debug_ranges  0x0000000000001388      0x1c8 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(divdf3.o)
+ .debug_ranges  0x0000000000001550       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(eqdf2.o)
+ .debug_ranges  0x0000000000001598       0x70 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(gedf2.o)
+ .debug_ranges  0x0000000000001608       0x70 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(ledf2.o)
+ .debug_ranges  0x0000000000001678      0x240 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(muldf3.o)
+ .debug_ranges  0x00000000000018b8      0x288 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(subdf3.o)
+ .debug_ranges  0x0000000000001b40       0x48 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(unorddf2.o)
+ .debug_ranges  0x0000000000001b88       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(fixdfsi.o)
+ .debug_ranges  0x0000000000001ba0       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatsidf.o)
+ .debug_ranges  0x0000000000001bf0       0x50 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(floatunsidf.o)
+ .debug_ranges  0x0000000000001c40       0x20 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1\libgcc.a(_clzsi2.o)
+ .debug_ranges  0x0000000000001c60       0x18 ../hit_pat_bsp\libucosii_bsp.a(altera_generic_quad_spi_controller.o)
+ .debug_ranges  0x0000000000001c78       0x30 ../hit_pat_bsp\libucosii_bsp.a(pktalloc.o)
+ .debug_ranges  0x0000000000001ca8       0x18 ../hit_pat_bsp\libucosii_bsp.a(nptcp.o)
+ .debug_ranges  0x0000000000001cc0       0x60 ../hit_pat_bsp\libucosii_bsp.a(tcp_in.o)
+ .debug_ranges  0x0000000000001d20       0x48 ../hit_pat_bsp\libucosii_bsp.a(tcp_out.o)
+ .debug_ranges  0x0000000000001d68       0x28 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_entry.o)
+ .debug_ranges  0x0000000000001d90       0x10 ../hit_pat_bsp\libucosii_bsp.a(alt_irq_handler.o)
+ .debug_ranges  0x0000000000001da0       0x30 ../hit_pat_bsp\libucosii_bsp.a(ipdemux.o)
+ .debug_ranges  0x0000000000001dd0       0x30 ../hit_pat_bsp\libucosii_bsp.a(udp.o)
+ .debug_ranges  0x0000000000001e00       0x30 ../hit_pat_bsp\libucosii_bsp.a(alt_exception_entry.o)
+ .debug_ranges  0x0000000000001e30       0x18 ../hit_pat_bsp\libucosii_bsp.a(alt_instruction_exception_entry.o)
+ .debug_ranges  0x0000000000001e48       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atexit.o)
+ .debug_ranges  0x0000000000001e58       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-atoi.o)
+ .debug_ranges  0x0000000000001e70       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-exit.o)
+ .debug_ranges  0x0000000000001e80       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malign.o)
+ .debug_ranges  0x0000000000001e90       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malignr.o)
+ .debug_ranges  0x0000000000001ea0       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-malloc.o)
+ .debug_ranges  0x0000000000001eb8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-memcmp.o)
+ .debug_ranges  0x0000000000001ec8       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-sprintf.o)
+ .debug_ranges  0x0000000000001ee0       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strchr.o)
+ .debug_ranges  0x0000000000001ef0       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strcpy.o)
+ .debug_ranges  0x0000000000001f00       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strncmp.o)
+ .debug_ranges  0x0000000000001f10       0x28 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-strtol.o)
+ .debug_ranges  0x0000000000001f38      0x198 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfprintf.o)
+ .debug_ranges  0x00000000000020d0       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vprintf.o)
+ .debug_ranges  0x00000000000020e8       0x18 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vsprintf.o)
+ .debug_ranges  0x0000000000002100       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__atexit.o)
+ .debug_ranges  0x0000000000002110       0x30 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-__call_atexit.o)
+ .debug_ranges  0x0000000000002140       0x68 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-svfiprintf.o)
+ .debug_ranges  0x00000000000021a8       0x10 c:/intelfpga_lite/19.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/8.3.1/../../../../../H-x86_64-mingw32/nios2-elf/lib\libc.a(lib_a-vfprintfr_1.o)
diff --git a/FPGA_nios/hit_pat/hit_pat.objdump b/FPGA_nios/hit_pat/hit_pat.objdump
new file mode 100644
index 0000000..ae87d1e
--- /dev/null
+++ b/FPGA_nios/hit_pat/hit_pat.objdump
@@ -0,0 +1,106020 @@
+
+hit_pat.elf:     file format elf32-littlenios2
+hit_pat.elf
+architecture: nios2:r1, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x08000338
+
+Program Header:
+    LOAD off    0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**12
+         filesz 0x0004cb8c memsz 0x0005e59c flags rwx
+    LOAD off    0x0004d000 vaddr 0x14000000 paddr 0x14000000 align 2**12
+         filesz 0x00000020 memsz 0x00000020 flags r-x
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .entry        00000020  14000000  14000000  0004d000  2**5
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .exceptions   00000218  08000120  08000120  00000120  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .text         00046670  08000338  08000338  00000338  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  3 .rodata       00004f6c  080469a8  080469a8  000469a8  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  4 .rwdata       0000126c  0804b920  0804b920  0004b920  2**4
+                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
+  5 .bss          00011a10  0804cb8c  0804cb8c  0004cb8c  2**2
+                  ALLOC, SMALL_DATA
+  6 .ddr3_ram     00000000  0805e59c  0805e59c  0004d020  2**0
+                  CONTENTS
+  7 .ext_flash_avl_mem 00000000  14000020  14000020  0004d020  2**0
+                  CONTENTS
+  8 .onchip_flash_data 00000000  18200000  18200000  0004d020  2**0
+                  CONTENTS
+  9 .descriptor_memory 00000000  18400000  18400000  0004d020  2**0
+                  CONTENTS
+ 10 .calibration_ram 00000000  18403400  18403400  0004d020  2**0
+                  CONTENTS
+ 11 .comment      0000002c  00000000  00000000  0004d020  2**0
+                  CONTENTS, READONLY
+ 12 .debug_aranges 00001c78  00000000  00000000  0004d050  2**3
+                  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_info   0010e51e  00000000  00000000  0004ecc8  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_abbrev 00021537  00000000  00000000  0015d1e6  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_line   0003ca4d  00000000  00000000  0017e71d  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_frame  00008900  00000000  00000000  001bb16c  2**2
+                  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_str    0000c2e6  00000000  00000000  001c3a6c  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 18 .debug_loc    00022905  00000000  00000000  001cfd52  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 19 .debug_alt_sim_info 00000060  00000000  00000000  001f2658  2**2
+                  CONTENTS, READONLY, DEBUGGING
+ 20 .debug_ranges 000021b8  00000000  00000000  001f26b8  2**3
+                  CONTENTS, READONLY, DEBUGGING
+ 21 .thread_model 00000006  00000000  00000000  001fec83  2**0
+                  CONTENTS, READONLY
+ 22 .cpu          00000003  00000000  00000000  001fec89  2**0
+                  CONTENTS, READONLY
+ 23 .qsys         00000001  00000000  00000000  001fec8c  2**0
+                  CONTENTS, READONLY
+ 24 .simulation_enabled 00000001  00000000  00000000  001fec8d  2**0
+                  CONTENTS, READONLY
+ 25 .sysid_hash   00000004  00000000  00000000  001fec8e  2**0
+                  CONTENTS, READONLY
+ 26 .sysid_base   00000004  00000000  00000000  001fec92  2**0
+                  CONTENTS, READONLY
+ 27 .sysid_time   00000004  00000000  00000000  001fec96  2**0
+                  CONTENTS, READONLY
+ 28 .stderr_dev   0000000a  00000000  00000000  001fec9a  2**0
+                  CONTENTS, READONLY
+ 29 .stdin_dev    0000000a  00000000  00000000  001feca4  2**0
+                  CONTENTS, READONLY
+ 30 .stdout_dev   0000000a  00000000  00000000  001fecae  2**0
+                  CONTENTS, READONLY
+ 31 .thread_model 00000006  00000000  00000000  001fecb8  2**0
+                  CONTENTS, READONLY
+ 32 .cpu          00000003  00000000  00000000  001fecbe  2**0
+                  CONTENTS, READONLY
+ 33 .qsys         00000001  00000000  00000000  001fecc1  2**0
+                  CONTENTS, READONLY
+ 34 .simulation_enabled 00000001  00000000  00000000  001fecc2  2**0
+                  CONTENTS, READONLY
+ 35 .sysid_hash   00000004  00000000  00000000  001fecc3  2**0
+                  CONTENTS, READONLY
+ 36 .sysid_base   00000004  00000000  00000000  001fecc7  2**0
+                  CONTENTS, READONLY
+ 37 .sysid_time   00000004  00000000  00000000  001feccb  2**0
+                  CONTENTS, READONLY
+ 38 .stderr_dev   0000000a  00000000  00000000  001feccf  2**0
+                  CONTENTS, READONLY
+ 39 .stdin_dev    0000000a  00000000  00000000  001fecd9  2**0
+                  CONTENTS, READONLY
+ 40 .stdout_dev   0000000a  00000000  00000000  001fece3  2**0
+                  CONTENTS, READONLY
+ 41 .sopc_system_name 00000005  00000000  00000000  001feced  2**0
+                  CONTENTS, READONLY
+ 42 .quartus_project_dir 0000001b  00000000  00000000  001fecf2  2**0
+                  CONTENTS, READONLY
+SYMBOL TABLE:
+14000000 l    d  .entry	00000000 .entry
+08000120 l    d  .exceptions	00000000 .exceptions
+08000338 l    d  .text	00000000 .text
+080469a8 l    d  .rodata	00000000 .rodata
+0804b920 l    d  .rwdata	00000000 .rwdata
+0804cb8c l    d  .bss	00000000 .bss
+0805e59c l    d  .ddr3_ram	00000000 .ddr3_ram
+14000020 l    d  .ext_flash_avl_mem	00000000 .ext_flash_avl_mem
+18200000 l    d  .onchip_flash_data	00000000 .onchip_flash_data
+18400000 l    d  .descriptor_memory	00000000 .descriptor_memory
+18403400 l    d  .calibration_ram	00000000 .calibration_ram
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_loc	00000000 .debug_loc
+00000000 l    d  .debug_alt_sim_info	00000000 .debug_alt_sim_info
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    df *ABS*	00000000 d:/hit20v3/software/hit_pat/software/hit_pat_bsp//obj/HAL/src/crt0.o
+0800037c l       .text	00000000 alt_after_alt_main
+00000000 l    df *ABS*	00000000 alt_irq_handler.c
+00000000 l    df *ABS*	00000000 alt_instruction_exception_entry.c
+00000000 l    df *ABS*	00000000 control.c
+0804cb8c l     O .bss	00000004 bytes_received.5850
+0804cb90 l     O .bss	00000006 header.5849
+0804cb98 l     O .bss	00000004 bytes_received.5856
+0804cd60 l     O .bss	00000020 packet_data.5855
+00000000 l    df *ABS*	00000000 main.c
+00000000 l    df *ABS*	00000000 network_utilities.c
+00000000 l    df *ABS*	00000000 sensor.c
+00000000 l    df *ABS*	00000000 socket_server.c
+0804cba8 l     O .bss	00000004 mutex
+0804cd80 l     O .bss	00000010 connections
+00000000 l    df *ABS*	00000000 tse_my_system.c
+00000000 l    df *ABS*	00000000 udpgen.c
+00000000 l    df *ABS*	00000000 utils.c
+00000000 l    df *ABS*	00000000 ctype_.c
+00000000 l    df *ABS*	00000000 getchar.c
+00000000 l    df *ABS*	00000000 impure.c
+0804ba80 l     O .rwdata	00000424 impure_data
+00000000 l    df *ABS*	00000000 printf.c
+00000000 l    df *ABS*	00000000 putchar.c
+00000000 l    df *ABS*	00000000 puts.c
+00000000 l    df *ABS*	00000000 strlen.c
+00000000 l    df *ABS*	00000000 vfprintf.c
+08004fbc l     F .text	000000c0 __sbprintf
+080474ae l     O .rodata	00000010 blanks.5226
+0804749e l     O .rodata	00000010 zeroes.5227
+00000000 l    df *ABS*	00000000 wsetup.c
+00000000 l    df *ABS*	00000000 dtoa.c
+080051dc l     F .text	00000210 quorem
+00000000 l    df *ABS*	00000000 fflush.c
+00000000 l    df *ABS*	00000000 findfp.c
+08006d64 l     F .text	00000008 __fp_lock
+08006d78 l     F .text	00000168 __sinit.part.0
+08006ee0 l     F .text	00000008 __fp_unlock
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 fvwrite.c
+00000000 l    df *ABS*	00000000 fwalk.c
+00000000 l    df *ABS*	00000000 getc.c
+00000000 l    df *ABS*	00000000 localeconv.c
+00000000 l    df *ABS*	00000000 makebuf.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 memchr.c
+00000000 l    df *ABS*	00000000 memcpy.c
+00000000 l    df *ABS*	00000000 memmove.c
+00000000 l    df *ABS*	00000000 memset.c
+00000000 l    df *ABS*	00000000 mprec.c
+080474d0 l     O .rodata	0000000c p05.4024
+00000000 l    df *ABS*	00000000 putc.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 rget.c
+00000000 l    df *ABS*	00000000 sbrkr.c
+00000000 l    df *ABS*	00000000 stdio.c
+00000000 l    df *ABS*	00000000 vfprintf.c
+0800a304 l     F .text	000000f4 __sprint_r.part.0
+0800b754 l     F .text	000000c0 __sbprintf
+08047604 l     O .rodata	00000010 blanks.5203
+080475f4 l     O .rodata	00000010 zeroes.5204
+00000000 l    df *ABS*	00000000 wbuf.c
+00000000 l    df *ABS*	00000000 writer.c
+00000000 l    df *ABS*	00000000 closer.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 fclose.c
+00000000 l    df *ABS*	00000000 fputwc.c
+00000000 l    df *ABS*	00000000 fstatr.c
+00000000 l    df *ABS*	00000000 int_errno.c
+00000000 l    df *ABS*	00000000 isattyr.c
+00000000 l    df *ABS*	00000000 locale.c
+00000000 l    df *ABS*	00000000 lseekr.c
+00000000 l    df *ABS*	00000000 mbtowc_r.c
+00000000 l    df *ABS*	00000000 readr.c
+00000000 l    df *ABS*	00000000 refill.c
+0800c03c l     F .text	0000001c lflush
+00000000 l    df *ABS*	00000000 strcmp.c
+00000000 l    df *ABS*	00000000 wcrtomb.c
+00000000 l    df *ABS*	00000000 wctomb_r.c
+00000000 l    df *ABS*	00000000 libgcc2.c
+00000000 l    df *ABS*	00000000 libgcc2.c
+00000000 l    df *ABS*	00000000 lib2-divmod.c
+00000000 l    df *ABS*	00000000 adddf3.c
+00000000 l    df *ABS*	00000000 divdf3.c
+00000000 l    df *ABS*	00000000 eqdf2.c
+00000000 l    df *ABS*	00000000 gedf2.c
+00000000 l    df *ABS*	00000000 ledf2.c
+00000000 l    df *ABS*	00000000 muldf3.c
+00000000 l    df *ABS*	00000000 subdf3.c
+00000000 l    df *ABS*	00000000 unorddf2.c
+00000000 l    df *ABS*	00000000 fixdfsi.c
+00000000 l    df *ABS*	00000000 floatsidf.c
+00000000 l    df *ABS*	00000000 floatunsidf.c
+00000000 l    df *ABS*	00000000 libgcc2.c
+00000000 l    df *ABS*	00000000 libgcc2.c
+00000000 l    df *ABS*	00000000 alt_flash_dev.c
+00000000 l    df *ABS*	00000000 alt_fstat.c
+0800f8a0 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_isatty.c
+0800f98c l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_lseek.c
+0800fa6c l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_main.c
+00000000 l    df *ABS*	00000000 alt_sbrk.c
+0804cad0 l     O .rwdata	00000004 heap_end
+00000000 l    df *ABS*	00000000 alt_env_lock.c
+0804cad4 l     O .rwdata	00000004 lockid
+0804cbd4 l     O .bss	00000004 locks
+00000000 l    df *ABS*	00000000 alt_malloc_lock.c
+0804cad8 l     O .rwdata	00000004 lockid
+0804cbdc l     O .bss	00000004 locks
+00000000 l    df *ABS*	00000000 os_core.c
+080113a0 l     F .text	0000003c OS_InitMisc
+080113dc l     F .text	0000006c OS_InitRdyList
+080114cc l     F .text	000000e4 OS_InitTCBList
+080112c0 l     F .text	000000e0 OS_InitEventList
+08011448 l     F .text	00000084 OS_InitTaskIdle
+08011734 l     F .text	0000006c OS_SchedNew
+00000000 l    df *ABS*	00000000 os_flag.c
+08012fb8 l     F .text	000000f4 OS_FlagTaskRdy
+08012d74 l     F .text	00000164 OS_FlagBlock
+00000000 l    df *ABS*	00000000 os_mem.c
+00000000 l    df *ABS*	00000000 os_mutex.c
+0801457c l     F .text	00000188 OSMutex_RdyAtPrio
+00000000 l    df *ABS*	00000000 os_q.c
+00000000 l    df *ABS*	00000000 os_sem.c
+00000000 l    df *ABS*	00000000 os_task.c
+00000000 l    df *ABS*	00000000 os_time.c
+00000000 l    df *ABS*	00000000 alt_sys_init.c
+08017794 l     F .text	00000034 alt_dev_reg
+0804c420 l     O .rwdata	000000d0 debug_uart
+0804c4f0 l     O .rwdata	000000dc ext_flash
+0804c5d0 l     O .rwdata	00000070 msgdma_rx
+0804c640 l     O .rwdata	00000070 msgdma_tx
+0804c6b0 l     O .rwdata	00000100 onchip_flash
+00000000 l    df *ABS*	00000000 altera_avalon_timer_sc.c
+08017a2c l     F .text	00000078 alt_avalon_timer_sc_irq
+00000000 l    df *ABS*	00000000 altera_avalon_tse.c
+0804cc26 l     O .bss	00000001 tse_system_count.5331
+0804cc27 l     O .bss	00000001 is_init.5413
+00000000 l    df *ABS*	00000000 altera_avalon_uart_fd.c
+00000000 l    df *ABS*	00000000 altera_avalon_uart_init.c
+0801ccb0 l     F .text	0000009c altera_avalon_uart_irq
+0801cd4c l     F .text	00000134 altera_avalon_uart_rxirq
+0801ce80 l     F .text	000001a0 altera_avalon_uart_txirq
+00000000 l    df *ABS*	00000000 altera_avalon_uart_read.c
+0801d074 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 altera_avalon_uart_write.c
+0801d318 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 altera_generic_quad_spi_controller.c
+0801d588 l     F .text	00000034 alt_flash_device_register
+0801e010 l     F .text	0000008c alt_qspi_poll_for_write_in_progress
+0801df74 l     F .text	0000009c alt_qspi_validate_read_write_arguments
+00000000 l    df *ABS*	00000000 altera_msgdma.c
+0801e09c l     F .text	0000003c alt_get_errno
+0801e0d8 l     F .text	00000094 alt_msgdma_write_standard_descriptor
+0801e16c l     F .text	0000012c alt_msgdma_write_extended_descriptor
+0801e298 l     F .text	00000184 alt_msgdma_irq
+0801e41c l     F .text	0000008c alt_msgdma_construct_standard_descriptor
+0801e4a8 l     F .text	00000154 alt_msgdma_construct_extended_descriptor
+0801e5fc l     F .text	0000033c alt_msgdma_descriptor_async_transfer
+0801e938 l     F .text	00000408 alt_msgdma_descriptor_sync_transfer
+0801f010 l     F .text	000000a4 alt_msgdma_construct_prefetcher_standard_descriptor
+0801f0b4 l     F .text	00000194 alt_msgdma_construct_prefetcher_extended_descriptor
+00000000 l    df *ABS*	00000000 altera_onchip_flash.c
+080201d8 l     F .text	00000034 alt_flash_device_register
+00000000 l    df *ABS*	00000000 ins_tse_mac.c
+00000000 l    df *ABS*	00000000 alt_iniche_close.c
+00000000 l    df *ABS*	00000000 alt_iniche_dev.c
+00000000 l    df *ABS*	00000000 alt_iniche_read.c
+00000000 l    df *ABS*	00000000 alt_iniche_write.c
+00000000 l    df *ABS*	00000000 et_arp.c
+0804cc2c l     O .bss	00000004 arp_timer
+0804cc34 l     O .bss	00000004 cachetime
+00000000 l    df *ABS*	00000000 iface.c
+00000000 l    df *ABS*	00000000 ipnet.c
+00000000 l    df *ABS*	00000000 ipstart.c
+0804cdb8 l     O .bss	0000003c closers
+0804cc58 l     O .bss	00000004 nclosers
+00000000 l    df *ABS*	00000000 igmp_cmn.c
+00000000 l    df *ABS*	00000000 bsdsock.c
+00000000 l    df *ABS*	00000000 cksum.c
+0804cb04 l     O .rwdata	00000004 cksum_select
+00000000 l    df *ABS*	00000000 in_utils.c
+0804cdf4 l     O .bss	00000018 tistring
+00000000 l    df *ABS*	00000000 netmain.c
+00000000 l    df *ABS*	00000000 tk_crnos.c
+00000000 l    df *ABS*	00000000 ping.c
+00000000 l    df *ABS*	00000000 pktalloc.c
+00000000 l    df *ABS*	00000000 q.c
+00000000 l    df *ABS*	00000000 asm_cksum.o
+08028cd0 l       .text	00000000 done
+08028b60 l       .text	00000000 asm1
+08028c8c l       .text	00000000 loop0
+08028b88 l       .text	00000000 loop
+08028ca8 l       .text	00000000 fold
+00000000 l    df *ABS*	00000000 brdutils.c
+0804cc8c l     O .bss	00000004 kbd_init.4507
+0804cc88 l     O .bss	00000004 cpu_statusreg
+00000000 l    df *ABS*	00000000 osportco.c
+00000000 l    df *ABS*	00000000 targnios.c
+00000000 l    df *ABS*	00000000 nptcp.c
+0804ccc0 l     O .bss	00000004 in_tcptick
+00000000 l    df *ABS*	00000000 rawsock.c
+00000000 l    df *ABS*	00000000 sockcall.c
+0802cf30 l     F .text	0000008c sockargs
+0802c26c l     F .text	000001e0 t_getname
+00000000 l    df *ABS*	00000000 socket.c
+00000000 l    df *ABS*	00000000 socket2.c
+00000000 l    df *ABS*	00000000 soselect.c
+00000000 l    df *ABS*	00000000 tcp_in.c
+00000000 l    df *ABS*	00000000 tcp_out.c
+0803492c l     F .text	000000cc bld_options
+00000000 l    df *ABS*	00000000 tcp_subr.c
+00000000 l    df *ABS*	00000000 tcp_timr.c
+00000000 l    df *ABS*	00000000 tcp_usr.c
+00000000 l    df *ABS*	00000000 tcpport.c
+00000000 l    df *ABS*	00000000 udpsock.c
+00000000 l    df *ABS*	00000000 alt_busy_sleep.c
+00000000 l    df *ABS*	00000000 alt_close.c
+080370b4 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_dcache_flush.c
+00000000 l    df *ABS*	00000000 alt_dev.c
+08037238 l     F .text	0000002c alt_dev_null_write
+00000000 l    df *ABS*	00000000 alt_dev_llist_insert.c
+08037264 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_do_ctors.c
+00000000 l    df *ABS*	00000000 alt_do_dtors.c
+00000000 l    df *ABS*	00000000 alt_errno.c
+00000000 l    df *ABS*	00000000 alt_find_dev.c
+00000000 l    df *ABS*	00000000 alt_iic.c
+00000000 l    df *ABS*	00000000 alt_iic_isr_register.c
+00000000 l    df *ABS*	00000000 alt_io_redirect.c
+08037728 l     F .text	000000b0 alt_open_fd
+00000000 l    df *ABS*	00000000 alt_irq_vars.c
+00000000 l    df *ABS*	00000000 alt_open.c
+08037854 l     F .text	0000003c alt_get_errno
+08037890 l     F .text	000000b8 alt_file_locked
+00000000 l    df *ABS*	00000000 alt_printf.c
+00000000 l    df *ABS*	00000000 alt_putchar.c
+00000000 l    df *ABS*	00000000 alt_read.c
+08037cf8 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_release_fd.c
+00000000 l    df *ABS*	00000000 alt_remap_cached.c
+00000000 l    df *ABS*	00000000 alt_tick.c
+00000000 l    df *ABS*	00000000 alt_uncached_free.c
+00000000 l    df *ABS*	00000000 alt_uncached_malloc.c
+00000000 l    df *ABS*	00000000 alt_usleep.c
+00000000 l    df *ABS*	00000000 alt_write.c
+08038230 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 altera_nios2_gen2_irq.c
+00000000 l    df *ABS*	00000000 os_cpu_a.o
+00000040 l       *ABS*	00000000 OSCtxSw_SWITCH_PC
+00000000 l    df *ABS*	00000000 os_cpu_c.c
+00000014 l       *ABS*	00000000 OSTCBNext_OFFSET
+00000032 l       *ABS*	00000000 OSTCBPrio_OFFSET
+00000000 l       *ABS*	00000000 OSTCBStkPtr_OFFSET
+00000000 l    df *ABS*	00000000 allports.c
+0804ccf8 l     O .bss	00000004 inside_pktdemux
+00000000 l    df *ABS*	00000000 timeouts.c
+08038b28 l     F .text	0000014c check_interval_timers
+0804cd04 l     O .bss	00000004 numtimers
+00000000 l    df *ABS*	00000000 tk_misc.c
+00000000 l    df *ABS*	00000000 alt_iniche_fcntl.c
+00000000 l    df *ABS*	00000000 icmp.c
+0804c940 l     O .rwdata	00000018 dsts
+00000000 l    df *ABS*	00000000 ip.c
+0804cb74 l     O .rwdata	00000004 uid
+00000000 l    df *ABS*	00000000 ipdemux.c
+00000000 l    df *ABS*	00000000 ipmc.c
+00000000 l    df *ABS*	00000000 ipport.c
+00000000 l    df *ABS*	00000000 ipraw.c
+00000000 l    df *ABS*	00000000 iproute.c
+00000000 l    df *ABS*	00000000 udp.c
+0804cd2c l     O .bss	00000002 usocket
+00000000 l    df *ABS*	00000000 igmp.c
+00000000 l    df *ABS*	00000000 igmp2.c
+00000000 l    df *ABS*	00000000 ipopt.c
+00000000 l    df *ABS*	00000000 u_mctest.c
+0804cb7c l     O .rwdata	00000004 iCounter.5304
+00000000 l    df *ABS*	00000000 memdev.c
+00000000 l    df *ABS*	00000000 parseip.c
+0804ce0c l     O .bss	0000001e nearBuf.4931
+00000000 l    df *ABS*	00000000 tcpcksum.c
+00000000 l    df *ABS*	00000000 udp_open.c
+00000000 l    df *ABS*	00000000 in_pcb.c
+00000000 l    df *ABS*	00000000 vfsfiles.c
+00000000 l    df *ABS*	00000000 vfsport.c
+00000000 l    df *ABS*	00000000 alt_fcntl.c
+080426b8 l     F .text	0000003c alt_get_errno
+00000000 l    df *ABS*	00000000 alt_find_file.c
+00000000 l    df *ABS*	00000000 alt_get_fd.c
+00000000 l    df *ABS*	00000000 atexit.c
+00000000 l    df *ABS*	00000000 atoi.c
+00000000 l    df *ABS*	00000000 exit.c
+00000000 l    df *ABS*	00000000 malign.c
+00000000 l    df *ABS*	00000000 mallocr.c
+00000000 l    df *ABS*	00000000 malloc.c
+00000000 l    df *ABS*	00000000 memcmp.c
+00000000 l    df *ABS*	00000000 sprintf.c
+00000000 l    df *ABS*	00000000 strchr.c
+00000000 l    df *ABS*	00000000 strcpy.c
+00000000 l    df *ABS*	00000000 strncmp.c
+00000000 l    df *ABS*	00000000 strtol.c
+080430e8 l     F .text	00000224 _strtol_l.isra.0
+00000000 l    df *ABS*	00000000 vfprintf.c
+0804b8e1 l     O .rodata	00000010 blanks.5207
+0804b8d1 l     O .rodata	00000010 zeroes.5208
+00000000 l    df *ABS*	00000000 vprintf.c
+00000000 l    df *ABS*	00000000 vsprintf.c
+00000000 l    df *ABS*	00000000 __atexit.c
+00000000 l    df *ABS*	00000000 __call_atexit.c
+00000000 l    df *ABS*	00000000 vfprintf.c
+0804b901 l     O .rodata	00000010 blanks.5187
+0804b8f1 l     O .rodata	00000010 zeroes.5188
+00000000 l    df *ABS*	00000000 vfprintfr_1.c
+00000000 l    df *ABS*	00000000 alt_exit.c
+0804cd5c g     O .bss	00000004 alt_instruction_exception_handler
+080200e8 g     F .text	0000003c alt_msgdma_standard_descriptor_async_transfer
+08002cb8 g     F .text	00000018 putchar
+0805e1c4 g     O .bss	00000014 soq
+18200000 g       *ABS*	00000000 __alt_mem_onchip_flash_data
+080097bc g     F .text	00000074 _mprec_log10
+0804cbac g     O .bss	00000001 to_sslistenertask
+08018c1c g     F .text	000000cc alt_tse_get_mac_info
+0800989c g     F .text	00000074 __any_on
+0800be3c g     F .text	00000058 _isatty_r
+080474dc g     O .rodata	00000028 __mprec_tinytens
+0803a2d4 g     F .text	00000714 ip_write_internal
+0800fb7c g     F .text	000000bc alt_main
+08042f60 g     F .text	0000008c strcpy
+08028748 g     F .text	000000ac pk_free
+08002cd0 g     F .text	000000cc _puts_r
+08000380 g     F .text	00000030 control_delay
+0805e370 g     O .bss	00000100 alt_irq
+08002a14 g     F .text	0000005c master_clock_enable
+0804c958 g     O .rwdata	00000009 rtp_priority
+0800bf24 g     F .text	00000064 _lseek_r
+08039d2c g     F .text	000002f0 icmp_timex
+08029cfc g     F .text	00000044 m_freem
+080421c0 g     F .text	00000048 vgetc
+08028e18 g     F .text	00000020 clock_c
+0804ccd8 g     O .bss	00000004 tcp_optionbuf
+08024088 g     F .text	0000006c if_getbynum
+08001d1c g     F .text	0000003c ss_reset_connection
+08013658 g     F .text	000000cc OS_MemInit
+08027c78 g     F .text	0000006c TK_OSTaskQuery
+08028b40 g       .text	00000000 asm_cksum
+0801c7dc g     F .text	000000f0 marvell_cfg_rgmii
+08017734 g     F .text	00000060 OSTimeSet
+080420c8 g     F .text	000000f8 vgetc_locked
+080295e8 g     F .text	00000020 post_task_setup
+080360cc g     F .text	00000118 tcp_attach
+0802b050 g     F .text	00000078 tcp_tick
+08026fbc g     F .text	0000007c print_ipad
+08027ba0 g     F .text	000000d8 tcp_wakeup
+0800e300 g     F .text	00000080 .hidden __eqdf2
+0804cba0 g     O .bss	00000004 last_flash_sector_offset
+0804cc5c g     O .bss	00000004 igmp_timers_are_running
+080333ec g     F .text	0000012c tcp_pulloutofband
+0801edf0 g     F .text	00000058 alt_msgdma_construct_standard_mm_to_mm_descriptor
+08019e30 g     F .text	000001d0 alt_tse_phy_print_profile
+080101d0 g     F .text	000005ac OSEventPendMulti
+08002314 g     F .text	000001b8 ethernet_read
+0805e59c g       *ABS*	00000000 __alt_heap_start
+080385a4 g     F .text	00000024 OSTaskCreateHook
+0801c57c g     F .text	00000098 marvell_phy_cfg
+0803b668 g     F .text	00000354 ip_rcv
+08041e68 g     F .text	00000154 vfseek
+0802f6ec g     F .text	00000108 soqremque
+0803d134 g     F .text	0000076c udpdemux
+08022984 g     F .text	000000dc tse_mac_close
+08002c78 g     F .text	00000038 printf
+0804cd0c g     O .bss	00000004 rt_mib
+080454d0 g     F .text	00000018 vsprintf
+080107cc g     F .text	0000004c OSIntEnter
+0800c2fc g     F .text	0000006c _wcrtomb_r
+0804ce2c g     O .bss	0000e000 InitialTaskStk
+0800a2a0 g     F .text	0000005c __sseek
+08007060 g     F .text	00000010 __sinit
+0803c3f8 g     F .text	0000010c in_delmulti
+0800b814 g     F .text	00000148 __swbuf_r
+0801c944 g     F .text	0000005c PEF7071_config
+0804cd18 g     O .bss	00000004 so_evtmap_create
+0804052c g     F .text	00000088 in_pcballoc
+18403400 g       *ABS*	00000000 __alt_mem_calibration_ram
+0804cb28 g     O .rwdata	00000002 socket_defaults
+0800be94 g     F .text	00000070 _setlocale_r
+08022f68 g     F .text	00000454 send_arp
+08006ee8 g     F .text	00000068 __sfmoreglue
+08040f88 g     F .text	00000338 vfopen_locked
+0800ff2c g     F .text	000000cc __malloc_unlock
+0805d5c8 g     O .bss	000000e0 eth_tse_if
+0803860c g     F .text	00000020 OSTaskStatHook
+08038a5c g     F .text	00000054 prep_modules
+08026574 g     F .text	00000190 bsd_i_sockoptlen
+0804cbe4 g     O .bss	00000001 OSLockNesting
+0801dd20 g     F .text	00000254 altera_qspi_controller_init
+08018e54 g     F .text	00000a78 getPHYSpeed
+080414cc g     F .text	00000044 vfclose
+0805e264 g     O .bss	0000002c tcb
+08037e88 g     F .text	00000034 alt_remap_cached
+0804cbe5 g     O .bss	00000001 OSRunning
+08023dd0 g     F .text	000002b8 grat_arp
+0800123c g     F .text	000001f8 get_ip_addr
+0803fce8 g     F .text	00000094 inet_pton
+080241c8 g     F .text	0000008c reg_type
+080254ec g     F .text	00000170 igmp_fasttimo
+08041678 g     F .text	0000005c vunlink_flag_open_files
+080024cc g     F .text	00000088 ethernet_close
+0805e290 g     O .bss	000000e0 tcpstat
+0802a22c g     F .text	00000098 dtom
+08034830 g     F .text	000000fc tcp_setpersist
+0802c60c g     F .text	00000188 t_getsockopt
+080087b8 g     F .text	0000012c memmove
+0802a658 g     F .text	00000588 ip_output
+08038658 g     F .text	00000020 OSInitHookBegin
+0803a01c g     F .text	00000054 icmp_du
+0804cb08 g     O .rwdata	00000004 num_net_tasks
+0804cd40 g     O .bss	00000004 vfiles
+0800704c g     F .text	00000014 _cleanup
+08002bc8 g     F .text	00000068 set_delay
+080089d4 g     F .text	000000a4 _Balloc
+080018b4 g     F .text	000001a0 get_board_mac_addr
+0801ed40 g     F .text	00000058 alt_msgdma_construct_standard_st_to_mm_descriptor
+0804cbe8 g     O .bss	00000004 OSIdleCtr
+0801b7f0 g     F .text	000001c4 alt_tse_phy_set_adv_1000
+0804cae0 g     O .rwdata	00000001 max_mac_system
+0803e7c4 g     F .text	000005a0 ip_setmoptions
+08018038 g     F .text	000008c4 alt_tse_system_add_sys
+0800e380 g     F .text	000000f0 .hidden __gtdf2
+0803f804 g     F .text	0000002c md_fseek
+08038364 g     F .text	00000024 altera_nios2_gen2_irq_init
+08038434 g       .text	00000000 OSStartTsk
+080118c4 g     F .text	000002d4 OS_TCBInit
+0805e58c g     O .bss	00000010 udp_mib
+14000000 g     F .entry	0000001c __reset
+0802cd9c g     F .text	000000d4 t_shutdown
+08007be8 g     F .text	00000008 __localeconv_l
+0802c870 g     F .text	0000013c t_recvfrom
+0803ef2c g     F .text	0000066c u_mctest_run
+0803c568 g     F .text	00000080 prep_ifaces
+0804cc78 g     O .bss	00000001 to_netmain
+08028434 g     F .text	000000c0 pk_alloc
+0804cbec g     O .bss	00000001 OSPrioHighRdy
+0800bddc g     F .text	00000060 _fstat_r
+0804b950 g     O .rwdata	00000130 tse_mac_device
+0802796c g     F .text	00000044 tk_nettick
+080385c8 g     F .text	00000024 OSTaskDelHook
+0804cbc0 g     O .bss	00000004 errno
+0800a15c g     F .text	00000010 __srget
+0800080c g     F .text	00000098 control_get_header
+080308f0 g     F .text	000000c4 in_pcbnotify
+0800a218 g     F .text	00000008 __seofread
+08038414 g       .text	00000000 OSStartHighRdy
+0805de58 g     O .bss	00000014 lilfreeq
+0803c610 g     F .text	0000002c evtmap_setup
+0801664c g     F .text	000001a4 OSTaskCreateExt
+0804cc7c g     O .bss	00000004 tcp_sleep_timeout
+080300b0 g     F .text	000001b8 sbdrop
+0804cd14 g     O .bss	00000004 net_system_exit
+08045850 g     F .text	00001120 ___svfiprintf_internal_r
+0805e4d4 g     O .bss	00000068 icmp_mib
+08035294 g     F .text	00000074 tcp_getseq
+0803c9e4 g     F .text	000000b8 ip_raw_alloc
+0801c0cc g     F .text	000004b0 alt_tse_phy_set_common_speed
+0801d87c g     F .text	00000210 alt_qspi_controller_write_block
+08012910 g     F .text	00000060 OSFlagPendGetFlagsRdy
+0804cbae g     O .bss	00000001 mastermode
+0805d6a8 g     O .bss	00000010 pmac_groups
+0802de94 g     F .text	00000758 soreceive
+08011b98 g     F .text	000002e0 OSFlagAccept
+08014c10 g     F .text	0000008c OSQFlush
+08014704 g     F .text	00000114 OSQAccept
+0804cbcc g     O .bss	00000004 alt_argv
+0800220c g     F .text	00000108 ethernet_write
+08054ab8 g       *ABS*	00000000 _gp
+0803811c g     F .text	00000114 usleep
+08041510 g     F .text	00000048 vfflush
+0805e16c g     O .bss	00000040 resid_semaphore
+08026e78 g     F .text	00000144 hexdump
+08025b04 g     F .text	00000080 igmp_leavegroup
+080164cc g     F .text	00000180 OSTaskCreate
+0801604c g     F .text	00000480 OSTaskChangePrio
+08021044 g     F .text	00000094 alt_onchip_flash_poll_for_status_write_passed
+0804cbe0 g     O .bss	00000004 alt_heapsem
+080350e8 g     F .text	000000e8 tcp_close
+080167f0 g     F .text	00000314 OSTaskDel
+080425e0 g     F .text	0000005c vferror
+080380a4 g     F .text	00000078 alt_uncached_malloc
+08013724 g     F .text	00000178 OSMutexAccept
+08017b50 g     F .text	00000060 tse_mac_initTransInfo2
+0801f8d8 g     F .text	0000014c alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits
+0803dcd8 g     F .text	000000bc udp_alloc
+0804c868 g     O .rwdata	000000c0 alt_fd_list
+0805ae2c g     O .bss	00000370 OSFlagTbl
+080010f0 g     F .text	00000034 control_init
+0804ccc4 g     O .bss	00000008 mbstat
+08007adc g     F .text	0000007c _getc_r
+08007b58 g     F .text	00000090 getc
+08002cb0 g     F .text	00000008 _putchar_r
+080110b0 g     F .text	000000b0 OS_EventTaskRemove
+0803e444 g     F .text	00000130 igmpv2_chk_set_timer
+080279b0 g     F .text	00000030 TK_OSTimeDly
+08037404 g     F .text	00000090 alt_find_dev
+080086b8 g     F .text	00000100 memcpy
+08017de0 g     F .text	00000054 tse_mac_setMIImode
+08038e5c g     F .text	0000007c task_stats
+0802ba20 g     F .text	00000050 DOMAIN_CHECK
+0802abe0 g     F .text	00000038 in_broadcast
+08027f0c g     F .text	0000029c icmpEcho
+080198cc g     F .text	00000048 alt_tse_phy_rd_mdio_addr
+0804cd3c g     O .bss	00000004 vfsystems
+0803dc28 g     F .text	000000b0 udp_socket
+0804cc4c g     O .bss	00000004 MaxMtu
+080305c8 g     F .text	00000140 sock_selscan
+08006d6c g     F .text	0000000c _cleanup_r
+0800f62c g     F .text	000000c8 .hidden __floatsidf
+08002a70 g     F .text	0000004c led_set
+0802f84c g     F .text	00000058 socantrcvmore
+08017bb0 g     F .text	000000c8 tse_mac_sTxWrite
+080377d8 g     F .text	0000007c alt_io_redirect
+0800e470 g     F .text	000000f0 .hidden __ltdf2
+0804cca0 g     O .bss	00000004 netq_intmask
+0803fc9c g     F .text	0000004c hextoa
+080469a8 g       *ABS*	00000000 __DTOR_END__
+0801fde4 g     F .text	000000b0 alt_msgdma_start_prefetcher_with_extd_desc_list
+08020124 g     F .text	0000003c alt_msgdma_extended_descriptor_async_transfer
+0802cb9c g     F .text	00000200 t_send
+080370f0 g     F .text	000000d0 alt_close
+08001124 g     F .text	00000054 InitialTask
+08020094 g     F .text	00000054 alt_msgdma_register_callback
+0804cccc g     O .bss	00000002 select_wait
+08002d9c g     F .text	00000010 puts
+08027500 g     F .text	00000044 std_out
+080429f8 g     F .text	00000098 alt_exception_cause_generated_bad_addr
+0805d6d8 g     O .bss	00000030 tse_iniche_dev_driver_data
+08042208 g     F .text	00000124 vfslookup_locked
+0802d74c g     F .text	00000098 soaccept
+0800fff8 g     F .text	000000d8 OSEventNameGet
+0805e1d8 g     O .bss	0000003c tcpmib
+0802cfbc g     F .text	00000094 t_errno
+0803c63c g     F .text	000000d8 ip_raw_open
+080004f8 g     F .text	00000314 control_process_config_peer
+08013cdc g     F .text	0000055c OSMutexPend
+08009714 g     F .text	000000a8 __ratio
+08010818 g     F .text	000000f0 OSIntExit
+0804cb78 g     O .rwdata	00000004 ipRoutes
+08041628 g     F .text	00000050 vfeof
+0800b73c g     F .text	00000018 __vfiprintf_internal
+08035564 g     F .text	0000005c tcp_canceltimers
+0804cbed g     O .bss	00000001 OSPrioCur
+08042c98 g     F .text	00000010 malloc
+0804cd38 g     O .bss	00000004 inpcb_cachemiss
+0801f540 g     F .text	000000f0 alt_msgdma_prefetcher_add_standard_desc_to_list
+08002c48 g     F .text	00000030 _printf_r
+0803fe5c g     F .text	000000c4 inet46_addr
+0804cd34 g     O .bss	00000004 inpcb_cachehits
+0800cff8 g     F .text	00000064 .hidden __udivsi3
+0804c828 g     O .rwdata	0000000b tcp_outflags
+0805d708 g     O .bss	00000290 tse
+0800f9c8 g     F .text	000000a4 isatty
+080188fc g     F .text	00000144 alt_tse_sys_enable_mdio_sharing
+08020fb0 g     F .text	00000094 alt_onchip_flash_poll_for_status_erase_passed
+0802144c g     F .text	00000078 msgdma_reset
+0804752c g     O .rodata	000000c8 __mprec_tens
+08040e00 g     F .text	00000070 vf_alloc_and_link_vop
+080251e4 g     F .text	00000068 exit_hook
+0804cc60 g     O .bss	00000004 igmp_cticks
+08018ba0 g     F .text	0000007c alt_tse_get_mac_info_index
+0804cbb0 g     O .bss	00000004 delays
+0804ccb4 g     O .bss	00000004 mheap_sem_ptr
+08033754 g     F .text	00000048 ip4_tcpmss
+0805da98 g     O .bss	00000014 netlist
+0802e5ec g     F .text	00000098 soshutdown
+08038388 g       .text	00000000 OSCtxSw
+080389e8 g     F .text	00000050 packet_check
+0805e214 g     O .bss	00000014 mbufq
+0802d6fc g     F .text	00000050 soabort
+0804cbbc g     O .bss	00000004 __malloc_top_pad
+0804caec g     O .rwdata	00000008 altera_onchip_flash_list
+0804cbf0 g     O .bss	00000004 OSTCBList
+08028a40 g     F .text	00000100 qdel
+08038850 g     F .text	00000160 station_state
+0803cb28 g     F .text	00000154 rt_lookup
+0804cce4 g     O .bss	00000004 alt_fd_list_lock
+08025b84 g     F .text	000002dc igmp_validate
+0801dc74 g     F .text	000000ac alt_qspi_controller_read
+08007bf0 g     F .text	0000000c _localeconv_r
+08024f80 g     F .text	00000264 ip_startup
+08022210 g     F .text	00000198 tse_msgdmaRx_isr
+0802bd24 g     F .text	00000250 t_accept
+0802f2ec g     F .text	00000098 soisdisconnecting
+08008dd4 g     F .text	00000034 __i2b
+080074c0 g     F .text	000004c4 __sfvwrite_r
+080249c4 g     F .text	000003a0 pktdemux
+0805b19c g     O .bss	00000c30 OSMemTbl
+0801996c g     F .text	0000012c alt_tse_phy_wr_mdio_reg
+08028d08 g     F .text	00000088 kbhit
+0802c44c g     F .text	000001c0 t_setsockopt
+0800a16c g     F .text	00000058 _sbrk_r
+0804c928 g     O .rwdata	00000018 icmpdu_types
+0801a000 g     F .text	00000698 alt_tse_mac_group_init
+080416d4 g     F .text	00000200 vunlink
+08002944 g     F .text	00000088 masterslave
+080214c4 g     F .text	00000a64 tse_mac_init
+14000000 g       *ABS*	00000000 __alt_mem_ext_flash_avl_mem
+08013a1c g     F .text	000002c0 OSMutexDel
+08026cd8 g     F .text	000000a4 ccksum
+08040e70 g     F .text	000000c8 vf_alloc_buffer
+0804cd28 g     O .bss	00000004 cachedRoute
+0804cb10 g     O .rwdata	00000004 lilbufs
+0803f830 g     F .text	00000024 md_ftell
+08026d7c g     F .text	00000054 cksum
+0801335c g     F .text	000000a8 OSMemNameGet
+0802d324 g     F .text	00000110 sofree
+0804cc54 g     O .bss	00000004 ifNumber
+0800bfd8 g     F .text	00000064 _read_r
+080371c0 g     F .text	00000078 alt_dcache_flush
+08020374 g     F .text	00000168 alt_onchip_flash_erase_block
+0801503c g     F .text	00000158 OSQPost
+080130ac g     F .text	000000a4 OS_FlagUnlink
+0804cb50 g     O .rwdata	00000004 alt_max_fd
+08011604 g     F .text	00000068 OS_MemCopy
+0804cb18 g     O .rwdata	00000004 bigbufs
+08017ce8 g     F .text	00000070 tse_mac_aTxWrite
+080361e4 g     F .text	000000cc tcp_disconnect
+0801166c g     F .text	000000c8 OS_Sched
+0800bae4 g     F .text	000000f8 _fclose_r
+08013298 g     F .text	000000c4 OSMemGet
+08016d64 g     F .text	0000015c OSTaskNameSet
+08006d3c g     F .text	00000028 fflush
+0804cbb8 g     O .bss	00000004 __malloc_max_sbrked_mem
+0804cbf4 g     O .bss	00000004 OSCtxSwCtr
+0805ddd0 g     O .bss	00000064 igmpstats
+0803862c g     F .text	0000002c OSTimeTickHook
+08026704 g     F .text	00000108 bsd_getsockopt
+08036418 g     F .text	000001a0 udp_soinput
+08028990 g     F .text	000000b0 putq
+08011160 g     F .text	000000f8 OS_EventTaskRemoveMulti
+080029cc g     F .text	00000048 master_clock_period
+0804cc74 g     O .bss	00000004 iniche_net_ready
+08002554 g     F .text	00000088 udpgen_command_bit
+0800d0b8 g     F .text	000009a0 .hidden __adddf3
+08010f68 g     F .text	00000148 OS_EventTaskWaitMulti
+08042598 g     F .text	00000048 isvfile
+0802e780 g     F .text	0000048c sosetopt
+08027814 g     F .text	000000e0 netmain
+0803379c g     F .text	000000f8 tcp_mss
+080094c8 g     F .text	00000104 __b2d
+0803f93c g     F .text	000002fc parse_ipad
+08040de0 g     F .text	00000020 get_vfopen_error
+0801f2a0 g     F .text	00000058 alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
+0800c9c0 g     F .text	00000540 .hidden __umoddi3
+0800faa8 g     F .text	000000d4 lseek
+08038ab0 g     F .text	00000078 inet_timer
+08015a60 g     F .text	000001e4 OSSemPend
+08019b68 g     F .text	000002c8 alt_tse_phy_add_profile_default
+0801b264 g     F .text	0000058c alt_tse_phy_get_cap
+0804cab8 g     O .rwdata	00000004 _global_impure_ptr
+080271c0 g     F .text	00000154 print_eth
+080412c0 g     F .text	00000050 vfopen
+08037d34 g     F .text	000000fc alt_read
+08009abc g     F .text	0000062c _realloc_r
+0805e59c g       *ABS*	00000000 __bss_end
+08037644 g     F .text	000000e4 alt_iic_isr_register
+08029bf8 g     F .text	00000104 m_free
+08043310 g     F .text	00000018 strtol_l
+080386b8 g     F .text	00000024 OSTCBInitHook
+08022944 g     F .text	00000040 tse_mac_stats
+080284f4 g     F .text	00000254 pk_validate
+08037f58 g     F .text	00000108 alt_tick
+0804b920 g     O .rwdata	00000018 controltask
+08040b60 g     F .text	00000254 in_pcblookup
+0801feec g     F .text	000001a8 alt_msgdma_init
+0800c428 g     F .text	00000598 .hidden __udivdi3
+08029a70 g     F .text	00000188 m_getnbuf
+08028814 g     F .text	000000c4 dump_buf_estats
+0800bd3c g     F .text	00000024 _fputwc_r
+0801b0dc g     F .text	00000188 alt_tse_phy_check_link
+0804cc44 g     O .bss	00000004 arpRepsOut
+08047504 g     O .rodata	00000028 __mprec_bigtens
+08008bb0 g     F .text	00000110 __s2b
+0800f6f4 g     F .text	0000009c .hidden __floatunsidf
+080386dc g     F .text	000000e8 netmain_init
+0801c6f8 g     F .text	000000e4 marvell_cfg_sgmii
+0801af18 g     F .text	000001c4 alt_tse_phy_restart_an
+08009258 g     F .text	00000058 __mcmp
+08001da8 g     F .text	000000e8 ss_handle_accept
+0801cb50 g     F .text	00000160 altera_avalon_uart_init
+0802019c g     F .text	0000003c alt_msgdma_extended_descriptor_sync_transfer
+08034b48 g     F .text	000003f8 tcp_respond
+080367f0 g     F .text	000002d0 udp4_sockbind
+0804cca4 g     O .bss	00000004 old_mode
+080258d8 g     F .text	0000022c igmp_joingroup
+0802ad08 g     F .text	00000348 so_icmpdu
+08007080 g     F .text	00000014 __fp_lock_all
+0804cd4c g     O .bss	00000004 vfs_dir_stale
+080375f8 g     F .text	0000004c alt_ic_irq_enabled
+0805d6b8 g     O .bss	00000020 pphy_profiles
+0804263c g     F .text	00000058 vclearerr
+08026bfc g     F .text	000000dc bsd_setsockopt
+080020d0 g     F .text	0000013c ethernet_listen
+0802a1d8 g     F .text	00000054 mbuf_len
+08012ed8 g     F .text	000000e0 OS_FlagInit
+08037ebc g     F .text	0000009c alt_alarm_stop
+08042374 g     F .text	000001cc strippath
+08027a54 g     F .text	0000014c tcp_sleep
+08043328 g     F .text	00000018 strtol
+080362b0 g     F .text	000000cc tcp_usrclosed
+18400000 g       *ABS*	00000000 __alt_mem_descriptor_memory
+0804cc90 g     O .bss	00000004 cticks_factor
+0804060c g     F .text	00000210 in_pcbbind
+0804cce8 g     O .bss	00000004 alt_irq_active
+080156d4 g     F .text	000000a0 OSSemAccept
+080134d8 g     F .text	000000b8 OSMemPut
+08013150 g     F .text	00000148 OSMemCreate
+080001fc g     F .exceptions	000000c8 alt_irq_handler
+0804c840 g     O .rwdata	00000028 alt_dev_null
+0801eed8 g     F .text	00000090 alt_msgdma_construct_extended_mm_to_st_descriptor
+0804cb2a g     O .rwdata	00000001 tcprexmtthresh
+08024254 g     F .text	00000090 if_killsocks
+0803a9e8 g     F .text	00000210 ip_write
+0803b9bc g     F .text	0000054c ip_rcv_phase2
+0802c228 g     F .text	00000044 t_getsockname
+0802bf74 g     F .text	00000270 t_connect
+0804cb24 g     O .rwdata	00000004 TCPTV_MSL
+0805de6c g     O .bss	00000010 memestats
+0801ae0c g     F .text	0000010c alt_tse_phy_init
+08028d90 g     F .text	00000050 getch
+0804ca38 g     O .rwdata	00000080 vfs_root_path
+0802c1e4 g     F .text	00000044 t_getpeername
+0802f9d8 g     F .text	00000088 soreserve
+08038388 g       .text	00000000 OSIntCtxSw
+0802982c g     F .text	00000034 npalloc
+0801fd34 g     F .text	000000b0 alt_msgdma_start_prefetcher_with_std_desc_list
+08008cc0 g     F .text	00000064 __hi0bits
+0804cd24 g     O .bss	00000004 ipraw_eps
+080281a8 g     F .text	0000028c pk_init
+0803f634 g     F .text	00000158 md_fread
+08022048 g     F .text	000001c8 tse_mac_raw_send
+0800f5ac g     F .text	00000080 .hidden __fixdfsi
+0805e470 g     O .bss	00000064 intimers
+0802fab0 g     F .text	0000004c sbrelease
+08030a34 g     F .text	000000e4 ifd_clr
+08030368 g     F .text	00000090 sbdroprecord
+08027314 g     F .text	0000007c uslash
+0803826c g     F .text	000000f8 alt_write
+0804cc40 g     O .bss	00000004 arpRepsIn
+08038c74 g     F .text	0000012c in_timerset
+0804cbf8 g     O .bss	00000004 OSTCBFreeList
+08015c44 g     F .text	00000140 OSSemPendAbort
+08033894 g     F .text	00000f9c tcp_output
+0804ccf4 g     O .bss	00000004 activehost
+0804cb48 g     O .rwdata	00000008 alt_dev_list
+0802761c g     F .text	000001f8 parse_args
+0804cca8 g     O .bss	00000004 global_TCPwakeup_setIndx
+08022c3c g     F .text	00000068 write
+08029860 g     F .text	00000040 npfree
+08009910 g     F .text	000000cc _putc_r
+08023624 g     F .text	000002c0 arpReply
+08026dfc g     F .text	0000007c nextarg
+0804cb84 g     O .rwdata	00000004 pton_error
+0805daac g     O .bss	00000014 rcvdq
+080309b4 g     F .text	00000080 tcp_notify
+0800f8dc g     F .text	000000b0 fstat
+0802d7e4 g     F .text	000000b8 soconnect
+0803cae0 g     F .text	00000048 ip_raw_maxalloc
+0800e470 g     F .text	000000f0 .hidden __ledf2
+0801c8cc g     F .text	00000078 DP83848C_link_status_read
+08040adc g     F .text	00000084 in_setpeeraddr
+08028de0 g     F .text	00000038 clock_init
+08041558 g     F .text	000000d0 vfgets
+08022cec g     F .text	00000180 et_send
+08008ff4 g     F .text	00000128 __pow5mult
+0800a410 g     F .text	0000132c ___vfiprintf_internal_r
+0800d05c g     F .text	0000005c .hidden __umodsi3
+0803fc38 g     F .text	00000064 inet_addr
+0802e684 g     F .text	000000fc sorflush
+08045458 g     F .text	0000001c vprintf
+0805df80 g     O .bss	000000fc global_tcb_ext
+0805dac0 g     O .bss	00000300 netstatic
+0802baf0 g     F .text	00000160 t_bind
+08040454 g     F .text	000000d8 udp_close
+0801f2f8 g     F .text	00000058 alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
+080293dc g     F .text	000001c0 alt_iniche_init
+0805e59c g       *ABS*	00000000 end
+08028ff4 g     F .text	00000080 UNLOCK_NET_RESOURCE
+08021220 g     F .text	0000022c prep_tse_mac
+0802c794 g     F .text	000000dc t_recv
+080418d4 g     F .text	00000188 vfread
+080248e4 g     F .text	000000e0 netclose
+08042ab0 g     F .text	0000000c _atoi_r
+0801d354 g     F .text	00000234 altera_avalon_uart_write
+08017e84 g     F .text	000001b4 alt_tse_phy_add_profile
+0804cb34 g     O .rwdata	00000004 tcp_keepintvl
+080002c4 g     F .exceptions	00000074 alt_instruction_exception_entry
+0804c7e0 g     O .rwdata	00000018 tcp_protosw
+080469a8 g       *ABS*	00000000 __CTOR_LIST__
+0804cd48 g     O .bss	00000004 vfopen_error
+10000000 g       *ABS*	00000000 __alt_stack_pointer
+0804ccdc g     O .bss	00000004 tcp_maxidle
+0804cd30 g     O .bss	00000004 firstudp
+08017aa4 g     F .text	0000007c alt_avalon_timer_sc_init
+0801caa0 g     F .text	00000060 altera_avalon_uart_write_fd
+0800f790 g     F .text	00000054 .hidden __clzsi2
+0801cb00 g     F .text	00000050 altera_avalon_uart_close_fd
+08007070 g     F .text	00000004 __sfp_lock_acquire
+080085d0 g     F .text	000000e8 memchr
+080115b0 g     F .text	00000054 OS_MemClr
+08002e44 g     F .text	00002160 ___vfprintf_internal_r
+08038458 g     F .text	0000014c OSTaskStkInit
+08042d44 g     F .text	00000054 _sprintf_r
+080202d8 g     F .text	0000009c alt_onchip_flash_get_info
+080071c4 g     F .text	000002fc _free_r
+0803e574 g     F .text	0000013c igmpv2_chk4_rtr_alert_opt
+08037a9c g     F .text	0000022c alt_printf
+080472d7 g     O .rodata	00000180 _ctype_b
+0800bf04 g     F .text	0000000c __locale_mb_cur_max
+0802ce70 g     F .text	000000c0 t_socketclose
+08010cd8 g     F .text	00000188 OS_EventTaskRdy
+080003b0 g     F .text	00000068 control_pong
+08045578 g     F .text	00000118 __call_exitprocs
+0800a0e8 g     F .text	00000074 __srget_r
+0805ddc0 g     O .bss	00000010 nets
+08028f38 g     F .text	000000bc LOCK_NET_RESOURCE
+080223a8 g     F .text	00000060 tse_msgdmaTx_isr
+080227f8 g     F .text	0000014c tse_mac_rcv
+0802ba70 g     F .text	00000080 t_socket
+0804cac0 g     O .rwdata	00000004 __malloc_sbrk_base
+08000338 g     F .text	00000048 _start
+08022ca4 g     F .text	00000048 etainit
+0804ccec g     O .bss	00000004 _alt_tick_rate
+08038a38 g     F .text	00000024 mcastlist
+08014c9c g     F .text	00000260 OSQPend
+0805de7c g     O .bss	000000f0 pktlog
+0803e170 g     F .text	00000114 igmpv2_process_report
+08030b8c g     F .text	00000074 ifd_isset
+0801d6cc g     F .text	0000008c alt_qspi_controller_get_info
+0803d020 g     F .text	00000114 del_route
+0801730c g     F .text	00000104 OSTimeDly
+080011e8 g     F .text	00000054 get_mac_addr
+0802d254 g     F .text	000000d0 solisten
+0800911c g     F .text	0000013c __lshift
+0804ccf0 g     O .bss	00000004 _alt_nticks
+0801ed98 g     F .text	00000058 alt_msgdma_construct_standard_mm_to_st_descriptor
+08019a98 g     F .text	000000d0 alt_tse_phy_rd_mdio_reg
+08022bcc g     F .text	00000070 read
+08017800 g     F .text	0000022c alt_sys_init
+08045690 g     F .text	000001c0 __ssprint_r
+080351d0 g     F .text	0000004c tcp_quench
+08002050 g     F .text	00000080 ethernet_init
+08027390 g     F .text	00000170 ns_printf
+080240f4 g     F .text	000000d4 isbcast
+08029074 g     F .text	00000240 TK_NEWTASK
+080454e8 g     F .text	00000090 __register_exitproc
+0804cbfc g     O .bss	00000001 OSTaskCtr
+0804cc24 g     O .bss	00000001 phy_profile_count
+08042fec g     F .text	000000fc strncmp
+08018b34 g     F .text	0000006c alt_tse_get_mac_group_index
+08017410 g     F .text	000000fc OSTimeDlyHMSM
+0803c714 g     F .text	000000bc ip_raw_close
+08008e08 g     F .text	000001ec __multiply
+0804c988 g     O .rwdata	000000b0 mdlist
+0802541c g     F .text	000000d0 igmp_input
+0803af6c g     F .text	000000bc ip_raw_write
+08041a5c g     F .text	000003ac vfwrite_locked
+0804cd90 g     O .bss	00000028 __malloc_current_mallinfo
+0803ff20 g     F .text	0000006c inet_setport
+080095cc g     F .text	00000148 __d2b
+08015d84 g     F .text	00000100 OSSemPost
+08033264 g     F .text	00000188 tcp_dooptions
+0802f1e8 g     F .text	00000104 soisconnected
+08010994 g     F .text	000000dc OSSchedUnlock
+0803c5e8 g     F .text	00000028 netexit
+08001434 g     F .text	00000194 get_serial_number
+0804cc70 g     O .bss	00000004 nettick_wakes
+08019914 g     F .text	00000058 alt_tse_phy_wr_mdio_addr
+0804ccd0 g     O .bss	00000001 tcpprintfs
+0803e064 g     F .text	0000010c igmpv2_input
+08038da0 g     F .text	00000098 in_timerkill
+08026dd0 g     F .text	0000002c do_trap
+08042920 g     F .text	000000d8 alt_get_fd
+0802680c g     F .text	000000f0 bsd_ioctl
+0804cc00 g     O .bss	00000004 OSMemFreeList
+0802a4a4 g     F .text	000001b4 tcp_rcv
+08027178 g     F .text	00000048 panic
+0804cd50 g     O .bss	00000004 vfs_open_files
+08024df4 g     F .text	0000018c ip2mac
+08036f5c g     F .text	00000158 alt_busy_sleep
+08012cdc g     F .text	00000098 OSFlagQuery
+08030708 g     F .text	000001e8 sock_select
+080349f8 g     F .text	00000048 tcp_init
+0804ccac g     O .bss	00000004 cticks
+0804cc79 g     O .bss	00000001 to_nettick
+0800b9d4 g     F .text	00000058 _close_r
+080242e4 g     F .text	000004d0 Netinit
+08029608 g     F .text	00000038 prep_armintcp
+0803c2ac g     F .text	0000014c in_addmulti
+08034a40 g     F .text	00000108 tcp_template
+0801bdb0 g     F .text	0000031c alt_tse_phy_get_common_speed
+0802a2c4 g     F .text	00000070 remque
+0804b938 g     O .rwdata	00000018 sslistenertask
+08045474 g     F .text	00000010 _vprintf_r
+08030c60 g     F .text	000003f0 tcp_reass
+080400c0 g     F .text	00000194 tcp_cksum
+08036ac0 g     F .text	00000374 udp4_socksend
+0801f248 g     F .text	00000058 alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
+08041310 g     F .text	000001bc vfclose_locked
+08030b18 g     F .text	00000074 ifd_set
+08042cb8 g     F .text	0000008c memcmp
+08010cb8 g     F .text	00000020 OS_Dummy
+0804cc50 g     O .bss	00000004 NDEBUG
+0805e59c g       *ABS*	00000000 __alt_stack_base
+0804cba4 g     O .bss	00000004 last_flash_sector
+0802fa60 g     F .text	00000050 sbreserve
+0804cc25 g     O .bss	00000001 mac_group_count
+0803c7d0 g     F .text	00000214 ip_raw_input
+0804cb14 g     O .rwdata	00000004 lilbufsiz
+08030c00 g     F .text	00000060 ifd_get
+0802f94c g     F .text	0000008c sbwakeup
+0801f350 g     F .text	000000a0 alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
+0800507c g     F .text	00000160 __swsetup_r
+080210d8 g     F .text	00000148 altera_eth_tse_init
+0805bdcc g     O .bss	000001e0 OSQTbl
+08033518 g     F .text	0000023c tcp_xmit_timer
+0800da58 g     F .text	000008a8 .hidden __divdf3
+0802020c g     F .text	000000cc alt_onchip_flash_read
+08006f50 g     F .text	000000fc __sfp
+08001780 g     F .text	00000134 generate_mac_addr
+0803a148 g     F .text	0000018c ip_bldhead
+08009830 g     F .text	0000006c __copybits
+0802fafc g     F .text	000000a0 sbappend
+0804bea4 g     O .rwdata	00000408 __malloc_av_
+0800707c g     F .text	00000004 __sinit_lock_release
+0804cc04 g     O .bss	00000004 OSTCBHighRdy
+0800e560 g     F .text	0000068c .hidden __muldf3
+0803abf8 g     F .text	00000374 ip_write2
+0800a1c4 g     F .text	00000054 __sread
+0804cafc g     O .rwdata	00000004 arp_ageout
+0804cc08 g     O .bss	00000004 OSQFreeList
+0801a698 g     F .text	0000040c alt_tse_mac_get_phy
+0803a070 g     F .text	000000d8 ip_init
+08042818 g     F .text	00000108 alt_find_file
+0803ca9c g     F .text	00000044 ip_raw_free
+0801d5bc g     F .text	00000110 alt_qspi_controller_lock
+08023528 g     F .text	000000fc make_arp_entry
+080372a0 g     F .text	000000a4 alt_dev_llist_insert
+0800fe0c g     F .text	00000120 __malloc_lock
+0800fc38 g     F .text	000000b0 sbrk
+08043340 g     F .text	00002118 ___svfprintf_internal_r
+080363bc g     F .text	0000005c udp_lookup
+080100d0 g     F .text	00000100 OSEventNameSet
+08006cdc g     F .text	00000060 _fflush_r
+08018dc8 g     F .text	0000008c alt_tse_mac_set_duplex
+0800ba2c g     F .text	000000b8 _calloc_r
+0802974c g     F .text	000000e0 npfree_base
+0804cc0c g     O .bss	00000001 OSRdyGrp
+08001c08 g     F .text	00000114 sensor_preconfigure
+0803f5e8 g     F .text	00000028 md_fopen
+0804c7f8 g     O .rwdata	00000018 udp_protosw
+0804cac8 g     O .rwdata	00000008 alt_flash_dev_list
+08021f28 g     F .text	00000120 tse_msgdma_write_init
+08040a58 g     F .text	00000084 in_setsockaddr
+0804cb8c g       *ABS*	00000000 __bss_start
+0802fb9c g     F .text	000000d8 sbappendrecord
+0805e53c g     O .bss	00000050 ip_mib
+080088e4 g     F .text	000000f0 memset
+0801fe94 g     F .text	00000058 alt_msgdma_open
+0802d89c g     F .text	00000098 sodisconnect
+08001178 g     F .text	00000070 main
+0804cbd0 g     O .bss	00000004 alt_envp
+0804cbb4 g     O .bss	00000004 __malloc_max_total_mem
+0801f630 g     F .text	00000198 alt_msgdma_prefetcher_add_extended_desc_to_list
+0802a018 g     F .text	000001c0 m_adj
+0800b95c g     F .text	00000014 __swbuf
+0803f854 g     F .text	000000c4 md_fgetc
+08047734 g     O .rodata	00000100 OSUnMapTbl
+0803b0cc g     F .text	000002a4 ip_dump
+08027d14 g     F .text	000001f8 tk_stats
+0804caf4 g     O .rwdata	00000008 alt_iniche_dev_list
+0804cc94 g     O .bss	00000004 OS_TPS
+0802b2e8 g     F .text	00000738 rawip_usrreq
+08012970 g     F .text	0000036c OSFlagPost
+0800a2fc g     F .text	00000008 __sclose
+0803fe00 g     F .text	0000005c print46_addr
+10000000 g       *ABS*	00000000 __alt_heap_limit
+0800bbdc g     F .text	00000010 fclose
+08010e60 g     F .text	00000108 OS_EventTaskWait
+0804330c g     F .text	00000004 _strtol_r
+08002c38 g     F .text	00000010 getchar
+08027038 g     F .text	00000140 print_uptime
+08016b04 g     F .text	00000128 OSTaskDelReq
+080053ec g     F .text	000016c8 _dtoa_r
+0801fa24 g     F .text	00000310 alt_msgdma_start_prefetcher_with_list_addr
+08007ddc g     F .text	000007f4 _malloc_r
+0803f918 g     F .text	00000024 md_unlink
+08017d58 g     F .text	00000088 tse_mac_SwReset
+0800c3f8 g     F .text	00000030 __ascii_wctomb
+08001e90 g     F .text	000001c0 SSListenerTask
+0801389c g     F .text	00000180 OSMutexCreate
+080405b4 g     F .text	00000058 in_pcbdetach
+0804cb54 g     O .rwdata	00000004 alt_errno
+0804cb80 g     O .rwdata	00000004 mdlist_size
+0801f488 g     F .text	000000b8 alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
+08010a70 g     F .text	00000068 OSStart
+08020f20 g     F .text	00000090 alt_onchip_flash_poll_for_status_to_go_idle
+0803eef8 g     F .text	00000034 u_mctest_init
+0800fdac g     F .text	00000060 __env_unlock
+08007984 g     F .text	000000a4 _fwalk
+08016ec0 g     F .text	000001b8 OSTaskResume
+08013590 g     F .text	000000c8 OSMemQuery
+0803ff8c g     F .text	00000134 convert_ip
+080233bc g     F .text	0000016c find_oldest_arp
+0804cc38 g     O .bss	00000004 arpReqsIn
+08040f38 g     F .text	00000050 vf_free_buffer
+0800bf88 g     F .text	0000000c _mbtowc_r
+080426f4 g     F .text	00000124 alt_fcntl
+08015194 g     F .text	00000160 OSQPostFront
+08028cd4 g     F .text	00000034 dtrap
+0804cb20 g     O .rwdata	00000004 kb_last
+080099dc g     F .text	000000e0 putc
+080025dc g     F .text	000001cc udpgen_test
+0800cf00 g     F .text	00000080 .hidden __divsi3
+08018a80 g     F .text	00000048 alt_tse_mac_set_common_speed
+0804cc0d g     O .bss	00000003 OSRdyTbl
+08029640 g     F .text	0000010c npalloc_base
+0802524c g     F .text	000000b0 ip_exit
+080070a8 g     F .text	0000011c _malloc_trim_r
+080469a8 g       *ABS*	00000000 __CTOR_END__
+08020a80 g     F .text	000004a0 altera_onchip_flash_init
+08000478 g     F .text	00000080 check_arp
+08028e38 g     F .text	0000005c cticks_hook
+080389b0 g     F .text	00000038 sysuptime
+0800c224 g     F .text	000000d8 strcmp
+080015c8 g     F .text	000001b8 generate_and_store_mac_addr
+08014818 g     F .text	000001a4 OSQCreate
+08028e94 g     F .text	00000060 irq_Mask
+08016c2c g     F .text	00000138 OSTaskNameGet
+0804ccfc g     O .bss	00000004 nextppp
+0804cc84 g     O .bss	00000004 irq_level
+08002904 g     F .text	00000040 reload_fpga
+080247b4 g     F .text	00000130 fixup_subnet_mask
+080152f4 g     F .text	000001fc OSQPostOpt
+08010ad8 g     F .text	000001c0 OSTimeTick
+0803b53c g     F .text	0000012c ip_copypkt
+080469a8 g       *ABS*	00000000 __DTOR_LIST__
+08015774 g     F .text	000000d8 OSSemCreate
+0804cc64 g     O .bss	00000004 igmp_all_hosts_group
+0802f8a4 g     F .text	0000003c sbselqueue
+0804cc6c g     O .bss	00000004 netmain_wakes
+08002b08 g     F .text	00000074 led_toggle
+08014430 g     F .text	0000014c OSMutexQuery
+080238e4 g     F .text	00000264 arprcv
+080279e0 g     F .text	00000074 TK_OSTaskResume
+08025e60 g     F .text	000003b4 igmp_print_stats
+0800e300 g     F .text	00000080 .hidden __nedf2
+08029914 g     F .text	00000090 pffindtype
+080027a8 g     F .text	00000098 swap_bytes
+0804cb38 g     O .rwdata	00000004 tcp_sendspace
+08041fbc g     F .text	0000010c vftell
+0805de34 g     O .bss	00000012 eth_prt_buf
+08015e84 g     F .text	000000f0 OSSemQuery
+080149bc g     F .text	00000254 OSQDel
+08014efc g     F .text	00000140 OSQPendAbort
+080177c8 g     F .text	00000038 alt_irq_init
+08018a40 g     F .text	00000040 alt_tse_mac_get_common_speed
+0805e1ac g     O .bss	00000018 app_semaphore
+08037e30 g     F .text	00000058 alt_release_fd
+08000000 g       *ABS*	00000000 __alt_mem_ddr3_ram
+08020160 g     F .text	0000003c alt_msgdma_standard_descriptor_sync_transfer
+08029368 g     F .text	00000074 post_app_sem
+0802537c g     F .text	000000a0 igmp_init
+08042af0 g     F .text	00000014 memalign
+08042d98 g     F .text	00000064 sprintf
+08047624 g     O .rodata	00000100 .hidden __clz_tab
+0803f78c g     F .text	00000078 md_fwrite
+0804cbc4 g     O .bss	00000004 _PathLocale
+0804cb0c g     O .rwdata	00000004 pingdata
+0804cc98 g     O .bss	00000004 tcp_sleep_count
+0802a334 g     F .text	0000007c insque
+08042a90 g     F .text	00000014 atexit
+0804cd44 g     O .bss	00000004 vfsfiles
+0800b970 g     F .text	00000064 _write_r
+08045484 g     F .text	0000004c _vsprintf_r
+0803d8a0 g     F .text	00000294 udp_send
+08010908 g     F .text	0000008c OSSchedLock
+0802565c g     F .text	0000027c igmp_send
+0800bf10 g     F .text	00000014 setlocale
+0801f3f0 g     F .text	00000098 alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
+08011e78 g     F .text	000000f8 OSFlagCreate
+08028ef4 g     F .text	00000044 irq_Unmask
+0802bc50 g     F .text	000000d4 t_listen
+0801c9a0 g     F .text	000000a0 PEF7071_link_status_read
+0804cabc g     O .rwdata	00000004 _impure_ptr
+08000950 g     F .text	00000714 control_step
+0804cbc8 g     O .bss	00000004 alt_argc
+08035a14 g     F .text	000006b8 tcp_usrreq
+080365b8 g     F .text	00000238 udp_usrreq
+080298a0 g     F .text	00000034 ncpalloc
+08006ab4 g     F .text	00000228 __sflush_r
+080373a4 g     F .text	00000060 _do_dtors
+0804cb6c g     O .rwdata	00000004 pingdelay
+08022ef4 g     F .text	00000074 arp_send_pending
+0803ddfc g     F .text	00000268 igmpv1_input
+0800c058 g     F .text	000001cc __srefill_r
+0802959c g     F .text	0000004c pre_task_setup
+0804ccb8 g     O .bss	00000004 rcvdq_sem_ptr
+08026454 g     F .text	00000120 bsd_getsockname
+08001a54 g     F .text	0000012c FindLastFlashSectorOffset
+08011f70 g     F .text	0000021c OSFlagDel
+0804cc10 g     O .bss	00000004 OSEventFreeList
+08000120 g       .exceptions	00000000 alt_irq_entry
+0804cc30 g     O .bss	00000004 arpcache
+08039a54 g     F .text	000002d8 icmp_destun
+0800bf94 g     F .text	00000044 __ascii_mbtowc
+0803c504 g     F .text	00000064 lookup_mcast
+0804232c g     F .text	00000048 vfslookup
+0803bf08 g     F .text	000003a4 ip_demux
+0800946c g     F .text	0000005c __ulp
+0804cc9c g     O .bss	00000004 tcp_wakeup_count
+08012378 g     F .text	00000598 OSFlagPend
+08007094 g     F .text	00000014 __fp_unlock_all
+080292b4 g     F .text	000000b4 wait_app_sem
+0804cb00 g     O .rwdata	00000004 ipmcfail_str
+0804ccb0 g     O .bss	00000004 memtrapsize
+08029d40 g     F .text	000002d8 m_copy
+0804cb40 g     O .rwdata	00000008 alt_fs_list
+0805e228 g     O .bss	00000014 mfreeq
+080204dc g     F .text	000002d8 alt_onchip_flash_write_block
+0801d758 g     F .text	00000124 alt_qspi_controller_erase_block
+080117a0 g     F .text	00000074 OS_StrCopy
+0802d1f8 g     F .text	0000005c sobind
+0804cadc g     O .rwdata	00000004 eth_tse_name
+0803f598 g     F .text	00000050 init_memdev
+0802a3b0 g     F .text	000000f4 nptcp_init
+08002abc g     F .text	0000004c led_clear
+0805e07c g     O .bss	000000f0 global_TCPwakeup_set
+08038678 g     F .text	00000020 OSInitHookEnd
+0802f384 g     F .text	000000c4 soisdisconnected
+08022e6c g     F .text	00000088 arp_free_pending
+08007bfc g     F .text	0000000c localeconv
+0802d434 g     F .text	000002c8 soclose
+0805df6c g     O .bss	00000014 bigfreeq
+08007c08 g     F .text	00000098 __swhatbuf_r
+0804cb68 g     O .rwdata	00000004 prompt
+0804cb30 g     O .rwdata	00000004 tcp_keepidle
+0801bc08 g     F .text	000001a8 alt_tse_phy_set_adv_10
+0802b124 g     F .text	000001c4 rawip_soinput
+08037494 g     F .text	00000050 alt_ic_isr_register
+08041e08 g     F .text	00000060 vfwrite
+0802f640 g     F .text	000000ac soqinsque
+0804cd1c g     O .bss	00000004 so_evtmap_delete
+0804cb8c g       *ABS*	00000000 _edata
+0801ca40 g     F .text	00000060 altera_avalon_uart_read_fd
+08022aa8 g     F .text	00000124 iniche_devices_init
+080207b4 g     F .text	000002cc alt_onchip_flash_write
+0805e23c g     O .bss	00000028 tcp_saveti
+08027544 g     F .text	000000d8 con_page
+0805e59c g       *ABS*	00000000 _end
+0802ec0c g     F .text	00000520 sogetopt
+08001064 g     F .text	0000008c ControlTask
+0800f7e4 g     F .text	00000068 alt_flash_open_dev
+0804cc14 g     O .bss	00000001 OSIntNesting
+08002c30 g     F .text	00000008 _getchar_r
+0801aaa4 g     F .text	00000240 alt_tse_mac_associate_phy
+0804c7b0 g     O .rwdata	00000030 nettasks
+080287f4 g     F .text	00000020 pk_get_max_intrsafe_buf_len
+0800bbec g     F .text	00000150 __fputwc
+0803b370 g     F .text	000001cc iproute
+0802ac18 g     F .text	000000f0 np_stripoptions
+0804cd20 g     O .bss	00000001 so_evtmap
+0801750c g     F .text	000001cc OSTimeDlyResume
+0803cc7c g     F .text	000003a4 add_route
+0801226c g     F .text	0000010c OSFlagNameSet
+08024d64 g     F .text	00000090 c_older
+0803002c g     F .text	00000084 sbflush
+0803f610 g     F .text	00000024 md_fclose
+08027ce4 g     F .text	00000030 tk_yield
+0803756c g     F .text	0000008c alt_ic_irq_disable
+0802d934 g     F .text	00000560 sosend
+0803b028 g     F .text	000000a4 ip_mymach
+0800a220 g     F .text	00000080 __swrite
+08002840 g     F .text	000000c4 swap_quad
+0804cc80 g     O .bss	00000004 cticks_initialized
+0804cb70 g     O .rwdata	00000004 deflength
+0802c9ac g     F .text	000001f0 t_sendto
+0804cac4 g     O .rwdata	00000004 __malloc_trim_threshold
+0804cc18 g     O .bss	00000004 OSTCBCur
+0802d050 g     F .text	000001a8 socreate
+08042abc g     F .text	00000034 exit
+0805d998 g     O .bss	00000100 arp_table
+08001b80 g     F .text	00000088 sensor_command_bit
+08014238 g     F .text	000001f8 OSMutexPost
+0804cd08 g     O .bss	00000004 icmpdu_hook
+08007a28 g     F .text	000000b4 _fwalk_reent
+0801f7c8 g     F .text	00000110 alt_msgdma_prefetcher_set_std_list_own_by_hw_bits
+08038e38 g     F .text	00000024 create_apptasks
+0804cb2c g     O .rwdata	00000004 tcp_ttl
+080092b0 g     F .text	000001bc __mdiff
+0800f84c g     F .text	00000054 alt_flash_close_dev
+080298d4 g     F .text	00000040 ncpfree
+0800cf80 g     F .text	00000078 .hidden __modsi3
+08042b04 g     F .text	00000194 _memalign_r
+0804cc48 g     O .bss	00000004 MaxLnh
+08017e34 g     F .text	00000050 tse_mac_setGMIImode
+0803fd7c g     F .text	00000084 inet_ntop
+0803dd94 g     F .text	00000024 udp_maxalloc
+0801c614 g     F .text	000000e4 marvell_cfg_gmii
+10000000 g       *ABS*	00000000 __alt_data_end
+08000120 g     F .exceptions	00000000 alt_exception
+08007074 g     F .text	00000004 __sfp_lock_release
+0801077c g     F .text	00000050 OSInit
+0801ef68 g     F .text	000000a8 alt_msgdma_construct_extended_mm_to_mm_descriptor
+0801ace4 g     F .text	00000128 alt_tse_phy_cfg_pcs
+08017220 g     F .text	000000ec OSTaskQuery
+080387c4 g     F .text	0000008c icmp_port_du
+0804cce0 g     O .bss	00000004 tcp_iss
+0801562c g     F .text	000000a8 OS_QInit
+08042aa4 g     F .text	0000000c atoi
+0804cb1c g     O .rwdata	00000004 bigbufsiz
+08011814 g     F .text	00000054 OS_StrLen
+0803521c g     F .text	00000078 tcp_putseq
+08013404 g     F .text	000000d4 OSMemNameSet
+080471d6 g     O .rodata	00000101 _ctype_
+0802fc74 g     F .text	000001dc sbappendaddr
+0804cd54 g     O .bss	00000004 vfs_total_rw_space
+0800f558 g     F .text	00000054 .hidden __unorddf2
+0803ed64 g     F .text	00000110 ip_getmoptions
+0801ee48 g     F .text	00000090 alt_msgdma_construct_extended_st_to_mm_descriptor
+0803db34 g     F .text	000000f4 udpswap
+0804cc1c g     O .bss	00000004 OSTime
+0804ccbc g     O .bss	00000004 nextslow
+08035308 g     F .text	0000025c tcp_slowtimo
+0801d020 g     F .text	00000054 altera_avalon_uart_close
+08034f40 g     F .text	0000010c tcp_newtcpcb
+08023b48 g     F .text	0000017c send_via_arp
+0805bfac g     O .bss	00000800 OSTaskIdleStk
+08046974 g     F .text	00000034 _exit
+08042540 g     F .text	00000058 isvfile_locked
+08026a74 g     F .text	00000188 bsd_select
+0801218c g     F .text	000000e0 OSFlagNameGet
+0803ddb8 g     F .text	00000044 udp_free
+080288d8 g     F .text	000000b8 getq
+08042694 g     F .text	00000024 prep_vfs
+080176d8 g     F .text	0000005c OSTimeGet
+0804cb64 g     O .rwdata	00000004 name
+08030268 g     F .text	00000100 sbdropend
+08007ca0 g     F .text	0000013c __smakebuf_r
+08023cc4 g     F .text	0000010c cb_arpent_tmo
+0804cae4 g     O .rwdata	00000008 alt_msgdma_list
+08002dac g     F .text	00000098 strlen
+0803e6b0 g     F .text	00000114 IPADDR_TO_NETP
+080268fc g     F .text	00000034 bsd_inet_ntoa
+080385ec g     F .text	00000020 OSTaskSwHook
+08037948 g     F .text	00000154 open
+08040254 g     F .text	00000200 udp_open
+0805c7ac g     O .bss	00000b40 OSEventTbl
+0802f7f4 g     F .text	00000058 socantsendmore
+0804cd58 g     O .bss	00000004 vfs_total_dyna_files
+0800e380 g     F .text	000000f0 .hidden __gedf2
+08038060 g     F .text	00000044 alt_uncached_free
+08037cc8 g     F .text	00000030 alt_putchar
+0805d2ec g     O .bss	00000288 OSTCBTbl
+0804cc3c g     O .bss	00000004 arpReqsOut
+08015f74 g     F .text	000000d8 OSSemSet
+0804cb88 g     O .rwdata	00000004 http_root_path
+0804cb9c g     O .bss	00000001 to_controltask
+0801da8c g     F .text	000001e8 alt_qspi_controller_write
+0800a3f8 g     F .text	00000018 __sprint_r
+08017c78 g     F .text	00000070 tse_mac_aRxRead
+08042dfc g     F .text	00000164 strchr
+0805de46 g     O .bss	00000012 ipreturn
+0804cd10 g     O .bss	00000004 port_prep
+0804c833 g     O .rwdata	0000000d tcp_backoff
+0802f178 g     F .text	00000070 soisconnecting
+080226c0 g     F .text	00000138 allocate_rx_descriptor_chain
+0804cb58 g     O .rwdata	00000004 alt_priority_mask
+0803e284 g     F .text	000001c0 igmpv2_process_query
+080303f8 g     F .text	000001d0 t_select
+08002b7c g     F .text	0000004c led4_blink_enable
+0801584c g     F .text	00000214 OSSemDel
+08000418 g     F .text	00000060 control_process_snapshot
+08036e34 g     F .text	00000128 udp4_sockaddr
+0804cc20 g     O .bss	00000004 OSFlagFreeList
+0804081c g     F .text	000001e0 in_pcbconnect
+0804ccd4 g     O .bss	00000004 dropline
+080374e4 g     F .text	00000088 alt_ic_irq_enable
+08004fa4 g     F .text	00000018 __vfprintf_internal
+080278f4 g     F .text	00000078 tk_netmain
+080409fc g     F .text	0000005c in_pcbdisconnect
+0805d574 g     O .bss	00000054 OSTCBPrioTbl
+0801d0b0 g     F .text	00000268 altera_avalon_uart_read
+0800c3ec g     F .text	0000000c _wctomb_r
+0800fce8 g     F .text	000000c4 __env_lock
+0804c964 g     O .rwdata	00000024 mdio
+08018ce8 g     F .text	000000e0 alt_tse_mac_set_speed
+08026214 g     F .text	00000120 bsd_accept
+0804cb3c g     O .rwdata	00000004 tcp_recvspace
+0800ebec g     F .text	0000096c .hidden __subdf3
+08046970 g     F .text	00000004 _vfprintf_r
+0803637c g     F .text	00000040 tcpinit
+0804cc68 g     O .bss	00000004 igmp_all_rtrs_group
+0802b0c8 g     F .text	0000005c rawip_lookup
+08038ed8 g     F .text	000000a0 fcntl
+080008a4 g     F .text	000000ac control_get_data
+08008d24 g     F .text	000000b0 __lo0bits
+0802fe50 g     F .text	000001dc sbcompress
+0804cb5c g     O .rwdata	00000008 alt_alarm_list
+0803504c g     F .text	0000009c tcp_drop
+08037344 g     F .text	00000060 _do_ctors
+0801b9b4 g     F .text	00000254 alt_tse_phy_set_adv_100
+080355c0 g     F .text	00000454 tcp_timers
+080252fc g     F .text	00000080 if_netnumber
+0803ee74 g     F .text	00000084 ip_freemoptions
+0802f12c g     F .text	0000004c sohasoutofband
+0800c368 g     F .text	00000084 wcrtomb
+08031050 g     F .text	00002214 tcp_input
+08026334 g     F .text	00000120 bsd_getpeername
+08026930 g     F .text	00000144 bsd_recvfrom
+08022a60 g     F .text	00000048 close
+0804cbd8 g     O .bss	00000004 alt_envsem
+0804c2ac g     O .rwdata	0000016c __global_locale
+08010c98 g     F .text	00000020 OSVersion
+08040db4 g     F .text	0000002c set_vfopen_error
+08022408 g     F .text	000002b8 tse_msgdma_read_init
+08018ac8 g     F .text	0000006c alt_tse_get_system_index
+0804c810 g     O .rwdata	00000018 rawip_protosw
+08001d58 g     F .text	00000050 ss_initialize_connection
+0802f8e0 g     F .text	0000006c sbwait
+08011258 g     F .text	00000068 OS_EventWaitListInit
+0804cd00 g     O .bss	00000004 port_1s_callout
+0800bd60 g     F .text	0000007c fputwc
+08038698 g     F .text	00000020 OSTaskIdleHook
+08042ca8 g     F .text	00000010 free
+08007078 g     F .text	00000004 __sinit_lock_acquire
+0804cc28 g     O .bss	00000001 number_of_tse_mac
+08008a9c g     F .text	00000114 __multadd
+08017078 g     F .text	000001a8 OSTaskSuspend
+08008a78 g     F .text	00000024 _Bfree
+08017b20 g     F .text	00000030 no_printf
+0802f448 g     F .text	000001f8 sonewconn
+08038f78 g     F .text	00000adc icmprcv
+080299a4 g     F .text	000000cc pffindproto
+08011868 g     F .text	0000005c OS_TaskIdle
+080154f0 g     F .text	0000013c OSQQuery
+
+
+
+Disassembly of section .entry:
+
+14000000 <__reset>:
+#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
+    /* Assume the instruction cache size is always a power of two. */
+#if NIOS2_ICACHE_SIZE > 0x8000
+    movhi r2, %hi(NIOS2_ICACHE_SIZE)
+#else
+    movui r2, NIOS2_ICACHE_SIZE
+14000000:	00820014 	movui	r2,2048
+#endif
+
+0:
+    initi r2
+14000004:	1001483a 	initi	r2
+    addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
+14000008:	10bff804 	addi	r2,r2,-32
+    bgt r2, zero, 0b
+1400000c:	00bffd16 	blt	zero,r2,14000004 <__reset+0x4>
+ * Jump to the _start entry point in the .text section if reset code
+ * is allowed or if optimizing for RTL simulation.
+ */
+#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
+    /* Jump to the _start entry point in the .text section. */
+    movhi r1, %hi(_start)
+14000010:	00420034 	movhi	at,2048
+    ori r1, r1, %lo(_start)
+14000014:	0840ce14 	ori	at,at,824
+    jmp r1
+14000018:	0800683a 	jmp	at
+1400001c:	00000000 	call	10000000 <__alt_data_end>
+
+Disassembly of section .exceptions:
+
+08000120 <alt_exception>:
+
+#else /* ALT_EXCEPTION_STACK disabled */
+        /* 
+         * Reserve space on normal stack for registers about to be pushed.
+         */
+        addi  sp, sp, -76
+ 8000120:	deffed04 	addi	sp,sp,-76
+         * documentation for details).
+         *
+         * Leave a gap in the stack frame at 4(sp) for the muldiv handler to
+         * store zero into.
+         */
+        stw   ra,  0(sp)
+ 8000124:	dfc00015 	stw	ra,0(sp)
+        stw   r1,   8(sp)
+ 8000128:	d8400215 	stw	at,8(sp)
+        stw   r2,  12(sp)
+ 800012c:	d8800315 	stw	r2,12(sp)
+        stw   r3,  16(sp)
+ 8000130:	d8c00415 	stw	r3,16(sp)
+        stw   r4,  20(sp)
+ 8000134:	d9000515 	stw	r4,20(sp)
+        stw   r5,  24(sp)
+ 8000138:	d9400615 	stw	r5,24(sp)
+        stw   r6,  28(sp)
+ 800013c:	d9800715 	stw	r6,28(sp)
+        stw   r7,  32(sp)
+ 8000140:	d9c00815 	stw	r7,32(sp)
+        rdctl r5, estatus   /* Read early to avoid usage stall */
+ 8000144:	000b307a 	rdctl	r5,estatus
+        stw   r8,  36(sp)
+ 8000148:	da000915 	stw	r8,36(sp)
+        stw   r9,  40(sp)
+ 800014c:	da400a15 	stw	r9,40(sp)
+        stw   r10, 44(sp)
+ 8000150:	da800b15 	stw	r10,44(sp)
+        stw   r11, 48(sp)
+ 8000154:	dac00c15 	stw	r11,48(sp)
+        stw   r12, 52(sp)
+ 8000158:	db000d15 	stw	r12,52(sp)
+        stw   r13, 56(sp)
+ 800015c:	db400e15 	stw	r13,56(sp)
+        stw   r14, 60(sp)
+ 8000160:	db800f15 	stw	r14,60(sp)
+        stw   r15, 64(sp)
+ 8000164:	dbc01015 	stw	r15,64(sp)
+        /*
+         * ea-4 contains the address of the instruction being executed
+         * when the exception occured. For interrupt exceptions, we will
+         * will be re-issue the isntruction. Store it in 72(sp)
+         */
+        stw   r5,  68(sp)  /* estatus */
+ 8000168:	d9401115 	stw	r5,68(sp)
+        addi  r15, ea, -4  /* instruction that caused exception */
+ 800016c:	ebffff04 	addi	r15,ea,-4
+        stw   r15,  72(sp)
+ 8000170:	dbc01215 	stw	r15,72(sp)
+#else
+        /*
+         * Test to see if the exception was a software exception or caused 
+         * by an external interrupt, and vector accordingly.
+         */
+        rdctl r4, ipending
+ 8000174:	0009313a 	rdctl	r4,ipending
+        andi  r2, r5, 1
+ 8000178:	2880004c 	andi	r2,r5,1
+        beq   r2, zero, .Lnot_irq
+ 800017c:	10000326 	beq	r2,zero,800018c <alt_exception+0x6c>
+        beq   r4, zero, .Lnot_irq
+ 8000180:	20000226 	beq	r4,zero,800018c <alt_exception+0x6c>
+        /*
+         * Now that all necessary registers have been preserved, call 
+         * alt_irq_handler() to process the interrupts.
+         */
+
+        call alt_irq_handler
+ 8000184:	80001fc0 	call	80001fc <alt_irq_handler>
+
+        .section .exceptions.irqreturn, "xa"
+
+        br    .Lexception_exit
+ 8000188:	00000706 	br	80001a8 <alt_exception+0x88>
+         * upon completion, so we write ea (address of instruction *after*
+         * the one where the exception occured) into 72(sp). The actual
+         * instruction that caused the exception is written in r2, which these
+         * handlers will utilize.
+         */
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
+ 800018c:	df401215 	stw	ea,72(sp)
+.Lunknown_16bit:
+        addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
+        stw r4, 72(sp)
+
+#else /* CDX is not Enabled and all instructions are 32bits */
+        ldw r2, -4(ea) /* Instruction value that caused exception */
+ 8000190:	e8bfff17 	ldw	r2,-4(ea)
+         * debugger is present) or go into an infinite loop since the
+         * handling behavior is undefined; in that case we will not return here.
+         */
+
+        /* Load exception-causing address as first argument (r4) */
+        addi   r4, ea, -4
+ 8000194:	e93fff04 	addi	r4,ea,-4
+
+        /* Call the instruction-exception entry */
+        call   alt_instruction_exception_entry
+ 8000198:	80002c40 	call	80002c4 <alt_instruction_exception_entry>
+         * instruction
+         *
+         * Return code was 0: Skip. The instruction after the exception is
+         * already stored in 72(sp).
+         */
+        bne   r2, r0, .Lexception_exit
+ 800019c:	1000021e 	bne	r2,zero,80001a8 <alt_exception+0x88>
+
+        /*
+         * Otherwise, modify 72(sp) to re-issue the instruction that caused the
+         * exception.
+         */
+        addi  r15, ea, -4  /* instruction that caused exception */
+ 80001a0:	ebffff04 	addi	r15,ea,-4
+        stw   r15,  72(sp)
+ 80001a4:	dbc01215 	stw	r15,72(sp)
+        /* 
+         * Restore the saved registers, so that all general purpose registers 
+         * have been restored to their state at the time the interrupt occured.
+         */
+
+        ldw   r5,  68(sp)
+ 80001a8:	d9401117 	ldw	r5,68(sp)
+        ldw   ea,  72(sp)  /* This becomes the PC once eret is executed */
+ 80001ac:	df401217 	ldw	ea,72(sp)
+        ldw   ra,   0(sp)
+ 80001b0:	dfc00017 	ldw	ra,0(sp)
+
+        wrctl estatus, r5
+ 80001b4:	2801707a 	wrctl	estatus,r5
+
+        ldw   r1,   8(sp)
+ 80001b8:	d8400217 	ldw	at,8(sp)
+        ldw   r2,  12(sp)
+ 80001bc:	d8800317 	ldw	r2,12(sp)
+        ldw   r3,  16(sp)
+ 80001c0:	d8c00417 	ldw	r3,16(sp)
+        ldw   r4,  20(sp)
+ 80001c4:	d9000517 	ldw	r4,20(sp)
+        ldw   r5,  24(sp)
+ 80001c8:	d9400617 	ldw	r5,24(sp)
+        ldw   r6,  28(sp)
+ 80001cc:	d9800717 	ldw	r6,28(sp)
+        ldw   r7,  32(sp)
+ 80001d0:	d9c00817 	ldw	r7,32(sp)
+
+#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
+        ldw   et, %gprel(alt_exception_old_stack_limit)(gp)
+#endif
+
+        ldw   r8,  36(sp)
+ 80001d4:	da000917 	ldw	r8,36(sp)
+        ldw   r9,  40(sp)
+ 80001d8:	da400a17 	ldw	r9,40(sp)
+        ldw   r10, 44(sp)
+ 80001dc:	da800b17 	ldw	r10,44(sp)
+        ldw   r11, 48(sp)
+ 80001e0:	dac00c17 	ldw	r11,48(sp)
+        ldw   r12, 52(sp)
+ 80001e4:	db000d17 	ldw	r12,52(sp)
+        ldw   r13, 56(sp)
+ 80001e8:	db400e17 	ldw	r13,56(sp)
+        ldw   r14, 60(sp)
+ 80001ec:	db800f17 	ldw	r14,60(sp)
+        ldw   r15, 64(sp)
+ 80001f0:	dbc01017 	ldw	r15,64(sp)
+        stw   et, %gprel(alt_stack_limit_value)(gp)
+        stw   zero, %gprel(alt_exception_old_stack_limit)(gp)
+#endif /* ALT_STACK_CHECK */
+        ldw   sp,  76(sp)
+#else /* ALT_EXCEPTION_STACK disabled */
+        addi  sp, sp, 76
+ 80001f4:	dec01304 	addi	sp,sp,76
+
+        /*
+         * Return to the interrupted instruction.
+         */
+
+        eret
+ 80001f8:	ef80083a 	eret
+
+080001fc <alt_irq_handler>:
+ * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined.
+ */
+
+void alt_irq_handler (void) __attribute__ ((section (".exceptions")));
+void alt_irq_handler (void)
+{
+ 80001fc:	defff904 	addi	sp,sp,-28
+ 8000200:	dfc00615 	stw	ra,24(sp)
+ 8000204:	df000515 	stw	fp,20(sp)
+ 8000208:	df000504 	addi	fp,sp,20
+  
+  /*
+   * Notify the operating system that we are at interrupt level.
+   */ 
+  
+  ALT_OS_INT_ENTER();
+ 800020c:	80107cc0 	call	80107cc <OSIntEnter>
+#ifndef NIOS2_EIC_PRESENT
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
+{
+  alt_u32 active;
+
+  NIOS2_READ_IPENDING (active);
+ 8000210:	0005313a 	rdctl	r2,ipending
+ 8000214:	e0bffc15 	stw	r2,-16(fp)
+
+  return active;
+ 8000218:	e0bffc17 	ldw	r2,-16(fp)
+   * Consider the case where the high priority interupt is asserted during
+   * the interrupt entry sequence for a lower priority interrupt to see why
+   * this is the case.
+   */
+
+  active = alt_irq_pending ();
+ 800021c:	e0bfff15 	stw	r2,-4(fp)
+
+  do
+  {
+    i = 0;
+ 8000220:	e03ffd15 	stw	zero,-12(fp)
+    mask = 1;
+ 8000224:	00800044 	movi	r2,1
+ 8000228:	e0bffe15 	stw	r2,-8(fp)
+     * called to clear the interrupt condition.
+     */
+
+    do
+    {
+      if (active & mask)
+ 800022c:	e0ffff17 	ldw	r3,-4(fp)
+ 8000230:	e0bffe17 	ldw	r2,-8(fp)
+ 8000234:	1884703a 	and	r2,r3,r2
+ 8000238:	10001126 	beq	r2,zero,8000280 <alt_irq_handler+0x84>
+      { 
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+        alt_irq[i].handler(alt_irq[i].context); 
+ 800023c:	e0bffd17 	ldw	r2,-12(fp)
+ 8000240:	100690fa 	slli	r3,r2,3
+ 8000244:	008201b4 	movhi	r2,2054
+ 8000248:	1885883a 	add	r2,r3,r2
+ 800024c:	10f8dc17 	ldw	r3,-7312(r2)
+ 8000250:	e0bffd17 	ldw	r2,-12(fp)
+ 8000254:	100890fa 	slli	r4,r2,3
+ 8000258:	008201b4 	movhi	r2,2054
+ 800025c:	2085883a 	add	r2,r4,r2
+ 8000260:	10b8dd17 	ldw	r2,-7308(r2)
+ 8000264:	1009883a 	mov	r4,r2
+ 8000268:	183ee83a 	callr	r3
+#else
+        alt_irq[i].handler(alt_irq[i].context, i); 
+#endif
+        break;
+ 800026c:	0001883a 	nop
+  NIOS2_READ_IPENDING (active);
+ 8000270:	0005313a 	rdctl	r2,ipending
+ 8000274:	e0bffb15 	stw	r2,-20(fp)
+  return active;
+ 8000278:	e0bffb17 	ldw	r2,-20(fp)
+ 800027c:	00000706 	br	800029c <alt_irq_handler+0xa0>
+      }
+      mask <<= 1;
+ 8000280:	e0bffe17 	ldw	r2,-8(fp)
+ 8000284:	1085883a 	add	r2,r2,r2
+ 8000288:	e0bffe15 	stw	r2,-8(fp)
+      i++;
+ 800028c:	e0bffd17 	ldw	r2,-12(fp)
+ 8000290:	10800044 	addi	r2,r2,1
+ 8000294:	e0bffd15 	stw	r2,-12(fp)
+      if (active & mask)
+ 8000298:	003fe406 	br	800022c <alt_irq_handler+0x30>
+
+    } while (1);
+
+    active = alt_irq_pending ();
+ 800029c:	e0bfff15 	stw	r2,-4(fp)
+    
+  } while (active);
+ 80002a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80002a4:	103fde1e 	bne	r2,zero,8000220 <alt_irq_handler+0x24>
+
+  /*
+   * Notify the operating system that interrupt processing is complete.
+   */ 
+
+  ALT_OS_INT_EXIT();
+ 80002a8:	80108180 	call	8010818 <OSIntExit>
+}
+ 80002ac:	0001883a 	nop
+ 80002b0:	e037883a 	mov	sp,fp
+ 80002b4:	dfc00117 	ldw	ra,4(sp)
+ 80002b8:	df000017 	ldw	fp,0(sp)
+ 80002bc:	dec00204 	addi	sp,sp,8
+ 80002c0:	f800283a 	ret
+
+080002c4 <alt_instruction_exception_entry>:
+ * that handler if it has been registered. Absent a handler, it will
+ * break break or hang as discussed below.
+ */
+int 
+alt_instruction_exception_entry (alt_u32 exception_pc)
+{
+ 80002c4:	defffb04 	addi	sp,sp,-20
+ 80002c8:	dfc00415 	stw	ra,16(sp)
+ 80002cc:	df000315 	stw	fp,12(sp)
+ 80002d0:	df000304 	addi	fp,sp,12
+ 80002d4:	e13ffd15 	stw	r4,-12(fp)
+ * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should
+ * check the validity of the cause argument before proceeding.
+ */
+#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO
+  /* Get exception cause & "badaddr" */
+  NIOS2_READ_EXCEPTION(cause);
+ 80002d8:	000531fa 	rdctl	r2,exception
+ 80002dc:	e0bfff15 	stw	r2,-4(fp)
+  cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >>
+ 80002e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80002e4:	1004d0ba 	srli	r2,r2,2
+ 80002e8:	108007cc 	andi	r2,r2,31
+ 80002ec:	e0bfff15 	stw	r2,-4(fp)
+              NIOS2_EXCEPTION_REG_CAUSE_OFST );
+
+  NIOS2_READ_BADADDR(badaddr);
+ 80002f0:	0005333a 	rdctl	r2,badaddr
+ 80002f4:	e0bffe15 	stw	r2,-8(fp)
+#else
+  cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT;
+  badaddr = 0;
+#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
+
+  if(alt_instruction_exception_handler) {
+ 80002f8:	d0a0a917 	ldw	r2,-32092(gp)
+ 80002fc:	10000726 	beq	r2,zero,800031c <alt_instruction_exception_entry+0x58>
+     * Call handler. Its return value indicates whether the exception-causing
+     * instruction should be re-issued. The code that called us,
+     * alt_eceptions_entry.S, will look at this value and adjust the ea
+     * register as necessary
+     */
+    return alt_instruction_exception_handler(cause, exception_pc, badaddr);
+ 8000300:	d0a0a917 	ldw	r2,-32092(gp)
+ 8000304:	e0ffff17 	ldw	r3,-4(fp)
+ 8000308:	e1bffe17 	ldw	r6,-8(fp)
+ 800030c:	e17ffd17 	ldw	r5,-12(fp)
+ 8000310:	1809883a 	mov	r4,r3
+ 8000314:	103ee83a 	callr	r2
+ 8000318:	00000206 	br	8000324 <alt_instruction_exception_entry+0x60>
+   *    (a peripheral which negates its interrupt output before its
+   *    interrupt handler has been executed will cause spurious interrupts)
+   */
+  else {
+#ifdef NIOS2_HAS_DEBUG_STUB
+    NIOS2_BREAK();
+ 800031c:	003da03a 	break	0
+      ;
+#endif /* NIOS2_HAS_DEBUG_STUB */
+  }
+
+  /* We should not get here. Remove compiler warning. */
+  return NIOS2_EXCEPTION_RETURN_REISSUE_INST;
+ 8000320:	0005883a 	mov	r2,zero
+}
+ 8000324:	e037883a 	mov	sp,fp
+ 8000328:	dfc00117 	ldw	ra,4(sp)
+ 800032c:	df000017 	ldw	fp,0(sp)
+ 8000330:	dec00204 	addi	sp,sp,8
+ 8000334:	f800283a 	ret
+
+Disassembly of section .text:
+
+08000338 <_start>:
+
+    /* Assume the data cache size is always a power of two. */
+#if NIOS2_DCACHE_SIZE > 0x8000
+    movhi r2, %hi(NIOS2_DCACHE_SIZE)
+#else
+    movui r2, NIOS2_DCACHE_SIZE
+ 8000338:	00820014 	movui	r2,2048
+#endif
+
+0:
+    initd 0(r2)
+ 800033c:	10000033 	initd	0(r2)
+#ifdef NIOS2_ECC_PRESENT
+    addi r2, r2, -4
+#else
+    addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
+ 8000340:	10bff804 	addi	r2,r2,-32
+#endif
+    bgt r2, zero, 0b
+ 8000344:	00bffd16 	blt	zero,r2,800033c <_start+0x4>
+
+    /*
+     * Now that the caches are initialized, set up the stack pointer and global pointer.
+     * The values provided by the linker are assumed to be correctly aligned.
+     */
+    movhi sp, %hi(__alt_stack_pointer)
+ 8000348:	06c40034 	movhi	sp,4096
+    ori sp, sp, %lo(__alt_stack_pointer)
+ 800034c:	dec00014 	ori	sp,sp,0
+    movhi gp, %hi(_gp)
+ 8000350:	06820174 	movhi	gp,2053
+    ori gp, gp, %lo(_gp)
+ 8000354:	d692ae14 	ori	gp,gp,19128
+ */
+#ifndef ALT_SIM_OPTIMIZE
+    /* Log that the BSS is about to be cleared. */
+    ALT_LOG_PUTS(alt_log_msg_bss)
+
+    movhi r2, %hi(__bss_start)
+ 8000358:	00820134 	movhi	r2,2052
+    ori r2, r2, %lo(__bss_start)
+ 800035c:	10b2e314 	ori	r2,r2,52108
+
+    movhi r3, %hi(__bss_end)
+ 8000360:	00c20174 	movhi	r3,2053
+    ori r3, r3, %lo(__bss_end)
+ 8000364:	18f96714 	ori	r3,r3,58780
+
+    beq r2, r3, 1f
+ 8000368:	10c00326 	beq	r2,r3,8000378 <_start+0x40>
+
+0:
+    stw zero, (r2)
+ 800036c:	10000015 	stw	zero,0(r2)
+    addi r2, r2, 4
+ 8000370:	10800104 	addi	r2,r2,4
+    bltu r2, r3, 0b
+ 8000374:	10fffd36 	bltu	r2,r3,800036c <_start+0x34>
+
+    /* Log that alt_main is about to be called. */
+    ALT_LOG_PUTS(alt_log_msg_alt_main)
+
+    /* Call the C entry point. It should never return. */
+    call alt_main
+ 8000378:	800fb7c0 	call	800fb7c <alt_main>
+
+0800037c <alt_after_alt_main>:
+
+    /* Wait in infinite loop in case alt_main does return. */
+alt_after_alt_main:
+    br alt_after_alt_main
+ 800037c:	003fff06 	br	800037c <alt_after_alt_main>
+
+08000380 <control_delay>:
+extern   NET   nets[MAXNETS];    /* pointers to the static network structs */
+
+// ****************************
+
+void control_delay()
+{
+ 8000380:	defffe04 	addi	sp,sp,-8
+ 8000384:	dfc00115 	stw	ra,4(sp)
+ 8000388:	df000015 	stw	fp,0(sp)
+ 800038c:	d839883a 	mov	fp,sp
+	TK_SLEEP(1);
+ 8000390:	01000084 	movi	r4,2
+ 8000394:	801730c0 	call	801730c <OSTimeDly>
+}
+ 8000398:	0001883a 	nop
+ 800039c:	e037883a 	mov	sp,fp
+ 80003a0:	dfc00117 	ldw	ra,4(sp)
+ 80003a4:	df000017 	ldw	fp,0(sp)
+ 80003a8:	dec00204 	addi	sp,sp,8
+ 80003ac:	f800283a 	ret
+
+080003b0 <control_pong>:
+
+// ****************************
+
+	//simple reply
+void control_pong(command_header* header)
+{
+ 80003b0:	defffb04 	addi	sp,sp,-20
+ 80003b4:	dfc00415 	stw	ra,16(sp)
+ 80003b8:	df000315 	stw	fp,12(sp)
+ 80003bc:	df000304 	addi	fp,sp,12
+ 80003c0:	e13ffd15 	stw	r4,-12(fp)
+	command_header tmp;
+	tmp = *header;
+ 80003c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80003c8:	10c0000b 	ldhu	r3,0(r2)
+ 80003cc:	e0fffe8d 	sth	r3,-6(fp)
+ 80003d0:	10c0008b 	ldhu	r3,2(r2)
+ 80003d4:	e0ffff0d 	sth	r3,-4(fp)
+ 80003d8:	1080010b 	ldhu	r2,4(r2)
+ 80003dc:	e0bfff8d 	sth	r2,-2(fp)
+	swap_bytes((char*)(void*)(&tmp), sizeof(tmp));
+ 80003e0:	e0bffe84 	addi	r2,fp,-6
+ 80003e4:	01400184 	movi	r5,6
+ 80003e8:	1009883a 	mov	r4,r2
+ 80003ec:	80027a80 	call	80027a8 <swap_bytes>
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(header));
+ 80003f0:	e1bffd17 	ldw	r6,-12(fp)
+ 80003f4:	01400184 	movi	r5,6
+ 80003f8:	0009883a 	mov	r4,zero
+ 80003fc:	800220c0 	call	800220c <ethernet_write>
+}
+ 8000400:	0001883a 	nop
+ 8000404:	e037883a 	mov	sp,fp
+ 8000408:	dfc00117 	ldw	ra,4(sp)
+ 800040c:	df000017 	ldw	fp,0(sp)
+ 8000410:	dec00204 	addi	sp,sp,8
+ 8000414:	f800283a 	ret
+
+08000418 <control_process_snapshot>:
+
+void control_process_snapshot()
+{
+ 8000418:	defffc04 	addi	sp,sp,-16
+ 800041c:	dfc00315 	stw	ra,12(sp)
+ 8000420:	df000215 	stw	fp,8(sp)
+ 8000424:	df000204 	addi	fp,sp,8
+	command_header header = {.marker = 0x5555, .command = COMMAND_SLOWCTRL_SNAPSHOT,
+ 8000428:	00955544 	movi	r2,21845
+ 800042c:	e0bffe8d 	sth	r2,-6(fp)
+ 8000430:	00810404 	movi	r2,1040
+ 8000434:	e0bfff0d 	sth	r2,-4(fp)
+ 8000438:	e03fff8d 	sth	zero,-2(fp)
+							 .length = 0};	//SLOWCTRL_ADC_CHANNEL_COUNT * sizeof(SLOWCTRL_ADC_DATA_TYPE) / sizeof(unsigned short)};
+	swap_bytes((char*)(void*)(&header), sizeof(header));
+ 800043c:	e0bffe84 	addi	r2,fp,-6
+ 8000440:	01400184 	movi	r5,6
+ 8000444:	1009883a 	mov	r4,r2
+ 8000448:	80027a80 	call	80027a8 <swap_bytes>
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(&header));
+ 800044c:	e0bffe84 	addi	r2,fp,-6
+ 8000450:	100d883a 	mov	r6,r2
+ 8000454:	01400184 	movi	r5,6
+ 8000458:	0009883a 	mov	r4,zero
+ 800045c:	800220c0 	call	800220c <ethernet_write>
+	//ethernet_write(0, SLOWCTRL_ADC_CHANNEL_COUNT*sizeof(SLOWCTRL_ADC_DATA_TYPE), (unsigned char*)slowctrl_adc_buffer);
+}
+ 8000460:	0001883a 	nop
+ 8000464:	e037883a 	mov	sp,fp
+ 8000468:	dfc00117 	ldw	ra,4(sp)
+ 800046c:	df000017 	ldw	fp,0(sp)
+ 8000470:	dec00204 	addi	sp,sp,8
+ 8000474:	f800283a 	ret
+
+08000478 <check_arp>:
+
+	//helper for the one below
+int check_arp(struct arptabent * arp_entry, ip_addr ip)
+{
+ 8000478:	defffc04 	addi	sp,sp,-16
+ 800047c:	df000315 	stw	fp,12(sp)
+ 8000480:	df000304 	addi	fp,sp,12
+ 8000484:	e13ffe15 	stw	r4,-8(fp)
+ 8000488:	e17ffd15 	stw	r5,-12(fp)
+	if (arp_entry->t_pro_addr != ip)
+ 800048c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000490:	10800017 	ldw	r2,0(r2)
+ 8000494:	e0fffd17 	ldw	r3,-12(fp)
+ 8000498:	18800226 	beq	r3,r2,80004a4 <check_arp+0x2c>
+		return 0;	//bad IP
+ 800049c:	0005883a 	mov	r2,zero
+ 80004a0:	00001106 	br	80004e8 <check_arp+0x70>
+
+	for (int i = 0; i < 6; i++)
+ 80004a4:	e03fff15 	stw	zero,-4(fp)
+ 80004a8:	00000b06 	br	80004d8 <check_arp+0x60>
+		if (arp_entry->t_phy_addr[i] != 0)
+ 80004ac:	e0fffe17 	ldw	r3,-8(fp)
+ 80004b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80004b4:	1885883a 	add	r2,r3,r2
+ 80004b8:	10800103 	ldbu	r2,4(r2)
+ 80004bc:	10803fcc 	andi	r2,r2,255
+ 80004c0:	10000226 	beq	r2,zero,80004cc <check_arp+0x54>
+			return 1;	//non-zero MAC
+ 80004c4:	00800044 	movi	r2,1
+ 80004c8:	00000706 	br	80004e8 <check_arp+0x70>
+	for (int i = 0; i < 6; i++)
+ 80004cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80004d0:	10800044 	addi	r2,r2,1
+ 80004d4:	e0bfff15 	stw	r2,-4(fp)
+ 80004d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80004dc:	10800190 	cmplti	r2,r2,6
+ 80004e0:	103ff21e 	bne	r2,zero,80004ac <check_arp+0x34>
+
+	return 0;
+ 80004e4:	0005883a 	mov	r2,zero
+}
+ 80004e8:	e037883a 	mov	sp,fp
+ 80004ec:	df000017 	ldw	fp,0(sp)
+ 80004f0:	dec00104 	addi	sp,sp,4
+ 80004f4:	f800283a 	ret
+
+080004f8 <control_process_config_peer>:
+
+void control_process_config_peer(unsigned short* data)
+{
+ 80004f8:	defff104 	addi	sp,sp,-60
+ 80004fc:	dfc00e15 	stw	ra,56(sp)
+ 8000500:	df000d15 	stw	fp,52(sp)
+ 8000504:	df000d04 	addi	fp,sp,52
+ 8000508:	e13ff615 	stw	r4,-40(fp)
+	ip_addr ip = 0;
+ 800050c:	e03ffa15 	stw	zero,-24(fp)
+	ip_addr srcip = 0;
+ 8000510:	e03ff915 	stw	zero,-28(fp)
+	int i;
+	command_header header = {.marker = 0x5555, .command = COMMAND_DAQ_CONFIG_PEER, .length = 0};
+ 8000514:	00955544 	movi	r2,21845
+ 8000518:	e0bff78d 	sth	r2,-34(fp)
+ 800051c:	0080cc44 	movi	r2,817
+ 8000520:	e0bff80d 	sth	r2,-32(fp)
+ 8000524:	e03ff88d 	sth	zero,-30(fp)
+
+	for (i = 0; i < 4; i++)
+ 8000528:	e03fff15 	stw	zero,-4(fp)
+ 800052c:	00001006 	br	8000570 <control_process_config_peer+0x78>
+		ip = (ip << 8) | (unsigned char)(data[3-i] & 0x00FF);
+ 8000530:	e0bffa17 	ldw	r2,-24(fp)
+ 8000534:	1006923a 	slli	r3,r2,8
+ 8000538:	010000c4 	movi	r4,3
+ 800053c:	e0bfff17 	ldw	r2,-4(fp)
+ 8000540:	2085c83a 	sub	r2,r4,r2
+ 8000544:	1085883a 	add	r2,r2,r2
+ 8000548:	1009883a 	mov	r4,r2
+ 800054c:	e0bff617 	ldw	r2,-40(fp)
+ 8000550:	1105883a 	add	r2,r2,r4
+ 8000554:	1080000b 	ldhu	r2,0(r2)
+ 8000558:	10803fcc 	andi	r2,r2,255
+ 800055c:	1884b03a 	or	r2,r3,r2
+ 8000560:	e0bffa15 	stw	r2,-24(fp)
+	for (i = 0; i < 4; i++)
+ 8000564:	e0bfff17 	ldw	r2,-4(fp)
+ 8000568:	10800044 	addi	r2,r2,1
+ 800056c:	e0bfff15 	stw	r2,-4(fp)
+ 8000570:	e0bfff17 	ldw	r2,-4(fp)
+ 8000574:	10800110 	cmplti	r2,r2,4
+ 8000578:	103fed1e 	bne	r2,zero,8000530 <control_process_config_peer+0x38>
+
+	//daq_configure_peer_addr(ip, data[4]);
+
+	printf("Querying ARP for %d.%d.%d.%d ...\n",data[0],data[1],data[2],data[3]);
+ 800057c:	e0bff617 	ldw	r2,-40(fp)
+ 8000580:	1080000b 	ldhu	r2,0(r2)
+ 8000584:	10ffffcc 	andi	r3,r2,65535
+ 8000588:	e0bff617 	ldw	r2,-40(fp)
+ 800058c:	10800084 	addi	r2,r2,2
+ 8000590:	1080000b 	ldhu	r2,0(r2)
+ 8000594:	113fffcc 	andi	r4,r2,65535
+ 8000598:	e0bff617 	ldw	r2,-40(fp)
+ 800059c:	10800104 	addi	r2,r2,4
+ 80005a0:	1080000b 	ldhu	r2,0(r2)
+ 80005a4:	117fffcc 	andi	r5,r2,65535
+ 80005a8:	e0bff617 	ldw	r2,-40(fp)
+ 80005ac:	10800184 	addi	r2,r2,6
+ 80005b0:	1080000b 	ldhu	r2,0(r2)
+ 80005b4:	10bfffcc 	andi	r2,r2,65535
+ 80005b8:	d8800015 	stw	r2,0(sp)
+ 80005bc:	280f883a 	mov	r7,r5
+ 80005c0:	200d883a 	mov	r6,r4
+ 80005c4:	180b883a 	mov	r5,r3
+ 80005c8:	01020134 	movhi	r4,2052
+ 80005cc:	211a6a04 	addi	r4,r4,27048
+ 80005d0:	8002c780 	call	8002c78 <printf>
+
+	struct arptabent * arp_entry = find_oldest_arp(ip);
+ 80005d4:	e0bffa17 	ldw	r2,-24(fp)
+ 80005d8:	1009883a 	mov	r4,r2
+ 80005dc:	80233bc0 	call	80233bc <find_oldest_arp>
+ 80005e0:	e0bffe15 	stw	r2,-8(fp)
+
+	int pingseq = 0;
+ 80005e4:	e03ffd15 	stw	zero,-12(fp)
+	while (!check_arp(arp_entry, ip))	//big loop for pinging 10 times
+ 80005e8:	00002606 	br	8000684 <control_process_config_peer+0x18c>
+	{
+		printf("ARP entry could not be found, pinging!\n");
+ 80005ec:	01020134 	movhi	r4,2052
+ 80005f0:	211a7304 	addi	r4,r4,27084
+ 80005f4:	8002d9c0 	call	8002d9c <puts>
+			//ping the peer to ARP it.
+		icmpEcho(ip, NULL, 8, pingseq++);
+ 80005f8:	e13ffa17 	ldw	r4,-24(fp)
+ 80005fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8000600:	10c00044 	addi	r3,r2,1
+ 8000604:	e0fffd15 	stw	r3,-12(fp)
+ 8000608:	10bfffcc 	andi	r2,r2,65535
+ 800060c:	100f883a 	mov	r7,r2
+ 8000610:	01800204 	movi	r6,8
+ 8000614:	000b883a 	mov	r5,zero
+ 8000618:	8027f0c0 	call	8027f0c <icmpEcho>
+
+		for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++)	//small loop for waiting 5 times after each ping
+ 800061c:	e03ffc15 	stw	zero,-16(fp)
+ 8000620:	00000906 	br	8000648 <control_process_config_peer+0x150>
+		{
+			TK_SLEEP(10);
+ 8000624:	010002c4 	movi	r4,11
+ 8000628:	801730c0 	call	801730c <OSTimeDly>
+			arp_entry = find_oldest_arp(ip);
+ 800062c:	e0bffa17 	ldw	r2,-24(fp)
+ 8000630:	1009883a 	mov	r4,r2
+ 8000634:	80233bc0 	call	80233bc <find_oldest_arp>
+ 8000638:	e0bffe15 	stw	r2,-8(fp)
+		for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++)	//small loop for waiting 5 times after each ping
+ 800063c:	e0bffc17 	ldw	r2,-16(fp)
+ 8000640:	10800044 	addi	r2,r2,1
+ 8000644:	e0bffc15 	stw	r2,-16(fp)
+ 8000648:	e0bffc17 	ldw	r2,-16(fp)
+ 800064c:	10800148 	cmpgei	r2,r2,5
+ 8000650:	1000051e 	bne	r2,zero,8000668 <control_process_config_peer+0x170>
+ 8000654:	e0bffa17 	ldw	r2,-24(fp)
+ 8000658:	100b883a 	mov	r5,r2
+ 800065c:	e13ffe17 	ldw	r4,-8(fp)
+ 8000660:	80004780 	call	8000478 <check_arp>
+ 8000664:	103fef26 	beq	r2,zero,8000624 <control_process_config_peer+0x12c>
+		}
+
+		if (pingseq > 10)
+ 8000668:	e0bffd17 	ldw	r2,-12(fp)
+ 800066c:	108002d0 	cmplti	r2,r2,11
+ 8000670:	1000041e 	bne	r2,zero,8000684 <control_process_config_peer+0x18c>
+		{
+			printf("Could not resolve MAC! The result below is random!\n");
+ 8000674:	01020134 	movhi	r4,2052
+ 8000678:	211a7d04 	addi	r4,r4,27124
+ 800067c:	8002d9c0 	call	8002d9c <puts>
+			break;
+ 8000680:	00000506 	br	8000698 <control_process_config_peer+0x1a0>
+	while (!check_arp(arp_entry, ip))	//big loop for pinging 10 times
+ 8000684:	e0bffa17 	ldw	r2,-24(fp)
+ 8000688:	100b883a 	mov	r5,r2
+ 800068c:	e13ffe17 	ldw	r4,-8(fp)
+ 8000690:	80004780 	call	8000478 <check_arp>
+ 8000694:	103fd526 	beq	r2,zero,80005ec <control_process_config_peer+0xf4>
+		}
+	}
+
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+			arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2],
+ 8000698:	e0bffe17 	ldw	r2,-8(fp)
+ 800069c:	10800103 	ldbu	r2,4(r2)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006a0:	11403fcc 	andi	r5,r2,255
+			arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2],
+ 80006a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80006a8:	10800143 	ldbu	r2,5(r2)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006ac:	11803fcc 	andi	r6,r2,255
+			arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2],
+ 80006b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80006b4:	10800183 	ldbu	r2,6(r2)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006b8:	11c03fcc 	andi	r7,r2,255
+			arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]);
+ 80006bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80006c0:	108001c3 	ldbu	r2,7(r2)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006c4:	10803fcc 	andi	r2,r2,255
+			arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]);
+ 80006c8:	e0fffe17 	ldw	r3,-8(fp)
+ 80006cc:	18c00203 	ldbu	r3,8(r3)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006d0:	18c03fcc 	andi	r3,r3,255
+			arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]);
+ 80006d4:	e13ffe17 	ldw	r4,-8(fp)
+ 80006d8:	21000243 	ldbu	r4,9(r4)
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+ 80006dc:	21003fcc 	andi	r4,r4,255
+ 80006e0:	d9000215 	stw	r4,8(sp)
+ 80006e4:	d8c00115 	stw	r3,4(sp)
+ 80006e8:	d8800015 	stw	r2,0(sp)
+ 80006ec:	01020134 	movhi	r4,2052
+ 80006f0:	211a8a04 	addi	r4,r4,27176
+ 80006f4:	8002c780 	call	8002c78 <printf>
+
+	srcip = nets[0]->n_ipaddr;
+ 80006f8:	008201b4 	movhi	r2,2054
+ 80006fc:	10b77017 	ldw	r2,-8768(r2)
+ 8000700:	10800a17 	ldw	r2,40(r2)
+ 8000704:	e0bff915 	stw	r2,-28(fp)
+	swap_quad((unsigned char*)(void*)(&srcip), 4);	//UDP generator needs such a format
+ 8000708:	e0bff904 	addi	r2,fp,-28
+ 800070c:	01400104 	movi	r5,4
+ 8000710:	1009883a 	mov	r4,r2
+ 8000714:	80028400 	call	8002840 <swap_quad>
+	swap_quad((unsigned char*)(void*)(&ip), 4);
+ 8000718:	e0bffa04 	addi	r2,fp,-24
+ 800071c:	01400104 	movi	r5,4
+ 8000720:	1009883a 	mov	r4,r2
+ 8000724:	80028400 	call	8002840 <swap_quad>
+
+	//set up udpgen with correct values
+	udpgen_set_size(UDP_GENERATOR_BASE, 167);	//sensor_interface.v:39
+ 8000728:	00c029c4 	movi	r3,167
+ 800072c:	00861034 	movhi	r2,6208
+ 8000730:	10cf30ad 	sthio	r3,15554(r2)
+	udpgen_set_srcip(UDP_GENERATOR_BASE, srcip);
+ 8000734:	e0bff917 	ldw	r2,-28(fp)
+ 8000738:	1007883a 	mov	r3,r2
+ 800073c:	00861034 	movhi	r2,6208
+ 8000740:	10cf3135 	stwio	r3,15556(r2)
+	udpgen_set_dstip(UDP_GENERATOR_BASE, ip);
+ 8000744:	e0bffa17 	ldw	r2,-24(fp)
+ 8000748:	1007883a 	mov	r3,r2
+ 800074c:	00861034 	movhi	r2,6208
+ 8000750:	10cf3235 	stwio	r3,15560(r2)
+	udpgen_set_srcport(UDP_GENERATOR_BASE, DATA_PORT);
+ 8000754:	00c3e844 	movi	r3,4001
+ 8000758:	00861034 	movhi	r2,6208
+ 800075c:	10cf33ad 	sthio	r3,15566(r2)
+	udpgen_set_dstport(UDP_GENERATOR_BASE, data[4]);
+ 8000760:	e0bff617 	ldw	r2,-40(fp)
+ 8000764:	10800204 	addi	r2,r2,8
+ 8000768:	1080000b 	ldhu	r2,0(r2)
+ 800076c:	10ffffcc 	andi	r3,r2,65535
+ 8000770:	00861034 	movhi	r2,6208
+ 8000774:	10cf332d 	sthio	r3,15564(r2)
+	udpgen_set_dstmac_a(UDP_GENERATOR_BASE, arp_entry->t_phy_addr);
+ 8000778:	e03ffb15 	stw	zero,-20(fp)
+ 800077c:	00001106 	br	80007c4 <control_process_config_peer+0x2cc>
+ 8000780:	e0bffb17 	ldw	r2,-20(fp)
+ 8000784:	10800404 	addi	r2,r2,16
+ 8000788:	1007883a 	mov	r3,r2
+ 800078c:	00861034 	movhi	r2,6208
+ 8000790:	108f3004 	addi	r2,r2,15552
+ 8000794:	1885883a 	add	r2,r3,r2
+ 8000798:	01000144 	movi	r4,5
+ 800079c:	e0fffb17 	ldw	r3,-20(fp)
+ 80007a0:	20c7c83a 	sub	r3,r4,r3
+ 80007a4:	e13ffe17 	ldw	r4,-8(fp)
+ 80007a8:	20c7883a 	add	r3,r4,r3
+ 80007ac:	18c00103 	ldbu	r3,4(r3)
+ 80007b0:	18c03fcc 	andi	r3,r3,255
+ 80007b4:	10c00025 	stbio	r3,0(r2)
+ 80007b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80007bc:	10800044 	addi	r2,r2,1
+ 80007c0:	e0bffb15 	stw	r2,-20(fp)
+ 80007c4:	e0bffb17 	ldw	r2,-20(fp)
+ 80007c8:	10800190 	cmplti	r2,r2,6
+ 80007cc:	103fec1e 	bne	r2,zero,8000780 <control_process_config_peer+0x288>
+
+	swap_bytes((unsigned char*)(void*)(&header), sizeof(header));
+ 80007d0:	e0bff784 	addi	r2,fp,-34
+ 80007d4:	01400184 	movi	r5,6
+ 80007d8:	1009883a 	mov	r4,r2
+ 80007dc:	80027a80 	call	80027a8 <swap_bytes>
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(&header));
+ 80007e0:	e0bff784 	addi	r2,fp,-34
+ 80007e4:	100d883a 	mov	r6,r2
+ 80007e8:	01400184 	movi	r5,6
+ 80007ec:	0009883a 	mov	r4,zero
+ 80007f0:	800220c0 	call	800220c <ethernet_write>
+}
+ 80007f4:	0001883a 	nop
+ 80007f8:	e037883a 	mov	sp,fp
+ 80007fc:	dfc00117 	ldw	ra,4(sp)
+ 8000800:	df000017 	ldw	fp,0(sp)
+ 8000804:	dec00204 	addi	sp,sp,8
+ 8000808:	f800283a 	ret
+
+0800080c <control_get_header>:
+
+// ****************************
+
+	//Receive command header. Return (without loosing data!) if number of received bytes is insufficient.
+unsigned char control_get_header(command_header** result)
+{
+ 800080c:	defffd04 	addi	sp,sp,-12
+ 8000810:	dfc00215 	stw	ra,8(sp)
+ 8000814:	df000115 	stw	fp,4(sp)
+ 8000818:	df000104 	addi	fp,sp,4
+ 800081c:	e13fff15 	stw	r4,-4(fp)
+	static command_header header;
+	static unsigned int bytes_received = 0;
+
+	bytes_received += ethernet_read(0, sizeof(command_header)-bytes_received, (unsigned char*)(&header) + bytes_received);
+ 8000820:	d0a03517 	ldw	r2,-32556(gp)
+ 8000824:	00c00184 	movi	r3,6
+ 8000828:	1885c83a 	sub	r2,r3,r2
+ 800082c:	1009883a 	mov	r4,r2
+ 8000830:	d0e03517 	ldw	r3,-32556(gp)
+ 8000834:	d0a03604 	addi	r2,gp,-32552
+ 8000838:	1885883a 	add	r2,r3,r2
+ 800083c:	100d883a 	mov	r6,r2
+ 8000840:	200b883a 	mov	r5,r4
+ 8000844:	0009883a 	mov	r4,zero
+ 8000848:	80023140 	call	8002314 <ethernet_read>
+ 800084c:	1007883a 	mov	r3,r2
+ 8000850:	d0a03517 	ldw	r2,-32556(gp)
+ 8000854:	1885883a 	add	r2,r3,r2
+ 8000858:	d0a03515 	stw	r2,-32556(gp)
+
+	if (bytes_received < sizeof(command_header))
+ 800085c:	d0a03517 	ldw	r2,-32556(gp)
+ 8000860:	108001a8 	cmpgeui	r2,r2,6
+ 8000864:	1000021e 	bne	r2,zero,8000870 <control_get_header+0x64>
+		return 0;
+ 8000868:	0005883a 	mov	r2,zero
+ 800086c:	00000806 	br	8000890 <control_get_header+0x84>
+
+	swap_bytes((unsigned char*)(void*)(&header),sizeof(header));	//if the header is complete, swap bytes and return it
+ 8000870:	01400184 	movi	r5,6
+ 8000874:	d1203604 	addi	r4,gp,-32552
+ 8000878:	80027a80 	call	80027a8 <swap_bytes>
+	*result = &header;
+ 800087c:	e0bfff17 	ldw	r2,-4(fp)
+ 8000880:	d0e03604 	addi	r3,gp,-32552
+ 8000884:	10c00015 	stw	r3,0(r2)
+	bytes_received = 0;
+ 8000888:	d0203515 	stw	zero,-32556(gp)
+	return 1;
+ 800088c:	00800044 	movi	r2,1
+}
+ 8000890:	e037883a 	mov	sp,fp
+ 8000894:	dfc00117 	ldw	ra,4(sp)
+ 8000898:	df000017 	ldw	fp,0(sp)
+ 800089c:	dec00204 	addi	sp,sp,8
+ 80008a0:	f800283a 	ret
+
+080008a4 <control_get_data>:
+
+	//Receive command data. Return (without loosing data!) if number of received bytes is insufficient.
+	//Expected data length is given in words!
+unsigned char control_get_data(unsigned short expected_length, unsigned short** data)
+{
+ 80008a4:	defffc04 	addi	sp,sp,-16
+ 80008a8:	dfc00315 	stw	ra,12(sp)
+ 80008ac:	df000215 	stw	fp,8(sp)
+ 80008b0:	df000204 	addi	fp,sp,8
+ 80008b4:	2005883a 	mov	r2,r4
+ 80008b8:	e17ffe15 	stw	r5,-8(fp)
+ 80008bc:	e0bfff0d 	sth	r2,-4(fp)
+	static unsigned short packet_data[CONTROL_MAX_DATA_LENGTH];
+	static unsigned int bytes_received = 0;
+
+	bytes_received += ethernet_read(0, 2*expected_length - bytes_received, (unsigned char*)(&packet_data) + bytes_received);
+ 80008c0:	e0bfff0b 	ldhu	r2,-4(fp)
+ 80008c4:	1085883a 	add	r2,r2,r2
+ 80008c8:	1007883a 	mov	r3,r2
+ 80008cc:	d0a03817 	ldw	r2,-32544(gp)
+ 80008d0:	1885c83a 	sub	r2,r3,r2
+ 80008d4:	1009883a 	mov	r4,r2
+ 80008d8:	d0e03817 	ldw	r3,-32544(gp)
+ 80008dc:	00820174 	movhi	r2,2053
+ 80008e0:	10b35804 	addi	r2,r2,-12960
+ 80008e4:	1885883a 	add	r2,r3,r2
+ 80008e8:	100d883a 	mov	r6,r2
+ 80008ec:	200b883a 	mov	r5,r4
+ 80008f0:	0009883a 	mov	r4,zero
+ 80008f4:	80023140 	call	8002314 <ethernet_read>
+ 80008f8:	1007883a 	mov	r3,r2
+ 80008fc:	d0a03817 	ldw	r2,-32544(gp)
+ 8000900:	1885883a 	add	r2,r3,r2
+ 8000904:	d0a03815 	stw	r2,-32544(gp)
+
+		if (bytes_received < (2*expected_length))
+ 8000908:	e0bfff0b 	ldhu	r2,-4(fp)
+ 800090c:	1085883a 	add	r2,r2,r2
+ 8000910:	1007883a 	mov	r3,r2
+ 8000914:	d0a03817 	ldw	r2,-32544(gp)
+ 8000918:	10c0022e 	bgeu	r2,r3,8000924 <control_get_data+0x80>
+			return 0;
+ 800091c:	0005883a 	mov	r2,zero
+ 8000920:	00000606 	br	800093c <control_get_data+0x98>
+
+		*data = packet_data;
+ 8000924:	e0fffe17 	ldw	r3,-8(fp)
+ 8000928:	00820174 	movhi	r2,2053
+ 800092c:	10b35804 	addi	r2,r2,-12960
+ 8000930:	18800015 	stw	r2,0(r3)
+		bytes_received = 0;
+ 8000934:	d0203815 	stw	zero,-32544(gp)
+		return 1;
+ 8000938:	00800044 	movi	r2,1
+}
+ 800093c:	e037883a 	mov	sp,fp
+ 8000940:	dfc00117 	ldw	ra,4(sp)
+ 8000944:	df000017 	ldw	fp,0(sp)
+ 8000948:	dec00204 	addi	sp,sp,8
+ 800094c:	f800283a 	ret
+
+08000950 <control_step>:
+
+// ****************************
+
+void control_step()
+{
+ 8000950:	defffb04 	addi	sp,sp,-20
+ 8000954:	dfc00415 	stw	ra,16(sp)
+ 8000958:	df000315 	stw	fp,12(sp)
+ 800095c:	df000304 	addi	fp,sp,12
+	command_header* header;
+	unsigned short* data;
+	unsigned int loop_ctr = 0;
+ 8000960:	e03fff15 	stw	zero,-4(fp)
+
+
+	//get header - at this moment this is blocking!
+	while (!control_get_header(&header))
+ 8000964:	00000706 	br	8000984 <control_step+0x34>
+	{
+		control_delay();
+ 8000968:	80003800 	call	8000380 <control_delay>
+
+		if (++loop_ctr > CONTROL_TIMEOUT)
+ 800096c:	e0bfff17 	ldw	r2,-4(fp)
+ 8000970:	10800044 	addi	r2,r2,1
+ 8000974:	e0bfff15 	stw	r2,-4(fp)
+ 8000978:	e0bfff17 	ldw	r2,-4(fp)
+ 800097c:	1080fa70 	cmpltui	r2,r2,1001
+ 8000980:	1001ae26 	beq	r2,zero,800103c <control_step+0x6ec>
+	while (!control_get_header(&header))
+ 8000984:	e0bffe04 	addi	r2,fp,-8
+ 8000988:	1009883a 	mov	r4,r2
+ 800098c:	800080c0 	call	800080c <control_get_header>
+ 8000990:	10803fcc 	andi	r2,r2,255
+ 8000994:	103ff426 	beq	r2,zero,8000968 <control_step+0x18>
+			return;
+		}
+	}
+
+		//check start marker
+	if (header->marker != 0x5555)
+ 8000998:	e0bffe17 	ldw	r2,-8(fp)
+ 800099c:	1080000b 	ldhu	r2,0(r2)
+ 80009a0:	10bfffcc 	andi	r2,r2,65535
+ 80009a4:	10955560 	cmpeqi	r2,r2,21845
+ 80009a8:	1001a626 	beq	r2,zero,8001044 <control_step+0x6f4>
+		return;
+
+
+		//get packet data - at this moment this is blocking!
+	while (!control_get_data(header->length, &data))
+ 80009ac:	00000706 	br	80009cc <control_step+0x7c>
+	{
+		control_delay();
+ 80009b0:	80003800 	call	8000380 <control_delay>
+
+		if (++loop_ctr > CONTROL_TIMEOUT)
+ 80009b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80009b8:	10800044 	addi	r2,r2,1
+ 80009bc:	e0bfff15 	stw	r2,-4(fp)
+ 80009c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80009c4:	1080fa70 	cmpltui	r2,r2,1001
+ 80009c8:	1001a026 	beq	r2,zero,800104c <control_step+0x6fc>
+	while (!control_get_data(header->length, &data))
+ 80009cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80009d0:	1080010b 	ldhu	r2,4(r2)
+ 80009d4:	10bfffcc 	andi	r2,r2,65535
+ 80009d8:	e0fffd04 	addi	r3,fp,-12
+ 80009dc:	180b883a 	mov	r5,r3
+ 80009e0:	1009883a 	mov	r4,r2
+ 80009e4:	80008a40 	call	80008a4 <control_get_data>
+ 80009e8:	10803fcc 	andi	r2,r2,255
+ 80009ec:	103ff026 	beq	r2,zero,80009b0 <control_step+0x60>
+		{
+			return;
+		}
+	}
+		//swap data bytes
+	swap_bytes((unsigned char*)(void*)data, header->length*2);
+ 80009f0:	e0fffd17 	ldw	r3,-12(fp)
+ 80009f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80009f8:	1080010b 	ldhu	r2,4(r2)
+ 80009fc:	10bfffcc 	andi	r2,r2,65535
+ 8000a00:	1085883a 	add	r2,r2,r2
+ 8000a04:	100b883a 	mov	r5,r2
+ 8000a08:	1809883a 	mov	r4,r3
+ 8000a0c:	80027a80 	call	80027a8 <swap_bytes>
+
+	switch(header->command)
+ 8000a10:	e0bffe17 	ldw	r2,-8(fp)
+ 8000a14:	1080008b 	ldhu	r2,2(r2)
+ 8000a18:	10bfffcc 	andi	r2,r2,65535
+ 8000a1c:	10c09420 	cmpeqi	r3,r2,592
+ 8000a20:	1800b51e 	bne	r3,zero,8000cf8 <control_step+0x3a8>
+ 8000a24:	10c09448 	cmpgei	r3,r2,593
+ 8000a28:	1800201e 	bne	r3,zero,8000aac <control_step+0x15c>
+ 8000a2c:	10c08420 	cmpeqi	r3,r2,528
+ 8000a30:	1800691e 	bne	r3,zero,8000bd8 <control_step+0x288>
+ 8000a34:	10c08448 	cmpgei	r3,r2,529
+ 8000a38:	18000e1e 	bne	r3,zero,8000a74 <control_step+0x124>
+ 8000a3c:	10c00460 	cmpeqi	r3,r2,17
+ 8000a40:	18004a1e 	bne	r3,zero,8000b6c <control_step+0x21c>
+ 8000a44:	10c00488 	cmpgei	r3,r2,18
+ 8000a48:	1800051e 	bne	r3,zero,8000a60 <control_step+0x110>
+ 8000a4c:	10c00060 	cmpeqi	r3,r2,1
+ 8000a50:	1800361e 	bne	r3,zero,8000b2c <control_step+0x1dc>
+ 8000a54:	10800420 	cmpeqi	r2,r2,16
+ 8000a58:	10003b1e 	bne	r2,zero,8000b48 <control_step+0x1f8>
+		control_pong(header);
+		break;
+
+
+	default:
+		break;
+ 8000a5c:	00017c06 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000a60:	10c04420 	cmpeqi	r3,r2,272
+ 8000a64:	18004a1e 	bne	r3,zero,8000b90 <control_step+0x240>
+ 8000a68:	10804460 	cmpeqi	r2,r2,273
+ 8000a6c:	1000511e 	bne	r2,zero,8000bb4 <control_step+0x264>
+		break;
+ 8000a70:	00017706 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000a74:	10c08860 	cmpeqi	r3,r2,545
+ 8000a78:	1800721e 	bne	r3,zero,8000c44 <control_step+0x2f4>
+ 8000a7c:	10c08888 	cmpgei	r3,r2,546
+ 8000a80:	1800051e 	bne	r3,zero,8000a98 <control_step+0x148>
+ 8000a84:	10c08460 	cmpeqi	r3,r2,529
+ 8000a88:	18005c1e 	bne	r3,zero,8000bfc <control_step+0x2ac>
+ 8000a8c:	10808820 	cmpeqi	r2,r2,544
+ 8000a90:	1000631e 	bne	r2,zero,8000c20 <control_step+0x2d0>
+		break;
+ 8000a94:	00016e06 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000a98:	10c08c20 	cmpeqi	r3,r2,560
+ 8000a9c:	1800721e 	bne	r3,zero,8000c68 <control_step+0x318>
+ 8000aa0:	10809020 	cmpeqi	r2,r2,576
+ 8000aa4:	1000821e 	bne	r2,zero,8000cb0 <control_step+0x360>
+		break;
+ 8000aa8:	00016906 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000aac:	10c0c8a0 	cmpeqi	r3,r2,802
+ 8000ab0:	1800ff1e 	bne	r3,zero,8000eb0 <control_step+0x560>
+ 8000ab4:	10c0c8c8 	cmpgei	r3,r2,803
+ 8000ab8:	18000e1e 	bne	r3,zero,8000af4 <control_step+0x1a4>
+ 8000abc:	10c0c420 	cmpeqi	r3,r2,784
+ 8000ac0:	1800c81e 	bne	r3,zero,8000de4 <control_step+0x494>
+ 8000ac4:	10c0c448 	cmpgei	r3,r2,785
+ 8000ac8:	1800051e 	bne	r3,zero,8000ae0 <control_step+0x190>
+ 8000acc:	10c09820 	cmpeqi	r3,r2,608
+ 8000ad0:	18009e1e 	bne	r3,zero,8000d4c <control_step+0x3fc>
+ 8000ad4:	10809c20 	cmpeqi	r2,r2,624
+ 8000ad8:	1000af1e 	bne	r2,zero,8000d98 <control_step+0x448>
+		break;
+ 8000adc:	00015c06 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000ae0:	10c0c460 	cmpeqi	r3,r2,785
+ 8000ae4:	1800d01e 	bne	r3,zero,8000e28 <control_step+0x4d8>
+ 8000ae8:	1080c860 	cmpeqi	r2,r2,801
+ 8000aec:	1000df1e 	bne	r2,zero,8000e6c <control_step+0x51c>
+		break;
+ 8000af0:	00015706 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000af4:	10d00060 	cmpeqi	r3,r2,16385
+ 8000af8:	1801001e 	bne	r3,zero,8000efc <control_step+0x5ac>
+ 8000afc:	10d00088 	cmpgei	r3,r2,16386
+ 8000b00:	1800051e 	bne	r3,zero,8000b18 <control_step+0x1c8>
+ 8000b04:	10c0cc60 	cmpeqi	r3,r2,817
+ 8000b08:	1800f01e 	bne	r3,zero,8000ecc <control_step+0x57c>
+ 8000b0c:	10810420 	cmpeqi	r2,r2,1040
+ 8000b10:	1000f51e 	bne	r2,zero,8000ee8 <control_step+0x598>
+		break;
+ 8000b14:	00014e06 	br	8001050 <control_step+0x700>
+	switch(header->command)
+ 8000b18:	10d000a0 	cmpeqi	r3,r2,16386
+ 8000b1c:	1801091e 	bne	r3,zero,8000f44 <control_step+0x5f4>
+ 8000b20:	109000e0 	cmpeqi	r2,r2,16387
+ 8000b24:	1001191e 	bne	r2,zero,8000f8c <control_step+0x63c>
+		break;
+ 8000b28:	00014906 	br	8001050 <control_step+0x700>
+		printf("COMMAND_PING\n");
+ 8000b2c:	01020134 	movhi	r4,2052
+ 8000b30:	211a9504 	addi	r4,r4,27220
+ 8000b34:	8002d9c0 	call	8002d9c <puts>
+		control_pong(header);
+ 8000b38:	e0bffe17 	ldw	r2,-8(fp)
+ 8000b3c:	1009883a 	mov	r4,r2
+ 8000b40:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000b44:	00014206 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DEBUG_LED_OFF\n");
+ 8000b48:	01020134 	movhi	r4,2052
+ 8000b4c:	211a9904 	addi	r4,r4,27236
+ 8000b50:	8002d9c0 	call	8002d9c <puts>
+		led_clear(0);
+ 8000b54:	0009883a 	mov	r4,zero
+ 8000b58:	8002abc0 	call	8002abc <led_clear>
+		control_pong(header);
+ 8000b5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000b60:	1009883a 	mov	r4,r2
+ 8000b64:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000b68:	00013906 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DEBUG_LED_ON\n");
+ 8000b6c:	01020134 	movhi	r4,2052
+ 8000b70:	211a9f04 	addi	r4,r4,27260
+ 8000b74:	8002d9c0 	call	8002d9c <puts>
+		led_set(0);
+ 8000b78:	0009883a 	mov	r4,zero
+ 8000b7c:	8002a700 	call	8002a70 <led_set>
+		control_pong(header);
+ 8000b80:	e0bffe17 	ldw	r2,-8(fp)
+ 8000b84:	1009883a 	mov	r4,r2
+ 8000b88:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000b8c:	00013006 	br	8001050 <control_step+0x700>
+		printf("COMMAND_LEDS_DISABLE\n");
+ 8000b90:	01020134 	movhi	r4,2052
+ 8000b94:	211aa504 	addi	r4,r4,27284
+ 8000b98:	8002d9c0 	call	8002d9c <puts>
+		led4_blink_enable(0);
+ 8000b9c:	0009883a 	mov	r4,zero
+ 8000ba0:	8002b7c0 	call	8002b7c <led4_blink_enable>
+		control_pong(header);
+ 8000ba4:	e0bffe17 	ldw	r2,-8(fp)
+ 8000ba8:	1009883a 	mov	r4,r2
+ 8000bac:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000bb0:	00012706 	br	8001050 <control_step+0x700>
+		printf("COMMAND_LEDS_ENABLE\n");
+ 8000bb4:	01020134 	movhi	r4,2052
+ 8000bb8:	211aab04 	addi	r4,r4,27308
+ 8000bbc:	8002d9c0 	call	8002d9c <puts>
+		led4_blink_enable(1);
+ 8000bc0:	01000044 	movi	r4,1
+ 8000bc4:	8002b7c0 	call	8002b7c <led4_blink_enable>
+		control_pong(header);
+ 8000bc8:	e0bffe17 	ldw	r2,-8(fp)
+ 8000bcc:	1009883a 	mov	r4,r2
+ 8000bd0:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000bd4:	00011e06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_DISABLE\n");
+ 8000bd8:	01020134 	movhi	r4,2052
+ 8000bdc:	211ab004 	addi	r4,r4,27328
+ 8000be0:	8002d9c0 	call	8002d9c <puts>
+		master_clock_enable(0);
+ 8000be4:	0009883a 	mov	r4,zero
+ 8000be8:	8002a140 	call	8002a14 <master_clock_enable>
+		control_pong(header);
+ 8000bec:	e0bffe17 	ldw	r2,-8(fp)
+ 8000bf0:	1009883a 	mov	r4,r2
+ 8000bf4:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000bf8:	00011506 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_ENABLE\n");
+ 8000bfc:	01020134 	movhi	r4,2052
+ 8000c00:	211ab604 	addi	r4,r4,27352
+ 8000c04:	8002d9c0 	call	8002d9c <puts>
+		master_clock_enable(1);
+ 8000c08:	01000044 	movi	r4,1
+ 8000c0c:	8002a140 	call	8002a14 <master_clock_enable>
+		control_pong(header);
+ 8000c10:	e0bffe17 	ldw	r2,-8(fp)
+ 8000c14:	1009883a 	mov	r4,r2
+ 8000c18:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000c1c:	00010c06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_SLAVE\n");
+ 8000c20:	01020134 	movhi	r4,2052
+ 8000c24:	211abc04 	addi	r4,r4,27376
+ 8000c28:	8002d9c0 	call	8002d9c <puts>
+		masterslave(TRIGGER_SLAVE);
+ 8000c2c:	0009883a 	mov	r4,zero
+ 8000c30:	80029440 	call	8002944 <masterslave>
+		control_pong(header);
+ 8000c34:	e0bffe17 	ldw	r2,-8(fp)
+ 8000c38:	1009883a 	mov	r4,r2
+ 8000c3c:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000c40:	00010306 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_MASTER\n");
+ 8000c44:	01020134 	movhi	r4,2052
+ 8000c48:	211ac304 	addi	r4,r4,27404
+ 8000c4c:	8002d9c0 	call	8002d9c <puts>
+		masterslave(TRIGGER_MASTER);
+ 8000c50:	01000044 	movi	r4,1
+ 8000c54:	80029440 	call	8002944 <masterslave>
+		control_pong(header);
+ 8000c58:	e0bffe17 	ldw	r2,-8(fp)
+ 8000c5c:	1009883a 	mov	r4,r2
+ 8000c60:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000c64:	0000fa06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_PERIOD: %d\n", data[0]);
+ 8000c68:	e0bffd17 	ldw	r2,-12(fp)
+ 8000c6c:	1080000b 	ldhu	r2,0(r2)
+ 8000c70:	10bfffcc 	andi	r2,r2,65535
+ 8000c74:	100b883a 	mov	r5,r2
+ 8000c78:	01020134 	movhi	r4,2052
+ 8000c7c:	211aca04 	addi	r4,r4,27432
+ 8000c80:	8002c780 	call	8002c78 <printf>
+		master_clock_period((alt_u32)data[0]);	//we set only 16 lsbs!
+ 8000c84:	e0bffd17 	ldw	r2,-12(fp)
+ 8000c88:	1080000b 	ldhu	r2,0(r2)
+ 8000c8c:	10bfffcc 	andi	r2,r2,65535
+ 8000c90:	1009883a 	mov	r4,r2
+ 8000c94:	80029cc0 	call	80029cc <master_clock_period>
+		header->length = 0;
+ 8000c98:	e0bffe17 	ldw	r2,-8(fp)
+ 8000c9c:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000ca0:	e0bffe17 	ldw	r2,-8(fp)
+ 8000ca4:	1009883a 	mov	r4,r2
+ 8000ca8:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000cac:	0000e806 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_TINT: %d\n", data[0]);
+ 8000cb0:	e0bffd17 	ldw	r2,-12(fp)
+ 8000cb4:	1080000b 	ldhu	r2,0(r2)
+ 8000cb8:	10bfffcc 	andi	r2,r2,65535
+ 8000cbc:	100b883a 	mov	r5,r2
+ 8000cc0:	01020134 	movhi	r4,2052
+ 8000cc4:	211ad204 	addi	r4,r4,27464
+ 8000cc8:	8002c780 	call	8002c78 <printf>
+		sensor_set_shutter(SENSOR_INTERFACE_BASE, data[0]);
+ 8000ccc:	e0bffd17 	ldw	r2,-12(fp)
+ 8000cd0:	1080000b 	ldhu	r2,0(r2)
+ 8000cd4:	10ffffcc 	andi	r3,r2,65535
+ 8000cd8:	00861034 	movhi	r2,6208
+ 8000cdc:	10cf55ad 	sthio	r3,15702(r2)
+		header->length = 0;
+ 8000ce0:	e0bffe17 	ldw	r2,-8(fp)
+ 8000ce4:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000ce8:	e0bffe17 	ldw	r2,-8(fp)
+ 8000cec:	1009883a 	mov	r4,r2
+ 8000cf0:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000cf4:	0000d606 	br	8001050 <control_step+0x700>
+		printf("COMMAND_SET_GAIN: %d\n", data[0]);
+ 8000cf8:	e0bffd17 	ldw	r2,-12(fp)
+ 8000cfc:	1080000b 	ldhu	r2,0(r2)
+ 8000d00:	10bfffcc 	andi	r2,r2,65535
+ 8000d04:	100b883a 	mov	r5,r2
+ 8000d08:	01020134 	movhi	r4,2052
+ 8000d0c:	211ada04 	addi	r4,r4,27496
+ 8000d10:	8002c780 	call	8002c78 <printf>
+		sensor_set_gain(SENSOR_INTERFACE_BASE, data[0]);
+ 8000d14:	e0bffd17 	ldw	r2,-12(fp)
+ 8000d18:	1080000b 	ldhu	r2,0(r2)
+ 8000d1c:	10803fcc 	andi	r2,r2,255
+ 8000d20:	100d883a 	mov	r6,r2
+ 8000d24:	01400084 	movi	r5,2
+ 8000d28:	01061034 	movhi	r4,6208
+ 8000d2c:	210f5404 	addi	r4,r4,15696
+ 8000d30:	8001b800 	call	8001b80 <sensor_command_bit>
+		header->length = 0;
+ 8000d34:	e0bffe17 	ldw	r2,-8(fp)
+ 8000d38:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000d3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000d40:	1009883a 	mov	r4,r2
+ 8000d44:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000d48:	0000c106 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_MASTER_DELAY: %d\n", data[0]);
+ 8000d4c:	e0bffd17 	ldw	r2,-12(fp)
+ 8000d50:	1080000b 	ldhu	r2,0(r2)
+ 8000d54:	10bfffcc 	andi	r2,r2,65535
+ 8000d58:	100b883a 	mov	r5,r2
+ 8000d5c:	01020134 	movhi	r4,2052
+ 8000d60:	211ae004 	addi	r4,r4,27520
+ 8000d64:	8002c780 	call	8002c78 <printf>
+		set_delay(TRIGGER_MASTER, data[0]);
+ 8000d68:	e0bffd17 	ldw	r2,-12(fp)
+ 8000d6c:	1080000b 	ldhu	r2,0(r2)
+ 8000d70:	10bfffcc 	andi	r2,r2,65535
+ 8000d74:	100b883a 	mov	r5,r2
+ 8000d78:	01000044 	movi	r4,1
+ 8000d7c:	8002bc80 	call	8002bc8 <set_delay>
+		header->length = 0;
+ 8000d80:	e0bffe17 	ldw	r2,-8(fp)
+ 8000d84:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000d88:	e0bffe17 	ldw	r2,-8(fp)
+ 8000d8c:	1009883a 	mov	r4,r2
+ 8000d90:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000d94:	0000ae06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_TRIGGER_SET_SLAVE_DELAY: %d\n", data[0]);
+ 8000d98:	e0bffd17 	ldw	r2,-12(fp)
+ 8000d9c:	1080000b 	ldhu	r2,0(r2)
+ 8000da0:	10bfffcc 	andi	r2,r2,65535
+ 8000da4:	100b883a 	mov	r5,r2
+ 8000da8:	01020134 	movhi	r4,2052
+ 8000dac:	211aea04 	addi	r4,r4,27560
+ 8000db0:	8002c780 	call	8002c78 <printf>
+		set_delay(TRIGGER_SLAVE, data[0]);
+ 8000db4:	e0bffd17 	ldw	r2,-12(fp)
+ 8000db8:	1080000b 	ldhu	r2,0(r2)
+ 8000dbc:	10bfffcc 	andi	r2,r2,65535
+ 8000dc0:	100b883a 	mov	r5,r2
+ 8000dc4:	0009883a 	mov	r4,zero
+ 8000dc8:	8002bc80 	call	8002bc8 <set_delay>
+		header->length = 0;
+ 8000dcc:	e0bffe17 	ldw	r2,-8(fp)
+ 8000dd0:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000dd4:	e0bffe17 	ldw	r2,-8(fp)
+ 8000dd8:	1009883a 	mov	r4,r2
+ 8000ddc:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000de0:	00009b06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DAQ_DISABLE\n");
+ 8000de4:	01020134 	movhi	r4,2052
+ 8000de8:	211af404 	addi	r4,r4,27600
+ 8000dec:	8002d9c0 	call	8002d9c <puts>
+		sensor_set_enable(SENSOR_INTERFACE_BASE, 0);
+ 8000df0:	000d883a 	mov	r6,zero
+ 8000df4:	01400044 	movi	r5,1
+ 8000df8:	01061034 	movhi	r4,6208
+ 8000dfc:	210f5404 	addi	r4,r4,15696
+ 8000e00:	8001b800 	call	8001b80 <sensor_command_bit>
+		udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,0);
+ 8000e04:	000d883a 	mov	r6,zero
+ 8000e08:	01400044 	movi	r5,1
+ 8000e0c:	01061034 	movhi	r4,6208
+ 8000e10:	210f3004 	addi	r4,r4,15552
+ 8000e14:	80025540 	call	8002554 <udpgen_command_bit>
+		control_pong(header);
+ 8000e18:	e0bffe17 	ldw	r2,-8(fp)
+ 8000e1c:	1009883a 	mov	r4,r2
+ 8000e20:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000e24:	00008a06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DAQ_ENABLE\n");
+ 8000e28:	01020134 	movhi	r4,2052
+ 8000e2c:	211af904 	addi	r4,r4,27620
+ 8000e30:	8002d9c0 	call	8002d9c <puts>
+		udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,1);
+ 8000e34:	01800044 	movi	r6,1
+ 8000e38:	01400044 	movi	r5,1
+ 8000e3c:	01061034 	movhi	r4,6208
+ 8000e40:	210f3004 	addi	r4,r4,15552
+ 8000e44:	80025540 	call	8002554 <udpgen_command_bit>
+		sensor_set_enable(SENSOR_INTERFACE_BASE, 1);
+ 8000e48:	01800044 	movi	r6,1
+ 8000e4c:	01400044 	movi	r5,1
+ 8000e50:	01061034 	movhi	r4,6208
+ 8000e54:	210f5404 	addi	r4,r4,15696
+ 8000e58:	8001b800 	call	8001b80 <sensor_command_bit>
+		control_pong(header);
+ 8000e5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000e60:	1009883a 	mov	r4,r2
+ 8000e64:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000e68:	00007906 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DAQ_RESET_COUNTERS\n");
+ 8000e6c:	01020134 	movhi	r4,2052
+ 8000e70:	211afe04 	addi	r4,r4,27640
+ 8000e74:	8002d9c0 	call	8002d9c <puts>
+		sensor_reset(SENSOR_INTERFACE_BASE);
+ 8000e78:	01800044 	movi	r6,1
+ 8000e7c:	01400204 	movi	r5,8
+ 8000e80:	01061034 	movhi	r4,6208
+ 8000e84:	210f5404 	addi	r4,r4,15696
+ 8000e88:	8001b800 	call	8001b80 <sensor_command_bit>
+ 8000e8c:	000d883a 	mov	r6,zero
+ 8000e90:	01400204 	movi	r5,8
+ 8000e94:	01061034 	movhi	r4,6208
+ 8000e98:	210f5404 	addi	r4,r4,15696
+ 8000e9c:	8001b800 	call	8001b80 <sensor_command_bit>
+		control_pong(header);
+ 8000ea0:	e0bffe17 	ldw	r2,-8(fp)
+ 8000ea4:	1009883a 	mov	r4,r2
+ 8000ea8:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000eac:	00006806 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DAQ_FLUSH_DATA\n");
+ 8000eb0:	01020134 	movhi	r4,2052
+ 8000eb4:	211b0504 	addi	r4,r4,27668
+ 8000eb8:	8002d9c0 	call	8002d9c <puts>
+		control_pong(header);
+ 8000ebc:	e0bffe17 	ldw	r2,-8(fp)
+ 8000ec0:	1009883a 	mov	r4,r2
+ 8000ec4:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000ec8:	00006106 	br	8001050 <control_step+0x700>
+		printf("COMMAND_DAQ_CONFIG_PEER\n");
+ 8000ecc:	01020134 	movhi	r4,2052
+ 8000ed0:	211b0b04 	addi	r4,r4,27692
+ 8000ed4:	8002d9c0 	call	8002d9c <puts>
+		control_process_config_peer(data);
+ 8000ed8:	e0bffd17 	ldw	r2,-12(fp)
+ 8000edc:	1009883a 	mov	r4,r2
+ 8000ee0:	80004f80 	call	80004f8 <control_process_config_peer>
+		break;
+ 8000ee4:	00005a06 	br	8001050 <control_step+0x700>
+		printf("COMMAND_SLOWCTRL_SNAPSHOT\n");
+ 8000ee8:	01020134 	movhi	r4,2052
+ 8000eec:	211b1104 	addi	r4,r4,27716
+ 8000ef0:	8002d9c0 	call	8002d9c <puts>
+		control_process_snapshot();
+ 8000ef4:	80004180 	call	8000418 <control_process_snapshot>
+		break;
+ 8000ef8:	00005506 	br	8001050 <control_step+0x700>
+		printf("COMMAND_SET_CLUSTER_THRESHOLD: %d\n", data[0]);
+ 8000efc:	e0bffd17 	ldw	r2,-12(fp)
+ 8000f00:	1080000b 	ldhu	r2,0(r2)
+ 8000f04:	10bfffcc 	andi	r2,r2,65535
+ 8000f08:	100b883a 	mov	r5,r2
+ 8000f0c:	01020134 	movhi	r4,2052
+ 8000f10:	211b1804 	addi	r4,r4,27744
+ 8000f14:	8002c780 	call	8002c78 <printf>
+		sensor_set_cluster_threshold(SENSOR_INTERFACE_BASE,data[0]);
+ 8000f18:	e0bffd17 	ldw	r2,-12(fp)
+ 8000f1c:	1080000b 	ldhu	r2,0(r2)
+ 8000f20:	10ffffcc 	andi	r3,r2,65535
+ 8000f24:	00861034 	movhi	r2,6208
+ 8000f28:	10cf5725 	stbio	r3,15708(r2)
+		header->length = 0;
+ 8000f2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000f30:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000f34:	e0bffe17 	ldw	r2,-8(fp)
+ 8000f38:	1009883a 	mov	r4,r2
+ 8000f3c:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000f40:	00004306 	br	8001050 <control_step+0x700>
+		printf("COMMAND_SET_CLUSTER_SIZE: %d\n", data[0]);
+ 8000f44:	e0bffd17 	ldw	r2,-12(fp)
+ 8000f48:	1080000b 	ldhu	r2,0(r2)
+ 8000f4c:	10bfffcc 	andi	r2,r2,65535
+ 8000f50:	100b883a 	mov	r5,r2
+ 8000f54:	01020134 	movhi	r4,2052
+ 8000f58:	211b2104 	addi	r4,r4,27780
+ 8000f5c:	8002c780 	call	8002c78 <printf>
+		sensor_set_cluster_size(SENSOR_INTERFACE_BASE,data[0]);
+ 8000f60:	e0bffd17 	ldw	r2,-12(fp)
+ 8000f64:	1080000b 	ldhu	r2,0(r2)
+ 8000f68:	10ffffcc 	andi	r3,r2,65535
+ 8000f6c:	00861034 	movhi	r2,6208
+ 8000f70:	10cf5765 	stbio	r3,15709(r2)
+		header->length = 0;
+ 8000f74:	e0bffe17 	ldw	r2,-8(fp)
+ 8000f78:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 8000f7c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000f80:	1009883a 	mov	r4,r2
+ 8000f84:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8000f88:	00003106 	br	8001050 <control_step+0x700>
+		if (header->length>=2){
+ 8000f8c:	e0bffe17 	ldw	r2,-8(fp)
+ 8000f90:	1080010b 	ldhu	r2,4(r2)
+ 8000f94:	10bfffcc 	andi	r2,r2,65535
+ 8000f98:	108000b0 	cmpltui	r2,r2,2
+ 8000f9c:	10001a1e 	bne	r2,zero,8001008 <control_step+0x6b8>
+		calibration_ram_set_factor(CALIBRATION_RAM_BASE,data[0],data[1]); //i is channelID
+ 8000fa0:	e0bffd17 	ldw	r2,-12(fp)
+ 8000fa4:	1080000b 	ldhu	r2,0(r2)
+ 8000fa8:	10bfffcc 	andi	r2,r2,65535
+ 8000fac:	1085883a 	add	r2,r2,r2
+ 8000fb0:	1007883a 	mov	r3,r2
+ 8000fb4:	00861034 	movhi	r2,6208
+ 8000fb8:	108d0004 	addi	r2,r2,13312
+ 8000fbc:	1885883a 	add	r2,r3,r2
+ 8000fc0:	e0fffd17 	ldw	r3,-12(fp)
+ 8000fc4:	18c00084 	addi	r3,r3,2
+ 8000fc8:	18c0000b 	ldhu	r3,0(r3)
+ 8000fcc:	18ffffcc 	andi	r3,r3,65535
+ 8000fd0:	10c0002d 	sthio	r3,0(r2)
+		printf("COMMAND_SET_CALIBRATION_FACTOR ChannelIP%d : %d\n", data[0],data[1]);
+ 8000fd4:	e0bffd17 	ldw	r2,-12(fp)
+ 8000fd8:	1080000b 	ldhu	r2,0(r2)
+ 8000fdc:	10ffffcc 	andi	r3,r2,65535
+ 8000fe0:	e0bffd17 	ldw	r2,-12(fp)
+ 8000fe4:	10800084 	addi	r2,r2,2
+ 8000fe8:	1080000b 	ldhu	r2,0(r2)
+ 8000fec:	10bfffcc 	andi	r2,r2,65535
+ 8000ff0:	100d883a 	mov	r6,r2
+ 8000ff4:	180b883a 	mov	r5,r3
+ 8000ff8:	01020134 	movhi	r4,2052
+ 8000ffc:	211b2904 	addi	r4,r4,27812
+ 8001000:	8002c780 	call	8002c78 <printf>
+ 8001004:	00000706 	br	8001024 <control_step+0x6d4>
+			printf("COMMAND_SET_CALIBRATION_FACTOR length: %d\n", header->length);
+ 8001008:	e0bffe17 	ldw	r2,-8(fp)
+ 800100c:	1080010b 	ldhu	r2,4(r2)
+ 8001010:	10bfffcc 	andi	r2,r2,65535
+ 8001014:	100b883a 	mov	r5,r2
+ 8001018:	01020134 	movhi	r4,2052
+ 800101c:	211b3604 	addi	r4,r4,27864
+ 8001020:	8002c780 	call	8002c78 <printf>
+		header->length = 0;
+ 8001024:	e0bffe17 	ldw	r2,-8(fp)
+ 8001028:	1000010d 	sth	zero,4(r2)
+		control_pong(header);
+ 800102c:	e0bffe17 	ldw	r2,-8(fp)
+ 8001030:	1009883a 	mov	r4,r2
+ 8001034:	80003b00 	call	80003b0 <control_pong>
+		break;
+ 8001038:	00000506 	br	8001050 <control_step+0x700>
+			return;
+ 800103c:	0001883a 	nop
+ 8001040:	00000306 	br	8001050 <control_step+0x700>
+		return;
+ 8001044:	0001883a 	nop
+ 8001048:	00000106 	br	8001050 <control_step+0x700>
+			return;
+ 800104c:	0001883a 	nop
+	}
+
+}
+ 8001050:	e037883a 	mov	sp,fp
+ 8001054:	dfc00117 	ldw	ra,4(sp)
+ 8001058:	df000017 	ldw	fp,0(sp)
+ 800105c:	dec00204 	addi	sp,sp,8
+ 8001060:	f800283a 	ret
+
+08001064 <ControlTask>:
+      CONTROL_STACK_SIZE,
+};
+
+
+void ControlTask(void* param)
+{
+ 8001064:	defffc04 	addi	sp,sp,-16
+ 8001068:	dfc00315 	stw	ra,12(sp)
+ 800106c:	df000215 	stw	fp,8(sp)
+ 8001070:	df000204 	addi	fp,sp,8
+ 8001074:	e13ffe15 	stw	r4,-8(fp)
+	printf ("::: Control task started ::: \n");
+ 8001078:	01020134 	movhi	r4,2052
+ 800107c:	211b4504 	addi	r4,r4,27924
+ 8001080:	8002d9c0 	call	8002d9c <puts>
+	ethernet_listen(0, CONTROL_PORT);
+ 8001084:	0143e804 	movi	r5,4000
+ 8001088:	0009883a 	mov	r4,zero
+ 800108c:	80020d00 	call	80020d0 <ethernet_listen>
+
+	sensor_preconfigure(SENSOR_INTERFACE_BASE);
+ 8001090:	01061034 	movhi	r4,6208
+ 8001094:	210f5404 	addi	r4,r4,15696
+ 8001098:	8001c080 	call	8001c08 <sensor_preconfigure>
+
+	//initial calibration factor here
+	printf("Initiate Calibration Factor 1 to 320 from channel1 to channel320 \n");
+ 800109c:	01020134 	movhi	r4,2052
+ 80010a0:	211b4d04 	addi	r4,r4,27956
+ 80010a4:	8002d9c0 	call	8002d9c <puts>
+
+
+	for (alt_u32 i = 0; i < 320; i++) {
+ 80010a8:	e03fff15 	stw	zero,-4(fp)
+ 80010ac:	00000b06 	br	80010dc <ControlTask+0x78>
+		//pow(2,13)=8192. represent calibration factor 1; range[0.00012,8)
+		//default calibration factor is 1.
+		calibration_ram_set_factor(CALIBRATION_RAM_BASE,i,8192); //i is channelID
+ 80010b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80010b4:	1085883a 	add	r2,r2,r2
+ 80010b8:	1007883a 	mov	r3,r2
+ 80010bc:	00861034 	movhi	r2,6208
+ 80010c0:	108d0004 	addi	r2,r2,13312
+ 80010c4:	1885883a 	add	r2,r3,r2
+ 80010c8:	00c80004 	movi	r3,8192
+ 80010cc:	10c0002d 	sthio	r3,0(r2)
+	for (alt_u32 i = 0; i < 320; i++) {
+ 80010d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80010d4:	10800044 	addi	r2,r2,1
+ 80010d8:	e0bfff15 	stw	r2,-4(fp)
+ 80010dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80010e0:	10805030 	cmpltui	r2,r2,320
+ 80010e4:	103ff21e 	bne	r2,zero,80010b0 <ControlTask+0x4c>
+	 }
+
+	while(1)
+		control_step();
+ 80010e8:	80009500 	call	8000950 <control_step>
+ 80010ec:	003ffe06 	br	80010e8 <ControlTask+0x84>
+
+080010f0 <control_init>:
+}
+
+void control_init()
+{
+ 80010f0:	defffe04 	addi	sp,sp,-8
+ 80010f4:	dfc00115 	stw	ra,4(sp)
+ 80010f8:	df000015 	stw	fp,0(sp)
+ 80010fc:	d839883a 	mov	fp,sp
+	TK_NEWTASK(&controltask);
+ 8001100:	01020174 	movhi	r4,2053
+ 8001104:	212e4804 	addi	r4,r4,-18144
+ 8001108:	80290740 	call	8029074 <TK_NEWTASK>
+}
+ 800110c:	0001883a 	nop
+ 8001110:	e037883a 	mov	sp,fp
+ 8001114:	dfc00117 	ldw	ra,4(sp)
+ 8001118:	df000017 	ldw	fp,0(sp)
+ 800111c:	dec00204 	addi	sp,sp,8
+ 8001120:	f800283a 	ret
+
+08001124 <InitialTask>:
+/* InitialTask will initialize the NicheStack
+ * TCP/IP Stack and then initialize the rest of the Simple Socket Server example 
+ * RTOS structures and tasks. 
+ */
+void InitialTask(void *task_data)
+{
+ 8001124:	defffc04 	addi	sp,sp,-16
+ 8001128:	dfc00315 	stw	ra,12(sp)
+ 800112c:	df000215 	stw	fp,8(sp)
+ 8001130:	df000204 	addi	fp,sp,8
+ 8001134:	e13ffe15 	stw	r4,-8(fp)
+   * I/O drivers are available.  Two tasks are created:
+   *    "Inet main"  task with priority 2
+   *    "clock tick" task with priority 3
+   */   
+
+  alt_iniche_init();
+ 8001138:	80293dc0 	call	80293dc <alt_iniche_init>
+  netmain(); 
+ 800113c:	80278140 	call	8027814 <netmain>
+
+  /* Wait for the network stack to be ready before proceeding. 
+   * iniche_net_ready indicates that TCP/IP stack is ready, and IP address is obtained.
+   */
+  while (!iniche_net_ready){
+ 8001140:	00000206 	br	800114c <InitialTask+0x28>
+    TK_SLEEP(1);
+ 8001144:	01000084 	movi	r4,2
+ 8001148:	801730c0 	call	801730c <OSTimeDly>
+  while (!iniche_net_ready){
+ 800114c:	d0a06f17 	ldw	r2,-32324(gp)
+ 8001150:	103ffc26 	beq	r2,zero,8001144 <InitialTask+0x20>
+
+  /* Now that the stack is running, perform the application initialization steps */
+  
+  /* Application Specific Task Launching Code Block Begin */
+
+  printf("\nSocket Server starting up\n");
+ 8001154:	01020134 	movhi	r4,2052
+ 8001158:	211b5e04 	addi	r4,r4,28024
+ 800115c:	8002d9c0 	call	8002d9c <puts>
+
+  /* Create tasks */
+  ethernet_init();
+ 8001160:	80020500 	call	8002050 <ethernet_init>
+  control_init();
+ 8001164:	80010f00 	call	80010f0 <control_init>
+  //TK_NEWTASK(&ssconntask);
+  
+  /* Application Specific Task Launching Code Block End */
+  
+  /*This task is deleted because there is no need for it to run again */
+  error_code = OSTaskDel(OS_PRIO_SELF);
+ 8001168:	01003fc4 	movi	r4,255
+ 800116c:	80167f00 	call	80167f0 <OSTaskDel>
+ 8001170:	e0bfffc5 	stb	r2,-1(fp)
+  //alt_uCOSIIErrorHandler(error_code, 0);
+  
+  while (1); /* Correct Program Flow should never get here */
+ 8001174:	003fff06 	br	8001174 <InitialTask+0x50>
+
+08001178 <main>:
+
+/* Main creates a single task, SSSInitialTask, and starts task scheduler.
+ */
+
+int main (int argc, char* argv[], char* envp[])
+{
+ 8001178:	defff504 	addi	sp,sp,-44
+ 800117c:	dfc00a15 	stw	ra,40(sp)
+ 8001180:	df000915 	stw	fp,36(sp)
+ 8001184:	df000904 	addi	fp,sp,36
+ 8001188:	e13ffe15 	stw	r4,-8(fp)
+ 800118c:	e17ffd15 	stw	r5,-12(fp)
+ 8001190:	e1bffc15 	stw	r6,-16(fp)
+  
+  INT8U error_code;
+
+  /* Clear the RTOS timer */
+  OSTimeSet(0);
+ 8001194:	0009883a 	mov	r4,zero
+ 8001198:	80177340 	call	8017734 <OSTimeSet>
+
+  /* SSSInitialTask will initialize the NicheStack
+   * TCP/IP Stack and then initialize the rest of the Simple Socket Server example
+   * RTOS structures and tasks.
+   */
+  error_code = OSTaskCreateExt(InitialTask,
+ 800119c:	d8000415 	stw	zero,16(sp)
+ 80011a0:	d8000315 	stw	zero,12(sp)
+ 80011a4:	008e0004 	movi	r2,14336
+ 80011a8:	d8800215 	stw	r2,8(sp)
+ 80011ac:	00820174 	movhi	r2,2053
+ 80011b0:	10b38b04 	addi	r2,r2,-12756
+ 80011b4:	d8800115 	stw	r2,4(sp)
+ 80011b8:	00800144 	movi	r2,5
+ 80011bc:	d8800015 	stw	r2,0(sp)
+ 80011c0:	01c00144 	movi	r7,5
+ 80011c4:	018201b4 	movhi	r6,2054
+ 80011c8:	31ab8b04 	addi	r6,r6,-20948
+ 80011cc:	000b883a 	mov	r5,zero
+ 80011d0:	01020034 	movhi	r4,2048
+ 80011d4:	21044904 	addi	r4,r4,4388
+ 80011d8:	801664c0 	call	801664c <OSTaskCreateExt>
+ 80011dc:	e0bfffc5 	stb	r2,-1(fp)
+
+  /*
+   * As with all MicroC/OS-II designs, once the initial thread(s) and
+   * associated RTOS resources are declared, we start the RTOS. That's it!
+   */
+  OSStart();
+ 80011e0:	8010a700 	call	8010a70 <OSStart>
+
+
+  
+  while(1); /* Correct Program Flow never gets here. */
+ 80011e4:	003fff06 	br	80011e4 <main+0x6c>
+
+080011e8 <get_mac_addr>:
+* Read the MAC address in a board specific way. Prompt user to enter serial 
+* number to generate MAC address if failed to read from flash.
+*
+*/
+int get_mac_addr(NET net, unsigned char mac_addr[6])
+{
+ 80011e8:	defffb04 	addi	sp,sp,-20
+ 80011ec:	dfc00415 	stw	ra,16(sp)
+ 80011f0:	df000315 	stw	fp,12(sp)
+ 80011f4:	df000304 	addi	fp,sp,12
+ 80011f8:	e13ffe15 	stw	r4,-8(fp)
+ 80011fc:	e17ffd15 	stw	r5,-12(fp)
+    error_t error = 0;
+ 8001200:	e03fff15 	stw	zero,-4(fp)
+    
+    error = get_board_mac_addr(mac_addr);
+ 8001204:	e13ffd17 	ldw	r4,-12(fp)
+ 8001208:	80018b40 	call	80018b4 <get_board_mac_addr>
+ 800120c:	e0bfff15 	stw	r2,-4(fp)
+    
+    if(error)
+ 8001210:	e0bfff17 	ldw	r2,-4(fp)
+ 8001214:	10000326 	beq	r2,zero,8001224 <get_mac_addr+0x3c>
+    {
+        /* Failed read MAC address from flash, prompt user to enter serial 
+           number to generate MAC address. */
+        error = generate_mac_addr(mac_addr);
+ 8001218:	e13ffd17 	ldw	r4,-12(fp)
+ 800121c:	80017800 	call	8001780 <generate_mac_addr>
+ 8001220:	e0bfff15 	stw	r2,-4(fp)
+    }
+    return error;
+ 8001224:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8001228:	e037883a 	mov	sp,fp
+ 800122c:	dfc00117 	ldw	ra,4(sp)
+ 8001230:	df000017 	ldw	fp,0(sp)
+ 8001234:	dec00204 	addi	sp,sp,8
+ 8001238:	f800283a 	ret
+
+0800123c <get_ip_addr>:
+int get_ip_addr(alt_iniche_dev *p_dev,
+                ip_addr* ipaddr,
+                ip_addr* netmask,
+                ip_addr* gw,
+                int* use_dhcp)
+{
+ 800123c:	defff804 	addi	sp,sp,-32
+ 8001240:	dfc00715 	stw	ra,28(sp)
+ 8001244:	df000615 	stw	fp,24(sp)
+ 8001248:	df000604 	addi	fp,sp,24
+ 800124c:	e13ffe15 	stw	r4,-8(fp)
+ 8001250:	e17ffd15 	stw	r5,-12(fp)
+ 8001254:	e1bffc15 	stw	r6,-16(fp)
+ 8001258:	e1fffb15 	stw	r7,-20(fp)
+
+	alt_u32 sw_state = ~(IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE));
+ 800125c:	00861034 	movhi	r2,6208
+ 8001260:	108f5037 	ldwio	r2,15680(r2)
+ 8001264:	0084303a 	nor	r2,zero,r2
+ 8001268:	e0bfff15 	stw	r2,-4(fp)
+
+    printf("Input state: 0x%08lx\n", sw_state);
+ 800126c:	e17fff17 	ldw	r5,-4(fp)
+ 8001270:	01020134 	movhi	r4,2052
+ 8001274:	211b6504 	addi	r4,r4,28052
+ 8001278:	8002c780 	call	8002c78 <printf>
+    		IP4_ADDR(*netmask, 0, 0, 0, 0);
+    		printf("DHCP enabled.\n");
+    }
+    else
+    {*/
+    	*use_dhcp = 0;
+ 800127c:	e0800217 	ldw	r2,8(fp)
+ 8001280:	10000015 	stw	zero,0(r2)
+        IP4_ADDR(*ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3+((sw_state>>4)&0x0F));
+ 8001284:	e0bfff17 	ldw	r2,-4(fp)
+ 8001288:	1004d13a 	srli	r2,r2,4
+ 800128c:	108003cc 	andi	r2,r2,15
+ 8001290:	10800404 	addi	r2,r2,16
+ 8001294:	1006963a 	slli	r3,r2,24
+ 8001298:	008001f4 	movhi	r2,7
+ 800129c:	10800284 	addi	r2,r2,10
+ 80012a0:	1886b03a 	or	r3,r3,r2
+ 80012a4:	e0bffd17 	ldw	r2,-12(fp)
+ 80012a8:	10c00015 	stw	r3,0(r2)
+        IP4_ADDR(*gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3);
+ 80012ac:	e0fffb17 	ldw	r3,-20(fp)
+ 80012b0:	008041f4 	movhi	r2,263
+ 80012b4:	10800284 	addi	r2,r2,10
+ 80012b8:	18800015 	stw	r2,0(r3)
+        IP4_ADDR(*netmask, MSKADDR0, MSKADDR1, MSKADDR2, MSKADDR3);
+ 80012bc:	e0fffc17 	ldw	r3,-16(fp)
+ 80012c0:	00804034 	movhi	r2,256
+ 80012c4:	10bfffc4 	addi	r2,r2,-1
+ 80012c8:	18800015 	stw	r2,0(r3)
+        printf("DHCP disabled.\n");
+ 80012cc:	01020134 	movhi	r4,2052
+ 80012d0:	211b6b04 	addi	r4,r4,28076
+ 80012d4:	8002d9c0 	call	8002d9c <puts>
+        printf("Static IP Address is %d.%d.%d.%d\n",
+            ip4_addr1(*ipaddr),
+ 80012d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80012dc:	10800017 	ldw	r2,0(r2)
+ 80012e0:	1006d63a 	srli	r3,r2,24
+ 80012e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80012e8:	10800017 	ldw	r2,0(r2)
+ 80012ec:	1004d23a 	srli	r2,r2,8
+ 80012f0:	10bfc00c 	andi	r2,r2,65280
+ 80012f4:	1886b03a 	or	r3,r3,r2
+ 80012f8:	e0bffd17 	ldw	r2,-12(fp)
+ 80012fc:	10800017 	ldw	r2,0(r2)
+ 8001300:	1004923a 	slli	r2,r2,8
+ 8001304:	10803fec 	andhi	r2,r2,255
+ 8001308:	1886b03a 	or	r3,r3,r2
+ 800130c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001310:	10800017 	ldw	r2,0(r2)
+ 8001314:	1004963a 	slli	r2,r2,24
+ 8001318:	1884b03a 	or	r2,r3,r2
+ 800131c:	1008d63a 	srli	r4,r2,24
+            ip4_addr2(*ipaddr),
+ 8001320:	e0bffd17 	ldw	r2,-12(fp)
+ 8001324:	10800017 	ldw	r2,0(r2)
+ 8001328:	1006d63a 	srli	r3,r2,24
+ 800132c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001330:	10800017 	ldw	r2,0(r2)
+ 8001334:	1004d23a 	srli	r2,r2,8
+ 8001338:	10bfc00c 	andi	r2,r2,65280
+ 800133c:	1886b03a 	or	r3,r3,r2
+ 8001340:	e0bffd17 	ldw	r2,-12(fp)
+ 8001344:	10800017 	ldw	r2,0(r2)
+ 8001348:	1004923a 	slli	r2,r2,8
+ 800134c:	10803fec 	andhi	r2,r2,255
+ 8001350:	1886b03a 	or	r3,r3,r2
+ 8001354:	e0bffd17 	ldw	r2,-12(fp)
+ 8001358:	10800017 	ldw	r2,0(r2)
+ 800135c:	1004963a 	slli	r2,r2,24
+ 8001360:	1884b03a 	or	r2,r3,r2
+ 8001364:	1004d43a 	srli	r2,r2,16
+        printf("Static IP Address is %d.%d.%d.%d\n",
+ 8001368:	11403fcc 	andi	r5,r2,255
+            ip4_addr3(*ipaddr),
+ 800136c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001370:	10800017 	ldw	r2,0(r2)
+ 8001374:	1006d63a 	srli	r3,r2,24
+ 8001378:	e0bffd17 	ldw	r2,-12(fp)
+ 800137c:	10800017 	ldw	r2,0(r2)
+ 8001380:	1004d23a 	srli	r2,r2,8
+ 8001384:	10bfc00c 	andi	r2,r2,65280
+ 8001388:	1886b03a 	or	r3,r3,r2
+ 800138c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001390:	10800017 	ldw	r2,0(r2)
+ 8001394:	1004923a 	slli	r2,r2,8
+ 8001398:	10803fec 	andhi	r2,r2,255
+ 800139c:	1886b03a 	or	r3,r3,r2
+ 80013a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80013a4:	10800017 	ldw	r2,0(r2)
+ 80013a8:	1004963a 	slli	r2,r2,24
+ 80013ac:	1884b03a 	or	r2,r3,r2
+ 80013b0:	1004d23a 	srli	r2,r2,8
+        printf("Static IP Address is %d.%d.%d.%d\n",
+ 80013b4:	11803fcc 	andi	r6,r2,255
+            ip4_addr4(*ipaddr));
+ 80013b8:	e0bffd17 	ldw	r2,-12(fp)
+ 80013bc:	10800017 	ldw	r2,0(r2)
+ 80013c0:	1006d63a 	srli	r3,r2,24
+ 80013c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80013c8:	10800017 	ldw	r2,0(r2)
+ 80013cc:	1004d23a 	srli	r2,r2,8
+ 80013d0:	10bfc00c 	andi	r2,r2,65280
+ 80013d4:	1886b03a 	or	r3,r3,r2
+ 80013d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80013dc:	10800017 	ldw	r2,0(r2)
+ 80013e0:	1004923a 	slli	r2,r2,8
+ 80013e4:	10803fec 	andhi	r2,r2,255
+ 80013e8:	1886b03a 	or	r3,r3,r2
+ 80013ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80013f0:	10800017 	ldw	r2,0(r2)
+ 80013f4:	1004963a 	slli	r2,r2,24
+ 80013f8:	1884b03a 	or	r2,r3,r2
+        printf("Static IP Address is %d.%d.%d.%d\n",
+ 80013fc:	10803fcc 	andi	r2,r2,255
+ 8001400:	d8800015 	stw	r2,0(sp)
+ 8001404:	300f883a 	mov	r7,r6
+ 8001408:	280d883a 	mov	r6,r5
+ 800140c:	200b883a 	mov	r5,r4
+ 8001410:	01020134 	movhi	r4,2052
+ 8001414:	211b6f04 	addi	r4,r4,28092
+ 8001418:	8002c780 	call	8002c78 <printf>
+    //}
+
+
+    /* Non-standard API: return 1 for success */
+    return 1;
+ 800141c:	00800044 	movi	r2,1
+}
+ 8001420:	e037883a 	mov	sp,fp
+ 8001424:	dfc00117 	ldw	ra,4(sp)
+ 8001428:	df000017 	ldw	fp,0(sp)
+ 800142c:	dec00204 	addi	sp,sp,8
+ 8001430:	f800283a 	ret
+
+08001434 <get_serial_number>:
+*
+* Prompt user to enter 9-digit serial number. 
+*
+*/
+alt_u32 get_serial_number (void)
+{
+ 8001434:	defff904 	addi	sp,sp,-28
+ 8001438:	dfc00615 	stw	ra,24(sp)
+ 800143c:	df000515 	stw	fp,20(sp)
+ 8001440:	df000504 	addi	fp,sp,20
+    alt_u32 ser_num = 0;
+ 8001444:	e03fff15 	stw	zero,-4(fp)
+    char serial_number[9];
+    int i = 0;
+ 8001448:	e03ffe15 	stw	zero,-8(fp)
+    
+    while(!ser_num)
+ 800144c:	00005606 	br	80015a8 <get_serial_number+0x174>
+    {
+        printf("Please enter your 9-digit serial number. This is printed on a \n");
+ 8001450:	01020134 	movhi	r4,2052
+ 8001454:	211b7804 	addi	r4,r4,28128
+ 8001458:	8002d9c0 	call	8002d9c <puts>
+        printf("label under your Nios dev. board. The first 3 digits of the \n");
+ 800145c:	01020134 	movhi	r4,2052
+ 8001460:	211b8804 	addi	r4,r4,28192
+ 8001464:	8002d9c0 	call	8002d9c <puts>
+        printf("label are ASJ and the serial number follows this.\n -->");
+ 8001468:	01020134 	movhi	r4,2052
+ 800146c:	211b9804 	addi	r4,r4,28256
+ 8001470:	8002c780 	call	8002c78 <printf>
+        
+        for(i=0; i<9; i++)
+ 8001474:	e03ffe15 	stw	zero,-8(fp)
+ 8001478:	00001d06 	br	80014f0 <get_serial_number+0xbc>
+        {
+            serial_number[i] = getchar();
+ 800147c:	8002c380 	call	8002c38 <getchar>
+ 8001480:	1007883a 	mov	r3,r2
+ 8001484:	e0bffe17 	ldw	r2,-8(fp)
+ 8001488:	e085883a 	add	r2,fp,r2
+ 800148c:	10fffbc5 	stb	r3,-17(r2)
+            putchar(serial_number[i]);
+ 8001490:	e0bffe17 	ldw	r2,-8(fp)
+ 8001494:	e085883a 	add	r2,fp,r2
+ 8001498:	10bffbc3 	ldbu	r2,-17(r2)
+ 800149c:	10803fcc 	andi	r2,r2,255
+ 80014a0:	1080201c 	xori	r2,r2,128
+ 80014a4:	10bfe004 	addi	r2,r2,-128
+ 80014a8:	1009883a 	mov	r4,r2
+ 80014ac:	8002cb80 	call	8002cb8 <putchar>
+            
+            /* Handle backspaces.  How civilized. */
+            if ((serial_number[i] == 0x08) && (i >= 0)) 
+ 80014b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80014b4:	e085883a 	add	r2,fp,r2
+ 80014b8:	10bffbc3 	ldbu	r2,-17(r2)
+ 80014bc:	10803fcc 	andi	r2,r2,255
+ 80014c0:	1080201c 	xori	r2,r2,128
+ 80014c4:	10bfe004 	addi	r2,r2,-128
+ 80014c8:	10800218 	cmpnei	r2,r2,8
+ 80014cc:	1000051e 	bne	r2,zero,80014e4 <get_serial_number+0xb0>
+ 80014d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80014d4:	10000316 	blt	r2,zero,80014e4 <get_serial_number+0xb0>
+            {
+                i--;
+ 80014d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80014dc:	10bfffc4 	addi	r2,r2,-1
+ 80014e0:	e0bffe15 	stw	r2,-8(fp)
+        for(i=0; i<9; i++)
+ 80014e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80014e8:	10800044 	addi	r2,r2,1
+ 80014ec:	e0bffe15 	stw	r2,-8(fp)
+ 80014f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80014f4:	10800250 	cmplti	r2,r2,9
+ 80014f8:	103fe01e 	bne	r2,zero,800147c <get_serial_number+0x48>
+            }
+        }
+        printf("\n");
+ 80014fc:	01000284 	movi	r4,10
+ 8001500:	8002cb80 	call	8002cb8 <putchar>
+                
+        for(i=0; i<9; i++)
+ 8001504:	e03ffe15 	stw	zero,-8(fp)
+ 8001508:	00002406 	br	800159c <get_serial_number+0x168>
+        {
+            if (isdigit(serial_number[i]))
+ 800150c:	e0bffe17 	ldw	r2,-8(fp)
+ 8001510:	e085883a 	add	r2,fp,r2
+ 8001514:	10bffbc3 	ldbu	r2,-17(r2)
+ 8001518:	10803fcc 	andi	r2,r2,255
+ 800151c:	1080201c 	xori	r2,r2,128
+ 8001520:	10bfe004 	addi	r2,r2,-128
+ 8001524:	10c00044 	addi	r3,r2,1
+ 8001528:	00820134 	movhi	r2,2052
+ 800152c:	109c7584 	addi	r2,r2,29142
+ 8001530:	1885883a 	add	r2,r3,r2
+ 8001534:	10800003 	ldbu	r2,0(r2)
+ 8001538:	10803fcc 	andi	r2,r2,255
+ 800153c:	1080010c 	andi	r2,r2,4
+ 8001540:	10000e26 	beq	r2,zero,800157c <get_serial_number+0x148>
+            {
+                ser_num *= 10;
+ 8001544:	e0bfff17 	ldw	r2,-4(fp)
+ 8001548:	108002a4 	muli	r2,r2,10
+ 800154c:	e0bfff15 	stw	r2,-4(fp)
+                ser_num += serial_number[i] - '0';
+ 8001550:	e0bffe17 	ldw	r2,-8(fp)
+ 8001554:	e085883a 	add	r2,fp,r2
+ 8001558:	10bffbc3 	ldbu	r2,-17(r2)
+ 800155c:	10c03fcc 	andi	r3,r2,255
+ 8001560:	18c0201c 	xori	r3,r3,128
+ 8001564:	18ffe004 	addi	r3,r3,-128
+ 8001568:	e0bfff17 	ldw	r2,-4(fp)
+ 800156c:	1885883a 	add	r2,r3,r2
+ 8001570:	10bff404 	addi	r2,r2,-48
+ 8001574:	e0bfff15 	stw	r2,-4(fp)
+ 8001578:	00000506 	br	8001590 <get_serial_number+0x15c>
+            }
+            else
+            {
+                ser_num = 0;
+ 800157c:	e03fff15 	stw	zero,-4(fp)
+                printf("Serial number only contains decimal digits and is non-zero\n");
+ 8001580:	01020134 	movhi	r4,2052
+ 8001584:	211ba604 	addi	r4,r4,28312
+ 8001588:	8002d9c0 	call	8002d9c <puts>
+                break;
+ 800158c:	00000606 	br	80015a8 <get_serial_number+0x174>
+        for(i=0; i<9; i++)
+ 8001590:	e0bffe17 	ldw	r2,-8(fp)
+ 8001594:	10800044 	addi	r2,r2,1
+ 8001598:	e0bffe15 	stw	r2,-8(fp)
+ 800159c:	e0bffe17 	ldw	r2,-8(fp)
+ 80015a0:	10800250 	cmplti	r2,r2,9
+ 80015a4:	103fd91e 	bne	r2,zero,800150c <get_serial_number+0xd8>
+    while(!ser_num)
+ 80015a8:	e0bfff17 	ldw	r2,-4(fp)
+ 80015ac:	103fa826 	beq	r2,zero,8001450 <get_serial_number+0x1c>
+            }
+        }
+    }
+    
+    return ser_num;
+ 80015b0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80015b4:	e037883a 	mov	sp,fp
+ 80015b8:	dfc00117 	ldw	ra,4(sp)
+ 80015bc:	df000017 	ldw	fp,0(sp)
+ 80015c0:	dec00204 	addi	sp,sp,8
+ 80015c4:	f800283a 	ret
+
+080015c8 <generate_and_store_mac_addr>:
+ * sections. These fail-safe static settings are compatible with previous
+ * Nios Ethernet designs, and allow the "factory-safe" design to behave 
+ * as expected if the last flash sector is erased.
+ */
+error_t generate_and_store_mac_addr()
+{
+ 80015c8:	deffef04 	addi	sp,sp,-68
+ 80015cc:	dfc01015 	stw	ra,64(sp)
+ 80015d0:	df000f15 	stw	fp,60(sp)
+ 80015d4:	df000f04 	addi	fp,sp,60
+    error_t error = -1;
+ 80015d8:	00bfffc4 	movi	r2,-1
+ 80015dc:	e0bfff15 	stw	r2,-4(fp)
+    alt_u32 ser_num = 0;
+ 80015e0:	e03ffe15 	stw	zero,-8(fp)
+    char flash_content[32];
+    alt_flash_fd* flash_handle;
+    
+    printf("Can't read the MAC address from your board (this probably means\n");
+ 80015e4:	01020134 	movhi	r4,2052
+ 80015e8:	211bb504 	addi	r4,r4,28372
+ 80015ec:	8002d9c0 	call	8002d9c <puts>
+    printf("that your flash was erased). We will assign you a MAC address and\n");
+ 80015f0:	01020134 	movhi	r4,2052
+ 80015f4:	211bc504 	addi	r4,r4,28436
+ 80015f8:	8002d9c0 	call	8002d9c <puts>
+    printf("static network settings\n\n");
+ 80015fc:	01020134 	movhi	r4,2052
+ 8001600:	211bd604 	addi	r4,r4,28504
+ 8001604:	8002d9c0 	call	8002d9c <puts>
+    
+    ser_num = get_serial_number();
+ 8001608:	80014340 	call	8001434 <get_serial_number>
+ 800160c:	e0bffe15 	stw	r2,-8(fp)
+  
+    if (ser_num)
+ 8001610:	e0bffe17 	ldw	r2,-8(fp)
+ 8001614:	10005426 	beq	r2,zero,8001768 <generate_and_store_mac_addr+0x1a0>
+    {
+        /* This says the image is safe */
+        flash_content[0] = 0xfe;
+ 8001618:	00bfff84 	movi	r2,-2
+ 800161c:	e0bff105 	stb	r2,-60(fp)
+        flash_content[1] = 0x5a;
+ 8001620:	00801684 	movi	r2,90
+ 8001624:	e0bff145 	stb	r2,-59(fp)
+        flash_content[2] = 0x0;
+ 8001628:	e03ff185 	stb	zero,-58(fp)
+        flash_content[3] = 0x0;
+ 800162c:	e03ff1c5 	stb	zero,-57(fp)
+        
+        /* This is the Altera Vendor ID */
+        flash_content[4] = 0x0;
+ 8001630:	e03ff205 	stb	zero,-56(fp)
+        flash_content[5] = 0x7;
+ 8001634:	008001c4 	movi	r2,7
+ 8001638:	e0bff245 	stb	r2,-55(fp)
+        flash_content[6] = 0xed;
+ 800163c:	00bffb44 	movi	r2,-19
+ 8001640:	e0bff285 	stb	r2,-54(fp)
+        
+        /* Reserverd Board identifier for erase boards */
+        flash_content[7] = 0xFF;
+ 8001644:	00bfffc4 	movi	r2,-1
+ 8001648:	e0bff2c5 	stb	r2,-53(fp)
+        flash_content[8] = (ser_num & 0xff00) >> 8;
+ 800164c:	e0bffe17 	ldw	r2,-8(fp)
+ 8001650:	1004d23a 	srli	r2,r2,8
+ 8001654:	e0bff305 	stb	r2,-52(fp)
+        flash_content[9] = ser_num & 0xff;
+ 8001658:	e0bffe17 	ldw	r2,-8(fp)
+ 800165c:	e0bff345 	stb	r2,-51(fp)
+        
+        /* Then comes a 16-bit "flags" field */
+        flash_content[10] = 0xFF;
+ 8001660:	00bfffc4 	movi	r2,-1
+ 8001664:	e0bff385 	stb	r2,-50(fp)
+        flash_content[11] = 0xFF;
+ 8001668:	00bfffc4 	movi	r2,-1
+ 800166c:	e0bff3c5 	stb	r2,-49(fp)
+        
+        /* Then comes the static IP address */
+        flash_content[12] = IPADDR0;
+ 8001670:	00800284 	movi	r2,10
+ 8001674:	e0bff405 	stb	r2,-48(fp)
+        flash_content[13] = IPADDR1;
+ 8001678:	e03ff445 	stb	zero,-47(fp)
+        flash_content[14] = IPADDR2;
+ 800167c:	008001c4 	movi	r2,7
+ 8001680:	e0bff485 	stb	r2,-46(fp)
+        flash_content[15] = IPADDR3;
+ 8001684:	00800404 	movi	r2,16
+ 8001688:	e0bff4c5 	stb	r2,-45(fp)
+        
+        /* Then comes the static nameserver address */
+        flash_content[16] = 0xFF;
+ 800168c:	00bfffc4 	movi	r2,-1
+ 8001690:	e0bff505 	stb	r2,-44(fp)
+        flash_content[17] = 0xFF;
+ 8001694:	00bfffc4 	movi	r2,-1
+ 8001698:	e0bff545 	stb	r2,-43(fp)
+        flash_content[18] = 0xFF;
+ 800169c:	00bfffc4 	movi	r2,-1
+ 80016a0:	e0bff585 	stb	r2,-42(fp)
+        flash_content[19] = 0xFF;
+ 80016a4:	00bfffc4 	movi	r2,-1
+ 80016a8:	e0bff5c5 	stb	r2,-41(fp)
+        
+        /* Then comes the static subnet mask */
+        flash_content[20] = MSKADDR0;
+ 80016ac:	00bfffc4 	movi	r2,-1
+ 80016b0:	e0bff605 	stb	r2,-40(fp)
+        flash_content[21] = MSKADDR1;
+ 80016b4:	00bfffc4 	movi	r2,-1
+ 80016b8:	e0bff645 	stb	r2,-39(fp)
+        flash_content[22] = MSKADDR2;
+ 80016bc:	00bfffc4 	movi	r2,-1
+ 80016c0:	e0bff685 	stb	r2,-38(fp)
+        flash_content[23] = MSKADDR3;
+ 80016c4:	e03ff6c5 	stb	zero,-37(fp)
+        
+        /* Then comes the static gateway address */
+        flash_content[24] = GWADDR0;
+ 80016c8:	00800284 	movi	r2,10
+ 80016cc:	e0bff705 	stb	r2,-36(fp)
+        flash_content[25] = GWADDR1;
+ 80016d0:	e03ff745 	stb	zero,-35(fp)
+        flash_content[26] = GWADDR2;
+ 80016d4:	008001c4 	movi	r2,7
+ 80016d8:	e0bff785 	stb	r2,-34(fp)
+        flash_content[27] = GWADDR3;
+ 80016dc:	00800044 	movi	r2,1
+ 80016e0:	e0bff7c5 	stb	r2,-33(fp)
+        
+        /* And finally whether to use DHCP - set all bits to be safe */
+        flash_content[28] = 0xFF;
+ 80016e4:	00bfffc4 	movi	r2,-1
+ 80016e8:	e0bff805 	stb	r2,-32(fp)
+        flash_content[29] = 0xFF;
+ 80016ec:	00bfffc4 	movi	r2,-1
+ 80016f0:	e0bff845 	stb	r2,-31(fp)
+        flash_content[30] = 0xFF;
+ 80016f4:	00bfffc4 	movi	r2,-1
+ 80016f8:	e0bff885 	stb	r2,-30(fp)
+        flash_content[31] = 0xFF;
+ 80016fc:	00bfffc4 	movi	r2,-1
+ 8001700:	e0bff8c5 	stb	r2,-29(fp)
+        
+        /* Write the MAC address to flash */
+        flash_handle = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME);
+ 8001704:	01020134 	movhi	r4,2052
+ 8001708:	211bdd04 	addi	r4,r4,28532
+ 800170c:	800f7e40 	call	800f7e4 <alt_flash_open_dev>
+ 8001710:	e0bffd15 	stw	r2,-12(fp)
+        if (flash_handle)
+ 8001714:	e0bffd17 	ldw	r2,-12(fp)
+ 8001718:	10001326 	beq	r2,zero,8001768 <generate_and_store_mac_addr+0x1a0>
+        {
+            alt_write_flash(flash_handle,
+ 800171c:	d0a03a17 	ldw	r2,-32536(gp)
+ 8001720:	1007883a 	mov	r3,r2
+ 8001724:	e0bffd17 	ldw	r2,-12(fp)
+ 8001728:	e0bffc15 	stw	r2,-16(fp)
+ 800172c:	e0fffb15 	stw	r3,-20(fp)
+ 8001730:	e0bff104 	addi	r2,fp,-60
+ 8001734:	e0bffa15 	stw	r2,-24(fp)
+ 8001738:	00800804 	movi	r2,32
+ 800173c:	e0bff915 	stw	r2,-28(fp)
+                                                           alt_flash_fd* fd, 
+                                                           int offset, 
+                                                           const void* src_addr, 
+                                                           int length )
+{
+  return fd->write( fd, offset, src_addr, length );
+ 8001740:	e0bffc17 	ldw	r2,-16(fp)
+ 8001744:	10800517 	ldw	r2,20(r2)
+ 8001748:	e1fff917 	ldw	r7,-28(fp)
+ 800174c:	e1bffa17 	ldw	r6,-24(fp)
+ 8001750:	e17ffb17 	ldw	r5,-20(fp)
+ 8001754:	e13ffc17 	ldw	r4,-16(fp)
+ 8001758:	103ee83a 	callr	r2
+                            last_flash_sector_offset,
+                            flash_content,
+                            32);
+            alt_flash_close_dev(flash_handle);
+ 800175c:	e13ffd17 	ldw	r4,-12(fp)
+ 8001760:	800f84c0 	call	800f84c <alt_flash_close_dev>
+            error = 0;
+ 8001764:	e03fff15 	stw	zero,-4(fp)
+        }
+    }
+
+    return error;    
+ 8001768:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 800176c:	e037883a 	mov	sp,fp
+ 8001770:	dfc00117 	ldw	ra,4(sp)
+ 8001774:	df000017 	ldw	fp,0(sp)
+ 8001778:	dec00204 	addi	sp,sp,8
+ 800177c:	f800283a 	ret
+
+08001780 <generate_mac_addr>:
+ * Development Board serial number is 040800017, the corresponding ethernet 
+ * number generated will be 00:07:ED:FF:8F:11.
+ * 
+ */
+error_t generate_mac_addr(unsigned char mac_addr[6])
+{
+ 8001780:	defff804 	addi	sp,sp,-32
+ 8001784:	dfc00715 	stw	ra,28(sp)
+ 8001788:	df000615 	stw	fp,24(sp)
+ 800178c:	df000604 	addi	fp,sp,24
+ 8001790:	e13ffd15 	stw	r4,-12(fp)
+    error_t error = -1;
+ 8001794:	00bfffc4 	movi	r2,-1
+ 8001798:	e0bfff15 	stw	r2,-4(fp)
+    alt_u32 ser_num = 0;
+ 800179c:	e03ffe15 	stw	zero,-8(fp)
+    
+    printf("\nCan't read the MAC address from your board. We will assign you\n");
+ 80017a0:	01020134 	movhi	r4,2052
+ 80017a4:	211be304 	addi	r4,r4,28556
+ 80017a8:	8002d9c0 	call	8002d9c <puts>
+    printf("a MAC address.\n\n");
+ 80017ac:	01020134 	movhi	r4,2052
+ 80017b0:	211bf304 	addi	r4,r4,28620
+ 80017b4:	8002d9c0 	call	8002d9c <puts>
+    
+    ser_num = get_serial_number();
+ 80017b8:	80014340 	call	8001434 <get_serial_number>
+ 80017bc:	e0bffe15 	stw	r2,-8(fp)
+  
+    if (ser_num)
+ 80017c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80017c4:	10003526 	beq	r2,zero,800189c <generate_mac_addr+0x11c>
+    {
+        /* This is the Altera Vendor ID */
+        mac_addr[0] = 0x0;
+ 80017c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80017cc:	10000005 	stb	zero,0(r2)
+        mac_addr[1] = 0x7;
+ 80017d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80017d4:	10800044 	addi	r2,r2,1
+ 80017d8:	00c001c4 	movi	r3,7
+ 80017dc:	10c00005 	stb	r3,0(r2)
+        mac_addr[2] = 0xed;
+ 80017e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80017e4:	10800084 	addi	r2,r2,2
+ 80017e8:	00fffb44 	movi	r3,-19
+ 80017ec:	10c00005 	stb	r3,0(r2)
+        
+        /* Reserverd Board identifier */
+        mac_addr[3] = 0xFF;
+ 80017f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80017f4:	108000c4 	addi	r2,r2,3
+ 80017f8:	00ffffc4 	movi	r3,-1
+ 80017fc:	10c00005 	stb	r3,0(r2)
+        mac_addr[4] = (ser_num & 0xff00) >> 8;
+ 8001800:	e0bffe17 	ldw	r2,-8(fp)
+ 8001804:	1006d23a 	srli	r3,r2,8
+ 8001808:	e0bffd17 	ldw	r2,-12(fp)
+ 800180c:	10800104 	addi	r2,r2,4
+ 8001810:	10c00005 	stb	r3,0(r2)
+        mac_addr[5] = ser_num & 0xff;
+ 8001814:	e0bffd17 	ldw	r2,-12(fp)
+ 8001818:	10800144 	addi	r2,r2,5
+ 800181c:	e0fffe17 	ldw	r3,-8(fp)
+ 8001820:	10c00005 	stb	r3,0(r2)
+        
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+            mac_addr[0],
+ 8001824:	e0bffd17 	ldw	r2,-12(fp)
+ 8001828:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800182c:	11403fcc 	andi	r5,r2,255
+            mac_addr[1],
+ 8001830:	e0bffd17 	ldw	r2,-12(fp)
+ 8001834:	10800044 	addi	r2,r2,1
+ 8001838:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800183c:	11803fcc 	andi	r6,r2,255
+            mac_addr[2],
+ 8001840:	e0bffd17 	ldw	r2,-12(fp)
+ 8001844:	10800084 	addi	r2,r2,2
+ 8001848:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800184c:	11c03fcc 	andi	r7,r2,255
+            mac_addr[3],
+ 8001850:	e0bffd17 	ldw	r2,-12(fp)
+ 8001854:	108000c4 	addi	r2,r2,3
+ 8001858:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800185c:	10803fcc 	andi	r2,r2,255
+            mac_addr[4],
+ 8001860:	e0fffd17 	ldw	r3,-12(fp)
+ 8001864:	18c00104 	addi	r3,r3,4
+ 8001868:	18c00003 	ldbu	r3,0(r3)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800186c:	18c03fcc 	andi	r3,r3,255
+            mac_addr[5]);
+ 8001870:	e13ffd17 	ldw	r4,-12(fp)
+ 8001874:	21000144 	addi	r4,r4,5
+ 8001878:	21000003 	ldbu	r4,0(r4)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 800187c:	21003fcc 	andi	r4,r4,255
+ 8001880:	d9000215 	stw	r4,8(sp)
+ 8001884:	d8c00115 	stw	r3,4(sp)
+ 8001888:	d8800015 	stw	r2,0(sp)
+ 800188c:	01020134 	movhi	r4,2052
+ 8001890:	211bf704 	addi	r4,r4,28636
+ 8001894:	8002c780 	call	8002c78 <printf>
+        
+        error = 0;
+ 8001898:	e03fff15 	stw	zero,-4(fp)
+    }
+  
+    return error;    
+ 800189c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80018a0:	e037883a 	mov	sp,fp
+ 80018a4:	dfc00117 	ldw	ra,4(sp)
+ 80018a8:	df000017 	ldw	fp,0(sp)
+ 80018ac:	dec00204 	addi	sp,sp,8
+ 80018b0:	f800283a 	ret
+
+080018b4 <get_board_mac_addr>:
+*
+* Read the MAC address in a board specific way
+*
+*/
+error_t get_board_mac_addr(unsigned char mac_addr[6])
+{
+ 80018b4:	defff804 	addi	sp,sp,-32
+ 80018b8:	dfc00715 	stw	ra,28(sp)
+ 80018bc:	df000615 	stw	fp,24(sp)
+ 80018c0:	df000604 	addi	fp,sp,24
+ 80018c4:	e13ffd15 	stw	r4,-12(fp)
+    error_t error = 0;
+ 80018c8:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 signature;
+    
+    /* Get the flash sector with the MAC address. */
+    error = FindLastFlashSectorOffset(&last_flash_sector_offset);
+ 80018cc:	d1203a04 	addi	r4,gp,-32536
+ 80018d0:	8001a540 	call	8001a54 <FindLastFlashSectorOffset>
+ 80018d4:	e0bfff15 	stw	r2,-4(fp)
+    if (!error)
+ 80018d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80018dc:	1000041e 	bne	r2,zero,80018f0 <get_board_mac_addr+0x3c>
+        last_flash_sector = EXT_FLASH_AVL_MEM_BASE + last_flash_sector_offset;
+ 80018e0:	d0e03a17 	ldw	r3,-32536(gp)
+ 80018e4:	00850034 	movhi	r2,5120
+ 80018e8:	1885883a 	add	r2,r3,r2
+ 80018ec:	d0a03b15 	stw	r2,-32532(gp)
+     * valid network settings are present, indicated by a signature of 0x00005afe at 
+     * the first address of the last flash sector.  This hex value is chosen as the 
+     * signature since it looks like the english word "SAFE", meaning that it is 
+     * safe to use these network address values.  
+    */
+    if (!error)
+ 80018f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80018f4:	1000081e 	bne	r2,zero,8001918 <get_board_mac_addr+0x64>
+    {
+        signature = IORD_32DIRECT(last_flash_sector, 0);
+ 80018f8:	d0a03b17 	ldw	r2,-32532(gp)
+ 80018fc:	10800037 	ldwio	r2,0(r2)
+ 8001900:	e0bffe15 	stw	r2,-8(fp)
+        if (signature != 0x00005afe)
+ 8001904:	e0bffe17 	ldw	r2,-8(fp)
+ 8001908:	1096bfa0 	cmpeqi	r2,r2,23294
+ 800190c:	1000021e 	bne	r2,zero,8001918 <get_board_mac_addr+0x64>
+        {
+          error = generate_and_store_mac_addr();
+ 8001910:	80015c80 	call	80015c8 <generate_and_store_mac_addr>
+ 8001914:	e0bfff15 	stw	r2,-4(fp)
+        }
+    }
+  
+    if (!error)
+ 8001918:	e0bfff17 	ldw	r2,-4(fp)
+ 800191c:	1000471e 	bne	r2,zero,8001a3c <get_board_mac_addr+0x188>
+    {
+        mac_addr[0] = IORD_8DIRECT(last_flash_sector, 4);
+ 8001920:	d0a03b17 	ldw	r2,-32532(gp)
+ 8001924:	10800104 	addi	r2,r2,4
+ 8001928:	10800023 	ldbuio	r2,0(r2)
+ 800192c:	10803fcc 	andi	r2,r2,255
+ 8001930:	1007883a 	mov	r3,r2
+ 8001934:	e0bffd17 	ldw	r2,-12(fp)
+ 8001938:	10c00005 	stb	r3,0(r2)
+        mac_addr[1] = IORD_8DIRECT(last_flash_sector, 5);
+ 800193c:	d0a03b17 	ldw	r2,-32532(gp)
+ 8001940:	10800144 	addi	r2,r2,5
+ 8001944:	10800023 	ldbuio	r2,0(r2)
+ 8001948:	10c03fcc 	andi	r3,r2,255
+ 800194c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001950:	10800044 	addi	r2,r2,1
+ 8001954:	10c00005 	stb	r3,0(r2)
+        mac_addr[2] = IORD_8DIRECT(last_flash_sector, 6);
+ 8001958:	d0a03b17 	ldw	r2,-32532(gp)
+ 800195c:	10800184 	addi	r2,r2,6
+ 8001960:	10800023 	ldbuio	r2,0(r2)
+ 8001964:	10c03fcc 	andi	r3,r2,255
+ 8001968:	e0bffd17 	ldw	r2,-12(fp)
+ 800196c:	10800084 	addi	r2,r2,2
+ 8001970:	10c00005 	stb	r3,0(r2)
+        mac_addr[3] = IORD_8DIRECT(last_flash_sector, 7);
+ 8001974:	d0a03b17 	ldw	r2,-32532(gp)
+ 8001978:	108001c4 	addi	r2,r2,7
+ 800197c:	10800023 	ldbuio	r2,0(r2)
+ 8001980:	10c03fcc 	andi	r3,r2,255
+ 8001984:	e0bffd17 	ldw	r2,-12(fp)
+ 8001988:	108000c4 	addi	r2,r2,3
+ 800198c:	10c00005 	stb	r3,0(r2)
+        mac_addr[4] = IORD_8DIRECT(last_flash_sector, 8);
+ 8001990:	d0a03b17 	ldw	r2,-32532(gp)
+ 8001994:	10800204 	addi	r2,r2,8
+ 8001998:	10800023 	ldbuio	r2,0(r2)
+ 800199c:	10c03fcc 	andi	r3,r2,255
+ 80019a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80019a4:	10800104 	addi	r2,r2,4
+ 80019a8:	10c00005 	stb	r3,0(r2)
+        mac_addr[5] = IORD_8DIRECT(last_flash_sector, 9);
+ 80019ac:	d0a03b17 	ldw	r2,-32532(gp)
+ 80019b0:	10800244 	addi	r2,r2,9
+ 80019b4:	10800023 	ldbuio	r2,0(r2)
+ 80019b8:	10c03fcc 	andi	r3,r2,255
+ 80019bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80019c0:	10800144 	addi	r2,r2,5
+ 80019c4:	10c00005 	stb	r3,0(r2)
+    
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+            mac_addr[0],
+ 80019c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80019cc:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 80019d0:	11403fcc 	andi	r5,r2,255
+            mac_addr[1],
+ 80019d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80019d8:	10800044 	addi	r2,r2,1
+ 80019dc:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 80019e0:	11803fcc 	andi	r6,r2,255
+            mac_addr[2],
+ 80019e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80019e8:	10800084 	addi	r2,r2,2
+ 80019ec:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 80019f0:	11c03fcc 	andi	r7,r2,255
+            mac_addr[3],
+ 80019f4:	e0bffd17 	ldw	r2,-12(fp)
+ 80019f8:	108000c4 	addi	r2,r2,3
+ 80019fc:	10800003 	ldbu	r2,0(r2)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 8001a00:	10803fcc 	andi	r2,r2,255
+            mac_addr[4],
+ 8001a04:	e0fffd17 	ldw	r3,-12(fp)
+ 8001a08:	18c00104 	addi	r3,r3,4
+ 8001a0c:	18c00003 	ldbu	r3,0(r3)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 8001a10:	18c03fcc 	andi	r3,r3,255
+            mac_addr[5]);
+ 8001a14:	e13ffd17 	ldw	r4,-12(fp)
+ 8001a18:	21000144 	addi	r4,r4,5
+ 8001a1c:	21000003 	ldbu	r4,0(r4)
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+ 8001a20:	21003fcc 	andi	r4,r4,255
+ 8001a24:	d9000215 	stw	r4,8(sp)
+ 8001a28:	d8c00115 	stw	r3,4(sp)
+ 8001a2c:	d8800015 	stw	r2,0(sp)
+ 8001a30:	01020134 	movhi	r4,2052
+ 8001a34:	211bf704 	addi	r4,r4,28636
+ 8001a38:	8002c780 	call	8002c78 <printf>
+    
+    }
+    
+    return error;
+ 8001a3c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8001a40:	e037883a 	mov	sp,fp
+ 8001a44:	dfc00117 	ldw	ra,4(sp)
+ 8001a48:	df000017 	ldw	fp,0(sp)
+ 8001a4c:	dec00204 	addi	sp,sp,8
+ 8001a50:	f800283a 	ret
+
+08001a54 <FindLastFlashSectorOffset>:
+ * in pLastFlashSectorOffset.
+ */
+
+int FindLastFlashSectorOffset(
+    alt_u32                     *pLastFlashSectorOffset)
+{
+ 8001a54:	defff304 	addi	sp,sp,-52
+ 8001a58:	dfc00c15 	stw	ra,48(sp)
+ 8001a5c:	df000b15 	stw	fp,44(sp)
+ 8001a60:	df000b04 	addi	fp,sp,44
+ 8001a64:	e13ff515 	stw	r4,-44(fp)
+    flash_region                *regions;
+    int                         numRegions;
+    flash_region                *pLastRegion;
+    int                         lastFlashSectorOffset;
+    int                         n;
+    int                         error = 0;
+ 8001a68:	e03ffc15 	stw	zero,-16(fp)
+
+    /* Open the flash device. */
+    fd = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME);
+ 8001a6c:	01020134 	movhi	r4,2052
+ 8001a70:	211bdd04 	addi	r4,r4,28532
+ 8001a74:	800f7e40 	call	800f7e4 <alt_flash_open_dev>
+ 8001a78:	e0bffb15 	stw	r2,-20(fp)
+    if (fd <= 0)
+ 8001a7c:	e0bffb17 	ldw	r2,-20(fp)
+ 8001a80:	1000021e 	bne	r2,zero,8001a8c <FindLastFlashSectorOffset+0x38>
+        error = -1;
+ 8001a84:	00bfffc4 	movi	r2,-1
+ 8001a88:	e0bffc15 	stw	r2,-16(fp)
+
+    /* Get the flash info. */
+    if (!error)
+ 8001a8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8001a90:	10000d1e 	bne	r2,zero,8001ac8 <FindLastFlashSectorOffset+0x74>
+ 8001a94:	e0bffb17 	ldw	r2,-20(fp)
+ 8001a98:	e0bffa15 	stw	r2,-24(fp)
+ 8001a9c:	e0bff704 	addi	r2,fp,-36
+ 8001aa0:	e0bff915 	stw	r2,-28(fp)
+ 8001aa4:	e0bff604 	addi	r2,fp,-40
+ 8001aa8:	e0bff815 	stw	r2,-32(fp)
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( 
+                                      alt_flash_fd* fd, flash_region** info, 
+                                      int* number_of_regions)
+{
+  return fd->get_info( fd, info, number_of_regions);
+ 8001aac:	e0bffa17 	ldw	r2,-24(fp)
+ 8001ab0:	10800717 	ldw	r2,28(r2)
+ 8001ab4:	e1bff817 	ldw	r6,-32(fp)
+ 8001ab8:	e17ff917 	ldw	r5,-28(fp)
+ 8001abc:	e13ffa17 	ldw	r4,-24(fp)
+ 8001ac0:	103ee83a 	callr	r2
+        error = alt_get_flash_info(fd, &regions, &numRegions);
+ 8001ac4:	e0bffc15 	stw	r2,-16(fp)
+
+    /* Find the last flash sector. */
+    if (!error)
+ 8001ac8:	e0bffc17 	ldw	r2,-16(fp)
+ 8001acc:	1000211e 	bne	r2,zero,8001b54 <FindLastFlashSectorOffset+0x100>
+    {
+        pLastRegion = &(regions[0]);
+ 8001ad0:	e0bff717 	ldw	r2,-36(fp)
+ 8001ad4:	e0bfff15 	stw	r2,-4(fp)
+        for (n = 1; n < numRegions; n++)
+ 8001ad8:	00800044 	movi	r2,1
+ 8001adc:	e0bffd15 	stw	r2,-12(fp)
+ 8001ae0:	00001006 	br	8001b24 <FindLastFlashSectorOffset+0xd0>
+        {
+            if (regions[n].offset > pLastRegion->offset)
+ 8001ae4:	e0fff717 	ldw	r3,-36(fp)
+ 8001ae8:	e0bffd17 	ldw	r2,-12(fp)
+ 8001aec:	1004913a 	slli	r2,r2,4
+ 8001af0:	1885883a 	add	r2,r3,r2
+ 8001af4:	10800017 	ldw	r2,0(r2)
+ 8001af8:	e0ffff17 	ldw	r3,-4(fp)
+ 8001afc:	18c00017 	ldw	r3,0(r3)
+ 8001b00:	1880050e 	bge	r3,r2,8001b18 <FindLastFlashSectorOffset+0xc4>
+                pLastRegion = &(regions[n]);
+ 8001b04:	e0fff717 	ldw	r3,-36(fp)
+ 8001b08:	e0bffd17 	ldw	r2,-12(fp)
+ 8001b0c:	1004913a 	slli	r2,r2,4
+ 8001b10:	1885883a 	add	r2,r3,r2
+ 8001b14:	e0bfff15 	stw	r2,-4(fp)
+        for (n = 1; n < numRegions; n++)
+ 8001b18:	e0bffd17 	ldw	r2,-12(fp)
+ 8001b1c:	10800044 	addi	r2,r2,1
+ 8001b20:	e0bffd15 	stw	r2,-12(fp)
+ 8001b24:	e0bff617 	ldw	r2,-40(fp)
+ 8001b28:	e0fffd17 	ldw	r3,-12(fp)
+ 8001b2c:	18bfed16 	blt	r3,r2,8001ae4 <FindLastFlashSectorOffset+0x90>
+        }
+        lastFlashSectorOffset =   pLastRegion->offset
+ 8001b30:	e0bfff17 	ldw	r2,-4(fp)
+ 8001b34:	10c00017 	ldw	r3,0(r2)
+                                + pLastRegion->region_size
+ 8001b38:	e0bfff17 	ldw	r2,-4(fp)
+ 8001b3c:	10800117 	ldw	r2,4(r2)
+ 8001b40:	1887883a 	add	r3,r3,r2
+                                - pLastRegion->block_size;
+ 8001b44:	e0bfff17 	ldw	r2,-4(fp)
+ 8001b48:	10800317 	ldw	r2,12(r2)
+        lastFlashSectorOffset =   pLastRegion->offset
+ 8001b4c:	1885c83a 	sub	r2,r3,r2
+ 8001b50:	e0bffe15 	stw	r2,-8(fp)
+    }
+
+    /* Return results. */
+    if (!error)
+ 8001b54:	e0bffc17 	ldw	r2,-16(fp)
+ 8001b58:	1000031e 	bne	r2,zero,8001b68 <FindLastFlashSectorOffset+0x114>
+        *pLastFlashSectorOffset = lastFlashSectorOffset;
+ 8001b5c:	e0fffe17 	ldw	r3,-8(fp)
+ 8001b60:	e0bff517 	ldw	r2,-44(fp)
+ 8001b64:	10c00015 	stw	r3,0(r2)
+
+    return (error);
+ 8001b68:	e0bffc17 	ldw	r2,-16(fp)
+}
+ 8001b6c:	e037883a 	mov	sp,fp
+ 8001b70:	dfc00117 	ldw	ra,4(sp)
+ 8001b74:	df000017 	ldw	fp,0(sp)
+ 8001b78:	dec00204 	addi	sp,sp,8
+ 8001b7c:	f800283a 	ret
+
+08001b80 <sensor_command_bit>:
+#include "dev_commands.h"
+#include "sensor.h"
+
+
+void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state)
+{
+ 8001b80:	defffb04 	addi	sp,sp,-20
+ 8001b84:	df000415 	stw	fp,16(sp)
+ 8001b88:	df000404 	addi	fp,sp,16
+ 8001b8c:	e13ffe15 	stw	r4,-8(fp)
+ 8001b90:	2805883a 	mov	r2,r5
+ 8001b94:	3007883a 	mov	r3,r6
+ 8001b98:	e0bffd05 	stb	r2,-12(fp)
+ 8001b9c:	1805883a 	mov	r2,r3
+ 8001ba0:	e0bffc05 	stb	r2,-16(fp)
+	alt_u8 tmp = IORD_8DIRECT(base, SENSOR_REG_COMMAND);
+ 8001ba4:	e0bffe17 	ldw	r2,-8(fp)
+ 8001ba8:	10800023 	ldbuio	r2,0(r2)
+ 8001bac:	10803fcc 	andi	r2,r2,255
+ 8001bb0:	e0bfffc5 	stb	r2,-1(fp)
+	if (state)
+ 8001bb4:	e0bffc03 	ldbu	r2,-16(fp)
+ 8001bb8:	10000526 	beq	r2,zero,8001bd0 <sensor_command_bit+0x50>
+		tmp |= bitmask;
+ 8001bbc:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8001bc0:	e0bffd03 	ldbu	r2,-12(fp)
+ 8001bc4:	1884b03a 	or	r2,r3,r2
+ 8001bc8:	e0bfffc5 	stb	r2,-1(fp)
+ 8001bcc:	00000606 	br	8001be8 <sensor_command_bit+0x68>
+	else
+		tmp &= ~bitmask;
+ 8001bd0:	e0bffd03 	ldbu	r2,-12(fp)
+ 8001bd4:	0084303a 	nor	r2,zero,r2
+ 8001bd8:	1007883a 	mov	r3,r2
+ 8001bdc:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8001be0:	1884703a 	and	r2,r3,r2
+ 8001be4:	e0bfffc5 	stb	r2,-1(fp)
+	IOWR_8DIRECT(base, SENSOR_REG_COMMAND, tmp);
+ 8001be8:	e0bffe17 	ldw	r2,-8(fp)
+ 8001bec:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8001bf0:	10c00025 	stbio	r3,0(r2)
+}
+ 8001bf4:	0001883a 	nop
+ 8001bf8:	e037883a 	mov	sp,fp
+ 8001bfc:	df000017 	ldw	fp,0(sp)
+ 8001c00:	dec00104 	addi	sp,sp,4
+ 8001c04:	f800283a 	ret
+
+08001c08 <sensor_preconfigure>:
+
+
+void sensor_preconfigure(alt_u32 base)
+{
+ 8001c08:	defffd04 	addi	sp,sp,-12
+ 8001c0c:	dfc00215 	stw	ra,8(sp)
+ 8001c10:	df000115 	stw	fp,4(sp)
+ 8001c14:	df000104 	addi	fp,sp,4
+ 8001c18:	e13fff15 	stw	r4,-4(fp)
+	printf(" *** Preconfiguring sensor module... \n");
+ 8001c1c:	01020134 	movhi	r4,2052
+ 8001c20:	211c0604 	addi	r4,r4,28696
+ 8001c24:	8002d9c0 	call	8002d9c <puts>
+
+	sensor_command(base, 0);				//disable
+ 8001c28:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c2c:	0007883a 	mov	r3,zero
+ 8001c30:	10c00025 	stbio	r3,0(r2)
+	sensor_set_sensorclk(base, 6);			//sensor clock - 3.57 MHz
+ 8001c34:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c38:	10800084 	addi	r2,r2,2
+ 8001c3c:	1007883a 	mov	r3,r2
+ 8001c40:	00800184 	movi	r2,6
+ 8001c44:	18800025 	stbio	r2,0(r3)
+	sensor_set_adccnv(base, 31);			//conversion delay - default
+ 8001c48:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c4c:	108000c4 	addi	r2,r2,3
+ 8001c50:	1007883a 	mov	r3,r2
+ 8001c54:	008007c4 	movi	r2,31
+ 8001c58:	18800025 	stbio	r2,0(r3)
+	sensor_set_delay(base, 1);				//trigger delay - default
+ 8001c5c:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c60:	10800104 	addi	r2,r2,4
+ 8001c64:	1007883a 	mov	r3,r2
+ 8001c68:	00800044 	movi	r2,1
+ 8001c6c:	1880002d 	sthio	r2,0(r3)
+	sensor_set_shutter(base, 100);			//integration time - dummy default
+ 8001c70:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c74:	10800184 	addi	r2,r2,6
+ 8001c78:	1007883a 	mov	r3,r2
+ 8001c7c:	00801904 	movi	r2,100
+ 8001c80:	1880002d 	sthio	r2,0(r3)
+	sensor_set_serspeed(base, 50);			//synchro serial port - 1 Mbps
+ 8001c84:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c88:	10800204 	addi	r2,r2,8
+ 8001c8c:	1007883a 	mov	r3,r2
+ 8001c90:	00800c84 	movi	r2,50
+ 8001c94:	18800025 	stbio	r2,0(r3)
+	sensor_set_header_anydata(base, 0x00);	//should be 0
+ 8001c98:	e0bfff17 	ldw	r2,-4(fp)
+ 8001c9c:	10800244 	addi	r2,r2,9
+ 8001ca0:	0007883a 	mov	r3,zero
+ 8001ca4:	10c00025 	stbio	r3,0(r2)
+	sensor_set_header_cmd(base, COMMAND_DATA_TRANSFER);	//command header, must be this one
+ 8001ca8:	e0bfff17 	ldw	r2,-4(fp)
+ 8001cac:	10800284 	addi	r2,r2,10
+ 8001cb0:	1007883a 	mov	r3,r2
+ 8001cb4:	00a00004 	movi	r2,-32768
+ 8001cb8:	1880002d 	sthio	r2,0(r3)
+	sensor_command(base, 1);			//enable, gain low, SCLK full
+ 8001cbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8001cc0:	00c00044 	movi	r3,1
+ 8001cc4:	10c00025 	stbio	r3,0(r2)
+
+	sensor_set_cluster_threshold(base, 10); //default cluster threshold 10
+ 8001cc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8001ccc:	10800304 	addi	r2,r2,12
+ 8001cd0:	1007883a 	mov	r3,r2
+ 8001cd4:	00800284 	movi	r2,10
+ 8001cd8:	18800025 	stbio	r2,0(r3)
+	sensor_set_cluster_size(base, 4);		//default cluster size  4
+ 8001cdc:	e0bfff17 	ldw	r2,-4(fp)
+ 8001ce0:	10800344 	addi	r2,r2,13
+ 8001ce4:	1007883a 	mov	r3,r2
+ 8001ce8:	00800104 	movi	r2,4
+ 8001cec:	18800025 	stbio	r2,0(r3)
+	sensor_set_in_algo_threshold(base, 4);  //default algo threshold  4
+ 8001cf0:	e0bfff17 	ldw	r2,-4(fp)
+ 8001cf4:	10800384 	addi	r2,r2,14
+ 8001cf8:	1007883a 	mov	r3,r2
+ 8001cfc:	00800104 	movi	r2,4
+ 8001d00:	18800025 	stbio	r2,0(r3)
+
+}
+ 8001d04:	0001883a 	nop
+ 8001d08:	e037883a 	mov	sp,fp
+ 8001d0c:	dfc00117 	ldw	ra,4(sp)
+ 8001d10:	df000017 	ldw	fp,0(sp)
+ 8001d14:	dec00204 	addi	sp,sp,8
+ 8001d18:	f800283a 	ret
+
+08001d1c <ss_reset_connection>:
+// ********************************************************
+
+
+
+void ss_reset_connection(SSConn* conn)	//called e.g. after closing a socket
+{
+ 8001d1c:	defffe04 	addi	sp,sp,-8
+ 8001d20:	df000115 	stw	fp,4(sp)
+ 8001d24:	df000104 	addi	fp,sp,4
+ 8001d28:	e13fff15 	stw	r4,-4(fp)
+  conn->fd_conn = -1;
+ 8001d2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d30:	00ffffc4 	movi	r3,-1
+ 8001d34:	10c00215 	stw	r3,8(r2)
+  conn->state = LISTENING;
+ 8001d38:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d3c:	00c00044 	movi	r3,1
+ 8001d40:	10c00015 	stw	r3,0(r2)
+  return;
+ 8001d44:	0001883a 	nop
+}
+ 8001d48:	e037883a 	mov	sp,fp
+ 8001d4c:	df000017 	ldw	fp,0(sp)
+ 8001d50:	dec00104 	addi	sp,sp,4
+ 8001d54:	f800283a 	ret
+
+08001d58 <ss_initialize_connection>:
+
+void ss_initialize_connection(SSConn* conn)	//called only at initialization
+{
+ 8001d58:	defffe04 	addi	sp,sp,-8
+ 8001d5c:	df000115 	stw	fp,4(sp)
+ 8001d60:	df000104 	addi	fp,sp,4
+ 8001d64:	e13fff15 	stw	r4,-4(fp)
+  conn->fd_conn = -1;
+ 8001d68:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d6c:	00ffffc4 	movi	r3,-1
+ 8001d70:	10c00215 	stw	r3,8(r2)
+  conn->fd_listen = -1;
+ 8001d74:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d78:	00ffffc4 	movi	r3,-1
+ 8001d7c:	10c00115 	stw	r3,4(r2)
+  conn->listenport = -1;
+ 8001d80:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d84:	00ffffc4 	movi	r3,-1
+ 8001d88:	10c00315 	stw	r3,12(r2)
+  conn->state = FREE;
+ 8001d8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8001d90:	10000015 	stw	zero,0(r2)
+  return;
+ 8001d94:	0001883a 	nop
+}
+ 8001d98:	e037883a 	mov	sp,fp
+ 8001d9c:	df000017 	ldw	fp,0(sp)
+ 8001da0:	dec00104 	addi	sp,sp,4
+ 8001da4:	f800283a 	ret
+
+08001da8 <ss_handle_accept>:
+
+void ss_handle_accept(SSConn* conn)
+{
+ 8001da8:	defff604 	addi	sp,sp,-40
+ 8001dac:	dfc00915 	stw	ra,36(sp)
+ 8001db0:	df000815 	stw	fp,32(sp)
+ 8001db4:	df000804 	addi	fp,sp,32
+ 8001db8:	e13ff815 	stw	r4,-32(fp)
+	int                 socket;
+	int					len;
+	struct sockaddr_in  incoming_addr;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+ 8001dbc:	d0a03c17 	ldw	r2,-32528(gp)
+ 8001dc0:	e0fff9c4 	addi	r3,fp,-25
+ 8001dc4:	180d883a 	mov	r6,r3
+ 8001dc8:	000b883a 	mov	r5,zero
+ 8001dcc:	1009883a 	mov	r4,r2
+ 8001dd0:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+	len = sizeof(incoming_addr);
+ 8001dd4:	00800404 	movi	r2,16
+ 8001dd8:	e0bffe15 	stw	r2,-8(fp)
+
+	  //Close old connection if needed
+	if ((conn)->fd_conn != -1)
+ 8001ddc:	e0bff817 	ldw	r2,-32(fp)
+ 8001de0:	10800217 	ldw	r2,8(r2)
+ 8001de4:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8001de8:	1000091e 	bne	r2,zero,8001e10 <ss_handle_accept+0x68>
+	{
+		printf("[ss_handle_accept] closing old connection\n");
+ 8001dec:	01020134 	movhi	r4,2052
+ 8001df0:	211c1604 	addi	r4,r4,28760
+ 8001df4:	8002d9c0 	call	8002d9c <puts>
+		close(conn->fd_conn);
+ 8001df8:	e0bff817 	ldw	r2,-32(fp)
+ 8001dfc:	10800217 	ldw	r2,8(r2)
+ 8001e00:	1009883a 	mov	r4,r2
+ 8001e04:	8022a600 	call	8022a60 <close>
+		ss_reset_connection(conn);
+ 8001e08:	e13ff817 	ldw	r4,-32(fp)
+ 8001e0c:	8001d1c0 	call	8001d1c <ss_reset_connection>
+	}
+
+	if((socket=accept(conn->fd_listen,(struct sockaddr*)&incoming_addr,&len))<0)
+ 8001e10:	e0bff817 	ldw	r2,-32(fp)
+ 8001e14:	10800117 	ldw	r2,4(r2)
+ 8001e18:	e13ffe04 	addi	r4,fp,-8
+ 8001e1c:	e0fffa04 	addi	r3,fp,-24
+ 8001e20:	200d883a 	mov	r6,r4
+ 8001e24:	180b883a 	mov	r5,r3
+ 8001e28:	1009883a 	mov	r4,r2
+ 8001e2c:	80262140 	call	8026214 <bsd_accept>
+ 8001e30:	e0bfff15 	stw	r2,-4(fp)
+ 8001e34:	e0bfff17 	ldw	r2,-4(fp)
+ 8001e38:	10000c16 	blt	r2,zero,8001e6c <ss_handle_accept+0xc4>
+		//alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,
+		//					 "[ss_handle_accept] accept failed");
+	}
+	else
+	{
+		(conn)->fd_conn = socket;
+ 8001e3c:	e0bff817 	ldw	r2,-32(fp)
+ 8001e40:	e0ffff17 	ldw	r3,-4(fp)
+ 8001e44:	10c00215 	stw	r3,8(r2)
+		(conn)->state = CONNECTED;
+ 8001e48:	e0bff817 	ldw	r2,-32(fp)
+ 8001e4c:	00c00084 	movi	r3,2
+ 8001e50:	10c00015 	stw	r3,0(r2)
+		printf("[ss_handle_accept] accepted connection request from %s\n",
+ 8001e54:	e13ffb17 	ldw	r4,-20(fp)
+ 8001e58:	80268fc0 	call	80268fc <bsd_inet_ntoa>
+ 8001e5c:	100b883a 	mov	r5,r2
+ 8001e60:	01020134 	movhi	r4,2052
+ 8001e64:	211c2104 	addi	r4,r4,28804
+ 8001e68:	8002c780 	call	8002c78 <printf>
+		   inet_ntoa(incoming_addr.sin_addr));
+	}
+  
+	OSMutexPost(mutex);
+ 8001e6c:	d0a03c17 	ldw	r2,-32528(gp)
+ 8001e70:	1009883a 	mov	r4,r2
+ 8001e74:	80142380 	call	8014238 <OSMutexPost>
+	return;
+ 8001e78:	0001883a 	nop
+}
+ 8001e7c:	e037883a 	mov	sp,fp
+ 8001e80:	dfc00117 	ldw	ra,4(sp)
+ 8001e84:	df000017 	ldw	fp,0(sp)
+ 8001e88:	dec00204 	addi	sp,sp,8
+ 8001e8c:	f800283a 	ret
+
+08001e90 <SSListenerTask>:
+
+/*
+ * Listener Task()
+ */
+void SSListenerTask(void* param)
+{
+ 8001e90:	deffb304 	addi	sp,sp,-308
+ 8001e94:	dfc04c15 	stw	ra,304(sp)
+ 8001e98:	df004b15 	stw	fp,300(sp)
+ 8001e9c:	df004b04 	addi	fp,sp,300
+ 8001ea0:	e13fb615 	stw	r4,-296(fp)
+
+  int max_socket = 0;
+ 8001ea4:	e03fff15 	stw	zero,-4(fp)
+  BSD_TIMEVAL_T timeout;
+
+  INT8U err;
+  OSMutexPend(mutex, 0, &err);	//wrap initialization in a mutex - just in case...
+ 8001ea8:	d0a03c17 	ldw	r2,-32528(gp)
+ 8001eac:	e0fff8c4 	addi	r3,fp,-29
+ 8001eb0:	180d883a 	mov	r6,r3
+ 8001eb4:	000b883a 	mov	r5,zero
+ 8001eb8:	1009883a 	mov	r4,r2
+ 8001ebc:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+  timeout.tv_sec = 0;
+ 8001ec0:	e03ff915 	stw	zero,-28(fp)
+ 8001ec4:	e03ffa15 	stw	zero,-24(fp)
+  timeout.tv_usec = 100000;
+ 8001ec8:	008000b4 	movhi	r2,2
+ 8001ecc:	10a1a804 	addi	r2,r2,-31072
+ 8001ed0:	e0bffb15 	stw	r2,-20(fp)
+
+  fd_set readfds;	//set of descriptors
+  
+  for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8001ed4:	e03ffe15 	stw	zero,-8(fp)
+ 8001ed8:	00000d06 	br	8001f10 <SSListenerTask+0x80>
+	  if ((connections[ch].fd_listen = socket(AF_INET, SOCK_STREAM, 0)) < 0)
+ 8001edc:	000d883a 	mov	r6,zero
+ 8001ee0:	01400044 	movi	r5,1
+ 8001ee4:	01000084 	movi	r4,2
+ 8001ee8:	802ba700 	call	802ba70 <t_socket>
+ 8001eec:	1009883a 	mov	r4,r2
+ 8001ef0:	e0bffe17 	ldw	r2,-8(fp)
+ 8001ef4:	1006913a 	slli	r3,r2,4
+ 8001ef8:	00820174 	movhi	r2,2053
+ 8001efc:	1885883a 	add	r2,r3,r2
+ 8001f00:	11336115 	stw	r4,-12924(r2)
+  for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8001f04:	e0bffe17 	ldw	r2,-8(fp)
+ 8001f08:	10800044 	addi	r2,r2,1
+ 8001f0c:	e0bffe15 	stw	r2,-8(fp)
+ 8001f10:	e0bffe17 	ldw	r2,-8(fp)
+ 8001f14:	00bff10e 	bge	zero,r2,8001edc <SSListenerTask+0x4c>
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Socket creation failed");
+	  }
+
+  	  //Binding etc. is done by ethernet_listen()
+
+  OSMutexPost(mutex);
+ 8001f18:	d0a03c17 	ldw	r2,-32528(gp)
+ 8001f1c:	1009883a 	mov	r4,r2
+ 8001f20:	80142380 	call	8014238 <OSMutexPost>
+
+  	  //Now run in loop to handle incoming requests on all listening ports
+  while(1)
+  {
+		FD_ZERO(&readfds);
+ 8001f24:	e03fb715 	stw	zero,-292(fp)
+
+		for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8001f28:	e03ffd15 	stw	zero,-12(fp)
+ 8001f2c:	00002006 	br	8001fb0 <SSListenerTask+0x120>
+			if (connections[ch].listenport >= 0)
+ 8001f30:	e0bffd17 	ldw	r2,-12(fp)
+ 8001f34:	1006913a 	slli	r3,r2,4
+ 8001f38:	00820174 	movhi	r2,2053
+ 8001f3c:	1885883a 	add	r2,r3,r2
+ 8001f40:	10b36317 	ldw	r2,-12916(r2)
+ 8001f44:	10001716 	blt	r2,zero,8001fa4 <SSListenerTask+0x114>
+			{
+				FD_SET(connections[ch].fd_listen, &readfds);
+ 8001f48:	e0bffd17 	ldw	r2,-12(fp)
+ 8001f4c:	1006913a 	slli	r3,r2,4
+ 8001f50:	00820174 	movhi	r2,2053
+ 8001f54:	1885883a 	add	r2,r3,r2
+ 8001f58:	10b36117 	ldw	r2,-12924(r2)
+ 8001f5c:	e0ffb704 	addi	r3,fp,-292
+ 8001f60:	180b883a 	mov	r5,r3
+ 8001f64:	1009883a 	mov	r4,r2
+ 8001f68:	8030b180 	call	8030b18 <ifd_set>
+				if (connections[ch].fd_listen >= max_socket)
+ 8001f6c:	e0bffd17 	ldw	r2,-12(fp)
+ 8001f70:	1006913a 	slli	r3,r2,4
+ 8001f74:	00820174 	movhi	r2,2053
+ 8001f78:	1885883a 	add	r2,r3,r2
+ 8001f7c:	10f36117 	ldw	r3,-12924(r2)
+ 8001f80:	e0bfff17 	ldw	r2,-4(fp)
+ 8001f84:	18800716 	blt	r3,r2,8001fa4 <SSListenerTask+0x114>
+					max_socket = connections[ch].fd_listen+1;
+ 8001f88:	e0bffd17 	ldw	r2,-12(fp)
+ 8001f8c:	1006913a 	slli	r3,r2,4
+ 8001f90:	00820174 	movhi	r2,2053
+ 8001f94:	1885883a 	add	r2,r3,r2
+ 8001f98:	10b36117 	ldw	r2,-12924(r2)
+ 8001f9c:	10800044 	addi	r2,r2,1
+ 8001fa0:	e0bfff15 	stw	r2,-4(fp)
+		for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8001fa4:	e0bffd17 	ldw	r2,-12(fp)
+ 8001fa8:	10800044 	addi	r2,r2,1
+ 8001fac:	e0bffd15 	stw	r2,-12(fp)
+ 8001fb0:	e0bffd17 	ldw	r2,-12(fp)
+ 8001fb4:	00bfde0e 	bge	zero,r2,8001f30 <SSListenerTask+0xa0>
+			}
+
+		if (max_socket == 0)
+ 8001fb8:	e0bfff17 	ldw	r2,-4(fp)
+ 8001fbc:	1000031e 	bne	r2,zero,8001fcc <SSListenerTask+0x13c>
+			TK_SLEEP(10);	//just sleep a bit if nothing to do
+ 8001fc0:	010002c4 	movi	r4,11
+ 8001fc4:	801730c0 	call	801730c <OSTimeDly>
+ 8001fc8:	003fd606 	br	8001f24 <SSListenerTask+0x94>
+		else
+		{
+			select(max_socket, &readfds, NULL, NULL, &timeout);	//we must timeout from time to time to find newly set-up channels
+ 8001fcc:	e0ffb704 	addi	r3,fp,-292
+ 8001fd0:	e0bff904 	addi	r2,fp,-28
+ 8001fd4:	d8800015 	stw	r2,0(sp)
+ 8001fd8:	000f883a 	mov	r7,zero
+ 8001fdc:	000d883a 	mov	r6,zero
+ 8001fe0:	180b883a 	mov	r5,r3
+ 8001fe4:	e13fff17 	ldw	r4,-4(fp)
+ 8001fe8:	8026a740 	call	8026a74 <bsd_select>
+
+			for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8001fec:	e03ffc15 	stw	zero,-16(fp)
+ 8001ff0:	00001406 	br	8002044 <SSListenerTask+0x1b4>
+				if (FD_ISSET(connections[ch].fd_listen, &readfds))
+ 8001ff4:	e0bffc17 	ldw	r2,-16(fp)
+ 8001ff8:	1006913a 	slli	r3,r2,4
+ 8001ffc:	00820174 	movhi	r2,2053
+ 8002000:	1885883a 	add	r2,r3,r2
+ 8002004:	10b36117 	ldw	r2,-12924(r2)
+ 8002008:	e0ffb704 	addi	r3,fp,-292
+ 800200c:	180b883a 	mov	r5,r3
+ 8002010:	1009883a 	mov	r4,r2
+ 8002014:	8030b8c0 	call	8030b8c <ifd_isset>
+ 8002018:	10000726 	beq	r2,zero,8002038 <SSListenerTask+0x1a8>
+					ss_handle_accept(&(connections[ch]));
+ 800201c:	e0bffc17 	ldw	r2,-16(fp)
+ 8002020:	1006913a 	slli	r3,r2,4
+ 8002024:	00820174 	movhi	r2,2053
+ 8002028:	10b36004 	addi	r2,r2,-12928
+ 800202c:	1885883a 	add	r2,r3,r2
+ 8002030:	1009883a 	mov	r4,r2
+ 8002034:	8001da80 	call	8001da8 <ss_handle_accept>
+			for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8002038:	e0bffc17 	ldw	r2,-16(fp)
+ 800203c:	10800044 	addi	r2,r2,1
+ 8002040:	e0bffc15 	stw	r2,-16(fp)
+ 8002044:	e0bffc17 	ldw	r2,-16(fp)
+ 8002048:	00bfea0e 	bge	zero,r2,8001ff4 <SSListenerTask+0x164>
+		FD_ZERO(&readfds);
+ 800204c:	003fb506 	br	8001f24 <SSListenerTask+0x94>
+
+08002050 <ethernet_init>:
+
+
+// ****************** User interface ********************
+
+int ethernet_init()
+{
+ 8002050:	defffc04 	addi	sp,sp,-16
+ 8002054:	dfc00315 	stw	ra,12(sp)
+ 8002058:	df000215 	stw	fp,8(sp)
+ 800205c:	df000204 	addi	fp,sp,8
+	  INT8U err;
+	  mutex = OSMutexCreate(SS_LISTENER_TASK_PRIORITY-1, &err);
+ 8002060:	e0bffec4 	addi	r2,fp,-5
+ 8002064:	100b883a 	mov	r5,r2
+ 8002068:	01000204 	movi	r4,8
+ 800206c:	801389c0 	call	801389c <OSMutexCreate>
+ 8002070:	d0a03c15 	stw	r2,-32528(gp)
+
+
+	  for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8002074:	e03fff15 	stw	zero,-4(fp)
+ 8002078:	00000a06 	br	80020a4 <ethernet_init+0x54>
+		  ss_initialize_connection(&(connections[ch]));
+ 800207c:	e0bfff17 	ldw	r2,-4(fp)
+ 8002080:	1006913a 	slli	r3,r2,4
+ 8002084:	00820174 	movhi	r2,2053
+ 8002088:	10b36004 	addi	r2,r2,-12928
+ 800208c:	1885883a 	add	r2,r3,r2
+ 8002090:	1009883a 	mov	r4,r2
+ 8002094:	8001d580 	call	8001d58 <ss_initialize_connection>
+	  for (int ch = 0; ch < NR_CHANNELS; ch++)
+ 8002098:	e0bfff17 	ldw	r2,-4(fp)
+ 800209c:	10800044 	addi	r2,r2,1
+ 80020a0:	e0bfff15 	stw	r2,-4(fp)
+ 80020a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80020a8:	00bff40e 	bge	zero,r2,800207c <ethernet_init+0x2c>
+
+	  TK_NEWTASK(&sslistenertask);
+ 80020ac:	01020174 	movhi	r4,2053
+ 80020b0:	212e4e04 	addi	r4,r4,-18120
+ 80020b4:	80290740 	call	8029074 <TK_NEWTASK>
+	  return 0;
+ 80020b8:	0005883a 	mov	r2,zero
+}
+ 80020bc:	e037883a 	mov	sp,fp
+ 80020c0:	dfc00117 	ldw	ra,4(sp)
+ 80020c4:	df000017 	ldw	fp,0(sp)
+ 80020c8:	dec00204 	addi	sp,sp,8
+ 80020cc:	f800283a 	ret
+
+080020d0 <ethernet_listen>:
+
+int ethernet_listen(int channel, int port)
+{
+ 80020d0:	defff704 	addi	sp,sp,-36
+ 80020d4:	dfc00815 	stw	ra,32(sp)
+ 80020d8:	df000715 	stw	fp,28(sp)
+ 80020dc:	df000704 	addi	fp,sp,28
+ 80020e0:	e13ffa15 	stw	r4,-24(fp)
+ 80020e4:	e17ff915 	stw	r5,-28(fp)
+	  struct sockaddr_in addr;
+
+		INT8U err;
+		OSMutexPend(mutex, 0, &err);
+ 80020e8:	d0a03c17 	ldw	r2,-32528(gp)
+ 80020ec:	e0fffbc4 	addi	r3,fp,-17
+ 80020f0:	180d883a 	mov	r6,r3
+ 80020f4:	000b883a 	mov	r5,zero
+ 80020f8:	1009883a 	mov	r4,r2
+ 80020fc:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+	  addr.sin_family = AF_INET;
+ 8002100:	00800084 	movi	r2,2
+ 8002104:	e0bffc0d 	sth	r2,-16(fp)
+	  addr.sin_port = htons(port);
+ 8002108:	e0bff917 	ldw	r2,-28(fp)
+ 800210c:	1005d23a 	srai	r2,r2,8
+ 8002110:	10803fcc 	andi	r2,r2,255
+ 8002114:	1007883a 	mov	r3,r2
+ 8002118:	e0bff917 	ldw	r2,-28(fp)
+ 800211c:	1004923a 	slli	r2,r2,8
+ 8002120:	1884b03a 	or	r2,r3,r2
+ 8002124:	e0bffc8d 	sth	r2,-14(fp)
+	  addr.sin_addr.s_addr = INADDR_ANY;
+ 8002128:	e03ffd15 	stw	zero,-12(fp)
+
+	  if (bind(connections[channel].fd_listen,(struct sockaddr *)&addr,sizeof(addr)) < 0)
+ 800212c:	e0bffa17 	ldw	r2,-24(fp)
+ 8002130:	1006913a 	slli	r3,r2,4
+ 8002134:	00820174 	movhi	r2,2053
+ 8002138:	1885883a 	add	r2,r3,r2
+ 800213c:	10b36117 	ldw	r2,-12924(r2)
+ 8002140:	e0fffc04 	addi	r3,fp,-16
+ 8002144:	01800404 	movi	r6,16
+ 8002148:	180b883a 	mov	r5,r3
+ 800214c:	1009883a 	mov	r4,r2
+ 8002150:	802baf00 	call	802baf0 <t_bind>
+ 8002154:	1000050e 	bge	r2,zero,800216c <ethernet_listen+0x9c>
+	  {
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Bind failed");
+		  OSMutexPost(mutex);
+ 8002158:	d0a03c17 	ldw	r2,-32528(gp)
+ 800215c:	1009883a 	mov	r4,r2
+ 8002160:	80142380 	call	8014238 <OSMutexPost>
+		  return -1;
+ 8002164:	00bfffc4 	movi	r2,-1
+ 8002168:	00002306 	br	80021f8 <ethernet_listen+0x128>
+	  }
+
+	  if (listen(connections[channel].fd_listen,1) < 0)
+ 800216c:	e0bffa17 	ldw	r2,-24(fp)
+ 8002170:	1006913a 	slli	r3,r2,4
+ 8002174:	00820174 	movhi	r2,2053
+ 8002178:	1885883a 	add	r2,r3,r2
+ 800217c:	10b36117 	ldw	r2,-12924(r2)
+ 8002180:	01400044 	movi	r5,1
+ 8002184:	1009883a 	mov	r4,r2
+ 8002188:	802bc500 	call	802bc50 <t_listen>
+ 800218c:	1000050e 	bge	r2,zero,80021a4 <ethernet_listen+0xd4>
+	  {
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Listen failed");
+		  OSMutexPost(mutex);
+ 8002190:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002194:	1009883a 	mov	r4,r2
+ 8002198:	80142380 	call	8014238 <OSMutexPost>
+		  return -2;
+ 800219c:	00bfff84 	movi	r2,-2
+ 80021a0:	00001506 	br	80021f8 <ethernet_listen+0x128>
+	  }
+
+	  ss_reset_connection(&(connections[channel]));
+ 80021a4:	e0bffa17 	ldw	r2,-24(fp)
+ 80021a8:	1006913a 	slli	r3,r2,4
+ 80021ac:	00820174 	movhi	r2,2053
+ 80021b0:	10b36004 	addi	r2,r2,-12928
+ 80021b4:	1885883a 	add	r2,r3,r2
+ 80021b8:	1009883a 	mov	r4,r2
+ 80021bc:	8001d1c0 	call	8001d1c <ss_reset_connection>
+	  connections[channel].listenport = port;
+ 80021c0:	e0bffa17 	ldw	r2,-24(fp)
+ 80021c4:	1008913a 	slli	r4,r2,4
+ 80021c8:	e0fff917 	ldw	r3,-28(fp)
+ 80021cc:	00820174 	movhi	r2,2053
+ 80021d0:	2085883a 	add	r2,r4,r2
+ 80021d4:	10f36315 	stw	r3,-12916(r2)
+	  printf("[sss_task] Simple Socket Server listening on port %d\n", port);
+ 80021d8:	e17ff917 	ldw	r5,-28(fp)
+ 80021dc:	01020134 	movhi	r4,2052
+ 80021e0:	211c2f04 	addi	r4,r4,28860
+ 80021e4:	8002c780 	call	8002c78 <printf>
+
+	  OSMutexPost(mutex);
+ 80021e8:	d0a03c17 	ldw	r2,-32528(gp)
+ 80021ec:	1009883a 	mov	r4,r2
+ 80021f0:	80142380 	call	8014238 <OSMutexPost>
+	  return 0;
+ 80021f4:	0005883a 	mov	r2,zero
+}
+ 80021f8:	e037883a 	mov	sp,fp
+ 80021fc:	dfc00117 	ldw	ra,4(sp)
+ 8002200:	df000017 	ldw	fp,0(sp)
+ 8002204:	dec00204 	addi	sp,sp,8
+ 8002208:	f800283a 	ret
+
+0800220c <ethernet_write>:
+
+int ethernet_write(int channel, int size, unsigned char* data)
+{
+ 800220c:	defff904 	addi	sp,sp,-28
+ 8002210:	dfc00615 	stw	ra,24(sp)
+ 8002214:	df000515 	stw	fp,20(sp)
+ 8002218:	df000504 	addi	fp,sp,20
+ 800221c:	e13ffd15 	stw	r4,-12(fp)
+ 8002220:	e17ffc15 	stw	r5,-16(fp)
+ 8002224:	e1bffb15 	stw	r6,-20(fp)
+	int result;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+ 8002228:	d0a03c17 	ldw	r2,-32528(gp)
+ 800222c:	e0fffec4 	addi	r3,fp,-5
+ 8002230:	180d883a 	mov	r6,r3
+ 8002234:	000b883a 	mov	r5,zero
+ 8002238:	1009883a 	mov	r4,r2
+ 800223c:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+	if (connections[channel].fd_conn == -1)	//socket is closed or channel unconfigured
+ 8002240:	e0bffd17 	ldw	r2,-12(fp)
+ 8002244:	1006913a 	slli	r3,r2,4
+ 8002248:	00820174 	movhi	r2,2053
+ 800224c:	1885883a 	add	r2,r3,r2
+ 8002250:	10b36217 	ldw	r2,-12920(r2)
+ 8002254:	10bfffd8 	cmpnei	r2,r2,-1
+ 8002258:	1000051e 	bne	r2,zero,8002270 <ethernet_write+0x64>
+	{
+		OSMutexPost(mutex);
+ 800225c:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002260:	1009883a 	mov	r4,r2
+ 8002264:	80142380 	call	8014238 <OSMutexPost>
+	    return 0;
+ 8002268:	0005883a 	mov	r2,zero
+ 800226c:	00002406 	br	8002300 <ethernet_write+0xf4>
+	}
+
+	result = (int)send(connections[channel].fd_conn, data, size, 0);
+ 8002270:	e0bffd17 	ldw	r2,-12(fp)
+ 8002274:	1006913a 	slli	r3,r2,4
+ 8002278:	00820174 	movhi	r2,2053
+ 800227c:	1885883a 	add	r2,r3,r2
+ 8002280:	10b36217 	ldw	r2,-12920(r2)
+ 8002284:	000f883a 	mov	r7,zero
+ 8002288:	e1bffc17 	ldw	r6,-16(fp)
+ 800228c:	e17ffb17 	ldw	r5,-20(fp)
+ 8002290:	1009883a 	mov	r4,r2
+ 8002294:	802cb9c0 	call	802cb9c <t_send>
+ 8002298:	e0bfff15 	stw	r2,-4(fp)
+	if (result == -1)
+ 800229c:	e0bfff17 	ldw	r2,-4(fp)
+ 80022a0:	10bfffd8 	cmpnei	r2,r2,-1
+ 80022a4:	1000121e 	bne	r2,zero,80022f0 <ethernet_write+0xe4>
+	{
+		printf("[ethernet_write] closing connection due to error\n");
+ 80022a8:	01020134 	movhi	r4,2052
+ 80022ac:	211c3d04 	addi	r4,r4,28916
+ 80022b0:	8002d9c0 	call	8002d9c <puts>
+		close(connections[channel].fd_conn);			//close connection on error
+ 80022b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80022b8:	1006913a 	slli	r3,r2,4
+ 80022bc:	00820174 	movhi	r2,2053
+ 80022c0:	1885883a 	add	r2,r3,r2
+ 80022c4:	10b36217 	ldw	r2,-12920(r2)
+ 80022c8:	1009883a 	mov	r4,r2
+ 80022cc:	8022a600 	call	8022a60 <close>
+		ss_reset_connection(&(connections[channel]));
+ 80022d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80022d4:	1006913a 	slli	r3,r2,4
+ 80022d8:	00820174 	movhi	r2,2053
+ 80022dc:	10b36004 	addi	r2,r2,-12928
+ 80022e0:	1885883a 	add	r2,r3,r2
+ 80022e4:	1009883a 	mov	r4,r2
+ 80022e8:	8001d1c0 	call	8001d1c <ss_reset_connection>
+		result = 0;
+ 80022ec:	e03fff15 	stw	zero,-4(fp)
+	}
+
+	OSMutexPost(mutex);
+ 80022f0:	d0a03c17 	ldw	r2,-32528(gp)
+ 80022f4:	1009883a 	mov	r4,r2
+ 80022f8:	80142380 	call	8014238 <OSMutexPost>
+	return result;
+ 80022fc:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8002300:	e037883a 	mov	sp,fp
+ 8002304:	dfc00117 	ldw	ra,4(sp)
+ 8002308:	df000017 	ldw	fp,0(sp)
+ 800230c:	dec00204 	addi	sp,sp,8
+ 8002310:	f800283a 	ret
+
+08002314 <ethernet_read>:
+
+int ethernet_read(int channel, int size, unsigned char* data)
+{
+ 8002314:	deffb304 	addi	sp,sp,-308
+ 8002318:	dfc04c15 	stw	ra,304(sp)
+ 800231c:	df004b15 	stw	fp,300(sp)
+ 8002320:	df004b04 	addi	fp,sp,300
+ 8002324:	e13fb815 	stw	r4,-288(fp)
+ 8002328:	e17fb715 	stw	r5,-292(fp)
+ 800232c:	e1bfb615 	stw	r6,-296(fp)
+	int max_socket;
+	BSD_TIMEVAL_T timeout;
+	int result;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+ 8002330:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002334:	e0ffb9c4 	addi	r3,fp,-281
+ 8002338:	180d883a 	mov	r6,r3
+ 800233c:	000b883a 	mov	r5,zero
+ 8002340:	1009883a 	mov	r4,r2
+ 8002344:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+	if (connections[channel].fd_conn == -1)	//socket is closed or channel unconfigured
+ 8002348:	e0bfb817 	ldw	r2,-288(fp)
+ 800234c:	1006913a 	slli	r3,r2,4
+ 8002350:	00820174 	movhi	r2,2053
+ 8002354:	1885883a 	add	r2,r3,r2
+ 8002358:	10b36217 	ldw	r2,-12920(r2)
+ 800235c:	10bfffd8 	cmpnei	r2,r2,-1
+ 8002360:	1000051e 	bne	r2,zero,8002378 <ethernet_read+0x64>
+	{
+		OSMutexPost(mutex);
+ 8002364:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002368:	1009883a 	mov	r4,r2
+ 800236c:	80142380 	call	8014238 <OSMutexPost>
+	    return 0;
+ 8002370:	0005883a 	mov	r2,zero
+ 8002374:	00005006 	br	80024b8 <ethernet_read+0x1a4>
+	}
+
+		//prepare call parameters
+    FD_ZERO(&readfds);
+ 8002378:	e03fbd15 	stw	zero,-268(fp)
+    FD_SET(connections[channel].fd_conn, &readfds);
+ 800237c:	e0bfb817 	ldw	r2,-288(fp)
+ 8002380:	1006913a 	slli	r3,r2,4
+ 8002384:	00820174 	movhi	r2,2053
+ 8002388:	1885883a 	add	r2,r3,r2
+ 800238c:	10b36217 	ldw	r2,-12920(r2)
+ 8002390:	e0ffbd04 	addi	r3,fp,-268
+ 8002394:	180b883a 	mov	r5,r3
+ 8002398:	1009883a 	mov	r4,r2
+ 800239c:	8030b180 	call	8030b18 <ifd_set>
+    max_socket = connections[channel].fd_conn+1;
+ 80023a0:	e0bfb817 	ldw	r2,-288(fp)
+ 80023a4:	1006913a 	slli	r3,r2,4
+ 80023a8:	00820174 	movhi	r2,2053
+ 80023ac:	1885883a 	add	r2,r3,r2
+ 80023b0:	10b36217 	ldw	r2,-12920(r2)
+ 80023b4:	10800044 	addi	r2,r2,1
+ 80023b8:	e0bffe15 	stw	r2,-8(fp)
+    timeout.tv_sec = 0;
+ 80023bc:	e03fba15 	stw	zero,-280(fp)
+ 80023c0:	e03fbb15 	stw	zero,-276(fp)
+    timeout.tv_usec = 0;
+ 80023c4:	e03fbc15 	stw	zero,-272(fp)
+
+    	//check for data
+    if (select(max_socket, &readfds, NULL, NULL, &timeout))
+ 80023c8:	e0ffbd04 	addi	r3,fp,-268
+ 80023cc:	e0bfba04 	addi	r2,fp,-280
+ 80023d0:	d8800015 	stw	r2,0(sp)
+ 80023d4:	000f883a 	mov	r7,zero
+ 80023d8:	000d883a 	mov	r6,zero
+ 80023dc:	180b883a 	mov	r5,r3
+ 80023e0:	e13ffe17 	ldw	r4,-8(fp)
+ 80023e4:	8026a740 	call	8026a74 <bsd_select>
+ 80023e8:	10002f26 	beq	r2,zero,80024a8 <ethernet_read+0x194>
+    	if (FD_ISSET(connections[channel].fd_conn, &readfds))
+ 80023ec:	e0bfb817 	ldw	r2,-288(fp)
+ 80023f0:	1006913a 	slli	r3,r2,4
+ 80023f4:	00820174 	movhi	r2,2053
+ 80023f8:	1885883a 	add	r2,r3,r2
+ 80023fc:	10b36217 	ldw	r2,-12920(r2)
+ 8002400:	e0ffbd04 	addi	r3,fp,-268
+ 8002404:	180b883a 	mov	r5,r3
+ 8002408:	1009883a 	mov	r4,r2
+ 800240c:	8030b8c0 	call	8030b8c <ifd_isset>
+ 8002410:	10002526 	beq	r2,zero,80024a8 <ethernet_read+0x194>
+    	{
+    		result =  (int)recv(connections[channel].fd_conn, data, size, 0);
+ 8002414:	e0bfb817 	ldw	r2,-288(fp)
+ 8002418:	1006913a 	slli	r3,r2,4
+ 800241c:	00820174 	movhi	r2,2053
+ 8002420:	1885883a 	add	r2,r3,r2
+ 8002424:	10b36217 	ldw	r2,-12920(r2)
+ 8002428:	000f883a 	mov	r7,zero
+ 800242c:	e1bfb717 	ldw	r6,-292(fp)
+ 8002430:	e17fb617 	ldw	r5,-296(fp)
+ 8002434:	1009883a 	mov	r4,r2
+ 8002438:	802c7940 	call	802c794 <t_recv>
+ 800243c:	e0bfff15 	stw	r2,-4(fp)
+    		if (result == -1)
+ 8002440:	e0bfff17 	ldw	r2,-4(fp)
+ 8002444:	10bfffd8 	cmpnei	r2,r2,-1
+ 8002448:	1000121e 	bne	r2,zero,8002494 <ethernet_read+0x180>
+    		{
+    			printf("[ethernet_read] closing connection due to error\n");
+ 800244c:	01020134 	movhi	r4,2052
+ 8002450:	211c4a04 	addi	r4,r4,28968
+ 8002454:	8002d9c0 	call	8002d9c <puts>
+    			close(connections[channel].fd_conn);			//close connection on error
+ 8002458:	e0bfb817 	ldw	r2,-288(fp)
+ 800245c:	1006913a 	slli	r3,r2,4
+ 8002460:	00820174 	movhi	r2,2053
+ 8002464:	1885883a 	add	r2,r3,r2
+ 8002468:	10b36217 	ldw	r2,-12920(r2)
+ 800246c:	1009883a 	mov	r4,r2
+ 8002470:	8022a600 	call	8022a60 <close>
+    			ss_reset_connection(&(connections[channel]));
+ 8002474:	e0bfb817 	ldw	r2,-288(fp)
+ 8002478:	1006913a 	slli	r3,r2,4
+ 800247c:	00820174 	movhi	r2,2053
+ 8002480:	10b36004 	addi	r2,r2,-12928
+ 8002484:	1885883a 	add	r2,r3,r2
+ 8002488:	1009883a 	mov	r4,r2
+ 800248c:	8001d1c0 	call	8001d1c <ss_reset_connection>
+    			result = 0;
+ 8002490:	e03fff15 	stw	zero,-4(fp)
+    		}
+    		OSMutexPost(mutex);
+ 8002494:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002498:	1009883a 	mov	r4,r2
+ 800249c:	80142380 	call	8014238 <OSMutexPost>
+    		return result;
+ 80024a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80024a4:	00000406 	br	80024b8 <ethernet_read+0x1a4>
+    	}
+
+	OSMutexPost(mutex);
+ 80024a8:	d0a03c17 	ldw	r2,-32528(gp)
+ 80024ac:	1009883a 	mov	r4,r2
+ 80024b0:	80142380 	call	8014238 <OSMutexPost>
+    return 0;
+ 80024b4:	0005883a 	mov	r2,zero
+}
+ 80024b8:	e037883a 	mov	sp,fp
+ 80024bc:	dfc00117 	ldw	ra,4(sp)
+ 80024c0:	df000017 	ldw	fp,0(sp)
+ 80024c4:	dec00204 	addi	sp,sp,8
+ 80024c8:	f800283a 	ret
+
+080024cc <ethernet_close>:
+
+int ethernet_close(int channel)
+{
+ 80024cc:	defffc04 	addi	sp,sp,-16
+ 80024d0:	dfc00315 	stw	ra,12(sp)
+ 80024d4:	df000215 	stw	fp,8(sp)
+ 80024d8:	df000204 	addi	fp,sp,8
+ 80024dc:	e13ffe15 	stw	r4,-8(fp)
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+ 80024e0:	d0a03c17 	ldw	r2,-32528(gp)
+ 80024e4:	e0ffffc4 	addi	r3,fp,-1
+ 80024e8:	180d883a 	mov	r6,r3
+ 80024ec:	000b883a 	mov	r5,zero
+ 80024f0:	1009883a 	mov	r4,r2
+ 80024f4:	8013cdc0 	call	8013cdc <OSMutexPend>
+
+	close(connections[channel].fd_conn);
+ 80024f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80024fc:	1006913a 	slli	r3,r2,4
+ 8002500:	00820174 	movhi	r2,2053
+ 8002504:	1885883a 	add	r2,r3,r2
+ 8002508:	10b36217 	ldw	r2,-12920(r2)
+ 800250c:	1009883a 	mov	r4,r2
+ 8002510:	8022a600 	call	8022a60 <close>
+	ss_reset_connection(&(connections[channel]));
+ 8002514:	e0bffe17 	ldw	r2,-8(fp)
+ 8002518:	1006913a 	slli	r3,r2,4
+ 800251c:	00820174 	movhi	r2,2053
+ 8002520:	10b36004 	addi	r2,r2,-12928
+ 8002524:	1885883a 	add	r2,r3,r2
+ 8002528:	1009883a 	mov	r4,r2
+ 800252c:	8001d1c0 	call	8001d1c <ss_reset_connection>
+
+	OSMutexPost(mutex);
+ 8002530:	d0a03c17 	ldw	r2,-32528(gp)
+ 8002534:	1009883a 	mov	r4,r2
+ 8002538:	80142380 	call	8014238 <OSMutexPost>
+	return 0;
+ 800253c:	0005883a 	mov	r2,zero
+}
+ 8002540:	e037883a 	mov	sp,fp
+ 8002544:	dfc00117 	ldw	ra,4(sp)
+ 8002548:	df000017 	ldw	fp,0(sp)
+ 800254c:	dec00204 	addi	sp,sp,8
+ 8002550:	f800283a 	ret
+
+08002554 <udpgen_command_bit>:
+
+//*******************************************************************
+
+
+void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state)
+{
+ 8002554:	defffb04 	addi	sp,sp,-20
+ 8002558:	df000415 	stw	fp,16(sp)
+ 800255c:	df000404 	addi	fp,sp,16
+ 8002560:	e13ffe15 	stw	r4,-8(fp)
+ 8002564:	2805883a 	mov	r2,r5
+ 8002568:	3007883a 	mov	r3,r6
+ 800256c:	e0bffd05 	stb	r2,-12(fp)
+ 8002570:	1805883a 	mov	r2,r3
+ 8002574:	e0bffc05 	stb	r2,-16(fp)
+	alt_u8 tmp = IORD_8DIRECT(base, UDPGEN_REG_CSR);
+ 8002578:	e0bffe17 	ldw	r2,-8(fp)
+ 800257c:	10800023 	ldbuio	r2,0(r2)
+ 8002580:	10803fcc 	andi	r2,r2,255
+ 8002584:	e0bfffc5 	stb	r2,-1(fp)
+	if (state)
+ 8002588:	e0bffc03 	ldbu	r2,-16(fp)
+ 800258c:	10000526 	beq	r2,zero,80025a4 <udpgen_command_bit+0x50>
+		tmp |= bitmask;
+ 8002590:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8002594:	e0bffd03 	ldbu	r2,-12(fp)
+ 8002598:	1884b03a 	or	r2,r3,r2
+ 800259c:	e0bfffc5 	stb	r2,-1(fp)
+ 80025a0:	00000606 	br	80025bc <udpgen_command_bit+0x68>
+	else
+		tmp &= ~bitmask;
+ 80025a4:	e0bffd03 	ldbu	r2,-12(fp)
+ 80025a8:	0084303a 	nor	r2,zero,r2
+ 80025ac:	1007883a 	mov	r3,r2
+ 80025b0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80025b4:	1884703a 	and	r2,r3,r2
+ 80025b8:	e0bfffc5 	stb	r2,-1(fp)
+	IOWR_8DIRECT(base, UDPGEN_REG_CSR, tmp);
+ 80025bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80025c0:	e0ffffc3 	ldbu	r3,-1(fp)
+ 80025c4:	10c00025 	stbio	r3,0(r2)
+}
+ 80025c8:	0001883a 	nop
+ 80025cc:	e037883a 	mov	sp,fp
+ 80025d0:	df000017 	ldw	fp,0(sp)
+ 80025d4:	dec00104 	addi	sp,sp,4
+ 80025d8:	f800283a 	ret
+
+080025dc <udpgen_test>:
+
+void udpgen_test(alt_u32 base)
+{
+ 80025dc:	defff604 	addi	sp,sp,-40
+ 80025e0:	dfc00915 	stw	ra,36(sp)
+ 80025e4:	df000815 	stw	fp,32(sp)
+ 80025e8:	df000804 	addi	fp,sp,32
+ 80025ec:	e13ff815 	stw	r4,-32(fp)
+	printf (" *** Setting up UDP generator... \n");
+ 80025f0:	01020134 	movhi	r4,2052
+ 80025f4:	211c6004 	addi	r4,r4,29056
+ 80025f8:	8002d9c0 	call	8002d9c <puts>
+
+	unsigned char dstmac[] = {0x18, 0xd6, 0xc7, 0x05, 0xaa, 0x63};
+ 80025fc:	00800604 	movi	r2,24
+ 8002600:	e0bffb85 	stb	r2,-18(fp)
+ 8002604:	00bff584 	movi	r2,-42
+ 8002608:	e0bffbc5 	stb	r2,-17(fp)
+ 800260c:	00bff1c4 	movi	r2,-57
+ 8002610:	e0bffc05 	stb	r2,-16(fp)
+ 8002614:	00800144 	movi	r2,5
+ 8002618:	e0bffc45 	stb	r2,-15(fp)
+ 800261c:	00bfea84 	movi	r2,-86
+ 8002620:	e0bffc85 	stb	r2,-14(fp)
+ 8002624:	008018c4 	movi	r2,99
+ 8002628:	e0bffcc5 	stb	r2,-13(fp)
+	unsigned char srcip[] = {10,0,7,17};
+ 800262c:	00800284 	movi	r2,10
+ 8002630:	e0bffa85 	stb	r2,-22(fp)
+ 8002634:	e03ffac5 	stb	zero,-21(fp)
+ 8002638:	008001c4 	movi	r2,7
+ 800263c:	e0bffb05 	stb	r2,-20(fp)
+ 8002640:	00800444 	movi	r2,17
+ 8002644:	e0bffb45 	stb	r2,-19(fp)
+	unsigned char dstip[] = {10,0,7,1};
+ 8002648:	00800284 	movi	r2,10
+ 800264c:	e0bff985 	stb	r2,-26(fp)
+ 8002650:	e03ff9c5 	stb	zero,-25(fp)
+ 8002654:	008001c4 	movi	r2,7
+ 8002658:	e0bffa05 	stb	r2,-24(fp)
+ 800265c:	00800044 	movi	r2,1
+ 8002660:	e0bffa45 	stb	r2,-23(fp)
+
+	udpgen_command(UDP_GENERATOR_BASE, 0x01);
+ 8002664:	00c00044 	movi	r3,1
+ 8002668:	00861034 	movhi	r2,6208
+ 800266c:	10cf3025 	stbio	r3,15552(r2)
+	udpgen_set_size(UDP_GENERATOR_BASE, 16);
+ 8002670:	00c00404 	movi	r3,16
+ 8002674:	00861034 	movhi	r2,6208
+ 8002678:	10cf30ad 	sthio	r3,15554(r2)
+	udpgen_set_srcip_a(UDP_GENERATOR_BASE, srcip);
+ 800267c:	e03fff15 	stw	zero,-4(fp)
+ 8002680:	00001006 	br	80026c4 <udpgen_test+0xe8>
+ 8002684:	e0bfff17 	ldw	r2,-4(fp)
+ 8002688:	10800104 	addi	r2,r2,4
+ 800268c:	1007883a 	mov	r3,r2
+ 8002690:	00861034 	movhi	r2,6208
+ 8002694:	108f3004 	addi	r2,r2,15552
+ 8002698:	1885883a 	add	r2,r3,r2
+ 800269c:	010000c4 	movi	r4,3
+ 80026a0:	e0ffff17 	ldw	r3,-4(fp)
+ 80026a4:	20c7c83a 	sub	r3,r4,r3
+ 80026a8:	e0c7883a 	add	r3,fp,r3
+ 80026ac:	18fffa83 	ldbu	r3,-22(r3)
+ 80026b0:	18c03fcc 	andi	r3,r3,255
+ 80026b4:	10c00025 	stbio	r3,0(r2)
+ 80026b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80026bc:	10800044 	addi	r2,r2,1
+ 80026c0:	e0bfff15 	stw	r2,-4(fp)
+ 80026c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80026c8:	10800110 	cmplti	r2,r2,4
+ 80026cc:	103fed1e 	bne	r2,zero,8002684 <udpgen_test+0xa8>
+	udpgen_set_dstip_a(UDP_GENERATOR_BASE, dstip);
+ 80026d0:	e03ffe15 	stw	zero,-8(fp)
+ 80026d4:	00001006 	br	8002718 <udpgen_test+0x13c>
+ 80026d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80026dc:	10800204 	addi	r2,r2,8
+ 80026e0:	1007883a 	mov	r3,r2
+ 80026e4:	00861034 	movhi	r2,6208
+ 80026e8:	108f3004 	addi	r2,r2,15552
+ 80026ec:	1885883a 	add	r2,r3,r2
+ 80026f0:	010000c4 	movi	r4,3
+ 80026f4:	e0fffe17 	ldw	r3,-8(fp)
+ 80026f8:	20c7c83a 	sub	r3,r4,r3
+ 80026fc:	e0c7883a 	add	r3,fp,r3
+ 8002700:	18fff983 	ldbu	r3,-26(r3)
+ 8002704:	18c03fcc 	andi	r3,r3,255
+ 8002708:	10c00025 	stbio	r3,0(r2)
+ 800270c:	e0bffe17 	ldw	r2,-8(fp)
+ 8002710:	10800044 	addi	r2,r2,1
+ 8002714:	e0bffe15 	stw	r2,-8(fp)
+ 8002718:	e0bffe17 	ldw	r2,-8(fp)
+ 800271c:	10800110 	cmplti	r2,r2,4
+ 8002720:	103fed1e 	bne	r2,zero,80026d8 <udpgen_test+0xfc>
+	udpgen_set_srcport(UDP_GENERATOR_BASE, 4096);
+ 8002724:	00c40004 	movi	r3,4096
+ 8002728:	00861034 	movhi	r2,6208
+ 800272c:	10cf33ad 	sthio	r3,15566(r2)
+	udpgen_set_dstport(UDP_GENERATOR_BASE, 4097);
+ 8002730:	00c40044 	movi	r3,4097
+ 8002734:	00861034 	movhi	r2,6208
+ 8002738:	10cf332d 	sthio	r3,15564(r2)
+	udpgen_set_dstmac_a(UDP_GENERATOR_BASE, dstmac);
+ 800273c:	e03ffd15 	stw	zero,-12(fp)
+ 8002740:	00001006 	br	8002784 <udpgen_test+0x1a8>
+ 8002744:	e0bffd17 	ldw	r2,-12(fp)
+ 8002748:	10800404 	addi	r2,r2,16
+ 800274c:	1007883a 	mov	r3,r2
+ 8002750:	00861034 	movhi	r2,6208
+ 8002754:	108f3004 	addi	r2,r2,15552
+ 8002758:	1885883a 	add	r2,r3,r2
+ 800275c:	01000144 	movi	r4,5
+ 8002760:	e0fffd17 	ldw	r3,-12(fp)
+ 8002764:	20c7c83a 	sub	r3,r4,r3
+ 8002768:	e0c7883a 	add	r3,fp,r3
+ 800276c:	18fffb83 	ldbu	r3,-18(r3)
+ 8002770:	18c03fcc 	andi	r3,r3,255
+ 8002774:	10c00025 	stbio	r3,0(r2)
+ 8002778:	e0bffd17 	ldw	r2,-12(fp)
+ 800277c:	10800044 	addi	r2,r2,1
+ 8002780:	e0bffd15 	stw	r2,-12(fp)
+ 8002784:	e0bffd17 	ldw	r2,-12(fp)
+ 8002788:	10800190 	cmplti	r2,r2,6
+ 800278c:	103fed1e 	bne	r2,zero,8002744 <udpgen_test+0x168>
+}
+ 8002790:	0001883a 	nop
+ 8002794:	e037883a 	mov	sp,fp
+ 8002798:	dfc00117 	ldw	ra,4(sp)
+ 800279c:	df000017 	ldw	fp,0(sp)
+ 80027a0:	dec00204 	addi	sp,sp,8
+ 80027a4:	f800283a 	ret
+
+080027a8 <swap_bytes>:
+
+//******************************************************
+
+//Swap odd/even bytes in a bunch of data to align endianness of shorts
+void swap_bytes(unsigned char* array, int size_bytes)
+{
+ 80027a8:	defffb04 	addi	sp,sp,-20
+ 80027ac:	df000415 	stw	fp,16(sp)
+ 80027b0:	df000404 	addi	fp,sp,16
+ 80027b4:	e13ffd15 	stw	r4,-12(fp)
+ 80027b8:	e17ffc15 	stw	r5,-16(fp)
+	for (int i = 0; i < size_bytes; i+= 2)
+ 80027bc:	e03fff15 	stw	zero,-4(fp)
+ 80027c0:	00001706 	br	8002820 <swap_bytes+0x78>
+	{
+		unsigned char tmp = array[i];
+ 80027c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80027c8:	e0fffd17 	ldw	r3,-12(fp)
+ 80027cc:	1885883a 	add	r2,r3,r2
+ 80027d0:	10800003 	ldbu	r2,0(r2)
+ 80027d4:	e0bffec5 	stb	r2,-5(fp)
+		array[i] = array[i+1];
+ 80027d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80027dc:	10800044 	addi	r2,r2,1
+ 80027e0:	e0fffd17 	ldw	r3,-12(fp)
+ 80027e4:	1887883a 	add	r3,r3,r2
+ 80027e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80027ec:	e13ffd17 	ldw	r4,-12(fp)
+ 80027f0:	2085883a 	add	r2,r4,r2
+ 80027f4:	18c00003 	ldbu	r3,0(r3)
+ 80027f8:	10c00005 	stb	r3,0(r2)
+		array[i+1] = tmp;
+ 80027fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8002800:	10800044 	addi	r2,r2,1
+ 8002804:	e0fffd17 	ldw	r3,-12(fp)
+ 8002808:	1885883a 	add	r2,r3,r2
+ 800280c:	e0fffec3 	ldbu	r3,-5(fp)
+ 8002810:	10c00005 	stb	r3,0(r2)
+	for (int i = 0; i < size_bytes; i+= 2)
+ 8002814:	e0bfff17 	ldw	r2,-4(fp)
+ 8002818:	10800084 	addi	r2,r2,2
+ 800281c:	e0bfff15 	stw	r2,-4(fp)
+ 8002820:	e0ffff17 	ldw	r3,-4(fp)
+ 8002824:	e0bffc17 	ldw	r2,-16(fp)
+ 8002828:	18bfe616 	blt	r3,r2,80027c4 <swap_bytes+0x1c>
+	}
+}
+ 800282c:	0001883a 	nop
+ 8002830:	e037883a 	mov	sp,fp
+ 8002834:	df000017 	ldw	fp,0(sp)
+ 8002838:	dec00104 	addi	sp,sp,4
+ 800283c:	f800283a 	ret
+
+08002840 <swap_quad>:
+//The same, but four-byte-wise
+void swap_quad(unsigned char* array, int size_bytes)
+{
+ 8002840:	defffa04 	addi	sp,sp,-24
+ 8002844:	df000515 	stw	fp,20(sp)
+ 8002848:	df000504 	addi	fp,sp,20
+ 800284c:	e13ffc15 	stw	r4,-16(fp)
+ 8002850:	e17ffb15 	stw	r5,-20(fp)
+	unsigned char buf[4];
+
+	for (int i = 0; i < size_bytes; i+= 4)
+ 8002854:	e03fff15 	stw	zero,-4(fp)
+ 8002858:	00002206 	br	80028e4 <swap_quad+0xa4>
+	{
+		memcpy(buf, array+i, 4);
+ 800285c:	e0bfff17 	ldw	r2,-4(fp)
+ 8002860:	e0fffc17 	ldw	r3,-16(fp)
+ 8002864:	1885883a 	add	r2,r3,r2
+ 8002868:	10c00003 	ldbu	r3,0(r2)
+ 800286c:	e0fffd05 	stb	r3,-12(fp)
+ 8002870:	10c00043 	ldbu	r3,1(r2)
+ 8002874:	e0fffd45 	stb	r3,-11(fp)
+ 8002878:	10c00083 	ldbu	r3,2(r2)
+ 800287c:	e0fffd85 	stb	r3,-10(fp)
+ 8002880:	108000c3 	ldbu	r2,3(r2)
+ 8002884:	e0bffdc5 	stb	r2,-9(fp)
+		for (int j = 0; j < 4; j++)
+ 8002888:	e03ffe15 	stw	zero,-8(fp)
+ 800288c:	00000f06 	br	80028cc <swap_quad+0x8c>
+			array[i+j] = buf[3-j];
+ 8002890:	00c000c4 	movi	r3,3
+ 8002894:	e0bffe17 	ldw	r2,-8(fp)
+ 8002898:	1887c83a 	sub	r3,r3,r2
+ 800289c:	e13fff17 	ldw	r4,-4(fp)
+ 80028a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80028a4:	2085883a 	add	r2,r4,r2
+ 80028a8:	1009883a 	mov	r4,r2
+ 80028ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80028b0:	1105883a 	add	r2,r2,r4
+ 80028b4:	e0c7883a 	add	r3,fp,r3
+ 80028b8:	18fffd03 	ldbu	r3,-12(r3)
+ 80028bc:	10c00005 	stb	r3,0(r2)
+		for (int j = 0; j < 4; j++)
+ 80028c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80028c4:	10800044 	addi	r2,r2,1
+ 80028c8:	e0bffe15 	stw	r2,-8(fp)
+ 80028cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80028d0:	10800110 	cmplti	r2,r2,4
+ 80028d4:	103fee1e 	bne	r2,zero,8002890 <swap_quad+0x50>
+	for (int i = 0; i < size_bytes; i+= 4)
+ 80028d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80028dc:	10800104 	addi	r2,r2,4
+ 80028e0:	e0bfff15 	stw	r2,-4(fp)
+ 80028e4:	e0ffff17 	ldw	r3,-4(fp)
+ 80028e8:	e0bffb17 	ldw	r2,-20(fp)
+ 80028ec:	18bfdb16 	blt	r3,r2,800285c <swap_quad+0x1c>
+	}
+}
+ 80028f0:	0001883a 	nop
+ 80028f4:	e037883a 	mov	sp,fp
+ 80028f8:	df000017 	ldw	fp,0(sp)
+ 80028fc:	dec00104 	addi	sp,sp,4
+ 8002900:	f800283a 	ret
+
+08002904 <reload_fpga>:
+
+	//trigger FPGA reload
+void reload_fpga()
+{
+ 8002904:	defffe04 	addi	sp,sp,-8
+ 8002908:	dfc00115 	stw	ra,4(sp)
+ 800290c:	df000015 	stw	fp,0(sp)
+ 8002910:	d839883a 	mov	fp,sp
+	printf("$$$$ RECONFIGURING FPGA!!! $$$$\n");
+ 8002914:	01020134 	movhi	r4,2052
+ 8002918:	211c6904 	addi	r4,r4,29092
+ 800291c:	8002d9c0 	call	8002d9c <puts>
+	//TK_SLEEP(100);	//let it print the message before dying
+	//IOWR(DUAL_BOOT_BASE, 0, 0x1);
+	printf("*** DISABLED! ***\n");
+ 8002920:	01020134 	movhi	r4,2052
+ 8002924:	211c7104 	addi	r4,r4,29124
+ 8002928:	8002d9c0 	call	8002d9c <puts>
+}
+ 800292c:	0001883a 	nop
+ 8002930:	e037883a 	mov	sp,fp
+ 8002934:	dfc00117 	ldw	ra,4(sp)
+ 8002938:	df000017 	ldw	fp,0(sp)
+ 800293c:	dec00204 	addi	sp,sp,8
+ 8002940:	f800283a 	ret
+
+08002944 <masterslave>:
+
+void masterslave(alt_u8 master)
+{
+ 8002944:	defffd04 	addi	sp,sp,-12
+ 8002948:	dfc00215 	stw	ra,8(sp)
+ 800294c:	df000115 	stw	fp,4(sp)
+ 8002950:	df000104 	addi	fp,sp,4
+ 8002954:	2005883a 	mov	r2,r4
+ 8002958:	e0bfff05 	stb	r2,-4(fp)
+	if (master)
+ 800295c:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002960:	10000426 	beq	r2,zero,8002974 <masterslave+0x30>
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 0x80);
+ 8002964:	00c02004 	movi	r3,128
+ 8002968:	00861034 	movhi	r2,6208
+ 800296c:	10cf1435 	stwio	r3,15440(r2)
+ 8002970:	00000306 	br	8002980 <masterslave+0x3c>
+	else
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 0x80);
+ 8002974:	00c02004 	movi	r3,128
+ 8002978:	00861034 	movhi	r2,6208
+ 800297c:	10cf1535 	stwio	r3,15444(r2)
+	mastermode = master;
+ 8002980:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002984:	d0a03d85 	stb	r2,-32522(gp)
+	set_delay(mastermode, delays[mastermode]);	//update sensor delay setting
+ 8002988:	d0a03d83 	ldbu	r2,-32522(gp)
+ 800298c:	11003fcc 	andi	r4,r2,255
+ 8002990:	d0a03d83 	ldbu	r2,-32522(gp)
+ 8002994:	10803fcc 	andi	r2,r2,255
+ 8002998:	1087883a 	add	r3,r2,r2
+ 800299c:	d0a03e04 	addi	r2,gp,-32520
+ 80029a0:	1885883a 	add	r2,r3,r2
+ 80029a4:	1080000b 	ldhu	r2,0(r2)
+ 80029a8:	10bfffcc 	andi	r2,r2,65535
+ 80029ac:	100b883a 	mov	r5,r2
+ 80029b0:	8002bc80 	call	8002bc8 <set_delay>
+}
+ 80029b4:	0001883a 	nop
+ 80029b8:	e037883a 	mov	sp,fp
+ 80029bc:	dfc00117 	ldw	ra,4(sp)
+ 80029c0:	df000017 	ldw	fp,0(sp)
+ 80029c4:	dec00204 	addi	sp,sp,8
+ 80029c8:	f800283a 	ret
+
+080029cc <master_clock_period>:
+
+void master_clock_period(alt_u32 period)
+{
+ 80029cc:	defffe04 	addi	sp,sp,-8
+ 80029d0:	df000115 	stw	fp,4(sp)
+ 80029d4:	df000104 	addi	fp,sp,4
+ 80029d8:	e13fff15 	stw	r4,-4(fp)
+		//set period
+	IOWR_ALTERA_AVALON_TIMER_PERIODL(FRAME_TIMER_BASE, (alt_u16)(period & 0xFFFF));
+ 80029dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80029e0:	10ffffcc 	andi	r3,r2,65535
+ 80029e4:	00861034 	movhi	r2,6208
+ 80029e8:	10cf0235 	stwio	r3,15368(r2)
+	IOWR_ALTERA_AVALON_TIMER_PERIODH(FRAME_TIMER_BASE, (alt_u16)((period>>16) & 0xFFFF));
+ 80029ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80029f0:	1004d43a 	srli	r2,r2,16
+ 80029f4:	10ffffcc 	andi	r3,r2,65535
+ 80029f8:	00861034 	movhi	r2,6208
+ 80029fc:	10cf0335 	stwio	r3,15372(r2)
+		//start timer in continuous mode
+	//IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,
+	//									ALTERA_AVALON_TIMER_CONTROL_CONT_MSK);
+}
+ 8002a00:	0001883a 	nop
+ 8002a04:	e037883a 	mov	sp,fp
+ 8002a08:	df000017 	ldw	fp,0(sp)
+ 8002a0c:	dec00104 	addi	sp,sp,4
+ 8002a10:	f800283a 	ret
+
+08002a14 <master_clock_enable>:
+
+void master_clock_enable(alt_u8 en)
+{
+ 8002a14:	defffd04 	addi	sp,sp,-12
+ 8002a18:	df000215 	stw	fp,8(sp)
+ 8002a1c:	df000204 	addi	fp,sp,8
+ 8002a20:	2005883a 	mov	r2,r4
+ 8002a24:	e0bffe05 	stb	r2,-8(fp)
+	alt_u16 tmp = 0;	// = IORD_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE);
+ 8002a28:	e03fff8d 	sth	zero,-2(fp)
+
+	if (en)
+ 8002a2c:	e0bffe03 	ldbu	r2,-8(fp)
+ 8002a30:	10000426 	beq	r2,zero,8002a44 <master_clock_enable+0x30>
+		tmp |= ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK;
+ 8002a34:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8002a38:	10800194 	ori	r2,r2,6
+ 8002a3c:	e0bfff8d 	sth	r2,-2(fp)
+ 8002a40:	00000306 	br	8002a50 <master_clock_enable+0x3c>
+	else
+		tmp |= ALTERA_AVALON_TIMER_CONTROL_STOP_MSK;
+ 8002a44:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8002a48:	10800214 	ori	r2,r2,8
+ 8002a4c:	e0bfff8d 	sth	r2,-2(fp)
+
+	IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,tmp);
+ 8002a50:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8002a54:	00861034 	movhi	r2,6208
+ 8002a58:	10cf0135 	stwio	r3,15364(r2)
+}
+ 8002a5c:	0001883a 	nop
+ 8002a60:	e037883a 	mov	sp,fp
+ 8002a64:	df000017 	ldw	fp,0(sp)
+ 8002a68:	dec00104 	addi	sp,sp,4
+ 8002a6c:	f800283a 	ret
+
+08002a70 <led_set>:
+
+void led_set(alt_u8 led_nr)
+{
+ 8002a70:	defffe04 	addi	sp,sp,-8
+ 8002a74:	df000115 	stw	fp,4(sp)
+ 8002a78:	df000104 	addi	fp,sp,4
+ 8002a7c:	2005883a 	mov	r2,r4
+ 8002a80:	e0bfff05 	stb	r2,-4(fp)
+	if (led_nr > 4)
+ 8002a84:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002a88:	10800170 	cmpltui	r2,r2,5
+ 8002a8c:	10000626 	beq	r2,zero,8002aa8 <led_set+0x38>
+		return;
+	IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<led_nr);
+ 8002a90:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002a94:	00c00044 	movi	r3,1
+ 8002a98:	1886983a 	sll	r3,r3,r2
+ 8002a9c:	00861034 	movhi	r2,6208
+ 8002aa0:	10cf1435 	stwio	r3,15440(r2)
+ 8002aa4:	00000106 	br	8002aac <led_set+0x3c>
+		return;
+ 8002aa8:	0001883a 	nop
+}
+ 8002aac:	e037883a 	mov	sp,fp
+ 8002ab0:	df000017 	ldw	fp,0(sp)
+ 8002ab4:	dec00104 	addi	sp,sp,4
+ 8002ab8:	f800283a 	ret
+
+08002abc <led_clear>:
+
+void led_clear(alt_u8 led_nr)
+{
+ 8002abc:	defffe04 	addi	sp,sp,-8
+ 8002ac0:	df000115 	stw	fp,4(sp)
+ 8002ac4:	df000104 	addi	fp,sp,4
+ 8002ac8:	2005883a 	mov	r2,r4
+ 8002acc:	e0bfff05 	stb	r2,-4(fp)
+	if (led_nr > 4)
+ 8002ad0:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002ad4:	10800170 	cmpltui	r2,r2,5
+ 8002ad8:	10000626 	beq	r2,zero,8002af4 <led_clear+0x38>
+		return;
+	IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1<<led_nr);
+ 8002adc:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002ae0:	00c00044 	movi	r3,1
+ 8002ae4:	1886983a 	sll	r3,r3,r2
+ 8002ae8:	00861034 	movhi	r2,6208
+ 8002aec:	10cf1535 	stwio	r3,15444(r2)
+ 8002af0:	00000106 	br	8002af8 <led_clear+0x3c>
+		return;
+ 8002af4:	0001883a 	nop
+}
+ 8002af8:	e037883a 	mov	sp,fp
+ 8002afc:	df000017 	ldw	fp,0(sp)
+ 8002b00:	dec00104 	addi	sp,sp,4
+ 8002b04:	f800283a 	ret
+
+08002b08 <led_toggle>:
+
+void led_toggle(alt_u8 led_nr)
+{
+ 8002b08:	defffd04 	addi	sp,sp,-12
+ 8002b0c:	df000215 	stw	fp,8(sp)
+ 8002b10:	df000204 	addi	fp,sp,8
+ 8002b14:	2005883a 	mov	r2,r4
+ 8002b18:	e0bffe05 	stb	r2,-8(fp)
+	if (led_nr > 4)
+ 8002b1c:	e0bffe03 	ldbu	r2,-8(fp)
+ 8002b20:	10800170 	cmpltui	r2,r2,5
+ 8002b24:	10001026 	beq	r2,zero,8002b68 <led_toggle+0x60>
+		return;
+	alt_u32 tmp = IORD_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE);
+ 8002b28:	00861034 	movhi	r2,6208
+ 8002b2c:	108f1037 	ldwio	r2,15424(r2)
+ 8002b30:	e0bfff15 	stw	r2,-4(fp)
+	tmp ^= (1<<led_nr);
+ 8002b34:	e0bffe03 	ldbu	r2,-8(fp)
+ 8002b38:	00c00044 	movi	r3,1
+ 8002b3c:	1884983a 	sll	r2,r3,r2
+ 8002b40:	1007883a 	mov	r3,r2
+ 8002b44:	e0bfff17 	ldw	r2,-4(fp)
+ 8002b48:	10c4f03a 	xor	r2,r2,r3
+ 8002b4c:	e0bfff15 	stw	r2,-4(fp)
+	IOWR_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE, 1<<led_nr);
+ 8002b50:	e0bffe03 	ldbu	r2,-8(fp)
+ 8002b54:	00c00044 	movi	r3,1
+ 8002b58:	1886983a 	sll	r3,r3,r2
+ 8002b5c:	00861034 	movhi	r2,6208
+ 8002b60:	10cf1035 	stwio	r3,15424(r2)
+ 8002b64:	00000106 	br	8002b6c <led_toggle+0x64>
+		return;
+ 8002b68:	0001883a 	nop
+}
+ 8002b6c:	e037883a 	mov	sp,fp
+ 8002b70:	df000017 	ldw	fp,0(sp)
+ 8002b74:	dec00104 	addi	sp,sp,4
+ 8002b78:	f800283a 	ret
+
+08002b7c <led4_blink_enable>:
+
+void led4_blink_enable(alt_u8 en)
+{
+ 8002b7c:	defffe04 	addi	sp,sp,-8
+ 8002b80:	df000115 	stw	fp,4(sp)
+ 8002b84:	df000104 	addi	fp,sp,4
+ 8002b88:	2005883a 	mov	r2,r4
+ 8002b8c:	e0bfff05 	stb	r2,-4(fp)
+	if (en)
+ 8002b90:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002b94:	10000426 	beq	r2,zero,8002ba8 <led4_blink_enable+0x2c>
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1<<5);
+ 8002b98:	00c00804 	movi	r3,32
+ 8002b9c:	00861034 	movhi	r2,6208
+ 8002ba0:	10cf1535 	stwio	r3,15444(r2)
+	else
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<5);
+}
+ 8002ba4:	00000306 	br	8002bb4 <led4_blink_enable+0x38>
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<5);
+ 8002ba8:	00c00804 	movi	r3,32
+ 8002bac:	00861034 	movhi	r2,6208
+ 8002bb0:	10cf1435 	stwio	r3,15440(r2)
+}
+ 8002bb4:	0001883a 	nop
+ 8002bb8:	e037883a 	mov	sp,fp
+ 8002bbc:	df000017 	ldw	fp,0(sp)
+ 8002bc0:	dec00104 	addi	sp,sp,4
+ 8002bc4:	f800283a 	ret
+
+08002bc8 <set_delay>:
+
+void set_delay(alt_u8 master, alt_u16 value)
+{
+ 8002bc8:	defffd04 	addi	sp,sp,-12
+ 8002bcc:	df000215 	stw	fp,8(sp)
+ 8002bd0:	df000204 	addi	fp,sp,8
+ 8002bd4:	2005883a 	mov	r2,r4
+ 8002bd8:	2807883a 	mov	r3,r5
+ 8002bdc:	e0bfff05 	stb	r2,-4(fp)
+ 8002be0:	1805883a 	mov	r2,r3
+ 8002be4:	e0bffe0d 	sth	r2,-8(fp)
+	delays[master] = value;
+ 8002be8:	e0bfff03 	ldbu	r2,-4(fp)
+ 8002bec:	1087883a 	add	r3,r2,r2
+ 8002bf0:	d0a03e04 	addi	r2,gp,-32520
+ 8002bf4:	1885883a 	add	r2,r3,r2
+ 8002bf8:	e0fffe0b 	ldhu	r3,-8(fp)
+ 8002bfc:	10c0000d 	sth	r3,0(r2)
+	if (master == mastermode)
+ 8002c00:	d0a03d83 	ldbu	r2,-32522(gp)
+ 8002c04:	e0ffff03 	ldbu	r3,-4(fp)
+ 8002c08:	10803fcc 	andi	r2,r2,255
+ 8002c0c:	1880031e 	bne	r3,r2,8002c1c <set_delay+0x54>
+		sensor_set_delay(SENSOR_INTERFACE_BASE, value);	//update sensor setting only if right mode
+ 8002c10:	e0fffe0b 	ldhu	r3,-8(fp)
+ 8002c14:	00861034 	movhi	r2,6208
+ 8002c18:	10cf552d 	sthio	r3,15700(r2)
+}
+ 8002c1c:	0001883a 	nop
+ 8002c20:	e037883a 	mov	sp,fp
+ 8002c24:	df000017 	ldw	fp,0(sp)
+ 8002c28:	dec00104 	addi	sp,sp,4
+ 8002c2c:	f800283a 	ret
+
+08002c30 <_getchar_r>:
+ 8002c30:	21400117 	ldw	r5,4(r4)
+ 8002c34:	8007adc1 	jmpi	8007adc <_getc_r>
+
+08002c38 <getchar>:
+ 8002c38:	00820174 	movhi	r2,2053
+ 8002c3c:	1132af17 	ldw	r4,-13636(r2)
+ 8002c40:	21400117 	ldw	r5,4(r4)
+ 8002c44:	8007adc1 	jmpi	8007adc <_getc_r>
+
+08002c48 <_printf_r>:
+ 8002c48:	defffd04 	addi	sp,sp,-12
+ 8002c4c:	2805883a 	mov	r2,r5
+ 8002c50:	dfc00015 	stw	ra,0(sp)
+ 8002c54:	d9800115 	stw	r6,4(sp)
+ 8002c58:	d9c00215 	stw	r7,8(sp)
+ 8002c5c:	21400217 	ldw	r5,8(r4)
+ 8002c60:	d9c00104 	addi	r7,sp,4
+ 8002c64:	100d883a 	mov	r6,r2
+ 8002c68:	8002e440 	call	8002e44 <___vfprintf_internal_r>
+ 8002c6c:	dfc00017 	ldw	ra,0(sp)
+ 8002c70:	dec00304 	addi	sp,sp,12
+ 8002c74:	f800283a 	ret
+
+08002c78 <printf>:
+ 8002c78:	defffc04 	addi	sp,sp,-16
+ 8002c7c:	dfc00015 	stw	ra,0(sp)
+ 8002c80:	d9400115 	stw	r5,4(sp)
+ 8002c84:	d9800215 	stw	r6,8(sp)
+ 8002c88:	d9c00315 	stw	r7,12(sp)
+ 8002c8c:	00820174 	movhi	r2,2053
+ 8002c90:	10b2af17 	ldw	r2,-13636(r2)
+ 8002c94:	200b883a 	mov	r5,r4
+ 8002c98:	d9800104 	addi	r6,sp,4
+ 8002c9c:	11000217 	ldw	r4,8(r2)
+ 8002ca0:	8004fa40 	call	8004fa4 <__vfprintf_internal>
+ 8002ca4:	dfc00017 	ldw	ra,0(sp)
+ 8002ca8:	dec00404 	addi	sp,sp,16
+ 8002cac:	f800283a 	ret
+
+08002cb0 <_putchar_r>:
+ 8002cb0:	21800217 	ldw	r6,8(r4)
+ 8002cb4:	80099101 	jmpi	8009910 <_putc_r>
+
+08002cb8 <putchar>:
+ 8002cb8:	00820174 	movhi	r2,2053
+ 8002cbc:	10b2af17 	ldw	r2,-13636(r2)
+ 8002cc0:	200b883a 	mov	r5,r4
+ 8002cc4:	11800217 	ldw	r6,8(r2)
+ 8002cc8:	1009883a 	mov	r4,r2
+ 8002ccc:	80099101 	jmpi	8009910 <_putc_r>
+
+08002cd0 <_puts_r>:
+ 8002cd0:	defff504 	addi	sp,sp,-44
+ 8002cd4:	dc000815 	stw	r16,32(sp)
+ 8002cd8:	2021883a 	mov	r16,r4
+ 8002cdc:	2809883a 	mov	r4,r5
+ 8002ce0:	dc400915 	stw	r17,36(sp)
+ 8002ce4:	dfc00a15 	stw	ra,40(sp)
+ 8002ce8:	2823883a 	mov	r17,r5
+ 8002cec:	8002dac0 	call	8002dac <strlen>
+ 8002cf0:	11000044 	addi	r4,r2,1
+ 8002cf4:	d8800515 	stw	r2,20(sp)
+ 8002cf8:	00800044 	movi	r2,1
+ 8002cfc:	00c20134 	movhi	r3,2052
+ 8002d00:	d8800715 	stw	r2,28(sp)
+ 8002d04:	d8800404 	addi	r2,sp,16
+ 8002d08:	18dd1604 	addi	r3,r3,29784
+ 8002d0c:	d8800115 	stw	r2,4(sp)
+ 8002d10:	00800084 	movi	r2,2
+ 8002d14:	dc400415 	stw	r17,16(sp)
+ 8002d18:	d8c00615 	stw	r3,24(sp)
+ 8002d1c:	d9000315 	stw	r4,12(sp)
+ 8002d20:	d8800215 	stw	r2,8(sp)
+ 8002d24:	81400217 	ldw	r5,8(r16)
+ 8002d28:	80000226 	beq	r16,zero,8002d34 <_puts_r+0x64>
+ 8002d2c:	80800e17 	ldw	r2,56(r16)
+ 8002d30:	10001326 	beq	r2,zero,8002d80 <_puts_r+0xb0>
+ 8002d34:	2880030b 	ldhu	r2,12(r5)
+ 8002d38:	10c8000c 	andi	r3,r2,8192
+ 8002d3c:	1800061e 	bne	r3,zero,8002d58 <_puts_r+0x88>
+ 8002d40:	28c01917 	ldw	r3,100(r5)
+ 8002d44:	0137ffc4 	movi	r4,-8193
+ 8002d48:	10880014 	ori	r2,r2,8192
+ 8002d4c:	1906703a 	and	r3,r3,r4
+ 8002d50:	2880030d 	sth	r2,12(r5)
+ 8002d54:	28c01915 	stw	r3,100(r5)
+ 8002d58:	d9800104 	addi	r6,sp,4
+ 8002d5c:	8009883a 	mov	r4,r16
+ 8002d60:	80074c00 	call	80074c0 <__sfvwrite_r>
+ 8002d64:	10000b1e 	bne	r2,zero,8002d94 <_puts_r+0xc4>
+ 8002d68:	00800284 	movi	r2,10
+ 8002d6c:	dfc00a17 	ldw	ra,40(sp)
+ 8002d70:	dc400917 	ldw	r17,36(sp)
+ 8002d74:	dc000817 	ldw	r16,32(sp)
+ 8002d78:	dec00b04 	addi	sp,sp,44
+ 8002d7c:	f800283a 	ret
+ 8002d80:	8009883a 	mov	r4,r16
+ 8002d84:	d9400015 	stw	r5,0(sp)
+ 8002d88:	80070600 	call	8007060 <__sinit>
+ 8002d8c:	d9400017 	ldw	r5,0(sp)
+ 8002d90:	003fe806 	br	8002d34 <_puts_r+0x64>
+ 8002d94:	00bfffc4 	movi	r2,-1
+ 8002d98:	003ff406 	br	8002d6c <_puts_r+0x9c>
+
+08002d9c <puts>:
+ 8002d9c:	00820174 	movhi	r2,2053
+ 8002da0:	200b883a 	mov	r5,r4
+ 8002da4:	1132af17 	ldw	r4,-13636(r2)
+ 8002da8:	8002cd01 	jmpi	8002cd0 <_puts_r>
+
+08002dac <strlen>:
+ 8002dac:	208000cc 	andi	r2,r4,3
+ 8002db0:	10002026 	beq	r2,zero,8002e34 <strlen+0x88>
+ 8002db4:	20800007 	ldb	r2,0(r4)
+ 8002db8:	10002026 	beq	r2,zero,8002e3c <strlen+0x90>
+ 8002dbc:	2005883a 	mov	r2,r4
+ 8002dc0:	00000206 	br	8002dcc <strlen+0x20>
+ 8002dc4:	10c00007 	ldb	r3,0(r2)
+ 8002dc8:	18001826 	beq	r3,zero,8002e2c <strlen+0x80>
+ 8002dcc:	10800044 	addi	r2,r2,1
+ 8002dd0:	10c000cc 	andi	r3,r2,3
+ 8002dd4:	183ffb1e 	bne	r3,zero,8002dc4 <strlen+0x18>
+ 8002dd8:	11400017 	ldw	r5,0(r2)
+ 8002ddc:	01ffbff4 	movhi	r7,65279
+ 8002de0:	39ffbfc4 	addi	r7,r7,-257
+ 8002de4:	29c7883a 	add	r3,r5,r7
+ 8002de8:	01a02074 	movhi	r6,32897
+ 8002dec:	014a303a 	nor	r5,zero,r5
+ 8002df0:	1946703a 	and	r3,r3,r5
+ 8002df4:	31a02004 	addi	r6,r6,-32640
+ 8002df8:	1986703a 	and	r3,r3,r6
+ 8002dfc:	1800091e 	bne	r3,zero,8002e24 <strlen+0x78>
+ 8002e00:	10800104 	addi	r2,r2,4
+ 8002e04:	11400017 	ldw	r5,0(r2)
+ 8002e08:	29c7883a 	add	r3,r5,r7
+ 8002e0c:	014a303a 	nor	r5,zero,r5
+ 8002e10:	1946703a 	and	r3,r3,r5
+ 8002e14:	1986703a 	and	r3,r3,r6
+ 8002e18:	183ff926 	beq	r3,zero,8002e00 <strlen+0x54>
+ 8002e1c:	00000106 	br	8002e24 <strlen+0x78>
+ 8002e20:	10800044 	addi	r2,r2,1
+ 8002e24:	10c00007 	ldb	r3,0(r2)
+ 8002e28:	183ffd1e 	bne	r3,zero,8002e20 <strlen+0x74>
+ 8002e2c:	1105c83a 	sub	r2,r2,r4
+ 8002e30:	f800283a 	ret
+ 8002e34:	2005883a 	mov	r2,r4
+ 8002e38:	003fe706 	br	8002dd8 <strlen+0x2c>
+ 8002e3c:	0005883a 	mov	r2,zero
+ 8002e40:	f800283a 	ret
+
+08002e44 <___vfprintf_internal_r>:
+ 8002e44:	deffbd04 	addi	sp,sp,-268
+ 8002e48:	dfc04215 	stw	ra,264(sp)
+ 8002e4c:	dd003d15 	stw	r20,244(sp)
+ 8002e50:	dcc03c15 	stw	r19,240(sp)
+ 8002e54:	dc003915 	stw	r16,228(sp)
+ 8002e58:	d9000515 	stw	r4,20(sp)
+ 8002e5c:	2021883a 	mov	r16,r4
+ 8002e60:	2827883a 	mov	r19,r5
+ 8002e64:	3029883a 	mov	r20,r6
+ 8002e68:	d9c00615 	stw	r7,24(sp)
+ 8002e6c:	df004115 	stw	fp,260(sp)
+ 8002e70:	ddc04015 	stw	r23,256(sp)
+ 8002e74:	dd803f15 	stw	r22,252(sp)
+ 8002e78:	dd403e15 	stw	r21,248(sp)
+ 8002e7c:	dc803b15 	stw	r18,236(sp)
+ 8002e80:	dc403a15 	stw	r17,232(sp)
+ 8002e84:	8007bf00 	call	8007bf0 <_localeconv_r>
+ 8002e88:	10800017 	ldw	r2,0(r2)
+ 8002e8c:	1009883a 	mov	r4,r2
+ 8002e90:	d8800d15 	stw	r2,52(sp)
+ 8002e94:	8002dac0 	call	8002dac <strlen>
+ 8002e98:	d8800b15 	stw	r2,44(sp)
+ 8002e9c:	80000226 	beq	r16,zero,8002ea8 <___vfprintf_internal_r+0x64>
+ 8002ea0:	80800e17 	ldw	r2,56(r16)
+ 8002ea4:	1002da26 	beq	r2,zero,8003a10 <___vfprintf_internal_r+0xbcc>
+ 8002ea8:	9880030b 	ldhu	r2,12(r19)
+ 8002eac:	10c8000c 	andi	r3,r2,8192
+ 8002eb0:	1800061e 	bne	r3,zero,8002ecc <___vfprintf_internal_r+0x88>
+ 8002eb4:	98c01917 	ldw	r3,100(r19)
+ 8002eb8:	0137ffc4 	movi	r4,-8193
+ 8002ebc:	10880014 	ori	r2,r2,8192
+ 8002ec0:	1906703a 	and	r3,r3,r4
+ 8002ec4:	9880030d 	sth	r2,12(r19)
+ 8002ec8:	98c01915 	stw	r3,100(r19)
+ 8002ecc:	10c0020c 	andi	r3,r2,8
+ 8002ed0:	18009a26 	beq	r3,zero,800313c <___vfprintf_internal_r+0x2f8>
+ 8002ed4:	98c00417 	ldw	r3,16(r19)
+ 8002ed8:	18009826 	beq	r3,zero,800313c <___vfprintf_internal_r+0x2f8>
+ 8002edc:	1080068c 	andi	r2,r2,26
+ 8002ee0:	10800298 	cmpnei	r2,r2,10
+ 8002ee4:	10009d26 	beq	r2,zero,800315c <___vfprintf_internal_r+0x318>
+ 8002ee8:	ddc02904 	addi	r23,sp,164
+ 8002eec:	ddc01c15 	stw	r23,112(sp)
+ 8002ef0:	d8001e15 	stw	zero,120(sp)
+ 8002ef4:	d8001d15 	stw	zero,116(sp)
+ 8002ef8:	d8000815 	stw	zero,32(sp)
+ 8002efc:	d8000915 	stw	zero,36(sp)
+ 8002f00:	d8000a15 	stw	zero,40(sp)
+ 8002f04:	b811883a 	mov	r8,r23
+ 8002f08:	d8000c15 	stw	zero,48(sp)
+ 8002f0c:	d8001115 	stw	zero,68(sp)
+ 8002f10:	d8000415 	stw	zero,16(sp)
+ 8002f14:	a02d883a 	mov	r22,r20
+ 8002f18:	b0800007 	ldb	r2,0(r22)
+ 8002f1c:	1000a226 	beq	r2,zero,80031a8 <___vfprintf_internal_r+0x364>
+ 8002f20:	10800960 	cmpeqi	r2,r2,37
+ 8002f24:	10052e1e 	bne	r2,zero,80043e0 <___vfprintf_internal_r+0x159c>
+ 8002f28:	b021883a 	mov	r16,r22
+ 8002f2c:	00000206 	br	8002f38 <___vfprintf_internal_r+0xf4>
+ 8002f30:	18009326 	beq	r3,zero,8003180 <___vfprintf_internal_r+0x33c>
+ 8002f34:	9021883a 	mov	r16,r18
+ 8002f38:	80800047 	ldb	r2,1(r16)
+ 8002f3c:	84800044 	addi	r18,r16,1
+ 8002f40:	10c00958 	cmpnei	r3,r2,37
+ 8002f44:	103ffa1e 	bne	r2,zero,8002f30 <___vfprintf_internal_r+0xec>
+ 8002f48:	95a3c83a 	sub	r17,r18,r22
+ 8002f4c:	88009626 	beq	r17,zero,80031a8 <___vfprintf_internal_r+0x364>
+ 8002f50:	d8c01e17 	ldw	r3,120(sp)
+ 8002f54:	d8801d17 	ldw	r2,116(sp)
+ 8002f58:	45800015 	stw	r22,0(r8)
+ 8002f5c:	1c47883a 	add	r3,r3,r17
+ 8002f60:	10800044 	addi	r2,r2,1
+ 8002f64:	d8801d15 	stw	r2,116(sp)
+ 8002f68:	44400115 	stw	r17,4(r8)
+ 8002f6c:	d8c01e15 	stw	r3,120(sp)
+ 8002f70:	10800208 	cmpgei	r2,r2,8
+ 8002f74:	1000851e 	bne	r2,zero,800318c <___vfprintf_internal_r+0x348>
+ 8002f78:	42000204 	addi	r8,r8,8
+ 8002f7c:	d8c00417 	ldw	r3,16(sp)
+ 8002f80:	80800047 	ldb	r2,1(r16)
+ 8002f84:	1c47883a 	add	r3,r3,r17
+ 8002f88:	d8c00415 	stw	r3,16(sp)
+ 8002f8c:	10008626 	beq	r2,zero,80031a8 <___vfprintf_internal_r+0x364>
+ 8002f90:	92800047 	ldb	r10,1(r18)
+ 8002f94:	95800044 	addi	r22,r18,1
+ 8002f98:	d8001545 	stb	zero,85(sp)
+ 8002f9c:	0009883a 	mov	r4,zero
+ 8002fa0:	000b883a 	mov	r5,zero
+ 8002fa4:	02ffffc4 	movi	r11,-1
+ 8002fa8:	0023883a 	mov	r17,zero
+ 8002fac:	0019883a 	mov	r12,zero
+ 8002fb0:	b5800044 	addi	r22,r22,1
+ 8002fb4:	5039883a 	mov	fp,r10
+ 8002fb8:	e0bff804 	addi	r2,fp,-32
+ 8002fbc:	10c01668 	cmpgeui	r3,r2,89
+ 8002fc0:	18009b1e 	bne	r3,zero,8003230 <___vfprintf_internal_r+0x3ec>
+ 8002fc4:	100490ba 	slli	r2,r2,2
+ 8002fc8:	00c20034 	movhi	r3,2048
+ 8002fcc:	10c7883a 	add	r3,r2,r3
+ 8002fd0:	188bf617 	ldw	r2,12248(r3)
+ 8002fd4:	1000683a 	jmp	r2
+ 8002fd8:	08003300 	call	800330 <OSCtxSw_SWITCH_PC+0x8002f0>
+ 8002fdc:	08003230 	cmpltui	zero,at,200
+ 8002fe0:	08003230 	cmpltui	zero,at,200
+ 8002fe4:	080032f4 	orhi	zero,at,203
+ 8002fe8:	08003230 	cmpltui	zero,at,200
+ 8002fec:	08003230 	cmpltui	zero,at,200
+ 8002ff0:	08003230 	cmpltui	zero,at,200
+ 8002ff4:	08003230 	cmpltui	zero,at,200
+ 8002ff8:	08003230 	cmpltui	zero,at,200
+ 8002ffc:	08003230 	cmpltui	zero,at,200
+ 8003000:	080032cc 	andi	zero,at,203
+ 8003004:	080032bc 	xorhi	zero,at,202
+ 8003008:	08003230 	cmpltui	zero,at,200
+ 800300c:	080032a4 	muli	zero,at,202
+ 8003010:	08003260 	cmpeqi	zero,at,201
+ 8003014:	08003230 	cmpltui	zero,at,200
+ 8003018:	08003254 	ori	zero,at,201
+ 800301c:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003020:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003024:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003028:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 800302c:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003030:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003034:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003038:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 800303c:	08003200 	call	800320 <OSCtxSw_SWITCH_PC+0x8002e0>
+ 8003040:	08003230 	cmpltui	zero,at,200
+ 8003044:	08003230 	cmpltui	zero,at,200
+ 8003048:	08003230 	cmpltui	zero,at,200
+ 800304c:	08003230 	cmpltui	zero,at,200
+ 8003050:	08003230 	cmpltui	zero,at,200
+ 8003054:	08003230 	cmpltui	zero,at,200
+ 8003058:	08003230 	cmpltui	zero,at,200
+ 800305c:	08003230 	cmpltui	zero,at,200
+ 8003060:	08003230 	cmpltui	zero,at,200
+ 8003064:	08003230 	cmpltui	zero,at,200
+ 8003068:	08003814 	ori	zero,at,224
+ 800306c:	08003734 	orhi	zero,at,220
+ 8003070:	08003230 	cmpltui	zero,at,200
+ 8003074:	08003734 	orhi	zero,at,220
+ 8003078:	08003230 	cmpltui	zero,at,200
+ 800307c:	08003230 	cmpltui	zero,at,200
+ 8003080:	08003230 	cmpltui	zero,at,200
+ 8003084:	08003230 	cmpltui	zero,at,200
+ 8003088:	08003728 	cmpgeui	zero,at,220
+ 800308c:	08003230 	cmpltui	zero,at,200
+ 8003090:	08003230 	cmpltui	zero,at,200
+ 8003094:	080036f4 	orhi	zero,at,219
+ 8003098:	08003230 	cmpltui	zero,at,200
+ 800309c:	08003230 	cmpltui	zero,at,200
+ 80030a0:	08003230 	cmpltui	zero,at,200
+ 80030a4:	08003230 	cmpltui	zero,at,200
+ 80030a8:	08003230 	cmpltui	zero,at,200
+ 80030ac:	08003934 	orhi	zero,at,228
+ 80030b0:	08003230 	cmpltui	zero,at,200
+ 80030b4:	08003230 	cmpltui	zero,at,200
+ 80030b8:	080038ec 	andhi	zero,at,227
+ 80030bc:	08003230 	cmpltui	zero,at,200
+ 80030c0:	08003230 	cmpltui	zero,at,200
+ 80030c4:	08003230 	cmpltui	zero,at,200
+ 80030c8:	08003230 	cmpltui	zero,at,200
+ 80030cc:	08003230 	cmpltui	zero,at,200
+ 80030d0:	08003230 	cmpltui	zero,at,200
+ 80030d4:	08003230 	cmpltui	zero,at,200
+ 80030d8:	08003230 	cmpltui	zero,at,200
+ 80030dc:	08003230 	cmpltui	zero,at,200
+ 80030e0:	08003230 	cmpltui	zero,at,200
+ 80030e4:	08003484 	addi	zero,at,210
+ 80030e8:	08003410 	cmplti	zero,at,208
+ 80030ec:	08003734 	orhi	zero,at,220
+ 80030f0:	08003734 	orhi	zero,at,220
+ 80030f4:	08003734 	orhi	zero,at,220
+ 80030f8:	08003a04 	addi	zero,at,232
+ 80030fc:	08003410 	cmplti	zero,at,208
+ 8003100:	08003230 	cmpltui	zero,at,200
+ 8003104:	08003230 	cmpltui	zero,at,200
+ 8003108:	080039f0 	cmpltui	zero,at,231
+ 800310c:	08003230 	cmpltui	zero,at,200
+ 8003110:	080036b4 	orhi	zero,at,218
+ 8003114:	08003674 	orhi	zero,at,217
+ 8003118:	08003974 	orhi	zero,at,229
+ 800311c:	08003968 	cmpgeui	zero,at,229
+ 8003120:	08003230 	cmpltui	zero,at,200
+ 8003124:	080033b4 	orhi	zero,at,206
+ 8003128:	08003230 	cmpltui	zero,at,200
+ 800312c:	08003374 	orhi	zero,at,205
+ 8003130:	08003230 	cmpltui	zero,at,200
+ 8003134:	08003230 	cmpltui	zero,at,200
+ 8003138:	0800332c 	andhi	zero,at,204
+ 800313c:	d9000517 	ldw	r4,20(sp)
+ 8003140:	980b883a 	mov	r5,r19
+ 8003144:	800507c0 	call	800507c <__swsetup_r>
+ 8003148:	10074c1e 	bne	r2,zero,8004e7c <___vfprintf_internal_r+0x2038>
+ 800314c:	9880030b 	ldhu	r2,12(r19)
+ 8003150:	1080068c 	andi	r2,r2,26
+ 8003154:	10800298 	cmpnei	r2,r2,10
+ 8003158:	103f631e 	bne	r2,zero,8002ee8 <___vfprintf_internal_r+0xa4>
+ 800315c:	9880038f 	ldh	r2,14(r19)
+ 8003160:	103f6116 	blt	r2,zero,8002ee8 <___vfprintf_internal_r+0xa4>
+ 8003164:	d9c00617 	ldw	r7,24(sp)
+ 8003168:	d9000517 	ldw	r4,20(sp)
+ 800316c:	a00d883a 	mov	r6,r20
+ 8003170:	980b883a 	mov	r5,r19
+ 8003174:	8004fbc0 	call	8004fbc <__sbprintf>
+ 8003178:	d8800415 	stw	r2,16(sp)
+ 800317c:	00001306 	br	80031cc <___vfprintf_internal_r+0x388>
+ 8003180:	95a3c83a 	sub	r17,r18,r22
+ 8003184:	883f8226 	beq	r17,zero,8002f90 <___vfprintf_internal_r+0x14c>
+ 8003188:	003f7106 	br	8002f50 <___vfprintf_internal_r+0x10c>
+ 800318c:	d9000517 	ldw	r4,20(sp)
+ 8003190:	d9801c04 	addi	r6,sp,112
+ 8003194:	980b883a 	mov	r5,r19
+ 8003198:	800a3f80 	call	800a3f8 <__sprint_r>
+ 800319c:	1000081e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80031a0:	b811883a 	mov	r8,r23
+ 80031a4:	003f7506 	br	8002f7c <___vfprintf_internal_r+0x138>
+ 80031a8:	d8801e17 	ldw	r2,120(sp)
+ 80031ac:	10000426 	beq	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80031b0:	d9000517 	ldw	r4,20(sp)
+ 80031b4:	d9801c04 	addi	r6,sp,112
+ 80031b8:	980b883a 	mov	r5,r19
+ 80031bc:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80031c0:	9880030b 	ldhu	r2,12(r19)
+ 80031c4:	1080100c 	andi	r2,r2,64
+ 80031c8:	10072c1e 	bne	r2,zero,8004e7c <___vfprintf_internal_r+0x2038>
+ 80031cc:	d8800417 	ldw	r2,16(sp)
+ 80031d0:	dfc04217 	ldw	ra,264(sp)
+ 80031d4:	df004117 	ldw	fp,260(sp)
+ 80031d8:	ddc04017 	ldw	r23,256(sp)
+ 80031dc:	dd803f17 	ldw	r22,252(sp)
+ 80031e0:	dd403e17 	ldw	r21,248(sp)
+ 80031e4:	dd003d17 	ldw	r20,244(sp)
+ 80031e8:	dcc03c17 	ldw	r19,240(sp)
+ 80031ec:	dc803b17 	ldw	r18,236(sp)
+ 80031f0:	dc403a17 	ldw	r17,232(sp)
+ 80031f4:	dc003917 	ldw	r16,228(sp)
+ 80031f8:	dec04304 	addi	sp,sp,268
+ 80031fc:	f800283a 	ret
+ 8003200:	0023883a 	mov	r17,zero
+ 8003204:	e0bff404 	addi	r2,fp,-48
+ 8003208:	b5800044 	addi	r22,r22,1
+ 800320c:	8c4002a4 	muli	r17,r17,10
+ 8003210:	b73fffc7 	ldb	fp,-1(r22)
+ 8003214:	1463883a 	add	r17,r2,r17
+ 8003218:	e0bff404 	addi	r2,fp,-48
+ 800321c:	10c002b0 	cmpltui	r3,r2,10
+ 8003220:	183ff91e 	bne	r3,zero,8003208 <___vfprintf_internal_r+0x3c4>
+ 8003224:	e0bff804 	addi	r2,fp,-32
+ 8003228:	10c01668 	cmpgeui	r3,r2,89
+ 800322c:	183f6526 	beq	r3,zero,8002fc4 <___vfprintf_internal_r+0x180>
+ 8003230:	21003fcc 	andi	r4,r4,255
+ 8003234:	20066d1e 	bne	r4,zero,8004bec <___vfprintf_internal_r+0x1da8>
+ 8003238:	e03fdb26 	beq	fp,zero,80031a8 <___vfprintf_internal_r+0x364>
+ 800323c:	df001f05 	stb	fp,124(sp)
+ 8003240:	d8001545 	stb	zero,85(sp)
+ 8003244:	05400044 	movi	r21,1
+ 8003248:	05000044 	movi	r20,1
+ 800324c:	dc001f04 	addi	r16,sp,124
+ 8003250:	00009506 	br	80034a8 <___vfprintf_internal_r+0x664>
+ 8003254:	63002014 	ori	r12,r12,128
+ 8003258:	b2800007 	ldb	r10,0(r22)
+ 800325c:	003f5406 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003260:	b7000007 	ldb	fp,0(r22)
+ 8003264:	b0c00044 	addi	r3,r22,1
+ 8003268:	e0800aa0 	cmpeqi	r2,fp,42
+ 800326c:	1007411e 	bne	r2,zero,8004f74 <___vfprintf_internal_r+0x2130>
+ 8003270:	e0bff404 	addi	r2,fp,-48
+ 8003274:	118002b0 	cmpltui	r6,r2,10
+ 8003278:	182d883a 	mov	r22,r3
+ 800327c:	0017883a 	mov	r11,zero
+ 8003280:	303f4d26 	beq	r6,zero,8002fb8 <___vfprintf_internal_r+0x174>
+ 8003284:	b5800044 	addi	r22,r22,1
+ 8003288:	5ac002a4 	muli	r11,r11,10
+ 800328c:	b73fffc7 	ldb	fp,-1(r22)
+ 8003290:	5897883a 	add	r11,r11,r2
+ 8003294:	e0bff404 	addi	r2,fp,-48
+ 8003298:	10c002b0 	cmpltui	r3,r2,10
+ 800329c:	183ff91e 	bne	r3,zero,8003284 <___vfprintf_internal_r+0x440>
+ 80032a0:	003f4506 	br	8002fb8 <___vfprintf_internal_r+0x174>
+ 80032a4:	b7000003 	ldbu	fp,0(r22)
+ 80032a8:	e2803fcc 	andi	r10,fp,255
+ 80032ac:	5280201c 	xori	r10,r10,128
+ 80032b0:	63000114 	ori	r12,r12,4
+ 80032b4:	52bfe004 	addi	r10,r10,-128
+ 80032b8:	003f3d06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 80032bc:	01000044 	movi	r4,1
+ 80032c0:	01400ac4 	movi	r5,43
+ 80032c4:	b2800007 	ldb	r10,0(r22)
+ 80032c8:	003f3906 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 80032cc:	d8800617 	ldw	r2,24(sp)
+ 80032d0:	b7000003 	ldbu	fp,0(r22)
+ 80032d4:	14400017 	ldw	r17,0(r2)
+ 80032d8:	10800104 	addi	r2,r2,4
+ 80032dc:	8804d716 	blt	r17,zero,800463c <___vfprintf_internal_r+0x17f8>
+ 80032e0:	d8800615 	stw	r2,24(sp)
+ 80032e4:	e2803fcc 	andi	r10,fp,255
+ 80032e8:	5280201c 	xori	r10,r10,128
+ 80032ec:	52bfe004 	addi	r10,r10,-128
+ 80032f0:	003f2f06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 80032f4:	63000054 	ori	r12,r12,1
+ 80032f8:	b2800007 	ldb	r10,0(r22)
+ 80032fc:	003f2c06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003300:	28803fcc 	andi	r2,r5,255
+ 8003304:	1080201c 	xori	r2,r2,128
+ 8003308:	10bfe004 	addi	r2,r2,-128
+ 800330c:	b7000003 	ldbu	fp,0(r22)
+ 8003310:	103ff41e 	bne	r2,zero,80032e4 <___vfprintf_internal_r+0x4a0>
+ 8003314:	e2803fcc 	andi	r10,fp,255
+ 8003318:	5280201c 	xori	r10,r10,128
+ 800331c:	01000044 	movi	r4,1
+ 8003320:	01400804 	movi	r5,32
+ 8003324:	52bfe004 	addi	r10,r10,-128
+ 8003328:	003f2106 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 800332c:	21003fcc 	andi	r4,r4,255
+ 8003330:	2006b31e 	bne	r4,zero,8004e00 <___vfprintf_internal_r+0x1fbc>
+ 8003334:	00820134 	movhi	r2,2052
+ 8003338:	109d2004 	addi	r2,r2,29824
+ 800333c:	d8800c15 	stw	r2,48(sp)
+ 8003340:	6080080c 	andi	r2,r12,32
+ 8003344:	10017026 	beq	r2,zero,8003908 <___vfprintf_internal_r+0xac4>
+ 8003348:	d8800617 	ldw	r2,24(sp)
+ 800334c:	15400017 	ldw	r21,0(r2)
+ 8003350:	15000117 	ldw	r20,4(r2)
+ 8003354:	10800204 	addi	r2,r2,8
+ 8003358:	d8800615 	stw	r2,24(sp)
+ 800335c:	6080004c 	andi	r2,r12,1
+ 8003360:	10000226 	beq	r2,zero,800336c <___vfprintf_internal_r+0x528>
+ 8003364:	ad04b03a 	or	r2,r21,r20
+ 8003368:	1004a71e 	bne	r2,zero,8004608 <___vfprintf_internal_r+0x17c4>
+ 800336c:	00800084 	movi	r2,2
+ 8003370:	00018f06 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8003374:	21003fcc 	andi	r4,r4,255
+ 8003378:	20069f1e 	bne	r4,zero,8004df8 <___vfprintf_internal_r+0x1fb4>
+ 800337c:	6080080c 	andi	r2,r12,32
+ 8003380:	1001b41e 	bne	r2,zero,8003a54 <___vfprintf_internal_r+0xc10>
+ 8003384:	d8800617 	ldw	r2,24(sp)
+ 8003388:	60c0040c 	andi	r3,r12,16
+ 800338c:	15400017 	ldw	r21,0(r2)
+ 8003390:	10800104 	addi	r2,r2,4
+ 8003394:	18016e1e 	bne	r3,zero,8003950 <___vfprintf_internal_r+0xb0c>
+ 8003398:	60c0100c 	andi	r3,r12,64
+ 800339c:	18059f26 	beq	r3,zero,8004a1c <___vfprintf_internal_r+0x1bd8>
+ 80033a0:	d8800615 	stw	r2,24(sp)
+ 80033a4:	ad7fffcc 	andi	r21,r21,65535
+ 80033a8:	0029883a 	mov	r20,zero
+ 80033ac:	00800044 	movi	r2,1
+ 80033b0:	00017f06 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 80033b4:	d8800617 	ldw	r2,24(sp)
+ 80033b8:	d8001545 	stb	zero,85(sp)
+ 80033bc:	14000017 	ldw	r16,0(r2)
+ 80033c0:	14800104 	addi	r18,r2,4
+ 80033c4:	8004c726 	beq	r16,zero,80046e4 <___vfprintf_internal_r+0x18a0>
+ 80033c8:	da000e15 	stw	r8,56(sp)
+ 80033cc:	db000715 	stw	r12,28(sp)
+ 80033d0:	58bfffe0 	cmpeqi	r2,r11,-1
+ 80033d4:	1005691e 	bne	r2,zero,800497c <___vfprintf_internal_r+0x1b38>
+ 80033d8:	580d883a 	mov	r6,r11
+ 80033dc:	000b883a 	mov	r5,zero
+ 80033e0:	8009883a 	mov	r4,r16
+ 80033e4:	dac00615 	stw	r11,24(sp)
+ 80033e8:	80085d00 	call	80085d0 <memchr>
+ 80033ec:	dac00617 	ldw	r11,24(sp)
+ 80033f0:	db000717 	ldw	r12,28(sp)
+ 80033f4:	da000e17 	ldw	r8,56(sp)
+ 80033f8:	10066726 	beq	r2,zero,8004d98 <___vfprintf_internal_r+0x1f54>
+ 80033fc:	1429c83a 	sub	r20,r2,r16
+ 8003400:	a02b883a 	mov	r21,r20
+ 8003404:	a005f716 	blt	r20,zero,8004be4 <___vfprintf_internal_r+0x1da0>
+ 8003408:	dc800615 	stw	r18,24(sp)
+ 800340c:	00002606 	br	80034a8 <___vfprintf_internal_r+0x664>
+ 8003410:	21003fcc 	andi	r4,r4,255
+ 8003414:	2006761e 	bne	r4,zero,8004df0 <___vfprintf_internal_r+0x1fac>
+ 8003418:	6080080c 	andi	r2,r12,32
+ 800341c:	10017f1e 	bne	r2,zero,8003a1c <___vfprintf_internal_r+0xbd8>
+ 8003420:	d8800617 	ldw	r2,24(sp)
+ 8003424:	60c0040c 	andi	r3,r12,16
+ 8003428:	10800104 	addi	r2,r2,4
+ 800342c:	1801001e 	bne	r3,zero,8003830 <___vfprintf_internal_r+0x9ec>
+ 8003430:	60c0100c 	andi	r3,r12,64
+ 8003434:	1800fe26 	beq	r3,zero,8003830 <___vfprintf_internal_r+0x9ec>
+ 8003438:	d8c00617 	ldw	r3,24(sp)
+ 800343c:	d8800615 	stw	r2,24(sp)
+ 8003440:	1d40000f 	ldh	r21,0(r3)
+ 8003444:	a829d7fa 	srai	r20,r21,31
+ 8003448:	a005883a 	mov	r2,r20
+ 800344c:	1000fe16 	blt	r2,zero,8003848 <___vfprintf_internal_r+0xa04>
+ 8003450:	58bfffd8 	cmpnei	r2,r11,-1
+ 8003454:	db401543 	ldbu	r13,85(sp)
+ 8003458:	10018526 	beq	r2,zero,8003a70 <___vfprintf_internal_r+0xc2c>
+ 800345c:	00ffdfc4 	movi	r3,-129
+ 8003460:	ad04b03a 	or	r2,r21,r20
+ 8003464:	60d8703a 	and	r12,r12,r3
+ 8003468:	1001811e 	bne	r2,zero,8003a70 <___vfprintf_internal_r+0xc2c>
+ 800346c:	5801831e 	bne	r11,zero,8003a7c <___vfprintf_internal_r+0xc38>
+ 8003470:	6025883a 	mov	r18,r12
+ 8003474:	0017883a 	mov	r11,zero
+ 8003478:	0029883a 	mov	r20,zero
+ 800347c:	b821883a 	mov	r16,r23
+ 8003480:	00018306 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 8003484:	d8c00617 	ldw	r3,24(sp)
+ 8003488:	d8001545 	stb	zero,85(sp)
+ 800348c:	05400044 	movi	r21,1
+ 8003490:	18800017 	ldw	r2,0(r3)
+ 8003494:	18c00104 	addi	r3,r3,4
+ 8003498:	d8c00615 	stw	r3,24(sp)
+ 800349c:	d8801f05 	stb	r2,124(sp)
+ 80034a0:	05000044 	movi	r20,1
+ 80034a4:	dc001f04 	addi	r16,sp,124
+ 80034a8:	6025883a 	mov	r18,r12
+ 80034ac:	0017883a 	mov	r11,zero
+ 80034b0:	d8000715 	stw	zero,28(sp)
+ 80034b4:	9380008c 	andi	r14,r18,2
+ 80034b8:	70000126 	beq	r14,zero,80034c0 <___vfprintf_internal_r+0x67c>
+ 80034bc:	ad400084 	addi	r21,r21,2
+ 80034c0:	9340210c 	andi	r13,r18,132
+ 80034c4:	d8c01e17 	ldw	r3,120(sp)
+ 80034c8:	6800021e 	bne	r13,zero,80034d4 <___vfprintf_internal_r+0x690>
+ 80034cc:	8d4fc83a 	sub	r7,r17,r21
+ 80034d0:	01c2ce16 	blt	zero,r7,800400c <___vfprintf_internal_r+0x11c8>
+ 80034d4:	d8801547 	ldb	r2,85(sp)
+ 80034d8:	10000c26 	beq	r2,zero,800350c <___vfprintf_internal_r+0x6c8>
+ 80034dc:	d8801d17 	ldw	r2,116(sp)
+ 80034e0:	d9001544 	addi	r4,sp,85
+ 80034e4:	18c00044 	addi	r3,r3,1
+ 80034e8:	10800044 	addi	r2,r2,1
+ 80034ec:	41000015 	stw	r4,0(r8)
+ 80034f0:	01000044 	movi	r4,1
+ 80034f4:	d8801d15 	stw	r2,116(sp)
+ 80034f8:	41000115 	stw	r4,4(r8)
+ 80034fc:	d8c01e15 	stw	r3,120(sp)
+ 8003500:	10800208 	cmpgei	r2,r2,8
+ 8003504:	1002fb1e 	bne	r2,zero,80040f4 <___vfprintf_internal_r+0x12b0>
+ 8003508:	42000204 	addi	r8,r8,8
+ 800350c:	70000c26 	beq	r14,zero,8003540 <___vfprintf_internal_r+0x6fc>
+ 8003510:	d8801d17 	ldw	r2,116(sp)
+ 8003514:	d9001584 	addi	r4,sp,86
+ 8003518:	18c00084 	addi	r3,r3,2
+ 800351c:	10800044 	addi	r2,r2,1
+ 8003520:	41000015 	stw	r4,0(r8)
+ 8003524:	01000084 	movi	r4,2
+ 8003528:	d8801d15 	stw	r2,116(sp)
+ 800352c:	41000115 	stw	r4,4(r8)
+ 8003530:	d8c01e15 	stw	r3,120(sp)
+ 8003534:	10800208 	cmpgei	r2,r2,8
+ 8003538:	1002fc1e 	bne	r2,zero,800412c <___vfprintf_internal_r+0x12e8>
+ 800353c:	42000204 	addi	r8,r8,8
+ 8003540:	6b402018 	cmpnei	r13,r13,128
+ 8003544:	6801cf26 	beq	r13,zero,8003c84 <___vfprintf_internal_r+0xe40>
+ 8003548:	5d0fc83a 	sub	r7,r11,r20
+ 800354c:	01c20616 	blt	zero,r7,8003d68 <___vfprintf_internal_r+0xf24>
+ 8003550:	9080400c 	andi	r2,r18,256
+ 8003554:	10017c1e 	bne	r2,zero,8003b48 <___vfprintf_internal_r+0xd04>
+ 8003558:	d8801d17 	ldw	r2,116(sp)
+ 800355c:	1d07883a 	add	r3,r3,r20
+ 8003560:	44000015 	stw	r16,0(r8)
+ 8003564:	10800044 	addi	r2,r2,1
+ 8003568:	d8801d15 	stw	r2,116(sp)
+ 800356c:	45000115 	stw	r20,4(r8)
+ 8003570:	d8c01e15 	stw	r3,120(sp)
+ 8003574:	10800208 	cmpgei	r2,r2,8
+ 8003578:	1002571e 	bne	r2,zero,8003ed8 <___vfprintf_internal_r+0x1094>
+ 800357c:	42000204 	addi	r8,r8,8
+ 8003580:	9480010c 	andi	r18,r18,4
+ 8003584:	90000226 	beq	r18,zero,8003590 <___vfprintf_internal_r+0x74c>
+ 8003588:	8d61c83a 	sub	r16,r17,r21
+ 800358c:	04000916 	blt	zero,r16,80035b4 <___vfprintf_internal_r+0x770>
+ 8003590:	8d40010e 	bge	r17,r21,8003598 <___vfprintf_internal_r+0x754>
+ 8003594:	a823883a 	mov	r17,r21
+ 8003598:	d8800417 	ldw	r2,16(sp)
+ 800359c:	1445883a 	add	r2,r2,r17
+ 80035a0:	d8800415 	stw	r2,16(sp)
+ 80035a4:	1802241e 	bne	r3,zero,8003e38 <___vfprintf_internal_r+0xff4>
+ 80035a8:	d8001d15 	stw	zero,116(sp)
+ 80035ac:	b811883a 	mov	r8,r23
+ 80035b0:	003e5906 	br	8002f18 <___vfprintf_internal_r+0xd4>
+ 80035b4:	03020134 	movhi	r12,2052
+ 80035b8:	81000450 	cmplti	r4,r16,17
+ 80035bc:	631d2b84 	addi	r12,r12,29870
+ 80035c0:	d8801d17 	ldw	r2,116(sp)
+ 80035c4:	20001c1e 	bne	r4,zero,8003638 <___vfprintf_internal_r+0x7f4>
+ 80035c8:	04800404 	movi	r18,16
+ 80035cc:	dd000517 	ldw	r20,20(sp)
+ 80035d0:	6039883a 	mov	fp,r12
+ 80035d4:	00000406 	br	80035e8 <___vfprintf_internal_r+0x7a4>
+ 80035d8:	843ffc04 	addi	r16,r16,-16
+ 80035dc:	81000448 	cmpgei	r4,r16,17
+ 80035e0:	42000204 	addi	r8,r8,8
+ 80035e4:	20001326 	beq	r4,zero,8003634 <___vfprintf_internal_r+0x7f0>
+ 80035e8:	10800044 	addi	r2,r2,1
+ 80035ec:	18c00404 	addi	r3,r3,16
+ 80035f0:	47000015 	stw	fp,0(r8)
+ 80035f4:	44800115 	stw	r18,4(r8)
+ 80035f8:	d8c01e15 	stw	r3,120(sp)
+ 80035fc:	d8801d15 	stw	r2,116(sp)
+ 8003600:	11000208 	cmpgei	r4,r2,8
+ 8003604:	203ff426 	beq	r4,zero,80035d8 <___vfprintf_internal_r+0x794>
+ 8003608:	d9801c04 	addi	r6,sp,112
+ 800360c:	980b883a 	mov	r5,r19
+ 8003610:	a009883a 	mov	r4,r20
+ 8003614:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003618:	103ee91e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 800361c:	843ffc04 	addi	r16,r16,-16
+ 8003620:	81000448 	cmpgei	r4,r16,17
+ 8003624:	d8c01e17 	ldw	r3,120(sp)
+ 8003628:	d8801d17 	ldw	r2,116(sp)
+ 800362c:	b811883a 	mov	r8,r23
+ 8003630:	203fed1e 	bne	r4,zero,80035e8 <___vfprintf_internal_r+0x7a4>
+ 8003634:	e019883a 	mov	r12,fp
+ 8003638:	10800044 	addi	r2,r2,1
+ 800363c:	1c07883a 	add	r3,r3,r16
+ 8003640:	d8801d15 	stw	r2,116(sp)
+ 8003644:	43000015 	stw	r12,0(r8)
+ 8003648:	44000115 	stw	r16,4(r8)
+ 800364c:	d8c01e15 	stw	r3,120(sp)
+ 8003650:	10800210 	cmplti	r2,r2,8
+ 8003654:	103fce1e 	bne	r2,zero,8003590 <___vfprintf_internal_r+0x74c>
+ 8003658:	d9000517 	ldw	r4,20(sp)
+ 800365c:	d9801c04 	addi	r6,sp,112
+ 8003660:	980b883a 	mov	r5,r19
+ 8003664:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003668:	103ed51e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 800366c:	d8c01e17 	ldw	r3,120(sp)
+ 8003670:	003fc706 	br	8003590 <___vfprintf_internal_r+0x74c>
+ 8003674:	21003fcc 	andi	r4,r4,255
+ 8003678:	2005d91e 	bne	r4,zero,8004de0 <___vfprintf_internal_r+0x1f9c>
+ 800367c:	6080080c 	andi	r2,r12,32
+ 8003680:	1000ed1e 	bne	r2,zero,8003a38 <___vfprintf_internal_r+0xbf4>
+ 8003684:	d8800617 	ldw	r2,24(sp)
+ 8003688:	60c0040c 	andi	r3,r12,16
+ 800368c:	15400017 	ldw	r21,0(r2)
+ 8003690:	10800104 	addi	r2,r2,4
+ 8003694:	18001e1e 	bne	r3,zero,8003710 <___vfprintf_internal_r+0x8cc>
+ 8003698:	60c0100c 	andi	r3,r12,64
+ 800369c:	1804db26 	beq	r3,zero,8004a0c <___vfprintf_internal_r+0x1bc8>
+ 80036a0:	d8800615 	stw	r2,24(sp)
+ 80036a4:	ad7fffcc 	andi	r21,r21,65535
+ 80036a8:	0029883a 	mov	r20,zero
+ 80036ac:	0005883a 	mov	r2,zero
+ 80036b0:	0000bf06 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 80036b4:	21003fcc 	andi	r4,r4,255
+ 80036b8:	2005cb1e 	bne	r4,zero,8004de8 <___vfprintf_internal_r+0x1fa4>
+ 80036bc:	d9000617 	ldw	r4,24(sp)
+ 80036c0:	6080080c 	andi	r2,r12,32
+ 80036c4:	20c00104 	addi	r3,r4,4
+ 80036c8:	1003d51e 	bne	r2,zero,8004620 <___vfprintf_internal_r+0x17dc>
+ 80036cc:	6080040c 	andi	r2,r12,16
+ 80036d0:	1004301e 	bne	r2,zero,8004794 <___vfprintf_internal_r+0x1950>
+ 80036d4:	6300100c 	andi	r12,r12,64
+ 80036d8:	60042e26 	beq	r12,zero,8004794 <___vfprintf_internal_r+0x1950>
+ 80036dc:	d8800617 	ldw	r2,24(sp)
+ 80036e0:	d8c00615 	stw	r3,24(sp)
+ 80036e4:	d8c00417 	ldw	r3,16(sp)
+ 80036e8:	10800017 	ldw	r2,0(r2)
+ 80036ec:	10c0000d 	sth	r3,0(r2)
+ 80036f0:	003e0906 	br	8002f18 <___vfprintf_internal_r+0xd4>
+ 80036f4:	21003fcc 	andi	r4,r4,255
+ 80036f8:	2005c31e 	bne	r4,zero,8004e08 <___vfprintf_internal_r+0x1fc4>
+ 80036fc:	6080080c 	andi	r2,r12,32
+ 8003700:	63000414 	ori	r12,r12,16
+ 8003704:	1000cc1e 	bne	r2,zero,8003a38 <___vfprintf_internal_r+0xbf4>
+ 8003708:	d8800617 	ldw	r2,24(sp)
+ 800370c:	10800104 	addi	r2,r2,4
+ 8003710:	d8c00617 	ldw	r3,24(sp)
+ 8003714:	0029883a 	mov	r20,zero
+ 8003718:	d8800615 	stw	r2,24(sp)
+ 800371c:	1d400017 	ldw	r21,0(r3)
+ 8003720:	0005883a 	mov	r2,zero
+ 8003724:	0000a206 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8003728:	63000214 	ori	r12,r12,8
+ 800372c:	b2800007 	ldb	r10,0(r22)
+ 8003730:	003e1f06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003734:	21003fcc 	andi	r4,r4,255
+ 8003738:	2005b71e 	bne	r4,zero,8004e18 <___vfprintf_internal_r+0x1fd4>
+ 800373c:	d8c00617 	ldw	r3,24(sp)
+ 8003740:	00a00034 	movhi	r2,32768
+ 8003744:	10bfffc4 	addi	r2,r2,-1
+ 8003748:	1d000117 	ldw	r20,4(r3)
+ 800374c:	1c800017 	ldw	r18,0(r3)
+ 8003750:	01dffc34 	movhi	r7,32752
+ 8003754:	a0a0703a 	and	r16,r20,r2
+ 8003758:	01bfffc4 	movi	r6,-1
+ 800375c:	18800204 	addi	r2,r3,8
+ 8003760:	39ffffc4 	addi	r7,r7,-1
+ 8003764:	9009883a 	mov	r4,r18
+ 8003768:	800b883a 	mov	r5,r16
+ 800376c:	da000f15 	stw	r8,60(sp)
+ 8003770:	dac00e15 	stw	r11,56(sp)
+ 8003774:	db000715 	stw	r12,28(sp)
+ 8003778:	dd000a15 	stw	r20,40(sp)
+ 800377c:	dc800915 	stw	r18,36(sp)
+ 8003780:	d8800615 	stw	r2,24(sp)
+ 8003784:	800f5580 	call	800f558 <__unorddf2>
+ 8003788:	db000717 	ldw	r12,28(sp)
+ 800378c:	dac00e17 	ldw	r11,56(sp)
+ 8003790:	da000f17 	ldw	r8,60(sp)
+ 8003794:	1003161e 	bne	r2,zero,80043f0 <___vfprintf_internal_r+0x15ac>
+ 8003798:	01dffc34 	movhi	r7,32752
+ 800379c:	01bfffc4 	movi	r6,-1
+ 80037a0:	39ffffc4 	addi	r7,r7,-1
+ 80037a4:	9009883a 	mov	r4,r18
+ 80037a8:	800b883a 	mov	r5,r16
+ 80037ac:	800e4700 	call	800e470 <__ledf2>
+ 80037b0:	db000717 	ldw	r12,28(sp)
+ 80037b4:	dac00e17 	ldw	r11,56(sp)
+ 80037b8:	da000f17 	ldw	r8,60(sp)
+ 80037bc:	00830c0e 	bge	zero,r2,80043f0 <___vfprintf_internal_r+0x15ac>
+ 80037c0:	000d883a 	mov	r6,zero
+ 80037c4:	000f883a 	mov	r7,zero
+ 80037c8:	9009883a 	mov	r4,r18
+ 80037cc:	a00b883a 	mov	r5,r20
+ 80037d0:	da000e15 	stw	r8,56(sp)
+ 80037d4:	800e4700 	call	800e470 <__ledf2>
+ 80037d8:	db000717 	ldw	r12,28(sp)
+ 80037dc:	da000e17 	ldw	r8,56(sp)
+ 80037e0:	1004e216 	blt	r2,zero,8004b6c <___vfprintf_internal_r+0x1d28>
+ 80037e4:	db401543 	ldbu	r13,85(sp)
+ 80037e8:	e0801210 	cmplti	r2,fp,72
+ 80037ec:	1004cb1e 	bne	r2,zero,8004b1c <___vfprintf_internal_r+0x1cd8>
+ 80037f0:	04020134 	movhi	r16,2052
+ 80037f4:	841d1804 	addi	r16,r16,29792
+ 80037f8:	04bfdfc4 	movi	r18,-129
+ 80037fc:	64a4703a 	and	r18,r12,r18
+ 8003800:	054000c4 	movi	r21,3
+ 8003804:	050000c4 	movi	r20,3
+ 8003808:	0017883a 	mov	r11,zero
+ 800380c:	d8000715 	stw	zero,28(sp)
+ 8003810:	0000a306 	br	8003aa0 <___vfprintf_internal_r+0xc5c>
+ 8003814:	21003fcc 	andi	r4,r4,255
+ 8003818:	20057d1e 	bne	r4,zero,8004e10 <___vfprintf_internal_r+0x1fcc>
+ 800381c:	6080080c 	andi	r2,r12,32
+ 8003820:	63000414 	ori	r12,r12,16
+ 8003824:	10007d1e 	bne	r2,zero,8003a1c <___vfprintf_internal_r+0xbd8>
+ 8003828:	d8800617 	ldw	r2,24(sp)
+ 800382c:	10800104 	addi	r2,r2,4
+ 8003830:	d8c00617 	ldw	r3,24(sp)
+ 8003834:	1d400017 	ldw	r21,0(r3)
+ 8003838:	d8800615 	stw	r2,24(sp)
+ 800383c:	a829d7fa 	srai	r20,r21,31
+ 8003840:	a005883a 	mov	r2,r20
+ 8003844:	103f020e 	bge	r2,zero,8003450 <___vfprintf_internal_r+0x60c>
+ 8003848:	056bc83a 	sub	r21,zero,r21
+ 800384c:	a804c03a 	cmpne	r2,r21,zero
+ 8003850:	0529c83a 	sub	r20,zero,r20
+ 8003854:	a0a9c83a 	sub	r20,r20,r2
+ 8003858:	00800b44 	movi	r2,45
+ 800385c:	d8801545 	stb	r2,85(sp)
+ 8003860:	58ffffe0 	cmpeqi	r3,r11,-1
+ 8003864:	03400b44 	movi	r13,45
+ 8003868:	00800044 	movi	r2,1
+ 800386c:	18005426 	beq	r3,zero,80039c0 <___vfprintf_internal_r+0xb7c>
+ 8003870:	10c00060 	cmpeqi	r3,r2,1
+ 8003874:	18007e1e 	bne	r3,zero,8003a70 <___vfprintf_internal_r+0xc2c>
+ 8003878:	108000a0 	cmpeqi	r2,r2,2
+ 800387c:	1002371e 	bne	r2,zero,800415c <___vfprintf_internal_r+0x1318>
+ 8003880:	b807883a 	mov	r3,r23
+ 8003884:	00000106 	br	800388c <___vfprintf_internal_r+0xa48>
+ 8003888:	8007883a 	mov	r3,r16
+ 800388c:	a808d0fa 	srli	r4,r21,3
+ 8003890:	a00a977a 	slli	r5,r20,29
+ 8003894:	a028d0fa 	srli	r20,r20,3
+ 8003898:	ad4001cc 	andi	r21,r21,7
+ 800389c:	a8800c04 	addi	r2,r21,48
+ 80038a0:	292ab03a 	or	r21,r5,r4
+ 80038a4:	18bfffc5 	stb	r2,-1(r3)
+ 80038a8:	ad08b03a 	or	r4,r21,r20
+ 80038ac:	1c3fffc4 	addi	r16,r3,-1
+ 80038b0:	203ff51e 	bne	r4,zero,8003888 <___vfprintf_internal_r+0xa44>
+ 80038b4:	6100004c 	andi	r4,r12,1
+ 80038b8:	2000a026 	beq	r4,zero,8003b3c <___vfprintf_internal_r+0xcf8>
+ 80038bc:	10803fcc 	andi	r2,r2,255
+ 80038c0:	1080201c 	xori	r2,r2,128
+ 80038c4:	10bfe004 	addi	r2,r2,-128
+ 80038c8:	10800c18 	cmpnei	r2,r2,48
+ 80038cc:	10009b26 	beq	r2,zero,8003b3c <___vfprintf_internal_r+0xcf8>
+ 80038d0:	18ffff84 	addi	r3,r3,-2
+ 80038d4:	00800c04 	movi	r2,48
+ 80038d8:	80bfffc5 	stb	r2,-1(r16)
+ 80038dc:	b8e9c83a 	sub	r20,r23,r3
+ 80038e0:	6025883a 	mov	r18,r12
+ 80038e4:	1821883a 	mov	r16,r3
+ 80038e8:	00006906 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 80038ec:	21003fcc 	andi	r4,r4,255
+ 80038f0:	2005391e 	bne	r4,zero,8004dd8 <___vfprintf_internal_r+0x1f94>
+ 80038f4:	00820134 	movhi	r2,2052
+ 80038f8:	109d1b04 	addi	r2,r2,29804
+ 80038fc:	d8800c15 	stw	r2,48(sp)
+ 8003900:	6080080c 	andi	r2,r12,32
+ 8003904:	103e901e 	bne	r2,zero,8003348 <___vfprintf_internal_r+0x504>
+ 8003908:	d8c00617 	ldw	r3,24(sp)
+ 800390c:	6080040c 	andi	r2,r12,16
+ 8003910:	1d400017 	ldw	r21,0(r3)
+ 8003914:	18c00104 	addi	r3,r3,4
+ 8003918:	d8c00615 	stw	r3,24(sp)
+ 800391c:	1002ae1e 	bne	r2,zero,80043d8 <___vfprintf_internal_r+0x1594>
+ 8003920:	6080100c 	andi	r2,r12,64
+ 8003924:	1002ac26 	beq	r2,zero,80043d8 <___vfprintf_internal_r+0x1594>
+ 8003928:	ad7fffcc 	andi	r21,r21,65535
+ 800392c:	0029883a 	mov	r20,zero
+ 8003930:	003e8a06 	br	800335c <___vfprintf_internal_r+0x518>
+ 8003934:	21003fcc 	andi	r4,r4,255
+ 8003938:	2005391e 	bne	r4,zero,8004e20 <___vfprintf_internal_r+0x1fdc>
+ 800393c:	6080080c 	andi	r2,r12,32
+ 8003940:	63000414 	ori	r12,r12,16
+ 8003944:	1000431e 	bne	r2,zero,8003a54 <___vfprintf_internal_r+0xc10>
+ 8003948:	d8800617 	ldw	r2,24(sp)
+ 800394c:	10800104 	addi	r2,r2,4
+ 8003950:	d8c00617 	ldw	r3,24(sp)
+ 8003954:	0029883a 	mov	r20,zero
+ 8003958:	d8800615 	stw	r2,24(sp)
+ 800395c:	1d400017 	ldw	r21,0(r3)
+ 8003960:	00800044 	movi	r2,1
+ 8003964:	00001206 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8003968:	63000814 	ori	r12,r12,32
+ 800396c:	b2800007 	ldb	r10,0(r22)
+ 8003970:	003d8f06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003974:	d8c00617 	ldw	r3,24(sp)
+ 8003978:	00800c04 	movi	r2,48
+ 800397c:	d8801585 	stb	r2,86(sp)
+ 8003980:	00801e04 	movi	r2,120
+ 8003984:	01020134 	movhi	r4,2052
+ 8003988:	d88015c5 	stb	r2,87(sp)
+ 800398c:	1d400017 	ldw	r21,0(r3)
+ 8003990:	18800104 	addi	r2,r3,4
+ 8003994:	d8800615 	stw	r2,24(sp)
+ 8003998:	209d2004 	addi	r2,r4,29824
+ 800399c:	d8800c15 	stw	r2,48(sp)
+ 80039a0:	0029883a 	mov	r20,zero
+ 80039a4:	63000094 	ori	r12,r12,2
+ 80039a8:	00800084 	movi	r2,2
+ 80039ac:	07001e04 	movi	fp,120
+ 80039b0:	d8001545 	stb	zero,85(sp)
+ 80039b4:	58ffffe0 	cmpeqi	r3,r11,-1
+ 80039b8:	001b883a 	mov	r13,zero
+ 80039bc:	183fac1e 	bne	r3,zero,8003870 <___vfprintf_internal_r+0xa2c>
+ 80039c0:	04bfdfc4 	movi	r18,-129
+ 80039c4:	ad06b03a 	or	r3,r21,r20
+ 80039c8:	64a4703a 	and	r18,r12,r18
+ 80039cc:	18018d1e 	bne	r3,zero,8004004 <___vfprintf_internal_r+0x11c0>
+ 80039d0:	5803b91e 	bne	r11,zero,80048b8 <___vfprintf_internal_r+0x1a74>
+ 80039d4:	103ea71e 	bne	r2,zero,8003474 <___vfprintf_internal_r+0x630>
+ 80039d8:	6500004c 	andi	r20,r12,1
+ 80039dc:	a0028226 	beq	r20,zero,80043e8 <___vfprintf_internal_r+0x15a4>
+ 80039e0:	00800c04 	movi	r2,48
+ 80039e4:	d88028c5 	stb	r2,163(sp)
+ 80039e8:	dc0028c4 	addi	r16,sp,163
+ 80039ec:	00002806 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 80039f0:	b2800007 	ldb	r10,0(r22)
+ 80039f4:	50801b18 	cmpnei	r2,r10,108
+ 80039f8:	10032926 	beq	r2,zero,80046a0 <___vfprintf_internal_r+0x185c>
+ 80039fc:	63000414 	ori	r12,r12,16
+ 8003a00:	003d6b06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003a04:	63001014 	ori	r12,r12,64
+ 8003a08:	b2800007 	ldb	r10,0(r22)
+ 8003a0c:	003d6806 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 8003a10:	d9000517 	ldw	r4,20(sp)
+ 8003a14:	80070600 	call	8007060 <__sinit>
+ 8003a18:	003d2306 	br	8002ea8 <___vfprintf_internal_r+0x64>
+ 8003a1c:	d8c00617 	ldw	r3,24(sp)
+ 8003a20:	18800117 	ldw	r2,4(r3)
+ 8003a24:	1d400017 	ldw	r21,0(r3)
+ 8003a28:	18c00204 	addi	r3,r3,8
+ 8003a2c:	d8c00615 	stw	r3,24(sp)
+ 8003a30:	1029883a 	mov	r20,r2
+ 8003a34:	003e8506 	br	800344c <___vfprintf_internal_r+0x608>
+ 8003a38:	d8c00617 	ldw	r3,24(sp)
+ 8003a3c:	0005883a 	mov	r2,zero
+ 8003a40:	1d400017 	ldw	r21,0(r3)
+ 8003a44:	1d000117 	ldw	r20,4(r3)
+ 8003a48:	18c00204 	addi	r3,r3,8
+ 8003a4c:	d8c00615 	stw	r3,24(sp)
+ 8003a50:	003fd706 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8003a54:	d8c00617 	ldw	r3,24(sp)
+ 8003a58:	00800044 	movi	r2,1
+ 8003a5c:	1d400017 	ldw	r21,0(r3)
+ 8003a60:	1d000117 	ldw	r20,4(r3)
+ 8003a64:	18c00204 	addi	r3,r3,8
+ 8003a68:	d8c00615 	stw	r3,24(sp)
+ 8003a6c:	003fd006 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8003a70:	a000111e 	bne	r20,zero,8003ab8 <___vfprintf_internal_r+0xc74>
+ 8003a74:	a88002a8 	cmpgeui	r2,r21,10
+ 8003a78:	10000f1e 	bne	r2,zero,8003ab8 <___vfprintf_internal_r+0xc74>
+ 8003a7c:	ad400c04 	addi	r21,r21,48
+ 8003a80:	dd4028c5 	stb	r21,163(sp)
+ 8003a84:	6025883a 	mov	r18,r12
+ 8003a88:	05000044 	movi	r20,1
+ 8003a8c:	dc0028c4 	addi	r16,sp,163
+ 8003a90:	582b883a 	mov	r21,r11
+ 8003a94:	5d00010e 	bge	r11,r20,8003a9c <___vfprintf_internal_r+0xc58>
+ 8003a98:	a02b883a 	mov	r21,r20
+ 8003a9c:	d8000715 	stw	zero,28(sp)
+ 8003aa0:	6b403fcc 	andi	r13,r13,255
+ 8003aa4:	6b40201c 	xori	r13,r13,128
+ 8003aa8:	6b7fe004 	addi	r13,r13,-128
+ 8003aac:	683e8126 	beq	r13,zero,80034b4 <___vfprintf_internal_r+0x670>
+ 8003ab0:	ad400044 	addi	r21,r21,1
+ 8003ab4:	003e7f06 	br	80034b4 <___vfprintf_internal_r+0x670>
+ 8003ab8:	dc400e15 	stw	r17,56(sp)
+ 8003abc:	b821883a 	mov	r16,r23
+ 8003ac0:	a023883a 	mov	r17,r20
+ 8003ac4:	db000715 	stw	r12,28(sp)
+ 8003ac8:	9829883a 	mov	r20,r19
+ 8003acc:	dac00f15 	stw	r11,60(sp)
+ 8003ad0:	4025883a 	mov	r18,r8
+ 8003ad4:	6827883a 	mov	r19,r13
+ 8003ad8:	00000206 	br	8003ae4 <___vfprintf_internal_r+0xca0>
+ 8003adc:	102b883a 	mov	r21,r2
+ 8003ae0:	1823883a 	mov	r17,r3
+ 8003ae4:	a809883a 	mov	r4,r21
+ 8003ae8:	880b883a 	mov	r5,r17
+ 8003aec:	01800284 	movi	r6,10
+ 8003af0:	000f883a 	mov	r7,zero
+ 8003af4:	800c9c00 	call	800c9c0 <__umoddi3>
+ 8003af8:	10800c04 	addi	r2,r2,48
+ 8003afc:	843fffc4 	addi	r16,r16,-1
+ 8003b00:	a809883a 	mov	r4,r21
+ 8003b04:	880b883a 	mov	r5,r17
+ 8003b08:	80800005 	stb	r2,0(r16)
+ 8003b0c:	01800284 	movi	r6,10
+ 8003b10:	000f883a 	mov	r7,zero
+ 8003b14:	800c4280 	call	800c428 <__udivdi3>
+ 8003b18:	883ff01e 	bne	r17,zero,8003adc <___vfprintf_internal_r+0xc98>
+ 8003b1c:	ad4002a8 	cmpgeui	r21,r21,10
+ 8003b20:	a83fee1e 	bne	r21,zero,8003adc <___vfprintf_internal_r+0xc98>
+ 8003b24:	db000717 	ldw	r12,28(sp)
+ 8003b28:	dc400e17 	ldw	r17,56(sp)
+ 8003b2c:	dac00f17 	ldw	r11,60(sp)
+ 8003b30:	981b883a 	mov	r13,r19
+ 8003b34:	9011883a 	mov	r8,r18
+ 8003b38:	a027883a 	mov	r19,r20
+ 8003b3c:	bc29c83a 	sub	r20,r23,r16
+ 8003b40:	6025883a 	mov	r18,r12
+ 8003b44:	003fd206 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 8003b48:	e2801990 	cmplti	r10,fp,102
+ 8003b4c:	5000ea1e 	bne	r10,zero,8003ef8 <___vfprintf_internal_r+0x10b4>
+ 8003b50:	d9000917 	ldw	r4,36(sp)
+ 8003b54:	d9400a17 	ldw	r5,40(sp)
+ 8003b58:	000d883a 	mov	r6,zero
+ 8003b5c:	000f883a 	mov	r7,zero
+ 8003b60:	da000f15 	stw	r8,60(sp)
+ 8003b64:	d8c00e15 	stw	r3,56(sp)
+ 8003b68:	800e3000 	call	800e300 <__eqdf2>
+ 8003b6c:	d8c00e17 	ldw	r3,56(sp)
+ 8003b70:	da000f17 	ldw	r8,60(sp)
+ 8003b74:	1001891e 	bne	r2,zero,800419c <___vfprintf_internal_r+0x1358>
+ 8003b78:	d8801d17 	ldw	r2,116(sp)
+ 8003b7c:	01020134 	movhi	r4,2052
+ 8003b80:	211d2704 	addi	r4,r4,29852
+ 8003b84:	10800044 	addi	r2,r2,1
+ 8003b88:	18c00044 	addi	r3,r3,1
+ 8003b8c:	41000015 	stw	r4,0(r8)
+ 8003b90:	01000044 	movi	r4,1
+ 8003b94:	d8801d15 	stw	r2,116(sp)
+ 8003b98:	41000115 	stw	r4,4(r8)
+ 8003b9c:	d8c01e15 	stw	r3,120(sp)
+ 8003ba0:	10800208 	cmpgei	r2,r2,8
+ 8003ba4:	1003331e 	bne	r2,zero,8004874 <___vfprintf_internal_r+0x1a30>
+ 8003ba8:	42000204 	addi	r8,r8,8
+ 8003bac:	d8801617 	ldw	r2,88(sp)
+ 8003bb0:	d8c00817 	ldw	r3,32(sp)
+ 8003bb4:	10c00416 	blt	r2,r3,8003bc8 <___vfprintf_internal_r+0xd84>
+ 8003bb8:	9080004c 	andi	r2,r18,1
+ 8003bbc:	1000021e 	bne	r2,zero,8003bc8 <___vfprintf_internal_r+0xd84>
+ 8003bc0:	d8c01e17 	ldw	r3,120(sp)
+ 8003bc4:	003e6e06 	br	8003580 <___vfprintf_internal_r+0x73c>
+ 8003bc8:	d8800d17 	ldw	r2,52(sp)
+ 8003bcc:	d8c01e17 	ldw	r3,120(sp)
+ 8003bd0:	d9000b17 	ldw	r4,44(sp)
+ 8003bd4:	40800015 	stw	r2,0(r8)
+ 8003bd8:	d8801d17 	ldw	r2,116(sp)
+ 8003bdc:	20c7883a 	add	r3,r4,r3
+ 8003be0:	41000115 	stw	r4,4(r8)
+ 8003be4:	10800044 	addi	r2,r2,1
+ 8003be8:	d8801d15 	stw	r2,116(sp)
+ 8003bec:	d8c01e15 	stw	r3,120(sp)
+ 8003bf0:	10800208 	cmpgei	r2,r2,8
+ 8003bf4:	1002b11e 	bne	r2,zero,80046bc <___vfprintf_internal_r+0x1878>
+ 8003bf8:	42000204 	addi	r8,r8,8
+ 8003bfc:	d8800817 	ldw	r2,32(sp)
+ 8003c00:	143fffc4 	addi	r16,r2,-1
+ 8003c04:	043e5e0e 	bge	zero,r16,8003580 <___vfprintf_internal_r+0x73c>
+ 8003c08:	03020134 	movhi	r12,2052
+ 8003c0c:	81000450 	cmplti	r4,r16,17
+ 8003c10:	631d2784 	addi	r12,r12,29854
+ 8003c14:	d8801d17 	ldw	r2,116(sp)
+ 8003c18:	2003731e 	bne	r4,zero,80049e8 <___vfprintf_internal_r+0x1ba4>
+ 8003c1c:	dc400715 	stw	r17,28(sp)
+ 8003c20:	05000404 	movi	r20,16
+ 8003c24:	df000517 	ldw	fp,20(sp)
+ 8003c28:	6023883a 	mov	r17,r12
+ 8003c2c:	00000406 	br	8003c40 <___vfprintf_internal_r+0xdfc>
+ 8003c30:	42000204 	addi	r8,r8,8
+ 8003c34:	843ffc04 	addi	r16,r16,-16
+ 8003c38:	81000448 	cmpgei	r4,r16,17
+ 8003c3c:	20036826 	beq	r4,zero,80049e0 <___vfprintf_internal_r+0x1b9c>
+ 8003c40:	10800044 	addi	r2,r2,1
+ 8003c44:	18c00404 	addi	r3,r3,16
+ 8003c48:	44400015 	stw	r17,0(r8)
+ 8003c4c:	45000115 	stw	r20,4(r8)
+ 8003c50:	d8c01e15 	stw	r3,120(sp)
+ 8003c54:	d8801d15 	stw	r2,116(sp)
+ 8003c58:	11000208 	cmpgei	r4,r2,8
+ 8003c5c:	203ff426 	beq	r4,zero,8003c30 <___vfprintf_internal_r+0xdec>
+ 8003c60:	d9801c04 	addi	r6,sp,112
+ 8003c64:	980b883a 	mov	r5,r19
+ 8003c68:	e009883a 	mov	r4,fp
+ 8003c6c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003c70:	103d531e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8003c74:	d8c01e17 	ldw	r3,120(sp)
+ 8003c78:	d8801d17 	ldw	r2,116(sp)
+ 8003c7c:	b811883a 	mov	r8,r23
+ 8003c80:	003fec06 	br	8003c34 <___vfprintf_internal_r+0xdf0>
+ 8003c84:	8d4fc83a 	sub	r7,r17,r21
+ 8003c88:	01fe2f0e 	bge	zero,r7,8003548 <___vfprintf_internal_r+0x704>
+ 8003c8c:	03020134 	movhi	r12,2052
+ 8003c90:	39000450 	cmplti	r4,r7,17
+ 8003c94:	631d2784 	addi	r12,r12,29854
+ 8003c98:	d8801d17 	ldw	r2,116(sp)
+ 8003c9c:	2000271e 	bne	r4,zero,8003d3c <___vfprintf_internal_r+0xef8>
+ 8003ca0:	dc000e15 	stw	r16,56(sp)
+ 8003ca4:	dc800f15 	stw	r18,60(sp)
+ 8003ca8:	dc401015 	stw	r17,64(sp)
+ 8003cac:	03400404 	movi	r13,16
+ 8003cb0:	3821883a 	mov	r16,r7
+ 8003cb4:	dac01215 	stw	r11,72(sp)
+ 8003cb8:	dc400517 	ldw	r17,20(sp)
+ 8003cbc:	6025883a 	mov	r18,r12
+ 8003cc0:	00000406 	br	8003cd4 <___vfprintf_internal_r+0xe90>
+ 8003cc4:	843ffc04 	addi	r16,r16,-16
+ 8003cc8:	81000448 	cmpgei	r4,r16,17
+ 8003ccc:	42000204 	addi	r8,r8,8
+ 8003cd0:	20001426 	beq	r4,zero,8003d24 <___vfprintf_internal_r+0xee0>
+ 8003cd4:	10800044 	addi	r2,r2,1
+ 8003cd8:	18c00404 	addi	r3,r3,16
+ 8003cdc:	44800015 	stw	r18,0(r8)
+ 8003ce0:	43400115 	stw	r13,4(r8)
+ 8003ce4:	d8c01e15 	stw	r3,120(sp)
+ 8003ce8:	d8801d15 	stw	r2,116(sp)
+ 8003cec:	11000208 	cmpgei	r4,r2,8
+ 8003cf0:	203ff426 	beq	r4,zero,8003cc4 <___vfprintf_internal_r+0xe80>
+ 8003cf4:	d9801c04 	addi	r6,sp,112
+ 8003cf8:	980b883a 	mov	r5,r19
+ 8003cfc:	8809883a 	mov	r4,r17
+ 8003d00:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003d04:	103d2e1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8003d08:	843ffc04 	addi	r16,r16,-16
+ 8003d0c:	81000448 	cmpgei	r4,r16,17
+ 8003d10:	d8c01e17 	ldw	r3,120(sp)
+ 8003d14:	d8801d17 	ldw	r2,116(sp)
+ 8003d18:	b811883a 	mov	r8,r23
+ 8003d1c:	03400404 	movi	r13,16
+ 8003d20:	203fec1e 	bne	r4,zero,8003cd4 <___vfprintf_internal_r+0xe90>
+ 8003d24:	800f883a 	mov	r7,r16
+ 8003d28:	9019883a 	mov	r12,r18
+ 8003d2c:	dc000e17 	ldw	r16,56(sp)
+ 8003d30:	dc401017 	ldw	r17,64(sp)
+ 8003d34:	dac01217 	ldw	r11,72(sp)
+ 8003d38:	dc800f17 	ldw	r18,60(sp)
+ 8003d3c:	10800044 	addi	r2,r2,1
+ 8003d40:	19c7883a 	add	r3,r3,r7
+ 8003d44:	d8801d15 	stw	r2,116(sp)
+ 8003d48:	43000015 	stw	r12,0(r8)
+ 8003d4c:	41c00115 	stw	r7,4(r8)
+ 8003d50:	d8c01e15 	stw	r3,120(sp)
+ 8003d54:	10800208 	cmpgei	r2,r2,8
+ 8003d58:	1002cd1e 	bne	r2,zero,8004890 <___vfprintf_internal_r+0x1a4c>
+ 8003d5c:	5d0fc83a 	sub	r7,r11,r20
+ 8003d60:	42000204 	addi	r8,r8,8
+ 8003d64:	01fdfa0e 	bge	zero,r7,8003550 <___vfprintf_internal_r+0x70c>
+ 8003d68:	03020134 	movhi	r12,2052
+ 8003d6c:	39000450 	cmplti	r4,r7,17
+ 8003d70:	631d2784 	addi	r12,r12,29854
+ 8003d74:	d8801d17 	ldw	r2,116(sp)
+ 8003d78:	2000251e 	bne	r4,zero,8003e10 <___vfprintf_internal_r+0xfcc>
+ 8003d7c:	dc000e15 	stw	r16,56(sp)
+ 8003d80:	dc800f15 	stw	r18,60(sp)
+ 8003d84:	dc401015 	stw	r17,64(sp)
+ 8003d88:	02c00404 	movi	r11,16
+ 8003d8c:	3821883a 	mov	r16,r7
+ 8003d90:	dc400517 	ldw	r17,20(sp)
+ 8003d94:	6025883a 	mov	r18,r12
+ 8003d98:	00000406 	br	8003dac <___vfprintf_internal_r+0xf68>
+ 8003d9c:	843ffc04 	addi	r16,r16,-16
+ 8003da0:	81000448 	cmpgei	r4,r16,17
+ 8003da4:	42000204 	addi	r8,r8,8
+ 8003da8:	20001426 	beq	r4,zero,8003dfc <___vfprintf_internal_r+0xfb8>
+ 8003dac:	10800044 	addi	r2,r2,1
+ 8003db0:	18c00404 	addi	r3,r3,16
+ 8003db4:	44800015 	stw	r18,0(r8)
+ 8003db8:	42c00115 	stw	r11,4(r8)
+ 8003dbc:	d8c01e15 	stw	r3,120(sp)
+ 8003dc0:	d8801d15 	stw	r2,116(sp)
+ 8003dc4:	11000208 	cmpgei	r4,r2,8
+ 8003dc8:	203ff426 	beq	r4,zero,8003d9c <___vfprintf_internal_r+0xf58>
+ 8003dcc:	d9801c04 	addi	r6,sp,112
+ 8003dd0:	980b883a 	mov	r5,r19
+ 8003dd4:	8809883a 	mov	r4,r17
+ 8003dd8:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003ddc:	103cf81e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8003de0:	843ffc04 	addi	r16,r16,-16
+ 8003de4:	81000448 	cmpgei	r4,r16,17
+ 8003de8:	d8c01e17 	ldw	r3,120(sp)
+ 8003dec:	d8801d17 	ldw	r2,116(sp)
+ 8003df0:	b811883a 	mov	r8,r23
+ 8003df4:	02c00404 	movi	r11,16
+ 8003df8:	203fec1e 	bne	r4,zero,8003dac <___vfprintf_internal_r+0xf68>
+ 8003dfc:	800f883a 	mov	r7,r16
+ 8003e00:	9019883a 	mov	r12,r18
+ 8003e04:	dc401017 	ldw	r17,64(sp)
+ 8003e08:	dc000e17 	ldw	r16,56(sp)
+ 8003e0c:	dc800f17 	ldw	r18,60(sp)
+ 8003e10:	10800044 	addi	r2,r2,1
+ 8003e14:	19c7883a 	add	r3,r3,r7
+ 8003e18:	d8801d15 	stw	r2,116(sp)
+ 8003e1c:	43000015 	stw	r12,0(r8)
+ 8003e20:	41c00115 	stw	r7,4(r8)
+ 8003e24:	d8c01e15 	stw	r3,120(sp)
+ 8003e28:	10800208 	cmpgei	r2,r2,8
+ 8003e2c:	1001621e 	bne	r2,zero,80043b8 <___vfprintf_internal_r+0x1574>
+ 8003e30:	42000204 	addi	r8,r8,8
+ 8003e34:	003dc606 	br	8003550 <___vfprintf_internal_r+0x70c>
+ 8003e38:	d9000517 	ldw	r4,20(sp)
+ 8003e3c:	d9801c04 	addi	r6,sp,112
+ 8003e40:	980b883a 	mov	r5,r19
+ 8003e44:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003e48:	103dd726 	beq	r2,zero,80035a8 <___vfprintf_internal_r+0x764>
+ 8003e4c:	003cdc06 	br	80031c0 <___vfprintf_internal_r+0x37c>
+ 8003e50:	d9000517 	ldw	r4,20(sp)
+ 8003e54:	d9801c04 	addi	r6,sp,112
+ 8003e58:	980b883a 	mov	r5,r19
+ 8003e5c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003e60:	103cd71e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8003e64:	d9001617 	ldw	r4,88(sp)
+ 8003e68:	d8c01e17 	ldw	r3,120(sp)
+ 8003e6c:	b811883a 	mov	r8,r23
+ 8003e70:	2002951e 	bne	r4,zero,80048c8 <___vfprintf_internal_r+0x1a84>
+ 8003e74:	d9000817 	ldw	r4,32(sp)
+ 8003e78:	9080004c 	andi	r2,r18,1
+ 8003e7c:	1104b03a 	or	r2,r2,r4
+ 8003e80:	103dbf26 	beq	r2,zero,8003580 <___vfprintf_internal_r+0x73c>
+ 8003e84:	d8800d17 	ldw	r2,52(sp)
+ 8003e88:	d9000b17 	ldw	r4,44(sp)
+ 8003e8c:	40800015 	stw	r2,0(r8)
+ 8003e90:	d8801d17 	ldw	r2,116(sp)
+ 8003e94:	20c7883a 	add	r3,r4,r3
+ 8003e98:	41000115 	stw	r4,4(r8)
+ 8003e9c:	10800044 	addi	r2,r2,1
+ 8003ea0:	d8c01e15 	stw	r3,120(sp)
+ 8003ea4:	d8801d15 	stw	r2,116(sp)
+ 8003ea8:	11000208 	cmpgei	r4,r2,8
+ 8003eac:	2003641e 	bne	r4,zero,8004c40 <___vfprintf_internal_r+0x1dfc>
+ 8003eb0:	42000204 	addi	r8,r8,8
+ 8003eb4:	d9000817 	ldw	r4,32(sp)
+ 8003eb8:	10800044 	addi	r2,r2,1
+ 8003ebc:	d8801d15 	stw	r2,116(sp)
+ 8003ec0:	20c7883a 	add	r3,r4,r3
+ 8003ec4:	44000015 	stw	r16,0(r8)
+ 8003ec8:	41000115 	stw	r4,4(r8)
+ 8003ecc:	d8c01e15 	stw	r3,120(sp)
+ 8003ed0:	10800208 	cmpgei	r2,r2,8
+ 8003ed4:	103da926 	beq	r2,zero,800357c <___vfprintf_internal_r+0x738>
+ 8003ed8:	d9000517 	ldw	r4,20(sp)
+ 8003edc:	d9801c04 	addi	r6,sp,112
+ 8003ee0:	980b883a 	mov	r5,r19
+ 8003ee4:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8003ee8:	103cb51e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8003eec:	d8c01e17 	ldw	r3,120(sp)
+ 8003ef0:	b811883a 	mov	r8,r23
+ 8003ef4:	003da206 	br	8003580 <___vfprintf_internal_r+0x73c>
+ 8003ef8:	d8800817 	ldw	r2,32(sp)
+ 8003efc:	df001d17 	ldw	fp,116(sp)
+ 8003f00:	18c00044 	addi	r3,r3,1
+ 8003f04:	10800088 	cmpgei	r2,r2,2
+ 8003f08:	e5000044 	addi	r20,fp,1
+ 8003f0c:	42800204 	addi	r10,r8,8
+ 8003f10:	1000fb26 	beq	r2,zero,8004300 <___vfprintf_internal_r+0x14bc>
+ 8003f14:	00800044 	movi	r2,1
+ 8003f18:	40800115 	stw	r2,4(r8)
+ 8003f1c:	44000015 	stw	r16,0(r8)
+ 8003f20:	d8c01e15 	stw	r3,120(sp)
+ 8003f24:	dd001d15 	stw	r20,116(sp)
+ 8003f28:	a0800210 	cmplti	r2,r20,8
+ 8003f2c:	10022c26 	beq	r2,zero,80047e0 <___vfprintf_internal_r+0x199c>
+ 8003f30:	d8800b17 	ldw	r2,44(sp)
+ 8003f34:	d9000d17 	ldw	r4,52(sp)
+ 8003f38:	a5000044 	addi	r20,r20,1
+ 8003f3c:	1887883a 	add	r3,r3,r2
+ 8003f40:	50800115 	stw	r2,4(r10)
+ 8003f44:	51000015 	stw	r4,0(r10)
+ 8003f48:	d8c01e15 	stw	r3,120(sp)
+ 8003f4c:	dd001d15 	stw	r20,116(sp)
+ 8003f50:	a0800208 	cmpgei	r2,r20,8
+ 8003f54:	1002191e 	bne	r2,zero,80047bc <___vfprintf_internal_r+0x1978>
+ 8003f58:	52800204 	addi	r10,r10,8
+ 8003f5c:	d8800817 	ldw	r2,32(sp)
+ 8003f60:	d9000917 	ldw	r4,36(sp)
+ 8003f64:	d9400a17 	ldw	r5,40(sp)
+ 8003f68:	52000204 	addi	r8,r10,8
+ 8003f6c:	12ffffc4 	addi	r11,r2,-1
+ 8003f70:	a7000044 	addi	fp,r20,1
+ 8003f74:	000d883a 	mov	r6,zero
+ 8003f78:	000f883a 	mov	r7,zero
+ 8003f7c:	d8c01215 	stw	r3,72(sp)
+ 8003f80:	da800f15 	stw	r10,60(sp)
+ 8003f84:	da000e15 	stw	r8,56(sp)
+ 8003f88:	dac00715 	stw	r11,28(sp)
+ 8003f8c:	df001015 	stw	fp,64(sp)
+ 8003f90:	800e3000 	call	800e300 <__eqdf2>
+ 8003f94:	dac00717 	ldw	r11,28(sp)
+ 8003f98:	da000e17 	ldw	r8,56(sp)
+ 8003f9c:	da800f17 	ldw	r10,60(sp)
+ 8003fa0:	db401017 	ldw	r13,64(sp)
+ 8003fa4:	d8c01217 	ldw	r3,72(sp)
+ 8003fa8:	1000e126 	beq	r2,zero,8004330 <___vfprintf_internal_r+0x14ec>
+ 8003fac:	84000044 	addi	r16,r16,1
+ 8003fb0:	1ac7883a 	add	r3,r3,r11
+ 8003fb4:	df001d15 	stw	fp,116(sp)
+ 8003fb8:	54000015 	stw	r16,0(r10)
+ 8003fbc:	52c00115 	stw	r11,4(r10)
+ 8003fc0:	d8c01e15 	stw	r3,120(sp)
+ 8003fc4:	e7000208 	cmpgei	fp,fp,8
+ 8003fc8:	e001aa1e 	bne	fp,zero,8004674 <___vfprintf_internal_r+0x1830>
+ 8003fcc:	50800404 	addi	r2,r10,16
+ 8003fd0:	a7000084 	addi	fp,r20,2
+ 8003fd4:	4015883a 	mov	r10,r8
+ 8003fd8:	1011883a 	mov	r8,r2
+ 8003fdc:	d9001117 	ldw	r4,68(sp)
+ 8003fe0:	d8801844 	addi	r2,sp,97
+ 8003fe4:	df001d15 	stw	fp,116(sp)
+ 8003fe8:	20c7883a 	add	r3,r4,r3
+ 8003fec:	50800015 	stw	r2,0(r10)
+ 8003ff0:	51000115 	stw	r4,4(r10)
+ 8003ff4:	d8c01e15 	stw	r3,120(sp)
+ 8003ff8:	e7000210 	cmplti	fp,fp,8
+ 8003ffc:	e03d601e 	bne	fp,zero,8003580 <___vfprintf_internal_r+0x73c>
+ 8004000:	003fb506 	br	8003ed8 <___vfprintf_internal_r+0x1094>
+ 8004004:	9019883a 	mov	r12,r18
+ 8004008:	003e1906 	br	8003870 <___vfprintf_internal_r+0xa2c>
+ 800400c:	03020134 	movhi	r12,2052
+ 8004010:	39000450 	cmplti	r4,r7,17
+ 8004014:	631d2b84 	addi	r12,r12,29870
+ 8004018:	d8801d17 	ldw	r2,116(sp)
+ 800401c:	20002b1e 	bne	r4,zero,80040cc <___vfprintf_internal_r+0x1288>
+ 8004020:	dc001015 	stw	r16,64(sp)
+ 8004024:	dc801215 	stw	r18,72(sp)
+ 8004028:	dc401315 	stw	r17,76(sp)
+ 800402c:	03c00404 	movi	r15,16
+ 8004030:	db800e15 	stw	r14,56(sp)
+ 8004034:	db400f15 	stw	r13,60(sp)
+ 8004038:	dac01415 	stw	r11,80(sp)
+ 800403c:	3821883a 	mov	r16,r7
+ 8004040:	dc400517 	ldw	r17,20(sp)
+ 8004044:	6025883a 	mov	r18,r12
+ 8004048:	00000406 	br	800405c <___vfprintf_internal_r+0x1218>
+ 800404c:	843ffc04 	addi	r16,r16,-16
+ 8004050:	81000448 	cmpgei	r4,r16,17
+ 8004054:	42000204 	addi	r8,r8,8
+ 8004058:	20001426 	beq	r4,zero,80040ac <___vfprintf_internal_r+0x1268>
+ 800405c:	10800044 	addi	r2,r2,1
+ 8004060:	18c00404 	addi	r3,r3,16
+ 8004064:	44800015 	stw	r18,0(r8)
+ 8004068:	43c00115 	stw	r15,4(r8)
+ 800406c:	d8c01e15 	stw	r3,120(sp)
+ 8004070:	d8801d15 	stw	r2,116(sp)
+ 8004074:	11000208 	cmpgei	r4,r2,8
+ 8004078:	203ff426 	beq	r4,zero,800404c <___vfprintf_internal_r+0x1208>
+ 800407c:	d9801c04 	addi	r6,sp,112
+ 8004080:	980b883a 	mov	r5,r19
+ 8004084:	8809883a 	mov	r4,r17
+ 8004088:	800a3f80 	call	800a3f8 <__sprint_r>
+ 800408c:	103c4c1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004090:	843ffc04 	addi	r16,r16,-16
+ 8004094:	81000448 	cmpgei	r4,r16,17
+ 8004098:	d8c01e17 	ldw	r3,120(sp)
+ 800409c:	d8801d17 	ldw	r2,116(sp)
+ 80040a0:	b811883a 	mov	r8,r23
+ 80040a4:	03c00404 	movi	r15,16
+ 80040a8:	203fec1e 	bne	r4,zero,800405c <___vfprintf_internal_r+0x1218>
+ 80040ac:	800f883a 	mov	r7,r16
+ 80040b0:	9019883a 	mov	r12,r18
+ 80040b4:	db800e17 	ldw	r14,56(sp)
+ 80040b8:	db400f17 	ldw	r13,60(sp)
+ 80040bc:	dc401317 	ldw	r17,76(sp)
+ 80040c0:	dac01417 	ldw	r11,80(sp)
+ 80040c4:	dc001017 	ldw	r16,64(sp)
+ 80040c8:	dc801217 	ldw	r18,72(sp)
+ 80040cc:	10800044 	addi	r2,r2,1
+ 80040d0:	19c7883a 	add	r3,r3,r7
+ 80040d4:	d8801d15 	stw	r2,116(sp)
+ 80040d8:	43000015 	stw	r12,0(r8)
+ 80040dc:	41c00115 	stw	r7,4(r8)
+ 80040e0:	d8c01e15 	stw	r3,120(sp)
+ 80040e4:	10800208 	cmpgei	r2,r2,8
+ 80040e8:	1001d41e 	bne	r2,zero,800483c <___vfprintf_internal_r+0x19f8>
+ 80040ec:	42000204 	addi	r8,r8,8
+ 80040f0:	003cf806 	br	80034d4 <___vfprintf_internal_r+0x690>
+ 80040f4:	d9000517 	ldw	r4,20(sp)
+ 80040f8:	d9801c04 	addi	r6,sp,112
+ 80040fc:	980b883a 	mov	r5,r19
+ 8004100:	dac01015 	stw	r11,64(sp)
+ 8004104:	db400f15 	stw	r13,60(sp)
+ 8004108:	db800e15 	stw	r14,56(sp)
+ 800410c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004110:	103c2b1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004114:	d8c01e17 	ldw	r3,120(sp)
+ 8004118:	b811883a 	mov	r8,r23
+ 800411c:	dac01017 	ldw	r11,64(sp)
+ 8004120:	db400f17 	ldw	r13,60(sp)
+ 8004124:	db800e17 	ldw	r14,56(sp)
+ 8004128:	003cf806 	br	800350c <___vfprintf_internal_r+0x6c8>
+ 800412c:	d9000517 	ldw	r4,20(sp)
+ 8004130:	d9801c04 	addi	r6,sp,112
+ 8004134:	980b883a 	mov	r5,r19
+ 8004138:	dac00f15 	stw	r11,60(sp)
+ 800413c:	db400e15 	stw	r13,56(sp)
+ 8004140:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004144:	103c1e1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004148:	d8c01e17 	ldw	r3,120(sp)
+ 800414c:	b811883a 	mov	r8,r23
+ 8004150:	dac00f17 	ldw	r11,60(sp)
+ 8004154:	db400e17 	ldw	r13,56(sp)
+ 8004158:	003cf906 	br	8003540 <___vfprintf_internal_r+0x6fc>
+ 800415c:	d9000c17 	ldw	r4,48(sp)
+ 8004160:	b821883a 	mov	r16,r23
+ 8004164:	a88003cc 	andi	r2,r21,15
+ 8004168:	a006973a 	slli	r3,r20,28
+ 800416c:	2085883a 	add	r2,r4,r2
+ 8004170:	a82ad13a 	srli	r21,r21,4
+ 8004174:	10800003 	ldbu	r2,0(r2)
+ 8004178:	a028d13a 	srli	r20,r20,4
+ 800417c:	843fffc4 	addi	r16,r16,-1
+ 8004180:	1d6ab03a 	or	r21,r3,r21
+ 8004184:	80800005 	stb	r2,0(r16)
+ 8004188:	ad04b03a 	or	r2,r21,r20
+ 800418c:	103ff51e 	bne	r2,zero,8004164 <___vfprintf_internal_r+0x1320>
+ 8004190:	bc29c83a 	sub	r20,r23,r16
+ 8004194:	6025883a 	mov	r18,r12
+ 8004198:	003e3d06 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 800419c:	d9001617 	ldw	r4,88(sp)
+ 80041a0:	0101980e 	bge	zero,r4,8004804 <___vfprintf_internal_r+0x19c0>
+ 80041a4:	d8800717 	ldw	r2,28(sp)
+ 80041a8:	d9000817 	ldw	r4,32(sp)
+ 80041ac:	1039883a 	mov	fp,r2
+ 80041b0:	20812516 	blt	r4,r2,8004648 <___vfprintf_internal_r+0x1804>
+ 80041b4:	07000a0e 	bge	zero,fp,80041e0 <___vfprintf_internal_r+0x139c>
+ 80041b8:	d8801d17 	ldw	r2,116(sp)
+ 80041bc:	1f07883a 	add	r3,r3,fp
+ 80041c0:	44000015 	stw	r16,0(r8)
+ 80041c4:	10800044 	addi	r2,r2,1
+ 80041c8:	d8801d15 	stw	r2,116(sp)
+ 80041cc:	47000115 	stw	fp,4(r8)
+ 80041d0:	d8c01e15 	stw	r3,120(sp)
+ 80041d4:	10800208 	cmpgei	r2,r2,8
+ 80041d8:	1002d91e 	bne	r2,zero,8004d40 <___vfprintf_internal_r+0x1efc>
+ 80041dc:	42000204 	addi	r8,r8,8
+ 80041e0:	e0013e16 	blt	fp,zero,80046dc <___vfprintf_internal_r+0x1898>
+ 80041e4:	d8800717 	ldw	r2,28(sp)
+ 80041e8:	1739c83a 	sub	fp,r2,fp
+ 80041ec:	07014516 	blt	zero,fp,8004704 <___vfprintf_internal_r+0x18c0>
+ 80041f0:	d9001617 	ldw	r4,88(sp)
+ 80041f4:	d8800817 	ldw	r2,32(sp)
+ 80041f8:	2081160e 	bge	r4,r2,8004654 <___vfprintf_internal_r+0x1810>
+ 80041fc:	d8800d17 	ldw	r2,52(sp)
+ 8004200:	d9400b17 	ldw	r5,44(sp)
+ 8004204:	40800015 	stw	r2,0(r8)
+ 8004208:	d8801d17 	ldw	r2,116(sp)
+ 800420c:	1947883a 	add	r3,r3,r5
+ 8004210:	41400115 	stw	r5,4(r8)
+ 8004214:	10800044 	addi	r2,r2,1
+ 8004218:	d8801d15 	stw	r2,116(sp)
+ 800421c:	d8c01e15 	stw	r3,120(sp)
+ 8004220:	10800208 	cmpgei	r2,r2,8
+ 8004224:	1002601e 	bne	r2,zero,8004ba8 <___vfprintf_internal_r+0x1d64>
+ 8004228:	42000204 	addi	r8,r8,8
+ 800422c:	d8800817 	ldw	r2,32(sp)
+ 8004230:	d9400717 	ldw	r5,28(sp)
+ 8004234:	1105c83a 	sub	r2,r2,r4
+ 8004238:	29015c0e 	bge	r5,r4,80047ac <___vfprintf_internal_r+0x1968>
+ 800423c:	1039883a 	mov	fp,r2
+ 8004240:	07000c0e 	bge	zero,fp,8004274 <___vfprintf_internal_r+0x1430>
+ 8004244:	d9000717 	ldw	r4,28(sp)
+ 8004248:	1f07883a 	add	r3,r3,fp
+ 800424c:	47000115 	stw	fp,4(r8)
+ 8004250:	8121883a 	add	r16,r16,r4
+ 8004254:	d9001d17 	ldw	r4,116(sp)
+ 8004258:	44000015 	stw	r16,0(r8)
+ 800425c:	d8c01e15 	stw	r3,120(sp)
+ 8004260:	21000044 	addi	r4,r4,1
+ 8004264:	d9001d15 	stw	r4,116(sp)
+ 8004268:	21000208 	cmpgei	r4,r4,8
+ 800426c:	2002bf1e 	bne	r4,zero,8004d6c <___vfprintf_internal_r+0x1f28>
+ 8004270:	42000204 	addi	r8,r8,8
+ 8004274:	e000010e 	bge	fp,zero,800427c <___vfprintf_internal_r+0x1438>
+ 8004278:	0039883a 	mov	fp,zero
+ 800427c:	1739c83a 	sub	fp,r2,fp
+ 8004280:	073cbf0e 	bge	zero,fp,8003580 <___vfprintf_internal_r+0x73c>
+ 8004284:	03020134 	movhi	r12,2052
+ 8004288:	e1000450 	cmplti	r4,fp,17
+ 800428c:	631d2784 	addi	r12,r12,29854
+ 8004290:	d8801d17 	ldw	r2,116(sp)
+ 8004294:	20023b1e 	bne	r4,zero,8004b84 <___vfprintf_internal_r+0x1d40>
+ 8004298:	dc400715 	stw	r17,28(sp)
+ 800429c:	05000404 	movi	r20,16
+ 80042a0:	dc000517 	ldw	r16,20(sp)
+ 80042a4:	6023883a 	mov	r17,r12
+ 80042a8:	00000406 	br	80042bc <___vfprintf_internal_r+0x1478>
+ 80042ac:	42000204 	addi	r8,r8,8
+ 80042b0:	e73ffc04 	addi	fp,fp,-16
+ 80042b4:	e1000448 	cmpgei	r4,fp,17
+ 80042b8:	20023026 	beq	r4,zero,8004b7c <___vfprintf_internal_r+0x1d38>
+ 80042bc:	10800044 	addi	r2,r2,1
+ 80042c0:	18c00404 	addi	r3,r3,16
+ 80042c4:	44400015 	stw	r17,0(r8)
+ 80042c8:	45000115 	stw	r20,4(r8)
+ 80042cc:	d8c01e15 	stw	r3,120(sp)
+ 80042d0:	d8801d15 	stw	r2,116(sp)
+ 80042d4:	11000208 	cmpgei	r4,r2,8
+ 80042d8:	203ff426 	beq	r4,zero,80042ac <___vfprintf_internal_r+0x1468>
+ 80042dc:	d9801c04 	addi	r6,sp,112
+ 80042e0:	980b883a 	mov	r5,r19
+ 80042e4:	8009883a 	mov	r4,r16
+ 80042e8:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80042ec:	103bb41e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80042f0:	d8c01e17 	ldw	r3,120(sp)
+ 80042f4:	d8801d17 	ldw	r2,116(sp)
+ 80042f8:	b811883a 	mov	r8,r23
+ 80042fc:	003fec06 	br	80042b0 <___vfprintf_internal_r+0x146c>
+ 8004300:	9080004c 	andi	r2,r18,1
+ 8004304:	103f031e 	bne	r2,zero,8003f14 <___vfprintf_internal_r+0x10d0>
+ 8004308:	00800044 	movi	r2,1
+ 800430c:	dd001d15 	stw	r20,116(sp)
+ 8004310:	44000015 	stw	r16,0(r8)
+ 8004314:	40800115 	stw	r2,4(r8)
+ 8004318:	d8c01e15 	stw	r3,120(sp)
+ 800431c:	a5000208 	cmpgei	r20,r20,8
+ 8004320:	a000d41e 	bne	r20,zero,8004674 <___vfprintf_internal_r+0x1830>
+ 8004324:	e7000084 	addi	fp,fp,2
+ 8004328:	42000404 	addi	r8,r8,16
+ 800432c:	003f2b06 	br	8003fdc <___vfprintf_internal_r+0x1198>
+ 8004330:	02ff2a0e 	bge	zero,r11,8003fdc <___vfprintf_internal_r+0x1198>
+ 8004334:	58800450 	cmplti	r2,r11,17
+ 8004338:	03020134 	movhi	r12,2052
+ 800433c:	1002f81e 	bne	r2,zero,8004f20 <___vfprintf_internal_r+0x20dc>
+ 8004340:	631d2784 	addi	r12,r12,29854
+ 8004344:	dc800715 	stw	r18,28(sp)
+ 8004348:	dc400e15 	stw	r17,56(sp)
+ 800434c:	04000404 	movi	r16,16
+ 8004350:	5823883a 	mov	r17,r11
+ 8004354:	df000517 	ldw	fp,20(sp)
+ 8004358:	6025883a 	mov	r18,r12
+ 800435c:	6829883a 	mov	r20,r13
+ 8004360:	00000506 	br	8004378 <___vfprintf_internal_r+0x1534>
+ 8004364:	52800204 	addi	r10,r10,8
+ 8004368:	8c7ffc04 	addi	r17,r17,-16
+ 800436c:	88800448 	cmpgei	r2,r17,17
+ 8004370:	10018a26 	beq	r2,zero,800499c <___vfprintf_internal_r+0x1b58>
+ 8004374:	a5000044 	addi	r20,r20,1
+ 8004378:	18c00404 	addi	r3,r3,16
+ 800437c:	54800015 	stw	r18,0(r10)
+ 8004380:	54000115 	stw	r16,4(r10)
+ 8004384:	d8c01e15 	stw	r3,120(sp)
+ 8004388:	dd001d15 	stw	r20,116(sp)
+ 800438c:	a0800208 	cmpgei	r2,r20,8
+ 8004390:	103ff426 	beq	r2,zero,8004364 <___vfprintf_internal_r+0x1520>
+ 8004394:	d9801c04 	addi	r6,sp,112
+ 8004398:	980b883a 	mov	r5,r19
+ 800439c:	e009883a 	mov	r4,fp
+ 80043a0:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80043a4:	103b861e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80043a8:	dd001d17 	ldw	r20,116(sp)
+ 80043ac:	d8c01e17 	ldw	r3,120(sp)
+ 80043b0:	b815883a 	mov	r10,r23
+ 80043b4:	003fec06 	br	8004368 <___vfprintf_internal_r+0x1524>
+ 80043b8:	d9000517 	ldw	r4,20(sp)
+ 80043bc:	d9801c04 	addi	r6,sp,112
+ 80043c0:	980b883a 	mov	r5,r19
+ 80043c4:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80043c8:	103b7d1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80043cc:	d8c01e17 	ldw	r3,120(sp)
+ 80043d0:	b811883a 	mov	r8,r23
+ 80043d4:	003c5e06 	br	8003550 <___vfprintf_internal_r+0x70c>
+ 80043d8:	0029883a 	mov	r20,zero
+ 80043dc:	003bdf06 	br	800335c <___vfprintf_internal_r+0x518>
+ 80043e0:	b025883a 	mov	r18,r22
+ 80043e4:	003aea06 	br	8002f90 <___vfprintf_internal_r+0x14c>
+ 80043e8:	b821883a 	mov	r16,r23
+ 80043ec:	003da806 	br	8003a90 <___vfprintf_internal_r+0xc4c>
+ 80043f0:	d9000917 	ldw	r4,36(sp)
+ 80043f4:	d9400a17 	ldw	r5,40(sp)
+ 80043f8:	da000f15 	stw	r8,60(sp)
+ 80043fc:	200d883a 	mov	r6,r4
+ 8004400:	280f883a 	mov	r7,r5
+ 8004404:	dac00e15 	stw	r11,56(sp)
+ 8004408:	db000715 	stw	r12,28(sp)
+ 800440c:	800f5580 	call	800f558 <__unorddf2>
+ 8004410:	db000717 	ldw	r12,28(sp)
+ 8004414:	dac00e17 	ldw	r11,56(sp)
+ 8004418:	da000f17 	ldw	r8,60(sp)
+ 800441c:	1002af1e 	bne	r2,zero,8004edc <___vfprintf_internal_r+0x2098>
+ 8004420:	00fff7c4 	movi	r3,-33
+ 8004424:	e0c6703a 	and	r3,fp,r3
+ 8004428:	58bfffe0 	cmpeqi	r2,r11,-1
+ 800442c:	d8c00715 	stw	r3,28(sp)
+ 8004430:	10024c1e 	bne	r2,zero,8004d64 <___vfprintf_internal_r+0x1f20>
+ 8004434:	188011d8 	cmpnei	r2,r3,71
+ 8004438:	1001fe26 	beq	r2,zero,8004c34 <___vfprintf_internal_r+0x1df0>
+ 800443c:	d8800a17 	ldw	r2,40(sp)
+ 8004440:	64804014 	ori	r18,r12,256
+ 8004444:	1001e116 	blt	r2,zero,8004bcc <___vfprintf_internal_r+0x1d88>
+ 8004448:	dd400a17 	ldw	r21,40(sp)
+ 800444c:	d8000e05 	stb	zero,56(sp)
+ 8004450:	e08019a0 	cmpeqi	r2,fp,102
+ 8004454:	d8800f15 	stw	r2,60(sp)
+ 8004458:	1001741e 	bne	r2,zero,8004a2c <___vfprintf_internal_r+0x1be8>
+ 800445c:	e08011a0 	cmpeqi	r2,fp,70
+ 8004460:	1001721e 	bne	r2,zero,8004a2c <___vfprintf_internal_r+0x1be8>
+ 8004464:	d8800717 	ldw	r2,28(sp)
+ 8004468:	da001215 	stw	r8,72(sp)
+ 800446c:	db001015 	stw	r12,64(sp)
+ 8004470:	10801158 	cmpnei	r2,r2,69
+ 8004474:	10020526 	beq	r2,zero,8004c8c <___vfprintf_internal_r+0x1e48>
+ 8004478:	d8801a04 	addi	r2,sp,104
+ 800447c:	d8800315 	stw	r2,12(sp)
+ 8004480:	d9400917 	ldw	r5,36(sp)
+ 8004484:	d8801704 	addi	r2,sp,92
+ 8004488:	d9000517 	ldw	r4,20(sp)
+ 800448c:	d8800215 	stw	r2,8(sp)
+ 8004490:	d8801604 	addi	r2,sp,88
+ 8004494:	dac00015 	stw	r11,0(sp)
+ 8004498:	d8800115 	stw	r2,4(sp)
+ 800449c:	01c00084 	movi	r7,2
+ 80044a0:	a80d883a 	mov	r6,r21
+ 80044a4:	dac00815 	stw	r11,32(sp)
+ 80044a8:	80053ec0 	call	80053ec <_dtoa_r>
+ 80044ac:	dac00817 	ldw	r11,32(sp)
+ 80044b0:	1021883a 	mov	r16,r2
+ 80044b4:	e08019d8 	cmpnei	r2,fp,103
+ 80044b8:	db001017 	ldw	r12,64(sp)
+ 80044bc:	da001217 	ldw	r8,72(sp)
+ 80044c0:	5829883a 	mov	r20,r11
+ 80044c4:	1002031e 	bne	r2,zero,8004cd4 <___vfprintf_internal_r+0x1e90>
+ 80044c8:	6080004c 	andi	r2,r12,1
+ 80044cc:	1002031e 	bne	r2,zero,8004cdc <___vfprintf_internal_r+0x1e98>
+ 80044d0:	d8c01617 	ldw	r3,88(sp)
+ 80044d4:	d8800717 	ldw	r2,28(sp)
+ 80044d8:	d8c00715 	stw	r3,28(sp)
+ 80044dc:	d8c01a17 	ldw	r3,104(sp)
+ 80044e0:	108011e0 	cmpeqi	r2,r2,71
+ 80044e4:	1c07c83a 	sub	r3,r3,r16
+ 80044e8:	d8c00815 	stw	r3,32(sp)
+ 80044ec:	10000526 	beq	r2,zero,8004504 <___vfprintf_internal_r+0x16c0>
+ 80044f0:	d8c00717 	ldw	r3,28(sp)
+ 80044f4:	18bfff50 	cmplti	r2,r3,-3
+ 80044f8:	1000011e 	bne	r2,zero,8004500 <___vfprintf_internal_r+0x16bc>
+ 80044fc:	58c2050e 	bge	r11,r3,8004d14 <___vfprintf_internal_r+0x1ed0>
+ 8004500:	e73fff84 	addi	fp,fp,-2
+ 8004504:	d8800717 	ldw	r2,28(sp)
+ 8004508:	df001845 	stb	fp,97(sp)
+ 800450c:	153fffc4 	addi	r20,r2,-1
+ 8004510:	dd001615 	stw	r20,88(sp)
+ 8004514:	a0027916 	blt	r20,zero,8004efc <___vfprintf_internal_r+0x20b8>
+ 8004518:	00800ac4 	movi	r2,43
+ 800451c:	d8801885 	stb	r2,98(sp)
+ 8004520:	a0800290 	cmplti	r2,r20,10
+ 8004524:	1002581e 	bne	r2,zero,8004e88 <___vfprintf_internal_r+0x2044>
+ 8004528:	dc000715 	stw	r16,28(sp)
+ 800452c:	dd401bc4 	addi	r21,sp,111
+ 8004530:	a021883a 	mov	r16,r20
+ 8004534:	db000f15 	stw	r12,60(sp)
+ 8004538:	9829883a 	mov	r20,r19
+ 800453c:	4027883a 	mov	r19,r8
+ 8004540:	00000206 	br	800454c <___vfprintf_internal_r+0x1708>
+ 8004544:	202b883a 	mov	r21,r4
+ 8004548:	1021883a 	mov	r16,r2
+ 800454c:	8009883a 	mov	r4,r16
+ 8004550:	01400284 	movi	r5,10
+ 8004554:	800cf800 	call	800cf80 <__modsi3>
+ 8004558:	10800c04 	addi	r2,r2,48
+ 800455c:	8009883a 	mov	r4,r16
+ 8004560:	a8bfffc5 	stb	r2,-1(r21)
+ 8004564:	01400284 	movi	r5,10
+ 8004568:	800cf000 	call	800cf00 <__divsi3>
+ 800456c:	80c01908 	cmpgei	r3,r16,100
+ 8004570:	a93fffc4 	addi	r4,r21,-1
+ 8004574:	183ff31e 	bne	r3,zero,8004544 <___vfprintf_internal_r+0x1700>
+ 8004578:	10800c04 	addi	r2,r2,48
+ 800457c:	20bfffc5 	stb	r2,-1(r4)
+ 8004580:	a8ffff84 	addi	r3,r21,-2
+ 8004584:	d9001bc4 	addi	r4,sp,111
+ 8004588:	9811883a 	mov	r8,r19
+ 800458c:	dc000717 	ldw	r16,28(sp)
+ 8004590:	db000f17 	ldw	r12,60(sp)
+ 8004594:	a027883a 	mov	r19,r20
+ 8004598:	1902732e 	bgeu	r3,r4,8004f68 <___vfprintf_internal_r+0x2124>
+ 800459c:	d90018c4 	addi	r4,sp,99
+ 80045a0:	00000106 	br	80045a8 <___vfprintf_internal_r+0x1764>
+ 80045a4:	18800003 	ldbu	r2,0(r3)
+ 80045a8:	21000044 	addi	r4,r4,1
+ 80045ac:	20bfffc5 	stb	r2,-1(r4)
+ 80045b0:	18c00044 	addi	r3,r3,1
+ 80045b4:	d8801bc4 	addi	r2,sp,111
+ 80045b8:	18bffa1e 	bne	r3,r2,80045a4 <___vfprintf_internal_r+0x1760>
+ 80045bc:	d8801c44 	addi	r2,sp,113
+ 80045c0:	d8c018c4 	addi	r3,sp,99
+ 80045c4:	1545c83a 	sub	r2,r2,r21
+ 80045c8:	1885883a 	add	r2,r3,r2
+ 80045cc:	d8c01844 	addi	r3,sp,97
+ 80045d0:	10c5c83a 	sub	r2,r2,r3
+ 80045d4:	d8801115 	stw	r2,68(sp)
+ 80045d8:	d8c00817 	ldw	r3,32(sp)
+ 80045dc:	d9001117 	ldw	r4,68(sp)
+ 80045e0:	18800088 	cmpgei	r2,r3,2
+ 80045e4:	1929883a 	add	r20,r3,r4
+ 80045e8:	10024926 	beq	r2,zero,8004f10 <___vfprintf_internal_r+0x20cc>
+ 80045ec:	d8800b17 	ldw	r2,44(sp)
+ 80045f0:	a0a9883a 	add	r20,r20,r2
+ 80045f4:	a02b883a 	mov	r21,r20
+ 80045f8:	a000010e 	bge	r20,zero,8004600 <___vfprintf_internal_r+0x17bc>
+ 80045fc:	002b883a 	mov	r21,zero
+ 8004600:	d8000715 	stw	zero,28(sp)
+ 8004604:	00013f06 	br	8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004608:	00800c04 	movi	r2,48
+ 800460c:	d8801585 	stb	r2,86(sp)
+ 8004610:	df0015c5 	stb	fp,87(sp)
+ 8004614:	63000094 	ori	r12,r12,2
+ 8004618:	00800084 	movi	r2,2
+ 800461c:	003ce406 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8004620:	d9400417 	ldw	r5,16(sp)
+ 8004624:	20800017 	ldw	r2,0(r4)
+ 8004628:	d8c00615 	stw	r3,24(sp)
+ 800462c:	2809d7fa 	srai	r4,r5,31
+ 8004630:	11400015 	stw	r5,0(r2)
+ 8004634:	11000115 	stw	r4,4(r2)
+ 8004638:	003a3706 	br	8002f18 <___vfprintf_internal_r+0xd4>
+ 800463c:	0463c83a 	sub	r17,zero,r17
+ 8004640:	d8800615 	stw	r2,24(sp)
+ 8004644:	003b1806 	br	80032a8 <___vfprintf_internal_r+0x464>
+ 8004648:	2039883a 	mov	fp,r4
+ 800464c:	073eda16 	blt	zero,fp,80041b8 <___vfprintf_internal_r+0x1374>
+ 8004650:	003ee306 	br	80041e0 <___vfprintf_internal_r+0x139c>
+ 8004654:	9080004c 	andi	r2,r18,1
+ 8004658:	103ee81e 	bne	r2,zero,80041fc <___vfprintf_internal_r+0x13b8>
+ 800465c:	d8800817 	ldw	r2,32(sp)
+ 8004660:	d9400717 	ldw	r5,28(sp)
+ 8004664:	1105c83a 	sub	r2,r2,r4
+ 8004668:	2900500e 	bge	r5,r4,80047ac <___vfprintf_internal_r+0x1968>
+ 800466c:	1039883a 	mov	fp,r2
+ 8004670:	003f0006 	br	8004274 <___vfprintf_internal_r+0x1430>
+ 8004674:	d9000517 	ldw	r4,20(sp)
+ 8004678:	d9801c04 	addi	r6,sp,112
+ 800467c:	980b883a 	mov	r5,r19
+ 8004680:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004684:	103ace1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004688:	df001d17 	ldw	fp,116(sp)
+ 800468c:	d8c01e17 	ldw	r3,120(sp)
+ 8004690:	da002b04 	addi	r8,sp,172
+ 8004694:	e7000044 	addi	fp,fp,1
+ 8004698:	b815883a 	mov	r10,r23
+ 800469c:	003e4f06 	br	8003fdc <___vfprintf_internal_r+0x1198>
+ 80046a0:	b7000043 	ldbu	fp,1(r22)
+ 80046a4:	63000814 	ori	r12,r12,32
+ 80046a8:	b5800044 	addi	r22,r22,1
+ 80046ac:	e2803fcc 	andi	r10,fp,255
+ 80046b0:	5280201c 	xori	r10,r10,128
+ 80046b4:	52bfe004 	addi	r10,r10,-128
+ 80046b8:	003a3d06 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+ 80046bc:	d9000517 	ldw	r4,20(sp)
+ 80046c0:	d9801c04 	addi	r6,sp,112
+ 80046c4:	980b883a 	mov	r5,r19
+ 80046c8:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80046cc:	103abc1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80046d0:	d8c01e17 	ldw	r3,120(sp)
+ 80046d4:	b811883a 	mov	r8,r23
+ 80046d8:	003d4806 	br	8003bfc <___vfprintf_internal_r+0xdb8>
+ 80046dc:	0039883a 	mov	fp,zero
+ 80046e0:	003ec006 	br	80041e4 <___vfprintf_internal_r+0x13a0>
+ 80046e4:	588001f0 	cmpltui	r2,r11,7
+ 80046e8:	5829883a 	mov	r20,r11
+ 80046ec:	10013b26 	beq	r2,zero,8004bdc <___vfprintf_internal_r+0x1d98>
+ 80046f0:	04020134 	movhi	r16,2052
+ 80046f4:	a02b883a 	mov	r21,r20
+ 80046f8:	dc800615 	stw	r18,24(sp)
+ 80046fc:	841d2504 	addi	r16,r16,29844
+ 8004700:	003b6906 	br	80034a8 <___vfprintf_internal_r+0x664>
+ 8004704:	03020134 	movhi	r12,2052
+ 8004708:	e1000450 	cmplti	r4,fp,17
+ 800470c:	631d2784 	addi	r12,r12,29854
+ 8004710:	d8801d17 	ldw	r2,116(sp)
+ 8004714:	20010b1e 	bne	r4,zero,8004b44 <___vfprintf_internal_r+0x1d00>
+ 8004718:	b009883a 	mov	r4,r22
+ 800471c:	dc000e15 	stw	r16,56(sp)
+ 8004720:	dc800f15 	stw	r18,60(sp)
+ 8004724:	882d883a 	mov	r22,r17
+ 8004728:	05000404 	movi	r20,16
+ 800472c:	e023883a 	mov	r17,fp
+ 8004730:	dc000517 	ldw	r16,20(sp)
+ 8004734:	6025883a 	mov	r18,r12
+ 8004738:	2039883a 	mov	fp,r4
+ 800473c:	00000406 	br	8004750 <___vfprintf_internal_r+0x190c>
+ 8004740:	42000204 	addi	r8,r8,8
+ 8004744:	8c7ffc04 	addi	r17,r17,-16
+ 8004748:	89000448 	cmpgei	r4,r17,17
+ 800474c:	2000f626 	beq	r4,zero,8004b28 <___vfprintf_internal_r+0x1ce4>
+ 8004750:	10800044 	addi	r2,r2,1
+ 8004754:	18c00404 	addi	r3,r3,16
+ 8004758:	44800015 	stw	r18,0(r8)
+ 800475c:	45000115 	stw	r20,4(r8)
+ 8004760:	d8c01e15 	stw	r3,120(sp)
+ 8004764:	d8801d15 	stw	r2,116(sp)
+ 8004768:	11000208 	cmpgei	r4,r2,8
+ 800476c:	203ff426 	beq	r4,zero,8004740 <___vfprintf_internal_r+0x18fc>
+ 8004770:	d9801c04 	addi	r6,sp,112
+ 8004774:	980b883a 	mov	r5,r19
+ 8004778:	8009883a 	mov	r4,r16
+ 800477c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004780:	103a8f1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004784:	d8c01e17 	ldw	r3,120(sp)
+ 8004788:	d8801d17 	ldw	r2,116(sp)
+ 800478c:	b811883a 	mov	r8,r23
+ 8004790:	003fec06 	br	8004744 <___vfprintf_internal_r+0x1900>
+ 8004794:	d8800617 	ldw	r2,24(sp)
+ 8004798:	10800017 	ldw	r2,0(r2)
+ 800479c:	d8c00615 	stw	r3,24(sp)
+ 80047a0:	d8c00417 	ldw	r3,16(sp)
+ 80047a4:	10c00015 	stw	r3,0(r2)
+ 80047a8:	0039db06 	br	8002f18 <___vfprintf_internal_r+0xd4>
+ 80047ac:	d9000817 	ldw	r4,32(sp)
+ 80047b0:	d9400717 	ldw	r5,28(sp)
+ 80047b4:	2179c83a 	sub	fp,r4,r5
+ 80047b8:	003ea106 	br	8004240 <___vfprintf_internal_r+0x13fc>
+ 80047bc:	d9000517 	ldw	r4,20(sp)
+ 80047c0:	d9801c04 	addi	r6,sp,112
+ 80047c4:	980b883a 	mov	r5,r19
+ 80047c8:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80047cc:	103a7c1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80047d0:	d8c01e17 	ldw	r3,120(sp)
+ 80047d4:	dd001d17 	ldw	r20,116(sp)
+ 80047d8:	b815883a 	mov	r10,r23
+ 80047dc:	003ddf06 	br	8003f5c <___vfprintf_internal_r+0x1118>
+ 80047e0:	d9000517 	ldw	r4,20(sp)
+ 80047e4:	d9801c04 	addi	r6,sp,112
+ 80047e8:	980b883a 	mov	r5,r19
+ 80047ec:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80047f0:	103a731e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80047f4:	d8c01e17 	ldw	r3,120(sp)
+ 80047f8:	dd001d17 	ldw	r20,116(sp)
+ 80047fc:	b815883a 	mov	r10,r23
+ 8004800:	003dcb06 	br	8003f30 <___vfprintf_internal_r+0x10ec>
+ 8004804:	d8801d17 	ldw	r2,116(sp)
+ 8004808:	01420134 	movhi	r5,2052
+ 800480c:	295d2704 	addi	r5,r5,29852
+ 8004810:	10800044 	addi	r2,r2,1
+ 8004814:	18c00044 	addi	r3,r3,1
+ 8004818:	41400015 	stw	r5,0(r8)
+ 800481c:	01400044 	movi	r5,1
+ 8004820:	d8801d15 	stw	r2,116(sp)
+ 8004824:	41400115 	stw	r5,4(r8)
+ 8004828:	d8c01e15 	stw	r3,120(sp)
+ 800482c:	10800208 	cmpgei	r2,r2,8
+ 8004830:	103d871e 	bne	r2,zero,8003e50 <___vfprintf_internal_r+0x100c>
+ 8004834:	42000204 	addi	r8,r8,8
+ 8004838:	003d8d06 	br	8003e70 <___vfprintf_internal_r+0x102c>
+ 800483c:	d9000517 	ldw	r4,20(sp)
+ 8004840:	d9801c04 	addi	r6,sp,112
+ 8004844:	980b883a 	mov	r5,r19
+ 8004848:	dac01015 	stw	r11,64(sp)
+ 800484c:	db400f15 	stw	r13,60(sp)
+ 8004850:	db800e15 	stw	r14,56(sp)
+ 8004854:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004858:	103a591e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 800485c:	d8c01e17 	ldw	r3,120(sp)
+ 8004860:	b811883a 	mov	r8,r23
+ 8004864:	dac01017 	ldw	r11,64(sp)
+ 8004868:	db400f17 	ldw	r13,60(sp)
+ 800486c:	db800e17 	ldw	r14,56(sp)
+ 8004870:	003b1806 	br	80034d4 <___vfprintf_internal_r+0x690>
+ 8004874:	d9000517 	ldw	r4,20(sp)
+ 8004878:	d9801c04 	addi	r6,sp,112
+ 800487c:	980b883a 	mov	r5,r19
+ 8004880:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004884:	103a4e1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004888:	b811883a 	mov	r8,r23
+ 800488c:	003cc706 	br	8003bac <___vfprintf_internal_r+0xd68>
+ 8004890:	d9000517 	ldw	r4,20(sp)
+ 8004894:	d9801c04 	addi	r6,sp,112
+ 8004898:	980b883a 	mov	r5,r19
+ 800489c:	dac00e15 	stw	r11,56(sp)
+ 80048a0:	800a3f80 	call	800a3f8 <__sprint_r>
+ 80048a4:	103a461e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 80048a8:	d8c01e17 	ldw	r3,120(sp)
+ 80048ac:	b811883a 	mov	r8,r23
+ 80048b0:	dac00e17 	ldw	r11,56(sp)
+ 80048b4:	003b2406 	br	8003548 <___vfprintf_internal_r+0x704>
+ 80048b8:	10c00060 	cmpeqi	r3,r2,1
+ 80048bc:	9019883a 	mov	r12,r18
+ 80048c0:	183bed26 	beq	r3,zero,8003878 <___vfprintf_internal_r+0xa34>
+ 80048c4:	003c6d06 	br	8003a7c <___vfprintf_internal_r+0xc38>
+ 80048c8:	d8800d17 	ldw	r2,52(sp)
+ 80048cc:	d9400b17 	ldw	r5,44(sp)
+ 80048d0:	40800015 	stw	r2,0(r8)
+ 80048d4:	d8801d17 	ldw	r2,116(sp)
+ 80048d8:	28c7883a 	add	r3,r5,r3
+ 80048dc:	41400115 	stw	r5,4(r8)
+ 80048e0:	10800044 	addi	r2,r2,1
+ 80048e4:	d8c01e15 	stw	r3,120(sp)
+ 80048e8:	d8801d15 	stw	r2,116(sp)
+ 80048ec:	11400208 	cmpgei	r5,r2,8
+ 80048f0:	2800d31e 	bne	r5,zero,8004c40 <___vfprintf_internal_r+0x1dfc>
+ 80048f4:	42000204 	addi	r8,r8,8
+ 80048f8:	203d6e0e 	bge	r4,zero,8003eb4 <___vfprintf_internal_r+0x1070>
+ 80048fc:	03020134 	movhi	r12,2052
+ 8004900:	217ffc08 	cmpgei	r5,r4,-16
+ 8004904:	631d2784 	addi	r12,r12,29854
+ 8004908:	0129c83a 	sub	r20,zero,r4
+ 800490c:	28014a1e 	bne	r5,zero,8004e38 <___vfprintf_internal_r+0x1ff4>
+ 8004910:	dc000715 	stw	r16,28(sp)
+ 8004914:	07000404 	movi	fp,16
+ 8004918:	a021883a 	mov	r16,r20
+ 800491c:	8829883a 	mov	r20,r17
+ 8004920:	6023883a 	mov	r17,r12
+ 8004924:	00000406 	br	8004938 <___vfprintf_internal_r+0x1af4>
+ 8004928:	42000204 	addi	r8,r8,8
+ 800492c:	843ffc04 	addi	r16,r16,-16
+ 8004930:	81000448 	cmpgei	r4,r16,17
+ 8004934:	20013c26 	beq	r4,zero,8004e28 <___vfprintf_internal_r+0x1fe4>
+ 8004938:	10800044 	addi	r2,r2,1
+ 800493c:	18c00404 	addi	r3,r3,16
+ 8004940:	44400015 	stw	r17,0(r8)
+ 8004944:	47000115 	stw	fp,4(r8)
+ 8004948:	d8c01e15 	stw	r3,120(sp)
+ 800494c:	d8801d15 	stw	r2,116(sp)
+ 8004950:	11000208 	cmpgei	r4,r2,8
+ 8004954:	203ff426 	beq	r4,zero,8004928 <___vfprintf_internal_r+0x1ae4>
+ 8004958:	d9000517 	ldw	r4,20(sp)
+ 800495c:	d9801c04 	addi	r6,sp,112
+ 8004960:	980b883a 	mov	r5,r19
+ 8004964:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004968:	103a151e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 800496c:	d8c01e17 	ldw	r3,120(sp)
+ 8004970:	d8801d17 	ldw	r2,116(sp)
+ 8004974:	b811883a 	mov	r8,r23
+ 8004978:	003fec06 	br	800492c <___vfprintf_internal_r+0x1ae8>
+ 800497c:	8009883a 	mov	r4,r16
+ 8004980:	8002dac0 	call	8002dac <strlen>
+ 8004984:	1029883a 	mov	r20,r2
+ 8004988:	102b883a 	mov	r21,r2
+ 800498c:	dc800615 	stw	r18,24(sp)
+ 8004990:	db000717 	ldw	r12,28(sp)
+ 8004994:	da000e17 	ldw	r8,56(sp)
+ 8004998:	003ac306 	br	80034a8 <___vfprintf_internal_r+0x664>
+ 800499c:	8817883a 	mov	r11,r17
+ 80049a0:	9019883a 	mov	r12,r18
+ 80049a4:	dc400e17 	ldw	r17,56(sp)
+ 80049a8:	dc800717 	ldw	r18,28(sp)
+ 80049ac:	a7000044 	addi	fp,r20,1
+ 80049b0:	50800204 	addi	r2,r10,8
+ 80049b4:	1ac7883a 	add	r3,r3,r11
+ 80049b8:	53000015 	stw	r12,0(r10)
+ 80049bc:	52c00115 	stw	r11,4(r10)
+ 80049c0:	d8c01e15 	stw	r3,120(sp)
+ 80049c4:	df001d15 	stw	fp,116(sp)
+ 80049c8:	e1000208 	cmpgei	r4,fp,8
+ 80049cc:	203f291e 	bne	r4,zero,8004674 <___vfprintf_internal_r+0x1830>
+ 80049d0:	e7000044 	addi	fp,fp,1
+ 80049d4:	12000204 	addi	r8,r2,8
+ 80049d8:	1015883a 	mov	r10,r2
+ 80049dc:	003d7f06 	br	8003fdc <___vfprintf_internal_r+0x1198>
+ 80049e0:	8819883a 	mov	r12,r17
+ 80049e4:	dc400717 	ldw	r17,28(sp)
+ 80049e8:	10800044 	addi	r2,r2,1
+ 80049ec:	1c07883a 	add	r3,r3,r16
+ 80049f0:	d8801d15 	stw	r2,116(sp)
+ 80049f4:	43000015 	stw	r12,0(r8)
+ 80049f8:	44000115 	stw	r16,4(r8)
+ 80049fc:	d8c01e15 	stw	r3,120(sp)
+ 8004a00:	10800208 	cmpgei	r2,r2,8
+ 8004a04:	103add26 	beq	r2,zero,800357c <___vfprintf_internal_r+0x738>
+ 8004a08:	003d3306 	br	8003ed8 <___vfprintf_internal_r+0x1094>
+ 8004a0c:	d8800615 	stw	r2,24(sp)
+ 8004a10:	0029883a 	mov	r20,zero
+ 8004a14:	0005883a 	mov	r2,zero
+ 8004a18:	003be506 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8004a1c:	d8800615 	stw	r2,24(sp)
+ 8004a20:	0029883a 	mov	r20,zero
+ 8004a24:	00800044 	movi	r2,1
+ 8004a28:	003be106 	br	80039b0 <___vfprintf_internal_r+0xb6c>
+ 8004a2c:	d8801a04 	addi	r2,sp,104
+ 8004a30:	d8800315 	stw	r2,12(sp)
+ 8004a34:	d9400917 	ldw	r5,36(sp)
+ 8004a38:	d8801704 	addi	r2,sp,92
+ 8004a3c:	d9000517 	ldw	r4,20(sp)
+ 8004a40:	d8800215 	stw	r2,8(sp)
+ 8004a44:	d8801604 	addi	r2,sp,88
+ 8004a48:	dac00015 	stw	r11,0(sp)
+ 8004a4c:	d8800115 	stw	r2,4(sp)
+ 8004a50:	01c000c4 	movi	r7,3
+ 8004a54:	a80d883a 	mov	r6,r21
+ 8004a58:	da001215 	stw	r8,72(sp)
+ 8004a5c:	db001015 	stw	r12,64(sp)
+ 8004a60:	dac00815 	stw	r11,32(sp)
+ 8004a64:	80053ec0 	call	80053ec <_dtoa_r>
+ 8004a68:	dac00817 	ldw	r11,32(sp)
+ 8004a6c:	1021883a 	mov	r16,r2
+ 8004a70:	db001017 	ldw	r12,64(sp)
+ 8004a74:	12e9883a 	add	r20,r2,r11
+ 8004a78:	80800007 	ldb	r2,0(r16)
+ 8004a7c:	da001217 	ldw	r8,72(sp)
+ 8004a80:	10800c20 	cmpeqi	r2,r2,48
+ 8004a84:	10005b1e 	bne	r2,zero,8004bf4 <___vfprintf_internal_r+0x1db0>
+ 8004a88:	d8801617 	ldw	r2,88(sp)
+ 8004a8c:	a0a9883a 	add	r20,r20,r2
+ 8004a90:	d9000917 	ldw	r4,36(sp)
+ 8004a94:	000d883a 	mov	r6,zero
+ 8004a98:	000f883a 	mov	r7,zero
+ 8004a9c:	a80b883a 	mov	r5,r21
+ 8004aa0:	da001215 	stw	r8,72(sp)
+ 8004aa4:	dac01015 	stw	r11,64(sp)
+ 8004aa8:	db000815 	stw	r12,32(sp)
+ 8004aac:	800e3000 	call	800e300 <__eqdf2>
+ 8004ab0:	db000817 	ldw	r12,32(sp)
+ 8004ab4:	dac01017 	ldw	r11,64(sp)
+ 8004ab8:	da001217 	ldw	r8,72(sp)
+ 8004abc:	1000891e 	bne	r2,zero,8004ce4 <___vfprintf_internal_r+0x1ea0>
+ 8004ac0:	a005883a 	mov	r2,r20
+ 8004ac4:	1405c83a 	sub	r2,r2,r16
+ 8004ac8:	d8c00717 	ldw	r3,28(sp)
+ 8004acc:	d8800815 	stw	r2,32(sp)
+ 8004ad0:	d8801617 	ldw	r2,88(sp)
+ 8004ad4:	18c011d8 	cmpnei	r3,r3,71
+ 8004ad8:	d8800715 	stw	r2,28(sp)
+ 8004adc:	183e8426 	beq	r3,zero,80044f0 <___vfprintf_internal_r+0x16ac>
+ 8004ae0:	d8800f17 	ldw	r2,60(sp)
+ 8004ae4:	103e8726 	beq	r2,zero,8004504 <___vfprintf_internal_r+0x16c0>
+ 8004ae8:	d8c00717 	ldw	r3,28(sp)
+ 8004aec:	6080004c 	andi	r2,r12,1
+ 8004af0:	12c4b03a 	or	r2,r2,r11
+ 8004af4:	00c10d0e 	bge	zero,r3,8004f2c <___vfprintf_internal_r+0x20e8>
+ 8004af8:	1000f11e 	bne	r2,zero,8004ec0 <___vfprintf_internal_r+0x207c>
+ 8004afc:	dd000717 	ldw	r20,28(sp)
+ 8004b00:	a02b883a 	mov	r21,r20
+ 8004b04:	d8800e07 	ldb	r2,56(sp)
+ 8004b08:	10007f26 	beq	r2,zero,8004d08 <___vfprintf_internal_r+0x1ec4>
+ 8004b0c:	00800b44 	movi	r2,45
+ 8004b10:	d8801545 	stb	r2,85(sp)
+ 8004b14:	0017883a 	mov	r11,zero
+ 8004b18:	003be506 	br	8003ab0 <___vfprintf_internal_r+0xc6c>
+ 8004b1c:	04020134 	movhi	r16,2052
+ 8004b20:	841d1704 	addi	r16,r16,29788
+ 8004b24:	003b3406 	br	80037f8 <___vfprintf_internal_r+0x9b4>
+ 8004b28:	9019883a 	mov	r12,r18
+ 8004b2c:	dc000e17 	ldw	r16,56(sp)
+ 8004b30:	dc800f17 	ldw	r18,60(sp)
+ 8004b34:	e009883a 	mov	r4,fp
+ 8004b38:	8839883a 	mov	fp,r17
+ 8004b3c:	b023883a 	mov	r17,r22
+ 8004b40:	202d883a 	mov	r22,r4
+ 8004b44:	10800044 	addi	r2,r2,1
+ 8004b48:	1f07883a 	add	r3,r3,fp
+ 8004b4c:	d8801d15 	stw	r2,116(sp)
+ 8004b50:	43000015 	stw	r12,0(r8)
+ 8004b54:	47000115 	stw	fp,4(r8)
+ 8004b58:	d8c01e15 	stw	r3,120(sp)
+ 8004b5c:	10800208 	cmpgei	r2,r2,8
+ 8004b60:	1000421e 	bne	r2,zero,8004c6c <___vfprintf_internal_r+0x1e28>
+ 8004b64:	42000204 	addi	r8,r8,8
+ 8004b68:	003da106 	br	80041f0 <___vfprintf_internal_r+0x13ac>
+ 8004b6c:	00800b44 	movi	r2,45
+ 8004b70:	d8801545 	stb	r2,85(sp)
+ 8004b74:	03400b44 	movi	r13,45
+ 8004b78:	003b1b06 	br	80037e8 <___vfprintf_internal_r+0x9a4>
+ 8004b7c:	8819883a 	mov	r12,r17
+ 8004b80:	dc400717 	ldw	r17,28(sp)
+ 8004b84:	10800044 	addi	r2,r2,1
+ 8004b88:	1f07883a 	add	r3,r3,fp
+ 8004b8c:	d8801d15 	stw	r2,116(sp)
+ 8004b90:	43000015 	stw	r12,0(r8)
+ 8004b94:	47000115 	stw	fp,4(r8)
+ 8004b98:	d8c01e15 	stw	r3,120(sp)
+ 8004b9c:	10800208 	cmpgei	r2,r2,8
+ 8004ba0:	103a7626 	beq	r2,zero,800357c <___vfprintf_internal_r+0x738>
+ 8004ba4:	003ccc06 	br	8003ed8 <___vfprintf_internal_r+0x1094>
+ 8004ba8:	d9000517 	ldw	r4,20(sp)
+ 8004bac:	d9801c04 	addi	r6,sp,112
+ 8004bb0:	980b883a 	mov	r5,r19
+ 8004bb4:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004bb8:	1039811e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004bbc:	d9001617 	ldw	r4,88(sp)
+ 8004bc0:	d8c01e17 	ldw	r3,120(sp)
+ 8004bc4:	b811883a 	mov	r8,r23
+ 8004bc8:	003d9806 	br	800422c <___vfprintf_internal_r+0x13e8>
+ 8004bcc:	1560003c 	xorhi	r21,r2,32768
+ 8004bd0:	00800b44 	movi	r2,45
+ 8004bd4:	d8800e05 	stb	r2,56(sp)
+ 8004bd8:	003e1d06 	br	8004450 <___vfprintf_internal_r+0x160c>
+ 8004bdc:	05000184 	movi	r20,6
+ 8004be0:	003ec306 	br	80046f0 <___vfprintf_internal_r+0x18ac>
+ 8004be4:	002b883a 	mov	r21,zero
+ 8004be8:	003a0706 	br	8003408 <___vfprintf_internal_r+0x5c4>
+ 8004bec:	d9401545 	stb	r5,85(sp)
+ 8004bf0:	00399106 	br	8003238 <___vfprintf_internal_r+0x3f4>
+ 8004bf4:	d9000917 	ldw	r4,36(sp)
+ 8004bf8:	000d883a 	mov	r6,zero
+ 8004bfc:	000f883a 	mov	r7,zero
+ 8004c00:	a80b883a 	mov	r5,r21
+ 8004c04:	da001215 	stw	r8,72(sp)
+ 8004c08:	dac01015 	stw	r11,64(sp)
+ 8004c0c:	db000815 	stw	r12,32(sp)
+ 8004c10:	800e3000 	call	800e300 <__eqdf2>
+ 8004c14:	db000817 	ldw	r12,32(sp)
+ 8004c18:	dac01017 	ldw	r11,64(sp)
+ 8004c1c:	da001217 	ldw	r8,72(sp)
+ 8004c20:	103f9926 	beq	r2,zero,8004a88 <___vfprintf_internal_r+0x1c44>
+ 8004c24:	00800044 	movi	r2,1
+ 8004c28:	12c5c83a 	sub	r2,r2,r11
+ 8004c2c:	d8801615 	stw	r2,88(sp)
+ 8004c30:	003f9606 	br	8004a8c <___vfprintf_internal_r+0x1c48>
+ 8004c34:	583e011e 	bne	r11,zero,800443c <___vfprintf_internal_r+0x15f8>
+ 8004c38:	02c00044 	movi	r11,1
+ 8004c3c:	003dff06 	br	800443c <___vfprintf_internal_r+0x15f8>
+ 8004c40:	d9000517 	ldw	r4,20(sp)
+ 8004c44:	d9801c04 	addi	r6,sp,112
+ 8004c48:	980b883a 	mov	r5,r19
+ 8004c4c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004c50:	10395b1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004c54:	d9001617 	ldw	r4,88(sp)
+ 8004c58:	d8c01e17 	ldw	r3,120(sp)
+ 8004c5c:	d8801d17 	ldw	r2,116(sp)
+ 8004c60:	b811883a 	mov	r8,r23
+ 8004c64:	203c930e 	bge	r4,zero,8003eb4 <___vfprintf_internal_r+0x1070>
+ 8004c68:	003f2406 	br	80048fc <___vfprintf_internal_r+0x1ab8>
+ 8004c6c:	d9000517 	ldw	r4,20(sp)
+ 8004c70:	d9801c04 	addi	r6,sp,112
+ 8004c74:	980b883a 	mov	r5,r19
+ 8004c78:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004c7c:	1039501e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004c80:	d8c01e17 	ldw	r3,120(sp)
+ 8004c84:	b811883a 	mov	r8,r23
+ 8004c88:	003d5906 	br	80041f0 <___vfprintf_internal_r+0x13ac>
+ 8004c8c:	d8801a04 	addi	r2,sp,104
+ 8004c90:	d8800315 	stw	r2,12(sp)
+ 8004c94:	d9400917 	ldw	r5,36(sp)
+ 8004c98:	d8801704 	addi	r2,sp,92
+ 8004c9c:	d9000517 	ldw	r4,20(sp)
+ 8004ca0:	5d000044 	addi	r20,r11,1
+ 8004ca4:	d8800215 	stw	r2,8(sp)
+ 8004ca8:	d8801604 	addi	r2,sp,88
+ 8004cac:	d8800115 	stw	r2,4(sp)
+ 8004cb0:	dd000015 	stw	r20,0(sp)
+ 8004cb4:	01c00084 	movi	r7,2
+ 8004cb8:	a80d883a 	mov	r6,r21
+ 8004cbc:	dac00815 	stw	r11,32(sp)
+ 8004cc0:	80053ec0 	call	80053ec <_dtoa_r>
+ 8004cc4:	dac00817 	ldw	r11,32(sp)
+ 8004cc8:	db001017 	ldw	r12,64(sp)
+ 8004ccc:	da001217 	ldw	r8,72(sp)
+ 8004cd0:	1021883a 	mov	r16,r2
+ 8004cd4:	e08011d8 	cmpnei	r2,fp,71
+ 8004cd8:	103dfb26 	beq	r2,zero,80044c8 <___vfprintf_internal_r+0x1684>
+ 8004cdc:	8529883a 	add	r20,r16,r20
+ 8004ce0:	003f6b06 	br	8004a90 <___vfprintf_internal_r+0x1c4c>
+ 8004ce4:	d8801a17 	ldw	r2,104(sp)
+ 8004ce8:	01000c04 	movi	r4,48
+ 8004cec:	153f752e 	bgeu	r2,r20,8004ac4 <___vfprintf_internal_r+0x1c80>
+ 8004cf0:	10c00044 	addi	r3,r2,1
+ 8004cf4:	d8c01a15 	stw	r3,104(sp)
+ 8004cf8:	11000005 	stb	r4,0(r2)
+ 8004cfc:	d8801a17 	ldw	r2,104(sp)
+ 8004d00:	153ffb36 	bltu	r2,r20,8004cf0 <___vfprintf_internal_r+0x1eac>
+ 8004d04:	003f6f06 	br	8004ac4 <___vfprintf_internal_r+0x1c80>
+ 8004d08:	db401543 	ldbu	r13,85(sp)
+ 8004d0c:	0017883a 	mov	r11,zero
+ 8004d10:	003b6306 	br	8003aa0 <___vfprintf_internal_r+0xc5c>
+ 8004d14:	d8800717 	ldw	r2,28(sp)
+ 8004d18:	d8c00817 	ldw	r3,32(sp)
+ 8004d1c:	10c02216 	blt	r2,r3,8004da8 <___vfprintf_internal_r+0x1f64>
+ 8004d20:	6300004c 	andi	r12,r12,1
+ 8004d24:	60005f1e 	bne	r12,zero,8004ea4 <___vfprintf_internal_r+0x2060>
+ 8004d28:	102b883a 	mov	r21,r2
+ 8004d2c:	1000010e 	bge	r2,zero,8004d34 <___vfprintf_internal_r+0x1ef0>
+ 8004d30:	002b883a 	mov	r21,zero
+ 8004d34:	dd000717 	ldw	r20,28(sp)
+ 8004d38:	070019c4 	movi	fp,103
+ 8004d3c:	003f7106 	br	8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004d40:	d9000517 	ldw	r4,20(sp)
+ 8004d44:	d9801c04 	addi	r6,sp,112
+ 8004d48:	980b883a 	mov	r5,r19
+ 8004d4c:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004d50:	10391b1e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004d54:	d8c01e17 	ldw	r3,120(sp)
+ 8004d58:	b811883a 	mov	r8,r23
+ 8004d5c:	e03d210e 	bge	fp,zero,80041e4 <___vfprintf_internal_r+0x13a0>
+ 8004d60:	003e5e06 	br	80046dc <___vfprintf_internal_r+0x1898>
+ 8004d64:	02c00184 	movi	r11,6
+ 8004d68:	003db406 	br	800443c <___vfprintf_internal_r+0x15f8>
+ 8004d6c:	d9000517 	ldw	r4,20(sp)
+ 8004d70:	d9801c04 	addi	r6,sp,112
+ 8004d74:	980b883a 	mov	r5,r19
+ 8004d78:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004d7c:	1039101e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004d80:	d8801617 	ldw	r2,88(sp)
+ 8004d84:	d9000817 	ldw	r4,32(sp)
+ 8004d88:	d8c01e17 	ldw	r3,120(sp)
+ 8004d8c:	b811883a 	mov	r8,r23
+ 8004d90:	2085c83a 	sub	r2,r4,r2
+ 8004d94:	003d3706 	br	8004274 <___vfprintf_internal_r+0x1430>
+ 8004d98:	582b883a 	mov	r21,r11
+ 8004d9c:	dc800615 	stw	r18,24(sp)
+ 8004da0:	5829883a 	mov	r20,r11
+ 8004da4:	0039c006 	br	80034a8 <___vfprintf_internal_r+0x664>
+ 8004da8:	d8800817 	ldw	r2,32(sp)
+ 8004dac:	d8c00b17 	ldw	r3,44(sp)
+ 8004db0:	10e9883a 	add	r20,r2,r3
+ 8004db4:	d8800717 	ldw	r2,28(sp)
+ 8004db8:	00800316 	blt	zero,r2,8004dc8 <___vfprintf_internal_r+0x1f84>
+ 8004dbc:	d8800717 	ldw	r2,28(sp)
+ 8004dc0:	a0b9c83a 	sub	fp,r20,r2
+ 8004dc4:	e5000044 	addi	r20,fp,1
+ 8004dc8:	a02b883a 	mov	r21,r20
+ 8004dcc:	a0003a16 	blt	r20,zero,8004eb8 <___vfprintf_internal_r+0x2074>
+ 8004dd0:	070019c4 	movi	fp,103
+ 8004dd4:	003f4b06 	br	8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004dd8:	d9401545 	stb	r5,85(sp)
+ 8004ddc:	003ac506 	br	80038f4 <___vfprintf_internal_r+0xab0>
+ 8004de0:	d9401545 	stb	r5,85(sp)
+ 8004de4:	003a2506 	br	800367c <___vfprintf_internal_r+0x838>
+ 8004de8:	d9401545 	stb	r5,85(sp)
+ 8004dec:	003a3306 	br	80036bc <___vfprintf_internal_r+0x878>
+ 8004df0:	d9401545 	stb	r5,85(sp)
+ 8004df4:	00398806 	br	8003418 <___vfprintf_internal_r+0x5d4>
+ 8004df8:	d9401545 	stb	r5,85(sp)
+ 8004dfc:	00395f06 	br	800337c <___vfprintf_internal_r+0x538>
+ 8004e00:	d9401545 	stb	r5,85(sp)
+ 8004e04:	00394b06 	br	8003334 <___vfprintf_internal_r+0x4f0>
+ 8004e08:	d9401545 	stb	r5,85(sp)
+ 8004e0c:	003a3b06 	br	80036fc <___vfprintf_internal_r+0x8b8>
+ 8004e10:	d9401545 	stb	r5,85(sp)
+ 8004e14:	003a8106 	br	800381c <___vfprintf_internal_r+0x9d8>
+ 8004e18:	d9401545 	stb	r5,85(sp)
+ 8004e1c:	003a4706 	br	800373c <___vfprintf_internal_r+0x8f8>
+ 8004e20:	d9401545 	stb	r5,85(sp)
+ 8004e24:	003ac506 	br	800393c <___vfprintf_internal_r+0xaf8>
+ 8004e28:	8819883a 	mov	r12,r17
+ 8004e2c:	a023883a 	mov	r17,r20
+ 8004e30:	8029883a 	mov	r20,r16
+ 8004e34:	dc000717 	ldw	r16,28(sp)
+ 8004e38:	10800044 	addi	r2,r2,1
+ 8004e3c:	1d07883a 	add	r3,r3,r20
+ 8004e40:	43000015 	stw	r12,0(r8)
+ 8004e44:	45000115 	stw	r20,4(r8)
+ 8004e48:	d8c01e15 	stw	r3,120(sp)
+ 8004e4c:	d8801d15 	stw	r2,116(sp)
+ 8004e50:	11000208 	cmpgei	r4,r2,8
+ 8004e54:	203c1626 	beq	r4,zero,8003eb0 <___vfprintf_internal_r+0x106c>
+ 8004e58:	d9000517 	ldw	r4,20(sp)
+ 8004e5c:	d9801c04 	addi	r6,sp,112
+ 8004e60:	980b883a 	mov	r5,r19
+ 8004e64:	800a3f80 	call	800a3f8 <__sprint_r>
+ 8004e68:	1038d51e 	bne	r2,zero,80031c0 <___vfprintf_internal_r+0x37c>
+ 8004e6c:	d8c01e17 	ldw	r3,120(sp)
+ 8004e70:	d8801d17 	ldw	r2,116(sp)
+ 8004e74:	b811883a 	mov	r8,r23
+ 8004e78:	003c0e06 	br	8003eb4 <___vfprintf_internal_r+0x1070>
+ 8004e7c:	00bfffc4 	movi	r2,-1
+ 8004e80:	d8800415 	stw	r2,16(sp)
+ 8004e84:	0038d106 	br	80031cc <___vfprintf_internal_r+0x388>
+ 8004e88:	00800c04 	movi	r2,48
+ 8004e8c:	a0c00c04 	addi	r3,r20,48
+ 8004e90:	d88018c5 	stb	r2,99(sp)
+ 8004e94:	00800104 	movi	r2,4
+ 8004e98:	d8c01905 	stb	r3,100(sp)
+ 8004e9c:	d8801115 	stw	r2,68(sp)
+ 8004ea0:	003dcd06 	br	80045d8 <___vfprintf_internal_r+0x1794>
+ 8004ea4:	d8800717 	ldw	r2,28(sp)
+ 8004ea8:	d8c00b17 	ldw	r3,44(sp)
+ 8004eac:	10e9883a 	add	r20,r2,r3
+ 8004eb0:	a02b883a 	mov	r21,r20
+ 8004eb4:	a03fc60e 	bge	r20,zero,8004dd0 <___vfprintf_internal_r+0x1f8c>
+ 8004eb8:	002b883a 	mov	r21,zero
+ 8004ebc:	003fc406 	br	8004dd0 <___vfprintf_internal_r+0x1f8c>
+ 8004ec0:	d8800b17 	ldw	r2,44(sp)
+ 8004ec4:	1885883a 	add	r2,r3,r2
+ 8004ec8:	12e9883a 	add	r20,r2,r11
+ 8004ecc:	a02b883a 	mov	r21,r20
+ 8004ed0:	a03f0c0e 	bge	r20,zero,8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004ed4:	002b883a 	mov	r21,zero
+ 8004ed8:	003f0a06 	br	8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004edc:	d8800a17 	ldw	r2,40(sp)
+ 8004ee0:	10001d16 	blt	r2,zero,8004f58 <___vfprintf_internal_r+0x2114>
+ 8004ee4:	db401543 	ldbu	r13,85(sp)
+ 8004ee8:	e0801210 	cmplti	r2,fp,72
+ 8004eec:	1000171e 	bne	r2,zero,8004f4c <___vfprintf_internal_r+0x2108>
+ 8004ef0:	04020134 	movhi	r16,2052
+ 8004ef4:	841d1a04 	addi	r16,r16,29800
+ 8004ef8:	003a3f06 	br	80037f8 <___vfprintf_internal_r+0x9b4>
+ 8004efc:	00c00044 	movi	r3,1
+ 8004f00:	18a9c83a 	sub	r20,r3,r2
+ 8004f04:	00800b44 	movi	r2,45
+ 8004f08:	d8801885 	stb	r2,98(sp)
+ 8004f0c:	003d8406 	br	8004520 <___vfprintf_internal_r+0x16dc>
+ 8004f10:	6080004c 	andi	r2,r12,1
+ 8004f14:	d8800715 	stw	r2,28(sp)
+ 8004f18:	103db41e 	bne	r2,zero,80045ec <___vfprintf_internal_r+0x17a8>
+ 8004f1c:	003feb06 	br	8004ecc <___vfprintf_internal_r+0x2088>
+ 8004f20:	4005883a 	mov	r2,r8
+ 8004f24:	631d2784 	addi	r12,r12,29854
+ 8004f28:	003ea206 	br	80049b4 <___vfprintf_internal_r+0x1b70>
+ 8004f2c:	1000031e 	bne	r2,zero,8004f3c <___vfprintf_internal_r+0x20f8>
+ 8004f30:	05400044 	movi	r21,1
+ 8004f34:	05000044 	movi	r20,1
+ 8004f38:	003ef206 	br	8004b04 <___vfprintf_internal_r+0x1cc0>
+ 8004f3c:	d8800b17 	ldw	r2,44(sp)
+ 8004f40:	10800044 	addi	r2,r2,1
+ 8004f44:	12e9883a 	add	r20,r2,r11
+ 8004f48:	003fe006 	br	8004ecc <___vfprintf_internal_r+0x2088>
+ 8004f4c:	04020134 	movhi	r16,2052
+ 8004f50:	841d1904 	addi	r16,r16,29796
+ 8004f54:	003a2806 	br	80037f8 <___vfprintf_internal_r+0x9b4>
+ 8004f58:	00800b44 	movi	r2,45
+ 8004f5c:	d8801545 	stb	r2,85(sp)
+ 8004f60:	03400b44 	movi	r13,45
+ 8004f64:	003fe006 	br	8004ee8 <___vfprintf_internal_r+0x20a4>
+ 8004f68:	00800084 	movi	r2,2
+ 8004f6c:	d8801115 	stw	r2,68(sp)
+ 8004f70:	003d9906 	br	80045d8 <___vfprintf_internal_r+0x1794>
+ 8004f74:	d8800617 	ldw	r2,24(sp)
+ 8004f78:	12c00017 	ldw	r11,0(r2)
+ 8004f7c:	10800104 	addi	r2,r2,4
+ 8004f80:	5800010e 	bge	r11,zero,8004f88 <___vfprintf_internal_r+0x2144>
+ 8004f84:	02ffffc4 	movi	r11,-1
+ 8004f88:	b7000043 	ldbu	fp,1(r22)
+ 8004f8c:	d8800615 	stw	r2,24(sp)
+ 8004f90:	182d883a 	mov	r22,r3
+ 8004f94:	e2803fcc 	andi	r10,fp,255
+ 8004f98:	5280201c 	xori	r10,r10,128
+ 8004f9c:	52bfe004 	addi	r10,r10,-128
+ 8004fa0:	00380306 	br	8002fb0 <___vfprintf_internal_r+0x16c>
+
+08004fa4 <__vfprintf_internal>:
+ 8004fa4:	00820174 	movhi	r2,2053
+ 8004fa8:	300f883a 	mov	r7,r6
+ 8004fac:	280d883a 	mov	r6,r5
+ 8004fb0:	200b883a 	mov	r5,r4
+ 8004fb4:	1132af17 	ldw	r4,-13636(r2)
+ 8004fb8:	8002e441 	jmpi	8002e44 <___vfprintf_internal_r>
+
+08004fbc <__sbprintf>:
+ 8004fbc:	2880030b 	ldhu	r2,12(r5)
+ 8004fc0:	2b001917 	ldw	r12,100(r5)
+ 8004fc4:	2ac0038b 	ldhu	r11,14(r5)
+ 8004fc8:	2a800717 	ldw	r10,28(r5)
+ 8004fcc:	2a400917 	ldw	r9,36(r5)
+ 8004fd0:	defee204 	addi	sp,sp,-1144
+ 8004fd4:	da001a04 	addi	r8,sp,104
+ 8004fd8:	00c10004 	movi	r3,1024
+ 8004fdc:	dc011a15 	stw	r16,1128(sp)
+ 8004fe0:	10bfff4c 	andi	r2,r2,65533
+ 8004fe4:	2821883a 	mov	r16,r5
+ 8004fe8:	d80b883a 	mov	r5,sp
+ 8004fec:	dc811c15 	stw	r18,1136(sp)
+ 8004ff0:	dc411b15 	stw	r17,1132(sp)
+ 8004ff4:	dfc11d15 	stw	ra,1140(sp)
+ 8004ff8:	2025883a 	mov	r18,r4
+ 8004ffc:	d880030d 	sth	r2,12(sp)
+ 8005000:	db001915 	stw	r12,100(sp)
+ 8005004:	dac0038d 	sth	r11,14(sp)
+ 8005008:	da800715 	stw	r10,28(sp)
+ 800500c:	da400915 	stw	r9,36(sp)
+ 8005010:	da000015 	stw	r8,0(sp)
+ 8005014:	da000415 	stw	r8,16(sp)
+ 8005018:	d8c00215 	stw	r3,8(sp)
+ 800501c:	d8c00515 	stw	r3,20(sp)
+ 8005020:	d8000615 	stw	zero,24(sp)
+ 8005024:	8002e440 	call	8002e44 <___vfprintf_internal_r>
+ 8005028:	1023883a 	mov	r17,r2
+ 800502c:	10000d0e 	bge	r2,zero,8005064 <__sbprintf+0xa8>
+ 8005030:	d880030b 	ldhu	r2,12(sp)
+ 8005034:	1080100c 	andi	r2,r2,64
+ 8005038:	10000326 	beq	r2,zero,8005048 <__sbprintf+0x8c>
+ 800503c:	8080030b 	ldhu	r2,12(r16)
+ 8005040:	10801014 	ori	r2,r2,64
+ 8005044:	8080030d 	sth	r2,12(r16)
+ 8005048:	8805883a 	mov	r2,r17
+ 800504c:	dfc11d17 	ldw	ra,1140(sp)
+ 8005050:	dc811c17 	ldw	r18,1136(sp)
+ 8005054:	dc411b17 	ldw	r17,1132(sp)
+ 8005058:	dc011a17 	ldw	r16,1128(sp)
+ 800505c:	dec11e04 	addi	sp,sp,1144
+ 8005060:	f800283a 	ret
+ 8005064:	d80b883a 	mov	r5,sp
+ 8005068:	9009883a 	mov	r4,r18
+ 800506c:	8006cdc0 	call	8006cdc <_fflush_r>
+ 8005070:	103fef26 	beq	r2,zero,8005030 <__sbprintf+0x74>
+ 8005074:	047fffc4 	movi	r17,-1
+ 8005078:	003fed06 	br	8005030 <__sbprintf+0x74>
+
+0800507c <__swsetup_r>:
+ 800507c:	00820174 	movhi	r2,2053
+ 8005080:	10b2af17 	ldw	r2,-13636(r2)
+ 8005084:	defffd04 	addi	sp,sp,-12
+ 8005088:	dc400115 	stw	r17,4(sp)
+ 800508c:	dc000015 	stw	r16,0(sp)
+ 8005090:	dfc00215 	stw	ra,8(sp)
+ 8005094:	2023883a 	mov	r17,r4
+ 8005098:	2821883a 	mov	r16,r5
+ 800509c:	10000226 	beq	r2,zero,80050a8 <__swsetup_r+0x2c>
+ 80050a0:	10c00e17 	ldw	r3,56(r2)
+ 80050a4:	18002026 	beq	r3,zero,8005128 <__swsetup_r+0xac>
+ 80050a8:	8080030b 	ldhu	r2,12(r16)
+ 80050ac:	10c0020c 	andi	r3,r2,8
+ 80050b0:	1009883a 	mov	r4,r2
+ 80050b4:	18002226 	beq	r3,zero,8005140 <__swsetup_r+0xc4>
+ 80050b8:	80c00417 	ldw	r3,16(r16)
+ 80050bc:	18002826 	beq	r3,zero,8005160 <__swsetup_r+0xe4>
+ 80050c0:	1100004c 	andi	r4,r2,1
+ 80050c4:	20000b1e 	bne	r4,zero,80050f4 <__swsetup_r+0x78>
+ 80050c8:	1080008c 	andi	r2,r2,2
+ 80050cc:	10002d1e 	bne	r2,zero,8005184 <__swsetup_r+0x108>
+ 80050d0:	80800517 	ldw	r2,20(r16)
+ 80050d4:	80800215 	stw	r2,8(r16)
+ 80050d8:	18000b26 	beq	r3,zero,8005108 <__swsetup_r+0x8c>
+ 80050dc:	0005883a 	mov	r2,zero
+ 80050e0:	dfc00217 	ldw	ra,8(sp)
+ 80050e4:	dc400117 	ldw	r17,4(sp)
+ 80050e8:	dc000017 	ldw	r16,0(sp)
+ 80050ec:	dec00304 	addi	sp,sp,12
+ 80050f0:	f800283a 	ret
+ 80050f4:	80800517 	ldw	r2,20(r16)
+ 80050f8:	80000215 	stw	zero,8(r16)
+ 80050fc:	0085c83a 	sub	r2,zero,r2
+ 8005100:	80800615 	stw	r2,24(r16)
+ 8005104:	183ff51e 	bne	r3,zero,80050dc <__swsetup_r+0x60>
+ 8005108:	80c0030b 	ldhu	r3,12(r16)
+ 800510c:	0005883a 	mov	r2,zero
+ 8005110:	1900200c 	andi	r4,r3,128
+ 8005114:	203ff226 	beq	r4,zero,80050e0 <__swsetup_r+0x64>
+ 8005118:	18c01014 	ori	r3,r3,64
+ 800511c:	80c0030d 	sth	r3,12(r16)
+ 8005120:	00bfffc4 	movi	r2,-1
+ 8005124:	003fee06 	br	80050e0 <__swsetup_r+0x64>
+ 8005128:	1009883a 	mov	r4,r2
+ 800512c:	80070600 	call	8007060 <__sinit>
+ 8005130:	8080030b 	ldhu	r2,12(r16)
+ 8005134:	10c0020c 	andi	r3,r2,8
+ 8005138:	1009883a 	mov	r4,r2
+ 800513c:	183fde1e 	bne	r3,zero,80050b8 <__swsetup_r+0x3c>
+ 8005140:	2080040c 	andi	r2,r4,16
+ 8005144:	10001f26 	beq	r2,zero,80051c4 <__swsetup_r+0x148>
+ 8005148:	2080010c 	andi	r2,r4,4
+ 800514c:	10000f1e 	bne	r2,zero,800518c <__swsetup_r+0x110>
+ 8005150:	80c00417 	ldw	r3,16(r16)
+ 8005154:	20800214 	ori	r2,r4,8
+ 8005158:	8080030d 	sth	r2,12(r16)
+ 800515c:	183fd81e 	bne	r3,zero,80050c0 <__swsetup_r+0x44>
+ 8005160:	1100a00c 	andi	r4,r2,640
+ 8005164:	21008020 	cmpeqi	r4,r4,512
+ 8005168:	203fd51e 	bne	r4,zero,80050c0 <__swsetup_r+0x44>
+ 800516c:	800b883a 	mov	r5,r16
+ 8005170:	8809883a 	mov	r4,r17
+ 8005174:	8007ca00 	call	8007ca0 <__smakebuf_r>
+ 8005178:	8080030b 	ldhu	r2,12(r16)
+ 800517c:	80c00417 	ldw	r3,16(r16)
+ 8005180:	003fcf06 	br	80050c0 <__swsetup_r+0x44>
+ 8005184:	0005883a 	mov	r2,zero
+ 8005188:	003fd206 	br	80050d4 <__swsetup_r+0x58>
+ 800518c:	81400c17 	ldw	r5,48(r16)
+ 8005190:	28000626 	beq	r5,zero,80051ac <__swsetup_r+0x130>
+ 8005194:	80801004 	addi	r2,r16,64
+ 8005198:	28800326 	beq	r5,r2,80051a8 <__swsetup_r+0x12c>
+ 800519c:	8809883a 	mov	r4,r17
+ 80051a0:	80071c40 	call	80071c4 <_free_r>
+ 80051a4:	8100030b 	ldhu	r4,12(r16)
+ 80051a8:	80000c15 	stw	zero,48(r16)
+ 80051ac:	80c00417 	ldw	r3,16(r16)
+ 80051b0:	00bff6c4 	movi	r2,-37
+ 80051b4:	1108703a 	and	r4,r2,r4
+ 80051b8:	80000115 	stw	zero,4(r16)
+ 80051bc:	80c00015 	stw	r3,0(r16)
+ 80051c0:	003fe406 	br	8005154 <__swsetup_r+0xd8>
+ 80051c4:	00800244 	movi	r2,9
+ 80051c8:	88800015 	stw	r2,0(r17)
+ 80051cc:	20801014 	ori	r2,r4,64
+ 80051d0:	8080030d 	sth	r2,12(r16)
+ 80051d4:	00bfffc4 	movi	r2,-1
+ 80051d8:	003fc106 	br	80050e0 <__swsetup_r+0x64>
+
+080051dc <quorem>:
+ 80051dc:	defff504 	addi	sp,sp,-44
+ 80051e0:	dc800315 	stw	r18,12(sp)
+ 80051e4:	20800417 	ldw	r2,16(r4)
+ 80051e8:	2c800417 	ldw	r18,16(r5)
+ 80051ec:	dfc00a15 	stw	ra,40(sp)
+ 80051f0:	df000915 	stw	fp,36(sp)
+ 80051f4:	ddc00815 	stw	r23,32(sp)
+ 80051f8:	dd800715 	stw	r22,28(sp)
+ 80051fc:	dd400615 	stw	r21,24(sp)
+ 8005200:	dd000515 	stw	r20,20(sp)
+ 8005204:	dcc00415 	stw	r19,16(sp)
+ 8005208:	dc400215 	stw	r17,8(sp)
+ 800520c:	dc000115 	stw	r16,4(sp)
+ 8005210:	14807416 	blt	r2,r18,80053e4 <quorem+0x208>
+ 8005214:	94bfffc4 	addi	r18,r18,-1
+ 8005218:	902e90ba 	slli	r23,r18,2
+ 800521c:	2c400504 	addi	r17,r5,20
+ 8005220:	25400504 	addi	r21,r4,20
+ 8005224:	8de9883a 	add	r20,r17,r23
+ 8005228:	a7000017 	ldw	fp,0(r20)
+ 800522c:	adef883a 	add	r23,r21,r23
+ 8005230:	b8c00017 	ldw	r3,0(r23)
+ 8005234:	e7000044 	addi	fp,fp,1
+ 8005238:	282d883a 	mov	r22,r5
+ 800523c:	2021883a 	mov	r16,r4
+ 8005240:	e00b883a 	mov	r5,fp
+ 8005244:	1809883a 	mov	r4,r3
+ 8005248:	d8c00015 	stw	r3,0(sp)
+ 800524c:	800cff80 	call	800cff8 <__udivsi3>
+ 8005250:	d8c00017 	ldw	r3,0(sp)
+ 8005254:	1027883a 	mov	r19,r2
+ 8005258:	1f002c36 	bltu	r3,fp,800530c <quorem+0x130>
+ 800525c:	8811883a 	mov	r8,r17
+ 8005260:	a80b883a 	mov	r5,r21
+ 8005264:	0013883a 	mov	r9,zero
+ 8005268:	0007883a 	mov	r3,zero
+ 800526c:	42000104 	addi	r8,r8,4
+ 8005270:	41ffff17 	ldw	r7,-4(r8)
+ 8005274:	29800017 	ldw	r6,0(r5)
+ 8005278:	29400104 	addi	r5,r5,4
+ 800527c:	38bfffcc 	andi	r2,r7,65535
+ 8005280:	14c5383a 	mul	r2,r2,r19
+ 8005284:	3808d43a 	srli	r4,r7,16
+ 8005288:	32bfffcc 	andi	r10,r6,65535
+ 800528c:	1245883a 	add	r2,r2,r9
+ 8005290:	1012d43a 	srli	r9,r2,16
+ 8005294:	11ffffcc 	andi	r7,r2,65535
+ 8005298:	24c9383a 	mul	r4,r4,r19
+ 800529c:	19c7c83a 	sub	r3,r3,r7
+ 80052a0:	1a8f883a 	add	r7,r3,r10
+ 80052a4:	3006d43a 	srli	r3,r6,16
+ 80052a8:	2249883a 	add	r4,r4,r9
+ 80052ac:	3805d43a 	srai	r2,r7,16
+ 80052b0:	21bfffcc 	andi	r6,r4,65535
+ 80052b4:	1987c83a 	sub	r3,r3,r6
+ 80052b8:	1887883a 	add	r3,r3,r2
+ 80052bc:	180c943a 	slli	r6,r3,16
+ 80052c0:	39ffffcc 	andi	r7,r7,65535
+ 80052c4:	2012d43a 	srli	r9,r4,16
+ 80052c8:	31ceb03a 	or	r7,r6,r7
+ 80052cc:	29ffff15 	stw	r7,-4(r5)
+ 80052d0:	1807d43a 	srai	r3,r3,16
+ 80052d4:	a23fe52e 	bgeu	r20,r8,800526c <quorem+0x90>
+ 80052d8:	b8800017 	ldw	r2,0(r23)
+ 80052dc:	10000b1e 	bne	r2,zero,800530c <quorem+0x130>
+ 80052e0:	b8bfff04 	addi	r2,r23,-4
+ 80052e4:	a880082e 	bgeu	r21,r2,8005308 <quorem+0x12c>
+ 80052e8:	b8ffff17 	ldw	r3,-4(r23)
+ 80052ec:	18000326 	beq	r3,zero,80052fc <quorem+0x120>
+ 80052f0:	00000506 	br	8005308 <quorem+0x12c>
+ 80052f4:	10c00017 	ldw	r3,0(r2)
+ 80052f8:	1800031e 	bne	r3,zero,8005308 <quorem+0x12c>
+ 80052fc:	10bfff04 	addi	r2,r2,-4
+ 8005300:	94bfffc4 	addi	r18,r18,-1
+ 8005304:	a8bffb36 	bltu	r21,r2,80052f4 <quorem+0x118>
+ 8005308:	84800415 	stw	r18,16(r16)
+ 800530c:	b00b883a 	mov	r5,r22
+ 8005310:	8009883a 	mov	r4,r16
+ 8005314:	80092580 	call	8009258 <__mcmp>
+ 8005318:	10002516 	blt	r2,zero,80053b0 <quorem+0x1d4>
+ 800531c:	9cc00044 	addi	r19,r19,1
+ 8005320:	a80d883a 	mov	r6,r21
+ 8005324:	0007883a 	mov	r3,zero
+ 8005328:	8c400104 	addi	r17,r17,4
+ 800532c:	893fff17 	ldw	r4,-4(r17)
+ 8005330:	31400017 	ldw	r5,0(r6)
+ 8005334:	31800104 	addi	r6,r6,4
+ 8005338:	20bfffcc 	andi	r2,r4,65535
+ 800533c:	1887c83a 	sub	r3,r3,r2
+ 8005340:	28bfffcc 	andi	r2,r5,65535
+ 8005344:	1885883a 	add	r2,r3,r2
+ 8005348:	2008d43a 	srli	r4,r4,16
+ 800534c:	2806d43a 	srli	r3,r5,16
+ 8005350:	100fd43a 	srai	r7,r2,16
+ 8005354:	117fffcc 	andi	r5,r2,65535
+ 8005358:	1907c83a 	sub	r3,r3,r4
+ 800535c:	19c7883a 	add	r3,r3,r7
+ 8005360:	1804943a 	slli	r2,r3,16
+ 8005364:	1807d43a 	srai	r3,r3,16
+ 8005368:	1144b03a 	or	r2,r2,r5
+ 800536c:	30bfff15 	stw	r2,-4(r6)
+ 8005370:	a47fed2e 	bgeu	r20,r17,8005328 <quorem+0x14c>
+ 8005374:	900690ba 	slli	r3,r18,2
+ 8005378:	a8c7883a 	add	r3,r21,r3
+ 800537c:	18800017 	ldw	r2,0(r3)
+ 8005380:	10000b1e 	bne	r2,zero,80053b0 <quorem+0x1d4>
+ 8005384:	18bfff04 	addi	r2,r3,-4
+ 8005388:	a880082e 	bgeu	r21,r2,80053ac <quorem+0x1d0>
+ 800538c:	18ffff17 	ldw	r3,-4(r3)
+ 8005390:	18000326 	beq	r3,zero,80053a0 <quorem+0x1c4>
+ 8005394:	00000506 	br	80053ac <quorem+0x1d0>
+ 8005398:	10c00017 	ldw	r3,0(r2)
+ 800539c:	1800031e 	bne	r3,zero,80053ac <quorem+0x1d0>
+ 80053a0:	10bfff04 	addi	r2,r2,-4
+ 80053a4:	94bfffc4 	addi	r18,r18,-1
+ 80053a8:	a8bffb36 	bltu	r21,r2,8005398 <quorem+0x1bc>
+ 80053ac:	84800415 	stw	r18,16(r16)
+ 80053b0:	9805883a 	mov	r2,r19
+ 80053b4:	dfc00a17 	ldw	ra,40(sp)
+ 80053b8:	df000917 	ldw	fp,36(sp)
+ 80053bc:	ddc00817 	ldw	r23,32(sp)
+ 80053c0:	dd800717 	ldw	r22,28(sp)
+ 80053c4:	dd400617 	ldw	r21,24(sp)
+ 80053c8:	dd000517 	ldw	r20,20(sp)
+ 80053cc:	dcc00417 	ldw	r19,16(sp)
+ 80053d0:	dc800317 	ldw	r18,12(sp)
+ 80053d4:	dc400217 	ldw	r17,8(sp)
+ 80053d8:	dc000117 	ldw	r16,4(sp)
+ 80053dc:	dec00b04 	addi	sp,sp,44
+ 80053e0:	f800283a 	ret
+ 80053e4:	0005883a 	mov	r2,zero
+ 80053e8:	003ff206 	br	80053b4 <quorem+0x1d8>
+
+080053ec <_dtoa_r>:
+ 80053ec:	20801017 	ldw	r2,64(r4)
+ 80053f0:	deffe204 	addi	sp,sp,-120
+ 80053f4:	df001c15 	stw	fp,112(sp)
+ 80053f8:	dcc01715 	stw	r19,92(sp)
+ 80053fc:	dc401515 	stw	r17,84(sp)
+ 8005400:	dc001415 	stw	r16,80(sp)
+ 8005404:	dfc01d15 	stw	ra,116(sp)
+ 8005408:	ddc01b15 	stw	r23,108(sp)
+ 800540c:	dd801a15 	stw	r22,104(sp)
+ 8005410:	dd401915 	stw	r21,100(sp)
+ 8005414:	dd001815 	stw	r20,96(sp)
+ 8005418:	dc801615 	stw	r18,88(sp)
+ 800541c:	d9400115 	stw	r5,4(sp)
+ 8005420:	d9c00215 	stw	r7,8(sp)
+ 8005424:	2039883a 	mov	fp,r4
+ 8005428:	3027883a 	mov	r19,r6
+ 800542c:	dc002017 	ldw	r16,128(sp)
+ 8005430:	3023883a 	mov	r17,r6
+ 8005434:	10000826 	beq	r2,zero,8005458 <_dtoa_r+0x6c>
+ 8005438:	21801117 	ldw	r6,68(r4)
+ 800543c:	00c00044 	movi	r3,1
+ 8005440:	100b883a 	mov	r5,r2
+ 8005444:	1986983a 	sll	r3,r3,r6
+ 8005448:	11800115 	stw	r6,4(r2)
+ 800544c:	10c00215 	stw	r3,8(r2)
+ 8005450:	8008a780 	call	8008a78 <_Bfree>
+ 8005454:	e0001015 	stw	zero,64(fp)
+ 8005458:	98018116 	blt	r19,zero,8005a60 <_dtoa_r+0x674>
+ 800545c:	80000015 	stw	zero,0(r16)
+ 8005460:	989ffc2c 	andhi	r2,r19,32752
+ 8005464:	00dffc34 	movhi	r3,32752
+ 8005468:	10c18626 	beq	r2,r3,8005a84 <_dtoa_r+0x698>
+ 800546c:	d9000117 	ldw	r4,4(sp)
+ 8005470:	000d883a 	mov	r6,zero
+ 8005474:	000f883a 	mov	r7,zero
+ 8005478:	880b883a 	mov	r5,r17
+ 800547c:	800e3000 	call	800e300 <__eqdf2>
+ 8005480:	1000191e 	bne	r2,zero,80054e8 <_dtoa_r+0xfc>
+ 8005484:	d8c01f17 	ldw	r3,124(sp)
+ 8005488:	00800044 	movi	r2,1
+ 800548c:	18800015 	stw	r2,0(r3)
+ 8005490:	d8802117 	ldw	r2,132(sp)
+ 8005494:	10032426 	beq	r2,zero,8006128 <_dtoa_r+0xd3c>
+ 8005498:	d9002117 	ldw	r4,132(sp)
+ 800549c:	00820134 	movhi	r2,2052
+ 80054a0:	109d2744 	addi	r2,r2,29853
+ 80054a4:	00c20134 	movhi	r3,2052
+ 80054a8:	20800015 	stw	r2,0(r4)
+ 80054ac:	189d2704 	addi	r2,r3,29852
+ 80054b0:	d8800315 	stw	r2,12(sp)
+ 80054b4:	d8800317 	ldw	r2,12(sp)
+ 80054b8:	dfc01d17 	ldw	ra,116(sp)
+ 80054bc:	df001c17 	ldw	fp,112(sp)
+ 80054c0:	ddc01b17 	ldw	r23,108(sp)
+ 80054c4:	dd801a17 	ldw	r22,104(sp)
+ 80054c8:	dd401917 	ldw	r21,100(sp)
+ 80054cc:	dd001817 	ldw	r20,96(sp)
+ 80054d0:	dcc01717 	ldw	r19,92(sp)
+ 80054d4:	dc801617 	ldw	r18,88(sp)
+ 80054d8:	dc401517 	ldw	r17,84(sp)
+ 80054dc:	dc001417 	ldw	r16,80(sp)
+ 80054e0:	dec01e04 	addi	sp,sp,120
+ 80054e4:	f800283a 	ret
+ 80054e8:	dc800117 	ldw	r18,4(sp)
+ 80054ec:	d8801204 	addi	r2,sp,72
+ 80054f0:	9820d53a 	srli	r16,r19,20
+ 80054f4:	d8800015 	stw	r2,0(sp)
+ 80054f8:	d9c01304 	addi	r7,sp,76
+ 80054fc:	900b883a 	mov	r5,r18
+ 8005500:	880d883a 	mov	r6,r17
+ 8005504:	e009883a 	mov	r4,fp
+ 8005508:	80095cc0 	call	80095cc <__d2b>
+ 800550c:	102b883a 	mov	r21,r2
+ 8005510:	8001701e 	bne	r16,zero,8005ad4 <_dtoa_r+0x6e8>
+ 8005514:	dc801217 	ldw	r18,72(sp)
+ 8005518:	dc001317 	ldw	r16,76(sp)
+ 800551c:	9421883a 	add	r16,r18,r16
+ 8005520:	80810c84 	addi	r2,r16,1074
+ 8005524:	10c00850 	cmplti	r3,r2,33
+ 8005528:	18030f1e 	bne	r3,zero,8006168 <_dtoa_r+0xd7c>
+ 800552c:	01001004 	movi	r4,64
+ 8005530:	2085c83a 	sub	r2,r4,r2
+ 8005534:	98a6983a 	sll	r19,r19,r2
+ 8005538:	d8800117 	ldw	r2,4(sp)
+ 800553c:	81010484 	addi	r4,r16,1042
+ 8005540:	1108d83a 	srl	r4,r2,r4
+ 8005544:	9908b03a 	or	r4,r19,r4
+ 8005548:	800f6f40 	call	800f6f4 <__floatunsidf>
+ 800554c:	1009883a 	mov	r4,r2
+ 8005550:	017f8434 	movhi	r5,65040
+ 8005554:	00800044 	movi	r2,1
+ 8005558:	194b883a 	add	r5,r3,r5
+ 800555c:	843fffc4 	addi	r16,r16,-1
+ 8005560:	d8800a15 	stw	r2,40(sp)
+ 8005564:	000d883a 	mov	r6,zero
+ 8005568:	01cffe34 	movhi	r7,16376
+ 800556c:	800ebec0 	call	800ebec <__subdf3>
+ 8005570:	0198dbf4 	movhi	r6,25455
+ 8005574:	01cff4f4 	movhi	r7,16339
+ 8005578:	3190d844 	addi	r6,r6,17249
+ 800557c:	39e1e9c4 	addi	r7,r7,-30809
+ 8005580:	1009883a 	mov	r4,r2
+ 8005584:	180b883a 	mov	r5,r3
+ 8005588:	800e5600 	call	800e560 <__muldf3>
+ 800558c:	01a2d874 	movhi	r6,35681
+ 8005590:	01cff1f4 	movhi	r7,16327
+ 8005594:	31b22cc4 	addi	r6,r6,-14157
+ 8005598:	39e28a04 	addi	r7,r7,-30168
+ 800559c:	180b883a 	mov	r5,r3
+ 80055a0:	1009883a 	mov	r4,r2
+ 80055a4:	800d0b80 	call	800d0b8 <__adddf3>
+ 80055a8:	8009883a 	mov	r4,r16
+ 80055ac:	1029883a 	mov	r20,r2
+ 80055b0:	1827883a 	mov	r19,r3
+ 80055b4:	800f62c0 	call	800f62c <__floatsidf>
+ 80055b8:	019427f4 	movhi	r6,20639
+ 80055bc:	01cff4f4 	movhi	r7,16339
+ 80055c0:	319e7ec4 	addi	r6,r6,31227
+ 80055c4:	39d104c4 	addi	r7,r7,17427
+ 80055c8:	1009883a 	mov	r4,r2
+ 80055cc:	180b883a 	mov	r5,r3
+ 80055d0:	800e5600 	call	800e560 <__muldf3>
+ 80055d4:	100d883a 	mov	r6,r2
+ 80055d8:	180f883a 	mov	r7,r3
+ 80055dc:	a009883a 	mov	r4,r20
+ 80055e0:	980b883a 	mov	r5,r19
+ 80055e4:	800d0b80 	call	800d0b8 <__adddf3>
+ 80055e8:	1009883a 	mov	r4,r2
+ 80055ec:	180b883a 	mov	r5,r3
+ 80055f0:	1029883a 	mov	r20,r2
+ 80055f4:	1827883a 	mov	r19,r3
+ 80055f8:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 80055fc:	000d883a 	mov	r6,zero
+ 8005600:	000f883a 	mov	r7,zero
+ 8005604:	a009883a 	mov	r4,r20
+ 8005608:	980b883a 	mov	r5,r19
+ 800560c:	102d883a 	mov	r22,r2
+ 8005610:	800e4700 	call	800e470 <__ledf2>
+ 8005614:	1002ba16 	blt	r2,zero,8006100 <_dtoa_r+0xd14>
+ 8005618:	9421c83a 	sub	r16,r18,r16
+ 800561c:	b08005e8 	cmpgeui	r2,r22,23
+ 8005620:	853fffc4 	addi	r20,r16,-1
+ 8005624:	1002ae1e 	bne	r2,zero,80060e0 <_dtoa_r+0xcf4>
+ 8005628:	b00690fa 	slli	r3,r22,3
+ 800562c:	00820134 	movhi	r2,2052
+ 8005630:	109d4b04 	addi	r2,r2,29996
+ 8005634:	10c5883a 	add	r2,r2,r3
+ 8005638:	11800017 	ldw	r6,0(r2)
+ 800563c:	11c00117 	ldw	r7,4(r2)
+ 8005640:	d9000117 	ldw	r4,4(sp)
+ 8005644:	880b883a 	mov	r5,r17
+ 8005648:	800e4700 	call	800e470 <__ledf2>
+ 800564c:	10026f0e 	bge	r2,zero,800600c <_dtoa_r+0xc20>
+ 8005650:	d8000915 	stw	zero,36(sp)
+ 8005654:	b5bfffc4 	addi	r22,r22,-1
+ 8005658:	a002a416 	blt	r20,zero,80060ec <_dtoa_r+0xd00>
+ 800565c:	d8000515 	stw	zero,20(sp)
+ 8005660:	b0026d0e 	bge	r22,zero,8006018 <_dtoa_r+0xc2c>
+ 8005664:	d8800517 	ldw	r2,20(sp)
+ 8005668:	d8c00217 	ldw	r3,8(sp)
+ 800566c:	dd800415 	stw	r22,16(sp)
+ 8005670:	1585c83a 	sub	r2,r2,r22
+ 8005674:	d8800515 	stw	r2,20(sp)
+ 8005678:	0585c83a 	sub	r2,zero,r22
+ 800567c:	d8800815 	stw	r2,32(sp)
+ 8005680:	188002a8 	cmpgeui	r2,r3,10
+ 8005684:	002d883a 	mov	r22,zero
+ 8005688:	1002691e 	bne	r2,zero,8006030 <_dtoa_r+0xc44>
+ 800568c:	18800190 	cmplti	r2,r3,6
+ 8005690:	1002ba1e 	bne	r2,zero,800617c <_dtoa_r+0xd90>
+ 8005694:	18bfff04 	addi	r2,r3,-4
+ 8005698:	d8800215 	stw	r2,8(sp)
+ 800569c:	0021883a 	mov	r16,zero
+ 80056a0:	d8c00217 	ldw	r3,8(sp)
+ 80056a4:	188000e0 	cmpeqi	r2,r3,3
+ 80056a8:	10039d1e 	bne	r2,zero,8006520 <_dtoa_r+0x1134>
+ 80056ac:	18800108 	cmpgei	r2,r3,4
+ 80056b0:	10027a26 	beq	r2,zero,800609c <_dtoa_r+0xcb0>
+ 80056b4:	d8c00217 	ldw	r3,8(sp)
+ 80056b8:	18800120 	cmpeqi	r2,r3,4
+ 80056bc:	10026926 	beq	r2,zero,8006064 <_dtoa_r+0xc78>
+ 80056c0:	00800044 	movi	r2,1
+ 80056c4:	d8800715 	stw	r2,28(sp)
+ 80056c8:	d8801e17 	ldw	r2,120(sp)
+ 80056cc:	0083670e 	bge	zero,r2,800646c <_dtoa_r+0x1080>
+ 80056d0:	d8800b15 	stw	r2,44(sp)
+ 80056d4:	d8800615 	stw	r2,24(sp)
+ 80056d8:	100d883a 	mov	r6,r2
+ 80056dc:	e0001115 	stw	zero,68(fp)
+ 80056e0:	30800610 	cmplti	r2,r6,24
+ 80056e4:	dc800617 	ldw	r18,24(sp)
+ 80056e8:	1004eb1e 	bne	r2,zero,8006a98 <_dtoa_r+0x16ac>
+ 80056ec:	00c00044 	movi	r3,1
+ 80056f0:	00800104 	movi	r2,4
+ 80056f4:	1085883a 	add	r2,r2,r2
+ 80056f8:	11000504 	addi	r4,r2,20
+ 80056fc:	180b883a 	mov	r5,r3
+ 8005700:	18c00044 	addi	r3,r3,1
+ 8005704:	313ffb2e 	bgeu	r6,r4,80056f4 <_dtoa_r+0x308>
+ 8005708:	e1401115 	stw	r5,68(fp)
+ 800570c:	e009883a 	mov	r4,fp
+ 8005710:	80089d40 	call	80089d4 <_Balloc>
+ 8005714:	d8800315 	stw	r2,12(sp)
+ 8005718:	e0801015 	stw	r2,64(fp)
+ 800571c:	948003e8 	cmpgeui	r18,r18,15
+ 8005720:	9000fe1e 	bne	r18,zero,8005b1c <_dtoa_r+0x730>
+ 8005724:	8000fd26 	beq	r16,zero,8005b1c <_dtoa_r+0x730>
+ 8005728:	d9000417 	ldw	r4,16(sp)
+ 800572c:	0103c60e 	bge	zero,r4,8006648 <_dtoa_r+0x125c>
+ 8005730:	208003cc 	andi	r2,r4,15
+ 8005734:	100690fa 	slli	r3,r2,3
+ 8005738:	202fd13a 	srai	r23,r4,4
+ 800573c:	00820134 	movhi	r2,2052
+ 8005740:	109d4b04 	addi	r2,r2,29996
+ 8005744:	10c5883a 	add	r2,r2,r3
+ 8005748:	b8c0040c 	andi	r3,r23,16
+ 800574c:	12800017 	ldw	r10,0(r2)
+ 8005750:	12400117 	ldw	r9,4(r2)
+ 8005754:	1803621e 	bne	r3,zero,80064e0 <_dtoa_r+0x10f4>
+ 8005758:	d8800117 	ldw	r2,4(sp)
+ 800575c:	8827883a 	mov	r19,r17
+ 8005760:	04000084 	movi	r16,2
+ 8005764:	d8800c15 	stw	r2,48(sp)
+ 8005768:	04820134 	movhi	r18,2052
+ 800576c:	949d4104 	addi	r18,r18,29956
+ 8005770:	b8000f26 	beq	r23,zero,80057b0 <_dtoa_r+0x3c4>
+ 8005774:	5005883a 	mov	r2,r10
+ 8005778:	4807883a 	mov	r3,r9
+ 800577c:	b980004c 	andi	r6,r23,1
+ 8005780:	1009883a 	mov	r4,r2
+ 8005784:	b82fd07a 	srai	r23,r23,1
+ 8005788:	180b883a 	mov	r5,r3
+ 800578c:	30000426 	beq	r6,zero,80057a0 <_dtoa_r+0x3b4>
+ 8005790:	91800017 	ldw	r6,0(r18)
+ 8005794:	91c00117 	ldw	r7,4(r18)
+ 8005798:	84000044 	addi	r16,r16,1
+ 800579c:	800e5600 	call	800e560 <__muldf3>
+ 80057a0:	94800204 	addi	r18,r18,8
+ 80057a4:	b83ff51e 	bne	r23,zero,800577c <_dtoa_r+0x390>
+ 80057a8:	1015883a 	mov	r10,r2
+ 80057ac:	1813883a 	mov	r9,r3
+ 80057b0:	d9000c17 	ldw	r4,48(sp)
+ 80057b4:	980b883a 	mov	r5,r19
+ 80057b8:	500d883a 	mov	r6,r10
+ 80057bc:	480f883a 	mov	r7,r9
+ 80057c0:	800da580 	call	800da58 <__divdf3>
+ 80057c4:	1025883a 	mov	r18,r2
+ 80057c8:	1827883a 	mov	r19,r3
+ 80057cc:	d8800917 	ldw	r2,36(sp)
+ 80057d0:	10000626 	beq	r2,zero,80057ec <_dtoa_r+0x400>
+ 80057d4:	000d883a 	mov	r6,zero
+ 80057d8:	01cffc34 	movhi	r7,16368
+ 80057dc:	9009883a 	mov	r4,r18
+ 80057e0:	980b883a 	mov	r5,r19
+ 80057e4:	800e4700 	call	800e470 <__ledf2>
+ 80057e8:	10042616 	blt	r2,zero,8006884 <_dtoa_r+0x1498>
+ 80057ec:	8009883a 	mov	r4,r16
+ 80057f0:	800f62c0 	call	800f62c <__floatsidf>
+ 80057f4:	900d883a 	mov	r6,r18
+ 80057f8:	980f883a 	mov	r7,r19
+ 80057fc:	1009883a 	mov	r4,r2
+ 8005800:	180b883a 	mov	r5,r3
+ 8005804:	800e5600 	call	800e560 <__muldf3>
+ 8005808:	000d883a 	mov	r6,zero
+ 800580c:	01d00734 	movhi	r7,16412
+ 8005810:	1009883a 	mov	r4,r2
+ 8005814:	180b883a 	mov	r5,r3
+ 8005818:	800d0b80 	call	800d0b8 <__adddf3>
+ 800581c:	d8800c15 	stw	r2,48(sp)
+ 8005820:	00bf3034 	movhi	r2,64704
+ 8005824:	1885883a 	add	r2,r3,r2
+ 8005828:	d8800d15 	stw	r2,52(sp)
+ 800582c:	d8800617 	ldw	r2,24(sp)
+ 8005830:	10036d26 	beq	r2,zero,80065e8 <_dtoa_r+0x11fc>
+ 8005834:	d8800417 	ldw	r2,16(sp)
+ 8005838:	d8800f15 	stw	r2,60(sp)
+ 800583c:	d8800617 	ldw	r2,24(sp)
+ 8005840:	d8800e15 	stw	r2,56(sp)
+ 8005844:	980b883a 	mov	r5,r19
+ 8005848:	9009883a 	mov	r4,r18
+ 800584c:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 8005850:	1009883a 	mov	r4,r2
+ 8005854:	102f883a 	mov	r23,r2
+ 8005858:	800f62c0 	call	800f62c <__floatsidf>
+ 800585c:	100d883a 	mov	r6,r2
+ 8005860:	180f883a 	mov	r7,r3
+ 8005864:	9009883a 	mov	r4,r18
+ 8005868:	980b883a 	mov	r5,r19
+ 800586c:	800ebec0 	call	800ebec <__subdf3>
+ 8005870:	1025883a 	mov	r18,r2
+ 8005874:	d8800e17 	ldw	r2,56(sp)
+ 8005878:	1821883a 	mov	r16,r3
+ 800587c:	ba400c04 	addi	r9,r23,48
+ 8005880:	10bfffc4 	addi	r2,r2,-1
+ 8005884:	100690fa 	slli	r3,r2,3
+ 8005888:	00820134 	movhi	r2,2052
+ 800588c:	109d4b04 	addi	r2,r2,29996
+ 8005890:	10c5883a 	add	r2,r2,r3
+ 8005894:	11800017 	ldw	r6,0(r2)
+ 8005898:	d8c00317 	ldw	r3,12(sp)
+ 800589c:	11c00117 	ldw	r7,4(r2)
+ 80058a0:	d8800717 	ldw	r2,28(sp)
+ 80058a4:	4811883a 	mov	r8,r9
+ 80058a8:	da001015 	stw	r8,64(sp)
+ 80058ac:	1dc00044 	addi	r23,r3,1
+ 80058b0:	1003a226 	beq	r2,zero,800673c <_dtoa_r+0x1350>
+ 80058b4:	0009883a 	mov	r4,zero
+ 80058b8:	014ff834 	movhi	r5,16352
+ 80058bc:	da401115 	stw	r9,68(sp)
+ 80058c0:	800da580 	call	800da58 <__divdf3>
+ 80058c4:	d9800c17 	ldw	r6,48(sp)
+ 80058c8:	d9c00d17 	ldw	r7,52(sp)
+ 80058cc:	1009883a 	mov	r4,r2
+ 80058d0:	180b883a 	mov	r5,r3
+ 80058d4:	800ebec0 	call	800ebec <__subdf3>
+ 80058d8:	1827883a 	mov	r19,r3
+ 80058dc:	da401117 	ldw	r9,68(sp)
+ 80058e0:	d8c00317 	ldw	r3,12(sp)
+ 80058e4:	900d883a 	mov	r6,r18
+ 80058e8:	800f883a 	mov	r7,r16
+ 80058ec:	1a400005 	stb	r9,0(r3)
+ 80058f0:	1009883a 	mov	r4,r2
+ 80058f4:	980b883a 	mov	r5,r19
+ 80058f8:	d8800c15 	stw	r2,48(sp)
+ 80058fc:	800e3800 	call	800e380 <__gedf2>
+ 8005900:	da001017 	ldw	r8,64(sp)
+ 8005904:	00804816 	blt	zero,r2,8005a28 <_dtoa_r+0x63c>
+ 8005908:	900d883a 	mov	r6,r18
+ 800590c:	800f883a 	mov	r7,r16
+ 8005910:	0009883a 	mov	r4,zero
+ 8005914:	014ffc34 	movhi	r5,16368
+ 8005918:	da000d15 	stw	r8,52(sp)
+ 800591c:	800ebec0 	call	800ebec <__subdf3>
+ 8005920:	d9000c17 	ldw	r4,48(sp)
+ 8005924:	100d883a 	mov	r6,r2
+ 8005928:	180f883a 	mov	r7,r3
+ 800592c:	980b883a 	mov	r5,r19
+ 8005930:	800e3800 	call	800e380 <__gedf2>
+ 8005934:	da000d17 	ldw	r8,52(sp)
+ 8005938:	00844e16 	blt	zero,r2,8006a74 <_dtoa_r+0x1688>
+ 800593c:	d8c00e17 	ldw	r3,56(sp)
+ 8005940:	18800060 	cmpeqi	r2,r3,1
+ 8005944:	1000751e 	bne	r2,zero,8005b1c <_dtoa_r+0x730>
+ 8005948:	d8800317 	ldw	r2,12(sp)
+ 800594c:	dd800d15 	stw	r22,52(sp)
+ 8005950:	dd000e15 	stw	r20,56(sp)
+ 8005954:	10c5883a 	add	r2,r2,r3
+ 8005958:	dd000c17 	ldw	r20,48(sp)
+ 800595c:	102d883a 	mov	r22,r2
+ 8005960:	dc400c15 	stw	r17,48(sp)
+ 8005964:	00000806 	br	8005988 <_dtoa_r+0x59c>
+ 8005968:	800ebec0 	call	800ebec <__subdf3>
+ 800596c:	a00d883a 	mov	r6,r20
+ 8005970:	980f883a 	mov	r7,r19
+ 8005974:	1009883a 	mov	r4,r2
+ 8005978:	180b883a 	mov	r5,r3
+ 800597c:	800e4700 	call	800e470 <__ledf2>
+ 8005980:	10042316 	blt	r2,zero,8006a10 <_dtoa_r+0x1624>
+ 8005984:	bd806226 	beq	r23,r22,8005b10 <_dtoa_r+0x724>
+ 8005988:	a009883a 	mov	r4,r20
+ 800598c:	980b883a 	mov	r5,r19
+ 8005990:	000d883a 	mov	r6,zero
+ 8005994:	01d00934 	movhi	r7,16420
+ 8005998:	800e5600 	call	800e560 <__muldf3>
+ 800599c:	000d883a 	mov	r6,zero
+ 80059a0:	01d00934 	movhi	r7,16420
+ 80059a4:	9009883a 	mov	r4,r18
+ 80059a8:	800b883a 	mov	r5,r16
+ 80059ac:	1029883a 	mov	r20,r2
+ 80059b0:	1827883a 	mov	r19,r3
+ 80059b4:	800e5600 	call	800e560 <__muldf3>
+ 80059b8:	180b883a 	mov	r5,r3
+ 80059bc:	1009883a 	mov	r4,r2
+ 80059c0:	1821883a 	mov	r16,r3
+ 80059c4:	1025883a 	mov	r18,r2
+ 80059c8:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 80059cc:	1009883a 	mov	r4,r2
+ 80059d0:	1023883a 	mov	r17,r2
+ 80059d4:	800f62c0 	call	800f62c <__floatsidf>
+ 80059d8:	9009883a 	mov	r4,r18
+ 80059dc:	800b883a 	mov	r5,r16
+ 80059e0:	100d883a 	mov	r6,r2
+ 80059e4:	180f883a 	mov	r7,r3
+ 80059e8:	800ebec0 	call	800ebec <__subdf3>
+ 80059ec:	bdc00044 	addi	r23,r23,1
+ 80059f0:	8c400c04 	addi	r17,r17,48
+ 80059f4:	a00d883a 	mov	r6,r20
+ 80059f8:	980f883a 	mov	r7,r19
+ 80059fc:	1009883a 	mov	r4,r2
+ 8005a00:	180b883a 	mov	r5,r3
+ 8005a04:	bc7fffc5 	stb	r17,-1(r23)
+ 8005a08:	1025883a 	mov	r18,r2
+ 8005a0c:	1821883a 	mov	r16,r3
+ 8005a10:	800e4700 	call	800e470 <__ledf2>
+ 8005a14:	900d883a 	mov	r6,r18
+ 8005a18:	800f883a 	mov	r7,r16
+ 8005a1c:	0009883a 	mov	r4,zero
+ 8005a20:	014ffc34 	movhi	r5,16368
+ 8005a24:	103fd00e 	bge	r2,zero,8005968 <_dtoa_r+0x57c>
+ 8005a28:	d8800f17 	ldw	r2,60(sp)
+ 8005a2c:	10800044 	addi	r2,r2,1
+ 8005a30:	d8800415 	stw	r2,16(sp)
+ 8005a34:	a80b883a 	mov	r5,r21
+ 8005a38:	e009883a 	mov	r4,fp
+ 8005a3c:	8008a780 	call	8008a78 <_Bfree>
+ 8005a40:	d8801f17 	ldw	r2,124(sp)
+ 8005a44:	d8c00417 	ldw	r3,16(sp)
+ 8005a48:	b8000005 	stb	zero,0(r23)
+ 8005a4c:	10c00015 	stw	r3,0(r2)
+ 8005a50:	d8802117 	ldw	r2,132(sp)
+ 8005a54:	103e9726 	beq	r2,zero,80054b4 <_dtoa_r+0xc8>
+ 8005a58:	15c00015 	stw	r23,0(r2)
+ 8005a5c:	003e9506 	br	80054b4 <_dtoa_r+0xc8>
+ 8005a60:	04600034 	movhi	r17,32768
+ 8005a64:	8c7fffc4 	addi	r17,r17,-1
+ 8005a68:	9c62703a 	and	r17,r19,r17
+ 8005a6c:	00800044 	movi	r2,1
+ 8005a70:	8827883a 	mov	r19,r17
+ 8005a74:	80800015 	stw	r2,0(r16)
+ 8005a78:	00dffc34 	movhi	r3,32752
+ 8005a7c:	989ffc2c 	andhi	r2,r19,32752
+ 8005a80:	10fe7a1e 	bne	r2,r3,800546c <_dtoa_r+0x80>
+ 8005a84:	00800434 	movhi	r2,16
+ 8005a88:	d8c01f17 	ldw	r3,124(sp)
+ 8005a8c:	10bfffc4 	addi	r2,r2,-1
+ 8005a90:	98a6703a 	and	r19,r19,r2
+ 8005a94:	0089c3c4 	movi	r2,9999
+ 8005a98:	18800015 	stw	r2,0(r3)
+ 8005a9c:	d8800117 	ldw	r2,4(sp)
+ 8005aa0:	98aab03a 	or	r21,r19,r2
+ 8005aa4:	a800141e 	bne	r21,zero,8005af8 <_dtoa_r+0x70c>
+ 8005aa8:	d8802117 	ldw	r2,132(sp)
+ 8005aac:	1003f626 	beq	r2,zero,8006a88 <_dtoa_r+0x169c>
+ 8005ab0:	00820134 	movhi	r2,2052
+ 8005ab4:	1007883a 	mov	r3,r2
+ 8005ab8:	18dd3104 	addi	r3,r3,29892
+ 8005abc:	00820134 	movhi	r2,2052
+ 8005ac0:	d8c00315 	stw	r3,12(sp)
+ 8005ac4:	109d3304 	addi	r2,r2,29900
+ 8005ac8:	d8c02117 	ldw	r3,132(sp)
+ 8005acc:	18800015 	stw	r2,0(r3)
+ 8005ad0:	003e7806 	br	80054b4 <_dtoa_r+0xc8>
+ 8005ad4:	01400434 	movhi	r5,16
+ 8005ad8:	297fffc4 	addi	r5,r5,-1
+ 8005adc:	894a703a 	and	r5,r17,r5
+ 8005ae0:	9009883a 	mov	r4,r18
+ 8005ae4:	294ffc34 	orhi	r5,r5,16368
+ 8005ae8:	843f0044 	addi	r16,r16,-1023
+ 8005aec:	dc801217 	ldw	r18,72(sp)
+ 8005af0:	d8000a15 	stw	zero,40(sp)
+ 8005af4:	003e9b06 	br	8005564 <_dtoa_r+0x178>
+ 8005af8:	d8802117 	ldw	r2,132(sp)
+ 8005afc:	1002461e 	bne	r2,zero,8006418 <_dtoa_r+0x102c>
+ 8005b00:	00820134 	movhi	r2,2052
+ 8005b04:	109d3004 	addi	r2,r2,29888
+ 8005b08:	d8800315 	stw	r2,12(sp)
+ 8005b0c:	003e6906 	br	80054b4 <_dtoa_r+0xc8>
+ 8005b10:	dd800d17 	ldw	r22,52(sp)
+ 8005b14:	dd000e17 	ldw	r20,56(sp)
+ 8005b18:	dc400c17 	ldw	r17,48(sp)
+ 8005b1c:	d8801317 	ldw	r2,76(sp)
+ 8005b20:	10009f16 	blt	r2,zero,8005da0 <_dtoa_r+0x9b4>
+ 8005b24:	d9000417 	ldw	r4,16(sp)
+ 8005b28:	20c003c8 	cmpgei	r3,r4,15
+ 8005b2c:	18009c1e 	bne	r3,zero,8005da0 <_dtoa_r+0x9b4>
+ 8005b30:	200690fa 	slli	r3,r4,3
+ 8005b34:	00820134 	movhi	r2,2052
+ 8005b38:	109d4b04 	addi	r2,r2,29996
+ 8005b3c:	10c5883a 	add	r2,r2,r3
+ 8005b40:	14000017 	ldw	r16,0(r2)
+ 8005b44:	14800117 	ldw	r18,4(r2)
+ 8005b48:	d8801e17 	ldw	r2,120(sp)
+ 8005b4c:	1000140e 	bge	r2,zero,8005ba0 <_dtoa_r+0x7b4>
+ 8005b50:	d8800617 	ldw	r2,24(sp)
+ 8005b54:	00801216 	blt	zero,r2,8005ba0 <_dtoa_r+0x7b4>
+ 8005b58:	1002b81e 	bne	r2,zero,800663c <_dtoa_r+0x1250>
+ 8005b5c:	8009883a 	mov	r4,r16
+ 8005b60:	900b883a 	mov	r5,r18
+ 8005b64:	000d883a 	mov	r6,zero
+ 8005b68:	01d00534 	movhi	r7,16404
+ 8005b6c:	800e5600 	call	800e560 <__muldf3>
+ 8005b70:	d9800117 	ldw	r6,4(sp)
+ 8005b74:	880f883a 	mov	r7,r17
+ 8005b78:	1009883a 	mov	r4,r2
+ 8005b7c:	180b883a 	mov	r5,r3
+ 8005b80:	800e3800 	call	800e380 <__gedf2>
+ 8005b84:	0025883a 	mov	r18,zero
+ 8005b88:	0021883a 	mov	r16,zero
+ 8005b8c:	1001fd16 	blt	r2,zero,8006384 <_dtoa_r+0xf98>
+ 8005b90:	d8801e17 	ldw	r2,120(sp)
+ 8005b94:	ddc00317 	ldw	r23,12(sp)
+ 8005b98:	00a2303a 	nor	r17,zero,r2
+ 8005b9c:	0001ff06 	br	800639c <_dtoa_r+0xfb0>
+ 8005ba0:	dcc00117 	ldw	r19,4(sp)
+ 8005ba4:	800d883a 	mov	r6,r16
+ 8005ba8:	900f883a 	mov	r7,r18
+ 8005bac:	880b883a 	mov	r5,r17
+ 8005bb0:	9809883a 	mov	r4,r19
+ 8005bb4:	800da580 	call	800da58 <__divdf3>
+ 8005bb8:	180b883a 	mov	r5,r3
+ 8005bbc:	1009883a 	mov	r4,r2
+ 8005bc0:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 8005bc4:	1009883a 	mov	r4,r2
+ 8005bc8:	102d883a 	mov	r22,r2
+ 8005bcc:	800f62c0 	call	800f62c <__floatsidf>
+ 8005bd0:	800d883a 	mov	r6,r16
+ 8005bd4:	900f883a 	mov	r7,r18
+ 8005bd8:	1009883a 	mov	r4,r2
+ 8005bdc:	180b883a 	mov	r5,r3
+ 8005be0:	800e5600 	call	800e560 <__muldf3>
+ 8005be4:	880b883a 	mov	r5,r17
+ 8005be8:	100d883a 	mov	r6,r2
+ 8005bec:	180f883a 	mov	r7,r3
+ 8005bf0:	9809883a 	mov	r4,r19
+ 8005bf4:	800ebec0 	call	800ebec <__subdf3>
+ 8005bf8:	dc400317 	ldw	r17,12(sp)
+ 8005bfc:	1009883a 	mov	r4,r2
+ 8005c00:	d9c00417 	ldw	r7,16(sp)
+ 8005c04:	b0800c04 	addi	r2,r22,48
+ 8005c08:	88800005 	stb	r2,0(r17)
+ 8005c0c:	d8800617 	ldw	r2,24(sp)
+ 8005c10:	39c00044 	addi	r7,r7,1
+ 8005c14:	d9c00415 	stw	r7,16(sp)
+ 8005c18:	11800060 	cmpeqi	r6,r2,1
+ 8005c1c:	180b883a 	mov	r5,r3
+ 8005c20:	2005883a 	mov	r2,r4
+ 8005c24:	8dc00044 	addi	r23,r17,1
+ 8005c28:	3000391e 	bne	r6,zero,8005d10 <_dtoa_r+0x924>
+ 8005c2c:	01d00934 	movhi	r7,16420
+ 8005c30:	800e5600 	call	800e560 <__muldf3>
+ 8005c34:	000d883a 	mov	r6,zero
+ 8005c38:	000f883a 	mov	r7,zero
+ 8005c3c:	1009883a 	mov	r4,r2
+ 8005c40:	180b883a 	mov	r5,r3
+ 8005c44:	1027883a 	mov	r19,r2
+ 8005c48:	1829883a 	mov	r20,r3
+ 8005c4c:	800e3000 	call	800e300 <__eqdf2>
+ 8005c50:	103f7826 	beq	r2,zero,8005a34 <_dtoa_r+0x648>
+ 8005c54:	d8c00617 	ldw	r3,24(sp)
+ 8005c58:	8805883a 	mov	r2,r17
+ 8005c5c:	dd400115 	stw	r21,4(sp)
+ 8005c60:	8c400084 	addi	r17,r17,2
+ 8005c64:	10ed883a 	add	r22,r2,r3
+ 8005c68:	00000a06 	br	8005c94 <_dtoa_r+0x8a8>
+ 8005c6c:	800e5600 	call	800e560 <__muldf3>
+ 8005c70:	000d883a 	mov	r6,zero
+ 8005c74:	000f883a 	mov	r7,zero
+ 8005c78:	1009883a 	mov	r4,r2
+ 8005c7c:	180b883a 	mov	r5,r3
+ 8005c80:	1027883a 	mov	r19,r2
+ 8005c84:	1829883a 	mov	r20,r3
+ 8005c88:	8c400044 	addi	r17,r17,1
+ 8005c8c:	800e3000 	call	800e300 <__eqdf2>
+ 8005c90:	10029d26 	beq	r2,zero,8006708 <_dtoa_r+0x131c>
+ 8005c94:	800d883a 	mov	r6,r16
+ 8005c98:	900f883a 	mov	r7,r18
+ 8005c9c:	9809883a 	mov	r4,r19
+ 8005ca0:	a00b883a 	mov	r5,r20
+ 8005ca4:	800da580 	call	800da58 <__divdf3>
+ 8005ca8:	180b883a 	mov	r5,r3
+ 8005cac:	1009883a 	mov	r4,r2
+ 8005cb0:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 8005cb4:	1009883a 	mov	r4,r2
+ 8005cb8:	102b883a 	mov	r21,r2
+ 8005cbc:	800f62c0 	call	800f62c <__floatsidf>
+ 8005cc0:	800d883a 	mov	r6,r16
+ 8005cc4:	900f883a 	mov	r7,r18
+ 8005cc8:	1009883a 	mov	r4,r2
+ 8005ccc:	180b883a 	mov	r5,r3
+ 8005cd0:	800e5600 	call	800e560 <__muldf3>
+ 8005cd4:	100d883a 	mov	r6,r2
+ 8005cd8:	180f883a 	mov	r7,r3
+ 8005cdc:	9809883a 	mov	r4,r19
+ 8005ce0:	a00b883a 	mov	r5,r20
+ 8005ce4:	800ebec0 	call	800ebec <__subdf3>
+ 8005ce8:	aa400c04 	addi	r9,r21,48
+ 8005cec:	8a7fffc5 	stb	r9,-1(r17)
+ 8005cf0:	000d883a 	mov	r6,zero
+ 8005cf4:	01d00934 	movhi	r7,16420
+ 8005cf8:	1009883a 	mov	r4,r2
+ 8005cfc:	180b883a 	mov	r5,r3
+ 8005d00:	882f883a 	mov	r23,r17
+ 8005d04:	b47fd91e 	bne	r22,r17,8005c6c <_dtoa_r+0x880>
+ 8005d08:	a82d883a 	mov	r22,r21
+ 8005d0c:	dd400117 	ldw	r21,4(sp)
+ 8005d10:	100d883a 	mov	r6,r2
+ 8005d14:	180f883a 	mov	r7,r3
+ 8005d18:	1009883a 	mov	r4,r2
+ 8005d1c:	180b883a 	mov	r5,r3
+ 8005d20:	800d0b80 	call	800d0b8 <__adddf3>
+ 8005d24:	800d883a 	mov	r6,r16
+ 8005d28:	900f883a 	mov	r7,r18
+ 8005d2c:	1009883a 	mov	r4,r2
+ 8005d30:	180b883a 	mov	r5,r3
+ 8005d34:	1027883a 	mov	r19,r2
+ 8005d38:	1823883a 	mov	r17,r3
+ 8005d3c:	800e3800 	call	800e380 <__gedf2>
+ 8005d40:	00800816 	blt	zero,r2,8005d64 <_dtoa_r+0x978>
+ 8005d44:	800d883a 	mov	r6,r16
+ 8005d48:	900f883a 	mov	r7,r18
+ 8005d4c:	9809883a 	mov	r4,r19
+ 8005d50:	880b883a 	mov	r5,r17
+ 8005d54:	800e3000 	call	800e300 <__eqdf2>
+ 8005d58:	103f361e 	bne	r2,zero,8005a34 <_dtoa_r+0x648>
+ 8005d5c:	b580004c 	andi	r22,r22,1
+ 8005d60:	b03f3426 	beq	r22,zero,8005a34 <_dtoa_r+0x648>
+ 8005d64:	ba3fffc3 	ldbu	r8,-1(r23)
+ 8005d68:	d9000317 	ldw	r4,12(sp)
+ 8005d6c:	00000306 	br	8005d7c <_dtoa_r+0x990>
+ 8005d70:	20c30e26 	beq	r4,r3,80069ac <_dtoa_r+0x15c0>
+ 8005d74:	1a3fffc3 	ldbu	r8,-1(r3)
+ 8005d78:	182f883a 	mov	r23,r3
+ 8005d7c:	40803fcc 	andi	r2,r8,255
+ 8005d80:	1080201c 	xori	r2,r2,128
+ 8005d84:	10bfe004 	addi	r2,r2,-128
+ 8005d88:	10800e60 	cmpeqi	r2,r2,57
+ 8005d8c:	b8ffffc4 	addi	r3,r23,-1
+ 8005d90:	103ff71e 	bne	r2,zero,8005d70 <_dtoa_r+0x984>
+ 8005d94:	42000044 	addi	r8,r8,1
+ 8005d98:	1a000005 	stb	r8,0(r3)
+ 8005d9c:	003f2506 	br	8005a34 <_dtoa_r+0x648>
+ 8005da0:	d8c00717 	ldw	r3,28(sp)
+ 8005da4:	1800e426 	beq	r3,zero,8006138 <_dtoa_r+0xd4c>
+ 8005da8:	d8c00217 	ldw	r3,8(sp)
+ 8005dac:	18c00088 	cmpgei	r3,r3,2
+ 8005db0:	1801ec26 	beq	r3,zero,8006564 <_dtoa_r+0x1178>
+ 8005db4:	d8800617 	ldw	r2,24(sp)
+ 8005db8:	14bfffc4 	addi	r18,r2,-1
+ 8005dbc:	d8800817 	ldw	r2,32(sp)
+ 8005dc0:	1481c50e 	bge	r2,r18,80064d8 <_dtoa_r+0x10ec>
+ 8005dc4:	d8800817 	ldw	r2,32(sp)
+ 8005dc8:	dc800815 	stw	r18,32(sp)
+ 8005dcc:	9085c83a 	sub	r2,r18,r2
+ 8005dd0:	b0ad883a 	add	r22,r22,r2
+ 8005dd4:	0025883a 	mov	r18,zero
+ 8005dd8:	d8800617 	ldw	r2,24(sp)
+ 8005ddc:	10024c16 	blt	r2,zero,8006710 <_dtoa_r+0x1324>
+ 8005de0:	d8c00517 	ldw	r3,20(sp)
+ 8005de4:	a0a9883a 	add	r20,r20,r2
+ 8005de8:	1885883a 	add	r2,r3,r2
+ 8005dec:	1827883a 	mov	r19,r3
+ 8005df0:	d8800515 	stw	r2,20(sp)
+ 8005df4:	01400044 	movi	r5,1
+ 8005df8:	e009883a 	mov	r4,fp
+ 8005dfc:	8008dd40 	call	8008dd4 <__i2b>
+ 8005e00:	1021883a 	mov	r16,r2
+ 8005e04:	04c0080e 	bge	zero,r19,8005e28 <_dtoa_r+0xa3c>
+ 8005e08:	0500070e 	bge	zero,r20,8005e28 <_dtoa_r+0xa3c>
+ 8005e0c:	9805883a 	mov	r2,r19
+ 8005e10:	a4c1a916 	blt	r20,r19,80064b8 <_dtoa_r+0x10cc>
+ 8005e14:	d8c00517 	ldw	r3,20(sp)
+ 8005e18:	98a7c83a 	sub	r19,r19,r2
+ 8005e1c:	a0a9c83a 	sub	r20,r20,r2
+ 8005e20:	1887c83a 	sub	r3,r3,r2
+ 8005e24:	d8c00515 	stw	r3,20(sp)
+ 8005e28:	d8800817 	ldw	r2,32(sp)
+ 8005e2c:	10001426 	beq	r2,zero,8005e80 <_dtoa_r+0xa94>
+ 8005e30:	d8800717 	ldw	r2,28(sp)
+ 8005e34:	10017226 	beq	r2,zero,8006400 <_dtoa_r+0x1014>
+ 8005e38:	04800e0e 	bge	zero,r18,8005e74 <_dtoa_r+0xa88>
+ 8005e3c:	800b883a 	mov	r5,r16
+ 8005e40:	900d883a 	mov	r6,r18
+ 8005e44:	e009883a 	mov	r4,fp
+ 8005e48:	8008ff40 	call	8008ff4 <__pow5mult>
+ 8005e4c:	a80d883a 	mov	r6,r21
+ 8005e50:	100b883a 	mov	r5,r2
+ 8005e54:	e009883a 	mov	r4,fp
+ 8005e58:	1021883a 	mov	r16,r2
+ 8005e5c:	8008e080 	call	8008e08 <__multiply>
+ 8005e60:	102f883a 	mov	r23,r2
+ 8005e64:	a80b883a 	mov	r5,r21
+ 8005e68:	e009883a 	mov	r4,fp
+ 8005e6c:	8008a780 	call	8008a78 <_Bfree>
+ 8005e70:	b82b883a 	mov	r21,r23
+ 8005e74:	d8800817 	ldw	r2,32(sp)
+ 8005e78:	148dc83a 	sub	r6,r2,r18
+ 8005e7c:	3001611e 	bne	r6,zero,8006404 <_dtoa_r+0x1018>
+ 8005e80:	01400044 	movi	r5,1
+ 8005e84:	e009883a 	mov	r4,fp
+ 8005e88:	8008dd40 	call	8008dd4 <__i2b>
+ 8005e8c:	1025883a 	mov	r18,r2
+ 8005e90:	0580bc16 	blt	zero,r22,8006184 <_dtoa_r+0xd98>
+ 8005e94:	d8800217 	ldw	r2,8(sp)
+ 8005e98:	10800088 	cmpgei	r2,r2,2
+ 8005e9c:	10016526 	beq	r2,zero,8006434 <_dtoa_r+0x1048>
+ 8005ea0:	0023883a 	mov	r17,zero
+ 8005ea4:	00800044 	movi	r2,1
+ 8005ea8:	b000bf1e 	bne	r22,zero,80061a8 <_dtoa_r+0xdbc>
+ 8005eac:	1505883a 	add	r2,r2,r20
+ 8005eb0:	108007cc 	andi	r2,r2,31
+ 8005eb4:	1000aa26 	beq	r2,zero,8006160 <_dtoa_r+0xd74>
+ 8005eb8:	00c00804 	movi	r3,32
+ 8005ebc:	1887c83a 	sub	r3,r3,r2
+ 8005ec0:	19000150 	cmplti	r4,r3,5
+ 8005ec4:	2002f61e 	bne	r4,zero,8006aa0 <_dtoa_r+0x16b4>
+ 8005ec8:	00c00704 	movi	r3,28
+ 8005ecc:	1885c83a 	sub	r2,r3,r2
+ 8005ed0:	d8c00517 	ldw	r3,20(sp)
+ 8005ed4:	98a7883a 	add	r19,r19,r2
+ 8005ed8:	a0a9883a 	add	r20,r20,r2
+ 8005edc:	1887883a 	add	r3,r3,r2
+ 8005ee0:	d8c00515 	stw	r3,20(sp)
+ 8005ee4:	d8800517 	ldw	r2,20(sp)
+ 8005ee8:	00809716 	blt	zero,r2,8006148 <_dtoa_r+0xd5c>
+ 8005eec:	0500050e 	bge	zero,r20,8005f04 <_dtoa_r+0xb18>
+ 8005ef0:	900b883a 	mov	r5,r18
+ 8005ef4:	a00d883a 	mov	r6,r20
+ 8005ef8:	e009883a 	mov	r4,fp
+ 8005efc:	800911c0 	call	800911c <__lshift>
+ 8005f00:	1025883a 	mov	r18,r2
+ 8005f04:	d8800917 	ldw	r2,36(sp)
+ 8005f08:	10012b1e 	bne	r2,zero,80063b8 <_dtoa_r+0xfcc>
+ 8005f0c:	d8800617 	ldw	r2,24(sp)
+ 8005f10:	00810d0e 	bge	zero,r2,8006348 <_dtoa_r+0xf5c>
+ 8005f14:	d8800417 	ldw	r2,16(sp)
+ 8005f18:	10800044 	addi	r2,r2,1
+ 8005f1c:	d8800415 	stw	r2,16(sp)
+ 8005f20:	d8800717 	ldw	r2,28(sp)
+ 8005f24:	1000b21e 	bne	r2,zero,80061f0 <_dtoa_r+0xe04>
+ 8005f28:	ddc00317 	ldw	r23,12(sp)
+ 8005f2c:	04400044 	movi	r17,1
+ 8005f30:	dcc00617 	ldw	r19,24(sp)
+ 8005f34:	00000306 	br	8005f44 <_dtoa_r+0xb58>
+ 8005f38:	8008a9c0 	call	8008a9c <__multadd>
+ 8005f3c:	102b883a 	mov	r21,r2
+ 8005f40:	8c400044 	addi	r17,r17,1
+ 8005f44:	900b883a 	mov	r5,r18
+ 8005f48:	a809883a 	mov	r4,r21
+ 8005f4c:	80051dc0 	call	80051dc <quorem>
+ 8005f50:	10800c04 	addi	r2,r2,48
+ 8005f54:	bdc00044 	addi	r23,r23,1
+ 8005f58:	b8bfffc5 	stb	r2,-1(r23)
+ 8005f5c:	000f883a 	mov	r7,zero
+ 8005f60:	01800284 	movi	r6,10
+ 8005f64:	a80b883a 	mov	r5,r21
+ 8005f68:	e009883a 	mov	r4,fp
+ 8005f6c:	8cfff216 	blt	r17,r19,8005f38 <_dtoa_r+0xb4c>
+ 8005f70:	1011883a 	mov	r8,r2
+ 8005f74:	0029883a 	mov	r20,zero
+ 8005f78:	a80b883a 	mov	r5,r21
+ 8005f7c:	01800044 	movi	r6,1
+ 8005f80:	e009883a 	mov	r4,fp
+ 8005f84:	da000115 	stw	r8,4(sp)
+ 8005f88:	800911c0 	call	800911c <__lshift>
+ 8005f8c:	900b883a 	mov	r5,r18
+ 8005f90:	1009883a 	mov	r4,r2
+ 8005f94:	102b883a 	mov	r21,r2
+ 8005f98:	80092580 	call	8009258 <__mcmp>
+ 8005f9c:	b8ffffc3 	ldbu	r3,-1(r23)
+ 8005fa0:	0081610e 	bge	zero,r2,8006528 <_dtoa_r+0x113c>
+ 8005fa4:	d9400317 	ldw	r5,12(sp)
+ 8005fa8:	00000306 	br	8005fb8 <_dtoa_r+0xbcc>
+ 8005fac:	29017726 	beq	r5,r4,800658c <_dtoa_r+0x11a0>
+ 8005fb0:	20ffffc3 	ldbu	r3,-1(r4)
+ 8005fb4:	202f883a 	mov	r23,r4
+ 8005fb8:	18803fcc 	andi	r2,r3,255
+ 8005fbc:	1080201c 	xori	r2,r2,128
+ 8005fc0:	10bfe004 	addi	r2,r2,-128
+ 8005fc4:	10800e60 	cmpeqi	r2,r2,57
+ 8005fc8:	b93fffc4 	addi	r4,r23,-1
+ 8005fcc:	103ff71e 	bne	r2,zero,8005fac <_dtoa_r+0xbc0>
+ 8005fd0:	18c00044 	addi	r3,r3,1
+ 8005fd4:	20c00005 	stb	r3,0(r4)
+ 8005fd8:	900b883a 	mov	r5,r18
+ 8005fdc:	e009883a 	mov	r4,fp
+ 8005fe0:	8008a780 	call	8008a78 <_Bfree>
+ 8005fe4:	803e9326 	beq	r16,zero,8005a34 <_dtoa_r+0x648>
+ 8005fe8:	a0000426 	beq	r20,zero,8005ffc <_dtoa_r+0xc10>
+ 8005fec:	a4000326 	beq	r20,r16,8005ffc <_dtoa_r+0xc10>
+ 8005ff0:	a00b883a 	mov	r5,r20
+ 8005ff4:	e009883a 	mov	r4,fp
+ 8005ff8:	8008a780 	call	8008a78 <_Bfree>
+ 8005ffc:	800b883a 	mov	r5,r16
+ 8006000:	e009883a 	mov	r4,fp
+ 8006004:	8008a780 	call	8008a78 <_Bfree>
+ 8006008:	003e8a06 	br	8005a34 <_dtoa_r+0x648>
+ 800600c:	d8000915 	stw	zero,36(sp)
+ 8006010:	a0003616 	blt	r20,zero,80060ec <_dtoa_r+0xd00>
+ 8006014:	d8000515 	stw	zero,20(sp)
+ 8006018:	d8c00217 	ldw	r3,8(sp)
+ 800601c:	dd800415 	stw	r22,16(sp)
+ 8006020:	d8000815 	stw	zero,32(sp)
+ 8006024:	188002a8 	cmpgeui	r2,r3,10
+ 8006028:	a5a9883a 	add	r20,r20,r22
+ 800602c:	103d9726 	beq	r2,zero,800568c <_dtoa_r+0x2a0>
+ 8006030:	00800044 	movi	r2,1
+ 8006034:	d8800715 	stw	r2,28(sp)
+ 8006038:	00bfffc4 	movi	r2,-1
+ 800603c:	04bfffc4 	movi	r18,-1
+ 8006040:	04000044 	movi	r16,1
+ 8006044:	d8000215 	stw	zero,8(sp)
+ 8006048:	d8800615 	stw	r2,24(sp)
+ 800604c:	d8001e15 	stw	zero,120(sp)
+ 8006050:	d8800617 	ldw	r2,24(sp)
+ 8006054:	e0001115 	stw	zero,68(fp)
+ 8006058:	000b883a 	mov	r5,zero
+ 800605c:	d8800b15 	stw	r2,44(sp)
+ 8006060:	003daa06 	br	800570c <_dtoa_r+0x320>
+ 8006064:	18800160 	cmpeqi	r2,r3,5
+ 8006068:	00c00044 	movi	r3,1
+ 800606c:	d8c00715 	stw	r3,28(sp)
+ 8006070:	10000d26 	beq	r2,zero,80060a8 <_dtoa_r+0xcbc>
+ 8006074:	d8801e17 	ldw	r2,120(sp)
+ 8006078:	d8c00417 	ldw	r3,16(sp)
+ 800607c:	10c5883a 	add	r2,r2,r3
+ 8006080:	d8800b15 	stw	r2,44(sp)
+ 8006084:	10800044 	addi	r2,r2,1
+ 8006088:	d8800615 	stw	r2,24(sp)
+ 800608c:	100d883a 	mov	r6,r2
+ 8006090:	00bd9216 	blt	zero,r2,80056dc <_dtoa_r+0x2f0>
+ 8006094:	01800044 	movi	r6,1
+ 8006098:	003d9006 	br	80056dc <_dtoa_r+0x2f0>
+ 800609c:	188000a0 	cmpeqi	r2,r3,2
+ 80060a0:	d8000715 	stw	zero,28(sp)
+ 80060a4:	103d881e 	bne	r2,zero,80056c8 <_dtoa_r+0x2dc>
+ 80060a8:	e0001115 	stw	zero,68(fp)
+ 80060ac:	000b883a 	mov	r5,zero
+ 80060b0:	e009883a 	mov	r4,fp
+ 80060b4:	80089d40 	call	80089d4 <_Balloc>
+ 80060b8:	d8800315 	stw	r2,12(sp)
+ 80060bc:	e0801015 	stw	r2,64(fp)
+ 80060c0:	00bfffc4 	movi	r2,-1
+ 80060c4:	d8800b15 	stw	r2,44(sp)
+ 80060c8:	00800044 	movi	r2,1
+ 80060cc:	d8800715 	stw	r2,28(sp)
+ 80060d0:	00bfffc4 	movi	r2,-1
+ 80060d4:	d8001e15 	stw	zero,120(sp)
+ 80060d8:	d8800615 	stw	r2,24(sp)
+ 80060dc:	003e8f06 	br	8005b1c <_dtoa_r+0x730>
+ 80060e0:	00800044 	movi	r2,1
+ 80060e4:	d8800915 	stw	r2,36(sp)
+ 80060e8:	a03d5c0e 	bge	r20,zero,800565c <_dtoa_r+0x270>
+ 80060ec:	04800044 	movi	r18,1
+ 80060f0:	9405c83a 	sub	r2,r18,r16
+ 80060f4:	d8800515 	stw	r2,20(sp)
+ 80060f8:	0029883a 	mov	r20,zero
+ 80060fc:	003d5806 	br	8005660 <_dtoa_r+0x274>
+ 8006100:	b009883a 	mov	r4,r22
+ 8006104:	800f62c0 	call	800f62c <__floatsidf>
+ 8006108:	a00d883a 	mov	r6,r20
+ 800610c:	980f883a 	mov	r7,r19
+ 8006110:	1009883a 	mov	r4,r2
+ 8006114:	180b883a 	mov	r5,r3
+ 8006118:	800e3000 	call	800e300 <__eqdf2>
+ 800611c:	103d3e26 	beq	r2,zero,8005618 <_dtoa_r+0x22c>
+ 8006120:	b5bfffc4 	addi	r22,r22,-1
+ 8006124:	003d3c06 	br	8005618 <_dtoa_r+0x22c>
+ 8006128:	00820134 	movhi	r2,2052
+ 800612c:	109d2704 	addi	r2,r2,29852
+ 8006130:	d8800315 	stw	r2,12(sp)
+ 8006134:	003cdf06 	br	80054b4 <_dtoa_r+0xc8>
+ 8006138:	dc800817 	ldw	r18,32(sp)
+ 800613c:	dcc00517 	ldw	r19,20(sp)
+ 8006140:	0021883a 	mov	r16,zero
+ 8006144:	003f2f06 	br	8005e04 <_dtoa_r+0xa18>
+ 8006148:	a80b883a 	mov	r5,r21
+ 800614c:	100d883a 	mov	r6,r2
+ 8006150:	e009883a 	mov	r4,fp
+ 8006154:	800911c0 	call	800911c <__lshift>
+ 8006158:	102b883a 	mov	r21,r2
+ 800615c:	003f6306 	br	8005eec <_dtoa_r+0xb00>
+ 8006160:	00800704 	movi	r2,28
+ 8006164:	003f5a06 	br	8005ed0 <_dtoa_r+0xae4>
+ 8006168:	01000804 	movi	r4,32
+ 800616c:	2089c83a 	sub	r4,r4,r2
+ 8006170:	d8800117 	ldw	r2,4(sp)
+ 8006174:	1108983a 	sll	r4,r2,r4
+ 8006178:	003cf306 	br	8005548 <_dtoa_r+0x15c>
+ 800617c:	04000044 	movi	r16,1
+ 8006180:	003d4706 	br	80056a0 <_dtoa_r+0x2b4>
+ 8006184:	b00d883a 	mov	r6,r22
+ 8006188:	100b883a 	mov	r5,r2
+ 800618c:	e009883a 	mov	r4,fp
+ 8006190:	8008ff40 	call	8008ff4 <__pow5mult>
+ 8006194:	1025883a 	mov	r18,r2
+ 8006198:	d8800217 	ldw	r2,8(sp)
+ 800619c:	10800090 	cmplti	r2,r2,2
+ 80061a0:	10012f1e 	bne	r2,zero,8006660 <_dtoa_r+0x1274>
+ 80061a4:	0023883a 	mov	r17,zero
+ 80061a8:	90800417 	ldw	r2,16(r18)
+ 80061ac:	10800104 	addi	r2,r2,4
+ 80061b0:	100490ba 	slli	r2,r2,2
+ 80061b4:	9085883a 	add	r2,r18,r2
+ 80061b8:	11000017 	ldw	r4,0(r2)
+ 80061bc:	8008cc00 	call	8008cc0 <__hi0bits>
+ 80061c0:	00c00804 	movi	r3,32
+ 80061c4:	1885c83a 	sub	r2,r3,r2
+ 80061c8:	003f3806 	br	8005eac <_dtoa_r+0xac0>
+ 80061cc:	800b883a 	mov	r5,r16
+ 80061d0:	000f883a 	mov	r7,zero
+ 80061d4:	01800284 	movi	r6,10
+ 80061d8:	e009883a 	mov	r4,fp
+ 80061dc:	8008a9c0 	call	8008a9c <__multadd>
+ 80061e0:	1021883a 	mov	r16,r2
+ 80061e4:	d8800b17 	ldw	r2,44(sp)
+ 80061e8:	00821b0e 	bge	zero,r2,8006a58 <_dtoa_r+0x166c>
+ 80061ec:	d8800615 	stw	r2,24(sp)
+ 80061f0:	04c0b316 	blt	zero,r19,80064c0 <_dtoa_r+0x10d4>
+ 80061f4:	8801341e 	bne	r17,zero,80066c8 <_dtoa_r+0x12dc>
+ 80061f8:	8027883a 	mov	r19,r16
+ 80061fc:	dc400317 	ldw	r17,12(sp)
+ 8006200:	d8c00617 	ldw	r3,24(sp)
+ 8006204:	d8800117 	ldw	r2,4(sp)
+ 8006208:	8dffffc4 	addi	r23,r17,-1
+ 800620c:	b8c7883a 	add	r3,r23,r3
+ 8006210:	d8c00615 	stw	r3,24(sp)
+ 8006214:	d8c00217 	ldw	r3,8(sp)
+ 8006218:	1080004c 	andi	r2,r2,1
+ 800621c:	d8800815 	stw	r2,32(sp)
+ 8006220:	10c4b03a 	or	r2,r2,r3
+ 8006224:	d8800715 	stw	r2,28(sp)
+ 8006228:	00002c06 	br	80062dc <_dtoa_r+0xef0>
+ 800622c:	b80b883a 	mov	r5,r23
+ 8006230:	a809883a 	mov	r4,r21
+ 8006234:	da000515 	stw	r8,20(sp)
+ 8006238:	80092580 	call	8009258 <__mcmp>
+ 800623c:	b80b883a 	mov	r5,r23
+ 8006240:	e009883a 	mov	r4,fp
+ 8006244:	d8800115 	stw	r2,4(sp)
+ 8006248:	8008a780 	call	8008a78 <_Bfree>
+ 800624c:	d8800117 	ldw	r2,4(sp)
+ 8006250:	da000517 	ldw	r8,20(sp)
+ 8006254:	1000021e 	bne	r2,zero,8006260 <_dtoa_r+0xe74>
+ 8006258:	d8c00717 	ldw	r3,28(sp)
+ 800625c:	1801f226 	beq	r3,zero,8006a28 <_dtoa_r+0x163c>
+ 8006260:	8dc00044 	addi	r23,r17,1
+ 8006264:	a0010516 	blt	r20,zero,800667c <_dtoa_r+0x1290>
+ 8006268:	d8c00217 	ldw	r3,8(sp)
+ 800626c:	a0e8b03a 	or	r20,r20,r3
+ 8006270:	d8c00817 	ldw	r3,32(sp)
+ 8006274:	1d28b03a 	or	r20,r3,r20
+ 8006278:	a0010026 	beq	r20,zero,800667c <_dtoa_r+0x1290>
+ 800627c:	00812816 	blt	zero,r2,8006720 <_dtoa_r+0x1334>
+ 8006280:	d8800617 	ldw	r2,24(sp)
+ 8006284:	8a000005 	stb	r8,0(r17)
+ 8006288:	14412926 	beq	r2,r17,8006730 <_dtoa_r+0x1344>
+ 800628c:	a80b883a 	mov	r5,r21
+ 8006290:	000f883a 	mov	r7,zero
+ 8006294:	01800284 	movi	r6,10
+ 8006298:	e009883a 	mov	r4,fp
+ 800629c:	8008a9c0 	call	8008a9c <__multadd>
+ 80062a0:	102b883a 	mov	r21,r2
+ 80062a4:	000f883a 	mov	r7,zero
+ 80062a8:	01800284 	movi	r6,10
+ 80062ac:	800b883a 	mov	r5,r16
+ 80062b0:	e009883a 	mov	r4,fp
+ 80062b4:	84c02026 	beq	r16,r19,8006338 <_dtoa_r+0xf4c>
+ 80062b8:	8008a9c0 	call	8008a9c <__multadd>
+ 80062bc:	980b883a 	mov	r5,r19
+ 80062c0:	000f883a 	mov	r7,zero
+ 80062c4:	01800284 	movi	r6,10
+ 80062c8:	e009883a 	mov	r4,fp
+ 80062cc:	1021883a 	mov	r16,r2
+ 80062d0:	8008a9c0 	call	8008a9c <__multadd>
+ 80062d4:	1027883a 	mov	r19,r2
+ 80062d8:	b823883a 	mov	r17,r23
+ 80062dc:	900b883a 	mov	r5,r18
+ 80062e0:	a809883a 	mov	r4,r21
+ 80062e4:	80051dc0 	call	80051dc <quorem>
+ 80062e8:	800b883a 	mov	r5,r16
+ 80062ec:	a809883a 	mov	r4,r21
+ 80062f0:	102d883a 	mov	r22,r2
+ 80062f4:	80092580 	call	8009258 <__mcmp>
+ 80062f8:	980d883a 	mov	r6,r19
+ 80062fc:	900b883a 	mov	r5,r18
+ 8006300:	e009883a 	mov	r4,fp
+ 8006304:	1029883a 	mov	r20,r2
+ 8006308:	80092b00 	call	80092b0 <__mdiff>
+ 800630c:	102f883a 	mov	r23,r2
+ 8006310:	10800317 	ldw	r2,12(r2)
+ 8006314:	b2000c04 	addi	r8,r22,48
+ 8006318:	103fc426 	beq	r2,zero,800622c <_dtoa_r+0xe40>
+ 800631c:	b80b883a 	mov	r5,r23
+ 8006320:	e009883a 	mov	r4,fp
+ 8006324:	da000115 	stw	r8,4(sp)
+ 8006328:	8008a780 	call	8008a78 <_Bfree>
+ 800632c:	00800044 	movi	r2,1
+ 8006330:	da000117 	ldw	r8,4(sp)
+ 8006334:	003fca06 	br	8006260 <_dtoa_r+0xe74>
+ 8006338:	8008a9c0 	call	8008a9c <__multadd>
+ 800633c:	1021883a 	mov	r16,r2
+ 8006340:	1027883a 	mov	r19,r2
+ 8006344:	003fe406 	br	80062d8 <_dtoa_r+0xeec>
+ 8006348:	d8800217 	ldw	r2,8(sp)
+ 800634c:	108000d0 	cmplti	r2,r2,3
+ 8006350:	10004b1e 	bne	r2,zero,8006480 <_dtoa_r+0x1094>
+ 8006354:	d8800617 	ldw	r2,24(sp)
+ 8006358:	103e0d1e 	bne	r2,zero,8005b90 <_dtoa_r+0x7a4>
+ 800635c:	900b883a 	mov	r5,r18
+ 8006360:	e009883a 	mov	r4,fp
+ 8006364:	000f883a 	mov	r7,zero
+ 8006368:	01800144 	movi	r6,5
+ 800636c:	8008a9c0 	call	8008a9c <__multadd>
+ 8006370:	100b883a 	mov	r5,r2
+ 8006374:	a809883a 	mov	r4,r21
+ 8006378:	1025883a 	mov	r18,r2
+ 800637c:	80092580 	call	8009258 <__mcmp>
+ 8006380:	00be030e 	bge	zero,r2,8005b90 <_dtoa_r+0x7a4>
+ 8006384:	d8c00317 	ldw	r3,12(sp)
+ 8006388:	00800c44 	movi	r2,49
+ 800638c:	18800005 	stb	r2,0(r3)
+ 8006390:	d8800417 	ldw	r2,16(sp)
+ 8006394:	1dc00044 	addi	r23,r3,1
+ 8006398:	14400044 	addi	r17,r2,1
+ 800639c:	900b883a 	mov	r5,r18
+ 80063a0:	e009883a 	mov	r4,fp
+ 80063a4:	8008a780 	call	8008a78 <_Bfree>
+ 80063a8:	88800044 	addi	r2,r17,1
+ 80063ac:	d8800415 	stw	r2,16(sp)
+ 80063b0:	803f121e 	bne	r16,zero,8005ffc <_dtoa_r+0xc10>
+ 80063b4:	003d9f06 	br	8005a34 <_dtoa_r+0x648>
+ 80063b8:	900b883a 	mov	r5,r18
+ 80063bc:	a809883a 	mov	r4,r21
+ 80063c0:	80092580 	call	8009258 <__mcmp>
+ 80063c4:	103ed10e 	bge	r2,zero,8005f0c <_dtoa_r+0xb20>
+ 80063c8:	a80b883a 	mov	r5,r21
+ 80063cc:	000f883a 	mov	r7,zero
+ 80063d0:	01800284 	movi	r6,10
+ 80063d4:	e009883a 	mov	r4,fp
+ 80063d8:	8008a9c0 	call	8008a9c <__multadd>
+ 80063dc:	102b883a 	mov	r21,r2
+ 80063e0:	d8800417 	ldw	r2,16(sp)
+ 80063e4:	153fffc4 	addi	r20,r2,-1
+ 80063e8:	d8800717 	ldw	r2,28(sp)
+ 80063ec:	103f771e 	bne	r2,zero,80061cc <_dtoa_r+0xde0>
+ 80063f0:	d8800b17 	ldw	r2,44(sp)
+ 80063f4:	0081910e 	bge	zero,r2,8006a3c <_dtoa_r+0x1650>
+ 80063f8:	d8800615 	stw	r2,24(sp)
+ 80063fc:	003eca06 	br	8005f28 <_dtoa_r+0xb3c>
+ 8006400:	d9800817 	ldw	r6,32(sp)
+ 8006404:	a80b883a 	mov	r5,r21
+ 8006408:	e009883a 	mov	r4,fp
+ 800640c:	8008ff40 	call	8008ff4 <__pow5mult>
+ 8006410:	102b883a 	mov	r21,r2
+ 8006414:	003e9a06 	br	8005e80 <_dtoa_r+0xa94>
+ 8006418:	00820134 	movhi	r2,2052
+ 800641c:	1007883a 	mov	r3,r2
+ 8006420:	18dd3004 	addi	r3,r3,29888
+ 8006424:	00820134 	movhi	r2,2052
+ 8006428:	d8c00315 	stw	r3,12(sp)
+ 800642c:	109d30c4 	addi	r2,r2,29891
+ 8006430:	003da506 	br	8005ac8 <_dtoa_r+0x6dc>
+ 8006434:	d8800117 	ldw	r2,4(sp)
+ 8006438:	103e991e 	bne	r2,zero,8005ea0 <_dtoa_r+0xab4>
+ 800643c:	00800434 	movhi	r2,16
+ 8006440:	10bfffc4 	addi	r2,r2,-1
+ 8006444:	8884703a 	and	r2,r17,r2
+ 8006448:	103e951e 	bne	r2,zero,8005ea0 <_dtoa_r+0xab4>
+ 800644c:	8c5ffc2c 	andhi	r17,r17,32752
+ 8006450:	883e9326 	beq	r17,zero,8005ea0 <_dtoa_r+0xab4>
+ 8006454:	d8800517 	ldw	r2,20(sp)
+ 8006458:	a5000044 	addi	r20,r20,1
+ 800645c:	04400044 	movi	r17,1
+ 8006460:	10800044 	addi	r2,r2,1
+ 8006464:	d8800515 	stw	r2,20(sp)
+ 8006468:	003e8e06 	br	8005ea4 <_dtoa_r+0xab8>
+ 800646c:	00800044 	movi	r2,1
+ 8006470:	04800044 	movi	r18,1
+ 8006474:	d8800615 	stw	r2,24(sp)
+ 8006478:	d8801e15 	stw	r2,120(sp)
+ 800647c:	003ef406 	br	8006050 <_dtoa_r+0xc64>
+ 8006480:	d8800417 	ldw	r2,16(sp)
+ 8006484:	10800044 	addi	r2,r2,1
+ 8006488:	d8800415 	stw	r2,16(sp)
+ 800648c:	d8800717 	ldw	r2,28(sp)
+ 8006490:	103f571e 	bne	r2,zero,80061f0 <_dtoa_r+0xe04>
+ 8006494:	900b883a 	mov	r5,r18
+ 8006498:	a809883a 	mov	r4,r21
+ 800649c:	80051dc0 	call	80051dc <quorem>
+ 80064a0:	12000c04 	addi	r8,r2,48
+ 80064a4:	d8800317 	ldw	r2,12(sp)
+ 80064a8:	0029883a 	mov	r20,zero
+ 80064ac:	15c00044 	addi	r23,r2,1
+ 80064b0:	12000005 	stb	r8,0(r2)
+ 80064b4:	003eb006 	br	8005f78 <_dtoa_r+0xb8c>
+ 80064b8:	a005883a 	mov	r2,r20
+ 80064bc:	003e5506 	br	8005e14 <_dtoa_r+0xa28>
+ 80064c0:	800b883a 	mov	r5,r16
+ 80064c4:	980d883a 	mov	r6,r19
+ 80064c8:	e009883a 	mov	r4,fp
+ 80064cc:	800911c0 	call	800911c <__lshift>
+ 80064d0:	1021883a 	mov	r16,r2
+ 80064d4:	003f4706 	br	80061f4 <_dtoa_r+0xe08>
+ 80064d8:	14a5c83a 	sub	r18,r2,r18
+ 80064dc:	003e3e06 	br	8005dd8 <_dtoa_r+0x9ec>
+ 80064e0:	00820134 	movhi	r2,2052
+ 80064e4:	109d4104 	addi	r2,r2,29956
+ 80064e8:	11800817 	ldw	r6,32(r2)
+ 80064ec:	11c00917 	ldw	r7,36(r2)
+ 80064f0:	d9000117 	ldw	r4,4(sp)
+ 80064f4:	880b883a 	mov	r5,r17
+ 80064f8:	da400e15 	stw	r9,56(sp)
+ 80064fc:	da800d15 	stw	r10,52(sp)
+ 8006500:	800da580 	call	800da58 <__divdf3>
+ 8006504:	d8800c15 	stw	r2,48(sp)
+ 8006508:	1827883a 	mov	r19,r3
+ 800650c:	bdc003cc 	andi	r23,r23,15
+ 8006510:	040000c4 	movi	r16,3
+ 8006514:	da800d17 	ldw	r10,52(sp)
+ 8006518:	da400e17 	ldw	r9,56(sp)
+ 800651c:	003c9206 	br	8005768 <_dtoa_r+0x37c>
+ 8006520:	d8000715 	stw	zero,28(sp)
+ 8006524:	003ed306 	br	8006074 <_dtoa_r+0xc88>
+ 8006528:	1000031e 	bne	r2,zero,8006538 <_dtoa_r+0x114c>
+ 800652c:	da000117 	ldw	r8,4(sp)
+ 8006530:	4200004c 	andi	r8,r8,1
+ 8006534:	403e9b1e 	bne	r8,zero,8005fa4 <_dtoa_r+0xbb8>
+ 8006538:	1805883a 	mov	r2,r3
+ 800653c:	00000206 	br	8006548 <_dtoa_r+0x115c>
+ 8006540:	b8bfff83 	ldbu	r2,-2(r23)
+ 8006544:	182f883a 	mov	r23,r3
+ 8006548:	10803fcc 	andi	r2,r2,255
+ 800654c:	1080201c 	xori	r2,r2,128
+ 8006550:	10bfe004 	addi	r2,r2,-128
+ 8006554:	10800c18 	cmpnei	r2,r2,48
+ 8006558:	b8ffffc4 	addi	r3,r23,-1
+ 800655c:	103ff826 	beq	r2,zero,8006540 <_dtoa_r+0x1154>
+ 8006560:	003e9d06 	br	8005fd8 <_dtoa_r+0xbec>
+ 8006564:	d8c00a17 	ldw	r3,40(sp)
+ 8006568:	1800bc26 	beq	r3,zero,800685c <_dtoa_r+0x1470>
+ 800656c:	d8c00517 	ldw	r3,20(sp)
+ 8006570:	10810cc4 	addi	r2,r2,1075
+ 8006574:	a0a9883a 	add	r20,r20,r2
+ 8006578:	1885883a 	add	r2,r3,r2
+ 800657c:	1827883a 	mov	r19,r3
+ 8006580:	dc800817 	ldw	r18,32(sp)
+ 8006584:	d8800515 	stw	r2,20(sp)
+ 8006588:	003e1a06 	br	8005df4 <_dtoa_r+0xa08>
+ 800658c:	d8c00317 	ldw	r3,12(sp)
+ 8006590:	00800c44 	movi	r2,49
+ 8006594:	18800005 	stb	r2,0(r3)
+ 8006598:	d8800417 	ldw	r2,16(sp)
+ 800659c:	10800044 	addi	r2,r2,1
+ 80065a0:	d8800415 	stw	r2,16(sp)
+ 80065a4:	003e8c06 	br	8005fd8 <_dtoa_r+0xbec>
+ 80065a8:	8009883a 	mov	r4,r16
+ 80065ac:	800f62c0 	call	800f62c <__floatsidf>
+ 80065b0:	900d883a 	mov	r6,r18
+ 80065b4:	980f883a 	mov	r7,r19
+ 80065b8:	1009883a 	mov	r4,r2
+ 80065bc:	180b883a 	mov	r5,r3
+ 80065c0:	800e5600 	call	800e560 <__muldf3>
+ 80065c4:	000d883a 	mov	r6,zero
+ 80065c8:	01d00734 	movhi	r7,16412
+ 80065cc:	1009883a 	mov	r4,r2
+ 80065d0:	180b883a 	mov	r5,r3
+ 80065d4:	800d0b80 	call	800d0b8 <__adddf3>
+ 80065d8:	d8800c15 	stw	r2,48(sp)
+ 80065dc:	00bf3034 	movhi	r2,64704
+ 80065e0:	1885883a 	add	r2,r3,r2
+ 80065e4:	d8800d15 	stw	r2,52(sp)
+ 80065e8:	9009883a 	mov	r4,r18
+ 80065ec:	980b883a 	mov	r5,r19
+ 80065f0:	000d883a 	mov	r6,zero
+ 80065f4:	01d00534 	movhi	r7,16404
+ 80065f8:	800ebec0 	call	800ebec <__subdf3>
+ 80065fc:	ddc00c17 	ldw	r23,48(sp)
+ 8006600:	dcc00d17 	ldw	r19,52(sp)
+ 8006604:	1009883a 	mov	r4,r2
+ 8006608:	b80d883a 	mov	r6,r23
+ 800660c:	980f883a 	mov	r7,r19
+ 8006610:	180b883a 	mov	r5,r3
+ 8006614:	1025883a 	mov	r18,r2
+ 8006618:	1821883a 	mov	r16,r3
+ 800661c:	800e3800 	call	800e380 <__gedf2>
+ 8006620:	0080ee16 	blt	zero,r2,80069dc <_dtoa_r+0x15f0>
+ 8006624:	99e0003c 	xorhi	r7,r19,32768
+ 8006628:	b80d883a 	mov	r6,r23
+ 800662c:	9009883a 	mov	r4,r18
+ 8006630:	800b883a 	mov	r5,r16
+ 8006634:	800e4700 	call	800e470 <__ledf2>
+ 8006638:	103d380e 	bge	r2,zero,8005b1c <_dtoa_r+0x730>
+ 800663c:	0025883a 	mov	r18,zero
+ 8006640:	0021883a 	mov	r16,zero
+ 8006644:	003d5206 	br	8005b90 <_dtoa_r+0x7a4>
+ 8006648:	d8800417 	ldw	r2,16(sp)
+ 800664c:	1000ad1e 	bne	r2,zero,8006904 <_dtoa_r+0x1518>
+ 8006650:	dc800117 	ldw	r18,4(sp)
+ 8006654:	8827883a 	mov	r19,r17
+ 8006658:	04000084 	movi	r16,2
+ 800665c:	003c5b06 	br	80057cc <_dtoa_r+0x3e0>
+ 8006660:	d8800117 	ldw	r2,4(sp)
+ 8006664:	103ecf1e 	bne	r2,zero,80061a4 <_dtoa_r+0xdb8>
+ 8006668:	00800434 	movhi	r2,16
+ 800666c:	10bfffc4 	addi	r2,r2,-1
+ 8006670:	8884703a 	and	r2,r17,r2
+ 8006674:	103f7526 	beq	r2,zero,800644c <_dtoa_r+0x1060>
+ 8006678:	003eca06 	br	80061a4 <_dtoa_r+0xdb8>
+ 800667c:	00800e0e 	bge	zero,r2,80066b8 <_dtoa_r+0x12cc>
+ 8006680:	a80b883a 	mov	r5,r21
+ 8006684:	01800044 	movi	r6,1
+ 8006688:	e009883a 	mov	r4,fp
+ 800668c:	da000115 	stw	r8,4(sp)
+ 8006690:	800911c0 	call	800911c <__lshift>
+ 8006694:	900b883a 	mov	r5,r18
+ 8006698:	1009883a 	mov	r4,r2
+ 800669c:	102b883a 	mov	r21,r2
+ 80066a0:	80092580 	call	8009258 <__mcmp>
+ 80066a4:	da000117 	ldw	r8,4(sp)
+ 80066a8:	0080d50e 	bge	zero,r2,8006a00 <_dtoa_r+0x1614>
+ 80066ac:	42000e60 	cmpeqi	r8,r8,57
+ 80066b0:	4000c31e 	bne	r8,zero,80069c0 <_dtoa_r+0x15d4>
+ 80066b4:	b2000c44 	addi	r8,r22,49
+ 80066b8:	8029883a 	mov	r20,r16
+ 80066bc:	8a000005 	stb	r8,0(r17)
+ 80066c0:	9821883a 	mov	r16,r19
+ 80066c4:	003e4406 	br	8005fd8 <_dtoa_r+0xbec>
+ 80066c8:	81400117 	ldw	r5,4(r16)
+ 80066cc:	e009883a 	mov	r4,fp
+ 80066d0:	80089d40 	call	80089d4 <_Balloc>
+ 80066d4:	81800417 	ldw	r6,16(r16)
+ 80066d8:	81400304 	addi	r5,r16,12
+ 80066dc:	11000304 	addi	r4,r2,12
+ 80066e0:	31800084 	addi	r6,r6,2
+ 80066e4:	300c90ba 	slli	r6,r6,2
+ 80066e8:	1023883a 	mov	r17,r2
+ 80066ec:	80086b80 	call	80086b8 <memcpy>
+ 80066f0:	01800044 	movi	r6,1
+ 80066f4:	880b883a 	mov	r5,r17
+ 80066f8:	e009883a 	mov	r4,fp
+ 80066fc:	800911c0 	call	800911c <__lshift>
+ 8006700:	1027883a 	mov	r19,r2
+ 8006704:	003ebd06 	br	80061fc <_dtoa_r+0xe10>
+ 8006708:	dd400117 	ldw	r21,4(sp)
+ 800670c:	003cc906 	br	8005a34 <_dtoa_r+0x648>
+ 8006710:	d8800517 	ldw	r2,20(sp)
+ 8006714:	d8c00617 	ldw	r3,24(sp)
+ 8006718:	10e7c83a 	sub	r19,r2,r3
+ 800671c:	003db506 	br	8005df4 <_dtoa_r+0xa08>
+ 8006720:	40800e58 	cmpnei	r2,r8,57
+ 8006724:	1000a626 	beq	r2,zero,80069c0 <_dtoa_r+0x15d4>
+ 8006728:	42000044 	addi	r8,r8,1
+ 800672c:	003fe206 	br	80066b8 <_dtoa_r+0x12cc>
+ 8006730:	8029883a 	mov	r20,r16
+ 8006734:	9821883a 	mov	r16,r19
+ 8006738:	003e0f06 	br	8005f78 <_dtoa_r+0xb8c>
+ 800673c:	d9000c17 	ldw	r4,48(sp)
+ 8006740:	d9400d17 	ldw	r5,52(sp)
+ 8006744:	da401015 	stw	r9,64(sp)
+ 8006748:	800e5600 	call	800e560 <__muldf3>
+ 800674c:	d9000e17 	ldw	r4,56(sp)
+ 8006750:	d8c00d15 	stw	r3,52(sp)
+ 8006754:	da401017 	ldw	r9,64(sp)
+ 8006758:	d8c00317 	ldw	r3,12(sp)
+ 800675c:	d8800c15 	stw	r2,48(sp)
+ 8006760:	20800058 	cmpnei	r2,r4,1
+ 8006764:	1a400005 	stb	r9,0(r3)
+ 8006768:	1907883a 	add	r3,r3,r4
+ 800676c:	1809883a 	mov	r4,r3
+ 8006770:	10001d26 	beq	r2,zero,80067e8 <_dtoa_r+0x13fc>
+ 8006774:	8007883a 	mov	r3,r16
+ 8006778:	9005883a 	mov	r2,r18
+ 800677c:	dc400e15 	stw	r17,56(sp)
+ 8006780:	2021883a 	mov	r16,r4
+ 8006784:	000d883a 	mov	r6,zero
+ 8006788:	01d00934 	movhi	r7,16420
+ 800678c:	1009883a 	mov	r4,r2
+ 8006790:	180b883a 	mov	r5,r3
+ 8006794:	800e5600 	call	800e560 <__muldf3>
+ 8006798:	180b883a 	mov	r5,r3
+ 800679c:	1009883a 	mov	r4,r2
+ 80067a0:	1825883a 	mov	r18,r3
+ 80067a4:	1023883a 	mov	r17,r2
+ 80067a8:	800f5ac0 	call	800f5ac <__fixdfsi>
+ 80067ac:	1009883a 	mov	r4,r2
+ 80067b0:	1027883a 	mov	r19,r2
+ 80067b4:	800f62c0 	call	800f62c <__floatsidf>
+ 80067b8:	100d883a 	mov	r6,r2
+ 80067bc:	180f883a 	mov	r7,r3
+ 80067c0:	8809883a 	mov	r4,r17
+ 80067c4:	900b883a 	mov	r5,r18
+ 80067c8:	bdc00044 	addi	r23,r23,1
+ 80067cc:	9cc00c04 	addi	r19,r19,48
+ 80067d0:	800ebec0 	call	800ebec <__subdf3>
+ 80067d4:	bcffffc5 	stb	r19,-1(r23)
+ 80067d8:	bc3fea1e 	bne	r23,r16,8006784 <_dtoa_r+0x1398>
+ 80067dc:	dc400e17 	ldw	r17,56(sp)
+ 80067e0:	1025883a 	mov	r18,r2
+ 80067e4:	1821883a 	mov	r16,r3
+ 80067e8:	d9000c17 	ldw	r4,48(sp)
+ 80067ec:	d9400d17 	ldw	r5,52(sp)
+ 80067f0:	000d883a 	mov	r6,zero
+ 80067f4:	01cff834 	movhi	r7,16352
+ 80067f8:	800d0b80 	call	800d0b8 <__adddf3>
+ 80067fc:	100d883a 	mov	r6,r2
+ 8006800:	180f883a 	mov	r7,r3
+ 8006804:	9009883a 	mov	r4,r18
+ 8006808:	800b883a 	mov	r5,r16
+ 800680c:	800e3800 	call	800e380 <__gedf2>
+ 8006810:	00807516 	blt	zero,r2,80069e8 <_dtoa_r+0x15fc>
+ 8006814:	d9800c17 	ldw	r6,48(sp)
+ 8006818:	d9c00d17 	ldw	r7,52(sp)
+ 800681c:	0009883a 	mov	r4,zero
+ 8006820:	014ff834 	movhi	r5,16352
+ 8006824:	800ebec0 	call	800ebec <__subdf3>
+ 8006828:	100d883a 	mov	r6,r2
+ 800682c:	180f883a 	mov	r7,r3
+ 8006830:	9009883a 	mov	r4,r18
+ 8006834:	800b883a 	mov	r5,r16
+ 8006838:	800e4700 	call	800e470 <__ledf2>
+ 800683c:	103cb70e 	bge	r2,zero,8005b1c <_dtoa_r+0x730>
+ 8006840:	00000106 	br	8006848 <_dtoa_r+0x145c>
+ 8006844:	182f883a 	mov	r23,r3
+ 8006848:	b8bfffc7 	ldb	r2,-1(r23)
+ 800684c:	b8ffffc4 	addi	r3,r23,-1
+ 8006850:	10800c20 	cmpeqi	r2,r2,48
+ 8006854:	103ffb1e 	bne	r2,zero,8006844 <_dtoa_r+0x1458>
+ 8006858:	003c7306 	br	8005a28 <_dtoa_r+0x63c>
+ 800685c:	d8c01217 	ldw	r3,72(sp)
+ 8006860:	d9000517 	ldw	r4,20(sp)
+ 8006864:	00800d84 	movi	r2,54
+ 8006868:	10c5c83a 	sub	r2,r2,r3
+ 800686c:	a0a9883a 	add	r20,r20,r2
+ 8006870:	2085883a 	add	r2,r4,r2
+ 8006874:	2027883a 	mov	r19,r4
+ 8006878:	dc800817 	ldw	r18,32(sp)
+ 800687c:	d8800515 	stw	r2,20(sp)
+ 8006880:	003d5c06 	br	8005df4 <_dtoa_r+0xa08>
+ 8006884:	d8800617 	ldw	r2,24(sp)
+ 8006888:	103f4726 	beq	r2,zero,80065a8 <_dtoa_r+0x11bc>
+ 800688c:	ddc00b17 	ldw	r23,44(sp)
+ 8006890:	05fca20e 	bge	zero,r23,8005b1c <_dtoa_r+0x730>
+ 8006894:	980b883a 	mov	r5,r19
+ 8006898:	000d883a 	mov	r6,zero
+ 800689c:	01d00934 	movhi	r7,16420
+ 80068a0:	9009883a 	mov	r4,r18
+ 80068a4:	800e5600 	call	800e560 <__muldf3>
+ 80068a8:	81000044 	addi	r4,r16,1
+ 80068ac:	1025883a 	mov	r18,r2
+ 80068b0:	1827883a 	mov	r19,r3
+ 80068b4:	800f62c0 	call	800f62c <__floatsidf>
+ 80068b8:	900d883a 	mov	r6,r18
+ 80068bc:	980f883a 	mov	r7,r19
+ 80068c0:	1009883a 	mov	r4,r2
+ 80068c4:	180b883a 	mov	r5,r3
+ 80068c8:	800e5600 	call	800e560 <__muldf3>
+ 80068cc:	000d883a 	mov	r6,zero
+ 80068d0:	01d00734 	movhi	r7,16412
+ 80068d4:	1009883a 	mov	r4,r2
+ 80068d8:	180b883a 	mov	r5,r3
+ 80068dc:	800d0b80 	call	800d0b8 <__adddf3>
+ 80068e0:	d8800c15 	stw	r2,48(sp)
+ 80068e4:	d8800417 	ldw	r2,16(sp)
+ 80068e8:	ddc00e15 	stw	r23,56(sp)
+ 80068ec:	10bfffc4 	addi	r2,r2,-1
+ 80068f0:	d8800f15 	stw	r2,60(sp)
+ 80068f4:	00bf3034 	movhi	r2,64704
+ 80068f8:	1885883a 	add	r2,r3,r2
+ 80068fc:	d8800d15 	stw	r2,52(sp)
+ 8006900:	003bd006 	br	8005844 <_dtoa_r+0x458>
+ 8006904:	d8800417 	ldw	r2,16(sp)
+ 8006908:	d9000117 	ldw	r4,4(sp)
+ 800690c:	880b883a 	mov	r5,r17
+ 8006910:	00afc83a 	sub	r23,zero,r2
+ 8006914:	b88003cc 	andi	r2,r23,15
+ 8006918:	100690fa 	slli	r3,r2,3
+ 800691c:	00820134 	movhi	r2,2052
+ 8006920:	109d4b04 	addi	r2,r2,29996
+ 8006924:	10c5883a 	add	r2,r2,r3
+ 8006928:	11800017 	ldw	r6,0(r2)
+ 800692c:	11c00117 	ldw	r7,4(r2)
+ 8006930:	b82fd13a 	srai	r23,r23,4
+ 8006934:	800e5600 	call	800e560 <__muldf3>
+ 8006938:	1025883a 	mov	r18,r2
+ 800693c:	1827883a 	mov	r19,r3
+ 8006940:	b8004a26 	beq	r23,zero,8006a6c <_dtoa_r+0x1680>
+ 8006944:	02020134 	movhi	r8,2052
+ 8006948:	04000084 	movi	r16,2
+ 800694c:	421d4104 	addi	r8,r8,29956
+ 8006950:	dc400c15 	stw	r17,48(sp)
+ 8006954:	000f883a 	mov	r7,zero
+ 8006958:	8023883a 	mov	r17,r16
+ 800695c:	4021883a 	mov	r16,r8
+ 8006960:	b980004c 	andi	r6,r23,1
+ 8006964:	1009883a 	mov	r4,r2
+ 8006968:	b82fd07a 	srai	r23,r23,1
+ 800696c:	180b883a 	mov	r5,r3
+ 8006970:	30000526 	beq	r6,zero,8006988 <_dtoa_r+0x159c>
+ 8006974:	81c00117 	ldw	r7,4(r16)
+ 8006978:	81800017 	ldw	r6,0(r16)
+ 800697c:	8c400044 	addi	r17,r17,1
+ 8006980:	800e5600 	call	800e560 <__muldf3>
+ 8006984:	01c00044 	movi	r7,1
+ 8006988:	84000204 	addi	r16,r16,8
+ 800698c:	b83ff41e 	bne	r23,zero,8006960 <_dtoa_r+0x1574>
+ 8006990:	39c03fcc 	andi	r7,r7,255
+ 8006994:	8821883a 	mov	r16,r17
+ 8006998:	dc400c17 	ldw	r17,48(sp)
+ 800699c:	383b8b26 	beq	r7,zero,80057cc <_dtoa_r+0x3e0>
+ 80069a0:	1025883a 	mov	r18,r2
+ 80069a4:	1827883a 	mov	r19,r3
+ 80069a8:	003b8806 	br	80057cc <_dtoa_r+0x3e0>
+ 80069ac:	d8800417 	ldw	r2,16(sp)
+ 80069b0:	02000c44 	movi	r8,49
+ 80069b4:	10800044 	addi	r2,r2,1
+ 80069b8:	d8800415 	stw	r2,16(sp)
+ 80069bc:	003cf606 	br	8005d98 <_dtoa_r+0x9ac>
+ 80069c0:	00800e44 	movi	r2,57
+ 80069c4:	8029883a 	mov	r20,r16
+ 80069c8:	88800005 	stb	r2,0(r17)
+ 80069cc:	9821883a 	mov	r16,r19
+ 80069d0:	00c00e44 	movi	r3,57
+ 80069d4:	d9400317 	ldw	r5,12(sp)
+ 80069d8:	003d7706 	br	8005fb8 <_dtoa_r+0xbcc>
+ 80069dc:	0025883a 	mov	r18,zero
+ 80069e0:	0021883a 	mov	r16,zero
+ 80069e4:	003e6706 	br	8006384 <_dtoa_r+0xf98>
+ 80069e8:	d8800f17 	ldw	r2,60(sp)
+ 80069ec:	ba3fffc3 	ldbu	r8,-1(r23)
+ 80069f0:	d9000317 	ldw	r4,12(sp)
+ 80069f4:	10800044 	addi	r2,r2,1
+ 80069f8:	d8800415 	stw	r2,16(sp)
+ 80069fc:	003cdf06 	br	8005d7c <_dtoa_r+0x990>
+ 8006a00:	103f2d1e 	bne	r2,zero,80066b8 <_dtoa_r+0x12cc>
+ 8006a04:	4080004c 	andi	r2,r8,1
+ 8006a08:	103f281e 	bne	r2,zero,80066ac <_dtoa_r+0x12c0>
+ 8006a0c:	003f2a06 	br	80066b8 <_dtoa_r+0x12cc>
+ 8006a10:	d8800f17 	ldw	r2,60(sp)
+ 8006a14:	8811883a 	mov	r8,r17
+ 8006a18:	d9000317 	ldw	r4,12(sp)
+ 8006a1c:	10800044 	addi	r2,r2,1
+ 8006a20:	d8800415 	stw	r2,16(sp)
+ 8006a24:	003cd506 	br	8005d7c <_dtoa_r+0x990>
+ 8006a28:	40800e60 	cmpeqi	r2,r8,57
+ 8006a2c:	8dc00044 	addi	r23,r17,1
+ 8006a30:	103fe31e 	bne	r2,zero,80069c0 <_dtoa_r+0x15d4>
+ 8006a34:	053f1f16 	blt	zero,r20,80066b4 <_dtoa_r+0x12c8>
+ 8006a38:	003f1f06 	br	80066b8 <_dtoa_r+0x12cc>
+ 8006a3c:	d8800217 	ldw	r2,8(sp)
+ 8006a40:	108000c8 	cmpgei	r2,r2,3
+ 8006a44:	103e9326 	beq	r2,zero,8006494 <_dtoa_r+0x10a8>
+ 8006a48:	d8800b17 	ldw	r2,44(sp)
+ 8006a4c:	dd000415 	stw	r20,16(sp)
+ 8006a50:	d8800615 	stw	r2,24(sp)
+ 8006a54:	003e3f06 	br	8006354 <_dtoa_r+0xf68>
+ 8006a58:	d8800217 	ldw	r2,8(sp)
+ 8006a5c:	108000c8 	cmpgei	r2,r2,3
+ 8006a60:	103ff91e 	bne	r2,zero,8006a48 <_dtoa_r+0x165c>
+ 8006a64:	d8800b17 	ldw	r2,44(sp)
+ 8006a68:	003de006 	br	80061ec <_dtoa_r+0xe00>
+ 8006a6c:	04000084 	movi	r16,2
+ 8006a70:	003b5606 	br	80057cc <_dtoa_r+0x3e0>
+ 8006a74:	d8800f17 	ldw	r2,60(sp)
+ 8006a78:	d9000317 	ldw	r4,12(sp)
+ 8006a7c:	10800044 	addi	r2,r2,1
+ 8006a80:	d8800415 	stw	r2,16(sp)
+ 8006a84:	003cbd06 	br	8005d7c <_dtoa_r+0x990>
+ 8006a88:	00820134 	movhi	r2,2052
+ 8006a8c:	109d3104 	addi	r2,r2,29892
+ 8006a90:	d8800315 	stw	r2,12(sp)
+ 8006a94:	003a8706 	br	80054b4 <_dtoa_r+0xc8>
+ 8006a98:	000b883a 	mov	r5,zero
+ 8006a9c:	003b1b06 	br	800570c <_dtoa_r+0x320>
+ 8006aa0:	18c00120 	cmpeqi	r3,r3,4
+ 8006aa4:	183d0f1e 	bne	r3,zero,8005ee4 <_dtoa_r+0xaf8>
+ 8006aa8:	00c00f04 	movi	r3,60
+ 8006aac:	1885c83a 	sub	r2,r3,r2
+ 8006ab0:	003d0706 	br	8005ed0 <_dtoa_r+0xae4>
+
+08006ab4 <__sflush_r>:
+ 8006ab4:	2880030b 	ldhu	r2,12(r5)
+ 8006ab8:	defffb04 	addi	sp,sp,-20
+ 8006abc:	dcc00315 	stw	r19,12(sp)
+ 8006ac0:	dc000015 	stw	r16,0(sp)
+ 8006ac4:	dfc00415 	stw	ra,16(sp)
+ 8006ac8:	dc800215 	stw	r18,8(sp)
+ 8006acc:	dc400115 	stw	r17,4(sp)
+ 8006ad0:	10c0020c 	andi	r3,r2,8
+ 8006ad4:	2821883a 	mov	r16,r5
+ 8006ad8:	2027883a 	mov	r19,r4
+ 8006adc:	18003f1e 	bne	r3,zero,8006bdc <__sflush_r+0x128>
+ 8006ae0:	28c00117 	ldw	r3,4(r5)
+ 8006ae4:	10820014 	ori	r2,r2,2048
+ 8006ae8:	2880030d 	sth	r2,12(r5)
+ 8006aec:	00c0550e 	bge	zero,r3,8006c44 <__sflush_r+0x190>
+ 8006af0:	82000a17 	ldw	r8,40(r16)
+ 8006af4:	40003126 	beq	r8,zero,8006bbc <__sflush_r+0x108>
+ 8006af8:	9c400017 	ldw	r17,0(r19)
+ 8006afc:	1104000c 	andi	r4,r2,4096
+ 8006b00:	98000015 	stw	zero,0(r19)
+ 8006b04:	1007883a 	mov	r3,r2
+ 8006b08:	81400717 	ldw	r5,28(r16)
+ 8006b0c:	2000521e 	bne	r4,zero,8006c58 <__sflush_r+0x1a4>
+ 8006b10:	01c00044 	movi	r7,1
+ 8006b14:	000d883a 	mov	r6,zero
+ 8006b18:	9809883a 	mov	r4,r19
+ 8006b1c:	403ee83a 	callr	r8
+ 8006b20:	10ffffd8 	cmpnei	r3,r2,-1
+ 8006b24:	18005826 	beq	r3,zero,8006c88 <__sflush_r+0x1d4>
+ 8006b28:	80c0030b 	ldhu	r3,12(r16)
+ 8006b2c:	82000a17 	ldw	r8,40(r16)
+ 8006b30:	81400717 	ldw	r5,28(r16)
+ 8006b34:	18c0010c 	andi	r3,r3,4
+ 8006b38:	18000626 	beq	r3,zero,8006b54 <__sflush_r+0xa0>
+ 8006b3c:	81000117 	ldw	r4,4(r16)
+ 8006b40:	80c00c17 	ldw	r3,48(r16)
+ 8006b44:	1105c83a 	sub	r2,r2,r4
+ 8006b48:	18000226 	beq	r3,zero,8006b54 <__sflush_r+0xa0>
+ 8006b4c:	80c00f17 	ldw	r3,60(r16)
+ 8006b50:	10c5c83a 	sub	r2,r2,r3
+ 8006b54:	000f883a 	mov	r7,zero
+ 8006b58:	100d883a 	mov	r6,r2
+ 8006b5c:	9809883a 	mov	r4,r19
+ 8006b60:	403ee83a 	callr	r8
+ 8006b64:	10ffffd8 	cmpnei	r3,r2,-1
+ 8006b68:	18003d1e 	bne	r3,zero,8006c60 <__sflush_r+0x1ac>
+ 8006b6c:	99000017 	ldw	r4,0(r19)
+ 8006b70:	80c0030b 	ldhu	r3,12(r16)
+ 8006b74:	20004e26 	beq	r4,zero,8006cb0 <__sflush_r+0x1fc>
+ 8006b78:	21400760 	cmpeqi	r5,r4,29
+ 8006b7c:	2800021e 	bne	r5,zero,8006b88 <__sflush_r+0xd4>
+ 8006b80:	210005a0 	cmpeqi	r4,r4,22
+ 8006b84:	20002c26 	beq	r4,zero,8006c38 <__sflush_r+0x184>
+ 8006b88:	80800417 	ldw	r2,16(r16)
+ 8006b8c:	18fdffcc 	andi	r3,r3,63487
+ 8006b90:	80c0030d 	sth	r3,12(r16)
+ 8006b94:	80000115 	stw	zero,4(r16)
+ 8006b98:	80800015 	stw	r2,0(r16)
+ 8006b9c:	81400c17 	ldw	r5,48(r16)
+ 8006ba0:	9c400015 	stw	r17,0(r19)
+ 8006ba4:	28000526 	beq	r5,zero,8006bbc <__sflush_r+0x108>
+ 8006ba8:	80801004 	addi	r2,r16,64
+ 8006bac:	28800226 	beq	r5,r2,8006bb8 <__sflush_r+0x104>
+ 8006bb0:	9809883a 	mov	r4,r19
+ 8006bb4:	80071c40 	call	80071c4 <_free_r>
+ 8006bb8:	80000c15 	stw	zero,48(r16)
+ 8006bbc:	0005883a 	mov	r2,zero
+ 8006bc0:	dfc00417 	ldw	ra,16(sp)
+ 8006bc4:	dcc00317 	ldw	r19,12(sp)
+ 8006bc8:	dc800217 	ldw	r18,8(sp)
+ 8006bcc:	dc400117 	ldw	r17,4(sp)
+ 8006bd0:	dc000017 	ldw	r16,0(sp)
+ 8006bd4:	dec00504 	addi	sp,sp,20
+ 8006bd8:	f800283a 	ret
+ 8006bdc:	2c800417 	ldw	r18,16(r5)
+ 8006be0:	903ff626 	beq	r18,zero,8006bbc <__sflush_r+0x108>
+ 8006be4:	2c400017 	ldw	r17,0(r5)
+ 8006be8:	108000cc 	andi	r2,r2,3
+ 8006bec:	2c800015 	stw	r18,0(r5)
+ 8006bf0:	8ca3c83a 	sub	r17,r17,r18
+ 8006bf4:	1000161e 	bne	r2,zero,8006c50 <__sflush_r+0x19c>
+ 8006bf8:	28800517 	ldw	r2,20(r5)
+ 8006bfc:	80800215 	stw	r2,8(r16)
+ 8006c00:	04400316 	blt	zero,r17,8006c10 <__sflush_r+0x15c>
+ 8006c04:	003fed06 	br	8006bbc <__sflush_r+0x108>
+ 8006c08:	90a5883a 	add	r18,r18,r2
+ 8006c0c:	047feb0e 	bge	zero,r17,8006bbc <__sflush_r+0x108>
+ 8006c10:	80800917 	ldw	r2,36(r16)
+ 8006c14:	81400717 	ldw	r5,28(r16)
+ 8006c18:	880f883a 	mov	r7,r17
+ 8006c1c:	900d883a 	mov	r6,r18
+ 8006c20:	9809883a 	mov	r4,r19
+ 8006c24:	103ee83a 	callr	r2
+ 8006c28:	88a3c83a 	sub	r17,r17,r2
+ 8006c2c:	00bff616 	blt	zero,r2,8006c08 <__sflush_r+0x154>
+ 8006c30:	80c0030b 	ldhu	r3,12(r16)
+ 8006c34:	00bfffc4 	movi	r2,-1
+ 8006c38:	18c01014 	ori	r3,r3,64
+ 8006c3c:	80c0030d 	sth	r3,12(r16)
+ 8006c40:	003fdf06 	br	8006bc0 <__sflush_r+0x10c>
+ 8006c44:	28c00f17 	ldw	r3,60(r5)
+ 8006c48:	00ffa916 	blt	zero,r3,8006af0 <__sflush_r+0x3c>
+ 8006c4c:	003fdb06 	br	8006bbc <__sflush_r+0x108>
+ 8006c50:	0005883a 	mov	r2,zero
+ 8006c54:	003fe906 	br	8006bfc <__sflush_r+0x148>
+ 8006c58:	80801417 	ldw	r2,80(r16)
+ 8006c5c:	003fb506 	br	8006b34 <__sflush_r+0x80>
+ 8006c60:	80c0030b 	ldhu	r3,12(r16)
+ 8006c64:	81000417 	ldw	r4,16(r16)
+ 8006c68:	80000115 	stw	zero,4(r16)
+ 8006c6c:	197dffcc 	andi	r5,r3,63487
+ 8006c70:	8140030d 	sth	r5,12(r16)
+ 8006c74:	81000015 	stw	r4,0(r16)
+ 8006c78:	18c4000c 	andi	r3,r3,4096
+ 8006c7c:	183fc726 	beq	r3,zero,8006b9c <__sflush_r+0xe8>
+ 8006c80:	80801415 	stw	r2,80(r16)
+ 8006c84:	003fc506 	br	8006b9c <__sflush_r+0xe8>
+ 8006c88:	98c00017 	ldw	r3,0(r19)
+ 8006c8c:	183fa626 	beq	r3,zero,8006b28 <__sflush_r+0x74>
+ 8006c90:	19000760 	cmpeqi	r4,r3,29
+ 8006c94:	20000e1e 	bne	r4,zero,8006cd0 <__sflush_r+0x21c>
+ 8006c98:	18c00598 	cmpnei	r3,r3,22
+ 8006c9c:	18000c26 	beq	r3,zero,8006cd0 <__sflush_r+0x21c>
+ 8006ca0:	80c0030b 	ldhu	r3,12(r16)
+ 8006ca4:	18c01014 	ori	r3,r3,64
+ 8006ca8:	80c0030d 	sth	r3,12(r16)
+ 8006cac:	003fc406 	br	8006bc0 <__sflush_r+0x10c>
+ 8006cb0:	81000417 	ldw	r4,16(r16)
+ 8006cb4:	197dffcc 	andi	r5,r3,63487
+ 8006cb8:	8140030d 	sth	r5,12(r16)
+ 8006cbc:	80000115 	stw	zero,4(r16)
+ 8006cc0:	81000015 	stw	r4,0(r16)
+ 8006cc4:	18c4000c 	andi	r3,r3,4096
+ 8006cc8:	183fb426 	beq	r3,zero,8006b9c <__sflush_r+0xe8>
+ 8006ccc:	003fec06 	br	8006c80 <__sflush_r+0x1cc>
+ 8006cd0:	9c400015 	stw	r17,0(r19)
+ 8006cd4:	0005883a 	mov	r2,zero
+ 8006cd8:	003fb906 	br	8006bc0 <__sflush_r+0x10c>
+
+08006cdc <_fflush_r>:
+ 8006cdc:	defffd04 	addi	sp,sp,-12
+ 8006ce0:	dc000115 	stw	r16,4(sp)
+ 8006ce4:	dfc00215 	stw	ra,8(sp)
+ 8006ce8:	2021883a 	mov	r16,r4
+ 8006cec:	20000226 	beq	r4,zero,8006cf8 <_fflush_r+0x1c>
+ 8006cf0:	20800e17 	ldw	r2,56(r4)
+ 8006cf4:	10000726 	beq	r2,zero,8006d14 <_fflush_r+0x38>
+ 8006cf8:	2880030f 	ldh	r2,12(r5)
+ 8006cfc:	10000a1e 	bne	r2,zero,8006d28 <_fflush_r+0x4c>
+ 8006d00:	0005883a 	mov	r2,zero
+ 8006d04:	dfc00217 	ldw	ra,8(sp)
+ 8006d08:	dc000117 	ldw	r16,4(sp)
+ 8006d0c:	dec00304 	addi	sp,sp,12
+ 8006d10:	f800283a 	ret
+ 8006d14:	d9400015 	stw	r5,0(sp)
+ 8006d18:	80070600 	call	8007060 <__sinit>
+ 8006d1c:	d9400017 	ldw	r5,0(sp)
+ 8006d20:	2880030f 	ldh	r2,12(r5)
+ 8006d24:	103ff626 	beq	r2,zero,8006d00 <_fflush_r+0x24>
+ 8006d28:	8009883a 	mov	r4,r16
+ 8006d2c:	dfc00217 	ldw	ra,8(sp)
+ 8006d30:	dc000117 	ldw	r16,4(sp)
+ 8006d34:	dec00304 	addi	sp,sp,12
+ 8006d38:	8006ab41 	jmpi	8006ab4 <__sflush_r>
+
+08006d3c <fflush>:
+ 8006d3c:	200b883a 	mov	r5,r4
+ 8006d40:	20000326 	beq	r4,zero,8006d50 <fflush+0x14>
+ 8006d44:	00820174 	movhi	r2,2053
+ 8006d48:	1132af17 	ldw	r4,-13636(r2)
+ 8006d4c:	8006cdc1 	jmpi	8006cdc <_fflush_r>
+ 8006d50:	00820174 	movhi	r2,2053
+ 8006d54:	1132ae17 	ldw	r4,-13640(r2)
+ 8006d58:	01420034 	movhi	r5,2048
+ 8006d5c:	295b3704 	addi	r5,r5,27868
+ 8006d60:	8007a281 	jmpi	8007a28 <_fwalk_reent>
+
+08006d64 <__fp_lock>:
+ 8006d64:	0005883a 	mov	r2,zero
+ 8006d68:	f800283a 	ret
+
+08006d6c <_cleanup_r>:
+ 8006d6c:	01420074 	movhi	r5,2049
+ 8006d70:	296eb904 	addi	r5,r5,-17692
+ 8006d74:	8007a281 	jmpi	8007a28 <_fwalk_reent>
+
+08006d78 <__sinit.part.0>:
+ 8006d78:	00c20034 	movhi	r3,2048
+ 8006d7c:	20800117 	ldw	r2,4(r4)
+ 8006d80:	18db5b04 	addi	r3,r3,28012
+ 8006d84:	20c00f15 	stw	r3,60(r4)
+ 8006d88:	2140bb04 	addi	r5,r4,748
+ 8006d8c:	00c000c4 	movi	r3,3
+ 8006d90:	20c0b915 	stw	r3,740(r4)
+ 8006d94:	2140ba15 	stw	r5,744(r4)
+ 8006d98:	2000b815 	stw	zero,736(r4)
+ 8006d9c:	10001705 	stb	zero,92(r2)
+ 8006da0:	10001745 	stb	zero,93(r2)
+ 8006da4:	10001785 	stb	zero,94(r2)
+ 8006da8:	100017c5 	stb	zero,95(r2)
+ 8006dac:	10001805 	stb	zero,96(r2)
+ 8006db0:	10001845 	stb	zero,97(r2)
+ 8006db4:	10001885 	stb	zero,98(r2)
+ 8006db8:	100018c5 	stb	zero,99(r2)
+ 8006dbc:	00c00104 	movi	r3,4
+ 8006dc0:	10c00315 	stw	r3,12(r2)
+ 8006dc4:	02020074 	movhi	r8,2049
+ 8006dc8:	20c00217 	ldw	r3,8(r4)
+ 8006dcc:	01c20074 	movhi	r7,2049
+ 8006dd0:	01820074 	movhi	r6,2049
+ 8006dd4:	01420074 	movhi	r5,2049
+ 8006dd8:	42287104 	addi	r8,r8,-24124
+ 8006ddc:	39e88804 	addi	r7,r7,-24032
+ 8006de0:	31a8a804 	addi	r6,r6,-23904
+ 8006de4:	2968bf04 	addi	r5,r5,-23812
+ 8006de8:	02400074 	movhi	r9,1
+ 8006dec:	10001915 	stw	zero,100(r2)
+ 8006df0:	10000015 	stw	zero,0(r2)
+ 8006df4:	10000115 	stw	zero,4(r2)
+ 8006df8:	10000215 	stw	zero,8(r2)
+ 8006dfc:	10000415 	stw	zero,16(r2)
+ 8006e00:	10000515 	stw	zero,20(r2)
+ 8006e04:	10000615 	stw	zero,24(r2)
+ 8006e08:	10800715 	stw	r2,28(r2)
+ 8006e0c:	12000815 	stw	r8,32(r2)
+ 8006e10:	11c00915 	stw	r7,36(r2)
+ 8006e14:	11800a15 	stw	r6,40(r2)
+ 8006e18:	11400b15 	stw	r5,44(r2)
+ 8006e1c:	4a400284 	addi	r9,r9,10
+ 8006e20:	1a400315 	stw	r9,12(r3)
+ 8006e24:	18001915 	stw	zero,100(r3)
+ 8006e28:	18000015 	stw	zero,0(r3)
+ 8006e2c:	18000115 	stw	zero,4(r3)
+ 8006e30:	18000215 	stw	zero,8(r3)
+ 8006e34:	18000415 	stw	zero,16(r3)
+ 8006e38:	18001705 	stb	zero,92(r3)
+ 8006e3c:	18001745 	stb	zero,93(r3)
+ 8006e40:	18001785 	stb	zero,94(r3)
+ 8006e44:	180017c5 	stb	zero,95(r3)
+ 8006e48:	18001805 	stb	zero,96(r3)
+ 8006e4c:	18001845 	stb	zero,97(r3)
+ 8006e50:	18001885 	stb	zero,98(r3)
+ 8006e54:	180018c5 	stb	zero,99(r3)
+ 8006e58:	20800317 	ldw	r2,12(r4)
+ 8006e5c:	024000b4 	movhi	r9,2
+ 8006e60:	18000515 	stw	zero,20(r3)
+ 8006e64:	18000615 	stw	zero,24(r3)
+ 8006e68:	18c00715 	stw	r3,28(r3)
+ 8006e6c:	1a000815 	stw	r8,32(r3)
+ 8006e70:	19c00915 	stw	r7,36(r3)
+ 8006e74:	19800a15 	stw	r6,40(r3)
+ 8006e78:	19400b15 	stw	r5,44(r3)
+ 8006e7c:	4a400484 	addi	r9,r9,18
+ 8006e80:	10001915 	stw	zero,100(r2)
+ 8006e84:	10000015 	stw	zero,0(r2)
+ 8006e88:	10000115 	stw	zero,4(r2)
+ 8006e8c:	10000215 	stw	zero,8(r2)
+ 8006e90:	12400315 	stw	r9,12(r2)
+ 8006e94:	10000415 	stw	zero,16(r2)
+ 8006e98:	10000515 	stw	zero,20(r2)
+ 8006e9c:	10000615 	stw	zero,24(r2)
+ 8006ea0:	10001705 	stb	zero,92(r2)
+ 8006ea4:	10001745 	stb	zero,93(r2)
+ 8006ea8:	10001785 	stb	zero,94(r2)
+ 8006eac:	100017c5 	stb	zero,95(r2)
+ 8006eb0:	10001805 	stb	zero,96(r2)
+ 8006eb4:	10001845 	stb	zero,97(r2)
+ 8006eb8:	10001885 	stb	zero,98(r2)
+ 8006ebc:	100018c5 	stb	zero,99(r2)
+ 8006ec0:	10800715 	stw	r2,28(r2)
+ 8006ec4:	12000815 	stw	r8,32(r2)
+ 8006ec8:	11c00915 	stw	r7,36(r2)
+ 8006ecc:	11800a15 	stw	r6,40(r2)
+ 8006ed0:	11400b15 	stw	r5,44(r2)
+ 8006ed4:	00800044 	movi	r2,1
+ 8006ed8:	20800e15 	stw	r2,56(r4)
+ 8006edc:	f800283a 	ret
+
+08006ee0 <__fp_unlock>:
+ 8006ee0:	0005883a 	mov	r2,zero
+ 8006ee4:	f800283a 	ret
+
+08006ee8 <__sfmoreglue>:
+ 8006ee8:	defffc04 	addi	sp,sp,-16
+ 8006eec:	dc400115 	stw	r17,4(sp)
+ 8006ef0:	2c7fffc4 	addi	r17,r5,-1
+ 8006ef4:	8c401a24 	muli	r17,r17,104
+ 8006ef8:	dc800215 	stw	r18,8(sp)
+ 8006efc:	2825883a 	mov	r18,r5
+ 8006f00:	89401d04 	addi	r5,r17,116
+ 8006f04:	dc000015 	stw	r16,0(sp)
+ 8006f08:	dfc00315 	stw	ra,12(sp)
+ 8006f0c:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8006f10:	1021883a 	mov	r16,r2
+ 8006f14:	10000726 	beq	r2,zero,8006f34 <__sfmoreglue+0x4c>
+ 8006f18:	11000304 	addi	r4,r2,12
+ 8006f1c:	10000015 	stw	zero,0(r2)
+ 8006f20:	14800115 	stw	r18,4(r2)
+ 8006f24:	11000215 	stw	r4,8(r2)
+ 8006f28:	89801a04 	addi	r6,r17,104
+ 8006f2c:	000b883a 	mov	r5,zero
+ 8006f30:	80088e40 	call	80088e4 <memset>
+ 8006f34:	8005883a 	mov	r2,r16
+ 8006f38:	dfc00317 	ldw	ra,12(sp)
+ 8006f3c:	dc800217 	ldw	r18,8(sp)
+ 8006f40:	dc400117 	ldw	r17,4(sp)
+ 8006f44:	dc000017 	ldw	r16,0(sp)
+ 8006f48:	dec00404 	addi	sp,sp,16
+ 8006f4c:	f800283a 	ret
+
+08006f50 <__sfp>:
+ 8006f50:	defffd04 	addi	sp,sp,-12
+ 8006f54:	00820174 	movhi	r2,2053
+ 8006f58:	dc000015 	stw	r16,0(sp)
+ 8006f5c:	1432ae17 	ldw	r16,-13640(r2)
+ 8006f60:	dc400115 	stw	r17,4(sp)
+ 8006f64:	dfc00215 	stw	ra,8(sp)
+ 8006f68:	80800e17 	ldw	r2,56(r16)
+ 8006f6c:	2023883a 	mov	r17,r4
+ 8006f70:	10002b26 	beq	r2,zero,8007020 <__sfp+0xd0>
+ 8006f74:	8400b804 	addi	r16,r16,736
+ 8006f78:	80c00117 	ldw	r3,4(r16)
+ 8006f7c:	80800217 	ldw	r2,8(r16)
+ 8006f80:	18ffffc4 	addi	r3,r3,-1
+ 8006f84:	1800050e 	bge	r3,zero,8006f9c <__sfp+0x4c>
+ 8006f88:	00002106 	br	8007010 <__sfp+0xc0>
+ 8006f8c:	18ffffc4 	addi	r3,r3,-1
+ 8006f90:	193fffd8 	cmpnei	r4,r3,-1
+ 8006f94:	10801a04 	addi	r2,r2,104
+ 8006f98:	20001d26 	beq	r4,zero,8007010 <__sfp+0xc0>
+ 8006f9c:	1100030f 	ldh	r4,12(r2)
+ 8006fa0:	203ffa1e 	bne	r4,zero,8006f8c <__sfp+0x3c>
+ 8006fa4:	00fffff4 	movhi	r3,65535
+ 8006fa8:	18c00044 	addi	r3,r3,1
+ 8006fac:	10001915 	stw	zero,100(r2)
+ 8006fb0:	10000015 	stw	zero,0(r2)
+ 8006fb4:	10000115 	stw	zero,4(r2)
+ 8006fb8:	10000215 	stw	zero,8(r2)
+ 8006fbc:	10c00315 	stw	r3,12(r2)
+ 8006fc0:	10000415 	stw	zero,16(r2)
+ 8006fc4:	10000515 	stw	zero,20(r2)
+ 8006fc8:	10000615 	stw	zero,24(r2)
+ 8006fcc:	10001705 	stb	zero,92(r2)
+ 8006fd0:	10001745 	stb	zero,93(r2)
+ 8006fd4:	10001785 	stb	zero,94(r2)
+ 8006fd8:	100017c5 	stb	zero,95(r2)
+ 8006fdc:	10001805 	stb	zero,96(r2)
+ 8006fe0:	10001845 	stb	zero,97(r2)
+ 8006fe4:	10001885 	stb	zero,98(r2)
+ 8006fe8:	100018c5 	stb	zero,99(r2)
+ 8006fec:	10000c15 	stw	zero,48(r2)
+ 8006ff0:	10000d15 	stw	zero,52(r2)
+ 8006ff4:	10001115 	stw	zero,68(r2)
+ 8006ff8:	10001215 	stw	zero,72(r2)
+ 8006ffc:	dfc00217 	ldw	ra,8(sp)
+ 8007000:	dc400117 	ldw	r17,4(sp)
+ 8007004:	dc000017 	ldw	r16,0(sp)
+ 8007008:	dec00304 	addi	sp,sp,12
+ 800700c:	f800283a 	ret
+ 8007010:	80800017 	ldw	r2,0(r16)
+ 8007014:	10000526 	beq	r2,zero,800702c <__sfp+0xdc>
+ 8007018:	1021883a 	mov	r16,r2
+ 800701c:	003fd606 	br	8006f78 <__sfp+0x28>
+ 8007020:	8009883a 	mov	r4,r16
+ 8007024:	8006d780 	call	8006d78 <__sinit.part.0>
+ 8007028:	003fd206 	br	8006f74 <__sfp+0x24>
+ 800702c:	01400104 	movi	r5,4
+ 8007030:	8809883a 	mov	r4,r17
+ 8007034:	8006ee80 	call	8006ee8 <__sfmoreglue>
+ 8007038:	80800015 	stw	r2,0(r16)
+ 800703c:	103ff61e 	bne	r2,zero,8007018 <__sfp+0xc8>
+ 8007040:	00c00304 	movi	r3,12
+ 8007044:	88c00015 	stw	r3,0(r17)
+ 8007048:	003fec06 	br	8006ffc <__sfp+0xac>
+
+0800704c <_cleanup>:
+ 800704c:	00820174 	movhi	r2,2053
+ 8007050:	1132ae17 	ldw	r4,-13640(r2)
+ 8007054:	01420074 	movhi	r5,2049
+ 8007058:	296eb904 	addi	r5,r5,-17692
+ 800705c:	8007a281 	jmpi	8007a28 <_fwalk_reent>
+
+08007060 <__sinit>:
+ 8007060:	20800e17 	ldw	r2,56(r4)
+ 8007064:	10000126 	beq	r2,zero,800706c <__sinit+0xc>
+ 8007068:	f800283a 	ret
+ 800706c:	8006d781 	jmpi	8006d78 <__sinit.part.0>
+
+08007070 <__sfp_lock_acquire>:
+ 8007070:	f800283a 	ret
+
+08007074 <__sfp_lock_release>:
+ 8007074:	f800283a 	ret
+
+08007078 <__sinit_lock_acquire>:
+ 8007078:	f800283a 	ret
+
+0800707c <__sinit_lock_release>:
+ 800707c:	f800283a 	ret
+
+08007080 <__fp_lock_all>:
+ 8007080:	00820174 	movhi	r2,2053
+ 8007084:	1132af17 	ldw	r4,-13636(r2)
+ 8007088:	01420034 	movhi	r5,2048
+ 800708c:	295b5904 	addi	r5,r5,28004
+ 8007090:	80079841 	jmpi	8007984 <_fwalk>
+
+08007094 <__fp_unlock_all>:
+ 8007094:	00820174 	movhi	r2,2053
+ 8007098:	1132af17 	ldw	r4,-13636(r2)
+ 800709c:	01420034 	movhi	r5,2048
+ 80070a0:	295bb804 	addi	r5,r5,28384
+ 80070a4:	80079841 	jmpi	8007984 <_fwalk>
+
+080070a8 <_malloc_trim_r>:
+ 80070a8:	defffb04 	addi	sp,sp,-20
+ 80070ac:	dcc00315 	stw	r19,12(sp)
+ 80070b0:	04c20174 	movhi	r19,2053
+ 80070b4:	dc800215 	stw	r18,8(sp)
+ 80070b8:	dc400115 	stw	r17,4(sp)
+ 80070bc:	dc000015 	stw	r16,0(sp)
+ 80070c0:	dfc00415 	stw	ra,16(sp)
+ 80070c4:	2821883a 	mov	r16,r5
+ 80070c8:	9cefa904 	addi	r19,r19,-16732
+ 80070cc:	2025883a 	mov	r18,r4
+ 80070d0:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 80070d4:	98800217 	ldw	r2,8(r19)
+ 80070d8:	14400117 	ldw	r17,4(r2)
+ 80070dc:	00bfff04 	movi	r2,-4
+ 80070e0:	88a2703a 	and	r17,r17,r2
+ 80070e4:	8c21c83a 	sub	r16,r17,r16
+ 80070e8:	8403fbc4 	addi	r16,r16,4079
+ 80070ec:	8020d33a 	srli	r16,r16,12
+ 80070f0:	843fffc4 	addi	r16,r16,-1
+ 80070f4:	8020933a 	slli	r16,r16,12
+ 80070f8:	80840008 	cmpgei	r2,r16,4096
+ 80070fc:	10000626 	beq	r2,zero,8007118 <_malloc_trim_r+0x70>
+ 8007100:	000b883a 	mov	r5,zero
+ 8007104:	9009883a 	mov	r4,r18
+ 8007108:	800a16c0 	call	800a16c <_sbrk_r>
+ 800710c:	98c00217 	ldw	r3,8(r19)
+ 8007110:	1c47883a 	add	r3,r3,r17
+ 8007114:	10c00a26 	beq	r2,r3,8007140 <_malloc_trim_r+0x98>
+ 8007118:	9009883a 	mov	r4,r18
+ 800711c:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8007120:	0005883a 	mov	r2,zero
+ 8007124:	dfc00417 	ldw	ra,16(sp)
+ 8007128:	dcc00317 	ldw	r19,12(sp)
+ 800712c:	dc800217 	ldw	r18,8(sp)
+ 8007130:	dc400117 	ldw	r17,4(sp)
+ 8007134:	dc000017 	ldw	r16,0(sp)
+ 8007138:	dec00504 	addi	sp,sp,20
+ 800713c:	f800283a 	ret
+ 8007140:	040bc83a 	sub	r5,zero,r16
+ 8007144:	9009883a 	mov	r4,r18
+ 8007148:	800a16c0 	call	800a16c <_sbrk_r>
+ 800714c:	10bfffd8 	cmpnei	r2,r2,-1
+ 8007150:	10000d26 	beq	r2,zero,8007188 <_malloc_trim_r+0xe0>
+ 8007154:	00820174 	movhi	r2,2053
+ 8007158:	10b36417 	ldw	r2,-12912(r2)
+ 800715c:	98c00217 	ldw	r3,8(r19)
+ 8007160:	8c23c83a 	sub	r17,r17,r16
+ 8007164:	8c400054 	ori	r17,r17,1
+ 8007168:	1421c83a 	sub	r16,r2,r16
+ 800716c:	1c400115 	stw	r17,4(r3)
+ 8007170:	00820174 	movhi	r2,2053
+ 8007174:	9009883a 	mov	r4,r18
+ 8007178:	14336415 	stw	r16,-12912(r2)
+ 800717c:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8007180:	00800044 	movi	r2,1
+ 8007184:	003fe706 	br	8007124 <_malloc_trim_r+0x7c>
+ 8007188:	000b883a 	mov	r5,zero
+ 800718c:	9009883a 	mov	r4,r18
+ 8007190:	800a16c0 	call	800a16c <_sbrk_r>
+ 8007194:	99000217 	ldw	r4,8(r19)
+ 8007198:	1107c83a 	sub	r3,r2,r4
+ 800719c:	19400410 	cmplti	r5,r3,16
+ 80071a0:	283fdd1e 	bne	r5,zero,8007118 <_malloc_trim_r+0x70>
+ 80071a4:	01420174 	movhi	r5,2053
+ 80071a8:	2972b017 	ldw	r5,-13632(r5)
+ 80071ac:	18c00054 	ori	r3,r3,1
+ 80071b0:	20c00115 	stw	r3,4(r4)
+ 80071b4:	1145c83a 	sub	r2,r2,r5
+ 80071b8:	01420174 	movhi	r5,2053
+ 80071bc:	28b36415 	stw	r2,-12912(r5)
+ 80071c0:	003fd506 	br	8007118 <_malloc_trim_r+0x70>
+
+080071c4 <_free_r>:
+ 80071c4:	28004f26 	beq	r5,zero,8007304 <_free_r+0x140>
+ 80071c8:	defffd04 	addi	sp,sp,-12
+ 80071cc:	dc400115 	stw	r17,4(sp)
+ 80071d0:	dc000015 	stw	r16,0(sp)
+ 80071d4:	2023883a 	mov	r17,r4
+ 80071d8:	2821883a 	mov	r16,r5
+ 80071dc:	dfc00215 	stw	ra,8(sp)
+ 80071e0:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 80071e4:	81ffff17 	ldw	r7,-4(r16)
+ 80071e8:	00bfff84 	movi	r2,-2
+ 80071ec:	80fffe04 	addi	r3,r16,-8
+ 80071f0:	3884703a 	and	r2,r7,r2
+ 80071f4:	01820174 	movhi	r6,2053
+ 80071f8:	1889883a 	add	r4,r3,r2
+ 80071fc:	31afa904 	addi	r6,r6,-16732
+ 8007200:	21400117 	ldw	r5,4(r4)
+ 8007204:	32000217 	ldw	r8,8(r6)
+ 8007208:	027fff04 	movi	r9,-4
+ 800720c:	2a4a703a 	and	r5,r5,r9
+ 8007210:	41006426 	beq	r8,r4,80073a4 <_free_r+0x1e0>
+ 8007214:	21400115 	stw	r5,4(r4)
+ 8007218:	39c0004c 	andi	r7,r7,1
+ 800721c:	2151883a 	add	r8,r4,r5
+ 8007220:	3800281e 	bne	r7,zero,80072c4 <_free_r+0x100>
+ 8007224:	82bffe17 	ldw	r10,-8(r16)
+ 8007228:	42000117 	ldw	r8,4(r8)
+ 800722c:	01c20174 	movhi	r7,2053
+ 8007230:	1a87c83a 	sub	r3,r3,r10
+ 8007234:	1a400217 	ldw	r9,8(r3)
+ 8007238:	39efab04 	addi	r7,r7,-16724
+ 800723c:	1285883a 	add	r2,r2,r10
+ 8007240:	4200004c 	andi	r8,r8,1
+ 8007244:	49c04c26 	beq	r9,r7,8007378 <_free_r+0x1b4>
+ 8007248:	1a800317 	ldw	r10,12(r3)
+ 800724c:	4a800315 	stw	r10,12(r9)
+ 8007250:	52400215 	stw	r9,8(r10)
+ 8007254:	40007126 	beq	r8,zero,800741c <_free_r+0x258>
+ 8007258:	11400054 	ori	r5,r2,1
+ 800725c:	19400115 	stw	r5,4(r3)
+ 8007260:	20800015 	stw	r2,0(r4)
+ 8007264:	11008028 	cmpgeui	r4,r2,512
+ 8007268:	20002c1e 	bne	r4,zero,800731c <_free_r+0x158>
+ 800726c:	1008d0fa 	srli	r4,r2,3
+ 8007270:	31c00117 	ldw	r7,4(r6)
+ 8007274:	20800044 	addi	r2,r4,1
+ 8007278:	200bd0ba 	srai	r5,r4,2
+ 800727c:	100490fa 	slli	r2,r2,3
+ 8007280:	01000044 	movi	r4,1
+ 8007284:	2148983a 	sll	r4,r4,r5
+ 8007288:	3085883a 	add	r2,r6,r2
+ 800728c:	11400017 	ldw	r5,0(r2)
+ 8007290:	21c8b03a 	or	r4,r4,r7
+ 8007294:	11fffe04 	addi	r7,r2,-8
+ 8007298:	19c00315 	stw	r7,12(r3)
+ 800729c:	19400215 	stw	r5,8(r3)
+ 80072a0:	31000115 	stw	r4,4(r6)
+ 80072a4:	10c00015 	stw	r3,0(r2)
+ 80072a8:	28c00315 	stw	r3,12(r5)
+ 80072ac:	8809883a 	mov	r4,r17
+ 80072b0:	dfc00217 	ldw	ra,8(sp)
+ 80072b4:	dc400117 	ldw	r17,4(sp)
+ 80072b8:	dc000017 	ldw	r16,0(sp)
+ 80072bc:	dec00304 	addi	sp,sp,12
+ 80072c0:	800ff2c1 	jmpi	800ff2c <__malloc_unlock>
+ 80072c4:	41c00117 	ldw	r7,4(r8)
+ 80072c8:	39c0004c 	andi	r7,r7,1
+ 80072cc:	38000e1e 	bne	r7,zero,8007308 <_free_r+0x144>
+ 80072d0:	01c20174 	movhi	r7,2053
+ 80072d4:	1145883a 	add	r2,r2,r5
+ 80072d8:	39efab04 	addi	r7,r7,-16724
+ 80072dc:	21400217 	ldw	r5,8(r4)
+ 80072e0:	12400054 	ori	r9,r2,1
+ 80072e4:	1891883a 	add	r8,r3,r2
+ 80072e8:	29c05226 	beq	r5,r7,8007434 <_free_r+0x270>
+ 80072ec:	21000317 	ldw	r4,12(r4)
+ 80072f0:	29000315 	stw	r4,12(r5)
+ 80072f4:	21400215 	stw	r5,8(r4)
+ 80072f8:	1a400115 	stw	r9,4(r3)
+ 80072fc:	40800015 	stw	r2,0(r8)
+ 8007300:	003fd806 	br	8007264 <_free_r+0xa0>
+ 8007304:	f800283a 	ret
+ 8007308:	11400054 	ori	r5,r2,1
+ 800730c:	817fff15 	stw	r5,-4(r16)
+ 8007310:	20800015 	stw	r2,0(r4)
+ 8007314:	11008028 	cmpgeui	r4,r2,512
+ 8007318:	203fd426 	beq	r4,zero,800726c <_free_r+0xa8>
+ 800731c:	1008d27a 	srli	r4,r2,9
+ 8007320:	21400168 	cmpgeui	r5,r4,5
+ 8007324:	2800341e 	bne	r5,zero,80073f8 <_free_r+0x234>
+ 8007328:	1008d1ba 	srli	r4,r2,6
+ 800732c:	21c00e44 	addi	r7,r4,57
+ 8007330:	380e90fa 	slli	r7,r7,3
+ 8007334:	21400e04 	addi	r5,r4,56
+ 8007338:	31cf883a 	add	r7,r6,r7
+ 800733c:	39000017 	ldw	r4,0(r7)
+ 8007340:	39fffe04 	addi	r7,r7,-8
+ 8007344:	39004226 	beq	r7,r4,8007450 <_free_r+0x28c>
+ 8007348:	01bfff04 	movi	r6,-4
+ 800734c:	21400117 	ldw	r5,4(r4)
+ 8007350:	298a703a 	and	r5,r5,r6
+ 8007354:	1140022e 	bgeu	r2,r5,8007360 <_free_r+0x19c>
+ 8007358:	21000217 	ldw	r4,8(r4)
+ 800735c:	393ffb1e 	bne	r7,r4,800734c <_free_r+0x188>
+ 8007360:	21c00317 	ldw	r7,12(r4)
+ 8007364:	19c00315 	stw	r7,12(r3)
+ 8007368:	19000215 	stw	r4,8(r3)
+ 800736c:	38c00215 	stw	r3,8(r7)
+ 8007370:	20c00315 	stw	r3,12(r4)
+ 8007374:	003fcd06 	br	80072ac <_free_r+0xe8>
+ 8007378:	40004d1e 	bne	r8,zero,80074b0 <_free_r+0x2ec>
+ 800737c:	21800317 	ldw	r6,12(r4)
+ 8007380:	21000217 	ldw	r4,8(r4)
+ 8007384:	2885883a 	add	r2,r5,r2
+ 8007388:	11400054 	ori	r5,r2,1
+ 800738c:	21800315 	stw	r6,12(r4)
+ 8007390:	31000215 	stw	r4,8(r6)
+ 8007394:	19400115 	stw	r5,4(r3)
+ 8007398:	1887883a 	add	r3,r3,r2
+ 800739c:	18800015 	stw	r2,0(r3)
+ 80073a0:	003fc206 	br	80072ac <_free_r+0xe8>
+ 80073a4:	39c0004c 	andi	r7,r7,1
+ 80073a8:	1145883a 	add	r2,r2,r5
+ 80073ac:	3800071e 	bne	r7,zero,80073cc <_free_r+0x208>
+ 80073b0:	81fffe17 	ldw	r7,-8(r16)
+ 80073b4:	19c7c83a 	sub	r3,r3,r7
+ 80073b8:	19000317 	ldw	r4,12(r3)
+ 80073bc:	19400217 	ldw	r5,8(r3)
+ 80073c0:	11c5883a 	add	r2,r2,r7
+ 80073c4:	29000315 	stw	r4,12(r5)
+ 80073c8:	21400215 	stw	r5,8(r4)
+ 80073cc:	01020174 	movhi	r4,2053
+ 80073d0:	11400054 	ori	r5,r2,1
+ 80073d4:	2132b117 	ldw	r4,-13628(r4)
+ 80073d8:	19400115 	stw	r5,4(r3)
+ 80073dc:	30c00215 	stw	r3,8(r6)
+ 80073e0:	113fb236 	bltu	r2,r4,80072ac <_free_r+0xe8>
+ 80073e4:	00820174 	movhi	r2,2053
+ 80073e8:	1172ef17 	ldw	r5,-13380(r2)
+ 80073ec:	8809883a 	mov	r4,r17
+ 80073f0:	80070a80 	call	80070a8 <_malloc_trim_r>
+ 80073f4:	003fad06 	br	80072ac <_free_r+0xe8>
+ 80073f8:	21400568 	cmpgeui	r5,r4,21
+ 80073fc:	28000926 	beq	r5,zero,8007424 <_free_r+0x260>
+ 8007400:	21401568 	cmpgeui	r5,r4,85
+ 8007404:	2800191e 	bne	r5,zero,800746c <_free_r+0x2a8>
+ 8007408:	1008d33a 	srli	r4,r2,12
+ 800740c:	21c01bc4 	addi	r7,r4,111
+ 8007410:	21401b84 	addi	r5,r4,110
+ 8007414:	380e90fa 	slli	r7,r7,3
+ 8007418:	003fc706 	br	8007338 <_free_r+0x174>
+ 800741c:	1145883a 	add	r2,r2,r5
+ 8007420:	003fae06 	br	80072dc <_free_r+0x118>
+ 8007424:	21c01704 	addi	r7,r4,92
+ 8007428:	214016c4 	addi	r5,r4,91
+ 800742c:	380e90fa 	slli	r7,r7,3
+ 8007430:	003fc106 	br	8007338 <_free_r+0x174>
+ 8007434:	30c00515 	stw	r3,20(r6)
+ 8007438:	30c00415 	stw	r3,16(r6)
+ 800743c:	19c00315 	stw	r7,12(r3)
+ 8007440:	19c00215 	stw	r7,8(r3)
+ 8007444:	1a400115 	stw	r9,4(r3)
+ 8007448:	40800015 	stw	r2,0(r8)
+ 800744c:	003f9706 	br	80072ac <_free_r+0xe8>
+ 8007450:	280bd0ba 	srai	r5,r5,2
+ 8007454:	00800044 	movi	r2,1
+ 8007458:	32000117 	ldw	r8,4(r6)
+ 800745c:	114a983a 	sll	r5,r2,r5
+ 8007460:	2a0ab03a 	or	r5,r5,r8
+ 8007464:	31400115 	stw	r5,4(r6)
+ 8007468:	003fbe06 	br	8007364 <_free_r+0x1a0>
+ 800746c:	21405568 	cmpgeui	r5,r4,341
+ 8007470:	2800051e 	bne	r5,zero,8007488 <_free_r+0x2c4>
+ 8007474:	1008d3fa 	srli	r4,r2,15
+ 8007478:	21c01e04 	addi	r7,r4,120
+ 800747c:	21401dc4 	addi	r5,r4,119
+ 8007480:	380e90fa 	slli	r7,r7,3
+ 8007484:	003fac06 	br	8007338 <_free_r+0x174>
+ 8007488:	21015568 	cmpgeui	r4,r4,1365
+ 800748c:	2000051e 	bne	r4,zero,80074a4 <_free_r+0x2e0>
+ 8007490:	1008d4ba 	srli	r4,r2,18
+ 8007494:	21c01f44 	addi	r7,r4,125
+ 8007498:	21401f04 	addi	r5,r4,124
+ 800749c:	380e90fa 	slli	r7,r7,3
+ 80074a0:	003fa506 	br	8007338 <_free_r+0x174>
+ 80074a4:	01c0fe04 	movi	r7,1016
+ 80074a8:	01401f84 	movi	r5,126
+ 80074ac:	003fa206 	br	8007338 <_free_r+0x174>
+ 80074b0:	11400054 	ori	r5,r2,1
+ 80074b4:	19400115 	stw	r5,4(r3)
+ 80074b8:	20800015 	stw	r2,0(r4)
+ 80074bc:	003f7b06 	br	80072ac <_free_r+0xe8>
+
+080074c0 <__sfvwrite_r>:
+ 80074c0:	30800217 	ldw	r2,8(r6)
+ 80074c4:	1000c926 	beq	r2,zero,80077ec <__sfvwrite_r+0x32c>
+ 80074c8:	2880030b 	ldhu	r2,12(r5)
+ 80074cc:	defff304 	addi	sp,sp,-52
+ 80074d0:	dd000715 	stw	r20,28(sp)
+ 80074d4:	dc000315 	stw	r16,12(sp)
+ 80074d8:	dfc00c15 	stw	ra,48(sp)
+ 80074dc:	df000b15 	stw	fp,44(sp)
+ 80074e0:	ddc00a15 	stw	r23,40(sp)
+ 80074e4:	dd800915 	stw	r22,36(sp)
+ 80074e8:	dd400815 	stw	r21,32(sp)
+ 80074ec:	dcc00615 	stw	r19,24(sp)
+ 80074f0:	dc800515 	stw	r18,20(sp)
+ 80074f4:	dc400415 	stw	r17,16(sp)
+ 80074f8:	d9000015 	stw	r4,0(sp)
+ 80074fc:	10c0020c 	andi	r3,r2,8
+ 8007500:	2821883a 	mov	r16,r5
+ 8007504:	3029883a 	mov	r20,r6
+ 8007508:	18002426 	beq	r3,zero,800759c <__sfvwrite_r+0xdc>
+ 800750c:	28c00417 	ldw	r3,16(r5)
+ 8007510:	18002226 	beq	r3,zero,800759c <__sfvwrite_r+0xdc>
+ 8007514:	10c0008c 	andi	r3,r2,2
+ 8007518:	a4400017 	ldw	r17,0(r20)
+ 800751c:	18002726 	beq	r3,zero,80075bc <__sfvwrite_r+0xfc>
+ 8007520:	80c00917 	ldw	r3,36(r16)
+ 8007524:	80800717 	ldw	r2,28(r16)
+ 8007528:	05600034 	movhi	r21,32768
+ 800752c:	0027883a 	mov	r19,zero
+ 8007530:	0025883a 	mov	r18,zero
+ 8007534:	ad7f0004 	addi	r21,r21,-1024
+ 8007538:	980d883a 	mov	r6,r19
+ 800753c:	100b883a 	mov	r5,r2
+ 8007540:	d9000017 	ldw	r4,0(sp)
+ 8007544:	90001126 	beq	r18,zero,800758c <__sfvwrite_r+0xcc>
+ 8007548:	900f883a 	mov	r7,r18
+ 800754c:	ac80012e 	bgeu	r21,r18,8007554 <__sfvwrite_r+0x94>
+ 8007550:	a80f883a 	mov	r7,r21
+ 8007554:	183ee83a 	callr	r3
+ 8007558:	00809f0e 	bge	zero,r2,80077d8 <__sfvwrite_r+0x318>
+ 800755c:	a0c00217 	ldw	r3,8(r20)
+ 8007560:	98a7883a 	add	r19,r19,r2
+ 8007564:	90a5c83a 	sub	r18,r18,r2
+ 8007568:	1885c83a 	sub	r2,r3,r2
+ 800756c:	a0800215 	stw	r2,8(r20)
+ 8007570:	10006326 	beq	r2,zero,8007700 <__sfvwrite_r+0x240>
+ 8007574:	80800717 	ldw	r2,28(r16)
+ 8007578:	80c00917 	ldw	r3,36(r16)
+ 800757c:	980d883a 	mov	r6,r19
+ 8007580:	100b883a 	mov	r5,r2
+ 8007584:	d9000017 	ldw	r4,0(sp)
+ 8007588:	903fef1e 	bne	r18,zero,8007548 <__sfvwrite_r+0x88>
+ 800758c:	8cc00017 	ldw	r19,0(r17)
+ 8007590:	8c800117 	ldw	r18,4(r17)
+ 8007594:	8c400204 	addi	r17,r17,8
+ 8007598:	003fe706 	br	8007538 <__sfvwrite_r+0x78>
+ 800759c:	d9000017 	ldw	r4,0(sp)
+ 80075a0:	800b883a 	mov	r5,r16
+ 80075a4:	800507c0 	call	800507c <__swsetup_r>
+ 80075a8:	1000f41e 	bne	r2,zero,800797c <__sfvwrite_r+0x4bc>
+ 80075ac:	8080030b 	ldhu	r2,12(r16)
+ 80075b0:	a4400017 	ldw	r17,0(r20)
+ 80075b4:	10c0008c 	andi	r3,r2,2
+ 80075b8:	183fd91e 	bne	r3,zero,8007520 <__sfvwrite_r+0x60>
+ 80075bc:	10c0004c 	andi	r3,r2,1
+ 80075c0:	84800217 	ldw	r18,8(r16)
+ 80075c4:	87000017 	ldw	fp,0(r16)
+ 80075c8:	18008a1e 	bne	r3,zero,80077f4 <__sfvwrite_r+0x334>
+ 80075cc:	00e00034 	movhi	r3,32768
+ 80075d0:	18ffff84 	addi	r3,r3,-2
+ 80075d4:	01200034 	movhi	r4,32768
+ 80075d8:	d8c00115 	stw	r3,4(sp)
+ 80075dc:	20ffffc4 	addi	r3,r4,-1
+ 80075e0:	002d883a 	mov	r22,zero
+ 80075e4:	002f883a 	mov	r23,zero
+ 80075e8:	d8c00215 	stw	r3,8(sp)
+ 80075ec:	b8004026 	beq	r23,zero,80076f0 <__sfvwrite_r+0x230>
+ 80075f0:	1100800c 	andi	r4,r2,512
+ 80075f4:	20009026 	beq	r4,zero,8007838 <__sfvwrite_r+0x378>
+ 80075f8:	902b883a 	mov	r21,r18
+ 80075fc:	bc80b436 	bltu	r23,r18,80078d0 <__sfvwrite_r+0x410>
+ 8007600:	1101200c 	andi	r4,r2,1152
+ 8007604:	20002526 	beq	r4,zero,800769c <__sfvwrite_r+0x1dc>
+ 8007608:	81800517 	ldw	r6,20(r16)
+ 800760c:	81400417 	ldw	r5,16(r16)
+ 8007610:	b9000044 	addi	r4,r23,1
+ 8007614:	318000e4 	muli	r6,r6,3
+ 8007618:	e167c83a 	sub	r19,fp,r5
+ 800761c:	24c9883a 	add	r4,r4,r19
+ 8007620:	3024d7fa 	srli	r18,r6,31
+ 8007624:	91a5883a 	add	r18,r18,r6
+ 8007628:	9025d07a 	srai	r18,r18,1
+ 800762c:	900d883a 	mov	r6,r18
+ 8007630:	9100022e 	bgeu	r18,r4,800763c <__sfvwrite_r+0x17c>
+ 8007634:	2025883a 	mov	r18,r4
+ 8007638:	200d883a 	mov	r6,r4
+ 800763c:	1081000c 	andi	r2,r2,1024
+ 8007640:	1000bc26 	beq	r2,zero,8007934 <__sfvwrite_r+0x474>
+ 8007644:	d9000017 	ldw	r4,0(sp)
+ 8007648:	300b883a 	mov	r5,r6
+ 800764c:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8007650:	1000c526 	beq	r2,zero,8007968 <__sfvwrite_r+0x4a8>
+ 8007654:	81400417 	ldw	r5,16(r16)
+ 8007658:	980d883a 	mov	r6,r19
+ 800765c:	1009883a 	mov	r4,r2
+ 8007660:	80086b80 	call	80086b8 <memcpy>
+ 8007664:	100f883a 	mov	r7,r2
+ 8007668:	8080030b 	ldhu	r2,12(r16)
+ 800766c:	00fedfc4 	movi	r3,-1153
+ 8007670:	10c4703a 	and	r2,r2,r3
+ 8007674:	10802014 	ori	r2,r2,128
+ 8007678:	8080030d 	sth	r2,12(r16)
+ 800767c:	94c5c83a 	sub	r2,r18,r19
+ 8007680:	3cf9883a 	add	fp,r7,r19
+ 8007684:	84800515 	stw	r18,20(r16)
+ 8007688:	81c00415 	stw	r7,16(r16)
+ 800768c:	87000015 	stw	fp,0(r16)
+ 8007690:	b825883a 	mov	r18,r23
+ 8007694:	80800215 	stw	r2,8(r16)
+ 8007698:	b82b883a 	mov	r21,r23
+ 800769c:	a80d883a 	mov	r6,r21
+ 80076a0:	b00b883a 	mov	r5,r22
+ 80076a4:	e009883a 	mov	r4,fp
+ 80076a8:	80087b80 	call	80087b8 <memmove>
+ 80076ac:	80800217 	ldw	r2,8(r16)
+ 80076b0:	81800017 	ldw	r6,0(r16)
+ 80076b4:	b827883a 	mov	r19,r23
+ 80076b8:	14a5c83a 	sub	r18,r2,r18
+ 80076bc:	354d883a 	add	r6,r6,r21
+ 80076c0:	84800215 	stw	r18,8(r16)
+ 80076c4:	81800015 	stw	r6,0(r16)
+ 80076c8:	002f883a 	mov	r23,zero
+ 80076cc:	a0800217 	ldw	r2,8(r20)
+ 80076d0:	b4ed883a 	add	r22,r22,r19
+ 80076d4:	14e7c83a 	sub	r19,r2,r19
+ 80076d8:	a4c00215 	stw	r19,8(r20)
+ 80076dc:	98000826 	beq	r19,zero,8007700 <__sfvwrite_r+0x240>
+ 80076e0:	8080030b 	ldhu	r2,12(r16)
+ 80076e4:	84800217 	ldw	r18,8(r16)
+ 80076e8:	87000017 	ldw	fp,0(r16)
+ 80076ec:	b83fc01e 	bne	r23,zero,80075f0 <__sfvwrite_r+0x130>
+ 80076f0:	8d800017 	ldw	r22,0(r17)
+ 80076f4:	8dc00117 	ldw	r23,4(r17)
+ 80076f8:	8c400204 	addi	r17,r17,8
+ 80076fc:	003fbb06 	br	80075ec <__sfvwrite_r+0x12c>
+ 8007700:	0005883a 	mov	r2,zero
+ 8007704:	dfc00c17 	ldw	ra,48(sp)
+ 8007708:	df000b17 	ldw	fp,44(sp)
+ 800770c:	ddc00a17 	ldw	r23,40(sp)
+ 8007710:	dd800917 	ldw	r22,36(sp)
+ 8007714:	dd400817 	ldw	r21,32(sp)
+ 8007718:	dd000717 	ldw	r20,28(sp)
+ 800771c:	dcc00617 	ldw	r19,24(sp)
+ 8007720:	dc800517 	ldw	r18,20(sp)
+ 8007724:	dc400417 	ldw	r17,16(sp)
+ 8007728:	dc000317 	ldw	r16,12(sp)
+ 800772c:	dec00d04 	addi	sp,sp,52
+ 8007730:	f800283a 	ret
+ 8007734:	b1c06e16 	blt	r22,r7,80078f0 <__sfvwrite_r+0x430>
+ 8007738:	80800917 	ldw	r2,36(r16)
+ 800773c:	81400717 	ldw	r5,28(r16)
+ 8007740:	d9000017 	ldw	r4,0(sp)
+ 8007744:	b80d883a 	mov	r6,r23
+ 8007748:	103ee83a 	callr	r2
+ 800774c:	1025883a 	mov	r18,r2
+ 8007750:	0080210e 	bge	zero,r2,80077d8 <__sfvwrite_r+0x318>
+ 8007754:	acabc83a 	sub	r21,r21,r18
+ 8007758:	a8006026 	beq	r21,zero,80078dc <__sfvwrite_r+0x41c>
+ 800775c:	00800044 	movi	r2,1
+ 8007760:	a0c00217 	ldw	r3,8(r20)
+ 8007764:	bcaf883a 	add	r23,r23,r18
+ 8007768:	9ca7c83a 	sub	r19,r19,r18
+ 800776c:	1ca5c83a 	sub	r18,r3,r18
+ 8007770:	a4800215 	stw	r18,8(r20)
+ 8007774:	903fe226 	beq	r18,zero,8007700 <__sfvwrite_r+0x240>
+ 8007778:	84800217 	ldw	r18,8(r16)
+ 800777c:	87000017 	ldw	fp,0(r16)
+ 8007780:	98002126 	beq	r19,zero,8007808 <__sfvwrite_r+0x348>
+ 8007784:	10002426 	beq	r2,zero,8007818 <__sfvwrite_r+0x358>
+ 8007788:	a805883a 	mov	r2,r21
+ 800778c:	982d883a 	mov	r22,r19
+ 8007790:	14c0012e 	bgeu	r2,r19,8007798 <__sfvwrite_r+0x2d8>
+ 8007794:	102d883a 	mov	r22,r2
+ 8007798:	80800417 	ldw	r2,16(r16)
+ 800779c:	81c00517 	ldw	r7,20(r16)
+ 80077a0:	173fe42e 	bgeu	r2,fp,8007734 <__sfvwrite_r+0x274>
+ 80077a4:	3ca5883a 	add	r18,r7,r18
+ 80077a8:	95bfe20e 	bge	r18,r22,8007734 <__sfvwrite_r+0x274>
+ 80077ac:	b80b883a 	mov	r5,r23
+ 80077b0:	e009883a 	mov	r4,fp
+ 80077b4:	900d883a 	mov	r6,r18
+ 80077b8:	80087b80 	call	80087b8 <memmove>
+ 80077bc:	80800017 	ldw	r2,0(r16)
+ 80077c0:	d9000017 	ldw	r4,0(sp)
+ 80077c4:	800b883a 	mov	r5,r16
+ 80077c8:	1485883a 	add	r2,r2,r18
+ 80077cc:	80800015 	stw	r2,0(r16)
+ 80077d0:	8006cdc0 	call	8006cdc <_fflush_r>
+ 80077d4:	103fdf26 	beq	r2,zero,8007754 <__sfvwrite_r+0x294>
+ 80077d8:	8080030b 	ldhu	r2,12(r16)
+ 80077dc:	10801014 	ori	r2,r2,64
+ 80077e0:	8080030d 	sth	r2,12(r16)
+ 80077e4:	00bfffc4 	movi	r2,-1
+ 80077e8:	003fc606 	br	8007704 <__sfvwrite_r+0x244>
+ 80077ec:	0005883a 	mov	r2,zero
+ 80077f0:	f800283a 	ret
+ 80077f4:	0027883a 	mov	r19,zero
+ 80077f8:	002b883a 	mov	r21,zero
+ 80077fc:	0005883a 	mov	r2,zero
+ 8007800:	002f883a 	mov	r23,zero
+ 8007804:	983fdf1e 	bne	r19,zero,8007784 <__sfvwrite_r+0x2c4>
+ 8007808:	8cc00117 	ldw	r19,4(r17)
+ 800780c:	8dc00017 	ldw	r23,0(r17)
+ 8007810:	8c400204 	addi	r17,r17,8
+ 8007814:	983ffc26 	beq	r19,zero,8007808 <__sfvwrite_r+0x348>
+ 8007818:	980d883a 	mov	r6,r19
+ 800781c:	01400284 	movi	r5,10
+ 8007820:	b809883a 	mov	r4,r23
+ 8007824:	80085d00 	call	80085d0 <memchr>
+ 8007828:	10003f26 	beq	r2,zero,8007928 <__sfvwrite_r+0x468>
+ 800782c:	10800044 	addi	r2,r2,1
+ 8007830:	15ebc83a 	sub	r21,r2,r23
+ 8007834:	003fd406 	br	8007788 <__sfvwrite_r+0x2c8>
+ 8007838:	80800417 	ldw	r2,16(r16)
+ 800783c:	17001136 	bltu	r2,fp,8007884 <__sfvwrite_r+0x3c4>
+ 8007840:	84c00517 	ldw	r19,20(r16)
+ 8007844:	bcc00f36 	bltu	r23,r19,8007884 <__sfvwrite_r+0x3c4>
+ 8007848:	d8800117 	ldw	r2,4(sp)
+ 800784c:	15c0342e 	bgeu	r2,r23,8007920 <__sfvwrite_r+0x460>
+ 8007850:	d9000217 	ldw	r4,8(sp)
+ 8007854:	980b883a 	mov	r5,r19
+ 8007858:	800cf000 	call	800cf00 <__divsi3>
+ 800785c:	14cf383a 	mul	r7,r2,r19
+ 8007860:	81400717 	ldw	r5,28(r16)
+ 8007864:	80800917 	ldw	r2,36(r16)
+ 8007868:	d9000017 	ldw	r4,0(sp)
+ 800786c:	b00d883a 	mov	r6,r22
+ 8007870:	103ee83a 	callr	r2
+ 8007874:	00bfd80e 	bge	zero,r2,80077d8 <__sfvwrite_r+0x318>
+ 8007878:	1027883a 	mov	r19,r2
+ 800787c:	bcefc83a 	sub	r23,r23,r19
+ 8007880:	003f9206 	br	80076cc <__sfvwrite_r+0x20c>
+ 8007884:	9027883a 	mov	r19,r18
+ 8007888:	bc80012e 	bgeu	r23,r18,8007890 <__sfvwrite_r+0x3d0>
+ 800788c:	b827883a 	mov	r19,r23
+ 8007890:	e009883a 	mov	r4,fp
+ 8007894:	980d883a 	mov	r6,r19
+ 8007898:	b00b883a 	mov	r5,r22
+ 800789c:	80087b80 	call	80087b8 <memmove>
+ 80078a0:	80800217 	ldw	r2,8(r16)
+ 80078a4:	81000017 	ldw	r4,0(r16)
+ 80078a8:	14c5c83a 	sub	r2,r2,r19
+ 80078ac:	24c9883a 	add	r4,r4,r19
+ 80078b0:	80800215 	stw	r2,8(r16)
+ 80078b4:	81000015 	stw	r4,0(r16)
+ 80078b8:	103ff01e 	bne	r2,zero,800787c <__sfvwrite_r+0x3bc>
+ 80078bc:	d9000017 	ldw	r4,0(sp)
+ 80078c0:	800b883a 	mov	r5,r16
+ 80078c4:	8006cdc0 	call	8006cdc <_fflush_r>
+ 80078c8:	103fec26 	beq	r2,zero,800787c <__sfvwrite_r+0x3bc>
+ 80078cc:	003fc206 	br	80077d8 <__sfvwrite_r+0x318>
+ 80078d0:	b825883a 	mov	r18,r23
+ 80078d4:	b82b883a 	mov	r21,r23
+ 80078d8:	003f7006 	br	800769c <__sfvwrite_r+0x1dc>
+ 80078dc:	d9000017 	ldw	r4,0(sp)
+ 80078e0:	800b883a 	mov	r5,r16
+ 80078e4:	8006cdc0 	call	8006cdc <_fflush_r>
+ 80078e8:	103f9d26 	beq	r2,zero,8007760 <__sfvwrite_r+0x2a0>
+ 80078ec:	003fba06 	br	80077d8 <__sfvwrite_r+0x318>
+ 80078f0:	b00d883a 	mov	r6,r22
+ 80078f4:	b80b883a 	mov	r5,r23
+ 80078f8:	e009883a 	mov	r4,fp
+ 80078fc:	80087b80 	call	80087b8 <memmove>
+ 8007900:	80c00217 	ldw	r3,8(r16)
+ 8007904:	80800017 	ldw	r2,0(r16)
+ 8007908:	b025883a 	mov	r18,r22
+ 800790c:	1d87c83a 	sub	r3,r3,r22
+ 8007910:	15ad883a 	add	r22,r2,r22
+ 8007914:	80c00215 	stw	r3,8(r16)
+ 8007918:	85800015 	stw	r22,0(r16)
+ 800791c:	003f8d06 	br	8007754 <__sfvwrite_r+0x294>
+ 8007920:	b809883a 	mov	r4,r23
+ 8007924:	003fcb06 	br	8007854 <__sfvwrite_r+0x394>
+ 8007928:	98800044 	addi	r2,r19,1
+ 800792c:	102b883a 	mov	r21,r2
+ 8007930:	003f9606 	br	800778c <__sfvwrite_r+0x2cc>
+ 8007934:	d9000017 	ldw	r4,0(sp)
+ 8007938:	8009abc0 	call	8009abc <_realloc_r>
+ 800793c:	100f883a 	mov	r7,r2
+ 8007940:	103f4e1e 	bne	r2,zero,800767c <__sfvwrite_r+0x1bc>
+ 8007944:	dc400017 	ldw	r17,0(sp)
+ 8007948:	81400417 	ldw	r5,16(r16)
+ 800794c:	8809883a 	mov	r4,r17
+ 8007950:	80071c40 	call	80071c4 <_free_r>
+ 8007954:	8080030b 	ldhu	r2,12(r16)
+ 8007958:	00c00304 	movi	r3,12
+ 800795c:	88c00015 	stw	r3,0(r17)
+ 8007960:	10bfdfcc 	andi	r2,r2,65407
+ 8007964:	003f9d06 	br	80077dc <__sfvwrite_r+0x31c>
+ 8007968:	d8c00017 	ldw	r3,0(sp)
+ 800796c:	00800304 	movi	r2,12
+ 8007970:	18800015 	stw	r2,0(r3)
+ 8007974:	8080030b 	ldhu	r2,12(r16)
+ 8007978:	003f9806 	br	80077dc <__sfvwrite_r+0x31c>
+ 800797c:	00bfffc4 	movi	r2,-1
+ 8007980:	003f6006 	br	8007704 <__sfvwrite_r+0x244>
+
+08007984 <_fwalk>:
+ 8007984:	defffa04 	addi	sp,sp,-24
+ 8007988:	dc800215 	stw	r18,8(sp)
+ 800798c:	dfc00515 	stw	ra,20(sp)
+ 8007990:	dd000415 	stw	r20,16(sp)
+ 8007994:	dcc00315 	stw	r19,12(sp)
+ 8007998:	dc400115 	stw	r17,4(sp)
+ 800799c:	dc000015 	stw	r16,0(sp)
+ 80079a0:	2480b804 	addi	r18,r4,736
+ 80079a4:	90001e26 	beq	r18,zero,8007a20 <_fwalk+0x9c>
+ 80079a8:	2827883a 	mov	r19,r5
+ 80079ac:	0029883a 	mov	r20,zero
+ 80079b0:	94400117 	ldw	r17,4(r18)
+ 80079b4:	94000217 	ldw	r16,8(r18)
+ 80079b8:	8c7fffc4 	addi	r17,r17,-1
+ 80079bc:	88000d16 	blt	r17,zero,80079f4 <_fwalk+0x70>
+ 80079c0:	8080030b 	ldhu	r2,12(r16)
+ 80079c4:	8c7fffc4 	addi	r17,r17,-1
+ 80079c8:	108000b0 	cmpltui	r2,r2,2
+ 80079cc:	1000061e 	bne	r2,zero,80079e8 <_fwalk+0x64>
+ 80079d0:	8080038f 	ldh	r2,14(r16)
+ 80079d4:	8009883a 	mov	r4,r16
+ 80079d8:	10bfffe0 	cmpeqi	r2,r2,-1
+ 80079dc:	1000021e 	bne	r2,zero,80079e8 <_fwalk+0x64>
+ 80079e0:	983ee83a 	callr	r19
+ 80079e4:	a0a8b03a 	or	r20,r20,r2
+ 80079e8:	88bfffd8 	cmpnei	r2,r17,-1
+ 80079ec:	84001a04 	addi	r16,r16,104
+ 80079f0:	103ff31e 	bne	r2,zero,80079c0 <_fwalk+0x3c>
+ 80079f4:	94800017 	ldw	r18,0(r18)
+ 80079f8:	903fed1e 	bne	r18,zero,80079b0 <_fwalk+0x2c>
+ 80079fc:	a005883a 	mov	r2,r20
+ 8007a00:	dfc00517 	ldw	ra,20(sp)
+ 8007a04:	dd000417 	ldw	r20,16(sp)
+ 8007a08:	dcc00317 	ldw	r19,12(sp)
+ 8007a0c:	dc800217 	ldw	r18,8(sp)
+ 8007a10:	dc400117 	ldw	r17,4(sp)
+ 8007a14:	dc000017 	ldw	r16,0(sp)
+ 8007a18:	dec00604 	addi	sp,sp,24
+ 8007a1c:	f800283a 	ret
+ 8007a20:	0029883a 	mov	r20,zero
+ 8007a24:	003ff506 	br	80079fc <_fwalk+0x78>
+
+08007a28 <_fwalk_reent>:
+ 8007a28:	defff904 	addi	sp,sp,-28
+ 8007a2c:	dc800215 	stw	r18,8(sp)
+ 8007a30:	dfc00615 	stw	ra,24(sp)
+ 8007a34:	dd400515 	stw	r21,20(sp)
+ 8007a38:	dd000415 	stw	r20,16(sp)
+ 8007a3c:	dcc00315 	stw	r19,12(sp)
+ 8007a40:	dc400115 	stw	r17,4(sp)
+ 8007a44:	dc000015 	stw	r16,0(sp)
+ 8007a48:	2480b804 	addi	r18,r4,736
+ 8007a4c:	90002126 	beq	r18,zero,8007ad4 <_fwalk_reent+0xac>
+ 8007a50:	2829883a 	mov	r20,r5
+ 8007a54:	2027883a 	mov	r19,r4
+ 8007a58:	002b883a 	mov	r21,zero
+ 8007a5c:	94400117 	ldw	r17,4(r18)
+ 8007a60:	94000217 	ldw	r16,8(r18)
+ 8007a64:	8c7fffc4 	addi	r17,r17,-1
+ 8007a68:	88000e16 	blt	r17,zero,8007aa4 <_fwalk_reent+0x7c>
+ 8007a6c:	8080030b 	ldhu	r2,12(r16)
+ 8007a70:	8c7fffc4 	addi	r17,r17,-1
+ 8007a74:	108000b0 	cmpltui	r2,r2,2
+ 8007a78:	1000071e 	bne	r2,zero,8007a98 <_fwalk_reent+0x70>
+ 8007a7c:	8080038f 	ldh	r2,14(r16)
+ 8007a80:	800b883a 	mov	r5,r16
+ 8007a84:	9809883a 	mov	r4,r19
+ 8007a88:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8007a8c:	1000021e 	bne	r2,zero,8007a98 <_fwalk_reent+0x70>
+ 8007a90:	a03ee83a 	callr	r20
+ 8007a94:	a8aab03a 	or	r21,r21,r2
+ 8007a98:	88bfffd8 	cmpnei	r2,r17,-1
+ 8007a9c:	84001a04 	addi	r16,r16,104
+ 8007aa0:	103ff21e 	bne	r2,zero,8007a6c <_fwalk_reent+0x44>
+ 8007aa4:	94800017 	ldw	r18,0(r18)
+ 8007aa8:	903fec1e 	bne	r18,zero,8007a5c <_fwalk_reent+0x34>
+ 8007aac:	a805883a 	mov	r2,r21
+ 8007ab0:	dfc00617 	ldw	ra,24(sp)
+ 8007ab4:	dd400517 	ldw	r21,20(sp)
+ 8007ab8:	dd000417 	ldw	r20,16(sp)
+ 8007abc:	dcc00317 	ldw	r19,12(sp)
+ 8007ac0:	dc800217 	ldw	r18,8(sp)
+ 8007ac4:	dc400117 	ldw	r17,4(sp)
+ 8007ac8:	dc000017 	ldw	r16,0(sp)
+ 8007acc:	dec00704 	addi	sp,sp,28
+ 8007ad0:	f800283a 	ret
+ 8007ad4:	002b883a 	mov	r21,zero
+ 8007ad8:	003ff406 	br	8007aac <_fwalk_reent+0x84>
+
+08007adc <_getc_r>:
+ 8007adc:	defffd04 	addi	sp,sp,-12
+ 8007ae0:	dc000115 	stw	r16,4(sp)
+ 8007ae4:	dfc00215 	stw	ra,8(sp)
+ 8007ae8:	2021883a 	mov	r16,r4
+ 8007aec:	20000226 	beq	r4,zero,8007af8 <_getc_r+0x1c>
+ 8007af0:	20800e17 	ldw	r2,56(r4)
+ 8007af4:	10000c26 	beq	r2,zero,8007b28 <_getc_r+0x4c>
+ 8007af8:	28800117 	ldw	r2,4(r5)
+ 8007afc:	10bfffc4 	addi	r2,r2,-1
+ 8007b00:	28800115 	stw	r2,4(r5)
+ 8007b04:	10000f16 	blt	r2,zero,8007b44 <_getc_r+0x68>
+ 8007b08:	28800017 	ldw	r2,0(r5)
+ 8007b0c:	10c00044 	addi	r3,r2,1
+ 8007b10:	28c00015 	stw	r3,0(r5)
+ 8007b14:	10800003 	ldbu	r2,0(r2)
+ 8007b18:	dfc00217 	ldw	ra,8(sp)
+ 8007b1c:	dc000117 	ldw	r16,4(sp)
+ 8007b20:	dec00304 	addi	sp,sp,12
+ 8007b24:	f800283a 	ret
+ 8007b28:	d9400015 	stw	r5,0(sp)
+ 8007b2c:	80070600 	call	8007060 <__sinit>
+ 8007b30:	d9400017 	ldw	r5,0(sp)
+ 8007b34:	28800117 	ldw	r2,4(r5)
+ 8007b38:	10bfffc4 	addi	r2,r2,-1
+ 8007b3c:	28800115 	stw	r2,4(r5)
+ 8007b40:	103ff10e 	bge	r2,zero,8007b08 <_getc_r+0x2c>
+ 8007b44:	8009883a 	mov	r4,r16
+ 8007b48:	dfc00217 	ldw	ra,8(sp)
+ 8007b4c:	dc000117 	ldw	r16,4(sp)
+ 8007b50:	dec00304 	addi	sp,sp,12
+ 8007b54:	800a0e81 	jmpi	800a0e8 <__srget_r>
+
+08007b58 <getc>:
+ 8007b58:	defffd04 	addi	sp,sp,-12
+ 8007b5c:	00820174 	movhi	r2,2053
+ 8007b60:	dc400115 	stw	r17,4(sp)
+ 8007b64:	1472af17 	ldw	r17,-13636(r2)
+ 8007b68:	dc000015 	stw	r16,0(sp)
+ 8007b6c:	dfc00215 	stw	ra,8(sp)
+ 8007b70:	2021883a 	mov	r16,r4
+ 8007b74:	88000226 	beq	r17,zero,8007b80 <getc+0x28>
+ 8007b78:	88800e17 	ldw	r2,56(r17)
+ 8007b7c:	10000d26 	beq	r2,zero,8007bb4 <getc+0x5c>
+ 8007b80:	80800117 	ldw	r2,4(r16)
+ 8007b84:	10bfffc4 	addi	r2,r2,-1
+ 8007b88:	80800115 	stw	r2,4(r16)
+ 8007b8c:	10000f16 	blt	r2,zero,8007bcc <getc+0x74>
+ 8007b90:	80800017 	ldw	r2,0(r16)
+ 8007b94:	10c00044 	addi	r3,r2,1
+ 8007b98:	80c00015 	stw	r3,0(r16)
+ 8007b9c:	10800003 	ldbu	r2,0(r2)
+ 8007ba0:	dfc00217 	ldw	ra,8(sp)
+ 8007ba4:	dc400117 	ldw	r17,4(sp)
+ 8007ba8:	dc000017 	ldw	r16,0(sp)
+ 8007bac:	dec00304 	addi	sp,sp,12
+ 8007bb0:	f800283a 	ret
+ 8007bb4:	8809883a 	mov	r4,r17
+ 8007bb8:	80070600 	call	8007060 <__sinit>
+ 8007bbc:	80800117 	ldw	r2,4(r16)
+ 8007bc0:	10bfffc4 	addi	r2,r2,-1
+ 8007bc4:	80800115 	stw	r2,4(r16)
+ 8007bc8:	103ff10e 	bge	r2,zero,8007b90 <getc+0x38>
+ 8007bcc:	800b883a 	mov	r5,r16
+ 8007bd0:	8809883a 	mov	r4,r17
+ 8007bd4:	dfc00217 	ldw	ra,8(sp)
+ 8007bd8:	dc400117 	ldw	r17,4(sp)
+ 8007bdc:	dc000017 	ldw	r16,0(sp)
+ 8007be0:	dec00304 	addi	sp,sp,12
+ 8007be4:	800a0e81 	jmpi	800a0e8 <__srget_r>
+
+08007be8 <__localeconv_l>:
+ 8007be8:	20803c04 	addi	r2,r4,240
+ 8007bec:	f800283a 	ret
+
+08007bf0 <_localeconv_r>:
+ 8007bf0:	00820174 	movhi	r2,2053
+ 8007bf4:	10b0e704 	addi	r2,r2,-15460
+ 8007bf8:	f800283a 	ret
+
+08007bfc <localeconv>:
+ 8007bfc:	00820174 	movhi	r2,2053
+ 8007c00:	10b0e704 	addi	r2,r2,-15460
+ 8007c04:	f800283a 	ret
+
+08007c08 <__swhatbuf_r>:
+ 8007c08:	deffea04 	addi	sp,sp,-88
+ 8007c0c:	dc001215 	stw	r16,72(sp)
+ 8007c10:	2821883a 	mov	r16,r5
+ 8007c14:	2940038f 	ldh	r5,14(r5)
+ 8007c18:	dc801415 	stw	r18,80(sp)
+ 8007c1c:	dc401315 	stw	r17,76(sp)
+ 8007c20:	dfc01515 	stw	ra,84(sp)
+ 8007c24:	3023883a 	mov	r17,r6
+ 8007c28:	3825883a 	mov	r18,r7
+ 8007c2c:	28001016 	blt	r5,zero,8007c70 <__swhatbuf_r+0x68>
+ 8007c30:	d80d883a 	mov	r6,sp
+ 8007c34:	800bddc0 	call	800bddc <_fstat_r>
+ 8007c38:	10000d16 	blt	r2,zero,8007c70 <__swhatbuf_r+0x68>
+ 8007c3c:	d8c00117 	ldw	r3,4(sp)
+ 8007c40:	00820004 	movi	r2,2048
+ 8007c44:	18fc000c 	andi	r3,r3,61440
+ 8007c48:	18c80020 	cmpeqi	r3,r3,8192
+ 8007c4c:	90c00015 	stw	r3,0(r18)
+ 8007c50:	00c10004 	movi	r3,1024
+ 8007c54:	88c00015 	stw	r3,0(r17)
+ 8007c58:	dfc01517 	ldw	ra,84(sp)
+ 8007c5c:	dc801417 	ldw	r18,80(sp)
+ 8007c60:	dc401317 	ldw	r17,76(sp)
+ 8007c64:	dc001217 	ldw	r16,72(sp)
+ 8007c68:	dec01604 	addi	sp,sp,88
+ 8007c6c:	f800283a 	ret
+ 8007c70:	8080030b 	ldhu	r2,12(r16)
+ 8007c74:	90000015 	stw	zero,0(r18)
+ 8007c78:	1080200c 	andi	r2,r2,128
+ 8007c7c:	10000426 	beq	r2,zero,8007c90 <__swhatbuf_r+0x88>
+ 8007c80:	00801004 	movi	r2,64
+ 8007c84:	88800015 	stw	r2,0(r17)
+ 8007c88:	0005883a 	mov	r2,zero
+ 8007c8c:	003ff206 	br	8007c58 <__swhatbuf_r+0x50>
+ 8007c90:	00810004 	movi	r2,1024
+ 8007c94:	88800015 	stw	r2,0(r17)
+ 8007c98:	0005883a 	mov	r2,zero
+ 8007c9c:	003fee06 	br	8007c58 <__swhatbuf_r+0x50>
+
+08007ca0 <__smakebuf_r>:
+ 8007ca0:	28c0030b 	ldhu	r3,12(r5)
+ 8007ca4:	defffa04 	addi	sp,sp,-24
+ 8007ca8:	dc000215 	stw	r16,8(sp)
+ 8007cac:	dfc00515 	stw	ra,20(sp)
+ 8007cb0:	dc800415 	stw	r18,16(sp)
+ 8007cb4:	dc400315 	stw	r17,12(sp)
+ 8007cb8:	18c0008c 	andi	r3,r3,2
+ 8007cbc:	2821883a 	mov	r16,r5
+ 8007cc0:	18000b26 	beq	r3,zero,8007cf0 <__smakebuf_r+0x50>
+ 8007cc4:	28c010c4 	addi	r3,r5,67
+ 8007cc8:	28c00015 	stw	r3,0(r5)
+ 8007ccc:	28c00415 	stw	r3,16(r5)
+ 8007cd0:	00c00044 	movi	r3,1
+ 8007cd4:	28c00515 	stw	r3,20(r5)
+ 8007cd8:	dfc00517 	ldw	ra,20(sp)
+ 8007cdc:	dc800417 	ldw	r18,16(sp)
+ 8007ce0:	dc400317 	ldw	r17,12(sp)
+ 8007ce4:	dc000217 	ldw	r16,8(sp)
+ 8007ce8:	dec00604 	addi	sp,sp,24
+ 8007cec:	f800283a 	ret
+ 8007cf0:	d9c00104 	addi	r7,sp,4
+ 8007cf4:	d80d883a 	mov	r6,sp
+ 8007cf8:	2023883a 	mov	r17,r4
+ 8007cfc:	8007c080 	call	8007c08 <__swhatbuf_r>
+ 8007d00:	1025883a 	mov	r18,r2
+ 8007d04:	d8800117 	ldw	r2,4(sp)
+ 8007d08:	1000131e 	bne	r2,zero,8007d58 <__smakebuf_r+0xb8>
+ 8007d0c:	d9400017 	ldw	r5,0(sp)
+ 8007d10:	8809883a 	mov	r4,r17
+ 8007d14:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8007d18:	10001c26 	beq	r2,zero,8007d8c <__smakebuf_r+0xec>
+ 8007d1c:	01020034 	movhi	r4,2048
+ 8007d20:	211b5b04 	addi	r4,r4,28012
+ 8007d24:	80c0030b 	ldhu	r3,12(r16)
+ 8007d28:	89000f15 	stw	r4,60(r17)
+ 8007d2c:	80800015 	stw	r2,0(r16)
+ 8007d30:	80800415 	stw	r2,16(r16)
+ 8007d34:	d8800017 	ldw	r2,0(sp)
+ 8007d38:	d9400117 	ldw	r5,4(sp)
+ 8007d3c:	18c02014 	ori	r3,r3,128
+ 8007d40:	80c0030d 	sth	r3,12(r16)
+ 8007d44:	80800515 	stw	r2,20(r16)
+ 8007d48:	28001c1e 	bne	r5,zero,8007dbc <__smakebuf_r+0x11c>
+ 8007d4c:	90c6b03a 	or	r3,r18,r3
+ 8007d50:	80c0030d 	sth	r3,12(r16)
+ 8007d54:	003fe006 	br	8007cd8 <__smakebuf_r+0x38>
+ 8007d58:	8140038f 	ldh	r5,14(r16)
+ 8007d5c:	8809883a 	mov	r4,r17
+ 8007d60:	800be3c0 	call	800be3c <_isatty_r>
+ 8007d64:	103fe926 	beq	r2,zero,8007d0c <__smakebuf_r+0x6c>
+ 8007d68:	8080030b 	ldhu	r2,12(r16)
+ 8007d6c:	80c010c4 	addi	r3,r16,67
+ 8007d70:	80c00015 	stw	r3,0(r16)
+ 8007d74:	10800054 	ori	r2,r2,1
+ 8007d78:	8080030d 	sth	r2,12(r16)
+ 8007d7c:	00800044 	movi	r2,1
+ 8007d80:	80c00415 	stw	r3,16(r16)
+ 8007d84:	80800515 	stw	r2,20(r16)
+ 8007d88:	003fe006 	br	8007d0c <__smakebuf_r+0x6c>
+ 8007d8c:	8080030b 	ldhu	r2,12(r16)
+ 8007d90:	10c0800c 	andi	r3,r2,512
+ 8007d94:	183fd01e 	bne	r3,zero,8007cd8 <__smakebuf_r+0x38>
+ 8007d98:	10bfff0c 	andi	r2,r2,65532
+ 8007d9c:	10800094 	ori	r2,r2,2
+ 8007da0:	80c010c4 	addi	r3,r16,67
+ 8007da4:	8080030d 	sth	r2,12(r16)
+ 8007da8:	00800044 	movi	r2,1
+ 8007dac:	80c00015 	stw	r3,0(r16)
+ 8007db0:	80c00415 	stw	r3,16(r16)
+ 8007db4:	80800515 	stw	r2,20(r16)
+ 8007db8:	003fc706 	br	8007cd8 <__smakebuf_r+0x38>
+ 8007dbc:	8140038f 	ldh	r5,14(r16)
+ 8007dc0:	8809883a 	mov	r4,r17
+ 8007dc4:	800be3c0 	call	800be3c <_isatty_r>
+ 8007dc8:	80c0030b 	ldhu	r3,12(r16)
+ 8007dcc:	103fdf26 	beq	r2,zero,8007d4c <__smakebuf_r+0xac>
+ 8007dd0:	18ffff0c 	andi	r3,r3,65532
+ 8007dd4:	18c00054 	ori	r3,r3,1
+ 8007dd8:	003fdc06 	br	8007d4c <__smakebuf_r+0xac>
+
+08007ddc <_malloc_r>:
+ 8007ddc:	defff604 	addi	sp,sp,-40
+ 8007de0:	dc400115 	stw	r17,4(sp)
+ 8007de4:	2c4002c4 	addi	r17,r5,11
+ 8007de8:	dc800215 	stw	r18,8(sp)
+ 8007dec:	dfc00915 	stw	ra,36(sp)
+ 8007df0:	df000815 	stw	fp,32(sp)
+ 8007df4:	ddc00715 	stw	r23,28(sp)
+ 8007df8:	dd800615 	stw	r22,24(sp)
+ 8007dfc:	dd400515 	stw	r21,20(sp)
+ 8007e00:	dd000415 	stw	r20,16(sp)
+ 8007e04:	dcc00315 	stw	r19,12(sp)
+ 8007e08:	dc000015 	stw	r16,0(sp)
+ 8007e0c:	888005e8 	cmpgeui	r2,r17,23
+ 8007e10:	2025883a 	mov	r18,r4
+ 8007e14:	10001b1e 	bne	r2,zero,8007e84 <_malloc_r+0xa8>
+ 8007e18:	29400468 	cmpgeui	r5,r5,17
+ 8007e1c:	2800951e 	bne	r5,zero,8008074 <_malloc_r+0x298>
+ 8007e20:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 8007e24:	04400404 	movi	r17,16
+ 8007e28:	00800604 	movi	r2,24
+ 8007e2c:	01800084 	movi	r6,2
+ 8007e30:	04c20174 	movhi	r19,2053
+ 8007e34:	9cefa904 	addi	r19,r19,-16732
+ 8007e38:	9885883a 	add	r2,r19,r2
+ 8007e3c:	14000117 	ldw	r16,4(r2)
+ 8007e40:	10fffe04 	addi	r3,r2,-8
+ 8007e44:	80c09e26 	beq	r16,r3,80080c0 <_malloc_r+0x2e4>
+ 8007e48:	80800117 	ldw	r2,4(r16)
+ 8007e4c:	81000317 	ldw	r4,12(r16)
+ 8007e50:	00ffff04 	movi	r3,-4
+ 8007e54:	10c4703a 	and	r2,r2,r3
+ 8007e58:	81400217 	ldw	r5,8(r16)
+ 8007e5c:	8085883a 	add	r2,r16,r2
+ 8007e60:	10c00117 	ldw	r3,4(r2)
+ 8007e64:	29000315 	stw	r4,12(r5)
+ 8007e68:	21400215 	stw	r5,8(r4)
+ 8007e6c:	18c00054 	ori	r3,r3,1
+ 8007e70:	10c00115 	stw	r3,4(r2)
+ 8007e74:	9009883a 	mov	r4,r18
+ 8007e78:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8007e7c:	80800204 	addi	r2,r16,8
+ 8007e80:	00007f06 	br	8008080 <_malloc_r+0x2a4>
+ 8007e84:	00bffe04 	movi	r2,-8
+ 8007e88:	88a2703a 	and	r17,r17,r2
+ 8007e8c:	88007916 	blt	r17,zero,8008074 <_malloc_r+0x298>
+ 8007e90:	89407836 	bltu	r17,r5,8008074 <_malloc_r+0x298>
+ 8007e94:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 8007e98:	88807e28 	cmpgeui	r2,r17,504
+ 8007e9c:	10013326 	beq	r2,zero,800836c <_malloc_r+0x590>
+ 8007ea0:	8804d27a 	srli	r2,r17,9
+ 8007ea4:	10008226 	beq	r2,zero,80080b0 <_malloc_r+0x2d4>
+ 8007ea8:	10c00168 	cmpgeui	r3,r2,5
+ 8007eac:	1801151e 	bne	r3,zero,8008304 <_malloc_r+0x528>
+ 8007eb0:	8804d1ba 	srli	r2,r17,6
+ 8007eb4:	11800e44 	addi	r6,r2,57
+ 8007eb8:	300a90fa 	slli	r5,r6,3
+ 8007ebc:	12000e04 	addi	r8,r2,56
+ 8007ec0:	04c20174 	movhi	r19,2053
+ 8007ec4:	9cefa904 	addi	r19,r19,-16732
+ 8007ec8:	994b883a 	add	r5,r19,r5
+ 8007ecc:	2c000117 	ldw	r16,4(r5)
+ 8007ed0:	297ffe04 	addi	r5,r5,-8
+ 8007ed4:	2c001126 	beq	r5,r16,8007f1c <_malloc_r+0x140>
+ 8007ed8:	80800117 	ldw	r2,4(r16)
+ 8007edc:	00ffff04 	movi	r3,-4
+ 8007ee0:	10c4703a 	and	r2,r2,r3
+ 8007ee4:	1447c83a 	sub	r3,r2,r17
+ 8007ee8:	19000408 	cmpgei	r4,r3,16
+ 8007eec:	2000e81e 	bne	r4,zero,8008290 <_malloc_r+0x4b4>
+ 8007ef0:	1800e90e 	bge	r3,zero,8008298 <_malloc_r+0x4bc>
+ 8007ef4:	01ffff04 	movi	r7,-4
+ 8007ef8:	00000606 	br	8007f14 <_malloc_r+0x138>
+ 8007efc:	80800117 	ldw	r2,4(r16)
+ 8007f00:	11c4703a 	and	r2,r2,r7
+ 8007f04:	1447c83a 	sub	r3,r2,r17
+ 8007f08:	19000408 	cmpgei	r4,r3,16
+ 8007f0c:	2000e01e 	bne	r4,zero,8008290 <_malloc_r+0x4b4>
+ 8007f10:	1800e10e 	bge	r3,zero,8008298 <_malloc_r+0x4bc>
+ 8007f14:	84000317 	ldw	r16,12(r16)
+ 8007f18:	2c3ff81e 	bne	r5,r16,8007efc <_malloc_r+0x120>
+ 8007f1c:	9c000417 	ldw	r16,16(r19)
+ 8007f20:	02020174 	movhi	r8,2053
+ 8007f24:	422fab04 	addi	r8,r8,-16724
+ 8007f28:	82006c26 	beq	r16,r8,80080dc <_malloc_r+0x300>
+ 8007f2c:	80c00117 	ldw	r3,4(r16)
+ 8007f30:	00bfff04 	movi	r2,-4
+ 8007f34:	1884703a 	and	r2,r3,r2
+ 8007f38:	1447c83a 	sub	r3,r2,r17
+ 8007f3c:	19000410 	cmplti	r4,r3,16
+ 8007f40:	20011526 	beq	r4,zero,8008398 <_malloc_r+0x5bc>
+ 8007f44:	9a000515 	stw	r8,20(r19)
+ 8007f48:	9a000415 	stw	r8,16(r19)
+ 8007f4c:	18010a0e 	bge	r3,zero,8008378 <_malloc_r+0x59c>
+ 8007f50:	10c08028 	cmpgeui	r3,r2,512
+ 8007f54:	1800d21e 	bne	r3,zero,80082a0 <_malloc_r+0x4c4>
+ 8007f58:	1004d0fa 	srli	r2,r2,3
+ 8007f5c:	99400117 	ldw	r5,4(r19)
+ 8007f60:	10c00044 	addi	r3,r2,1
+ 8007f64:	1009d0ba 	srai	r4,r2,2
+ 8007f68:	180690fa 	slli	r3,r3,3
+ 8007f6c:	00800044 	movi	r2,1
+ 8007f70:	1104983a 	sll	r2,r2,r4
+ 8007f74:	98c7883a 	add	r3,r19,r3
+ 8007f78:	19000017 	ldw	r4,0(r3)
+ 8007f7c:	1144b03a 	or	r2,r2,r5
+ 8007f80:	197ffe04 	addi	r5,r3,-8
+ 8007f84:	81400315 	stw	r5,12(r16)
+ 8007f88:	81000215 	stw	r4,8(r16)
+ 8007f8c:	98800115 	stw	r2,4(r19)
+ 8007f90:	1c000015 	stw	r16,0(r3)
+ 8007f94:	24000315 	stw	r16,12(r4)
+ 8007f98:	3007d0ba 	srai	r3,r6,2
+ 8007f9c:	01000044 	movi	r4,1
+ 8007fa0:	20c8983a 	sll	r4,r4,r3
+ 8007fa4:	11005236 	bltu	r2,r4,80080f0 <_malloc_r+0x314>
+ 8007fa8:	2086703a 	and	r3,r4,r2
+ 8007fac:	18000a1e 	bne	r3,zero,8007fd8 <_malloc_r+0x1fc>
+ 8007fb0:	00ffff04 	movi	r3,-4
+ 8007fb4:	2109883a 	add	r4,r4,r4
+ 8007fb8:	30cc703a 	and	r6,r6,r3
+ 8007fbc:	2086703a 	and	r3,r4,r2
+ 8007fc0:	31800104 	addi	r6,r6,4
+ 8007fc4:	1800041e 	bne	r3,zero,8007fd8 <_malloc_r+0x1fc>
+ 8007fc8:	2109883a 	add	r4,r4,r4
+ 8007fcc:	2086703a 	and	r3,r4,r2
+ 8007fd0:	31800104 	addi	r6,r6,4
+ 8007fd4:	183ffc26 	beq	r3,zero,8007fc8 <_malloc_r+0x1ec>
+ 8007fd8:	027fff04 	movi	r9,-4
+ 8007fdc:	301490fa 	slli	r10,r6,3
+ 8007fe0:	3017883a 	mov	r11,r6
+ 8007fe4:	9a95883a 	add	r10,r19,r10
+ 8007fe8:	500f883a 	mov	r7,r10
+ 8007fec:	3c000317 	ldw	r16,12(r7)
+ 8007ff0:	3c00cd26 	beq	r7,r16,8008328 <_malloc_r+0x54c>
+ 8007ff4:	80800117 	ldw	r2,4(r16)
+ 8007ff8:	1244703a 	and	r2,r2,r9
+ 8007ffc:	1447c83a 	sub	r3,r2,r17
+ 8008000:	19400408 	cmpgei	r5,r3,16
+ 8008004:	2800081e 	bne	r5,zero,8008028 <_malloc_r+0x24c>
+ 8008008:	1800cc0e 	bge	r3,zero,800833c <_malloc_r+0x560>
+ 800800c:	84000317 	ldw	r16,12(r16)
+ 8008010:	3c00c526 	beq	r7,r16,8008328 <_malloc_r+0x54c>
+ 8008014:	80800117 	ldw	r2,4(r16)
+ 8008018:	1244703a 	and	r2,r2,r9
+ 800801c:	1447c83a 	sub	r3,r2,r17
+ 8008020:	19400410 	cmplti	r5,r3,16
+ 8008024:	283ff81e 	bne	r5,zero,8008008 <_malloc_r+0x22c>
+ 8008028:	81000317 	ldw	r4,12(r16)
+ 800802c:	81400217 	ldw	r5,8(r16)
+ 8008030:	89800054 	ori	r6,r17,1
+ 8008034:	81800115 	stw	r6,4(r16)
+ 8008038:	29000315 	stw	r4,12(r5)
+ 800803c:	21400215 	stw	r5,8(r4)
+ 8008040:	8463883a 	add	r17,r16,r17
+ 8008044:	9c400515 	stw	r17,20(r19)
+ 8008048:	9c400415 	stw	r17,16(r19)
+ 800804c:	19000054 	ori	r4,r3,1
+ 8008050:	89000115 	stw	r4,4(r17)
+ 8008054:	8085883a 	add	r2,r16,r2
+ 8008058:	8a000315 	stw	r8,12(r17)
+ 800805c:	8a000215 	stw	r8,8(r17)
+ 8008060:	10c00015 	stw	r3,0(r2)
+ 8008064:	9009883a 	mov	r4,r18
+ 8008068:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 800806c:	80800204 	addi	r2,r16,8
+ 8008070:	00000306 	br	8008080 <_malloc_r+0x2a4>
+ 8008074:	00800304 	movi	r2,12
+ 8008078:	90800015 	stw	r2,0(r18)
+ 800807c:	0005883a 	mov	r2,zero
+ 8008080:	dfc00917 	ldw	ra,36(sp)
+ 8008084:	df000817 	ldw	fp,32(sp)
+ 8008088:	ddc00717 	ldw	r23,28(sp)
+ 800808c:	dd800617 	ldw	r22,24(sp)
+ 8008090:	dd400517 	ldw	r21,20(sp)
+ 8008094:	dd000417 	ldw	r20,16(sp)
+ 8008098:	dcc00317 	ldw	r19,12(sp)
+ 800809c:	dc800217 	ldw	r18,8(sp)
+ 80080a0:	dc400117 	ldw	r17,4(sp)
+ 80080a4:	dc000017 	ldw	r16,0(sp)
+ 80080a8:	dec00a04 	addi	sp,sp,40
+ 80080ac:	f800283a 	ret
+ 80080b0:	01408004 	movi	r5,512
+ 80080b4:	01801004 	movi	r6,64
+ 80080b8:	02000fc4 	movi	r8,63
+ 80080bc:	003f8006 	br	8007ec0 <_malloc_r+0xe4>
+ 80080c0:	14000317 	ldw	r16,12(r2)
+ 80080c4:	31800084 	addi	r6,r6,2
+ 80080c8:	143f5f1e 	bne	r2,r16,8007e48 <_malloc_r+0x6c>
+ 80080cc:	9c000417 	ldw	r16,16(r19)
+ 80080d0:	02020174 	movhi	r8,2053
+ 80080d4:	422fab04 	addi	r8,r8,-16724
+ 80080d8:	823f941e 	bne	r16,r8,8007f2c <_malloc_r+0x150>
+ 80080dc:	3007d0ba 	srai	r3,r6,2
+ 80080e0:	01000044 	movi	r4,1
+ 80080e4:	98800117 	ldw	r2,4(r19)
+ 80080e8:	20c8983a 	sll	r4,r4,r3
+ 80080ec:	113fae2e 	bgeu	r2,r4,8007fa8 <_malloc_r+0x1cc>
+ 80080f0:	9c000217 	ldw	r16,8(r19)
+ 80080f4:	00bfff04 	movi	r2,-4
+ 80080f8:	85000117 	ldw	r20,4(r16)
+ 80080fc:	a0ac703a 	and	r22,r20,r2
+ 8008100:	b4400336 	bltu	r22,r17,8008110 <_malloc_r+0x334>
+ 8008104:	b445c83a 	sub	r2,r22,r17
+ 8008108:	10c00408 	cmpgei	r3,r2,16
+ 800810c:	1800561e 	bne	r3,zero,8008268 <_malloc_r+0x48c>
+ 8008110:	00820174 	movhi	r2,2053
+ 8008114:	10b2b017 	ldw	r2,-13632(r2)
+ 8008118:	00c20174 	movhi	r3,2053
+ 800811c:	1d32ef17 	ldw	r20,-13380(r3)
+ 8008120:	10bfffd8 	cmpnei	r2,r2,-1
+ 8008124:	85ab883a 	add	r21,r16,r22
+ 8008128:	8d29883a 	add	r20,r17,r20
+ 800812c:	1000c826 	beq	r2,zero,8008450 <_malloc_r+0x674>
+ 8008130:	a50403c4 	addi	r20,r20,4111
+ 8008134:	00bc0004 	movi	r2,-4096
+ 8008138:	a0a8703a 	and	r20,r20,r2
+ 800813c:	a00b883a 	mov	r5,r20
+ 8008140:	9009883a 	mov	r4,r18
+ 8008144:	800a16c0 	call	800a16c <_sbrk_r>
+ 8008148:	102f883a 	mov	r23,r2
+ 800814c:	10bfffd8 	cmpnei	r2,r2,-1
+ 8008150:	10009a26 	beq	r2,zero,80083bc <_malloc_r+0x5e0>
+ 8008154:	bd409836 	bltu	r23,r21,80083b8 <_malloc_r+0x5dc>
+ 8008158:	00820174 	movhi	r2,2053
+ 800815c:	10b36417 	ldw	r2,-12912(r2)
+ 8008160:	00c20174 	movhi	r3,2053
+ 8008164:	a085883a 	add	r2,r20,r2
+ 8008168:	18b36415 	stw	r2,-12912(r3)
+ 800816c:	1007883a 	mov	r3,r2
+ 8008170:	adc0dd26 	beq	r21,r23,80084e8 <_malloc_r+0x70c>
+ 8008174:	00820174 	movhi	r2,2053
+ 8008178:	10b2b017 	ldw	r2,-13632(r2)
+ 800817c:	10bfffd8 	cmpnei	r2,r2,-1
+ 8008180:	1000e026 	beq	r2,zero,8008504 <_malloc_r+0x728>
+ 8008184:	bd6bc83a 	sub	r21,r23,r21
+ 8008188:	a8c7883a 	add	r3,r21,r3
+ 800818c:	00820174 	movhi	r2,2053
+ 8008190:	10f36415 	stw	r3,-12912(r2)
+ 8008194:	bf0001cc 	andi	fp,r23,7
+ 8008198:	e000b626 	beq	fp,zero,8008474 <_malloc_r+0x698>
+ 800819c:	bf2fc83a 	sub	r23,r23,fp
+ 80081a0:	bdc00204 	addi	r23,r23,8
+ 80081a4:	00840204 	movi	r2,4104
+ 80081a8:	1705c83a 	sub	r2,r2,fp
+ 80081ac:	bd29883a 	add	r20,r23,r20
+ 80081b0:	1505c83a 	sub	r2,r2,r20
+ 80081b4:	1543ffcc 	andi	r21,r2,4095
+ 80081b8:	a80b883a 	mov	r5,r21
+ 80081bc:	9009883a 	mov	r4,r18
+ 80081c0:	800a16c0 	call	800a16c <_sbrk_r>
+ 80081c4:	10ffffe0 	cmpeqi	r3,r2,-1
+ 80081c8:	1800e41e 	bne	r3,zero,800855c <_malloc_r+0x780>
+ 80081cc:	15c5c83a 	sub	r2,r2,r23
+ 80081d0:	1569883a 	add	r20,r2,r21
+ 80081d4:	00820174 	movhi	r2,2053
+ 80081d8:	10b36417 	ldw	r2,-12912(r2)
+ 80081dc:	9dc00215 	stw	r23,8(r19)
+ 80081e0:	a5000054 	ori	r20,r20,1
+ 80081e4:	a885883a 	add	r2,r21,r2
+ 80081e8:	00c20174 	movhi	r3,2053
+ 80081ec:	18b36415 	stw	r2,-12912(r3)
+ 80081f0:	bd000115 	stw	r20,4(r23)
+ 80081f4:	84c0c626 	beq	r16,r19,8008510 <_malloc_r+0x734>
+ 80081f8:	b0c00428 	cmpgeui	r3,r22,16
+ 80081fc:	1800c626 	beq	r3,zero,8008518 <_malloc_r+0x73c>
+ 8008200:	81000117 	ldw	r4,4(r16)
+ 8008204:	017ffe04 	movi	r5,-8
+ 8008208:	b0fffd04 	addi	r3,r22,-12
+ 800820c:	1946703a 	and	r3,r3,r5
+ 8008210:	2100004c 	andi	r4,r4,1
+ 8008214:	20c8b03a 	or	r4,r4,r3
+ 8008218:	81000115 	stw	r4,4(r16)
+ 800821c:	01400144 	movi	r5,5
+ 8008220:	80c9883a 	add	r4,r16,r3
+ 8008224:	21400115 	stw	r5,4(r4)
+ 8008228:	21400215 	stw	r5,8(r4)
+ 800822c:	18c00428 	cmpgeui	r3,r3,16
+ 8008230:	1800cf1e 	bne	r3,zero,8008570 <_malloc_r+0x794>
+ 8008234:	bd000117 	ldw	r20,4(r23)
+ 8008238:	b821883a 	mov	r16,r23
+ 800823c:	00c20174 	movhi	r3,2053
+ 8008240:	18f2ee17 	ldw	r3,-13384(r3)
+ 8008244:	1880022e 	bgeu	r3,r2,8008250 <_malloc_r+0x474>
+ 8008248:	00c20174 	movhi	r3,2053
+ 800824c:	18b2ee15 	stw	r2,-13384(r3)
+ 8008250:	00c20174 	movhi	r3,2053
+ 8008254:	18f2ed17 	ldw	r3,-13388(r3)
+ 8008258:	18805a2e 	bgeu	r3,r2,80083c4 <_malloc_r+0x5e8>
+ 800825c:	00c20174 	movhi	r3,2053
+ 8008260:	18b2ed15 	stw	r2,-13388(r3)
+ 8008264:	00005706 	br	80083c4 <_malloc_r+0x5e8>
+ 8008268:	88c00054 	ori	r3,r17,1
+ 800826c:	80c00115 	stw	r3,4(r16)
+ 8008270:	8463883a 	add	r17,r16,r17
+ 8008274:	10800054 	ori	r2,r2,1
+ 8008278:	9c400215 	stw	r17,8(r19)
+ 800827c:	88800115 	stw	r2,4(r17)
+ 8008280:	9009883a 	mov	r4,r18
+ 8008284:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8008288:	80800204 	addi	r2,r16,8
+ 800828c:	003f7c06 	br	8008080 <_malloc_r+0x2a4>
+ 8008290:	400d883a 	mov	r6,r8
+ 8008294:	003f2106 	br	8007f1c <_malloc_r+0x140>
+ 8008298:	81000317 	ldw	r4,12(r16)
+ 800829c:	003eee06 	br	8007e58 <_malloc_r+0x7c>
+ 80082a0:	1006d27a 	srli	r3,r2,9
+ 80082a4:	19000168 	cmpgeui	r4,r3,5
+ 80082a8:	20003e26 	beq	r4,zero,80083a4 <_malloc_r+0x5c8>
+ 80082ac:	19000568 	cmpgeui	r4,r3,21
+ 80082b0:	20007a1e 	bne	r4,zero,800849c <_malloc_r+0x6c0>
+ 80082b4:	19401704 	addi	r5,r3,92
+ 80082b8:	280a90fa 	slli	r5,r5,3
+ 80082bc:	190016c4 	addi	r4,r3,91
+ 80082c0:	994b883a 	add	r5,r19,r5
+ 80082c4:	28c00017 	ldw	r3,0(r5)
+ 80082c8:	297ffe04 	addi	r5,r5,-8
+ 80082cc:	28c06226 	beq	r5,r3,8008458 <_malloc_r+0x67c>
+ 80082d0:	01ffff04 	movi	r7,-4
+ 80082d4:	19000117 	ldw	r4,4(r3)
+ 80082d8:	21c8703a 	and	r4,r4,r7
+ 80082dc:	1100022e 	bgeu	r2,r4,80082e8 <_malloc_r+0x50c>
+ 80082e0:	18c00217 	ldw	r3,8(r3)
+ 80082e4:	28fffb1e 	bne	r5,r3,80082d4 <_malloc_r+0x4f8>
+ 80082e8:	19400317 	ldw	r5,12(r3)
+ 80082ec:	98800117 	ldw	r2,4(r19)
+ 80082f0:	81400315 	stw	r5,12(r16)
+ 80082f4:	80c00215 	stw	r3,8(r16)
+ 80082f8:	2c000215 	stw	r16,8(r5)
+ 80082fc:	1c000315 	stw	r16,12(r3)
+ 8008300:	003f2506 	br	8007f98 <_malloc_r+0x1bc>
+ 8008304:	10c00568 	cmpgeui	r3,r2,21
+ 8008308:	18003826 	beq	r3,zero,80083ec <_malloc_r+0x610>
+ 800830c:	10c01568 	cmpgeui	r3,r2,85
+ 8008310:	1800691e 	bne	r3,zero,80084b8 <_malloc_r+0x6dc>
+ 8008314:	8804d33a 	srli	r2,r17,12
+ 8008318:	11801bc4 	addi	r6,r2,111
+ 800831c:	12001b84 	addi	r8,r2,110
+ 8008320:	300a90fa 	slli	r5,r6,3
+ 8008324:	003ee606 	br	8007ec0 <_malloc_r+0xe4>
+ 8008328:	5ac00044 	addi	r11,r11,1
+ 800832c:	588000cc 	andi	r2,r11,3
+ 8008330:	39c00204 	addi	r7,r7,8
+ 8008334:	103f2d1e 	bne	r2,zero,8007fec <_malloc_r+0x210>
+ 8008338:	00003306 	br	8008408 <_malloc_r+0x62c>
+ 800833c:	8085883a 	add	r2,r16,r2
+ 8008340:	10c00117 	ldw	r3,4(r2)
+ 8008344:	81000317 	ldw	r4,12(r16)
+ 8008348:	81400217 	ldw	r5,8(r16)
+ 800834c:	18c00054 	ori	r3,r3,1
+ 8008350:	10c00115 	stw	r3,4(r2)
+ 8008354:	29000315 	stw	r4,12(r5)
+ 8008358:	21400215 	stw	r5,8(r4)
+ 800835c:	9009883a 	mov	r4,r18
+ 8008360:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8008364:	80800204 	addi	r2,r16,8
+ 8008368:	003f4506 	br	8008080 <_malloc_r+0x2a4>
+ 800836c:	880cd0fa 	srli	r6,r17,3
+ 8008370:	88800204 	addi	r2,r17,8
+ 8008374:	003eae06 	br	8007e30 <_malloc_r+0x54>
+ 8008378:	8085883a 	add	r2,r16,r2
+ 800837c:	10c00117 	ldw	r3,4(r2)
+ 8008380:	9009883a 	mov	r4,r18
+ 8008384:	18c00054 	ori	r3,r3,1
+ 8008388:	10c00115 	stw	r3,4(r2)
+ 800838c:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8008390:	80800204 	addi	r2,r16,8
+ 8008394:	003f3a06 	br	8008080 <_malloc_r+0x2a4>
+ 8008398:	89000054 	ori	r4,r17,1
+ 800839c:	81000115 	stw	r4,4(r16)
+ 80083a0:	003f2706 	br	8008040 <_malloc_r+0x264>
+ 80083a4:	1006d1ba 	srli	r3,r2,6
+ 80083a8:	19400e44 	addi	r5,r3,57
+ 80083ac:	19000e04 	addi	r4,r3,56
+ 80083b0:	280a90fa 	slli	r5,r5,3
+ 80083b4:	003fc206 	br	80082c0 <_malloc_r+0x4e4>
+ 80083b8:	84c04626 	beq	r16,r19,80084d4 <_malloc_r+0x6f8>
+ 80083bc:	9c000217 	ldw	r16,8(r19)
+ 80083c0:	85000117 	ldw	r20,4(r16)
+ 80083c4:	00bfff04 	movi	r2,-4
+ 80083c8:	a0a8703a 	and	r20,r20,r2
+ 80083cc:	a445c83a 	sub	r2,r20,r17
+ 80083d0:	a4400236 	bltu	r20,r17,80083dc <_malloc_r+0x600>
+ 80083d4:	10c00408 	cmpgei	r3,r2,16
+ 80083d8:	183fa31e 	bne	r3,zero,8008268 <_malloc_r+0x48c>
+ 80083dc:	9009883a 	mov	r4,r18
+ 80083e0:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 80083e4:	0005883a 	mov	r2,zero
+ 80083e8:	003f2506 	br	8008080 <_malloc_r+0x2a4>
+ 80083ec:	11801704 	addi	r6,r2,92
+ 80083f0:	120016c4 	addi	r8,r2,91
+ 80083f4:	300a90fa 	slli	r5,r6,3
+ 80083f8:	003eb106 	br	8007ec0 <_malloc_r+0xe4>
+ 80083fc:	50800217 	ldw	r2,8(r10)
+ 8008400:	31bfffc4 	addi	r6,r6,-1
+ 8008404:	1280701e 	bne	r2,r10,80085c8 <_malloc_r+0x7ec>
+ 8008408:	308000cc 	andi	r2,r6,3
+ 800840c:	52bffe04 	addi	r10,r10,-8
+ 8008410:	103ffa1e 	bne	r2,zero,80083fc <_malloc_r+0x620>
+ 8008414:	98c00117 	ldw	r3,4(r19)
+ 8008418:	0104303a 	nor	r2,zero,r4
+ 800841c:	10c4703a 	and	r2,r2,r3
+ 8008420:	98800115 	stw	r2,4(r19)
+ 8008424:	2109883a 	add	r4,r4,r4
+ 8008428:	113f3136 	bltu	r2,r4,80080f0 <_malloc_r+0x314>
+ 800842c:	203f3026 	beq	r4,zero,80080f0 <_malloc_r+0x314>
+ 8008430:	2086703a 	and	r3,r4,r2
+ 8008434:	1800041e 	bne	r3,zero,8008448 <_malloc_r+0x66c>
+ 8008438:	2109883a 	add	r4,r4,r4
+ 800843c:	2086703a 	and	r3,r4,r2
+ 8008440:	5ac00104 	addi	r11,r11,4
+ 8008444:	183ffc26 	beq	r3,zero,8008438 <_malloc_r+0x65c>
+ 8008448:	580d883a 	mov	r6,r11
+ 800844c:	003ee306 	br	8007fdc <_malloc_r+0x200>
+ 8008450:	a5000404 	addi	r20,r20,16
+ 8008454:	003f3906 	br	800813c <_malloc_r+0x360>
+ 8008458:	2009d0ba 	srai	r4,r4,2
+ 800845c:	00800044 	movi	r2,1
+ 8008460:	99c00117 	ldw	r7,4(r19)
+ 8008464:	1104983a 	sll	r2,r2,r4
+ 8008468:	11c4b03a 	or	r2,r2,r7
+ 800846c:	98800115 	stw	r2,4(r19)
+ 8008470:	003f9f06 	br	80082f0 <_malloc_r+0x514>
+ 8008474:	bd05883a 	add	r2,r23,r20
+ 8008478:	0085c83a 	sub	r2,zero,r2
+ 800847c:	1543ffcc 	andi	r21,r2,4095
+ 8008480:	a80b883a 	mov	r5,r21
+ 8008484:	9009883a 	mov	r4,r18
+ 8008488:	800a16c0 	call	800a16c <_sbrk_r>
+ 800848c:	10ffffe0 	cmpeqi	r3,r2,-1
+ 8008490:	183f4e26 	beq	r3,zero,80081cc <_malloc_r+0x3f0>
+ 8008494:	002b883a 	mov	r21,zero
+ 8008498:	003f4e06 	br	80081d4 <_malloc_r+0x3f8>
+ 800849c:	19001568 	cmpgeui	r4,r3,85
+ 80084a0:	2000201e 	bne	r4,zero,8008524 <_malloc_r+0x748>
+ 80084a4:	1006d33a 	srli	r3,r2,12
+ 80084a8:	19401bc4 	addi	r5,r3,111
+ 80084ac:	19001b84 	addi	r4,r3,110
+ 80084b0:	280a90fa 	slli	r5,r5,3
+ 80084b4:	003f8206 	br	80082c0 <_malloc_r+0x4e4>
+ 80084b8:	10c05568 	cmpgeui	r3,r2,341
+ 80084bc:	1800201e 	bne	r3,zero,8008540 <_malloc_r+0x764>
+ 80084c0:	8804d3fa 	srli	r2,r17,15
+ 80084c4:	11801e04 	addi	r6,r2,120
+ 80084c8:	12001dc4 	addi	r8,r2,119
+ 80084cc:	300a90fa 	slli	r5,r6,3
+ 80084d0:	003e7b06 	br	8007ec0 <_malloc_r+0xe4>
+ 80084d4:	00820174 	movhi	r2,2053
+ 80084d8:	10f36417 	ldw	r3,-12912(r2)
+ 80084dc:	a0c7883a 	add	r3,r20,r3
+ 80084e0:	10f36415 	stw	r3,-12912(r2)
+ 80084e4:	003f2306 	br	8008174 <_malloc_r+0x398>
+ 80084e8:	a903ffcc 	andi	r4,r21,4095
+ 80084ec:	203f211e 	bne	r4,zero,8008174 <_malloc_r+0x398>
+ 80084f0:	9c000217 	ldw	r16,8(r19)
+ 80084f4:	b529883a 	add	r20,r22,r20
+ 80084f8:	a5000054 	ori	r20,r20,1
+ 80084fc:	85000115 	stw	r20,4(r16)
+ 8008500:	003f4e06 	br	800823c <_malloc_r+0x460>
+ 8008504:	00820174 	movhi	r2,2053
+ 8008508:	15f2b015 	stw	r23,-13632(r2)
+ 800850c:	003f2106 	br	8008194 <_malloc_r+0x3b8>
+ 8008510:	b821883a 	mov	r16,r23
+ 8008514:	003f4906 	br	800823c <_malloc_r+0x460>
+ 8008518:	00800044 	movi	r2,1
+ 800851c:	b8800115 	stw	r2,4(r23)
+ 8008520:	003fae06 	br	80083dc <_malloc_r+0x600>
+ 8008524:	19005568 	cmpgeui	r4,r3,341
+ 8008528:	2000191e 	bne	r4,zero,8008590 <_malloc_r+0x7b4>
+ 800852c:	1006d3fa 	srli	r3,r2,15
+ 8008530:	19401e04 	addi	r5,r3,120
+ 8008534:	19001dc4 	addi	r4,r3,119
+ 8008538:	280a90fa 	slli	r5,r5,3
+ 800853c:	003f6006 	br	80082c0 <_malloc_r+0x4e4>
+ 8008540:	10815568 	cmpgeui	r2,r2,1365
+ 8008544:	1000191e 	bne	r2,zero,80085ac <_malloc_r+0x7d0>
+ 8008548:	8804d4ba 	srli	r2,r17,18
+ 800854c:	11801f44 	addi	r6,r2,125
+ 8008550:	12001f04 	addi	r8,r2,124
+ 8008554:	300a90fa 	slli	r5,r6,3
+ 8008558:	003e5906 	br	8007ec0 <_malloc_r+0xe4>
+ 800855c:	e73ffe04 	addi	fp,fp,-8
+ 8008560:	a729883a 	add	r20,r20,fp
+ 8008564:	a5e9c83a 	sub	r20,r20,r23
+ 8008568:	002b883a 	mov	r21,zero
+ 800856c:	003f1906 	br	80081d4 <_malloc_r+0x3f8>
+ 8008570:	81400204 	addi	r5,r16,8
+ 8008574:	9009883a 	mov	r4,r18
+ 8008578:	80071c40 	call	80071c4 <_free_r>
+ 800857c:	9c000217 	ldw	r16,8(r19)
+ 8008580:	00820174 	movhi	r2,2053
+ 8008584:	10b36417 	ldw	r2,-12912(r2)
+ 8008588:	85000117 	ldw	r20,4(r16)
+ 800858c:	003f2b06 	br	800823c <_malloc_r+0x460>
+ 8008590:	18c15568 	cmpgeui	r3,r3,1365
+ 8008594:	1800091e 	bne	r3,zero,80085bc <_malloc_r+0x7e0>
+ 8008598:	1006d4ba 	srli	r3,r2,18
+ 800859c:	19401f44 	addi	r5,r3,125
+ 80085a0:	19001f04 	addi	r4,r3,124
+ 80085a4:	280a90fa 	slli	r5,r5,3
+ 80085a8:	003f4506 	br	80082c0 <_malloc_r+0x4e4>
+ 80085ac:	0140fe04 	movi	r5,1016
+ 80085b0:	01801fc4 	movi	r6,127
+ 80085b4:	02001f84 	movi	r8,126
+ 80085b8:	003e4106 	br	8007ec0 <_malloc_r+0xe4>
+ 80085bc:	0140fe04 	movi	r5,1016
+ 80085c0:	01001f84 	movi	r4,126
+ 80085c4:	003f3e06 	br	80082c0 <_malloc_r+0x4e4>
+ 80085c8:	98800117 	ldw	r2,4(r19)
+ 80085cc:	003f9506 	br	8008424 <_malloc_r+0x648>
+
+080085d0 <memchr>:
+ 80085d0:	208000cc 	andi	r2,r4,3
+ 80085d4:	280f883a 	mov	r7,r5
+ 80085d8:	10003526 	beq	r2,zero,80086b0 <memchr+0xe0>
+ 80085dc:	30bfffc4 	addi	r2,r6,-1
+ 80085e0:	30001926 	beq	r6,zero,8008648 <memchr+0x78>
+ 80085e4:	20c00003 	ldbu	r3,0(r4)
+ 80085e8:	29803fcc 	andi	r6,r5,255
+ 80085ec:	30c0061e 	bne	r6,r3,8008608 <memchr+0x38>
+ 80085f0:	00001706 	br	8008650 <memchr+0x80>
+ 80085f4:	10bfffc4 	addi	r2,r2,-1
+ 80085f8:	10ffffe0 	cmpeqi	r3,r2,-1
+ 80085fc:	1800121e 	bne	r3,zero,8008648 <memchr+0x78>
+ 8008600:	20c00003 	ldbu	r3,0(r4)
+ 8008604:	19801226 	beq	r3,r6,8008650 <memchr+0x80>
+ 8008608:	21000044 	addi	r4,r4,1
+ 800860c:	20c000cc 	andi	r3,r4,3
+ 8008610:	183ff81e 	bne	r3,zero,80085f4 <memchr+0x24>
+ 8008614:	10c00128 	cmpgeui	r3,r2,4
+ 8008618:	18000f1e 	bne	r3,zero,8008658 <memchr+0x88>
+ 800861c:	10000a26 	beq	r2,zero,8008648 <memchr+0x78>
+ 8008620:	20c00003 	ldbu	r3,0(r4)
+ 8008624:	29403fcc 	andi	r5,r5,255
+ 8008628:	19400926 	beq	r3,r5,8008650 <memchr+0x80>
+ 800862c:	2085883a 	add	r2,r4,r2
+ 8008630:	39403fcc 	andi	r5,r7,255
+ 8008634:	00000206 	br	8008640 <memchr+0x70>
+ 8008638:	20c00003 	ldbu	r3,0(r4)
+ 800863c:	19400426 	beq	r3,r5,8008650 <memchr+0x80>
+ 8008640:	21000044 	addi	r4,r4,1
+ 8008644:	113ffc1e 	bne	r2,r4,8008638 <memchr+0x68>
+ 8008648:	0005883a 	mov	r2,zero
+ 800864c:	f800283a 	ret
+ 8008650:	2005883a 	mov	r2,r4
+ 8008654:	f800283a 	ret
+ 8008658:	280c923a 	slli	r6,r5,8
+ 800865c:	2a403fcc 	andi	r9,r5,255
+ 8008660:	02bfbff4 	movhi	r10,65279
+ 8008664:	31bfffcc 	andi	r6,r6,65535
+ 8008668:	3246b03a 	or	r3,r6,r9
+ 800866c:	1812943a 	slli	r9,r3,16
+ 8008670:	02202074 	movhi	r8,32897
+ 8008674:	52bfbfc4 	addi	r10,r10,-257
+ 8008678:	48d2b03a 	or	r9,r9,r3
+ 800867c:	42202004 	addi	r8,r8,-32640
+ 8008680:	20c00017 	ldw	r3,0(r4)
+ 8008684:	48c6f03a 	xor	r3,r9,r3
+ 8008688:	1a8d883a 	add	r6,r3,r10
+ 800868c:	00c6303a 	nor	r3,zero,r3
+ 8008690:	30c6703a 	and	r3,r6,r3
+ 8008694:	1a06703a 	and	r3,r3,r8
+ 8008698:	183fe11e 	bne	r3,zero,8008620 <memchr+0x50>
+ 800869c:	10bfff04 	addi	r2,r2,-4
+ 80086a0:	10c00128 	cmpgeui	r3,r2,4
+ 80086a4:	21000104 	addi	r4,r4,4
+ 80086a8:	183ff51e 	bne	r3,zero,8008680 <memchr+0xb0>
+ 80086ac:	003fdb06 	br	800861c <memchr+0x4c>
+ 80086b0:	3005883a 	mov	r2,r6
+ 80086b4:	003fd706 	br	8008614 <memchr+0x44>
+
+080086b8 <memcpy>:
+ 80086b8:	30c00430 	cmpltui	r3,r6,16
+ 80086bc:	2005883a 	mov	r2,r4
+ 80086c0:	18002d1e 	bne	r3,zero,8008778 <memcpy+0xc0>
+ 80086c4:	2906b03a 	or	r3,r5,r4
+ 80086c8:	18c000cc 	andi	r3,r3,3
+ 80086cc:	1800351e 	bne	r3,zero,80087a4 <memcpy+0xec>
+ 80086d0:	32fffc04 	addi	r11,r6,-16
+ 80086d4:	5816d13a 	srli	r11,r11,4
+ 80086d8:	2007883a 	mov	r3,r4
+ 80086dc:	280f883a 	mov	r7,r5
+ 80086e0:	5ac00044 	addi	r11,r11,1
+ 80086e4:	5816913a 	slli	r11,r11,4
+ 80086e8:	22c9883a 	add	r4,r4,r11
+ 80086ec:	3a000017 	ldw	r8,0(r7)
+ 80086f0:	3a800117 	ldw	r10,4(r7)
+ 80086f4:	3a400217 	ldw	r9,8(r7)
+ 80086f8:	39c00404 	addi	r7,r7,16
+ 80086fc:	1a000015 	stw	r8,0(r3)
+ 8008700:	3a3fff17 	ldw	r8,-4(r7)
+ 8008704:	1a800115 	stw	r10,4(r3)
+ 8008708:	1a400215 	stw	r9,8(r3)
+ 800870c:	18c00404 	addi	r3,r3,16
+ 8008710:	1a3fff15 	stw	r8,-4(r3)
+ 8008714:	20fff51e 	bne	r4,r3,80086ec <memcpy+0x34>
+ 8008718:	3100030c 	andi	r4,r6,12
+ 800871c:	2acb883a 	add	r5,r5,r11
+ 8008720:	320003cc 	andi	r8,r6,15
+ 8008724:	20002226 	beq	r4,zero,80087b0 <memcpy+0xf8>
+ 8008728:	2809883a 	mov	r4,r5
+ 800872c:	1813883a 	mov	r9,r3
+ 8008730:	21000104 	addi	r4,r4,4
+ 8008734:	22bfff17 	ldw	r10,-4(r4)
+ 8008738:	410fc83a 	sub	r7,r8,r4
+ 800873c:	4a400104 	addi	r9,r9,4
+ 8008740:	29cf883a 	add	r7,r5,r7
+ 8008744:	4abfff15 	stw	r10,-4(r9)
+ 8008748:	39c00128 	cmpgeui	r7,r7,4
+ 800874c:	383ff81e 	bne	r7,zero,8008730 <memcpy+0x78>
+ 8008750:	413fff04 	addi	r4,r8,-4
+ 8008754:	2008d0ba 	srli	r4,r4,2
+ 8008758:	318000cc 	andi	r6,r6,3
+ 800875c:	31ffffc4 	addi	r7,r6,-1
+ 8008760:	21000044 	addi	r4,r4,1
+ 8008764:	200890ba 	slli	r4,r4,2
+ 8008768:	1907883a 	add	r3,r3,r4
+ 800876c:	290b883a 	add	r5,r5,r4
+ 8008770:	3000041e 	bne	r6,zero,8008784 <memcpy+0xcc>
+ 8008774:	f800283a 	ret
+ 8008778:	2007883a 	mov	r3,r4
+ 800877c:	31ffffc4 	addi	r7,r6,-1
+ 8008780:	303ffc26 	beq	r6,zero,8008774 <memcpy+0xbc>
+ 8008784:	39c00044 	addi	r7,r7,1
+ 8008788:	19cf883a 	add	r7,r3,r7
+ 800878c:	29400044 	addi	r5,r5,1
+ 8008790:	29bfffc3 	ldbu	r6,-1(r5)
+ 8008794:	18c00044 	addi	r3,r3,1
+ 8008798:	19bfffc5 	stb	r6,-1(r3)
+ 800879c:	19fffb1e 	bne	r3,r7,800878c <memcpy+0xd4>
+ 80087a0:	f800283a 	ret
+ 80087a4:	31ffffc4 	addi	r7,r6,-1
+ 80087a8:	2007883a 	mov	r3,r4
+ 80087ac:	003ff506 	br	8008784 <memcpy+0xcc>
+ 80087b0:	400d883a 	mov	r6,r8
+ 80087b4:	003ff106 	br	800877c <memcpy+0xc4>
+
+080087b8 <memmove>:
+ 80087b8:	2005883a 	mov	r2,r4
+ 80087bc:	29000a2e 	bgeu	r5,r4,80087e8 <memmove+0x30>
+ 80087c0:	2989883a 	add	r4,r5,r6
+ 80087c4:	1100082e 	bgeu	r2,r4,80087e8 <memmove+0x30>
+ 80087c8:	1187883a 	add	r3,r2,r6
+ 80087cc:	30003e26 	beq	r6,zero,80088c8 <memmove+0x110>
+ 80087d0:	213fffc4 	addi	r4,r4,-1
+ 80087d4:	21400003 	ldbu	r5,0(r4)
+ 80087d8:	18ffffc4 	addi	r3,r3,-1
+ 80087dc:	19400005 	stb	r5,0(r3)
+ 80087e0:	10fffb1e 	bne	r2,r3,80087d0 <memmove+0x18>
+ 80087e4:	f800283a 	ret
+ 80087e8:	30c00430 	cmpltui	r3,r6,16
+ 80087ec:	18000b26 	beq	r3,zero,800881c <memmove+0x64>
+ 80087f0:	1007883a 	mov	r3,r2
+ 80087f4:	31ffffc4 	addi	r7,r6,-1
+ 80087f8:	30003726 	beq	r6,zero,80088d8 <memmove+0x120>
+ 80087fc:	39c00044 	addi	r7,r7,1
+ 8008800:	29cf883a 	add	r7,r5,r7
+ 8008804:	29400044 	addi	r5,r5,1
+ 8008808:	29bfffc3 	ldbu	r6,-1(r5)
+ 800880c:	18c00044 	addi	r3,r3,1
+ 8008810:	19bfffc5 	stb	r6,-1(r3)
+ 8008814:	29fffb1e 	bne	r5,r7,8008804 <memmove+0x4c>
+ 8008818:	f800283a 	ret
+ 800881c:	2886b03a 	or	r3,r5,r2
+ 8008820:	18c000cc 	andi	r3,r3,3
+ 8008824:	1800291e 	bne	r3,zero,80088cc <memmove+0x114>
+ 8008828:	327ffc04 	addi	r9,r6,-16
+ 800882c:	4812d13a 	srli	r9,r9,4
+ 8008830:	280f883a 	mov	r7,r5
+ 8008834:	1007883a 	mov	r3,r2
+ 8008838:	4a400044 	addi	r9,r9,1
+ 800883c:	4812913a 	slli	r9,r9,4
+ 8008840:	1251883a 	add	r8,r2,r9
+ 8008844:	39000017 	ldw	r4,0(r7)
+ 8008848:	18c00404 	addi	r3,r3,16
+ 800884c:	39c00404 	addi	r7,r7,16
+ 8008850:	193ffc15 	stw	r4,-16(r3)
+ 8008854:	393ffd17 	ldw	r4,-12(r7)
+ 8008858:	193ffd15 	stw	r4,-12(r3)
+ 800885c:	393ffe17 	ldw	r4,-8(r7)
+ 8008860:	193ffe15 	stw	r4,-8(r3)
+ 8008864:	393fff17 	ldw	r4,-4(r7)
+ 8008868:	193fff15 	stw	r4,-4(r3)
+ 800886c:	40fff51e 	bne	r8,r3,8008844 <memmove+0x8c>
+ 8008870:	3100030c 	andi	r4,r6,12
+ 8008874:	2a4b883a 	add	r5,r5,r9
+ 8008878:	320003cc 	andi	r8,r6,15
+ 800887c:	20001726 	beq	r4,zero,80088dc <memmove+0x124>
+ 8008880:	2813883a 	mov	r9,r5
+ 8008884:	180f883a 	mov	r7,r3
+ 8008888:	4a400104 	addi	r9,r9,4
+ 800888c:	39c00104 	addi	r7,r7,4
+ 8008890:	4abfff17 	ldw	r10,-4(r9)
+ 8008894:	41c9c83a 	sub	r4,r8,r7
+ 8008898:	1909883a 	add	r4,r3,r4
+ 800889c:	3abfff15 	stw	r10,-4(r7)
+ 80088a0:	21000128 	cmpgeui	r4,r4,4
+ 80088a4:	203ff81e 	bne	r4,zero,8008888 <memmove+0xd0>
+ 80088a8:	413fff04 	addi	r4,r8,-4
+ 80088ac:	2008d0ba 	srli	r4,r4,2
+ 80088b0:	318000cc 	andi	r6,r6,3
+ 80088b4:	21000044 	addi	r4,r4,1
+ 80088b8:	200890ba 	slli	r4,r4,2
+ 80088bc:	1907883a 	add	r3,r3,r4
+ 80088c0:	290b883a 	add	r5,r5,r4
+ 80088c4:	003fcb06 	br	80087f4 <memmove+0x3c>
+ 80088c8:	f800283a 	ret
+ 80088cc:	31ffffc4 	addi	r7,r6,-1
+ 80088d0:	1007883a 	mov	r3,r2
+ 80088d4:	003fc906 	br	80087fc <memmove+0x44>
+ 80088d8:	f800283a 	ret
+ 80088dc:	400d883a 	mov	r6,r8
+ 80088e0:	003fc406 	br	80087f4 <memmove+0x3c>
+
+080088e4 <memset>:
+ 80088e4:	20c000cc 	andi	r3,r4,3
+ 80088e8:	2005883a 	mov	r2,r4
+ 80088ec:	18003626 	beq	r3,zero,80089c8 <memset+0xe4>
+ 80088f0:	31ffffc4 	addi	r7,r6,-1
+ 80088f4:	30003326 	beq	r6,zero,80089c4 <memset+0xe0>
+ 80088f8:	2811883a 	mov	r8,r5
+ 80088fc:	2007883a 	mov	r3,r4
+ 8008900:	00000306 	br	8008910 <memset+0x2c>
+ 8008904:	39ffffc4 	addi	r7,r7,-1
+ 8008908:	39bfffe0 	cmpeqi	r6,r7,-1
+ 800890c:	30002d1e 	bne	r6,zero,80089c4 <memset+0xe0>
+ 8008910:	18c00044 	addi	r3,r3,1
+ 8008914:	1a3fffc5 	stb	r8,-1(r3)
+ 8008918:	198000cc 	andi	r6,r3,3
+ 800891c:	303ff91e 	bne	r6,zero,8008904 <memset+0x20>
+ 8008920:	39000130 	cmpltui	r4,r7,4
+ 8008924:	2000221e 	bne	r4,zero,80089b0 <memset+0xcc>
+ 8008928:	29003fcc 	andi	r4,r5,255
+ 800892c:	200c923a 	slli	r6,r4,8
+ 8008930:	3a000430 	cmpltui	r8,r7,16
+ 8008934:	3108b03a 	or	r4,r6,r4
+ 8008938:	200c943a 	slli	r6,r4,16
+ 800893c:	310cb03a 	or	r6,r6,r4
+ 8008940:	40000e1e 	bne	r8,zero,800897c <memset+0x98>
+ 8008944:	3a3ffc04 	addi	r8,r7,-16
+ 8008948:	4010d13a 	srli	r8,r8,4
+ 800894c:	42000044 	addi	r8,r8,1
+ 8008950:	4010913a 	slli	r8,r8,4
+ 8008954:	1a11883a 	add	r8,r3,r8
+ 8008958:	19800015 	stw	r6,0(r3)
+ 800895c:	19800115 	stw	r6,4(r3)
+ 8008960:	19800215 	stw	r6,8(r3)
+ 8008964:	18c00404 	addi	r3,r3,16
+ 8008968:	19bfff15 	stw	r6,-4(r3)
+ 800896c:	40fffa1e 	bne	r8,r3,8008958 <memset+0x74>
+ 8008970:	3900030c 	andi	r4,r7,12
+ 8008974:	39c003cc 	andi	r7,r7,15
+ 8008978:	20000d26 	beq	r4,zero,80089b0 <memset+0xcc>
+ 800897c:	1809883a 	mov	r4,r3
+ 8008980:	21000104 	addi	r4,r4,4
+ 8008984:	3911c83a 	sub	r8,r7,r4
+ 8008988:	1a11883a 	add	r8,r3,r8
+ 800898c:	21bfff15 	stw	r6,-4(r4)
+ 8008990:	42000128 	cmpgeui	r8,r8,4
+ 8008994:	403ffa1e 	bne	r8,zero,8008980 <memset+0x9c>
+ 8008998:	393fff04 	addi	r4,r7,-4
+ 800899c:	2008d0ba 	srli	r4,r4,2
+ 80089a0:	39c000cc 	andi	r7,r7,3
+ 80089a4:	21000044 	addi	r4,r4,1
+ 80089a8:	200890ba 	slli	r4,r4,2
+ 80089ac:	1907883a 	add	r3,r3,r4
+ 80089b0:	38000426 	beq	r7,zero,80089c4 <memset+0xe0>
+ 80089b4:	19cf883a 	add	r7,r3,r7
+ 80089b8:	18c00044 	addi	r3,r3,1
+ 80089bc:	197fffc5 	stb	r5,-1(r3)
+ 80089c0:	38fffd1e 	bne	r7,r3,80089b8 <memset+0xd4>
+ 80089c4:	f800283a 	ret
+ 80089c8:	2007883a 	mov	r3,r4
+ 80089cc:	300f883a 	mov	r7,r6
+ 80089d0:	003fd306 	br	8008920 <memset+0x3c>
+
+080089d4 <_Balloc>:
+ 80089d4:	20801317 	ldw	r2,76(r4)
+ 80089d8:	defffc04 	addi	sp,sp,-16
+ 80089dc:	dc400115 	stw	r17,4(sp)
+ 80089e0:	dc000015 	stw	r16,0(sp)
+ 80089e4:	dfc00315 	stw	ra,12(sp)
+ 80089e8:	dc800215 	stw	r18,8(sp)
+ 80089ec:	2021883a 	mov	r16,r4
+ 80089f0:	2823883a 	mov	r17,r5
+ 80089f4:	10000e26 	beq	r2,zero,8008a30 <_Balloc+0x5c>
+ 80089f8:	880690ba 	slli	r3,r17,2
+ 80089fc:	10c7883a 	add	r3,r2,r3
+ 8008a00:	18800017 	ldw	r2,0(r3)
+ 8008a04:	10001126 	beq	r2,zero,8008a4c <_Balloc+0x78>
+ 8008a08:	11000017 	ldw	r4,0(r2)
+ 8008a0c:	19000015 	stw	r4,0(r3)
+ 8008a10:	10000415 	stw	zero,16(r2)
+ 8008a14:	10000315 	stw	zero,12(r2)
+ 8008a18:	dfc00317 	ldw	ra,12(sp)
+ 8008a1c:	dc800217 	ldw	r18,8(sp)
+ 8008a20:	dc400117 	ldw	r17,4(sp)
+ 8008a24:	dc000017 	ldw	r16,0(sp)
+ 8008a28:	dec00404 	addi	sp,sp,16
+ 8008a2c:	f800283a 	ret
+ 8008a30:	01800844 	movi	r6,33
+ 8008a34:	01400104 	movi	r5,4
+ 8008a38:	800ba2c0 	call	800ba2c <_calloc_r>
+ 8008a3c:	80801315 	stw	r2,76(r16)
+ 8008a40:	103fed1e 	bne	r2,zero,80089f8 <_Balloc+0x24>
+ 8008a44:	0005883a 	mov	r2,zero
+ 8008a48:	003ff306 	br	8008a18 <_Balloc+0x44>
+ 8008a4c:	04800044 	movi	r18,1
+ 8008a50:	9464983a 	sll	r18,r18,r17
+ 8008a54:	01400044 	movi	r5,1
+ 8008a58:	8009883a 	mov	r4,r16
+ 8008a5c:	91800144 	addi	r6,r18,5
+ 8008a60:	300c90ba 	slli	r6,r6,2
+ 8008a64:	800ba2c0 	call	800ba2c <_calloc_r>
+ 8008a68:	103ff626 	beq	r2,zero,8008a44 <_Balloc+0x70>
+ 8008a6c:	14400115 	stw	r17,4(r2)
+ 8008a70:	14800215 	stw	r18,8(r2)
+ 8008a74:	003fe606 	br	8008a10 <_Balloc+0x3c>
+
+08008a78 <_Bfree>:
+ 8008a78:	28000726 	beq	r5,zero,8008a98 <_Bfree+0x20>
+ 8008a7c:	28c00117 	ldw	r3,4(r5)
+ 8008a80:	20801317 	ldw	r2,76(r4)
+ 8008a84:	180690ba 	slli	r3,r3,2
+ 8008a88:	10c5883a 	add	r2,r2,r3
+ 8008a8c:	10c00017 	ldw	r3,0(r2)
+ 8008a90:	28c00015 	stw	r3,0(r5)
+ 8008a94:	11400015 	stw	r5,0(r2)
+ 8008a98:	f800283a 	ret
+
+08008a9c <__multadd>:
+ 8008a9c:	defffa04 	addi	sp,sp,-24
+ 8008aa0:	dc800315 	stw	r18,12(sp)
+ 8008aa4:	dc400215 	stw	r17,8(sp)
+ 8008aa8:	dc000115 	stw	r16,4(sp)
+ 8008aac:	2823883a 	mov	r17,r5
+ 8008ab0:	2c000417 	ldw	r16,16(r5)
+ 8008ab4:	2025883a 	mov	r18,r4
+ 8008ab8:	dfc00515 	stw	ra,20(sp)
+ 8008abc:	29000504 	addi	r4,r5,20
+ 8008ac0:	dcc00415 	stw	r19,16(sp)
+ 8008ac4:	000b883a 	mov	r5,zero
+ 8008ac8:	20800017 	ldw	r2,0(r4)
+ 8008acc:	21000104 	addi	r4,r4,4
+ 8008ad0:	29400044 	addi	r5,r5,1
+ 8008ad4:	10ffffcc 	andi	r3,r2,65535
+ 8008ad8:	1987383a 	mul	r3,r3,r6
+ 8008adc:	1004d43a 	srli	r2,r2,16
+ 8008ae0:	19cf883a 	add	r7,r3,r7
+ 8008ae4:	1185383a 	mul	r2,r2,r6
+ 8008ae8:	3810d43a 	srli	r8,r7,16
+ 8008aec:	38ffffcc 	andi	r3,r7,65535
+ 8008af0:	120f883a 	add	r7,r2,r8
+ 8008af4:	3804943a 	slli	r2,r7,16
+ 8008af8:	380ed43a 	srli	r7,r7,16
+ 8008afc:	10c7883a 	add	r3,r2,r3
+ 8008b00:	20ffff15 	stw	r3,-4(r4)
+ 8008b04:	2c3ff016 	blt	r5,r16,8008ac8 <__multadd+0x2c>
+ 8008b08:	38000826 	beq	r7,zero,8008b2c <__multadd+0x90>
+ 8008b0c:	88800217 	ldw	r2,8(r17)
+ 8008b10:	80800e0e 	bge	r16,r2,8008b4c <__multadd+0xb0>
+ 8008b14:	80800144 	addi	r2,r16,5
+ 8008b18:	100490ba 	slli	r2,r2,2
+ 8008b1c:	84000044 	addi	r16,r16,1
+ 8008b20:	8885883a 	add	r2,r17,r2
+ 8008b24:	11c00015 	stw	r7,0(r2)
+ 8008b28:	8c000415 	stw	r16,16(r17)
+ 8008b2c:	8805883a 	mov	r2,r17
+ 8008b30:	dfc00517 	ldw	ra,20(sp)
+ 8008b34:	dcc00417 	ldw	r19,16(sp)
+ 8008b38:	dc800317 	ldw	r18,12(sp)
+ 8008b3c:	dc400217 	ldw	r17,8(sp)
+ 8008b40:	dc000117 	ldw	r16,4(sp)
+ 8008b44:	dec00604 	addi	sp,sp,24
+ 8008b48:	f800283a 	ret
+ 8008b4c:	89400117 	ldw	r5,4(r17)
+ 8008b50:	9009883a 	mov	r4,r18
+ 8008b54:	d9c00015 	stw	r7,0(sp)
+ 8008b58:	29400044 	addi	r5,r5,1
+ 8008b5c:	80089d40 	call	80089d4 <_Balloc>
+ 8008b60:	89800417 	ldw	r6,16(r17)
+ 8008b64:	89400304 	addi	r5,r17,12
+ 8008b68:	11000304 	addi	r4,r2,12
+ 8008b6c:	31800084 	addi	r6,r6,2
+ 8008b70:	300c90ba 	slli	r6,r6,2
+ 8008b74:	1027883a 	mov	r19,r2
+ 8008b78:	80086b80 	call	80086b8 <memcpy>
+ 8008b7c:	d9c00017 	ldw	r7,0(sp)
+ 8008b80:	88000926 	beq	r17,zero,8008ba8 <__multadd+0x10c>
+ 8008b84:	88c00117 	ldw	r3,4(r17)
+ 8008b88:	90801317 	ldw	r2,76(r18)
+ 8008b8c:	180690ba 	slli	r3,r3,2
+ 8008b90:	10c5883a 	add	r2,r2,r3
+ 8008b94:	10c00017 	ldw	r3,0(r2)
+ 8008b98:	88c00015 	stw	r3,0(r17)
+ 8008b9c:	14400015 	stw	r17,0(r2)
+ 8008ba0:	9823883a 	mov	r17,r19
+ 8008ba4:	003fdb06 	br	8008b14 <__multadd+0x78>
+ 8008ba8:	9823883a 	mov	r17,r19
+ 8008bac:	003fd906 	br	8008b14 <__multadd+0x78>
+
+08008bb0 <__s2b>:
+ 8008bb0:	defff904 	addi	sp,sp,-28
+ 8008bb4:	dc800215 	stw	r18,8(sp)
+ 8008bb8:	dc000015 	stw	r16,0(sp)
+ 8008bbc:	2025883a 	mov	r18,r4
+ 8008bc0:	2821883a 	mov	r16,r5
+ 8008bc4:	39000204 	addi	r4,r7,8
+ 8008bc8:	01400244 	movi	r5,9
+ 8008bcc:	dcc00315 	stw	r19,12(sp)
+ 8008bd0:	dc400115 	stw	r17,4(sp)
+ 8008bd4:	dfc00615 	stw	ra,24(sp)
+ 8008bd8:	3823883a 	mov	r17,r7
+ 8008bdc:	dd400515 	stw	r21,20(sp)
+ 8008be0:	dd000415 	stw	r20,16(sp)
+ 8008be4:	3027883a 	mov	r19,r6
+ 8008be8:	800cf000 	call	800cf00 <__divsi3>
+ 8008bec:	88c00290 	cmplti	r3,r17,10
+ 8008bf0:	1800311e 	bne	r3,zero,8008cb8 <__s2b+0x108>
+ 8008bf4:	00c00044 	movi	r3,1
+ 8008bf8:	000b883a 	mov	r5,zero
+ 8008bfc:	18c7883a 	add	r3,r3,r3
+ 8008c00:	29400044 	addi	r5,r5,1
+ 8008c04:	18bffd16 	blt	r3,r2,8008bfc <__s2b+0x4c>
+ 8008c08:	9009883a 	mov	r4,r18
+ 8008c0c:	80089d40 	call	80089d4 <_Balloc>
+ 8008c10:	d8c00717 	ldw	r3,28(sp)
+ 8008c14:	10c00515 	stw	r3,20(r2)
+ 8008c18:	00c00044 	movi	r3,1
+ 8008c1c:	10c00415 	stw	r3,16(r2)
+ 8008c20:	98c00290 	cmplti	r3,r19,10
+ 8008c24:	1800211e 	bne	r3,zero,8008cac <__s2b+0xfc>
+ 8008c28:	85400244 	addi	r21,r16,9
+ 8008c2c:	84e9883a 	add	r20,r16,r19
+ 8008c30:	a821883a 	mov	r16,r21
+ 8008c34:	84000044 	addi	r16,r16,1
+ 8008c38:	81ffffc7 	ldb	r7,-1(r16)
+ 8008c3c:	01800284 	movi	r6,10
+ 8008c40:	100b883a 	mov	r5,r2
+ 8008c44:	39fff404 	addi	r7,r7,-48
+ 8008c48:	9009883a 	mov	r4,r18
+ 8008c4c:	8008a9c0 	call	8008a9c <__multadd>
+ 8008c50:	a43ff81e 	bne	r20,r16,8008c34 <__s2b+0x84>
+ 8008c54:	9c3ffe04 	addi	r16,r19,-8
+ 8008c58:	ac21883a 	add	r16,r21,r16
+ 8008c5c:	9c400a0e 	bge	r19,r17,8008c88 <__s2b+0xd8>
+ 8008c60:	8ce3c83a 	sub	r17,r17,r19
+ 8008c64:	8463883a 	add	r17,r16,r17
+ 8008c68:	84000044 	addi	r16,r16,1
+ 8008c6c:	81ffffc7 	ldb	r7,-1(r16)
+ 8008c70:	01800284 	movi	r6,10
+ 8008c74:	100b883a 	mov	r5,r2
+ 8008c78:	39fff404 	addi	r7,r7,-48
+ 8008c7c:	9009883a 	mov	r4,r18
+ 8008c80:	8008a9c0 	call	8008a9c <__multadd>
+ 8008c84:	8c3ff81e 	bne	r17,r16,8008c68 <__s2b+0xb8>
+ 8008c88:	dfc00617 	ldw	ra,24(sp)
+ 8008c8c:	dd400517 	ldw	r21,20(sp)
+ 8008c90:	dd000417 	ldw	r20,16(sp)
+ 8008c94:	dcc00317 	ldw	r19,12(sp)
+ 8008c98:	dc800217 	ldw	r18,8(sp)
+ 8008c9c:	dc400117 	ldw	r17,4(sp)
+ 8008ca0:	dc000017 	ldw	r16,0(sp)
+ 8008ca4:	dec00704 	addi	sp,sp,28
+ 8008ca8:	f800283a 	ret
+ 8008cac:	84000284 	addi	r16,r16,10
+ 8008cb0:	04c00244 	movi	r19,9
+ 8008cb4:	003fe906 	br	8008c5c <__s2b+0xac>
+ 8008cb8:	000b883a 	mov	r5,zero
+ 8008cbc:	003fd206 	br	8008c08 <__s2b+0x58>
+
+08008cc0 <__hi0bits>:
+ 8008cc0:	20bfffec 	andhi	r2,r4,65535
+ 8008cc4:	1000131e 	bne	r2,zero,8008d14 <__hi0bits+0x54>
+ 8008cc8:	2008943a 	slli	r4,r4,16
+ 8008ccc:	00800404 	movi	r2,16
+ 8008cd0:	20ffc02c 	andhi	r3,r4,65280
+ 8008cd4:	1800021e 	bne	r3,zero,8008ce0 <__hi0bits+0x20>
+ 8008cd8:	2008923a 	slli	r4,r4,8
+ 8008cdc:	10800204 	addi	r2,r2,8
+ 8008ce0:	20fc002c 	andhi	r3,r4,61440
+ 8008ce4:	1800021e 	bne	r3,zero,8008cf0 <__hi0bits+0x30>
+ 8008ce8:	2008913a 	slli	r4,r4,4
+ 8008cec:	10800104 	addi	r2,r2,4
+ 8008cf0:	20f0002c 	andhi	r3,r4,49152
+ 8008cf4:	1800021e 	bne	r3,zero,8008d00 <__hi0bits+0x40>
+ 8008cf8:	200890ba 	slli	r4,r4,2
+ 8008cfc:	10800084 	addi	r2,r2,2
+ 8008d00:	20000316 	blt	r4,zero,8008d10 <__hi0bits+0x50>
+ 8008d04:	2110002c 	andhi	r4,r4,16384
+ 8008d08:	10800044 	addi	r2,r2,1
+ 8008d0c:	20000326 	beq	r4,zero,8008d1c <__hi0bits+0x5c>
+ 8008d10:	f800283a 	ret
+ 8008d14:	0005883a 	mov	r2,zero
+ 8008d18:	003fed06 	br	8008cd0 <__hi0bits+0x10>
+ 8008d1c:	00800804 	movi	r2,32
+ 8008d20:	f800283a 	ret
+
+08008d24 <__lo0bits>:
+ 8008d24:	20c00017 	ldw	r3,0(r4)
+ 8008d28:	188001cc 	andi	r2,r3,7
+ 8008d2c:	10000826 	beq	r2,zero,8008d50 <__lo0bits+0x2c>
+ 8008d30:	1880004c 	andi	r2,r3,1
+ 8008d34:	10001f1e 	bne	r2,zero,8008db4 <__lo0bits+0x90>
+ 8008d38:	1880008c 	andi	r2,r3,2
+ 8008d3c:	10002126 	beq	r2,zero,8008dc4 <__lo0bits+0xa0>
+ 8008d40:	1806d07a 	srli	r3,r3,1
+ 8008d44:	00800044 	movi	r2,1
+ 8008d48:	20c00015 	stw	r3,0(r4)
+ 8008d4c:	f800283a 	ret
+ 8008d50:	18bfffcc 	andi	r2,r3,65535
+ 8008d54:	1000151e 	bne	r2,zero,8008dac <__lo0bits+0x88>
+ 8008d58:	1806d43a 	srli	r3,r3,16
+ 8008d5c:	00800404 	movi	r2,16
+ 8008d60:	19403fcc 	andi	r5,r3,255
+ 8008d64:	2800021e 	bne	r5,zero,8008d70 <__lo0bits+0x4c>
+ 8008d68:	1806d23a 	srli	r3,r3,8
+ 8008d6c:	10800204 	addi	r2,r2,8
+ 8008d70:	194003cc 	andi	r5,r3,15
+ 8008d74:	2800021e 	bne	r5,zero,8008d80 <__lo0bits+0x5c>
+ 8008d78:	1806d13a 	srli	r3,r3,4
+ 8008d7c:	10800104 	addi	r2,r2,4
+ 8008d80:	194000cc 	andi	r5,r3,3
+ 8008d84:	2800021e 	bne	r5,zero,8008d90 <__lo0bits+0x6c>
+ 8008d88:	1806d0ba 	srli	r3,r3,2
+ 8008d8c:	10800084 	addi	r2,r2,2
+ 8008d90:	1940004c 	andi	r5,r3,1
+ 8008d94:	2800031e 	bne	r5,zero,8008da4 <__lo0bits+0x80>
+ 8008d98:	1806d07a 	srli	r3,r3,1
+ 8008d9c:	10800044 	addi	r2,r2,1
+ 8008da0:	18000626 	beq	r3,zero,8008dbc <__lo0bits+0x98>
+ 8008da4:	20c00015 	stw	r3,0(r4)
+ 8008da8:	f800283a 	ret
+ 8008dac:	0005883a 	mov	r2,zero
+ 8008db0:	003feb06 	br	8008d60 <__lo0bits+0x3c>
+ 8008db4:	0005883a 	mov	r2,zero
+ 8008db8:	f800283a 	ret
+ 8008dbc:	00800804 	movi	r2,32
+ 8008dc0:	f800283a 	ret
+ 8008dc4:	1806d0ba 	srli	r3,r3,2
+ 8008dc8:	00800084 	movi	r2,2
+ 8008dcc:	20c00015 	stw	r3,0(r4)
+ 8008dd0:	f800283a 	ret
+
+08008dd4 <__i2b>:
+ 8008dd4:	defffe04 	addi	sp,sp,-8
+ 8008dd8:	dc000015 	stw	r16,0(sp)
+ 8008ddc:	2821883a 	mov	r16,r5
+ 8008de0:	01400044 	movi	r5,1
+ 8008de4:	dfc00115 	stw	ra,4(sp)
+ 8008de8:	80089d40 	call	80089d4 <_Balloc>
+ 8008dec:	01000044 	movi	r4,1
+ 8008df0:	14000515 	stw	r16,20(r2)
+ 8008df4:	11000415 	stw	r4,16(r2)
+ 8008df8:	dfc00117 	ldw	ra,4(sp)
+ 8008dfc:	dc000017 	ldw	r16,0(sp)
+ 8008e00:	dec00204 	addi	sp,sp,8
+ 8008e04:	f800283a 	ret
+
+08008e08 <__multiply>:
+ 8008e08:	defffa04 	addi	sp,sp,-24
+ 8008e0c:	dd000415 	stw	r20,16(sp)
+ 8008e10:	dcc00315 	stw	r19,12(sp)
+ 8008e14:	35000417 	ldw	r20,16(r6)
+ 8008e18:	2cc00417 	ldw	r19,16(r5)
+ 8008e1c:	dc800215 	stw	r18,8(sp)
+ 8008e20:	dc400115 	stw	r17,4(sp)
+ 8008e24:	dfc00515 	stw	ra,20(sp)
+ 8008e28:	dc000015 	stw	r16,0(sp)
+ 8008e2c:	2823883a 	mov	r17,r5
+ 8008e30:	3025883a 	mov	r18,r6
+ 8008e34:	9d000516 	blt	r19,r20,8008e4c <__multiply+0x44>
+ 8008e38:	a007883a 	mov	r3,r20
+ 8008e3c:	2825883a 	mov	r18,r5
+ 8008e40:	9829883a 	mov	r20,r19
+ 8008e44:	3023883a 	mov	r17,r6
+ 8008e48:	1827883a 	mov	r19,r3
+ 8008e4c:	90800217 	ldw	r2,8(r18)
+ 8008e50:	a4e1883a 	add	r16,r20,r19
+ 8008e54:	91400117 	ldw	r5,4(r18)
+ 8008e58:	1400010e 	bge	r2,r16,8008e60 <__multiply+0x58>
+ 8008e5c:	29400044 	addi	r5,r5,1
+ 8008e60:	80089d40 	call	80089d4 <_Balloc>
+ 8008e64:	801290ba 	slli	r9,r16,2
+ 8008e68:	12800504 	addi	r10,r2,20
+ 8008e6c:	5007883a 	mov	r3,r10
+ 8008e70:	5253883a 	add	r9,r10,r9
+ 8008e74:	5240032e 	bgeu	r10,r9,8008e84 <__multiply+0x7c>
+ 8008e78:	18000015 	stw	zero,0(r3)
+ 8008e7c:	18c00104 	addi	r3,r3,4
+ 8008e80:	1a7ffd36 	bltu	r3,r9,8008e78 <__multiply+0x70>
+ 8008e84:	981690ba 	slli	r11,r19,2
+ 8008e88:	a01090ba 	slli	r8,r20,2
+ 8008e8c:	89400504 	addi	r5,r17,20
+ 8008e90:	91800504 	addi	r6,r18,20
+ 8008e94:	2ad7883a 	add	r11,r5,r11
+ 8008e98:	3211883a 	add	r8,r6,r8
+ 8008e9c:	2ac00636 	bltu	r5,r11,8008eb8 <__multiply+0xb0>
+ 8008ea0:	00004106 	br	8008fa8 <__multiply+0x1a0>
+ 8008ea4:	701cd43a 	srli	r14,r14,16
+ 8008ea8:	7000221e 	bne	r14,zero,8008f34 <__multiply+0x12c>
+ 8008eac:	29400104 	addi	r5,r5,4
+ 8008eb0:	52800104 	addi	r10,r10,4
+ 8008eb4:	2ac03c2e 	bgeu	r5,r11,8008fa8 <__multiply+0x1a0>
+ 8008eb8:	2b800017 	ldw	r14,0(r5)
+ 8008ebc:	73ffffcc 	andi	r15,r14,65535
+ 8008ec0:	783ff826 	beq	r15,zero,8008ea4 <__multiply+0x9c>
+ 8008ec4:	501b883a 	mov	r13,r10
+ 8008ec8:	301d883a 	mov	r14,r6
+ 8008ecc:	003f883a 	mov	ra,zero
+ 8008ed0:	71000017 	ldw	r4,0(r14)
+ 8008ed4:	6b000017 	ldw	r12,0(r13)
+ 8008ed8:	6b400104 	addi	r13,r13,4
+ 8008edc:	21ffffcc 	andi	r7,r4,65535
+ 8008ee0:	3bcf383a 	mul	r7,r7,r15
+ 8008ee4:	2006d43a 	srli	r3,r4,16
+ 8008ee8:	613fffcc 	andi	r4,r12,65535
+ 8008eec:	390f883a 	add	r7,r7,r4
+ 8008ef0:	3fcf883a 	add	r7,r7,ra
+ 8008ef4:	1bc7383a 	mul	r3,r3,r15
+ 8008ef8:	6018d43a 	srli	r12,r12,16
+ 8008efc:	3808d43a 	srli	r4,r7,16
+ 8008f00:	39ffffcc 	andi	r7,r7,65535
+ 8008f04:	1b07883a 	add	r3,r3,r12
+ 8008f08:	1907883a 	add	r3,r3,r4
+ 8008f0c:	1808943a 	slli	r4,r3,16
+ 8008f10:	73800104 	addi	r14,r14,4
+ 8008f14:	183ed43a 	srli	ra,r3,16
+ 8008f18:	21ceb03a 	or	r7,r4,r7
+ 8008f1c:	69ffff15 	stw	r7,-4(r13)
+ 8008f20:	723feb36 	bltu	r14,r8,8008ed0 <__multiply+0xc8>
+ 8008f24:	6fc00015 	stw	ra,0(r13)
+ 8008f28:	2b800017 	ldw	r14,0(r5)
+ 8008f2c:	701cd43a 	srli	r14,r14,16
+ 8008f30:	703fde26 	beq	r14,zero,8008eac <__multiply+0xa4>
+ 8008f34:	50c00017 	ldw	r3,0(r10)
+ 8008f38:	501b883a 	mov	r13,r10
+ 8008f3c:	3019883a 	mov	r12,r6
+ 8008f40:	180f883a 	mov	r7,r3
+ 8008f44:	001f883a 	mov	r15,zero
+ 8008f48:	6100000b 	ldhu	r4,0(r12)
+ 8008f4c:	380ed43a 	srli	r7,r7,16
+ 8008f50:	18ffffcc 	andi	r3,r3,65535
+ 8008f54:	2389383a 	mul	r4,r4,r14
+ 8008f58:	6b400104 	addi	r13,r13,4
+ 8008f5c:	63000104 	addi	r12,r12,4
+ 8008f60:	21c9883a 	add	r4,r4,r7
+ 8008f64:	23c9883a 	add	r4,r4,r15
+ 8008f68:	201e943a 	slli	r15,r4,16
+ 8008f6c:	69c00017 	ldw	r7,0(r13)
+ 8008f70:	2008d43a 	srli	r4,r4,16
+ 8008f74:	78c6b03a 	or	r3,r15,r3
+ 8008f78:	68ffff15 	stw	r3,-4(r13)
+ 8008f7c:	60ffff8b 	ldhu	r3,-2(r12)
+ 8008f80:	3bffffcc 	andi	r15,r7,65535
+ 8008f84:	1b87383a 	mul	r3,r3,r14
+ 8008f88:	1bc7883a 	add	r3,r3,r15
+ 8008f8c:	1907883a 	add	r3,r3,r4
+ 8008f90:	181ed43a 	srli	r15,r3,16
+ 8008f94:	623fec36 	bltu	r12,r8,8008f48 <__multiply+0x140>
+ 8008f98:	68c00015 	stw	r3,0(r13)
+ 8008f9c:	29400104 	addi	r5,r5,4
+ 8008fa0:	52800104 	addi	r10,r10,4
+ 8008fa4:	2affc436 	bltu	r5,r11,8008eb8 <__multiply+0xb0>
+ 8008fa8:	0400090e 	bge	zero,r16,8008fd0 <__multiply+0x1c8>
+ 8008fac:	48ffff17 	ldw	r3,-4(r9)
+ 8008fb0:	4a7fff04 	addi	r9,r9,-4
+ 8008fb4:	18000326 	beq	r3,zero,8008fc4 <__multiply+0x1bc>
+ 8008fb8:	00000506 	br	8008fd0 <__multiply+0x1c8>
+ 8008fbc:	48c00017 	ldw	r3,0(r9)
+ 8008fc0:	1800031e 	bne	r3,zero,8008fd0 <__multiply+0x1c8>
+ 8008fc4:	843fffc4 	addi	r16,r16,-1
+ 8008fc8:	4a7fff04 	addi	r9,r9,-4
+ 8008fcc:	803ffb1e 	bne	r16,zero,8008fbc <__multiply+0x1b4>
+ 8008fd0:	14000415 	stw	r16,16(r2)
+ 8008fd4:	dfc00517 	ldw	ra,20(sp)
+ 8008fd8:	dd000417 	ldw	r20,16(sp)
+ 8008fdc:	dcc00317 	ldw	r19,12(sp)
+ 8008fe0:	dc800217 	ldw	r18,8(sp)
+ 8008fe4:	dc400117 	ldw	r17,4(sp)
+ 8008fe8:	dc000017 	ldw	r16,0(sp)
+ 8008fec:	dec00604 	addi	sp,sp,24
+ 8008ff0:	f800283a 	ret
+
+08008ff4 <__pow5mult>:
+ 8008ff4:	defffb04 	addi	sp,sp,-20
+ 8008ff8:	dcc00315 	stw	r19,12(sp)
+ 8008ffc:	dc000015 	stw	r16,0(sp)
+ 8009000:	dfc00415 	stw	ra,16(sp)
+ 8009004:	dc800215 	stw	r18,8(sp)
+ 8009008:	dc400115 	stw	r17,4(sp)
+ 800900c:	308000cc 	andi	r2,r6,3
+ 8009010:	3021883a 	mov	r16,r6
+ 8009014:	2027883a 	mov	r19,r4
+ 8009018:	10002d1e 	bne	r2,zero,80090d0 <__pow5mult+0xdc>
+ 800901c:	2825883a 	mov	r18,r5
+ 8009020:	8021d0ba 	srai	r16,r16,2
+ 8009024:	80001926 	beq	r16,zero,800908c <__pow5mult+0x98>
+ 8009028:	9c401217 	ldw	r17,72(r19)
+ 800902c:	8800061e 	bne	r17,zero,8009048 <__pow5mult+0x54>
+ 8009030:	00002f06 	br	80090f0 <__pow5mult+0xfc>
+ 8009034:	8021d07a 	srai	r16,r16,1
+ 8009038:	80001426 	beq	r16,zero,800908c <__pow5mult+0x98>
+ 800903c:	88800017 	ldw	r2,0(r17)
+ 8009040:	10001a26 	beq	r2,zero,80090ac <__pow5mult+0xb8>
+ 8009044:	1023883a 	mov	r17,r2
+ 8009048:	8080004c 	andi	r2,r16,1
+ 800904c:	103ff926 	beq	r2,zero,8009034 <__pow5mult+0x40>
+ 8009050:	880d883a 	mov	r6,r17
+ 8009054:	900b883a 	mov	r5,r18
+ 8009058:	9809883a 	mov	r4,r19
+ 800905c:	8008e080 	call	8008e08 <__multiply>
+ 8009060:	90001926 	beq	r18,zero,80090c8 <__pow5mult+0xd4>
+ 8009064:	91000117 	ldw	r4,4(r18)
+ 8009068:	98c01317 	ldw	r3,76(r19)
+ 800906c:	8021d07a 	srai	r16,r16,1
+ 8009070:	200890ba 	slli	r4,r4,2
+ 8009074:	1907883a 	add	r3,r3,r4
+ 8009078:	19000017 	ldw	r4,0(r3)
+ 800907c:	91000015 	stw	r4,0(r18)
+ 8009080:	1c800015 	stw	r18,0(r3)
+ 8009084:	1025883a 	mov	r18,r2
+ 8009088:	803fec1e 	bne	r16,zero,800903c <__pow5mult+0x48>
+ 800908c:	9005883a 	mov	r2,r18
+ 8009090:	dfc00417 	ldw	ra,16(sp)
+ 8009094:	dcc00317 	ldw	r19,12(sp)
+ 8009098:	dc800217 	ldw	r18,8(sp)
+ 800909c:	dc400117 	ldw	r17,4(sp)
+ 80090a0:	dc000017 	ldw	r16,0(sp)
+ 80090a4:	dec00504 	addi	sp,sp,20
+ 80090a8:	f800283a 	ret
+ 80090ac:	880d883a 	mov	r6,r17
+ 80090b0:	880b883a 	mov	r5,r17
+ 80090b4:	9809883a 	mov	r4,r19
+ 80090b8:	8008e080 	call	8008e08 <__multiply>
+ 80090bc:	88800015 	stw	r2,0(r17)
+ 80090c0:	10000015 	stw	zero,0(r2)
+ 80090c4:	003fdf06 	br	8009044 <__pow5mult+0x50>
+ 80090c8:	1025883a 	mov	r18,r2
+ 80090cc:	003fd906 	br	8009034 <__pow5mult+0x40>
+ 80090d0:	100490ba 	slli	r2,r2,2
+ 80090d4:	00c20134 	movhi	r3,2052
+ 80090d8:	000f883a 	mov	r7,zero
+ 80090dc:	10c7883a 	add	r3,r2,r3
+ 80090e0:	199d3317 	ldw	r6,29900(r3)
+ 80090e4:	8008a9c0 	call	8008a9c <__multadd>
+ 80090e8:	1025883a 	mov	r18,r2
+ 80090ec:	003fcc06 	br	8009020 <__pow5mult+0x2c>
+ 80090f0:	01400044 	movi	r5,1
+ 80090f4:	9809883a 	mov	r4,r19
+ 80090f8:	80089d40 	call	80089d4 <_Balloc>
+ 80090fc:	1023883a 	mov	r17,r2
+ 8009100:	00809c44 	movi	r2,625
+ 8009104:	88800515 	stw	r2,20(r17)
+ 8009108:	00800044 	movi	r2,1
+ 800910c:	88800415 	stw	r2,16(r17)
+ 8009110:	9c401215 	stw	r17,72(r19)
+ 8009114:	88000015 	stw	zero,0(r17)
+ 8009118:	003fcb06 	br	8009048 <__pow5mult+0x54>
+
+0800911c <__lshift>:
+ 800911c:	defff904 	addi	sp,sp,-28
+ 8009120:	dcc00315 	stw	r19,12(sp)
+ 8009124:	dc400115 	stw	r17,4(sp)
+ 8009128:	2cc00417 	ldw	r19,16(r5)
+ 800912c:	3023d17a 	srai	r17,r6,5
+ 8009130:	28800217 	ldw	r2,8(r5)
+ 8009134:	dd400515 	stw	r21,20(sp)
+ 8009138:	8ce7883a 	add	r19,r17,r19
+ 800913c:	dd000415 	stw	r20,16(sp)
+ 8009140:	dc800215 	stw	r18,8(sp)
+ 8009144:	dc000015 	stw	r16,0(sp)
+ 8009148:	dfc00615 	stw	ra,24(sp)
+ 800914c:	9c000044 	addi	r16,r19,1
+ 8009150:	2825883a 	mov	r18,r5
+ 8009154:	302b883a 	mov	r21,r6
+ 8009158:	2029883a 	mov	r20,r4
+ 800915c:	29400117 	ldw	r5,4(r5)
+ 8009160:	1400030e 	bge	r2,r16,8009170 <__lshift+0x54>
+ 8009164:	1085883a 	add	r2,r2,r2
+ 8009168:	29400044 	addi	r5,r5,1
+ 800916c:	143ffd16 	blt	r2,r16,8009164 <__lshift+0x48>
+ 8009170:	a009883a 	mov	r4,r20
+ 8009174:	80089d40 	call	80089d4 <_Balloc>
+ 8009178:	11000504 	addi	r4,r2,20
+ 800917c:	0440090e 	bge	zero,r17,80091a4 <__lshift+0x88>
+ 8009180:	8c400144 	addi	r17,r17,5
+ 8009184:	882290ba 	slli	r17,r17,2
+ 8009188:	2007883a 	mov	r3,r4
+ 800918c:	144b883a 	add	r5,r2,r17
+ 8009190:	18c00104 	addi	r3,r3,4
+ 8009194:	183fff15 	stw	zero,-4(r3)
+ 8009198:	28fffd1e 	bne	r5,r3,8009190 <__lshift+0x74>
+ 800919c:	8c7ffb04 	addi	r17,r17,-20
+ 80091a0:	2449883a 	add	r4,r4,r17
+ 80091a4:	92000417 	ldw	r8,16(r18)
+ 80091a8:	90c00504 	addi	r3,r18,20
+ 80091ac:	a98007cc 	andi	r6,r21,31
+ 80091b0:	401090ba 	slli	r8,r8,2
+ 80091b4:	1a11883a 	add	r8,r3,r8
+ 80091b8:	30002126 	beq	r6,zero,8009240 <__lshift+0x124>
+ 80091bc:	02400804 	movi	r9,32
+ 80091c0:	4993c83a 	sub	r9,r9,r6
+ 80091c4:	000f883a 	mov	r7,zero
+ 80091c8:	19400017 	ldw	r5,0(r3)
+ 80091cc:	21000104 	addi	r4,r4,4
+ 80091d0:	18c00104 	addi	r3,r3,4
+ 80091d4:	298a983a 	sll	r5,r5,r6
+ 80091d8:	29cab03a 	or	r5,r5,r7
+ 80091dc:	217fff15 	stw	r5,-4(r4)
+ 80091e0:	197fff17 	ldw	r5,-4(r3)
+ 80091e4:	2a4ed83a 	srl	r7,r5,r9
+ 80091e8:	1a3ff736 	bltu	r3,r8,80091c8 <__lshift+0xac>
+ 80091ec:	21c00015 	stw	r7,0(r4)
+ 80091f0:	38000126 	beq	r7,zero,80091f8 <__lshift+0xdc>
+ 80091f4:	8027883a 	mov	r19,r16
+ 80091f8:	14c00415 	stw	r19,16(r2)
+ 80091fc:	90000726 	beq	r18,zero,800921c <__lshift+0x100>
+ 8009200:	91000117 	ldw	r4,4(r18)
+ 8009204:	a0c01317 	ldw	r3,76(r20)
+ 8009208:	200890ba 	slli	r4,r4,2
+ 800920c:	1907883a 	add	r3,r3,r4
+ 8009210:	19000017 	ldw	r4,0(r3)
+ 8009214:	91000015 	stw	r4,0(r18)
+ 8009218:	1c800015 	stw	r18,0(r3)
+ 800921c:	dfc00617 	ldw	ra,24(sp)
+ 8009220:	dd400517 	ldw	r21,20(sp)
+ 8009224:	dd000417 	ldw	r20,16(sp)
+ 8009228:	dcc00317 	ldw	r19,12(sp)
+ 800922c:	dc800217 	ldw	r18,8(sp)
+ 8009230:	dc400117 	ldw	r17,4(sp)
+ 8009234:	dc000017 	ldw	r16,0(sp)
+ 8009238:	dec00704 	addi	sp,sp,28
+ 800923c:	f800283a 	ret
+ 8009240:	18c00104 	addi	r3,r3,4
+ 8009244:	197fff17 	ldw	r5,-4(r3)
+ 8009248:	21000104 	addi	r4,r4,4
+ 800924c:	217fff15 	stw	r5,-4(r4)
+ 8009250:	1a3ffb36 	bltu	r3,r8,8009240 <__lshift+0x124>
+ 8009254:	003fe806 	br	80091f8 <__lshift+0xdc>
+
+08009258 <__mcmp>:
+ 8009258:	20800417 	ldw	r2,16(r4)
+ 800925c:	28c00417 	ldw	r3,16(r5)
+ 8009260:	10c5c83a 	sub	r2,r2,r3
+ 8009264:	10000e1e 	bne	r2,zero,80092a0 <__mcmp+0x48>
+ 8009268:	180c90ba 	slli	r6,r3,2
+ 800926c:	21000504 	addi	r4,r4,20
+ 8009270:	29400504 	addi	r5,r5,20
+ 8009274:	2187883a 	add	r3,r4,r6
+ 8009278:	298b883a 	add	r5,r5,r6
+ 800927c:	00000106 	br	8009284 <__mcmp+0x2c>
+ 8009280:	20c0082e 	bgeu	r4,r3,80092a4 <__mcmp+0x4c>
+ 8009284:	18ffff04 	addi	r3,r3,-4
+ 8009288:	297fff04 	addi	r5,r5,-4
+ 800928c:	19c00017 	ldw	r7,0(r3)
+ 8009290:	29800017 	ldw	r6,0(r5)
+ 8009294:	39bffa26 	beq	r7,r6,8009280 <__mcmp+0x28>
+ 8009298:	3980032e 	bgeu	r7,r6,80092a8 <__mcmp+0x50>
+ 800929c:	00bfffc4 	movi	r2,-1
+ 80092a0:	f800283a 	ret
+ 80092a4:	f800283a 	ret
+ 80092a8:	00800044 	movi	r2,1
+ 80092ac:	f800283a 	ret
+
+080092b0 <__mdiff>:
+ 80092b0:	defffa04 	addi	sp,sp,-24
+ 80092b4:	dc800215 	stw	r18,8(sp)
+ 80092b8:	30c00417 	ldw	r3,16(r6)
+ 80092bc:	2c800417 	ldw	r18,16(r5)
+ 80092c0:	dd000415 	stw	r20,16(sp)
+ 80092c4:	dcc00315 	stw	r19,12(sp)
+ 80092c8:	dc400115 	stw	r17,4(sp)
+ 80092cc:	dc000015 	stw	r16,0(sp)
+ 80092d0:	dfc00515 	stw	ra,20(sp)
+ 80092d4:	90e5c83a 	sub	r18,r18,r3
+ 80092d8:	2827883a 	mov	r19,r5
+ 80092dc:	3029883a 	mov	r20,r6
+ 80092e0:	2c000504 	addi	r16,r5,20
+ 80092e4:	34400504 	addi	r17,r6,20
+ 80092e8:	9000131e 	bne	r18,zero,8009338 <__mdiff+0x88>
+ 80092ec:	180690ba 	slli	r3,r3,2
+ 80092f0:	80c5883a 	add	r2,r16,r3
+ 80092f4:	88c7883a 	add	r3,r17,r3
+ 80092f8:	00000106 	br	8009300 <__mdiff+0x50>
+ 80092fc:	8080552e 	bgeu	r16,r2,8009454 <__mdiff+0x1a4>
+ 8009300:	10bfff04 	addi	r2,r2,-4
+ 8009304:	18ffff04 	addi	r3,r3,-4
+ 8009308:	11c00017 	ldw	r7,0(r2)
+ 800930c:	19400017 	ldw	r5,0(r3)
+ 8009310:	397ffa26 	beq	r7,r5,80092fc <__mdiff+0x4c>
+ 8009314:	39400a2e 	bgeu	r7,r5,8009340 <__mdiff+0x90>
+ 8009318:	8007883a 	mov	r3,r16
+ 800931c:	9805883a 	mov	r2,r19
+ 8009320:	8821883a 	mov	r16,r17
+ 8009324:	a027883a 	mov	r19,r20
+ 8009328:	1823883a 	mov	r17,r3
+ 800932c:	1029883a 	mov	r20,r2
+ 8009330:	04800044 	movi	r18,1
+ 8009334:	00000206 	br	8009340 <__mdiff+0x90>
+ 8009338:	903ff716 	blt	r18,zero,8009318 <__mdiff+0x68>
+ 800933c:	0025883a 	mov	r18,zero
+ 8009340:	99400117 	ldw	r5,4(r19)
+ 8009344:	80089d40 	call	80089d4 <_Balloc>
+ 8009348:	9a400417 	ldw	r9,16(r19)
+ 800934c:	a2c00417 	ldw	r11,16(r20)
+ 8009350:	12800504 	addi	r10,r2,20
+ 8009354:	481090ba 	slli	r8,r9,2
+ 8009358:	581690ba 	slli	r11,r11,2
+ 800935c:	14800315 	stw	r18,12(r2)
+ 8009360:	8211883a 	add	r8,r16,r8
+ 8009364:	8ad7883a 	add	r11,r17,r11
+ 8009368:	0007883a 	mov	r3,zero
+ 800936c:	00000106 	br	8009374 <__mdiff+0xc4>
+ 8009370:	3815883a 	mov	r10,r7
+ 8009374:	81000017 	ldw	r4,0(r16)
+ 8009378:	89800017 	ldw	r6,0(r17)
+ 800937c:	51c00104 	addi	r7,r10,4
+ 8009380:	217fffcc 	andi	r5,r4,65535
+ 8009384:	28cb883a 	add	r5,r5,r3
+ 8009388:	30ffffcc 	andi	r3,r6,65535
+ 800938c:	28cbc83a 	sub	r5,r5,r3
+ 8009390:	300cd43a 	srli	r6,r6,16
+ 8009394:	2006d43a 	srli	r3,r4,16
+ 8009398:	2809d43a 	srai	r4,r5,16
+ 800939c:	297fffcc 	andi	r5,r5,65535
+ 80093a0:	1987c83a 	sub	r3,r3,r6
+ 80093a4:	1907883a 	add	r3,r3,r4
+ 80093a8:	1808943a 	slli	r4,r3,16
+ 80093ac:	8c400104 	addi	r17,r17,4
+ 80093b0:	84000104 	addi	r16,r16,4
+ 80093b4:	214ab03a 	or	r5,r4,r5
+ 80093b8:	397fff15 	stw	r5,-4(r7)
+ 80093bc:	1807d43a 	srai	r3,r3,16
+ 80093c0:	8affeb36 	bltu	r17,r11,8009370 <__mdiff+0xc0>
+ 80093c4:	8200152e 	bgeu	r16,r8,800941c <__mdiff+0x16c>
+ 80093c8:	3815883a 	mov	r10,r7
+ 80093cc:	800d883a 	mov	r6,r16
+ 80093d0:	31000017 	ldw	r4,0(r6)
+ 80093d4:	52800104 	addi	r10,r10,4
+ 80093d8:	31800104 	addi	r6,r6,4
+ 80093dc:	217fffcc 	andi	r5,r4,65535
+ 80093e0:	28cb883a 	add	r5,r5,r3
+ 80093e4:	2817d43a 	srai	r11,r5,16
+ 80093e8:	2006d43a 	srli	r3,r4,16
+ 80093ec:	293fffcc 	andi	r4,r5,65535
+ 80093f0:	1ac7883a 	add	r3,r3,r11
+ 80093f4:	180a943a 	slli	r5,r3,16
+ 80093f8:	1807d43a 	srai	r3,r3,16
+ 80093fc:	290ab03a 	or	r5,r5,r4
+ 8009400:	517fff15 	stw	r5,-4(r10)
+ 8009404:	323ff236 	bltu	r6,r8,80093d0 <__mdiff+0x120>
+ 8009408:	42bfffc4 	addi	r10,r8,-1
+ 800940c:	5415c83a 	sub	r10,r10,r16
+ 8009410:	5014d0ba 	srli	r10,r10,2
+ 8009414:	501490ba 	slli	r10,r10,2
+ 8009418:	3a95883a 	add	r10,r7,r10
+ 800941c:	2800041e 	bne	r5,zero,8009430 <__mdiff+0x180>
+ 8009420:	52bfff04 	addi	r10,r10,-4
+ 8009424:	50c00017 	ldw	r3,0(r10)
+ 8009428:	4a7fffc4 	addi	r9,r9,-1
+ 800942c:	183ffc26 	beq	r3,zero,8009420 <__mdiff+0x170>
+ 8009430:	12400415 	stw	r9,16(r2)
+ 8009434:	dfc00517 	ldw	ra,20(sp)
+ 8009438:	dd000417 	ldw	r20,16(sp)
+ 800943c:	dcc00317 	ldw	r19,12(sp)
+ 8009440:	dc800217 	ldw	r18,8(sp)
+ 8009444:	dc400117 	ldw	r17,4(sp)
+ 8009448:	dc000017 	ldw	r16,0(sp)
+ 800944c:	dec00604 	addi	sp,sp,24
+ 8009450:	f800283a 	ret
+ 8009454:	000b883a 	mov	r5,zero
+ 8009458:	80089d40 	call	80089d4 <_Balloc>
+ 800945c:	00c00044 	movi	r3,1
+ 8009460:	10c00415 	stw	r3,16(r2)
+ 8009464:	10000515 	stw	zero,20(r2)
+ 8009468:	003ff206 	br	8009434 <__mdiff+0x184>
+
+0800946c <__ulp>:
+ 800946c:	295ffc2c 	andhi	r5,r5,32752
+ 8009470:	00ff3034 	movhi	r3,64704
+ 8009474:	28c7883a 	add	r3,r5,r3
+ 8009478:	00c0020e 	bge	zero,r3,8009484 <__ulp+0x18>
+ 800947c:	0005883a 	mov	r2,zero
+ 8009480:	f800283a 	ret
+ 8009484:	00c7c83a 	sub	r3,zero,r3
+ 8009488:	1807d53a 	srai	r3,r3,20
+ 800948c:	18800508 	cmpgei	r2,r3,20
+ 8009490:	1000041e 	bne	r2,zero,80094a4 <__ulp+0x38>
+ 8009494:	01400234 	movhi	r5,8
+ 8009498:	28c7d83a 	sra	r3,r5,r3
+ 800949c:	0005883a 	mov	r2,zero
+ 80094a0:	f800283a 	ret
+ 80094a4:	193ffb04 	addi	r4,r3,-20
+ 80094a8:	208007c8 	cmpgei	r2,r4,31
+ 80094ac:	0007883a 	mov	r3,zero
+ 80094b0:	1000031e 	bne	r2,zero,80094c0 <__ulp+0x54>
+ 80094b4:	00a00034 	movhi	r2,32768
+ 80094b8:	1104d83a 	srl	r2,r2,r4
+ 80094bc:	f800283a 	ret
+ 80094c0:	00800044 	movi	r2,1
+ 80094c4:	f800283a 	ret
+
+080094c8 <__b2d>:
+ 80094c8:	defffa04 	addi	sp,sp,-24
+ 80094cc:	dc000015 	stw	r16,0(sp)
+ 80094d0:	24000417 	ldw	r16,16(r4)
+ 80094d4:	dc800215 	stw	r18,8(sp)
+ 80094d8:	24800504 	addi	r18,r4,20
+ 80094dc:	802090ba 	slli	r16,r16,2
+ 80094e0:	dc400115 	stw	r17,4(sp)
+ 80094e4:	dd000415 	stw	r20,16(sp)
+ 80094e8:	9421883a 	add	r16,r18,r16
+ 80094ec:	847fff17 	ldw	r17,-4(r16)
+ 80094f0:	dcc00315 	stw	r19,12(sp)
+ 80094f4:	2829883a 	mov	r20,r5
+ 80094f8:	8809883a 	mov	r4,r17
+ 80094fc:	dfc00515 	stw	ra,20(sp)
+ 8009500:	8008cc00 	call	8008cc0 <__hi0bits>
+ 8009504:	01000804 	movi	r4,32
+ 8009508:	2087c83a 	sub	r3,r4,r2
+ 800950c:	a0c00015 	stw	r3,0(r20)
+ 8009510:	10c002c8 	cmpgei	r3,r2,11
+ 8009514:	84ffff04 	addi	r19,r16,-4
+ 8009518:	18001f26 	beq	r3,zero,8009598 <__b2d+0xd0>
+ 800951c:	10fffd44 	addi	r3,r2,-11
+ 8009520:	94c00e2e 	bgeu	r18,r19,800955c <__b2d+0x94>
+ 8009524:	80bffe17 	ldw	r2,-8(r16)
+ 8009528:	18001226 	beq	r3,zero,8009574 <__b2d+0xac>
+ 800952c:	20c9c83a 	sub	r4,r4,r3
+ 8009530:	110cd83a 	srl	r6,r2,r4
+ 8009534:	88e2983a 	sll	r17,r17,r3
+ 8009538:	10c4983a 	sll	r2,r2,r3
+ 800953c:	817ffe04 	addi	r5,r16,-8
+ 8009540:	8986b03a 	or	r3,r17,r6
+ 8009544:	18cffc34 	orhi	r3,r3,16368
+ 8009548:	91400b2e 	bgeu	r18,r5,8009578 <__b2d+0xb0>
+ 800954c:	817ffd17 	ldw	r5,-12(r16)
+ 8009550:	2908d83a 	srl	r4,r5,r4
+ 8009554:	1104b03a 	or	r2,r2,r4
+ 8009558:	00000706 	br	8009578 <__b2d+0xb0>
+ 800955c:	18000426 	beq	r3,zero,8009570 <__b2d+0xa8>
+ 8009560:	88c6983a 	sll	r3,r17,r3
+ 8009564:	0005883a 	mov	r2,zero
+ 8009568:	18cffc34 	orhi	r3,r3,16368
+ 800956c:	00000206 	br	8009578 <__b2d+0xb0>
+ 8009570:	0005883a 	mov	r2,zero
+ 8009574:	88cffc34 	orhi	r3,r17,16368
+ 8009578:	dfc00517 	ldw	ra,20(sp)
+ 800957c:	dd000417 	ldw	r20,16(sp)
+ 8009580:	dcc00317 	ldw	r19,12(sp)
+ 8009584:	dc800217 	ldw	r18,8(sp)
+ 8009588:	dc400117 	ldw	r17,4(sp)
+ 800958c:	dc000017 	ldw	r16,0(sp)
+ 8009590:	dec00604 	addi	sp,sp,24
+ 8009594:	f800283a 	ret
+ 8009598:	014002c4 	movi	r5,11
+ 800959c:	2889c83a 	sub	r4,r5,r2
+ 80095a0:	8906d83a 	srl	r3,r17,r4
+ 80095a4:	18cffc34 	orhi	r3,r3,16368
+ 80095a8:	94c00536 	bltu	r18,r19,80095c0 <__b2d+0xf8>
+ 80095ac:	000b883a 	mov	r5,zero
+ 80095b0:	10800544 	addi	r2,r2,21
+ 80095b4:	8884983a 	sll	r2,r17,r2
+ 80095b8:	1144b03a 	or	r2,r2,r5
+ 80095bc:	003fee06 	br	8009578 <__b2d+0xb0>
+ 80095c0:	817ffe17 	ldw	r5,-8(r16)
+ 80095c4:	290ad83a 	srl	r5,r5,r4
+ 80095c8:	003ff906 	br	80095b0 <__b2d+0xe8>
+
+080095cc <__d2b>:
+ 80095cc:	defff804 	addi	sp,sp,-32
+ 80095d0:	dc400315 	stw	r17,12(sp)
+ 80095d4:	3023883a 	mov	r17,r6
+ 80095d8:	dd000615 	stw	r20,24(sp)
+ 80095dc:	dc000215 	stw	r16,8(sp)
+ 80095e0:	2829883a 	mov	r20,r5
+ 80095e4:	8820d53a 	srli	r16,r17,20
+ 80095e8:	01400044 	movi	r5,1
+ 80095ec:	dcc00515 	stw	r19,20(sp)
+ 80095f0:	dc800415 	stw	r18,16(sp)
+ 80095f4:	dfc00715 	stw	ra,28(sp)
+ 80095f8:	3825883a 	mov	r18,r7
+ 80095fc:	80089d40 	call	80089d4 <_Balloc>
+ 8009600:	01800434 	movhi	r6,16
+ 8009604:	31bfffc4 	addi	r6,r6,-1
+ 8009608:	8401ffcc 	andi	r16,r16,2047
+ 800960c:	1027883a 	mov	r19,r2
+ 8009610:	89a2703a 	and	r17,r17,r6
+ 8009614:	80000126 	beq	r16,zero,800961c <__d2b+0x50>
+ 8009618:	8c400434 	orhi	r17,r17,16
+ 800961c:	dc400115 	stw	r17,4(sp)
+ 8009620:	a0002826 	beq	r20,zero,80096c4 <__d2b+0xf8>
+ 8009624:	d809883a 	mov	r4,sp
+ 8009628:	dd000015 	stw	r20,0(sp)
+ 800962c:	8008d240 	call	8008d24 <__lo0bits>
+ 8009630:	d8c00117 	ldw	r3,4(sp)
+ 8009634:	1000171e 	bne	r2,zero,8009694 <__d2b+0xc8>
+ 8009638:	d9000017 	ldw	r4,0(sp)
+ 800963c:	98c00615 	stw	r3,24(r19)
+ 8009640:	99000515 	stw	r4,20(r19)
+ 8009644:	18001d1e 	bne	r3,zero,80096bc <__d2b+0xf0>
+ 8009648:	04400044 	movi	r17,1
+ 800964c:	9c400415 	stw	r17,16(r19)
+ 8009650:	80002526 	beq	r16,zero,80096e8 <__d2b+0x11c>
+ 8009654:	00c00d44 	movi	r3,53
+ 8009658:	843ef344 	addi	r16,r16,-1075
+ 800965c:	80a1883a 	add	r16,r16,r2
+ 8009660:	1885c83a 	sub	r2,r3,r2
+ 8009664:	d8c00817 	ldw	r3,32(sp)
+ 8009668:	94000015 	stw	r16,0(r18)
+ 800966c:	18800015 	stw	r2,0(r3)
+ 8009670:	9805883a 	mov	r2,r19
+ 8009674:	dfc00717 	ldw	ra,28(sp)
+ 8009678:	dd000617 	ldw	r20,24(sp)
+ 800967c:	dcc00517 	ldw	r19,20(sp)
+ 8009680:	dc800417 	ldw	r18,16(sp)
+ 8009684:	dc400317 	ldw	r17,12(sp)
+ 8009688:	dc000217 	ldw	r16,8(sp)
+ 800968c:	dec00804 	addi	sp,sp,32
+ 8009690:	f800283a 	ret
+ 8009694:	01000804 	movi	r4,32
+ 8009698:	2089c83a 	sub	r4,r4,r2
+ 800969c:	1908983a 	sll	r4,r3,r4
+ 80096a0:	d9400017 	ldw	r5,0(sp)
+ 80096a4:	1886d83a 	srl	r3,r3,r2
+ 80096a8:	2148b03a 	or	r4,r4,r5
+ 80096ac:	99000515 	stw	r4,20(r19)
+ 80096b0:	d8c00115 	stw	r3,4(sp)
+ 80096b4:	98c00615 	stw	r3,24(r19)
+ 80096b8:	183fe326 	beq	r3,zero,8009648 <__d2b+0x7c>
+ 80096bc:	04400084 	movi	r17,2
+ 80096c0:	003fe206 	br	800964c <__d2b+0x80>
+ 80096c4:	d9000104 	addi	r4,sp,4
+ 80096c8:	8008d240 	call	8008d24 <__lo0bits>
+ 80096cc:	00c00044 	movi	r3,1
+ 80096d0:	98c00415 	stw	r3,16(r19)
+ 80096d4:	d8c00117 	ldw	r3,4(sp)
+ 80096d8:	10800804 	addi	r2,r2,32
+ 80096dc:	04400044 	movi	r17,1
+ 80096e0:	98c00515 	stw	r3,20(r19)
+ 80096e4:	803fdb1e 	bne	r16,zero,8009654 <__d2b+0x88>
+ 80096e8:	880690ba 	slli	r3,r17,2
+ 80096ec:	10bef384 	addi	r2,r2,-1074
+ 80096f0:	8822917a 	slli	r17,r17,5
+ 80096f4:	98c7883a 	add	r3,r19,r3
+ 80096f8:	19000417 	ldw	r4,16(r3)
+ 80096fc:	90800015 	stw	r2,0(r18)
+ 8009700:	8008cc00 	call	8008cc0 <__hi0bits>
+ 8009704:	88a3c83a 	sub	r17,r17,r2
+ 8009708:	d8800817 	ldw	r2,32(sp)
+ 800970c:	14400015 	stw	r17,0(r2)
+ 8009710:	003fd706 	br	8009670 <__d2b+0xa4>
+
+08009714 <__ratio>:
+ 8009714:	defff904 	addi	sp,sp,-28
+ 8009718:	dc400315 	stw	r17,12(sp)
+ 800971c:	2823883a 	mov	r17,r5
+ 8009720:	d80b883a 	mov	r5,sp
+ 8009724:	dfc00615 	stw	ra,24(sp)
+ 8009728:	dcc00515 	stw	r19,20(sp)
+ 800972c:	dc800415 	stw	r18,16(sp)
+ 8009730:	2027883a 	mov	r19,r4
+ 8009734:	dc000215 	stw	r16,8(sp)
+ 8009738:	80094c80 	call	80094c8 <__b2d>
+ 800973c:	d9400104 	addi	r5,sp,4
+ 8009740:	8809883a 	mov	r4,r17
+ 8009744:	1025883a 	mov	r18,r2
+ 8009748:	1821883a 	mov	r16,r3
+ 800974c:	80094c80 	call	80094c8 <__b2d>
+ 8009750:	89400417 	ldw	r5,16(r17)
+ 8009754:	99000417 	ldw	r4,16(r19)
+ 8009758:	d9800117 	ldw	r6,4(sp)
+ 800975c:	2149c83a 	sub	r4,r4,r5
+ 8009760:	d9400017 	ldw	r5,0(sp)
+ 8009764:	2008917a 	slli	r4,r4,5
+ 8009768:	298bc83a 	sub	r5,r5,r6
+ 800976c:	2149883a 	add	r4,r4,r5
+ 8009770:	01000e0e 	bge	zero,r4,80097ac <__ratio+0x98>
+ 8009774:	2008953a 	slli	r4,r4,20
+ 8009778:	2421883a 	add	r16,r4,r16
+ 800977c:	100d883a 	mov	r6,r2
+ 8009780:	180f883a 	mov	r7,r3
+ 8009784:	9009883a 	mov	r4,r18
+ 8009788:	800b883a 	mov	r5,r16
+ 800978c:	800da580 	call	800da58 <__divdf3>
+ 8009790:	dfc00617 	ldw	ra,24(sp)
+ 8009794:	dcc00517 	ldw	r19,20(sp)
+ 8009798:	dc800417 	ldw	r18,16(sp)
+ 800979c:	dc400317 	ldw	r17,12(sp)
+ 80097a0:	dc000217 	ldw	r16,8(sp)
+ 80097a4:	dec00704 	addi	sp,sp,28
+ 80097a8:	f800283a 	ret
+ 80097ac:	017ffc34 	movhi	r5,65520
+ 80097b0:	2149383a 	mul	r4,r4,r5
+ 80097b4:	20c7883a 	add	r3,r4,r3
+ 80097b8:	003ff006 	br	800977c <__ratio+0x68>
+
+080097bc <_mprec_log10>:
+ 80097bc:	defffe04 	addi	sp,sp,-8
+ 80097c0:	dc000015 	stw	r16,0(sp)
+ 80097c4:	dfc00115 	stw	ra,4(sp)
+ 80097c8:	20800608 	cmpgei	r2,r4,24
+ 80097cc:	2021883a 	mov	r16,r4
+ 80097d0:	10000d26 	beq	r2,zero,8009808 <_mprec_log10+0x4c>
+ 80097d4:	0005883a 	mov	r2,zero
+ 80097d8:	00cffc34 	movhi	r3,16368
+ 80097dc:	843fffc4 	addi	r16,r16,-1
+ 80097e0:	000d883a 	mov	r6,zero
+ 80097e4:	01d00934 	movhi	r7,16420
+ 80097e8:	1009883a 	mov	r4,r2
+ 80097ec:	180b883a 	mov	r5,r3
+ 80097f0:	800e5600 	call	800e560 <__muldf3>
+ 80097f4:	803ff91e 	bne	r16,zero,80097dc <_mprec_log10+0x20>
+ 80097f8:	dfc00117 	ldw	ra,4(sp)
+ 80097fc:	dc000017 	ldw	r16,0(sp)
+ 8009800:	dec00204 	addi	sp,sp,8
+ 8009804:	f800283a 	ret
+ 8009808:	202090fa 	slli	r16,r4,3
+ 800980c:	00820134 	movhi	r2,2052
+ 8009810:	109d4b04 	addi	r2,r2,29996
+ 8009814:	1421883a 	add	r16,r2,r16
+ 8009818:	80800017 	ldw	r2,0(r16)
+ 800981c:	80c00117 	ldw	r3,4(r16)
+ 8009820:	dfc00117 	ldw	ra,4(sp)
+ 8009824:	dc000017 	ldw	r16,0(sp)
+ 8009828:	dec00204 	addi	sp,sp,8
+ 800982c:	f800283a 	ret
+
+08009830 <__copybits>:
+ 8009830:	29ffffc4 	addi	r7,r5,-1
+ 8009834:	380fd17a 	srai	r7,r7,5
+ 8009838:	31400417 	ldw	r5,16(r6)
+ 800983c:	30800504 	addi	r2,r6,20
+ 8009840:	39c00044 	addi	r7,r7,1
+ 8009844:	280a90ba 	slli	r5,r5,2
+ 8009848:	380e90ba 	slli	r7,r7,2
+ 800984c:	114b883a 	add	r5,r2,r5
+ 8009850:	21cf883a 	add	r7,r4,r7
+ 8009854:	11400c2e 	bgeu	r2,r5,8009888 <__copybits+0x58>
+ 8009858:	2007883a 	mov	r3,r4
+ 800985c:	10800104 	addi	r2,r2,4
+ 8009860:	123fff17 	ldw	r8,-4(r2)
+ 8009864:	18c00104 	addi	r3,r3,4
+ 8009868:	1a3fff15 	stw	r8,-4(r3)
+ 800986c:	117ffb36 	bltu	r2,r5,800985c <__copybits+0x2c>
+ 8009870:	2985c83a 	sub	r2,r5,r6
+ 8009874:	10bffac4 	addi	r2,r2,-21
+ 8009878:	1004d0ba 	srli	r2,r2,2
+ 800987c:	10800044 	addi	r2,r2,1
+ 8009880:	100490ba 	slli	r2,r2,2
+ 8009884:	2089883a 	add	r4,r4,r2
+ 8009888:	21c0032e 	bgeu	r4,r7,8009898 <__copybits+0x68>
+ 800988c:	21000104 	addi	r4,r4,4
+ 8009890:	203fff15 	stw	zero,-4(r4)
+ 8009894:	21fffd36 	bltu	r4,r7,800988c <__copybits+0x5c>
+ 8009898:	f800283a 	ret
+
+0800989c <__any_on>:
+ 800989c:	20800417 	ldw	r2,16(r4)
+ 80098a0:	280dd17a 	srai	r6,r5,5
+ 80098a4:	21000504 	addi	r4,r4,20
+ 80098a8:	11800c0e 	bge	r2,r6,80098dc <__any_on+0x40>
+ 80098ac:	100690ba 	slli	r3,r2,2
+ 80098b0:	20c7883a 	add	r3,r4,r3
+ 80098b4:	20c0142e 	bgeu	r4,r3,8009908 <__any_on+0x6c>
+ 80098b8:	18bfff17 	ldw	r2,-4(r3)
+ 80098bc:	18ffff04 	addi	r3,r3,-4
+ 80098c0:	1000041e 	bne	r2,zero,80098d4 <__any_on+0x38>
+ 80098c4:	20c00f2e 	bgeu	r4,r3,8009904 <__any_on+0x68>
+ 80098c8:	18ffff04 	addi	r3,r3,-4
+ 80098cc:	19400017 	ldw	r5,0(r3)
+ 80098d0:	283ffc26 	beq	r5,zero,80098c4 <__any_on+0x28>
+ 80098d4:	00800044 	movi	r2,1
+ 80098d8:	f800283a 	ret
+ 80098dc:	300690ba 	slli	r3,r6,2
+ 80098e0:	20c7883a 	add	r3,r4,r3
+ 80098e4:	30bff30e 	bge	r6,r2,80098b4 <__any_on+0x18>
+ 80098e8:	294007cc 	andi	r5,r5,31
+ 80098ec:	283ff126 	beq	r5,zero,80098b4 <__any_on+0x18>
+ 80098f0:	19800017 	ldw	r6,0(r3)
+ 80098f4:	3144d83a 	srl	r2,r6,r5
+ 80098f8:	114a983a 	sll	r5,r2,r5
+ 80098fc:	317ff51e 	bne	r6,r5,80098d4 <__any_on+0x38>
+ 8009900:	003fec06 	br	80098b4 <__any_on+0x18>
+ 8009904:	f800283a 	ret
+ 8009908:	0005883a 	mov	r2,zero
+ 800990c:	f800283a 	ret
+
+08009910 <_putc_r>:
+ 8009910:	defffc04 	addi	sp,sp,-16
+ 8009914:	dc000215 	stw	r16,8(sp)
+ 8009918:	dfc00315 	stw	ra,12(sp)
+ 800991c:	2021883a 	mov	r16,r4
+ 8009920:	20000226 	beq	r4,zero,800992c <_putc_r+0x1c>
+ 8009924:	20800e17 	ldw	r2,56(r4)
+ 8009928:	10000e26 	beq	r2,zero,8009964 <_putc_r+0x54>
+ 800992c:	30800217 	ldw	r2,8(r6)
+ 8009930:	10bfffc4 	addi	r2,r2,-1
+ 8009934:	30800215 	stw	r2,8(r6)
+ 8009938:	10001316 	blt	r2,zero,8009988 <_putc_r+0x78>
+ 800993c:	30800017 	ldw	r2,0(r6)
+ 8009940:	11400005 	stb	r5,0(r2)
+ 8009944:	30800017 	ldw	r2,0(r6)
+ 8009948:	10c00044 	addi	r3,r2,1
+ 800994c:	30c00015 	stw	r3,0(r6)
+ 8009950:	10800003 	ldbu	r2,0(r2)
+ 8009954:	dfc00317 	ldw	ra,12(sp)
+ 8009958:	dc000217 	ldw	r16,8(sp)
+ 800995c:	dec00404 	addi	sp,sp,16
+ 8009960:	f800283a 	ret
+ 8009964:	d9800115 	stw	r6,4(sp)
+ 8009968:	d9400015 	stw	r5,0(sp)
+ 800996c:	80070600 	call	8007060 <__sinit>
+ 8009970:	d9800117 	ldw	r6,4(sp)
+ 8009974:	d9400017 	ldw	r5,0(sp)
+ 8009978:	30800217 	ldw	r2,8(r6)
+ 800997c:	10bfffc4 	addi	r2,r2,-1
+ 8009980:	30800215 	stw	r2,8(r6)
+ 8009984:	103fed0e 	bge	r2,zero,800993c <_putc_r+0x2c>
+ 8009988:	30c00617 	ldw	r3,24(r6)
+ 800998c:	10c00e16 	blt	r2,r3,80099c8 <_putc_r+0xb8>
+ 8009990:	30800017 	ldw	r2,0(r6)
+ 8009994:	11400005 	stb	r5,0(r2)
+ 8009998:	30c00017 	ldw	r3,0(r6)
+ 800999c:	18800003 	ldbu	r2,0(r3)
+ 80099a0:	108002a0 	cmpeqi	r2,r2,10
+ 80099a4:	1000071e 	bne	r2,zero,80099c4 <_putc_r+0xb4>
+ 80099a8:	18800044 	addi	r2,r3,1
+ 80099ac:	30800015 	stw	r2,0(r6)
+ 80099b0:	18800003 	ldbu	r2,0(r3)
+ 80099b4:	dfc00317 	ldw	ra,12(sp)
+ 80099b8:	dc000217 	ldw	r16,8(sp)
+ 80099bc:	dec00404 	addi	sp,sp,16
+ 80099c0:	f800283a 	ret
+ 80099c4:	01400284 	movi	r5,10
+ 80099c8:	8009883a 	mov	r4,r16
+ 80099cc:	dfc00317 	ldw	ra,12(sp)
+ 80099d0:	dc000217 	ldw	r16,8(sp)
+ 80099d4:	dec00404 	addi	sp,sp,16
+ 80099d8:	800b8141 	jmpi	800b814 <__swbuf_r>
+
+080099dc <putc>:
+ 80099dc:	defffc04 	addi	sp,sp,-16
+ 80099e0:	00820174 	movhi	r2,2053
+ 80099e4:	dc000115 	stw	r16,4(sp)
+ 80099e8:	1432af17 	ldw	r16,-13636(r2)
+ 80099ec:	dc400215 	stw	r17,8(sp)
+ 80099f0:	dfc00315 	stw	ra,12(sp)
+ 80099f4:	2023883a 	mov	r17,r4
+ 80099f8:	80000226 	beq	r16,zero,8009a04 <putc+0x28>
+ 80099fc:	80800e17 	ldw	r2,56(r16)
+ 8009a00:	10000f26 	beq	r2,zero,8009a40 <putc+0x64>
+ 8009a04:	28800217 	ldw	r2,8(r5)
+ 8009a08:	10bfffc4 	addi	r2,r2,-1
+ 8009a0c:	28800215 	stw	r2,8(r5)
+ 8009a10:	10001316 	blt	r2,zero,8009a60 <putc+0x84>
+ 8009a14:	28800017 	ldw	r2,0(r5)
+ 8009a18:	14400005 	stb	r17,0(r2)
+ 8009a1c:	28800017 	ldw	r2,0(r5)
+ 8009a20:	10c00044 	addi	r3,r2,1
+ 8009a24:	28c00015 	stw	r3,0(r5)
+ 8009a28:	10800003 	ldbu	r2,0(r2)
+ 8009a2c:	dfc00317 	ldw	ra,12(sp)
+ 8009a30:	dc400217 	ldw	r17,8(sp)
+ 8009a34:	dc000117 	ldw	r16,4(sp)
+ 8009a38:	dec00404 	addi	sp,sp,16
+ 8009a3c:	f800283a 	ret
+ 8009a40:	8009883a 	mov	r4,r16
+ 8009a44:	d9400015 	stw	r5,0(sp)
+ 8009a48:	80070600 	call	8007060 <__sinit>
+ 8009a4c:	d9400017 	ldw	r5,0(sp)
+ 8009a50:	28800217 	ldw	r2,8(r5)
+ 8009a54:	10bfffc4 	addi	r2,r2,-1
+ 8009a58:	28800215 	stw	r2,8(r5)
+ 8009a5c:	103fed0e 	bge	r2,zero,8009a14 <putc+0x38>
+ 8009a60:	28c00617 	ldw	r3,24(r5)
+ 8009a64:	10c00a16 	blt	r2,r3,8009a90 <putc+0xb4>
+ 8009a68:	28800017 	ldw	r2,0(r5)
+ 8009a6c:	14400005 	stb	r17,0(r2)
+ 8009a70:	28c00017 	ldw	r3,0(r5)
+ 8009a74:	18800003 	ldbu	r2,0(r3)
+ 8009a78:	108002a0 	cmpeqi	r2,r2,10
+ 8009a7c:	10000c1e 	bne	r2,zero,8009ab0 <putc+0xd4>
+ 8009a80:	18800044 	addi	r2,r3,1
+ 8009a84:	28800015 	stw	r2,0(r5)
+ 8009a88:	18800003 	ldbu	r2,0(r3)
+ 8009a8c:	003fe706 	br	8009a2c <putc+0x50>
+ 8009a90:	280d883a 	mov	r6,r5
+ 8009a94:	880b883a 	mov	r5,r17
+ 8009a98:	8009883a 	mov	r4,r16
+ 8009a9c:	dfc00317 	ldw	ra,12(sp)
+ 8009aa0:	dc400217 	ldw	r17,8(sp)
+ 8009aa4:	dc000117 	ldw	r16,4(sp)
+ 8009aa8:	dec00404 	addi	sp,sp,16
+ 8009aac:	800b8141 	jmpi	800b814 <__swbuf_r>
+ 8009ab0:	280d883a 	mov	r6,r5
+ 8009ab4:	01400284 	movi	r5,10
+ 8009ab8:	003ff706 	br	8009a98 <putc+0xbc>
+
+08009abc <_realloc_r>:
+ 8009abc:	defff504 	addi	sp,sp,-44
+ 8009ac0:	dcc00415 	stw	r19,16(sp)
+ 8009ac4:	dfc00a15 	stw	ra,40(sp)
+ 8009ac8:	df000915 	stw	fp,36(sp)
+ 8009acc:	ddc00815 	stw	r23,32(sp)
+ 8009ad0:	dd800715 	stw	r22,28(sp)
+ 8009ad4:	dd400615 	stw	r21,24(sp)
+ 8009ad8:	dd000515 	stw	r20,20(sp)
+ 8009adc:	dc800315 	stw	r18,12(sp)
+ 8009ae0:	dc400215 	stw	r17,8(sp)
+ 8009ae4:	dc000115 	stw	r16,4(sp)
+ 8009ae8:	3027883a 	mov	r19,r6
+ 8009aec:	28008b26 	beq	r5,zero,8009d1c <_realloc_r+0x260>
+ 8009af0:	282d883a 	mov	r22,r5
+ 8009af4:	202b883a 	mov	r21,r4
+ 8009af8:	9c0002c4 	addi	r16,r19,11
+ 8009afc:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 8009b00:	808005f0 	cmpltui	r2,r16,23
+ 8009b04:	1000521e 	bne	r2,zero,8009c50 <_realloc_r+0x194>
+ 8009b08:	017ffe04 	movi	r5,-8
+ 8009b0c:	8160703a 	and	r16,r16,r5
+ 8009b10:	8007883a 	mov	r3,r16
+ 8009b14:	80005116 	blt	r16,zero,8009c5c <_realloc_r+0x1a0>
+ 8009b18:	84c05036 	bltu	r16,r19,8009c5c <_realloc_r+0x1a0>
+ 8009b1c:	b0bfff17 	ldw	r2,-4(r22)
+ 8009b20:	017fff04 	movi	r5,-4
+ 8009b24:	b4bffe04 	addi	r18,r22,-8
+ 8009b28:	1162703a 	and	r17,r2,r5
+ 8009b2c:	9469883a 	add	r20,r18,r17
+ 8009b30:	88c0390e 	bge	r17,r3,8009c18 <_realloc_r+0x15c>
+ 8009b34:	07020174 	movhi	fp,2053
+ 8009b38:	e72fa904 	addi	fp,fp,-16732
+ 8009b3c:	e2000217 	ldw	r8,8(fp)
+ 8009b40:	a1000117 	ldw	r4,4(r20)
+ 8009b44:	45008e26 	beq	r8,r20,8009d80 <_realloc_r+0x2c4>
+ 8009b48:	01bfff84 	movi	r6,-2
+ 8009b4c:	218c703a 	and	r6,r4,r6
+ 8009b50:	a18d883a 	add	r6,r20,r6
+ 8009b54:	31800117 	ldw	r6,4(r6)
+ 8009b58:	3180004c 	andi	r6,r6,1
+ 8009b5c:	30004f1e 	bne	r6,zero,8009c9c <_realloc_r+0x1e0>
+ 8009b60:	2148703a 	and	r4,r4,r5
+ 8009b64:	890b883a 	add	r5,r17,r4
+ 8009b68:	28c0cb0e 	bge	r5,r3,8009e98 <_realloc_r+0x3dc>
+ 8009b6c:	1080004c 	andi	r2,r2,1
+ 8009b70:	10004c1e 	bne	r2,zero,8009ca4 <_realloc_r+0x1e8>
+ 8009b74:	b1fffe17 	ldw	r7,-8(r22)
+ 8009b78:	00bfff04 	movi	r2,-4
+ 8009b7c:	91cfc83a 	sub	r7,r18,r7
+ 8009b80:	39400117 	ldw	r5,4(r7)
+ 8009b84:	288a703a 	and	r5,r5,r2
+ 8009b88:	a0000426 	beq	r20,zero,8009b9c <_realloc_r+0xe0>
+ 8009b8c:	896f883a 	add	r23,r17,r5
+ 8009b90:	b92f883a 	add	r23,r23,r4
+ 8009b94:	4500cb26 	beq	r8,r20,8009ec4 <_realloc_r+0x408>
+ 8009b98:	b8c0930e 	bge	r23,r3,8009de8 <_realloc_r+0x32c>
+ 8009b9c:	38004126 	beq	r7,zero,8009ca4 <_realloc_r+0x1e8>
+ 8009ba0:	896f883a 	add	r23,r17,r5
+ 8009ba4:	b8c03f16 	blt	r23,r3,8009ca4 <_realloc_r+0x1e8>
+ 8009ba8:	38c00217 	ldw	r3,8(r7)
+ 8009bac:	38800317 	ldw	r2,12(r7)
+ 8009bb0:	89bfff04 	addi	r6,r17,-4
+ 8009bb4:	31000968 	cmpgeui	r4,r6,37
+ 8009bb8:	18800315 	stw	r2,12(r3)
+ 8009bbc:	10c00215 	stw	r3,8(r2)
+ 8009bc0:	3de9883a 	add	r20,r7,r23
+ 8009bc4:	38c00204 	addi	r3,r7,8
+ 8009bc8:	2000f81e 	bne	r4,zero,8009fac <_realloc_r+0x4f0>
+ 8009bcc:	30800530 	cmpltui	r2,r6,20
+ 8009bd0:	b1000017 	ldw	r4,0(r22)
+ 8009bd4:	1000eb1e 	bne	r2,zero,8009f84 <_realloc_r+0x4c8>
+ 8009bd8:	39000215 	stw	r4,8(r7)
+ 8009bdc:	b1000117 	ldw	r4,4(r22)
+ 8009be0:	30800728 	cmpgeui	r2,r6,28
+ 8009be4:	39000315 	stw	r4,12(r7)
+ 8009be8:	1001041e 	bne	r2,zero,8009ffc <_realloc_r+0x540>
+ 8009bec:	b1000217 	ldw	r4,8(r22)
+ 8009bf0:	38800404 	addi	r2,r7,16
+ 8009bf4:	b5800204 	addi	r22,r22,8
+ 8009bf8:	11000015 	stw	r4,0(r2)
+ 8009bfc:	b1000117 	ldw	r4,4(r22)
+ 8009c00:	b823883a 	mov	r17,r23
+ 8009c04:	3825883a 	mov	r18,r7
+ 8009c08:	11000115 	stw	r4,4(r2)
+ 8009c0c:	b1000217 	ldw	r4,8(r22)
+ 8009c10:	182d883a 	mov	r22,r3
+ 8009c14:	11000215 	stw	r4,8(r2)
+ 8009c18:	91800117 	ldw	r6,4(r18)
+ 8009c1c:	8c05c83a 	sub	r2,r17,r16
+ 8009c20:	10c00430 	cmpltui	r3,r2,16
+ 8009c24:	3180004c 	andi	r6,r6,1
+ 8009c28:	18004926 	beq	r3,zero,8009d50 <_realloc_r+0x294>
+ 8009c2c:	898cb03a 	or	r6,r17,r6
+ 8009c30:	91800115 	stw	r6,4(r18)
+ 8009c34:	a0800117 	ldw	r2,4(r20)
+ 8009c38:	10800054 	ori	r2,r2,1
+ 8009c3c:	a0800115 	stw	r2,4(r20)
+ 8009c40:	a809883a 	mov	r4,r21
+ 8009c44:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8009c48:	b027883a 	mov	r19,r22
+ 8009c4c:	00000606 	br	8009c68 <_realloc_r+0x1ac>
+ 8009c50:	04000404 	movi	r16,16
+ 8009c54:	00c00404 	movi	r3,16
+ 8009c58:	84ffb02e 	bgeu	r16,r19,8009b1c <_realloc_r+0x60>
+ 8009c5c:	00800304 	movi	r2,12
+ 8009c60:	a8800015 	stw	r2,0(r21)
+ 8009c64:	0027883a 	mov	r19,zero
+ 8009c68:	9805883a 	mov	r2,r19
+ 8009c6c:	dfc00a17 	ldw	ra,40(sp)
+ 8009c70:	df000917 	ldw	fp,36(sp)
+ 8009c74:	ddc00817 	ldw	r23,32(sp)
+ 8009c78:	dd800717 	ldw	r22,28(sp)
+ 8009c7c:	dd400617 	ldw	r21,24(sp)
+ 8009c80:	dd000517 	ldw	r20,20(sp)
+ 8009c84:	dcc00417 	ldw	r19,16(sp)
+ 8009c88:	dc800317 	ldw	r18,12(sp)
+ 8009c8c:	dc400217 	ldw	r17,8(sp)
+ 8009c90:	dc000117 	ldw	r16,4(sp)
+ 8009c94:	dec00b04 	addi	sp,sp,44
+ 8009c98:	f800283a 	ret
+ 8009c9c:	1080004c 	andi	r2,r2,1
+ 8009ca0:	10007826 	beq	r2,zero,8009e84 <_realloc_r+0x3c8>
+ 8009ca4:	980b883a 	mov	r5,r19
+ 8009ca8:	a809883a 	mov	r4,r21
+ 8009cac:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8009cb0:	1027883a 	mov	r19,r2
+ 8009cb4:	10001626 	beq	r2,zero,8009d10 <_realloc_r+0x254>
+ 8009cb8:	b0bfff17 	ldw	r2,-4(r22)
+ 8009cbc:	013fff84 	movi	r4,-2
+ 8009cc0:	98fffe04 	addi	r3,r19,-8
+ 8009cc4:	1104703a 	and	r2,r2,r4
+ 8009cc8:	9085883a 	add	r2,r18,r2
+ 8009ccc:	10c06726 	beq	r2,r3,8009e6c <_realloc_r+0x3b0>
+ 8009cd0:	89bfff04 	addi	r6,r17,-4
+ 8009cd4:	30800968 	cmpgeui	r2,r6,37
+ 8009cd8:	1000761e 	bne	r2,zero,8009eb4 <_realloc_r+0x3f8>
+ 8009cdc:	30800530 	cmpltui	r2,r6,20
+ 8009ce0:	b1000017 	ldw	r4,0(r22)
+ 8009ce4:	10003726 	beq	r2,zero,8009dc4 <_realloc_r+0x308>
+ 8009ce8:	9805883a 	mov	r2,r19
+ 8009cec:	b007883a 	mov	r3,r22
+ 8009cf0:	11000015 	stw	r4,0(r2)
+ 8009cf4:	19000117 	ldw	r4,4(r3)
+ 8009cf8:	11000115 	stw	r4,4(r2)
+ 8009cfc:	18c00217 	ldw	r3,8(r3)
+ 8009d00:	10c00215 	stw	r3,8(r2)
+ 8009d04:	b00b883a 	mov	r5,r22
+ 8009d08:	a809883a 	mov	r4,r21
+ 8009d0c:	80071c40 	call	80071c4 <_free_r>
+ 8009d10:	a809883a 	mov	r4,r21
+ 8009d14:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8009d18:	003fd306 	br	8009c68 <_realloc_r+0x1ac>
+ 8009d1c:	300b883a 	mov	r5,r6
+ 8009d20:	dfc00a17 	ldw	ra,40(sp)
+ 8009d24:	df000917 	ldw	fp,36(sp)
+ 8009d28:	ddc00817 	ldw	r23,32(sp)
+ 8009d2c:	dd800717 	ldw	r22,28(sp)
+ 8009d30:	dd400617 	ldw	r21,24(sp)
+ 8009d34:	dd000517 	ldw	r20,20(sp)
+ 8009d38:	dcc00417 	ldw	r19,16(sp)
+ 8009d3c:	dc800317 	ldw	r18,12(sp)
+ 8009d40:	dc400217 	ldw	r17,8(sp)
+ 8009d44:	dc000117 	ldw	r16,4(sp)
+ 8009d48:	dec00b04 	addi	sp,sp,44
+ 8009d4c:	8007ddc1 	jmpi	8007ddc <_malloc_r>
+ 8009d50:	340cb03a 	or	r6,r6,r16
+ 8009d54:	91800115 	stw	r6,4(r18)
+ 8009d58:	940b883a 	add	r5,r18,r16
+ 8009d5c:	10800054 	ori	r2,r2,1
+ 8009d60:	28800115 	stw	r2,4(r5)
+ 8009d64:	a0800117 	ldw	r2,4(r20)
+ 8009d68:	29400204 	addi	r5,r5,8
+ 8009d6c:	a809883a 	mov	r4,r21
+ 8009d70:	10800054 	ori	r2,r2,1
+ 8009d74:	a0800115 	stw	r2,4(r20)
+ 8009d78:	80071c40 	call	80071c4 <_free_r>
+ 8009d7c:	003fb006 	br	8009c40 <_realloc_r+0x184>
+ 8009d80:	2148703a 	and	r4,r4,r5
+ 8009d84:	890b883a 	add	r5,r17,r4
+ 8009d88:	81800404 	addi	r6,r16,16
+ 8009d8c:	29bf7716 	blt	r5,r6,8009b6c <_realloc_r+0xb0>
+ 8009d90:	9425883a 	add	r18,r18,r16
+ 8009d94:	2c05c83a 	sub	r2,r5,r16
+ 8009d98:	e4800215 	stw	r18,8(fp)
+ 8009d9c:	10800054 	ori	r2,r2,1
+ 8009da0:	90800115 	stw	r2,4(r18)
+ 8009da4:	b0bfff17 	ldw	r2,-4(r22)
+ 8009da8:	a809883a 	mov	r4,r21
+ 8009dac:	b027883a 	mov	r19,r22
+ 8009db0:	1080004c 	andi	r2,r2,1
+ 8009db4:	1420b03a 	or	r16,r2,r16
+ 8009db8:	b43fff15 	stw	r16,-4(r22)
+ 8009dbc:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8009dc0:	003fa906 	br	8009c68 <_realloc_r+0x1ac>
+ 8009dc4:	99000015 	stw	r4,0(r19)
+ 8009dc8:	b0c00117 	ldw	r3,4(r22)
+ 8009dcc:	30800728 	cmpgeui	r2,r6,28
+ 8009dd0:	98c00115 	stw	r3,4(r19)
+ 8009dd4:	1000611e 	bne	r2,zero,8009f5c <_realloc_r+0x4a0>
+ 8009dd8:	b0c00204 	addi	r3,r22,8
+ 8009ddc:	98800204 	addi	r2,r19,8
+ 8009de0:	b1000217 	ldw	r4,8(r22)
+ 8009de4:	003fc206 	br	8009cf0 <_realloc_r+0x234>
+ 8009de8:	a0800317 	ldw	r2,12(r20)
+ 8009dec:	a0c00217 	ldw	r3,8(r20)
+ 8009df0:	89bfff04 	addi	r6,r17,-4
+ 8009df4:	31000968 	cmpgeui	r4,r6,37
+ 8009df8:	18800315 	stw	r2,12(r3)
+ 8009dfc:	10c00215 	stw	r3,8(r2)
+ 8009e00:	38c00217 	ldw	r3,8(r7)
+ 8009e04:	38800317 	ldw	r2,12(r7)
+ 8009e08:	3a000204 	addi	r8,r7,8
+ 8009e0c:	3de9883a 	add	r20,r7,r23
+ 8009e10:	18800315 	stw	r2,12(r3)
+ 8009e14:	10c00215 	stw	r3,8(r2)
+ 8009e18:	20006f1e 	bne	r4,zero,8009fd8 <_realloc_r+0x51c>
+ 8009e1c:	30800530 	cmpltui	r2,r6,20
+ 8009e20:	b0c00017 	ldw	r3,0(r22)
+ 8009e24:	10006a1e 	bne	r2,zero,8009fd0 <_realloc_r+0x514>
+ 8009e28:	38c00215 	stw	r3,8(r7)
+ 8009e2c:	b0c00117 	ldw	r3,4(r22)
+ 8009e30:	30800728 	cmpgeui	r2,r6,28
+ 8009e34:	38c00315 	stw	r3,12(r7)
+ 8009e38:	10007a1e 	bne	r2,zero,800a024 <_realloc_r+0x568>
+ 8009e3c:	b0c00217 	ldw	r3,8(r22)
+ 8009e40:	38800404 	addi	r2,r7,16
+ 8009e44:	b5800204 	addi	r22,r22,8
+ 8009e48:	10c00015 	stw	r3,0(r2)
+ 8009e4c:	b0c00117 	ldw	r3,4(r22)
+ 8009e50:	b823883a 	mov	r17,r23
+ 8009e54:	3825883a 	mov	r18,r7
+ 8009e58:	10c00115 	stw	r3,4(r2)
+ 8009e5c:	b0c00217 	ldw	r3,8(r22)
+ 8009e60:	402d883a 	mov	r22,r8
+ 8009e64:	10c00215 	stw	r3,8(r2)
+ 8009e68:	003f6b06 	br	8009c18 <_realloc_r+0x15c>
+ 8009e6c:	98bfff17 	ldw	r2,-4(r19)
+ 8009e70:	00ffff04 	movi	r3,-4
+ 8009e74:	10c4703a 	and	r2,r2,r3
+ 8009e78:	88a3883a 	add	r17,r17,r2
+ 8009e7c:	9469883a 	add	r20,r18,r17
+ 8009e80:	003f6506 	br	8009c18 <_realloc_r+0x15c>
+ 8009e84:	b1fffe17 	ldw	r7,-8(r22)
+ 8009e88:	91cfc83a 	sub	r7,r18,r7
+ 8009e8c:	39000117 	ldw	r4,4(r7)
+ 8009e90:	214a703a 	and	r5,r4,r5
+ 8009e94:	003f4106 	br	8009b9c <_realloc_r+0xe0>
+ 8009e98:	a0800317 	ldw	r2,12(r20)
+ 8009e9c:	a0c00217 	ldw	r3,8(r20)
+ 8009ea0:	2823883a 	mov	r17,r5
+ 8009ea4:	9169883a 	add	r20,r18,r5
+ 8009ea8:	18800315 	stw	r2,12(r3)
+ 8009eac:	10c00215 	stw	r3,8(r2)
+ 8009eb0:	003f5906 	br	8009c18 <_realloc_r+0x15c>
+ 8009eb4:	b00b883a 	mov	r5,r22
+ 8009eb8:	9809883a 	mov	r4,r19
+ 8009ebc:	80087b80 	call	80087b8 <memmove>
+ 8009ec0:	003f9006 	br	8009d04 <_realloc_r+0x248>
+ 8009ec4:	80800404 	addi	r2,r16,16
+ 8009ec8:	b8bf3416 	blt	r23,r2,8009b9c <_realloc_r+0xe0>
+ 8009ecc:	38800317 	ldw	r2,12(r7)
+ 8009ed0:	38c00217 	ldw	r3,8(r7)
+ 8009ed4:	89bfff04 	addi	r6,r17,-4
+ 8009ed8:	31000968 	cmpgeui	r4,r6,37
+ 8009edc:	18800315 	stw	r2,12(r3)
+ 8009ee0:	10c00215 	stw	r3,8(r2)
+ 8009ee4:	3cc00204 	addi	r19,r7,8
+ 8009ee8:	20005a1e 	bne	r4,zero,800a054 <_realloc_r+0x598>
+ 8009eec:	30800530 	cmpltui	r2,r6,20
+ 8009ef0:	b0c00017 	ldw	r3,0(r22)
+ 8009ef4:	1000551e 	bne	r2,zero,800a04c <_realloc_r+0x590>
+ 8009ef8:	38c00215 	stw	r3,8(r7)
+ 8009efc:	b0c00117 	ldw	r3,4(r22)
+ 8009f00:	30800728 	cmpgeui	r2,r6,28
+ 8009f04:	38c00315 	stw	r3,12(r7)
+ 8009f08:	1000661e 	bne	r2,zero,800a0a4 <_realloc_r+0x5e8>
+ 8009f0c:	b0c00217 	ldw	r3,8(r22)
+ 8009f10:	38800404 	addi	r2,r7,16
+ 8009f14:	b5800204 	addi	r22,r22,8
+ 8009f18:	10c00015 	stw	r3,0(r2)
+ 8009f1c:	b0c00117 	ldw	r3,4(r22)
+ 8009f20:	10c00115 	stw	r3,4(r2)
+ 8009f24:	b0c00217 	ldw	r3,8(r22)
+ 8009f28:	10c00215 	stw	r3,8(r2)
+ 8009f2c:	3c07883a 	add	r3,r7,r16
+ 8009f30:	bc05c83a 	sub	r2,r23,r16
+ 8009f34:	e0c00215 	stw	r3,8(fp)
+ 8009f38:	10800054 	ori	r2,r2,1
+ 8009f3c:	18800115 	stw	r2,4(r3)
+ 8009f40:	38800117 	ldw	r2,4(r7)
+ 8009f44:	a809883a 	mov	r4,r21
+ 8009f48:	1080004c 	andi	r2,r2,1
+ 8009f4c:	1420b03a 	or	r16,r2,r16
+ 8009f50:	3c000115 	stw	r16,4(r7)
+ 8009f54:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8009f58:	003f4306 	br	8009c68 <_realloc_r+0x1ac>
+ 8009f5c:	b0800217 	ldw	r2,8(r22)
+ 8009f60:	31800920 	cmpeqi	r6,r6,36
+ 8009f64:	98800215 	stw	r2,8(r19)
+ 8009f68:	b0800317 	ldw	r2,12(r22)
+ 8009f6c:	98800315 	stw	r2,12(r19)
+ 8009f70:	3000061e 	bne	r6,zero,8009f8c <_realloc_r+0x4d0>
+ 8009f74:	b0c00404 	addi	r3,r22,16
+ 8009f78:	98800404 	addi	r2,r19,16
+ 8009f7c:	b1000417 	ldw	r4,16(r22)
+ 8009f80:	003f5b06 	br	8009cf0 <_realloc_r+0x234>
+ 8009f84:	1805883a 	mov	r2,r3
+ 8009f88:	003f1b06 	br	8009bf8 <_realloc_r+0x13c>
+ 8009f8c:	b1000417 	ldw	r4,16(r22)
+ 8009f90:	b0c00604 	addi	r3,r22,24
+ 8009f94:	98800604 	addi	r2,r19,24
+ 8009f98:	99000415 	stw	r4,16(r19)
+ 8009f9c:	b1000517 	ldw	r4,20(r22)
+ 8009fa0:	99000515 	stw	r4,20(r19)
+ 8009fa4:	b1000617 	ldw	r4,24(r22)
+ 8009fa8:	003f5106 	br	8009cf0 <_realloc_r+0x234>
+ 8009fac:	b00b883a 	mov	r5,r22
+ 8009fb0:	1809883a 	mov	r4,r3
+ 8009fb4:	d9c00015 	stw	r7,0(sp)
+ 8009fb8:	80087b80 	call	80087b8 <memmove>
+ 8009fbc:	d9c00017 	ldw	r7,0(sp)
+ 8009fc0:	102d883a 	mov	r22,r2
+ 8009fc4:	b823883a 	mov	r17,r23
+ 8009fc8:	3825883a 	mov	r18,r7
+ 8009fcc:	003f1206 	br	8009c18 <_realloc_r+0x15c>
+ 8009fd0:	4005883a 	mov	r2,r8
+ 8009fd4:	003f9c06 	br	8009e48 <_realloc_r+0x38c>
+ 8009fd8:	b00b883a 	mov	r5,r22
+ 8009fdc:	4009883a 	mov	r4,r8
+ 8009fe0:	d9c00015 	stw	r7,0(sp)
+ 8009fe4:	80087b80 	call	80087b8 <memmove>
+ 8009fe8:	d9c00017 	ldw	r7,0(sp)
+ 8009fec:	102d883a 	mov	r22,r2
+ 8009ff0:	b823883a 	mov	r17,r23
+ 8009ff4:	3825883a 	mov	r18,r7
+ 8009ff8:	003f0706 	br	8009c18 <_realloc_r+0x15c>
+ 8009ffc:	b0800217 	ldw	r2,8(r22)
+ 800a000:	31800920 	cmpeqi	r6,r6,36
+ 800a004:	38800415 	stw	r2,16(r7)
+ 800a008:	b0800317 	ldw	r2,12(r22)
+ 800a00c:	38800515 	stw	r2,20(r7)
+ 800a010:	b1000417 	ldw	r4,16(r22)
+ 800a014:	3000151e 	bne	r6,zero,800a06c <_realloc_r+0x5b0>
+ 800a018:	38800604 	addi	r2,r7,24
+ 800a01c:	b5800404 	addi	r22,r22,16
+ 800a020:	003ef506 	br	8009bf8 <_realloc_r+0x13c>
+ 800a024:	b0800217 	ldw	r2,8(r22)
+ 800a028:	31800920 	cmpeqi	r6,r6,36
+ 800a02c:	38800415 	stw	r2,16(r7)
+ 800a030:	b0800317 	ldw	r2,12(r22)
+ 800a034:	38800515 	stw	r2,20(r7)
+ 800a038:	b0c00417 	ldw	r3,16(r22)
+ 800a03c:	3000121e 	bne	r6,zero,800a088 <_realloc_r+0x5cc>
+ 800a040:	38800604 	addi	r2,r7,24
+ 800a044:	b5800404 	addi	r22,r22,16
+ 800a048:	003f7f06 	br	8009e48 <_realloc_r+0x38c>
+ 800a04c:	9805883a 	mov	r2,r19
+ 800a050:	003fb106 	br	8009f18 <_realloc_r+0x45c>
+ 800a054:	b00b883a 	mov	r5,r22
+ 800a058:	9809883a 	mov	r4,r19
+ 800a05c:	d9c00015 	stw	r7,0(sp)
+ 800a060:	80087b80 	call	80087b8 <memmove>
+ 800a064:	d9c00017 	ldw	r7,0(sp)
+ 800a068:	003fb006 	br	8009f2c <_realloc_r+0x470>
+ 800a06c:	b5800604 	addi	r22,r22,24
+ 800a070:	39000615 	stw	r4,24(r7)
+ 800a074:	b13fff17 	ldw	r4,-4(r22)
+ 800a078:	38800804 	addi	r2,r7,32
+ 800a07c:	39000715 	stw	r4,28(r7)
+ 800a080:	b1000017 	ldw	r4,0(r22)
+ 800a084:	003edc06 	br	8009bf8 <_realloc_r+0x13c>
+ 800a088:	b5800604 	addi	r22,r22,24
+ 800a08c:	38c00615 	stw	r3,24(r7)
+ 800a090:	b0ffff17 	ldw	r3,-4(r22)
+ 800a094:	38800804 	addi	r2,r7,32
+ 800a098:	38c00715 	stw	r3,28(r7)
+ 800a09c:	b0c00017 	ldw	r3,0(r22)
+ 800a0a0:	003f6906 	br	8009e48 <_realloc_r+0x38c>
+ 800a0a4:	b0800217 	ldw	r2,8(r22)
+ 800a0a8:	31800920 	cmpeqi	r6,r6,36
+ 800a0ac:	38800415 	stw	r2,16(r7)
+ 800a0b0:	b0800317 	ldw	r2,12(r22)
+ 800a0b4:	38800515 	stw	r2,20(r7)
+ 800a0b8:	b0c00417 	ldw	r3,16(r22)
+ 800a0bc:	3000031e 	bne	r6,zero,800a0cc <_realloc_r+0x610>
+ 800a0c0:	38800604 	addi	r2,r7,24
+ 800a0c4:	b5800404 	addi	r22,r22,16
+ 800a0c8:	003f9306 	br	8009f18 <_realloc_r+0x45c>
+ 800a0cc:	b5800604 	addi	r22,r22,24
+ 800a0d0:	38c00615 	stw	r3,24(r7)
+ 800a0d4:	b0ffff17 	ldw	r3,-4(r22)
+ 800a0d8:	38800804 	addi	r2,r7,32
+ 800a0dc:	38c00715 	stw	r3,28(r7)
+ 800a0e0:	b0c00017 	ldw	r3,0(r22)
+ 800a0e4:	003f8c06 	br	8009f18 <_realloc_r+0x45c>
+
+0800a0e8 <__srget_r>:
+ 800a0e8:	defffd04 	addi	sp,sp,-12
+ 800a0ec:	dc400115 	stw	r17,4(sp)
+ 800a0f0:	dc000015 	stw	r16,0(sp)
+ 800a0f4:	dfc00215 	stw	ra,8(sp)
+ 800a0f8:	2023883a 	mov	r17,r4
+ 800a0fc:	2821883a 	mov	r16,r5
+ 800a100:	20000226 	beq	r4,zero,800a10c <__srget_r+0x24>
+ 800a104:	20800e17 	ldw	r2,56(r4)
+ 800a108:	10001026 	beq	r2,zero,800a14c <__srget_r+0x64>
+ 800a10c:	800b883a 	mov	r5,r16
+ 800a110:	8809883a 	mov	r4,r17
+ 800a114:	800c0580 	call	800c058 <__srefill_r>
+ 800a118:	10000e1e 	bne	r2,zero,800a154 <__srget_r+0x6c>
+ 800a11c:	80c00017 	ldw	r3,0(r16)
+ 800a120:	80800117 	ldw	r2,4(r16)
+ 800a124:	19000044 	addi	r4,r3,1
+ 800a128:	10bfffc4 	addi	r2,r2,-1
+ 800a12c:	80800115 	stw	r2,4(r16)
+ 800a130:	81000015 	stw	r4,0(r16)
+ 800a134:	18800003 	ldbu	r2,0(r3)
+ 800a138:	dfc00217 	ldw	ra,8(sp)
+ 800a13c:	dc400117 	ldw	r17,4(sp)
+ 800a140:	dc000017 	ldw	r16,0(sp)
+ 800a144:	dec00304 	addi	sp,sp,12
+ 800a148:	f800283a 	ret
+ 800a14c:	80070600 	call	8007060 <__sinit>
+ 800a150:	003fee06 	br	800a10c <__srget_r+0x24>
+ 800a154:	00bfffc4 	movi	r2,-1
+ 800a158:	003ff706 	br	800a138 <__srget_r+0x50>
+
+0800a15c <__srget>:
+ 800a15c:	00820174 	movhi	r2,2053
+ 800a160:	200b883a 	mov	r5,r4
+ 800a164:	1132af17 	ldw	r4,-13636(r2)
+ 800a168:	800a0e81 	jmpi	800a0e8 <__srget_r>
+
+0800a16c <_sbrk_r>:
+ 800a16c:	defffe04 	addi	sp,sp,-8
+ 800a170:	dc000015 	stw	r16,0(sp)
+ 800a174:	00820174 	movhi	r2,2053
+ 800a178:	2021883a 	mov	r16,r4
+ 800a17c:	2809883a 	mov	r4,r5
+ 800a180:	dfc00115 	stw	ra,4(sp)
+ 800a184:	1032f015 	stw	zero,-13376(r2)
+ 800a188:	800fc380 	call	800fc38 <sbrk>
+ 800a18c:	10ffffd8 	cmpnei	r3,r2,-1
+ 800a190:	18000426 	beq	r3,zero,800a1a4 <_sbrk_r+0x38>
+ 800a194:	dfc00117 	ldw	ra,4(sp)
+ 800a198:	dc000017 	ldw	r16,0(sp)
+ 800a19c:	dec00204 	addi	sp,sp,8
+ 800a1a0:	f800283a 	ret
+ 800a1a4:	00c20174 	movhi	r3,2053
+ 800a1a8:	18f2f017 	ldw	r3,-13376(r3)
+ 800a1ac:	183ff926 	beq	r3,zero,800a194 <_sbrk_r+0x28>
+ 800a1b0:	80c00015 	stw	r3,0(r16)
+ 800a1b4:	dfc00117 	ldw	ra,4(sp)
+ 800a1b8:	dc000017 	ldw	r16,0(sp)
+ 800a1bc:	dec00204 	addi	sp,sp,8
+ 800a1c0:	f800283a 	ret
+
+0800a1c4 <__sread>:
+ 800a1c4:	defffe04 	addi	sp,sp,-8
+ 800a1c8:	dc000015 	stw	r16,0(sp)
+ 800a1cc:	2821883a 	mov	r16,r5
+ 800a1d0:	2940038f 	ldh	r5,14(r5)
+ 800a1d4:	dfc00115 	stw	ra,4(sp)
+ 800a1d8:	800bfd80 	call	800bfd8 <_read_r>
+ 800a1dc:	10000716 	blt	r2,zero,800a1fc <__sread+0x38>
+ 800a1e0:	80c01417 	ldw	r3,80(r16)
+ 800a1e4:	1887883a 	add	r3,r3,r2
+ 800a1e8:	80c01415 	stw	r3,80(r16)
+ 800a1ec:	dfc00117 	ldw	ra,4(sp)
+ 800a1f0:	dc000017 	ldw	r16,0(sp)
+ 800a1f4:	dec00204 	addi	sp,sp,8
+ 800a1f8:	f800283a 	ret
+ 800a1fc:	80c0030b 	ldhu	r3,12(r16)
+ 800a200:	18fbffcc 	andi	r3,r3,61439
+ 800a204:	80c0030d 	sth	r3,12(r16)
+ 800a208:	dfc00117 	ldw	ra,4(sp)
+ 800a20c:	dc000017 	ldw	r16,0(sp)
+ 800a210:	dec00204 	addi	sp,sp,8
+ 800a214:	f800283a 	ret
+
+0800a218 <__seofread>:
+ 800a218:	0005883a 	mov	r2,zero
+ 800a21c:	f800283a 	ret
+
+0800a220 <__swrite>:
+ 800a220:	2880030b 	ldhu	r2,12(r5)
+ 800a224:	defffb04 	addi	sp,sp,-20
+ 800a228:	dcc00315 	stw	r19,12(sp)
+ 800a22c:	dc800215 	stw	r18,8(sp)
+ 800a230:	dc400115 	stw	r17,4(sp)
+ 800a234:	dc000015 	stw	r16,0(sp)
+ 800a238:	dfc00415 	stw	ra,16(sp)
+ 800a23c:	10c0400c 	andi	r3,r2,256
+ 800a240:	2821883a 	mov	r16,r5
+ 800a244:	2023883a 	mov	r17,r4
+ 800a248:	3025883a 	mov	r18,r6
+ 800a24c:	3827883a 	mov	r19,r7
+ 800a250:	2940038f 	ldh	r5,14(r5)
+ 800a254:	18000c1e 	bne	r3,zero,800a288 <__swrite+0x68>
+ 800a258:	10bbffcc 	andi	r2,r2,61439
+ 800a25c:	980f883a 	mov	r7,r19
+ 800a260:	900d883a 	mov	r6,r18
+ 800a264:	8809883a 	mov	r4,r17
+ 800a268:	8080030d 	sth	r2,12(r16)
+ 800a26c:	dfc00417 	ldw	ra,16(sp)
+ 800a270:	dcc00317 	ldw	r19,12(sp)
+ 800a274:	dc800217 	ldw	r18,8(sp)
+ 800a278:	dc400117 	ldw	r17,4(sp)
+ 800a27c:	dc000017 	ldw	r16,0(sp)
+ 800a280:	dec00504 	addi	sp,sp,20
+ 800a284:	800b9701 	jmpi	800b970 <_write_r>
+ 800a288:	01c00084 	movi	r7,2
+ 800a28c:	000d883a 	mov	r6,zero
+ 800a290:	800bf240 	call	800bf24 <_lseek_r>
+ 800a294:	8080030b 	ldhu	r2,12(r16)
+ 800a298:	8140038f 	ldh	r5,14(r16)
+ 800a29c:	003fee06 	br	800a258 <__swrite+0x38>
+
+0800a2a0 <__sseek>:
+ 800a2a0:	defffe04 	addi	sp,sp,-8
+ 800a2a4:	dc000015 	stw	r16,0(sp)
+ 800a2a8:	2821883a 	mov	r16,r5
+ 800a2ac:	2940038f 	ldh	r5,14(r5)
+ 800a2b0:	dfc00115 	stw	ra,4(sp)
+ 800a2b4:	800bf240 	call	800bf24 <_lseek_r>
+ 800a2b8:	10ffffd8 	cmpnei	r3,r2,-1
+ 800a2bc:	18000826 	beq	r3,zero,800a2e0 <__sseek+0x40>
+ 800a2c0:	80c0030b 	ldhu	r3,12(r16)
+ 800a2c4:	80801415 	stw	r2,80(r16)
+ 800a2c8:	18c40014 	ori	r3,r3,4096
+ 800a2cc:	80c0030d 	sth	r3,12(r16)
+ 800a2d0:	dfc00117 	ldw	ra,4(sp)
+ 800a2d4:	dc000017 	ldw	r16,0(sp)
+ 800a2d8:	dec00204 	addi	sp,sp,8
+ 800a2dc:	f800283a 	ret
+ 800a2e0:	80c0030b 	ldhu	r3,12(r16)
+ 800a2e4:	18fbffcc 	andi	r3,r3,61439
+ 800a2e8:	80c0030d 	sth	r3,12(r16)
+ 800a2ec:	dfc00117 	ldw	ra,4(sp)
+ 800a2f0:	dc000017 	ldw	r16,0(sp)
+ 800a2f4:	dec00204 	addi	sp,sp,8
+ 800a2f8:	f800283a 	ret
+
+0800a2fc <__sclose>:
+ 800a2fc:	2940038f 	ldh	r5,14(r5)
+ 800a300:	800b9d41 	jmpi	800b9d4 <_close_r>
+
+0800a304 <__sprint_r.part.0>:
+ 800a304:	28801917 	ldw	r2,100(r5)
+ 800a308:	defff604 	addi	sp,sp,-40
+ 800a30c:	dd000415 	stw	r20,16(sp)
+ 800a310:	dfc00915 	stw	ra,36(sp)
+ 800a314:	df000815 	stw	fp,32(sp)
+ 800a318:	ddc00715 	stw	r23,28(sp)
+ 800a31c:	dd800615 	stw	r22,24(sp)
+ 800a320:	dd400515 	stw	r21,20(sp)
+ 800a324:	dcc00315 	stw	r19,12(sp)
+ 800a328:	dc800215 	stw	r18,8(sp)
+ 800a32c:	dc400115 	stw	r17,4(sp)
+ 800a330:	dc000015 	stw	r16,0(sp)
+ 800a334:	1088000c 	andi	r2,r2,8192
+ 800a338:	3029883a 	mov	r20,r6
+ 800a33c:	10002c26 	beq	r2,zero,800a3f0 <__sprint_r.part.0+0xec>
+ 800a340:	30800217 	ldw	r2,8(r6)
+ 800a344:	2823883a 	mov	r17,r5
+ 800a348:	2027883a 	mov	r19,r4
+ 800a34c:	35400017 	ldw	r21,0(r6)
+ 800a350:	05ffff04 	movi	r23,-4
+ 800a354:	10002426 	beq	r2,zero,800a3e8 <__sprint_r.part.0+0xe4>
+ 800a358:	ad800117 	ldw	r22,4(r21)
+ 800a35c:	ac000017 	ldw	r16,0(r21)
+ 800a360:	b024d0ba 	srli	r18,r22,2
+ 800a364:	90001b26 	beq	r18,zero,800a3d4 <__sprint_r.part.0+0xd0>
+ 800a368:	0039883a 	mov	fp,zero
+ 800a36c:	00000206 	br	800a378 <__sprint_r.part.0+0x74>
+ 800a370:	84000104 	addi	r16,r16,4
+ 800a374:	97001626 	beq	r18,fp,800a3d0 <__sprint_r.part.0+0xcc>
+ 800a378:	81400017 	ldw	r5,0(r16)
+ 800a37c:	880d883a 	mov	r6,r17
+ 800a380:	9809883a 	mov	r4,r19
+ 800a384:	800bd3c0 	call	800bd3c <_fputwc_r>
+ 800a388:	10bfffe0 	cmpeqi	r2,r2,-1
+ 800a38c:	e7000044 	addi	fp,fp,1
+ 800a390:	103ff726 	beq	r2,zero,800a370 <__sprint_r.part.0+0x6c>
+ 800a394:	00bfffc4 	movi	r2,-1
+ 800a398:	a0000215 	stw	zero,8(r20)
+ 800a39c:	a0000115 	stw	zero,4(r20)
+ 800a3a0:	dfc00917 	ldw	ra,36(sp)
+ 800a3a4:	df000817 	ldw	fp,32(sp)
+ 800a3a8:	ddc00717 	ldw	r23,28(sp)
+ 800a3ac:	dd800617 	ldw	r22,24(sp)
+ 800a3b0:	dd400517 	ldw	r21,20(sp)
+ 800a3b4:	dd000417 	ldw	r20,16(sp)
+ 800a3b8:	dcc00317 	ldw	r19,12(sp)
+ 800a3bc:	dc800217 	ldw	r18,8(sp)
+ 800a3c0:	dc400117 	ldw	r17,4(sp)
+ 800a3c4:	dc000017 	ldw	r16,0(sp)
+ 800a3c8:	dec00a04 	addi	sp,sp,40
+ 800a3cc:	f800283a 	ret
+ 800a3d0:	a0800217 	ldw	r2,8(r20)
+ 800a3d4:	b5ec703a 	and	r22,r22,r23
+ 800a3d8:	1585c83a 	sub	r2,r2,r22
+ 800a3dc:	a0800215 	stw	r2,8(r20)
+ 800a3e0:	ad400204 	addi	r21,r21,8
+ 800a3e4:	103fdc1e 	bne	r2,zero,800a358 <__sprint_r.part.0+0x54>
+ 800a3e8:	0005883a 	mov	r2,zero
+ 800a3ec:	003fea06 	br	800a398 <__sprint_r.part.0+0x94>
+ 800a3f0:	80074c00 	call	80074c0 <__sfvwrite_r>
+ 800a3f4:	003fe806 	br	800a398 <__sprint_r.part.0+0x94>
+
+0800a3f8 <__sprint_r>:
+ 800a3f8:	30c00217 	ldw	r3,8(r6)
+ 800a3fc:	18000126 	beq	r3,zero,800a404 <__sprint_r+0xc>
+ 800a400:	800a3041 	jmpi	800a304 <__sprint_r.part.0>
+ 800a404:	30000115 	stw	zero,4(r6)
+ 800a408:	0005883a 	mov	r2,zero
+ 800a40c:	f800283a 	ret
+
+0800a410 <___vfiprintf_internal_r>:
+ 800a410:	deffd004 	addi	sp,sp,-192
+ 800a414:	df002e15 	stw	fp,184(sp)
+ 800a418:	dcc02915 	stw	r19,164(sp)
+ 800a41c:	dc802815 	stw	r18,160(sp)
+ 800a420:	dfc02f15 	stw	ra,188(sp)
+ 800a424:	ddc02d15 	stw	r23,180(sp)
+ 800a428:	dd802c15 	stw	r22,176(sp)
+ 800a42c:	dd402b15 	stw	r21,172(sp)
+ 800a430:	dd002a15 	stw	r20,168(sp)
+ 800a434:	dc402715 	stw	r17,156(sp)
+ 800a438:	dc002615 	stw	r16,152(sp)
+ 800a43c:	d9c00315 	stw	r7,12(sp)
+ 800a440:	2027883a 	mov	r19,r4
+ 800a444:	2825883a 	mov	r18,r5
+ 800a448:	3039883a 	mov	fp,r6
+ 800a44c:	20000226 	beq	r4,zero,800a458 <___vfiprintf_internal_r+0x48>
+ 800a450:	20800e17 	ldw	r2,56(r4)
+ 800a454:	1002b626 	beq	r2,zero,800af30 <___vfiprintf_internal_r+0xb20>
+ 800a458:	9080030b 	ldhu	r2,12(r18)
+ 800a45c:	10c8000c 	andi	r3,r2,8192
+ 800a460:	1800061e 	bne	r3,zero,800a47c <___vfiprintf_internal_r+0x6c>
+ 800a464:	90c01917 	ldw	r3,100(r18)
+ 800a468:	0137ffc4 	movi	r4,-8193
+ 800a46c:	10880014 	ori	r2,r2,8192
+ 800a470:	1906703a 	and	r3,r3,r4
+ 800a474:	9080030d 	sth	r2,12(r18)
+ 800a478:	90c01915 	stw	r3,100(r18)
+ 800a47c:	10c0020c 	andi	r3,r2,8
+ 800a480:	18009426 	beq	r3,zero,800a6d4 <___vfiprintf_internal_r+0x2c4>
+ 800a484:	90c00417 	ldw	r3,16(r18)
+ 800a488:	18009226 	beq	r3,zero,800a6d4 <___vfiprintf_internal_r+0x2c4>
+ 800a48c:	1080068c 	andi	r2,r2,26
+ 800a490:	10800298 	cmpnei	r2,r2,10
+ 800a494:	10009726 	beq	r2,zero,800a6f4 <___vfiprintf_internal_r+0x2e4>
+ 800a498:	dc401604 	addi	r17,sp,88
+ 800a49c:	dc400915 	stw	r17,36(sp)
+ 800a4a0:	d8000b15 	stw	zero,44(sp)
+ 800a4a4:	d8000a15 	stw	zero,40(sp)
+ 800a4a8:	8811883a 	mov	r8,r17
+ 800a4ac:	d8000415 	stw	zero,16(sp)
+ 800a4b0:	d8000015 	stw	zero,0(sp)
+ 800a4b4:	e0800007 	ldb	r2,0(fp)
+ 800a4b8:	1000a226 	beq	r2,zero,800a744 <___vfiprintf_internal_r+0x334>
+ 800a4bc:	10800960 	cmpeqi	r2,r2,37
+ 800a4c0:	1003e71e 	bne	r2,zero,800b460 <___vfiprintf_internal_r+0x1050>
+ 800a4c4:	e021883a 	mov	r16,fp
+ 800a4c8:	00000206 	br	800a4d4 <___vfiprintf_internal_r+0xc4>
+ 800a4cc:	18009226 	beq	r3,zero,800a718 <___vfiprintf_internal_r+0x308>
+ 800a4d0:	a021883a 	mov	r16,r20
+ 800a4d4:	80800047 	ldb	r2,1(r16)
+ 800a4d8:	85000044 	addi	r20,r16,1
+ 800a4dc:	10c00958 	cmpnei	r3,r2,37
+ 800a4e0:	103ffa1e 	bne	r2,zero,800a4cc <___vfiprintf_internal_r+0xbc>
+ 800a4e4:	a72bc83a 	sub	r21,r20,fp
+ 800a4e8:	a8009626 	beq	r21,zero,800a744 <___vfiprintf_internal_r+0x334>
+ 800a4ec:	d8c00b17 	ldw	r3,44(sp)
+ 800a4f0:	d8800a17 	ldw	r2,40(sp)
+ 800a4f4:	47000015 	stw	fp,0(r8)
+ 800a4f8:	a8c7883a 	add	r3,r21,r3
+ 800a4fc:	10800044 	addi	r2,r2,1
+ 800a500:	d8800a15 	stw	r2,40(sp)
+ 800a504:	45400115 	stw	r21,4(r8)
+ 800a508:	d8c00b15 	stw	r3,44(sp)
+ 800a50c:	10800208 	cmpgei	r2,r2,8
+ 800a510:	1000841e 	bne	r2,zero,800a724 <___vfiprintf_internal_r+0x314>
+ 800a514:	42000204 	addi	r8,r8,8
+ 800a518:	d8c00017 	ldw	r3,0(sp)
+ 800a51c:	80800047 	ldb	r2,1(r16)
+ 800a520:	1d47883a 	add	r3,r3,r21
+ 800a524:	d8c00015 	stw	r3,0(sp)
+ 800a528:	10008626 	beq	r2,zero,800a744 <___vfiprintf_internal_r+0x334>
+ 800a52c:	a0800047 	ldb	r2,1(r20)
+ 800a530:	a7000044 	addi	fp,r20,1
+ 800a534:	d8000845 	stb	zero,33(sp)
+ 800a538:	000b883a 	mov	r5,zero
+ 800a53c:	000d883a 	mov	r6,zero
+ 800a540:	027fffc4 	movi	r9,-1
+ 800a544:	0021883a 	mov	r16,zero
+ 800a548:	0019883a 	mov	r12,zero
+ 800a54c:	e7000044 	addi	fp,fp,1
+ 800a550:	10fff804 	addi	r3,r2,-32
+ 800a554:	19001668 	cmpgeui	r4,r3,89
+ 800a558:	20009c1e 	bne	r4,zero,800a7cc <___vfiprintf_internal_r+0x3bc>
+ 800a55c:	180690ba 	slli	r3,r3,2
+ 800a560:	01020074 	movhi	r4,2049
+ 800a564:	1909883a 	add	r4,r3,r4
+ 800a568:	20e95c17 	ldw	r3,-23184(r4)
+ 800a56c:	1800683a 	jmp	r3
+ 800a570:	0800a89c 	xori	zero,at,674
+ 800a574:	0800a7cc 	andi	zero,at,671
+ 800a578:	0800a7cc 	andi	zero,at,671
+ 800a57c:	0800a890 	cmplti	zero,at,674
+ 800a580:	0800a7cc 	andi	zero,at,671
+ 800a584:	0800a7cc 	andi	zero,at,671
+ 800a588:	0800a7cc 	andi	zero,at,671
+ 800a58c:	0800a7cc 	andi	zero,at,671
+ 800a590:	0800a7cc 	andi	zero,at,671
+ 800a594:	0800a7cc 	andi	zero,at,671
+ 800a598:	0800a868 	cmpgeui	zero,at,673
+ 800a59c:	0800a858 	cmpnei	zero,at,673
+ 800a5a0:	0800a7cc 	andi	zero,at,671
+ 800a5a4:	0800a840 	call	800a84 <OSCtxSw_SWITCH_PC+0x800a44>
+ 800a5a8:	0800a7fc 	xorhi	zero,at,671
+ 800a5ac:	0800a7cc 	andi	zero,at,671
+ 800a5b0:	0800a7f0 	cmpltui	zero,at,671
+ 800a5b4:	0800a79c 	xori	zero,at,670
+ 800a5b8:	0800a79c 	xori	zero,at,670
+ 800a5bc:	0800a79c 	xori	zero,at,670
+ 800a5c0:	0800a79c 	xori	zero,at,670
+ 800a5c4:	0800a79c 	xori	zero,at,670
+ 800a5c8:	0800a79c 	xori	zero,at,670
+ 800a5cc:	0800a79c 	xori	zero,at,670
+ 800a5d0:	0800a79c 	xori	zero,at,670
+ 800a5d4:	0800a79c 	xori	zero,at,670
+ 800a5d8:	0800a7cc 	andi	zero,at,671
+ 800a5dc:	0800a7cc 	andi	zero,at,671
+ 800a5e0:	0800a7cc 	andi	zero,at,671
+ 800a5e4:	0800a7cc 	andi	zero,at,671
+ 800a5e8:	0800a7cc 	andi	zero,at,671
+ 800a5ec:	0800a7cc 	andi	zero,at,671
+ 800a5f0:	0800a7cc 	andi	zero,at,671
+ 800a5f4:	0800a7cc 	andi	zero,at,671
+ 800a5f8:	0800a7cc 	andi	zero,at,671
+ 800a5fc:	0800a7cc 	andi	zero,at,671
+ 800a600:	0800ae58 	cmpnei	zero,at,697
+ 800a604:	0800a7cc 	andi	zero,at,671
+ 800a608:	0800a7cc 	andi	zero,at,671
+ 800a60c:	0800a7cc 	andi	zero,at,671
+ 800a610:	0800a7cc 	andi	zero,at,671
+ 800a614:	0800a7cc 	andi	zero,at,671
+ 800a618:	0800a7cc 	andi	zero,at,671
+ 800a61c:	0800a7cc 	andi	zero,at,671
+ 800a620:	0800a7cc 	andi	zero,at,671
+ 800a624:	0800a7cc 	andi	zero,at,671
+ 800a628:	0800a7cc 	andi	zero,at,671
+ 800a62c:	0800adf0 	cmpltui	zero,at,695
+ 800a630:	0800a7cc 	andi	zero,at,671
+ 800a634:	0800a7cc 	andi	zero,at,671
+ 800a638:	0800a7cc 	andi	zero,at,671
+ 800a63c:	0800a7cc 	andi	zero,at,671
+ 800a640:	0800a7cc 	andi	zero,at,671
+ 800a644:	0800ae24 	muli	zero,at,696
+ 800a648:	0800a7cc 	andi	zero,at,671
+ 800a64c:	0800a7cc 	andi	zero,at,671
+ 800a650:	0800a9f4 	orhi	zero,at,679
+ 800a654:	0800a7cc 	andi	zero,at,671
+ 800a658:	0800a7cc 	andi	zero,at,671
+ 800a65c:	0800a7cc 	andi	zero,at,671
+ 800a660:	0800a7cc 	andi	zero,at,671
+ 800a664:	0800a7cc 	andi	zero,at,671
+ 800a668:	0800a7cc 	andi	zero,at,671
+ 800a66c:	0800a7cc 	andi	zero,at,671
+ 800a670:	0800a7cc 	andi	zero,at,671
+ 800a674:	0800a7cc 	andi	zero,at,671
+ 800a678:	0800a7cc 	andi	zero,at,671
+ 800a67c:	0800ab90 	cmplti	zero,at,686
+ 800a680:	0800ab1c 	xori	zero,at,684
+ 800a684:	0800a7cc 	andi	zero,at,671
+ 800a688:	0800a7cc 	andi	zero,at,671
+ 800a68c:	0800a7cc 	andi	zero,at,671
+ 800a690:	0800a924 	muli	zero,at,676
+ 800a694:	0800ab1c 	xori	zero,at,684
+ 800a698:	0800a7cc 	andi	zero,at,671
+ 800a69c:	0800a7cc 	andi	zero,at,671
+ 800a6a0:	0800a910 	cmplti	zero,at,676
+ 800a6a4:	0800a7cc 	andi	zero,at,671
+ 800a6a8:	0800aadc 	xori	zero,at,683
+ 800a6ac:	0800a9b4 	orhi	zero,at,678
+ 800a6b0:	0800a93c 	xorhi	zero,at,676
+ 800a6b4:	0800a930 	cmpltui	zero,at,676
+ 800a6b8:	0800a7cc 	andi	zero,at,671
+ 800a6bc:	0800aa7c 	xorhi	zero,at,681
+ 800a6c0:	0800a7cc 	andi	zero,at,671
+ 800a6c4:	0800aa3c 	xorhi	zero,at,680
+ 800a6c8:	0800a7cc 	andi	zero,at,671
+ 800a6cc:	0800a7cc 	andi	zero,at,671
+ 800a6d0:	0800a8c8 	cmpgei	zero,at,675
+ 800a6d4:	900b883a 	mov	r5,r18
+ 800a6d8:	9809883a 	mov	r4,r19
+ 800a6dc:	800507c0 	call	800507c <__swsetup_r>
+ 800a6e0:	1004071e 	bne	r2,zero,800b700 <___vfiprintf_internal_r+0x12f0>
+ 800a6e4:	9080030b 	ldhu	r2,12(r18)
+ 800a6e8:	1080068c 	andi	r2,r2,26
+ 800a6ec:	10800298 	cmpnei	r2,r2,10
+ 800a6f0:	103f691e 	bne	r2,zero,800a498 <___vfiprintf_internal_r+0x88>
+ 800a6f4:	9080038f 	ldh	r2,14(r18)
+ 800a6f8:	103f6716 	blt	r2,zero,800a498 <___vfiprintf_internal_r+0x88>
+ 800a6fc:	d9c00317 	ldw	r7,12(sp)
+ 800a700:	e00d883a 	mov	r6,fp
+ 800a704:	900b883a 	mov	r5,r18
+ 800a708:	9809883a 	mov	r4,r19
+ 800a70c:	800b7540 	call	800b754 <__sbprintf>
+ 800a710:	d8800015 	stw	r2,0(sp)
+ 800a714:	00001406 	br	800a768 <___vfiprintf_internal_r+0x358>
+ 800a718:	a72bc83a 	sub	r21,r20,fp
+ 800a71c:	a83f8326 	beq	r21,zero,800a52c <___vfiprintf_internal_r+0x11c>
+ 800a720:	003f7206 	br	800a4ec <___vfiprintf_internal_r+0xdc>
+ 800a724:	18032b26 	beq	r3,zero,800b3d4 <___vfiprintf_internal_r+0xfc4>
+ 800a728:	d9800904 	addi	r6,sp,36
+ 800a72c:	900b883a 	mov	r5,r18
+ 800a730:	9809883a 	mov	r4,r19
+ 800a734:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800a738:	1000081e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800a73c:	8811883a 	mov	r8,r17
+ 800a740:	003f7506 	br	800a518 <___vfiprintf_internal_r+0x108>
+ 800a744:	d8800b17 	ldw	r2,44(sp)
+ 800a748:	10000426 	beq	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800a74c:	d9800904 	addi	r6,sp,36
+ 800a750:	900b883a 	mov	r5,r18
+ 800a754:	9809883a 	mov	r4,r19
+ 800a758:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800a75c:	9080030b 	ldhu	r2,12(r18)
+ 800a760:	1080100c 	andi	r2,r2,64
+ 800a764:	1003e61e 	bne	r2,zero,800b700 <___vfiprintf_internal_r+0x12f0>
+ 800a768:	d8800017 	ldw	r2,0(sp)
+ 800a76c:	dfc02f17 	ldw	ra,188(sp)
+ 800a770:	df002e17 	ldw	fp,184(sp)
+ 800a774:	ddc02d17 	ldw	r23,180(sp)
+ 800a778:	dd802c17 	ldw	r22,176(sp)
+ 800a77c:	dd402b17 	ldw	r21,172(sp)
+ 800a780:	dd002a17 	ldw	r20,168(sp)
+ 800a784:	dcc02917 	ldw	r19,164(sp)
+ 800a788:	dc802817 	ldw	r18,160(sp)
+ 800a78c:	dc402717 	ldw	r17,156(sp)
+ 800a790:	dc002617 	ldw	r16,152(sp)
+ 800a794:	dec03004 	addi	sp,sp,192
+ 800a798:	f800283a 	ret
+ 800a79c:	0021883a 	mov	r16,zero
+ 800a7a0:	10fff404 	addi	r3,r2,-48
+ 800a7a4:	e7000044 	addi	fp,fp,1
+ 800a7a8:	840002a4 	muli	r16,r16,10
+ 800a7ac:	e0bfffc7 	ldb	r2,-1(fp)
+ 800a7b0:	1c21883a 	add	r16,r3,r16
+ 800a7b4:	10fff404 	addi	r3,r2,-48
+ 800a7b8:	190002b0 	cmpltui	r4,r3,10
+ 800a7bc:	203ff91e 	bne	r4,zero,800a7a4 <___vfiprintf_internal_r+0x394>
+ 800a7c0:	10fff804 	addi	r3,r2,-32
+ 800a7c4:	19001668 	cmpgeui	r4,r3,89
+ 800a7c8:	203f6426 	beq	r4,zero,800a55c <___vfiprintf_internal_r+0x14c>
+ 800a7cc:	29403fcc 	andi	r5,r5,255
+ 800a7d0:	2803a91e 	bne	r5,zero,800b678 <___vfiprintf_internal_r+0x1268>
+ 800a7d4:	103fdb26 	beq	r2,zero,800a744 <___vfiprintf_internal_r+0x334>
+ 800a7d8:	d8800c05 	stb	r2,48(sp)
+ 800a7dc:	d8000845 	stb	zero,33(sp)
+ 800a7e0:	05400044 	movi	r21,1
+ 800a7e4:	05800044 	movi	r22,1
+ 800a7e8:	ddc00c04 	addi	r23,sp,48
+ 800a7ec:	0000f106 	br	800abb4 <___vfiprintf_internal_r+0x7a4>
+ 800a7f0:	63002014 	ori	r12,r12,128
+ 800a7f4:	e0800007 	ldb	r2,0(fp)
+ 800a7f8:	003f5406 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a7fc:	e0800007 	ldb	r2,0(fp)
+ 800a800:	e1000044 	addi	r4,fp,1
+ 800a804:	10c00aa0 	cmpeqi	r3,r2,42
+ 800a808:	1803c01e 	bne	r3,zero,800b70c <___vfiprintf_internal_r+0x12fc>
+ 800a80c:	10fff404 	addi	r3,r2,-48
+ 800a810:	19c002b0 	cmpltui	r7,r3,10
+ 800a814:	2039883a 	mov	fp,r4
+ 800a818:	0013883a 	mov	r9,zero
+ 800a81c:	383f4c26 	beq	r7,zero,800a550 <___vfiprintf_internal_r+0x140>
+ 800a820:	e7000044 	addi	fp,fp,1
+ 800a824:	4a4002a4 	muli	r9,r9,10
+ 800a828:	e0bfffc7 	ldb	r2,-1(fp)
+ 800a82c:	48d3883a 	add	r9,r9,r3
+ 800a830:	10fff404 	addi	r3,r2,-48
+ 800a834:	190002b0 	cmpltui	r4,r3,10
+ 800a838:	203ff91e 	bne	r4,zero,800a820 <___vfiprintf_internal_r+0x410>
+ 800a83c:	003f4406 	br	800a550 <___vfiprintf_internal_r+0x140>
+ 800a840:	e0800003 	ldbu	r2,0(fp)
+ 800a844:	10803fcc 	andi	r2,r2,255
+ 800a848:	1080201c 	xori	r2,r2,128
+ 800a84c:	63000114 	ori	r12,r12,4
+ 800a850:	10bfe004 	addi	r2,r2,-128
+ 800a854:	003f3d06 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a858:	01400044 	movi	r5,1
+ 800a85c:	01800ac4 	movi	r6,43
+ 800a860:	e0800007 	ldb	r2,0(fp)
+ 800a864:	003f3906 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a868:	d8800317 	ldw	r2,12(sp)
+ 800a86c:	14000017 	ldw	r16,0(r2)
+ 800a870:	15c00104 	addi	r23,r2,4
+ 800a874:	e0800003 	ldbu	r2,0(fp)
+ 800a878:	80031416 	blt	r16,zero,800b4cc <___vfiprintf_internal_r+0x10bc>
+ 800a87c:	ddc00315 	stw	r23,12(sp)
+ 800a880:	10803fcc 	andi	r2,r2,255
+ 800a884:	1080201c 	xori	r2,r2,128
+ 800a888:	10bfe004 	addi	r2,r2,-128
+ 800a88c:	003f2f06 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a890:	63000054 	ori	r12,r12,1
+ 800a894:	e0800007 	ldb	r2,0(fp)
+ 800a898:	003f2c06 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a89c:	30c03fcc 	andi	r3,r6,255
+ 800a8a0:	18c0201c 	xori	r3,r3,128
+ 800a8a4:	18ffe004 	addi	r3,r3,-128
+ 800a8a8:	e0800003 	ldbu	r2,0(fp)
+ 800a8ac:	183ff41e 	bne	r3,zero,800a880 <___vfiprintf_internal_r+0x470>
+ 800a8b0:	10803fcc 	andi	r2,r2,255
+ 800a8b4:	1080201c 	xori	r2,r2,128
+ 800a8b8:	01400044 	movi	r5,1
+ 800a8bc:	01800804 	movi	r6,32
+ 800a8c0:	10bfe004 	addi	r2,r2,-128
+ 800a8c4:	003f2106 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a8c8:	29403fcc 	andi	r5,r5,255
+ 800a8cc:	2803741e 	bne	r5,zero,800b6a0 <___vfiprintf_internal_r+0x1290>
+ 800a8d0:	00c20134 	movhi	r3,2052
+ 800a8d4:	18dd2004 	addi	r3,r3,29824
+ 800a8d8:	d8c00415 	stw	r3,16(sp)
+ 800a8dc:	60c0080c 	andi	r3,r12,32
+ 800a8e0:	18004b26 	beq	r3,zero,800aa10 <___vfiprintf_internal_r+0x600>
+ 800a8e4:	d8c00317 	ldw	r3,12(sp)
+ 800a8e8:	1d400017 	ldw	r21,0(r3)
+ 800a8ec:	1d800117 	ldw	r22,4(r3)
+ 800a8f0:	18c00204 	addi	r3,r3,8
+ 800a8f4:	d8c00315 	stw	r3,12(sp)
+ 800a8f8:	60c0004c 	andi	r3,r12,1
+ 800a8fc:	18000226 	beq	r3,zero,800a908 <___vfiprintf_internal_r+0x4f8>
+ 800a900:	ad86b03a 	or	r3,r21,r22
+ 800a904:	1802df1e 	bne	r3,zero,800b484 <___vfiprintf_internal_r+0x1074>
+ 800a908:	00800084 	movi	r2,2
+ 800a90c:	00001906 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800a910:	e0800007 	ldb	r2,0(fp)
+ 800a914:	10c01b18 	cmpnei	r3,r2,108
+ 800a918:	18033026 	beq	r3,zero,800b5dc <___vfiprintf_internal_r+0x11cc>
+ 800a91c:	63000414 	ori	r12,r12,16
+ 800a920:	003f0a06 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a924:	63001014 	ori	r12,r12,64
+ 800a928:	e0800007 	ldb	r2,0(fp)
+ 800a92c:	003f0706 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a930:	63000814 	ori	r12,r12,32
+ 800a934:	e0800007 	ldb	r2,0(fp)
+ 800a938:	003f0406 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800a93c:	d8c00317 	ldw	r3,12(sp)
+ 800a940:	00800c04 	movi	r2,48
+ 800a944:	d8800885 	stb	r2,34(sp)
+ 800a948:	00801e04 	movi	r2,120
+ 800a94c:	01020134 	movhi	r4,2052
+ 800a950:	d88008c5 	stb	r2,35(sp)
+ 800a954:	1d400017 	ldw	r21,0(r3)
+ 800a958:	18800104 	addi	r2,r3,4
+ 800a95c:	d8800315 	stw	r2,12(sp)
+ 800a960:	209d2004 	addi	r2,r4,29824
+ 800a964:	d8800415 	stw	r2,16(sp)
+ 800a968:	002d883a 	mov	r22,zero
+ 800a96c:	63000094 	ori	r12,r12,2
+ 800a970:	00800084 	movi	r2,2
+ 800a974:	d8000845 	stb	zero,33(sp)
+ 800a978:	48ffffe0 	cmpeqi	r3,r9,-1
+ 800a97c:	001b883a 	mov	r13,zero
+ 800a980:	18014c1e 	bne	r3,zero,800aeb4 <___vfiprintf_internal_r+0xaa4>
+ 800a984:	053fdfc4 	movi	r20,-129
+ 800a988:	ad86b03a 	or	r3,r21,r22
+ 800a98c:	6528703a 	and	r20,r12,r20
+ 800a990:	1802411e 	bne	r3,zero,800b298 <___vfiprintf_internal_r+0xe88>
+ 800a994:	48030d1e 	bne	r9,zero,800b5cc <___vfiprintf_internal_r+0x11bc>
+ 800a998:	1000791e 	bne	r2,zero,800ab80 <___vfiprintf_internal_r+0x770>
+ 800a99c:	6580004c 	andi	r22,r12,1
+ 800a9a0:	b002b126 	beq	r22,zero,800b468 <___vfiprintf_internal_r+0x1058>
+ 800a9a4:	00800c04 	movi	r2,48
+ 800a9a8:	d88015c5 	stb	r2,87(sp)
+ 800a9ac:	ddc015c4 	addi	r23,sp,87
+ 800a9b0:	00017e06 	br	800afac <___vfiprintf_internal_r+0xb9c>
+ 800a9b4:	29403fcc 	andi	r5,r5,255
+ 800a9b8:	2803461e 	bne	r5,zero,800b6d4 <___vfiprintf_internal_r+0x12c4>
+ 800a9bc:	6080080c 	andi	r2,r12,32
+ 800a9c0:	10016b1e 	bne	r2,zero,800af70 <___vfiprintf_internal_r+0xb60>
+ 800a9c4:	d8800317 	ldw	r2,12(sp)
+ 800a9c8:	60c0040c 	andi	r3,r12,16
+ 800a9cc:	15400017 	ldw	r21,0(r2)
+ 800a9d0:	10800104 	addi	r2,r2,4
+ 800a9d4:	18010d1e 	bne	r3,zero,800ae0c <___vfiprintf_internal_r+0x9fc>
+ 800a9d8:	60c0100c 	andi	r3,r12,64
+ 800a9dc:	18031326 	beq	r3,zero,800b62c <___vfiprintf_internal_r+0x121c>
+ 800a9e0:	d8800315 	stw	r2,12(sp)
+ 800a9e4:	ad7fffcc 	andi	r21,r21,65535
+ 800a9e8:	002d883a 	mov	r22,zero
+ 800a9ec:	0005883a 	mov	r2,zero
+ 800a9f0:	003fe006 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800a9f4:	29403fcc 	andi	r5,r5,255
+ 800a9f8:	2803251e 	bne	r5,zero,800b690 <___vfiprintf_internal_r+0x1280>
+ 800a9fc:	00c20134 	movhi	r3,2052
+ 800aa00:	18dd1b04 	addi	r3,r3,29804
+ 800aa04:	d8c00415 	stw	r3,16(sp)
+ 800aa08:	60c0080c 	andi	r3,r12,32
+ 800aa0c:	183fb51e 	bne	r3,zero,800a8e4 <___vfiprintf_internal_r+0x4d4>
+ 800aa10:	d9000317 	ldw	r4,12(sp)
+ 800aa14:	60c0040c 	andi	r3,r12,16
+ 800aa18:	25400017 	ldw	r21,0(r4)
+ 800aa1c:	21000104 	addi	r4,r4,4
+ 800aa20:	d9000315 	stw	r4,12(sp)
+ 800aa24:	18026e1e 	bne	r3,zero,800b3e0 <___vfiprintf_internal_r+0xfd0>
+ 800aa28:	60c0100c 	andi	r3,r12,64
+ 800aa2c:	18026c26 	beq	r3,zero,800b3e0 <___vfiprintf_internal_r+0xfd0>
+ 800aa30:	ad7fffcc 	andi	r21,r21,65535
+ 800aa34:	002d883a 	mov	r22,zero
+ 800aa38:	003faf06 	br	800a8f8 <___vfiprintf_internal_r+0x4e8>
+ 800aa3c:	29403fcc 	andi	r5,r5,255
+ 800aa40:	2803151e 	bne	r5,zero,800b698 <___vfiprintf_internal_r+0x1288>
+ 800aa44:	6080080c 	andi	r2,r12,32
+ 800aa48:	10013b1e 	bne	r2,zero,800af38 <___vfiprintf_internal_r+0xb28>
+ 800aa4c:	d8800317 	ldw	r2,12(sp)
+ 800aa50:	60c0040c 	andi	r3,r12,16
+ 800aa54:	15400017 	ldw	r21,0(r2)
+ 800aa58:	10800104 	addi	r2,r2,4
+ 800aa5c:	1800f81e 	bne	r3,zero,800ae40 <___vfiprintf_internal_r+0xa30>
+ 800aa60:	60c0100c 	andi	r3,r12,64
+ 800aa64:	1802ed26 	beq	r3,zero,800b61c <___vfiprintf_internal_r+0x120c>
+ 800aa68:	d8800315 	stw	r2,12(sp)
+ 800aa6c:	ad7fffcc 	andi	r21,r21,65535
+ 800aa70:	002d883a 	mov	r22,zero
+ 800aa74:	00800044 	movi	r2,1
+ 800aa78:	003fbe06 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800aa7c:	d8800317 	ldw	r2,12(sp)
+ 800aa80:	d8000845 	stb	zero,33(sp)
+ 800aa84:	15c00017 	ldw	r23,0(r2)
+ 800aa88:	15000104 	addi	r20,r2,4
+ 800aa8c:	b802da26 	beq	r23,zero,800b5f8 <___vfiprintf_internal_r+0x11e8>
+ 800aa90:	48bfffe0 	cmpeqi	r2,r9,-1
+ 800aa94:	1002901e 	bne	r2,zero,800b4d8 <___vfiprintf_internal_r+0x10c8>
+ 800aa98:	480d883a 	mov	r6,r9
+ 800aa9c:	000b883a 	mov	r5,zero
+ 800aaa0:	b809883a 	mov	r4,r23
+ 800aaa4:	da000315 	stw	r8,12(sp)
+ 800aaa8:	db000215 	stw	r12,8(sp)
+ 800aaac:	da400115 	stw	r9,4(sp)
+ 800aab0:	80085d00 	call	80085d0 <memchr>
+ 800aab4:	da400117 	ldw	r9,4(sp)
+ 800aab8:	db000217 	ldw	r12,8(sp)
+ 800aabc:	da000317 	ldw	r8,12(sp)
+ 800aac0:	1002ef26 	beq	r2,zero,800b680 <___vfiprintf_internal_r+0x1270>
+ 800aac4:	15edc83a 	sub	r22,r2,r23
+ 800aac8:	b02b883a 	mov	r21,r22
+ 800aacc:	b000010e 	bge	r22,zero,800aad4 <___vfiprintf_internal_r+0x6c4>
+ 800aad0:	002b883a 	mov	r21,zero
+ 800aad4:	dd000315 	stw	r20,12(sp)
+ 800aad8:	00003606 	br	800abb4 <___vfiprintf_internal_r+0x7a4>
+ 800aadc:	29403fcc 	andi	r5,r5,255
+ 800aae0:	2802fa1e 	bne	r5,zero,800b6cc <___vfiprintf_internal_r+0x12bc>
+ 800aae4:	d9000317 	ldw	r4,12(sp)
+ 800aae8:	6080080c 	andi	r2,r12,32
+ 800aaec:	20c00104 	addi	r3,r4,4
+ 800aaf0:	10026a1e 	bne	r2,zero,800b49c <___vfiprintf_internal_r+0x108c>
+ 800aaf4:	6080040c 	andi	r2,r12,16
+ 800aaf8:	1002891e 	bne	r2,zero,800b520 <___vfiprintf_internal_r+0x1110>
+ 800aafc:	6300100c 	andi	r12,r12,64
+ 800ab00:	60028726 	beq	r12,zero,800b520 <___vfiprintf_internal_r+0x1110>
+ 800ab04:	d8800317 	ldw	r2,12(sp)
+ 800ab08:	d8c00315 	stw	r3,12(sp)
+ 800ab0c:	d8c00017 	ldw	r3,0(sp)
+ 800ab10:	10800017 	ldw	r2,0(r2)
+ 800ab14:	10c0000d 	sth	r3,0(r2)
+ 800ab18:	003e6606 	br	800a4b4 <___vfiprintf_internal_r+0xa4>
+ 800ab1c:	29403fcc 	andi	r5,r5,255
+ 800ab20:	2802e81e 	bne	r5,zero,800b6c4 <___vfiprintf_internal_r+0x12b4>
+ 800ab24:	6080080c 	andi	r2,r12,32
+ 800ab28:	10010a1e 	bne	r2,zero,800af54 <___vfiprintf_internal_r+0xb44>
+ 800ab2c:	d8800317 	ldw	r2,12(sp)
+ 800ab30:	60c0040c 	andi	r3,r12,16
+ 800ab34:	10800104 	addi	r2,r2,4
+ 800ab38:	1800ce1e 	bne	r3,zero,800ae74 <___vfiprintf_internal_r+0xa64>
+ 800ab3c:	60c0100c 	andi	r3,r12,64
+ 800ab40:	1800cc26 	beq	r3,zero,800ae74 <___vfiprintf_internal_r+0xa64>
+ 800ab44:	d8c00317 	ldw	r3,12(sp)
+ 800ab48:	d8800315 	stw	r2,12(sp)
+ 800ab4c:	1d40000f 	ldh	r21,0(r3)
+ 800ab50:	a82dd7fa 	srai	r22,r21,31
+ 800ab54:	b005883a 	mov	r2,r22
+ 800ab58:	1000cc16 	blt	r2,zero,800ae8c <___vfiprintf_internal_r+0xa7c>
+ 800ab5c:	48bfffd8 	cmpnei	r2,r9,-1
+ 800ab60:	db400843 	ldbu	r13,33(sp)
+ 800ab64:	10010926 	beq	r2,zero,800af8c <___vfiprintf_internal_r+0xb7c>
+ 800ab68:	00ffdfc4 	movi	r3,-129
+ 800ab6c:	ad84b03a 	or	r2,r21,r22
+ 800ab70:	60d8703a 	and	r12,r12,r3
+ 800ab74:	1001051e 	bne	r2,zero,800af8c <___vfiprintf_internal_r+0xb7c>
+ 800ab78:	4801071e 	bne	r9,zero,800af98 <___vfiprintf_internal_r+0xb88>
+ 800ab7c:	6029883a 	mov	r20,r12
+ 800ab80:	0013883a 	mov	r9,zero
+ 800ab84:	002d883a 	mov	r22,zero
+ 800ab88:	882f883a 	mov	r23,r17
+ 800ab8c:	00010706 	br	800afac <___vfiprintf_internal_r+0xb9c>
+ 800ab90:	d8c00317 	ldw	r3,12(sp)
+ 800ab94:	d8000845 	stb	zero,33(sp)
+ 800ab98:	05400044 	movi	r21,1
+ 800ab9c:	18800017 	ldw	r2,0(r3)
+ 800aba0:	18c00104 	addi	r3,r3,4
+ 800aba4:	d8c00315 	stw	r3,12(sp)
+ 800aba8:	d8800c05 	stb	r2,48(sp)
+ 800abac:	05800044 	movi	r22,1
+ 800abb0:	ddc00c04 	addi	r23,sp,48
+ 800abb4:	6029883a 	mov	r20,r12
+ 800abb8:	0013883a 	mov	r9,zero
+ 800abbc:	a340008c 	andi	r13,r20,2
+ 800abc0:	68000126 	beq	r13,zero,800abc8 <___vfiprintf_internal_r+0x7b8>
+ 800abc4:	ad400084 	addi	r21,r21,2
+ 800abc8:	d9000a17 	ldw	r4,40(sp)
+ 800abcc:	a300210c 	andi	r12,r20,132
+ 800abd0:	d8800b17 	ldw	r2,44(sp)
+ 800abd4:	21800044 	addi	r6,r4,1
+ 800abd8:	300b883a 	mov	r5,r6
+ 800abdc:	6000021e 	bne	r12,zero,800abe8 <___vfiprintf_internal_r+0x7d8>
+ 800abe0:	8547c83a 	sub	r3,r16,r21
+ 800abe4:	00c1ae16 	blt	zero,r3,800b2a0 <___vfiprintf_internal_r+0xe90>
+ 800abe8:	d9800847 	ldb	r6,33(sp)
+ 800abec:	40c00204 	addi	r3,r8,8
+ 800abf0:	30000d26 	beq	r6,zero,800ac28 <___vfiprintf_internal_r+0x818>
+ 800abf4:	d9000844 	addi	r4,sp,33
+ 800abf8:	10800044 	addi	r2,r2,1
+ 800abfc:	41000015 	stw	r4,0(r8)
+ 800ac00:	01000044 	movi	r4,1
+ 800ac04:	41000115 	stw	r4,4(r8)
+ 800ac08:	d8800b15 	stw	r2,44(sp)
+ 800ac0c:	d9400a15 	stw	r5,40(sp)
+ 800ac10:	29000208 	cmpgei	r4,r5,8
+ 800ac14:	2001831e 	bne	r4,zero,800b224 <___vfiprintf_internal_r+0xe14>
+ 800ac18:	2809883a 	mov	r4,r5
+ 800ac1c:	1811883a 	mov	r8,r3
+ 800ac20:	29400044 	addi	r5,r5,1
+ 800ac24:	18c00204 	addi	r3,r3,8
+ 800ac28:	68001826 	beq	r13,zero,800ac8c <___vfiprintf_internal_r+0x87c>
+ 800ac2c:	d9000884 	addi	r4,sp,34
+ 800ac30:	10800084 	addi	r2,r2,2
+ 800ac34:	41000015 	stw	r4,0(r8)
+ 800ac38:	01000084 	movi	r4,2
+ 800ac3c:	41000115 	stw	r4,4(r8)
+ 800ac40:	d8800b15 	stw	r2,44(sp)
+ 800ac44:	d9400a15 	stw	r5,40(sp)
+ 800ac48:	29000208 	cmpgei	r4,r5,8
+ 800ac4c:	20018d26 	beq	r4,zero,800b284 <___vfiprintf_internal_r+0xe74>
+ 800ac50:	1001ed26 	beq	r2,zero,800b408 <___vfiprintf_internal_r+0xff8>
+ 800ac54:	d9800904 	addi	r6,sp,36
+ 800ac58:	900b883a 	mov	r5,r18
+ 800ac5c:	9809883a 	mov	r4,r19
+ 800ac60:	da400215 	stw	r9,8(sp)
+ 800ac64:	db000115 	stw	r12,4(sp)
+ 800ac68:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800ac6c:	103ebb1e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800ac70:	d9000a17 	ldw	r4,40(sp)
+ 800ac74:	d8800b17 	ldw	r2,44(sp)
+ 800ac78:	da400217 	ldw	r9,8(sp)
+ 800ac7c:	db000117 	ldw	r12,4(sp)
+ 800ac80:	d8c01804 	addi	r3,sp,96
+ 800ac84:	21400044 	addi	r5,r4,1
+ 800ac88:	8811883a 	mov	r8,r17
+ 800ac8c:	63002018 	cmpnei	r12,r12,128
+ 800ac90:	6000e326 	beq	r12,zero,800b020 <___vfiprintf_internal_r+0xc10>
+ 800ac94:	4d93c83a 	sub	r9,r9,r22
+ 800ac98:	02412216 	blt	zero,r9,800b124 <___vfiprintf_internal_r+0xd14>
+ 800ac9c:	b085883a 	add	r2,r22,r2
+ 800aca0:	d9400a15 	stw	r5,40(sp)
+ 800aca4:	45c00015 	stw	r23,0(r8)
+ 800aca8:	45800115 	stw	r22,4(r8)
+ 800acac:	d8800b15 	stw	r2,44(sp)
+ 800acb0:	29400210 	cmplti	r5,r5,8
+ 800acb4:	2800081e 	bne	r5,zero,800acd8 <___vfiprintf_internal_r+0x8c8>
+ 800acb8:	10001426 	beq	r2,zero,800ad0c <___vfiprintf_internal_r+0x8fc>
+ 800acbc:	d9800904 	addi	r6,sp,36
+ 800acc0:	900b883a 	mov	r5,r18
+ 800acc4:	9809883a 	mov	r4,r19
+ 800acc8:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800accc:	103ea31e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800acd0:	d8800b17 	ldw	r2,44(sp)
+ 800acd4:	8807883a 	mov	r3,r17
+ 800acd8:	a500010c 	andi	r20,r20,4
+ 800acdc:	a0000226 	beq	r20,zero,800ace8 <___vfiprintf_internal_r+0x8d8>
+ 800ace0:	8569c83a 	sub	r20,r16,r21
+ 800ace4:	05000f16 	blt	zero,r20,800ad24 <___vfiprintf_internal_r+0x914>
+ 800ace8:	8540010e 	bge	r16,r21,800acf0 <___vfiprintf_internal_r+0x8e0>
+ 800acec:	a821883a 	mov	r16,r21
+ 800acf0:	d8c00017 	ldw	r3,0(sp)
+ 800acf4:	1c07883a 	add	r3,r3,r16
+ 800acf8:	d8c00015 	stw	r3,0(sp)
+ 800acfc:	10013f1e 	bne	r2,zero,800b1fc <___vfiprintf_internal_r+0xdec>
+ 800ad00:	d8000a15 	stw	zero,40(sp)
+ 800ad04:	8811883a 	mov	r8,r17
+ 800ad08:	003dea06 	br	800a4b4 <___vfiprintf_internal_r+0xa4>
+ 800ad0c:	d8000a15 	stw	zero,40(sp)
+ 800ad10:	a500010c 	andi	r20,r20,4
+ 800ad14:	a0019d26 	beq	r20,zero,800b38c <___vfiprintf_internal_r+0xf7c>
+ 800ad18:	8569c83a 	sub	r20,r16,r21
+ 800ad1c:	05019b0e 	bge	zero,r20,800b38c <___vfiprintf_internal_r+0xf7c>
+ 800ad20:	8807883a 	mov	r3,r17
+ 800ad24:	a1000450 	cmplti	r4,r20,17
+ 800ad28:	01c20134 	movhi	r7,2052
+ 800ad2c:	d9400a17 	ldw	r5,40(sp)
+ 800ad30:	20026c1e 	bne	r4,zero,800b6e4 <___vfiprintf_internal_r+0x12d4>
+ 800ad34:	39dd8104 	addi	r7,r7,30212
+ 800ad38:	05800404 	movi	r22,16
+ 800ad3c:	00000606 	br	800ad58 <___vfiprintf_internal_r+0x948>
+ 800ad40:	29800084 	addi	r6,r5,2
+ 800ad44:	18c00204 	addi	r3,r3,8
+ 800ad48:	200b883a 	mov	r5,r4
+ 800ad4c:	a53ffc04 	addi	r20,r20,-16
+ 800ad50:	a1000448 	cmpgei	r4,r20,17
+ 800ad54:	20001726 	beq	r4,zero,800adb4 <___vfiprintf_internal_r+0x9a4>
+ 800ad58:	29000044 	addi	r4,r5,1
+ 800ad5c:	10800404 	addi	r2,r2,16
+ 800ad60:	19c00015 	stw	r7,0(r3)
+ 800ad64:	1d800115 	stw	r22,4(r3)
+ 800ad68:	d8800b15 	stw	r2,44(sp)
+ 800ad6c:	d9000a15 	stw	r4,40(sp)
+ 800ad70:	21800208 	cmpgei	r6,r4,8
+ 800ad74:	303ff226 	beq	r6,zero,800ad40 <___vfiprintf_internal_r+0x930>
+ 800ad78:	d9800904 	addi	r6,sp,36
+ 800ad7c:	900b883a 	mov	r5,r18
+ 800ad80:	9809883a 	mov	r4,r19
+ 800ad84:	1000a226 	beq	r2,zero,800b010 <___vfiprintf_internal_r+0xc00>
+ 800ad88:	d9c00115 	stw	r7,4(sp)
+ 800ad8c:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800ad90:	103e721e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800ad94:	d9400a17 	ldw	r5,40(sp)
+ 800ad98:	a53ffc04 	addi	r20,r20,-16
+ 800ad9c:	a1000448 	cmpgei	r4,r20,17
+ 800ada0:	d8800b17 	ldw	r2,44(sp)
+ 800ada4:	8807883a 	mov	r3,r17
+ 800ada8:	29800044 	addi	r6,r5,1
+ 800adac:	d9c00117 	ldw	r7,4(sp)
+ 800adb0:	203fe91e 	bne	r4,zero,800ad58 <___vfiprintf_internal_r+0x948>
+ 800adb4:	1505883a 	add	r2,r2,r20
+ 800adb8:	d9800a15 	stw	r6,40(sp)
+ 800adbc:	19c00015 	stw	r7,0(r3)
+ 800adc0:	1d000115 	stw	r20,4(r3)
+ 800adc4:	d8800b15 	stw	r2,44(sp)
+ 800adc8:	31800210 	cmplti	r6,r6,8
+ 800adcc:	303fc61e 	bne	r6,zero,800ace8 <___vfiprintf_internal_r+0x8d8>
+ 800add0:	10016e26 	beq	r2,zero,800b38c <___vfiprintf_internal_r+0xf7c>
+ 800add4:	d9800904 	addi	r6,sp,36
+ 800add8:	900b883a 	mov	r5,r18
+ 800addc:	9809883a 	mov	r4,r19
+ 800ade0:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800ade4:	103e5d1e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800ade8:	d8800b17 	ldw	r2,44(sp)
+ 800adec:	003fbe06 	br	800ace8 <___vfiprintf_internal_r+0x8d8>
+ 800adf0:	29403fcc 	andi	r5,r5,255
+ 800adf4:	28022c1e 	bne	r5,zero,800b6a8 <___vfiprintf_internal_r+0x1298>
+ 800adf8:	6080080c 	andi	r2,r12,32
+ 800adfc:	63000414 	ori	r12,r12,16
+ 800ae00:	10005b1e 	bne	r2,zero,800af70 <___vfiprintf_internal_r+0xb60>
+ 800ae04:	d8800317 	ldw	r2,12(sp)
+ 800ae08:	10800104 	addi	r2,r2,4
+ 800ae0c:	d8c00317 	ldw	r3,12(sp)
+ 800ae10:	002d883a 	mov	r22,zero
+ 800ae14:	d8800315 	stw	r2,12(sp)
+ 800ae18:	1d400017 	ldw	r21,0(r3)
+ 800ae1c:	0005883a 	mov	r2,zero
+ 800ae20:	003ed406 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800ae24:	29403fcc 	andi	r5,r5,255
+ 800ae28:	2802211e 	bne	r5,zero,800b6b0 <___vfiprintf_internal_r+0x12a0>
+ 800ae2c:	6080080c 	andi	r2,r12,32
+ 800ae30:	63000414 	ori	r12,r12,16
+ 800ae34:	1000401e 	bne	r2,zero,800af38 <___vfiprintf_internal_r+0xb28>
+ 800ae38:	d8800317 	ldw	r2,12(sp)
+ 800ae3c:	10800104 	addi	r2,r2,4
+ 800ae40:	d8c00317 	ldw	r3,12(sp)
+ 800ae44:	002d883a 	mov	r22,zero
+ 800ae48:	d8800315 	stw	r2,12(sp)
+ 800ae4c:	1d400017 	ldw	r21,0(r3)
+ 800ae50:	00800044 	movi	r2,1
+ 800ae54:	003ec706 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800ae58:	29403fcc 	andi	r5,r5,255
+ 800ae5c:	28021f1e 	bne	r5,zero,800b6dc <___vfiprintf_internal_r+0x12cc>
+ 800ae60:	6080080c 	andi	r2,r12,32
+ 800ae64:	63000414 	ori	r12,r12,16
+ 800ae68:	10003a1e 	bne	r2,zero,800af54 <___vfiprintf_internal_r+0xb44>
+ 800ae6c:	d8800317 	ldw	r2,12(sp)
+ 800ae70:	10800104 	addi	r2,r2,4
+ 800ae74:	d8c00317 	ldw	r3,12(sp)
+ 800ae78:	1d400017 	ldw	r21,0(r3)
+ 800ae7c:	d8800315 	stw	r2,12(sp)
+ 800ae80:	a82dd7fa 	srai	r22,r21,31
+ 800ae84:	b005883a 	mov	r2,r22
+ 800ae88:	103f340e 	bge	r2,zero,800ab5c <___vfiprintf_internal_r+0x74c>
+ 800ae8c:	056bc83a 	sub	r21,zero,r21
+ 800ae90:	a804c03a 	cmpne	r2,r21,zero
+ 800ae94:	05adc83a 	sub	r22,zero,r22
+ 800ae98:	b0adc83a 	sub	r22,r22,r2
+ 800ae9c:	00800b44 	movi	r2,45
+ 800aea0:	d8800845 	stb	r2,33(sp)
+ 800aea4:	48ffffe0 	cmpeqi	r3,r9,-1
+ 800aea8:	03400b44 	movi	r13,45
+ 800aeac:	00800044 	movi	r2,1
+ 800aeb0:	183eb426 	beq	r3,zero,800a984 <___vfiprintf_internal_r+0x574>
+ 800aeb4:	10c00060 	cmpeqi	r3,r2,1
+ 800aeb8:	1800341e 	bne	r3,zero,800af8c <___vfiprintf_internal_r+0xb7c>
+ 800aebc:	108000a0 	cmpeqi	r2,r2,2
+ 800aec0:	1000431e 	bne	r2,zero,800afd0 <___vfiprintf_internal_r+0xbc0>
+ 800aec4:	8807883a 	mov	r3,r17
+ 800aec8:	00000106 	br	800aed0 <___vfiprintf_internal_r+0xac0>
+ 800aecc:	b807883a 	mov	r3,r23
+ 800aed0:	a808d0fa 	srli	r4,r21,3
+ 800aed4:	b00a977a 	slli	r5,r22,29
+ 800aed8:	b02cd0fa 	srli	r22,r22,3
+ 800aedc:	ad4001cc 	andi	r21,r21,7
+ 800aee0:	a8800c04 	addi	r2,r21,48
+ 800aee4:	292ab03a 	or	r21,r5,r4
+ 800aee8:	18bfffc5 	stb	r2,-1(r3)
+ 800aeec:	ad88b03a 	or	r4,r21,r22
+ 800aef0:	1dffffc4 	addi	r23,r3,-1
+ 800aef4:	203ff51e 	bne	r4,zero,800aecc <___vfiprintf_internal_r+0xabc>
+ 800aef8:	6100004c 	andi	r4,r12,1
+ 800aefc:	20004126 	beq	r4,zero,800b004 <___vfiprintf_internal_r+0xbf4>
+ 800af00:	10803fcc 	andi	r2,r2,255
+ 800af04:	1080201c 	xori	r2,r2,128
+ 800af08:	10bfe004 	addi	r2,r2,-128
+ 800af0c:	10800c18 	cmpnei	r2,r2,48
+ 800af10:	10003c26 	beq	r2,zero,800b004 <___vfiprintf_internal_r+0xbf4>
+ 800af14:	18ffff84 	addi	r3,r3,-2
+ 800af18:	00800c04 	movi	r2,48
+ 800af1c:	b8bfffc5 	stb	r2,-1(r23)
+ 800af20:	88edc83a 	sub	r22,r17,r3
+ 800af24:	6029883a 	mov	r20,r12
+ 800af28:	182f883a 	mov	r23,r3
+ 800af2c:	00001f06 	br	800afac <___vfiprintf_internal_r+0xb9c>
+ 800af30:	80070600 	call	8007060 <__sinit>
+ 800af34:	003d4806 	br	800a458 <___vfiprintf_internal_r+0x48>
+ 800af38:	d8c00317 	ldw	r3,12(sp)
+ 800af3c:	00800044 	movi	r2,1
+ 800af40:	1d400017 	ldw	r21,0(r3)
+ 800af44:	1d800117 	ldw	r22,4(r3)
+ 800af48:	18c00204 	addi	r3,r3,8
+ 800af4c:	d8c00315 	stw	r3,12(sp)
+ 800af50:	003e8806 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800af54:	d8c00317 	ldw	r3,12(sp)
+ 800af58:	18800117 	ldw	r2,4(r3)
+ 800af5c:	1d400017 	ldw	r21,0(r3)
+ 800af60:	18c00204 	addi	r3,r3,8
+ 800af64:	d8c00315 	stw	r3,12(sp)
+ 800af68:	102d883a 	mov	r22,r2
+ 800af6c:	003efa06 	br	800ab58 <___vfiprintf_internal_r+0x748>
+ 800af70:	d8c00317 	ldw	r3,12(sp)
+ 800af74:	0005883a 	mov	r2,zero
+ 800af78:	1d400017 	ldw	r21,0(r3)
+ 800af7c:	1d800117 	ldw	r22,4(r3)
+ 800af80:	18c00204 	addi	r3,r3,8
+ 800af84:	d8c00315 	stw	r3,12(sp)
+ 800af88:	003e7a06 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800af8c:	b0016a1e 	bne	r22,zero,800b538 <___vfiprintf_internal_r+0x1128>
+ 800af90:	a88002a8 	cmpgeui	r2,r21,10
+ 800af94:	1001681e 	bne	r2,zero,800b538 <___vfiprintf_internal_r+0x1128>
+ 800af98:	ad400c04 	addi	r21,r21,48
+ 800af9c:	dd4015c5 	stb	r21,87(sp)
+ 800afa0:	6029883a 	mov	r20,r12
+ 800afa4:	05800044 	movi	r22,1
+ 800afa8:	ddc015c4 	addi	r23,sp,87
+ 800afac:	482b883a 	mov	r21,r9
+ 800afb0:	4d80010e 	bge	r9,r22,800afb8 <___vfiprintf_internal_r+0xba8>
+ 800afb4:	b02b883a 	mov	r21,r22
+ 800afb8:	6b403fcc 	andi	r13,r13,255
+ 800afbc:	6b40201c 	xori	r13,r13,128
+ 800afc0:	6b7fe004 	addi	r13,r13,-128
+ 800afc4:	683efd26 	beq	r13,zero,800abbc <___vfiprintf_internal_r+0x7ac>
+ 800afc8:	ad400044 	addi	r21,r21,1
+ 800afcc:	003efb06 	br	800abbc <___vfiprintf_internal_r+0x7ac>
+ 800afd0:	882f883a 	mov	r23,r17
+ 800afd4:	d9000417 	ldw	r4,16(sp)
+ 800afd8:	a88003cc 	andi	r2,r21,15
+ 800afdc:	b006973a 	slli	r3,r22,28
+ 800afe0:	2085883a 	add	r2,r4,r2
+ 800afe4:	a82ad13a 	srli	r21,r21,4
+ 800afe8:	10800003 	ldbu	r2,0(r2)
+ 800afec:	b02cd13a 	srli	r22,r22,4
+ 800aff0:	bdffffc4 	addi	r23,r23,-1
+ 800aff4:	1d6ab03a 	or	r21,r3,r21
+ 800aff8:	b8800005 	stb	r2,0(r23)
+ 800affc:	ad84b03a 	or	r2,r21,r22
+ 800b000:	103ff41e 	bne	r2,zero,800afd4 <___vfiprintf_internal_r+0xbc4>
+ 800b004:	8dedc83a 	sub	r22,r17,r23
+ 800b008:	6029883a 	mov	r20,r12
+ 800b00c:	003fe706 	br	800afac <___vfiprintf_internal_r+0xb9c>
+ 800b010:	01800044 	movi	r6,1
+ 800b014:	000b883a 	mov	r5,zero
+ 800b018:	8807883a 	mov	r3,r17
+ 800b01c:	003f4b06 	br	800ad4c <___vfiprintf_internal_r+0x93c>
+ 800b020:	8559c83a 	sub	r12,r16,r21
+ 800b024:	033f1b0e 	bge	zero,r12,800ac94 <___vfiprintf_internal_r+0x884>
+ 800b028:	61800450 	cmplti	r6,r12,17
+ 800b02c:	01c20134 	movhi	r7,2052
+ 800b030:	3001af1e 	bne	r6,zero,800b6f0 <___vfiprintf_internal_r+0x12e0>
+ 800b034:	39dd7d04 	addi	r7,r7,30196
+ 800b038:	03400404 	movi	r13,16
+ 800b03c:	00000606 	br	800b058 <___vfiprintf_internal_r+0xc48>
+ 800b040:	21800084 	addi	r6,r4,2
+ 800b044:	42000204 	addi	r8,r8,8
+ 800b048:	1809883a 	mov	r4,r3
+ 800b04c:	633ffc04 	addi	r12,r12,-16
+ 800b050:	60c00448 	cmpgei	r3,r12,17
+ 800b054:	18001c26 	beq	r3,zero,800b0c8 <___vfiprintf_internal_r+0xcb8>
+ 800b058:	20c00044 	addi	r3,r4,1
+ 800b05c:	10800404 	addi	r2,r2,16
+ 800b060:	41c00015 	stw	r7,0(r8)
+ 800b064:	43400115 	stw	r13,4(r8)
+ 800b068:	d8800b15 	stw	r2,44(sp)
+ 800b06c:	d8c00a15 	stw	r3,40(sp)
+ 800b070:	19400208 	cmpgei	r5,r3,8
+ 800b074:	283ff226 	beq	r5,zero,800b040 <___vfiprintf_internal_r+0xc30>
+ 800b078:	d9800904 	addi	r6,sp,36
+ 800b07c:	900b883a 	mov	r5,r18
+ 800b080:	9809883a 	mov	r4,r19
+ 800b084:	10006326 	beq	r2,zero,800b214 <___vfiprintf_internal_r+0xe04>
+ 800b088:	d9c00515 	stw	r7,20(sp)
+ 800b08c:	db000215 	stw	r12,8(sp)
+ 800b090:	da400115 	stw	r9,4(sp)
+ 800b094:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b098:	103db01e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b09c:	db000217 	ldw	r12,8(sp)
+ 800b0a0:	d9000a17 	ldw	r4,40(sp)
+ 800b0a4:	d8800b17 	ldw	r2,44(sp)
+ 800b0a8:	633ffc04 	addi	r12,r12,-16
+ 800b0ac:	60c00448 	cmpgei	r3,r12,17
+ 800b0b0:	8811883a 	mov	r8,r17
+ 800b0b4:	21800044 	addi	r6,r4,1
+ 800b0b8:	d9c00517 	ldw	r7,20(sp)
+ 800b0bc:	03400404 	movi	r13,16
+ 800b0c0:	da400117 	ldw	r9,4(sp)
+ 800b0c4:	183fe41e 	bne	r3,zero,800b058 <___vfiprintf_internal_r+0xc48>
+ 800b0c8:	43400204 	addi	r13,r8,8
+ 800b0cc:	1305883a 	add	r2,r2,r12
+ 800b0d0:	41c00015 	stw	r7,0(r8)
+ 800b0d4:	43000115 	stw	r12,4(r8)
+ 800b0d8:	d8800b15 	stw	r2,44(sp)
+ 800b0dc:	d9800a15 	stw	r6,40(sp)
+ 800b0e0:	30c00208 	cmpgei	r3,r6,8
+ 800b0e4:	1800e226 	beq	r3,zero,800b470 <___vfiprintf_internal_r+0x1060>
+ 800b0e8:	10015726 	beq	r2,zero,800b648 <___vfiprintf_internal_r+0x1238>
+ 800b0ec:	d9800904 	addi	r6,sp,36
+ 800b0f0:	900b883a 	mov	r5,r18
+ 800b0f4:	9809883a 	mov	r4,r19
+ 800b0f8:	da400115 	stw	r9,4(sp)
+ 800b0fc:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b100:	103d961e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b104:	da400117 	ldw	r9,4(sp)
+ 800b108:	d9000a17 	ldw	r4,40(sp)
+ 800b10c:	d8800b17 	ldw	r2,44(sp)
+ 800b110:	4d93c83a 	sub	r9,r9,r22
+ 800b114:	d8c01804 	addi	r3,sp,96
+ 800b118:	21400044 	addi	r5,r4,1
+ 800b11c:	8811883a 	mov	r8,r17
+ 800b120:	027ede0e 	bge	zero,r9,800ac9c <___vfiprintf_internal_r+0x88c>
+ 800b124:	49800450 	cmplti	r6,r9,17
+ 800b128:	01c20134 	movhi	r7,2052
+ 800b12c:	3001431e 	bne	r6,zero,800b63c <___vfiprintf_internal_r+0x122c>
+ 800b130:	39dd7d04 	addi	r7,r7,30196
+ 800b134:	03000404 	movi	r12,16
+ 800b138:	00000606 	br	800b154 <___vfiprintf_internal_r+0xd44>
+ 800b13c:	21400084 	addi	r5,r4,2
+ 800b140:	42000204 	addi	r8,r8,8
+ 800b144:	1809883a 	mov	r4,r3
+ 800b148:	4a7ffc04 	addi	r9,r9,-16
+ 800b14c:	48c00448 	cmpgei	r3,r9,17
+ 800b150:	18001a26 	beq	r3,zero,800b1bc <___vfiprintf_internal_r+0xdac>
+ 800b154:	20c00044 	addi	r3,r4,1
+ 800b158:	10800404 	addi	r2,r2,16
+ 800b15c:	41c00015 	stw	r7,0(r8)
+ 800b160:	43000115 	stw	r12,4(r8)
+ 800b164:	d8800b15 	stw	r2,44(sp)
+ 800b168:	d8c00a15 	stw	r3,40(sp)
+ 800b16c:	19400208 	cmpgei	r5,r3,8
+ 800b170:	283ff226 	beq	r5,zero,800b13c <___vfiprintf_internal_r+0xd2c>
+ 800b174:	d9800904 	addi	r6,sp,36
+ 800b178:	900b883a 	mov	r5,r18
+ 800b17c:	9809883a 	mov	r4,r19
+ 800b180:	10001a26 	beq	r2,zero,800b1ec <___vfiprintf_internal_r+0xddc>
+ 800b184:	d9c00215 	stw	r7,8(sp)
+ 800b188:	da400115 	stw	r9,4(sp)
+ 800b18c:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b190:	103d721e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b194:	da400117 	ldw	r9,4(sp)
+ 800b198:	d9000a17 	ldw	r4,40(sp)
+ 800b19c:	d8800b17 	ldw	r2,44(sp)
+ 800b1a0:	4a7ffc04 	addi	r9,r9,-16
+ 800b1a4:	48c00448 	cmpgei	r3,r9,17
+ 800b1a8:	8811883a 	mov	r8,r17
+ 800b1ac:	21400044 	addi	r5,r4,1
+ 800b1b0:	d9c00217 	ldw	r7,8(sp)
+ 800b1b4:	03000404 	movi	r12,16
+ 800b1b8:	183fe61e 	bne	r3,zero,800b154 <___vfiprintf_internal_r+0xd44>
+ 800b1bc:	41000204 	addi	r4,r8,8
+ 800b1c0:	1245883a 	add	r2,r2,r9
+ 800b1c4:	41c00015 	stw	r7,0(r8)
+ 800b1c8:	42400115 	stw	r9,4(r8)
+ 800b1cc:	d8800b15 	stw	r2,44(sp)
+ 800b1d0:	d9400a15 	stw	r5,40(sp)
+ 800b1d4:	28c00208 	cmpgei	r3,r5,8
+ 800b1d8:	1800721e 	bne	r3,zero,800b3a4 <___vfiprintf_internal_r+0xf94>
+ 800b1dc:	29400044 	addi	r5,r5,1
+ 800b1e0:	20c00204 	addi	r3,r4,8
+ 800b1e4:	2011883a 	mov	r8,r4
+ 800b1e8:	003eac06 	br	800ac9c <___vfiprintf_internal_r+0x88c>
+ 800b1ec:	01400044 	movi	r5,1
+ 800b1f0:	0009883a 	mov	r4,zero
+ 800b1f4:	8811883a 	mov	r8,r17
+ 800b1f8:	003fd306 	br	800b148 <___vfiprintf_internal_r+0xd38>
+ 800b1fc:	d9800904 	addi	r6,sp,36
+ 800b200:	900b883a 	mov	r5,r18
+ 800b204:	9809883a 	mov	r4,r19
+ 800b208:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b20c:	103ebc26 	beq	r2,zero,800ad00 <___vfiprintf_internal_r+0x8f0>
+ 800b210:	003d5206 	br	800a75c <___vfiprintf_internal_r+0x34c>
+ 800b214:	01800044 	movi	r6,1
+ 800b218:	0009883a 	mov	r4,zero
+ 800b21c:	8811883a 	mov	r8,r17
+ 800b220:	003f8a06 	br	800b04c <___vfiprintf_internal_r+0xc3c>
+ 800b224:	10007026 	beq	r2,zero,800b3e8 <___vfiprintf_internal_r+0xfd8>
+ 800b228:	d9800904 	addi	r6,sp,36
+ 800b22c:	900b883a 	mov	r5,r18
+ 800b230:	9809883a 	mov	r4,r19
+ 800b234:	da400515 	stw	r9,20(sp)
+ 800b238:	db000215 	stw	r12,8(sp)
+ 800b23c:	db400115 	stw	r13,4(sp)
+ 800b240:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b244:	103d451e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b248:	d9000a17 	ldw	r4,40(sp)
+ 800b24c:	d8800b17 	ldw	r2,44(sp)
+ 800b250:	d8c01804 	addi	r3,sp,96
+ 800b254:	21400044 	addi	r5,r4,1
+ 800b258:	8811883a 	mov	r8,r17
+ 800b25c:	da400517 	ldw	r9,20(sp)
+ 800b260:	db000217 	ldw	r12,8(sp)
+ 800b264:	db400117 	ldw	r13,4(sp)
+ 800b268:	003e6f06 	br	800ac28 <___vfiprintf_internal_r+0x818>
+ 800b26c:	d8800884 	addi	r2,sp,34
+ 800b270:	d8801615 	stw	r2,88(sp)
+ 800b274:	00800084 	movi	r2,2
+ 800b278:	d8801715 	stw	r2,92(sp)
+ 800b27c:	d8c01804 	addi	r3,sp,96
+ 800b280:	01400044 	movi	r5,1
+ 800b284:	1811883a 	mov	r8,r3
+ 800b288:	2809883a 	mov	r4,r5
+ 800b28c:	21400044 	addi	r5,r4,1
+ 800b290:	40c00204 	addi	r3,r8,8
+ 800b294:	003e7d06 	br	800ac8c <___vfiprintf_internal_r+0x87c>
+ 800b298:	a019883a 	mov	r12,r20
+ 800b29c:	003f0506 	br	800aeb4 <___vfiprintf_internal_r+0xaa4>
+ 800b2a0:	19400450 	cmplti	r5,r3,17
+ 800b2a4:	01c20134 	movhi	r7,2052
+ 800b2a8:	2801031e 	bne	r5,zero,800b6b8 <___vfiprintf_internal_r+0x12a8>
+ 800b2ac:	39dd8104 	addi	r7,r7,30212
+ 800b2b0:	03800404 	movi	r14,16
+ 800b2b4:	00000706 	br	800b2d4 <___vfiprintf_internal_r+0xec4>
+ 800b2b8:	23c00084 	addi	r15,r4,2
+ 800b2bc:	42000204 	addi	r8,r8,8
+ 800b2c0:	3009883a 	mov	r4,r6
+ 800b2c4:	18fffc04 	addi	r3,r3,-16
+ 800b2c8:	19400448 	cmpgei	r5,r3,17
+ 800b2cc:	28002026 	beq	r5,zero,800b350 <___vfiprintf_internal_r+0xf40>
+ 800b2d0:	21800044 	addi	r6,r4,1
+ 800b2d4:	10800404 	addi	r2,r2,16
+ 800b2d8:	41c00015 	stw	r7,0(r8)
+ 800b2dc:	43800115 	stw	r14,4(r8)
+ 800b2e0:	d8800b15 	stw	r2,44(sp)
+ 800b2e4:	d9800a15 	stw	r6,40(sp)
+ 800b2e8:	31400208 	cmpgei	r5,r6,8
+ 800b2ec:	283ff226 	beq	r5,zero,800b2b8 <___vfiprintf_internal_r+0xea8>
+ 800b2f0:	d9800904 	addi	r6,sp,36
+ 800b2f4:	900b883a 	mov	r5,r18
+ 800b2f8:	9809883a 	mov	r4,r19
+ 800b2fc:	10001f26 	beq	r2,zero,800b37c <___vfiprintf_internal_r+0xf6c>
+ 800b300:	d9c00715 	stw	r7,28(sp)
+ 800b304:	d8c00615 	stw	r3,24(sp)
+ 800b308:	da400515 	stw	r9,20(sp)
+ 800b30c:	db000215 	stw	r12,8(sp)
+ 800b310:	db400115 	stw	r13,4(sp)
+ 800b314:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b318:	103d101e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b31c:	d8c00617 	ldw	r3,24(sp)
+ 800b320:	d9000a17 	ldw	r4,40(sp)
+ 800b324:	d8800b17 	ldw	r2,44(sp)
+ 800b328:	18fffc04 	addi	r3,r3,-16
+ 800b32c:	19400448 	cmpgei	r5,r3,17
+ 800b330:	8811883a 	mov	r8,r17
+ 800b334:	23c00044 	addi	r15,r4,1
+ 800b338:	d9c00717 	ldw	r7,28(sp)
+ 800b33c:	03800404 	movi	r14,16
+ 800b340:	da400517 	ldw	r9,20(sp)
+ 800b344:	db000217 	ldw	r12,8(sp)
+ 800b348:	db400117 	ldw	r13,4(sp)
+ 800b34c:	283fe01e 	bne	r5,zero,800b2d0 <___vfiprintf_internal_r+0xec0>
+ 800b350:	10c5883a 	add	r2,r2,r3
+ 800b354:	40c00115 	stw	r3,4(r8)
+ 800b358:	41c00015 	stw	r7,0(r8)
+ 800b35c:	d8800b15 	stw	r2,44(sp)
+ 800b360:	dbc00a15 	stw	r15,40(sp)
+ 800b364:	78c00208 	cmpgei	r3,r15,8
+ 800b368:	18002c1e 	bne	r3,zero,800b41c <___vfiprintf_internal_r+0x100c>
+ 800b36c:	42000204 	addi	r8,r8,8
+ 800b370:	79400044 	addi	r5,r15,1
+ 800b374:	7809883a 	mov	r4,r15
+ 800b378:	003e1b06 	br	800abe8 <___vfiprintf_internal_r+0x7d8>
+ 800b37c:	0009883a 	mov	r4,zero
+ 800b380:	03c00044 	movi	r15,1
+ 800b384:	8811883a 	mov	r8,r17
+ 800b388:	003fce06 	br	800b2c4 <___vfiprintf_internal_r+0xeb4>
+ 800b38c:	8540010e 	bge	r16,r21,800b394 <___vfiprintf_internal_r+0xf84>
+ 800b390:	a821883a 	mov	r16,r21
+ 800b394:	d8800017 	ldw	r2,0(sp)
+ 800b398:	1405883a 	add	r2,r2,r16
+ 800b39c:	d8800015 	stw	r2,0(sp)
+ 800b3a0:	003e5706 	br	800ad00 <___vfiprintf_internal_r+0x8f0>
+ 800b3a4:	10008126 	beq	r2,zero,800b5ac <___vfiprintf_internal_r+0x119c>
+ 800b3a8:	d9800904 	addi	r6,sp,36
+ 800b3ac:	900b883a 	mov	r5,r18
+ 800b3b0:	9809883a 	mov	r4,r19
+ 800b3b4:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b3b8:	103ce81e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b3bc:	d9400a17 	ldw	r5,40(sp)
+ 800b3c0:	d8800b17 	ldw	r2,44(sp)
+ 800b3c4:	d8c01804 	addi	r3,sp,96
+ 800b3c8:	29400044 	addi	r5,r5,1
+ 800b3cc:	8811883a 	mov	r8,r17
+ 800b3d0:	003e3206 	br	800ac9c <___vfiprintf_internal_r+0x88c>
+ 800b3d4:	d8000a15 	stw	zero,40(sp)
+ 800b3d8:	8811883a 	mov	r8,r17
+ 800b3dc:	003c4e06 	br	800a518 <___vfiprintf_internal_r+0x108>
+ 800b3e0:	002d883a 	mov	r22,zero
+ 800b3e4:	003d4406 	br	800a8f8 <___vfiprintf_internal_r+0x4e8>
+ 800b3e8:	68003326 	beq	r13,zero,800b4b8 <___vfiprintf_internal_r+0x10a8>
+ 800b3ec:	d8800884 	addi	r2,sp,34
+ 800b3f0:	d8801615 	stw	r2,88(sp)
+ 800b3f4:	00800084 	movi	r2,2
+ 800b3f8:	d8801715 	stw	r2,92(sp)
+ 800b3fc:	da001804 	addi	r8,sp,96
+ 800b400:	01000044 	movi	r4,1
+ 800b404:	003fa106 	br	800b28c <___vfiprintf_internal_r+0xe7c>
+ 800b408:	d8c01804 	addi	r3,sp,96
+ 800b40c:	01400044 	movi	r5,1
+ 800b410:	0009883a 	mov	r4,zero
+ 800b414:	8811883a 	mov	r8,r17
+ 800b418:	003e1c06 	br	800ac8c <___vfiprintf_internal_r+0x87c>
+ 800b41c:	10003826 	beq	r2,zero,800b500 <___vfiprintf_internal_r+0x10f0>
+ 800b420:	d9800904 	addi	r6,sp,36
+ 800b424:	900b883a 	mov	r5,r18
+ 800b428:	9809883a 	mov	r4,r19
+ 800b42c:	da400515 	stw	r9,20(sp)
+ 800b430:	db000215 	stw	r12,8(sp)
+ 800b434:	db400115 	stw	r13,4(sp)
+ 800b438:	800a3040 	call	800a304 <__sprint_r.part.0>
+ 800b43c:	103cc71e 	bne	r2,zero,800a75c <___vfiprintf_internal_r+0x34c>
+ 800b440:	d9000a17 	ldw	r4,40(sp)
+ 800b444:	d8800b17 	ldw	r2,44(sp)
+ 800b448:	8811883a 	mov	r8,r17
+ 800b44c:	21400044 	addi	r5,r4,1
+ 800b450:	da400517 	ldw	r9,20(sp)
+ 800b454:	db000217 	ldw	r12,8(sp)
+ 800b458:	db400117 	ldw	r13,4(sp)
+ 800b45c:	003de206 	br	800abe8 <___vfiprintf_internal_r+0x7d8>
+ 800b460:	e029883a 	mov	r20,fp
+ 800b464:	003c3106 	br	800a52c <___vfiprintf_internal_r+0x11c>
+ 800b468:	882f883a 	mov	r23,r17
+ 800b46c:	003ecf06 	br	800afac <___vfiprintf_internal_r+0xb9c>
+ 800b470:	31400044 	addi	r5,r6,1
+ 800b474:	68c00204 	addi	r3,r13,8
+ 800b478:	3009883a 	mov	r4,r6
+ 800b47c:	6811883a 	mov	r8,r13
+ 800b480:	003e0406 	br	800ac94 <___vfiprintf_internal_r+0x884>
+ 800b484:	00c00c04 	movi	r3,48
+ 800b488:	d88008c5 	stb	r2,35(sp)
+ 800b48c:	d8c00885 	stb	r3,34(sp)
+ 800b490:	63000094 	ori	r12,r12,2
+ 800b494:	00800084 	movi	r2,2
+ 800b498:	003d3606 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800b49c:	d9400017 	ldw	r5,0(sp)
+ 800b4a0:	20800017 	ldw	r2,0(r4)
+ 800b4a4:	d8c00315 	stw	r3,12(sp)
+ 800b4a8:	2809d7fa 	srai	r4,r5,31
+ 800b4ac:	11400015 	stw	r5,0(r2)
+ 800b4b0:	11000115 	stw	r4,4(r2)
+ 800b4b4:	003bff06 	br	800a4b4 <___vfiprintf_internal_r+0xa4>
+ 800b4b8:	0009883a 	mov	r4,zero
+ 800b4bc:	d8c01804 	addi	r3,sp,96
+ 800b4c0:	01400044 	movi	r5,1
+ 800b4c4:	8811883a 	mov	r8,r17
+ 800b4c8:	003df006 	br	800ac8c <___vfiprintf_internal_r+0x87c>
+ 800b4cc:	0421c83a 	sub	r16,zero,r16
+ 800b4d0:	ddc00315 	stw	r23,12(sp)
+ 800b4d4:	003cdb06 	br	800a844 <___vfiprintf_internal_r+0x434>
+ 800b4d8:	b809883a 	mov	r4,r23
+ 800b4dc:	da000215 	stw	r8,8(sp)
+ 800b4e0:	db000115 	stw	r12,4(sp)
+ 800b4e4:	8002dac0 	call	8002dac <strlen>
+ 800b4e8:	102d883a 	mov	r22,r2
+ 800b4ec:	102b883a 	mov	r21,r2
+ 800b4f0:	dd000315 	stw	r20,12(sp)
+ 800b4f4:	db000117 	ldw	r12,4(sp)
+ 800b4f8:	da000217 	ldw	r8,8(sp)
+ 800b4fc:	003dad06 	br	800abb4 <___vfiprintf_internal_r+0x7a4>
+ 800b500:	d8c00847 	ldb	r3,33(sp)
+ 800b504:	1800551e 	bne	r3,zero,800b65c <___vfiprintf_internal_r+0x124c>
+ 800b508:	683f581e 	bne	r13,zero,800b26c <___vfiprintf_internal_r+0xe5c>
+ 800b50c:	0009883a 	mov	r4,zero
+ 800b510:	d8c01804 	addi	r3,sp,96
+ 800b514:	01400044 	movi	r5,1
+ 800b518:	8811883a 	mov	r8,r17
+ 800b51c:	003ddd06 	br	800ac94 <___vfiprintf_internal_r+0x884>
+ 800b520:	d8800317 	ldw	r2,12(sp)
+ 800b524:	10800017 	ldw	r2,0(r2)
+ 800b528:	d8c00315 	stw	r3,12(sp)
+ 800b52c:	d8c00017 	ldw	r3,0(sp)
+ 800b530:	10c00015 	stw	r3,0(r2)
+ 800b534:	003bdf06 	br	800a4b4 <___vfiprintf_internal_r+0xa4>
+ 800b538:	882f883a 	mov	r23,r17
+ 800b53c:	00000206 	br	800b548 <___vfiprintf_internal_r+0x1138>
+ 800b540:	102b883a 	mov	r21,r2
+ 800b544:	182d883a 	mov	r22,r3
+ 800b548:	a809883a 	mov	r4,r21
+ 800b54c:	b00b883a 	mov	r5,r22
+ 800b550:	01800284 	movi	r6,10
+ 800b554:	000f883a 	mov	r7,zero
+ 800b558:	db400615 	stw	r13,24(sp)
+ 800b55c:	da000515 	stw	r8,20(sp)
+ 800b560:	da400215 	stw	r9,8(sp)
+ 800b564:	db000115 	stw	r12,4(sp)
+ 800b568:	800c9c00 	call	800c9c0 <__umoddi3>
+ 800b56c:	10800c04 	addi	r2,r2,48
+ 800b570:	bdffffc4 	addi	r23,r23,-1
+ 800b574:	a809883a 	mov	r4,r21
+ 800b578:	b00b883a 	mov	r5,r22
+ 800b57c:	b8800005 	stb	r2,0(r23)
+ 800b580:	01800284 	movi	r6,10
+ 800b584:	000f883a 	mov	r7,zero
+ 800b588:	800c4280 	call	800c428 <__udivdi3>
+ 800b58c:	db000117 	ldw	r12,4(sp)
+ 800b590:	da400217 	ldw	r9,8(sp)
+ 800b594:	da000517 	ldw	r8,20(sp)
+ 800b598:	db400617 	ldw	r13,24(sp)
+ 800b59c:	b03fe81e 	bne	r22,zero,800b540 <___vfiprintf_internal_r+0x1130>
+ 800b5a0:	ad4002a8 	cmpgeui	r21,r21,10
+ 800b5a4:	a83fe61e 	bne	r21,zero,800b540 <___vfiprintf_internal_r+0x1130>
+ 800b5a8:	003e9606 	br	800b004 <___vfiprintf_internal_r+0xbf4>
+ 800b5ac:	00c00044 	movi	r3,1
+ 800b5b0:	d8c00a15 	stw	r3,40(sp)
+ 800b5b4:	b005883a 	mov	r2,r22
+ 800b5b8:	ddc01615 	stw	r23,88(sp)
+ 800b5bc:	dd801715 	stw	r22,92(sp)
+ 800b5c0:	dd800b15 	stw	r22,44(sp)
+ 800b5c4:	d8c01804 	addi	r3,sp,96
+ 800b5c8:	003dc306 	br	800acd8 <___vfiprintf_internal_r+0x8c8>
+ 800b5cc:	10c00060 	cmpeqi	r3,r2,1
+ 800b5d0:	a019883a 	mov	r12,r20
+ 800b5d4:	183e3926 	beq	r3,zero,800aebc <___vfiprintf_internal_r+0xaac>
+ 800b5d8:	003e6f06 	br	800af98 <___vfiprintf_internal_r+0xb88>
+ 800b5dc:	e0800043 	ldbu	r2,1(fp)
+ 800b5e0:	63000814 	ori	r12,r12,32
+ 800b5e4:	e7000044 	addi	fp,fp,1
+ 800b5e8:	10803fcc 	andi	r2,r2,255
+ 800b5ec:	1080201c 	xori	r2,r2,128
+ 800b5f0:	10bfe004 	addi	r2,r2,-128
+ 800b5f4:	003bd506 	br	800a54c <___vfiprintf_internal_r+0x13c>
+ 800b5f8:	488001f0 	cmpltui	r2,r9,7
+ 800b5fc:	482d883a 	mov	r22,r9
+ 800b600:	1000011e 	bne	r2,zero,800b608 <___vfiprintf_internal_r+0x11f8>
+ 800b604:	05800184 	movi	r22,6
+ 800b608:	05c20134 	movhi	r23,2052
+ 800b60c:	b02b883a 	mov	r21,r22
+ 800b610:	dd000315 	stw	r20,12(sp)
+ 800b614:	bddd2504 	addi	r23,r23,29844
+ 800b618:	003d6606 	br	800abb4 <___vfiprintf_internal_r+0x7a4>
+ 800b61c:	d8800315 	stw	r2,12(sp)
+ 800b620:	002d883a 	mov	r22,zero
+ 800b624:	00800044 	movi	r2,1
+ 800b628:	003cd206 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800b62c:	d8800315 	stw	r2,12(sp)
+ 800b630:	002d883a 	mov	r22,zero
+ 800b634:	0005883a 	mov	r2,zero
+ 800b638:	003cce06 	br	800a974 <___vfiprintf_internal_r+0x564>
+ 800b63c:	1809883a 	mov	r4,r3
+ 800b640:	39dd7d04 	addi	r7,r7,30196
+ 800b644:	003ede06 	br	800b1c0 <___vfiprintf_internal_r+0xdb0>
+ 800b648:	d8c01804 	addi	r3,sp,96
+ 800b64c:	01400044 	movi	r5,1
+ 800b650:	0009883a 	mov	r4,zero
+ 800b654:	8811883a 	mov	r8,r17
+ 800b658:	003d8e06 	br	800ac94 <___vfiprintf_internal_r+0x884>
+ 800b65c:	d8800844 	addi	r2,sp,33
+ 800b660:	d8801615 	stw	r2,88(sp)
+ 800b664:	00800044 	movi	r2,1
+ 800b668:	d8801715 	stw	r2,92(sp)
+ 800b66c:	d8c01804 	addi	r3,sp,96
+ 800b670:	01400044 	movi	r5,1
+ 800b674:	003d6806 	br	800ac18 <___vfiprintf_internal_r+0x808>
+ 800b678:	d9800845 	stb	r6,33(sp)
+ 800b67c:	003c5506 	br	800a7d4 <___vfiprintf_internal_r+0x3c4>
+ 800b680:	482b883a 	mov	r21,r9
+ 800b684:	dd000315 	stw	r20,12(sp)
+ 800b688:	482d883a 	mov	r22,r9
+ 800b68c:	003d4906 	br	800abb4 <___vfiprintf_internal_r+0x7a4>
+ 800b690:	d9800845 	stb	r6,33(sp)
+ 800b694:	003cd906 	br	800a9fc <___vfiprintf_internal_r+0x5ec>
+ 800b698:	d9800845 	stb	r6,33(sp)
+ 800b69c:	003ce906 	br	800aa44 <___vfiprintf_internal_r+0x634>
+ 800b6a0:	d9800845 	stb	r6,33(sp)
+ 800b6a4:	003c8a06 	br	800a8d0 <___vfiprintf_internal_r+0x4c0>
+ 800b6a8:	d9800845 	stb	r6,33(sp)
+ 800b6ac:	003dd206 	br	800adf8 <___vfiprintf_internal_r+0x9e8>
+ 800b6b0:	d9800845 	stb	r6,33(sp)
+ 800b6b4:	003ddd06 	br	800ae2c <___vfiprintf_internal_r+0xa1c>
+ 800b6b8:	301f883a 	mov	r15,r6
+ 800b6bc:	39dd8104 	addi	r7,r7,30212
+ 800b6c0:	003f2306 	br	800b350 <___vfiprintf_internal_r+0xf40>
+ 800b6c4:	d9800845 	stb	r6,33(sp)
+ 800b6c8:	003d1606 	br	800ab24 <___vfiprintf_internal_r+0x714>
+ 800b6cc:	d9800845 	stb	r6,33(sp)
+ 800b6d0:	003d0406 	br	800aae4 <___vfiprintf_internal_r+0x6d4>
+ 800b6d4:	d9800845 	stb	r6,33(sp)
+ 800b6d8:	003cb806 	br	800a9bc <___vfiprintf_internal_r+0x5ac>
+ 800b6dc:	d9800845 	stb	r6,33(sp)
+ 800b6e0:	003ddf06 	br	800ae60 <___vfiprintf_internal_r+0xa50>
+ 800b6e4:	29800044 	addi	r6,r5,1
+ 800b6e8:	39dd8104 	addi	r7,r7,30212
+ 800b6ec:	003db106 	br	800adb4 <___vfiprintf_internal_r+0x9a4>
+ 800b6f0:	181b883a 	mov	r13,r3
+ 800b6f4:	280d883a 	mov	r6,r5
+ 800b6f8:	39dd7d04 	addi	r7,r7,30196
+ 800b6fc:	003e7306 	br	800b0cc <___vfiprintf_internal_r+0xcbc>
+ 800b700:	00bfffc4 	movi	r2,-1
+ 800b704:	d8800015 	stw	r2,0(sp)
+ 800b708:	003c1706 	br	800a768 <___vfiprintf_internal_r+0x358>
+ 800b70c:	d8800317 	ldw	r2,12(sp)
+ 800b710:	12400017 	ldw	r9,0(r2)
+ 800b714:	15c00104 	addi	r23,r2,4
+ 800b718:	4800010e 	bge	r9,zero,800b720 <___vfiprintf_internal_r+0x1310>
+ 800b71c:	027fffc4 	movi	r9,-1
+ 800b720:	e0800043 	ldbu	r2,1(fp)
+ 800b724:	ddc00315 	stw	r23,12(sp)
+ 800b728:	2039883a 	mov	fp,r4
+ 800b72c:	10803fcc 	andi	r2,r2,255
+ 800b730:	1080201c 	xori	r2,r2,128
+ 800b734:	10bfe004 	addi	r2,r2,-128
+ 800b738:	003b8406 	br	800a54c <___vfiprintf_internal_r+0x13c>
+
+0800b73c <__vfiprintf_internal>:
+ 800b73c:	00820174 	movhi	r2,2053
+ 800b740:	300f883a 	mov	r7,r6
+ 800b744:	280d883a 	mov	r6,r5
+ 800b748:	200b883a 	mov	r5,r4
+ 800b74c:	1132af17 	ldw	r4,-13636(r2)
+ 800b750:	800a4101 	jmpi	800a410 <___vfiprintf_internal_r>
+
+0800b754 <__sbprintf>:
+ 800b754:	2880030b 	ldhu	r2,12(r5)
+ 800b758:	2b001917 	ldw	r12,100(r5)
+ 800b75c:	2ac0038b 	ldhu	r11,14(r5)
+ 800b760:	2a800717 	ldw	r10,28(r5)
+ 800b764:	2a400917 	ldw	r9,36(r5)
+ 800b768:	defee204 	addi	sp,sp,-1144
+ 800b76c:	da001a04 	addi	r8,sp,104
+ 800b770:	00c10004 	movi	r3,1024
+ 800b774:	dc011a15 	stw	r16,1128(sp)
+ 800b778:	10bfff4c 	andi	r2,r2,65533
+ 800b77c:	2821883a 	mov	r16,r5
+ 800b780:	d80b883a 	mov	r5,sp
+ 800b784:	dc811c15 	stw	r18,1136(sp)
+ 800b788:	dc411b15 	stw	r17,1132(sp)
+ 800b78c:	dfc11d15 	stw	ra,1140(sp)
+ 800b790:	2025883a 	mov	r18,r4
+ 800b794:	d880030d 	sth	r2,12(sp)
+ 800b798:	db001915 	stw	r12,100(sp)
+ 800b79c:	dac0038d 	sth	r11,14(sp)
+ 800b7a0:	da800715 	stw	r10,28(sp)
+ 800b7a4:	da400915 	stw	r9,36(sp)
+ 800b7a8:	da000015 	stw	r8,0(sp)
+ 800b7ac:	da000415 	stw	r8,16(sp)
+ 800b7b0:	d8c00215 	stw	r3,8(sp)
+ 800b7b4:	d8c00515 	stw	r3,20(sp)
+ 800b7b8:	d8000615 	stw	zero,24(sp)
+ 800b7bc:	800a4100 	call	800a410 <___vfiprintf_internal_r>
+ 800b7c0:	1023883a 	mov	r17,r2
+ 800b7c4:	10000d0e 	bge	r2,zero,800b7fc <__sbprintf+0xa8>
+ 800b7c8:	d880030b 	ldhu	r2,12(sp)
+ 800b7cc:	1080100c 	andi	r2,r2,64
+ 800b7d0:	10000326 	beq	r2,zero,800b7e0 <__sbprintf+0x8c>
+ 800b7d4:	8080030b 	ldhu	r2,12(r16)
+ 800b7d8:	10801014 	ori	r2,r2,64
+ 800b7dc:	8080030d 	sth	r2,12(r16)
+ 800b7e0:	8805883a 	mov	r2,r17
+ 800b7e4:	dfc11d17 	ldw	ra,1140(sp)
+ 800b7e8:	dc811c17 	ldw	r18,1136(sp)
+ 800b7ec:	dc411b17 	ldw	r17,1132(sp)
+ 800b7f0:	dc011a17 	ldw	r16,1128(sp)
+ 800b7f4:	dec11e04 	addi	sp,sp,1144
+ 800b7f8:	f800283a 	ret
+ 800b7fc:	d80b883a 	mov	r5,sp
+ 800b800:	9009883a 	mov	r4,r18
+ 800b804:	8006cdc0 	call	8006cdc <_fflush_r>
+ 800b808:	103fef26 	beq	r2,zero,800b7c8 <__sbprintf+0x74>
+ 800b80c:	047fffc4 	movi	r17,-1
+ 800b810:	003fed06 	br	800b7c8 <__sbprintf+0x74>
+
+0800b814 <__swbuf_r>:
+ 800b814:	defffb04 	addi	sp,sp,-20
+ 800b818:	dc800215 	stw	r18,8(sp)
+ 800b81c:	dc400115 	stw	r17,4(sp)
+ 800b820:	dc000015 	stw	r16,0(sp)
+ 800b824:	dfc00415 	stw	ra,16(sp)
+ 800b828:	dcc00315 	stw	r19,12(sp)
+ 800b82c:	2023883a 	mov	r17,r4
+ 800b830:	2825883a 	mov	r18,r5
+ 800b834:	3021883a 	mov	r16,r6
+ 800b838:	20000226 	beq	r4,zero,800b844 <__swbuf_r+0x30>
+ 800b83c:	20800e17 	ldw	r2,56(r4)
+ 800b840:	10003e26 	beq	r2,zero,800b93c <__swbuf_r+0x128>
+ 800b844:	80800617 	ldw	r2,24(r16)
+ 800b848:	80c0030b 	ldhu	r3,12(r16)
+ 800b84c:	80800215 	stw	r2,8(r16)
+ 800b850:	1880020c 	andi	r2,r3,8
+ 800b854:	10001f26 	beq	r2,zero,800b8d4 <__swbuf_r+0xc0>
+ 800b858:	80800417 	ldw	r2,16(r16)
+ 800b85c:	10001d26 	beq	r2,zero,800b8d4 <__swbuf_r+0xc0>
+ 800b860:	1908000c 	andi	r4,r3,8192
+ 800b864:	94c03fcc 	andi	r19,r18,255
+ 800b868:	20002326 	beq	r4,zero,800b8f8 <__swbuf_r+0xe4>
+ 800b86c:	80c00017 	ldw	r3,0(r16)
+ 800b870:	81000517 	ldw	r4,20(r16)
+ 800b874:	1885c83a 	sub	r2,r3,r2
+ 800b878:	1100290e 	bge	r2,r4,800b920 <__swbuf_r+0x10c>
+ 800b87c:	10800044 	addi	r2,r2,1
+ 800b880:	81000217 	ldw	r4,8(r16)
+ 800b884:	19400044 	addi	r5,r3,1
+ 800b888:	81400015 	stw	r5,0(r16)
+ 800b88c:	213fffc4 	addi	r4,r4,-1
+ 800b890:	81000215 	stw	r4,8(r16)
+ 800b894:	1c800005 	stb	r18,0(r3)
+ 800b898:	80c00517 	ldw	r3,20(r16)
+ 800b89c:	18802926 	beq	r3,r2,800b944 <__swbuf_r+0x130>
+ 800b8a0:	8080030b 	ldhu	r2,12(r16)
+ 800b8a4:	1080004c 	andi	r2,r2,1
+ 800b8a8:	10000226 	beq	r2,zero,800b8b4 <__swbuf_r+0xa0>
+ 800b8ac:	98800298 	cmpnei	r2,r19,10
+ 800b8b0:	10002426 	beq	r2,zero,800b944 <__swbuf_r+0x130>
+ 800b8b4:	9805883a 	mov	r2,r19
+ 800b8b8:	dfc00417 	ldw	ra,16(sp)
+ 800b8bc:	dcc00317 	ldw	r19,12(sp)
+ 800b8c0:	dc800217 	ldw	r18,8(sp)
+ 800b8c4:	dc400117 	ldw	r17,4(sp)
+ 800b8c8:	dc000017 	ldw	r16,0(sp)
+ 800b8cc:	dec00504 	addi	sp,sp,20
+ 800b8d0:	f800283a 	ret
+ 800b8d4:	800b883a 	mov	r5,r16
+ 800b8d8:	8809883a 	mov	r4,r17
+ 800b8dc:	800507c0 	call	800507c <__swsetup_r>
+ 800b8e0:	10001c1e 	bne	r2,zero,800b954 <__swbuf_r+0x140>
+ 800b8e4:	80c0030b 	ldhu	r3,12(r16)
+ 800b8e8:	80800417 	ldw	r2,16(r16)
+ 800b8ec:	94c03fcc 	andi	r19,r18,255
+ 800b8f0:	1908000c 	andi	r4,r3,8192
+ 800b8f4:	203fdd1e 	bne	r4,zero,800b86c <__swbuf_r+0x58>
+ 800b8f8:	81001917 	ldw	r4,100(r16)
+ 800b8fc:	18c80014 	ori	r3,r3,8192
+ 800b900:	0177ffc4 	movi	r5,-8193
+ 800b904:	2148703a 	and	r4,r4,r5
+ 800b908:	80c0030d 	sth	r3,12(r16)
+ 800b90c:	80c00017 	ldw	r3,0(r16)
+ 800b910:	81001915 	stw	r4,100(r16)
+ 800b914:	81000517 	ldw	r4,20(r16)
+ 800b918:	1885c83a 	sub	r2,r3,r2
+ 800b91c:	113fd716 	blt	r2,r4,800b87c <__swbuf_r+0x68>
+ 800b920:	800b883a 	mov	r5,r16
+ 800b924:	8809883a 	mov	r4,r17
+ 800b928:	8006cdc0 	call	8006cdc <_fflush_r>
+ 800b92c:	1000091e 	bne	r2,zero,800b954 <__swbuf_r+0x140>
+ 800b930:	80c00017 	ldw	r3,0(r16)
+ 800b934:	00800044 	movi	r2,1
+ 800b938:	003fd106 	br	800b880 <__swbuf_r+0x6c>
+ 800b93c:	80070600 	call	8007060 <__sinit>
+ 800b940:	003fc006 	br	800b844 <__swbuf_r+0x30>
+ 800b944:	800b883a 	mov	r5,r16
+ 800b948:	8809883a 	mov	r4,r17
+ 800b94c:	8006cdc0 	call	8006cdc <_fflush_r>
+ 800b950:	103fd826 	beq	r2,zero,800b8b4 <__swbuf_r+0xa0>
+ 800b954:	04ffffc4 	movi	r19,-1
+ 800b958:	003fd606 	br	800b8b4 <__swbuf_r+0xa0>
+
+0800b95c <__swbuf>:
+ 800b95c:	00820174 	movhi	r2,2053
+ 800b960:	280d883a 	mov	r6,r5
+ 800b964:	200b883a 	mov	r5,r4
+ 800b968:	1132af17 	ldw	r4,-13636(r2)
+ 800b96c:	800b8141 	jmpi	800b814 <__swbuf_r>
+
+0800b970 <_write_r>:
+ 800b970:	defffe04 	addi	sp,sp,-8
+ 800b974:	2805883a 	mov	r2,r5
+ 800b978:	dc000015 	stw	r16,0(sp)
+ 800b97c:	300b883a 	mov	r5,r6
+ 800b980:	2021883a 	mov	r16,r4
+ 800b984:	380d883a 	mov	r6,r7
+ 800b988:	1009883a 	mov	r4,r2
+ 800b98c:	00820174 	movhi	r2,2053
+ 800b990:	dfc00115 	stw	ra,4(sp)
+ 800b994:	1032f015 	stw	zero,-13376(r2)
+ 800b998:	8022c3c0 	call	8022c3c <write>
+ 800b99c:	10ffffd8 	cmpnei	r3,r2,-1
+ 800b9a0:	18000426 	beq	r3,zero,800b9b4 <_write_r+0x44>
+ 800b9a4:	dfc00117 	ldw	ra,4(sp)
+ 800b9a8:	dc000017 	ldw	r16,0(sp)
+ 800b9ac:	dec00204 	addi	sp,sp,8
+ 800b9b0:	f800283a 	ret
+ 800b9b4:	00c20174 	movhi	r3,2053
+ 800b9b8:	18f2f017 	ldw	r3,-13376(r3)
+ 800b9bc:	183ff926 	beq	r3,zero,800b9a4 <_write_r+0x34>
+ 800b9c0:	80c00015 	stw	r3,0(r16)
+ 800b9c4:	dfc00117 	ldw	ra,4(sp)
+ 800b9c8:	dc000017 	ldw	r16,0(sp)
+ 800b9cc:	dec00204 	addi	sp,sp,8
+ 800b9d0:	f800283a 	ret
+
+0800b9d4 <_close_r>:
+ 800b9d4:	defffe04 	addi	sp,sp,-8
+ 800b9d8:	dc000015 	stw	r16,0(sp)
+ 800b9dc:	00820174 	movhi	r2,2053
+ 800b9e0:	2021883a 	mov	r16,r4
+ 800b9e4:	2809883a 	mov	r4,r5
+ 800b9e8:	dfc00115 	stw	ra,4(sp)
+ 800b9ec:	1032f015 	stw	zero,-13376(r2)
+ 800b9f0:	8022a600 	call	8022a60 <close>
+ 800b9f4:	10ffffd8 	cmpnei	r3,r2,-1
+ 800b9f8:	18000426 	beq	r3,zero,800ba0c <_close_r+0x38>
+ 800b9fc:	dfc00117 	ldw	ra,4(sp)
+ 800ba00:	dc000017 	ldw	r16,0(sp)
+ 800ba04:	dec00204 	addi	sp,sp,8
+ 800ba08:	f800283a 	ret
+ 800ba0c:	00c20174 	movhi	r3,2053
+ 800ba10:	18f2f017 	ldw	r3,-13376(r3)
+ 800ba14:	183ff926 	beq	r3,zero,800b9fc <_close_r+0x28>
+ 800ba18:	80c00015 	stw	r3,0(r16)
+ 800ba1c:	dfc00117 	ldw	ra,4(sp)
+ 800ba20:	dc000017 	ldw	r16,0(sp)
+ 800ba24:	dec00204 	addi	sp,sp,8
+ 800ba28:	f800283a 	ret
+
+0800ba2c <_calloc_r>:
+ 800ba2c:	298b383a 	mul	r5,r5,r6
+ 800ba30:	deffff04 	addi	sp,sp,-4
+ 800ba34:	dfc00015 	stw	ra,0(sp)
+ 800ba38:	8007ddc0 	call	8007ddc <_malloc_r>
+ 800ba3c:	1007883a 	mov	r3,r2
+ 800ba40:	10000c26 	beq	r2,zero,800ba74 <_calloc_r+0x48>
+ 800ba44:	11bfff17 	ldw	r6,-4(r2)
+ 800ba48:	00bfff04 	movi	r2,-4
+ 800ba4c:	308c703a 	and	r6,r6,r2
+ 800ba50:	31bfff04 	addi	r6,r6,-4
+ 800ba54:	30800968 	cmpgeui	r2,r6,37
+ 800ba58:	1000141e 	bne	r2,zero,800baac <_calloc_r+0x80>
+ 800ba5c:	30800530 	cmpltui	r2,r6,20
+ 800ba60:	10000826 	beq	r2,zero,800ba84 <_calloc_r+0x58>
+ 800ba64:	1805883a 	mov	r2,r3
+ 800ba68:	10000015 	stw	zero,0(r2)
+ 800ba6c:	10000115 	stw	zero,4(r2)
+ 800ba70:	10000215 	stw	zero,8(r2)
+ 800ba74:	1805883a 	mov	r2,r3
+ 800ba78:	dfc00017 	ldw	ra,0(sp)
+ 800ba7c:	dec00104 	addi	sp,sp,4
+ 800ba80:	f800283a 	ret
+ 800ba84:	18000015 	stw	zero,0(r3)
+ 800ba88:	18000115 	stw	zero,4(r3)
+ 800ba8c:	30800728 	cmpgeui	r2,r6,28
+ 800ba90:	10000e26 	beq	r2,zero,800bacc <_calloc_r+0xa0>
+ 800ba94:	18000215 	stw	zero,8(r3)
+ 800ba98:	18000315 	stw	zero,12(r3)
+ 800ba9c:	31800920 	cmpeqi	r6,r6,36
+ 800baa0:	30000c1e 	bne	r6,zero,800bad4 <_calloc_r+0xa8>
+ 800baa4:	18800404 	addi	r2,r3,16
+ 800baa8:	003fef06 	br	800ba68 <_calloc_r+0x3c>
+ 800baac:	1809883a 	mov	r4,r3
+ 800bab0:	000b883a 	mov	r5,zero
+ 800bab4:	80088e40 	call	80088e4 <memset>
+ 800bab8:	1007883a 	mov	r3,r2
+ 800babc:	1805883a 	mov	r2,r3
+ 800bac0:	dfc00017 	ldw	ra,0(sp)
+ 800bac4:	dec00104 	addi	sp,sp,4
+ 800bac8:	f800283a 	ret
+ 800bacc:	18800204 	addi	r2,r3,8
+ 800bad0:	003fe506 	br	800ba68 <_calloc_r+0x3c>
+ 800bad4:	18000415 	stw	zero,16(r3)
+ 800bad8:	18800604 	addi	r2,r3,24
+ 800badc:	18000515 	stw	zero,20(r3)
+ 800bae0:	003fe106 	br	800ba68 <_calloc_r+0x3c>
+
+0800bae4 <_fclose_r>:
+ 800bae4:	defffc04 	addi	sp,sp,-16
+ 800bae8:	dfc00315 	stw	ra,12(sp)
+ 800baec:	dc800215 	stw	r18,8(sp)
+ 800baf0:	dc400115 	stw	r17,4(sp)
+ 800baf4:	dc000015 	stw	r16,0(sp)
+ 800baf8:	28000726 	beq	r5,zero,800bb18 <_fclose_r+0x34>
+ 800bafc:	2023883a 	mov	r17,r4
+ 800bb00:	2821883a 	mov	r16,r5
+ 800bb04:	20000226 	beq	r4,zero,800bb10 <_fclose_r+0x2c>
+ 800bb08:	20800e17 	ldw	r2,56(r4)
+ 800bb0c:	10002726 	beq	r2,zero,800bbac <_fclose_r+0xc8>
+ 800bb10:	8080030f 	ldh	r2,12(r16)
+ 800bb14:	1000081e 	bne	r2,zero,800bb38 <_fclose_r+0x54>
+ 800bb18:	0025883a 	mov	r18,zero
+ 800bb1c:	9005883a 	mov	r2,r18
+ 800bb20:	dfc00317 	ldw	ra,12(sp)
+ 800bb24:	dc800217 	ldw	r18,8(sp)
+ 800bb28:	dc400117 	ldw	r17,4(sp)
+ 800bb2c:	dc000017 	ldw	r16,0(sp)
+ 800bb30:	dec00404 	addi	sp,sp,16
+ 800bb34:	f800283a 	ret
+ 800bb38:	800b883a 	mov	r5,r16
+ 800bb3c:	8809883a 	mov	r4,r17
+ 800bb40:	8006ab40 	call	8006ab4 <__sflush_r>
+ 800bb44:	1025883a 	mov	r18,r2
+ 800bb48:	80800b17 	ldw	r2,44(r16)
+ 800bb4c:	10000426 	beq	r2,zero,800bb60 <_fclose_r+0x7c>
+ 800bb50:	81400717 	ldw	r5,28(r16)
+ 800bb54:	8809883a 	mov	r4,r17
+ 800bb58:	103ee83a 	callr	r2
+ 800bb5c:	10001716 	blt	r2,zero,800bbbc <_fclose_r+0xd8>
+ 800bb60:	8080030b 	ldhu	r2,12(r16)
+ 800bb64:	1080200c 	andi	r2,r2,128
+ 800bb68:	1000181e 	bne	r2,zero,800bbcc <_fclose_r+0xe8>
+ 800bb6c:	81400c17 	ldw	r5,48(r16)
+ 800bb70:	28000526 	beq	r5,zero,800bb88 <_fclose_r+0xa4>
+ 800bb74:	80801004 	addi	r2,r16,64
+ 800bb78:	28800226 	beq	r5,r2,800bb84 <_fclose_r+0xa0>
+ 800bb7c:	8809883a 	mov	r4,r17
+ 800bb80:	80071c40 	call	80071c4 <_free_r>
+ 800bb84:	80000c15 	stw	zero,48(r16)
+ 800bb88:	81401117 	ldw	r5,68(r16)
+ 800bb8c:	28000326 	beq	r5,zero,800bb9c <_fclose_r+0xb8>
+ 800bb90:	8809883a 	mov	r4,r17
+ 800bb94:	80071c40 	call	80071c4 <_free_r>
+ 800bb98:	80001115 	stw	zero,68(r16)
+ 800bb9c:	80070700 	call	8007070 <__sfp_lock_acquire>
+ 800bba0:	8000030d 	sth	zero,12(r16)
+ 800bba4:	80070740 	call	8007074 <__sfp_lock_release>
+ 800bba8:	003fdc06 	br	800bb1c <_fclose_r+0x38>
+ 800bbac:	80070600 	call	8007060 <__sinit>
+ 800bbb0:	8080030f 	ldh	r2,12(r16)
+ 800bbb4:	103fd826 	beq	r2,zero,800bb18 <_fclose_r+0x34>
+ 800bbb8:	003fdf06 	br	800bb38 <_fclose_r+0x54>
+ 800bbbc:	8080030b 	ldhu	r2,12(r16)
+ 800bbc0:	04bfffc4 	movi	r18,-1
+ 800bbc4:	1080200c 	andi	r2,r2,128
+ 800bbc8:	103fe826 	beq	r2,zero,800bb6c <_fclose_r+0x88>
+ 800bbcc:	81400417 	ldw	r5,16(r16)
+ 800bbd0:	8809883a 	mov	r4,r17
+ 800bbd4:	80071c40 	call	80071c4 <_free_r>
+ 800bbd8:	003fe406 	br	800bb6c <_fclose_r+0x88>
+
+0800bbdc <fclose>:
+ 800bbdc:	00820174 	movhi	r2,2053
+ 800bbe0:	200b883a 	mov	r5,r4
+ 800bbe4:	1132af17 	ldw	r4,-13636(r2)
+ 800bbe8:	800bae41 	jmpi	800bae4 <_fclose_r>
+
+0800bbec <__fputwc>:
+ 800bbec:	defff904 	addi	sp,sp,-28
+ 800bbf0:	dcc00415 	stw	r19,16(sp)
+ 800bbf4:	dc800315 	stw	r18,12(sp)
+ 800bbf8:	dc000115 	stw	r16,4(sp)
+ 800bbfc:	dfc00615 	stw	ra,24(sp)
+ 800bc00:	dd000515 	stw	r20,20(sp)
+ 800bc04:	dc400215 	stw	r17,8(sp)
+ 800bc08:	2025883a 	mov	r18,r4
+ 800bc0c:	2827883a 	mov	r19,r5
+ 800bc10:	3021883a 	mov	r16,r6
+ 800bc14:	800bf040 	call	800bf04 <__locale_mb_cur_max>
+ 800bc18:	10800058 	cmpnei	r2,r2,1
+ 800bc1c:	1000071e 	bne	r2,zero,800bc3c <__fputwc+0x50>
+ 800bc20:	98bfffc4 	addi	r2,r19,-1
+ 800bc24:	10803fe8 	cmpgeui	r2,r2,255
+ 800bc28:	1000041e 	bne	r2,zero,800bc3c <__fputwc+0x50>
+ 800bc2c:	980b883a 	mov	r5,r19
+ 800bc30:	dcc000c5 	stb	r19,3(sp)
+ 800bc34:	05000044 	movi	r20,1
+ 800bc38:	00000a06 	br	800bc64 <__fputwc+0x78>
+ 800bc3c:	81c01704 	addi	r7,r16,92
+ 800bc40:	980d883a 	mov	r6,r19
+ 800bc44:	d94000c4 	addi	r5,sp,3
+ 800bc48:	9009883a 	mov	r4,r18
+ 800bc4c:	800c2fc0 	call	800c2fc <_wcrtomb_r>
+ 800bc50:	1029883a 	mov	r20,r2
+ 800bc54:	10bfffd8 	cmpnei	r2,r2,-1
+ 800bc58:	10003426 	beq	r2,zero,800bd2c <__fputwc+0x140>
+ 800bc5c:	a0002926 	beq	r20,zero,800bd04 <__fputwc+0x118>
+ 800bc60:	d94000c3 	ldbu	r5,3(sp)
+ 800bc64:	0023883a 	mov	r17,zero
+ 800bc68:	00000a06 	br	800bc94 <__fputwc+0xa8>
+ 800bc6c:	80800017 	ldw	r2,0(r16)
+ 800bc70:	11400005 	stb	r5,0(r2)
+ 800bc74:	80800017 	ldw	r2,0(r16)
+ 800bc78:	10800044 	addi	r2,r2,1
+ 800bc7c:	80800015 	stw	r2,0(r16)
+ 800bc80:	8c400044 	addi	r17,r17,1
+ 800bc84:	d88000c4 	addi	r2,sp,3
+ 800bc88:	1445883a 	add	r2,r2,r17
+ 800bc8c:	8d001d2e 	bgeu	r17,r20,800bd04 <__fputwc+0x118>
+ 800bc90:	11400003 	ldbu	r5,0(r2)
+ 800bc94:	80800217 	ldw	r2,8(r16)
+ 800bc98:	10bfffc4 	addi	r2,r2,-1
+ 800bc9c:	80800215 	stw	r2,8(r16)
+ 800bca0:	103ff20e 	bge	r2,zero,800bc6c <__fputwc+0x80>
+ 800bca4:	80c00617 	ldw	r3,24(r16)
+ 800bca8:	10c01016 	blt	r2,r3,800bcec <__fputwc+0x100>
+ 800bcac:	80800017 	ldw	r2,0(r16)
+ 800bcb0:	11400005 	stb	r5,0(r2)
+ 800bcb4:	80800017 	ldw	r2,0(r16)
+ 800bcb8:	10c00003 	ldbu	r3,0(r2)
+ 800bcbc:	10800044 	addi	r2,r2,1
+ 800bcc0:	18c002a0 	cmpeqi	r3,r3,10
+ 800bcc4:	183fed26 	beq	r3,zero,800bc7c <__fputwc+0x90>
+ 800bcc8:	800d883a 	mov	r6,r16
+ 800bccc:	01400284 	movi	r5,10
+ 800bcd0:	9009883a 	mov	r4,r18
+ 800bcd4:	800b8140 	call	800b814 <__swbuf_r>
+ 800bcd8:	10bfffe0 	cmpeqi	r2,r2,-1
+ 800bcdc:	10803fcc 	andi	r2,r2,255
+ 800bce0:	103fe726 	beq	r2,zero,800bc80 <__fputwc+0x94>
+ 800bce4:	053fffc4 	movi	r20,-1
+ 800bce8:	00000706 	br	800bd08 <__fputwc+0x11c>
+ 800bcec:	29403fcc 	andi	r5,r5,255
+ 800bcf0:	800d883a 	mov	r6,r16
+ 800bcf4:	9009883a 	mov	r4,r18
+ 800bcf8:	800b8140 	call	800b814 <__swbuf_r>
+ 800bcfc:	10bfffe0 	cmpeqi	r2,r2,-1
+ 800bd00:	003ff606 	br	800bcdc <__fputwc+0xf0>
+ 800bd04:	9829883a 	mov	r20,r19
+ 800bd08:	a005883a 	mov	r2,r20
+ 800bd0c:	dfc00617 	ldw	ra,24(sp)
+ 800bd10:	dd000517 	ldw	r20,20(sp)
+ 800bd14:	dcc00417 	ldw	r19,16(sp)
+ 800bd18:	dc800317 	ldw	r18,12(sp)
+ 800bd1c:	dc400217 	ldw	r17,8(sp)
+ 800bd20:	dc000117 	ldw	r16,4(sp)
+ 800bd24:	dec00704 	addi	sp,sp,28
+ 800bd28:	f800283a 	ret
+ 800bd2c:	8080030b 	ldhu	r2,12(r16)
+ 800bd30:	10801014 	ori	r2,r2,64
+ 800bd34:	8080030d 	sth	r2,12(r16)
+ 800bd38:	003ff306 	br	800bd08 <__fputwc+0x11c>
+
+0800bd3c <_fputwc_r>:
+ 800bd3c:	3080030b 	ldhu	r2,12(r6)
+ 800bd40:	10c8000c 	andi	r3,r2,8192
+ 800bd44:	1800051e 	bne	r3,zero,800bd5c <_fputwc_r+0x20>
+ 800bd48:	30c01917 	ldw	r3,100(r6)
+ 800bd4c:	10880014 	ori	r2,r2,8192
+ 800bd50:	3080030d 	sth	r2,12(r6)
+ 800bd54:	18880014 	ori	r2,r3,8192
+ 800bd58:	30801915 	stw	r2,100(r6)
+ 800bd5c:	800bbec1 	jmpi	800bbec <__fputwc>
+
+0800bd60 <fputwc>:
+ 800bd60:	defffc04 	addi	sp,sp,-16
+ 800bd64:	00820174 	movhi	r2,2053
+ 800bd68:	dc000115 	stw	r16,4(sp)
+ 800bd6c:	1432af17 	ldw	r16,-13636(r2)
+ 800bd70:	dc400215 	stw	r17,8(sp)
+ 800bd74:	dfc00315 	stw	ra,12(sp)
+ 800bd78:	2023883a 	mov	r17,r4
+ 800bd7c:	80000226 	beq	r16,zero,800bd88 <fputwc+0x28>
+ 800bd80:	80800e17 	ldw	r2,56(r16)
+ 800bd84:	10001026 	beq	r2,zero,800bdc8 <fputwc+0x68>
+ 800bd88:	2880030b 	ldhu	r2,12(r5)
+ 800bd8c:	10c8000c 	andi	r3,r2,8192
+ 800bd90:	1800051e 	bne	r3,zero,800bda8 <fputwc+0x48>
+ 800bd94:	28c01917 	ldw	r3,100(r5)
+ 800bd98:	10880014 	ori	r2,r2,8192
+ 800bd9c:	2880030d 	sth	r2,12(r5)
+ 800bda0:	18880014 	ori	r2,r3,8192
+ 800bda4:	28801915 	stw	r2,100(r5)
+ 800bda8:	280d883a 	mov	r6,r5
+ 800bdac:	8009883a 	mov	r4,r16
+ 800bdb0:	880b883a 	mov	r5,r17
+ 800bdb4:	dfc00317 	ldw	ra,12(sp)
+ 800bdb8:	dc400217 	ldw	r17,8(sp)
+ 800bdbc:	dc000117 	ldw	r16,4(sp)
+ 800bdc0:	dec00404 	addi	sp,sp,16
+ 800bdc4:	800bbec1 	jmpi	800bbec <__fputwc>
+ 800bdc8:	8009883a 	mov	r4,r16
+ 800bdcc:	d9400015 	stw	r5,0(sp)
+ 800bdd0:	80070600 	call	8007060 <__sinit>
+ 800bdd4:	d9400017 	ldw	r5,0(sp)
+ 800bdd8:	003feb06 	br	800bd88 <fputwc+0x28>
+
+0800bddc <_fstat_r>:
+ 800bddc:	defffe04 	addi	sp,sp,-8
+ 800bde0:	2805883a 	mov	r2,r5
+ 800bde4:	dc000015 	stw	r16,0(sp)
+ 800bde8:	300b883a 	mov	r5,r6
+ 800bdec:	2021883a 	mov	r16,r4
+ 800bdf0:	1009883a 	mov	r4,r2
+ 800bdf4:	00820174 	movhi	r2,2053
+ 800bdf8:	dfc00115 	stw	ra,4(sp)
+ 800bdfc:	1032f015 	stw	zero,-13376(r2)
+ 800be00:	800f8dc0 	call	800f8dc <fstat>
+ 800be04:	10ffffd8 	cmpnei	r3,r2,-1
+ 800be08:	18000426 	beq	r3,zero,800be1c <_fstat_r+0x40>
+ 800be0c:	dfc00117 	ldw	ra,4(sp)
+ 800be10:	dc000017 	ldw	r16,0(sp)
+ 800be14:	dec00204 	addi	sp,sp,8
+ 800be18:	f800283a 	ret
+ 800be1c:	00c20174 	movhi	r3,2053
+ 800be20:	18f2f017 	ldw	r3,-13376(r3)
+ 800be24:	183ff926 	beq	r3,zero,800be0c <_fstat_r+0x30>
+ 800be28:	80c00015 	stw	r3,0(r16)
+ 800be2c:	dfc00117 	ldw	ra,4(sp)
+ 800be30:	dc000017 	ldw	r16,0(sp)
+ 800be34:	dec00204 	addi	sp,sp,8
+ 800be38:	f800283a 	ret
+
+0800be3c <_isatty_r>:
+ 800be3c:	defffe04 	addi	sp,sp,-8
+ 800be40:	dc000015 	stw	r16,0(sp)
+ 800be44:	00820174 	movhi	r2,2053
+ 800be48:	2021883a 	mov	r16,r4
+ 800be4c:	2809883a 	mov	r4,r5
+ 800be50:	dfc00115 	stw	ra,4(sp)
+ 800be54:	1032f015 	stw	zero,-13376(r2)
+ 800be58:	800f9c80 	call	800f9c8 <isatty>
+ 800be5c:	10ffffd8 	cmpnei	r3,r2,-1
+ 800be60:	18000426 	beq	r3,zero,800be74 <_isatty_r+0x38>
+ 800be64:	dfc00117 	ldw	ra,4(sp)
+ 800be68:	dc000017 	ldw	r16,0(sp)
+ 800be6c:	dec00204 	addi	sp,sp,8
+ 800be70:	f800283a 	ret
+ 800be74:	00c20174 	movhi	r3,2053
+ 800be78:	18f2f017 	ldw	r3,-13376(r3)
+ 800be7c:	183ff926 	beq	r3,zero,800be64 <_isatty_r+0x28>
+ 800be80:	80c00015 	stw	r3,0(r16)
+ 800be84:	dfc00117 	ldw	ra,4(sp)
+ 800be88:	dc000017 	ldw	r16,0(sp)
+ 800be8c:	dec00204 	addi	sp,sp,8
+ 800be90:	f800283a 	ret
+
+0800be94 <_setlocale_r>:
+ 800be94:	30001826 	beq	r6,zero,800bef8 <_setlocale_r+0x64>
+ 800be98:	01420134 	movhi	r5,2052
+ 800be9c:	defffe04 	addi	sp,sp,-8
+ 800bea0:	295d8604 	addi	r5,r5,30232
+ 800bea4:	3009883a 	mov	r4,r6
+ 800bea8:	dc000015 	stw	r16,0(sp)
+ 800beac:	dfc00115 	stw	ra,4(sp)
+ 800beb0:	3021883a 	mov	r16,r6
+ 800beb4:	800c2240 	call	800c224 <strcmp>
+ 800beb8:	1000061e 	bne	r2,zero,800bed4 <_setlocale_r+0x40>
+ 800bebc:	00820134 	movhi	r2,2052
+ 800bec0:	109d8504 	addi	r2,r2,30228
+ 800bec4:	dfc00117 	ldw	ra,4(sp)
+ 800bec8:	dc000017 	ldw	r16,0(sp)
+ 800becc:	dec00204 	addi	sp,sp,8
+ 800bed0:	f800283a 	ret
+ 800bed4:	01420134 	movhi	r5,2052
+ 800bed8:	295d8504 	addi	r5,r5,30228
+ 800bedc:	8009883a 	mov	r4,r16
+ 800bee0:	800c2240 	call	800c224 <strcmp>
+ 800bee4:	103ff526 	beq	r2,zero,800bebc <_setlocale_r+0x28>
+ 800bee8:	80800003 	ldbu	r2,0(r16)
+ 800beec:	103ff326 	beq	r2,zero,800bebc <_setlocale_r+0x28>
+ 800bef0:	0005883a 	mov	r2,zero
+ 800bef4:	003ff306 	br	800bec4 <_setlocale_r+0x30>
+ 800bef8:	00820134 	movhi	r2,2052
+ 800befc:	109d8504 	addi	r2,r2,30228
+ 800bf00:	f800283a 	ret
+
+0800bf04 <__locale_mb_cur_max>:
+ 800bf04:	00820174 	movhi	r2,2053
+ 800bf08:	10b0f507 	ldb	r2,-15404(r2)
+ 800bf0c:	f800283a 	ret
+
+0800bf10 <setlocale>:
+ 800bf10:	00820174 	movhi	r2,2053
+ 800bf14:	280d883a 	mov	r6,r5
+ 800bf18:	200b883a 	mov	r5,r4
+ 800bf1c:	1132af17 	ldw	r4,-13636(r2)
+ 800bf20:	800be941 	jmpi	800be94 <_setlocale_r>
+
+0800bf24 <_lseek_r>:
+ 800bf24:	defffe04 	addi	sp,sp,-8
+ 800bf28:	2805883a 	mov	r2,r5
+ 800bf2c:	dc000015 	stw	r16,0(sp)
+ 800bf30:	300b883a 	mov	r5,r6
+ 800bf34:	2021883a 	mov	r16,r4
+ 800bf38:	380d883a 	mov	r6,r7
+ 800bf3c:	1009883a 	mov	r4,r2
+ 800bf40:	00820174 	movhi	r2,2053
+ 800bf44:	dfc00115 	stw	ra,4(sp)
+ 800bf48:	1032f015 	stw	zero,-13376(r2)
+ 800bf4c:	800faa80 	call	800faa8 <lseek>
+ 800bf50:	10ffffd8 	cmpnei	r3,r2,-1
+ 800bf54:	18000426 	beq	r3,zero,800bf68 <_lseek_r+0x44>
+ 800bf58:	dfc00117 	ldw	ra,4(sp)
+ 800bf5c:	dc000017 	ldw	r16,0(sp)
+ 800bf60:	dec00204 	addi	sp,sp,8
+ 800bf64:	f800283a 	ret
+ 800bf68:	00c20174 	movhi	r3,2053
+ 800bf6c:	18f2f017 	ldw	r3,-13376(r3)
+ 800bf70:	183ff926 	beq	r3,zero,800bf58 <_lseek_r+0x34>
+ 800bf74:	80c00015 	stw	r3,0(r16)
+ 800bf78:	dfc00117 	ldw	ra,4(sp)
+ 800bf7c:	dc000017 	ldw	r16,0(sp)
+ 800bf80:	dec00204 	addi	sp,sp,8
+ 800bf84:	f800283a 	ret
+
+0800bf88 <_mbtowc_r>:
+ 800bf88:	00820174 	movhi	r2,2053
+ 800bf8c:	10b0e417 	ldw	r2,-15472(r2)
+ 800bf90:	1000683a 	jmp	r2
+
+0800bf94 <__ascii_mbtowc>:
+ 800bf94:	deffff04 	addi	sp,sp,-4
+ 800bf98:	28000826 	beq	r5,zero,800bfbc <__ascii_mbtowc+0x28>
+ 800bf9c:	30000926 	beq	r6,zero,800bfc4 <__ascii_mbtowc+0x30>
+ 800bfa0:	38000b26 	beq	r7,zero,800bfd0 <__ascii_mbtowc+0x3c>
+ 800bfa4:	30800003 	ldbu	r2,0(r6)
+ 800bfa8:	28800015 	stw	r2,0(r5)
+ 800bfac:	30800003 	ldbu	r2,0(r6)
+ 800bfb0:	1004c03a 	cmpne	r2,r2,zero
+ 800bfb4:	dec00104 	addi	sp,sp,4
+ 800bfb8:	f800283a 	ret
+ 800bfbc:	d80b883a 	mov	r5,sp
+ 800bfc0:	303ff71e 	bne	r6,zero,800bfa0 <__ascii_mbtowc+0xc>
+ 800bfc4:	0005883a 	mov	r2,zero
+ 800bfc8:	dec00104 	addi	sp,sp,4
+ 800bfcc:	f800283a 	ret
+ 800bfd0:	00bfff84 	movi	r2,-2
+ 800bfd4:	003ff706 	br	800bfb4 <__ascii_mbtowc+0x20>
+
+0800bfd8 <_read_r>:
+ 800bfd8:	defffe04 	addi	sp,sp,-8
+ 800bfdc:	2805883a 	mov	r2,r5
+ 800bfe0:	dc000015 	stw	r16,0(sp)
+ 800bfe4:	300b883a 	mov	r5,r6
+ 800bfe8:	2021883a 	mov	r16,r4
+ 800bfec:	380d883a 	mov	r6,r7
+ 800bff0:	1009883a 	mov	r4,r2
+ 800bff4:	00820174 	movhi	r2,2053
+ 800bff8:	dfc00115 	stw	ra,4(sp)
+ 800bffc:	1032f015 	stw	zero,-13376(r2)
+ 800c000:	8022bcc0 	call	8022bcc <read>
+ 800c004:	10ffffd8 	cmpnei	r3,r2,-1
+ 800c008:	18000426 	beq	r3,zero,800c01c <_read_r+0x44>
+ 800c00c:	dfc00117 	ldw	ra,4(sp)
+ 800c010:	dc000017 	ldw	r16,0(sp)
+ 800c014:	dec00204 	addi	sp,sp,8
+ 800c018:	f800283a 	ret
+ 800c01c:	00c20174 	movhi	r3,2053
+ 800c020:	18f2f017 	ldw	r3,-13376(r3)
+ 800c024:	183ff926 	beq	r3,zero,800c00c <_read_r+0x34>
+ 800c028:	80c00015 	stw	r3,0(r16)
+ 800c02c:	dfc00117 	ldw	ra,4(sp)
+ 800c030:	dc000017 	ldw	r16,0(sp)
+ 800c034:	dec00204 	addi	sp,sp,8
+ 800c038:	f800283a 	ret
+
+0800c03c <lflush>:
+ 800c03c:	2080030b 	ldhu	r2,12(r4)
+ 800c040:	1080024c 	andi	r2,r2,9
+ 800c044:	10800258 	cmpnei	r2,r2,9
+ 800c048:	10000226 	beq	r2,zero,800c054 <lflush+0x18>
+ 800c04c:	0005883a 	mov	r2,zero
+ 800c050:	f800283a 	ret
+ 800c054:	8006d3c1 	jmpi	8006d3c <fflush>
+
+0800c058 <__srefill_r>:
+ 800c058:	defffc04 	addi	sp,sp,-16
+ 800c05c:	dc400115 	stw	r17,4(sp)
+ 800c060:	dc000015 	stw	r16,0(sp)
+ 800c064:	dfc00315 	stw	ra,12(sp)
+ 800c068:	dc800215 	stw	r18,8(sp)
+ 800c06c:	2023883a 	mov	r17,r4
+ 800c070:	2821883a 	mov	r16,r5
+ 800c074:	20000226 	beq	r4,zero,800c080 <__srefill_r+0x28>
+ 800c078:	20800e17 	ldw	r2,56(r4)
+ 800c07c:	10003a26 	beq	r2,zero,800c168 <__srefill_r+0x110>
+ 800c080:	80c0030b 	ldhu	r3,12(r16)
+ 800c084:	1908000c 	andi	r4,r3,8192
+ 800c088:	1805883a 	mov	r2,r3
+ 800c08c:	2000071e 	bne	r4,zero,800c0ac <__srefill_r+0x54>
+ 800c090:	81001917 	ldw	r4,100(r16)
+ 800c094:	18880014 	ori	r2,r3,8192
+ 800c098:	00f7ffc4 	movi	r3,-8193
+ 800c09c:	20c8703a 	and	r4,r4,r3
+ 800c0a0:	8080030d 	sth	r2,12(r16)
+ 800c0a4:	1007883a 	mov	r3,r2
+ 800c0a8:	81001915 	stw	r4,100(r16)
+ 800c0ac:	80000115 	stw	zero,4(r16)
+ 800c0b0:	1100080c 	andi	r4,r2,32
+ 800c0b4:	20004d1e 	bne	r4,zero,800c1ec <__srefill_r+0x194>
+ 800c0b8:	1100010c 	andi	r4,r2,4
+ 800c0bc:	20001c1e 	bne	r4,zero,800c130 <__srefill_r+0xd8>
+ 800c0c0:	1100040c 	andi	r4,r2,16
+ 800c0c4:	20005126 	beq	r4,zero,800c20c <__srefill_r+0x1b4>
+ 800c0c8:	1080020c 	andi	r2,r2,8
+ 800c0cc:	1000371e 	bne	r2,zero,800c1ac <__srefill_r+0x154>
+ 800c0d0:	18c00114 	ori	r3,r3,4
+ 800c0d4:	80c0030d 	sth	r3,12(r16)
+ 800c0d8:	80800417 	ldw	r2,16(r16)
+ 800c0dc:	10003c26 	beq	r2,zero,800c1d0 <__srefill_r+0x178>
+ 800c0e0:	8480030b 	ldhu	r18,12(r16)
+ 800c0e4:	908000cc 	andi	r2,r18,3
+ 800c0e8:	1000211e 	bne	r2,zero,800c170 <__srefill_r+0x118>
+ 800c0ec:	81800417 	ldw	r6,16(r16)
+ 800c0f0:	80800817 	ldw	r2,32(r16)
+ 800c0f4:	81c00517 	ldw	r7,20(r16)
+ 800c0f8:	81400717 	ldw	r5,28(r16)
+ 800c0fc:	81800015 	stw	r6,0(r16)
+ 800c100:	8809883a 	mov	r4,r17
+ 800c104:	103ee83a 	callr	r2
+ 800c108:	1007883a 	mov	r3,r2
+ 800c10c:	80800115 	stw	r2,4(r16)
+ 800c110:	0005883a 	mov	r2,zero
+ 800c114:	00c0370e 	bge	zero,r3,800c1f4 <__srefill_r+0x19c>
+ 800c118:	dfc00317 	ldw	ra,12(sp)
+ 800c11c:	dc800217 	ldw	r18,8(sp)
+ 800c120:	dc400117 	ldw	r17,4(sp)
+ 800c124:	dc000017 	ldw	r16,0(sp)
+ 800c128:	dec00404 	addi	sp,sp,16
+ 800c12c:	f800283a 	ret
+ 800c130:	81400c17 	ldw	r5,48(r16)
+ 800c134:	283fe826 	beq	r5,zero,800c0d8 <__srefill_r+0x80>
+ 800c138:	80801004 	addi	r2,r16,64
+ 800c13c:	28800226 	beq	r5,r2,800c148 <__srefill_r+0xf0>
+ 800c140:	8809883a 	mov	r4,r17
+ 800c144:	80071c40 	call	80071c4 <_free_r>
+ 800c148:	80800f17 	ldw	r2,60(r16)
+ 800c14c:	80000c15 	stw	zero,48(r16)
+ 800c150:	80800115 	stw	r2,4(r16)
+ 800c154:	103fe026 	beq	r2,zero,800c0d8 <__srefill_r+0x80>
+ 800c158:	80c00e17 	ldw	r3,56(r16)
+ 800c15c:	0005883a 	mov	r2,zero
+ 800c160:	80c00015 	stw	r3,0(r16)
+ 800c164:	003fec06 	br	800c118 <__srefill_r+0xc0>
+ 800c168:	80070600 	call	8007060 <__sinit>
+ 800c16c:	003fc406 	br	800c080 <__srefill_r+0x28>
+ 800c170:	00820174 	movhi	r2,2053
+ 800c174:	1132ae17 	ldw	r4,-13640(r2)
+ 800c178:	01420074 	movhi	r5,2049
+ 800c17c:	00800044 	movi	r2,1
+ 800c180:	8080030d 	sth	r2,12(r16)
+ 800c184:	29700f04 	addi	r5,r5,-16324
+ 800c188:	80079840 	call	8007984 <_fwalk>
+ 800c18c:	9080024c 	andi	r2,r18,9
+ 800c190:	8480030d 	sth	r18,12(r16)
+ 800c194:	10800258 	cmpnei	r2,r2,9
+ 800c198:	103fd41e 	bne	r2,zero,800c0ec <__srefill_r+0x94>
+ 800c19c:	800b883a 	mov	r5,r16
+ 800c1a0:	8809883a 	mov	r4,r17
+ 800c1a4:	8006ab40 	call	8006ab4 <__sflush_r>
+ 800c1a8:	003fd006 	br	800c0ec <__srefill_r+0x94>
+ 800c1ac:	800b883a 	mov	r5,r16
+ 800c1b0:	8809883a 	mov	r4,r17
+ 800c1b4:	8006cdc0 	call	8006cdc <_fflush_r>
+ 800c1b8:	10000c1e 	bne	r2,zero,800c1ec <__srefill_r+0x194>
+ 800c1bc:	80c0030b 	ldhu	r3,12(r16)
+ 800c1c0:	80000215 	stw	zero,8(r16)
+ 800c1c4:	80000615 	stw	zero,24(r16)
+ 800c1c8:	18fffdcc 	andi	r3,r3,65527
+ 800c1cc:	003fc006 	br	800c0d0 <__srefill_r+0x78>
+ 800c1d0:	800b883a 	mov	r5,r16
+ 800c1d4:	8809883a 	mov	r4,r17
+ 800c1d8:	8007ca00 	call	8007ca0 <__smakebuf_r>
+ 800c1dc:	003fc006 	br	800c0e0 <__srefill_r+0x88>
+ 800c1e0:	10801014 	ori	r2,r2,64
+ 800c1e4:	80000115 	stw	zero,4(r16)
+ 800c1e8:	8080030d 	sth	r2,12(r16)
+ 800c1ec:	00bfffc4 	movi	r2,-1
+ 800c1f0:	003fc906 	br	800c118 <__srefill_r+0xc0>
+ 800c1f4:	8080030b 	ldhu	r2,12(r16)
+ 800c1f8:	183ff91e 	bne	r3,zero,800c1e0 <__srefill_r+0x188>
+ 800c1fc:	10800814 	ori	r2,r2,32
+ 800c200:	8080030d 	sth	r2,12(r16)
+ 800c204:	00bfffc4 	movi	r2,-1
+ 800c208:	003fc306 	br	800c118 <__srefill_r+0xc0>
+ 800c20c:	00800244 	movi	r2,9
+ 800c210:	88800015 	stw	r2,0(r17)
+ 800c214:	18c01014 	ori	r3,r3,64
+ 800c218:	80c0030d 	sth	r3,12(r16)
+ 800c21c:	00bfffc4 	movi	r2,-1
+ 800c220:	003fbd06 	br	800c118 <__srefill_r+0xc0>
+
+0800c224 <strcmp>:
+ 800c224:	2144b03a 	or	r2,r4,r5
+ 800c228:	108000cc 	andi	r2,r2,3
+ 800c22c:	1000171e 	bne	r2,zero,800c28c <strcmp+0x68>
+ 800c230:	20800017 	ldw	r2,0(r4)
+ 800c234:	28c00017 	ldw	r3,0(r5)
+ 800c238:	10c0141e 	bne	r2,r3,800c28c <strcmp+0x68>
+ 800c23c:	027fbff4 	movhi	r9,65279
+ 800c240:	4a7fbfc4 	addi	r9,r9,-257
+ 800c244:	1247883a 	add	r3,r2,r9
+ 800c248:	02202074 	movhi	r8,32897
+ 800c24c:	0084303a 	nor	r2,zero,r2
+ 800c250:	1884703a 	and	r2,r3,r2
+ 800c254:	42202004 	addi	r8,r8,-32640
+ 800c258:	1204703a 	and	r2,r2,r8
+ 800c25c:	10000226 	beq	r2,zero,800c268 <strcmp+0x44>
+ 800c260:	00002406 	br	800c2f4 <strcmp+0xd0>
+ 800c264:	1000231e 	bne	r2,zero,800c2f4 <strcmp+0xd0>
+ 800c268:	21000104 	addi	r4,r4,4
+ 800c26c:	20c00017 	ldw	r3,0(r4)
+ 800c270:	29400104 	addi	r5,r5,4
+ 800c274:	29800017 	ldw	r6,0(r5)
+ 800c278:	1a45883a 	add	r2,r3,r9
+ 800c27c:	00ce303a 	nor	r7,zero,r3
+ 800c280:	11c4703a 	and	r2,r2,r7
+ 800c284:	1204703a 	and	r2,r2,r8
+ 800c288:	19bff626 	beq	r3,r6,800c264 <strcmp+0x40>
+ 800c28c:	20800003 	ldbu	r2,0(r4)
+ 800c290:	10c03fcc 	andi	r3,r2,255
+ 800c294:	18c0201c 	xori	r3,r3,128
+ 800c298:	18ffe004 	addi	r3,r3,-128
+ 800c29c:	18000d26 	beq	r3,zero,800c2d4 <strcmp+0xb0>
+ 800c2a0:	29800007 	ldb	r6,0(r5)
+ 800c2a4:	10803fcc 	andi	r2,r2,255
+ 800c2a8:	19800326 	beq	r3,r6,800c2b8 <strcmp+0x94>
+ 800c2ac:	00000a06 	br	800c2d8 <strcmp+0xb4>
+ 800c2b0:	29800007 	ldb	r6,0(r5)
+ 800c2b4:	11800b1e 	bne	r2,r6,800c2e4 <strcmp+0xc0>
+ 800c2b8:	21000044 	addi	r4,r4,1
+ 800c2bc:	20c00003 	ldbu	r3,0(r4)
+ 800c2c0:	29400044 	addi	r5,r5,1
+ 800c2c4:	18803fcc 	andi	r2,r3,255
+ 800c2c8:	1080201c 	xori	r2,r2,128
+ 800c2cc:	10bfe004 	addi	r2,r2,-128
+ 800c2d0:	103ff71e 	bne	r2,zero,800c2b0 <strcmp+0x8c>
+ 800c2d4:	0005883a 	mov	r2,zero
+ 800c2d8:	28c00003 	ldbu	r3,0(r5)
+ 800c2dc:	10c5c83a 	sub	r2,r2,r3
+ 800c2e0:	f800283a 	ret
+ 800c2e4:	18803fcc 	andi	r2,r3,255
+ 800c2e8:	28c00003 	ldbu	r3,0(r5)
+ 800c2ec:	10c5c83a 	sub	r2,r2,r3
+ 800c2f0:	f800283a 	ret
+ 800c2f4:	0005883a 	mov	r2,zero
+ 800c2f8:	f800283a 	ret
+
+0800c2fc <_wcrtomb_r>:
+ 800c2fc:	defffa04 	addi	sp,sp,-24
+ 800c300:	dc400415 	stw	r17,16(sp)
+ 800c304:	dc000315 	stw	r16,12(sp)
+ 800c308:	00820174 	movhi	r2,2053
+ 800c30c:	dfc00515 	stw	ra,20(sp)
+ 800c310:	2021883a 	mov	r16,r4
+ 800c314:	3823883a 	mov	r17,r7
+ 800c318:	10b0e317 	ldw	r2,-15476(r2)
+ 800c31c:	28000826 	beq	r5,zero,800c340 <_wcrtomb_r+0x44>
+ 800c320:	103ee83a 	callr	r2
+ 800c324:	10ffffd8 	cmpnei	r3,r2,-1
+ 800c328:	18000a26 	beq	r3,zero,800c354 <_wcrtomb_r+0x58>
+ 800c32c:	dfc00517 	ldw	ra,20(sp)
+ 800c330:	dc400417 	ldw	r17,16(sp)
+ 800c334:	dc000317 	ldw	r16,12(sp)
+ 800c338:	dec00604 	addi	sp,sp,24
+ 800c33c:	f800283a 	ret
+ 800c340:	000d883a 	mov	r6,zero
+ 800c344:	d9400084 	addi	r5,sp,2
+ 800c348:	103ee83a 	callr	r2
+ 800c34c:	10ffffd8 	cmpnei	r3,r2,-1
+ 800c350:	183ff61e 	bne	r3,zero,800c32c <_wcrtomb_r+0x30>
+ 800c354:	00802284 	movi	r2,138
+ 800c358:	88000015 	stw	zero,0(r17)
+ 800c35c:	80800015 	stw	r2,0(r16)
+ 800c360:	00bfffc4 	movi	r2,-1
+ 800c364:	003ff106 	br	800c32c <_wcrtomb_r+0x30>
+
+0800c368 <wcrtomb>:
+ 800c368:	defffa04 	addi	sp,sp,-24
+ 800c36c:	00820174 	movhi	r2,2053
+ 800c370:	dc400415 	stw	r17,16(sp)
+ 800c374:	dc000315 	stw	r16,12(sp)
+ 800c378:	dfc00515 	stw	ra,20(sp)
+ 800c37c:	1432af17 	ldw	r16,-13636(r2)
+ 800c380:	00820174 	movhi	r2,2053
+ 800c384:	3023883a 	mov	r17,r6
+ 800c388:	10b0e317 	ldw	r2,-15476(r2)
+ 800c38c:	300f883a 	mov	r7,r6
+ 800c390:	20000b26 	beq	r4,zero,800c3c0 <wcrtomb+0x58>
+ 800c394:	280d883a 	mov	r6,r5
+ 800c398:	200b883a 	mov	r5,r4
+ 800c39c:	8009883a 	mov	r4,r16
+ 800c3a0:	103ee83a 	callr	r2
+ 800c3a4:	10ffffd8 	cmpnei	r3,r2,-1
+ 800c3a8:	18000b26 	beq	r3,zero,800c3d8 <wcrtomb+0x70>
+ 800c3ac:	dfc00517 	ldw	ra,20(sp)
+ 800c3b0:	dc400417 	ldw	r17,16(sp)
+ 800c3b4:	dc000317 	ldw	r16,12(sp)
+ 800c3b8:	dec00604 	addi	sp,sp,24
+ 800c3bc:	f800283a 	ret
+ 800c3c0:	000d883a 	mov	r6,zero
+ 800c3c4:	d9400084 	addi	r5,sp,2
+ 800c3c8:	8009883a 	mov	r4,r16
+ 800c3cc:	103ee83a 	callr	r2
+ 800c3d0:	10ffffd8 	cmpnei	r3,r2,-1
+ 800c3d4:	183ff51e 	bne	r3,zero,800c3ac <wcrtomb+0x44>
+ 800c3d8:	00802284 	movi	r2,138
+ 800c3dc:	88000015 	stw	zero,0(r17)
+ 800c3e0:	80800015 	stw	r2,0(r16)
+ 800c3e4:	00bfffc4 	movi	r2,-1
+ 800c3e8:	003ff006 	br	800c3ac <wcrtomb+0x44>
+
+0800c3ec <_wctomb_r>:
+ 800c3ec:	00820174 	movhi	r2,2053
+ 800c3f0:	10b0e317 	ldw	r2,-15476(r2)
+ 800c3f4:	1000683a 	jmp	r2
+
+0800c3f8 <__ascii_wctomb>:
+ 800c3f8:	28000926 	beq	r5,zero,800c420 <__ascii_wctomb+0x28>
+ 800c3fc:	30804030 	cmpltui	r2,r6,256
+ 800c400:	10000326 	beq	r2,zero,800c410 <__ascii_wctomb+0x18>
+ 800c404:	29800005 	stb	r6,0(r5)
+ 800c408:	00800044 	movi	r2,1
+ 800c40c:	f800283a 	ret
+ 800c410:	00802284 	movi	r2,138
+ 800c414:	20800015 	stw	r2,0(r4)
+ 800c418:	00bfffc4 	movi	r2,-1
+ 800c41c:	f800283a 	ret
+ 800c420:	0005883a 	mov	r2,zero
+ 800c424:	f800283a 	ret
+
+0800c428 <__udivdi3>:
+ 800c428:	defff504 	addi	sp,sp,-44
+ 800c42c:	dd400615 	stw	r21,24(sp)
+ 800c430:	dc000115 	stw	r16,4(sp)
+ 800c434:	dfc00a15 	stw	ra,40(sp)
+ 800c438:	df000915 	stw	fp,36(sp)
+ 800c43c:	ddc00815 	stw	r23,32(sp)
+ 800c440:	dd800715 	stw	r22,28(sp)
+ 800c444:	dd000515 	stw	r20,20(sp)
+ 800c448:	dcc00415 	stw	r19,16(sp)
+ 800c44c:	dc800315 	stw	r18,12(sp)
+ 800c450:	dc400215 	stw	r17,8(sp)
+ 800c454:	202b883a 	mov	r21,r4
+ 800c458:	2821883a 	mov	r16,r5
+ 800c45c:	3800821e 	bne	r7,zero,800c668 <__udivdi3+0x240>
+ 800c460:	3827883a 	mov	r19,r7
+ 800c464:	3023883a 	mov	r17,r6
+ 800c468:	2025883a 	mov	r18,r4
+ 800c46c:	29803d2e 	bgeu	r5,r6,800c564 <__udivdi3+0x13c>
+ 800c470:	00bfffd4 	movui	r2,65535
+ 800c474:	282d883a 	mov	r22,r5
+ 800c478:	1180a52e 	bgeu	r2,r6,800c710 <__udivdi3+0x2e8>
+ 800c47c:	00804034 	movhi	r2,256
+ 800c480:	30813836 	bltu	r6,r2,800c964 <__udivdi3+0x53c>
+ 800c484:	3006d63a 	srli	r3,r6,24
+ 800c488:	04c00604 	movi	r19,24
+ 800c48c:	00820134 	movhi	r2,2052
+ 800c490:	1885883a 	add	r2,r3,r2
+ 800c494:	109d8903 	ldbu	r2,30244(r2)
+ 800c498:	14e7883a 	add	r19,r2,r19
+ 800c49c:	00800804 	movi	r2,32
+ 800c4a0:	14c5c83a 	sub	r2,r2,r19
+ 800c4a4:	10000526 	beq	r2,zero,800c4bc <__udivdi3+0x94>
+ 800c4a8:	80a0983a 	sll	r16,r16,r2
+ 800c4ac:	ace6d83a 	srl	r19,r21,r19
+ 800c4b0:	30a2983a 	sll	r17,r6,r2
+ 800c4b4:	a8a4983a 	sll	r18,r21,r2
+ 800c4b8:	9c2cb03a 	or	r22,r19,r16
+ 800c4bc:	882ad43a 	srli	r21,r17,16
+ 800c4c0:	b009883a 	mov	r4,r22
+ 800c4c4:	8d3fffcc 	andi	r20,r17,65535
+ 800c4c8:	a80b883a 	mov	r5,r21
+ 800c4cc:	800d05c0 	call	800d05c <__umodsi3>
+ 800c4d0:	a80b883a 	mov	r5,r21
+ 800c4d4:	b009883a 	mov	r4,r22
+ 800c4d8:	1027883a 	mov	r19,r2
+ 800c4dc:	800cff80 	call	800cff8 <__udivsi3>
+ 800c4e0:	1021883a 	mov	r16,r2
+ 800c4e4:	9826943a 	slli	r19,r19,16
+ 800c4e8:	9004d43a 	srli	r2,r18,16
+ 800c4ec:	a407383a 	mul	r3,r20,r16
+ 800c4f0:	9884b03a 	or	r2,r19,r2
+ 800c4f4:	10c0052e 	bgeu	r2,r3,800c50c <__udivdi3+0xe4>
+ 800c4f8:	1445883a 	add	r2,r2,r17
+ 800c4fc:	813fffc4 	addi	r4,r16,-1
+ 800c500:	14400136 	bltu	r2,r17,800c508 <__udivdi3+0xe0>
+ 800c504:	10c12836 	bltu	r2,r3,800c9a8 <__udivdi3+0x580>
+ 800c508:	2021883a 	mov	r16,r4
+ 800c50c:	10e7c83a 	sub	r19,r2,r3
+ 800c510:	a80b883a 	mov	r5,r21
+ 800c514:	9809883a 	mov	r4,r19
+ 800c518:	800d05c0 	call	800d05c <__umodsi3>
+ 800c51c:	102d883a 	mov	r22,r2
+ 800c520:	a80b883a 	mov	r5,r21
+ 800c524:	9809883a 	mov	r4,r19
+ 800c528:	800cff80 	call	800cff8 <__udivsi3>
+ 800c52c:	b02c943a 	slli	r22,r22,16
+ 800c530:	a0a9383a 	mul	r20,r20,r2
+ 800c534:	94bfffcc 	andi	r18,r18,65535
+ 800c538:	b4a4b03a 	or	r18,r22,r18
+ 800c53c:	9500052e 	bgeu	r18,r20,800c554 <__udivdi3+0x12c>
+ 800c540:	8ca5883a 	add	r18,r17,r18
+ 800c544:	10ffffc4 	addi	r3,r2,-1
+ 800c548:	94400136 	bltu	r18,r17,800c550 <__udivdi3+0x128>
+ 800c54c:	95011436 	bltu	r18,r20,800c9a0 <__udivdi3+0x578>
+ 800c550:	1805883a 	mov	r2,r3
+ 800c554:	800c943a 	slli	r6,r16,16
+ 800c558:	0007883a 	mov	r3,zero
+ 800c55c:	3084b03a 	or	r2,r6,r2
+ 800c560:	00005506 	br	800c6b8 <__udivdi3+0x290>
+ 800c564:	3000041e 	bne	r6,zero,800c578 <__udivdi3+0x150>
+ 800c568:	000b883a 	mov	r5,zero
+ 800c56c:	01000044 	movi	r4,1
+ 800c570:	800cff80 	call	800cff8 <__udivsi3>
+ 800c574:	1023883a 	mov	r17,r2
+ 800c578:	00bfffd4 	movui	r2,65535
+ 800c57c:	14405f2e 	bgeu	r2,r17,800c6fc <__udivdi3+0x2d4>
+ 800c580:	00804034 	movhi	r2,256
+ 800c584:	8880f436 	bltu	r17,r2,800c958 <__udivdi3+0x530>
+ 800c588:	8806d63a 	srli	r3,r17,24
+ 800c58c:	04c00604 	movi	r19,24
+ 800c590:	00820134 	movhi	r2,2052
+ 800c594:	1885883a 	add	r2,r3,r2
+ 800c598:	109d8903 	ldbu	r2,30244(r2)
+ 800c59c:	14e7883a 	add	r19,r2,r19
+ 800c5a0:	00800804 	movi	r2,32
+ 800c5a4:	14c5c83a 	sub	r2,r2,r19
+ 800c5a8:	10005e1e 	bne	r2,zero,800c724 <__udivdi3+0x2fc>
+ 800c5ac:	8828d43a 	srli	r20,r17,16
+ 800c5b0:	8461c83a 	sub	r16,r16,r17
+ 800c5b4:	8d7fffcc 	andi	r21,r17,65535
+ 800c5b8:	00c00044 	movi	r3,1
+ 800c5bc:	8009883a 	mov	r4,r16
+ 800c5c0:	a00b883a 	mov	r5,r20
+ 800c5c4:	d8c00015 	stw	r3,0(sp)
+ 800c5c8:	800d05c0 	call	800d05c <__umodsi3>
+ 800c5cc:	8009883a 	mov	r4,r16
+ 800c5d0:	a00b883a 	mov	r5,r20
+ 800c5d4:	1027883a 	mov	r19,r2
+ 800c5d8:	800cff80 	call	800cff8 <__udivsi3>
+ 800c5dc:	1021883a 	mov	r16,r2
+ 800c5e0:	9826943a 	slli	r19,r19,16
+ 800c5e4:	9004d43a 	srli	r2,r18,16
+ 800c5e8:	8549383a 	mul	r4,r16,r21
+ 800c5ec:	d8c00017 	ldw	r3,0(sp)
+ 800c5f0:	9884b03a 	or	r2,r19,r2
+ 800c5f4:	1100052e 	bgeu	r2,r4,800c60c <__udivdi3+0x1e4>
+ 800c5f8:	1445883a 	add	r2,r2,r17
+ 800c5fc:	817fffc4 	addi	r5,r16,-1
+ 800c600:	14400136 	bltu	r2,r17,800c608 <__udivdi3+0x1e0>
+ 800c604:	1100eb36 	bltu	r2,r4,800c9b4 <__udivdi3+0x58c>
+ 800c608:	2821883a 	mov	r16,r5
+ 800c60c:	1127c83a 	sub	r19,r2,r4
+ 800c610:	a00b883a 	mov	r5,r20
+ 800c614:	9809883a 	mov	r4,r19
+ 800c618:	d8c00015 	stw	r3,0(sp)
+ 800c61c:	800d05c0 	call	800d05c <__umodsi3>
+ 800c620:	102d883a 	mov	r22,r2
+ 800c624:	a00b883a 	mov	r5,r20
+ 800c628:	9809883a 	mov	r4,r19
+ 800c62c:	800cff80 	call	800cff8 <__udivsi3>
+ 800c630:	b02c943a 	slli	r22,r22,16
+ 800c634:	156b383a 	mul	r21,r2,r21
+ 800c638:	94bfffcc 	andi	r18,r18,65535
+ 800c63c:	b4a4b03a 	or	r18,r22,r18
+ 800c640:	d8c00017 	ldw	r3,0(sp)
+ 800c644:	9540052e 	bgeu	r18,r21,800c65c <__udivdi3+0x234>
+ 800c648:	8ca5883a 	add	r18,r17,r18
+ 800c64c:	113fffc4 	addi	r4,r2,-1
+ 800c650:	94400136 	bltu	r18,r17,800c658 <__udivdi3+0x230>
+ 800c654:	9540d036 	bltu	r18,r21,800c998 <__udivdi3+0x570>
+ 800c658:	2005883a 	mov	r2,r4
+ 800c65c:	800c943a 	slli	r6,r16,16
+ 800c660:	3084b03a 	or	r2,r6,r2
+ 800c664:	00001406 	br	800c6b8 <__udivdi3+0x290>
+ 800c668:	29c01136 	bltu	r5,r7,800c6b0 <__udivdi3+0x288>
+ 800c66c:	00bfffd4 	movui	r2,65535
+ 800c670:	11c01d2e 	bgeu	r2,r7,800c6e8 <__udivdi3+0x2c0>
+ 800c674:	00804034 	movhi	r2,256
+ 800c678:	3880ac36 	bltu	r7,r2,800c92c <__udivdi3+0x504>
+ 800c67c:	3806d63a 	srli	r3,r7,24
+ 800c680:	01000604 	movi	r4,24
+ 800c684:	00820134 	movhi	r2,2052
+ 800c688:	1885883a 	add	r2,r3,r2
+ 800c68c:	10dd8903 	ldbu	r3,30244(r2)
+ 800c690:	05800804 	movi	r22,32
+ 800c694:	1907883a 	add	r3,r3,r4
+ 800c698:	b0edc83a 	sub	r22,r22,r3
+ 800c69c:	b000531e 	bne	r22,zero,800c7ec <__udivdi3+0x3c4>
+ 800c6a0:	3c00a536 	bltu	r7,r16,800c938 <__udivdi3+0x510>
+ 800c6a4:	a985403a 	cmpgeu	r2,r21,r6
+ 800c6a8:	0007883a 	mov	r3,zero
+ 800c6ac:	00000206 	br	800c6b8 <__udivdi3+0x290>
+ 800c6b0:	0007883a 	mov	r3,zero
+ 800c6b4:	0005883a 	mov	r2,zero
+ 800c6b8:	dfc00a17 	ldw	ra,40(sp)
+ 800c6bc:	df000917 	ldw	fp,36(sp)
+ 800c6c0:	ddc00817 	ldw	r23,32(sp)
+ 800c6c4:	dd800717 	ldw	r22,28(sp)
+ 800c6c8:	dd400617 	ldw	r21,24(sp)
+ 800c6cc:	dd000517 	ldw	r20,20(sp)
+ 800c6d0:	dcc00417 	ldw	r19,16(sp)
+ 800c6d4:	dc800317 	ldw	r18,12(sp)
+ 800c6d8:	dc400217 	ldw	r17,8(sp)
+ 800c6dc:	dc000117 	ldw	r16,4(sp)
+ 800c6e0:	dec00b04 	addi	sp,sp,44
+ 800c6e4:	f800283a 	ret
+ 800c6e8:	38804030 	cmpltui	r2,r7,256
+ 800c6ec:	1000951e 	bne	r2,zero,800c944 <__udivdi3+0x51c>
+ 800c6f0:	3806d23a 	srli	r3,r7,8
+ 800c6f4:	01000204 	movi	r4,8
+ 800c6f8:	003fe206 	br	800c684 <__udivdi3+0x25c>
+ 800c6fc:	88804030 	cmpltui	r2,r17,256
+ 800c700:	10009b1e 	bne	r2,zero,800c970 <__udivdi3+0x548>
+ 800c704:	8806d23a 	srli	r3,r17,8
+ 800c708:	04c00204 	movi	r19,8
+ 800c70c:	003fa006 	br	800c590 <__udivdi3+0x168>
+ 800c710:	30804030 	cmpltui	r2,r6,256
+ 800c714:	10008e1e 	bne	r2,zero,800c950 <__udivdi3+0x528>
+ 800c718:	3006d23a 	srli	r3,r6,8
+ 800c71c:	04c00204 	movi	r19,8
+ 800c720:	003f5a06 	br	800c48c <__udivdi3+0x64>
+ 800c724:	88a2983a 	sll	r17,r17,r2
+ 800c728:	84ecd83a 	srl	r22,r16,r19
+ 800c72c:	80a0983a 	sll	r16,r16,r2
+ 800c730:	8828d43a 	srli	r20,r17,16
+ 800c734:	b009883a 	mov	r4,r22
+ 800c738:	ace6d83a 	srl	r19,r21,r19
+ 800c73c:	a00b883a 	mov	r5,r20
+ 800c740:	a8a4983a 	sll	r18,r21,r2
+ 800c744:	800d05c0 	call	800d05c <__umodsi3>
+ 800c748:	b009883a 	mov	r4,r22
+ 800c74c:	a00b883a 	mov	r5,r20
+ 800c750:	9c26b03a 	or	r19,r19,r16
+ 800c754:	1021883a 	mov	r16,r2
+ 800c758:	800cff80 	call	800cff8 <__udivsi3>
+ 800c75c:	102f883a 	mov	r23,r2
+ 800c760:	8d7fffcc 	andi	r21,r17,65535
+ 800c764:	8020943a 	slli	r16,r16,16
+ 800c768:	9804d43a 	srli	r2,r19,16
+ 800c76c:	aded383a 	mul	r22,r21,r23
+ 800c770:	8084b03a 	or	r2,r16,r2
+ 800c774:	1580062e 	bgeu	r2,r22,800c790 <__udivdi3+0x368>
+ 800c778:	1445883a 	add	r2,r2,r17
+ 800c77c:	b8ffffc4 	addi	r3,r23,-1
+ 800c780:	14408336 	bltu	r2,r17,800c990 <__udivdi3+0x568>
+ 800c784:	1580822e 	bgeu	r2,r22,800c990 <__udivdi3+0x568>
+ 800c788:	bdffff84 	addi	r23,r23,-2
+ 800c78c:	1445883a 	add	r2,r2,r17
+ 800c790:	15adc83a 	sub	r22,r2,r22
+ 800c794:	a00b883a 	mov	r5,r20
+ 800c798:	b009883a 	mov	r4,r22
+ 800c79c:	800d05c0 	call	800d05c <__umodsi3>
+ 800c7a0:	1021883a 	mov	r16,r2
+ 800c7a4:	b009883a 	mov	r4,r22
+ 800c7a8:	a00b883a 	mov	r5,r20
+ 800c7ac:	800cff80 	call	800cff8 <__udivsi3>
+ 800c7b0:	8020943a 	slli	r16,r16,16
+ 800c7b4:	a889383a 	mul	r4,r21,r2
+ 800c7b8:	9cffffcc 	andi	r19,r19,65535
+ 800c7bc:	84e0b03a 	or	r16,r16,r19
+ 800c7c0:	8100062e 	bgeu	r16,r4,800c7dc <__udivdi3+0x3b4>
+ 800c7c4:	8461883a 	add	r16,r16,r17
+ 800c7c8:	10ffffc4 	addi	r3,r2,-1
+ 800c7cc:	84406c36 	bltu	r16,r17,800c980 <__udivdi3+0x558>
+ 800c7d0:	81006b2e 	bgeu	r16,r4,800c980 <__udivdi3+0x558>
+ 800c7d4:	10bfff84 	addi	r2,r2,-2
+ 800c7d8:	8461883a 	add	r16,r16,r17
+ 800c7dc:	b806943a 	slli	r3,r23,16
+ 800c7e0:	8121c83a 	sub	r16,r16,r4
+ 800c7e4:	1886b03a 	or	r3,r3,r2
+ 800c7e8:	003f7406 	br	800c5bc <__udivdi3+0x194>
+ 800c7ec:	30f8d83a 	srl	fp,r6,r3
+ 800c7f0:	3d8e983a 	sll	r7,r7,r22
+ 800c7f4:	80eed83a 	srl	r23,r16,r3
+ 800c7f8:	a8c6d83a 	srl	r3,r21,r3
+ 800c7fc:	e1f8b03a 	or	fp,fp,r7
+ 800c800:	e024d43a 	srli	r18,fp,16
+ 800c804:	85a0983a 	sll	r16,r16,r22
+ 800c808:	b809883a 	mov	r4,r23
+ 800c80c:	900b883a 	mov	r5,r18
+ 800c810:	1c22b03a 	or	r17,r3,r16
+ 800c814:	35a8983a 	sll	r20,r6,r22
+ 800c818:	800d05c0 	call	800d05c <__umodsi3>
+ 800c81c:	b809883a 	mov	r4,r23
+ 800c820:	900b883a 	mov	r5,r18
+ 800c824:	1027883a 	mov	r19,r2
+ 800c828:	800cff80 	call	800cff8 <__udivsi3>
+ 800c82c:	1021883a 	mov	r16,r2
+ 800c830:	e0ffffcc 	andi	r3,fp,65535
+ 800c834:	9826943a 	slli	r19,r19,16
+ 800c838:	8804d43a 	srli	r2,r17,16
+ 800c83c:	1c09383a 	mul	r4,r3,r16
+ 800c840:	9884b03a 	or	r2,r19,r2
+ 800c844:	1100062e 	bgeu	r2,r4,800c860 <__udivdi3+0x438>
+ 800c848:	1705883a 	add	r2,r2,fp
+ 800c84c:	817fffc4 	addi	r5,r16,-1
+ 800c850:	17004d36 	bltu	r2,fp,800c988 <__udivdi3+0x560>
+ 800c854:	11004c2e 	bgeu	r2,r4,800c988 <__udivdi3+0x560>
+ 800c858:	843fff84 	addi	r16,r16,-2
+ 800c85c:	1705883a 	add	r2,r2,fp
+ 800c860:	1127c83a 	sub	r19,r2,r4
+ 800c864:	900b883a 	mov	r5,r18
+ 800c868:	9809883a 	mov	r4,r19
+ 800c86c:	d8c00015 	stw	r3,0(sp)
+ 800c870:	800d05c0 	call	800d05c <__umodsi3>
+ 800c874:	9809883a 	mov	r4,r19
+ 800c878:	900b883a 	mov	r5,r18
+ 800c87c:	102f883a 	mov	r23,r2
+ 800c880:	800cff80 	call	800cff8 <__udivsi3>
+ 800c884:	d8c00017 	ldw	r3,0(sp)
+ 800c888:	b82e943a 	slli	r23,r23,16
+ 800c88c:	8c7fffcc 	andi	r17,r17,65535
+ 800c890:	1889383a 	mul	r4,r3,r2
+ 800c894:	bc62b03a 	or	r17,r23,r17
+ 800c898:	8900062e 	bgeu	r17,r4,800c8b4 <__udivdi3+0x48c>
+ 800c89c:	8f23883a 	add	r17,r17,fp
+ 800c8a0:	10ffffc4 	addi	r3,r2,-1
+ 800c8a4:	8f003436 	bltu	r17,fp,800c978 <__udivdi3+0x550>
+ 800c8a8:	8900332e 	bgeu	r17,r4,800c978 <__udivdi3+0x550>
+ 800c8ac:	10bfff84 	addi	r2,r2,-2
+ 800c8b0:	8f23883a 	add	r17,r17,fp
+ 800c8b4:	8020943a 	slli	r16,r16,16
+ 800c8b8:	a17fffcc 	andi	r5,r20,65535
+ 800c8bc:	a00cd43a 	srli	r6,r20,16
+ 800c8c0:	8084b03a 	or	r2,r16,r2
+ 800c8c4:	10ffffcc 	andi	r3,r2,65535
+ 800c8c8:	1028d43a 	srli	r20,r2,16
+ 800c8cc:	1951383a 	mul	r8,r3,r5
+ 800c8d0:	1987383a 	mul	r3,r3,r6
+ 800c8d4:	a14b383a 	mul	r5,r20,r5
+ 800c8d8:	400ed43a 	srli	r7,r8,16
+ 800c8dc:	8923c83a 	sub	r17,r17,r4
+ 800c8e0:	1947883a 	add	r3,r3,r5
+ 800c8e4:	38c7883a 	add	r3,r7,r3
+ 800c8e8:	a1a9383a 	mul	r20,r20,r6
+ 800c8ec:	1940022e 	bgeu	r3,r5,800c8f8 <__udivdi3+0x4d0>
+ 800c8f0:	01000074 	movhi	r4,1
+ 800c8f4:	a129883a 	add	r20,r20,r4
+ 800c8f8:	180cd43a 	srli	r6,r3,16
+ 800c8fc:	3529883a 	add	r20,r6,r20
+ 800c900:	8d000836 	bltu	r17,r20,800c924 <__udivdi3+0x4fc>
+ 800c904:	8d000226 	beq	r17,r20,800c910 <__udivdi3+0x4e8>
+ 800c908:	0007883a 	mov	r3,zero
+ 800c90c:	003f6a06 	br	800c6b8 <__udivdi3+0x290>
+ 800c910:	1806943a 	slli	r3,r3,16
+ 800c914:	ad8c983a 	sll	r6,r21,r22
+ 800c918:	423fffcc 	andi	r8,r8,65535
+ 800c91c:	1a07883a 	add	r3,r3,r8
+ 800c920:	30fff92e 	bgeu	r6,r3,800c908 <__udivdi3+0x4e0>
+ 800c924:	10bfffc4 	addi	r2,r2,-1
+ 800c928:	003ff706 	br	800c908 <__udivdi3+0x4e0>
+ 800c92c:	3806d43a 	srli	r3,r7,16
+ 800c930:	01000404 	movi	r4,16
+ 800c934:	003f5306 	br	800c684 <__udivdi3+0x25c>
+ 800c938:	0007883a 	mov	r3,zero
+ 800c93c:	00800044 	movi	r2,1
+ 800c940:	003f5d06 	br	800c6b8 <__udivdi3+0x290>
+ 800c944:	3807883a 	mov	r3,r7
+ 800c948:	0009883a 	mov	r4,zero
+ 800c94c:	003f4d06 	br	800c684 <__udivdi3+0x25c>
+ 800c950:	3007883a 	mov	r3,r6
+ 800c954:	003ecd06 	br	800c48c <__udivdi3+0x64>
+ 800c958:	8806d43a 	srli	r3,r17,16
+ 800c95c:	04c00404 	movi	r19,16
+ 800c960:	003f0b06 	br	800c590 <__udivdi3+0x168>
+ 800c964:	3006d43a 	srli	r3,r6,16
+ 800c968:	04c00404 	movi	r19,16
+ 800c96c:	003ec706 	br	800c48c <__udivdi3+0x64>
+ 800c970:	8807883a 	mov	r3,r17
+ 800c974:	003f0606 	br	800c590 <__udivdi3+0x168>
+ 800c978:	1805883a 	mov	r2,r3
+ 800c97c:	003fcd06 	br	800c8b4 <__udivdi3+0x48c>
+ 800c980:	1805883a 	mov	r2,r3
+ 800c984:	003f9506 	br	800c7dc <__udivdi3+0x3b4>
+ 800c988:	2821883a 	mov	r16,r5
+ 800c98c:	003fb406 	br	800c860 <__udivdi3+0x438>
+ 800c990:	182f883a 	mov	r23,r3
+ 800c994:	003f7e06 	br	800c790 <__udivdi3+0x368>
+ 800c998:	10bfff84 	addi	r2,r2,-2
+ 800c99c:	003f2f06 	br	800c65c <__udivdi3+0x234>
+ 800c9a0:	10bfff84 	addi	r2,r2,-2
+ 800c9a4:	003eeb06 	br	800c554 <__udivdi3+0x12c>
+ 800c9a8:	843fff84 	addi	r16,r16,-2
+ 800c9ac:	1445883a 	add	r2,r2,r17
+ 800c9b0:	003ed606 	br	800c50c <__udivdi3+0xe4>
+ 800c9b4:	843fff84 	addi	r16,r16,-2
+ 800c9b8:	1445883a 	add	r2,r2,r17
+ 800c9bc:	003f1306 	br	800c60c <__udivdi3+0x1e4>
+
+0800c9c0 <__umoddi3>:
+ 800c9c0:	defff404 	addi	sp,sp,-48
+ 800c9c4:	dc400315 	stw	r17,12(sp)
+ 800c9c8:	dc000215 	stw	r16,8(sp)
+ 800c9cc:	dfc00b15 	stw	ra,44(sp)
+ 800c9d0:	df000a15 	stw	fp,40(sp)
+ 800c9d4:	ddc00915 	stw	r23,36(sp)
+ 800c9d8:	dd800815 	stw	r22,32(sp)
+ 800c9dc:	dd400715 	stw	r21,28(sp)
+ 800c9e0:	dd000615 	stw	r20,24(sp)
+ 800c9e4:	dcc00515 	stw	r19,20(sp)
+ 800c9e8:	dc800415 	stw	r18,16(sp)
+ 800c9ec:	2823883a 	mov	r17,r5
+ 800c9f0:	2021883a 	mov	r16,r4
+ 800c9f4:	3800701e 	bne	r7,zero,800cbb8 <__umoddi3+0x1f8>
+ 800c9f8:	382b883a 	mov	r21,r7
+ 800c9fc:	3027883a 	mov	r19,r6
+ 800ca00:	2029883a 	mov	r20,r4
+ 800ca04:	2980392e 	bgeu	r5,r6,800caec <__umoddi3+0x12c>
+ 800ca08:	00bfffd4 	movui	r2,65535
+ 800ca0c:	282f883a 	mov	r23,r5
+ 800ca10:	11809736 	bltu	r2,r6,800cc70 <__umoddi3+0x2b0>
+ 800ca14:	30804030 	cmpltui	r2,r6,256
+ 800ca18:	1001231e 	bne	r2,zero,800cea8 <__umoddi3+0x4e8>
+ 800ca1c:	3006d23a 	srli	r3,r6,8
+ 800ca20:	05400204 	movi	r21,8
+ 800ca24:	00820134 	movhi	r2,2052
+ 800ca28:	1885883a 	add	r2,r3,r2
+ 800ca2c:	109d8903 	ldbu	r2,30244(r2)
+ 800ca30:	156b883a 	add	r21,r2,r21
+ 800ca34:	00800804 	movi	r2,32
+ 800ca38:	1565c83a 	sub	r18,r2,r21
+ 800ca3c:	90000526 	beq	r18,zero,800ca54 <__umoddi3+0x94>
+ 800ca40:	8ca2983a 	sll	r17,r17,r18
+ 800ca44:	856ad83a 	srl	r21,r16,r21
+ 800ca48:	34a6983a 	sll	r19,r6,r18
+ 800ca4c:	84a8983a 	sll	r20,r16,r18
+ 800ca50:	ac6eb03a 	or	r23,r21,r17
+ 800ca54:	982cd43a 	srli	r22,r19,16
+ 800ca58:	b809883a 	mov	r4,r23
+ 800ca5c:	9c3fffcc 	andi	r16,r19,65535
+ 800ca60:	b00b883a 	mov	r5,r22
+ 800ca64:	800d05c0 	call	800d05c <__umodsi3>
+ 800ca68:	b00b883a 	mov	r5,r22
+ 800ca6c:	b809883a 	mov	r4,r23
+ 800ca70:	102b883a 	mov	r21,r2
+ 800ca74:	800cff80 	call	800cff8 <__udivsi3>
+ 800ca78:	a82a943a 	slli	r21,r21,16
+ 800ca7c:	a006d43a 	srli	r3,r20,16
+ 800ca80:	8085383a 	mul	r2,r16,r2
+ 800ca84:	a8c6b03a 	or	r3,r21,r3
+ 800ca88:	1880032e 	bgeu	r3,r2,800ca98 <__umoddi3+0xd8>
+ 800ca8c:	1cc7883a 	add	r3,r3,r19
+ 800ca90:	1cc00136 	bltu	r3,r19,800ca98 <__umoddi3+0xd8>
+ 800ca94:	18811836 	bltu	r3,r2,800cef8 <__umoddi3+0x538>
+ 800ca98:	18abc83a 	sub	r21,r3,r2
+ 800ca9c:	b00b883a 	mov	r5,r22
+ 800caa0:	a809883a 	mov	r4,r21
+ 800caa4:	800d05c0 	call	800d05c <__umodsi3>
+ 800caa8:	1023883a 	mov	r17,r2
+ 800caac:	b00b883a 	mov	r5,r22
+ 800cab0:	a809883a 	mov	r4,r21
+ 800cab4:	800cff80 	call	800cff8 <__udivsi3>
+ 800cab8:	8822943a 	slli	r17,r17,16
+ 800cabc:	8085383a 	mul	r2,r16,r2
+ 800cac0:	a0ffffcc 	andi	r3,r20,65535
+ 800cac4:	88c6b03a 	or	r3,r17,r3
+ 800cac8:	1880042e 	bgeu	r3,r2,800cadc <__umoddi3+0x11c>
+ 800cacc:	1cc7883a 	add	r3,r3,r19
+ 800cad0:	1cc00236 	bltu	r3,r19,800cadc <__umoddi3+0x11c>
+ 800cad4:	1880012e 	bgeu	r3,r2,800cadc <__umoddi3+0x11c>
+ 800cad8:	1cc7883a 	add	r3,r3,r19
+ 800cadc:	1885c83a 	sub	r2,r3,r2
+ 800cae0:	1484d83a 	srl	r2,r2,r18
+ 800cae4:	0007883a 	mov	r3,zero
+ 800cae8:	00003606 	br	800cbc4 <__umoddi3+0x204>
+ 800caec:	3000041e 	bne	r6,zero,800cb00 <__umoddi3+0x140>
+ 800caf0:	000b883a 	mov	r5,zero
+ 800caf4:	01000044 	movi	r4,1
+ 800caf8:	800cff80 	call	800cff8 <__udivsi3>
+ 800cafc:	1027883a 	mov	r19,r2
+ 800cb00:	00bfffd4 	movui	r2,65535
+ 800cb04:	14c0552e 	bgeu	r2,r19,800cc5c <__umoddi3+0x29c>
+ 800cb08:	00804034 	movhi	r2,256
+ 800cb0c:	9880ee36 	bltu	r19,r2,800cec8 <__umoddi3+0x508>
+ 800cb10:	9806d63a 	srli	r3,r19,24
+ 800cb14:	05400604 	movi	r21,24
+ 800cb18:	00820134 	movhi	r2,2052
+ 800cb1c:	1885883a 	add	r2,r3,r2
+ 800cb20:	109d8903 	ldbu	r2,30244(r2)
+ 800cb24:	156b883a 	add	r21,r2,r21
+ 800cb28:	00800804 	movi	r2,32
+ 800cb2c:	1565c83a 	sub	r18,r2,r21
+ 800cb30:	9000ab1e 	bne	r18,zero,800cde0 <__umoddi3+0x420>
+ 800cb34:	982cd43a 	srli	r22,r19,16
+ 800cb38:	8ce3c83a 	sub	r17,r17,r19
+ 800cb3c:	9d7fffcc 	andi	r21,r19,65535
+ 800cb40:	b00b883a 	mov	r5,r22
+ 800cb44:	8809883a 	mov	r4,r17
+ 800cb48:	800d05c0 	call	800d05c <__umodsi3>
+ 800cb4c:	b00b883a 	mov	r5,r22
+ 800cb50:	8809883a 	mov	r4,r17
+ 800cb54:	1021883a 	mov	r16,r2
+ 800cb58:	800cff80 	call	800cff8 <__udivsi3>
+ 800cb5c:	8020943a 	slli	r16,r16,16
+ 800cb60:	a006d43a 	srli	r3,r20,16
+ 800cb64:	1545383a 	mul	r2,r2,r21
+ 800cb68:	80c6b03a 	or	r3,r16,r3
+ 800cb6c:	1880042e 	bgeu	r3,r2,800cb80 <__umoddi3+0x1c0>
+ 800cb70:	1cc7883a 	add	r3,r3,r19
+ 800cb74:	1cc00236 	bltu	r3,r19,800cb80 <__umoddi3+0x1c0>
+ 800cb78:	1880012e 	bgeu	r3,r2,800cb80 <__umoddi3+0x1c0>
+ 800cb7c:	1cc7883a 	add	r3,r3,r19
+ 800cb80:	18a1c83a 	sub	r16,r3,r2
+ 800cb84:	b00b883a 	mov	r5,r22
+ 800cb88:	8009883a 	mov	r4,r16
+ 800cb8c:	800d05c0 	call	800d05c <__umodsi3>
+ 800cb90:	1023883a 	mov	r17,r2
+ 800cb94:	b00b883a 	mov	r5,r22
+ 800cb98:	8009883a 	mov	r4,r16
+ 800cb9c:	800cff80 	call	800cff8 <__udivsi3>
+ 800cba0:	8822943a 	slli	r17,r17,16
+ 800cba4:	1545383a 	mul	r2,r2,r21
+ 800cba8:	a53fffcc 	andi	r20,r20,65535
+ 800cbac:	8d06b03a 	or	r3,r17,r20
+ 800cbb0:	18bfca2e 	bgeu	r3,r2,800cadc <__umoddi3+0x11c>
+ 800cbb4:	003fc506 	br	800cacc <__umoddi3+0x10c>
+ 800cbb8:	2005883a 	mov	r2,r4
+ 800cbbc:	29c00d2e 	bgeu	r5,r7,800cbf4 <__umoddi3+0x234>
+ 800cbc0:	2807883a 	mov	r3,r5
+ 800cbc4:	dfc00b17 	ldw	ra,44(sp)
+ 800cbc8:	df000a17 	ldw	fp,40(sp)
+ 800cbcc:	ddc00917 	ldw	r23,36(sp)
+ 800cbd0:	dd800817 	ldw	r22,32(sp)
+ 800cbd4:	dd400717 	ldw	r21,28(sp)
+ 800cbd8:	dd000617 	ldw	r20,24(sp)
+ 800cbdc:	dcc00517 	ldw	r19,20(sp)
+ 800cbe0:	dc800417 	ldw	r18,16(sp)
+ 800cbe4:	dc400317 	ldw	r17,12(sp)
+ 800cbe8:	dc000217 	ldw	r16,8(sp)
+ 800cbec:	dec00c04 	addi	sp,sp,48
+ 800cbf0:	f800283a 	ret
+ 800cbf4:	013fffd4 	movui	r4,65535
+ 800cbf8:	2807883a 	mov	r3,r5
+ 800cbfc:	21c0122e 	bgeu	r4,r7,800cc48 <__umoddi3+0x288>
+ 800cc00:	01004034 	movhi	r4,256
+ 800cc04:	3900ad36 	bltu	r7,r4,800cebc <__umoddi3+0x4fc>
+ 800cc08:	3810d63a 	srli	r8,r7,24
+ 800cc0c:	01400604 	movi	r5,24
+ 800cc10:	01020134 	movhi	r4,2052
+ 800cc14:	4109883a 	add	r4,r8,r4
+ 800cc18:	251d8903 	ldbu	r20,30244(r4)
+ 800cc1c:	04c00804 	movi	r19,32
+ 800cc20:	a169883a 	add	r20,r20,r5
+ 800cc24:	9d27c83a 	sub	r19,r19,r20
+ 800cc28:	9800161e 	bne	r19,zero,800cc84 <__umoddi3+0x2c4>
+ 800cc2c:	3c400136 	bltu	r7,r17,800cc34 <__umoddi3+0x274>
+ 800cc30:	81bfe436 	bltu	r16,r6,800cbc4 <__umoddi3+0x204>
+ 800cc34:	8185c83a 	sub	r2,r16,r6
+ 800cc38:	89cfc83a 	sub	r7,r17,r7
+ 800cc3c:	8087803a 	cmpltu	r3,r16,r2
+ 800cc40:	38c7c83a 	sub	r3,r7,r3
+ 800cc44:	003fdf06 	br	800cbc4 <__umoddi3+0x204>
+ 800cc48:	39004030 	cmpltui	r4,r7,256
+ 800cc4c:	2000981e 	bne	r4,zero,800ceb0 <__umoddi3+0x4f0>
+ 800cc50:	3810d23a 	srli	r8,r7,8
+ 800cc54:	01400204 	movi	r5,8
+ 800cc58:	003fed06 	br	800cc10 <__umoddi3+0x250>
+ 800cc5c:	98804030 	cmpltui	r2,r19,256
+ 800cc60:	10009c1e 	bne	r2,zero,800ced4 <__umoddi3+0x514>
+ 800cc64:	9806d23a 	srli	r3,r19,8
+ 800cc68:	05400204 	movi	r21,8
+ 800cc6c:	003faa06 	br	800cb18 <__umoddi3+0x158>
+ 800cc70:	00804034 	movhi	r2,256
+ 800cc74:	30809936 	bltu	r6,r2,800cedc <__umoddi3+0x51c>
+ 800cc78:	3006d63a 	srli	r3,r6,24
+ 800cc7c:	05400604 	movi	r21,24
+ 800cc80:	003f6806 	br	800ca24 <__umoddi3+0x64>
+ 800cc84:	3504d83a 	srl	r2,r6,r20
+ 800cc88:	3cce983a 	sll	r7,r7,r19
+ 800cc8c:	8d38d83a 	srl	fp,r17,r20
+ 800cc90:	8ce2983a 	sll	r17,r17,r19
+ 800cc94:	11eeb03a 	or	r23,r2,r7
+ 800cc98:	b82cd43a 	srli	r22,r23,16
+ 800cc9c:	8504d83a 	srl	r2,r16,r20
+ 800cca0:	e009883a 	mov	r4,fp
+ 800cca4:	b00b883a 	mov	r5,r22
+ 800cca8:	34e4983a 	sll	r18,r6,r19
+ 800ccac:	1462b03a 	or	r17,r2,r17
+ 800ccb0:	800d05c0 	call	800d05c <__umodsi3>
+ 800ccb4:	e009883a 	mov	r4,fp
+ 800ccb8:	b00b883a 	mov	r5,r22
+ 800ccbc:	102b883a 	mov	r21,r2
+ 800ccc0:	800cff80 	call	800cff8 <__udivsi3>
+ 800ccc4:	100d883a 	mov	r6,r2
+ 800ccc8:	b8ffffcc 	andi	r3,r23,65535
+ 800cccc:	a82a943a 	slli	r21,r21,16
+ 800ccd0:	8804d43a 	srli	r2,r17,16
+ 800ccd4:	1989383a 	mul	r4,r3,r6
+ 800ccd8:	84e0983a 	sll	r16,r16,r19
+ 800ccdc:	a884b03a 	or	r2,r21,r2
+ 800cce0:	1100062e 	bgeu	r2,r4,800ccfc <__umoddi3+0x33c>
+ 800cce4:	15c5883a 	add	r2,r2,r23
+ 800cce8:	317fffc4 	addi	r5,r6,-1
+ 800ccec:	15c08036 	bltu	r2,r23,800cef0 <__umoddi3+0x530>
+ 800ccf0:	11007f2e 	bgeu	r2,r4,800cef0 <__umoddi3+0x530>
+ 800ccf4:	31bfff84 	addi	r6,r6,-2
+ 800ccf8:	15c5883a 	add	r2,r2,r23
+ 800ccfc:	112bc83a 	sub	r21,r2,r4
+ 800cd00:	b00b883a 	mov	r5,r22
+ 800cd04:	a809883a 	mov	r4,r21
+ 800cd08:	d9800115 	stw	r6,4(sp)
+ 800cd0c:	d8c00015 	stw	r3,0(sp)
+ 800cd10:	800d05c0 	call	800d05c <__umodsi3>
+ 800cd14:	b00b883a 	mov	r5,r22
+ 800cd18:	a809883a 	mov	r4,r21
+ 800cd1c:	1039883a 	mov	fp,r2
+ 800cd20:	800cff80 	call	800cff8 <__udivsi3>
+ 800cd24:	d8c00017 	ldw	r3,0(sp)
+ 800cd28:	e038943a 	slli	fp,fp,16
+ 800cd2c:	8c7fffcc 	andi	r17,r17,65535
+ 800cd30:	1887383a 	mul	r3,r3,r2
+ 800cd34:	e462b03a 	or	r17,fp,r17
+ 800cd38:	d9800117 	ldw	r6,4(sp)
+ 800cd3c:	88c0062e 	bgeu	r17,r3,800cd58 <__umoddi3+0x398>
+ 800cd40:	8de3883a 	add	r17,r17,r23
+ 800cd44:	113fffc4 	addi	r4,r2,-1
+ 800cd48:	8dc06736 	bltu	r17,r23,800cee8 <__umoddi3+0x528>
+ 800cd4c:	88c0662e 	bgeu	r17,r3,800cee8 <__umoddi3+0x528>
+ 800cd50:	10bfff84 	addi	r2,r2,-2
+ 800cd54:	8de3883a 	add	r17,r17,r23
+ 800cd58:	300a943a 	slli	r5,r6,16
+ 800cd5c:	9010d43a 	srli	r8,r18,16
+ 800cd60:	91bfffcc 	andi	r6,r18,65535
+ 800cd64:	2888b03a 	or	r4,r5,r2
+ 800cd68:	21ffffcc 	andi	r7,r4,65535
+ 800cd6c:	2008d43a 	srli	r4,r4,16
+ 800cd70:	300b883a 	mov	r5,r6
+ 800cd74:	398d383a 	mul	r6,r7,r6
+ 800cd78:	214b383a 	mul	r5,r4,r5
+ 800cd7c:	3a0f383a 	mul	r7,r7,r8
+ 800cd80:	3004d43a 	srli	r2,r6,16
+ 800cd84:	88c7c83a 	sub	r3,r17,r3
+ 800cd88:	394f883a 	add	r7,r7,r5
+ 800cd8c:	11c5883a 	add	r2,r2,r7
+ 800cd90:	2209383a 	mul	r4,r4,r8
+ 800cd94:	1140022e 	bgeu	r2,r5,800cda0 <__umoddi3+0x3e0>
+ 800cd98:	01400074 	movhi	r5,1
+ 800cd9c:	2149883a 	add	r4,r4,r5
+ 800cda0:	100ad43a 	srli	r5,r2,16
+ 800cda4:	1004943a 	slli	r2,r2,16
+ 800cda8:	31bfffcc 	andi	r6,r6,65535
+ 800cdac:	2909883a 	add	r4,r5,r4
+ 800cdb0:	1185883a 	add	r2,r2,r6
+ 800cdb4:	19003636 	bltu	r3,r4,800ce90 <__umoddi3+0x4d0>
+ 800cdb8:	19003426 	beq	r3,r4,800ce8c <__umoddi3+0x4cc>
+ 800cdbc:	8085c83a 	sub	r2,r16,r2
+ 800cdc0:	80a1803a 	cmpltu	r16,r16,r2
+ 800cdc4:	1907c83a 	sub	r3,r3,r4
+ 800cdc8:	1c07c83a 	sub	r3,r3,r16
+ 800cdcc:	1d20983a 	sll	r16,r3,r20
+ 800cdd0:	14c4d83a 	srl	r2,r2,r19
+ 800cdd4:	1cc6d83a 	srl	r3,r3,r19
+ 800cdd8:	8084b03a 	or	r2,r16,r2
+ 800cddc:	003f7906 	br	800cbc4 <__umoddi3+0x204>
+ 800cde0:	9ca6983a 	sll	r19,r19,r18
+ 800cde4:	8d68d83a 	srl	r20,r17,r21
+ 800cde8:	856ad83a 	srl	r21,r16,r21
+ 800cdec:	982cd43a 	srli	r22,r19,16
+ 800cdf0:	a009883a 	mov	r4,r20
+ 800cdf4:	8ca2983a 	sll	r17,r17,r18
+ 800cdf8:	b00b883a 	mov	r5,r22
+ 800cdfc:	800d05c0 	call	800d05c <__umodsi3>
+ 800ce00:	a009883a 	mov	r4,r20
+ 800ce04:	b00b883a 	mov	r5,r22
+ 800ce08:	ac6eb03a 	or	r23,r21,r17
+ 800ce0c:	1023883a 	mov	r17,r2
+ 800ce10:	800cff80 	call	800cff8 <__udivsi3>
+ 800ce14:	9d7fffcc 	andi	r21,r19,65535
+ 800ce18:	8822943a 	slli	r17,r17,16
+ 800ce1c:	b806d43a 	srli	r3,r23,16
+ 800ce20:	a885383a 	mul	r2,r21,r2
+ 800ce24:	84a8983a 	sll	r20,r16,r18
+ 800ce28:	88c6b03a 	or	r3,r17,r3
+ 800ce2c:	1880042e 	bgeu	r3,r2,800ce40 <__umoddi3+0x480>
+ 800ce30:	1cc7883a 	add	r3,r3,r19
+ 800ce34:	1cc00236 	bltu	r3,r19,800ce40 <__umoddi3+0x480>
+ 800ce38:	1880012e 	bgeu	r3,r2,800ce40 <__umoddi3+0x480>
+ 800ce3c:	1cc7883a 	add	r3,r3,r19
+ 800ce40:	18a3c83a 	sub	r17,r3,r2
+ 800ce44:	8809883a 	mov	r4,r17
+ 800ce48:	b00b883a 	mov	r5,r22
+ 800ce4c:	800d05c0 	call	800d05c <__umodsi3>
+ 800ce50:	1021883a 	mov	r16,r2
+ 800ce54:	8809883a 	mov	r4,r17
+ 800ce58:	b00b883a 	mov	r5,r22
+ 800ce5c:	800cff80 	call	800cff8 <__udivsi3>
+ 800ce60:	8022943a 	slli	r17,r16,16
+ 800ce64:	a885383a 	mul	r2,r21,r2
+ 800ce68:	bdffffcc 	andi	r23,r23,65535
+ 800ce6c:	8de2b03a 	or	r17,r17,r23
+ 800ce70:	8880042e 	bgeu	r17,r2,800ce84 <__umoddi3+0x4c4>
+ 800ce74:	8ce3883a 	add	r17,r17,r19
+ 800ce78:	8cc00236 	bltu	r17,r19,800ce84 <__umoddi3+0x4c4>
+ 800ce7c:	8880012e 	bgeu	r17,r2,800ce84 <__umoddi3+0x4c4>
+ 800ce80:	8ce3883a 	add	r17,r17,r19
+ 800ce84:	88a3c83a 	sub	r17,r17,r2
+ 800ce88:	003f2d06 	br	800cb40 <__umoddi3+0x180>
+ 800ce8c:	80bfcb2e 	bgeu	r16,r2,800cdbc <__umoddi3+0x3fc>
+ 800ce90:	14a5c83a 	sub	r18,r2,r18
+ 800ce94:	1485803a 	cmpltu	r2,r2,r18
+ 800ce98:	15c5883a 	add	r2,r2,r23
+ 800ce9c:	2089c83a 	sub	r4,r4,r2
+ 800cea0:	9005883a 	mov	r2,r18
+ 800cea4:	003fc506 	br	800cdbc <__umoddi3+0x3fc>
+ 800cea8:	3007883a 	mov	r3,r6
+ 800ceac:	003edd06 	br	800ca24 <__umoddi3+0x64>
+ 800ceb0:	3811883a 	mov	r8,r7
+ 800ceb4:	000b883a 	mov	r5,zero
+ 800ceb8:	003f5506 	br	800cc10 <__umoddi3+0x250>
+ 800cebc:	3810d43a 	srli	r8,r7,16
+ 800cec0:	01400404 	movi	r5,16
+ 800cec4:	003f5206 	br	800cc10 <__umoddi3+0x250>
+ 800cec8:	9806d43a 	srli	r3,r19,16
+ 800cecc:	05400404 	movi	r21,16
+ 800ced0:	003f1106 	br	800cb18 <__umoddi3+0x158>
+ 800ced4:	9807883a 	mov	r3,r19
+ 800ced8:	003f0f06 	br	800cb18 <__umoddi3+0x158>
+ 800cedc:	3006d43a 	srli	r3,r6,16
+ 800cee0:	05400404 	movi	r21,16
+ 800cee4:	003ecf06 	br	800ca24 <__umoddi3+0x64>
+ 800cee8:	2005883a 	mov	r2,r4
+ 800ceec:	003f9a06 	br	800cd58 <__umoddi3+0x398>
+ 800cef0:	280d883a 	mov	r6,r5
+ 800cef4:	003f8106 	br	800ccfc <__umoddi3+0x33c>
+ 800cef8:	1cc7883a 	add	r3,r3,r19
+ 800cefc:	003ee606 	br	800ca98 <__umoddi3+0xd8>
+
+0800cf00 <__divsi3>:
+ 800cf00:	20001a16 	blt	r4,zero,800cf6c <__divsi3+0x6c>
+ 800cf04:	000f883a 	mov	r7,zero
+ 800cf08:	2800020e 	bge	r5,zero,800cf14 <__divsi3+0x14>
+ 800cf0c:	014bc83a 	sub	r5,zero,r5
+ 800cf10:	39c0005c 	xori	r7,r7,1
+ 800cf14:	200d883a 	mov	r6,r4
+ 800cf18:	00c00044 	movi	r3,1
+ 800cf1c:	2900092e 	bgeu	r5,r4,800cf44 <__divsi3+0x44>
+ 800cf20:	00800804 	movi	r2,32
+ 800cf24:	00c00044 	movi	r3,1
+ 800cf28:	00000106 	br	800cf30 <__divsi3+0x30>
+ 800cf2c:	10001226 	beq	r2,zero,800cf78 <__divsi3+0x78>
+ 800cf30:	294b883a 	add	r5,r5,r5
+ 800cf34:	10bfffc4 	addi	r2,r2,-1
+ 800cf38:	18c7883a 	add	r3,r3,r3
+ 800cf3c:	293ffb36 	bltu	r5,r4,800cf2c <__divsi3+0x2c>
+ 800cf40:	18000d26 	beq	r3,zero,800cf78 <__divsi3+0x78>
+ 800cf44:	0005883a 	mov	r2,zero
+ 800cf48:	31400236 	bltu	r6,r5,800cf54 <__divsi3+0x54>
+ 800cf4c:	314dc83a 	sub	r6,r6,r5
+ 800cf50:	10c4b03a 	or	r2,r2,r3
+ 800cf54:	1806d07a 	srli	r3,r3,1
+ 800cf58:	280ad07a 	srli	r5,r5,1
+ 800cf5c:	183ffa1e 	bne	r3,zero,800cf48 <__divsi3+0x48>
+ 800cf60:	38000126 	beq	r7,zero,800cf68 <__divsi3+0x68>
+ 800cf64:	0085c83a 	sub	r2,zero,r2
+ 800cf68:	f800283a 	ret
+ 800cf6c:	0109c83a 	sub	r4,zero,r4
+ 800cf70:	01c00044 	movi	r7,1
+ 800cf74:	003fe406 	br	800cf08 <__divsi3+0x8>
+ 800cf78:	0005883a 	mov	r2,zero
+ 800cf7c:	003ff806 	br	800cf60 <__divsi3+0x60>
+
+0800cf80 <__modsi3>:
+ 800cf80:	20001a16 	blt	r4,zero,800cfec <__modsi3+0x6c>
+ 800cf84:	000f883a 	mov	r7,zero
+ 800cf88:	2005883a 	mov	r2,r4
+ 800cf8c:	2800010e 	bge	r5,zero,800cf94 <__modsi3+0x14>
+ 800cf90:	014bc83a 	sub	r5,zero,r5
+ 800cf94:	00c00044 	movi	r3,1
+ 800cf98:	2900092e 	bgeu	r5,r4,800cfc0 <__modsi3+0x40>
+ 800cf9c:	01800804 	movi	r6,32
+ 800cfa0:	00c00044 	movi	r3,1
+ 800cfa4:	00000106 	br	800cfac <__modsi3+0x2c>
+ 800cfa8:	30000d26 	beq	r6,zero,800cfe0 <__modsi3+0x60>
+ 800cfac:	294b883a 	add	r5,r5,r5
+ 800cfb0:	31bfffc4 	addi	r6,r6,-1
+ 800cfb4:	18c7883a 	add	r3,r3,r3
+ 800cfb8:	293ffb36 	bltu	r5,r4,800cfa8 <__modsi3+0x28>
+ 800cfbc:	18000826 	beq	r3,zero,800cfe0 <__modsi3+0x60>
+ 800cfc0:	1806d07a 	srli	r3,r3,1
+ 800cfc4:	11400136 	bltu	r2,r5,800cfcc <__modsi3+0x4c>
+ 800cfc8:	1145c83a 	sub	r2,r2,r5
+ 800cfcc:	280ad07a 	srli	r5,r5,1
+ 800cfd0:	183ffb1e 	bne	r3,zero,800cfc0 <__modsi3+0x40>
+ 800cfd4:	38000126 	beq	r7,zero,800cfdc <__modsi3+0x5c>
+ 800cfd8:	0085c83a 	sub	r2,zero,r2
+ 800cfdc:	f800283a 	ret
+ 800cfe0:	2005883a 	mov	r2,r4
+ 800cfe4:	383ffd26 	beq	r7,zero,800cfdc <__modsi3+0x5c>
+ 800cfe8:	003ffb06 	br	800cfd8 <__modsi3+0x58>
+ 800cfec:	0109c83a 	sub	r4,zero,r4
+ 800cff0:	01c00044 	movi	r7,1
+ 800cff4:	003fe406 	br	800cf88 <__modsi3+0x8>
+
+0800cff8 <__udivsi3>:
+ 800cff8:	200d883a 	mov	r6,r4
+ 800cffc:	2900152e 	bgeu	r5,r4,800d054 <__udivsi3+0x5c>
+ 800d000:	28001416 	blt	r5,zero,800d054 <__udivsi3+0x5c>
+ 800d004:	00800804 	movi	r2,32
+ 800d008:	00c00044 	movi	r3,1
+ 800d00c:	00000206 	br	800d018 <__udivsi3+0x20>
+ 800d010:	10000e26 	beq	r2,zero,800d04c <__udivsi3+0x54>
+ 800d014:	28000516 	blt	r5,zero,800d02c <__udivsi3+0x34>
+ 800d018:	294b883a 	add	r5,r5,r5
+ 800d01c:	10bfffc4 	addi	r2,r2,-1
+ 800d020:	18c7883a 	add	r3,r3,r3
+ 800d024:	293ffa36 	bltu	r5,r4,800d010 <__udivsi3+0x18>
+ 800d028:	18000826 	beq	r3,zero,800d04c <__udivsi3+0x54>
+ 800d02c:	0005883a 	mov	r2,zero
+ 800d030:	31400236 	bltu	r6,r5,800d03c <__udivsi3+0x44>
+ 800d034:	314dc83a 	sub	r6,r6,r5
+ 800d038:	10c4b03a 	or	r2,r2,r3
+ 800d03c:	1806d07a 	srli	r3,r3,1
+ 800d040:	280ad07a 	srli	r5,r5,1
+ 800d044:	183ffa1e 	bne	r3,zero,800d030 <__udivsi3+0x38>
+ 800d048:	f800283a 	ret
+ 800d04c:	0005883a 	mov	r2,zero
+ 800d050:	f800283a 	ret
+ 800d054:	00c00044 	movi	r3,1
+ 800d058:	003ff406 	br	800d02c <__udivsi3+0x34>
+
+0800d05c <__umodsi3>:
+ 800d05c:	2005883a 	mov	r2,r4
+ 800d060:	2900132e 	bgeu	r5,r4,800d0b0 <__umodsi3+0x54>
+ 800d064:	28001216 	blt	r5,zero,800d0b0 <__umodsi3+0x54>
+ 800d068:	01800804 	movi	r6,32
+ 800d06c:	00c00044 	movi	r3,1
+ 800d070:	00000206 	br	800d07c <__umodsi3+0x20>
+ 800d074:	30000c26 	beq	r6,zero,800d0a8 <__umodsi3+0x4c>
+ 800d078:	28000516 	blt	r5,zero,800d090 <__umodsi3+0x34>
+ 800d07c:	294b883a 	add	r5,r5,r5
+ 800d080:	31bfffc4 	addi	r6,r6,-1
+ 800d084:	18c7883a 	add	r3,r3,r3
+ 800d088:	293ffa36 	bltu	r5,r4,800d074 <__umodsi3+0x18>
+ 800d08c:	18000626 	beq	r3,zero,800d0a8 <__umodsi3+0x4c>
+ 800d090:	1806d07a 	srli	r3,r3,1
+ 800d094:	11400136 	bltu	r2,r5,800d09c <__umodsi3+0x40>
+ 800d098:	1145c83a 	sub	r2,r2,r5
+ 800d09c:	280ad07a 	srli	r5,r5,1
+ 800d0a0:	183ffb1e 	bne	r3,zero,800d090 <__umodsi3+0x34>
+ 800d0a4:	f800283a 	ret
+ 800d0a8:	2005883a 	mov	r2,r4
+ 800d0ac:	f800283a 	ret
+ 800d0b0:	00c00044 	movi	r3,1
+ 800d0b4:	003ff606 	br	800d090 <__umodsi3+0x34>
+
+0800d0b8 <__adddf3>:
+ 800d0b8:	02000434 	movhi	r8,16
+ 800d0bc:	defffb04 	addi	sp,sp,-20
+ 800d0c0:	423fffc4 	addi	r8,r8,-1
+ 800d0c4:	2a12703a 	and	r9,r5,r8
+ 800d0c8:	3a06703a 	and	r3,r7,r8
+ 800d0cc:	3804d53a 	srli	r2,r7,20
+ 800d0d0:	dc000015 	stw	r16,0(sp)
+ 800d0d4:	2820d53a 	srli	r16,r5,20
+ 800d0d8:	2016d77a 	srli	r11,r4,29
+ 800d0dc:	3014d77a 	srli	r10,r6,29
+ 800d0e0:	280ad7fa 	srli	r5,r5,31
+ 800d0e4:	481290fa 	slli	r9,r9,3
+ 800d0e8:	180690fa 	slli	r3,r3,3
+ 800d0ec:	380ed7fa 	srli	r7,r7,31
+ 800d0f0:	dc400115 	stw	r17,4(sp)
+ 800d0f4:	8401ffcc 	andi	r16,r16,2047
+ 800d0f8:	1081ffcc 	andi	r2,r2,2047
+ 800d0fc:	dfc00415 	stw	ra,16(sp)
+ 800d100:	dcc00315 	stw	r19,12(sp)
+ 800d104:	dc800215 	stw	r18,8(sp)
+ 800d108:	5a52b03a 	or	r9,r11,r9
+ 800d10c:	50c6b03a 	or	r3,r10,r3
+ 800d110:	2823883a 	mov	r17,r5
+ 800d114:	201890fa 	slli	r12,r4,3
+ 800d118:	301690fa 	slli	r11,r6,3
+ 800d11c:	8095c83a 	sub	r10,r16,r2
+ 800d120:	29c06a26 	beq	r5,r7,800d2cc <__adddf3+0x214>
+ 800d124:	0280590e 	bge	zero,r10,800d28c <__adddf3+0x1d4>
+ 800d128:	10007c26 	beq	r2,zero,800d31c <__adddf3+0x264>
+ 800d12c:	8081ffd8 	cmpnei	r2,r16,2047
+ 800d130:	10010726 	beq	r2,zero,800d550 <__adddf3+0x498>
+ 800d134:	18c02034 	orhi	r3,r3,128
+ 800d138:	50800e48 	cmpgei	r2,r10,57
+ 800d13c:	1000ed1e 	bne	r2,zero,800d4f4 <__adddf3+0x43c>
+ 800d140:	50800808 	cmpgei	r2,r10,32
+ 800d144:	1001541e 	bne	r2,zero,800d698 <__adddf3+0x5e0>
+ 800d148:	01000804 	movi	r4,32
+ 800d14c:	2289c83a 	sub	r4,r4,r10
+ 800d150:	1926983a 	sll	r19,r3,r4
+ 800d154:	5a84d83a 	srl	r2,r11,r10
+ 800d158:	5908983a 	sll	r4,r11,r4
+ 800d15c:	1a86d83a 	srl	r3,r3,r10
+ 800d160:	98a6b03a 	or	r19,r19,r2
+ 800d164:	2016c03a 	cmpne	r11,r4,zero
+ 800d168:	9ae6b03a 	or	r19,r19,r11
+ 800d16c:	48d3c83a 	sub	r9,r9,r3
+ 800d170:	64e7c83a 	sub	r19,r12,r19
+ 800d174:	64c9803a 	cmpltu	r4,r12,r19
+ 800d178:	4909c83a 	sub	r4,r9,r4
+ 800d17c:	2080202c 	andhi	r2,r4,128
+ 800d180:	10008726 	beq	r2,zero,800d3a0 <__adddf3+0x2e8>
+ 800d184:	02402034 	movhi	r9,128
+ 800d188:	4a7fffc4 	addi	r9,r9,-1
+ 800d18c:	2264703a 	and	r18,r4,r9
+ 800d190:	9000cf26 	beq	r18,zero,800d4d0 <__adddf3+0x418>
+ 800d194:	9009883a 	mov	r4,r18
+ 800d198:	800f7900 	call	800f790 <__clzsi2>
+ 800d19c:	10fffe04 	addi	r3,r2,-8
+ 800d1a0:	01000804 	movi	r4,32
+ 800d1a4:	20c9c83a 	sub	r4,r4,r3
+ 800d1a8:	990ad83a 	srl	r5,r19,r4
+ 800d1ac:	90c8983a 	sll	r4,r18,r3
+ 800d1b0:	98e6983a 	sll	r19,r19,r3
+ 800d1b4:	2908b03a 	or	r4,r5,r4
+ 800d1b8:	1c00be16 	blt	r3,r16,800d4b4 <__adddf3+0x3fc>
+ 800d1bc:	1c21c83a 	sub	r16,r3,r16
+ 800d1c0:	81400044 	addi	r5,r16,1
+ 800d1c4:	28800808 	cmpgei	r2,r5,32
+ 800d1c8:	10011b1e 	bne	r2,zero,800d638 <__adddf3+0x580>
+ 800d1cc:	00800804 	movi	r2,32
+ 800d1d0:	1145c83a 	sub	r2,r2,r5
+ 800d1d4:	9946d83a 	srl	r3,r19,r5
+ 800d1d8:	98a6983a 	sll	r19,r19,r2
+ 800d1dc:	2084983a 	sll	r2,r4,r2
+ 800d1e0:	2148d83a 	srl	r4,r4,r5
+ 800d1e4:	9826c03a 	cmpne	r19,r19,zero
+ 800d1e8:	10c4b03a 	or	r2,r2,r3
+ 800d1ec:	14e6b03a 	or	r19,r2,r19
+ 800d1f0:	0021883a 	mov	r16,zero
+ 800d1f4:	988001cc 	andi	r2,r19,7
+ 800d1f8:	10000726 	beq	r2,zero,800d218 <__adddf3+0x160>
+ 800d1fc:	988003cc 	andi	r2,r19,15
+ 800d200:	10800120 	cmpeqi	r2,r2,4
+ 800d204:	1000041e 	bne	r2,zero,800d218 <__adddf3+0x160>
+ 800d208:	99400104 	addi	r5,r19,4
+ 800d20c:	2ce7803a 	cmpltu	r19,r5,r19
+ 800d210:	24c9883a 	add	r4,r4,r19
+ 800d214:	2827883a 	mov	r19,r5
+ 800d218:	2080202c 	andhi	r2,r4,128
+ 800d21c:	10006226 	beq	r2,zero,800d3a8 <__adddf3+0x2f0>
+ 800d220:	84000044 	addi	r16,r16,1
+ 800d224:	8081ffe0 	cmpeqi	r2,r16,2047
+ 800d228:	8401ffcc 	andi	r16,r16,2047
+ 800d22c:	1000731e 	bne	r2,zero,800d3fc <__adddf3+0x344>
+ 800d230:	017fe034 	movhi	r5,65408
+ 800d234:	297fffc4 	addi	r5,r5,-1
+ 800d238:	214a703a 	and	r5,r4,r5
+ 800d23c:	2804977a 	slli	r2,r5,29
+ 800d240:	280a927a 	slli	r5,r5,9
+ 800d244:	9826d0fa 	srli	r19,r19,3
+ 800d248:	2808d33a 	srli	r4,r5,12
+ 800d24c:	14c4b03a 	or	r2,r2,r19
+ 800d250:	8020953a 	slli	r16,r16,20
+ 800d254:	00c00434 	movhi	r3,16
+ 800d258:	8c403fcc 	andi	r17,r17,255
+ 800d25c:	882297fa 	slli	r17,r17,31
+ 800d260:	18ffffc4 	addi	r3,r3,-1
+ 800d264:	20c6703a 	and	r3,r4,r3
+ 800d268:	1c06b03a 	or	r3,r3,r16
+ 800d26c:	1c46b03a 	or	r3,r3,r17
+ 800d270:	dfc00417 	ldw	ra,16(sp)
+ 800d274:	dcc00317 	ldw	r19,12(sp)
+ 800d278:	dc800217 	ldw	r18,8(sp)
+ 800d27c:	dc400117 	ldw	r17,4(sp)
+ 800d280:	dc000017 	ldw	r16,0(sp)
+ 800d284:	dec00504 	addi	sp,sp,20
+ 800d288:	f800283a 	ret
+ 800d28c:	50002b1e 	bne	r10,zero,800d33c <__adddf3+0x284>
+ 800d290:	80800044 	addi	r2,r16,1
+ 800d294:	1081ff8c 	andi	r2,r2,2046
+ 800d298:	1000a11e 	bne	r2,zero,800d520 <__adddf3+0x468>
+ 800d29c:	4b0ab03a 	or	r5,r9,r12
+ 800d2a0:	1ac4b03a 	or	r2,r3,r11
+ 800d2a4:	80015c1e 	bne	r16,zero,800d818 <__adddf3+0x760>
+ 800d2a8:	28012826 	beq	r5,zero,800d74c <__adddf3+0x694>
+ 800d2ac:	1001671e 	bne	r2,zero,800d84c <__adddf3+0x794>
+ 800d2b0:	4826977a 	slli	r19,r9,29
+ 800d2b4:	00c80034 	movhi	r3,8192
+ 800d2b8:	18ffffc4 	addi	r3,r3,-1
+ 800d2bc:	20c4703a 	and	r2,r4,r3
+ 800d2c0:	9884b03a 	or	r2,r19,r2
+ 800d2c4:	4812d0fa 	srli	r9,r9,3
+ 800d2c8:	00003d06 	br	800d3c0 <__adddf3+0x308>
+ 800d2cc:	02804f0e 	bge	zero,r10,800d40c <__adddf3+0x354>
+ 800d2d0:	10002426 	beq	r2,zero,800d364 <__adddf3+0x2ac>
+ 800d2d4:	8081ffd8 	cmpnei	r2,r16,2047
+ 800d2d8:	10009d26 	beq	r2,zero,800d550 <__adddf3+0x498>
+ 800d2dc:	18c02034 	orhi	r3,r3,128
+ 800d2e0:	50800e48 	cmpgei	r2,r10,57
+ 800d2e4:	10003b1e 	bne	r2,zero,800d3d4 <__adddf3+0x31c>
+ 800d2e8:	50800808 	cmpgei	r2,r10,32
+ 800d2ec:	10010326 	beq	r2,zero,800d6fc <__adddf3+0x644>
+ 800d2f0:	54fff804 	addi	r19,r10,-32
+ 800d2f4:	51000820 	cmpeqi	r4,r10,32
+ 800d2f8:	1cc4d83a 	srl	r2,r3,r19
+ 800d2fc:	2000041e 	bne	r4,zero,800d310 <__adddf3+0x258>
+ 800d300:	01001004 	movi	r4,64
+ 800d304:	2295c83a 	sub	r10,r4,r10
+ 800d308:	1a86983a 	sll	r3,r3,r10
+ 800d30c:	58d6b03a 	or	r11,r11,r3
+ 800d310:	5826c03a 	cmpne	r19,r11,zero
+ 800d314:	98a6b03a 	or	r19,r19,r2
+ 800d318:	00003006 	br	800d3dc <__adddf3+0x324>
+ 800d31c:	1ac4b03a 	or	r2,r3,r11
+ 800d320:	10007726 	beq	r2,zero,800d500 <__adddf3+0x448>
+ 800d324:	50bfffc4 	addi	r2,r10,-1
+ 800d328:	10011926 	beq	r2,zero,800d790 <__adddf3+0x6d8>
+ 800d32c:	5281ffd8 	cmpnei	r10,r10,2047
+ 800d330:	50012026 	beq	r10,zero,800d7b4 <__adddf3+0x6fc>
+ 800d334:	1015883a 	mov	r10,r2
+ 800d338:	003f7f06 	br	800d138 <__adddf3+0x80>
+ 800d33c:	1409c83a 	sub	r4,r2,r16
+ 800d340:	8000a61e 	bne	r16,zero,800d5dc <__adddf3+0x524>
+ 800d344:	4b0ab03a 	or	r5,r9,r12
+ 800d348:	2800f726 	beq	r5,zero,800d728 <__adddf3+0x670>
+ 800d34c:	217fffc4 	addi	r5,r4,-1
+ 800d350:	28017f26 	beq	r5,zero,800d950 <__adddf3+0x898>
+ 800d354:	2101ffd8 	cmpnei	r4,r4,2047
+ 800d358:	2001a326 	beq	r4,zero,800d9e8 <__adddf3+0x930>
+ 800d35c:	2809883a 	mov	r4,r5
+ 800d360:	0000a106 	br	800d5e8 <__adddf3+0x530>
+ 800d364:	1ac4b03a 	or	r2,r3,r11
+ 800d368:	10006526 	beq	r2,zero,800d500 <__adddf3+0x448>
+ 800d36c:	50bfffc4 	addi	r2,r10,-1
+ 800d370:	10000426 	beq	r2,zero,800d384 <__adddf3+0x2cc>
+ 800d374:	5281ffd8 	cmpnei	r10,r10,2047
+ 800d378:	50014326 	beq	r10,zero,800d888 <__adddf3+0x7d0>
+ 800d37c:	1015883a 	mov	r10,r2
+ 800d380:	003fd706 	br	800d2e0 <__adddf3+0x228>
+ 800d384:	62e7883a 	add	r19,r12,r11
+ 800d388:	48d3883a 	add	r9,r9,r3
+ 800d38c:	9b09803a 	cmpltu	r4,r19,r12
+ 800d390:	4909883a 	add	r4,r9,r4
+ 800d394:	2080202c 	andhi	r2,r4,128
+ 800d398:	1000b41e 	bne	r2,zero,800d66c <__adddf3+0x5b4>
+ 800d39c:	04000044 	movi	r16,1
+ 800d3a0:	988001cc 	andi	r2,r19,7
+ 800d3a4:	103f951e 	bne	r2,zero,800d1fc <__adddf3+0x144>
+ 800d3a8:	9826d0fa 	srli	r19,r19,3
+ 800d3ac:	2004977a 	slli	r2,r4,29
+ 800d3b0:	2012d0fa 	srli	r9,r4,3
+ 800d3b4:	9884b03a 	or	r2,r19,r2
+ 800d3b8:	80c1ffe0 	cmpeqi	r3,r16,2047
+ 800d3bc:	1800351e 	bne	r3,zero,800d494 <__adddf3+0x3dc>
+ 800d3c0:	01000434 	movhi	r4,16
+ 800d3c4:	213fffc4 	addi	r4,r4,-1
+ 800d3c8:	4908703a 	and	r4,r9,r4
+ 800d3cc:	8401ffcc 	andi	r16,r16,2047
+ 800d3d0:	003f9f06 	br	800d250 <__adddf3+0x198>
+ 800d3d4:	1ac8b03a 	or	r4,r3,r11
+ 800d3d8:	2026c03a 	cmpne	r19,r4,zero
+ 800d3dc:	9b27883a 	add	r19,r19,r12
+ 800d3e0:	9b09803a 	cmpltu	r4,r19,r12
+ 800d3e4:	2249883a 	add	r4,r4,r9
+ 800d3e8:	2080202c 	andhi	r2,r4,128
+ 800d3ec:	103fec26 	beq	r2,zero,800d3a0 <__adddf3+0x2e8>
+ 800d3f0:	84000044 	addi	r16,r16,1
+ 800d3f4:	8081ffe0 	cmpeqi	r2,r16,2047
+ 800d3f8:	10009d26 	beq	r2,zero,800d670 <__adddf3+0x5b8>
+ 800d3fc:	0401ffc4 	movi	r16,2047
+ 800d400:	0009883a 	mov	r4,zero
+ 800d404:	0005883a 	mov	r2,zero
+ 800d408:	003f9106 	br	800d250 <__adddf3+0x198>
+ 800d40c:	5000571e 	bne	r10,zero,800d56c <__adddf3+0x4b4>
+ 800d410:	80800044 	addi	r2,r16,1
+ 800d414:	1141ff8c 	andi	r5,r2,2046
+ 800d418:	2800ed1e 	bne	r5,zero,800d7d0 <__adddf3+0x718>
+ 800d41c:	4b04b03a 	or	r2,r9,r12
+ 800d420:	8000a826 	beq	r16,zero,800d6c4 <__adddf3+0x60c>
+ 800d424:	10010226 	beq	r2,zero,800d830 <__adddf3+0x778>
+ 800d428:	1ad6b03a 	or	r11,r3,r11
+ 800d42c:	480a977a 	slli	r5,r9,29
+ 800d430:	4812d0fa 	srli	r9,r9,3
+ 800d434:	58015f26 	beq	r11,zero,800d9b4 <__adddf3+0x8fc>
+ 800d438:	02080034 	movhi	r8,8192
+ 800d43c:	423fffc4 	addi	r8,r8,-1
+ 800d440:	2204703a 	and	r2,r4,r8
+ 800d444:	4900022c 	andhi	r4,r9,8
+ 800d448:	114ab03a 	or	r5,r2,r5
+ 800d44c:	20000826 	beq	r4,zero,800d470 <__adddf3+0x3b8>
+ 800d450:	1808d0fa 	srli	r4,r3,3
+ 800d454:	2080022c 	andhi	r2,r4,8
+ 800d458:	1000051e 	bne	r2,zero,800d470 <__adddf3+0x3b8>
+ 800d45c:	1806977a 	slli	r3,r3,29
+ 800d460:	3204703a 	and	r2,r6,r8
+ 800d464:	3823883a 	mov	r17,r7
+ 800d468:	10cab03a 	or	r5,r2,r3
+ 800d46c:	2013883a 	mov	r9,r4
+ 800d470:	2804d77a 	srli	r2,r5,29
+ 800d474:	480890fa 	slli	r4,r9,3
+ 800d478:	00c80034 	movhi	r3,8192
+ 800d47c:	18ffffc4 	addi	r3,r3,-1
+ 800d480:	1108b03a 	or	r4,r2,r4
+ 800d484:	2004977a 	slli	r2,r4,29
+ 800d488:	2012d0fa 	srli	r9,r4,3
+ 800d48c:	28ca703a 	and	r5,r5,r3
+ 800d490:	1144b03a 	or	r2,r2,r5
+ 800d494:	4886b03a 	or	r3,r9,r2
+ 800d498:	18016b26 	beq	r3,zero,800da48 <__adddf3+0x990>
+ 800d49c:	00c00434 	movhi	r3,16
+ 800d4a0:	49000234 	orhi	r4,r9,8
+ 800d4a4:	18ffffc4 	addi	r3,r3,-1
+ 800d4a8:	20c8703a 	and	r4,r4,r3
+ 800d4ac:	0401ffc4 	movi	r16,2047
+ 800d4b0:	003f6706 	br	800d250 <__adddf3+0x198>
+ 800d4b4:	017fe034 	movhi	r5,65408
+ 800d4b8:	297fffc4 	addi	r5,r5,-1
+ 800d4bc:	988001cc 	andi	r2,r19,7
+ 800d4c0:	80e1c83a 	sub	r16,r16,r3
+ 800d4c4:	2148703a 	and	r4,r4,r5
+ 800d4c8:	103f4c1e 	bne	r2,zero,800d1fc <__adddf3+0x144>
+ 800d4cc:	003fb606 	br	800d3a8 <__adddf3+0x2f0>
+ 800d4d0:	9809883a 	mov	r4,r19
+ 800d4d4:	800f7900 	call	800f790 <__clzsi2>
+ 800d4d8:	10c00604 	addi	r3,r2,24
+ 800d4dc:	19000808 	cmpgei	r4,r3,32
+ 800d4e0:	203f2f26 	beq	r4,zero,800d1a0 <__adddf3+0xe8>
+ 800d4e4:	113ffe04 	addi	r4,r2,-8
+ 800d4e8:	9908983a 	sll	r4,r19,r4
+ 800d4ec:	0027883a 	mov	r19,zero
+ 800d4f0:	003f3106 	br	800d1b8 <__adddf3+0x100>
+ 800d4f4:	1ac8b03a 	or	r4,r3,r11
+ 800d4f8:	2026c03a 	cmpne	r19,r4,zero
+ 800d4fc:	003f1c06 	br	800d170 <__adddf3+0xb8>
+ 800d500:	4826977a 	slli	r19,r9,29
+ 800d504:	00c80034 	movhi	r3,8192
+ 800d508:	18ffffc4 	addi	r3,r3,-1
+ 800d50c:	20c4703a 	and	r2,r4,r3
+ 800d510:	14c4b03a 	or	r2,r2,r19
+ 800d514:	4812d0fa 	srli	r9,r9,3
+ 800d518:	5021883a 	mov	r16,r10
+ 800d51c:	003fa606 	br	800d3b8 <__adddf3+0x300>
+ 800d520:	62e7c83a 	sub	r19,r12,r11
+ 800d524:	48e5c83a 	sub	r18,r9,r3
+ 800d528:	64c9803a 	cmpltu	r4,r12,r19
+ 800d52c:	9125c83a 	sub	r18,r18,r4
+ 800d530:	9080202c 	andhi	r2,r18,128
+ 800d534:	1000b21e 	bne	r2,zero,800d800 <__adddf3+0x748>
+ 800d538:	9c84b03a 	or	r2,r19,r18
+ 800d53c:	103f141e 	bne	r2,zero,800d190 <__adddf3+0xd8>
+ 800d540:	0013883a 	mov	r9,zero
+ 800d544:	0021883a 	mov	r16,zero
+ 800d548:	0023883a 	mov	r17,zero
+ 800d54c:	003f9c06 	br	800d3c0 <__adddf3+0x308>
+ 800d550:	4826977a 	slli	r19,r9,29
+ 800d554:	00c80034 	movhi	r3,8192
+ 800d558:	18ffffc4 	addi	r3,r3,-1
+ 800d55c:	20c4703a 	and	r2,r4,r3
+ 800d560:	14c4b03a 	or	r2,r2,r19
+ 800d564:	4812d0fa 	srli	r9,r9,3
+ 800d568:	003fca06 	br	800d494 <__adddf3+0x3dc>
+ 800d56c:	1409c83a 	sub	r4,r2,r16
+ 800d570:	80005e1e 	bne	r16,zero,800d6ec <__adddf3+0x634>
+ 800d574:	4b0ab03a 	or	r5,r9,r12
+ 800d578:	28011326 	beq	r5,zero,800d9c8 <__adddf3+0x910>
+ 800d57c:	217fffc4 	addi	r5,r4,-1
+ 800d580:	28012c26 	beq	r5,zero,800da34 <__adddf3+0x97c>
+ 800d584:	2101ffd8 	cmpnei	r4,r4,2047
+ 800d588:	2000a926 	beq	r4,zero,800d830 <__adddf3+0x778>
+ 800d58c:	2809883a 	mov	r4,r5
+ 800d590:	21400e48 	cmpgei	r5,r4,57
+ 800d594:	2800b91e 	bne	r5,zero,800d87c <__adddf3+0x7c4>
+ 800d598:	21400808 	cmpgei	r5,r4,32
+ 800d59c:	28011a1e 	bne	r5,zero,800da08 <__adddf3+0x950>
+ 800d5a0:	01400804 	movi	r5,32
+ 800d5a4:	290bc83a 	sub	r5,r5,r4
+ 800d5a8:	4966983a 	sll	r19,r9,r5
+ 800d5ac:	610cd83a 	srl	r6,r12,r4
+ 800d5b0:	614a983a 	sll	r5,r12,r5
+ 800d5b4:	4912d83a 	srl	r9,r9,r4
+ 800d5b8:	99a6b03a 	or	r19,r19,r6
+ 800d5bc:	280ac03a 	cmpne	r5,r5,zero
+ 800d5c0:	9966b03a 	or	r19,r19,r5
+ 800d5c4:	1a47883a 	add	r3,r3,r9
+ 800d5c8:	9ae7883a 	add	r19,r19,r11
+ 800d5cc:	9ac9803a 	cmpltu	r4,r19,r11
+ 800d5d0:	20c9883a 	add	r4,r4,r3
+ 800d5d4:	1021883a 	mov	r16,r2
+ 800d5d8:	003f8306 	br	800d3e8 <__adddf3+0x330>
+ 800d5dc:	1141ffd8 	cmpnei	r5,r2,2047
+ 800d5e0:	28006326 	beq	r5,zero,800d770 <__adddf3+0x6b8>
+ 800d5e4:	4a402034 	orhi	r9,r9,128
+ 800d5e8:	21400e48 	cmpgei	r5,r4,57
+ 800d5ec:	28006e1e 	bne	r5,zero,800d7a8 <__adddf3+0x6f0>
+ 800d5f0:	21400808 	cmpgei	r5,r4,32
+ 800d5f4:	2800ab1e 	bne	r5,zero,800d8a4 <__adddf3+0x7ec>
+ 800d5f8:	01400804 	movi	r5,32
+ 800d5fc:	290bc83a 	sub	r5,r5,r4
+ 800d600:	4966983a 	sll	r19,r9,r5
+ 800d604:	610cd83a 	srl	r6,r12,r4
+ 800d608:	614a983a 	sll	r5,r12,r5
+ 800d60c:	4912d83a 	srl	r9,r9,r4
+ 800d610:	99a6b03a 	or	r19,r19,r6
+ 800d614:	280ac03a 	cmpne	r5,r5,zero
+ 800d618:	9966b03a 	or	r19,r19,r5
+ 800d61c:	1a47c83a 	sub	r3,r3,r9
+ 800d620:	5ce7c83a 	sub	r19,r11,r19
+ 800d624:	5cc9803a 	cmpltu	r4,r11,r19
+ 800d628:	1909c83a 	sub	r4,r3,r4
+ 800d62c:	3823883a 	mov	r17,r7
+ 800d630:	1021883a 	mov	r16,r2
+ 800d634:	003ed106 	br	800d17c <__adddf3+0xc4>
+ 800d638:	843ff844 	addi	r16,r16,-31
+ 800d63c:	28800820 	cmpeqi	r2,r5,32
+ 800d640:	2420d83a 	srl	r16,r4,r16
+ 800d644:	1000041e 	bne	r2,zero,800d658 <__adddf3+0x5a0>
+ 800d648:	00801004 	movi	r2,64
+ 800d64c:	114bc83a 	sub	r5,r2,r5
+ 800d650:	2148983a 	sll	r4,r4,r5
+ 800d654:	9926b03a 	or	r19,r19,r4
+ 800d658:	9826c03a 	cmpne	r19,r19,zero
+ 800d65c:	9c26b03a 	or	r19,r19,r16
+ 800d660:	0009883a 	mov	r4,zero
+ 800d664:	0021883a 	mov	r16,zero
+ 800d668:	003f4d06 	br	800d3a0 <__adddf3+0x2e8>
+ 800d66c:	04000084 	movi	r16,2
+ 800d670:	00bfe034 	movhi	r2,65408
+ 800d674:	10bfffc4 	addi	r2,r2,-1
+ 800d678:	208a703a 	and	r5,r4,r2
+ 800d67c:	9804d07a 	srli	r2,r19,1
+ 800d680:	280697fa 	slli	r3,r5,31
+ 800d684:	9cc0004c 	andi	r19,r19,1
+ 800d688:	14e6b03a 	or	r19,r2,r19
+ 800d68c:	2808d07a 	srli	r4,r5,1
+ 800d690:	1ce6b03a 	or	r19,r3,r19
+ 800d694:	003ed706 	br	800d1f4 <__adddf3+0x13c>
+ 800d698:	54fff804 	addi	r19,r10,-32
+ 800d69c:	50800820 	cmpeqi	r2,r10,32
+ 800d6a0:	1ce6d83a 	srl	r19,r3,r19
+ 800d6a4:	1000041e 	bne	r2,zero,800d6b8 <__adddf3+0x600>
+ 800d6a8:	00801004 	movi	r2,64
+ 800d6ac:	1295c83a 	sub	r10,r2,r10
+ 800d6b0:	1a86983a 	sll	r3,r3,r10
+ 800d6b4:	58d6b03a 	or	r11,r11,r3
+ 800d6b8:	5808c03a 	cmpne	r4,r11,zero
+ 800d6bc:	24e6b03a 	or	r19,r4,r19
+ 800d6c0:	003eab06 	br	800d170 <__adddf3+0xb8>
+ 800d6c4:	1000a926 	beq	r2,zero,800d96c <__adddf3+0x8b4>
+ 800d6c8:	1ac4b03a 	or	r2,r3,r11
+ 800d6cc:	1000ae1e 	bne	r2,zero,800d988 <__adddf3+0x8d0>
+ 800d6d0:	4806977a 	slli	r3,r9,29
+ 800d6d4:	00880034 	movhi	r2,8192
+ 800d6d8:	10bfffc4 	addi	r2,r2,-1
+ 800d6dc:	2084703a 	and	r2,r4,r2
+ 800d6e0:	10c4b03a 	or	r2,r2,r3
+ 800d6e4:	4812d0fa 	srli	r9,r9,3
+ 800d6e8:	003f3506 	br	800d3c0 <__adddf3+0x308>
+ 800d6ec:	1141ffd8 	cmpnei	r5,r2,2047
+ 800d6f0:	28004f26 	beq	r5,zero,800d830 <__adddf3+0x778>
+ 800d6f4:	4a402034 	orhi	r9,r9,128
+ 800d6f8:	003fa506 	br	800d590 <__adddf3+0x4d8>
+ 800d6fc:	01000804 	movi	r4,32
+ 800d700:	2289c83a 	sub	r4,r4,r10
+ 800d704:	1926983a 	sll	r19,r3,r4
+ 800d708:	5a84d83a 	srl	r2,r11,r10
+ 800d70c:	5908983a 	sll	r4,r11,r4
+ 800d710:	1a86d83a 	srl	r3,r3,r10
+ 800d714:	98a6b03a 	or	r19,r19,r2
+ 800d718:	2016c03a 	cmpne	r11,r4,zero
+ 800d71c:	9ae6b03a 	or	r19,r19,r11
+ 800d720:	48d3883a 	add	r9,r9,r3
+ 800d724:	003f2d06 	br	800d3dc <__adddf3+0x324>
+ 800d728:	01480034 	movhi	r5,8192
+ 800d72c:	1826977a 	slli	r19,r3,29
+ 800d730:	297fffc4 	addi	r5,r5,-1
+ 800d734:	3144703a 	and	r2,r6,r5
+ 800d738:	14c4b03a 	or	r2,r2,r19
+ 800d73c:	1812d0fa 	srli	r9,r3,3
+ 800d740:	3823883a 	mov	r17,r7
+ 800d744:	2021883a 	mov	r16,r4
+ 800d748:	003f1b06 	br	800d3b8 <__adddf3+0x300>
+ 800d74c:	10007d26 	beq	r2,zero,800d944 <__adddf3+0x88c>
+ 800d750:	00880034 	movhi	r2,8192
+ 800d754:	1808977a 	slli	r4,r3,29
+ 800d758:	10bfffc4 	addi	r2,r2,-1
+ 800d75c:	3084703a 	and	r2,r6,r2
+ 800d760:	1104b03a 	or	r2,r2,r4
+ 800d764:	1812d0fa 	srli	r9,r3,3
+ 800d768:	3823883a 	mov	r17,r7
+ 800d76c:	003f1406 	br	800d3c0 <__adddf3+0x308>
+ 800d770:	180a977a 	slli	r5,r3,29
+ 800d774:	01080034 	movhi	r4,8192
+ 800d778:	213fffc4 	addi	r4,r4,-1
+ 800d77c:	3104703a 	and	r2,r6,r4
+ 800d780:	2884b03a 	or	r2,r5,r2
+ 800d784:	1812d0fa 	srli	r9,r3,3
+ 800d788:	3823883a 	mov	r17,r7
+ 800d78c:	003f4106 	br	800d494 <__adddf3+0x3dc>
+ 800d790:	62e7c83a 	sub	r19,r12,r11
+ 800d794:	48d3c83a 	sub	r9,r9,r3
+ 800d798:	64c9803a 	cmpltu	r4,r12,r19
+ 800d79c:	4909c83a 	sub	r4,r9,r4
+ 800d7a0:	04000044 	movi	r16,1
+ 800d7a4:	003e7506 	br	800d17c <__adddf3+0xc4>
+ 800d7a8:	4b12b03a 	or	r9,r9,r12
+ 800d7ac:	4826c03a 	cmpne	r19,r9,zero
+ 800d7b0:	003f9b06 	br	800d620 <__adddf3+0x568>
+ 800d7b4:	4826977a 	slli	r19,r9,29
+ 800d7b8:	00c80034 	movhi	r3,8192
+ 800d7bc:	18ffffc4 	addi	r3,r3,-1
+ 800d7c0:	20c4703a 	and	r2,r4,r3
+ 800d7c4:	9884b03a 	or	r2,r19,r2
+ 800d7c8:	4812d0fa 	srli	r9,r9,3
+ 800d7cc:	003f3106 	br	800d494 <__adddf3+0x3dc>
+ 800d7d0:	1101ffe0 	cmpeqi	r4,r2,2047
+ 800d7d4:	203f091e 	bne	r4,zero,800d3fc <__adddf3+0x344>
+ 800d7d8:	62d7883a 	add	r11,r12,r11
+ 800d7dc:	5b09803a 	cmpltu	r4,r11,r12
+ 800d7e0:	48d3883a 	add	r9,r9,r3
+ 800d7e4:	490b883a 	add	r5,r9,r4
+ 800d7e8:	282697fa 	slli	r19,r5,31
+ 800d7ec:	5816d07a 	srli	r11,r11,1
+ 800d7f0:	2808d07a 	srli	r4,r5,1
+ 800d7f4:	1021883a 	mov	r16,r2
+ 800d7f8:	9ae6b03a 	or	r19,r19,r11
+ 800d7fc:	003ee806 	br	800d3a0 <__adddf3+0x2e8>
+ 800d800:	5b27c83a 	sub	r19,r11,r12
+ 800d804:	1a53c83a 	sub	r9,r3,r9
+ 800d808:	5cc9803a 	cmpltu	r4,r11,r19
+ 800d80c:	4925c83a 	sub	r18,r9,r4
+ 800d810:	3823883a 	mov	r17,r7
+ 800d814:	003e5e06 	br	800d190 <__adddf3+0xd8>
+ 800d818:	28002d1e 	bne	r5,zero,800d8d0 <__adddf3+0x818>
+ 800d81c:	103fd41e 	bne	r2,zero,800d770 <__adddf3+0x6b8>
+ 800d820:	00bfffc4 	movi	r2,-1
+ 800d824:	0023883a 	mov	r17,zero
+ 800d828:	4013883a 	mov	r9,r8
+ 800d82c:	003f1b06 	br	800d49c <__adddf3+0x3e4>
+ 800d830:	00880034 	movhi	r2,8192
+ 800d834:	1808977a 	slli	r4,r3,29
+ 800d838:	10bfffc4 	addi	r2,r2,-1
+ 800d83c:	3084703a 	and	r2,r6,r2
+ 800d840:	1104b03a 	or	r2,r2,r4
+ 800d844:	1812d0fa 	srli	r9,r3,3
+ 800d848:	003f1206 	br	800d494 <__adddf3+0x3dc>
+ 800d84c:	62e7c83a 	sub	r19,r12,r11
+ 800d850:	48cbc83a 	sub	r5,r9,r3
+ 800d854:	64c9803a 	cmpltu	r4,r12,r19
+ 800d858:	2909c83a 	sub	r4,r5,r4
+ 800d85c:	2080202c 	andhi	r2,r4,128
+ 800d860:	10003626 	beq	r2,zero,800d93c <__adddf3+0x884>
+ 800d864:	5b27c83a 	sub	r19,r11,r12
+ 800d868:	1a53c83a 	sub	r9,r3,r9
+ 800d86c:	5cc9803a 	cmpltu	r4,r11,r19
+ 800d870:	4909c83a 	sub	r4,r9,r4
+ 800d874:	3823883a 	mov	r17,r7
+ 800d878:	003e5e06 	br	800d1f4 <__adddf3+0x13c>
+ 800d87c:	4b12b03a 	or	r9,r9,r12
+ 800d880:	4826c03a 	cmpne	r19,r9,zero
+ 800d884:	003f5006 	br	800d5c8 <__adddf3+0x510>
+ 800d888:	4806977a 	slli	r3,r9,29
+ 800d88c:	00880034 	movhi	r2,8192
+ 800d890:	10bfffc4 	addi	r2,r2,-1
+ 800d894:	2084703a 	and	r2,r4,r2
+ 800d898:	10c4b03a 	or	r2,r2,r3
+ 800d89c:	4812d0fa 	srli	r9,r9,3
+ 800d8a0:	003efc06 	br	800d494 <__adddf3+0x3dc>
+ 800d8a4:	217ff804 	addi	r5,r4,-32
+ 800d8a8:	21800820 	cmpeqi	r6,r4,32
+ 800d8ac:	494ad83a 	srl	r5,r9,r5
+ 800d8b0:	3000041e 	bne	r6,zero,800d8c4 <__adddf3+0x80c>
+ 800d8b4:	01801004 	movi	r6,64
+ 800d8b8:	3109c83a 	sub	r4,r6,r4
+ 800d8bc:	4912983a 	sll	r9,r9,r4
+ 800d8c0:	6258b03a 	or	r12,r12,r9
+ 800d8c4:	6026c03a 	cmpne	r19,r12,zero
+ 800d8c8:	9966b03a 	or	r19,r19,r5
+ 800d8cc:	003f5406 	br	800d620 <__adddf3+0x568>
+ 800d8d0:	480a977a 	slli	r5,r9,29
+ 800d8d4:	4812d0fa 	srli	r9,r9,3
+ 800d8d8:	10003626 	beq	r2,zero,800d9b4 <__adddf3+0x8fc>
+ 800d8dc:	02080034 	movhi	r8,8192
+ 800d8e0:	423fffc4 	addi	r8,r8,-1
+ 800d8e4:	2204703a 	and	r2,r4,r8
+ 800d8e8:	4900022c 	andhi	r4,r9,8
+ 800d8ec:	114ab03a 	or	r5,r2,r5
+ 800d8f0:	20000826 	beq	r4,zero,800d914 <__adddf3+0x85c>
+ 800d8f4:	1808d0fa 	srli	r4,r3,3
+ 800d8f8:	2080022c 	andhi	r2,r4,8
+ 800d8fc:	1000051e 	bne	r2,zero,800d914 <__adddf3+0x85c>
+ 800d900:	1806977a 	slli	r3,r3,29
+ 800d904:	3204703a 	and	r2,r6,r8
+ 800d908:	3823883a 	mov	r17,r7
+ 800d90c:	10cab03a 	or	r5,r2,r3
+ 800d910:	2013883a 	mov	r9,r4
+ 800d914:	480890fa 	slli	r4,r9,3
+ 800d918:	2804d77a 	srli	r2,r5,29
+ 800d91c:	00c80034 	movhi	r3,8192
+ 800d920:	18ffffc4 	addi	r3,r3,-1
+ 800d924:	1108b03a 	or	r4,r2,r4
+ 800d928:	200c977a 	slli	r6,r4,29
+ 800d92c:	28c4703a 	and	r2,r5,r3
+ 800d930:	2012d0fa 	srli	r9,r4,3
+ 800d934:	3084b03a 	or	r2,r6,r2
+ 800d938:	003ed606 	br	800d494 <__adddf3+0x3dc>
+ 800d93c:	9904b03a 	or	r2,r19,r4
+ 800d940:	103e971e 	bne	r2,zero,800d3a0 <__adddf3+0x2e8>
+ 800d944:	0013883a 	mov	r9,zero
+ 800d948:	0023883a 	mov	r17,zero
+ 800d94c:	003e9c06 	br	800d3c0 <__adddf3+0x308>
+ 800d950:	5b27c83a 	sub	r19,r11,r12
+ 800d954:	1a53c83a 	sub	r9,r3,r9
+ 800d958:	5cc9803a 	cmpltu	r4,r11,r19
+ 800d95c:	4909c83a 	sub	r4,r9,r4
+ 800d960:	3823883a 	mov	r17,r7
+ 800d964:	04000044 	movi	r16,1
+ 800d968:	003e0406 	br	800d17c <__adddf3+0xc4>
+ 800d96c:	180a977a 	slli	r5,r3,29
+ 800d970:	01080034 	movhi	r4,8192
+ 800d974:	213fffc4 	addi	r4,r4,-1
+ 800d978:	3104703a 	and	r2,r6,r4
+ 800d97c:	2884b03a 	or	r2,r5,r2
+ 800d980:	1812d0fa 	srli	r9,r3,3
+ 800d984:	003e8e06 	br	800d3c0 <__adddf3+0x308>
+ 800d988:	62e7883a 	add	r19,r12,r11
+ 800d98c:	48d3883a 	add	r9,r9,r3
+ 800d990:	9b09803a 	cmpltu	r4,r19,r12
+ 800d994:	4909883a 	add	r4,r9,r4
+ 800d998:	2080202c 	andhi	r2,r4,128
+ 800d99c:	103e8026 	beq	r2,zero,800d3a0 <__adddf3+0x2e8>
+ 800d9a0:	00bfe034 	movhi	r2,65408
+ 800d9a4:	10bfffc4 	addi	r2,r2,-1
+ 800d9a8:	2088703a 	and	r4,r4,r2
+ 800d9ac:	04000044 	movi	r16,1
+ 800d9b0:	003e7b06 	br	800d3a0 <__adddf3+0x2e8>
+ 800d9b4:	00880034 	movhi	r2,8192
+ 800d9b8:	10bfffc4 	addi	r2,r2,-1
+ 800d9bc:	2084703a 	and	r2,r4,r2
+ 800d9c0:	1144b03a 	or	r2,r2,r5
+ 800d9c4:	003eb306 	br	800d494 <__adddf3+0x3dc>
+ 800d9c8:	180e977a 	slli	r7,r3,29
+ 800d9cc:	01480034 	movhi	r5,8192
+ 800d9d0:	297fffc4 	addi	r5,r5,-1
+ 800d9d4:	3144703a 	and	r2,r6,r5
+ 800d9d8:	3884b03a 	or	r2,r7,r2
+ 800d9dc:	1812d0fa 	srli	r9,r3,3
+ 800d9e0:	2021883a 	mov	r16,r4
+ 800d9e4:	003e7406 	br	800d3b8 <__adddf3+0x300>
+ 800d9e8:	00880034 	movhi	r2,8192
+ 800d9ec:	1808977a 	slli	r4,r3,29
+ 800d9f0:	10bfffc4 	addi	r2,r2,-1
+ 800d9f4:	3084703a 	and	r2,r6,r2
+ 800d9f8:	1104b03a 	or	r2,r2,r4
+ 800d9fc:	1812d0fa 	srli	r9,r3,3
+ 800da00:	3823883a 	mov	r17,r7
+ 800da04:	003ea306 	br	800d494 <__adddf3+0x3dc>
+ 800da08:	217ff804 	addi	r5,r4,-32
+ 800da0c:	21800820 	cmpeqi	r6,r4,32
+ 800da10:	494ad83a 	srl	r5,r9,r5
+ 800da14:	3000041e 	bne	r6,zero,800da28 <__adddf3+0x970>
+ 800da18:	01801004 	movi	r6,64
+ 800da1c:	3109c83a 	sub	r4,r6,r4
+ 800da20:	4912983a 	sll	r9,r9,r4
+ 800da24:	6258b03a 	or	r12,r12,r9
+ 800da28:	6026c03a 	cmpne	r19,r12,zero
+ 800da2c:	9966b03a 	or	r19,r19,r5
+ 800da30:	003ee506 	br	800d5c8 <__adddf3+0x510>
+ 800da34:	62e7883a 	add	r19,r12,r11
+ 800da38:	48d3883a 	add	r9,r9,r3
+ 800da3c:	9ac9803a 	cmpltu	r4,r19,r11
+ 800da40:	4909883a 	add	r4,r9,r4
+ 800da44:	003e5306 	br	800d394 <__adddf3+0x2dc>
+ 800da48:	0005883a 	mov	r2,zero
+ 800da4c:	0401ffc4 	movi	r16,2047
+ 800da50:	0009883a 	mov	r4,zero
+ 800da54:	003dfe06 	br	800d250 <__adddf3+0x198>
+
+0800da58 <__divdf3>:
+ 800da58:	defff104 	addi	sp,sp,-60
+ 800da5c:	2804d53a 	srli	r2,r5,20
+ 800da60:	dd000915 	stw	r20,36(sp)
+ 800da64:	2828d7fa 	srli	r20,r5,31
+ 800da68:	dc000515 	stw	r16,20(sp)
+ 800da6c:	04000434 	movhi	r16,16
+ 800da70:	ddc00c15 	stw	r23,48(sp)
+ 800da74:	dc800715 	stw	r18,28(sp)
+ 800da78:	843fffc4 	addi	r16,r16,-1
+ 800da7c:	dfc00e15 	stw	ra,56(sp)
+ 800da80:	df000d15 	stw	fp,52(sp)
+ 800da84:	dd800b15 	stw	r22,44(sp)
+ 800da88:	dd400a15 	stw	r21,40(sp)
+ 800da8c:	dcc00815 	stw	r19,32(sp)
+ 800da90:	dc400615 	stw	r17,24(sp)
+ 800da94:	1081ffcc 	andi	r2,r2,2047
+ 800da98:	2025883a 	mov	r18,r4
+ 800da9c:	2c20703a 	and	r16,r5,r16
+ 800daa0:	a02f883a 	mov	r23,r20
+ 800daa4:	10008926 	beq	r2,zero,800dccc <__divdf3+0x274>
+ 800daa8:	10c1ffe0 	cmpeqi	r3,r2,2047
+ 800daac:	18009f1e 	bne	r3,zero,800dd2c <__divdf3+0x2d4>
+ 800dab0:	800a90fa 	slli	r5,r16,3
+ 800dab4:	2008d77a 	srli	r4,r4,29
+ 800dab8:	902490fa 	slli	r18,r18,3
+ 800dabc:	157f0044 	addi	r21,r2,-1023
+ 800dac0:	2148b03a 	or	r4,r4,r5
+ 800dac4:	25802034 	orhi	r22,r4,128
+ 800dac8:	0023883a 	mov	r17,zero
+ 800dacc:	0021883a 	mov	r16,zero
+ 800dad0:	3806d53a 	srli	r3,r7,20
+ 800dad4:	01000434 	movhi	r4,16
+ 800dad8:	213fffc4 	addi	r4,r4,-1
+ 800dadc:	18c1ffcc 	andi	r3,r3,2047
+ 800dae0:	3926703a 	and	r19,r7,r4
+ 800dae4:	380ed7fa 	srli	r7,r7,31
+ 800dae8:	18006326 	beq	r3,zero,800dc78 <__divdf3+0x220>
+ 800daec:	1881ffe0 	cmpeqi	r2,r3,2047
+ 800daf0:	1000201e 	bne	r2,zero,800db74 <__divdf3+0x11c>
+ 800daf4:	980890fa 	slli	r4,r19,3
+ 800daf8:	300ad77a 	srli	r5,r6,29
+ 800dafc:	301090fa 	slli	r8,r6,3
+ 800db00:	18ff0044 	addi	r3,r3,-1023
+ 800db04:	2908b03a 	or	r4,r5,r4
+ 800db08:	a8ebc83a 	sub	r21,r21,r3
+ 800db0c:	24c02034 	orhi	r19,r4,128
+ 800db10:	0007883a 	mov	r3,zero
+ 800db14:	89800428 	cmpgeui	r6,r17,16
+ 800db18:	a1f8f03a 	xor	fp,r20,r7
+ 800db1c:	3000ad1e 	bne	r6,zero,800ddd4 <__divdf3+0x37c>
+ 800db20:	882290ba 	slli	r17,r17,2
+ 800db24:	00820074 	movhi	r2,2049
+ 800db28:	8885883a 	add	r2,r17,r2
+ 800db2c:	10b6cd17 	ldw	r2,-9420(r2)
+ 800db30:	1000683a 	jmp	r2
+ 800db34:	0800ddd4 	ori	zero,at,887
+ 800db38:	0800dc68 	cmpgeui	zero,at,881
+ 800db3c:	0800dc0c 	andi	zero,at,880
+ 800db40:	0800db90 	cmplti	zero,at,878
+ 800db44:	0800dc0c 	andi	zero,at,880
+ 800db48:	0800dd90 	cmplti	zero,at,886
+ 800db4c:	0800dc0c 	andi	zero,at,880
+ 800db50:	0800db90 	cmplti	zero,at,878
+ 800db54:	0800dc68 	cmpgeui	zero,at,881
+ 800db58:	0800dc68 	cmpgeui	zero,at,881
+ 800db5c:	0800dd90 	cmplti	zero,at,886
+ 800db60:	0800db90 	cmplti	zero,at,878
+ 800db64:	0800dba0 	cmpeqi	zero,at,878
+ 800db68:	0800dba0 	cmpeqi	zero,at,878
+ 800db6c:	0800dba0 	cmpeqi	zero,at,878
+ 800db70:	0800dda8 	cmpgeui	zero,at,886
+ 800db74:	9990b03a 	or	r8,r19,r6
+ 800db78:	ad7e0044 	addi	r21,r21,-2047
+ 800db7c:	4000801e 	bne	r8,zero,800dd80 <__divdf3+0x328>
+ 800db80:	8c400094 	ori	r17,r17,2
+ 800db84:	0027883a 	mov	r19,zero
+ 800db88:	00c00084 	movi	r3,2
+ 800db8c:	003fe106 	br	800db14 <__divdf3+0xbc>
+ 800db90:	382f883a 	mov	r23,r7
+ 800db94:	982d883a 	mov	r22,r19
+ 800db98:	4025883a 	mov	r18,r8
+ 800db9c:	1821883a 	mov	r16,r3
+ 800dba0:	808000a0 	cmpeqi	r2,r16,2
+ 800dba4:	10017c1e 	bne	r2,zero,800e198 <__divdf3+0x740>
+ 800dba8:	808000e0 	cmpeqi	r2,r16,3
+ 800dbac:	1001ca1e 	bne	r2,zero,800e2d8 <__divdf3+0x880>
+ 800dbb0:	80800060 	cmpeqi	r2,r16,1
+ 800dbb4:	1000141e 	bne	r2,zero,800dc08 <__divdf3+0x1b0>
+ 800dbb8:	ac00ffc4 	addi	r16,r21,1023
+ 800dbbc:	b839883a 	mov	fp,r23
+ 800dbc0:	0401580e 	bge	zero,r16,800e124 <__divdf3+0x6cc>
+ 800dbc4:	908001cc 	andi	r2,r18,7
+ 800dbc8:	1001921e 	bne	r2,zero,800e214 <__divdf3+0x7bc>
+ 800dbcc:	900ad0fa 	srli	r5,r18,3
+ 800dbd0:	b080402c 	andhi	r2,r22,256
+ 800dbd4:	10000426 	beq	r2,zero,800dbe8 <__divdf3+0x190>
+ 800dbd8:	00bfc034 	movhi	r2,65280
+ 800dbdc:	10bfffc4 	addi	r2,r2,-1
+ 800dbe0:	b0ac703a 	and	r22,r22,r2
+ 800dbe4:	ac010004 	addi	r16,r21,1024
+ 800dbe8:	8081ffc8 	cmpgei	r2,r16,2047
+ 800dbec:	10001e1e 	bne	r2,zero,800dc68 <__divdf3+0x210>
+ 800dbf0:	b024977a 	slli	r18,r22,29
+ 800dbf4:	b008927a 	slli	r4,r22,9
+ 800dbf8:	8081ffcc 	andi	r2,r16,2047
+ 800dbfc:	9164b03a 	or	r18,r18,r5
+ 800dc00:	2008d33a 	srli	r4,r4,12
+ 800dc04:	00000406 	br	800dc18 <__divdf3+0x1c0>
+ 800dc08:	b839883a 	mov	fp,r23
+ 800dc0c:	0005883a 	mov	r2,zero
+ 800dc10:	0009883a 	mov	r4,zero
+ 800dc14:	0025883a 	mov	r18,zero
+ 800dc18:	1004953a 	slli	r2,r2,20
+ 800dc1c:	00c00434 	movhi	r3,16
+ 800dc20:	e03897fa 	slli	fp,fp,31
+ 800dc24:	18ffffc4 	addi	r3,r3,-1
+ 800dc28:	20c6703a 	and	r3,r4,r3
+ 800dc2c:	1886b03a 	or	r3,r3,r2
+ 800dc30:	1f06b03a 	or	r3,r3,fp
+ 800dc34:	9005883a 	mov	r2,r18
+ 800dc38:	dfc00e17 	ldw	ra,56(sp)
+ 800dc3c:	df000d17 	ldw	fp,52(sp)
+ 800dc40:	ddc00c17 	ldw	r23,48(sp)
+ 800dc44:	dd800b17 	ldw	r22,44(sp)
+ 800dc48:	dd400a17 	ldw	r21,40(sp)
+ 800dc4c:	dd000917 	ldw	r20,36(sp)
+ 800dc50:	dcc00817 	ldw	r19,32(sp)
+ 800dc54:	dc800717 	ldw	r18,28(sp)
+ 800dc58:	dc400617 	ldw	r17,24(sp)
+ 800dc5c:	dc000517 	ldw	r16,20(sp)
+ 800dc60:	dec00f04 	addi	sp,sp,60
+ 800dc64:	f800283a 	ret
+ 800dc68:	0081ffc4 	movi	r2,2047
+ 800dc6c:	0009883a 	mov	r4,zero
+ 800dc70:	0025883a 	mov	r18,zero
+ 800dc74:	003fe806 	br	800dc18 <__divdf3+0x1c0>
+ 800dc78:	9990b03a 	or	r8,r19,r6
+ 800dc7c:	40003c26 	beq	r8,zero,800dd70 <__divdf3+0x318>
+ 800dc80:	98011826 	beq	r19,zero,800e0e4 <__divdf3+0x68c>
+ 800dc84:	9809883a 	mov	r4,r19
+ 800dc88:	d9800115 	stw	r6,4(sp)
+ 800dc8c:	d9c00015 	stw	r7,0(sp)
+ 800dc90:	800f7900 	call	800f790 <__clzsi2>
+ 800dc94:	d9c00017 	ldw	r7,0(sp)
+ 800dc98:	d9800117 	ldw	r6,4(sp)
+ 800dc9c:	117ffd44 	addi	r5,r2,-11
+ 800dca0:	00c00744 	movi	r3,29
+ 800dca4:	123ffe04 	addi	r8,r2,-8
+ 800dca8:	1947c83a 	sub	r3,r3,r5
+ 800dcac:	9a08983a 	sll	r4,r19,r8
+ 800dcb0:	30c6d83a 	srl	r3,r6,r3
+ 800dcb4:	3210983a 	sll	r8,r6,r8
+ 800dcb8:	1926b03a 	or	r19,r3,r4
+ 800dcbc:	1545883a 	add	r2,r2,r21
+ 800dcc0:	1540fcc4 	addi	r21,r2,1011
+ 800dcc4:	0007883a 	mov	r3,zero
+ 800dcc8:	003f9206 	br	800db14 <__divdf3+0xbc>
+ 800dccc:	242cb03a 	or	r22,r4,r16
+ 800dcd0:	2023883a 	mov	r17,r4
+ 800dcd4:	b0002126 	beq	r22,zero,800dd5c <__divdf3+0x304>
+ 800dcd8:	d9c00115 	stw	r7,4(sp)
+ 800dcdc:	d9800015 	stw	r6,0(sp)
+ 800dce0:	8000f526 	beq	r16,zero,800e0b8 <__divdf3+0x660>
+ 800dce4:	8009883a 	mov	r4,r16
+ 800dce8:	800f7900 	call	800f790 <__clzsi2>
+ 800dcec:	d9800017 	ldw	r6,0(sp)
+ 800dcf0:	d9c00117 	ldw	r7,4(sp)
+ 800dcf4:	102b883a 	mov	r21,r2
+ 800dcf8:	113ffd44 	addi	r4,r2,-11
+ 800dcfc:	05800744 	movi	r22,29
+ 800dd00:	acbffe04 	addi	r18,r21,-8
+ 800dd04:	b12dc83a 	sub	r22,r22,r4
+ 800dd08:	848a983a 	sll	r5,r16,r18
+ 800dd0c:	8d88d83a 	srl	r4,r17,r22
+ 800dd10:	8ca4983a 	sll	r18,r17,r18
+ 800dd14:	216cb03a 	or	r22,r4,r5
+ 800dd18:	00bf0344 	movi	r2,-1011
+ 800dd1c:	156bc83a 	sub	r21,r2,r21
+ 800dd20:	0023883a 	mov	r17,zero
+ 800dd24:	0021883a 	mov	r16,zero
+ 800dd28:	003f6906 	br	800dad0 <__divdf3+0x78>
+ 800dd2c:	242cb03a 	or	r22,r4,r16
+ 800dd30:	b000051e 	bne	r22,zero,800dd48 <__divdf3+0x2f0>
+ 800dd34:	0025883a 	mov	r18,zero
+ 800dd38:	04400204 	movi	r17,8
+ 800dd3c:	0541ffc4 	movi	r21,2047
+ 800dd40:	04000084 	movi	r16,2
+ 800dd44:	003f6206 	br	800dad0 <__divdf3+0x78>
+ 800dd48:	802d883a 	mov	r22,r16
+ 800dd4c:	04400304 	movi	r17,12
+ 800dd50:	0541ffc4 	movi	r21,2047
+ 800dd54:	040000c4 	movi	r16,3
+ 800dd58:	003f5d06 	br	800dad0 <__divdf3+0x78>
+ 800dd5c:	0025883a 	mov	r18,zero
+ 800dd60:	04400104 	movi	r17,4
+ 800dd64:	002b883a 	mov	r21,zero
+ 800dd68:	04000044 	movi	r16,1
+ 800dd6c:	003f5806 	br	800dad0 <__divdf3+0x78>
+ 800dd70:	8c400054 	ori	r17,r17,1
+ 800dd74:	0027883a 	mov	r19,zero
+ 800dd78:	00c00044 	movi	r3,1
+ 800dd7c:	003f6506 	br	800db14 <__divdf3+0xbc>
+ 800dd80:	8c4000d4 	ori	r17,r17,3
+ 800dd84:	3011883a 	mov	r8,r6
+ 800dd88:	00c000c4 	movi	r3,3
+ 800dd8c:	003f6106 	br	800db14 <__divdf3+0xbc>
+ 800dd90:	01000434 	movhi	r4,16
+ 800dd94:	0039883a 	mov	fp,zero
+ 800dd98:	213fffc4 	addi	r4,r4,-1
+ 800dd9c:	04bfffc4 	movi	r18,-1
+ 800dda0:	0081ffc4 	movi	r2,2047
+ 800dda4:	003f9c06 	br	800dc18 <__divdf3+0x1c0>
+ 800dda8:	b080022c 	andhi	r2,r22,8
+ 800ddac:	1000a126 	beq	r2,zero,800e034 <__divdf3+0x5dc>
+ 800ddb0:	9880022c 	andhi	r2,r19,8
+ 800ddb4:	10009f1e 	bne	r2,zero,800e034 <__divdf3+0x5dc>
+ 800ddb8:	00800434 	movhi	r2,16
+ 800ddbc:	99000234 	orhi	r4,r19,8
+ 800ddc0:	10bfffc4 	addi	r2,r2,-1
+ 800ddc4:	2088703a 	and	r4,r4,r2
+ 800ddc8:	3839883a 	mov	fp,r7
+ 800ddcc:	4025883a 	mov	r18,r8
+ 800ddd0:	003ff306 	br	800dda0 <__divdf3+0x348>
+ 800ddd4:	9d80b236 	bltu	r19,r22,800e0a0 <__divdf3+0x648>
+ 800ddd8:	9d80b026 	beq	r19,r22,800e09c <__divdf3+0x644>
+ 800dddc:	ad7fffc4 	addi	r21,r21,-1
+ 800dde0:	b007883a 	mov	r3,r22
+ 800dde4:	0021883a 	mov	r16,zero
+ 800dde8:	400cd63a 	srli	r6,r8,24
+ 800ddec:	9826923a 	slli	r19,r19,8
+ 800ddf0:	4004923a 	slli	r2,r8,8
+ 800ddf4:	1809883a 	mov	r4,r3
+ 800ddf8:	34e2b03a 	or	r17,r6,r19
+ 800ddfc:	8828d43a 	srli	r20,r17,16
+ 800de00:	d8c00115 	stw	r3,4(sp)
+ 800de04:	d8800015 	stw	r2,0(sp)
+ 800de08:	a00b883a 	mov	r5,r20
+ 800de0c:	800cff80 	call	800cff8 <__udivsi3>
+ 800de10:	d8c00117 	ldw	r3,4(sp)
+ 800de14:	a00b883a 	mov	r5,r20
+ 800de18:	102d883a 	mov	r22,r2
+ 800de1c:	1809883a 	mov	r4,r3
+ 800de20:	800d05c0 	call	800d05c <__umodsi3>
+ 800de24:	1006943a 	slli	r3,r2,16
+ 800de28:	8dffffcc 	andi	r23,r17,65535
+ 800de2c:	9004d43a 	srli	r2,r18,16
+ 800de30:	bda7383a 	mul	r19,r23,r22
+ 800de34:	10c4b03a 	or	r2,r2,r3
+ 800de38:	14c0042e 	bgeu	r2,r19,800de4c <__divdf3+0x3f4>
+ 800de3c:	1445883a 	add	r2,r2,r17
+ 800de40:	b0ffffc4 	addi	r3,r22,-1
+ 800de44:	1440e12e 	bgeu	r2,r17,800e1cc <__divdf3+0x774>
+ 800de48:	182d883a 	mov	r22,r3
+ 800de4c:	14e7c83a 	sub	r19,r2,r19
+ 800de50:	a00b883a 	mov	r5,r20
+ 800de54:	9809883a 	mov	r4,r19
+ 800de58:	800cff80 	call	800cff8 <__udivsi3>
+ 800de5c:	a00b883a 	mov	r5,r20
+ 800de60:	9809883a 	mov	r4,r19
+ 800de64:	d8800115 	stw	r2,4(sp)
+ 800de68:	800d05c0 	call	800d05c <__umodsi3>
+ 800de6c:	d8c00117 	ldw	r3,4(sp)
+ 800de70:	1004943a 	slli	r2,r2,16
+ 800de74:	94bfffcc 	andi	r18,r18,65535
+ 800de78:	b8cb383a 	mul	r5,r23,r3
+ 800de7c:	9084b03a 	or	r2,r18,r2
+ 800de80:	1140042e 	bgeu	r2,r5,800de94 <__divdf3+0x43c>
+ 800de84:	1445883a 	add	r2,r2,r17
+ 800de88:	193fffc4 	addi	r4,r3,-1
+ 800de8c:	1440cb2e 	bgeu	r2,r17,800e1bc <__divdf3+0x764>
+ 800de90:	2007883a 	mov	r3,r4
+ 800de94:	b008943a 	slli	r4,r22,16
+ 800de98:	d9800017 	ldw	r6,0(sp)
+ 800de9c:	1145c83a 	sub	r2,r2,r5
+ 800dea0:	20ecb03a 	or	r22,r4,r3
+ 800dea4:	b0ffffcc 	andi	r3,r22,65535
+ 800dea8:	300ed43a 	srli	r7,r6,16
+ 800deac:	323fffcc 	andi	r8,r6,65535
+ 800deb0:	b026d43a 	srli	r19,r22,16
+ 800deb4:	40e5383a 	mul	r18,r8,r3
+ 800deb8:	38c9383a 	mul	r4,r7,r3
+ 800debc:	9a13383a 	mul	r9,r19,r8
+ 800dec0:	9006d43a 	srli	r3,r18,16
+ 800dec4:	2249883a 	add	r4,r4,r9
+ 800dec8:	1907883a 	add	r3,r3,r4
+ 800decc:	99c9383a 	mul	r4,r19,r7
+ 800ded0:	1a40022e 	bgeu	r3,r9,800dedc <__divdf3+0x484>
+ 800ded4:	01400074 	movhi	r5,1
+ 800ded8:	2149883a 	add	r4,r4,r5
+ 800dedc:	1826d43a 	srli	r19,r3,16
+ 800dee0:	1806943a 	slli	r3,r3,16
+ 800dee4:	94bfffcc 	andi	r18,r18,65535
+ 800dee8:	9927883a 	add	r19,r19,r4
+ 800deec:	1ca5883a 	add	r18,r3,r18
+ 800def0:	14c05f36 	bltu	r2,r19,800e070 <__divdf3+0x618>
+ 800def4:	14c05d26 	beq	r2,r19,800e06c <__divdf3+0x614>
+ 800def8:	84a5c83a 	sub	r18,r16,r18
+ 800defc:	14c5c83a 	sub	r2,r2,r19
+ 800df00:	84a7803a 	cmpltu	r19,r16,r18
+ 800df04:	da000215 	stw	r8,8(sp)
+ 800df08:	d9c00115 	stw	r7,4(sp)
+ 800df0c:	14e7c83a 	sub	r19,r2,r19
+ 800df10:	ac00ffc4 	addi	r16,r21,1023
+ 800df14:	8cc0b626 	beq	r17,r19,800e1f0 <__divdf3+0x798>
+ 800df18:	9809883a 	mov	r4,r19
+ 800df1c:	a00b883a 	mov	r5,r20
+ 800df20:	800cff80 	call	800cff8 <__udivsi3>
+ 800df24:	9809883a 	mov	r4,r19
+ 800df28:	a00b883a 	mov	r5,r20
+ 800df2c:	d8800315 	stw	r2,12(sp)
+ 800df30:	800d05c0 	call	800d05c <__umodsi3>
+ 800df34:	d8c00317 	ldw	r3,12(sp)
+ 800df38:	1008943a 	slli	r4,r2,16
+ 800df3c:	9004d43a 	srli	r2,r18,16
+ 800df40:	b8e7383a 	mul	r19,r23,r3
+ 800df44:	d9c00117 	ldw	r7,4(sp)
+ 800df48:	1104b03a 	or	r2,r2,r4
+ 800df4c:	da000217 	ldw	r8,8(sp)
+ 800df50:	14c0062e 	bgeu	r2,r19,800df6c <__divdf3+0x514>
+ 800df54:	1445883a 	add	r2,r2,r17
+ 800df58:	193fffc4 	addi	r4,r3,-1
+ 800df5c:	1440ab36 	bltu	r2,r17,800e20c <__divdf3+0x7b4>
+ 800df60:	14c0aa2e 	bgeu	r2,r19,800e20c <__divdf3+0x7b4>
+ 800df64:	18ffff84 	addi	r3,r3,-2
+ 800df68:	1445883a 	add	r2,r2,r17
+ 800df6c:	14e7c83a 	sub	r19,r2,r19
+ 800df70:	a00b883a 	mov	r5,r20
+ 800df74:	9809883a 	mov	r4,r19
+ 800df78:	da000415 	stw	r8,16(sp)
+ 800df7c:	d8c00315 	stw	r3,12(sp)
+ 800df80:	d9c00215 	stw	r7,8(sp)
+ 800df84:	800cff80 	call	800cff8 <__udivsi3>
+ 800df88:	a00b883a 	mov	r5,r20
+ 800df8c:	9809883a 	mov	r4,r19
+ 800df90:	d8800115 	stw	r2,4(sp)
+ 800df94:	800d05c0 	call	800d05c <__umodsi3>
+ 800df98:	da400117 	ldw	r9,4(sp)
+ 800df9c:	1004943a 	slli	r2,r2,16
+ 800dfa0:	94bfffcc 	andi	r18,r18,65535
+ 800dfa4:	ba6f383a 	mul	r23,r23,r9
+ 800dfa8:	9084b03a 	or	r2,r18,r2
+ 800dfac:	d9c00217 	ldw	r7,8(sp)
+ 800dfb0:	d8c00317 	ldw	r3,12(sp)
+ 800dfb4:	da000417 	ldw	r8,16(sp)
+ 800dfb8:	15c0062e 	bgeu	r2,r23,800dfd4 <__divdf3+0x57c>
+ 800dfbc:	1445883a 	add	r2,r2,r17
+ 800dfc0:	493fffc4 	addi	r4,r9,-1
+ 800dfc4:	14408f36 	bltu	r2,r17,800e204 <__divdf3+0x7ac>
+ 800dfc8:	15c08e2e 	bgeu	r2,r23,800e204 <__divdf3+0x7ac>
+ 800dfcc:	4a7fff84 	addi	r9,r9,-2
+ 800dfd0:	1445883a 	add	r2,r2,r17
+ 800dfd4:	180a943a 	slli	r5,r3,16
+ 800dfd8:	15c5c83a 	sub	r2,r2,r23
+ 800dfdc:	2a64b03a 	or	r18,r5,r9
+ 800dfe0:	9012d43a 	srli	r9,r18,16
+ 800dfe4:	913fffcc 	andi	r4,r18,65535
+ 800dfe8:	220b383a 	mul	r5,r4,r8
+ 800dfec:	3909383a 	mul	r4,r7,r4
+ 800dff0:	4a11383a 	mul	r8,r9,r8
+ 800dff4:	2806d43a 	srli	r3,r5,16
+ 800dff8:	3a4f383a 	mul	r7,r7,r9
+ 800dffc:	2209883a 	add	r4,r4,r8
+ 800e000:	1907883a 	add	r3,r3,r4
+ 800e004:	1a00022e 	bgeu	r3,r8,800e010 <__divdf3+0x5b8>
+ 800e008:	01000074 	movhi	r4,1
+ 800e00c:	390f883a 	add	r7,r7,r4
+ 800e010:	1808d43a 	srli	r4,r3,16
+ 800e014:	1806943a 	slli	r3,r3,16
+ 800e018:	297fffcc 	andi	r5,r5,65535
+ 800e01c:	21cf883a 	add	r7,r4,r7
+ 800e020:	1947883a 	add	r3,r3,r5
+ 800e024:	11c00a36 	bltu	r2,r7,800e050 <__divdf3+0x5f8>
+ 800e028:	11c00826 	beq	r2,r7,800e04c <__divdf3+0x5f4>
+ 800e02c:	94800054 	ori	r18,r18,1
+ 800e030:	003ee306 	br	800dbc0 <__divdf3+0x168>
+ 800e034:	00800434 	movhi	r2,16
+ 800e038:	b1000234 	orhi	r4,r22,8
+ 800e03c:	10bfffc4 	addi	r2,r2,-1
+ 800e040:	2088703a 	and	r4,r4,r2
+ 800e044:	a039883a 	mov	fp,r20
+ 800e048:	003f5506 	br	800dda0 <__divdf3+0x348>
+ 800e04c:	183edc26 	beq	r3,zero,800dbc0 <__divdf3+0x168>
+ 800e050:	8885883a 	add	r2,r17,r2
+ 800e054:	913fffc4 	addi	r4,r18,-1
+ 800e058:	14406036 	bltu	r2,r17,800e1dc <__divdf3+0x784>
+ 800e05c:	11c07d36 	bltu	r2,r7,800e254 <__divdf3+0x7fc>
+ 800e060:	11c0a326 	beq	r2,r7,800e2f0 <__divdf3+0x898>
+ 800e064:	2025883a 	mov	r18,r4
+ 800e068:	003ff006 	br	800e02c <__divdf3+0x5d4>
+ 800e06c:	84bfa22e 	bgeu	r16,r18,800def8 <__divdf3+0x4a0>
+ 800e070:	d8c00017 	ldw	r3,0(sp)
+ 800e074:	80e1883a 	add	r16,r16,r3
+ 800e078:	80c7803a 	cmpltu	r3,r16,r3
+ 800e07c:	1c47883a 	add	r3,r3,r17
+ 800e080:	10c5883a 	add	r2,r2,r3
+ 800e084:	b0ffffc4 	addi	r3,r22,-1
+ 800e088:	8880482e 	bgeu	r17,r2,800e1ac <__divdf3+0x754>
+ 800e08c:	14c06a36 	bltu	r2,r19,800e238 <__divdf3+0x7e0>
+ 800e090:	98806826 	beq	r19,r2,800e234 <__divdf3+0x7dc>
+ 800e094:	182d883a 	mov	r22,r3
+ 800e098:	003f9706 	br	800def8 <__divdf3+0x4a0>
+ 800e09c:	923f4f36 	bltu	r18,r8,800dddc <__divdf3+0x384>
+ 800e0a0:	b00a97fa 	slli	r5,r22,31
+ 800e0a4:	9004d07a 	srli	r2,r18,1
+ 800e0a8:	902097fa 	slli	r16,r18,31
+ 800e0ac:	b006d07a 	srli	r3,r22,1
+ 800e0b0:	28a4b03a 	or	r18,r5,r2
+ 800e0b4:	003f4c06 	br	800dde8 <__divdf3+0x390>
+ 800e0b8:	800f7900 	call	800f790 <__clzsi2>
+ 800e0bc:	11000544 	addi	r4,r2,21
+ 800e0c0:	21400748 	cmpgei	r5,r4,29
+ 800e0c4:	15400804 	addi	r21,r2,32
+ 800e0c8:	d9800017 	ldw	r6,0(sp)
+ 800e0cc:	d9c00117 	ldw	r7,4(sp)
+ 800e0d0:	283f0a26 	beq	r5,zero,800dcfc <__divdf3+0x2a4>
+ 800e0d4:	113ffe04 	addi	r4,r2,-8
+ 800e0d8:	912c983a 	sll	r22,r18,r4
+ 800e0dc:	0025883a 	mov	r18,zero
+ 800e0e0:	003f0d06 	br	800dd18 <__divdf3+0x2c0>
+ 800e0e4:	3009883a 	mov	r4,r6
+ 800e0e8:	d9c00115 	stw	r7,4(sp)
+ 800e0ec:	d9800015 	stw	r6,0(sp)
+ 800e0f0:	800f7900 	call	800f790 <__clzsi2>
+ 800e0f4:	11400544 	addi	r5,r2,21
+ 800e0f8:	28c00748 	cmpgei	r3,r5,29
+ 800e0fc:	1009883a 	mov	r4,r2
+ 800e100:	d9800017 	ldw	r6,0(sp)
+ 800e104:	10800804 	addi	r2,r2,32
+ 800e108:	d9c00117 	ldw	r7,4(sp)
+ 800e10c:	183ee426 	beq	r3,zero,800dca0 <__divdf3+0x248>
+ 800e110:	213ffe04 	addi	r4,r4,-8
+ 800e114:	3126983a 	sll	r19,r6,r4
+ 800e118:	0011883a 	mov	r8,zero
+ 800e11c:	003ee706 	br	800dcbc <__divdf3+0x264>
+ 800e120:	04bfffc4 	movi	r18,-1
+ 800e124:	01000044 	movi	r4,1
+ 800e128:	2409c83a 	sub	r4,r4,r16
+ 800e12c:	20800e48 	cmpgei	r2,r4,57
+ 800e130:	103eb61e 	bne	r2,zero,800dc0c <__divdf3+0x1b4>
+ 800e134:	20800808 	cmpgei	r2,r4,32
+ 800e138:	10004e1e 	bne	r2,zero,800e274 <__divdf3+0x81c>
+ 800e13c:	a8810784 	addi	r2,r21,1054
+ 800e140:	b086983a 	sll	r3,r22,r2
+ 800e144:	910ad83a 	srl	r5,r18,r4
+ 800e148:	9084983a 	sll	r2,r18,r2
+ 800e14c:	b108d83a 	srl	r4,r22,r4
+ 800e150:	1964b03a 	or	r18,r3,r5
+ 800e154:	1004c03a 	cmpne	r2,r2,zero
+ 800e158:	90a4b03a 	or	r18,r18,r2
+ 800e15c:	908001cc 	andi	r2,r18,7
+ 800e160:	10000726 	beq	r2,zero,800e180 <__divdf3+0x728>
+ 800e164:	908003cc 	andi	r2,r18,15
+ 800e168:	10800120 	cmpeqi	r2,r2,4
+ 800e16c:	1000041e 	bne	r2,zero,800e180 <__divdf3+0x728>
+ 800e170:	90800104 	addi	r2,r18,4
+ 800e174:	14a5803a 	cmpltu	r18,r2,r18
+ 800e178:	2489883a 	add	r4,r4,r18
+ 800e17c:	1025883a 	mov	r18,r2
+ 800e180:	2080202c 	andhi	r2,r4,128
+ 800e184:	10005026 	beq	r2,zero,800e2c8 <__divdf3+0x870>
+ 800e188:	00800044 	movi	r2,1
+ 800e18c:	0009883a 	mov	r4,zero
+ 800e190:	0025883a 	mov	r18,zero
+ 800e194:	003ea006 	br	800dc18 <__divdf3+0x1c0>
+ 800e198:	b839883a 	mov	fp,r23
+ 800e19c:	0081ffc4 	movi	r2,2047
+ 800e1a0:	0009883a 	mov	r4,zero
+ 800e1a4:	0025883a 	mov	r18,zero
+ 800e1a8:	003e9b06 	br	800dc18 <__divdf3+0x1c0>
+ 800e1ac:	88bfb91e 	bne	r17,r2,800e094 <__divdf3+0x63c>
+ 800e1b0:	d9000017 	ldw	r4,0(sp)
+ 800e1b4:	813fb736 	bltu	r16,r4,800e094 <__divdf3+0x63c>
+ 800e1b8:	003fb406 	br	800e08c <__divdf3+0x634>
+ 800e1bc:	117f342e 	bgeu	r2,r5,800de90 <__divdf3+0x438>
+ 800e1c0:	18ffff84 	addi	r3,r3,-2
+ 800e1c4:	1445883a 	add	r2,r2,r17
+ 800e1c8:	003f3206 	br	800de94 <__divdf3+0x43c>
+ 800e1cc:	14ff1e2e 	bgeu	r2,r19,800de48 <__divdf3+0x3f0>
+ 800e1d0:	b5bfff84 	addi	r22,r22,-2
+ 800e1d4:	1445883a 	add	r2,r2,r17
+ 800e1d8:	003f1c06 	br	800de4c <__divdf3+0x3f4>
+ 800e1dc:	2025883a 	mov	r18,r4
+ 800e1e0:	11ff921e 	bne	r2,r7,800e02c <__divdf3+0x5d4>
+ 800e1e4:	d8800017 	ldw	r2,0(sp)
+ 800e1e8:	10ff901e 	bne	r2,r3,800e02c <__divdf3+0x5d4>
+ 800e1ec:	003e7406 	br	800dbc0 <__divdf3+0x168>
+ 800e1f0:	043fcb0e 	bge	zero,r16,800e120 <__divdf3+0x6c8>
+ 800e1f4:	000b883a 	mov	r5,zero
+ 800e1f8:	04800044 	movi	r18,1
+ 800e1fc:	b4ad883a 	add	r22,r22,r18
+ 800e200:	003e7306 	br	800dbd0 <__divdf3+0x178>
+ 800e204:	2013883a 	mov	r9,r4
+ 800e208:	003f7206 	br	800dfd4 <__divdf3+0x57c>
+ 800e20c:	2007883a 	mov	r3,r4
+ 800e210:	003f5606 	br	800df6c <__divdf3+0x514>
+ 800e214:	908003cc 	andi	r2,r18,15
+ 800e218:	10800118 	cmpnei	r2,r2,4
+ 800e21c:	103e6b26 	beq	r2,zero,800dbcc <__divdf3+0x174>
+ 800e220:	91400104 	addi	r5,r18,4
+ 800e224:	00bffec4 	movi	r2,-5
+ 800e228:	14a5803a 	cmpltu	r18,r2,r18
+ 800e22c:	280ad0fa 	srli	r5,r5,3
+ 800e230:	003ff206 	br	800e1fc <__divdf3+0x7a4>
+ 800e234:	84bf972e 	bgeu	r16,r18,800e094 <__divdf3+0x63c>
+ 800e238:	d8c00017 	ldw	r3,0(sp)
+ 800e23c:	b5bfff84 	addi	r22,r22,-2
+ 800e240:	80e1883a 	add	r16,r16,r3
+ 800e244:	80c7803a 	cmpltu	r3,r16,r3
+ 800e248:	1c47883a 	add	r3,r3,r17
+ 800e24c:	10c5883a 	add	r2,r2,r3
+ 800e250:	003f2906 	br	800def8 <__divdf3+0x4a0>
+ 800e254:	d9400017 	ldw	r5,0(sp)
+ 800e258:	94bfff84 	addi	r18,r18,-2
+ 800e25c:	2949883a 	add	r4,r5,r5
+ 800e260:	214b803a 	cmpltu	r5,r4,r5
+ 800e264:	2c4d883a 	add	r6,r5,r17
+ 800e268:	1185883a 	add	r2,r2,r6
+ 800e26c:	d9000015 	stw	r4,0(sp)
+ 800e270:	003fdb06 	br	800e1e0 <__divdf3+0x788>
+ 800e274:	00bff844 	movi	r2,-31
+ 800e278:	1421c83a 	sub	r16,r2,r16
+ 800e27c:	21000820 	cmpeqi	r4,r4,32
+ 800e280:	b420d83a 	srl	r16,r22,r16
+ 800e284:	2000031e 	bne	r4,zero,800e294 <__divdf3+0x83c>
+ 800e288:	a8810f84 	addi	r2,r21,1086
+ 800e28c:	b088983a 	sll	r4,r22,r2
+ 800e290:	9124b03a 	or	r18,r18,r4
+ 800e294:	9024c03a 	cmpne	r18,r18,zero
+ 800e298:	9424b03a 	or	r18,r18,r16
+ 800e29c:	914001cc 	andi	r5,r18,7
+ 800e2a0:	2800051e 	bne	r5,zero,800e2b8 <__divdf3+0x860>
+ 800e2a4:	0009883a 	mov	r4,zero
+ 800e2a8:	9024d0fa 	srli	r18,r18,3
+ 800e2ac:	0005883a 	mov	r2,zero
+ 800e2b0:	9164b03a 	or	r18,r18,r5
+ 800e2b4:	003e5806 	br	800dc18 <__divdf3+0x1c0>
+ 800e2b8:	908003cc 	andi	r2,r18,15
+ 800e2bc:	10800118 	cmpnei	r2,r2,4
+ 800e2c0:	0009883a 	mov	r4,zero
+ 800e2c4:	103faa1e 	bne	r2,zero,800e170 <__divdf3+0x718>
+ 800e2c8:	2004927a 	slli	r2,r4,9
+ 800e2cc:	200a977a 	slli	r5,r4,29
+ 800e2d0:	1008d33a 	srli	r4,r2,12
+ 800e2d4:	003ff406 	br	800e2a8 <__divdf3+0x850>
+ 800e2d8:	00800434 	movhi	r2,16
+ 800e2dc:	b1000234 	orhi	r4,r22,8
+ 800e2e0:	10bfffc4 	addi	r2,r2,-1
+ 800e2e4:	2088703a 	and	r4,r4,r2
+ 800e2e8:	b839883a 	mov	fp,r23
+ 800e2ec:	003eac06 	br	800dda0 <__divdf3+0x348>
+ 800e2f0:	d9400017 	ldw	r5,0(sp)
+ 800e2f4:	28ffd736 	bltu	r5,r3,800e254 <__divdf3+0x7fc>
+ 800e2f8:	2025883a 	mov	r18,r4
+ 800e2fc:	003fb906 	br	800e1e4 <__divdf3+0x78c>
+
+0800e300 <__eqdf2>:
+ 800e300:	2810d53a 	srli	r8,r5,20
+ 800e304:	3806d53a 	srli	r3,r7,20
+ 800e308:	00800434 	movhi	r2,16
+ 800e30c:	4201ffcc 	andi	r8,r8,2047
+ 800e310:	10bfffc4 	addi	r2,r2,-1
+ 800e314:	4281ffd8 	cmpnei	r10,r8,2047
+ 800e318:	2892703a 	and	r9,r5,r2
+ 800e31c:	18c1ffcc 	andi	r3,r3,2047
+ 800e320:	3884703a 	and	r2,r7,r2
+ 800e324:	280ad7fa 	srli	r5,r5,31
+ 800e328:	380ed7fa 	srli	r7,r7,31
+ 800e32c:	50000626 	beq	r10,zero,800e348 <__eqdf2+0x48>
+ 800e330:	1a81ffe0 	cmpeqi	r10,r3,2047
+ 800e334:	5000021e 	bne	r10,zero,800e340 <__eqdf2+0x40>
+ 800e338:	40c0011e 	bne	r8,r3,800e340 <__eqdf2+0x40>
+ 800e33c:	48800826 	beq	r9,r2,800e360 <__eqdf2+0x60>
+ 800e340:	00800044 	movi	r2,1
+ 800e344:	f800283a 	ret
+ 800e348:	4914b03a 	or	r10,r9,r4
+ 800e34c:	503ffc1e 	bne	r10,zero,800e340 <__eqdf2+0x40>
+ 800e350:	18c1ffd8 	cmpnei	r3,r3,2047
+ 800e354:	183ffa1e 	bne	r3,zero,800e340 <__eqdf2+0x40>
+ 800e358:	1184b03a 	or	r2,r2,r6
+ 800e35c:	103ff81e 	bne	r2,zero,800e340 <__eqdf2+0x40>
+ 800e360:	21bff71e 	bne	r4,r6,800e340 <__eqdf2+0x40>
+ 800e364:	29c00426 	beq	r5,r7,800e378 <__eqdf2+0x78>
+ 800e368:	403ff51e 	bne	r8,zero,800e340 <__eqdf2+0x40>
+ 800e36c:	4904b03a 	or	r2,r9,r4
+ 800e370:	1004c03a 	cmpne	r2,r2,zero
+ 800e374:	f800283a 	ret
+ 800e378:	0005883a 	mov	r2,zero
+ 800e37c:	f800283a 	ret
+
+0800e380 <__gedf2>:
+ 800e380:	2810d53a 	srli	r8,r5,20
+ 800e384:	3812d53a 	srli	r9,r7,20
+ 800e388:	00800434 	movhi	r2,16
+ 800e38c:	4201ffcc 	andi	r8,r8,2047
+ 800e390:	10bfffc4 	addi	r2,r2,-1
+ 800e394:	4281ffd8 	cmpnei	r10,r8,2047
+ 800e398:	2896703a 	and	r11,r5,r2
+ 800e39c:	3886703a 	and	r3,r7,r2
+ 800e3a0:	280ad7fa 	srli	r5,r5,31
+ 800e3a4:	4a41ffcc 	andi	r9,r9,2047
+ 800e3a8:	3804d7fa 	srli	r2,r7,31
+ 800e3ac:	50000b26 	beq	r10,zero,800e3dc <__gedf2+0x5c>
+ 800e3b0:	49c1ffd8 	cmpnei	r7,r9,2047
+ 800e3b4:	38000d26 	beq	r7,zero,800e3ec <__gedf2+0x6c>
+ 800e3b8:	4000191e 	bne	r8,zero,800e420 <__gedf2+0xa0>
+ 800e3bc:	5914b03a 	or	r10,r11,r4
+ 800e3c0:	500f003a 	cmpeq	r7,r10,zero
+ 800e3c4:	4800131e 	bne	r9,zero,800e414 <__gedf2+0x94>
+ 800e3c8:	1998b03a 	or	r12,r3,r6
+ 800e3cc:	6000111e 	bne	r12,zero,800e414 <__gedf2+0x94>
+ 800e3d0:	50000a1e 	bne	r10,zero,800e3fc <__gedf2+0x7c>
+ 800e3d4:	0005883a 	mov	r2,zero
+ 800e3d8:	f800283a 	ret
+ 800e3dc:	590eb03a 	or	r7,r11,r4
+ 800e3e0:	38001e1e 	bne	r7,zero,800e45c <__gedf2+0xdc>
+ 800e3e4:	49c1ffe0 	cmpeqi	r7,r9,2047
+ 800e3e8:	38000d26 	beq	r7,zero,800e420 <__gedf2+0xa0>
+ 800e3ec:	198eb03a 	or	r7,r3,r6
+ 800e3f0:	38001a1e 	bne	r7,zero,800e45c <__gedf2+0xdc>
+ 800e3f4:	40000526 	beq	r8,zero,800e40c <__gedf2+0x8c>
+ 800e3f8:	28800d26 	beq	r5,r2,800e430 <__gedf2+0xb0>
+ 800e3fc:	00800044 	movi	r2,1
+ 800e400:	28000626 	beq	r5,zero,800e41c <__gedf2+0x9c>
+ 800e404:	00bfffc4 	movi	r2,-1
+ 800e408:	f800283a 	ret
+ 800e40c:	590eb03a 	or	r7,r11,r4
+ 800e410:	380f003a 	cmpeq	r7,r7,zero
+ 800e414:	383ff826 	beq	r7,zero,800e3f8 <__gedf2+0x78>
+ 800e418:	103ffa26 	beq	r2,zero,800e404 <__gedf2+0x84>
+ 800e41c:	f800283a 	ret
+ 800e420:	483ff51e 	bne	r9,zero,800e3f8 <__gedf2+0x78>
+ 800e424:	198eb03a 	or	r7,r3,r6
+ 800e428:	383ff31e 	bne	r7,zero,800e3f8 <__gedf2+0x78>
+ 800e42c:	003ff306 	br	800e3fc <__gedf2+0x7c>
+ 800e430:	4a000716 	blt	r9,r8,800e450 <__gedf2+0xd0>
+ 800e434:	427ff816 	blt	r8,r9,800e418 <__gedf2+0x98>
+ 800e438:	1afff036 	bltu	r3,r11,800e3fc <__gedf2+0x7c>
+ 800e43c:	58c00926 	beq	r11,r3,800e464 <__gedf2+0xe4>
+ 800e440:	58ffe42e 	bgeu	r11,r3,800e3d4 <__gedf2+0x54>
+ 800e444:	283fef26 	beq	r5,zero,800e404 <__gedf2+0x84>
+ 800e448:	2805883a 	mov	r2,r5
+ 800e44c:	f800283a 	ret
+ 800e450:	103fec1e 	bne	r2,zero,800e404 <__gedf2+0x84>
+ 800e454:	00800044 	movi	r2,1
+ 800e458:	f800283a 	ret
+ 800e45c:	00bfff84 	movi	r2,-2
+ 800e460:	f800283a 	ret
+ 800e464:	313fe536 	bltu	r6,r4,800e3fc <__gedf2+0x7c>
+ 800e468:	21bfda2e 	bgeu	r4,r6,800e3d4 <__gedf2+0x54>
+ 800e46c:	003ff506 	br	800e444 <__gedf2+0xc4>
+
+0800e470 <__ledf2>:
+ 800e470:	2810d53a 	srli	r8,r5,20
+ 800e474:	3812d53a 	srli	r9,r7,20
+ 800e478:	00800434 	movhi	r2,16
+ 800e47c:	4201ffcc 	andi	r8,r8,2047
+ 800e480:	10bfffc4 	addi	r2,r2,-1
+ 800e484:	4281ffd8 	cmpnei	r10,r8,2047
+ 800e488:	2896703a 	and	r11,r5,r2
+ 800e48c:	3886703a 	and	r3,r7,r2
+ 800e490:	280ad7fa 	srli	r5,r5,31
+ 800e494:	4a41ffcc 	andi	r9,r9,2047
+ 800e498:	3804d7fa 	srli	r2,r7,31
+ 800e49c:	50000b26 	beq	r10,zero,800e4cc <__ledf2+0x5c>
+ 800e4a0:	49c1ffd8 	cmpnei	r7,r9,2047
+ 800e4a4:	38000d26 	beq	r7,zero,800e4dc <__ledf2+0x6c>
+ 800e4a8:	40001b1e 	bne	r8,zero,800e518 <__ledf2+0xa8>
+ 800e4ac:	5914b03a 	or	r10,r11,r4
+ 800e4b0:	500f003a 	cmpeq	r7,r10,zero
+ 800e4b4:	48000e1e 	bne	r9,zero,800e4f0 <__ledf2+0x80>
+ 800e4b8:	1998b03a 	or	r12,r3,r6
+ 800e4bc:	60000c1e 	bne	r12,zero,800e4f0 <__ledf2+0x80>
+ 800e4c0:	50000d1e 	bne	r10,zero,800e4f8 <__ledf2+0x88>
+ 800e4c4:	0005883a 	mov	r2,zero
+ 800e4c8:	f800283a 	ret
+ 800e4cc:	590eb03a 	or	r7,r11,r4
+ 800e4d0:	38000d1e 	bne	r7,zero,800e508 <__ledf2+0x98>
+ 800e4d4:	49c1ffe0 	cmpeqi	r7,r9,2047
+ 800e4d8:	38000f26 	beq	r7,zero,800e518 <__ledf2+0xa8>
+ 800e4dc:	198eb03a 	or	r7,r3,r6
+ 800e4e0:	3800091e 	bne	r7,zero,800e508 <__ledf2+0x98>
+ 800e4e4:	4000031e 	bne	r8,zero,800e4f4 <__ledf2+0x84>
+ 800e4e8:	590eb03a 	or	r7,r11,r4
+ 800e4ec:	380f003a 	cmpeq	r7,r7,zero
+ 800e4f0:	3800071e 	bne	r7,zero,800e510 <__ledf2+0xa0>
+ 800e4f4:	28800c26 	beq	r5,r2,800e528 <__ledf2+0xb8>
+ 800e4f8:	00800044 	movi	r2,1
+ 800e4fc:	28000526 	beq	r5,zero,800e514 <__ledf2+0xa4>
+ 800e500:	00bfffc4 	movi	r2,-1
+ 800e504:	f800283a 	ret
+ 800e508:	00800084 	movi	r2,2
+ 800e50c:	f800283a 	ret
+ 800e510:	103ffb26 	beq	r2,zero,800e500 <__ledf2+0x90>
+ 800e514:	f800283a 	ret
+ 800e518:	483ff61e 	bne	r9,zero,800e4f4 <__ledf2+0x84>
+ 800e51c:	198eb03a 	or	r7,r3,r6
+ 800e520:	383ff41e 	bne	r7,zero,800e4f4 <__ledf2+0x84>
+ 800e524:	003ff406 	br	800e4f8 <__ledf2+0x88>
+ 800e528:	4a00030e 	bge	r9,r8,800e538 <__ledf2+0xc8>
+ 800e52c:	103ff41e 	bne	r2,zero,800e500 <__ledf2+0x90>
+ 800e530:	00800044 	movi	r2,1
+ 800e534:	f800283a 	ret
+ 800e538:	427ff516 	blt	r8,r9,800e510 <__ledf2+0xa0>
+ 800e53c:	1affee36 	bltu	r3,r11,800e4f8 <__ledf2+0x88>
+ 800e540:	58c00426 	beq	r11,r3,800e554 <__ledf2+0xe4>
+ 800e544:	58ffdf2e 	bgeu	r11,r3,800e4c4 <__ledf2+0x54>
+ 800e548:	283fed26 	beq	r5,zero,800e500 <__ledf2+0x90>
+ 800e54c:	2805883a 	mov	r2,r5
+ 800e550:	f800283a 	ret
+ 800e554:	313fe836 	bltu	r6,r4,800e4f8 <__ledf2+0x88>
+ 800e558:	21bfda2e 	bgeu	r4,r6,800e4c4 <__ledf2+0x54>
+ 800e55c:	003ffa06 	br	800e548 <__ledf2+0xd8>
+
+0800e560 <__muldf3>:
+ 800e560:	2806d53a 	srli	r3,r5,20
+ 800e564:	defff504 	addi	sp,sp,-44
+ 800e568:	dc000215 	stw	r16,8(sp)
+ 800e56c:	04000434 	movhi	r16,16
+ 800e570:	dd000615 	stw	r20,24(sp)
+ 800e574:	dc800415 	stw	r18,16(sp)
+ 800e578:	843fffc4 	addi	r16,r16,-1
+ 800e57c:	dfc00a15 	stw	ra,40(sp)
+ 800e580:	ddc00915 	stw	r23,36(sp)
+ 800e584:	dd800815 	stw	r22,32(sp)
+ 800e588:	dd400715 	stw	r21,28(sp)
+ 800e58c:	dcc00515 	stw	r19,20(sp)
+ 800e590:	dc400315 	stw	r17,12(sp)
+ 800e594:	18c1ffcc 	andi	r3,r3,2047
+ 800e598:	2025883a 	mov	r18,r4
+ 800e59c:	2c20703a 	and	r16,r5,r16
+ 800e5a0:	2828d7fa 	srli	r20,r5,31
+ 800e5a4:	18005c26 	beq	r3,zero,800e718 <__muldf3+0x1b8>
+ 800e5a8:	1881ffe0 	cmpeqi	r2,r3,2047
+ 800e5ac:	1000711e 	bne	r2,zero,800e774 <__muldf3+0x214>
+ 800e5b0:	800490fa 	slli	r2,r16,3
+ 800e5b4:	2020d77a 	srli	r16,r4,29
+ 800e5b8:	202290fa 	slli	r17,r4,3
+ 800e5bc:	1cff0044 	addi	r19,r3,-1023
+ 800e5c0:	80a0b03a 	or	r16,r16,r2
+ 800e5c4:	84002034 	orhi	r16,r16,128
+ 800e5c8:	002d883a 	mov	r22,zero
+ 800e5cc:	002f883a 	mov	r23,zero
+ 800e5d0:	3806d53a 	srli	r3,r7,20
+ 800e5d4:	01000434 	movhi	r4,16
+ 800e5d8:	213fffc4 	addi	r4,r4,-1
+ 800e5dc:	18c1ffcc 	andi	r3,r3,2047
+ 800e5e0:	3924703a 	and	r18,r7,r4
+ 800e5e4:	382ad7fa 	srli	r21,r7,31
+ 800e5e8:	18006926 	beq	r3,zero,800e790 <__muldf3+0x230>
+ 800e5ec:	1881ffe0 	cmpeqi	r2,r3,2047
+ 800e5f0:	1000211e 	bne	r2,zero,800e678 <__muldf3+0x118>
+ 800e5f4:	900890fa 	slli	r4,r18,3
+ 800e5f8:	300ad77a 	srli	r5,r6,29
+ 800e5fc:	301090fa 	slli	r8,r6,3
+ 800e600:	18ff0044 	addi	r3,r3,-1023
+ 800e604:	2908b03a 	or	r4,r5,r4
+ 800e608:	98e7883a 	add	r19,r19,r3
+ 800e60c:	24802034 	orhi	r18,r4,128
+ 800e610:	0007883a 	mov	r3,zero
+ 800e614:	b1000428 	cmpgeui	r4,r22,16
+ 800e618:	a54cf03a 	xor	r6,r20,r21
+ 800e61c:	99400044 	addi	r5,r19,1
+ 800e620:	2000981e 	bne	r4,zero,800e884 <__muldf3+0x324>
+ 800e624:	b00890ba 	slli	r4,r22,2
+ 800e628:	00820074 	movhi	r2,2049
+ 800e62c:	2085883a 	add	r2,r4,r2
+ 800e630:	10b98e17 	ldw	r2,-6600(r2)
+ 800e634:	1000683a 	jmp	r2
+ 800e638:	0800e884 	addi	zero,at,930
+ 800e63c:	0800e698 	cmpnei	zero,at,922
+ 800e640:	0800e698 	cmpnei	zero,at,922
+ 800e644:	0800e694 	ori	zero,at,922
+ 800e648:	0800e6a4 	muli	zero,at,922
+ 800e64c:	0800e6a4 	muli	zero,at,922
+ 800e650:	0800e840 	call	800e84 <OSCtxSw_SWITCH_PC+0x800e44>
+ 800e654:	0800e694 	ori	zero,at,922
+ 800e658:	0800e6a4 	muli	zero,at,922
+ 800e65c:	0800e840 	call	800e84 <OSCtxSw_SWITCH_PC+0x800e44>
+ 800e660:	0800e6a4 	muli	zero,at,922
+ 800e664:	0800e694 	ori	zero,at,922
+ 800e668:	0800e838 	rdprs	zero,at,928
+ 800e66c:	0800e838 	rdprs	zero,at,928
+ 800e670:	0800e838 	rdprs	zero,at,928
+ 800e674:	0800e858 	cmpnei	zero,at,929
+ 800e678:	3490b03a 	or	r8,r6,r18
+ 800e67c:	9cc1ffc4 	addi	r19,r19,2047
+ 800e680:	4000691e 	bne	r8,zero,800e828 <__muldf3+0x2c8>
+ 800e684:	b5800094 	ori	r22,r22,2
+ 800e688:	0025883a 	mov	r18,zero
+ 800e68c:	00c00084 	movi	r3,2
+ 800e690:	003fe006 	br	800e614 <__muldf3+0xb4>
+ 800e694:	a80d883a 	mov	r6,r21
+ 800e698:	9021883a 	mov	r16,r18
+ 800e69c:	4023883a 	mov	r17,r8
+ 800e6a0:	182f883a 	mov	r23,r3
+ 800e6a4:	b88000a0 	cmpeqi	r2,r23,2
+ 800e6a8:	10004d1e 	bne	r2,zero,800e7e0 <__muldf3+0x280>
+ 800e6ac:	b88000e0 	cmpeqi	r2,r23,3
+ 800e6b0:	1001491e 	bne	r2,zero,800ebd8 <__muldf3+0x678>
+ 800e6b4:	b8800060 	cmpeqi	r2,r23,1
+ 800e6b8:	1000d826 	beq	r2,zero,800ea1c <__muldf3+0x4bc>
+ 800e6bc:	0007883a 	mov	r3,zero
+ 800e6c0:	0021883a 	mov	r16,zero
+ 800e6c4:	0023883a 	mov	r17,zero
+ 800e6c8:	30803fcc 	andi	r2,r6,255
+ 800e6cc:	01000434 	movhi	r4,16
+ 800e6d0:	1806953a 	slli	r3,r3,20
+ 800e6d4:	213fffc4 	addi	r4,r4,-1
+ 800e6d8:	100497fa 	slli	r2,r2,31
+ 800e6dc:	8120703a 	and	r16,r16,r4
+ 800e6e0:	80c6b03a 	or	r3,r16,r3
+ 800e6e4:	1886b03a 	or	r3,r3,r2
+ 800e6e8:	8805883a 	mov	r2,r17
+ 800e6ec:	dfc00a17 	ldw	ra,40(sp)
+ 800e6f0:	ddc00917 	ldw	r23,36(sp)
+ 800e6f4:	dd800817 	ldw	r22,32(sp)
+ 800e6f8:	dd400717 	ldw	r21,28(sp)
+ 800e6fc:	dd000617 	ldw	r20,24(sp)
+ 800e700:	dcc00517 	ldw	r19,20(sp)
+ 800e704:	dc800417 	ldw	r18,16(sp)
+ 800e708:	dc400317 	ldw	r17,12(sp)
+ 800e70c:	dc000217 	ldw	r16,8(sp)
+ 800e710:	dec00b04 	addi	sp,sp,44
+ 800e714:	f800283a 	ret
+ 800e718:	8122b03a 	or	r17,r16,r4
+ 800e71c:	88003d26 	beq	r17,zero,800e814 <__muldf3+0x2b4>
+ 800e720:	d9c00115 	stw	r7,4(sp)
+ 800e724:	d9800015 	stw	r6,0(sp)
+ 800e728:	8000e826 	beq	r16,zero,800eacc <__muldf3+0x56c>
+ 800e72c:	8009883a 	mov	r4,r16
+ 800e730:	800f7900 	call	800f790 <__clzsi2>
+ 800e734:	d9800017 	ldw	r6,0(sp)
+ 800e738:	d9c00117 	ldw	r7,4(sp)
+ 800e73c:	1007883a 	mov	r3,r2
+ 800e740:	117ffd44 	addi	r5,r2,-11
+ 800e744:	01000744 	movi	r4,29
+ 800e748:	1c7ffe04 	addi	r17,r3,-8
+ 800e74c:	2149c83a 	sub	r4,r4,r5
+ 800e750:	8460983a 	sll	r16,r16,r17
+ 800e754:	9108d83a 	srl	r4,r18,r4
+ 800e758:	9462983a 	sll	r17,r18,r17
+ 800e75c:	2420b03a 	or	r16,r4,r16
+ 800e760:	04ff0344 	movi	r19,-1011
+ 800e764:	98e7c83a 	sub	r19,r19,r3
+ 800e768:	002d883a 	mov	r22,zero
+ 800e76c:	002f883a 	mov	r23,zero
+ 800e770:	003f9706 	br	800e5d0 <__muldf3+0x70>
+ 800e774:	8122b03a 	or	r17,r16,r4
+ 800e778:	8800211e 	bne	r17,zero,800e800 <__muldf3+0x2a0>
+ 800e77c:	0021883a 	mov	r16,zero
+ 800e780:	05800204 	movi	r22,8
+ 800e784:	04c1ffc4 	movi	r19,2047
+ 800e788:	05c00084 	movi	r23,2
+ 800e78c:	003f9006 	br	800e5d0 <__muldf3+0x70>
+ 800e790:	3490b03a 	or	r8,r6,r18
+ 800e794:	40001626 	beq	r8,zero,800e7f0 <__muldf3+0x290>
+ 800e798:	9000c026 	beq	r18,zero,800ea9c <__muldf3+0x53c>
+ 800e79c:	9009883a 	mov	r4,r18
+ 800e7a0:	d9800015 	stw	r6,0(sp)
+ 800e7a4:	800f7900 	call	800f790 <__clzsi2>
+ 800e7a8:	d9800017 	ldw	r6,0(sp)
+ 800e7ac:	1007883a 	mov	r3,r2
+ 800e7b0:	113ffd44 	addi	r4,r2,-11
+ 800e7b4:	01400744 	movi	r5,29
+ 800e7b8:	1a3ffe04 	addi	r8,r3,-8
+ 800e7bc:	290bc83a 	sub	r5,r5,r4
+ 800e7c0:	314ad83a 	srl	r5,r6,r5
+ 800e7c4:	9208983a 	sll	r4,r18,r8
+ 800e7c8:	3210983a 	sll	r8,r6,r8
+ 800e7cc:	2924b03a 	or	r18,r5,r4
+ 800e7d0:	98c7c83a 	sub	r3,r19,r3
+ 800e7d4:	1cff0344 	addi	r19,r3,-1011
+ 800e7d8:	0007883a 	mov	r3,zero
+ 800e7dc:	003f8d06 	br	800e614 <__muldf3+0xb4>
+ 800e7e0:	00c1ffc4 	movi	r3,2047
+ 800e7e4:	0021883a 	mov	r16,zero
+ 800e7e8:	0023883a 	mov	r17,zero
+ 800e7ec:	003fb606 	br	800e6c8 <__muldf3+0x168>
+ 800e7f0:	b5800054 	ori	r22,r22,1
+ 800e7f4:	0025883a 	mov	r18,zero
+ 800e7f8:	00c00044 	movi	r3,1
+ 800e7fc:	003f8506 	br	800e614 <__muldf3+0xb4>
+ 800e800:	2023883a 	mov	r17,r4
+ 800e804:	05800304 	movi	r22,12
+ 800e808:	04c1ffc4 	movi	r19,2047
+ 800e80c:	05c000c4 	movi	r23,3
+ 800e810:	003f6f06 	br	800e5d0 <__muldf3+0x70>
+ 800e814:	0021883a 	mov	r16,zero
+ 800e818:	05800104 	movi	r22,4
+ 800e81c:	0027883a 	mov	r19,zero
+ 800e820:	05c00044 	movi	r23,1
+ 800e824:	003f6a06 	br	800e5d0 <__muldf3+0x70>
+ 800e828:	b58000d4 	ori	r22,r22,3
+ 800e82c:	3011883a 	mov	r8,r6
+ 800e830:	00c000c4 	movi	r3,3
+ 800e834:	003f7706 	br	800e614 <__muldf3+0xb4>
+ 800e838:	a00d883a 	mov	r6,r20
+ 800e83c:	003f9906 	br	800e6a4 <__muldf3+0x144>
+ 800e840:	04000434 	movhi	r16,16
+ 800e844:	000d883a 	mov	r6,zero
+ 800e848:	843fffc4 	addi	r16,r16,-1
+ 800e84c:	047fffc4 	movi	r17,-1
+ 800e850:	00c1ffc4 	movi	r3,2047
+ 800e854:	003f9c06 	br	800e6c8 <__muldf3+0x168>
+ 800e858:	8080022c 	andhi	r2,r16,8
+ 800e85c:	10008926 	beq	r2,zero,800ea84 <__muldf3+0x524>
+ 800e860:	9080022c 	andhi	r2,r18,8
+ 800e864:	1000871e 	bne	r2,zero,800ea84 <__muldf3+0x524>
+ 800e868:	00800434 	movhi	r2,16
+ 800e86c:	94000234 	orhi	r16,r18,8
+ 800e870:	10bfffc4 	addi	r2,r2,-1
+ 800e874:	80a0703a 	and	r16,r16,r2
+ 800e878:	a80d883a 	mov	r6,r21
+ 800e87c:	4023883a 	mov	r17,r8
+ 800e880:	003ff306 	br	800e850 <__muldf3+0x2f0>
+ 800e884:	8818d43a 	srli	r12,r17,16
+ 800e888:	4028d43a 	srli	r20,r8,16
+ 800e88c:	42ffffcc 	andi	r11,r8,65535
+ 800e890:	8c7fffcc 	andi	r17,r17,65535
+ 800e894:	5c47383a 	mul	r3,r11,r17
+ 800e898:	62c9383a 	mul	r4,r12,r11
+ 800e89c:	a445383a 	mul	r2,r20,r17
+ 800e8a0:	1810d43a 	srli	r8,r3,16
+ 800e8a4:	651d383a 	mul	r14,r12,r20
+ 800e8a8:	1105883a 	add	r2,r2,r4
+ 800e8ac:	4091883a 	add	r8,r8,r2
+ 800e8b0:	4100022e 	bgeu	r8,r4,800e8bc <__muldf3+0x35c>
+ 800e8b4:	00800074 	movhi	r2,1
+ 800e8b8:	709d883a 	add	r14,r14,r2
+ 800e8bc:	901ed43a 	srli	r15,r18,16
+ 800e8c0:	94bfffcc 	andi	r18,r18,65535
+ 800e8c4:	9449383a 	mul	r4,r18,r17
+ 800e8c8:	648f383a 	mul	r7,r12,r18
+ 800e8cc:	7c63383a 	mul	r17,r15,r17
+ 800e8d0:	201ad43a 	srli	r13,r4,16
+ 800e8d4:	4014943a 	slli	r10,r8,16
+ 800e8d8:	89e3883a 	add	r17,r17,r7
+ 800e8dc:	1a7fffcc 	andi	r9,r3,65535
+ 800e8e0:	6c5b883a 	add	r13,r13,r17
+ 800e8e4:	4006d43a 	srli	r3,r8,16
+ 800e8e8:	5253883a 	add	r9,r10,r9
+ 800e8ec:	63c5383a 	mul	r2,r12,r15
+ 800e8f0:	69c0022e 	bgeu	r13,r7,800e8fc <__muldf3+0x39c>
+ 800e8f4:	01c00074 	movhi	r7,1
+ 800e8f8:	11c5883a 	add	r2,r2,r7
+ 800e8fc:	802ad43a 	srli	r21,r16,16
+ 800e900:	823fffcc 	andi	r8,r16,65535
+ 800e904:	5a2d383a 	mul	r22,r11,r8
+ 800e908:	a20f383a 	mul	r7,r20,r8
+ 800e90c:	aad7383a 	mul	r11,r21,r11
+ 800e910:	6814943a 	slli	r10,r13,16
+ 800e914:	b018d43a 	srli	r12,r22,16
+ 800e918:	6822d43a 	srli	r17,r13,16
+ 800e91c:	213fffcc 	andi	r4,r4,65535
+ 800e920:	3acf883a 	add	r7,r7,r11
+ 800e924:	5115883a 	add	r10,r10,r4
+ 800e928:	61cf883a 	add	r7,r12,r7
+ 800e92c:	889b883a 	add	r13,r17,r2
+ 800e930:	1a87883a 	add	r3,r3,r10
+ 800e934:	a569383a 	mul	r20,r20,r21
+ 800e938:	3ac0022e 	bgeu	r7,r11,800e944 <__muldf3+0x3e4>
+ 800e93c:	00800074 	movhi	r2,1
+ 800e940:	a0a9883a 	add	r20,r20,r2
+ 800e944:	9217383a 	mul	r11,r18,r8
+ 800e948:	aca5383a 	mul	r18,r21,r18
+ 800e94c:	7a11383a 	mul	r8,r15,r8
+ 800e950:	5820d43a 	srli	r16,r11,16
+ 800e954:	3808d43a 	srli	r4,r7,16
+ 800e958:	380e943a 	slli	r7,r7,16
+ 800e95c:	4491883a 	add	r8,r8,r18
+ 800e960:	b5bfffcc 	andi	r22,r22,65535
+ 800e964:	8211883a 	add	r8,r16,r8
+ 800e968:	2529883a 	add	r20,r4,r20
+ 800e96c:	3d8f883a 	add	r7,r7,r22
+ 800e970:	7d59383a 	mul	r12,r15,r21
+ 800e974:	4480022e 	bgeu	r8,r18,800e980 <__muldf3+0x420>
+ 800e978:	00800074 	movhi	r2,1
+ 800e97c:	6099883a 	add	r12,r12,r2
+ 800e980:	4004943a 	slli	r2,r8,16
+ 800e984:	5affffcc 	andi	r11,r11,65535
+ 800e988:	1b87883a 	add	r3,r3,r14
+ 800e98c:	12c5883a 	add	r2,r2,r11
+ 800e990:	1a95803a 	cmpltu	r10,r3,r10
+ 800e994:	1345883a 	add	r2,r2,r13
+ 800e998:	19c7883a 	add	r3,r3,r7
+ 800e99c:	129d883a 	add	r14,r2,r10
+ 800e9a0:	19cf803a 	cmpltu	r7,r3,r7
+ 800e9a4:	7509883a 	add	r4,r14,r20
+ 800e9a8:	4010d43a 	srli	r8,r8,16
+ 800e9ac:	21d7883a 	add	r11,r4,r7
+ 800e9b0:	1345803a 	cmpltu	r2,r2,r13
+ 800e9b4:	72a1803a 	cmpltu	r16,r14,r10
+ 800e9b8:	1420b03a 	or	r16,r2,r16
+ 800e9bc:	2509803a 	cmpltu	r4,r4,r20
+ 800e9c0:	59cf803a 	cmpltu	r7,r11,r7
+ 800e9c4:	21ceb03a 	or	r7,r4,r7
+ 800e9c8:	8221883a 	add	r16,r16,r8
+ 800e9cc:	81e1883a 	add	r16,r16,r7
+ 800e9d0:	1822927a 	slli	r17,r3,9
+ 800e9d4:	8321883a 	add	r16,r16,r12
+ 800e9d8:	8020927a 	slli	r16,r16,9
+ 800e9dc:	5808d5fa 	srli	r4,r11,23
+ 800e9e0:	1806d5fa 	srli	r3,r3,23
+ 800e9e4:	8a62b03a 	or	r17,r17,r9
+ 800e9e8:	5804927a 	slli	r2,r11,9
+ 800e9ec:	8120b03a 	or	r16,r16,r4
+ 800e9f0:	8822c03a 	cmpne	r17,r17,zero
+ 800e9f4:	88e2b03a 	or	r17,r17,r3
+ 800e9f8:	80c0402c 	andhi	r3,r16,256
+ 800e9fc:	88a2b03a 	or	r17,r17,r2
+ 800ea00:	18005a26 	beq	r3,zero,800eb6c <__muldf3+0x60c>
+ 800ea04:	8804d07a 	srli	r2,r17,1
+ 800ea08:	800697fa 	slli	r3,r16,31
+ 800ea0c:	8c40004c 	andi	r17,r17,1
+ 800ea10:	8020d07a 	srli	r16,r16,1
+ 800ea14:	1462b03a 	or	r17,r2,r17
+ 800ea18:	88e2b03a 	or	r17,r17,r3
+ 800ea1c:	28c0ffc4 	addi	r3,r5,1023
+ 800ea20:	00c0350e 	bge	zero,r3,800eaf8 <__muldf3+0x598>
+ 800ea24:	888001cc 	andi	r2,r17,7
+ 800ea28:	10000726 	beq	r2,zero,800ea48 <__muldf3+0x4e8>
+ 800ea2c:	888003cc 	andi	r2,r17,15
+ 800ea30:	10800120 	cmpeqi	r2,r2,4
+ 800ea34:	1000041e 	bne	r2,zero,800ea48 <__muldf3+0x4e8>
+ 800ea38:	88800104 	addi	r2,r17,4
+ 800ea3c:	1463803a 	cmpltu	r17,r2,r17
+ 800ea40:	8461883a 	add	r16,r16,r17
+ 800ea44:	1023883a 	mov	r17,r2
+ 800ea48:	8080402c 	andhi	r2,r16,256
+ 800ea4c:	10000426 	beq	r2,zero,800ea60 <__muldf3+0x500>
+ 800ea50:	00bfc034 	movhi	r2,65280
+ 800ea54:	10bfffc4 	addi	r2,r2,-1
+ 800ea58:	80a0703a 	and	r16,r16,r2
+ 800ea5c:	28c10004 	addi	r3,r5,1024
+ 800ea60:	1881ffc8 	cmpgei	r2,r3,2047
+ 800ea64:	103f5e1e 	bne	r2,zero,800e7e0 <__muldf3+0x280>
+ 800ea68:	8004977a 	slli	r2,r16,29
+ 800ea6c:	8822d0fa 	srli	r17,r17,3
+ 800ea70:	8020927a 	slli	r16,r16,9
+ 800ea74:	18c1ffcc 	andi	r3,r3,2047
+ 800ea78:	1462b03a 	or	r17,r2,r17
+ 800ea7c:	8020d33a 	srli	r16,r16,12
+ 800ea80:	003f1106 	br	800e6c8 <__muldf3+0x168>
+ 800ea84:	00800434 	movhi	r2,16
+ 800ea88:	84000234 	orhi	r16,r16,8
+ 800ea8c:	10bfffc4 	addi	r2,r2,-1
+ 800ea90:	80a0703a 	and	r16,r16,r2
+ 800ea94:	a00d883a 	mov	r6,r20
+ 800ea98:	003f6d06 	br	800e850 <__muldf3+0x2f0>
+ 800ea9c:	3009883a 	mov	r4,r6
+ 800eaa0:	d9800015 	stw	r6,0(sp)
+ 800eaa4:	800f7900 	call	800f790 <__clzsi2>
+ 800eaa8:	11000544 	addi	r4,r2,21
+ 800eaac:	21400748 	cmpgei	r5,r4,29
+ 800eab0:	10c00804 	addi	r3,r2,32
+ 800eab4:	d9800017 	ldw	r6,0(sp)
+ 800eab8:	283f3e26 	beq	r5,zero,800e7b4 <__muldf3+0x254>
+ 800eabc:	10bffe04 	addi	r2,r2,-8
+ 800eac0:	30a4983a 	sll	r18,r6,r2
+ 800eac4:	0011883a 	mov	r8,zero
+ 800eac8:	003f4106 	br	800e7d0 <__muldf3+0x270>
+ 800eacc:	800f7900 	call	800f790 <__clzsi2>
+ 800ead0:	11400544 	addi	r5,r2,21
+ 800ead4:	29000748 	cmpgei	r4,r5,29
+ 800ead8:	10c00804 	addi	r3,r2,32
+ 800eadc:	d9800017 	ldw	r6,0(sp)
+ 800eae0:	d9c00117 	ldw	r7,4(sp)
+ 800eae4:	203f1726 	beq	r4,zero,800e744 <__muldf3+0x1e4>
+ 800eae8:	10bffe04 	addi	r2,r2,-8
+ 800eaec:	90a0983a 	sll	r16,r18,r2
+ 800eaf0:	0023883a 	mov	r17,zero
+ 800eaf4:	003f1a06 	br	800e760 <__muldf3+0x200>
+ 800eaf8:	00800044 	movi	r2,1
+ 800eafc:	10c5c83a 	sub	r2,r2,r3
+ 800eb00:	11000e48 	cmpgei	r4,r2,57
+ 800eb04:	203eed1e 	bne	r4,zero,800e6bc <__muldf3+0x15c>
+ 800eb08:	11000808 	cmpgei	r4,r2,32
+ 800eb0c:	2000191e 	bne	r4,zero,800eb74 <__muldf3+0x614>
+ 800eb10:	29410784 	addi	r5,r5,1054
+ 800eb14:	8146983a 	sll	r3,r16,r5
+ 800eb18:	8888d83a 	srl	r4,r17,r2
+ 800eb1c:	894a983a 	sll	r5,r17,r5
+ 800eb20:	80a0d83a 	srl	r16,r16,r2
+ 800eb24:	1904b03a 	or	r2,r3,r4
+ 800eb28:	2822c03a 	cmpne	r17,r5,zero
+ 800eb2c:	1444b03a 	or	r2,r2,r17
+ 800eb30:	10c001cc 	andi	r3,r2,7
+ 800eb34:	18000726 	beq	r3,zero,800eb54 <__muldf3+0x5f4>
+ 800eb38:	10c003cc 	andi	r3,r2,15
+ 800eb3c:	18c00120 	cmpeqi	r3,r3,4
+ 800eb40:	1800041e 	bne	r3,zero,800eb54 <__muldf3+0x5f4>
+ 800eb44:	10c00104 	addi	r3,r2,4
+ 800eb48:	1885803a 	cmpltu	r2,r3,r2
+ 800eb4c:	80a1883a 	add	r16,r16,r2
+ 800eb50:	1805883a 	mov	r2,r3
+ 800eb54:	80c0202c 	andhi	r3,r16,128
+ 800eb58:	18001b26 	beq	r3,zero,800ebc8 <__muldf3+0x668>
+ 800eb5c:	00c00044 	movi	r3,1
+ 800eb60:	0021883a 	mov	r16,zero
+ 800eb64:	0023883a 	mov	r17,zero
+ 800eb68:	003ed706 	br	800e6c8 <__muldf3+0x168>
+ 800eb6c:	980b883a 	mov	r5,r19
+ 800eb70:	003faa06 	br	800ea1c <__muldf3+0x4bc>
+ 800eb74:	013ff844 	movi	r4,-31
+ 800eb78:	20c7c83a 	sub	r3,r4,r3
+ 800eb7c:	10800820 	cmpeqi	r2,r2,32
+ 800eb80:	80c6d83a 	srl	r3,r16,r3
+ 800eb84:	1000031e 	bne	r2,zero,800eb94 <__muldf3+0x634>
+ 800eb88:	28810f84 	addi	r2,r5,1086
+ 800eb8c:	8084983a 	sll	r2,r16,r2
+ 800eb90:	88a2b03a 	or	r17,r17,r2
+ 800eb94:	8822c03a 	cmpne	r17,r17,zero
+ 800eb98:	88c4b03a 	or	r2,r17,r3
+ 800eb9c:	144001cc 	andi	r17,r2,7
+ 800eba0:	8800051e 	bne	r17,zero,800ebb8 <__muldf3+0x658>
+ 800eba4:	0021883a 	mov	r16,zero
+ 800eba8:	1004d0fa 	srli	r2,r2,3
+ 800ebac:	0007883a 	mov	r3,zero
+ 800ebb0:	1462b03a 	or	r17,r2,r17
+ 800ebb4:	003ec406 	br	800e6c8 <__muldf3+0x168>
+ 800ebb8:	10c003cc 	andi	r3,r2,15
+ 800ebbc:	18c00118 	cmpnei	r3,r3,4
+ 800ebc0:	0021883a 	mov	r16,zero
+ 800ebc4:	183fdf1e 	bne	r3,zero,800eb44 <__muldf3+0x5e4>
+ 800ebc8:	8006927a 	slli	r3,r16,9
+ 800ebcc:	8022977a 	slli	r17,r16,29
+ 800ebd0:	1820d33a 	srli	r16,r3,12
+ 800ebd4:	003ff406 	br	800eba8 <__muldf3+0x648>
+ 800ebd8:	00800434 	movhi	r2,16
+ 800ebdc:	84000234 	orhi	r16,r16,8
+ 800ebe0:	10bfffc4 	addi	r2,r2,-1
+ 800ebe4:	80a0703a 	and	r16,r16,r2
+ 800ebe8:	003f1906 	br	800e850 <__muldf3+0x2f0>
+
+0800ebec <__subdf3>:
+ 800ebec:	00800434 	movhi	r2,16
+ 800ebf0:	3812d53a 	srli	r9,r7,20
+ 800ebf4:	10bfffc4 	addi	r2,r2,-1
+ 800ebf8:	defffb04 	addi	sp,sp,-20
+ 800ebfc:	2890703a 	and	r8,r5,r2
+ 800ec00:	3884703a 	and	r2,r7,r2
+ 800ec04:	2806d7fa 	srli	r3,r5,31
+ 800ec08:	dcc00315 	stw	r19,12(sp)
+ 800ec0c:	dc400115 	stw	r17,4(sp)
+ 800ec10:	280ad53a 	srli	r5,r5,20
+ 800ec14:	401090fa 	slli	r8,r8,3
+ 800ec18:	2026d77a 	srli	r19,r4,29
+ 800ec1c:	100490fa 	slli	r2,r2,3
+ 800ec20:	3022d77a 	srli	r17,r6,29
+ 800ec24:	4a81ffcc 	andi	r10,r9,2047
+ 800ec28:	dc800215 	stw	r18,8(sp)
+ 800ec2c:	dc000015 	stw	r16,0(sp)
+ 800ec30:	dfc00415 	stw	ra,16(sp)
+ 800ec34:	5241ffe0 	cmpeqi	r9,r10,2047
+ 800ec38:	1825883a 	mov	r18,r3
+ 800ec3c:	2c01ffcc 	andi	r16,r5,2047
+ 800ec40:	18c03fcc 	andi	r3,r3,255
+ 800ec44:	9a18b03a 	or	r12,r19,r8
+ 800ec48:	201a90fa 	slli	r13,r4,3
+ 800ec4c:	380ed7fa 	srli	r7,r7,31
+ 800ec50:	8896b03a 	or	r11,r17,r2
+ 800ec54:	301c90fa 	slli	r14,r6,3
+ 800ec58:	4800711e 	bne	r9,zero,800ee20 <__subdf3+0x234>
+ 800ec5c:	39c0005c 	xori	r7,r7,1
+ 800ec60:	8291c83a 	sub	r8,r16,r10
+ 800ec64:	19c05a26 	beq	r3,r7,800edd0 <__subdf3+0x1e4>
+ 800ec68:	0200720e 	bge	zero,r8,800ee34 <__subdf3+0x248>
+ 800ec6c:	50008126 	beq	r10,zero,800ee74 <__subdf3+0x288>
+ 800ec70:	8081ffd8 	cmpnei	r2,r16,2047
+ 800ec74:	10011626 	beq	r2,zero,800f0d0 <__subdf3+0x4e4>
+ 800ec78:	5ac02034 	orhi	r11,r11,128
+ 800ec7c:	40800e48 	cmpgei	r2,r8,57
+ 800ec80:	1000fe1e 	bne	r2,zero,800f07c <__subdf3+0x490>
+ 800ec84:	40800808 	cmpgei	r2,r8,32
+ 800ec88:	10015e1e 	bne	r2,zero,800f204 <__subdf3+0x618>
+ 800ec8c:	00800804 	movi	r2,32
+ 800ec90:	1205c83a 	sub	r2,r2,r8
+ 800ec94:	58a2983a 	sll	r17,r11,r2
+ 800ec98:	7206d83a 	srl	r3,r14,r8
+ 800ec9c:	709c983a 	sll	r14,r14,r2
+ 800eca0:	5a04d83a 	srl	r2,r11,r8
+ 800eca4:	88e2b03a 	or	r17,r17,r3
+ 800eca8:	701cc03a 	cmpne	r14,r14,zero
+ 800ecac:	8ba2b03a 	or	r17,r17,r14
+ 800ecb0:	6099c83a 	sub	r12,r12,r2
+ 800ecb4:	6c63c83a 	sub	r17,r13,r17
+ 800ecb8:	6c49803a 	cmpltu	r4,r13,r17
+ 800ecbc:	6109c83a 	sub	r4,r12,r4
+ 800ecc0:	2080202c 	andhi	r2,r4,128
+ 800ecc4:	10009f26 	beq	r2,zero,800ef44 <__subdf3+0x358>
+ 800ecc8:	04c02034 	movhi	r19,128
+ 800eccc:	9cffffc4 	addi	r19,r19,-1
+ 800ecd0:	24e6703a 	and	r19,r4,r19
+ 800ecd4:	9800e026 	beq	r19,zero,800f058 <__subdf3+0x46c>
+ 800ecd8:	9809883a 	mov	r4,r19
+ 800ecdc:	800f7900 	call	800f790 <__clzsi2>
+ 800ece0:	123ffe04 	addi	r8,r2,-8
+ 800ece4:	01000804 	movi	r4,32
+ 800ece8:	2209c83a 	sub	r4,r4,r8
+ 800ecec:	8906d83a 	srl	r3,r17,r4
+ 800ecf0:	9a08983a 	sll	r4,r19,r8
+ 800ecf4:	8a22983a 	sll	r17,r17,r8
+ 800ecf8:	1908b03a 	or	r4,r3,r4
+ 800ecfc:	4400cf16 	blt	r8,r16,800f03c <__subdf3+0x450>
+ 800ed00:	4411c83a 	sub	r8,r8,r16
+ 800ed04:	40800044 	addi	r2,r8,1
+ 800ed08:	10c00808 	cmpgei	r3,r2,32
+ 800ed0c:	1801251e 	bne	r3,zero,800f1a4 <__subdf3+0x5b8>
+ 800ed10:	00c00804 	movi	r3,32
+ 800ed14:	1887c83a 	sub	r3,r3,r2
+ 800ed18:	888ad83a 	srl	r5,r17,r2
+ 800ed1c:	88e2983a 	sll	r17,r17,r3
+ 800ed20:	20c6983a 	sll	r3,r4,r3
+ 800ed24:	2088d83a 	srl	r4,r4,r2
+ 800ed28:	8822c03a 	cmpne	r17,r17,zero
+ 800ed2c:	1946b03a 	or	r3,r3,r5
+ 800ed30:	1c62b03a 	or	r17,r3,r17
+ 800ed34:	0021883a 	mov	r16,zero
+ 800ed38:	888001cc 	andi	r2,r17,7
+ 800ed3c:	10000726 	beq	r2,zero,800ed5c <__subdf3+0x170>
+ 800ed40:	888003cc 	andi	r2,r17,15
+ 800ed44:	10800120 	cmpeqi	r2,r2,4
+ 800ed48:	1000041e 	bne	r2,zero,800ed5c <__subdf3+0x170>
+ 800ed4c:	88c00104 	addi	r3,r17,4
+ 800ed50:	1c63803a 	cmpltu	r17,r3,r17
+ 800ed54:	2449883a 	add	r4,r4,r17
+ 800ed58:	1823883a 	mov	r17,r3
+ 800ed5c:	2080202c 	andhi	r2,r4,128
+ 800ed60:	10007a26 	beq	r2,zero,800ef4c <__subdf3+0x360>
+ 800ed64:	82000044 	addi	r8,r16,1
+ 800ed68:	4081ffe0 	cmpeqi	r2,r8,2047
+ 800ed6c:	4201ffcc 	andi	r8,r8,2047
+ 800ed70:	10008c1e 	bne	r2,zero,800efa4 <__subdf3+0x3b8>
+ 800ed74:	00bfe034 	movhi	r2,65408
+ 800ed78:	10bfffc4 	addi	r2,r2,-1
+ 800ed7c:	2084703a 	and	r2,r4,r2
+ 800ed80:	1008927a 	slli	r4,r2,9
+ 800ed84:	8822d0fa 	srli	r17,r17,3
+ 800ed88:	100c977a 	slli	r6,r2,29
+ 800ed8c:	2008d33a 	srli	r4,r4,12
+ 800ed90:	3444b03a 	or	r2,r6,r17
+ 800ed94:	4010953a 	slli	r8,r8,20
+ 800ed98:	00c00434 	movhi	r3,16
+ 800ed9c:	94803fcc 	andi	r18,r18,255
+ 800eda0:	902497fa 	slli	r18,r18,31
+ 800eda4:	18ffffc4 	addi	r3,r3,-1
+ 800eda8:	20c6703a 	and	r3,r4,r3
+ 800edac:	1a06b03a 	or	r3,r3,r8
+ 800edb0:	1c86b03a 	or	r3,r3,r18
+ 800edb4:	dfc00417 	ldw	ra,16(sp)
+ 800edb8:	dcc00317 	ldw	r19,12(sp)
+ 800edbc:	dc800217 	ldw	r18,8(sp)
+ 800edc0:	dc400117 	ldw	r17,4(sp)
+ 800edc4:	dc000017 	ldw	r16,0(sp)
+ 800edc8:	dec00504 	addi	sp,sp,20
+ 800edcc:	f800283a 	ret
+ 800edd0:	0200320e 	bge	zero,r8,800ee9c <__subdf3+0x2b0>
+ 800edd4:	50004c26 	beq	r10,zero,800ef08 <__subdf3+0x31c>
+ 800edd8:	8081ffd8 	cmpnei	r2,r16,2047
+ 800eddc:	1000bc26 	beq	r2,zero,800f0d0 <__subdf3+0x4e4>
+ 800ede0:	5ac02034 	orhi	r11,r11,128
+ 800ede4:	40800e48 	cmpgei	r2,r8,57
+ 800ede8:	1000641e 	bne	r2,zero,800ef7c <__subdf3+0x390>
+ 800edec:	40800808 	cmpgei	r2,r8,32
+ 800edf0:	10011726 	beq	r2,zero,800f250 <__subdf3+0x664>
+ 800edf4:	447ff804 	addi	r17,r8,-32
+ 800edf8:	40800820 	cmpeqi	r2,r8,32
+ 800edfc:	5c46d83a 	srl	r3,r11,r17
+ 800ee00:	1000041e 	bne	r2,zero,800ee14 <__subdf3+0x228>
+ 800ee04:	00801004 	movi	r2,64
+ 800ee08:	1205c83a 	sub	r2,r2,r8
+ 800ee0c:	5884983a 	sll	r2,r11,r2
+ 800ee10:	709cb03a 	or	r14,r14,r2
+ 800ee14:	7022c03a 	cmpne	r17,r14,zero
+ 800ee18:	88e2b03a 	or	r17,r17,r3
+ 800ee1c:	00005906 	br	800ef84 <__subdf3+0x398>
+ 800ee20:	5b8ab03a 	or	r5,r11,r14
+ 800ee24:	823e0044 	addi	r8,r16,-2047
+ 800ee28:	28001a1e 	bne	r5,zero,800ee94 <__subdf3+0x2a8>
+ 800ee2c:	39c0005c 	xori	r7,r7,1
+ 800ee30:	19c01a26 	beq	r3,r7,800ee9c <__subdf3+0x2b0>
+ 800ee34:	4000291e 	bne	r8,zero,800eedc <__subdf3+0x2f0>
+ 800ee38:	80800044 	addi	r2,r16,1
+ 800ee3c:	1081ff8c 	andi	r2,r2,2046
+ 800ee40:	1000911e 	bne	r2,zero,800f088 <__subdf3+0x49c>
+ 800ee44:	6346b03a 	or	r3,r12,r13
+ 800ee48:	5b84b03a 	or	r2,r11,r14
+ 800ee4c:	8001551e 	bne	r16,zero,800f3a4 <__subdf3+0x7b8>
+ 800ee50:	18011b26 	beq	r3,zero,800f2c0 <__subdf3+0x6d4>
+ 800ee54:	1001641e 	bne	r2,zero,800f3e8 <__subdf3+0x7fc>
+ 800ee58:	00880034 	movhi	r2,8192
+ 800ee5c:	6022977a 	slli	r17,r12,29
+ 800ee60:	10bfffc4 	addi	r2,r2,-1
+ 800ee64:	2088703a 	and	r4,r4,r2
+ 800ee68:	2444b03a 	or	r2,r4,r17
+ 800ee6c:	6026d0fa 	srli	r19,r12,3
+ 800ee70:	00003d06 	br	800ef68 <__subdf3+0x37c>
+ 800ee74:	5b84b03a 	or	r2,r11,r14
+ 800ee78:	10008e26 	beq	r2,zero,800f0b4 <__subdf3+0x4c8>
+ 800ee7c:	40bfffc4 	addi	r2,r8,-1
+ 800ee80:	10011f26 	beq	r2,zero,800f300 <__subdf3+0x714>
+ 800ee84:	4201ffd8 	cmpnei	r8,r8,2047
+ 800ee88:	40012d26 	beq	r8,zero,800f340 <__subdf3+0x754>
+ 800ee8c:	1011883a 	mov	r8,r2
+ 800ee90:	003f7a06 	br	800ec7c <__subdf3+0x90>
+ 800ee94:	39c03fcc 	andi	r7,r7,255
+ 800ee98:	19ffe61e 	bne	r3,r7,800ee34 <__subdf3+0x248>
+ 800ee9c:	4000931e 	bne	r8,zero,800f0ec <__subdf3+0x500>
+ 800eea0:	80c00044 	addi	r3,r16,1
+ 800eea4:	1881ff8c 	andi	r2,r3,2046
+ 800eea8:	10012c1e 	bne	r2,zero,800f35c <__subdf3+0x770>
+ 800eeac:	6344b03a 	or	r2,r12,r13
+ 800eeb0:	8000f91e 	bne	r16,zero,800f298 <__subdf3+0x6ac>
+ 800eeb4:	10017326 	beq	r2,zero,800f484 <__subdf3+0x898>
+ 800eeb8:	5b84b03a 	or	r2,r11,r14
+ 800eebc:	1001781e 	bne	r2,zero,800f4a0 <__subdf3+0x8b4>
+ 800eec0:	6004977a 	slli	r2,r12,29
+ 800eec4:	00c80034 	movhi	r3,8192
+ 800eec8:	18ffffc4 	addi	r3,r3,-1
+ 800eecc:	20c6703a 	and	r3,r4,r3
+ 800eed0:	10c4b03a 	or	r2,r2,r3
+ 800eed4:	6026d0fa 	srli	r19,r12,3
+ 800eed8:	00002306 	br	800ef68 <__subdf3+0x37c>
+ 800eedc:	5411c83a 	sub	r8,r10,r16
+ 800eee0:	3825883a 	mov	r18,r7
+ 800eee4:	8000991e 	bne	r16,zero,800f14c <__subdf3+0x560>
+ 800eee8:	6344b03a 	or	r2,r12,r13
+ 800eeec:	1000e326 	beq	r2,zero,800f27c <__subdf3+0x690>
+ 800eef0:	40bfffc4 	addi	r2,r8,-1
+ 800eef4:	10015d26 	beq	r2,zero,800f46c <__subdf3+0x880>
+ 800eef8:	4201ffd8 	cmpnei	r8,r8,2047
+ 800eefc:	4000f926 	beq	r8,zero,800f2e4 <__subdf3+0x6f8>
+ 800ef00:	1011883a 	mov	r8,r2
+ 800ef04:	00009406 	br	800f158 <__subdf3+0x56c>
+ 800ef08:	5b84b03a 	or	r2,r11,r14
+ 800ef0c:	10010226 	beq	r2,zero,800f318 <__subdf3+0x72c>
+ 800ef10:	40bfffc4 	addi	r2,r8,-1
+ 800ef14:	10000426 	beq	r2,zero,800ef28 <__subdf3+0x33c>
+ 800ef18:	4201ffd8 	cmpnei	r8,r8,2047
+ 800ef1c:	40014126 	beq	r8,zero,800f424 <__subdf3+0x838>
+ 800ef20:	1011883a 	mov	r8,r2
+ 800ef24:	003faf06 	br	800ede4 <__subdf3+0x1f8>
+ 800ef28:	6ba3883a 	add	r17,r13,r14
+ 800ef2c:	62c9883a 	add	r4,r12,r11
+ 800ef30:	8b5b803a 	cmpltu	r13,r17,r13
+ 800ef34:	2349883a 	add	r4,r4,r13
+ 800ef38:	2080202c 	andhi	r2,r4,128
+ 800ef3c:	1000a61e 	bne	r2,zero,800f1d8 <__subdf3+0x5ec>
+ 800ef40:	04000044 	movi	r16,1
+ 800ef44:	888001cc 	andi	r2,r17,7
+ 800ef48:	103f7d1e 	bne	r2,zero,800ed40 <__subdf3+0x154>
+ 800ef4c:	8822d0fa 	srli	r17,r17,3
+ 800ef50:	2004977a 	slli	r2,r4,29
+ 800ef54:	2026d0fa 	srli	r19,r4,3
+ 800ef58:	8011883a 	mov	r8,r16
+ 800ef5c:	8884b03a 	or	r2,r17,r2
+ 800ef60:	40c1ffe0 	cmpeqi	r3,r8,2047
+ 800ef64:	18002d1e 	bne	r3,zero,800f01c <__subdf3+0x430>
+ 800ef68:	01000434 	movhi	r4,16
+ 800ef6c:	213fffc4 	addi	r4,r4,-1
+ 800ef70:	9908703a 	and	r4,r19,r4
+ 800ef74:	4201ffcc 	andi	r8,r8,2047
+ 800ef78:	003f8606 	br	800ed94 <__subdf3+0x1a8>
+ 800ef7c:	5ba2b03a 	or	r17,r11,r14
+ 800ef80:	8822c03a 	cmpne	r17,r17,zero
+ 800ef84:	8b63883a 	add	r17,r17,r13
+ 800ef88:	8b49803a 	cmpltu	r4,r17,r13
+ 800ef8c:	2309883a 	add	r4,r4,r12
+ 800ef90:	2080202c 	andhi	r2,r4,128
+ 800ef94:	103feb26 	beq	r2,zero,800ef44 <__subdf3+0x358>
+ 800ef98:	84000044 	addi	r16,r16,1
+ 800ef9c:	8081ffe0 	cmpeqi	r2,r16,2047
+ 800efa0:	10008e26 	beq	r2,zero,800f1dc <__subdf3+0x5f0>
+ 800efa4:	0201ffc4 	movi	r8,2047
+ 800efa8:	0009883a 	mov	r4,zero
+ 800efac:	0005883a 	mov	r2,zero
+ 800efb0:	003f7806 	br	800ed94 <__subdf3+0x1a8>
+ 800efb4:	6010977a 	slli	r8,r12,29
+ 800efb8:	6026d0fa 	srli	r19,r12,3
+ 800efbc:	1000bb26 	beq	r2,zero,800f2ac <__subdf3+0x6c0>
+ 800efc0:	01480034 	movhi	r5,8192
+ 800efc4:	297fffc4 	addi	r5,r5,-1
+ 800efc8:	2146703a 	and	r3,r4,r5
+ 800efcc:	9880022c 	andhi	r2,r19,8
+ 800efd0:	1a06b03a 	or	r3,r3,r8
+ 800efd4:	10000826 	beq	r2,zero,800eff8 <__subdf3+0x40c>
+ 800efd8:	5808d0fa 	srli	r4,r11,3
+ 800efdc:	2080022c 	andhi	r2,r4,8
+ 800efe0:	1000051e 	bne	r2,zero,800eff8 <__subdf3+0x40c>
+ 800efe4:	5804977a 	slli	r2,r11,29
+ 800efe8:	3146703a 	and	r3,r6,r5
+ 800efec:	3825883a 	mov	r18,r7
+ 800eff0:	1886b03a 	or	r3,r3,r2
+ 800eff4:	2027883a 	mov	r19,r4
+ 800eff8:	1804d77a 	srli	r2,r3,29
+ 800effc:	980890fa 	slli	r4,r19,3
+ 800f000:	01480034 	movhi	r5,8192
+ 800f004:	297fffc4 	addi	r5,r5,-1
+ 800f008:	1108b03a 	or	r4,r2,r4
+ 800f00c:	2004977a 	slli	r2,r4,29
+ 800f010:	2026d0fa 	srli	r19,r4,3
+ 800f014:	1946703a 	and	r3,r3,r5
+ 800f018:	10c4b03a 	or	r2,r2,r3
+ 800f01c:	14c6b03a 	or	r3,r2,r19
+ 800f020:	18014926 	beq	r3,zero,800f548 <__subdf3+0x95c>
+ 800f024:	00c00434 	movhi	r3,16
+ 800f028:	99000234 	orhi	r4,r19,8
+ 800f02c:	18ffffc4 	addi	r3,r3,-1
+ 800f030:	20c8703a 	and	r4,r4,r3
+ 800f034:	0201ffc4 	movi	r8,2047
+ 800f038:	003f5606 	br	800ed94 <__subdf3+0x1a8>
+ 800f03c:	00bfe034 	movhi	r2,65408
+ 800f040:	10bfffc4 	addi	r2,r2,-1
+ 800f044:	2088703a 	and	r4,r4,r2
+ 800f048:	888001cc 	andi	r2,r17,7
+ 800f04c:	8221c83a 	sub	r16,r16,r8
+ 800f050:	103f3b1e 	bne	r2,zero,800ed40 <__subdf3+0x154>
+ 800f054:	003fbd06 	br	800ef4c <__subdf3+0x360>
+ 800f058:	8809883a 	mov	r4,r17
+ 800f05c:	800f7900 	call	800f790 <__clzsi2>
+ 800f060:	12000604 	addi	r8,r2,24
+ 800f064:	40c00808 	cmpgei	r3,r8,32
+ 800f068:	183f1e26 	beq	r3,zero,800ece4 <__subdf3+0xf8>
+ 800f06c:	113ffe04 	addi	r4,r2,-8
+ 800f070:	8908983a 	sll	r4,r17,r4
+ 800f074:	0023883a 	mov	r17,zero
+ 800f078:	003f2006 	br	800ecfc <__subdf3+0x110>
+ 800f07c:	5ba2b03a 	or	r17,r11,r14
+ 800f080:	8822c03a 	cmpne	r17,r17,zero
+ 800f084:	003f0b06 	br	800ecb4 <__subdf3+0xc8>
+ 800f088:	6ba3c83a 	sub	r17,r13,r14
+ 800f08c:	62e7c83a 	sub	r19,r12,r11
+ 800f090:	6c49803a 	cmpltu	r4,r13,r17
+ 800f094:	9927c83a 	sub	r19,r19,r4
+ 800f098:	9880202c 	andhi	r2,r19,128
+ 800f09c:	1000bb1e 	bne	r2,zero,800f38c <__subdf3+0x7a0>
+ 800f0a0:	8cc4b03a 	or	r2,r17,r19
+ 800f0a4:	103f0b1e 	bne	r2,zero,800ecd4 <__subdf3+0xe8>
+ 800f0a8:	0027883a 	mov	r19,zero
+ 800f0ac:	0025883a 	mov	r18,zero
+ 800f0b0:	003fad06 	br	800ef68 <__subdf3+0x37c>
+ 800f0b4:	00880034 	movhi	r2,8192
+ 800f0b8:	6022977a 	slli	r17,r12,29
+ 800f0bc:	10bfffc4 	addi	r2,r2,-1
+ 800f0c0:	2088703a 	and	r4,r4,r2
+ 800f0c4:	2444b03a 	or	r2,r4,r17
+ 800f0c8:	6026d0fa 	srli	r19,r12,3
+ 800f0cc:	003fa406 	br	800ef60 <__subdf3+0x374>
+ 800f0d0:	00880034 	movhi	r2,8192
+ 800f0d4:	6022977a 	slli	r17,r12,29
+ 800f0d8:	10bfffc4 	addi	r2,r2,-1
+ 800f0dc:	2088703a 	and	r4,r4,r2
+ 800f0e0:	2444b03a 	or	r2,r4,r17
+ 800f0e4:	6026d0fa 	srli	r19,r12,3
+ 800f0e8:	003fcc06 	br	800f01c <__subdf3+0x430>
+ 800f0ec:	5411c83a 	sub	r8,r10,r16
+ 800f0f0:	80004f26 	beq	r16,zero,800f230 <__subdf3+0x644>
+ 800f0f4:	5081ffd8 	cmpnei	r2,r10,2047
+ 800f0f8:	1000b426 	beq	r2,zero,800f3cc <__subdf3+0x7e0>
+ 800f0fc:	63002034 	orhi	r12,r12,128
+ 800f100:	40800e48 	cmpgei	r2,r8,57
+ 800f104:	1000c41e 	bne	r2,zero,800f418 <__subdf3+0x82c>
+ 800f108:	40800808 	cmpgei	r2,r8,32
+ 800f10c:	1000f91e 	bne	r2,zero,800f4f4 <__subdf3+0x908>
+ 800f110:	00800804 	movi	r2,32
+ 800f114:	1205c83a 	sub	r2,r2,r8
+ 800f118:	60a2983a 	sll	r17,r12,r2
+ 800f11c:	6a06d83a 	srl	r3,r13,r8
+ 800f120:	6884983a 	sll	r2,r13,r2
+ 800f124:	6210d83a 	srl	r8,r12,r8
+ 800f128:	88e2b03a 	or	r17,r17,r3
+ 800f12c:	1004c03a 	cmpne	r2,r2,zero
+ 800f130:	88a2b03a 	or	r17,r17,r2
+ 800f134:	5a17883a 	add	r11,r11,r8
+ 800f138:	8ba3883a 	add	r17,r17,r14
+ 800f13c:	8b85803a 	cmpltu	r2,r17,r14
+ 800f140:	12c9883a 	add	r4,r2,r11
+ 800f144:	5021883a 	mov	r16,r10
+ 800f148:	003f9106 	br	800ef90 <__subdf3+0x3a4>
+ 800f14c:	5081ffd8 	cmpnei	r2,r10,2047
+ 800f150:	10006426 	beq	r2,zero,800f2e4 <__subdf3+0x6f8>
+ 800f154:	63002034 	orhi	r12,r12,128
+ 800f158:	40800e48 	cmpgei	r2,r8,57
+ 800f15c:	1000751e 	bne	r2,zero,800f334 <__subdf3+0x748>
+ 800f160:	40800808 	cmpgei	r2,r8,32
+ 800f164:	1000b61e 	bne	r2,zero,800f440 <__subdf3+0x854>
+ 800f168:	00800804 	movi	r2,32
+ 800f16c:	1205c83a 	sub	r2,r2,r8
+ 800f170:	60a2983a 	sll	r17,r12,r2
+ 800f174:	6a06d83a 	srl	r3,r13,r8
+ 800f178:	6884983a 	sll	r2,r13,r2
+ 800f17c:	6210d83a 	srl	r8,r12,r8
+ 800f180:	88e2b03a 	or	r17,r17,r3
+ 800f184:	1004c03a 	cmpne	r2,r2,zero
+ 800f188:	88a2b03a 	or	r17,r17,r2
+ 800f18c:	5a17c83a 	sub	r11,r11,r8
+ 800f190:	7463c83a 	sub	r17,r14,r17
+ 800f194:	7445803a 	cmpltu	r2,r14,r17
+ 800f198:	5889c83a 	sub	r4,r11,r2
+ 800f19c:	5021883a 	mov	r16,r10
+ 800f1a0:	003ec706 	br	800ecc0 <__subdf3+0xd4>
+ 800f1a4:	423ff844 	addi	r8,r8,-31
+ 800f1a8:	10c00820 	cmpeqi	r3,r2,32
+ 800f1ac:	2210d83a 	srl	r8,r4,r8
+ 800f1b0:	1800041e 	bne	r3,zero,800f1c4 <__subdf3+0x5d8>
+ 800f1b4:	00c01004 	movi	r3,64
+ 800f1b8:	1885c83a 	sub	r2,r3,r2
+ 800f1bc:	2088983a 	sll	r4,r4,r2
+ 800f1c0:	8922b03a 	or	r17,r17,r4
+ 800f1c4:	8822c03a 	cmpne	r17,r17,zero
+ 800f1c8:	8a22b03a 	or	r17,r17,r8
+ 800f1cc:	0009883a 	mov	r4,zero
+ 800f1d0:	0021883a 	mov	r16,zero
+ 800f1d4:	003f5b06 	br	800ef44 <__subdf3+0x358>
+ 800f1d8:	04000084 	movi	r16,2
+ 800f1dc:	00bfe034 	movhi	r2,65408
+ 800f1e0:	10bfffc4 	addi	r2,r2,-1
+ 800f1e4:	2084703a 	and	r2,r4,r2
+ 800f1e8:	8806d07a 	srli	r3,r17,1
+ 800f1ec:	100a97fa 	slli	r5,r2,31
+ 800f1f0:	8c40004c 	andi	r17,r17,1
+ 800f1f4:	1c62b03a 	or	r17,r3,r17
+ 800f1f8:	1008d07a 	srli	r4,r2,1
+ 800f1fc:	2c62b03a 	or	r17,r5,r17
+ 800f200:	003ecd06 	br	800ed38 <__subdf3+0x14c>
+ 800f204:	447ff804 	addi	r17,r8,-32
+ 800f208:	40800820 	cmpeqi	r2,r8,32
+ 800f20c:	5c46d83a 	srl	r3,r11,r17
+ 800f210:	1000041e 	bne	r2,zero,800f224 <__subdf3+0x638>
+ 800f214:	00801004 	movi	r2,64
+ 800f218:	1205c83a 	sub	r2,r2,r8
+ 800f21c:	5884983a 	sll	r2,r11,r2
+ 800f220:	709cb03a 	or	r14,r14,r2
+ 800f224:	7022c03a 	cmpne	r17,r14,zero
+ 800f228:	88e2b03a 	or	r17,r17,r3
+ 800f22c:	003ea106 	br	800ecb4 <__subdf3+0xc8>
+ 800f230:	6344b03a 	or	r2,r12,r13
+ 800f234:	1000a526 	beq	r2,zero,800f4cc <__subdf3+0x8e0>
+ 800f238:	40bfffc4 	addi	r2,r8,-1
+ 800f23c:	1000bd26 	beq	r2,zero,800f534 <__subdf3+0x948>
+ 800f240:	4201ffd8 	cmpnei	r8,r8,2047
+ 800f244:	40006126 	beq	r8,zero,800f3cc <__subdf3+0x7e0>
+ 800f248:	1011883a 	mov	r8,r2
+ 800f24c:	003fac06 	br	800f100 <__subdf3+0x514>
+ 800f250:	00800804 	movi	r2,32
+ 800f254:	1205c83a 	sub	r2,r2,r8
+ 800f258:	58a2983a 	sll	r17,r11,r2
+ 800f25c:	7206d83a 	srl	r3,r14,r8
+ 800f260:	709c983a 	sll	r14,r14,r2
+ 800f264:	5a04d83a 	srl	r2,r11,r8
+ 800f268:	88e2b03a 	or	r17,r17,r3
+ 800f26c:	701cc03a 	cmpne	r14,r14,zero
+ 800f270:	8ba2b03a 	or	r17,r17,r14
+ 800f274:	6099883a 	add	r12,r12,r2
+ 800f278:	003f4206 	br	800ef84 <__subdf3+0x398>
+ 800f27c:	5808977a 	slli	r4,r11,29
+ 800f280:	00c80034 	movhi	r3,8192
+ 800f284:	18ffffc4 	addi	r3,r3,-1
+ 800f288:	30cc703a 	and	r6,r6,r3
+ 800f28c:	2184b03a 	or	r2,r4,r6
+ 800f290:	5826d0fa 	srli	r19,r11,3
+ 800f294:	003f3206 	br	800ef60 <__subdf3+0x374>
+ 800f298:	10004c26 	beq	r2,zero,800f3cc <__subdf3+0x7e0>
+ 800f29c:	5b9cb03a 	or	r14,r11,r14
+ 800f2a0:	6010977a 	slli	r8,r12,29
+ 800f2a4:	6026d0fa 	srli	r19,r12,3
+ 800f2a8:	703f451e 	bne	r14,zero,800efc0 <__subdf3+0x3d4>
+ 800f2ac:	00880034 	movhi	r2,8192
+ 800f2b0:	10bfffc4 	addi	r2,r2,-1
+ 800f2b4:	2084703a 	and	r2,r4,r2
+ 800f2b8:	1204b03a 	or	r2,r2,r8
+ 800f2bc:	003f5706 	br	800f01c <__subdf3+0x430>
+ 800f2c0:	103f7926 	beq	r2,zero,800f0a8 <__subdf3+0x4bc>
+ 800f2c4:	5804977a 	slli	r2,r11,29
+ 800f2c8:	00c80034 	movhi	r3,8192
+ 800f2cc:	18ffffc4 	addi	r3,r3,-1
+ 800f2d0:	30c6703a 	and	r3,r6,r3
+ 800f2d4:	10c4b03a 	or	r2,r2,r3
+ 800f2d8:	5826d0fa 	srli	r19,r11,3
+ 800f2dc:	3825883a 	mov	r18,r7
+ 800f2e0:	003f2106 	br	800ef68 <__subdf3+0x37c>
+ 800f2e4:	5804977a 	slli	r2,r11,29
+ 800f2e8:	00c80034 	movhi	r3,8192
+ 800f2ec:	18ffffc4 	addi	r3,r3,-1
+ 800f2f0:	30c6703a 	and	r3,r6,r3
+ 800f2f4:	10c4b03a 	or	r2,r2,r3
+ 800f2f8:	5826d0fa 	srli	r19,r11,3
+ 800f2fc:	003f4706 	br	800f01c <__subdf3+0x430>
+ 800f300:	6ba3c83a 	sub	r17,r13,r14
+ 800f304:	62c9c83a 	sub	r4,r12,r11
+ 800f308:	6c5b803a 	cmpltu	r13,r13,r17
+ 800f30c:	2349c83a 	sub	r4,r4,r13
+ 800f310:	04000044 	movi	r16,1
+ 800f314:	003e6a06 	br	800ecc0 <__subdf3+0xd4>
+ 800f318:	6004977a 	slli	r2,r12,29
+ 800f31c:	00c80034 	movhi	r3,8192
+ 800f320:	18ffffc4 	addi	r3,r3,-1
+ 800f324:	20c8703a 	and	r4,r4,r3
+ 800f328:	1104b03a 	or	r2,r2,r4
+ 800f32c:	6026d0fa 	srli	r19,r12,3
+ 800f330:	003f0b06 	br	800ef60 <__subdf3+0x374>
+ 800f334:	6366b03a 	or	r19,r12,r13
+ 800f338:	9822c03a 	cmpne	r17,r19,zero
+ 800f33c:	003f9406 	br	800f190 <__subdf3+0x5a4>
+ 800f340:	6004977a 	slli	r2,r12,29
+ 800f344:	00c80034 	movhi	r3,8192
+ 800f348:	18ffffc4 	addi	r3,r3,-1
+ 800f34c:	20c8703a 	and	r4,r4,r3
+ 800f350:	1104b03a 	or	r2,r2,r4
+ 800f354:	6026d0fa 	srli	r19,r12,3
+ 800f358:	003f3006 	br	800f01c <__subdf3+0x430>
+ 800f35c:	1881ffe0 	cmpeqi	r2,r3,2047
+ 800f360:	103f101e 	bne	r2,zero,800efa4 <__subdf3+0x3b8>
+ 800f364:	6b9d883a 	add	r14,r13,r14
+ 800f368:	62c9883a 	add	r4,r12,r11
+ 800f36c:	7345803a 	cmpltu	r2,r14,r13
+ 800f370:	2085883a 	add	r2,r4,r2
+ 800f374:	102297fa 	slli	r17,r2,31
+ 800f378:	701cd07a 	srli	r14,r14,1
+ 800f37c:	1008d07a 	srli	r4,r2,1
+ 800f380:	1821883a 	mov	r16,r3
+ 800f384:	8ba2b03a 	or	r17,r17,r14
+ 800f388:	003eee06 	br	800ef44 <__subdf3+0x358>
+ 800f38c:	7363c83a 	sub	r17,r14,r13
+ 800f390:	5b09c83a 	sub	r4,r11,r12
+ 800f394:	7467803a 	cmpltu	r19,r14,r17
+ 800f398:	24e7c83a 	sub	r19,r4,r19
+ 800f39c:	3825883a 	mov	r18,r7
+ 800f3a0:	003e4c06 	br	800ecd4 <__subdf3+0xe8>
+ 800f3a4:	183f031e 	bne	r3,zero,800efb4 <__subdf3+0x3c8>
+ 800f3a8:	10005d26 	beq	r2,zero,800f520 <__subdf3+0x934>
+ 800f3ac:	00880034 	movhi	r2,8192
+ 800f3b0:	5806977a 	slli	r3,r11,29
+ 800f3b4:	10bfffc4 	addi	r2,r2,-1
+ 800f3b8:	3084703a 	and	r2,r6,r2
+ 800f3bc:	10c4b03a 	or	r2,r2,r3
+ 800f3c0:	5826d0fa 	srli	r19,r11,3
+ 800f3c4:	3825883a 	mov	r18,r7
+ 800f3c8:	003f1406 	br	800f01c <__subdf3+0x430>
+ 800f3cc:	00880034 	movhi	r2,8192
+ 800f3d0:	5806977a 	slli	r3,r11,29
+ 800f3d4:	10bfffc4 	addi	r2,r2,-1
+ 800f3d8:	3084703a 	and	r2,r6,r2
+ 800f3dc:	10c4b03a 	or	r2,r2,r3
+ 800f3e0:	5826d0fa 	srli	r19,r11,3
+ 800f3e4:	003f0d06 	br	800f01c <__subdf3+0x430>
+ 800f3e8:	6ba3c83a 	sub	r17,r13,r14
+ 800f3ec:	62c5c83a 	sub	r2,r12,r11
+ 800f3f0:	6c49803a 	cmpltu	r4,r13,r17
+ 800f3f4:	1109c83a 	sub	r4,r2,r4
+ 800f3f8:	2080202c 	andhi	r2,r4,128
+ 800f3fc:	10003a26 	beq	r2,zero,800f4e8 <__subdf3+0x8fc>
+ 800f400:	7363c83a 	sub	r17,r14,r13
+ 800f404:	5b09c83a 	sub	r4,r11,r12
+ 800f408:	745d803a 	cmpltu	r14,r14,r17
+ 800f40c:	2389c83a 	sub	r4,r4,r14
+ 800f410:	3825883a 	mov	r18,r7
+ 800f414:	003e4806 	br	800ed38 <__subdf3+0x14c>
+ 800f418:	6362b03a 	or	r17,r12,r13
+ 800f41c:	8822c03a 	cmpne	r17,r17,zero
+ 800f420:	003f4506 	br	800f138 <__subdf3+0x54c>
+ 800f424:	6004977a 	slli	r2,r12,29
+ 800f428:	00c80034 	movhi	r3,8192
+ 800f42c:	18ffffc4 	addi	r3,r3,-1
+ 800f430:	20c6703a 	and	r3,r4,r3
+ 800f434:	10c4b03a 	or	r2,r2,r3
+ 800f438:	6026d0fa 	srli	r19,r12,3
+ 800f43c:	003ef706 	br	800f01c <__subdf3+0x430>
+ 800f440:	40bff804 	addi	r2,r8,-32
+ 800f444:	40c00820 	cmpeqi	r3,r8,32
+ 800f448:	6084d83a 	srl	r2,r12,r2
+ 800f44c:	1800041e 	bne	r3,zero,800f460 <__subdf3+0x874>
+ 800f450:	04c01004 	movi	r19,64
+ 800f454:	9a11c83a 	sub	r8,r19,r8
+ 800f458:	6226983a 	sll	r19,r12,r8
+ 800f45c:	6cdab03a 	or	r13,r13,r19
+ 800f460:	6822c03a 	cmpne	r17,r13,zero
+ 800f464:	88a2b03a 	or	r17,r17,r2
+ 800f468:	003f4906 	br	800f190 <__subdf3+0x5a4>
+ 800f46c:	7363c83a 	sub	r17,r14,r13
+ 800f470:	5b09c83a 	sub	r4,r11,r12
+ 800f474:	745d803a 	cmpltu	r14,r14,r17
+ 800f478:	2389c83a 	sub	r4,r4,r14
+ 800f47c:	04000044 	movi	r16,1
+ 800f480:	003e0f06 	br	800ecc0 <__subdf3+0xd4>
+ 800f484:	00880034 	movhi	r2,8192
+ 800f488:	5806977a 	slli	r3,r11,29
+ 800f48c:	10bfffc4 	addi	r2,r2,-1
+ 800f490:	3084703a 	and	r2,r6,r2
+ 800f494:	10c4b03a 	or	r2,r2,r3
+ 800f498:	5826d0fa 	srli	r19,r11,3
+ 800f49c:	003eb206 	br	800ef68 <__subdf3+0x37c>
+ 800f4a0:	6ba3883a 	add	r17,r13,r14
+ 800f4a4:	62c9883a 	add	r4,r12,r11
+ 800f4a8:	8b5b803a 	cmpltu	r13,r17,r13
+ 800f4ac:	2349883a 	add	r4,r4,r13
+ 800f4b0:	2080202c 	andhi	r2,r4,128
+ 800f4b4:	103ea326 	beq	r2,zero,800ef44 <__subdf3+0x358>
+ 800f4b8:	00bfe034 	movhi	r2,65408
+ 800f4bc:	10bfffc4 	addi	r2,r2,-1
+ 800f4c0:	2088703a 	and	r4,r4,r2
+ 800f4c4:	04000044 	movi	r16,1
+ 800f4c8:	003e9e06 	br	800ef44 <__subdf3+0x358>
+ 800f4cc:	00880034 	movhi	r2,8192
+ 800f4d0:	5806977a 	slli	r3,r11,29
+ 800f4d4:	10bfffc4 	addi	r2,r2,-1
+ 800f4d8:	3084703a 	and	r2,r6,r2
+ 800f4dc:	10c4b03a 	or	r2,r2,r3
+ 800f4e0:	5826d0fa 	srli	r19,r11,3
+ 800f4e4:	003e9e06 	br	800ef60 <__subdf3+0x374>
+ 800f4e8:	8904b03a 	or	r2,r17,r4
+ 800f4ec:	103eee26 	beq	r2,zero,800f0a8 <__subdf3+0x4bc>
+ 800f4f0:	003e9406 	br	800ef44 <__subdf3+0x358>
+ 800f4f4:	40bff804 	addi	r2,r8,-32
+ 800f4f8:	40c00820 	cmpeqi	r3,r8,32
+ 800f4fc:	6084d83a 	srl	r2,r12,r2
+ 800f500:	1800041e 	bne	r3,zero,800f514 <__subdf3+0x928>
+ 800f504:	04c01004 	movi	r19,64
+ 800f508:	9a11c83a 	sub	r8,r19,r8
+ 800f50c:	6226983a 	sll	r19,r12,r8
+ 800f510:	6cdab03a 	or	r13,r13,r19
+ 800f514:	6822c03a 	cmpne	r17,r13,zero
+ 800f518:	88a2b03a 	or	r17,r17,r2
+ 800f51c:	003f0606 	br	800f138 <__subdf3+0x54c>
+ 800f520:	04c00434 	movhi	r19,16
+ 800f524:	9cffffc4 	addi	r19,r19,-1
+ 800f528:	0025883a 	mov	r18,zero
+ 800f52c:	00bfffc4 	movi	r2,-1
+ 800f530:	003ebc06 	br	800f024 <__subdf3+0x438>
+ 800f534:	6ba3883a 	add	r17,r13,r14
+ 800f538:	62c9883a 	add	r4,r12,r11
+ 800f53c:	8b9d803a 	cmpltu	r14,r17,r14
+ 800f540:	2389883a 	add	r4,r4,r14
+ 800f544:	003e7c06 	br	800ef38 <__subdf3+0x34c>
+ 800f548:	0005883a 	mov	r2,zero
+ 800f54c:	0201ffc4 	movi	r8,2047
+ 800f550:	0009883a 	mov	r4,zero
+ 800f554:	003e0f06 	br	800ed94 <__subdf3+0x1a8>
+
+0800f558 <__unorddf2>:
+ 800f558:	2806d53a 	srli	r3,r5,20
+ 800f55c:	3810d53a 	srli	r8,r7,20
+ 800f560:	00800434 	movhi	r2,16
+ 800f564:	18c1ffcc 	andi	r3,r3,2047
+ 800f568:	10bfffc4 	addi	r2,r2,-1
+ 800f56c:	18c1ffd8 	cmpnei	r3,r3,2047
+ 800f570:	288a703a 	and	r5,r5,r2
+ 800f574:	388e703a 	and	r7,r7,r2
+ 800f578:	4201ffcc 	andi	r8,r8,2047
+ 800f57c:	18000426 	beq	r3,zero,800f590 <__unorddf2+0x38>
+ 800f580:	4201ffd8 	cmpnei	r8,r8,2047
+ 800f584:	40000626 	beq	r8,zero,800f5a0 <__unorddf2+0x48>
+ 800f588:	0005883a 	mov	r2,zero
+ 800f58c:	f800283a 	ret
+ 800f590:	214ab03a 	or	r5,r4,r5
+ 800f594:	283ffa26 	beq	r5,zero,800f580 <__unorddf2+0x28>
+ 800f598:	00800044 	movi	r2,1
+ 800f59c:	f800283a 	ret
+ 800f5a0:	398eb03a 	or	r7,r7,r6
+ 800f5a4:	3804c03a 	cmpne	r2,r7,zero
+ 800f5a8:	f800283a 	ret
+
+0800f5ac <__fixdfsi>:
+ 800f5ac:	280cd53a 	srli	r6,r5,20
+ 800f5b0:	00c00434 	movhi	r3,16
+ 800f5b4:	18ffffc4 	addi	r3,r3,-1
+ 800f5b8:	3181ffcc 	andi	r6,r6,2047
+ 800f5bc:	31c0ffd0 	cmplti	r7,r6,1023
+ 800f5c0:	28c6703a 	and	r3,r5,r3
+ 800f5c4:	280ad7fa 	srli	r5,r5,31
+ 800f5c8:	3800061e 	bne	r7,zero,800f5e4 <__fixdfsi+0x38>
+ 800f5cc:	30810790 	cmplti	r2,r6,1054
+ 800f5d0:	1000061e 	bne	r2,zero,800f5ec <__fixdfsi+0x40>
+ 800f5d4:	00a00034 	movhi	r2,32768
+ 800f5d8:	10bfffc4 	addi	r2,r2,-1
+ 800f5dc:	2885883a 	add	r2,r5,r2
+ 800f5e0:	f800283a 	ret
+ 800f5e4:	0005883a 	mov	r2,zero
+ 800f5e8:	f800283a 	ret
+ 800f5ec:	00810cc4 	movi	r2,1075
+ 800f5f0:	118fc83a 	sub	r7,r2,r6
+ 800f5f4:	38800808 	cmpgei	r2,r7,32
+ 800f5f8:	18c00434 	orhi	r3,r3,16
+ 800f5fc:	1000071e 	bne	r2,zero,800f61c <__fixdfsi+0x70>
+ 800f600:	30befb44 	addi	r2,r6,-1043
+ 800f604:	1886983a 	sll	r3,r3,r2
+ 800f608:	21c4d83a 	srl	r2,r4,r7
+ 800f60c:	1884b03a 	or	r2,r3,r2
+ 800f610:	283ff526 	beq	r5,zero,800f5e8 <__fixdfsi+0x3c>
+ 800f614:	0085c83a 	sub	r2,zero,r2
+ 800f618:	f800283a 	ret
+ 800f61c:	008104c4 	movi	r2,1043
+ 800f620:	1185c83a 	sub	r2,r2,r6
+ 800f624:	1884d83a 	srl	r2,r3,r2
+ 800f628:	003ff906 	br	800f610 <__fixdfsi+0x64>
+
+0800f62c <__floatsidf>:
+ 800f62c:	defffd04 	addi	sp,sp,-12
+ 800f630:	dfc00215 	stw	ra,8(sp)
+ 800f634:	dc400115 	stw	r17,4(sp)
+ 800f638:	dc000015 	stw	r16,0(sp)
+ 800f63c:	20001326 	beq	r4,zero,800f68c <__floatsidf+0x60>
+ 800f640:	2021883a 	mov	r16,r4
+ 800f644:	2022d7fa 	srli	r17,r4,31
+ 800f648:	20002116 	blt	r4,zero,800f6d0 <__floatsidf+0xa4>
+ 800f64c:	8009883a 	mov	r4,r16
+ 800f650:	800f7900 	call	800f790 <__clzsi2>
+ 800f654:	01010784 	movi	r4,1054
+ 800f658:	2089c83a 	sub	r4,r4,r2
+ 800f65c:	10c002c8 	cmpgei	r3,r2,11
+ 800f660:	2101ffcc 	andi	r4,r4,2047
+ 800f664:	18001c1e 	bne	r3,zero,800f6d8 <__floatsidf+0xac>
+ 800f668:	018002c4 	movi	r6,11
+ 800f66c:	308dc83a 	sub	r6,r6,r2
+ 800f670:	818ad83a 	srl	r5,r16,r6
+ 800f674:	00c00434 	movhi	r3,16
+ 800f678:	10800544 	addi	r2,r2,21
+ 800f67c:	18ffffc4 	addi	r3,r3,-1
+ 800f680:	8084983a 	sll	r2,r16,r2
+ 800f684:	28ca703a 	and	r5,r5,r3
+ 800f688:	00000406 	br	800f69c <__floatsidf+0x70>
+ 800f68c:	0023883a 	mov	r17,zero
+ 800f690:	0009883a 	mov	r4,zero
+ 800f694:	000b883a 	mov	r5,zero
+ 800f698:	0005883a 	mov	r2,zero
+ 800f69c:	2008953a 	slli	r4,r4,20
+ 800f6a0:	8c403fcc 	andi	r17,r17,255
+ 800f6a4:	01800434 	movhi	r6,16
+ 800f6a8:	31bfffc4 	addi	r6,r6,-1
+ 800f6ac:	880697fa 	slli	r3,r17,31
+ 800f6b0:	298a703a 	and	r5,r5,r6
+ 800f6b4:	290ab03a 	or	r5,r5,r4
+ 800f6b8:	28c6b03a 	or	r3,r5,r3
+ 800f6bc:	dfc00217 	ldw	ra,8(sp)
+ 800f6c0:	dc400117 	ldw	r17,4(sp)
+ 800f6c4:	dc000017 	ldw	r16,0(sp)
+ 800f6c8:	dec00304 	addi	sp,sp,12
+ 800f6cc:	f800283a 	ret
+ 800f6d0:	0121c83a 	sub	r16,zero,r4
+ 800f6d4:	003fdd06 	br	800f64c <__floatsidf+0x20>
+ 800f6d8:	10bffd44 	addi	r2,r2,-11
+ 800f6dc:	808a983a 	sll	r5,r16,r2
+ 800f6e0:	00800434 	movhi	r2,16
+ 800f6e4:	10bfffc4 	addi	r2,r2,-1
+ 800f6e8:	288a703a 	and	r5,r5,r2
+ 800f6ec:	0005883a 	mov	r2,zero
+ 800f6f0:	003fea06 	br	800f69c <__floatsidf+0x70>
+
+0800f6f4 <__floatunsidf>:
+ 800f6f4:	defffe04 	addi	sp,sp,-8
+ 800f6f8:	dc000015 	stw	r16,0(sp)
+ 800f6fc:	dfc00115 	stw	ra,4(sp)
+ 800f700:	2021883a 	mov	r16,r4
+ 800f704:	20000f26 	beq	r4,zero,800f744 <__floatunsidf+0x50>
+ 800f708:	800f7900 	call	800f790 <__clzsi2>
+ 800f70c:	01010784 	movi	r4,1054
+ 800f710:	2089c83a 	sub	r4,r4,r2
+ 800f714:	10c002c8 	cmpgei	r3,r2,11
+ 800f718:	2101ffcc 	andi	r4,r4,2047
+ 800f71c:	1800151e 	bne	r3,zero,800f774 <__floatunsidf+0x80>
+ 800f720:	00c002c4 	movi	r3,11
+ 800f724:	1887c83a 	sub	r3,r3,r2
+ 800f728:	80c6d83a 	srl	r3,r16,r3
+ 800f72c:	01400434 	movhi	r5,16
+ 800f730:	10800544 	addi	r2,r2,21
+ 800f734:	297fffc4 	addi	r5,r5,-1
+ 800f738:	80a0983a 	sll	r16,r16,r2
+ 800f73c:	1944703a 	and	r2,r3,r5
+ 800f740:	00000206 	br	800f74c <__floatunsidf+0x58>
+ 800f744:	0009883a 	mov	r4,zero
+ 800f748:	0005883a 	mov	r2,zero
+ 800f74c:	2008953a 	slli	r4,r4,20
+ 800f750:	00c00434 	movhi	r3,16
+ 800f754:	18ffffc4 	addi	r3,r3,-1
+ 800f758:	10c6703a 	and	r3,r2,r3
+ 800f75c:	1906b03a 	or	r3,r3,r4
+ 800f760:	8005883a 	mov	r2,r16
+ 800f764:	dfc00117 	ldw	ra,4(sp)
+ 800f768:	dc000017 	ldw	r16,0(sp)
+ 800f76c:	dec00204 	addi	sp,sp,8
+ 800f770:	f800283a 	ret
+ 800f774:	10bffd44 	addi	r2,r2,-11
+ 800f778:	8084983a 	sll	r2,r16,r2
+ 800f77c:	00c00434 	movhi	r3,16
+ 800f780:	18ffffc4 	addi	r3,r3,-1
+ 800f784:	10c4703a 	and	r2,r2,r3
+ 800f788:	0021883a 	mov	r16,zero
+ 800f78c:	003fef06 	br	800f74c <__floatunsidf+0x58>
+
+0800f790 <__clzsi2>:
+ 800f790:	00bfffd4 	movui	r2,65535
+ 800f794:	11000b36 	bltu	r2,r4,800f7c4 <__clzsi2+0x34>
+ 800f798:	20804030 	cmpltui	r2,r4,256
+ 800f79c:	1000071e 	bne	r2,zero,800f7bc <__clzsi2+0x2c>
+ 800f7a0:	2008d23a 	srli	r4,r4,8
+ 800f7a4:	01400604 	movi	r5,24
+ 800f7a8:	00c20134 	movhi	r3,2052
+ 800f7ac:	20c7883a 	add	r3,r4,r3
+ 800f7b0:	189d8903 	ldbu	r2,30244(r3)
+ 800f7b4:	2885c83a 	sub	r2,r5,r2
+ 800f7b8:	f800283a 	ret
+ 800f7bc:	01400804 	movi	r5,32
+ 800f7c0:	003ff906 	br	800f7a8 <__clzsi2+0x18>
+ 800f7c4:	00804034 	movhi	r2,256
+ 800f7c8:	20800336 	bltu	r4,r2,800f7d8 <__clzsi2+0x48>
+ 800f7cc:	2008d63a 	srli	r4,r4,24
+ 800f7d0:	01400204 	movi	r5,8
+ 800f7d4:	003ff406 	br	800f7a8 <__clzsi2+0x18>
+ 800f7d8:	2008d43a 	srli	r4,r4,16
+ 800f7dc:	01400404 	movi	r5,16
+ 800f7e0:	003ff106 	br	800f7a8 <__clzsi2+0x18>
+
+0800f7e4 <alt_flash_open_dev>:
+#include "priv/alt_file.h"
+
+ALT_LLIST_HEAD(alt_flash_dev_list);
+
+alt_flash_fd* alt_flash_open_dev(const char* name)
+{
+ 800f7e4:	defffc04 	addi	sp,sp,-16
+ 800f7e8:	dfc00315 	stw	ra,12(sp)
+ 800f7ec:	df000215 	stw	fp,8(sp)
+ 800f7f0:	df000204 	addi	fp,sp,8
+ 800f7f4:	e13ffe15 	stw	r4,-8(fp)
+  alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list);
+ 800f7f8:	d1600404 	addi	r5,gp,-32752
+ 800f7fc:	e13ffe17 	ldw	r4,-8(fp)
+ 800f800:	80374040 	call	8037404 <alt_find_dev>
+ 800f804:	e0bfff15 	stw	r2,-4(fp)
+
+  if ((dev) && dev->open)
+ 800f808:	e0bfff17 	ldw	r2,-4(fp)
+ 800f80c:	10000926 	beq	r2,zero,800f834 <alt_flash_open_dev+0x50>
+ 800f810:	e0bfff17 	ldw	r2,-4(fp)
+ 800f814:	10800317 	ldw	r2,12(r2)
+ 800f818:	10000626 	beq	r2,zero,800f834 <alt_flash_open_dev+0x50>
+  {
+    return dev->open(dev, name);
+ 800f81c:	e0bfff17 	ldw	r2,-4(fp)
+ 800f820:	10800317 	ldw	r2,12(r2)
+ 800f824:	e17ffe17 	ldw	r5,-8(fp)
+ 800f828:	e13fff17 	ldw	r4,-4(fp)
+ 800f82c:	103ee83a 	callr	r2
+ 800f830:	00000106 	br	800f838 <alt_flash_open_dev+0x54>
+  }
+
+  return dev;
+ 800f834:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 800f838:	e037883a 	mov	sp,fp
+ 800f83c:	dfc00117 	ldw	ra,4(sp)
+ 800f840:	df000017 	ldw	fp,0(sp)
+ 800f844:	dec00204 	addi	sp,sp,8
+ 800f848:	f800283a 	ret
+
+0800f84c <alt_flash_close_dev>:
+
+void alt_flash_close_dev(alt_flash_fd* fd)
+{
+ 800f84c:	defffd04 	addi	sp,sp,-12
+ 800f850:	dfc00215 	stw	ra,8(sp)
+ 800f854:	df000115 	stw	fp,4(sp)
+ 800f858:	df000104 	addi	fp,sp,4
+ 800f85c:	e13fff15 	stw	r4,-4(fp)
+  if (fd && fd->close)
+ 800f860:	e0bfff17 	ldw	r2,-4(fp)
+ 800f864:	10000826 	beq	r2,zero,800f888 <alt_flash_close_dev+0x3c>
+ 800f868:	e0bfff17 	ldw	r2,-4(fp)
+ 800f86c:	10800417 	ldw	r2,16(r2)
+ 800f870:	10000526 	beq	r2,zero,800f888 <alt_flash_close_dev+0x3c>
+  {
+    fd->close(fd);
+ 800f874:	e0bfff17 	ldw	r2,-4(fp)
+ 800f878:	10800417 	ldw	r2,16(r2)
+ 800f87c:	e13fff17 	ldw	r4,-4(fp)
+ 800f880:	103ee83a 	callr	r2
+  }
+  return;
+ 800f884:	0001883a 	nop
+ 800f888:	0001883a 	nop
+}
+ 800f88c:	e037883a 	mov	sp,fp
+ 800f890:	dfc00117 	ldw	ra,4(sp)
+ 800f894:	df000017 	ldw	fp,0(sp)
+ 800f898:	dec00204 	addi	sp,sp,8
+ 800f89c:	f800283a 	ret
+
+0800f8a0 <alt_get_errno>:
+#undef errno
+
+extern int errno;
+
+static ALT_INLINE int* alt_get_errno(void)
+{
+ 800f8a0:	defffe04 	addi	sp,sp,-8
+ 800f8a4:	dfc00115 	stw	ra,4(sp)
+ 800f8a8:	df000015 	stw	fp,0(sp)
+ 800f8ac:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 800f8b0:	d0a02717 	ldw	r2,-32612(gp)
+ 800f8b4:	10000326 	beq	r2,zero,800f8c4 <alt_get_errno+0x24>
+ 800f8b8:	d0a02717 	ldw	r2,-32612(gp)
+ 800f8bc:	103ee83a 	callr	r2
+ 800f8c0:	00000106 	br	800f8c8 <alt_get_errno+0x28>
+ 800f8c4:	d0a04204 	addi	r2,gp,-32504
+}
+ 800f8c8:	e037883a 	mov	sp,fp
+ 800f8cc:	dfc00117 	ldw	ra,4(sp)
+ 800f8d0:	df000017 	ldw	fp,0(sp)
+ 800f8d4:	dec00204 	addi	sp,sp,8
+ 800f8d8:	f800283a 	ret
+
+0800f8dc <fstat>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_FSTAT (int file, struct stat *st)
+{
+ 800f8dc:	defffb04 	addi	sp,sp,-20
+ 800f8e0:	dfc00415 	stw	ra,16(sp)
+ 800f8e4:	df000315 	stw	fp,12(sp)
+ 800f8e8:	df000304 	addi	fp,sp,12
+ 800f8ec:	e13ffe15 	stw	r4,-8(fp)
+ 800f8f0:	e17ffd15 	stw	r5,-12(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 800f8f4:	e0bffe17 	ldw	r2,-8(fp)
+ 800f8f8:	10000616 	blt	r2,zero,800f914 <fstat+0x38>
+ 800f8fc:	e0bffe17 	ldw	r2,-8(fp)
+ 800f900:	10c00324 	muli	r3,r2,12
+ 800f904:	00820174 	movhi	r2,2053
+ 800f908:	10b21a04 	addi	r2,r2,-14232
+ 800f90c:	1885883a 	add	r2,r3,r2
+ 800f910:	00000106 	br	800f918 <fstat+0x3c>
+ 800f914:	0005883a 	mov	r2,zero
+ 800f918:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+ 800f91c:	e0bfff17 	ldw	r2,-4(fp)
+ 800f920:	10001026 	beq	r2,zero,800f964 <fstat+0x88>
+  {
+    /* Call the drivers fstat() function to fill out the "st" structure. */
+
+    if (fd->dev->fstat)
+ 800f924:	e0bfff17 	ldw	r2,-4(fp)
+ 800f928:	10800017 	ldw	r2,0(r2)
+ 800f92c:	10800817 	ldw	r2,32(r2)
+ 800f930:	10000726 	beq	r2,zero,800f950 <fstat+0x74>
+    {
+      return fd->dev->fstat(fd, st);
+ 800f934:	e0bfff17 	ldw	r2,-4(fp)
+ 800f938:	10800017 	ldw	r2,0(r2)
+ 800f93c:	10800817 	ldw	r2,32(r2)
+ 800f940:	e17ffd17 	ldw	r5,-12(fp)
+ 800f944:	e13fff17 	ldw	r4,-4(fp)
+ 800f948:	103ee83a 	callr	r2
+ 800f94c:	00000a06 	br	800f978 <fstat+0x9c>
+     * device.
+     */
+ 
+    else
+    {
+      st->st_mode = _IFCHR;
+ 800f950:	e0bffd17 	ldw	r2,-12(fp)
+ 800f954:	00c80004 	movi	r3,8192
+ 800f958:	10c00115 	stw	r3,4(r2)
+      return 0;
+ 800f95c:	0005883a 	mov	r2,zero
+ 800f960:	00000506 	br	800f978 <fstat+0x9c>
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+ 800f964:	800f8a00 	call	800f8a0 <alt_get_errno>
+ 800f968:	1007883a 	mov	r3,r2
+ 800f96c:	00801444 	movi	r2,81
+ 800f970:	18800015 	stw	r2,0(r3)
+    return -1;
+ 800f974:	00bfffc4 	movi	r2,-1
+  }
+}
+ 800f978:	e037883a 	mov	sp,fp
+ 800f97c:	dfc00117 	ldw	ra,4(sp)
+ 800f980:	df000017 	ldw	fp,0(sp)
+ 800f984:	dec00204 	addi	sp,sp,8
+ 800f988:	f800283a 	ret
+
+0800f98c <alt_get_errno>:
+{
+ 800f98c:	defffe04 	addi	sp,sp,-8
+ 800f990:	dfc00115 	stw	ra,4(sp)
+ 800f994:	df000015 	stw	fp,0(sp)
+ 800f998:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 800f99c:	d0a02717 	ldw	r2,-32612(gp)
+ 800f9a0:	10000326 	beq	r2,zero,800f9b0 <alt_get_errno+0x24>
+ 800f9a4:	d0a02717 	ldw	r2,-32612(gp)
+ 800f9a8:	103ee83a 	callr	r2
+ 800f9ac:	00000106 	br	800f9b4 <alt_get_errno+0x28>
+ 800f9b0:	d0a04204 	addi	r2,gp,-32504
+}
+ 800f9b4:	e037883a 	mov	sp,fp
+ 800f9b8:	dfc00117 	ldw	ra,4(sp)
+ 800f9bc:	df000017 	ldw	fp,0(sp)
+ 800f9c0:	dec00204 	addi	sp,sp,8
+ 800f9c4:	f800283a 	ret
+
+0800f9c8 <isatty>:
+ *
+ * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h
+ */
+ 
+int ALT_ISATTY (int file)
+{
+ 800f9c8:	deffea04 	addi	sp,sp,-88
+ 800f9cc:	dfc01515 	stw	ra,84(sp)
+ 800f9d0:	df001415 	stw	fp,80(sp)
+ 800f9d4:	df001404 	addi	fp,sp,80
+ 800f9d8:	e13fec15 	stw	r4,-80(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 800f9dc:	e0bfec17 	ldw	r2,-80(fp)
+ 800f9e0:	10000616 	blt	r2,zero,800f9fc <isatty+0x34>
+ 800f9e4:	e0bfec17 	ldw	r2,-80(fp)
+ 800f9e8:	10c00324 	muli	r3,r2,12
+ 800f9ec:	00820174 	movhi	r2,2053
+ 800f9f0:	10b21a04 	addi	r2,r2,-14232
+ 800f9f4:	1885883a 	add	r2,r3,r2
+ 800f9f8:	00000106 	br	800fa00 <isatty+0x38>
+ 800f9fc:	0005883a 	mov	r2,zero
+ 800fa00:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+ 800fa04:	e0bfff17 	ldw	r2,-4(fp)
+ 800fa08:	10000e26 	beq	r2,zero,800fa44 <isatty+0x7c>
+    /*
+     * If a device driver does not provide an fstat() function, then it is 
+     * treated as a terminal device by default.
+     */
+
+    if (!fd->dev->fstat)
+ 800fa0c:	e0bfff17 	ldw	r2,-4(fp)
+ 800fa10:	10800017 	ldw	r2,0(r2)
+ 800fa14:	10800817 	ldw	r2,32(r2)
+ 800fa18:	1000021e 	bne	r2,zero,800fa24 <isatty+0x5c>
+    {
+      return 1;
+ 800fa1c:	00800044 	movi	r2,1
+ 800fa20:	00000d06 	br	800fa58 <isatty+0x90>
+     * this is called so that the device can identify itself.
+     */ 
+
+    else
+    {
+      fstat (file, &stat);
+ 800fa24:	e0bfed04 	addi	r2,fp,-76
+ 800fa28:	100b883a 	mov	r5,r2
+ 800fa2c:	e13fec17 	ldw	r4,-80(fp)
+ 800fa30:	800f8dc0 	call	800f8dc <fstat>
+      return (stat.st_mode == _IFCHR) ? 1 : 0;
+ 800fa34:	e0bfee17 	ldw	r2,-72(fp)
+ 800fa38:	10880020 	cmpeqi	r2,r2,8192
+ 800fa3c:	10803fcc 	andi	r2,r2,255
+ 800fa40:	00000506 	br	800fa58 <isatty+0x90>
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+ 800fa44:	800f98c0 	call	800f98c <alt_get_errno>
+ 800fa48:	1007883a 	mov	r3,r2
+ 800fa4c:	00801444 	movi	r2,81
+ 800fa50:	18800015 	stw	r2,0(r3)
+    return 0;
+ 800fa54:	0005883a 	mov	r2,zero
+  }
+}
+ 800fa58:	e037883a 	mov	sp,fp
+ 800fa5c:	dfc00117 	ldw	ra,4(sp)
+ 800fa60:	df000017 	ldw	fp,0(sp)
+ 800fa64:	dec00204 	addi	sp,sp,8
+ 800fa68:	f800283a 	ret
+
+0800fa6c <alt_get_errno>:
+{
+ 800fa6c:	defffe04 	addi	sp,sp,-8
+ 800fa70:	dfc00115 	stw	ra,4(sp)
+ 800fa74:	df000015 	stw	fp,0(sp)
+ 800fa78:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 800fa7c:	d0a02717 	ldw	r2,-32612(gp)
+ 800fa80:	10000326 	beq	r2,zero,800fa90 <alt_get_errno+0x24>
+ 800fa84:	d0a02717 	ldw	r2,-32612(gp)
+ 800fa88:	103ee83a 	callr	r2
+ 800fa8c:	00000106 	br	800fa94 <alt_get_errno+0x28>
+ 800fa90:	d0a04204 	addi	r2,gp,-32504
+}
+ 800fa94:	e037883a 	mov	sp,fp
+ 800fa98:	dfc00117 	ldw	ra,4(sp)
+ 800fa9c:	df000017 	ldw	fp,0(sp)
+ 800faa0:	dec00204 	addi	sp,sp,8
+ 800faa4:	f800283a 	ret
+
+0800faa8 <lseek>:
+ * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h
+ *
+ */
+
+off_t ALT_LSEEK (int file, off_t ptr, int dir)
+{
+ 800faa8:	defff904 	addi	sp,sp,-28
+ 800faac:	dfc00615 	stw	ra,24(sp)
+ 800fab0:	df000515 	stw	fp,20(sp)
+ 800fab4:	df000504 	addi	fp,sp,20
+ 800fab8:	e13ffd15 	stw	r4,-12(fp)
+ 800fabc:	e17ffc15 	stw	r5,-16(fp)
+ 800fac0:	e1bffb15 	stw	r6,-20(fp)
+  alt_fd* fd;
+  off_t   rc = 0; 
+ 800fac4:	e03fff15 	stw	zero,-4(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 800fac8:	e0bffd17 	ldw	r2,-12(fp)
+ 800facc:	10000616 	blt	r2,zero,800fae8 <lseek+0x40>
+ 800fad0:	e0bffd17 	ldw	r2,-12(fp)
+ 800fad4:	10c00324 	muli	r3,r2,12
+ 800fad8:	00820174 	movhi	r2,2053
+ 800fadc:	10b21a04 	addi	r2,r2,-14232
+ 800fae0:	1885883a 	add	r2,r3,r2
+ 800fae4:	00000106 	br	800faec <lseek+0x44>
+ 800fae8:	0005883a 	mov	r2,zero
+ 800faec:	e0bffe15 	stw	r2,-8(fp)
+  
+  if (fd) 
+ 800faf0:	e0bffe17 	ldw	r2,-8(fp)
+ 800faf4:	10001026 	beq	r2,zero,800fb38 <lseek+0x90>
+    /*
+     * If the device driver provides an implementation of the lseek() function,
+     * then call that to process the request.
+     */
+ 
+    if (fd->dev->lseek)
+ 800faf8:	e0bffe17 	ldw	r2,-8(fp)
+ 800fafc:	10800017 	ldw	r2,0(r2)
+ 800fb00:	10800717 	ldw	r2,28(r2)
+ 800fb04:	10000926 	beq	r2,zero,800fb2c <lseek+0x84>
+    {
+      rc = fd->dev->lseek(fd, ptr, dir);
+ 800fb08:	e0bffe17 	ldw	r2,-8(fp)
+ 800fb0c:	10800017 	ldw	r2,0(r2)
+ 800fb10:	10800717 	ldw	r2,28(r2)
+ 800fb14:	e1bffb17 	ldw	r6,-20(fp)
+ 800fb18:	e17ffc17 	ldw	r5,-16(fp)
+ 800fb1c:	e13ffe17 	ldw	r4,-8(fp)
+ 800fb20:	103ee83a 	callr	r2
+ 800fb24:	e0bfff15 	stw	r2,-4(fp)
+ 800fb28:	00000506 	br	800fb40 <lseek+0x98>
+     * Otherwise return an error.
+     */
+
+    else
+    {
+      rc = -ENOTSUP;
+ 800fb2c:	00bfde84 	movi	r2,-134
+ 800fb30:	e0bfff15 	stw	r2,-4(fp)
+ 800fb34:	00000206 	br	800fb40 <lseek+0x98>
+    }
+  }
+  else  
+  {
+    rc = -EBADFD;
+ 800fb38:	00bfebc4 	movi	r2,-81
+ 800fb3c:	e0bfff15 	stw	r2,-4(fp)
+  }
+
+  if (rc < 0)
+ 800fb40:	e0bfff17 	ldw	r2,-4(fp)
+ 800fb44:	1000070e 	bge	r2,zero,800fb64 <lseek+0xbc>
+  {
+    ALT_ERRNO = -rc;
+ 800fb48:	800fa6c0 	call	800fa6c <alt_get_errno>
+ 800fb4c:	1007883a 	mov	r3,r2
+ 800fb50:	e0bfff17 	ldw	r2,-4(fp)
+ 800fb54:	0085c83a 	sub	r2,zero,r2
+ 800fb58:	18800015 	stw	r2,0(r3)
+    rc = -1;
+ 800fb5c:	00bfffc4 	movi	r2,-1
+ 800fb60:	e0bfff15 	stw	r2,-4(fp)
+  }
+
+  return rc;
+ 800fb64:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 800fb68:	e037883a 	mov	sp,fp
+ 800fb6c:	dfc00117 	ldw	ra,4(sp)
+ 800fb70:	df000017 	ldw	fp,0(sp)
+ 800fb74:	dec00204 	addi	sp,sp,8
+ 800fb78:	f800283a 	ret
+
+0800fb7c <alt_main>:
+ * devices/filesystems/components in the system; and call the entry point for
+ * the users application, i.e. main().
+ */
+
+void alt_main (void)
+{
+ 800fb7c:	defffb04 	addi	sp,sp,-20
+ 800fb80:	dfc00415 	stw	ra,16(sp)
+ 800fb84:	df000315 	stw	fp,12(sp)
+ 800fb88:	df000304 	addi	fp,sp,12
+#endif
+
+  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
+  /* Initialize the interrupt controller. */
+  alt_irq_init (NULL);
+ 800fb8c:	0009883a 	mov	r4,zero
+ 800fb90:	80177c80 	call	80177c8 <alt_irq_init>
+
+  /* Initialize the operating system */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n");
+  ALT_OS_INIT();
+ 800fb94:	801077c0 	call	801077c <OSInit>
+ 800fb98:	01000044 	movi	r4,1
+ 800fb9c:	80157740 	call	8015774 <OSSemCreate>
+ 800fba0:	d0a04815 	stw	r2,-32480(gp)
+ 800fba4:	01000044 	movi	r4,1
+ 800fba8:	80157740 	call	8015774 <OSSemCreate>
+ 800fbac:	d0a04a15 	stw	r2,-32472(gp)
+ 800fbb0:	d0a08b04 	addi	r2,gp,-32212
+ 800fbb4:	e0bffe15 	stw	r2,-8(fp)
+ 800fbb8:	00800044 	movi	r2,1
+ 800fbbc:	e0bffd8d 	sth	r2,-10(fp)
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, 
+              INT16U value)
+{
+  *sem = OSSemCreate (value);
+ 800fbc0:	e0bffd8b 	ldhu	r2,-10(fp)
+ 800fbc4:	1009883a 	mov	r4,r2
+ 800fbc8:	80157740 	call	8015774 <OSSemCreate>
+ 800fbcc:	1007883a 	mov	r3,r2
+ 800fbd0:	e0bffe17 	ldw	r2,-8(fp)
+ 800fbd4:	10c00015 	stw	r3,0(r2)
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
+  ALT_SEM_CREATE (&alt_fd_list_lock, 1);
+
+  /* Initialize the device drivers/software components. */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
+  alt_sys_init();
+ 800fbd8:	80178000 	call	8017800 <alt_sys_init>
+   * devices be present (not equal to /dev/null) and if direct drivers
+   * aren't being used.
+   */
+
+    ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n");
+    alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR);
+ 800fbdc:	01820134 	movhi	r6,2052
+ 800fbe0:	319dc904 	addi	r6,r6,30500
+ 800fbe4:	01420134 	movhi	r5,2052
+ 800fbe8:	295dc904 	addi	r5,r5,30500
+ 800fbec:	01020134 	movhi	r4,2052
+ 800fbf0:	211dc904 	addi	r4,r4,30500
+ 800fbf4:	80377d80 	call	80377d8 <alt_io_redirect>
+  /* 
+   * Call the C++ constructors 
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n");
+  _do_ctors ();
+ 800fbf8:	80373440 	call	8037344 <_do_ctors>
+   * redefined as _exit()). This is in the interest of reducing code footprint,
+   * in that the atexit() overhead is removed when it's not needed.
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n");
+  atexit (_do_dtors);
+ 800fbfc:	010200f4 	movhi	r4,2051
+ 800fc00:	211ce904 	addi	r4,r4,29604
+ 800fc04:	8042a900 	call	8042a90 <atexit>
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");
+
+#ifdef ALT_NO_EXIT
+  main (alt_argc, alt_argv, alt_envp);
+#else
+  result = main (alt_argc, alt_argv, alt_envp);
+ 800fc08:	d0a04417 	ldw	r2,-32496(gp)
+ 800fc0c:	d0e04517 	ldw	r3,-32492(gp)
+ 800fc10:	d1204617 	ldw	r4,-32488(gp)
+ 800fc14:	200d883a 	mov	r6,r4
+ 800fc18:	180b883a 	mov	r5,r3
+ 800fc1c:	1009883a 	mov	r4,r2
+ 800fc20:	80011780 	call	8001178 <main>
+ 800fc24:	e0bfff15 	stw	r2,-4(fp)
+  close(STDOUT_FILENO);
+ 800fc28:	01000044 	movi	r4,1
+ 800fc2c:	8022a600 	call	8022a60 <close>
+  exit (result);
+ 800fc30:	e13fff17 	ldw	r4,-4(fp)
+ 800fc34:	8042abc0 	call	8042abc <exit>
+
+0800fc38 <sbrk>:
+#endif
+ 
+caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function ));
+
+caddr_t ALT_SBRK (int incr)
+{ 
+ 800fc38:	defff904 	addi	sp,sp,-28
+ 800fc3c:	df000615 	stw	fp,24(sp)
+ 800fc40:	df000604 	addi	fp,sp,24
+ 800fc44:	e13ffa15 	stw	r4,-24(fp)
+  NIOS2_READ_STATUS (context);
+ 800fc48:	0005303a 	rdctl	r2,status
+ 800fc4c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 800fc50:	e0fffd17 	ldw	r3,-12(fp)
+ 800fc54:	00bfff84 	movi	r2,-2
+ 800fc58:	1884703a 	and	r2,r3,r2
+ 800fc5c:	1001703a 	wrctl	status,r2
+  return context;
+ 800fc60:	e0bffd17 	ldw	r2,-12(fp)
+  alt_irq_context context;
+  char *prev_heap_end; 
+
+  context = alt_irq_disable_all();
+ 800fc64:	e0bfff15 	stw	r2,-4(fp)
+
+  /* Always return data aligned on a word boundary */
+  heap_end = (char *)(((unsigned int)heap_end + 3) & ~3);
+ 800fc68:	d0a00617 	ldw	r2,-32744(gp)
+ 800fc6c:	10c000c4 	addi	r3,r2,3
+ 800fc70:	00bfff04 	movi	r2,-4
+ 800fc74:	1884703a 	and	r2,r3,r2
+ 800fc78:	d0a00615 	stw	r2,-32744(gp)
+  if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) {
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+  }
+#else
+  if ((heap_end + incr) > __alt_heap_limit) {
+ 800fc7c:	d0e00617 	ldw	r3,-32744(gp)
+ 800fc80:	e0bffa17 	ldw	r2,-24(fp)
+ 800fc84:	1887883a 	add	r3,r3,r2
+ 800fc88:	00840034 	movhi	r2,4096
+ 800fc8c:	10800004 	addi	r2,r2,0
+ 800fc90:	10c0062e 	bgeu	r2,r3,800fcac <sbrk+0x74>
+ 800fc94:	e0bfff17 	ldw	r2,-4(fp)
+ 800fc98:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 800fc9c:	e0bffc17 	ldw	r2,-16(fp)
+ 800fca0:	1001703a 	wrctl	status,r2
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+ 800fca4:	00bfffc4 	movi	r2,-1
+ 800fca8:	00000b06 	br	800fcd8 <sbrk+0xa0>
+  }
+#endif
+
+  prev_heap_end = heap_end; 
+ 800fcac:	d0a00617 	ldw	r2,-32744(gp)
+ 800fcb0:	e0bffe15 	stw	r2,-8(fp)
+  heap_end += incr; 
+ 800fcb4:	d0e00617 	ldw	r3,-32744(gp)
+ 800fcb8:	e0bffa17 	ldw	r2,-24(fp)
+ 800fcbc:	1885883a 	add	r2,r3,r2
+ 800fcc0:	d0a00615 	stw	r2,-32744(gp)
+ 800fcc4:	e0bfff17 	ldw	r2,-4(fp)
+ 800fcc8:	e0bffb15 	stw	r2,-20(fp)
+ 800fccc:	e0bffb17 	ldw	r2,-20(fp)
+ 800fcd0:	1001703a 	wrctl	status,r2
+
+#endif
+
+  alt_irq_enable_all(context);
+
+  return (caddr_t) prev_heap_end; 
+ 800fcd4:	e0bffe17 	ldw	r2,-8(fp)
+} 
+ 800fcd8:	e037883a 	mov	sp,fp
+ 800fcdc:	df000017 	ldw	fp,0(sp)
+ 800fce0:	dec00104 	addi	sp,sp,4
+ 800fce4:	f800283a 	ret
+
+0800fce8 <__env_lock>:
+/*
+ *
+ */
+
+void __env_lock ( struct _reent *_r )
+{
+ 800fce8:	deffdf04 	addi	sp,sp,-132
+ 800fcec:	dfc02015 	stw	ra,128(sp)
+ 800fcf0:	df001f15 	stw	fp,124(sp)
+ 800fcf4:	df001f04 	addi	fp,sp,124
+ 800fcf8:	e13fe115 	stw	r4,-124(fp)
+  INT8U err;
+  int id;
+
+  /* use our priority as a task id */
+
+  err = OSTaskQuery( OS_PRIO_SELF, &tcb );
+ 800fcfc:	e0bfe404 	addi	r2,fp,-112
+ 800fd00:	100b883a 	mov	r5,r2
+ 800fd04:	01003fc4 	movi	r4,255
+ 800fd08:	80172200 	call	8017220 <OSTaskQuery>
+ 800fd0c:	e0bfe245 	stb	r2,-119(fp)
+  if (err != OS_NO_ERR)
+ 800fd10:	e0bfe243 	ldbu	r2,-119(fp)
+ 800fd14:	10803fcc 	andi	r2,r2,255
+ 800fd18:	10001e1e 	bne	r2,zero,800fd94 <__env_lock+0xac>
+    return;
+
+  id = tcb.OSTCBPrio;
+ 800fd1c:	e0bff083 	ldbu	r2,-62(fp)
+ 800fd20:	10803fcc 	andi	r2,r2,255
+ 800fd24:	e0bfff15 	stw	r2,-4(fp)
+   
+  /* see if we own the environment already */
+
+  OSSemQuery( alt_envsem, &semdata );
+ 800fd28:	d0a04817 	ldw	r2,-32480(gp)
+ 800fd2c:	e0ffe284 	addi	r3,fp,-118
+ 800fd30:	180b883a 	mov	r5,r3
+ 800fd34:	1009883a 	mov	r4,r2
+ 800fd38:	8015e840 	call	8015e84 <OSSemQuery>
+  if( semdata.OSEventGrp && id == lockid ) 
+ 800fd3c:	e0bfe3c3 	ldbu	r2,-113(fp)
+ 800fd40:	10803fcc 	andi	r2,r2,255
+ 800fd44:	10000726 	beq	r2,zero,800fd64 <__env_lock+0x7c>
+ 800fd48:	d0a00717 	ldw	r2,-32740(gp)
+ 800fd4c:	e0ffff17 	ldw	r3,-4(fp)
+ 800fd50:	1880041e 	bne	r3,r2,800fd64 <__env_lock+0x7c>
+  {
+    /* we do; just count the recursion */
+
+    locks++;
+ 800fd54:	d0a04717 	ldw	r2,-32484(gp)
+ 800fd58:	10800044 	addi	r2,r2,1
+ 800fd5c:	d0a04715 	stw	r2,-32484(gp)
+ 800fd60:	00000a06 	br	800fd8c <__env_lock+0xa4>
+  }
+  else 
+  {
+    /* wait on the other task to yield, then claim ownership */
+
+    OSSemPend( alt_envsem, 0, &err );
+ 800fd64:	d0a04817 	ldw	r2,-32480(gp)
+ 800fd68:	e0ffe244 	addi	r3,fp,-119
+ 800fd6c:	180d883a 	mov	r6,r3
+ 800fd70:	000b883a 	mov	r5,zero
+ 800fd74:	1009883a 	mov	r4,r2
+ 800fd78:	8015a600 	call	8015a60 <OSSemPend>
+    locks  = 1;
+ 800fd7c:	00800044 	movi	r2,1
+ 800fd80:	d0a04715 	stw	r2,-32484(gp)
+    lockid = id;
+ 800fd84:	e0bfff17 	ldw	r2,-4(fp)
+ 800fd88:	d0a00715 	stw	r2,-32740(gp)
+  }
+
+#endif /* OS_THREAD_SAFE_NEWLIB */
+  return;
+ 800fd8c:	0001883a 	nop
+ 800fd90:	00000106 	br	800fd98 <__env_lock+0xb0>
+    return;
+ 800fd94:	0001883a 	nop
+}
+ 800fd98:	e037883a 	mov	sp,fp
+ 800fd9c:	dfc00117 	ldw	ra,4(sp)
+ 800fda0:	df000017 	ldw	fp,0(sp)
+ 800fda4:	dec00204 	addi	sp,sp,8
+ 800fda8:	f800283a 	ret
+
+0800fdac <__env_unlock>:
+/*
+ *
+ */
+
+void __env_unlock ( struct _reent *_r )
+{
+ 800fdac:	defffd04 	addi	sp,sp,-12
+ 800fdb0:	dfc00215 	stw	ra,8(sp)
+ 800fdb4:	df000115 	stw	fp,4(sp)
+ 800fdb8:	df000104 	addi	fp,sp,4
+ 800fdbc:	e13fff15 	stw	r4,-4(fp)
+#if OS_THREAD_SAFE_NEWLIB
+  if (locks == 0)
+ 800fdc0:	d0a04717 	ldw	r2,-32484(gp)
+ 800fdc4:	10000b26 	beq	r2,zero,800fdf4 <__env_unlock+0x48>
+   /* 
+    * release the environment once the number of locks == the number 
+    * of unlocks 
+    */
+
+  if( (--locks) == 0 ) 
+ 800fdc8:	d0a04717 	ldw	r2,-32484(gp)
+ 800fdcc:	10bfffc4 	addi	r2,r2,-1
+ 800fdd0:	d0a04715 	stw	r2,-32484(gp)
+ 800fdd4:	d0a04717 	ldw	r2,-32484(gp)
+ 800fdd8:	1000071e 	bne	r2,zero,800fdf8 <__env_unlock+0x4c>
+  {
+    lockid = -1;
+ 800fddc:	00bfffc4 	movi	r2,-1
+ 800fde0:	d0a00715 	stw	r2,-32740(gp)
+    OSSemPost( alt_envsem );
+ 800fde4:	d0a04817 	ldw	r2,-32480(gp)
+ 800fde8:	1009883a 	mov	r4,r2
+ 800fdec:	8015d840 	call	8015d84 <OSSemPost>
+ 800fdf0:	00000106 	br	800fdf8 <__env_unlock+0x4c>
+    return;
+ 800fdf4:	0001883a 	nop
+  }
+#endif /* OS_THREAD_SAFE_NEWLIB */
+}
+ 800fdf8:	e037883a 	mov	sp,fp
+ 800fdfc:	dfc00117 	ldw	ra,4(sp)
+ 800fe00:	df000017 	ldw	fp,0(sp)
+ 800fe04:	dec00204 	addi	sp,sp,8
+ 800fe08:	f800283a 	ret
+
+0800fe0c <__malloc_lock>:
+/*
+ *
+ */
+
+void __malloc_lock ( struct _reent *_r )
+{
+ 800fe0c:	deffdb04 	addi	sp,sp,-148
+ 800fe10:	dfc02415 	stw	ra,144(sp)
+ 800fe14:	df002315 	stw	fp,140(sp)
+ 800fe18:	df002304 	addi	fp,sp,140
+ 800fe1c:	e13fdd15 	stw	r4,-140(fp)
+  OS_TCB tcb;
+  OS_SEM_DATA semdata;
+  INT8U err;
+  int id;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 800fe20:	e03fff15 	stw	zero,-4(fp)
+#endif  
+  
+  if (OSRunning != OS_TRUE)
+ 800fe24:	d0a04b43 	ldbu	r2,-32467(gp)
+ 800fe28:	10803fcc 	andi	r2,r2,255
+ 800fe2c:	10800060 	cmpeqi	r2,r2,1
+ 800fe30:	10003626 	beq	r2,zero,800ff0c <__malloc_lock+0x100>
+      return;
+
+  /* use our priority as a task id */
+
+  err = OSTaskQuery( OS_PRIO_SELF, &tcb );
+ 800fe34:	e0bfe004 	addi	r2,fp,-128
+ 800fe38:	100b883a 	mov	r5,r2
+ 800fe3c:	01003fc4 	movi	r4,255
+ 800fe40:	80172200 	call	8017220 <OSTaskQuery>
+ 800fe44:	e0bfde45 	stb	r2,-135(fp)
+  if (err != OS_NO_ERR)
+ 800fe48:	e0bfde43 	ldbu	r2,-135(fp)
+ 800fe4c:	10803fcc 	andi	r2,r2,255
+ 800fe50:	1000301e 	bne	r2,zero,800ff14 <__malloc_lock+0x108>
+    return;
+
+  id = tcb.OSTCBPrio;
+ 800fe54:	e0bfec83 	ldbu	r2,-78(fp)
+ 800fe58:	10803fcc 	andi	r2,r2,255
+ 800fe5c:	e0bffe15 	stw	r2,-8(fp)
+   
+  /* see if we own the heap already */
+
+  OSSemQuery( alt_heapsem, &semdata );
+ 800fe60:	d0a04a17 	ldw	r2,-32472(gp)
+ 800fe64:	e0ffde84 	addi	r3,fp,-134
+ 800fe68:	180b883a 	mov	r5,r3
+ 800fe6c:	1009883a 	mov	r4,r2
+ 800fe70:	8015e840 	call	8015e84 <OSSemQuery>
+  NIOS2_READ_STATUS (context);
+ 800fe74:	0005303a 	rdctl	r2,status
+ 800fe78:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 800fe7c:	e0fffd17 	ldw	r3,-12(fp)
+ 800fe80:	00bfff84 	movi	r2,-2
+ 800fe84:	1884703a 	and	r2,r3,r2
+ 800fe88:	1001703a 	wrctl	status,r2
+  return context;
+ 800fe8c:	e0bffd17 	ldw	r2,-12(fp)
+  
+  OS_ENTER_CRITICAL();
+ 800fe90:	e0bfff15 	stw	r2,-4(fp)
+
+  if( !semdata.OSCnt && id == lockid ) 
+ 800fe94:	e0bfde8b 	ldhu	r2,-134(fp)
+ 800fe98:	10bfffcc 	andi	r2,r2,65535
+ 800fe9c:	10000b1e 	bne	r2,zero,800fecc <__malloc_lock+0xc0>
+ 800fea0:	d0a00817 	ldw	r2,-32736(gp)
+ 800fea4:	e0fffe17 	ldw	r3,-8(fp)
+ 800fea8:	1880081e 	bne	r3,r2,800fecc <__malloc_lock+0xc0>
+  {
+    /* we do; just count the recursion */
+    locks++;
+ 800feac:	d0a04917 	ldw	r2,-32476(gp)
+ 800feb0:	10800044 	addi	r2,r2,1
+ 800feb4:	d0a04915 	stw	r2,-32476(gp)
+ 800feb8:	e0bfff17 	ldw	r2,-4(fp)
+ 800febc:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 800fec0:	e0bffc17 	ldw	r2,-16(fp)
+ 800fec4:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+ 800fec8:	00000e06 	br	800ff04 <__malloc_lock+0xf8>
+ 800fecc:	e0bfff17 	ldw	r2,-4(fp)
+ 800fed0:	e0bffb15 	stw	r2,-20(fp)
+ 800fed4:	e0bffb17 	ldw	r2,-20(fp)
+ 800fed8:	1001703a 	wrctl	status,r2
+  else 
+  {
+    /* wait on the other task to yield the heap, then claim ownership of it */
+    OS_EXIT_CRITICAL();
+
+    OSSemPend( alt_heapsem, 0, &err );
+ 800fedc:	d0a04a17 	ldw	r2,-32472(gp)
+ 800fee0:	e0ffde44 	addi	r3,fp,-135
+ 800fee4:	180d883a 	mov	r6,r3
+ 800fee8:	000b883a 	mov	r5,zero
+ 800feec:	1009883a 	mov	r4,r2
+ 800fef0:	8015a600 	call	8015a60 <OSSemPend>
+    locks  = 1;
+ 800fef4:	00800044 	movi	r2,1
+ 800fef8:	d0a04915 	stw	r2,-32476(gp)
+    lockid = id;
+ 800fefc:	e0bffe17 	ldw	r2,-8(fp)
+ 800ff00:	d0a00815 	stw	r2,-32736(gp)
+  }
+
+#endif /* OS_THREAD_SAFE_NEWLIB */
+  return;
+ 800ff04:	0001883a 	nop
+ 800ff08:	00000306 	br	800ff18 <__malloc_lock+0x10c>
+      return;
+ 800ff0c:	0001883a 	nop
+ 800ff10:	00000106 	br	800ff18 <__malloc_lock+0x10c>
+    return;
+ 800ff14:	0001883a 	nop
+}
+ 800ff18:	e037883a 	mov	sp,fp
+ 800ff1c:	dfc00117 	ldw	ra,4(sp)
+ 800ff20:	df000017 	ldw	fp,0(sp)
+ 800ff24:	dec00204 	addi	sp,sp,8
+ 800ff28:	f800283a 	ret
+
+0800ff2c <__malloc_unlock>:
+/*
+ *
+ */
+
+void __malloc_unlock ( struct _reent *_r )
+{
+ 800ff2c:	defff804 	addi	sp,sp,-32
+ 800ff30:	dfc00715 	stw	ra,28(sp)
+ 800ff34:	df000615 	stw	fp,24(sp)
+ 800ff38:	df000604 	addi	fp,sp,24
+ 800ff3c:	e13ffa15 	stw	r4,-24(fp)
+#if OS_THREAD_SAFE_NEWLIB
+
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 800ff40:	e03fff15 	stw	zero,-4(fp)
+#endif 
+
+  if (OSRunning != OS_TRUE)
+ 800ff44:	d0a04b43 	ldbu	r2,-32467(gp)
+ 800ff48:	10803fcc 	andi	r2,r2,255
+ 800ff4c:	10800060 	cmpeqi	r2,r2,1
+ 800ff50:	10002326 	beq	r2,zero,800ffe0 <__malloc_unlock+0xb4>
+  NIOS2_READ_STATUS (context);
+ 800ff54:	0005303a 	rdctl	r2,status
+ 800ff58:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 800ff5c:	e0fffe17 	ldw	r3,-8(fp)
+ 800ff60:	00bfff84 	movi	r2,-2
+ 800ff64:	1884703a 	and	r2,r3,r2
+ 800ff68:	1001703a 	wrctl	status,r2
+  return context;
+ 800ff6c:	e0bffe17 	ldw	r2,-8(fp)
+      return;
+
+  OS_ENTER_CRITICAL();
+ 800ff70:	e0bfff15 	stw	r2,-4(fp)
+  if (locks == 0)
+ 800ff74:	d0a04917 	ldw	r2,-32476(gp)
+ 800ff78:	1000051e 	bne	r2,zero,800ff90 <__malloc_unlock+0x64>
+ 800ff7c:	e0bfff17 	ldw	r2,-4(fp)
+ 800ff80:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 800ff84:	e0bffd17 	ldw	r2,-12(fp)
+ 800ff88:	1001703a 	wrctl	status,r2
+  {
+      OS_EXIT_CRITICAL();
+      return;
+ 800ff8c:	00001506 	br	800ffe4 <__malloc_unlock+0xb8>
+  }
+
+  /* release the heap once the number of locks == the number of unlocks */
+  if( (--locks) == 0 ) 
+ 800ff90:	d0a04917 	ldw	r2,-32476(gp)
+ 800ff94:	10bfffc4 	addi	r2,r2,-1
+ 800ff98:	d0a04915 	stw	r2,-32476(gp)
+ 800ff9c:	d0a04917 	ldw	r2,-32476(gp)
+ 800ffa0:	10000a1e 	bne	r2,zero,800ffcc <__malloc_unlock+0xa0>
+  {
+    lockid = -1;
+ 800ffa4:	00bfffc4 	movi	r2,-1
+ 800ffa8:	d0a00815 	stw	r2,-32736(gp)
+ 800ffac:	e0bfff17 	ldw	r2,-4(fp)
+ 800ffb0:	e0bffc15 	stw	r2,-16(fp)
+ 800ffb4:	e0bffc17 	ldw	r2,-16(fp)
+ 800ffb8:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    OSSemPost( alt_heapsem );
+ 800ffbc:	d0a04a17 	ldw	r2,-32472(gp)
+ 800ffc0:	1009883a 	mov	r4,r2
+ 800ffc4:	8015d840 	call	8015d84 <OSSemPost>
+ 800ffc8:	00000606 	br	800ffe4 <__malloc_unlock+0xb8>
+ 800ffcc:	e0bfff17 	ldw	r2,-4(fp)
+ 800ffd0:	e0bffb15 	stw	r2,-20(fp)
+ 800ffd4:	e0bffb17 	ldw	r2,-20(fp)
+ 800ffd8:	1001703a 	wrctl	status,r2
+ 800ffdc:	00000106 	br	800ffe4 <__malloc_unlock+0xb8>
+      return;
+ 800ffe0:	0001883a 	nop
+  {
+      OS_EXIT_CRITICAL();
+  }
+  
+#endif /* OS_THREAD_SAFE_NEWLIB */
+}
+ 800ffe4:	e037883a 	mov	sp,fp
+ 800ffe8:	dfc00117 	ldw	ra,4(sp)
+ 800ffec:	df000017 	ldw	fp,0(sp)
+ 800fff0:	dec00204 	addi	sp,sp,8
+ 800fff4:	f800283a 	ret
+
+0800fff8 <OSEventNameGet>:
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1)
+INT8U  OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr)
+{
+ 800fff8:	defff704 	addi	sp,sp,-36
+ 800fffc:	dfc00815 	stw	ra,32(sp)
+ 8010000:	df000715 	stw	fp,28(sp)
+ 8010004:	df000704 	addi	fp,sp,28
+ 8010008:	e13ffb15 	stw	r4,-20(fp)
+ 801000c:	e17ffa15 	stw	r5,-24(fp)
+ 8010010:	e1bff915 	stw	r6,-28(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8010014:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 8010018:	d0a05703 	ldbu	r2,-32420(gp)
+ 801001c:	10803fcc 	andi	r2,r2,255
+ 8010020:	10000526 	beq	r2,zero,8010038 <OSEventNameGet+0x40>
+        *perr  = OS_ERR_NAME_GET_ISR;
+ 8010024:	e0bff917 	ldw	r2,-28(fp)
+ 8010028:	00c00444 	movi	r3,17
+ 801002c:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8010030:	0005883a 	mov	r2,zero
+ 8010034:	00002106 	br	80100bc <OSEventNameGet+0xc4>
+    }
+    switch (pevent->OSEventType) {
+ 8010038:	e0bffb17 	ldw	r2,-20(fp)
+ 801003c:	10800003 	ldbu	r2,0(r2)
+ 8010040:	10803fcc 	andi	r2,r2,255
+ 8010044:	10bfffc4 	addi	r2,r2,-1
+ 8010048:	10800128 	cmpgeui	r2,r2,4
+ 801004c:	10000526 	beq	r2,zero,8010064 <OSEventNameGet+0x6c>
+        case OS_EVENT_TYPE_MBOX:
+        case OS_EVENT_TYPE_Q:
+             break;
+
+        default:
+             *perr = OS_ERR_EVENT_TYPE;
+ 8010050:	e0bff917 	ldw	r2,-28(fp)
+ 8010054:	00c00044 	movi	r3,1
+ 8010058:	10c00005 	stb	r3,0(r2)
+             return (0);
+ 801005c:	0005883a 	mov	r2,zero
+ 8010060:	00001606 	br	80100bc <OSEventNameGet+0xc4>
+             break;
+ 8010064:	0001883a 	nop
+  NIOS2_READ_STATUS (context);
+ 8010068:	0005303a 	rdctl	r2,status
+ 801006c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010070:	e0fffc17 	ldw	r3,-16(fp)
+ 8010074:	00bfff84 	movi	r2,-2
+ 8010078:	1884703a 	and	r2,r3,r2
+ 801007c:	1001703a 	wrctl	status,r2
+  return context;
+ 8010080:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8010084:	e0bfff15 	stw	r2,-4(fp)
+    len   = OS_StrCopy(pname, pevent->OSEventName);   /* Copy name from OS_EVENT                       */
+ 8010088:	e0bffb17 	ldw	r2,-20(fp)
+ 801008c:	10800384 	addi	r2,r2,14
+ 8010090:	100b883a 	mov	r5,r2
+ 8010094:	e13ffa17 	ldw	r4,-24(fp)
+ 8010098:	80117a00 	call	80117a0 <OS_StrCopy>
+ 801009c:	e0bffec5 	stb	r2,-5(fp)
+ 80100a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80100a4:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80100a8:	e0bffd17 	ldw	r2,-12(fp)
+ 80100ac:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 80100b0:	e0bff917 	ldw	r2,-28(fp)
+ 80100b4:	10000005 	stb	zero,0(r2)
+    return (len);
+ 80100b8:	e0bffec3 	ldbu	r2,-5(fp)
+}
+ 80100bc:	e037883a 	mov	sp,fp
+ 80100c0:	dfc00117 	ldw	ra,4(sp)
+ 80100c4:	df000017 	ldw	fp,0(sp)
+ 80100c8:	dec00204 	addi	sp,sp,8
+ 80100cc:	f800283a 	ret
+
+080100d0 <OSEventNameSet>:
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1)
+void  OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr)
+{
+ 80100d0:	defff604 	addi	sp,sp,-40
+ 80100d4:	dfc00915 	stw	ra,36(sp)
+ 80100d8:	df000815 	stw	fp,32(sp)
+ 80100dc:	df000804 	addi	fp,sp,32
+ 80100e0:	e13ffa15 	stw	r4,-24(fp)
+ 80100e4:	e17ff915 	stw	r5,-28(fp)
+ 80100e8:	e1bff815 	stw	r6,-32(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 80100ec:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 80100f0:	d0a05703 	ldbu	r2,-32420(gp)
+ 80100f4:	10803fcc 	andi	r2,r2,255
+ 80100f8:	10000426 	beq	r2,zero,801010c <OSEventNameSet+0x3c>
+        *perr = OS_ERR_NAME_SET_ISR;
+ 80100fc:	e0bff817 	ldw	r2,-32(fp)
+ 8010100:	00c00484 	movi	r3,18
+ 8010104:	10c00005 	stb	r3,0(r2)
+        return;
+ 8010108:	00002c06 	br	80101bc <OSEventNameSet+0xec>
+    }
+    switch (pevent->OSEventType) {
+ 801010c:	e0bffa17 	ldw	r2,-24(fp)
+ 8010110:	10800003 	ldbu	r2,0(r2)
+ 8010114:	10803fcc 	andi	r2,r2,255
+ 8010118:	10bfffc4 	addi	r2,r2,-1
+ 801011c:	10800128 	cmpgeui	r2,r2,4
+ 8010120:	10000426 	beq	r2,zero,8010134 <OSEventNameSet+0x64>
+        case OS_EVENT_TYPE_MBOX:
+        case OS_EVENT_TYPE_Q:
+             break;
+
+        default:
+             *perr = OS_ERR_EVENT_TYPE;
+ 8010124:	e0bff817 	ldw	r2,-32(fp)
+ 8010128:	00c00044 	movi	r3,1
+ 801012c:	10c00005 	stb	r3,0(r2)
+             return;
+ 8010130:	00002206 	br	80101bc <OSEventNameSet+0xec>
+             break;
+ 8010134:	0001883a 	nop
+  NIOS2_READ_STATUS (context);
+ 8010138:	0005303a 	rdctl	r2,status
+ 801013c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010140:	e0fffd17 	ldw	r3,-12(fp)
+ 8010144:	00bfff84 	movi	r2,-2
+ 8010148:	1884703a 	and	r2,r3,r2
+ 801014c:	1001703a 	wrctl	status,r2
+  return context;
+ 8010150:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8010154:	e0bfff15 	stw	r2,-4(fp)
+    len = OS_StrLen(pname);                           /* Can we fit the string in the storage area?    */
+ 8010158:	e13ff917 	ldw	r4,-28(fp)
+ 801015c:	80118140 	call	8011814 <OS_StrLen>
+ 8010160:	e0bffec5 	stb	r2,-5(fp)
+    if (len > (OS_EVENT_NAME_SIZE - 1)) {             /* No                                            */
+ 8010164:	e0bffec3 	ldbu	r2,-5(fp)
+ 8010168:	10800830 	cmpltui	r2,r2,32
+ 801016c:	1000081e 	bne	r2,zero,8010190 <OSEventNameSet+0xc0>
+ 8010170:	e0bfff17 	ldw	r2,-4(fp)
+ 8010174:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8010178:	e0bffc17 	ldw	r2,-16(fp)
+ 801017c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_NAME_TOO_LONG;
+ 8010180:	e0bff817 	ldw	r2,-32(fp)
+ 8010184:	00c002c4 	movi	r3,11
+ 8010188:	10c00005 	stb	r3,0(r2)
+        return;
+ 801018c:	00000b06 	br	80101bc <OSEventNameSet+0xec>
+    }
+    (void)OS_StrCopy(pevent->OSEventName, pname);     /* Yes, copy name to the event control block     */
+ 8010190:	e0bffa17 	ldw	r2,-24(fp)
+ 8010194:	10800384 	addi	r2,r2,14
+ 8010198:	e17ff917 	ldw	r5,-28(fp)
+ 801019c:	1009883a 	mov	r4,r2
+ 80101a0:	80117a00 	call	80117a0 <OS_StrCopy>
+ 80101a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80101a8:	e0bffb15 	stw	r2,-20(fp)
+ 80101ac:	e0bffb17 	ldw	r2,-20(fp)
+ 80101b0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 80101b4:	e0bff817 	ldw	r2,-32(fp)
+ 80101b8:	10000005 	stb	zero,0(r2)
+}
+ 80101bc:	e037883a 	mov	sp,fp
+ 80101c0:	dfc00117 	ldw	ra,4(sp)
+ 80101c4:	df000017 	ldw	fp,0(sp)
+ 80101c8:	dec00204 	addi	sp,sp,8
+ 80101cc:	f800283a 	ret
+
+080101d0 <OSEventPendMulti>:
+*********************************************************************************************************
+*/
+/*$PAGE*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+INT16U  OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr)
+{
+ 80101d0:	deffed04 	addi	sp,sp,-76
+ 80101d4:	dfc01215 	stw	ra,72(sp)
+ 80101d8:	df001115 	stw	fp,68(sp)
+ 80101dc:	df001104 	addi	fp,sp,68
+ 80101e0:	e13ff215 	stw	r4,-56(fp)
+ 80101e4:	e17ff115 	stw	r5,-60(fp)
+ 80101e8:	e1bff015 	stw	r6,-64(fp)
+ 80101ec:	3805883a 	mov	r2,r7
+ 80101f0:	e0bfef0d 	sth	r2,-68(fp)
+#endif
+    BOOLEAN     events_rdy;
+    INT16U      events_rdy_nbr;
+    INT8U       events_stat;
+#if (OS_CRITICAL_METHOD == 3)                           /* Allocate storage for CPU status register    */
+    OS_CPU_SR   cpu_sr = 0;
+ 80101f4:	e03ffb15 	stw	zero,-20(fp)
+       *perr =  OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+
+   *pevents_rdy = (OS_EVENT *)0;                        /* Init array to NULL in case of errors        */
+ 80101f8:	e0bff117 	ldw	r2,-60(fp)
+ 80101fc:	10000015 	stw	zero,0(r2)
+
+    pevents     =  pevents_pend;
+ 8010200:	e0bff217 	ldw	r2,-56(fp)
+ 8010204:	e0bfff15 	stw	r2,-4(fp)
+    pevent      = *pevents;
+ 8010208:	e0bfff17 	ldw	r2,-4(fp)
+ 801020c:	10800017 	ldw	r2,0(r2)
+ 8010210:	e0bffe15 	stw	r2,-8(fp)
+    while  (pevent != (OS_EVENT *)0) {
+ 8010214:	00001906 	br	801027c <OSEventPendMulti+0xac>
+        switch (pevent->OSEventType) {                  /* Validate event block types                  */
+ 8010218:	e0bffe17 	ldw	r2,-8(fp)
+ 801021c:	10800003 	ldbu	r2,0(r2)
+ 8010220:	10803fcc 	andi	r2,r2,255
+ 8010224:	10c000a0 	cmpeqi	r3,r2,2
+ 8010228:	1800091e 	bne	r3,zero,8010250 <OSEventPendMulti+0x80>
+ 801022c:	10c000e0 	cmpeqi	r3,r2,3
+ 8010230:	1800091e 	bne	r3,zero,8010258 <OSEventPendMulti+0x88>
+ 8010234:	10800060 	cmpeqi	r2,r2,1
+ 8010238:	1000091e 	bne	r2,zero,8010260 <OSEventPendMulti+0x90>
+#endif
+
+            case OS_EVENT_TYPE_MUTEX:                                            
+            case OS_EVENT_TYPE_FLAG:
+            default:           
+                *perr = OS_ERR_EVENT_TYPE;
+ 801023c:	e0800217 	ldw	r2,8(fp)
+ 8010240:	00c00044 	movi	r3,1
+ 8010244:	10c00005 	stb	r3,0(r2)
+                 return (0);
+ 8010248:	0005883a 	mov	r2,zero
+ 801024c:	00014606 	br	8010768 <OSEventPendMulti+0x598>
+                 break;
+ 8010250:	0001883a 	nop
+ 8010254:	00000306 	br	8010264 <OSEventPendMulti+0x94>
+                 break;
+ 8010258:	0001883a 	nop
+ 801025c:	00000106 	br	8010264 <OSEventPendMulti+0x94>
+                 break;
+ 8010260:	0001883a 	nop
+        }
+        pevents++;
+ 8010264:	e0bfff17 	ldw	r2,-4(fp)
+ 8010268:	10800104 	addi	r2,r2,4
+ 801026c:	e0bfff15 	stw	r2,-4(fp)
+        pevent = *pevents;
+ 8010270:	e0bfff17 	ldw	r2,-4(fp)
+ 8010274:	10800017 	ldw	r2,0(r2)
+ 8010278:	e0bffe15 	stw	r2,-8(fp)
+    while  (pevent != (OS_EVENT *)0) {
+ 801027c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010280:	103fe51e 	bne	r2,zero,8010218 <OSEventPendMulti+0x48>
+    }
+
+    if (OSIntNesting  > 0) {                            /* See if called from ISR ...                  */
+ 8010284:	d0a05703 	ldbu	r2,-32420(gp)
+ 8010288:	10803fcc 	andi	r2,r2,255
+ 801028c:	10000526 	beq	r2,zero,80102a4 <OSEventPendMulti+0xd4>
+       *perr =  OS_ERR_PEND_ISR;                        /* ... can't PEND from an ISR                  */
+ 8010290:	e0800217 	ldw	r2,8(fp)
+ 8010294:	00c00084 	movi	r3,2
+ 8010298:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 801029c:	0005883a 	mov	r2,zero
+ 80102a0:	00013106 	br	8010768 <OSEventPendMulti+0x598>
+    }
+    if (OSLockNesting > 0) {                            /* See if called with scheduler locked ...     */
+ 80102a4:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80102a8:	10803fcc 	andi	r2,r2,255
+ 80102ac:	10000526 	beq	r2,zero,80102c4 <OSEventPendMulti+0xf4>
+       *perr =  OS_ERR_PEND_LOCKED;                     /* ... can't PEND when locked                  */
+ 80102b0:	e0800217 	ldw	r2,8(fp)
+ 80102b4:	00c00344 	movi	r3,13
+ 80102b8:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 80102bc:	0005883a 	mov	r2,zero
+ 80102c0:	00012906 	br	8010768 <OSEventPendMulti+0x598>
+  NIOS2_READ_STATUS (context);
+ 80102c4:	0005303a 	rdctl	r2,status
+ 80102c8:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80102cc:	e0fff917 	ldw	r3,-28(fp)
+ 80102d0:	00bfff84 	movi	r2,-2
+ 80102d4:	1884703a 	and	r2,r3,r2
+ 80102d8:	1001703a 	wrctl	status,r2
+  return context;
+ 80102dc:	e0bff917 	ldw	r2,-28(fp)
+    }
+
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+ 80102e0:	e0bffb15 	stw	r2,-20(fp)
+    events_rdy     =  OS_FALSE;
+ 80102e4:	e03ffdc5 	stb	zero,-9(fp)
+    events_rdy_nbr =  0;
+ 80102e8:	e03ffd0d 	sth	zero,-12(fp)
+    events_stat    =  OS_STAT_RDY;
+ 80102ec:	e03ffcc5 	stb	zero,-13(fp)
+    pevents        =  pevents_pend;
+ 80102f0:	e0bff217 	ldw	r2,-56(fp)
+ 80102f4:	e0bfff15 	stw	r2,-4(fp)
+    pevent         = *pevents;
+ 80102f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80102fc:	10800017 	ldw	r2,0(r2)
+ 8010300:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                   /* See if any events already available         */
+ 8010304:	00008106 	br	801050c <OSEventPendMulti+0x33c>
+        switch (pevent->OSEventType) {
+ 8010308:	e0bffe17 	ldw	r2,-8(fp)
+ 801030c:	10800003 	ldbu	r2,0(r2)
+ 8010310:	10803fcc 	andi	r2,r2,255
+ 8010314:	10c000a0 	cmpeqi	r3,r2,2
+ 8010318:	18003c1e 	bne	r3,zero,801040c <OSEventPendMulti+0x23c>
+ 801031c:	10c000e0 	cmpeqi	r3,r2,3
+ 8010320:	1800031e 	bne	r3,zero,8010330 <OSEventPendMulti+0x160>
+ 8010324:	10800060 	cmpeqi	r2,r2,1
+ 8010328:	10001e1e 	bne	r2,zero,80103a4 <OSEventPendMulti+0x1d4>
+ 801032c:	00006606 	br	80104c8 <OSEventPendMulti+0x2f8>
+#if (OS_SEM_EN > 0)
+            case OS_EVENT_TYPE_SEM:
+                 if (pevent->OSEventCnt > 0) {          /* If semaphore count > 0, resource available; */
+ 8010330:	e0bffe17 	ldw	r2,-8(fp)
+ 8010334:	1080020b 	ldhu	r2,8(r2)
+ 8010338:	10bfffcc 	andi	r2,r2,65535
+ 801033c:	10001526 	beq	r2,zero,8010394 <OSEventPendMulti+0x1c4>
+                     pevent->OSEventCnt--;              /* ... decrement semaphore,                ... */
+ 8010340:	e0bffe17 	ldw	r2,-8(fp)
+ 8010344:	1080020b 	ldhu	r2,8(r2)
+ 8010348:	10bfffc4 	addi	r2,r2,-1
+ 801034c:	1007883a 	mov	r3,r2
+ 8010350:	e0bffe17 	ldw	r2,-8(fp)
+ 8010354:	10c0020d 	sth	r3,8(r2)
+                    *pevents_rdy++ =  pevent;           /* ... and return available semaphore event    */
+ 8010358:	e0bff117 	ldw	r2,-60(fp)
+ 801035c:	10c00104 	addi	r3,r2,4
+ 8010360:	e0fff115 	stw	r3,-60(fp)
+ 8010364:	e0fffe17 	ldw	r3,-8(fp)
+ 8010368:	10c00015 	stw	r3,0(r2)
+                      events_rdy   =  OS_TRUE;
+ 801036c:	00800044 	movi	r2,1
+ 8010370:	e0bffdc5 	stb	r2,-9(fp)
+                    *pmsgs_rdy++   = (void *)0;         /* NO message returned  for semaphores         */
+ 8010374:	e0bff017 	ldw	r2,-64(fp)
+ 8010378:	10c00104 	addi	r3,r2,4
+ 801037c:	e0fff015 	stw	r3,-64(fp)
+ 8010380:	10000015 	stw	zero,0(r2)
+                      events_rdy_nbr++;
+ 8010384:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8010388:	10800044 	addi	r2,r2,1
+ 801038c:	e0bffd0d 	sth	r2,-12(fp)
+
+                 } else {
+                      events_stat |=  OS_STAT_SEM;      /* Configure multi-pend for semaphore events   */
+                 }
+                 break;
+ 8010390:	00005806 	br	80104f4 <OSEventPendMulti+0x324>
+                      events_stat |=  OS_STAT_SEM;      /* Configure multi-pend for semaphore events   */
+ 8010394:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8010398:	10800054 	ori	r2,r2,1
+ 801039c:	e0bffcc5 	stb	r2,-13(fp)
+                 break;
+ 80103a0:	00005406 	br	80104f4 <OSEventPendMulti+0x324>
+#endif
+
+#if (OS_MBOX_EN > 0)
+            case OS_EVENT_TYPE_MBOX:
+                 if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty;                   ... */
+ 80103a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80103a8:	10800117 	ldw	r2,4(r2)
+ 80103ac:	10001326 	beq	r2,zero,80103fc <OSEventPendMulti+0x22c>
+                                                        /* ... return available message,           ... */
+                    *pmsgs_rdy++         = (void *)pevent->OSEventPtr;
+ 80103b0:	e0bff017 	ldw	r2,-64(fp)
+ 80103b4:	10c00104 	addi	r3,r2,4
+ 80103b8:	e0fff015 	stw	r3,-64(fp)
+ 80103bc:	e0fffe17 	ldw	r3,-8(fp)
+ 80103c0:	18c00117 	ldw	r3,4(r3)
+ 80103c4:	10c00015 	stw	r3,0(r2)
+                     pevent->OSEventPtr  = (void *)0;
+ 80103c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80103cc:	10000115 	stw	zero,4(r2)
+                    *pevents_rdy++       =  pevent;     /* ... and return available mailbox event      */
+ 80103d0:	e0bff117 	ldw	r2,-60(fp)
+ 80103d4:	10c00104 	addi	r3,r2,4
+ 80103d8:	e0fff115 	stw	r3,-60(fp)
+ 80103dc:	e0fffe17 	ldw	r3,-8(fp)
+ 80103e0:	10c00015 	stw	r3,0(r2)
+                      events_rdy         =  OS_TRUE;
+ 80103e4:	00800044 	movi	r2,1
+ 80103e8:	e0bffdc5 	stb	r2,-9(fp)
+                      events_rdy_nbr++;
+ 80103ec:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80103f0:	10800044 	addi	r2,r2,1
+ 80103f4:	e0bffd0d 	sth	r2,-12(fp)
+
+                 } else {
+                      events_stat |= OS_STAT_MBOX;      /* Configure multi-pend for mailbox events     */
+                 }
+                 break;
+ 80103f8:	00003e06 	br	80104f4 <OSEventPendMulti+0x324>
+                      events_stat |= OS_STAT_MBOX;      /* Configure multi-pend for mailbox events     */
+ 80103fc:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8010400:	10800094 	ori	r2,r2,2
+ 8010404:	e0bffcc5 	stb	r2,-13(fp)
+                 break;
+ 8010408:	00003a06 	br	80104f4 <OSEventPendMulti+0x324>
+#endif
+
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0))
+            case OS_EVENT_TYPE_Q:
+                 pq = (OS_Q *)pevent->OSEventPtr;
+ 801040c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010410:	10800117 	ldw	r2,4(r2)
+ 8010414:	e0bffa15 	stw	r2,-24(fp)
+                 if (pq->OSQEntries > 0) {              /* If queue NOT empty;                     ... */
+ 8010418:	e0bffa17 	ldw	r2,-24(fp)
+ 801041c:	1080058b 	ldhu	r2,22(r2)
+ 8010420:	10bfffcc 	andi	r2,r2,65535
+ 8010424:	10002426 	beq	r2,zero,80104b8 <OSEventPendMulti+0x2e8>
+                                                        /* ... return available message,           ... */
+                    *pmsgs_rdy++ = (void *)*pq->OSQOut++;
+ 8010428:	e0bffa17 	ldw	r2,-24(fp)
+ 801042c:	10c00417 	ldw	r3,16(r2)
+ 8010430:	19000104 	addi	r4,r3,4
+ 8010434:	e0bffa17 	ldw	r2,-24(fp)
+ 8010438:	11000415 	stw	r4,16(r2)
+ 801043c:	e0bff017 	ldw	r2,-64(fp)
+ 8010440:	11000104 	addi	r4,r2,4
+ 8010444:	e13ff015 	stw	r4,-64(fp)
+ 8010448:	18c00017 	ldw	r3,0(r3)
+ 801044c:	10c00015 	stw	r3,0(r2)
+                     if (pq->OSQOut == pq->OSQEnd) {    /* If OUT ptr at queue end, ...                */
+ 8010450:	e0bffa17 	ldw	r2,-24(fp)
+ 8010454:	10c00417 	ldw	r3,16(r2)
+ 8010458:	e0bffa17 	ldw	r2,-24(fp)
+ 801045c:	10800217 	ldw	r2,8(r2)
+ 8010460:	1880041e 	bne	r3,r2,8010474 <OSEventPendMulti+0x2a4>
+                         pq->OSQOut  = pq->OSQStart;    /* ... wrap   to queue start                   */
+ 8010464:	e0bffa17 	ldw	r2,-24(fp)
+ 8010468:	10c00117 	ldw	r3,4(r2)
+ 801046c:	e0bffa17 	ldw	r2,-24(fp)
+ 8010470:	10c00415 	stw	r3,16(r2)
+                     }
+                     pq->OSQEntries--;                  /* Update number of queue entries              */
+ 8010474:	e0bffa17 	ldw	r2,-24(fp)
+ 8010478:	1080058b 	ldhu	r2,22(r2)
+ 801047c:	10bfffc4 	addi	r2,r2,-1
+ 8010480:	1007883a 	mov	r3,r2
+ 8010484:	e0bffa17 	ldw	r2,-24(fp)
+ 8010488:	10c0058d 	sth	r3,22(r2)
+                    *pevents_rdy++ = pevent;            /* ... and return available queue event        */
+ 801048c:	e0bff117 	ldw	r2,-60(fp)
+ 8010490:	10c00104 	addi	r3,r2,4
+ 8010494:	e0fff115 	stw	r3,-60(fp)
+ 8010498:	e0fffe17 	ldw	r3,-8(fp)
+ 801049c:	10c00015 	stw	r3,0(r2)
+                      events_rdy   = OS_TRUE;
+ 80104a0:	00800044 	movi	r2,1
+ 80104a4:	e0bffdc5 	stb	r2,-9(fp)
+                      events_rdy_nbr++;
+ 80104a8:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80104ac:	10800044 	addi	r2,r2,1
+ 80104b0:	e0bffd0d 	sth	r2,-12(fp)
+
+                 } else {
+                      events_stat |= OS_STAT_Q;         /* Configure multi-pend for queue events       */
+                 }
+                 break;
+ 80104b4:	00000f06 	br	80104f4 <OSEventPendMulti+0x324>
+                      events_stat |= OS_STAT_Q;         /* Configure multi-pend for queue events       */
+ 80104b8:	e0bffcc3 	ldbu	r2,-13(fp)
+ 80104bc:	10800114 	ori	r2,r2,4
+ 80104c0:	e0bffcc5 	stb	r2,-13(fp)
+                 break;
+ 80104c4:	00000b06 	br	80104f4 <OSEventPendMulti+0x324>
+ 80104c8:	e0bffb17 	ldw	r2,-20(fp)
+ 80104cc:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80104d0:	e0bff817 	ldw	r2,-32(fp)
+ 80104d4:	1001703a 	wrctl	status,r2
+
+            case OS_EVENT_TYPE_MUTEX:                                            
+            case OS_EVENT_TYPE_FLAG:
+            default:           
+                 OS_EXIT_CRITICAL();
+                *pevents_rdy = (OS_EVENT *)0;           /* NULL terminate return event array           */
+ 80104d8:	e0bff117 	ldw	r2,-60(fp)
+ 80104dc:	10000015 	stw	zero,0(r2)
+                *perr        =  OS_ERR_EVENT_TYPE;
+ 80104e0:	e0800217 	ldw	r2,8(fp)
+ 80104e4:	00c00044 	movi	r3,1
+ 80104e8:	10c00005 	stb	r3,0(r2)
+                 return (events_rdy_nbr);
+ 80104ec:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80104f0:	00009d06 	br	8010768 <OSEventPendMulti+0x598>
+        }
+        pevents++;
+ 80104f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80104f8:	10800104 	addi	r2,r2,4
+ 80104fc:	e0bfff15 	stw	r2,-4(fp)
+        pevent = *pevents;
+ 8010500:	e0bfff17 	ldw	r2,-4(fp)
+ 8010504:	10800017 	ldw	r2,0(r2)
+ 8010508:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                   /* See if any events already available         */
+ 801050c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010510:	103f7d1e 	bne	r2,zero,8010308 <OSEventPendMulti+0x138>
+    }
+
+    if ( events_rdy == OS_TRUE) {                       /* Return any events already available         */
+ 8010514:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8010518:	10800058 	cmpnei	r2,r2,1
+ 801051c:	10000a1e 	bne	r2,zero,8010548 <OSEventPendMulti+0x378>
+       *pevents_rdy = (OS_EVENT *)0;                    /* NULL terminate return event array           */
+ 8010520:	e0bff117 	ldw	r2,-60(fp)
+ 8010524:	10000015 	stw	zero,0(r2)
+ 8010528:	e0bffb17 	ldw	r2,-20(fp)
+ 801052c:	e0bff715 	stw	r2,-36(fp)
+ 8010530:	e0bff717 	ldw	r2,-36(fp)
+ 8010534:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+       *perr        =  OS_ERR_NONE;
+ 8010538:	e0800217 	ldw	r2,8(fp)
+ 801053c:	10000005 	stb	zero,0(r2)
+        return (events_rdy_nbr);
+ 8010540:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8010544:	00008806 	br	8010768 <OSEventPendMulti+0x598>
+    }
+/*$PAGE*/
+                                                        /* Otherwise, must wait until any event occurs */
+    OSTCBCur->OSTCBStat     |= events_stat  |           /* Resource not available, ...                 */
+ 8010548:	d0a05817 	ldw	r2,-32416(gp)
+ 801054c:	10800c03 	ldbu	r2,48(r2)
+ 8010550:	e0fffcc3 	ldbu	r3,-13(fp)
+ 8010554:	1884b03a 	or	r2,r3,r2
+ 8010558:	1009883a 	mov	r4,r2
+ 801055c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010560:	00ffe004 	movi	r3,-128
+ 8010564:	20c6b03a 	or	r3,r4,r3
+ 8010568:	10c00c05 	stb	r3,48(r2)
+                               OS_STAT_MULTI;           /* ... pend on multiple events                 */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 801056c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010570:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBDly       = timeout;                 /* Store pend timeout in TCB                   */
+ 8010574:	d0a05817 	ldw	r2,-32416(gp)
+ 8010578:	e0ffef0b 	ldhu	r3,-68(fp)
+ 801057c:	10c00b8d 	sth	r3,46(r2)
+    OS_EventTaskWaitMulti(pevents_pend);                /* Suspend task until events or timeout occurs */
+ 8010580:	e13ff217 	ldw	r4,-56(fp)
+ 8010584:	8010f680 	call	8010f68 <OS_EventTaskWaitMulti>
+ 8010588:	e0bffb17 	ldw	r2,-20(fp)
+ 801058c:	e0bff515 	stw	r2,-44(fp)
+ 8010590:	e0bff517 	ldw	r2,-44(fp)
+ 8010594:	1001703a 	wrctl	status,r2
+
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                         /* Find next highest priority task ready       */
+ 8010598:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 801059c:	0005303a 	rdctl	r2,status
+ 80105a0:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80105a4:	e0fff617 	ldw	r3,-40(fp)
+ 80105a8:	00bfff84 	movi	r2,-2
+ 80105ac:	1884703a 	and	r2,r3,r2
+ 80105b0:	1001703a 	wrctl	status,r2
+  return context;
+ 80105b4:	e0bff617 	ldw	r2,-40(fp)
+    OS_ENTER_CRITICAL();
+ 80105b8:	e0bffb15 	stw	r2,-20(fp)
+
+    switch (OSTCBCur->OSTCBStatPend) {                  /* Handle event posted, aborted, or timed-out  */
+ 80105bc:	d0a05817 	ldw	r2,-32416(gp)
+ 80105c0:	10800c43 	ldbu	r2,49(r2)
+ 80105c4:	10803fcc 	andi	r2,r2,255
+ 80105c8:	10000226 	beq	r2,zero,80105d4 <OSEventPendMulti+0x404>
+ 80105cc:	10800098 	cmpnei	r2,r2,2
+ 80105d0:	1000181e 	bne	r2,zero,8010634 <OSEventPendMulti+0x464>
+        case OS_STAT_PEND_OK:
+        case OS_STAT_PEND_ABORT:
+             pevent = OSTCBCur->OSTCBEventPtr;
+ 80105d4:	d0a05817 	ldw	r2,-32416(gp)
+ 80105d8:	10800717 	ldw	r2,28(r2)
+ 80105dc:	e0bffe15 	stw	r2,-8(fp)
+             if (pevent != (OS_EVENT *)0) {             /* If task event ptr != NULL, ...              */
+ 80105e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80105e4:	10000b26 	beq	r2,zero,8010614 <OSEventPendMulti+0x444>
+                *pevents_rdy++ =  pevent;               /* ... return available event ...              */
+ 80105e8:	e0bff117 	ldw	r2,-60(fp)
+ 80105ec:	10c00104 	addi	r3,r2,4
+ 80105f0:	e0fff115 	stw	r3,-60(fp)
+ 80105f4:	e0fffe17 	ldw	r3,-8(fp)
+ 80105f8:	10c00015 	stw	r3,0(r2)
+                *pevents_rdy   = (OS_EVENT *)0;         /* ... & NULL terminate return event array     */
+ 80105fc:	e0bff117 	ldw	r2,-60(fp)
+ 8010600:	10000015 	stw	zero,0(r2)
+                  events_rdy_nbr++;
+ 8010604:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8010608:	10800044 	addi	r2,r2,1
+ 801060c:	e0bffd0d 	sth	r2,-12(fp)
+
+             } else {                                   /* Else NO event available, handle as timeout  */
+                 OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO;
+                 OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend);
+             }
+			 break;
+ 8010610:	00000d06 	br	8010648 <OSEventPendMulti+0x478>
+                 OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO;
+ 8010614:	d0a05817 	ldw	r2,-32416(gp)
+ 8010618:	00c00044 	movi	r3,1
+ 801061c:	10c00c45 	stb	r3,49(r2)
+                 OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend);
+ 8010620:	d0a05817 	ldw	r2,-32416(gp)
+ 8010624:	e17ff217 	ldw	r5,-56(fp)
+ 8010628:	1009883a 	mov	r4,r2
+ 801062c:	80111600 	call	8011160 <OS_EventTaskRemoveMulti>
+			 break;
+ 8010630:	00000506 	br	8010648 <OSEventPendMulti+0x478>
+
+        case OS_STAT_PEND_TO:
+        default:                                        /* ... remove task from events' wait lists     */
+             OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend);
+ 8010634:	d0a05817 	ldw	r2,-32416(gp)
+ 8010638:	e17ff217 	ldw	r5,-56(fp)
+ 801063c:	1009883a 	mov	r4,r2
+ 8010640:	80111600 	call	8011160 <OS_EventTaskRemoveMulti>
+             break;
+ 8010644:	0001883a 	nop
+    }
+
+    switch (OSTCBCur->OSTCBStatPend) {
+ 8010648:	d0a05817 	ldw	r2,-32416(gp)
+ 801064c:	10800c43 	ldbu	r2,49(r2)
+ 8010650:	10803fcc 	andi	r2,r2,255
+ 8010654:	10000326 	beq	r2,zero,8010664 <OSEventPendMulti+0x494>
+ 8010658:	108000a0 	cmpeqi	r2,r2,2
+ 801065c:	1000231e 	bne	r2,zero,80106ec <OSEventPendMulti+0x51c>
+ 8010660:	00002a06 	br	801070c <OSEventPendMulti+0x53c>
+        case OS_STAT_PEND_OK:
+             switch (pevent->OSEventType) {             /* Return event's message                      */
+ 8010664:	e0bffe17 	ldw	r2,-8(fp)
+ 8010668:	10800003 	ldbu	r2,0(r2)
+ 801066c:	10803fcc 	andi	r2,r2,255
+ 8010670:	0080100e 	bge	zero,r2,80106b4 <OSEventPendMulti+0x4e4>
+ 8010674:	10c000d0 	cmplti	r3,r2,3
+ 8010678:	1800071e 	bne	r3,zero,8010698 <OSEventPendMulti+0x4c8>
+ 801067c:	108000d8 	cmpnei	r2,r2,3
+ 8010680:	10000c1e 	bne	r2,zero,80106b4 <OSEventPendMulti+0x4e4>
+#if (OS_SEM_EN > 0)
+                 case OS_EVENT_TYPE_SEM:
+                     *pmsgs_rdy++ = (void *)0;          /* NO message returned for semaphores          */
+ 8010684:	e0bff017 	ldw	r2,-64(fp)
+ 8010688:	10c00104 	addi	r3,r2,4
+ 801068c:	e0fff015 	stw	r3,-64(fp)
+ 8010690:	10000015 	stw	zero,0(r2)
+                      break;
+ 8010694:	00001206 	br	80106e0 <OSEventPendMulti+0x510>
+
+#if ((OS_MBOX_EN > 0) ||                 \
+    ((OS_Q_EN    > 0) && (OS_MAX_QS > 0)))
+                 case OS_EVENT_TYPE_MBOX:
+                 case OS_EVENT_TYPE_Q:
+                     *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg;     /* Return received message         */
+ 8010698:	d0e05817 	ldw	r3,-32416(gp)
+ 801069c:	e0bff017 	ldw	r2,-64(fp)
+ 80106a0:	11000104 	addi	r4,r2,4
+ 80106a4:	e13ff015 	stw	r4,-64(fp)
+ 80106a8:	18c00917 	ldw	r3,36(r3)
+ 80106ac:	10c00015 	stw	r3,0(r2)
+                      break;
+ 80106b0:	00000b06 	br	80106e0 <OSEventPendMulti+0x510>
+ 80106b4:	e0bffb17 	ldw	r2,-20(fp)
+ 80106b8:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80106bc:	e0bff417 	ldw	r2,-48(fp)
+ 80106c0:	1001703a 	wrctl	status,r2
+
+                 case OS_EVENT_TYPE_MUTEX:                                       
+                 case OS_EVENT_TYPE_FLAG:
+                 default:           
+                      OS_EXIT_CRITICAL();
+                     *pevents_rdy = (OS_EVENT *)0;      /* NULL terminate return event array           */
+ 80106c4:	e0bff117 	ldw	r2,-60(fp)
+ 80106c8:	10000015 	stw	zero,0(r2)
+                     *perr        =  OS_ERR_EVENT_TYPE;
+ 80106cc:	e0800217 	ldw	r2,8(fp)
+ 80106d0:	00c00044 	movi	r3,1
+ 80106d4:	10c00005 	stb	r3,0(r2)
+                      return (events_rdy_nbr);
+ 80106d8:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80106dc:	00002206 	br	8010768 <OSEventPendMulti+0x598>
+             }
+            *perr = OS_ERR_NONE;
+ 80106e0:	e0800217 	ldw	r2,8(fp)
+ 80106e4:	10000005 	stb	zero,0(r2)
+             break;
+ 80106e8:	00001006 	br	801072c <OSEventPendMulti+0x55c>
+
+        case OS_STAT_PEND_ABORT:
+            *pmsgs_rdy++ = (void *)0;                   /* NO message returned for abort               */
+ 80106ec:	e0bff017 	ldw	r2,-64(fp)
+ 80106f0:	10c00104 	addi	r3,r2,4
+ 80106f4:	e0fff015 	stw	r3,-64(fp)
+ 80106f8:	10000015 	stw	zero,0(r2)
+            *perr        =  OS_ERR_PEND_ABORT;          /* Indicate that event  aborted                */
+ 80106fc:	e0800217 	ldw	r2,8(fp)
+ 8010700:	00c00384 	movi	r3,14
+ 8010704:	10c00005 	stb	r3,0(r2)
+             break;
+ 8010708:	00000806 	br	801072c <OSEventPendMulti+0x55c>
+                                                        
+        case OS_STAT_PEND_TO:                                                
+        default:        
+            *pmsgs_rdy++ = (void *)0;                   /* NO message returned for timeout             */
+ 801070c:	e0bff017 	ldw	r2,-64(fp)
+ 8010710:	10c00104 	addi	r3,r2,4
+ 8010714:	e0fff015 	stw	r3,-64(fp)
+ 8010718:	10000015 	stw	zero,0(r2)
+            *perr        =  OS_ERR_TIMEOUT;             /* Indicate that events timed out              */
+ 801071c:	e0800217 	ldw	r2,8(fp)
+ 8010720:	00c00284 	movi	r3,10
+ 8010724:	10c00005 	stb	r3,0(r2)
+             break;
+ 8010728:	0001883a 	nop
+    }
+
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;        /* Set   task  status to ready                 */
+ 801072c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010730:	10000c05 	stb	zero,48(r2)
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;    /* Clear pend  status                          */
+ 8010734:	d0a05817 	ldw	r2,-32416(gp)
+ 8010738:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;      /* Clear event pointers                        */
+ 801073c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010740:	10000715 	stw	zero,28(r2)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+ 8010744:	d0a05817 	ldw	r2,-32416(gp)
+ 8010748:	10000815 	stw	zero,32(r2)
+    OSTCBCur->OSTCBMsg           = (void      *)0;      /* Clear task  message                         */
+ 801074c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010750:	10000915 	stw	zero,36(r2)
+ 8010754:	e0bffb17 	ldw	r2,-20(fp)
+ 8010758:	e0bff315 	stw	r2,-52(fp)
+ 801075c:	e0bff317 	ldw	r2,-52(fp)
+ 8010760:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+
+    return (events_rdy_nbr);
+ 8010764:	e0bffd0b 	ldhu	r2,-12(fp)
+}
+ 8010768:	e037883a 	mov	sp,fp
+ 801076c:	dfc00117 	ldw	ra,4(sp)
+ 8010770:	df000017 	ldw	fp,0(sp)
+ 8010774:	dec00204 	addi	sp,sp,8
+ 8010778:	f800283a 	ret
+
+0801077c <OSInit>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSInit (void)
+{
+ 801077c:	defffe04 	addi	sp,sp,-8
+ 8010780:	dfc00115 	stw	ra,4(sp)
+ 8010784:	df000015 	stw	fp,0(sp)
+ 8010788:	d839883a 	mov	fp,sp
+    OSInitHookBegin();                                           /* Call port specific initialization code   */
+ 801078c:	80386580 	call	8038658 <OSInitHookBegin>
+
+    OS_InitMisc();                                               /* Initialize miscellaneous variables       */
+ 8010790:	80113a00 	call	80113a0 <OS_InitMisc>
+
+    OS_InitRdyList();                                            /* Initialize the Ready List                */
+ 8010794:	80113dc0 	call	80113dc <OS_InitRdyList>
+
+    OS_InitTCBList();                                            /* Initialize the free list of OS_TCBs      */
+ 8010798:	80114cc0 	call	80114cc <OS_InitTCBList>
+
+    OS_InitEventList();                                          /* Initialize the free list of OS_EVENTs    */
+ 801079c:	80112c00 	call	80112c0 <OS_InitEventList>
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    OS_FlagInit();                                               /* Initialize the event flag structures     */
+ 80107a0:	8012ed80 	call	8012ed8 <OS_FlagInit>
+#endif
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+    OS_MemInit();                                                /* Initialize the memory manager            */
+ 80107a4:	80136580 	call	8013658 <OS_MemInit>
+#endif
+
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+    OS_QInit();                                                  /* Initialize the message queue structures  */
+ 80107a8:	801562c0 	call	801562c <OS_QInit>
+#endif
+
+    OS_InitTaskIdle();                                           /* Create the Idle Task                     */
+ 80107ac:	80114480 	call	8011448 <OS_InitTaskIdle>
+
+#if OS_TMR_EN > 0
+    OSTmr_Init();                                                /* Initialize the Timer Manager             */
+#endif
+
+    OSInitHookEnd();                                             /* Call port specific init. code            */
+ 80107b0:	80386780 	call	8038678 <OSInitHookEnd>
+
+#if OS_DEBUG_EN > 0
+    OSDebugInit();
+#endif
+}
+ 80107b4:	0001883a 	nop
+ 80107b8:	e037883a 	mov	sp,fp
+ 80107bc:	dfc00117 	ldw	ra,4(sp)
+ 80107c0:	df000017 	ldw	fp,0(sp)
+ 80107c4:	dec00204 	addi	sp,sp,8
+ 80107c8:	f800283a 	ret
+
+080107cc <OSIntEnter>:
+*              5) You are allowed to nest interrupts up to 255 levels deep.
+*********************************************************************************************************
+*/
+
+void  OSIntEnter (void)
+{
+ 80107cc:	deffff04 	addi	sp,sp,-4
+ 80107d0:	df000015 	stw	fp,0(sp)
+ 80107d4:	d839883a 	mov	fp,sp
+    if (OSRunning == OS_TRUE) {
+ 80107d8:	d0a04b43 	ldbu	r2,-32467(gp)
+ 80107dc:	10803fcc 	andi	r2,r2,255
+ 80107e0:	10800058 	cmpnei	r2,r2,1
+ 80107e4:	1000071e 	bne	r2,zero,8010804 <OSIntEnter+0x38>
+        if (OSIntNesting < 255u) {
+ 80107e8:	d0a05703 	ldbu	r2,-32420(gp)
+ 80107ec:	10803fcc 	andi	r2,r2,255
+ 80107f0:	10803fe0 	cmpeqi	r2,r2,255
+ 80107f4:	1000031e 	bne	r2,zero,8010804 <OSIntEnter+0x38>
+            OSIntNesting++;                      /* Increment ISR nesting level                        */
+ 80107f8:	d0a05703 	ldbu	r2,-32420(gp)
+ 80107fc:	10800044 	addi	r2,r2,1
+ 8010800:	d0a05705 	stb	r2,-32420(gp)
+        }
+    }
+}
+ 8010804:	0001883a 	nop
+ 8010808:	e037883a 	mov	sp,fp
+ 801080c:	df000017 	ldw	fp,0(sp)
+ 8010810:	dec00104 	addi	sp,sp,4
+ 8010814:	f800283a 	ret
+
+08010818 <OSIntExit>:
+*              2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock())
+*********************************************************************************************************
+*/
+
+void  OSIntExit (void)
+{
+ 8010818:	defffb04 	addi	sp,sp,-20
+ 801081c:	dfc00415 	stw	ra,16(sp)
+ 8010820:	df000315 	stw	fp,12(sp)
+ 8010824:	df000304 	addi	fp,sp,12
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 8010828:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {
+ 801082c:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8010830:	10803fcc 	andi	r2,r2,255
+ 8010834:	10800058 	cmpnei	r2,r2,1
+ 8010838:	10002d1e 	bne	r2,zero,80108f0 <OSIntExit+0xd8>
+  NIOS2_READ_STATUS (context);
+ 801083c:	0005303a 	rdctl	r2,status
+ 8010840:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010844:	e0fffe17 	ldw	r3,-8(fp)
+ 8010848:	00bfff84 	movi	r2,-2
+ 801084c:	1884703a 	and	r2,r3,r2
+ 8010850:	1001703a 	wrctl	status,r2
+  return context;
+ 8010854:	e0bffe17 	ldw	r2,-8(fp)
+        OS_ENTER_CRITICAL();
+ 8010858:	e0bfff15 	stw	r2,-4(fp)
+        if (OSIntNesting > 0) {                            /* Prevent OSIntNesting from wrapping       */
+ 801085c:	d0a05703 	ldbu	r2,-32420(gp)
+ 8010860:	10803fcc 	andi	r2,r2,255
+ 8010864:	10000326 	beq	r2,zero,8010874 <OSIntExit+0x5c>
+            OSIntNesting--;
+ 8010868:	d0a05703 	ldbu	r2,-32420(gp)
+ 801086c:	10bfffc4 	addi	r2,r2,-1
+ 8010870:	d0a05705 	stb	r2,-32420(gp)
+        }
+        if (OSIntNesting == 0) {                           /* Reschedule only if all ISRs complete ... */
+ 8010874:	d0a05703 	ldbu	r2,-32420(gp)
+ 8010878:	10803fcc 	andi	r2,r2,255
+ 801087c:	1000181e 	bne	r2,zero,80108e0 <OSIntExit+0xc8>
+            if (OSLockNesting == 0) {                      /* ... and not locked.                      */
+ 8010880:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8010884:	10803fcc 	andi	r2,r2,255
+ 8010888:	1000151e 	bne	r2,zero,80108e0 <OSIntExit+0xc8>
+                OS_SchedNew();
+ 801088c:	80117340 	call	8011734 <OS_SchedNew>
+                if (OSPrioHighRdy != OSPrioCur) {          /* No Ctx Sw if current task is highest rdy */
+ 8010890:	d0e04d03 	ldbu	r3,-32460(gp)
+ 8010894:	d0a04d43 	ldbu	r2,-32459(gp)
+ 8010898:	18c03fcc 	andi	r3,r3,255
+ 801089c:	10803fcc 	andi	r2,r2,255
+ 80108a0:	18800f26 	beq	r3,r2,80108e0 <OSIntExit+0xc8>
+                    OSTCBHighRdy  = OSTCBPrioTbl[OSPrioHighRdy];
+ 80108a4:	d0a04d03 	ldbu	r2,-32460(gp)
+ 80108a8:	10803fcc 	andi	r2,r2,255
+ 80108ac:	100690ba 	slli	r3,r2,2
+ 80108b0:	008201b4 	movhi	r2,2054
+ 80108b4:	1885883a 	add	r2,r3,r2
+ 80108b8:	10b55d17 	ldw	r2,-10892(r2)
+ 80108bc:	d0a05315 	stw	r2,-32436(gp)
+#if OS_TASK_PROFILE_EN > 0
+                    OSTCBHighRdy->OSTCBCtxSwCtr++;         /* Inc. # of context switches to this task  */
+ 80108c0:	d0a05317 	ldw	r2,-32436(gp)
+ 80108c4:	10c00e17 	ldw	r3,56(r2)
+ 80108c8:	18c00044 	addi	r3,r3,1
+ 80108cc:	10c00e15 	stw	r3,56(r2)
+#endif
+                    OSCtxSwCtr++;                          /* Keep track of the number of ctx switches */
+ 80108d0:	d0a04f17 	ldw	r2,-32452(gp)
+ 80108d4:	10800044 	addi	r2,r2,1
+ 80108d8:	d0a04f15 	stw	r2,-32452(gp)
+                    OSIntCtxSw();                          /* Perform interrupt level ctx switch       */
+ 80108dc:	80383880 	call	8038388 <OSCtxSw>
+ 80108e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80108e4:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80108e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80108ec:	1001703a 	wrctl	status,r2
+                }
+            }
+        }
+        OS_EXIT_CRITICAL();
+    }
+}
+ 80108f0:	0001883a 	nop
+ 80108f4:	e037883a 	mov	sp,fp
+ 80108f8:	dfc00117 	ldw	ra,4(sp)
+ 80108fc:	df000017 	ldw	fp,0(sp)
+ 8010900:	dec00204 	addi	sp,sp,8
+ 8010904:	f800283a 	ret
+
+08010908 <OSSchedLock>:
+*********************************************************************************************************
+*/
+
+#if OS_SCHED_LOCK_EN > 0
+void  OSSchedLock (void)
+{
+ 8010908:	defffc04 	addi	sp,sp,-16
+ 801090c:	df000315 	stw	fp,12(sp)
+ 8010910:	df000304 	addi	fp,sp,12
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8010914:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {                  /* Make sure multitasking is running                  */
+ 8010918:	d0a04b43 	ldbu	r2,-32467(gp)
+ 801091c:	10803fcc 	andi	r2,r2,255
+ 8010920:	10800058 	cmpnei	r2,r2,1
+ 8010924:	1000161e 	bne	r2,zero,8010980 <OSSchedLock+0x78>
+  NIOS2_READ_STATUS (context);
+ 8010928:	0005303a 	rdctl	r2,status
+ 801092c:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010930:	e0fffe17 	ldw	r3,-8(fp)
+ 8010934:	00bfff84 	movi	r2,-2
+ 8010938:	1884703a 	and	r2,r3,r2
+ 801093c:	1001703a 	wrctl	status,r2
+  return context;
+ 8010940:	e0bffe17 	ldw	r2,-8(fp)
+        OS_ENTER_CRITICAL();
+ 8010944:	e0bfff15 	stw	r2,-4(fp)
+        if (OSIntNesting == 0) {                 /* Can't call from an ISR                             */
+ 8010948:	d0a05703 	ldbu	r2,-32420(gp)
+ 801094c:	10803fcc 	andi	r2,r2,255
+ 8010950:	1000071e 	bne	r2,zero,8010970 <OSSchedLock+0x68>
+            if (OSLockNesting < 255u) {          /* Prevent OSLockNesting from wrapping back to 0      */
+ 8010954:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8010958:	10803fcc 	andi	r2,r2,255
+ 801095c:	10803fe0 	cmpeqi	r2,r2,255
+ 8010960:	1000031e 	bne	r2,zero,8010970 <OSSchedLock+0x68>
+                OSLockNesting++;                 /* Increment lock nesting level                       */
+ 8010964:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8010968:	10800044 	addi	r2,r2,1
+ 801096c:	d0a04b05 	stb	r2,-32468(gp)
+ 8010970:	e0bfff17 	ldw	r2,-4(fp)
+ 8010974:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8010978:	e0bffd17 	ldw	r2,-12(fp)
+ 801097c:	1001703a 	wrctl	status,r2
+            }
+        }
+        OS_EXIT_CRITICAL();
+    }
+}
+ 8010980:	0001883a 	nop
+ 8010984:	e037883a 	mov	sp,fp
+ 8010988:	df000017 	ldw	fp,0(sp)
+ 801098c:	dec00104 	addi	sp,sp,4
+ 8010990:	f800283a 	ret
+
+08010994 <OSSchedUnlock>:
+*********************************************************************************************************
+*/
+
+#if OS_SCHED_LOCK_EN > 0
+void  OSSchedUnlock (void)
+{
+ 8010994:	defff804 	addi	sp,sp,-32
+ 8010998:	dfc00715 	stw	ra,28(sp)
+ 801099c:	df000615 	stw	fp,24(sp)
+ 80109a0:	df000604 	addi	fp,sp,24
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 80109a4:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {                            /* Make sure multitasking is running        */
+ 80109a8:	d0a04b43 	ldbu	r2,-32467(gp)
+ 80109ac:	10803fcc 	andi	r2,r2,255
+ 80109b0:	10800058 	cmpnei	r2,r2,1
+ 80109b4:	1000281e 	bne	r2,zero,8010a58 <OSSchedUnlock+0xc4>
+  NIOS2_READ_STATUS (context);
+ 80109b8:	0005303a 	rdctl	r2,status
+ 80109bc:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80109c0:	e0fffe17 	ldw	r3,-8(fp)
+ 80109c4:	00bfff84 	movi	r2,-2
+ 80109c8:	1884703a 	and	r2,r3,r2
+ 80109cc:	1001703a 	wrctl	status,r2
+  return context;
+ 80109d0:	e0bffe17 	ldw	r2,-8(fp)
+        OS_ENTER_CRITICAL();
+ 80109d4:	e0bfff15 	stw	r2,-4(fp)
+        if (OSLockNesting > 0) {                           /* Do not decrement if already 0            */
+ 80109d8:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80109dc:	10803fcc 	andi	r2,r2,255
+ 80109e0:	10001926 	beq	r2,zero,8010a48 <OSSchedUnlock+0xb4>
+            OSLockNesting--;                               /* Decrement lock nesting level             */
+ 80109e4:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80109e8:	10bfffc4 	addi	r2,r2,-1
+ 80109ec:	d0a04b05 	stb	r2,-32468(gp)
+            if (OSLockNesting == 0) {                      /* See if scheduler is enabled and ...      */
+ 80109f0:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80109f4:	10803fcc 	andi	r2,r2,255
+ 80109f8:	10000e1e 	bne	r2,zero,8010a34 <OSSchedUnlock+0xa0>
+                if (OSIntNesting == 0) {                   /* ... not in an ISR                        */
+ 80109fc:	d0a05703 	ldbu	r2,-32420(gp)
+ 8010a00:	10803fcc 	andi	r2,r2,255
+ 8010a04:	1000061e 	bne	r2,zero,8010a20 <OSSchedUnlock+0x8c>
+ 8010a08:	e0bfff17 	ldw	r2,-4(fp)
+ 8010a0c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8010a10:	e0bffd17 	ldw	r2,-12(fp)
+ 8010a14:	1001703a 	wrctl	status,r2
+                    OS_EXIT_CRITICAL();
+                    OS_Sched();                            /* See if a HPT is ready                    */
+ 8010a18:	801166c0 	call	801166c <OS_Sched>
+            }
+        } else {
+            OS_EXIT_CRITICAL();
+        }
+    }
+}
+ 8010a1c:	00000e06 	br	8010a58 <OSSchedUnlock+0xc4>
+ 8010a20:	e0bfff17 	ldw	r2,-4(fp)
+ 8010a24:	e0bffc15 	stw	r2,-16(fp)
+ 8010a28:	e0bffc17 	ldw	r2,-16(fp)
+ 8010a2c:	1001703a 	wrctl	status,r2
+ 8010a30:	00000906 	br	8010a58 <OSSchedUnlock+0xc4>
+ 8010a34:	e0bfff17 	ldw	r2,-4(fp)
+ 8010a38:	e0bffb15 	stw	r2,-20(fp)
+ 8010a3c:	e0bffb17 	ldw	r2,-20(fp)
+ 8010a40:	1001703a 	wrctl	status,r2
+ 8010a44:	00000406 	br	8010a58 <OSSchedUnlock+0xc4>
+ 8010a48:	e0bfff17 	ldw	r2,-4(fp)
+ 8010a4c:	e0bffa15 	stw	r2,-24(fp)
+ 8010a50:	e0bffa17 	ldw	r2,-24(fp)
+ 8010a54:	1001703a 	wrctl	status,r2
+ 8010a58:	0001883a 	nop
+ 8010a5c:	e037883a 	mov	sp,fp
+ 8010a60:	dfc00117 	ldw	ra,4(sp)
+ 8010a64:	df000017 	ldw	fp,0(sp)
+ 8010a68:	dec00204 	addi	sp,sp,8
+ 8010a6c:	f800283a 	ret
+
+08010a70 <OSStart>:
+*                 d_ Execute the task.
+*********************************************************************************************************
+*/
+
+void  OSStart (void)
+{
+ 8010a70:	defffe04 	addi	sp,sp,-8
+ 8010a74:	dfc00115 	stw	ra,4(sp)
+ 8010a78:	df000015 	stw	fp,0(sp)
+ 8010a7c:	d839883a 	mov	fp,sp
+    if (OSRunning == OS_FALSE) {
+ 8010a80:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8010a84:	10803fcc 	andi	r2,r2,255
+ 8010a88:	10000d1e 	bne	r2,zero,8010ac0 <OSStart+0x50>
+        OS_SchedNew();                               /* Find highest priority's task priority number   */
+ 8010a8c:	80117340 	call	8011734 <OS_SchedNew>
+        OSPrioCur     = OSPrioHighRdy;
+ 8010a90:	d0a04d03 	ldbu	r2,-32460(gp)
+ 8010a94:	d0a04d45 	stb	r2,-32459(gp)
+        OSTCBHighRdy  = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run    */
+ 8010a98:	d0a04d03 	ldbu	r2,-32460(gp)
+ 8010a9c:	10803fcc 	andi	r2,r2,255
+ 8010aa0:	100690ba 	slli	r3,r2,2
+ 8010aa4:	008201b4 	movhi	r2,2054
+ 8010aa8:	1885883a 	add	r2,r3,r2
+ 8010aac:	10b55d17 	ldw	r2,-10892(r2)
+ 8010ab0:	d0a05315 	stw	r2,-32436(gp)
+        OSTCBCur      = OSTCBHighRdy;
+ 8010ab4:	d0a05317 	ldw	r2,-32436(gp)
+ 8010ab8:	d0a05815 	stw	r2,-32416(gp)
+        OSStartHighRdy();                            /* Execute target specific code to start task     */
+ 8010abc:	80384140 	call	8038414 <OSStartHighRdy>
+    }
+}
+ 8010ac0:	0001883a 	nop
+ 8010ac4:	e037883a 	mov	sp,fp
+ 8010ac8:	dfc00117 	ldw	ra,4(sp)
+ 8010acc:	df000017 	ldw	fp,0(sp)
+ 8010ad0:	dec00204 	addi	sp,sp,8
+ 8010ad4:	f800283a 	ret
+
+08010ad8 <OSTimeTick>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSTimeTick (void)
+{
+ 8010ad8:	defff804 	addi	sp,sp,-32
+ 8010adc:	dfc00715 	stw	ra,28(sp)
+ 8010ae0:	df000615 	stw	fp,24(sp)
+ 8010ae4:	df000604 	addi	fp,sp,24
+    OS_TCB    *ptcb;
+#if OS_TICK_STEP_EN > 0
+    BOOLEAN    step;
+#endif
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+ 8010ae8:	e03ffe15 	stw	zero,-8(fp)
+#endif
+
+
+
+#if OS_TIME_TICK_HOOK_EN > 0
+    OSTimeTickHook();                                      /* Call user definable hook                     */
+ 8010aec:	803862c0 	call	803862c <OSTimeTickHook>
+  NIOS2_READ_STATUS (context);
+ 8010af0:	0005303a 	rdctl	r2,status
+ 8010af4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010af8:	e0fffc17 	ldw	r3,-16(fp)
+ 8010afc:	00bfff84 	movi	r2,-2
+ 8010b00:	1884703a 	and	r2,r3,r2
+ 8010b04:	1001703a 	wrctl	status,r2
+  return context;
+ 8010b08:	e0bffc17 	ldw	r2,-16(fp)
+#endif
+#if OS_TIME_GET_SET_EN > 0
+    OS_ENTER_CRITICAL();                                   /* Update the 32-bit tick counter               */
+ 8010b0c:	e0bffe15 	stw	r2,-8(fp)
+    OSTime++;
+ 8010b10:	d0a05917 	ldw	r2,-32412(gp)
+ 8010b14:	10800044 	addi	r2,r2,1
+ 8010b18:	d0a05915 	stw	r2,-32412(gp)
+ 8010b1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010b20:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8010b24:	e0bffd17 	ldw	r2,-12(fp)
+ 8010b28:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+#endif
+    if (OSRunning == OS_TRUE) {
+ 8010b2c:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8010b30:	10803fcc 	andi	r2,r2,255
+ 8010b34:	10800058 	cmpnei	r2,r2,1
+ 8010b38:	1000511e 	bne	r2,zero,8010c80 <OSTimeTick+0x1a8>
+        }
+        if (step == OS_FALSE) {                            /* Return if waiting for step command           */
+            return;
+        }
+#endif
+        ptcb = OSTCBList;                                  /* Point at first TCB in TCB list               */
+ 8010b3c:	d0a04e17 	ldw	r2,-32456(gp)
+ 8010b40:	e0bfff15 	stw	r2,-4(fp)
+        while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) {     /* Go through all TCBs in TCB list              */
+ 8010b44:	00004906 	br	8010c6c <OSTimeTick+0x194>
+  NIOS2_READ_STATUS (context);
+ 8010b48:	0005303a 	rdctl	r2,status
+ 8010b4c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8010b50:	e0fffb17 	ldw	r3,-20(fp)
+ 8010b54:	00bfff84 	movi	r2,-2
+ 8010b58:	1884703a 	and	r2,r3,r2
+ 8010b5c:	1001703a 	wrctl	status,r2
+  return context;
+ 8010b60:	e0bffb17 	ldw	r2,-20(fp)
+            OS_ENTER_CRITICAL();
+ 8010b64:	e0bffe15 	stw	r2,-8(fp)
+            if (ptcb->OSTCBDly != 0) {                     /* No, Delayed or waiting for event with TO     */
+ 8010b68:	e0bfff17 	ldw	r2,-4(fp)
+ 8010b6c:	10800b8b 	ldhu	r2,46(r2)
+ 8010b70:	10bfffcc 	andi	r2,r2,65535
+ 8010b74:	10003626 	beq	r2,zero,8010c50 <OSTimeTick+0x178>
+                if (--ptcb->OSTCBDly == 0) {               /* Decrement nbr of ticks to end of delay       */
+ 8010b78:	e0bfff17 	ldw	r2,-4(fp)
+ 8010b7c:	10800b8b 	ldhu	r2,46(r2)
+ 8010b80:	10bfffc4 	addi	r2,r2,-1
+ 8010b84:	1007883a 	mov	r3,r2
+ 8010b88:	e0bfff17 	ldw	r2,-4(fp)
+ 8010b8c:	10c00b8d 	sth	r3,46(r2)
+ 8010b90:	e0bfff17 	ldw	r2,-4(fp)
+ 8010b94:	10800b8b 	ldhu	r2,46(r2)
+ 8010b98:	10bfffcc 	andi	r2,r2,65535
+ 8010b9c:	10002c1e 	bne	r2,zero,8010c50 <OSTimeTick+0x178>
+                                                           /* Check for timeout                            */
+                    if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) {
+ 8010ba0:	e0bfff17 	ldw	r2,-4(fp)
+ 8010ba4:	10800c03 	ldbu	r2,48(r2)
+ 8010ba8:	10803fcc 	andi	r2,r2,255
+ 8010bac:	10800dcc 	andi	r2,r2,55
+ 8010bb0:	10000b26 	beq	r2,zero,8010be0 <OSTimeTick+0x108>
+                        ptcb->OSTCBStat  &= ~(INT8U)OS_STAT_PEND_ANY;          /* Yes, Clear status flag   */
+ 8010bb4:	e0bfff17 	ldw	r2,-4(fp)
+ 8010bb8:	10c00c03 	ldbu	r3,48(r2)
+ 8010bbc:	00bff204 	movi	r2,-56
+ 8010bc0:	1884703a 	and	r2,r3,r2
+ 8010bc4:	1007883a 	mov	r3,r2
+ 8010bc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8010bcc:	10c00c05 	stb	r3,48(r2)
+                        ptcb->OSTCBStatPend = OS_STAT_PEND_TO;                 /* Indicate PEND timeout    */
+ 8010bd0:	e0bfff17 	ldw	r2,-4(fp)
+ 8010bd4:	00c00044 	movi	r3,1
+ 8010bd8:	10c00c45 	stb	r3,49(r2)
+ 8010bdc:	00000206 	br	8010be8 <OSTimeTick+0x110>
+                    } else {
+                        ptcb->OSTCBStatPend = OS_STAT_PEND_OK;
+ 8010be0:	e0bfff17 	ldw	r2,-4(fp)
+ 8010be4:	10000c45 	stb	zero,49(r2)
+                    }
+
+                    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) {  /* Is task suspended?       */
+ 8010be8:	e0bfff17 	ldw	r2,-4(fp)
+ 8010bec:	10800c03 	ldbu	r2,48(r2)
+ 8010bf0:	10803fcc 	andi	r2,r2,255
+ 8010bf4:	1080020c 	andi	r2,r2,8
+ 8010bf8:	1000151e 	bne	r2,zero,8010c50 <OSTimeTick+0x178>
+                        OSRdyGrp               |= ptcb->OSTCBBitY;             /* No,  Make ready          */
+ 8010bfc:	e0bfff17 	ldw	r2,-4(fp)
+ 8010c00:	10c00d83 	ldbu	r3,54(r2)
+ 8010c04:	d0a05503 	ldbu	r2,-32428(gp)
+ 8010c08:	1884b03a 	or	r2,r3,r2
+ 8010c0c:	d0a05505 	stb	r2,-32428(gp)
+                        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8010c10:	e0bfff17 	ldw	r2,-4(fp)
+ 8010c14:	10800d03 	ldbu	r2,52(r2)
+ 8010c18:	10c03fcc 	andi	r3,r2,255
+ 8010c1c:	d0a05544 	addi	r2,gp,-32427
+ 8010c20:	1885883a 	add	r2,r3,r2
+ 8010c24:	11000003 	ldbu	r4,0(r2)
+ 8010c28:	e0bfff17 	ldw	r2,-4(fp)
+ 8010c2c:	10800d43 	ldbu	r2,53(r2)
+ 8010c30:	e0ffff17 	ldw	r3,-4(fp)
+ 8010c34:	18c00d03 	ldbu	r3,52(r3)
+ 8010c38:	18c03fcc 	andi	r3,r3,255
+ 8010c3c:	2084b03a 	or	r2,r4,r2
+ 8010c40:	1009883a 	mov	r4,r2
+ 8010c44:	d0a05544 	addi	r2,gp,-32427
+ 8010c48:	1885883a 	add	r2,r3,r2
+ 8010c4c:	11000005 	stb	r4,0(r2)
+                    }
+                }
+            }
+            ptcb = ptcb->OSTCBNext;                        /* Point at next TCB in TCB list                */
+ 8010c50:	e0bfff17 	ldw	r2,-4(fp)
+ 8010c54:	10800517 	ldw	r2,20(r2)
+ 8010c58:	e0bfff15 	stw	r2,-4(fp)
+ 8010c5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010c60:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8010c64:	e0bffa17 	ldw	r2,-24(fp)
+ 8010c68:	1001703a 	wrctl	status,r2
+        while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) {     /* Go through all TCBs in TCB list              */
+ 8010c6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8010c70:	10800c83 	ldbu	r2,50(r2)
+ 8010c74:	10803fcc 	andi	r2,r2,255
+ 8010c78:	10800518 	cmpnei	r2,r2,20
+ 8010c7c:	103fb21e 	bne	r2,zero,8010b48 <OSTimeTick+0x70>
+            OS_EXIT_CRITICAL();
+        }
+    }
+}
+ 8010c80:	0001883a 	nop
+ 8010c84:	e037883a 	mov	sp,fp
+ 8010c88:	dfc00117 	ldw	ra,4(sp)
+ 8010c8c:	df000017 	ldw	fp,0(sp)
+ 8010c90:	dec00204 	addi	sp,sp,8
+ 8010c94:	f800283a 	ret
+
+08010c98 <OSVersion>:
+* Returns    : the version number of uC/OS-II multiplied by 100.
+*********************************************************************************************************
+*/
+
+INT16U  OSVersion (void)
+{
+ 8010c98:	deffff04 	addi	sp,sp,-4
+ 8010c9c:	df000015 	stw	fp,0(sp)
+ 8010ca0:	d839883a 	mov	fp,sp
+    return (OS_VERSION);
+ 8010ca4:	00804784 	movi	r2,286
+}
+ 8010ca8:	e037883a 	mov	sp,fp
+ 8010cac:	df000017 	ldw	fp,0(sp)
+ 8010cb0:	dec00104 	addi	sp,sp,4
+ 8010cb4:	f800283a 	ret
+
+08010cb8 <OS_Dummy>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_DEL_EN > 0
+void  OS_Dummy (void)
+{
+ 8010cb8:	deffff04 	addi	sp,sp,-4
+ 8010cbc:	df000015 	stw	fp,0(sp)
+ 8010cc0:	d839883a 	mov	fp,sp
+}
+ 8010cc4:	0001883a 	nop
+ 8010cc8:	e037883a 	mov	sp,fp
+ 8010ccc:	df000017 	ldw	fp,0(sp)
+ 8010cd0:	dec00104 	addi	sp,sp,4
+ 8010cd4:	f800283a 	ret
+
+08010cd8 <OS_EventTaskRdy>:
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+INT8U  OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat)
+{
+ 8010cd8:	defff804 	addi	sp,sp,-32
+ 8010cdc:	dfc00715 	stw	ra,28(sp)
+ 8010ce0:	df000615 	stw	fp,24(sp)
+ 8010ce4:	df000604 	addi	fp,sp,24
+ 8010ce8:	e13ffd15 	stw	r4,-12(fp)
+ 8010cec:	e17ffc15 	stw	r5,-16(fp)
+ 8010cf0:	3005883a 	mov	r2,r6
+ 8010cf4:	3807883a 	mov	r3,r7
+ 8010cf8:	e0bffb05 	stb	r2,-20(fp)
+ 8010cfc:	1805883a 	mov	r2,r3
+ 8010d00:	e0bffa05 	stb	r2,-24(fp)
+    INT16U  *ptbl;
+#endif
+
+
+#if OS_LOWEST_PRIO <= 63
+    y    = OSUnMapTbl[pevent->OSEventGrp];              /* Find HPT waiting for message                */
+ 8010d04:	e0bffd17 	ldw	r2,-12(fp)
+ 8010d08:	10800283 	ldbu	r2,10(r2)
+ 8010d0c:	10c03fcc 	andi	r3,r2,255
+ 8010d10:	00820134 	movhi	r2,2052
+ 8010d14:	1885883a 	add	r2,r3,r2
+ 8010d18:	109dcd03 	ldbu	r2,30516(r2)
+ 8010d1c:	e0bfffc5 	stb	r2,-1(fp)
+    x    = OSUnMapTbl[pevent->OSEventTbl[y]];
+ 8010d20:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8010d24:	e0fffd17 	ldw	r3,-12(fp)
+ 8010d28:	1885883a 	add	r2,r3,r2
+ 8010d2c:	108002c3 	ldbu	r2,11(r2)
+ 8010d30:	10c03fcc 	andi	r3,r2,255
+ 8010d34:	00820134 	movhi	r2,2052
+ 8010d38:	1885883a 	add	r2,r3,r2
+ 8010d3c:	109dcd03 	ldbu	r2,30516(r2)
+ 8010d40:	e0bfff85 	stb	r2,-2(fp)
+    prio = (INT8U)((y << 3) + x);                       /* Find priority of task getting the msg       */
+ 8010d44:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8010d48:	100490fa 	slli	r2,r2,3
+ 8010d4c:	1007883a 	mov	r3,r2
+ 8010d50:	e0bfff83 	ldbu	r2,-2(fp)
+ 8010d54:	10c5883a 	add	r2,r2,r3
+ 8010d58:	e0bfff45 	stb	r2,-3(fp)
+        x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8;
+    }
+    prio = (INT8U)((y << 4) + x);                       /* Find priority of task getting the msg       */
+#endif
+
+    ptcb                  =  OSTCBPrioTbl[prio];        /* Point to this task's OS_TCB                 */
+ 8010d5c:	e0bfff43 	ldbu	r2,-3(fp)
+ 8010d60:	100690ba 	slli	r3,r2,2
+ 8010d64:	008201b4 	movhi	r2,2054
+ 8010d68:	1885883a 	add	r2,r3,r2
+ 8010d6c:	10b55d17 	ldw	r2,-10892(r2)
+ 8010d70:	e0bffe15 	stw	r2,-8(fp)
+    ptcb->OSTCBDly        =  0;                         /* Prevent OSTimeTick() from readying task     */
+ 8010d74:	e0bffe17 	ldw	r2,-8(fp)
+ 8010d78:	10000b8d 	sth	zero,46(r2)
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0)
+    ptcb->OSTCBMsg        =  pmsg;                      /* Send message directly to waiting task       */
+ 8010d7c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010d80:	e0fffc17 	ldw	r3,-16(fp)
+ 8010d84:	10c00915 	stw	r3,36(r2)
+#else
+    pmsg                  =  pmsg;                      /* Prevent compiler warning if not used        */
+#endif
+    ptcb->OSTCBStat      &= ~msk;                       /* Clear bit associated with event type        */
+ 8010d88:	e0bffe17 	ldw	r2,-8(fp)
+ 8010d8c:	10800c03 	ldbu	r2,48(r2)
+ 8010d90:	1007883a 	mov	r3,r2
+ 8010d94:	e0bffb03 	ldbu	r2,-20(fp)
+ 8010d98:	0084303a 	nor	r2,zero,r2
+ 8010d9c:	1884703a 	and	r2,r3,r2
+ 8010da0:	1007883a 	mov	r3,r2
+ 8010da4:	e0bffe17 	ldw	r2,-8(fp)
+ 8010da8:	10c00c05 	stb	r3,48(r2)
+    ptcb->OSTCBStatPend   =  pend_stat;                 /* Set pend status of post or abort            */
+ 8010dac:	e0bffe17 	ldw	r2,-8(fp)
+ 8010db0:	e0fffa03 	ldbu	r3,-24(fp)
+ 8010db4:	10c00c45 	stb	r3,49(r2)
+                                                        /* See if task is ready (could be susp'd)      */
+    if ((ptcb->OSTCBStat &   OS_STAT_SUSPEND) == OS_STAT_RDY) {
+ 8010db8:	e0bffe17 	ldw	r2,-8(fp)
+ 8010dbc:	10800c03 	ldbu	r2,48(r2)
+ 8010dc0:	10803fcc 	andi	r2,r2,255
+ 8010dc4:	1080020c 	andi	r2,r2,8
+ 8010dc8:	1000111e 	bne	r2,zero,8010e10 <OS_EventTaskRdy+0x138>
+        OSRdyGrp         |=  ptcb->OSTCBBitY;           /* Put task in the ready to run list           */
+ 8010dcc:	e0bffe17 	ldw	r2,-8(fp)
+ 8010dd0:	10c00d83 	ldbu	r3,54(r2)
+ 8010dd4:	d0a05503 	ldbu	r2,-32428(gp)
+ 8010dd8:	1884b03a 	or	r2,r3,r2
+ 8010ddc:	d0a05505 	stb	r2,-32428(gp)
+        OSRdyTbl[y]      |=  ptcb->OSTCBBitX;
+ 8010de0:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8010de4:	d0a05544 	addi	r2,gp,-32427
+ 8010de8:	1885883a 	add	r2,r3,r2
+ 8010dec:	11000003 	ldbu	r4,0(r2)
+ 8010df0:	e0bffe17 	ldw	r2,-8(fp)
+ 8010df4:	10800d43 	ldbu	r2,53(r2)
+ 8010df8:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8010dfc:	2084b03a 	or	r2,r4,r2
+ 8010e00:	1009883a 	mov	r4,r2
+ 8010e04:	d0a05544 	addi	r2,gp,-32427
+ 8010e08:	1885883a 	add	r2,r3,r2
+ 8010e0c:	11000005 	stb	r4,0(r2)
+    }
+
+    OS_EventTaskRemove(ptcb, pevent);                   /* Remove this task from event   wait list     */
+ 8010e10:	e17ffd17 	ldw	r5,-12(fp)
+ 8010e14:	e13ffe17 	ldw	r4,-8(fp)
+ 8010e18:	80110b00 	call	80110b0 <OS_EventTaskRemove>
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {   /* Remove this task from events' wait lists    */
+ 8010e1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010e20:	10800817 	ldw	r2,32(r2)
+ 8010e24:	10000826 	beq	r2,zero,8010e48 <OS_EventTaskRdy+0x170>
+        OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr);
+ 8010e28:	e0bffe17 	ldw	r2,-8(fp)
+ 8010e2c:	10800817 	ldw	r2,32(r2)
+ 8010e30:	100b883a 	mov	r5,r2
+ 8010e34:	e13ffe17 	ldw	r4,-8(fp)
+ 8010e38:	80111600 	call	8011160 <OS_EventTaskRemoveMulti>
+        ptcb->OSTCBEventPtr       = (OS_EVENT  *)pevent;/* Return event as first multi-pend event ready*/
+ 8010e3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8010e40:	e0fffd17 	ldw	r3,-12(fp)
+ 8010e44:	10c00715 	stw	r3,28(r2)
+    }
+#endif
+
+    return (prio);
+ 8010e48:	e0bfff43 	ldbu	r2,-3(fp)
+}
+ 8010e4c:	e037883a 	mov	sp,fp
+ 8010e50:	dfc00117 	ldw	ra,4(sp)
+ 8010e54:	df000017 	ldw	fp,0(sp)
+ 8010e58:	dec00204 	addi	sp,sp,8
+ 8010e5c:	f800283a 	ret
+
+08010e60 <OS_EventTaskWait>:
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventTaskWait (OS_EVENT *pevent)
+{
+ 8010e60:	defffd04 	addi	sp,sp,-12
+ 8010e64:	df000215 	stw	fp,8(sp)
+ 8010e68:	df000204 	addi	fp,sp,8
+ 8010e6c:	e13ffe15 	stw	r4,-8(fp)
+    INT8U  y;
+
+
+    OSTCBCur->OSTCBEventPtr               = pevent;                 /* Store ptr to ECB in TCB         */
+ 8010e70:	d0a05817 	ldw	r2,-32416(gp)
+ 8010e74:	e0fffe17 	ldw	r3,-8(fp)
+ 8010e78:	10c00715 	stw	r3,28(r2)
+
+    pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX;    /* Put task in waiting list        */
+ 8010e7c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010e80:	10800d03 	ldbu	r2,52(r2)
+ 8010e84:	10803fcc 	andi	r2,r2,255
+ 8010e88:	e0fffe17 	ldw	r3,-8(fp)
+ 8010e8c:	1885883a 	add	r2,r3,r2
+ 8010e90:	110002c3 	ldbu	r4,11(r2)
+ 8010e94:	d0a05817 	ldw	r2,-32416(gp)
+ 8010e98:	10c00d43 	ldbu	r3,53(r2)
+ 8010e9c:	d0a05817 	ldw	r2,-32416(gp)
+ 8010ea0:	10800d03 	ldbu	r2,52(r2)
+ 8010ea4:	10803fcc 	andi	r2,r2,255
+ 8010ea8:	20c6b03a 	or	r3,r4,r3
+ 8010eac:	1809883a 	mov	r4,r3
+ 8010eb0:	e0fffe17 	ldw	r3,-8(fp)
+ 8010eb4:	1885883a 	add	r2,r3,r2
+ 8010eb8:	110002c5 	stb	r4,11(r2)
+    pevent->OSEventGrp                   |= OSTCBCur->OSTCBBitY;
+ 8010ebc:	e0bffe17 	ldw	r2,-8(fp)
+ 8010ec0:	10c00283 	ldbu	r3,10(r2)
+ 8010ec4:	d0a05817 	ldw	r2,-32416(gp)
+ 8010ec8:	10800d83 	ldbu	r2,54(r2)
+ 8010ecc:	1884b03a 	or	r2,r3,r2
+ 8010ed0:	1007883a 	mov	r3,r2
+ 8010ed4:	e0bffe17 	ldw	r2,-8(fp)
+ 8010ed8:	10c00285 	stb	r3,10(r2)
+
+    y             =  OSTCBCur->OSTCBY;            /* Task no longer ready                              */
+ 8010edc:	d0a05817 	ldw	r2,-32416(gp)
+ 8010ee0:	10800d03 	ldbu	r2,52(r2)
+ 8010ee4:	e0bfffc5 	stb	r2,-1(fp)
+    OSRdyTbl[y]  &= ~OSTCBCur->OSTCBBitX;
+ 8010ee8:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8010eec:	d0a05544 	addi	r2,gp,-32427
+ 8010ef0:	1885883a 	add	r2,r3,r2
+ 8010ef4:	10800003 	ldbu	r2,0(r2)
+ 8010ef8:	1007883a 	mov	r3,r2
+ 8010efc:	d0a05817 	ldw	r2,-32416(gp)
+ 8010f00:	10800d43 	ldbu	r2,53(r2)
+ 8010f04:	0084303a 	nor	r2,zero,r2
+ 8010f08:	1884703a 	and	r2,r3,r2
+ 8010f0c:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8010f10:	1009883a 	mov	r4,r2
+ 8010f14:	d0a05544 	addi	r2,gp,-32427
+ 8010f18:	1885883a 	add	r2,r3,r2
+ 8010f1c:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[y] == 0) {
+ 8010f20:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8010f24:	d0a05544 	addi	r2,gp,-32427
+ 8010f28:	1885883a 	add	r2,r3,r2
+ 8010f2c:	10800003 	ldbu	r2,0(r2)
+ 8010f30:	10803fcc 	andi	r2,r2,255
+ 8010f34:	1000071e 	bne	r2,zero,8010f54 <OS_EventTaskWait+0xf4>
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;         /* Clear event grp bit if this was only task pending */
+ 8010f38:	d0a05817 	ldw	r2,-32416(gp)
+ 8010f3c:	10800d83 	ldbu	r2,54(r2)
+ 8010f40:	0084303a 	nor	r2,zero,r2
+ 8010f44:	1007883a 	mov	r3,r2
+ 8010f48:	d0a05503 	ldbu	r2,-32428(gp)
+ 8010f4c:	1884703a 	and	r2,r3,r2
+ 8010f50:	d0a05505 	stb	r2,-32428(gp)
+    }
+}
+ 8010f54:	0001883a 	nop
+ 8010f58:	e037883a 	mov	sp,fp
+ 8010f5c:	df000017 	ldw	fp,0(sp)
+ 8010f60:	dec00104 	addi	sp,sp,4
+ 8010f64:	f800283a 	ret
+
+08010f68 <OS_EventTaskWaitMulti>:
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+void  OS_EventTaskWaitMulti (OS_EVENT **pevents_wait)
+{
+ 8010f68:	defffb04 	addi	sp,sp,-20
+ 8010f6c:	df000415 	stw	fp,16(sp)
+ 8010f70:	df000404 	addi	fp,sp,16
+ 8010f74:	e13ffc15 	stw	r4,-16(fp)
+    OS_EVENT **pevents;
+    OS_EVENT  *pevent;
+    INT8U      y;
+
+
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;
+ 8010f78:	d0a05817 	ldw	r2,-32416(gp)
+ 8010f7c:	10000715 	stw	zero,28(r2)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait;       /* Store ptr to ECBs in TCB        */
+ 8010f80:	d0a05817 	ldw	r2,-32416(gp)
+ 8010f84:	e0fffc17 	ldw	r3,-16(fp)
+ 8010f88:	10c00815 	stw	r3,32(r2)
+
+    pevents =  pevents_wait;
+ 8010f8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8010f90:	e0bfff15 	stw	r2,-4(fp)
+    pevent  = *pevents;
+ 8010f94:	e0bfff17 	ldw	r2,-4(fp)
+ 8010f98:	10800017 	ldw	r2,0(r2)
+ 8010f9c:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                               /* Put task in waiting lists       */
+ 8010fa0:	00001e06 	br	801101c <OS_EventTaskWaitMulti+0xb4>
+        pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX;
+ 8010fa4:	d0a05817 	ldw	r2,-32416(gp)
+ 8010fa8:	10800d03 	ldbu	r2,52(r2)
+ 8010fac:	10803fcc 	andi	r2,r2,255
+ 8010fb0:	e0fffe17 	ldw	r3,-8(fp)
+ 8010fb4:	1885883a 	add	r2,r3,r2
+ 8010fb8:	110002c3 	ldbu	r4,11(r2)
+ 8010fbc:	d0a05817 	ldw	r2,-32416(gp)
+ 8010fc0:	10c00d43 	ldbu	r3,53(r2)
+ 8010fc4:	d0a05817 	ldw	r2,-32416(gp)
+ 8010fc8:	10800d03 	ldbu	r2,52(r2)
+ 8010fcc:	10803fcc 	andi	r2,r2,255
+ 8010fd0:	20c6b03a 	or	r3,r4,r3
+ 8010fd4:	1809883a 	mov	r4,r3
+ 8010fd8:	e0fffe17 	ldw	r3,-8(fp)
+ 8010fdc:	1885883a 	add	r2,r3,r2
+ 8010fe0:	110002c5 	stb	r4,11(r2)
+        pevent->OSEventGrp                   |= OSTCBCur->OSTCBBitY;
+ 8010fe4:	e0bffe17 	ldw	r2,-8(fp)
+ 8010fe8:	10c00283 	ldbu	r3,10(r2)
+ 8010fec:	d0a05817 	ldw	r2,-32416(gp)
+ 8010ff0:	10800d83 	ldbu	r2,54(r2)
+ 8010ff4:	1884b03a 	or	r2,r3,r2
+ 8010ff8:	1007883a 	mov	r3,r2
+ 8010ffc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011000:	10c00285 	stb	r3,10(r2)
+        pevents++;
+ 8011004:	e0bfff17 	ldw	r2,-4(fp)
+ 8011008:	10800104 	addi	r2,r2,4
+ 801100c:	e0bfff15 	stw	r2,-4(fp)
+        pevent = *pevents;
+ 8011010:	e0bfff17 	ldw	r2,-4(fp)
+ 8011014:	10800017 	ldw	r2,0(r2)
+ 8011018:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                               /* Put task in waiting lists       */
+ 801101c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011020:	103fe01e 	bne	r2,zero,8010fa4 <OS_EventTaskWaitMulti+0x3c>
+    }
+
+    y             =  OSTCBCur->OSTCBY;            /* Task no longer ready                              */
+ 8011024:	d0a05817 	ldw	r2,-32416(gp)
+ 8011028:	10800d03 	ldbu	r2,52(r2)
+ 801102c:	e0bffdc5 	stb	r2,-9(fp)
+    OSRdyTbl[y]  &= ~OSTCBCur->OSTCBBitX;
+ 8011030:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8011034:	d0a05544 	addi	r2,gp,-32427
+ 8011038:	1885883a 	add	r2,r3,r2
+ 801103c:	10800003 	ldbu	r2,0(r2)
+ 8011040:	1007883a 	mov	r3,r2
+ 8011044:	d0a05817 	ldw	r2,-32416(gp)
+ 8011048:	10800d43 	ldbu	r2,53(r2)
+ 801104c:	0084303a 	nor	r2,zero,r2
+ 8011050:	1884703a 	and	r2,r3,r2
+ 8011054:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8011058:	1009883a 	mov	r4,r2
+ 801105c:	d0a05544 	addi	r2,gp,-32427
+ 8011060:	1885883a 	add	r2,r3,r2
+ 8011064:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[y] == 0) {
+ 8011068:	e0fffdc3 	ldbu	r3,-9(fp)
+ 801106c:	d0a05544 	addi	r2,gp,-32427
+ 8011070:	1885883a 	add	r2,r3,r2
+ 8011074:	10800003 	ldbu	r2,0(r2)
+ 8011078:	10803fcc 	andi	r2,r2,255
+ 801107c:	1000071e 	bne	r2,zero,801109c <OS_EventTaskWaitMulti+0x134>
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;         /* Clear event grp bit if this was only task pending */
+ 8011080:	d0a05817 	ldw	r2,-32416(gp)
+ 8011084:	10800d83 	ldbu	r2,54(r2)
+ 8011088:	0084303a 	nor	r2,zero,r2
+ 801108c:	1007883a 	mov	r3,r2
+ 8011090:	d0a05503 	ldbu	r2,-32428(gp)
+ 8011094:	1884703a 	and	r2,r3,r2
+ 8011098:	d0a05505 	stb	r2,-32428(gp)
+    }
+}
+ 801109c:	0001883a 	nop
+ 80110a0:	e037883a 	mov	sp,fp
+ 80110a4:	df000017 	ldw	fp,0(sp)
+ 80110a8:	dec00104 	addi	sp,sp,4
+ 80110ac:	f800283a 	ret
+
+080110b0 <OS_EventTaskRemove>:
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventTaskRemove (OS_TCB   *ptcb,
+                          OS_EVENT *pevent)
+{
+ 80110b0:	defffc04 	addi	sp,sp,-16
+ 80110b4:	df000315 	stw	fp,12(sp)
+ 80110b8:	df000304 	addi	fp,sp,12
+ 80110bc:	e13ffe15 	stw	r4,-8(fp)
+ 80110c0:	e17ffd15 	stw	r5,-12(fp)
+    INT8U  y;
+
+
+    y                       =  ptcb->OSTCBY;
+ 80110c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80110c8:	10800d03 	ldbu	r2,52(r2)
+ 80110cc:	e0bfffc5 	stb	r2,-1(fp)
+    pevent->OSEventTbl[y]  &= ~ptcb->OSTCBBitX;         /* Remove task from wait list                  */
+ 80110d0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80110d4:	e0fffd17 	ldw	r3,-12(fp)
+ 80110d8:	1885883a 	add	r2,r3,r2
+ 80110dc:	108002c3 	ldbu	r2,11(r2)
+ 80110e0:	1007883a 	mov	r3,r2
+ 80110e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80110e8:	10800d43 	ldbu	r2,53(r2)
+ 80110ec:	0084303a 	nor	r2,zero,r2
+ 80110f0:	1884703a 	and	r2,r3,r2
+ 80110f4:	1007883a 	mov	r3,r2
+ 80110f8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80110fc:	1809883a 	mov	r4,r3
+ 8011100:	e0fffd17 	ldw	r3,-12(fp)
+ 8011104:	1885883a 	add	r2,r3,r2
+ 8011108:	110002c5 	stb	r4,11(r2)
+    if (pevent->OSEventTbl[y] == 0) {
+ 801110c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8011110:	e0fffd17 	ldw	r3,-12(fp)
+ 8011114:	1885883a 	add	r2,r3,r2
+ 8011118:	108002c3 	ldbu	r2,11(r2)
+ 801111c:	10803fcc 	andi	r2,r2,255
+ 8011120:	10000a1e 	bne	r2,zero,801114c <OS_EventTaskRemove+0x9c>
+        pevent->OSEventGrp &= ~ptcb->OSTCBBitY;
+ 8011124:	e0bffd17 	ldw	r2,-12(fp)
+ 8011128:	10800283 	ldbu	r2,10(r2)
+ 801112c:	1007883a 	mov	r3,r2
+ 8011130:	e0bffe17 	ldw	r2,-8(fp)
+ 8011134:	10800d83 	ldbu	r2,54(r2)
+ 8011138:	0084303a 	nor	r2,zero,r2
+ 801113c:	1884703a 	and	r2,r3,r2
+ 8011140:	1007883a 	mov	r3,r2
+ 8011144:	e0bffd17 	ldw	r2,-12(fp)
+ 8011148:	10c00285 	stb	r3,10(r2)
+    }
+}
+ 801114c:	0001883a 	nop
+ 8011150:	e037883a 	mov	sp,fp
+ 8011154:	df000017 	ldw	fp,0(sp)
+ 8011158:	dec00104 	addi	sp,sp,4
+ 801115c:	f800283a 	ret
+
+08011160 <OS_EventTaskRemoveMulti>:
+*********************************************************************************************************
+*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+void  OS_EventTaskRemoveMulti (OS_TCB    *ptcb,
+                               OS_EVENT **pevents_multi)
+{
+ 8011160:	defffa04 	addi	sp,sp,-24
+ 8011164:	df000515 	stw	fp,20(sp)
+ 8011168:	df000504 	addi	fp,sp,20
+ 801116c:	e13ffc15 	stw	r4,-16(fp)
+ 8011170:	e17ffb15 	stw	r5,-20(fp)
+    INT16U     bity;
+    INT16U     bitx;
+#endif
+
+
+    y       =  ptcb->OSTCBY;
+ 8011174:	e0bffc17 	ldw	r2,-16(fp)
+ 8011178:	10800d03 	ldbu	r2,52(r2)
+ 801117c:	e0bffdc5 	stb	r2,-9(fp)
+    bity    =  ptcb->OSTCBBitY;
+ 8011180:	e0bffc17 	ldw	r2,-16(fp)
+ 8011184:	10800d83 	ldbu	r2,54(r2)
+ 8011188:	e0bffd85 	stb	r2,-10(fp)
+    bitx    =  ptcb->OSTCBBitX;
+ 801118c:	e0bffc17 	ldw	r2,-16(fp)
+ 8011190:	10800d43 	ldbu	r2,53(r2)
+ 8011194:	e0bffd45 	stb	r2,-11(fp)
+    pevents =  pevents_multi;
+ 8011198:	e0bffb17 	ldw	r2,-20(fp)
+ 801119c:	e0bfff15 	stw	r2,-4(fp)
+    pevent  = *pevents;
+ 80111a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80111a4:	10800017 	ldw	r2,0(r2)
+ 80111a8:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                   /* Remove task from all events' wait lists     */
+ 80111ac:	00002306 	br	801123c <OS_EventTaskRemoveMulti+0xdc>
+        pevent->OSEventTbl[y]  &= ~bitx;
+ 80111b0:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80111b4:	e0fffe17 	ldw	r3,-8(fp)
+ 80111b8:	1885883a 	add	r2,r3,r2
+ 80111bc:	108002c3 	ldbu	r2,11(r2)
+ 80111c0:	1007883a 	mov	r3,r2
+ 80111c4:	e0bffd43 	ldbu	r2,-11(fp)
+ 80111c8:	0084303a 	nor	r2,zero,r2
+ 80111cc:	1884703a 	and	r2,r3,r2
+ 80111d0:	1007883a 	mov	r3,r2
+ 80111d4:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80111d8:	1809883a 	mov	r4,r3
+ 80111dc:	e0fffe17 	ldw	r3,-8(fp)
+ 80111e0:	1885883a 	add	r2,r3,r2
+ 80111e4:	110002c5 	stb	r4,11(r2)
+        if (pevent->OSEventTbl[y] == 0) {
+ 80111e8:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80111ec:	e0fffe17 	ldw	r3,-8(fp)
+ 80111f0:	1885883a 	add	r2,r3,r2
+ 80111f4:	108002c3 	ldbu	r2,11(r2)
+ 80111f8:	10803fcc 	andi	r2,r2,255
+ 80111fc:	1000091e 	bne	r2,zero,8011224 <OS_EventTaskRemoveMulti+0xc4>
+            pevent->OSEventGrp &= ~bity;
+ 8011200:	e0bffe17 	ldw	r2,-8(fp)
+ 8011204:	10800283 	ldbu	r2,10(r2)
+ 8011208:	1007883a 	mov	r3,r2
+ 801120c:	e0bffd83 	ldbu	r2,-10(fp)
+ 8011210:	0084303a 	nor	r2,zero,r2
+ 8011214:	1884703a 	and	r2,r3,r2
+ 8011218:	1007883a 	mov	r3,r2
+ 801121c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011220:	10c00285 	stb	r3,10(r2)
+        }
+        pevents++;
+ 8011224:	e0bfff17 	ldw	r2,-4(fp)
+ 8011228:	10800104 	addi	r2,r2,4
+ 801122c:	e0bfff15 	stw	r2,-4(fp)
+        pevent = *pevents;
+ 8011230:	e0bfff17 	ldw	r2,-4(fp)
+ 8011234:	10800017 	ldw	r2,0(r2)
+ 8011238:	e0bffe15 	stw	r2,-8(fp)
+    while (pevent != (OS_EVENT *)0) {                   /* Remove task from all events' wait lists     */
+ 801123c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011240:	103fdb1e 	bne	r2,zero,80111b0 <OS_EventTaskRemoveMulti+0x50>
+    }
+}
+ 8011244:	0001883a 	nop
+ 8011248:	e037883a 	mov	sp,fp
+ 801124c:	df000017 	ldw	fp,0(sp)
+ 8011250:	dec00104 	addi	sp,sp,4
+ 8011254:	f800283a 	ret
+
+08011258 <OS_EventWaitListInit>:
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventWaitListInit (OS_EVENT *pevent)
+{
+ 8011258:	defffc04 	addi	sp,sp,-16
+ 801125c:	df000315 	stw	fp,12(sp)
+ 8011260:	df000304 	addi	fp,sp,12
+ 8011264:	e13ffd15 	stw	r4,-12(fp)
+    INT16U *ptbl;
+#endif
+    INT8U   i;
+
+
+    pevent->OSEventGrp = 0;                      /* No task waiting on event                           */
+ 8011268:	e0bffd17 	ldw	r2,-12(fp)
+ 801126c:	10000285 	stb	zero,10(r2)
+    ptbl               = &pevent->OSEventTbl[0];
+ 8011270:	e0bffd17 	ldw	r2,-12(fp)
+ 8011274:	108002c4 	addi	r2,r2,11
+ 8011278:	e0bfff15 	stw	r2,-4(fp)
+
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 801127c:	e03ffec5 	stb	zero,-5(fp)
+ 8011280:	00000706 	br	80112a0 <OS_EventWaitListInit+0x48>
+        *ptbl++ = 0;
+ 8011284:	e0bfff17 	ldw	r2,-4(fp)
+ 8011288:	10c00044 	addi	r3,r2,1
+ 801128c:	e0ffff15 	stw	r3,-4(fp)
+ 8011290:	10000005 	stb	zero,0(r2)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8011294:	e0bffec3 	ldbu	r2,-5(fp)
+ 8011298:	10800044 	addi	r2,r2,1
+ 801129c:	e0bffec5 	stb	r2,-5(fp)
+ 80112a0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80112a4:	108000f0 	cmpltui	r2,r2,3
+ 80112a8:	103ff61e 	bne	r2,zero,8011284 <OS_EventWaitListInit+0x2c>
+    }
+}
+ 80112ac:	0001883a 	nop
+ 80112b0:	e037883a 	mov	sp,fp
+ 80112b4:	df000017 	ldw	fp,0(sp)
+ 80112b8:	dec00104 	addi	sp,sp,4
+ 80112bc:	f800283a 	ret
+
+080112c0 <OS_InitEventList>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitEventList (void)
+{
+ 80112c0:	defffb04 	addi	sp,sp,-20
+ 80112c4:	dfc00415 	stw	ra,16(sp)
+ 80112c8:	df000315 	stw	fp,12(sp)
+ 80112cc:	df000304 	addi	fp,sp,12
+    INT16U     i;
+    OS_EVENT  *pevent1;
+    OS_EVENT  *pevent2;
+
+
+    OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table                   */
+ 80112d0:	0142d004 	movi	r5,2880
+ 80112d4:	010201b4 	movhi	r4,2054
+ 80112d8:	2131eb04 	addi	r4,r4,-14420
+ 80112dc:	80115b00 	call	80115b0 <OS_MemClr>
+    pevent1 = &OSEventTbl[0];
+ 80112e0:	008201b4 	movhi	r2,2054
+ 80112e4:	10b1eb04 	addi	r2,r2,-14420
+ 80112e8:	e0bffe15 	stw	r2,-8(fp)
+    pevent2 = &OSEventTbl[1];
+ 80112ec:	008201b4 	movhi	r2,2054
+ 80112f0:	10b1f704 	addi	r2,r2,-14372
+ 80112f4:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_EVENTS - 1); i++) {             /* Init. list of free EVENT control blocks */
+ 80112f8:	e03fff8d 	sth	zero,-2(fp)
+ 80112fc:	00001306 	br	801134c <OS_InitEventList+0x8c>
+        pevent1->OSEventType    = OS_EVENT_TYPE_UNUSED;
+ 8011300:	e0bffe17 	ldw	r2,-8(fp)
+ 8011304:	10000005 	stb	zero,0(r2)
+        pevent1->OSEventPtr     = pevent2;
+ 8011308:	e0bffe17 	ldw	r2,-8(fp)
+ 801130c:	e0fffd17 	ldw	r3,-12(fp)
+ 8011310:	10c00115 	stw	r3,4(r2)
+#if OS_EVENT_NAME_SIZE > 1
+        pevent1->OSEventName[0] = '?';                      /* Unknown name                            */
+ 8011314:	e0bffe17 	ldw	r2,-8(fp)
+ 8011318:	00c00fc4 	movi	r3,63
+ 801131c:	10c00385 	stb	r3,14(r2)
+        pevent1->OSEventName[1] = OS_ASCII_NUL;
+ 8011320:	e0bffe17 	ldw	r2,-8(fp)
+ 8011324:	100003c5 	stb	zero,15(r2)
+#endif
+        pevent1++;
+ 8011328:	e0bffe17 	ldw	r2,-8(fp)
+ 801132c:	10800c04 	addi	r2,r2,48
+ 8011330:	e0bffe15 	stw	r2,-8(fp)
+        pevent2++;
+ 8011334:	e0bffd17 	ldw	r2,-12(fp)
+ 8011338:	10800c04 	addi	r2,r2,48
+ 801133c:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_EVENTS - 1); i++) {             /* Init. list of free EVENT control blocks */
+ 8011340:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011344:	10800044 	addi	r2,r2,1
+ 8011348:	e0bfff8d 	sth	r2,-2(fp)
+ 801134c:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011350:	10800ef0 	cmpltui	r2,r2,59
+ 8011354:	103fea1e 	bne	r2,zero,8011300 <OS_InitEventList+0x40>
+    }
+    pevent1->OSEventType            = OS_EVENT_TYPE_UNUSED;
+ 8011358:	e0bffe17 	ldw	r2,-8(fp)
+ 801135c:	10000005 	stb	zero,0(r2)
+    pevent1->OSEventPtr             = (OS_EVENT *)0;
+ 8011360:	e0bffe17 	ldw	r2,-8(fp)
+ 8011364:	10000115 	stw	zero,4(r2)
+#if OS_EVENT_NAME_SIZE > 1
+    pevent1->OSEventName[0]         = '?';
+ 8011368:	e0bffe17 	ldw	r2,-8(fp)
+ 801136c:	00c00fc4 	movi	r3,63
+ 8011370:	10c00385 	stb	r3,14(r2)
+    pevent1->OSEventName[1]         = OS_ASCII_NUL;
+ 8011374:	e0bffe17 	ldw	r2,-8(fp)
+ 8011378:	100003c5 	stb	zero,15(r2)
+#endif
+    OSEventFreeList                 = &OSEventTbl[0];
+ 801137c:	008201b4 	movhi	r2,2054
+ 8011380:	10b1eb04 	addi	r2,r2,-14420
+ 8011384:	d0a05615 	stw	r2,-32424(gp)
+    OSEventFreeList->OSEventName[0] = '?';                  /* Unknown name                            */
+    OSEventFreeList->OSEventName[1] = OS_ASCII_NUL;
+#endif
+#endif
+#endif
+}
+ 8011388:	0001883a 	nop
+ 801138c:	e037883a 	mov	sp,fp
+ 8011390:	dfc00117 	ldw	ra,4(sp)
+ 8011394:	df000017 	ldw	fp,0(sp)
+ 8011398:	dec00204 	addi	sp,sp,8
+ 801139c:	f800283a 	ret
+
+080113a0 <OS_InitMisc>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitMisc (void)
+{
+ 80113a0:	deffff04 	addi	sp,sp,-4
+ 80113a4:	df000015 	stw	fp,0(sp)
+ 80113a8:	d839883a 	mov	fp,sp
+#if OS_TIME_GET_SET_EN > 0
+    OSTime        = 0L;                                    /* Clear the 32-bit system clock            */
+ 80113ac:	d0205915 	stw	zero,-32412(gp)
+#endif
+
+    OSIntNesting  = 0;                                     /* Clear the interrupt nesting counter      */
+ 80113b0:	d0205705 	stb	zero,-32420(gp)
+    OSLockNesting = 0;                                     /* Clear the scheduling lock counter        */
+ 80113b4:	d0204b05 	stb	zero,-32468(gp)
+
+    OSTaskCtr     = 0;                                     /* Clear the number of tasks                */
+ 80113b8:	d0205105 	stb	zero,-32444(gp)
+
+    OSRunning     = OS_FALSE;                              /* Indicate that multitasking not started   */
+ 80113bc:	d0204b45 	stb	zero,-32467(gp)
+
+    OSCtxSwCtr    = 0;                                     /* Clear the context switch counter         */
+ 80113c0:	d0204f15 	stw	zero,-32452(gp)
+    OSIdleCtr     = 0L;                                    /* Clear the 32-bit idle counter            */
+ 80113c4:	d0204c15 	stw	zero,-32464(gp)
+#if OS_TASK_STAT_EN > 0
+    OSIdleCtrRun  = 0L;
+    OSIdleCtrMax  = 0L;
+    OSStatRdy     = OS_FALSE;                              /* Statistic task is not ready              */
+#endif
+}
+ 80113c8:	0001883a 	nop
+ 80113cc:	e037883a 	mov	sp,fp
+ 80113d0:	df000017 	ldw	fp,0(sp)
+ 80113d4:	dec00104 	addi	sp,sp,4
+ 80113d8:	f800283a 	ret
+
+080113dc <OS_InitRdyList>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitRdyList (void)
+{
+ 80113dc:	defffd04 	addi	sp,sp,-12
+ 80113e0:	df000215 	stw	fp,8(sp)
+ 80113e4:	df000204 	addi	fp,sp,8
+#else
+    INT16U  *prdytbl;
+#endif
+
+
+    OSRdyGrp      = 0;                                     /* Clear the ready list                     */
+ 80113e8:	d0205505 	stb	zero,-32428(gp)
+    prdytbl       = &OSRdyTbl[0];
+ 80113ec:	d0a05544 	addi	r2,gp,-32427
+ 80113f0:	e0bffe15 	stw	r2,-8(fp)
+    for (i = 0; i < OS_RDY_TBL_SIZE; i++) {
+ 80113f4:	e03fffc5 	stb	zero,-1(fp)
+ 80113f8:	00000706 	br	8011418 <OS_InitRdyList+0x3c>
+        *prdytbl++ = 0;
+ 80113fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011400:	10c00044 	addi	r3,r2,1
+ 8011404:	e0fffe15 	stw	r3,-8(fp)
+ 8011408:	10000005 	stb	zero,0(r2)
+    for (i = 0; i < OS_RDY_TBL_SIZE; i++) {
+ 801140c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8011410:	10800044 	addi	r2,r2,1
+ 8011414:	e0bfffc5 	stb	r2,-1(fp)
+ 8011418:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801141c:	108000f0 	cmpltui	r2,r2,3
+ 8011420:	103ff61e 	bne	r2,zero,80113fc <OS_InitRdyList+0x20>
+    }
+
+    OSPrioCur     = 0;
+ 8011424:	d0204d45 	stb	zero,-32459(gp)
+    OSPrioHighRdy = 0;
+ 8011428:	d0204d05 	stb	zero,-32460(gp)
+
+    OSTCBHighRdy  = (OS_TCB *)0;
+ 801142c:	d0205315 	stw	zero,-32436(gp)
+    OSTCBCur      = (OS_TCB *)0;
+ 8011430:	d0205815 	stw	zero,-32416(gp)
+}
+ 8011434:	0001883a 	nop
+ 8011438:	e037883a 	mov	sp,fp
+ 801143c:	df000017 	ldw	fp,0(sp)
+ 8011440:	dec00104 	addi	sp,sp,4
+ 8011444:	f800283a 	ret
+
+08011448 <OS_InitTaskIdle>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitTaskIdle (void)
+{
+ 8011448:	defff804 	addi	sp,sp,-32
+ 801144c:	dfc00715 	stw	ra,28(sp)
+ 8011450:	df000615 	stw	fp,24(sp)
+ 8011454:	df000604 	addi	fp,sp,24
+#endif
+
+
+#if OS_TASK_CREATE_EXT_EN > 0
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreateExt(OS_TaskIdle,
+ 8011458:	008000c4 	movi	r2,3
+ 801145c:	d8800415 	stw	r2,16(sp)
+ 8011460:	d8000315 	stw	zero,12(sp)
+ 8011464:	00808004 	movi	r2,512
+ 8011468:	d8800215 	stw	r2,8(sp)
+ 801146c:	008201b4 	movhi	r2,2054
+ 8011470:	10afeb04 	addi	r2,r2,-16468
+ 8011474:	d8800115 	stw	r2,4(sp)
+ 8011478:	00bfffd4 	movui	r2,65535
+ 801147c:	d8800015 	stw	r2,0(sp)
+ 8011480:	01c00504 	movi	r7,20
+ 8011484:	018201b4 	movhi	r6,2054
+ 8011488:	31b1ea04 	addi	r6,r6,-14424
+ 801148c:	000b883a 	mov	r5,zero
+ 8011490:	01020074 	movhi	r4,2049
+ 8011494:	21061a04 	addi	r4,r4,6248
+ 8011498:	801664c0 	call	801664c <OSTaskCreateExt>
+                       OS_TASK_IDLE_PRIO);
+    #endif
+#endif
+
+#if OS_TASK_NAME_SIZE > 14
+    OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err);
+ 801149c:	e0bfffc4 	addi	r2,fp,-1
+ 80114a0:	100d883a 	mov	r6,r2
+ 80114a4:	01420134 	movhi	r5,2052
+ 80114a8:	295e0d04 	addi	r5,r5,30772
+ 80114ac:	01000504 	movi	r4,20
+ 80114b0:	8016d640 	call	8016d64 <OSTaskNameSet>
+#else
+#if OS_TASK_NAME_SIZE > 7
+    OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err);
+#endif
+#endif
+}
+ 80114b4:	0001883a 	nop
+ 80114b8:	e037883a 	mov	sp,fp
+ 80114bc:	dfc00117 	ldw	ra,4(sp)
+ 80114c0:	df000017 	ldw	fp,0(sp)
+ 80114c4:	dec00204 	addi	sp,sp,8
+ 80114c8:	f800283a 	ret
+
+080114cc <OS_InitTCBList>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitTCBList (void)
+{
+ 80114cc:	defffb04 	addi	sp,sp,-20
+ 80114d0:	dfc00415 	stw	ra,16(sp)
+ 80114d4:	df000315 	stw	fp,12(sp)
+ 80114d8:	df000304 	addi	fp,sp,12
+    INT8U    i;
+    OS_TCB  *ptcb1;
+    OS_TCB  *ptcb2;
+
+
+    OS_MemClr((INT8U *)&OSTCBTbl[0],     sizeof(OSTCBTbl));      /* Clear all the TCBs                 */
+ 80114dc:	0140a204 	movi	r5,648
+ 80114e0:	010201b4 	movhi	r4,2054
+ 80114e4:	2134bb04 	addi	r4,r4,-11540
+ 80114e8:	80115b00 	call	80115b0 <OS_MemClr>
+    OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl));  /* Clear the priority table           */
+ 80114ec:	01401504 	movi	r5,84
+ 80114f0:	010201b4 	movhi	r4,2054
+ 80114f4:	21355d04 	addi	r4,r4,-10892
+ 80114f8:	80115b00 	call	80115b0 <OS_MemClr>
+    ptcb1 = &OSTCBTbl[0];
+ 80114fc:	008201b4 	movhi	r2,2054
+ 8011500:	10b4bb04 	addi	r2,r2,-11540
+ 8011504:	e0bffe15 	stw	r2,-8(fp)
+    ptcb2 = &OSTCBTbl[1];
+ 8011508:	008201b4 	movhi	r2,2054
+ 801150c:	10b4d604 	addi	r2,r2,-11432
+ 8011510:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) {  /* Init. list of free TCBs            */
+ 8011514:	e03fffc5 	stb	zero,-1(fp)
+ 8011518:	00001106 	br	8011560 <OS_InitTCBList+0x94>
+        ptcb1->OSTCBNext = ptcb2;
+ 801151c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011520:	e0fffd17 	ldw	r3,-12(fp)
+ 8011524:	10c00515 	stw	r3,20(r2)
+#if OS_TASK_NAME_SIZE > 1
+        ptcb1->OSTCBTaskName[0] = '?';                           /* Unknown name                       */
+ 8011528:	e0bffe17 	ldw	r2,-8(fp)
+ 801152c:	00c00fc4 	movi	r3,63
+ 8011530:	10c01305 	stb	r3,76(r2)
+        ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL;
+ 8011534:	e0bffe17 	ldw	r2,-8(fp)
+ 8011538:	10001345 	stb	zero,77(r2)
+#endif
+        ptcb1++;
+ 801153c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011540:	10801b04 	addi	r2,r2,108
+ 8011544:	e0bffe15 	stw	r2,-8(fp)
+        ptcb2++;
+ 8011548:	e0bffd17 	ldw	r2,-12(fp)
+ 801154c:	10801b04 	addi	r2,r2,108
+ 8011550:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) {  /* Init. list of free TCBs            */
+ 8011554:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8011558:	10800044 	addi	r2,r2,1
+ 801155c:	e0bfffc5 	stb	r2,-1(fp)
+ 8011560:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8011564:	10800170 	cmpltui	r2,r2,5
+ 8011568:	103fec1e 	bne	r2,zero,801151c <OS_InitTCBList+0x50>
+    }
+    ptcb1->OSTCBNext = (OS_TCB *)0;                              /* Last OS_TCB                        */
+ 801156c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011570:	10000515 	stw	zero,20(r2)
+#if OS_TASK_NAME_SIZE > 1
+    ptcb1->OSTCBTaskName[0] = '?';                               /* Unknown name                       */
+ 8011574:	e0bffe17 	ldw	r2,-8(fp)
+ 8011578:	00c00fc4 	movi	r3,63
+ 801157c:	10c01305 	stb	r3,76(r2)
+    ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL;
+ 8011580:	e0bffe17 	ldw	r2,-8(fp)
+ 8011584:	10001345 	stb	zero,77(r2)
+#endif
+    OSTCBList               = (OS_TCB *)0;                       /* TCB lists initializations          */
+ 8011588:	d0204e15 	stw	zero,-32456(gp)
+    OSTCBFreeList           = &OSTCBTbl[0];
+ 801158c:	008201b4 	movhi	r2,2054
+ 8011590:	10b4bb04 	addi	r2,r2,-11540
+ 8011594:	d0a05015 	stw	r2,-32448(gp)
+}
+ 8011598:	0001883a 	nop
+ 801159c:	e037883a 	mov	sp,fp
+ 80115a0:	dfc00117 	ldw	ra,4(sp)
+ 80115a4:	df000017 	ldw	fp,0(sp)
+ 80115a8:	dec00204 	addi	sp,sp,8
+ 80115ac:	f800283a 	ret
+
+080115b0 <OS_MemClr>:
+*                 of the alignment of the destination.
+*********************************************************************************************************
+*/
+
+void  OS_MemClr (INT8U *pdest, INT16U size)
+{
+ 80115b0:	defffd04 	addi	sp,sp,-12
+ 80115b4:	df000215 	stw	fp,8(sp)
+ 80115b8:	df000204 	addi	fp,sp,8
+ 80115bc:	e13fff15 	stw	r4,-4(fp)
+ 80115c0:	2805883a 	mov	r2,r5
+ 80115c4:	e0bffe0d 	sth	r2,-8(fp)
+    while (size > 0) {
+ 80115c8:	00000706 	br	80115e8 <OS_MemClr+0x38>
+        *pdest++ = (INT8U)0;
+ 80115cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80115d0:	10c00044 	addi	r3,r2,1
+ 80115d4:	e0ffff15 	stw	r3,-4(fp)
+ 80115d8:	10000005 	stb	zero,0(r2)
+        size--;
+ 80115dc:	e0bffe0b 	ldhu	r2,-8(fp)
+ 80115e0:	10bfffc4 	addi	r2,r2,-1
+ 80115e4:	e0bffe0d 	sth	r2,-8(fp)
+    while (size > 0) {
+ 80115e8:	e0bffe0b 	ldhu	r2,-8(fp)
+ 80115ec:	103ff71e 	bne	r2,zero,80115cc <OS_MemClr+0x1c>
+    }
+}
+ 80115f0:	0001883a 	nop
+ 80115f4:	e037883a 	mov	sp,fp
+ 80115f8:	df000017 	ldw	fp,0(sp)
+ 80115fc:	dec00104 	addi	sp,sp,4
+ 8011600:	f800283a 	ret
+
+08011604 <OS_MemCopy>:
+*                 of the alignment of the source and destination.
+*********************************************************************************************************
+*/
+
+void  OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size)
+{
+ 8011604:	defffc04 	addi	sp,sp,-16
+ 8011608:	df000315 	stw	fp,12(sp)
+ 801160c:	df000304 	addi	fp,sp,12
+ 8011610:	e13fff15 	stw	r4,-4(fp)
+ 8011614:	e17ffe15 	stw	r5,-8(fp)
+ 8011618:	3005883a 	mov	r2,r6
+ 801161c:	e0bffd0d 	sth	r2,-12(fp)
+    while (size > 0) {
+ 8011620:	00000b06 	br	8011650 <OS_MemCopy+0x4c>
+        *pdest++ = *psrc++;
+ 8011624:	e0fffe17 	ldw	r3,-8(fp)
+ 8011628:	18800044 	addi	r2,r3,1
+ 801162c:	e0bffe15 	stw	r2,-8(fp)
+ 8011630:	e0bfff17 	ldw	r2,-4(fp)
+ 8011634:	11000044 	addi	r4,r2,1
+ 8011638:	e13fff15 	stw	r4,-4(fp)
+ 801163c:	18c00003 	ldbu	r3,0(r3)
+ 8011640:	10c00005 	stb	r3,0(r2)
+        size--;
+ 8011644:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8011648:	10bfffc4 	addi	r2,r2,-1
+ 801164c:	e0bffd0d 	sth	r2,-12(fp)
+    while (size > 0) {
+ 8011650:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8011654:	103ff31e 	bne	r2,zero,8011624 <OS_MemCopy+0x20>
+    }
+}
+ 8011658:	0001883a 	nop
+ 801165c:	e037883a 	mov	sp,fp
+ 8011660:	df000017 	ldw	fp,0(sp)
+ 8011664:	dec00104 	addi	sp,sp,4
+ 8011668:	f800283a 	ret
+
+0801166c <OS_Sched>:
+*              2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock())
+*********************************************************************************************************
+*/
+
+void  OS_Sched (void)
+{
+ 801166c:	defffb04 	addi	sp,sp,-20
+ 8011670:	dfc00415 	stw	ra,16(sp)
+ 8011674:	df000315 	stw	fp,12(sp)
+ 8011678:	df000304 	addi	fp,sp,12
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+ 801167c:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8011680:	0005303a 	rdctl	r2,status
+ 8011684:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011688:	e0fffe17 	ldw	r3,-8(fp)
+ 801168c:	00bfff84 	movi	r2,-2
+ 8011690:	1884703a 	and	r2,r3,r2
+ 8011694:	1001703a 	wrctl	status,r2
+  return context;
+ 8011698:	e0bffe17 	ldw	r2,-8(fp)
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+ 801169c:	e0bfff15 	stw	r2,-4(fp)
+    if (OSIntNesting == 0) {                           /* Schedule only if all ISRs done and ...       */
+ 80116a0:	d0a05703 	ldbu	r2,-32420(gp)
+ 80116a4:	10803fcc 	andi	r2,r2,255
+ 80116a8:	1000181e 	bne	r2,zero,801170c <OS_Sched+0xa0>
+        if (OSLockNesting == 0) {                      /* ... scheduler is not locked                  */
+ 80116ac:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80116b0:	10803fcc 	andi	r2,r2,255
+ 80116b4:	1000151e 	bne	r2,zero,801170c <OS_Sched+0xa0>
+            OS_SchedNew();
+ 80116b8:	80117340 	call	8011734 <OS_SchedNew>
+            if (OSPrioHighRdy != OSPrioCur) {          /* No Ctx Sw if current task is highest rdy     */
+ 80116bc:	d0e04d03 	ldbu	r3,-32460(gp)
+ 80116c0:	d0a04d43 	ldbu	r2,-32459(gp)
+ 80116c4:	18c03fcc 	andi	r3,r3,255
+ 80116c8:	10803fcc 	andi	r2,r2,255
+ 80116cc:	18800f26 	beq	r3,r2,801170c <OS_Sched+0xa0>
+                OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy];
+ 80116d0:	d0a04d03 	ldbu	r2,-32460(gp)
+ 80116d4:	10803fcc 	andi	r2,r2,255
+ 80116d8:	100690ba 	slli	r3,r2,2
+ 80116dc:	008201b4 	movhi	r2,2054
+ 80116e0:	1885883a 	add	r2,r3,r2
+ 80116e4:	10b55d17 	ldw	r2,-10892(r2)
+ 80116e8:	d0a05315 	stw	r2,-32436(gp)
+#if OS_TASK_PROFILE_EN > 0
+                OSTCBHighRdy->OSTCBCtxSwCtr++;         /* Inc. # of context switches to this task      */
+ 80116ec:	d0a05317 	ldw	r2,-32436(gp)
+ 80116f0:	10c00e17 	ldw	r3,56(r2)
+ 80116f4:	18c00044 	addi	r3,r3,1
+ 80116f8:	10c00e15 	stw	r3,56(r2)
+#endif
+                OSCtxSwCtr++;                          /* Increment context switch counter             */
+ 80116fc:	d0a04f17 	ldw	r2,-32452(gp)
+ 8011700:	10800044 	addi	r2,r2,1
+ 8011704:	d0a04f15 	stw	r2,-32452(gp)
+                OS_TASK_SW();                          /* Perform a context switch                     */
+ 8011708:	80383880 	call	8038388 <OSCtxSw>
+ 801170c:	e0bfff17 	ldw	r2,-4(fp)
+ 8011710:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8011714:	e0bffd17 	ldw	r2,-12(fp)
+ 8011718:	1001703a 	wrctl	status,r2
+            }
+        }
+    }
+    OS_EXIT_CRITICAL();
+}
+ 801171c:	0001883a 	nop
+ 8011720:	e037883a 	mov	sp,fp
+ 8011724:	dfc00117 	ldw	ra,4(sp)
+ 8011728:	df000017 	ldw	fp,0(sp)
+ 801172c:	dec00204 	addi	sp,sp,8
+ 8011730:	f800283a 	ret
+
+08011734 <OS_SchedNew>:
+*              2) Interrupts are assumed to be disabled when this function is called.
+*********************************************************************************************************
+*/
+
+static  void  OS_SchedNew (void)
+{
+ 8011734:	defffe04 	addi	sp,sp,-8
+ 8011738:	df000115 	stw	fp,4(sp)
+ 801173c:	df000104 	addi	fp,sp,4
+#if OS_LOWEST_PRIO <= 63                         /* See if we support up to 64 tasks                   */
+    INT8U   y;
+
+
+    y             = OSUnMapTbl[OSRdyGrp];
+ 8011740:	d0a05503 	ldbu	r2,-32428(gp)
+ 8011744:	10c03fcc 	andi	r3,r2,255
+ 8011748:	00820134 	movhi	r2,2052
+ 801174c:	1885883a 	add	r2,r3,r2
+ 8011750:	109dcd03 	ldbu	r2,30516(r2)
+ 8011754:	e0bfffc5 	stb	r2,-1(fp)
+    OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]);
+ 8011758:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801175c:	100490fa 	slli	r2,r2,3
+ 8011760:	1009883a 	mov	r4,r2
+ 8011764:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8011768:	d0a05544 	addi	r2,gp,-32427
+ 801176c:	1885883a 	add	r2,r3,r2
+ 8011770:	10800003 	ldbu	r2,0(r2)
+ 8011774:	10c03fcc 	andi	r3,r2,255
+ 8011778:	00820134 	movhi	r2,2052
+ 801177c:	1885883a 	add	r2,r3,r2
+ 8011780:	109dcd03 	ldbu	r2,30516(r2)
+ 8011784:	2085883a 	add	r2,r4,r2
+ 8011788:	d0a04d05 	stb	r2,-32460(gp)
+        OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]);
+    } else {
+        OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8);
+    }
+#endif
+}
+ 801178c:	0001883a 	nop
+ 8011790:	e037883a 	mov	sp,fp
+ 8011794:	df000017 	ldw	fp,0(sp)
+ 8011798:	dec00104 	addi	sp,sp,4
+ 801179c:	f800283a 	ret
+
+080117a0 <OS_StrCopy>:
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1)
+INT8U  OS_StrCopy (INT8U *pdest, INT8U *psrc)
+{
+ 80117a0:	defffc04 	addi	sp,sp,-16
+ 80117a4:	df000315 	stw	fp,12(sp)
+ 80117a8:	df000304 	addi	fp,sp,12
+ 80117ac:	e13ffe15 	stw	r4,-8(fp)
+ 80117b0:	e17ffd15 	stw	r5,-12(fp)
+    INT8U  len;
+
+
+    len = 0;
+ 80117b4:	e03fffc5 	stb	zero,-1(fp)
+    while (*psrc != OS_ASCII_NUL) {
+ 80117b8:	00000b06 	br	80117e8 <OS_StrCopy+0x48>
+        *pdest++ = *psrc++;
+ 80117bc:	e0fffd17 	ldw	r3,-12(fp)
+ 80117c0:	18800044 	addi	r2,r3,1
+ 80117c4:	e0bffd15 	stw	r2,-12(fp)
+ 80117c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80117cc:	11000044 	addi	r4,r2,1
+ 80117d0:	e13ffe15 	stw	r4,-8(fp)
+ 80117d4:	18c00003 	ldbu	r3,0(r3)
+ 80117d8:	10c00005 	stb	r3,0(r2)
+        len++;
+ 80117dc:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80117e0:	10800044 	addi	r2,r2,1
+ 80117e4:	e0bfffc5 	stb	r2,-1(fp)
+    while (*psrc != OS_ASCII_NUL) {
+ 80117e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80117ec:	10800003 	ldbu	r2,0(r2)
+ 80117f0:	10803fcc 	andi	r2,r2,255
+ 80117f4:	103ff11e 	bne	r2,zero,80117bc <OS_StrCopy+0x1c>
+    }
+    *pdest = OS_ASCII_NUL;
+ 80117f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80117fc:	10000005 	stb	zero,0(r2)
+    return (len);
+ 8011800:	e0bfffc3 	ldbu	r2,-1(fp)
+}
+ 8011804:	e037883a 	mov	sp,fp
+ 8011808:	df000017 	ldw	fp,0(sp)
+ 801180c:	dec00104 	addi	sp,sp,4
+ 8011810:	f800283a 	ret
+
+08011814 <OS_StrLen>:
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1)
+INT8U  OS_StrLen (INT8U *psrc)
+{
+ 8011814:	defffd04 	addi	sp,sp,-12
+ 8011818:	df000215 	stw	fp,8(sp)
+ 801181c:	df000204 	addi	fp,sp,8
+ 8011820:	e13ffe15 	stw	r4,-8(fp)
+    INT8U  len;
+
+
+    len = 0;
+ 8011824:	e03fffc5 	stb	zero,-1(fp)
+    while (*psrc != OS_ASCII_NUL) {
+ 8011828:	00000606 	br	8011844 <OS_StrLen+0x30>
+        psrc++;
+ 801182c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011830:	10800044 	addi	r2,r2,1
+ 8011834:	e0bffe15 	stw	r2,-8(fp)
+        len++;
+ 8011838:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801183c:	10800044 	addi	r2,r2,1
+ 8011840:	e0bfffc5 	stb	r2,-1(fp)
+    while (*psrc != OS_ASCII_NUL) {
+ 8011844:	e0bffe17 	ldw	r2,-8(fp)
+ 8011848:	10800003 	ldbu	r2,0(r2)
+ 801184c:	10803fcc 	andi	r2,r2,255
+ 8011850:	103ff61e 	bne	r2,zero,801182c <OS_StrLen+0x18>
+    }
+    return (len);
+ 8011854:	e0bfffc3 	ldbu	r2,-1(fp)
+}
+ 8011858:	e037883a 	mov	sp,fp
+ 801185c:	df000017 	ldw	fp,0(sp)
+ 8011860:	dec00104 	addi	sp,sp,4
+ 8011864:	f800283a 	ret
+
+08011868 <OS_TaskIdle>:
+*                 power.
+*********************************************************************************************************
+*/
+
+void  OS_TaskIdle (void *p_arg)
+{
+ 8011868:	defffa04 	addi	sp,sp,-24
+ 801186c:	dfc00515 	stw	ra,20(sp)
+ 8011870:	df000415 	stw	fp,16(sp)
+ 8011874:	df000404 	addi	fp,sp,16
+ 8011878:	e13ffc15 	stw	r4,-16(fp)
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 801187c:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8011880:	0005303a 	rdctl	r2,status
+ 8011884:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011888:	e0fffd17 	ldw	r3,-12(fp)
+ 801188c:	00bfff84 	movi	r2,-2
+ 8011890:	1884703a 	and	r2,r3,r2
+ 8011894:	1001703a 	wrctl	status,r2
+  return context;
+ 8011898:	e0bffd17 	ldw	r2,-12(fp)
+
+
+
+    (void)p_arg;                                 /* Prevent compiler warning for not using 'p_arg'     */
+    for (;;) {
+        OS_ENTER_CRITICAL();
+ 801189c:	e0bfff15 	stw	r2,-4(fp)
+        OSIdleCtr++;
+ 80118a0:	d0a04c17 	ldw	r2,-32464(gp)
+ 80118a4:	10800044 	addi	r2,r2,1
+ 80118a8:	d0a04c15 	stw	r2,-32464(gp)
+ 80118ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80118b0:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80118b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80118b8:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OSTaskIdleHook();                        /* Call user definable HOOK                           */
+ 80118bc:	80386980 	call	8038698 <OSTaskIdleHook>
+        OS_ENTER_CRITICAL();
+ 80118c0:	003fef06 	br	8011880 <OS_TaskIdle+0x18>
+
+080118c4 <OS_TCBInit>:
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+INT8U  OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt)
+{
+ 80118c4:	defff204 	addi	sp,sp,-56
+ 80118c8:	dfc00d15 	stw	ra,52(sp)
+ 80118cc:	df000c15 	stw	fp,48(sp)
+ 80118d0:	df000c04 	addi	fp,sp,48
+ 80118d4:	2007883a 	mov	r3,r4
+ 80118d8:	e17ff715 	stw	r5,-36(fp)
+ 80118dc:	e1bff615 	stw	r6,-40(fp)
+ 80118e0:	3809883a 	mov	r4,r7
+ 80118e4:	e0800417 	ldw	r2,16(fp)
+ 80118e8:	e0fff805 	stb	r3,-32(fp)
+ 80118ec:	2007883a 	mov	r3,r4
+ 80118f0:	e0fff50d 	sth	r3,-44(fp)
+ 80118f4:	e0bff40d 	sth	r2,-48(fp)
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 80118f8:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80118fc:	0005303a 	rdctl	r2,status
+ 8011900:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011904:	e0fffd17 	ldw	r3,-12(fp)
+ 8011908:	00bfff84 	movi	r2,-2
+ 801190c:	1884703a 	and	r2,r3,r2
+ 8011910:	1001703a 	wrctl	status,r2
+  return context;
+ 8011914:	e0bffd17 	ldw	r2,-12(fp)
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+ 8011918:	e0bfff15 	stw	r2,-4(fp)
+    ptcb = OSTCBFreeList;                                  /* Get a free TCB from the free TCB list    */
+ 801191c:	d0a05017 	ldw	r2,-32448(gp)
+ 8011920:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb != (OS_TCB *)0) {
+ 8011924:	e0bffe17 	ldw	r2,-8(fp)
+ 8011928:	10009126 	beq	r2,zero,8011b70 <OS_TCBInit+0x2ac>
+        OSTCBFreeList            = ptcb->OSTCBNext;        /* Update pointer to free TCB list          */
+ 801192c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011930:	10800517 	ldw	r2,20(r2)
+ 8011934:	d0a05015 	stw	r2,-32448(gp)
+ 8011938:	e0bfff17 	ldw	r2,-4(fp)
+ 801193c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8011940:	e0bffb17 	ldw	r2,-20(fp)
+ 8011944:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        ptcb->OSTCBStkPtr        = ptos;                   /* Load Stack pointer in TCB                */
+ 8011948:	e0bffe17 	ldw	r2,-8(fp)
+ 801194c:	e0fff717 	ldw	r3,-36(fp)
+ 8011950:	10c00015 	stw	r3,0(r2)
+        ptcb->OSTCBPrio          = prio;                   /* Load task priority into TCB              */
+ 8011954:	e0bffe17 	ldw	r2,-8(fp)
+ 8011958:	e0fff803 	ldbu	r3,-32(fp)
+ 801195c:	10c00c85 	stb	r3,50(r2)
+        ptcb->OSTCBStat          = OS_STAT_RDY;            /* Task is ready to run                     */
+ 8011960:	e0bffe17 	ldw	r2,-8(fp)
+ 8011964:	10000c05 	stb	zero,48(r2)
+        ptcb->OSTCBStatPend      = OS_STAT_PEND_OK;        /* Clear pend status                        */
+ 8011968:	e0bffe17 	ldw	r2,-8(fp)
+ 801196c:	10000c45 	stb	zero,49(r2)
+        ptcb->OSTCBDly           = 0;                      /* Task is not delayed                      */
+ 8011970:	e0bffe17 	ldw	r2,-8(fp)
+ 8011974:	10000b8d 	sth	zero,46(r2)
+
+#if OS_TASK_CREATE_EXT_EN > 0
+        ptcb->OSTCBExtPtr        = pext;                   /* Store pointer to TCB extension           */
+ 8011978:	e0bffe17 	ldw	r2,-8(fp)
+ 801197c:	e0c00317 	ldw	r3,12(fp)
+ 8011980:	10c00115 	stw	r3,4(r2)
+        ptcb->OSTCBStkSize       = stk_size;               /* Store stack size                         */
+ 8011984:	e0bffe17 	ldw	r2,-8(fp)
+ 8011988:	e0c00217 	ldw	r3,8(fp)
+ 801198c:	10c00315 	stw	r3,12(r2)
+        ptcb->OSTCBStkBottom     = pbos;                   /* Store pointer to bottom of stack         */
+ 8011990:	e0bffe17 	ldw	r2,-8(fp)
+ 8011994:	e0fff617 	ldw	r3,-40(fp)
+ 8011998:	10c00215 	stw	r3,8(r2)
+        ptcb->OSTCBOpt           = opt;                    /* Store task options                       */
+ 801199c:	e0bffe17 	ldw	r2,-8(fp)
+ 80119a0:	e0fff40b 	ldhu	r3,-48(fp)
+ 80119a4:	10c0040d 	sth	r3,16(r2)
+        ptcb->OSTCBId            = id;                     /* Store task ID                            */
+ 80119a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80119ac:	e0fff50b 	ldhu	r3,-44(fp)
+ 80119b0:	10c0048d 	sth	r3,18(r2)
+        opt                      = opt;
+        id                       = id;
+#endif
+
+#if OS_TASK_DEL_EN > 0
+        ptcb->OSTCBDelReq        = OS_ERR_NONE;
+ 80119b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80119b8:	10000dc5 	stb	zero,55(r2)
+#endif
+
+#if OS_LOWEST_PRIO <= 63
+        ptcb->OSTCBY             = (INT8U)(prio >> 3);          /* Pre-compute X, Y, BitX and BitY     */
+ 80119bc:	e0bff803 	ldbu	r2,-32(fp)
+ 80119c0:	1004d0fa 	srli	r2,r2,3
+ 80119c4:	1007883a 	mov	r3,r2
+ 80119c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80119cc:	10c00d05 	stb	r3,52(r2)
+        ptcb->OSTCBX             = (INT8U)(prio & 0x07);
+ 80119d0:	e0bff803 	ldbu	r2,-32(fp)
+ 80119d4:	108001cc 	andi	r2,r2,7
+ 80119d8:	1007883a 	mov	r3,r2
+ 80119dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80119e0:	10c00cc5 	stb	r3,51(r2)
+        ptcb->OSTCBBitY          = (INT8U)(1 << ptcb->OSTCBY);
+ 80119e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80119e8:	10800d03 	ldbu	r2,52(r2)
+ 80119ec:	10803fcc 	andi	r2,r2,255
+ 80119f0:	00c00044 	movi	r3,1
+ 80119f4:	1884983a 	sll	r2,r3,r2
+ 80119f8:	1007883a 	mov	r3,r2
+ 80119fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a00:	10c00d85 	stb	r3,54(r2)
+        ptcb->OSTCBBitX          = (INT8U)(1 << ptcb->OSTCBX);
+ 8011a04:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a08:	10800cc3 	ldbu	r2,51(r2)
+ 8011a0c:	10803fcc 	andi	r2,r2,255
+ 8011a10:	00c00044 	movi	r3,1
+ 8011a14:	1884983a 	sll	r2,r3,r2
+ 8011a18:	1007883a 	mov	r3,r2
+ 8011a1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a20:	10c00d45 	stb	r3,53(r2)
+        ptcb->OSTCBBitY          = (INT16U)(1 << ptcb->OSTCBY);
+        ptcb->OSTCBBitX          = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+
+#if (OS_EVENT_EN)
+        ptcb->OSTCBEventPtr      = (OS_EVENT  *)0;         /* Task is not pending on an  event         */
+ 8011a24:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a28:	10000715 	stw	zero,28(r2)
+#if (OS_EVENT_MULTI_EN > 0)
+        ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0;         /* Task is not pending on any events        */
+ 8011a2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a30:	10000815 	stw	zero,32(r2)
+#endif
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0)
+        ptcb->OSTCBFlagNode  = (OS_FLAG_NODE *)0;          /* Task is not pending on an event flag     */
+ 8011a34:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a38:	10000a15 	stw	zero,40(r2)
+#endif
+
+#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0))
+        ptcb->OSTCBMsg       = (void *)0;                  /* No message received                      */
+ 8011a3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a40:	10000915 	stw	zero,36(r2)
+#endif
+
+#if OS_TASK_PROFILE_EN > 0
+        ptcb->OSTCBCtxSwCtr    = 0L;                       /* Initialize profiling variables           */
+ 8011a44:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a48:	10000e15 	stw	zero,56(r2)
+        ptcb->OSTCBCyclesStart = 0L;
+ 8011a4c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a50:	10001015 	stw	zero,64(r2)
+        ptcb->OSTCBCyclesTot   = 0L;
+ 8011a54:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a58:	10000f15 	stw	zero,60(r2)
+        ptcb->OSTCBStkBase     = (OS_STK *)0;
+ 8011a5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a60:	10001115 	stw	zero,68(r2)
+        ptcb->OSTCBStkUsed     = 0L;
+ 8011a64:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a68:	10001215 	stw	zero,72(r2)
+#endif
+
+#if OS_TASK_NAME_SIZE > 1
+        ptcb->OSTCBTaskName[0] = '?';                      /* Unknown name at task creation            */
+ 8011a6c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a70:	00c00fc4 	movi	r3,63
+ 8011a74:	10c01305 	stb	r3,76(r2)
+        ptcb->OSTCBTaskName[1] = OS_ASCII_NUL;
+ 8011a78:	e0bffe17 	ldw	r2,-8(fp)
+ 8011a7c:	10001345 	stb	zero,77(r2)
+#endif
+
+        OSTCBInitHook(ptcb);
+ 8011a80:	e13ffe17 	ldw	r4,-8(fp)
+ 8011a84:	80386b80 	call	80386b8 <OSTCBInitHook>
+
+        OSTaskCreateHook(ptcb);                            /* Call user defined hook                   */
+ 8011a88:	e13ffe17 	ldw	r4,-8(fp)
+ 8011a8c:	80385a40 	call	80385a4 <OSTaskCreateHook>
+  NIOS2_READ_STATUS (context);
+ 8011a90:	0005303a 	rdctl	r2,status
+ 8011a94:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011a98:	e0fffc17 	ldw	r3,-16(fp)
+ 8011a9c:	00bfff84 	movi	r2,-2
+ 8011aa0:	1884703a 	and	r2,r3,r2
+ 8011aa4:	1001703a 	wrctl	status,r2
+  return context;
+ 8011aa8:	e0bffc17 	ldw	r2,-16(fp)
+
+        OS_ENTER_CRITICAL();
+ 8011aac:	e0bfff15 	stw	r2,-4(fp)
+        OSTCBPrioTbl[prio] = ptcb;
+ 8011ab0:	e0bff803 	ldbu	r2,-32(fp)
+ 8011ab4:	100890ba 	slli	r4,r2,2
+ 8011ab8:	e0fffe17 	ldw	r3,-8(fp)
+ 8011abc:	008201b4 	movhi	r2,2054
+ 8011ac0:	2085883a 	add	r2,r4,r2
+ 8011ac4:	10f55d15 	stw	r3,-10892(r2)
+        ptcb->OSTCBNext    = OSTCBList;                    /* Link into TCB chain                      */
+ 8011ac8:	d0e04e17 	ldw	r3,-32456(gp)
+ 8011acc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011ad0:	10c00515 	stw	r3,20(r2)
+        ptcb->OSTCBPrev    = (OS_TCB *)0;
+ 8011ad4:	e0bffe17 	ldw	r2,-8(fp)
+ 8011ad8:	10000615 	stw	zero,24(r2)
+        if (OSTCBList != (OS_TCB *)0) {
+ 8011adc:	d0a04e17 	ldw	r2,-32456(gp)
+ 8011ae0:	10000326 	beq	r2,zero,8011af0 <OS_TCBInit+0x22c>
+            OSTCBList->OSTCBPrev = ptcb;
+ 8011ae4:	d0a04e17 	ldw	r2,-32456(gp)
+ 8011ae8:	e0fffe17 	ldw	r3,-8(fp)
+ 8011aec:	10c00615 	stw	r3,24(r2)
+        }
+        OSTCBList               = ptcb;
+ 8011af0:	e0bffe17 	ldw	r2,-8(fp)
+ 8011af4:	d0a04e15 	stw	r2,-32456(gp)
+        OSRdyGrp               |= ptcb->OSTCBBitY;         /* Make task ready to run                   */
+ 8011af8:	e0bffe17 	ldw	r2,-8(fp)
+ 8011afc:	10c00d83 	ldbu	r3,54(r2)
+ 8011b00:	d0a05503 	ldbu	r2,-32428(gp)
+ 8011b04:	1884b03a 	or	r2,r3,r2
+ 8011b08:	d0a05505 	stb	r2,-32428(gp)
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8011b0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011b10:	10800d03 	ldbu	r2,52(r2)
+ 8011b14:	10c03fcc 	andi	r3,r2,255
+ 8011b18:	d0a05544 	addi	r2,gp,-32427
+ 8011b1c:	1885883a 	add	r2,r3,r2
+ 8011b20:	11000003 	ldbu	r4,0(r2)
+ 8011b24:	e0bffe17 	ldw	r2,-8(fp)
+ 8011b28:	10800d43 	ldbu	r2,53(r2)
+ 8011b2c:	e0fffe17 	ldw	r3,-8(fp)
+ 8011b30:	18c00d03 	ldbu	r3,52(r3)
+ 8011b34:	18c03fcc 	andi	r3,r3,255
+ 8011b38:	2084b03a 	or	r2,r4,r2
+ 8011b3c:	1009883a 	mov	r4,r2
+ 8011b40:	d0a05544 	addi	r2,gp,-32427
+ 8011b44:	1885883a 	add	r2,r3,r2
+ 8011b48:	11000005 	stb	r4,0(r2)
+        OSTaskCtr++;                                       /* Increment the #tasks counter             */
+ 8011b4c:	d0a05103 	ldbu	r2,-32444(gp)
+ 8011b50:	10800044 	addi	r2,r2,1
+ 8011b54:	d0a05105 	stb	r2,-32444(gp)
+ 8011b58:	e0bfff17 	ldw	r2,-4(fp)
+ 8011b5c:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8011b60:	e0bffa17 	ldw	r2,-24(fp)
+ 8011b64:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NONE);
+ 8011b68:	0005883a 	mov	r2,zero
+ 8011b6c:	00000506 	br	8011b84 <OS_TCBInit+0x2c0>
+ 8011b70:	e0bfff17 	ldw	r2,-4(fp)
+ 8011b74:	e0bff915 	stw	r2,-28(fp)
+ 8011b78:	e0bff917 	ldw	r2,-28(fp)
+ 8011b7c:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_TASK_NO_MORE_TCB);
+ 8011b80:	00801084 	movi	r2,66
+}
+ 8011b84:	e037883a 	mov	sp,fp
+ 8011b88:	dfc00117 	ldw	ra,4(sp)
+ 8011b8c:	df000017 	ldw	fp,0(sp)
+ 8011b90:	dec00204 	addi	sp,sp,8
+ 8011b94:	f800283a 	ret
+
+08011b98 <OSFlagAccept>:
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_ACCEPT_EN > 0
+OS_FLAGS  OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr)
+{
+ 8011b98:	defff204 	addi	sp,sp,-56
+ 8011b9c:	df000d15 	stw	fp,52(sp)
+ 8011ba0:	df000d04 	addi	fp,sp,52
+ 8011ba4:	e13ff615 	stw	r4,-40(fp)
+ 8011ba8:	2805883a 	mov	r2,r5
+ 8011bac:	3007883a 	mov	r3,r6
+ 8011bb0:	e1fff315 	stw	r7,-52(fp)
+ 8011bb4:	e0bff50d 	sth	r2,-44(fp)
+ 8011bb8:	1805883a 	mov	r2,r3
+ 8011bbc:	e0bff405 	stb	r2,-48(fp)
+    OS_FLAGS      flags_rdy;
+    INT8U         result;
+    BOOLEAN       consume;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+ 8011bc0:	e03ffe15 	stw	zero,-8(fp)
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event block type                */
+ 8011bc4:	e0bff617 	ldw	r2,-40(fp)
+ 8011bc8:	10800003 	ldbu	r2,0(r2)
+ 8011bcc:	10803fcc 	andi	r2,r2,255
+ 8011bd0:	10800160 	cmpeqi	r2,r2,5
+ 8011bd4:	1000051e 	bne	r2,zero,8011bec <OSFlagAccept+0x54>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8011bd8:	e0bff317 	ldw	r2,-52(fp)
+ 8011bdc:	00c00044 	movi	r3,1
+ 8011be0:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 8011be4:	0005883a 	mov	r2,zero
+ 8011be8:	00009f06 	br	8011e68 <OSFlagAccept+0x2d0>
+    }
+    result = (INT8U)(wait_type & OS_FLAG_CONSUME);
+ 8011bec:	e0fff403 	ldbu	r3,-48(fp)
+ 8011bf0:	00bfe004 	movi	r2,-128
+ 8011bf4:	1884703a 	and	r2,r3,r2
+ 8011bf8:	e0bffdc5 	stb	r2,-9(fp)
+    if (result != (INT8U)0) {                              /* See if we need to consume the flags      */
+ 8011bfc:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8011c00:	10000626 	beq	r2,zero,8011c1c <OSFlagAccept+0x84>
+        wait_type &= ~OS_FLAG_CONSUME;
+ 8011c04:	e0bff403 	ldbu	r2,-48(fp)
+ 8011c08:	10801fcc 	andi	r2,r2,127
+ 8011c0c:	e0bff405 	stb	r2,-48(fp)
+        consume    = OS_TRUE;
+ 8011c10:	00800044 	movi	r2,1
+ 8011c14:	e0bfff45 	stb	r2,-3(fp)
+ 8011c18:	00000106 	br	8011c20 <OSFlagAccept+0x88>
+    } else {
+        consume    = OS_FALSE;
+ 8011c1c:	e03fff45 	stb	zero,-3(fp)
+    }
+/*$PAGE*/
+    *perr = OS_ERR_NONE;                                   /* Assume NO error until proven otherwise.  */
+ 8011c20:	e0bff317 	ldw	r2,-52(fp)
+ 8011c24:	10000005 	stb	zero,0(r2)
+  NIOS2_READ_STATUS (context);
+ 8011c28:	0005303a 	rdctl	r2,status
+ 8011c2c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011c30:	e0fffc17 	ldw	r3,-16(fp)
+ 8011c34:	00bfff84 	movi	r2,-2
+ 8011c38:	1884703a 	and	r2,r3,r2
+ 8011c3c:	1001703a 	wrctl	status,r2
+  return context;
+ 8011c40:	e0bffc17 	ldw	r2,-16(fp)
+    OS_ENTER_CRITICAL();
+ 8011c44:	e0bffe15 	stw	r2,-8(fp)
+    switch (wait_type) {
+ 8011c48:	e0bff403 	ldbu	r2,-48(fp)
+ 8011c4c:	10c00060 	cmpeqi	r3,r2,1
+ 8011c50:	18005f1e 	bne	r3,zero,8011dd0 <OSFlagAccept+0x238>
+ 8011c54:	10c00088 	cmpgei	r3,r2,2
+ 8011c58:	1800021e 	bne	r3,zero,8011c64 <OSFlagAccept+0xcc>
+ 8011c5c:	10003f26 	beq	r2,zero,8011d5c <OSFlagAccept+0x1c4>
+ 8011c60:	00007706 	br	8011e40 <OSFlagAccept+0x2a8>
+ 8011c64:	10c000a0 	cmpeqi	r3,r2,2
+ 8011c68:	1800031e 	bne	r3,zero,8011c78 <OSFlagAccept+0xe0>
+ 8011c6c:	108000e0 	cmpeqi	r2,r2,3
+ 8011c70:	10001e1e 	bne	r2,zero,8011cec <OSFlagAccept+0x154>
+ 8011c74:	00007206 	br	8011e40 <OSFlagAccept+0x2a8>
+        case OS_FLAG_WAIT_SET_ALL:                         /* See if all required flags are set        */
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);     /* Extract only the bits we want   */
+ 8011c78:	e0bff617 	ldw	r2,-40(fp)
+ 8011c7c:	1080020b 	ldhu	r2,8(r2)
+ 8011c80:	e0fff50b 	ldhu	r3,-44(fp)
+ 8011c84:	1884703a 	and	r2,r3,r2
+ 8011c88:	e0bfff8d 	sth	r2,-2(fp)
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+ 8011c8c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8011c90:	e0bff50b 	ldhu	r2,-44(fp)
+ 8011c94:	18800d1e 	bne	r3,r2,8011ccc <OSFlagAccept+0x134>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8011c98:	e0bfff43 	ldbu	r2,-3(fp)
+ 8011c9c:	10800058 	cmpnei	r2,r2,1
+ 8011ca0:	10000d1e 	bne	r2,zero,8011cd8 <OSFlagAccept+0x140>
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we wanted      */
+ 8011ca4:	e0bff617 	ldw	r2,-40(fp)
+ 8011ca8:	1080020b 	ldhu	r2,8(r2)
+ 8011cac:	1007883a 	mov	r3,r2
+ 8011cb0:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011cb4:	0084303a 	nor	r2,zero,r2
+ 8011cb8:	1884703a 	and	r2,r3,r2
+ 8011cbc:	1007883a 	mov	r3,r2
+ 8011cc0:	e0bff617 	ldw	r2,-40(fp)
+ 8011cc4:	10c0020d 	sth	r3,8(r2)
+ 8011cc8:	00000306 	br	8011cd8 <OSFlagAccept+0x140>
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+ 8011ccc:	e0bff317 	ldw	r2,-52(fp)
+ 8011cd0:	00c01c04 	movi	r3,112
+ 8011cd4:	10c00005 	stb	r3,0(r2)
+ 8011cd8:	e0bffe17 	ldw	r2,-8(fp)
+ 8011cdc:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8011ce0:	e0bffb17 	ldw	r2,-20(fp)
+ 8011ce4:	1001703a 	wrctl	status,r2
+             }
+             OS_EXIT_CRITICAL();
+             break;
+ 8011ce8:	00005e06 	br	8011e64 <OSFlagAccept+0x2cc>
+
+        case OS_FLAG_WAIT_SET_ANY:
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);     /* Extract only the bits we want   */
+ 8011cec:	e0bff617 	ldw	r2,-40(fp)
+ 8011cf0:	1080020b 	ldhu	r2,8(r2)
+ 8011cf4:	e0fff50b 	ldhu	r3,-44(fp)
+ 8011cf8:	1884703a 	and	r2,r3,r2
+ 8011cfc:	e0bfff8d 	sth	r2,-2(fp)
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag set                      */
+ 8011d00:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011d04:	10000d26 	beq	r2,zero,8011d3c <OSFlagAccept+0x1a4>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8011d08:	e0bfff43 	ldbu	r2,-3(fp)
+ 8011d0c:	10800058 	cmpnei	r2,r2,1
+ 8011d10:	10000d1e 	bne	r2,zero,8011d48 <OSFlagAccept+0x1b0>
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we got         */
+ 8011d14:	e0bff617 	ldw	r2,-40(fp)
+ 8011d18:	1080020b 	ldhu	r2,8(r2)
+ 8011d1c:	1007883a 	mov	r3,r2
+ 8011d20:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011d24:	0084303a 	nor	r2,zero,r2
+ 8011d28:	1884703a 	and	r2,r3,r2
+ 8011d2c:	1007883a 	mov	r3,r2
+ 8011d30:	e0bff617 	ldw	r2,-40(fp)
+ 8011d34:	10c0020d 	sth	r3,8(r2)
+ 8011d38:	00000306 	br	8011d48 <OSFlagAccept+0x1b0>
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+ 8011d3c:	e0bff317 	ldw	r2,-52(fp)
+ 8011d40:	00c01c04 	movi	r3,112
+ 8011d44:	10c00005 	stb	r3,0(r2)
+ 8011d48:	e0bffe17 	ldw	r2,-8(fp)
+ 8011d4c:	e0bffa15 	stw	r2,-24(fp)
+ 8011d50:	e0bffa17 	ldw	r2,-24(fp)
+ 8011d54:	1001703a 	wrctl	status,r2
+             }
+             OS_EXIT_CRITICAL();
+             break;
+ 8011d58:	00004206 	br	8011e64 <OSFlagAccept+0x2cc>
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+        case OS_FLAG_WAIT_CLR_ALL:                         /* See if all required flags are cleared    */
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags);  /* Extract only the bits we want     */
+ 8011d5c:	e0bff617 	ldw	r2,-40(fp)
+ 8011d60:	1080020b 	ldhu	r2,8(r2)
+ 8011d64:	0084303a 	nor	r2,zero,r2
+ 8011d68:	1007883a 	mov	r3,r2
+ 8011d6c:	e0bff50b 	ldhu	r2,-44(fp)
+ 8011d70:	1884703a 	and	r2,r3,r2
+ 8011d74:	e0bfff8d 	sth	r2,-2(fp)
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+ 8011d78:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8011d7c:	e0bff50b 	ldhu	r2,-44(fp)
+ 8011d80:	18800b1e 	bne	r3,r2,8011db0 <OSFlagAccept+0x218>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8011d84:	e0bfff43 	ldbu	r2,-3(fp)
+ 8011d88:	10800058 	cmpnei	r2,r2,1
+ 8011d8c:	10000b1e 	bne	r2,zero,8011dbc <OSFlagAccept+0x224>
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we wanted        */
+ 8011d90:	e0bff617 	ldw	r2,-40(fp)
+ 8011d94:	1080020b 	ldhu	r2,8(r2)
+ 8011d98:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8011d9c:	1884b03a 	or	r2,r3,r2
+ 8011da0:	1007883a 	mov	r3,r2
+ 8011da4:	e0bff617 	ldw	r2,-40(fp)
+ 8011da8:	10c0020d 	sth	r3,8(r2)
+ 8011dac:	00000306 	br	8011dbc <OSFlagAccept+0x224>
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+ 8011db0:	e0bff317 	ldw	r2,-52(fp)
+ 8011db4:	00c01c04 	movi	r3,112
+ 8011db8:	10c00005 	stb	r3,0(r2)
+ 8011dbc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011dc0:	e0bff915 	stw	r2,-28(fp)
+ 8011dc4:	e0bff917 	ldw	r2,-28(fp)
+ 8011dc8:	1001703a 	wrctl	status,r2
+             }
+             OS_EXIT_CRITICAL();
+             break;
+ 8011dcc:	00002506 	br	8011e64 <OSFlagAccept+0x2cc>
+
+        case OS_FLAG_WAIT_CLR_ANY:
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want      */
+ 8011dd0:	e0bff617 	ldw	r2,-40(fp)
+ 8011dd4:	1080020b 	ldhu	r2,8(r2)
+ 8011dd8:	0084303a 	nor	r2,zero,r2
+ 8011ddc:	1007883a 	mov	r3,r2
+ 8011de0:	e0bff50b 	ldhu	r2,-44(fp)
+ 8011de4:	1884703a 	and	r2,r3,r2
+ 8011de8:	e0bfff8d 	sth	r2,-2(fp)
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag cleared                  */
+ 8011dec:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8011df0:	10000b26 	beq	r2,zero,8011e20 <OSFlagAccept+0x288>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8011df4:	e0bfff43 	ldbu	r2,-3(fp)
+ 8011df8:	10800058 	cmpnei	r2,r2,1
+ 8011dfc:	10000b1e 	bne	r2,zero,8011e2c <OSFlagAccept+0x294>
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we got           */
+ 8011e00:	e0bff617 	ldw	r2,-40(fp)
+ 8011e04:	1080020b 	ldhu	r2,8(r2)
+ 8011e08:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8011e0c:	1884b03a 	or	r2,r3,r2
+ 8011e10:	1007883a 	mov	r3,r2
+ 8011e14:	e0bff617 	ldw	r2,-40(fp)
+ 8011e18:	10c0020d 	sth	r3,8(r2)
+ 8011e1c:	00000306 	br	8011e2c <OSFlagAccept+0x294>
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+ 8011e20:	e0bff317 	ldw	r2,-52(fp)
+ 8011e24:	00c01c04 	movi	r3,112
+ 8011e28:	10c00005 	stb	r3,0(r2)
+ 8011e2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011e30:	e0bff815 	stw	r2,-32(fp)
+ 8011e34:	e0bff817 	ldw	r2,-32(fp)
+ 8011e38:	1001703a 	wrctl	status,r2
+             }
+             OS_EXIT_CRITICAL();
+             break;
+ 8011e3c:	00000906 	br	8011e64 <OSFlagAccept+0x2cc>
+ 8011e40:	e0bffe17 	ldw	r2,-8(fp)
+ 8011e44:	e0bff715 	stw	r2,-36(fp)
+ 8011e48:	e0bff717 	ldw	r2,-36(fp)
+ 8011e4c:	1001703a 	wrctl	status,r2
+#endif
+
+        default:
+             OS_EXIT_CRITICAL();
+             flags_rdy = (OS_FLAGS)0;
+ 8011e50:	e03fff8d 	sth	zero,-2(fp)
+             *perr     = OS_ERR_FLAG_WAIT_TYPE;
+ 8011e54:	e0bff317 	ldw	r2,-52(fp)
+ 8011e58:	00c01bc4 	movi	r3,111
+ 8011e5c:	10c00005 	stb	r3,0(r2)
+             break;
+ 8011e60:	0001883a 	nop
+    }
+    return (flags_rdy);
+ 8011e64:	e0bfff8b 	ldhu	r2,-2(fp)
+}
+ 8011e68:	e037883a 	mov	sp,fp
+ 8011e6c:	df000017 	ldw	fp,0(sp)
+ 8011e70:	dec00104 	addi	sp,sp,4
+ 8011e74:	f800283a 	ret
+
+08011e78 <OSFlagCreate>:
+* Called from: Task ONLY
+*********************************************************************************************************
+*/
+
+OS_FLAG_GRP  *OSFlagCreate (OS_FLAGS flags, INT8U *perr)
+{
+ 8011e78:	defff804 	addi	sp,sp,-32
+ 8011e7c:	df000715 	stw	fp,28(sp)
+ 8011e80:	df000704 	addi	fp,sp,28
+ 8011e84:	2005883a 	mov	r2,r4
+ 8011e88:	e17ff915 	stw	r5,-28(fp)
+ 8011e8c:	e0bffa0d 	sth	r2,-24(fp)
+    OS_FLAG_GRP *pgrp;
+#if OS_CRITICAL_METHOD == 3                         /* Allocate storage for CPU status register        */
+    OS_CPU_SR    cpu_sr = 0;
+ 8011e90:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                       /* Validate 'perr'                                 */
+        return ((OS_FLAG_GRP *)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                         /* See if called from ISR ...                      */
+ 8011e94:	d0a05703 	ldbu	r2,-32420(gp)
+ 8011e98:	10803fcc 	andi	r2,r2,255
+ 8011e9c:	10000526 	beq	r2,zero,8011eb4 <OSFlagCreate+0x3c>
+        *perr = OS_ERR_CREATE_ISR;                  /* ... can't CREATE from an ISR                    */
+ 8011ea0:	e0bff917 	ldw	r2,-28(fp)
+ 8011ea4:	00c00404 	movi	r3,16
+ 8011ea8:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAG_GRP *)0);
+ 8011eac:	0005883a 	mov	r2,zero
+ 8011eb0:	00002b06 	br	8011f60 <OSFlagCreate+0xe8>
+  NIOS2_READ_STATUS (context);
+ 8011eb4:	0005303a 	rdctl	r2,status
+ 8011eb8:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011ebc:	e0fffd17 	ldw	r3,-12(fp)
+ 8011ec0:	00bfff84 	movi	r2,-2
+ 8011ec4:	1884703a 	and	r2,r3,r2
+ 8011ec8:	1001703a 	wrctl	status,r2
+  return context;
+ 8011ecc:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8011ed0:	e0bfff15 	stw	r2,-4(fp)
+    pgrp = OSFlagFreeList;                          /* Get next free event flag                        */
+ 8011ed4:	d0a05a17 	ldw	r2,-32408(gp)
+ 8011ed8:	e0bffe15 	stw	r2,-8(fp)
+    if (pgrp != (OS_FLAG_GRP *)0) {                 /* See if we have event flag groups available      */
+ 8011edc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011ee0:	10001726 	beq	r2,zero,8011f40 <OSFlagCreate+0xc8>
+                                                    /* Adjust free list                                */
+        OSFlagFreeList       = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList;
+ 8011ee4:	d0a05a17 	ldw	r2,-32408(gp)
+ 8011ee8:	10800117 	ldw	r2,4(r2)
+ 8011eec:	d0a05a15 	stw	r2,-32408(gp)
+        pgrp->OSFlagType     = OS_EVENT_TYPE_FLAG;  /* Set to event flag group type                    */
+ 8011ef0:	e0bffe17 	ldw	r2,-8(fp)
+ 8011ef4:	00c00144 	movi	r3,5
+ 8011ef8:	10c00005 	stb	r3,0(r2)
+        pgrp->OSFlagFlags    = flags;               /* Set to desired initial value                    */
+ 8011efc:	e0bffe17 	ldw	r2,-8(fp)
+ 8011f00:	e0fffa0b 	ldhu	r3,-24(fp)
+ 8011f04:	10c0020d 	sth	r3,8(r2)
+        pgrp->OSFlagWaitList = (void *)0;           /* Clear list of tasks waiting on flags            */
+ 8011f08:	e0bffe17 	ldw	r2,-8(fp)
+ 8011f0c:	10000115 	stw	zero,4(r2)
+#if OS_FLAG_NAME_SIZE > 1
+        pgrp->OSFlagName[0]  = '?';
+ 8011f10:	e0bffe17 	ldw	r2,-8(fp)
+ 8011f14:	00c00fc4 	movi	r3,63
+ 8011f18:	10c00285 	stb	r3,10(r2)
+        pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+ 8011f1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8011f20:	100002c5 	stb	zero,11(r2)
+ 8011f24:	e0bfff17 	ldw	r2,-4(fp)
+ 8011f28:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8011f2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8011f30:	1001703a 	wrctl	status,r2
+#endif
+        OS_EXIT_CRITICAL();
+        *perr                = OS_ERR_NONE;
+ 8011f34:	e0bff917 	ldw	r2,-28(fp)
+ 8011f38:	10000005 	stb	zero,0(r2)
+ 8011f3c:	00000706 	br	8011f5c <OSFlagCreate+0xe4>
+ 8011f40:	e0bfff17 	ldw	r2,-4(fp)
+ 8011f44:	e0bffb15 	stw	r2,-20(fp)
+ 8011f48:	e0bffb17 	ldw	r2,-20(fp)
+ 8011f4c:	1001703a 	wrctl	status,r2
+    } else {
+        OS_EXIT_CRITICAL();
+        *perr                = OS_ERR_FLAG_GRP_DEPLETED;
+ 8011f50:	e0bff917 	ldw	r2,-28(fp)
+ 8011f54:	00c01c84 	movi	r3,114
+ 8011f58:	10c00005 	stb	r3,0(r2)
+    }
+    return (pgrp);                                  /* Return pointer to event flag group              */
+ 8011f5c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8011f60:	e037883a 	mov	sp,fp
+ 8011f64:	df000017 	ldw	fp,0(sp)
+ 8011f68:	dec00104 	addi	sp,sp,4
+ 8011f6c:	f800283a 	ret
+
+08011f70 <OSFlagDel>:
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_DEL_EN > 0
+OS_FLAG_GRP  *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr)
+{
+ 8011f70:	defff204 	addi	sp,sp,-56
+ 8011f74:	dfc00d15 	stw	ra,52(sp)
+ 8011f78:	df000c15 	stw	fp,48(sp)
+ 8011f7c:	df000c04 	addi	fp,sp,48
+ 8011f80:	e13ff615 	stw	r4,-40(fp)
+ 8011f84:	2805883a 	mov	r2,r5
+ 8011f88:	e1bff415 	stw	r6,-48(fp)
+ 8011f8c:	e0bff505 	stb	r2,-44(fp)
+    BOOLEAN       tasks_waiting;
+    OS_FLAG_NODE *pnode;
+    OS_FLAG_GRP  *pgrp_return;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+ 8011f90:	e03ffc15 	stw	zero,-16(fp)
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return (pgrp);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8011f94:	d0a05703 	ldbu	r2,-32420(gp)
+ 8011f98:	10803fcc 	andi	r2,r2,255
+ 8011f9c:	10000526 	beq	r2,zero,8011fb4 <OSFlagDel+0x44>
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+ 8011fa0:	e0bff417 	ldw	r2,-48(fp)
+ 8011fa4:	00c003c4 	movi	r3,15
+ 8011fa8:	10c00005 	stb	r3,0(r2)
+        return (pgrp);
+ 8011fac:	e0bff617 	ldw	r2,-40(fp)
+ 8011fb0:	00007106 	br	8012178 <OSFlagDel+0x208>
+    }
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event group type                */
+ 8011fb4:	e0bff617 	ldw	r2,-40(fp)
+ 8011fb8:	10800003 	ldbu	r2,0(r2)
+ 8011fbc:	10803fcc 	andi	r2,r2,255
+ 8011fc0:	10800160 	cmpeqi	r2,r2,5
+ 8011fc4:	1000051e 	bne	r2,zero,8011fdc <OSFlagDel+0x6c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8011fc8:	e0bff417 	ldw	r2,-48(fp)
+ 8011fcc:	00c00044 	movi	r3,1
+ 8011fd0:	10c00005 	stb	r3,0(r2)
+        return (pgrp);
+ 8011fd4:	e0bff617 	ldw	r2,-40(fp)
+ 8011fd8:	00006706 	br	8012178 <OSFlagDel+0x208>
+  NIOS2_READ_STATUS (context);
+ 8011fdc:	0005303a 	rdctl	r2,status
+ 8011fe0:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8011fe4:	e0fffb17 	ldw	r3,-20(fp)
+ 8011fe8:	00bfff84 	movi	r2,-2
+ 8011fec:	1884703a 	and	r2,r3,r2
+ 8011ff0:	1001703a 	wrctl	status,r2
+  return context;
+ 8011ff4:	e0bffb17 	ldw	r2,-20(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8011ff8:	e0bffc15 	stw	r2,-16(fp)
+    if (pgrp->OSFlagWaitList != (void *)0) {               /* See if any tasks waiting on event flags  */
+ 8011ffc:	e0bff617 	ldw	r2,-40(fp)
+ 8012000:	10800117 	ldw	r2,4(r2)
+ 8012004:	10000326 	beq	r2,zero,8012014 <OSFlagDel+0xa4>
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+ 8012008:	00800044 	movi	r2,1
+ 801200c:	e0bfffc5 	stb	r2,-1(fp)
+ 8012010:	00000106 	br	8012018 <OSFlagDel+0xa8>
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+ 8012014:	e03fffc5 	stb	zero,-1(fp)
+    }
+    switch (opt) {
+ 8012018:	e0bff503 	ldbu	r2,-44(fp)
+ 801201c:	10000326 	beq	r2,zero,801202c <OSFlagDel+0xbc>
+ 8012020:	10800060 	cmpeqi	r2,r2,1
+ 8012024:	1000231e 	bne	r2,zero,80120b4 <OSFlagDel+0x144>
+ 8012028:	00004806 	br	801214c <OSFlagDel+0x1dc>
+        case OS_DEL_NO_PEND:                               /* Delete group if no task waiting          */
+             if (tasks_waiting == OS_FALSE) {
+ 801202c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8012030:	1000161e 	bne	r2,zero,801208c <OSFlagDel+0x11c>
+#if OS_FLAG_NAME_SIZE > 1
+                 pgrp->OSFlagName[0]  = '?';               /* Unknown name                             */
+ 8012034:	e0bff617 	ldw	r2,-40(fp)
+ 8012038:	00c00fc4 	movi	r3,63
+ 801203c:	10c00285 	stb	r3,10(r2)
+                 pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+ 8012040:	e0bff617 	ldw	r2,-40(fp)
+ 8012044:	100002c5 	stb	zero,11(r2)
+#endif
+                 pgrp->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+ 8012048:	e0bff617 	ldw	r2,-40(fp)
+ 801204c:	10000005 	stb	zero,0(r2)
+                 pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list           */
+ 8012050:	d0e05a17 	ldw	r3,-32408(gp)
+ 8012054:	e0bff617 	ldw	r2,-40(fp)
+ 8012058:	10c00115 	stw	r3,4(r2)
+                 pgrp->OSFlagFlags    = (OS_FLAGS)0;
+ 801205c:	e0bff617 	ldw	r2,-40(fp)
+ 8012060:	1000020d 	sth	zero,8(r2)
+                 OSFlagFreeList       = pgrp;
+ 8012064:	e0bff617 	ldw	r2,-40(fp)
+ 8012068:	d0a05a15 	stw	r2,-32408(gp)
+ 801206c:	e0bffc17 	ldw	r2,-16(fp)
+ 8012070:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012074:	e0bffa17 	ldw	r2,-24(fp)
+ 8012078:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+                 *perr                = OS_ERR_NONE;
+ 801207c:	e0bff417 	ldw	r2,-48(fp)
+ 8012080:	10000005 	stb	zero,0(r2)
+                 pgrp_return          = (OS_FLAG_GRP *)0;  /* Event Flag Group has been deleted        */
+ 8012084:	e03ffd15 	stw	zero,-12(fp)
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                = OS_ERR_TASK_WAITING;
+                 pgrp_return          = pgrp;
+             }
+             break;
+ 8012088:	00003a06 	br	8012174 <OSFlagDel+0x204>
+ 801208c:	e0bffc17 	ldw	r2,-16(fp)
+ 8012090:	e0bff915 	stw	r2,-28(fp)
+ 8012094:	e0bff917 	ldw	r2,-28(fp)
+ 8012098:	1001703a 	wrctl	status,r2
+                 *perr                = OS_ERR_TASK_WAITING;
+ 801209c:	e0bff417 	ldw	r2,-48(fp)
+ 80120a0:	00c01244 	movi	r3,73
+ 80120a4:	10c00005 	stb	r3,0(r2)
+                 pgrp_return          = pgrp;
+ 80120a8:	e0bff617 	ldw	r2,-40(fp)
+ 80120ac:	e0bffd15 	stw	r2,-12(fp)
+             break;
+ 80120b0:	00003006 	br	8012174 <OSFlagDel+0x204>
+
+        case OS_DEL_ALWAYS:                                /* Always delete the event flag group       */
+             pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+ 80120b4:	e0bff617 	ldw	r2,-40(fp)
+ 80120b8:	10800117 	ldw	r2,4(r2)
+ 80120bc:	e0bffe15 	stw	r2,-8(fp)
+             while (pnode != (OS_FLAG_NODE *)0) {          /* Ready ALL tasks waiting for flags        */
+ 80120c0:	00000606 	br	80120dc <OSFlagDel+0x16c>
+                 (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0);
+ 80120c4:	000b883a 	mov	r5,zero
+ 80120c8:	e13ffe17 	ldw	r4,-8(fp)
+ 80120cc:	8012fb80 	call	8012fb8 <OS_FlagTaskRdy>
+                 pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext;
+ 80120d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80120d4:	10800017 	ldw	r2,0(r2)
+ 80120d8:	e0bffe15 	stw	r2,-8(fp)
+             while (pnode != (OS_FLAG_NODE *)0) {          /* Ready ALL tasks waiting for flags        */
+ 80120dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80120e0:	103ff81e 	bne	r2,zero,80120c4 <OSFlagDel+0x154>
+             }
+#if OS_FLAG_NAME_SIZE > 1
+             pgrp->OSFlagName[0]  = '?';                   /* Unknown name                             */
+ 80120e4:	e0bff617 	ldw	r2,-40(fp)
+ 80120e8:	00c00fc4 	movi	r3,63
+ 80120ec:	10c00285 	stb	r3,10(r2)
+             pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+ 80120f0:	e0bff617 	ldw	r2,-40(fp)
+ 80120f4:	100002c5 	stb	zero,11(r2)
+#endif
+             pgrp->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+ 80120f8:	e0bff617 	ldw	r2,-40(fp)
+ 80120fc:	10000005 	stb	zero,0(r2)
+             pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list                */
+ 8012100:	d0e05a17 	ldw	r3,-32408(gp)
+ 8012104:	e0bff617 	ldw	r2,-40(fp)
+ 8012108:	10c00115 	stw	r3,4(r2)
+             pgrp->OSFlagFlags    = (OS_FLAGS)0;
+ 801210c:	e0bff617 	ldw	r2,-40(fp)
+ 8012110:	1000020d 	sth	zero,8(r2)
+             OSFlagFreeList       = pgrp;
+ 8012114:	e0bff617 	ldw	r2,-40(fp)
+ 8012118:	d0a05a15 	stw	r2,-32408(gp)
+ 801211c:	e0bffc17 	ldw	r2,-16(fp)
+ 8012120:	e0bff815 	stw	r2,-32(fp)
+ 8012124:	e0bff817 	ldw	r2,-32(fp)
+ 8012128:	1001703a 	wrctl	status,r2
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+ 801212c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8012130:	10800058 	cmpnei	r2,r2,1
+ 8012134:	1000011e 	bne	r2,zero,801213c <OSFlagDel+0x1cc>
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+ 8012138:	801166c0 	call	801166c <OS_Sched>
+             }
+             *perr = OS_ERR_NONE;
+ 801213c:	e0bff417 	ldw	r2,-48(fp)
+ 8012140:	10000005 	stb	zero,0(r2)
+             pgrp_return          = (OS_FLAG_GRP *)0;      /* Event Flag Group has been deleted        */
+ 8012144:	e03ffd15 	stw	zero,-12(fp)
+             break;
+ 8012148:	00000a06 	br	8012174 <OSFlagDel+0x204>
+ 801214c:	e0bffc17 	ldw	r2,-16(fp)
+ 8012150:	e0bff715 	stw	r2,-36(fp)
+ 8012154:	e0bff717 	ldw	r2,-36(fp)
+ 8012158:	1001703a 	wrctl	status,r2
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                = OS_ERR_INVALID_OPT;
+ 801215c:	e0bff417 	ldw	r2,-48(fp)
+ 8012160:	00c001c4 	movi	r3,7
+ 8012164:	10c00005 	stb	r3,0(r2)
+             pgrp_return          = pgrp;
+ 8012168:	e0bff617 	ldw	r2,-40(fp)
+ 801216c:	e0bffd15 	stw	r2,-12(fp)
+             break;
+ 8012170:	0001883a 	nop
+    }
+    return (pgrp_return);
+ 8012174:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8012178:	e037883a 	mov	sp,fp
+ 801217c:	dfc00117 	ldw	ra,4(sp)
+ 8012180:	df000017 	ldw	fp,0(sp)
+ 8012184:	dec00204 	addi	sp,sp,8
+ 8012188:	f800283a 	ret
+
+0801218c <OSFlagNameGet>:
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_NAME_SIZE > 1
+INT8U  OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr)
+{
+ 801218c:	defff604 	addi	sp,sp,-40
+ 8012190:	dfc00915 	stw	ra,36(sp)
+ 8012194:	df000815 	stw	fp,32(sp)
+ 8012198:	df000804 	addi	fp,sp,32
+ 801219c:	e13ffa15 	stw	r4,-24(fp)
+ 80121a0:	e17ff915 	stw	r5,-28(fp)
+ 80121a4:	e1bff815 	stw	r6,-32(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 80121a8:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 80121ac:	d0a05703 	ldbu	r2,-32420(gp)
+ 80121b0:	10803fcc 	andi	r2,r2,255
+ 80121b4:	10000526 	beq	r2,zero,80121cc <OSFlagNameGet+0x40>
+        *perr = OS_ERR_NAME_GET_ISR;
+ 80121b8:	e0bff817 	ldw	r2,-32(fp)
+ 80121bc:	00c00444 	movi	r3,17
+ 80121c0:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 80121c4:	0005883a 	mov	r2,zero
+ 80121c8:	00002306 	br	8012258 <OSFlagNameGet+0xcc>
+  NIOS2_READ_STATUS (context);
+ 80121cc:	0005303a 	rdctl	r2,status
+ 80121d0:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80121d4:	e0fffd17 	ldw	r3,-12(fp)
+ 80121d8:	00bfff84 	movi	r2,-2
+ 80121dc:	1884703a 	and	r2,r3,r2
+ 80121e0:	1001703a 	wrctl	status,r2
+  return context;
+ 80121e4:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80121e8:	e0bfff15 	stw	r2,-4(fp)
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {
+ 80121ec:	e0bffa17 	ldw	r2,-24(fp)
+ 80121f0:	10800003 	ldbu	r2,0(r2)
+ 80121f4:	10803fcc 	andi	r2,r2,255
+ 80121f8:	10800160 	cmpeqi	r2,r2,5
+ 80121fc:	1000091e 	bne	r2,zero,8012224 <OSFlagNameGet+0x98>
+ 8012200:	e0bfff17 	ldw	r2,-4(fp)
+ 8012204:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012208:	e0bffc17 	ldw	r2,-16(fp)
+ 801220c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_TYPE;
+ 8012210:	e0bff817 	ldw	r2,-32(fp)
+ 8012214:	00c00044 	movi	r3,1
+ 8012218:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 801221c:	0005883a 	mov	r2,zero
+ 8012220:	00000d06 	br	8012258 <OSFlagNameGet+0xcc>
+    }
+    len   = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP                         */
+ 8012224:	e0bffa17 	ldw	r2,-24(fp)
+ 8012228:	10800284 	addi	r2,r2,10
+ 801222c:	100b883a 	mov	r5,r2
+ 8012230:	e13ff917 	ldw	r4,-28(fp)
+ 8012234:	80117a00 	call	80117a0 <OS_StrCopy>
+ 8012238:	e0bffec5 	stb	r2,-5(fp)
+ 801223c:	e0bfff17 	ldw	r2,-4(fp)
+ 8012240:	e0bffb15 	stw	r2,-20(fp)
+ 8012244:	e0bffb17 	ldw	r2,-20(fp)
+ 8012248:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 801224c:	e0bff817 	ldw	r2,-32(fp)
+ 8012250:	10000005 	stb	zero,0(r2)
+    return (len);
+ 8012254:	e0bffec3 	ldbu	r2,-5(fp)
+}
+ 8012258:	e037883a 	mov	sp,fp
+ 801225c:	dfc00117 	ldw	ra,4(sp)
+ 8012260:	df000017 	ldw	fp,0(sp)
+ 8012264:	dec00204 	addi	sp,sp,8
+ 8012268:	f800283a 	ret
+
+0801226c <OSFlagNameSet>:
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_NAME_SIZE > 1
+void  OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr)
+{
+ 801226c:	defff504 	addi	sp,sp,-44
+ 8012270:	dfc00a15 	stw	ra,40(sp)
+ 8012274:	df000915 	stw	fp,36(sp)
+ 8012278:	df000904 	addi	fp,sp,36
+ 801227c:	e13ff915 	stw	r4,-28(fp)
+ 8012280:	e17ff815 	stw	r5,-32(fp)
+ 8012284:	e1bff715 	stw	r6,-36(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8012288:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 801228c:	d0a05703 	ldbu	r2,-32420(gp)
+ 8012290:	10803fcc 	andi	r2,r2,255
+ 8012294:	10000426 	beq	r2,zero,80122a8 <OSFlagNameSet+0x3c>
+        *perr = OS_ERR_NAME_SET_ISR;
+ 8012298:	e0bff717 	ldw	r2,-36(fp)
+ 801229c:	00c00484 	movi	r3,18
+ 80122a0:	10c00005 	stb	r3,0(r2)
+        return;
+ 80122a4:	00002f06 	br	8012364 <OSFlagNameSet+0xf8>
+  NIOS2_READ_STATUS (context);
+ 80122a8:	0005303a 	rdctl	r2,status
+ 80122ac:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80122b0:	e0fffd17 	ldw	r3,-12(fp)
+ 80122b4:	00bfff84 	movi	r2,-2
+ 80122b8:	1884703a 	and	r2,r3,r2
+ 80122bc:	1001703a 	wrctl	status,r2
+  return context;
+ 80122c0:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80122c4:	e0bfff15 	stw	r2,-4(fp)
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {
+ 80122c8:	e0bff917 	ldw	r2,-28(fp)
+ 80122cc:	10800003 	ldbu	r2,0(r2)
+ 80122d0:	10803fcc 	andi	r2,r2,255
+ 80122d4:	10800160 	cmpeqi	r2,r2,5
+ 80122d8:	1000081e 	bne	r2,zero,80122fc <OSFlagNameSet+0x90>
+ 80122dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80122e0:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80122e4:	e0bffc17 	ldw	r2,-16(fp)
+ 80122e8:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_TYPE;
+ 80122ec:	e0bff717 	ldw	r2,-36(fp)
+ 80122f0:	00c00044 	movi	r3,1
+ 80122f4:	10c00005 	stb	r3,0(r2)
+        return;
+ 80122f8:	00001a06 	br	8012364 <OSFlagNameSet+0xf8>
+    }
+    len = OS_StrLen(pname);                      /* Can we fit the string in the storage area?         */
+ 80122fc:	e13ff817 	ldw	r4,-32(fp)
+ 8012300:	80118140 	call	8011814 <OS_StrLen>
+ 8012304:	e0bffec5 	stb	r2,-5(fp)
+    if (len > (OS_FLAG_NAME_SIZE - 1)) {         /* No                                                 */
+ 8012308:	e0bffec3 	ldbu	r2,-5(fp)
+ 801230c:	10800830 	cmpltui	r2,r2,32
+ 8012310:	1000081e 	bne	r2,zero,8012334 <OSFlagNameSet+0xc8>
+ 8012314:	e0bfff17 	ldw	r2,-4(fp)
+ 8012318:	e0bffb15 	stw	r2,-20(fp)
+ 801231c:	e0bffb17 	ldw	r2,-20(fp)
+ 8012320:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_FLAG_NAME_TOO_LONG;
+ 8012324:	e0bff717 	ldw	r2,-36(fp)
+ 8012328:	00c01cc4 	movi	r3,115
+ 801232c:	10c00005 	stb	r3,0(r2)
+        return;
+ 8012330:	00000c06 	br	8012364 <OSFlagNameSet+0xf8>
+    }
+    (void)OS_StrCopy(pgrp->OSFlagName, pname);   /* Yes, copy name from OS_FLAG_GRP                    */
+ 8012334:	e0bff917 	ldw	r2,-28(fp)
+ 8012338:	10800284 	addi	r2,r2,10
+ 801233c:	e17ff817 	ldw	r5,-32(fp)
+ 8012340:	1009883a 	mov	r4,r2
+ 8012344:	80117a00 	call	80117a0 <OS_StrCopy>
+ 8012348:	e0bfff17 	ldw	r2,-4(fp)
+ 801234c:	e0bffa15 	stw	r2,-24(fp)
+ 8012350:	e0bffa17 	ldw	r2,-24(fp)
+ 8012354:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8012358:	e0bff717 	ldw	r2,-36(fp)
+ 801235c:	10000005 	stb	zero,0(r2)
+    return;
+ 8012360:	0001883a 	nop
+}
+ 8012364:	e037883a 	mov	sp,fp
+ 8012368:	dfc00117 	ldw	ra,4(sp)
+ 801236c:	df000017 	ldw	fp,0(sp)
+ 8012370:	dec00204 	addi	sp,sp,8
+ 8012374:	f800283a 	ret
+
+08012378 <OSFlagPend>:
+*                 event flags.
+*********************************************************************************************************
+*/
+
+OS_FLAGS  OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr)
+{
+ 8012378:	deffe204 	addi	sp,sp,-120
+ 801237c:	dfc01d15 	stw	ra,116(sp)
+ 8012380:	df001c15 	stw	fp,112(sp)
+ 8012384:	df001c04 	addi	fp,sp,112
+ 8012388:	e13fe815 	stw	r4,-96(fp)
+ 801238c:	2805883a 	mov	r2,r5
+ 8012390:	3009883a 	mov	r4,r6
+ 8012394:	3807883a 	mov	r3,r7
+ 8012398:	e0bfe70d 	sth	r2,-100(fp)
+ 801239c:	2005883a 	mov	r2,r4
+ 80123a0:	e0bfe605 	stb	r2,-104(fp)
+ 80123a4:	1805883a 	mov	r2,r3
+ 80123a8:	e0bfe50d 	sth	r2,-108(fp)
+    OS_FLAGS      flags_rdy;
+    INT8U         result;
+    INT8U         pend_stat;
+    BOOLEAN       consume;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+ 80123ac:	e03ffe15 	stw	zero,-8(fp)
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 80123b0:	d0a05703 	ldbu	r2,-32420(gp)
+ 80123b4:	10803fcc 	andi	r2,r2,255
+ 80123b8:	10000526 	beq	r2,zero,80123d0 <OSFlagPend+0x58>
+        *perr = OS_ERR_PEND_ISR;                           /* ... can't PEND from an ISR               */
+ 80123bc:	e0800217 	ldw	r2,8(fp)
+ 80123c0:	00c00084 	movi	r3,2
+ 80123c4:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 80123c8:	0005883a 	mov	r2,zero
+ 80123cc:	00014b06 	br	80128fc <OSFlagPend+0x584>
+    }
+    if (OSLockNesting > 0) {                               /* See if called with scheduler locked ...  */
+ 80123d0:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80123d4:	10803fcc 	andi	r2,r2,255
+ 80123d8:	10000526 	beq	r2,zero,80123f0 <OSFlagPend+0x78>
+        *perr = OS_ERR_PEND_LOCKED;                        /* ... can't PEND when locked               */
+ 80123dc:	e0800217 	ldw	r2,8(fp)
+ 80123e0:	00c00344 	movi	r3,13
+ 80123e4:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 80123e8:	0005883a 	mov	r2,zero
+ 80123ec:	00014306 	br	80128fc <OSFlagPend+0x584>
+    }
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event block type                */
+ 80123f0:	e0bfe817 	ldw	r2,-96(fp)
+ 80123f4:	10800003 	ldbu	r2,0(r2)
+ 80123f8:	10803fcc 	andi	r2,r2,255
+ 80123fc:	10800160 	cmpeqi	r2,r2,5
+ 8012400:	1000051e 	bne	r2,zero,8012418 <OSFlagPend+0xa0>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8012404:	e0800217 	ldw	r2,8(fp)
+ 8012408:	00c00044 	movi	r3,1
+ 801240c:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 8012410:	0005883a 	mov	r2,zero
+ 8012414:	00013906 	br	80128fc <OSFlagPend+0x584>
+    }
+    result = (INT8U)(wait_type & OS_FLAG_CONSUME);
+ 8012418:	e0ffe603 	ldbu	r3,-104(fp)
+ 801241c:	00bfe004 	movi	r2,-128
+ 8012420:	1884703a 	and	r2,r3,r2
+ 8012424:	e0bffdc5 	stb	r2,-9(fp)
+    if (result != (INT8U)0) {                             /* See if we need to consume the flags      */
+ 8012428:	e0bffdc3 	ldbu	r2,-9(fp)
+ 801242c:	10000626 	beq	r2,zero,8012448 <OSFlagPend+0xd0>
+        wait_type &= ~(INT8U)OS_FLAG_CONSUME;
+ 8012430:	e0bfe603 	ldbu	r2,-104(fp)
+ 8012434:	10801fcc 	andi	r2,r2,127
+ 8012438:	e0bfe605 	stb	r2,-104(fp)
+        consume    = OS_TRUE;
+ 801243c:	00800044 	movi	r2,1
+ 8012440:	e0bfffc5 	stb	r2,-1(fp)
+ 8012444:	00000106 	br	801244c <OSFlagPend+0xd4>
+    } else {
+        consume    = OS_FALSE;
+ 8012448:	e03fffc5 	stb	zero,-1(fp)
+  NIOS2_READ_STATUS (context);
+ 801244c:	0005303a 	rdctl	r2,status
+ 8012450:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8012454:	e0fffb17 	ldw	r3,-20(fp)
+ 8012458:	00bfff84 	movi	r2,-2
+ 801245c:	1884703a 	and	r2,r3,r2
+ 8012460:	1001703a 	wrctl	status,r2
+  return context;
+ 8012464:	e0bffb17 	ldw	r2,-20(fp)
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+ 8012468:	e0bffe15 	stw	r2,-8(fp)
+    switch (wait_type) {
+ 801246c:	e0bfe603 	ldbu	r2,-104(fp)
+ 8012470:	10c00060 	cmpeqi	r3,r2,1
+ 8012474:	1800921e 	bne	r3,zero,80126c0 <OSFlagPend+0x348>
+ 8012478:	10c00088 	cmpgei	r3,r2,2
+ 801247c:	1800021e 	bne	r3,zero,8012488 <OSFlagPend+0x110>
+ 8012480:	10006126 	beq	r2,zero,8012608 <OSFlagPend+0x290>
+ 8012484:	0000bb06 	br	8012774 <OSFlagPend+0x3fc>
+ 8012488:	10c000a0 	cmpeqi	r3,r2,2
+ 801248c:	1800031e 	bne	r3,zero,801249c <OSFlagPend+0x124>
+ 8012490:	108000e0 	cmpeqi	r2,r2,3
+ 8012494:	10002f1e 	bne	r2,zero,8012554 <OSFlagPend+0x1dc>
+ 8012498:	0000b606 	br	8012774 <OSFlagPend+0x3fc>
+        case OS_FLAG_WAIT_SET_ALL:                         /* See if all required flags are set        */
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);   /* Extract only the bits we want     */
+ 801249c:	e0bfe817 	ldw	r2,-96(fp)
+ 80124a0:	1080020b 	ldhu	r2,8(r2)
+ 80124a4:	e0ffe70b 	ldhu	r3,-100(fp)
+ 80124a8:	1884703a 	and	r2,r3,r2
+ 80124ac:	e0bffd0d 	sth	r2,-12(fp)
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+ 80124b0:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80124b4:	e0bfe70b 	ldhu	r2,-100(fp)
+ 80124b8:	1880171e 	bne	r3,r2,8012518 <OSFlagPend+0x1a0>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 80124bc:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80124c0:	10800058 	cmpnei	r2,r2,1
+ 80124c4:	1000091e 	bne	r2,zero,80124ec <OSFlagPend+0x174>
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we wanted      */
+ 80124c8:	e0bfe817 	ldw	r2,-96(fp)
+ 80124cc:	1080020b 	ldhu	r2,8(r2)
+ 80124d0:	1007883a 	mov	r3,r2
+ 80124d4:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80124d8:	0084303a 	nor	r2,zero,r2
+ 80124dc:	1884703a 	and	r2,r3,r2
+ 80124e0:	1007883a 	mov	r3,r2
+ 80124e4:	e0bfe817 	ldw	r2,-96(fp)
+ 80124e8:	10c0020d 	sth	r3,8(r2)
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+ 80124ec:	d0a05817 	ldw	r2,-32416(gp)
+ 80124f0:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80124f4:	10c00b0d 	sth	r3,44(r2)
+ 80124f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80124fc:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012500:	e0bffa17 	ldw	r2,-24(fp)
+ 8012504:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+ 8012508:	e0800217 	ldw	r2,8(fp)
+ 801250c:	10000005 	stb	zero,0(r2)
+                 return (flags_rdy);
+ 8012510:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8012514:	0000f906 	br	80128fc <OSFlagPend+0x584>
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+ 8012518:	e13fe70b 	ldhu	r4,-100(fp)
+ 801251c:	e17fe603 	ldbu	r5,-104(fp)
+ 8012520:	e0bfe50b 	ldhu	r2,-108(fp)
+ 8012524:	e0ffe904 	addi	r3,fp,-92
+ 8012528:	d8800015 	stw	r2,0(sp)
+ 801252c:	280f883a 	mov	r7,r5
+ 8012530:	200d883a 	mov	r6,r4
+ 8012534:	180b883a 	mov	r5,r3
+ 8012538:	e13fe817 	ldw	r4,-96(fp)
+ 801253c:	8012d740 	call	8012d74 <OS_FlagBlock>
+ 8012540:	e0bffe17 	ldw	r2,-8(fp)
+ 8012544:	e0bff915 	stw	r2,-28(fp)
+ 8012548:	e0bff917 	ldw	r2,-28(fp)
+ 801254c:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+ 8012550:	00009206 	br	801279c <OSFlagPend+0x424>
+
+        case OS_FLAG_WAIT_SET_ANY:
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);    /* Extract only the bits we want    */
+ 8012554:	e0bfe817 	ldw	r2,-96(fp)
+ 8012558:	1080020b 	ldhu	r2,8(r2)
+ 801255c:	e0ffe70b 	ldhu	r3,-100(fp)
+ 8012560:	1884703a 	and	r2,r3,r2
+ 8012564:	e0bffd0d 	sth	r2,-12(fp)
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag set                      */
+ 8012568:	e0bffd0b 	ldhu	r2,-12(fp)
+ 801256c:	10001726 	beq	r2,zero,80125cc <OSFlagPend+0x254>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8012570:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8012574:	10800058 	cmpnei	r2,r2,1
+ 8012578:	1000091e 	bne	r2,zero,80125a0 <OSFlagPend+0x228>
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we got         */
+ 801257c:	e0bfe817 	ldw	r2,-96(fp)
+ 8012580:	1080020b 	ldhu	r2,8(r2)
+ 8012584:	1007883a 	mov	r3,r2
+ 8012588:	e0bffd0b 	ldhu	r2,-12(fp)
+ 801258c:	0084303a 	nor	r2,zero,r2
+ 8012590:	1884703a 	and	r2,r3,r2
+ 8012594:	1007883a 	mov	r3,r2
+ 8012598:	e0bfe817 	ldw	r2,-96(fp)
+ 801259c:	10c0020d 	sth	r3,8(r2)
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+ 80125a0:	d0a05817 	ldw	r2,-32416(gp)
+ 80125a4:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80125a8:	10c00b0d 	sth	r3,44(r2)
+ 80125ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80125b0:	e0bff815 	stw	r2,-32(fp)
+ 80125b4:	e0bff817 	ldw	r2,-32(fp)
+ 80125b8:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+ 80125bc:	e0800217 	ldw	r2,8(fp)
+ 80125c0:	10000005 	stb	zero,0(r2)
+                 return (flags_rdy);
+ 80125c4:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80125c8:	0000cc06 	br	80128fc <OSFlagPend+0x584>
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+ 80125cc:	e13fe70b 	ldhu	r4,-100(fp)
+ 80125d0:	e17fe603 	ldbu	r5,-104(fp)
+ 80125d4:	e0bfe50b 	ldhu	r2,-108(fp)
+ 80125d8:	e0ffe904 	addi	r3,fp,-92
+ 80125dc:	d8800015 	stw	r2,0(sp)
+ 80125e0:	280f883a 	mov	r7,r5
+ 80125e4:	200d883a 	mov	r6,r4
+ 80125e8:	180b883a 	mov	r5,r3
+ 80125ec:	e13fe817 	ldw	r4,-96(fp)
+ 80125f0:	8012d740 	call	8012d74 <OS_FlagBlock>
+ 80125f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80125f8:	e0bff715 	stw	r2,-36(fp)
+ 80125fc:	e0bff717 	ldw	r2,-36(fp)
+ 8012600:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+ 8012604:	00006506 	br	801279c <OSFlagPend+0x424>
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+        case OS_FLAG_WAIT_CLR_ALL:                         /* See if all required flags are cleared    */
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags);  /* Extract only the bits we want     */
+ 8012608:	e0bfe817 	ldw	r2,-96(fp)
+ 801260c:	1080020b 	ldhu	r2,8(r2)
+ 8012610:	0084303a 	nor	r2,zero,r2
+ 8012614:	1007883a 	mov	r3,r2
+ 8012618:	e0bfe70b 	ldhu	r2,-100(fp)
+ 801261c:	1884703a 	and	r2,r3,r2
+ 8012620:	e0bffd0d 	sth	r2,-12(fp)
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+ 8012624:	e0fffd0b 	ldhu	r3,-12(fp)
+ 8012628:	e0bfe70b 	ldhu	r2,-100(fp)
+ 801262c:	1880151e 	bne	r3,r2,8012684 <OSFlagPend+0x30c>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 8012630:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8012634:	10800058 	cmpnei	r2,r2,1
+ 8012638:	1000071e 	bne	r2,zero,8012658 <OSFlagPend+0x2e0>
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we wanted        */
+ 801263c:	e0bfe817 	ldw	r2,-96(fp)
+ 8012640:	1080020b 	ldhu	r2,8(r2)
+ 8012644:	e0fffd0b 	ldhu	r3,-12(fp)
+ 8012648:	1884b03a 	or	r2,r3,r2
+ 801264c:	1007883a 	mov	r3,r2
+ 8012650:	e0bfe817 	ldw	r2,-96(fp)
+ 8012654:	10c0020d 	sth	r3,8(r2)
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+ 8012658:	d0a05817 	ldw	r2,-32416(gp)
+ 801265c:	e0fffd0b 	ldhu	r3,-12(fp)
+ 8012660:	10c00b0d 	sth	r3,44(r2)
+ 8012664:	e0bffe17 	ldw	r2,-8(fp)
+ 8012668:	e0bff615 	stw	r2,-40(fp)
+ 801266c:	e0bff617 	ldw	r2,-40(fp)
+ 8012670:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+ 8012674:	e0800217 	ldw	r2,8(fp)
+ 8012678:	10000005 	stb	zero,0(r2)
+                 return (flags_rdy);
+ 801267c:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8012680:	00009e06 	br	80128fc <OSFlagPend+0x584>
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+ 8012684:	e13fe70b 	ldhu	r4,-100(fp)
+ 8012688:	e17fe603 	ldbu	r5,-104(fp)
+ 801268c:	e0bfe50b 	ldhu	r2,-108(fp)
+ 8012690:	e0ffe904 	addi	r3,fp,-92
+ 8012694:	d8800015 	stw	r2,0(sp)
+ 8012698:	280f883a 	mov	r7,r5
+ 801269c:	200d883a 	mov	r6,r4
+ 80126a0:	180b883a 	mov	r5,r3
+ 80126a4:	e13fe817 	ldw	r4,-96(fp)
+ 80126a8:	8012d740 	call	8012d74 <OS_FlagBlock>
+ 80126ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80126b0:	e0bff515 	stw	r2,-44(fp)
+ 80126b4:	e0bff517 	ldw	r2,-44(fp)
+ 80126b8:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+ 80126bc:	00003706 	br	801279c <OSFlagPend+0x424>
+
+        case OS_FLAG_WAIT_CLR_ANY:
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want      */
+ 80126c0:	e0bfe817 	ldw	r2,-96(fp)
+ 80126c4:	1080020b 	ldhu	r2,8(r2)
+ 80126c8:	0084303a 	nor	r2,zero,r2
+ 80126cc:	1007883a 	mov	r3,r2
+ 80126d0:	e0bfe70b 	ldhu	r2,-100(fp)
+ 80126d4:	1884703a 	and	r2,r3,r2
+ 80126d8:	e0bffd0d 	sth	r2,-12(fp)
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag cleared                  */
+ 80126dc:	e0bffd0b 	ldhu	r2,-12(fp)
+ 80126e0:	10001526 	beq	r2,zero,8012738 <OSFlagPend+0x3c0>
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+ 80126e4:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80126e8:	10800058 	cmpnei	r2,r2,1
+ 80126ec:	1000071e 	bne	r2,zero,801270c <OSFlagPend+0x394>
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we got           */
+ 80126f0:	e0bfe817 	ldw	r2,-96(fp)
+ 80126f4:	1080020b 	ldhu	r2,8(r2)
+ 80126f8:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80126fc:	1884b03a 	or	r2,r3,r2
+ 8012700:	1007883a 	mov	r3,r2
+ 8012704:	e0bfe817 	ldw	r2,-96(fp)
+ 8012708:	10c0020d 	sth	r3,8(r2)
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+ 801270c:	d0a05817 	ldw	r2,-32416(gp)
+ 8012710:	e0fffd0b 	ldhu	r3,-12(fp)
+ 8012714:	10c00b0d 	sth	r3,44(r2)
+ 8012718:	e0bffe17 	ldw	r2,-8(fp)
+ 801271c:	e0bff415 	stw	r2,-48(fp)
+ 8012720:	e0bff417 	ldw	r2,-48(fp)
+ 8012724:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+ 8012728:	e0800217 	ldw	r2,8(fp)
+ 801272c:	10000005 	stb	zero,0(r2)
+                 return (flags_rdy);
+ 8012730:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8012734:	00007106 	br	80128fc <OSFlagPend+0x584>
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+ 8012738:	e13fe70b 	ldhu	r4,-100(fp)
+ 801273c:	e17fe603 	ldbu	r5,-104(fp)
+ 8012740:	e0bfe50b 	ldhu	r2,-108(fp)
+ 8012744:	e0ffe904 	addi	r3,fp,-92
+ 8012748:	d8800015 	stw	r2,0(sp)
+ 801274c:	280f883a 	mov	r7,r5
+ 8012750:	200d883a 	mov	r6,r4
+ 8012754:	180b883a 	mov	r5,r3
+ 8012758:	e13fe817 	ldw	r4,-96(fp)
+ 801275c:	8012d740 	call	8012d74 <OS_FlagBlock>
+ 8012760:	e0bffe17 	ldw	r2,-8(fp)
+ 8012764:	e0bff315 	stw	r2,-52(fp)
+ 8012768:	e0bff317 	ldw	r2,-52(fp)
+ 801276c:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+ 8012770:	00000a06 	br	801279c <OSFlagPend+0x424>
+ 8012774:	e0bffe17 	ldw	r2,-8(fp)
+ 8012778:	e0bff215 	stw	r2,-56(fp)
+ 801277c:	e0bff217 	ldw	r2,-56(fp)
+ 8012780:	1001703a 	wrctl	status,r2
+#endif
+
+        default:
+             OS_EXIT_CRITICAL();
+             flags_rdy = (OS_FLAGS)0;
+ 8012784:	e03ffd0d 	sth	zero,-12(fp)
+             *perr      = OS_ERR_FLAG_WAIT_TYPE;
+ 8012788:	e0800217 	ldw	r2,8(fp)
+ 801278c:	00c01bc4 	movi	r3,111
+ 8012790:	10c00005 	stb	r3,0(r2)
+             return (flags_rdy);
+ 8012794:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8012798:	00005806 	br	80128fc <OSFlagPend+0x584>
+    }
+/*$PAGE*/
+    OS_Sched();                                            /* Find next HPT ready to run               */
+ 801279c:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 80127a0:	0005303a 	rdctl	r2,status
+ 80127a4:	e0bff115 	stw	r2,-60(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80127a8:	e0fff117 	ldw	r3,-60(fp)
+ 80127ac:	00bfff84 	movi	r2,-2
+ 80127b0:	1884703a 	and	r2,r3,r2
+ 80127b4:	1001703a 	wrctl	status,r2
+  return context;
+ 80127b8:	e0bff117 	ldw	r2,-60(fp)
+    OS_ENTER_CRITICAL();
+ 80127bc:	e0bffe15 	stw	r2,-8(fp)
+    if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) {      /* Have we timed-out or aborted?            */
+ 80127c0:	d0a05817 	ldw	r2,-32416(gp)
+ 80127c4:	10800c43 	ldbu	r2,49(r2)
+ 80127c8:	10803fcc 	andi	r2,r2,255
+ 80127cc:	10001c26 	beq	r2,zero,8012840 <OSFlagPend+0x4c8>
+        pend_stat                = OSTCBCur->OSTCBStatPend;
+ 80127d0:	d0a05817 	ldw	r2,-32416(gp)
+ 80127d4:	10800c43 	ldbu	r2,49(r2)
+ 80127d8:	e0bffcc5 	stb	r2,-13(fp)
+        OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 80127dc:	d0a05817 	ldw	r2,-32416(gp)
+ 80127e0:	10000c45 	stb	zero,49(r2)
+        OS_FlagUnlink(&node);
+ 80127e4:	e0bfe904 	addi	r2,fp,-92
+ 80127e8:	1009883a 	mov	r4,r2
+ 80127ec:	80130ac0 	call	80130ac <OS_FlagUnlink>
+        OSTCBCur->OSTCBStat      = OS_STAT_RDY;            /* Yes, make task ready-to-run              */
+ 80127f0:	d0a05817 	ldw	r2,-32416(gp)
+ 80127f4:	10000c05 	stb	zero,48(r2)
+ 80127f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80127fc:	e0bff015 	stw	r2,-64(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012800:	e0bff017 	ldw	r2,-64(fp)
+ 8012804:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        flags_rdy                = (OS_FLAGS)0;
+ 8012808:	e03ffd0d 	sth	zero,-12(fp)
+        switch (pend_stat) {
+ 801280c:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8012810:	10800098 	cmpnei	r2,r2,2
+ 8012814:	1000041e 	bne	r2,zero,8012828 <OSFlagPend+0x4b0>
+            case OS_STAT_PEND_ABORT:
+                 *perr = OS_ERR_PEND_ABORT;                 /* Indicate that we aborted   waiting       */
+ 8012818:	e0800217 	ldw	r2,8(fp)
+ 801281c:	00c00384 	movi	r3,14
+ 8012820:	10c00005 	stb	r3,0(r2)
+                 break;
+ 8012824:	00000406 	br	8012838 <OSFlagPend+0x4c0>
+
+            case OS_STAT_PEND_TO:
+            default:
+                 *perr = OS_ERR_TIMEOUT;                    /* Indicate that we timed-out waiting       */
+ 8012828:	e0800217 	ldw	r2,8(fp)
+ 801282c:	00c00284 	movi	r3,10
+ 8012830:	10c00005 	stb	r3,0(r2)
+                 break;
+ 8012834:	0001883a 	nop
+        }
+        return (flags_rdy);
+ 8012838:	e0bffd0b 	ldhu	r2,-12(fp)
+ 801283c:	00002f06 	br	80128fc <OSFlagPend+0x584>
+    }
+    flags_rdy = OSTCBCur->OSTCBFlagsRdy;
+ 8012840:	d0a05817 	ldw	r2,-32416(gp)
+ 8012844:	10800b0b 	ldhu	r2,44(r2)
+ 8012848:	e0bffd0d 	sth	r2,-12(fp)
+    if (consume == OS_TRUE) {                              /* See if we need to consume the flags      */
+ 801284c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8012850:	10800058 	cmpnei	r2,r2,1
+ 8012854:	1000211e 	bne	r2,zero,80128dc <OSFlagPend+0x564>
+        switch (wait_type) {
+ 8012858:	e0bfe603 	ldbu	r2,-104(fp)
+ 801285c:	10001616 	blt	r2,zero,80128b8 <OSFlagPend+0x540>
+ 8012860:	10c00090 	cmplti	r3,r2,2
+ 8012864:	18000c1e 	bne	r3,zero,8012898 <OSFlagPend+0x520>
+ 8012868:	10800108 	cmpgei	r2,r2,4
+ 801286c:	1000121e 	bne	r2,zero,80128b8 <OSFlagPend+0x540>
+            case OS_FLAG_WAIT_SET_ALL:
+            case OS_FLAG_WAIT_SET_ANY:                     /* Clear ONLY the flags we got              */
+                 pgrp->OSFlagFlags &= ~flags_rdy;
+ 8012870:	e0bfe817 	ldw	r2,-96(fp)
+ 8012874:	1080020b 	ldhu	r2,8(r2)
+ 8012878:	1007883a 	mov	r3,r2
+ 801287c:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8012880:	0084303a 	nor	r2,zero,r2
+ 8012884:	1884703a 	and	r2,r3,r2
+ 8012888:	1007883a 	mov	r3,r2
+ 801288c:	e0bfe817 	ldw	r2,-96(fp)
+ 8012890:	10c0020d 	sth	r3,8(r2)
+                 break;
+ 8012894:	00001206 	br	80128e0 <OSFlagPend+0x568>
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+            case OS_FLAG_WAIT_CLR_ALL:
+            case OS_FLAG_WAIT_CLR_ANY:                     /* Set   ONLY the flags we got              */
+                 pgrp->OSFlagFlags |=  flags_rdy;
+ 8012898:	e0bfe817 	ldw	r2,-96(fp)
+ 801289c:	1080020b 	ldhu	r2,8(r2)
+ 80128a0:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80128a4:	1884b03a 	or	r2,r3,r2
+ 80128a8:	1007883a 	mov	r3,r2
+ 80128ac:	e0bfe817 	ldw	r2,-96(fp)
+ 80128b0:	10c0020d 	sth	r3,8(r2)
+                 break;
+ 80128b4:	00000a06 	br	80128e0 <OSFlagPend+0x568>
+ 80128b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80128bc:	e0bfef15 	stw	r2,-68(fp)
+ 80128c0:	e0bfef17 	ldw	r2,-68(fp)
+ 80128c4:	1001703a 	wrctl	status,r2
+#endif
+            default:
+                 OS_EXIT_CRITICAL();
+                 *perr = OS_ERR_FLAG_WAIT_TYPE;
+ 80128c8:	e0800217 	ldw	r2,8(fp)
+ 80128cc:	00c01bc4 	movi	r3,111
+ 80128d0:	10c00005 	stb	r3,0(r2)
+                 return ((OS_FLAGS)0);
+ 80128d4:	0005883a 	mov	r2,zero
+ 80128d8:	00000806 	br	80128fc <OSFlagPend+0x584>
+        }
+    }
+ 80128dc:	0001883a 	nop
+ 80128e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80128e4:	e0bfee15 	stw	r2,-72(fp)
+ 80128e8:	e0bfee17 	ldw	r2,-72(fp)
+ 80128ec:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;                                   /* Event(s) must have occurred              */
+ 80128f0:	e0800217 	ldw	r2,8(fp)
+ 80128f4:	10000005 	stb	zero,0(r2)
+    return (flags_rdy);
+ 80128f8:	e0bffd0b 	ldhu	r2,-12(fp)
+}
+ 80128fc:	e037883a 	mov	sp,fp
+ 8012900:	dfc00117 	ldw	ra,4(sp)
+ 8012904:	df000017 	ldw	fp,0(sp)
+ 8012908:	dec00204 	addi	sp,sp,8
+ 801290c:	f800283a 	ret
+
+08012910 <OSFlagPendGetFlagsRdy>:
+* Called from: Task ONLY
+*********************************************************************************************************
+*/
+
+OS_FLAGS  OSFlagPendGetFlagsRdy (void)
+{
+ 8012910:	defffb04 	addi	sp,sp,-20
+ 8012914:	df000415 	stw	fp,16(sp)
+ 8012918:	df000404 	addi	fp,sp,16
+    OS_FLAGS      flags;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+ 801291c:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8012920:	0005303a 	rdctl	r2,status
+ 8012924:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8012928:	e0fffc17 	ldw	r3,-16(fp)
+ 801292c:	00bfff84 	movi	r2,-2
+ 8012930:	1884703a 	and	r2,r3,r2
+ 8012934:	1001703a 	wrctl	status,r2
+  return context;
+ 8012938:	e0bffc17 	ldw	r2,-16(fp)
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+ 801293c:	e0bfff15 	stw	r2,-4(fp)
+    flags = OSTCBCur->OSTCBFlagsRdy;
+ 8012940:	d0a05817 	ldw	r2,-32416(gp)
+ 8012944:	10800b0b 	ldhu	r2,44(r2)
+ 8012948:	e0bffe8d 	sth	r2,-6(fp)
+ 801294c:	e0bfff17 	ldw	r2,-4(fp)
+ 8012950:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012954:	e0bffd17 	ldw	r2,-12(fp)
+ 8012958:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (flags);
+ 801295c:	e0bffe8b 	ldhu	r2,-6(fp)
+}
+ 8012960:	e037883a 	mov	sp,fp
+ 8012964:	df000017 	ldw	fp,0(sp)
+ 8012968:	dec00104 	addi	sp,sp,4
+ 801296c:	f800283a 	ret
+
+08012970 <OSFlagPost>:
+*              2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on
+*                 the event flag group.
+*********************************************************************************************************
+*/
+OS_FLAGS  OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr)
+{
+ 8012970:	deffef04 	addi	sp,sp,-68
+ 8012974:	dfc01015 	stw	ra,64(sp)
+ 8012978:	df000f15 	stw	fp,60(sp)
+ 801297c:	df000f04 	addi	fp,sp,60
+ 8012980:	e13ff415 	stw	r4,-48(fp)
+ 8012984:	2805883a 	mov	r2,r5
+ 8012988:	3007883a 	mov	r3,r6
+ 801298c:	e1fff115 	stw	r7,-60(fp)
+ 8012990:	e0bff30d 	sth	r2,-52(fp)
+ 8012994:	1805883a 	mov	r2,r3
+ 8012998:	e0bff205 	stb	r2,-56(fp)
+    BOOLEAN       sched;
+    OS_FLAGS      flags_cur;
+    OS_FLAGS      flags_rdy;
+    BOOLEAN       rdy;
+#if OS_CRITICAL_METHOD == 3                          /* Allocate storage for CPU status register       */
+    OS_CPU_SR     cpu_sr = 0;
+ 801299c:	e03ffd15 	stw	zero,-12(fp)
+    if (pgrp == (OS_FLAG_GRP *)0) {                  /* Validate 'pgrp'                                */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {    /* Make sure we are pointing to an event flag grp */
+ 80129a0:	e0bff417 	ldw	r2,-48(fp)
+ 80129a4:	10800003 	ldbu	r2,0(r2)
+ 80129a8:	10803fcc 	andi	r2,r2,255
+ 80129ac:	10800160 	cmpeqi	r2,r2,5
+ 80129b0:	1000051e 	bne	r2,zero,80129c8 <OSFlagPost+0x58>
+        *perr = OS_ERR_EVENT_TYPE;
+ 80129b4:	e0bff117 	ldw	r2,-60(fp)
+ 80129b8:	00c00044 	movi	r3,1
+ 80129bc:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 80129c0:	0005883a 	mov	r2,zero
+ 80129c4:	0000c006 	br	8012cc8 <OSFlagPost+0x358>
+  NIOS2_READ_STATUS (context);
+ 80129c8:	0005303a 	rdctl	r2,status
+ 80129cc:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80129d0:	e0fffa17 	ldw	r3,-24(fp)
+ 80129d4:	00bfff84 	movi	r2,-2
+ 80129d8:	1884703a 	and	r2,r3,r2
+ 80129dc:	1001703a 	wrctl	status,r2
+  return context;
+ 80129e0:	e0bffa17 	ldw	r2,-24(fp)
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+ 80129e4:	e0bffd15 	stw	r2,-12(fp)
+    switch (opt) {
+ 80129e8:	e0bff203 	ldbu	r2,-56(fp)
+ 80129ec:	10000326 	beq	r2,zero,80129fc <OSFlagPost+0x8c>
+ 80129f0:	10800060 	cmpeqi	r2,r2,1
+ 80129f4:	10000b1e 	bne	r2,zero,8012a24 <OSFlagPost+0xb4>
+ 80129f8:	00001206 	br	8012a44 <OSFlagPost+0xd4>
+        case OS_FLAG_CLR:
+             pgrp->OSFlagFlags &= ~flags;            /* Clear the flags specified in the group         */
+ 80129fc:	e0bff417 	ldw	r2,-48(fp)
+ 8012a00:	1080020b 	ldhu	r2,8(r2)
+ 8012a04:	1007883a 	mov	r3,r2
+ 8012a08:	e0bff30b 	ldhu	r2,-52(fp)
+ 8012a0c:	0084303a 	nor	r2,zero,r2
+ 8012a10:	1884703a 	and	r2,r3,r2
+ 8012a14:	1007883a 	mov	r3,r2
+ 8012a18:	e0bff417 	ldw	r2,-48(fp)
+ 8012a1c:	10c0020d 	sth	r3,8(r2)
+             break;
+ 8012a20:	00001106 	br	8012a68 <OSFlagPost+0xf8>
+
+        case OS_FLAG_SET:
+             pgrp->OSFlagFlags |=  flags;            /* Set   the flags specified in the group         */
+ 8012a24:	e0bff417 	ldw	r2,-48(fp)
+ 8012a28:	1080020b 	ldhu	r2,8(r2)
+ 8012a2c:	e0fff30b 	ldhu	r3,-52(fp)
+ 8012a30:	1884b03a 	or	r2,r3,r2
+ 8012a34:	1007883a 	mov	r3,r2
+ 8012a38:	e0bff417 	ldw	r2,-48(fp)
+ 8012a3c:	10c0020d 	sth	r3,8(r2)
+             break;
+ 8012a40:	00000906 	br	8012a68 <OSFlagPost+0xf8>
+ 8012a44:	e0bffd17 	ldw	r2,-12(fp)
+ 8012a48:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012a4c:	e0bff917 	ldw	r2,-28(fp)
+ 8012a50:	1001703a 	wrctl	status,r2
+
+        default:
+             OS_EXIT_CRITICAL();                     /* INVALID option                                 */
+             *perr = OS_ERR_FLAG_INVALID_OPT;
+ 8012a54:	e0bff117 	ldw	r2,-60(fp)
+ 8012a58:	00c01c44 	movi	r3,113
+ 8012a5c:	10c00005 	stb	r3,0(r2)
+             return ((OS_FLAGS)0);
+ 8012a60:	0005883a 	mov	r2,zero
+ 8012a64:	00009806 	br	8012cc8 <OSFlagPost+0x358>
+    }
+    sched = OS_FALSE;                                /* Indicate that we don't need rescheduling       */
+ 8012a68:	e03ffec5 	stb	zero,-5(fp)
+    pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+ 8012a6c:	e0bff417 	ldw	r2,-48(fp)
+ 8012a70:	10800117 	ldw	r2,4(r2)
+ 8012a74:	e0bfff15 	stw	r2,-4(fp)
+    while (pnode != (OS_FLAG_NODE *)0) {             /* Go through all tasks waiting on event flag(s)  */
+ 8012a78:	00007706 	br	8012c58 <OSFlagPost+0x2e8>
+        switch (pnode->OSFlagNodeWaitType) {
+ 8012a7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8012a80:	10800483 	ldbu	r2,18(r2)
+ 8012a84:	10803fcc 	andi	r2,r2,255
+ 8012a88:	10c00060 	cmpeqi	r3,r2,1
+ 8012a8c:	18004a1e 	bne	r3,zero,8012bb8 <OSFlagPost+0x248>
+ 8012a90:	10c00088 	cmpgei	r3,r2,2
+ 8012a94:	1800021e 	bne	r3,zero,8012aa0 <OSFlagPost+0x130>
+ 8012a98:	10002f26 	beq	r2,zero,8012b58 <OSFlagPost+0x1e8>
+ 8012a9c:	00005b06 	br	8012c0c <OSFlagPost+0x29c>
+ 8012aa0:	10c000a0 	cmpeqi	r3,r2,2
+ 8012aa4:	1800031e 	bne	r3,zero,8012ab4 <OSFlagPost+0x144>
+ 8012aa8:	108000e0 	cmpeqi	r2,r2,3
+ 8012aac:	1000171e 	bne	r2,zero,8012b0c <OSFlagPost+0x19c>
+ 8012ab0:	00005606 	br	8012c0c <OSFlagPost+0x29c>
+            case OS_FLAG_WAIT_SET_ALL:               /* See if all req. flags are set for current node */
+                 flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+ 8012ab4:	e0bff417 	ldw	r2,-48(fp)
+ 8012ab8:	10c0020b 	ldhu	r3,8(r2)
+ 8012abc:	e0bfff17 	ldw	r2,-4(fp)
+ 8012ac0:	1080040b 	ldhu	r2,16(r2)
+ 8012ac4:	1884703a 	and	r2,r3,r2
+ 8012ac8:	e0bffc8d 	sth	r2,-14(fp)
+                 if (flags_rdy == pnode->OSFlagNodeFlags) {
+ 8012acc:	e0bfff17 	ldw	r2,-4(fp)
+ 8012ad0:	1080040b 	ldhu	r2,16(r2)
+ 8012ad4:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8012ad8:	10bfffcc 	andi	r2,r2,65535
+ 8012adc:	1880541e 	bne	r3,r2,8012c30 <OSFlagPost+0x2c0>
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+ 8012ae0:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012ae4:	100b883a 	mov	r5,r2
+ 8012ae8:	e13fff17 	ldw	r4,-4(fp)
+ 8012aec:	8012fb80 	call	8012fb8 <OS_FlagTaskRdy>
+ 8012af0:	e0bffc45 	stb	r2,-15(fp)
+                     if (rdy == OS_TRUE) {
+ 8012af4:	e0bffc43 	ldbu	r2,-15(fp)
+ 8012af8:	10800058 	cmpnei	r2,r2,1
+ 8012afc:	10004c1e 	bne	r2,zero,8012c30 <OSFlagPost+0x2c0>
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+ 8012b00:	00800044 	movi	r2,1
+ 8012b04:	e0bffec5 	stb	r2,-5(fp)
+                     }
+                 }
+                 break;
+ 8012b08:	00004906 	br	8012c30 <OSFlagPost+0x2c0>
+
+            case OS_FLAG_WAIT_SET_ANY:               /* See if any flag set                            */
+                 flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+ 8012b0c:	e0bff417 	ldw	r2,-48(fp)
+ 8012b10:	10c0020b 	ldhu	r3,8(r2)
+ 8012b14:	e0bfff17 	ldw	r2,-4(fp)
+ 8012b18:	1080040b 	ldhu	r2,16(r2)
+ 8012b1c:	1884703a 	and	r2,r3,r2
+ 8012b20:	e0bffc8d 	sth	r2,-14(fp)
+                 if (flags_rdy != (OS_FLAGS)0) {
+ 8012b24:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012b28:	10004326 	beq	r2,zero,8012c38 <OSFlagPost+0x2c8>
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+ 8012b2c:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012b30:	100b883a 	mov	r5,r2
+ 8012b34:	e13fff17 	ldw	r4,-4(fp)
+ 8012b38:	8012fb80 	call	8012fb8 <OS_FlagTaskRdy>
+ 8012b3c:	e0bffc45 	stb	r2,-15(fp)
+                     if (rdy == OS_TRUE) {
+ 8012b40:	e0bffc43 	ldbu	r2,-15(fp)
+ 8012b44:	10800058 	cmpnei	r2,r2,1
+ 8012b48:	10003b1e 	bne	r2,zero,8012c38 <OSFlagPost+0x2c8>
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+ 8012b4c:	00800044 	movi	r2,1
+ 8012b50:	e0bffec5 	stb	r2,-5(fp)
+                     }
+                 }
+                 break;
+ 8012b54:	00003806 	br	8012c38 <OSFlagPost+0x2c8>
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+            case OS_FLAG_WAIT_CLR_ALL:               /* See if all req. flags are set for current node */
+                 flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+ 8012b58:	e0bff417 	ldw	r2,-48(fp)
+ 8012b5c:	1080020b 	ldhu	r2,8(r2)
+ 8012b60:	0084303a 	nor	r2,zero,r2
+ 8012b64:	1007883a 	mov	r3,r2
+ 8012b68:	e0bfff17 	ldw	r2,-4(fp)
+ 8012b6c:	1080040b 	ldhu	r2,16(r2)
+ 8012b70:	1884703a 	and	r2,r3,r2
+ 8012b74:	e0bffc8d 	sth	r2,-14(fp)
+                 if (flags_rdy == pnode->OSFlagNodeFlags) {
+ 8012b78:	e0bfff17 	ldw	r2,-4(fp)
+ 8012b7c:	1080040b 	ldhu	r2,16(r2)
+ 8012b80:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8012b84:	10bfffcc 	andi	r2,r2,65535
+ 8012b88:	18802d1e 	bne	r3,r2,8012c40 <OSFlagPost+0x2d0>
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+ 8012b8c:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012b90:	100b883a 	mov	r5,r2
+ 8012b94:	e13fff17 	ldw	r4,-4(fp)
+ 8012b98:	8012fb80 	call	8012fb8 <OS_FlagTaskRdy>
+ 8012b9c:	e0bffc45 	stb	r2,-15(fp)
+                     if (rdy == OS_TRUE) {
+ 8012ba0:	e0bffc43 	ldbu	r2,-15(fp)
+ 8012ba4:	10800058 	cmpnei	r2,r2,1
+ 8012ba8:	1000251e 	bne	r2,zero,8012c40 <OSFlagPost+0x2d0>
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+ 8012bac:	00800044 	movi	r2,1
+ 8012bb0:	e0bffec5 	stb	r2,-5(fp)
+                     }
+                 }
+                 break;
+ 8012bb4:	00002206 	br	8012c40 <OSFlagPost+0x2d0>
+
+            case OS_FLAG_WAIT_CLR_ANY:               /* See if any flag set                            */
+                 flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+ 8012bb8:	e0bff417 	ldw	r2,-48(fp)
+ 8012bbc:	1080020b 	ldhu	r2,8(r2)
+ 8012bc0:	0084303a 	nor	r2,zero,r2
+ 8012bc4:	1007883a 	mov	r3,r2
+ 8012bc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8012bcc:	1080040b 	ldhu	r2,16(r2)
+ 8012bd0:	1884703a 	and	r2,r3,r2
+ 8012bd4:	e0bffc8d 	sth	r2,-14(fp)
+                 if (flags_rdy != (OS_FLAGS)0) {
+ 8012bd8:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012bdc:	10001a26 	beq	r2,zero,8012c48 <OSFlagPost+0x2d8>
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+ 8012be0:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8012be4:	100b883a 	mov	r5,r2
+ 8012be8:	e13fff17 	ldw	r4,-4(fp)
+ 8012bec:	8012fb80 	call	8012fb8 <OS_FlagTaskRdy>
+ 8012bf0:	e0bffc45 	stb	r2,-15(fp)
+                     if (rdy == OS_TRUE) {
+ 8012bf4:	e0bffc43 	ldbu	r2,-15(fp)
+ 8012bf8:	10800058 	cmpnei	r2,r2,1
+ 8012bfc:	1000121e 	bne	r2,zero,8012c48 <OSFlagPost+0x2d8>
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+ 8012c00:	00800044 	movi	r2,1
+ 8012c04:	e0bffec5 	stb	r2,-5(fp)
+                     }
+                 }
+                 break;
+ 8012c08:	00000f06 	br	8012c48 <OSFlagPost+0x2d8>
+ 8012c0c:	e0bffd17 	ldw	r2,-12(fp)
+ 8012c10:	e0bff815 	stw	r2,-32(fp)
+ 8012c14:	e0bff817 	ldw	r2,-32(fp)
+ 8012c18:	1001703a 	wrctl	status,r2
+#endif
+            default:
+                 OS_EXIT_CRITICAL();
+                 *perr = OS_ERR_FLAG_WAIT_TYPE;
+ 8012c1c:	e0bff117 	ldw	r2,-60(fp)
+ 8012c20:	00c01bc4 	movi	r3,111
+ 8012c24:	10c00005 	stb	r3,0(r2)
+                 return ((OS_FLAGS)0);
+ 8012c28:	0005883a 	mov	r2,zero
+ 8012c2c:	00002606 	br	8012cc8 <OSFlagPost+0x358>
+                 break;
+ 8012c30:	0001883a 	nop
+ 8012c34:	00000506 	br	8012c4c <OSFlagPost+0x2dc>
+                 break;
+ 8012c38:	0001883a 	nop
+ 8012c3c:	00000306 	br	8012c4c <OSFlagPost+0x2dc>
+                 break;
+ 8012c40:	0001883a 	nop
+ 8012c44:	00000106 	br	8012c4c <OSFlagPost+0x2dc>
+                 break;
+ 8012c48:	0001883a 	nop
+        }
+        pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */
+ 8012c4c:	e0bfff17 	ldw	r2,-4(fp)
+ 8012c50:	10800017 	ldw	r2,0(r2)
+ 8012c54:	e0bfff15 	stw	r2,-4(fp)
+    while (pnode != (OS_FLAG_NODE *)0) {             /* Go through all tasks waiting on event flag(s)  */
+ 8012c58:	e0bfff17 	ldw	r2,-4(fp)
+ 8012c5c:	103f871e 	bne	r2,zero,8012a7c <OSFlagPost+0x10c>
+ 8012c60:	e0bffd17 	ldw	r2,-12(fp)
+ 8012c64:	e0bff715 	stw	r2,-36(fp)
+ 8012c68:	e0bff717 	ldw	r2,-36(fp)
+ 8012c6c:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    if (sched == OS_TRUE) {
+ 8012c70:	e0bffec3 	ldbu	r2,-5(fp)
+ 8012c74:	10800058 	cmpnei	r2,r2,1
+ 8012c78:	1000011e 	bne	r2,zero,8012c80 <OSFlagPost+0x310>
+        OS_Sched();
+ 8012c7c:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 8012c80:	0005303a 	rdctl	r2,status
+ 8012c84:	e0bff515 	stw	r2,-44(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8012c88:	e0fff517 	ldw	r3,-44(fp)
+ 8012c8c:	00bfff84 	movi	r2,-2
+ 8012c90:	1884703a 	and	r2,r3,r2
+ 8012c94:	1001703a 	wrctl	status,r2
+  return context;
+ 8012c98:	e0bff517 	ldw	r2,-44(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8012c9c:	e0bffd15 	stw	r2,-12(fp)
+    flags_cur = pgrp->OSFlagFlags;
+ 8012ca0:	e0bff417 	ldw	r2,-48(fp)
+ 8012ca4:	1080020b 	ldhu	r2,8(r2)
+ 8012ca8:	e0bffb8d 	sth	r2,-18(fp)
+ 8012cac:	e0bffd17 	ldw	r2,-12(fp)
+ 8012cb0:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012cb4:	e0bff617 	ldw	r2,-40(fp)
+ 8012cb8:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr     = OS_ERR_NONE;
+ 8012cbc:	e0bff117 	ldw	r2,-60(fp)
+ 8012cc0:	10000005 	stb	zero,0(r2)
+    return (flags_cur);
+ 8012cc4:	e0bffb8b 	ldhu	r2,-18(fp)
+}
+ 8012cc8:	e037883a 	mov	sp,fp
+ 8012ccc:	dfc00117 	ldw	ra,4(sp)
+ 8012cd0:	df000017 	ldw	fp,0(sp)
+ 8012cd4:	dec00204 	addi	sp,sp,8
+ 8012cd8:	f800283a 	ret
+
+08012cdc <OSFlagQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_QUERY_EN > 0
+OS_FLAGS  OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr)
+{
+ 8012cdc:	defff904 	addi	sp,sp,-28
+ 8012ce0:	df000615 	stw	fp,24(sp)
+ 8012ce4:	df000604 	addi	fp,sp,24
+ 8012ce8:	e13ffb15 	stw	r4,-20(fp)
+ 8012cec:	e17ffa15 	stw	r5,-24(fp)
+    OS_FLAGS   flags;
+#if OS_CRITICAL_METHOD == 3                       /* Allocate storage for CPU status register          */
+    OS_CPU_SR  cpu_sr = 0;
+ 8012cf0:	e03fff15 	stw	zero,-4(fp)
+    if (pgrp == (OS_FLAG_GRP *)0) {               /* Validate 'pgrp'                                   */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type                         */
+ 8012cf4:	e0bffb17 	ldw	r2,-20(fp)
+ 8012cf8:	10800003 	ldbu	r2,0(r2)
+ 8012cfc:	10803fcc 	andi	r2,r2,255
+ 8012d00:	10800160 	cmpeqi	r2,r2,5
+ 8012d04:	1000051e 	bne	r2,zero,8012d1c <OSFlagQuery+0x40>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8012d08:	e0bffa17 	ldw	r2,-24(fp)
+ 8012d0c:	00c00044 	movi	r3,1
+ 8012d10:	10c00005 	stb	r3,0(r2)
+        return ((OS_FLAGS)0);
+ 8012d14:	0005883a 	mov	r2,zero
+ 8012d18:	00001206 	br	8012d64 <OSFlagQuery+0x88>
+  NIOS2_READ_STATUS (context);
+ 8012d1c:	0005303a 	rdctl	r2,status
+ 8012d20:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8012d24:	e0fffc17 	ldw	r3,-16(fp)
+ 8012d28:	00bfff84 	movi	r2,-2
+ 8012d2c:	1884703a 	and	r2,r3,r2
+ 8012d30:	1001703a 	wrctl	status,r2
+  return context;
+ 8012d34:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8012d38:	e0bfff15 	stw	r2,-4(fp)
+    flags = pgrp->OSFlagFlags;
+ 8012d3c:	e0bffb17 	ldw	r2,-20(fp)
+ 8012d40:	1080020b 	ldhu	r2,8(r2)
+ 8012d44:	e0bffe8d 	sth	r2,-6(fp)
+ 8012d48:	e0bfff17 	ldw	r2,-4(fp)
+ 8012d4c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8012d50:	e0bffd17 	ldw	r2,-12(fp)
+ 8012d54:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8012d58:	e0bffa17 	ldw	r2,-24(fp)
+ 8012d5c:	10000005 	stb	zero,0(r2)
+    return (flags);                               /* Return the current value of the event flags       */
+ 8012d60:	e0bffe8b 	ldhu	r2,-6(fp)
+}
+ 8012d64:	e037883a 	mov	sp,fp
+ 8012d68:	df000017 	ldw	fp,0(sp)
+ 8012d6c:	dec00104 	addi	sp,sp,4
+ 8012d70:	f800283a 	ret
+
+08012d74 <OS_FlagBlock>:
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+static  void  OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout)
+{
+ 8012d74:	defff804 	addi	sp,sp,-32
+ 8012d78:	df000715 	stw	fp,28(sp)
+ 8012d7c:	df000704 	addi	fp,sp,28
+ 8012d80:	e13ffd15 	stw	r4,-12(fp)
+ 8012d84:	e17ffc15 	stw	r5,-16(fp)
+ 8012d88:	3007883a 	mov	r3,r6
+ 8012d8c:	3809883a 	mov	r4,r7
+ 8012d90:	e0800117 	ldw	r2,4(fp)
+ 8012d94:	e0fffb0d 	sth	r3,-20(fp)
+ 8012d98:	2007883a 	mov	r3,r4
+ 8012d9c:	e0fffa05 	stb	r3,-24(fp)
+ 8012da0:	e0bff90d 	sth	r2,-28(fp)
+    OS_FLAG_NODE  *pnode_next;
+    INT8U          y;
+
+
+    OSTCBCur->OSTCBStat      |= OS_STAT_FLAG;
+ 8012da4:	d0a05817 	ldw	r2,-32416(gp)
+ 8012da8:	10c00c03 	ldbu	r3,48(r2)
+ 8012dac:	d0a05817 	ldw	r2,-32416(gp)
+ 8012db0:	18c00814 	ori	r3,r3,32
+ 8012db4:	10c00c05 	stb	r3,48(r2)
+    OSTCBCur->OSTCBStatPend   = OS_STAT_PEND_OK;
+ 8012db8:	d0a05817 	ldw	r2,-32416(gp)
+ 8012dbc:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBDly        = timeout;              /* Store timeout in task's TCB                   */
+ 8012dc0:	d0a05817 	ldw	r2,-32416(gp)
+ 8012dc4:	e0fff90b 	ldhu	r3,-28(fp)
+ 8012dc8:	10c00b8d 	sth	r3,46(r2)
+#if OS_TASK_DEL_EN > 0
+    OSTCBCur->OSTCBFlagNode   = pnode;                /* TCB to link to node                           */
+ 8012dcc:	d0a05817 	ldw	r2,-32416(gp)
+ 8012dd0:	e0fffc17 	ldw	r3,-16(fp)
+ 8012dd4:	10c00a15 	stw	r3,40(r2)
+#endif
+    pnode->OSFlagNodeFlags    = flags;                /* Save the flags that we need to wait for       */
+ 8012dd8:	e0bffc17 	ldw	r2,-16(fp)
+ 8012ddc:	e0fffb0b 	ldhu	r3,-20(fp)
+ 8012de0:	10c0040d 	sth	r3,16(r2)
+    pnode->OSFlagNodeWaitType = wait_type;            /* Save the type of wait we are doing            */
+ 8012de4:	e0bffc17 	ldw	r2,-16(fp)
+ 8012de8:	e0fffa03 	ldbu	r3,-24(fp)
+ 8012dec:	10c00485 	stb	r3,18(r2)
+    pnode->OSFlagNodeTCB      = (void *)OSTCBCur;     /* Link to task's TCB                            */
+ 8012df0:	d0e05817 	ldw	r3,-32416(gp)
+ 8012df4:	e0bffc17 	ldw	r2,-16(fp)
+ 8012df8:	10c00215 	stw	r3,8(r2)
+    pnode->OSFlagNodeNext     = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */
+ 8012dfc:	e0bffd17 	ldw	r2,-12(fp)
+ 8012e00:	10c00117 	ldw	r3,4(r2)
+ 8012e04:	e0bffc17 	ldw	r2,-16(fp)
+ 8012e08:	10c00015 	stw	r3,0(r2)
+    pnode->OSFlagNodePrev     = (void *)0;
+ 8012e0c:	e0bffc17 	ldw	r2,-16(fp)
+ 8012e10:	10000115 	stw	zero,4(r2)
+    pnode->OSFlagNodeFlagGrp  = (void *)pgrp;         /* Link to Event Flag Group                      */
+ 8012e14:	e0bffc17 	ldw	r2,-16(fp)
+ 8012e18:	e0fffd17 	ldw	r3,-12(fp)
+ 8012e1c:	10c00315 	stw	r3,12(r2)
+    pnode_next                = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+ 8012e20:	e0bffd17 	ldw	r2,-12(fp)
+ 8012e24:	10800117 	ldw	r2,4(r2)
+ 8012e28:	e0bfff15 	stw	r2,-4(fp)
+    if (pnode_next != (void *)0) {                    /* Is this the first NODE to insert?             */
+ 8012e2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8012e30:	10000326 	beq	r2,zero,8012e40 <OS_FlagBlock+0xcc>
+        pnode_next->OSFlagNodePrev = pnode;           /* No, link in doubly linked list                */
+ 8012e34:	e0bfff17 	ldw	r2,-4(fp)
+ 8012e38:	e0fffc17 	ldw	r3,-16(fp)
+ 8012e3c:	10c00115 	stw	r3,4(r2)
+    }
+    pgrp->OSFlagWaitList = (void *)pnode;
+ 8012e40:	e0bffd17 	ldw	r2,-12(fp)
+ 8012e44:	e0fffc17 	ldw	r3,-16(fp)
+ 8012e48:	10c00115 	stw	r3,4(r2)
+
+    y            =  OSTCBCur->OSTCBY;                 /* Suspend current task until flag(s) received   */
+ 8012e4c:	d0a05817 	ldw	r2,-32416(gp)
+ 8012e50:	10800d03 	ldbu	r2,52(r2)
+ 8012e54:	e0bffec5 	stb	r2,-5(fp)
+    OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX;
+ 8012e58:	e0fffec3 	ldbu	r3,-5(fp)
+ 8012e5c:	d0a05544 	addi	r2,gp,-32427
+ 8012e60:	1885883a 	add	r2,r3,r2
+ 8012e64:	10800003 	ldbu	r2,0(r2)
+ 8012e68:	1007883a 	mov	r3,r2
+ 8012e6c:	d0a05817 	ldw	r2,-32416(gp)
+ 8012e70:	10800d43 	ldbu	r2,53(r2)
+ 8012e74:	0084303a 	nor	r2,zero,r2
+ 8012e78:	1884703a 	and	r2,r3,r2
+ 8012e7c:	e0fffec3 	ldbu	r3,-5(fp)
+ 8012e80:	1009883a 	mov	r4,r2
+ 8012e84:	d0a05544 	addi	r2,gp,-32427
+ 8012e88:	1885883a 	add	r2,r3,r2
+ 8012e8c:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[y] == 0x00) {
+ 8012e90:	e0fffec3 	ldbu	r3,-5(fp)
+ 8012e94:	d0a05544 	addi	r2,gp,-32427
+ 8012e98:	1885883a 	add	r2,r3,r2
+ 8012e9c:	10800003 	ldbu	r2,0(r2)
+ 8012ea0:	10803fcc 	andi	r2,r2,255
+ 8012ea4:	1000071e 	bne	r2,zero,8012ec4 <OS_FlagBlock+0x150>
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;
+ 8012ea8:	d0a05817 	ldw	r2,-32416(gp)
+ 8012eac:	10800d83 	ldbu	r2,54(r2)
+ 8012eb0:	0084303a 	nor	r2,zero,r2
+ 8012eb4:	1007883a 	mov	r3,r2
+ 8012eb8:	d0a05503 	ldbu	r2,-32428(gp)
+ 8012ebc:	1884703a 	and	r2,r3,r2
+ 8012ec0:	d0a05505 	stb	r2,-32428(gp)
+    }
+}
+ 8012ec4:	0001883a 	nop
+ 8012ec8:	e037883a 	mov	sp,fp
+ 8012ecc:	df000017 	ldw	fp,0(sp)
+ 8012ed0:	dec00104 	addi	sp,sp,4
+ 8012ed4:	f800283a 	ret
+
+08012ed8 <OS_FlagInit>:
+* WARNING    : You MUST NOT call this function from your code.  This is an INTERNAL function to uC/OS-II.
+*********************************************************************************************************
+*/
+
+void  OS_FlagInit (void)
+{
+ 8012ed8:	defffb04 	addi	sp,sp,-20
+ 8012edc:	dfc00415 	stw	ra,16(sp)
+ 8012ee0:	df000315 	stw	fp,12(sp)
+ 8012ee4:	df000304 	addi	fp,sp,12
+    INT16U       i;
+    OS_FLAG_GRP *pgrp1;
+    OS_FLAG_GRP *pgrp2;
+
+
+    OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl));           /* Clear the flag group table      */
+ 8012ee8:	0140dc04 	movi	r5,880
+ 8012eec:	010201b4 	movhi	r4,2054
+ 8012ef0:	212b8b04 	addi	r4,r4,-20948
+ 8012ef4:	80115b00 	call	80115b0 <OS_MemClr>
+    pgrp1 = &OSFlagTbl[0];
+ 8012ef8:	008201b4 	movhi	r2,2054
+ 8012efc:	10ab8b04 	addi	r2,r2,-20948
+ 8012f00:	e0bffe15 	stw	r2,-8(fp)
+    pgrp2 = &OSFlagTbl[1];
+ 8012f04:	008201b4 	movhi	r2,2054
+ 8012f08:	10ab9604 	addi	r2,r2,-20904
+ 8012f0c:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_FLAGS - 1); i++) {                      /* Init. list of free EVENT FLAGS  */
+ 8012f10:	e03fff8d 	sth	zero,-2(fp)
+ 8012f14:	00001306 	br	8012f64 <OS_FlagInit+0x8c>
+        pgrp1->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+ 8012f18:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f1c:	10000005 	stb	zero,0(r2)
+        pgrp1->OSFlagWaitList = (void *)pgrp2;
+ 8012f20:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f24:	e0fffd17 	ldw	r3,-12(fp)
+ 8012f28:	10c00115 	stw	r3,4(r2)
+#if OS_FLAG_NAME_SIZE > 1
+        pgrp1->OSFlagName[0]  = '?';                                /* Unknown name                    */
+ 8012f2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f30:	00c00fc4 	movi	r3,63
+ 8012f34:	10c00285 	stb	r3,10(r2)
+        pgrp1->OSFlagName[1]  = OS_ASCII_NUL;
+ 8012f38:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f3c:	100002c5 	stb	zero,11(r2)
+#endif
+        pgrp1++;
+ 8012f40:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f44:	10800b04 	addi	r2,r2,44
+ 8012f48:	e0bffe15 	stw	r2,-8(fp)
+        pgrp2++;
+ 8012f4c:	e0bffd17 	ldw	r2,-12(fp)
+ 8012f50:	10800b04 	addi	r2,r2,44
+ 8012f54:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_FLAGS - 1); i++) {                      /* Init. list of free EVENT FLAGS  */
+ 8012f58:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8012f5c:	10800044 	addi	r2,r2,1
+ 8012f60:	e0bfff8d 	sth	r2,-2(fp)
+ 8012f64:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8012f68:	108004f0 	cmpltui	r2,r2,19
+ 8012f6c:	103fea1e 	bne	r2,zero,8012f18 <OS_FlagInit+0x40>
+    }
+    pgrp1->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+ 8012f70:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f74:	10000005 	stb	zero,0(r2)
+    pgrp1->OSFlagWaitList = (void *)0;
+ 8012f78:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f7c:	10000115 	stw	zero,4(r2)
+#if OS_FLAG_NAME_SIZE > 1
+    pgrp1->OSFlagName[0]  = '?';                                    /* Unknown name                    */
+ 8012f80:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f84:	00c00fc4 	movi	r3,63
+ 8012f88:	10c00285 	stb	r3,10(r2)
+    pgrp1->OSFlagName[1]  = OS_ASCII_NUL;
+ 8012f8c:	e0bffe17 	ldw	r2,-8(fp)
+ 8012f90:	100002c5 	stb	zero,11(r2)
+#endif
+    OSFlagFreeList        = &OSFlagTbl[0];
+ 8012f94:	008201b4 	movhi	r2,2054
+ 8012f98:	10ab8b04 	addi	r2,r2,-20948
+ 8012f9c:	d0a05a15 	stw	r2,-32408(gp)
+#endif
+}
+ 8012fa0:	0001883a 	nop
+ 8012fa4:	e037883a 	mov	sp,fp
+ 8012fa8:	dfc00117 	ldw	ra,4(sp)
+ 8012fac:	df000017 	ldw	fp,0(sp)
+ 8012fb0:	dec00204 	addi	sp,sp,8
+ 8012fb4:	f800283a 	ret
+
+08012fb8 <OS_FlagTaskRdy>:
+*              2) This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+static  BOOLEAN  OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy)
+{
+ 8012fb8:	defffa04 	addi	sp,sp,-24
+ 8012fbc:	dfc00515 	stw	ra,20(sp)
+ 8012fc0:	df000415 	stw	fp,16(sp)
+ 8012fc4:	df000404 	addi	fp,sp,16
+ 8012fc8:	e13ffd15 	stw	r4,-12(fp)
+ 8012fcc:	2805883a 	mov	r2,r5
+ 8012fd0:	e0bffc0d 	sth	r2,-16(fp)
+    OS_TCB   *ptcb;
+    BOOLEAN   sched;
+
+
+    ptcb                 = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task             */
+ 8012fd4:	e0bffd17 	ldw	r2,-12(fp)
+ 8012fd8:	10800217 	ldw	r2,8(r2)
+ 8012fdc:	e0bffe15 	stw	r2,-8(fp)
+    ptcb->OSTCBDly       = 0;
+ 8012fe0:	e0bffe17 	ldw	r2,-8(fp)
+ 8012fe4:	10000b8d 	sth	zero,46(r2)
+    ptcb->OSTCBFlagsRdy  = flags_rdy;
+ 8012fe8:	e0bffe17 	ldw	r2,-8(fp)
+ 8012fec:	e0fffc0b 	ldhu	r3,-16(fp)
+ 8012ff0:	10c00b0d 	sth	r3,44(r2)
+    ptcb->OSTCBStat     &= ~(INT8U)OS_STAT_FLAG;
+ 8012ff4:	e0bffe17 	ldw	r2,-8(fp)
+ 8012ff8:	10c00c03 	ldbu	r3,48(r2)
+ 8012ffc:	00bff7c4 	movi	r2,-33
+ 8013000:	1884703a 	and	r2,r3,r2
+ 8013004:	1007883a 	mov	r3,r2
+ 8013008:	e0bffe17 	ldw	r2,-8(fp)
+ 801300c:	10c00c05 	stb	r3,48(r2)
+    ptcb->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 8013010:	e0bffe17 	ldw	r2,-8(fp)
+ 8013014:	10000c45 	stb	zero,49(r2)
+    if (ptcb->OSTCBStat == OS_STAT_RDY) {                  /* Task now ready?                          */
+ 8013018:	e0bffe17 	ldw	r2,-8(fp)
+ 801301c:	10800c03 	ldbu	r2,48(r2)
+ 8013020:	10803fcc 	andi	r2,r2,255
+ 8013024:	1000181e 	bne	r2,zero,8013088 <OS_FlagTaskRdy+0xd0>
+        OSRdyGrp               |= ptcb->OSTCBBitY;         /* Put task into ready list                 */
+ 8013028:	e0bffe17 	ldw	r2,-8(fp)
+ 801302c:	10c00d83 	ldbu	r3,54(r2)
+ 8013030:	d0a05503 	ldbu	r2,-32428(gp)
+ 8013034:	1884b03a 	or	r2,r3,r2
+ 8013038:	d0a05505 	stb	r2,-32428(gp)
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 801303c:	e0bffe17 	ldw	r2,-8(fp)
+ 8013040:	10800d03 	ldbu	r2,52(r2)
+ 8013044:	10c03fcc 	andi	r3,r2,255
+ 8013048:	d0a05544 	addi	r2,gp,-32427
+ 801304c:	1885883a 	add	r2,r3,r2
+ 8013050:	11000003 	ldbu	r4,0(r2)
+ 8013054:	e0bffe17 	ldw	r2,-8(fp)
+ 8013058:	10800d43 	ldbu	r2,53(r2)
+ 801305c:	e0fffe17 	ldw	r3,-8(fp)
+ 8013060:	18c00d03 	ldbu	r3,52(r3)
+ 8013064:	18c03fcc 	andi	r3,r3,255
+ 8013068:	2084b03a 	or	r2,r4,r2
+ 801306c:	1009883a 	mov	r4,r2
+ 8013070:	d0a05544 	addi	r2,gp,-32427
+ 8013074:	1885883a 	add	r2,r3,r2
+ 8013078:	11000005 	stb	r4,0(r2)
+        sched                   = OS_TRUE;
+ 801307c:	00800044 	movi	r2,1
+ 8013080:	e0bfffc5 	stb	r2,-1(fp)
+ 8013084:	00000106 	br	801308c <OS_FlagTaskRdy+0xd4>
+    } else {
+        sched                   = OS_FALSE;
+ 8013088:	e03fffc5 	stb	zero,-1(fp)
+    }
+    OS_FlagUnlink(pnode);
+ 801308c:	e13ffd17 	ldw	r4,-12(fp)
+ 8013090:	80130ac0 	call	80130ac <OS_FlagUnlink>
+    return (sched);
+ 8013094:	e0bfffc3 	ldbu	r2,-1(fp)
+}
+ 8013098:	e037883a 	mov	sp,fp
+ 801309c:	dfc00117 	ldw	ra,4(sp)
+ 80130a0:	df000017 	ldw	fp,0(sp)
+ 80130a4:	dec00204 	addi	sp,sp,8
+ 80130a8:	f800283a 	ret
+
+080130ac <OS_FlagUnlink>:
+*              2) This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_FlagUnlink (OS_FLAG_NODE *pnode)
+{
+ 80130ac:	defffa04 	addi	sp,sp,-24
+ 80130b0:	df000515 	stw	fp,20(sp)
+ 80130b4:	df000504 	addi	fp,sp,20
+ 80130b8:	e13ffb15 	stw	r4,-20(fp)
+    OS_FLAG_GRP  *pgrp;
+    OS_FLAG_NODE *pnode_prev;
+    OS_FLAG_NODE *pnode_next;
+
+
+    pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev;
+ 80130bc:	e0bffb17 	ldw	r2,-20(fp)
+ 80130c0:	10800117 	ldw	r2,4(r2)
+ 80130c4:	e0bfff15 	stw	r2,-4(fp)
+    pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext;
+ 80130c8:	e0bffb17 	ldw	r2,-20(fp)
+ 80130cc:	10800017 	ldw	r2,0(r2)
+ 80130d0:	e0bffe15 	stw	r2,-8(fp)
+    if (pnode_prev == (OS_FLAG_NODE *)0) {                      /* Is it first node in wait list?      */
+ 80130d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80130d8:	10000b1e 	bne	r2,zero,8013108 <OS_FlagUnlink+0x5c>
+        pgrp                 = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp;
+ 80130dc:	e0bffb17 	ldw	r2,-20(fp)
+ 80130e0:	10800317 	ldw	r2,12(r2)
+ 80130e4:	e0bffd15 	stw	r2,-12(fp)
+        pgrp->OSFlagWaitList = (void *)pnode_next;              /*      Update list for new 1st node   */
+ 80130e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80130ec:	e0fffe17 	ldw	r3,-8(fp)
+ 80130f0:	10c00115 	stw	r3,4(r2)
+        if (pnode_next != (OS_FLAG_NODE *)0) {
+ 80130f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80130f8:	10000b26 	beq	r2,zero,8013128 <OS_FlagUnlink+0x7c>
+            pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0;     /*      Link new 1st node PREV to NULL */
+ 80130fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8013100:	10000115 	stw	zero,4(r2)
+ 8013104:	00000806 	br	8013128 <OS_FlagUnlink+0x7c>
+        }
+    } else {                                                    /* No,  A node somewhere in the list   */
+        pnode_prev->OSFlagNodeNext = pnode_next;                /*      Link around the node to unlink */
+ 8013108:	e0bfff17 	ldw	r2,-4(fp)
+ 801310c:	e0fffe17 	ldw	r3,-8(fp)
+ 8013110:	10c00015 	stw	r3,0(r2)
+        if (pnode_next != (OS_FLAG_NODE *)0) {                  /*      Was this the LAST node?        */
+ 8013114:	e0bffe17 	ldw	r2,-8(fp)
+ 8013118:	10000326 	beq	r2,zero,8013128 <OS_FlagUnlink+0x7c>
+            pnode_next->OSFlagNodePrev = pnode_prev;            /*      No, Link around current node   */
+ 801311c:	e0bffe17 	ldw	r2,-8(fp)
+ 8013120:	e0ffff17 	ldw	r3,-4(fp)
+ 8013124:	10c00115 	stw	r3,4(r2)
+        }
+    }
+#if OS_TASK_DEL_EN > 0
+    ptcb                = (OS_TCB *)pnode->OSFlagNodeTCB;
+ 8013128:	e0bffb17 	ldw	r2,-20(fp)
+ 801312c:	10800217 	ldw	r2,8(r2)
+ 8013130:	e0bffc15 	stw	r2,-16(fp)
+    ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0;
+ 8013134:	e0bffc17 	ldw	r2,-16(fp)
+ 8013138:	10000a15 	stw	zero,40(r2)
+#endif
+}
+ 801313c:	0001883a 	nop
+ 8013140:	e037883a 	mov	sp,fp
+ 8013144:	df000017 	ldw	fp,0(sp)
+ 8013148:	dec00104 	addi	sp,sp,4
+ 801314c:	f800283a 	ret
+
+08013150 <OSMemCreate>:
+*                              free partition is available.
+*********************************************************************************************************
+*/
+
+OS_MEM  *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr)
+{
+ 8013150:	defff404 	addi	sp,sp,-48
+ 8013154:	df000b15 	stw	fp,44(sp)
+ 8013158:	df000b04 	addi	fp,sp,44
+ 801315c:	e13ff815 	stw	r4,-32(fp)
+ 8013160:	e17ff715 	stw	r5,-36(fp)
+ 8013164:	e1bff615 	stw	r6,-40(fp)
+ 8013168:	e1fff515 	stw	r7,-44(fp)
+    OS_MEM    *pmem;
+    INT8U     *pblk;
+    void     **plink;
+    INT32U     i;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 801316c:	e03ffc15 	stw	zero,-16(fp)
+  NIOS2_READ_STATUS (context);
+ 8013170:	0005303a 	rdctl	r2,status
+ 8013174:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8013178:	e0fffa17 	ldw	r3,-24(fp)
+ 801317c:	00bfff84 	movi	r2,-2
+ 8013180:	1884703a 	and	r2,r3,r2
+ 8013184:	1001703a 	wrctl	status,r2
+  return context;
+ 8013188:	e0bffa17 	ldw	r2,-24(fp)
+    if (blksize < sizeof(void *)) {                   /* Must contain space for at least a pointer     */
+        *perr = OS_ERR_MEM_INVALID_SIZE;
+        return ((OS_MEM *)0);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 801318c:	e0bffc15 	stw	r2,-16(fp)
+    pmem = OSMemFreeList;                             /* Get next free memory partition                */
+ 8013190:	d0a05217 	ldw	r2,-32440(gp)
+ 8013194:	e0bffb15 	stw	r2,-20(fp)
+    if (OSMemFreeList != (OS_MEM *)0) {               /* See if pool of free partitions was empty      */
+ 8013198:	d0a05217 	ldw	r2,-32440(gp)
+ 801319c:	10000326 	beq	r2,zero,80131ac <OSMemCreate+0x5c>
+        OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList;
+ 80131a0:	d0a05217 	ldw	r2,-32440(gp)
+ 80131a4:	10800117 	ldw	r2,4(r2)
+ 80131a8:	d0a05215 	stw	r2,-32440(gp)
+ 80131ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80131b0:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80131b4:	e0bff917 	ldw	r2,-28(fp)
+ 80131b8:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    if (pmem == (OS_MEM *)0) {                        /* See if we have a memory partition             */
+ 80131bc:	e0bffb17 	ldw	r2,-20(fp)
+ 80131c0:	1000051e 	bne	r2,zero,80131d8 <OSMemCreate+0x88>
+        *perr = OS_ERR_MEM_INVALID_PART;
+ 80131c4:	e0bff517 	ldw	r2,-44(fp)
+ 80131c8:	00c01684 	movi	r3,90
+ 80131cc:	10c00005 	stb	r3,0(r2)
+        return ((OS_MEM *)0);
+ 80131d0:	0005883a 	mov	r2,zero
+ 80131d4:	00002c06 	br	8013288 <OSMemCreate+0x138>
+    }
+    plink = (void **)addr;                            /* Create linked list of free memory blocks      */
+ 80131d8:	e0bff817 	ldw	r2,-32(fp)
+ 80131dc:	e0bffe15 	stw	r2,-8(fp)
+    pblk  = (INT8U *)((INT32U)addr + blksize);
+ 80131e0:	e0fff817 	ldw	r3,-32(fp)
+ 80131e4:	e0bff617 	ldw	r2,-40(fp)
+ 80131e8:	1885883a 	add	r2,r3,r2
+ 80131ec:	e0bfff15 	stw	r2,-4(fp)
+    for (i = 0; i < (nblks - 1); i++) {
+ 80131f0:	e03ffd15 	stw	zero,-12(fp)
+ 80131f4:	00000c06 	br	8013228 <OSMemCreate+0xd8>
+       *plink = (void *)pblk;                         /* Save pointer to NEXT block in CURRENT block   */
+ 80131f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80131fc:	e0ffff17 	ldw	r3,-4(fp)
+ 8013200:	10c00015 	stw	r3,0(r2)
+        plink = (void **)pblk;                        /* Position to  NEXT      block                  */
+ 8013204:	e0bfff17 	ldw	r2,-4(fp)
+ 8013208:	e0bffe15 	stw	r2,-8(fp)
+        pblk  = (INT8U *)((INT32U)pblk + blksize);    /* Point to the FOLLOWING block                  */
+ 801320c:	e0ffff17 	ldw	r3,-4(fp)
+ 8013210:	e0bff617 	ldw	r2,-40(fp)
+ 8013214:	1885883a 	add	r2,r3,r2
+ 8013218:	e0bfff15 	stw	r2,-4(fp)
+    for (i = 0; i < (nblks - 1); i++) {
+ 801321c:	e0bffd17 	ldw	r2,-12(fp)
+ 8013220:	10800044 	addi	r2,r2,1
+ 8013224:	e0bffd15 	stw	r2,-12(fp)
+ 8013228:	e0bff717 	ldw	r2,-36(fp)
+ 801322c:	10bfffc4 	addi	r2,r2,-1
+ 8013230:	e0fffd17 	ldw	r3,-12(fp)
+ 8013234:	18bff036 	bltu	r3,r2,80131f8 <OSMemCreate+0xa8>
+    }
+    *plink              = (void *)0;                  /* Last memory block points to NULL              */
+ 8013238:	e0bffe17 	ldw	r2,-8(fp)
+ 801323c:	10000015 	stw	zero,0(r2)
+    pmem->OSMemAddr     = addr;                       /* Store start address of memory partition       */
+ 8013240:	e0bffb17 	ldw	r2,-20(fp)
+ 8013244:	e0fff817 	ldw	r3,-32(fp)
+ 8013248:	10c00015 	stw	r3,0(r2)
+    pmem->OSMemFreeList = addr;                       /* Initialize pointer to pool of free blocks     */
+ 801324c:	e0bffb17 	ldw	r2,-20(fp)
+ 8013250:	e0fff817 	ldw	r3,-32(fp)
+ 8013254:	10c00115 	stw	r3,4(r2)
+    pmem->OSMemNFree    = nblks;                      /* Store number of free blocks in MCB            */
+ 8013258:	e0bffb17 	ldw	r2,-20(fp)
+ 801325c:	e0fff717 	ldw	r3,-36(fp)
+ 8013260:	10c00415 	stw	r3,16(r2)
+    pmem->OSMemNBlks    = nblks;
+ 8013264:	e0bffb17 	ldw	r2,-20(fp)
+ 8013268:	e0fff717 	ldw	r3,-36(fp)
+ 801326c:	10c00315 	stw	r3,12(r2)
+    pmem->OSMemBlkSize  = blksize;                    /* Store block size of each memory blocks        */
+ 8013270:	e0bffb17 	ldw	r2,-20(fp)
+ 8013274:	e0fff617 	ldw	r3,-40(fp)
+ 8013278:	10c00215 	stw	r3,8(r2)
+    *perr               = OS_ERR_NONE;
+ 801327c:	e0bff517 	ldw	r2,-44(fp)
+ 8013280:	10000005 	stb	zero,0(r2)
+    return (pmem);
+ 8013284:	e0bffb17 	ldw	r2,-20(fp)
+}
+ 8013288:	e037883a 	mov	sp,fp
+ 801328c:	df000017 	ldw	fp,0(sp)
+ 8013290:	dec00104 	addi	sp,sp,4
+ 8013294:	f800283a 	ret
+
+08013298 <OSMemGet>:
+*               A pointer to NULL if an error is detected
+*********************************************************************************************************
+*/
+
+void  *OSMemGet (OS_MEM *pmem, INT8U *perr)
+{
+ 8013298:	defff804 	addi	sp,sp,-32
+ 801329c:	df000715 	stw	fp,28(sp)
+ 80132a0:	df000704 	addi	fp,sp,28
+ 80132a4:	e13ffa15 	stw	r4,-24(fp)
+ 80132a8:	e17ff915 	stw	r5,-28(fp)
+    void      *pblk;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 80132ac:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80132b0:	0005303a 	rdctl	r2,status
+ 80132b4:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80132b8:	e0fffd17 	ldw	r3,-12(fp)
+ 80132bc:	00bfff84 	movi	r2,-2
+ 80132c0:	1884703a 	and	r2,r3,r2
+ 80132c4:	1001703a 	wrctl	status,r2
+  return context;
+ 80132c8:	e0bffd17 	ldw	r2,-12(fp)
+    if (pmem == (OS_MEM *)0) {                        /* Must point to a valid memory partition        */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return ((void *)0);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 80132cc:	e0bfff15 	stw	r2,-4(fp)
+    if (pmem->OSMemNFree > 0) {                       /* See if there are any free memory blocks       */
+ 80132d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80132d4:	10800417 	ldw	r2,16(r2)
+ 80132d8:	10001426 	beq	r2,zero,801332c <OSMemGet+0x94>
+        pblk                = pmem->OSMemFreeList;    /* Yes, point to next free memory block          */
+ 80132dc:	e0bffa17 	ldw	r2,-24(fp)
+ 80132e0:	10800117 	ldw	r2,4(r2)
+ 80132e4:	e0bffe15 	stw	r2,-8(fp)
+        pmem->OSMemFreeList = *(void **)pblk;         /*      Adjust pointer to new free list          */
+ 80132e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80132ec:	10c00017 	ldw	r3,0(r2)
+ 80132f0:	e0bffa17 	ldw	r2,-24(fp)
+ 80132f4:	10c00115 	stw	r3,4(r2)
+        pmem->OSMemNFree--;                           /*      One less memory block in this partition  */
+ 80132f8:	e0bffa17 	ldw	r2,-24(fp)
+ 80132fc:	10800417 	ldw	r2,16(r2)
+ 8013300:	10ffffc4 	addi	r3,r2,-1
+ 8013304:	e0bffa17 	ldw	r2,-24(fp)
+ 8013308:	10c00415 	stw	r3,16(r2)
+ 801330c:	e0bfff17 	ldw	r2,-4(fp)
+ 8013310:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013314:	e0bffc17 	ldw	r2,-16(fp)
+ 8013318:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;                          /*      No error                                 */
+ 801331c:	e0bff917 	ldw	r2,-28(fp)
+ 8013320:	10000005 	stb	zero,0(r2)
+        return (pblk);                                /*      Return memory block to caller            */
+ 8013324:	e0bffe17 	ldw	r2,-8(fp)
+ 8013328:	00000806 	br	801334c <OSMemGet+0xb4>
+ 801332c:	e0bfff17 	ldw	r2,-4(fp)
+ 8013330:	e0bffb15 	stw	r2,-20(fp)
+ 8013334:	e0bffb17 	ldw	r2,-20(fp)
+ 8013338:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_MEM_NO_FREE_BLKS;                  /* No,  Notify caller of empty memory partition  */
+ 801333c:	e0bff917 	ldw	r2,-28(fp)
+ 8013340:	00c01744 	movi	r3,93
+ 8013344:	10c00005 	stb	r3,0(r2)
+    return ((void *)0);                               /*      Return NULL pointer to caller            */
+ 8013348:	0005883a 	mov	r2,zero
+}
+ 801334c:	e037883a 	mov	sp,fp
+ 8013350:	df000017 	ldw	fp,0(sp)
+ 8013354:	dec00104 	addi	sp,sp,4
+ 8013358:	f800283a 	ret
+
+0801335c <OSMemNameGet>:
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_SIZE > 1
+INT8U  OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr)
+{
+ 801335c:	defff704 	addi	sp,sp,-36
+ 8013360:	dfc00815 	stw	ra,32(sp)
+ 8013364:	df000715 	stw	fp,28(sp)
+ 8013368:	df000704 	addi	fp,sp,28
+ 801336c:	e13ffb15 	stw	r4,-20(fp)
+ 8013370:	e17ffa15 	stw	r5,-24(fp)
+ 8013374:	e1bff915 	stw	r6,-28(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8013378:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 801337c:	d0a05703 	ldbu	r2,-32420(gp)
+ 8013380:	10803fcc 	andi	r2,r2,255
+ 8013384:	10000526 	beq	r2,zero,801339c <OSMemNameGet+0x40>
+        *perr = OS_ERR_NAME_GET_ISR;
+ 8013388:	e0bff917 	ldw	r2,-28(fp)
+ 801338c:	00c00444 	movi	r3,17
+ 8013390:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8013394:	0005883a 	mov	r2,zero
+ 8013398:	00001506 	br	80133f0 <OSMemNameGet+0x94>
+  NIOS2_READ_STATUS (context);
+ 801339c:	0005303a 	rdctl	r2,status
+ 80133a0:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80133a4:	e0fffc17 	ldw	r3,-16(fp)
+ 80133a8:	00bfff84 	movi	r2,-2
+ 80133ac:	1884703a 	and	r2,r3,r2
+ 80133b0:	1001703a 	wrctl	status,r2
+  return context;
+ 80133b4:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80133b8:	e0bfff15 	stw	r2,-4(fp)
+    len   = OS_StrCopy(pname, pmem->OSMemName);  /* Copy name from OS_MEM                              */
+ 80133bc:	e0bffb17 	ldw	r2,-20(fp)
+ 80133c0:	10800504 	addi	r2,r2,20
+ 80133c4:	100b883a 	mov	r5,r2
+ 80133c8:	e13ffa17 	ldw	r4,-24(fp)
+ 80133cc:	80117a00 	call	80117a0 <OS_StrCopy>
+ 80133d0:	e0bffec5 	stb	r2,-5(fp)
+ 80133d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80133d8:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80133dc:	e0bffd17 	ldw	r2,-12(fp)
+ 80133e0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 80133e4:	e0bff917 	ldw	r2,-28(fp)
+ 80133e8:	10000005 	stb	zero,0(r2)
+    return (len);
+ 80133ec:	e0bffec3 	ldbu	r2,-5(fp)
+}
+ 80133f0:	e037883a 	mov	sp,fp
+ 80133f4:	dfc00117 	ldw	ra,4(sp)
+ 80133f8:	df000017 	ldw	fp,0(sp)
+ 80133fc:	dec00204 	addi	sp,sp,8
+ 8013400:	f800283a 	ret
+
+08013404 <OSMemNameSet>:
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_SIZE > 1
+void  OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr)
+{
+ 8013404:	defff604 	addi	sp,sp,-40
+ 8013408:	dfc00915 	stw	ra,36(sp)
+ 801340c:	df000815 	stw	fp,32(sp)
+ 8013410:	df000804 	addi	fp,sp,32
+ 8013414:	e13ffa15 	stw	r4,-24(fp)
+ 8013418:	e17ff915 	stw	r5,-28(fp)
+ 801341c:	e1bff815 	stw	r6,-32(fp)
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8013420:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 8013424:	d0a05703 	ldbu	r2,-32420(gp)
+ 8013428:	10803fcc 	andi	r2,r2,255
+ 801342c:	10000426 	beq	r2,zero,8013440 <OSMemNameSet+0x3c>
+        *perr = OS_ERR_NAME_SET_ISR;
+ 8013430:	e0bff817 	ldw	r2,-32(fp)
+ 8013434:	00c00484 	movi	r3,18
+ 8013438:	10c00005 	stb	r3,0(r2)
+        return;
+ 801343c:	00002106 	br	80134c4 <OSMemNameSet+0xc0>
+  NIOS2_READ_STATUS (context);
+ 8013440:	0005303a 	rdctl	r2,status
+ 8013444:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8013448:	e0fffd17 	ldw	r3,-12(fp)
+ 801344c:	00bfff84 	movi	r2,-2
+ 8013450:	1884703a 	and	r2,r3,r2
+ 8013454:	1001703a 	wrctl	status,r2
+  return context;
+ 8013458:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 801345c:	e0bfff15 	stw	r2,-4(fp)
+    len = OS_StrLen(pname);                      /* Can we fit the string in the storage area?         */
+ 8013460:	e13ff917 	ldw	r4,-28(fp)
+ 8013464:	80118140 	call	8011814 <OS_StrLen>
+ 8013468:	e0bffec5 	stb	r2,-5(fp)
+    if (len > (OS_MEM_NAME_SIZE - 1)) {          /* No                                                 */
+ 801346c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8013470:	10800830 	cmpltui	r2,r2,32
+ 8013474:	1000081e 	bne	r2,zero,8013498 <OSMemNameSet+0x94>
+ 8013478:	e0bfff17 	ldw	r2,-4(fp)
+ 801347c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013480:	e0bffc17 	ldw	r2,-16(fp)
+ 8013484:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_MEM_NAME_TOO_LONG;
+ 8013488:	e0bff817 	ldw	r2,-32(fp)
+ 801348c:	00c018c4 	movi	r3,99
+ 8013490:	10c00005 	stb	r3,0(r2)
+        return;
+ 8013494:	00000b06 	br	80134c4 <OSMemNameSet+0xc0>
+    }
+    (void)OS_StrCopy(pmem->OSMemName, pname);    /* Yes, copy name to the memory partition header      */
+ 8013498:	e0bffa17 	ldw	r2,-24(fp)
+ 801349c:	10800504 	addi	r2,r2,20
+ 80134a0:	e17ff917 	ldw	r5,-28(fp)
+ 80134a4:	1009883a 	mov	r4,r2
+ 80134a8:	80117a00 	call	80117a0 <OS_StrCopy>
+ 80134ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80134b0:	e0bffb15 	stw	r2,-20(fp)
+ 80134b4:	e0bffb17 	ldw	r2,-20(fp)
+ 80134b8:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 80134bc:	e0bff817 	ldw	r2,-32(fp)
+ 80134c0:	10000005 	stb	zero,0(r2)
+}
+ 80134c4:	e037883a 	mov	sp,fp
+ 80134c8:	dfc00117 	ldw	ra,4(sp)
+ 80134cc:	df000017 	ldw	fp,0(sp)
+ 80134d0:	dec00204 	addi	sp,sp,8
+ 80134d4:	f800283a 	ret
+
+080134d8 <OSMemPut>:
+*               OS_ERR_MEM_INVALID_PBLK  if you passed a NULL pointer for the block to release.
+*********************************************************************************************************
+*/
+
+INT8U  OSMemPut (OS_MEM *pmem, void *pblk)
+{
+ 80134d8:	defff904 	addi	sp,sp,-28
+ 80134dc:	df000615 	stw	fp,24(sp)
+ 80134e0:	df000604 	addi	fp,sp,24
+ 80134e4:	e13ffb15 	stw	r4,-20(fp)
+ 80134e8:	e17ffa15 	stw	r5,-24(fp)
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 80134ec:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80134f0:	0005303a 	rdctl	r2,status
+ 80134f4:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80134f8:	e0fffe17 	ldw	r3,-8(fp)
+ 80134fc:	00bfff84 	movi	r2,-2
+ 8013500:	1884703a 	and	r2,r3,r2
+ 8013504:	1001703a 	wrctl	status,r2
+  return context;
+ 8013508:	e0bffe17 	ldw	r2,-8(fp)
+    }
+    if (pblk == (void *)0) {                     /* Must release a valid block                         */
+        return (OS_ERR_MEM_INVALID_PBLK);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 801350c:	e0bfff15 	stw	r2,-4(fp)
+    if (pmem->OSMemNFree >= pmem->OSMemNBlks) {  /* Make sure all blocks not already returned          */
+ 8013510:	e0bffb17 	ldw	r2,-20(fp)
+ 8013514:	10c00417 	ldw	r3,16(r2)
+ 8013518:	e0bffb17 	ldw	r2,-20(fp)
+ 801351c:	10800317 	ldw	r2,12(r2)
+ 8013520:	18800636 	bltu	r3,r2,801353c <OSMemPut+0x64>
+ 8013524:	e0bfff17 	ldw	r2,-4(fp)
+ 8013528:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801352c:	e0bffd17 	ldw	r2,-12(fp)
+ 8013530:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_MEM_FULL);
+ 8013534:	00801784 	movi	r2,94
+ 8013538:	00001106 	br	8013580 <OSMemPut+0xa8>
+    }
+    *(void **)pblk      = pmem->OSMemFreeList;   /* Insert released block into free block list         */
+ 801353c:	e0bffb17 	ldw	r2,-20(fp)
+ 8013540:	10c00117 	ldw	r3,4(r2)
+ 8013544:	e0bffa17 	ldw	r2,-24(fp)
+ 8013548:	10c00015 	stw	r3,0(r2)
+    pmem->OSMemFreeList = pblk;
+ 801354c:	e0bffb17 	ldw	r2,-20(fp)
+ 8013550:	e0fffa17 	ldw	r3,-24(fp)
+ 8013554:	10c00115 	stw	r3,4(r2)
+    pmem->OSMemNFree++;                          /* One more memory block in this partition            */
+ 8013558:	e0bffb17 	ldw	r2,-20(fp)
+ 801355c:	10800417 	ldw	r2,16(r2)
+ 8013560:	10c00044 	addi	r3,r2,1
+ 8013564:	e0bffb17 	ldw	r2,-20(fp)
+ 8013568:	10c00415 	stw	r3,16(r2)
+ 801356c:	e0bfff17 	ldw	r2,-4(fp)
+ 8013570:	e0bffc15 	stw	r2,-16(fp)
+ 8013574:	e0bffc17 	ldw	r2,-16(fp)
+ 8013578:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);                        /* Notify caller that memory block was released       */
+ 801357c:	0005883a 	mov	r2,zero
+}
+ 8013580:	e037883a 	mov	sp,fp
+ 8013584:	df000017 	ldw	fp,0(sp)
+ 8013588:	dec00104 	addi	sp,sp,4
+ 801358c:	f800283a 	ret
+
+08013590 <OSMemQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_MEM_QUERY_EN > 0
+INT8U  OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data)
+{
+ 8013590:	defffa04 	addi	sp,sp,-24
+ 8013594:	df000515 	stw	fp,20(sp)
+ 8013598:	df000504 	addi	fp,sp,20
+ 801359c:	e13ffc15 	stw	r4,-16(fp)
+ 80135a0:	e17ffb15 	stw	r5,-20(fp)
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 80135a4:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80135a8:	0005303a 	rdctl	r2,status
+ 80135ac:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80135b0:	e0fffd17 	ldw	r3,-12(fp)
+ 80135b4:	00bfff84 	movi	r2,-2
+ 80135b8:	1884703a 	and	r2,r3,r2
+ 80135bc:	1001703a 	wrctl	status,r2
+  return context;
+ 80135c0:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    if (p_mem_data == (OS_MEM_DATA *)0) {        /* Must release a valid storage area for the data     */
+        return (OS_ERR_MEM_INVALID_PDATA);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 80135c4:	e0bfff15 	stw	r2,-4(fp)
+    p_mem_data->OSAddr     = pmem->OSMemAddr;
+ 80135c8:	e0bffc17 	ldw	r2,-16(fp)
+ 80135cc:	10c00017 	ldw	r3,0(r2)
+ 80135d0:	e0bffb17 	ldw	r2,-20(fp)
+ 80135d4:	10c00015 	stw	r3,0(r2)
+    p_mem_data->OSFreeList = pmem->OSMemFreeList;
+ 80135d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80135dc:	10c00117 	ldw	r3,4(r2)
+ 80135e0:	e0bffb17 	ldw	r2,-20(fp)
+ 80135e4:	10c00115 	stw	r3,4(r2)
+    p_mem_data->OSBlkSize  = pmem->OSMemBlkSize;
+ 80135e8:	e0bffc17 	ldw	r2,-16(fp)
+ 80135ec:	10c00217 	ldw	r3,8(r2)
+ 80135f0:	e0bffb17 	ldw	r2,-20(fp)
+ 80135f4:	10c00215 	stw	r3,8(r2)
+    p_mem_data->OSNBlks    = pmem->OSMemNBlks;
+ 80135f8:	e0bffc17 	ldw	r2,-16(fp)
+ 80135fc:	10c00317 	ldw	r3,12(r2)
+ 8013600:	e0bffb17 	ldw	r2,-20(fp)
+ 8013604:	10c00315 	stw	r3,12(r2)
+    p_mem_data->OSNFree    = pmem->OSMemNFree;
+ 8013608:	e0bffc17 	ldw	r2,-16(fp)
+ 801360c:	10c00417 	ldw	r3,16(r2)
+ 8013610:	e0bffb17 	ldw	r2,-20(fp)
+ 8013614:	10c00415 	stw	r3,16(r2)
+ 8013618:	e0bfff17 	ldw	r2,-4(fp)
+ 801361c:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013620:	e0bffe17 	ldw	r2,-8(fp)
+ 8013624:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    p_mem_data->OSNUsed    = p_mem_data->OSNBlks - p_mem_data->OSNFree;
+ 8013628:	e0bffb17 	ldw	r2,-20(fp)
+ 801362c:	10c00317 	ldw	r3,12(r2)
+ 8013630:	e0bffb17 	ldw	r2,-20(fp)
+ 8013634:	10800417 	ldw	r2,16(r2)
+ 8013638:	1887c83a 	sub	r3,r3,r2
+ 801363c:	e0bffb17 	ldw	r2,-20(fp)
+ 8013640:	10c00515 	stw	r3,20(r2)
+    return (OS_ERR_NONE);
+ 8013644:	0005883a 	mov	r2,zero
+}
+ 8013648:	e037883a 	mov	sp,fp
+ 801364c:	df000017 	ldw	fp,0(sp)
+ 8013650:	dec00104 	addi	sp,sp,4
+ 8013654:	f800283a 	ret
+
+08013658 <OS_MemInit>:
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_MemInit (void)
+{
+ 8013658:	defffc04 	addi	sp,sp,-16
+ 801365c:	dfc00315 	stw	ra,12(sp)
+ 8013660:	df000215 	stw	fp,8(sp)
+ 8013664:	df000204 	addi	fp,sp,8
+#if OS_MAX_MEM_PART >= 2
+    OS_MEM  *pmem;
+    INT16U   i;
+
+
+    OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl));   /* Clear the memory partition table          */
+ 8013668:	01430c04 	movi	r5,3120
+ 801366c:	010201b4 	movhi	r4,2054
+ 8013670:	212c6704 	addi	r4,r4,-20068
+ 8013674:	80115b00 	call	80115b0 <OS_MemClr>
+    pmem = &OSMemTbl[0];                                  /* Point to memory control block (MCB)       */
+ 8013678:	008201b4 	movhi	r2,2054
+ 801367c:	10ac6704 	addi	r2,r2,-20068
+ 8013680:	e0bfff15 	stw	r2,-4(fp)
+    for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) {         /* Init. list of free memory partitions      */
+ 8013684:	e03ffe8d 	sth	zero,-6(fp)
+ 8013688:	00001306 	br	80136d8 <OS_MemInit+0x80>
+        pmem->OSMemFreeList = (void *)&OSMemTbl[i+1];     /* Chain list of free partitions             */
+ 801368c:	e0bffe8b 	ldhu	r2,-6(fp)
+ 8013690:	10800044 	addi	r2,r2,1
+ 8013694:	10c00d24 	muli	r3,r2,52
+ 8013698:	008201b4 	movhi	r2,2054
+ 801369c:	10ac6704 	addi	r2,r2,-20068
+ 80136a0:	1887883a 	add	r3,r3,r2
+ 80136a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80136a8:	10c00115 	stw	r3,4(r2)
+#if OS_MEM_NAME_SIZE > 1
+        pmem->OSMemName[0]  = '?';                        /* Unknown name                              */
+ 80136ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80136b0:	00c00fc4 	movi	r3,63
+ 80136b4:	10c00505 	stb	r3,20(r2)
+        pmem->OSMemName[1]  = OS_ASCII_NUL;
+ 80136b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80136bc:	10000545 	stb	zero,21(r2)
+#endif
+        pmem++;
+ 80136c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80136c4:	10800d04 	addi	r2,r2,52
+ 80136c8:	e0bfff15 	stw	r2,-4(fp)
+    for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) {         /* Init. list of free memory partitions      */
+ 80136cc:	e0bffe8b 	ldhu	r2,-6(fp)
+ 80136d0:	10800044 	addi	r2,r2,1
+ 80136d4:	e0bffe8d 	sth	r2,-6(fp)
+ 80136d8:	e0bffe8b 	ldhu	r2,-6(fp)
+ 80136dc:	10800ef0 	cmpltui	r2,r2,59
+ 80136e0:	103fea1e 	bne	r2,zero,801368c <OS_MemInit+0x34>
+    }
+    pmem->OSMemFreeList = (void *)0;                      /* Initialize last node                      */
+ 80136e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80136e8:	10000115 	stw	zero,4(r2)
+#if OS_MEM_NAME_SIZE > 1
+    pmem->OSMemName[0]  = '?';                            /* Unknown name                              */
+ 80136ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80136f0:	00c00fc4 	movi	r3,63
+ 80136f4:	10c00505 	stb	r3,20(r2)
+    pmem->OSMemName[1]  = OS_ASCII_NUL;
+ 80136f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80136fc:	10000545 	stb	zero,21(r2)
+#endif
+
+    OSMemFreeList       = &OSMemTbl[0];                   /* Point to beginning of free list           */
+ 8013700:	008201b4 	movhi	r2,2054
+ 8013704:	10ac6704 	addi	r2,r2,-20068
+ 8013708:	d0a05215 	stw	r2,-32440(gp)
+#endif
+}
+ 801370c:	0001883a 	nop
+ 8013710:	e037883a 	mov	sp,fp
+ 8013714:	dfc00117 	ldw	ra,4(sp)
+ 8013718:	df000017 	ldw	fp,0(sp)
+ 801371c:	dec00204 	addi	sp,sp,8
+ 8013720:	f800283a 	ret
+
+08013724 <OSMutexAccept>:
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_ACCEPT_EN > 0
+BOOLEAN  OSMutexAccept (OS_EVENT *pevent, INT8U *perr)
+{
+ 8013724:	defff704 	addi	sp,sp,-36
+ 8013728:	df000815 	stw	fp,32(sp)
+ 801372c:	df000804 	addi	fp,sp,32
+ 8013730:	e13ff915 	stw	r4,-28(fp)
+ 8013734:	e17ff815 	stw	r5,-32(fp)
+    INT8U      pip;                                    /* Priority Inheritance Priority (PIP)          */
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+ 8013738:	e03fff15 	stw	zero,-4(fp)
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (OS_FALSE);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {  /* Validate event block type                    */
+ 801373c:	e0bff917 	ldw	r2,-28(fp)
+ 8013740:	10800003 	ldbu	r2,0(r2)
+ 8013744:	10803fcc 	andi	r2,r2,255
+ 8013748:	10800120 	cmpeqi	r2,r2,4
+ 801374c:	1000051e 	bne	r2,zero,8013764 <OSMutexAccept+0x40>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8013750:	e0bff817 	ldw	r2,-32(fp)
+ 8013754:	00c00044 	movi	r3,1
+ 8013758:	10c00005 	stb	r3,0(r2)
+        return (OS_FALSE);
+ 801375c:	0005883a 	mov	r2,zero
+ 8013760:	00004a06 	br	801388c <OSMutexAccept+0x168>
+    }
+    if (OSIntNesting > 0) {                            /* Make sure it's not called from an ISR        */
+ 8013764:	d0a05703 	ldbu	r2,-32420(gp)
+ 8013768:	10803fcc 	andi	r2,r2,255
+ 801376c:	10000526 	beq	r2,zero,8013784 <OSMutexAccept+0x60>
+        *perr = OS_ERR_PEND_ISR;
+ 8013770:	e0bff817 	ldw	r2,-32(fp)
+ 8013774:	00c00084 	movi	r3,2
+ 8013778:	10c00005 	stb	r3,0(r2)
+        return (OS_FALSE);
+ 801377c:	0005883a 	mov	r2,zero
+ 8013780:	00004206 	br	801388c <OSMutexAccept+0x168>
+  NIOS2_READ_STATUS (context);
+ 8013784:	0005303a 	rdctl	r2,status
+ 8013788:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801378c:	e0fffd17 	ldw	r3,-12(fp)
+ 8013790:	00bfff84 	movi	r2,-2
+ 8013794:	1884703a 	and	r2,r3,r2
+ 8013798:	1001703a 	wrctl	status,r2
+  return context;
+ 801379c:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();                               /* Get value (0 or 1) of Mutex                  */
+ 80137a0:	e0bfff15 	stw	r2,-4(fp)
+    pip = (INT8U)(pevent->OSEventCnt >> 8);            /* Get PIP from mutex                           */
+ 80137a4:	e0bff917 	ldw	r2,-28(fp)
+ 80137a8:	1080020b 	ldhu	r2,8(r2)
+ 80137ac:	10bfffcc 	andi	r2,r2,65535
+ 80137b0:	1004d23a 	srli	r2,r2,8
+ 80137b4:	e0bffec5 	stb	r2,-5(fp)
+    if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+ 80137b8:	e0bff917 	ldw	r2,-28(fp)
+ 80137bc:	1080020b 	ldhu	r2,8(r2)
+ 80137c0:	10bfffcc 	andi	r2,r2,65535
+ 80137c4:	10803fcc 	andi	r2,r2,255
+ 80137c8:	10803fd8 	cmpnei	r2,r2,255
+ 80137cc:	1000281e 	bne	r2,zero,8013870 <OSMutexAccept+0x14c>
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;   /*      Mask off LSByte (Acquire Mutex)         */
+ 80137d0:	e0bff917 	ldw	r2,-28(fp)
+ 80137d4:	10c0020b 	ldhu	r3,8(r2)
+ 80137d8:	00bfc004 	movi	r2,-256
+ 80137dc:	1884703a 	and	r2,r3,r2
+ 80137e0:	1007883a 	mov	r3,r2
+ 80137e4:	e0bff917 	ldw	r2,-28(fp)
+ 80137e8:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventCnt |= OSTCBCur->OSTCBPrio;     /*      Save current task priority in LSByte    */
+ 80137ec:	e0bff917 	ldw	r2,-28(fp)
+ 80137f0:	10c0020b 	ldhu	r3,8(r2)
+ 80137f4:	d0a05817 	ldw	r2,-32416(gp)
+ 80137f8:	10800c83 	ldbu	r2,50(r2)
+ 80137fc:	10803fcc 	andi	r2,r2,255
+ 8013800:	1884b03a 	or	r2,r3,r2
+ 8013804:	1007883a 	mov	r3,r2
+ 8013808:	e0bff917 	ldw	r2,-28(fp)
+ 801380c:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventPtr  = (void *)OSTCBCur;        /*      Link TCB of task owning Mutex           */
+ 8013810:	d0e05817 	ldw	r3,-32416(gp)
+ 8013814:	e0bff917 	ldw	r2,-28(fp)
+ 8013818:	10c00115 	stw	r3,4(r2)
+        if (OSTCBCur->OSTCBPrio <= pip) {              /*      PIP 'must' have a SMALLER prio ...      */
+ 801381c:	d0a05817 	ldw	r2,-32416(gp)
+ 8013820:	10800c83 	ldbu	r2,50(r2)
+ 8013824:	e0fffec3 	ldbu	r3,-5(fp)
+ 8013828:	10803fcc 	andi	r2,r2,255
+ 801382c:	18800836 	bltu	r3,r2,8013850 <OSMutexAccept+0x12c>
+ 8013830:	e0bfff17 	ldw	r2,-4(fp)
+ 8013834:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013838:	e0bffc17 	ldw	r2,-16(fp)
+ 801383c:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();                        /*      ... than current task!                  */
+            *perr = OS_ERR_PIP_LOWER;
+ 8013840:	e0bff817 	ldw	r2,-32(fp)
+ 8013844:	00c01e04 	movi	r3,120
+ 8013848:	10c00005 	stb	r3,0(r2)
+ 801384c:	00000606 	br	8013868 <OSMutexAccept+0x144>
+ 8013850:	e0bfff17 	ldw	r2,-4(fp)
+ 8013854:	e0bffb15 	stw	r2,-20(fp)
+ 8013858:	e0bffb17 	ldw	r2,-20(fp)
+ 801385c:	1001703a 	wrctl	status,r2
+        } else {
+            OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+ 8013860:	e0bff817 	ldw	r2,-32(fp)
+ 8013864:	10000005 	stb	zero,0(r2)
+        }
+        return (OS_TRUE);
+ 8013868:	00800044 	movi	r2,1
+ 801386c:	00000706 	br	801388c <OSMutexAccept+0x168>
+ 8013870:	e0bfff17 	ldw	r2,-4(fp)
+ 8013874:	e0bffa15 	stw	r2,-24(fp)
+ 8013878:	e0bffa17 	ldw	r2,-24(fp)
+ 801387c:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8013880:	e0bff817 	ldw	r2,-32(fp)
+ 8013884:	10000005 	stb	zero,0(r2)
+    return (OS_FALSE);
+ 8013888:	0005883a 	mov	r2,zero
+}
+ 801388c:	e037883a 	mov	sp,fp
+ 8013890:	df000017 	ldw	fp,0(sp)
+ 8013894:	dec00104 	addi	sp,sp,4
+ 8013898:	f800283a 	ret
+
+0801389c <OSMutexCreate>:
+*                 to use to reduce priority inversion.
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSMutexCreate (INT8U prio, INT8U *perr)
+{
+ 801389c:	defff604 	addi	sp,sp,-40
+ 80138a0:	dfc00915 	stw	ra,36(sp)
+ 80138a4:	df000815 	stw	fp,32(sp)
+ 80138a8:	df000804 	addi	fp,sp,32
+ 80138ac:	2005883a 	mov	r2,r4
+ 80138b0:	e17ff815 	stw	r5,-32(fp)
+ 80138b4:	e0bff905 	stb	r2,-28(fp)
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 80138b8:	e03fff15 	stw	zero,-4(fp)
+    if (prio >= OS_LOWEST_PRIO) {                          /* Validate PIP                             */
+        *perr = OS_ERR_PRIO_INVALID;
+        return ((OS_EVENT *)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 80138bc:	d0a05703 	ldbu	r2,-32420(gp)
+ 80138c0:	10803fcc 	andi	r2,r2,255
+ 80138c4:	10000526 	beq	r2,zero,80138dc <OSMutexCreate+0x40>
+        *perr = OS_ERR_CREATE_ISR;                         /* ... can't CREATE mutex from an ISR       */
+ 80138c8:	e0bff817 	ldw	r2,-32(fp)
+ 80138cc:	00c00404 	movi	r3,16
+ 80138d0:	10c00005 	stb	r3,0(r2)
+        return ((OS_EVENT *)0);
+ 80138d4:	0005883a 	mov	r2,zero
+ 80138d8:	00004b06 	br	8013a08 <OSMutexCreate+0x16c>
+  NIOS2_READ_STATUS (context);
+ 80138dc:	0005303a 	rdctl	r2,status
+ 80138e0:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80138e4:	e0fffd17 	ldw	r3,-12(fp)
+ 80138e8:	00bfff84 	movi	r2,-2
+ 80138ec:	1884703a 	and	r2,r3,r2
+ 80138f0:	1001703a 	wrctl	status,r2
+  return context;
+ 80138f4:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80138f8:	e0bfff15 	stw	r2,-4(fp)
+    if (OSTCBPrioTbl[prio] != (OS_TCB *)0) {               /* Mutex priority must not already exist    */
+ 80138fc:	e0bff903 	ldbu	r2,-28(fp)
+ 8013900:	100690ba 	slli	r3,r2,2
+ 8013904:	008201b4 	movhi	r2,2054
+ 8013908:	1885883a 	add	r2,r3,r2
+ 801390c:	10b55d17 	ldw	r2,-10892(r2)
+ 8013910:	10000926 	beq	r2,zero,8013938 <OSMutexCreate+0x9c>
+ 8013914:	e0bfff17 	ldw	r2,-4(fp)
+ 8013918:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801391c:	e0bffc17 	ldw	r2,-16(fp)
+ 8013920:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                                /* Task already exist at priority ...       */
+        *perr = OS_ERR_PRIO_EXIST;                         /* ... inheritance priority                 */
+ 8013924:	e0bff817 	ldw	r2,-32(fp)
+ 8013928:	00c00a04 	movi	r3,40
+ 801392c:	10c00005 	stb	r3,0(r2)
+        return ((OS_EVENT *)0);
+ 8013930:	0005883a 	mov	r2,zero
+ 8013934:	00003406 	br	8013a08 <OSMutexCreate+0x16c>
+    }
+    OSTCBPrioTbl[prio] = OS_TCB_RESERVED;                  /* Reserve the table entry                  */
+ 8013938:	e0bff903 	ldbu	r2,-28(fp)
+ 801393c:	100890ba 	slli	r4,r2,2
+ 8013940:	00c00044 	movi	r3,1
+ 8013944:	008201b4 	movhi	r2,2054
+ 8013948:	2085883a 	add	r2,r4,r2
+ 801394c:	10f55d15 	stw	r3,-10892(r2)
+    pevent             = OSEventFreeList;                  /* Get next free event control block        */
+ 8013950:	d0a05617 	ldw	r2,-32424(gp)
+ 8013954:	e0bffe15 	stw	r2,-8(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* See if an ECB was available              */
+ 8013958:	e0bffe17 	ldw	r2,-8(fp)
+ 801395c:	10000e1e 	bne	r2,zero,8013998 <OSMutexCreate+0xfc>
+        OSTCBPrioTbl[prio] = (OS_TCB *)0;                  /* No, Release the table entry              */
+ 8013960:	e0bff903 	ldbu	r2,-28(fp)
+ 8013964:	100690ba 	slli	r3,r2,2
+ 8013968:	008201b4 	movhi	r2,2054
+ 801396c:	1885883a 	add	r2,r3,r2
+ 8013970:	10355d15 	stw	zero,-10892(r2)
+ 8013974:	e0bfff17 	ldw	r2,-4(fp)
+ 8013978:	e0bffb15 	stw	r2,-20(fp)
+ 801397c:	e0bffb17 	ldw	r2,-20(fp)
+ 8013980:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr              = OS_ERR_PEVENT_NULL;           /* No more event control blocks             */
+ 8013984:	e0bff817 	ldw	r2,-32(fp)
+ 8013988:	00c00104 	movi	r3,4
+ 801398c:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8013990:	e0bffe17 	ldw	r2,-8(fp)
+ 8013994:	00001c06 	br	8013a08 <OSMutexCreate+0x16c>
+    }
+    OSEventFreeList        = (OS_EVENT *)OSEventFreeList->OSEventPtr;   /* Adjust the free list        */
+ 8013998:	d0a05617 	ldw	r2,-32424(gp)
+ 801399c:	10800117 	ldw	r2,4(r2)
+ 80139a0:	d0a05615 	stw	r2,-32424(gp)
+ 80139a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80139a8:	e0bffa15 	stw	r2,-24(fp)
+ 80139ac:	e0bffa17 	ldw	r2,-24(fp)
+ 80139b0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    pevent->OSEventType    = OS_EVENT_TYPE_MUTEX;
+ 80139b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80139b8:	00c00104 	movi	r3,4
+ 80139bc:	10c00005 	stb	r3,0(r2)
+    pevent->OSEventCnt     = (INT16U)((INT16U)prio << 8) | OS_MUTEX_AVAILABLE; /* Resource is avail.   */
+ 80139c0:	e0bff903 	ldbu	r2,-28(fp)
+ 80139c4:	1004923a 	slli	r2,r2,8
+ 80139c8:	10803fd4 	ori	r2,r2,255
+ 80139cc:	1007883a 	mov	r3,r2
+ 80139d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80139d4:	10c0020d 	sth	r3,8(r2)
+    pevent->OSEventPtr     = (void *)0;                                 /* No task owning the mutex    */
+ 80139d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80139dc:	10000115 	stw	zero,4(r2)
+#if OS_EVENT_NAME_SIZE > 1
+    pevent->OSEventName[0] = '?';
+ 80139e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80139e4:	00c00fc4 	movi	r3,63
+ 80139e8:	10c00385 	stb	r3,14(r2)
+    pevent->OSEventName[1] = OS_ASCII_NUL;
+ 80139ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80139f0:	100003c5 	stb	zero,15(r2)
+#endif
+    OS_EventWaitListInit(pevent);
+ 80139f4:	e13ffe17 	ldw	r4,-8(fp)
+ 80139f8:	80112580 	call	8011258 <OS_EventWaitListInit>
+    *perr                  = OS_ERR_NONE;
+ 80139fc:	e0bff817 	ldw	r2,-32(fp)
+ 8013a00:	10000005 	stb	zero,0(r2)
+    return (pevent);
+ 8013a04:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8013a08:	e037883a 	mov	sp,fp
+ 8013a0c:	dfc00117 	ldw	ra,4(sp)
+ 8013a10:	df000017 	ldw	fp,0(sp)
+ 8013a14:	dec00204 	addi	sp,sp,8
+ 8013a18:	f800283a 	ret
+
+08013a1c <OSMutexDel>:
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_DEL_EN
+OS_EVENT  *OSMutexDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+ 8013a1c:	defff104 	addi	sp,sp,-60
+ 8013a20:	dfc00e15 	stw	ra,56(sp)
+ 8013a24:	df000d15 	stw	fp,52(sp)
+ 8013a28:	df000d04 	addi	fp,sp,52
+ 8013a2c:	e13ff515 	stw	r4,-44(fp)
+ 8013a30:	2805883a 	mov	r2,r5
+ 8013a34:	e1bff315 	stw	r6,-52(fp)
+ 8013a38:	e0bff405 	stb	r2,-48(fp)
+    OS_EVENT  *pevent_return;
+    INT8U      pip;                                        /* Priority inheritance priority            */
+    INT8U      prio;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 8013a3c:	e03ffd15 	stw	zero,-12(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+ 8013a40:	e0bff517 	ldw	r2,-44(fp)
+ 8013a44:	10800003 	ldbu	r2,0(r2)
+ 8013a48:	10803fcc 	andi	r2,r2,255
+ 8013a4c:	10800120 	cmpeqi	r2,r2,4
+ 8013a50:	1000051e 	bne	r2,zero,8013a68 <OSMutexDel+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8013a54:	e0bff317 	ldw	r2,-52(fp)
+ 8013a58:	00c00044 	movi	r3,1
+ 8013a5c:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8013a60:	e0bff517 	ldw	r2,-44(fp)
+ 8013a64:	00009806 	br	8013cc8 <OSMutexDel+0x2ac>
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8013a68:	d0a05703 	ldbu	r2,-32420(gp)
+ 8013a6c:	10803fcc 	andi	r2,r2,255
+ 8013a70:	10000526 	beq	r2,zero,8013a88 <OSMutexDel+0x6c>
+        *perr = OS_ERR_DEL_ISR;                             /* ... can't DELETE from an ISR             */
+ 8013a74:	e0bff317 	ldw	r2,-52(fp)
+ 8013a78:	00c003c4 	movi	r3,15
+ 8013a7c:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8013a80:	e0bff517 	ldw	r2,-44(fp)
+ 8013a84:	00009006 	br	8013cc8 <OSMutexDel+0x2ac>
+  NIOS2_READ_STATUS (context);
+ 8013a88:	0005303a 	rdctl	r2,status
+ 8013a8c:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8013a90:	e0fffa17 	ldw	r3,-24(fp)
+ 8013a94:	00bfff84 	movi	r2,-2
+ 8013a98:	1884703a 	and	r2,r3,r2
+ 8013a9c:	1001703a 	wrctl	status,r2
+  return context;
+ 8013aa0:	e0bffa17 	ldw	r2,-24(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8013aa4:	e0bffd15 	stw	r2,-12(fp)
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on mutex        */
+ 8013aa8:	e0bff517 	ldw	r2,-44(fp)
+ 8013aac:	10800283 	ldbu	r2,10(r2)
+ 8013ab0:	10803fcc 	andi	r2,r2,255
+ 8013ab4:	10000326 	beq	r2,zero,8013ac4 <OSMutexDel+0xa8>
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+ 8013ab8:	00800044 	movi	r2,1
+ 8013abc:	e0bfffc5 	stb	r2,-1(fp)
+ 8013ac0:	00000106 	br	8013ac8 <OSMutexDel+0xac>
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+ 8013ac4:	e03fffc5 	stb	zero,-1(fp)
+    }
+    switch (opt) {
+ 8013ac8:	e0bff403 	ldbu	r2,-48(fp)
+ 8013acc:	10000326 	beq	r2,zero,8013adc <OSMutexDel+0xc0>
+ 8013ad0:	10800060 	cmpeqi	r2,r2,1
+ 8013ad4:	10002d1e 	bne	r2,zero,8013b8c <OSMutexDel+0x170>
+ 8013ad8:	00007006 	br	8013c9c <OSMutexDel+0x280>
+        case OS_DEL_NO_PEND:                               /* DELETE MUTEX ONLY IF NO TASK WAITING --- */
+             if (tasks_waiting == OS_FALSE) {
+ 8013adc:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8013ae0:	1000201e 	bne	r2,zero,8013b64 <OSMutexDel+0x148>
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+ 8013ae4:	e0bff517 	ldw	r2,-44(fp)
+ 8013ae8:	00c00fc4 	movi	r3,63
+ 8013aec:	10c00385 	stb	r3,14(r2)
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8013af0:	e0bff517 	ldw	r2,-44(fp)
+ 8013af4:	100003c5 	stb	zero,15(r2)
+#endif
+                 pip                 = (INT8U)(pevent->OSEventCnt >> 8);
+ 8013af8:	e0bff517 	ldw	r2,-44(fp)
+ 8013afc:	1080020b 	ldhu	r2,8(r2)
+ 8013b00:	10bfffcc 	andi	r2,r2,65535
+ 8013b04:	1004d23a 	srli	r2,r2,8
+ 8013b08:	e0bffcc5 	stb	r2,-13(fp)
+                 OSTCBPrioTbl[pip]   = (OS_TCB *)0;        /* Free up the PIP                          */
+ 8013b0c:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8013b10:	100690ba 	slli	r3,r2,2
+ 8013b14:	008201b4 	movhi	r2,2054
+ 8013b18:	1885883a 	add	r2,r3,r2
+ 8013b1c:	10355d15 	stw	zero,-10892(r2)
+                 pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+ 8013b20:	e0bff517 	ldw	r2,-44(fp)
+ 8013b24:	10000005 	stb	zero,0(r2)
+                 pevent->OSEventPtr  = OSEventFreeList;    /* Return Event Control Block to free list  */
+ 8013b28:	d0e05617 	ldw	r3,-32424(gp)
+ 8013b2c:	e0bff517 	ldw	r2,-44(fp)
+ 8013b30:	10c00115 	stw	r3,4(r2)
+                 pevent->OSEventCnt  = 0;
+ 8013b34:	e0bff517 	ldw	r2,-44(fp)
+ 8013b38:	1000020d 	sth	zero,8(r2)
+                 OSEventFreeList     = pevent;
+ 8013b3c:	e0bff517 	ldw	r2,-44(fp)
+ 8013b40:	d0a05615 	stw	r2,-32424(gp)
+ 8013b44:	e0bffd17 	ldw	r2,-12(fp)
+ 8013b48:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013b4c:	e0bff917 	ldw	r2,-28(fp)
+ 8013b50:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_NONE;
+ 8013b54:	e0bff317 	ldw	r2,-52(fp)
+ 8013b58:	10000005 	stb	zero,0(r2)
+                 pevent_return       = (OS_EVENT *)0;      /* Mutex has been deleted                   */
+ 8013b5c:	e03ffe15 	stw	zero,-8(fp)
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_TASK_WAITING;
+                 pevent_return       = pevent;
+             }
+             break;
+ 8013b60:	00005806 	br	8013cc4 <OSMutexDel+0x2a8>
+ 8013b64:	e0bffd17 	ldw	r2,-12(fp)
+ 8013b68:	e0bff815 	stw	r2,-32(fp)
+ 8013b6c:	e0bff817 	ldw	r2,-32(fp)
+ 8013b70:	1001703a 	wrctl	status,r2
+                 *perr               = OS_ERR_TASK_WAITING;
+ 8013b74:	e0bff317 	ldw	r2,-52(fp)
+ 8013b78:	00c01244 	movi	r3,73
+ 8013b7c:	10c00005 	stb	r3,0(r2)
+                 pevent_return       = pevent;
+ 8013b80:	e0bff517 	ldw	r2,-44(fp)
+ 8013b84:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8013b88:	00004e06 	br	8013cc4 <OSMutexDel+0x2a8>
+
+        case OS_DEL_ALWAYS:                                /* ALWAYS DELETE THE MUTEX ---------------- */
+             pip  = (INT8U)(pevent->OSEventCnt >> 8);                     /* Get PIP of mutex          */
+ 8013b8c:	e0bff517 	ldw	r2,-44(fp)
+ 8013b90:	1080020b 	ldhu	r2,8(r2)
+ 8013b94:	10bfffcc 	andi	r2,r2,65535
+ 8013b98:	1004d23a 	srli	r2,r2,8
+ 8013b9c:	e0bffcc5 	stb	r2,-13(fp)
+             prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* Get owner's original prio */
+ 8013ba0:	e0bff517 	ldw	r2,-44(fp)
+ 8013ba4:	1080020b 	ldhu	r2,8(r2)
+ 8013ba8:	e0bffc85 	stb	r2,-14(fp)
+             ptcb = (OS_TCB *)pevent->OSEventPtr;
+ 8013bac:	e0bff517 	ldw	r2,-44(fp)
+ 8013bb0:	10800117 	ldw	r2,4(r2)
+ 8013bb4:	e0bffb15 	stw	r2,-20(fp)
+             if (ptcb != (OS_TCB *)0) {                    /* See if any task owns the mutex           */
+ 8013bb8:	e0bffb17 	ldw	r2,-20(fp)
+ 8013bbc:	10000f26 	beq	r2,zero,8013bfc <OSMutexDel+0x1e0>
+                 if (ptcb->OSTCBPrio == pip) {             /* See if original prio was changed         */
+ 8013bc0:	e0bffb17 	ldw	r2,-20(fp)
+ 8013bc4:	10800c83 	ldbu	r2,50(r2)
+ 8013bc8:	e0fffcc3 	ldbu	r3,-13(fp)
+ 8013bcc:	10803fcc 	andi	r2,r2,255
+ 8013bd0:	18800a1e 	bne	r3,r2,8013bfc <OSMutexDel+0x1e0>
+                     OSMutex_RdyAtPrio(ptcb, prio);        /* Yes, Restore the task's original prio    */
+ 8013bd4:	e0bffc83 	ldbu	r2,-14(fp)
+ 8013bd8:	100b883a 	mov	r5,r2
+ 8013bdc:	e13ffb17 	ldw	r4,-20(fp)
+ 8013be0:	801457c0 	call	801457c <OSMutex_RdyAtPrio>
+                 }
+             }
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for mutex        */
+ 8013be4:	00000506 	br	8013bfc <OSMutexDel+0x1e0>
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK);
+ 8013be8:	000f883a 	mov	r7,zero
+ 8013bec:	01800404 	movi	r6,16
+ 8013bf0:	000b883a 	mov	r5,zero
+ 8013bf4:	e13ff517 	ldw	r4,-44(fp)
+ 8013bf8:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for mutex        */
+ 8013bfc:	e0bff517 	ldw	r2,-44(fp)
+ 8013c00:	10800283 	ldbu	r2,10(r2)
+ 8013c04:	10803fcc 	andi	r2,r2,255
+ 8013c08:	103ff71e 	bne	r2,zero,8013be8 <OSMutexDel+0x1cc>
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+ 8013c0c:	e0bff517 	ldw	r2,-44(fp)
+ 8013c10:	00c00fc4 	movi	r3,63
+ 8013c14:	10c00385 	stb	r3,14(r2)
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8013c18:	e0bff517 	ldw	r2,-44(fp)
+ 8013c1c:	100003c5 	stb	zero,15(r2)
+#endif
+             pip                 = (INT8U)(pevent->OSEventCnt >> 8);
+ 8013c20:	e0bff517 	ldw	r2,-44(fp)
+ 8013c24:	1080020b 	ldhu	r2,8(r2)
+ 8013c28:	10bfffcc 	andi	r2,r2,65535
+ 8013c2c:	1004d23a 	srli	r2,r2,8
+ 8013c30:	e0bffcc5 	stb	r2,-13(fp)
+             OSTCBPrioTbl[pip]   = (OS_TCB *)0;            /* Free up the PIP                          */
+ 8013c34:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8013c38:	100690ba 	slli	r3,r2,2
+ 8013c3c:	008201b4 	movhi	r2,2054
+ 8013c40:	1885883a 	add	r2,r3,r2
+ 8013c44:	10355d15 	stw	zero,-10892(r2)
+             pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+ 8013c48:	e0bff517 	ldw	r2,-44(fp)
+ 8013c4c:	10000005 	stb	zero,0(r2)
+             pevent->OSEventPtr  = OSEventFreeList;        /* Return Event Control Block to free list  */
+ 8013c50:	d0e05617 	ldw	r3,-32424(gp)
+ 8013c54:	e0bff517 	ldw	r2,-44(fp)
+ 8013c58:	10c00115 	stw	r3,4(r2)
+             pevent->OSEventCnt  = 0;
+ 8013c5c:	e0bff517 	ldw	r2,-44(fp)
+ 8013c60:	1000020d 	sth	zero,8(r2)
+             OSEventFreeList     = pevent;                 /* Get next free event control block        */
+ 8013c64:	e0bff517 	ldw	r2,-44(fp)
+ 8013c68:	d0a05615 	stw	r2,-32424(gp)
+ 8013c6c:	e0bffd17 	ldw	r2,-12(fp)
+ 8013c70:	e0bff715 	stw	r2,-36(fp)
+ 8013c74:	e0bff717 	ldw	r2,-36(fp)
+ 8013c78:	1001703a 	wrctl	status,r2
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+ 8013c7c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8013c80:	10800058 	cmpnei	r2,r2,1
+ 8013c84:	1000011e 	bne	r2,zero,8013c8c <OSMutexDel+0x270>
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+ 8013c88:	801166c0 	call	801166c <OS_Sched>
+             }
+             *perr         = OS_ERR_NONE;
+ 8013c8c:	e0bff317 	ldw	r2,-52(fp)
+ 8013c90:	10000005 	stb	zero,0(r2)
+             pevent_return = (OS_EVENT *)0;                /* Mutex has been deleted                   */
+ 8013c94:	e03ffe15 	stw	zero,-8(fp)
+             break;
+ 8013c98:	00000a06 	br	8013cc4 <OSMutexDel+0x2a8>
+ 8013c9c:	e0bffd17 	ldw	r2,-12(fp)
+ 8013ca0:	e0bff615 	stw	r2,-40(fp)
+ 8013ca4:	e0bff617 	ldw	r2,-40(fp)
+ 8013ca8:	1001703a 	wrctl	status,r2
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr         = OS_ERR_INVALID_OPT;
+ 8013cac:	e0bff317 	ldw	r2,-52(fp)
+ 8013cb0:	00c001c4 	movi	r3,7
+ 8013cb4:	10c00005 	stb	r3,0(r2)
+             pevent_return = pevent;
+ 8013cb8:	e0bff517 	ldw	r2,-44(fp)
+ 8013cbc:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8013cc0:	0001883a 	nop
+    }
+    return (pevent_return);
+ 8013cc4:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8013cc8:	e037883a 	mov	sp,fp
+ 8013ccc:	dfc00117 	ldw	ra,4(sp)
+ 8013cd0:	df000017 	ldw	fp,0(sp)
+ 8013cd4:	dec00204 	addi	sp,sp,8
+ 8013cd8:	f800283a 	ret
+
+08013cdc <OSMutexPend>:
+*              2) You MUST NOT change the priority of the task that owns the mutex
+*********************************************************************************************************
+*/
+
+void  OSMutexPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+ 8013cdc:	deffef04 	addi	sp,sp,-68
+ 8013ce0:	dfc01015 	stw	ra,64(sp)
+ 8013ce4:	df000f15 	stw	fp,60(sp)
+ 8013ce8:	df000f04 	addi	fp,sp,60
+ 8013cec:	e13ff315 	stw	r4,-52(fp)
+ 8013cf0:	2805883a 	mov	r2,r5
+ 8013cf4:	e1bff115 	stw	r6,-60(fp)
+ 8013cf8:	e0bff20d 	sth	r2,-56(fp)
+    BOOLEAN    rdy;                                        /* Flag indicating task was ready           */
+    OS_TCB    *ptcb;
+    OS_EVENT  *pevent2;
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 8013cfc:	e03ffe15 	stw	zero,-8(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+ 8013d00:	e0bff317 	ldw	r2,-52(fp)
+ 8013d04:	10800003 	ldbu	r2,0(r2)
+ 8013d08:	10803fcc 	andi	r2,r2,255
+ 8013d0c:	10800120 	cmpeqi	r2,r2,4
+ 8013d10:	1000041e 	bne	r2,zero,8013d24 <OSMutexPend+0x48>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8013d14:	e0bff117 	ldw	r2,-60(fp)
+ 8013d18:	00c00044 	movi	r3,1
+ 8013d1c:	10c00005 	stb	r3,0(r2)
+        return;
+ 8013d20:	00014006 	br	8014224 <OSMutexPend+0x548>
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8013d24:	d0a05703 	ldbu	r2,-32420(gp)
+ 8013d28:	10803fcc 	andi	r2,r2,255
+ 8013d2c:	10000426 	beq	r2,zero,8013d40 <OSMutexPend+0x64>
+        *perr = OS_ERR_PEND_ISR;                           /* ... can't PEND from an ISR               */
+ 8013d30:	e0bff117 	ldw	r2,-60(fp)
+ 8013d34:	00c00084 	movi	r3,2
+ 8013d38:	10c00005 	stb	r3,0(r2)
+        return;
+ 8013d3c:	00013906 	br	8014224 <OSMutexPend+0x548>
+    }
+    if (OSLockNesting > 0) {                               /* See if called with scheduler locked ...  */
+ 8013d40:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8013d44:	10803fcc 	andi	r2,r2,255
+ 8013d48:	10000426 	beq	r2,zero,8013d5c <OSMutexPend+0x80>
+        *perr = OS_ERR_PEND_LOCKED;                        /* ... can't PEND when locked               */
+ 8013d4c:	e0bff117 	ldw	r2,-60(fp)
+ 8013d50:	00c00344 	movi	r3,13
+ 8013d54:	10c00005 	stb	r3,0(r2)
+        return;
+ 8013d58:	00013206 	br	8014224 <OSMutexPend+0x548>
+  NIOS2_READ_STATUS (context);
+ 8013d5c:	0005303a 	rdctl	r2,status
+ 8013d60:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8013d64:	e0fff917 	ldw	r3,-28(fp)
+ 8013d68:	00bfff84 	movi	r2,-2
+ 8013d6c:	1884703a 	and	r2,r3,r2
+ 8013d70:	1001703a 	wrctl	status,r2
+  return context;
+ 8013d74:	e0bff917 	ldw	r2,-28(fp)
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+ 8013d78:	e0bffe15 	stw	r2,-8(fp)
+    pip = (INT8U)(pevent->OSEventCnt >> 8);                /* Get PIP from mutex                       */
+ 8013d7c:	e0bff317 	ldw	r2,-52(fp)
+ 8013d80:	1080020b 	ldhu	r2,8(r2)
+ 8013d84:	10bfffcc 	andi	r2,r2,65535
+ 8013d88:	1004d23a 	srli	r2,r2,8
+ 8013d8c:	e0bffdc5 	stb	r2,-9(fp)
+                                                           /* Is Mutex available?                      */
+    if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+ 8013d90:	e0bff317 	ldw	r2,-52(fp)
+ 8013d94:	1080020b 	ldhu	r2,8(r2)
+ 8013d98:	10803fcc 	andi	r2,r2,255
+ 8013d9c:	10803fd8 	cmpnei	r2,r2,255
+ 8013da0:	1000271e 	bne	r2,zero,8013e40 <OSMutexPend+0x164>
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;       /* Yes, Acquire the resource                */
+ 8013da4:	e0bff317 	ldw	r2,-52(fp)
+ 8013da8:	10c0020b 	ldhu	r3,8(r2)
+ 8013dac:	00bfc004 	movi	r2,-256
+ 8013db0:	1884703a 	and	r2,r3,r2
+ 8013db4:	1007883a 	mov	r3,r2
+ 8013db8:	e0bff317 	ldw	r2,-52(fp)
+ 8013dbc:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventCnt |= OSTCBCur->OSTCBPrio;         /*      Save priority of owning task        */
+ 8013dc0:	e0bff317 	ldw	r2,-52(fp)
+ 8013dc4:	10c0020b 	ldhu	r3,8(r2)
+ 8013dc8:	d0a05817 	ldw	r2,-32416(gp)
+ 8013dcc:	10800c83 	ldbu	r2,50(r2)
+ 8013dd0:	10803fcc 	andi	r2,r2,255
+ 8013dd4:	1884b03a 	or	r2,r3,r2
+ 8013dd8:	1007883a 	mov	r3,r2
+ 8013ddc:	e0bff317 	ldw	r2,-52(fp)
+ 8013de0:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventPtr  = (void *)OSTCBCur;            /*      Point to owning task's OS_TCB       */
+ 8013de4:	d0e05817 	ldw	r3,-32416(gp)
+ 8013de8:	e0bff317 	ldw	r2,-52(fp)
+ 8013dec:	10c00115 	stw	r3,4(r2)
+        if (OSTCBCur->OSTCBPrio <= pip) {                  /*      PIP 'must' have a SMALLER prio ...  */
+ 8013df0:	d0a05817 	ldw	r2,-32416(gp)
+ 8013df4:	10800c83 	ldbu	r2,50(r2)
+ 8013df8:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8013dfc:	10803fcc 	andi	r2,r2,255
+ 8013e00:	18800836 	bltu	r3,r2,8013e24 <OSMutexPend+0x148>
+ 8013e04:	e0bffe17 	ldw	r2,-8(fp)
+ 8013e08:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8013e0c:	e0bff817 	ldw	r2,-32(fp)
+ 8013e10:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();                            /*      ... than current task!              */
+            *perr = OS_ERR_PIP_LOWER;
+ 8013e14:	e0bff117 	ldw	r2,-60(fp)
+ 8013e18:	00c01e04 	movi	r3,120
+ 8013e1c:	10c00005 	stb	r3,0(r2)
+        } else {
+            OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+        }
+        return;
+ 8013e20:	00010006 	br	8014224 <OSMutexPend+0x548>
+ 8013e24:	e0bffe17 	ldw	r2,-8(fp)
+ 8013e28:	e0bff715 	stw	r2,-36(fp)
+ 8013e2c:	e0bff717 	ldw	r2,-36(fp)
+ 8013e30:	1001703a 	wrctl	status,r2
+            *perr = OS_ERR_NONE;
+ 8013e34:	e0bff117 	ldw	r2,-60(fp)
+ 8013e38:	10000005 	stb	zero,0(r2)
+        return;
+ 8013e3c:	0000f906 	br	8014224 <OSMutexPend+0x548>
+    }
+    mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* No, Get priority of mutex owner   */
+ 8013e40:	e0bff317 	ldw	r2,-52(fp)
+ 8013e44:	1080020b 	ldhu	r2,8(r2)
+ 8013e48:	e0bffd85 	stb	r2,-10(fp)
+    ptcb  = (OS_TCB *)(pevent->OSEventPtr);                       /*     Point to TCB of mutex owner   */
+ 8013e4c:	e0bff317 	ldw	r2,-52(fp)
+ 8013e50:	10800117 	ldw	r2,4(r2)
+ 8013e54:	e0bffc15 	stw	r2,-16(fp)
+    if (ptcb->OSTCBPrio > pip) {                                  /*     Need to promote prio of owner?*/
+ 8013e58:	e0bffc17 	ldw	r2,-16(fp)
+ 8013e5c:	10800c83 	ldbu	r2,50(r2)
+ 8013e60:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8013e64:	10803fcc 	andi	r2,r2,255
+ 8013e68:	1880b32e 	bgeu	r3,r2,8014138 <OSMutexPend+0x45c>
+        if (mprio > OSTCBCur->OSTCBPrio) {
+ 8013e6c:	d0a05817 	ldw	r2,-32416(gp)
+ 8013e70:	10c00c83 	ldbu	r3,50(r2)
+ 8013e74:	e0bffd83 	ldbu	r2,-10(fp)
+ 8013e78:	18c03fcc 	andi	r3,r3,255
+ 8013e7c:	1880ae2e 	bgeu	r3,r2,8014138 <OSMutexPend+0x45c>
+            y = ptcb->OSTCBY;
+ 8013e80:	e0bffc17 	ldw	r2,-16(fp)
+ 8013e84:	10800d03 	ldbu	r2,52(r2)
+ 8013e88:	e0bffbc5 	stb	r2,-17(fp)
+            if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0) {           /*     See if mutex owner is ready   */
+ 8013e8c:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8013e90:	d0a05544 	addi	r2,gp,-32427
+ 8013e94:	1885883a 	add	r2,r3,r2
+ 8013e98:	10c00003 	ldbu	r3,0(r2)
+ 8013e9c:	e0bffc17 	ldw	r2,-16(fp)
+ 8013ea0:	10800d43 	ldbu	r2,53(r2)
+ 8013ea4:	1884703a 	and	r2,r3,r2
+ 8013ea8:	10803fcc 	andi	r2,r2,255
+ 8013eac:	10001e26 	beq	r2,zero,8013f28 <OSMutexPend+0x24c>
+                OSRdyTbl[y] &= ~ptcb->OSTCBBitX;                  /*     Yes, Remove owner from Rdy ...*/
+ 8013eb0:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8013eb4:	d0a05544 	addi	r2,gp,-32427
+ 8013eb8:	1885883a 	add	r2,r3,r2
+ 8013ebc:	10800003 	ldbu	r2,0(r2)
+ 8013ec0:	1007883a 	mov	r3,r2
+ 8013ec4:	e0bffc17 	ldw	r2,-16(fp)
+ 8013ec8:	10800d43 	ldbu	r2,53(r2)
+ 8013ecc:	0084303a 	nor	r2,zero,r2
+ 8013ed0:	1884703a 	and	r2,r3,r2
+ 8013ed4:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8013ed8:	1009883a 	mov	r4,r2
+ 8013edc:	d0a05544 	addi	r2,gp,-32427
+ 8013ee0:	1885883a 	add	r2,r3,r2
+ 8013ee4:	11000005 	stb	r4,0(r2)
+                if (OSRdyTbl[y] == 0) {                           /*          ... list at current prio */
+ 8013ee8:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8013eec:	d0a05544 	addi	r2,gp,-32427
+ 8013ef0:	1885883a 	add	r2,r3,r2
+ 8013ef4:	10800003 	ldbu	r2,0(r2)
+ 8013ef8:	10803fcc 	andi	r2,r2,255
+ 8013efc:	1000071e 	bne	r2,zero,8013f1c <OSMutexPend+0x240>
+                    OSRdyGrp &= ~ptcb->OSTCBBitY;
+ 8013f00:	e0bffc17 	ldw	r2,-16(fp)
+ 8013f04:	10800d83 	ldbu	r2,54(r2)
+ 8013f08:	0084303a 	nor	r2,zero,r2
+ 8013f0c:	1007883a 	mov	r3,r2
+ 8013f10:	d0a05503 	ldbu	r2,-32428(gp)
+ 8013f14:	1884703a 	and	r2,r3,r2
+ 8013f18:	d0a05505 	stb	r2,-32428(gp)
+                }
+                rdy = OS_TRUE;
+ 8013f1c:	00800044 	movi	r2,1
+ 8013f20:	e0bfffc5 	stb	r2,-1(fp)
+ 8013f24:	00002806 	br	8013fc8 <OSMutexPend+0x2ec>
+            } else {
+                pevent2 = ptcb->OSTCBEventPtr;
+ 8013f28:	e0bffc17 	ldw	r2,-16(fp)
+ 8013f2c:	10800717 	ldw	r2,28(r2)
+ 8013f30:	e0bffa15 	stw	r2,-24(fp)
+                if (pevent2 != (OS_EVENT *)0) {                   /* Remove from event wait list       */
+ 8013f34:	e0bffa17 	ldw	r2,-24(fp)
+ 8013f38:	10002226 	beq	r2,zero,8013fc4 <OSMutexPend+0x2e8>
+                    if ((pevent2->OSEventTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX) == 0) {
+ 8013f3c:	e0bffc17 	ldw	r2,-16(fp)
+ 8013f40:	10800d03 	ldbu	r2,52(r2)
+ 8013f44:	10803fcc 	andi	r2,r2,255
+ 8013f48:	e0fffa17 	ldw	r3,-24(fp)
+ 8013f4c:	1885883a 	add	r2,r3,r2
+ 8013f50:	108002c3 	ldbu	r2,11(r2)
+ 8013f54:	1007883a 	mov	r3,r2
+ 8013f58:	e0bffc17 	ldw	r2,-16(fp)
+ 8013f5c:	10800d43 	ldbu	r2,53(r2)
+ 8013f60:	0084303a 	nor	r2,zero,r2
+ 8013f64:	1884703a 	and	r2,r3,r2
+ 8013f68:	1007883a 	mov	r3,r2
+ 8013f6c:	e0bffc17 	ldw	r2,-16(fp)
+ 8013f70:	10800d03 	ldbu	r2,52(r2)
+ 8013f74:	10803fcc 	andi	r2,r2,255
+ 8013f78:	1809883a 	mov	r4,r3
+ 8013f7c:	e0fffa17 	ldw	r3,-24(fp)
+ 8013f80:	1887883a 	add	r3,r3,r2
+ 8013f84:	190002c5 	stb	r4,11(r3)
+ 8013f88:	e0fffa17 	ldw	r3,-24(fp)
+ 8013f8c:	1885883a 	add	r2,r3,r2
+ 8013f90:	108002c3 	ldbu	r2,11(r2)
+ 8013f94:	10803fcc 	andi	r2,r2,255
+ 8013f98:	10000a1e 	bne	r2,zero,8013fc4 <OSMutexPend+0x2e8>
+                        pevent2->OSEventGrp &= ~ptcb->OSTCBBitY;
+ 8013f9c:	e0bffa17 	ldw	r2,-24(fp)
+ 8013fa0:	10800283 	ldbu	r2,10(r2)
+ 8013fa4:	1007883a 	mov	r3,r2
+ 8013fa8:	e0bffc17 	ldw	r2,-16(fp)
+ 8013fac:	10800d83 	ldbu	r2,54(r2)
+ 8013fb0:	0084303a 	nor	r2,zero,r2
+ 8013fb4:	1884703a 	and	r2,r3,r2
+ 8013fb8:	1007883a 	mov	r3,r2
+ 8013fbc:	e0bffa17 	ldw	r2,-24(fp)
+ 8013fc0:	10c00285 	stb	r3,10(r2)
+                    }
+                }
+                rdy = OS_FALSE;                            /* No                                       */
+ 8013fc4:	e03fffc5 	stb	zero,-1(fp)
+            }
+            ptcb->OSTCBPrio = pip;                         /* Change owner task prio to PIP            */
+ 8013fc8:	e0bffc17 	ldw	r2,-16(fp)
+ 8013fcc:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8013fd0:	10c00c85 	stb	r3,50(r2)
+#if OS_LOWEST_PRIO <= 63
+            ptcb->OSTCBY    = (INT8U)( ptcb->OSTCBPrio >> 3);
+ 8013fd4:	e0bffc17 	ldw	r2,-16(fp)
+ 8013fd8:	10800c83 	ldbu	r2,50(r2)
+ 8013fdc:	10803fcc 	andi	r2,r2,255
+ 8013fe0:	1004d0fa 	srli	r2,r2,3
+ 8013fe4:	1007883a 	mov	r3,r2
+ 8013fe8:	e0bffc17 	ldw	r2,-16(fp)
+ 8013fec:	10c00d05 	stb	r3,52(r2)
+            ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x07);
+ 8013ff0:	e0bffc17 	ldw	r2,-16(fp)
+ 8013ff4:	10800c83 	ldbu	r2,50(r2)
+ 8013ff8:	108001cc 	andi	r2,r2,7
+ 8013ffc:	1007883a 	mov	r3,r2
+ 8014000:	e0bffc17 	ldw	r2,-16(fp)
+ 8014004:	10c00cc5 	stb	r3,51(r2)
+            ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY);
+ 8014008:	e0bffc17 	ldw	r2,-16(fp)
+ 801400c:	10800d03 	ldbu	r2,52(r2)
+ 8014010:	10803fcc 	andi	r2,r2,255
+ 8014014:	00c00044 	movi	r3,1
+ 8014018:	1884983a 	sll	r2,r3,r2
+ 801401c:	1007883a 	mov	r3,r2
+ 8014020:	e0bffc17 	ldw	r2,-16(fp)
+ 8014024:	10c00d85 	stb	r3,54(r2)
+            ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX);
+ 8014028:	e0bffc17 	ldw	r2,-16(fp)
+ 801402c:	10800cc3 	ldbu	r2,51(r2)
+ 8014030:	10803fcc 	andi	r2,r2,255
+ 8014034:	00c00044 	movi	r3,1
+ 8014038:	1884983a 	sll	r2,r3,r2
+ 801403c:	1007883a 	mov	r3,r2
+ 8014040:	e0bffc17 	ldw	r2,-16(fp)
+ 8014044:	10c00d45 	stb	r3,53(r2)
+            ptcb->OSTCBY    = (INT8U)((ptcb->OSTCBPrio >> 4) & 0xFF);
+            ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x0F);
+            ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY);
+            ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+            if (rdy == OS_TRUE) {                          /* If task was ready at owner's priority ...*/
+ 8014048:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801404c:	10800058 	cmpnei	r2,r2,1
+ 8014050:	1000161e 	bne	r2,zero,80140ac <OSMutexPend+0x3d0>
+                OSRdyGrp               |= ptcb->OSTCBBitY; /* ... make it ready at new priority.       */
+ 8014054:	e0bffc17 	ldw	r2,-16(fp)
+ 8014058:	10c00d83 	ldbu	r3,54(r2)
+ 801405c:	d0a05503 	ldbu	r2,-32428(gp)
+ 8014060:	1884b03a 	or	r2,r3,r2
+ 8014064:	d0a05505 	stb	r2,-32428(gp)
+                OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8014068:	e0bffc17 	ldw	r2,-16(fp)
+ 801406c:	10800d03 	ldbu	r2,52(r2)
+ 8014070:	10c03fcc 	andi	r3,r2,255
+ 8014074:	d0a05544 	addi	r2,gp,-32427
+ 8014078:	1885883a 	add	r2,r3,r2
+ 801407c:	11000003 	ldbu	r4,0(r2)
+ 8014080:	e0bffc17 	ldw	r2,-16(fp)
+ 8014084:	10800d43 	ldbu	r2,53(r2)
+ 8014088:	e0fffc17 	ldw	r3,-16(fp)
+ 801408c:	18c00d03 	ldbu	r3,52(r3)
+ 8014090:	18c03fcc 	andi	r3,r3,255
+ 8014094:	2084b03a 	or	r2,r4,r2
+ 8014098:	1009883a 	mov	r4,r2
+ 801409c:	d0a05544 	addi	r2,gp,-32427
+ 80140a0:	1885883a 	add	r2,r3,r2
+ 80140a4:	11000005 	stb	r4,0(r2)
+ 80140a8:	00001d06 	br	8014120 <OSMutexPend+0x444>
+            } else {
+                pevent2 = ptcb->OSTCBEventPtr;
+ 80140ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80140b0:	10800717 	ldw	r2,28(r2)
+ 80140b4:	e0bffa15 	stw	r2,-24(fp)
+                if (pevent2 != (OS_EVENT *)0) {            /* Add to event wait list                   */
+ 80140b8:	e0bffa17 	ldw	r2,-24(fp)
+ 80140bc:	10001826 	beq	r2,zero,8014120 <OSMutexPend+0x444>
+                    pevent2->OSEventGrp               |= ptcb->OSTCBBitY;
+ 80140c0:	e0bffa17 	ldw	r2,-24(fp)
+ 80140c4:	10c00283 	ldbu	r3,10(r2)
+ 80140c8:	e0bffc17 	ldw	r2,-16(fp)
+ 80140cc:	10800d83 	ldbu	r2,54(r2)
+ 80140d0:	1884b03a 	or	r2,r3,r2
+ 80140d4:	1007883a 	mov	r3,r2
+ 80140d8:	e0bffa17 	ldw	r2,-24(fp)
+ 80140dc:	10c00285 	stb	r3,10(r2)
+                    pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 80140e0:	e0bffc17 	ldw	r2,-16(fp)
+ 80140e4:	10800d03 	ldbu	r2,52(r2)
+ 80140e8:	10803fcc 	andi	r2,r2,255
+ 80140ec:	e0fffa17 	ldw	r3,-24(fp)
+ 80140f0:	1885883a 	add	r2,r3,r2
+ 80140f4:	110002c3 	ldbu	r4,11(r2)
+ 80140f8:	e0bffc17 	ldw	r2,-16(fp)
+ 80140fc:	10c00d43 	ldbu	r3,53(r2)
+ 8014100:	e0bffc17 	ldw	r2,-16(fp)
+ 8014104:	10800d03 	ldbu	r2,52(r2)
+ 8014108:	10803fcc 	andi	r2,r2,255
+ 801410c:	20c6b03a 	or	r3,r4,r3
+ 8014110:	1809883a 	mov	r4,r3
+ 8014114:	e0fffa17 	ldw	r3,-24(fp)
+ 8014118:	1885883a 	add	r2,r3,r2
+ 801411c:	110002c5 	stb	r4,11(r2)
+                }
+            }
+            OSTCBPrioTbl[pip] = ptcb;
+ 8014120:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8014124:	100890ba 	slli	r4,r2,2
+ 8014128:	e0fffc17 	ldw	r3,-16(fp)
+ 801412c:	008201b4 	movhi	r2,2054
+ 8014130:	2085883a 	add	r2,r4,r2
+ 8014134:	10f55d15 	stw	r3,-10892(r2)
+        }
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_MUTEX;         /* Mutex not available, pend current task        */
+ 8014138:	d0a05817 	ldw	r2,-32416(gp)
+ 801413c:	10c00c03 	ldbu	r3,48(r2)
+ 8014140:	d0a05817 	ldw	r2,-32416(gp)
+ 8014144:	18c00414 	ori	r3,r3,16
+ 8014148:	10c00c05 	stb	r3,48(r2)
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 801414c:	d0a05817 	ldw	r2,-32416(gp)
+ 8014150:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBDly       = timeout;               /* Store timeout in current task's TCB           */
+ 8014154:	d0a05817 	ldw	r2,-32416(gp)
+ 8014158:	e0fff20b 	ldhu	r3,-56(fp)
+ 801415c:	10c00b8d 	sth	r3,46(r2)
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+ 8014160:	e13ff317 	ldw	r4,-52(fp)
+ 8014164:	8010e600 	call	8010e60 <OS_EventTaskWait>
+ 8014168:	e0bffe17 	ldw	r2,-8(fp)
+ 801416c:	e0bff515 	stw	r2,-44(fp)
+ 8014170:	e0bff517 	ldw	r2,-44(fp)
+ 8014174:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+ 8014178:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 801417c:	0005303a 	rdctl	r2,status
+ 8014180:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014184:	e0fff617 	ldw	r3,-40(fp)
+ 8014188:	00bfff84 	movi	r2,-2
+ 801418c:	1884703a 	and	r2,r3,r2
+ 8014190:	1001703a 	wrctl	status,r2
+  return context;
+ 8014194:	e0bff617 	ldw	r2,-40(fp)
+    OS_ENTER_CRITICAL();
+ 8014198:	e0bffe15 	stw	r2,-8(fp)
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+ 801419c:	d0a05817 	ldw	r2,-32416(gp)
+ 80141a0:	10800c43 	ldbu	r2,49(r2)
+ 80141a4:	10803fcc 	andi	r2,r2,255
+ 80141a8:	10000326 	beq	r2,zero,80141b8 <OSMutexPend+0x4dc>
+ 80141ac:	108000a0 	cmpeqi	r2,r2,2
+ 80141b0:	1000041e 	bne	r2,zero,80141c4 <OSMutexPend+0x4e8>
+ 80141b4:	00000706 	br	80141d4 <OSMutexPend+0x4f8>
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+ 80141b8:	e0bff117 	ldw	r2,-60(fp)
+ 80141bc:	10000005 	stb	zero,0(r2)
+             break;
+ 80141c0:	00000c06 	br	80141f4 <OSMutexPend+0x518>
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted getting mutex        */
+ 80141c4:	e0bff117 	ldw	r2,-60(fp)
+ 80141c8:	00c00384 	movi	r3,14
+ 80141cc:	10c00005 	stb	r3,0(r2)
+             break;
+ 80141d0:	00000806 	br	80141f4 <OSMutexPend+0x518>
+             
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+ 80141d4:	d0a05817 	ldw	r2,-32416(gp)
+ 80141d8:	e17ff317 	ldw	r5,-52(fp)
+ 80141dc:	1009883a 	mov	r4,r2
+ 80141e0:	80110b00 	call	80110b0 <OS_EventTaskRemove>
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get mutex within TO   */
+ 80141e4:	e0bff117 	ldw	r2,-60(fp)
+ 80141e8:	00c00284 	movi	r3,10
+ 80141ec:	10c00005 	stb	r3,0(r2)
+             break;
+ 80141f0:	0001883a 	nop
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+ 80141f4:	d0a05817 	ldw	r2,-32416(gp)
+ 80141f8:	10000c05 	stb	zero,48(r2)
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+ 80141fc:	d0a05817 	ldw	r2,-32416(gp)
+ 8014200:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+ 8014204:	d0a05817 	ldw	r2,-32416(gp)
+ 8014208:	10000715 	stw	zero,28(r2)
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+ 801420c:	d0a05817 	ldw	r2,-32416(gp)
+ 8014210:	10000815 	stw	zero,32(r2)
+ 8014214:	e0bffe17 	ldw	r2,-8(fp)
+ 8014218:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801421c:	e0bff417 	ldw	r2,-48(fp)
+ 8014220:	1001703a 	wrctl	status,r2
+#endif
+    OS_EXIT_CRITICAL();
+}
+ 8014224:	e037883a 	mov	sp,fp
+ 8014228:	dfc00117 	ldw	ra,4(sp)
+ 801422c:	df000017 	ldw	fp,0(sp)
+ 8014230:	dec00204 	addi	sp,sp,8
+ 8014234:	f800283a 	ret
+
+08014238 <OSMutexPost>:
+*                                      what tasks will be using the Mutex.
+*********************************************************************************************************
+*/
+
+INT8U  OSMutexPost (OS_EVENT *pevent)
+{
+ 8014238:	defff604 	addi	sp,sp,-40
+ 801423c:	dfc00915 	stw	ra,36(sp)
+ 8014240:	df000815 	stw	fp,32(sp)
+ 8014244:	df000804 	addi	fp,sp,32
+ 8014248:	e13ff815 	stw	r4,-32(fp)
+    INT8U      pip;                                   /* Priority inheritance priority                 */
+    INT8U      prio;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 801424c:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                           /* See if called from ISR ...                    */
+ 8014250:	d0a05703 	ldbu	r2,-32420(gp)
+ 8014254:	10803fcc 	andi	r2,r2,255
+ 8014258:	10000226 	beq	r2,zero,8014264 <OSMutexPost+0x2c>
+        return (OS_ERR_POST_ISR);                     /* ... can't POST mutex from an ISR              */
+ 801425c:	00800144 	movi	r2,5
+ 8014260:	00006e06 	br	801441c <OSMutexPost+0x1e4>
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type                     */
+ 8014264:	e0bff817 	ldw	r2,-32(fp)
+ 8014268:	10800003 	ldbu	r2,0(r2)
+ 801426c:	10803fcc 	andi	r2,r2,255
+ 8014270:	10800120 	cmpeqi	r2,r2,4
+ 8014274:	1000021e 	bne	r2,zero,8014280 <OSMutexPost+0x48>
+        return (OS_ERR_EVENT_TYPE);
+ 8014278:	00800044 	movi	r2,1
+ 801427c:	00006706 	br	801441c <OSMutexPost+0x1e4>
+  NIOS2_READ_STATUS (context);
+ 8014280:	0005303a 	rdctl	r2,status
+ 8014284:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014288:	e0fffd17 	ldw	r3,-12(fp)
+ 801428c:	00bfff84 	movi	r2,-2
+ 8014290:	1884703a 	and	r2,r3,r2
+ 8014294:	1001703a 	wrctl	status,r2
+  return context;
+ 8014298:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 801429c:	e0bfff15 	stw	r2,-4(fp)
+    pip  = (INT8U)(pevent->OSEventCnt >> 8);          /* Get priority inheritance priority of mutex    */
+ 80142a0:	e0bff817 	ldw	r2,-32(fp)
+ 80142a4:	1080020b 	ldhu	r2,8(r2)
+ 80142a8:	10bfffcc 	andi	r2,r2,65535
+ 80142ac:	1004d23a 	srli	r2,r2,8
+ 80142b0:	e0bffec5 	stb	r2,-5(fp)
+    prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* Get owner's original priority      */
+ 80142b4:	e0bff817 	ldw	r2,-32(fp)
+ 80142b8:	1080020b 	ldhu	r2,8(r2)
+ 80142bc:	e0bffe85 	stb	r2,-6(fp)
+    if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) {   /* See if posting task owns the MUTEX            */
+ 80142c0:	e0bff817 	ldw	r2,-32(fp)
+ 80142c4:	10c00117 	ldw	r3,4(r2)
+ 80142c8:	d0a05817 	ldw	r2,-32416(gp)
+ 80142cc:	18800626 	beq	r3,r2,80142e8 <OSMutexPost+0xb0>
+ 80142d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80142d4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80142d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80142dc:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NOT_MUTEX_OWNER);
+ 80142e0:	00801904 	movi	r2,100
+ 80142e4:	00004d06 	br	801441c <OSMutexPost+0x1e4>
+    }
+    if (OSTCBCur->OSTCBPrio == pip) {                 /* Did we have to raise current task's priority? */
+ 80142e8:	d0a05817 	ldw	r2,-32416(gp)
+ 80142ec:	10800c83 	ldbu	r2,50(r2)
+ 80142f0:	e0fffec3 	ldbu	r3,-5(fp)
+ 80142f4:	10803fcc 	andi	r2,r2,255
+ 80142f8:	1880051e 	bne	r3,r2,8014310 <OSMutexPost+0xd8>
+        OSMutex_RdyAtPrio(OSTCBCur, prio);            /* Restore the task's original priority          */
+ 80142fc:	d0a05817 	ldw	r2,-32416(gp)
+ 8014300:	e0fffe83 	ldbu	r3,-6(fp)
+ 8014304:	180b883a 	mov	r5,r3
+ 8014308:	1009883a 	mov	r4,r2
+ 801430c:	801457c0 	call	801457c <OSMutex_RdyAtPrio>
+    }
+    OSTCBPrioTbl[pip] = OS_TCB_RESERVED;              /* Reserve table entry                           */
+ 8014310:	e0bffec3 	ldbu	r2,-5(fp)
+ 8014314:	100890ba 	slli	r4,r2,2
+ 8014318:	00c00044 	movi	r3,1
+ 801431c:	008201b4 	movhi	r2,2054
+ 8014320:	2085883a 	add	r2,r4,r2
+ 8014324:	10f55d15 	stw	r3,-10892(r2)
+    if (pevent->OSEventGrp != 0) {                    /* Any task waiting for the mutex?               */
+ 8014328:	e0bff817 	ldw	r2,-32(fp)
+ 801432c:	10800283 	ldbu	r2,10(r2)
+ 8014330:	10803fcc 	andi	r2,r2,255
+ 8014334:	10002c26 	beq	r2,zero,80143e8 <OSMutexPost+0x1b0>
+                                                      /* Yes, Make HPT waiting for mutex ready         */
+        prio                = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK);
+ 8014338:	000f883a 	mov	r7,zero
+ 801433c:	01800404 	movi	r6,16
+ 8014340:	000b883a 	mov	r5,zero
+ 8014344:	e13ff817 	ldw	r4,-32(fp)
+ 8014348:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+ 801434c:	e0bffe85 	stb	r2,-6(fp)
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;  /*      Save priority of mutex's new owner       */
+ 8014350:	e0bff817 	ldw	r2,-32(fp)
+ 8014354:	10c0020b 	ldhu	r3,8(r2)
+ 8014358:	00bfc004 	movi	r2,-256
+ 801435c:	1884703a 	and	r2,r3,r2
+ 8014360:	1007883a 	mov	r3,r2
+ 8014364:	e0bff817 	ldw	r2,-32(fp)
+ 8014368:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventCnt |= prio;
+ 801436c:	e0bff817 	ldw	r2,-32(fp)
+ 8014370:	10c0020b 	ldhu	r3,8(r2)
+ 8014374:	e0bffe83 	ldbu	r2,-6(fp)
+ 8014378:	1884b03a 	or	r2,r3,r2
+ 801437c:	1007883a 	mov	r3,r2
+ 8014380:	e0bff817 	ldw	r2,-32(fp)
+ 8014384:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventPtr  = OSTCBPrioTbl[prio];     /*      Link to new mutex owner's OS_TCB         */
+ 8014388:	e0bffe83 	ldbu	r2,-6(fp)
+ 801438c:	100690ba 	slli	r3,r2,2
+ 8014390:	008201b4 	movhi	r2,2054
+ 8014394:	1885883a 	add	r2,r3,r2
+ 8014398:	10f55d17 	ldw	r3,-10892(r2)
+ 801439c:	e0bff817 	ldw	r2,-32(fp)
+ 80143a0:	10c00115 	stw	r3,4(r2)
+        if (prio <= pip) {                            /*      PIP 'must' have a SMALLER prio ...       */
+ 80143a4:	e0bffe83 	ldbu	r2,-6(fp)
+ 80143a8:	e0fffec3 	ldbu	r3,-5(fp)
+ 80143ac:	18800736 	bltu	r3,r2,80143cc <OSMutexPost+0x194>
+ 80143b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80143b4:	e0bffb15 	stw	r2,-20(fp)
+ 80143b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80143bc:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();                       /*      ... than current task!                   */
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+ 80143c0:	801166c0 	call	801166c <OS_Sched>
+            return (OS_ERR_PIP_LOWER);
+ 80143c4:	00801e04 	movi	r2,120
+ 80143c8:	00001406 	br	801441c <OSMutexPost+0x1e4>
+ 80143cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80143d0:	e0bffa15 	stw	r2,-24(fp)
+ 80143d4:	e0bffa17 	ldw	r2,-24(fp)
+ 80143d8:	1001703a 	wrctl	status,r2
+        } else {
+            OS_EXIT_CRITICAL();
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+ 80143dc:	801166c0 	call	801166c <OS_Sched>
+            return (OS_ERR_NONE);
+ 80143e0:	0005883a 	mov	r2,zero
+ 80143e4:	00000d06 	br	801441c <OSMutexPost+0x1e4>
+        }
+    }
+    pevent->OSEventCnt |= OS_MUTEX_AVAILABLE;         /* No,  Mutex is now available                   */
+ 80143e8:	e0bff817 	ldw	r2,-32(fp)
+ 80143ec:	1080020b 	ldhu	r2,8(r2)
+ 80143f0:	10803fd4 	ori	r2,r2,255
+ 80143f4:	1007883a 	mov	r3,r2
+ 80143f8:	e0bff817 	ldw	r2,-32(fp)
+ 80143fc:	10c0020d 	sth	r3,8(r2)
+    pevent->OSEventPtr  = (void *)0;
+ 8014400:	e0bff817 	ldw	r2,-32(fp)
+ 8014404:	10000115 	stw	zero,4(r2)
+ 8014408:	e0bfff17 	ldw	r2,-4(fp)
+ 801440c:	e0bff915 	stw	r2,-28(fp)
+ 8014410:	e0bff917 	ldw	r2,-28(fp)
+ 8014414:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8014418:	0005883a 	mov	r2,zero
+}
+ 801441c:	e037883a 	mov	sp,fp
+ 8014420:	dfc00117 	ldw	ra,4(sp)
+ 8014424:	df000017 	ldw	fp,0(sp)
+ 8014428:	dec00204 	addi	sp,sp,8
+ 801442c:	f800283a 	ret
+
+08014430 <OSMutexQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_QUERY_EN > 0
+INT8U  OSMutexQuery (OS_EVENT *pevent, OS_MUTEX_DATA *p_mutex_data)
+{
+ 8014430:	defff704 	addi	sp,sp,-36
+ 8014434:	df000815 	stw	fp,32(sp)
+ 8014438:	df000804 	addi	fp,sp,32
+ 801443c:	e13ff915 	stw	r4,-28(fp)
+ 8014440:	e17ff815 	stw	r5,-32(fp)
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014444:	e03ffc15 	stw	zero,-16(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8014448:	d0a05703 	ldbu	r2,-32420(gp)
+ 801444c:	10803fcc 	andi	r2,r2,255
+ 8014450:	10000226 	beq	r2,zero,801445c <OSMutexQuery+0x2c>
+        return (OS_ERR_QUERY_ISR);                         /* ... can't QUERY mutex from an ISR        */
+ 8014454:	00800184 	movi	r2,6
+ 8014458:	00004406 	br	801456c <OSMutexQuery+0x13c>
+    }
+    if (p_mutex_data == (OS_MUTEX_DATA *)0) {              /* Validate 'p_mutex_data'                  */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+ 801445c:	e0bff917 	ldw	r2,-28(fp)
+ 8014460:	10800003 	ldbu	r2,0(r2)
+ 8014464:	10803fcc 	andi	r2,r2,255
+ 8014468:	10800120 	cmpeqi	r2,r2,4
+ 801446c:	1000021e 	bne	r2,zero,8014478 <OSMutexQuery+0x48>
+        return (OS_ERR_EVENT_TYPE);
+ 8014470:	00800044 	movi	r2,1
+ 8014474:	00003d06 	br	801456c <OSMutexQuery+0x13c>
+  NIOS2_READ_STATUS (context);
+ 8014478:	0005303a 	rdctl	r2,status
+ 801447c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014480:	e0fffb17 	ldw	r3,-20(fp)
+ 8014484:	00bfff84 	movi	r2,-2
+ 8014488:	1884703a 	and	r2,r3,r2
+ 801448c:	1001703a 	wrctl	status,r2
+  return context;
+ 8014490:	e0bffb17 	ldw	r2,-20(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014494:	e0bffc15 	stw	r2,-16(fp)
+    p_mutex_data->OSMutexPIP  = (INT8U)(pevent->OSEventCnt >> 8);
+ 8014498:	e0bff917 	ldw	r2,-28(fp)
+ 801449c:	1080020b 	ldhu	r2,8(r2)
+ 80144a0:	10bfffcc 	andi	r2,r2,65535
+ 80144a4:	1004d23a 	srli	r2,r2,8
+ 80144a8:	1007883a 	mov	r3,r2
+ 80144ac:	e0bff817 	ldw	r2,-32(fp)
+ 80144b0:	10c00185 	stb	r3,6(r2)
+    p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);
+ 80144b4:	e0bff917 	ldw	r2,-28(fp)
+ 80144b8:	1080020b 	ldhu	r2,8(r2)
+ 80144bc:	1007883a 	mov	r3,r2
+ 80144c0:	e0bff817 	ldw	r2,-32(fp)
+ 80144c4:	10c00145 	stb	r3,5(r2)
+    if (p_mutex_data->OSOwnerPrio == 0xFF) {
+ 80144c8:	e0bff817 	ldw	r2,-32(fp)
+ 80144cc:	10800143 	ldbu	r2,5(r2)
+ 80144d0:	10803fcc 	andi	r2,r2,255
+ 80144d4:	10803fd8 	cmpnei	r2,r2,255
+ 80144d8:	1000041e 	bne	r2,zero,80144ec <OSMutexQuery+0xbc>
+        p_mutex_data->OSValue = OS_TRUE;
+ 80144dc:	e0bff817 	ldw	r2,-32(fp)
+ 80144e0:	00c00044 	movi	r3,1
+ 80144e4:	10c00105 	stb	r3,4(r2)
+ 80144e8:	00000206 	br	80144f4 <OSMutexQuery+0xc4>
+    } else {
+        p_mutex_data->OSValue = OS_FALSE;
+ 80144ec:	e0bff817 	ldw	r2,-32(fp)
+ 80144f0:	10000105 	stb	zero,4(r2)
+    }
+    p_mutex_data->OSEventGrp  = pevent->OSEventGrp;        /* Copy wait list                           */
+ 80144f4:	e0bff917 	ldw	r2,-28(fp)
+ 80144f8:	10c00283 	ldbu	r3,10(r2)
+ 80144fc:	e0bff817 	ldw	r2,-32(fp)
+ 8014500:	10c000c5 	stb	r3,3(r2)
+    psrc                      = &pevent->OSEventTbl[0];
+ 8014504:	e0bff917 	ldw	r2,-28(fp)
+ 8014508:	108002c4 	addi	r2,r2,11
+ 801450c:	e0bffe15 	stw	r2,-8(fp)
+    pdest                     = &p_mutex_data->OSEventTbl[0];
+ 8014510:	e0bff817 	ldw	r2,-32(fp)
+ 8014514:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8014518:	e03fffc5 	stb	zero,-1(fp)
+ 801451c:	00000b06 	br	801454c <OSMutexQuery+0x11c>
+        *pdest++ = *psrc++;
+ 8014520:	e0fffe17 	ldw	r3,-8(fp)
+ 8014524:	18800044 	addi	r2,r3,1
+ 8014528:	e0bffe15 	stw	r2,-8(fp)
+ 801452c:	e0bffd17 	ldw	r2,-12(fp)
+ 8014530:	11000044 	addi	r4,r2,1
+ 8014534:	e13ffd15 	stw	r4,-12(fp)
+ 8014538:	18c00003 	ldbu	r3,0(r3)
+ 801453c:	10c00005 	stb	r3,0(r2)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8014540:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014544:	10800044 	addi	r2,r2,1
+ 8014548:	e0bfffc5 	stb	r2,-1(fp)
+ 801454c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014550:	108000f0 	cmpltui	r2,r2,3
+ 8014554:	103ff21e 	bne	r2,zero,8014520 <OSMutexQuery+0xf0>
+ 8014558:	e0bffc17 	ldw	r2,-16(fp)
+ 801455c:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014560:	e0bffa17 	ldw	r2,-24(fp)
+ 8014564:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8014568:	0005883a 	mov	r2,zero
+}
+ 801456c:	e037883a 	mov	sp,fp
+ 8014570:	df000017 	ldw	fp,0(sp)
+ 8014574:	dec00104 	addi	sp,sp,4
+ 8014578:	f800283a 	ret
+
+0801457c <OSMutex_RdyAtPrio>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OSMutex_RdyAtPrio (OS_TCB *ptcb, INT8U prio)
+{
+ 801457c:	defffc04 	addi	sp,sp,-16
+ 8014580:	df000315 	stw	fp,12(sp)
+ 8014584:	df000304 	addi	fp,sp,12
+ 8014588:	e13ffe15 	stw	r4,-8(fp)
+ 801458c:	2805883a 	mov	r2,r5
+ 8014590:	e0bffd05 	stb	r2,-12(fp)
+    INT8U   y;
+
+
+    y            =  ptcb->OSTCBY;                          /* Remove owner from ready list at 'pip'    */
+ 8014594:	e0bffe17 	ldw	r2,-8(fp)
+ 8014598:	10800d03 	ldbu	r2,52(r2)
+ 801459c:	e0bfffc5 	stb	r2,-1(fp)
+    OSRdyTbl[y] &= ~ptcb->OSTCBBitX;
+ 80145a0:	e0ffffc3 	ldbu	r3,-1(fp)
+ 80145a4:	d0a05544 	addi	r2,gp,-32427
+ 80145a8:	1885883a 	add	r2,r3,r2
+ 80145ac:	10800003 	ldbu	r2,0(r2)
+ 80145b0:	1007883a 	mov	r3,r2
+ 80145b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80145b8:	10800d43 	ldbu	r2,53(r2)
+ 80145bc:	0084303a 	nor	r2,zero,r2
+ 80145c0:	1884703a 	and	r2,r3,r2
+ 80145c4:	e0ffffc3 	ldbu	r3,-1(fp)
+ 80145c8:	1009883a 	mov	r4,r2
+ 80145cc:	d0a05544 	addi	r2,gp,-32427
+ 80145d0:	1885883a 	add	r2,r3,r2
+ 80145d4:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[y] == 0) {
+ 80145d8:	e0ffffc3 	ldbu	r3,-1(fp)
+ 80145dc:	d0a05544 	addi	r2,gp,-32427
+ 80145e0:	1885883a 	add	r2,r3,r2
+ 80145e4:	10800003 	ldbu	r2,0(r2)
+ 80145e8:	10803fcc 	andi	r2,r2,255
+ 80145ec:	1000071e 	bne	r2,zero,801460c <OSMutex_RdyAtPrio+0x90>
+        OSRdyGrp &= ~ptcb->OSTCBBitY;
+ 80145f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80145f4:	10800d83 	ldbu	r2,54(r2)
+ 80145f8:	0084303a 	nor	r2,zero,r2
+ 80145fc:	1007883a 	mov	r3,r2
+ 8014600:	d0a05503 	ldbu	r2,-32428(gp)
+ 8014604:	1884703a 	and	r2,r3,r2
+ 8014608:	d0a05505 	stb	r2,-32428(gp)
+    }
+    ptcb->OSTCBPrio         = prio;
+ 801460c:	e0bffe17 	ldw	r2,-8(fp)
+ 8014610:	e0fffd03 	ldbu	r3,-12(fp)
+ 8014614:	10c00c85 	stb	r3,50(r2)
+#if OS_LOWEST_PRIO <= 63
+    ptcb->OSTCBY            = (INT8U)((prio >> (INT8U)3) & (INT8U)0x07);
+ 8014618:	e0bffd03 	ldbu	r2,-12(fp)
+ 801461c:	1004d0fa 	srli	r2,r2,3
+ 8014620:	108001cc 	andi	r2,r2,7
+ 8014624:	1007883a 	mov	r3,r2
+ 8014628:	e0bffe17 	ldw	r2,-8(fp)
+ 801462c:	10c00d05 	stb	r3,52(r2)
+    ptcb->OSTCBX            = (INT8U) (prio & (INT8U)0x07);
+ 8014630:	e0bffd03 	ldbu	r2,-12(fp)
+ 8014634:	108001cc 	andi	r2,r2,7
+ 8014638:	1007883a 	mov	r3,r2
+ 801463c:	e0bffe17 	ldw	r2,-8(fp)
+ 8014640:	10c00cc5 	stb	r3,51(r2)
+    ptcb->OSTCBBitY         = (INT8U)(1 << ptcb->OSTCBY);
+ 8014644:	e0bffe17 	ldw	r2,-8(fp)
+ 8014648:	10800d03 	ldbu	r2,52(r2)
+ 801464c:	10803fcc 	andi	r2,r2,255
+ 8014650:	00c00044 	movi	r3,1
+ 8014654:	1884983a 	sll	r2,r3,r2
+ 8014658:	1007883a 	mov	r3,r2
+ 801465c:	e0bffe17 	ldw	r2,-8(fp)
+ 8014660:	10c00d85 	stb	r3,54(r2)
+    ptcb->OSTCBBitX         = (INT8U)(1 << ptcb->OSTCBX);
+ 8014664:	e0bffe17 	ldw	r2,-8(fp)
+ 8014668:	10800cc3 	ldbu	r2,51(r2)
+ 801466c:	10803fcc 	andi	r2,r2,255
+ 8014670:	00c00044 	movi	r3,1
+ 8014674:	1884983a 	sll	r2,r3,r2
+ 8014678:	1007883a 	mov	r3,r2
+ 801467c:	e0bffe17 	ldw	r2,-8(fp)
+ 8014680:	10c00d45 	stb	r3,53(r2)
+    ptcb->OSTCBY            = (INT8U)((prio >> (INT8U)4) & (INT8U)0x0F);
+    ptcb->OSTCBX            = (INT8U) (prio & (INT8U)0x0F);
+    ptcb->OSTCBBitY         = (INT16U)(1 << ptcb->OSTCBY);
+    ptcb->OSTCBBitX         = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+    OSRdyGrp               |= ptcb->OSTCBBitY;             /* Make task ready at original priority     */
+ 8014684:	e0bffe17 	ldw	r2,-8(fp)
+ 8014688:	10c00d83 	ldbu	r3,54(r2)
+ 801468c:	d0a05503 	ldbu	r2,-32428(gp)
+ 8014690:	1884b03a 	or	r2,r3,r2
+ 8014694:	d0a05505 	stb	r2,-32428(gp)
+    OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8014698:	e0bffe17 	ldw	r2,-8(fp)
+ 801469c:	10800d03 	ldbu	r2,52(r2)
+ 80146a0:	10c03fcc 	andi	r3,r2,255
+ 80146a4:	d0a05544 	addi	r2,gp,-32427
+ 80146a8:	1885883a 	add	r2,r3,r2
+ 80146ac:	11000003 	ldbu	r4,0(r2)
+ 80146b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80146b4:	10800d43 	ldbu	r2,53(r2)
+ 80146b8:	e0fffe17 	ldw	r3,-8(fp)
+ 80146bc:	18c00d03 	ldbu	r3,52(r3)
+ 80146c0:	18c03fcc 	andi	r3,r3,255
+ 80146c4:	2084b03a 	or	r2,r4,r2
+ 80146c8:	1009883a 	mov	r4,r2
+ 80146cc:	d0a05544 	addi	r2,gp,-32427
+ 80146d0:	1885883a 	add	r2,r3,r2
+ 80146d4:	11000005 	stb	r4,0(r2)
+    OSTCBPrioTbl[prio]      = ptcb;
+ 80146d8:	e0bffd03 	ldbu	r2,-12(fp)
+ 80146dc:	100890ba 	slli	r4,r2,2
+ 80146e0:	e0fffe17 	ldw	r3,-8(fp)
+ 80146e4:	008201b4 	movhi	r2,2054
+ 80146e8:	2085883a 	add	r2,r4,r2
+ 80146ec:	10f55d15 	stw	r3,-10892(r2)
+}
+ 80146f0:	0001883a 	nop
+ 80146f4:	e037883a 	mov	sp,fp
+ 80146f8:	df000017 	ldw	fp,0(sp)
+ 80146fc:	dec00104 	addi	sp,sp,4
+ 8014700:	f800283a 	ret
+
+08014704 <OSQAccept>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_ACCEPT_EN > 0
+void  *OSQAccept (OS_EVENT *pevent, INT8U *perr)
+{
+ 8014704:	defff804 	addi	sp,sp,-32
+ 8014708:	df000715 	stw	fp,28(sp)
+ 801470c:	df000704 	addi	fp,sp,28
+ 8014710:	e13ffa15 	stw	r4,-24(fp)
+ 8014714:	e17ff915 	stw	r5,-28(fp)
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014718:	e03ffe15 	stw	zero,-8(fp)
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+ 801471c:	e0bffa17 	ldw	r2,-24(fp)
+ 8014720:	10800003 	ldbu	r2,0(r2)
+ 8014724:	10803fcc 	andi	r2,r2,255
+ 8014728:	108000a0 	cmpeqi	r2,r2,2
+ 801472c:	1000051e 	bne	r2,zero,8014744 <OSQAccept+0x40>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8014730:	e0bff917 	ldw	r2,-28(fp)
+ 8014734:	00c00044 	movi	r3,1
+ 8014738:	10c00005 	stb	r3,0(r2)
+        return ((void *)0);
+ 801473c:	0005883a 	mov	r2,zero
+ 8014740:	00003106 	br	8014808 <OSQAccept+0x104>
+  NIOS2_READ_STATUS (context);
+ 8014744:	0005303a 	rdctl	r2,status
+ 8014748:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801474c:	e0fffc17 	ldw	r3,-16(fp)
+ 8014750:	00bfff84 	movi	r2,-2
+ 8014754:	1884703a 	and	r2,r3,r2
+ 8014758:	1001703a 	wrctl	status,r2
+  return context;
+ 801475c:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014760:	e0bffe15 	stw	r2,-8(fp)
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+ 8014764:	e0bffa17 	ldw	r2,-24(fp)
+ 8014768:	10800117 	ldw	r2,4(r2)
+ 801476c:	e0bffd15 	stw	r2,-12(fp)
+    if (pq->OSQEntries > 0) {                    /* See if any messages in the queue                   */
+ 8014770:	e0bffd17 	ldw	r2,-12(fp)
+ 8014774:	1080058b 	ldhu	r2,22(r2)
+ 8014778:	10bfffcc 	andi	r2,r2,65535
+ 801477c:	10001926 	beq	r2,zero,80147e4 <OSQAccept+0xe0>
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+ 8014780:	e0bffd17 	ldw	r2,-12(fp)
+ 8014784:	10800417 	ldw	r2,16(r2)
+ 8014788:	11000104 	addi	r4,r2,4
+ 801478c:	e0fffd17 	ldw	r3,-12(fp)
+ 8014790:	19000415 	stw	r4,16(r3)
+ 8014794:	10800017 	ldw	r2,0(r2)
+ 8014798:	e0bfff15 	stw	r2,-4(fp)
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+ 801479c:	e0bffd17 	ldw	r2,-12(fp)
+ 80147a0:	1080058b 	ldhu	r2,22(r2)
+ 80147a4:	10bfffc4 	addi	r2,r2,-1
+ 80147a8:	1007883a 	mov	r3,r2
+ 80147ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80147b0:	10c0058d 	sth	r3,22(r2)
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+ 80147b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80147b8:	10c00417 	ldw	r3,16(r2)
+ 80147bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80147c0:	10800217 	ldw	r2,8(r2)
+ 80147c4:	1880041e 	bne	r3,r2,80147d8 <OSQAccept+0xd4>
+            pq->OSQOut = pq->OSQStart;
+ 80147c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80147cc:	10c00117 	ldw	r3,4(r2)
+ 80147d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80147d4:	10c00415 	stw	r3,16(r2)
+        }
+        *perr = OS_ERR_NONE;
+ 80147d8:	e0bff917 	ldw	r2,-28(fp)
+ 80147dc:	10000005 	stb	zero,0(r2)
+ 80147e0:	00000406 	br	80147f4 <OSQAccept+0xf0>
+    } else {
+        *perr = OS_ERR_Q_EMPTY;
+ 80147e4:	e0bff917 	ldw	r2,-28(fp)
+ 80147e8:	00c007c4 	movi	r3,31
+ 80147ec:	10c00005 	stb	r3,0(r2)
+        pmsg  = (void *)0;                       /* Queue is empty                                     */
+ 80147f0:	e03fff15 	stw	zero,-4(fp)
+ 80147f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80147f8:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80147fc:	e0bffb17 	ldw	r2,-20(fp)
+ 8014800:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (pmsg);                               /* Return message received (or NULL)                  */
+ 8014804:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8014808:	e037883a 	mov	sp,fp
+ 801480c:	df000017 	ldw	fp,0(sp)
+ 8014810:	dec00104 	addi	sp,sp,4
+ 8014814:	f800283a 	ret
+
+08014818 <OSQCreate>:
+*              == (OS_EVENT *)0  if no event control blocks were available or an error was detected
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSQCreate (void **start, INT16U size)
+{
+ 8014818:	defff404 	addi	sp,sp,-48
+ 801481c:	dfc00b15 	stw	ra,44(sp)
+ 8014820:	df000a15 	stw	fp,40(sp)
+ 8014824:	df000a04 	addi	fp,sp,40
+ 8014828:	e13ff715 	stw	r4,-36(fp)
+ 801482c:	2805883a 	mov	r2,r5
+ 8014830:	e0bff60d 	sth	r2,-40(fp)
+    OS_EVENT  *pevent;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014834:	e03ffe15 	stw	zero,-8(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                      /* See if called from ISR ...                         */
+ 8014838:	d0a05703 	ldbu	r2,-32420(gp)
+ 801483c:	10803fcc 	andi	r2,r2,255
+ 8014840:	10000226 	beq	r2,zero,801484c <OSQCreate+0x34>
+        return ((OS_EVENT *)0);                  /* ... can't CREATE from an ISR                       */
+ 8014844:	0005883a 	mov	r2,zero
+ 8014848:	00005706 	br	80149a8 <OSQCreate+0x190>
+  NIOS2_READ_STATUS (context);
+ 801484c:	0005303a 	rdctl	r2,status
+ 8014850:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014854:	e0fffc17 	ldw	r3,-16(fp)
+ 8014858:	00bfff84 	movi	r2,-2
+ 801485c:	1884703a 	and	r2,r3,r2
+ 8014860:	1001703a 	wrctl	status,r2
+  return context;
+ 8014864:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014868:	e0bffe15 	stw	r2,-8(fp)
+    pevent = OSEventFreeList;                    /* Get next free event control block                  */
+ 801486c:	d0a05617 	ldw	r2,-32424(gp)
+ 8014870:	e0bfff15 	stw	r2,-4(fp)
+    if (OSEventFreeList != (OS_EVENT *)0) {      /* See if pool of free ECB pool was empty             */
+ 8014874:	d0a05617 	ldw	r2,-32424(gp)
+ 8014878:	10000326 	beq	r2,zero,8014888 <OSQCreate+0x70>
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+ 801487c:	d0a05617 	ldw	r2,-32424(gp)
+ 8014880:	10800117 	ldw	r2,4(r2)
+ 8014884:	d0a05615 	stw	r2,-32424(gp)
+ 8014888:	e0bffe17 	ldw	r2,-8(fp)
+ 801488c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014890:	e0bffb17 	ldw	r2,-20(fp)
+ 8014894:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {               /* See if we have an event control block              */
+ 8014898:	e0bfff17 	ldw	r2,-4(fp)
+ 801489c:	10004126 	beq	r2,zero,80149a4 <OSQCreate+0x18c>
+  NIOS2_READ_STATUS (context);
+ 80148a0:	0005303a 	rdctl	r2,status
+ 80148a4:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80148a8:	e0fffa17 	ldw	r3,-24(fp)
+ 80148ac:	00bfff84 	movi	r2,-2
+ 80148b0:	1884703a 	and	r2,r3,r2
+ 80148b4:	1001703a 	wrctl	status,r2
+  return context;
+ 80148b8:	e0bffa17 	ldw	r2,-24(fp)
+        OS_ENTER_CRITICAL();
+ 80148bc:	e0bffe15 	stw	r2,-8(fp)
+        pq = OSQFreeList;                        /* Get a free queue control block                     */
+ 80148c0:	d0a05417 	ldw	r2,-32432(gp)
+ 80148c4:	e0bffd15 	stw	r2,-12(fp)
+        if (pq != (OS_Q *)0) {                   /* Were we able to get a queue control block ?        */
+ 80148c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80148cc:	10002b26 	beq	r2,zero,801497c <OSQCreate+0x164>
+            OSQFreeList            = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/
+ 80148d0:	d0a05417 	ldw	r2,-32432(gp)
+ 80148d4:	10800017 	ldw	r2,0(r2)
+ 80148d8:	d0a05415 	stw	r2,-32432(gp)
+ 80148dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80148e0:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80148e4:	e0bff917 	ldw	r2,-28(fp)
+ 80148e8:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();
+            pq->OSQStart           = start;               /*      Initialize the queue                 */
+ 80148ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80148f0:	e0fff717 	ldw	r3,-36(fp)
+ 80148f4:	10c00115 	stw	r3,4(r2)
+            pq->OSQEnd             = &start[size];
+ 80148f8:	e0bff60b 	ldhu	r2,-40(fp)
+ 80148fc:	100490ba 	slli	r2,r2,2
+ 8014900:	e0fff717 	ldw	r3,-36(fp)
+ 8014904:	1887883a 	add	r3,r3,r2
+ 8014908:	e0bffd17 	ldw	r2,-12(fp)
+ 801490c:	10c00215 	stw	r3,8(r2)
+            pq->OSQIn              = start;
+ 8014910:	e0bffd17 	ldw	r2,-12(fp)
+ 8014914:	e0fff717 	ldw	r3,-36(fp)
+ 8014918:	10c00315 	stw	r3,12(r2)
+            pq->OSQOut             = start;
+ 801491c:	e0bffd17 	ldw	r2,-12(fp)
+ 8014920:	e0fff717 	ldw	r3,-36(fp)
+ 8014924:	10c00415 	stw	r3,16(r2)
+            pq->OSQSize            = size;
+ 8014928:	e0bffd17 	ldw	r2,-12(fp)
+ 801492c:	e0fff60b 	ldhu	r3,-40(fp)
+ 8014930:	10c0050d 	sth	r3,20(r2)
+            pq->OSQEntries         = 0;
+ 8014934:	e0bffd17 	ldw	r2,-12(fp)
+ 8014938:	1000058d 	sth	zero,22(r2)
+            pevent->OSEventType    = OS_EVENT_TYPE_Q;
+ 801493c:	e0bfff17 	ldw	r2,-4(fp)
+ 8014940:	00c00084 	movi	r3,2
+ 8014944:	10c00005 	stb	r3,0(r2)
+            pevent->OSEventCnt     = 0;
+ 8014948:	e0bfff17 	ldw	r2,-4(fp)
+ 801494c:	1000020d 	sth	zero,8(r2)
+            pevent->OSEventPtr     = pq;
+ 8014950:	e0bfff17 	ldw	r2,-4(fp)
+ 8014954:	e0fffd17 	ldw	r3,-12(fp)
+ 8014958:	10c00115 	stw	r3,4(r2)
+#if OS_EVENT_NAME_SIZE > 1
+            pevent->OSEventName[0] = '?';                  /* Unknown name                             */
+ 801495c:	e0bfff17 	ldw	r2,-4(fp)
+ 8014960:	00c00fc4 	movi	r3,63
+ 8014964:	10c00385 	stb	r3,14(r2)
+            pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8014968:	e0bfff17 	ldw	r2,-4(fp)
+ 801496c:	100003c5 	stb	zero,15(r2)
+#endif
+            OS_EventWaitListInit(pevent);                 /*      Initalize the wait list              */
+ 8014970:	e13fff17 	ldw	r4,-4(fp)
+ 8014974:	80112580 	call	8011258 <OS_EventWaitListInit>
+ 8014978:	00000a06 	br	80149a4 <OSQCreate+0x18c>
+        } else {
+            pevent->OSEventPtr = (void *)OSEventFreeList; /* No,  Return event control block on error  */
+ 801497c:	d0e05617 	ldw	r3,-32424(gp)
+ 8014980:	e0bfff17 	ldw	r2,-4(fp)
+ 8014984:	10c00115 	stw	r3,4(r2)
+            OSEventFreeList    = pevent;
+ 8014988:	e0bfff17 	ldw	r2,-4(fp)
+ 801498c:	d0a05615 	stw	r2,-32424(gp)
+ 8014990:	e0bffe17 	ldw	r2,-8(fp)
+ 8014994:	e0bff815 	stw	r2,-32(fp)
+ 8014998:	e0bff817 	ldw	r2,-32(fp)
+ 801499c:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();
+            pevent = (OS_EVENT *)0;
+ 80149a0:	e03fff15 	stw	zero,-4(fp)
+        }
+    }
+    return (pevent);
+ 80149a4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80149a8:	e037883a 	mov	sp,fp
+ 80149ac:	dfc00117 	ldw	ra,4(sp)
+ 80149b0:	df000017 	ldw	fp,0(sp)
+ 80149b4:	dec00204 	addi	sp,sp,8
+ 80149b8:	f800283a 	ret
+
+080149bc <OSQDel>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_DEL_EN > 0
+OS_EVENT  *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+ 80149bc:	defff204 	addi	sp,sp,-56
+ 80149c0:	dfc00d15 	stw	ra,52(sp)
+ 80149c4:	df000c15 	stw	fp,48(sp)
+ 80149c8:	df000c04 	addi	fp,sp,48
+ 80149cc:	e13ff615 	stw	r4,-40(fp)
+ 80149d0:	2805883a 	mov	r2,r5
+ 80149d4:	e1bff415 	stw	r6,-48(fp)
+ 80149d8:	e0bff505 	stb	r2,-44(fp)
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 80149dc:	e03ffd15 	stw	zero,-12(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+ 80149e0:	e0bff617 	ldw	r2,-40(fp)
+ 80149e4:	10800003 	ldbu	r2,0(r2)
+ 80149e8:	10803fcc 	andi	r2,r2,255
+ 80149ec:	108000a0 	cmpeqi	r2,r2,2
+ 80149f0:	1000051e 	bne	r2,zero,8014a08 <OSQDel+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 80149f4:	e0bff417 	ldw	r2,-48(fp)
+ 80149f8:	00c00044 	movi	r3,1
+ 80149fc:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8014a00:	e0bff617 	ldw	r2,-40(fp)
+ 8014a04:	00007d06 	br	8014bfc <OSQDel+0x240>
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8014a08:	d0a05703 	ldbu	r2,-32420(gp)
+ 8014a0c:	10803fcc 	andi	r2,r2,255
+ 8014a10:	10000526 	beq	r2,zero,8014a28 <OSQDel+0x6c>
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+ 8014a14:	e0bff417 	ldw	r2,-48(fp)
+ 8014a18:	00c003c4 	movi	r3,15
+ 8014a1c:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8014a20:	e0bff617 	ldw	r2,-40(fp)
+ 8014a24:	00007506 	br	8014bfc <OSQDel+0x240>
+  NIOS2_READ_STATUS (context);
+ 8014a28:	0005303a 	rdctl	r2,status
+ 8014a2c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014a30:	e0fffb17 	ldw	r3,-20(fp)
+ 8014a34:	00bfff84 	movi	r2,-2
+ 8014a38:	1884703a 	and	r2,r3,r2
+ 8014a3c:	1001703a 	wrctl	status,r2
+  return context;
+ 8014a40:	e0bffb17 	ldw	r2,-20(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014a44:	e0bffd15 	stw	r2,-12(fp)
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on queue        */
+ 8014a48:	e0bff617 	ldw	r2,-40(fp)
+ 8014a4c:	10800283 	ldbu	r2,10(r2)
+ 8014a50:	10803fcc 	andi	r2,r2,255
+ 8014a54:	10000326 	beq	r2,zero,8014a64 <OSQDel+0xa8>
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+ 8014a58:	00800044 	movi	r2,1
+ 8014a5c:	e0bfffc5 	stb	r2,-1(fp)
+ 8014a60:	00000106 	br	8014a68 <OSQDel+0xac>
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+ 8014a64:	e03fffc5 	stb	zero,-1(fp)
+    }
+    switch (opt) {
+ 8014a68:	e0bff503 	ldbu	r2,-44(fp)
+ 8014a6c:	10000326 	beq	r2,zero,8014a7c <OSQDel+0xc0>
+ 8014a70:	10800060 	cmpeqi	r2,r2,1
+ 8014a74:	1000301e 	bne	r2,zero,8014b38 <OSQDel+0x17c>
+ 8014a78:	00005506 	br	8014bd0 <OSQDel+0x214>
+        case OS_DEL_NO_PEND:                               /* Delete queue only if no task waiting     */
+             if (tasks_waiting == OS_FALSE) {
+ 8014a7c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014a80:	10001e1e 	bne	r2,zero,8014afc <OSQDel+0x140>
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+ 8014a84:	e0bff617 	ldw	r2,-40(fp)
+ 8014a88:	00c00fc4 	movi	r3,63
+ 8014a8c:	10c00385 	stb	r3,14(r2)
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8014a90:	e0bff617 	ldw	r2,-40(fp)
+ 8014a94:	100003c5 	stb	zero,15(r2)
+#endif
+                 pq                     = (OS_Q *)pevent->OSEventPtr;  /* Return OS_Q to free list     */
+ 8014a98:	e0bff617 	ldw	r2,-40(fp)
+ 8014a9c:	10800117 	ldw	r2,4(r2)
+ 8014aa0:	e0bffc15 	stw	r2,-16(fp)
+                 pq->OSQPtr             = OSQFreeList;
+ 8014aa4:	d0e05417 	ldw	r3,-32432(gp)
+ 8014aa8:	e0bffc17 	ldw	r2,-16(fp)
+ 8014aac:	10c00015 	stw	r3,0(r2)
+                 OSQFreeList            = pq;
+ 8014ab0:	e0bffc17 	ldw	r2,-16(fp)
+ 8014ab4:	d0a05415 	stw	r2,-32432(gp)
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+ 8014ab8:	e0bff617 	ldw	r2,-40(fp)
+ 8014abc:	10000005 	stb	zero,0(r2)
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+ 8014ac0:	d0e05617 	ldw	r3,-32424(gp)
+ 8014ac4:	e0bff617 	ldw	r2,-40(fp)
+ 8014ac8:	10c00115 	stw	r3,4(r2)
+                 pevent->OSEventCnt     = 0;
+ 8014acc:	e0bff617 	ldw	r2,-40(fp)
+ 8014ad0:	1000020d 	sth	zero,8(r2)
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+ 8014ad4:	e0bff617 	ldw	r2,-40(fp)
+ 8014ad8:	d0a05615 	stw	r2,-32424(gp)
+ 8014adc:	e0bffd17 	ldw	r2,-12(fp)
+ 8014ae0:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014ae4:	e0bffa17 	ldw	r2,-24(fp)
+ 8014ae8:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+ 8014aec:	e0bff417 	ldw	r2,-48(fp)
+ 8014af0:	10000005 	stb	zero,0(r2)
+                 pevent_return          = (OS_EVENT *)0;   /* Queue has been deleted                   */
+ 8014af4:	e03ffe15 	stw	zero,-8(fp)
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+ 8014af8:	00003f06 	br	8014bf8 <OSQDel+0x23c>
+ 8014afc:	e0bffd17 	ldw	r2,-12(fp)
+ 8014b00:	e0bff915 	stw	r2,-28(fp)
+ 8014b04:	e0bff917 	ldw	r2,-28(fp)
+ 8014b08:	1001703a 	wrctl	status,r2
+                 *perr                  = OS_ERR_TASK_WAITING;
+ 8014b0c:	e0bff417 	ldw	r2,-48(fp)
+ 8014b10:	00c01244 	movi	r3,73
+ 8014b14:	10c00005 	stb	r3,0(r2)
+                 pevent_return          = pevent;
+ 8014b18:	e0bff617 	ldw	r2,-40(fp)
+ 8014b1c:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8014b20:	00003506 	br	8014bf8 <OSQDel+0x23c>
+
+        case OS_DEL_ALWAYS:                                /* Always delete the queue                  */
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for queue        */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK);
+ 8014b24:	000f883a 	mov	r7,zero
+ 8014b28:	01800104 	movi	r6,4
+ 8014b2c:	000b883a 	mov	r5,zero
+ 8014b30:	e13ff617 	ldw	r4,-40(fp)
+ 8014b34:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for queue        */
+ 8014b38:	e0bff617 	ldw	r2,-40(fp)
+ 8014b3c:	10800283 	ldbu	r2,10(r2)
+ 8014b40:	10803fcc 	andi	r2,r2,255
+ 8014b44:	103ff71e 	bne	r2,zero,8014b24 <OSQDel+0x168>
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+ 8014b48:	e0bff617 	ldw	r2,-40(fp)
+ 8014b4c:	00c00fc4 	movi	r3,63
+ 8014b50:	10c00385 	stb	r3,14(r2)
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8014b54:	e0bff617 	ldw	r2,-40(fp)
+ 8014b58:	100003c5 	stb	zero,15(r2)
+#endif
+             pq                     = (OS_Q *)pevent->OSEventPtr;   /* Return OS_Q to free list        */
+ 8014b5c:	e0bff617 	ldw	r2,-40(fp)
+ 8014b60:	10800117 	ldw	r2,4(r2)
+ 8014b64:	e0bffc15 	stw	r2,-16(fp)
+             pq->OSQPtr             = OSQFreeList;
+ 8014b68:	d0e05417 	ldw	r3,-32432(gp)
+ 8014b6c:	e0bffc17 	ldw	r2,-16(fp)
+ 8014b70:	10c00015 	stw	r3,0(r2)
+             OSQFreeList            = pq;
+ 8014b74:	e0bffc17 	ldw	r2,-16(fp)
+ 8014b78:	d0a05415 	stw	r2,-32432(gp)
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+ 8014b7c:	e0bff617 	ldw	r2,-40(fp)
+ 8014b80:	10000005 	stb	zero,0(r2)
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+ 8014b84:	d0e05617 	ldw	r3,-32424(gp)
+ 8014b88:	e0bff617 	ldw	r2,-40(fp)
+ 8014b8c:	10c00115 	stw	r3,4(r2)
+             pevent->OSEventCnt     = 0;
+ 8014b90:	e0bff617 	ldw	r2,-40(fp)
+ 8014b94:	1000020d 	sth	zero,8(r2)
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+ 8014b98:	e0bff617 	ldw	r2,-40(fp)
+ 8014b9c:	d0a05615 	stw	r2,-32424(gp)
+ 8014ba0:	e0bffd17 	ldw	r2,-12(fp)
+ 8014ba4:	e0bff815 	stw	r2,-32(fp)
+ 8014ba8:	e0bff817 	ldw	r2,-32(fp)
+ 8014bac:	1001703a 	wrctl	status,r2
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+ 8014bb0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014bb4:	10800058 	cmpnei	r2,r2,1
+ 8014bb8:	1000011e 	bne	r2,zero,8014bc0 <OSQDel+0x204>
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+ 8014bbc:	801166c0 	call	801166c <OS_Sched>
+             }
+             *perr                  = OS_ERR_NONE;
+ 8014bc0:	e0bff417 	ldw	r2,-48(fp)
+ 8014bc4:	10000005 	stb	zero,0(r2)
+             pevent_return          = (OS_EVENT *)0;       /* Queue has been deleted                   */
+ 8014bc8:	e03ffe15 	stw	zero,-8(fp)
+             break;
+ 8014bcc:	00000a06 	br	8014bf8 <OSQDel+0x23c>
+ 8014bd0:	e0bffd17 	ldw	r2,-12(fp)
+ 8014bd4:	e0bff715 	stw	r2,-36(fp)
+ 8014bd8:	e0bff717 	ldw	r2,-36(fp)
+ 8014bdc:	1001703a 	wrctl	status,r2
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+ 8014be0:	e0bff417 	ldw	r2,-48(fp)
+ 8014be4:	00c001c4 	movi	r3,7
+ 8014be8:	10c00005 	stb	r3,0(r2)
+             pevent_return          = pevent;
+ 8014bec:	e0bff617 	ldw	r2,-40(fp)
+ 8014bf0:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8014bf4:	0001883a 	nop
+    }
+    return (pevent_return);
+ 8014bf8:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8014bfc:	e037883a 	mov	sp,fp
+ 8014c00:	dfc00117 	ldw	ra,4(sp)
+ 8014c04:	df000017 	ldw	fp,0(sp)
+ 8014c08:	dec00204 	addi	sp,sp,8
+ 8014c0c:	f800283a 	ret
+
+08014c10 <OSQFlush>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_FLUSH_EN > 0
+INT8U  OSQFlush (OS_EVENT *pevent)
+{
+ 8014c10:	defffa04 	addi	sp,sp,-24
+ 8014c14:	df000515 	stw	fp,20(sp)
+ 8014c18:	df000504 	addi	fp,sp,20
+ 8014c1c:	e13ffb15 	stw	r4,-20(fp)
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014c20:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8014c24:	0005303a 	rdctl	r2,status
+ 8014c28:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014c2c:	e0fffc17 	ldw	r3,-16(fp)
+ 8014c30:	00bfff84 	movi	r2,-2
+ 8014c34:	1884703a 	and	r2,r3,r2
+ 8014c38:	1001703a 	wrctl	status,r2
+  return context;
+ 8014c3c:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 8014c40:	e0bfff15 	stw	r2,-4(fp)
+    pq             = (OS_Q *)pevent->OSEventPtr;      /* Point to queue storage structure              */
+ 8014c44:	e0bffb17 	ldw	r2,-20(fp)
+ 8014c48:	10800117 	ldw	r2,4(r2)
+ 8014c4c:	e0bffe15 	stw	r2,-8(fp)
+    pq->OSQIn      = pq->OSQStart;
+ 8014c50:	e0bffe17 	ldw	r2,-8(fp)
+ 8014c54:	10c00117 	ldw	r3,4(r2)
+ 8014c58:	e0bffe17 	ldw	r2,-8(fp)
+ 8014c5c:	10c00315 	stw	r3,12(r2)
+    pq->OSQOut     = pq->OSQStart;
+ 8014c60:	e0bffe17 	ldw	r2,-8(fp)
+ 8014c64:	10c00117 	ldw	r3,4(r2)
+ 8014c68:	e0bffe17 	ldw	r2,-8(fp)
+ 8014c6c:	10c00415 	stw	r3,16(r2)
+    pq->OSQEntries = 0;
+ 8014c70:	e0bffe17 	ldw	r2,-8(fp)
+ 8014c74:	1000058d 	sth	zero,22(r2)
+ 8014c78:	e0bfff17 	ldw	r2,-4(fp)
+ 8014c7c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014c80:	e0bffd17 	ldw	r2,-12(fp)
+ 8014c84:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8014c88:	0005883a 	mov	r2,zero
+}
+ 8014c8c:	e037883a 	mov	sp,fp
+ 8014c90:	df000017 	ldw	fp,0(sp)
+ 8014c94:	dec00104 	addi	sp,sp,4
+ 8014c98:	f800283a 	ret
+
+08014c9c <OSQPend>:
+* Note(s)    : As of V2.60, this function allows you to receive NULL pointer messages.
+*********************************************************************************************************
+*/
+
+void  *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+ 8014c9c:	defff304 	addi	sp,sp,-52
+ 8014ca0:	dfc00c15 	stw	ra,48(sp)
+ 8014ca4:	df000b15 	stw	fp,44(sp)
+ 8014ca8:	df000b04 	addi	fp,sp,44
+ 8014cac:	e13ff715 	stw	r4,-36(fp)
+ 8014cb0:	2805883a 	mov	r2,r5
+ 8014cb4:	e1bff515 	stw	r6,-44(fp)
+ 8014cb8:	e0bff60d 	sth	r2,-40(fp)
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014cbc:	e03ffe15 	stw	zero,-8(fp)
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+ 8014cc0:	e0bff717 	ldw	r2,-36(fp)
+ 8014cc4:	10800003 	ldbu	r2,0(r2)
+ 8014cc8:	10803fcc 	andi	r2,r2,255
+ 8014ccc:	108000a0 	cmpeqi	r2,r2,2
+ 8014cd0:	1000051e 	bne	r2,zero,8014ce8 <OSQPend+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8014cd4:	e0bff517 	ldw	r2,-44(fp)
+ 8014cd8:	00c00044 	movi	r3,1
+ 8014cdc:	10c00005 	stb	r3,0(r2)
+        return ((void *)0);
+ 8014ce0:	0005883a 	mov	r2,zero
+ 8014ce4:	00008006 	br	8014ee8 <OSQPend+0x24c>
+    }
+    if (OSIntNesting > 0) {                      /* See if called from ISR ...                         */
+ 8014ce8:	d0a05703 	ldbu	r2,-32420(gp)
+ 8014cec:	10803fcc 	andi	r2,r2,255
+ 8014cf0:	10000526 	beq	r2,zero,8014d08 <OSQPend+0x6c>
+        *perr = OS_ERR_PEND_ISR;                 /* ... can't PEND from an ISR                         */
+ 8014cf4:	e0bff517 	ldw	r2,-44(fp)
+ 8014cf8:	00c00084 	movi	r3,2
+ 8014cfc:	10c00005 	stb	r3,0(r2)
+        return ((void *)0);
+ 8014d00:	0005883a 	mov	r2,zero
+ 8014d04:	00007806 	br	8014ee8 <OSQPend+0x24c>
+    }
+    if (OSLockNesting > 0) {                     /* See if called with scheduler locked ...            */
+ 8014d08:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8014d0c:	10803fcc 	andi	r2,r2,255
+ 8014d10:	10000526 	beq	r2,zero,8014d28 <OSQPend+0x8c>
+        *perr = OS_ERR_PEND_LOCKED;              /* ... can't PEND when locked                         */
+ 8014d14:	e0bff517 	ldw	r2,-44(fp)
+ 8014d18:	00c00344 	movi	r3,13
+ 8014d1c:	10c00005 	stb	r3,0(r2)
+        return ((void *)0);
+ 8014d20:	0005883a 	mov	r2,zero
+ 8014d24:	00007006 	br	8014ee8 <OSQPend+0x24c>
+  NIOS2_READ_STATUS (context);
+ 8014d28:	0005303a 	rdctl	r2,status
+ 8014d2c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014d30:	e0fffc17 	ldw	r3,-16(fp)
+ 8014d34:	00bfff84 	movi	r2,-2
+ 8014d38:	1884703a 	and	r2,r3,r2
+ 8014d3c:	1001703a 	wrctl	status,r2
+  return context;
+ 8014d40:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014d44:	e0bffe15 	stw	r2,-8(fp)
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+ 8014d48:	e0bff717 	ldw	r2,-36(fp)
+ 8014d4c:	10800117 	ldw	r2,4(r2)
+ 8014d50:	e0bffd15 	stw	r2,-12(fp)
+    if (pq->OSQEntries > 0) {                    /* See if any messages in the queue                   */
+ 8014d54:	e0bffd17 	ldw	r2,-12(fp)
+ 8014d58:	1080058b 	ldhu	r2,22(r2)
+ 8014d5c:	10bfffcc 	andi	r2,r2,65535
+ 8014d60:	10001e26 	beq	r2,zero,8014ddc <OSQPend+0x140>
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+ 8014d64:	e0bffd17 	ldw	r2,-12(fp)
+ 8014d68:	10800417 	ldw	r2,16(r2)
+ 8014d6c:	11000104 	addi	r4,r2,4
+ 8014d70:	e0fffd17 	ldw	r3,-12(fp)
+ 8014d74:	19000415 	stw	r4,16(r3)
+ 8014d78:	10800017 	ldw	r2,0(r2)
+ 8014d7c:	e0bfff15 	stw	r2,-4(fp)
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+ 8014d80:	e0bffd17 	ldw	r2,-12(fp)
+ 8014d84:	1080058b 	ldhu	r2,22(r2)
+ 8014d88:	10bfffc4 	addi	r2,r2,-1
+ 8014d8c:	1007883a 	mov	r3,r2
+ 8014d90:	e0bffd17 	ldw	r2,-12(fp)
+ 8014d94:	10c0058d 	sth	r3,22(r2)
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+ 8014d98:	e0bffd17 	ldw	r2,-12(fp)
+ 8014d9c:	10c00417 	ldw	r3,16(r2)
+ 8014da0:	e0bffd17 	ldw	r2,-12(fp)
+ 8014da4:	10800217 	ldw	r2,8(r2)
+ 8014da8:	1880041e 	bne	r3,r2,8014dbc <OSQPend+0x120>
+            pq->OSQOut = pq->OSQStart;
+ 8014dac:	e0bffd17 	ldw	r2,-12(fp)
+ 8014db0:	10c00117 	ldw	r3,4(r2)
+ 8014db4:	e0bffd17 	ldw	r2,-12(fp)
+ 8014db8:	10c00415 	stw	r3,16(r2)
+ 8014dbc:	e0bffe17 	ldw	r2,-8(fp)
+ 8014dc0:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014dc4:	e0bffb17 	ldw	r2,-20(fp)
+ 8014dc8:	1001703a 	wrctl	status,r2
+        }
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+ 8014dcc:	e0bff517 	ldw	r2,-44(fp)
+ 8014dd0:	10000005 	stb	zero,0(r2)
+        return (pmsg);                           /* Return message received                            */
+ 8014dd4:	e0bfff17 	ldw	r2,-4(fp)
+ 8014dd8:	00004306 	br	8014ee8 <OSQPend+0x24c>
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_Q;        /* Task will have to pend for a message to be posted  */
+ 8014ddc:	d0a05817 	ldw	r2,-32416(gp)
+ 8014de0:	10c00c03 	ldbu	r3,48(r2)
+ 8014de4:	d0a05817 	ldw	r2,-32416(gp)
+ 8014de8:	18c00114 	ori	r3,r3,4
+ 8014dec:	10c00c05 	stb	r3,48(r2)
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 8014df0:	d0a05817 	ldw	r2,-32416(gp)
+ 8014df4:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBDly       = timeout;          /* Load timeout into TCB                              */
+ 8014df8:	d0a05817 	ldw	r2,-32416(gp)
+ 8014dfc:	e0fff60b 	ldhu	r3,-40(fp)
+ 8014e00:	10c00b8d 	sth	r3,46(r2)
+    OS_EventTaskWait(pevent);                    /* Suspend task until event or timeout occurs         */
+ 8014e04:	e13ff717 	ldw	r4,-36(fp)
+ 8014e08:	8010e600 	call	8010e60 <OS_EventTaskWait>
+ 8014e0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8014e10:	e0bff915 	stw	r2,-28(fp)
+ 8014e14:	e0bff917 	ldw	r2,-28(fp)
+ 8014e18:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                  /* Find next highest priority task ready to run       */
+ 8014e1c:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 8014e20:	0005303a 	rdctl	r2,status
+ 8014e24:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014e28:	e0fffa17 	ldw	r3,-24(fp)
+ 8014e2c:	00bfff84 	movi	r2,-2
+ 8014e30:	1884703a 	and	r2,r3,r2
+ 8014e34:	1001703a 	wrctl	status,r2
+  return context;
+ 8014e38:	e0bffa17 	ldw	r2,-24(fp)
+    OS_ENTER_CRITICAL();
+ 8014e3c:	e0bffe15 	stw	r2,-8(fp)
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+ 8014e40:	d0a05817 	ldw	r2,-32416(gp)
+ 8014e44:	10800c43 	ldbu	r2,49(r2)
+ 8014e48:	10803fcc 	andi	r2,r2,255
+ 8014e4c:	10000326 	beq	r2,zero,8014e5c <OSQPend+0x1c0>
+ 8014e50:	108000a0 	cmpeqi	r2,r2,2
+ 8014e54:	1000071e 	bne	r2,zero,8014e74 <OSQPend+0x1d8>
+ 8014e58:	00000b06 	br	8014e88 <OSQPend+0x1ec>
+        case OS_STAT_PEND_OK:                         /* Extract message from TCB (Put there by QPost) */
+             pmsg =  OSTCBCur->OSTCBMsg;
+ 8014e5c:	d0a05817 	ldw	r2,-32416(gp)
+ 8014e60:	10800917 	ldw	r2,36(r2)
+ 8014e64:	e0bfff15 	stw	r2,-4(fp)
+            *perr =  OS_ERR_NONE;
+ 8014e68:	e0bff517 	ldw	r2,-44(fp)
+ 8014e6c:	10000005 	stb	zero,0(r2)
+             break;
+ 8014e70:	00000e06 	br	8014eac <OSQPend+0x210>
+
+        case OS_STAT_PEND_ABORT:
+             pmsg = (void *)0;
+ 8014e74:	e03fff15 	stw	zero,-4(fp)
+            *perr =  OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+ 8014e78:	e0bff517 	ldw	r2,-44(fp)
+ 8014e7c:	00c00384 	movi	r3,14
+ 8014e80:	10c00005 	stb	r3,0(r2)
+             break;
+ 8014e84:	00000906 	br	8014eac <OSQPend+0x210>
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+ 8014e88:	d0a05817 	ldw	r2,-32416(gp)
+ 8014e8c:	e17ff717 	ldw	r5,-36(fp)
+ 8014e90:	1009883a 	mov	r4,r2
+ 8014e94:	80110b00 	call	80110b0 <OS_EventTaskRemove>
+             pmsg = (void *)0;
+ 8014e98:	e03fff15 	stw	zero,-4(fp)
+            *perr =  OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+ 8014e9c:	e0bff517 	ldw	r2,-44(fp)
+ 8014ea0:	00c00284 	movi	r3,10
+ 8014ea4:	10c00005 	stb	r3,0(r2)
+             break;
+ 8014ea8:	0001883a 	nop
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+ 8014eac:	d0a05817 	ldw	r2,-32416(gp)
+ 8014eb0:	10000c05 	stb	zero,48(r2)
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+ 8014eb4:	d0a05817 	ldw	r2,-32416(gp)
+ 8014eb8:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+ 8014ebc:	d0a05817 	ldw	r2,-32416(gp)
+ 8014ec0:	10000715 	stw	zero,28(r2)
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+ 8014ec4:	d0a05817 	ldw	r2,-32416(gp)
+ 8014ec8:	10000815 	stw	zero,32(r2)
+#endif
+    OSTCBCur->OSTCBMsg           = (void      *)0;    /* Clear  received message                       */
+ 8014ecc:	d0a05817 	ldw	r2,-32416(gp)
+ 8014ed0:	10000915 	stw	zero,36(r2)
+ 8014ed4:	e0bffe17 	ldw	r2,-8(fp)
+ 8014ed8:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014edc:	e0bff817 	ldw	r2,-32(fp)
+ 8014ee0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (pmsg);                                    /* Return received message                       */
+ 8014ee4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8014ee8:	e037883a 	mov	sp,fp
+ 8014eec:	dfc00117 	ldw	ra,4(sp)
+ 8014ef0:	df000017 	ldw	fp,0(sp)
+ 8014ef4:	dec00204 	addi	sp,sp,8
+ 8014ef8:	f800283a 	ret
+
+08014efc <OSQPendAbort>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_PEND_ABORT_EN > 0
+INT8U  OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+ 8014efc:	defff604 	addi	sp,sp,-40
+ 8014f00:	dfc00915 	stw	ra,36(sp)
+ 8014f04:	df000815 	stw	fp,32(sp)
+ 8014f08:	df000804 	addi	fp,sp,32
+ 8014f0c:	e13ffa15 	stw	r4,-24(fp)
+ 8014f10:	2805883a 	mov	r2,r5
+ 8014f14:	e1bff815 	stw	r6,-32(fp)
+ 8014f18:	e0bff905 	stb	r2,-28(fp)
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 8014f1c:	e03ffe15 	stw	zero,-8(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+ 8014f20:	e0bffa17 	ldw	r2,-24(fp)
+ 8014f24:	10800003 	ldbu	r2,0(r2)
+ 8014f28:	10803fcc 	andi	r2,r2,255
+ 8014f2c:	108000a0 	cmpeqi	r2,r2,2
+ 8014f30:	1000051e 	bne	r2,zero,8014f48 <OSQPendAbort+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8014f34:	e0bff817 	ldw	r2,-32(fp)
+ 8014f38:	00c00044 	movi	r3,1
+ 8014f3c:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8014f40:	0005883a 	mov	r2,zero
+ 8014f44:	00003806 	br	8015028 <OSQPendAbort+0x12c>
+  NIOS2_READ_STATUS (context);
+ 8014f48:	0005303a 	rdctl	r2,status
+ 8014f4c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8014f50:	e0fffd17 	ldw	r3,-12(fp)
+ 8014f54:	00bfff84 	movi	r2,-2
+ 8014f58:	1884703a 	and	r2,r3,r2
+ 8014f5c:	1001703a 	wrctl	status,r2
+  return context;
+ 8014f60:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8014f64:	e0bffe15 	stw	r2,-8(fp)
+    if (pevent->OSEventGrp != 0) {                         /* See if any task waiting on queue?        */
+ 8014f68:	e0bffa17 	ldw	r2,-24(fp)
+ 8014f6c:	10800283 	ldbu	r2,10(r2)
+ 8014f70:	10803fcc 	andi	r2,r2,255
+ 8014f74:	10002526 	beq	r2,zero,801500c <OSQPendAbort+0x110>
+        nbr_tasks = 0;
+ 8014f78:	e03fffc5 	stb	zero,-1(fp)
+        switch (opt) {
+ 8014f7c:	e0bff903 	ldbu	r2,-28(fp)
+ 8014f80:	10800058 	cmpnei	r2,r2,1
+ 8014f84:	10000e1e 	bne	r2,zero,8014fc0 <OSQPendAbort+0xc4>
+            case OS_PEND_OPT_BROADCAST:                    /* Do we need to abort ALL waiting tasks?   */
+                 while (pevent->OSEventGrp != 0) {         /* Yes, ready ALL tasks waiting on queue    */
+ 8014f88:	00000806 	br	8014fac <OSQPendAbort+0xb0>
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+ 8014f8c:	01c00084 	movi	r7,2
+ 8014f90:	01800104 	movi	r6,4
+ 8014f94:	000b883a 	mov	r5,zero
+ 8014f98:	e13ffa17 	ldw	r4,-24(fp)
+ 8014f9c:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+                     nbr_tasks++;
+ 8014fa0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014fa4:	10800044 	addi	r2,r2,1
+ 8014fa8:	e0bfffc5 	stb	r2,-1(fp)
+                 while (pevent->OSEventGrp != 0) {         /* Yes, ready ALL tasks waiting on queue    */
+ 8014fac:	e0bffa17 	ldw	r2,-24(fp)
+ 8014fb0:	10800283 	ldbu	r2,10(r2)
+ 8014fb4:	10803fcc 	andi	r2,r2,255
+ 8014fb8:	103ff41e 	bne	r2,zero,8014f8c <OSQPendAbort+0x90>
+                 }
+                 break;
+ 8014fbc:	00000906 	br	8014fe4 <OSQPendAbort+0xe8>
+               
+            case OS_PEND_OPT_NONE:
+            default:                                       /* No,  ready HPT       waiting on queue    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+ 8014fc0:	01c00084 	movi	r7,2
+ 8014fc4:	01800104 	movi	r6,4
+ 8014fc8:	000b883a 	mov	r5,zero
+ 8014fcc:	e13ffa17 	ldw	r4,-24(fp)
+ 8014fd0:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+                 nbr_tasks++;
+ 8014fd4:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8014fd8:	10800044 	addi	r2,r2,1
+ 8014fdc:	e0bfffc5 	stb	r2,-1(fp)
+                 break;
+ 8014fe0:	0001883a 	nop
+ 8014fe4:	e0bffe17 	ldw	r2,-8(fp)
+ 8014fe8:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8014fec:	e0bffc17 	ldw	r2,-16(fp)
+ 8014ff0:	1001703a 	wrctl	status,r2
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                        /* Find HPT ready to run                    */
+ 8014ff4:	801166c0 	call	801166c <OS_Sched>
+        *perr = OS_ERR_PEND_ABORT;
+ 8014ff8:	e0bff817 	ldw	r2,-32(fp)
+ 8014ffc:	00c00384 	movi	r3,14
+ 8015000:	10c00005 	stb	r3,0(r2)
+        return (nbr_tasks);
+ 8015004:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015008:	00000706 	br	8015028 <OSQPendAbort+0x12c>
+ 801500c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015010:	e0bffb15 	stw	r2,-20(fp)
+ 8015014:	e0bffb17 	ldw	r2,-20(fp)
+ 8015018:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 801501c:	e0bff817 	ldw	r2,-32(fp)
+ 8015020:	10000005 	stb	zero,0(r2)
+    return (0);                                            /* No tasks waiting on queue                */
+ 8015024:	0005883a 	mov	r2,zero
+}
+ 8015028:	e037883a 	mov	sp,fp
+ 801502c:	dfc00117 	ldw	ra,4(sp)
+ 8015030:	df000017 	ldw	fp,0(sp)
+ 8015034:	dec00204 	addi	sp,sp,8
+ 8015038:	f800283a 	ret
+
+0801503c <OSQPost>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_EN > 0
+INT8U  OSQPost (OS_EVENT *pevent, void *pmsg)
+{
+ 801503c:	defff604 	addi	sp,sp,-40
+ 8015040:	dfc00915 	stw	ra,36(sp)
+ 8015044:	df000815 	stw	fp,32(sp)
+ 8015048:	df000804 	addi	fp,sp,32
+ 801504c:	e13ff915 	stw	r4,-28(fp)
+ 8015050:	e17ff815 	stw	r5,-32(fp)
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015054:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+ 8015058:	e0bff917 	ldw	r2,-28(fp)
+ 801505c:	10800003 	ldbu	r2,0(r2)
+ 8015060:	10803fcc 	andi	r2,r2,255
+ 8015064:	108000a0 	cmpeqi	r2,r2,2
+ 8015068:	1000021e 	bne	r2,zero,8015074 <OSQPost+0x38>
+        return (OS_ERR_EVENT_TYPE);
+ 801506c:	00800044 	movi	r2,1
+ 8015070:	00004306 	br	8015180 <OSQPost+0x144>
+  NIOS2_READ_STATUS (context);
+ 8015074:	0005303a 	rdctl	r2,status
+ 8015078:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801507c:	e0fffd17 	ldw	r3,-12(fp)
+ 8015080:	00bfff84 	movi	r2,-2
+ 8015084:	1884703a 	and	r2,r3,r2
+ 8015088:	1001703a 	wrctl	status,r2
+  return context;
+ 801508c:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015090:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent->OSEventGrp != 0) {                     /* See if any task pending on queue             */
+ 8015094:	e0bff917 	ldw	r2,-28(fp)
+ 8015098:	10800283 	ldbu	r2,10(r2)
+ 801509c:	10803fcc 	andi	r2,r2,255
+ 80150a0:	10000c26 	beq	r2,zero,80150d4 <OSQPost+0x98>
+                                                       /* Ready highest priority task waiting on event */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+ 80150a4:	000f883a 	mov	r7,zero
+ 80150a8:	01800104 	movi	r6,4
+ 80150ac:	e17ff817 	ldw	r5,-32(fp)
+ 80150b0:	e13ff917 	ldw	r4,-28(fp)
+ 80150b4:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+ 80150b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80150bc:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80150c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80150c4:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                    /* Find highest priority task ready to run      */
+ 80150c8:	801166c0 	call	801166c <OS_Sched>
+        return (OS_ERR_NONE);
+ 80150cc:	0005883a 	mov	r2,zero
+ 80150d0:	00002b06 	br	8015180 <OSQPost+0x144>
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                   /* Point to queue control block                 */
+ 80150d4:	e0bff917 	ldw	r2,-28(fp)
+ 80150d8:	10800117 	ldw	r2,4(r2)
+ 80150dc:	e0bffe15 	stw	r2,-8(fp)
+    if (pq->OSQEntries >= pq->OSQSize) {               /* Make sure queue is not full                  */
+ 80150e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80150e4:	10c0058b 	ldhu	r3,22(r2)
+ 80150e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80150ec:	1080050b 	ldhu	r2,20(r2)
+ 80150f0:	18ffffcc 	andi	r3,r3,65535
+ 80150f4:	10bfffcc 	andi	r2,r2,65535
+ 80150f8:	18800636 	bltu	r3,r2,8015114 <OSQPost+0xd8>
+ 80150fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8015100:	e0bffb15 	stw	r2,-20(fp)
+ 8015104:	e0bffb17 	ldw	r2,-20(fp)
+ 8015108:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+ 801510c:	00800784 	movi	r2,30
+ 8015110:	00001b06 	br	8015180 <OSQPost+0x144>
+    }
+    *pq->OSQIn++ = pmsg;                               /* Insert message into queue                    */
+ 8015114:	e0bffe17 	ldw	r2,-8(fp)
+ 8015118:	10800317 	ldw	r2,12(r2)
+ 801511c:	11000104 	addi	r4,r2,4
+ 8015120:	e0fffe17 	ldw	r3,-8(fp)
+ 8015124:	19000315 	stw	r4,12(r3)
+ 8015128:	e0fff817 	ldw	r3,-32(fp)
+ 801512c:	10c00015 	stw	r3,0(r2)
+    pq->OSQEntries++;                                  /* Update the nbr of entries in the queue       */
+ 8015130:	e0bffe17 	ldw	r2,-8(fp)
+ 8015134:	1080058b 	ldhu	r2,22(r2)
+ 8015138:	10800044 	addi	r2,r2,1
+ 801513c:	1007883a 	mov	r3,r2
+ 8015140:	e0bffe17 	ldw	r2,-8(fp)
+ 8015144:	10c0058d 	sth	r3,22(r2)
+    if (pq->OSQIn == pq->OSQEnd) {                     /* Wrap IN ptr if we are at end of queue        */
+ 8015148:	e0bffe17 	ldw	r2,-8(fp)
+ 801514c:	10c00317 	ldw	r3,12(r2)
+ 8015150:	e0bffe17 	ldw	r2,-8(fp)
+ 8015154:	10800217 	ldw	r2,8(r2)
+ 8015158:	1880041e 	bne	r3,r2,801516c <OSQPost+0x130>
+        pq->OSQIn = pq->OSQStart;
+ 801515c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015160:	10c00117 	ldw	r3,4(r2)
+ 8015164:	e0bffe17 	ldw	r2,-8(fp)
+ 8015168:	10c00315 	stw	r3,12(r2)
+ 801516c:	e0bfff17 	ldw	r2,-4(fp)
+ 8015170:	e0bffa15 	stw	r2,-24(fp)
+ 8015174:	e0bffa17 	ldw	r2,-24(fp)
+ 8015178:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 801517c:	0005883a 	mov	r2,zero
+}
+ 8015180:	e037883a 	mov	sp,fp
+ 8015184:	dfc00117 	ldw	ra,4(sp)
+ 8015188:	df000017 	ldw	fp,0(sp)
+ 801518c:	dec00204 	addi	sp,sp,8
+ 8015190:	f800283a 	ret
+
+08015194 <OSQPostFront>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_FRONT_EN > 0
+INT8U  OSQPostFront (OS_EVENT *pevent, void *pmsg)
+{
+ 8015194:	defff604 	addi	sp,sp,-40
+ 8015198:	dfc00915 	stw	ra,36(sp)
+ 801519c:	df000815 	stw	fp,32(sp)
+ 80151a0:	df000804 	addi	fp,sp,32
+ 80151a4:	e13ff915 	stw	r4,-28(fp)
+ 80151a8:	e17ff815 	stw	r5,-32(fp)
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 80151ac:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+ 80151b0:	e0bff917 	ldw	r2,-28(fp)
+ 80151b4:	10800003 	ldbu	r2,0(r2)
+ 80151b8:	10803fcc 	andi	r2,r2,255
+ 80151bc:	108000a0 	cmpeqi	r2,r2,2
+ 80151c0:	1000021e 	bne	r2,zero,80151cc <OSQPostFront+0x38>
+        return (OS_ERR_EVENT_TYPE);
+ 80151c4:	00800044 	movi	r2,1
+ 80151c8:	00004506 	br	80152e0 <OSQPostFront+0x14c>
+  NIOS2_READ_STATUS (context);
+ 80151cc:	0005303a 	rdctl	r2,status
+ 80151d0:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80151d4:	e0fffd17 	ldw	r3,-12(fp)
+ 80151d8:	00bfff84 	movi	r2,-2
+ 80151dc:	1884703a 	and	r2,r3,r2
+ 80151e0:	1001703a 	wrctl	status,r2
+  return context;
+ 80151e4:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80151e8:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent->OSEventGrp != 0) {                    /* See if any task pending on queue              */
+ 80151ec:	e0bff917 	ldw	r2,-28(fp)
+ 80151f0:	10800283 	ldbu	r2,10(r2)
+ 80151f4:	10803fcc 	andi	r2,r2,255
+ 80151f8:	10000c26 	beq	r2,zero,801522c <OSQPostFront+0x98>
+                                                      /* Ready highest priority task waiting on event  */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+ 80151fc:	000f883a 	mov	r7,zero
+ 8015200:	01800104 	movi	r6,4
+ 8015204:	e17ff817 	ldw	r5,-32(fp)
+ 8015208:	e13ff917 	ldw	r4,-28(fp)
+ 801520c:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+ 8015210:	e0bfff17 	ldw	r2,-4(fp)
+ 8015214:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015218:	e0bffc17 	ldw	r2,-16(fp)
+ 801521c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find highest priority task ready to run       */
+ 8015220:	801166c0 	call	801166c <OS_Sched>
+        return (OS_ERR_NONE);
+ 8015224:	0005883a 	mov	r2,zero
+ 8015228:	00002d06 	br	80152e0 <OSQPostFront+0x14c>
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+ 801522c:	e0bff917 	ldw	r2,-28(fp)
+ 8015230:	10800117 	ldw	r2,4(r2)
+ 8015234:	e0bffe15 	stw	r2,-8(fp)
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+ 8015238:	e0bffe17 	ldw	r2,-8(fp)
+ 801523c:	10c0058b 	ldhu	r3,22(r2)
+ 8015240:	e0bffe17 	ldw	r2,-8(fp)
+ 8015244:	1080050b 	ldhu	r2,20(r2)
+ 8015248:	18ffffcc 	andi	r3,r3,65535
+ 801524c:	10bfffcc 	andi	r2,r2,65535
+ 8015250:	18800636 	bltu	r3,r2,801526c <OSQPostFront+0xd8>
+ 8015254:	e0bfff17 	ldw	r2,-4(fp)
+ 8015258:	e0bffb15 	stw	r2,-20(fp)
+ 801525c:	e0bffb17 	ldw	r2,-20(fp)
+ 8015260:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+ 8015264:	00800784 	movi	r2,30
+ 8015268:	00001d06 	br	80152e0 <OSQPostFront+0x14c>
+    }
+    if (pq->OSQOut == pq->OSQStart) {                 /* Wrap OUT ptr if we are at the 1st queue entry */
+ 801526c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015270:	10c00417 	ldw	r3,16(r2)
+ 8015274:	e0bffe17 	ldw	r2,-8(fp)
+ 8015278:	10800117 	ldw	r2,4(r2)
+ 801527c:	1880041e 	bne	r3,r2,8015290 <OSQPostFront+0xfc>
+        pq->OSQOut = pq->OSQEnd;
+ 8015280:	e0bffe17 	ldw	r2,-8(fp)
+ 8015284:	10c00217 	ldw	r3,8(r2)
+ 8015288:	e0bffe17 	ldw	r2,-8(fp)
+ 801528c:	10c00415 	stw	r3,16(r2)
+    }
+    pq->OSQOut--;
+ 8015290:	e0bffe17 	ldw	r2,-8(fp)
+ 8015294:	10800417 	ldw	r2,16(r2)
+ 8015298:	10ffff04 	addi	r3,r2,-4
+ 801529c:	e0bffe17 	ldw	r2,-8(fp)
+ 80152a0:	10c00415 	stw	r3,16(r2)
+    *pq->OSQOut = pmsg;                               /* Insert message into queue                     */
+ 80152a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80152a8:	10800417 	ldw	r2,16(r2)
+ 80152ac:	e0fff817 	ldw	r3,-32(fp)
+ 80152b0:	10c00015 	stw	r3,0(r2)
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+ 80152b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80152b8:	1080058b 	ldhu	r2,22(r2)
+ 80152bc:	10800044 	addi	r2,r2,1
+ 80152c0:	1007883a 	mov	r3,r2
+ 80152c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80152c8:	10c0058d 	sth	r3,22(r2)
+ 80152cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80152d0:	e0bffa15 	stw	r2,-24(fp)
+ 80152d4:	e0bffa17 	ldw	r2,-24(fp)
+ 80152d8:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 80152dc:	0005883a 	mov	r2,zero
+}
+ 80152e0:	e037883a 	mov	sp,fp
+ 80152e4:	dfc00117 	ldw	ra,4(sp)
+ 80152e8:	df000017 	ldw	fp,0(sp)
+ 80152ec:	dec00204 	addi	sp,sp,8
+ 80152f0:	f800283a 	ret
+
+080152f4 <OSQPostOpt>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_OPT_EN > 0
+INT8U  OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt)
+{
+ 80152f4:	defff504 	addi	sp,sp,-44
+ 80152f8:	dfc00a15 	stw	ra,40(sp)
+ 80152fc:	df000915 	stw	fp,36(sp)
+ 8015300:	df000904 	addi	fp,sp,36
+ 8015304:	e13ff915 	stw	r4,-28(fp)
+ 8015308:	e17ff815 	stw	r5,-32(fp)
+ 801530c:	3005883a 	mov	r2,r6
+ 8015310:	e0bff705 	stb	r2,-36(fp)
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015314:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+ 8015318:	e0bff917 	ldw	r2,-28(fp)
+ 801531c:	10800003 	ldbu	r2,0(r2)
+ 8015320:	10803fcc 	andi	r2,r2,255
+ 8015324:	108000a0 	cmpeqi	r2,r2,2
+ 8015328:	1000021e 	bne	r2,zero,8015334 <OSQPostOpt+0x40>
+        return (OS_ERR_EVENT_TYPE);
+ 801532c:	00800044 	movi	r2,1
+ 8015330:	00006a06 	br	80154dc <OSQPostOpt+0x1e8>
+  NIOS2_READ_STATUS (context);
+ 8015334:	0005303a 	rdctl	r2,status
+ 8015338:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801533c:	e0fffd17 	ldw	r3,-12(fp)
+ 8015340:	00bfff84 	movi	r2,-2
+ 8015344:	1884703a 	and	r2,r3,r2
+ 8015348:	1001703a 	wrctl	status,r2
+  return context;
+ 801534c:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015350:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent->OSEventGrp != 0x00) {                 /* See if any task pending on queue              */
+ 8015354:	e0bff917 	ldw	r2,-28(fp)
+ 8015358:	10800283 	ldbu	r2,10(r2)
+ 801535c:	10803fcc 	andi	r2,r2,255
+ 8015360:	10001d26 	beq	r2,zero,80153d8 <OSQPostOpt+0xe4>
+        if ((opt & OS_POST_OPT_BROADCAST) != 0x00) {  /* Do we need to post msg to ALL waiting tasks ? */
+ 8015364:	e0bff703 	ldbu	r2,-36(fp)
+ 8015368:	1080004c 	andi	r2,r2,1
+ 801536c:	10000b26 	beq	r2,zero,801539c <OSQPostOpt+0xa8>
+            while (pevent->OSEventGrp != 0) {         /* Yes, Post to ALL tasks waiting on queue       */
+ 8015370:	00000506 	br	8015388 <OSQPostOpt+0x94>
+                (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+ 8015374:	000f883a 	mov	r7,zero
+ 8015378:	01800104 	movi	r6,4
+ 801537c:	e17ff817 	ldw	r5,-32(fp)
+ 8015380:	e13ff917 	ldw	r4,-28(fp)
+ 8015384:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+            while (pevent->OSEventGrp != 0) {         /* Yes, Post to ALL tasks waiting on queue       */
+ 8015388:	e0bff917 	ldw	r2,-28(fp)
+ 801538c:	10800283 	ldbu	r2,10(r2)
+ 8015390:	10803fcc 	andi	r2,r2,255
+ 8015394:	103ff71e 	bne	r2,zero,8015374 <OSQPostOpt+0x80>
+ 8015398:	00000506 	br	80153b0 <OSQPostOpt+0xbc>
+            }
+        } else {                                      /* No,  Post to HPT waiting on queue             */
+            (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+ 801539c:	000f883a 	mov	r7,zero
+ 80153a0:	01800104 	movi	r6,4
+ 80153a4:	e17ff817 	ldw	r5,-32(fp)
+ 80153a8:	e13ff917 	ldw	r4,-28(fp)
+ 80153ac:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+ 80153b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80153b4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80153b8:	e0bffc17 	ldw	r2,-16(fp)
+ 80153bc:	1001703a 	wrctl	status,r2
+        }
+        OS_EXIT_CRITICAL();
+        if ((opt & OS_POST_OPT_NO_SCHED) == 0) {	  /* See if scheduler needs to be invoked          */
+ 80153c0:	e0bff703 	ldbu	r2,-36(fp)
+ 80153c4:	1080010c 	andi	r2,r2,4
+ 80153c8:	1000011e 	bne	r2,zero,80153d0 <OSQPostOpt+0xdc>
+            OS_Sched();                               /* Find highest priority task ready to run       */
+ 80153cc:	801166c0 	call	801166c <OS_Sched>
+        }
+        return (OS_ERR_NONE);
+ 80153d0:	0005883a 	mov	r2,zero
+ 80153d4:	00004106 	br	80154dc <OSQPostOpt+0x1e8>
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+ 80153d8:	e0bff917 	ldw	r2,-28(fp)
+ 80153dc:	10800117 	ldw	r2,4(r2)
+ 80153e0:	e0bffe15 	stw	r2,-8(fp)
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+ 80153e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80153e8:	10c0058b 	ldhu	r3,22(r2)
+ 80153ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80153f0:	1080050b 	ldhu	r2,20(r2)
+ 80153f4:	18ffffcc 	andi	r3,r3,65535
+ 80153f8:	10bfffcc 	andi	r2,r2,65535
+ 80153fc:	18800636 	bltu	r3,r2,8015418 <OSQPostOpt+0x124>
+ 8015400:	e0bfff17 	ldw	r2,-4(fp)
+ 8015404:	e0bffb15 	stw	r2,-20(fp)
+ 8015408:	e0bffb17 	ldw	r2,-20(fp)
+ 801540c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+ 8015410:	00800784 	movi	r2,30
+ 8015414:	00003106 	br	80154dc <OSQPostOpt+0x1e8>
+    }
+    if ((opt & OS_POST_OPT_FRONT) != 0x00) {          /* Do we post to the FRONT of the queue?         */
+ 8015418:	e0bff703 	ldbu	r2,-36(fp)
+ 801541c:	1080008c 	andi	r2,r2,2
+ 8015420:	10001326 	beq	r2,zero,8015470 <OSQPostOpt+0x17c>
+        if (pq->OSQOut == pq->OSQStart) {             /* Yes, Post as LIFO, Wrap OUT pointer if we ... */
+ 8015424:	e0bffe17 	ldw	r2,-8(fp)
+ 8015428:	10c00417 	ldw	r3,16(r2)
+ 801542c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015430:	10800117 	ldw	r2,4(r2)
+ 8015434:	1880041e 	bne	r3,r2,8015448 <OSQPostOpt+0x154>
+            pq->OSQOut = pq->OSQEnd;                  /*      ... are at the 1st queue entry           */
+ 8015438:	e0bffe17 	ldw	r2,-8(fp)
+ 801543c:	10c00217 	ldw	r3,8(r2)
+ 8015440:	e0bffe17 	ldw	r2,-8(fp)
+ 8015444:	10c00415 	stw	r3,16(r2)
+        }
+        pq->OSQOut--;
+ 8015448:	e0bffe17 	ldw	r2,-8(fp)
+ 801544c:	10800417 	ldw	r2,16(r2)
+ 8015450:	10ffff04 	addi	r3,r2,-4
+ 8015454:	e0bffe17 	ldw	r2,-8(fp)
+ 8015458:	10c00415 	stw	r3,16(r2)
+        *pq->OSQOut = pmsg;                           /*      Insert message into queue                */
+ 801545c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015460:	10800417 	ldw	r2,16(r2)
+ 8015464:	e0fff817 	ldw	r3,-32(fp)
+ 8015468:	10c00015 	stw	r3,0(r2)
+ 801546c:	00001006 	br	80154b0 <OSQPostOpt+0x1bc>
+    } else {                                          /* No,  Post as FIFO                             */
+        *pq->OSQIn++ = pmsg;                          /*      Insert message into queue                */
+ 8015470:	e0bffe17 	ldw	r2,-8(fp)
+ 8015474:	10800317 	ldw	r2,12(r2)
+ 8015478:	11000104 	addi	r4,r2,4
+ 801547c:	e0fffe17 	ldw	r3,-8(fp)
+ 8015480:	19000315 	stw	r4,12(r3)
+ 8015484:	e0fff817 	ldw	r3,-32(fp)
+ 8015488:	10c00015 	stw	r3,0(r2)
+        if (pq->OSQIn == pq->OSQEnd) {                /*      Wrap IN ptr if we are at end of queue    */
+ 801548c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015490:	10c00317 	ldw	r3,12(r2)
+ 8015494:	e0bffe17 	ldw	r2,-8(fp)
+ 8015498:	10800217 	ldw	r2,8(r2)
+ 801549c:	1880041e 	bne	r3,r2,80154b0 <OSQPostOpt+0x1bc>
+            pq->OSQIn = pq->OSQStart;
+ 80154a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80154a4:	10c00117 	ldw	r3,4(r2)
+ 80154a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80154ac:	10c00315 	stw	r3,12(r2)
+        }
+    }
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+ 80154b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80154b4:	1080058b 	ldhu	r2,22(r2)
+ 80154b8:	10800044 	addi	r2,r2,1
+ 80154bc:	1007883a 	mov	r3,r2
+ 80154c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80154c4:	10c0058d 	sth	r3,22(r2)
+ 80154c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80154cc:	e0bffa15 	stw	r2,-24(fp)
+ 80154d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80154d4:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 80154d8:	0005883a 	mov	r2,zero
+}
+ 80154dc:	e037883a 	mov	sp,fp
+ 80154e0:	dfc00117 	ldw	ra,4(sp)
+ 80154e4:	df000017 	ldw	fp,0(sp)
+ 80154e8:	dec00204 	addi	sp,sp,8
+ 80154ec:	f800283a 	ret
+
+080154f0 <OSQQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_Q_QUERY_EN > 0
+INT8U  OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data)
+{
+ 80154f0:	defff604 	addi	sp,sp,-40
+ 80154f4:	df000915 	stw	fp,36(sp)
+ 80154f8:	df000904 	addi	fp,sp,36
+ 80154fc:	e13ff815 	stw	r4,-32(fp)
+ 8015500:	e17ff715 	stw	r5,-36(fp)
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015504:	e03ffc15 	stw	zero,-16(fp)
+    }
+    if (p_q_data == (OS_Q_DATA *)0) {                  /* Validate 'p_q_data'                          */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+ 8015508:	e0bff817 	ldw	r2,-32(fp)
+ 801550c:	10800003 	ldbu	r2,0(r2)
+ 8015510:	10803fcc 	andi	r2,r2,255
+ 8015514:	108000a0 	cmpeqi	r2,r2,2
+ 8015518:	1000021e 	bne	r2,zero,8015524 <OSQQuery+0x34>
+        return (OS_ERR_EVENT_TYPE);
+ 801551c:	00800044 	movi	r2,1
+ 8015520:	00003e06 	br	801561c <OSQQuery+0x12c>
+  NIOS2_READ_STATUS (context);
+ 8015524:	0005303a 	rdctl	r2,status
+ 8015528:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801552c:	e0fffa17 	ldw	r3,-24(fp)
+ 8015530:	00bfff84 	movi	r2,-2
+ 8015534:	1884703a 	and	r2,r3,r2
+ 8015538:	1001703a 	wrctl	status,r2
+  return context;
+ 801553c:	e0bffa17 	ldw	r2,-24(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015540:	e0bffc15 	stw	r2,-16(fp)
+    p_q_data->OSEventGrp = pevent->OSEventGrp;         /* Copy message queue wait list                 */
+ 8015544:	e0bff817 	ldw	r2,-32(fp)
+ 8015548:	10c00283 	ldbu	r3,10(r2)
+ 801554c:	e0bff717 	ldw	r2,-36(fp)
+ 8015550:	10c002c5 	stb	r3,11(r2)
+    psrc                 = &pevent->OSEventTbl[0];
+ 8015554:	e0bff817 	ldw	r2,-32(fp)
+ 8015558:	108002c4 	addi	r2,r2,11
+ 801555c:	e0bffe15 	stw	r2,-8(fp)
+    pdest                = &p_q_data->OSEventTbl[0];
+ 8015560:	e0bff717 	ldw	r2,-36(fp)
+ 8015564:	10800204 	addi	r2,r2,8
+ 8015568:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 801556c:	e03fffc5 	stb	zero,-1(fp)
+ 8015570:	00000b06 	br	80155a0 <OSQQuery+0xb0>
+        *pdest++ = *psrc++;
+ 8015574:	e0fffe17 	ldw	r3,-8(fp)
+ 8015578:	18800044 	addi	r2,r3,1
+ 801557c:	e0bffe15 	stw	r2,-8(fp)
+ 8015580:	e0bffd17 	ldw	r2,-12(fp)
+ 8015584:	11000044 	addi	r4,r2,1
+ 8015588:	e13ffd15 	stw	r4,-12(fp)
+ 801558c:	18c00003 	ldbu	r3,0(r3)
+ 8015590:	10c00005 	stb	r3,0(r2)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8015594:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015598:	10800044 	addi	r2,r2,1
+ 801559c:	e0bfffc5 	stb	r2,-1(fp)
+ 80155a0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80155a4:	108000f0 	cmpltui	r2,r2,3
+ 80155a8:	103ff21e 	bne	r2,zero,8015574 <OSQQuery+0x84>
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;
+ 80155ac:	e0bff817 	ldw	r2,-32(fp)
+ 80155b0:	10800117 	ldw	r2,4(r2)
+ 80155b4:	e0bffb15 	stw	r2,-20(fp)
+    if (pq->OSQEntries > 0) {
+ 80155b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80155bc:	1080058b 	ldhu	r2,22(r2)
+ 80155c0:	10bfffcc 	andi	r2,r2,65535
+ 80155c4:	10000626 	beq	r2,zero,80155e0 <OSQQuery+0xf0>
+        p_q_data->OSMsg = *pq->OSQOut;                 /* Get next message to return if available      */
+ 80155c8:	e0bffb17 	ldw	r2,-20(fp)
+ 80155cc:	10800417 	ldw	r2,16(r2)
+ 80155d0:	10c00017 	ldw	r3,0(r2)
+ 80155d4:	e0bff717 	ldw	r2,-36(fp)
+ 80155d8:	10c00015 	stw	r3,0(r2)
+ 80155dc:	00000206 	br	80155e8 <OSQQuery+0xf8>
+    } else {
+        p_q_data->OSMsg = (void *)0;
+ 80155e0:	e0bff717 	ldw	r2,-36(fp)
+ 80155e4:	10000015 	stw	zero,0(r2)
+    }
+    p_q_data->OSNMsgs = pq->OSQEntries;
+ 80155e8:	e0bffb17 	ldw	r2,-20(fp)
+ 80155ec:	10c0058b 	ldhu	r3,22(r2)
+ 80155f0:	e0bff717 	ldw	r2,-36(fp)
+ 80155f4:	10c0010d 	sth	r3,4(r2)
+    p_q_data->OSQSize = pq->OSQSize;
+ 80155f8:	e0bffb17 	ldw	r2,-20(fp)
+ 80155fc:	10c0050b 	ldhu	r3,20(r2)
+ 8015600:	e0bff717 	ldw	r2,-36(fp)
+ 8015604:	10c0018d 	sth	r3,6(r2)
+ 8015608:	e0bffc17 	ldw	r2,-16(fp)
+ 801560c:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015610:	e0bff917 	ldw	r2,-28(fp)
+ 8015614:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8015618:	0005883a 	mov	r2,zero
+}
+ 801561c:	e037883a 	mov	sp,fp
+ 8015620:	df000017 	ldw	fp,0(sp)
+ 8015624:	dec00104 	addi	sp,sp,4
+ 8015628:	f800283a 	ret
+
+0801562c <OS_QInit>:
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_QInit (void)
+{
+ 801562c:	defffb04 	addi	sp,sp,-20
+ 8015630:	dfc00415 	stw	ra,16(sp)
+ 8015634:	df000315 	stw	fp,12(sp)
+ 8015638:	df000304 	addi	fp,sp,12
+    OS_Q   *pq1;
+    OS_Q   *pq2;
+
+
+
+    OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl));  /* Clear the queue table                          */
+ 801563c:	01407804 	movi	r5,480
+ 8015640:	010201b4 	movhi	r4,2054
+ 8015644:	212f7304 	addi	r4,r4,-16948
+ 8015648:	80115b00 	call	80115b0 <OS_MemClr>
+    pq1 = &OSQTbl[0];
+ 801564c:	008201b4 	movhi	r2,2054
+ 8015650:	10af7304 	addi	r2,r2,-16948
+ 8015654:	e0bffe15 	stw	r2,-8(fp)
+    pq2 = &OSQTbl[1];
+ 8015658:	008201b4 	movhi	r2,2054
+ 801565c:	10af7904 	addi	r2,r2,-16924
+ 8015660:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_QS - 1); i++) {          /* Init. list of free QUEUE control blocks        */
+ 8015664:	e03fff8d 	sth	zero,-2(fp)
+ 8015668:	00000c06 	br	801569c <OS_QInit+0x70>
+        pq1->OSQPtr = pq2;
+ 801566c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015670:	e0fffd17 	ldw	r3,-12(fp)
+ 8015674:	10c00015 	stw	r3,0(r2)
+        pq1++;
+ 8015678:	e0bffe17 	ldw	r2,-8(fp)
+ 801567c:	10800604 	addi	r2,r2,24
+ 8015680:	e0bffe15 	stw	r2,-8(fp)
+        pq2++;
+ 8015684:	e0bffd17 	ldw	r2,-12(fp)
+ 8015688:	10800604 	addi	r2,r2,24
+ 801568c:	e0bffd15 	stw	r2,-12(fp)
+    for (i = 0; i < (OS_MAX_QS - 1); i++) {          /* Init. list of free QUEUE control blocks        */
+ 8015690:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8015694:	10800044 	addi	r2,r2,1
+ 8015698:	e0bfff8d 	sth	r2,-2(fp)
+ 801569c:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80156a0:	108004f0 	cmpltui	r2,r2,19
+ 80156a4:	103ff11e 	bne	r2,zero,801566c <OS_QInit+0x40>
+    }
+    pq1->OSQPtr = (OS_Q *)0;
+ 80156a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80156ac:	10000015 	stw	zero,0(r2)
+    OSQFreeList = &OSQTbl[0];
+ 80156b0:	008201b4 	movhi	r2,2054
+ 80156b4:	10af7304 	addi	r2,r2,-16948
+ 80156b8:	d0a05415 	stw	r2,-32432(gp)
+#endif
+}
+ 80156bc:	0001883a 	nop
+ 80156c0:	e037883a 	mov	sp,fp
+ 80156c4:	dfc00117 	ldw	ra,4(sp)
+ 80156c8:	df000017 	ldw	fp,0(sp)
+ 80156cc:	dec00204 	addi	sp,sp,8
+ 80156d0:	f800283a 	ret
+
+080156d4 <OSSemAccept>:
+*********************************************************************************************************
+*/
+
+#if OS_SEM_ACCEPT_EN > 0
+INT16U  OSSemAccept (OS_EVENT *pevent)
+{
+ 80156d4:	defffa04 	addi	sp,sp,-24
+ 80156d8:	df000515 	stw	fp,20(sp)
+ 80156dc:	df000504 	addi	fp,sp,20
+ 80156e0:	e13ffb15 	stw	r4,-20(fp)
+    INT16U     cnt;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 80156e4:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+ 80156e8:	e0bffb17 	ldw	r2,-20(fp)
+ 80156ec:	10800003 	ldbu	r2,0(r2)
+ 80156f0:	10803fcc 	andi	r2,r2,255
+ 80156f4:	108000e0 	cmpeqi	r2,r2,3
+ 80156f8:	1000021e 	bne	r2,zero,8015704 <OSSemAccept+0x30>
+        return (0);
+ 80156fc:	0005883a 	mov	r2,zero
+ 8015700:	00001806 	br	8015764 <OSSemAccept+0x90>
+  NIOS2_READ_STATUS (context);
+ 8015704:	0005303a 	rdctl	r2,status
+ 8015708:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801570c:	e0fffd17 	ldw	r3,-12(fp)
+ 8015710:	00bfff84 	movi	r2,-2
+ 8015714:	1884703a 	and	r2,r3,r2
+ 8015718:	1001703a 	wrctl	status,r2
+  return context;
+ 801571c:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015720:	e0bfff15 	stw	r2,-4(fp)
+    cnt = pevent->OSEventCnt;
+ 8015724:	e0bffb17 	ldw	r2,-20(fp)
+ 8015728:	1080020b 	ldhu	r2,8(r2)
+ 801572c:	e0bffe8d 	sth	r2,-6(fp)
+    if (cnt > 0) {                                    /* See if resource is available                  */
+ 8015730:	e0bffe8b 	ldhu	r2,-6(fp)
+ 8015734:	10000626 	beq	r2,zero,8015750 <OSSemAccept+0x7c>
+        pevent->OSEventCnt--;                         /* Yes, decrement semaphore and notify caller    */
+ 8015738:	e0bffb17 	ldw	r2,-20(fp)
+ 801573c:	1080020b 	ldhu	r2,8(r2)
+ 8015740:	10bfffc4 	addi	r2,r2,-1
+ 8015744:	1007883a 	mov	r3,r2
+ 8015748:	e0bffb17 	ldw	r2,-20(fp)
+ 801574c:	10c0020d 	sth	r3,8(r2)
+ 8015750:	e0bfff17 	ldw	r2,-4(fp)
+ 8015754:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015758:	e0bffc17 	ldw	r2,-16(fp)
+ 801575c:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (cnt);                                     /* Return semaphore count                        */
+ 8015760:	e0bffe8b 	ldhu	r2,-6(fp)
+}
+ 8015764:	e037883a 	mov	sp,fp
+ 8015768:	df000017 	ldw	fp,0(sp)
+ 801576c:	dec00104 	addi	sp,sp,4
+ 8015770:	f800283a 	ret
+
+08015774 <OSSemCreate>:
+*              == (void *)0  if no event control blocks were available
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSSemCreate (INT16U cnt)
+{
+ 8015774:	defff904 	addi	sp,sp,-28
+ 8015778:	dfc00615 	stw	ra,24(sp)
+ 801577c:	df000515 	stw	fp,20(sp)
+ 8015780:	df000504 	addi	fp,sp,20
+ 8015784:	2005883a 	mov	r2,r4
+ 8015788:	e0bffb0d 	sth	r2,-20(fp)
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 801578c:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8015790:	d0a05703 	ldbu	r2,-32420(gp)
+ 8015794:	10803fcc 	andi	r2,r2,255
+ 8015798:	10000226 	beq	r2,zero,80157a4 <OSSemCreate+0x30>
+        return ((OS_EVENT *)0);                            /* ... can't CREATE from an ISR             */
+ 801579c:	0005883a 	mov	r2,zero
+ 80157a0:	00002506 	br	8015838 <OSSemCreate+0xc4>
+  NIOS2_READ_STATUS (context);
+ 80157a4:	0005303a 	rdctl	r2,status
+ 80157a8:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80157ac:	e0fffd17 	ldw	r3,-12(fp)
+ 80157b0:	00bfff84 	movi	r2,-2
+ 80157b4:	1884703a 	and	r2,r3,r2
+ 80157b8:	1001703a 	wrctl	status,r2
+  return context;
+ 80157bc:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80157c0:	e0bfff15 	stw	r2,-4(fp)
+    pevent = OSEventFreeList;                              /* Get next free event control block        */
+ 80157c4:	d0a05617 	ldw	r2,-32424(gp)
+ 80157c8:	e0bffe15 	stw	r2,-8(fp)
+    if (OSEventFreeList != (OS_EVENT *)0) {                /* See if pool of free ECB pool was empty   */
+ 80157cc:	d0a05617 	ldw	r2,-32424(gp)
+ 80157d0:	10000326 	beq	r2,zero,80157e0 <OSSemCreate+0x6c>
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+ 80157d4:	d0a05617 	ldw	r2,-32424(gp)
+ 80157d8:	10800117 	ldw	r2,4(r2)
+ 80157dc:	d0a05615 	stw	r2,-32424(gp)
+ 80157e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80157e4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80157e8:	e0bffc17 	ldw	r2,-16(fp)
+ 80157ec:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {                         /* Get an event control block               */
+ 80157f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80157f4:	10000f26 	beq	r2,zero,8015834 <OSSemCreate+0xc0>
+        pevent->OSEventType    = OS_EVENT_TYPE_SEM;
+ 80157f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80157fc:	00c000c4 	movi	r3,3
+ 8015800:	10c00005 	stb	r3,0(r2)
+        pevent->OSEventCnt     = cnt;                      /* Set semaphore value                      */
+ 8015804:	e0bffe17 	ldw	r2,-8(fp)
+ 8015808:	e0fffb0b 	ldhu	r3,-20(fp)
+ 801580c:	10c0020d 	sth	r3,8(r2)
+        pevent->OSEventPtr     = (void *)0;                /* Unlink from ECB free list                */
+ 8015810:	e0bffe17 	ldw	r2,-8(fp)
+ 8015814:	10000115 	stw	zero,4(r2)
+#if OS_EVENT_NAME_SIZE > 1
+        pevent->OSEventName[0] = '?';                      /* Unknown name                             */
+ 8015818:	e0bffe17 	ldw	r2,-8(fp)
+ 801581c:	00c00fc4 	movi	r3,63
+ 8015820:	10c00385 	stb	r3,14(r2)
+        pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8015824:	e0bffe17 	ldw	r2,-8(fp)
+ 8015828:	100003c5 	stb	zero,15(r2)
+#endif
+        OS_EventWaitListInit(pevent);                      /* Initialize to 'nobody waiting' on sem.   */
+ 801582c:	e13ffe17 	ldw	r4,-8(fp)
+ 8015830:	80112580 	call	8011258 <OS_EventWaitListInit>
+    }
+    return (pevent);
+ 8015834:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8015838:	e037883a 	mov	sp,fp
+ 801583c:	dfc00117 	ldw	ra,4(sp)
+ 8015840:	df000017 	ldw	fp,0(sp)
+ 8015844:	dec00204 	addi	sp,sp,8
+ 8015848:	f800283a 	ret
+
+0801584c <OSSemDel>:
+*********************************************************************************************************
+*/
+
+#if OS_SEM_DEL_EN > 0
+OS_EVENT  *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+ 801584c:	defff304 	addi	sp,sp,-52
+ 8015850:	dfc00c15 	stw	ra,48(sp)
+ 8015854:	df000b15 	stw	fp,44(sp)
+ 8015858:	df000b04 	addi	fp,sp,44
+ 801585c:	e13ff715 	stw	r4,-36(fp)
+ 8015860:	2805883a 	mov	r2,r5
+ 8015864:	e1bff515 	stw	r6,-44(fp)
+ 8015868:	e0bff605 	stb	r2,-40(fp)
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 801586c:	e03ffd15 	stw	zero,-12(fp)
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+ 8015870:	e0bff717 	ldw	r2,-36(fp)
+ 8015874:	10800003 	ldbu	r2,0(r2)
+ 8015878:	10803fcc 	andi	r2,r2,255
+ 801587c:	108000e0 	cmpeqi	r2,r2,3
+ 8015880:	1000051e 	bne	r2,zero,8015898 <OSSemDel+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8015884:	e0bff517 	ldw	r2,-44(fp)
+ 8015888:	00c00044 	movi	r3,1
+ 801588c:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 8015890:	e0bff717 	ldw	r2,-36(fp)
+ 8015894:	00006d06 	br	8015a4c <OSSemDel+0x200>
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+ 8015898:	d0a05703 	ldbu	r2,-32420(gp)
+ 801589c:	10803fcc 	andi	r2,r2,255
+ 80158a0:	10000526 	beq	r2,zero,80158b8 <OSSemDel+0x6c>
+        *perr = OS_ERR_DEL_ISR;                             /* ... can't DELETE from an ISR             */
+ 80158a4:	e0bff517 	ldw	r2,-44(fp)
+ 80158a8:	00c003c4 	movi	r3,15
+ 80158ac:	10c00005 	stb	r3,0(r2)
+        return (pevent);
+ 80158b0:	e0bff717 	ldw	r2,-36(fp)
+ 80158b4:	00006506 	br	8015a4c <OSSemDel+0x200>
+  NIOS2_READ_STATUS (context);
+ 80158b8:	0005303a 	rdctl	r2,status
+ 80158bc:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80158c0:	e0fffc17 	ldw	r3,-16(fp)
+ 80158c4:	00bfff84 	movi	r2,-2
+ 80158c8:	1884703a 	and	r2,r3,r2
+ 80158cc:	1001703a 	wrctl	status,r2
+  return context;
+ 80158d0:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 80158d4:	e0bffd15 	stw	r2,-12(fp)
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on semaphore    */
+ 80158d8:	e0bff717 	ldw	r2,-36(fp)
+ 80158dc:	10800283 	ldbu	r2,10(r2)
+ 80158e0:	10803fcc 	andi	r2,r2,255
+ 80158e4:	10000326 	beq	r2,zero,80158f4 <OSSemDel+0xa8>
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+ 80158e8:	00800044 	movi	r2,1
+ 80158ec:	e0bfffc5 	stb	r2,-1(fp)
+ 80158f0:	00000106 	br	80158f8 <OSSemDel+0xac>
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+ 80158f4:	e03fffc5 	stb	zero,-1(fp)
+    }
+    switch (opt) {
+ 80158f8:	e0bff603 	ldbu	r2,-40(fp)
+ 80158fc:	10000326 	beq	r2,zero,801590c <OSSemDel+0xc0>
+ 8015900:	10800060 	cmpeqi	r2,r2,1
+ 8015904:	1000281e 	bne	r2,zero,80159a8 <OSSemDel+0x15c>
+ 8015908:	00004506 	br	8015a20 <OSSemDel+0x1d4>
+        case OS_DEL_NO_PEND:                               /* Delete semaphore only if no task waiting */
+             if (tasks_waiting == OS_FALSE) {
+ 801590c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015910:	1000161e 	bne	r2,zero,801596c <OSSemDel+0x120>
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+ 8015914:	e0bff717 	ldw	r2,-36(fp)
+ 8015918:	00c00fc4 	movi	r3,63
+ 801591c:	10c00385 	stb	r3,14(r2)
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+ 8015920:	e0bff717 	ldw	r2,-36(fp)
+ 8015924:	100003c5 	stb	zero,15(r2)
+#endif
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+ 8015928:	e0bff717 	ldw	r2,-36(fp)
+ 801592c:	10000005 	stb	zero,0(r2)
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+ 8015930:	d0e05617 	ldw	r3,-32424(gp)
+ 8015934:	e0bff717 	ldw	r2,-36(fp)
+ 8015938:	10c00115 	stw	r3,4(r2)
+                 pevent->OSEventCnt     = 0;
+ 801593c:	e0bff717 	ldw	r2,-36(fp)
+ 8015940:	1000020d 	sth	zero,8(r2)
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+ 8015944:	e0bff717 	ldw	r2,-36(fp)
+ 8015948:	d0a05615 	stw	r2,-32424(gp)
+ 801594c:	e0bffd17 	ldw	r2,-12(fp)
+ 8015950:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015954:	e0bffb17 	ldw	r2,-20(fp)
+ 8015958:	1001703a 	wrctl	status,r2
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+ 801595c:	e0bff517 	ldw	r2,-44(fp)
+ 8015960:	10000005 	stb	zero,0(r2)
+                 pevent_return          = (OS_EVENT *)0;   /* Semaphore has been deleted               */
+ 8015964:	e03ffe15 	stw	zero,-8(fp)
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+ 8015968:	00003706 	br	8015a48 <OSSemDel+0x1fc>
+ 801596c:	e0bffd17 	ldw	r2,-12(fp)
+ 8015970:	e0bffa15 	stw	r2,-24(fp)
+ 8015974:	e0bffa17 	ldw	r2,-24(fp)
+ 8015978:	1001703a 	wrctl	status,r2
+                 *perr                  = OS_ERR_TASK_WAITING;
+ 801597c:	e0bff517 	ldw	r2,-44(fp)
+ 8015980:	00c01244 	movi	r3,73
+ 8015984:	10c00005 	stb	r3,0(r2)
+                 pevent_return          = pevent;
+ 8015988:	e0bff717 	ldw	r2,-36(fp)
+ 801598c:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8015990:	00002d06 	br	8015a48 <OSSemDel+0x1fc>
+
+        case OS_DEL_ALWAYS:                                /* Always delete the semaphore              */
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for semaphore    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK);
+ 8015994:	000f883a 	mov	r7,zero
+ 8015998:	01800044 	movi	r6,1
+ 801599c:	000b883a 	mov	r5,zero
+ 80159a0:	e13ff717 	ldw	r4,-36(fp)
+ 80159a4:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for semaphore    */
+ 80159a8:	e0bff717 	ldw	r2,-36(fp)
+ 80159ac:	10800283 	ldbu	r2,10(r2)
+ 80159b0:	10803fcc 	andi	r2,r2,255
+ 80159b4:	103ff71e 	bne	r2,zero,8015994 <OSSemDel+0x148>
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+ 80159b8:	e0bff717 	ldw	r2,-36(fp)
+ 80159bc:	00c00fc4 	movi	r3,63
+ 80159c0:	10c00385 	stb	r3,14(r2)
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+ 80159c4:	e0bff717 	ldw	r2,-36(fp)
+ 80159c8:	100003c5 	stb	zero,15(r2)
+#endif
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+ 80159cc:	e0bff717 	ldw	r2,-36(fp)
+ 80159d0:	10000005 	stb	zero,0(r2)
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+ 80159d4:	d0e05617 	ldw	r3,-32424(gp)
+ 80159d8:	e0bff717 	ldw	r2,-36(fp)
+ 80159dc:	10c00115 	stw	r3,4(r2)
+             pevent->OSEventCnt     = 0;
+ 80159e0:	e0bff717 	ldw	r2,-36(fp)
+ 80159e4:	1000020d 	sth	zero,8(r2)
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+ 80159e8:	e0bff717 	ldw	r2,-36(fp)
+ 80159ec:	d0a05615 	stw	r2,-32424(gp)
+ 80159f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80159f4:	e0bff915 	stw	r2,-28(fp)
+ 80159f8:	e0bff917 	ldw	r2,-28(fp)
+ 80159fc:	1001703a 	wrctl	status,r2
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+ 8015a00:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015a04:	10800058 	cmpnei	r2,r2,1
+ 8015a08:	1000011e 	bne	r2,zero,8015a10 <OSSemDel+0x1c4>
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+ 8015a0c:	801166c0 	call	801166c <OS_Sched>
+             }
+             *perr                  = OS_ERR_NONE;
+ 8015a10:	e0bff517 	ldw	r2,-44(fp)
+ 8015a14:	10000005 	stb	zero,0(r2)
+             pevent_return          = (OS_EVENT *)0;       /* Semaphore has been deleted               */
+ 8015a18:	e03ffe15 	stw	zero,-8(fp)
+             break;
+ 8015a1c:	00000a06 	br	8015a48 <OSSemDel+0x1fc>
+ 8015a20:	e0bffd17 	ldw	r2,-12(fp)
+ 8015a24:	e0bff815 	stw	r2,-32(fp)
+ 8015a28:	e0bff817 	ldw	r2,-32(fp)
+ 8015a2c:	1001703a 	wrctl	status,r2
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+ 8015a30:	e0bff517 	ldw	r2,-44(fp)
+ 8015a34:	00c001c4 	movi	r3,7
+ 8015a38:	10c00005 	stb	r3,0(r2)
+             pevent_return          = pevent;
+ 8015a3c:	e0bff717 	ldw	r2,-36(fp)
+ 8015a40:	e0bffe15 	stw	r2,-8(fp)
+             break;
+ 8015a44:	0001883a 	nop
+    }
+    return (pevent_return);
+ 8015a48:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8015a4c:	e037883a 	mov	sp,fp
+ 8015a50:	dfc00117 	ldw	ra,4(sp)
+ 8015a54:	df000017 	ldw	fp,0(sp)
+ 8015a58:	dec00204 	addi	sp,sp,8
+ 8015a5c:	f800283a 	ret
+
+08015a60 <OSSemPend>:
+* Returns    : none
+*********************************************************************************************************
+*/
+/*$PAGE*/
+void  OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+ 8015a60:	defff504 	addi	sp,sp,-44
+ 8015a64:	dfc00a15 	stw	ra,40(sp)
+ 8015a68:	df000915 	stw	fp,36(sp)
+ 8015a6c:	df000904 	addi	fp,sp,36
+ 8015a70:	e13ff915 	stw	r4,-28(fp)
+ 8015a74:	2805883a 	mov	r2,r5
+ 8015a78:	e1bff715 	stw	r6,-36(fp)
+ 8015a7c:	e0bff80d 	sth	r2,-32(fp)
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015a80:	e03fff15 	stw	zero,-4(fp)
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+ 8015a84:	e0bff917 	ldw	r2,-28(fp)
+ 8015a88:	10800003 	ldbu	r2,0(r2)
+ 8015a8c:	10803fcc 	andi	r2,r2,255
+ 8015a90:	108000e0 	cmpeqi	r2,r2,3
+ 8015a94:	1000041e 	bne	r2,zero,8015aa8 <OSSemPend+0x48>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8015a98:	e0bff717 	ldw	r2,-36(fp)
+ 8015a9c:	00c00044 	movi	r3,1
+ 8015aa0:	10c00005 	stb	r3,0(r2)
+        return;
+ 8015aa4:	00006206 	br	8015c30 <OSSemPend+0x1d0>
+    }
+    if (OSIntNesting > 0) {                           /* See if called from ISR ...                    */
+ 8015aa8:	d0a05703 	ldbu	r2,-32420(gp)
+ 8015aac:	10803fcc 	andi	r2,r2,255
+ 8015ab0:	10000426 	beq	r2,zero,8015ac4 <OSSemPend+0x64>
+        *perr = OS_ERR_PEND_ISR;                      /* ... can't PEND from an ISR                    */
+ 8015ab4:	e0bff717 	ldw	r2,-36(fp)
+ 8015ab8:	00c00084 	movi	r3,2
+ 8015abc:	10c00005 	stb	r3,0(r2)
+        return;
+ 8015ac0:	00005b06 	br	8015c30 <OSSemPend+0x1d0>
+    }
+    if (OSLockNesting > 0) {                          /* See if called with scheduler locked ...       */
+ 8015ac4:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8015ac8:	10803fcc 	andi	r2,r2,255
+ 8015acc:	10000426 	beq	r2,zero,8015ae0 <OSSemPend+0x80>
+        *perr = OS_ERR_PEND_LOCKED;                   /* ... can't PEND when locked                    */
+ 8015ad0:	e0bff717 	ldw	r2,-36(fp)
+ 8015ad4:	00c00344 	movi	r3,13
+ 8015ad8:	10c00005 	stb	r3,0(r2)
+        return;
+ 8015adc:	00005406 	br	8015c30 <OSSemPend+0x1d0>
+  NIOS2_READ_STATUS (context);
+ 8015ae0:	0005303a 	rdctl	r2,status
+ 8015ae4:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015ae8:	e0fffe17 	ldw	r3,-8(fp)
+ 8015aec:	00bfff84 	movi	r2,-2
+ 8015af0:	1884703a 	and	r2,r3,r2
+ 8015af4:	1001703a 	wrctl	status,r2
+  return context;
+ 8015af8:	e0bffe17 	ldw	r2,-8(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015afc:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent->OSEventCnt > 0) {                     /* If sem. is positive, resource available ...   */
+ 8015b00:	e0bff917 	ldw	r2,-28(fp)
+ 8015b04:	1080020b 	ldhu	r2,8(r2)
+ 8015b08:	10bfffcc 	andi	r2,r2,65535
+ 8015b0c:	10000d26 	beq	r2,zero,8015b44 <OSSemPend+0xe4>
+        pevent->OSEventCnt--;                         /* ... decrement semaphore only if positive.     */
+ 8015b10:	e0bff917 	ldw	r2,-28(fp)
+ 8015b14:	1080020b 	ldhu	r2,8(r2)
+ 8015b18:	10bfffc4 	addi	r2,r2,-1
+ 8015b1c:	1007883a 	mov	r3,r2
+ 8015b20:	e0bff917 	ldw	r2,-28(fp)
+ 8015b24:	10c0020d 	sth	r3,8(r2)
+ 8015b28:	e0bfff17 	ldw	r2,-4(fp)
+ 8015b2c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015b30:	e0bffd17 	ldw	r2,-12(fp)
+ 8015b34:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+ 8015b38:	e0bff717 	ldw	r2,-36(fp)
+ 8015b3c:	10000005 	stb	zero,0(r2)
+        return;
+ 8015b40:	00003b06 	br	8015c30 <OSSemPend+0x1d0>
+    }
+                                                      /* Otherwise, must wait until event occurs       */
+    OSTCBCur->OSTCBStat     |= OS_STAT_SEM;           /* Resource not available, pend on semaphore     */
+ 8015b44:	d0a05817 	ldw	r2,-32416(gp)
+ 8015b48:	10c00c03 	ldbu	r3,48(r2)
+ 8015b4c:	d0a05817 	ldw	r2,-32416(gp)
+ 8015b50:	18c00054 	ori	r3,r3,1
+ 8015b54:	10c00c05 	stb	r3,48(r2)
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+ 8015b58:	d0a05817 	ldw	r2,-32416(gp)
+ 8015b5c:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBDly       = timeout;               /* Store pend timeout in TCB                     */
+ 8015b60:	d0a05817 	ldw	r2,-32416(gp)
+ 8015b64:	e0fff80b 	ldhu	r3,-32(fp)
+ 8015b68:	10c00b8d 	sth	r3,46(r2)
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+ 8015b6c:	e13ff917 	ldw	r4,-28(fp)
+ 8015b70:	8010e600 	call	8010e60 <OS_EventTaskWait>
+ 8015b74:	e0bfff17 	ldw	r2,-4(fp)
+ 8015b78:	e0bffb15 	stw	r2,-20(fp)
+ 8015b7c:	e0bffb17 	ldw	r2,-20(fp)
+ 8015b80:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+ 8015b84:	801166c0 	call	801166c <OS_Sched>
+  NIOS2_READ_STATUS (context);
+ 8015b88:	0005303a 	rdctl	r2,status
+ 8015b8c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015b90:	e0fffc17 	ldw	r3,-16(fp)
+ 8015b94:	00bfff84 	movi	r2,-2
+ 8015b98:	1884703a 	and	r2,r3,r2
+ 8015b9c:	1001703a 	wrctl	status,r2
+  return context;
+ 8015ba0:	e0bffc17 	ldw	r2,-16(fp)
+    OS_ENTER_CRITICAL();
+ 8015ba4:	e0bfff15 	stw	r2,-4(fp)
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+ 8015ba8:	d0a05817 	ldw	r2,-32416(gp)
+ 8015bac:	10800c43 	ldbu	r2,49(r2)
+ 8015bb0:	10803fcc 	andi	r2,r2,255
+ 8015bb4:	10000326 	beq	r2,zero,8015bc4 <OSSemPend+0x164>
+ 8015bb8:	108000a0 	cmpeqi	r2,r2,2
+ 8015bbc:	1000041e 	bne	r2,zero,8015bd0 <OSSemPend+0x170>
+ 8015bc0:	00000706 	br	8015be0 <OSSemPend+0x180>
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+ 8015bc4:	e0bff717 	ldw	r2,-36(fp)
+ 8015bc8:	10000005 	stb	zero,0(r2)
+             break;
+ 8015bcc:	00000c06 	br	8015c00 <OSSemPend+0x1a0>
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+ 8015bd0:	e0bff717 	ldw	r2,-36(fp)
+ 8015bd4:	00c00384 	movi	r3,14
+ 8015bd8:	10c00005 	stb	r3,0(r2)
+             break;
+ 8015bdc:	00000806 	br	8015c00 <OSSemPend+0x1a0>
+
+        case OS_STAT_PEND_TO:
+        default:        
+             OS_EventTaskRemove(OSTCBCur, pevent);
+ 8015be0:	d0a05817 	ldw	r2,-32416(gp)
+ 8015be4:	e17ff917 	ldw	r5,-28(fp)
+ 8015be8:	1009883a 	mov	r4,r2
+ 8015bec:	80110b00 	call	80110b0 <OS_EventTaskRemove>
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+ 8015bf0:	e0bff717 	ldw	r2,-36(fp)
+ 8015bf4:	00c00284 	movi	r3,10
+ 8015bf8:	10c00005 	stb	r3,0(r2)
+             break;
+ 8015bfc:	0001883a 	nop
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+ 8015c00:	d0a05817 	ldw	r2,-32416(gp)
+ 8015c04:	10000c05 	stb	zero,48(r2)
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+ 8015c08:	d0a05817 	ldw	r2,-32416(gp)
+ 8015c0c:	10000c45 	stb	zero,49(r2)
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+ 8015c10:	d0a05817 	ldw	r2,-32416(gp)
+ 8015c14:	10000715 	stw	zero,28(r2)
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+ 8015c18:	d0a05817 	ldw	r2,-32416(gp)
+ 8015c1c:	10000815 	stw	zero,32(r2)
+ 8015c20:	e0bfff17 	ldw	r2,-4(fp)
+ 8015c24:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015c28:	e0bffa17 	ldw	r2,-24(fp)
+ 8015c2c:	1001703a 	wrctl	status,r2
+#endif
+    OS_EXIT_CRITICAL();
+}
+ 8015c30:	e037883a 	mov	sp,fp
+ 8015c34:	dfc00117 	ldw	ra,4(sp)
+ 8015c38:	df000017 	ldw	fp,0(sp)
+ 8015c3c:	dec00204 	addi	sp,sp,8
+ 8015c40:	f800283a 	ret
+
+08015c44 <OSSemPendAbort>:
+*********************************************************************************************************
+*/
+
+#if OS_SEM_PEND_ABORT_EN > 0
+INT8U  OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+ 8015c44:	defff604 	addi	sp,sp,-40
+ 8015c48:	dfc00915 	stw	ra,36(sp)
+ 8015c4c:	df000815 	stw	fp,32(sp)
+ 8015c50:	df000804 	addi	fp,sp,32
+ 8015c54:	e13ffa15 	stw	r4,-24(fp)
+ 8015c58:	2805883a 	mov	r2,r5
+ 8015c5c:	e1bff815 	stw	r6,-32(fp)
+ 8015c60:	e0bff905 	stb	r2,-28(fp)
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015c64:	e03ffe15 	stw	zero,-8(fp)
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+ 8015c68:	e0bffa17 	ldw	r2,-24(fp)
+ 8015c6c:	10800003 	ldbu	r2,0(r2)
+ 8015c70:	10803fcc 	andi	r2,r2,255
+ 8015c74:	108000e0 	cmpeqi	r2,r2,3
+ 8015c78:	1000051e 	bne	r2,zero,8015c90 <OSSemPendAbort+0x4c>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8015c7c:	e0bff817 	ldw	r2,-32(fp)
+ 8015c80:	00c00044 	movi	r3,1
+ 8015c84:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8015c88:	0005883a 	mov	r2,zero
+ 8015c8c:	00003806 	br	8015d70 <OSSemPendAbort+0x12c>
+  NIOS2_READ_STATUS (context);
+ 8015c90:	0005303a 	rdctl	r2,status
+ 8015c94:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015c98:	e0fffd17 	ldw	r3,-12(fp)
+ 8015c9c:	00bfff84 	movi	r2,-2
+ 8015ca0:	1884703a 	and	r2,r3,r2
+ 8015ca4:	1001703a 	wrctl	status,r2
+  return context;
+ 8015ca8:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015cac:	e0bffe15 	stw	r2,-8(fp)
+    if (pevent->OSEventGrp != 0) {                    /* See if any task waiting on semaphore?         */
+ 8015cb0:	e0bffa17 	ldw	r2,-24(fp)
+ 8015cb4:	10800283 	ldbu	r2,10(r2)
+ 8015cb8:	10803fcc 	andi	r2,r2,255
+ 8015cbc:	10002526 	beq	r2,zero,8015d54 <OSSemPendAbort+0x110>
+        nbr_tasks = 0;
+ 8015cc0:	e03fffc5 	stb	zero,-1(fp)
+        switch (opt) {
+ 8015cc4:	e0bff903 	ldbu	r2,-28(fp)
+ 8015cc8:	10800058 	cmpnei	r2,r2,1
+ 8015ccc:	10000e1e 	bne	r2,zero,8015d08 <OSSemPendAbort+0xc4>
+            case OS_PEND_OPT_BROADCAST:               /* Do we need to abort ALL waiting tasks?        */
+                 while (pevent->OSEventGrp != 0) {    /* Yes, ready ALL tasks waiting on semaphore     */
+ 8015cd0:	00000806 	br	8015cf4 <OSSemPendAbort+0xb0>
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+ 8015cd4:	01c00084 	movi	r7,2
+ 8015cd8:	01800044 	movi	r6,1
+ 8015cdc:	000b883a 	mov	r5,zero
+ 8015ce0:	e13ffa17 	ldw	r4,-24(fp)
+ 8015ce4:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+                     nbr_tasks++;
+ 8015ce8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015cec:	10800044 	addi	r2,r2,1
+ 8015cf0:	e0bfffc5 	stb	r2,-1(fp)
+                 while (pevent->OSEventGrp != 0) {    /* Yes, ready ALL tasks waiting on semaphore     */
+ 8015cf4:	e0bffa17 	ldw	r2,-24(fp)
+ 8015cf8:	10800283 	ldbu	r2,10(r2)
+ 8015cfc:	10803fcc 	andi	r2,r2,255
+ 8015d00:	103ff41e 	bne	r2,zero,8015cd4 <OSSemPendAbort+0x90>
+                 }
+                 break;
+ 8015d04:	00000906 	br	8015d2c <OSSemPendAbort+0xe8>
+                 
+            case OS_PEND_OPT_NONE:
+            default:                                  /* No,  ready HPT       waiting on semaphore     */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+ 8015d08:	01c00084 	movi	r7,2
+ 8015d0c:	01800044 	movi	r6,1
+ 8015d10:	000b883a 	mov	r5,zero
+ 8015d14:	e13ffa17 	ldw	r4,-24(fp)
+ 8015d18:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+                 nbr_tasks++;
+ 8015d1c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015d20:	10800044 	addi	r2,r2,1
+ 8015d24:	e0bfffc5 	stb	r2,-1(fp)
+                 break;
+ 8015d28:	0001883a 	nop
+ 8015d2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8015d30:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015d34:	e0bffc17 	ldw	r2,-16(fp)
+ 8015d38:	1001703a 	wrctl	status,r2
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+ 8015d3c:	801166c0 	call	801166c <OS_Sched>
+        *perr = OS_ERR_PEND_ABORT;
+ 8015d40:	e0bff817 	ldw	r2,-32(fp)
+ 8015d44:	00c00384 	movi	r3,14
+ 8015d48:	10c00005 	stb	r3,0(r2)
+        return (nbr_tasks);
+ 8015d4c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8015d50:	00000706 	br	8015d70 <OSSemPendAbort+0x12c>
+ 8015d54:	e0bffe17 	ldw	r2,-8(fp)
+ 8015d58:	e0bffb15 	stw	r2,-20(fp)
+ 8015d5c:	e0bffb17 	ldw	r2,-20(fp)
+ 8015d60:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8015d64:	e0bff817 	ldw	r2,-32(fp)
+ 8015d68:	10000005 	stb	zero,0(r2)
+    return (0);                                       /* No tasks waiting on semaphore                 */
+ 8015d6c:	0005883a 	mov	r2,zero
+}
+ 8015d70:	e037883a 	mov	sp,fp
+ 8015d74:	dfc00117 	ldw	ra,4(sp)
+ 8015d78:	df000017 	ldw	fp,0(sp)
+ 8015d7c:	dec00204 	addi	sp,sp,8
+ 8015d80:	f800283a 	ret
+
+08015d84 <OSSemPost>:
+*              OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+INT8U  OSSemPost (OS_EVENT *pevent)
+{
+ 8015d84:	defff804 	addi	sp,sp,-32
+ 8015d88:	dfc00715 	stw	ra,28(sp)
+ 8015d8c:	df000615 	stw	fp,24(sp)
+ 8015d90:	df000604 	addi	fp,sp,24
+ 8015d94:	e13ffa15 	stw	r4,-24(fp)
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015d98:	e03fff15 	stw	zero,-4(fp)
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+ 8015d9c:	e0bffa17 	ldw	r2,-24(fp)
+ 8015da0:	10800003 	ldbu	r2,0(r2)
+ 8015da4:	10803fcc 	andi	r2,r2,255
+ 8015da8:	108000e0 	cmpeqi	r2,r2,3
+ 8015dac:	1000021e 	bne	r2,zero,8015db8 <OSSemPost+0x34>
+        return (OS_ERR_EVENT_TYPE);
+ 8015db0:	00800044 	movi	r2,1
+ 8015db4:	00002e06 	br	8015e70 <OSSemPost+0xec>
+  NIOS2_READ_STATUS (context);
+ 8015db8:	0005303a 	rdctl	r2,status
+ 8015dbc:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015dc0:	e0fffe17 	ldw	r3,-8(fp)
+ 8015dc4:	00bfff84 	movi	r2,-2
+ 8015dc8:	1884703a 	and	r2,r3,r2
+ 8015dcc:	1001703a 	wrctl	status,r2
+  return context;
+ 8015dd0:	e0bffe17 	ldw	r2,-8(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015dd4:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent->OSEventGrp != 0) {                    /* See if any task waiting for semaphore         */
+ 8015dd8:	e0bffa17 	ldw	r2,-24(fp)
+ 8015ddc:	10800283 	ldbu	r2,10(r2)
+ 8015de0:	10803fcc 	andi	r2,r2,255
+ 8015de4:	10000c26 	beq	r2,zero,8015e18 <OSSemPost+0x94>
+                                                      /* Ready HPT waiting on event                    */
+        (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK);
+ 8015de8:	000f883a 	mov	r7,zero
+ 8015dec:	01800044 	movi	r6,1
+ 8015df0:	000b883a 	mov	r5,zero
+ 8015df4:	e13ffa17 	ldw	r4,-24(fp)
+ 8015df8:	8010cd80 	call	8010cd8 <OS_EventTaskRdy>
+ 8015dfc:	e0bfff17 	ldw	r2,-4(fp)
+ 8015e00:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015e04:	e0bffd17 	ldw	r2,-12(fp)
+ 8015e08:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+ 8015e0c:	801166c0 	call	801166c <OS_Sched>
+        return (OS_ERR_NONE);
+ 8015e10:	0005883a 	mov	r2,zero
+ 8015e14:	00001606 	br	8015e70 <OSSemPost+0xec>
+    }
+    if (pevent->OSEventCnt < 65535u) {                /* Make sure semaphore will not overflow         */
+ 8015e18:	e0bffa17 	ldw	r2,-24(fp)
+ 8015e1c:	1080020b 	ldhu	r2,8(r2)
+ 8015e20:	10ffffcc 	andi	r3,r2,65535
+ 8015e24:	00bfffd4 	movui	r2,65535
+ 8015e28:	18800c26 	beq	r3,r2,8015e5c <OSSemPost+0xd8>
+        pevent->OSEventCnt++;                         /* Increment semaphore count to register event   */
+ 8015e2c:	e0bffa17 	ldw	r2,-24(fp)
+ 8015e30:	1080020b 	ldhu	r2,8(r2)
+ 8015e34:	10800044 	addi	r2,r2,1
+ 8015e38:	1007883a 	mov	r3,r2
+ 8015e3c:	e0bffa17 	ldw	r2,-24(fp)
+ 8015e40:	10c0020d 	sth	r3,8(r2)
+ 8015e44:	e0bfff17 	ldw	r2,-4(fp)
+ 8015e48:	e0bffc15 	stw	r2,-16(fp)
+ 8015e4c:	e0bffc17 	ldw	r2,-16(fp)
+ 8015e50:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NONE);
+ 8015e54:	0005883a 	mov	r2,zero
+ 8015e58:	00000506 	br	8015e70 <OSSemPost+0xec>
+ 8015e5c:	e0bfff17 	ldw	r2,-4(fp)
+ 8015e60:	e0bffb15 	stw	r2,-20(fp)
+ 8015e64:	e0bffb17 	ldw	r2,-20(fp)
+ 8015e68:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();                               /* Semaphore value has reached its maximum       */
+    return (OS_ERR_SEM_OVF);
+ 8015e6c:	00800c84 	movi	r2,50
+}
+ 8015e70:	e037883a 	mov	sp,fp
+ 8015e74:	dfc00117 	ldw	ra,4(sp)
+ 8015e78:	df000017 	ldw	fp,0(sp)
+ 8015e7c:	dec00204 	addi	sp,sp,8
+ 8015e80:	f800283a 	ret
+
+08015e84 <OSSemQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_SEM_QUERY_EN > 0
+INT8U  OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data)
+{
+ 8015e84:	defff704 	addi	sp,sp,-36
+ 8015e88:	df000815 	stw	fp,32(sp)
+ 8015e8c:	df000804 	addi	fp,sp,32
+ 8015e90:	e13ff915 	stw	r4,-28(fp)
+ 8015e94:	e17ff815 	stw	r5,-32(fp)
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+    INT8U      i;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015e98:	e03ffc15 	stw	zero,-16(fp)
+    }
+    if (p_sem_data == (OS_SEM_DATA *)0) {                  /* Validate 'p_sem_data'                    */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+ 8015e9c:	e0bff917 	ldw	r2,-28(fp)
+ 8015ea0:	10800003 	ldbu	r2,0(r2)
+ 8015ea4:	10803fcc 	andi	r2,r2,255
+ 8015ea8:	108000e0 	cmpeqi	r2,r2,3
+ 8015eac:	1000021e 	bne	r2,zero,8015eb8 <OSSemQuery+0x34>
+        return (OS_ERR_EVENT_TYPE);
+ 8015eb0:	00800044 	movi	r2,1
+ 8015eb4:	00002b06 	br	8015f64 <OSSemQuery+0xe0>
+  NIOS2_READ_STATUS (context);
+ 8015eb8:	0005303a 	rdctl	r2,status
+ 8015ebc:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015ec0:	e0fffb17 	ldw	r3,-20(fp)
+ 8015ec4:	00bfff84 	movi	r2,-2
+ 8015ec8:	1884703a 	and	r2,r3,r2
+ 8015ecc:	1001703a 	wrctl	status,r2
+  return context;
+ 8015ed0:	e0bffb17 	ldw	r2,-20(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015ed4:	e0bffc15 	stw	r2,-16(fp)
+    p_sem_data->OSEventGrp = pevent->OSEventGrp;           /* Copy message mailbox wait list           */
+ 8015ed8:	e0bff917 	ldw	r2,-28(fp)
+ 8015edc:	10c00283 	ldbu	r3,10(r2)
+ 8015ee0:	e0bff817 	ldw	r2,-32(fp)
+ 8015ee4:	10c00145 	stb	r3,5(r2)
+    psrc                   = &pevent->OSEventTbl[0];
+ 8015ee8:	e0bff917 	ldw	r2,-28(fp)
+ 8015eec:	108002c4 	addi	r2,r2,11
+ 8015ef0:	e0bfff15 	stw	r2,-4(fp)
+    pdest                  = &p_sem_data->OSEventTbl[0];
+ 8015ef4:	e0bff817 	ldw	r2,-32(fp)
+ 8015ef8:	10800084 	addi	r2,r2,2
+ 8015efc:	e0bffe15 	stw	r2,-8(fp)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8015f00:	e03ffdc5 	stb	zero,-9(fp)
+ 8015f04:	00000b06 	br	8015f34 <OSSemQuery+0xb0>
+        *pdest++ = *psrc++;
+ 8015f08:	e0ffff17 	ldw	r3,-4(fp)
+ 8015f0c:	18800044 	addi	r2,r3,1
+ 8015f10:	e0bfff15 	stw	r2,-4(fp)
+ 8015f14:	e0bffe17 	ldw	r2,-8(fp)
+ 8015f18:	11000044 	addi	r4,r2,1
+ 8015f1c:	e13ffe15 	stw	r4,-8(fp)
+ 8015f20:	18c00003 	ldbu	r3,0(r3)
+ 8015f24:	10c00005 	stb	r3,0(r2)
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+ 8015f28:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8015f2c:	10800044 	addi	r2,r2,1
+ 8015f30:	e0bffdc5 	stb	r2,-9(fp)
+ 8015f34:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8015f38:	108000f0 	cmpltui	r2,r2,3
+ 8015f3c:	103ff21e 	bne	r2,zero,8015f08 <OSSemQuery+0x84>
+    }
+    p_sem_data->OSCnt = pevent->OSEventCnt;                /* Get semaphore count                      */
+ 8015f40:	e0bff917 	ldw	r2,-28(fp)
+ 8015f44:	10c0020b 	ldhu	r3,8(r2)
+ 8015f48:	e0bff817 	ldw	r2,-32(fp)
+ 8015f4c:	10c0000d 	sth	r3,0(r2)
+ 8015f50:	e0bffc17 	ldw	r2,-16(fp)
+ 8015f54:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8015f58:	e0bffa17 	ldw	r2,-24(fp)
+ 8015f5c:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8015f60:	0005883a 	mov	r2,zero
+}
+ 8015f64:	e037883a 	mov	sp,fp
+ 8015f68:	df000017 	ldw	fp,0(sp)
+ 8015f6c:	dec00104 	addi	sp,sp,4
+ 8015f70:	f800283a 	ret
+
+08015f74 <OSSemSet>:
+*********************************************************************************************************
+*/
+
+#if OS_SEM_SET_EN > 0
+void  OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr)
+{
+ 8015f74:	defff904 	addi	sp,sp,-28
+ 8015f78:	df000615 	stw	fp,24(sp)
+ 8015f7c:	df000604 	addi	fp,sp,24
+ 8015f80:	e13ffc15 	stw	r4,-16(fp)
+ 8015f84:	2805883a 	mov	r2,r5
+ 8015f88:	e1bffa15 	stw	r6,-24(fp)
+ 8015f8c:	e0bffb0d 	sth	r2,-20(fp)
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8015f90:	e03fff15 	stw	zero,-4(fp)
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+ 8015f94:	e0bffc17 	ldw	r2,-16(fp)
+ 8015f98:	10800003 	ldbu	r2,0(r2)
+ 8015f9c:	10803fcc 	andi	r2,r2,255
+ 8015fa0:	108000e0 	cmpeqi	r2,r2,3
+ 8015fa4:	1000041e 	bne	r2,zero,8015fb8 <OSSemSet+0x44>
+        *perr = OS_ERR_EVENT_TYPE;
+ 8015fa8:	e0bffa17 	ldw	r2,-24(fp)
+ 8015fac:	00c00044 	movi	r3,1
+ 8015fb0:	10c00005 	stb	r3,0(r2)
+        return;
+ 8015fb4:	00002106 	br	801603c <OSSemSet+0xc8>
+  NIOS2_READ_STATUS (context);
+ 8015fb8:	0005303a 	rdctl	r2,status
+ 8015fbc:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8015fc0:	e0fffe17 	ldw	r3,-8(fp)
+ 8015fc4:	00bfff84 	movi	r2,-2
+ 8015fc8:	1884703a 	and	r2,r3,r2
+ 8015fcc:	1001703a 	wrctl	status,r2
+  return context;
+ 8015fd0:	e0bffe17 	ldw	r2,-8(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8015fd4:	e0bfff15 	stw	r2,-4(fp)
+    *perr = OS_ERR_NONE;
+ 8015fd8:	e0bffa17 	ldw	r2,-24(fp)
+ 8015fdc:	10000005 	stb	zero,0(r2)
+    if (pevent->OSEventCnt > 0) {                     /* See if semaphore already has a count          */
+ 8015fe0:	e0bffc17 	ldw	r2,-16(fp)
+ 8015fe4:	1080020b 	ldhu	r2,8(r2)
+ 8015fe8:	10bfffcc 	andi	r2,r2,65535
+ 8015fec:	10000426 	beq	r2,zero,8016000 <OSSemSet+0x8c>
+        pevent->OSEventCnt = cnt;                     /* Yes, set it to the new value specified.       */
+ 8015ff0:	e0bffc17 	ldw	r2,-16(fp)
+ 8015ff4:	e0fffb0b 	ldhu	r3,-20(fp)
+ 8015ff8:	10c0020d 	sth	r3,8(r2)
+ 8015ffc:	00000b06 	br	801602c <OSSemSet+0xb8>
+    } else {                                          /* No                                            */
+        if (pevent->OSEventGrp == 0) {                /*      See if task(s) waiting?                  */
+ 8016000:	e0bffc17 	ldw	r2,-16(fp)
+ 8016004:	10800283 	ldbu	r2,10(r2)
+ 8016008:	10803fcc 	andi	r2,r2,255
+ 801600c:	1000041e 	bne	r2,zero,8016020 <OSSemSet+0xac>
+            pevent->OSEventCnt = cnt;                 /*      No, OK to set the value                  */
+ 8016010:	e0bffc17 	ldw	r2,-16(fp)
+ 8016014:	e0fffb0b 	ldhu	r3,-20(fp)
+ 8016018:	10c0020d 	sth	r3,8(r2)
+ 801601c:	00000306 	br	801602c <OSSemSet+0xb8>
+        } else {
+            *perr              = OS_ERR_TASK_WAITING;
+ 8016020:	e0bffa17 	ldw	r2,-24(fp)
+ 8016024:	00c01244 	movi	r3,73
+ 8016028:	10c00005 	stb	r3,0(r2)
+ 801602c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016030:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016034:	e0bffd17 	ldw	r2,-12(fp)
+ 8016038:	1001703a 	wrctl	status,r2
+        }
+    }
+    OS_EXIT_CRITICAL();
+}
+ 801603c:	e037883a 	mov	sp,fp
+ 8016040:	df000017 	ldw	fp,0(sp)
+ 8016044:	dec00104 	addi	sp,sp,4
+ 8016048:	f800283a 	ret
+
+0801604c <OSTaskChangePrio>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_CHANGE_PRIO_EN > 0
+INT8U  OSTaskChangePrio (INT8U oldprio, INT8U newprio)
+{
+ 801604c:	defff104 	addi	sp,sp,-60
+ 8016050:	dfc00e15 	stw	ra,56(sp)
+ 8016054:	df000d15 	stw	fp,52(sp)
+ 8016058:	df000d04 	addi	fp,sp,52
+ 801605c:	2005883a 	mov	r2,r4
+ 8016060:	2807883a 	mov	r3,r5
+ 8016064:	e0bff405 	stb	r2,-48(fp)
+ 8016068:	1805883a 	mov	r2,r3
+ 801606c:	e0bff305 	stb	r2,-52(fp)
+    INT16U     bitx_new;
+    INT16U     bity_old;
+    INT16U     bitx_old;
+#endif
+#if OS_CRITICAL_METHOD == 3
+    OS_CPU_SR  cpu_sr = 0;                                  /* Storage for CPU status register         */
+ 8016070:	e03ffd15 	stw	zero,-12(fp)
+  NIOS2_READ_STATUS (context);
+ 8016074:	0005303a 	rdctl	r2,status
+ 8016078:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801607c:	e0fff917 	ldw	r3,-28(fp)
+ 8016080:	00bfff84 	movi	r2,-2
+ 8016084:	1884703a 	and	r2,r3,r2
+ 8016088:	1001703a 	wrctl	status,r2
+  return context;
+ 801608c:	e0bff917 	ldw	r2,-28(fp)
+    }
+    if (newprio >= OS_LOWEST_PRIO) {
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 8016090:	e0bffd15 	stw	r2,-12(fp)
+    if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) {             /* New priority must not already exist     */
+ 8016094:	e0bff303 	ldbu	r2,-52(fp)
+ 8016098:	100690ba 	slli	r3,r2,2
+ 801609c:	008201b4 	movhi	r2,2054
+ 80160a0:	1885883a 	add	r2,r3,r2
+ 80160a4:	10b55d17 	ldw	r2,-10892(r2)
+ 80160a8:	10000626 	beq	r2,zero,80160c4 <OSTaskChangePrio+0x78>
+ 80160ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80160b0:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80160b4:	e0bff817 	ldw	r2,-32(fp)
+ 80160b8:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_PRIO_EXIST);
+ 80160bc:	00800a04 	movi	r2,40
+ 80160c0:	0000fd06 	br	80164b8 <OSTaskChangePrio+0x46c>
+    }
+    if (oldprio == OS_PRIO_SELF) {                          /* See if changing self                    */
+ 80160c4:	e0bff403 	ldbu	r2,-48(fp)
+ 80160c8:	10803fd8 	cmpnei	r2,r2,255
+ 80160cc:	1000031e 	bne	r2,zero,80160dc <OSTaskChangePrio+0x90>
+        oldprio = OSTCBCur->OSTCBPrio;                      /* Yes, get priority                       */
+ 80160d0:	d0a05817 	ldw	r2,-32416(gp)
+ 80160d4:	10800c83 	ldbu	r2,50(r2)
+ 80160d8:	e0bff405 	stb	r2,-48(fp)
+    }
+    ptcb = OSTCBPrioTbl[oldprio];
+ 80160dc:	e0bff403 	ldbu	r2,-48(fp)
+ 80160e0:	100690ba 	slli	r3,r2,2
+ 80160e4:	008201b4 	movhi	r2,2054
+ 80160e8:	1885883a 	add	r2,r3,r2
+ 80160ec:	10b55d17 	ldw	r2,-10892(r2)
+ 80160f0:	e0bffc15 	stw	r2,-16(fp)
+    if (ptcb == (OS_TCB *)0) {                              /* Does task to change exist?              */
+ 80160f4:	e0bffc17 	ldw	r2,-16(fp)
+ 80160f8:	1000061e 	bne	r2,zero,8016114 <OSTaskChangePrio+0xc8>
+ 80160fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8016100:	e0bff715 	stw	r2,-36(fp)
+ 8016104:	e0bff717 	ldw	r2,-36(fp)
+ 8016108:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                                 /* No, can't change its priority!          */
+        return (OS_ERR_PRIO);
+ 801610c:	00800a44 	movi	r2,41
+ 8016110:	0000e906 	br	80164b8 <OSTaskChangePrio+0x46c>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                          /* Is task assigned to Mutex               */
+ 8016114:	e0bffc17 	ldw	r2,-16(fp)
+ 8016118:	10800058 	cmpnei	r2,r2,1
+ 801611c:	1000061e 	bne	r2,zero,8016138 <OSTaskChangePrio+0xec>
+ 8016120:	e0bffd17 	ldw	r2,-12(fp)
+ 8016124:	e0bff615 	stw	r2,-40(fp)
+ 8016128:	e0bff617 	ldw	r2,-40(fp)
+ 801612c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                                 /* No, can't change its priority!          */
+        return (OS_ERR_TASK_NOT_EXIST);
+ 8016130:	008010c4 	movi	r2,67
+ 8016134:	0000e006 	br	80164b8 <OSTaskChangePrio+0x46c>
+    }
+#if OS_LOWEST_PRIO <= 63
+    y_new                 = (INT8U)(newprio >> 3);          /* Yes, compute new TCB fields             */
+ 8016138:	e0bff303 	ldbu	r2,-52(fp)
+ 801613c:	1004d0fa 	srli	r2,r2,3
+ 8016140:	e0bffbc5 	stb	r2,-17(fp)
+    x_new                 = (INT8U)(newprio & 0x07);
+ 8016144:	e0bff303 	ldbu	r2,-52(fp)
+ 8016148:	108001cc 	andi	r2,r2,7
+ 801614c:	e0bffb85 	stb	r2,-18(fp)
+    bity_new              = (INT8U)(1 << y_new);
+ 8016150:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8016154:	00c00044 	movi	r3,1
+ 8016158:	1884983a 	sll	r2,r3,r2
+ 801615c:	e0bffb45 	stb	r2,-19(fp)
+    bitx_new              = (INT8U)(1 << x_new);
+ 8016160:	e0bffb83 	ldbu	r2,-18(fp)
+ 8016164:	00c00044 	movi	r3,1
+ 8016168:	1884983a 	sll	r2,r3,r2
+ 801616c:	e0bffb05 	stb	r2,-20(fp)
+    x_new                 = (INT8U)( newprio & 0x0F);
+    bity_new              = (INT16U)(1 << y_new);
+    bitx_new              = (INT16U)(1 << x_new);
+#endif
+
+    OSTCBPrioTbl[oldprio] = (OS_TCB *)0;                    /* Remove TCB from old priority            */
+ 8016170:	e0bff403 	ldbu	r2,-48(fp)
+ 8016174:	100690ba 	slli	r3,r2,2
+ 8016178:	008201b4 	movhi	r2,2054
+ 801617c:	1885883a 	add	r2,r3,r2
+ 8016180:	10355d15 	stw	zero,-10892(r2)
+    OSTCBPrioTbl[newprio] =  ptcb;                          /* Place pointer to TCB @ new priority     */
+ 8016184:	e0bff303 	ldbu	r2,-52(fp)
+ 8016188:	100890ba 	slli	r4,r2,2
+ 801618c:	e0fffc17 	ldw	r3,-16(fp)
+ 8016190:	008201b4 	movhi	r2,2054
+ 8016194:	2085883a 	add	r2,r4,r2
+ 8016198:	10f55d15 	stw	r3,-10892(r2)
+    y_old                 =  ptcb->OSTCBY;
+ 801619c:	e0bffc17 	ldw	r2,-16(fp)
+ 80161a0:	10800d03 	ldbu	r2,52(r2)
+ 80161a4:	e0bffac5 	stb	r2,-21(fp)
+    bity_old              =  ptcb->OSTCBBitY;
+ 80161a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80161ac:	10800d83 	ldbu	r2,54(r2)
+ 80161b0:	e0bffa85 	stb	r2,-22(fp)
+    bitx_old              =  ptcb->OSTCBBitX;
+ 80161b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80161b8:	10800d43 	ldbu	r2,53(r2)
+ 80161bc:	e0bffa45 	stb	r2,-23(fp)
+    if ((OSRdyTbl[y_old] &   bitx_old) != 0) {              /* If task is ready make it not            */
+ 80161c0:	e0fffac3 	ldbu	r3,-21(fp)
+ 80161c4:	d0a05544 	addi	r2,gp,-32427
+ 80161c8:	1885883a 	add	r2,r3,r2
+ 80161cc:	10800003 	ldbu	r2,0(r2)
+ 80161d0:	e0fffa43 	ldbu	r3,-23(fp)
+ 80161d4:	1884703a 	and	r2,r3,r2
+ 80161d8:	10803fcc 	andi	r2,r2,255
+ 80161dc:	10002826 	beq	r2,zero,8016280 <OSTaskChangePrio+0x234>
+         OSRdyTbl[y_old] &= ~bitx_old;
+ 80161e0:	e0fffac3 	ldbu	r3,-21(fp)
+ 80161e4:	d0a05544 	addi	r2,gp,-32427
+ 80161e8:	1885883a 	add	r2,r3,r2
+ 80161ec:	10800003 	ldbu	r2,0(r2)
+ 80161f0:	1007883a 	mov	r3,r2
+ 80161f4:	e0bffa43 	ldbu	r2,-23(fp)
+ 80161f8:	0084303a 	nor	r2,zero,r2
+ 80161fc:	1884703a 	and	r2,r3,r2
+ 8016200:	e0fffac3 	ldbu	r3,-21(fp)
+ 8016204:	1009883a 	mov	r4,r2
+ 8016208:	d0a05544 	addi	r2,gp,-32427
+ 801620c:	1885883a 	add	r2,r3,r2
+ 8016210:	11000005 	stb	r4,0(r2)
+         if (OSRdyTbl[y_old] == 0) {
+ 8016214:	e0fffac3 	ldbu	r3,-21(fp)
+ 8016218:	d0a05544 	addi	r2,gp,-32427
+ 801621c:	1885883a 	add	r2,r3,r2
+ 8016220:	10800003 	ldbu	r2,0(r2)
+ 8016224:	10803fcc 	andi	r2,r2,255
+ 8016228:	1000061e 	bne	r2,zero,8016244 <OSTaskChangePrio+0x1f8>
+             OSRdyGrp &= ~bity_old;
+ 801622c:	e0bffa83 	ldbu	r2,-22(fp)
+ 8016230:	0084303a 	nor	r2,zero,r2
+ 8016234:	1007883a 	mov	r3,r2
+ 8016238:	d0a05503 	ldbu	r2,-32428(gp)
+ 801623c:	1884703a 	and	r2,r3,r2
+ 8016240:	d0a05505 	stb	r2,-32428(gp)
+         }
+         OSRdyGrp        |= bity_new;                       /* Make new priority ready to run          */
+ 8016244:	d0a05503 	ldbu	r2,-32428(gp)
+ 8016248:	e0fffb43 	ldbu	r3,-19(fp)
+ 801624c:	1884b03a 	or	r2,r3,r2
+ 8016250:	d0a05505 	stb	r2,-32428(gp)
+         OSRdyTbl[y_new] |= bitx_new;
+ 8016254:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8016258:	d0a05544 	addi	r2,gp,-32427
+ 801625c:	1885883a 	add	r2,r3,r2
+ 8016260:	10800003 	ldbu	r2,0(r2)
+ 8016264:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8016268:	e13ffb03 	ldbu	r4,-20(fp)
+ 801626c:	2084b03a 	or	r2,r4,r2
+ 8016270:	1009883a 	mov	r4,r2
+ 8016274:	d0a05544 	addi	r2,gp,-32427
+ 8016278:	1885883a 	add	r2,r3,r2
+ 801627c:	11000005 	stb	r4,0(r2)
+    }
+
+#if (OS_EVENT_EN)
+    pevent = ptcb->OSTCBEventPtr;
+ 8016280:	e0bffc17 	ldw	r2,-16(fp)
+ 8016284:	10800717 	ldw	r2,28(r2)
+ 8016288:	e0bfff15 	stw	r2,-4(fp)
+    if (pevent != (OS_EVENT *)0) {
+ 801628c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016290:	10002f26 	beq	r2,zero,8016350 <OSTaskChangePrio+0x304>
+        pevent->OSEventTbl[y_old] &= ~bitx_old;             /* Remove old task prio from wait list     */
+ 8016294:	e0bffac3 	ldbu	r2,-21(fp)
+ 8016298:	e0ffff17 	ldw	r3,-4(fp)
+ 801629c:	1885883a 	add	r2,r3,r2
+ 80162a0:	108002c3 	ldbu	r2,11(r2)
+ 80162a4:	1007883a 	mov	r3,r2
+ 80162a8:	e0bffa43 	ldbu	r2,-23(fp)
+ 80162ac:	0084303a 	nor	r2,zero,r2
+ 80162b0:	1884703a 	and	r2,r3,r2
+ 80162b4:	1007883a 	mov	r3,r2
+ 80162b8:	e0bffac3 	ldbu	r2,-21(fp)
+ 80162bc:	1809883a 	mov	r4,r3
+ 80162c0:	e0ffff17 	ldw	r3,-4(fp)
+ 80162c4:	1885883a 	add	r2,r3,r2
+ 80162c8:	110002c5 	stb	r4,11(r2)
+        if (pevent->OSEventTbl[y_old] == 0) {
+ 80162cc:	e0bffac3 	ldbu	r2,-21(fp)
+ 80162d0:	e0ffff17 	ldw	r3,-4(fp)
+ 80162d4:	1885883a 	add	r2,r3,r2
+ 80162d8:	108002c3 	ldbu	r2,11(r2)
+ 80162dc:	10803fcc 	andi	r2,r2,255
+ 80162e0:	1000091e 	bne	r2,zero,8016308 <OSTaskChangePrio+0x2bc>
+            pevent->OSEventGrp    &= ~bity_old;
+ 80162e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80162e8:	10800283 	ldbu	r2,10(r2)
+ 80162ec:	1007883a 	mov	r3,r2
+ 80162f0:	e0bffa83 	ldbu	r2,-22(fp)
+ 80162f4:	0084303a 	nor	r2,zero,r2
+ 80162f8:	1884703a 	and	r2,r3,r2
+ 80162fc:	1007883a 	mov	r3,r2
+ 8016300:	e0bfff17 	ldw	r2,-4(fp)
+ 8016304:	10c00285 	stb	r3,10(r2)
+        }
+        pevent->OSEventGrp        |= bity_new;              /* Add    new task prio to   wait list     */
+ 8016308:	e0bfff17 	ldw	r2,-4(fp)
+ 801630c:	10800283 	ldbu	r2,10(r2)
+ 8016310:	e0fffb43 	ldbu	r3,-19(fp)
+ 8016314:	1884b03a 	or	r2,r3,r2
+ 8016318:	1007883a 	mov	r3,r2
+ 801631c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016320:	10c00285 	stb	r3,10(r2)
+        pevent->OSEventTbl[y_new] |= bitx_new;
+ 8016324:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8016328:	e0ffff17 	ldw	r3,-4(fp)
+ 801632c:	1885883a 	add	r2,r3,r2
+ 8016330:	10c002c3 	ldbu	r3,11(r2)
+ 8016334:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8016338:	e13ffb03 	ldbu	r4,-20(fp)
+ 801633c:	20c6b03a 	or	r3,r4,r3
+ 8016340:	1809883a 	mov	r4,r3
+ 8016344:	e0ffff17 	ldw	r3,-4(fp)
+ 8016348:	1885883a 	add	r2,r3,r2
+ 801634c:	110002c5 	stb	r4,11(r2)
+    }
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {
+ 8016350:	e0bffc17 	ldw	r2,-16(fp)
+ 8016354:	10800817 	ldw	r2,32(r2)
+ 8016358:	10003e26 	beq	r2,zero,8016454 <OSTaskChangePrio+0x408>
+        pevents =  ptcb->OSTCBEventMultiPtr;
+ 801635c:	e0bffc17 	ldw	r2,-16(fp)
+ 8016360:	10800817 	ldw	r2,32(r2)
+ 8016364:	e0bffe15 	stw	r2,-8(fp)
+        pevent  = *pevents;
+ 8016368:	e0bffe17 	ldw	r2,-8(fp)
+ 801636c:	10800017 	ldw	r2,0(r2)
+ 8016370:	e0bfff15 	stw	r2,-4(fp)
+        while (pevent != (OS_EVENT *)0) {
+ 8016374:	00003506 	br	801644c <OSTaskChangePrio+0x400>
+            pevent->OSEventTbl[y_old] &= ~bitx_old;         /* Remove old task prio from wait lists    */
+ 8016378:	e0bffac3 	ldbu	r2,-21(fp)
+ 801637c:	e0ffff17 	ldw	r3,-4(fp)
+ 8016380:	1885883a 	add	r2,r3,r2
+ 8016384:	108002c3 	ldbu	r2,11(r2)
+ 8016388:	1007883a 	mov	r3,r2
+ 801638c:	e0bffa43 	ldbu	r2,-23(fp)
+ 8016390:	0084303a 	nor	r2,zero,r2
+ 8016394:	1884703a 	and	r2,r3,r2
+ 8016398:	1007883a 	mov	r3,r2
+ 801639c:	e0bffac3 	ldbu	r2,-21(fp)
+ 80163a0:	1809883a 	mov	r4,r3
+ 80163a4:	e0ffff17 	ldw	r3,-4(fp)
+ 80163a8:	1885883a 	add	r2,r3,r2
+ 80163ac:	110002c5 	stb	r4,11(r2)
+            if (pevent->OSEventTbl[y_old] == 0) {
+ 80163b0:	e0bffac3 	ldbu	r2,-21(fp)
+ 80163b4:	e0ffff17 	ldw	r3,-4(fp)
+ 80163b8:	1885883a 	add	r2,r3,r2
+ 80163bc:	108002c3 	ldbu	r2,11(r2)
+ 80163c0:	10803fcc 	andi	r2,r2,255
+ 80163c4:	1000091e 	bne	r2,zero,80163ec <OSTaskChangePrio+0x3a0>
+                pevent->OSEventGrp    &= ~bity_old;
+ 80163c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80163cc:	10800283 	ldbu	r2,10(r2)
+ 80163d0:	1007883a 	mov	r3,r2
+ 80163d4:	e0bffa83 	ldbu	r2,-22(fp)
+ 80163d8:	0084303a 	nor	r2,zero,r2
+ 80163dc:	1884703a 	and	r2,r3,r2
+ 80163e0:	1007883a 	mov	r3,r2
+ 80163e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80163e8:	10c00285 	stb	r3,10(r2)
+            }
+            pevent->OSEventGrp        |= bity_new;          /* Add    new task prio to   wait lists    */
+ 80163ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80163f0:	10800283 	ldbu	r2,10(r2)
+ 80163f4:	e0fffb43 	ldbu	r3,-19(fp)
+ 80163f8:	1884b03a 	or	r2,r3,r2
+ 80163fc:	1007883a 	mov	r3,r2
+ 8016400:	e0bfff17 	ldw	r2,-4(fp)
+ 8016404:	10c00285 	stb	r3,10(r2)
+            pevent->OSEventTbl[y_new] |= bitx_new;
+ 8016408:	e0bffbc3 	ldbu	r2,-17(fp)
+ 801640c:	e0ffff17 	ldw	r3,-4(fp)
+ 8016410:	1885883a 	add	r2,r3,r2
+ 8016414:	10c002c3 	ldbu	r3,11(r2)
+ 8016418:	e0bffbc3 	ldbu	r2,-17(fp)
+ 801641c:	e13ffb03 	ldbu	r4,-20(fp)
+ 8016420:	20c6b03a 	or	r3,r4,r3
+ 8016424:	1809883a 	mov	r4,r3
+ 8016428:	e0ffff17 	ldw	r3,-4(fp)
+ 801642c:	1885883a 	add	r2,r3,r2
+ 8016430:	110002c5 	stb	r4,11(r2)
+            pevents++;
+ 8016434:	e0bffe17 	ldw	r2,-8(fp)
+ 8016438:	10800104 	addi	r2,r2,4
+ 801643c:	e0bffe15 	stw	r2,-8(fp)
+            pevent                     = *pevents;
+ 8016440:	e0bffe17 	ldw	r2,-8(fp)
+ 8016444:	10800017 	ldw	r2,0(r2)
+ 8016448:	e0bfff15 	stw	r2,-4(fp)
+        while (pevent != (OS_EVENT *)0) {
+ 801644c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016450:	103fc91e 	bne	r2,zero,8016378 <OSTaskChangePrio+0x32c>
+        }
+    }
+#endif
+#endif
+
+    ptcb->OSTCBPrio = newprio;                              /* Set new task priority                   */
+ 8016454:	e0bffc17 	ldw	r2,-16(fp)
+ 8016458:	e0fff303 	ldbu	r3,-52(fp)
+ 801645c:	10c00c85 	stb	r3,50(r2)
+    ptcb->OSTCBY    = y_new;
+ 8016460:	e0bffc17 	ldw	r2,-16(fp)
+ 8016464:	e0fffbc3 	ldbu	r3,-17(fp)
+ 8016468:	10c00d05 	stb	r3,52(r2)
+    ptcb->OSTCBX    = x_new;
+ 801646c:	e0bffc17 	ldw	r2,-16(fp)
+ 8016470:	e0fffb83 	ldbu	r3,-18(fp)
+ 8016474:	10c00cc5 	stb	r3,51(r2)
+    ptcb->OSTCBBitY = bity_new;
+ 8016478:	e0bffc17 	ldw	r2,-16(fp)
+ 801647c:	e0fffb43 	ldbu	r3,-19(fp)
+ 8016480:	10c00d85 	stb	r3,54(r2)
+    ptcb->OSTCBBitX = bitx_new;
+ 8016484:	e0bffc17 	ldw	r2,-16(fp)
+ 8016488:	e0fffb03 	ldbu	r3,-20(fp)
+ 801648c:	10c00d45 	stb	r3,53(r2)
+ 8016490:	e0bffd17 	ldw	r2,-12(fp)
+ 8016494:	e0bff515 	stw	r2,-44(fp)
+ 8016498:	e0bff517 	ldw	r2,-44(fp)
+ 801649c:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    if (OSRunning == OS_TRUE) {
+ 80164a0:	d0a04b43 	ldbu	r2,-32467(gp)
+ 80164a4:	10803fcc 	andi	r2,r2,255
+ 80164a8:	10800058 	cmpnei	r2,r2,1
+ 80164ac:	1000011e 	bne	r2,zero,80164b4 <OSTaskChangePrio+0x468>
+        OS_Sched();                                         /* Find new highest priority task          */
+ 80164b0:	801166c0 	call	801166c <OS_Sched>
+    }
+    return (OS_ERR_NONE);
+ 80164b4:	0005883a 	mov	r2,zero
+}
+ 80164b8:	e037883a 	mov	sp,fp
+ 80164bc:	dfc00117 	ldw	ra,4(sp)
+ 80164c0:	df000017 	ldw	fp,0(sp)
+ 80164c4:	dec00204 	addi	sp,sp,8
+ 80164c8:	f800283a 	ret
+
+080164cc <OSTaskCreate>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_CREATE_EN > 0
+INT8U  OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio)
+{
+ 80164cc:	deffee04 	addi	sp,sp,-72
+ 80164d0:	dfc01115 	stw	ra,68(sp)
+ 80164d4:	df001015 	stw	fp,64(sp)
+ 80164d8:	df001004 	addi	fp,sp,64
+ 80164dc:	e13ff615 	stw	r4,-40(fp)
+ 80164e0:	e17ff515 	stw	r5,-44(fp)
+ 80164e4:	e1bff415 	stw	r6,-48(fp)
+ 80164e8:	3805883a 	mov	r2,r7
+ 80164ec:	e0bff305 	stb	r2,-52(fp)
+    OS_STK    *psp;
+    INT8U      err;
+#if OS_CRITICAL_METHOD == 3                  /* Allocate storage for CPU status register               */
+    OS_CPU_SR  cpu_sr = 0;
+ 80164f0:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80164f4:	0005303a 	rdctl	r2,status
+ 80164f8:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80164fc:	e0fffc17 	ldw	r3,-16(fp)
+ 8016500:	00bfff84 	movi	r2,-2
+ 8016504:	1884703a 	and	r2,r3,r2
+ 8016508:	1001703a 	wrctl	status,r2
+  return context;
+ 801650c:	e0bffc17 	ldw	r2,-16(fp)
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {             /* Make sure priority is within allowable range           */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 8016510:	e0bfff15 	stw	r2,-4(fp)
+    if (OSIntNesting > 0) {                  /* Make sure we don't create the task from within an ISR  */
+ 8016514:	d0a05703 	ldbu	r2,-32420(gp)
+ 8016518:	10803fcc 	andi	r2,r2,255
+ 801651c:	10000626 	beq	r2,zero,8016538 <OSTaskCreate+0x6c>
+ 8016520:	e0bfff17 	ldw	r2,-4(fp)
+ 8016524:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016528:	e0bffb17 	ldw	r2,-20(fp)
+ 801652c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_CREATE_ISR);
+ 8016530:	00800f04 	movi	r2,60
+ 8016534:	00004006 	br	8016638 <OSTaskCreate+0x16c>
+    }
+    if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority  */
+ 8016538:	e0bff303 	ldbu	r2,-52(fp)
+ 801653c:	100690ba 	slli	r3,r2,2
+ 8016540:	008201b4 	movhi	r2,2054
+ 8016544:	1885883a 	add	r2,r3,r2
+ 8016548:	10b55d17 	ldw	r2,-10892(r2)
+ 801654c:	1000351e 	bne	r2,zero,8016624 <OSTaskCreate+0x158>
+        OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ...  */
+ 8016550:	e0bff303 	ldbu	r2,-52(fp)
+ 8016554:	100890ba 	slli	r4,r2,2
+ 8016558:	00c00044 	movi	r3,1
+ 801655c:	008201b4 	movhi	r2,2054
+ 8016560:	2085883a 	add	r2,r4,r2
+ 8016564:	10f55d15 	stw	r3,-10892(r2)
+ 8016568:	e0bfff17 	ldw	r2,-4(fp)
+ 801656c:	e0bffa15 	stw	r2,-24(fp)
+ 8016570:	e0bffa17 	ldw	r2,-24(fp)
+ 8016574:	1001703a 	wrctl	status,r2
+                                             /* ... the same thing until task is created.              */
+        OS_EXIT_CRITICAL();
+        psp = OSTaskStkInit(task, p_arg, ptos, 0);              /* Initialize the task's stack         */
+ 8016578:	000f883a 	mov	r7,zero
+ 801657c:	e1bff417 	ldw	r6,-48(fp)
+ 8016580:	e17ff517 	ldw	r5,-44(fp)
+ 8016584:	e13ff617 	ldw	r4,-40(fp)
+ 8016588:	80384580 	call	8038458 <OSTaskStkInit>
+ 801658c:	e0bffe15 	stw	r2,-8(fp)
+        err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0);
+ 8016590:	e0bff303 	ldbu	r2,-52(fp)
+ 8016594:	d8000215 	stw	zero,8(sp)
+ 8016598:	d8000115 	stw	zero,4(sp)
+ 801659c:	d8000015 	stw	zero,0(sp)
+ 80165a0:	000f883a 	mov	r7,zero
+ 80165a4:	000d883a 	mov	r6,zero
+ 80165a8:	e17ffe17 	ldw	r5,-8(fp)
+ 80165ac:	1009883a 	mov	r4,r2
+ 80165b0:	80118c40 	call	80118c4 <OS_TCBInit>
+ 80165b4:	e0bffdc5 	stb	r2,-9(fp)
+        if (err == OS_ERR_NONE) {
+ 80165b8:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80165bc:	1000061e 	bne	r2,zero,80165d8 <OSTaskCreate+0x10c>
+            if (OSRunning == OS_TRUE) {      /* Find highest priority task if multitasking has started */
+ 80165c0:	d0a04b43 	ldbu	r2,-32467(gp)
+ 80165c4:	10803fcc 	andi	r2,r2,255
+ 80165c8:	10800058 	cmpnei	r2,r2,1
+ 80165cc:	1000131e 	bne	r2,zero,801661c <OSTaskCreate+0x150>
+                OS_Sched();
+ 80165d0:	801166c0 	call	801166c <OS_Sched>
+ 80165d4:	00001106 	br	801661c <OSTaskCreate+0x150>
+  NIOS2_READ_STATUS (context);
+ 80165d8:	0005303a 	rdctl	r2,status
+ 80165dc:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80165e0:	e0fff817 	ldw	r3,-32(fp)
+ 80165e4:	00bfff84 	movi	r2,-2
+ 80165e8:	1884703a 	and	r2,r3,r2
+ 80165ec:	1001703a 	wrctl	status,r2
+  return context;
+ 80165f0:	e0bff817 	ldw	r2,-32(fp)
+            }
+        } else {
+            OS_ENTER_CRITICAL();
+ 80165f4:	e0bfff15 	stw	r2,-4(fp)
+            OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others                 */
+ 80165f8:	e0bff303 	ldbu	r2,-52(fp)
+ 80165fc:	100690ba 	slli	r3,r2,2
+ 8016600:	008201b4 	movhi	r2,2054
+ 8016604:	1885883a 	add	r2,r3,r2
+ 8016608:	10355d15 	stw	zero,-10892(r2)
+ 801660c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016610:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016614:	e0bff917 	ldw	r2,-28(fp)
+ 8016618:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();
+        }
+        return (err);
+ 801661c:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8016620:	00000506 	br	8016638 <OSTaskCreate+0x16c>
+ 8016624:	e0bfff17 	ldw	r2,-4(fp)
+ 8016628:	e0bff715 	stw	r2,-36(fp)
+ 801662c:	e0bff717 	ldw	r2,-36(fp)
+ 8016630:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_PRIO_EXIST);
+ 8016634:	00800a04 	movi	r2,40
+}
+ 8016638:	e037883a 	mov	sp,fp
+ 801663c:	dfc00117 	ldw	ra,4(sp)
+ 8016640:	df000017 	ldw	fp,0(sp)
+ 8016644:	dec00204 	addi	sp,sp,8
+ 8016648:	f800283a 	ret
+
+0801664c <OSTaskCreateExt>:
+                        INT16U   id,
+                        OS_STK  *pbos,
+                        INT32U   stk_size,
+                        void    *pext,
+                        INT16U   opt)
+{
+ 801664c:	deffec04 	addi	sp,sp,-80
+ 8016650:	dfc01315 	stw	ra,76(sp)
+ 8016654:	df001215 	stw	fp,72(sp)
+ 8016658:	df001204 	addi	fp,sp,72
+ 801665c:	e13ff615 	stw	r4,-40(fp)
+ 8016660:	e17ff515 	stw	r5,-44(fp)
+ 8016664:	e1bff415 	stw	r6,-48(fp)
+ 8016668:	3809883a 	mov	r4,r7
+ 801666c:	e0c00217 	ldw	r3,8(fp)
+ 8016670:	e0800617 	ldw	r2,24(fp)
+ 8016674:	e13ff305 	stb	r4,-52(fp)
+ 8016678:	e0fff20d 	sth	r3,-56(fp)
+ 801667c:	e0bff10d 	sth	r2,-60(fp)
+    OS_STK    *psp;
+    INT8U      err;
+#if OS_CRITICAL_METHOD == 3                  /* Allocate storage for CPU status register               */
+    OS_CPU_SR  cpu_sr = 0;
+ 8016680:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8016684:	0005303a 	rdctl	r2,status
+ 8016688:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801668c:	e0fffc17 	ldw	r3,-16(fp)
+ 8016690:	00bfff84 	movi	r2,-2
+ 8016694:	1884703a 	and	r2,r3,r2
+ 8016698:	1001703a 	wrctl	status,r2
+  return context;
+ 801669c:	e0bffc17 	ldw	r2,-16(fp)
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {             /* Make sure priority is within allowable range           */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 80166a0:	e0bfff15 	stw	r2,-4(fp)
+    if (OSIntNesting > 0) {                  /* Make sure we don't create the task from within an ISR  */
+ 80166a4:	d0a05703 	ldbu	r2,-32420(gp)
+ 80166a8:	10803fcc 	andi	r2,r2,255
+ 80166ac:	10000626 	beq	r2,zero,80166c8 <OSTaskCreateExt+0x7c>
+ 80166b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80166b4:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80166b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80166bc:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_CREATE_ISR);
+ 80166c0:	00800f04 	movi	r2,60
+ 80166c4:	00004506 	br	80167dc <OSTaskCreateExt+0x190>
+    }
+    if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority  */
+ 80166c8:	e0bff303 	ldbu	r2,-52(fp)
+ 80166cc:	100690ba 	slli	r3,r2,2
+ 80166d0:	008201b4 	movhi	r2,2054
+ 80166d4:	1885883a 	add	r2,r3,r2
+ 80166d8:	10b55d17 	ldw	r2,-10892(r2)
+ 80166dc:	10003a1e 	bne	r2,zero,80167c8 <OSTaskCreateExt+0x17c>
+        OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ...  */
+ 80166e0:	e0bff303 	ldbu	r2,-52(fp)
+ 80166e4:	100890ba 	slli	r4,r2,2
+ 80166e8:	00c00044 	movi	r3,1
+ 80166ec:	008201b4 	movhi	r2,2054
+ 80166f0:	2085883a 	add	r2,r4,r2
+ 80166f4:	10f55d15 	stw	r3,-10892(r2)
+ 80166f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80166fc:	e0bffa15 	stw	r2,-24(fp)
+ 8016700:	e0bffa17 	ldw	r2,-24(fp)
+ 8016704:	1001703a 	wrctl	status,r2
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0)
+        OS_TaskStkClr(pbos, stk_size, opt);                    /* Clear the task stack (if needed)     */
+#endif
+
+        psp = OSTaskStkInit(task, p_arg, ptos, opt);           /* Initialize the task's stack          */
+ 8016708:	e0bff10b 	ldhu	r2,-60(fp)
+ 801670c:	100f883a 	mov	r7,r2
+ 8016710:	e1bff417 	ldw	r6,-48(fp)
+ 8016714:	e17ff517 	ldw	r5,-44(fp)
+ 8016718:	e13ff617 	ldw	r4,-40(fp)
+ 801671c:	80384580 	call	8038458 <OSTaskStkInit>
+ 8016720:	e0bffe15 	stw	r2,-8(fp)
+        err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt);
+ 8016724:	e0fff303 	ldbu	r3,-52(fp)
+ 8016728:	e13ff20b 	ldhu	r4,-56(fp)
+ 801672c:	e0bff10b 	ldhu	r2,-60(fp)
+ 8016730:	d8800215 	stw	r2,8(sp)
+ 8016734:	e0800517 	ldw	r2,20(fp)
+ 8016738:	d8800115 	stw	r2,4(sp)
+ 801673c:	e0800417 	ldw	r2,16(fp)
+ 8016740:	d8800015 	stw	r2,0(sp)
+ 8016744:	200f883a 	mov	r7,r4
+ 8016748:	e1800317 	ldw	r6,12(fp)
+ 801674c:	e17ffe17 	ldw	r5,-8(fp)
+ 8016750:	1809883a 	mov	r4,r3
+ 8016754:	80118c40 	call	80118c4 <OS_TCBInit>
+ 8016758:	e0bffdc5 	stb	r2,-9(fp)
+        if (err == OS_ERR_NONE) {
+ 801675c:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8016760:	1000061e 	bne	r2,zero,801677c <OSTaskCreateExt+0x130>
+            if (OSRunning == OS_TRUE) {                        /* Find HPT if multitasking has started */
+ 8016764:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8016768:	10803fcc 	andi	r2,r2,255
+ 801676c:	10800058 	cmpnei	r2,r2,1
+ 8016770:	1000131e 	bne	r2,zero,80167c0 <OSTaskCreateExt+0x174>
+                OS_Sched();
+ 8016774:	801166c0 	call	801166c <OS_Sched>
+ 8016778:	00001106 	br	80167c0 <OSTaskCreateExt+0x174>
+  NIOS2_READ_STATUS (context);
+ 801677c:	0005303a 	rdctl	r2,status
+ 8016780:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016784:	e0fff817 	ldw	r3,-32(fp)
+ 8016788:	00bfff84 	movi	r2,-2
+ 801678c:	1884703a 	and	r2,r3,r2
+ 8016790:	1001703a 	wrctl	status,r2
+  return context;
+ 8016794:	e0bff817 	ldw	r2,-32(fp)
+            }
+        } else {
+            OS_ENTER_CRITICAL();
+ 8016798:	e0bfff15 	stw	r2,-4(fp)
+            OSTCBPrioTbl[prio] = (OS_TCB *)0;                  /* Make this priority avail. to others  */
+ 801679c:	e0bff303 	ldbu	r2,-52(fp)
+ 80167a0:	100690ba 	slli	r3,r2,2
+ 80167a4:	008201b4 	movhi	r2,2054
+ 80167a8:	1885883a 	add	r2,r3,r2
+ 80167ac:	10355d15 	stw	zero,-10892(r2)
+ 80167b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80167b4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80167b8:	e0bff917 	ldw	r2,-28(fp)
+ 80167bc:	1001703a 	wrctl	status,r2
+            OS_EXIT_CRITICAL();
+        }
+        return (err);
+ 80167c0:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80167c4:	00000506 	br	80167dc <OSTaskCreateExt+0x190>
+ 80167c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80167cc:	e0bff715 	stw	r2,-36(fp)
+ 80167d0:	e0bff717 	ldw	r2,-36(fp)
+ 80167d4:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_PRIO_EXIST);
+ 80167d8:	00800a04 	movi	r2,40
+}
+ 80167dc:	e037883a 	mov	sp,fp
+ 80167e0:	dfc00117 	ldw	ra,4(sp)
+ 80167e4:	df000017 	ldw	fp,0(sp)
+ 80167e8:	dec00204 	addi	sp,sp,8
+ 80167ec:	f800283a 	ret
+
+080167f0 <OSTaskDel>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_DEL_EN > 0
+INT8U  OSTaskDel (INT8U prio)
+{
+ 80167f0:	defff404 	addi	sp,sp,-48
+ 80167f4:	dfc00b15 	stw	ra,44(sp)
+ 80167f8:	df000a15 	stw	fp,40(sp)
+ 80167fc:	df000a04 	addi	fp,sp,40
+ 8016800:	2005883a 	mov	r2,r4
+ 8016804:	e0bff605 	stb	r2,-40(fp)
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    OS_FLAG_NODE *pnode;
+#endif
+    OS_TCB       *ptcb;
+#if OS_CRITICAL_METHOD == 3                             /* Allocate storage for CPU status register    */
+    OS_CPU_SR     cpu_sr = 0;
+ 8016808:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                             /* See if trying to delete from ISR            */
+ 801680c:	d0a05703 	ldbu	r2,-32420(gp)
+ 8016810:	10803fcc 	andi	r2,r2,255
+ 8016814:	10000226 	beq	r2,zero,8016820 <OSTaskDel+0x30>
+        return (OS_ERR_TASK_DEL_ISR);
+ 8016818:	00801004 	movi	r2,64
+ 801681c:	0000b406 	br	8016af0 <OSTaskDel+0x300>
+    }
+    if (prio == OS_TASK_IDLE_PRIO) {                    /* Not allowed to delete idle task             */
+ 8016820:	e0bff603 	ldbu	r2,-40(fp)
+ 8016824:	10800518 	cmpnei	r2,r2,20
+ 8016828:	1000021e 	bne	r2,zero,8016834 <OSTaskDel+0x44>
+        return (OS_ERR_TASK_DEL_IDLE);
+ 801682c:	00800f84 	movi	r2,62
+ 8016830:	0000af06 	br	8016af0 <OSTaskDel+0x300>
+  NIOS2_READ_STATUS (context);
+ 8016834:	0005303a 	rdctl	r2,status
+ 8016838:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801683c:	e0fffc17 	ldw	r3,-16(fp)
+ 8016840:	00bfff84 	movi	r2,-2
+ 8016844:	1884703a 	and	r2,r3,r2
+ 8016848:	1001703a 	wrctl	status,r2
+  return context;
+ 801684c:	e0bffc17 	ldw	r2,-16(fp)
+        }
+    }
+#endif
+
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+ 8016850:	e0bfff15 	stw	r2,-4(fp)
+    if (prio == OS_PRIO_SELF) {                         /* See if requesting to delete self            */
+ 8016854:	e0bff603 	ldbu	r2,-40(fp)
+ 8016858:	10803fd8 	cmpnei	r2,r2,255
+ 801685c:	1000031e 	bne	r2,zero,801686c <OSTaskDel+0x7c>
+        prio = OSTCBCur->OSTCBPrio;                     /* Set priority to delete to current           */
+ 8016860:	d0a05817 	ldw	r2,-32416(gp)
+ 8016864:	10800c83 	ldbu	r2,50(r2)
+ 8016868:	e0bff605 	stb	r2,-40(fp)
+    }
+    ptcb = OSTCBPrioTbl[prio];
+ 801686c:	e0bff603 	ldbu	r2,-40(fp)
+ 8016870:	100690ba 	slli	r3,r2,2
+ 8016874:	008201b4 	movhi	r2,2054
+ 8016878:	1885883a 	add	r2,r3,r2
+ 801687c:	10b55d17 	ldw	r2,-10892(r2)
+ 8016880:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {                          /* Task to delete must exist                   */
+ 8016884:	e0bffe17 	ldw	r2,-8(fp)
+ 8016888:	1000061e 	bne	r2,zero,80168a4 <OSTaskDel+0xb4>
+ 801688c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016890:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016894:	e0bffb17 	ldw	r2,-20(fp)
+ 8016898:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+ 801689c:	008010c4 	movi	r2,67
+ 80168a0:	00009306 	br	8016af0 <OSTaskDel+0x300>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                      /* Must not be assigned to Mutex               */
+ 80168a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80168a8:	10800058 	cmpnei	r2,r2,1
+ 80168ac:	1000061e 	bne	r2,zero,80168c8 <OSTaskDel+0xd8>
+ 80168b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80168b4:	e0bffa15 	stw	r2,-24(fp)
+ 80168b8:	e0bffa17 	ldw	r2,-24(fp)
+ 80168bc:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_DEL);
+ 80168c0:	00800f44 	movi	r2,61
+ 80168c4:	00008a06 	br	8016af0 <OSTaskDel+0x300>
+    }
+
+    OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX;
+ 80168c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80168cc:	10800d03 	ldbu	r2,52(r2)
+ 80168d0:	10c03fcc 	andi	r3,r2,255
+ 80168d4:	d0a05544 	addi	r2,gp,-32427
+ 80168d8:	1885883a 	add	r2,r3,r2
+ 80168dc:	10800003 	ldbu	r2,0(r2)
+ 80168e0:	1007883a 	mov	r3,r2
+ 80168e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80168e8:	10800d43 	ldbu	r2,53(r2)
+ 80168ec:	0084303a 	nor	r2,zero,r2
+ 80168f0:	1884703a 	and	r2,r3,r2
+ 80168f4:	1009883a 	mov	r4,r2
+ 80168f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80168fc:	10800d03 	ldbu	r2,52(r2)
+ 8016900:	10c03fcc 	andi	r3,r2,255
+ 8016904:	d0a05544 	addi	r2,gp,-32427
+ 8016908:	1885883a 	add	r2,r3,r2
+ 801690c:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[ptcb->OSTCBY] == 0) {                  /* Make task not ready                         */
+ 8016910:	e0bffe17 	ldw	r2,-8(fp)
+ 8016914:	10800d03 	ldbu	r2,52(r2)
+ 8016918:	10c03fcc 	andi	r3,r2,255
+ 801691c:	d0a05544 	addi	r2,gp,-32427
+ 8016920:	1885883a 	add	r2,r3,r2
+ 8016924:	10800003 	ldbu	r2,0(r2)
+ 8016928:	10803fcc 	andi	r2,r2,255
+ 801692c:	1000071e 	bne	r2,zero,801694c <OSTaskDel+0x15c>
+        OSRdyGrp           &= ~ptcb->OSTCBBitY;
+ 8016930:	e0bffe17 	ldw	r2,-8(fp)
+ 8016934:	10800d83 	ldbu	r2,54(r2)
+ 8016938:	0084303a 	nor	r2,zero,r2
+ 801693c:	1007883a 	mov	r3,r2
+ 8016940:	d0a05503 	ldbu	r2,-32428(gp)
+ 8016944:	1884703a 	and	r2,r3,r2
+ 8016948:	d0a05505 	stb	r2,-32428(gp)
+    }
+    
+#if (OS_EVENT_EN)
+    if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) {
+ 801694c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016950:	10800717 	ldw	r2,28(r2)
+ 8016954:	10000526 	beq	r2,zero,801696c <OSTaskDel+0x17c>
+        OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr);  /* Remove this task from any event   wait list */
+ 8016958:	e0bffe17 	ldw	r2,-8(fp)
+ 801695c:	10800717 	ldw	r2,28(r2)
+ 8016960:	100b883a 	mov	r5,r2
+ 8016964:	e13ffe17 	ldw	r4,-8(fp)
+ 8016968:	80110b00 	call	80110b0 <OS_EventTaskRemove>
+    }
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {   /* Remove this task from any events' wait lists*/
+ 801696c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016970:	10800817 	ldw	r2,32(r2)
+ 8016974:	10000526 	beq	r2,zero,801698c <OSTaskDel+0x19c>
+        OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr);
+ 8016978:	e0bffe17 	ldw	r2,-8(fp)
+ 801697c:	10800817 	ldw	r2,32(r2)
+ 8016980:	100b883a 	mov	r5,r2
+ 8016984:	e13ffe17 	ldw	r4,-8(fp)
+ 8016988:	80111600 	call	8011160 <OS_EventTaskRemoveMulti>
+    }
+#endif
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    pnode = ptcb->OSTCBFlagNode;
+ 801698c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016990:	10800a17 	ldw	r2,40(r2)
+ 8016994:	e0bffd15 	stw	r2,-12(fp)
+    if (pnode != (OS_FLAG_NODE *)0) {                   /* If task is waiting on event flag            */
+ 8016998:	e0bffd17 	ldw	r2,-12(fp)
+ 801699c:	10000226 	beq	r2,zero,80169a8 <OSTaskDel+0x1b8>
+        OS_FlagUnlink(pnode);                           /* Remove from wait list                       */
+ 80169a0:	e13ffd17 	ldw	r4,-12(fp)
+ 80169a4:	80130ac0 	call	80130ac <OS_FlagUnlink>
+    }
+#endif
+
+    ptcb->OSTCBDly      = 0;                            /* Prevent OSTimeTick() from updating          */
+ 80169a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80169ac:	10000b8d 	sth	zero,46(r2)
+    ptcb->OSTCBStat     = OS_STAT_RDY;                  /* Prevent task from being resumed             */
+ 80169b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80169b4:	10000c05 	stb	zero,48(r2)
+    ptcb->OSTCBStatPend = OS_STAT_PEND_OK;
+ 80169b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80169bc:	10000c45 	stb	zero,49(r2)
+    if (OSLockNesting < 255u) {                         /* Make sure we don't context switch           */
+ 80169c0:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80169c4:	10803fcc 	andi	r2,r2,255
+ 80169c8:	10803fe0 	cmpeqi	r2,r2,255
+ 80169cc:	1000031e 	bne	r2,zero,80169dc <OSTaskDel+0x1ec>
+        OSLockNesting++;
+ 80169d0:	d0a04b03 	ldbu	r2,-32468(gp)
+ 80169d4:	10800044 	addi	r2,r2,1
+ 80169d8:	d0a04b05 	stb	r2,-32468(gp)
+ 80169dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80169e0:	e0bff815 	stw	r2,-32(fp)
+ 80169e4:	e0bff817 	ldw	r2,-32(fp)
+ 80169e8:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();                                 /* Enabling INT. ignores next instruc.         */
+    OS_Dummy();                                         /* ... Dummy ensures that INTs will be         */
+ 80169ec:	8010cb80 	call	8010cb8 <OS_Dummy>
+  NIOS2_READ_STATUS (context);
+ 80169f0:	0005303a 	rdctl	r2,status
+ 80169f4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80169f8:	e0fff917 	ldw	r3,-28(fp)
+ 80169fc:	00bfff84 	movi	r2,-2
+ 8016a00:	1884703a 	and	r2,r3,r2
+ 8016a04:	1001703a 	wrctl	status,r2
+  return context;
+ 8016a08:	e0bff917 	ldw	r2,-28(fp)
+    OS_ENTER_CRITICAL();                                /* ... disabled HERE!                          */
+ 8016a0c:	e0bfff15 	stw	r2,-4(fp)
+    if (OSLockNesting > 0) {                            /* Remove context switch lock                  */
+ 8016a10:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8016a14:	10803fcc 	andi	r2,r2,255
+ 8016a18:	10000326 	beq	r2,zero,8016a28 <OSTaskDel+0x238>
+        OSLockNesting--;
+ 8016a1c:	d0a04b03 	ldbu	r2,-32468(gp)
+ 8016a20:	10bfffc4 	addi	r2,r2,-1
+ 8016a24:	d0a04b05 	stb	r2,-32468(gp)
+    }
+    OSTaskDelHook(ptcb);                                /* Call user defined hook                      */
+ 8016a28:	e13ffe17 	ldw	r4,-8(fp)
+ 8016a2c:	80385c80 	call	80385c8 <OSTaskDelHook>
+    OSTaskCtr--;                                        /* One less task being managed                 */
+ 8016a30:	d0a05103 	ldbu	r2,-32444(gp)
+ 8016a34:	10bfffc4 	addi	r2,r2,-1
+ 8016a38:	d0a05105 	stb	r2,-32444(gp)
+    OSTCBPrioTbl[prio] = (OS_TCB *)0;                   /* Clear old priority entry                    */
+ 8016a3c:	e0bff603 	ldbu	r2,-40(fp)
+ 8016a40:	100690ba 	slli	r3,r2,2
+ 8016a44:	008201b4 	movhi	r2,2054
+ 8016a48:	1885883a 	add	r2,r3,r2
+ 8016a4c:	10355d15 	stw	zero,-10892(r2)
+    if (ptcb->OSTCBPrev == (OS_TCB *)0) {               /* Remove from TCB chain                       */
+ 8016a50:	e0bffe17 	ldw	r2,-8(fp)
+ 8016a54:	10800617 	ldw	r2,24(r2)
+ 8016a58:	1000071e 	bne	r2,zero,8016a78 <OSTaskDel+0x288>
+        ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0;
+ 8016a5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016a60:	10800517 	ldw	r2,20(r2)
+ 8016a64:	10000615 	stw	zero,24(r2)
+        OSTCBList                  = ptcb->OSTCBNext;
+ 8016a68:	e0bffe17 	ldw	r2,-8(fp)
+ 8016a6c:	10800517 	ldw	r2,20(r2)
+ 8016a70:	d0a04e15 	stw	r2,-32456(gp)
+ 8016a74:	00000a06 	br	8016aa0 <OSTaskDel+0x2b0>
+    } else {
+        ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext;
+ 8016a78:	e0bffe17 	ldw	r2,-8(fp)
+ 8016a7c:	10800617 	ldw	r2,24(r2)
+ 8016a80:	e0fffe17 	ldw	r3,-8(fp)
+ 8016a84:	18c00517 	ldw	r3,20(r3)
+ 8016a88:	10c00515 	stw	r3,20(r2)
+        ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev;
+ 8016a8c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016a90:	10800517 	ldw	r2,20(r2)
+ 8016a94:	e0fffe17 	ldw	r3,-8(fp)
+ 8016a98:	18c00617 	ldw	r3,24(r3)
+ 8016a9c:	10c00615 	stw	r3,24(r2)
+    }
+    ptcb->OSTCBNext   = OSTCBFreeList;                  /* Return TCB to free TCB list                 */
+ 8016aa0:	d0e05017 	ldw	r3,-32448(gp)
+ 8016aa4:	e0bffe17 	ldw	r2,-8(fp)
+ 8016aa8:	10c00515 	stw	r3,20(r2)
+    OSTCBFreeList     = ptcb;
+ 8016aac:	e0bffe17 	ldw	r2,-8(fp)
+ 8016ab0:	d0a05015 	stw	r2,-32448(gp)
+#if OS_TASK_NAME_SIZE > 1
+    ptcb->OSTCBTaskName[0] = '?';                       /* Unknown name                                */
+ 8016ab4:	e0bffe17 	ldw	r2,-8(fp)
+ 8016ab8:	00c00fc4 	movi	r3,63
+ 8016abc:	10c01305 	stb	r3,76(r2)
+    ptcb->OSTCBTaskName[1] = OS_ASCII_NUL;
+ 8016ac0:	e0bffe17 	ldw	r2,-8(fp)
+ 8016ac4:	10001345 	stb	zero,77(r2)
+ 8016ac8:	e0bfff17 	ldw	r2,-4(fp)
+ 8016acc:	e0bff715 	stw	r2,-36(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016ad0:	e0bff717 	ldw	r2,-36(fp)
+ 8016ad4:	1001703a 	wrctl	status,r2
+#endif
+    OS_EXIT_CRITICAL();
+    if (OSRunning == OS_TRUE) {
+ 8016ad8:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8016adc:	10803fcc 	andi	r2,r2,255
+ 8016ae0:	10800058 	cmpnei	r2,r2,1
+ 8016ae4:	1000011e 	bne	r2,zero,8016aec <OSTaskDel+0x2fc>
+        OS_Sched();                                     /* Find new highest priority task              */
+ 8016ae8:	801166c0 	call	801166c <OS_Sched>
+    }
+    return (OS_ERR_NONE);
+ 8016aec:	0005883a 	mov	r2,zero
+}
+ 8016af0:	e037883a 	mov	sp,fp
+ 8016af4:	dfc00117 	ldw	ra,4(sp)
+ 8016af8:	df000017 	ldw	fp,0(sp)
+ 8016afc:	dec00204 	addi	sp,sp,8
+ 8016b00:	f800283a 	ret
+
+08016b04 <OSTaskDelReq>:
+*********************************************************************************************************
+*/
+/*$PAGE*/
+#if OS_TASK_DEL_EN > 0
+INT8U  OSTaskDelReq (INT8U prio)
+{
+ 8016b04:	defff504 	addi	sp,sp,-44
+ 8016b08:	df000a15 	stw	fp,40(sp)
+ 8016b0c:	df000a04 	addi	fp,sp,40
+ 8016b10:	2005883a 	mov	r2,r4
+ 8016b14:	e0bff605 	stb	r2,-40(fp)
+    INT8U      stat;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8016b18:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (prio == OS_TASK_IDLE_PRIO) {                            /* Not allowed to delete idle task     */
+ 8016b1c:	e0bff603 	ldbu	r2,-40(fp)
+ 8016b20:	10800518 	cmpnei	r2,r2,20
+ 8016b24:	1000021e 	bne	r2,zero,8016b30 <OSTaskDelReq+0x2c>
+        return (OS_ERR_TASK_DEL_IDLE);
+ 8016b28:	00800f84 	movi	r2,62
+ 8016b2c:	00003b06 	br	8016c1c <OSTaskDelReq+0x118>
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+#endif
+    if (prio == OS_PRIO_SELF) {                                 /* See if a task is requesting to ...  */
+ 8016b30:	e0bff603 	ldbu	r2,-40(fp)
+ 8016b34:	10803fd8 	cmpnei	r2,r2,255
+ 8016b38:	1000111e 	bne	r2,zero,8016b80 <OSTaskDelReq+0x7c>
+  NIOS2_READ_STATUS (context);
+ 8016b3c:	0005303a 	rdctl	r2,status
+ 8016b40:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016b44:	e0fffb17 	ldw	r3,-20(fp)
+ 8016b48:	00bfff84 	movi	r2,-2
+ 8016b4c:	1884703a 	and	r2,r3,r2
+ 8016b50:	1001703a 	wrctl	status,r2
+  return context;
+ 8016b54:	e0bffb17 	ldw	r2,-20(fp)
+        OS_ENTER_CRITICAL();                                    /* ... this task to delete itself      */
+ 8016b58:	e0bfff15 	stw	r2,-4(fp)
+        stat = OSTCBCur->OSTCBDelReq;                           /* Return request status to caller     */
+ 8016b5c:	d0a05817 	ldw	r2,-32416(gp)
+ 8016b60:	10800dc3 	ldbu	r2,55(r2)
+ 8016b64:	e0bffec5 	stb	r2,-5(fp)
+ 8016b68:	e0bfff17 	ldw	r2,-4(fp)
+ 8016b6c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016b70:	e0bffc17 	ldw	r2,-16(fp)
+ 8016b74:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (stat);
+ 8016b78:	e0bffec3 	ldbu	r2,-5(fp)
+ 8016b7c:	00002706 	br	8016c1c <OSTaskDelReq+0x118>
+  NIOS2_READ_STATUS (context);
+ 8016b80:	0005303a 	rdctl	r2,status
+ 8016b84:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016b88:	e0fffa17 	ldw	r3,-24(fp)
+ 8016b8c:	00bfff84 	movi	r2,-2
+ 8016b90:	1884703a 	and	r2,r3,r2
+ 8016b94:	1001703a 	wrctl	status,r2
+  return context;
+ 8016b98:	e0bffa17 	ldw	r2,-24(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8016b9c:	e0bfff15 	stw	r2,-4(fp)
+    ptcb = OSTCBPrioTbl[prio];
+ 8016ba0:	e0bff603 	ldbu	r2,-40(fp)
+ 8016ba4:	100690ba 	slli	r3,r2,2
+ 8016ba8:	008201b4 	movhi	r2,2054
+ 8016bac:	1885883a 	add	r2,r3,r2
+ 8016bb0:	10b55d17 	ldw	r2,-10892(r2)
+ 8016bb4:	e0bffd15 	stw	r2,-12(fp)
+    if (ptcb == (OS_TCB *)0) {                                  /* Task to delete must exist           */
+ 8016bb8:	e0bffd17 	ldw	r2,-12(fp)
+ 8016bbc:	1000061e 	bne	r2,zero,8016bd8 <OSTaskDelReq+0xd4>
+ 8016bc0:	e0bfff17 	ldw	r2,-4(fp)
+ 8016bc4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016bc8:	e0bff917 	ldw	r2,-28(fp)
+ 8016bcc:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                         /* Task must already be deleted        */
+ 8016bd0:	008010c4 	movi	r2,67
+ 8016bd4:	00001106 	br	8016c1c <OSTaskDelReq+0x118>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                              /* Must NOT be assigned to a Mutex     */
+ 8016bd8:	e0bffd17 	ldw	r2,-12(fp)
+ 8016bdc:	10800058 	cmpnei	r2,r2,1
+ 8016be0:	1000061e 	bne	r2,zero,8016bfc <OSTaskDelReq+0xf8>
+ 8016be4:	e0bfff17 	ldw	r2,-4(fp)
+ 8016be8:	e0bff815 	stw	r2,-32(fp)
+ 8016bec:	e0bff817 	ldw	r2,-32(fp)
+ 8016bf0:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_DEL);
+ 8016bf4:	00800f44 	movi	r2,61
+ 8016bf8:	00000806 	br	8016c1c <OSTaskDelReq+0x118>
+    }
+    ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ;                    /* Set flag indicating task to be DEL. */
+ 8016bfc:	e0bffd17 	ldw	r2,-12(fp)
+ 8016c00:	00c00fc4 	movi	r3,63
+ 8016c04:	10c00dc5 	stb	r3,55(r2)
+ 8016c08:	e0bfff17 	ldw	r2,-4(fp)
+ 8016c0c:	e0bff715 	stw	r2,-36(fp)
+ 8016c10:	e0bff717 	ldw	r2,-36(fp)
+ 8016c14:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 8016c18:	0005883a 	mov	r2,zero
+}
+ 8016c1c:	e037883a 	mov	sp,fp
+ 8016c20:	df000017 	ldw	fp,0(sp)
+ 8016c24:	dec00104 	addi	sp,sp,4
+ 8016c28:	f800283a 	ret
+
+08016c2c <OSTaskNameGet>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_NAME_SIZE > 1
+INT8U  OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr)
+{
+ 8016c2c:	defff404 	addi	sp,sp,-48
+ 8016c30:	dfc00b15 	stw	ra,44(sp)
+ 8016c34:	df000a15 	stw	fp,40(sp)
+ 8016c38:	df000a04 	addi	fp,sp,40
+ 8016c3c:	2005883a 	mov	r2,r4
+ 8016c40:	e17ff715 	stw	r5,-36(fp)
+ 8016c44:	e1bff615 	stw	r6,-40(fp)
+ 8016c48:	e0bff805 	stb	r2,-32(fp)
+    OS_TCB    *ptcb;
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                              /* Allocate storage for CPU status register   */
+    OS_CPU_SR  cpu_sr = 0;
+ 8016c4c:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                           /* Is 'pname' a NULL pointer?                 */
+        *perr = OS_ERR_PNAME_NULL;                       /* Yes                                        */
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                              /* See if trying to call from an ISR          */
+ 8016c50:	d0a05703 	ldbu	r2,-32420(gp)
+ 8016c54:	10803fcc 	andi	r2,r2,255
+ 8016c58:	10000526 	beq	r2,zero,8016c70 <OSTaskNameGet+0x44>
+        *perr = OS_ERR_NAME_GET_ISR;
+ 8016c5c:	e0bff617 	ldw	r2,-40(fp)
+ 8016c60:	00c00444 	movi	r3,17
+ 8016c64:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8016c68:	0005883a 	mov	r2,zero
+ 8016c6c:	00003806 	br	8016d50 <OSTaskNameGet+0x124>
+  NIOS2_READ_STATUS (context);
+ 8016c70:	0005303a 	rdctl	r2,status
+ 8016c74:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016c78:	e0fffc17 	ldw	r3,-16(fp)
+ 8016c7c:	00bfff84 	movi	r2,-2
+ 8016c80:	1884703a 	and	r2,r3,r2
+ 8016c84:	1001703a 	wrctl	status,r2
+  return context;
+ 8016c88:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8016c8c:	e0bfff15 	stw	r2,-4(fp)
+    if (prio == OS_PRIO_SELF) {                          /* See if caller desires it's own name        */
+ 8016c90:	e0bff803 	ldbu	r2,-32(fp)
+ 8016c94:	10803fd8 	cmpnei	r2,r2,255
+ 8016c98:	1000031e 	bne	r2,zero,8016ca8 <OSTaskNameGet+0x7c>
+        prio = OSTCBCur->OSTCBPrio;
+ 8016c9c:	d0a05817 	ldw	r2,-32416(gp)
+ 8016ca0:	10800c83 	ldbu	r2,50(r2)
+ 8016ca4:	e0bff805 	stb	r2,-32(fp)
+    }
+    ptcb = OSTCBPrioTbl[prio];
+ 8016ca8:	e0bff803 	ldbu	r2,-32(fp)
+ 8016cac:	100690ba 	slli	r3,r2,2
+ 8016cb0:	008201b4 	movhi	r2,2054
+ 8016cb4:	1885883a 	add	r2,r3,r2
+ 8016cb8:	10b55d17 	ldw	r2,-10892(r2)
+ 8016cbc:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {                           /* Does task exist?                           */
+ 8016cc0:	e0bffe17 	ldw	r2,-8(fp)
+ 8016cc4:	1000091e 	bne	r2,zero,8016cec <OSTaskNameGet+0xc0>
+ 8016cc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8016ccc:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016cd0:	e0bffb17 	ldw	r2,-20(fp)
+ 8016cd4:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                              /* No                                         */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+ 8016cd8:	e0bff617 	ldw	r2,-40(fp)
+ 8016cdc:	00c010c4 	movi	r3,67
+ 8016ce0:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8016ce4:	0005883a 	mov	r2,zero
+ 8016ce8:	00001906 	br	8016d50 <OSTaskNameGet+0x124>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                       /* Task assigned to a Mutex?                  */
+ 8016cec:	e0bffe17 	ldw	r2,-8(fp)
+ 8016cf0:	10800058 	cmpnei	r2,r2,1
+ 8016cf4:	1000091e 	bne	r2,zero,8016d1c <OSTaskNameGet+0xf0>
+ 8016cf8:	e0bfff17 	ldw	r2,-4(fp)
+ 8016cfc:	e0bffa15 	stw	r2,-24(fp)
+ 8016d00:	e0bffa17 	ldw	r2,-24(fp)
+ 8016d04:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                              /* Yes                                        */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+ 8016d08:	e0bff617 	ldw	r2,-40(fp)
+ 8016d0c:	00c010c4 	movi	r3,67
+ 8016d10:	10c00005 	stb	r3,0(r2)
+        return (0);
+ 8016d14:	0005883a 	mov	r2,zero
+ 8016d18:	00000d06 	br	8016d50 <OSTaskNameGet+0x124>
+    }
+    len   = OS_StrCopy(pname, ptcb->OSTCBTaskName);      /* Yes, copy name from TCB                    */
+ 8016d1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016d20:	10801304 	addi	r2,r2,76
+ 8016d24:	100b883a 	mov	r5,r2
+ 8016d28:	e13ff717 	ldw	r4,-36(fp)
+ 8016d2c:	80117a00 	call	80117a0 <OS_StrCopy>
+ 8016d30:	e0bffdc5 	stb	r2,-9(fp)
+ 8016d34:	e0bfff17 	ldw	r2,-4(fp)
+ 8016d38:	e0bff915 	stw	r2,-28(fp)
+ 8016d3c:	e0bff917 	ldw	r2,-28(fp)
+ 8016d40:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8016d44:	e0bff617 	ldw	r2,-40(fp)
+ 8016d48:	10000005 	stb	zero,0(r2)
+    return (len);
+ 8016d4c:	e0bffdc3 	ldbu	r2,-9(fp)
+}
+ 8016d50:	e037883a 	mov	sp,fp
+ 8016d54:	dfc00117 	ldw	ra,4(sp)
+ 8016d58:	df000017 	ldw	fp,0(sp)
+ 8016d5c:	dec00204 	addi	sp,sp,8
+ 8016d60:	f800283a 	ret
+
+08016d64 <OSTaskNameSet>:
+* Returns    : None
+*********************************************************************************************************
+*/
+#if OS_TASK_NAME_SIZE > 1
+void  OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr)
+{
+ 8016d64:	defff304 	addi	sp,sp,-52
+ 8016d68:	dfc00c15 	stw	ra,48(sp)
+ 8016d6c:	df000b15 	stw	fp,44(sp)
+ 8016d70:	df000b04 	addi	fp,sp,44
+ 8016d74:	2005883a 	mov	r2,r4
+ 8016d78:	e17ff615 	stw	r5,-40(fp)
+ 8016d7c:	e1bff515 	stw	r6,-44(fp)
+ 8016d80:	e0bff705 	stb	r2,-36(fp)
+    INT8U      len;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                          /* Allocate storage for CPU status register       */
+    OS_CPU_SR  cpu_sr = 0;
+ 8016d84:	e03fff15 	stw	zero,-4(fp)
+    if (pname == (INT8U *)0) {                       /* Is 'pname' a NULL pointer?                     */
+        *perr = OS_ERR_PNAME_NULL;                   /* Yes                                            */
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                          /* See if trying to call from an ISR              */
+ 8016d88:	d0a05703 	ldbu	r2,-32420(gp)
+ 8016d8c:	10803fcc 	andi	r2,r2,255
+ 8016d90:	10000426 	beq	r2,zero,8016da4 <OSTaskNameSet+0x40>
+        *perr = OS_ERR_NAME_SET_ISR;
+ 8016d94:	e0bff517 	ldw	r2,-44(fp)
+ 8016d98:	00c00484 	movi	r3,18
+ 8016d9c:	10c00005 	stb	r3,0(r2)
+        return;
+ 8016da0:	00004206 	br	8016eac <OSTaskNameSet+0x148>
+  NIOS2_READ_STATUS (context);
+ 8016da4:	0005303a 	rdctl	r2,status
+ 8016da8:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016dac:	e0fffc17 	ldw	r3,-16(fp)
+ 8016db0:	00bfff84 	movi	r2,-2
+ 8016db4:	1884703a 	and	r2,r3,r2
+ 8016db8:	1001703a 	wrctl	status,r2
+  return context;
+ 8016dbc:	e0bffc17 	ldw	r2,-16(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8016dc0:	e0bfff15 	stw	r2,-4(fp)
+    if (prio == OS_PRIO_SELF) {                      /* See if caller desires to set it's own name     */
+ 8016dc4:	e0bff703 	ldbu	r2,-36(fp)
+ 8016dc8:	10803fd8 	cmpnei	r2,r2,255
+ 8016dcc:	1000031e 	bne	r2,zero,8016ddc <OSTaskNameSet+0x78>
+        prio = OSTCBCur->OSTCBPrio;
+ 8016dd0:	d0a05817 	ldw	r2,-32416(gp)
+ 8016dd4:	10800c83 	ldbu	r2,50(r2)
+ 8016dd8:	e0bff705 	stb	r2,-36(fp)
+    }
+    ptcb = OSTCBPrioTbl[prio];
+ 8016ddc:	e0bff703 	ldbu	r2,-36(fp)
+ 8016de0:	100690ba 	slli	r3,r2,2
+ 8016de4:	008201b4 	movhi	r2,2054
+ 8016de8:	1885883a 	add	r2,r3,r2
+ 8016dec:	10b55d17 	ldw	r2,-10892(r2)
+ 8016df0:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {                       /* Does task exist?                               */
+ 8016df4:	e0bffe17 	ldw	r2,-8(fp)
+ 8016df8:	1000081e 	bne	r2,zero,8016e1c <OSTaskNameSet+0xb8>
+ 8016dfc:	e0bfff17 	ldw	r2,-4(fp)
+ 8016e00:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016e04:	e0bffb17 	ldw	r2,-20(fp)
+ 8016e08:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                          /* No                                             */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+ 8016e0c:	e0bff517 	ldw	r2,-44(fp)
+ 8016e10:	00c010c4 	movi	r3,67
+ 8016e14:	10c00005 	stb	r3,0(r2)
+        return;
+ 8016e18:	00002406 	br	8016eac <OSTaskNameSet+0x148>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                   /* Task assigned to a Mutex?                      */
+ 8016e1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016e20:	10800058 	cmpnei	r2,r2,1
+ 8016e24:	1000081e 	bne	r2,zero,8016e48 <OSTaskNameSet+0xe4>
+ 8016e28:	e0bfff17 	ldw	r2,-4(fp)
+ 8016e2c:	e0bffa15 	stw	r2,-24(fp)
+ 8016e30:	e0bffa17 	ldw	r2,-24(fp)
+ 8016e34:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();                          /* Yes                                            */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+ 8016e38:	e0bff517 	ldw	r2,-44(fp)
+ 8016e3c:	00c010c4 	movi	r3,67
+ 8016e40:	10c00005 	stb	r3,0(r2)
+        return;
+ 8016e44:	00001906 	br	8016eac <OSTaskNameSet+0x148>
+    }
+    len = OS_StrLen(pname);                          /* Yes, Can we fit the string in the TCB?         */
+ 8016e48:	e13ff617 	ldw	r4,-40(fp)
+ 8016e4c:	80118140 	call	8011814 <OS_StrLen>
+ 8016e50:	e0bffdc5 	stb	r2,-9(fp)
+    if (len > (OS_TASK_NAME_SIZE - 1)) {             /*      No                                        */
+ 8016e54:	e0bffdc3 	ldbu	r2,-9(fp)
+ 8016e58:	10800830 	cmpltui	r2,r2,32
+ 8016e5c:	1000081e 	bne	r2,zero,8016e80 <OSTaskNameSet+0x11c>
+ 8016e60:	e0bfff17 	ldw	r2,-4(fp)
+ 8016e64:	e0bff915 	stw	r2,-28(fp)
+ 8016e68:	e0bff917 	ldw	r2,-28(fp)
+ 8016e6c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_TASK_NAME_TOO_LONG;
+ 8016e70:	e0bff517 	ldw	r2,-44(fp)
+ 8016e74:	00c01044 	movi	r3,65
+ 8016e78:	10c00005 	stb	r3,0(r2)
+        return;
+ 8016e7c:	00000b06 	br	8016eac <OSTaskNameSet+0x148>
+    }
+    (void)OS_StrCopy(ptcb->OSTCBTaskName, pname);    /*      Yes, copy to TCB                          */
+ 8016e80:	e0bffe17 	ldw	r2,-8(fp)
+ 8016e84:	10801304 	addi	r2,r2,76
+ 8016e88:	e17ff617 	ldw	r5,-40(fp)
+ 8016e8c:	1009883a 	mov	r4,r2
+ 8016e90:	80117a00 	call	80117a0 <OS_StrCopy>
+ 8016e94:	e0bfff17 	ldw	r2,-4(fp)
+ 8016e98:	e0bff815 	stw	r2,-32(fp)
+ 8016e9c:	e0bff817 	ldw	r2,-32(fp)
+ 8016ea0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+ 8016ea4:	e0bff517 	ldw	r2,-44(fp)
+ 8016ea8:	10000005 	stb	zero,0(r2)
+}
+ 8016eac:	e037883a 	mov	sp,fp
+ 8016eb0:	dfc00117 	ldw	ra,4(sp)
+ 8016eb4:	df000017 	ldw	fp,0(sp)
+ 8016eb8:	dec00204 	addi	sp,sp,8
+ 8016ebc:	f800283a 	ret
+
+08016ec0 <OSTaskResume>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SUSPEND_EN > 0
+INT8U  OSTaskResume (INT8U prio)
+{
+ 8016ec0:	defff404 	addi	sp,sp,-48
+ 8016ec4:	dfc00b15 	stw	ra,44(sp)
+ 8016ec8:	df000a15 	stw	fp,40(sp)
+ 8016ecc:	df000a04 	addi	fp,sp,40
+ 8016ed0:	2005883a 	mov	r2,r4
+ 8016ed4:	e0bff605 	stb	r2,-40(fp)
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                   /* Storage for CPU status register       */
+    OS_CPU_SR  cpu_sr = 0;
+ 8016ed8:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8016edc:	0005303a 	rdctl	r2,status
+ 8016ee0:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8016ee4:	e0fffd17 	ldw	r3,-12(fp)
+ 8016ee8:	00bfff84 	movi	r2,-2
+ 8016eec:	1884703a 	and	r2,r3,r2
+ 8016ef0:	1001703a 	wrctl	status,r2
+  return context;
+ 8016ef4:	e0bffd17 	ldw	r2,-12(fp)
+#if OS_ARG_CHK_EN > 0
+    if (prio >= OS_LOWEST_PRIO) {                             /* Make sure task priority is valid      */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 8016ef8:	e0bfff15 	stw	r2,-4(fp)
+    ptcb = OSTCBPrioTbl[prio];
+ 8016efc:	e0bff603 	ldbu	r2,-40(fp)
+ 8016f00:	100690ba 	slli	r3,r2,2
+ 8016f04:	008201b4 	movhi	r2,2054
+ 8016f08:	1885883a 	add	r2,r3,r2
+ 8016f0c:	10b55d17 	ldw	r2,-10892(r2)
+ 8016f10:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {                                /* Task to suspend must exist            */
+ 8016f14:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f18:	1000061e 	bne	r2,zero,8016f34 <OSTaskResume+0x74>
+ 8016f1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8016f20:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8016f24:	e0bffc17 	ldw	r2,-16(fp)
+ 8016f28:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_RESUME_PRIO);
+ 8016f2c:	00801184 	movi	r2,70
+ 8016f30:	00004c06 	br	8017064 <OSTaskResume+0x1a4>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                            /* See if assigned to Mutex              */
+ 8016f34:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f38:	10800058 	cmpnei	r2,r2,1
+ 8016f3c:	1000061e 	bne	r2,zero,8016f58 <OSTaskResume+0x98>
+ 8016f40:	e0bfff17 	ldw	r2,-4(fp)
+ 8016f44:	e0bffb15 	stw	r2,-20(fp)
+ 8016f48:	e0bffb17 	ldw	r2,-20(fp)
+ 8016f4c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+ 8016f50:	008010c4 	movi	r2,67
+ 8016f54:	00004306 	br	8017064 <OSTaskResume+0x1a4>
+    }
+    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended                */
+ 8016f58:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f5c:	10800c03 	ldbu	r2,48(r2)
+ 8016f60:	10803fcc 	andi	r2,r2,255
+ 8016f64:	1080020c 	andi	r2,r2,8
+ 8016f68:	10003926 	beq	r2,zero,8017050 <OSTaskResume+0x190>
+        ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND;           /* Remove suspension                     */
+ 8016f6c:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f70:	10c00c03 	ldbu	r3,48(r2)
+ 8016f74:	00bffdc4 	movi	r2,-9
+ 8016f78:	1884703a 	and	r2,r3,r2
+ 8016f7c:	1007883a 	mov	r3,r2
+ 8016f80:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f84:	10c00c05 	stb	r3,48(r2)
+        if (ptcb->OSTCBStat == OS_STAT_RDY) {                 /* See if task is now ready              */
+ 8016f88:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f8c:	10800c03 	ldbu	r2,48(r2)
+ 8016f90:	10803fcc 	andi	r2,r2,255
+ 8016f94:	1000281e 	bne	r2,zero,8017038 <OSTaskResume+0x178>
+            if (ptcb->OSTCBDly == 0) {
+ 8016f98:	e0bffe17 	ldw	r2,-8(fp)
+ 8016f9c:	10800b8b 	ldhu	r2,46(r2)
+ 8016fa0:	10bfffcc 	andi	r2,r2,65535
+ 8016fa4:	10001f1e 	bne	r2,zero,8017024 <OSTaskResume+0x164>
+                OSRdyGrp               |= ptcb->OSTCBBitY;    /* Yes, Make task ready to run           */
+ 8016fa8:	e0bffe17 	ldw	r2,-8(fp)
+ 8016fac:	10c00d83 	ldbu	r3,54(r2)
+ 8016fb0:	d0a05503 	ldbu	r2,-32428(gp)
+ 8016fb4:	1884b03a 	or	r2,r3,r2
+ 8016fb8:	d0a05505 	stb	r2,-32428(gp)
+                OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8016fbc:	e0bffe17 	ldw	r2,-8(fp)
+ 8016fc0:	10800d03 	ldbu	r2,52(r2)
+ 8016fc4:	10c03fcc 	andi	r3,r2,255
+ 8016fc8:	d0a05544 	addi	r2,gp,-32427
+ 8016fcc:	1885883a 	add	r2,r3,r2
+ 8016fd0:	11000003 	ldbu	r4,0(r2)
+ 8016fd4:	e0bffe17 	ldw	r2,-8(fp)
+ 8016fd8:	10800d43 	ldbu	r2,53(r2)
+ 8016fdc:	e0fffe17 	ldw	r3,-8(fp)
+ 8016fe0:	18c00d03 	ldbu	r3,52(r3)
+ 8016fe4:	18c03fcc 	andi	r3,r3,255
+ 8016fe8:	2084b03a 	or	r2,r4,r2
+ 8016fec:	1009883a 	mov	r4,r2
+ 8016ff0:	d0a05544 	addi	r2,gp,-32427
+ 8016ff4:	1885883a 	add	r2,r3,r2
+ 8016ff8:	11000005 	stb	r4,0(r2)
+ 8016ffc:	e0bfff17 	ldw	r2,-4(fp)
+ 8017000:	e0bffa15 	stw	r2,-24(fp)
+ 8017004:	e0bffa17 	ldw	r2,-24(fp)
+ 8017008:	1001703a 	wrctl	status,r2
+                OS_EXIT_CRITICAL();
+                if (OSRunning == OS_TRUE) {
+ 801700c:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8017010:	10803fcc 	andi	r2,r2,255
+ 8017014:	10800058 	cmpnei	r2,r2,1
+ 8017018:	10000b1e 	bne	r2,zero,8017048 <OSTaskResume+0x188>
+                    OS_Sched();                               /* Find new highest priority task        */
+ 801701c:	801166c0 	call	801166c <OS_Sched>
+ 8017020:	00000906 	br	8017048 <OSTaskResume+0x188>
+ 8017024:	e0bfff17 	ldw	r2,-4(fp)
+ 8017028:	e0bff915 	stw	r2,-28(fp)
+ 801702c:	e0bff917 	ldw	r2,-28(fp)
+ 8017030:	1001703a 	wrctl	status,r2
+ 8017034:	00000406 	br	8017048 <OSTaskResume+0x188>
+ 8017038:	e0bfff17 	ldw	r2,-4(fp)
+ 801703c:	e0bff815 	stw	r2,-32(fp)
+ 8017040:	e0bff817 	ldw	r2,-32(fp)
+ 8017044:	1001703a 	wrctl	status,r2
+                OS_EXIT_CRITICAL();
+            }
+        } else {                                              /* Must be pending on event              */
+            OS_EXIT_CRITICAL();
+        }
+        return (OS_ERR_NONE);
+ 8017048:	0005883a 	mov	r2,zero
+ 801704c:	00000506 	br	8017064 <OSTaskResume+0x1a4>
+ 8017050:	e0bfff17 	ldw	r2,-4(fp)
+ 8017054:	e0bff715 	stw	r2,-36(fp)
+ 8017058:	e0bff717 	ldw	r2,-36(fp)
+ 801705c:	1001703a 	wrctl	status,r2
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_TASK_NOT_SUSPENDED);
+ 8017060:	00801104 	movi	r2,68
+}
+ 8017064:	e037883a 	mov	sp,fp
+ 8017068:	dfc00117 	ldw	ra,4(sp)
+ 801706c:	df000017 	ldw	fp,0(sp)
+ 8017070:	dec00204 	addi	sp,sp,8
+ 8017074:	f800283a 	ret
+
+08017078 <OSTaskSuspend>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SUSPEND_EN > 0
+INT8U  OSTaskSuspend (INT8U prio)
+{
+ 8017078:	defff504 	addi	sp,sp,-44
+ 801707c:	dfc00a15 	stw	ra,40(sp)
+ 8017080:	df000915 	stw	fp,36(sp)
+ 8017084:	df000904 	addi	fp,sp,36
+ 8017088:	2005883a 	mov	r2,r4
+ 801708c:	e0bff705 	stb	r2,-36(fp)
+    BOOLEAN    self;
+    OS_TCB    *ptcb;
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8017090:	e03ffe15 	stw	zero,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 8017094:	0005303a 	rdctl	r2,status
+ 8017098:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801709c:	e0fffb17 	ldw	r3,-20(fp)
+ 80170a0:	00bfff84 	movi	r2,-2
+ 80170a4:	1884703a 	and	r2,r3,r2
+ 80170a8:	1001703a 	wrctl	status,r2
+  return context;
+ 80170ac:	e0bffb17 	ldw	r2,-20(fp)
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 80170b0:	e0bffe15 	stw	r2,-8(fp)
+    if (prio == OS_PRIO_SELF) {                                 /* See if suspend SELF                 */
+ 80170b4:	e0bff703 	ldbu	r2,-36(fp)
+ 80170b8:	10803fd8 	cmpnei	r2,r2,255
+ 80170bc:	1000061e 	bne	r2,zero,80170d8 <OSTaskSuspend+0x60>
+        prio = OSTCBCur->OSTCBPrio;
+ 80170c0:	d0a05817 	ldw	r2,-32416(gp)
+ 80170c4:	10800c83 	ldbu	r2,50(r2)
+ 80170c8:	e0bff705 	stb	r2,-36(fp)
+        self = OS_TRUE;
+ 80170cc:	00800044 	movi	r2,1
+ 80170d0:	e0bfffc5 	stb	r2,-1(fp)
+ 80170d4:	00000906 	br	80170fc <OSTaskSuspend+0x84>
+    } else if (prio == OSTCBCur->OSTCBPrio) {                   /* See if suspending self              */
+ 80170d8:	d0a05817 	ldw	r2,-32416(gp)
+ 80170dc:	10800c83 	ldbu	r2,50(r2)
+ 80170e0:	e0fff703 	ldbu	r3,-36(fp)
+ 80170e4:	10803fcc 	andi	r2,r2,255
+ 80170e8:	1880031e 	bne	r3,r2,80170f8 <OSTaskSuspend+0x80>
+        self = OS_TRUE;
+ 80170ec:	00800044 	movi	r2,1
+ 80170f0:	e0bfffc5 	stb	r2,-1(fp)
+ 80170f4:	00000106 	br	80170fc <OSTaskSuspend+0x84>
+    } else {
+        self = OS_FALSE;                                        /* No suspending another task          */
+ 80170f8:	e03fffc5 	stb	zero,-1(fp)
+    }
+    ptcb = OSTCBPrioTbl[prio];
+ 80170fc:	e0bff703 	ldbu	r2,-36(fp)
+ 8017100:	100690ba 	slli	r3,r2,2
+ 8017104:	008201b4 	movhi	r2,2054
+ 8017108:	1885883a 	add	r2,r3,r2
+ 801710c:	10b55d17 	ldw	r2,-10892(r2)
+ 8017110:	e0bffd15 	stw	r2,-12(fp)
+    if (ptcb == (OS_TCB *)0) {                                  /* Task to suspend must exist          */
+ 8017114:	e0bffd17 	ldw	r2,-12(fp)
+ 8017118:	1000061e 	bne	r2,zero,8017134 <OSTaskSuspend+0xbc>
+ 801711c:	e0bffe17 	ldw	r2,-8(fp)
+ 8017120:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8017124:	e0bffa17 	ldw	r2,-24(fp)
+ 8017128:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_SUSPEND_PRIO);
+ 801712c:	00801204 	movi	r2,72
+ 8017130:	00003606 	br	801720c <OSTaskSuspend+0x194>
+    }
+    if (ptcb == OS_TCB_RESERVED) {                              /* See if assigned to Mutex            */
+ 8017134:	e0bffd17 	ldw	r2,-12(fp)
+ 8017138:	10800058 	cmpnei	r2,r2,1
+ 801713c:	1000061e 	bne	r2,zero,8017158 <OSTaskSuspend+0xe0>
+ 8017140:	e0bffe17 	ldw	r2,-8(fp)
+ 8017144:	e0bff915 	stw	r2,-28(fp)
+ 8017148:	e0bff917 	ldw	r2,-28(fp)
+ 801714c:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+ 8017150:	008010c4 	movi	r2,67
+ 8017154:	00002d06 	br	801720c <OSTaskSuspend+0x194>
+    }
+    y            = ptcb->OSTCBY;
+ 8017158:	e0bffd17 	ldw	r2,-12(fp)
+ 801715c:	10800d03 	ldbu	r2,52(r2)
+ 8017160:	e0bffcc5 	stb	r2,-13(fp)
+    OSRdyTbl[y] &= ~ptcb->OSTCBBitX;                            /* Make task not ready                 */
+ 8017164:	e0fffcc3 	ldbu	r3,-13(fp)
+ 8017168:	d0a05544 	addi	r2,gp,-32427
+ 801716c:	1885883a 	add	r2,r3,r2
+ 8017170:	10800003 	ldbu	r2,0(r2)
+ 8017174:	1007883a 	mov	r3,r2
+ 8017178:	e0bffd17 	ldw	r2,-12(fp)
+ 801717c:	10800d43 	ldbu	r2,53(r2)
+ 8017180:	0084303a 	nor	r2,zero,r2
+ 8017184:	1884703a 	and	r2,r3,r2
+ 8017188:	e0fffcc3 	ldbu	r3,-13(fp)
+ 801718c:	1009883a 	mov	r4,r2
+ 8017190:	d0a05544 	addi	r2,gp,-32427
+ 8017194:	1885883a 	add	r2,r3,r2
+ 8017198:	11000005 	stb	r4,0(r2)
+    if (OSRdyTbl[y] == 0) {
+ 801719c:	e0fffcc3 	ldbu	r3,-13(fp)
+ 80171a0:	d0a05544 	addi	r2,gp,-32427
+ 80171a4:	1885883a 	add	r2,r3,r2
+ 80171a8:	10800003 	ldbu	r2,0(r2)
+ 80171ac:	10803fcc 	andi	r2,r2,255
+ 80171b0:	1000071e 	bne	r2,zero,80171d0 <OSTaskSuspend+0x158>
+        OSRdyGrp &= ~ptcb->OSTCBBitY;
+ 80171b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80171b8:	10800d83 	ldbu	r2,54(r2)
+ 80171bc:	0084303a 	nor	r2,zero,r2
+ 80171c0:	1007883a 	mov	r3,r2
+ 80171c4:	d0a05503 	ldbu	r2,-32428(gp)
+ 80171c8:	1884703a 	and	r2,r3,r2
+ 80171cc:	d0a05505 	stb	r2,-32428(gp)
+    }
+    ptcb->OSTCBStat |= OS_STAT_SUSPEND;                         /* Status of task is 'SUSPENDED'       */
+ 80171d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80171d4:	10800c03 	ldbu	r2,48(r2)
+ 80171d8:	10800214 	ori	r2,r2,8
+ 80171dc:	1007883a 	mov	r3,r2
+ 80171e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80171e4:	10c00c05 	stb	r3,48(r2)
+ 80171e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80171ec:	e0bff815 	stw	r2,-32(fp)
+ 80171f0:	e0bff817 	ldw	r2,-32(fp)
+ 80171f4:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    if (self == OS_TRUE) {                                      /* Context switch only if SELF         */
+ 80171f8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80171fc:	10800058 	cmpnei	r2,r2,1
+ 8017200:	1000011e 	bne	r2,zero,8017208 <OSTaskSuspend+0x190>
+        OS_Sched();                                             /* Find new highest priority task      */
+ 8017204:	801166c0 	call	801166c <OS_Sched>
+    }
+    return (OS_ERR_NONE);
+ 8017208:	0005883a 	mov	r2,zero
+}
+ 801720c:	e037883a 	mov	sp,fp
+ 8017210:	dfc00117 	ldw	ra,4(sp)
+ 8017214:	df000017 	ldw	fp,0(sp)
+ 8017218:	dec00204 	addi	sp,sp,8
+ 801721c:	f800283a 	ret
+
+08017220 <OSTaskQuery>:
+*********************************************************************************************************
+*/
+
+#if OS_TASK_QUERY_EN > 0
+INT8U  OSTaskQuery (INT8U prio, OS_TCB *p_task_data)
+{
+ 8017220:	defff604 	addi	sp,sp,-40
+ 8017224:	dfc00915 	stw	ra,36(sp)
+ 8017228:	df000815 	stw	fp,32(sp)
+ 801722c:	df000804 	addi	fp,sp,32
+ 8017230:	2005883a 	mov	r2,r4
+ 8017234:	e17ff815 	stw	r5,-32(fp)
+ 8017238:	e0bff905 	stb	r2,-28(fp)
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 801723c:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8017240:	0005303a 	rdctl	r2,status
+ 8017244:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8017248:	e0fffd17 	ldw	r3,-12(fp)
+ 801724c:	00bfff84 	movi	r2,-2
+ 8017250:	1884703a 	and	r2,r3,r2
+ 8017254:	1001703a 	wrctl	status,r2
+  return context;
+ 8017258:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    if (p_task_data == (OS_TCB *)0) {            /* Validate 'p_task_data'                             */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+ 801725c:	e0bfff15 	stw	r2,-4(fp)
+    if (prio == OS_PRIO_SELF) {                  /* See if suspend SELF                                */
+ 8017260:	e0bff903 	ldbu	r2,-28(fp)
+ 8017264:	10803fd8 	cmpnei	r2,r2,255
+ 8017268:	1000031e 	bne	r2,zero,8017278 <OSTaskQuery+0x58>
+        prio = OSTCBCur->OSTCBPrio;
+ 801726c:	d0a05817 	ldw	r2,-32416(gp)
+ 8017270:	10800c83 	ldbu	r2,50(r2)
+ 8017274:	e0bff905 	stb	r2,-28(fp)
+    }
+    ptcb = OSTCBPrioTbl[prio];
+ 8017278:	e0bff903 	ldbu	r2,-28(fp)
+ 801727c:	100690ba 	slli	r3,r2,2
+ 8017280:	008201b4 	movhi	r2,2054
+ 8017284:	1885883a 	add	r2,r3,r2
+ 8017288:	10b55d17 	ldw	r2,-10892(r2)
+ 801728c:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {                   /* Task to query must exist                           */
+ 8017290:	e0bffe17 	ldw	r2,-8(fp)
+ 8017294:	1000061e 	bne	r2,zero,80172b0 <OSTaskQuery+0x90>
+ 8017298:	e0bfff17 	ldw	r2,-4(fp)
+ 801729c:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80172a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80172a4:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_PRIO);
+ 80172a8:	00800a44 	movi	r2,41
+ 80172ac:	00001206 	br	80172f8 <OSTaskQuery+0xd8>
+    }
+    if (ptcb == OS_TCB_RESERVED) {               /* Task to query must not be assigned to a Mutex      */
+ 80172b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80172b4:	10800058 	cmpnei	r2,r2,1
+ 80172b8:	1000061e 	bne	r2,zero,80172d4 <OSTaskQuery+0xb4>
+ 80172bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80172c0:	e0bffb15 	stw	r2,-20(fp)
+ 80172c4:	e0bffb17 	ldw	r2,-20(fp)
+ 80172c8:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+ 80172cc:	008010c4 	movi	r2,67
+ 80172d0:	00000906 	br	80172f8 <OSTaskQuery+0xd8>
+    }
+                                                 /* Copy TCB into user storage area                    */
+    OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB));
+ 80172d4:	01801b04 	movi	r6,108
+ 80172d8:	e17ffe17 	ldw	r5,-8(fp)
+ 80172dc:	e13ff817 	ldw	r4,-32(fp)
+ 80172e0:	80116040 	call	8011604 <OS_MemCopy>
+ 80172e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80172e8:	e0bffa15 	stw	r2,-24(fp)
+ 80172ec:	e0bffa17 	ldw	r2,-24(fp)
+ 80172f0:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+ 80172f4:	0005883a 	mov	r2,zero
+}
+ 80172f8:	e037883a 	mov	sp,fp
+ 80172fc:	dfc00117 	ldw	ra,4(sp)
+ 8017300:	df000017 	ldw	fp,0(sp)
+ 8017304:	dec00204 	addi	sp,sp,8
+ 8017308:	f800283a 	ret
+
+0801730c <OSTimeDly>:
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSTimeDly (INT16U ticks)
+{
+ 801730c:	defff904 	addi	sp,sp,-28
+ 8017310:	dfc00615 	stw	ra,24(sp)
+ 8017314:	df000515 	stw	fp,20(sp)
+ 8017318:	df000504 	addi	fp,sp,20
+ 801731c:	2005883a 	mov	r2,r4
+ 8017320:	e0bffb0d 	sth	r2,-20(fp)
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8017324:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 8017328:	d0a05703 	ldbu	r2,-32420(gp)
+ 801732c:	10803fcc 	andi	r2,r2,255
+ 8017330:	1000311e 	bne	r2,zero,80173f8 <OSTimeDly+0xec>
+        return;
+    }
+    if (ticks > 0) {                             /* 0 means no delay!                                  */
+ 8017334:	e0bffb0b 	ldhu	r2,-20(fp)
+ 8017338:	10003026 	beq	r2,zero,80173fc <OSTimeDly+0xf0>
+  NIOS2_READ_STATUS (context);
+ 801733c:	0005303a 	rdctl	r2,status
+ 8017340:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8017344:	e0fffd17 	ldw	r3,-12(fp)
+ 8017348:	00bfff84 	movi	r2,-2
+ 801734c:	1884703a 	and	r2,r3,r2
+ 8017350:	1001703a 	wrctl	status,r2
+  return context;
+ 8017354:	e0bffd17 	ldw	r2,-12(fp)
+        OS_ENTER_CRITICAL();
+ 8017358:	e0bfff15 	stw	r2,-4(fp)
+        y            =  OSTCBCur->OSTCBY;        /* Delay current task                                 */
+ 801735c:	d0a05817 	ldw	r2,-32416(gp)
+ 8017360:	10800d03 	ldbu	r2,52(r2)
+ 8017364:	e0bffec5 	stb	r2,-5(fp)
+        OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX;
+ 8017368:	e0fffec3 	ldbu	r3,-5(fp)
+ 801736c:	d0a05544 	addi	r2,gp,-32427
+ 8017370:	1885883a 	add	r2,r3,r2
+ 8017374:	10800003 	ldbu	r2,0(r2)
+ 8017378:	1007883a 	mov	r3,r2
+ 801737c:	d0a05817 	ldw	r2,-32416(gp)
+ 8017380:	10800d43 	ldbu	r2,53(r2)
+ 8017384:	0084303a 	nor	r2,zero,r2
+ 8017388:	1884703a 	and	r2,r3,r2
+ 801738c:	e0fffec3 	ldbu	r3,-5(fp)
+ 8017390:	1009883a 	mov	r4,r2
+ 8017394:	d0a05544 	addi	r2,gp,-32427
+ 8017398:	1885883a 	add	r2,r3,r2
+ 801739c:	11000005 	stb	r4,0(r2)
+        if (OSRdyTbl[y] == 0) {
+ 80173a0:	e0fffec3 	ldbu	r3,-5(fp)
+ 80173a4:	d0a05544 	addi	r2,gp,-32427
+ 80173a8:	1885883a 	add	r2,r3,r2
+ 80173ac:	10800003 	ldbu	r2,0(r2)
+ 80173b0:	10803fcc 	andi	r2,r2,255
+ 80173b4:	1000071e 	bne	r2,zero,80173d4 <OSTimeDly+0xc8>
+            OSRdyGrp &= ~OSTCBCur->OSTCBBitY;
+ 80173b8:	d0a05817 	ldw	r2,-32416(gp)
+ 80173bc:	10800d83 	ldbu	r2,54(r2)
+ 80173c0:	0084303a 	nor	r2,zero,r2
+ 80173c4:	1007883a 	mov	r3,r2
+ 80173c8:	d0a05503 	ldbu	r2,-32428(gp)
+ 80173cc:	1884703a 	and	r2,r3,r2
+ 80173d0:	d0a05505 	stb	r2,-32428(gp)
+        }
+        OSTCBCur->OSTCBDly = ticks;              /* Load ticks in TCB                                  */
+ 80173d4:	d0a05817 	ldw	r2,-32416(gp)
+ 80173d8:	e0fffb0b 	ldhu	r3,-20(fp)
+ 80173dc:	10c00b8d 	sth	r3,46(r2)
+ 80173e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80173e4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80173e8:	e0bffc17 	ldw	r2,-16(fp)
+ 80173ec:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OS_Sched();                              /* Find next task to run!                             */
+ 80173f0:	801166c0 	call	801166c <OS_Sched>
+ 80173f4:	00000106 	br	80173fc <OSTimeDly+0xf0>
+        return;
+ 80173f8:	0001883a 	nop
+    }
+}
+ 80173fc:	e037883a 	mov	sp,fp
+ 8017400:	dfc00117 	ldw	ra,4(sp)
+ 8017404:	df000017 	ldw	fp,0(sp)
+ 8017408:	dec00204 	addi	sp,sp,8
+ 801740c:	f800283a 	ret
+
+08017410 <OSTimeDlyHMSM>:
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_HMSM_EN > 0
+INT8U  OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms)
+{
+ 8017410:	defff704 	addi	sp,sp,-36
+ 8017414:	dfc00815 	stw	ra,32(sp)
+ 8017418:	df000715 	stw	fp,28(sp)
+ 801741c:	dc000615 	stw	r16,24(sp)
+ 8017420:	df000704 	addi	fp,sp,28
+ 8017424:	2005883a 	mov	r2,r4
+ 8017428:	3009883a 	mov	r4,r6
+ 801742c:	3807883a 	mov	r3,r7
+ 8017430:	e0bffc05 	stb	r2,-16(fp)
+ 8017434:	2805883a 	mov	r2,r5
+ 8017438:	e0bffb05 	stb	r2,-20(fp)
+ 801743c:	2005883a 	mov	r2,r4
+ 8017440:	e0bffa05 	stb	r2,-24(fp)
+ 8017444:	1805883a 	mov	r2,r3
+ 8017448:	e0bff90d 	sth	r2,-28(fp)
+    INT32U ticks;
+    INT16U loops;
+
+
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+ 801744c:	d0a05703 	ldbu	r2,-32420(gp)
+ 8017450:	10803fcc 	andi	r2,r2,255
+ 8017454:	10000226 	beq	r2,zero,8017460 <OSTimeDlyHMSM+0x50>
+        return (OS_ERR_TIME_DLY_ISR);
+ 8017458:	00801544 	movi	r2,85
+ 801745c:	00002506 	br	80174f4 <OSTimeDlyHMSM+0xe4>
+        return (OS_ERR_TIME_INVALID_MS);
+    }
+#endif
+                                                 /* Compute the total number of clock ticks required.. */
+                                                 /* .. (rounded to the nearest tick)                   */
+    ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC
+ 8017460:	e0bffc03 	ldbu	r2,-16(fp)
+ 8017464:	10c38424 	muli	r3,r2,3600
+ 8017468:	e0bffb03 	ldbu	r2,-20(fp)
+ 801746c:	10800f24 	muli	r2,r2,60
+ 8017470:	1887883a 	add	r3,r3,r2
+ 8017474:	e0bffa03 	ldbu	r2,-24(fp)
+ 8017478:	1885883a 	add	r2,r3,r2
+ 801747c:	14001924 	muli	r16,r2,100
+          + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L;
+ 8017480:	e0bff90b 	ldhu	r2,-28(fp)
+ 8017484:	10801924 	muli	r2,r2,100
+ 8017488:	10807d04 	addi	r2,r2,500
+ 801748c:	0140fa04 	movi	r5,1000
+ 8017490:	1009883a 	mov	r4,r2
+ 8017494:	800cff80 	call	800cff8 <__udivsi3>
+    ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC
+ 8017498:	8085883a 	add	r2,r16,r2
+ 801749c:	e0bffd15 	stw	r2,-12(fp)
+    loops = (INT16U)(ticks >> 16);               /* Compute the integral number of 65536 tick delays   */
+ 80174a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80174a4:	1004d43a 	srli	r2,r2,16
+ 80174a8:	e0bffe8d 	sth	r2,-6(fp)
+    ticks = ticks & 0xFFFFL;                     /* Obtain  the fractional number of ticks             */
+ 80174ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80174b0:	10bfffcc 	andi	r2,r2,65535
+ 80174b4:	e0bffd15 	stw	r2,-12(fp)
+    OSTimeDly((INT16U)ticks);
+ 80174b8:	e0bffd17 	ldw	r2,-12(fp)
+ 80174bc:	10bfffcc 	andi	r2,r2,65535
+ 80174c0:	1009883a 	mov	r4,r2
+ 80174c4:	801730c0 	call	801730c <OSTimeDly>
+    while (loops > 0) {
+ 80174c8:	00000706 	br	80174e8 <OSTimeDlyHMSM+0xd8>
+        OSTimeDly((INT16U)32768u);
+ 80174cc:	01200014 	movui	r4,32768
+ 80174d0:	801730c0 	call	801730c <OSTimeDly>
+        OSTimeDly((INT16U)32768u);
+ 80174d4:	01200014 	movui	r4,32768
+ 80174d8:	801730c0 	call	801730c <OSTimeDly>
+        loops--;
+ 80174dc:	e0bffe8b 	ldhu	r2,-6(fp)
+ 80174e0:	10bfffc4 	addi	r2,r2,-1
+ 80174e4:	e0bffe8d 	sth	r2,-6(fp)
+    while (loops > 0) {
+ 80174e8:	e0bffe8b 	ldhu	r2,-6(fp)
+ 80174ec:	103ff71e 	bne	r2,zero,80174cc <OSTimeDlyHMSM+0xbc>
+    }
+    return (OS_ERR_NONE);
+ 80174f0:	0005883a 	mov	r2,zero
+}
+ 80174f4:	e6ffff04 	addi	sp,fp,-4
+ 80174f8:	dfc00217 	ldw	ra,8(sp)
+ 80174fc:	df000117 	ldw	fp,4(sp)
+ 8017500:	dc000017 	ldw	r16,0(sp)
+ 8017504:	dec00304 	addi	sp,sp,12
+ 8017508:	f800283a 	ret
+
+0801750c <OSTimeDlyResume>:
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_RESUME_EN > 0
+INT8U  OSTimeDlyResume (INT8U prio)
+{
+ 801750c:	defff504 	addi	sp,sp,-44
+ 8017510:	dfc00a15 	stw	ra,40(sp)
+ 8017514:	df000915 	stw	fp,36(sp)
+ 8017518:	df000904 	addi	fp,sp,36
+ 801751c:	2005883a 	mov	r2,r4
+ 8017520:	e0bff705 	stb	r2,-36(fp)
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                    /* Storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+ 8017524:	e03fff15 	stw	zero,-4(fp)
+#endif
+
+
+
+    if (prio >= OS_LOWEST_PRIO) {
+ 8017528:	e0bff703 	ldbu	r2,-36(fp)
+ 801752c:	10800530 	cmpltui	r2,r2,20
+ 8017530:	1000021e 	bne	r2,zero,801753c <OSTimeDlyResume+0x30>
+        return (OS_ERR_PRIO_INVALID);
+ 8017534:	00800a84 	movi	r2,42
+ 8017538:	00006206 	br	80176c4 <OSTimeDlyResume+0x1b8>
+  NIOS2_READ_STATUS (context);
+ 801753c:	0005303a 	rdctl	r2,status
+ 8017540:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8017544:	e0fffd17 	ldw	r3,-12(fp)
+ 8017548:	00bfff84 	movi	r2,-2
+ 801754c:	1884703a 	and	r2,r3,r2
+ 8017550:	1001703a 	wrctl	status,r2
+  return context;
+ 8017554:	e0bffd17 	ldw	r2,-12(fp)
+    }
+    OS_ENTER_CRITICAL();
+ 8017558:	e0bfff15 	stw	r2,-4(fp)
+    ptcb = OSTCBPrioTbl[prio];                                 /* Make sure that task exist            */
+ 801755c:	e0bff703 	ldbu	r2,-36(fp)
+ 8017560:	100690ba 	slli	r3,r2,2
+ 8017564:	008201b4 	movhi	r2,2054
+ 8017568:	1885883a 	add	r2,r3,r2
+ 801756c:	10b55d17 	ldw	r2,-10892(r2)
+ 8017570:	e0bffe15 	stw	r2,-8(fp)
+    if (ptcb == (OS_TCB *)0) {
+ 8017574:	e0bffe17 	ldw	r2,-8(fp)
+ 8017578:	1000061e 	bne	r2,zero,8017594 <OSTimeDlyResume+0x88>
+ 801757c:	e0bfff17 	ldw	r2,-4(fp)
+ 8017580:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8017584:	e0bffc17 	ldw	r2,-16(fp)
+ 8017588:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+ 801758c:	008010c4 	movi	r2,67
+ 8017590:	00004c06 	br	80176c4 <OSTimeDlyResume+0x1b8>
+    }
+    if (ptcb == OS_TCB_RESERVED) {
+ 8017594:	e0bffe17 	ldw	r2,-8(fp)
+ 8017598:	10800058 	cmpnei	r2,r2,1
+ 801759c:	1000061e 	bne	r2,zero,80175b8 <OSTimeDlyResume+0xac>
+ 80175a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80175a4:	e0bffb15 	stw	r2,-20(fp)
+ 80175a8:	e0bffb17 	ldw	r2,-20(fp)
+ 80175ac:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+ 80175b0:	008010c4 	movi	r2,67
+ 80175b4:	00004306 	br	80176c4 <OSTimeDlyResume+0x1b8>
+    }
+    if (ptcb->OSTCBDly == 0) {                                 /* See if task is delayed               */
+ 80175b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80175bc:	10800b8b 	ldhu	r2,46(r2)
+ 80175c0:	10bfffcc 	andi	r2,r2,65535
+ 80175c4:	1000061e 	bne	r2,zero,80175e0 <OSTimeDlyResume+0xd4>
+ 80175c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80175cc:	e0bffa15 	stw	r2,-24(fp)
+ 80175d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80175d4:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TIME_NOT_DLY);                          /* Indicate that task was not delayed   */
+ 80175d8:	00801404 	movi	r2,80
+ 80175dc:	00003906 	br	80176c4 <OSTimeDlyResume+0x1b8>
+    }
+
+    ptcb->OSTCBDly = 0;                                        /* Clear the time delay                 */
+ 80175e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80175e4:	10000b8d 	sth	zero,46(r2)
+    if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) {
+ 80175e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80175ec:	10800c03 	ldbu	r2,48(r2)
+ 80175f0:	10803fcc 	andi	r2,r2,255
+ 80175f4:	10800dcc 	andi	r2,r2,55
+ 80175f8:	10000b26 	beq	r2,zero,8017628 <OSTimeDlyResume+0x11c>
+        ptcb->OSTCBStat     &= ~OS_STAT_PEND_ANY;              /* Yes, Clear status flag               */
+ 80175fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8017600:	10c00c03 	ldbu	r3,48(r2)
+ 8017604:	00bff204 	movi	r2,-56
+ 8017608:	1884703a 	and	r2,r3,r2
+ 801760c:	1007883a 	mov	r3,r2
+ 8017610:	e0bffe17 	ldw	r2,-8(fp)
+ 8017614:	10c00c05 	stb	r3,48(r2)
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_TO;               /* Indicate PEND timeout                */
+ 8017618:	e0bffe17 	ldw	r2,-8(fp)
+ 801761c:	00c00044 	movi	r3,1
+ 8017620:	10c00c45 	stb	r3,49(r2)
+ 8017624:	00000206 	br	8017630 <OSTimeDlyResume+0x124>
+    } else {
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_OK;
+ 8017628:	e0bffe17 	ldw	r2,-8(fp)
+ 801762c:	10000c45 	stb	zero,49(r2)
+    }
+    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) {  /* Is task suspended?                   */
+ 8017630:	e0bffe17 	ldw	r2,-8(fp)
+ 8017634:	10800c03 	ldbu	r2,48(r2)
+ 8017638:	10803fcc 	andi	r2,r2,255
+ 801763c:	1080020c 	andi	r2,r2,8
+ 8017640:	10001b1e 	bne	r2,zero,80176b0 <OSTimeDlyResume+0x1a4>
+        OSRdyGrp               |= ptcb->OSTCBBitY;             /* No,  Make ready                      */
+ 8017644:	e0bffe17 	ldw	r2,-8(fp)
+ 8017648:	10c00d83 	ldbu	r3,54(r2)
+ 801764c:	d0a05503 	ldbu	r2,-32428(gp)
+ 8017650:	1884b03a 	or	r2,r3,r2
+ 8017654:	d0a05505 	stb	r2,-32428(gp)
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+ 8017658:	e0bffe17 	ldw	r2,-8(fp)
+ 801765c:	10800d03 	ldbu	r2,52(r2)
+ 8017660:	10c03fcc 	andi	r3,r2,255
+ 8017664:	d0a05544 	addi	r2,gp,-32427
+ 8017668:	1885883a 	add	r2,r3,r2
+ 801766c:	11000003 	ldbu	r4,0(r2)
+ 8017670:	e0bffe17 	ldw	r2,-8(fp)
+ 8017674:	10800d43 	ldbu	r2,53(r2)
+ 8017678:	e0fffe17 	ldw	r3,-8(fp)
+ 801767c:	18c00d03 	ldbu	r3,52(r3)
+ 8017680:	18c03fcc 	andi	r3,r3,255
+ 8017684:	2084b03a 	or	r2,r4,r2
+ 8017688:	1009883a 	mov	r4,r2
+ 801768c:	d0a05544 	addi	r2,gp,-32427
+ 8017690:	1885883a 	add	r2,r3,r2
+ 8017694:	11000005 	stb	r4,0(r2)
+ 8017698:	e0bfff17 	ldw	r2,-4(fp)
+ 801769c:	e0bff915 	stw	r2,-28(fp)
+ 80176a0:	e0bff917 	ldw	r2,-28(fp)
+ 80176a4:	1001703a 	wrctl	status,r2
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                            /* See if this is new highest priority  */
+ 80176a8:	801166c0 	call	801166c <OS_Sched>
+ 80176ac:	00000406 	br	80176c0 <OSTimeDlyResume+0x1b4>
+ 80176b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80176b4:	e0bff815 	stw	r2,-32(fp)
+ 80176b8:	e0bff817 	ldw	r2,-32(fp)
+ 80176bc:	1001703a 	wrctl	status,r2
+    } else {
+        OS_EXIT_CRITICAL();                                    /* Task may be suspended                */
+    }
+    return (OS_ERR_NONE);
+ 80176c0:	0005883a 	mov	r2,zero
+}
+ 80176c4:	e037883a 	mov	sp,fp
+ 80176c8:	dfc00117 	ldw	ra,4(sp)
+ 80176cc:	df000017 	ldw	fp,0(sp)
+ 80176d0:	dec00204 	addi	sp,sp,8
+ 80176d4:	f800283a 	ret
+
+080176d8 <OSTimeGet>:
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0
+INT32U  OSTimeGet (void)
+{
+ 80176d8:	defffb04 	addi	sp,sp,-20
+ 80176dc:	df000415 	stw	fp,16(sp)
+ 80176e0:	df000404 	addi	fp,sp,16
+    INT32U     ticks;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 80176e4:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 80176e8:	0005303a 	rdctl	r2,status
+ 80176ec:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 80176f0:	e0fffc17 	ldw	r3,-16(fp)
+ 80176f4:	00bfff84 	movi	r2,-2
+ 80176f8:	1884703a 	and	r2,r3,r2
+ 80176fc:	1001703a 	wrctl	status,r2
+  return context;
+ 8017700:	e0bffc17 	ldw	r2,-16(fp)
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+ 8017704:	e0bfff15 	stw	r2,-4(fp)
+    ticks = OSTime;
+ 8017708:	d0a05917 	ldw	r2,-32412(gp)
+ 801770c:	e0bffe15 	stw	r2,-8(fp)
+ 8017710:	e0bfff17 	ldw	r2,-4(fp)
+ 8017714:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8017718:	e0bffd17 	ldw	r2,-12(fp)
+ 801771c:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+    return (ticks);
+ 8017720:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8017724:	e037883a 	mov	sp,fp
+ 8017728:	df000017 	ldw	fp,0(sp)
+ 801772c:	dec00104 	addi	sp,sp,4
+ 8017730:	f800283a 	ret
+
+08017734 <OSTimeSet>:
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0
+void  OSTimeSet (INT32U ticks)
+{
+ 8017734:	defffb04 	addi	sp,sp,-20
+ 8017738:	df000415 	stw	fp,16(sp)
+ 801773c:	df000404 	addi	fp,sp,16
+ 8017740:	e13ffc15 	stw	r4,-16(fp)
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+ 8017744:	e03fff15 	stw	zero,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8017748:	0005303a 	rdctl	r2,status
+ 801774c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8017750:	e0fffd17 	ldw	r3,-12(fp)
+ 8017754:	00bfff84 	movi	r2,-2
+ 8017758:	1884703a 	and	r2,r3,r2
+ 801775c:	1001703a 	wrctl	status,r2
+  return context;
+ 8017760:	e0bffd17 	ldw	r2,-12(fp)
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+ 8017764:	e0bfff15 	stw	r2,-4(fp)
+    OSTime = ticks;
+ 8017768:	e0bffc17 	ldw	r2,-16(fp)
+ 801776c:	d0a05915 	stw	r2,-32412(gp)
+ 8017770:	e0bfff17 	ldw	r2,-4(fp)
+ 8017774:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8017778:	e0bffe17 	ldw	r2,-8(fp)
+ 801777c:	1001703a 	wrctl	status,r2
+    OS_EXIT_CRITICAL();
+}
+ 8017780:	0001883a 	nop
+ 8017784:	e037883a 	mov	sp,fp
+ 8017788:	df000017 	ldw	fp,0(sp)
+ 801778c:	dec00104 	addi	sp,sp,4
+ 8017790:	f800283a 	ret
+
+08017794 <alt_dev_reg>:
+ */
+
+extern int alt_fs_reg  (alt_dev* dev); 
+
+static ALT_INLINE int alt_dev_reg (alt_dev* dev)
+{
+ 8017794:	defffd04 	addi	sp,sp,-12
+ 8017798:	dfc00215 	stw	ra,8(sp)
+ 801779c:	df000115 	stw	fp,4(sp)
+ 80177a0:	df000104 	addi	fp,sp,4
+ 80177a4:	e13fff15 	stw	r4,-4(fp)
+  extern alt_llist alt_dev_list;
+
+  return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list);
+ 80177a8:	d1602404 	addi	r5,gp,-32624
+ 80177ac:	e13fff17 	ldw	r4,-4(fp)
+ 80177b0:	80372a00 	call	80372a0 <alt_dev_llist_insert>
+}
+ 80177b4:	e037883a 	mov	sp,fp
+ 80177b8:	dfc00117 	ldw	ra,4(sp)
+ 80177bc:	df000017 	ldw	fp,0(sp)
+ 80177c0:	dec00204 	addi	sp,sp,8
+ 80177c4:	f800283a 	ret
+
+080177c8 <alt_irq_init>:
+ * The "base" parameter is ignored and only
+ * present for backwards-compatibility.
+ */
+
+void alt_irq_init ( const void* base )
+{
+ 80177c8:	defffd04 	addi	sp,sp,-12
+ 80177cc:	dfc00215 	stw	ra,8(sp)
+ 80177d0:	df000115 	stw	fp,4(sp)
+ 80177d4:	df000104 	addi	fp,sp,4
+ 80177d8:	e13fff15 	stw	r4,-4(fp)
+    ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu);
+ 80177dc:	80383640 	call	8038364 <altera_nios2_gen2_irq_init>
+    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
+ 80177e0:	00800044 	movi	r2,1
+ 80177e4:	1001703a 	wrctl	status,r2
+    alt_irq_cpu_enable_interrupts();
+}
+ 80177e8:	0001883a 	nop
+ 80177ec:	e037883a 	mov	sp,fp
+ 80177f0:	dfc00117 	ldw	ra,4(sp)
+ 80177f4:	df000017 	ldw	fp,0(sp)
+ 80177f8:	dec00204 	addi	sp,sp,8
+ 80177fc:	f800283a 	ret
+
+08017800 <alt_sys_init>:
+ * Initialize the non-interrupt controller devices.
+ * Called after alt_irq_init().
+ */
+
+void alt_sys_init( void )
+{
+ 8017800:	defffa04 	addi	sp,sp,-24
+ 8017804:	dfc00515 	stw	ra,20(sp)
+ 8017808:	df000415 	stw	fp,16(sp)
+ 801780c:	df000404 	addi	fp,sp,16
+    ALTERA_AVALON_TIMER_INIT ( FRAME_TIMER, frame_timer);
+    ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
+ 8017810:	01c01904 	movi	r7,100
+ 8017814:	000d883a 	mov	r6,zero
+ 8017818:	000b883a 	mov	r5,zero
+ 801781c:	01061034 	movhi	r4,6208
+ 8017820:	210f1804 	addi	r4,r4,15456
+ 8017824:	8017aa40 	call	8017aa4 <alt_avalon_timer_sc_init>
+    ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid);
+ 8017828:	0001883a 	nop
+    ALTERA_AVALON_UART_INIT ( DEBUG_UART, debug_uart);
+ 801782c:	01800104 	movi	r6,4
+ 8017830:	000b883a 	mov	r5,zero
+ 8017834:	01020174 	movhi	r4,2053
+ 8017838:	21311204 	addi	r4,r4,-15288
+ 801783c:	801cb500 	call	801cb50 <altera_avalon_uart_init>
+ 8017840:	01020174 	movhi	r4,2053
+ 8017844:	21310804 	addi	r4,r4,-15328
+ 8017848:	80177940 	call	8017794 <alt_dev_reg>
+    ALTERA_ETH_TSE_INIT ( ETH_TSE, eth_tse);
+ 801784c:	e03fff15 	stw	zero,-4(fp)
+ 8017850:	00800044 	movi	r2,1
+ 8017854:	e0bffe15 	stw	r2,-8(fp)
+ 8017858:	e0bffe17 	ldw	r2,-8(fp)
+ 801785c:	00800216 	blt	zero,r2,8017868 <alt_sys_init+0x68>
+ 8017860:	00800044 	movi	r2,1
+ 8017864:	e0bffe15 	stw	r2,-8(fp)
+ 8017868:	e03fff15 	stw	zero,-4(fp)
+ 801786c:	00004e06 	br	80179a8 <alt_sys_init+0x1a8>
+ 8017870:	e0bfff17 	ldw	r2,-4(fp)
+ 8017874:	10c00724 	muli	r3,r2,28
+ 8017878:	008201b4 	movhi	r2,2054
+ 801787c:	1885883a 	add	r2,r3,r2
+ 8017880:	10357215 	stw	zero,-10808(r2)
+ 8017884:	e0bfff17 	ldw	r2,-4(fp)
+ 8017888:	10c00724 	muli	r3,r2,28
+ 801788c:	008201b4 	movhi	r2,2054
+ 8017890:	1885883a 	add	r2,r3,r2
+ 8017894:	10357315 	stw	zero,-10804(r2)
+ 8017898:	d0e00917 	ldw	r3,-32732(gp)
+ 801789c:	e0bfff17 	ldw	r2,-4(fp)
+ 80178a0:	11000724 	muli	r4,r2,28
+ 80178a4:	008201b4 	movhi	r2,2054
+ 80178a8:	2085883a 	add	r2,r4,r2
+ 80178ac:	10f57415 	stw	r3,-10800(r2)
+ 80178b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80178b4:	11000724 	muli	r4,r2,28
+ 80178b8:	00c200b4 	movhi	r3,2050
+ 80178bc:	18c43604 	addi	r3,r3,4312
+ 80178c0:	008201b4 	movhi	r2,2054
+ 80178c4:	2085883a 	add	r2,r4,r2
+ 80178c8:	10f57515 	stw	r3,-10796(r2)
+ 80178cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80178d0:	10c00724 	muli	r3,r2,28
+ 80178d4:	008201b4 	movhi	r2,2054
+ 80178d8:	10b57204 	addi	r2,r2,-10808
+ 80178dc:	1885883a 	add	r2,r3,r2
+ 80178e0:	d0e00f04 	addi	r3,gp,-32708
+ 80178e4:	e0fffd15 	stw	r3,-12(fp)
+ 80178e8:	e0bffc15 	stw	r2,-16(fp)
+ */
+
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, 
+                alt_llist* entry)
+{
+  entry->previous = list;
+ 80178ec:	e0bffc17 	ldw	r2,-16(fp)
+ 80178f0:	e0fffd17 	ldw	r3,-12(fp)
+ 80178f4:	10c00115 	stw	r3,4(r2)
+  entry->next     = list->next;
+ 80178f8:	e0bffd17 	ldw	r2,-12(fp)
+ 80178fc:	10c00017 	ldw	r3,0(r2)
+ 8017900:	e0bffc17 	ldw	r2,-16(fp)
+ 8017904:	10c00015 	stw	r3,0(r2)
+
+  list->next->previous = entry;
+ 8017908:	e0bffd17 	ldw	r2,-12(fp)
+ 801790c:	10800017 	ldw	r2,0(r2)
+ 8017910:	e0fffc17 	ldw	r3,-16(fp)
+ 8017914:	10c00115 	stw	r3,4(r2)
+  list->next           = entry;
+ 8017918:	e0bffd17 	ldw	r2,-12(fp)
+ 801791c:	e0fffc17 	ldw	r3,-16(fp)
+ 8017920:	10c00015 	stw	r3,0(r2)
+ 8017924:	d0a05c03 	ldbu	r2,-32400(gp)
+ 8017928:	11003fcc 	andi	r4,r2,255
+ 801792c:	e0bfff17 	ldw	r2,-4(fp)
+ 8017930:	10c00724 	muli	r3,r2,28
+ 8017934:	008201b4 	movhi	r2,2054
+ 8017938:	10b57204 	addi	r2,r2,-10808
+ 801793c:	1887883a 	add	r3,r3,r2
+ 8017940:	21000324 	muli	r4,r4,12
+ 8017944:	008201b4 	movhi	r2,2054
+ 8017948:	2085883a 	add	r2,r4,r2
+ 801794c:	10f5b615 	stw	r3,-10536(r2)
+ 8017950:	d0a05c03 	ldbu	r2,-32400(gp)
+ 8017954:	10803fcc 	andi	r2,r2,255
+ 8017958:	11000324 	muli	r4,r2,12
+ 801795c:	00c61034 	movhi	r3,6208
+ 8017960:	18cc0004 	addi	r3,r3,12288
+ 8017964:	008201b4 	movhi	r2,2054
+ 8017968:	2085883a 	add	r2,r4,r2
+ 801796c:	10f5b715 	stw	r3,-10532(r2)
+ 8017970:	d0a05c03 	ldbu	r2,-32400(gp)
+ 8017974:	10803fcc 	andi	r2,r2,255
+ 8017978:	e0ffff17 	ldw	r3,-4(fp)
+ 801797c:	1809883a 	mov	r4,r3
+ 8017980:	10c00324 	muli	r3,r2,12
+ 8017984:	008201b4 	movhi	r2,2054
+ 8017988:	1885883a 	add	r2,r3,r2
+ 801798c:	1135b805 	stb	r4,-10528(r2)
+ 8017990:	d0a05c03 	ldbu	r2,-32400(gp)
+ 8017994:	10800044 	addi	r2,r2,1
+ 8017998:	d0a05c05 	stb	r2,-32400(gp)
+ 801799c:	e0bfff17 	ldw	r2,-4(fp)
+ 80179a0:	10800044 	addi	r2,r2,1
+ 80179a4:	e0bfff15 	stw	r2,-4(fp)
+ 80179a8:	e0ffff17 	ldw	r3,-4(fp)
+ 80179ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80179b0:	18bfaf16 	blt	r3,r2,8017870 <alt_sys_init+0x70>
+    ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT ( EXT_FLASH, ext_flash);
+ 80179b4:	01020174 	movhi	r4,2053
+ 80179b8:	21313c04 	addi	r4,r4,-15120
+ 80179bc:	801dd200 	call	801dd20 <altera_qspi_controller_init>
+    ALTERA_MSGDMA_INIT ( MSGDMA_RX, msgdma_rx);
+ 80179c0:	00820174 	movhi	r2,2053
+ 80179c4:	10f17b17 	ldw	r3,-14868(r2)
+ 80179c8:	00820174 	movhi	r2,2053
+ 80179cc:	10b17c17 	ldw	r2,-14864(r2)
+ 80179d0:	100d883a 	mov	r6,r2
+ 80179d4:	180b883a 	mov	r5,r3
+ 80179d8:	01020174 	movhi	r4,2053
+ 80179dc:	21317404 	addi	r4,r4,-14896
+ 80179e0:	801feec0 	call	801feec <alt_msgdma_init>
+    ALTERA_MSGDMA_INIT ( MSGDMA_TX, msgdma_tx);
+ 80179e4:	00820174 	movhi	r2,2053
+ 80179e8:	10f19717 	ldw	r3,-14756(r2)
+ 80179ec:	00820174 	movhi	r2,2053
+ 80179f0:	10b19817 	ldw	r2,-14752(r2)
+ 80179f4:	100d883a 	mov	r6,r2
+ 80179f8:	180b883a 	mov	r5,r3
+ 80179fc:	01020174 	movhi	r4,2053
+ 8017a00:	21319004 	addi	r4,r4,-14784
+ 8017a04:	801feec0 	call	801feec <alt_msgdma_init>
+    ALTERA_ONCHIP_FLASH_INIT ( ONCHIP_FLASH, onchip_flash);
+ 8017a08:	01020174 	movhi	r4,2053
+ 8017a0c:	2131ac04 	addi	r4,r4,-14672
+ 8017a10:	8020a800 	call	8020a80 <altera_onchip_flash_init>
+}
+ 8017a14:	0001883a 	nop
+ 8017a18:	e037883a 	mov	sp,fp
+ 8017a1c:	dfc00117 	ldw	ra,4(sp)
+ 8017a20:	df000017 	ldw	fp,0(sp)
+ 8017a24:	dec00204 	addi	sp,sp,8
+ 8017a28:	f800283a 	ret
+
+08017a2c <alt_avalon_timer_sc_irq>:
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void alt_avalon_timer_sc_irq (void* base)
+#else
+static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
+#endif
+{
+ 8017a2c:	defffa04 	addi	sp,sp,-24
+ 8017a30:	dfc00515 	stw	ra,20(sp)
+ 8017a34:	df000415 	stw	fp,16(sp)
+ 8017a38:	df000404 	addi	fp,sp,16
+ 8017a3c:	e13ffc15 	stw	r4,-16(fp)
+  alt_irq_context cpu_sr;
+  
+  /* clear the interrupt */
+  IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
+ 8017a40:	0007883a 	mov	r3,zero
+ 8017a44:	e0bffc17 	ldw	r2,-16(fp)
+ 8017a48:	10c00035 	stwio	r3,0(r2)
+  /* 
+   * Dummy read to ensure IRQ is negated before the ISR returns.
+   * The control register is read because reading the status
+   * register has side-effects per the register map documentation.
+   */
+  IORD_ALTERA_AVALON_TIMER_CONTROL (base);
+ 8017a4c:	e0bffc17 	ldw	r2,-16(fp)
+ 8017a50:	10800104 	addi	r2,r2,4
+ 8017a54:	10800037 	ldwio	r2,0(r2)
+  NIOS2_READ_STATUS (context);
+ 8017a58:	0005303a 	rdctl	r2,status
+ 8017a5c:	e0bffd15 	stw	r2,-12(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8017a60:	e0fffd17 	ldw	r3,-12(fp)
+ 8017a64:	00bfff84 	movi	r2,-2
+ 8017a68:	1884703a 	and	r2,r3,r2
+ 8017a6c:	1001703a 	wrctl	status,r2
+  return context;
+ 8017a70:	e0bffd17 	ldw	r2,-12(fp)
+
+  /* 
+   * Notify the system of a clock tick. disable interrupts 
+   * during this time to safely support ISR preemption
+   */
+  cpu_sr = alt_irq_disable_all();
+ 8017a74:	e0bfff15 	stw	r2,-4(fp)
+  alt_tick ();
+ 8017a78:	8037f580 	call	8037f58 <alt_tick>
+ 8017a7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8017a80:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8017a84:	e0bffe17 	ldw	r2,-8(fp)
+ 8017a88:	1001703a 	wrctl	status,r2
+  alt_irq_enable_all(cpu_sr);
+}
+ 8017a8c:	0001883a 	nop
+ 8017a90:	e037883a 	mov	sp,fp
+ 8017a94:	dfc00117 	ldw	ra,4(sp)
+ 8017a98:	df000017 	ldw	fp,0(sp)
+ 8017a9c:	dec00204 	addi	sp,sp,8
+ 8017aa0:	f800283a 	ret
+
+08017aa4 <alt_avalon_timer_sc_init>:
+ * auto-generated alt_sys_init() function.
+ */
+
+void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, 
+                                alt_u32 irq, alt_u32 freq)
+{
+ 8017aa4:	defff804 	addi	sp,sp,-32
+ 8017aa8:	dfc00715 	stw	ra,28(sp)
+ 8017aac:	df000615 	stw	fp,24(sp)
+ 8017ab0:	df000604 	addi	fp,sp,24
+ 8017ab4:	e13ffe15 	stw	r4,-8(fp)
+ 8017ab8:	e17ffd15 	stw	r5,-12(fp)
+ 8017abc:	e1bffc15 	stw	r6,-16(fp)
+ 8017ac0:	e1fffb15 	stw	r7,-20(fp)
+ 8017ac4:	e0bffb17 	ldw	r2,-20(fp)
+ 8017ac8:	e0bfff15 	stw	r2,-4(fp)
+ * in order to initialise the value of the clock frequency.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks)
+{
+  if (! _alt_tick_rate)
+ 8017acc:	d0a08d17 	ldw	r2,-32204(gp)
+ 8017ad0:	1000021e 	bne	r2,zero,8017adc <alt_avalon_timer_sc_init+0x38>
+  {
+    _alt_tick_rate = nticks;
+ 8017ad4:	e0bfff17 	ldw	r2,-4(fp)
+ 8017ad8:	d0a08d15 	stw	r2,-32204(gp)
+  
+  alt_sysclk_init (freq);
+  
+  /* set to free running mode */
+  
+  IOWR_ALTERA_AVALON_TIMER_CONTROL (base, 
+ 8017adc:	e0bffe17 	ldw	r2,-8(fp)
+ 8017ae0:	10800104 	addi	r2,r2,4
+ 8017ae4:	00c001c4 	movi	r3,7
+ 8017ae8:	10c00035 	stwio	r3,0(r2)
+            ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
+            ALTERA_AVALON_TIMER_CONTROL_START_MSK);
+
+  /* register the interrupt handler, and enable the interrupt */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, 
+ 8017aec:	d8000015 	stw	zero,0(sp)
+ 8017af0:	e1fffe17 	ldw	r7,-8(fp)
+ 8017af4:	01820074 	movhi	r6,2049
+ 8017af8:	319e8b04 	addi	r6,r6,31276
+ 8017afc:	e17ffc17 	ldw	r5,-16(fp)
+ 8017b00:	e13ffd17 	ldw	r4,-12(fp)
+ 8017b04:	80374940 	call	8037494 <alt_ic_isr_register>
+                      base, NULL);
+#else
+  alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
+#endif  
+}
+ 8017b08:	0001883a 	nop
+ 8017b0c:	e037883a 	mov	sp,fp
+ 8017b10:	dfc00117 	ldw	ra,4(sp)
+ 8017b14:	df000017 	ldw	fp,0(sp)
+ 8017b18:	dec00204 	addi	sp,sp,8
+ 8017b1c:	f800283a 	ret
+
+08017b20 <no_printf>:
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+void no_printf (char *fmt, ...) {}
+ 8017b20:	defffb04 	addi	sp,sp,-20
+ 8017b24:	df000115 	stw	fp,4(sp)
+ 8017b28:	df000104 	addi	fp,sp,4
+ 8017b2c:	e13fff15 	stw	r4,-4(fp)
+ 8017b30:	e1400115 	stw	r5,4(fp)
+ 8017b34:	e1800215 	stw	r6,8(fp)
+ 8017b38:	e1c00315 	stw	r7,12(fp)
+ 8017b3c:	0001883a 	nop
+ 8017b40:	e037883a 	mov	sp,fp
+ 8017b44:	df000017 	ldw	fp,0(sp)
+ 8017b48:	dec00404 	addi	sp,sp,16
+ 8017b4c:	f800283a 	ret
+
+08017b50 <tse_mac_initTransInfo2>:
+
+alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi,
+                                        alt_u32 mac_base,
+                                        alt_32 tx_msgdma,
+                                        alt_32 rx_msgdma,
+                                        alt_32 cfgflags) {
+ 8017b50:	defffb04 	addi	sp,sp,-20
+ 8017b54:	df000415 	stw	fp,16(sp)
+ 8017b58:	df000404 	addi	fp,sp,16
+ 8017b5c:	e13fff15 	stw	r4,-4(fp)
+ 8017b60:	e17ffe15 	stw	r5,-8(fp)
+ 8017b64:	e1bffd15 	stw	r6,-12(fp)
+ 8017b68:	e1fffc15 	stw	r7,-16(fp)
+                                              
+        mi->base     = (np_tse_mac*)mac_base;
+ 8017b6c:	e0fffe17 	ldw	r3,-8(fp)
+ 8017b70:	e0bfff17 	ldw	r2,-4(fp)
+ 8017b74:	10c00015 	stw	r3,0(r2)
+        mi->tx_msgdma = (alt_msgdma_dev *)tx_msgdma;
+ 8017b78:	e0fffd17 	ldw	r3,-12(fp)
+ 8017b7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8017b80:	10c00115 	stw	r3,4(r2)
+        mi->rx_msgdma = (alt_msgdma_dev *)rx_msgdma;
+ 8017b84:	e0fffc17 	ldw	r3,-16(fp)
+ 8017b88:	e0bfff17 	ldw	r2,-4(fp)
+ 8017b8c:	10c00215 	stw	r3,8(r2)
+        mi->cfgflags = cfgflags;     
+ 8017b90:	e0c00117 	ldw	r3,4(fp)
+ 8017b94:	e0bfff17 	ldw	r2,-4(fp)
+ 8017b98:	10c00415 	stw	r3,16(r2)
+        return SUCCESS;
+ 8017b9c:	0005883a 	mov	r2,zero
+}
+ 8017ba0:	e037883a 	mov	sp,fp
+ 8017ba4:	df000017 	ldw	fp,0(sp)
+ 8017ba8:	dec00104 	addi	sp,sp,4
+ 8017bac:	f800283a 	ret
+
+08017bb0 <tse_mac_sTxWrite>:
+  * @param txDesc           Pointer to the transmit MSGDMA descriptor
+  * @return actual bytes transferred if ok, else error (-1)
+  */
+alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, 
+                       alt_msgdma_standard_descriptor *txDesc)   
+{ 
+ 8017bb0:	defffa04 	addi	sp,sp,-24
+ 8017bb4:	dfc00515 	stw	ra,20(sp)
+ 8017bb8:	df000415 	stw	fp,16(sp)
+ 8017bbc:	df000404 	addi	fp,sp,16
+ 8017bc0:	e13ffd15 	stw	r4,-12(fp)
+ 8017bc4:	e17ffc15 	stw	r5,-16(fp)
+
+  alt_32 timeout;
+  alt_u8 result = 0;
+ 8017bc8:	e03ffec5 	stb	zero,-5(fp)
+  
+  // Make sure DMA controller is not busy from a former command
+  // and TX is able to accept data
+  timeout = 0;
+ 8017bcc:	e03fff15 	stw	zero,-4(fp)
+  while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & 
+ 8017bd0:	00000b06 	br	8017c00 <tse_mac_sTxWrite+0x50>
+           ALTERA_MSGDMA_CSR_BUSY_MASK) ) {
+           if(timeout++ == ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT) {
+ 8017bd4:	e0ffff17 	ldw	r3,-4(fp)
+ 8017bd8:	18800044 	addi	r2,r3,1
+ 8017bdc:	e0bfff15 	stw	r2,-4(fp)
+ 8017be0:	008003f4 	movhi	r2,15
+ 8017be4:	10909004 	addi	r2,r2,16960
+ 8017be8:	1880051e 	bne	r3,r2,8017c00 <tse_mac_sTxWrite+0x50>
+            tse_dprintf(4, "WARNING : TX MSGDMA Timeout\n");
+ 8017bec:	01020134 	movhi	r4,2052
+ 8017bf0:	211e3404 	addi	r4,r4,30928
+ 8017bf4:	8002d9c0 	call	8002d9c <puts>
+            return ENP_RESOURCE;  // avoid being stuck here
+ 8017bf8:	00bffa84 	movi	r2,-22
+ 8017bfc:	00001906 	br	8017c64 <tse_mac_sTxWrite+0xb4>
+  while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & 
+ 8017c00:	e0bffd17 	ldw	r2,-12(fp)
+ 8017c04:	10800117 	ldw	r2,4(r2)
+ 8017c08:	10800317 	ldw	r2,12(r2)
+ 8017c0c:	10800037 	ldwio	r2,0(r2)
+ 8017c10:	1080004c 	andi	r2,r2,1
+ 8017c14:	103fef1e 	bne	r2,zero,8017bd4 <tse_mac_sTxWrite+0x24>
+           }
+  }
+  
+  // Start MSGDMA (blocking call)
+  alt_dcache_flush(txDesc,sizeof(alt_msgdma_standard_descriptor));
+ 8017c18:	01400404 	movi	r5,16
+ 8017c1c:	e13ffc17 	ldw	r4,-16(fp)
+ 8017c20:	80371c00 	call	80371c0 <alt_dcache_flush>
+  result = alt_msgdma_standard_descriptor_sync_transfer(
+ 8017c24:	e0bffd17 	ldw	r2,-12(fp)
+ 8017c28:	10800117 	ldw	r2,4(r2)
+ 8017c2c:	e17ffc17 	ldw	r5,-16(fp)
+ 8017c30:	1009883a 	mov	r4,r2
+ 8017c34:	80201600 	call	8020160 <alt_msgdma_standard_descriptor_sync_transfer>
+ 8017c38:	e0bffec5 	stb	r2,-5(fp)
+                mi->tx_msgdma, 
+                txDesc);
+  
+  if (result != 0) {
+ 8017c3c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8017c40:	10000726 	beq	r2,zero,8017c60 <tse_mac_sTxWrite+0xb0>
+    tse_dprintf(4, "WARNING :alt_msgdma_standard_descriptor_sync_transfer Error code 0x%x\n",result);
+ 8017c44:	e0bffec3 	ldbu	r2,-5(fp)
+ 8017c48:	100b883a 	mov	r5,r2
+ 8017c4c:	01020134 	movhi	r4,2052
+ 8017c50:	211e3b04 	addi	r4,r4,30956
+ 8017c54:	8002c780 	call	8002c78 <printf>
+    return -1;
+ 8017c58:	00bfffc4 	movi	r2,-1
+ 8017c5c:	00000106 	br	8017c64 <tse_mac_sTxWrite+0xb4>
+  }
+
+  return 0;
+ 8017c60:	0005883a 	mov	r2,zero
+}
+ 8017c64:	e037883a 	mov	sp,fp
+ 8017c68:	dfc00117 	ldw	ra,4(sp)
+ 8017c6c:	df000017 	ldw	fp,0(sp)
+ 8017c70:	dec00204 	addi	sp,sp,8
+ 8017c74:	f800283a 	ret
+
+08017c78 <tse_mac_aRxRead>:
+  *        the actual bytes transferred for current descriptor
+  */
+alt_32 tse_mac_aRxRead( 
+  tse_mac_trans_info *mi,       
+  alt_msgdma_prefetcher_standard_descriptor *rxDesc)  
+{
+ 8017c78:	defff904 	addi	sp,sp,-28
+ 8017c7c:	dfc00615 	stw	ra,24(sp)
+ 8017c80:	df000515 	stw	fp,20(sp)
+ 8017c84:	df000504 	addi	fp,sp,20
+ 8017c88:	e13ffe15 	stw	r4,-8(fp)
+ 8017c8c:	e17ffd15 	stw	r5,-12(fp)
+  alt_u8 result;
+           
+  result = alt_msgdma_start_prefetcher_with_std_desc_list(
+ 8017c90:	e0bffe17 	ldw	r2,-8(fp)
+ 8017c94:	10c00217 	ldw	r3,8(r2)
+ 8017c98:	00800044 	movi	r2,1
+ 8017c9c:	d8800115 	stw	r2,4(sp)
+ 8017ca0:	00800044 	movi	r2,1
+ 8017ca4:	d8800015 	stw	r2,0(sp)
+ 8017ca8:	000f883a 	mov	r7,zero
+ 8017cac:	000d883a 	mov	r6,zero
+ 8017cb0:	e17ffd17 	ldw	r5,-12(fp)
+ 8017cb4:	1809883a 	mov	r4,r3
+ 8017cb8:	801fd340 	call	801fd34 <alt_msgdma_start_prefetcher_with_std_desc_list>
+ 8017cbc:	e0bfffc5 	stb	r2,-1(fp)
+                mi->rx_msgdma, 
+                rxDesc,0,0,1,1);
+  
+  if (result != 0) { return -1; }
+ 8017cc0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8017cc4:	10000226 	beq	r2,zero,8017cd0 <tse_mac_aRxRead+0x58>
+ 8017cc8:	00bfffc4 	movi	r2,-1
+ 8017ccc:	00000106 	br	8017cd4 <tse_mac_aRxRead+0x5c>
+ 
+  return SUCCESS;
+ 8017cd0:	0005883a 	mov	r2,zero
+}
+ 8017cd4:	e037883a 	mov	sp,fp
+ 8017cd8:	dfc00117 	ldw	ra,4(sp)
+ 8017cdc:	df000017 	ldw	fp,0(sp)
+ 8017ce0:	dec00204 	addi	sp,sp,8
+ 8017ce4:	f800283a 	ret
+
+08017ce8 <tse_mac_aTxWrite>:
+  *
+  */
+alt_32 tse_mac_aTxWrite( 
+  tse_mac_trans_info *mi,       
+  alt_msgdma_prefetcher_standard_descriptor *txDesc)  
+{
+ 8017ce8:	defff904 	addi	sp,sp,-28
+ 8017cec:	dfc00615 	stw	ra,24(sp)
+ 8017cf0:	df000515 	stw	fp,20(sp)
+ 8017cf4:	df000504 	addi	fp,sp,20
+ 8017cf8:	e13ffe15 	stw	r4,-8(fp)
+ 8017cfc:	e17ffd15 	stw	r5,-12(fp)
+  alt_u8 result;
+  
+  result = alt_msgdma_start_prefetcher_with_std_desc_list(
+ 8017d00:	e0bffe17 	ldw	r2,-8(fp)
+ 8017d04:	10c00117 	ldw	r3,4(r2)
+ 8017d08:	00800044 	movi	r2,1
+ 8017d0c:	d8800115 	stw	r2,4(sp)
+ 8017d10:	00800044 	movi	r2,1
+ 8017d14:	d8800015 	stw	r2,0(sp)
+ 8017d18:	000f883a 	mov	r7,zero
+ 8017d1c:	000d883a 	mov	r6,zero
+ 8017d20:	e17ffd17 	ldw	r5,-12(fp)
+ 8017d24:	1809883a 	mov	r4,r3
+ 8017d28:	801fd340 	call	801fd34 <alt_msgdma_start_prefetcher_with_std_desc_list>
+ 8017d2c:	e0bfffc5 	stb	r2,-1(fp)
+                mi->tx_msgdma, 
+                txDesc,0,0,1,1);
+
+  if (result != 0) { return -1; }
+ 8017d30:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8017d34:	10000226 	beq	r2,zero,8017d40 <tse_mac_aTxWrite+0x58>
+ 8017d38:	00bfffc4 	movi	r2,-1
+ 8017d3c:	00000106 	br	8017d44 <tse_mac_aTxWrite+0x5c>
+ 
+  return SUCCESS;
+ 8017d40:	0005883a 	mov	r2,zero
+}
+ 8017d44:	e037883a 	mov	sp,fp
+ 8017d48:	dfc00117 	ldw	ra,4(sp)
+ 8017d4c:	df000017 	ldw	fp,0(sp)
+ 8017d50:	dec00204 	addi	sp,sp,8
+ 8017d54:	f800283a 	ret
+
+08017d58 <tse_mac_SwReset>:
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+*/
+alt_32 tse_mac_SwReset(np_tse_mac *pmac) 
+{
+ 8017d58:	defffc04 	addi	sp,sp,-16
+ 8017d5c:	df000315 	stw	fp,12(sp)
+ 8017d60:	df000304 	addi	fp,sp,12
+ 8017d64:	e13ffd15 	stw	r4,-12(fp)
+    alt_32 timeout;
+    alt_32 cc;
+        
+    cc = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+ 8017d68:	e0bffd17 	ldw	r2,-12(fp)
+ 8017d6c:	10800204 	addi	r2,r2,8
+ 8017d70:	10800037 	ldwio	r2,0(r2)
+ 8017d74:	e0bffe15 	stw	r2,-8(fp)
+    
+    // set reset and Gig-Speed bits to make sure we have an incoming clock on
+    // tx side. If there is a 10/100 PHY, we will still have a valid clock on
+    // tx_clk no matter what setting we have here, but on a Gig phy the
+    // MII clock may be missing.
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,(ALTERA_TSEMAC_CMD_SW_RESET_MSK | ALTERA_TSEMAC_CMD_ETH_SPEED_MSK));
+ 8017d78:	e0bffd17 	ldw	r2,-12(fp)
+ 8017d7c:	10800204 	addi	r2,r2,8
+ 8017d80:	00c80204 	movi	r3,8200
+ 8017d84:	10c00035 	stwio	r3,0(r2)
+
+    
+    // wait for completion with fallback in case there is no PHY or it is
+    // not connected and hence might not provide any clocks at all.
+    timeout=0;
+ 8017d88:	e03fff15 	stw	zero,-4(fp)
+    while( (IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac) & ALTERA_TSEMAC_CMD_SW_RESET_MSK) != 0 && timeout < ALTERA_TSE_SW_RESET_TIME_OUT_CNT) timeout++;
+ 8017d8c:	00000306 	br	8017d9c <tse_mac_SwReset+0x44>
+ 8017d90:	e0bfff17 	ldw	r2,-4(fp)
+ 8017d94:	10800044 	addi	r2,r2,1
+ 8017d98:	e0bfff15 	stw	r2,-4(fp)
+ 8017d9c:	e0bffd17 	ldw	r2,-12(fp)
+ 8017da0:	10800204 	addi	r2,r2,8
+ 8017da4:	10800037 	ldwio	r2,0(r2)
+ 8017da8:	1088000c 	andi	r2,r2,8192
+ 8017dac:	10000326 	beq	r2,zero,8017dbc <tse_mac_SwReset+0x64>
+ 8017db0:	e0bfff17 	ldw	r2,-4(fp)
+ 8017db4:	1089c410 	cmplti	r2,r2,10000
+ 8017db8:	103ff51e 	bne	r2,zero,8017d90 <tse_mac_SwReset+0x38>
+   
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,cc); // Restore
+ 8017dbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8017dc0:	10800204 	addi	r2,r2,8
+ 8017dc4:	e0fffe17 	ldw	r3,-8(fp)
+ 8017dc8:	10c00035 	stwio	r3,0(r2)
+    return SUCCESS;
+ 8017dcc:	0005883a 	mov	r2,zero
+}
+ 8017dd0:	e037883a 	mov	sp,fp
+ 8017dd4:	df000017 	ldw	fp,0(sp)
+ 8017dd8:	dec00104 	addi	sp,sp,4
+ 8017ddc:	f800283a 	ret
+
+08017de0 <tse_mac_setMIImode>:
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+*/
+alt_32 tse_mac_setMIImode(np_tse_mac *pmac)
+{
+ 8017de0:	defffd04 	addi	sp,sp,-12
+ 8017de4:	df000215 	stw	fp,8(sp)
+ 8017de8:	df000204 	addi	fp,sp,8
+ 8017dec:	e13ffe15 	stw	r4,-8(fp)
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+ 8017df0:	e0bffe17 	ldw	r2,-8(fp)
+ 8017df4:	10800204 	addi	r2,r2,8
+ 8017df8:	10800037 	ldwio	r2,0(r2)
+ 8017dfc:	e0bfff15 	stw	r2,-4(fp)
+  helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; 
+ 8017e00:	e0ffff17 	ldw	r3,-4(fp)
+ 8017e04:	00bffdc4 	movi	r2,-9
+ 8017e08:	1884703a 	and	r2,r3,r2
+ 8017e0c:	e0bfff15 	stw	r2,-4(fp)
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar);
+ 8017e10:	e0bffe17 	ldw	r2,-8(fp)
+ 8017e14:	10800204 	addi	r2,r2,8
+ 8017e18:	e0ffff17 	ldw	r3,-4(fp)
+ 8017e1c:	10c00035 	stwio	r3,0(r2)
+  return SUCCESS;
+ 8017e20:	0005883a 	mov	r2,zero
+}
+ 8017e24:	e037883a 	mov	sp,fp
+ 8017e28:	df000017 	ldw	fp,0(sp)
+ 8017e2c:	dec00104 	addi	sp,sp,4
+ 8017e30:	f800283a 	ret
+
+08017e34 <tse_mac_setGMIImode>:
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+ */
+alt_32 tse_mac_setGMIImode(np_tse_mac *pmac)
+{
+ 8017e34:	defffd04 	addi	sp,sp,-12
+ 8017e38:	df000215 	stw	fp,8(sp)
+ 8017e3c:	df000204 	addi	fp,sp,8
+ 8017e40:	e13ffe15 	stw	r4,-8(fp)
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+ 8017e44:	e0bffe17 	ldw	r2,-8(fp)
+ 8017e48:	10800204 	addi	r2,r2,8
+ 8017e4c:	10800037 	ldwio	r2,0(r2)
+ 8017e50:	e0bfff15 	stw	r2,-4(fp)
+  helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8017e54:	e0bfff17 	ldw	r2,-4(fp)
+ 8017e58:	10800214 	ori	r2,r2,8
+ 8017e5c:	e0bfff15 	stw	r2,-4(fp)
+
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar);
+ 8017e60:	e0bffe17 	ldw	r2,-8(fp)
+ 8017e64:	10800204 	addi	r2,r2,8
+ 8017e68:	e0ffff17 	ldw	r3,-4(fp)
+ 8017e6c:	10c00035 	stwio	r3,0(r2)
+  return SUCCESS;
+ 8017e70:	0005883a 	mov	r2,zero
+}
+ 8017e74:	e037883a 	mov	sp,fp
+ 8017e78:	df000017 	ldw	fp,0(sp)
+ 8017e7c:	dec00104 	addi	sp,sp,4
+ 8017e80:	f800283a 	ret
+
+08017e84 <alt_tse_phy_add_profile>:
+ * @param  phy  pointer to alt_tse_phy_profile structure describing PHY registers
+ * @return      index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ * PHY which are currently supported by default :  Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C
+ */
+alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy)
+{
+ 8017e84:	defffb04 	addi	sp,sp,-20
+ 8017e88:	dfc00415 	stw	ra,16(sp)
+ 8017e8c:	df000315 	stw	fp,12(sp)
+ 8017e90:	dc000215 	stw	r16,8(sp)
+ 8017e94:	df000304 	addi	fp,sp,12
+ 8017e98:	e13ffd15 	stw	r4,-12(fp)
+    alt_32 i;
+    
+    /* search PHY profile for same ID */
+    for(i = 0; i < phy_profile_count; i++)
+ 8017e9c:	e03ffe15 	stw	zero,-8(fp)
+ 8017ea0:	00002506 	br	8017f38 <alt_tse_phy_add_profile+0xb4>
+    {
+        if(pphy_profiles[i]->oui == phy->oui && pphy_profiles[i]->model_number == phy->model_number)
+ 8017ea4:	e0bffe17 	ldw	r2,-8(fp)
+ 8017ea8:	100690ba 	slli	r3,r2,2
+ 8017eac:	008201b4 	movhi	r2,2054
+ 8017eb0:	1885883a 	add	r2,r3,r2
+ 8017eb4:	10b5ae17 	ldw	r2,-10568(r2)
+ 8017eb8:	10c01417 	ldw	r3,80(r2)
+ 8017ebc:	e0bffd17 	ldw	r2,-12(fp)
+ 8017ec0:	10801417 	ldw	r2,80(r2)
+ 8017ec4:	1880191e 	bne	r3,r2,8017f2c <alt_tse_phy_add_profile+0xa8>
+ 8017ec8:	e0bffe17 	ldw	r2,-8(fp)
+ 8017ecc:	100690ba 	slli	r3,r2,2
+ 8017ed0:	008201b4 	movhi	r2,2054
+ 8017ed4:	1885883a 	add	r2,r3,r2
+ 8017ed8:	10b5ae17 	ldw	r2,-10568(r2)
+ 8017edc:	10c01503 	ldbu	r3,84(r2)
+ 8017ee0:	e0bffd17 	ldw	r2,-12(fp)
+ 8017ee4:	10801503 	ldbu	r2,84(r2)
+ 8017ee8:	18c03fcc 	andi	r3,r3,255
+ 8017eec:	10803fcc 	andi	r2,r2,255
+ 8017ef0:	18800e1e 	bne	r3,r2,8017f2c <alt_tse_phy_add_profile+0xa8>
+        {
+            tse_dprintf(4, "WARNING : PHY OUI 0x%06x, PHY Model Number 0x%02x already exist in PHY profile\n", (int) phy->oui, phy->model_number);
+ 8017ef4:	e0bffd17 	ldw	r2,-12(fp)
+ 8017ef8:	10801417 	ldw	r2,80(r2)
+ 8017efc:	1007883a 	mov	r3,r2
+ 8017f00:	e0bffd17 	ldw	r2,-12(fp)
+ 8017f04:	10801503 	ldbu	r2,84(r2)
+ 8017f08:	10803fcc 	andi	r2,r2,255
+ 8017f0c:	100d883a 	mov	r6,r2
+ 8017f10:	180b883a 	mov	r5,r3
+ 8017f14:	01020134 	movhi	r4,2052
+ 8017f18:	211e4d04 	addi	r4,r4,31028
+ 8017f1c:	8002c780 	call	8002c78 <printf>
+            tse_dprintf(4, "In case of same PHY OUI and PHY Model Number in profile, first added PHY setting will be used\n");
+ 8017f20:	01020134 	movhi	r4,2052
+ 8017f24:	211e6104 	addi	r4,r4,31108
+ 8017f28:	8002d9c0 	call	8002d9c <puts>
+    for(i = 0; i < phy_profile_count; i++)
+ 8017f2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8017f30:	10800044 	addi	r2,r2,1
+ 8017f34:	e0bffe15 	stw	r2,-8(fp)
+ 8017f38:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017f3c:	10803fcc 	andi	r2,r2,255
+ 8017f40:	e0fffe17 	ldw	r3,-8(fp)
+ 8017f44:	18bfd716 	blt	r3,r2,8017ea4 <alt_tse_phy_add_profile+0x20>
+        }
+    }
+
+    /* Allocate memory space to store the profile */    
+    pphy_profiles[phy_profile_count] = (alt_tse_phy_profile *) malloc(sizeof(alt_tse_phy_profile));
+ 8017f48:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017f4c:	14003fcc 	andi	r16,r2,255
+ 8017f50:	01001904 	movi	r4,100
+ 8017f54:	8042c980 	call	8042c98 <malloc>
+ 8017f58:	1009883a 	mov	r4,r2
+ 8017f5c:	800690ba 	slli	r3,r16,2
+ 8017f60:	008201b4 	movhi	r2,2054
+ 8017f64:	1885883a 	add	r2,r3,r2
+ 8017f68:	1135ae15 	stw	r4,-10568(r2)
+    if(!pphy_profiles[phy_profile_count]) {
+ 8017f6c:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017f70:	10803fcc 	andi	r2,r2,255
+ 8017f74:	100690ba 	slli	r3,r2,2
+ 8017f78:	008201b4 	movhi	r2,2054
+ 8017f7c:	1885883a 	add	r2,r3,r2
+ 8017f80:	10b5ae17 	ldw	r2,-10568(r2)
+ 8017f84:	1000081e 	bne	r2,zero,8017fa8 <alt_tse_phy_add_profile+0x124>
+        tse_dprintf(1, "ERROR   : Unable to allocate memory for pphy_profile[%d]\n", phy_profile_count);
+ 8017f88:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017f8c:	10803fcc 	andi	r2,r2,255
+ 8017f90:	100b883a 	mov	r5,r2
+ 8017f94:	01020134 	movhi	r4,2052
+ 8017f98:	211e7904 	addi	r4,r4,31204
+ 8017f9c:	8002c780 	call	8002c78 <printf>
+        return ALTERA_TSE_MALLOC_FAILED;
+ 8017fa0:	00bfffc4 	movi	r2,-1
+ 8017fa4:	00001e06 	br	8018020 <alt_tse_phy_add_profile+0x19c>
+    }
+
+    /* Store PHY information */
+    *pphy_profiles[phy_profile_count] = *phy;
+ 8017fa8:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017fac:	10803fcc 	andi	r2,r2,255
+ 8017fb0:	100690ba 	slli	r3,r2,2
+ 8017fb4:	008201b4 	movhi	r2,2054
+ 8017fb8:	1885883a 	add	r2,r3,r2
+ 8017fbc:	10f5ae17 	ldw	r3,-10568(r2)
+ 8017fc0:	e0bffd17 	ldw	r2,-12(fp)
+ 8017fc4:	1009883a 	mov	r4,r2
+ 8017fc8:	00801904 	movi	r2,100
+ 8017fcc:	100d883a 	mov	r6,r2
+ 8017fd0:	200b883a 	mov	r5,r4
+ 8017fd4:	1809883a 	mov	r4,r3
+ 8017fd8:	80086b80 	call	80086b8 <memcpy>
+    strcpy(pphy_profiles[phy_profile_count]->name, phy->name);
+ 8017fdc:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8017fe0:	10803fcc 	andi	r2,r2,255
+ 8017fe4:	100690ba 	slli	r3,r2,2
+ 8017fe8:	008201b4 	movhi	r2,2054
+ 8017fec:	1885883a 	add	r2,r3,r2
+ 8017ff0:	10b5ae17 	ldw	r2,-10568(r2)
+ 8017ff4:	1007883a 	mov	r3,r2
+ 8017ff8:	e0bffd17 	ldw	r2,-12(fp)
+ 8017ffc:	100b883a 	mov	r5,r2
+ 8018000:	1809883a 	mov	r4,r3
+ 8018004:	8042f600 	call	8042f60 <strcpy>
+    
+    phy_profile_count++;
+ 8018008:	d0a05b03 	ldbu	r2,-32404(gp)
+ 801800c:	10800044 	addi	r2,r2,1
+ 8018010:	d0a05b05 	stb	r2,-32404(gp)
+    
+    return phy_profile_count - 1;
+ 8018014:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8018018:	10803fcc 	andi	r2,r2,255
+ 801801c:	10bfffc4 	addi	r2,r2,-1
+}
+ 8018020:	e6ffff04 	addi	sp,fp,-4
+ 8018024:	dfc00217 	ldw	ra,8(sp)
+ 8018028:	df000117 	ldw	fp,4(sp)
+ 801802c:	dc000017 	ldw	r16,0(sp)
+ 8018030:	dec00304 	addi	sp,sp,12
+ 8018034:	f800283a 	ret
+
+08018038 <alt_tse_system_add_sys>:
+alt_32 alt_tse_system_add_sys(
+    alt_tse_system_mac                    *psys_mac,
+    alt_tse_system_msgdma                *psys_msgdma,
+    alt_tse_system_desc_mem                *psys_mem,
+    alt_tse_system_shared_fifo            *psys_shared_fifo,
+    alt_tse_system_phy                     *psys_phy ) {
+ 8018038:	defff204 	addi	sp,sp,-56
+ 801803c:	dfc00d15 	stw	ra,52(sp)
+ 8018040:	df000c15 	stw	fp,48(sp)
+ 8018044:	dc000b15 	stw	r16,44(sp)
+ 8018048:	df000c04 	addi	fp,sp,48
+ 801804c:	e13ff715 	stw	r4,-36(fp)
+ 8018050:	e17ff615 	stw	r5,-40(fp)
+ 8018054:	e1bff515 	stw	r6,-44(fp)
+ 8018058:	e1fff415 	stw	r7,-48(fp)
+
+    int i;
+    int loop_end;
+    
+    alt_tse_system_mac                    *pmac    = psys_mac;
+ 801805c:	e0bff717 	ldw	r2,-36(fp)
+ 8018060:	e0bff815 	stw	r2,-32(fp)
+    alt_tse_system_msgdma                *pmsgdma    = psys_msgdma;
+ 8018064:	e0bff617 	ldw	r2,-40(fp)
+ 8018068:	e0bffb15 	stw	r2,-20(fp)
+    alt_tse_system_desc_mem                *pmem    = psys_mem;
+ 801806c:	e0bff517 	ldw	r2,-44(fp)
+ 8018070:	e0bffc15 	stw	r2,-16(fp)
+    alt_tse_system_shared_fifo            *pfifo    = psys_shared_fifo;
+ 8018074:	e0bff417 	ldw	r2,-48(fp)
+ 8018078:	e0bffe15 	stw	r2,-8(fp)
+    alt_tse_system_phy                     *pphy    = psys_phy;
+ 801807c:	e0800217 	ldw	r2,8(fp)
+ 8018080:	e0bffd15 	stw	r2,-12(fp)
+    
+    static alt_8 tse_system_count = 0;
+    
+    /* Determine number of loop */
+    /* Run at least one for non-multi-channel MAC */
+    if(pmac->tse_num_of_channel == 0) {
+ 8018084:	e0bff817 	ldw	r2,-32(fp)
+ 8018088:	10800303 	ldbu	r2,12(r2)
+ 801808c:	10803fcc 	andi	r2,r2,255
+ 8018090:	1000031e 	bne	r2,zero,80180a0 <alt_tse_system_add_sys+0x68>
+        loop_end = 1;
+ 8018094:	00800044 	movi	r2,1
+ 8018098:	e0bff915 	stw	r2,-28(fp)
+ 801809c:	00000e06 	br	80180d8 <alt_tse_system_add_sys+0xa0>
+    }
+    else if(pmac->tse_num_of_channel > 0) {
+ 80180a0:	e0bff817 	ldw	r2,-32(fp)
+ 80180a4:	10800303 	ldbu	r2,12(r2)
+ 80180a8:	10803fcc 	andi	r2,r2,255
+ 80180ac:	10000526 	beq	r2,zero,80180c4 <alt_tse_system_add_sys+0x8c>
+        loop_end = pmac->tse_num_of_channel; 
+ 80180b0:	e0bff817 	ldw	r2,-32(fp)
+ 80180b4:	10800303 	ldbu	r2,12(r2)
+ 80180b8:	10803fcc 	andi	r2,r2,255
+ 80180bc:	e0bff915 	stw	r2,-28(fp)
+ 80180c0:	00000506 	br	80180d8 <alt_tse_system_add_sys+0xa0>
+    }
+    else {
+        tse_dprintf(2, "ERROR   : Invalid number of channel specified!\n");
+ 80180c4:	01020134 	movhi	r4,2052
+ 80180c8:	211e8804 	addi	r4,r4,31264
+ 80180cc:	8002d9c0 	call	8002d9c <puts>
+        return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 80180d0:	00bfffc4 	movi	r2,-1
+ 80180d4:	00020306 	br	80188e4 <alt_tse_system_add_sys+0x8ac>
+    }
+
+    for(i = 0; i < loop_end; i++) {
+ 80180d8:	e03ffa15 	stw	zero,-24(fp)
+ 80180dc:	0001fd06 	br	80188d4 <alt_tse_system_add_sys+0x89c>
+        
+        /* Make sure the boundary of array is not exceeded */
+        if(tse_system_count >= MAXNETS) {
+ 80180e0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80180e4:	10803fcc 	andi	r2,r2,255
+ 80180e8:	1080201c 	xori	r2,r2,128
+ 80180ec:	10bfe004 	addi	r2,r2,-128
+ 80180f0:	10800110 	cmplti	r2,r2,4
+ 80180f4:	10000c1e 	bne	r2,zero,8018128 <alt_tse_system_add_sys+0xf0>
+            tse_dprintf(2, "ERROR   : Number of TSE System added exceed the size of array!\n");
+ 80180f8:	01020134 	movhi	r4,2052
+ 80180fc:	211e9404 	addi	r4,r4,31312
+ 8018100:	8002d9c0 	call	8002d9c <puts>
+            tse_dprintf(2, "ERROR   : Size of array = %d, Number of TSE System = %d\n", MAXNETS, tse_system_count);
+ 8018104:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018108:	10803fcc 	andi	r2,r2,255
+ 801810c:	1080201c 	xori	r2,r2,128
+ 8018110:	10bfe004 	addi	r2,r2,-128
+ 8018114:	100d883a 	mov	r6,r2
+ 8018118:	01400104 	movi	r5,4
+ 801811c:	01020134 	movhi	r4,2052
+ 8018120:	211ea404 	addi	r4,r4,31376
+ 8018124:	8002c780 	call	8002c78 <printf>
+        }
+
+        /* Add MAC info to alt_tse_system_info structure */
+        if(pmac == 0) {
+ 8018128:	e0bff817 	ldw	r2,-32(fp)
+ 801812c:	1000081e 	bne	r2,zero,8018150 <alt_tse_system_add_sys+0x118>
+            tse_dprintf(2, "ERROR   : MAC system structure == NULL\n");
+ 8018130:	01020134 	movhi	r4,2052
+ 8018134:	211eb304 	addi	r4,r4,31436
+ 8018138:	8002d9c0 	call	8002d9c <puts>
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_system_add_sys()\n");
+ 801813c:	01020134 	movhi	r4,2052
+ 8018140:	211ebd04 	addi	r4,r4,31476
+ 8018144:	8002d9c0 	call	8002d9c <puts>
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 8018148:	00bfffc4 	movi	r2,-1
+ 801814c:	0001e506 	br	80188e4 <alt_tse_system_add_sys+0x8ac>
+        }        
+        
+        tse_mac_device[tse_system_count].tse_mac_base                     = pmac->tse_mac_base + (i * 0x400);
+ 8018150:	e0bff817 	ldw	r2,-32(fp)
+ 8018154:	10c00017 	ldw	r3,0(r2)
+ 8018158:	e0bffa17 	ldw	r2,-24(fp)
+ 801815c:	100492ba 	slli	r2,r2,10
+ 8018160:	1009883a 	mov	r4,r2
+ 8018164:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018168:	10803fcc 	andi	r2,r2,255
+ 801816c:	1080201c 	xori	r2,r2,128
+ 8018170:	10bfe004 	addi	r2,r2,-128
+ 8018174:	1907883a 	add	r3,r3,r4
+ 8018178:	11001324 	muli	r4,r2,76
+ 801817c:	00820174 	movhi	r2,2053
+ 8018180:	2085883a 	add	r2,r4,r2
+ 8018184:	10ee5415 	stw	r3,-18096(r2)
+        tse_mac_device[tse_system_count].tse_tx_depth                     = pmac->tse_tx_depth;
+ 8018188:	e0bff817 	ldw	r2,-32(fp)
+ 801818c:	10c0010b 	ldhu	r3,4(r2)
+ 8018190:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018194:	10803fcc 	andi	r2,r2,255
+ 8018198:	1080201c 	xori	r2,r2,128
+ 801819c:	10bfe004 	addi	r2,r2,-128
+ 80181a0:	18ffffcc 	andi	r3,r3,65535
+ 80181a4:	11001324 	muli	r4,r2,76
+ 80181a8:	00820174 	movhi	r2,2053
+ 80181ac:	2085883a 	add	r2,r4,r2
+ 80181b0:	10ee5515 	stw	r3,-18092(r2)
+        tse_mac_device[tse_system_count].tse_rx_depth                     = pmac->tse_rx_depth;
+ 80181b4:	e0bff817 	ldw	r2,-32(fp)
+ 80181b8:	10c0018b 	ldhu	r3,6(r2)
+ 80181bc:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80181c0:	10803fcc 	andi	r2,r2,255
+ 80181c4:	1080201c 	xori	r2,r2,128
+ 80181c8:	10bfe004 	addi	r2,r2,-128
+ 80181cc:	18ffffcc 	andi	r3,r3,65535
+ 80181d0:	11001324 	muli	r4,r2,76
+ 80181d4:	00820174 	movhi	r2,2053
+ 80181d8:	2085883a 	add	r2,r4,r2
+ 80181dc:	10ee5615 	stw	r3,-18088(r2)
+        tse_mac_device[tse_system_count].tse_use_mdio                     = pmac->tse_use_mdio;
+ 80181e0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80181e4:	10803fcc 	andi	r2,r2,255
+ 80181e8:	1080201c 	xori	r2,r2,128
+ 80181ec:	10bfe004 	addi	r2,r2,-128
+ 80181f0:	e0fff817 	ldw	r3,-32(fp)
+ 80181f4:	18c00203 	ldbu	r3,8(r3)
+ 80181f8:	11001324 	muli	r4,r2,76
+ 80181fc:	00820174 	movhi	r2,2053
+ 8018200:	2085883a 	add	r2,r4,r2
+ 8018204:	10ee5705 	stb	r3,-18084(r2)
+        tse_mac_device[tse_system_count].tse_en_maclite                 = pmac->tse_en_maclite;
+ 8018208:	d0a05b83 	ldbu	r2,-32402(gp)
+ 801820c:	10803fcc 	andi	r2,r2,255
+ 8018210:	1080201c 	xori	r2,r2,128
+ 8018214:	10bfe004 	addi	r2,r2,-128
+ 8018218:	e0fff817 	ldw	r3,-32(fp)
+ 801821c:	18c00243 	ldbu	r3,9(r3)
+ 8018220:	11001324 	muli	r4,r2,76
+ 8018224:	00820174 	movhi	r2,2053
+ 8018228:	2085883a 	add	r2,r4,r2
+ 801822c:	10ee5745 	stb	r3,-18083(r2)
+        tse_mac_device[tse_system_count].tse_maclite_gige                 = pmac->tse_maclite_gige;
+ 8018230:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018234:	10803fcc 	andi	r2,r2,255
+ 8018238:	1080201c 	xori	r2,r2,128
+ 801823c:	10bfe004 	addi	r2,r2,-128
+ 8018240:	e0fff817 	ldw	r3,-32(fp)
+ 8018244:	18c00283 	ldbu	r3,10(r3)
+ 8018248:	11001324 	muli	r4,r2,76
+ 801824c:	00820174 	movhi	r2,2053
+ 8018250:	2085883a 	add	r2,r4,r2
+ 8018254:	10ee5785 	stb	r3,-18082(r2)
+        tse_mac_device[tse_system_count].tse_multichannel_mac             = pmac->tse_multichannel_mac;
+ 8018258:	d0a05b83 	ldbu	r2,-32402(gp)
+ 801825c:	10803fcc 	andi	r2,r2,255
+ 8018260:	1080201c 	xori	r2,r2,128
+ 8018264:	10bfe004 	addi	r2,r2,-128
+ 8018268:	e0fff817 	ldw	r3,-32(fp)
+ 801826c:	18c002c3 	ldbu	r3,11(r3)
+ 8018270:	11001324 	muli	r4,r2,76
+ 8018274:	00820174 	movhi	r2,2053
+ 8018278:	2085883a 	add	r2,r4,r2
+ 801827c:	10ee57c5 	stb	r3,-18081(r2)
+        tse_mac_device[tse_system_count].tse_num_of_channel             = pmac->tse_num_of_channel;
+ 8018280:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018284:	10803fcc 	andi	r2,r2,255
+ 8018288:	1080201c 	xori	r2,r2,128
+ 801828c:	10bfe004 	addi	r2,r2,-128
+ 8018290:	e0fff817 	ldw	r3,-32(fp)
+ 8018294:	18c00303 	ldbu	r3,12(r3)
+ 8018298:	11001324 	muli	r4,r2,76
+ 801829c:	00820174 	movhi	r2,2053
+ 80182a0:	2085883a 	add	r2,r4,r2
+ 80182a4:	10ee5805 	stb	r3,-18080(r2)
+        tse_mac_device[tse_system_count].tse_mdio_shared                 = pmac->tse_mdio_shared;
+ 80182a8:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80182ac:	10803fcc 	andi	r2,r2,255
+ 80182b0:	1080201c 	xori	r2,r2,128
+ 80182b4:	10bfe004 	addi	r2,r2,-128
+ 80182b8:	e0fff817 	ldw	r3,-32(fp)
+ 80182bc:	18c00343 	ldbu	r3,13(r3)
+ 80182c0:	11001324 	muli	r4,r2,76
+ 80182c4:	00820174 	movhi	r2,2053
+ 80182c8:	2085883a 	add	r2,r4,r2
+ 80182cc:	10ee5845 	stb	r3,-18079(r2)
+        tse_mac_device[tse_system_count].tse_number_of_mac_mdio_shared    = pmac->tse_number_of_mac_mdio_shared;
+ 80182d0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80182d4:	10803fcc 	andi	r2,r2,255
+ 80182d8:	1080201c 	xori	r2,r2,128
+ 80182dc:	10bfe004 	addi	r2,r2,-128
+ 80182e0:	e0fff817 	ldw	r3,-32(fp)
+ 80182e4:	18c00383 	ldbu	r3,14(r3)
+ 80182e8:	11001324 	muli	r4,r2,76
+ 80182ec:	00820174 	movhi	r2,2053
+ 80182f0:	2085883a 	add	r2,r4,r2
+ 80182f4:	10ee5885 	stb	r3,-18078(r2)
+        tse_mac_device[tse_system_count].tse_pcs_ena                     = pmac->tse_pcs_ena;
+ 80182f8:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80182fc:	10803fcc 	andi	r2,r2,255
+ 8018300:	1080201c 	xori	r2,r2,128
+ 8018304:	10bfe004 	addi	r2,r2,-128
+ 8018308:	e0fff817 	ldw	r3,-32(fp)
+ 801830c:	18c003c3 	ldbu	r3,15(r3)
+ 8018310:	11001324 	muli	r4,r2,76
+ 8018314:	00820174 	movhi	r2,2053
+ 8018318:	2085883a 	add	r2,r4,r2
+ 801831c:	10ee58c5 	stb	r3,-18077(r2)
+        tse_mac_device[tse_system_count].tse_pcs_sgmii                     = pmac->tse_pcs_sgmii;
+ 8018320:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018324:	10803fcc 	andi	r2,r2,255
+ 8018328:	1080201c 	xori	r2,r2,128
+ 801832c:	10bfe004 	addi	r2,r2,-128
+ 8018330:	e0fff817 	ldw	r3,-32(fp)
+ 8018334:	18c00403 	ldbu	r3,16(r3)
+ 8018338:	11001324 	muli	r4,r2,76
+ 801833c:	00820174 	movhi	r2,2053
+ 8018340:	2085883a 	add	r2,r4,r2
+ 8018344:	10ee5905 	stb	r3,-18076(r2)
+        
+        /* Add MSGDMA info to alt_tse_system_info structure */
+        if(pmsgdma == 0) {
+ 8018348:	e0bffb17 	ldw	r2,-20(fp)
+ 801834c:	10000d1e 	bne	r2,zero,8018384 <alt_tse_system_add_sys+0x34c>
+            tse_dprintf(2, "ERROR   : MSGDMA system structure == NULL\n");
+ 8018350:	01020134 	movhi	r4,2052
+ 8018354:	211ecf04 	addi	r4,r4,31548
+ 8018358:	8002d9c0 	call	8002d9c <puts>
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_system_add_sys() for tse_mac_device[%d]\n", tse_system_count);
+ 801835c:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018360:	10803fcc 	andi	r2,r2,255
+ 8018364:	1080201c 	xori	r2,r2,128
+ 8018368:	10bfe004 	addi	r2,r2,-128
+ 801836c:	100b883a 	mov	r5,r2
+ 8018370:	01020134 	movhi	r4,2052
+ 8018374:	211eda04 	addi	r4,r4,31592
+ 8018378:	8002c780 	call	8002c78 <printf>
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 801837c:	00bfffc4 	movi	r2,-1
+ 8018380:	00015806 	br	80188e4 <alt_tse_system_add_sys+0x8ac>
+        }
+        
+        tse_mac_device[tse_system_count].tse_msgdma_tx = (char *) malloc(strlen(pmsgdma->tse_msgdma_tx) + 1);
+ 8018384:	e0bffb17 	ldw	r2,-20(fp)
+ 8018388:	10800017 	ldw	r2,0(r2)
+ 801838c:	1009883a 	mov	r4,r2
+ 8018390:	8002dac0 	call	8002dac <strlen>
+ 8018394:	10800044 	addi	r2,r2,1
+ 8018398:	d0e05b83 	ldbu	r3,-32402(gp)
+ 801839c:	1c003fcc 	andi	r16,r3,255
+ 80183a0:	8400201c 	xori	r16,r16,128
+ 80183a4:	843fe004 	addi	r16,r16,-128
+ 80183a8:	1009883a 	mov	r4,r2
+ 80183ac:	8042c980 	call	8042c98 <malloc>
+ 80183b0:	1009883a 	mov	r4,r2
+ 80183b4:	80c01324 	muli	r3,r16,76
+ 80183b8:	00820174 	movhi	r2,2053
+ 80183bc:	1885883a 	add	r2,r3,r2
+ 80183c0:	112e5a15 	stw	r4,-18072(r2)
+        if(!tse_mac_device[tse_system_count].tse_msgdma_tx) {
+ 80183c4:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80183c8:	10803fcc 	andi	r2,r2,255
+ 80183cc:	1080201c 	xori	r2,r2,128
+ 80183d0:	10bfe004 	addi	r2,r2,-128
+ 80183d4:	10c01324 	muli	r3,r2,76
+ 80183d8:	00820174 	movhi	r2,2053
+ 80183dc:	1885883a 	add	r2,r3,r2
+ 80183e0:	10ae5a17 	ldw	r2,-18072(r2)
+ 80183e4:	10000a1e 	bne	r2,zero,8018410 <alt_tse_system_add_sys+0x3d8>
+            tse_dprintf(1, "ERROR   : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_tx\n", tse_system_count);
+ 80183e8:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80183ec:	10803fcc 	andi	r2,r2,255
+ 80183f0:	1080201c 	xori	r2,r2,128
+ 80183f4:	10bfe004 	addi	r2,r2,-128
+ 80183f8:	100b883a 	mov	r5,r2
+ 80183fc:	01020134 	movhi	r4,2052
+ 8018400:	211ef204 	addi	r4,r4,31688
+ 8018404:	8002c780 	call	8002c78 <printf>
+            return ALTERA_TSE_MALLOC_FAILED;
+ 8018408:	00bfffc4 	movi	r2,-1
+ 801840c:	00013506 	br	80188e4 <alt_tse_system_add_sys+0x8ac>
+        }   
+        strcpy(tse_mac_device[tse_system_count].tse_msgdma_tx, pmsgdma->tse_msgdma_tx);
+ 8018410:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018414:	10803fcc 	andi	r2,r2,255
+ 8018418:	1080201c 	xori	r2,r2,128
+ 801841c:	10bfe004 	addi	r2,r2,-128
+ 8018420:	10c01324 	muli	r3,r2,76
+ 8018424:	00820174 	movhi	r2,2053
+ 8018428:	1885883a 	add	r2,r3,r2
+ 801842c:	10ee5a17 	ldw	r3,-18072(r2)
+ 8018430:	e0bffb17 	ldw	r2,-20(fp)
+ 8018434:	10800017 	ldw	r2,0(r2)
+ 8018438:	100b883a 	mov	r5,r2
+ 801843c:	1809883a 	mov	r4,r3
+ 8018440:	8042f600 	call	8042f60 <strcpy>
+        
+        tse_mac_device[tse_system_count].tse_msgdma_rx = (char *) malloc(strlen(pmsgdma->tse_msgdma_rx) + 1);
+ 8018444:	e0bffb17 	ldw	r2,-20(fp)
+ 8018448:	10800117 	ldw	r2,4(r2)
+ 801844c:	1009883a 	mov	r4,r2
+ 8018450:	8002dac0 	call	8002dac <strlen>
+ 8018454:	10800044 	addi	r2,r2,1
+ 8018458:	d0e05b83 	ldbu	r3,-32402(gp)
+ 801845c:	1c003fcc 	andi	r16,r3,255
+ 8018460:	8400201c 	xori	r16,r16,128
+ 8018464:	843fe004 	addi	r16,r16,-128
+ 8018468:	1009883a 	mov	r4,r2
+ 801846c:	8042c980 	call	8042c98 <malloc>
+ 8018470:	1009883a 	mov	r4,r2
+ 8018474:	80c01324 	muli	r3,r16,76
+ 8018478:	00820174 	movhi	r2,2053
+ 801847c:	1885883a 	add	r2,r3,r2
+ 8018480:	112e5b15 	stw	r4,-18068(r2)
+        if(!tse_mac_device[tse_system_count].tse_msgdma_rx) {
+ 8018484:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018488:	10803fcc 	andi	r2,r2,255
+ 801848c:	1080201c 	xori	r2,r2,128
+ 8018490:	10bfe004 	addi	r2,r2,-128
+ 8018494:	10c01324 	muli	r3,r2,76
+ 8018498:	00820174 	movhi	r2,2053
+ 801849c:	1885883a 	add	r2,r3,r2
+ 80184a0:	10ae5b17 	ldw	r2,-18068(r2)
+ 80184a4:	10000a1e 	bne	r2,zero,80184d0 <alt_tse_system_add_sys+0x498>
+            tse_dprintf(1, "ERROR   : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_rx\n", tse_system_count);
+ 80184a8:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80184ac:	10803fcc 	andi	r2,r2,255
+ 80184b0:	1080201c 	xori	r2,r2,128
+ 80184b4:	10bfe004 	addi	r2,r2,-128
+ 80184b8:	100b883a 	mov	r5,r2
+ 80184bc:	01020134 	movhi	r4,2052
+ 80184c0:	211f0504 	addi	r4,r4,31764
+ 80184c4:	8002c780 	call	8002c78 <printf>
+            return ALTERA_TSE_MALLOC_FAILED;
+ 80184c8:	00bfffc4 	movi	r2,-1
+ 80184cc:	00010506 	br	80188e4 <alt_tse_system_add_sys+0x8ac>
+        }
+        strcpy(tse_mac_device[tse_system_count].tse_msgdma_rx, pmsgdma->tse_msgdma_rx);
+ 80184d0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80184d4:	10803fcc 	andi	r2,r2,255
+ 80184d8:	1080201c 	xori	r2,r2,128
+ 80184dc:	10bfe004 	addi	r2,r2,-128
+ 80184e0:	10c01324 	muli	r3,r2,76
+ 80184e4:	00820174 	movhi	r2,2053
+ 80184e8:	1885883a 	add	r2,r3,r2
+ 80184ec:	10ee5b17 	ldw	r3,-18068(r2)
+ 80184f0:	e0bffb17 	ldw	r2,-20(fp)
+ 80184f4:	10800117 	ldw	r2,4(r2)
+ 80184f8:	100b883a 	mov	r5,r2
+ 80184fc:	1809883a 	mov	r4,r3
+ 8018500:	8042f600 	call	8042f60 <strcpy>
+        
+        tse_mac_device[tse_system_count].tse_msgdma_rx_irq = pmsgdma->tse_msgdma_rx_irq;
+ 8018504:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018508:	10803fcc 	andi	r2,r2,255
+ 801850c:	1080201c 	xori	r2,r2,128
+ 8018510:	10bfe004 	addi	r2,r2,-128
+ 8018514:	e0fffb17 	ldw	r3,-20(fp)
+ 8018518:	18c0020b 	ldhu	r3,8(r3)
+ 801851c:	11001324 	muli	r4,r2,76
+ 8018520:	00820174 	movhi	r2,2053
+ 8018524:	2085883a 	add	r2,r4,r2
+ 8018528:	10ee5c0d 	sth	r3,-18064(r2)
+        
+        /* Add descriptor memory info to alt_tse_system_info structure */
+        if(pmem == 0) {
+ 801852c:	e0bffc17 	ldw	r2,-16(fp)
+ 8018530:	1000111e 	bne	r2,zero,8018578 <alt_tse_system_add_sys+0x540>
+            tse_mac_device[tse_system_count].ext_desc_mem    = TSE_INT_DESC_MEM;
+ 8018534:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018538:	10803fcc 	andi	r2,r2,255
+ 801853c:	1080201c 	xori	r2,r2,128
+ 8018540:	10bfe004 	addi	r2,r2,-128
+ 8018544:	10c01324 	muli	r3,r2,76
+ 8018548:	00820174 	movhi	r2,2053
+ 801854c:	1885883a 	add	r2,r3,r2
+ 8018550:	102e5c85 	stb	zero,-18062(r2)
+            tse_mac_device[tse_system_count].desc_mem_base    = TSE_INT_DESC_MEM;
+ 8018554:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018558:	10803fcc 	andi	r2,r2,255
+ 801855c:	1080201c 	xori	r2,r2,128
+ 8018560:	10bfe004 	addi	r2,r2,-128
+ 8018564:	10c01324 	muli	r3,r2,76
+ 8018568:	00820174 	movhi	r2,2053
+ 801856c:	1885883a 	add	r2,r3,r2
+ 8018570:	102e5d15 	stw	zero,-18060(r2)
+ 8018574:	00001406 	br	80185c8 <alt_tse_system_add_sys+0x590>
+        }
+        else {
+            tse_mac_device[tse_system_count].ext_desc_mem    = pmem->ext_desc_mem;
+ 8018578:	d0a05b83 	ldbu	r2,-32402(gp)
+ 801857c:	10803fcc 	andi	r2,r2,255
+ 8018580:	1080201c 	xori	r2,r2,128
+ 8018584:	10bfe004 	addi	r2,r2,-128
+ 8018588:	e0fffc17 	ldw	r3,-16(fp)
+ 801858c:	18c00003 	ldbu	r3,0(r3)
+ 8018590:	11001324 	muli	r4,r2,76
+ 8018594:	00820174 	movhi	r2,2053
+ 8018598:	2085883a 	add	r2,r4,r2
+ 801859c:	10ee5c85 	stb	r3,-18062(r2)
+            tse_mac_device[tse_system_count].desc_mem_base    = pmem->desc_mem_base;
+ 80185a0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80185a4:	10803fcc 	andi	r2,r2,255
+ 80185a8:	1080201c 	xori	r2,r2,128
+ 80185ac:	10bfe004 	addi	r2,r2,-128
+ 80185b0:	e0fffc17 	ldw	r3,-16(fp)
+ 80185b4:	18c00117 	ldw	r3,4(r3)
+ 80185b8:	11001324 	muli	r4,r2,76
+ 80185bc:	00820174 	movhi	r2,2053
+ 80185c0:	2085883a 	add	r2,r4,r2
+ 80185c4:	10ee5d15 	stw	r3,-18060(r2)
+        }
+        
+        /* Add shared fifo info to alt_tse_system_info structure */
+        if(pfifo == 0) {
+ 80185c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80185cc:	1000391e 	bne	r2,zero,80186b4 <alt_tse_system_add_sys+0x67c>
+            tse_mac_device[tse_system_count].use_shared_fifo                = TSE_NO_SHARED_FIFO;
+ 80185d0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80185d4:	10803fcc 	andi	r2,r2,255
+ 80185d8:	1080201c 	xori	r2,r2,128
+ 80185dc:	10bfe004 	addi	r2,r2,-128
+ 80185e0:	10c01324 	muli	r3,r2,76
+ 80185e4:	00820174 	movhi	r2,2053
+ 80185e8:	1885883a 	add	r2,r3,r2
+ 80185ec:	102e5e05 	stb	zero,-18056(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base    = TSE_NO_SHARED_FIFO;
+ 80185f0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80185f4:	10803fcc 	andi	r2,r2,255
+ 80185f8:	1080201c 	xori	r2,r2,128
+ 80185fc:	10bfe004 	addi	r2,r2,-128
+ 8018600:	10c01324 	muli	r3,r2,76
+ 8018604:	00820174 	movhi	r2,2053
+ 8018608:	1885883a 	add	r2,r3,r2
+ 801860c:	102e5f15 	stw	zero,-18052(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base    = TSE_NO_SHARED_FIFO;
+ 8018610:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018614:	10803fcc 	andi	r2,r2,255
+ 8018618:	1080201c 	xori	r2,r2,128
+ 801861c:	10bfe004 	addi	r2,r2,-128
+ 8018620:	10c01324 	muli	r3,r2,76
+ 8018624:	00820174 	movhi	r2,2053
+ 8018628:	1885883a 	add	r2,r3,r2
+ 801862c:	102e6015 	stw	zero,-18048(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth       = TSE_NO_SHARED_FIFO;
+ 8018630:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018634:	10803fcc 	andi	r2,r2,255
+ 8018638:	1080201c 	xori	r2,r2,128
+ 801863c:	10bfe004 	addi	r2,r2,-128
+ 8018640:	10c01324 	muli	r3,r2,76
+ 8018644:	00820174 	movhi	r2,2053
+ 8018648:	1885883a 	add	r2,r3,r2
+ 801864c:	102e6115 	stw	zero,-18044(r2)
+            
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base    = TSE_NO_SHARED_FIFO;
+ 8018650:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018654:	10803fcc 	andi	r2,r2,255
+ 8018658:	1080201c 	xori	r2,r2,128
+ 801865c:	10bfe004 	addi	r2,r2,-128
+ 8018660:	10c01324 	muli	r3,r2,76
+ 8018664:	00820174 	movhi	r2,2053
+ 8018668:	1885883a 	add	r2,r3,r2
+ 801866c:	102e6215 	stw	zero,-18040(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base    = TSE_NO_SHARED_FIFO;
+ 8018670:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018674:	10803fcc 	andi	r2,r2,255
+ 8018678:	1080201c 	xori	r2,r2,128
+ 801867c:	10bfe004 	addi	r2,r2,-128
+ 8018680:	10c01324 	muli	r3,r2,76
+ 8018684:	00820174 	movhi	r2,2053
+ 8018688:	1885883a 	add	r2,r3,r2
+ 801868c:	102e6315 	stw	zero,-18036(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth       = TSE_NO_SHARED_FIFO;
+ 8018690:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018694:	10803fcc 	andi	r2,r2,255
+ 8018698:	1080201c 	xori	r2,r2,128
+ 801869c:	10bfe004 	addi	r2,r2,-128
+ 80186a0:	10c01324 	muli	r3,r2,76
+ 80186a4:	00820174 	movhi	r2,2053
+ 80186a8:	1885883a 	add	r2,r3,r2
+ 80186ac:	102e6415 	stw	zero,-18032(r2)
+ 80186b0:	00004606 	br	80187cc <alt_tse_system_add_sys+0x794>
+        }
+        else {
+            tse_mac_device[tse_system_count].use_shared_fifo                = pfifo->use_shared_fifo;
+ 80186b4:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80186b8:	10803fcc 	andi	r2,r2,255
+ 80186bc:	1080201c 	xori	r2,r2,128
+ 80186c0:	10bfe004 	addi	r2,r2,-128
+ 80186c4:	e0fffe17 	ldw	r3,-8(fp)
+ 80186c8:	18c00003 	ldbu	r3,0(r3)
+ 80186cc:	11001324 	muli	r4,r2,76
+ 80186d0:	00820174 	movhi	r2,2053
+ 80186d4:	2085883a 	add	r2,r4,r2
+ 80186d8:	10ee5e05 	stb	r3,-18056(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base    = pfifo->tse_shared_fifo_tx_ctrl_base;
+ 80186dc:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80186e0:	10803fcc 	andi	r2,r2,255
+ 80186e4:	1080201c 	xori	r2,r2,128
+ 80186e8:	10bfe004 	addi	r2,r2,-128
+ 80186ec:	e0fffe17 	ldw	r3,-8(fp)
+ 80186f0:	18c00117 	ldw	r3,4(r3)
+ 80186f4:	11001324 	muli	r4,r2,76
+ 80186f8:	00820174 	movhi	r2,2053
+ 80186fc:	2085883a 	add	r2,r4,r2
+ 8018700:	10ee5f15 	stw	r3,-18052(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base    = pfifo->tse_shared_fifo_tx_stat_base;
+ 8018704:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018708:	10803fcc 	andi	r2,r2,255
+ 801870c:	1080201c 	xori	r2,r2,128
+ 8018710:	10bfe004 	addi	r2,r2,-128
+ 8018714:	e0fffe17 	ldw	r3,-8(fp)
+ 8018718:	18c00217 	ldw	r3,8(r3)
+ 801871c:	11001324 	muli	r4,r2,76
+ 8018720:	00820174 	movhi	r2,2053
+ 8018724:	2085883a 	add	r2,r4,r2
+ 8018728:	10ee6015 	stw	r3,-18048(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth       = pfifo->tse_shared_fifo_tx_depth;
+ 801872c:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018730:	10803fcc 	andi	r2,r2,255
+ 8018734:	1080201c 	xori	r2,r2,128
+ 8018738:	10bfe004 	addi	r2,r2,-128
+ 801873c:	e0fffe17 	ldw	r3,-8(fp)
+ 8018740:	18c00317 	ldw	r3,12(r3)
+ 8018744:	11001324 	muli	r4,r2,76
+ 8018748:	00820174 	movhi	r2,2053
+ 801874c:	2085883a 	add	r2,r4,r2
+ 8018750:	10ee6115 	stw	r3,-18044(r2)
+            
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base    = pfifo->tse_shared_fifo_rx_ctrl_base;
+ 8018754:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018758:	10803fcc 	andi	r2,r2,255
+ 801875c:	1080201c 	xori	r2,r2,128
+ 8018760:	10bfe004 	addi	r2,r2,-128
+ 8018764:	e0fffe17 	ldw	r3,-8(fp)
+ 8018768:	18c00417 	ldw	r3,16(r3)
+ 801876c:	11001324 	muli	r4,r2,76
+ 8018770:	00820174 	movhi	r2,2053
+ 8018774:	2085883a 	add	r2,r4,r2
+ 8018778:	10ee6215 	stw	r3,-18040(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base    = pfifo->tse_shared_fifo_rx_stat_base;
+ 801877c:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018780:	10803fcc 	andi	r2,r2,255
+ 8018784:	1080201c 	xori	r2,r2,128
+ 8018788:	10bfe004 	addi	r2,r2,-128
+ 801878c:	e0fffe17 	ldw	r3,-8(fp)
+ 8018790:	18c00517 	ldw	r3,20(r3)
+ 8018794:	11001324 	muli	r4,r2,76
+ 8018798:	00820174 	movhi	r2,2053
+ 801879c:	2085883a 	add	r2,r4,r2
+ 80187a0:	10ee6315 	stw	r3,-18036(r2)
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth       = pfifo->tse_shared_fifo_rx_depth;
+ 80187a4:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80187a8:	10803fcc 	andi	r2,r2,255
+ 80187ac:	1080201c 	xori	r2,r2,128
+ 80187b0:	10bfe004 	addi	r2,r2,-128
+ 80187b4:	e0fffe17 	ldw	r3,-8(fp)
+ 80187b8:	18c00617 	ldw	r3,24(r3)
+ 80187bc:	11001324 	muli	r4,r2,76
+ 80187c0:	00820174 	movhi	r2,2053
+ 80187c4:	2085883a 	add	r2,r4,r2
+ 80187c8:	10ee6415 	stw	r3,-18032(r2)
+        }
+        
+        /* Add PHY info to alt_tse_system_info structure */
+        if(pphy == 0) {
+ 80187cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80187d0:	1000121e 	bne	r2,zero,801881c <alt_tse_system_add_sys+0x7e4>
+            tse_mac_device[tse_system_count].tse_phy_mdio_address    = TSE_PHY_AUTO_ADDRESS;
+ 80187d4:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80187d8:	10803fcc 	andi	r2,r2,255
+ 80187dc:	1080201c 	xori	r2,r2,128
+ 80187e0:	10bfe004 	addi	r2,r2,-128
+ 80187e4:	11001324 	muli	r4,r2,76
+ 80187e8:	00ffffc4 	movi	r3,-1
+ 80187ec:	00820174 	movhi	r2,2053
+ 80187f0:	2085883a 	add	r2,r4,r2
+ 80187f4:	10ee6515 	stw	r3,-18028(r2)
+            tse_mac_device[tse_system_count].tse_phy_cfg             = 0;
+ 80187f8:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80187fc:	10803fcc 	andi	r2,r2,255
+ 8018800:	1080201c 	xori	r2,r2,128
+ 8018804:	10bfe004 	addi	r2,r2,-128
+ 8018808:	10c01324 	muli	r3,r2,76
+ 801880c:	00820174 	movhi	r2,2053
+ 8018810:	1885883a 	add	r2,r3,r2
+ 8018814:	102e6615 	stw	zero,-18024(r2)
+ 8018818:	00001406 	br	801886c <alt_tse_system_add_sys+0x834>
+        }
+        else {
+            tse_mac_device[tse_system_count].tse_phy_mdio_address    = pphy->tse_phy_mdio_address;
+ 801881c:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018820:	10803fcc 	andi	r2,r2,255
+ 8018824:	1080201c 	xori	r2,r2,128
+ 8018828:	10bfe004 	addi	r2,r2,-128
+ 801882c:	e0fffd17 	ldw	r3,-12(fp)
+ 8018830:	18c00017 	ldw	r3,0(r3)
+ 8018834:	11001324 	muli	r4,r2,76
+ 8018838:	00820174 	movhi	r2,2053
+ 801883c:	2085883a 	add	r2,r4,r2
+ 8018840:	10ee6515 	stw	r3,-18028(r2)
+            tse_mac_device[tse_system_count].tse_phy_cfg             = pphy->tse_phy_cfg;
+ 8018844:	d0a05b83 	ldbu	r2,-32402(gp)
+ 8018848:	10803fcc 	andi	r2,r2,255
+ 801884c:	1080201c 	xori	r2,r2,128
+ 8018850:	10bfe004 	addi	r2,r2,-128
+ 8018854:	e0fffd17 	ldw	r3,-12(fp)
+ 8018858:	18c00117 	ldw	r3,4(r3)
+ 801885c:	11001324 	muli	r4,r2,76
+ 8018860:	00820174 	movhi	r2,2053
+ 8018864:	2085883a 	add	r2,r4,r2
+ 8018868:	10ee6615 	stw	r3,-18024(r2)
+        }
+        
+        /* Point to next structure */
+        pmsgdma++;
+ 801886c:	e0bffb17 	ldw	r2,-20(fp)
+ 8018870:	10800304 	addi	r2,r2,12
+ 8018874:	e0bffb15 	stw	r2,-20(fp)
+        if(pmem) pmem++;
+ 8018878:	e0bffc17 	ldw	r2,-16(fp)
+ 801887c:	10000326 	beq	r2,zero,801888c <alt_tse_system_add_sys+0x854>
+ 8018880:	e0bffc17 	ldw	r2,-16(fp)
+ 8018884:	10800204 	addi	r2,r2,8
+ 8018888:	e0bffc15 	stw	r2,-16(fp)
+        if(pfifo) pfifo++;
+ 801888c:	e0bffe17 	ldw	r2,-8(fp)
+ 8018890:	10000326 	beq	r2,zero,80188a0 <alt_tse_system_add_sys+0x868>
+ 8018894:	e0bffe17 	ldw	r2,-8(fp)
+ 8018898:	10800704 	addi	r2,r2,28
+ 801889c:	e0bffe15 	stw	r2,-8(fp)
+        if(pphy) pphy++;
+ 80188a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80188a4:	10000326 	beq	r2,zero,80188b4 <alt_tse_system_add_sys+0x87c>
+ 80188a8:	e0bffd17 	ldw	r2,-12(fp)
+ 80188ac:	10800204 	addi	r2,r2,8
+ 80188b0:	e0bffd15 	stw	r2,-12(fp)
+        
+        tse_system_count++;
+ 80188b4:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80188b8:	10800044 	addi	r2,r2,1
+ 80188bc:	d0a05b85 	stb	r2,-32402(gp)
+        max_mac_system = tse_system_count;
+ 80188c0:	d0a05b83 	ldbu	r2,-32402(gp)
+ 80188c4:	d0a00a05 	stb	r2,-32728(gp)
+    for(i = 0; i < loop_end; i++) {
+ 80188c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80188cc:	10800044 	addi	r2,r2,1
+ 80188d0:	e0bffa15 	stw	r2,-24(fp)
+ 80188d4:	e0fffa17 	ldw	r3,-24(fp)
+ 80188d8:	e0bff917 	ldw	r2,-28(fp)
+ 80188dc:	18be0016 	blt	r3,r2,80180e0 <alt_tse_system_add_sys+0xa8>
+    }
+    
+    return SUCCESS;
+ 80188e0:	0005883a 	mov	r2,zero
+    
+}
+ 80188e4:	e6ffff04 	addi	sp,fp,-4
+ 80188e8:	dfc00217 	ldw	ra,8(sp)
+ 80188ec:	df000117 	ldw	fp,4(sp)
+ 80188f0:	dc000017 	ldw	r16,0(sp)
+ 80188f4:	dec00304 	addi	sp,sp,12
+ 80188f8:	f800283a 	ret
+
+080188fc <alt_tse_sys_enable_mdio_sharing>:
+ * @param        number_of_mac  number of MAC sharing MDIO block
+ * @return      SUCCESS on success
+ *                 ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL
+ * Multi-channel MAC not supported
+ */
+alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac) {
+ 80188fc:	defff904 	addi	sp,sp,-28
+ 8018900:	dfc00615 	stw	ra,24(sp)
+ 8018904:	df000515 	stw	fp,20(sp)
+ 8018908:	df000504 	addi	fp,sp,20
+ 801890c:	e13ffc15 	stw	r4,-16(fp)
+ 8018910:	2805883a 	mov	r2,r5
+ 8018914:	e0bffb05 	stb	r2,-20(fp)
+    alt_32 i;
+    alt_32 j;
+    
+    alt_tse_system_mac *psys_mac;
+    
+    for(i = 0; i < number_of_mac; i++) {
+ 8018918:	e03fff15 	stw	zero,-4(fp)
+ 801891c:	00003f06 	br	8018a1c <alt_tse_sys_enable_mdio_sharing+0x120>
+        psys_mac = psys_mac_list[i];
+ 8018920:	e0bfff17 	ldw	r2,-4(fp)
+ 8018924:	100490ba 	slli	r2,r2,2
+ 8018928:	e0fffc17 	ldw	r3,-16(fp)
+ 801892c:	1885883a 	add	r2,r3,r2
+ 8018930:	10800017 	ldw	r2,0(r2)
+ 8018934:	e0bffd15 	stw	r2,-12(fp)
+        
+        if(psys_mac == 0) {
+ 8018938:	e0bffd17 	ldw	r2,-12(fp)
+ 801893c:	1000081e 	bne	r2,zero,8018960 <alt_tse_sys_enable_mdio_sharing+0x64>
+            tse_dprintf(2, "ERROR   : MAC system structure == NULL\n");
+ 8018940:	01020134 	movhi	r4,2052
+ 8018944:	211eb304 	addi	r4,r4,31436
+ 8018948:	8002d9c0 	call	8002d9c <puts>
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_sys_enable_mdio_sharing()\n");
+ 801894c:	01020134 	movhi	r4,2052
+ 8018950:	211f1804 	addi	r4,r4,31840
+ 8018954:	8002d9c0 	call	8002d9c <puts>
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 8018958:	00bfffc4 	movi	r2,-1
+ 801895c:	00003306 	br	8018a2c <alt_tse_sys_enable_mdio_sharing+0x130>
+        }
+        
+        for(j = 0; j < max_mac_system; j++) {
+ 8018960:	e03ffe15 	stw	zero,-8(fp)
+ 8018964:	00002606 	br	8018a00 <alt_tse_sys_enable_mdio_sharing+0x104>
+            
+            if(psys_mac->tse_mac_base == tse_mac_device[j].tse_mac_base) {
+ 8018968:	e0bffd17 	ldw	r2,-12(fp)
+ 801896c:	10c00017 	ldw	r3,0(r2)
+ 8018970:	e0bffe17 	ldw	r2,-8(fp)
+ 8018974:	11001324 	muli	r4,r2,76
+ 8018978:	00820174 	movhi	r2,2053
+ 801897c:	2085883a 	add	r2,r4,r2
+ 8018980:	10ae5417 	ldw	r2,-18096(r2)
+ 8018984:	18801b1e 	bne	r3,r2,80189f4 <alt_tse_sys_enable_mdio_sharing+0xf8>
+                if(tse_mac_device[j].tse_multichannel_mac) {
+ 8018988:	e0bffe17 	ldw	r2,-8(fp)
+ 801898c:	10c01324 	muli	r3,r2,76
+ 8018990:	00820174 	movhi	r2,2053
+ 8018994:	1885883a 	add	r2,r3,r2
+ 8018998:	10ae57c3 	ldbu	r2,-18081(r2)
+ 801899c:	10803fcc 	andi	r2,r2,255
+ 80189a0:	10000826 	beq	r2,zero,80189c4 <alt_tse_sys_enable_mdio_sharing+0xc8>
+                    tse_dprintf(2, "ERROR   : MDIO sharing supported by default for Multi-channel MAC\n");
+ 80189a4:	01020134 	movhi	r4,2052
+ 80189a8:	211f2c04 	addi	r4,r4,31920
+ 80189ac:	8002d9c0 	call	8002d9c <puts>
+                    tse_dprintf(2, "ERROR   : Do not include Multi-channel MAC in the MAC List\n");
+ 80189b0:	01020134 	movhi	r4,2052
+ 80189b4:	211f3d04 	addi	r4,r4,31988
+ 80189b8:	8002d9c0 	call	8002d9c <puts>
+                    return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 80189bc:	00bfffc4 	movi	r2,-1
+ 80189c0:	00001a06 	br	8018a2c <alt_tse_sys_enable_mdio_sharing+0x130>
+                }
+                
+                tse_mac_device[j].tse_mdio_shared = 1;
+ 80189c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80189c8:	11001324 	muli	r4,r2,76
+ 80189cc:	00c00044 	movi	r3,1
+ 80189d0:	00820174 	movhi	r2,2053
+ 80189d4:	2085883a 	add	r2,r4,r2
+ 80189d8:	10ee5845 	stb	r3,-18079(r2)
+                tse_mac_device[j].tse_number_of_mac_mdio_shared = number_of_mac;
+ 80189dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80189e0:	11001324 	muli	r4,r2,76
+ 80189e4:	e0fffb03 	ldbu	r3,-20(fp)
+ 80189e8:	00820174 	movhi	r2,2053
+ 80189ec:	2085883a 	add	r2,r4,r2
+ 80189f0:	10ee5885 	stb	r3,-18078(r2)
+        for(j = 0; j < max_mac_system; j++) {
+ 80189f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80189f8:	10800044 	addi	r2,r2,1
+ 80189fc:	e0bffe15 	stw	r2,-8(fp)
+ 8018a00:	d0a00a03 	ldbu	r2,-32728(gp)
+ 8018a04:	10803fcc 	andi	r2,r2,255
+ 8018a08:	e0fffe17 	ldw	r3,-8(fp)
+ 8018a0c:	18bfd616 	blt	r3,r2,8018968 <alt_tse_sys_enable_mdio_sharing+0x6c>
+    for(i = 0; i < number_of_mac; i++) {
+ 8018a10:	e0bfff17 	ldw	r2,-4(fp)
+ 8018a14:	10800044 	addi	r2,r2,1
+ 8018a18:	e0bfff15 	stw	r2,-4(fp)
+ 8018a1c:	e0bffb03 	ldbu	r2,-20(fp)
+ 8018a20:	e0ffff17 	ldw	r3,-4(fp)
+ 8018a24:	18bfbe16 	blt	r3,r2,8018920 <alt_tse_sys_enable_mdio_sharing+0x24>
+            }
+        }    
+    }
+    
+    return SUCCESS;
+ 8018a28:	0005883a 	mov	r2,zero
+}
+ 8018a2c:	e037883a 	mov	sp,fp
+ 8018a30:	dfc00117 	ldw	ra,4(sp)
+ 8018a34:	df000017 	ldw	fp,0(sp)
+ 8018a38:	dec00204 	addi	sp,sp,8
+ 8018a3c:	f800283a 	ret
+
+08018a40 <alt_tse_mac_get_common_speed>:
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Public
+ * @param pmac          Pointer to the TSE MAC Control Interface Base address
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac) {
+ 8018a40:	defffc04 	addi	sp,sp,-16
+ 8018a44:	dfc00315 	stw	ra,12(sp)
+ 8018a48:	df000215 	stw	fp,8(sp)
+ 8018a4c:	df000204 	addi	fp,sp,8
+ 8018a50:	e13ffe15 	stw	r4,-8(fp)
+    alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group;
+ 8018a54:	e13ffe17 	ldw	r4,-8(fp)
+ 8018a58:	8018c1c0 	call	8018c1c <alt_tse_get_mac_info>
+ 8018a5c:	10800317 	ldw	r2,12(r2)
+ 8018a60:	e0bfff15 	stw	r2,-4(fp)
+    return alt_tse_phy_get_common_speed(pmac_group);
+ 8018a64:	e13fff17 	ldw	r4,-4(fp)
+ 8018a68:	801bdb00 	call	801bdb0 <alt_tse_phy_get_common_speed>
+}
+ 8018a6c:	e037883a 	mov	sp,fp
+ 8018a70:	dfc00117 	ldw	ra,4(sp)
+ 8018a74:	df000017 	ldw	fp,0(sp)
+ 8018a78:	dec00204 	addi	sp,sp,8
+ 8018a7c:	f800283a 	ret
+
+08018a80 <alt_tse_mac_set_common_speed>:
+ * @API Type:               Public
+ * @param pmac              Pointer to the TSE MAC Control Interface Base address
+ *        common_speed      common speed supported by all PHYs
+ * @return                  common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed) {
+ 8018a80:	defffb04 	addi	sp,sp,-20
+ 8018a84:	dfc00415 	stw	ra,16(sp)
+ 8018a88:	df000315 	stw	fp,12(sp)
+ 8018a8c:	df000304 	addi	fp,sp,12
+ 8018a90:	e13ffe15 	stw	r4,-8(fp)
+ 8018a94:	e17ffd15 	stw	r5,-12(fp)
+    alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group;
+ 8018a98:	e13ffe17 	ldw	r4,-8(fp)
+ 8018a9c:	8018c1c0 	call	8018c1c <alt_tse_get_mac_info>
+ 8018aa0:	10800317 	ldw	r2,12(r2)
+ 8018aa4:	e0bfff15 	stw	r2,-4(fp)
+    return alt_tse_phy_set_common_speed(pmac_group, common_speed);
+ 8018aa8:	e17ffd17 	ldw	r5,-12(fp)
+ 8018aac:	e13fff17 	ldw	r4,-4(fp)
+ 8018ab0:	801c0cc0 	call	801c0cc <alt_tse_phy_set_common_speed>
+}
+ 8018ab4:	e037883a 	mov	sp,fp
+ 8018ab8:	dfc00117 	ldw	ra,4(sp)
+ 8018abc:	df000017 	ldw	fp,0(sp)
+ 8018ac0:	dec00204 	addi	sp,sp,8
+ 8018ac4:	f800283a 	ret
+
+08018ac8 <alt_tse_get_system_index>:
+/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[]
+ * @API Type:        Internal
+ * @param psys_info  Pointer to the alt_tse_system_info structure
+ * @return           Index of alt_tse_system_info structure in tse_mac_device[]
+ */
+alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info) {
+ 8018ac8:	defffd04 	addi	sp,sp,-12
+ 8018acc:	df000215 	stw	fp,8(sp)
+ 8018ad0:	df000204 	addi	fp,sp,8
+ 8018ad4:	e13ffe15 	stw	r4,-8(fp)
+    alt_32 i;
+    
+    for(i = 0; i < max_mac_system; i++) {
+ 8018ad8:	e03fff15 	stw	zero,-4(fp)
+ 8018adc:	00000c06 	br	8018b10 <alt_tse_get_system_index+0x48>
+        if(psys_info == &tse_mac_device[i]) {
+ 8018ae0:	e0bfff17 	ldw	r2,-4(fp)
+ 8018ae4:	10c01324 	muli	r3,r2,76
+ 8018ae8:	00820174 	movhi	r2,2053
+ 8018aec:	10ae5404 	addi	r2,r2,-18096
+ 8018af0:	1885883a 	add	r2,r3,r2
+ 8018af4:	e0fffe17 	ldw	r3,-8(fp)
+ 8018af8:	1880021e 	bne	r3,r2,8018b04 <alt_tse_get_system_index+0x3c>
+            return i;
+ 8018afc:	e0bfff17 	ldw	r2,-4(fp)
+ 8018b00:	00000806 	br	8018b24 <alt_tse_get_system_index+0x5c>
+    for(i = 0; i < max_mac_system; i++) {
+ 8018b04:	e0bfff17 	ldw	r2,-4(fp)
+ 8018b08:	10800044 	addi	r2,r2,1
+ 8018b0c:	e0bfff15 	stw	r2,-4(fp)
+ 8018b10:	d0a00a03 	ldbu	r2,-32728(gp)
+ 8018b14:	10803fcc 	andi	r2,r2,255
+ 8018b18:	e0ffff17 	ldw	r3,-4(fp)
+ 8018b1c:	18bff016 	blt	r3,r2,8018ae0 <alt_tse_get_system_index+0x18>
+        }
+    }
+    return ALTERA_TSE_NO_INDEX_FOUND;
+ 8018b20:	00bfffc4 	movi	r2,-1
+}
+ 8018b24:	e037883a 	mov	sp,fp
+ 8018b28:	df000017 	ldw	fp,0(sp)
+ 8018b2c:	dec00104 	addi	sp,sp,4
+ 8018b30:	f800283a 	ret
+
+08018b34 <alt_tse_get_mac_group_index>:
+/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_group structure
+ * @return            Index of alt_tse_mac_group structure in pmac_groups[]
+ */
+alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group) {
+ 8018b34:	defffd04 	addi	sp,sp,-12
+ 8018b38:	df000215 	stw	fp,8(sp)
+ 8018b3c:	df000204 	addi	fp,sp,8
+ 8018b40:	e13ffe15 	stw	r4,-8(fp)
+    alt_32 i;
+    
+    for(i = 0; i < mac_group_count; i++) {
+ 8018b44:	e03fff15 	stw	zero,-4(fp)
+ 8018b48:	00000c06 	br	8018b7c <alt_tse_get_mac_group_index+0x48>
+        if(pmac_group == pmac_groups[i]) {
+ 8018b4c:	e0bfff17 	ldw	r2,-4(fp)
+ 8018b50:	100690ba 	slli	r3,r2,2
+ 8018b54:	008201b4 	movhi	r2,2054
+ 8018b58:	1885883a 	add	r2,r3,r2
+ 8018b5c:	10b5aa17 	ldw	r2,-10584(r2)
+ 8018b60:	e0fffe17 	ldw	r3,-8(fp)
+ 8018b64:	1880021e 	bne	r3,r2,8018b70 <alt_tse_get_mac_group_index+0x3c>
+            return i;
+ 8018b68:	e0bfff17 	ldw	r2,-4(fp)
+ 8018b6c:	00000806 	br	8018b90 <alt_tse_get_mac_group_index+0x5c>
+    for(i = 0; i < mac_group_count; i++) {
+ 8018b70:	e0bfff17 	ldw	r2,-4(fp)
+ 8018b74:	10800044 	addi	r2,r2,1
+ 8018b78:	e0bfff15 	stw	r2,-4(fp)
+ 8018b7c:	d0a05b43 	ldbu	r2,-32403(gp)
+ 8018b80:	10803fcc 	andi	r2,r2,255
+ 8018b84:	e0ffff17 	ldw	r3,-4(fp)
+ 8018b88:	18bff016 	blt	r3,r2,8018b4c <alt_tse_get_mac_group_index+0x18>
+        }
+    }
+    return ALTERA_TSE_NO_INDEX_FOUND;
+ 8018b8c:	00bfffc4 	movi	r2,-1
+}
+ 8018b90:	e037883a 	mov	sp,fp
+ 8018b94:	df000017 	ldw	fp,0(sp)
+ 8018b98:	dec00104 	addi	sp,sp,4
+ 8018b9c:	f800283a 	ret
+
+08018ba0 <alt_tse_get_mac_info_index>:
+/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_info structure
+ * @return            Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info) {
+ 8018ba0:	defffd04 	addi	sp,sp,-12
+ 8018ba4:	df000215 	stw	fp,8(sp)
+ 8018ba8:	df000204 	addi	fp,sp,8
+ 8018bac:	e13ffe15 	stw	r4,-8(fp)
+    alt_32 i;
+    
+    for(i = 0; i < pmac_info->pmac_group->channel; i++) {
+ 8018bb0:	e03fff15 	stw	zero,-4(fp)
+ 8018bb4:	00000e06 	br	8018bf0 <alt_tse_get_mac_info_index+0x50>
+        if(pmac_info == pmac_info->pmac_group->pmac_info[i]) {
+ 8018bb8:	e0bffe17 	ldw	r2,-8(fp)
+ 8018bbc:	10c00317 	ldw	r3,12(r2)
+ 8018bc0:	e0bfff17 	ldw	r2,-4(fp)
+ 8018bc4:	10800044 	addi	r2,r2,1
+ 8018bc8:	100490ba 	slli	r2,r2,2
+ 8018bcc:	1885883a 	add	r2,r3,r2
+ 8018bd0:	10800017 	ldw	r2,0(r2)
+ 8018bd4:	e0fffe17 	ldw	r3,-8(fp)
+ 8018bd8:	1880021e 	bne	r3,r2,8018be4 <alt_tse_get_mac_info_index+0x44>
+            return i;
+ 8018bdc:	e0bfff17 	ldw	r2,-4(fp)
+ 8018be0:	00000a06 	br	8018c0c <alt_tse_get_mac_info_index+0x6c>
+    for(i = 0; i < pmac_info->pmac_group->channel; i++) {
+ 8018be4:	e0bfff17 	ldw	r2,-4(fp)
+ 8018be8:	10800044 	addi	r2,r2,1
+ 8018bec:	e0bfff15 	stw	r2,-4(fp)
+ 8018bf0:	e0bffe17 	ldw	r2,-8(fp)
+ 8018bf4:	10800317 	ldw	r2,12(r2)
+ 8018bf8:	10800003 	ldbu	r2,0(r2)
+ 8018bfc:	10803fcc 	andi	r2,r2,255
+ 8018c00:	e0ffff17 	ldw	r3,-4(fp)
+ 8018c04:	18bfec16 	blt	r3,r2,8018bb8 <alt_tse_get_mac_info_index+0x18>
+        }
+    }
+    
+    return ALTERA_TSE_NO_INDEX_FOUND;
+ 8018c08:	00bfffc4 	movi	r2,-1
+}
+ 8018c0c:	e037883a 	mov	sp,fp
+ 8018c10:	df000017 	ldw	fp,0(sp)
+ 8018c14:	dec00104 	addi	sp,sp,4
+ 8018c18:	f800283a 	ret
+
+08018c1c <alt_tse_get_mac_info>:
+/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac        Pointer to the TSE MAC Control Interface Base address
+ * @return            Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac) {
+ 8018c1c:	defffa04 	addi	sp,sp,-24
+ 8018c20:	df000515 	stw	fp,20(sp)
+ 8018c24:	df000504 	addi	fp,sp,20
+ 8018c28:	e13ffb15 	stw	r4,-20(fp)
+    alt_32 i;
+    alt_32 j;
+    alt_tse_mac_group *pmac_group = 0;
+ 8018c2c:	e03ffd15 	stw	zero,-12(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 8018c30:	e03ffc15 	stw	zero,-16(fp)
+    
+    for(i = 0; i < mac_group_count; i++) {
+ 8018c34:	e03fff15 	stw	zero,-4(fp)
+ 8018c38:	00002206 	br	8018cc4 <alt_tse_get_mac_info+0xa8>
+        pmac_group = pmac_groups[i];
+ 8018c3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8018c40:	100690ba 	slli	r3,r2,2
+ 8018c44:	008201b4 	movhi	r2,2054
+ 8018c48:	1885883a 	add	r2,r3,r2
+ 8018c4c:	10b5aa17 	ldw	r2,-10584(r2)
+ 8018c50:	e0bffd15 	stw	r2,-12(fp)
+        for(j = 0; j < pmac_group->channel; j++) {
+ 8018c54:	e03ffe15 	stw	zero,-8(fp)
+ 8018c58:	00001206 	br	8018ca4 <alt_tse_get_mac_info+0x88>
+            pmac_info = pmac_group->pmac_info[j];
+ 8018c5c:	e0fffd17 	ldw	r3,-12(fp)
+ 8018c60:	e0bffe17 	ldw	r2,-8(fp)
+ 8018c64:	10800044 	addi	r2,r2,1
+ 8018c68:	100490ba 	slli	r2,r2,2
+ 8018c6c:	1885883a 	add	r2,r3,r2
+ 8018c70:	10800017 	ldw	r2,0(r2)
+ 8018c74:	e0bffc15 	stw	r2,-16(fp)
+            if(((np_tse_mac *) pmac_info->psys_info->tse_mac_base) == pmac) {
+ 8018c78:	e0bffc17 	ldw	r2,-16(fp)
+ 8018c7c:	10800217 	ldw	r2,8(r2)
+ 8018c80:	10800017 	ldw	r2,0(r2)
+ 8018c84:	1007883a 	mov	r3,r2
+ 8018c88:	e0bffb17 	ldw	r2,-20(fp)
+ 8018c8c:	10c0021e 	bne	r2,r3,8018c98 <alt_tse_get_mac_info+0x7c>
+                return pmac_info;
+ 8018c90:	e0bffc17 	ldw	r2,-16(fp)
+ 8018c94:	00001006 	br	8018cd8 <alt_tse_get_mac_info+0xbc>
+        for(j = 0; j < pmac_group->channel; j++) {
+ 8018c98:	e0bffe17 	ldw	r2,-8(fp)
+ 8018c9c:	10800044 	addi	r2,r2,1
+ 8018ca0:	e0bffe15 	stw	r2,-8(fp)
+ 8018ca4:	e0bffd17 	ldw	r2,-12(fp)
+ 8018ca8:	10800003 	ldbu	r2,0(r2)
+ 8018cac:	10803fcc 	andi	r2,r2,255
+ 8018cb0:	e0fffe17 	ldw	r3,-8(fp)
+ 8018cb4:	18bfe916 	blt	r3,r2,8018c5c <alt_tse_get_mac_info+0x40>
+    for(i = 0; i < mac_group_count; i++) {
+ 8018cb8:	e0bfff17 	ldw	r2,-4(fp)
+ 8018cbc:	10800044 	addi	r2,r2,1
+ 8018cc0:	e0bfff15 	stw	r2,-4(fp)
+ 8018cc4:	d0a05b43 	ldbu	r2,-32403(gp)
+ 8018cc8:	10803fcc 	andi	r2,r2,255
+ 8018ccc:	e0ffff17 	ldw	r3,-4(fp)
+ 8018cd0:	18bfda16 	blt	r3,r2,8018c3c <alt_tse_get_mac_info+0x20>
+            }
+        }        
+    }
+    
+    return 0;
+ 8018cd4:	0005883a 	mov	r2,zero
+}
+ 8018cd8:	e037883a 	mov	sp,fp
+ 8018cdc:	df000017 	ldw	fp,0(sp)
+ 8018ce0:	dec00104 	addi	sp,sp,4
+ 8018ce4:	f800283a 	ret
+
+08018ce8 <alt_tse_mac_set_speed>:
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps
+ * @return ENP_PARAM if invalid speed specified, else return SUCCESS
+ */
+alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed)
+{
+ 8018ce8:	defffc04 	addi	sp,sp,-16
+ 8018cec:	df000315 	stw	fp,12(sp)
+ 8018cf0:	df000304 	addi	fp,sp,12
+ 8018cf4:	e13ffe15 	stw	r4,-8(fp)
+ 8018cf8:	2805883a 	mov	r2,r5
+ 8018cfc:	e0bffd05 	stb	r2,-12(fp)
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+ 8018d00:	e0bffe17 	ldw	r2,-8(fp)
+ 8018d04:	10800204 	addi	r2,r2,8
+ 8018d08:	10800037 	ldwio	r2,0(r2)
+ 8018d0c:	e0bfff15 	stw	r2,-4(fp)
+  
+  /* 1000 Mbps */
+  if(speed == TSE_PHY_SPEED_1000) {
+ 8018d10:	e0bffd03 	ldbu	r2,-12(fp)
+ 8018d14:	10800098 	cmpnei	r2,r2,2
+ 8018d18:	1000091e 	bne	r2,zero,8018d40 <alt_tse_mac_set_speed+0x58>
+    helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8018d1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8018d20:	10800214 	ori	r2,r2,8
+ 8018d24:	e0bfff15 	stw	r2,-4(fp)
+    helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8018d28:	e0ffff17 	ldw	r3,-4(fp)
+ 8018d2c:	00bf8034 	movhi	r2,65024
+ 8018d30:	10bfffc4 	addi	r2,r2,-1
+ 8018d34:	1884703a 	and	r2,r3,r2
+ 8018d38:	e0bfff15 	stw	r2,-4(fp)
+ 8018d3c:	00001906 	br	8018da4 <alt_tse_mac_set_speed+0xbc>
+  }
+  /* 100 Mbps */
+  else if(speed == TSE_PHY_SPEED_100) {
+ 8018d40:	e0bffd03 	ldbu	r2,-12(fp)
+ 8018d44:	10800058 	cmpnei	r2,r2,1
+ 8018d48:	10000a1e 	bne	r2,zero,8018d74 <alt_tse_mac_set_speed+0x8c>
+    helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8018d4c:	e0ffff17 	ldw	r3,-4(fp)
+ 8018d50:	00bffdc4 	movi	r2,-9
+ 8018d54:	1884703a 	and	r2,r3,r2
+ 8018d58:	e0bfff15 	stw	r2,-4(fp)
+    helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8018d5c:	e0ffff17 	ldw	r3,-4(fp)
+ 8018d60:	00bf8034 	movhi	r2,65024
+ 8018d64:	10bfffc4 	addi	r2,r2,-1
+ 8018d68:	1884703a 	and	r2,r3,r2
+ 8018d6c:	e0bfff15 	stw	r2,-4(fp)
+ 8018d70:	00000c06 	br	8018da4 <alt_tse_mac_set_speed+0xbc>
+  }
+  /* 10 Mbps */
+  else if(speed == TSE_PHY_SPEED_10) {
+ 8018d74:	e0bffd03 	ldbu	r2,-12(fp)
+ 8018d78:	1000081e 	bne	r2,zero,8018d9c <alt_tse_mac_set_speed+0xb4>
+    helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8018d7c:	e0ffff17 	ldw	r3,-4(fp)
+ 8018d80:	00bffdc4 	movi	r2,-9
+ 8018d84:	1884703a 	and	r2,r3,r2
+ 8018d88:	e0bfff15 	stw	r2,-4(fp)
+    helpvar |= ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8018d8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8018d90:	10808034 	orhi	r2,r2,512
+ 8018d94:	e0bfff15 	stw	r2,-4(fp)
+ 8018d98:	00000206 	br	8018da4 <alt_tse_mac_set_speed+0xbc>
+  }  
+  else {
+    return ENP_PARAM;
+ 8018d9c:	00bffd84 	movi	r2,-10
+ 8018da0:	00000506 	br	8018db8 <alt_tse_mac_set_speed+0xd0>
+  }
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar);
+ 8018da4:	e0bffe17 	ldw	r2,-8(fp)
+ 8018da8:	10800204 	addi	r2,r2,8
+ 8018dac:	e0ffff17 	ldw	r3,-4(fp)
+ 8018db0:	10c00035 	stwio	r3,0(r2)
+  return SUCCESS;
+ 8018db4:	0005883a 	mov	r2,zero
+}
+ 8018db8:	e037883a 	mov	sp,fp
+ 8018dbc:	df000017 	ldw	fp,0(sp)
+ 8018dc0:	dec00104 	addi	sp,sp,4
+ 8018dc4:	f800283a 	ret
+
+08018dc8 <alt_tse_mac_set_duplex>:
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param duplex 1 = Full Duplex, 0 = Half Duplex
+ * @return ENP_PARAM if invalid duplex specified, else return SUCCESS
+ */
+alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex)
+{
+ 8018dc8:	defffc04 	addi	sp,sp,-16
+ 8018dcc:	df000315 	stw	fp,12(sp)
+ 8018dd0:	df000304 	addi	fp,sp,12
+ 8018dd4:	e13ffe15 	stw	r4,-8(fp)
+ 8018dd8:	2805883a 	mov	r2,r5
+ 8018ddc:	e0bffd05 	stb	r2,-12(fp)
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+ 8018de0:	e0bffe17 	ldw	r2,-8(fp)
+ 8018de4:	10800204 	addi	r2,r2,8
+ 8018de8:	10800037 	ldwio	r2,0(r2)
+ 8018dec:	e0bfff15 	stw	r2,-4(fp)
+  
+  /* Half Duplex */
+  if(duplex == TSE_PHY_DUPLEX_HALF) {
+ 8018df0:	e0bffd03 	ldbu	r2,-12(fp)
+ 8018df4:	1000041e 	bne	r2,zero,8018e08 <alt_tse_mac_set_duplex+0x40>
+    helpvar |= ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+ 8018df8:	e0bfff17 	ldw	r2,-4(fp)
+ 8018dfc:	10810014 	ori	r2,r2,1024
+ 8018e00:	e0bfff15 	stw	r2,-4(fp)
+ 8018e04:	00000a06 	br	8018e30 <alt_tse_mac_set_duplex+0x68>
+  } 
+  /* Full Duplex */
+  else if(duplex == TSE_PHY_DUPLEX_FULL) {
+ 8018e08:	e0bffd03 	ldbu	r2,-12(fp)
+ 8018e0c:	10800058 	cmpnei	r2,r2,1
+ 8018e10:	1000051e 	bne	r2,zero,8018e28 <alt_tse_mac_set_duplex+0x60>
+    helpvar &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+ 8018e14:	e0ffff17 	ldw	r3,-4(fp)
+ 8018e18:	00beffc4 	movi	r2,-1025
+ 8018e1c:	1884703a 	and	r2,r3,r2
+ 8018e20:	e0bfff15 	stw	r2,-4(fp)
+ 8018e24:	00000206 	br	8018e30 <alt_tse_mac_set_duplex+0x68>
+  }
+  else {
+    return ENP_PARAM;
+ 8018e28:	00bffd84 	movi	r2,-10
+ 8018e2c:	00000506 	br	8018e44 <alt_tse_mac_set_duplex+0x7c>
+  }
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar);
+ 8018e30:	e0bffe17 	ldw	r2,-8(fp)
+ 8018e34:	10800204 	addi	r2,r2,8
+ 8018e38:	e0ffff17 	ldw	r3,-4(fp)
+ 8018e3c:	10c00035 	stwio	r3,0(r2)
+  return SUCCESS;
+ 8018e40:	0005883a 	mov	r2,zero
+
+}
+ 8018e44:	e037883a 	mov	sp,fp
+ 8018e48:	df000017 	ldw	fp,0(sp)
+ 8018e4c:	dec00104 	addi	sp,sp,4
+ 8018e50:	f800283a 	ret
+
+08018e54 <getPHYSpeed>:
+      (((speed == TSE_PHY_SPEED_1000) ? 1 : 0) << 1) |   \
+    (((speed == TSE_PHY_SPEED_100) ? 1 : 0) << 2) |     \
+    (((speed == TSE_PHY_SPEED_10) ? 1 : 0) << 3) |      \
+    ((speed == TSE_PHY_SPEED_INVALID) ? ALT_TSE_E_INVALID_SPEED : 0))
+  
+alt_32 getPHYSpeed(np_tse_mac *pmac) {
+ 8018e54:	defff404 	addi	sp,sp,-48
+ 8018e58:	dfc00b15 	stw	ra,44(sp)
+ 8018e5c:	df000a15 	stw	fp,40(sp)
+ 8018e60:	df000a04 	addi	fp,sp,40
+ 8018e64:	e13ff715 	stw	r4,-36(fp)
+
+    alt_u8 speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 8018e68:	00800044 	movi	r2,1
+ 8018e6c:	e0bffec5 	stb	r2,-5(fp)
+    alt_u8 duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;     /* 1 = full ; 0 = half*/
+ 8018e70:	00800044 	movi	r2,1
+ 8018e74:	e0bffe85 	stb	r2,-6(fp)
+    alt_32 result = ALT_TSE_SPEED_DUPLEX(speed, duplex);
+ 8018e78:	e0bffe83 	ldbu	r2,-6(fp)
+ 8018e7c:	10c0004c 	andi	r3,r2,1
+ 8018e80:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018e84:	10800098 	cmpnei	r2,r2,2
+ 8018e88:	1000021e 	bne	r2,zero,8018e94 <getPHYSpeed+0x40>
+ 8018e8c:	00800084 	movi	r2,2
+ 8018e90:	00000106 	br	8018e98 <getPHYSpeed+0x44>
+ 8018e94:	0005883a 	mov	r2,zero
+ 8018e98:	10c6b03a 	or	r3,r2,r3
+ 8018e9c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018ea0:	10800058 	cmpnei	r2,r2,1
+ 8018ea4:	1000021e 	bne	r2,zero,8018eb0 <getPHYSpeed+0x5c>
+ 8018ea8:	00800104 	movi	r2,4
+ 8018eac:	00000106 	br	8018eb4 <getPHYSpeed+0x60>
+ 8018eb0:	0005883a 	mov	r2,zero
+ 8018eb4:	10c6b03a 	or	r3,r2,r3
+ 8018eb8:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018ebc:	1000021e 	bne	r2,zero,8018ec8 <getPHYSpeed+0x74>
+ 8018ec0:	00800204 	movi	r2,8
+ 8018ec4:	00000106 	br	8018ecc <getPHYSpeed+0x78>
+ 8018ec8:	0005883a 	mov	r2,zero
+ 8018ecc:	10c6b03a 	or	r3,r2,r3
+ 8018ed0:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018ed4:	108000d8 	cmpnei	r2,r2,3
+ 8018ed8:	1000021e 	bne	r2,zero,8018ee4 <getPHYSpeed+0x90>
+ 8018edc:	00800074 	movhi	r2,1
+ 8018ee0:	00000106 	br	8018ee8 <getPHYSpeed+0x94>
+ 8018ee4:	0005883a 	mov	r2,zero
+ 8018ee8:	10c4b03a 	or	r2,r2,r3
+ 8018eec:	e0bfff15 	stw	r2,-4(fp)
+    
+    alt_tse_phy_info *pphy = 0;
+ 8018ef0:	e03ffd15 	stw	zero,-12(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 8018ef4:	e03ffc15 	stw	zero,-16(fp)
+    alt_tse_mac_group *pmac_group = 0;
+ 8018ef8:	e03ffb15 	stw	zero,-20(fp)
+    alt_tse_system_info *psys = 0;
+ 8018efc:	e03ffa15 	stw	zero,-24(fp)
+    
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+ 8018f00:	e03ff9c5 	stb	zero,-25(fp)
+    alt_8 mac_group_index = 0;
+ 8018f04:	e03ff985 	stb	zero,-26(fp)
+    
+    /* initialized PHYs only once */
+    static alt_u8 is_init = 0;
+    if(is_init == 0) {
+ 8018f08:	d0a05bc3 	ldbu	r2,-32401(gp)
+ 8018f0c:	10803fcc 	andi	r2,r2,255
+ 8018f10:	1000031e 	bne	r2,zero,8018f20 <getPHYSpeed+0xcc>
+        alt_tse_phy_init();
+ 8018f14:	801ae0c0 	call	801ae0c <alt_tse_phy_init>
+        is_init = 1;
+ 8018f18:	00800044 	movi	r2,1
+ 8018f1c:	d0a05bc5 	stb	r2,-32401(gp)
+    }
+    
+    /* Look for pmac_group and pmac_info structure based on pmac or iface */
+    pmac_info = alt_tse_get_mac_info(pmac);
+ 8018f20:	e13ff717 	ldw	r4,-36(fp)
+ 8018f24:	8018c1c0 	call	8018c1c <alt_tse_get_mac_info>
+ 8018f28:	e0bffc15 	stw	r2,-16(fp)
+    
+    if(pmac_info == 0) {
+ 8018f2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8018f30:	1000481e 	bne	r2,zero,8019054 <getPHYSpeed+0x200>
+        speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 8018f34:	00800044 	movi	r2,1
+ 8018f38:	e0bffec5 	stb	r2,-5(fp)
+        duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 8018f3c:	00800044 	movi	r2,1
+ 8018f40:	e0bffe85 	stb	r2,-6(fp)
+        result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PMAC_FOUND;
+ 8018f44:	e0bffe83 	ldbu	r2,-6(fp)
+ 8018f48:	10c0004c 	andi	r3,r2,1
+ 8018f4c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018f50:	10800098 	cmpnei	r2,r2,2
+ 8018f54:	1000021e 	bne	r2,zero,8018f60 <getPHYSpeed+0x10c>
+ 8018f58:	00800084 	movi	r2,2
+ 8018f5c:	00000106 	br	8018f64 <getPHYSpeed+0x110>
+ 8018f60:	0005883a 	mov	r2,zero
+ 8018f64:	10c6b03a 	or	r3,r2,r3
+ 8018f68:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018f6c:	10800058 	cmpnei	r2,r2,1
+ 8018f70:	1000021e 	bne	r2,zero,8018f7c <getPHYSpeed+0x128>
+ 8018f74:	00800104 	movi	r2,4
+ 8018f78:	00000106 	br	8018f80 <getPHYSpeed+0x12c>
+ 8018f7c:	0005883a 	mov	r2,zero
+ 8018f80:	10c6b03a 	or	r3,r2,r3
+ 8018f84:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018f88:	1000021e 	bne	r2,zero,8018f94 <getPHYSpeed+0x140>
+ 8018f8c:	00800204 	movi	r2,8
+ 8018f90:	00000106 	br	8018f98 <getPHYSpeed+0x144>
+ 8018f94:	0005883a 	mov	r2,zero
+ 8018f98:	10c6b03a 	or	r3,r2,r3
+ 8018f9c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018fa0:	108000d8 	cmpnei	r2,r2,3
+ 8018fa4:	1000021e 	bne	r2,zero,8018fb0 <getPHYSpeed+0x15c>
+ 8018fa8:	00800074 	movhi	r2,1
+ 8018fac:	00000106 	br	8018fb4 <getPHYSpeed+0x160>
+ 8018fb0:	0005883a 	mov	r2,zero
+ 8018fb4:	10c4b03a 	or	r2,r2,r3
+ 8018fb8:	10802034 	orhi	r2,r2,128
+ 8018fbc:	e0bfff15 	stw	r2,-4(fp)
+        tse_dprintf(2, "ERROR   : [getPHYSpeed] pmac not found from list of pmac_info[]! Speed = %s Mbps, Duplex = %s\n", speed == TSE_PHY_SPEED_1000 ? "1000" :
+ 8018fc0:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018fc4:	108000a0 	cmpeqi	r2,r2,2
+ 8018fc8:	10000e1e 	bne	r2,zero,8019004 <getPHYSpeed+0x1b0>
+ 8018fcc:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018fd0:	10800060 	cmpeqi	r2,r2,1
+ 8018fd4:	1000081e 	bne	r2,zero,8018ff8 <getPHYSpeed+0x1a4>
+ 8018fd8:	e0bffec3 	ldbu	r2,-5(fp)
+ 8018fdc:	1000031e 	bne	r2,zero,8018fec <getPHYSpeed+0x198>
+ 8018fe0:	00820134 	movhi	r2,2052
+ 8018fe4:	109f4c04 	addi	r2,r2,32048
+ 8018fe8:	00000806 	br	801900c <getPHYSpeed+0x1b8>
+ 8018fec:	00820134 	movhi	r2,2052
+ 8018ff0:	109f4d04 	addi	r2,r2,32052
+ 8018ff4:	00000506 	br	801900c <getPHYSpeed+0x1b8>
+ 8018ff8:	00820134 	movhi	r2,2052
+ 8018ffc:	109f4f04 	addi	r2,r2,32060
+ 8019000:	00000206 	br	801900c <getPHYSpeed+0x1b8>
+ 8019004:	00820134 	movhi	r2,2052
+ 8019008:	109f5004 	addi	r2,r2,32064
+ 801900c:	e0fffe83 	ldbu	r3,-6(fp)
+ 8019010:	18c00058 	cmpnei	r3,r3,1
+ 8019014:	1800031e 	bne	r3,zero,8019024 <getPHYSpeed+0x1d0>
+ 8019018:	00c20134 	movhi	r3,2052
+ 801901c:	18df5204 	addi	r3,r3,32072
+ 8019020:	00000206 	br	801902c <getPHYSpeed+0x1d8>
+ 8019024:	00c20134 	movhi	r3,2052
+ 8019028:	18df5404 	addi	r3,r3,32080
+ 801902c:	180d883a 	mov	r6,r3
+ 8019030:	100b883a 	mov	r5,r2
+ 8019034:	01020134 	movhi	r4,2052
+ 8019038:	211f5604 	addi	r4,r4,32088
+ 801903c:	8002c780 	call	8002c78 <printf>
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+        tse_dprintf(2, "ERROR   : [getPHYSpeed] Please define tse_mac_device[] correctly\n");
+ 8019040:	01020134 	movhi	r4,2052
+ 8019044:	211f6e04 	addi	r4,r4,32184
+ 8019048:	8002d9c0 	call	8002d9c <puts>
+        return result;
+ 801904c:	e0bfff17 	ldw	r2,-4(fp)
+ 8019050:	00021906 	br	80198b8 <getPHYSpeed+0xa64>
+    }
+    
+    pphy = pmac_info->pphy_info;
+ 8019054:	e0bffc17 	ldw	r2,-16(fp)
+ 8019058:	10800117 	ldw	r2,4(r2)
+ 801905c:	e0bffd15 	stw	r2,-12(fp)
+    pmac_group = pmac_info->pmac_group;
+ 8019060:	e0bffc17 	ldw	r2,-16(fp)
+ 8019064:	10800317 	ldw	r2,12(r2)
+ 8019068:	e0bffb15 	stw	r2,-20(fp)
+    psys = pmac_info->psys_info;
+ 801906c:	e0bffc17 	ldw	r2,-16(fp)
+ 8019070:	10800217 	ldw	r2,8(r2)
+ 8019074:	e0bffa15 	stw	r2,-24(fp)
+    
+    mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 8019078:	e13ffc17 	ldw	r4,-16(fp)
+ 801907c:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 8019080:	e0bff9c5 	stb	r2,-25(fp)
+    mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 8019084:	e13ffb17 	ldw	r4,-20(fp)
+ 8019088:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801908c:	e0bff985 	stb	r2,-26(fp)
+         
+    /* MDIO is not used */
+    if (pmac_group->pmac_info[0]->psys_info->tse_use_mdio == 0)
+ 8019090:	e0bffb17 	ldw	r2,-20(fp)
+ 8019094:	10800117 	ldw	r2,4(r2)
+ 8019098:	10800217 	ldw	r2,8(r2)
+ 801909c:	10800303 	ldbu	r2,12(r2)
+ 80190a0:	10803fcc 	andi	r2,r2,255
+ 80190a4:	10005a1e 	bne	r2,zero,8019210 <getPHYSpeed+0x3bc>
+    {
+        speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 80190a8:	00800044 	movi	r2,1
+ 80190ac:	e0bffec5 	stb	r2,-5(fp)
+        duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 80190b0:	00800044 	movi	r2,1
+ 80190b4:	e0bffe85 	stb	r2,-6(fp)
+        result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_MDIO;
+ 80190b8:	e0bffe83 	ldbu	r2,-6(fp)
+ 80190bc:	10c0004c 	andi	r3,r2,1
+ 80190c0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80190c4:	10800098 	cmpnei	r2,r2,2
+ 80190c8:	1000021e 	bne	r2,zero,80190d4 <getPHYSpeed+0x280>
+ 80190cc:	00800084 	movi	r2,2
+ 80190d0:	00000106 	br	80190d8 <getPHYSpeed+0x284>
+ 80190d4:	0005883a 	mov	r2,zero
+ 80190d8:	10c6b03a 	or	r3,r2,r3
+ 80190dc:	e0bffec3 	ldbu	r2,-5(fp)
+ 80190e0:	10800058 	cmpnei	r2,r2,1
+ 80190e4:	1000021e 	bne	r2,zero,80190f0 <getPHYSpeed+0x29c>
+ 80190e8:	00800104 	movi	r2,4
+ 80190ec:	00000106 	br	80190f4 <getPHYSpeed+0x2a0>
+ 80190f0:	0005883a 	mov	r2,zero
+ 80190f4:	10c6b03a 	or	r3,r2,r3
+ 80190f8:	e0bffec3 	ldbu	r2,-5(fp)
+ 80190fc:	1000021e 	bne	r2,zero,8019108 <getPHYSpeed+0x2b4>
+ 8019100:	00800204 	movi	r2,8
+ 8019104:	00000106 	br	801910c <getPHYSpeed+0x2b8>
+ 8019108:	0005883a 	mov	r2,zero
+ 801910c:	10c6b03a 	or	r3,r2,r3
+ 8019110:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019114:	108000d8 	cmpnei	r2,r2,3
+ 8019118:	1000021e 	bne	r2,zero,8019124 <getPHYSpeed+0x2d0>
+ 801911c:	00800074 	movhi	r2,1
+ 8019120:	00000106 	br	8019128 <getPHYSpeed+0x2d4>
+ 8019124:	0005883a 	mov	r2,zero
+ 8019128:	10c4b03a 	or	r2,r2,r3
+ 801912c:	10801034 	orhi	r2,r2,64
+ 8019130:	e0bfff15 	stw	r2,-4(fp)
+        usleep(ALTERA_NOMDIO_TIMEOUT_THRESHOLD);
+ 8019134:	010003f4 	movhi	r4,15
+ 8019138:	21109004 	addi	r4,r4,16960
+ 801913c:	803811c0 	call	803811c <usleep>
+        if(psys->tse_phy_cfg) {
+ 8019140:	e0bffa17 	ldw	r2,-24(fp)
+ 8019144:	10801217 	ldw	r2,72(r2)
+ 8019148:	10000d26 	beq	r2,zero,8019180 <getPHYSpeed+0x32c>
+            tse_dprintf(4, "WARNING : PHY[%d.%d] - MDIO not enabled! Running user configuration...\n", mac_group_index, mac_info_index);
+ 801914c:	e0bff987 	ldb	r2,-26(fp)
+ 8019150:	e0fff9c7 	ldb	r3,-25(fp)
+ 8019154:	180d883a 	mov	r6,r3
+ 8019158:	100b883a 	mov	r5,r2
+ 801915c:	01020134 	movhi	r4,2052
+ 8019160:	211f7f04 	addi	r4,r4,32252
+ 8019164:	8002c780 	call	8002c78 <printf>
+            result = psys->tse_phy_cfg(pmac);
+ 8019168:	e0bffa17 	ldw	r2,-24(fp)
+ 801916c:	10801217 	ldw	r2,72(r2)
+ 8019170:	e13ff717 	ldw	r4,-36(fp)
+ 8019174:	103ee83a 	callr	r2
+ 8019178:	e0bfff15 	stw	r2,-4(fp)
+ 801917c:	00002206 	br	8019208 <getPHYSpeed+0x3b4>
+        }
+        else {
+            tse_dprintf(4, "WARNING : MAC Group[%d] - MDIO not enabled! Speed = %s, Duplex = %s\n", mac_group_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+ 8019180:	e13ff987 	ldb	r4,-26(fp)
+ 8019184:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019188:	108000a0 	cmpeqi	r2,r2,2
+ 801918c:	10000e1e 	bne	r2,zero,80191c8 <getPHYSpeed+0x374>
+ 8019190:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019194:	10800060 	cmpeqi	r2,r2,1
+ 8019198:	1000081e 	bne	r2,zero,80191bc <getPHYSpeed+0x368>
+ 801919c:	e0bffec3 	ldbu	r2,-5(fp)
+ 80191a0:	1000031e 	bne	r2,zero,80191b0 <getPHYSpeed+0x35c>
+ 80191a4:	00820134 	movhi	r2,2052
+ 80191a8:	109f4c04 	addi	r2,r2,32048
+ 80191ac:	00000806 	br	80191d0 <getPHYSpeed+0x37c>
+ 80191b0:	00820134 	movhi	r2,2052
+ 80191b4:	109f4d04 	addi	r2,r2,32052
+ 80191b8:	00000506 	br	80191d0 <getPHYSpeed+0x37c>
+ 80191bc:	00820134 	movhi	r2,2052
+ 80191c0:	109f4f04 	addi	r2,r2,32060
+ 80191c4:	00000206 	br	80191d0 <getPHYSpeed+0x37c>
+ 80191c8:	00820134 	movhi	r2,2052
+ 80191cc:	109f5004 	addi	r2,r2,32064
+ 80191d0:	e0fffe83 	ldbu	r3,-6(fp)
+ 80191d4:	18c00058 	cmpnei	r3,r3,1
+ 80191d8:	1800031e 	bne	r3,zero,80191e8 <getPHYSpeed+0x394>
+ 80191dc:	00c20134 	movhi	r3,2052
+ 80191e0:	18df5204 	addi	r3,r3,32072
+ 80191e4:	00000206 	br	80191f0 <getPHYSpeed+0x39c>
+ 80191e8:	00c20134 	movhi	r3,2052
+ 80191ec:	18df5404 	addi	r3,r3,32080
+ 80191f0:	180f883a 	mov	r7,r3
+ 80191f4:	100d883a 	mov	r6,r2
+ 80191f8:	200b883a 	mov	r5,r4
+ 80191fc:	01020134 	movhi	r4,2052
+ 8019200:	211f9104 	addi	r4,r4,32324
+ 8019204:	8002c780 	call	8002c78 <printf>
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+        }
+        return result;
+ 8019208:	e0bfff17 	ldw	r2,-4(fp)
+ 801920c:	0001aa06 	br	80198b8 <getPHYSpeed+0xa64>
+
+    /* Not running simulation */
+    #ifndef ALT_SIM_OPTIMIZE
+    
+        /* These variables declaration are here to avoid "warning: unused variable" message when compile for simulation */
+        np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 8019210:	e0bffb17 	ldw	r2,-20(fp)
+ 8019214:	10800117 	ldw	r2,4(r2)
+ 8019218:	10800217 	ldw	r2,8(r2)
+ 801921c:	10800017 	ldw	r2,0(r2)
+ 8019220:	e0bff815 	stw	r2,-32(fp)
+    
+        /* if no PHY connected to the MAC */
+        if(pphy == 0) {
+ 8019224:	e0bffd17 	ldw	r2,-12(fp)
+ 8019228:	1000491e 	bne	r2,zero,8019350 <getPHYSpeed+0x4fc>
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 801922c:	00800044 	movi	r2,1
+ 8019230:	e0bffec5 	stb	r2,-5(fp)
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 8019234:	00800044 	movi	r2,1
+ 8019238:	e0bffe85 	stb	r2,-6(fp)
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY;
+ 801923c:	e0bffe83 	ldbu	r2,-6(fp)
+ 8019240:	10c0004c 	andi	r3,r2,1
+ 8019244:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019248:	10800098 	cmpnei	r2,r2,2
+ 801924c:	1000021e 	bne	r2,zero,8019258 <getPHYSpeed+0x404>
+ 8019250:	00800084 	movi	r2,2
+ 8019254:	00000106 	br	801925c <getPHYSpeed+0x408>
+ 8019258:	0005883a 	mov	r2,zero
+ 801925c:	10c6b03a 	or	r3,r2,r3
+ 8019260:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019264:	10800058 	cmpnei	r2,r2,1
+ 8019268:	1000021e 	bne	r2,zero,8019274 <getPHYSpeed+0x420>
+ 801926c:	00800104 	movi	r2,4
+ 8019270:	00000106 	br	8019278 <getPHYSpeed+0x424>
+ 8019274:	0005883a 	mov	r2,zero
+ 8019278:	10c6b03a 	or	r3,r2,r3
+ 801927c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019280:	1000021e 	bne	r2,zero,801928c <getPHYSpeed+0x438>
+ 8019284:	00800204 	movi	r2,8
+ 8019288:	00000106 	br	8019290 <getPHYSpeed+0x43c>
+ 801928c:	0005883a 	mov	r2,zero
+ 8019290:	10c6b03a 	or	r3,r2,r3
+ 8019294:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019298:	108000d8 	cmpnei	r2,r2,3
+ 801929c:	1000021e 	bne	r2,zero,80192a8 <getPHYSpeed+0x454>
+ 80192a0:	00800074 	movhi	r2,1
+ 80192a4:	00000106 	br	80192ac <getPHYSpeed+0x458>
+ 80192a8:	0005883a 	mov	r2,zero
+ 80192ac:	10c4b03a 	or	r2,r2,r3
+ 80192b0:	10800834 	orhi	r2,r2,32
+ 80192b4:	e0bfff15 	stw	r2,-4(fp)
+            tse_dprintf(2, "ERROR   : PHY[%d.%d] - No PHY connected! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+ 80192b8:	e13ff987 	ldb	r4,-26(fp)
+ 80192bc:	e17ff9c7 	ldb	r5,-25(fp)
+ 80192c0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80192c4:	108000a0 	cmpeqi	r2,r2,2
+ 80192c8:	10000e1e 	bne	r2,zero,8019304 <getPHYSpeed+0x4b0>
+ 80192cc:	e0bffec3 	ldbu	r2,-5(fp)
+ 80192d0:	10800060 	cmpeqi	r2,r2,1
+ 80192d4:	1000081e 	bne	r2,zero,80192f8 <getPHYSpeed+0x4a4>
+ 80192d8:	e0bffec3 	ldbu	r2,-5(fp)
+ 80192dc:	1000031e 	bne	r2,zero,80192ec <getPHYSpeed+0x498>
+ 80192e0:	00820134 	movhi	r2,2052
+ 80192e4:	109f4c04 	addi	r2,r2,32048
+ 80192e8:	00000806 	br	801930c <getPHYSpeed+0x4b8>
+ 80192ec:	00820134 	movhi	r2,2052
+ 80192f0:	109f4d04 	addi	r2,r2,32052
+ 80192f4:	00000506 	br	801930c <getPHYSpeed+0x4b8>
+ 80192f8:	00820134 	movhi	r2,2052
+ 80192fc:	109f4f04 	addi	r2,r2,32060
+ 8019300:	00000206 	br	801930c <getPHYSpeed+0x4b8>
+ 8019304:	00820134 	movhi	r2,2052
+ 8019308:	109f5004 	addi	r2,r2,32064
+ 801930c:	e0fffe83 	ldbu	r3,-6(fp)
+ 8019310:	18c00058 	cmpnei	r3,r3,1
+ 8019314:	1800031e 	bne	r3,zero,8019324 <getPHYSpeed+0x4d0>
+ 8019318:	00c20134 	movhi	r3,2052
+ 801931c:	18df5204 	addi	r3,r3,32072
+ 8019320:	00000206 	br	801932c <getPHYSpeed+0x4d8>
+ 8019324:	00c20134 	movhi	r3,2052
+ 8019328:	18df5404 	addi	r3,r3,32080
+ 801932c:	d8c00015 	stw	r3,0(sp)
+ 8019330:	100f883a 	mov	r7,r2
+ 8019334:	280d883a 	mov	r6,r5
+ 8019338:	200b883a 	mov	r5,r4
+ 801933c:	01020134 	movhi	r4,2052
+ 8019340:	211fa304 	addi	r4,r4,32396
+ 8019344:	8002c780 	call	8002c78 <printf>
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+            return result;
+ 8019348:	e0bfff17 	ldw	r2,-4(fp)
+ 801934c:	00015a06 	br	80198b8 <getPHYSpeed+0xa64>
+        }
+
+        /* Small MAC */
+        if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) {
+ 8019350:	e0bffc17 	ldw	r2,-16(fp)
+ 8019354:	10800003 	ldbu	r2,0(r2)
+ 8019358:	10803fcc 	andi	r2,r2,255
+ 801935c:	10800058 	cmpnei	r2,r2,1
+ 8019360:	1000071e 	bne	r2,zero,8019380 <getPHYSpeed+0x52c>
+            alt_tse_phy_set_adv_1000(pphy, 0);
+ 8019364:	000b883a 	mov	r5,zero
+ 8019368:	e13ffd17 	ldw	r4,-12(fp)
+ 801936c:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+ 8019370:	01427104 	movi	r5,2500
+ 8019374:	e13ffd17 	ldw	r4,-12(fp)
+ 8019378:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+ 801937c:	00000e06 	br	80193b8 <getPHYSpeed+0x564>
+        }
+        else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) {
+ 8019380:	e0bffc17 	ldw	r2,-16(fp)
+ 8019384:	10800003 	ldbu	r2,0(r2)
+ 8019388:	10803fcc 	andi	r2,r2,255
+ 801938c:	10800098 	cmpnei	r2,r2,2
+ 8019390:	1000091e 	bne	r2,zero,80193b8 <getPHYSpeed+0x564>
+            alt_tse_phy_set_adv_100(pphy, 0);
+ 8019394:	000b883a 	mov	r5,zero
+ 8019398:	e13ffd17 	ldw	r4,-12(fp)
+ 801939c:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 0);
+ 80193a0:	000b883a 	mov	r5,zero
+ 80193a4:	e13ffd17 	ldw	r4,-12(fp)
+ 80193a8:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+            alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+ 80193ac:	01427104 	movi	r5,2500
+ 80193b0:	e13ffd17 	ldw	r4,-12(fp)
+ 80193b4:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+        }
+        
+        /* check link connection for this PHY */
+        if(alt_tse_phy_check_link(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD) == TSE_PHY_AN_NOT_COMPLETE) {
+ 80193b8:	01427104 	movi	r5,2500
+ 80193bc:	e13ffd17 	ldw	r4,-12(fp)
+ 80193c0:	801b0dc0 	call	801b0dc <alt_tse_phy_check_link>
+ 80193c4:	10bfffd8 	cmpnei	r2,r2,-1
+ 80193c8:	1000491e 	bne	r2,zero,80194f0 <getPHYSpeed+0x69c>
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 80193cc:	00800044 	movi	r2,1
+ 80193d0:	e0bffec5 	stb	r2,-5(fp)
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 80193d4:	00800044 	movi	r2,1
+ 80193d8:	e0bffe85 	stb	r2,-6(fp)
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_AN_NOT_COMPLETE;
+ 80193dc:	e0bffe83 	ldbu	r2,-6(fp)
+ 80193e0:	10c0004c 	andi	r3,r2,1
+ 80193e4:	e0bffec3 	ldbu	r2,-5(fp)
+ 80193e8:	10800098 	cmpnei	r2,r2,2
+ 80193ec:	1000021e 	bne	r2,zero,80193f8 <getPHYSpeed+0x5a4>
+ 80193f0:	00800084 	movi	r2,2
+ 80193f4:	00000106 	br	80193fc <getPHYSpeed+0x5a8>
+ 80193f8:	0005883a 	mov	r2,zero
+ 80193fc:	10c6b03a 	or	r3,r2,r3
+ 8019400:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019404:	10800058 	cmpnei	r2,r2,1
+ 8019408:	1000021e 	bne	r2,zero,8019414 <getPHYSpeed+0x5c0>
+ 801940c:	00800104 	movi	r2,4
+ 8019410:	00000106 	br	8019418 <getPHYSpeed+0x5c4>
+ 8019414:	0005883a 	mov	r2,zero
+ 8019418:	10c6b03a 	or	r3,r2,r3
+ 801941c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019420:	1000021e 	bne	r2,zero,801942c <getPHYSpeed+0x5d8>
+ 8019424:	00800204 	movi	r2,8
+ 8019428:	00000106 	br	8019430 <getPHYSpeed+0x5dc>
+ 801942c:	0005883a 	mov	r2,zero
+ 8019430:	10c6b03a 	or	r3,r2,r3
+ 8019434:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019438:	108000d8 	cmpnei	r2,r2,3
+ 801943c:	1000021e 	bne	r2,zero,8019448 <getPHYSpeed+0x5f4>
+ 8019440:	00800074 	movhi	r2,1
+ 8019444:	00000106 	br	801944c <getPHYSpeed+0x5f8>
+ 8019448:	0005883a 	mov	r2,zero
+ 801944c:	10c4b03a 	or	r2,r2,r3
+ 8019450:	10800234 	orhi	r2,r2,8
+ 8019454:	e0bfff15 	stw	r2,-4(fp)
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - Auto-Negotiation not completed! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+ 8019458:	e13ff987 	ldb	r4,-26(fp)
+ 801945c:	e17ff9c7 	ldb	r5,-25(fp)
+ 8019460:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019464:	108000a0 	cmpeqi	r2,r2,2
+ 8019468:	10000e1e 	bne	r2,zero,80194a4 <getPHYSpeed+0x650>
+ 801946c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019470:	10800060 	cmpeqi	r2,r2,1
+ 8019474:	1000081e 	bne	r2,zero,8019498 <getPHYSpeed+0x644>
+ 8019478:	e0bffec3 	ldbu	r2,-5(fp)
+ 801947c:	1000031e 	bne	r2,zero,801948c <getPHYSpeed+0x638>
+ 8019480:	00820134 	movhi	r2,2052
+ 8019484:	109f4c04 	addi	r2,r2,32048
+ 8019488:	00000806 	br	80194ac <getPHYSpeed+0x658>
+ 801948c:	00820134 	movhi	r2,2052
+ 8019490:	109f4d04 	addi	r2,r2,32052
+ 8019494:	00000506 	br	80194ac <getPHYSpeed+0x658>
+ 8019498:	00820134 	movhi	r2,2052
+ 801949c:	109f4f04 	addi	r2,r2,32060
+ 80194a0:	00000206 	br	80194ac <getPHYSpeed+0x658>
+ 80194a4:	00820134 	movhi	r2,2052
+ 80194a8:	109f5004 	addi	r2,r2,32064
+ 80194ac:	e0fffe83 	ldbu	r3,-6(fp)
+ 80194b0:	18c00058 	cmpnei	r3,r3,1
+ 80194b4:	1800031e 	bne	r3,zero,80194c4 <getPHYSpeed+0x670>
+ 80194b8:	00c20134 	movhi	r3,2052
+ 80194bc:	18df5204 	addi	r3,r3,32072
+ 80194c0:	00000206 	br	80194cc <getPHYSpeed+0x678>
+ 80194c4:	00c20134 	movhi	r3,2052
+ 80194c8:	18df5404 	addi	r3,r3,32080
+ 80194cc:	d8c00015 	stw	r3,0(sp)
+ 80194d0:	100f883a 	mov	r7,r2
+ 80194d4:	280d883a 	mov	r6,r5
+ 80194d8:	200b883a 	mov	r5,r4
+ 80194dc:	01020134 	movhi	r4,2052
+ 80194e0:	211fb404 	addi	r4,r4,32464
+ 80194e4:	8002c780 	call	8002c78 <printf>
+                                                                             speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                             speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                             duplex == 1 ? "Full" : "Half");
+            return result;
+ 80194e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80194ec:	0000f206 	br	80198b8 <getPHYSpeed+0xa64>
+        }
+
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, pphy->mdio_address);
+ 80194f0:	e0bff817 	ldw	r2,-32(fp)
+ 80194f4:	10801004 	addi	r2,r2,64
+ 80194f8:	e0fffd17 	ldw	r3,-12(fp)
+ 80194fc:	18c00003 	ldbu	r3,0(r3)
+ 8019500:	18c03fcc 	andi	r3,r3,255
+ 8019504:	10c00035 	stwio	r3,0(r2)
+        /* To enable PHY loopback */
+        #if ENABLE_PHY_LOOPBACK
+            tse_dprintf(5, "INFO    : PHY[%d.%d] - Putting PHY in loopback\n", mac_group_index, mac_info_index);
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 1);   // enable PHY loopback
+        #else
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0);   // disable PHY loopback
+ 8019508:	d8000015 	stw	zero,0(sp)
+ 801950c:	01c00044 	movi	r7,1
+ 8019510:	01800384 	movi	r6,14
+ 8019514:	000b883a 	mov	r5,zero
+ 8019518:	e13ffd17 	ldw	r4,-12(fp)
+ 801951c:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        #endif
+       
+        /* if PHY not found in profile */
+        if(pphy->pphy_profile == 0) {
+ 8019520:	e0bffd17 	ldw	r2,-12(fp)
+ 8019524:	10800517 	ldw	r2,20(r2)
+ 8019528:	10002b1e 	bne	r2,zero,80195d8 <getPHYSpeed+0x784>
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not found in PHY profile\n", mac_group_index, mac_info_index);
+ 801952c:	e0bff987 	ldb	r2,-26(fp)
+ 8019530:	e0fff9c7 	ldb	r3,-25(fp)
+ 8019534:	180d883a 	mov	r6,r3
+ 8019538:	100b883a 	mov	r5,r2
+ 801953c:	01020134 	movhi	r4,2052
+ 8019540:	211fc804 	addi	r4,r4,32544
+ 8019544:	8002c780 	call	8002c78 <printf>
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 8019548:	00800044 	movi	r2,1
+ 801954c:	e0bffec5 	stb	r2,-5(fp)
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 8019550:	00800044 	movi	r2,1
+ 8019554:	e0bffe85 	stb	r2,-6(fp)
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY_PROFILE;
+ 8019558:	e0bffe83 	ldbu	r2,-6(fp)
+ 801955c:	10c0004c 	andi	r3,r2,1
+ 8019560:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019564:	10800098 	cmpnei	r2,r2,2
+ 8019568:	1000021e 	bne	r2,zero,8019574 <getPHYSpeed+0x720>
+ 801956c:	00800084 	movi	r2,2
+ 8019570:	00000106 	br	8019578 <getPHYSpeed+0x724>
+ 8019574:	0005883a 	mov	r2,zero
+ 8019578:	10c6b03a 	or	r3,r2,r3
+ 801957c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019580:	10800058 	cmpnei	r2,r2,1
+ 8019584:	1000021e 	bne	r2,zero,8019590 <getPHYSpeed+0x73c>
+ 8019588:	00800104 	movi	r2,4
+ 801958c:	00000106 	br	8019594 <getPHYSpeed+0x740>
+ 8019590:	0005883a 	mov	r2,zero
+ 8019594:	10c6b03a 	or	r3,r2,r3
+ 8019598:	e0bffec3 	ldbu	r2,-5(fp)
+ 801959c:	1000021e 	bne	r2,zero,80195a8 <getPHYSpeed+0x754>
+ 80195a0:	00800204 	movi	r2,8
+ 80195a4:	00000106 	br	80195ac <getPHYSpeed+0x758>
+ 80195a8:	0005883a 	mov	r2,zero
+ 80195ac:	10c6b03a 	or	r3,r2,r3
+ 80195b0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80195b4:	108000d8 	cmpnei	r2,r2,3
+ 80195b8:	1000021e 	bne	r2,zero,80195c4 <getPHYSpeed+0x770>
+ 80195bc:	00800074 	movhi	r2,1
+ 80195c0:	00000106 	br	80195c8 <getPHYSpeed+0x774>
+ 80195c4:	0005883a 	mov	r2,zero
+ 80195c8:	10c4b03a 	or	r2,r2,r3
+ 80195cc:	10800134 	orhi	r2,r2,4
+ 80195d0:	e0bfff15 	stw	r2,-4(fp)
+ 80195d4:	00009306 	br	8019824 <getPHYSpeed+0x9d0>
+        }
+        // retrieve duplex information from PHY
+        else
+        {
+            if(pphy->pphy_profile->link_status_read)
+ 80195d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80195dc:	10800517 	ldw	r2,20(r2)
+ 80195e0:	10801817 	ldw	r2,96(r2)
+ 80195e4:	10002526 	beq	r2,zero,801967c <getPHYSpeed+0x828>
+            {
+                result = pphy->pphy_profile->link_status_read(pmac_group_base);
+ 80195e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80195ec:	10800517 	ldw	r2,20(r2)
+ 80195f0:	10801817 	ldw	r2,96(r2)
+ 80195f4:	e13ff817 	ldw	r4,-32(fp)
+ 80195f8:	103ee83a 	callr	r2
+ 80195fc:	e0bfff15 	stw	r2,-4(fp)
+                speed = (result & 0x02) ? TSE_PHY_SPEED_1000 :
+ 8019600:	e0bfff17 	ldw	r2,-4(fp)
+ 8019604:	1080008c 	andi	r2,r2,2
+ 8019608:	10000c1e 	bne	r2,zero,801963c <getPHYSpeed+0x7e8>
+                        (result & 0x04) ? TSE_PHY_SPEED_100  :
+ 801960c:	e0bfff17 	ldw	r2,-4(fp)
+ 8019610:	1080010c 	andi	r2,r2,4
+                speed = (result & 0x02) ? TSE_PHY_SPEED_1000 :
+ 8019614:	1000071e 	bne	r2,zero,8019634 <getPHYSpeed+0x7e0>
+                        (result & 0x08) ? TSE_PHY_SPEED_10  : TSE_PHY_SPEED_INVALID;
+ 8019618:	e0bfff17 	ldw	r2,-4(fp)
+ 801961c:	1080020c 	andi	r2,r2,8
+                speed = (result & 0x02) ? TSE_PHY_SPEED_1000 :
+ 8019620:	10000226 	beq	r2,zero,801962c <getPHYSpeed+0x7d8>
+ 8019624:	0005883a 	mov	r2,zero
+ 8019628:	00000506 	br	8019640 <getPHYSpeed+0x7ec>
+ 801962c:	008000c4 	movi	r2,3
+ 8019630:	00000306 	br	8019640 <getPHYSpeed+0x7ec>
+ 8019634:	00800044 	movi	r2,1
+ 8019638:	00000106 	br	8019640 <getPHYSpeed+0x7ec>
+ 801963c:	00800084 	movi	r2,2
+ 8019640:	e0bffec5 	stb	r2,-5(fp)
+                duplex = (result & 0x01) ? TSE_PHY_DUPLEX_FULL : TSE_PHY_DUPLEX_HALF;
+ 8019644:	e0bfff17 	ldw	r2,-4(fp)
+ 8019648:	1080004c 	andi	r2,r2,1
+ 801964c:	e0bffe85 	stb	r2,-6(fp)
+                
+                if(result & ALT_TSE_E_INVALID_SPEED)
+ 8019650:	e0bfff17 	ldw	r2,-4(fp)
+ 8019654:	1080006c 	andhi	r2,r2,1
+ 8019658:	10007226 	beq	r2,zero,8019824 <getPHYSpeed+0x9d0>
+                {
+                    tse_dprintf(3, "WARNING : PHY[%d.%d] - Invalid speed read from PHY\n", mac_group_index, mac_info_index);
+ 801965c:	e0bff987 	ldb	r2,-26(fp)
+ 8019660:	e0fff9c7 	ldb	r3,-25(fp)
+ 8019664:	180d883a 	mov	r6,r3
+ 8019668:	100b883a 	mov	r5,r2
+ 801966c:	01020134 	movhi	r4,2052
+ 8019670:	211fd604 	addi	r4,r4,32600
+ 8019674:	8002c780 	call	8002c78 <printf>
+ 8019678:	00006a06 	br	8019824 <getPHYSpeed+0x9d0>
+                }
+            }
+            else if(pphy->pphy_profile->status_reg_location == 0)
+ 801967c:	e0bffd17 	ldw	r2,-12(fp)
+ 8019680:	10800517 	ldw	r2,20(r2)
+ 8019684:	10801583 	ldbu	r2,86(r2)
+ 8019688:	10803fcc 	andi	r2,r2,255
+ 801968c:	10002b1e 	bne	r2,zero,801973c <getPHYSpeed+0x8e8>
+            {
+                tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY Specific Status register information not provided in profile\n", mac_group_index, mac_info_index);
+ 8019690:	e0bff987 	ldb	r2,-26(fp)
+ 8019694:	e0fff9c7 	ldb	r3,-25(fp)
+ 8019698:	180d883a 	mov	r6,r3
+ 801969c:	100b883a 	mov	r5,r2
+ 80196a0:	01020134 	movhi	r4,2052
+ 80196a4:	211fe304 	addi	r4,r4,32652
+ 80196a8:	8002c780 	call	8002c78 <printf>
+                speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+ 80196ac:	00800044 	movi	r2,1
+ 80196b0:	e0bffec5 	stb	r2,-5(fp)
+                duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+ 80196b4:	00800044 	movi	r2,1
+ 80196b8:	e0bffe85 	stb	r2,-6(fp)
+                result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_PROFILE_INCORRECT_DEFINED;
+ 80196bc:	e0bffe83 	ldbu	r2,-6(fp)
+ 80196c0:	10c0004c 	andi	r3,r2,1
+ 80196c4:	e0bffec3 	ldbu	r2,-5(fp)
+ 80196c8:	10800098 	cmpnei	r2,r2,2
+ 80196cc:	1000021e 	bne	r2,zero,80196d8 <getPHYSpeed+0x884>
+ 80196d0:	00800084 	movi	r2,2
+ 80196d4:	00000106 	br	80196dc <getPHYSpeed+0x888>
+ 80196d8:	0005883a 	mov	r2,zero
+ 80196dc:	10c6b03a 	or	r3,r2,r3
+ 80196e0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80196e4:	10800058 	cmpnei	r2,r2,1
+ 80196e8:	1000021e 	bne	r2,zero,80196f4 <getPHYSpeed+0x8a0>
+ 80196ec:	00800104 	movi	r2,4
+ 80196f0:	00000106 	br	80196f8 <getPHYSpeed+0x8a4>
+ 80196f4:	0005883a 	mov	r2,zero
+ 80196f8:	10c6b03a 	or	r3,r2,r3
+ 80196fc:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019700:	1000021e 	bne	r2,zero,801970c <getPHYSpeed+0x8b8>
+ 8019704:	00800204 	movi	r2,8
+ 8019708:	00000106 	br	8019710 <getPHYSpeed+0x8bc>
+ 801970c:	0005883a 	mov	r2,zero
+ 8019710:	10c6b03a 	or	r3,r2,r3
+ 8019714:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019718:	108000d8 	cmpnei	r2,r2,3
+ 801971c:	1000021e 	bne	r2,zero,8019728 <getPHYSpeed+0x8d4>
+ 8019720:	00800074 	movhi	r2,1
+ 8019724:	00000106 	br	801972c <getPHYSpeed+0x8d8>
+ 8019728:	0005883a 	mov	r2,zero
+ 801972c:	10c4b03a 	or	r2,r2,r3
+ 8019730:	108000b4 	orhi	r2,r2,2
+ 8019734:	e0bfff15 	stw	r2,-4(fp)
+ 8019738:	00003a06 	br	8019824 <getPHYSpeed+0x9d0>
+            }
+            else
+            {
+                /* extract connection speed and duplex information */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2);
+ 801973c:	e0bffd17 	ldw	r2,-12(fp)
+ 8019740:	10800517 	ldw	r2,20(r2)
+ 8019744:	10801583 	ldbu	r2,86(r2)
+ 8019748:	10c03fcc 	andi	r3,r2,255
+ 801974c:	e0bffd17 	ldw	r2,-12(fp)
+ 8019750:	10800517 	ldw	r2,20(r2)
+ 8019754:	108015c3 	ldbu	r2,87(r2)
+ 8019758:	10803fcc 	andi	r2,r2,255
+ 801975c:	01c00084 	movi	r7,2
+ 8019760:	100d883a 	mov	r6,r2
+ 8019764:	180b883a 	mov	r5,r3
+ 8019768:	e13ffd17 	ldw	r4,-12(fp)
+ 801976c:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 8019770:	e0bffec5 	stb	r2,-5(fp)
+                duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1);
+ 8019774:	e0bffd17 	ldw	r2,-12(fp)
+ 8019778:	10800517 	ldw	r2,20(r2)
+ 801977c:	10801583 	ldbu	r2,86(r2)
+ 8019780:	10c03fcc 	andi	r3,r2,255
+ 8019784:	e0bffd17 	ldw	r2,-12(fp)
+ 8019788:	10800517 	ldw	r2,20(r2)
+ 801978c:	10801603 	ldbu	r2,88(r2)
+ 8019790:	10803fcc 	andi	r2,r2,255
+ 8019794:	01c00044 	movi	r7,1
+ 8019798:	100d883a 	mov	r6,r2
+ 801979c:	180b883a 	mov	r5,r3
+ 80197a0:	e13ffd17 	ldw	r4,-12(fp)
+ 80197a4:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 80197a8:	e0bffe85 	stb	r2,-6(fp)
+                
+                result = ALT_TSE_SPEED_DUPLEX(speed, duplex);
+ 80197ac:	e0bffe83 	ldbu	r2,-6(fp)
+ 80197b0:	10c0004c 	andi	r3,r2,1
+ 80197b4:	e0bffec3 	ldbu	r2,-5(fp)
+ 80197b8:	10800098 	cmpnei	r2,r2,2
+ 80197bc:	1000021e 	bne	r2,zero,80197c8 <getPHYSpeed+0x974>
+ 80197c0:	00800084 	movi	r2,2
+ 80197c4:	00000106 	br	80197cc <getPHYSpeed+0x978>
+ 80197c8:	0005883a 	mov	r2,zero
+ 80197cc:	10c6b03a 	or	r3,r2,r3
+ 80197d0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80197d4:	10800058 	cmpnei	r2,r2,1
+ 80197d8:	1000021e 	bne	r2,zero,80197e4 <getPHYSpeed+0x990>
+ 80197dc:	00800104 	movi	r2,4
+ 80197e0:	00000106 	br	80197e8 <getPHYSpeed+0x994>
+ 80197e4:	0005883a 	mov	r2,zero
+ 80197e8:	10c6b03a 	or	r3,r2,r3
+ 80197ec:	e0bffec3 	ldbu	r2,-5(fp)
+ 80197f0:	1000021e 	bne	r2,zero,80197fc <getPHYSpeed+0x9a8>
+ 80197f4:	00800204 	movi	r2,8
+ 80197f8:	00000106 	br	8019800 <getPHYSpeed+0x9ac>
+ 80197fc:	0005883a 	mov	r2,zero
+ 8019800:	10c6b03a 	or	r3,r2,r3
+ 8019804:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019808:	108000d8 	cmpnei	r2,r2,3
+ 801980c:	1000021e 	bne	r2,zero,8019818 <getPHYSpeed+0x9c4>
+ 8019810:	00800074 	movhi	r2,1
+ 8019814:	00000106 	br	801981c <getPHYSpeed+0x9c8>
+ 8019818:	0005883a 	mov	r2,zero
+ 801981c:	10c4b03a 	or	r2,r2,r3
+ 8019820:	e0bfff15 	stw	r2,-4(fp)
+        /* for simulation purpose, default to gigabit mode */
+        speed = 1;
+        duplex = 1;
+    #endif
+
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Speed = %s, Duplex = %s\n",  mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+ 8019824:	e13ff987 	ldb	r4,-26(fp)
+ 8019828:	e17ff9c7 	ldb	r5,-25(fp)
+ 801982c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019830:	108000a0 	cmpeqi	r2,r2,2
+ 8019834:	10000e1e 	bne	r2,zero,8019870 <getPHYSpeed+0xa1c>
+ 8019838:	e0bffec3 	ldbu	r2,-5(fp)
+ 801983c:	10800060 	cmpeqi	r2,r2,1
+ 8019840:	1000081e 	bne	r2,zero,8019864 <getPHYSpeed+0xa10>
+ 8019844:	e0bffec3 	ldbu	r2,-5(fp)
+ 8019848:	1000031e 	bne	r2,zero,8019858 <getPHYSpeed+0xa04>
+ 801984c:	00820134 	movhi	r2,2052
+ 8019850:	109f4c04 	addi	r2,r2,32048
+ 8019854:	00000806 	br	8019878 <getPHYSpeed+0xa24>
+ 8019858:	00820134 	movhi	r2,2052
+ 801985c:	109f4d04 	addi	r2,r2,32052
+ 8019860:	00000506 	br	8019878 <getPHYSpeed+0xa24>
+ 8019864:	00820134 	movhi	r2,2052
+ 8019868:	109f4f04 	addi	r2,r2,32060
+ 801986c:	00000206 	br	8019878 <getPHYSpeed+0xa24>
+ 8019870:	00820134 	movhi	r2,2052
+ 8019874:	109f5004 	addi	r2,r2,32064
+ 8019878:	e0fffe83 	ldbu	r3,-6(fp)
+ 801987c:	18c00058 	cmpnei	r3,r3,1
+ 8019880:	1800031e 	bne	r3,zero,8019890 <getPHYSpeed+0xa3c>
+ 8019884:	00c20134 	movhi	r3,2052
+ 8019888:	18df5204 	addi	r3,r3,32072
+ 801988c:	00000206 	br	8019898 <getPHYSpeed+0xa44>
+ 8019890:	00c20134 	movhi	r3,2052
+ 8019894:	18df5404 	addi	r3,r3,32080
+ 8019898:	d8c00015 	stw	r3,0(sp)
+ 801989c:	100f883a 	mov	r7,r2
+ 80198a0:	280d883a 	mov	r6,r5
+ 80198a4:	200b883a 	mov	r5,r4
+ 80198a8:	01020134 	movhi	r4,2052
+ 80198ac:	211ffa04 	addi	r4,r4,32744
+ 80198b0:	8002c780 	call	8002c78 <printf>
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+
+    return result;
+ 80198b4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80198b8:	e037883a 	mov	sp,fp
+ 80198bc:	dfc00117 	ldw	ra,4(sp)
+ 80198c0:	df000017 	ldw	fp,0(sp)
+ 80198c4:	dec00204 	addi	sp,sp,8
+ 80198c8:	f800283a 	ret
+
+080198cc <alt_tse_phy_rd_mdio_addr>:
+/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy) {
+ 80198cc:	defffd04 	addi	sp,sp,-12
+ 80198d0:	df000215 	stw	fp,8(sp)
+ 80198d4:	df000204 	addi	fp,sp,8
+ 80198d8:	e13ffe15 	stw	r4,-8(fp)
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 80198dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80198e0:	10800617 	ldw	r2,24(r2)
+ 80198e4:	10800317 	ldw	r2,12(r2)
+ 80198e8:	10800117 	ldw	r2,4(r2)
+ 80198ec:	10800217 	ldw	r2,8(r2)
+ 80198f0:	10800017 	ldw	r2,0(r2)
+ 80198f4:	e0bfff15 	stw	r2,-4(fp)
+    return IORD(&pmac_group_base->MDIO_ADDR1, 0);
+ 80198f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80198fc:	10801004 	addi	r2,r2,64
+ 8019900:	10800037 	ldwio	r2,0(r2)
+}
+ 8019904:	e037883a 	mov	sp,fp
+ 8019908:	df000017 	ldw	fp,0(sp)
+ 801990c:	dec00104 	addi	sp,sp,4
+ 8019910:	f800283a 	ret
+
+08019914 <alt_tse_phy_wr_mdio_addr>:
+ * @API Type:           Internal
+ * @param pmac          Pointer to the alt_tse_phy_info structure
+ * @param mdio_address  MDIO address to be written
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address) {
+ 8019914:	defffc04 	addi	sp,sp,-16
+ 8019918:	df000315 	stw	fp,12(sp)
+ 801991c:	df000304 	addi	fp,sp,12
+ 8019920:	e13ffe15 	stw	r4,-8(fp)
+ 8019924:	2805883a 	mov	r2,r5
+ 8019928:	e0bffd05 	stb	r2,-12(fp)
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 801992c:	e0bffe17 	ldw	r2,-8(fp)
+ 8019930:	10800617 	ldw	r2,24(r2)
+ 8019934:	10800317 	ldw	r2,12(r2)
+ 8019938:	10800117 	ldw	r2,4(r2)
+ 801993c:	10800217 	ldw	r2,8(r2)
+ 8019940:	10800017 	ldw	r2,0(r2)
+ 8019944:	e0bfff15 	stw	r2,-4(fp)
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdio_address);
+ 8019948:	e0bfff17 	ldw	r2,-4(fp)
+ 801994c:	10801004 	addi	r2,r2,64
+ 8019950:	e0fffd03 	ldbu	r3,-12(fp)
+ 8019954:	10c00035 	stwio	r3,0(r2)
+    
+    return SUCCESS;
+ 8019958:	0005883a 	mov	r2,zero
+}
+ 801995c:	e037883a 	mov	sp,fp
+ 8019960:	df000017 	ldw	fp,0(sp)
+ 8019964:	dec00104 	addi	sp,sp,4
+ 8019968:	f800283a 	ret
+
+0801996c <alt_tse_phy_wr_mdio_reg>:
+  * @param  bit_length       number of bits to be written to the register.
+  * @param  data             data to be written to the register at specific bit location of register.
+  * @return SUCCESS 
+  */
+alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data)
+{
+ 801996c:	defff604 	addi	sp,sp,-40
+ 8019970:	df000915 	stw	fp,36(sp)
+ 8019974:	df000904 	addi	fp,sp,36
+ 8019978:	e13ffb15 	stw	r4,-20(fp)
+ 801997c:	2807883a 	mov	r3,r5
+ 8019980:	300b883a 	mov	r5,r6
+ 8019984:	3809883a 	mov	r4,r7
+ 8019988:	e0800117 	ldw	r2,4(fp)
+ 801998c:	e0fffa05 	stb	r3,-24(fp)
+ 8019990:	2807883a 	mov	r3,r5
+ 8019994:	e0fff905 	stb	r3,-28(fp)
+ 8019998:	2007883a 	mov	r3,r4
+ 801999c:	e0fff805 	stb	r3,-32(fp)
+ 80199a0:	e0bff70d 	sth	r2,-36(fp)
+    
+    alt_u16 temp_data;
+    alt_u16 bit_mask;
+    alt_32 i;
+    np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 80199a4:	e0bffb17 	ldw	r2,-20(fp)
+ 80199a8:	10800617 	ldw	r2,24(r2)
+ 80199ac:	10800317 	ldw	r2,12(r2)
+ 80199b0:	10800117 	ldw	r2,4(r2)
+ 80199b4:	10800217 	ldw	r2,8(r2)
+ 80199b8:	10800017 	ldw	r2,0(r2)
+ 80199bc:	e0bffd15 	stw	r2,-12(fp)
+    
+    bit_mask = 0x00;
+ 80199c0:	e03fff8d 	sth	zero,-2(fp)
+    /* generate mask consist of bit_length number of 1
+     * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111
+     */
+    for(i = 0; i < bit_length; i++)
+ 80199c4:	e03ffe15 	stw	zero,-8(fp)
+ 80199c8:	00000906 	br	80199f0 <alt_tse_phy_wr_mdio_reg+0x84>
+    {
+        bit_mask <<= 1;
+ 80199cc:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80199d0:	1085883a 	add	r2,r2,r2
+ 80199d4:	e0bfff8d 	sth	r2,-2(fp)
+        bit_mask |= 0x01;        
+ 80199d8:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80199dc:	10800054 	ori	r2,r2,1
+ 80199e0:	e0bfff8d 	sth	r2,-2(fp)
+    for(i = 0; i < bit_length; i++)
+ 80199e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80199e8:	10800044 	addi	r2,r2,1
+ 80199ec:	e0bffe15 	stw	r2,-8(fp)
+ 80199f0:	e0bff803 	ldbu	r2,-32(fp)
+ 80199f4:	e0fffe17 	ldw	r3,-8(fp)
+ 80199f8:	18bff416 	blt	r3,r2,80199cc <alt_tse_phy_wr_mdio_reg+0x60>
+    }
+    
+    /* shifting mask to left by bit_num */
+    bit_mask <<= lsb_num;
+ 80199fc:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8019a00:	e0bff903 	ldbu	r2,-28(fp)
+ 8019a04:	1884983a 	sll	r2,r3,r2
+ 8019a08:	e0bfff8d 	sth	r2,-2(fp)
+
+    /* read register data */
+    temp_data = IORD(&pmac->mdio1, reg_num);
+ 8019a0c:	e0bffd17 	ldw	r2,-12(fp)
+ 8019a10:	1080a004 	addi	r2,r2,640
+ 8019a14:	e0fffa03 	ldbu	r3,-24(fp)
+ 8019a18:	180690ba 	slli	r3,r3,2
+ 8019a1c:	10c5883a 	add	r2,r2,r3
+ 8019a20:	10800037 	ldwio	r2,0(r2)
+ 8019a24:	e0bffc8d 	sth	r2,-14(fp)
+    
+    /* clear bits to be written */
+    temp_data &= ~bit_mask;
+ 8019a28:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8019a2c:	0084303a 	nor	r2,zero,r2
+ 8019a30:	1007883a 	mov	r3,r2
+ 8019a34:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8019a38:	1884703a 	and	r2,r3,r2
+ 8019a3c:	e0bffc8d 	sth	r2,-14(fp)
+    
+    /* OR-ed together corresponding bits data */
+    temp_data |= ((data << lsb_num) & bit_mask);    
+ 8019a40:	e0fff70b 	ldhu	r3,-36(fp)
+ 8019a44:	e0bff903 	ldbu	r2,-28(fp)
+ 8019a48:	1884983a 	sll	r2,r3,r2
+ 8019a4c:	1007883a 	mov	r3,r2
+ 8019a50:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8019a54:	1884703a 	and	r2,r3,r2
+ 8019a58:	1007883a 	mov	r3,r2
+ 8019a5c:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8019a60:	1884b03a 	or	r2,r3,r2
+ 8019a64:	e0bffc8d 	sth	r2,-14(fp)
+    
+    /* write data to MDIO register */
+    IOWR(&pmac->mdio1, reg_num, temp_data);
+ 8019a68:	e0bffd17 	ldw	r2,-12(fp)
+ 8019a6c:	1080a004 	addi	r2,r2,640
+ 8019a70:	e0fffa03 	ldbu	r3,-24(fp)
+ 8019a74:	180690ba 	slli	r3,r3,2
+ 8019a78:	10c5883a 	add	r2,r2,r3
+ 8019a7c:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8019a80:	10c00035 	stwio	r3,0(r2)
+    
+    return SUCCESS;
+ 8019a84:	0005883a 	mov	r2,zero
+    
+}
+ 8019a88:	e037883a 	mov	sp,fp
+ 8019a8c:	df000017 	ldw	fp,0(sp)
+ 8019a90:	dec00104 	addi	sp,sp,4
+ 8019a94:	f800283a 	ret
+
+08019a98 <alt_tse_phy_rd_mdio_reg>:
+ * @param  bit_length       number of bits to be read from the register.
+ * @return data read from MDIO register 
+ */
+
+alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length)
+{
+ 8019a98:	defff704 	addi	sp,sp,-36
+ 8019a9c:	df000815 	stw	fp,32(sp)
+ 8019aa0:	df000804 	addi	fp,sp,32
+ 8019aa4:	e13ffb15 	stw	r4,-20(fp)
+ 8019aa8:	2805883a 	mov	r2,r5
+ 8019aac:	3009883a 	mov	r4,r6
+ 8019ab0:	3807883a 	mov	r3,r7
+ 8019ab4:	e0bffa05 	stb	r2,-24(fp)
+ 8019ab8:	2005883a 	mov	r2,r4
+ 8019abc:	e0bff905 	stb	r2,-28(fp)
+ 8019ac0:	1805883a 	mov	r2,r3
+ 8019ac4:	e0bff805 	stb	r2,-32(fp)
+    alt_u16 temp_data;
+    alt_u32 bit_mask;
+    alt_32 i;
+    np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 8019ac8:	e0bffb17 	ldw	r2,-20(fp)
+ 8019acc:	10800617 	ldw	r2,24(r2)
+ 8019ad0:	10800317 	ldw	r2,12(r2)
+ 8019ad4:	10800117 	ldw	r2,4(r2)
+ 8019ad8:	10800217 	ldw	r2,8(r2)
+ 8019adc:	10800017 	ldw	r2,0(r2)
+ 8019ae0:	e0bffd15 	stw	r2,-12(fp)
+    
+    bit_mask = 0x00;
+ 8019ae4:	e03fff15 	stw	zero,-4(fp)
+    /* generate mask consist of bit_length number of 1
+     * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111
+     */
+    for(i = 0; i < bit_length; i++)
+ 8019ae8:	e03ffe15 	stw	zero,-8(fp)
+ 8019aec:	00000906 	br	8019b14 <alt_tse_phy_rd_mdio_reg+0x7c>
+    {
+        bit_mask <<= 1;
+ 8019af0:	e0bfff17 	ldw	r2,-4(fp)
+ 8019af4:	1085883a 	add	r2,r2,r2
+ 8019af8:	e0bfff15 	stw	r2,-4(fp)
+        bit_mask |= 0x01;        
+ 8019afc:	e0bfff17 	ldw	r2,-4(fp)
+ 8019b00:	10800054 	ori	r2,r2,1
+ 8019b04:	e0bfff15 	stw	r2,-4(fp)
+    for(i = 0; i < bit_length; i++)
+ 8019b08:	e0bffe17 	ldw	r2,-8(fp)
+ 8019b0c:	10800044 	addi	r2,r2,1
+ 8019b10:	e0bffe15 	stw	r2,-8(fp)
+ 8019b14:	e0bff803 	ldbu	r2,-32(fp)
+ 8019b18:	e0fffe17 	ldw	r3,-8(fp)
+ 8019b1c:	18bff416 	blt	r3,r2,8019af0 <alt_tse_phy_rd_mdio_reg+0x58>
+    }
+    
+    /* read register data */
+    temp_data = IORD(&pmac->mdio1, reg_num);
+ 8019b20:	e0bffd17 	ldw	r2,-12(fp)
+ 8019b24:	1080a004 	addi	r2,r2,640
+ 8019b28:	e0fffa03 	ldbu	r3,-24(fp)
+ 8019b2c:	180690ba 	slli	r3,r3,2
+ 8019b30:	10c5883a 	add	r2,r2,r3
+ 8019b34:	10800037 	ldwio	r2,0(r2)
+ 8019b38:	e0bffc8d 	sth	r2,-14(fp)
+    
+    /* shifting read data */
+    temp_data >>= lsb_num;
+ 8019b3c:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8019b40:	e0bff903 	ldbu	r2,-28(fp)
+ 8019b44:	1885d83a 	sra	r2,r3,r2
+ 8019b48:	e0bffc8d 	sth	r2,-14(fp)
+    
+    return (temp_data & bit_mask);
+ 8019b4c:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8019b50:	e0bfff17 	ldw	r2,-4(fp)
+ 8019b54:	1884703a 	and	r2,r3,r2
+}
+ 8019b58:	e037883a 	mov	sp,fp
+ 8019b5c:	df000017 	ldw	fp,0(sp)
+ 8019b60:	dec00104 	addi	sp,sp,4
+ 8019b64:	f800283a 	ret
+
+08019b68 <alt_tse_phy_add_profile_default>:
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ * 
+ * User might add their own PHY by calling alt_tse_phy_add_profile()
+ */
+alt_32 alt_tse_phy_add_profile_default() {
+ 8019b68:	deff8104 	addi	sp,sp,-508
+ 8019b6c:	dfc07e15 	stw	ra,504(sp)
+ 8019b70:	df007d15 	stw	fp,500(sp)
+ 8019b74:	df007d04 	addi	fp,sp,500
+        
+    /* ------------------------------ */
+    /* Marvell PHY on PHYWORKX board  */
+    /* ------------------------------ */
+    
+    alt_tse_phy_profile MV88E1111 = {"Marvell 88E1111",      /* Marvell 88E1111                                  */
+ 8019b78:	e0bfe704 	addi	r2,fp,-100
+ 8019b7c:	00c01904 	movi	r3,100
+ 8019b80:	180d883a 	mov	r6,r3
+ 8019b84:	000b883a 	mov	r5,zero
+ 8019b88:	1009883a 	mov	r4,r2
+ 8019b8c:	80088e40 	call	80088e4 <memset>
+ 8019b90:	009d9cb4 	movhi	r2,30322
+ 8019b94:	10985344 	addi	r2,r2,24909
+ 8019b98:	e0bfe715 	stw	r2,-100(fp)
+ 8019b9c:	00881b34 	movhi	r2,8300
+ 8019ba0:	109b1944 	addi	r2,r2,27749
+ 8019ba4:	e0bfe815 	stw	r2,-96(fp)
+ 8019ba8:	008c5174 	movhi	r2,12613
+ 8019bac:	108e0e04 	addi	r2,r2,14392
+ 8019bb0:	e0bfe915 	stw	r2,-92(fp)
+ 8019bb4:	00800c74 	movhi	r2,49
+ 8019bb8:	108c4c44 	addi	r2,r2,12593
+ 8019bbc:	e0bfea15 	stw	r2,-88(fp)
+ 8019bc0:	e0bfeb04 	addi	r2,fp,-84
+ 8019bc4:	00c01004 	movi	r3,64
+ 8019bc8:	180d883a 	mov	r6,r3
+ 8019bcc:	000b883a 	mov	r5,zero
+ 8019bd0:	1009883a 	mov	r4,r2
+ 8019bd4:	80088e40 	call	80088e4 <memset>
+ 8019bd8:	009410c4 	movi	r2,20547
+ 8019bdc:	e0bffb15 	stw	r2,-20(fp)
+ 8019be0:	00800304 	movi	r2,12
+ 8019be4:	e0bffc05 	stb	r2,-16(fp)
+ 8019be8:	00800084 	movi	r2,2
+ 8019bec:	e0bffc45 	stb	r2,-15(fp)
+ 8019bf0:	00800444 	movi	r2,17
+ 8019bf4:	e0bffc85 	stb	r2,-14(fp)
+ 8019bf8:	00800384 	movi	r2,14
+ 8019bfc:	e0bffcc5 	stb	r2,-13(fp)
+ 8019c00:	00800344 	movi	r2,13
+ 8019c04:	e0bffd05 	stb	r2,-12(fp)
+ 8019c08:	00800284 	movi	r2,10
+ 8019c0c:	e0bffd45 	stb	r2,-11(fp)
+ 8019c10:	008200b4 	movhi	r2,2050
+ 8019c14:	10b15f04 	addi	r2,r2,-14980
+ 8019c18:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* ---------------------------------- */
+    /* Marvell Quad PHY on PHYWORKX board */
+    /* ---------------------------------- */
+    
+    alt_tse_phy_profile MV88E1145 = {"Marvell Quad PHY 88E1145",      /* Marvell 88E1145                                  */
+ 8019c1c:	e0bfce04 	addi	r2,fp,-200
+ 8019c20:	00c01904 	movi	r3,100
+ 8019c24:	180d883a 	mov	r6,r3
+ 8019c28:	000b883a 	mov	r5,zero
+ 8019c2c:	1009883a 	mov	r4,r2
+ 8019c30:	80088e40 	call	80088e4 <memset>
+ 8019c34:	009d9cb4 	movhi	r2,30322
+ 8019c38:	10985344 	addi	r2,r2,24909
+ 8019c3c:	e0bfce15 	stw	r2,-200(fp)
+ 8019c40:	00881b34 	movhi	r2,8300
+ 8019c44:	109b1944 	addi	r2,r2,27749
+ 8019c48:	e0bfcf15 	stw	r2,-196(fp)
+ 8019c4c:	00991874 	movhi	r2,25697
+ 8019c50:	109d5444 	addi	r2,r2,30033
+ 8019c54:	e0bfd015 	stw	r2,-192(fp)
+ 8019c58:	00965234 	movhi	r2,22856
+ 8019c5c:	10940804 	addi	r2,r2,20512
+ 8019c60:	e0bfd115 	stw	r2,-188(fp)
+ 8019c64:	00914e34 	movhi	r2,17720
+ 8019c68:	108e0804 	addi	r2,r2,14368
+ 8019c6c:	e0bfd215 	stw	r2,-184(fp)
+ 8019c70:	008d4d34 	movhi	r2,13620
+ 8019c74:	108c4c44 	addi	r2,r2,12593
+ 8019c78:	e0bfd315 	stw	r2,-180(fp)
+ 8019c7c:	e03fd415 	stw	zero,-176(fp)
+ 8019c80:	e03fd515 	stw	zero,-172(fp)
+ 8019c84:	e03fd615 	stw	zero,-168(fp)
+ 8019c88:	e03fd715 	stw	zero,-164(fp)
+ 8019c8c:	e03fd815 	stw	zero,-160(fp)
+ 8019c90:	e03fd915 	stw	zero,-156(fp)
+ 8019c94:	e03fda15 	stw	zero,-152(fp)
+ 8019c98:	e03fdb15 	stw	zero,-148(fp)
+ 8019c9c:	e03fdc15 	stw	zero,-144(fp)
+ 8019ca0:	e03fdd15 	stw	zero,-140(fp)
+ 8019ca4:	e03fde15 	stw	zero,-136(fp)
+ 8019ca8:	e03fdf15 	stw	zero,-132(fp)
+ 8019cac:	e03fe015 	stw	zero,-128(fp)
+ 8019cb0:	e03fe115 	stw	zero,-124(fp)
+ 8019cb4:	009410c4 	movi	r2,20547
+ 8019cb8:	e0bfe215 	stw	r2,-120(fp)
+ 8019cbc:	00800344 	movi	r2,13
+ 8019cc0:	e0bfe305 	stb	r2,-116(fp)
+ 8019cc4:	00800084 	movi	r2,2
+ 8019cc8:	e0bfe345 	stb	r2,-115(fp)
+ 8019ccc:	00800444 	movi	r2,17
+ 8019cd0:	e0bfe385 	stb	r2,-114(fp)
+ 8019cd4:	00800384 	movi	r2,14
+ 8019cd8:	e0bfe3c5 	stb	r2,-113(fp)
+ 8019cdc:	00800344 	movi	r2,13
+ 8019ce0:	e0bfe405 	stb	r2,-112(fp)
+ 8019ce4:	00800284 	movi	r2,10
+ 8019ce8:	e0bfe445 	stb	r2,-111(fp)
+ 8019cec:	008200b4 	movhi	r2,2050
+ 8019cf0:	10b15f04 	addi	r2,r2,-14980
+ 8019cf4:	e0bfe515 	stw	r2,-108(fp)
+                      
+    /* ------------------------------ */
+    /* National PHY on PHYWORKX board */
+    /* ------------------------------ */  
+    
+    alt_tse_phy_profile DP83865 = {"National DP83865",     /* National DP83865                                 */
+ 8019cf8:	e0bfb504 	addi	r2,fp,-300
+ 8019cfc:	00c01904 	movi	r3,100
+ 8019d00:	180d883a 	mov	r6,r3
+ 8019d04:	000b883a 	mov	r5,zero
+ 8019d08:	1009883a 	mov	r4,r2
+ 8019d0c:	80088e40 	call	80088e4 <memset>
+ 8019d10:	009a5d34 	movhi	r2,26996
+ 8019d14:	10985384 	addi	r2,r2,24910
+ 8019d18:	e0bfb515 	stw	r2,-300(fp)
+ 8019d1c:	009b1874 	movhi	r2,27745
+ 8019d20:	109b9bc4 	addi	r2,r2,28271
+ 8019d24:	e0bfb615 	stw	r2,-296(fp)
+ 8019d28:	008e1434 	movhi	r2,14416
+ 8019d2c:	10910804 	addi	r2,r2,17440
+ 8019d30:	e0bfb715 	stw	r2,-292(fp)
+ 8019d34:	008d4db4 	movhi	r2,13622
+ 8019d38:	108e0cc4 	addi	r2,r2,14387
+ 8019d3c:	e0bfb815 	stw	r2,-288(fp)
+ 8019d40:	e03fb915 	stw	zero,-284(fp)
+ 8019d44:	e0bfba04 	addi	r2,fp,-280
+ 8019d48:	00c00f04 	movi	r3,60
+ 8019d4c:	180d883a 	mov	r6,r3
+ 8019d50:	000b883a 	mov	r5,zero
+ 8019d54:	1009883a 	mov	r4,r2
+ 8019d58:	80088e40 	call	80088e4 <memset>
+ 8019d5c:	00800234 	movhi	r2,8
+ 8019d60:	108005c4 	addi	r2,r2,23
+ 8019d64:	e0bfc915 	stw	r2,-220(fp)
+ 8019d68:	008001c4 	movi	r2,7
+ 8019d6c:	e0bfca05 	stb	r2,-216(fp)
+ 8019d70:	00800284 	movi	r2,10
+ 8019d74:	e0bfca45 	stb	r2,-215(fp)
+ 8019d78:	00800444 	movi	r2,17
+ 8019d7c:	e0bfca85 	stb	r2,-214(fp)
+ 8019d80:	008000c4 	movi	r2,3
+ 8019d84:	e0bfcac5 	stb	r2,-213(fp)
+ 8019d88:	00800044 	movi	r2,1
+ 8019d8c:	e0bfcb05 	stb	r2,-212(fp)
+ 8019d90:	00800084 	movi	r2,2
+ 8019d94:	e0bfcb45 	stb	r2,-211(fp)
+                      
+    /* -------------------------------------- */
+    /* National 10/100 PHY on PHYWORKX board  */
+    /* -------------------------------------- */ 
+                      
+    alt_tse_phy_profile DP83848C = {"National DP83848C",  /* National DP83848C                                          */
+ 8019d98:	e0ff9c04 	addi	r3,fp,-400
+ 8019d9c:	00820174 	movhi	r2,2053
+ 8019da0:	10a00604 	addi	r2,r2,-32744
+ 8019da4:	01001904 	movi	r4,100
+ 8019da8:	200d883a 	mov	r6,r4
+ 8019dac:	100b883a 	mov	r5,r2
+ 8019db0:	1809883a 	mov	r4,r3
+ 8019db4:	80086b80 	call	80086b8 <memcpy>
+
+    /* -------------------------------------- */
+    /* Intel PHY on C10LP EVA board  */
+    /* -------------------------------------- */ 
+                      
+    alt_tse_phy_profile PEF7071 = {"Intel PEF7071",       /* National DP83848C                                          */
+ 8019db8:	e0ff8304 	addi	r3,fp,-500
+ 8019dbc:	00820174 	movhi	r2,2053
+ 8019dc0:	10a01f04 	addi	r2,r2,-32644
+ 8019dc4:	01001904 	movi	r4,100
+ 8019dc8:	200d883a 	mov	r6,r4
+ 8019dcc:	100b883a 	mov	r5,r2
+ 8019dd0:	1809883a 	mov	r4,r3
+ 8019dd4:	80086b80 	call	80086b8 <memcpy>
+                           &PEF7071_config,               /* configure PEF7071                                          */
+                           &PEF7071_link_status_read      /* Function pointer to read from PHY specific status register */           
+                          };
+                      
+    /* add supported PHY to profile */                          
+    alt_tse_phy_add_profile(&MV88E1111);
+ 8019dd8:	e0bfe704 	addi	r2,fp,-100
+ 8019ddc:	1009883a 	mov	r4,r2
+ 8019de0:	8017e840 	call	8017e84 <alt_tse_phy_add_profile>
+    alt_tse_phy_add_profile(&MV88E1145);
+ 8019de4:	e0bfce04 	addi	r2,fp,-200
+ 8019de8:	1009883a 	mov	r4,r2
+ 8019dec:	8017e840 	call	8017e84 <alt_tse_phy_add_profile>
+    alt_tse_phy_add_profile(&DP83865);
+ 8019df0:	e0bfb504 	addi	r2,fp,-300
+ 8019df4:	1009883a 	mov	r4,r2
+ 8019df8:	8017e840 	call	8017e84 <alt_tse_phy_add_profile>
+    alt_tse_phy_add_profile(&DP83848C);
+ 8019dfc:	e0bf9c04 	addi	r2,fp,-400
+ 8019e00:	1009883a 	mov	r4,r2
+ 8019e04:	8017e840 	call	8017e84 <alt_tse_phy_add_profile>
+    alt_tse_phy_add_profile(&PEF7071);
+ 8019e08:	e0bf8304 	addi	r2,fp,-500
+ 8019e0c:	1009883a 	mov	r4,r2
+ 8019e10:	8017e840 	call	8017e84 <alt_tse_phy_add_profile>
+    
+    
+    return phy_profile_count;
+ 8019e14:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8019e18:	10803fcc 	andi	r2,r2,255
+}
+ 8019e1c:	e037883a 	mov	sp,fp
+ 8019e20:	dfc00117 	ldw	ra,4(sp)
+ 8019e24:	df000017 	ldw	fp,0(sp)
+ 8019e28:	dec00204 	addi	sp,sp,8
+ 8019e2c:	f800283a 	ret
+
+08019e30 <alt_tse_phy_print_profile>:
+/* @Function Description: Display PHYs available in profile
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ */
+alt_32 alt_tse_phy_print_profile() {
+ 8019e30:	defffd04 	addi	sp,sp,-12
+ 8019e34:	dfc00215 	stw	ra,8(sp)
+ 8019e38:	df000115 	stw	fp,4(sp)
+ 8019e3c:	df000104 	addi	fp,sp,4
+   
+    alt_8 i;
+    /* display PHY in profile */
+    tse_dprintf(6, "List of PHY profiles supported (Total profiles = %d)...\n", phy_profile_count);
+ 8019e40:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8019e44:	10803fcc 	andi	r2,r2,255
+ 8019e48:	100b883a 	mov	r5,r2
+ 8019e4c:	01020174 	movhi	r4,2053
+ 8019e50:	21203804 	addi	r4,r4,-32544
+ 8019e54:	8002c780 	call	8002c78 <printf>
+    
+    for(i = 0; i < phy_profile_count; i++)
+ 8019e58:	e03fffc5 	stb	zero,-1(fp)
+ 8019e5c:	00005d06 	br	8019fd4 <alt_tse_phy_print_profile+0x1a4>
+    {
+        tse_dprintf(6, "Profile No.%2d   :\n", i);
+ 8019e60:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019e64:	100b883a 	mov	r5,r2
+ 8019e68:	01020174 	movhi	r4,2053
+ 8019e6c:	21204704 	addi	r4,r4,-32484
+ 8019e70:	8002c780 	call	8002c78 <printf>
+        tse_dprintf(6, "PHY Name        : %s\n", pphy_profiles[i]->name);
+ 8019e74:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019e78:	100690ba 	slli	r3,r2,2
+ 8019e7c:	008201b4 	movhi	r2,2054
+ 8019e80:	1885883a 	add	r2,r3,r2
+ 8019e84:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019e88:	100b883a 	mov	r5,r2
+ 8019e8c:	01020174 	movhi	r4,2053
+ 8019e90:	21204c04 	addi	r4,r4,-32464
+ 8019e94:	8002c780 	call	8002c78 <printf>
+   
+        tse_dprintf(6, "PHY OUI         : 0x%06x\n", (int)pphy_profiles[i]->oui);
+ 8019e98:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019e9c:	100690ba 	slli	r3,r2,2
+ 8019ea0:	008201b4 	movhi	r2,2054
+ 8019ea4:	1885883a 	add	r2,r3,r2
+ 8019ea8:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019eac:	10801417 	ldw	r2,80(r2)
+ 8019eb0:	100b883a 	mov	r5,r2
+ 8019eb4:	01020174 	movhi	r4,2053
+ 8019eb8:	21205204 	addi	r4,r4,-32440
+ 8019ebc:	8002c780 	call	8002c78 <printf>
+        tse_dprintf(6, "PHY Model Num.  : 0x%02x\n", pphy_profiles[i]->model_number);
+ 8019ec0:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019ec4:	100690ba 	slli	r3,r2,2
+ 8019ec8:	008201b4 	movhi	r2,2054
+ 8019ecc:	1885883a 	add	r2,r3,r2
+ 8019ed0:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019ed4:	10801503 	ldbu	r2,84(r2)
+ 8019ed8:	10803fcc 	andi	r2,r2,255
+ 8019edc:	100b883a 	mov	r5,r2
+ 8019ee0:	01020174 	movhi	r4,2053
+ 8019ee4:	21205904 	addi	r4,r4,-32412
+ 8019ee8:	8002c780 	call	8002c78 <printf>
+        tse_dprintf(6, "PHY Rev. Num.   : 0x%02x\n", pphy_profiles[i]->revision_number);
+ 8019eec:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019ef0:	100690ba 	slli	r3,r2,2
+ 8019ef4:	008201b4 	movhi	r2,2054
+ 8019ef8:	1885883a 	add	r2,r3,r2
+ 8019efc:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019f00:	10801543 	ldbu	r2,85(r2)
+ 8019f04:	10803fcc 	andi	r2,r2,255
+ 8019f08:	100b883a 	mov	r5,r2
+ 8019f0c:	01020174 	movhi	r4,2053
+ 8019f10:	21206004 	addi	r4,r4,-32384
+ 8019f14:	8002c780 	call	8002c78 <printf>
+        
+        tse_dprintf(6, "Status Register : 0x%02x\n", pphy_profiles[i]->status_reg_location); 
+ 8019f18:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019f1c:	100690ba 	slli	r3,r2,2
+ 8019f20:	008201b4 	movhi	r2,2054
+ 8019f24:	1885883a 	add	r2,r3,r2
+ 8019f28:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019f2c:	10801583 	ldbu	r2,86(r2)
+ 8019f30:	10803fcc 	andi	r2,r2,255
+ 8019f34:	100b883a 	mov	r5,r2
+ 8019f38:	01020174 	movhi	r4,2053
+ 8019f3c:	21206704 	addi	r4,r4,-32356
+ 8019f40:	8002c780 	call	8002c78 <printf>
+        
+        tse_dprintf(6, "Speed Bit       : %d\n", pphy_profiles[i]->speed_lsb_location);
+ 8019f44:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019f48:	100690ba 	slli	r3,r2,2
+ 8019f4c:	008201b4 	movhi	r2,2054
+ 8019f50:	1885883a 	add	r2,r3,r2
+ 8019f54:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019f58:	108015c3 	ldbu	r2,87(r2)
+ 8019f5c:	10803fcc 	andi	r2,r2,255
+ 8019f60:	100b883a 	mov	r5,r2
+ 8019f64:	01020174 	movhi	r4,2053
+ 8019f68:	21206e04 	addi	r4,r4,-32328
+ 8019f6c:	8002c780 	call	8002c78 <printf>
+        
+        tse_dprintf(6, "Duplex Bit      : %d\n", pphy_profiles[i]->duplex_bit_location);
+ 8019f70:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019f74:	100690ba 	slli	r3,r2,2
+ 8019f78:	008201b4 	movhi	r2,2054
+ 8019f7c:	1885883a 	add	r2,r3,r2
+ 8019f80:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019f84:	10801603 	ldbu	r2,88(r2)
+ 8019f88:	10803fcc 	andi	r2,r2,255
+ 8019f8c:	100b883a 	mov	r5,r2
+ 8019f90:	01020174 	movhi	r4,2053
+ 8019f94:	21207404 	addi	r4,r4,-32304
+ 8019f98:	8002c780 	call	8002c78 <printf>
+        
+        tse_dprintf(6, "Link Bit        : %d\n\n", pphy_profiles[i]->link_bit_location);
+ 8019f9c:	e0bfffc7 	ldb	r2,-1(fp)
+ 8019fa0:	100690ba 	slli	r3,r2,2
+ 8019fa4:	008201b4 	movhi	r2,2054
+ 8019fa8:	1885883a 	add	r2,r3,r2
+ 8019fac:	10b5ae17 	ldw	r2,-10568(r2)
+ 8019fb0:	10801643 	ldbu	r2,89(r2)
+ 8019fb4:	10803fcc 	andi	r2,r2,255
+ 8019fb8:	100b883a 	mov	r5,r2
+ 8019fbc:	01020174 	movhi	r4,2053
+ 8019fc0:	21207a04 	addi	r4,r4,-32280
+ 8019fc4:	8002c780 	call	8002c78 <printf>
+    for(i = 0; i < phy_profile_count; i++)
+ 8019fc8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8019fcc:	10800044 	addi	r2,r2,1
+ 8019fd0:	e0bfffc5 	stb	r2,-1(fp)
+ 8019fd4:	e0ffffc7 	ldb	r3,-1(fp)
+ 8019fd8:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8019fdc:	10803fcc 	andi	r2,r2,255
+ 8019fe0:	18bf9f16 	blt	r3,r2,8019e60 <alt_tse_phy_print_profile+0x30>
+ 
+    }
+    
+    return phy_profile_count;
+ 8019fe4:	d0a05b03 	ldbu	r2,-32404(gp)
+ 8019fe8:	10803fcc 	andi	r2,r2,255
+}
+ 8019fec:	e037883a 	mov	sp,fp
+ 8019ff0:	dfc00117 	ldw	ra,4(sp)
+ 8019ff4:	df000017 	ldw	fp,0(sp)
+ 8019ff8:	dec00204 	addi	sp,sp,8
+ 8019ffc:	f800283a 	ret
+
+0801a000 <alt_tse_mac_group_init>:
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      return SUCCESS
+ *              return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error
+ */
+alt_32 alt_tse_mac_group_init() {
+ 801a000:	defffa04 	addi	sp,sp,-24
+ 801a004:	dfc00515 	stw	ra,20(sp)
+ 801a008:	df000415 	stw	fp,16(sp)
+ 801a00c:	df000404 	addi	fp,sp,16
+    
+    alt_8 i;
+    alt_8 j;
+    
+    alt_tse_mac_group *pmac_group = 0;
+ 801a010:	e03ffd15 	stw	zero,-12(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 801a014:	e03fff15 	stw	zero,-4(fp)
+    alt_tse_system_info *psys = 0;
+ 801a018:	e03ffc15 	stw	zero,-16(fp)
+
+    /* reset number of MAC group */
+    mac_group_count = 0;
+ 801a01c:	d0205b45 	stb	zero,-32403(gp)
+    
+    /* loop through every alt_tse_system_info structure */
+    for(i = 0; i < max_mac_system; i++) {
+ 801a020:	e03ffec5 	stb	zero,-5(fp)
+ 801a024:	00019206 	br	801a670 <alt_tse_mac_group_init+0x670>
+        psys = &tse_mac_device[i];
+ 801a028:	e0bffec7 	ldb	r2,-5(fp)
+ 801a02c:	10c01324 	muli	r3,r2,76
+ 801a030:	00820174 	movhi	r2,2053
+ 801a034:	10ae5404 	addi	r2,r2,-18096
+ 801a038:	1885883a 	add	r2,r3,r2
+ 801a03c:	e0bffc15 	stw	r2,-16(fp)
+
+        if((psys->tse_msgdma_tx != 0) && (psys->tse_msgdma_rx != 0)) {        
+ 801a040:	e0bffc17 	ldw	r2,-16(fp)
+ 801a044:	10800617 	ldw	r2,24(r2)
+ 801a048:	10018626 	beq	r2,zero,801a664 <alt_tse_mac_group_init+0x664>
+ 801a04c:	e0bffc17 	ldw	r2,-16(fp)
+ 801a050:	10800717 	ldw	r2,28(r2)
+ 801a054:	10018326 	beq	r2,zero,801a664 <alt_tse_mac_group_init+0x664>
+            tse_dprintf(5, "INFO    : TSE MAC %d found at address 0x%08x\n", mac_group_count, (int) psys->tse_mac_base);
+ 801a058:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801a05c:	10c03fcc 	andi	r3,r2,255
+ 801a060:	e0bffc17 	ldw	r2,-16(fp)
+ 801a064:	10800017 	ldw	r2,0(r2)
+ 801a068:	100d883a 	mov	r6,r2
+ 801a06c:	180b883a 	mov	r5,r3
+ 801a070:	01020174 	movhi	r4,2053
+ 801a074:	21208004 	addi	r4,r4,-32256
+ 801a078:	8002c780 	call	8002c78 <printf>
+            
+            /* Allocate memory for the structure */
+            pmac_group = (alt_tse_mac_group *) malloc(sizeof(alt_tse_mac_group));
+ 801a07c:	01000504 	movi	r4,20
+ 801a080:	8042c980 	call	8042c98 <malloc>
+ 801a084:	e0bffd15 	stw	r2,-12(fp)
+            if(!pmac_group) {
+ 801a088:	e0bffd17 	ldw	r2,-12(fp)
+ 801a08c:	1000081e 	bne	r2,zero,801a0b0 <alt_tse_mac_group_init+0xb0>
+                tse_dprintf(1, "ERROR   : Unable to allocate memory for MAC Group[%d]\n", mac_group_count);
+ 801a090:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801a094:	10803fcc 	andi	r2,r2,255
+ 801a098:	100b883a 	mov	r5,r2
+ 801a09c:	01020174 	movhi	r4,2053
+ 801a0a0:	21208c04 	addi	r4,r4,-32208
+ 801a0a4:	8002c780 	call	8002c78 <printf>
+                return ALTERA_TSE_MALLOC_FAILED;
+ 801a0a8:	00bfffc4 	movi	r2,-1
+ 801a0ac:	00017506 	br	801a684 <alt_tse_mac_group_init+0x684>
+            }
+           
+            /* Non-multi-channel MAC considered as 1 channel */
+            if(psys->tse_multichannel_mac) {
+ 801a0b0:	e0bffc17 	ldw	r2,-16(fp)
+ 801a0b4:	108003c3 	ldbu	r2,15(r2)
+ 801a0b8:	10803fcc 	andi	r2,r2,255
+ 801a0bc:	10001226 	beq	r2,zero,801a108 <alt_tse_mac_group_init+0x108>
+                pmac_group->channel = psys->tse_num_of_channel;
+ 801a0c0:	e0bffc17 	ldw	r2,-16(fp)
+ 801a0c4:	10c00403 	ldbu	r3,16(r2)
+ 801a0c8:	e0bffd17 	ldw	r2,-12(fp)
+ 801a0cc:	10c00005 	stb	r3,0(r2)
+                tse_dprintf(6, "INFO    : Multi Channel            = Yes\n");
+ 801a0d0:	01020174 	movhi	r4,2053
+ 801a0d4:	21209a04 	addi	r4,r4,-32152
+ 801a0d8:	8002d9c0 	call	8002d9c <puts>
+                tse_dprintf(6, "INFO    : Number of channel        = %d\n", pmac_group->channel);
+ 801a0dc:	e0bffd17 	ldw	r2,-12(fp)
+ 801a0e0:	10800003 	ldbu	r2,0(r2)
+ 801a0e4:	10803fcc 	andi	r2,r2,255
+ 801a0e8:	100b883a 	mov	r5,r2
+ 801a0ec:	01020174 	movhi	r4,2053
+ 801a0f0:	2120a504 	addi	r4,r4,-32108
+ 801a0f4:	8002c780 	call	8002c78 <printf>
+                tse_dprintf(6, "INFO    : MDIO Shared              = Yes\n");
+ 801a0f8:	01020174 	movhi	r4,2053
+ 801a0fc:	2120b004 	addi	r4,r4,-32064
+ 801a100:	8002d9c0 	call	8002d9c <puts>
+ 801a104:	00001f06 	br	801a184 <alt_tse_mac_group_init+0x184>
+            }
+            else if(psys->tse_mdio_shared) {
+ 801a108:	e0bffc17 	ldw	r2,-16(fp)
+ 801a10c:	10800443 	ldbu	r2,17(r2)
+ 801a110:	10803fcc 	andi	r2,r2,255
+ 801a114:	10001226 	beq	r2,zero,801a160 <alt_tse_mac_group_init+0x160>
+                pmac_group->channel = psys->tse_number_of_mac_mdio_shared;
+ 801a118:	e0bffc17 	ldw	r2,-16(fp)
+ 801a11c:	10c00483 	ldbu	r3,18(r2)
+ 801a120:	e0bffd17 	ldw	r2,-12(fp)
+ 801a124:	10c00005 	stb	r3,0(r2)
+                tse_dprintf(6, "INFO    : Multi Channel            = No\n");
+ 801a128:	01020174 	movhi	r4,2053
+ 801a12c:	2120bb04 	addi	r4,r4,-32020
+ 801a130:	8002d9c0 	call	8002d9c <puts>
+                tse_dprintf(6, "INFO    : MDIO Shared              = Yes\n");
+ 801a134:	01020174 	movhi	r4,2053
+ 801a138:	2120b004 	addi	r4,r4,-32064
+ 801a13c:	8002d9c0 	call	8002d9c <puts>
+                tse_dprintf(6, "INFO    : Number of MAC Share MDIO = %d\n", pmac_group->channel);
+ 801a140:	e0bffd17 	ldw	r2,-12(fp)
+ 801a144:	10800003 	ldbu	r2,0(r2)
+ 801a148:	10803fcc 	andi	r2,r2,255
+ 801a14c:	100b883a 	mov	r5,r2
+ 801a150:	01020174 	movhi	r4,2053
+ 801a154:	2120c504 	addi	r4,r4,-31980
+ 801a158:	8002c780 	call	8002c78 <printf>
+ 801a15c:	00000906 	br	801a184 <alt_tse_mac_group_init+0x184>
+            }
+            else {
+                pmac_group->channel = 1;
+ 801a160:	e0bffd17 	ldw	r2,-12(fp)
+ 801a164:	00c00044 	movi	r3,1
+ 801a168:	10c00005 	stb	r3,0(r2)
+                tse_dprintf(6, "INFO    : Multi Channel            = No\n");
+ 801a16c:	01020174 	movhi	r4,2053
+ 801a170:	2120bb04 	addi	r4,r4,-32020
+ 801a174:	8002d9c0 	call	8002d9c <puts>
+                tse_dprintf(6, "INFO    : MDIO Shared              = No\n");
+ 801a178:	01020174 	movhi	r4,2053
+ 801a17c:	2120d004 	addi	r4,r4,-31936
+ 801a180:	8002d9c0 	call	8002d9c <puts>
+            }
+            
+            for(j = 0; j < pmac_group->channel; j++) {
+ 801a184:	e03ffe85 	stb	zero,-6(fp)
+ 801a188:	00012106 	br	801a610 <alt_tse_mac_group_init+0x610>
+                /* Allocate memory for the structure */
+                pmac_info = (alt_tse_mac_info *) malloc(sizeof(alt_tse_mac_info));
+ 801a18c:	01000404 	movi	r4,16
+ 801a190:	8042c980 	call	8042c98 <malloc>
+ 801a194:	e0bfff15 	stw	r2,-4(fp)
+                if(!pmac_info) {
+ 801a198:	e0bfff17 	ldw	r2,-4(fp)
+ 801a19c:	10000a1e 	bne	r2,zero,801a1c8 <alt_tse_mac_group_init+0x1c8>
+                    tse_dprintf(1, "ERROR   : Unable to allocate memory for MAC Group[%d]->pmac_info[%d]\n", mac_group_count, j);
+ 801a1a0:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801a1a4:	10803fcc 	andi	r2,r2,255
+ 801a1a8:	e0fffe87 	ldb	r3,-6(fp)
+ 801a1ac:	180d883a 	mov	r6,r3
+ 801a1b0:	100b883a 	mov	r5,r2
+ 801a1b4:	01020174 	movhi	r4,2053
+ 801a1b8:	2120da04 	addi	r4,r4,-31896
+ 801a1bc:	8002c780 	call	8002c78 <printf>
+                    return ALTERA_TSE_MALLOC_FAILED;
+ 801a1c0:	00bfffc4 	movi	r2,-1
+ 801a1c4:	00012f06 	br	801a684 <alt_tse_mac_group_init+0x684>
+                }
+                
+                pmac_info->pmac_group = pmac_group;
+ 801a1c8:	e0bfff17 	ldw	r2,-4(fp)
+ 801a1cc:	e0fffd17 	ldw	r3,-12(fp)
+ 801a1d0:	10c00315 	stw	r3,12(r2)
+                
+                pmac_info->pphy_info = 0;
+ 801a1d4:	e0bfff17 	ldw	r2,-4(fp)
+ 801a1d8:	10000115 	stw	zero,4(r2)
+                
+                pmac_info->psys_info = &tse_mac_device[i + j];
+ 801a1dc:	e0fffec7 	ldb	r3,-5(fp)
+ 801a1e0:	e0bffe87 	ldb	r2,-6(fp)
+ 801a1e4:	1885883a 	add	r2,r3,r2
+ 801a1e8:	10c01324 	muli	r3,r2,76
+ 801a1ec:	00820174 	movhi	r2,2053
+ 801a1f0:	10ae5404 	addi	r2,r2,-18096
+ 801a1f4:	1887883a 	add	r3,r3,r2
+ 801a1f8:	e0bfff17 	ldw	r2,-4(fp)
+ 801a1fc:	10c00215 	stw	r3,8(r2)
+                
+                /* check to make sure the alt_tse_system_info defined correctly or has been defined */
+                if((pmac_info->psys_info->tse_msgdma_tx == 0) || (pmac_info->psys_info->tse_msgdma_rx == 0)){                    
+ 801a200:	e0bfff17 	ldw	r2,-4(fp)
+ 801a204:	10800217 	ldw	r2,8(r2)
+ 801a208:	10800617 	ldw	r2,24(r2)
+ 801a20c:	10000426 	beq	r2,zero,801a220 <alt_tse_mac_group_init+0x220>
+ 801a210:	e0bfff17 	ldw	r2,-4(fp)
+ 801a214:	10800217 	ldw	r2,8(r2)
+ 801a218:	10800717 	ldw	r2,28(r2)
+ 801a21c:	1000091e 	bne	r2,zero,801a244 <alt_tse_mac_group_init+0x244>
+                    tse_dprintf(2, "ERROR   : tse_mac_device[%d] does not defined correctly!\n", i + j);
+ 801a220:	e0fffec7 	ldb	r3,-5(fp)
+ 801a224:	e0bffe87 	ldb	r2,-6(fp)
+ 801a228:	1885883a 	add	r2,r3,r2
+ 801a22c:	100b883a 	mov	r5,r2
+ 801a230:	01020174 	movhi	r4,2053
+ 801a234:	2120ec04 	addi	r4,r4,-31824
+ 801a238:	8002c780 	call	8002c78 <printf>
+                    return ALTERA_TSE_SYSTEM_DEF_ERROR;
+ 801a23c:	00bfffc4 	movi	r2,-1
+ 801a240:	00011006 	br	801a684 <alt_tse_mac_group_init+0x684>
+                }
+                
+                /* MAC type detection */
+                if(pmac_info->psys_info->tse_en_maclite) {
+ 801a244:	e0bfff17 	ldw	r2,-4(fp)
+ 801a248:	10800217 	ldw	r2,8(r2)
+ 801a24c:	10800343 	ldbu	r2,13(r2)
+ 801a250:	10803fcc 	andi	r2,r2,255
+ 801a254:	10000d26 	beq	r2,zero,801a28c <alt_tse_mac_group_init+0x28c>
+                    if(pmac_info->psys_info->tse_maclite_gige) {
+ 801a258:	e0bfff17 	ldw	r2,-4(fp)
+ 801a25c:	10800217 	ldw	r2,8(r2)
+ 801a260:	10800383 	ldbu	r2,14(r2)
+ 801a264:	10803fcc 	andi	r2,r2,255
+ 801a268:	10000426 	beq	r2,zero,801a27c <alt_tse_mac_group_init+0x27c>
+                        pmac_info->mac_type = ALTERA_TSE_MACLITE_1000;
+ 801a26c:	e0bfff17 	ldw	r2,-4(fp)
+ 801a270:	00c00084 	movi	r3,2
+ 801a274:	10c00005 	stb	r3,0(r2)
+ 801a278:	00000606 	br	801a294 <alt_tse_mac_group_init+0x294>
+                    }
+                    else {
+                        pmac_info->mac_type = ALTERA_TSE_MACLITE_10_100;
+ 801a27c:	e0bfff17 	ldw	r2,-4(fp)
+ 801a280:	00c00044 	movi	r3,1
+ 801a284:	10c00005 	stb	r3,0(r2)
+ 801a288:	00000206 	br	801a294 <alt_tse_mac_group_init+0x294>
+                    }
+                }
+                else {
+                    pmac_info->mac_type = ALTERA_TSE_FULL_MAC;                    
+ 801a28c:	e0bfff17 	ldw	r2,-4(fp)
+ 801a290:	10000005 	stb	zero,0(r2)
+                }
+                
+                if((pmac_info->psys_info->tse_mdio_shared) && (!pmac_info->psys_info->tse_multichannel_mac)){
+ 801a294:	e0bfff17 	ldw	r2,-4(fp)
+ 801a298:	10800217 	ldw	r2,8(r2)
+ 801a29c:	10800443 	ldbu	r2,17(r2)
+ 801a2a0:	10803fcc 	andi	r2,r2,255
+ 801a2a4:	10006626 	beq	r2,zero,801a440 <alt_tse_mac_group_init+0x440>
+ 801a2a8:	e0bfff17 	ldw	r2,-4(fp)
+ 801a2ac:	10800217 	ldw	r2,8(r2)
+ 801a2b0:	108003c3 	ldbu	r2,15(r2)
+ 801a2b4:	10803fcc 	andi	r2,r2,255
+ 801a2b8:	1000611e 	bne	r2,zero,801a440 <alt_tse_mac_group_init+0x440>
+                    tse_dprintf(6, "INFO    : MAC %2d Address           = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base);
+ 801a2bc:	e0fffe87 	ldb	r3,-6(fp)
+ 801a2c0:	e0bfff17 	ldw	r2,-4(fp)
+ 801a2c4:	10800217 	ldw	r2,8(r2)
+ 801a2c8:	10800017 	ldw	r2,0(r2)
+ 801a2cc:	100d883a 	mov	r6,r2
+ 801a2d0:	180b883a 	mov	r5,r3
+ 801a2d4:	01020174 	movhi	r4,2053
+ 801a2d8:	2120fb04 	addi	r4,r4,-31764
+ 801a2dc:	8002c780 	call	8002c78 <printf>
+                    tse_dprintf(6, "INFO    : MAC %2d Device            = tse_mac_device[%d]\n", j, i + j);
+ 801a2e0:	e13ffe87 	ldb	r4,-6(fp)
+ 801a2e4:	e0fffec7 	ldb	r3,-5(fp)
+ 801a2e8:	e0bffe87 	ldb	r2,-6(fp)
+ 801a2ec:	1885883a 	add	r2,r3,r2
+ 801a2f0:	100d883a 	mov	r6,r2
+ 801a2f4:	200b883a 	mov	r5,r4
+ 801a2f8:	01020174 	movhi	r4,2053
+ 801a2fc:	21210704 	addi	r4,r4,-31716
+ 801a300:	8002c780 	call	8002c78 <printf>
+                    
+                    switch(pmac_info->mac_type) {
+ 801a304:	e0bfff17 	ldw	r2,-4(fp)
+ 801a308:	10800003 	ldbu	r2,0(r2)
+ 801a30c:	10803fcc 	andi	r2,r2,255
+ 801a310:	10c00060 	cmpeqi	r3,r2,1
+ 801a314:	18000c1e 	bne	r3,zero,801a348 <alt_tse_mac_group_init+0x348>
+ 801a318:	10c000a0 	cmpeqi	r3,r2,2
+ 801a31c:	1800021e 	bne	r3,zero,801a328 <alt_tse_mac_group_init+0x328>
+ 801a320:	10001126 	beq	r2,zero,801a368 <alt_tse_mac_group_init+0x368>
+ 801a324:	00001806 	br	801a388 <alt_tse_mac_group_init+0x388>
+                        case ALTERA_TSE_MACLITE_1000:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "1000 Mbps Small MAC");
+ 801a328:	e0bffe87 	ldb	r2,-6(fp)
+ 801a32c:	01820174 	movhi	r6,2053
+ 801a330:	31a11604 	addi	r6,r6,-31656
+ 801a334:	100b883a 	mov	r5,r2
+ 801a338:	01020174 	movhi	r4,2053
+ 801a33c:	21211b04 	addi	r4,r4,-31636
+ 801a340:	8002c780 	call	8002c78 <printf>
+                            break;
+ 801a344:	00001806 	br	801a3a8 <alt_tse_mac_group_init+0x3a8>
+                        case ALTERA_TSE_MACLITE_10_100:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "10/100 Mbps Small MAC");
+ 801a348:	e0bffe87 	ldb	r2,-6(fp)
+ 801a34c:	01820174 	movhi	r6,2053
+ 801a350:	31a12604 	addi	r6,r6,-31592
+ 801a354:	100b883a 	mov	r5,r2
+ 801a358:	01020174 	movhi	r4,2053
+ 801a35c:	21211b04 	addi	r4,r4,-31636
+ 801a360:	8002c780 	call	8002c78 <printf>
+                            break;
+ 801a364:	00001006 	br	801a3a8 <alt_tse_mac_group_init+0x3a8>
+                        case ALTERA_TSE_FULL_MAC:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "10/100/1000 Ethernet MAC");
+ 801a368:	e0bffe87 	ldb	r2,-6(fp)
+ 801a36c:	01820174 	movhi	r6,2053
+ 801a370:	31a12c04 	addi	r6,r6,-31568
+ 801a374:	100b883a 	mov	r5,r2
+ 801a378:	01020174 	movhi	r4,2053
+ 801a37c:	21211b04 	addi	r4,r4,-31636
+ 801a380:	8002c780 	call	8002c78 <printf>
+                            break;
+ 801a384:	00000806 	br	801a3a8 <alt_tse_mac_group_init+0x3a8>
+                        default :
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "Unknown");
+ 801a388:	e0bffe87 	ldb	r2,-6(fp)
+ 801a38c:	01820134 	movhi	r6,2052
+ 801a390:	319f4d04 	addi	r6,r6,32052
+ 801a394:	100b883a 	mov	r5,r2
+ 801a398:	01020174 	movhi	r4,2053
+ 801a39c:	21211b04 	addi	r4,r4,-31636
+ 801a3a0:	8002c780 	call	8002c78 <printf>
+                            break;
+ 801a3a4:	0001883a 	nop
+                    }
+                    
+                    if(pmac_info->psys_info->tse_pcs_ena) {
+ 801a3a8:	e0bfff17 	ldw	r2,-4(fp)
+ 801a3ac:	10800217 	ldw	r2,8(r2)
+ 801a3b0:	108004c3 	ldbu	r2,19(r2)
+ 801a3b4:	10803fcc 	andi	r2,r2,255
+ 801a3b8:	10008b26 	beq	r2,zero,801a5e8 <alt_tse_mac_group_init+0x5e8>
+                        tse_dprintf(6, "INFO    : PCS %2d Enable            = %s\n", j, pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No");
+ 801a3bc:	e0fffe87 	ldb	r3,-6(fp)
+ 801a3c0:	e0bfff17 	ldw	r2,-4(fp)
+ 801a3c4:	10800217 	ldw	r2,8(r2)
+ 801a3c8:	108004c3 	ldbu	r2,19(r2)
+ 801a3cc:	10803fcc 	andi	r2,r2,255
+ 801a3d0:	10000326 	beq	r2,zero,801a3e0 <alt_tse_mac_group_init+0x3e0>
+ 801a3d4:	00820174 	movhi	r2,2053
+ 801a3d8:	10a13304 	addi	r2,r2,-31540
+ 801a3dc:	00000206 	br	801a3e8 <alt_tse_mac_group_init+0x3e8>
+ 801a3e0:	00820174 	movhi	r2,2053
+ 801a3e4:	10a13404 	addi	r2,r2,-31536
+ 801a3e8:	100d883a 	mov	r6,r2
+ 801a3ec:	180b883a 	mov	r5,r3
+ 801a3f0:	01020174 	movhi	r4,2053
+ 801a3f4:	21213504 	addi	r4,r4,-31532
+ 801a3f8:	8002c780 	call	8002c78 <printf>
+                        tse_dprintf(6, "INFO    : PCS %2d SGMII Enable      = %s\n", j, pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No");                        
+ 801a3fc:	e0fffe87 	ldb	r3,-6(fp)
+ 801a400:	e0bfff17 	ldw	r2,-4(fp)
+ 801a404:	10800217 	ldw	r2,8(r2)
+ 801a408:	10800503 	ldbu	r2,20(r2)
+ 801a40c:	10803fcc 	andi	r2,r2,255
+ 801a410:	10000326 	beq	r2,zero,801a420 <alt_tse_mac_group_init+0x420>
+ 801a414:	00820174 	movhi	r2,2053
+ 801a418:	10a13304 	addi	r2,r2,-31540
+ 801a41c:	00000206 	br	801a428 <alt_tse_mac_group_init+0x428>
+ 801a420:	00820174 	movhi	r2,2053
+ 801a424:	10a13404 	addi	r2,r2,-31536
+ 801a428:	100d883a 	mov	r6,r2
+ 801a42c:	180b883a 	mov	r5,r3
+ 801a430:	01020174 	movhi	r4,2053
+ 801a434:	21214004 	addi	r4,r4,-31488
+ 801a438:	8002c780 	call	8002c78 <printf>
+                    if(pmac_info->psys_info->tse_pcs_ena) {
+ 801a43c:	00006a06 	br	801a5e8 <alt_tse_mac_group_init+0x5e8>
+                    }
+                }
+                else {
+                    /* display only once for all MAC, except shared MDIO MACs */
+                    if(j == 0) {
+ 801a440:	e0bffe87 	ldb	r2,-6(fp)
+ 801a444:	1000421e 	bne	r2,zero,801a550 <alt_tse_mac_group_init+0x550>
+                        switch(pmac_info->mac_type) {
+ 801a448:	e0bfff17 	ldw	r2,-4(fp)
+ 801a44c:	10800003 	ldbu	r2,0(r2)
+ 801a450:	10803fcc 	andi	r2,r2,255
+ 801a454:	10c00060 	cmpeqi	r3,r2,1
+ 801a458:	18000a1e 	bne	r3,zero,801a484 <alt_tse_mac_group_init+0x484>
+ 801a45c:	10c000a0 	cmpeqi	r3,r2,2
+ 801a460:	1800021e 	bne	r3,zero,801a46c <alt_tse_mac_group_init+0x46c>
+ 801a464:	10000d26 	beq	r2,zero,801a49c <alt_tse_mac_group_init+0x49c>
+ 801a468:	00001206 	br	801a4b4 <alt_tse_mac_group_init+0x4b4>
+                            case ALTERA_TSE_MACLITE_1000:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "1000 Mbps Small MAC");
+ 801a46c:	01420174 	movhi	r5,2053
+ 801a470:	29611604 	addi	r5,r5,-31656
+ 801a474:	01020174 	movhi	r4,2053
+ 801a478:	21214b04 	addi	r4,r4,-31444
+ 801a47c:	8002c780 	call	8002c78 <printf>
+                                break;
+ 801a480:	00001206 	br	801a4cc <alt_tse_mac_group_init+0x4cc>
+                            case ALTERA_TSE_MACLITE_10_100:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "10/100 Mbps Small MAC");
+ 801a484:	01420174 	movhi	r5,2053
+ 801a488:	29612604 	addi	r5,r5,-31592
+ 801a48c:	01020174 	movhi	r4,2053
+ 801a490:	21214b04 	addi	r4,r4,-31444
+ 801a494:	8002c780 	call	8002c78 <printf>
+                                break;
+ 801a498:	00000c06 	br	801a4cc <alt_tse_mac_group_init+0x4cc>
+                            case ALTERA_TSE_FULL_MAC:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "10/100/1000 Ethernet MAC");
+ 801a49c:	01420174 	movhi	r5,2053
+ 801a4a0:	29612c04 	addi	r5,r5,-31568
+ 801a4a4:	01020174 	movhi	r4,2053
+ 801a4a8:	21214b04 	addi	r4,r4,-31444
+ 801a4ac:	8002c780 	call	8002c78 <printf>
+                                break;
+ 801a4b0:	00000606 	br	801a4cc <alt_tse_mac_group_init+0x4cc>
+                            default :
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "Unknown");
+ 801a4b4:	01420134 	movhi	r5,2052
+ 801a4b8:	295f4d04 	addi	r5,r5,32052
+ 801a4bc:	01020174 	movhi	r4,2053
+ 801a4c0:	21214b04 	addi	r4,r4,-31444
+ 801a4c4:	8002c780 	call	8002c78 <printf>
+                                    break;
+ 801a4c8:	0001883a 	nop
+                }
+                        
+                        if(pmac_info->psys_info->tse_pcs_ena) {
+ 801a4cc:	e0bfff17 	ldw	r2,-4(fp)
+ 801a4d0:	10800217 	ldw	r2,8(r2)
+ 801a4d4:	108004c3 	ldbu	r2,19(r2)
+ 801a4d8:	10803fcc 	andi	r2,r2,255
+ 801a4dc:	10001c26 	beq	r2,zero,801a550 <alt_tse_mac_group_init+0x550>
+                            tse_dprintf(6, "INFO    : PCS Enable               = %s\n", pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No");
+ 801a4e0:	e0bfff17 	ldw	r2,-4(fp)
+ 801a4e4:	10800217 	ldw	r2,8(r2)
+ 801a4e8:	108004c3 	ldbu	r2,19(r2)
+ 801a4ec:	10803fcc 	andi	r2,r2,255
+ 801a4f0:	10000326 	beq	r2,zero,801a500 <alt_tse_mac_group_init+0x500>
+ 801a4f4:	00820174 	movhi	r2,2053
+ 801a4f8:	10a13304 	addi	r2,r2,-31540
+ 801a4fc:	00000206 	br	801a508 <alt_tse_mac_group_init+0x508>
+ 801a500:	00820174 	movhi	r2,2053
+ 801a504:	10a13404 	addi	r2,r2,-31536
+ 801a508:	100b883a 	mov	r5,r2
+ 801a50c:	01020174 	movhi	r4,2053
+ 801a510:	21215604 	addi	r4,r4,-31400
+ 801a514:	8002c780 	call	8002c78 <printf>
+                            tse_dprintf(6, "INFO    : PCS SGMII Enable         = %s\n", pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No");                            
+ 801a518:	e0bfff17 	ldw	r2,-4(fp)
+ 801a51c:	10800217 	ldw	r2,8(r2)
+ 801a520:	10800503 	ldbu	r2,20(r2)
+ 801a524:	10803fcc 	andi	r2,r2,255
+ 801a528:	10000326 	beq	r2,zero,801a538 <alt_tse_mac_group_init+0x538>
+ 801a52c:	00820174 	movhi	r2,2053
+ 801a530:	10a13304 	addi	r2,r2,-31540
+ 801a534:	00000206 	br	801a540 <alt_tse_mac_group_init+0x540>
+ 801a538:	00820174 	movhi	r2,2053
+ 801a53c:	10a13404 	addi	r2,r2,-31536
+ 801a540:	100b883a 	mov	r5,r2
+ 801a544:	01020174 	movhi	r4,2053
+ 801a548:	21216104 	addi	r4,r4,-31356
+ 801a54c:	8002c780 	call	8002c78 <printf>
+                        }
+                    }
+                    
+                    if(pmac_info->psys_info->tse_multichannel_mac) {
+ 801a550:	e0bfff17 	ldw	r2,-4(fp)
+ 801a554:	10800217 	ldw	r2,8(r2)
+ 801a558:	108003c3 	ldbu	r2,15(r2)
+ 801a55c:	10803fcc 	andi	r2,r2,255
+ 801a560:	10001326 	beq	r2,zero,801a5b0 <alt_tse_mac_group_init+0x5b0>
+                        tse_dprintf(6, "INFO    : Channel %2d Address       = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base);
+ 801a564:	e0fffe87 	ldb	r3,-6(fp)
+ 801a568:	e0bfff17 	ldw	r2,-4(fp)
+ 801a56c:	10800217 	ldw	r2,8(r2)
+ 801a570:	10800017 	ldw	r2,0(r2)
+ 801a574:	100d883a 	mov	r6,r2
+ 801a578:	180b883a 	mov	r5,r3
+ 801a57c:	01020174 	movhi	r4,2053
+ 801a580:	21216c04 	addi	r4,r4,-31312
+ 801a584:	8002c780 	call	8002c78 <printf>
+                        tse_dprintf(6, "INFO    : Channel %2d Device        = tse_mac_device[%d]\n", j, i + j);
+ 801a588:	e13ffe87 	ldb	r4,-6(fp)
+ 801a58c:	e0fffec7 	ldb	r3,-5(fp)
+ 801a590:	e0bffe87 	ldb	r2,-6(fp)
+ 801a594:	1885883a 	add	r2,r3,r2
+ 801a598:	100d883a 	mov	r6,r2
+ 801a59c:	200b883a 	mov	r5,r4
+ 801a5a0:	01020174 	movhi	r4,2053
+ 801a5a4:	21217804 	addi	r4,r4,-31264
+ 801a5a8:	8002c780 	call	8002c78 <printf>
+ 801a5ac:	00000e06 	br	801a5e8 <alt_tse_mac_group_init+0x5e8>
+                    }                
+                    else {
+                        tse_dprintf(6, "INFO    : MAC Address              = 0x%08x\n", (int) pmac_info->psys_info->tse_mac_base);
+ 801a5b0:	e0bfff17 	ldw	r2,-4(fp)
+ 801a5b4:	10800217 	ldw	r2,8(r2)
+ 801a5b8:	10800017 	ldw	r2,0(r2)
+ 801a5bc:	100b883a 	mov	r5,r2
+ 801a5c0:	01020174 	movhi	r4,2053
+ 801a5c4:	21218704 	addi	r4,r4,-31204
+ 801a5c8:	8002c780 	call	8002c78 <printf>
+                        tse_dprintf(6, "INFO    : MAC Device               = tse_mac_device[%d]\n", i + j);
+ 801a5cc:	e0fffec7 	ldb	r3,-5(fp)
+ 801a5d0:	e0bffe87 	ldb	r2,-6(fp)
+ 801a5d4:	1885883a 	add	r2,r3,r2
+ 801a5d8:	100b883a 	mov	r5,r2
+ 801a5dc:	01020174 	movhi	r4,2053
+ 801a5e0:	21219304 	addi	r4,r4,-31156
+ 801a5e4:	8002c780 	call	8002c78 <printf>
+                    }
+                }
+                
+                /* store the pointer in MAC group variable for the detected channel */
+                pmac_group->pmac_info[j] = pmac_info;
+ 801a5e8:	e0bffe87 	ldb	r2,-6(fp)
+ 801a5ec:	e0fffd17 	ldw	r3,-12(fp)
+ 801a5f0:	10800044 	addi	r2,r2,1
+ 801a5f4:	100490ba 	slli	r2,r2,2
+ 801a5f8:	1885883a 	add	r2,r3,r2
+ 801a5fc:	e0ffff17 	ldw	r3,-4(fp)
+ 801a600:	10c00015 	stw	r3,0(r2)
+            for(j = 0; j < pmac_group->channel; j++) {
+ 801a604:	e0bffe83 	ldbu	r2,-6(fp)
+ 801a608:	10800044 	addi	r2,r2,1
+ 801a60c:	e0bffe85 	stb	r2,-6(fp)
+ 801a610:	e0fffe87 	ldb	r3,-6(fp)
+ 801a614:	e0bffd17 	ldw	r2,-12(fp)
+ 801a618:	10800003 	ldbu	r2,0(r2)
+ 801a61c:	10803fcc 	andi	r2,r2,255
+ 801a620:	18beda16 	blt	r3,r2,801a18c <alt_tse_mac_group_init+0x18c>
+            }
+            
+            /* store the pointer in global variable */
+            pmac_groups[mac_group_count] = pmac_group;
+ 801a624:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801a628:	10803fcc 	andi	r2,r2,255
+ 801a62c:	100890ba 	slli	r4,r2,2
+ 801a630:	e0fffd17 	ldw	r3,-12(fp)
+ 801a634:	008201b4 	movhi	r2,2054
+ 801a638:	2085883a 	add	r2,r4,r2
+ 801a63c:	10f5aa15 	stw	r3,-10584(r2)
+            
+            mac_group_count++;
+ 801a640:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801a644:	10800044 	addi	r2,r2,1
+ 801a648:	d0a05b45 	stb	r2,-32403(gp)
+
+            /* skip for subsequent Multi-channel MAC */
+            i += (pmac_group->channel - 1);
+ 801a64c:	e0bffd17 	ldw	r2,-12(fp)
+ 801a650:	10c00003 	ldbu	r3,0(r2)
+ 801a654:	e0bffec3 	ldbu	r2,-5(fp)
+ 801a658:	1885883a 	add	r2,r3,r2
+ 801a65c:	10bfffc4 	addi	r2,r2,-1
+ 801a660:	e0bffec5 	stb	r2,-5(fp)
+    for(i = 0; i < max_mac_system; i++) {
+ 801a664:	e0bffec3 	ldbu	r2,-5(fp)
+ 801a668:	10800044 	addi	r2,r2,1
+ 801a66c:	e0bffec5 	stb	r2,-5(fp)
+ 801a670:	e0fffec7 	ldb	r3,-5(fp)
+ 801a674:	d0a00a03 	ldbu	r2,-32728(gp)
+ 801a678:	10803fcc 	andi	r2,r2,255
+ 801a67c:	18be6a16 	blt	r3,r2,801a028 <alt_tse_mac_group_init+0x28>
+                        
+        }
+    }
+    return SUCCESS;
+ 801a680:	0005883a 	mov	r2,zero
+}
+ 801a684:	e037883a 	mov	sp,fp
+ 801a688:	dfc00117 	ldw	ra,4(sp)
+ 801a68c:	df000017 	ldw	fp,0(sp)
+ 801a690:	dec00204 	addi	sp,sp,8
+ 801a694:	f800283a 	ret
+
+0801a698 <alt_tse_mac_get_phy>:
+/* @Function Description: Store information of all the PHYs connected to MAC to phy_list
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @return            Number of PHY not in profile, return ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ */
+alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group) {
+ 801a698:	deffed04 	addi	sp,sp,-76
+ 801a69c:	dfc01215 	stw	ra,72(sp)
+ 801a6a0:	df001115 	stw	fp,68(sp)
+ 801a6a4:	df001104 	addi	fp,sp,68
+ 801a6a8:	e13ff015 	stw	r4,-64(fp)
+    
+    alt_32 phyid; 
+    alt_32 phyid2 = 0;
+ 801a6ac:	e03fff15 	stw	zero,-4(fp)
+    alt_u8 revision_number;
+
+    alt_32 i;
+
+    alt_u8 is_phy_in_profile;
+    alt_32 return_value = 0;
+ 801a6b0:	e03ffd15 	stw	zero,-12(fp)
+    
+    alt_8 phy_info_count = 0;
+ 801a6b4:	e03ffec5 	stb	zero,-5(fp)
+    
+    alt_tse_phy_info *pphy = 0;
+ 801a6b8:	e03ff915 	stw	zero,-28(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 801a6bc:	e03ff815 	stw	zero,-32(fp)
+    alt_tse_system_info *psys = 0;
+ 801a6c0:	e03ff715 	stw	zero,-36(fp)
+    
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 801a6c4:	e0bff017 	ldw	r2,-64(fp)
+ 801a6c8:	10800117 	ldw	r2,4(r2)
+ 801a6cc:	10800217 	ldw	r2,8(r2)
+ 801a6d0:	10800017 	ldw	r2,0(r2)
+ 801a6d4:	e0bff615 	stw	r2,-40(fp)
+            
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0);
+ 801a6d8:	e0bff617 	ldw	r2,-40(fp)
+ 801a6dc:	10801004 	addi	r2,r2,64
+ 801a6e0:	10800037 	ldwio	r2,0(r2)
+ 801a6e4:	e0bff515 	stw	r2,-44(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801a6e8:	e13ff017 	ldw	r4,-64(fp)
+ 801a6ec:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801a6f0:	e0bff4c5 	stb	r2,-45(fp)
+    
+    /* loop all valid PHY address to look for connected PHY */
+    for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++)	//M.D. 2019-08-05: don't look at unused PHYs
+ 801a6f4:	e03ffcc5 	stb	zero,-13(fp)
+ 801a6f8:	0000c106 	br	801aa00 <alt_tse_mac_get_phy+0x368>
+    {
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, phyadd);
+ 801a6fc:	e0bff617 	ldw	r2,-40(fp)
+ 801a700:	10801004 	addi	r2,r2,64
+ 801a704:	e0fffcc3 	ldbu	r3,-13(fp)
+ 801a708:	10c00035 	stwio	r3,0(r2)
+        phyid = IORD(&pmac_group_base->mdio1.PHY_ID1,0);     // read PHY ID
+ 801a70c:	e0bff617 	ldw	r2,-40(fp)
+ 801a710:	1080a204 	addi	r2,r2,648
+ 801a714:	10800037 	ldwio	r2,0(r2)
+ 801a718:	e0bff315 	stw	r2,-52(fp)
+        phyid2 = IORD(&pmac_group_base->mdio1.PHY_ID2,0);     // read PHY ID
+ 801a71c:	e0bff617 	ldw	r2,-40(fp)
+ 801a720:	1080a304 	addi	r2,r2,652
+ 801a724:	10800037 	ldwio	r2,0(r2)
+ 801a728:	e0bfff15 	stw	r2,-4(fp)
+        
+        /* PHY found */
+        if (phyid != phyid2)
+ 801a72c:	e0fff317 	ldw	r3,-52(fp)
+ 801a730:	e0bfff17 	ldw	r2,-4(fp)
+ 801a734:	1880af26 	beq	r3,r2,801a9f4 <alt_tse_mac_get_phy+0x35c>
+        {
+            pphy = (alt_tse_phy_info *) malloc(sizeof(alt_tse_phy_info));
+ 801a738:	01000704 	movi	r4,28
+ 801a73c:	8042c980 	call	8042c98 <malloc>
+ 801a740:	e0bff915 	stw	r2,-28(fp)
+            if(!pphy) {
+ 801a744:	e0bff917 	ldw	r2,-28(fp)
+ 801a748:	1000091e 	bne	r2,zero,801a770 <alt_tse_mac_get_phy+0xd8>
+                tse_dprintf(1, "ERROR   : Unable to allocate memory for phy_info[%d.%d]\n", mac_group_index, phy_info_count);
+ 801a74c:	e0bff4c7 	ldb	r2,-45(fp)
+ 801a750:	e0fffec7 	ldb	r3,-5(fp)
+ 801a754:	180d883a 	mov	r6,r3
+ 801a758:	100b883a 	mov	r5,r2
+ 801a75c:	01020174 	movhi	r4,2053
+ 801a760:	2121a204 	addi	r4,r4,-31096
+ 801a764:	8002c780 	call	8002c78 <printf>
+                return ALTERA_TSE_MALLOC_FAILED;
+ 801a768:	00bfffc4 	movi	r2,-1
+ 801a76c:	0000c806 	br	801aa90 <alt_tse_mac_get_phy+0x3f8>
+            }
+            
+            /* store PHY address */
+            pphy->mdio_address = phyadd;
+ 801a770:	e0bff917 	ldw	r2,-28(fp)
+ 801a774:	e0fffcc3 	ldbu	r3,-13(fp)
+ 801a778:	10c00005 	stb	r3,0(r2)
+
+            /* get oui, model number, and revision number from PHYID and PHYID2 */
+            oui = (phyid << 6) | ((phyid2 >> 10) & 0x3f);
+ 801a77c:	e0bff317 	ldw	r2,-52(fp)
+ 801a780:	100691ba 	slli	r3,r2,6
+ 801a784:	e0bfff17 	ldw	r2,-4(fp)
+ 801a788:	1005d2ba 	srai	r2,r2,10
+ 801a78c:	10800fcc 	andi	r2,r2,63
+ 801a790:	1884b03a 	or	r2,r3,r2
+ 801a794:	e0bff215 	stw	r2,-56(fp)
+            model_number = (phyid2 >> 4) & 0x3f;
+ 801a798:	e0bfff17 	ldw	r2,-4(fp)
+ 801a79c:	1005d13a 	srai	r2,r2,4
+ 801a7a0:	10800fcc 	andi	r2,r2,63
+ 801a7a4:	e0bff1c5 	stb	r2,-57(fp)
+            revision_number = phyid2 & 0x0f;
+ 801a7a8:	e0bfff17 	ldw	r2,-4(fp)
+ 801a7ac:	108003cc 	andi	r2,r2,15
+ 801a7b0:	e0bff185 	stb	r2,-58(fp)
+            
+            /* map the PHY with PHY in profile */
+            is_phy_in_profile = 0;
+ 801a7b4:	e03ffac5 	stb	zero,-21(fp)
+            for(i = 0; i < phy_profile_count; i++) {
+ 801a7b8:	e03ffb15 	stw	zero,-20(fp)
+ 801a7bc:	00002c06 	br	801a870 <alt_tse_mac_get_phy+0x1d8>
+                
+                /* if PHY match with PHY in profile */
+                if((pphy_profiles[i]->oui == oui) && (pphy_profiles[i]->model_number == model_number))
+ 801a7c0:	e0bffb17 	ldw	r2,-20(fp)
+ 801a7c4:	100690ba 	slli	r3,r2,2
+ 801a7c8:	008201b4 	movhi	r2,2054
+ 801a7cc:	1885883a 	add	r2,r3,r2
+ 801a7d0:	10b5ae17 	ldw	r2,-10568(r2)
+ 801a7d4:	10801417 	ldw	r2,80(r2)
+ 801a7d8:	e0fff217 	ldw	r3,-56(fp)
+ 801a7dc:	1880211e 	bne	r3,r2,801a864 <alt_tse_mac_get_phy+0x1cc>
+ 801a7e0:	e0bffb17 	ldw	r2,-20(fp)
+ 801a7e4:	100690ba 	slli	r3,r2,2
+ 801a7e8:	008201b4 	movhi	r2,2054
+ 801a7ec:	1885883a 	add	r2,r3,r2
+ 801a7f0:	10b5ae17 	ldw	r2,-10568(r2)
+ 801a7f4:	10801503 	ldbu	r2,84(r2)
+ 801a7f8:	e0fff1c3 	ldbu	r3,-57(fp)
+ 801a7fc:	10803fcc 	andi	r2,r2,255
+ 801a800:	1880181e 	bne	r3,r2,801a864 <alt_tse_mac_get_phy+0x1cc>
+                {
+                    pphy->pphy_profile = pphy_profiles[i];
+ 801a804:	e0bffb17 	ldw	r2,-20(fp)
+ 801a808:	100690ba 	slli	r3,r2,2
+ 801a80c:	008201b4 	movhi	r2,2054
+ 801a810:	1885883a 	add	r2,r3,r2
+ 801a814:	10f5ae17 	ldw	r3,-10568(r2)
+ 801a818:	e0bff917 	ldw	r2,-28(fp)
+ 801a81c:	10c00515 	stw	r3,20(r2)
+                    
+                    /* PHY found, add it to phy_list */
+                    tse_dprintf(5, "INFO    : PHY %s found at PHY address 0x%02x of MAC Group[%d]\n", pphy_profiles[i]->name, phyadd, mac_group_index);
+ 801a820:	e0bffb17 	ldw	r2,-20(fp)
+ 801a824:	100690ba 	slli	r3,r2,2
+ 801a828:	008201b4 	movhi	r2,2054
+ 801a82c:	1885883a 	add	r2,r3,r2
+ 801a830:	10b5ae17 	ldw	r2,-10568(r2)
+ 801a834:	1009883a 	mov	r4,r2
+ 801a838:	e0bffcc3 	ldbu	r2,-13(fp)
+ 801a83c:	e0fff4c7 	ldb	r3,-45(fp)
+ 801a840:	180f883a 	mov	r7,r3
+ 801a844:	100d883a 	mov	r6,r2
+ 801a848:	200b883a 	mov	r5,r4
+ 801a84c:	01020174 	movhi	r4,2053
+ 801a850:	2121b104 	addi	r4,r4,-31036
+ 801a854:	8002c780 	call	8002c78 <printf>
+                    is_phy_in_profile = 1;
+ 801a858:	00800044 	movi	r2,1
+ 801a85c:	e0bffac5 	stb	r2,-21(fp)
+                    break;
+ 801a860:	00000706 	br	801a880 <alt_tse_mac_get_phy+0x1e8>
+            for(i = 0; i < phy_profile_count; i++) {
+ 801a864:	e0bffb17 	ldw	r2,-20(fp)
+ 801a868:	10800044 	addi	r2,r2,1
+ 801a86c:	e0bffb15 	stw	r2,-20(fp)
+ 801a870:	d0a05b03 	ldbu	r2,-32404(gp)
+ 801a874:	10803fcc 	andi	r2,r2,255
+ 801a878:	e0fffb17 	ldw	r3,-20(fp)
+ 801a87c:	18bfd016 	blt	r3,r2,801a7c0 <alt_tse_mac_get_phy+0x128>
+                }
+            }
+            /* PHY not found in PHY profile */
+            if(is_phy_in_profile == 0) {
+ 801a880:	e0bffac3 	ldbu	r2,-21(fp)
+ 801a884:	10000f1e 	bne	r2,zero,801a8c4 <alt_tse_mac_get_phy+0x22c>
+                pphy->pphy_profile = 0;
+ 801a888:	e0bff917 	ldw	r2,-28(fp)
+ 801a88c:	10000515 	stw	zero,20(r2)
+                tse_dprintf(3, "WARNING : Unknown PHY found at PHY address 0x%02x of MAC Group[%d]\n", phyadd, mac_group_index);
+ 801a890:	e0bffcc3 	ldbu	r2,-13(fp)
+ 801a894:	e0fff4c7 	ldb	r3,-45(fp)
+ 801a898:	180d883a 	mov	r6,r3
+ 801a89c:	100b883a 	mov	r5,r2
+ 801a8a0:	01020174 	movhi	r4,2053
+ 801a8a4:	2121c104 	addi	r4,r4,-30972
+ 801a8a8:	8002c780 	call	8002c78 <printf>
+                tse_dprintf(3, "WARNING : Please add PHY information to PHY profile\n");
+ 801a8ac:	01020174 	movhi	r4,2053
+ 801a8b0:	2121d204 	addi	r4,r4,-30904
+ 801a8b4:	8002d9c0 	call	8002d9c <puts>
+                return_value++;
+ 801a8b8:	e0bffd17 	ldw	r2,-12(fp)
+ 801a8bc:	10800044 	addi	r2,r2,1
+ 801a8c0:	e0bffd15 	stw	r2,-12(fp)
+            }
+            
+            tse_dprintf(6, "INFO    : PHY OUI             =  0x%06x\n", (int) oui);
+ 801a8c4:	e0bff217 	ldw	r2,-56(fp)
+ 801a8c8:	100b883a 	mov	r5,r2
+ 801a8cc:	01020174 	movhi	r4,2053
+ 801a8d0:	2121df04 	addi	r4,r4,-30852
+ 801a8d4:	8002c780 	call	8002c78 <printf>
+            tse_dprintf(6, "INFO    : PHY Model Number    =  0x%02x\n", model_number);
+ 801a8d8:	e0bff1c3 	ldbu	r2,-57(fp)
+ 801a8dc:	100b883a 	mov	r5,r2
+ 801a8e0:	01020174 	movhi	r4,2053
+ 801a8e4:	2121ea04 	addi	r4,r4,-30808
+ 801a8e8:	8002c780 	call	8002c78 <printf>
+            tse_dprintf(6, "INFO    : PHY Revision Number =  0x%01x\n", revision_number);
+ 801a8ec:	e0bff183 	ldbu	r2,-58(fp)
+ 801a8f0:	100b883a 	mov	r5,r2
+ 801a8f4:	01020174 	movhi	r4,2053
+ 801a8f8:	2121f504 	addi	r4,r4,-30764
+ 801a8fc:	8002c780 	call	8002c78 <printf>
+            
+            /* map the detected PHY to connected MAC */
+            if(alt_tse_mac_associate_phy(pmac_group, pphy) == TSE_PHY_MAP_SUCCESS) {
+ 801a900:	e17ff917 	ldw	r5,-28(fp)
+ 801a904:	e13ff017 	ldw	r4,-64(fp)
+ 801a908:	801aaa40 	call	801aaa4 <alt_tse_mac_associate_phy>
+ 801a90c:	1000341e 	bne	r2,zero,801a9e0 <alt_tse_mac_get_phy+0x348>
+                
+                pmac_info = pphy->pmac_info;
+ 801a910:	e0bff917 	ldw	r2,-28(fp)
+ 801a914:	10800617 	ldw	r2,24(r2)
+ 801a918:	e0bff815 	stw	r2,-32(fp)
+                psys = pmac_info->psys_info;
+ 801a91c:	e0bff817 	ldw	r2,-32(fp)
+ 801a920:	10800217 	ldw	r2,8(r2)
+ 801a924:	e0bff715 	stw	r2,-36(fp)
+                
+                /* Disable PHY loopback to allow Auto-Negotiation completed */
+                alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0);   // disable PHY loopback
+ 801a928:	d8000015 	stw	zero,0(sp)
+ 801a92c:	01c00044 	movi	r7,1
+ 801a930:	01800384 	movi	r6,14
+ 801a934:	000b883a 	mov	r5,zero
+ 801a938:	e13ff917 	ldw	r4,-28(fp)
+ 801a93c:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+                
+                /* Reset auto-negotiation advertisement */
+                alt_tse_phy_set_adv_1000(pphy, 1);
+ 801a940:	01400044 	movi	r5,1
+ 801a944:	e13ff917 	ldw	r4,-28(fp)
+ 801a948:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+                alt_tse_phy_set_adv_100(pphy, 1);
+ 801a94c:	01400044 	movi	r5,1
+ 801a950:	e13ff917 	ldw	r4,-28(fp)
+ 801a954:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+                alt_tse_phy_set_adv_10(pphy, 1);
+ 801a958:	01400044 	movi	r5,1
+ 801a95c:	e13ff917 	ldw	r4,-28(fp)
+ 801a960:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+                                
+                /* check link connection for this PHY */
+                alt_tse_phy_restart_an(pphy, ALTERA_CHECKLINK_TIMEOUT_THRESHOLD);
+ 801a964:	0149c404 	movi	r5,10000
+ 801a968:	e13ff917 	ldw	r4,-28(fp)
+ 801a96c:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+                
+                /* Perform additional setting if there is any */
+                /* Profile specific */
+                if(pphy->pphy_profile) {
+ 801a970:	e0bff917 	ldw	r2,-28(fp)
+ 801a974:	10800517 	ldw	r2,20(r2)
+ 801a978:	10000f26 	beq	r2,zero,801a9b8 <alt_tse_mac_get_phy+0x320>
+                    if(pphy->pphy_profile->phy_cfg) {
+ 801a97c:	e0bff917 	ldw	r2,-28(fp)
+ 801a980:	10800517 	ldw	r2,20(r2)
+ 801a984:	10801717 	ldw	r2,92(r2)
+ 801a988:	10000b26 	beq	r2,zero,801a9b8 <alt_tse_mac_get_phy+0x320>
+                        tse_dprintf(6, "INFO    : Applying additional PHY configuration of %s\n", pphy->pphy_profile->name);
+ 801a98c:	e0bff917 	ldw	r2,-28(fp)
+ 801a990:	10800517 	ldw	r2,20(r2)
+ 801a994:	100b883a 	mov	r5,r2
+ 801a998:	01020174 	movhi	r4,2053
+ 801a99c:	21220004 	addi	r4,r4,-30720
+ 801a9a0:	8002c780 	call	8002c78 <printf>
+                        pphy->pphy_profile->phy_cfg(pmac_group_base);
+ 801a9a4:	e0bff917 	ldw	r2,-28(fp)
+ 801a9a8:	10800517 	ldw	r2,20(r2)
+ 801a9ac:	10801717 	ldw	r2,92(r2)
+ 801a9b0:	e13ff617 	ldw	r4,-40(fp)
+ 801a9b4:	103ee83a 	callr	r2
+                    }
+                }
+                
+                /* Initialize PHY, call user's function pointer in alt_tse_system_info structure */
+                /* Individual PHY specific */
+                if(psys->tse_phy_cfg) {
+ 801a9b8:	e0bff717 	ldw	r2,-36(fp)
+ 801a9bc:	10801217 	ldw	r2,72(r2)
+ 801a9c0:	10000726 	beq	r2,zero,801a9e0 <alt_tse_mac_get_phy+0x348>
+                    tse_dprintf(6, "INFO    : Applying additional user PHY configuration\n");
+ 801a9c4:	01020174 	movhi	r4,2053
+ 801a9c8:	21220e04 	addi	r4,r4,-30664
+ 801a9cc:	8002d9c0 	call	8002d9c <puts>
+                    psys->tse_phy_cfg(pmac_group_base);
+ 801a9d0:	e0bff717 	ldw	r2,-36(fp)
+ 801a9d4:	10801217 	ldw	r2,72(r2)
+ 801a9d8:	e13ff617 	ldw	r4,-40(fp)
+ 801a9dc:	103ee83a 	callr	r2
+                }
+            }
+            
+            tse_dprintf(6, "\n");
+ 801a9e0:	01000284 	movi	r4,10
+ 801a9e4:	8002cb80 	call	8002cb8 <putchar>
+                
+            phy_info_count++;
+ 801a9e8:	e0bffec3 	ldbu	r2,-5(fp)
+ 801a9ec:	10800044 	addi	r2,r2,1
+ 801a9f0:	e0bffec5 	stb	r2,-5(fp)
+    for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++)	//M.D. 2019-08-05: don't look at unused PHYs
+ 801a9f4:	e0bffcc3 	ldbu	r2,-13(fp)
+ 801a9f8:	10800044 	addi	r2,r2,1
+ 801a9fc:	e0bffcc5 	stb	r2,-13(fp)
+ 801aa00:	e0bff017 	ldw	r2,-64(fp)
+ 801aa04:	10800003 	ldbu	r2,0(r2)
+ 801aa08:	e0fffcc3 	ldbu	r3,-13(fp)
+ 801aa0c:	10803fcc 	andi	r2,r2,255
+ 801aa10:	18bf3a36 	bltu	r3,r2,801a6fc <alt_tse_mac_get_phy+0x64>
+        }
+    }
+    
+    TK_SLEEP(100);	//Wait a little bit for PHY reset after specific configuration
+ 801aa14:	01001944 	movi	r4,101
+ 801aa18:	801730c0 	call	801730c <OSTimeDly>
+
+
+    /* check to verify the number of connected PHY match the number of channel */
+    if(pmac_group->channel != phy_info_count) {
+ 801aa1c:	e0bff017 	ldw	r2,-64(fp)
+ 801aa20:	10800003 	ldbu	r2,0(r2)
+ 801aa24:	10c03fcc 	andi	r3,r2,255
+ 801aa28:	e0bffec7 	ldb	r2,-5(fp)
+ 801aa2c:	18801326 	beq	r3,r2,801aa7c <alt_tse_mac_get_phy+0x3e4>
+        if(phy_info_count == 0) {
+ 801aa30:	e0bffec7 	ldb	r2,-5(fp)
+ 801aa34:	1000061e 	bne	r2,zero,801aa50 <alt_tse_mac_get_phy+0x3b8>
+            tse_dprintf(2, "ERROR   : MAC Group[%d] - No PHY connected!\n", mac_group_index);
+ 801aa38:	e0bff4c7 	ldb	r2,-45(fp)
+ 801aa3c:	100b883a 	mov	r5,r2
+ 801aa40:	01020174 	movhi	r4,2053
+ 801aa44:	21221c04 	addi	r4,r4,-30608
+ 801aa48:	8002c780 	call	8002c78 <printf>
+ 801aa4c:	00000b06 	br	801aa7c <alt_tse_mac_get_phy+0x3e4>
+        }
+        else {
+            tse_dprintf(3, "WARNING : MAC Group[%d] - Number of PHY connected is not equal to the number of channel, Number of PHY : %d, Channel : %d\n", mac_group_index, phy_info_count, pmac_group->channel);
+ 801aa50:	e0fff4c7 	ldb	r3,-45(fp)
+ 801aa54:	e13ffec7 	ldb	r4,-5(fp)
+ 801aa58:	e0bff017 	ldw	r2,-64(fp)
+ 801aa5c:	10800003 	ldbu	r2,0(r2)
+ 801aa60:	10803fcc 	andi	r2,r2,255
+ 801aa64:	100f883a 	mov	r7,r2
+ 801aa68:	200d883a 	mov	r6,r4
+ 801aa6c:	180b883a 	mov	r5,r3
+ 801aa70:	01020174 	movhi	r4,2053
+ 801aa74:	21222804 	addi	r4,r4,-30560
+ 801aa78:	8002c780 	call	8002c78 <printf>
+        }
+    }
+    
+    /* Restore previous MDIO address */
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+ 801aa7c:	e0bff617 	ldw	r2,-40(fp)
+ 801aa80:	10801004 	addi	r2,r2,64
+ 801aa84:	e0fff517 	ldw	r3,-44(fp)
+ 801aa88:	10c00035 	stwio	r3,0(r2)
+    
+    return return_value;
+ 801aa8c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 801aa90:	e037883a 	mov	sp,fp
+ 801aa94:	dfc00117 	ldw	ra,4(sp)
+ 801aa98:	df000017 	ldw	fp,0(sp)
+ 801aa9c:	dec00204 	addi	sp,sp,8
+ 801aaa0:	f800283a 	ret
+
+0801aaa4 <alt_tse_mac_associate_phy>:
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @param pphy        Pointer to the TSE PHY info structure which hold information of PHY
+ * @return            return TSE_PHY_MAP_ERROR if mapping error
+ *                    return TSE_PHY_MAP_SUCCESS otherwise
+ */
+alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy) {
+ 801aaa4:	defff604 	addi	sp,sp,-40
+ 801aaa8:	dfc00915 	stw	ra,36(sp)
+ 801aaac:	df000815 	stw	fp,32(sp)
+ 801aab0:	df000804 	addi	fp,sp,32
+ 801aab4:	e13ff915 	stw	r4,-28(fp)
+ 801aab8:	e17ff815 	stw	r5,-32(fp)
+    
+    alt_32 i;
+    alt_32 return_value = TSE_PHY_MAP_SUCCESS;
+ 801aabc:	e03ffd15 	stw	zero,-12(fp)
+    
+    alt_u8 is_mapped;
+
+    alt_tse_system_info *psys = 0;
+ 801aac0:	e03ffc15 	stw	zero,-16(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 801aac4:	e03ffb15 	stw	zero,-20(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+ 801aac8:	e03ffac5 	stb	zero,-21(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801aacc:	e13ff917 	ldw	r4,-28(fp)
+ 801aad0:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801aad4:	e0bffa85 	stb	r2,-22(fp)
+    alt_8 sys_info_index = 0;
+ 801aad8:	e03ffa45 	stb	zero,-23(fp)
+    
+    is_mapped = 0;
+ 801aadc:	e03fffc5 	stb	zero,-1(fp)
+    
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801aae0:	e03ffe15 	stw	zero,-8(fp)
+ 801aae4:	00002b06 	br	801ab94 <alt_tse_mac_associate_phy+0xf0>
+        pmac_info = pmac_group->pmac_info[i];
+ 801aae8:	e0fff917 	ldw	r3,-28(fp)
+ 801aaec:	e0bffe17 	ldw	r2,-8(fp)
+ 801aaf0:	10800044 	addi	r2,r2,1
+ 801aaf4:	100490ba 	slli	r2,r2,2
+ 801aaf8:	1885883a 	add	r2,r3,r2
+ 801aafc:	10800017 	ldw	r2,0(r2)
+ 801ab00:	e0bffb15 	stw	r2,-20(fp)
+        psys = pmac_info->psys_info;
+ 801ab04:	e0bffb17 	ldw	r2,-20(fp)
+ 801ab08:	10800217 	ldw	r2,8(r2)
+ 801ab0c:	e0bffc15 	stw	r2,-16(fp)
+       
+        /* map according to the PHY address in alt_tse_system_info.h */
+        if(psys->tse_phy_mdio_address == pphy->mdio_address) {
+ 801ab10:	e0bffc17 	ldw	r2,-16(fp)
+ 801ab14:	10c01117 	ldw	r3,68(r2)
+ 801ab18:	e0bff817 	ldw	r2,-32(fp)
+ 801ab1c:	10800003 	ldbu	r2,0(r2)
+ 801ab20:	10803fcc 	andi	r2,r2,255
+ 801ab24:	1880181e 	bne	r3,r2,801ab88 <alt_tse_mac_associate_phy+0xe4>
+            mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801ab28:	e13ffb17 	ldw	r4,-20(fp)
+ 801ab2c:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801ab30:	e0bffac5 	stb	r2,-21(fp)
+            sys_info_index = alt_tse_get_system_index(psys);
+ 801ab34:	e13ffc17 	ldw	r4,-16(fp)
+ 801ab38:	8018ac80 	call	8018ac8 <alt_tse_get_system_index>
+ 801ab3c:	e0bffa45 	stb	r2,-23(fp)
+            
+            pmac_info->pphy_info = pphy;
+ 801ab40:	e0bffb17 	ldw	r2,-20(fp)
+ 801ab44:	e0fff817 	ldw	r3,-32(fp)
+ 801ab48:	10c00115 	stw	r3,4(r2)
+            pphy->pmac_info = pmac_info;
+ 801ab4c:	e0bff817 	ldw	r2,-32(fp)
+ 801ab50:	e0fffb17 	ldw	r3,-20(fp)
+ 801ab54:	10c00615 	stw	r3,24(r2)
+            tse_dprintf(5, "INFO    : PHY[%d.%d] - Explicitly mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index);
+ 801ab58:	e0bffa87 	ldb	r2,-22(fp)
+ 801ab5c:	e0fffac7 	ldb	r3,-21(fp)
+ 801ab60:	e13ffa47 	ldb	r4,-23(fp)
+ 801ab64:	200f883a 	mov	r7,r4
+ 801ab68:	180d883a 	mov	r6,r3
+ 801ab6c:	100b883a 	mov	r5,r2
+ 801ab70:	01020174 	movhi	r4,2053
+ 801ab74:	21224704 	addi	r4,r4,-30436
+ 801ab78:	8002c780 	call	8002c78 <printf>
+            is_mapped = 1;
+ 801ab7c:	00800044 	movi	r2,1
+ 801ab80:	e0bfffc5 	stb	r2,-1(fp)
+            break;
+ 801ab84:	00000806 	br	801aba8 <alt_tse_mac_associate_phy+0x104>
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801ab88:	e0bffe17 	ldw	r2,-8(fp)
+ 801ab8c:	10800044 	addi	r2,r2,1
+ 801ab90:	e0bffe15 	stw	r2,-8(fp)
+ 801ab94:	e0bff917 	ldw	r2,-28(fp)
+ 801ab98:	10800003 	ldbu	r2,0(r2)
+ 801ab9c:	10803fcc 	andi	r2,r2,255
+ 801aba0:	e0fffe17 	ldw	r3,-8(fp)
+ 801aba4:	18bfd016 	blt	r3,r2,801aae8 <alt_tse_mac_associate_phy+0x44>
+        }
+    }
+    
+    /* if not yet map, it will automatically mapped to the first TSE device encountered with tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS */
+    if(is_mapped == 0) {
+ 801aba8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801abac:	10003c1e 	bne	r2,zero,801aca0 <alt_tse_mac_associate_phy+0x1fc>
+        for(i = 0; i < pmac_group->channel; i++) {
+ 801abb0:	e03ffe15 	stw	zero,-8(fp)
+ 801abb4:	00003506 	br	801ac8c <alt_tse_mac_associate_phy+0x1e8>
+            pmac_info = pmac_group->pmac_info[i];
+ 801abb8:	e0fff917 	ldw	r3,-28(fp)
+ 801abbc:	e0bffe17 	ldw	r2,-8(fp)
+ 801abc0:	10800044 	addi	r2,r2,1
+ 801abc4:	100490ba 	slli	r2,r2,2
+ 801abc8:	1885883a 	add	r2,r3,r2
+ 801abcc:	10800017 	ldw	r2,0(r2)
+ 801abd0:	e0bffb15 	stw	r2,-20(fp)
+            psys = pmac_info->psys_info;
+ 801abd4:	e0bffb17 	ldw	r2,-20(fp)
+ 801abd8:	10800217 	ldw	r2,8(r2)
+ 801abdc:	e0bffc15 	stw	r2,-16(fp)
+            
+            /* alt_tse_system_info structure definition error */
+            if((psys->tse_msgdma_tx == 0) || (psys->tse_msgdma_rx == 0)){
+ 801abe0:	e0bffc17 	ldw	r2,-16(fp)
+ 801abe4:	10800617 	ldw	r2,24(r2)
+ 801abe8:	10002426 	beq	r2,zero,801ac7c <alt_tse_mac_associate_phy+0x1d8>
+ 801abec:	e0bffc17 	ldw	r2,-16(fp)
+ 801abf0:	10800717 	ldw	r2,28(r2)
+ 801abf4:	10002126 	beq	r2,zero,801ac7c <alt_tse_mac_associate_phy+0x1d8>
+                continue;
+            }
+            
+            if(psys->tse_phy_mdio_address == TSE_PHY_AUTO_ADDRESS) {
+ 801abf8:	e0bffc17 	ldw	r2,-16(fp)
+ 801abfc:	10801117 	ldw	r2,68(r2)
+ 801ac00:	10bfffd8 	cmpnei	r2,r2,-1
+ 801ac04:	10001e1e 	bne	r2,zero,801ac80 <alt_tse_mac_associate_phy+0x1dc>
+                mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801ac08:	e13ffb17 	ldw	r4,-20(fp)
+ 801ac0c:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801ac10:	e0bffac5 	stb	r2,-21(fp)
+                sys_info_index = alt_tse_get_system_index(psys);
+ 801ac14:	e13ffc17 	ldw	r4,-16(fp)
+ 801ac18:	8018ac80 	call	8018ac8 <alt_tse_get_system_index>
+ 801ac1c:	e0bffa45 	stb	r2,-23(fp)
+                
+                pmac_info->pphy_info = pphy;
+ 801ac20:	e0bffb17 	ldw	r2,-20(fp)
+ 801ac24:	e0fff817 	ldw	r3,-32(fp)
+ 801ac28:	10c00115 	stw	r3,4(r2)
+                pphy->pmac_info = pmac_info;
+ 801ac2c:	e0bff817 	ldw	r2,-32(fp)
+ 801ac30:	e0fffb17 	ldw	r3,-20(fp)
+ 801ac34:	10c00615 	stw	r3,24(r2)
+                psys->tse_phy_mdio_address = pphy->mdio_address;
+ 801ac38:	e0bff817 	ldw	r2,-32(fp)
+ 801ac3c:	10800003 	ldbu	r2,0(r2)
+ 801ac40:	10c03fcc 	andi	r3,r2,255
+ 801ac44:	e0bffc17 	ldw	r2,-16(fp)
+ 801ac48:	10c01115 	stw	r3,68(r2)
+                tse_dprintf(5, "INFO    : PHY[%d.%d] - Automatically mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index);
+ 801ac4c:	e0bffa87 	ldb	r2,-22(fp)
+ 801ac50:	e0fffac7 	ldb	r3,-21(fp)
+ 801ac54:	e13ffa47 	ldb	r4,-23(fp)
+ 801ac58:	200f883a 	mov	r7,r4
+ 801ac5c:	180d883a 	mov	r6,r3
+ 801ac60:	100b883a 	mov	r5,r2
+ 801ac64:	01020174 	movhi	r4,2053
+ 801ac68:	21225704 	addi	r4,r4,-30372
+ 801ac6c:	8002c780 	call	8002c78 <printf>
+                is_mapped = 1;
+ 801ac70:	00800044 	movi	r2,1
+ 801ac74:	e0bfffc5 	stb	r2,-1(fp)
+                break;
+ 801ac78:	00000906 	br	801aca0 <alt_tse_mac_associate_phy+0x1fc>
+                continue;
+ 801ac7c:	0001883a 	nop
+        for(i = 0; i < pmac_group->channel; i++) {
+ 801ac80:	e0bffe17 	ldw	r2,-8(fp)
+ 801ac84:	10800044 	addi	r2,r2,1
+ 801ac88:	e0bffe15 	stw	r2,-8(fp)
+ 801ac8c:	e0bff917 	ldw	r2,-28(fp)
+ 801ac90:	10800003 	ldbu	r2,0(r2)
+ 801ac94:	10803fcc 	andi	r2,r2,255
+ 801ac98:	e0fffe17 	ldw	r3,-8(fp)
+ 801ac9c:	18bfc616 	blt	r3,r2,801abb8 <alt_tse_mac_associate_phy+0x114>
+            }
+        }
+    }
+    
+    /* Still cannot find any matched MAC-PHY */
+    if(is_mapped == 0) {
+ 801aca0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801aca4:	1000091e 	bne	r2,zero,801accc <alt_tse_mac_associate_phy+0x228>
+        pphy->pmac_info = 0;
+ 801aca8:	e0bff817 	ldw	r2,-32(fp)
+ 801acac:	10000615 	stw	zero,24(r2)
+        tse_dprintf(2, "WARNING : PHY[%d.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel\n", mac_group_index);
+ 801acb0:	e0bffa87 	ldb	r2,-22(fp)
+ 801acb4:	100b883a 	mov	r5,r2
+ 801acb8:	01020174 	movhi	r4,2053
+ 801acbc:	21226804 	addi	r4,r4,-30304
+ 801acc0:	8002c780 	call	8002c78 <printf>
+        return_value = TSE_PHY_MAP_ERROR;
+ 801acc4:	00bfffc4 	movi	r2,-1
+ 801acc8:	e0bffd15 	stw	r2,-12(fp)
+    }
+    
+    return return_value;
+ 801accc:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 801acd0:	e037883a 	mov	sp,fp
+ 801acd4:	dfc00117 	ldw	ra,4(sp)
+ 801acd8:	df000017 	ldw	fp,0(sp)
+ 801acdc:	dec00204 	addi	sp,sp,8
+ 801ace0:	f800283a 	ret
+
+0801ace4 <alt_tse_phy_cfg_pcs>:
+/* @Function Description: Configure operating mode of Altera PCS if available
+ * @API Type:           Internal
+ * @param pmac_info     pointer to MAC info variable
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) {
+ 801ace4:	defff804 	addi	sp,sp,-32
+ 801ace8:	dfc00715 	stw	ra,28(sp)
+ 801acec:	df000615 	stw	fp,24(sp)
+ 801acf0:	df000604 	addi	fp,sp,24
+ 801acf4:	e13ffa15 	stw	r4,-24(fp)
+    
+    alt_tse_system_info *psys = pmac_info->psys_info;
+ 801acf8:	e0bffa17 	ldw	r2,-24(fp)
+ 801acfc:	10800217 	ldw	r2,8(r2)
+ 801ad00:	e0bffd15 	stw	r2,-12(fp)
+    np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base;
+ 801ad04:	e0bffd17 	ldw	r2,-12(fp)
+ 801ad08:	10800017 	ldw	r2,0(r2)
+ 801ad0c:	e0bfff15 	stw	r2,-4(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801ad10:	e0bffa17 	ldw	r2,-24(fp)
+ 801ad14:	10800317 	ldw	r2,12(r2)
+ 801ad18:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801ad1c:	e13ffa17 	ldw	r4,-24(fp)
+ 801ad20:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801ad24:	e0bffcc5 	stb	r2,-13(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801ad28:	e13ffe17 	ldw	r4,-8(fp)
+ 801ad2c:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801ad30:	e0bffc85 	stb	r2,-14(fp)
+
+    if(psys->tse_pcs_ena) {
+ 801ad34:	e0bffd17 	ldw	r2,-12(fp)
+ 801ad38:	108004c3 	ldbu	r2,19(r2)
+ 801ad3c:	10803fcc 	andi	r2,r2,255
+ 801ad40:	10002c26 	beq	r2,zero,801adf4 <alt_tse_phy_cfg_pcs+0x110>
+        tse_dprintf(5, "INFO    : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index);
+ 801ad44:	e0bffc87 	ldb	r2,-14(fp)
+ 801ad48:	e0fffcc7 	ldb	r3,-13(fp)
+ 801ad4c:	180d883a 	mov	r6,r3
+ 801ad50:	100b883a 	mov	r5,r2
+ 801ad54:	01020174 	movhi	r4,2053
+ 801ad58:	21229904 	addi	r4,r4,-30108
+ 801ad5c:	8002c780 	call	8002c78 <printf>
+        
+        alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); 
+ 801ad60:	e0bfff17 	ldw	r2,-4(fp)
+ 801ad64:	10808004 	addi	r2,r2,512
+ 801ad68:	10801404 	addi	r2,r2,80
+ 801ad6c:	10800037 	ldwio	r2,0(r2)
+ 801ad70:	e0bffb15 	stw	r2,-20(fp)
+        
+        if(psys->tse_pcs_sgmii) {
+ 801ad74:	e0bffd17 	ldw	r2,-12(fp)
+ 801ad78:	10800503 	ldbu	r2,20(r2)
+ 801ad7c:	10803fcc 	andi	r2,r2,255
+ 801ad80:	10000e26 	beq	r2,zero,801adbc <alt_tse_phy_cfg_pcs+0xd8>
+            tse_dprintf(5, "INFO    : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index);
+ 801ad84:	e0bffc87 	ldb	r2,-14(fp)
+ 801ad88:	e0fffcc7 	ldb	r3,-13(fp)
+ 801ad8c:	180d883a 	mov	r6,r3
+ 801ad90:	100b883a 	mov	r5,r2
+ 801ad94:	01020174 	movhi	r4,2053
+ 801ad98:	2122a704 	addi	r4,r4,-30052
+ 801ad9c:	8002c780 	call	8002c78 <printf>
+            IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03);
+ 801ada0:	e0bfff17 	ldw	r2,-4(fp)
+ 801ada4:	10808004 	addi	r2,r2,512
+ 801ada8:	10801404 	addi	r2,r2,80
+ 801adac:	e0fffb17 	ldw	r3,-20(fp)
+ 801adb0:	18c000d4 	ori	r3,r3,3
+ 801adb4:	10c00035 	stwio	r3,0(r2)
+ 801adb8:	00000e06 	br	801adf4 <alt_tse_phy_cfg_pcs+0x110>
+            }
+        else {
+            tse_dprintf(5, "INFO    : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index);
+ 801adbc:	e0bffc87 	ldb	r2,-14(fp)
+ 801adc0:	e0fffcc7 	ldb	r3,-13(fp)
+ 801adc4:	180d883a 	mov	r6,r3
+ 801adc8:	100b883a 	mov	r5,r2
+ 801adcc:	01020174 	movhi	r4,2053
+ 801add0:	2122b304 	addi	r4,r4,-30004
+ 801add4:	8002c780 	call	8002c78 <printf>
+            IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03);
+ 801add8:	e0bfff17 	ldw	r2,-4(fp)
+ 801addc:	10808004 	addi	r2,r2,512
+ 801ade0:	10801404 	addi	r2,r2,80
+ 801ade4:	e13ffb17 	ldw	r4,-20(fp)
+ 801ade8:	00ffff04 	movi	r3,-4
+ 801adec:	20c6703a 	and	r3,r4,r3
+ 801adf0:	10c00035 	stwio	r3,0(r2)
+        }
+    }
+    
+    return SUCCESS;
+ 801adf4:	0005883a 	mov	r2,zero
+}
+ 801adf8:	e037883a 	mov	sp,fp
+ 801adfc:	dfc00117 	ldw	ra,4(sp)
+ 801ae00:	df000017 	ldw	fp,0(sp)
+ 801ae04:	dec00204 	addi	sp,sp,8
+ 801ae08:	f800283a 	ret
+
+0801ae0c <alt_tse_phy_init>:
+/* @Function Description: Detect and initialize all the PHYs connected
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      SUCCESS
+ */
+alt_32 alt_tse_phy_init() {
+ 801ae0c:	defffb04 	addi	sp,sp,-20
+ 801ae10:	dfc00415 	stw	ra,16(sp)
+ 801ae14:	df000315 	stw	fp,12(sp)
+ 801ae18:	df000304 	addi	fp,sp,12
+    alt_8 i = 0;
+ 801ae1c:	e03fffc5 	stb	zero,-1(fp)
+    alt_8 j = 0;
+ 801ae20:	e03fff85 	stb	zero,-2(fp)
+    
+    alt_tse_mac_group *pmac_group = 0;
+ 801ae24:	e03ffe15 	stw	zero,-8(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 801ae28:	e03ffd15 	stw	zero,-12(fp)
+    
+    /* add supported PHYs */
+    alt_tse_phy_add_profile_default();
+ 801ae2c:	8019b680 	call	8019b68 <alt_tse_phy_add_profile_default>
+    
+    /* display PHY in profile */
+    alt_tse_phy_print_profile();
+ 801ae30:	8019e300 	call	8019e30 <alt_tse_phy_print_profile>
+    
+    alt_tse_mac_group_init();
+ 801ae34:	801a0000 	call	801a000 <alt_tse_mac_group_init>
+        
+    /* initialize for each TSE MAC */
+    /* run once only for multi-channel MAC */
+    for(i = 0; i < mac_group_count; i++) {
+ 801ae38:	e03fffc5 	stb	zero,-1(fp)
+ 801ae3c:	00002c06 	br	801aef0 <alt_tse_phy_init+0xe4>
+        pmac_group = pmac_groups[i];
+ 801ae40:	e0bfffc7 	ldb	r2,-1(fp)
+ 801ae44:	100690ba 	slli	r3,r2,2
+ 801ae48:	008201b4 	movhi	r2,2054
+ 801ae4c:	1885883a 	add	r2,r3,r2
+ 801ae50:	10b5aa17 	ldw	r2,-10584(r2)
+ 801ae54:	e0bffe15 	stw	r2,-8(fp)
+        
+        if(pmac_group->pmac_info[0]->psys_info->tse_use_mdio) {
+ 801ae58:	e0bffe17 	ldw	r2,-8(fp)
+ 801ae5c:	10800117 	ldw	r2,4(r2)
+ 801ae60:	10800217 	ldw	r2,8(r2)
+ 801ae64:	10800303 	ldbu	r2,12(r2)
+ 801ae68:	10803fcc 	andi	r2,r2,255
+ 801ae6c:	10000326 	beq	r2,zero,801ae7c <alt_tse_phy_init+0x70>
+            
+            /* get connected PHYs */
+            alt_tse_mac_get_phy(pmac_group);
+ 801ae70:	e13ffe17 	ldw	r4,-8(fp)
+ 801ae74:	801a6980 	call	801a698 <alt_tse_mac_get_phy>
+ 801ae78:	00000706 	br	801ae98 <alt_tse_phy_init+0x8c>
+        }
+        else {
+            tse_dprintf(3, "WARNING : MAC Groups[%d]->pmac_info[%d] MDIO is not used, unable to run PHY detection\n", i, j);
+ 801ae7c:	e0bfffc7 	ldb	r2,-1(fp)
+ 801ae80:	e0ffff87 	ldb	r3,-2(fp)
+ 801ae84:	180d883a 	mov	r6,r3
+ 801ae88:	100b883a 	mov	r5,r2
+ 801ae8c:	01020174 	movhi	r4,2053
+ 801ae90:	2122bf04 	addi	r4,r4,-29956
+ 801ae94:	8002c780 	call	8002c78 <printf>
+        }
+        
+        /* Configure PCS mode if MAC+PCS system is used */
+        for(j = 0; j < pmac_group->channel; j++) {
+ 801ae98:	e03fff85 	stb	zero,-2(fp)
+ 801ae9c:	00000c06 	br	801aed0 <alt_tse_phy_init+0xc4>
+            pmac_info = pmac_group->pmac_info[j];
+ 801aea0:	e0bfff87 	ldb	r2,-2(fp)
+ 801aea4:	e0fffe17 	ldw	r3,-8(fp)
+ 801aea8:	10800044 	addi	r2,r2,1
+ 801aeac:	100490ba 	slli	r2,r2,2
+ 801aeb0:	1885883a 	add	r2,r3,r2
+ 801aeb4:	10800017 	ldw	r2,0(r2)
+ 801aeb8:	e0bffd15 	stw	r2,-12(fp)
+            
+            alt_tse_phy_cfg_pcs(pmac_info);
+ 801aebc:	e13ffd17 	ldw	r4,-12(fp)
+ 801aec0:	801ace40 	call	801ace4 <alt_tse_phy_cfg_pcs>
+        for(j = 0; j < pmac_group->channel; j++) {
+ 801aec4:	e0bfff83 	ldbu	r2,-2(fp)
+ 801aec8:	10800044 	addi	r2,r2,1
+ 801aecc:	e0bfff85 	stb	r2,-2(fp)
+ 801aed0:	e0ffff87 	ldb	r3,-2(fp)
+ 801aed4:	e0bffe17 	ldw	r2,-8(fp)
+ 801aed8:	10800003 	ldbu	r2,0(r2)
+ 801aedc:	10803fcc 	andi	r2,r2,255
+ 801aee0:	18bfef16 	blt	r3,r2,801aea0 <alt_tse_phy_init+0x94>
+    for(i = 0; i < mac_group_count; i++) {
+ 801aee4:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801aee8:	10800044 	addi	r2,r2,1
+ 801aeec:	e0bfffc5 	stb	r2,-1(fp)
+ 801aef0:	e0ffffc7 	ldb	r3,-1(fp)
+ 801aef4:	d0a05b43 	ldbu	r2,-32403(gp)
+ 801aef8:	10803fcc 	andi	r2,r2,255
+ 801aefc:	18bfd016 	blt	r3,r2,801ae40 <alt_tse_phy_init+0x34>
+        }
+    }
+                
+    return SUCCESS;
+ 801af00:	0005883a 	mov	r2,zero
+}
+ 801af04:	e037883a 	mov	sp,fp
+ 801af08:	dfc00117 	ldw	ra,4(sp)
+ 801af0c:	df000017 	ldw	fp,0(sp)
+ 801af10:	dec00204 	addi	sp,sp,8
+ 801af14:	f800283a 	ret
+
+0801af18 <alt_tse_phy_restart_an>:
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *                              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) {
+ 801af18:	defff704 	addi	sp,sp,-36
+ 801af1c:	dfc00815 	stw	ra,32(sp)
+ 801af20:	df000715 	stw	fp,28(sp)
+ 801af24:	df000704 	addi	fp,sp,28
+ 801af28:	e13ffb15 	stw	r4,-20(fp)
+ 801af2c:	e17ffa15 	stw	r5,-24(fp)
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801af30:	e0bffb17 	ldw	r2,-20(fp)
+ 801af34:	10800617 	ldw	r2,24(r2)
+ 801af38:	e0bfff15 	stw	r2,-4(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801af3c:	e0bfff17 	ldw	r2,-4(fp)
+ 801af40:	10800317 	ldw	r2,12(r2)
+ 801af44:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801af48:	e13fff17 	ldw	r4,-4(fp)
+ 801af4c:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801af50:	e0bffcc5 	stb	r2,-13(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801af54:	e13ffe17 	ldw	r4,-8(fp)
+ 801af58:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801af5c:	e0bffc85 	stb	r2,-14(fp)
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801af60:	e13ffb17 	ldw	r4,-20(fp)
+ 801af64:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801af68:	e0bffc45 	stb	r2,-15(fp)
+    
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801af6c:	e0bffb17 	ldw	r2,-20(fp)
+ 801af70:	10800003 	ldbu	r2,0(r2)
+ 801af74:	10803fcc 	andi	r2,r2,255
+ 801af78:	100b883a 	mov	r5,r2
+ 801af7c:	e13ffb17 	ldw	r4,-20(fp)
+ 801af80:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+ 801af84:	01c00044 	movi	r7,1
+ 801af88:	018000c4 	movi	r6,3
+ 801af8c:	01400044 	movi	r5,1
+ 801af90:	e13ffb17 	ldw	r4,-20(fp)
+ 801af94:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801af98:	10000d1e 	bne	r2,zero,801afd0 <alt_tse_phy_restart_an+0xb8>
+        tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index);
+ 801af9c:	e0bffc87 	ldb	r2,-14(fp)
+ 801afa0:	e0fffcc7 	ldb	r3,-13(fp)
+ 801afa4:	180d883a 	mov	r6,r3
+ 801afa8:	100b883a 	mov	r5,r2
+ 801afac:	01020174 	movhi	r4,2053
+ 801afb0:	2122d504 	addi	r4,r4,-29868
+ 801afb4:	8002c780 	call	8002c78 <printf>
+        
+        /* Restore previous MDIO address */
+        alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801afb8:	e0bffc43 	ldbu	r2,-15(fp)
+ 801afbc:	100b883a 	mov	r5,r2
+ 801afc0:	e13ffb17 	ldw	r4,-20(fp)
+ 801afc4:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+        
+        return TSE_PHY_AN_NOT_CAPABLE;
+ 801afc8:	00bfff84 	movi	r2,-2
+ 801afcc:	00003e06 	br	801b0c8 <alt_tse_phy_restart_an+0x1b0>
+    }
+    
+    /* enable Auto-Negotiation */    
+    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_AN_ENA, 1, 1);
+ 801afd0:	00800044 	movi	r2,1
+ 801afd4:	d8800015 	stw	r2,0(sp)
+ 801afd8:	01c00044 	movi	r7,1
+ 801afdc:	01800304 	movi	r6,12
+ 801afe0:	000b883a 	mov	r5,zero
+ 801afe4:	e13ffb17 	ldw	r4,-20(fp)
+ 801afe8:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+    
+    /* send PHY reset command */
+    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESTART_AN, 1, 1);
+ 801afec:	00800044 	movi	r2,1
+ 801aff0:	d8800015 	stw	r2,0(sp)
+ 801aff4:	01c00044 	movi	r7,1
+ 801aff8:	01800244 	movi	r6,9
+ 801affc:	000b883a 	mov	r5,zero
+ 801b000:	e13ffb17 	ldw	r4,-20(fp)
+ 801b004:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Restart Auto-Negotiation, checking PHY link...\n", mac_group_index, mac_info_index);
+ 801b008:	e0bffc87 	ldb	r2,-14(fp)
+ 801b00c:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b010:	180d883a 	mov	r6,r3
+ 801b014:	100b883a 	mov	r5,r2
+ 801b018:	01020174 	movhi	r4,2053
+ 801b01c:	2122e504 	addi	r4,r4,-29804
+ 801b020:	8002c780 	call	8002c78 <printf>
+    
+    alt_32 timeout = 0;
+ 801b024:	e03ffd15 	stw	zero,-12(fp)
+    while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ 
+ 801b028:	00001506 	br	801b080 <alt_tse_phy_restart_an+0x168>
+        if(timeout++ > timeout_threshold) {
+ 801b02c:	e0bffd17 	ldw	r2,-12(fp)
+ 801b030:	10c00044 	addi	r3,r2,1
+ 801b034:	e0fffd15 	stw	r3,-12(fp)
+ 801b038:	1007883a 	mov	r3,r2
+ 801b03c:	e0bffa17 	ldw	r2,-24(fp)
+ 801b040:	10c00d2e 	bgeu	r2,r3,801b078 <alt_tse_phy_restart_an+0x160>
+           tse_dprintf(4, "WARNING : PHY[%d.%d] - Auto-Negotiation FAILED\n", mac_group_index, mac_info_index);
+ 801b044:	e0bffc87 	ldb	r2,-14(fp)
+ 801b048:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b04c:	180d883a 	mov	r6,r3
+ 801b050:	100b883a 	mov	r5,r2
+ 801b054:	01020174 	movhi	r4,2053
+ 801b058:	2122f704 	addi	r4,r4,-29732
+ 801b05c:	8002c780 	call	8002c78 <printf>
+           
+           /* Restore previous MDIO address */
+           alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b060:	e0bffc43 	ldbu	r2,-15(fp)
+ 801b064:	100b883a 	mov	r5,r2
+ 801b068:	e13ffb17 	ldw	r4,-20(fp)
+ 801b06c:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+           
+           return TSE_PHY_AN_NOT_COMPLETE;
+ 801b070:	00bfffc4 	movi	r2,-1
+ 801b074:	00001406 	br	801b0c8 <alt_tse_phy_restart_an+0x1b0>
+        }
+        usleep(1000);
+ 801b078:	0100fa04 	movi	r4,1000
+ 801b07c:	803811c0 	call	803811c <usleep>
+    while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ 
+ 801b080:	01c00044 	movi	r7,1
+ 801b084:	01800144 	movi	r6,5
+ 801b088:	01400044 	movi	r5,1
+ 801b08c:	e13ffb17 	ldw	r4,-20(fp)
+ 801b090:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b094:	103fe526 	beq	r2,zero,801b02c <alt_tse_phy_restart_an+0x114>
+    }
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Auto-Negotiation PASSED\n", mac_group_index, mac_info_index);
+ 801b098:	e0bffc87 	ldb	r2,-14(fp)
+ 801b09c:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b0a0:	180d883a 	mov	r6,r3
+ 801b0a4:	100b883a 	mov	r5,r2
+ 801b0a8:	01020174 	movhi	r4,2053
+ 801b0ac:	21230304 	addi	r4,r4,-29684
+ 801b0b0:	8002c780 	call	8002c78 <printf>
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b0b4:	e0bffc43 	ldbu	r2,-15(fp)
+ 801b0b8:	100b883a 	mov	r5,r2
+ 801b0bc:	e13ffb17 	ldw	r4,-20(fp)
+ 801b0c0:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    return TSE_PHY_AN_COMPLETE;
+ 801b0c4:	0005883a 	mov	r2,zero
+}
+ 801b0c8:	e037883a 	mov	sp,fp
+ 801b0cc:	dfc00117 	ldw	ra,4(sp)
+ 801b0d0:	df000017 	ldw	fp,0(sp)
+ 801b0d4:	dec00204 	addi	sp,sp,8
+ 801b0d8:	f800283a 	ret
+
+0801b0dc <alt_tse_phy_check_link>:
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ */
+alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold)
+{
+ 801b0dc:	defff804 	addi	sp,sp,-32
+ 801b0e0:	dfc00715 	stw	ra,28(sp)
+ 801b0e4:	df000615 	stw	fp,24(sp)
+ 801b0e8:	df000604 	addi	fp,sp,24
+ 801b0ec:	e13ffb15 	stw	r4,-20(fp)
+ 801b0f0:	e17ffa15 	stw	r5,-24(fp)
+    alt_32 timeout=0;
+ 801b0f4:	e03fff15 	stw	zero,-4(fp)
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801b0f8:	e0bffb17 	ldw	r2,-20(fp)
+ 801b0fc:	10800617 	ldw	r2,24(r2)
+ 801b100:	e0bffe15 	stw	r2,-8(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801b104:	e0bffe17 	ldw	r2,-8(fp)
+ 801b108:	10800317 	ldw	r2,12(r2)
+ 801b10c:	e0bffd15 	stw	r2,-12(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801b110:	e13ffe17 	ldw	r4,-8(fp)
+ 801b114:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801b118:	e0bffcc5 	stb	r2,-13(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); 
+ 801b11c:	e13ffd17 	ldw	r4,-12(fp)
+ 801b120:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801b124:	e0bffc85 	stb	r2,-14(fp)
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801b128:	e13ffb17 	ldw	r4,-20(fp)
+ 801b12c:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801b130:	e0bffc45 	stb	r2,-15(fp)
+    
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801b134:	e0bffb17 	ldw	r2,-20(fp)
+ 801b138:	10800003 	ldbu	r2,0(r2)
+ 801b13c:	10803fcc 	andi	r2,r2,255
+ 801b140:	100b883a 	mov	r5,r2
+ 801b144:	e13ffb17 	ldw	r4,-20(fp)
+ 801b148:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    /* Issue a PHY reset here and wait for the link
+     * autonegotiation complete again... this takes several SECONDS(!)
+     * so be very careful not to do it frequently
+     * perform this when PHY is configured in loopback or has no link yet.
+     */
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Checking link...\n", mac_group_index, mac_info_index);
+ 801b14c:	e0bffc87 	ldb	r2,-14(fp)
+ 801b150:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b154:	180d883a 	mov	r6,r3
+ 801b158:	100b883a 	mov	r5,r2
+ 801b15c:	01020174 	movhi	r4,2053
+ 801b160:	21230f04 	addi	r4,r4,-29636
+ 801b164:	8002c780 	call	8002c78 <printf>
+    while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) ||
+ 801b168:	00002106 	br	801b1f0 <alt_tse_phy_check_link+0x114>
+        ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) )
+    {                 
+        if (timeout++ > timeout_threshold) 
+ 801b16c:	e0bfff17 	ldw	r2,-4(fp)
+ 801b170:	10c00044 	addi	r3,r2,1
+ 801b174:	e0ffff15 	stw	r3,-4(fp)
+ 801b178:	1007883a 	mov	r3,r2
+ 801b17c:	e0bffa17 	ldw	r2,-24(fp)
+ 801b180:	10c0192e 	bgeu	r2,r3,801b1e8 <alt_tse_phy_check_link+0x10c>
+        {    
+          tse_dprintf(5, "INFO    : PHY[%d.%d] - Link not yet established, restart auto-negotiation...\n", mac_group_index, mac_info_index);
+ 801b184:	e0bffc87 	ldb	r2,-14(fp)
+ 801b188:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b18c:	180d883a 	mov	r6,r3
+ 801b190:	100b883a 	mov	r5,r2
+ 801b194:	01020174 	movhi	r4,2053
+ 801b198:	21231a04 	addi	r4,r4,-29592
+ 801b19c:	8002c780 	call	8002c78 <printf>
+          /* restart Auto-Negotiation */
+          /* if Auto-Negotiation still cannot complete, then go to next PHY */
+          if(alt_tse_phy_restart_an(pphy, timeout_threshold) == TSE_PHY_AN_NOT_COMPLETE)
+ 801b1a0:	e17ffa17 	ldw	r5,-24(fp)
+ 801b1a4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b1a8:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+ 801b1ac:	10bfffd8 	cmpnei	r2,r2,-1
+ 801b1b0:	10000d1e 	bne	r2,zero,801b1e8 <alt_tse_phy_check_link+0x10c>
+          {
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - Link could not established\n", mac_group_index, mac_info_index);
+ 801b1b4:	e0bffc87 	ldb	r2,-14(fp)
+ 801b1b8:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b1bc:	180d883a 	mov	r6,r3
+ 801b1c0:	100b883a 	mov	r5,r2
+ 801b1c4:	01020174 	movhi	r4,2053
+ 801b1c8:	21232e04 	addi	r4,r4,-29512
+ 801b1cc:	8002c780 	call	8002c78 <printf>
+            
+            /* Restore previous MDIO address */
+            alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b1d0:	e0bffc43 	ldbu	r2,-15(fp)
+ 801b1d4:	100b883a 	mov	r5,r2
+ 801b1d8:	e13ffb17 	ldw	r4,-20(fp)
+ 801b1dc:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+            return TSE_PHY_AN_NOT_COMPLETE;
+ 801b1e0:	00bfffc4 	movi	r2,-1
+ 801b1e4:	00001a06 	br	801b250 <alt_tse_phy_check_link+0x174>
+          } 
+        }   
+        usleep(1000);        
+ 801b1e8:	0100fa04 	movi	r4,1000
+ 801b1ec:	803811c0 	call	803811c <usleep>
+    while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) ||
+ 801b1f0:	01c00044 	movi	r7,1
+ 801b1f4:	01800384 	movi	r6,14
+ 801b1f8:	000b883a 	mov	r5,zero
+ 801b1fc:	e13ffb17 	ldw	r4,-20(fp)
+ 801b200:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b204:	103fd91e 	bne	r2,zero,801b16c <alt_tse_phy_check_link+0x90>
+        ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) )
+ 801b208:	01c00044 	movi	r7,1
+ 801b20c:	01800144 	movi	r6,5
+ 801b210:	01400044 	movi	r5,1
+ 801b214:	e13ffb17 	ldw	r4,-20(fp)
+ 801b218:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+    while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) ||
+ 801b21c:	103fd326 	beq	r2,zero,801b16c <alt_tse_phy_check_link+0x90>
+    }
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Link established\n", mac_group_index, mac_info_index);
+ 801b220:	e0bffc87 	ldb	r2,-14(fp)
+ 801b224:	e0fffcc7 	ldb	r3,-13(fp)
+ 801b228:	180d883a 	mov	r6,r3
+ 801b22c:	100b883a 	mov	r5,r2
+ 801b230:	01020174 	movhi	r4,2053
+ 801b234:	21233b04 	addi	r4,r4,-29460
+ 801b238:	8002c780 	call	8002c78 <printf>
+            
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b23c:	e0bffc43 	ldbu	r2,-15(fp)
+ 801b240:	100b883a 	mov	r5,r2
+ 801b244:	e13ffb17 	ldw	r4,-20(fp)
+ 801b248:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    return TSE_PHY_AN_COMPLETE; 
+ 801b24c:	0005883a 	mov	r2,zero
+}
+ 801b250:	e037883a 	mov	sp,fp
+ 801b254:	dfc00117 	ldw	ra,4(sp)
+ 801b258:	df000017 	ldw	fp,0(sp)
+ 801b25c:	dec00204 	addi	sp,sp,8
+ 801b260:	f800283a 	ret
+
+0801b264 <alt_tse_phy_get_cap>:
+ * @param pmac  Pointer to the alt_tse_phy_info structure
+ * @return      return TSE_PHY_AN_COMPLETE if success
+ *              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy) {
+ 801b264:	defff904 	addi	sp,sp,-28
+ 801b268:	dfc00615 	stw	ra,24(sp)
+ 801b26c:	df000515 	stw	fp,20(sp)
+ 801b270:	df000504 	addi	fp,sp,20
+ 801b274:	e13ffb15 	stw	r4,-20(fp)
+    alt_32 return_value = TSE_PHY_AN_COMPLETE;
+ 801b278:	e03fff15 	stw	zero,-4(fp)
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801b27c:	e0bffb17 	ldw	r2,-20(fp)
+ 801b280:	10800617 	ldw	r2,24(r2)
+ 801b284:	e0bffd15 	stw	r2,-12(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801b288:	e0bffd17 	ldw	r2,-12(fp)
+ 801b28c:	10800317 	ldw	r2,12(r2)
+ 801b290:	e0bffc15 	stw	r2,-16(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801b294:	e13ffd17 	ldw	r4,-12(fp)
+ 801b298:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801b29c:	e0bffe45 	stb	r2,-7(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);    
+ 801b2a0:	e13ffc17 	ldw	r4,-16(fp)
+ 801b2a4:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801b2a8:	e0bffe85 	stb	r2,-6(fp)
+        
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801b2ac:	e13ffb17 	ldw	r4,-20(fp)
+ 801b2b0:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801b2b4:	e0bffec5 	stb	r2,-5(fp)
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801b2b8:	e0bffb17 	ldw	r2,-20(fp)
+ 801b2bc:	10800003 	ldbu	r2,0(r2)
+ 801b2c0:	10803fcc 	andi	r2,r2,255
+ 801b2c4:	100b883a 	mov	r5,r2
+ 801b2c8:	e13ffb17 	ldw	r4,-20(fp)
+ 801b2cc:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+            
+    if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+ 801b2d0:	01c00044 	movi	r7,1
+ 801b2d4:	018000c4 	movi	r6,3
+ 801b2d8:	01400044 	movi	r5,1
+ 801b2dc:	e13ffb17 	ldw	r4,-20(fp)
+ 801b2e0:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b2e4:	10000d1e 	bne	r2,zero,801b31c <alt_tse_phy_get_cap+0xb8>
+        tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index);
+ 801b2e8:	e0bffe87 	ldb	r2,-6(fp)
+ 801b2ec:	e0fffe47 	ldb	r3,-7(fp)
+ 801b2f0:	180d883a 	mov	r6,r3
+ 801b2f4:	100b883a 	mov	r5,r2
+ 801b2f8:	01020174 	movhi	r4,2053
+ 801b2fc:	2122d504 	addi	r4,r4,-29868
+ 801b300:	8002c780 	call	8002c78 <printf>
+        
+        /* Restore previous MDIO address */
+        alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b304:	e0bffec3 	ldbu	r2,-5(fp)
+ 801b308:	100b883a 	mov	r5,r2
+ 801b30c:	e13ffb17 	ldw	r4,-20(fp)
+ 801b310:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+        
+        return TSE_PHY_AN_NOT_CAPABLE;
+ 801b314:	00bfff84 	movi	r2,-2
+ 801b318:	00013006 	br	801b7dc <alt_tse_phy_get_cap+0x578>
+    }
+    
+    /* check whether link has been established */
+    alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+ 801b31c:	01427104 	movi	r5,2500
+ 801b320:	e13ffb17 	ldw	r4,-20(fp)
+ 801b324:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+    
+    if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0) {
+ 801b328:	01c00044 	movi	r7,1
+ 801b32c:	01800144 	movi	r6,5
+ 801b330:	01400044 	movi	r5,1
+ 801b334:	e13ffb17 	ldw	r4,-20(fp)
+ 801b338:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b33c:	1000021e 	bne	r2,zero,801b348 <alt_tse_phy_get_cap+0xe4>
+        return_value = TSE_PHY_AN_NOT_COMPLETE;
+ 801b340:	00bfffc4 	movi	r2,-1
+ 801b344:	e0bfff15 	stw	r2,-4(fp)
+    }
+    
+    /* get PHY capabilities */
+    pphy->link_capability.cap_1000_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL, 1);
+ 801b348:	01c00044 	movi	r7,1
+ 801b34c:	018003c4 	movi	r6,15
+ 801b350:	014003c4 	movi	r5,15
+ 801b354:	e13ffb17 	ldw	r4,-20(fp)
+ 801b358:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b35c:	1007883a 	mov	r3,r2
+ 801b360:	e0bffb17 	ldw	r2,-20(fp)
+ 801b364:	10c00045 	stb	r3,1(r2)
+    pphy->link_capability.cap_1000_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF, 1);
+ 801b368:	01c00044 	movi	r7,1
+ 801b36c:	01800384 	movi	r6,14
+ 801b370:	014003c4 	movi	r5,15
+ 801b374:	e13ffb17 	ldw	r4,-20(fp)
+ 801b378:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b37c:	1007883a 	mov	r3,r2
+ 801b380:	e0bffb17 	ldw	r2,-20(fp)
+ 801b384:	10c00085 	stb	r3,2(r2)
+    pphy->link_capability.cap_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1);
+ 801b388:	01c00044 	movi	r7,1
+ 801b38c:	01800344 	movi	r6,13
+ 801b390:	014003c4 	movi	r5,15
+ 801b394:	e13ffb17 	ldw	r4,-20(fp)
+ 801b398:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b39c:	1007883a 	mov	r3,r2
+ 801b3a0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b3a4:	10c000c5 	stb	r3,3(r2)
+    pphy->link_capability.cap_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1);
+ 801b3a8:	01c00044 	movi	r7,1
+ 801b3ac:	01800304 	movi	r6,12
+ 801b3b0:	014003c4 	movi	r5,15
+ 801b3b4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b3b8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b3bc:	1007883a 	mov	r3,r2
+ 801b3c0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b3c4:	10c00105 	stb	r3,4(r2)
+    
+    pphy->link_capability.cap_100_base_t4      = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1);
+ 801b3c8:	01c00044 	movi	r7,1
+ 801b3cc:	018003c4 	movi	r6,15
+ 801b3d0:	01400044 	movi	r5,1
+ 801b3d4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b3d8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b3dc:	1007883a 	mov	r3,r2
+ 801b3e0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b3e4:	10c00145 	stb	r3,5(r2)
+    pphy->link_capability.cap_100_base_x_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1);
+ 801b3e8:	01c00044 	movi	r7,1
+ 801b3ec:	01800384 	movi	r6,14
+ 801b3f0:	01400044 	movi	r5,1
+ 801b3f4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b3f8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b3fc:	1007883a 	mov	r3,r2
+ 801b400:	e0bffb17 	ldw	r2,-20(fp)
+ 801b404:	10c00185 	stb	r3,6(r2)
+    pphy->link_capability.cap_100_base_x_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1);
+ 801b408:	01c00044 	movi	r7,1
+ 801b40c:	01800344 	movi	r6,13
+ 801b410:	01400044 	movi	r5,1
+ 801b414:	e13ffb17 	ldw	r4,-20(fp)
+ 801b418:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b41c:	1007883a 	mov	r3,r2
+ 801b420:	e0bffb17 	ldw	r2,-20(fp)
+ 801b424:	10c001c5 	stb	r3,7(r2)
+    pphy->link_capability.cap_100_base_t2_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_FULL, 1);
+ 801b428:	01c00044 	movi	r7,1
+ 801b42c:	01800284 	movi	r6,10
+ 801b430:	01400044 	movi	r5,1
+ 801b434:	e13ffb17 	ldw	r4,-20(fp)
+ 801b438:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b43c:	1007883a 	mov	r3,r2
+ 801b440:	e0bffb17 	ldw	r2,-20(fp)
+ 801b444:	10c00205 	stb	r3,8(r2)
+    pphy->link_capability.cap_100_base_t2_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_HALF, 1);
+ 801b448:	01c00044 	movi	r7,1
+ 801b44c:	01800244 	movi	r6,9
+ 801b450:	01400044 	movi	r5,1
+ 801b454:	e13ffb17 	ldw	r4,-20(fp)
+ 801b458:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b45c:	1007883a 	mov	r3,r2
+ 801b460:	e0bffb17 	ldw	r2,-20(fp)
+ 801b464:	10c00245 	stb	r3,9(r2)
+    pphy->link_capability.cap_10_base_t_full   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1);
+ 801b468:	01c00044 	movi	r7,1
+ 801b46c:	01800304 	movi	r6,12
+ 801b470:	01400044 	movi	r5,1
+ 801b474:	e13ffb17 	ldw	r4,-20(fp)
+ 801b478:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b47c:	1007883a 	mov	r3,r2
+ 801b480:	e0bffb17 	ldw	r2,-20(fp)
+ 801b484:	10c00285 	stb	r3,10(r2)
+    pphy->link_capability.cap_10_base_t_half   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1);
+ 801b488:	01c00044 	movi	r7,1
+ 801b48c:	018002c4 	movi	r6,11
+ 801b490:	01400044 	movi	r5,1
+ 801b494:	e13ffb17 	ldw	r4,-20(fp)
+ 801b498:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b49c:	1007883a 	mov	r3,r2
+ 801b4a0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b4a4:	10c002c5 	stb	r3,11(r2)
+    
+    /* get link partner capability */
+    pphy->link_capability.lp_1000_base_t_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV, 1);
+ 801b4a8:	01c00044 	movi	r7,1
+ 801b4ac:	018002c4 	movi	r6,11
+ 801b4b0:	01400284 	movi	r5,10
+ 801b4b4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b4b8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b4bc:	1007883a 	mov	r3,r2
+ 801b4c0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b4c4:	10c00305 	stb	r3,12(r2)
+    pphy->link_capability.lp_1000_base_t_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV, 1);
+ 801b4c8:	01c00044 	movi	r7,1
+ 801b4cc:	01800284 	movi	r6,10
+ 801b4d0:	01400284 	movi	r5,10
+ 801b4d4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b4d8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b4dc:	1007883a 	mov	r3,r2
+ 801b4e0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b4e4:	10c00345 	stb	r3,13(r2)
+    
+    pphy->link_capability.lp_100_base_t4       = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1);
+ 801b4e8:	01c00044 	movi	r7,1
+ 801b4ec:	01800244 	movi	r6,9
+ 801b4f0:	01400144 	movi	r5,5
+ 801b4f4:	e13ffb17 	ldw	r4,-20(fp)
+ 801b4f8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b4fc:	1007883a 	mov	r3,r2
+ 801b500:	e0bffb17 	ldw	r2,-20(fp)
+ 801b504:	10c00385 	stb	r3,14(r2)
+    pphy->link_capability.lp_100_base_tx_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1);
+ 801b508:	01c00044 	movi	r7,1
+ 801b50c:	01800204 	movi	r6,8
+ 801b510:	01400144 	movi	r5,5
+ 801b514:	e13ffb17 	ldw	r4,-20(fp)
+ 801b518:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b51c:	1007883a 	mov	r3,r2
+ 801b520:	e0bffb17 	ldw	r2,-20(fp)
+ 801b524:	10c003c5 	stb	r3,15(r2)
+    pphy->link_capability.lp_100_base_tx_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1);
+ 801b528:	01c00044 	movi	r7,1
+ 801b52c:	018001c4 	movi	r6,7
+ 801b530:	01400144 	movi	r5,5
+ 801b534:	e13ffb17 	ldw	r4,-20(fp)
+ 801b538:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b53c:	1007883a 	mov	r3,r2
+ 801b540:	e0bffb17 	ldw	r2,-20(fp)
+ 801b544:	10c00405 	stb	r3,16(r2)
+    pphy->link_capability.lp_10_base_tx_full   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1);
+ 801b548:	01c00044 	movi	r7,1
+ 801b54c:	01800184 	movi	r6,6
+ 801b550:	01400144 	movi	r5,5
+ 801b554:	e13ffb17 	ldw	r4,-20(fp)
+ 801b558:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b55c:	1007883a 	mov	r3,r2
+ 801b560:	e0bffb17 	ldw	r2,-20(fp)
+ 801b564:	10c00445 	stb	r3,17(r2)
+    pphy->link_capability.lp_10_base_tx_half   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1);
+ 801b568:	01c00044 	movi	r7,1
+ 801b56c:	01800144 	movi	r6,5
+ 801b570:	01400144 	movi	r5,5
+ 801b574:	e13ffb17 	ldw	r4,-20(fp)
+ 801b578:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b57c:	1007883a 	mov	r3,r2
+ 801b580:	e0bffb17 	ldw	r2,-20(fp)
+ 801b584:	10c00485 	stb	r3,18(r2)
+    
+    tse_dprintf(6, "INFO    : PHY[%d.%d] - Capability of PHY :\n", mac_group_index, mac_info_index);
+ 801b588:	e0bffe87 	ldb	r2,-6(fp)
+ 801b58c:	e0fffe47 	ldb	r3,-7(fp)
+ 801b590:	180d883a 	mov	r6,r3
+ 801b594:	100b883a 	mov	r5,r2
+ 801b598:	01020174 	movhi	r4,2053
+ 801b59c:	21234604 	addi	r4,r4,-29416
+ 801b5a0:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-X Full Duplex = %d\n", pphy->link_capability.cap_1000_base_x_full);
+ 801b5a4:	e0bffb17 	ldw	r2,-20(fp)
+ 801b5a8:	10800043 	ldbu	r2,1(r2)
+ 801b5ac:	10803fcc 	andi	r2,r2,255
+ 801b5b0:	100b883a 	mov	r5,r2
+ 801b5b4:	01020174 	movhi	r4,2053
+ 801b5b8:	21235104 	addi	r4,r4,-29372
+ 801b5bc:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-X Half Duplex = %d\n", pphy->link_capability.cap_1000_base_x_half);
+ 801b5c0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b5c4:	10800083 	ldbu	r2,2(r2)
+ 801b5c8:	10803fcc 	andi	r2,r2,255
+ 801b5cc:	100b883a 	mov	r5,r2
+ 801b5d0:	01020174 	movhi	r4,2053
+ 801b5d4:	21235b04 	addi	r4,r4,-29332
+ 801b5d8:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.cap_1000_base_t_full);
+ 801b5dc:	e0bffb17 	ldw	r2,-20(fp)
+ 801b5e0:	108000c3 	ldbu	r2,3(r2)
+ 801b5e4:	10803fcc 	andi	r2,r2,255
+ 801b5e8:	100b883a 	mov	r5,r2
+ 801b5ec:	01020174 	movhi	r4,2053
+ 801b5f0:	21236504 	addi	r4,r4,-29292
+ 801b5f4:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.cap_1000_base_t_half);
+ 801b5f8:	e0bffb17 	ldw	r2,-20(fp)
+ 801b5fc:	10800103 	ldbu	r2,4(r2)
+ 801b600:	10803fcc 	andi	r2,r2,255
+ 801b604:	100b883a 	mov	r5,r2
+ 801b608:	01020174 	movhi	r4,2053
+ 801b60c:	21236f04 	addi	r4,r4,-29252
+ 801b610:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-T4             = %d\n", pphy->link_capability.cap_100_base_t4);
+ 801b614:	e0bffb17 	ldw	r2,-20(fp)
+ 801b618:	10800143 	ldbu	r2,5(r2)
+ 801b61c:	10803fcc 	andi	r2,r2,255
+ 801b620:	100b883a 	mov	r5,r2
+ 801b624:	01020174 	movhi	r4,2053
+ 801b628:	21237904 	addi	r4,r4,-29212
+ 801b62c:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-X Full Duplex  = %d\n", pphy->link_capability.cap_100_base_x_full);
+ 801b630:	e0bffb17 	ldw	r2,-20(fp)
+ 801b634:	10800183 	ldbu	r2,6(r2)
+ 801b638:	10803fcc 	andi	r2,r2,255
+ 801b63c:	100b883a 	mov	r5,r2
+ 801b640:	01020174 	movhi	r4,2053
+ 801b644:	21238304 	addi	r4,r4,-29172
+ 801b648:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-X Half Duplex  = %d\n", pphy->link_capability.cap_100_base_x_half);
+ 801b64c:	e0bffb17 	ldw	r2,-20(fp)
+ 801b650:	108001c3 	ldbu	r2,7(r2)
+ 801b654:	10803fcc 	andi	r2,r2,255
+ 801b658:	100b883a 	mov	r5,r2
+ 801b65c:	01020174 	movhi	r4,2053
+ 801b660:	21238d04 	addi	r4,r4,-29132
+ 801b664:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-T2 Full Duplex = %d\n", pphy->link_capability.cap_100_base_t2_full);
+ 801b668:	e0bffb17 	ldw	r2,-20(fp)
+ 801b66c:	10800203 	ldbu	r2,8(r2)
+ 801b670:	10803fcc 	andi	r2,r2,255
+ 801b674:	100b883a 	mov	r5,r2
+ 801b678:	01020174 	movhi	r4,2053
+ 801b67c:	21239704 	addi	r4,r4,-29092
+ 801b680:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-T2 Half Duplex = %d\n", pphy->link_capability.cap_100_base_t2_half);
+ 801b684:	e0bffb17 	ldw	r2,-20(fp)
+ 801b688:	10800243 	ldbu	r2,9(r2)
+ 801b68c:	10803fcc 	andi	r2,r2,255
+ 801b690:	100b883a 	mov	r5,r2
+ 801b694:	01020174 	movhi	r4,2053
+ 801b698:	2123a104 	addi	r4,r4,-29052
+ 801b69c:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 10 Base-T Full Duplex   = %d\n", pphy->link_capability.cap_10_base_t_full);
+ 801b6a0:	e0bffb17 	ldw	r2,-20(fp)
+ 801b6a4:	10800283 	ldbu	r2,10(r2)
+ 801b6a8:	10803fcc 	andi	r2,r2,255
+ 801b6ac:	100b883a 	mov	r5,r2
+ 801b6b0:	01020174 	movhi	r4,2053
+ 801b6b4:	2123ab04 	addi	r4,r4,-29012
+ 801b6b8:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 10 Base-T Half Duplex   = %d\n", pphy->link_capability.cap_10_base_t_half);
+ 801b6bc:	e0bffb17 	ldw	r2,-20(fp)
+ 801b6c0:	108002c3 	ldbu	r2,11(r2)
+ 801b6c4:	10803fcc 	andi	r2,r2,255
+ 801b6c8:	100b883a 	mov	r5,r2
+ 801b6cc:	01020174 	movhi	r4,2053
+ 801b6d0:	2123b504 	addi	r4,r4,-28972
+ 801b6d4:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "\n");
+ 801b6d8:	01000284 	movi	r4,10
+ 801b6dc:	8002cb80 	call	8002cb8 <putchar>
+    
+    tse_dprintf(6, "INFO    : PHY[%d.%d] - Link Partner Capability :\n", mac_group_index, mac_info_index);
+ 801b6e0:	e0bffe87 	ldb	r2,-6(fp)
+ 801b6e4:	e0fffe47 	ldb	r3,-7(fp)
+ 801b6e8:	180d883a 	mov	r6,r3
+ 801b6ec:	100b883a 	mov	r5,r2
+ 801b6f0:	01020174 	movhi	r4,2053
+ 801b6f4:	2123bf04 	addi	r4,r4,-28932
+ 801b6f8:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.lp_1000_base_t_full);
+ 801b6fc:	e0bffb17 	ldw	r2,-20(fp)
+ 801b700:	10800303 	ldbu	r2,12(r2)
+ 801b704:	10803fcc 	andi	r2,r2,255
+ 801b708:	100b883a 	mov	r5,r2
+ 801b70c:	01020174 	movhi	r4,2053
+ 801b710:	21236504 	addi	r4,r4,-29292
+ 801b714:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.lp_1000_base_t_half);
+ 801b718:	e0bffb17 	ldw	r2,-20(fp)
+ 801b71c:	10800343 	ldbu	r2,13(r2)
+ 801b720:	10803fcc 	andi	r2,r2,255
+ 801b724:	100b883a 	mov	r5,r2
+ 801b728:	01020174 	movhi	r4,2053
+ 801b72c:	21236f04 	addi	r4,r4,-29252
+ 801b730:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-T4             = %d\n", pphy->link_capability.lp_100_base_t4);
+ 801b734:	e0bffb17 	ldw	r2,-20(fp)
+ 801b738:	10800383 	ldbu	r2,14(r2)
+ 801b73c:	10803fcc 	andi	r2,r2,255
+ 801b740:	100b883a 	mov	r5,r2
+ 801b744:	01020174 	movhi	r4,2053
+ 801b748:	21237904 	addi	r4,r4,-29212
+ 801b74c:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_100_base_tx_full);
+ 801b750:	e0bffb17 	ldw	r2,-20(fp)
+ 801b754:	108003c3 	ldbu	r2,15(r2)
+ 801b758:	10803fcc 	andi	r2,r2,255
+ 801b75c:	100b883a 	mov	r5,r2
+ 801b760:	01020174 	movhi	r4,2053
+ 801b764:	2123cc04 	addi	r4,r4,-28880
+ 801b768:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 100 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_100_base_tx_half);
+ 801b76c:	e0bffb17 	ldw	r2,-20(fp)
+ 801b770:	10800403 	ldbu	r2,16(r2)
+ 801b774:	10803fcc 	andi	r2,r2,255
+ 801b778:	100b883a 	mov	r5,r2
+ 801b77c:	01020174 	movhi	r4,2053
+ 801b780:	2123d604 	addi	r4,r4,-28840
+ 801b784:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 10 Base-TX Full Duplex  = %d\n", pphy->link_capability.lp_10_base_tx_full);
+ 801b788:	e0bffb17 	ldw	r2,-20(fp)
+ 801b78c:	10800443 	ldbu	r2,17(r2)
+ 801b790:	10803fcc 	andi	r2,r2,255
+ 801b794:	100b883a 	mov	r5,r2
+ 801b798:	01020174 	movhi	r4,2053
+ 801b79c:	2123e004 	addi	r4,r4,-28800
+ 801b7a0:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "INFO    : 10 Base-TX Half Duplex  = %d\n", pphy->link_capability.lp_10_base_tx_half);
+ 801b7a4:	e0bffb17 	ldw	r2,-20(fp)
+ 801b7a8:	10800483 	ldbu	r2,18(r2)
+ 801b7ac:	10803fcc 	andi	r2,r2,255
+ 801b7b0:	100b883a 	mov	r5,r2
+ 801b7b4:	01020174 	movhi	r4,2053
+ 801b7b8:	2123ea04 	addi	r4,r4,-28760
+ 801b7bc:	8002c780 	call	8002c78 <printf>
+    tse_dprintf(6, "\n");
+ 801b7c0:	01000284 	movi	r4,10
+ 801b7c4:	8002cb80 	call	8002cb8 <putchar>
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801b7c8:	e0bffec3 	ldbu	r2,-5(fp)
+ 801b7cc:	100b883a 	mov	r5,r2
+ 801b7d0:	e13ffb17 	ldw	r4,-20(fp)
+ 801b7d4:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    return return_value;
+ 801b7d8:	e0bfff17 	ldw	r2,-4(fp)
+    
+}
+ 801b7dc:	e037883a 	mov	sp,fp
+ 801b7e0:	dfc00117 	ldw	ra,4(sp)
+ 801b7e4:	df000017 	ldw	fp,0(sp)
+ 801b7e8:	dec00204 	addi	sp,sp,8
+ 801b7ec:	f800283a 	ret
+
+0801b7f0 <alt_tse_phy_set_adv_1000>:
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable) {
+ 801b7f0:	defff604 	addi	sp,sp,-40
+ 801b7f4:	dfc00915 	stw	ra,36(sp)
+ 801b7f8:	df000815 	stw	fp,32(sp)
+ 801b7fc:	df000804 	addi	fp,sp,32
+ 801b800:	e13ffa15 	stw	r4,-24(fp)
+ 801b804:	2805883a 	mov	r2,r5
+ 801b808:	e0bff905 	stb	r2,-28(fp)
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801b80c:	e0bffa17 	ldw	r2,-24(fp)
+ 801b810:	10800617 	ldw	r2,24(r2)
+ 801b814:	e0bffc15 	stw	r2,-16(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801b818:	e0bffc17 	ldw	r2,-16(fp)
+ 801b81c:	10800317 	ldw	r2,12(r2)
+ 801b820:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801b824:	e13ffc17 	ldw	r4,-16(fp)
+ 801b828:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801b82c:	e0bffdc5 	stb	r2,-9(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801b830:	e13ffe17 	ldw	r4,-8(fp)
+ 801b834:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801b838:	e0bfffc5 	stb	r2,-1(fp)
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801b83c:	e13ffa17 	ldw	r4,-24(fp)
+ 801b840:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801b844:	e0bffbc5 	stb	r2,-17(fp)
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801b848:	e0bffa17 	ldw	r2,-24(fp)
+ 801b84c:	10800003 	ldbu	r2,0(r2)
+ 801b850:	10803fcc 	andi	r2,r2,255
+ 801b854:	100b883a 	mov	r5,r2
+ 801b858:	e13ffa17 	ldw	r4,-24(fp)
+ 801b85c:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+ 801b860:	e0bff903 	ldbu	r2,-28(fp)
+ 801b864:	10002d26 	beq	r2,zero,801b91c <alt_tse_phy_set_adv_1000+0x12c>
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); 
+ 801b868:	01c00044 	movi	r7,1
+ 801b86c:	01800344 	movi	r6,13
+ 801b870:	014003c4 	movi	r5,15
+ 801b874:	e13ffa17 	ldw	r4,-24(fp)
+ 801b878:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b87c:	e0bffb85 	stb	r2,-18(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, cap);
+ 801b880:	e0bffb83 	ldbu	r2,-18(fp)
+ 801b884:	d8800015 	stw	r2,0(sp)
+ 801b888:	01c00044 	movi	r7,1
+ 801b88c:	01800244 	movi	r6,9
+ 801b890:	01400244 	movi	r5,9
+ 801b894:	e13ffa17 	ldw	r4,-24(fp)
+ 801b898:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801b89c:	e0bfffc7 	ldb	r2,-1(fp)
+ 801b8a0:	e0fffdc7 	ldb	r3,-9(fp)
+ 801b8a4:	e13ffb83 	ldbu	r4,-18(fp)
+ 801b8a8:	200f883a 	mov	r7,r4
+ 801b8ac:	180d883a 	mov	r6,r3
+ 801b8b0:	100b883a 	mov	r5,r2
+ 801b8b4:	01020174 	movhi	r4,2053
+ 801b8b8:	2123f404 	addi	r4,r4,-28720
+ 801b8bc:	8002c780 	call	8002c78 <printf>
+        
+        /* 1000 Mbps Half duplex not supported by TSE MAC */
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1);
+ 801b8c0:	01c00044 	movi	r7,1
+ 801b8c4:	01800304 	movi	r6,12
+ 801b8c8:	014003c4 	movi	r5,15
+ 801b8cc:	e13ffa17 	ldw	r4,-24(fp)
+ 801b8d0:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801b8d4:	e0bffb85 	stb	r2,-18(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, cap);
+ 801b8d8:	e0bffb83 	ldbu	r2,-18(fp)
+ 801b8dc:	d8800015 	stw	r2,0(sp)
+ 801b8e0:	01c00044 	movi	r7,1
+ 801b8e4:	01800204 	movi	r6,8
+ 801b8e8:	01400244 	movi	r5,9
+ 801b8ec:	e13ffa17 	ldw	r4,-24(fp)
+ 801b8f0:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801b8f4:	e0bfffc7 	ldb	r2,-1(fp)
+ 801b8f8:	e0fffdc7 	ldb	r3,-9(fp)
+ 801b8fc:	e13ffb83 	ldbu	r4,-18(fp)
+ 801b900:	200f883a 	mov	r7,r4
+ 801b904:	180d883a 	mov	r6,r3
+ 801b908:	100b883a 	mov	r5,r2
+ 801b90c:	01020174 	movhi	r4,2053
+ 801b910:	21240704 	addi	r4,r4,-28644
+ 801b914:	8002c780 	call	8002c78 <printf>
+ 801b918:	00001c06 	br	801b98c <alt_tse_phy_set_adv_1000+0x19c>
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, 0);
+ 801b91c:	d8000015 	stw	zero,0(sp)
+ 801b920:	01c00044 	movi	r7,1
+ 801b924:	01800244 	movi	r6,9
+ 801b928:	01400244 	movi	r5,9
+ 801b92c:	e13ffa17 	ldw	r4,-24(fp)
+ 801b930:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801b934:	e0bfffc7 	ldb	r2,-1(fp)
+ 801b938:	e0fffdc7 	ldb	r3,-9(fp)
+ 801b93c:	000f883a 	mov	r7,zero
+ 801b940:	180d883a 	mov	r6,r3
+ 801b944:	100b883a 	mov	r5,r2
+ 801b948:	01020174 	movhi	r4,2053
+ 801b94c:	2123f404 	addi	r4,r4,-28720
+ 801b950:	8002c780 	call	8002c78 <printf>
+        
+        /* 1000 Mbps Half duplex not supported by TSE MAC */
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, 0);
+ 801b954:	d8000015 	stw	zero,0(sp)
+ 801b958:	01c00044 	movi	r7,1
+ 801b95c:	01800204 	movi	r6,8
+ 801b960:	01400244 	movi	r5,9
+ 801b964:	e13ffa17 	ldw	r4,-24(fp)
+ 801b968:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement 1000 Base-T half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801b96c:	e0bfffc7 	ldb	r2,-1(fp)
+ 801b970:	e0fffdc7 	ldb	r3,-9(fp)
+ 801b974:	000f883a 	mov	r7,zero
+ 801b978:	180d883a 	mov	r6,r3
+ 801b97c:	100b883a 	mov	r5,r2
+ 801b980:	01020174 	movhi	r4,2053
+ 801b984:	21241a04 	addi	r4,r4,-28568
+ 801b988:	8002c780 	call	8002c78 <printf>
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);    
+ 801b98c:	e0bffbc3 	ldbu	r2,-17(fp)
+ 801b990:	100b883a 	mov	r5,r2
+ 801b994:	e13ffa17 	ldw	r4,-24(fp)
+ 801b998:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+
+    return SUCCESS;
+ 801b99c:	0005883a 	mov	r2,zero
+}
+ 801b9a0:	e037883a 	mov	sp,fp
+ 801b9a4:	dfc00117 	ldw	ra,4(sp)
+ 801b9a8:	df000017 	ldw	fp,0(sp)
+ 801b9ac:	dec00204 	addi	sp,sp,8
+ 801b9b0:	f800283a 	ret
+
+0801b9b4 <alt_tse_phy_set_adv_100>:
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable) {
+ 801b9b4:	defff804 	addi	sp,sp,-32
+ 801b9b8:	dfc00715 	stw	ra,28(sp)
+ 801b9bc:	df000615 	stw	fp,24(sp)
+ 801b9c0:	df000604 	addi	fp,sp,24
+ 801b9c4:	e13ffc15 	stw	r4,-16(fp)
+ 801b9c8:	2805883a 	mov	r2,r5
+ 801b9cc:	e0bffb05 	stb	r2,-20(fp)
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801b9d0:	e0bffc17 	ldw	r2,-16(fp)
+ 801b9d4:	10800617 	ldw	r2,24(r2)
+ 801b9d8:	e0bffd15 	stw	r2,-12(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801b9dc:	e0bffd17 	ldw	r2,-12(fp)
+ 801b9e0:	10800317 	ldw	r2,12(r2)
+ 801b9e4:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801b9e8:	e13ffd17 	ldw	r4,-12(fp)
+ 801b9ec:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801b9f0:	e0bfff45 	stb	r2,-3(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801b9f4:	e13ffe17 	ldw	r4,-8(fp)
+ 801b9f8:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801b9fc:	e0bfff05 	stb	r2,-4(fp)
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801ba00:	e13ffc17 	ldw	r4,-16(fp)
+ 801ba04:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801ba08:	e0bfff85 	stb	r2,-2(fp)
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801ba0c:	e0bffc17 	ldw	r2,-16(fp)
+ 801ba10:	10800003 	ldbu	r2,0(r2)
+ 801ba14:	10803fcc 	andi	r2,r2,255
+ 801ba18:	100b883a 	mov	r5,r2
+ 801ba1c:	e13ffc17 	ldw	r4,-16(fp)
+ 801ba20:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+ 801ba24:	e0bffb03 	ldbu	r2,-20(fp)
+ 801ba28:	10004326 	beq	r2,zero,801bb38 <alt_tse_phy_set_adv_100+0x184>
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1);
+ 801ba2c:	01c00044 	movi	r7,1
+ 801ba30:	018003c4 	movi	r6,15
+ 801ba34:	01400044 	movi	r5,1
+ 801ba38:	e13ffc17 	ldw	r4,-16(fp)
+ 801ba3c:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801ba40:	e0bfffc5 	stb	r2,-1(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, cap);
+ 801ba44:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801ba48:	d8800015 	stw	r2,0(sp)
+ 801ba4c:	01c00044 	movi	r7,1
+ 801ba50:	01800244 	movi	r6,9
+ 801ba54:	01400104 	movi	r5,4
+ 801ba58:	e13ffc17 	ldw	r4,-16(fp)
+ 801ba5c:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, cap);
+ 801ba60:	e0bfff07 	ldb	r2,-4(fp)
+ 801ba64:	e0ffff47 	ldb	r3,-3(fp)
+ 801ba68:	e13fffc3 	ldbu	r4,-1(fp)
+ 801ba6c:	200f883a 	mov	r7,r4
+ 801ba70:	180d883a 	mov	r6,r3
+ 801ba74:	100b883a 	mov	r5,r2
+ 801ba78:	01020174 	movhi	r4,2053
+ 801ba7c:	21242c04 	addi	r4,r4,-28496
+ 801ba80:	8002c780 	call	8002c78 <printf>
+        
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1);
+ 801ba84:	01c00044 	movi	r7,1
+ 801ba88:	01800384 	movi	r6,14
+ 801ba8c:	01400044 	movi	r5,1
+ 801ba90:	e13ffc17 	ldw	r4,-16(fp)
+ 801ba94:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801ba98:	e0bfffc5 	stb	r2,-1(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, cap);
+ 801ba9c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801baa0:	d8800015 	stw	r2,0(sp)
+ 801baa4:	01c00044 	movi	r7,1
+ 801baa8:	01800204 	movi	r6,8
+ 801baac:	01400104 	movi	r5,4
+ 801bab0:	e13ffc17 	ldw	r4,-16(fp)
+ 801bab4:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801bab8:	e0bfff07 	ldb	r2,-4(fp)
+ 801babc:	e0ffff47 	ldb	r3,-3(fp)
+ 801bac0:	e13fffc3 	ldbu	r4,-1(fp)
+ 801bac4:	200f883a 	mov	r7,r4
+ 801bac8:	180d883a 	mov	r6,r3
+ 801bacc:	100b883a 	mov	r5,r2
+ 801bad0:	01020174 	movhi	r4,2053
+ 801bad4:	21243c04 	addi	r4,r4,-28432
+ 801bad8:	8002c780 	call	8002c78 <printf>
+        
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1);
+ 801badc:	01c00044 	movi	r7,1
+ 801bae0:	01800344 	movi	r6,13
+ 801bae4:	01400044 	movi	r5,1
+ 801bae8:	e13ffc17 	ldw	r4,-16(fp)
+ 801baec:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801baf0:	e0bfffc5 	stb	r2,-1(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, cap);
+ 801baf4:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801baf8:	d8800015 	stw	r2,0(sp)
+ 801bafc:	01c00044 	movi	r7,1
+ 801bb00:	018001c4 	movi	r6,7
+ 801bb04:	01400104 	movi	r5,4
+ 801bb08:	e13ffc17 	ldw	r4,-16(fp)
+ 801bb0c:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801bb10:	e0bfff07 	ldb	r2,-4(fp)
+ 801bb14:	e0ffff47 	ldb	r3,-3(fp)
+ 801bb18:	e13fffc3 	ldbu	r4,-1(fp)
+ 801bb1c:	200f883a 	mov	r7,r4
+ 801bb20:	180d883a 	mov	r6,r3
+ 801bb24:	100b883a 	mov	r5,r2
+ 801bb28:	01020174 	movhi	r4,2053
+ 801bb2c:	21244f04 	addi	r4,r4,-28356
+ 801bb30:	8002c780 	call	8002c78 <printf>
+ 801bb34:	00002a06 	br	801bbe0 <alt_tse_phy_set_adv_100+0x22c>
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, 0);
+ 801bb38:	d8000015 	stw	zero,0(sp)
+ 801bb3c:	01c00044 	movi	r7,1
+ 801bb40:	01800244 	movi	r6,9
+ 801bb44:	01400104 	movi	r5,4
+ 801bb48:	e13ffc17 	ldw	r4,-16(fp)
+ 801bb4c:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, 0);
+ 801bb50:	e0bfff07 	ldb	r2,-4(fp)
+ 801bb54:	e0ffff47 	ldb	r3,-3(fp)
+ 801bb58:	000f883a 	mov	r7,zero
+ 801bb5c:	180d883a 	mov	r6,r3
+ 801bb60:	100b883a 	mov	r5,r2
+ 801bb64:	01020174 	movhi	r4,2053
+ 801bb68:	21242c04 	addi	r4,r4,-28496
+ 801bb6c:	8002c780 	call	8002c78 <printf>
+        
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, 0);
+ 801bb70:	d8000015 	stw	zero,0(sp)
+ 801bb74:	01c00044 	movi	r7,1
+ 801bb78:	01800204 	movi	r6,8
+ 801bb7c:	01400104 	movi	r5,4
+ 801bb80:	e13ffc17 	ldw	r4,-16(fp)
+ 801bb84:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801bb88:	e0bfff07 	ldb	r2,-4(fp)
+ 801bb8c:	e0ffff47 	ldb	r3,-3(fp)
+ 801bb90:	000f883a 	mov	r7,zero
+ 801bb94:	180d883a 	mov	r6,r3
+ 801bb98:	100b883a 	mov	r5,r2
+ 801bb9c:	01020174 	movhi	r4,2053
+ 801bba0:	21243c04 	addi	r4,r4,-28432
+ 801bba4:	8002c780 	call	8002c78 <printf>
+        
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, 0);
+ 801bba8:	d8000015 	stw	zero,0(sp)
+ 801bbac:	01c00044 	movi	r7,1
+ 801bbb0:	018001c4 	movi	r6,7
+ 801bbb4:	01400104 	movi	r5,4
+ 801bbb8:	e13ffc17 	ldw	r4,-16(fp)
+ 801bbbc:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801bbc0:	e0bfff07 	ldb	r2,-4(fp)
+ 801bbc4:	e0ffff47 	ldb	r3,-3(fp)
+ 801bbc8:	000f883a 	mov	r7,zero
+ 801bbcc:	180d883a 	mov	r6,r3
+ 801bbd0:	100b883a 	mov	r5,r2
+ 801bbd4:	01020174 	movhi	r4,2053
+ 801bbd8:	21244f04 	addi	r4,r4,-28356
+ 801bbdc:	8002c780 	call	8002c78 <printf>
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);  
+ 801bbe0:	e0bfff83 	ldbu	r2,-2(fp)
+ 801bbe4:	100b883a 	mov	r5,r2
+ 801bbe8:	e13ffc17 	ldw	r4,-16(fp)
+ 801bbec:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    return SUCCESS;
+ 801bbf0:	0005883a 	mov	r2,zero
+}
+ 801bbf4:	e037883a 	mov	sp,fp
+ 801bbf8:	dfc00117 	ldw	ra,4(sp)
+ 801bbfc:	df000017 	ldw	fp,0(sp)
+ 801bc00:	dec00204 	addi	sp,sp,8
+ 801bc04:	f800283a 	ret
+
+0801bc08 <alt_tse_phy_set_adv_10>:
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable) {
+ 801bc08:	defff504 	addi	sp,sp,-44
+ 801bc0c:	dfc00a15 	stw	ra,40(sp)
+ 801bc10:	df000915 	stw	fp,36(sp)
+ 801bc14:	df000904 	addi	fp,sp,36
+ 801bc18:	e13ff915 	stw	r4,-28(fp)
+ 801bc1c:	2805883a 	mov	r2,r5
+ 801bc20:	e0bff805 	stb	r2,-32(fp)
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+ 801bc24:	e0bff917 	ldw	r2,-28(fp)
+ 801bc28:	10800617 	ldw	r2,24(r2)
+ 801bc2c:	e0bfff15 	stw	r2,-4(fp)
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+ 801bc30:	e0bfff17 	ldw	r2,-4(fp)
+ 801bc34:	10800317 	ldw	r2,12(r2)
+ 801bc38:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* get index of the pointers in pointer array list */
+    int mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801bc3c:	e13fff17 	ldw	r4,-4(fp)
+ 801bc40:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801bc44:	e0bffd15 	stw	r2,-12(fp)
+    int mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801bc48:	e13ffe17 	ldw	r4,-8(fp)
+ 801bc4c:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801bc50:	e0bffc15 	stw	r2,-16(fp)
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    int mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+ 801bc54:	e13ff917 	ldw	r4,-28(fp)
+ 801bc58:	80198cc0 	call	80198cc <alt_tse_phy_rd_mdio_addr>
+ 801bc5c:	e0bffb15 	stw	r2,-20(fp)
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801bc60:	e0bff917 	ldw	r2,-28(fp)
+ 801bc64:	10800003 	ldbu	r2,0(r2)
+ 801bc68:	10803fcc 	andi	r2,r2,255
+ 801bc6c:	100b883a 	mov	r5,r2
+ 801bc70:	e13ff917 	ldw	r4,-28(fp)
+ 801bc74:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+ 801bc78:	e0bff803 	ldbu	r2,-32(fp)
+ 801bc7c:	10002926 	beq	r2,zero,801bd24 <alt_tse_phy_set_adv_10+0x11c>
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1);
+ 801bc80:	01c00044 	movi	r7,1
+ 801bc84:	01800304 	movi	r6,12
+ 801bc88:	01400044 	movi	r5,1
+ 801bc8c:	e13ff917 	ldw	r4,-28(fp)
+ 801bc90:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801bc94:	e0bffac5 	stb	r2,-21(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, cap);
+ 801bc98:	e0bffac3 	ldbu	r2,-21(fp)
+ 801bc9c:	d8800015 	stw	r2,0(sp)
+ 801bca0:	01c00044 	movi	r7,1
+ 801bca4:	01800184 	movi	r6,6
+ 801bca8:	01400104 	movi	r5,4
+ 801bcac:	e13ff917 	ldw	r4,-28(fp)
+ 801bcb0:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801bcb4:	e0bffac3 	ldbu	r2,-21(fp)
+ 801bcb8:	100f883a 	mov	r7,r2
+ 801bcbc:	e1bffd17 	ldw	r6,-12(fp)
+ 801bcc0:	e17ffc17 	ldw	r5,-16(fp)
+ 801bcc4:	01020174 	movhi	r4,2053
+ 801bcc8:	21246204 	addi	r4,r4,-28280
+ 801bccc:	8002c780 	call	8002c78 <printf>
+    
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1);
+ 801bcd0:	01c00044 	movi	r7,1
+ 801bcd4:	018002c4 	movi	r6,11
+ 801bcd8:	01400044 	movi	r5,1
+ 801bcdc:	e13ff917 	ldw	r4,-28(fp)
+ 801bce0:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801bce4:	e0bffac5 	stb	r2,-21(fp)
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, cap);
+ 801bce8:	e0bffac3 	ldbu	r2,-21(fp)
+ 801bcec:	d8800015 	stw	r2,0(sp)
+ 801bcf0:	01c00044 	movi	r7,1
+ 801bcf4:	01800144 	movi	r6,5
+ 801bcf8:	01400104 	movi	r5,4
+ 801bcfc:	e13ff917 	ldw	r4,-28(fp)
+ 801bd00:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+ 801bd04:	e0bffac3 	ldbu	r2,-21(fp)
+ 801bd08:	100f883a 	mov	r7,r2
+ 801bd0c:	e1bffd17 	ldw	r6,-12(fp)
+ 801bd10:	e17ffc17 	ldw	r5,-16(fp)
+ 801bd14:	01020174 	movhi	r4,2053
+ 801bd18:	21247504 	addi	r4,r4,-28204
+ 801bd1c:	8002c780 	call	8002c78 <printf>
+ 801bd20:	00001806 	br	801bd84 <alt_tse_phy_set_adv_10+0x17c>
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, 0);
+ 801bd24:	d8000015 	stw	zero,0(sp)
+ 801bd28:	01c00044 	movi	r7,1
+ 801bd2c:	01800184 	movi	r6,6
+ 801bd30:	01400104 	movi	r5,4
+ 801bd34:	e13ff917 	ldw	r4,-28(fp)
+ 801bd38:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801bd3c:	000f883a 	mov	r7,zero
+ 801bd40:	e1bffd17 	ldw	r6,-12(fp)
+ 801bd44:	e17ffc17 	ldw	r5,-16(fp)
+ 801bd48:	01020174 	movhi	r4,2053
+ 801bd4c:	21246204 	addi	r4,r4,-28280
+ 801bd50:	8002c780 	call	8002c78 <printf>
+    
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, 0);
+ 801bd54:	d8000015 	stw	zero,0(sp)
+ 801bd58:	01c00044 	movi	r7,1
+ 801bd5c:	01800144 	movi	r6,5
+ 801bd60:	01400104 	movi	r5,4
+ 801bd64:	e13ff917 	ldw	r4,-28(fp)
+ 801bd68:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+ 801bd6c:	000f883a 	mov	r7,zero
+ 801bd70:	e1bffd17 	ldw	r6,-12(fp)
+ 801bd74:	e17ffc17 	ldw	r5,-16(fp)
+ 801bd78:	01020174 	movhi	r4,2053
+ 801bd7c:	21247504 	addi	r4,r4,-28204
+ 801bd80:	8002c780 	call	8002c78 <printf>
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+ 801bd84:	e0bffb17 	ldw	r2,-20(fp)
+ 801bd88:	10803fcc 	andi	r2,r2,255
+ 801bd8c:	100b883a 	mov	r5,r2
+ 801bd90:	e13ff917 	ldw	r4,-28(fp)
+ 801bd94:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+    
+    return SUCCESS;
+ 801bd98:	0005883a 	mov	r2,zero
+}
+ 801bd9c:	e037883a 	mov	sp,fp
+ 801bda0:	dfc00117 	ldw	ra,4(sp)
+ 801bda4:	df000017 	ldw	fp,0(sp)
+ 801bda8:	dec00204 	addi	sp,sp,8
+ 801bdac:	f800283a 	ret
+
+0801bdb0 <alt_tse_phy_get_common_speed>:
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Internal
+ * @param pmac_group    Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group) {
+ 801bdb0:	defff504 	addi	sp,sp,-44
+ 801bdb4:	dfc00a15 	stw	ra,40(sp)
+ 801bdb8:	df000915 	stw	fp,36(sp)
+ 801bdbc:	df000904 	addi	fp,sp,36
+ 801bdc0:	e13ff715 	stw	r4,-36(fp)
+    
+    alt_32 i;
+    alt_u8 common_1000 = 1;
+ 801bdc4:	00800044 	movi	r2,1
+ 801bdc8:	e0bfffc5 	stb	r2,-1(fp)
+    alt_u8 common_100 = 1;
+ 801bdcc:	00800044 	movi	r2,1
+ 801bdd0:	e0bffdc5 	stb	r2,-9(fp)
+    alt_u8 common_10 = 1;
+ 801bdd4:	00800044 	movi	r2,1
+ 801bdd8:	e0bffd85 	stb	r2,-10(fp)
+    
+    alt_32 common_speed;
+    
+    alt_u8 none_an_complete = 1;
+ 801bddc:	00800044 	movi	r2,1
+ 801bde0:	e0bffbc5 	stb	r2,-17(fp)
+    
+    alt_tse_mac_info *pmac_info = 0;
+ 801bde4:	e03ffa15 	stw	zero,-24(fp)
+    alt_tse_phy_info *pphy = 0;
+ 801bde8:	e03ff915 	stw	zero,-28(fp)
+    
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801bdec:	e13ff717 	ldw	r4,-36(fp)
+ 801bdf0:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801bdf4:	e0bff8c5 	stb	r2,-29(fp)
+    
+    /* reset Auto-Negotiation advertisement */
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801bdf8:	e03ffe15 	stw	zero,-8(fp)
+ 801bdfc:	00001a06 	br	801be68 <alt_tse_phy_get_common_speed+0xb8>
+        pmac_info = pmac_group->pmac_info[i];
+ 801be00:	e0fff717 	ldw	r3,-36(fp)
+ 801be04:	e0bffe17 	ldw	r2,-8(fp)
+ 801be08:	10800044 	addi	r2,r2,1
+ 801be0c:	100490ba 	slli	r2,r2,2
+ 801be10:	1885883a 	add	r2,r3,r2
+ 801be14:	10800017 	ldw	r2,0(r2)
+ 801be18:	e0bffa15 	stw	r2,-24(fp)
+        pphy = pmac_info->pphy_info;
+ 801be1c:	e0bffa17 	ldw	r2,-24(fp)
+ 801be20:	10800117 	ldw	r2,4(r2)
+ 801be24:	e0bff915 	stw	r2,-28(fp)
+        
+        /* run only if PHY connected */
+        if(pphy) {
+ 801be28:	e0bff917 	ldw	r2,-28(fp)
+ 801be2c:	10000926 	beq	r2,zero,801be54 <alt_tse_phy_get_common_speed+0xa4>
+            alt_tse_phy_set_adv_1000(pphy, 1);
+ 801be30:	01400044 	movi	r5,1
+ 801be34:	e13ff917 	ldw	r4,-28(fp)
+ 801be38:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_set_adv_100(pphy, 1);
+ 801be3c:	01400044 	movi	r5,1
+ 801be40:	e13ff917 	ldw	r4,-28(fp)
+ 801be44:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 1);
+ 801be48:	01400044 	movi	r5,1
+ 801be4c:	e13ff917 	ldw	r4,-28(fp)
+ 801be50:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+        }
+        tse_dprintf(6, "\n");
+ 801be54:	01000284 	movi	r4,10
+ 801be58:	8002cb80 	call	8002cb8 <putchar>
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801be5c:	e0bffe17 	ldw	r2,-8(fp)
+ 801be60:	10800044 	addi	r2,r2,1
+ 801be64:	e0bffe15 	stw	r2,-8(fp)
+ 801be68:	e0bff717 	ldw	r2,-36(fp)
+ 801be6c:	10800003 	ldbu	r2,0(r2)
+ 801be70:	10803fcc 	andi	r2,r2,255
+ 801be74:	e0fffe17 	ldw	r3,-8(fp)
+ 801be78:	18bfe116 	blt	r3,r2,801be00 <alt_tse_phy_get_common_speed+0x50>
+    }
+    
+    /* loop through every PHY connected */
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801be7c:	e03ffe15 	stw	zero,-8(fp)
+ 801be80:	00005506 	br	801bfd8 <alt_tse_phy_get_common_speed+0x228>
+
+        pmac_info = pmac_group->pmac_info[i];
+ 801be84:	e0fff717 	ldw	r3,-36(fp)
+ 801be88:	e0bffe17 	ldw	r2,-8(fp)
+ 801be8c:	10800044 	addi	r2,r2,1
+ 801be90:	100490ba 	slli	r2,r2,2
+ 801be94:	1885883a 	add	r2,r3,r2
+ 801be98:	10800017 	ldw	r2,0(r2)
+ 801be9c:	e0bffa15 	stw	r2,-24(fp)
+        pphy = pmac_info->pphy_info;
+ 801bea0:	e0bffa17 	ldw	r2,-24(fp)
+ 801bea4:	10800117 	ldw	r2,4(r2)
+ 801bea8:	e0bff915 	stw	r2,-28(fp)
+        
+        /* if no PHY connected */
+        if(!pphy) {
+ 801beac:	e0bff917 	ldw	r2,-28(fp)
+ 801beb0:	10004326 	beq	r2,zero,801bfc0 <alt_tse_phy_get_common_speed+0x210>
+            continue;
+        }
+        
+        /* get PHY capability */
+        /* skip for PHY with Auto-Negotiation not completed */
+        if(alt_tse_phy_get_cap(pphy) != TSE_PHY_AN_COMPLETE) {
+ 801beb4:	e13ff917 	ldw	r4,-28(fp)
+ 801beb8:	801b2640 	call	801b264 <alt_tse_phy_get_cap>
+ 801bebc:	1000421e 	bne	r2,zero,801bfc8 <alt_tse_phy_get_common_speed+0x218>
+            continue;
+        }
+        
+        none_an_complete = 0;
+ 801bec0:	e03ffbc5 	stb	zero,-17(fp)
+        
+        /* Small MAC */
+        if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) {
+ 801bec4:	e0bffa17 	ldw	r2,-24(fp)
+ 801bec8:	10800003 	ldbu	r2,0(r2)
+ 801becc:	10803fcc 	andi	r2,r2,255
+ 801bed0:	10800058 	cmpnei	r2,r2,1
+ 801bed4:	1000021e 	bne	r2,zero,801bee0 <alt_tse_phy_get_common_speed+0x130>
+            common_1000 = 0;
+ 801bed8:	e03fffc5 	stb	zero,-1(fp)
+ 801bedc:	00000706 	br	801befc <alt_tse_phy_get_common_speed+0x14c>
+        }
+        else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) {
+ 801bee0:	e0bffa17 	ldw	r2,-24(fp)
+ 801bee4:	10800003 	ldbu	r2,0(r2)
+ 801bee8:	10803fcc 	andi	r2,r2,255
+ 801beec:	10800098 	cmpnei	r2,r2,2
+ 801bef0:	1000021e 	bne	r2,zero,801befc <alt_tse_phy_get_common_speed+0x14c>
+            common_100 = 0;
+ 801bef4:	e03ffdc5 	stb	zero,-9(fp)
+            common_10 = 0;            
+ 801bef8:	e03ffd85 	stb	zero,-10(fp)
+        }
+        
+        /* get common capabilities for all PHYs and link partners */
+        common_1000 &= ((pphy->link_capability.cap_1000_base_t_full & pphy->link_capability.lp_1000_base_t_full));
+ 801befc:	e0bff917 	ldw	r2,-28(fp)
+ 801bf00:	10c000c3 	ldbu	r3,3(r2)
+ 801bf04:	e0bff917 	ldw	r2,-28(fp)
+ 801bf08:	10800303 	ldbu	r2,12(r2)
+ 801bf0c:	1884703a 	and	r2,r3,r2
+ 801bf10:	1007883a 	mov	r3,r2
+ 801bf14:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801bf18:	10c4703a 	and	r2,r2,r3
+ 801bf1c:	e0bfffc5 	stb	r2,-1(fp)
+                        //(pphy->link_capability.cap_1000_base_t_half & pphy->link_capability.lp_1000_base_t_half));
+        common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) |
+ 801bf20:	e0bff917 	ldw	r2,-28(fp)
+ 801bf24:	10c00183 	ldbu	r3,6(r2)
+ 801bf28:	e0bff917 	ldw	r2,-28(fp)
+ 801bf2c:	108003c3 	ldbu	r2,15(r2)
+ 801bf30:	1884703a 	and	r2,r3,r2
+ 801bf34:	1009883a 	mov	r4,r2
+                        (pphy->link_capability.cap_100_base_x_half & pphy->link_capability.lp_100_base_tx_half) |
+ 801bf38:	e0bff917 	ldw	r2,-28(fp)
+ 801bf3c:	10c001c3 	ldbu	r3,7(r2)
+ 801bf40:	e0bff917 	ldw	r2,-28(fp)
+ 801bf44:	10800403 	ldbu	r2,16(r2)
+        common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) |
+ 801bf48:	1884703a 	and	r2,r3,r2
+ 801bf4c:	2084b03a 	or	r2,r4,r2
+ 801bf50:	1009883a 	mov	r4,r2
+                        (pphy->link_capability.cap_100_base_t4 & pphy->link_capability.lp_100_base_t4));
+ 801bf54:	e0bff917 	ldw	r2,-28(fp)
+ 801bf58:	10c00143 	ldbu	r3,5(r2)
+ 801bf5c:	e0bff917 	ldw	r2,-28(fp)
+ 801bf60:	10800383 	ldbu	r2,14(r2)
+        common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) |
+ 801bf64:	1884703a 	and	r2,r3,r2
+ 801bf68:	2084b03a 	or	r2,r4,r2
+ 801bf6c:	1007883a 	mov	r3,r2
+ 801bf70:	e0bffdc3 	ldbu	r2,-9(fp)
+ 801bf74:	10c4703a 	and	r2,r2,r3
+ 801bf78:	e0bffdc5 	stb	r2,-9(fp)
+        common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) |
+ 801bf7c:	e0bff917 	ldw	r2,-28(fp)
+ 801bf80:	10c00283 	ldbu	r3,10(r2)
+ 801bf84:	e0bff917 	ldw	r2,-28(fp)
+ 801bf88:	10800443 	ldbu	r2,17(r2)
+ 801bf8c:	1884703a 	and	r2,r3,r2
+ 801bf90:	1009883a 	mov	r4,r2
+                        (pphy->link_capability.cap_10_base_t_half & pphy->link_capability.lp_10_base_tx_half));
+ 801bf94:	e0bff917 	ldw	r2,-28(fp)
+ 801bf98:	10c002c3 	ldbu	r3,11(r2)
+ 801bf9c:	e0bff917 	ldw	r2,-28(fp)
+ 801bfa0:	10800483 	ldbu	r2,18(r2)
+        common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) |
+ 801bfa4:	1884703a 	and	r2,r3,r2
+ 801bfa8:	2084b03a 	or	r2,r4,r2
+ 801bfac:	1007883a 	mov	r3,r2
+ 801bfb0:	e0bffd83 	ldbu	r2,-10(fp)
+ 801bfb4:	10c4703a 	and	r2,r2,r3
+ 801bfb8:	e0bffd85 	stb	r2,-10(fp)
+ 801bfbc:	00000306 	br	801bfcc <alt_tse_phy_get_common_speed+0x21c>
+            continue;
+ 801bfc0:	0001883a 	nop
+ 801bfc4:	00000106 	br	801bfcc <alt_tse_phy_get_common_speed+0x21c>
+            continue;
+ 801bfc8:	0001883a 	nop
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801bfcc:	e0bffe17 	ldw	r2,-8(fp)
+ 801bfd0:	10800044 	addi	r2,r2,1
+ 801bfd4:	e0bffe15 	stw	r2,-8(fp)
+ 801bfd8:	e0bff717 	ldw	r2,-36(fp)
+ 801bfdc:	10800003 	ldbu	r2,0(r2)
+ 801bfe0:	10803fcc 	andi	r2,r2,255
+ 801bfe4:	e0fffe17 	ldw	r3,-8(fp)
+ 801bfe8:	18bfa616 	blt	r3,r2,801be84 <alt_tse_phy_get_common_speed+0xd4>
+
+    }
+    
+    /* get common speed based on capabilities */
+    if(none_an_complete == 1) {
+ 801bfec:	e0bffbc3 	ldbu	r2,-17(fp)
+ 801bff0:	10800058 	cmpnei	r2,r2,1
+ 801bff4:	1000081e 	bne	r2,zero,801c018 <alt_tse_phy_get_common_speed+0x268>
+        common_speed = TSE_PHY_SPEED_NO_COMMON;
+ 801bff8:	00bfffc4 	movi	r2,-1
+ 801bffc:	e0bffc15 	stw	r2,-16(fp)
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - None of the PHYs Auto-Negotiation completed!\n", mac_group_index);
+ 801c000:	e0bff8c7 	ldb	r2,-29(fp)
+ 801c004:	100b883a 	mov	r5,r2
+ 801c008:	01020174 	movhi	r4,2053
+ 801c00c:	21248804 	addi	r4,r4,-28128
+ 801c010:	8002c780 	call	8002c78 <printf>
+ 801c014:	00002706 	br	801c0b4 <alt_tse_phy_get_common_speed+0x304>
+    }
+    else if(common_1000) {
+ 801c018:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801c01c:	10000926 	beq	r2,zero,801c044 <alt_tse_phy_get_common_speed+0x294>
+        common_speed = TSE_PHY_SPEED_1000;
+ 801c020:	00800084 	movi	r2,2
+ 801c024:	e0bffc15 	stw	r2,-16(fp)
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 1000);
+ 801c028:	e0bff8c7 	ldb	r2,-29(fp)
+ 801c02c:	0180fa04 	movi	r6,1000
+ 801c030:	100b883a 	mov	r5,r2
+ 801c034:	01020174 	movhi	r4,2053
+ 801c038:	21249a04 	addi	r4,r4,-28056
+ 801c03c:	8002c780 	call	8002c78 <printf>
+ 801c040:	00001c06 	br	801c0b4 <alt_tse_phy_get_common_speed+0x304>
+    }
+    else if(common_100) {
+ 801c044:	e0bffdc3 	ldbu	r2,-9(fp)
+ 801c048:	10000926 	beq	r2,zero,801c070 <alt_tse_phy_get_common_speed+0x2c0>
+        common_speed = TSE_PHY_SPEED_100;
+ 801c04c:	00800044 	movi	r2,1
+ 801c050:	e0bffc15 	stw	r2,-16(fp)
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 100);
+ 801c054:	e0bff8c7 	ldb	r2,-29(fp)
+ 801c058:	01801904 	movi	r6,100
+ 801c05c:	100b883a 	mov	r5,r2
+ 801c060:	01020174 	movhi	r4,2053
+ 801c064:	21249a04 	addi	r4,r4,-28056
+ 801c068:	8002c780 	call	8002c78 <printf>
+ 801c06c:	00001106 	br	801c0b4 <alt_tse_phy_get_common_speed+0x304>
+    }
+    else if(common_10) {
+ 801c070:	e0bffd83 	ldbu	r2,-10(fp)
+ 801c074:	10000826 	beq	r2,zero,801c098 <alt_tse_phy_get_common_speed+0x2e8>
+        common_speed = TSE_PHY_SPEED_10;
+ 801c078:	e03ffc15 	stw	zero,-16(fp)
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 10);
+ 801c07c:	e0bff8c7 	ldb	r2,-29(fp)
+ 801c080:	01800284 	movi	r6,10
+ 801c084:	100b883a 	mov	r5,r2
+ 801c088:	01020174 	movhi	r4,2053
+ 801c08c:	21249a04 	addi	r4,r4,-28056
+ 801c090:	8002c780 	call	8002c78 <printf>
+ 801c094:	00000706 	br	801c0b4 <alt_tse_phy_get_common_speed+0x304>
+    }
+    else {
+        common_speed = TSE_PHY_SPEED_NO_COMMON;
+ 801c098:	00bfffc4 	movi	r2,-1
+ 801c09c:	e0bffc15 	stw	r2,-16(fp)
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - No common speed at all!\n", mac_group_index);    }
+ 801c0a0:	e0bff8c7 	ldb	r2,-29(fp)
+ 801c0a4:	100b883a 	mov	r5,r2
+ 801c0a8:	01020174 	movhi	r4,2053
+ 801c0ac:	2124a704 	addi	r4,r4,-28004
+ 801c0b0:	8002c780 	call	8002c78 <printf>
+
+    return common_speed;
+ 801c0b4:	e0bffc17 	ldw	r2,-16(fp)
+}
+ 801c0b8:	e037883a 	mov	sp,fp
+ 801c0bc:	dfc00117 	ldw	ra,4(sp)
+ 801c0c0:	df000017 	ldw	fp,0(sp)
+ 801c0c4:	dec00204 	addi	sp,sp,8
+ 801c0c8:	f800283a 	ret
+
+0801c0cc <alt_tse_phy_set_common_speed>:
+ * @API Type:               Internal
+ * @param pmac_group        Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ *        common_speed      common speed supported by all PHYs
+ * @return      common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed) {
+ 801c0cc:	defff004 	addi	sp,sp,-64
+ 801c0d0:	dfc00f15 	stw	ra,60(sp)
+ 801c0d4:	df000e15 	stw	fp,56(sp)
+ 801c0d8:	dc400d15 	stw	r17,52(sp)
+ 801c0dc:	dc000c15 	stw	r16,48(sp)
+ 801c0e0:	df000e04 	addi	fp,sp,56
+ 801c0e4:	e13ff415 	stw	r4,-48(fp)
+ 801c0e8:	e17ff315 	stw	r5,-52(fp)
+    alt_u8 speed;
+    alt_u8 duplex;
+    
+    alt_u8 gb_capable;
+    
+    alt_tse_phy_info *pphy = 0;
+ 801c0ec:	e03ffb15 	stw	zero,-20(fp)
+    alt_tse_mac_info *pmac_info = 0;
+ 801c0f0:	e03ffa15 	stw	zero,-24(fp)
+    alt_tse_system_info *psys = 0;
+ 801c0f4:	e03ff915 	stw	zero,-28(fp)
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+ 801c0f8:	e03ff8c5 	stb	zero,-29(fp)
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+ 801c0fc:	e13ff417 	ldw	r4,-48(fp)
+ 801c100:	8018b340 	call	8018b34 <alt_tse_get_mac_group_index>
+ 801c104:	e0bff885 	stb	r2,-30(fp)
+         
+    /* Record previous MDIO address, to be restored at the end of function */
+    np_tse_mac *pmac_group_base = (np_tse_mac *)pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+ 801c108:	e0bff417 	ldw	r2,-48(fp)
+ 801c10c:	10800117 	ldw	r2,4(r2)
+ 801c110:	10800217 	ldw	r2,8(r2)
+ 801c114:	10800017 	ldw	r2,0(r2)
+ 801c118:	e0bff715 	stw	r2,-36(fp)
+    alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0);
+ 801c11c:	e0bff717 	ldw	r2,-36(fp)
+ 801c120:	10801004 	addi	r2,r2,64
+ 801c124:	10800037 	ldwio	r2,0(r2)
+ 801c128:	e0bff615 	stw	r2,-40(fp)
+    
+    if((common_speed < TSE_PHY_SPEED_10) || (common_speed > TSE_PHY_SPEED_1000)) {
+ 801c12c:	e0bff317 	ldw	r2,-52(fp)
+ 801c130:	10000316 	blt	r2,zero,801c140 <alt_tse_phy_set_common_speed+0x74>
+ 801c134:	e0bff317 	ldw	r2,-52(fp)
+ 801c138:	108000d0 	cmplti	r2,r2,3
+ 801c13c:	10000c1e 	bne	r2,zero,801c170 <alt_tse_phy_set_common_speed+0xa4>
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - Invalid common speed specified! common speed = %d\n", mac_group_index, (int)common_speed);
+ 801c140:	e0bff887 	ldb	r2,-30(fp)
+ 801c144:	e1bff317 	ldw	r6,-52(fp)
+ 801c148:	100b883a 	mov	r5,r2
+ 801c14c:	01020174 	movhi	r4,2053
+ 801c150:	2124b404 	addi	r4,r4,-27952
+ 801c154:	8002c780 	call	8002c78 <printf>
+        /* Restore previous MDIO address */
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+ 801c158:	e0bff717 	ldw	r2,-36(fp)
+ 801c15c:	10801004 	addi	r2,r2,64
+ 801c160:	e0fff617 	ldw	r3,-40(fp)
+ 801c164:	10c00035 	stwio	r3,0(r2)
+        return TSE_PHY_SPEED_NO_COMMON;
+ 801c168:	00bfffc4 	movi	r2,-1
+ 801c16c:	0000fc06 	br	801c560 <alt_tse_phy_set_common_speed+0x494>
+    }
+    
+    /* loop through every PHY connected */
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801c170:	e03ffc15 	stw	zero,-16(fp)
+ 801c174:	0000da06 	br	801c4e0 <alt_tse_phy_set_common_speed+0x414>
+        pmac_info = pmac_group->pmac_info[i];
+ 801c178:	e0fff417 	ldw	r3,-48(fp)
+ 801c17c:	e0bffc17 	ldw	r2,-16(fp)
+ 801c180:	10800044 	addi	r2,r2,1
+ 801c184:	100490ba 	slli	r2,r2,2
+ 801c188:	1885883a 	add	r2,r3,r2
+ 801c18c:	10800017 	ldw	r2,0(r2)
+ 801c190:	e0bffa15 	stw	r2,-24(fp)
+        mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+ 801c194:	e13ffa17 	ldw	r4,-24(fp)
+ 801c198:	8018ba00 	call	8018ba0 <alt_tse_get_mac_info_index>
+ 801c19c:	e0bff8c5 	stb	r2,-29(fp)
+
+        pphy = pmac_info->pphy_info;
+ 801c1a0:	e0bffa17 	ldw	r2,-24(fp)
+ 801c1a4:	10800117 	ldw	r2,4(r2)
+ 801c1a8:	e0bffb15 	stw	r2,-20(fp)
+        
+        /* if no PHY connected */
+        if(!pphy) {
+ 801c1ac:	e0bffb17 	ldw	r2,-20(fp)
+ 801c1b0:	1000c726 	beq	r2,zero,801c4d0 <alt_tse_phy_set_common_speed+0x404>
+            continue;
+        }
+        
+        psys = pmac_info->psys_info; 
+ 801c1b4:	e0bffa17 	ldw	r2,-24(fp)
+ 801c1b8:	10800217 	ldw	r2,8(r2)
+ 801c1bc:	e0bff915 	stw	r2,-28(fp)
+            
+        /* write PHY address to MDIO to access the i-th PHY */
+        alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+ 801c1c0:	e0bffb17 	ldw	r2,-20(fp)
+ 801c1c4:	10800003 	ldbu	r2,0(r2)
+ 801c1c8:	10803fcc 	andi	r2,r2,255
+ 801c1cc:	100b883a 	mov	r5,r2
+ 801c1d0:	e13ffb17 	ldw	r4,-20(fp)
+ 801c1d4:	80199140 	call	8019914 <alt_tse_phy_wr_mdio_addr>
+
+        /* capability of PHY supports 1000 Mbps */
+        gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || 
+ 801c1d8:	e0bffb17 	ldw	r2,-20(fp)
+ 801c1dc:	108000c3 	ldbu	r2,3(r2)
+                 pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half;
+ 801c1e0:	10803fcc 	andi	r2,r2,255
+ 801c1e4:	10000c1e 	bne	r2,zero,801c218 <alt_tse_phy_set_common_speed+0x14c>
+        gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || 
+ 801c1e8:	e0bffb17 	ldw	r2,-20(fp)
+ 801c1ec:	10800103 	ldbu	r2,4(r2)
+ 801c1f0:	10803fcc 	andi	r2,r2,255
+ 801c1f4:	1000081e 	bne	r2,zero,801c218 <alt_tse_phy_set_common_speed+0x14c>
+                 pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half;
+ 801c1f8:	e0bffb17 	ldw	r2,-20(fp)
+ 801c1fc:	10800043 	ldbu	r2,1(r2)
+        gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || 
+ 801c200:	10803fcc 	andi	r2,r2,255
+ 801c204:	1000041e 	bne	r2,zero,801c218 <alt_tse_phy_set_common_speed+0x14c>
+                 pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half;
+ 801c208:	e0bffb17 	ldw	r2,-20(fp)
+ 801c20c:	10800083 	ldbu	r2,2(r2)
+ 801c210:	10803fcc 	andi	r2,r2,255
+ 801c214:	10000226 	beq	r2,zero,801c220 <alt_tse_phy_set_common_speed+0x154>
+ 801c218:	00800044 	movi	r2,1
+ 801c21c:	00000106 	br	801c224 <alt_tse_phy_set_common_speed+0x158>
+ 801c220:	0005883a 	mov	r2,zero
+        gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || 
+ 801c224:	e0bff5c5 	stb	r2,-41(fp)
+        
+        /* if PHY does not supports 1000 Mbps, and common speed is 1000 Mbps */
+        if((!gb_capable) && (common_speed == TSE_PHY_SPEED_1000)) {
+ 801c228:	e0bff5c3 	ldbu	r2,-41(fp)
+ 801c22c:	1000101e 	bne	r2,zero,801c270 <alt_tse_phy_set_common_speed+0x1a4>
+ 801c230:	e0bff317 	ldw	r2,-52(fp)
+ 801c234:	10800098 	cmpnei	r2,r2,2
+ 801c238:	10000d1e 	bne	r2,zero,801c270 <alt_tse_phy_set_common_speed+0x1a4>
+            tse_dprintf(2, "ERROR   : PHY[%d.%d] - PHY does not support 1000 Mbps, please specify valid common speed\n", mac_group_index, mac_info_index);
+ 801c23c:	e0bff887 	ldb	r2,-30(fp)
+ 801c240:	e0fff8c7 	ldb	r3,-29(fp)
+ 801c244:	180d883a 	mov	r6,r3
+ 801c248:	100b883a 	mov	r5,r2
+ 801c24c:	01020174 	movhi	r4,2053
+ 801c250:	2124c804 	addi	r4,r4,-27872
+ 801c254:	8002c780 	call	8002c78 <printf>
+            /* Restore previous MDIO address */
+            IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+ 801c258:	e0bff717 	ldw	r2,-36(fp)
+ 801c25c:	10801004 	addi	r2,r2,64
+ 801c260:	e0fff617 	ldw	r3,-40(fp)
+ 801c264:	10c00035 	stwio	r3,0(r2)
+            return TSE_PHY_SPEED_NO_COMMON;
+ 801c268:	00bfffc4 	movi	r2,-1
+ 801c26c:	0000bc06 	br	801c560 <alt_tse_phy_set_common_speed+0x494>
+        }
+        
+        /* if PHY is not Auto-Negotiation capable */
+        if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+ 801c270:	01c00044 	movi	r7,1
+ 801c274:	018000c4 	movi	r6,3
+ 801c278:	01400044 	movi	r5,1
+ 801c27c:	e13ffb17 	ldw	r4,-20(fp)
+ 801c280:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c284:	1000141e 	bne	r2,zero,801c2d8 <alt_tse_phy_set_common_speed+0x20c>
+            
+            /* if PHY supports 1000 Mbps, write msb of speed */
+            if(gb_capable) {
+ 801c288:	e0bff5c3 	ldbu	r2,-41(fp)
+ 801c28c:	10000926 	beq	r2,zero,801c2b4 <alt_tse_phy_set_common_speed+0x1e8>
+                alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_MSB, 1, common_speed >> 1);
+ 801c290:	e0bff317 	ldw	r2,-52(fp)
+ 801c294:	1005d07a 	srai	r2,r2,1
+ 801c298:	10bfffcc 	andi	r2,r2,65535
+ 801c29c:	d8800015 	stw	r2,0(sp)
+ 801c2a0:	01c00044 	movi	r7,1
+ 801c2a4:	01800184 	movi	r6,6
+ 801c2a8:	000b883a 	mov	r5,zero
+ 801c2ac:	e13ffb17 	ldw	r4,-20(fp)
+ 801c2b0:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+            }
+            /* write lsb of speed */
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_LSB, 1, common_speed);
+ 801c2b4:	e0bff317 	ldw	r2,-52(fp)
+ 801c2b8:	10bfffcc 	andi	r2,r2,65535
+ 801c2bc:	d8800015 	stw	r2,0(sp)
+ 801c2c0:	01c00044 	movi	r7,1
+ 801c2c4:	01800344 	movi	r6,13
+ 801c2c8:	000b883a 	mov	r5,zero
+ 801c2cc:	e13ffb17 	ldw	r4,-20(fp)
+ 801c2d0:	801996c0 	call	801996c <alt_tse_phy_wr_mdio_reg>
+            
+            /* continue to next PHY */
+            continue;
+ 801c2d4:	00007f06 	br	801c4d4 <alt_tse_phy_set_common_speed+0x408>
+        }
+        
+        /* set Auto-Negotiation advertisement based on common speed */
+        if(common_speed == TSE_PHY_SPEED_1000) {
+ 801c2d8:	e0bff317 	ldw	r2,-52(fp)
+ 801c2dc:	10800098 	cmpnei	r2,r2,2
+ 801c2e0:	10000a1e 	bne	r2,zero,801c30c <alt_tse_phy_set_common_speed+0x240>
+            alt_tse_phy_set_adv_1000(pphy, 1);
+ 801c2e4:	01400044 	movi	r5,1
+ 801c2e8:	e13ffb17 	ldw	r4,-20(fp)
+ 801c2ec:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_set_adv_100(pphy, 1);
+ 801c2f0:	01400044 	movi	r5,1
+ 801c2f4:	e13ffb17 	ldw	r4,-20(fp)
+ 801c2f8:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 1);
+ 801c2fc:	01400044 	movi	r5,1
+ 801c300:	e13ffb17 	ldw	r4,-20(fp)
+ 801c304:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+ 801c308:	00002206 	br	801c394 <alt_tse_phy_set_common_speed+0x2c8>
+        }
+        else if(common_speed == TSE_PHY_SPEED_100) {
+ 801c30c:	e0bff317 	ldw	r2,-52(fp)
+ 801c310:	10800058 	cmpnei	r2,r2,1
+ 801c314:	10000a1e 	bne	r2,zero,801c340 <alt_tse_phy_set_common_speed+0x274>
+            alt_tse_phy_set_adv_1000(pphy, 0);
+ 801c318:	000b883a 	mov	r5,zero
+ 801c31c:	e13ffb17 	ldw	r4,-20(fp)
+ 801c320:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_set_adv_100(pphy, 1);
+ 801c324:	01400044 	movi	r5,1
+ 801c328:	e13ffb17 	ldw	r4,-20(fp)
+ 801c32c:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 1);
+ 801c330:	01400044 	movi	r5,1
+ 801c334:	e13ffb17 	ldw	r4,-20(fp)
+ 801c338:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+ 801c33c:	00001506 	br	801c394 <alt_tse_phy_set_common_speed+0x2c8>
+        }    
+        else if(common_speed == TSE_PHY_SPEED_10) {
+ 801c340:	e0bff317 	ldw	r2,-52(fp)
+ 801c344:	10000a1e 	bne	r2,zero,801c370 <alt_tse_phy_set_common_speed+0x2a4>
+            alt_tse_phy_set_adv_1000(pphy, 0);
+ 801c348:	000b883a 	mov	r5,zero
+ 801c34c:	e13ffb17 	ldw	r4,-20(fp)
+ 801c350:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_set_adv_100(pphy, 0);
+ 801c354:	000b883a 	mov	r5,zero
+ 801c358:	e13ffb17 	ldw	r4,-20(fp)
+ 801c35c:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 1);
+ 801c360:	01400044 	movi	r5,1
+ 801c364:	e13ffb17 	ldw	r4,-20(fp)
+ 801c368:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+ 801c36c:	00000906 	br	801c394 <alt_tse_phy_set_common_speed+0x2c8>
+        }
+        else {
+            alt_tse_phy_set_adv_1000(pphy, 0);
+ 801c370:	000b883a 	mov	r5,zero
+ 801c374:	e13ffb17 	ldw	r4,-20(fp)
+ 801c378:	801b7f00 	call	801b7f0 <alt_tse_phy_set_adv_1000>
+            alt_tse_phy_set_adv_100(pphy, 0);
+ 801c37c:	000b883a 	mov	r5,zero
+ 801c380:	e13ffb17 	ldw	r4,-20(fp)
+ 801c384:	801b9b40 	call	801b9b4 <alt_tse_phy_set_adv_100>
+            alt_tse_phy_set_adv_10(pphy, 0);
+ 801c388:	000b883a 	mov	r5,zero
+ 801c38c:	e13ffb17 	ldw	r4,-20(fp)
+ 801c390:	801bc080 	call	801bc08 <alt_tse_phy_set_adv_10>
+        }
+        
+        /* if PHY Auto-Negotiation is completed */
+        if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 1) {
+ 801c394:	01c00044 	movi	r7,1
+ 801c398:	01800144 	movi	r6,5
+ 801c39c:	01400044 	movi	r5,1
+ 801c3a0:	e13ffb17 	ldw	r4,-20(fp)
+ 801c3a4:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c3a8:	10800058 	cmpnei	r2,r2,1
+ 801c3ac:	10003a1e 	bne	r2,zero,801c498 <alt_tse_phy_set_common_speed+0x3cc>
+            
+            /* read both msb and lsb of speed bits if PHY support 1000 Mbps */
+            if(gb_capable) {
+ 801c3b0:	e0bff5c3 	ldbu	r2,-41(fp)
+ 801c3b4:	10000f26 	beq	r2,zero,801c3f4 <alt_tse_phy_set_common_speed+0x328>
+        
+                /* get speed information after Auto-Negotiation */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2);
+ 801c3b8:	e0bffb17 	ldw	r2,-20(fp)
+ 801c3bc:	10800517 	ldw	r2,20(r2)
+ 801c3c0:	10801583 	ldbu	r2,86(r2)
+ 801c3c4:	10c03fcc 	andi	r3,r2,255
+ 801c3c8:	e0bffb17 	ldw	r2,-20(fp)
+ 801c3cc:	10800517 	ldw	r2,20(r2)
+ 801c3d0:	108015c3 	ldbu	r2,87(r2)
+ 801c3d4:	10803fcc 	andi	r2,r2,255
+ 801c3d8:	01c00084 	movi	r7,2
+ 801c3dc:	100d883a 	mov	r6,r2
+ 801c3e0:	180b883a 	mov	r5,r3
+ 801c3e4:	e13ffb17 	ldw	r4,-20(fp)
+ 801c3e8:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c3ec:	e0bffdc5 	stb	r2,-9(fp)
+ 801c3f0:	00000e06 	br	801c42c <alt_tse_phy_set_common_speed+0x360>
+            }
+            
+            /* read lsb of speed only if PHY support only 10/100 Mbps */
+            else {
+                /* get speed and link information after Auto-Negotiation */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 1);
+ 801c3f4:	e0bffb17 	ldw	r2,-20(fp)
+ 801c3f8:	10800517 	ldw	r2,20(r2)
+ 801c3fc:	10801583 	ldbu	r2,86(r2)
+ 801c400:	10c03fcc 	andi	r3,r2,255
+ 801c404:	e0bffb17 	ldw	r2,-20(fp)
+ 801c408:	10800517 	ldw	r2,20(r2)
+ 801c40c:	108015c3 	ldbu	r2,87(r2)
+ 801c410:	10803fcc 	andi	r2,r2,255
+ 801c414:	01c00044 	movi	r7,1
+ 801c418:	100d883a 	mov	r6,r2
+ 801c41c:	180b883a 	mov	r5,r3
+ 801c420:	e13ffb17 	ldw	r4,-20(fp)
+ 801c424:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c428:	e0bffdc5 	stb	r2,-9(fp)
+            }
+            
+            /* if current speed != common speed, then restart Auto-Negotiation */
+            if(speed != common_speed) {
+ 801c42c:	e0bffdc3 	ldbu	r2,-9(fp)
+ 801c430:	e0fff317 	ldw	r3,-52(fp)
+ 801c434:	18800326 	beq	r3,r2,801c444 <alt_tse_phy_set_common_speed+0x378>
+                alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+ 801c438:	01427104 	movi	r5,2500
+ 801c43c:	e13ffb17 	ldw	r4,-20(fp)
+ 801c440:	801af180 	call	801af18 <alt_tse_phy_restart_an>
+            }
+            
+            /* get speed information after Auto-Negotiation */
+            duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1);
+ 801c444:	e0bffb17 	ldw	r2,-20(fp)
+ 801c448:	10800517 	ldw	r2,20(r2)
+ 801c44c:	10801583 	ldbu	r2,86(r2)
+ 801c450:	10c03fcc 	andi	r3,r2,255
+ 801c454:	e0bffb17 	ldw	r2,-20(fp)
+ 801c458:	10800517 	ldw	r2,20(r2)
+ 801c45c:	10801603 	ldbu	r2,88(r2)
+ 801c460:	10803fcc 	andi	r2,r2,255
+ 801c464:	01c00044 	movi	r7,1
+ 801c468:	100d883a 	mov	r6,r2
+ 801c46c:	180b883a 	mov	r5,r3
+ 801c470:	e13ffb17 	ldw	r4,-20(fp)
+ 801c474:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c478:	e0bff585 	stb	r2,-42(fp)
+            
+            /* Set MAC duplex register */
+            alt_tse_mac_set_duplex((np_tse_mac *)psys->tse_mac_base, duplex);
+ 801c47c:	e0bff917 	ldw	r2,-28(fp)
+ 801c480:	10800017 	ldw	r2,0(r2)
+ 801c484:	1007883a 	mov	r3,r2
+ 801c488:	e0bff583 	ldbu	r2,-42(fp)
+ 801c48c:	100b883a 	mov	r5,r2
+ 801c490:	1809883a 	mov	r4,r3
+ 801c494:	8018dc80 	call	8018dc8 <alt_tse_mac_set_duplex>
+            
+        }
+        tse_dprintf(5, "INFO    : PHY[%d.%d] - PHY STATUS = 0x%04x\n\n", mac_group_index, mac_info_index, (int) alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, 0, 16));        
+ 801c498:	e43ff887 	ldb	r16,-30(fp)
+ 801c49c:	e47ff8c7 	ldb	r17,-29(fp)
+ 801c4a0:	01c00404 	movi	r7,16
+ 801c4a4:	000d883a 	mov	r6,zero
+ 801c4a8:	01400044 	movi	r5,1
+ 801c4ac:	e13ffb17 	ldw	r4,-20(fp)
+ 801c4b0:	8019a980 	call	8019a98 <alt_tse_phy_rd_mdio_reg>
+ 801c4b4:	100f883a 	mov	r7,r2
+ 801c4b8:	880d883a 	mov	r6,r17
+ 801c4bc:	800b883a 	mov	r5,r16
+ 801c4c0:	01020174 	movhi	r4,2053
+ 801c4c4:	2124df04 	addi	r4,r4,-27780
+ 801c4c8:	8002c780 	call	8002c78 <printf>
+ 801c4cc:	00000106 	br	801c4d4 <alt_tse_phy_set_common_speed+0x408>
+            continue;
+ 801c4d0:	0001883a 	nop
+    for(i = 0; i < pmac_group->channel; i++) {
+ 801c4d4:	e0bffc17 	ldw	r2,-16(fp)
+ 801c4d8:	10800044 	addi	r2,r2,1
+ 801c4dc:	e0bffc15 	stw	r2,-16(fp)
+ 801c4e0:	e0bff417 	ldw	r2,-48(fp)
+ 801c4e4:	10800003 	ldbu	r2,0(r2)
+ 801c4e8:	10803fcc 	andi	r2,r2,255
+ 801c4ec:	e0fffc17 	ldw	r3,-16(fp)
+ 801c4f0:	18bf2116 	blt	r3,r2,801c178 <alt_tse_phy_set_common_speed+0xac>
+    }
+    tse_dprintf(5, "INFO    : MAC Group[%d] - All PHYs set to common speed : %d Mbps\n", mac_group_index, (common_speed == TSE_PHY_SPEED_1000) ? 1000 : ((common_speed == TSE_PHY_SPEED_100) ? 100 : 10));
+ 801c4f4:	e0fff887 	ldb	r3,-30(fp)
+ 801c4f8:	e0bff317 	ldw	r2,-52(fp)
+ 801c4fc:	108000a0 	cmpeqi	r2,r2,2
+ 801c500:	1000071e 	bne	r2,zero,801c520 <alt_tse_phy_set_common_speed+0x454>
+ 801c504:	e0bff317 	ldw	r2,-52(fp)
+ 801c508:	10800058 	cmpnei	r2,r2,1
+ 801c50c:	1000021e 	bne	r2,zero,801c518 <alt_tse_phy_set_common_speed+0x44c>
+ 801c510:	00801904 	movi	r2,100
+ 801c514:	00000306 	br	801c524 <alt_tse_phy_set_common_speed+0x458>
+ 801c518:	00800284 	movi	r2,10
+ 801c51c:	00000106 	br	801c524 <alt_tse_phy_set_common_speed+0x458>
+ 801c520:	0080fa04 	movi	r2,1000
+ 801c524:	100d883a 	mov	r6,r2
+ 801c528:	180b883a 	mov	r5,r3
+ 801c52c:	01020174 	movhi	r4,2053
+ 801c530:	2124eb04 	addi	r4,r4,-27732
+ 801c534:	8002c780 	call	8002c78 <printf>
+
+    /* Set MAC speed register */
+    alt_tse_mac_set_speed(pmac_group_base, common_speed);
+ 801c538:	e0bff317 	ldw	r2,-52(fp)
+ 801c53c:	10803fcc 	andi	r2,r2,255
+ 801c540:	100b883a 	mov	r5,r2
+ 801c544:	e13ff717 	ldw	r4,-36(fp)
+ 801c548:	8018ce80 	call	8018ce8 <alt_tse_mac_set_speed>
+    
+    /* Restore previous MDIO address */
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+ 801c54c:	e0bff717 	ldw	r2,-36(fp)
+ 801c550:	10801004 	addi	r2,r2,64
+ 801c554:	e0fff617 	ldw	r3,-40(fp)
+ 801c558:	10c00035 	stwio	r3,0(r2)
+        
+    return common_speed;
+ 801c55c:	e0bff317 	ldw	r2,-52(fp)
+}
+ 801c560:	e6fffe04 	addi	sp,fp,-8
+ 801c564:	dfc00317 	ldw	ra,12(sp)
+ 801c568:	df000217 	ldw	fp,8(sp)
+ 801c56c:	dc400117 	ldw	r17,4(sp)
+ 801c570:	dc000017 	ldw	r16,0(sp)
+ 801c574:	dec00404 	addi	sp,sp,16
+ 801c578:	f800283a 	ret
+
+0801c57c <marvell_phy_cfg>:
+
+/* @Function Description: Additional configuration for Marvell PHY
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address of MAC group
+ */
+alt_32 marvell_phy_cfg(np_tse_mac *pmac) {
+ 801c57c:	defffc04 	addi	sp,sp,-16
+ 801c580:	dfc00315 	stw	ra,12(sp)
+ 801c584:	df000215 	stw	fp,8(sp)
+ 801c588:	df000204 	addi	fp,sp,8
+ 801c58c:	e13ffe15 	stw	r4,-8(fp)
+    
+    alt_u16 dat;
+    
+    /* If there is no link yet, we enable auto crossover and reset the PHY */
+    if((IORD(&pmac->mdio1.STATUS, 0) & PCS_ST_an_done) == 0) {
+ 801c590:	e0bffe17 	ldw	r2,-8(fp)
+ 801c594:	1080a104 	addi	r2,r2,644
+ 801c598:	10800037 	ldwio	r2,0(r2)
+ 801c59c:	1080080c 	andi	r2,r2,32
+ 801c5a0:	1000161e 	bne	r2,zero,801c5fc <marvell_phy_cfg+0x80>
+        tse_dprintf(5, "MARVELL : Enabling auto crossover\n");
+ 801c5a4:	01020174 	movhi	r4,2053
+ 801c5a8:	2124fc04 	addi	r4,r4,-27664
+ 801c5ac:	8002d9c0 	call	8002d9c <puts>
+        IOWR(&pmac->mdio1.CONTROL, 16, 0x0078);
+ 801c5b0:	e0bffe17 	ldw	r2,-8(fp)
+ 801c5b4:	1080a004 	addi	r2,r2,640
+ 801c5b8:	10801004 	addi	r2,r2,64
+ 801c5bc:	00c01e04 	movi	r3,120
+ 801c5c0:	10c00035 	stwio	r3,0(r2)
+        tse_dprintf(5, "MARVELL : PHY reset\n");
+ 801c5c4:	01020174 	movhi	r4,2053
+ 801c5c8:	21250504 	addi	r4,r4,-27628
+ 801c5cc:	8002d9c0 	call	8002d9c <puts>
+        dat = IORD(&pmac->mdio1.CONTROL, 0); 
+ 801c5d0:	e0bffe17 	ldw	r2,-8(fp)
+ 801c5d4:	1080a004 	addi	r2,r2,640
+ 801c5d8:	10800037 	ldwio	r2,0(r2)
+ 801c5dc:	e0bfff8d 	sth	r2,-2(fp)
+        IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);        
+ 801c5e0:	e0bffe17 	ldw	r2,-8(fp)
+ 801c5e4:	1080a004 	addi	r2,r2,640
+ 801c5e8:	e13fff8b 	ldhu	r4,-2(fp)
+ 801c5ec:	00e00004 	movi	r3,-32768
+ 801c5f0:	20c6b03a 	or	r3,r4,r3
+ 801c5f4:	18ffffcc 	andi	r3,r3,65535
+ 801c5f8:	10c00035 	stwio	r3,0(r2)
+    }
+    
+    return 0;
+ 801c5fc:	0005883a 	mov	r2,zero
+}
+ 801c600:	e037883a 	mov	sp,fp
+ 801c604:	dfc00117 	ldw	ra,4(sp)
+ 801c608:	df000017 	ldw	fp,0(sp)
+ 801c60c:	dec00204 	addi	sp,sp,8
+ 801c610:	f800283a 	ret
+
+0801c614 <marvell_cfg_gmii>:
+
+/* @Function Description: Change operating mode of Marvell PHY to GMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_gmii(np_tse_mac *pmac) {
+ 801c614:	defffc04 	addi	sp,sp,-16
+ 801c618:	dfc00315 	stw	ra,12(sp)
+ 801c61c:	df000215 	stw	fp,8(sp)
+ 801c620:	df000204 	addi	fp,sp,8
+ 801c624:	e13ffe15 	stw	r4,-8(fp)
+    
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+ 801c628:	e0bffe17 	ldw	r2,-8(fp)
+ 801c62c:	1080bb04 	addi	r2,r2,748
+ 801c630:	10800037 	ldwio	r2,0(r2)
+ 801c634:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= 0xfff0;
+ 801c638:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c63c:	00bffc04 	movi	r2,-16
+ 801c640:	1884703a 	and	r2,r3,r2
+ 801c644:	e0bfff8d 	sth	r2,-2(fp)
+
+    tse_dprintf(5, "MARVELL : Mode changed to GMII to copper mode\n");
+ 801c648:	01020174 	movhi	r4,2053
+ 801c64c:	21250a04 	addi	r4,r4,-27608
+ 801c650:	8002d9c0 	call	8002d9c <puts>
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0xf);
+ 801c654:	e0bffe17 	ldw	r2,-8(fp)
+ 801c658:	1080bb04 	addi	r2,r2,748
+ 801c65c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c660:	18c003d4 	ori	r3,r3,15
+ 801c664:	18ffffcc 	andi	r3,r3,65535
+ 801c668:	10c00035 	stwio	r3,0(r2)
+    
+    tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n");
+ 801c66c:	01020174 	movhi	r4,2053
+ 801c670:	21251604 	addi	r4,r4,-27560
+ 801c674:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.reg14, 0); 
+ 801c678:	e0bffe17 	ldw	r2,-8(fp)
+ 801c67c:	1080b404 	addi	r2,r2,720
+ 801c680:	10800037 	ldwio	r2,0(r2)
+ 801c684:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= ~0x82;
+ 801c688:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c68c:	00bfdf44 	movi	r2,-131
+ 801c690:	1884703a 	and	r2,r3,r2
+ 801c694:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+ 801c698:	e0bffe17 	ldw	r2,-8(fp)
+ 801c69c:	1080b404 	addi	r2,r2,720
+ 801c6a0:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c6a4:	10c00035 	stwio	r3,0(r2)
+    
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+ 801c6a8:	01020174 	movhi	r4,2053
+ 801c6ac:	21250504 	addi	r4,r4,-27628
+ 801c6b0:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+ 801c6b4:	e0bffe17 	ldw	r2,-8(fp)
+ 801c6b8:	1080a004 	addi	r2,r2,640
+ 801c6bc:	10800037 	ldwio	r2,0(r2)
+ 801c6c0:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+ 801c6c4:	e0bffe17 	ldw	r2,-8(fp)
+ 801c6c8:	1080a004 	addi	r2,r2,640
+ 801c6cc:	e13fff8b 	ldhu	r4,-2(fp)
+ 801c6d0:	00e00004 	movi	r3,-32768
+ 801c6d4:	20c6b03a 	or	r3,r4,r3
+ 801c6d8:	18ffffcc 	andi	r3,r3,65535
+ 801c6dc:	10c00035 	stwio	r3,0(r2)
+    
+    return 1;
+ 801c6e0:	00800044 	movi	r2,1
+}
+ 801c6e4:	e037883a 	mov	sp,fp
+ 801c6e8:	dfc00117 	ldw	ra,4(sp)
+ 801c6ec:	df000017 	ldw	fp,0(sp)
+ 801c6f0:	dec00204 	addi	sp,sp,8
+ 801c6f4:	f800283a 	ret
+
+0801c6f8 <marvell_cfg_sgmii>:
+
+/* @Function Description: Change operating mode of Marvell PHY to SGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_sgmii(np_tse_mac *pmac) {
+ 801c6f8:	defffc04 	addi	sp,sp,-16
+ 801c6fc:	dfc00315 	stw	ra,12(sp)
+ 801c700:	df000215 	stw	fp,8(sp)
+ 801c704:	df000204 	addi	fp,sp,8
+ 801c708:	e13ffe15 	stw	r4,-8(fp)
+    
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+ 801c70c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c710:	1080bb04 	addi	r2,r2,748
+ 801c714:	10800037 	ldwio	r2,0(r2)
+ 801c718:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= 0xfff0;
+ 801c71c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c720:	00bffc04 	movi	r2,-16
+ 801c724:	1884703a 	and	r2,r3,r2
+ 801c728:	e0bfff8d 	sth	r2,-2(fp)
+
+    tse_dprintf(5, "MARVELL : Mode changed to SGMII without clock with SGMII Auto-Neg to copper mode\n");
+ 801c72c:	01020174 	movhi	r4,2053
+ 801c730:	21252004 	addi	r4,r4,-27520
+ 801c734:	8002d9c0 	call	8002d9c <puts>
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0x4);
+ 801c738:	e0bffe17 	ldw	r2,-8(fp)
+ 801c73c:	1080bb04 	addi	r2,r2,748
+ 801c740:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c744:	18c00114 	ori	r3,r3,4
+ 801c748:	18ffffcc 	andi	r3,r3,65535
+ 801c74c:	10c00035 	stwio	r3,0(r2)
+    
+    tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n");
+ 801c750:	01020174 	movhi	r4,2053
+ 801c754:	21251604 	addi	r4,r4,-27560
+ 801c758:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.reg14, 0); 
+ 801c75c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c760:	1080b404 	addi	r2,r2,720
+ 801c764:	10800037 	ldwio	r2,0(r2)
+ 801c768:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= ~0x82;
+ 801c76c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c770:	00bfdf44 	movi	r2,-131
+ 801c774:	1884703a 	and	r2,r3,r2
+ 801c778:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+ 801c77c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c780:	1080b404 	addi	r2,r2,720
+ 801c784:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c788:	10c00035 	stwio	r3,0(r2)
+
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+ 801c78c:	01020174 	movhi	r4,2053
+ 801c790:	21250504 	addi	r4,r4,-27628
+ 801c794:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+ 801c798:	e0bffe17 	ldw	r2,-8(fp)
+ 801c79c:	1080a004 	addi	r2,r2,640
+ 801c7a0:	10800037 	ldwio	r2,0(r2)
+ 801c7a4:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+ 801c7a8:	e0bffe17 	ldw	r2,-8(fp)
+ 801c7ac:	1080a004 	addi	r2,r2,640
+ 801c7b0:	e13fff8b 	ldhu	r4,-2(fp)
+ 801c7b4:	00e00004 	movi	r3,-32768
+ 801c7b8:	20c6b03a 	or	r3,r4,r3
+ 801c7bc:	18ffffcc 	andi	r3,r3,65535
+ 801c7c0:	10c00035 	stwio	r3,0(r2)
+    
+    return 1;
+ 801c7c4:	00800044 	movi	r2,1
+}
+ 801c7c8:	e037883a 	mov	sp,fp
+ 801c7cc:	dfc00117 	ldw	ra,4(sp)
+ 801c7d0:	df000017 	ldw	fp,0(sp)
+ 801c7d4:	dec00204 	addi	sp,sp,8
+ 801c7d8:	f800283a 	ret
+
+0801c7dc <marvell_cfg_rgmii>:
+
+/* @Function Description: Change operating mode of Marvell PHY to RGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) {
+ 801c7dc:	defffc04 	addi	sp,sp,-16
+ 801c7e0:	dfc00315 	stw	ra,12(sp)
+ 801c7e4:	df000215 	stw	fp,8(sp)
+ 801c7e8:	df000204 	addi	fp,sp,8
+ 801c7ec:	e13ffe15 	stw	r4,-8(fp)
+    
+
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+ 801c7f0:	e0bffe17 	ldw	r2,-8(fp)
+ 801c7f4:	1080bb04 	addi	r2,r2,748
+ 801c7f8:	10800037 	ldwio	r2,0(r2)
+ 801c7fc:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= 0xfff0;
+ 801c800:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c804:	00bffc04 	movi	r2,-16
+ 801c808:	1884703a 	and	r2,r3,r2
+ 801c80c:	e0bfff8d 	sth	r2,-2(fp)
+    
+    tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n");
+ 801c810:	01020174 	movhi	r4,2053
+ 801c814:	21253504 	addi	r4,r4,-27436
+ 801c818:	8002d9c0 	call	8002d9c <puts>
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb);
+ 801c81c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c820:	1080bb04 	addi	r2,r2,748
+ 801c824:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c828:	18c002d4 	ori	r3,r3,11
+ 801c82c:	18ffffcc 	andi	r3,r3,65535
+ 801c830:	10c00035 	stwio	r3,0(r2)
+    
+    tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n");
+ 801c834:	01020174 	movhi	r4,2053
+ 801c838:	21254404 	addi	r4,r4,-27376
+ 801c83c:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.reg14, 0);
+ 801c840:	e0bffe17 	ldw	r2,-8(fp)
+ 801c844:	1080b404 	addi	r2,r2,720
+ 801c848:	10800037 	ldwio	r2,0(r2)
+ 801c84c:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= ~0x82;
+ 801c850:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c854:	00bfdf44 	movi	r2,-131
+ 801c858:	1884703a 	and	r2,r3,r2
+ 801c85c:	e0bfff8d 	sth	r2,-2(fp)
+    dat |= 0x82;
+ 801c860:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801c864:	10802094 	ori	r2,r2,130
+ 801c868:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+ 801c86c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c870:	1080b404 	addi	r2,r2,720
+ 801c874:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c878:	10c00035 	stwio	r3,0(r2)
+    
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+ 801c87c:	01020174 	movhi	r4,2053
+ 801c880:	21250504 	addi	r4,r4,-27628
+ 801c884:	8002d9c0 	call	8002d9c <puts>
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+ 801c888:	e0bffe17 	ldw	r2,-8(fp)
+ 801c88c:	1080a004 	addi	r2,r2,640
+ 801c890:	10800037 	ldwio	r2,0(r2)
+ 801c894:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+ 801c898:	e0bffe17 	ldw	r2,-8(fp)
+ 801c89c:	1080a004 	addi	r2,r2,640
+ 801c8a0:	e13fff8b 	ldhu	r4,-2(fp)
+ 801c8a4:	00e00004 	movi	r3,-32768
+ 801c8a8:	20c6b03a 	or	r3,r4,r3
+ 801c8ac:	18ffffcc 	andi	r3,r3,65535
+ 801c8b0:	10c00035 	stwio	r3,0(r2)
+    
+    return 1;
+ 801c8b4:	00800044 	movi	r2,1
+    
+}
+ 801c8b8:	e037883a 	mov	sp,fp
+ 801c8bc:	dfc00117 	ldw	ra,4(sp)
+ 801c8c0:	df000017 	ldw	fp,0(sp)
+ 801c8c4:	dec00204 	addi	sp,sp,8
+ 801c8c8:	f800283a 	ret
+
+0801c8cc <DP83848C_link_status_read>:
+
+/* @Function Description: Read link status from PHY specific status register of DP83848C
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 DP83848C_link_status_read(np_tse_mac *pmac) {
+ 801c8cc:	defffc04 	addi	sp,sp,-16
+ 801c8d0:	df000315 	stw	fp,12(sp)
+ 801c8d4:	df000304 	addi	fp,sp,12
+ 801c8d8:	e13ffd15 	stw	r4,-12(fp)
+    alt_u32 link_status = 0;
+ 801c8dc:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0);
+ 801c8e0:	e0bffd17 	ldw	r2,-12(fp)
+ 801c8e4:	1080b004 	addi	r2,r2,704
+ 801c8e8:	10800037 	ldwio	r2,0(r2)
+ 801c8ec:	e0bffe15 	stw	r2,-8(fp)
+    
+    /* If speed == 10 Mbps */
+    if(reg_status & 0x2) {
+ 801c8f0:	e0bffe17 	ldw	r2,-8(fp)
+ 801c8f4:	1080008c 	andi	r2,r2,2
+ 801c8f8:	10000426 	beq	r2,zero,801c90c <DP83848C_link_status_read+0x40>
+        link_status |= 0x8;
+ 801c8fc:	e0bfff17 	ldw	r2,-4(fp)
+ 801c900:	10800214 	ori	r2,r2,8
+ 801c904:	e0bfff15 	stw	r2,-4(fp)
+ 801c908:	00000306 	br	801c918 <DP83848C_link_status_read+0x4c>
+    }
+    /* Else speed = 100 Mbps */
+    else {
+        link_status |= 0x4;
+ 801c90c:	e0bfff17 	ldw	r2,-4(fp)
+ 801c910:	10800114 	ori	r2,r2,4
+ 801c914:	e0bfff15 	stw	r2,-4(fp)
+    }
+    
+    /* If duplex == Full */
+    if(reg_status & 0x4) {
+ 801c918:	e0bffe17 	ldw	r2,-8(fp)
+ 801c91c:	1080010c 	andi	r2,r2,4
+ 801c920:	10000326 	beq	r2,zero,801c930 <DP83848C_link_status_read+0x64>
+        link_status |= 0x1;
+ 801c924:	e0bfff17 	ldw	r2,-4(fp)
+ 801c928:	10800054 	ori	r2,r2,1
+ 801c92c:	e0bfff15 	stw	r2,-4(fp)
+    }
+    
+    return link_status;
+ 801c930:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801c934:	e037883a 	mov	sp,fp
+ 801c938:	df000017 	ldw	fp,0(sp)
+ 801c93c:	dec00104 	addi	sp,sp,4
+ 801c940:	f800283a 	ret
+
+0801c944 <PEF7071_config>:
+/* @Function Description: Additional configuration for PEF7071 Phy
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 PEF7071_config(np_tse_mac *pmac)
+{  
+ 801c944:	defffd04 	addi	sp,sp,-12
+ 801c948:	df000215 	stw	fp,8(sp)
+ 801c94c:	df000204 	addi	fp,sp,8
+ 801c950:	e13ffe15 	stw	r4,-8(fp)
+    alt_u16 dat;
+        
+    dat = IORD(&pmac->mdio1.reg14, 0);
+ 801c954:	e0bffe17 	ldw	r2,-8(fp)
+ 801c958:	1080b404 	addi	r2,r2,720
+ 801c95c:	10800037 	ldwio	r2,0(r2)
+ 801c960:	e0bfff8d 	sth	r2,-2(fp)
+    dat &= 0x3FFF;
+ 801c964:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801c968:	108fffcc 	andi	r2,r2,16383
+ 801c96c:	e0bfff8d 	sth	r2,-2(fp)
+    dat |= 0x0100;
+ 801c970:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801c974:	10804014 	ori	r2,r2,256
+ 801c978:	e0bfff8d 	sth	r2,-2(fp)
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+ 801c97c:	e0bffe17 	ldw	r2,-8(fp)
+ 801c980:	1080b404 	addi	r2,r2,720
+ 801c984:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801c988:	10c00035 	stwio	r3,0(r2)
+    
+    return 0;
+ 801c98c:	0005883a 	mov	r2,zero
+    
+}
+ 801c990:	e037883a 	mov	sp,fp
+ 801c994:	df000017 	ldw	fp,0(sp)
+ 801c998:	dec00104 	addi	sp,sp,4
+ 801c99c:	f800283a 	ret
+
+0801c9a0 <PEF7071_link_status_read>:
+/* @Function Description: Read link status from PHY specific status register of PEF7071
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 PEF7071_link_status_read(np_tse_mac *pmac)
+{
+ 801c9a0:	defffc04 	addi	sp,sp,-16
+ 801c9a4:	df000315 	stw	fp,12(sp)
+ 801c9a8:	df000304 	addi	fp,sp,12
+ 801c9ac:	e13ffd15 	stw	r4,-12(fp)
+    alt_u32 link_status = 0;
+ 801c9b0:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 reg18 = IORD(&pmac->mdio1.reg18, 0);
+ 801c9b4:	e0bffd17 	ldw	r2,-12(fp)
+ 801c9b8:	1080b804 	addi	r2,r2,736
+ 801c9bc:	10800037 	ldwio	r2,0(r2)
+ 801c9c0:	e0bffe15 	stw	r2,-8(fp)
+        
+    if ((reg18 & 0x3)==0) { link_status |= 0x8; }  /* If speed == 10 Mbps */
+ 801c9c4:	e0bffe17 	ldw	r2,-8(fp)
+ 801c9c8:	108000cc 	andi	r2,r2,3
+ 801c9cc:	1000031e 	bne	r2,zero,801c9dc <PEF7071_link_status_read+0x3c>
+ 801c9d0:	e0bfff17 	ldw	r2,-4(fp)
+ 801c9d4:	10800214 	ori	r2,r2,8
+ 801c9d8:	e0bfff15 	stw	r2,-4(fp)
+    if ((reg18 & 0x3)==1) { link_status |= 0x4; }  /* Else speed = 100 Mbps */
+ 801c9dc:	e0bffe17 	ldw	r2,-8(fp)
+ 801c9e0:	108000cc 	andi	r2,r2,3
+ 801c9e4:	10800058 	cmpnei	r2,r2,1
+ 801c9e8:	1000031e 	bne	r2,zero,801c9f8 <PEF7071_link_status_read+0x58>
+ 801c9ec:	e0bfff17 	ldw	r2,-4(fp)
+ 801c9f0:	10800114 	ori	r2,r2,4
+ 801c9f4:	e0bfff15 	stw	r2,-4(fp)
+    if ((reg18 & 0x3)==2) { link_status |= 0x2; }  /* Else speed = 1000 Mbps */    
+ 801c9f8:	e0bffe17 	ldw	r2,-8(fp)
+ 801c9fc:	108000cc 	andi	r2,r2,3
+ 801ca00:	10800098 	cmpnei	r2,r2,2
+ 801ca04:	1000031e 	bne	r2,zero,801ca14 <PEF7071_link_status_read+0x74>
+ 801ca08:	e0bfff17 	ldw	r2,-4(fp)
+ 801ca0c:	10800094 	ori	r2,r2,2
+ 801ca10:	e0bfff15 	stw	r2,-4(fp)
+        
+    /* If duplex == Full */
+    if(reg18 & 0x8) {
+ 801ca14:	e0bffe17 	ldw	r2,-8(fp)
+ 801ca18:	1080020c 	andi	r2,r2,8
+ 801ca1c:	10000326 	beq	r2,zero,801ca2c <PEF7071_link_status_read+0x8c>
+        link_status |= 0x1;
+ 801ca20:	e0bfff17 	ldw	r2,-4(fp)
+ 801ca24:	10800054 	ori	r2,r2,1
+ 801ca28:	e0bfff15 	stw	r2,-4(fp)
+    }
+    
+    return link_status;
+ 801ca2c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801ca30:	e037883a 	mov	sp,fp
+ 801ca34:	df000017 	ldw	fp,0(sp)
+ 801ca38:	dec00104 	addi	sp,sp,4
+ 801ca3c:	f800283a 	ret
+
+0801ca40 <altera_avalon_uart_read_fd>:
+ *
+ */
+
+int 
+altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space)
+{
+ 801ca40:	defffa04 	addi	sp,sp,-24
+ 801ca44:	dfc00515 	stw	ra,20(sp)
+ 801ca48:	df000415 	stw	fp,16(sp)
+ 801ca4c:	df000404 	addi	fp,sp,16
+ 801ca50:	e13ffe15 	stw	r4,-8(fp)
+ 801ca54:	e17ffd15 	stw	r5,-12(fp)
+ 801ca58:	e1bffc15 	stw	r6,-16(fp)
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+ 801ca5c:	e0bffe17 	ldw	r2,-8(fp)
+ 801ca60:	10800017 	ldw	r2,0(r2)
+ 801ca64:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_uart_read(&dev->state, buffer, space,
+ 801ca68:	e0bfff17 	ldw	r2,-4(fp)
+ 801ca6c:	10c00a04 	addi	r3,r2,40
+ 801ca70:	e0bffe17 	ldw	r2,-8(fp)
+ 801ca74:	10800217 	ldw	r2,8(r2)
+ 801ca78:	100f883a 	mov	r7,r2
+ 801ca7c:	e1bffc17 	ldw	r6,-16(fp)
+ 801ca80:	e17ffd17 	ldw	r5,-12(fp)
+ 801ca84:	1809883a 	mov	r4,r3
+ 801ca88:	801d0b00 	call	801d0b0 <altera_avalon_uart_read>
+      fd->fd_flags);
+}
+ 801ca8c:	e037883a 	mov	sp,fp
+ 801ca90:	dfc00117 	ldw	ra,4(sp)
+ 801ca94:	df000017 	ldw	fp,0(sp)
+ 801ca98:	dec00204 	addi	sp,sp,8
+ 801ca9c:	f800283a 	ret
+
+0801caa0 <altera_avalon_uart_write_fd>:
+
+int 
+altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space)
+{
+ 801caa0:	defffa04 	addi	sp,sp,-24
+ 801caa4:	dfc00515 	stw	ra,20(sp)
+ 801caa8:	df000415 	stw	fp,16(sp)
+ 801caac:	df000404 	addi	fp,sp,16
+ 801cab0:	e13ffe15 	stw	r4,-8(fp)
+ 801cab4:	e17ffd15 	stw	r5,-12(fp)
+ 801cab8:	e1bffc15 	stw	r6,-16(fp)
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+ 801cabc:	e0bffe17 	ldw	r2,-8(fp)
+ 801cac0:	10800017 	ldw	r2,0(r2)
+ 801cac4:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_uart_write(&dev->state, buffer, space,
+ 801cac8:	e0bfff17 	ldw	r2,-4(fp)
+ 801cacc:	10c00a04 	addi	r3,r2,40
+ 801cad0:	e0bffe17 	ldw	r2,-8(fp)
+ 801cad4:	10800217 	ldw	r2,8(r2)
+ 801cad8:	100f883a 	mov	r7,r2
+ 801cadc:	e1bffc17 	ldw	r6,-16(fp)
+ 801cae0:	e17ffd17 	ldw	r5,-12(fp)
+ 801cae4:	1809883a 	mov	r4,r3
+ 801cae8:	801d3540 	call	801d354 <altera_avalon_uart_write>
+      fd->fd_flags);
+}
+ 801caec:	e037883a 	mov	sp,fp
+ 801caf0:	dfc00117 	ldw	ra,4(sp)
+ 801caf4:	df000017 	ldw	fp,0(sp)
+ 801caf8:	dec00204 	addi	sp,sp,8
+ 801cafc:	f800283a 	ret
+
+0801cb00 <altera_avalon_uart_close_fd>:
+
+#endif /* ALTERA_AVALON_UART_USE_IOCTL */
+
+int 
+altera_avalon_uart_close_fd(alt_fd* fd)
+{
+ 801cb00:	defffc04 	addi	sp,sp,-16
+ 801cb04:	dfc00315 	stw	ra,12(sp)
+ 801cb08:	df000215 	stw	fp,8(sp)
+ 801cb0c:	df000204 	addi	fp,sp,8
+ 801cb10:	e13ffe15 	stw	r4,-8(fp)
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+ 801cb14:	e0bffe17 	ldw	r2,-8(fp)
+ 801cb18:	10800017 	ldw	r2,0(r2)
+ 801cb1c:	e0bfff15 	stw	r2,-4(fp)
+
+    return altera_avalon_uart_close(&dev->state, fd->fd_flags);
+ 801cb20:	e0bfff17 	ldw	r2,-4(fp)
+ 801cb24:	10c00a04 	addi	r3,r2,40
+ 801cb28:	e0bffe17 	ldw	r2,-8(fp)
+ 801cb2c:	10800217 	ldw	r2,8(r2)
+ 801cb30:	100b883a 	mov	r5,r2
+ 801cb34:	1809883a 	mov	r4,r3
+ 801cb38:	801d0200 	call	801d020 <altera_avalon_uart_close>
+}
+ 801cb3c:	e037883a 	mov	sp,fp
+ 801cb40:	dfc00117 	ldw	ra,4(sp)
+ 801cb44:	df000017 	ldw	fp,0(sp)
+ 801cb48:	dec00204 	addi	sp,sp,8
+ 801cb4c:	f800283a 	ret
+
+0801cb50 <altera_avalon_uart_init>:
+  alt_u32 status);
+
+void 
+altera_avalon_uart_init(altera_avalon_uart_state* sp, 
+  alt_u32 irq_controller_id,  alt_u32 irq)
+{
+ 801cb50:	defff204 	addi	sp,sp,-56
+ 801cb54:	dfc00d15 	stw	ra,52(sp)
+ 801cb58:	df000c15 	stw	fp,48(sp)
+ 801cb5c:	df000c04 	addi	fp,sp,48
+ 801cb60:	e13ff715 	stw	r4,-36(fp)
+ 801cb64:	e17ff615 	stw	r5,-40(fp)
+ 801cb68:	e1bff515 	stw	r6,-44(fp)
+  void* base = sp->base;
+ 801cb6c:	e0bff717 	ldw	r2,-36(fp)
+ 801cb70:	10800017 	ldw	r2,0(r2)
+ 801cb74:	e0bfff15 	stw	r2,-4(fp)
+  /* 
+   * Initialise the read and write flags and the semaphores used to 
+   * protect access to the circular buffers when running in a multi-threaded
+   * environment.
+   */
+  error = ALT_FLAG_CREATE (&sp->events, 0)    || 
+ 801cb78:	e0bff717 	ldw	r2,-36(fp)
+ 801cb7c:	10800704 	addi	r2,r2,28
+ 801cb80:	e0bffd15 	stw	r2,-12(fp)
+ 801cb84:	e03ffc8d 	sth	zero,-14(fp)
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, 
+               OS_FLAGS flags)
+{
+  INT8U err;
+  *pgroup = OSFlagCreate (flags, &err);
+ 801cb88:	e0bffc8b 	ldhu	r2,-14(fp)
+ 801cb8c:	e0fff844 	addi	r3,fp,-31
+ 801cb90:	180b883a 	mov	r5,r3
+ 801cb94:	1009883a 	mov	r4,r2
+ 801cb98:	8011e780 	call	8011e78 <OSFlagCreate>
+ 801cb9c:	1007883a 	mov	r3,r2
+ 801cba0:	e0bffd17 	ldw	r2,-12(fp)
+ 801cba4:	10c00015 	stw	r3,0(r2)
+  return err;
+ 801cba8:	e0bff843 	ldbu	r2,-31(fp)
+ 801cbac:	10803fcc 	andi	r2,r2,255
+          ALT_SEM_CREATE (&sp->read_lock, 1)  ||
+ 801cbb0:	1000241e 	bne	r2,zero,801cc44 <altera_avalon_uart_init+0xf4>
+ 801cbb4:	e0bff717 	ldw	r2,-36(fp)
+ 801cbb8:	10800804 	addi	r2,r2,32
+ 801cbbc:	e0bffb15 	stw	r2,-20(fp)
+ 801cbc0:	00800044 	movi	r2,1
+ 801cbc4:	e0bffa8d 	sth	r2,-22(fp)
+ 801cbc8:	e0bffa8b 	ldhu	r2,-22(fp)
+ 801cbcc:	1009883a 	mov	r4,r2
+ 801cbd0:	80157740 	call	8015774 <OSSemCreate>
+ 801cbd4:	1007883a 	mov	r3,r2
+ 801cbd8:	e0bffb17 	ldw	r2,-20(fp)
+ 801cbdc:	10c00015 	stw	r3,0(r2)
+  return *sem ? 0 : -1;
+ 801cbe0:	e0bffb17 	ldw	r2,-20(fp)
+ 801cbe4:	10800017 	ldw	r2,0(r2)
+ 801cbe8:	10000226 	beq	r2,zero,801cbf4 <altera_avalon_uart_init+0xa4>
+ 801cbec:	0005883a 	mov	r2,zero
+ 801cbf0:	00000106 	br	801cbf8 <altera_avalon_uart_init+0xa8>
+ 801cbf4:	00bfffc4 	movi	r2,-1
+  error = ALT_FLAG_CREATE (&sp->events, 0)    || 
+ 801cbf8:	1000121e 	bne	r2,zero,801cc44 <altera_avalon_uart_init+0xf4>
+          ALT_SEM_CREATE (&sp->write_lock, 1);
+ 801cbfc:	e0bff717 	ldw	r2,-36(fp)
+ 801cc00:	10800904 	addi	r2,r2,36
+ 801cc04:	e0bff915 	stw	r2,-28(fp)
+ 801cc08:	00800044 	movi	r2,1
+ 801cc0c:	e0bff88d 	sth	r2,-30(fp)
+  *sem = OSSemCreate (value);
+ 801cc10:	e0bff88b 	ldhu	r2,-30(fp)
+ 801cc14:	1009883a 	mov	r4,r2
+ 801cc18:	80157740 	call	8015774 <OSSemCreate>
+ 801cc1c:	1007883a 	mov	r3,r2
+ 801cc20:	e0bff917 	ldw	r2,-28(fp)
+ 801cc24:	10c00015 	stw	r3,0(r2)
+  return *sem ? 0 : -1;
+ 801cc28:	e0bff917 	ldw	r2,-28(fp)
+ 801cc2c:	10800017 	ldw	r2,0(r2)
+ 801cc30:	10000226 	beq	r2,zero,801cc3c <altera_avalon_uart_init+0xec>
+ 801cc34:	0005883a 	mov	r2,zero
+ 801cc38:	00000106 	br	801cc40 <altera_avalon_uart_init+0xf0>
+ 801cc3c:	00bfffc4 	movi	r2,-1
+          ALT_SEM_CREATE (&sp->read_lock, 1)  ||
+ 801cc40:	10000226 	beq	r2,zero,801cc4c <altera_avalon_uart_init+0xfc>
+ 801cc44:	00800044 	movi	r2,1
+ 801cc48:	00000106 	br	801cc50 <altera_avalon_uart_init+0x100>
+ 801cc4c:	0005883a 	mov	r2,zero
+  error = ALT_FLAG_CREATE (&sp->events, 0)    || 
+ 801cc50:	e0bffe15 	stw	r2,-8(fp)
+
+  if (!error)
+ 801cc54:	e0bffe17 	ldw	r2,-8(fp)
+ 801cc58:	10000f1e 	bne	r2,zero,801cc98 <altera_avalon_uart_init+0x148>
+  {
+    /* enable interrupts at the device */
+    sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK  |
+ 801cc5c:	e0bff717 	ldw	r2,-36(fp)
+ 801cc60:	00c32004 	movi	r3,3200
+ 801cc64:	10c00115 	stw	r3,4(r2)
+                ALTERA_AVALON_UART_CONTROL_RRDY_MSK |
+                ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
+
+    IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); 
+ 801cc68:	e0bfff17 	ldw	r2,-4(fp)
+ 801cc6c:	10800304 	addi	r2,r2,12
+ 801cc70:	e0fff717 	ldw	r3,-36(fp)
+ 801cc74:	18c00117 	ldw	r3,4(r3)
+ 801cc78:	10c00035 	stwio	r3,0(r2)
+  
+    /* register the interrupt handler */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+    alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, 
+ 801cc7c:	d8000015 	stw	zero,0(sp)
+ 801cc80:	e1fff717 	ldw	r7,-36(fp)
+ 801cc84:	018200b4 	movhi	r6,2050
+ 801cc88:	31b32c04 	addi	r6,r6,-13136
+ 801cc8c:	e17ff517 	ldw	r5,-44(fp)
+ 801cc90:	e13ff617 	ldw	r4,-40(fp)
+ 801cc94:	80374940 	call	8037494 <alt_ic_isr_register>
+      0x0);
+#else
+    alt_irq_register (irq, sp, altera_avalon_uart_irq);
+#endif  
+  }
+}
+ 801cc98:	0001883a 	nop
+ 801cc9c:	e037883a 	mov	sp,fp
+ 801cca0:	dfc00117 	ldw	ra,4(sp)
+ 801cca4:	df000017 	ldw	fp,0(sp)
+ 801cca8:	dec00204 	addi	sp,sp,8
+ 801ccac:	f800283a 	ret
+
+0801ccb0 <altera_avalon_uart_irq>:
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void altera_avalon_uart_irq(void* context)
+#else
+static void altera_avalon_uart_irq(void* context, alt_u32 id)
+#endif
+{
+ 801ccb0:	defffa04 	addi	sp,sp,-24
+ 801ccb4:	dfc00515 	stw	ra,20(sp)
+ 801ccb8:	df000415 	stw	fp,16(sp)
+ 801ccbc:	df000404 	addi	fp,sp,16
+ 801ccc0:	e13ffc15 	stw	r4,-16(fp)
+  alt_u32 status;
+
+  altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context;
+ 801ccc4:	e0bffc17 	ldw	r2,-16(fp)
+ 801ccc8:	e0bfff15 	stw	r2,-4(fp)
+  void* base               = sp->base;
+ 801cccc:	e0bfff17 	ldw	r2,-4(fp)
+ 801ccd0:	10800017 	ldw	r2,0(r2)
+ 801ccd4:	e0bffe15 	stw	r2,-8(fp)
+  /*
+   * Read the status register in order to determine the cause of the
+   * interrupt.
+   */
+
+  status = IORD_ALTERA_AVALON_UART_STATUS(base);
+ 801ccd8:	e0bffe17 	ldw	r2,-8(fp)
+ 801ccdc:	10800204 	addi	r2,r2,8
+ 801cce0:	10800037 	ldwio	r2,0(r2)
+ 801cce4:	e0bffd15 	stw	r2,-12(fp)
+
+  /* Clear any error flags set at the device */
+  IOWR_ALTERA_AVALON_UART_STATUS(base, 0);
+ 801cce8:	e0bffe17 	ldw	r2,-8(fp)
+ 801ccec:	10800204 	addi	r2,r2,8
+ 801ccf0:	0007883a 	mov	r3,zero
+ 801ccf4:	10c00035 	stwio	r3,0(r2)
+
+  /* Dummy read to ensure IRQ is negated before ISR returns */
+  IORD_ALTERA_AVALON_UART_STATUS(base);
+ 801ccf8:	e0bffe17 	ldw	r2,-8(fp)
+ 801ccfc:	10800204 	addi	r2,r2,8
+ 801cd00:	10800037 	ldwio	r2,0(r2)
+  
+  /* process a read irq */
+  if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK)
+ 801cd04:	e0bffd17 	ldw	r2,-12(fp)
+ 801cd08:	1080200c 	andi	r2,r2,128
+ 801cd0c:	10000326 	beq	r2,zero,801cd1c <altera_avalon_uart_irq+0x6c>
+  {
+    altera_avalon_uart_rxirq(sp, status);
+ 801cd10:	e17ffd17 	ldw	r5,-12(fp)
+ 801cd14:	e13fff17 	ldw	r4,-4(fp)
+ 801cd18:	801cd4c0 	call	801cd4c <altera_avalon_uart_rxirq>
+  }
+
+  /* process a write irq */
+  if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | 
+ 801cd1c:	e0bffd17 	ldw	r2,-12(fp)
+ 801cd20:	1081100c 	andi	r2,r2,1088
+ 801cd24:	10000326 	beq	r2,zero,801cd34 <altera_avalon_uart_irq+0x84>
+                  ALTERA_AVALON_UART_STATUS_DCTS_MSK))
+  {
+    altera_avalon_uart_txirq(sp, status);
+ 801cd28:	e17ffd17 	ldw	r5,-12(fp)
+ 801cd2c:	e13fff17 	ldw	r4,-4(fp)
+ 801cd30:	801ce800 	call	801ce80 <altera_avalon_uart_txirq>
+  }
+  
+
+}
+ 801cd34:	0001883a 	nop
+ 801cd38:	e037883a 	mov	sp,fp
+ 801cd3c:	dfc00117 	ldw	ra,4(sp)
+ 801cd40:	df000017 	ldw	fp,0(sp)
+ 801cd44:	dec00204 	addi	sp,sp,8
+ 801cd48:	f800283a 	ret
+
+0801cd4c <altera_avalon_uart_rxirq>:
+ * the receive circular buffer, and sets the apropriate flags to indicate 
+ * that there is data ready to be processed.
+ */
+static void 
+altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status)
+{
+ 801cd4c:	defff904 	addi	sp,sp,-28
+ 801cd50:	dfc00615 	stw	ra,24(sp)
+ 801cd54:	df000515 	stw	fp,20(sp)
+ 801cd58:	df000504 	addi	fp,sp,20
+ 801cd5c:	e13ffc15 	stw	r4,-16(fp)
+ 801cd60:	e17ffb15 	stw	r5,-20(fp)
+  alt_u32 next;
+  
+  /* If there was an error, discard the data */
+
+  if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | 
+ 801cd64:	e0bffb17 	ldw	r2,-20(fp)
+ 801cd68:	108000cc 	andi	r2,r2,3
+ 801cd6c:	10003e1e 	bne	r2,zero,801ce68 <altera_avalon_uart_rxirq+0x11c>
+   * In a multi-threaded environment, set the read event flag to indicate
+   * that there is data ready. This is only done if the circular buffer was
+   * previously empty.
+   */
+
+  if (sp->rx_end == sp->rx_start)
+ 801cd70:	e0bffc17 	ldw	r2,-16(fp)
+ 801cd74:	10c00317 	ldw	r3,12(r2)
+ 801cd78:	e0bffc17 	ldw	r2,-16(fp)
+ 801cd7c:	10800217 	ldw	r2,8(r2)
+ 801cd80:	1880121e 	bne	r3,r2,801cdcc <altera_avalon_uart_rxirq+0x80>
+  {
+    ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET);
+ 801cd84:	e0bffc17 	ldw	r2,-16(fp)
+ 801cd88:	10800717 	ldw	r2,28(r2)
+ 801cd8c:	e0bffe15 	stw	r2,-8(fp)
+ 801cd90:	00800044 	movi	r2,1
+ 801cd94:	e0bffd8d 	sth	r2,-10(fp)
+ 801cd98:	00800044 	movi	r2,1
+ 801cd9c:	e0bffd45 	stb	r2,-11(fp)
+                   OS_FLAGS     flags, 
+                   INT8U        opt)
+{
+  INT8U err;
+
+  if (OSRunning)
+ 801cda0:	d0a04b43 	ldbu	r2,-32467(gp)
+ 801cda4:	10803fcc 	andi	r2,r2,255
+ 801cda8:	10000826 	beq	r2,zero,801cdcc <altera_avalon_uart_rxirq+0x80>
+  {
+    OSFlagPost (group, flags, opt, &err);
+ 801cdac:	e0bffd8b 	ldhu	r2,-10(fp)
+ 801cdb0:	e0fffd43 	ldbu	r3,-11(fp)
+ 801cdb4:	e13ffd04 	addi	r4,fp,-12
+ 801cdb8:	200f883a 	mov	r7,r4
+ 801cdbc:	180d883a 	mov	r6,r3
+ 801cdc0:	100b883a 	mov	r5,r2
+ 801cdc4:	e13ffe17 	ldw	r4,-8(fp)
+ 801cdc8:	80129700 	call	8012970 <OSFlagPost>
+  }
+
+  /* Determine which slot to use next in the circular buffer */
+
+  next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+ 801cdcc:	e0bffc17 	ldw	r2,-16(fp)
+ 801cdd0:	10800317 	ldw	r2,12(r2)
+ 801cdd4:	10800044 	addi	r2,r2,1
+ 801cdd8:	10800fcc 	andi	r2,r2,63
+ 801cddc:	e0bfff15 	stw	r2,-4(fp)
+
+  /* Transfer data from the device to the circular buffer */
+
+  sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base);
+ 801cde0:	e0bffc17 	ldw	r2,-16(fp)
+ 801cde4:	10800017 	ldw	r2,0(r2)
+ 801cde8:	10c00037 	ldwio	r3,0(r2)
+ 801cdec:	e0bffc17 	ldw	r2,-16(fp)
+ 801cdf0:	10800317 	ldw	r2,12(r2)
+ 801cdf4:	1809883a 	mov	r4,r3
+ 801cdf8:	e0fffc17 	ldw	r3,-16(fp)
+ 801cdfc:	1885883a 	add	r2,r3,r2
+ 801ce00:	11000a05 	stb	r4,40(r2)
+
+  sp->rx_end = next;
+ 801ce04:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce08:	e0ffff17 	ldw	r3,-4(fp)
+ 801ce0c:	10c00315 	stw	r3,12(r2)
+
+  next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+ 801ce10:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce14:	10800317 	ldw	r2,12(r2)
+ 801ce18:	10800044 	addi	r2,r2,1
+ 801ce1c:	10800fcc 	andi	r2,r2,63
+ 801ce20:	e0bfff15 	stw	r2,-4(fp)
+  /*
+   * If the cicular buffer was full, disable interrupts. Interrupts will be
+   * re-enabled when data is removed from the buffer.
+   */
+
+  if (next == sp->rx_start)
+ 801ce24:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce28:	10800217 	ldw	r2,8(r2)
+ 801ce2c:	e0ffff17 	ldw	r3,-4(fp)
+ 801ce30:	18800e1e 	bne	r3,r2,801ce6c <altera_avalon_uart_rxirq+0x120>
+  {
+    sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+ 801ce34:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce38:	10c00117 	ldw	r3,4(r2)
+ 801ce3c:	00bfdfc4 	movi	r2,-129
+ 801ce40:	1886703a 	and	r3,r3,r2
+ 801ce44:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce48:	10c00115 	stw	r3,4(r2)
+    IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); 
+ 801ce4c:	e0bffc17 	ldw	r2,-16(fp)
+ 801ce50:	10800017 	ldw	r2,0(r2)
+ 801ce54:	10800304 	addi	r2,r2,12
+ 801ce58:	e0fffc17 	ldw	r3,-16(fp)
+ 801ce5c:	18c00117 	ldw	r3,4(r3)
+ 801ce60:	10c00035 	stwio	r3,0(r2)
+ 801ce64:	00000106 	br	801ce6c <altera_avalon_uart_rxirq+0x120>
+    return;
+ 801ce68:	0001883a 	nop
+  }   
+}
+ 801ce6c:	e037883a 	mov	sp,fp
+ 801ce70:	dfc00117 	ldw	ra,4(sp)
+ 801ce74:	df000017 	ldw	fp,0(sp)
+ 801ce78:	dec00204 	addi	sp,sp,8
+ 801ce7c:	f800283a 	ret
+
+0801ce80 <altera_avalon_uart_txirq>:
+ * buffer to the device, and sets the apropriate flags to indicate that 
+ * there is data ready to be processed.
+ */
+static void 
+altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status)
+{
+ 801ce80:	defffa04 	addi	sp,sp,-24
+ 801ce84:	dfc00515 	stw	ra,20(sp)
+ 801ce88:	df000415 	stw	fp,16(sp)
+ 801ce8c:	df000404 	addi	fp,sp,16
+ 801ce90:	e13ffd15 	stw	r4,-12(fp)
+ 801ce94:	e17ffc15 	stw	r5,-16(fp)
+  /* Transfer data if there is some ready to be transfered */
+
+  if (sp->tx_start != sp->tx_end)
+ 801ce98:	e0bffd17 	ldw	r2,-12(fp)
+ 801ce9c:	10c00417 	ldw	r3,16(r2)
+ 801cea0:	e0bffd17 	ldw	r2,-12(fp)
+ 801cea4:	10800517 	ldw	r2,20(r2)
+ 801cea8:	18804626 	beq	r3,r2,801cfc4 <altera_avalon_uart_txirq+0x144>
+    /* 
+     * If the device is using flow control (i.e. RTS/CTS), then the
+     * transmitter is required to throttle if CTS is high.
+     */
+
+    if (!(sp->flags & ALT_AVALON_UART_FC) ||
+ 801ceac:	e0bffd17 	ldw	r2,-12(fp)
+ 801ceb0:	10800617 	ldw	r2,24(r2)
+ 801ceb4:	1080008c 	andi	r2,r2,2
+ 801ceb8:	10000326 	beq	r2,zero,801cec8 <altera_avalon_uart_txirq+0x48>
+      (status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
+ 801cebc:	e0bffc17 	ldw	r2,-16(fp)
+ 801cec0:	1082000c 	andi	r2,r2,2048
+    if (!(sp->flags & ALT_AVALON_UART_FC) ||
+ 801cec4:	10003126 	beq	r2,zero,801cf8c <altera_avalon_uart_txirq+0x10c>
+       * In a multi-threaded environment, set the write event flag to indicate
+       * that there is space in the circular buffer. This is only done if the
+       * buffer was previously empty.
+       */
+
+      if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))
+ 801cec8:	e0bffd17 	ldw	r2,-12(fp)
+ 801cecc:	10c00417 	ldw	r3,16(r2)
+ 801ced0:	e0bffd17 	ldw	r2,-12(fp)
+ 801ced4:	10800517 	ldw	r2,20(r2)
+ 801ced8:	10800044 	addi	r2,r2,1
+ 801cedc:	10800fcc 	andi	r2,r2,63
+ 801cee0:	1880121e 	bne	r3,r2,801cf2c <altera_avalon_uart_txirq+0xac>
+      { 
+        ALT_FLAG_POST (sp->events, 
+ 801cee4:	e0bffd17 	ldw	r2,-12(fp)
+ 801cee8:	10800717 	ldw	r2,28(r2)
+ 801ceec:	e0bfff15 	stw	r2,-4(fp)
+ 801cef0:	00800084 	movi	r2,2
+ 801cef4:	e0bffe8d 	sth	r2,-6(fp)
+ 801cef8:	00800044 	movi	r2,1
+ 801cefc:	e0bffe45 	stb	r2,-7(fp)
+  if (OSRunning)
+ 801cf00:	d0a04b43 	ldbu	r2,-32467(gp)
+ 801cf04:	10803fcc 	andi	r2,r2,255
+ 801cf08:	10000826 	beq	r2,zero,801cf2c <altera_avalon_uart_txirq+0xac>
+    OSFlagPost (group, flags, opt, &err);
+ 801cf0c:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801cf10:	e0fffe43 	ldbu	r3,-7(fp)
+ 801cf14:	e13ffe04 	addi	r4,fp,-8
+ 801cf18:	200f883a 	mov	r7,r4
+ 801cf1c:	180d883a 	mov	r6,r3
+ 801cf20:	100b883a 	mov	r5,r2
+ 801cf24:	e13fff17 	ldw	r4,-4(fp)
+ 801cf28:	80129700 	call	8012970 <OSFlagPost>
+                       OS_FLAG_SET);
+      }
+
+      /* Write the data to the device */
+
+      IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]);
+ 801cf2c:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf30:	10800017 	ldw	r2,0(r2)
+ 801cf34:	10800104 	addi	r2,r2,4
+ 801cf38:	e0fffd17 	ldw	r3,-12(fp)
+ 801cf3c:	18c00417 	ldw	r3,16(r3)
+ 801cf40:	e13ffd17 	ldw	r4,-12(fp)
+ 801cf44:	20c7883a 	add	r3,r4,r3
+ 801cf48:	18c01a03 	ldbu	r3,104(r3)
+ 801cf4c:	18c03fcc 	andi	r3,r3,255
+ 801cf50:	10c00035 	stwio	r3,0(r2)
+
+      sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK;
+ 801cf54:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf58:	10800417 	ldw	r2,16(r2)
+ 801cf5c:	10800044 	addi	r2,r2,1
+ 801cf60:	e0fffd17 	ldw	r3,-12(fp)
+ 801cf64:	18800415 	stw	r2,16(r3)
+ 801cf68:	10c00fcc 	andi	r3,r2,63
+ 801cf6c:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf70:	10c00415 	stw	r3,16(r2)
+      /*
+       * In case the tranmit interrupt had previously been disabled by 
+       * detecting a low value on CTS, it is reenabled here.
+       */ 
+
+      sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+ 801cf74:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf78:	10800117 	ldw	r2,4(r2)
+ 801cf7c:	10c01014 	ori	r3,r2,64
+ 801cf80:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf84:	10c00115 	stw	r3,4(r2)
+ 801cf88:	00000e06 	br	801cfc4 <altera_avalon_uart_txirq+0x144>
+       * the last write to the status register. To avoid this resulting in
+       * deadlock, it's necessary to re-check the status register here
+       * before throttling.
+       */
+ 
+      status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); 
+ 801cf8c:	e0bffd17 	ldw	r2,-12(fp)
+ 801cf90:	10800017 	ldw	r2,0(r2)
+ 801cf94:	10800204 	addi	r2,r2,8
+ 801cf98:	10800037 	ldwio	r2,0(r2)
+ 801cf9c:	e0bffc15 	stw	r2,-16(fp)
+
+      if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
+ 801cfa0:	e0bffc17 	ldw	r2,-16(fp)
+ 801cfa4:	1082000c 	andi	r2,r2,2048
+ 801cfa8:	1000061e 	bne	r2,zero,801cfc4 <altera_avalon_uart_txirq+0x144>
+      {
+        sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+ 801cfac:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfb0:	10c00117 	ldw	r3,4(r2)
+ 801cfb4:	00bfefc4 	movi	r2,-65
+ 801cfb8:	1886703a 	and	r3,r3,r2
+ 801cfbc:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfc0:	10c00115 	stw	r3,4(r2)
+  /*
+   * If the circular buffer is empty, disable the interrupt. This will be
+   * re-enabled when new data is placed in the buffer.
+   */
+
+  if (sp->tx_start == sp->tx_end)
+ 801cfc4:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfc8:	10c00417 	ldw	r3,16(r2)
+ 801cfcc:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfd0:	10800517 	ldw	r2,20(r2)
+ 801cfd4:	1880061e 	bne	r3,r2,801cff0 <altera_avalon_uart_txirq+0x170>
+  {
+    sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+ 801cfd8:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfdc:	10c00117 	ldw	r3,4(r2)
+ 801cfe0:	00beefc4 	movi	r2,-1089
+ 801cfe4:	1886703a 	and	r3,r3,r2
+ 801cfe8:	e0bffd17 	ldw	r2,-12(fp)
+ 801cfec:	10c00115 	stw	r3,4(r2)
+                    ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
+  }
+
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+ 801cff0:	e0bffd17 	ldw	r2,-12(fp)
+ 801cff4:	10800017 	ldw	r2,0(r2)
+ 801cff8:	10800304 	addi	r2,r2,12
+ 801cffc:	e0fffd17 	ldw	r3,-12(fp)
+ 801d000:	18c00117 	ldw	r3,4(r3)
+ 801d004:	10c00035 	stwio	r3,0(r2)
+}
+ 801d008:	0001883a 	nop
+ 801d00c:	e037883a 	mov	sp,fp
+ 801d010:	dfc00117 	ldw	ra,4(sp)
+ 801d014:	df000017 	ldw	fp,0(sp)
+ 801d018:	dec00204 	addi	sp,sp,8
+ 801d01c:	f800283a 	ret
+
+0801d020 <altera_avalon_uart_close>:
+ * The close routine is not implemented for the small driver; instead it will
+ * map to null. This is because the small driver simply waits while characters
+ * are transmitted; there is no interrupt-serviced buffer to empty 
+ */
+int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags)
+{
+ 801d020:	defffd04 	addi	sp,sp,-12
+ 801d024:	df000215 	stw	fp,8(sp)
+ 801d028:	df000204 	addi	fp,sp,8
+ 801d02c:	e13fff15 	stw	r4,-4(fp)
+ 801d030:	e17ffe15 	stw	r5,-8(fp)
+  /* 
+   * Wait for all transmit data to be emptied by the UART ISR.
+   */
+  while (sp->tx_start != sp->tx_end) {
+ 801d034:	00000506 	br	801d04c <altera_avalon_uart_close+0x2c>
+    if (flags & O_NONBLOCK) {
+ 801d038:	e0bffe17 	ldw	r2,-8(fp)
+ 801d03c:	1090000c 	andi	r2,r2,16384
+ 801d040:	10000226 	beq	r2,zero,801d04c <altera_avalon_uart_close+0x2c>
+      return -EWOULDBLOCK; 
+ 801d044:	00bffd44 	movi	r2,-11
+ 801d048:	00000606 	br	801d064 <altera_avalon_uart_close+0x44>
+  while (sp->tx_start != sp->tx_end) {
+ 801d04c:	e0bfff17 	ldw	r2,-4(fp)
+ 801d050:	10c00417 	ldw	r3,16(r2)
+ 801d054:	e0bfff17 	ldw	r2,-4(fp)
+ 801d058:	10800517 	ldw	r2,20(r2)
+ 801d05c:	18bff61e 	bne	r3,r2,801d038 <altera_avalon_uart_close+0x18>
+    }
+  }
+
+  return 0;
+ 801d060:	0005883a 	mov	r2,zero
+}
+ 801d064:	e037883a 	mov	sp,fp
+ 801d068:	df000017 	ldw	fp,0(sp)
+ 801d06c:	dec00104 	addi	sp,sp,4
+ 801d070:	f800283a 	ret
+
+0801d074 <alt_get_errno>:
+{
+ 801d074:	defffe04 	addi	sp,sp,-8
+ 801d078:	dfc00115 	stw	ra,4(sp)
+ 801d07c:	df000015 	stw	fp,0(sp)
+ 801d080:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 801d084:	d0a02717 	ldw	r2,-32612(gp)
+ 801d088:	10000326 	beq	r2,zero,801d098 <alt_get_errno+0x24>
+ 801d08c:	d0a02717 	ldw	r2,-32612(gp)
+ 801d090:	103ee83a 	callr	r2
+ 801d094:	00000106 	br	801d09c <alt_get_errno+0x28>
+ 801d098:	d0a04204 	addi	r2,gp,-32504
+}
+ 801d09c:	e037883a 	mov	sp,fp
+ 801d0a0:	dfc00117 	ldw	ra,4(sp)
+ 801d0a4:	df000017 	ldw	fp,0(sp)
+ 801d0a8:	dec00204 	addi	sp,sp,8
+ 801d0ac:	f800283a 	ret
+
+0801d0b0 <altera_avalon_uart_read>:
+ */
+
+int 
+altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len,
+  int flags)
+{
+ 801d0b0:	deffeb04 	addi	sp,sp,-84
+ 801d0b4:	dfc01415 	stw	ra,80(sp)
+ 801d0b8:	df001315 	stw	fp,76(sp)
+ 801d0bc:	df001304 	addi	fp,sp,76
+ 801d0c0:	e13ff115 	stw	r4,-60(fp)
+ 801d0c4:	e17ff015 	stw	r5,-64(fp)
+ 801d0c8:	e1bfef15 	stw	r6,-68(fp)
+ 801d0cc:	e1ffee15 	stw	r7,-72(fp)
+  alt_irq_context context;
+  int             block;
+  alt_u8          read_would_block = 0;
+ 801d0d0:	e03fffc5 	stb	zero,-1(fp)
+  int             count = 0;
+ 801d0d4:	e03ffe15 	stw	zero,-8(fp)
+  /* 
+   * Construct a flag to indicate whether the device is being accessed in
+   * blocking or non-blocking mode.
+   */
+
+  block = !(flags & O_NONBLOCK);
+ 801d0d8:	e0bfee17 	ldw	r2,-72(fp)
+ 801d0dc:	1090000c 	andi	r2,r2,16384
+ 801d0e0:	1005003a 	cmpeq	r2,r2,zero
+ 801d0e4:	10803fcc 	andi	r2,r2,255
+ 801d0e8:	e0bffd15 	stw	r2,-12(fp)
+  /*
+   * When running in a multi threaded environment, obtain the "read_lock"
+   * semaphore. This ensures that reading from the device is thread-safe.
+   */
+
+  ALT_SEM_PEND (sp->read_lock, 0);
+ 801d0ec:	e0bff117 	ldw	r2,-60(fp)
+ 801d0f0:	10800817 	ldw	r2,32(r2)
+ 801d0f4:	e0bffb15 	stw	r2,-20(fp)
+ 801d0f8:	e03ffa8d 	sth	zero,-22(fp)
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, 
+                  INT16U timeout)
+{
+  INT8U err;
+  OSSemPend (sem, timeout, &err);
+ 801d0fc:	e0bffa8b 	ldhu	r2,-22(fp)
+ 801d100:	e0fff284 	addi	r3,fp,-54
+ 801d104:	180d883a 	mov	r6,r3
+ 801d108:	100b883a 	mov	r5,r2
+ 801d10c:	e13ffb17 	ldw	r4,-20(fp)
+ 801d110:	8015a600 	call	8015a60 <OSSemPend>
+    /*
+     * Read the required amount of data, until the circular buffer runs
+     * empty
+     */
+
+    while ((count < len) && (sp->rx_start != sp->rx_end))
+ 801d114:	00001306 	br	801d164 <altera_avalon_uart_read+0xb4>
+    {
+      count++;
+ 801d118:	e0bffe17 	ldw	r2,-8(fp)
+ 801d11c:	10800044 	addi	r2,r2,1
+ 801d120:	e0bffe15 	stw	r2,-8(fp)
+      *ptr++ = sp->rx_buf[sp->rx_start];
+ 801d124:	e0bff117 	ldw	r2,-60(fp)
+ 801d128:	10800217 	ldw	r2,8(r2)
+ 801d12c:	e0fff117 	ldw	r3,-60(fp)
+ 801d130:	1885883a 	add	r2,r3,r2
+ 801d134:	11000a03 	ldbu	r4,40(r2)
+ 801d138:	e0bff017 	ldw	r2,-64(fp)
+ 801d13c:	10c00044 	addi	r3,r2,1
+ 801d140:	e0fff015 	stw	r3,-64(fp)
+ 801d144:	2007883a 	mov	r3,r4
+ 801d148:	10c00005 	stb	r3,0(r2)
+      
+      sp->rx_start = (sp->rx_start+1) & ALT_AVALON_UART_BUF_MSK;
+ 801d14c:	e0bff117 	ldw	r2,-60(fp)
+ 801d150:	10800217 	ldw	r2,8(r2)
+ 801d154:	10800044 	addi	r2,r2,1
+ 801d158:	10c00fcc 	andi	r3,r2,63
+ 801d15c:	e0bff117 	ldw	r2,-60(fp)
+ 801d160:	10c00215 	stw	r3,8(r2)
+    while ((count < len) && (sp->rx_start != sp->rx_end))
+ 801d164:	e0fffe17 	ldw	r3,-8(fp)
+ 801d168:	e0bfef17 	ldw	r2,-68(fp)
+ 801d16c:	1880050e 	bge	r3,r2,801d184 <altera_avalon_uart_read+0xd4>
+ 801d170:	e0bff117 	ldw	r2,-60(fp)
+ 801d174:	10c00217 	ldw	r3,8(r2)
+ 801d178:	e0bff117 	ldw	r2,-60(fp)
+ 801d17c:	10800317 	ldw	r2,12(r2)
+ 801d180:	18bfe51e 	bne	r3,r2,801d118 <altera_avalon_uart_read+0x68>
+    /*
+     * If no data has been transferred, the circular buffer is empty, and
+     * this is not a non-blocking access, block waiting for data to arrive.
+     */
+
+    if (!count && (sp->rx_start == sp->rx_end))
+ 801d184:	e0bffe17 	ldw	r2,-8(fp)
+ 801d188:	10003a1e 	bne	r2,zero,801d274 <altera_avalon_uart_read+0x1c4>
+ 801d18c:	e0bff117 	ldw	r2,-60(fp)
+ 801d190:	10c00217 	ldw	r3,8(r2)
+ 801d194:	e0bff117 	ldw	r2,-60(fp)
+ 801d198:	10800317 	ldw	r2,12(r2)
+ 801d19c:	1880351e 	bne	r3,r2,801d274 <altera_avalon_uart_read+0x1c4>
+    {
+      if (!block)
+ 801d1a0:	e0bffd17 	ldw	r2,-12(fp)
+ 801d1a4:	1000071e 	bne	r2,zero,801d1c4 <altera_avalon_uart_read+0x114>
+      {
+        /* Set errno to indicate the reason we're not returning any data */
+
+        ALT_ERRNO = EWOULDBLOCK;
+ 801d1a8:	801d0740 	call	801d074 <alt_get_errno>
+ 801d1ac:	1007883a 	mov	r3,r2
+ 801d1b0:	008002c4 	movi	r2,11
+ 801d1b4:	18800015 	stw	r2,0(r3)
+        read_would_block = 1;
+ 801d1b8:	00800044 	movi	r2,1
+ 801d1bc:	e0bfffc5 	stb	r2,-1(fp)
+        break;
+ 801d1c0:	00003006 	br	801d284 <altera_avalon_uart_read+0x1d4>
+  NIOS2_READ_STATUS (context);
+ 801d1c4:	0005303a 	rdctl	r2,status
+ 801d1c8:	e0bff515 	stw	r2,-44(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801d1cc:	e0fff517 	ldw	r3,-44(fp)
+ 801d1d0:	00bfff84 	movi	r2,-2
+ 801d1d4:	1884703a 	and	r2,r3,r2
+ 801d1d8:	1001703a 	wrctl	status,r2
+  return context;
+ 801d1dc:	e0bff517 	ldw	r2,-44(fp)
+      {
+       /* Block waiting for some data to arrive */
+
+       /* First, ensure read interrupts are enabled to avoid deadlock */
+
+       context = alt_irq_disable_all ();
+ 801d1e0:	e0bffc15 	stw	r2,-16(fp)
+       sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+ 801d1e4:	e0bff117 	ldw	r2,-60(fp)
+ 801d1e8:	10800117 	ldw	r2,4(r2)
+ 801d1ec:	10c02014 	ori	r3,r2,128
+ 801d1f0:	e0bff117 	ldw	r2,-60(fp)
+ 801d1f4:	10c00115 	stw	r3,4(r2)
+       IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+ 801d1f8:	e0bff117 	ldw	r2,-60(fp)
+ 801d1fc:	10800017 	ldw	r2,0(r2)
+ 801d200:	10800304 	addi	r2,r2,12
+ 801d204:	e0fff117 	ldw	r3,-60(fp)
+ 801d208:	18c00117 	ldw	r3,4(r3)
+ 801d20c:	10c00035 	stwio	r3,0(r2)
+ 801d210:	e0bffc17 	ldw	r2,-16(fp)
+ 801d214:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801d218:	e0bff617 	ldw	r2,-40(fp)
+ 801d21c:	1001703a 	wrctl	status,r2
+        * flag set in the interrupt service routine. This avoids wasting CPU
+        * cycles waiting in this thread, when we could be doing something more 
+        * profitable elsewhere.
+        */
+
+       ALT_FLAG_PEND (sp->events, 
+ 801d220:	e0bff117 	ldw	r2,-60(fp)
+ 801d224:	10800717 	ldw	r2,28(r2)
+ 801d228:	e0bff915 	stw	r2,-28(fp)
+ 801d22c:	00800044 	movi	r2,1
+ 801d230:	e0bff88d 	sth	r2,-30(fp)
+ 801d234:	00bfe0c4 	movi	r2,-125
+ 801d238:	e0bff845 	stb	r2,-31(fp)
+ 801d23c:	e03ff78d 	sth	zero,-34(fp)
+  if (OSRunning)
+ 801d240:	d0a04b43 	ldbu	r2,-32467(gp)
+ 801d244:	10803fcc 	andi	r2,r2,255
+ 801d248:	10000a26 	beq	r2,zero,801d274 <altera_avalon_uart_read+0x1c4>
+    OSFlagPend (group, flags, wait_type, timeout, &err);
+ 801d24c:	e0fff88b 	ldhu	r3,-30(fp)
+ 801d250:	e13ff843 	ldbu	r4,-31(fp)
+ 801d254:	e17ff78b 	ldhu	r5,-34(fp)
+ 801d258:	e0bff2c4 	addi	r2,fp,-53
+ 801d25c:	d8800015 	stw	r2,0(sp)
+ 801d260:	280f883a 	mov	r7,r5
+ 801d264:	200d883a 	mov	r6,r4
+ 801d268:	180b883a 	mov	r5,r3
+ 801d26c:	e13ff917 	ldw	r4,-28(fp)
+ 801d270:	80123780 	call	8012378 <OSFlagPend>
+                      OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
+                      0);
+      }
+    }
+  }
+  while (!count && len);
+ 801d274:	e0bffe17 	ldw	r2,-8(fp)
+ 801d278:	1000021e 	bne	r2,zero,801d284 <altera_avalon_uart_read+0x1d4>
+ 801d27c:	e0bfef17 	ldw	r2,-68(fp)
+ 801d280:	103fb81e 	bne	r2,zero,801d164 <altera_avalon_uart_read+0xb4>
+  /*
+   * Now that access to the circular buffer is complete, release the read
+   * semaphore so that other threads can access the buffer.
+   */
+
+  ALT_SEM_POST (sp->read_lock);
+ 801d284:	e0bff117 	ldw	r2,-60(fp)
+ 801d288:	10800817 	ldw	r2,32(r2)
+ 801d28c:	1009883a 	mov	r4,r2
+ 801d290:	8015d840 	call	8015d84 <OSSemPost>
+  NIOS2_READ_STATUS (context);
+ 801d294:	0005303a 	rdctl	r2,status
+ 801d298:	e0bff315 	stw	r2,-52(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801d29c:	e0fff317 	ldw	r3,-52(fp)
+ 801d2a0:	00bfff84 	movi	r2,-2
+ 801d2a4:	1884703a 	and	r2,r3,r2
+ 801d2a8:	1001703a 	wrctl	status,r2
+  return context;
+ 801d2ac:	e0bff317 	ldw	r2,-52(fp)
+  /*
+   * Ensure that interrupts are enabled, so that the circular buffer can
+   * re-fill.
+   */
+
+  context = alt_irq_disable_all ();
+ 801d2b0:	e0bffc15 	stw	r2,-16(fp)
+  sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+ 801d2b4:	e0bff117 	ldw	r2,-60(fp)
+ 801d2b8:	10800117 	ldw	r2,4(r2)
+ 801d2bc:	10c02014 	ori	r3,r2,128
+ 801d2c0:	e0bff117 	ldw	r2,-60(fp)
+ 801d2c4:	10c00115 	stw	r3,4(r2)
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+ 801d2c8:	e0bff117 	ldw	r2,-60(fp)
+ 801d2cc:	10800017 	ldw	r2,0(r2)
+ 801d2d0:	10800304 	addi	r2,r2,12
+ 801d2d4:	e0fff117 	ldw	r3,-60(fp)
+ 801d2d8:	18c00117 	ldw	r3,4(r3)
+ 801d2dc:	10c00035 	stwio	r3,0(r2)
+ 801d2e0:	e0bffc17 	ldw	r2,-16(fp)
+ 801d2e4:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801d2e8:	e0bff417 	ldw	r2,-48(fp)
+ 801d2ec:	1001703a 	wrctl	status,r2
+  alt_irq_enable_all (context);
+
+  /* Return the number of bytes read */
+  if(read_would_block) {
+ 801d2f0:	e0bfffc3 	ldbu	r2,-1(fp)
+ 801d2f4:	10000226 	beq	r2,zero,801d300 <altera_avalon_uart_read+0x250>
+    return -EWOULDBLOCK;
+ 801d2f8:	00bffd44 	movi	r2,-11
+ 801d2fc:	00000106 	br	801d304 <altera_avalon_uart_read+0x254>
+  }
+  else {
+    return count;
+ 801d300:	e0bffe17 	ldw	r2,-8(fp)
+  }
+}
+ 801d304:	e037883a 	mov	sp,fp
+ 801d308:	dfc00117 	ldw	ra,4(sp)
+ 801d30c:	df000017 	ldw	fp,0(sp)
+ 801d310:	dec00204 	addi	sp,sp,8
+ 801d314:	f800283a 	ret
+
+0801d318 <alt_get_errno>:
+{
+ 801d318:	defffe04 	addi	sp,sp,-8
+ 801d31c:	dfc00115 	stw	ra,4(sp)
+ 801d320:	df000015 	stw	fp,0(sp)
+ 801d324:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 801d328:	d0a02717 	ldw	r2,-32612(gp)
+ 801d32c:	10000326 	beq	r2,zero,801d33c <alt_get_errno+0x24>
+ 801d330:	d0a02717 	ldw	r2,-32612(gp)
+ 801d334:	103ee83a 	callr	r2
+ 801d338:	00000106 	br	801d340 <alt_get_errno+0x28>
+ 801d33c:	d0a04204 	addi	r2,gp,-32504
+}
+ 801d340:	e037883a 	mov	sp,fp
+ 801d344:	dfc00117 	ldw	ra,4(sp)
+ 801d348:	df000017 	ldw	fp,0(sp)
+ 801d34c:	dec00204 	addi	sp,sp,8
+ 801d350:	f800283a 	ret
+
+0801d354 <altera_avalon_uart_write>:
+ */
+
+int
+altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len,
+  int flags)
+{
+ 801d354:	deffeb04 	addi	sp,sp,-84
+ 801d358:	dfc01415 	stw	ra,80(sp)
+ 801d35c:	df001315 	stw	fp,76(sp)
+ 801d360:	df001304 	addi	fp,sp,76
+ 801d364:	e13ff115 	stw	r4,-60(fp)
+ 801d368:	e17ff015 	stw	r5,-64(fp)
+ 801d36c:	e1bfef15 	stw	r6,-68(fp)
+ 801d370:	e1ffee15 	stw	r7,-72(fp)
+  alt_irq_context context;
+  int             no_block;
+  alt_u32         next;
+  int             count = len;
+ 801d374:	e0bfef17 	ldw	r2,-68(fp)
+ 801d378:	e0bfff15 	stw	r2,-4(fp)
+  /* 
+   * Construct a flag to indicate whether the device is being accessed in
+   * blocking or non-blocking mode.
+   */
+
+  no_block = (flags & O_NONBLOCK);
+ 801d37c:	e0bfee17 	ldw	r2,-72(fp)
+ 801d380:	1090000c 	andi	r2,r2,16384
+ 801d384:	e0bffe15 	stw	r2,-8(fp)
+  /*
+   * When running in a multi threaded environment, obtain the "write_lock"
+   * semaphore. This ensures that writing to the device is thread-safe.
+   */
+
+  ALT_SEM_PEND (sp->write_lock, 0);
+ 801d388:	e0bff117 	ldw	r2,-60(fp)
+ 801d38c:	10800917 	ldw	r2,36(r2)
+ 801d390:	e0bffb15 	stw	r2,-20(fp)
+ 801d394:	e03ffa8d 	sth	zero,-22(fp)
+ 801d398:	e0bffa8b 	ldhu	r2,-22(fp)
+ 801d39c:	e0fff284 	addi	r3,fp,-54
+ 801d3a0:	180d883a 	mov	r6,r3
+ 801d3a4:	100b883a 	mov	r5,r2
+ 801d3a8:	e13ffb17 	ldw	r4,-20(fp)
+ 801d3ac:	8015a600 	call	8015a60 <OSSemPend>
+   * Loop transferring data from the input buffer to the transmit circular
+   * buffer. The loop is terminated once all the data has been transferred,
+   * or, (if in non-blocking mode) the buffer becomes full.
+   */
+
+  while (count)
+ 801d3b0:	00005006 	br	801d4f4 <altera_avalon_uart_write+0x1a0>
+  {
+    /* Determine the next slot in the buffer to access */
+
+    next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+ 801d3b4:	e0bff117 	ldw	r2,-60(fp)
+ 801d3b8:	10800517 	ldw	r2,20(r2)
+ 801d3bc:	10800044 	addi	r2,r2,1
+ 801d3c0:	10800fcc 	andi	r2,r2,63
+ 801d3c4:	e0bffd15 	stw	r2,-12(fp)
+
+    /* block waiting for space if necessary */
+
+    if (next == sp->tx_start)
+ 801d3c8:	e0bff117 	ldw	r2,-60(fp)
+ 801d3cc:	10800417 	ldw	r2,16(r2)
+ 801d3d0:	e0fffd17 	ldw	r3,-12(fp)
+ 801d3d4:	1880371e 	bne	r3,r2,801d4b4 <altera_avalon_uart_write+0x160>
+    {
+      if (no_block)
+ 801d3d8:	e0bffe17 	ldw	r2,-8(fp)
+ 801d3dc:	10000526 	beq	r2,zero,801d3f4 <altera_avalon_uart_write+0xa0>
+      {
+        /* Set errno to indicate why this function returned early */
+ 
+        ALT_ERRNO = EWOULDBLOCK;
+ 801d3e0:	801d3180 	call	801d318 <alt_get_errno>
+ 801d3e4:	1007883a 	mov	r3,r2
+ 801d3e8:	008002c4 	movi	r2,11
+ 801d3ec:	18800015 	stw	r2,0(r3)
+        break;
+ 801d3f0:	00004206 	br	801d4fc <altera_avalon_uart_write+0x1a8>
+  NIOS2_READ_STATUS (context);
+ 801d3f4:	0005303a 	rdctl	r2,status
+ 801d3f8:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801d3fc:	e0fff817 	ldw	r3,-32(fp)
+ 801d400:	00bfff84 	movi	r2,-2
+ 801d404:	1884703a 	and	r2,r3,r2
+ 801d408:	1001703a 	wrctl	status,r2
+  return context;
+ 801d40c:	e0bff817 	ldw	r2,-32(fp)
+      {
+        /* Block waiting for space in the circular buffer */
+
+        /* First, ensure transmit interrupts are enabled to avoid deadlock */
+
+        context = alt_irq_disable_all ();
+ 801d410:	e0bffc15 	stw	r2,-16(fp)
+        sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+ 801d414:	e0bff117 	ldw	r2,-60(fp)
+ 801d418:	10800117 	ldw	r2,4(r2)
+ 801d41c:	10c11014 	ori	r3,r2,1088
+ 801d420:	e0bff117 	ldw	r2,-60(fp)
+ 801d424:	10c00115 	stw	r3,4(r2)
+                        ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
+        IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+ 801d428:	e0bff117 	ldw	r2,-60(fp)
+ 801d42c:	10800017 	ldw	r2,0(r2)
+ 801d430:	10800304 	addi	r2,r2,12
+ 801d434:	e0fff117 	ldw	r3,-60(fp)
+ 801d438:	18c00117 	ldw	r3,4(r3)
+ 801d43c:	10c00035 	stwio	r3,0(r2)
+ 801d440:	e0bffc17 	ldw	r2,-16(fp)
+ 801d444:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801d448:	e0bff917 	ldw	r2,-28(fp)
+ 801d44c:	1001703a 	wrctl	status,r2
+           * flag set in the interrupt service routine. This avoids wasting CPU
+           * cycles waiting in this thread, when we could be doing something
+           * more profitable elsewhere.
+           */
+
+          ALT_FLAG_PEND (sp->events, 
+ 801d450:	e0bff117 	ldw	r2,-60(fp)
+ 801d454:	10800717 	ldw	r2,28(r2)
+ 801d458:	e0bff715 	stw	r2,-36(fp)
+ 801d45c:	00800084 	movi	r2,2
+ 801d460:	e0bff68d 	sth	r2,-38(fp)
+ 801d464:	00bfe0c4 	movi	r2,-125
+ 801d468:	e0bff645 	stb	r2,-39(fp)
+ 801d46c:	e03ff58d 	sth	zero,-42(fp)
+  if (OSRunning)
+ 801d470:	d0a04b43 	ldbu	r2,-32467(gp)
+ 801d474:	10803fcc 	andi	r2,r2,255
+ 801d478:	10000a26 	beq	r2,zero,801d4a4 <altera_avalon_uart_write+0x150>
+    OSFlagPend (group, flags, wait_type, timeout, &err);
+ 801d47c:	e0fff68b 	ldhu	r3,-38(fp)
+ 801d480:	e13ff643 	ldbu	r4,-39(fp)
+ 801d484:	e17ff58b 	ldhu	r5,-42(fp)
+ 801d488:	e0bff2c4 	addi	r2,fp,-53
+ 801d48c:	d8800015 	stw	r2,0(sp)
+ 801d490:	280f883a 	mov	r7,r5
+ 801d494:	200d883a 	mov	r6,r4
+ 801d498:	180b883a 	mov	r5,r3
+ 801d49c:	e13ff717 	ldw	r4,-36(fp)
+ 801d4a0:	80123780 	call	8012378 <OSFlagPend>
+                         ALT_UART_WRITE_RDY,
+                         OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
+                         0);
+        }
+        while ((next == sp->tx_start));
+ 801d4a4:	e0bff117 	ldw	r2,-60(fp)
+ 801d4a8:	10800417 	ldw	r2,16(r2)
+ 801d4ac:	e0fffd17 	ldw	r3,-12(fp)
+ 801d4b0:	18bfe726 	beq	r3,r2,801d450 <altera_avalon_uart_write+0xfc>
+      }
+    }
+
+    count--;
+ 801d4b4:	e0bfff17 	ldw	r2,-4(fp)
+ 801d4b8:	10bfffc4 	addi	r2,r2,-1
+ 801d4bc:	e0bfff15 	stw	r2,-4(fp)
+
+    /* Add the next character to the transmit buffer */
+
+    sp->tx_buf[sp->tx_end] = *ptr++;
+ 801d4c0:	e0bff017 	ldw	r2,-64(fp)
+ 801d4c4:	10c00044 	addi	r3,r2,1
+ 801d4c8:	e0fff015 	stw	r3,-64(fp)
+ 801d4cc:	10c00003 	ldbu	r3,0(r2)
+ 801d4d0:	e0bff117 	ldw	r2,-60(fp)
+ 801d4d4:	10800517 	ldw	r2,20(r2)
+ 801d4d8:	1809883a 	mov	r4,r3
+ 801d4dc:	e0fff117 	ldw	r3,-60(fp)
+ 801d4e0:	1885883a 	add	r2,r3,r2
+ 801d4e4:	11001a05 	stb	r4,104(r2)
+    sp->tx_end = next;
+ 801d4e8:	e0bff117 	ldw	r2,-60(fp)
+ 801d4ec:	e0fffd17 	ldw	r3,-12(fp)
+ 801d4f0:	10c00515 	stw	r3,20(r2)
+  while (count)
+ 801d4f4:	e0bfff17 	ldw	r2,-4(fp)
+ 801d4f8:	103fae1e 	bne	r2,zero,801d3b4 <altera_avalon_uart_write+0x60>
+  /*
+   * Now that access to the circular buffer is complete, release the write
+   * semaphore so that other threads can access the buffer.
+   */
+
+  ALT_SEM_POST (sp->write_lock);
+ 801d4fc:	e0bff117 	ldw	r2,-60(fp)
+ 801d500:	10800917 	ldw	r2,36(r2)
+ 801d504:	1009883a 	mov	r4,r2
+ 801d508:	8015d840 	call	8015d84 <OSSemPost>
+  NIOS2_READ_STATUS (context);
+ 801d50c:	0005303a 	rdctl	r2,status
+ 801d510:	e0bff315 	stw	r2,-52(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801d514:	e0fff317 	ldw	r3,-52(fp)
+ 801d518:	00bfff84 	movi	r2,-2
+ 801d51c:	1884703a 	and	r2,r3,r2
+ 801d520:	1001703a 	wrctl	status,r2
+  return context;
+ 801d524:	e0bff317 	ldw	r2,-52(fp)
+  /* 
+   * Ensure that interrupts are enabled, so that the circular buffer can 
+   * drain.
+   */
+
+  context = alt_irq_disable_all ();
+ 801d528:	e0bffc15 	stw	r2,-16(fp)
+  sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+ 801d52c:	e0bff117 	ldw	r2,-60(fp)
+ 801d530:	10800117 	ldw	r2,4(r2)
+ 801d534:	10c11014 	ori	r3,r2,1088
+ 801d538:	e0bff117 	ldw	r2,-60(fp)
+ 801d53c:	10c00115 	stw	r3,4(r2)
+                 ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+ 801d540:	e0bff117 	ldw	r2,-60(fp)
+ 801d544:	10800017 	ldw	r2,0(r2)
+ 801d548:	10800304 	addi	r2,r2,12
+ 801d54c:	e0fff117 	ldw	r3,-60(fp)
+ 801d550:	18c00117 	ldw	r3,4(r3)
+ 801d554:	10c00035 	stwio	r3,0(r2)
+ 801d558:	e0bffc17 	ldw	r2,-16(fp)
+ 801d55c:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801d560:	e0bff417 	ldw	r2,-48(fp)
+ 801d564:	1001703a 	wrctl	status,r2
+  alt_irq_enable_all (context);
+
+  /* return the number of bytes written */
+
+  return (len - count);
+ 801d568:	e0ffef17 	ldw	r3,-68(fp)
+ 801d56c:	e0bfff17 	ldw	r2,-4(fp)
+ 801d570:	1885c83a 	sub	r2,r3,r2
+}
+ 801d574:	e037883a 	mov	sp,fp
+ 801d578:	dfc00117 	ldw	ra,4(sp)
+ 801d57c:	df000017 	ldw	fp,0(sp)
+ 801d580:	dec00204 	addi	sp,sp,8
+ 801d584:	f800283a 	ret
+
+0801d588 <alt_flash_device_register>:
+
+typedef struct alt_flash_dev alt_flash_dev; 
+typedef alt_flash_dev alt_flash_fd;
+
+static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd)
+{
+ 801d588:	defffd04 	addi	sp,sp,-12
+ 801d58c:	dfc00215 	stw	ra,8(sp)
+ 801d590:	df000115 	stw	fp,4(sp)
+ 801d594:	df000104 	addi	fp,sp,4
+ 801d598:	e13fff15 	stw	r4,-4(fp)
+  extern alt_llist alt_flash_dev_list;
+
+  return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list);
+ 801d59c:	d1600404 	addi	r5,gp,-32752
+ 801d5a0:	e13fff17 	ldw	r4,-4(fp)
+ 801d5a4:	80372a00 	call	80372a0 <alt_dev_llist_insert>
+}
+ 801d5a8:	e037883a 	mov	sp,fp
+ 801d5ac:	dfc00117 	ldw	ra,4(sp)
+ 801d5b0:	df000017 	ldw	fp,0(sp)
+ 801d5b4:	dec00204 	addi	sp,sp,8
+ 801d5b8:	f800283a 	ret
+
+0801d5bc <alt_qspi_controller_lock>:
+  * -EINVAL -> Invalid arguments
+  * -ETIME  -> Time out and skipping the looping after 0.7 sec.
+  * -ENOLCK -> Sectors lock failed.
+**/
+int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
+{
+ 801d5bc:	defff804 	addi	sp,sp,-32
+ 801d5c0:	dfc00715 	stw	ra,28(sp)
+ 801d5c4:	df000615 	stw	fp,24(sp)
+ 801d5c8:	df000604 	addi	fp,sp,24
+ 801d5cc:	e13ffb15 	stw	r4,-20(fp)
+ 801d5d0:	e17ffa15 	stw	r5,-24(fp)
+    alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
+ 801d5d4:	e03fff15 	stw	zero,-4(fp)
+    alt_qspi_controller_dev* qspi_flash_info = NULL;
+ 801d5d8:	e03ffe15 	stw	zero,-8(fp)
+    alt_u32 result = 0;
+ 801d5dc:	e03ffd15 	stw	zero,-12(fp)
+    alt_32 status = 0;
+ 801d5e0:	e03ffc15 	stw	zero,-16(fp)
+
+    /* return -EINVAL if flash_info is NULL */
+    if(NULL == flash_info || 0 > sectors_to_lock)
+ 801d5e4:	e0bffb17 	ldw	r2,-20(fp)
+ 801d5e8:	1000021e 	bne	r2,zero,801d5f4 <alt_qspi_controller_lock+0x38>
+    {
+    	return -EINVAL;
+ 801d5ec:	00bffa84 	movi	r2,-22
+ 801d5f0:	00003106 	br	801d6b8 <alt_qspi_controller_lock+0xfc>
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801d5f4:	e0bffb17 	ldw	r2,-20(fp)
+ 801d5f8:	e0bffe15 	stw	r2,-8(fp)
+
+    /* sector value should occupy bits 17:8 */
+    mem_op_value = sectors_to_lock << 8;
+ 801d5fc:	e0bffa17 	ldw	r2,-24(fp)
+ 801d600:	1004923a 	slli	r2,r2,8
+ 801d604:	e0bfff15 	stw	r2,-4(fp)
+
+    /* sector protect commands 0b11 occupies lower 2 bits */
+    mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD;
+ 801d608:	e0bfff17 	ldw	r2,-4(fp)
+ 801d60c:	108000d4 	ori	r2,r2,3
+ 801d610:	e0bfff15 	stw	r2,-4(fp)
+
+    /* write sector protect command to QSPI_MEM_OP register to protect sectors */
+    IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value);
+ 801d614:	e0bffe17 	ldw	r2,-8(fp)
+ 801d618:	10803017 	ldw	r2,192(r2)
+ 801d61c:	10800304 	addi	r2,r2,12
+ 801d620:	1007883a 	mov	r3,r2
+ 801d624:	e0bfff17 	ldw	r2,-4(fp)
+ 801d628:	18800035 	stwio	r2,0(r3)
+    
+    /* poll write in progress to make sure no operation is in progress */
+    status = alt_qspi_poll_for_write_in_progress(qspi_flash_info);
+ 801d62c:	e13ffe17 	ldw	r4,-8(fp)
+ 801d630:	801e0100 	call	801e010 <alt_qspi_poll_for_write_in_progress>
+ 801d634:	e0bffc15 	stw	r2,-16(fp)
+    if(status != 0)
+ 801d638:	e0bffc17 	ldw	r2,-16(fp)
+ 801d63c:	10000226 	beq	r2,zero,801d648 <alt_qspi_controller_lock+0x8c>
+    {
+    	return status;
+ 801d640:	e0bffc17 	ldw	r2,-16(fp)
+ 801d644:	00001c06 	br	801d6b8 <alt_qspi_controller_lock+0xfc>
+    }
+	
+	status = IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base);
+ 801d648:	e0bffe17 	ldw	r2,-8(fp)
+ 801d64c:	10803017 	ldw	r2,192(r2)
+ 801d650:	10800037 	ldwio	r2,0(r2)
+ 801d654:	e0bffc15 	stw	r2,-16(fp)
+	result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */
+ 801d658:	e0bffc17 	ldw	r2,-16(fp)
+ 801d65c:	1005d0ba 	srai	r2,r2,2
+ 801d660:	108001cc 	andi	r2,r2,7
+ 801d664:	e0fffd17 	ldw	r3,-12(fp)
+ 801d668:	1884b03a 	or	r2,r3,r2
+ 801d66c:	e0bffd15 	stw	r2,-12(fp)
+	result |= (status >> 3) & 0x08; /* extract out BP4 */
+ 801d670:	e0bffc17 	ldw	r2,-16(fp)
+ 801d674:	1005d0fa 	srai	r2,r2,3
+ 801d678:	1080020c 	andi	r2,r2,8
+ 801d67c:	e0fffd17 	ldw	r3,-12(fp)
+ 801d680:	1884b03a 	or	r2,r3,r2
+ 801d684:	e0bffd15 	stw	r2,-12(fp)
+    result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */
+ 801d688:	e0bffc17 	ldw	r2,-16(fp)
+ 801d68c:	1005d07a 	srai	r2,r2,1
+ 801d690:	1080040c 	andi	r2,r2,16
+ 801d694:	e0fffd17 	ldw	r3,-12(fp)
+ 801d698:	1884b03a 	or	r2,r3,r2
+ 801d69c:	e0bffd15 	stw	r2,-12(fp)
+
+	if(result != sectors_to_lock)
+ 801d6a0:	e0fffd17 	ldw	r3,-12(fp)
+ 801d6a4:	e0bffa17 	ldw	r2,-24(fp)
+ 801d6a8:	18800226 	beq	r3,r2,801d6b4 <alt_qspi_controller_lock+0xf8>
+	{
+		return -ENOLCK;
+ 801d6ac:	00bff484 	movi	r2,-46
+ 801d6b0:	00000106 	br	801d6b8 <alt_qspi_controller_lock+0xfc>
+	}
+
+    return 0;
+ 801d6b4:	0005883a 	mov	r2,zero
+}
+ 801d6b8:	e037883a 	mov	sp,fp
+ 801d6bc:	dfc00117 	ldw	ra,4(sp)
+ 801d6c0:	df000017 	ldw	fp,0(sp)
+ 801d6c4:	dec00204 	addi	sp,sp,8
+ 801d6c8:	f800283a 	ret
+
+0801d6cc <alt_qspi_controller_get_info>:
+(
+    alt_flash_fd *fd, /** flash device descriptor */
+    flash_region **info, /** pointer to flash_region will be stored here */
+    int *number_of_regions /** number of regions will be stored here */
+)
+{
+ 801d6cc:	defffb04 	addi	sp,sp,-20
+ 801d6d0:	df000415 	stw	fp,16(sp)
+ 801d6d4:	df000404 	addi	fp,sp,16
+ 801d6d8:	e13ffe15 	stw	r4,-8(fp)
+ 801d6dc:	e17ffd15 	stw	r5,-12(fp)
+ 801d6e0:	e1bffc15 	stw	r6,-16(fp)
+	alt_flash_dev* flash = NULL;
+ 801d6e4:	e03fff15 	stw	zero,-4(fp)
+	
+	/* return -EINVAL if fd,info and number_of_regions are NULL */
+	if(NULL == fd || NULL == info || NULL == number_of_regions)
+ 801d6e8:	e0bffe17 	ldw	r2,-8(fp)
+ 801d6ec:	10000426 	beq	r2,zero,801d700 <alt_qspi_controller_get_info+0x34>
+ 801d6f0:	e0bffd17 	ldw	r2,-12(fp)
+ 801d6f4:	10000226 	beq	r2,zero,801d700 <alt_qspi_controller_get_info+0x34>
+ 801d6f8:	e0bffc17 	ldw	r2,-16(fp)
+ 801d6fc:	1000021e 	bne	r2,zero,801d708 <alt_qspi_controller_get_info+0x3c>
+    {
+    	return -EINVAL;
+ 801d700:	00bffa84 	movi	r2,-22
+ 801d704:	00001006 	br	801d748 <alt_qspi_controller_get_info+0x7c>
+    }
+
+    flash = (alt_flash_dev*)fd;
+ 801d708:	e0bffe17 	ldw	r2,-8(fp)
+ 801d70c:	e0bfff15 	stw	r2,-4(fp)
+
+    *number_of_regions = flash->number_of_regions;
+ 801d710:	e0bfff17 	ldw	r2,-4(fp)
+ 801d714:	10c00c17 	ldw	r3,48(r2)
+ 801d718:	e0bffc17 	ldw	r2,-16(fp)
+ 801d71c:	10c00015 	stw	r3,0(r2)
+
+    if (!flash->number_of_regions)
+ 801d720:	e0bfff17 	ldw	r2,-4(fp)
+ 801d724:	10800c17 	ldw	r2,48(r2)
+ 801d728:	1000021e 	bne	r2,zero,801d734 <alt_qspi_controller_get_info+0x68>
+    {
+      return -EIO;
+ 801d72c:	00bffec4 	movi	r2,-5
+ 801d730:	00000506 	br	801d748 <alt_qspi_controller_get_info+0x7c>
+    }
+    else
+    {
+      *info = &flash->region_info[0];
+ 801d734:	e0bfff17 	ldw	r2,-4(fp)
+ 801d738:	10c00d04 	addi	r3,r2,52
+ 801d73c:	e0bffd17 	ldw	r2,-12(fp)
+ 801d740:	10c00015 	stw	r3,0(r2)
+    }
+
+    return 0;
+ 801d744:	0005883a 	mov	r2,zero
+}
+ 801d748:	e037883a 	mov	sp,fp
+ 801d74c:	df000017 	ldw	fp,0(sp)
+ 801d750:	dec00104 	addi	sp,sp,4
+ 801d754:	f800283a 	ret
+
+0801d758 <alt_qspi_controller_erase_block>:
+  * 0 -> success
+  * -EINVAL -> Invalid arguments
+  * -EIO -> write failed, sector might be protected 
+**/
+int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset)
+{
+ 801d758:	defff804 	addi	sp,sp,-32
+ 801d75c:	dfc00715 	stw	ra,28(sp)
+ 801d760:	df000615 	stw	fp,24(sp)
+ 801d764:	df000604 	addi	fp,sp,24
+ 801d768:	e13ffb15 	stw	r4,-20(fp)
+ 801d76c:	e17ffa15 	stw	r5,-24(fp)
+    alt_32 ret_code = 0;
+ 801d770:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
+ 801d774:	e03ffe15 	stw	zero,-8(fp)
+    alt_qspi_controller_dev* qspi_flash_info = NULL;
+ 801d778:	e03ffd15 	stw	zero,-12(fp)
+    alt_u32 sector_number = 0; 
+ 801d77c:	e03ffc15 	stw	zero,-16(fp)
+
+    /* return -EINVAL if flash_info is NULL */
+    if(NULL == flash_info)
+ 801d780:	e0bffb17 	ldw	r2,-20(fp)
+ 801d784:	1000021e 	bne	r2,zero,801d790 <alt_qspi_controller_erase_block+0x38>
+    {
+    	return -EINVAL;
+ 801d788:	00bffa84 	movi	r2,-22
+ 801d78c:	00003606 	br	801d868 <alt_qspi_controller_erase_block+0x110>
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801d790:	e0bffb17 	ldw	r2,-20(fp)
+ 801d794:	e0bffd15 	stw	r2,-12(fp)
+    /* 
+     * Sanity checks that block_offset is within the flash memory span and that the 
+     * block offset is sector aligned.
+     *
+     */
+    if((block_offset < 0) 
+ 801d798:	e0bffa17 	ldw	r2,-24(fp)
+ 801d79c:	10000a16 	blt	r2,zero,801d7c8 <alt_qspi_controller_erase_block+0x70>
+        || (block_offset >= qspi_flash_info->size_in_bytes)
+ 801d7a0:	e0bffd17 	ldw	r2,-12(fp)
+ 801d7a4:	10803117 	ldw	r2,196(r2)
+ 801d7a8:	e0fffa17 	ldw	r3,-24(fp)
+ 801d7ac:	1880062e 	bgeu	r3,r2,801d7c8 <alt_qspi_controller_erase_block+0x70>
+        || (block_offset & (qspi_flash_info->sector_size - 1)) != 0)
+ 801d7b0:	e0bffd17 	ldw	r2,-12(fp)
+ 801d7b4:	10803417 	ldw	r2,208(r2)
+ 801d7b8:	10ffffc4 	addi	r3,r2,-1
+ 801d7bc:	e0bffa17 	ldw	r2,-24(fp)
+ 801d7c0:	1884703a 	and	r2,r3,r2
+ 801d7c4:	10000226 	beq	r2,zero,801d7d0 <alt_qspi_controller_erase_block+0x78>
+    {
+    	return -EINVAL;
+ 801d7c8:	00bffa84 	movi	r2,-22
+ 801d7cc:	00002606 	br	801d868 <alt_qspi_controller_erase_block+0x110>
+    }
+
+    /* calculate current sector/block number */
+    sector_number = (block_offset/(qspi_flash_info->sector_size));
+ 801d7d0:	e0fffa17 	ldw	r3,-24(fp)
+ 801d7d4:	e0bffd17 	ldw	r2,-12(fp)
+ 801d7d8:	10803417 	ldw	r2,208(r2)
+ 801d7dc:	100b883a 	mov	r5,r2
+ 801d7e0:	1809883a 	mov	r4,r3
+ 801d7e4:	800cff80 	call	800cff8 <__udivsi3>
+ 801d7e8:	e0bffc15 	stw	r2,-16(fp)
+
+    /* sector value should occupy bits 23:8 */
+    mem_op_value = (sector_number << 8) & ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK;
+ 801d7ec:	e0bffc17 	ldw	r2,-16(fp)
+ 801d7f0:	1006923a 	slli	r3,r2,8
+ 801d7f4:	00804034 	movhi	r2,256
+ 801d7f8:	10bfc004 	addi	r2,r2,-256
+ 801d7fc:	1884703a 	and	r2,r3,r2
+ 801d800:	e0bffe15 	stw	r2,-8(fp)
+
+    /* sector erase commands 0b10 occupies lower 2 bits */
+    mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD;
+ 801d804:	e0bffe17 	ldw	r2,-8(fp)
+ 801d808:	10800094 	ori	r2,r2,2
+ 801d80c:	e0bffe15 	stw	r2,-8(fp)
+
+    /* write sector erase command to QSPI_MEM_OP register to erase sector "sector_number" */
+    IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value);
+ 801d810:	e0bffd17 	ldw	r2,-12(fp)
+ 801d814:	10803017 	ldw	r2,192(r2)
+ 801d818:	10800304 	addi	r2,r2,12
+ 801d81c:	1007883a 	mov	r3,r2
+ 801d820:	e0bffe17 	ldw	r2,-8(fp)
+ 801d824:	18800035 	stwio	r2,0(r3)
+	
+    /* check whether erase triggered a illegal erase interrupt  */
+    if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) &
+ 801d828:	e0bffd17 	ldw	r2,-12(fp)
+ 801d82c:	10803017 	ldw	r2,192(r2)
+ 801d830:	10800404 	addi	r2,r2,16
+ 801d834:	10800037 	ldwio	r2,0(r2)
+ 801d838:	1080004c 	andi	r2,r2,1
+ 801d83c:	10800058 	cmpnei	r2,r2,1
+ 801d840:	1000081e 	bne	r2,zero,801d864 <alt_qspi_controller_erase_block+0x10c>
+            		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK) ==
+            				ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE)
+    {
+	    /* clear register */
+	    /* QSPI_ISR access is write one to clear (W1C) */
+    	IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base,
+ 801d844:	e0bffd17 	ldw	r2,-12(fp)
+ 801d848:	10803017 	ldw	r2,192(r2)
+ 801d84c:	10800404 	addi	r2,r2,16
+ 801d850:	1007883a 	mov	r3,r2
+ 801d854:	00800044 	movi	r2,1
+ 801d858:	18800035 	stwio	r2,0(r3)
+    		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK );
+    	return -EIO; /* erase failed, sector might be protected */
+ 801d85c:	00bffec4 	movi	r2,-5
+ 801d860:	00000106 	br	801d868 <alt_qspi_controller_erase_block+0x110>
+    }
+
+    return ret_code;
+ 801d864:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801d868:	e037883a 	mov	sp,fp
+ 801d86c:	dfc00117 	ldw	ra,4(sp)
+ 801d870:	df000017 	ldw	fp,0(sp)
+ 801d874:	dec00204 	addi	sp,sp,8
+ 801d878:	f800283a 	ret
+
+0801d87c <alt_qspi_controller_write_block>:
+    int block_offset, /** sector/block offset in byte addressing */
+    int data_offset, /** offset of write from base address */
+    const void *data, /** data to be written */
+    int length /** bytes of data to be written, >0 */
+)
+{
+ 801d87c:	defff304 	addi	sp,sp,-52
+ 801d880:	dfc00c15 	stw	ra,48(sp)
+ 801d884:	df000b15 	stw	fp,44(sp)
+ 801d888:	df000b04 	addi	fp,sp,44
+ 801d88c:	e13ff815 	stw	r4,-32(fp)
+ 801d890:	e17ff715 	stw	r5,-36(fp)
+ 801d894:	e1bff615 	stw	r6,-40(fp)
+ 801d898:	e1fff515 	stw	r7,-44(fp)
+    alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */
+ 801d89c:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 remaining_length = length; /** length left to write */
+ 801d8a0:	e0800217 	ldw	r2,8(fp)
+ 801d8a4:	e0bffe15 	stw	r2,-8(fp)
+    alt_u32 write_offset = data_offset; /** offset into flash to write too */
+ 801d8a8:	e0bff617 	ldw	r2,-40(fp)
+ 801d8ac:	e0bffd15 	stw	r2,-12(fp)
+
+    alt_qspi_controller_dev *qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801d8b0:	e0bff817 	ldw	r2,-32(fp)
+ 801d8b4:	e0bffa15 	stw	r2,-24(fp)
+    /* 
+     * Sanity checks that data offset is not larger then a sector, that block offset is 
+     * sector aligned and within the valid flash memory range and a write doesn't spill into 
+     * the adjacent flash sector.
+     */
+    if(block_offset < 0
+ 801d8b8:	e0bff717 	ldw	r2,-36(fp)
+ 801d8bc:	10001e16 	blt	r2,zero,801d938 <alt_qspi_controller_write_block+0xbc>
+        || data_offset < 0
+ 801d8c0:	e0bff617 	ldw	r2,-40(fp)
+ 801d8c4:	10001c16 	blt	r2,zero,801d938 <alt_qspi_controller_write_block+0xbc>
+        || NULL == flash_info
+ 801d8c8:	e0bff817 	ldw	r2,-32(fp)
+ 801d8cc:	10001a26 	beq	r2,zero,801d938 <alt_qspi_controller_write_block+0xbc>
+        || NULL == data
+ 801d8d0:	e0bff517 	ldw	r2,-44(fp)
+ 801d8d4:	10001826 	beq	r2,zero,801d938 <alt_qspi_controller_write_block+0xbc>
+        || data_offset >= qspi_flash_info->size_in_bytes
+ 801d8d8:	e0bffa17 	ldw	r2,-24(fp)
+ 801d8dc:	10803117 	ldw	r2,196(r2)
+ 801d8e0:	e0fff617 	ldw	r3,-40(fp)
+ 801d8e4:	1880142e 	bgeu	r3,r2,801d938 <alt_qspi_controller_write_block+0xbc>
+        || block_offset >= qspi_flash_info->size_in_bytes
+ 801d8e8:	e0bffa17 	ldw	r2,-24(fp)
+ 801d8ec:	10803117 	ldw	r2,196(r2)
+ 801d8f0:	e0fff717 	ldw	r3,-36(fp)
+ 801d8f4:	1880102e 	bgeu	r3,r2,801d938 <alt_qspi_controller_write_block+0xbc>
+        || length > (qspi_flash_info->sector_size - (data_offset - block_offset))
+ 801d8f8:	e0bffa17 	ldw	r2,-24(fp)
+ 801d8fc:	10803417 	ldw	r2,208(r2)
+ 801d900:	e13ff617 	ldw	r4,-40(fp)
+ 801d904:	e0fff717 	ldw	r3,-36(fp)
+ 801d908:	20c7c83a 	sub	r3,r4,r3
+ 801d90c:	10c7c83a 	sub	r3,r2,r3
+ 801d910:	e0800217 	ldw	r2,8(fp)
+ 801d914:	18800836 	bltu	r3,r2,801d938 <alt_qspi_controller_write_block+0xbc>
+        || length < 0
+ 801d918:	e0800217 	ldw	r2,8(fp)
+ 801d91c:	10000616 	blt	r2,zero,801d938 <alt_qspi_controller_write_block+0xbc>
+        || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) 
+ 801d920:	e0bffa17 	ldw	r2,-24(fp)
+ 801d924:	10803417 	ldw	r2,208(r2)
+ 801d928:	10ffffc4 	addi	r3,r2,-1
+ 801d92c:	e0bff717 	ldw	r2,-36(fp)
+ 801d930:	1884703a 	and	r2,r3,r2
+ 801d934:	10004d26 	beq	r2,zero,801da6c <alt_qspi_controller_write_block+0x1f0>
+    {
+    	return -EINVAL;
+ 801d938:	00bffa84 	movi	r2,-22
+ 801d93c:	00004e06 	br	801da78 <alt_qspi_controller_write_block+0x1fc>
+     * We need to make sure that we pad the first few bytes so they're word aligned if they are
+     * not already.
+     */
+    while (remaining_length > 0)
+    {
+    	alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
+ 801d940:	00bfffc4 	movi	r2,-1
+ 801d944:	e0bff915 	stw	r2,-28(fp)
+    	alt_u32 padding = 0; /** bytes to pad the next word that is written */
+ 801d948:	e03ffc15 	stw	zero,-16(fp)
+    	alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
+ 801d94c:	00800104 	movi	r2,4
+ 801d950:	e0bffb15 	stw	r2,-20(fp)
+
+        /*
+         * we need to make sure the write is word aligned
+    	 * this should only be true at most 1 time
+    	 */
+        if (0 != (write_offset & (sizeof(alt_u32) - 1)))
+ 801d954:	e0bffd17 	ldw	r2,-12(fp)
+ 801d958:	108000cc 	andi	r2,r2,3
+ 801d95c:	10001526 	beq	r2,zero,801d9b4 <alt_qspi_controller_write_block+0x138>
+        {
+        	/*
+        	 * data is not word aligned
+        	 * calculate padding bytes need to add before start of a data offset
+        	 */
+            padding = write_offset & (sizeof(alt_u32) - 1);
+ 801d960:	e0bffd17 	ldw	r2,-12(fp)
+ 801d964:	108000cc 	andi	r2,r2,3
+ 801d968:	e0bffc15 	stw	r2,-16(fp)
+
+            /* update variables to account for padding being added */
+            bytes_to_copy -= padding;
+ 801d96c:	e0fffb17 	ldw	r3,-20(fp)
+ 801d970:	e0bffc17 	ldw	r2,-16(fp)
+ 801d974:	1885c83a 	sub	r2,r3,r2
+ 801d978:	e0bffb15 	stw	r2,-20(fp)
+
+            if(bytes_to_copy > remaining_length)
+ 801d97c:	e0bffb17 	ldw	r2,-20(fp)
+ 801d980:	e0fffe17 	ldw	r3,-8(fp)
+ 801d984:	1880022e 	bgeu	r3,r2,801d990 <alt_qspi_controller_write_block+0x114>
+            {
+            	bytes_to_copy = remaining_length;
+ 801d988:	e0bffe17 	ldw	r2,-8(fp)
+ 801d98c:	e0bffb15 	stw	r2,-20(fp)
+            }
+
+            write_offset = write_offset - padding;
+ 801d990:	e0fffd17 	ldw	r3,-12(fp)
+ 801d994:	e0bffc17 	ldw	r2,-16(fp)
+ 801d998:	1885c83a 	sub	r2,r3,r2
+ 801d99c:	e0bffd15 	stw	r2,-12(fp)
+            if(0 != (write_offset & (sizeof(alt_u32) - 1)))
+ 801d9a0:	e0bffd17 	ldw	r2,-12(fp)
+ 801d9a4:	108000cc 	andi	r2,r2,3
+ 801d9a8:	10000726 	beq	r2,zero,801d9c8 <alt_qspi_controller_write_block+0x14c>
+            {
+            	return -EINVAL;
+ 801d9ac:	00bffa84 	movi	r2,-22
+ 801d9b0:	00003106 	br	801da78 <alt_qspi_controller_write_block+0x1fc>
+            }
+        }
+        else
+        {
+            if(bytes_to_copy > remaining_length)
+ 801d9b4:	e0bffb17 	ldw	r2,-20(fp)
+ 801d9b8:	e0fffe17 	ldw	r3,-8(fp)
+ 801d9bc:	1880022e 	bgeu	r3,r2,801d9c8 <alt_qspi_controller_write_block+0x14c>
+            {
+            	bytes_to_copy = remaining_length;
+ 801d9c0:	e0bffe17 	ldw	r2,-8(fp)
+ 801d9c4:	e0bffb15 	stw	r2,-20(fp)
+            }
+        }
+
+        /* prepare the word to be written */
+        memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy);
+ 801d9c8:	e0fff904 	addi	r3,fp,-28
+ 801d9cc:	e0bffc17 	ldw	r2,-16(fp)
+ 801d9d0:	1889883a 	add	r4,r3,r2
+ 801d9d4:	e0fff517 	ldw	r3,-44(fp)
+ 801d9d8:	e0bfff17 	ldw	r2,-4(fp)
+ 801d9dc:	1885883a 	add	r2,r3,r2
+ 801d9e0:	e1bffb17 	ldw	r6,-20(fp)
+ 801d9e4:	100b883a 	mov	r5,r2
+ 801d9e8:	80086b80 	call	80086b8 <memcpy>
+
+        /* update offset and length variables */
+        buffer_offset += bytes_to_copy;
+ 801d9ec:	e0ffff17 	ldw	r3,-4(fp)
+ 801d9f0:	e0bffb17 	ldw	r2,-20(fp)
+ 801d9f4:	1885883a 	add	r2,r3,r2
+ 801d9f8:	e0bfff15 	stw	r2,-4(fp)
+        remaining_length -= bytes_to_copy;
+ 801d9fc:	e0fffe17 	ldw	r3,-8(fp)
+ 801da00:	e0bffb17 	ldw	r2,-20(fp)
+ 801da04:	1885c83a 	sub	r2,r3,r2
+ 801da08:	e0bffe15 	stw	r2,-8(fp)
+
+        /* write to flash 32 bits at a time */
+        IOWR_32DIRECT(qspi_flash_info->data_base, write_offset, word_to_write);
+ 801da0c:	e0bffa17 	ldw	r2,-24(fp)
+ 801da10:	10c02e17 	ldw	r3,184(r2)
+ 801da14:	e0bffd17 	ldw	r2,-12(fp)
+ 801da18:	1885883a 	add	r2,r3,r2
+ 801da1c:	e0fff917 	ldw	r3,-28(fp)
+ 801da20:	10c00035 	stwio	r3,0(r2)
+
+        /* check whether write triggered a illegal write interrupt */
+        if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) &
+ 801da24:	e0bffa17 	ldw	r2,-24(fp)
+ 801da28:	10803017 	ldw	r2,192(r2)
+ 801da2c:	10800404 	addi	r2,r2,16
+ 801da30:	10800037 	ldwio	r2,0(r2)
+ 801da34:	1080008c 	andi	r2,r2,2
+ 801da38:	10800098 	cmpnei	r2,r2,2
+ 801da3c:	1000081e 	bne	r2,zero,801da60 <alt_qspi_controller_write_block+0x1e4>
+        		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) ==
+        				ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE)
+        {
+		    /* clear register */
+        	IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base,
+ 801da40:	e0bffa17 	ldw	r2,-24(fp)
+ 801da44:	10803017 	ldw	r2,192(r2)
+ 801da48:	10800404 	addi	r2,r2,16
+ 801da4c:	1007883a 	mov	r3,r2
+ 801da50:	00800084 	movi	r2,2
+ 801da54:	18800035 	stwio	r2,0(r3)
+			ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK );
+        	return -EIO; /** write failed, sector might be protected */
+ 801da58:	00bffec4 	movi	r2,-5
+ 801da5c:	00000606 	br	801da78 <alt_qspi_controller_write_block+0x1fc>
+        }
+
+        /* update current offset */
+        write_offset = write_offset + sizeof(alt_u32);
+ 801da60:	e0bffd17 	ldw	r2,-12(fp)
+ 801da64:	10800104 	addi	r2,r2,4
+ 801da68:	e0bffd15 	stw	r2,-12(fp)
+    while (remaining_length > 0)
+ 801da6c:	e0bffe17 	ldw	r2,-8(fp)
+ 801da70:	103fb31e 	bne	r2,zero,801d940 <alt_qspi_controller_write_block+0xc4>
+    }
+
+    return 0;
+ 801da74:	0005883a 	mov	r2,zero
+}
+ 801da78:	e037883a 	mov	sp,fp
+ 801da7c:	dfc00117 	ldw	ra,4(sp)
+ 801da80:	df000017 	ldw	fp,0(sp)
+ 801da84:	dec00204 	addi	sp,sp,8
+ 801da88:	f800283a 	ret
+
+0801da8c <alt_qspi_controller_write>:
+    alt_flash_dev *flash_info, /** device info */
+    int offset, /** offset of write from base address */
+    const void *src_addr, /** source buffer */
+    int length /** size of writing */
+)
+{
+ 801da8c:	defff004 	addi	sp,sp,-64
+ 801da90:	dfc00f15 	stw	ra,60(sp)
+ 801da94:	df000e15 	stw	fp,56(sp)
+ 801da98:	df000e04 	addi	fp,sp,56
+ 801da9c:	e13ff615 	stw	r4,-40(fp)
+ 801daa0:	e17ff515 	stw	r5,-44(fp)
+ 801daa4:	e1bff415 	stw	r6,-48(fp)
+ 801daa8:	e1fff315 	stw	r7,-52(fp)
+    alt_32 ret_code = 0;
+ 801daac:	e03fff15 	stw	zero,-4(fp)
+
+    alt_qspi_controller_dev *qspi_flash_info = NULL;
+ 801dab0:	e03ff915 	stw	zero,-28(fp)
+
+    alt_u32 write_offset = offset; /** address of next byte to write */
+ 801dab4:	e0bff517 	ldw	r2,-44(fp)
+ 801dab8:	e0bffe15 	stw	r2,-8(fp)
+    alt_u32 remaining_length = length; /** length of write data left to be written */
+ 801dabc:	e0bff317 	ldw	r2,-52(fp)
+ 801dac0:	e0bffd15 	stw	r2,-12(fp)
+    alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */
+ 801dac4:	e03ffc15 	stw	zero,-16(fp)
+    alt_u32 i = 0;
+ 801dac8:	e03ffb15 	stw	zero,-20(fp)
+
+    /* return -EINVAL if flash_info and src_addr are NULL */
+	if(NULL == flash_info || NULL == src_addr)
+ 801dacc:	e0bff617 	ldw	r2,-40(fp)
+ 801dad0:	10000226 	beq	r2,zero,801dadc <alt_qspi_controller_write+0x50>
+ 801dad4:	e0bff417 	ldw	r2,-48(fp)
+ 801dad8:	1000021e 	bne	r2,zero,801dae4 <alt_qspi_controller_write+0x58>
+    {
+    	return -EINVAL;
+ 801dadc:	00bffa84 	movi	r2,-22
+ 801dae0:	00005f06 	br	801dc60 <alt_qspi_controller_write+0x1d4>
+    }
+	
+	qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801dae4:	e0bff617 	ldw	r2,-40(fp)
+ 801dae8:	e0bff915 	stw	r2,-28(fp)
+	
+    /* make sure the write parameters are within the bounds of the flash */
+    ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length);
+ 801daec:	e0bff517 	ldw	r2,-44(fp)
+ 801daf0:	e0fff317 	ldw	r3,-52(fp)
+ 801daf4:	180d883a 	mov	r6,r3
+ 801daf8:	100b883a 	mov	r5,r2
+ 801dafc:	e13ff917 	ldw	r4,-28(fp)
+ 801db00:	801df740 	call	801df74 <alt_qspi_validate_read_write_arguments>
+ 801db04:	e0bfff15 	stw	r2,-4(fp)
+
+	if(0 != ret_code)
+ 801db08:	e0bfff17 	ldw	r2,-4(fp)
+ 801db0c:	10000226 	beq	r2,zero,801db18 <alt_qspi_controller_write+0x8c>
+	{
+		return ret_code;
+ 801db10:	e0bfff17 	ldw	r2,-4(fp)
+ 801db14:	00005206 	br	801dc60 <alt_qspi_controller_write+0x1d4>
+
+    /*
+     * This loop erases and writes data one sector at a time. We check for write completion 
+     * before starting the next sector.
+     */
+    for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++)
+ 801db18:	e0fff517 	ldw	r3,-44(fp)
+ 801db1c:	e0bff917 	ldw	r2,-28(fp)
+ 801db20:	10803417 	ldw	r2,208(r2)
+ 801db24:	100b883a 	mov	r5,r2
+ 801db28:	1809883a 	mov	r4,r3
+ 801db2c:	800cff80 	call	800cff8 <__udivsi3>
+ 801db30:	e0bffb15 	stw	r2,-20(fp)
+ 801db34:	00004306 	br	801dc44 <alt_qspi_controller_write+0x1b8>
+    {
+        alt_u32 block_offset = 0; /** block offset in byte addressing */
+ 801db38:	e03ff815 	stw	zero,-32(fp)
+    	alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */
+ 801db3c:	e03ffa15 	stw	zero,-24(fp)
+        alt_u32 length_to_write = 0; /** length to write to current sector */
+ 801db40:	e03ff715 	stw	zero,-36(fp)
+
+    	if(0 >= remaining_length)
+ 801db44:	e0bffd17 	ldw	r2,-12(fp)
+ 801db48:	10004326 	beq	r2,zero,801dc58 <alt_qspi_controller_write+0x1cc>
+    	{
+    		break; /* out of data to write */
+    	}
+
+        /* calculate current sector/block offset in byte addressing */
+        block_offset = write_offset & ~(qspi_flash_info->sector_size - 1);
+ 801db4c:	e0bff917 	ldw	r2,-28(fp)
+ 801db50:	10803417 	ldw	r2,208(r2)
+ 801db54:	0085c83a 	sub	r2,zero,r2
+ 801db58:	e0fffe17 	ldw	r3,-8(fp)
+ 801db5c:	1884703a 	and	r2,r3,r2
+ 801db60:	e0bff815 	stw	r2,-32(fp)
+           
+        /* calculate offset into sector/block if there is one */
+        if(block_offset != write_offset)
+ 801db64:	e0fff817 	ldw	r3,-32(fp)
+ 801db68:	e0bffe17 	ldw	r2,-8(fp)
+ 801db6c:	18800426 	beq	r3,r2,801db80 <alt_qspi_controller_write+0xf4>
+        {
+            offset_within_current_sector = write_offset - block_offset;
+ 801db70:	e0fffe17 	ldw	r3,-8(fp)
+ 801db74:	e0bff817 	ldw	r2,-32(fp)
+ 801db78:	1885c83a 	sub	r2,r3,r2
+ 801db7c:	e0bffa15 	stw	r2,-24(fp)
+        }
+
+        /* erase sector */
+        ret_code = alt_qspi_controller_erase_block(flash_info, block_offset);
+ 801db80:	e0bff817 	ldw	r2,-32(fp)
+ 801db84:	100b883a 	mov	r5,r2
+ 801db88:	e13ff617 	ldw	r4,-40(fp)
+ 801db8c:	801d7580 	call	801d758 <alt_qspi_controller_erase_block>
+ 801db90:	e0bfff15 	stw	r2,-4(fp)
+
+        if(0 != ret_code)
+ 801db94:	e0bfff17 	ldw	r2,-4(fp)
+ 801db98:	10000226 	beq	r2,zero,801dba4 <alt_qspi_controller_write+0x118>
+        {
+            return ret_code;
+ 801db9c:	e0bfff17 	ldw	r2,-4(fp)
+ 801dba0:	00002f06 	br	801dc60 <alt_qspi_controller_write+0x1d4>
+        }
+
+        /* calculate the byte size of data to be written in a sector */
+        length_to_write = MIN(qspi_flash_info->sector_size - offset_within_current_sector, 
+ 801dba4:	e0bff917 	ldw	r2,-28(fp)
+ 801dba8:	10c03417 	ldw	r3,208(r2)
+ 801dbac:	e0bffa17 	ldw	r2,-24(fp)
+ 801dbb0:	1887c83a 	sub	r3,r3,r2
+ 801dbb4:	e0bffd17 	ldw	r2,-12(fp)
+ 801dbb8:	1880012e 	bgeu	r3,r2,801dbc0 <alt_qspi_controller_write+0x134>
+ 801dbbc:	1805883a 	mov	r2,r3
+ 801dbc0:	e0bff715 	stw	r2,-36(fp)
+                remaining_length);
+
+        /* write data to erased block */
+        ret_code = alt_qspi_controller_write_block(flash_info, block_offset, write_offset,
+ 801dbc4:	e13ff817 	ldw	r4,-32(fp)
+ 801dbc8:	e17ffe17 	ldw	r5,-8(fp)
+ 801dbcc:	e0fff417 	ldw	r3,-48(fp)
+ 801dbd0:	e0bffc17 	ldw	r2,-16(fp)
+ 801dbd4:	1887883a 	add	r3,r3,r2
+ 801dbd8:	e0bff717 	ldw	r2,-36(fp)
+ 801dbdc:	d8800015 	stw	r2,0(sp)
+ 801dbe0:	180f883a 	mov	r7,r3
+ 801dbe4:	280d883a 	mov	r6,r5
+ 801dbe8:	200b883a 	mov	r5,r4
+ 801dbec:	e13ff617 	ldw	r4,-40(fp)
+ 801dbf0:	801d87c0 	call	801d87c <alt_qspi_controller_write_block>
+ 801dbf4:	e0bfff15 	stw	r2,-4(fp)
+            src_addr + buffer_offset, length_to_write);
+
+
+        if(0 != ret_code)
+ 801dbf8:	e0bfff17 	ldw	r2,-4(fp)
+ 801dbfc:	10000226 	beq	r2,zero,801dc08 <alt_qspi_controller_write+0x17c>
+        {
+            return ret_code;
+ 801dc00:	e0bfff17 	ldw	r2,-4(fp)
+ 801dc04:	00001606 	br	801dc60 <alt_qspi_controller_write+0x1d4>
+        }
+
+        /* update remaining length and buffer_offset pointer */
+        remaining_length -= length_to_write;
+ 801dc08:	e0fffd17 	ldw	r3,-12(fp)
+ 801dc0c:	e0bff717 	ldw	r2,-36(fp)
+ 801dc10:	1885c83a 	sub	r2,r3,r2
+ 801dc14:	e0bffd15 	stw	r2,-12(fp)
+        buffer_offset += length_to_write;
+ 801dc18:	e0fffc17 	ldw	r3,-16(fp)
+ 801dc1c:	e0bff717 	ldw	r2,-36(fp)
+ 801dc20:	1885883a 	add	r2,r3,r2
+ 801dc24:	e0bffc15 	stw	r2,-16(fp)
+        write_offset += length_to_write; 
+ 801dc28:	e0fffe17 	ldw	r3,-8(fp)
+ 801dc2c:	e0bff717 	ldw	r2,-36(fp)
+ 801dc30:	1885883a 	add	r2,r3,r2
+ 801dc34:	e0bffe15 	stw	r2,-8(fp)
+    for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++)
+ 801dc38:	e0bffb17 	ldw	r2,-20(fp)
+ 801dc3c:	10800044 	addi	r2,r2,1
+ 801dc40:	e0bffb15 	stw	r2,-20(fp)
+ 801dc44:	e0bff917 	ldw	r2,-28(fp)
+ 801dc48:	10803317 	ldw	r2,204(r2)
+ 801dc4c:	e0fffb17 	ldw	r3,-20(fp)
+ 801dc50:	18bfb936 	bltu	r3,r2,801db38 <alt_qspi_controller_write+0xac>
+ 801dc54:	00000106 	br	801dc5c <alt_qspi_controller_write+0x1d0>
+    		break; /* out of data to write */
+ 801dc58:	0001883a 	nop
+    }
+
+    return ret_code;
+ 801dc5c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801dc60:	e037883a 	mov	sp,fp
+ 801dc64:	dfc00117 	ldw	ra,4(sp)
+ 801dc68:	df000017 	ldw	fp,0(sp)
+ 801dc6c:	dec00204 	addi	sp,sp,8
+ 801dc70:	f800283a 	ret
+
+0801dc74 <alt_qspi_controller_read>:
+    alt_flash_dev *flash_info, /** device info */
+    int offset, /** offset of read from base address */
+    void *dest_addr, /** destination buffer */
+    int length /** size of read */
+)
+{
+ 801dc74:	defff804 	addi	sp,sp,-32
+ 801dc78:	dfc00715 	stw	ra,28(sp)
+ 801dc7c:	df000615 	stw	fp,24(sp)
+ 801dc80:	df000604 	addi	fp,sp,24
+ 801dc84:	e13ffd15 	stw	r4,-12(fp)
+ 801dc88:	e17ffc15 	stw	r5,-16(fp)
+ 801dc8c:	e1bffb15 	stw	r6,-20(fp)
+ 801dc90:	e1fffa15 	stw	r7,-24(fp)
+    alt_32 ret_code = 0;
+ 801dc94:	e03fff15 	stw	zero,-4(fp)
+	alt_qspi_controller_dev *qspi_flash_info = NULL;
+ 801dc98:	e03ffe15 	stw	zero,-8(fp)
+	
+	/* return -EINVAL if flash_info and dest_addr are NULL */
+	if(NULL == flash_info || NULL == dest_addr)
+ 801dc9c:	e0bffd17 	ldw	r2,-12(fp)
+ 801dca0:	10000226 	beq	r2,zero,801dcac <alt_qspi_controller_read+0x38>
+ 801dca4:	e0bffb17 	ldw	r2,-20(fp)
+ 801dca8:	1000021e 	bne	r2,zero,801dcb4 <alt_qspi_controller_read+0x40>
+    {
+    	return -EINVAL;
+ 801dcac:	00bffa84 	movi	r2,-22
+ 801dcb0:	00001606 	br	801dd0c <alt_qspi_controller_read+0x98>
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801dcb4:	e0bffd17 	ldw	r2,-12(fp)
+ 801dcb8:	e0bffe15 	stw	r2,-8(fp)
+
+	/* validate arguments */
+	ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length);
+ 801dcbc:	e0bffc17 	ldw	r2,-16(fp)
+ 801dcc0:	e0fffa17 	ldw	r3,-24(fp)
+ 801dcc4:	180d883a 	mov	r6,r3
+ 801dcc8:	100b883a 	mov	r5,r2
+ 801dccc:	e13ffe17 	ldw	r4,-8(fp)
+ 801dcd0:	801df740 	call	801df74 <alt_qspi_validate_read_write_arguments>
+ 801dcd4:	e0bfff15 	stw	r2,-4(fp)
+
+	/* copy data from flash to destination address */
+	if(0 == ret_code)
+ 801dcd8:	e0bfff17 	ldw	r2,-4(fp)
+ 801dcdc:	10000a1e 	bne	r2,zero,801dd08 <alt_qspi_controller_read+0x94>
+	{
+		memcpy(dest_addr, (alt_u8*)qspi_flash_info->data_base + offset, length);
+ 801dce0:	e0bffe17 	ldw	r2,-8(fp)
+ 801dce4:	10c02e17 	ldw	r3,184(r2)
+ 801dce8:	e0bffc17 	ldw	r2,-16(fp)
+ 801dcec:	1885883a 	add	r2,r3,r2
+ 801dcf0:	1007883a 	mov	r3,r2
+ 801dcf4:	e0bffa17 	ldw	r2,-24(fp)
+ 801dcf8:	100d883a 	mov	r6,r2
+ 801dcfc:	180b883a 	mov	r5,r3
+ 801dd00:	e13ffb17 	ldw	r4,-20(fp)
+ 801dd04:	80086b80 	call	80086b8 <memcpy>
+	}
+
+    return ret_code;
+ 801dd08:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801dd0c:	e037883a 	mov	sp,fp
+ 801dd10:	dfc00117 	ldw	ra,4(sp)
+ 801dd14:	df000017 	ldw	fp,0(sp)
+ 801dd18:	dec00204 	addi	sp,sp,8
+ 801dd1c:	f800283a 	ret
+
+0801dd20 <altera_qspi_controller_init>:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments.
+ * -ENODEV -> System is configured incorrectly.
+**/
+alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *flash)
+{
+ 801dd20:	defffa04 	addi	sp,sp,-24
+ 801dd24:	dfc00515 	stw	ra,20(sp)
+ 801dd28:	df000415 	stw	fp,16(sp)
+ 801dd2c:	df000404 	addi	fp,sp,16
+ 801dd30:	e13ffc15 	stw	r4,-16(fp)
+	alt_u32 silicon_id = 0;
+ 801dd34:	e03fff15 	stw	zero,-4(fp)
+	alt_u32 size_in_bytes = 0;
+ 801dd38:	e03ffd15 	stw	zero,-12(fp)
+	alt_u32 number_of_sectors = 0;
+ 801dd3c:	e03ffe15 	stw	zero,-8(fp)
+
+    /* return -EINVAL if flash is NULL */
+	if(NULL == flash)
+ 801dd40:	e0bffc17 	ldw	r2,-16(fp)
+ 801dd44:	1000021e 	bne	r2,zero,801dd50 <altera_qspi_controller_init+0x30>
+    {
+    	return -EINVAL;
+ 801dd48:	00bffa84 	movi	r2,-22
+ 801dd4c:	00008406 	br	801df60 <altera_qspi_controller_init+0x240>
+    }
+	
+	/* return -ENODEV if CSR slave is not attached */
+	if(NULL == (void *)flash->csr_base)
+ 801dd50:	e0bffc17 	ldw	r2,-16(fp)
+ 801dd54:	10803017 	ldw	r2,192(r2)
+ 801dd58:	1000021e 	bne	r2,zero,801dd64 <altera_qspi_controller_init+0x44>
+	{
+		return -ENODEV;
+ 801dd5c:	00bffb44 	movi	r2,-19
+ 801dd60:	00007f06 	br	801df60 <altera_qspi_controller_init+0x240>
+	 *
+	 * In both cases, we can determine the number of sectors, which we can use
+	 * to calculate a size. We compare that size to the system.h value to make sure
+	 * the QSPI soft IP was configured correctly.
+	 */
+	if(0 == flash->is_epcs)
+ 801dd64:	e0bffc17 	ldw	r2,-16(fp)
+ 801dd68:	10803217 	ldw	r2,200(r2)
+ 801dd6c:	1000351e 	bne	r2,zero,801de44 <altera_qspi_controller_init+0x124>
+	{
+		/* If we're an EPCQ or QSPI, we read QSPI_RD_RDID for the silicon ID */
+		silicon_id = IORD_ALTERA_QSPI_CONTROLLER_RDID(flash->csr_base);
+ 801dd70:	e0bffc17 	ldw	r2,-16(fp)
+ 801dd74:	10803017 	ldw	r2,192(r2)
+ 801dd78:	10800204 	addi	r2,r2,8
+ 801dd7c:	10800037 	ldwio	r2,0(r2)
+ 801dd80:	e0bfff15 	stw	r2,-4(fp)
+		silicon_id &= ALTERA_QSPI_CONTROLLER_RDID_MASK;
+ 801dd84:	e0bfff17 	ldw	r2,-4(fp)
+ 801dd88:	10803fcc 	andi	r2,r2,255
+ 801dd8c:	e0bfff15 	stw	r2,-4(fp)
+
+		/* Determine which EPCQ/QSPI device so we can figure out the number of sectors */
+		/*EPCQ and QSPI share the same ID for the same capacity*/
+		switch(silicon_id)
+ 801dd90:	e0bfff17 	ldw	r2,-4(fp)
+ 801dd94:	10bffac4 	addi	r2,r2,-21
+ 801dd98:	10c00368 	cmpgeui	r3,r2,13
+ 801dd9c:	1800271e 	bne	r3,zero,801de3c <altera_qspi_controller_init+0x11c>
+ 801dda0:	100690ba 	slli	r3,r2,2
+ 801dda4:	008200b4 	movhi	r2,2050
+ 801dda8:	1885883a 	add	r2,r3,r2
+ 801ddac:	10b76d17 	ldw	r2,-8780(r2)
+ 801ddb0:	1000683a 	jmp	r2
+ 801ddb4:	0801dde8 	cmpgeui	zero,at,1911
+ 801ddb8:	0801ddf4 	orhi	zero,at,1911
+ 801ddbc:	0801de00 	call	801de0 <OSCtxSw_SWITCH_PC+0x801da0>
+ 801ddc0:	0801de0c 	andi	zero,at,1912
+ 801ddc4:	0801de18 	cmpnei	zero,at,1912
+ 801ddc8:	0801de3c 	xorhi	zero,at,1912
+ 801ddcc:	0801de3c 	xorhi	zero,at,1912
+ 801ddd0:	0801de3c 	xorhi	zero,at,1912
+ 801ddd4:	0801de3c 	xorhi	zero,at,1912
+ 801ddd8:	0801de3c 	xorhi	zero,at,1912
+ 801dddc:	0801de3c 	xorhi	zero,at,1912
+ 801dde0:	0801de24 	muli	zero,at,1912
+ 801dde4:	0801de30 	cmpltui	zero,at,1912
+		{
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI16:
+			{
+				number_of_sectors = 32;
+ 801dde8:	00800804 	movi	r2,32
+ 801ddec:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801ddf0:	00003006 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI32:
+			{
+				number_of_sectors = 64;
+ 801ddf4:	00801004 	movi	r2,64
+ 801ddf8:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801ddfc:	00002d06 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI64:
+			{
+				number_of_sectors = 128;
+ 801de00:	00802004 	movi	r2,128
+ 801de04:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de08:	00002a06 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI128:
+			{
+				number_of_sectors = 256;
+ 801de0c:	00804004 	movi	r2,256
+ 801de10:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de14:	00002706 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI256:
+			{
+				number_of_sectors = 512;
+ 801de18:	00808004 	movi	r2,512
+ 801de1c:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de20:	00002406 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI512:
+			{
+				number_of_sectors = 1024;
+ 801de24:	00810004 	movi	r2,1024
+ 801de28:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de2c:	00002106 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI1024:
+			{
+				number_of_sectors = 2048;
+ 801de30:	00820004 	movi	r2,2048
+ 801de34:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de38:	00001e06 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			default:
+			{
+				return -ENODEV;
+ 801de3c:	00bffb44 	movi	r2,-19
+ 801de40:	00004706 	br	801df60 <altera_qspi_controller_init+0x240>
+			}
+		}
+	}
+	else {
+		/* If we're an EPCS, we read QSPI_RD_SID for the silicon ID */
+		silicon_id = IORD_ALTERA_QSPI_CONTROLLER_SID(flash->csr_base);
+ 801de44:	e0bffc17 	ldw	r2,-16(fp)
+ 801de48:	10803017 	ldw	r2,192(r2)
+ 801de4c:	10800104 	addi	r2,r2,4
+ 801de50:	10800037 	ldwio	r2,0(r2)
+ 801de54:	e0bfff15 	stw	r2,-4(fp)
+		silicon_id &= ALTERA_QSPI_CONTROLLER_SID_MASK;
+ 801de58:	e0bfff17 	ldw	r2,-4(fp)
+ 801de5c:	10803fcc 	andi	r2,r2,255
+ 801de60:	e0bfff15 	stw	r2,-4(fp)
+
+		/* Determine which EPCS device so we can figure out various properties */
+		switch(silicon_id)
+ 801de64:	e0bfff17 	ldw	r2,-4(fp)
+ 801de68:	108005a0 	cmpeqi	r2,r2,22
+ 801de6c:	1000091e 	bne	r2,zero,801de94 <altera_qspi_controller_init+0x174>
+ 801de70:	e0bfff17 	ldw	r2,-4(fp)
+ 801de74:	10800620 	cmpeqi	r2,r2,24
+ 801de78:	1000091e 	bne	r2,zero,801dea0 <altera_qspi_controller_init+0x180>
+ 801de7c:	e0bfff17 	ldw	r2,-4(fp)
+ 801de80:	10800518 	cmpnei	r2,r2,20
+ 801de84:	1000091e 	bne	r2,zero,801deac <altera_qspi_controller_init+0x18c>
+		{
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS16:
+			{
+				number_of_sectors = 32;
+ 801de88:	00800804 	movi	r2,32
+ 801de8c:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de90:	00000806 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS64:
+			{
+				number_of_sectors = 128;
+ 801de94:	00802004 	movi	r2,128
+ 801de98:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801de9c:	00000506 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS128:
+			{
+				number_of_sectors = 256;
+ 801dea0:	00804004 	movi	r2,256
+ 801dea4:	e0bffe15 	stw	r2,-8(fp)
+				break;
+ 801dea8:	00000206 	br	801deb4 <altera_qspi_controller_init+0x194>
+			}
+			default:
+			{
+				return -ENODEV;
+ 801deac:	00bffb44 	movi	r2,-19
+ 801deb0:	00002b06 	br	801df60 <altera_qspi_controller_init+0x240>
+			}
+		}
+	}
+
+	/* Calculate size of flash based on number of sectors */
+	size_in_bytes = number_of_sectors * flash->sector_size;
+ 801deb4:	e0bffc17 	ldw	r2,-16(fp)
+ 801deb8:	10803417 	ldw	r2,208(r2)
+ 801debc:	e0fffe17 	ldw	r3,-8(fp)
+ 801dec0:	1885383a 	mul	r2,r3,r2
+ 801dec4:	e0bffd15 	stw	r2,-12(fp)
+	/*
+	 * Make sure calculated size is the same size given in system.h
+	 * Also check number of sectors is the same number given in system.h
+	 * Otherwise the QSPI IP was not configured correctly
+	 */
+	if(	size_in_bytes != flash->size_in_bytes ||
+ 801dec8:	e0bffc17 	ldw	r2,-16(fp)
+ 801decc:	10803117 	ldw	r2,196(r2)
+ 801ded0:	e0fffd17 	ldw	r3,-12(fp)
+ 801ded4:	1880041e 	bne	r3,r2,801dee8 <altera_qspi_controller_init+0x1c8>
+			number_of_sectors != flash->number_of_sectors)
+ 801ded8:	e0bffc17 	ldw	r2,-16(fp)
+ 801dedc:	10803317 	ldw	r2,204(r2)
+	if(	size_in_bytes != flash->size_in_bytes ||
+ 801dee0:	e0fffe17 	ldw	r3,-8(fp)
+ 801dee4:	18800426 	beq	r3,r2,801def8 <altera_qspi_controller_init+0x1d8>
+	{
+		flash->dev.number_of_regions = 0;
+ 801dee8:	e0bffc17 	ldw	r2,-16(fp)
+ 801deec:	10000c15 	stw	zero,48(r2)
+		return -ENODEV;
+ 801def0:	00bffb44 	movi	r2,-19
+ 801def4:	00001a06 	br	801df60 <altera_qspi_controller_init+0x240>
+	}
+	else
+	{
+		flash->silicon_id = silicon_id;
+ 801def8:	e0bffc17 	ldw	r2,-16(fp)
+ 801defc:	e0ffff17 	ldw	r3,-4(fp)
+ 801df00:	10c03615 	stw	r3,216(r2)
+		flash->number_of_sectors = number_of_sectors;
+ 801df04:	e0bffc17 	ldw	r2,-16(fp)
+ 801df08:	e0fffe17 	ldw	r3,-8(fp)
+ 801df0c:	10c03315 	stw	r3,204(r2)
+
+		/*
+		 * populate fields of region_info required to conform to HAL API
+		 * create 1 region that composed of "number_of_sectors" blocks
+		 */
+		flash->dev.number_of_regions = 1;
+ 801df10:	e0bffc17 	ldw	r2,-16(fp)
+ 801df14:	00c00044 	movi	r3,1
+ 801df18:	10c00c15 	stw	r3,48(r2)
+		flash->dev.region_info[0].offset = 0;
+ 801df1c:	e0bffc17 	ldw	r2,-16(fp)
+ 801df20:	10000d15 	stw	zero,52(r2)
+		flash->dev.region_info[0].region_size = size_in_bytes;
+ 801df24:	e0fffd17 	ldw	r3,-12(fp)
+ 801df28:	e0bffc17 	ldw	r2,-16(fp)
+ 801df2c:	10c00e15 	stw	r3,56(r2)
+		flash->dev.region_info[0].number_of_blocks = number_of_sectors;
+ 801df30:	e0fffe17 	ldw	r3,-8(fp)
+ 801df34:	e0bffc17 	ldw	r2,-16(fp)
+ 801df38:	10c00f15 	stw	r3,60(r2)
+		flash->dev.region_info[0].block_size = flash->sector_size;
+ 801df3c:	e0bffc17 	ldw	r2,-16(fp)
+ 801df40:	10803417 	ldw	r2,208(r2)
+ 801df44:	1007883a 	mov	r3,r2
+ 801df48:	e0bffc17 	ldw	r2,-16(fp)
+ 801df4c:	10c01015 	stw	r3,64(r2)
+    /*
+     * Register this device as a valid flash device type
+     *
+     * Only register the device if it's configured correctly.
+     */
+		alt_flash_device_register(&(flash->dev));
+ 801df50:	e0bffc17 	ldw	r2,-16(fp)
+ 801df54:	1009883a 	mov	r4,r2
+ 801df58:	801d5880 	call	801d588 <alt_flash_device_register>
+
+
+    return 0;
+ 801df5c:	0005883a 	mov	r2,zero
+}
+ 801df60:	e037883a 	mov	sp,fp
+ 801df64:	dfc00117 	ldw	ra,4(sp)
+ 801df68:	df000017 	ldw	fp,0(sp)
+ 801df6c:	dec00204 	addi	sp,sp,8
+ 801df70:	f800283a 	ret
+
+0801df74 <alt_qspi_validate_read_write_arguments>:
+(
+		alt_qspi_controller_dev *flash_info, /** device info */
+		alt_u32 offset, /** offset of read/write */
+		alt_u32 length /** length of read/write */
+)
+{
+ 801df74:	defff904 	addi	sp,sp,-28
+ 801df78:	df000615 	stw	fp,24(sp)
+ 801df7c:	df000604 	addi	fp,sp,24
+ 801df80:	e13ffc15 	stw	r4,-16(fp)
+ 801df84:	e17ffb15 	stw	r5,-20(fp)
+ 801df88:	e1bffa15 	stw	r6,-24(fp)
+    alt_qspi_controller_dev *qspi_flash_info = NULL;
+ 801df8c:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 start_address = 0;
+ 801df90:	e03ffe15 	stw	zero,-8(fp)
+    alt_32 end_address = 0;
+ 801df94:	e03ffd15 	stw	zero,-12(fp)
+	
+  /* return -EINVAL if flash_info is NULL */
+   if(NULL == flash_info)
+ 801df98:	e0bffc17 	ldw	r2,-16(fp)
+ 801df9c:	1000021e 	bne	r2,zero,801dfa8 <alt_qspi_validate_read_write_arguments+0x34>
+   {
+    	return -EINVAL;
+ 801dfa0:	00bffa84 	movi	r2,-22
+ 801dfa4:	00001606 	br	801e000 <alt_qspi_validate_read_write_arguments+0x8c>
+   }
+	
+  qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+ 801dfa8:	e0bffc17 	ldw	r2,-16(fp)
+ 801dfac:	e0bfff15 	stw	r2,-4(fp)
+
+  start_address = qspi_flash_info->data_base + offset; /** first address of read or write */
+ 801dfb0:	e0bfff17 	ldw	r2,-4(fp)
+ 801dfb4:	10802e17 	ldw	r2,184(r2)
+ 801dfb8:	e0fffb17 	ldw	r3,-20(fp)
+ 801dfbc:	1885883a 	add	r2,r3,r2
+ 801dfc0:	e0bffe15 	stw	r2,-8(fp)
+  end_address = start_address + length; /** last address of read or write (not inclusive) */
+ 801dfc4:	e0fffe17 	ldw	r3,-8(fp)
+ 801dfc8:	e0bffa17 	ldw	r2,-24(fp)
+ 801dfcc:	1885883a 	add	r2,r3,r2
+ 801dfd0:	e0bffd15 	stw	r2,-12(fp)
+
+  /* make sure start and end address is less then the end address of the flash */
+  if(
+		  start_address >= qspi_flash_info->data_end ||
+ 801dfd4:	e0bfff17 	ldw	r2,-4(fp)
+ 801dfd8:	10802f17 	ldw	r2,188(r2)
+  if(
+ 801dfdc:	e0fffe17 	ldw	r3,-8(fp)
+ 801dfe0:	1880042e 	bgeu	r3,r2,801dff4 <alt_qspi_validate_read_write_arguments+0x80>
+		  end_address >= qspi_flash_info->data_end ||
+ 801dfe4:	e0bfff17 	ldw	r2,-4(fp)
+ 801dfe8:	10802f17 	ldw	r2,188(r2)
+ 801dfec:	e0fffd17 	ldw	r3,-12(fp)
+		  offset < 0 ||
+ 801dff0:	18800236 	bltu	r3,r2,801dffc <alt_qspi_validate_read_write_arguments+0x88>
+		  length < 0
+  )
+  {
+	  return -EINVAL;
+ 801dff4:	00bffa84 	movi	r2,-22
+ 801dff8:	00000106 	br	801e000 <alt_qspi_validate_read_write_arguments+0x8c>
+  }
+
+  return 0;
+ 801dffc:	0005883a 	mov	r2,zero
+}
+ 801e000:	e037883a 	mov	sp,fp
+ 801e004:	df000017 	ldw	fp,0(sp)
+ 801e008:	dec00104 	addi	sp,sp,4
+ 801e00c:	f800283a 	ret
+
+0801e010 <alt_qspi_poll_for_write_in_progress>:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ * -ETIME  -> Time out and skipping the looping after 0.7 sec.
+ */
+alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info)
+{  
+ 801e010:	defffb04 	addi	sp,sp,-20
+ 801e014:	dfc00415 	stw	ra,16(sp)
+ 801e018:	df000315 	stw	fp,12(sp)
+ 801e01c:	df000304 	addi	fp,sp,12
+ 801e020:	e13ffd15 	stw	r4,-12(fp)
+    /* we'll want to implement timeout if a timeout value is specified */
+#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0
+	alt_u32 timeout = ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE;
+ 801e024:	008002f4 	movhi	r2,11
+ 801e028:	10ab9804 	addi	r2,r2,-20896
+ 801e02c:	e0bffe15 	stw	r2,-8(fp)
+	alt_u16 counter = 0;
+ 801e030:	e03fff8d 	sth	zero,-2(fp)
+#endif
+
+    /* return -EINVAL if qspi_flash_info is NULL */
+	if(NULL == qspi_flash_info)
+ 801e034:	e0bffd17 	ldw	r2,-12(fp)
+ 801e038:	10000c1e 	bne	r2,zero,801e06c <alt_qspi_poll_for_write_in_progress+0x5c>
+    {
+    	return -EINVAL;
+ 801e03c:	00bffa84 	movi	r2,-22
+ 801e040:	00001106 	br	801e088 <alt_qspi_poll_for_write_in_progress+0x78>
+	/* while Write in Progress bit is set, we wait */
+	while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) &
+			ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK) ==
+			ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY)
+	{
+        alt_busy_sleep(1); /* delay 1us */
+ 801e044:	01000044 	movi	r4,1
+ 801e048:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0
+		if(timeout <= counter )
+ 801e04c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 801e050:	e0bffe17 	ldw	r2,-8(fp)
+ 801e054:	18800236 	bltu	r3,r2,801e060 <alt_qspi_poll_for_write_in_progress+0x50>
+		{
+			return -ETIME;
+ 801e058:	00bff084 	movi	r2,-62
+ 801e05c:	00000a06 	br	801e088 <alt_qspi_poll_for_write_in_progress+0x78>
+		}
+		
+		counter++;
+ 801e060:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801e064:	10800044 	addi	r2,r2,1
+ 801e068:	e0bfff8d 	sth	r2,-2(fp)
+	while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) &
+ 801e06c:	e0bffd17 	ldw	r2,-12(fp)
+ 801e070:	10803017 	ldw	r2,192(r2)
+ 801e074:	10800037 	ldwio	r2,0(r2)
+ 801e078:	1080004c 	andi	r2,r2,1
+ 801e07c:	10800060 	cmpeqi	r2,r2,1
+ 801e080:	103ff01e 	bne	r2,zero,801e044 <alt_qspi_poll_for_write_in_progress+0x34>
+#endif
+
+	}
+
+	return 0;
+ 801e084:	0005883a 	mov	r2,zero
+}
+ 801e088:	e037883a 	mov	sp,fp
+ 801e08c:	dfc00117 	ldw	ra,4(sp)
+ 801e090:	df000017 	ldw	fp,0(sp)
+ 801e094:	dec00204 	addi	sp,sp,8
+ 801e098:	f800283a 	ret
+
+0801e09c <alt_get_errno>:
+{
+ 801e09c:	defffe04 	addi	sp,sp,-8
+ 801e0a0:	dfc00115 	stw	ra,4(sp)
+ 801e0a4:	df000015 	stw	fp,0(sp)
+ 801e0a8:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 801e0ac:	d0a02717 	ldw	r2,-32612(gp)
+ 801e0b0:	10000326 	beq	r2,zero,801e0c0 <alt_get_errno+0x24>
+ 801e0b4:	d0a02717 	ldw	r2,-32612(gp)
+ 801e0b8:	103ee83a 	callr	r2
+ 801e0bc:	00000106 	br	801e0c4 <alt_get_errno+0x28>
+ 801e0c0:	d0a04204 	addi	r2,gp,-32504
+}
+ 801e0c4:	e037883a 	mov	sp,fp
+ 801e0c8:	dfc00117 	ldw	ra,4(sp)
+ 801e0cc:	df000017 	ldw	fp,0(sp)
+ 801e0d0:	dec00204 	addi	sp,sp,8
+ 801e0d4:	f800283a 	ret
+
+0801e0d8 <alt_msgdma_write_standard_descriptor>:
+ */
+static int alt_msgdma_write_standard_descriptor (
+    alt_u32 *csr_base, 
+    alt_u32 *descriptor_base,
+    alt_msgdma_standard_descriptor *descriptor)
+{
+ 801e0d8:	defffc04 	addi	sp,sp,-16
+ 801e0dc:	df000315 	stw	fp,12(sp)
+ 801e0e0:	df000304 	addi	fp,sp,12
+ 801e0e4:	e13fff15 	stw	r4,-4(fp)
+ 801e0e8:	e17ffe15 	stw	r5,-8(fp)
+ 801e0ec:	e1bffd15 	stw	r6,-12(fp)
+    if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & 
+ 801e0f0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e0f4:	10800037 	ldwio	r2,0(r2)
+ 801e0f8:	1080010c 	andi	r2,r2,4
+ 801e0fc:	10000226 	beq	r2,zero,801e108 <alt_msgdma_write_standard_descriptor+0x30>
+        ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK))
+    {
+      /*at least one descriptor buffer is full, returning so that this function 
+        is non-blocking*/
+        return -ENOSPC;
+ 801e100:	00bff904 	movi	r2,-28
+ 801e104:	00001506 	br	801e15c <alt_msgdma_write_standard_descriptor+0x84>
+    }
+
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(descriptor_base, 
+ 801e108:	e0bffd17 	ldw	r2,-12(fp)
+ 801e10c:	10800017 	ldw	r2,0(r2)
+ 801e110:	1007883a 	mov	r3,r2
+ 801e114:	e0bffe17 	ldw	r2,-8(fp)
+ 801e118:	10c00035 	stwio	r3,0(r2)
+        (alt_u32)descriptor->read_address);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(descriptor_base, 
+ 801e11c:	e0bffe17 	ldw	r2,-8(fp)
+ 801e120:	10800104 	addi	r2,r2,4
+ 801e124:	e0fffd17 	ldw	r3,-12(fp)
+ 801e128:	18c00117 	ldw	r3,4(r3)
+ 801e12c:	10c00035 	stwio	r3,0(r2)
+    (    alt_u32)descriptor->write_address);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(descriptor_base, 
+ 801e130:	e0bffe17 	ldw	r2,-8(fp)
+ 801e134:	10800204 	addi	r2,r2,8
+ 801e138:	e0fffd17 	ldw	r3,-12(fp)
+ 801e13c:	18c00217 	ldw	r3,8(r3)
+ 801e140:	10c00035 	stwio	r3,0(r2)
+        descriptor->transfer_length);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(descriptor_base, 
+ 801e144:	e0bffe17 	ldw	r2,-8(fp)
+ 801e148:	10800304 	addi	r2,r2,12
+ 801e14c:	e0fffd17 	ldw	r3,-12(fp)
+ 801e150:	18c00317 	ldw	r3,12(r3)
+ 801e154:	10c00035 	stwio	r3,0(r2)
+        descriptor->control);
+        return 0;
+ 801e158:	0005883a 	mov	r2,zero
+}
+ 801e15c:	e037883a 	mov	sp,fp
+ 801e160:	df000017 	ldw	fp,0(sp)
+ 801e164:	dec00104 	addi	sp,sp,4
+ 801e168:	f800283a 	ret
+
+0801e16c <alt_msgdma_write_extended_descriptor>:
+ */
+static int alt_msgdma_write_extended_descriptor (
+    alt_u32 *csr_base, 
+    alt_u32 *descriptor_base,
+    alt_msgdma_extended_descriptor *descriptor)
+{
+ 801e16c:	defffc04 	addi	sp,sp,-16
+ 801e170:	df000315 	stw	fp,12(sp)
+ 801e174:	df000304 	addi	fp,sp,12
+ 801e178:	e13fff15 	stw	r4,-4(fp)
+ 801e17c:	e17ffe15 	stw	r5,-8(fp)
+ 801e180:	e1bffd15 	stw	r6,-12(fp)
+    if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & 
+ 801e184:	e0bfff17 	ldw	r2,-4(fp)
+ 801e188:	10800037 	ldwio	r2,0(r2)
+ 801e18c:	1080010c 	andi	r2,r2,4
+ 801e190:	10000226 	beq	r2,zero,801e19c <alt_msgdma_write_extended_descriptor+0x30>
+        ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK))
+    {
+      /*at least one descriptor buffer is full, returning so that this function 
+    is non-blocking*/
+        return -ENOSPC;
+ 801e194:	00bff904 	movi	r2,-28
+ 801e198:	00003b06 	br	801e288 <alt_msgdma_write_extended_descriptor+0x11c>
+    }
+
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(
+ 801e19c:	e0bffd17 	ldw	r2,-12(fp)
+ 801e1a0:	10800017 	ldw	r2,0(r2)
+ 801e1a4:	1007883a 	mov	r3,r2
+ 801e1a8:	e0bffe17 	ldw	r2,-8(fp)
+ 801e1ac:	10c00035 	stwio	r3,0(r2)
+        descriptor_base, 
+        (alt_u32)descriptor->read_address_low);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(
+ 801e1b0:	e0bffe17 	ldw	r2,-8(fp)
+ 801e1b4:	10800104 	addi	r2,r2,4
+ 801e1b8:	e0fffd17 	ldw	r3,-12(fp)
+ 801e1bc:	18c00117 	ldw	r3,4(r3)
+ 801e1c0:	10c00035 	stwio	r3,0(r2)
+        descriptor_base, 
+        (alt_u32)descriptor->write_address_low);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(
+ 801e1c4:	e0bffe17 	ldw	r2,-8(fp)
+ 801e1c8:	10800204 	addi	r2,r2,8
+ 801e1cc:	e0fffd17 	ldw	r3,-12(fp)
+ 801e1d0:	18c00217 	ldw	r3,8(r3)
+ 801e1d4:	10c00035 	stwio	r3,0(r2)
+        descriptor_base, 
+        descriptor->transfer_length);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(
+ 801e1d8:	e0bffe17 	ldw	r2,-8(fp)
+ 801e1dc:	10800304 	addi	r2,r2,12
+ 801e1e0:	e0fffd17 	ldw	r3,-12(fp)
+ 801e1e4:	18c0030b 	ldhu	r3,12(r3)
+ 801e1e8:	18ffffcc 	andi	r3,r3,65535
+ 801e1ec:	10c0002d 	sthio	r3,0(r2)
+        descriptor_base, 
+        descriptor->sequence_number);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(
+ 801e1f0:	e0bffe17 	ldw	r2,-8(fp)
+ 801e1f4:	10800384 	addi	r2,r2,14
+ 801e1f8:	e0fffd17 	ldw	r3,-12(fp)
+ 801e1fc:	18c00383 	ldbu	r3,14(r3)
+ 801e200:	18c03fcc 	andi	r3,r3,255
+ 801e204:	10c00025 	stbio	r3,0(r2)
+        descriptor_base, 
+        descriptor->read_burst_count);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(
+ 801e208:	e0bffe17 	ldw	r2,-8(fp)
+ 801e20c:	108003c4 	addi	r2,r2,15
+ 801e210:	e0fffd17 	ldw	r3,-12(fp)
+ 801e214:	18c003c3 	ldbu	r3,15(r3)
+ 801e218:	18c03fcc 	andi	r3,r3,255
+ 801e21c:	10c00025 	stbio	r3,0(r2)
+        descriptor_base, 
+        descriptor->write_burst_count);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(
+ 801e220:	e0bffe17 	ldw	r2,-8(fp)
+ 801e224:	10800404 	addi	r2,r2,16
+ 801e228:	e0fffd17 	ldw	r3,-12(fp)
+ 801e22c:	18c0040b 	ldhu	r3,16(r3)
+ 801e230:	18ffffcc 	andi	r3,r3,65535
+ 801e234:	10c0002d 	sthio	r3,0(r2)
+        descriptor_base, 
+        descriptor->read_stride);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(
+ 801e238:	e0bffe17 	ldw	r2,-8(fp)
+ 801e23c:	10800484 	addi	r2,r2,18
+ 801e240:	e0fffd17 	ldw	r3,-12(fp)
+ 801e244:	18c0048b 	ldhu	r3,18(r3)
+ 801e248:	18ffffcc 	andi	r3,r3,65535
+ 801e24c:	10c0002d 	sthio	r3,0(r2)
+        descriptor_base, 
+        descriptor->write_stride);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(descriptor_base, 0);
+ 801e250:	e0bffe17 	ldw	r2,-8(fp)
+ 801e254:	10800504 	addi	r2,r2,20
+ 801e258:	0007883a 	mov	r3,zero
+ 801e25c:	10c00035 	stwio	r3,0(r2)
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(descriptor_base, 0);
+ 801e260:	e0bffe17 	ldw	r2,-8(fp)
+ 801e264:	10800604 	addi	r2,r2,24
+ 801e268:	0007883a 	mov	r3,zero
+ 801e26c:	10c00035 	stwio	r3,0(r2)
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED(
+ 801e270:	e0bffe17 	ldw	r2,-8(fp)
+ 801e274:	10800704 	addi	r2,r2,28
+ 801e278:	e0fffd17 	ldw	r3,-12(fp)
+ 801e27c:	18c00717 	ldw	r3,28(r3)
+ 801e280:	10c00035 	stwio	r3,0(r2)
+        descriptor_base, 
+        descriptor->control);
+    return 0;
+ 801e284:	0005883a 	mov	r2,zero
+}
+ 801e288:	e037883a 	mov	sp,fp
+ 801e28c:	df000017 	ldw	fp,0(sp)
+ 801e290:	dec00104 	addi	sp,sp,4
+ 801e294:	f800283a 	ret
+
+0801e298 <alt_msgdma_irq>:
+ * alt_msgdma_irq()
+ *
+ * Interrupt handler for the Modular Scatter-Gather DMA controller.
+ */
+static void alt_msgdma_irq(void *context)
+{
+ 801e298:	defff804 	addi	sp,sp,-32
+ 801e29c:	dfc00715 	stw	ra,28(sp)
+ 801e2a0:	df000615 	stw	fp,24(sp)
+ 801e2a4:	df000604 	addi	fp,sp,24
+ 801e2a8:	e13ffa15 	stw	r4,-24(fp)
+    alt_msgdma_dev *dev = (alt_msgdma_dev *) context;
+ 801e2ac:	e0bffa17 	ldw	r2,-24(fp)
+ 801e2b0:	e0bfff15 	stw	r2,-4(fp)
+    alt_irq_context cpu_sr;
+    alt_u32 temporary_control;
+
+    
+    /* disable global interrupt*/
+    if (dev->prefetcher_enable)
+ 801e2b4:	e0bfff17 	ldw	r2,-4(fp)
+ 801e2b8:	10801783 	ldbu	r2,94(r2)
+ 801e2bc:	10803fcc 	andi	r2,r2,255
+ 801e2c0:	10001126 	beq	r2,zero,801e308 <alt_msgdma_irq+0x70>
+    {
+        temporary_control = 
+                IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)
+ 801e2c4:	e0bfff17 	ldw	r2,-4(fp)
+ 801e2c8:	10800617 	ldw	r2,24(r2)
+ 801e2cc:	10800037 	ldwio	r2,0(r2)
+                & ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK;
+ 801e2d0:	1007883a 	mov	r3,r2
+        temporary_control = 
+ 801e2d4:	00bffdc4 	movi	r2,-9
+ 801e2d8:	1884703a 	and	r2,r3,r2
+ 801e2dc:	e0bffe15 	stw	r2,-8(fp)
+        
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base,
+ 801e2e0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e2e4:	10800617 	ldw	r2,24(r2)
+ 801e2e8:	e0fffe17 	ldw	r3,-8(fp)
+ 801e2ec:	10c00035 	stwio	r3,0(r2)
+                temporary_control);
+        
+        /* clear the IRQ status- W1C */
+        IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base,
+ 801e2f0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e2f4:	10800617 	ldw	r2,24(r2)
+ 801e2f8:	10800404 	addi	r2,r2,16
+ 801e2fc:	00c00044 	movi	r3,1
+ 801e300:	10c00035 	stwio	r3,0(r2)
+ 801e304:	00001106 	br	801e34c <alt_msgdma_irq+0xb4>
+                ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK);
+    }
+    else
+    {
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+ 801e308:	e0bfff17 	ldw	r2,-4(fp)
+ 801e30c:	10800317 	ldw	r2,12(r2)
+ 801e310:	10800104 	addi	r2,r2,4
+ 801e314:	10800037 	ldwio	r2,0(r2)
+                & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+ 801e318:	1007883a 	mov	r3,r2
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+ 801e31c:	00bffbc4 	movi	r2,-17
+ 801e320:	1884703a 	and	r2,r3,r2
+ 801e324:	e0bffe15 	stw	r2,-8(fp)
+        
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+ 801e328:	e0bfff17 	ldw	r2,-4(fp)
+ 801e32c:	10800317 	ldw	r2,12(r2)
+ 801e330:	10800104 	addi	r2,r2,4
+ 801e334:	e0fffe17 	ldw	r3,-8(fp)
+ 801e338:	10c00035 	stwio	r3,0(r2)
+        /* clear the IRQ status */
+        IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base,
+ 801e33c:	e0bfff17 	ldw	r2,-4(fp)
+ 801e340:	10800317 	ldw	r2,12(r2)
+ 801e344:	00c08004 	movi	r3,512
+ 801e348:	10c00035 	stwio	r3,0(r2)
+    * Other interrupts are explicitly disabled if callbacks
+    * are registered because there is no guarantee that they are 
+    * pre-emption-safe. This allows the driver to support 
+    * interrupt pre-emption.
+    */
+    if(dev->callback) 
+ 801e34c:	e0bfff17 	ldw	r2,-4(fp)
+ 801e350:	10800b17 	ldw	r2,44(r2)
+ 801e354:	10001226 	beq	r2,zero,801e3a0 <alt_msgdma_irq+0x108>
+  NIOS2_READ_STATUS (context);
+ 801e358:	0005303a 	rdctl	r2,status
+ 801e35c:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801e360:	e0fffb17 	ldw	r3,-20(fp)
+ 801e364:	00bfff84 	movi	r2,-2
+ 801e368:	1884703a 	and	r2,r3,r2
+ 801e36c:	1001703a 	wrctl	status,r2
+  return context;
+ 801e370:	e0bffb17 	ldw	r2,-20(fp)
+    {
+        cpu_sr = alt_irq_disable_all();
+ 801e374:	e0bffd15 	stw	r2,-12(fp)
+        dev->callback (dev->callback_context);
+ 801e378:	e0bfff17 	ldw	r2,-4(fp)
+ 801e37c:	10800b17 	ldw	r2,44(r2)
+ 801e380:	e0ffff17 	ldw	r3,-4(fp)
+ 801e384:	18c00c17 	ldw	r3,48(r3)
+ 801e388:	1809883a 	mov	r4,r3
+ 801e38c:	103ee83a 	callr	r2
+ 801e390:	e0bffd17 	ldw	r2,-12(fp)
+ 801e394:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801e398:	e0bffc17 	ldw	r2,-16(fp)
+ 801e39c:	1001703a 	wrctl	status,r2
+        alt_irq_enable_all(cpu_sr);
+    }
+
+    /* enable global interrupt */
+    if (dev->prefetcher_enable)
+ 801e3a0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e3a4:	10801783 	ldbu	r2,94(r2)
+ 801e3a8:	10803fcc 	andi	r2,r2,255
+ 801e3ac:	10000a26 	beq	r2,zero,801e3d8 <alt_msgdma_irq+0x140>
+    {
+        temporary_control = 
+                IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)
+ 801e3b0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e3b4:	10800617 	ldw	r2,24(r2)
+ 801e3b8:	10800037 	ldwio	r2,0(r2)
+                | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK;
+ 801e3bc:	10800214 	ori	r2,r2,8
+        temporary_control = 
+ 801e3c0:	e0bffe15 	stw	r2,-8(fp)
+        
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base,
+ 801e3c4:	e0bfff17 	ldw	r2,-4(fp)
+ 801e3c8:	10800617 	ldw	r2,24(r2)
+ 801e3cc:	e0fffe17 	ldw	r3,-8(fp)
+ 801e3d0:	10c00035 	stwio	r3,0(r2)
+                | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+        
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+    }
+
+    return;
+ 801e3d4:	00000c06 	br	801e408 <alt_msgdma_irq+0x170>
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) 
+ 801e3d8:	e0bfff17 	ldw	r2,-4(fp)
+ 801e3dc:	10800317 	ldw	r2,12(r2)
+ 801e3e0:	10800104 	addi	r2,r2,4
+ 801e3e4:	10800037 	ldwio	r2,0(r2)
+                | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+ 801e3e8:	10800414 	ori	r2,r2,16
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) 
+ 801e3ec:	e0bffe15 	stw	r2,-8(fp)
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+ 801e3f0:	e0bfff17 	ldw	r2,-4(fp)
+ 801e3f4:	10800317 	ldw	r2,12(r2)
+ 801e3f8:	10800104 	addi	r2,r2,4
+ 801e3fc:	e0fffe17 	ldw	r3,-8(fp)
+ 801e400:	10c00035 	stwio	r3,0(r2)
+    return;
+ 801e404:	0001883a 	nop
+}
+ 801e408:	e037883a 	mov	sp,fp
+ 801e40c:	dfc00117 	ldw	ra,4(sp)
+ 801e410:	df000017 	ldw	fp,0(sp)
+ 801e414:	dec00204 	addi	sp,sp,8
+ 801e418:	f800283a 	ret
+
+0801e41c <alt_msgdma_construct_standard_descriptor>:
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+ 801e41c:	defffb04 	addi	sp,sp,-20
+ 801e420:	df000415 	stw	fp,16(sp)
+ 801e424:	df000404 	addi	fp,sp,16
+ 801e428:	e13fff15 	stw	r4,-4(fp)
+ 801e42c:	e17ffe15 	stw	r5,-8(fp)
+ 801e430:	e1bffd15 	stw	r6,-12(fp)
+ 801e434:	e1fffc15 	stw	r7,-16(fp)
+    if(dev->max_byte < length ||
+ 801e438:	e0bfff17 	ldw	r2,-4(fp)
+ 801e43c:	10c01217 	ldw	r3,72(r2)
+ 801e440:	e0800117 	ldw	r2,4(fp)
+ 801e444:	18800436 	bltu	r3,r2,801e458 <alt_msgdma_construct_standard_descriptor+0x3c>
+       dev->enhanced_features != 0
+ 801e448:	e0bfff17 	ldw	r2,-4(fp)
+ 801e44c:	10801703 	ldbu	r2,92(r2)
+    if(dev->max_byte < length ||
+ 801e450:	10803fcc 	andi	r2,r2,255
+ 801e454:	10000226 	beq	r2,zero,801e460 <alt_msgdma_construct_standard_descriptor+0x44>
+      )
+    {
+        return -EINVAL;
+ 801e458:	00bffa84 	movi	r2,-22
+ 801e45c:	00000e06 	br	801e498 <alt_msgdma_construct_standard_descriptor+0x7c>
+    }
+    descriptor->read_address = read_address;
+ 801e460:	e0bffe17 	ldw	r2,-8(fp)
+ 801e464:	e0fffd17 	ldw	r3,-12(fp)
+ 801e468:	10c00015 	stw	r3,0(r2)
+    descriptor->write_address = write_address;
+ 801e46c:	e0bffe17 	ldw	r2,-8(fp)
+ 801e470:	e0fffc17 	ldw	r3,-16(fp)
+ 801e474:	10c00115 	stw	r3,4(r2)
+    descriptor->transfer_length = length;
+ 801e478:	e0bffe17 	ldw	r2,-8(fp)
+ 801e47c:	e0c00117 	ldw	r3,4(fp)
+ 801e480:	10c00215 	stw	r3,8(r2)
+    descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 801e484:	e0800217 	ldw	r2,8(fp)
+ 801e488:	10e00034 	orhi	r3,r2,32768
+ 801e48c:	e0bffe17 	ldw	r2,-8(fp)
+ 801e490:	10c00315 	stw	r3,12(r2)
+    
+    return 0;
+ 801e494:	0005883a 	mov	r2,zero
+}
+ 801e498:	e037883a 	mov	sp,fp
+ 801e49c:	df000017 	ldw	fp,0(sp)
+ 801e4a0:	dec00104 	addi	sp,sp,4
+ 801e4a4:	f800283a 	ret
+
+0801e4a8 <alt_msgdma_construct_extended_descriptor>:
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+ 801e4a8:	defff604 	addi	sp,sp,-40
+ 801e4ac:	df000915 	stw	fp,36(sp)
+ 801e4b0:	df000904 	addi	fp,sp,36
+ 801e4b4:	e13fff15 	stw	r4,-4(fp)
+ 801e4b8:	e17ffe15 	stw	r5,-8(fp)
+ 801e4bc:	e1bffd15 	stw	r6,-12(fp)
+ 801e4c0:	e1fffc15 	stw	r7,-16(fp)
+ 801e4c4:	e1800317 	ldw	r6,12(fp)
+ 801e4c8:	e1400417 	ldw	r5,16(fp)
+ 801e4cc:	e1000517 	ldw	r4,20(fp)
+ 801e4d0:	e0c00617 	ldw	r3,24(fp)
+ 801e4d4:	e0800717 	ldw	r2,28(fp)
+ 801e4d8:	e1bffb0d 	sth	r6,-20(fp)
+ 801e4dc:	e17ffa05 	stb	r5,-24(fp)
+ 801e4e0:	e13ff905 	stb	r4,-28(fp)
+ 801e4e4:	e0fff80d 	sth	r3,-32(fp)
+ 801e4e8:	e0bff70d 	sth	r2,-36(fp)
+    if(dev->max_byte < length ||
+ 801e4ec:	e0bfff17 	ldw	r2,-4(fp)
+ 801e4f0:	10c01217 	ldw	r3,72(r2)
+ 801e4f4:	e0800117 	ldw	r2,4(fp)
+ 801e4f8:	18801936 	bltu	r3,r2,801e560 <alt_msgdma_construct_extended_descriptor+0xb8>
+       dev->max_stride < read_stride ||
+ 801e4fc:	e13fff17 	ldw	r4,-4(fp)
+ 801e500:	20801317 	ldw	r2,76(r4)
+ 801e504:	20c01417 	ldw	r3,80(r4)
+ 801e508:	e13ff80b 	ldhu	r4,-32(fp)
+ 801e50c:	213fffcc 	andi	r4,r4,65535
+ 801e510:	2015883a 	mov	r10,r4
+ 801e514:	0017883a 	mov	r11,zero
+    if(dev->max_byte < length ||
+ 801e518:	1ac01136 	bltu	r3,r11,801e560 <alt_msgdma_construct_extended_descriptor+0xb8>
+ 801e51c:	58c0011e 	bne	r11,r3,801e524 <alt_msgdma_construct_extended_descriptor+0x7c>
+ 801e520:	12800f36 	bltu	r2,r10,801e560 <alt_msgdma_construct_extended_descriptor+0xb8>
+       dev->max_stride < write_stride ||
+ 801e524:	e13fff17 	ldw	r4,-4(fp)
+ 801e528:	20801317 	ldw	r2,76(r4)
+ 801e52c:	20c01417 	ldw	r3,80(r4)
+ 801e530:	e13ff70b 	ldhu	r4,-36(fp)
+ 801e534:	213fffcc 	andi	r4,r4,65535
+ 801e538:	2011883a 	mov	r8,r4
+ 801e53c:	0013883a 	mov	r9,zero
+       dev->max_stride < read_stride ||
+ 801e540:	1a400736 	bltu	r3,r9,801e560 <alt_msgdma_construct_extended_descriptor+0xb8>
+ 801e544:	48c0011e 	bne	r9,r3,801e54c <alt_msgdma_construct_extended_descriptor+0xa4>
+ 801e548:	12000536 	bltu	r2,r8,801e560 <alt_msgdma_construct_extended_descriptor+0xb8>
+       dev->enhanced_features != 1 
+ 801e54c:	e0bfff17 	ldw	r2,-4(fp)
+ 801e550:	10801703 	ldbu	r2,92(r2)
+       dev->max_stride < write_stride ||
+ 801e554:	10803fcc 	andi	r2,r2,255
+ 801e558:	10800060 	cmpeqi	r2,r2,1
+ 801e55c:	1000021e 	bne	r2,zero,801e568 <alt_msgdma_construct_extended_descriptor+0xc0>
+      )
+    {
+        return -EINVAL;
+ 801e560:	00bffa84 	movi	r2,-22
+ 801e564:	00002106 	br	801e5ec <alt_msgdma_construct_extended_descriptor+0x144>
+    }
+    
+    descriptor->read_address_low = read_address;
+ 801e568:	e0bffe17 	ldw	r2,-8(fp)
+ 801e56c:	e0fffd17 	ldw	r3,-12(fp)
+ 801e570:	10c00015 	stw	r3,0(r2)
+    descriptor->write_address_low = write_address;
+ 801e574:	e0bffe17 	ldw	r2,-8(fp)
+ 801e578:	e0fffc17 	ldw	r3,-16(fp)
+ 801e57c:	10c00115 	stw	r3,4(r2)
+    descriptor->transfer_length = length;
+ 801e580:	e0bffe17 	ldw	r2,-8(fp)
+ 801e584:	e0c00117 	ldw	r3,4(fp)
+ 801e588:	10c00215 	stw	r3,8(r2)
+    descriptor->sequence_number = sequence_number;
+ 801e58c:	e0bffe17 	ldw	r2,-8(fp)
+ 801e590:	e0fffb0b 	ldhu	r3,-20(fp)
+ 801e594:	10c0030d 	sth	r3,12(r2)
+    descriptor->read_burst_count = read_burst_count;
+ 801e598:	e0bffe17 	ldw	r2,-8(fp)
+ 801e59c:	e0fffa03 	ldbu	r3,-24(fp)
+ 801e5a0:	10c00385 	stb	r3,14(r2)
+    descriptor->write_burst_count = write_burst_count;
+ 801e5a4:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5a8:	e0fff903 	ldbu	r3,-28(fp)
+ 801e5ac:	10c003c5 	stb	r3,15(r2)
+    descriptor->read_stride = read_stride;
+ 801e5b0:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5b4:	e0fff80b 	ldhu	r3,-32(fp)
+ 801e5b8:	10c0040d 	sth	r3,16(r2)
+    descriptor->write_stride = write_stride;
+ 801e5bc:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5c0:	e0fff70b 	ldhu	r3,-36(fp)
+ 801e5c4:	10c0048d 	sth	r3,18(r2)
+    descriptor->read_address_high = NULL;
+ 801e5c8:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5cc:	10000515 	stw	zero,20(r2)
+    descriptor->write_address_high = NULL;
+ 801e5d0:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5d4:	10000615 	stw	zero,24(r2)
+    descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 801e5d8:	e0800217 	ldw	r2,8(fp)
+ 801e5dc:	10e00034 	orhi	r3,r2,32768
+ 801e5e0:	e0bffe17 	ldw	r2,-8(fp)
+ 801e5e4:	10c00715 	stw	r3,28(r2)
+
+  return 0 ;
+ 801e5e8:	0005883a 	mov	r2,zero
+
+}
+ 801e5ec:	e037883a 	mov	sp,fp
+ 801e5f0:	df000017 	ldw	fp,0(sp)
+ 801e5f4:	dec00104 	addi	sp,sp,4
+ 801e5f8:	f800283a 	ret
+
+0801e5fc <alt_msgdma_descriptor_async_transfer>:
+ */
+static int alt_msgdma_descriptor_async_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc)
+{
+ 801e5fc:	deffed04 	addi	sp,sp,-76
+ 801e600:	dfc01215 	stw	ra,72(sp)
+ 801e604:	df001115 	stw	fp,68(sp)
+ 801e608:	df001104 	addi	fp,sp,68
+ 801e60c:	e13ff115 	stw	r4,-60(fp)
+ 801e610:	e17ff015 	stw	r5,-64(fp)
+ 801e614:	e1bfef15 	stw	r6,-68(fp)
+    alt_u32 control = 0;
+ 801e618:	e03ffe15 	stw	zero,-8(fp)
+    alt_irq_context context = 0;
+ 801e61c:	e03ffd15 	stw	zero,-12(fp)
+    alt_u16 counter = 0;
+ 801e620:	e03fff8d 	sth	zero,-2(fp)
+    alt_u32 fifo_read_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e624:	e0bff117 	ldw	r2,-60(fp)
+ 801e628:	10800317 	ldw	r2,12(r2)
+ 801e62c:	10800204 	addi	r2,r2,8
+ 801e630:	10800037 	ldwio	r2,0(r2)
+    alt_u32 fifo_read_fill_level = (
+ 801e634:	10bfffcc 	andi	r2,r2,65535
+ 801e638:	e0bffc15 	stw	r2,-16(fp)
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+    alt_u32 fifo_write_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e63c:	e0bff117 	ldw	r2,-60(fp)
+ 801e640:	10800317 	ldw	r2,12(r2)
+ 801e644:	10800204 	addi	r2,r2,8
+ 801e648:	10800037 	ldwio	r2,0(r2)
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+ 801e64c:	1004d43a 	srli	r2,r2,16
+    alt_u32 fifo_write_fill_level = (
+ 801e650:	10bfffcc 	andi	r2,r2,65535
+ 801e654:	e0bffb15 	stw	r2,-20(fp)
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET;
+
+    /* Return with error immediately if one of read/write buffer is full */
+    if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+ 801e658:	e0bff117 	ldw	r2,-60(fp)
+ 801e65c:	10800917 	ldw	r2,36(r2)
+ 801e660:	e0fffb17 	ldw	r3,-20(fp)
+ 801e664:	1880042e 	bgeu	r3,r2,801e678 <alt_msgdma_descriptor_async_transfer+0x7c>
+        (dev->descriptor_fifo_depth <= fifo_read_fill_level))
+ 801e668:	e0bff117 	ldw	r2,-60(fp)
+ 801e66c:	10800917 	ldw	r2,36(r2)
+    if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+ 801e670:	e0fffc17 	ldw	r3,-16(fp)
+ 801e674:	18800236 	bltu	r3,r2,801e680 <alt_msgdma_descriptor_async_transfer+0x84>
+    {
+        /*at least one write or read FIFO descriptor buffer is full,
+        returning so that this function is non-blocking*/
+        return -ENOSPC;
+ 801e678:	00bff904 	movi	r2,-28
+ 801e67c:	0000a906 	br	801e924 <alt_msgdma_descriptor_async_transfer+0x328>
+    
+    /*
+    * When running in a multi threaded environment, obtain the "regs_lock"
+    * semaphore. This ensures that accessing registers is thread-safe.
+    */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+ 801e680:	e0bff117 	ldw	r2,-60(fp)
+ 801e684:	10801817 	ldw	r2,96(r2)
+ 801e688:	e0bff815 	stw	r2,-32(fp)
+ 801e68c:	e03ff78d 	sth	zero,-34(fp)
+ 801e690:	e0bff78b 	ldhu	r2,-34(fp)
+ 801e694:	e0fff2c4 	addi	r3,fp,-53
+ 801e698:	180d883a 	mov	r6,r3
+ 801e69c:	100b883a 	mov	r5,r2
+ 801e6a0:	e13ff817 	ldw	r4,-32(fp)
+ 801e6a4:	8015a600 	call	8015a60 <OSSemPend>
+    
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* stop issuing more descriptors */
+    control = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+ 801e6a8:	00800804 	movi	r2,32
+ 801e6ac:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 801e6b0:	0005303a 	rdctl	r2,status
+ 801e6b4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801e6b8:	e0fff917 	ldw	r3,-28(fp)
+ 801e6bc:	00bfff84 	movi	r2,-2
+ 801e6c0:	1884703a 	and	r2,r3,r2
+ 801e6c4:	1001703a 	wrctl	status,r2
+  return context;
+ 801e6c8:	e0bff917 	ldw	r2,-28(fp)
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+ 801e6cc:	e0bffd15 	stw	r2,-12(fp)
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+ 801e6d0:	e0bff117 	ldw	r2,-60(fp)
+ 801e6d4:	10800317 	ldw	r2,12(r2)
+ 801e6d8:	10800104 	addi	r2,r2,4
+ 801e6dc:	e0fffe17 	ldw	r3,-8(fp)
+ 801e6e0:	10c00035 	stwio	r3,0(r2)
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+ 801e6e4:	e0bff117 	ldw	r2,-60(fp)
+ 801e6e8:	10800317 	ldw	r2,12(r2)
+ 801e6ec:	e0fff117 	ldw	r3,-60(fp)
+ 801e6f0:	18c00317 	ldw	r3,12(r3)
+ 801e6f4:	18c00037 	ldwio	r3,0(r3)
+ 801e6f8:	10c00035 	stwio	r3,0(r2)
+ 801e6fc:	e0bffd17 	ldw	r2,-12(fp)
+ 801e700:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801e704:	e0bffa17 	ldw	r2,-24(fp)
+ 801e708:	1001703a 	wrctl	status,r2
+        dev->csr_base, 
+        IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+    alt_irq_enable_all(context);
+
+    if (NULL != standard_desc && NULL == extended_desc)
+ 801e70c:	e0bff017 	ldw	r2,-64(fp)
+ 801e710:	10001e26 	beq	r2,zero,801e78c <alt_msgdma_descriptor_async_transfer+0x190>
+ 801e714:	e0bfef17 	ldw	r2,-68(fp)
+ 801e718:	10001c1e 	bne	r2,zero,801e78c <alt_msgdma_descriptor_async_transfer+0x190>
+    {
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+      write is succeed*/
+        while(0 != alt_msgdma_write_standard_descriptor (
+ 801e71c:	00001106 	br	801e764 <alt_msgdma_descriptor_async_transfer+0x168>
+        dev->csr_base, dev->descriptor_base, standard_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+ 801e720:	01000044 	movi	r4,1
+ 801e724:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801e728:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801e72c:	1084e230 	cmpltui	r2,r2,5000
+ 801e730:	1000091e 	bne	r2,zero,801e758 <alt_msgdma_descriptor_async_transfer+0x15c>
+            {
+                alt_printf("time out after 5 msec while waiting" 
+ 801e734:	01020174 	movhi	r4,2053
+ 801e738:	21254e04 	addi	r4,r4,-27336
+ 801e73c:	8037a9c0 	call	8037a9c <alt_printf>
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+ 801e740:	e0bff117 	ldw	r2,-60(fp)
+ 801e744:	10801817 	ldw	r2,96(r2)
+ 801e748:	1009883a 	mov	r4,r2
+ 801e74c:	8015d840 	call	8015d84 <OSSemPost>
+                
+                return -ETIME;
+ 801e750:	00bff084 	movi	r2,-62
+ 801e754:	00007306 	br	801e924 <alt_msgdma_descriptor_async_transfer+0x328>
+            }
+            counter++; 
+ 801e758:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801e75c:	10800044 	addi	r2,r2,1
+ 801e760:	e0bfff8d 	sth	r2,-2(fp)
+        while(0 != alt_msgdma_write_standard_descriptor (
+ 801e764:	e0bff117 	ldw	r2,-60(fp)
+ 801e768:	10c00317 	ldw	r3,12(r2)
+ 801e76c:	e0bff117 	ldw	r2,-60(fp)
+ 801e770:	10800417 	ldw	r2,16(r2)
+ 801e774:	e1bff017 	ldw	r6,-64(fp)
+ 801e778:	100b883a 	mov	r5,r2
+ 801e77c:	1809883a 	mov	r4,r3
+ 801e780:	801e0d80 	call	801e0d8 <alt_msgdma_write_standard_descriptor>
+ 801e784:	103fe61e 	bne	r2,zero,801e720 <alt_msgdma_descriptor_async_transfer+0x124>
+    if (NULL != standard_desc && NULL == extended_desc)
+ 801e788:	00002706 	br	801e828 <alt_msgdma_descriptor_async_transfer+0x22c>
+        }
+    }
+    else if (NULL == standard_desc && NULL != extended_desc)
+ 801e78c:	e0bff017 	ldw	r2,-64(fp)
+ 801e790:	10001f1e 	bne	r2,zero,801e810 <alt_msgdma_descriptor_async_transfer+0x214>
+ 801e794:	e0bfef17 	ldw	r2,-68(fp)
+ 801e798:	10001d26 	beq	r2,zero,801e810 <alt_msgdma_descriptor_async_transfer+0x214>
+    {
+        counter = 0; /* reset counter */
+ 801e79c:	e03fff8d 	sth	zero,-2(fp)
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+      write is succeed*/
+        while(0 != alt_msgdma_write_extended_descriptor (
+ 801e7a0:	00001106 	br	801e7e8 <alt_msgdma_descriptor_async_transfer+0x1ec>
+        dev->csr_base, 
+        dev->descriptor_base, 
+        extended_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+ 801e7a4:	01000044 	movi	r4,1
+ 801e7a8:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801e7ac:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801e7b0:	1084e230 	cmpltui	r2,r2,5000
+ 801e7b4:	1000091e 	bne	r2,zero,801e7dc <alt_msgdma_descriptor_async_transfer+0x1e0>
+            {
+                alt_printf("time out after 5 msec while waiting free FIFO buffer" 
+ 801e7b8:	01020174 	movhi	r4,2053
+ 801e7bc:	21256404 	addi	r4,r4,-27248
+ 801e7c0:	8037a9c0 	call	8037a9c <alt_printf>
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+ 801e7c4:	e0bff117 	ldw	r2,-60(fp)
+ 801e7c8:	10801817 	ldw	r2,96(r2)
+ 801e7cc:	1009883a 	mov	r4,r2
+ 801e7d0:	8015d840 	call	8015d84 <OSSemPost>
+                
+                return -ETIME;
+ 801e7d4:	00bff084 	movi	r2,-62
+ 801e7d8:	00005206 	br	801e924 <alt_msgdma_descriptor_async_transfer+0x328>
+            }
+            counter++; 
+ 801e7dc:	e0bfff8b 	ldhu	r2,-2(fp)
+ 801e7e0:	10800044 	addi	r2,r2,1
+ 801e7e4:	e0bfff8d 	sth	r2,-2(fp)
+        while(0 != alt_msgdma_write_extended_descriptor (
+ 801e7e8:	e0bff117 	ldw	r2,-60(fp)
+ 801e7ec:	10c00317 	ldw	r3,12(r2)
+ 801e7f0:	e0bff117 	ldw	r2,-60(fp)
+ 801e7f4:	10800417 	ldw	r2,16(r2)
+ 801e7f8:	e1bfef17 	ldw	r6,-68(fp)
+ 801e7fc:	100b883a 	mov	r5,r2
+ 801e800:	1809883a 	mov	r4,r3
+ 801e804:	801e16c0 	call	801e16c <alt_msgdma_write_extended_descriptor>
+ 801e808:	103fe61e 	bne	r2,zero,801e7a4 <alt_msgdma_descriptor_async_transfer+0x1a8>
+    else if (NULL == standard_desc && NULL != extended_desc)
+ 801e80c:	00000606 	br	801e828 <alt_msgdma_descriptor_async_transfer+0x22c>
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+ 801e810:	e0bff117 	ldw	r2,-60(fp)
+ 801e814:	10801817 	ldw	r2,96(r2)
+ 801e818:	1009883a 	mov	r4,r2
+ 801e81c:	8015d840 	call	8015d84 <OSSemPost>
+        
+        /* operation not permitted due to descriptor type conflict */
+        return -EPERM; 
+ 801e820:	00bfffc4 	movi	r2,-1
+ 801e824:	00003f06 	br	801e924 <alt_msgdma_descriptor_async_transfer+0x328>
+    * If a callback routine has been previously registered which will be
+    * called from the msgdma ISR. Set up controller to:
+    *  - Run
+    *  - Stop on an error with any particular descriptor
+    */
+    if(dev->callback)
+ 801e828:	e0bff117 	ldw	r2,-60(fp)
+ 801e82c:	10800b17 	ldw	r2,44(r2)
+ 801e830:	10001c26 	beq	r2,zero,801e8a4 <alt_msgdma_descriptor_async_transfer+0x2a8>
+    {
+
+        control |= (dev->control |
+ 801e834:	e0bff117 	ldw	r2,-60(fp)
+ 801e838:	10c00d17 	ldw	r3,52(r2)
+ 801e83c:	e0bffe17 	ldw	r2,-8(fp)
+ 801e840:	1884b03a 	or	r2,r3,r2
+ 801e844:	10800514 	ori	r2,r2,20
+ 801e848:	e0bffe15 	stw	r2,-8(fp)
+                    ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK |
+                    ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK );
+        control &=  (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+ 801e84c:	e0fffe17 	ldw	r3,-8(fp)
+ 801e850:	00bff7c4 	movi	r2,-33
+ 801e854:	1884703a 	and	r2,r3,r2
+ 801e858:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 801e85c:	0005303a 	rdctl	r2,status
+ 801e860:	e0bff515 	stw	r2,-44(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801e864:	e0fff517 	ldw	r3,-44(fp)
+ 801e868:	00bfff84 	movi	r2,-2
+ 801e86c:	1884703a 	and	r2,r3,r2
+ 801e870:	1001703a 	wrctl	status,r2
+  return context;
+ 801e874:	e0bff517 	ldw	r2,-44(fp)
+    /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all(); 
+ 801e878:	e0bffd15 	stw	r2,-12(fp)
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+ 801e87c:	e0bff117 	ldw	r2,-60(fp)
+ 801e880:	10800317 	ldw	r2,12(r2)
+ 801e884:	10800104 	addi	r2,r2,4
+ 801e888:	e0fffe17 	ldw	r3,-8(fp)
+ 801e88c:	10c00035 	stwio	r3,0(r2)
+ 801e890:	e0bffd17 	ldw	r2,-12(fp)
+ 801e894:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801e898:	e0bff617 	ldw	r2,-40(fp)
+ 801e89c:	1001703a 	wrctl	status,r2
+ 801e8a0:	00001b06 	br	801e910 <alt_msgdma_descriptor_async_transfer+0x314>
+    *   - Stop on an error with any particular descriptor
+    *   - Disable interrupt generation
+    */
+    else
+    {
+        control |= (dev->control |
+ 801e8a4:	e0bff117 	ldw	r2,-60(fp)
+ 801e8a8:	10c00d17 	ldw	r3,52(r2)
+ 801e8ac:	e0bffe17 	ldw	r2,-8(fp)
+ 801e8b0:	1884b03a 	or	r2,r3,r2
+ 801e8b4:	10800114 	ori	r2,r2,4
+ 801e8b8:	e0bffe15 	stw	r2,-8(fp)
+                    ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK );
+        control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) &
+ 801e8bc:	e0fffe17 	ldw	r3,-8(fp)
+ 801e8c0:	00bff3c4 	movi	r2,-49
+ 801e8c4:	1884703a 	and	r2,r3,r2
+ 801e8c8:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 801e8cc:	0005303a 	rdctl	r2,status
+ 801e8d0:	e0bff315 	stw	r2,-52(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801e8d4:	e0fff317 	ldw	r3,-52(fp)
+ 801e8d8:	00bfff84 	movi	r2,-2
+ 801e8dc:	1884703a 	and	r2,r3,r2
+ 801e8e0:	1001703a 	wrctl	status,r2
+  return context;
+ 801e8e4:	e0bff317 	ldw	r2,-52(fp)
+                   (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+        /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all();
+ 801e8e8:	e0bffd15 	stw	r2,-12(fp)
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+ 801e8ec:	e0bff117 	ldw	r2,-60(fp)
+ 801e8f0:	10800317 	ldw	r2,12(r2)
+ 801e8f4:	10800104 	addi	r2,r2,4
+ 801e8f8:	e0fffe17 	ldw	r3,-8(fp)
+ 801e8fc:	10c00035 	stwio	r3,0(r2)
+ 801e900:	e0bffd17 	ldw	r2,-12(fp)
+ 801e904:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801e908:	e0bff417 	ldw	r2,-48(fp)
+ 801e90c:	1001703a 	wrctl	status,r2
+
+    /*
+     * Now that access to the registers is complete, release the registers
+     * semaphore so that other threads can access the registers.
+     */
+    ALT_SEM_POST (dev->regs_lock);
+ 801e910:	e0bff117 	ldw	r2,-60(fp)
+ 801e914:	10801817 	ldw	r2,96(r2)
+ 801e918:	1009883a 	mov	r4,r2
+ 801e91c:	8015d840 	call	8015d84 <OSSemPost>
+    
+    return 0;
+ 801e920:	0005883a 	mov	r2,zero
+}
+ 801e924:	e037883a 	mov	sp,fp
+ 801e928:	dfc00117 	ldw	ra,4(sp)
+ 801e92c:	df000017 	ldw	fp,0(sp)
+ 801e930:	dec00204 	addi	sp,sp,8
+ 801e934:	f800283a 	ret
+
+0801e938 <alt_msgdma_descriptor_sync_transfer>:
+ */
+static int alt_msgdma_descriptor_sync_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc)
+{
+ 801e938:	deffed04 	addi	sp,sp,-76
+ 801e93c:	dfc01215 	stw	ra,72(sp)
+ 801e940:	df001115 	stw	fp,68(sp)
+ 801e944:	df001104 	addi	fp,sp,68
+ 801e948:	e13ff115 	stw	r4,-60(fp)
+ 801e94c:	e17ff015 	stw	r5,-64(fp)
+ 801e950:	e1bfef15 	stw	r6,-68(fp)
+    alt_u32 control=0;
+ 801e954:	e03ffb15 	stw	zero,-20(fp)
+    alt_irq_context context=0;
+ 801e958:	e03ffa15 	stw	zero,-24(fp)
+    alt_u32 csr_status = 0;
+ 801e95c:	e03fff15 	stw	zero,-4(fp)
+    alt_u16 counter = 0;
+ 801e960:	e03ffe8d 	sth	zero,-6(fp)
+    alt_u32 fifo_read_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e964:	e0bff117 	ldw	r2,-60(fp)
+ 801e968:	10800317 	ldw	r2,12(r2)
+ 801e96c:	10800204 	addi	r2,r2,8
+ 801e970:	10800037 	ldwio	r2,0(r2)
+    alt_u32 fifo_read_fill_level = (
+ 801e974:	10bfffcc 	andi	r2,r2,65535
+ 801e978:	e0bffd15 	stw	r2,-12(fp)
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+    alt_u32 fifo_write_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e97c:	e0bff117 	ldw	r2,-60(fp)
+ 801e980:	10800317 	ldw	r2,12(r2)
+ 801e984:	10800204 	addi	r2,r2,8
+ 801e988:	10800037 	ldwio	r2,0(r2)
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+ 801e98c:	1004d43a 	srli	r2,r2,16
+    alt_u32 fifo_write_fill_level = (
+ 801e990:	10bfffcc 	andi	r2,r2,65535
+ 801e994:	e0bffc15 	stw	r2,-16(fp)
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET;
+    alt_u32 error = ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK | 
+ 801e998:	00807804 	movi	r2,480
+ 801e99c:	e0bff915 	stw	r2,-28(fp)
+                    ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK |
+                    ALTERA_MSGDMA_CSR_STOP_STATE_MASK |
+                    ALTERA_MSGDMA_CSR_RESET_STATE_MASK;
+    
+    /* Wait for available FIFO buffer to store new descriptor*/
+    while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+ 801e9a0:	00001a06 	br	801ea0c <alt_msgdma_descriptor_sync_transfer+0xd4>
+        (dev->descriptor_fifo_depth <= fifo_read_fill_level))
+    { 
+        alt_busy_sleep(1); /* delay 1us */
+ 801e9a4:	01000044 	movi	r4,1
+ 801e9a8:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+        if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801e9ac:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801e9b0:	1084e230 	cmpltui	r2,r2,5000
+ 801e9b4:	1000051e 	bne	r2,zero,801e9cc <alt_msgdma_descriptor_sync_transfer+0x94>
+        {
+            alt_printf("time out after 5 msec while waiting free FIFO buffer"
+ 801e9b8:	01020174 	movhi	r4,2053
+ 801e9bc:	21257a04 	addi	r4,r4,-27160
+ 801e9c0:	8037a9c0 	call	8037a9c <alt_printf>
+                " for storing descriptor\n");
+            return -ETIME;
+ 801e9c4:	00bff084 	movi	r2,-62
+ 801e9c8:	0000d806 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+        }
+        counter++;  
+ 801e9cc:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801e9d0:	10800044 	addi	r2,r2,1
+ 801e9d4:	e0bffe8d 	sth	r2,-6(fp)
+        fifo_read_fill_level = (
+            IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e9d8:	e0bff117 	ldw	r2,-60(fp)
+ 801e9dc:	10800317 	ldw	r2,12(r2)
+ 801e9e0:	10800204 	addi	r2,r2,8
+ 801e9e4:	10800037 	ldwio	r2,0(r2)
+        fifo_read_fill_level = (
+ 801e9e8:	10bfffcc 	andi	r2,r2,65535
+ 801e9ec:	e0bffd15 	stw	r2,-12(fp)
+            ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+            ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+        fifo_write_fill_level = (
+            IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+ 801e9f0:	e0bff117 	ldw	r2,-60(fp)
+ 801e9f4:	10800317 	ldw	r2,12(r2)
+ 801e9f8:	10800204 	addi	r2,r2,8
+ 801e9fc:	10800037 	ldwio	r2,0(r2)
+            ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+ 801ea00:	1004d43a 	srli	r2,r2,16
+        fifo_write_fill_level = (
+ 801ea04:	10bfffcc 	andi	r2,r2,65535
+ 801ea08:	e0bffc15 	stw	r2,-16(fp)
+    while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+ 801ea0c:	e0bff117 	ldw	r2,-60(fp)
+ 801ea10:	10800917 	ldw	r2,36(r2)
+ 801ea14:	e0fffc17 	ldw	r3,-16(fp)
+ 801ea18:	18bfe22e 	bgeu	r3,r2,801e9a4 <alt_msgdma_descriptor_sync_transfer+0x6c>
+        (dev->descriptor_fifo_depth <= fifo_read_fill_level))
+ 801ea1c:	e0bff117 	ldw	r2,-60(fp)
+ 801ea20:	10800917 	ldw	r2,36(r2)
+    while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+ 801ea24:	e0fffd17 	ldw	r3,-12(fp)
+ 801ea28:	18bfde2e 	bgeu	r3,r2,801e9a4 <alt_msgdma_descriptor_sync_transfer+0x6c>
+
+     /*
+     * When running in a multi threaded environment, obtain the "regs_lock"
+     * semaphore. This ensures that accessing registers is thread-safe.
+     */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+ 801ea2c:	e0bff117 	ldw	r2,-60(fp)
+ 801ea30:	10801817 	ldw	r2,96(r2)
+ 801ea34:	e0bff715 	stw	r2,-36(fp)
+ 801ea38:	e03ff68d 	sth	zero,-38(fp)
+ 801ea3c:	e0bff68b 	ldhu	r2,-38(fp)
+ 801ea40:	e0fff2c4 	addi	r3,fp,-53
+ 801ea44:	180d883a 	mov	r6,r3
+ 801ea48:	100b883a 	mov	r5,r2
+ 801ea4c:	e13ff717 	ldw	r4,-36(fp)
+ 801ea50:	8015a600 	call	8015a60 <OSSemPend>
+  NIOS2_READ_STATUS (context);
+ 801ea54:	0005303a 	rdctl	r2,status
+ 801ea58:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801ea5c:	e0fff817 	ldw	r3,-32(fp)
+ 801ea60:	00bfff84 	movi	r2,-2
+ 801ea64:	1884703a 	and	r2,r3,r2
+ 801ea68:	1001703a 	wrctl	status,r2
+  return context;
+ 801ea6c:	e0bff817 	ldw	r2,-32(fp)
+    
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+ 801ea70:	e0bffa15 	stw	r2,-24(fp)
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base,
+ 801ea74:	e0bff117 	ldw	r2,-60(fp)
+ 801ea78:	10800317 	ldw	r2,12(r2)
+ 801ea7c:	10800104 	addi	r2,r2,4
+ 801ea80:	00c00804 	movi	r3,32
+ 801ea84:	10c00035 	stwio	r3,0(r2)
+        ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+ 801ea88:	e0bff117 	ldw	r2,-60(fp)
+ 801ea8c:	10800317 	ldw	r2,12(r2)
+ 801ea90:	e0fff117 	ldw	r3,-60(fp)
+ 801ea94:	18c00317 	ldw	r3,12(r3)
+ 801ea98:	18c00037 	ldwio	r3,0(r3)
+ 801ea9c:	10c00035 	stwio	r3,0(r2)
+        dev->csr_base, 
+        IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+
+    if (NULL != standard_desc && NULL == extended_desc)
+ 801eaa0:	e0bff017 	ldw	r2,-64(fp)
+ 801eaa4:	10001f26 	beq	r2,zero,801eb24 <alt_msgdma_descriptor_sync_transfer+0x1ec>
+ 801eaa8:	e0bfef17 	ldw	r2,-68(fp)
+ 801eaac:	10001d1e 	bne	r2,zero,801eb24 <alt_msgdma_descriptor_sync_transfer+0x1ec>
+    {
+        counter = 0; /* reset counter */
+ 801eab0:	e03ffe8d 	sth	zero,-6(fp)
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+          write is succeed*/
+        while(0 != alt_msgdma_write_standard_descriptor (
+ 801eab4:	00001106 	br	801eafc <alt_msgdma_descriptor_sync_transfer+0x1c4>
+            dev->csr_base, dev->descriptor_base, standard_desc))
+        {     
+            alt_busy_sleep(1); /* delay 1us */
+ 801eab8:	01000044 	movi	r4,1
+ 801eabc:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801eac0:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801eac4:	1084e230 	cmpltui	r2,r2,5000
+ 801eac8:	1000091e 	bne	r2,zero,801eaf0 <alt_msgdma_descriptor_sync_transfer+0x1b8>
+            {
+                alt_printf("time out after 5 msec while writing standard" 
+ 801eacc:	01020174 	movhi	r4,2053
+ 801ead0:	21258e04 	addi	r4,r4,-27080
+ 801ead4:	8037a9c0 	call	8037a9c <alt_printf>
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+ 801ead8:	e0bff117 	ldw	r2,-60(fp)
+ 801eadc:	10801817 	ldw	r2,96(r2)
+ 801eae0:	1009883a 	mov	r4,r2
+ 801eae4:	8015d840 	call	8015d84 <OSSemPost>
+                
+                return -ETIME;
+ 801eae8:	00bff084 	movi	r2,-62
+ 801eaec:	00008f06 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+            }
+            counter++;    
+ 801eaf0:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801eaf4:	10800044 	addi	r2,r2,1
+ 801eaf8:	e0bffe8d 	sth	r2,-6(fp)
+        while(0 != alt_msgdma_write_standard_descriptor (
+ 801eafc:	e0bff117 	ldw	r2,-60(fp)
+ 801eb00:	10c00317 	ldw	r3,12(r2)
+ 801eb04:	e0bff117 	ldw	r2,-60(fp)
+ 801eb08:	10800417 	ldw	r2,16(r2)
+ 801eb0c:	e1bff017 	ldw	r6,-64(fp)
+ 801eb10:	100b883a 	mov	r5,r2
+ 801eb14:	1809883a 	mov	r4,r3
+ 801eb18:	801e0d80 	call	801e0d8 <alt_msgdma_write_standard_descriptor>
+ 801eb1c:	103fe61e 	bne	r2,zero,801eab8 <alt_msgdma_descriptor_sync_transfer+0x180>
+    if (NULL != standard_desc && NULL == extended_desc)
+ 801eb20:	00002706 	br	801ebc0 <alt_msgdma_descriptor_sync_transfer+0x288>
+        }
+    }
+    else if (NULL == standard_desc && NULL != extended_desc)
+ 801eb24:	e0bff017 	ldw	r2,-64(fp)
+ 801eb28:	10001f1e 	bne	r2,zero,801eba8 <alt_msgdma_descriptor_sync_transfer+0x270>
+ 801eb2c:	e0bfef17 	ldw	r2,-68(fp)
+ 801eb30:	10001d26 	beq	r2,zero,801eba8 <alt_msgdma_descriptor_sync_transfer+0x270>
+    {
+        counter = 0; /* reset counter */
+ 801eb34:	e03ffe8d 	sth	zero,-6(fp)
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+          write is succeed*/
+        while(0 != alt_msgdma_write_extended_descriptor (
+ 801eb38:	00001106 	br	801eb80 <alt_msgdma_descriptor_sync_transfer+0x248>
+            dev->csr_base, dev->descriptor_base, extended_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+ 801eb3c:	01000044 	movi	r4,1
+ 801eb40:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801eb44:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801eb48:	1084e230 	cmpltui	r2,r2,5000
+ 801eb4c:	1000091e 	bne	r2,zero,801eb74 <alt_msgdma_descriptor_sync_transfer+0x23c>
+            {
+                alt_printf("time out after 5 msec while writing extended" 
+ 801eb50:	01020174 	movhi	r4,2053
+ 801eb54:	21259f04 	addi	r4,r4,-27012
+ 801eb58:	8037a9c0 	call	8037a9c <alt_printf>
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+ 801eb5c:	e0bff117 	ldw	r2,-60(fp)
+ 801eb60:	10801817 	ldw	r2,96(r2)
+ 801eb64:	1009883a 	mov	r4,r2
+ 801eb68:	8015d840 	call	8015d84 <OSSemPost>
+                
+                return -ETIME;
+ 801eb6c:	00bff084 	movi	r2,-62
+ 801eb70:	00006e06 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+            }
+            counter++;
+ 801eb74:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801eb78:	10800044 	addi	r2,r2,1
+ 801eb7c:	e0bffe8d 	sth	r2,-6(fp)
+        while(0 != alt_msgdma_write_extended_descriptor (
+ 801eb80:	e0bff117 	ldw	r2,-60(fp)
+ 801eb84:	10c00317 	ldw	r3,12(r2)
+ 801eb88:	e0bff117 	ldw	r2,-60(fp)
+ 801eb8c:	10800417 	ldw	r2,16(r2)
+ 801eb90:	e1bfef17 	ldw	r6,-68(fp)
+ 801eb94:	100b883a 	mov	r5,r2
+ 801eb98:	1809883a 	mov	r4,r3
+ 801eb9c:	801e16c0 	call	801e16c <alt_msgdma_write_extended_descriptor>
+ 801eba0:	103fe61e 	bne	r2,zero,801eb3c <alt_msgdma_descriptor_sync_transfer+0x204>
+    else if (NULL == standard_desc && NULL != extended_desc)
+ 801eba4:	00000606 	br	801ebc0 <alt_msgdma_descriptor_sync_transfer+0x288>
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+ 801eba8:	e0bff117 	ldw	r2,-60(fp)
+ 801ebac:	10801817 	ldw	r2,96(r2)
+ 801ebb0:	1009883a 	mov	r4,r2
+ 801ebb4:	8015d840 	call	8015d84 <OSSemPost>
+        
+        /* operation not permitted due to descriptor type conflict */
+        return -EPERM; 
+ 801ebb8:	00bfffc4 	movi	r2,-1
+ 801ebbc:	00005b06 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+    * Set up msgdma controller to:
+    * - Disable interrupt generation
+    * - Run once a valid descriptor is written to controller
+    * - Stop on an error with any particular descriptor
+    */
+     IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base,
+ 801ebc0:	e0bff117 	ldw	r2,-60(fp)
+ 801ebc4:	10800317 	ldw	r2,12(r2)
+ 801ebc8:	10800104 	addi	r2,r2,4
+ 801ebcc:	e0fff117 	ldw	r3,-60(fp)
+ 801ebd0:	19000d17 	ldw	r4,52(r3)
+ 801ebd4:	00fff2c4 	movi	r3,-53
+ 801ebd8:	20c6703a 	and	r3,r4,r3
+ 801ebdc:	18c00114 	ori	r3,r3,4
+ 801ebe0:	10c00035 	stwio	r3,0(r2)
+ 801ebe4:	e0bffa17 	ldw	r2,-24(fp)
+ 801ebe8:	e0bff515 	stw	r2,-44(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801ebec:	e0bff517 	ldw	r2,-44(fp)
+ 801ebf0:	1001703a 	wrctl	status,r2
+        (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) &
+        (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK)) ;
+     
+    alt_irq_enable_all(context);
+     
+    counter = 0; /* reset counter */ 
+ 801ebf4:	e03ffe8d 	sth	zero,-6(fp)
+    
+    csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base);
+ 801ebf8:	e0bff117 	ldw	r2,-60(fp)
+ 801ebfc:	10800317 	ldw	r2,12(r2)
+ 801ec00:	10800037 	ldwio	r2,0(r2)
+ 801ec04:	e0bfff15 	stw	r2,-4(fp)
+    
+    /* Wait for any pending transfers to complete or checking any errors or 
+    conditions causing descriptor to stop dispatching */
+    while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK))
+ 801ec08:	00001506 	br	801ec60 <alt_msgdma_descriptor_sync_transfer+0x328>
+    {
+        alt_busy_sleep(1); /* delay 1us */
+ 801ec0c:	01000044 	movi	r4,1
+ 801ec10:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+        if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+ 801ec14:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801ec18:	1084e230 	cmpltui	r2,r2,5000
+ 801ec1c:	1000091e 	bne	r2,zero,801ec44 <alt_msgdma_descriptor_sync_transfer+0x30c>
+        {
+            alt_printf("time out after 5 msec while waiting for any pending" 
+ 801ec20:	01020174 	movhi	r4,2053
+ 801ec24:	2125b004 	addi	r4,r4,-26944
+ 801ec28:	8037a9c0 	call	8037a9c <alt_printf>
+            
+            /*
+            * Now that access to the registers is complete, release the registers
+            * semaphore so that other threads can access the registers.
+            */
+            ALT_SEM_POST (dev->regs_lock);
+ 801ec2c:	e0bff117 	ldw	r2,-60(fp)
+ 801ec30:	10801817 	ldw	r2,96(r2)
+ 801ec34:	1009883a 	mov	r4,r2
+ 801ec38:	8015d840 	call	8015d84 <OSSemPost>
+            
+            return -ETIME;
+ 801ec3c:	00bff084 	movi	r2,-62
+ 801ec40:	00003a06 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+        }
+        counter++;
+ 801ec44:	e0bffe8b 	ldhu	r2,-6(fp)
+ 801ec48:	10800044 	addi	r2,r2,1
+ 801ec4c:	e0bffe8d 	sth	r2,-6(fp)
+        csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base);
+ 801ec50:	e0bff117 	ldw	r2,-60(fp)
+ 801ec54:	10800317 	ldw	r2,12(r2)
+ 801ec58:	10800037 	ldwio	r2,0(r2)
+ 801ec5c:	e0bfff15 	stw	r2,-4(fp)
+    while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK))
+ 801ec60:	e0ffff17 	ldw	r3,-4(fp)
+ 801ec64:	e0bff917 	ldw	r2,-28(fp)
+ 801ec68:	1884703a 	and	r2,r3,r2
+ 801ec6c:	1000031e 	bne	r2,zero,801ec7c <alt_msgdma_descriptor_sync_transfer+0x344>
+ 801ec70:	e0bfff17 	ldw	r2,-4(fp)
+ 801ec74:	1080004c 	andi	r2,r2,1
+ 801ec78:	103fe41e 	bne	r2,zero,801ec0c <alt_msgdma_descriptor_sync_transfer+0x2d4>
+    }
+    
+
+    /*Errors or conditions causing the dispatcher stopping issuing read/write 
+      commands to masters*/
+    if(0 != (csr_status & error))
+ 801ec7c:	e0ffff17 	ldw	r3,-4(fp)
+ 801ec80:	e0bff917 	ldw	r2,-28(fp)
+ 801ec84:	1884703a 	and	r2,r3,r2
+ 801ec88:	10000626 	beq	r2,zero,801eca4 <alt_msgdma_descriptor_sync_transfer+0x36c>
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+ 801ec8c:	e0bff117 	ldw	r2,-60(fp)
+ 801ec90:	10801817 	ldw	r2,96(r2)
+ 801ec94:	1009883a 	mov	r4,r2
+ 801ec98:	8015d840 	call	8015d84 <OSSemPost>
+        
+        return error;
+ 801ec9c:	e0bff917 	ldw	r2,-28(fp)
+ 801eca0:	00002206 	br	801ed2c <alt_msgdma_descriptor_sync_transfer+0x3f4>
+    }
+
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* stop issuing more descriptors */
+    control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) | 
+ 801eca4:	e0bff117 	ldw	r2,-60(fp)
+ 801eca8:	10800317 	ldw	r2,12(r2)
+ 801ecac:	10800104 	addi	r2,r2,4
+ 801ecb0:	10800037 	ldwio	r2,0(r2)
+ 801ecb4:	10800814 	ori	r2,r2,32
+ 801ecb8:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_READ_STATUS (context);
+ 801ecbc:	0005303a 	rdctl	r2,status
+ 801ecc0:	e0bff315 	stw	r2,-52(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801ecc4:	e0fff317 	ldw	r3,-52(fp)
+ 801ecc8:	00bfff84 	movi	r2,-2
+ 801eccc:	1884703a 	and	r2,r3,r2
+ 801ecd0:	1001703a 	wrctl	status,r2
+  return context;
+ 801ecd4:	e0bff317 	ldw	r2,-52(fp)
+    ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();  
+ 801ecd8:	e0bffa15 	stw	r2,-24(fp)
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+ 801ecdc:	e0bff117 	ldw	r2,-60(fp)
+ 801ece0:	10800317 	ldw	r2,12(r2)
+ 801ece4:	10800104 	addi	r2,r2,4
+ 801ece8:	e0fffb17 	ldw	r3,-20(fp)
+ 801ecec:	10c00035 	stwio	r3,0(r2)
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+ 801ecf0:	e0bff117 	ldw	r2,-60(fp)
+ 801ecf4:	10800317 	ldw	r2,12(r2)
+ 801ecf8:	e0fff117 	ldw	r3,-60(fp)
+ 801ecfc:	18c00317 	ldw	r3,12(r3)
+ 801ed00:	18c00037 	ldwio	r3,0(r3)
+ 801ed04:	10c00035 	stwio	r3,0(r2)
+ 801ed08:	e0bffa17 	ldw	r2,-24(fp)
+ 801ed0c:	e0bff415 	stw	r2,-48(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801ed10:	e0bff417 	ldw	r2,-48(fp)
+ 801ed14:	1001703a 	wrctl	status,r2
+
+    /*
+    * Now that access to the registers is complete, release the registers
+    * semaphore so that other threads can access the registers.
+    */
+    ALT_SEM_POST (dev->regs_lock);
+ 801ed18:	e0bff117 	ldw	r2,-60(fp)
+ 801ed1c:	10801817 	ldw	r2,96(r2)
+ 801ed20:	1009883a 	mov	r4,r2
+ 801ed24:	8015d840 	call	8015d84 <OSSemPost>
+    
+    return 0;
+ 801ed28:	0005883a 	mov	r2,zero
+
+}
+ 801ed2c:	e037883a 	mov	sp,fp
+ 801ed30:	dfc00117 	ldw	ra,4(sp)
+ 801ed34:	df000017 	ldw	fp,0(sp)
+ 801ed38:	dec00204 	addi	sp,sp,8
+ 801ed3c:	f800283a 	ret
+
+0801ed40 <alt_msgdma_construct_standard_st_to_mm_descriptor>:
+ */
+int alt_msgdma_construct_standard_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *write_address, alt_u32 length, alt_u32 control)
+{
+ 801ed40:	defff804 	addi	sp,sp,-32
+ 801ed44:	dfc00715 	stw	ra,28(sp)
+ 801ed48:	df000615 	stw	fp,24(sp)
+ 801ed4c:	df000604 	addi	fp,sp,24
+ 801ed50:	e13fff15 	stw	r4,-4(fp)
+ 801ed54:	e17ffe15 	stw	r5,-8(fp)
+ 801ed58:	e1bffd15 	stw	r6,-12(fp)
+ 801ed5c:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, NULL, 
+ 801ed60:	e0800217 	ldw	r2,8(fp)
+ 801ed64:	d8800115 	stw	r2,4(sp)
+ 801ed68:	e0bffc17 	ldw	r2,-16(fp)
+ 801ed6c:	d8800015 	stw	r2,0(sp)
+ 801ed70:	e1fffd17 	ldw	r7,-12(fp)
+ 801ed74:	000d883a 	mov	r6,zero
+ 801ed78:	e17ffe17 	ldw	r5,-8(fp)
+ 801ed7c:	e13fff17 	ldw	r4,-4(fp)
+ 801ed80:	801e41c0 	call	801e41c <alt_msgdma_construct_standard_descriptor>
+            write_address, length, control);
+}
+ 801ed84:	e037883a 	mov	sp,fp
+ 801ed88:	dfc00117 	ldw	ra,4(sp)
+ 801ed8c:	df000017 	ldw	fp,0(sp)
+ 801ed90:	dec00204 	addi	sp,sp,8
+ 801ed94:	f800283a 	ret
+
+0801ed98 <alt_msgdma_construct_standard_mm_to_st_descriptor>:
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address,
+    alt_u32 length,
+    alt_u32 control)
+{
+ 801ed98:	defff804 	addi	sp,sp,-32
+ 801ed9c:	dfc00715 	stw	ra,28(sp)
+ 801eda0:	df000615 	stw	fp,24(sp)
+ 801eda4:	df000604 	addi	fp,sp,24
+ 801eda8:	e13fff15 	stw	r4,-4(fp)
+ 801edac:	e17ffe15 	stw	r5,-8(fp)
+ 801edb0:	e1bffd15 	stw	r6,-12(fp)
+ 801edb4:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, 
+ 801edb8:	e0800217 	ldw	r2,8(fp)
+ 801edbc:	d8800115 	stw	r2,4(sp)
+ 801edc0:	e0bffc17 	ldw	r2,-16(fp)
+ 801edc4:	d8800015 	stw	r2,0(sp)
+ 801edc8:	000f883a 	mov	r7,zero
+ 801edcc:	e1bffd17 	ldw	r6,-12(fp)
+ 801edd0:	e17ffe17 	ldw	r5,-8(fp)
+ 801edd4:	e13fff17 	ldw	r4,-4(fp)
+ 801edd8:	801e41c0 	call	801e41c <alt_msgdma_construct_standard_descriptor>
+            NULL, length, control);
+
+}
+ 801eddc:	e037883a 	mov	sp,fp
+ 801ede0:	dfc00117 	ldw	ra,4(sp)
+ 801ede4:	df000017 	ldw	fp,0(sp)
+ 801ede8:	dec00204 	addi	sp,sp,8
+ 801edec:	f800283a 	ret
+
+0801edf0 <alt_msgdma_construct_standard_mm_to_mm_descriptor>:
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+ 801edf0:	defff804 	addi	sp,sp,-32
+ 801edf4:	dfc00715 	stw	ra,28(sp)
+ 801edf8:	df000615 	stw	fp,24(sp)
+ 801edfc:	df000604 	addi	fp,sp,24
+ 801ee00:	e13fff15 	stw	r4,-4(fp)
+ 801ee04:	e17ffe15 	stw	r5,-8(fp)
+ 801ee08:	e1bffd15 	stw	r6,-12(fp)
+ 801ee0c:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, 
+ 801ee10:	e0800317 	ldw	r2,12(fp)
+ 801ee14:	d8800115 	stw	r2,4(sp)
+ 801ee18:	e0800217 	ldw	r2,8(fp)
+ 801ee1c:	d8800015 	stw	r2,0(sp)
+ 801ee20:	e1fffc17 	ldw	r7,-16(fp)
+ 801ee24:	e1bffd17 	ldw	r6,-12(fp)
+ 801ee28:	e17ffe17 	ldw	r5,-8(fp)
+ 801ee2c:	e13fff17 	ldw	r4,-4(fp)
+ 801ee30:	801e41c0 	call	801e41c <alt_msgdma_construct_standard_descriptor>
+            write_address, length, control);
+}
+ 801ee34:	e037883a 	mov	sp,fp
+ 801ee38:	dfc00117 	ldw	ra,4(sp)
+ 801ee3c:	df000017 	ldw	fp,0(sp)
+ 801ee40:	dec00204 	addi	sp,sp,8
+ 801ee44:	f800283a 	ret
+
+0801ee48 <alt_msgdma_construct_extended_st_to_mm_descriptor>:
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 write_burst_count, 
+    alt_u16 write_stride)
+{
+ 801ee48:	defff004 	addi	sp,sp,-64
+ 801ee4c:	dfc00f15 	stw	ra,60(sp)
+ 801ee50:	df000e15 	stw	fp,56(sp)
+ 801ee54:	df000e04 	addi	fp,sp,56
+ 801ee58:	e13fff15 	stw	r4,-4(fp)
+ 801ee5c:	e17ffe15 	stw	r5,-8(fp)
+ 801ee60:	e1bffd15 	stw	r6,-12(fp)
+ 801ee64:	e1fffc15 	stw	r7,-16(fp)
+ 801ee68:	e1000317 	ldw	r4,12(fp)
+ 801ee6c:	e0c00417 	ldw	r3,16(fp)
+ 801ee70:	e0800517 	ldw	r2,20(fp)
+ 801ee74:	e13ffb0d 	sth	r4,-20(fp)
+ 801ee78:	e0fffa05 	stb	r3,-24(fp)
+ 801ee7c:	e0bff90d 	sth	r2,-28(fp)
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, 
+ 801ee80:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801ee84:	e0fffa03 	ldbu	r3,-24(fp)
+ 801ee88:	e13ff90b 	ldhu	r4,-28(fp)
+ 801ee8c:	d9000615 	stw	r4,24(sp)
+ 801ee90:	d8000515 	stw	zero,20(sp)
+ 801ee94:	d8c00415 	stw	r3,16(sp)
+ 801ee98:	d8000315 	stw	zero,12(sp)
+ 801ee9c:	d8800215 	stw	r2,8(sp)
+ 801eea0:	e0800217 	ldw	r2,8(fp)
+ 801eea4:	d8800115 	stw	r2,4(sp)
+ 801eea8:	e0bffc17 	ldw	r2,-16(fp)
+ 801eeac:	d8800015 	stw	r2,0(sp)
+ 801eeb0:	e1fffd17 	ldw	r7,-12(fp)
+ 801eeb4:	000d883a 	mov	r6,zero
+ 801eeb8:	e17ffe17 	ldw	r5,-8(fp)
+ 801eebc:	e13fff17 	ldw	r4,-4(fp)
+ 801eec0:	801e4a80 	call	801e4a8 <alt_msgdma_construct_extended_descriptor>
+            NULL, write_address, length, control, sequence_number, 0, 
+            write_burst_count, 0, write_stride);
+}
+ 801eec4:	e037883a 	mov	sp,fp
+ 801eec8:	dfc00117 	ldw	ra,4(sp)
+ 801eecc:	df000017 	ldw	fp,0(sp)
+ 801eed0:	dec00204 	addi	sp,sp,8
+ 801eed4:	f800283a 	ret
+
+0801eed8 <alt_msgdma_construct_extended_mm_to_st_descriptor>:
+    alt_u32 length,
+    alt_u32 control,
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride)
+{
+ 801eed8:	defff004 	addi	sp,sp,-64
+ 801eedc:	dfc00f15 	stw	ra,60(sp)
+ 801eee0:	df000e15 	stw	fp,56(sp)
+ 801eee4:	df000e04 	addi	fp,sp,56
+ 801eee8:	e13fff15 	stw	r4,-4(fp)
+ 801eeec:	e17ffe15 	stw	r5,-8(fp)
+ 801eef0:	e1bffd15 	stw	r6,-12(fp)
+ 801eef4:	e1fffc15 	stw	r7,-16(fp)
+ 801eef8:	e1000317 	ldw	r4,12(fp)
+ 801eefc:	e0c00417 	ldw	r3,16(fp)
+ 801ef00:	e0800517 	ldw	r2,20(fp)
+ 801ef04:	e13ffb0d 	sth	r4,-20(fp)
+ 801ef08:	e0fffa05 	stb	r3,-24(fp)
+ 801ef0c:	e0bff90d 	sth	r2,-28(fp)
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, read_address, 
+ 801ef10:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801ef14:	e0fffa03 	ldbu	r3,-24(fp)
+ 801ef18:	e13ff90b 	ldhu	r4,-28(fp)
+ 801ef1c:	d8000615 	stw	zero,24(sp)
+ 801ef20:	d9000515 	stw	r4,20(sp)
+ 801ef24:	d8000415 	stw	zero,16(sp)
+ 801ef28:	d8c00315 	stw	r3,12(sp)
+ 801ef2c:	d8800215 	stw	r2,8(sp)
+ 801ef30:	e0800217 	ldw	r2,8(fp)
+ 801ef34:	d8800115 	stw	r2,4(sp)
+ 801ef38:	e0bffc17 	ldw	r2,-16(fp)
+ 801ef3c:	d8800015 	stw	r2,0(sp)
+ 801ef40:	000f883a 	mov	r7,zero
+ 801ef44:	e1bffd17 	ldw	r6,-12(fp)
+ 801ef48:	e17ffe17 	ldw	r5,-8(fp)
+ 801ef4c:	e13fff17 	ldw	r4,-4(fp)
+ 801ef50:	801e4a80 	call	801e4a8 <alt_msgdma_construct_extended_descriptor>
+            NULL, length, control, sequence_number, read_burst_count, 0, 
+            read_stride, 0);
+
+}
+ 801ef54:	e037883a 	mov	sp,fp
+ 801ef58:	dfc00117 	ldw	ra,4(sp)
+ 801ef5c:	df000017 	ldw	fp,0(sp)
+ 801ef60:	dec00204 	addi	sp,sp,8
+ 801ef64:	f800283a 	ret
+
+0801ef68 <alt_msgdma_construct_extended_mm_to_mm_descriptor>:
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+ 801ef68:	deffee04 	addi	sp,sp,-72
+ 801ef6c:	dfc01115 	stw	ra,68(sp)
+ 801ef70:	df001015 	stw	fp,64(sp)
+ 801ef74:	df001004 	addi	fp,sp,64
+ 801ef78:	e13fff15 	stw	r4,-4(fp)
+ 801ef7c:	e17ffe15 	stw	r5,-8(fp)
+ 801ef80:	e1bffd15 	stw	r6,-12(fp)
+ 801ef84:	e1fffc15 	stw	r7,-16(fp)
+ 801ef88:	e1800417 	ldw	r6,16(fp)
+ 801ef8c:	e1400517 	ldw	r5,20(fp)
+ 801ef90:	e1000617 	ldw	r4,24(fp)
+ 801ef94:	e0c00717 	ldw	r3,28(fp)
+ 801ef98:	e0800817 	ldw	r2,32(fp)
+ 801ef9c:	e1bffb0d 	sth	r6,-20(fp)
+ 801efa0:	e17ffa05 	stb	r5,-24(fp)
+ 801efa4:	e13ff905 	stb	r4,-28(fp)
+ 801efa8:	e0fff80d 	sth	r3,-32(fp)
+ 801efac:	e0bff70d 	sth	r2,-36(fp)
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, 
+ 801efb0:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801efb4:	e0fffa03 	ldbu	r3,-24(fp)
+ 801efb8:	e13ff903 	ldbu	r4,-28(fp)
+ 801efbc:	e17ff80b 	ldhu	r5,-32(fp)
+ 801efc0:	e1bff70b 	ldhu	r6,-36(fp)
+ 801efc4:	d9800615 	stw	r6,24(sp)
+ 801efc8:	d9400515 	stw	r5,20(sp)
+ 801efcc:	d9000415 	stw	r4,16(sp)
+ 801efd0:	d8c00315 	stw	r3,12(sp)
+ 801efd4:	d8800215 	stw	r2,8(sp)
+ 801efd8:	e0800317 	ldw	r2,12(fp)
+ 801efdc:	d8800115 	stw	r2,4(sp)
+ 801efe0:	e0800217 	ldw	r2,8(fp)
+ 801efe4:	d8800015 	stw	r2,0(sp)
+ 801efe8:	e1fffc17 	ldw	r7,-16(fp)
+ 801efec:	e1bffd17 	ldw	r6,-12(fp)
+ 801eff0:	e17ffe17 	ldw	r5,-8(fp)
+ 801eff4:	e13fff17 	ldw	r4,-4(fp)
+ 801eff8:	801e4a80 	call	801e4a8 <alt_msgdma_construct_extended_descriptor>
+            read_address, write_address, length, control, sequence_number, 
+            read_burst_count, write_burst_count, read_stride, write_stride);
+
+}
+ 801effc:	e037883a 	mov	sp,fp
+ 801f000:	dfc00117 	ldw	ra,4(sp)
+ 801f004:	df000017 	ldw	fp,0(sp)
+ 801f008:	dec00204 	addi	sp,sp,8
+ 801f00c:	f800283a 	ret
+
+0801f010 <alt_msgdma_construct_prefetcher_standard_descriptor>:
+    alt_msgdma_prefetcher_standard_descriptor *descriptor,
+    alt_u32 read_address, 
+    alt_u32 write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+ 801f010:	defffb04 	addi	sp,sp,-20
+ 801f014:	df000415 	stw	fp,16(sp)
+ 801f018:	df000404 	addi	fp,sp,16
+ 801f01c:	e13fff15 	stw	r4,-4(fp)
+ 801f020:	e17ffe15 	stw	r5,-8(fp)
+ 801f024:	e1bffd15 	stw	r6,-12(fp)
+ 801f028:	e1fffc15 	stw	r7,-16(fp)
+    if(dev->max_byte < length ||
+ 801f02c:	e0bfff17 	ldw	r2,-4(fp)
+ 801f030:	10c01217 	ldw	r3,72(r2)
+ 801f034:	e0800117 	ldw	r2,4(fp)
+ 801f038:	18800436 	bltu	r3,r2,801f04c <alt_msgdma_construct_prefetcher_standard_descriptor+0x3c>
+       dev->enhanced_features != 0
+ 801f03c:	e0bfff17 	ldw	r2,-4(fp)
+ 801f040:	10801703 	ldbu	r2,92(r2)
+    if(dev->max_byte < length ||
+ 801f044:	10803fcc 	andi	r2,r2,255
+ 801f048:	10000226 	beq	r2,zero,801f054 <alt_msgdma_construct_prefetcher_standard_descriptor+0x44>
+      )
+    {
+        return -EINVAL;
+ 801f04c:	00bffa84 	movi	r2,-22
+ 801f050:	00001406 	br	801f0a4 <alt_msgdma_construct_prefetcher_standard_descriptor+0x94>
+    }
+    descriptor->read_address = read_address;
+ 801f054:	e0bffe17 	ldw	r2,-8(fp)
+ 801f058:	e0fffd17 	ldw	r3,-12(fp)
+ 801f05c:	10c00015 	stw	r3,0(r2)
+    descriptor->write_address = write_address;
+ 801f060:	e0bffe17 	ldw	r2,-8(fp)
+ 801f064:	e0fffc17 	ldw	r3,-16(fp)
+ 801f068:	10c00115 	stw	r3,4(r2)
+    descriptor->transfer_length = length;
+ 801f06c:	e0bffe17 	ldw	r2,-8(fp)
+ 801f070:	e0c00117 	ldw	r3,4(fp)
+ 801f074:	10c00215 	stw	r3,8(r2)
+    /* have descriptor point to itself for park_mode */
+    descriptor->next_desc_ptr = (alt_u32)descriptor;  
+ 801f078:	e0fffe17 	ldw	r3,-8(fp)
+ 801f07c:	e0bffe17 	ldw	r2,-8(fp)
+ 801f080:	10c00315 	stw	r3,12(r2)
+    
+    /* clear control own_by_hw bit field (SW owns this descriptor)*/
+    descriptor->control = (control 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 801f084:	e0c00217 	ldw	r3,8(fp)
+ 801f088:	00900034 	movhi	r2,16384
+ 801f08c:	10bfffc4 	addi	r2,r2,-1
+ 801f090:	1884703a 	and	r2,r3,r2
+ 801f094:	10e00034 	orhi	r3,r2,32768
+    descriptor->control = (control 
+ 801f098:	e0bffe17 	ldw	r2,-8(fp)
+ 801f09c:	10c00715 	stw	r3,28(r2)
+    
+    return 0;
+ 801f0a0:	0005883a 	mov	r2,zero
+}
+ 801f0a4:	e037883a 	mov	sp,fp
+ 801f0a8:	df000017 	ldw	fp,0(sp)
+ 801f0ac:	dec00104 	addi	sp,sp,4
+ 801f0b0:	f800283a 	ret
+
+0801f0b4 <alt_msgdma_construct_prefetcher_extended_descriptor>:
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+ 801f0b4:	defff404 	addi	sp,sp,-48
+ 801f0b8:	df000b15 	stw	fp,44(sp)
+ 801f0bc:	df000b04 	addi	fp,sp,44
+ 801f0c0:	e13ffd15 	stw	r4,-12(fp)
+ 801f0c4:	e17ffc15 	stw	r5,-16(fp)
+ 801f0c8:	e1bffb15 	stw	r6,-20(fp)
+ 801f0cc:	e1fffa15 	stw	r7,-24(fp)
+ 801f0d0:	e1800517 	ldw	r6,20(fp)
+ 801f0d4:	e1400617 	ldw	r5,24(fp)
+ 801f0d8:	e1000717 	ldw	r4,28(fp)
+ 801f0dc:	e0c00817 	ldw	r3,32(fp)
+ 801f0e0:	e0800917 	ldw	r2,36(fp)
+ 801f0e4:	e1bff90d 	sth	r6,-28(fp)
+ 801f0e8:	e17ff805 	stb	r5,-32(fp)
+ 801f0ec:	e13ff705 	stb	r4,-36(fp)
+ 801f0f0:	e0fff60d 	sth	r3,-40(fp)
+ 801f0f4:	e0bff50d 	sth	r2,-44(fp)
+    msgdma_addr64 node_addr;
+    
+    if(dev->max_byte < length ||
+ 801f0f8:	e0bffd17 	ldw	r2,-12(fp)
+ 801f0fc:	10c01217 	ldw	r3,72(r2)
+ 801f100:	e0800317 	ldw	r2,12(fp)
+ 801f104:	18801936 	bltu	r3,r2,801f16c <alt_msgdma_construct_prefetcher_extended_descriptor+0xb8>
+       dev->max_stride < read_stride ||
+ 801f108:	e13ffd17 	ldw	r4,-12(fp)
+ 801f10c:	20801317 	ldw	r2,76(r4)
+ 801f110:	20c01417 	ldw	r3,80(r4)
+ 801f114:	e13ff60b 	ldhu	r4,-40(fp)
+ 801f118:	213fffcc 	andi	r4,r4,65535
+ 801f11c:	2015883a 	mov	r10,r4
+ 801f120:	0017883a 	mov	r11,zero
+    if(dev->max_byte < length ||
+ 801f124:	1ac01136 	bltu	r3,r11,801f16c <alt_msgdma_construct_prefetcher_extended_descriptor+0xb8>
+ 801f128:	58c0011e 	bne	r11,r3,801f130 <alt_msgdma_construct_prefetcher_extended_descriptor+0x7c>
+ 801f12c:	12800f36 	bltu	r2,r10,801f16c <alt_msgdma_construct_prefetcher_extended_descriptor+0xb8>
+       dev->max_stride < write_stride ||
+ 801f130:	e13ffd17 	ldw	r4,-12(fp)
+ 801f134:	20801317 	ldw	r2,76(r4)
+ 801f138:	20c01417 	ldw	r3,80(r4)
+ 801f13c:	e13ff50b 	ldhu	r4,-44(fp)
+ 801f140:	213fffcc 	andi	r4,r4,65535
+ 801f144:	2011883a 	mov	r8,r4
+ 801f148:	0013883a 	mov	r9,zero
+       dev->max_stride < read_stride ||
+ 801f14c:	1a400736 	bltu	r3,r9,801f16c <alt_msgdma_construct_prefetcher_extended_descriptor+0xb8>
+ 801f150:	48c0011e 	bne	r9,r3,801f158 <alt_msgdma_construct_prefetcher_extended_descriptor+0xa4>
+ 801f154:	12000536 	bltu	r2,r8,801f16c <alt_msgdma_construct_prefetcher_extended_descriptor+0xb8>
+       dev->enhanced_features != 1 
+ 801f158:	e0bffd17 	ldw	r2,-12(fp)
+ 801f15c:	10801703 	ldbu	r2,92(r2)
+       dev->max_stride < write_stride ||
+ 801f160:	10803fcc 	andi	r2,r2,255
+ 801f164:	10800060 	cmpeqi	r2,r2,1
+ 801f168:	1000021e 	bne	r2,zero,801f174 <alt_msgdma_construct_prefetcher_extended_descriptor+0xc0>
+      )
+    {
+        return -EINVAL;
+ 801f16c:	00bffa84 	movi	r2,-22
+ 801f170:	00003106 	br	801f238 <alt_msgdma_construct_prefetcher_extended_descriptor+0x184>
+    }
+    
+    descriptor->read_address_high = read_address_high;
+ 801f174:	e0bffc17 	ldw	r2,-16(fp)
+ 801f178:	e0fffb17 	ldw	r3,-20(fp)
+ 801f17c:	10c00915 	stw	r3,36(r2)
+    descriptor->read_address_low = read_address_low;
+ 801f180:	e0bffc17 	ldw	r2,-16(fp)
+ 801f184:	e0fffa17 	ldw	r3,-24(fp)
+ 801f188:	10c00015 	stw	r3,0(r2)
+    descriptor->write_address_high = write_address_high;
+ 801f18c:	e0bffc17 	ldw	r2,-16(fp)
+ 801f190:	e0c00117 	ldw	r3,4(fp)
+ 801f194:	10c00a15 	stw	r3,40(r2)
+    descriptor->write_address_low = write_address_low;
+ 801f198:	e0bffc17 	ldw	r2,-16(fp)
+ 801f19c:	e0c00217 	ldw	r3,8(fp)
+ 801f1a0:	10c00115 	stw	r3,4(r2)
+    descriptor->transfer_length = length;
+ 801f1a4:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1a8:	e0c00317 	ldw	r3,12(fp)
+ 801f1ac:	10c00215 	stw	r3,8(r2)
+    descriptor->sequence_number = sequence_number;
+ 801f1b0:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1b4:	e0fff90b 	ldhu	r3,-28(fp)
+ 801f1b8:	10c0070d 	sth	r3,28(r2)
+    descriptor->read_burst_count = read_burst_count;
+ 801f1bc:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1c0:	e0fff803 	ldbu	r3,-32(fp)
+ 801f1c4:	10c00785 	stb	r3,30(r2)
+    descriptor->write_burst_count = write_burst_count;
+ 801f1c8:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1cc:	e0fff703 	ldbu	r3,-36(fp)
+ 801f1d0:	10c007c5 	stb	r3,31(r2)
+    descriptor->read_stride = read_stride;
+ 801f1d4:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1d8:	e0fff60b 	ldhu	r3,-40(fp)
+ 801f1dc:	10c0080d 	sth	r3,32(r2)
+    descriptor->write_stride = write_stride;
+ 801f1e0:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1e4:	e0fff50b 	ldhu	r3,-44(fp)
+ 801f1e8:	10c0088d 	sth	r3,34(r2)
+    /* have descriptor point to itself */
+    node_addr.u64 = (uintptr_t)descriptor;
+ 801f1ec:	e0bffc17 	ldw	r2,-16(fp)
+ 801f1f0:	1019883a 	mov	r12,r2
+ 801f1f4:	001b883a 	mov	r13,zero
+ 801f1f8:	e33ffe15 	stw	r12,-8(fp)
+ 801f1fc:	e37fff15 	stw	r13,-4(fp)
+    descriptor->next_desc_ptr_low = node_addr.u32[0];  
+ 801f200:	e0fffe17 	ldw	r3,-8(fp)
+ 801f204:	e0bffc17 	ldw	r2,-16(fp)
+ 801f208:	10c00315 	stw	r3,12(r2)
+    descriptor->next_desc_ptr_high = node_addr.u32[1];
+ 801f20c:	e0ffff17 	ldw	r3,-4(fp)
+ 801f210:	e0bffc17 	ldw	r2,-16(fp)
+ 801f214:	10c00b15 	stw	r3,44(r2)
+    
+    /* clear control own_by_hw bit field (SW still owns this descriptor). */
+    descriptor->control = (control 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 801f218:	e0c00417 	ldw	r3,16(fp)
+ 801f21c:	00900034 	movhi	r2,16384
+ 801f220:	10bfffc4 	addi	r2,r2,-1
+ 801f224:	1884703a 	and	r2,r3,r2
+ 801f228:	10e00034 	orhi	r3,r2,32768
+    descriptor->control = (control 
+ 801f22c:	e0bffc17 	ldw	r2,-16(fp)
+ 801f230:	10c00f15 	stw	r3,60(r2)
+
+  return 0 ;
+ 801f234:	0005883a 	mov	r2,zero
+}
+ 801f238:	e037883a 	mov	sp,fp
+ 801f23c:	df000017 	ldw	fp,0(sp)
+ 801f240:	dec00104 	addi	sp,sp,4
+ 801f244:	f800283a 	ret
+
+0801f248 <alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor>:
+    alt_msgdma_prefetcher_standard_descriptor *descriptor,
+    alt_u32 read_address,
+    alt_u32 write_address,
+    alt_u32 length,
+    alt_u32 control)
+{
+ 801f248:	defff804 	addi	sp,sp,-32
+ 801f24c:	dfc00715 	stw	ra,28(sp)
+ 801f250:	df000615 	stw	fp,24(sp)
+ 801f254:	df000604 	addi	fp,sp,24
+ 801f258:	e13fff15 	stw	r4,-4(fp)
+ 801f25c:	e17ffe15 	stw	r5,-8(fp)
+ 801f260:	e1bffd15 	stw	r6,-12(fp)
+ 801f264:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+ 801f268:	e0800317 	ldw	r2,12(fp)
+ 801f26c:	d8800115 	stw	r2,4(sp)
+ 801f270:	e0800217 	ldw	r2,8(fp)
+ 801f274:	d8800015 	stw	r2,0(sp)
+ 801f278:	e1fffc17 	ldw	r7,-16(fp)
+ 801f27c:	e1bffd17 	ldw	r6,-12(fp)
+ 801f280:	e17ffe17 	ldw	r5,-8(fp)
+ 801f284:	e13fff17 	ldw	r4,-4(fp)
+ 801f288:	801f0100 	call	801f010 <alt_msgdma_construct_prefetcher_standard_descriptor>
+            read_address, write_address, length, control);
+}
+ 801f28c:	e037883a 	mov	sp,fp
+ 801f290:	dfc00117 	ldw	ra,4(sp)
+ 801f294:	df000017 	ldw	fp,0(sp)
+ 801f298:	dec00204 	addi	sp,sp,8
+ 801f29c:	f800283a 	ret
+
+0801f2a0 <alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor>:
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+ 801f2a0:	defff804 	addi	sp,sp,-32
+ 801f2a4:	dfc00715 	stw	ra,28(sp)
+ 801f2a8:	df000615 	stw	fp,24(sp)
+ 801f2ac:	df000604 	addi	fp,sp,24
+ 801f2b0:	e13fff15 	stw	r4,-4(fp)
+ 801f2b4:	e17ffe15 	stw	r5,-8(fp)
+ 801f2b8:	e1bffd15 	stw	r6,-12(fp)
+ 801f2bc:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+ 801f2c0:	e0800217 	ldw	r2,8(fp)
+ 801f2c4:	d8800115 	stw	r2,4(sp)
+ 801f2c8:	e0bffc17 	ldw	r2,-16(fp)
+ 801f2cc:	d8800015 	stw	r2,0(sp)
+ 801f2d0:	e1fffd17 	ldw	r7,-12(fp)
+ 801f2d4:	000d883a 	mov	r6,zero
+ 801f2d8:	e17ffe17 	ldw	r5,-8(fp)
+ 801f2dc:	e13fff17 	ldw	r4,-4(fp)
+ 801f2e0:	801f0100 	call	801f010 <alt_msgdma_construct_prefetcher_standard_descriptor>
+            0, write_address, length, control);
+}
+ 801f2e4:	e037883a 	mov	sp,fp
+ 801f2e8:	dfc00117 	ldw	ra,4(sp)
+ 801f2ec:	df000017 	ldw	fp,0(sp)
+ 801f2f0:	dec00204 	addi	sp,sp,8
+ 801f2f4:	f800283a 	ret
+
+0801f2f8 <alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor>:
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 read_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+ 801f2f8:	defff804 	addi	sp,sp,-32
+ 801f2fc:	dfc00715 	stw	ra,28(sp)
+ 801f300:	df000615 	stw	fp,24(sp)
+ 801f304:	df000604 	addi	fp,sp,24
+ 801f308:	e13fff15 	stw	r4,-4(fp)
+ 801f30c:	e17ffe15 	stw	r5,-8(fp)
+ 801f310:	e1bffd15 	stw	r6,-12(fp)
+ 801f314:	e1fffc15 	stw	r7,-16(fp)
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+ 801f318:	e0800217 	ldw	r2,8(fp)
+ 801f31c:	d8800115 	stw	r2,4(sp)
+ 801f320:	e0bffc17 	ldw	r2,-16(fp)
+ 801f324:	d8800015 	stw	r2,0(sp)
+ 801f328:	000f883a 	mov	r7,zero
+ 801f32c:	e1bffd17 	ldw	r6,-12(fp)
+ 801f330:	e17ffe17 	ldw	r5,-8(fp)
+ 801f334:	e13fff17 	ldw	r4,-4(fp)
+ 801f338:	801f0100 	call	801f010 <alt_msgdma_construct_prefetcher_standard_descriptor>
+            read_address, 0, length, control);
+}
+ 801f33c:	e037883a 	mov	sp,fp
+ 801f340:	dfc00117 	ldw	ra,4(sp)
+ 801f344:	df000017 	ldw	fp,0(sp)
+ 801f348:	dec00204 	addi	sp,sp,8
+ 801f34c:	f800283a 	ret
+
+0801f350 <alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor>:
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number,
+    alt_u8 write_burst_count,
+    alt_u16 write_stride)
+{
+ 801f350:	deffee04 	addi	sp,sp,-72
+ 801f354:	dfc01115 	stw	ra,68(sp)
+ 801f358:	df001015 	stw	fp,64(sp)
+ 801f35c:	df001004 	addi	fp,sp,64
+ 801f360:	e13fff15 	stw	r4,-4(fp)
+ 801f364:	e17ffe15 	stw	r5,-8(fp)
+ 801f368:	e1bffd15 	stw	r6,-12(fp)
+ 801f36c:	e1fffc15 	stw	r7,-16(fp)
+ 801f370:	e1000417 	ldw	r4,16(fp)
+ 801f374:	e0c00517 	ldw	r3,20(fp)
+ 801f378:	e0800617 	ldw	r2,24(fp)
+ 801f37c:	e13ffb0d 	sth	r4,-20(fp)
+ 801f380:	e0fffa05 	stb	r3,-24(fp)
+ 801f384:	e0bff90d 	sth	r2,-28(fp)
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, 
+ 801f388:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801f38c:	e0fffa03 	ldbu	r3,-24(fp)
+ 801f390:	e13ff90b 	ldhu	r4,-28(fp)
+ 801f394:	d9000815 	stw	r4,32(sp)
+ 801f398:	d8000715 	stw	zero,28(sp)
+ 801f39c:	d8c00615 	stw	r3,24(sp)
+ 801f3a0:	d8000515 	stw	zero,20(sp)
+ 801f3a4:	d8800415 	stw	r2,16(sp)
+ 801f3a8:	e0800317 	ldw	r2,12(fp)
+ 801f3ac:	d8800315 	stw	r2,12(sp)
+ 801f3b0:	e0800217 	ldw	r2,8(fp)
+ 801f3b4:	d8800215 	stw	r2,8(sp)
+ 801f3b8:	e0bffc17 	ldw	r2,-16(fp)
+ 801f3bc:	d8800115 	stw	r2,4(sp)
+ 801f3c0:	e0bffd17 	ldw	r2,-12(fp)
+ 801f3c4:	d8800015 	stw	r2,0(sp)
+ 801f3c8:	000f883a 	mov	r7,zero
+ 801f3cc:	000d883a 	mov	r6,zero
+ 801f3d0:	e17ffe17 	ldw	r5,-8(fp)
+ 801f3d4:	e13fff17 	ldw	r4,-4(fp)
+ 801f3d8:	801f0b40 	call	801f0b4 <alt_msgdma_construct_prefetcher_extended_descriptor>
+            0, 0, write_address_high, write_address_low, length, control, 
+            sequence_number, 0, write_burst_count, 0, write_stride);
+}
+ 801f3dc:	e037883a 	mov	sp,fp
+ 801f3e0:	dfc00117 	ldw	ra,4(sp)
+ 801f3e4:	df000017 	ldw	fp,0(sp)
+ 801f3e8:	dec00204 	addi	sp,sp,8
+ 801f3ec:	f800283a 	ret
+
+0801f3f0 <alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor>:
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride)
+{
+ 801f3f0:	deffee04 	addi	sp,sp,-72
+ 801f3f4:	dfc01115 	stw	ra,68(sp)
+ 801f3f8:	df001015 	stw	fp,64(sp)
+ 801f3fc:	df001004 	addi	fp,sp,64
+ 801f400:	e13fff15 	stw	r4,-4(fp)
+ 801f404:	e17ffe15 	stw	r5,-8(fp)
+ 801f408:	e1bffd15 	stw	r6,-12(fp)
+ 801f40c:	e1fffc15 	stw	r7,-16(fp)
+ 801f410:	e1000417 	ldw	r4,16(fp)
+ 801f414:	e0c00517 	ldw	r3,20(fp)
+ 801f418:	e0800617 	ldw	r2,24(fp)
+ 801f41c:	e13ffb0d 	sth	r4,-20(fp)
+ 801f420:	e0fffa05 	stb	r3,-24(fp)
+ 801f424:	e0bff90d 	sth	r2,-28(fp)
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor,
+ 801f428:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801f42c:	e0fffa03 	ldbu	r3,-24(fp)
+ 801f430:	e13ff90b 	ldhu	r4,-28(fp)
+ 801f434:	d8000815 	stw	zero,32(sp)
+ 801f438:	d9000715 	stw	r4,28(sp)
+ 801f43c:	d8000615 	stw	zero,24(sp)
+ 801f440:	d8c00515 	stw	r3,20(sp)
+ 801f444:	d8800415 	stw	r2,16(sp)
+ 801f448:	e0800317 	ldw	r2,12(fp)
+ 801f44c:	d8800315 	stw	r2,12(sp)
+ 801f450:	e0800217 	ldw	r2,8(fp)
+ 801f454:	d8800215 	stw	r2,8(sp)
+ 801f458:	d8000115 	stw	zero,4(sp)
+ 801f45c:	d8000015 	stw	zero,0(sp)
+ 801f460:	e1fffc17 	ldw	r7,-16(fp)
+ 801f464:	e1bffd17 	ldw	r6,-12(fp)
+ 801f468:	e17ffe17 	ldw	r5,-8(fp)
+ 801f46c:	e13fff17 	ldw	r4,-4(fp)
+ 801f470:	801f0b40 	call	801f0b4 <alt_msgdma_construct_prefetcher_extended_descriptor>
+            read_address_high, read_address_low, 0, 0, length, control, 
+            sequence_number, read_burst_count, 0, read_stride, 0);
+}
+ 801f474:	e037883a 	mov	sp,fp
+ 801f478:	dfc00117 	ldw	ra,4(sp)
+ 801f47c:	df000017 	ldw	fp,0(sp)
+ 801f480:	dec00204 	addi	sp,sp,8
+ 801f484:	f800283a 	ret
+
+0801f488 <alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor>:
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count,
+    alt_u8 write_burst_count, 
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+ 801f488:	deffec04 	addi	sp,sp,-80
+ 801f48c:	dfc01315 	stw	ra,76(sp)
+ 801f490:	df001215 	stw	fp,72(sp)
+ 801f494:	df001204 	addi	fp,sp,72
+ 801f498:	e13fff15 	stw	r4,-4(fp)
+ 801f49c:	e17ffe15 	stw	r5,-8(fp)
+ 801f4a0:	e1bffd15 	stw	r6,-12(fp)
+ 801f4a4:	e1fffc15 	stw	r7,-16(fp)
+ 801f4a8:	e1800617 	ldw	r6,24(fp)
+ 801f4ac:	e1400717 	ldw	r5,28(fp)
+ 801f4b0:	e1000817 	ldw	r4,32(fp)
+ 801f4b4:	e0c00917 	ldw	r3,36(fp)
+ 801f4b8:	e0800a17 	ldw	r2,40(fp)
+ 801f4bc:	e1bffb0d 	sth	r6,-20(fp)
+ 801f4c0:	e17ffa05 	stb	r5,-24(fp)
+ 801f4c4:	e13ff905 	stb	r4,-28(fp)
+ 801f4c8:	e0fff80d 	sth	r3,-32(fp)
+ 801f4cc:	e0bff70d 	sth	r2,-36(fp)
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor,
+ 801f4d0:	e0bffb0b 	ldhu	r2,-20(fp)
+ 801f4d4:	e0fffa03 	ldbu	r3,-24(fp)
+ 801f4d8:	e13ff903 	ldbu	r4,-28(fp)
+ 801f4dc:	e17ff80b 	ldhu	r5,-32(fp)
+ 801f4e0:	e1bff70b 	ldhu	r6,-36(fp)
+ 801f4e4:	d9800815 	stw	r6,32(sp)
+ 801f4e8:	d9400715 	stw	r5,28(sp)
+ 801f4ec:	d9000615 	stw	r4,24(sp)
+ 801f4f0:	d8c00515 	stw	r3,20(sp)
+ 801f4f4:	d8800415 	stw	r2,16(sp)
+ 801f4f8:	e0800517 	ldw	r2,20(fp)
+ 801f4fc:	d8800315 	stw	r2,12(sp)
+ 801f500:	e0800417 	ldw	r2,16(fp)
+ 801f504:	d8800215 	stw	r2,8(sp)
+ 801f508:	e0800317 	ldw	r2,12(fp)
+ 801f50c:	d8800115 	stw	r2,4(sp)
+ 801f510:	e0800217 	ldw	r2,8(fp)
+ 801f514:	d8800015 	stw	r2,0(sp)
+ 801f518:	e1fffc17 	ldw	r7,-16(fp)
+ 801f51c:	e1bffd17 	ldw	r6,-12(fp)
+ 801f520:	e17ffe17 	ldw	r5,-8(fp)
+ 801f524:	e13fff17 	ldw	r4,-4(fp)
+ 801f528:	801f0b40 	call	801f0b4 <alt_msgdma_construct_prefetcher_extended_descriptor>
+            read_address_high, read_address_low, write_address_high, 
+            write_address_low, length, control, sequence_number, 
+            read_burst_count, write_burst_count, read_stride, write_stride);
+
+}
+ 801f52c:	e037883a 	mov	sp,fp
+ 801f530:	dfc00117 	ldw	ra,4(sp)
+ 801f534:	df000017 	ldw	fp,0(sp)
+ 801f538:	dec00204 	addi	sp,sp,8
+ 801f53c:	f800283a 	ret
+
+0801f540 <alt_msgdma_prefetcher_add_standard_desc_to_list>:
+ *           descriptor.next_ptr not pointing back to itslef)
+ */
+int alt_msgdma_prefetcher_add_standard_desc_to_list (
+    alt_msgdma_prefetcher_standard_descriptor** list,
+    alt_msgdma_prefetcher_standard_descriptor* descriptor)
+{
+ 801f540:	defffc04 	addi	sp,sp,-16
+ 801f544:	df000315 	stw	fp,12(sp)
+ 801f548:	df000304 	addi	fp,sp,12
+ 801f54c:	e13ffe15 	stw	r4,-8(fp)
+ 801f550:	e17ffd15 	stw	r5,-12(fp)
+    alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr;
+    
+    if (descriptor == NULL)
+ 801f554:	e0bffd17 	ldw	r2,-12(fp)
+ 801f558:	1000021e 	bne	r2,zero,801f564 <alt_msgdma_prefetcher_add_standard_desc_to_list+0x24>
+    {
+        return -EINVAL;  /* this descriptor cannot be NULL */
+ 801f55c:	00bffa84 	movi	r2,-22
+ 801f560:	00002f06 	br	801f620 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xe0>
+    }
+    if (descriptor->next_desc_ptr != (alt_u32)descriptor)
+ 801f564:	e0bffd17 	ldw	r2,-12(fp)
+ 801f568:	10c00317 	ldw	r3,12(r2)
+ 801f56c:	e0bffd17 	ldw	r2,-12(fp)
+ 801f570:	18800226 	beq	r3,r2,801f57c <alt_msgdma_prefetcher_add_standard_desc_to_list+0x3c>
+    {
+        return -EINVAL;  /* descriptor.next_ptr must point to itself */
+ 801f574:	00bffa84 	movi	r2,-22
+ 801f578:	00002906 	br	801f620 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xe0>
+    }
+    if (*list == NULL)
+ 801f57c:	e0bffe17 	ldw	r2,-8(fp)
+ 801f580:	10800017 	ldw	r2,0(r2)
+ 801f584:	1000051e 	bne	r2,zero,801f59c <alt_msgdma_prefetcher_add_standard_desc_to_list+0x5c>
+    {
+        *list = descriptor;  /* make this root-node if list is empty */
+ 801f588:	e0bffe17 	ldw	r2,-8(fp)
+ 801f58c:	e0fffd17 	ldw	r3,-12(fp)
+ 801f590:	10c00015 	stw	r3,0(r2)
+        return 0;  /* successfully added */
+ 801f594:	0005883a 	mov	r2,zero
+ 801f598:	00002106 	br	801f620 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xe0>
+    }
+    if (*list == descriptor)
+ 801f59c:	e0bffe17 	ldw	r2,-8(fp)
+ 801f5a0:	10800017 	ldw	r2,0(r2)
+ 801f5a4:	e0fffd17 	ldw	r3,-12(fp)
+ 801f5a8:	1880021e 	bne	r3,r2,801f5b4 <alt_msgdma_prefetcher_add_standard_desc_to_list+0x74>
+    {
+        return -EINVAL;  /* this descriptor cannot already be root-node */
+ 801f5ac:	00bffa84 	movi	r2,-22
+ 801f5b0:	00001b06 	br	801f620 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xe0>
+    }
+    
+    /* get to last node in the list */
+    last_descr_ptr = *list; /* start at list root-node */
+ 801f5b4:	e0bffe17 	ldw	r2,-8(fp)
+ 801f5b8:	10800017 	ldw	r2,0(r2)
+ 801f5bc:	e0bfff15 	stw	r2,-4(fp)
+    /* traverse list until you get the last node */
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)*list)  
+ 801f5c0:	00000906 	br	801f5e8 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xa8>
+    {
+        if (last_descr_ptr->next_desc_ptr == (alt_u32)descriptor)
+ 801f5c4:	e0bfff17 	ldw	r2,-4(fp)
+ 801f5c8:	10c00317 	ldw	r3,12(r2)
+ 801f5cc:	e0bffd17 	ldw	r2,-12(fp)
+ 801f5d0:	1880021e 	bne	r3,r2,801f5dc <alt_msgdma_prefetcher_add_standard_desc_to_list+0x9c>
+        {
+            return -EINVAL;  /* descriptor cannot already be in the list */
+ 801f5d4:	00bffa84 	movi	r2,-22
+ 801f5d8:	00001106 	br	801f620 <alt_msgdma_prefetcher_add_standard_desc_to_list+0xe0>
+        }
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr);
+ 801f5dc:	e0bfff17 	ldw	r2,-4(fp)
+ 801f5e0:	10800317 	ldw	r2,12(r2)
+        last_descr_ptr = 
+ 801f5e4:	e0bfff15 	stw	r2,-4(fp)
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)*list)  
+ 801f5e8:	e0bfff17 	ldw	r2,-4(fp)
+ 801f5ec:	10800317 	ldw	r2,12(r2)
+ 801f5f0:	e0fffe17 	ldw	r3,-8(fp)
+ 801f5f4:	18c00017 	ldw	r3,0(r3)
+ 801f5f8:	10fff21e 	bne	r2,r3,801f5c4 <alt_msgdma_prefetcher_add_standard_desc_to_list+0x84>
+    }
+    /* add this descriptor to end of list */
+    last_descr_ptr->next_desc_ptr = (alt_u32)((uintptr_t)descriptor);
+ 801f5fc:	e0fffd17 	ldw	r3,-12(fp)
+ 801f600:	e0bfff17 	ldw	r2,-4(fp)
+ 801f604:	10c00315 	stw	r3,12(r2)
+    /* ensure new last pointer points the start of the list */
+    descriptor->next_desc_ptr = (alt_u32)((uintptr_t)*list);  
+ 801f608:	e0bffe17 	ldw	r2,-8(fp)
+ 801f60c:	10800017 	ldw	r2,0(r2)
+ 801f610:	1007883a 	mov	r3,r2
+ 801f614:	e0bffd17 	ldw	r2,-12(fp)
+ 801f618:	10c00315 	stw	r3,12(r2)
+    return 0; /* successfully added */
+ 801f61c:	0005883a 	mov	r2,zero
+}
+ 801f620:	e037883a 	mov	sp,fp
+ 801f624:	df000017 	ldw	fp,0(sp)
+ 801f628:	dec00104 	addi	sp,sp,4
+ 801f62c:	f800283a 	ret
+
+0801f630 <alt_msgdma_prefetcher_add_extended_desc_to_list>:
+
+int alt_msgdma_prefetcher_add_extended_desc_to_list (
+    alt_msgdma_prefetcher_extended_descriptor** list,
+    alt_msgdma_prefetcher_extended_descriptor* descriptor)
+{
+ 801f630:	defff804 	addi	sp,sp,-32
+ 801f634:	df000715 	stw	fp,28(sp)
+ 801f638:	df000704 	addi	fp,sp,28
+ 801f63c:	e13ffa15 	stw	r4,-24(fp)
+ 801f640:	e17ff915 	stw	r5,-28(fp)
+    alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr;
+    msgdma_addr64 root_node_addr, next_node_addr;
+    
+    if (descriptor == NULL)
+ 801f644:	e13ff917 	ldw	r4,-28(fp)
+ 801f648:	2000021e 	bne	r4,zero,801f654 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x24>
+    {
+        return -EINVAL;  /* this descriptor cannot be NULL */
+ 801f64c:	00bffa84 	movi	r2,-22
+ 801f650:	00005906 	br	801f7b8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x188>
+    }
+    
+    next_node_addr.u64 = (uintptr_t)descriptor;
+ 801f654:	e13ff917 	ldw	r4,-28(fp)
+ 801f658:	2015883a 	mov	r10,r4
+ 801f65c:	0017883a 	mov	r11,zero
+ 801f660:	e2bffb15 	stw	r10,-20(fp)
+ 801f664:	e2fffc15 	stw	r11,-16(fp)
+    if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) ||
+ 801f668:	e13ff917 	ldw	r4,-28(fp)
+ 801f66c:	21400317 	ldw	r5,12(r4)
+ 801f670:	e13ffb17 	ldw	r4,-20(fp)
+ 801f674:	2900041e 	bne	r5,r4,801f688 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x58>
+        (descriptor->next_desc_ptr_high != next_node_addr.u32[1]))
+ 801f678:	e13ff917 	ldw	r4,-28(fp)
+ 801f67c:	21400b17 	ldw	r5,44(r4)
+ 801f680:	e13ffc17 	ldw	r4,-16(fp)
+    if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) ||
+ 801f684:	29000226 	beq	r5,r4,801f690 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x60>
+    {
+        return -EINVAL;  /* descriptor.next_ptr must point to itself */
+ 801f688:	00bffa84 	movi	r2,-22
+ 801f68c:	00004a06 	br	801f7b8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x188>
+    }
+    
+    if (*list == NULL)
+ 801f690:	e13ffa17 	ldw	r4,-24(fp)
+ 801f694:	21000017 	ldw	r4,0(r4)
+ 801f698:	2000051e 	bne	r4,zero,801f6b0 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x80>
+    {
+        *list = descriptor;  /* make this the root-node if list is empty */
+ 801f69c:	e0bffa17 	ldw	r2,-24(fp)
+ 801f6a0:	e0fff917 	ldw	r3,-28(fp)
+ 801f6a4:	10c00015 	stw	r3,0(r2)
+        return 0;
+ 801f6a8:	0005883a 	mov	r2,zero
+ 801f6ac:	00004206 	br	801f7b8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x188>
+    }
+    if (*list == descriptor)
+ 801f6b0:	e13ffa17 	ldw	r4,-24(fp)
+ 801f6b4:	21000017 	ldw	r4,0(r4)
+ 801f6b8:	e17ff917 	ldw	r5,-28(fp)
+ 801f6bc:	2900021e 	bne	r5,r4,801f6c8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x98>
+    {
+        return -EINVAL;  /* this descriptor cannot already be root-node */
+ 801f6c0:	00bffa84 	movi	r2,-22
+ 801f6c4:	00003c06 	br	801f7b8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x188>
+    }
+    
+    /* get to last node in the list */
+    last_descr_ptr = *list; /* start at list root-node */
+ 801f6c8:	e13ffa17 	ldw	r4,-24(fp)
+ 801f6cc:	21000017 	ldw	r4,0(r4)
+ 801f6d0:	e13fff15 	stw	r4,-4(fp)
+    /* the last nodes next ptr should point to the root node*/
+    root_node_addr.u64 = (uintptr_t)*list;
+ 801f6d4:	e13ffa17 	ldw	r4,-24(fp)
+ 801f6d8:	21000017 	ldw	r4,0(r4)
+ 801f6dc:	2011883a 	mov	r8,r4
+ 801f6e0:	0013883a 	mov	r9,zero
+ 801f6e4:	e23ffd15 	stw	r8,-12(fp)
+ 801f6e8:	e27ffe15 	stw	r9,-8(fp)
+    
+    /* traverse list until you get the last node */
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+ 801f6ec:	00001806 	br	801f750 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x120>
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+    {
+        /* first check if descriptor already in the list */
+        next_node_addr.u64 = (uintptr_t)descriptor;
+ 801f6f0:	e13ff917 	ldw	r4,-28(fp)
+ 801f6f4:	200d883a 	mov	r6,r4
+ 801f6f8:	000f883a 	mov	r7,zero
+ 801f6fc:	e1bffb15 	stw	r6,-20(fp)
+ 801f700:	e1fffc15 	stw	r7,-16(fp)
+        if ((last_descr_ptr->next_desc_ptr_low == next_node_addr.u32[0])
+ 801f704:	e13fff17 	ldw	r4,-4(fp)
+ 801f708:	21400317 	ldw	r5,12(r4)
+ 801f70c:	e13ffb17 	ldw	r4,-20(fp)
+ 801f710:	2900061e 	bne	r5,r4,801f72c <alt_msgdma_prefetcher_add_extended_desc_to_list+0xfc>
+            && (last_descr_ptr->next_desc_ptr_high == next_node_addr.u32[1]))
+ 801f714:	e13fff17 	ldw	r4,-4(fp)
+ 801f718:	21400b17 	ldw	r5,44(r4)
+ 801f71c:	e13ffc17 	ldw	r4,-16(fp)
+ 801f720:	2900021e 	bne	r5,r4,801f72c <alt_msgdma_prefetcher_add_extended_desc_to_list+0xfc>
+        {
+            return -EINVAL;  /* descriptor cannot already be in the list */
+ 801f724:	00bffa84 	movi	r2,-22
+ 801f728:	00002306 	br	801f7b8 <alt_msgdma_prefetcher_add_extended_desc_to_list+0x188>
+        }
+        /* go to next node in list, using 64 bit address */
+        next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low;
+ 801f72c:	e13fff17 	ldw	r4,-4(fp)
+ 801f730:	21000317 	ldw	r4,12(r4)
+ 801f734:	e13ffb15 	stw	r4,-20(fp)
+        next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high;
+ 801f738:	e13fff17 	ldw	r4,-4(fp)
+ 801f73c:	21000b17 	ldw	r4,44(r4)
+ 801f740:	e13ffc15 	stw	r4,-16(fp)
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64);
+ 801f744:	e13ffb17 	ldw	r4,-20(fp)
+ 801f748:	e17ffc17 	ldw	r5,-16(fp)
+        last_descr_ptr = 
+ 801f74c:	e13fff15 	stw	r4,-4(fp)
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+ 801f750:	e13fff17 	ldw	r4,-4(fp)
+ 801f754:	21400317 	ldw	r5,12(r4)
+ 801f758:	e13ffd17 	ldw	r4,-12(fp)
+ 801f75c:	293fe41e 	bne	r5,r4,801f6f0 <alt_msgdma_prefetcher_add_extended_desc_to_list+0xc0>
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+ 801f760:	e13fff17 	ldw	r4,-4(fp)
+ 801f764:	21400b17 	ldw	r5,44(r4)
+ 801f768:	e13ffe17 	ldw	r4,-8(fp)
+ 801f76c:	293fe01e 	bne	r5,r4,801f6f0 <alt_msgdma_prefetcher_add_extended_desc_to_list+0xc0>
+    }
+    /* add this descriptor to end of list */
+    next_node_addr.u64 = (uintptr_t)descriptor;
+ 801f770:	e13ff917 	ldw	r4,-28(fp)
+ 801f774:	2005883a 	mov	r2,r4
+ 801f778:	0007883a 	mov	r3,zero
+ 801f77c:	e0bffb15 	stw	r2,-20(fp)
+ 801f780:	e0fffc15 	stw	r3,-16(fp)
+    last_descr_ptr->next_desc_ptr_low = next_node_addr.u32[0];
+ 801f784:	e0fffb17 	ldw	r3,-20(fp)
+ 801f788:	e0bfff17 	ldw	r2,-4(fp)
+ 801f78c:	10c00315 	stw	r3,12(r2)
+    last_descr_ptr->next_desc_ptr_high = next_node_addr.u32[1];
+ 801f790:	e0fffc17 	ldw	r3,-16(fp)
+ 801f794:	e0bfff17 	ldw	r2,-4(fp)
+ 801f798:	10c00b15 	stw	r3,44(r2)
+    /* ensure new last pointer points the beginning of the list */
+    descriptor->next_desc_ptr_low = root_node_addr.u32[0];
+ 801f79c:	e0fffd17 	ldw	r3,-12(fp)
+ 801f7a0:	e0bff917 	ldw	r2,-28(fp)
+ 801f7a4:	10c00315 	stw	r3,12(r2)
+    descriptor->next_desc_ptr_high = root_node_addr.u32[1];
+ 801f7a8:	e0fffe17 	ldw	r3,-8(fp)
+ 801f7ac:	e0bff917 	ldw	r2,-28(fp)
+ 801f7b0:	10c00b15 	stw	r3,44(r2)
+    return 0;
+ 801f7b4:	0005883a 	mov	r2,zero
+}
+ 801f7b8:	e037883a 	mov	sp,fp
+ 801f7bc:	df000017 	ldw	fp,0(sp)
+ 801f7c0:	dec00104 	addi	sp,sp,4
+ 801f7c4:	f800283a 	ret
+
+0801f7c8 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits>:
+ */ 
+int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)    
+{
+ 801f7c8:	defff804 	addi	sp,sp,-32
+ 801f7cc:	dfc00715 	stw	ra,28(sp)
+ 801f7d0:	df000615 	stw	fp,24(sp)
+ 801f7d4:	df000604 	addi	fp,sp,24
+ 801f7d8:	e13ffc15 	stw	r4,-16(fp)
+ 801f7dc:	2805883a 	mov	r2,r5
+ 801f7e0:	3007883a 	mov	r3,r6
+ 801f7e4:	e0bffb05 	stb	r2,-20(fp)
+ 801f7e8:	1805883a 	mov	r2,r3
+ 801f7ec:	e0bffa05 	stb	r2,-24(fp)
+    alt_u32 descriptor_control_field = 0;
+ 801f7f0:	e03ffd15 	stw	zero,-12(fp)
+    alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr;
+    alt_u32 descriptor_count = 0;
+ 801f7f4:	e03ffe15 	stw	zero,-8(fp)
+    
+    if (list == NULL)
+ 801f7f8:	e0bffc17 	ldw	r2,-16(fp)
+ 801f7fc:	1000021e 	bne	r2,zero,801f808 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0x40>
+    {
+        return -EINVAL;  /* this list cannot be empty */
+ 801f800:	00bffa84 	movi	r2,-22
+ 801f804:	00002f06 	br	801f8c4 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0xfc>
+    }
+
+    /* update all nodes in the list */
+    last_descr_ptr = list; /* start at list root-node */
+ 801f808:	e0bffc17 	ldw	r2,-16(fp)
+ 801f80c:	e0bfff15 	stw	r2,-4(fp)
+    /* traverse list to update all of the nodes */
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)list)  
+ 801f810:	00000d06 	br	801f848 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0x80>
+    {
+        /* get current value */
+        descriptor_control_field = last_descr_ptr->control;
+ 801f814:	e0bfff17 	ldw	r2,-4(fp)
+ 801f818:	10800717 	ldw	r2,28(r2)
+ 801f81c:	e0bffd15 	stw	r2,-12(fp)
+        /* update own_by_hw bit only */
+        last_descr_ptr->control = descriptor_control_field 
+                | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;
+ 801f820:	e0bffd17 	ldw	r2,-12(fp)
+ 801f824:	10d00034 	orhi	r3,r2,16384
+        last_descr_ptr->control = descriptor_control_field 
+ 801f828:	e0bfff17 	ldw	r2,-4(fp)
+ 801f82c:	10c00715 	stw	r3,28(r2)
+        /* go to next node in list */
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr);
+ 801f830:	e0bfff17 	ldw	r2,-4(fp)
+ 801f834:	10800317 	ldw	r2,12(r2)
+        last_descr_ptr = 
+ 801f838:	e0bfff15 	stw	r2,-4(fp)
+            
+        descriptor_count++;
+ 801f83c:	e0bffe17 	ldw	r2,-8(fp)
+ 801f840:	10800044 	addi	r2,r2,1
+ 801f844:	e0bffe15 	stw	r2,-8(fp)
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)list)  
+ 801f848:	e0bfff17 	ldw	r2,-4(fp)
+ 801f84c:	10c00317 	ldw	r3,12(r2)
+ 801f850:	e0bffc17 	ldw	r2,-16(fp)
+ 801f854:	18bfef1e 	bne	r3,r2,801f814 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0x4c>
+    }
+    /* update the last node in the list, currently last_descr_ptr after while loop */
+    descriptor_control_field = last_descr_ptr->control;    /* get current value */
+ 801f858:	e0bfff17 	ldw	r2,-4(fp)
+ 801f85c:	10800717 	ldw	r2,28(r2)
+ 801f860:	e0bffd15 	stw	r2,-12(fp)
+    /* update own_by_hw bit only */
+    if (last_desc_owned_by_sw)
+ 801f864:	e0bffb03 	ldbu	r2,-20(fp)
+ 801f868:	10000726 	beq	r2,zero,801f888 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0xc0>
+    {
+        last_descr_ptr->control = descriptor_control_field 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK;
+ 801f86c:	e0fffd17 	ldw	r3,-12(fp)
+ 801f870:	00b00034 	movhi	r2,49152
+ 801f874:	10bfffc4 	addi	r2,r2,-1
+ 801f878:	1886703a 	and	r3,r3,r2
+        last_descr_ptr->control = descriptor_control_field 
+ 801f87c:	e0bfff17 	ldw	r2,-4(fp)
+ 801f880:	10c00715 	stw	r3,28(r2)
+ 801f884:	00000406 	br	801f898 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0xd0>
+    }
+    else {
+        last_descr_ptr->control = descriptor_control_field 
+            | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;        
+ 801f888:	e0bffd17 	ldw	r2,-12(fp)
+ 801f88c:	10d00034 	orhi	r3,r2,16384
+        last_descr_ptr->control = descriptor_control_field 
+ 801f890:	e0bfff17 	ldw	r2,-4(fp)
+ 801f894:	10c00715 	stw	r3,28(r2)
+    }
+    
+    descriptor_count++;
+ 801f898:	e0bffe17 	ldw	r2,-8(fp)
+ 801f89c:	10800044 	addi	r2,r2,1
+ 801f8a0:	e0bffe15 	stw	r2,-8(fp)
+    
+    if (dcache_flush_desc_list)
+ 801f8a4:	e0bffa03 	ldbu	r2,-24(fp)
+ 801f8a8:	10000526 	beq	r2,zero,801f8c0 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits+0xf8>
+    {        
+        alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_standard_descriptor) * descriptor_count);
+ 801f8ac:	e0bffe17 	ldw	r2,-8(fp)
+ 801f8b0:	1004917a 	slli	r2,r2,5
+ 801f8b4:	100b883a 	mov	r5,r2
+ 801f8b8:	e13ffc17 	ldw	r4,-16(fp)
+ 801f8bc:	80371c00 	call	80371c0 <alt_dcache_flush>
+    }
+    
+    return 0;
+ 801f8c0:	0005883a 	mov	r2,zero
+}
+ 801f8c4:	e037883a 	mov	sp,fp
+ 801f8c8:	dfc00117 	ldw	ra,4(sp)
+ 801f8cc:	df000017 	ldw	fp,0(sp)
+ 801f8d0:	dec00204 	addi	sp,sp,8
+ 801f8d4:	f800283a 	ret
+
+0801f8d8 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits>:
+ */    
+int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list) 
+{    
+ 801f8d8:	defff404 	addi	sp,sp,-48
+ 801f8dc:	dfc00b15 	stw	ra,44(sp)
+ 801f8e0:	df000a15 	stw	fp,40(sp)
+ 801f8e4:	df000a04 	addi	fp,sp,40
+ 801f8e8:	e13ff815 	stw	r4,-32(fp)
+ 801f8ec:	2809883a 	mov	r4,r5
+ 801f8f0:	300b883a 	mov	r5,r6
+ 801f8f4:	e13ff705 	stb	r4,-36(fp)
+ 801f8f8:	2809883a 	mov	r4,r5
+ 801f8fc:	e13ff605 	stb	r4,-40(fp)
+    alt_u32 descriptor_control_field = 0;
+ 801f900:	e03ffd15 	stw	zero,-12(fp)
+    msgdma_addr64 root_node_addr, next_node_addr;
+    alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr;
+    alt_u32 descriptor_count = 0;
+ 801f904:	e03ffe15 	stw	zero,-8(fp)
+    
+    if (list == NULL)
+ 801f908:	e13ff817 	ldw	r4,-32(fp)
+ 801f90c:	2000021e 	bne	r4,zero,801f918 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x40>
+    {
+        return -EINVAL;  /* this list cannot be empty */
+ 801f910:	00bffa84 	movi	r2,-22
+ 801f914:	00003e06 	br	801fa10 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x138>
+    }
+    
+    /* update all nodes in the list */
+    last_descr_ptr = list; /* start at list root-node */
+ 801f918:	e13ff817 	ldw	r4,-32(fp)
+ 801f91c:	e13fff15 	stw	r4,-4(fp)
+    /* the last nodes next ptr should point to the root node*/
+    root_node_addr.u64 = (uintptr_t)list;
+ 801f920:	e13ff817 	ldw	r4,-32(fp)
+ 801f924:	2005883a 	mov	r2,r4
+ 801f928:	0007883a 	mov	r3,zero
+ 801f92c:	e0bffb15 	stw	r2,-20(fp)
+ 801f930:	e0fffc15 	stw	r3,-16(fp)
+
+    /* traverse list until you get the last node */
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+ 801f934:	00001306 	br	801f984 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0xac>
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+    {
+        /* start with current value */
+        descriptor_control_field = last_descr_ptr->control;
+ 801f938:	e0bfff17 	ldw	r2,-4(fp)
+ 801f93c:	10800f17 	ldw	r2,60(r2)
+ 801f940:	e0bffd15 	stw	r2,-12(fp)
+        /* update own_by_hw bit only */
+        last_descr_ptr->control = descriptor_control_field 
+                | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;
+ 801f944:	e0bffd17 	ldw	r2,-12(fp)
+ 801f948:	10d00034 	orhi	r3,r2,16384
+        last_descr_ptr->control = descriptor_control_field 
+ 801f94c:	e0bfff17 	ldw	r2,-4(fp)
+ 801f950:	10c00f15 	stw	r3,60(r2)
+        /* go to next node in list, using 64 bit address */
+        next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low;
+ 801f954:	e0bfff17 	ldw	r2,-4(fp)
+ 801f958:	10800317 	ldw	r2,12(r2)
+ 801f95c:	e0bff915 	stw	r2,-28(fp)
+        next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high;
+ 801f960:	e0bfff17 	ldw	r2,-4(fp)
+ 801f964:	10800b17 	ldw	r2,44(r2)
+ 801f968:	e0bffa15 	stw	r2,-24(fp)
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64);
+ 801f96c:	e0bff917 	ldw	r2,-28(fp)
+ 801f970:	e0fffa17 	ldw	r3,-24(fp)
+        last_descr_ptr = 
+ 801f974:	e0bfff15 	stw	r2,-4(fp)
+        descriptor_count++;            
+ 801f978:	e0bffe17 	ldw	r2,-8(fp)
+ 801f97c:	10800044 	addi	r2,r2,1
+ 801f980:	e0bffe15 	stw	r2,-8(fp)
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+ 801f984:	e0bfff17 	ldw	r2,-4(fp)
+ 801f988:	10c00317 	ldw	r3,12(r2)
+ 801f98c:	e0bffb17 	ldw	r2,-20(fp)
+ 801f990:	18bfe91e 	bne	r3,r2,801f938 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x60>
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+ 801f994:	e0bfff17 	ldw	r2,-4(fp)
+ 801f998:	10c00b17 	ldw	r3,44(r2)
+ 801f99c:	e0bffc17 	ldw	r2,-16(fp)
+ 801f9a0:	18bfe51e 	bne	r3,r2,801f938 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x60>
+    }
+    /* update the last node in the list, currently last_descr_ptr after while loop */
+    descriptor_control_field = last_descr_ptr->control;    /* start with current value */
+ 801f9a4:	e0bfff17 	ldw	r2,-4(fp)
+ 801f9a8:	10800f17 	ldw	r2,60(r2)
+ 801f9ac:	e0bffd15 	stw	r2,-12(fp)
+    /* update own_by_hw bit only */
+    if (last_desc_owned_by_sw)
+ 801f9b0:	e0bff703 	ldbu	r2,-36(fp)
+ 801f9b4:	10000726 	beq	r2,zero,801f9d4 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0xfc>
+    {
+        last_descr_ptr->control = descriptor_control_field 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK;
+ 801f9b8:	e0fffd17 	ldw	r3,-12(fp)
+ 801f9bc:	00b00034 	movhi	r2,49152
+ 801f9c0:	10bfffc4 	addi	r2,r2,-1
+ 801f9c4:	1886703a 	and	r3,r3,r2
+        last_descr_ptr->control = descriptor_control_field 
+ 801f9c8:	e0bfff17 	ldw	r2,-4(fp)
+ 801f9cc:	10c00f15 	stw	r3,60(r2)
+ 801f9d0:	00000406 	br	801f9e4 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x10c>
+    }
+    else {
+        last_descr_ptr->control = descriptor_control_field 
+            | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;        
+ 801f9d4:	e0bffd17 	ldw	r2,-12(fp)
+ 801f9d8:	10d00034 	orhi	r3,r2,16384
+        last_descr_ptr->control = descriptor_control_field 
+ 801f9dc:	e0bfff17 	ldw	r2,-4(fp)
+ 801f9e0:	10c00f15 	stw	r3,60(r2)
+    }
+    
+    descriptor_count++;
+ 801f9e4:	e0bffe17 	ldw	r2,-8(fp)
+ 801f9e8:	10800044 	addi	r2,r2,1
+ 801f9ec:	e0bffe15 	stw	r2,-8(fp)
+    
+    if (dcache_flush_desc_list)
+ 801f9f0:	e0bff603 	ldbu	r2,-40(fp)
+ 801f9f4:	10000526 	beq	r2,zero,801fa0c <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits+0x134>
+    {        
+        alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_extended_descriptor) * descriptor_count);        
+ 801f9f8:	e0bffe17 	ldw	r2,-8(fp)
+ 801f9fc:	100491ba 	slli	r2,r2,6
+ 801fa00:	100b883a 	mov	r5,r2
+ 801fa04:	e13ff817 	ldw	r4,-32(fp)
+ 801fa08:	80371c00 	call	80371c0 <alt_dcache_flush>
+    }
+    
+    return 0;
+ 801fa0c:	0005883a 	mov	r2,zero
+}
+ 801fa10:	e037883a 	mov	sp,fp
+ 801fa14:	dfc00117 	ldw	ra,4(sp)
+ 801fa18:	df000017 	ldw	fp,0(sp)
+ 801fa1c:	dec00204 	addi	sp,sp,8
+ 801fa20:	f800283a 	ret
+
+0801fa24 <alt_msgdma_start_prefetcher_with_list_addr>:
+int alt_msgdma_start_prefetcher_with_list_addr (
+    alt_msgdma_dev *dev,
+    alt_u64  list_addr,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en)
+{
+ 801fa24:	deffeb04 	addi	sp,sp,-84
+ 801fa28:	dfc01415 	stw	ra,80(sp)
+ 801fa2c:	df001315 	stw	fp,76(sp)
+ 801fa30:	df001304 	addi	fp,sp,76
+ 801fa34:	e13ff115 	stw	r4,-60(fp)
+ 801fa38:	e17fef15 	stw	r5,-68(fp)
+ 801fa3c:	e1bff015 	stw	r6,-64(fp)
+ 801fa40:	3807883a 	mov	r3,r7
+ 801fa44:	e0800217 	ldw	r2,8(fp)
+ 801fa48:	e0ffee05 	stb	r3,-72(fp)
+ 801fa4c:	e0bfed05 	stb	r2,-76(fp)
+    alt_u32 prefetcher_ctl = 0;
+ 801fa50:	e03fff15 	stw	zero,-4(fp)
+    alt_u32 dispatcher_ctl = 0;
+ 801fa54:	e03ffe15 	stw	zero,-8(fp)
+    alt_irq_context context = 0;
+ 801fa58:	e03ffd15 	stw	zero,-12(fp)
+    
+    /* use helper struct to get easy access to hi/low address */
+    msgdma_addr64 root_node_addr;
+    root_node_addr.u64 = list_addr;  
+ 801fa5c:	e0bfef17 	ldw	r2,-68(fp)
+ 801fa60:	e0bff315 	stw	r2,-52(fp)
+ 801fa64:	e0bff017 	ldw	r2,-64(fp)
+ 801fa68:	e0bff415 	stw	r2,-48(fp)
+    
+    /*
+     * When running in a multi threaded environment, obtain the "regs_lock"
+     * semaphore. This ensures that accessing registers is thread-safe.
+     */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+ 801fa6c:	e0bff117 	ldw	r2,-60(fp)
+ 801fa70:	10801817 	ldw	r2,96(r2)
+ 801fa74:	e0bffc15 	stw	r2,-16(fp)
+ 801fa78:	e03ffb8d 	sth	zero,-18(fp)
+ 801fa7c:	e0bffb8b 	ldhu	r2,-18(fp)
+ 801fa80:	e0fff2c4 	addi	r3,fp,-53
+ 801fa84:	180d883a 	mov	r6,r3
+ 801fa88:	100b883a 	mov	r5,r2
+ 801fa8c:	e13ffc17 	ldw	r4,-16(fp)
+ 801fa90:	8015a600 	call	8015a60 <OSSemPend>
+    
+    /* case where prefetcher already started, return busy error */ 
+    prefetcher_ctl = IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base);
+ 801fa94:	e0bff117 	ldw	r2,-60(fp)
+ 801fa98:	10800617 	ldw	r2,24(r2)
+ 801fa9c:	10800037 	ldwio	r2,0(r2)
+ 801faa0:	e0bfff15 	stw	r2,-4(fp)
+    if(ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(prefetcher_ctl)){
+ 801faa4:	e0bfff17 	ldw	r2,-4(fp)
+ 801faa8:	1080004c 	andi	r2,r2,1
+ 801faac:	10000626 	beq	r2,zero,801fac8 <alt_msgdma_start_prefetcher_with_list_addr+0xa4>
+        /* release the registers semaphore */
+        ALT_SEM_POST (dev->regs_lock);
+ 801fab0:	e0bff117 	ldw	r2,-60(fp)
+ 801fab4:	10801817 	ldw	r2,96(r2)
+ 801fab8:	1009883a 	mov	r4,r2
+ 801fabc:	8015d840 	call	8015d84 <OSSemPost>
+        return -EBUSY;
+ 801fac0:	00bffc04 	movi	r2,-16
+ 801fac4:	00009606 	br	801fd20 <alt_msgdma_start_prefetcher_with_list_addr+0x2fc>
+    }
+        
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+       read or write masters  */
+    /* stop issuing more descriptors */
+    dispatcher_ctl = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+ 801fac8:	00800804 	movi	r2,32
+ 801facc:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 801fad0:	0005303a 	rdctl	r2,status
+ 801fad4:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801fad8:	e0fff917 	ldw	r3,-28(fp)
+ 801fadc:	00bfff84 	movi	r2,-2
+ 801fae0:	1884703a 	and	r2,r3,r2
+ 801fae4:	1001703a 	wrctl	status,r2
+  return context;
+ 801fae8:	e0bff917 	ldw	r2,-28(fp)
+    
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+ 801faec:	e0bffd15 	stw	r2,-12(fp)
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+ 801faf0:	e0bff117 	ldw	r2,-60(fp)
+ 801faf4:	10800317 	ldw	r2,12(r2)
+ 801faf8:	10800104 	addi	r2,r2,4
+ 801fafc:	e0fffe17 	ldw	r3,-8(fp)
+ 801fb00:	10c00035 	stwio	r3,0(r2)
+    /*
+     * Clear any (previous) status register information
+     * that might occlude our error checking later.
+     */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS( dev->csr_base, 
+ 801fb04:	e0bff117 	ldw	r2,-60(fp)
+ 801fb08:	10800317 	ldw	r2,12(r2)
+ 801fb0c:	e0fff117 	ldw	r3,-60(fp)
+ 801fb10:	18c00317 	ldw	r3,12(r3)
+ 801fb14:	18c00037 	ldwio	r3,0(r3)
+ 801fb18:	10c00035 	stwio	r3,0(r2)
+ 801fb1c:	e0bffd17 	ldw	r2,-12(fp)
+ 801fb20:	e0bffa15 	stw	r2,-24(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801fb24:	e0bffa17 	ldw	r2,-24(fp)
+ 801fb28:	1001703a 	wrctl	status,r2
+     * If a callback routine has been previously registered which will be
+     * called from the msgdma ISR. Set up dispatcher to:
+     *  - Run
+     *  - Stop on an error with any particular descriptor
+     */
+    if(dev->callback)
+ 801fb2c:	e0bff117 	ldw	r2,-60(fp)
+ 801fb30:	10800b17 	ldw	r2,44(r2)
+ 801fb34:	10002326 	beq	r2,zero,801fbc4 <alt_msgdma_start_prefetcher_with_list_addr+0x1a0>
+    {
+        dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK 
+ 801fb38:	e0bff117 	ldw	r2,-60(fp)
+ 801fb3c:	10c00d17 	ldw	r3,52(r2)
+ 801fb40:	e0bffe17 	ldw	r2,-8(fp)
+ 801fb44:	1884b03a 	or	r2,r3,r2
+ 801fb48:	10800514 	ori	r2,r2,20
+ 801fb4c:	e0bffe15 	stw	r2,-8(fp)
+                | ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK );
+        dispatcher_ctl &=  (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+ 801fb50:	e0fffe17 	ldw	r3,-8(fp)
+ 801fb54:	00bff7c4 	movi	r2,-33
+ 801fb58:	1884703a 	and	r2,r3,r2
+ 801fb5c:	e0bffe15 	stw	r2,-8(fp)
+        
+        prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK;
+ 801fb60:	e0bfff17 	ldw	r2,-4(fp)
+ 801fb64:	10800214 	ori	r2,r2,8
+ 801fb68:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 801fb6c:	0005303a 	rdctl	r2,status
+ 801fb70:	e0bff715 	stw	r2,-36(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801fb74:	e0fff717 	ldw	r3,-36(fp)
+ 801fb78:	00bfff84 	movi	r2,-2
+ 801fb7c:	1884703a 	and	r2,r3,r2
+ 801fb80:	1001703a 	wrctl	status,r2
+  return context;
+ 801fb84:	e0bff717 	ldw	r2,-36(fp)
+        /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all(); 
+ 801fb88:	e0bffd15 	stw	r2,-12(fp)
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+ 801fb8c:	e0bff117 	ldw	r2,-60(fp)
+ 801fb90:	10800317 	ldw	r2,12(r2)
+ 801fb94:	10800104 	addi	r2,r2,4
+ 801fb98:	e0fffe17 	ldw	r3,-8(fp)
+ 801fb9c:	10c00035 	stwio	r3,0(r2)
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+ 801fba0:	e0bff117 	ldw	r2,-60(fp)
+ 801fba4:	10800617 	ldw	r2,24(r2)
+ 801fba8:	e0ffff17 	ldw	r3,-4(fp)
+ 801fbac:	10c00035 	stwio	r3,0(r2)
+ 801fbb0:	e0bffd17 	ldw	r2,-12(fp)
+ 801fbb4:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801fbb8:	e0bff817 	ldw	r2,-32(fp)
+ 801fbbc:	1001703a 	wrctl	status,r2
+ 801fbc0:	00002306 	br	801fc50 <alt_msgdma_start_prefetcher_with_list_addr+0x22c>
+      *   - Stop on an error with any particular descriptor
+      *   - Disable interrupt generation
+      */
+     else
+     {
+         dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK);
+ 801fbc4:	e0bff117 	ldw	r2,-60(fp)
+ 801fbc8:	10c00d17 	ldw	r3,52(r2)
+ 801fbcc:	e0bffe17 	ldw	r2,-8(fp)
+ 801fbd0:	1884b03a 	or	r2,r3,r2
+ 801fbd4:	10800114 	ori	r2,r2,4
+ 801fbd8:	e0bffe15 	stw	r2,-8(fp)
+         dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) 
+ 801fbdc:	e0fffe17 	ldw	r3,-8(fp)
+ 801fbe0:	00bff3c4 	movi	r2,-49
+ 801fbe4:	1884703a 	and	r2,r3,r2
+ 801fbe8:	e0bffe15 	stw	r2,-8(fp)
+                 & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK;
+ 801fbec:	e0ffff17 	ldw	r3,-4(fp)
+ 801fbf0:	00bffdc4 	movi	r2,-9
+ 801fbf4:	1884703a 	and	r2,r3,r2
+ 801fbf8:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 801fbfc:	0005303a 	rdctl	r2,status
+ 801fc00:	e0bff515 	stw	r2,-44(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 801fc04:	e0fff517 	ldw	r3,-44(fp)
+ 801fc08:	00bfff84 	movi	r2,-2
+ 801fc0c:	1884703a 	and	r2,r3,r2
+ 801fc10:	1001703a 	wrctl	status,r2
+  return context;
+ 801fc14:	e0bff517 	ldw	r2,-44(fp)
+         /* making sure the read-modify-write below can't be pre-empted */
+         context = alt_irq_disable_all();
+ 801fc18:	e0bffd15 	stw	r2,-12(fp)
+         IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+ 801fc1c:	e0bff117 	ldw	r2,-60(fp)
+ 801fc20:	10800317 	ldw	r2,12(r2)
+ 801fc24:	10800104 	addi	r2,r2,4
+ 801fc28:	e0fffe17 	ldw	r3,-8(fp)
+ 801fc2c:	10c00035 	stwio	r3,0(r2)
+         IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+ 801fc30:	e0bff117 	ldw	r2,-60(fp)
+ 801fc34:	10800617 	ldw	r2,24(r2)
+ 801fc38:	e0ffff17 	ldw	r3,-4(fp)
+ 801fc3c:	10c00035 	stwio	r3,0(r2)
+ 801fc40:	e0bffd17 	ldw	r2,-12(fp)
+ 801fc44:	e0bff615 	stw	r2,-40(fp)
+  NIOS2_WRITE_STATUS (context);
+ 801fc48:	e0bff617 	ldw	r2,-40(fp)
+ 801fc4c:	1001703a 	wrctl	status,r2
+         alt_irq_enable_all(context);
+     }   
+    
+     /* set next descriptor registers to point to the list root-node */
+     IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(dev->prefetcher_base,
+ 801fc50:	e0bff117 	ldw	r2,-60(fp)
+ 801fc54:	10800617 	ldw	r2,24(r2)
+ 801fc58:	10800104 	addi	r2,r2,4
+ 801fc5c:	e0fff317 	ldw	r3,-52(fp)
+ 801fc60:	10c00035 	stwio	r3,0(r2)
+             root_node_addr.u32[0]);
+     IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(dev->prefetcher_base,
+ 801fc64:	e0bff117 	ldw	r2,-60(fp)
+ 801fc68:	10800617 	ldw	r2,24(r2)
+ 801fc6c:	10800204 	addi	r2,r2,8
+ 801fc70:	e0fff417 	ldw	r3,-48(fp)
+ 801fc74:	10c00035 	stwio	r3,0(r2)
+             root_node_addr.u32[1]);
+        
+     /* set park-mode */
+     if (park_mode_en){
+ 801fc78:	e0bfee03 	ldbu	r2,-72(fp)
+ 801fc7c:	10000426 	beq	r2,zero,801fc90 <alt_msgdma_start_prefetcher_with_list_addr+0x26c>
+         prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK;
+ 801fc80:	e0bfff17 	ldw	r2,-4(fp)
+ 801fc84:	10800414 	ori	r2,r2,16
+ 801fc88:	e0bfff15 	stw	r2,-4(fp)
+ 801fc8c:	00000406 	br	801fca0 <alt_msgdma_start_prefetcher_with_list_addr+0x27c>
+     }
+     else {
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK;
+ 801fc90:	e0ffff17 	ldw	r3,-4(fp)
+ 801fc94:	00bffbc4 	movi	r2,-17
+ 801fc98:	1884703a 	and	r2,r3,r2
+ 801fc9c:	e0bfff15 	stw	r2,-4(fp)
+     }
+     
+     /* set poll-en */
+     if (poll_en){
+ 801fca0:	e0bfed03 	ldbu	r2,-76(fp)
+ 801fca4:	10000e26 	beq	r2,zero,801fce0 <alt_msgdma_start_prefetcher_with_list_addr+0x2bc>
+         prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK; 
+ 801fca8:	e0bfff17 	ldw	r2,-4(fp)
+ 801fcac:	10800094 	ori	r2,r2,2
+ 801fcb0:	e0bfff15 	stw	r2,-4(fp)
+         if(IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(
+ 801fcb4:	e0bff117 	ldw	r2,-60(fp)
+ 801fcb8:	10800617 	ldw	r2,24(r2)
+ 801fcbc:	10800304 	addi	r2,r2,12
+ 801fcc0:	10800037 	ldwio	r2,0(r2)
+ 801fcc4:	10000a1e 	bne	r2,zero,801fcf0 <alt_msgdma_start_prefetcher_with_list_addr+0x2cc>
+                 dev->prefetcher_base) == 0){
+             /* set poll frequency to some non-zero default value */
+             IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(
+ 801fcc8:	e0bff117 	ldw	r2,-60(fp)
+ 801fccc:	10800617 	ldw	r2,24(r2)
+ 801fcd0:	10800304 	addi	r2,r2,12
+ 801fcd4:	00c03fc4 	movi	r3,255
+ 801fcd8:	10c00035 	stwio	r3,0(r2)
+ 801fcdc:	00000406 	br	801fcf0 <alt_msgdma_start_prefetcher_with_list_addr+0x2cc>
+                     dev->prefetcher_base, 0xFF);
+         }
+     }
+     else {
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK; 
+ 801fce0:	e0ffff17 	ldw	r3,-4(fp)
+ 801fce4:	00bfff44 	movi	r2,-3
+ 801fce8:	1884703a 	and	r2,r3,r2
+ 801fcec:	e0bfff15 	stw	r2,-4(fp)
+     }
+     
+     /* set the prefetcher run bit */
+     prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK;
+ 801fcf0:	e0bfff17 	ldw	r2,-4(fp)
+ 801fcf4:	10800054 	ori	r2,r2,1
+ 801fcf8:	e0bfff15 	stw	r2,-4(fp)
+     /* start the dma since run bit is set */
+     IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+ 801fcfc:	e0bff117 	ldw	r2,-60(fp)
+ 801fd00:	10800617 	ldw	r2,24(r2)
+ 801fd04:	e0ffff17 	ldw	r3,-4(fp)
+ 801fd08:	10c00035 	stwio	r3,0(r2)
+     
+     /*
+      * Now that access to the registers is complete, release the registers
+      * semaphore so that other threads can access the registers.
+      */
+     ALT_SEM_POST (dev->regs_lock);
+ 801fd0c:	e0bff117 	ldw	r2,-60(fp)
+ 801fd10:	10801817 	ldw	r2,96(r2)
+ 801fd14:	1009883a 	mov	r4,r2
+ 801fd18:	8015d840 	call	8015d84 <OSSemPost>
+     
+     return 0;
+ 801fd1c:	0005883a 	mov	r2,zero
+}
+ 801fd20:	e037883a 	mov	sp,fp
+ 801fd24:	dfc00117 	ldw	ra,4(sp)
+ 801fd28:	df000017 	ldw	fp,0(sp)
+ 801fd2c:	dec00204 	addi	sp,sp,8
+ 801fd30:	f800283a 	ret
+
+0801fd34 <alt_msgdma_start_prefetcher_with_std_desc_list>:
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)
+{    
+ 801fd34:	defff504 	addi	sp,sp,-44
+ 801fd38:	dfc00a15 	stw	ra,40(sp)
+ 801fd3c:	df000915 	stw	fp,36(sp)
+ 801fd40:	dc400815 	stw	r17,32(sp)
+ 801fd44:	dc000715 	stw	r16,28(sp)
+ 801fd48:	df000904 	addi	fp,sp,36
+ 801fd4c:	e13ffd15 	stw	r4,-12(fp)
+ 801fd50:	e17ffc15 	stw	r5,-16(fp)
+ 801fd54:	3009883a 	mov	r4,r6
+ 801fd58:	380b883a 	mov	r5,r7
+ 801fd5c:	e0c00217 	ldw	r3,8(fp)
+ 801fd60:	e0800317 	ldw	r2,12(fp)
+ 801fd64:	e13ffb05 	stb	r4,-20(fp)
+ 801fd68:	2809883a 	mov	r4,r5
+ 801fd6c:	e13ffa05 	stb	r4,-24(fp)
+ 801fd70:	e0fff905 	stb	r3,-28(fp)
+ 801fd74:	e0bff805 	stb	r2,-32(fp)
+    if (alt_msgdma_prefetcher_set_std_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0)
+ 801fd78:	e0bff903 	ldbu	r2,-28(fp)
+ 801fd7c:	e0fff803 	ldbu	r3,-32(fp)
+ 801fd80:	180d883a 	mov	r6,r3
+ 801fd84:	100b883a 	mov	r5,r2
+ 801fd88:	e13ffc17 	ldw	r4,-16(fp)
+ 801fd8c:	801f7c80 	call	801f7c8 <alt_msgdma_prefetcher_set_std_list_own_by_hw_bits>
+ 801fd90:	10000226 	beq	r2,zero,801fd9c <alt_msgdma_start_prefetcher_with_std_desc_list+0x68>
+    {
+        return -EINVAL;
+ 801fd94:	00bffa84 	movi	r2,-22
+ 801fd98:	00000b06 	br	801fdc8 <alt_msgdma_start_prefetcher_with_std_desc_list+0x94>
+    }
+
+    return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list,
+ 801fd9c:	e0bffc17 	ldw	r2,-16(fp)
+ 801fda0:	1021883a 	mov	r16,r2
+ 801fda4:	0023883a 	mov	r17,zero
+ 801fda8:	e0fffb03 	ldbu	r3,-20(fp)
+ 801fdac:	e0bffa03 	ldbu	r2,-24(fp)
+ 801fdb0:	d8800015 	stw	r2,0(sp)
+ 801fdb4:	180f883a 	mov	r7,r3
+ 801fdb8:	800b883a 	mov	r5,r16
+ 801fdbc:	880d883a 	mov	r6,r17
+ 801fdc0:	e13ffd17 	ldw	r4,-12(fp)
+ 801fdc4:	801fa240 	call	801fa24 <alt_msgdma_start_prefetcher_with_list_addr>
+            park_mode_en, poll_en);
+}
+ 801fdc8:	e6fffe04 	addi	sp,fp,-8
+ 801fdcc:	dfc00317 	ldw	ra,12(sp)
+ 801fdd0:	df000217 	ldw	fp,8(sp)
+ 801fdd4:	dc400117 	ldw	r17,4(sp)
+ 801fdd8:	dc000017 	ldw	r16,0(sp)
+ 801fddc:	dec00404 	addi	sp,sp,16
+ 801fde0:	f800283a 	ret
+
+0801fde4 <alt_msgdma_start_prefetcher_with_extd_desc_list>:
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)
+{
+ 801fde4:	defff504 	addi	sp,sp,-44
+ 801fde8:	dfc00a15 	stw	ra,40(sp)
+ 801fdec:	df000915 	stw	fp,36(sp)
+ 801fdf0:	dc400815 	stw	r17,32(sp)
+ 801fdf4:	dc000715 	stw	r16,28(sp)
+ 801fdf8:	df000904 	addi	fp,sp,36
+ 801fdfc:	e13ffd15 	stw	r4,-12(fp)
+ 801fe00:	e17ffc15 	stw	r5,-16(fp)
+ 801fe04:	3009883a 	mov	r4,r6
+ 801fe08:	380b883a 	mov	r5,r7
+ 801fe0c:	e0c00217 	ldw	r3,8(fp)
+ 801fe10:	e0800317 	ldw	r2,12(fp)
+ 801fe14:	e13ffb05 	stb	r4,-20(fp)
+ 801fe18:	2809883a 	mov	r4,r5
+ 801fe1c:	e13ffa05 	stb	r4,-24(fp)
+ 801fe20:	e0fff905 	stb	r3,-28(fp)
+ 801fe24:	e0bff805 	stb	r2,-32(fp)
+    
+     if (alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0)
+ 801fe28:	e0bff903 	ldbu	r2,-28(fp)
+ 801fe2c:	e0fff803 	ldbu	r3,-32(fp)
+ 801fe30:	180d883a 	mov	r6,r3
+ 801fe34:	100b883a 	mov	r5,r2
+ 801fe38:	e13ffc17 	ldw	r4,-16(fp)
+ 801fe3c:	801f8d80 	call	801f8d8 <alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits>
+ 801fe40:	10000226 	beq	r2,zero,801fe4c <alt_msgdma_start_prefetcher_with_extd_desc_list+0x68>
+    {
+        return -EINVAL;
+ 801fe44:	00bffa84 	movi	r2,-22
+ 801fe48:	00000b06 	br	801fe78 <alt_msgdma_start_prefetcher_with_extd_desc_list+0x94>
+    }
+        
+    return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, 
+ 801fe4c:	e0bffc17 	ldw	r2,-16(fp)
+ 801fe50:	1021883a 	mov	r16,r2
+ 801fe54:	0023883a 	mov	r17,zero
+ 801fe58:	e0fffb03 	ldbu	r3,-20(fp)
+ 801fe5c:	e0bffa03 	ldbu	r2,-24(fp)
+ 801fe60:	d8800015 	stw	r2,0(sp)
+ 801fe64:	180f883a 	mov	r7,r3
+ 801fe68:	800b883a 	mov	r5,r16
+ 801fe6c:	880d883a 	mov	r6,r17
+ 801fe70:	e13ffd17 	ldw	r4,-12(fp)
+ 801fe74:	801fa240 	call	801fa24 <alt_msgdma_start_prefetcher_with_list_addr>
+            park_mode_en, poll_en);
+}
+ 801fe78:	e6fffe04 	addi	sp,fp,-8
+ 801fe7c:	dfc00317 	ldw	ra,12(sp)
+ 801fe80:	df000217 	ldw	fp,8(sp)
+ 801fe84:	dc400117 	ldw	r17,4(sp)
+ 801fe88:	dc000017 	ldw	r16,0(sp)
+ 801fe8c:	dec00404 	addi	sp,sp,16
+ 801fe90:	f800283a 	ret
+
+0801fe94 <alt_msgdma_open>:
+ * Returns:
+ * - Pointer to msgdma device instance structure, or null if the device
+ *   could not be opened.
+ */
+alt_msgdma_dev* alt_msgdma_open (const char* name)
+{
+ 801fe94:	defffc04 	addi	sp,sp,-16
+ 801fe98:	dfc00315 	stw	ra,12(sp)
+ 801fe9c:	df000215 	stw	fp,8(sp)
+ 801fea0:	df000204 	addi	fp,sp,8
+ 801fea4:	e13ffe15 	stw	r4,-8(fp)
+    alt_msgdma_dev* dev = NULL;
+ 801fea8:	e03fff15 	stw	zero,-4(fp)
+
+    dev = (alt_msgdma_dev*) alt_find_dev (name, &alt_msgdma_list);
+ 801feac:	d1600b04 	addi	r5,gp,-32724
+ 801feb0:	e13ffe17 	ldw	r4,-8(fp)
+ 801feb4:	80374040 	call	8037404 <alt_find_dev>
+ 801feb8:	e0bfff15 	stw	r2,-4(fp)
+
+    if (NULL == dev)
+ 801febc:	e0bfff17 	ldw	r2,-4(fp)
+ 801fec0:	1000041e 	bne	r2,zero,801fed4 <alt_msgdma_open+0x40>
+    {
+        ALT_ERRNO = ENODEV;
+ 801fec4:	801e09c0 	call	801e09c <alt_get_errno>
+ 801fec8:	1007883a 	mov	r3,r2
+ 801fecc:	008004c4 	movi	r2,19
+ 801fed0:	18800015 	stw	r2,0(r3)
+    }
+
+    return dev;
+ 801fed4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 801fed8:	e037883a 	mov	sp,fp
+ 801fedc:	dfc00117 	ldw	ra,4(sp)
+ 801fee0:	df000017 	ldw	fp,0(sp)
+ 801fee4:	dec00204 	addi	sp,sp,8
+ 801fee8:	f800283a 	ret
+
+0801feec <alt_msgdma_init>:
+ * This routine disables interrupts, descriptor processing,
+ * registers a specific instance of the device with the HAL,
+ * and installs an interrupt handler for the device.
+ */
+void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq)
+{
+ 801feec:	defff604 	addi	sp,sp,-40
+ 801fef0:	dfc00915 	stw	ra,36(sp)
+ 801fef4:	df000815 	stw	fp,32(sp)
+ 801fef8:	df000804 	addi	fp,sp,32
+ 801fefc:	e13ffb15 	stw	r4,-20(fp)
+ 801ff00:	e17ffa15 	stw	r5,-24(fp)
+ 801ff04:	e1bff915 	stw	r6,-28(fp)
+    extern alt_llist alt_msgdma_list;
+    alt_u32 temporary_control;
+    int error;
+
+    if (dev->prefetcher_enable)
+ 801ff08:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff0c:	10801783 	ldbu	r2,94(r2)
+ 801ff10:	10803fcc 	andi	r2,r2,255
+ 801ff14:	10000a26 	beq	r2,zero,801ff40 <alt_msgdma_init+0x54>
+    {
+        /* start prefetcher reset sequence */
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, 
+ 801ff18:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff1c:	10800617 	ldw	r2,24(r2)
+ 801ff20:	00c00104 	movi	r3,4
+ 801ff24:	10c00035 	stwio	r3,0(r2)
+                ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
+        /* wait until hw clears the bit */
+        while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
+ 801ff28:	0001883a 	nop
+ 801ff2c:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff30:	10800617 	ldw	r2,24(r2)
+ 801ff34:	10800037 	ldwio	r2,0(r2)
+ 801ff38:	1080010c 	andi	r2,r2,4
+ 801ff3c:	103ffb1e 	bne	r2,zero,801ff2c <alt_msgdma_init+0x40>
+    }    
+    
+    /* Reset the registers and FIFOs of the dispatcher and master modules */
+    /* set the reset bit, no need to read the control register first since 
+    this write is going to clear it out */
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK);
+ 801ff40:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff44:	10800317 	ldw	r2,12(r2)
+ 801ff48:	10800104 	addi	r2,r2,4
+ 801ff4c:	00c00084 	movi	r3,2
+ 801ff50:	10c00035 	stwio	r3,0(r2)
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+ 801ff54:	0001883a 	nop
+ 801ff58:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff5c:	10800317 	ldw	r2,12(r2)
+ 801ff60:	10800037 	ldwio	r2,0(r2)
+            & ALTERA_MSGDMA_CSR_RESET_STATE_MASK));
+ 801ff64:	1080100c 	andi	r2,r2,64
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+ 801ff68:	103ffb1e 	bne	r2,zero,801ff58 <alt_msgdma_init+0x6c>
+    * Disable interrupts, halt descriptor processing,
+    * and clear status register content
+    */
+
+    /* disable global interrupt */
+    temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+ 801ff6c:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff70:	10800317 	ldw	r2,12(r2)
+ 801ff74:	10800104 	addi	r2,r2,4
+ 801ff78:	10800037 	ldwio	r2,0(r2)
+            & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+ 801ff7c:	1007883a 	mov	r3,r2
+    temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+ 801ff80:	00bffbc4 	movi	r2,-17
+ 801ff84:	1884703a 	and	r2,r3,r2
+ 801ff88:	e0bfff15 	stw	r2,-4(fp)
+    /* stopping descriptor */
+    temporary_control |= ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+ 801ff8c:	e0bfff17 	ldw	r2,-4(fp)
+ 801ff90:	10800814 	ori	r2,r2,32
+ 801ff94:	e0bfff15 	stw	r2,-4(fp)
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+ 801ff98:	e0bffb17 	ldw	r2,-20(fp)
+ 801ff9c:	10800317 	ldw	r2,12(r2)
+ 801ffa0:	10800104 	addi	r2,r2,4
+ 801ffa4:	e0ffff17 	ldw	r3,-4(fp)
+ 801ffa8:	10c00035 	stwio	r3,0(r2)
+
+    /* clear the CSR status register */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, 
+ 801ffac:	e0bffb17 	ldw	r2,-20(fp)
+ 801ffb0:	10800317 	ldw	r2,12(r2)
+ 801ffb4:	e0fffb17 	ldw	r3,-20(fp)
+ 801ffb8:	18c00317 	ldw	r3,12(r3)
+ 801ffbc:	18c00037 	ldwio	r3,0(r3)
+ 801ffc0:	10c00035 	stwio	r3,0(r2)
+            IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+    
+    if (dev->prefetcher_enable)
+ 801ffc4:	e0bffb17 	ldw	r2,-20(fp)
+ 801ffc8:	10801783 	ldbu	r2,94(r2)
+ 801ffcc:	10803fcc 	andi	r2,r2,255
+ 801ffd0:	10000826 	beq	r2,zero,801fff4 <alt_msgdma_init+0x108>
+    {
+        /* clear all status bits that are set, since theyre W1C */
+        IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, 
+ 801ffd4:	e0bffb17 	ldw	r2,-20(fp)
+ 801ffd8:	10800617 	ldw	r2,24(r2)
+ 801ffdc:	10800404 	addi	r2,r2,16
+ 801ffe0:	e0fffb17 	ldw	r3,-20(fp)
+ 801ffe4:	18c00617 	ldw	r3,24(r3)
+ 801ffe8:	18c00404 	addi	r3,r3,16
+ 801ffec:	18c00037 	ldwio	r3,0(r3)
+ 801fff0:	10c00035 	stwio	r3,0(r2)
+                IORD_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base));
+    }
+
+    /* Register this instance of the msgdma controller with HAL */
+    alt_dev_llist_insert((alt_dev_llist*) dev, &alt_msgdma_list);
+ 801fff4:	d1600b04 	addi	r5,gp,-32724
+ 801fff8:	e13ffb17 	ldw	r4,-20(fp)
+ 801fffc:	80372a00 	call	80372a0 <alt_dev_llist_insert>
+
+    /*
+     * Creating semaphores used to protect access to the registers 
+     * when running in a multi-threaded environment.
+     */
+    error = ALT_SEM_CREATE (&dev->regs_lock, 1);
+ 8020000:	e0bffb17 	ldw	r2,-20(fp)
+ 8020004:	10801804 	addi	r2,r2,96
+ 8020008:	e0bffd15 	stw	r2,-12(fp)
+ 802000c:	00800044 	movi	r2,1
+ 8020010:	e0bffc8d 	sth	r2,-14(fp)
+  *sem = OSSemCreate (value);
+ 8020014:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8020018:	1009883a 	mov	r4,r2
+ 802001c:	80157740 	call	8015774 <OSSemCreate>
+ 8020020:	1007883a 	mov	r3,r2
+ 8020024:	e0bffd17 	ldw	r2,-12(fp)
+ 8020028:	10c00015 	stw	r3,0(r2)
+  return *sem ? 0 : -1;
+ 802002c:	e0bffd17 	ldw	r2,-12(fp)
+ 8020030:	10800017 	ldw	r2,0(r2)
+ 8020034:	10000226 	beq	r2,zero,8020040 <alt_msgdma_init+0x154>
+ 8020038:	0005883a 	mov	r2,zero
+ 802003c:	00000106 	br	8020044 <alt_msgdma_init+0x158>
+ 8020040:	00bfffc4 	movi	r2,-1
+ 8020044:	e0bffe15 	stw	r2,-8(fp)
+            
+    if (!error)
+ 8020048:	e0bffe17 	ldw	r2,-8(fp)
+ 802004c:	1000081e 	bne	r2,zero,8020070 <alt_msgdma_init+0x184>
+    {        
+        /* Install IRQ handler */
+        alt_ic_isr_register(ic_id, irq, alt_msgdma_irq, dev, 0x0);
+ 8020050:	d8000015 	stw	zero,0(sp)
+ 8020054:	e1fffb17 	ldw	r7,-20(fp)
+ 8020058:	018200b4 	movhi	r6,2050
+ 802005c:	31b8a604 	addi	r6,r6,-7528
+ 8020060:	e17ff917 	ldw	r5,-28(fp)
+ 8020064:	e13ffa17 	ldw	r4,-24(fp)
+ 8020068:	80374940 	call	8037494 <alt_ic_isr_register>
+    else
+    {
+        alt_printf("failed to create semaphores\n");
+    }
+    
+    return;
+ 802006c:	00000406 	br	8020080 <alt_msgdma_init+0x194>
+        alt_printf("failed to create semaphores\n");
+ 8020070:	01020174 	movhi	r4,2053
+ 8020074:	2125c204 	addi	r4,r4,-26872
+ 8020078:	8037a9c0 	call	8037a9c <alt_printf>
+    return;
+ 802007c:	0001883a 	nop
+
+}
+ 8020080:	e037883a 	mov	sp,fp
+ 8020084:	dfc00117 	ldw	ra,4(sp)
+ 8020088:	df000017 	ldw	fp,0(sp)
+ 802008c:	dec00204 	addi	sp,sp,8
+ 8020090:	f800283a 	ret
+
+08020094 <alt_msgdma_register_callback>:
+void alt_msgdma_register_callback(
+    alt_msgdma_dev *dev,
+    alt_msgdma_callback callback,
+    alt_u32 control,
+    void *context)
+{
+ 8020094:	defffb04 	addi	sp,sp,-20
+ 8020098:	df000415 	stw	fp,16(sp)
+ 802009c:	df000404 	addi	fp,sp,16
+ 80200a0:	e13fff15 	stw	r4,-4(fp)
+ 80200a4:	e17ffe15 	stw	r5,-8(fp)
+ 80200a8:	e1bffd15 	stw	r6,-12(fp)
+ 80200ac:	e1fffc15 	stw	r7,-16(fp)
+    dev->callback         = callback;
+ 80200b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80200b4:	e0fffe17 	ldw	r3,-8(fp)
+ 80200b8:	10c00b15 	stw	r3,44(r2)
+    dev->callback_context = context;
+ 80200bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80200c0:	e0fffc17 	ldw	r3,-16(fp)
+ 80200c4:	10c00c15 	stw	r3,48(r2)
+    dev->control          = control;
+ 80200c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80200cc:	e0fffd17 	ldw	r3,-12(fp)
+ 80200d0:	10c00d15 	stw	r3,52(r2)
+
+    return ;
+ 80200d4:	0001883a 	nop
+}
+ 80200d8:	e037883a 	mov	sp,fp
+ 80200dc:	df000017 	ldw	fp,0(sp)
+ 80200e0:	dec00104 	addi	sp,sp,4
+ 80200e4:	f800283a 	ret
+
+080200e8 <alt_msgdma_standard_descriptor_async_transfer>:
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+int alt_msgdma_standard_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc)
+{
+ 80200e8:	defffc04 	addi	sp,sp,-16
+ 80200ec:	dfc00315 	stw	ra,12(sp)
+ 80200f0:	df000215 	stw	fp,8(sp)
+ 80200f4:	df000204 	addi	fp,sp,8
+ 80200f8:	e13fff15 	stw	r4,-4(fp)
+ 80200fc:	e17ffe15 	stw	r5,-8(fp)
+   /*
+   * Error detection/handling should be performed at the application
+   * or callback level as appropriate.
+   */
+    return alt_msgdma_descriptor_async_transfer(dev, desc, NULL);
+ 8020100:	000d883a 	mov	r6,zero
+ 8020104:	e17ffe17 	ldw	r5,-8(fp)
+ 8020108:	e13fff17 	ldw	r4,-4(fp)
+ 802010c:	801e5fc0 	call	801e5fc <alt_msgdma_descriptor_async_transfer>
+
+}
+ 8020110:	e037883a 	mov	sp,fp
+ 8020114:	dfc00117 	ldw	ra,4(sp)
+ 8020118:	df000017 	ldw	fp,0(sp)
+ 802011c:	dec00204 	addi	sp,sp,8
+ 8020120:	f800283a 	ret
+
+08020124 <alt_msgdma_extended_descriptor_async_transfer>:
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+int alt_msgdma_extended_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc)
+{
+ 8020124:	defffc04 	addi	sp,sp,-16
+ 8020128:	dfc00315 	stw	ra,12(sp)
+ 802012c:	df000215 	stw	fp,8(sp)
+ 8020130:	df000204 	addi	fp,sp,8
+ 8020134:	e13fff15 	stw	r4,-4(fp)
+ 8020138:	e17ffe15 	stw	r5,-8(fp)
+    /*
+    * Error detection/handling should be performed at the application
+    * or callback level as appropriate.
+    */
+    return alt_msgdma_descriptor_async_transfer(dev, NULL, desc);
+ 802013c:	e1bffe17 	ldw	r6,-8(fp)
+ 8020140:	000b883a 	mov	r5,zero
+ 8020144:	e13fff17 	ldw	r4,-4(fp)
+ 8020148:	801e5fc0 	call	801e5fc <alt_msgdma_descriptor_async_transfer>
+}
+ 802014c:	e037883a 	mov	sp,fp
+ 8020150:	dfc00117 	ldw	ra,4(sp)
+ 8020154:	df000017 	ldw	fp,0(sp)
+ 8020158:	dec00204 	addi	sp,sp,8
+ 802015c:	f800283a 	ret
+
+08020160 <alt_msgdma_standard_descriptor_sync_transfer>:
+ *           return -ETIME (Time out and skipping the looping after 5 msec)
+ */
+int alt_msgdma_standard_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc)
+{
+ 8020160:	defffc04 	addi	sp,sp,-16
+ 8020164:	dfc00315 	stw	ra,12(sp)
+ 8020168:	df000215 	stw	fp,8(sp)
+ 802016c:	df000204 	addi	fp,sp,8
+ 8020170:	e13fff15 	stw	r4,-4(fp)
+ 8020174:	e17ffe15 	stw	r5,-8(fp)
+    return alt_msgdma_descriptor_sync_transfer(dev, desc, NULL);
+ 8020178:	000d883a 	mov	r6,zero
+ 802017c:	e17ffe17 	ldw	r5,-8(fp)
+ 8020180:	e13fff17 	ldw	r4,-4(fp)
+ 8020184:	801e9380 	call	801e938 <alt_msgdma_descriptor_sync_transfer>
+}
+ 8020188:	e037883a 	mov	sp,fp
+ 802018c:	dfc00117 	ldw	ra,4(sp)
+ 8020190:	df000017 	ldw	fp,0(sp)
+ 8020194:	dec00204 	addi	sp,sp,8
+ 8020198:	f800283a 	ret
+
+0802019c <alt_msgdma_extended_descriptor_sync_transfer>:
+ *           return -ETIME (Time out and skipping the looping after 5 msec)
+ */
+int alt_msgdma_extended_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc)
+{
+ 802019c:	defffc04 	addi	sp,sp,-16
+ 80201a0:	dfc00315 	stw	ra,12(sp)
+ 80201a4:	df000215 	stw	fp,8(sp)
+ 80201a8:	df000204 	addi	fp,sp,8
+ 80201ac:	e13fff15 	stw	r4,-4(fp)
+ 80201b0:	e17ffe15 	stw	r5,-8(fp)
+    return alt_msgdma_descriptor_sync_transfer(dev, NULL, desc);
+ 80201b4:	e1bffe17 	ldw	r6,-8(fp)
+ 80201b8:	000b883a 	mov	r5,zero
+ 80201bc:	e13fff17 	ldw	r4,-4(fp)
+ 80201c0:	801e9380 	call	801e938 <alt_msgdma_descriptor_sync_transfer>
+}
+ 80201c4:	e037883a 	mov	sp,fp
+ 80201c8:	dfc00117 	ldw	ra,4(sp)
+ 80201cc:	df000017 	ldw	fp,0(sp)
+ 80201d0:	dec00204 	addi	sp,sp,8
+ 80201d4:	f800283a 	ret
+
+080201d8 <alt_flash_device_register>:
+{
+ 80201d8:	defffd04 	addi	sp,sp,-12
+ 80201dc:	dfc00215 	stw	ra,8(sp)
+ 80201e0:	df000115 	stw	fp,4(sp)
+ 80201e4:	df000104 	addi	fp,sp,4
+ 80201e8:	e13fff15 	stw	r4,-4(fp)
+  return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list);
+ 80201ec:	d1600404 	addi	r5,gp,-32752
+ 80201f0:	e13fff17 	ldw	r4,-4(fp)
+ 80201f4:	80372a00 	call	80372a0 <alt_dev_llist_insert>
+}
+ 80201f8:	e037883a 	mov	sp,fp
+ 80201fc:	dfc00117 	ldw	ra,4(sp)
+ 8020200:	df000017 	ldw	fp,0(sp)
+ 8020204:	dec00204 	addi	sp,sp,8
+ 8020208:	f800283a 	ret
+
+0802020c <alt_onchip_flash_read>:
+    alt_flash_dev *flash_info,
+    int           offset,
+    void          *dest_addr,
+    int           length
+)
+{
+ 802020c:	defff704 	addi	sp,sp,-36
+ 8020210:	dfc00815 	stw	ra,32(sp)
+ 8020214:	df000715 	stw	fp,28(sp)
+ 8020218:	df000704 	addi	fp,sp,28
+ 802021c:	e13ffc15 	stw	r4,-16(fp)
+ 8020220:	e17ffb15 	stw	r5,-20(fp)
+ 8020224:	e1bffa15 	stw	r6,-24(fp)
+ 8020228:	e1fff915 	stw	r7,-28(fp)
+    int ret_code = 0;
+ 802022c:	e03fff15 	stw	zero,-4(fp)
+    alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info;
+ 8020230:	e0bffc17 	ldw	r2,-16(fp)
+ 8020234:	e0bffe15 	stw	r2,-8(fp)
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if ((offset >= flash->dev.length) || ((offset+length) > flash->dev.length)) {
+ 8020238:	e0bffe17 	ldw	r2,-8(fp)
+ 802023c:	10800b17 	ldw	r2,44(r2)
+ 8020240:	e0fffb17 	ldw	r3,-20(fp)
+ 8020244:	1880060e 	bge	r3,r2,8020260 <alt_onchip_flash_read+0x54>
+ 8020248:	e0fffb17 	ldw	r3,-20(fp)
+ 802024c:	e0bff917 	ldw	r2,-28(fp)
+ 8020250:	1885883a 	add	r2,r3,r2
+ 8020254:	e0fffe17 	ldw	r3,-8(fp)
+ 8020258:	18c00b17 	ldw	r3,44(r3)
+ 802025c:	1880020e 	bge	r3,r2,8020268 <alt_onchip_flash_read+0x5c>
+        return -EFAULT;
+ 8020260:	00bffc84 	movi	r2,-14
+ 8020264:	00001706 	br	80202c4 <alt_onchip_flash_read+0xb8>
+    }
+    
+    memcpy(dest_addr, (alt_u8*)flash->dev.base_addr+offset, length);
+ 8020268:	e0bffe17 	ldw	r2,-8(fp)
+ 802026c:	10c00a17 	ldw	r3,40(r2)
+ 8020270:	e0bffb17 	ldw	r2,-20(fp)
+ 8020274:	1885883a 	add	r2,r3,r2
+ 8020278:	e0fff917 	ldw	r3,-28(fp)
+ 802027c:	180d883a 	mov	r6,r3
+ 8020280:	100b883a 	mov	r5,r2
+ 8020284:	e13ffa17 	ldw	r4,-24(fp)
+ 8020288:	80086b80 	call	80086b8 <memcpy>
+
+    if (NULL != flash->csr_base) {
+ 802028c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020290:	10802f17 	ldw	r2,188(r2)
+ 8020294:	10000a26 	beq	r2,zero,80202c0 <alt_onchip_flash_read+0xb4>
+        int read_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_READ_MSK;
+ 8020298:	e0bffe17 	ldw	r2,-8(fp)
+ 802029c:	10802f17 	ldw	r2,188(r2)
+ 80202a0:	10800037 	ldwio	r2,0(r2)
+ 80202a4:	1080010c 	andi	r2,r2,4
+ 80202a8:	e0bffd15 	stw	r2,-12(fp)
+        if (read_status != ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED) {
+ 80202ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80202b0:	10800120 	cmpeqi	r2,r2,4
+ 80202b4:	1000021e 	bne	r2,zero,80202c0 <alt_onchip_flash_read+0xb4>
+            /* Read failed.  Return error.*/
+            ret_code = -EIO;
+ 80202b8:	00bffec4 	movi	r2,-5
+ 80202bc:	e0bfff15 	stw	r2,-4(fp)
+        }
+    }
+    return ret_code;
+ 80202c0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80202c4:	e037883a 	mov	sp,fp
+ 80202c8:	dfc00117 	ldw	ra,4(sp)
+ 80202cc:	df000017 	ldw	fp,0(sp)
+ 80202d0:	dec00204 	addi	sp,sp,8
+ 80202d4:	f800283a 	ret
+
+080202d8 <alt_onchip_flash_get_info>:
+(
+    alt_flash_fd *fd,
+    flash_region **info,
+    int          *number_of_regions
+)
+{
+ 80202d8:	defffa04 	addi	sp,sp,-24
+ 80202dc:	df000515 	stw	fp,20(sp)
+ 80202e0:	df000504 	addi	fp,sp,20
+ 80202e4:	e13ffd15 	stw	r4,-12(fp)
+ 80202e8:	e17ffc15 	stw	r5,-16(fp)
+ 80202ec:	e1bffb15 	stw	r6,-20(fp)
+    int ret_code = 0;
+ 80202f0:	e03fff15 	stw	zero,-4(fp)
+
+    alt_flash_dev* flash = (alt_flash_dev*)fd;
+ 80202f4:	e0bffd17 	ldw	r2,-12(fp)
+ 80202f8:	e0bffe15 	stw	r2,-8(fp)
+
+    if (NULL != number_of_regions)
+ 80202fc:	e0bffb17 	ldw	r2,-20(fp)
+ 8020300:	10000426 	beq	r2,zero,8020314 <alt_onchip_flash_get_info+0x3c>
+    {
+        /* Pass the number of region to user */
+        *number_of_regions = flash->number_of_regions;
+ 8020304:	e0bffe17 	ldw	r2,-8(fp)
+ 8020308:	10c00c17 	ldw	r3,48(r2)
+ 802030c:	e0bffb17 	ldw	r2,-20(fp)
+ 8020310:	10c00015 	stw	r3,0(r2)
+    }
+
+    if (!flash->number_of_regions)
+ 8020314:	e0bffe17 	ldw	r2,-8(fp)
+ 8020318:	10800c17 	ldw	r2,48(r2)
+ 802031c:	1000031e 	bne	r2,zero,802032c <alt_onchip_flash_get_info+0x54>
+    {
+        ret_code = -ENOMEM;
+ 8020320:	00bffd04 	movi	r2,-12
+ 8020324:	e0bfff15 	stw	r2,-4(fp)
+ 8020328:	00000d06 	br	8020360 <alt_onchip_flash_get_info+0x88>
+    }
+    else if (flash->number_of_regions > ALT_MAX_NUMBER_OF_FLASH_REGIONS)
+ 802032c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020330:	10800c17 	ldw	r2,48(r2)
+ 8020334:	10800250 	cmplti	r2,r2,9
+ 8020338:	1000031e 	bne	r2,zero,8020348 <alt_onchip_flash_get_info+0x70>
+    {
+        ret_code = -EFAULT;
+ 802033c:	00bffc84 	movi	r2,-14
+ 8020340:	e0bfff15 	stw	r2,-4(fp)
+ 8020344:	00000606 	br	8020360 <alt_onchip_flash_get_info+0x88>
+    }
+    else
+    {
+        if (NULL != info)
+ 8020348:	e0bffc17 	ldw	r2,-16(fp)
+ 802034c:	10000426 	beq	r2,zero,8020360 <alt_onchip_flash_get_info+0x88>
+        {
+            /* Pass the table of erase blocks to user */
+            *info = &flash->region_info[0];
+ 8020350:	e0bffe17 	ldw	r2,-8(fp)
+ 8020354:	10c00d04 	addi	r3,r2,52
+ 8020358:	e0bffc17 	ldw	r2,-16(fp)
+ 802035c:	10c00015 	stw	r3,0(r2)
+        }
+    }
+
+    return ret_code;
+ 8020360:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8020364:	e037883a 	mov	sp,fp
+ 8020368:	df000017 	ldw	fp,0(sp)
+ 802036c:	dec00104 	addi	sp,sp,4
+ 8020370:	f800283a 	ret
+
+08020374 <alt_onchip_flash_erase_block>:
+int alt_onchip_flash_erase_block
+(
+    alt_flash_dev *flash_info,
+    int           block_offset
+)
+{
+ 8020374:	defff904 	addi	sp,sp,-28
+ 8020378:	dfc00615 	stw	ra,24(sp)
+ 802037c:	df000515 	stw	fp,20(sp)
+ 8020380:	df000504 	addi	fp,sp,20
+ 8020384:	e13ffc15 	stw	r4,-16(fp)
+ 8020388:	e17ffb15 	stw	r5,-20(fp)
+    int ret_code = 0;
+ 802038c:	e03fff15 	stw	zero,-4(fp)
+    alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info;
+ 8020390:	e0bffc17 	ldw	r2,-16(fp)
+ 8020394:	e0bffe15 	stw	r2,-8(fp)
+    int page_address;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if (block_offset >= flash->dev.length) {
+ 8020398:	e0bffe17 	ldw	r2,-8(fp)
+ 802039c:	10800b17 	ldw	r2,44(r2)
+ 80203a0:	e0fffb17 	ldw	r3,-20(fp)
+ 80203a4:	18800216 	blt	r3,r2,80203b0 <alt_onchip_flash_erase_block+0x3c>
+        return -EFAULT;
+ 80203a8:	00bffc84 	movi	r2,-14
+ 80203ac:	00004606 	br	80204c8 <alt_onchip_flash_erase_block+0x154>
+    }
+
+    /* Make sure IP support write and erase operation */
+    if ((flash->csr_base == NULL) || (flash->is_read_only)) {
+ 80203b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80203b4:	10802f17 	ldw	r2,188(r2)
+ 80203b8:	10000326 	beq	r2,zero,80203c8 <alt_onchip_flash_erase_block+0x54>
+ 80203bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80203c0:	10802e17 	ldw	r2,184(r2)
+ 80203c4:	10000226 	beq	r2,zero,80203d0 <alt_onchip_flash_erase_block+0x5c>
+        return -ENODEV;
+ 80203c8:	00bffb44 	movi	r2,-19
+ 80203cc:	00003e06 	br	80204c8 <alt_onchip_flash_erase_block+0x154>
+    }
+
+    /* The block_offset must be page size aligned */
+    if ((block_offset & (flash->page_size - 1)) != 0)
+ 80203d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80203d4:	10803f17 	ldw	r2,252(r2)
+ 80203d8:	10ffffc4 	addi	r3,r2,-1
+ 80203dc:	e0bffb17 	ldw	r2,-20(fp)
+ 80203e0:	1884703a 	and	r2,r3,r2
+ 80203e4:	10000226 	beq	r2,zero,80203f0 <alt_onchip_flash_erase_block+0x7c>
+    {
+        /* The address is not aligned */
+        return -EINVAL;
+ 80203e8:	00bffa84 	movi	r2,-22
+ 80203ec:	00003606 	br	80204c8 <alt_onchip_flash_erase_block+0x154>
+    }
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+ 80203f0:	e13ffe17 	ldw	r4,-8(fp)
+ 80203f4:	8020f200 	call	8020f20 <alt_onchip_flash_poll_for_status_to_go_idle>
+ 80203f8:	e0bfff15 	stw	r2,-4(fp)
+    if (ret_code != 0)
+ 80203fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8020400:	10000226 	beq	r2,zero,802040c <alt_onchip_flash_erase_block+0x98>
+    {
+        return ret_code;
+ 8020404:	e0bfff17 	ldw	r2,-4(fp)
+ 8020408:	00002f06 	br	80204c8 <alt_onchip_flash_erase_block+0x154>
+    }
+
+    /* Enable write and erase operation */
+    ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+ 802040c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020410:	10802f17 	ldw	r2,188(r2)
+ 8020414:	10c00104 	addi	r3,r2,4
+ 8020418:	e0bffe17 	ldw	r2,-8(fp)
+ 802041c:	10802f17 	ldw	r2,188(r2)
+ 8020420:	10800104 	addi	r2,r2,4
+ 8020424:	10800037 	ldwio	r2,0(r2)
+ 8020428:	113c002c 	andhi	r4,r2,61440
+ 802042c:	00802034 	movhi	r2,128
+ 8020430:	10bfffc4 	addi	r2,r2,-1
+ 8020434:	2084b03a 	or	r2,r4,r2
+ 8020438:	18800035 	stwio	r2,0(r3)
+
+    /* Calculate Page erase address, it is 32bit word addressing*/
+    page_address = block_offset / 4;
+ 802043c:	e0bffb17 	ldw	r2,-20(fp)
+ 8020440:	1000010e 	bge	r2,zero,8020448 <alt_onchip_flash_erase_block+0xd4>
+ 8020444:	108000c4 	addi	r2,r2,3
+ 8020448:	1005d0ba 	srai	r2,r2,2
+ 802044c:	e0bffd15 	stw	r2,-12(fp)
+
+    /* Perform Page erase operation */
+    ALTERA_ONCHIP_FLASH_PAGE_ERASE(flash->csr_base, page_address);
+ 8020450:	e0bffe17 	ldw	r2,-8(fp)
+ 8020454:	10802f17 	ldw	r2,188(r2)
+ 8020458:	10800104 	addi	r2,r2,4
+ 802045c:	e0fffe17 	ldw	r3,-8(fp)
+ 8020460:	18c02f17 	ldw	r3,188(r3)
+ 8020464:	18c00104 	addi	r3,r3,4
+ 8020468:	18c00037 	ldwio	r3,0(r3)
+ 802046c:	193c002c 	andhi	r4,r3,61440
+ 8020470:	e0fffd17 	ldw	r3,-12(fp)
+ 8020474:	18c01c34 	orhi	r3,r3,112
+ 8020478:	20c6b03a 	or	r3,r4,r3
+ 802047c:	10c00035 	stwio	r3,0(r2)
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+ 8020480:	e13ffe17 	ldw	r4,-8(fp)
+ 8020484:	8020f200 	call	8020f20 <alt_onchip_flash_poll_for_status_to_go_idle>
+ 8020488:	e0bfff15 	stw	r2,-4(fp)
+
+    /* Wait until flash controller indicate erase passed */
+    ret_code = alt_onchip_flash_poll_for_status_erase_passed(flash);
+ 802048c:	e13ffe17 	ldw	r4,-8(fp)
+ 8020490:	8020fb00 	call	8020fb0 <alt_onchip_flash_poll_for_status_erase_passed>
+ 8020494:	e0bfff15 	stw	r2,-4(fp)
+
+    /* Disable write and erase operation */
+    ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+ 8020498:	e0bffe17 	ldw	r2,-8(fp)
+ 802049c:	10802f17 	ldw	r2,188(r2)
+ 80204a0:	10c00104 	addi	r3,r2,4
+ 80204a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80204a8:	10802f17 	ldw	r2,188(r2)
+ 80204ac:	10800104 	addi	r2,r2,4
+ 80204b0:	11000037 	ldwio	r4,0(r2)
+ 80204b4:	00840034 	movhi	r2,4096
+ 80204b8:	10bfffc4 	addi	r2,r2,-1
+ 80204bc:	2084b03a 	or	r2,r4,r2
+ 80204c0:	18800035 	stwio	r2,0(r3)
+
+    return ret_code;
+ 80204c4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80204c8:	e037883a 	mov	sp,fp
+ 80204cc:	dfc00117 	ldw	ra,4(sp)
+ 80204d0:	df000017 	ldw	fp,0(sp)
+ 80204d4:	dec00204 	addi	sp,sp,8
+ 80204d8:	f800283a 	ret
+
+080204dc <alt_onchip_flash_write_block>:
+    int           block_offset,
+    int           data_offset,
+    const void    *data,
+    int           length
+)
+{
+ 80204dc:	defff204 	addi	sp,sp,-56
+ 80204e0:	dfc00d15 	stw	ra,52(sp)
+ 80204e4:	df000c15 	stw	fp,48(sp)
+ 80204e8:	df000c04 	addi	fp,sp,48
+ 80204ec:	e13ff715 	stw	r4,-36(fp)
+ 80204f0:	e17ff615 	stw	r5,-40(fp)
+ 80204f4:	e1bff515 	stw	r6,-44(fp)
+ 80204f8:	e1fff415 	stw	r7,-48(fp)
+    int ret_code = 0;
+ 80204fc:	e03fff15 	stw	zero,-4(fp)
+    alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info;
+ 8020500:	e0bff717 	ldw	r2,-36(fp)
+ 8020504:	e0bffb15 	stw	r2,-20(fp)
+    int buffer_offset = 0;
+ 8020508:	e03ffe15 	stw	zero,-8(fp)
+    int length_of_current_write;
+    int current_data_offset = data_offset;
+ 802050c:	e0bff517 	ldw	r2,-44(fp)
+ 8020510:	e0bffd15 	stw	r2,-12(fp)
+    int next_data_offset;
+    alt_u32 chunk_of_data;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if (
+        (block_offset >= flash->dev.length) ||
+ 8020514:	e0bffb17 	ldw	r2,-20(fp)
+ 8020518:	10800b17 	ldw	r2,44(r2)
+    if (
+ 802051c:	e0fff617 	ldw	r3,-40(fp)
+ 8020520:	18800a0e 	bge	r3,r2,802054c <alt_onchip_flash_write_block+0x70>
+        (data_offset >= flash->dev.length) ||
+ 8020524:	e0bffb17 	ldw	r2,-20(fp)
+ 8020528:	10800b17 	ldw	r2,44(r2)
+        (block_offset >= flash->dev.length) ||
+ 802052c:	e0fff517 	ldw	r3,-44(fp)
+ 8020530:	1880060e 	bge	r3,r2,802054c <alt_onchip_flash_write_block+0x70>
+        (length > (flash->dev.length - data_offset))
+ 8020534:	e0bffb17 	ldw	r2,-20(fp)
+ 8020538:	10c00b17 	ldw	r3,44(r2)
+ 802053c:	e0bff517 	ldw	r2,-44(fp)
+ 8020540:	1887c83a 	sub	r3,r3,r2
+        (data_offset >= flash->dev.length) ||
+ 8020544:	e0800217 	ldw	r2,8(fp)
+ 8020548:	1880020e 	bge	r3,r2,8020554 <alt_onchip_flash_write_block+0x78>
+    ) {
+        return -EFAULT;
+ 802054c:	00bffc84 	movi	r2,-14
+ 8020550:	00009306 	br	80207a0 <alt_onchip_flash_write_block+0x2c4>
+    }
+
+    /* Make sure IP support support write and erase operation */
+    if ((flash->csr_base == NULL) || (flash->is_read_only != 0)) {
+ 8020554:	e0bffb17 	ldw	r2,-20(fp)
+ 8020558:	10802f17 	ldw	r2,188(r2)
+ 802055c:	10000326 	beq	r2,zero,802056c <alt_onchip_flash_write_block+0x90>
+ 8020560:	e0bffb17 	ldw	r2,-20(fp)
+ 8020564:	10802e17 	ldw	r2,184(r2)
+ 8020568:	10000226 	beq	r2,zero,8020574 <alt_onchip_flash_write_block+0x98>
+        return -ENODEV;
+ 802056c:	00bffb44 	movi	r2,-19
+ 8020570:	00008b06 	br	80207a0 <alt_onchip_flash_write_block+0x2c4>
+    }
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+ 8020574:	e13ffb17 	ldw	r4,-20(fp)
+ 8020578:	8020f200 	call	8020f20 <alt_onchip_flash_poll_for_status_to_go_idle>
+ 802057c:	e0bfff15 	stw	r2,-4(fp)
+    if (ret_code != 0)
+ 8020580:	e0bfff17 	ldw	r2,-4(fp)
+ 8020584:	10000226 	beq	r2,zero,8020590 <alt_onchip_flash_write_block+0xb4>
+    {
+        return ret_code;
+ 8020588:	e0bfff17 	ldw	r2,-4(fp)
+ 802058c:	00008406 	br	80207a0 <alt_onchip_flash_write_block+0x2c4>
+    }
+
+    /* Enable write and erase operation */
+    ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+ 8020590:	e0bffb17 	ldw	r2,-20(fp)
+ 8020594:	10802f17 	ldw	r2,188(r2)
+ 8020598:	10c00104 	addi	r3,r2,4
+ 802059c:	e0bffb17 	ldw	r2,-20(fp)
+ 80205a0:	10802f17 	ldw	r2,188(r2)
+ 80205a4:	10800104 	addi	r2,r2,4
+ 80205a8:	10800037 	ldwio	r2,0(r2)
+ 80205ac:	113c002c 	andhi	r4,r2,61440
+ 80205b0:	00802034 	movhi	r2,128
+ 80205b4:	10bfffc4 	addi	r2,r2,-1
+ 80205b8:	2084b03a 	or	r2,r4,r2
+ 80205bc:	18800035 	stwio	r2,0(r3)
+
+    /* Check data length */
+    while (length)
+ 80205c0:	00006506 	br	8020758 <alt_onchip_flash_write_block+0x27c>
+    {
+        /* Minimum write size to onchip flash is 32 bits of data */
+        chunk_of_data = 0xFFFFFFFF;
+ 80205c4:	00bfffc4 	movi	r2,-1
+ 80205c8:	e0bff815 	stw	r2,-32(fp)
+
+        /* The start of data_offset must be 4 bytes (32 bits) aligned */
+        if ((current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1)) == 0)
+ 80205cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80205d0:	108000cc 	andi	r2,r2,3
+ 80205d4:	10001e1e 	bne	r2,zero,8020650 <alt_onchip_flash_write_block+0x174>
+        {
+            /* The address is 4-byte aligned here */
+            next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+ 80205d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80205dc:	10c00104 	addi	r3,r2,4
+ 80205e0:	00bfff04 	movi	r2,-4
+ 80205e4:	1884703a 	and	r2,r3,r2
+ 80205e8:	e0bffc15 	stw	r2,-16(fp)
+            length_of_current_write = MIN(length, next_data_offset - current_data_offset);
+ 80205ec:	e0fffc17 	ldw	r3,-16(fp)
+ 80205f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80205f4:	1887c83a 	sub	r3,r3,r2
+ 80205f8:	e0800217 	ldw	r2,8(fp)
+ 80205fc:	1880010e 	bge	r3,r2,8020604 <alt_onchip_flash_write_block+0x128>
+ 8020600:	1805883a 	mov	r2,r3
+ 8020604:	e0bffa15 	stw	r2,-24(fp)
+            /* Prepare the 4 bytes chunk of data to be written */
+            memcpy(&chunk_of_data, &((alt_u8*)data)[buffer_offset], length_of_current_write);
+ 8020608:	e0bffe17 	ldw	r2,-8(fp)
+ 802060c:	e0fff417 	ldw	r3,-48(fp)
+ 8020610:	1887883a 	add	r3,r3,r2
+ 8020614:	e13ffa17 	ldw	r4,-24(fp)
+ 8020618:	e0bff804 	addi	r2,fp,-32
+ 802061c:	200d883a 	mov	r6,r4
+ 8020620:	180b883a 	mov	r5,r3
+ 8020624:	1009883a 	mov	r4,r2
+ 8020628:	80086b80 	call	80086b8 <memcpy>
+            buffer_offset += length_of_current_write;
+ 802062c:	e0fffe17 	ldw	r3,-8(fp)
+ 8020630:	e0bffa17 	ldw	r2,-24(fp)
+ 8020634:	1885883a 	add	r2,r3,r2
+ 8020638:	e0bffe15 	stw	r2,-8(fp)
+            length -= length_of_current_write;
+ 802063c:	e0c00217 	ldw	r3,8(fp)
+ 8020640:	e0bffa17 	ldw	r2,-24(fp)
+ 8020644:	1885c83a 	sub	r2,r3,r2
+ 8020648:	e0800215 	stw	r2,8(fp)
+ 802064c:	00003006 	br	8020710 <alt_onchip_flash_write_block+0x234>
+        } else {
+            /* Calculate how many padding bytes need to be added before the start of a data offset */
+            int padding = current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+ 8020650:	e0bffd17 	ldw	r2,-12(fp)
+ 8020654:	108000cc 	andi	r2,r2,3
+ 8020658:	e0bff915 	stw	r2,-28(fp)
+
+            /* Calculate new 4-byte aligned data offset */
+            current_data_offset = current_data_offset - padding;
+ 802065c:	e0fffd17 	ldw	r3,-12(fp)
+ 8020660:	e0bff917 	ldw	r2,-28(fp)
+ 8020664:	1885c83a 	sub	r2,r3,r2
+ 8020668:	e0bffd15 	stw	r2,-12(fp)
+            next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+ 802066c:	e0bffd17 	ldw	r2,-12(fp)
+ 8020670:	10c00104 	addi	r3,r2,4
+ 8020674:	00bfff04 	movi	r2,-4
+ 8020678:	1884703a 	and	r2,r3,r2
+ 802067c:	e0bffc15 	stw	r2,-16(fp)
+            length_of_current_write = MIN(length + padding, next_data_offset - current_data_offset);
+ 8020680:	e0fffc17 	ldw	r3,-16(fp)
+ 8020684:	e0bffd17 	ldw	r2,-12(fp)
+ 8020688:	1889c83a 	sub	r4,r3,r2
+ 802068c:	e0c00217 	ldw	r3,8(fp)
+ 8020690:	e0bff917 	ldw	r2,-28(fp)
+ 8020694:	1887883a 	add	r3,r3,r2
+ 8020698:	2005883a 	mov	r2,r4
+ 802069c:	1880010e 	bge	r3,r2,80206a4 <alt_onchip_flash_write_block+0x1c8>
+ 80206a0:	1805883a 	mov	r2,r3
+ 80206a4:	e0bffa15 	stw	r2,-24(fp)
+            /* Prepare the 4 bytes chunk of data to be written */
+            memcpy((void *)(((int)&chunk_of_data) + (int)padding), &((alt_u8*)data)[buffer_offset], length_of_current_write - padding);
+ 80206a8:	e0fff804 	addi	r3,fp,-32
+ 80206ac:	e0bff917 	ldw	r2,-28(fp)
+ 80206b0:	1885883a 	add	r2,r3,r2
+ 80206b4:	100f883a 	mov	r7,r2
+ 80206b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80206bc:	e0fff417 	ldw	r3,-48(fp)
+ 80206c0:	1889883a 	add	r4,r3,r2
+ 80206c4:	e0fffa17 	ldw	r3,-24(fp)
+ 80206c8:	e0bff917 	ldw	r2,-28(fp)
+ 80206cc:	1885c83a 	sub	r2,r3,r2
+ 80206d0:	100d883a 	mov	r6,r2
+ 80206d4:	200b883a 	mov	r5,r4
+ 80206d8:	3809883a 	mov	r4,r7
+ 80206dc:	80086b80 	call	80086b8 <memcpy>
+            buffer_offset += length_of_current_write - padding;
+ 80206e0:	e0fffa17 	ldw	r3,-24(fp)
+ 80206e4:	e0bff917 	ldw	r2,-28(fp)
+ 80206e8:	1885c83a 	sub	r2,r3,r2
+ 80206ec:	e0fffe17 	ldw	r3,-8(fp)
+ 80206f0:	1885883a 	add	r2,r3,r2
+ 80206f4:	e0bffe15 	stw	r2,-8(fp)
+            length -= length_of_current_write - padding;
+ 80206f8:	e0fffa17 	ldw	r3,-24(fp)
+ 80206fc:	e0bff917 	ldw	r2,-28(fp)
+ 8020700:	1885c83a 	sub	r2,r3,r2
+ 8020704:	e0c00217 	ldw	r3,8(fp)
+ 8020708:	1885c83a 	sub	r2,r3,r2
+ 802070c:	e0800215 	stw	r2,8(fp)
+        }
+
+        /* Writing to flash via IO 32 bits at a time */
+        IOWR_32DIRECT(flash->dev.base_addr, current_data_offset, chunk_of_data);
+ 8020710:	e0bffb17 	ldw	r2,-20(fp)
+ 8020714:	10c00a17 	ldw	r3,40(r2)
+ 8020718:	e0bffd17 	ldw	r2,-12(fp)
+ 802071c:	1885883a 	add	r2,r3,r2
+ 8020720:	e0fff817 	ldw	r3,-32(fp)
+ 8020724:	10c00035 	stwio	r3,0(r2)
+
+        /* Wait until flash controller idle */
+        ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+ 8020728:	e13ffb17 	ldw	r4,-20(fp)
+ 802072c:	8020f200 	call	8020f20 <alt_onchip_flash_poll_for_status_to_go_idle>
+ 8020730:	e0bfff15 	stw	r2,-4(fp)
+        if (ret_code != 0)
+ 8020734:	e0bfff17 	ldw	r2,-4(fp)
+ 8020738:	10000a1e 	bne	r2,zero,8020764 <alt_onchip_flash_write_block+0x288>
+        {
+            break;
+        }
+
+        /* Wait until flash controller indicate write passed */
+        ret_code = alt_onchip_flash_poll_for_status_write_passed(flash);
+ 802073c:	e13ffb17 	ldw	r4,-20(fp)
+ 8020740:	80210440 	call	8021044 <alt_onchip_flash_poll_for_status_write_passed>
+ 8020744:	e0bfff15 	stw	r2,-4(fp)
+        if (ret_code != 0)
+ 8020748:	e0bfff17 	ldw	r2,-4(fp)
+ 802074c:	1000071e 	bne	r2,zero,802076c <alt_onchip_flash_write_block+0x290>
+        {
+            break;
+        }
+
+        /* Prepare to write next 4 bytes */
+        current_data_offset = next_data_offset;
+ 8020750:	e0bffc17 	ldw	r2,-16(fp)
+ 8020754:	e0bffd15 	stw	r2,-12(fp)
+    while (length)
+ 8020758:	e0800217 	ldw	r2,8(fp)
+ 802075c:	103f991e 	bne	r2,zero,80205c4 <alt_onchip_flash_write_block+0xe8>
+ 8020760:	00000306 	br	8020770 <alt_onchip_flash_write_block+0x294>
+            break;
+ 8020764:	0001883a 	nop
+ 8020768:	00000106 	br	8020770 <alt_onchip_flash_write_block+0x294>
+            break;
+ 802076c:	0001883a 	nop
+    }
+
+    /* Disable write and erase operation */
+    ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+ 8020770:	e0bffb17 	ldw	r2,-20(fp)
+ 8020774:	10802f17 	ldw	r2,188(r2)
+ 8020778:	10c00104 	addi	r3,r2,4
+ 802077c:	e0bffb17 	ldw	r2,-20(fp)
+ 8020780:	10802f17 	ldw	r2,188(r2)
+ 8020784:	10800104 	addi	r2,r2,4
+ 8020788:	11000037 	ldwio	r4,0(r2)
+ 802078c:	00840034 	movhi	r2,4096
+ 8020790:	10bfffc4 	addi	r2,r2,-1
+ 8020794:	2084b03a 	or	r2,r4,r2
+ 8020798:	18800035 	stwio	r2,0(r3)
+
+    return ret_code;
+ 802079c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80207a0:	e037883a 	mov	sp,fp
+ 80207a4:	dfc00117 	ldw	ra,4(sp)
+ 80207a8:	df000017 	ldw	fp,0(sp)
+ 80207ac:	dec00204 	addi	sp,sp,8
+ 80207b0:	f800283a 	ret
+
+080207b4 <alt_onchip_flash_write>:
+    alt_flash_dev *flash_info,
+    int           offset,
+    const void    *src_addr,
+    int           length
+)
+{
+ 80207b4:	defff104 	addi	sp,sp,-60
+ 80207b8:	dfc00e15 	stw	ra,56(sp)
+ 80207bc:	df000d15 	stw	fp,52(sp)
+ 80207c0:	df000d04 	addi	fp,sp,52
+ 80207c4:	e13ff715 	stw	r4,-36(fp)
+ 80207c8:	e17ff615 	stw	r5,-40(fp)
+ 80207cc:	e1bff515 	stw	r6,-44(fp)
+ 80207d0:	e1fff415 	stw	r7,-48(fp)
+    int         ret_code = 0;
+ 80207d4:	e03fff15 	stw	zero,-4(fp)
+    int         i,j;
+    int         data_to_write;
+    int         current_offset;
+    int         full_length = length;
+ 80207d8:	e0bff417 	ldw	r2,-48(fp)
+ 80207dc:	e0bffb15 	stw	r2,-20(fp)
+    int         start_offset = offset;
+ 80207e0:	e0bff617 	ldw	r2,-40(fp)
+ 80207e4:	e0bffa15 	stw	r2,-24(fp)
+    alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info;
+ 80207e8:	e0bff717 	ldw	r2,-36(fp)
+ 80207ec:	e0bff915 	stw	r2,-28(fp)
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if ((offset >= flash->dev.length) || (length > (flash->dev.length - offset)))
+ 80207f0:	e0bff917 	ldw	r2,-28(fp)
+ 80207f4:	10800b17 	ldw	r2,44(r2)
+ 80207f8:	e0fff617 	ldw	r3,-40(fp)
+ 80207fc:	1880060e 	bge	r3,r2,8020818 <alt_onchip_flash_write+0x64>
+ 8020800:	e0bff917 	ldw	r2,-28(fp)
+ 8020804:	10c00b17 	ldw	r3,44(r2)
+ 8020808:	e0bff617 	ldw	r2,-40(fp)
+ 802080c:	1887c83a 	sub	r3,r3,r2
+ 8020810:	e0bff417 	ldw	r2,-48(fp)
+ 8020814:	1880020e 	bge	r3,r2,8020820 <alt_onchip_flash_write+0x6c>
+    {
+        return -EFAULT;
+ 8020818:	00bffc84 	movi	r2,-14
+ 802081c:	00009306 	br	8020a6c <alt_onchip_flash_write+0x2b8>
+    }
+
+    /*
+    * First and foremost which sectors are affected?
+    */
+    for(i=0;i<flash->dev.number_of_regions;i++)
+ 8020820:	e03ffe15 	stw	zero,-8(fp)
+ 8020824:	00008206 	br	8020a30 <alt_onchip_flash_write+0x27c>
+    {
+        /* Is it in this erase block region?*/
+        if((offset >= flash->dev.region_info[i].offset) &&
+ 8020828:	e0fff917 	ldw	r3,-28(fp)
+ 802082c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020830:	1004913a 	slli	r2,r2,4
+ 8020834:	1885883a 	add	r2,r3,r2
+ 8020838:	10800d17 	ldw	r2,52(r2)
+ 802083c:	e0fff617 	ldw	r3,-40(fp)
+ 8020840:	18807816 	blt	r3,r2,8020a24 <alt_onchip_flash_write+0x270>
+            (offset < (flash->dev.region_info[i].offset +
+ 8020844:	e0fff917 	ldw	r3,-28(fp)
+ 8020848:	e0bffe17 	ldw	r2,-8(fp)
+ 802084c:	1004913a 	slli	r2,r2,4
+ 8020850:	1885883a 	add	r2,r3,r2
+ 8020854:	10c00d17 	ldw	r3,52(r2)
+            flash->dev.region_info[i].region_size)))
+ 8020858:	e13ff917 	ldw	r4,-28(fp)
+ 802085c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020860:	1004913a 	slli	r2,r2,4
+ 8020864:	2085883a 	add	r2,r4,r2
+ 8020868:	10800e17 	ldw	r2,56(r2)
+            (offset < (flash->dev.region_info[i].offset +
+ 802086c:	1885883a 	add	r2,r3,r2
+        if((offset >= flash->dev.region_info[i].offset) &&
+ 8020870:	e0fff617 	ldw	r3,-40(fp)
+ 8020874:	18806b0e 	bge	r3,r2,8020a24 <alt_onchip_flash_write+0x270>
+        {
+            current_offset = flash->dev.region_info[i].offset;
+ 8020878:	e0fff917 	ldw	r3,-28(fp)
+ 802087c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020880:	1004913a 	slli	r2,r2,4
+ 8020884:	1885883a 	add	r2,r3,r2
+ 8020888:	10800d17 	ldw	r2,52(r2)
+ 802088c:	e0bffc15 	stw	r2,-16(fp)
+
+            for(j=0;j<flash->dev.region_info[i].number_of_blocks;j++)
+ 8020890:	e03ffd15 	stw	zero,-12(fp)
+ 8020894:	00005c06 	br	8020a08 <alt_onchip_flash_write+0x254>
+            {
+                if ((offset >= current_offset ) &&
+ 8020898:	e0fff617 	ldw	r3,-40(fp)
+ 802089c:	e0bffc17 	ldw	r2,-16(fp)
+ 80208a0:	18804d16 	blt	r3,r2,80209d8 <alt_onchip_flash_write+0x224>
+                    (offset < (current_offset +
+                    flash->dev.region_info[i].block_size)))
+ 80208a4:	e0fff917 	ldw	r3,-28(fp)
+ 80208a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80208ac:	10800104 	addi	r2,r2,4
+ 80208b0:	1004913a 	slli	r2,r2,4
+ 80208b4:	1885883a 	add	r2,r3,r2
+ 80208b8:	10c00017 	ldw	r3,0(r2)
+                    (offset < (current_offset +
+ 80208bc:	e0bffc17 	ldw	r2,-16(fp)
+ 80208c0:	1885883a 	add	r2,r3,r2
+                if ((offset >= current_offset ) &&
+ 80208c4:	e0fff617 	ldw	r3,-40(fp)
+ 80208c8:	1880430e 	bge	r3,r2,80209d8 <alt_onchip_flash_write+0x224>
+                {
+                    /*
+                    * Check if the contents of the block are different
+                    * from the data we wish to put there
+                    */
+                    data_to_write = (current_offset + flash->dev.region_info[i].block_size - offset);
+ 80208cc:	e0fff917 	ldw	r3,-28(fp)
+ 80208d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80208d4:	10800104 	addi	r2,r2,4
+ 80208d8:	1004913a 	slli	r2,r2,4
+ 80208dc:	1885883a 	add	r2,r3,r2
+ 80208e0:	10c00017 	ldw	r3,0(r2)
+ 80208e4:	e0bffc17 	ldw	r2,-16(fp)
+ 80208e8:	1887883a 	add	r3,r3,r2
+ 80208ec:	e0bff617 	ldw	r2,-40(fp)
+ 80208f0:	1885c83a 	sub	r2,r3,r2
+ 80208f4:	e0bff815 	stw	r2,-32(fp)
+                    data_to_write = MIN(data_to_write, length);
+ 80208f8:	e0fff817 	ldw	r3,-32(fp)
+ 80208fc:	e0bff417 	ldw	r2,-48(fp)
+ 8020900:	1880010e 	bge	r3,r2,8020908 <alt_onchip_flash_write+0x154>
+ 8020904:	1805883a 	mov	r2,r3
+ 8020908:	e0bff815 	stw	r2,-32(fp)
+                    if(memcmp(src_addr, (alt_u8*)flash->dev.base_addr+offset, data_to_write))
+ 802090c:	e0bff917 	ldw	r2,-28(fp)
+ 8020910:	10c00a17 	ldw	r3,40(r2)
+ 8020914:	e0bff617 	ldw	r2,-40(fp)
+ 8020918:	1885883a 	add	r2,r3,r2
+ 802091c:	e0fff817 	ldw	r3,-32(fp)
+ 8020920:	180d883a 	mov	r6,r3
+ 8020924:	100b883a 	mov	r5,r2
+ 8020928:	e13ff517 	ldw	r4,-44(fp)
+ 802092c:	8042cb80 	call	8042cb8 <memcmp>
+ 8020930:	10001326 	beq	r2,zero,8020980 <alt_onchip_flash_write+0x1cc>
+                    {
+                        ret_code = (*flash->dev.erase_block)(&flash->dev, current_offset);
+ 8020934:	e0bff917 	ldw	r2,-28(fp)
+ 8020938:	10800817 	ldw	r2,32(r2)
+ 802093c:	e0fff917 	ldw	r3,-28(fp)
+ 8020940:	e17ffc17 	ldw	r5,-16(fp)
+ 8020944:	1809883a 	mov	r4,r3
+ 8020948:	103ee83a 	callr	r2
+ 802094c:	e0bfff15 	stw	r2,-4(fp)
+
+                        if (!ret_code)
+ 8020950:	e0bfff17 	ldw	r2,-4(fp)
+ 8020954:	10000a1e 	bne	r2,zero,8020980 <alt_onchip_flash_write+0x1cc>
+                        {
+                            ret_code = (*flash->dev.write_block)(
+ 8020958:	e0bff917 	ldw	r2,-28(fp)
+ 802095c:	10800917 	ldw	r2,36(r2)
+ 8020960:	e13ff917 	ldw	r4,-28(fp)
+ 8020964:	e0fff817 	ldw	r3,-32(fp)
+ 8020968:	d8c00015 	stw	r3,0(sp)
+ 802096c:	e1fff517 	ldw	r7,-44(fp)
+ 8020970:	e1bff617 	ldw	r6,-40(fp)
+ 8020974:	e17ffc17 	ldw	r5,-16(fp)
+ 8020978:	103ee83a 	callr	r2
+ 802097c:	e0bfff15 	stw	r2,-4(fp)
+                                                                data_to_write);
+                        }
+                    }
+
+                    /* Was this the last block? */
+                    if ((length == data_to_write) || ret_code)
+ 8020980:	e0fff417 	ldw	r3,-48(fp)
+ 8020984:	e0bff817 	ldw	r2,-32(fp)
+ 8020988:	18802e26 	beq	r3,r2,8020a44 <alt_onchip_flash_write+0x290>
+ 802098c:	e0bfff17 	ldw	r2,-4(fp)
+ 8020990:	10002c1e 	bne	r2,zero,8020a44 <alt_onchip_flash_write+0x290>
+                    {
+                        goto finished;
+                    }
+
+                    length -= data_to_write;
+ 8020994:	e0fff417 	ldw	r3,-48(fp)
+ 8020998:	e0bff817 	ldw	r2,-32(fp)
+ 802099c:	1885c83a 	sub	r2,r3,r2
+ 80209a0:	e0bff415 	stw	r2,-48(fp)
+                    offset = current_offset + flash->dev.region_info[i].block_size;
+ 80209a4:	e0fff917 	ldw	r3,-28(fp)
+ 80209a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80209ac:	10800104 	addi	r2,r2,4
+ 80209b0:	1004913a 	slli	r2,r2,4
+ 80209b4:	1885883a 	add	r2,r3,r2
+ 80209b8:	10800017 	ldw	r2,0(r2)
+ 80209bc:	e0fffc17 	ldw	r3,-16(fp)
+ 80209c0:	1885883a 	add	r2,r3,r2
+ 80209c4:	e0bff615 	stw	r2,-40(fp)
+                    src_addr = (alt_u8*)src_addr + data_to_write;
+ 80209c8:	e0bff817 	ldw	r2,-32(fp)
+ 80209cc:	e0fff517 	ldw	r3,-44(fp)
+ 80209d0:	1885883a 	add	r2,r3,r2
+ 80209d4:	e0bff515 	stw	r2,-44(fp)
+                }
+                current_offset += flash->dev.region_info[i].block_size;
+ 80209d8:	e0fff917 	ldw	r3,-28(fp)
+ 80209dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80209e0:	10800104 	addi	r2,r2,4
+ 80209e4:	1004913a 	slli	r2,r2,4
+ 80209e8:	1885883a 	add	r2,r3,r2
+ 80209ec:	10800017 	ldw	r2,0(r2)
+ 80209f0:	e0fffc17 	ldw	r3,-16(fp)
+ 80209f4:	1885883a 	add	r2,r3,r2
+ 80209f8:	e0bffc15 	stw	r2,-16(fp)
+            for(j=0;j<flash->dev.region_info[i].number_of_blocks;j++)
+ 80209fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8020a00:	10800044 	addi	r2,r2,1
+ 8020a04:	e0bffd15 	stw	r2,-12(fp)
+ 8020a08:	e0fff917 	ldw	r3,-28(fp)
+ 8020a0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020a10:	1004913a 	slli	r2,r2,4
+ 8020a14:	1885883a 	add	r2,r3,r2
+ 8020a18:	10800f17 	ldw	r2,60(r2)
+ 8020a1c:	e0fffd17 	ldw	r3,-12(fp)
+ 8020a20:	18bf9d16 	blt	r3,r2,8020898 <alt_onchip_flash_write+0xe4>
+    for(i=0;i<flash->dev.number_of_regions;i++)
+ 8020a24:	e0bffe17 	ldw	r2,-8(fp)
+ 8020a28:	10800044 	addi	r2,r2,1
+ 8020a2c:	e0bffe15 	stw	r2,-8(fp)
+ 8020a30:	e0bff917 	ldw	r2,-28(fp)
+ 8020a34:	10800c17 	ldw	r2,48(r2)
+ 8020a38:	e0fffe17 	ldw	r3,-8(fp)
+ 8020a3c:	18bf7a16 	blt	r3,r2,8020828 <alt_onchip_flash_write+0x74>
+            }
+        }
+    }
+
+finished:
+ 8020a40:	00000106 	br	8020a48 <alt_onchip_flash_write+0x294>
+                        goto finished;
+ 8020a44:	0001883a 	nop
+    alt_dcache_flush((alt_u8*)flash->dev.base_addr+start_offset, full_length);
+ 8020a48:	e0bff917 	ldw	r2,-28(fp)
+ 8020a4c:	10c00a17 	ldw	r3,40(r2)
+ 8020a50:	e0bffa17 	ldw	r2,-24(fp)
+ 8020a54:	1885883a 	add	r2,r3,r2
+ 8020a58:	e0fffb17 	ldw	r3,-20(fp)
+ 8020a5c:	180b883a 	mov	r5,r3
+ 8020a60:	1009883a 	mov	r4,r2
+ 8020a64:	80371c00 	call	80371c0 <alt_dcache_flush>
+    return ret_code;
+ 8020a68:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8020a6c:	e037883a 	mov	sp,fp
+ 8020a70:	dfc00117 	ldw	ra,4(sp)
+ 8020a74:	df000017 	ldw	fp,0(sp)
+ 8020a78:	dec00204 	addi	sp,sp,8
+ 8020a7c:	f800283a 	ret
+
+08020a80 <altera_onchip_flash_init>:
+**/
+void altera_onchip_flash_init
+(
+    alt_onchip_flash_dev *flash
+)
+{
+ 8020a80:	defff504 	addi	sp,sp,-44
+ 8020a84:	dfc00a15 	stw	ra,40(sp)
+ 8020a88:	df000915 	stw	fp,36(sp)
+ 8020a8c:	dc000815 	stw	r16,32(sp)
+ 8020a90:	df000904 	addi	fp,sp,36
+ 8020a94:	e13ff715 	stw	r4,-36(fp)
+    /* A region is a sector of the onchip flash */
+    int number_of_regions;
+    flash_region* region_info;
+    int sector1_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE;
+ 8020a98:	e03ffd15 	stw	zero,-12(fp)
+    int sector2_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE;
+ 8020a9c:	e03ffc15 	stw	zero,-16(fp)
+    int sector3_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE;
+ 8020aa0:	e03ffb15 	stw	zero,-20(fp)
+    int sector4_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE;
+ 8020aa4:	e03ffa15 	stw	zero,-24(fp)
+    int sector5_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE;
+ 8020aa8:	e03ff915 	stw	zero,-28(fp)
+
+    /* Set up flash_region data structures. */
+    number_of_regions = 0;
+ 8020aac:	e03ffe15 	stw	zero,-8(fp)
+    region_info = &flash->dev.region_info[0];
+ 8020ab0:	e0bff717 	ldw	r2,-36(fp)
+ 8020ab4:	10800d04 	addi	r2,r2,52
+ 8020ab8:	e0bff815 	stw	r2,-32(fp)
+
+    if (flash->csr_base != NULL) {
+ 8020abc:	e0bff717 	ldw	r2,-36(fp)
+ 8020ac0:	10802f17 	ldw	r2,188(r2)
+ 8020ac4:	10001926 	beq	r2,zero,8020b2c <altera_onchip_flash_init+0xac>
+        sector1_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK;
+ 8020ac8:	e0bff717 	ldw	r2,-36(fp)
+ 8020acc:	10802f17 	ldw	r2,188(r2)
+ 8020ad0:	10800037 	ldwio	r2,0(r2)
+ 8020ad4:	1080080c 	andi	r2,r2,32
+ 8020ad8:	e0bffd15 	stw	r2,-12(fp)
+        sector2_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK;
+ 8020adc:	e0bff717 	ldw	r2,-36(fp)
+ 8020ae0:	10802f17 	ldw	r2,188(r2)
+ 8020ae4:	10800037 	ldwio	r2,0(r2)
+ 8020ae8:	1080100c 	andi	r2,r2,64
+ 8020aec:	e0bffc15 	stw	r2,-16(fp)
+        sector3_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK;
+ 8020af0:	e0bff717 	ldw	r2,-36(fp)
+ 8020af4:	10802f17 	ldw	r2,188(r2)
+ 8020af8:	10800037 	ldwio	r2,0(r2)
+ 8020afc:	1080200c 	andi	r2,r2,128
+ 8020b00:	e0bffb15 	stw	r2,-20(fp)
+        sector4_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK;
+ 8020b04:	e0bff717 	ldw	r2,-36(fp)
+ 8020b08:	10802f17 	ldw	r2,188(r2)
+ 8020b0c:	10800037 	ldwio	r2,0(r2)
+ 8020b10:	1080400c 	andi	r2,r2,256
+ 8020b14:	e0bffa15 	stw	r2,-24(fp)
+        sector5_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK;
+ 8020b18:	e0bff717 	ldw	r2,-36(fp)
+ 8020b1c:	10802f17 	ldw	r2,188(r2)
+ 8020b20:	10800037 	ldwio	r2,0(r2)
+ 8020b24:	1080800c 	andi	r2,r2,512
+ 8020b28:	e0bff915 	stw	r2,-28(fp)
+    }
+
+    if ((flash->sector1_enabled == 1) && (sector1_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE)) {
+ 8020b2c:	e0bff717 	ldw	r2,-36(fp)
+ 8020b30:	10803017 	ldw	r2,192(r2)
+ 8020b34:	10800058 	cmpnei	r2,r2,1
+ 8020b38:	10002c1e 	bne	r2,zero,8020bec <altera_onchip_flash_init+0x16c>
+ 8020b3c:	e0bffd17 	ldw	r2,-12(fp)
+ 8020b40:	10800820 	cmpeqi	r2,r2,32
+ 8020b44:	1000291e 	bne	r2,zero,8020bec <altera_onchip_flash_init+0x16c>
+
+        region_info[number_of_regions].offset = flash->sector1_start_addr;
+ 8020b48:	e0bffe17 	ldw	r2,-8(fp)
+ 8020b4c:	1004913a 	slli	r2,r2,4
+ 8020b50:	e0fff817 	ldw	r3,-32(fp)
+ 8020b54:	1885883a 	add	r2,r3,r2
+ 8020b58:	e0fff717 	ldw	r3,-36(fp)
+ 8020b5c:	18c03117 	ldw	r3,196(r3)
+ 8020b60:	10c00015 	stw	r3,0(r2)
+        region_info[number_of_regions].region_size = flash->sector1_end_addr - flash->sector1_start_addr + 1;
+ 8020b64:	e0bff717 	ldw	r2,-36(fp)
+ 8020b68:	10c03217 	ldw	r3,200(r2)
+ 8020b6c:	e0bff717 	ldw	r2,-36(fp)
+ 8020b70:	10803117 	ldw	r2,196(r2)
+ 8020b74:	1887c83a 	sub	r3,r3,r2
+ 8020b78:	e0bffe17 	ldw	r2,-8(fp)
+ 8020b7c:	1004913a 	slli	r2,r2,4
+ 8020b80:	e13ff817 	ldw	r4,-32(fp)
+ 8020b84:	2085883a 	add	r2,r4,r2
+ 8020b88:	18c00044 	addi	r3,r3,1
+ 8020b8c:	10c00115 	stw	r3,4(r2)
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+ 8020b90:	e0fff717 	ldw	r3,-36(fp)
+ 8020b94:	e0bffe17 	ldw	r2,-8(fp)
+ 8020b98:	1004913a 	slli	r2,r2,4
+ 8020b9c:	1885883a 	add	r2,r3,r2
+ 8020ba0:	11000e17 	ldw	r4,56(r2)
+ 8020ba4:	e0bff717 	ldw	r2,-36(fp)
+ 8020ba8:	11403f17 	ldw	r5,252(r2)
+ 8020bac:	e0bffe17 	ldw	r2,-8(fp)
+ 8020bb0:	1004913a 	slli	r2,r2,4
+ 8020bb4:	e0fff817 	ldw	r3,-32(fp)
+ 8020bb8:	18a1883a 	add	r16,r3,r2
+ 8020bbc:	800cf000 	call	800cf00 <__divsi3>
+ 8020bc0:	80800215 	stw	r2,8(r16)
+        region_info[number_of_regions].block_size = flash->page_size;
+ 8020bc4:	e0bffe17 	ldw	r2,-8(fp)
+ 8020bc8:	1004913a 	slli	r2,r2,4
+ 8020bcc:	e0fff817 	ldw	r3,-32(fp)
+ 8020bd0:	1885883a 	add	r2,r3,r2
+ 8020bd4:	e0fff717 	ldw	r3,-36(fp)
+ 8020bd8:	18c03f17 	ldw	r3,252(r3)
+ 8020bdc:	10c00315 	stw	r3,12(r2)
+
+        number_of_regions++;
+ 8020be0:	e0bffe17 	ldw	r2,-8(fp)
+ 8020be4:	10800044 	addi	r2,r2,1
+ 8020be8:	e0bffe15 	stw	r2,-8(fp)
+    }
+
+    if ((flash->sector2_enabled == 1) && (sector2_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE)) {
+ 8020bec:	e0bff717 	ldw	r2,-36(fp)
+ 8020bf0:	10803317 	ldw	r2,204(r2)
+ 8020bf4:	10800058 	cmpnei	r2,r2,1
+ 8020bf8:	10002c1e 	bne	r2,zero,8020cac <altera_onchip_flash_init+0x22c>
+ 8020bfc:	e0bffc17 	ldw	r2,-16(fp)
+ 8020c00:	10801020 	cmpeqi	r2,r2,64
+ 8020c04:	1000291e 	bne	r2,zero,8020cac <altera_onchip_flash_init+0x22c>
+
+        region_info[number_of_regions].offset = flash->sector2_start_addr;
+ 8020c08:	e0bffe17 	ldw	r2,-8(fp)
+ 8020c0c:	1004913a 	slli	r2,r2,4
+ 8020c10:	e0fff817 	ldw	r3,-32(fp)
+ 8020c14:	1885883a 	add	r2,r3,r2
+ 8020c18:	e0fff717 	ldw	r3,-36(fp)
+ 8020c1c:	18c03417 	ldw	r3,208(r3)
+ 8020c20:	10c00015 	stw	r3,0(r2)
+        region_info[number_of_regions].region_size = flash->sector2_end_addr - flash->sector2_start_addr + 1;
+ 8020c24:	e0bff717 	ldw	r2,-36(fp)
+ 8020c28:	10c03517 	ldw	r3,212(r2)
+ 8020c2c:	e0bff717 	ldw	r2,-36(fp)
+ 8020c30:	10803417 	ldw	r2,208(r2)
+ 8020c34:	1887c83a 	sub	r3,r3,r2
+ 8020c38:	e0bffe17 	ldw	r2,-8(fp)
+ 8020c3c:	1004913a 	slli	r2,r2,4
+ 8020c40:	e13ff817 	ldw	r4,-32(fp)
+ 8020c44:	2085883a 	add	r2,r4,r2
+ 8020c48:	18c00044 	addi	r3,r3,1
+ 8020c4c:	10c00115 	stw	r3,4(r2)
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+ 8020c50:	e0fff717 	ldw	r3,-36(fp)
+ 8020c54:	e0bffe17 	ldw	r2,-8(fp)
+ 8020c58:	1004913a 	slli	r2,r2,4
+ 8020c5c:	1885883a 	add	r2,r3,r2
+ 8020c60:	11000e17 	ldw	r4,56(r2)
+ 8020c64:	e0bff717 	ldw	r2,-36(fp)
+ 8020c68:	11403f17 	ldw	r5,252(r2)
+ 8020c6c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020c70:	1004913a 	slli	r2,r2,4
+ 8020c74:	e0fff817 	ldw	r3,-32(fp)
+ 8020c78:	18a1883a 	add	r16,r3,r2
+ 8020c7c:	800cf000 	call	800cf00 <__divsi3>
+ 8020c80:	80800215 	stw	r2,8(r16)
+        region_info[number_of_regions].block_size = flash->page_size;
+ 8020c84:	e0bffe17 	ldw	r2,-8(fp)
+ 8020c88:	1004913a 	slli	r2,r2,4
+ 8020c8c:	e0fff817 	ldw	r3,-32(fp)
+ 8020c90:	1885883a 	add	r2,r3,r2
+ 8020c94:	e0fff717 	ldw	r3,-36(fp)
+ 8020c98:	18c03f17 	ldw	r3,252(r3)
+ 8020c9c:	10c00315 	stw	r3,12(r2)
+
+        number_of_regions++;
+ 8020ca0:	e0bffe17 	ldw	r2,-8(fp)
+ 8020ca4:	10800044 	addi	r2,r2,1
+ 8020ca8:	e0bffe15 	stw	r2,-8(fp)
+	}
+
+    if ((flash->sector3_enabled == 1) && (sector3_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE)) {
+ 8020cac:	e0bff717 	ldw	r2,-36(fp)
+ 8020cb0:	10803617 	ldw	r2,216(r2)
+ 8020cb4:	10800058 	cmpnei	r2,r2,1
+ 8020cb8:	10002c1e 	bne	r2,zero,8020d6c <altera_onchip_flash_init+0x2ec>
+ 8020cbc:	e0bffb17 	ldw	r2,-20(fp)
+ 8020cc0:	10802020 	cmpeqi	r2,r2,128
+ 8020cc4:	1000291e 	bne	r2,zero,8020d6c <altera_onchip_flash_init+0x2ec>
+
+        region_info[number_of_regions].offset = flash->sector3_start_addr;
+ 8020cc8:	e0bffe17 	ldw	r2,-8(fp)
+ 8020ccc:	1004913a 	slli	r2,r2,4
+ 8020cd0:	e0fff817 	ldw	r3,-32(fp)
+ 8020cd4:	1885883a 	add	r2,r3,r2
+ 8020cd8:	e0fff717 	ldw	r3,-36(fp)
+ 8020cdc:	18c03717 	ldw	r3,220(r3)
+ 8020ce0:	10c00015 	stw	r3,0(r2)
+        region_info[number_of_regions].region_size = flash->sector3_end_addr - flash->sector3_start_addr + 1;
+ 8020ce4:	e0bff717 	ldw	r2,-36(fp)
+ 8020ce8:	10c03817 	ldw	r3,224(r2)
+ 8020cec:	e0bff717 	ldw	r2,-36(fp)
+ 8020cf0:	10803717 	ldw	r2,220(r2)
+ 8020cf4:	1887c83a 	sub	r3,r3,r2
+ 8020cf8:	e0bffe17 	ldw	r2,-8(fp)
+ 8020cfc:	1004913a 	slli	r2,r2,4
+ 8020d00:	e13ff817 	ldw	r4,-32(fp)
+ 8020d04:	2085883a 	add	r2,r4,r2
+ 8020d08:	18c00044 	addi	r3,r3,1
+ 8020d0c:	10c00115 	stw	r3,4(r2)
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+ 8020d10:	e0fff717 	ldw	r3,-36(fp)
+ 8020d14:	e0bffe17 	ldw	r2,-8(fp)
+ 8020d18:	1004913a 	slli	r2,r2,4
+ 8020d1c:	1885883a 	add	r2,r3,r2
+ 8020d20:	11000e17 	ldw	r4,56(r2)
+ 8020d24:	e0bff717 	ldw	r2,-36(fp)
+ 8020d28:	11403f17 	ldw	r5,252(r2)
+ 8020d2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8020d30:	1004913a 	slli	r2,r2,4
+ 8020d34:	e0fff817 	ldw	r3,-32(fp)
+ 8020d38:	18a1883a 	add	r16,r3,r2
+ 8020d3c:	800cf000 	call	800cf00 <__divsi3>
+ 8020d40:	80800215 	stw	r2,8(r16)
+        region_info[number_of_regions].block_size = flash->page_size;
+ 8020d44:	e0bffe17 	ldw	r2,-8(fp)
+ 8020d48:	1004913a 	slli	r2,r2,4
+ 8020d4c:	e0fff817 	ldw	r3,-32(fp)
+ 8020d50:	1885883a 	add	r2,r3,r2
+ 8020d54:	e0fff717 	ldw	r3,-36(fp)
+ 8020d58:	18c03f17 	ldw	r3,252(r3)
+ 8020d5c:	10c00315 	stw	r3,12(r2)
+
+        number_of_regions++;
+ 8020d60:	e0bffe17 	ldw	r2,-8(fp)
+ 8020d64:	10800044 	addi	r2,r2,1
+ 8020d68:	e0bffe15 	stw	r2,-8(fp)
+	}
+
+	if ((flash->sector4_enabled == 1) && (sector4_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE)) {
+ 8020d6c:	e0bff717 	ldw	r2,-36(fp)
+ 8020d70:	10803917 	ldw	r2,228(r2)
+ 8020d74:	10800058 	cmpnei	r2,r2,1
+ 8020d78:	10002c1e 	bne	r2,zero,8020e2c <altera_onchip_flash_init+0x3ac>
+ 8020d7c:	e0bffa17 	ldw	r2,-24(fp)
+ 8020d80:	10804020 	cmpeqi	r2,r2,256
+ 8020d84:	1000291e 	bne	r2,zero,8020e2c <altera_onchip_flash_init+0x3ac>
+
+        region_info[number_of_regions].offset = flash->sector4_start_addr;
+ 8020d88:	e0bffe17 	ldw	r2,-8(fp)
+ 8020d8c:	1004913a 	slli	r2,r2,4
+ 8020d90:	e0fff817 	ldw	r3,-32(fp)
+ 8020d94:	1885883a 	add	r2,r3,r2
+ 8020d98:	e0fff717 	ldw	r3,-36(fp)
+ 8020d9c:	18c03a17 	ldw	r3,232(r3)
+ 8020da0:	10c00015 	stw	r3,0(r2)
+        region_info[number_of_regions].region_size = flash->sector4_end_addr - flash->sector4_start_addr + 1;
+ 8020da4:	e0bff717 	ldw	r2,-36(fp)
+ 8020da8:	10c03b17 	ldw	r3,236(r2)
+ 8020dac:	e0bff717 	ldw	r2,-36(fp)
+ 8020db0:	10803a17 	ldw	r2,232(r2)
+ 8020db4:	1887c83a 	sub	r3,r3,r2
+ 8020db8:	e0bffe17 	ldw	r2,-8(fp)
+ 8020dbc:	1004913a 	slli	r2,r2,4
+ 8020dc0:	e13ff817 	ldw	r4,-32(fp)
+ 8020dc4:	2085883a 	add	r2,r4,r2
+ 8020dc8:	18c00044 	addi	r3,r3,1
+ 8020dcc:	10c00115 	stw	r3,4(r2)
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+ 8020dd0:	e0fff717 	ldw	r3,-36(fp)
+ 8020dd4:	e0bffe17 	ldw	r2,-8(fp)
+ 8020dd8:	1004913a 	slli	r2,r2,4
+ 8020ddc:	1885883a 	add	r2,r3,r2
+ 8020de0:	11000e17 	ldw	r4,56(r2)
+ 8020de4:	e0bff717 	ldw	r2,-36(fp)
+ 8020de8:	11403f17 	ldw	r5,252(r2)
+ 8020dec:	e0bffe17 	ldw	r2,-8(fp)
+ 8020df0:	1004913a 	slli	r2,r2,4
+ 8020df4:	e0fff817 	ldw	r3,-32(fp)
+ 8020df8:	18a1883a 	add	r16,r3,r2
+ 8020dfc:	800cf000 	call	800cf00 <__divsi3>
+ 8020e00:	80800215 	stw	r2,8(r16)
+        region_info[number_of_regions].block_size = flash->page_size;
+ 8020e04:	e0bffe17 	ldw	r2,-8(fp)
+ 8020e08:	1004913a 	slli	r2,r2,4
+ 8020e0c:	e0fff817 	ldw	r3,-32(fp)
+ 8020e10:	1885883a 	add	r2,r3,r2
+ 8020e14:	e0fff717 	ldw	r3,-36(fp)
+ 8020e18:	18c03f17 	ldw	r3,252(r3)
+ 8020e1c:	10c00315 	stw	r3,12(r2)
+
+        number_of_regions++;
+ 8020e20:	e0bffe17 	ldw	r2,-8(fp)
+ 8020e24:	10800044 	addi	r2,r2,1
+ 8020e28:	e0bffe15 	stw	r2,-8(fp)
+	}
+
+    if ((flash->sector5_enabled == 1) && (sector5_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE)) {
+ 8020e2c:	e0bff717 	ldw	r2,-36(fp)
+ 8020e30:	10803c17 	ldw	r2,240(r2)
+ 8020e34:	10800058 	cmpnei	r2,r2,1
+ 8020e38:	10002c1e 	bne	r2,zero,8020eec <altera_onchip_flash_init+0x46c>
+ 8020e3c:	e0bff917 	ldw	r2,-28(fp)
+ 8020e40:	10808020 	cmpeqi	r2,r2,512
+ 8020e44:	1000291e 	bne	r2,zero,8020eec <altera_onchip_flash_init+0x46c>
+
+        region_info[number_of_regions].offset = flash->sector5_start_addr;
+ 8020e48:	e0bffe17 	ldw	r2,-8(fp)
+ 8020e4c:	1004913a 	slli	r2,r2,4
+ 8020e50:	e0fff817 	ldw	r3,-32(fp)
+ 8020e54:	1885883a 	add	r2,r3,r2
+ 8020e58:	e0fff717 	ldw	r3,-36(fp)
+ 8020e5c:	18c03d17 	ldw	r3,244(r3)
+ 8020e60:	10c00015 	stw	r3,0(r2)
+        region_info[number_of_regions].region_size = flash->sector5_end_addr - flash->sector5_start_addr + 1;
+ 8020e64:	e0bff717 	ldw	r2,-36(fp)
+ 8020e68:	10c03e17 	ldw	r3,248(r2)
+ 8020e6c:	e0bff717 	ldw	r2,-36(fp)
+ 8020e70:	10803d17 	ldw	r2,244(r2)
+ 8020e74:	1887c83a 	sub	r3,r3,r2
+ 8020e78:	e0bffe17 	ldw	r2,-8(fp)
+ 8020e7c:	1004913a 	slli	r2,r2,4
+ 8020e80:	e13ff817 	ldw	r4,-32(fp)
+ 8020e84:	2085883a 	add	r2,r4,r2
+ 8020e88:	18c00044 	addi	r3,r3,1
+ 8020e8c:	10c00115 	stw	r3,4(r2)
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+ 8020e90:	e0fff717 	ldw	r3,-36(fp)
+ 8020e94:	e0bffe17 	ldw	r2,-8(fp)
+ 8020e98:	1004913a 	slli	r2,r2,4
+ 8020e9c:	1885883a 	add	r2,r3,r2
+ 8020ea0:	11000e17 	ldw	r4,56(r2)
+ 8020ea4:	e0bff717 	ldw	r2,-36(fp)
+ 8020ea8:	11403f17 	ldw	r5,252(r2)
+ 8020eac:	e0bffe17 	ldw	r2,-8(fp)
+ 8020eb0:	1004913a 	slli	r2,r2,4
+ 8020eb4:	e0fff817 	ldw	r3,-32(fp)
+ 8020eb8:	18a1883a 	add	r16,r3,r2
+ 8020ebc:	800cf000 	call	800cf00 <__divsi3>
+ 8020ec0:	80800215 	stw	r2,8(r16)
+        region_info[number_of_regions].block_size = flash->page_size;
+ 8020ec4:	e0bffe17 	ldw	r2,-8(fp)
+ 8020ec8:	1004913a 	slli	r2,r2,4
+ 8020ecc:	e0fff817 	ldw	r3,-32(fp)
+ 8020ed0:	1885883a 	add	r2,r3,r2
+ 8020ed4:	e0fff717 	ldw	r3,-36(fp)
+ 8020ed8:	18c03f17 	ldw	r3,252(r3)
+ 8020edc:	10c00315 	stw	r3,12(r2)
+
+        number_of_regions++;
+ 8020ee0:	e0bffe17 	ldw	r2,-8(fp)
+ 8020ee4:	10800044 	addi	r2,r2,1
+ 8020ee8:	e0bffe15 	stw	r2,-8(fp)
+    }
+
+    /* Update number of regions. */
+    flash->dev.number_of_regions = number_of_regions;
+ 8020eec:	e0bff717 	ldw	r2,-36(fp)
+ 8020ef0:	e0fffe17 	ldw	r3,-8(fp)
+ 8020ef4:	10c00c15 	stw	r3,48(r2)
+
+    /*
+    *  Register this device as a valid flash device type
+    */
+    alt_flash_device_register(&(flash->dev));
+ 8020ef8:	e0bff717 	ldw	r2,-36(fp)
+ 8020efc:	1009883a 	mov	r4,r2
+ 8020f00:	80201d80 	call	80201d8 <alt_flash_device_register>
+}
+ 8020f04:	0001883a 	nop
+ 8020f08:	e6ffff04 	addi	sp,fp,-4
+ 8020f0c:	dfc00217 	ldw	ra,8(sp)
+ 8020f10:	df000117 	ldw	fp,4(sp)
+ 8020f14:	dc000017 	ldw	r16,0(sp)
+ 8020f18:	dec00304 	addi	sp,sp,12
+ 8020f1c:	f800283a 	ret
+
+08020f20 <alt_onchip_flash_poll_for_status_to_go_idle>:
+**/
+int alt_onchip_flash_poll_for_status_to_go_idle
+(
+    alt_onchip_flash_dev *flash
+)
+{
+ 8020f20:	defffa04 	addi	sp,sp,-24
+ 8020f24:	dfc00515 	stw	ra,20(sp)
+ 8020f28:	df000415 	stw	fp,16(sp)
+ 8020f2c:	df000404 	addi	fp,sp,16
+ 8020f30:	e13ffc15 	stw	r4,-16(fp)
+    int ret_code = 0;
+ 8020f34:	e03fff15 	stw	zero,-4(fp)
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 8020f38:	008002f4 	movhi	r2,11
+ 8020f3c:	10ab9804 	addi	r2,r2,-20896
+ 8020f40:	e0bffd15 	stw	r2,-12(fp)
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 8020f44:	008002f4 	movhi	r2,11
+ 8020f48:	10ab9804 	addi	r2,r2,-20896
+ 8020f4c:	e0bffe15 	stw	r2,-8(fp)
+
+    while (
+ 8020f50:	00000c06 	br	8020f84 <alt_onchip_flash_poll_for_status_to_go_idle+0x64>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE
+    ) {
+	 
+	alt_busy_sleep(1); /* delay 1us */
+ 8020f54:	01000044 	movi	r4,1
+ 8020f58:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+ 8020f5c:	e0bffd17 	ldw	r2,-12(fp)
+ 8020f60:	10000826 	beq	r2,zero,8020f84 <alt_onchip_flash_poll_for_status_to_go_idle+0x64>
+            count_down--;
+ 8020f64:	e0bffe17 	ldw	r2,-8(fp)
+ 8020f68:	10bfffc4 	addi	r2,r2,-1
+ 8020f6c:	e0bffe15 	stw	r2,-8(fp)
+            if (count_down == 0) {
+ 8020f70:	e0bffe17 	ldw	r2,-8(fp)
+ 8020f74:	1000031e 	bne	r2,zero,8020f84 <alt_onchip_flash_poll_for_status_to_go_idle+0x64>
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+ 8020f78:	00bfe304 	movi	r2,-116
+ 8020f7c:	e0bfff15 	stw	r2,-4(fp)
+                break;
+ 8020f80:	00000506 	br	8020f98 <alt_onchip_flash_poll_for_status_to_go_idle+0x78>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+ 8020f84:	e0bffc17 	ldw	r2,-16(fp)
+ 8020f88:	10802f17 	ldw	r2,188(r2)
+ 8020f8c:	10800037 	ldwio	r2,0(r2)
+ 8020f90:	108000cc 	andi	r2,r2,3
+    while (
+ 8020f94:	103fef1e 	bne	r2,zero,8020f54 <alt_onchip_flash_poll_for_status_to_go_idle+0x34>
+            }
+        }
+    }
+
+    return ret_code;
+ 8020f98:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8020f9c:	e037883a 	mov	sp,fp
+ 8020fa0:	dfc00117 	ldw	ra,4(sp)
+ 8020fa4:	df000017 	ldw	fp,0(sp)
+ 8020fa8:	dec00204 	addi	sp,sp,8
+ 8020fac:	f800283a 	ret
+
+08020fb0 <alt_onchip_flash_poll_for_status_erase_passed>:
+**/
+int alt_onchip_flash_poll_for_status_erase_passed
+(
+    alt_onchip_flash_dev *flash
+)
+{
+ 8020fb0:	defffa04 	addi	sp,sp,-24
+ 8020fb4:	dfc00515 	stw	ra,20(sp)
+ 8020fb8:	df000415 	stw	fp,16(sp)
+ 8020fbc:	df000404 	addi	fp,sp,16
+ 8020fc0:	e13ffc15 	stw	r4,-16(fp)
+    int ret_code = 0;
+ 8020fc4:	e03fff15 	stw	zero,-4(fp)
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 8020fc8:	008002f4 	movhi	r2,11
+ 8020fcc:	10ab9804 	addi	r2,r2,-20896
+ 8020fd0:	e0bffd15 	stw	r2,-12(fp)
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 8020fd4:	008002f4 	movhi	r2,11
+ 8020fd8:	10ab9804 	addi	r2,r2,-20896
+ 8020fdc:	e0bffe15 	stw	r2,-8(fp)
+
+    while (
+ 8020fe0:	00000c06 	br	8021014 <alt_onchip_flash_poll_for_status_erase_passed+0x64>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED
+    ) {
+
+	alt_busy_sleep(1); /* delay 1us */
+ 8020fe4:	01000044 	movi	r4,1
+ 8020fe8:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+ 8020fec:	e0bffd17 	ldw	r2,-12(fp)
+ 8020ff0:	10000826 	beq	r2,zero,8021014 <alt_onchip_flash_poll_for_status_erase_passed+0x64>
+            count_down--;
+ 8020ff4:	e0bffe17 	ldw	r2,-8(fp)
+ 8020ff8:	10bfffc4 	addi	r2,r2,-1
+ 8020ffc:	e0bffe15 	stw	r2,-8(fp)
+            if (count_down == 0) {
+ 8021000:	e0bffe17 	ldw	r2,-8(fp)
+ 8021004:	1000031e 	bne	r2,zero,8021014 <alt_onchip_flash_poll_for_status_erase_passed+0x64>
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+ 8021008:	00bfe304 	movi	r2,-116
+ 802100c:	e0bfff15 	stw	r2,-4(fp)
+                break;
+ 8021010:	00000606 	br	802102c <alt_onchip_flash_poll_for_status_erase_passed+0x7c>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+ 8021014:	e0bffc17 	ldw	r2,-16(fp)
+ 8021018:	10802f17 	ldw	r2,188(r2)
+ 802101c:	10800037 	ldwio	r2,0(r2)
+ 8021020:	1080040c 	andi	r2,r2,16
+    while (
+ 8021024:	10800418 	cmpnei	r2,r2,16
+ 8021028:	103fee1e 	bne	r2,zero,8020fe4 <alt_onchip_flash_poll_for_status_erase_passed+0x34>
+            }
+        }
+    }
+
+    return ret_code;
+ 802102c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8021030:	e037883a 	mov	sp,fp
+ 8021034:	dfc00117 	ldw	ra,4(sp)
+ 8021038:	df000017 	ldw	fp,0(sp)
+ 802103c:	dec00204 	addi	sp,sp,8
+ 8021040:	f800283a 	ret
+
+08021044 <alt_onchip_flash_poll_for_status_write_passed>:
+**/
+int alt_onchip_flash_poll_for_status_write_passed
+(
+    alt_onchip_flash_dev *flash
+)
+{
+ 8021044:	defffa04 	addi	sp,sp,-24
+ 8021048:	dfc00515 	stw	ra,20(sp)
+ 802104c:	df000415 	stw	fp,16(sp)
+ 8021050:	df000404 	addi	fp,sp,16
+ 8021054:	e13ffc15 	stw	r4,-16(fp)
+    int ret_code = 0;
+ 8021058:	e03fff15 	stw	zero,-4(fp)
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 802105c:	008002f4 	movhi	r2,11
+ 8021060:	10ab9804 	addi	r2,r2,-20896
+ 8021064:	e0bffd15 	stw	r2,-12(fp)
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+ 8021068:	008002f4 	movhi	r2,11
+ 802106c:	10ab9804 	addi	r2,r2,-20896
+ 8021070:	e0bffe15 	stw	r2,-8(fp)
+
+    while (
+ 8021074:	00000c06 	br	80210a8 <alt_onchip_flash_poll_for_status_write_passed+0x64>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED
+    ) {
+
+	alt_busy_sleep(1); /* delay 1us */
+ 8021078:	01000044 	movi	r4,1
+ 802107c:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+ 8021080:	e0bffd17 	ldw	r2,-12(fp)
+ 8021084:	10000826 	beq	r2,zero,80210a8 <alt_onchip_flash_poll_for_status_write_passed+0x64>
+            count_down--;
+ 8021088:	e0bffe17 	ldw	r2,-8(fp)
+ 802108c:	10bfffc4 	addi	r2,r2,-1
+ 8021090:	e0bffe15 	stw	r2,-8(fp)
+            if (count_down == 0) {
+ 8021094:	e0bffe17 	ldw	r2,-8(fp)
+ 8021098:	1000031e 	bne	r2,zero,80210a8 <alt_onchip_flash_poll_for_status_write_passed+0x64>
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+ 802109c:	00bfe304 	movi	r2,-116
+ 80210a0:	e0bfff15 	stw	r2,-4(fp)
+                break;
+ 80210a4:	00000606 	br	80210c0 <alt_onchip_flash_poll_for_status_write_passed+0x7c>
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+ 80210a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80210ac:	10802f17 	ldw	r2,188(r2)
+ 80210b0:	10800037 	ldwio	r2,0(r2)
+ 80210b4:	1080020c 	andi	r2,r2,8
+    while (
+ 80210b8:	10800218 	cmpnei	r2,r2,8
+ 80210bc:	103fee1e 	bne	r2,zero,8021078 <alt_onchip_flash_poll_for_status_write_passed+0x34>
+            }
+        }
+    }
+
+    return ret_code;
+ 80210c0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80210c4:	e037883a 	mov	sp,fp
+ 80210c8:	dfc00117 	ldw	ra,4(sp)
+ 80210cc:	df000017 	ldw	fp,0(sp)
+ 80210d0:	dec00204 	addi	sp,sp,8
+ 80210d4:	f800283a 	ret
+
+080210d8 <altera_eth_tse_init>:
+ * @Return ENP_HARDWARE on error, otherwise return SUCCESS
+ */
+
+error_t altera_eth_tse_init(
+    alt_iniche_dev              *p_dev)
+{
+ 80210d8:	defffa04 	addi	sp,sp,-24
+ 80210dc:	dfc00515 	stw	ra,20(sp)
+ 80210e0:	df000415 	stw	fp,16(sp)
+ 80210e4:	df000404 	addi	fp,sp,16
+ 80210e8:	e13ffc15 	stw	r4,-16(fp)
+    int i;
+    
+    alt_tse_iniche_dev_driver_data *p_driver_data = 0;
+ 80210ec:	e03ffe15 	stw	zero,-8(fp)
+    alt_tse_system_info *psys_info = 0;
+ 80210f0:	e03ffd15 	stw	zero,-12(fp)
+
+    dprintf("altera_eth_tse_init %d\n", p_dev->if_num);
+ 80210f4:	e0bffc17 	ldw	r2,-16(fp)
+ 80210f8:	10800517 	ldw	r2,20(r2)
+ 80210fc:	100b883a 	mov	r5,r2
+ 8021100:	01020174 	movhi	r4,2053
+ 8021104:	2125ca04 	addi	r4,r4,-26840
+ 8021108:	8002c780 	call	8002c78 <printf>
+       
+    /* Get the pointer to the alt_tse_iniche_dev_driver_data structure from the global array */
+    for(i = 0; i < number_of_tse_mac; i++) {
+ 802110c:	e03fff15 	stw	zero,-4(fp)
+ 8021110:	00001006 	br	8021154 <altera_eth_tse_init+0x7c>
+        if(tse_iniche_dev_driver_data[i].p_dev == p_dev) {
+ 8021114:	e0bfff17 	ldw	r2,-4(fp)
+ 8021118:	10c00324 	muli	r3,r2,12
+ 802111c:	008201b4 	movhi	r2,2054
+ 8021120:	1885883a 	add	r2,r3,r2
+ 8021124:	10b5b617 	ldw	r2,-10536(r2)
+ 8021128:	e0fffc17 	ldw	r3,-16(fp)
+ 802112c:	1880061e 	bne	r3,r2,8021148 <altera_eth_tse_init+0x70>
+            p_driver_data = &tse_iniche_dev_driver_data[i];
+ 8021130:	e0bfff17 	ldw	r2,-4(fp)
+ 8021134:	10c00324 	muli	r3,r2,12
+ 8021138:	008201b4 	movhi	r2,2054
+ 802113c:	10b5b604 	addi	r2,r2,-10536
+ 8021140:	1885883a 	add	r2,r3,r2
+ 8021144:	e0bffe15 	stw	r2,-8(fp)
+    for(i = 0; i < number_of_tse_mac; i++) {
+ 8021148:	e0bfff17 	ldw	r2,-4(fp)
+ 802114c:	10800044 	addi	r2,r2,1
+ 8021150:	e0bfff15 	stw	r2,-4(fp)
+ 8021154:	d0a05c03 	ldbu	r2,-32400(gp)
+ 8021158:	10803fcc 	andi	r2,r2,255
+ 802115c:	e0ffff17 	ldw	r3,-4(fp)
+ 8021160:	18bfec16 	blt	r3,r2,8021114 <altera_eth_tse_init+0x3c>
+        }
+    }
+    /* If pointer could not found */
+    if(p_driver_data == 0) {
+ 8021164:	e0bffe17 	ldw	r2,-8(fp)
+ 8021168:	1000021e 	bne	r2,zero,8021174 <altera_eth_tse_init+0x9c>
+        return ENP_HARDWARE;
+ 802116c:	00bff744 	movi	r2,-35
+ 8021170:	00002606 	br	802120c <altera_eth_tse_init+0x134>
+    }
+    
+    /* Get the pointer to the alt_tse_system_info structure from the global array */
+    for(i = 0; i < max_mac_system; i++) {
+ 8021174:	e03fff15 	stw	zero,-4(fp)
+ 8021178:	00001106 	br	80211c0 <altera_eth_tse_init+0xe8>
+        if(tse_mac_device[i].tse_mac_base == p_driver_data->hw_mac_base_addr) {
+ 802117c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021180:	10c01324 	muli	r3,r2,76
+ 8021184:	00820174 	movhi	r2,2053
+ 8021188:	1885883a 	add	r2,r3,r2
+ 802118c:	10ee5417 	ldw	r3,-18096(r2)
+ 8021190:	e0bffe17 	ldw	r2,-8(fp)
+ 8021194:	10800117 	ldw	r2,4(r2)
+ 8021198:	1880061e 	bne	r3,r2,80211b4 <altera_eth_tse_init+0xdc>
+            psys_info = &tse_mac_device[i];
+ 802119c:	e0bfff17 	ldw	r2,-4(fp)
+ 80211a0:	10c01324 	muli	r3,r2,76
+ 80211a4:	00820174 	movhi	r2,2053
+ 80211a8:	10ae5404 	addi	r2,r2,-18096
+ 80211ac:	1885883a 	add	r2,r3,r2
+ 80211b0:	e0bffd15 	stw	r2,-12(fp)
+    for(i = 0; i < max_mac_system; i++) {
+ 80211b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80211b8:	10800044 	addi	r2,r2,1
+ 80211bc:	e0bfff15 	stw	r2,-4(fp)
+ 80211c0:	d0a00a03 	ldbu	r2,-32728(gp)
+ 80211c4:	10803fcc 	andi	r2,r2,255
+ 80211c8:	e0ffff17 	ldw	r3,-4(fp)
+ 80211cc:	18bfeb16 	blt	r3,r2,802117c <altera_eth_tse_init+0xa4>
+        }
+    }
+    /* If pointer could not found */
+    if(psys_info == 0) {
+ 80211d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80211d4:	1000021e 	bne	r2,zero,80211e0 <altera_eth_tse_init+0x108>
+        return ENP_HARDWARE;
+ 80211d8:	00bff744 	movi	r2,-35
+ 80211dc:	00000b06 	br	802120c <altera_eth_tse_init+0x134>
+    }
+    
+    prep_tse_mac(p_dev->if_num, psys_info + p_driver_data->hw_channel_number);
+ 80211e0:	e0bffc17 	ldw	r2,-16(fp)
+ 80211e4:	11000517 	ldw	r4,20(r2)
+ 80211e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80211ec:	10800203 	ldbu	r2,8(r2)
+ 80211f0:	10803fcc 	andi	r2,r2,255
+ 80211f4:	10801324 	muli	r2,r2,76
+ 80211f8:	e0fffd17 	ldw	r3,-12(fp)
+ 80211fc:	1885883a 	add	r2,r3,r2
+ 8021200:	100b883a 	mov	r5,r2
+ 8021204:	80212200 	call	8021220 <prep_tse_mac>
+    
+    return SUCCESS;
+ 8021208:	0005883a 	mov	r2,zero
+}
+ 802120c:	e037883a 	mov	sp,fp
+ 8021210:	dfc00117 	ldw	ra,4(sp)
+ 8021214:	df000017 	ldw	fp,0(sp)
+ 8021218:	dec00204 	addi	sp,sp,8
+ 802121c:	f800283a 	ret
+
+08021220 <prep_tse_mac>:
+ * @Param index     index of the NET structure associated with TSE instance
+ * @Param psys_info pointer to the TSE hardware info structure
+ * @Return next index of NET
+ */
+int prep_tse_mac(int index, alt_tse_system_info *psys_info)
+{
+ 8021220:	defffb04 	addi	sp,sp,-20
+ 8021224:	dfc00415 	stw	ra,16(sp)
+ 8021228:	df000315 	stw	fp,12(sp)
+ 802122c:	df000304 	addi	fp,sp,12
+ 8021230:	e13ffe15 	stw	r4,-8(fp)
+ 8021234:	e17ffd15 	stw	r5,-12(fp)
+    NET ifp;
+    dprintf("prep_tse_mac %d\n", index);
+ 8021238:	e17ffe17 	ldw	r5,-8(fp)
+ 802123c:	01020174 	movhi	r4,2053
+ 8021240:	2125d004 	addi	r4,r4,-26816
+ 8021244:	8002c780 	call	8002c78 <printf>
+    {
+        tse[index].sem = 0; /*Tx IDLE*/
+ 8021248:	e0bffe17 	ldw	r2,-8(fp)
+ 802124c:	10c02924 	muli	r3,r2,164
+ 8021250:	008201b4 	movhi	r2,2054
+ 8021254:	1885883a 	add	r2,r3,r2
+ 8021258:	1035cd15 	stw	zero,-10444(r2)
+        tse[index].tse = (void *)psys_info;
+ 802125c:	e0bffe17 	ldw	r2,-8(fp)
+ 8021260:	11002924 	muli	r4,r2,164
+ 8021264:	e0fffd17 	ldw	r3,-12(fp)
+ 8021268:	008201b4 	movhi	r2,2054
+ 802126c:	2085883a 	add	r2,r4,r2
+ 8021270:	10f5ea15 	stw	r3,-10328(r2)
+
+        ifp = nets[index];
+ 8021274:	e0bffe17 	ldw	r2,-8(fp)
+ 8021278:	100690ba 	slli	r3,r2,2
+ 802127c:	008201b4 	movhi	r2,2054
+ 8021280:	1885883a 	add	r2,r3,r2
+ 8021284:	10b77017 	ldw	r2,-8768(r2)
+ 8021288:	e0bfff15 	stw	r2,-4(fp)
+        ifp->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; /* status = down */
+ 802128c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021290:	10802717 	ldw	r2,156(r2)
+ 8021294:	00c00084 	movi	r3,2
+ 8021298:	10c00615 	stw	r3,24(r2)
+        ifp->n_mib->ifOperStatus =  ALTERA_TSE_ADMIN_STATUS_DOWN;   
+ 802129c:	e0bfff17 	ldw	r2,-4(fp)
+ 80212a0:	10802717 	ldw	r2,156(r2)
+ 80212a4:	00c00084 	movi	r3,2
+ 80212a8:	10c00715 	stw	r3,28(r2)
+        ifp->n_mib->ifLastChange =  cticks * (100/TPS);
+ 80212ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80212b0:	10802717 	ldw	r2,156(r2)
+ 80212b4:	d0e07d17 	ldw	r3,-32268(gp)
+ 80212b8:	10c00815 	stw	r3,32(r2)
+        ifp->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr;
+ 80212bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80212c0:	10c02717 	ldw	r3,156(r2)
+ 80212c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80212c8:	10802924 	muli	r2,r2,164
+ 80212cc:	11000604 	addi	r4,r2,24
+ 80212d0:	008201b4 	movhi	r2,2054
+ 80212d4:	10b5c204 	addi	r2,r2,-10488
+ 80212d8:	2085883a 	add	r2,r4,r2
+ 80212dc:	18800515 	stw	r2,20(r3)
+        ifp->n_mib->ifDescr =       "Altera TSE MAC ethernet";
+ 80212e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80212e4:	10c02717 	ldw	r3,156(r2)
+ 80212e8:	00820174 	movhi	r2,2053
+ 80212ec:	10a5d504 	addi	r2,r2,-26796
+ 80212f0:	18800115 	stw	r2,4(r3)
+        ifp->n_lnh =                ETHHDR_SIZE; /* ethernet header size. was:14 */
+ 80212f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80212f8:	00c00404 	movi	r3,16
+ 80212fc:	10c00815 	stw	r3,32(r2)
+        ifp->n_hal =                ALTERA_TSE_HAL_ADDR_LEN;  /* hardware address length */
+ 8021300:	e0bfff17 	ldw	r2,-4(fp)
+ 8021304:	00c00184 	movi	r3,6
+ 8021308:	10c01115 	stw	r3,68(r2)
+        ifp->n_mib->ifType =        ETHERNET;   /* device type */
+ 802130c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021310:	10802717 	ldw	r2,156(r2)
+ 8021314:	00c00184 	movi	r3,6
+ 8021318:	10c00215 	stw	r3,8(r2)
+        ifp->n_mtu =                ALTERA_TSE_MAX_MTU_SIZE;  /* max frame size */
+ 802131c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021320:	00c17a84 	movi	r3,1514
+ 8021324:	10c00915 	stw	r3,36(r2)
+    
+        /* install our hardware driver routines */
+        ifp->n_init =       tse_mac_init;
+ 8021328:	e0ffff17 	ldw	r3,-4(fp)
+ 802132c:	008200b4 	movhi	r2,2050
+ 8021330:	10853104 	addi	r2,r2,5316
+ 8021334:	18800215 	stw	r2,8(r3)
+        ifp->pkt_send =     NULL;
+ 8021338:	e0bfff17 	ldw	r2,-4(fp)
+ 802133c:	10000415 	stw	zero,16(r2)
+        ifp->raw_send =     tse_mac_raw_send;
+ 8021340:	e0ffff17 	ldw	r3,-4(fp)
+ 8021344:	008200b4 	movhi	r2,2050
+ 8021348:	10881204 	addi	r2,r2,8264
+ 802134c:	18800315 	stw	r2,12(r3)
+        ifp->n_close =      tse_mac_close;
+ 8021350:	e0ffff17 	ldw	r3,-4(fp)
+ 8021354:	008200b4 	movhi	r2,2050
+ 8021358:	108a6104 	addi	r2,r2,10628
+ 802135c:	18800515 	stw	r2,20(r3)
+        ifp->n_stats =      (void(*)(void *, int))tse_mac_stats; 
+ 8021360:	e0ffff17 	ldw	r3,-4(fp)
+ 8021364:	008200b4 	movhi	r2,2050
+ 8021368:	108a5104 	addi	r2,r2,10564
+ 802136c:	18800715 	stw	r2,28(r3)
+    
+    #ifdef IP_V6
+        ifp->n_flags |= (NF_NBPROT | NF_IPV6);
+    #else
+        ifp->n_flags |= NF_NBPROT;
+ 8021370:	e0bfff17 	ldw	r2,-4(fp)
+ 8021374:	10802a17 	ldw	r2,168(r2)
+ 8021378:	10c00214 	ori	r3,r2,8
+ 802137c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021380:	10c02a15 	stw	r3,168(r2)
+    #endif
+    
+        nets[index]->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr;   /* ptr to MAC address */
+ 8021384:	e0bffe17 	ldw	r2,-8(fp)
+ 8021388:	100690ba 	slli	r3,r2,2
+ 802138c:	008201b4 	movhi	r2,2054
+ 8021390:	1885883a 	add	r2,r3,r2
+ 8021394:	10b77017 	ldw	r2,-8768(r2)
+ 8021398:	10c02717 	ldw	r3,156(r2)
+ 802139c:	e0bffe17 	ldw	r2,-8(fp)
+ 80213a0:	10802924 	muli	r2,r2,164
+ 80213a4:	11000604 	addi	r4,r2,24
+ 80213a8:	008201b4 	movhi	r2,2054
+ 80213ac:	10b5c204 	addi	r2,r2,-10488
+ 80213b0:	2085883a 	add	r2,r4,r2
+ 80213b4:	18800515 	stw	r2,20(r3)
+    
+    #ifdef ALT_INICHE
+        /* get the MAC address. */
+        get_mac_addr(ifp, (unsigned char *)tse[index].mac_addr);
+ 80213b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80213bc:	10802924 	muli	r2,r2,164
+ 80213c0:	10c00604 	addi	r3,r2,24
+ 80213c4:	008201b4 	movhi	r2,2054
+ 80213c8:	10b5c204 	addi	r2,r2,-10488
+ 80213cc:	1885883a 	add	r2,r3,r2
+ 80213d0:	100b883a 	mov	r5,r2
+ 80213d4:	e13fff17 	ldw	r4,-4(fp)
+ 80213d8:	80011e80 	call	80011e8 <get_mac_addr>
+    #endif /* ALT_INICHE */
+    
+        /* set cross-pointers between iface and tse structs */
+        tse[index].index = index;
+ 80213dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80213e0:	11002924 	muli	r4,r2,164
+ 80213e4:	e0fffe17 	ldw	r3,-8(fp)
+ 80213e8:	008201b4 	movhi	r2,2054
+ 80213ec:	2085883a 	add	r2,r4,r2
+ 80213f0:	10f5c215 	stw	r3,-10488(r2)
+        tse[index].netp = ifp;
+ 80213f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80213f8:	11002924 	muli	r4,r2,164
+ 80213fc:	e0ffff17 	ldw	r3,-4(fp)
+ 8021400:	008201b4 	movhi	r2,2054
+ 8021404:	2085883a 	add	r2,r4,r2
+ 8021408:	10f5ca15 	stw	r3,-10456(r2)
+        ifp->n_local = (void*)(&tse[index]);
+ 802140c:	e0bffe17 	ldw	r2,-8(fp)
+ 8021410:	10c02924 	muli	r3,r2,164
+ 8021414:	008201b4 	movhi	r2,2054
+ 8021418:	10b5c204 	addi	r2,r2,-10488
+ 802141c:	1887883a 	add	r3,r3,r2
+ 8021420:	e0bfff17 	ldw	r2,-4(fp)
+ 8021424:	10c02815 	stw	r3,160(r2)
+    
+        index++;
+ 8021428:	e0bffe17 	ldw	r2,-8(fp)
+ 802142c:	10800044 	addi	r2,r2,1
+ 8021430:	e0bffe15 	stw	r2,-8(fp)
+   }
+ 
+   return index;
+ 8021434:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8021438:	e037883a 	mov	sp,fp
+ 802143c:	dfc00117 	ldw	ra,4(sp)
+ 8021440:	df000017 	ldw	fp,0(sp)
+ 8021444:	dec00204 	addi	sp,sp,8
+ 8021448:	f800283a 	ret
+
+0802144c <msgdma_reset>:
+
+//temporary code for msgdma hw workaround
+void msgdma_reset(alt_msgdma_dev * dev)
+{
+ 802144c:	defffe04 	addi	sp,sp,-8
+ 8021450:	df000115 	stw	fp,4(sp)
+ 8021454:	df000104 	addi	fp,sp,4
+ 8021458:	e13fff15 	stw	r4,-4(fp)
+
+   /* start prefetcher reset sequence */
+   IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, 
+ 802145c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021460:	10800617 	ldw	r2,24(r2)
+ 8021464:	00c00104 	movi	r3,4
+ 8021468:	10c00035 	stwio	r3,0(r2)
+   ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
+   /* wait until hw clears the bit */
+   while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
+ 802146c:	0001883a 	nop
+ 8021470:	e0bfff17 	ldw	r2,-4(fp)
+ 8021474:	10800617 	ldw	r2,24(r2)
+ 8021478:	10800037 	ldwio	r2,0(r2)
+ 802147c:	1080010c 	andi	r2,r2,4
+ 8021480:	103ffb1e 	bne	r2,zero,8021470 <msgdma_reset+0x24>
+    */
+
+    /* Reset the registers and FIFOs of the dispatcher and master modules */
+    /* set the reset bit, no need to read the control register first since 
+    this write is going to clear it out */
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK);
+ 8021484:	e0bfff17 	ldw	r2,-4(fp)
+ 8021488:	10800317 	ldw	r2,12(r2)
+ 802148c:	10800104 	addi	r2,r2,4
+ 8021490:	00c00084 	movi	r3,2
+ 8021494:	10c00035 	stwio	r3,0(r2)
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+ 8021498:	0001883a 	nop
+ 802149c:	e0bfff17 	ldw	r2,-4(fp)
+ 80214a0:	10800317 	ldw	r2,12(r2)
+ 80214a4:	10800037 	ldwio	r2,0(r2)
+                   & ALTERA_MSGDMA_CSR_RESET_STATE_MASK));
+ 80214a8:	1080100c 	andi	r2,r2,64
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+ 80214ac:	103ffb1e 	bne	r2,zero,802149c <msgdma_reset+0x50>
+
+}  
+ 80214b0:	0001883a 	nop
+ 80214b4:	e037883a 	mov	sp,fp
+ 80214b8:	df000017 	ldw	fp,0(sp)
+ 80214bc:	dec00104 	addi	sp,sp,4
+ 80214c0:	f800283a 	ret
+
+080214c4 <tse_mac_init>:
+ * @API TYPE: Internal
+ * @Param iface index of the NET structure associated with TSE instance
+ * @Return 0 if ok, else -1 if error
+ */
+int tse_mac_init(int iface)
+{
+ 80214c4:	defff104 	addi	sp,sp,-60
+ 80214c8:	dfc00e15 	stw	ra,56(sp)
+ 80214cc:	df000d15 	stw	fp,52(sp)
+ 80214d0:	df000d04 	addi	fp,sp,52
+ 80214d4:	e13ff415 	stw	r4,-48(fp)
+   int dat;
+   int speed, duplex, result, x;
+   int status = SUCCESS;
+ 80214d8:	e03ffd15 	stw	zero,-12(fp)
+   
+   alt_msgdma_dev *msgdma_tx_dev;
+   alt_msgdma_dev *msgdma_rx_dev;
+   alt_tse_system_info* tse_hw = (alt_tse_system_info *) tse[iface].tse;
+ 80214dc:	e0bff417 	ldw	r2,-48(fp)
+ 80214e0:	10c02924 	muli	r3,r2,164
+ 80214e4:	008201b4 	movhi	r2,2054
+ 80214e8:	1885883a 	add	r2,r3,r2
+ 80214ec:	10b5ea17 	ldw	r2,-10328(r2)
+ 80214f0:	e0bffa15 	stw	r2,-24(fp)
+   
+   dprintf("tse_mac_init %d\n", iface);
+ 80214f4:	e17ff417 	ldw	r5,-48(fp)
+ 80214f8:	01020174 	movhi	r4,2053
+ 80214fc:	2125db04 	addi	r4,r4,-26772
+ 8021500:	8002c780 	call	8002c78 <printf>
+
+    if (tse_hw->ext_desc_mem == 1) {
+ 8021504:	e0bffa17 	ldw	r2,-24(fp)
+ 8021508:	10800883 	ldbu	r2,34(r2)
+ 802150c:	10803fcc 	andi	r2,r2,255
+ 8021510:	10800058 	cmpnei	r2,r2,1
+ 8021514:	10001b1e 	bne	r2,zero,8021584 <tse_mac_init+0xc0>
+        tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *) tse_hw->desc_mem_base;
+ 8021518:	e0bffa17 	ldw	r2,-24(fp)
+ 802151c:	10800917 	ldw	r2,36(r2)
+ 8021520:	1009883a 	mov	r4,r2
+ 8021524:	e0bff417 	ldw	r2,-48(fp)
+ 8021528:	10c02924 	muli	r3,r2,164
+ 802152c:	008201b4 	movhi	r2,2054
+ 8021530:	1885883a 	add	r2,r3,r2
+ 8021534:	1135d315 	stw	r4,-10420(r2)
+        tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) 
+               (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))));          
+ 8021538:	e0bffa17 	ldw	r2,-24(fp)
+ 802153c:	10800917 	ldw	r2,36(r2)
+ 8021540:	10805004 	addi	r2,r2,320
+        tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) 
+ 8021544:	1009883a 	mov	r4,r2
+ 8021548:	e0bff417 	ldw	r2,-48(fp)
+ 802154c:	10c02924 	muli	r3,r2,164
+ 8021550:	008201b4 	movhi	r2,2054
+ 8021554:	1885883a 	add	r2,r3,r2
+ 8021558:	1135d415 	stw	r4,-10416(r2)
+        tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) 
+               (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE+1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))));          
+ 802155c:	e0bffa17 	ldw	r2,-24(fp)
+ 8021560:	10800917 	ldw	r2,36(r2)
+ 8021564:	1080a004 	addi	r2,r2,640
+        tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) 
+ 8021568:	1009883a 	mov	r4,r2
+ 802156c:	e0bff417 	ldw	r2,-48(fp)
+ 8021570:	10c02924 	muli	r3,r2,164
+ 8021574:	008201b4 	movhi	r2,2054
+ 8021578:	1885883a 	add	r2,r3,r2
+ 802157c:	1135d015 	stw	r4,-10432(r2)
+ 8021580:	00005106 	br	80216c8 <tse_mac_init+0x204>
+    }
+    else {
+        tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+ 8021584:	01005004 	movi	r4,320
+ 8021588:	80380a40 	call	80380a4 <alt_uncached_malloc>
+ 802158c:	1009883a 	mov	r4,r2
+ 8021590:	e0bff417 	ldw	r2,-48(fp)
+ 8021594:	10c02924 	muli	r3,r2,164
+ 8021598:	008201b4 	movhi	r2,2054
+ 802159c:	1885883a 	add	r2,r3,r2
+ 80215a0:	1135d315 	stw	r4,-10420(r2)
+        while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+ 80215a4:	00000b06 	br	80215d4 <tse_mac_init+0x110>
+        tse[iface].rxdesc[0]++;  //boundary
+ 80215a8:	e0bff417 	ldw	r2,-48(fp)
+ 80215ac:	10c02924 	muli	r3,r2,164
+ 80215b0:	008201b4 	movhi	r2,2054
+ 80215b4:	1885883a 	add	r2,r3,r2
+ 80215b8:	10b5d317 	ldw	r2,-10420(r2)
+ 80215bc:	10c00804 	addi	r3,r2,32
+ 80215c0:	e0bff417 	ldw	r2,-48(fp)
+ 80215c4:	11002924 	muli	r4,r2,164
+ 80215c8:	008201b4 	movhi	r2,2054
+ 80215cc:	2085883a 	add	r2,r4,r2
+ 80215d0:	10f5d315 	stw	r3,-10420(r2)
+        while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+ 80215d4:	e0bff417 	ldw	r2,-48(fp)
+ 80215d8:	10c02924 	muli	r3,r2,164
+ 80215dc:	008201b4 	movhi	r2,2054
+ 80215e0:	1885883a 	add	r2,r3,r2
+ 80215e4:	10b5d317 	ldw	r2,-10420(r2)
+ 80215e8:	108007cc 	andi	r2,r2,31
+ 80215ec:	103fee1e 	bne	r2,zero,80215a8 <tse_mac_init+0xe4>
+          
+        tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+ 80215f0:	01005004 	movi	r4,320
+ 80215f4:	80380a40 	call	80380a4 <alt_uncached_malloc>
+ 80215f8:	1009883a 	mov	r4,r2
+ 80215fc:	e0bff417 	ldw	r2,-48(fp)
+ 8021600:	10c02924 	muli	r3,r2,164
+ 8021604:	008201b4 	movhi	r2,2054
+ 8021608:	1885883a 	add	r2,r3,r2
+ 802160c:	1135d415 	stw	r4,-10416(r2)
+        while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+ 8021610:	00000b06 	br	8021640 <tse_mac_init+0x17c>
+        tse[iface].rxdesc[1]++;  //boundary  
+ 8021614:	e0bff417 	ldw	r2,-48(fp)
+ 8021618:	10c02924 	muli	r3,r2,164
+ 802161c:	008201b4 	movhi	r2,2054
+ 8021620:	1885883a 	add	r2,r3,r2
+ 8021624:	10b5d417 	ldw	r2,-10416(r2)
+ 8021628:	10c00804 	addi	r3,r2,32
+ 802162c:	e0bff417 	ldw	r2,-48(fp)
+ 8021630:	11002924 	muli	r4,r2,164
+ 8021634:	008201b4 	movhi	r2,2054
+ 8021638:	2085883a 	add	r2,r4,r2
+ 802163c:	10f5d415 	stw	r3,-10416(r2)
+        while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+ 8021640:	e0bff417 	ldw	r2,-48(fp)
+ 8021644:	10c02924 	muli	r3,r2,164
+ 8021648:	008201b4 	movhi	r2,2054
+ 802164c:	1885883a 	add	r2,r3,r2
+ 8021650:	10b5d417 	ldw	r2,-10416(r2)
+ 8021654:	108007cc 	andi	r2,r2,31
+ 8021658:	103fee1e 	bne	r2,zero,8021614 <tse_mac_init+0x150>
+    
+        tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+ 802165c:	01001804 	movi	r4,96
+ 8021660:	80380a40 	call	80380a4 <alt_uncached_malloc>
+ 8021664:	1009883a 	mov	r4,r2
+ 8021668:	e0bff417 	ldw	r2,-48(fp)
+ 802166c:	10c02924 	muli	r3,r2,164
+ 8021670:	008201b4 	movhi	r2,2054
+ 8021674:	1885883a 	add	r2,r3,r2
+ 8021678:	1135d015 	stw	r4,-10432(r2)
+        while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0)  
+ 802167c:	00000b06 	br	80216ac <tse_mac_init+0x1e8>
+          tse[iface].txdesc++;  //boundary
+ 8021680:	e0bff417 	ldw	r2,-48(fp)
+ 8021684:	10c02924 	muli	r3,r2,164
+ 8021688:	008201b4 	movhi	r2,2054
+ 802168c:	1885883a 	add	r2,r3,r2
+ 8021690:	10b5d017 	ldw	r2,-10432(r2)
+ 8021694:	10c00804 	addi	r3,r2,32
+ 8021698:	e0bff417 	ldw	r2,-48(fp)
+ 802169c:	11002924 	muli	r4,r2,164
+ 80216a0:	008201b4 	movhi	r2,2054
+ 80216a4:	2085883a 	add	r2,r4,r2
+ 80216a8:	10f5d015 	stw	r3,-10432(r2)
+        while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0)  
+ 80216ac:	e0bff417 	ldw	r2,-48(fp)
+ 80216b0:	10c02924 	muli	r3,r2,164
+ 80216b4:	008201b4 	movhi	r2,2054
+ 80216b8:	1885883a 	add	r2,r3,r2
+ 80216bc:	10b5d017 	ldw	r2,-10432(r2)
+ 80216c0:	108007cc 	andi	r2,r2,31
+ 80216c4:	103fee1e 	bne	r2,zero,8021680 <tse_mac_init+0x1bc>
+    }
+   
+    /* Get the Rx and Tx MSGDMA addresses */
+    msgdma_tx_dev = alt_msgdma_open(tse_hw->tse_msgdma_tx); 
+ 80216c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80216cc:	10800617 	ldw	r2,24(r2)
+ 80216d0:	1009883a 	mov	r4,r2
+ 80216d4:	801fe940 	call	801fe94 <alt_msgdma_open>
+ 80216d8:	e0bff915 	stw	r2,-28(fp)
+    
+    if(!msgdma_tx_dev) {
+ 80216dc:	e0bff917 	ldw	r2,-28(fp)
+ 80216e0:	1000051e 	bne	r2,zero,80216f8 <tse_mac_init+0x234>
+      dprintf("[altera_eth_tse_init] Error opening TX MSGDMA\n");
+ 80216e4:	01020174 	movhi	r4,2053
+ 80216e8:	2125e004 	addi	r4,r4,-26752
+ 80216ec:	8002d9c0 	call	8002d9c <puts>
+      return ENP_RESOURCE;
+ 80216f0:	00bffa84 	movi	r2,-22
+ 80216f4:	00020706 	br	8021f14 <tse_mac_init+0xa50>
+    }
+  
+    msgdma_rx_dev = alt_msgdma_open(tse_hw->tse_msgdma_rx);
+ 80216f8:	e0bffa17 	ldw	r2,-24(fp)
+ 80216fc:	10800717 	ldw	r2,28(r2)
+ 8021700:	1009883a 	mov	r4,r2
+ 8021704:	801fe940 	call	801fe94 <alt_msgdma_open>
+ 8021708:	e0bff815 	stw	r2,-32(fp)
+    if(!msgdma_rx_dev) {
+ 802170c:	e0bff817 	ldw	r2,-32(fp)
+ 8021710:	1000051e 	bne	r2,zero,8021728 <tse_mac_init+0x264>
+      dprintf("[altera_eth_tse_init] Error opening RX MSGDMA\n");
+ 8021714:	01020174 	movhi	r4,2053
+ 8021718:	2125ec04 	addi	r4,r4,-26704
+ 802171c:	8002d9c0 	call	8002d9c <puts>
+      return ENP_RESOURCE;
+ 8021720:	00bffa84 	movi	r2,-22
+ 8021724:	0001fb06 	br	8021f14 <tse_mac_init+0xa50>
+    }
+
+    /* Initialize mtip_mac_trans_info structure with values from <system.h>*/
+    tse_mac_initTransInfo2(&tse[iface].mi, (int)tse_hw->tse_mac_base,
+ 8021728:	e0bff417 	ldw	r2,-48(fp)
+ 802172c:	10802924 	muli	r2,r2,164
+ 8021730:	10c00104 	addi	r3,r2,4
+ 8021734:	008201b4 	movhi	r2,2054
+ 8021738:	10b5c204 	addi	r2,r2,-10488
+ 802173c:	1887883a 	add	r3,r3,r2
+ 8021740:	e0bffa17 	ldw	r2,-24(fp)
+ 8021744:	10800017 	ldw	r2,0(r2)
+ 8021748:	e13ff917 	ldw	r4,-28(fp)
+ 802174c:	e17ff817 	ldw	r5,-32(fp)
+ 8021750:	d8000015 	stw	zero,0(sp)
+ 8021754:	280f883a 	mov	r7,r5
+ 8021758:	200d883a 	mov	r6,r4
+ 802175c:	100b883a 	mov	r5,r2
+ 8021760:	1809883a 	mov	r4,r3
+ 8021764:	8017b500 	call	8017b50 <tse_mac_initTransInfo2>
+                                   (unsigned int)msgdma_tx_dev,            
+                                   (unsigned int)msgdma_rx_dev,
+                                   0);
+
+   /* reset the PHY if necessary */   
+   result = getPHYSpeed(tse[iface].mi.base);
+ 8021768:	e0bff417 	ldw	r2,-48(fp)
+ 802176c:	10c02924 	muli	r3,r2,164
+ 8021770:	008201b4 	movhi	r2,2054
+ 8021774:	1885883a 	add	r2,r3,r2
+ 8021778:	10b5c317 	ldw	r2,-10484(r2)
+ 802177c:	1009883a 	mov	r4,r2
+ 8021780:	8018e540 	call	8018e54 <getPHYSpeed>
+ 8021784:	e0bff715 	stw	r2,-36(fp)
+   speed = (result >> 1) & 0x07;
+ 8021788:	e0bff717 	ldw	r2,-36(fp)
+ 802178c:	1005d07a 	srai	r2,r2,1
+ 8021790:	108001cc 	andi	r2,r2,7
+ 8021794:	e0bff615 	stw	r2,-40(fp)
+   duplex = result & 0x01;
+ 8021798:	e0bff717 	ldw	r2,-36(fp)
+ 802179c:	1080004c 	andi	r2,r2,1
+ 80217a0:	e0bff515 	stw	r2,-44(fp)
+   
+   /* reset the mac */ 
+   IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,
+ 80217a4:	e0bff417 	ldw	r2,-48(fp)
+ 80217a8:	10c02924 	muli	r3,r2,164
+ 80217ac:	008201b4 	movhi	r2,2054
+ 80217b0:	1885883a 	add	r2,r3,r2
+ 80217b4:	10b5c317 	ldw	r2,-10484(r2)
+ 80217b8:	10800204 	addi	r2,r2,8
+ 80217bc:	00c800c4 	movi	r3,8195
+ 80217c0:	10c00035 	stwio	r3,0(r2)
+                             mmac_cc_SW_RESET_mask | 
+                             mmac_cc_TX_ENA_mask | 
+                             mmac_cc_RX_ENA_mask);
+  
+   x=0;
+ 80217c4:	e03ffe15 	stw	zero,-8(fp)
+   while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & 
+ 80217c8:	00000506 	br	80217e0 <tse_mac_init+0x31c>
+         ALTERA_TSEMAC_CMD_SW_RESET_MSK) {
+     if( x++ > 10000 ) {
+ 80217cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80217d0:	10c00044 	addi	r3,r2,1
+ 80217d4:	e0fffe15 	stw	r3,-8(fp)
+ 80217d8:	1089c450 	cmplti	r2,r2,10001
+ 80217dc:	10000a26 	beq	r2,zero,8021808 <tse_mac_init+0x344>
+   while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & 
+ 80217e0:	e0bff417 	ldw	r2,-48(fp)
+ 80217e4:	10c02924 	muli	r3,r2,164
+ 80217e8:	008201b4 	movhi	r2,2054
+ 80217ec:	1885883a 	add	r2,r3,r2
+ 80217f0:	10b5c317 	ldw	r2,-10484(r2)
+ 80217f4:	10800204 	addi	r2,r2,8
+ 80217f8:	10800037 	ldwio	r2,0(r2)
+ 80217fc:	1088000c 	andi	r2,r2,8192
+ 8021800:	103ff21e 	bne	r2,zero,80217cc <tse_mac_init+0x308>
+ 8021804:	00000106 	br	802180c <tse_mac_init+0x348>
+       break;
+ 8021808:	0001883a 	nop
+     }
+   }
+   if(x >= 10000) {
+ 802180c:	e0bffe17 	ldw	r2,-8(fp)
+ 8021810:	1089c410 	cmplti	r2,r2,10000
+ 8021814:	1000031e 	bne	r2,zero,8021824 <tse_mac_init+0x360>
+     dprintf("TSEMAC SW reset bit never cleared!\n");
+ 8021818:	01020174 	movhi	r4,2053
+ 802181c:	2125f804 	addi	r4,r4,-26656
+ 8021820:	8002d9c0 	call	8002d9c <puts>
+   }
+
+   dat = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base);
+ 8021824:	e0bff417 	ldw	r2,-48(fp)
+ 8021828:	10c02924 	muli	r3,r2,164
+ 802182c:	008201b4 	movhi	r2,2054
+ 8021830:	1885883a 	add	r2,r3,r2
+ 8021834:	10b5c317 	ldw	r2,-10484(r2)
+ 8021838:	10800204 	addi	r2,r2,8
+ 802183c:	10800037 	ldwio	r2,0(r2)
+ 8021840:	e0bfff15 	stw	r2,-4(fp)
+   if( (dat & 0x03) != 0 ) {
+ 8021844:	e0bfff17 	ldw	r2,-4(fp)
+ 8021848:	108000cc 	andi	r2,r2,3
+ 802184c:	10000526 	beq	r2,zero,8021864 <tse_mac_init+0x3a0>
+     dprintf("WARN: RX/TX not disabled after reset... missing PHY clock? CMD_CONFIG=0x%08x\n", dat);
+ 8021850:	e17fff17 	ldw	r5,-4(fp)
+ 8021854:	01020174 	movhi	r4,2053
+ 8021858:	21260104 	addi	r4,r4,-26620
+ 802185c:	8002c780 	call	8002c78 <printf>
+ 8021860:	00000506 	br	8021878 <tse_mac_init+0x3b4>
+   } 
+   else {
+     dprintf("OK, x=%d, CMD_CONFIG=0x%08x\n", x, dat);
+ 8021864:	e1bfff17 	ldw	r6,-4(fp)
+ 8021868:	e17ffe17 	ldw	r5,-8(fp)
+ 802186c:	01020174 	movhi	r4,2053
+ 8021870:	21261504 	addi	r4,r4,-26540
+ 8021874:	8002c780 	call	8002c78 <printf>
+  
+   /* Hack code to determine the Channel number <- Someone please fix this ugly code in the future */
+   extern alt_u8 mac_group_count;
+   extern alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM];
+      
+   if(tse_hw->use_shared_fifo == 1) {
+ 8021878:	e0bffa17 	ldw	r2,-24(fp)
+ 802187c:	10800a03 	ldbu	r2,40(r2)
+ 8021880:	10803fcc 	andi	r2,r2,255
+ 8021884:	10800058 	cmpnei	r2,r2,1
+ 8021888:	10002c1e 	bne	r2,zero,802193c <tse_mac_init+0x478>
+     int channel_loop = 0;
+ 802188c:	e03ffc15 	stw	zero,-16(fp)
+     int mac_loop = 0;
+ 8021890:	e03ffb15 	stw	zero,-20(fp)
+         
+     for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) {
+ 8021894:	e03ffc15 	stw	zero,-16(fp)
+ 8021898:	00002406 	br	802192c <tse_mac_init+0x468>
+       for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) {
+ 802189c:	e03ffb15 	stw	zero,-20(fp)
+ 80218a0:	00001606 	br	80218fc <tse_mac_init+0x438>
+         if (pmac_groups[channel_loop]->pmac_info[mac_loop]->psys_info == tse_hw) {
+ 80218a4:	e0bffc17 	ldw	r2,-16(fp)
+ 80218a8:	100690ba 	slli	r3,r2,2
+ 80218ac:	008201b4 	movhi	r2,2054
+ 80218b0:	1885883a 	add	r2,r3,r2
+ 80218b4:	10f5aa17 	ldw	r3,-10584(r2)
+ 80218b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80218bc:	10800044 	addi	r2,r2,1
+ 80218c0:	100490ba 	slli	r2,r2,2
+ 80218c4:	1885883a 	add	r2,r3,r2
+ 80218c8:	10800017 	ldw	r2,0(r2)
+ 80218cc:	10800217 	ldw	r2,8(r2)
+ 80218d0:	e0fffa17 	ldw	r3,-24(fp)
+ 80218d4:	1880061e 	bne	r3,r2,80218f0 <tse_mac_init+0x42c>
+           tse[iface].channel = mac_loop;
+ 80218d8:	e0bff417 	ldw	r2,-48(fp)
+ 80218dc:	11002924 	muli	r4,r2,164
+ 80218e0:	e0fffb17 	ldw	r3,-20(fp)
+ 80218e4:	008201b4 	movhi	r2,2054
+ 80218e8:	2085883a 	add	r2,r4,r2
+ 80218ec:	10f5ce15 	stw	r3,-10440(r2)
+       for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) {
+ 80218f0:	e0bffb17 	ldw	r2,-20(fp)
+ 80218f4:	10800044 	addi	r2,r2,1
+ 80218f8:	e0bffb15 	stw	r2,-20(fp)
+ 80218fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8021900:	100690ba 	slli	r3,r2,2
+ 8021904:	008201b4 	movhi	r2,2054
+ 8021908:	1885883a 	add	r2,r3,r2
+ 802190c:	10b5aa17 	ldw	r2,-10584(r2)
+ 8021910:	10800003 	ldbu	r2,0(r2)
+ 8021914:	10803fcc 	andi	r2,r2,255
+ 8021918:	e0fffb17 	ldw	r3,-20(fp)
+ 802191c:	18bfe116 	blt	r3,r2,80218a4 <tse_mac_init+0x3e0>
+     for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) {
+ 8021920:	e0bffc17 	ldw	r2,-16(fp)
+ 8021924:	10800044 	addi	r2,r2,1
+ 8021928:	e0bffc15 	stw	r2,-16(fp)
+ 802192c:	d0a05b43 	ldbu	r2,-32403(gp)
+ 8021930:	10803fcc 	andi	r2,r2,255
+ 8021934:	e0fffc17 	ldw	r3,-16(fp)
+ 8021938:	18bfd816 	blt	r3,r2,802189c <tse_mac_init+0x3d8>
+       }
+     }
+   }
+   /* End of Hack code */
+  
+   if(tse_hw->use_shared_fifo == 1) {
+ 802193c:	e0bffa17 	ldw	r2,-24(fp)
+ 8021940:	10800a03 	ldbu	r2,40(r2)
+ 8021944:	10803fcc 	andi	r2,r2,255
+ 8021948:	10800058 	cmpnei	r2,r2,1
+ 802194c:	10000f1e 	bne	r2,zero,802198c <tse_mac_init+0x4c8>
+      IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,tse_hw->tse_shared_fifo_rx_depth);
+ 8021950:	e0bffa17 	ldw	r2,-24(fp)
+ 8021954:	10800e17 	ldw	r2,56(r2)
+ 8021958:	1007883a 	mov	r3,r2
+ 802195c:	e0bffa17 	ldw	r2,-24(fp)
+ 8021960:	10801017 	ldw	r2,64(r2)
+ 8021964:	18800035 	stwio	r2,0(r3)
+      IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,((tse_hw->tse_shared_fifo_rx_depth) - 140));
+ 8021968:	e0bffa17 	ldw	r2,-24(fp)
+ 802196c:	10800e17 	ldw	r2,56(r2)
+ 8021970:	10800204 	addi	r2,r2,8
+ 8021974:	1007883a 	mov	r3,r2
+ 8021978:	e0bffa17 	ldw	r2,-24(fp)
+ 802197c:	10801017 	ldw	r2,64(r2)
+ 8021980:	10bfdd04 	addi	r2,r2,-140
+ 8021984:	18800035 	stwio	r2,0(r3)
+ 8021988:	00004c06 	br	8021abc <tse_mac_init+0x5f8>
+   }
+   else {
+      /* Initialize MAC registers */
+      IOWR_ALTERA_TSEMAC_FRM_LENGTH(tse[iface].mi.base, ALTERA_TSE_MAC_MAX_FRAME_LENGTH); 
+ 802198c:	e0bff417 	ldw	r2,-48(fp)
+ 8021990:	10c02924 	muli	r3,r2,164
+ 8021994:	008201b4 	movhi	r2,2054
+ 8021998:	1885883a 	add	r2,r3,r2
+ 802199c:	10b5c317 	ldw	r2,-10484(r2)
+ 80219a0:	10800504 	addi	r2,r2,20
+ 80219a4:	00c17b84 	movi	r3,1518
+ 80219a8:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse[iface].mi.base, 8);
+ 80219ac:	e0bff417 	ldw	r2,-48(fp)
+ 80219b0:	10c02924 	muli	r3,r2,164
+ 80219b4:	008201b4 	movhi	r2,2054
+ 80219b8:	1885883a 	add	r2,r3,r2
+ 80219bc:	10b5c317 	ldw	r2,-10484(r2)
+ 80219c0:	10800b04 	addi	r2,r2,44
+ 80219c4:	00c00204 	movi	r3,8
+ 80219c8:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse[iface].mi.base, 8);
+ 80219cc:	e0bff417 	ldw	r2,-48(fp)
+ 80219d0:	10c02924 	muli	r3,r2,164
+ 80219d4:	008201b4 	movhi	r2,2054
+ 80219d8:	1885883a 	add	r2,r3,r2
+ 80219dc:	10b5c317 	ldw	r2,-10484(r2)
+ 80219e0:	10800c04 	addi	r2,r2,48
+ 80219e4:	00c00204 	movi	r3,8
+ 80219e8:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse[iface].mi.base, 8);
+ 80219ec:	e0bff417 	ldw	r2,-48(fp)
+ 80219f0:	10c02924 	muli	r3,r2,164
+ 80219f4:	008201b4 	movhi	r2,2054
+ 80219f8:	1885883a 	add	r2,r3,r2
+ 80219fc:	10b5c317 	ldw	r2,-10484(r2)
+ 8021a00:	10800d04 	addi	r2,r2,52
+ 8021a04:	00c00204 	movi	r3,8
+ 8021a08:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse[iface].mi.base,  3);
+ 8021a0c:	e0bff417 	ldw	r2,-48(fp)
+ 8021a10:	10c02924 	muli	r3,r2,164
+ 8021a14:	008201b4 	movhi	r2,2054
+ 8021a18:	1885883a 	add	r2,r3,r2
+ 8021a1c:	10b5c317 	ldw	r2,-10484(r2)
+ 8021a20:	10800e04 	addi	r2,r2,56
+ 8021a24:	00c000c4 	movi	r3,3
+ 8021a28:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_tx_depth - 16); //1024/4;  
+ 8021a2c:	e0bff417 	ldw	r2,-48(fp)
+ 8021a30:	10c02924 	muli	r3,r2,164
+ 8021a34:	008201b4 	movhi	r2,2054
+ 8021a38:	1885883a 	add	r2,r3,r2
+ 8021a3c:	10b5c317 	ldw	r2,-10484(r2)
+ 8021a40:	10800904 	addi	r2,r2,36
+ 8021a44:	e0fffa17 	ldw	r3,-24(fp)
+ 8021a48:	18c00117 	ldw	r3,4(r3)
+ 8021a4c:	18fffc04 	addi	r3,r3,-16
+ 8021a50:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse[iface].mi.base,  0); //32/4; // start transmit when there are 48 bytes
+ 8021a54:	e0bff417 	ldw	r2,-48(fp)
+ 8021a58:	10c02924 	muli	r3,r2,164
+ 8021a5c:	008201b4 	movhi	r2,2054
+ 8021a60:	1885883a 	add	r2,r3,r2
+ 8021a64:	10b5c317 	ldw	r2,-10484(r2)
+ 8021a68:	10800a04 	addi	r2,r2,40
+ 8021a6c:	0007883a 	mov	r3,zero
+ 8021a70:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_rx_depth - 16); //4000/4);
+ 8021a74:	e0bff417 	ldw	r2,-48(fp)
+ 8021a78:	10c02924 	muli	r3,r2,164
+ 8021a7c:	008201b4 	movhi	r2,2054
+ 8021a80:	1885883a 	add	r2,r3,r2
+ 8021a84:	10b5c317 	ldw	r2,-10484(r2)
+ 8021a88:	10800704 	addi	r2,r2,28
+ 8021a8c:	e0fffa17 	ldw	r3,-24(fp)
+ 8021a90:	18c00217 	ldw	r3,8(r3)
+ 8021a94:	18fffc04 	addi	r3,r3,-16
+ 8021a98:	10c00035 	stwio	r3,0(r2)
+      IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse[iface].mi.base,  0);
+ 8021a9c:	e0bff417 	ldw	r2,-48(fp)
+ 8021aa0:	10c02924 	muli	r3,r2,164
+ 8021aa4:	008201b4 	movhi	r2,2054
+ 8021aa8:	1885883a 	add	r2,r3,r2
+ 8021aac:	10b5c317 	ldw	r2,-10484(r2)
+ 8021ab0:	10800804 	addi	r2,r2,32
+ 8021ab4:	0007883a 	mov	r3,zero
+ 8021ab8:	10c00035 	stwio	r3,0(r2)
+      tse[iface].rxShift16OK = 0;
+    }
+  } /* if(ETHHDR_BIAS == 0) */
+ 
+  if(ETHHDR_BIAS == 2) {
+    IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK);
+ 8021abc:	e0bff417 	ldw	r2,-48(fp)
+ 8021ac0:	10c02924 	muli	r3,r2,164
+ 8021ac4:	008201b4 	movhi	r2,2054
+ 8021ac8:	1885883a 	add	r2,r3,r2
+ 8021acc:	10b5c317 	ldw	r2,-10484(r2)
+ 8021ad0:	10803a04 	addi	r2,r2,232
+ 8021ad4:	00c00134 	movhi	r3,4
+ 8021ad8:	10c00035 	stwio	r3,0(r2)
+ 
+    /*
+     * check if the MAC supports the 16-bit shift option allowing us
+     * to send BIASed frames without copying. Used by the send function later.
+     */
+    if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) &
+ 8021adc:	e0bff417 	ldw	r2,-48(fp)
+ 8021ae0:	10c02924 	muli	r3,r2,164
+ 8021ae4:	008201b4 	movhi	r2,2054
+ 8021ae8:	1885883a 	add	r2,r3,r2
+ 8021aec:	10b5c317 	ldw	r2,-10484(r2)
+ 8021af0:	10803a04 	addi	r2,r2,232
+ 8021af4:	10800037 	ldwio	r2,0(r2)
+ 8021af8:	1080012c 	andhi	r2,r2,4
+ 8021afc:	10001826 	beq	r2,zero,8021b60 <tse_mac_init+0x69c>
+      ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) {
+      tse[iface].txShift16OK = 1;
+ 8021b00:	e0bff417 	ldw	r2,-48(fp)
+ 8021b04:	11002924 	muli	r4,r2,164
+ 8021b08:	00c00044 	movi	r3,1
+ 8021b0c:	008201b4 	movhi	r2,2054
+ 8021b10:	2085883a 	add	r2,r4,r2
+ 8021b14:	10f5cb15 	stw	r3,-10452(r2)
+      dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS);
+      return ENP_LOGIC;
+    }
+  
+    /* Enable RX shift 16 for alignment of all received frames on 16-bit start address */
+    IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK);
+ 8021b18:	e0bff417 	ldw	r2,-48(fp)
+ 8021b1c:	10c02924 	muli	r3,r2,164
+ 8021b20:	008201b4 	movhi	r2,2054
+ 8021b24:	1885883a 	add	r2,r3,r2
+ 8021b28:	10b5c317 	ldw	r2,-10484(r2)
+ 8021b2c:	10803b04 	addi	r2,r2,236
+ 8021b30:	00c08034 	movhi	r3,512
+ 8021b34:	10c00035 	stwio	r3,0(r2)
+ 
+    /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register  */ 
+    if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK)
+ 8021b38:	e0bff417 	ldw	r2,-48(fp)
+ 8021b3c:	10c02924 	muli	r3,r2,164
+ 8021b40:	008201b4 	movhi	r2,2054
+ 8021b44:	1885883a 	add	r2,r3,r2
+ 8021b48:	10b5c317 	ldw	r2,-10484(r2)
+ 8021b4c:	10803b04 	addi	r2,r2,236
+ 8021b50:	10800037 	ldwio	r2,0(r2)
+ 8021b54:	1080802c 	andhi	r2,r2,512
+ 8021b58:	10001926 	beq	r2,zero,8021bc0 <tse_mac_init+0x6fc>
+ 8021b5c:	00000b06 	br	8021b8c <tse_mac_init+0x6c8>
+      tse[iface].txShift16OK = 0;
+ 8021b60:	e0bff417 	ldw	r2,-48(fp)
+ 8021b64:	10c02924 	muli	r3,r2,164
+ 8021b68:	008201b4 	movhi	r2,2054
+ 8021b6c:	1885883a 	add	r2,r3,r2
+ 8021b70:	1035cb15 	stw	zero,-10452(r2)
+      dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS);
+ 8021b74:	01400084 	movi	r5,2
+ 8021b78:	01020174 	movhi	r4,2053
+ 8021b7c:	21261d04 	addi	r4,r4,-26508
+ 8021b80:	8002c780 	call	8002c78 <printf>
+      return ENP_LOGIC;
+ 8021b84:	00bffd44 	movi	r2,-11
+ 8021b88:	0000e206 	br	8021f14 <tse_mac_init+0xa50>
+    {
+      tse[iface].rxShift16OK = 1;
+ 8021b8c:	e0bff417 	ldw	r2,-48(fp)
+ 8021b90:	11002924 	muli	r4,r2,164
+ 8021b94:	00c00044 	movi	r3,1
+ 8021b98:	008201b4 	movhi	r2,2054
+ 8021b9c:	2085883a 	add	r2,r4,r2
+ 8021ba0:	10f5cc15 	stw	r3,-10448(r2)
+      return ENP_LOGIC;
+    }
+  } /* if(ETHHDR_BIAS == 2) */
+  
+  /* enable MAC */
+  dat = ALTERA_TSEMAC_CMD_TX_ENA_MSK       |
+ 8021ba4:	00810034 	movhi	r2,1024
+ 8021ba8:	108080c4 	addi	r2,r2,515
+ 8021bac:	e0bfff15 	stw	r2,-4(fp)
+        ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK  |
+        ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK;  /* automatically discard frames with CRC errors */
+    
+  
+  /* 1000 Mbps */
+  if(speed == 0x01) {
+ 8021bb0:	e0bff617 	ldw	r2,-40(fp)
+ 8021bb4:	10800058 	cmpnei	r2,r2,1
+ 8021bb8:	1000151e 	bne	r2,zero,8021c10 <tse_mac_init+0x74c>
+ 8021bbc:	00000b06 	br	8021bec <tse_mac_init+0x728>
+      tse[iface].rxShift16OK = 0;
+ 8021bc0:	e0bff417 	ldw	r2,-48(fp)
+ 8021bc4:	10c02924 	muli	r3,r2,164
+ 8021bc8:	008201b4 	movhi	r2,2054
+ 8021bcc:	1885883a 	add	r2,r3,r2
+ 8021bd0:	1035cc15 	stw	zero,-10448(r2)
+      dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS);
+ 8021bd4:	01400084 	movi	r5,2
+ 8021bd8:	01020174 	movhi	r4,2053
+ 8021bdc:	21263504 	addi	r4,r4,-26412
+ 8021be0:	8002c780 	call	8002c78 <printf>
+      return ENP_LOGIC;
+ 8021be4:	00bffd44 	movi	r2,-11
+ 8021be8:	0000ca06 	br	8021f14 <tse_mac_init+0xa50>
+    dat |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8021bec:	e0bfff17 	ldw	r2,-4(fp)
+ 8021bf0:	10800214 	ori	r2,r2,8
+ 8021bf4:	e0bfff15 	stw	r2,-4(fp)
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8021bf8:	e0ffff17 	ldw	r3,-4(fp)
+ 8021bfc:	00bf8034 	movhi	r2,65024
+ 8021c00:	10bfffc4 	addi	r2,r2,-1
+ 8021c04:	1884703a 	and	r2,r3,r2
+ 8021c08:	e0bfff15 	stw	r2,-4(fp)
+ 8021c0c:	00002106 	br	8021c94 <tse_mac_init+0x7d0>
+  }
+  /* 100 Mbps */
+  else if(speed == 0x02) {
+ 8021c10:	e0bff617 	ldw	r2,-40(fp)
+ 8021c14:	10800098 	cmpnei	r2,r2,2
+ 8021c18:	10000a1e 	bne	r2,zero,8021c44 <tse_mac_init+0x780>
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8021c1c:	e0ffff17 	ldw	r3,-4(fp)
+ 8021c20:	00bffdc4 	movi	r2,-9
+ 8021c24:	1884703a 	and	r2,r3,r2
+ 8021c28:	e0bfff15 	stw	r2,-4(fp)
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8021c2c:	e0ffff17 	ldw	r3,-4(fp)
+ 8021c30:	00bf8034 	movhi	r2,65024
+ 8021c34:	10bfffc4 	addi	r2,r2,-1
+ 8021c38:	1884703a 	and	r2,r3,r2
+ 8021c3c:	e0bfff15 	stw	r2,-4(fp)
+ 8021c40:	00001406 	br	8021c94 <tse_mac_init+0x7d0>
+  }
+  /* 10 Mbps */
+  else if(speed == 0x04) {
+ 8021c44:	e0bff617 	ldw	r2,-40(fp)
+ 8021c48:	10800118 	cmpnei	r2,r2,4
+ 8021c4c:	1000081e 	bne	r2,zero,8021c70 <tse_mac_init+0x7ac>
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8021c50:	e0ffff17 	ldw	r3,-4(fp)
+ 8021c54:	00bffdc4 	movi	r2,-9
+ 8021c58:	1884703a 	and	r2,r3,r2
+ 8021c5c:	e0bfff15 	stw	r2,-4(fp)
+    dat |= ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8021c60:	e0bfff17 	ldw	r2,-4(fp)
+ 8021c64:	10808034 	orhi	r2,r2,512
+ 8021c68:	e0bfff15 	stw	r2,-4(fp)
+ 8021c6c:	00000906 	br	8021c94 <tse_mac_init+0x7d0>
+  }
+  /* default to 100 Mbps if returned invalid speed */
+  else {
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+ 8021c70:	e0ffff17 	ldw	r3,-4(fp)
+ 8021c74:	00bffdc4 	movi	r2,-9
+ 8021c78:	1884703a 	and	r2,r3,r2
+ 8021c7c:	e0bfff15 	stw	r2,-4(fp)
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+ 8021c80:	e0ffff17 	ldw	r3,-4(fp)
+ 8021c84:	00bf8034 	movhi	r2,65024
+ 8021c88:	10bfffc4 	addi	r2,r2,-1
+ 8021c8c:	1884703a 	and	r2,r3,r2
+ 8021c90:	e0bfff15 	stw	r2,-4(fp)
+  }
+  
+  /* Half Duplex */
+  if(duplex == TSE_PHY_DUPLEX_HALF) {
+ 8021c94:	e0bff517 	ldw	r2,-44(fp)
+ 8021c98:	1000041e 	bne	r2,zero,8021cac <tse_mac_init+0x7e8>
+    dat |= ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+ 8021c9c:	e0bfff17 	ldw	r2,-4(fp)
+ 8021ca0:	10810014 	ori	r2,r2,1024
+ 8021ca4:	e0bfff15 	stw	r2,-4(fp)
+ 8021ca8:	00000406 	br	8021cbc <tse_mac_init+0x7f8>
+  }
+  /* Full Duplex */
+  else {
+    dat &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+ 8021cac:	e0ffff17 	ldw	r3,-4(fp)
+ 8021cb0:	00beffc4 	movi	r2,-1025
+ 8021cb4:	1884703a 	and	r2,r3,r2
+ 8021cb8:	e0bfff15 	stw	r2,-4(fp)
+  }
+          
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, dat);
+ 8021cbc:	e0bff417 	ldw	r2,-48(fp)
+ 8021cc0:	10c02924 	muli	r3,r2,164
+ 8021cc4:	008201b4 	movhi	r2,2054
+ 8021cc8:	1885883a 	add	r2,r3,r2
+ 8021ccc:	10b5c317 	ldw	r2,-10484(r2)
+ 8021cd0:	10800204 	addi	r2,r2,8
+ 8021cd4:	e0ffff17 	ldw	r3,-4(fp)
+ 8021cd8:	10c00035 	stwio	r3,0(r2)
+  dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", 
+  IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base));
+ 8021cdc:	e0bff417 	ldw	r2,-48(fp)
+ 8021ce0:	10c02924 	muli	r3,r2,164
+ 8021ce4:	008201b4 	movhi	r2,2054
+ 8021ce8:	1885883a 	add	r2,r3,r2
+ 8021cec:	10b5c317 	ldw	r2,-10484(r2)
+  dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", 
+ 8021cf0:	10800204 	addi	r2,r2,8
+ 8021cf4:	10800037 	ldwio	r2,0(r2)
+ 8021cf8:	100b883a 	mov	r5,r2
+ 8021cfc:	01020174 	movhi	r4,2053
+ 8021d00:	21264d04 	addi	r4,r4,-26316
+ 8021d04:	8002c780 	call	8002c78 <printf>
+  
+                          
+#ifdef ALT_INICHE
+   /* Set the MAC address */  
+   IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base,
+ 8021d08:	e0bff417 	ldw	r2,-48(fp)
+ 8021d0c:	10c02924 	muli	r3,r2,164
+ 8021d10:	008201b4 	movhi	r2,2054
+ 8021d14:	1885883a 	add	r2,r3,r2
+ 8021d18:	10b5c317 	ldw	r2,-10484(r2)
+ 8021d1c:	10c00304 	addi	r3,r2,12
+ 8021d20:	e0bff417 	ldw	r2,-48(fp)
+ 8021d24:	11002924 	muli	r4,r2,164
+ 8021d28:	008201b4 	movhi	r2,2054
+ 8021d2c:	2085883a 	add	r2,r4,r2
+ 8021d30:	10b5c803 	ldbu	r2,-10464(r2)
+ 8021d34:	11003fcc 	andi	r4,r2,255
+ 8021d38:	e0bff417 	ldw	r2,-48(fp)
+ 8021d3c:	11402924 	muli	r5,r2,164
+ 8021d40:	008201b4 	movhi	r2,2054
+ 8021d44:	2885883a 	add	r2,r5,r2
+ 8021d48:	10b5c843 	ldbu	r2,-10463(r2)
+ 8021d4c:	10803fcc 	andi	r2,r2,255
+ 8021d50:	1004923a 	slli	r2,r2,8
+ 8021d54:	2088b03a 	or	r4,r4,r2
+ 8021d58:	e0bff417 	ldw	r2,-48(fp)
+ 8021d5c:	11402924 	muli	r5,r2,164
+ 8021d60:	008201b4 	movhi	r2,2054
+ 8021d64:	2885883a 	add	r2,r5,r2
+ 8021d68:	10b5c883 	ldbu	r2,-10462(r2)
+ 8021d6c:	10803fcc 	andi	r2,r2,255
+ 8021d70:	1004943a 	slli	r2,r2,16
+ 8021d74:	2088b03a 	or	r4,r4,r2
+ 8021d78:	e0bff417 	ldw	r2,-48(fp)
+ 8021d7c:	11402924 	muli	r5,r2,164
+ 8021d80:	008201b4 	movhi	r2,2054
+ 8021d84:	2885883a 	add	r2,r5,r2
+ 8021d88:	10b5c8c3 	ldbu	r2,-10461(r2)
+ 8021d8c:	10803fcc 	andi	r2,r2,255
+ 8021d90:	1004963a 	slli	r2,r2,24
+ 8021d94:	2084b03a 	or	r2,r4,r2
+ 8021d98:	18800035 	stwio	r2,0(r3)
+                           ((int)((unsigned char) tse[iface].mac_addr[0]) | 
+                            (int)((unsigned char) tse[iface].mac_addr[1] <<  8) |
+                            (int)((unsigned char) tse[iface].mac_addr[2] << 16) | 
+                            (int)((unsigned char) tse[iface].mac_addr[3] << 24)));
+  
+   IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, 
+ 8021d9c:	e0bff417 	ldw	r2,-48(fp)
+ 8021da0:	10c02924 	muli	r3,r2,164
+ 8021da4:	008201b4 	movhi	r2,2054
+ 8021da8:	1885883a 	add	r2,r3,r2
+ 8021dac:	10b5c317 	ldw	r2,-10484(r2)
+ 8021db0:	10c00404 	addi	r3,r2,16
+ 8021db4:	e0bff417 	ldw	r2,-48(fp)
+ 8021db8:	11002924 	muli	r4,r2,164
+ 8021dbc:	008201b4 	movhi	r2,2054
+ 8021dc0:	2085883a 	add	r2,r4,r2
+ 8021dc4:	10b5c903 	ldbu	r2,-10460(r2)
+ 8021dc8:	11003fcc 	andi	r4,r2,255
+ 8021dcc:	e0bff417 	ldw	r2,-48(fp)
+ 8021dd0:	11402924 	muli	r5,r2,164
+ 8021dd4:	008201b4 	movhi	r2,2054
+ 8021dd8:	2885883a 	add	r2,r5,r2
+ 8021ddc:	10b5c943 	ldbu	r2,-10459(r2)
+ 8021de0:	10803fcc 	andi	r2,r2,255
+ 8021de4:	1004923a 	slli	r2,r2,8
+ 8021de8:	2084b03a 	or	r2,r4,r2
+ 8021dec:	10bfffcc 	andi	r2,r2,65535
+ 8021df0:	18800035 	stwio	r2,0(r3)
+   tse[iface].mac_addr[5] = 0xBA;
+
+#endif /* not ALT_INICHE */
+
+   /* status = UP */ 
+   nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_UP;    
+ 8021df4:	e0bff417 	ldw	r2,-48(fp)
+ 8021df8:	100690ba 	slli	r3,r2,2
+ 8021dfc:	008201b4 	movhi	r2,2054
+ 8021e00:	1885883a 	add	r2,r3,r2
+ 8021e04:	10b77017 	ldw	r2,-8768(r2)
+ 8021e08:	10802717 	ldw	r2,156(r2)
+ 8021e0c:	00c00044 	movi	r3,1
+ 8021e10:	10c00615 	stw	r3,24(r2)
+   nets[iface]->n_mib->ifOperStatus =  ALTERA_TSE_ADMIN_STATUS_UP;
+ 8021e14:	e0bff417 	ldw	r2,-48(fp)
+ 8021e18:	100690ba 	slli	r3,r2,2
+ 8021e1c:	008201b4 	movhi	r2,2054
+ 8021e20:	1885883a 	add	r2,r3,r2
+ 8021e24:	10b77017 	ldw	r2,-8768(r2)
+ 8021e28:	10802717 	ldw	r2,156(r2)
+ 8021e2c:	00c00044 	movi	r3,1
+ 8021e30:	10c00715 	stw	r3,28(r2)
+   
+   /* Install MSGDMA (RX) interrupt handler */
+   alt_msgdma_register_callback(
+ 8021e34:	e0bff417 	ldw	r2,-48(fp)
+ 8021e38:	10c02924 	muli	r3,r2,164
+ 8021e3c:	008201b4 	movhi	r2,2054
+ 8021e40:	1885883a 	add	r2,r3,r2
+ 8021e44:	1135c517 	ldw	r4,-10476(r2)
+        tse[iface].mi.rx_msgdma,
+        (alt_msgdma_callback)&tse_msgdmaRx_isr,
+        0,
+        (void*)(&tse[iface]));
+ 8021e48:	e0bff417 	ldw	r2,-48(fp)
+ 8021e4c:	10c02924 	muli	r3,r2,164
+ 8021e50:	008201b4 	movhi	r2,2054
+ 8021e54:	10b5c204 	addi	r2,r2,-10488
+ 8021e58:	1885883a 	add	r2,r3,r2
+   alt_msgdma_register_callback(
+ 8021e5c:	100f883a 	mov	r7,r2
+ 8021e60:	000d883a 	mov	r6,zero
+ 8021e64:	014200b4 	movhi	r5,2050
+ 8021e68:	29488404 	addi	r5,r5,8720
+ 8021e6c:	80200940 	call	8020094 <alt_msgdma_register_callback>
+        
+           /* Install MSGDMA (TX) interrupt handler */
+    alt_msgdma_register_callback(
+ 8021e70:	e0bff417 	ldw	r2,-48(fp)
+ 8021e74:	10c02924 	muli	r3,r2,164
+ 8021e78:	008201b4 	movhi	r2,2054
+ 8021e7c:	1885883a 	add	r2,r3,r2
+ 8021e80:	1135c417 	ldw	r4,-10480(r2)
+          tse[iface].mi.tx_msgdma,
+          (alt_msgdma_callback)&tse_msgdmaTx_isr,
+          0,
+          (void*)(&tse[iface]));
+ 8021e84:	e0bff417 	ldw	r2,-48(fp)
+ 8021e88:	10c02924 	muli	r3,r2,164
+ 8021e8c:	008201b4 	movhi	r2,2054
+ 8021e90:	10b5c204 	addi	r2,r2,-10488
+ 8021e94:	1885883a 	add	r2,r3,r2
+    alt_msgdma_register_callback(
+ 8021e98:	100f883a 	mov	r7,r2
+ 8021e9c:	000d883a 	mov	r6,zero
+ 8021ea0:	014200b4 	movhi	r5,2050
+ 8021ea4:	2948ea04 	addi	r5,r5,9128
+ 8021ea8:	80200940 	call	8020094 <alt_msgdma_register_callback>
+    
+  status = tse_msgdma_read_init(&tse[iface]);
+ 8021eac:	e0bff417 	ldw	r2,-48(fp)
+ 8021eb0:	10c02924 	muli	r3,r2,164
+ 8021eb4:	008201b4 	movhi	r2,2054
+ 8021eb8:	10b5c204 	addi	r2,r2,-10488
+ 8021ebc:	1885883a 	add	r2,r3,r2
+ 8021ec0:	1009883a 	mov	r4,r2
+ 8021ec4:	80224080 	call	8022408 <tse_msgdma_read_init>
+ 8021ec8:	e0bffd15 	stw	r2,-12(fp)
+  if (status == 0 ) status = tse_msgdma_write_init(&tse[iface],0,0);
+ 8021ecc:	e0bffd17 	ldw	r2,-12(fp)
+ 8021ed0:	10000a1e 	bne	r2,zero,8021efc <tse_mac_init+0xa38>
+ 8021ed4:	e0bff417 	ldw	r2,-48(fp)
+ 8021ed8:	10c02924 	muli	r3,r2,164
+ 8021edc:	008201b4 	movhi	r2,2054
+ 8021ee0:	10b5c204 	addi	r2,r2,-10488
+ 8021ee4:	1885883a 	add	r2,r3,r2
+ 8021ee8:	000d883a 	mov	r6,zero
+ 8021eec:	000b883a 	mov	r5,zero
+ 8021ef0:	1009883a 	mov	r4,r2
+ 8021ef4:	8021f280 	call	8021f28 <tse_msgdma_write_init>
+ 8021ef8:	e0bffd15 	stw	r2,-12(fp)
+  
+  if (status!=0) dprintf("TSE_MAC_INIT error\n");
+ 8021efc:	e0bffd17 	ldw	r2,-12(fp)
+ 8021f00:	10000326 	beq	r2,zero,8021f10 <tse_mac_init+0xa4c>
+ 8021f04:	01020174 	movhi	r4,2053
+ 8021f08:	21265904 	addi	r4,r4,-26268
+ 8021f0c:	8002d9c0 	call	8002d9c <puts>
+  
+  return status;
+ 8021f10:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8021f14:	e037883a 	mov	sp,fp
+ 8021f18:	dfc00117 	ldw	ra,4(sp)
+ 8021f1c:	df000017 	ldw	fp,0(sp)
+ 8021f20:	dec00204 	addi	sp,sp,8
+ 8021f24:	f800283a 	ret
+
+08021f28 <tse_msgdma_write_init>:
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success 
+ */
+int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len)
+{     
+ 8021f28:	defff704 	addi	sp,sp,-36
+ 8021f2c:	dfc00815 	stw	ra,32(sp)
+ 8021f30:	df000715 	stw	fp,28(sp)
+ 8021f34:	df000704 	addi	fp,sp,28
+ 8021f38:	e13ffc15 	stw	r4,-16(fp)
+ 8021f3c:	e17ffb15 	stw	r5,-20(fp)
+ 8021f40:	e1bffa15 	stw	r6,-24(fp)
+  alt_u32 control = 0;
+ 8021f44:	e03fff15 	stw	zero,-4(fp)
+  int desc_index;
+  int rc;
+  
+  tse_ptr->txdesc_list = NULL;
+ 8021f48:	e0bffc17 	ldw	r2,-16(fp)
+ 8021f4c:	10000d15 	stw	zero,52(r2)
+  
+  for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++)
+ 8021f50:	e03ffe15 	stw	zero,-8(fp)
+ 8021f54:	00003306 	br	8022024 <tse_msgdma_write_init+0xfc>
+  { 
+        
+    /* trigger interrupt when transfer complete */
+    control =  ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK; 
+ 8021f58:	0080c004 	movi	r2,768
+ 8021f5c:	e0bfff15 	stw	r2,-4(fp)
+            
+    if (desc_index >= ( ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE - 2)) control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK;
+ 8021f60:	e0bffe17 	ldw	r2,-8(fp)
+ 8021f64:	10000416 	blt	r2,zero,8021f78 <tse_msgdma_write_init+0x50>
+ 8021f68:	e0bfff17 	ldw	r2,-4(fp)
+ 8021f6c:	10900014 	ori	r2,r2,16384
+ 8021f70:	e0bfff15 	stw	r2,-4(fp)
+ 8021f74:	00000306 	br	8021f84 <tse_msgdma_write_init+0x5c>
+    else control  |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK;
+ 8021f78:	e0bfff17 	ldw	r2,-4(fp)
+ 8021f7c:	10804034 	orhi	r2,r2,256
+ 8021f80:	e0bfff15 	stw	r2,-4(fp)
+            
+    rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor(
+ 8021f84:	e0bffc17 	ldw	r2,-16(fp)
+ 8021f88:	11000217 	ldw	r4,8(r2)
+            tse_ptr->mi.tx_msgdma,
+            (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->txdesc[desc_index],  
+ 8021f8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8021f90:	10c00e17 	ldw	r3,56(r2)
+ 8021f94:	e0bffe17 	ldw	r2,-8(fp)
+ 8021f98:	1004917a 	slli	r2,r2,5
+    rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor(
+ 8021f9c:	1887883a 	add	r3,r3,r2
+ 8021fa0:	e17ffb17 	ldw	r5,-20(fp)
+ 8021fa4:	e0bfff17 	ldw	r2,-4(fp)
+ 8021fa8:	d8800015 	stw	r2,0(sp)
+ 8021fac:	e1fffa17 	ldw	r7,-24(fp)
+ 8021fb0:	280d883a 	mov	r6,r5
+ 8021fb4:	180b883a 	mov	r5,r3
+ 8021fb8:	801f2f80 	call	801f2f8 <alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor>
+ 8021fbc:	e0bffd15 	stw	r2,-12(fp)
+            (int)ActualData,   
+            len,
+            control);
+    if (rc!=0) return -1;
+ 8021fc0:	e0bffd17 	ldw	r2,-12(fp)
+ 8021fc4:	10000226 	beq	r2,zero,8021fd0 <tse_msgdma_write_init+0xa8>
+ 8021fc8:	00bfffc4 	movi	r2,-1
+ 8021fcc:	00001906 	br	8022034 <tse_msgdma_write_init+0x10c>
+    
+    if (desc_index==0) tse_ptr->txdesc_list = NULL; 
+ 8021fd0:	e0bffe17 	ldw	r2,-8(fp)
+ 8021fd4:	1000021e 	bne	r2,zero,8021fe0 <tse_msgdma_write_init+0xb8>
+ 8021fd8:	e0bffc17 	ldw	r2,-16(fp)
+ 8021fdc:	10000d15 	stw	zero,52(r2)
+            
+    rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+ 8021fe0:	e0bffc17 	ldw	r2,-16(fp)
+ 8021fe4:	11000d04 	addi	r4,r2,52
+               &tse_ptr->txdesc_list,
+               &tse_ptr->txdesc[desc_index] );        
+ 8021fe8:	e0bffc17 	ldw	r2,-16(fp)
+ 8021fec:	10c00e17 	ldw	r3,56(r2)
+ 8021ff0:	e0bffe17 	ldw	r2,-8(fp)
+ 8021ff4:	1004917a 	slli	r2,r2,5
+    rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+ 8021ff8:	1885883a 	add	r2,r3,r2
+ 8021ffc:	100b883a 	mov	r5,r2
+ 8022000:	801f5400 	call	801f540 <alt_msgdma_prefetcher_add_standard_desc_to_list>
+ 8022004:	e0bffd15 	stw	r2,-12(fp)
+    if (rc!=0) return -1;
+ 8022008:	e0bffd17 	ldw	r2,-12(fp)
+ 802200c:	10000226 	beq	r2,zero,8022018 <tse_msgdma_write_init+0xf0>
+ 8022010:	00bfffc4 	movi	r2,-1
+ 8022014:	00000706 	br	8022034 <tse_msgdma_write_init+0x10c>
+  for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++)
+ 8022018:	e0bffe17 	ldw	r2,-8(fp)
+ 802201c:	10800044 	addi	r2,r2,1
+ 8022020:	e0bffe15 	stw	r2,-8(fp)
+ 8022024:	e0bffe17 	ldw	r2,-8(fp)
+ 8022028:	10800090 	cmplti	r2,r2,2
+ 802202c:	103fca1e 	bne	r2,zero,8021f58 <tse_msgdma_write_init+0x30>
+
+  } 
+  
+  return 0;
+ 8022030:	0005883a 	mov	r2,zero
+}
+ 8022034:	e037883a 	mov	sp,fp
+ 8022038:	dfc00117 	ldw	ra,4(sp)
+ 802203c:	df000017 	ldw	fp,0(sp)
+ 8022040:	dec00204 	addi	sp,sp,8
+ 8022044:	f800283a 	ret
+
+08022048 <tse_mac_raw_send>:
+ * @param  data - pointer to the data payload
+ * @param  data_bytes - number of bytes of the data payload to be sent to the MAC
+ * @return SUCCESS if success, else a negative value
+ */
+int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes)
+{
+ 8022048:	defff104 	addi	sp,sp,-60
+ 802204c:	dfc00e15 	stw	ra,56(sp)
+ 8022050:	df000d15 	stw	fp,52(sp)
+ 8022054:	df000d04 	addi	fp,sp,52
+ 8022058:	e13ff515 	stw	r4,-44(fp)
+ 802205c:	e17ff415 	stw	r5,-48(fp)
+ 8022060:	e1bff315 	stw	r6,-52(fp)
+   unsigned int len = data_bytes;
+ 8022064:	e0bff317 	ldw	r2,-52(fp)
+ 8022068:	e0bfff15 	stw	r2,-4(fp)
+   int rc;
+
+   ins_tse_info* tse_ptr = (ins_tse_info*) net->n_local;
+ 802206c:	e0bff517 	ldw	r2,-44(fp)
+ 8022070:	10802817 	ldw	r2,160(r2)
+ 8022074:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_READ_STATUS (context);
+ 8022078:	0005303a 	rdctl	r2,status
+ 802207c:	e0bff915 	stw	r2,-28(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8022080:	e0fff917 	ldw	r3,-28(fp)
+ 8022084:	00bfff84 	movi	r2,-2
+ 8022088:	1884703a 	and	r2,r3,r2
+ 802208c:	1001703a 	wrctl	status,r2
+  return context;
+ 8022090:	e0bff917 	ldw	r2,-28(fp)
+   tse_mac_trans_info *mi;
+   unsigned int* ActualData;
+   int cpu_sr;
+   
+   OS_ENTER_CRITICAL();
+ 8022094:	e0bffd15 	stw	r2,-12(fp)
+   mi = &tse_ptr->mi;
+ 8022098:	e0bffe17 	ldw	r2,-8(fp)
+ 802209c:	10800104 	addi	r2,r2,4
+ 80220a0:	e0bffc15 	stw	r2,-16(fp)
+   
+   if(tse_ptr->sem!=0) /* Tx is busy*/
+ 80220a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80220a8:	10800b17 	ldw	r2,44(r2)
+ 80220ac:	10000926 	beq	r2,zero,80220d4 <tse_mac_raw_send+0x8c>
+   {
+      dprintf("raw_send CALLED AGAIN!!!\n");
+ 80220b0:	01020174 	movhi	r4,2053
+ 80220b4:	21265e04 	addi	r4,r4,-26248
+ 80220b8:	8002d9c0 	call	8002d9c <puts>
+ 80220bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80220c0:	e0bff815 	stw	r2,-32(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80220c4:	e0bff817 	ldw	r2,-32(fp)
+ 80220c8:	1001703a 	wrctl	status,r2
+      OS_EXIT_CRITICAL();
+      return ENP_RESOURCE;
+ 80220cc:	00bffa84 	movi	r2,-22
+ 80220d0:	00004a06 	br	80221fc <tse_mac_raw_send+0x1b4>
+   }
+ 
+   tse_ptr->sem = 1;  
+ 80220d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80220d8:	00c00044 	movi	r3,1
+ 80220dc:	10c00b15 	stw	r3,44(r2)
+   
+   // clear bit-31 before passing it to MSGDMA Driver
+   ActualData = (unsigned int*)alt_remap_cached ((volatile void*) data, 4);
+ 80220e0:	01400104 	movi	r5,4
+ 80220e4:	e13ff417 	ldw	r4,-48(fp)
+ 80220e8:	8037e880 	call	8037e88 <alt_remap_cached>
+ 80220ec:	e0bffb15 	stw	r2,-20(fp)
+     dprintf("tse_msgdma_write_init bad return\n");
+     OS_EXIT_CRITICAL();
+     return -1;
+   }
+   #else
+     tse_ptr->txdesc[0].read_address = (alt_u32)ActualData;
+ 80220f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80220f4:	10800e17 	ldw	r2,56(r2)
+ 80220f8:	e0fffb17 	ldw	r3,-20(fp)
+ 80220fc:	10c00015 	stw	r3,0(r2)
+     tse_ptr->txdesc[0].transfer_length = len;
+ 8022100:	e0bffe17 	ldw	r2,-8(fp)
+ 8022104:	10800e17 	ldw	r2,56(r2)
+ 8022108:	e0ffff17 	ldw	r3,-4(fp)
+ 802210c:	10c00215 	stw	r3,8(r2)
+     tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control
+ 8022110:	e0bffe17 	ldw	r2,-8(fp)
+ 8022114:	10800e17 	ldw	r2,56(r2)
+ 8022118:	10c00717 	ldw	r3,28(r2)
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 802211c:	00900034 	movhi	r2,16384
+ 8022120:	10bfffc4 	addi	r2,r2,-1
+ 8022124:	1886703a 	and	r3,r3,r2
+     tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control
+ 8022128:	e0bffe17 	ldw	r2,-8(fp)
+ 802212c:	10800e17 	ldw	r2,56(r2)
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+ 8022130:	18e00034 	orhi	r3,r3,32768
+     tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control
+ 8022134:	10c00715 	stw	r3,28(r2)
+   #endif  
+        
+   alt_dcache_flush(ActualData,len);   
+ 8022138:	e17fff17 	ldw	r5,-4(fp)
+ 802213c:	e13ffb17 	ldw	r4,-20(fp)
+ 8022140:	80371c00 	call	80371c0 <alt_dcache_flush>
+   rc = tse_mac_aTxWrite(mi,tse_ptr->txdesc);
+ 8022144:	e0bffe17 	ldw	r2,-8(fp)
+ 8022148:	10800e17 	ldw	r2,56(r2)
+ 802214c:	100b883a 	mov	r5,r2
+ 8022150:	e13ffc17 	ldw	r4,-16(fp)
+ 8022154:	8017ce80 	call	8017ce8 <tse_mac_aTxWrite>
+ 8022158:	e0bffa15 	stw	r2,-24(fp)
+   if(rc < 0)   /* MSGDMA not available */
+ 802215c:	e0bffa17 	ldw	r2,-24(fp)
+ 8022160:	1000120e 	bge	r2,zero,80221ac <tse_mac_raw_send+0x164>
+   {
+      dprintf("raw_send() MSGDMA not available, ret=%d, len=%d\n",rc, len);
+ 8022164:	e1bfff17 	ldw	r6,-4(fp)
+ 8022168:	e17ffa17 	ldw	r5,-24(fp)
+ 802216c:	01020174 	movhi	r4,2053
+ 8022170:	21266504 	addi	r4,r4,-26220
+ 8022174:	8002c780 	call	8002c78 <printf>
+      net->n_mib->ifOutDiscards++;
+ 8022178:	e0bff517 	ldw	r2,-44(fp)
+ 802217c:	10802717 	ldw	r2,156(r2)
+ 8022180:	10c01217 	ldw	r3,72(r2)
+ 8022184:	18c00044 	addi	r3,r3,1
+ 8022188:	10c01215 	stw	r3,72(r2)
+      tse_ptr->sem = 0;
+ 802218c:	e0bffe17 	ldw	r2,-8(fp)
+ 8022190:	10000b15 	stw	zero,44(r2)
+ 8022194:	e0bffd17 	ldw	r2,-12(fp)
+ 8022198:	e0bff715 	stw	r2,-36(fp)
+ 802219c:	e0bff717 	ldw	r2,-36(fp)
+ 80221a0:	1001703a 	wrctl	status,r2
+
+      OS_EXIT_CRITICAL();
+      return SEND_DROPPED;   /* ENP_RESOURCE and SEND_DROPPED have the same value! */
+ 80221a4:	00bffa84 	movi	r2,-22
+ 80221a8:	00001406 	br	80221fc <tse_mac_raw_send+0x1b4>
+   }
+   else   /* = 0, success */
+   {
+      net->n_mib->ifOutOctets += data_bytes;
+ 80221ac:	e0bff517 	ldw	r2,-44(fp)
+ 80221b0:	10802717 	ldw	r2,156(r2)
+ 80221b4:	11000f17 	ldw	r4,60(r2)
+ 80221b8:	e0bff517 	ldw	r2,-44(fp)
+ 80221bc:	10802717 	ldw	r2,156(r2)
+ 80221c0:	e0fff317 	ldw	r3,-52(fp)
+ 80221c4:	20c7883a 	add	r3,r4,r3
+ 80221c8:	10c00f15 	stw	r3,60(r2)
+      /* we dont know whether it was unicast or not, we count both in <ifOutUcastPkts> */
+      net->n_mib->ifOutUcastPkts++;
+ 80221cc:	e0bff517 	ldw	r2,-44(fp)
+ 80221d0:	10802717 	ldw	r2,156(r2)
+ 80221d4:	10c01017 	ldw	r3,64(r2)
+ 80221d8:	18c00044 	addi	r3,r3,1
+ 80221dc:	10c01015 	stw	r3,64(r2)
+      tse_ptr->sem = 0;
+ 80221e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80221e4:	10000b15 	stw	zero,44(r2)
+ 80221e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80221ec:	e0bff615 	stw	r2,-40(fp)
+ 80221f0:	e0bff617 	ldw	r2,-40(fp)
+ 80221f4:	1001703a 	wrctl	status,r2
+
+      OS_EXIT_CRITICAL();
+      return SUCCESS;  /*success */
+ 80221f8:	0005883a 	mov	r2,zero
+   }
+}
+ 80221fc:	e037883a 	mov	sp,fp
+ 8022200:	dfc00117 	ldw	ra,4(sp)
+ 8022204:	df000017 	ldw	fp,0(sp)
+ 8022208:	dec00204 	addi	sp,sp,8
+ 802220c:	f800283a 	ret
+
+08022210 <tse_msgdmaRx_isr>:
+ * @API TYPE - callback
+ * @param  context  - context of the TSE MAC instance
+ * @param  intnum - temporary storage
+ */
+void tse_msgdmaRx_isr(void * context)
+{
+ 8022210:	defff804 	addi	sp,sp,-32
+ 8022214:	dfc00715 	stw	ra,28(sp)
+ 8022218:	df000615 	stw	fp,24(sp)
+ 802221c:	df000604 	addi	fp,sp,24
+ 8022220:	e13ffa15 	stw	r4,-24(fp)
+    ins_tse_info* tse_ptr = (ins_tse_info *) context; 
+ 8022224:	e0bffa17 	ldw	r2,-24(fp)
+ 8022228:	e0bffe15 	stw	r2,-8(fp)
+    alt_u32 msgdma_status;
+    alt_u32 i,control;
+    
+    /* Capture current rcv queue length */
+    int initial_rcvdq_len = rcvdq.q_len;
+ 802222c:	008201b4 	movhi	r2,2054
+ 8022230:	10b6ad17 	ldw	r2,-9548(r2)
+ 8022234:	e0bffd15 	stw	r2,-12(fp)
+
+    /* reenable global interrupts so we don't miss one that occurs during the
+       processing of this ISR */
+    IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base,
+ 8022238:	e0bffe17 	ldw	r2,-8(fp)
+ 802223c:	10800317 	ldw	r2,12(r2)
+ 8022240:	10800617 	ldw	r2,24(r2)
+ 8022244:	e0fffe17 	ldw	r3,-8(fp)
+ 8022248:	18c00317 	ldw	r3,12(r3)
+ 802224c:	18c00617 	ldw	r3,24(r3)
+ 8022250:	18c00037 	ldwio	r3,0(r3)
+ 8022254:	18c00214 	ori	r3,r3,8
+ 8022258:	10c00035 	stwio	r3,0(r2)
+      			IORD_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base)
+	  			| ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK);
+       
+    msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.rx_msgdma->csr_base);
+ 802225c:	e0bffe17 	ldw	r2,-8(fp)
+ 8022260:	10800317 	ldw	r2,12(r2)
+ 8022264:	10800317 	ldw	r2,12(r2)
+ 8022268:	10800037 	ldwio	r2,0(r2)
+ 802226c:	e0bffc15 	stw	r2,-16(fp)
+       
+    if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)==0)
+ 8022270:	e0bffc17 	ldw	r2,-16(fp)
+ 8022274:	1080200c 	andi	r2,r2,128
+ 8022278:	1000421e 	bne	r2,zero,8022384 <tse_msgdmaRx_isr+0x174>
+    {   
+       /* Handle received packet */
+        tse_mac_rcv(tse_ptr); 
+ 802227c:	e13ffe17 	ldw	r4,-8(fp)
+ 8022280:	80227f80 	call	80227f8 <tse_mac_rcv>
+        
+        /* read the control field of the last descriptor in the chain */
+        control = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-2],0x1c);
+ 8022284:	e0bffe17 	ldw	r2,-8(fp)
+ 8022288:	10801317 	ldw	r2,76(r2)
+ 802228c:	e0fffe17 	ldw	r3,-8(fp)
+ 8022290:	10800444 	addi	r2,r2,17
+ 8022294:	100490ba 	slli	r2,r2,2
+ 8022298:	1885883a 	add	r2,r3,r2
+ 802229c:	10800017 	ldw	r2,0(r2)
+ 80222a0:	10803804 	addi	r2,r2,224
+ 80222a4:	10800704 	addi	r2,r2,28
+ 80222a8:	10800037 	ldwio	r2,0(r2)
+ 80222ac:	e0bffb15 	stw	r2,-20(fp)
+                          
+        //if the chain is completed then start a new chain
+        if ((control & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK)==0)            
+ 80222b0:	e0bffb17 	ldw	r2,-20(fp)
+ 80222b4:	1090002c 	andhi	r2,r2,16384
+ 80222b8:	10002a1e 	bne	r2,zero,8022364 <tse_msgdmaRx_isr+0x154>
+        {
+            /* process any unprocessed descriptors */      
+            for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+ 80222bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80222c0:	10801417 	ldw	r2,80(r2)
+ 80222c4:	e0bfff15 	stw	r2,-4(fp)
+ 80222c8:	00000506 	br	80222e0 <tse_msgdmaRx_isr+0xd0>
+            {
+                tse_mac_rcv(tse_ptr); 
+ 80222cc:	e13ffe17 	ldw	r4,-8(fp)
+ 80222d0:	80227f80 	call	80227f8 <tse_mac_rcv>
+            for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+ 80222d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80222d8:	10800044 	addi	r2,r2,1
+ 80222dc:	e0bfff15 	stw	r2,-4(fp)
+ 80222e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80222e4:	10800230 	cmpltui	r2,r2,8
+ 80222e8:	103ff81e 	bne	r2,zero,80222cc <tse_msgdmaRx_isr+0xbc>
+            }
+            
+            /* cancel any pending ints */
+            /* the chain could have been completed and int generated during the processing of this ISR */
+            /* But we are handling that in this ISR, so cancel any pending interrupt */
+            IOWR_ALT_MSGDMA_PREFETCHER_STATUS(tse_ptr->mi.rx_msgdma->prefetcher_base,1);
+ 80222ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80222f0:	10800317 	ldw	r2,12(r2)
+ 80222f4:	10800617 	ldw	r2,24(r2)
+ 80222f8:	10800404 	addi	r2,r2,16
+ 80222fc:	00c00044 	movi	r3,1
+ 8022300:	10c00035 	stwio	r3,0(r2)
+          
+            /* switch chains */
+            tse_ptr->rx_descriptor_index = 0;
+ 8022304:	e0bffe17 	ldw	r2,-8(fp)
+ 8022308:	10001415 	stw	zero,80(r2)
+            if (tse->rx_chain == 0) tse->rx_chain=1; else tse->rx_chain=0; 
+ 802230c:	008201b4 	movhi	r2,2054
+ 8022310:	10b5d517 	ldw	r2,-10412(r2)
+ 8022314:	1000041e 	bne	r2,zero,8022328 <tse_msgdmaRx_isr+0x118>
+ 8022318:	00c00044 	movi	r3,1
+ 802231c:	008201b4 	movhi	r2,2054
+ 8022320:	10f5d515 	stw	r3,-10412(r2)
+ 8022324:	00000206 	br	8022330 <tse_msgdmaRx_isr+0x120>
+ 8022328:	008201b4 	movhi	r2,2054
+ 802232c:	1035d515 	stw	zero,-10412(r2)
+                
+            /* start new chain */            
+            tse_mac_aRxRead(&tse_ptr->mi, tse_ptr->rxdesc_list[tse->rx_chain]);
+ 8022330:	e0bffe17 	ldw	r2,-8(fp)
+ 8022334:	11000104 	addi	r4,r2,4
+ 8022338:	008201b4 	movhi	r2,2054
+ 802233c:	10b5d517 	ldw	r2,-10412(r2)
+ 8022340:	e0fffe17 	ldw	r3,-8(fp)
+ 8022344:	108003c4 	addi	r2,r2,15
+ 8022348:	100490ba 	slli	r2,r2,2
+ 802234c:	1885883a 	add	r2,r3,r2
+ 8022350:	10800017 	ldw	r2,0(r2)
+ 8022354:	100b883a 	mov	r5,r2
+ 8022358:	8017c780 	call	8017c78 <tse_mac_aRxRead>
+            
+            /* allocate storage for the non active chain */
+            allocate_rx_descriptor_chain(tse_ptr); 
+ 802235c:	e13ffe17 	ldw	r4,-8(fp)
+ 8022360:	80226c00 	call	80226c0 <allocate_rx_descriptor_chain>
+        }    
+        
+        /* Wake up Niche stack if there are new packets are on queue */
+        if ((rcvdq.q_len) > initial_rcvdq_len) {
+ 8022364:	008201b4 	movhi	r2,2054
+ 8022368:	10b6ad17 	ldw	r2,-9548(r2)
+ 802236c:	e0fffd17 	ldw	r3,-12(fp)
+ 8022370:	1880070e 	bge	r3,r2,8022390 <tse_msgdmaRx_isr+0x180>
+            SignalPktDemux();
+ 8022374:	d0a08017 	ldw	r2,-32256(gp)
+ 8022378:	1009883a 	mov	r4,r2
+ 802237c:	8015d840 	call	8015d84 <OSSemPost>
+        }       
+    } /* if (no error) */
+    else {  dprintf("RX ERROR\n");  }
+    
+}
+ 8022380:	00000306 	br	8022390 <tse_msgdmaRx_isr+0x180>
+    else {  dprintf("RX ERROR\n");  }
+ 8022384:	01020174 	movhi	r4,2053
+ 8022388:	21267204 	addi	r4,r4,-26168
+ 802238c:	8002d9c0 	call	8002d9c <puts>
+}
+ 8022390:	0001883a 	nop
+ 8022394:	e037883a 	mov	sp,fp
+ 8022398:	dfc00117 	ldw	ra,4(sp)
+ 802239c:	df000017 	ldw	fp,0(sp)
+ 80223a0:	dec00204 	addi	sp,sp,8
+ 80223a4:	f800283a 	ret
+
+080223a8 <tse_msgdmaTx_isr>:
+ * 
+ * @API TYPE - callback
+ * @param  context  - context of the TSE MAC instance
+ */
+void tse_msgdmaTx_isr(void * context)
+{
+ 80223a8:	defffb04 	addi	sp,sp,-20
+ 80223ac:	dfc00415 	stw	ra,16(sp)
+ 80223b0:	df000315 	stw	fp,12(sp)
+ 80223b4:	df000304 	addi	fp,sp,12
+ 80223b8:	e13ffd15 	stw	r4,-12(fp)
+  ins_tse_info* tse_ptr = (ins_tse_info *) context; 
+ 80223bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80223c0:	e0bfff15 	stw	r2,-4(fp)
+   * IO read to peripheral that generated the IRQ is done after IO write
+   * to negate the interrupt request. This ensures at the IO write reaches 
+   * the peripheral (through any high-latency hardware in the system)
+   * before the ISR exits.
+   */   
+  msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.tx_msgdma->csr_base);
+ 80223c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80223c8:	10800217 	ldw	r2,8(r2)
+ 80223cc:	10800317 	ldw	r2,12(r2)
+ 80223d0:	10800037 	ldwio	r2,0(r2)
+ 80223d4:	e0bffe15 	stw	r2,-8(fp)
+  
+  if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)!=0)
+ 80223d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80223dc:	1080200c 	andi	r2,r2,128
+ 80223e0:	10000326 	beq	r2,zero,80223f0 <tse_msgdmaTx_isr+0x48>
+      dprintf("TX STOPPED\n");
+ 80223e4:	01020174 	movhi	r4,2053
+ 80223e8:	21267504 	addi	r4,r4,-26156
+ 80223ec:	8002d9c0 	call	8002d9c <puts>
+   
+}
+ 80223f0:	0001883a 	nop
+ 80223f4:	e037883a 	mov	sp,fp
+ 80223f8:	dfc00117 	ldw	ra,4(sp)
+ 80223fc:	df000017 	ldw	fp,0(sp)
+ 8022400:	dec00204 	addi	sp,sp,8
+ 8022404:	f800283a 	ret
+
+08022408 <tse_msgdma_read_init>:
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success 
+ */
+int tse_msgdma_read_init(ins_tse_info* tse_ptr)
+{     
+ 8022408:	defff604 	addi	sp,sp,-40
+ 802240c:	dfc00915 	stw	ra,36(sp)
+ 8022410:	df000815 	stw	fp,32(sp)
+ 8022414:	df000804 	addi	fp,sp,32
+ 8022418:	e13ff915 	stw	r4,-28(fp)
+  alt_u32 *uncached_packet_payload;
+  alt_u32 control = 0;
+ 802241c:	e03ffb15 	stw	zero,-20(fp)
+  int desc_index;
+  int chain_index;
+  int rc;
+  int max_transfer_size=0xffff;
+ 8022420:	00bfffd4 	movui	r2,65535
+ 8022424:	e0bffc15 	stw	r2,-16(fp)
+  
+  if  (tse_ptr->mi.rx_msgdma->max_byte < max_transfer_size) { max_transfer_size = tse_ptr->mi.rx_msgdma->max_byte; }
+ 8022428:	e0bff917 	ldw	r2,-28(fp)
+ 802242c:	10800317 	ldw	r2,12(r2)
+ 8022430:	10c01217 	ldw	r3,72(r2)
+ 8022434:	e0bffc17 	ldw	r2,-16(fp)
+ 8022438:	1880042e 	bgeu	r3,r2,802244c <tse_msgdma_read_init+0x44>
+ 802243c:	e0bff917 	ldw	r2,-28(fp)
+ 8022440:	10800317 	ldw	r2,12(r2)
+ 8022444:	10801217 	ldw	r2,72(r2)
+ 8022448:	e0bffc15 	stw	r2,-16(fp)
+   
+  for (chain_index=0;chain_index<2;chain_index++)
+ 802244c:	e03ffd15 	stw	zero,-12(fp)
+ 8022450:	00007f06 	br	8022650 <tse_msgdma_read_init+0x248>
+  { 
+    tse_ptr->rxdesc_list[chain_index] = NULL;
+ 8022454:	e0fff917 	ldw	r3,-28(fp)
+ 8022458:	e0bffd17 	ldw	r2,-12(fp)
+ 802245c:	108003c4 	addi	r2,r2,15
+ 8022460:	100490ba 	slli	r2,r2,2
+ 8022464:	1885883a 	add	r2,r3,r2
+ 8022468:	10000015 	stw	zero,0(r2)
+  
+    for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++)
+ 802246c:	e03ffe15 	stw	zero,-8(fp)
+ 8022470:	00007106 	br	8022638 <tse_msgdma_read_init+0x230>
+    { 
+      uncached_packet_payload = NULL;
+ 8022474:	e03fff15 	stw	zero,-4(fp)
+      
+      if ((desc_index < (ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1))) {  
+ 8022478:	e0bffe17 	ldw	r2,-8(fp)
+ 802247c:	10800208 	cmpgei	r2,r2,8
+ 8022480:	1000321e 	bne	r2,zero,802254c <tse_msgdma_read_init+0x144>
+        tse_ptr->pkt_array_rx[chain_index][desc_index] = pk_alloc(ALTERA_TSE_PKT_INIT_LEN);
+ 8022484:	01017e04 	movi	r4,1528
+ 8022488:	80284340 	call	8028434 <pk_alloc>
+ 802248c:	100b883a 	mov	r5,r2
+ 8022490:	e0fff917 	ldw	r3,-28(fp)
+ 8022494:	e0bffd17 	ldw	r2,-12(fp)
+ 8022498:	11000264 	muli	r4,r2,9
+ 802249c:	e0bffe17 	ldw	r2,-8(fp)
+ 80224a0:	2085883a 	add	r2,r4,r2
+ 80224a4:	10800584 	addi	r2,r2,22
+ 80224a8:	100490ba 	slli	r2,r2,2
+ 80224ac:	1885883a 	add	r2,r3,r2
+ 80224b0:	11400015 	stw	r5,0(r2)
+      
+        if (!tse_ptr->pkt_array_rx[chain_index][desc_index])   /* couldn't get a free buffer for rx */
+ 80224b4:	e0fff917 	ldw	r3,-28(fp)
+ 80224b8:	e0bffd17 	ldw	r2,-12(fp)
+ 80224bc:	11000264 	muli	r4,r2,9
+ 80224c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80224c4:	2085883a 	add	r2,r4,r2
+ 80224c8:	10800584 	addi	r2,r2,22
+ 80224cc:	100490ba 	slli	r2,r2,2
+ 80224d0:	1885883a 	add	r2,r3,r2
+ 80224d4:	10800017 	ldw	r2,0(r2)
+ 80224d8:	10000b1e 	bne	r2,zero,8022508 <tse_msgdma_read_init+0x100>
+        {
+          dprintf("[tse_msgdma_read_init] Fatal error: No free packet buffers for RX\n");
+ 80224dc:	01020174 	movhi	r4,2053
+ 80224e0:	21267804 	addi	r4,r4,-26144
+ 80224e4:	8002d9c0 	call	8002d9c <puts>
+          tse_ptr->netp->n_mib->ifInDiscards++;
+ 80224e8:	e0bff917 	ldw	r2,-28(fp)
+ 80224ec:	10800817 	ldw	r2,32(r2)
+ 80224f0:	10802717 	ldw	r2,156(r2)
+ 80224f4:	10c00c17 	ldw	r3,48(r2)
+ 80224f8:	18c00044 	addi	r3,r3,1
+ 80224fc:	10c00c15 	stw	r3,48(r2)
+        
+          return ENP_NOBUFFER;
+ 8022500:	00bffac4 	movi	r2,-21
+ 8022504:	00006906 	br	80226ac <tse_msgdma_read_init+0x2a4>
+        }
+      
+        // ensure bit-31 of tse_ptr->pkt_array_rx[desc_index]->nb_buff is clear before passing
+        // to MSGDMA Driver
+        uncached_packet_payload = (alt_u32 *)alt_remap_cached ((volatile void*) tse_ptr->pkt_array_rx[chain_index][desc_index]->nb_buff, 4);
+ 8022508:	e0fff917 	ldw	r3,-28(fp)
+ 802250c:	e0bffd17 	ldw	r2,-12(fp)
+ 8022510:	11000264 	muli	r4,r2,9
+ 8022514:	e0bffe17 	ldw	r2,-8(fp)
+ 8022518:	2085883a 	add	r2,r4,r2
+ 802251c:	10800584 	addi	r2,r2,22
+ 8022520:	100490ba 	slli	r2,r2,2
+ 8022524:	1885883a 	add	r2,r3,r2
+ 8022528:	10800017 	ldw	r2,0(r2)
+ 802252c:	10800117 	ldw	r2,4(r2)
+ 8022530:	01400104 	movi	r5,4
+ 8022534:	1009883a 	mov	r4,r2
+ 8022538:	8037e880 	call	8037e88 <alt_remap_cached>
+ 802253c:	e0bfff15 	stw	r2,-4(fp)
+        alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN);
+ 8022540:	01417e04 	movi	r5,1528
+ 8022544:	e13fff17 	ldw	r4,-4(fp)
+ 8022548:	80371c00 	call	80371c0 <alt_dcache_flush>
+      }
+   
+      /* trigger interrupt when transfer complete */
+      control =  ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK |
+ 802254c:	00803ff4 	movhi	r2,255
+ 8022550:	10940004 	addi	r2,r2,20480
+ 8022554:	e0bffb15 	stw	r2,-20(fp)
+            ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK; 
+            
+      rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor(
+ 8022558:	e0bff917 	ldw	r2,-28(fp)
+ 802255c:	11000317 	ldw	r4,12(r2)
+            tse_ptr->mi.rx_msgdma,
+            (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->rxdesc[chain_index][desc_index],  
+ 8022560:	e0fff917 	ldw	r3,-28(fp)
+ 8022564:	e0bffd17 	ldw	r2,-12(fp)
+ 8022568:	10800444 	addi	r2,r2,17
+ 802256c:	100490ba 	slli	r2,r2,2
+ 8022570:	1885883a 	add	r2,r3,r2
+ 8022574:	10c00017 	ldw	r3,0(r2)
+ 8022578:	e0bffe17 	ldw	r2,-8(fp)
+ 802257c:	1004917a 	slli	r2,r2,5
+      rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor(
+ 8022580:	1887883a 	add	r3,r3,r2
+ 8022584:	e17fff17 	ldw	r5,-4(fp)
+ 8022588:	e1bffc17 	ldw	r6,-16(fp)
+ 802258c:	e0bffb17 	ldw	r2,-20(fp)
+ 8022590:	d8800015 	stw	r2,0(sp)
+ 8022594:	300f883a 	mov	r7,r6
+ 8022598:	280d883a 	mov	r6,r5
+ 802259c:	180b883a 	mov	r5,r3
+ 80225a0:	801f2a00 	call	801f2a0 <alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor>
+ 80225a4:	e0bffa15 	stw	r2,-24(fp)
+            (alt_u32)uncached_packet_payload,   
+            max_transfer_size,
+            control);
+      if (rc!=0) return -1;
+ 80225a8:	e0bffa17 	ldw	r2,-24(fp)
+ 80225ac:	10000226 	beq	r2,zero,80225b8 <tse_msgdma_read_init+0x1b0>
+ 80225b0:	00bfffc4 	movi	r2,-1
+ 80225b4:	00003d06 	br	80226ac <tse_msgdma_read_init+0x2a4>
+      
+      if (desc_index==0) tse_ptr->rxdesc_list[chain_index] = NULL;  
+ 80225b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80225bc:	1000061e 	bne	r2,zero,80225d8 <tse_msgdma_read_init+0x1d0>
+ 80225c0:	e0fff917 	ldw	r3,-28(fp)
+ 80225c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80225c8:	108003c4 	addi	r2,r2,15
+ 80225cc:	100490ba 	slli	r2,r2,2
+ 80225d0:	1885883a 	add	r2,r3,r2
+ 80225d4:	10000015 	stw	zero,0(r2)
+            
+      rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+ 80225d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80225dc:	108003c4 	addi	r2,r2,15
+ 80225e0:	100490ba 	slli	r2,r2,2
+ 80225e4:	e0fff917 	ldw	r3,-28(fp)
+ 80225e8:	1889883a 	add	r4,r3,r2
+               &tse_ptr->rxdesc_list[chain_index],
+               &tse_ptr->rxdesc[chain_index][desc_index] );        
+ 80225ec:	e0fff917 	ldw	r3,-28(fp)
+ 80225f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80225f4:	10800444 	addi	r2,r2,17
+ 80225f8:	100490ba 	slli	r2,r2,2
+ 80225fc:	1885883a 	add	r2,r3,r2
+ 8022600:	10c00017 	ldw	r3,0(r2)
+ 8022604:	e0bffe17 	ldw	r2,-8(fp)
+ 8022608:	1004917a 	slli	r2,r2,5
+      rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+ 802260c:	1885883a 	add	r2,r3,r2
+ 8022610:	100b883a 	mov	r5,r2
+ 8022614:	801f5400 	call	801f540 <alt_msgdma_prefetcher_add_standard_desc_to_list>
+ 8022618:	e0bffa15 	stw	r2,-24(fp)
+      if (rc!=0) return -1;
+ 802261c:	e0bffa17 	ldw	r2,-24(fp)
+ 8022620:	10000226 	beq	r2,zero,802262c <tse_msgdma_read_init+0x224>
+ 8022624:	00bfffc4 	movi	r2,-1
+ 8022628:	00002006 	br	80226ac <tse_msgdma_read_init+0x2a4>
+    for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++)
+ 802262c:	e0bffe17 	ldw	r2,-8(fp)
+ 8022630:	10800044 	addi	r2,r2,1
+ 8022634:	e0bffe15 	stw	r2,-8(fp)
+ 8022638:	e0bffe17 	ldw	r2,-8(fp)
+ 802263c:	10800250 	cmplti	r2,r2,9
+ 8022640:	103f8c1e 	bne	r2,zero,8022474 <tse_msgdma_read_init+0x6c>
+  for (chain_index=0;chain_index<2;chain_index++)
+ 8022644:	e0bffd17 	ldw	r2,-12(fp)
+ 8022648:	10800044 	addi	r2,r2,1
+ 802264c:	e0bffd15 	stw	r2,-12(fp)
+ 8022650:	e0bffd17 	ldw	r2,-12(fp)
+ 8022654:	10800090 	cmplti	r2,r2,2
+ 8022658:	103f7e1e 	bne	r2,zero,8022454 <tse_msgdma_read_init+0x4c>
+    }
+
+  } 
+
+  dprintf("[tse_msgdma_read_init] RX descriptor chain desc (%d depth) created\n",  desc_index);
+ 802265c:	e17ffe17 	ldw	r5,-8(fp)
+ 8022660:	01020174 	movhi	r4,2053
+ 8022664:	21268904 	addi	r4,r4,-26076
+ 8022668:	8002c780 	call	8002c78 <printf>
+   
+  tse_ptr->rx_descriptor_index=0;   //for processing completed rx descriptors
+ 802266c:	e0bff917 	ldw	r2,-28(fp)
+ 8022670:	10001415 	stw	zero,80(r2)
+  tse_ptr->rx_chain=0;
+ 8022674:	e0bff917 	ldw	r2,-28(fp)
+ 8022678:	10001315 	stw	zero,76(r2)
+  tse_mac_aRxRead( &tse_ptr->mi, tse_ptr->rxdesc_list[tse_ptr->rx_chain]);
+ 802267c:	e0bff917 	ldw	r2,-28(fp)
+ 8022680:	11000104 	addi	r4,r2,4
+ 8022684:	e0bff917 	ldw	r2,-28(fp)
+ 8022688:	10801317 	ldw	r2,76(r2)
+ 802268c:	e0fff917 	ldw	r3,-28(fp)
+ 8022690:	108003c4 	addi	r2,r2,15
+ 8022694:	100490ba 	slli	r2,r2,2
+ 8022698:	1885883a 	add	r2,r3,r2
+ 802269c:	10800017 	ldw	r2,0(r2)
+ 80226a0:	100b883a 	mov	r5,r2
+ 80226a4:	8017c780 	call	8017c78 <tse_mac_aRxRead>
+  
+  return SUCCESS;
+ 80226a8:	0005883a 	mov	r2,zero
+}
+ 80226ac:	e037883a 	mov	sp,fp
+ 80226b0:	dfc00117 	ldw	ra,4(sp)
+ 80226b4:	df000017 	ldw	fp,0(sp)
+ 80226b8:	dec00204 	addi	sp,sp,8
+ 80226bc:	f800283a 	ret
+
+080226c0 <allocate_rx_descriptor_chain>:
+
+/* allocate the storage for the non active rx descriptor chain 
+   update the write pointers in each descriptor to point
+   to the allocated storage. */
+int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr)
+{
+ 80226c0:	defff904 	addi	sp,sp,-28
+ 80226c4:	dfc00615 	stw	ra,24(sp)
+ 80226c8:	df000515 	stw	fp,20(sp)
+ 80226cc:	df000504 	addi	fp,sp,20
+ 80226d0:	e13ffb15 	stw	r4,-20(fp)
+    PACKET replacement_pkt;
+    alt_u32 *uncached_packet_payload;
+    alt_msgdma_prefetcher_standard_descriptor *rxDesc;
+    int i;
+    
+    for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+ 80226d4:	e03fff15 	stw	zero,-4(fp)
+ 80226d8:	00003e06 	br	80227d4 <allocate_rx_descriptor_chain+0x114>
+    {
+        replacement_pkt = pk_alloc(ALTERA_TSE_PKT_INIT_LEN);
+ 80226dc:	01017e04 	movi	r4,1528
+ 80226e0:	80284340 	call	8028434 <pk_alloc>
+ 80226e4:	e0bffe15 	stw	r2,-8(fp)
+        if (!replacement_pkt) { /* couldn't get a free buffer for rx */
+ 80226e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80226ec:	1000051e 	bne	r2,zero,8022704 <allocate_rx_descriptor_chain+0x44>
+          dprintf("No free buffers for rx\n");
+ 80226f0:	01020174 	movhi	r4,2053
+ 80226f4:	21269a04 	addi	r4,r4,-26008
+ 80226f8:	8002d9c0 	call	8002d9c <puts>
+          return 1;
+ 80226fc:	00800044 	movi	r2,1
+ 8022700:	00003806 	br	80227e4 <allocate_rx_descriptor_chain+0x124>
+        }
+        else
+        {
+            rxDesc = &tse_ptr->rxdesc[!tse_ptr->rx_chain][i];
+ 8022704:	e0bffb17 	ldw	r2,-20(fp)
+ 8022708:	10801317 	ldw	r2,76(r2)
+ 802270c:	1005003a 	cmpeq	r2,r2,zero
+ 8022710:	10803fcc 	andi	r2,r2,255
+ 8022714:	e0fffb17 	ldw	r3,-20(fp)
+ 8022718:	10800444 	addi	r2,r2,17
+ 802271c:	100490ba 	slli	r2,r2,2
+ 8022720:	1885883a 	add	r2,r3,r2
+ 8022724:	10c00017 	ldw	r3,0(r2)
+ 8022728:	e0bfff17 	ldw	r2,-4(fp)
+ 802272c:	1004917a 	slli	r2,r2,5
+ 8022730:	1885883a 	add	r2,r3,r2
+ 8022734:	e0bffd15 	stw	r2,-12(fp)
+            tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i] = replacement_pkt;
+ 8022738:	e0bffb17 	ldw	r2,-20(fp)
+ 802273c:	10801317 	ldw	r2,76(r2)
+ 8022740:	1005003a 	cmpeq	r2,r2,zero
+ 8022744:	10803fcc 	andi	r2,r2,255
+ 8022748:	e0fffb17 	ldw	r3,-20(fp)
+ 802274c:	11000264 	muli	r4,r2,9
+ 8022750:	e0bfff17 	ldw	r2,-4(fp)
+ 8022754:	2085883a 	add	r2,r4,r2
+ 8022758:	10800584 	addi	r2,r2,22
+ 802275c:	100490ba 	slli	r2,r2,2
+ 8022760:	1885883a 	add	r2,r3,r2
+ 8022764:	e0fffe17 	ldw	r3,-8(fp)
+ 8022768:	10c00015 	stw	r3,0(r2)
+            uncached_packet_payload = (alt_u32 *)alt_remap_cached(tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i]->nb_buff, 4);
+ 802276c:	e0bffb17 	ldw	r2,-20(fp)
+ 8022770:	10801317 	ldw	r2,76(r2)
+ 8022774:	1005003a 	cmpeq	r2,r2,zero
+ 8022778:	10803fcc 	andi	r2,r2,255
+ 802277c:	e0fffb17 	ldw	r3,-20(fp)
+ 8022780:	11000264 	muli	r4,r2,9
+ 8022784:	e0bfff17 	ldw	r2,-4(fp)
+ 8022788:	2085883a 	add	r2,r4,r2
+ 802278c:	10800584 	addi	r2,r2,22
+ 8022790:	100490ba 	slli	r2,r2,2
+ 8022794:	1885883a 	add	r2,r3,r2
+ 8022798:	10800017 	ldw	r2,0(r2)
+ 802279c:	10800117 	ldw	r2,4(r2)
+ 80227a0:	01400104 	movi	r5,4
+ 80227a4:	1009883a 	mov	r4,r2
+ 80227a8:	8037e880 	call	8037e88 <alt_remap_cached>
+ 80227ac:	e0bffc15 	stw	r2,-16(fp)
+            alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN);
+ 80227b0:	01417e04 	movi	r5,1528
+ 80227b4:	e13ffc17 	ldw	r4,-16(fp)
+ 80227b8:	80371c00 	call	80371c0 <alt_dcache_flush>
+            rxDesc->write_address = (alt_u32)(uncached_packet_payload);
+ 80227bc:	e0fffc17 	ldw	r3,-16(fp)
+ 80227c0:	e0bffd17 	ldw	r2,-12(fp)
+ 80227c4:	10c00115 	stw	r3,4(r2)
+    for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+ 80227c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80227cc:	10800044 	addi	r2,r2,1
+ 80227d0:	e0bfff15 	stw	r2,-4(fp)
+ 80227d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80227d8:	10800210 	cmplti	r2,r2,8
+ 80227dc:	103fbf1e 	bne	r2,zero,80226dc <allocate_rx_descriptor_chain+0x1c>
+        }
+    } 
+    
+    return 0;
+ 80227e0:	0005883a 	mov	r2,zero
+}
+ 80227e4:	e037883a 	mov	sp,fp
+ 80227e8:	dfc00117 	ldw	ra,4(sp)
+ 80227ec:	df000017 	ldw	fp,0(sp)
+ 80227f0:	dec00204 	addi	sp,sp,8
+ 80227f4:	f800283a 	ret
+
+080227f8 <tse_mac_rcv>:
+ * @API TYPE        - callback internal function
+ * @return SUCCESS on success
+ */
+
+void tse_mac_rcv(ins_tse_info* tse_ptr)
+{     
+ 80227f8:	defffa04 	addi	sp,sp,-24
+ 80227fc:	dfc00515 	stw	ra,20(sp)
+ 8022800:	df000415 	stw	fp,16(sp)
+ 8022804:	df000404 	addi	fp,sp,16
+ 8022808:	e13ffc15 	stw	r4,-16(fp)
+    struct ethhdr * eth;
+    int pklen;
+    PACKET rx_packet;
+        
+    /* Correct frame length to actual (this is different from TX side) */
+    pklen = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index].bytes_transfered,0) - 2;  
+ 802280c:	e0bffc17 	ldw	r2,-16(fp)
+ 8022810:	10801317 	ldw	r2,76(r2)
+ 8022814:	e0fffc17 	ldw	r3,-16(fp)
+ 8022818:	10800444 	addi	r2,r2,17
+ 802281c:	100490ba 	slli	r2,r2,2
+ 8022820:	1885883a 	add	r2,r3,r2
+ 8022824:	10c00017 	ldw	r3,0(r2)
+ 8022828:	e0bffc17 	ldw	r2,-16(fp)
+ 802282c:	10801417 	ldw	r2,80(r2)
+ 8022830:	1004917a 	slli	r2,r2,5
+ 8022834:	1885883a 	add	r2,r3,r2
+ 8022838:	10800404 	addi	r2,r2,16
+ 802283c:	10800037 	ldwio	r2,0(r2)
+ 8022840:	10bfff84 	addi	r2,r2,-2
+ 8022844:	e0bfff15 	stw	r2,-4(fp)
+    
+    tse_ptr->netp->n_mib->ifInOctets += (u_long)pklen;
+ 8022848:	e0bffc17 	ldw	r2,-16(fp)
+ 802284c:	10800817 	ldw	r2,32(r2)
+ 8022850:	10802717 	ldw	r2,156(r2)
+ 8022854:	11000917 	ldw	r4,36(r2)
+ 8022858:	e0ffff17 	ldw	r3,-4(fp)
+ 802285c:	e0bffc17 	ldw	r2,-16(fp)
+ 8022860:	10800817 	ldw	r2,32(r2)
+ 8022864:	10802717 	ldw	r2,156(r2)
+ 8022868:	20c7883a 	add	r3,r4,r3
+ 802286c:	10c00915 	stw	r3,36(r2)
+    
+    rx_packet = tse_ptr->pkt_array_rx[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index];   
+ 8022870:	e0bffc17 	ldw	r2,-16(fp)
+ 8022874:	11001317 	ldw	r4,76(r2)
+ 8022878:	e0bffc17 	ldw	r2,-16(fp)
+ 802287c:	10801417 	ldw	r2,80(r2)
+ 8022880:	e0fffc17 	ldw	r3,-16(fp)
+ 8022884:	21000264 	muli	r4,r4,9
+ 8022888:	2085883a 	add	r2,r4,r2
+ 802288c:	10800584 	addi	r2,r2,22
+ 8022890:	100490ba 	slli	r2,r2,2
+ 8022894:	1885883a 	add	r2,r3,r2
+ 8022898:	10800017 	ldw	r2,0(r2)
+ 802289c:	e0bffe15 	stw	r2,-8(fp)
+    rx_packet->nb_prot = rx_packet->nb_buff + ETHHDR_SIZE;
+ 80228a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80228a4:	10800117 	ldw	r2,4(r2)
+ 80228a8:	10c00404 	addi	r3,r2,16
+ 80228ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80228b0:	10c00315 	stw	r3,12(r2)
+    rx_packet->nb_plen = pklen - 14;
+ 80228b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80228b8:	10bffc84 	addi	r2,r2,-14
+ 80228bc:	1007883a 	mov	r3,r2
+ 80228c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80228c4:	10c00415 	stw	r3,16(r2)
+    rx_packet->nb_tstamp = cticks;
+ 80228c8:	d0a07d17 	ldw	r2,-32268(gp)
+ 80228cc:	1007883a 	mov	r3,r2
+ 80228d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80228d4:	10c00515 	stw	r3,20(r2)
+    rx_packet->net = tse_ptr->netp;
+ 80228d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80228dc:	10c00817 	ldw	r3,32(r2)
+ 80228e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80228e4:	10c00615 	stw	r3,24(r2)
+    
+    // set packet type for demux routine
+    eth = (struct ethhdr *)(rx_packet->nb_buff + ETHHDR_BIAS);
+ 80228e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80228ec:	10800117 	ldw	r2,4(r2)
+ 80228f0:	10800084 	addi	r2,r2,2
+ 80228f4:	e0bffd15 	stw	r2,-12(fp)
+    rx_packet->type = eth->e_type;
+ 80228f8:	e0bffd17 	ldw	r2,-12(fp)
+ 80228fc:	10c0030b 	ldhu	r3,12(r2)
+ 8022900:	e0bffe17 	ldw	r2,-8(fp)
+ 8022904:	10c0080d 	sth	r3,32(r2)
+    
+    putq(&rcvdq, rx_packet);
+ 8022908:	e17ffe17 	ldw	r5,-8(fp)
+ 802290c:	010201b4 	movhi	r4,2054
+ 8022910:	2136ab04 	addi	r4,r4,-9556
+ 8022914:	80289900 	call	8028990 <putq>
+              
+    tse_ptr->rx_descriptor_index++; 
+ 8022918:	e0bffc17 	ldw	r2,-16(fp)
+ 802291c:	10801417 	ldw	r2,80(r2)
+ 8022920:	10c00044 	addi	r3,r2,1
+ 8022924:	e0bffc17 	ldw	r2,-16(fp)
+ 8022928:	10c01415 	stw	r3,80(r2)
+} 
+ 802292c:	0001883a 	nop
+ 8022930:	e037883a 	mov	sp,fp
+ 8022934:	dfc00117 	ldw	ra,4(sp)
+ 8022938:	df000017 	ldw	fp,0(sp)
+ 802293c:	dec00204 	addi	sp,sp,8
+ 8022940:	f800283a 	ret
+
+08022944 <tse_mac_stats>:
+
+int tse_mac_stats(void * pio, int iface)
+{
+ 8022944:	defffc04 	addi	sp,sp,-16
+ 8022948:	dfc00315 	stw	ra,12(sp)
+ 802294c:	df000215 	stw	fp,8(sp)
+ 8022950:	df000204 	addi	fp,sp,8
+ 8022954:	e13fff15 	stw	r4,-4(fp)
+ 8022958:	e17ffe15 	stw	r5,-8(fp)
+    ns_printf(pio, "tse_mac_stats(), stats will be added later!\n");
+ 802295c:	01420174 	movhi	r5,2053
+ 8022960:	2966a004 	addi	r5,r5,-25984
+ 8022964:	e13fff17 	ldw	r4,-4(fp)
+ 8022968:	80273900 	call	8027390 <ns_printf>
+    return SUCCESS;
+ 802296c:	0005883a 	mov	r2,zero
+}
+ 8022970:	e037883a 	mov	sp,fp
+ 8022974:	dfc00117 	ldw	ra,4(sp)
+ 8022978:	df000017 	ldw	fp,0(sp)
+ 802297c:	dec00204 	addi	sp,sp,8
+ 8022980:	f800283a 	ret
+
+08022984 <tse_mac_close>:
+ * @API TYPE - Public
+ * @param  iface    index of the NET interface associated with the TSE MAC.
+ * @return SUCCESS
+ */
+int tse_mac_close(int iface)
+{
+ 8022984:	defffc04 	addi	sp,sp,-16
+ 8022988:	dfc00315 	stw	ra,12(sp)
+ 802298c:	df000215 	stw	fp,8(sp)
+ 8022990:	df000204 	addi	fp,sp,8
+ 8022994:	e13ffe15 	stw	r4,-8(fp)
+    int state;
+     
+    /* status = down */
+    nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN;    
+ 8022998:	e0bffe17 	ldw	r2,-8(fp)
+ 802299c:	100690ba 	slli	r3,r2,2
+ 80229a0:	008201b4 	movhi	r2,2054
+ 80229a4:	1885883a 	add	r2,r3,r2
+ 80229a8:	10b77017 	ldw	r2,-8768(r2)
+ 80229ac:	10802717 	ldw	r2,156(r2)
+ 80229b0:	00c00084 	movi	r3,2
+ 80229b4:	10c00615 	stw	r3,24(r2)
+    
+    /* disable the interrupt in the OS*/
+    alt_msgdma_register_callback(tse[iface].mi.rx_msgdma, 0, 0, 0);
+ 80229b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80229bc:	10c02924 	muli	r3,r2,164
+ 80229c0:	008201b4 	movhi	r2,2054
+ 80229c4:	1885883a 	add	r2,r3,r2
+ 80229c8:	10b5c517 	ldw	r2,-10476(r2)
+ 80229cc:	000f883a 	mov	r7,zero
+ 80229d0:	000d883a 	mov	r6,zero
+ 80229d4:	000b883a 	mov	r5,zero
+ 80229d8:	1009883a 	mov	r4,r2
+ 80229dc:	80200940 	call	8020094 <alt_msgdma_register_callback>
+     
+    /* Disable Receive path on the device*/
+    state = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base);
+ 80229e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80229e4:	10c02924 	muli	r3,r2,164
+ 80229e8:	008201b4 	movhi	r2,2054
+ 80229ec:	1885883a 	add	r2,r3,r2
+ 80229f0:	10b5c317 	ldw	r2,-10484(r2)
+ 80229f4:	10800204 	addi	r2,r2,8
+ 80229f8:	10800037 	ldwio	r2,0(r2)
+ 80229fc:	e0bfff15 	stw	r2,-4(fp)
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,state & ~ALTERA_TSEMAC_CMD_RX_ENA_MSK); 
+ 8022a00:	e0bffe17 	ldw	r2,-8(fp)
+ 8022a04:	10c02924 	muli	r3,r2,164
+ 8022a08:	008201b4 	movhi	r2,2054
+ 8022a0c:	1885883a 	add	r2,r3,r2
+ 8022a10:	10b5c317 	ldw	r2,-10484(r2)
+ 8022a14:	10800204 	addi	r2,r2,8
+ 8022a18:	e13fff17 	ldw	r4,-4(fp)
+ 8022a1c:	00ffff44 	movi	r3,-3
+ 8022a20:	20c6703a 	and	r3,r4,r3
+ 8022a24:	10c00035 	stwio	r3,0(r2)
+    
+    /* status = down */                                     
+    nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN;     
+ 8022a28:	e0bffe17 	ldw	r2,-8(fp)
+ 8022a2c:	100690ba 	slli	r3,r2,2
+ 8022a30:	008201b4 	movhi	r2,2054
+ 8022a34:	1885883a 	add	r2,r3,r2
+ 8022a38:	10b77017 	ldw	r2,-8768(r2)
+ 8022a3c:	10802717 	ldw	r2,156(r2)
+ 8022a40:	00c00084 	movi	r3,2
+ 8022a44:	10c00715 	stw	r3,28(r2)
+    
+    return SUCCESS;
+ 8022a48:	0005883a 	mov	r2,zero
+}
+ 8022a4c:	e037883a 	mov	sp,fp
+ 8022a50:	dfc00117 	ldw	ra,4(sp)
+ 8022a54:	df000017 	ldw	fp,0(sp)
+ 8022a58:	dec00204 	addi	sp,sp,8
+ 8022a5c:	f800283a 	ret
+
+08022a60 <close>:
+ * (for files and device drivers) or the InterNiche soclose() function for
+ * sockets.
+ */
+ 
+int close (int fd)
+{
+ 8022a60:	defffd04 	addi	sp,sp,-12
+ 8022a64:	dfc00215 	stw	ra,8(sp)
+ 8022a68:	df000115 	stw	fp,4(sp)
+ 8022a6c:	df000104 	addi	fp,sp,4
+ 8022a70:	e13fff15 	stw	r4,-4(fp)
+  return (fd < ALT_MAX_FD) ? alt_close (fd) : t_socketclose ((long) fd);
+ 8022a74:	e0bfff17 	ldw	r2,-4(fp)
+ 8022a78:	10800408 	cmpgei	r2,r2,16
+ 8022a7c:	1000031e 	bne	r2,zero,8022a8c <close+0x2c>
+ 8022a80:	e13fff17 	ldw	r4,-4(fp)
+ 8022a84:	80370f00 	call	80370f0 <alt_close>
+ 8022a88:	00000206 	br	8022a94 <close+0x34>
+ 8022a8c:	e13fff17 	ldw	r4,-4(fp)
+ 8022a90:	802ce700 	call	802ce70 <t_socketclose>
+}
+ 8022a94:	e037883a 	mov	sp,fp
+ 8022a98:	dfc00117 	ldw	ra,4(sp)
+ 8022a9c:	df000017 	ldw	fp,0(sp)
+ 8022aa0:	dec00204 	addi	sp,sp,8
+ 8022aa4:	f800283a 	ret
+
+08022aa8 <iniche_devices_init>:
+ * total number of interfaces after initialization.
+ */
+
+int iniche_devices_init(
+    int                         if_count)
+{
+ 8022aa8:	defff504 	addi	sp,sp,-44
+ 8022aac:	dfc00a15 	stw	ra,40(sp)
+ 8022ab0:	df000915 	stw	fp,36(sp)
+ 8022ab4:	df000904 	addi	fp,sp,36
+ 8022ab8:	e13ff815 	stw	r4,-32(fp)
+                                netmask,
+                                gw;
+    int                         use_dhcp;
+
+    /* Get the InterNiche device list. */
+    p_dev = (alt_iniche_dev *) (alt_iniche_dev_list.next);
+ 8022abc:	d0a00f17 	ldw	r2,-32708(gp)
+ 8022ac0:	e0bfff15 	stw	r2,-4(fp)
+    p_dev_list_end = (alt_iniche_dev *) (&(alt_iniche_dev_list.next));
+ 8022ac4:	d0a00f04 	addi	r2,gp,-32708
+ 8022ac8:	e0bffe15 	stw	r2,-8(fp)
+
+    /* Initialize each InterNiche device. */
+    while (p_dev != p_dev_list_end)
+ 8022acc:	00003606 	br	8022ba8 <iniche_devices_init+0x100>
+    {
+        /* Initialize the InterNiche device data record. */
+        p_dev->p_driver_data = p_dev;
+ 8022ad0:	e0bfff17 	ldw	r2,-4(fp)
+ 8022ad4:	e0ffff17 	ldw	r3,-4(fp)
+ 8022ad8:	10c00415 	stw	r3,16(r2)
+        p_dev->if_num = if_count;
+ 8022adc:	e0bfff17 	ldw	r2,-4(fp)
+ 8022ae0:	e0fff817 	ldw	r3,-32(fp)
+ 8022ae4:	10c00515 	stw	r3,20(r2)
+        p_dev->p_net = nets[p_dev->if_num];
+ 8022ae8:	e0bfff17 	ldw	r2,-4(fp)
+ 8022aec:	10800517 	ldw	r2,20(r2)
+ 8022af0:	100690ba 	slli	r3,r2,2
+ 8022af4:	008201b4 	movhi	r2,2054
+ 8022af8:	1885883a 	add	r2,r3,r2
+ 8022afc:	10f77017 	ldw	r3,-8768(r2)
+ 8022b00:	e0bfff17 	ldw	r2,-4(fp)
+ 8022b04:	10c00615 	stw	r3,24(r2)
+
+        /* Perform device specific initialization. */
+        (*(p_dev->init_func))(p_dev);
+ 8022b08:	e0bfff17 	ldw	r2,-4(fp)
+ 8022b0c:	10800317 	ldw	r2,12(r2)
+ 8022b10:	e13fff17 	ldw	r4,-4(fp)
+ 8022b14:	103ee83a 	callr	r2
+
+        /* Get the interface IP address. */
+        p_net = p_dev->p_net;
+ 8022b18:	e0bfff17 	ldw	r2,-4(fp)
+ 8022b1c:	10800617 	ldw	r2,24(r2)
+ 8022b20:	e0bffd15 	stw	r2,-12(fp)
+                
+        if (get_ip_addr(p_dev, &ipaddr, &netmask, &gw, &use_dhcp))
+ 8022b24:	e17ffa04 	addi	r5,fp,-24
+ 8022b28:	e13ffb04 	addi	r4,fp,-20
+ 8022b2c:	e0fffc04 	addi	r3,fp,-16
+ 8022b30:	e0bff904 	addi	r2,fp,-28
+ 8022b34:	d8800015 	stw	r2,0(sp)
+ 8022b38:	280f883a 	mov	r7,r5
+ 8022b3c:	200d883a 	mov	r6,r4
+ 8022b40:	180b883a 	mov	r5,r3
+ 8022b44:	e13fff17 	ldw	r4,-4(fp)
+ 8022b48:	800123c0 	call	800123c <get_ip_addr>
+ 8022b4c:	10001026 	beq	r2,zero,8022b90 <iniche_devices_init+0xe8>
+             */
+            if (use_dhcp) {
+                p_net->n_flags |= NF_DHCPC;
+            }
+#endif
+            p_net->n_ipaddr = ipaddr;
+ 8022b50:	e0fffc17 	ldw	r3,-16(fp)
+ 8022b54:	e0bffd17 	ldw	r2,-12(fp)
+ 8022b58:	10c00a15 	stw	r3,40(r2)
+            p_net->snmask = netmask;
+ 8022b5c:	e0fffb17 	ldw	r3,-20(fp)
+ 8022b60:	e0bffd17 	ldw	r2,-12(fp)
+ 8022b64:	10c00c15 	stw	r3,48(r2)
+            p_net->n_defgw = gw;
+ 8022b68:	e0fffa17 	ldw	r3,-24(fp)
+ 8022b6c:	e0bffd17 	ldw	r2,-12(fp)
+ 8022b70:	10c00d15 	stw	r3,52(r2)
+#ifdef IP_MULTICAST
+	    p_net->n_mcastlist = mcastlist;
+ 8022b74:	e0fffd17 	ldw	r3,-12(fp)
+ 8022b78:	00820134 	movhi	r2,2052
+ 8022b7c:	10a28e04 	addi	r2,r2,-30152
+ 8022b80:	18802b15 	stw	r2,172(r3)
+#if defined (IGMP_V1) || defined (IGMP_V2)
+            p_net->igmp_oper_mode = IGMP_MODE_DEFAULT;
+ 8022b84:	e0bffd17 	ldw	r2,-12(fp)
+ 8022b88:	00c00084 	movi	r3,2
+ 8022b8c:	10c02f05 	stb	r3,188(r2)
+#endif  /* IGMPv1 or IGMPv2 */
+#endif  /* IP_MULTICAST */
+        }
+
+        /* Initialize next device. */
+        if_count++;
+ 8022b90:	e0bff817 	ldw	r2,-32(fp)
+ 8022b94:	10800044 	addi	r2,r2,1
+ 8022b98:	e0bff815 	stw	r2,-32(fp)
+        p_dev = (alt_iniche_dev *) p_dev->llist.next;
+ 8022b9c:	e0bfff17 	ldw	r2,-4(fp)
+ 8022ba0:	10800017 	ldw	r2,0(r2)
+ 8022ba4:	e0bfff15 	stw	r2,-4(fp)
+    while (p_dev != p_dev_list_end)
+ 8022ba8:	e0ffff17 	ldw	r3,-4(fp)
+ 8022bac:	e0bffe17 	ldw	r2,-8(fp)
+ 8022bb0:	18bfc71e 	bne	r3,r2,8022ad0 <iniche_devices_init+0x28>
+    }
+
+    return (if_count);
+ 8022bb4:	e0bff817 	ldw	r2,-32(fp)
+}
+ 8022bb8:	e037883a 	mov	sp,fp
+ 8022bbc:	dfc00117 	ldw	ra,4(sp)
+ 8022bc0:	df000017 	ldw	fp,0(sp)
+ 8022bc4:	dec00204 	addi	sp,sp,8
+ 8022bc8:	f800283a 	ret
+
+08022bcc <read>:
+ * (for files and device drivers) or the InterNiche recvfrom() function for
+ * sockets.
+ */
+
+int read (int fd, void *ptr, size_t len)
+{
+ 8022bcc:	defff904 	addi	sp,sp,-28
+ 8022bd0:	dfc00615 	stw	ra,24(sp)
+ 8022bd4:	df000515 	stw	fp,20(sp)
+ 8022bd8:	df000504 	addi	fp,sp,20
+ 8022bdc:	e13fff15 	stw	r4,-4(fp)
+ 8022be0:	e17ffe15 	stw	r5,-8(fp)
+ 8022be4:	e1bffd15 	stw	r6,-12(fp)
+  return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len)
+                           : recvfrom(fd, ptr, len, 0, NULL, NULL);
+ 8022be8:	e0bfff17 	ldw	r2,-4(fp)
+ 8022bec:	10800408 	cmpgei	r2,r2,16
+ 8022bf0:	1000051e 	bne	r2,zero,8022c08 <read+0x3c>
+  return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len)
+ 8022bf4:	e1bffd17 	ldw	r6,-12(fp)
+ 8022bf8:	e17ffe17 	ldw	r5,-8(fp)
+ 8022bfc:	e13fff17 	ldw	r4,-4(fp)
+ 8022c00:	8037d340 	call	8037d34 <alt_read>
+                           : recvfrom(fd, ptr, len, 0, NULL, NULL);
+ 8022c04:	00000806 	br	8022c28 <read+0x5c>
+ 8022c08:	e0bffd17 	ldw	r2,-12(fp)
+ 8022c0c:	d8000115 	stw	zero,4(sp)
+ 8022c10:	d8000015 	stw	zero,0(sp)
+ 8022c14:	000f883a 	mov	r7,zero
+ 8022c18:	100d883a 	mov	r6,r2
+ 8022c1c:	e17ffe17 	ldw	r5,-8(fp)
+ 8022c20:	e13fff17 	ldw	r4,-4(fp)
+ 8022c24:	80269300 	call	8026930 <bsd_recvfrom>
+}
+ 8022c28:	e037883a 	mov	sp,fp
+ 8022c2c:	dfc00117 	ldw	ra,4(sp)
+ 8022c30:	df000017 	ldw	fp,0(sp)
+ 8022c34:	dec00204 	addi	sp,sp,8
+ 8022c38:	f800283a 	ret
+
+08022c3c <write>:
+ * This implementation vectors requests to either the HAL alt_write() function 
+ * (for files and device drivers) or the InterNiche send() function for sockets.
+ */
+
+int write (int fd, const void *ptr, size_t len)
+{
+ 8022c3c:	defffb04 	addi	sp,sp,-20
+ 8022c40:	dfc00415 	stw	ra,16(sp)
+ 8022c44:	df000315 	stw	fp,12(sp)
+ 8022c48:	df000304 	addi	fp,sp,12
+ 8022c4c:	e13fff15 	stw	r4,-4(fp)
+ 8022c50:	e17ffe15 	stw	r5,-8(fp)
+ 8022c54:	e1bffd15 	stw	r6,-12(fp)
+  if (fd < ALT_MAX_FD)
+ 8022c58:	e0bfff17 	ldw	r2,-4(fp)
+ 8022c5c:	10800408 	cmpgei	r2,r2,16
+ 8022c60:	1000051e 	bne	r2,zero,8022c78 <write+0x3c>
+  {
+    return alt_write (fd, ptr, len);
+ 8022c64:	e1bffd17 	ldw	r6,-12(fp)
+ 8022c68:	e17ffe17 	ldw	r5,-8(fp)
+ 8022c6c:	e13fff17 	ldw	r4,-4(fp)
+ 8022c70:	803826c0 	call	803826c <alt_write>
+ 8022c74:	00000606 	br	8022c90 <write+0x54>
+  }
+  else
+  { 
+    return send (fd, (void*) ptr, len, 0);
+ 8022c78:	e0bffd17 	ldw	r2,-12(fp)
+ 8022c7c:	000f883a 	mov	r7,zero
+ 8022c80:	100d883a 	mov	r6,r2
+ 8022c84:	e17ffe17 	ldw	r5,-8(fp)
+ 8022c88:	e13fff17 	ldw	r4,-4(fp)
+ 8022c8c:	802cb9c0 	call	802cb9c <t_send>
+  }  
+}
+ 8022c90:	e037883a 	mov	sp,fp
+ 8022c94:	dfc00117 	ldw	ra,4(sp)
+ 8022c98:	df000017 	ldw	fp,0(sp)
+ 8022c9c:	dec00204 	addi	sp,sp,8
+ 8022ca0:	f800283a 	ret
+
+08022ca4 <etainit>:
+ * RETURNS: int               0 if OK, else nonzero
+ */
+
+int
+etainit(void)
+{
+ 8022ca4:	defffe04 	addi	sp,sp,-8
+ 8022ca8:	dfc00115 	stw	ra,4(sp)
+ 8022cac:	df000015 	stw	fp,0(sp)
+ 8022cb0:	d839883a 	mov	fp,sp
+   /* register ARP type with the Net Driver */
+   if (reg_type(ET_ARP) != 0)
+ 8022cb4:	01018204 	movi	r4,1544
+ 8022cb8:	80241c80 	call	80241c8 <reg_type>
+ 8022cbc:	10000526 	beq	r2,zero,8022cd4 <etainit+0x30>
+   {
+#ifdef NPDEBUG
+      dprintf("ARP: unable to register type with MAC Driver\n");
+ 8022cc0:	01020174 	movhi	r4,2053
+ 8022cc4:	2126ac04 	addi	r4,r4,-25936
+ 8022cc8:	8002d9c0 	call	8002d9c <puts>
+#endif
+      return (1);
+ 8022ccc:	00800044 	movi	r2,1
+ 8022cd0:	00000106 	br	8022cd8 <etainit+0x34>
+   }
+   return (0);
+ 8022cd4:	0005883a 	mov	r2,zero
+}
+ 8022cd8:	e037883a 	mov	sp,fp
+ 8022cdc:	dfc00117 	ldw	ra,4(sp)
+ 8022ce0:	df000017 	ldw	fp,0(sp)
+ 8022ce4:	dec00204 	addi	sp,sp,8
+ 8022ce8:	f800283a 	ret
+
+08022cec <et_send>:
+ * and MIB info in the packet header. 
+ */
+
+int
+et_send(PACKET pkt, struct arptabent *tp)
+{
+ 8022cec:	defff904 	addi	sp,sp,-28
+ 8022cf0:	dfc00615 	stw	ra,24(sp)
+ 8022cf4:	df000515 	stw	fp,20(sp)
+ 8022cf8:	df000504 	addi	fp,sp,20
+ 8022cfc:	e13ffc15 	stw	r4,-16(fp)
+ 8022d00:	e17ffb15 	stw	r5,-20(fp)
+   char *ethhdr;
+   IFMIB etif = pkt->net->n_mib;    /* mib info for this ethernet interface */
+ 8022d04:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d08:	10800617 	ldw	r2,24(r2)
+ 8022d0c:	10802717 	ldw	r2,156(r2)
+ 8022d10:	e0bffe15 	stw	r2,-8(fp)
+   int err;
+
+   tp->lasttime = cticks;
+ 8022d14:	d0e07d17 	ldw	r3,-32268(gp)
+ 8022d18:	e0bffb17 	ldw	r2,-20(fp)
+ 8022d1c:	10c00615 	stw	r3,24(r2)
+   pkt->nb_prot -= ETHHDR_SIZE;  /* prepare for prepending ethernet header */
+ 8022d20:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d24:	10800317 	ldw	r2,12(r2)
+ 8022d28:	10fffc04 	addi	r3,r2,-16
+ 8022d2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d30:	10c00315 	stw	r3,12(r2)
+   pkt->nb_plen += ETHHDR_SIZE;
+ 8022d34:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d38:	10800417 	ldw	r2,16(r2)
+ 8022d3c:	10c00404 	addi	r3,r2,16
+ 8022d40:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d44:	10c00415 	stw	r3,16(r2)
+   ethhdr = pkt->nb_prot + ETHHDR_BIAS;
+ 8022d48:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d4c:	10800317 	ldw	r2,12(r2)
+ 8022d50:	10800084 	addi	r2,r2,2
+ 8022d54:	e0bffd15 	stw	r2,-12(fp)
+      MEMMOVE(snap, snapdata, 6);
+      snap->type = ARPIP;
+   }
+#endif   /* IEEE_802_3 */
+
+   if (ethhdr < pkt->nb_buff)   /* sanity check pointer */
+ 8022d58:	e0bffc17 	ldw	r2,-16(fp)
+ 8022d5c:	10800117 	ldw	r2,4(r2)
+ 8022d60:	e0fffd17 	ldw	r3,-12(fp)
+ 8022d64:	1880032e 	bgeu	r3,r2,8022d74 <et_send+0x88>
+      panic("et_send: prepend");
+ 8022d68:	01020174 	movhi	r4,2053
+ 8022d6c:	2126b804 	addi	r4,r4,-25888
+ 8022d70:	80271780 	call	8027178 <panic>
+
+   MEMMOVE(ethhdr + ET_DSTOFF, tp->t_phy_addr, 6);  /* set pkt's MAC dst addr */
+ 8022d74:	e0bffb17 	ldw	r2,-20(fp)
+ 8022d78:	10800104 	addi	r2,r2,4
+ 8022d7c:	01800184 	movi	r6,6
+ 8022d80:	100b883a 	mov	r5,r2
+ 8022d84:	e13ffd17 	ldw	r4,-12(fp)
+ 8022d88:	80087b80 	call	80087b8 <memmove>
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);  /* MAC src */
+ 8022d8c:	e0bffd17 	ldw	r2,-12(fp)
+ 8022d90:	10c00184 	addi	r3,r2,6
+ 8022d94:	e0bffe17 	ldw	r2,-8(fp)
+ 8022d98:	10800517 	ldw	r2,20(r2)
+ 8022d9c:	01800184 	movi	r6,6
+ 8022da0:	100b883a 	mov	r5,r2
+ 8022da4:	1809883a 	mov	r4,r3
+ 8022da8:	80087b80 	call	80087b8 <memmove>
+
+   /* nice clean ethernet II header */
+   if ((tp->flags & (ET_ETH2|ET_SNAP)) != ET_SNAP)
+ 8022dac:	e0bffb17 	ldw	r2,-20(fp)
+ 8022db0:	1080070b 	ldhu	r2,28(r2)
+ 8022db4:	10bfffcc 	andi	r2,r2,65535
+ 8022db8:	108000cc 	andi	r2,r2,3
+ 8022dbc:	108000a0 	cmpeqi	r2,r2,2
+ 8022dc0:	1000041e 	bne	r2,zero,8022dd4 <et_send+0xe8>
+      ET_TYPE_SET(ethhdr, ntohs(ARPIP));
+ 8022dc4:	e0bffd17 	ldw	r2,-12(fp)
+ 8022dc8:	10800304 	addi	r2,r2,12
+ 8022dcc:	00c00204 	movi	r3,8
+ 8022dd0:	10c00005 	stb	r3,0(r2)
+ 8022dd4:	e0bffd17 	ldw	r2,-12(fp)
+ 8022dd8:	10800344 	addi	r2,r2,13
+ 8022ddc:	10000005 	stb	zero,0(r2)
+      ET_TYPE_SET(ethhdr, len8023);
+   }
+#endif   /* IEEE_802_3 */
+
+   /* if a packet oriented send exists, use it: */
+   if (pkt->net->pkt_send)
+ 8022de0:	e0bffc17 	ldw	r2,-16(fp)
+ 8022de4:	10800617 	ldw	r2,24(r2)
+ 8022de8:	10800417 	ldw	r2,16(r2)
+ 8022dec:	10000726 	beq	r2,zero,8022e0c <et_send+0x120>
+      err = pkt->net->pkt_send(pkt);   /* send packet to media */
+ 8022df0:	e0bffc17 	ldw	r2,-16(fp)
+ 8022df4:	10800617 	ldw	r2,24(r2)
+ 8022df8:	10800417 	ldw	r2,16(r2)
+ 8022dfc:	e13ffc17 	ldw	r4,-16(fp)
+ 8022e00:	103ee83a 	callr	r2
+ 8022e04:	e0bfff15 	stw	r2,-4(fp)
+ 8022e08:	00001206 	br	8022e54 <et_send+0x168>
+   else  /* else use older raw_send routine */
+   {
+      /* sent to media */
+      err = pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen);
+ 8022e0c:	e0bffc17 	ldw	r2,-16(fp)
+ 8022e10:	10800617 	ldw	r2,24(r2)
+ 8022e14:	10800317 	ldw	r2,12(r2)
+ 8022e18:	e0fffc17 	ldw	r3,-16(fp)
+ 8022e1c:	19000617 	ldw	r4,24(r3)
+ 8022e20:	e0fffc17 	ldw	r3,-16(fp)
+ 8022e24:	19400317 	ldw	r5,12(r3)
+ 8022e28:	e0fffc17 	ldw	r3,-16(fp)
+ 8022e2c:	18c00417 	ldw	r3,16(r3)
+ 8022e30:	180d883a 	mov	r6,r3
+ 8022e34:	103ee83a 	callr	r2
+ 8022e38:	e0bfff15 	stw	r2,-4(fp)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8022e3c:	01000084 	movi	r4,2
+ 8022e40:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);
+ 8022e44:	e13ffc17 	ldw	r4,-16(fp)
+ 8022e48:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8022e4c:	01000084 	movi	r4,2
+ 8022e50:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   }
+
+   return (err);
+ 8022e54:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8022e58:	e037883a 	mov	sp,fp
+ 8022e5c:	dfc00117 	ldw	ra,4(sp)
+ 8022e60:	df000017 	ldw	fp,0(sp)
+ 8022e64:	dec00204 	addi	sp,sp,8
+ 8022e68:	f800283a 	ret
+
+08022e6c <arp_free_pending>:
+ * and mark the entry "unused".
+ */
+
+void
+arp_free_pending(struct arptabent *entry)
+{
+ 8022e6c:	defffb04 	addi	sp,sp,-20
+ 8022e70:	dfc00415 	stw	ra,16(sp)
+ 8022e74:	df000315 	stw	fp,12(sp)
+ 8022e78:	df000304 	addi	fp,sp,12
+ 8022e7c:	e13ffd15 	stw	r4,-12(fp)
+   PACKET tmppkt;
+   PACKET nextpkt;
+
+   /* entry->pending has the linked list of all pending packets */
+   tmppkt = entry->pending;
+ 8022e80:	e0bffd17 	ldw	r2,-12(fp)
+ 8022e84:	10800417 	ldw	r2,16(r2)
+ 8022e88:	e0bfff15 	stw	r2,-4(fp)
+   entry->pending = (PACKET)NULL;
+ 8022e8c:	e0bffd17 	ldw	r2,-12(fp)
+ 8022e90:	10000415 	stw	zero,16(r2)
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8022e94:	01000084 	movi	r4,2
+ 8022e98:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* free all pending packets */
+   while (tmppkt)
+ 8022e9c:	00000906 	br	8022ec4 <arp_free_pending+0x58>
+   {
+      nextpkt = tmppkt->next;        /* save the next packet in list */
+ 8022ea0:	e0bfff17 	ldw	r2,-4(fp)
+ 8022ea4:	10800017 	ldw	r2,0(r2)
+ 8022ea8:	e0bffe15 	stw	r2,-8(fp)
+      tmppkt->next = (PACKET)NULL;
+ 8022eac:	e0bfff17 	ldw	r2,-4(fp)
+ 8022eb0:	10000015 	stw	zero,0(r2)
+      pk_free(tmppkt);               /* free current packet */
+ 8022eb4:	e13fff17 	ldw	r4,-4(fp)
+ 8022eb8:	80287480 	call	8028748 <pk_free>
+      tmppkt = nextpkt;              /* process the next packet */
+ 8022ebc:	e0bffe17 	ldw	r2,-8(fp)
+ 8022ec0:	e0bfff15 	stw	r2,-4(fp)
+   while (tmppkt)
+ 8022ec4:	e0bfff17 	ldw	r2,-4(fp)
+ 8022ec8:	103ff51e 	bne	r2,zero,8022ea0 <arp_free_pending+0x34>
+   }
+
+   entry->t_pro_addr = 0;     /* mark the entry "unused" */
+ 8022ecc:	e0bffd17 	ldw	r2,-12(fp)
+ 8022ed0:	10000015 	stw	zero,0(r2)
+
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8022ed4:	01000084 	movi	r4,2
+ 8022ed8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+}
+ 8022edc:	0001883a 	nop
+ 8022ee0:	e037883a 	mov	sp,fp
+ 8022ee4:	dfc00117 	ldw	ra,4(sp)
+ 8022ee8:	df000017 	ldw	fp,0(sp)
+ 8022eec:	dec00204 	addi	sp,sp,8
+ 8022ef0:	f800283a 	ret
+
+08022ef4 <arp_send_pending>:
+ * Clear the list (entry->pending) after sending the packets.
+ */
+
+void
+arp_send_pending(struct arptabent *entry)
+{
+ 8022ef4:	defffc04 	addi	sp,sp,-16
+ 8022ef8:	dfc00315 	stw	ra,12(sp)
+ 8022efc:	df000215 	stw	fp,8(sp)
+ 8022f00:	df000204 	addi	fp,sp,8
+ 8022f04:	e13ffe15 	stw	r4,-8(fp)
+   PACKET tmppkt = entry->pending;
+ 8022f08:	e0bffe17 	ldw	r2,-8(fp)
+ 8022f0c:	10800417 	ldw	r2,16(r2)
+ 8022f10:	e0bfff15 	stw	r2,-4(fp)
+
+   /* entry->pending has the linked list of all pending packets */
+
+   /* send all pending packets */
+   while ((tmppkt = entry->pending) != (PACKET)NULL)
+ 8022f14:	00000906 	br	8022f3c <arp_send_pending+0x48>
+   {
+      entry->pending = tmppkt->next;   /* unlink the next packet */
+ 8022f18:	e0bfff17 	ldw	r2,-4(fp)
+ 8022f1c:	10c00017 	ldw	r3,0(r2)
+ 8022f20:	e0bffe17 	ldw	r2,-8(fp)
+ 8022f24:	10c00415 	stw	r3,16(r2)
+      tmppkt->next = (PACKET)NULL;
+ 8022f28:	e0bfff17 	ldw	r2,-4(fp)
+ 8022f2c:	10000015 	stw	zero,0(r2)
+      et_send(tmppkt, entry);          /* try send again */
+ 8022f30:	e17ffe17 	ldw	r5,-8(fp)
+ 8022f34:	e13fff17 	ldw	r4,-4(fp)
+ 8022f38:	8022cec0 	call	8022cec <et_send>
+   while ((tmppkt = entry->pending) != (PACKET)NULL)
+ 8022f3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8022f40:	10800417 	ldw	r2,16(r2)
+ 8022f44:	e0bfff15 	stw	r2,-4(fp)
+ 8022f48:	e0bfff17 	ldw	r2,-4(fp)
+ 8022f4c:	103ff21e 	bne	r2,zero,8022f18 <arp_send_pending+0x24>
+   }
+}
+ 8022f50:	0001883a 	nop
+ 8022f54:	e037883a 	mov	sp,fp
+ 8022f58:	dfc00117 	ldw	ra,4(sp)
+ 8022f5c:	df000017 	ldw	fp,0(sp)
+ 8022f60:	dec00204 	addi	sp,sp,8
+ 8022f64:	f800283a 	ret
+
+08022f68 <send_arp>:
+ * timeout will eventually free packet. 
+ */
+
+int
+send_arp(PACKET pkt, ip_addr dest_ip)
+{
+ 8022f68:	defff404 	addi	sp,sp,-48
+ 8022f6c:	dfc00b15 	stw	ra,44(sp)
+ 8022f70:	df000a15 	stw	fp,40(sp)
+ 8022f74:	df000a04 	addi	fp,sp,40
+ 8022f78:	e13ff715 	stw	r4,-36(fp)
+ 8022f7c:	e17ff615 	stw	r5,-40(fp)
+   struct arptabent *   oldest;
+   char * ethhdr;
+   NET net = pkt->net;
+ 8022f80:	e0bff717 	ldw	r2,-36(fp)
+ 8022f84:	10800617 	ldw	r2,24(r2)
+ 8022f88:	e0bfff15 	stw	r2,-4(fp)
+   struct arp_hdr *  arphdr;
+   IFMIB etif = pkt->net->n_mib;    /* mib info for this ethernet interface */
+ 8022f8c:	e0bff717 	ldw	r2,-36(fp)
+ 8022f90:	10800617 	ldw	r2,24(r2)
+ 8022f94:	10802717 	ldw	r2,156(r2)
+ 8022f98:	e0bffe15 	stw	r2,-8(fp)
+   } dest_ip_ptr;
+#endif /* ETHMCAST */
+
+
+   /* If we are broadcasting or multicasting ... */
+   if ((dest_ip == 0xFFFFFFFF) ||  
+ 8022f9c:	e0bff617 	ldw	r2,-40(fp)
+ 8022fa0:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8022fa4:	1000191e 	bne	r2,zero,802300c <send_arp+0xa4>
+      ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask)))
+ 8022fa8:	e0bfff17 	ldw	r2,-4(fp)
+ 8022fac:	10800c17 	ldw	r2,48(r2)
+ 8022fb0:	0086303a 	nor	r3,zero,r2
+ 8022fb4:	e0bff617 	ldw	r2,-40(fp)
+ 8022fb8:	1886703a 	and	r3,r3,r2
+ 8022fbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8022fc0:	10800c17 	ldw	r2,48(r2)
+ 8022fc4:	0084303a 	nor	r2,zero,r2
+   if ((dest_ip == 0xFFFFFFFF) ||  
+ 8022fc8:	18801026 	beq	r3,r2,802300c <send_arp+0xa4>
+       || (IN_MULTICAST(ntohl(dest_ip)) ))
+ 8022fcc:	e0bff617 	ldw	r2,-40(fp)
+ 8022fd0:	1006d63a 	srli	r3,r2,24
+ 8022fd4:	e0bff617 	ldw	r2,-40(fp)
+ 8022fd8:	1004d23a 	srli	r2,r2,8
+ 8022fdc:	10bfc00c 	andi	r2,r2,65280
+ 8022fe0:	1886b03a 	or	r3,r3,r2
+ 8022fe4:	e0bff617 	ldw	r2,-40(fp)
+ 8022fe8:	1004923a 	slli	r2,r2,8
+ 8022fec:	10803fec 	andhi	r2,r2,255
+ 8022ff0:	1886b03a 	or	r3,r3,r2
+ 8022ff4:	e0bff617 	ldw	r2,-40(fp)
+ 8022ff8:	1004963a 	slli	r2,r2,24
+ 8022ffc:	1884b03a 	or	r2,r3,r2
+ 8023000:	10fc002c 	andhi	r3,r2,61440
+ 8023004:	00b80034 	movhi	r2,57344
+ 8023008:	1880391e 	bne	r3,r2,80230f0 <send_arp+0x188>
+      ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask))))
+
+#endif /* IP_MULTICAST */
+   {
+      /* get unused or oldest entry in table */
+      oldest = make_arp_entry(dest_ip, pkt->net);
+ 802300c:	e0bff717 	ldw	r2,-36(fp)
+ 8023010:	10800617 	ldw	r2,24(r2)
+ 8023014:	100b883a 	mov	r5,r2
+ 8023018:	e13ff617 	ldw	r4,-40(fp)
+ 802301c:	80235280 	call	8023528 <make_arp_entry>
+ 8023020:	e0bffc15 	stw	r2,-16(fp)
+
+      /* set MAC destination to ethernet broadcast (all FFs) */
+      MEMSET(oldest->t_phy_addr, 0xFF, 6);
+ 8023024:	e0bffc17 	ldw	r2,-16(fp)
+ 8023028:	10800104 	addi	r2,r2,4
+ 802302c:	01800184 	movi	r6,6
+ 8023030:	01403fc4 	movi	r5,255
+ 8023034:	1009883a 	mov	r4,r2
+ 8023038:	80088e40 	call	80088e4 <memset>
+#ifdef IP_MULTICAST
+      /* If n_mcastlist routine is defined in the net structure,
+         map IP mcast to Ether multicast  */
+
+#ifdef ETHMCAST
+      if ((pkt->net->n_mcastlist) && (IN_MULTICAST(ntohl(dest_ip))))
+ 802303c:	e0bff717 	ldw	r2,-36(fp)
+ 8023040:	10800617 	ldw	r2,24(r2)
+ 8023044:	10802b17 	ldw	r2,172(r2)
+ 8023048:	10002526 	beq	r2,zero,80230e0 <send_arp+0x178>
+ 802304c:	e0bff617 	ldw	r2,-40(fp)
+ 8023050:	1006d63a 	srli	r3,r2,24
+ 8023054:	e0bff617 	ldw	r2,-40(fp)
+ 8023058:	1004d23a 	srli	r2,r2,8
+ 802305c:	10bfc00c 	andi	r2,r2,65280
+ 8023060:	1886b03a 	or	r3,r3,r2
+ 8023064:	e0bff617 	ldw	r2,-40(fp)
+ 8023068:	1004923a 	slli	r2,r2,8
+ 802306c:	10803fec 	andhi	r2,r2,255
+ 8023070:	1886b03a 	or	r3,r3,r2
+ 8023074:	e0bff617 	ldw	r2,-40(fp)
+ 8023078:	1004963a 	slli	r2,r2,24
+ 802307c:	1884b03a 	or	r2,r3,r2
+ 8023080:	10fc002c 	andhi	r3,r2,61440
+ 8023084:	00b80034 	movhi	r2,57344
+ 8023088:	1880151e 	bne	r3,r2,80230e0 <send_arp+0x178>
+      {
+         /* If IP mcast to be mapped to Ethernet multicast */
+         dest_ip_ptr.l = dest_ip;
+ 802308c:	e0bff617 	ldw	r2,-40(fp)
+ 8023090:	e0bff815 	stw	r2,-32(fp)
+         oldest->t_phy_addr[0] = 0x01;
+ 8023094:	e0bffc17 	ldw	r2,-16(fp)
+ 8023098:	00c00044 	movi	r3,1
+ 802309c:	10c00105 	stb	r3,4(r2)
+         oldest->t_phy_addr[1] = 0x00;
+ 80230a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80230a4:	10000145 	stb	zero,5(r2)
+         oldest->t_phy_addr[2] = 0x5e;
+ 80230a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80230ac:	00c01784 	movi	r3,94
+ 80230b0:	10c00185 	stb	r3,6(r2)
+         oldest->t_phy_addr[3] = (u_char )(dest_ip_ptr.c[1] & 0x7f);
+ 80230b4:	e0bff843 	ldbu	r2,-31(fp)
+ 80230b8:	10801fcc 	andi	r2,r2,127
+ 80230bc:	1007883a 	mov	r3,r2
+ 80230c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80230c4:	10c001c5 	stb	r3,7(r2)
+         oldest->t_phy_addr[4] = (u_char )dest_ip_ptr.c[2];
+ 80230c8:	e0fff883 	ldbu	r3,-30(fp)
+ 80230cc:	e0bffc17 	ldw	r2,-16(fp)
+ 80230d0:	10c00205 	stb	r3,8(r2)
+         oldest->t_phy_addr[5] = (u_char )dest_ip_ptr.c[3];
+ 80230d4:	e0fff8c3 	ldbu	r3,-29(fp)
+ 80230d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80230dc:	10c00245 	stb	r3,9(r2)
+      }
+#endif /* ETHMCAST */
+#endif /* IP_MULTICAST */
+      return (et_send(pkt, oldest));
+ 80230e0:	e17ffc17 	ldw	r5,-16(fp)
+ 80230e4:	e13ff717 	ldw	r4,-36(fp)
+ 80230e8:	8022cec0 	call	8022cec <et_send>
+ 80230ec:	0000ae06 	br	80233a8 <send_arp+0x440>
+
+   /* If packet is addressed to this Ethernet interface, and
+    * it's not a loopback address, then don't send it on the wire. 
+    * Instead, free the packet and return ENP_NO_ROUTE  
+    */
+   if ((pkt->fhost == pkt->net->n_ipaddr) &&
+ 80230f0:	e0bff717 	ldw	r2,-36(fp)
+ 80230f4:	10c00717 	ldw	r3,28(r2)
+ 80230f8:	e0bff717 	ldw	r2,-36(fp)
+ 80230fc:	10800617 	ldw	r2,24(r2)
+ 8023100:	10800a17 	ldw	r2,40(r2)
+ 8023104:	18800d1e 	bne	r3,r2,802313c <send_arp+0x1d4>
+      ((pkt->fhost & htonl(0xFF000000)) != htonl(0x7F000000)))
+ 8023108:	e0bff717 	ldw	r2,-36(fp)
+ 802310c:	10800717 	ldw	r2,28(r2)
+ 8023110:	10803fcc 	andi	r2,r2,255
+   if ((pkt->fhost == pkt->net->n_ipaddr) &&
+ 8023114:	10801fe0 	cmpeqi	r2,r2,127
+ 8023118:	1000081e 	bne	r2,zero,802313c <send_arp+0x1d4>
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802311c:	01000084 	movi	r4,2
+ 8023120:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);
+ 8023124:	e13ff717 	ldw	r4,-36(fp)
+ 8023128:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802312c:	01000084 	movi	r4,2
+ 8023130:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_NO_ROUTE;
+ 8023134:	00bff7c4 	movi	r2,-33
+ 8023138:	00009b06 	br	80233a8 <send_arp+0x440>
+   }
+
+   /* not broadcasting, so get a packet for an ARP request */
+   LOCK_NET_RESOURCE(FREEQ_RESID); 
+ 802313c:	01000084 	movi	r4,2
+ 8023140:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   arppkt = pk_alloc(arpsize);
+ 8023144:	01000c04 	movi	r4,48
+ 8023148:	80284340 	call	8028434 <pk_alloc>
+ 802314c:	e0bffd15 	stw	r2,-12(fp)
+   if (!arppkt)
+ 8023150:	e0bffd17 	ldw	r2,-12(fp)
+ 8023154:	1000061e 	bne	r2,zero,8023170 <send_arp+0x208>
+   {
+      pk_free(pkt);
+ 8023158:	e13ff717 	ldw	r4,-36(fp)
+ 802315c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023160:	01000084 	movi	r4,2
+ 8023164:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_RESOURCE;
+ 8023168:	00bffa84 	movi	r2,-22
+ 802316c:	00008e06 	br	80233a8 <send_arp+0x440>
+   }
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023170:	01000084 	movi	r4,2
+ 8023174:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   arppkt->nb_prot = arppkt->nb_buff;
+ 8023178:	e0bffd17 	ldw	r2,-12(fp)
+ 802317c:	10c00117 	ldw	r3,4(r2)
+ 8023180:	e0bffd17 	ldw	r2,-12(fp)
+ 8023184:	10c00315 	stw	r3,12(r2)
+   arppkt->nb_plen = arpsize;
+ 8023188:	e0bffd17 	ldw	r2,-12(fp)
+ 802318c:	00c00c04 	movi	r3,48
+ 8023190:	10c00415 	stw	r3,16(r2)
+   arppkt->net = pkt->net;
+ 8023194:	e0bff717 	ldw	r2,-36(fp)
+ 8023198:	10c00617 	ldw	r3,24(r2)
+ 802319c:	e0bffd17 	ldw	r2,-12(fp)
+ 80231a0:	10c00615 	stw	r3,24(r2)
+
+   /* get unused or oldest entry in table */
+   oldest = make_arp_entry(dest_ip, pkt->net);
+ 80231a4:	e0bff717 	ldw	r2,-36(fp)
+ 80231a8:	10800617 	ldw	r2,24(r2)
+ 80231ac:	100b883a 	mov	r5,r2
+ 80231b0:	e13ff617 	ldw	r4,-40(fp)
+ 80231b4:	80235280 	call	8023528 <make_arp_entry>
+ 80231b8:	e0bffc15 	stw	r2,-16(fp)
+
+   oldest->pending = pkt;           /* packet is "pended", not pk_free()d */
+ 80231bc:	e0bffc17 	ldw	r2,-16(fp)
+ 80231c0:	e0fff717 	ldw	r3,-36(fp)
+ 80231c4:	10c00415 	stw	r3,16(r2)
+
+   /* build arp request packet */
+   ethhdr = arppkt->nb_buff + ETHHDR_BIAS;     /* ethernet header at start of buffer */
+ 80231c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80231cc:	10800117 	ldw	r2,4(r2)
+ 80231d0:	10800084 	addi	r2,r2,2
+ 80231d4:	e0bffb15 	stw	r2,-20(fp)
+   arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */
+ 80231d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80231dc:	10800117 	ldw	r2,4(r2)
+ 80231e0:	10800404 	addi	r2,r2,16
+ 80231e4:	e0bffa15 	stw	r2,-24(fp)
+
+#ifdef IEEE_802_3
+   arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   arphdr->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+ 80231e8:	e0bffa17 	ldw	r2,-24(fp)
+ 80231ec:	00c04004 	movi	r3,256
+ 80231f0:	10c0000d 	sth	r3,0(r2)
+#endif /* IEEE_802_3 */
+
+   arphdr->ar_pro = ARPIP;
+ 80231f4:	e0bffa17 	ldw	r2,-24(fp)
+ 80231f8:	00c00204 	movi	r3,8
+ 80231fc:	10c0008d 	sth	r3,2(r2)
+   arphdr->ar_hln = 6;
+ 8023200:	e0bffa17 	ldw	r2,-24(fp)
+ 8023204:	00c00184 	movi	r3,6
+ 8023208:	10c00105 	stb	r3,4(r2)
+   arphdr->ar_pln = 4;
+ 802320c:	e0bffa17 	ldw	r2,-24(fp)
+ 8023210:	00c00104 	movi	r3,4
+ 8023214:	10c00145 	stb	r3,5(r2)
+   arphdr->ar_op = ARREQ;
+ 8023218:	e0bffa17 	ldw	r2,-24(fp)
+ 802321c:	00c04004 	movi	r3,256
+ 8023220:	10c0018d 	sth	r3,6(r2)
+   arphdr->ar_tpa = dest_ip;        /* target's IP address */
+ 8023224:	e0bffa17 	ldw	r2,-24(fp)
+ 8023228:	e0fff617 	ldw	r3,-40(fp)
+ 802322c:	10c00715 	stw	r3,28(r2)
+   arphdr->ar_spa = pkt->net->n_ipaddr;   /* my IP address */
+ 8023230:	e0bff717 	ldw	r2,-36(fp)
+ 8023234:	10800617 	ldw	r2,24(r2)
+ 8023238:	10c00a17 	ldw	r3,40(r2)
+ 802323c:	e0bffa17 	ldw	r2,-24(fp)
+ 8023240:	10c00415 	stw	r3,16(r2)
+   MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6);
+ 8023244:	e0bffa17 	ldw	r2,-24(fp)
+ 8023248:	10c00204 	addi	r3,r2,8
+ 802324c:	e0bffe17 	ldw	r2,-8(fp)
+ 8023250:	10800517 	ldw	r2,20(r2)
+ 8023254:	01800184 	movi	r6,6
+ 8023258:	100b883a 	mov	r5,r2
+ 802325c:	1809883a 	mov	r4,r3
+ 8023260:	80087b80 	call	80087b8 <memmove>
+   MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6);     /* destination to broadcast (all FFs) */
+ 8023264:	01800184 	movi	r6,6
+ 8023268:	01403fc4 	movi	r5,255
+ 802326c:	e13ffb17 	ldw	r4,-20(fp)
+ 8023270:	80088e40 	call	80088e4 <memset>
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);
+ 8023274:	e0bffb17 	ldw	r2,-20(fp)
+ 8023278:	10c00184 	addi	r3,r2,6
+ 802327c:	e0bffe17 	ldw	r2,-8(fp)
+ 8023280:	10800517 	ldw	r2,20(r2)
+ 8023284:	01800184 	movi	r6,6
+ 8023288:	100b883a 	mov	r5,r2
+ 802328c:	1809883a 	mov	r4,r3
+ 8023290:	80087b80 	call	80087b8 <memmove>
+   ET_TYPE_SET(ethhdr, ntohs(ET_ARP));
+ 8023294:	e0bffb17 	ldw	r2,-20(fp)
+ 8023298:	10800304 	addi	r2,r2,12
+ 802329c:	00c00204 	movi	r3,8
+ 80232a0:	10c00005 	stb	r3,0(r2)
+ 80232a4:	e0bffb17 	ldw	r2,-20(fp)
+ 80232a8:	10800344 	addi	r2,r2,13
+ 80232ac:	00c00184 	movi	r3,6
+ 80232b0:	10c00005 	stb	r3,0(r2)
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+ 80232b4:	e0bffa17 	ldw	r2,-24(fp)
+ 80232b8:	e0bff915 	stw	r2,-28(fp)
+      MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6);
+ 80232bc:	e0bff917 	ldw	r2,-28(fp)
+ 80232c0:	10c00204 	addi	r3,r2,8
+ 80232c4:	e0bffa17 	ldw	r2,-24(fp)
+ 80232c8:	10800204 	addi	r2,r2,8
+ 80232cc:	01800184 	movi	r6,6
+ 80232d0:	100b883a 	mov	r5,r2
+ 80232d4:	1809883a 	mov	r4,r3
+ 80232d8:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4);
+ 80232dc:	e0bff917 	ldw	r2,-28(fp)
+ 80232e0:	10c00384 	addi	r3,r2,14
+ 80232e4:	e0bffa17 	ldw	r2,-24(fp)
+ 80232e8:	10800404 	addi	r2,r2,16
+ 80232ec:	01800104 	movi	r6,4
+ 80232f0:	100b883a 	mov	r5,r2
+ 80232f4:	1809883a 	mov	r4,r3
+ 80232f8:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6);
+ 80232fc:	e0bff917 	ldw	r2,-28(fp)
+ 8023300:	10c00484 	addi	r3,r2,18
+ 8023304:	e0bffa17 	ldw	r2,-24(fp)
+ 8023308:	10800504 	addi	r2,r2,20
+ 802330c:	01800184 	movi	r6,6
+ 8023310:	100b883a 	mov	r5,r2
+ 8023314:	1809883a 	mov	r4,r3
+ 8023318:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4);
+ 802331c:	e0bff917 	ldw	r2,-28(fp)
+ 8023320:	10c00604 	addi	r3,r2,24
+ 8023324:	e0bffa17 	ldw	r2,-24(fp)
+ 8023328:	10800704 	addi	r2,r2,28
+ 802332c:	01800104 	movi	r6,4
+ 8023330:	100b883a 	mov	r5,r2
+ 8023334:	1809883a 	mov	r4,r3
+ 8023338:	80087b80 	call	80087b8 <memmove>
+   }
+#endif   /* IEEE_802_3 */
+
+#ifndef IEEE_802_3_ONLY
+   /* send arp request - if a packet oriented send exists, use it: */
+   if (net->pkt_send)
+ 802333c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023340:	10800417 	ldw	r2,16(r2)
+ 8023344:	10000526 	beq	r2,zero,802335c <send_arp+0x3f4>
+      net->pkt_send(arppkt);  /* driver should free arppkt later */
+ 8023348:	e0bfff17 	ldw	r2,-4(fp)
+ 802334c:	10800417 	ldw	r2,16(r2)
+ 8023350:	e13ffd17 	ldw	r4,-12(fp)
+ 8023354:	103ee83a 	callr	r2
+ 8023358:	00000f06 	br	8023398 <send_arp+0x430>
+   else  /* use old raw send */
+   {
+      net->raw_send(arppkt->net, arppkt->nb_buff, arpsize);
+ 802335c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023360:	10800317 	ldw	r2,12(r2)
+ 8023364:	e0fffd17 	ldw	r3,-12(fp)
+ 8023368:	19000617 	ldw	r4,24(r3)
+ 802336c:	e0fffd17 	ldw	r3,-12(fp)
+ 8023370:	18c00117 	ldw	r3,4(r3)
+ 8023374:	01800c04 	movi	r6,48
+ 8023378:	180b883a 	mov	r5,r3
+ 802337c:	103ee83a 	callr	r2
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023380:	01000084 	movi	r4,2
+ 8023384:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(arppkt);
+ 8023388:	e13ffd17 	ldw	r4,-12(fp)
+ 802338c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023390:	01000084 	movi	r4,2
+ 8023394:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   }
+   arpReqsOut++;
+ 8023398:	d0a06117 	ldw	r2,-32380(gp)
+ 802339c:	10800044 	addi	r2,r2,1
+ 80233a0:	d0a06115 	stw	r2,-32380(gp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(arppkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif  /* IEEE_802_3_ONLY */
+   
+   return ENP_SEND_PENDING;
+ 80233a4:	00800044 	movi	r2,1
+}
+ 80233a8:	e037883a 	mov	sp,fp
+ 80233ac:	dfc00117 	ldw	ra,4(sp)
+ 80233b0:	df000017 	ldw	fp,0(sp)
+ 80233b4:	dec00204 	addi	sp,sp,8
+ 80233b8:	f800283a 	ret
+
+080233bc <find_oldest_arp>:
+ * Old entries are removed from the table.
+ */
+
+struct arptabent * 
+find_oldest_arp(ip_addr dest_ip)
+{
+ 80233bc:	defff804 	addi	sp,sp,-32
+ 80233c0:	dfc00715 	stw	ra,28(sp)
+ 80233c4:	df000615 	stw	fp,24(sp)
+ 80233c8:	df000604 	addi	fp,sp,24
+ 80233cc:	e13ffa15 	stw	r4,-24(fp)
+   struct arptabent *tp;
+   struct arptabent *exact  = (struct arptabent *)NULL;
+ 80233d0:	e03ffe15 	stw	zero,-8(fp)
+   struct arptabent *oldest = (struct arptabent *)NULL;
+ 80233d4:	e03ffd15 	stw	zero,-12(fp)
+   struct arptabent *empty  = (struct arptabent *)NULL;
+ 80233d8:	e03ffc15 	stw	zero,-16(fp)
+   unsigned long lticks = cticks;
+ 80233dc:	d0a07d17 	ldw	r2,-32268(gp)
+ 80233e0:	e0bffb15 	stw	r2,-20(fp)
+
+   /* find lru (or free) entry */
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 80233e4:	008201b4 	movhi	r2,2054
+ 80233e8:	10b66604 	addi	r2,r2,-9832
+ 80233ec:	e0bfff15 	stw	r2,-4(fp)
+ 80233f0:	00003b06 	br	80234e0 <find_oldest_arp+0x124>
+   {
+      /* age out old, pending entries */
+      if (tp->pending)
+ 80233f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80233f8:	10800417 	ldw	r2,16(r2)
+ 80233fc:	10000b26 	beq	r2,zero,802342c <find_oldest_arp+0x70>
+      {
+         /* purge if pending for more than one second */
+         if ((lticks - tp->createtime) > TPS)
+ 8023400:	e0bfff17 	ldw	r2,-4(fp)
+ 8023404:	10800517 	ldw	r2,20(r2)
+ 8023408:	e0fffb17 	ldw	r3,-20(fp)
+ 802340c:	1885c83a 	sub	r2,r3,r2
+ 8023410:	10801970 	cmpltui	r2,r2,101
+ 8023414:	1000171e 	bne	r2,zero,8023474 <find_oldest_arp+0xb8>
+         {
+            arp_free_pending(tp);   /* free pending packets */
+ 8023418:	e13fff17 	ldw	r4,-4(fp)
+ 802341c:	8022e6c0 	call	8022e6c <arp_free_pending>
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+ 8023420:	e0bfff17 	ldw	r2,-4(fp)
+ 8023424:	10000015 	stw	zero,0(r2)
+ 8023428:	00001206 	br	8023474 <find_oldest_arp+0xb8>
+         }
+      }
+      else if ((tp->t_pro_addr != 0) &&
+ 802342c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023430:	10800017 	ldw	r2,0(r2)
+ 8023434:	10000f26 	beq	r2,zero,8023474 <find_oldest_arp+0xb8>
+               ((int)(lticks - tp->createtime) >= arp_ageout) &&
+ 8023438:	e0bfff17 	ldw	r2,-4(fp)
+ 802343c:	10800517 	ldw	r2,20(r2)
+ 8023440:	e0fffb17 	ldw	r3,-20(fp)
+ 8023444:	1885c83a 	sub	r2,r3,r2
+ 8023448:	1007883a 	mov	r3,r2
+ 802344c:	d0a01117 	ldw	r2,-32700(gp)
+      else if ((tp->t_pro_addr != 0) &&
+ 8023450:	18800816 	blt	r3,r2,8023474 <find_oldest_arp+0xb8>
+               ((int)(lticks - tp->lasttime)   >= TPS))
+ 8023454:	e0bfff17 	ldw	r2,-4(fp)
+ 8023458:	10800617 	ldw	r2,24(r2)
+ 802345c:	e0fffb17 	ldw	r3,-20(fp)
+ 8023460:	1885c83a 	sub	r2,r3,r2
+               ((int)(lticks - tp->createtime) >= arp_ageout) &&
+ 8023464:	10801910 	cmplti	r2,r2,100
+ 8023468:	1000021e 	bne	r2,zero,8023474 <find_oldest_arp+0xb8>
+      {
+         /* entry has "expired" and has not been reference in 1 sec. */
+         tp->t_pro_addr = 0;     /* mark entry as "unused" */
+ 802346c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023470:	10000015 	stw	zero,0(r2)
+      }
+
+      if (tp->t_pro_addr == dest_ip)   /* ip addr already has entry */
+ 8023474:	e0bfff17 	ldw	r2,-4(fp)
+ 8023478:	10800017 	ldw	r2,0(r2)
+ 802347c:	e0fffa17 	ldw	r3,-24(fp)
+ 8023480:	1880031e 	bne	r3,r2,8023490 <find_oldest_arp+0xd4>
+      {
+         exact = tp;
+ 8023484:	e0bfff17 	ldw	r2,-4(fp)
+ 8023488:	e0bffe15 	stw	r2,-8(fp)
+ 802348c:	00001106 	br	80234d4 <find_oldest_arp+0x118>
+      }
+      else if (tp->t_pro_addr != 0)
+ 8023490:	e0bfff17 	ldw	r2,-4(fp)
+ 8023494:	10800017 	ldw	r2,0(r2)
+ 8023498:	10000a26 	beq	r2,zero,80234c4 <find_oldest_arp+0x108>
+      {
+         if (!oldest || (tp->lasttime < oldest->lasttime))
+ 802349c:	e0bffd17 	ldw	r2,-12(fp)
+ 80234a0:	10000526 	beq	r2,zero,80234b8 <find_oldest_arp+0xfc>
+ 80234a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80234a8:	10c00617 	ldw	r3,24(r2)
+ 80234ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80234b0:	10800617 	ldw	r2,24(r2)
+ 80234b4:	1880072e 	bgeu	r3,r2,80234d4 <find_oldest_arp+0x118>
+            oldest = tp;
+ 80234b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80234bc:	e0bffd15 	stw	r2,-12(fp)
+ 80234c0:	00000406 	br	80234d4 <find_oldest_arp+0x118>
+      }
+      else if (!empty)
+ 80234c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80234c8:	1000021e 	bne	r2,zero,80234d4 <find_oldest_arp+0x118>
+         empty = tp;          /* grab first empty slot */
+ 80234cc:	e0bfff17 	ldw	r2,-4(fp)
+ 80234d0:	e0bffc15 	stw	r2,-16(fp)
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 80234d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80234d8:	10800804 	addi	r2,r2,32
+ 80234dc:	e0bfff15 	stw	r2,-4(fp)
+ 80234e0:	e0ffff17 	ldw	r3,-4(fp)
+ 80234e4:	008201b4 	movhi	r2,2054
+ 80234e8:	10b6a604 	addi	r2,r2,-9576
+ 80234ec:	18bfc136 	bltu	r3,r2,80233f4 <find_oldest_arp+0x38>
+   }
+
+   return ((exact) ? exact : ((empty) ? empty : oldest));
+ 80234f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80234f4:	1000061e 	bne	r2,zero,8023510 <find_oldest_arp+0x154>
+ 80234f8:	e0bffc17 	ldw	r2,-16(fp)
+ 80234fc:	10000226 	beq	r2,zero,8023508 <find_oldest_arp+0x14c>
+ 8023500:	e0bffc17 	ldw	r2,-16(fp)
+ 8023504:	00000306 	br	8023514 <find_oldest_arp+0x158>
+ 8023508:	e0bffd17 	ldw	r2,-12(fp)
+ 802350c:	00000106 	br	8023514 <find_oldest_arp+0x158>
+ 8023510:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8023514:	e037883a 	mov	sp,fp
+ 8023518:	dfc00117 	ldw	ra,4(sp)
+ 802351c:	df000017 	ldw	fp,0(sp)
+ 8023520:	dec00204 	addi	sp,sp,8
+ 8023524:	f800283a 	ret
+
+08023528 <make_arp_entry>:
+ * active.
+ */
+
+struct arptabent *   
+make_arp_entry(ip_addr dest_ip, NET net)
+{
+ 8023528:	defffa04 	addi	sp,sp,-24
+ 802352c:	dfc00515 	stw	ra,20(sp)
+ 8023530:	df000415 	stw	fp,16(sp)
+ 8023534:	df000404 	addi	fp,sp,16
+ 8023538:	e13ffd15 	stw	r4,-12(fp)
+ 802353c:	e17ffc15 	stw	r5,-16(fp)
+   struct arptabent *oldest;
+   unsigned long lticks = cticks;
+ 8023540:	d0a07d17 	ldw	r2,-32268(gp)
+ 8023544:	e0bfff15 	stw	r2,-4(fp)
+
+   /* find usable (or existing) ARP table entry */
+   oldest = find_oldest_arp(dest_ip);
+ 8023548:	e13ffd17 	ldw	r4,-12(fp)
+ 802354c:	80233bc0 	call	80233bc <find_oldest_arp>
+ 8023550:	e0bffe15 	stw	r2,-8(fp)
+
+   /* If recycling entry, don't leak packets which may be stuck here */
+   if (oldest->pending && (oldest->t_pro_addr != dest_ip))
+ 8023554:	e0bffe17 	ldw	r2,-8(fp)
+ 8023558:	10800417 	ldw	r2,16(r2)
+ 802355c:	10000626 	beq	r2,zero,8023578 <make_arp_entry+0x50>
+ 8023560:	e0bffe17 	ldw	r2,-8(fp)
+ 8023564:	10800017 	ldw	r2,0(r2)
+ 8023568:	e0fffd17 	ldw	r3,-12(fp)
+ 802356c:	18800226 	beq	r3,r2,8023578 <make_arp_entry+0x50>
+   {
+      arp_free_pending(oldest);
+ 8023570:	e13ffe17 	ldw	r4,-8(fp)
+ 8023574:	8022e6c0 	call	8022e6c <arp_free_pending>
+   }
+
+   /* partially fill in arp entry */
+   oldest->t_pro_addr = dest_ip;
+ 8023578:	e0bffe17 	ldw	r2,-8(fp)
+ 802357c:	e0fffd17 	ldw	r3,-12(fp)
+ 8023580:	10c00015 	stw	r3,0(r2)
+   oldest->net = net;
+ 8023584:	e0bffe17 	ldw	r2,-8(fp)
+ 8023588:	e0fffc17 	ldw	r3,-16(fp)
+ 802358c:	10c00315 	stw	r3,12(r2)
+   oldest->flags = 0;
+ 8023590:	e0bffe17 	ldw	r2,-8(fp)
+ 8023594:	1000070d 	sth	zero,28(r2)
+   MEMSET(oldest->t_phy_addr, '\0', 6);   /* clear mac address */
+ 8023598:	e0bffe17 	ldw	r2,-8(fp)
+ 802359c:	10800104 	addi	r2,r2,4
+ 80235a0:	01800184 	movi	r6,6
+ 80235a4:	000b883a 	mov	r5,zero
+ 80235a8:	1009883a 	mov	r4,r2
+ 80235ac:	80088e40 	call	80088e4 <memset>
+   oldest->createtime = oldest->lasttime = lticks;
+ 80235b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80235b4:	e0ffff17 	ldw	r3,-4(fp)
+ 80235b8:	10c00615 	stw	r3,24(r2)
+ 80235bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80235c0:	10c00617 	ldw	r3,24(r2)
+ 80235c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80235c8:	10c00515 	stw	r3,20(r2)
+
+   /* start a ARP timer if there isn't one already */
+   /* update the timeout value if there is a timer */
+   /* time is specified in milliseconds */
+   if (arp_timer == 0)
+ 80235cc:	d0a05d17 	ldw	r2,-32396(gp)
+ 80235d0:	1000071e 	bne	r2,zero,80235f0 <make_arp_entry+0xc8>
+   {
+      arp_timer = in_timerset(&cb_arpent_tmo, ARPENT_TMO * 1000, 0);
+ 80235d4:	000d883a 	mov	r6,zero
+ 80235d8:	0149c404 	movi	r5,10000
+ 80235dc:	010200b4 	movhi	r4,2050
+ 80235e0:	210f3104 	addi	r4,r4,15556
+ 80235e4:	8038c740 	call	8038c74 <in_timerset>
+ 80235e8:	d0a05d15 	stw	r2,-32396(gp)
+ 80235ec:	00000706 	br	802360c <make_arp_entry+0xe4>
+   }
+   else
+   {
+      ((struct intimer *)arp_timer)->tmo =
+              ((struct intimer *)arp_timer)->interval + lticks;
+ 80235f0:	d0a05d17 	ldw	r2,-32396(gp)
+ 80235f4:	10c00217 	ldw	r3,8(r2)
+      ((struct intimer *)arp_timer)->tmo =
+ 80235f8:	d0a05d17 	ldw	r2,-32396(gp)
+ 80235fc:	1009883a 	mov	r4,r2
+              ((struct intimer *)arp_timer)->interval + lticks;
+ 8023600:	e0bfff17 	ldw	r2,-4(fp)
+ 8023604:	1885883a 	add	r2,r3,r2
+      ((struct intimer *)arp_timer)->tmo =
+ 8023608:	20800315 	stw	r2,12(r4)
+   }
+
+   return oldest;
+ 802360c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8023610:	e037883a 	mov	sp,fp
+ 8023614:	dfc00117 	ldw	ra,4(sp)
+ 8023618:	df000017 	ldw	fp,0(sp)
+ 802361c:	dec00204 	addi	sp,sp,8
+ 8023620:	f800283a 	ret
+
+08023624 <arpReply>:
+ * must be freed (or reused) herein. 
+ */
+
+void
+arpReply(PACKET pkt)
+{
+ 8023624:	defff704 	addi	sp,sp,-36
+ 8023628:	dfc00815 	stw	ra,32(sp)
+ 802362c:	df000715 	stw	fp,28(sp)
+ 8023630:	df000704 	addi	fp,sp,28
+ 8023634:	e13ff915 	stw	r4,-28(fp)
+   struct arp_hdr *in;
+   struct arp_hdr *out;
+   char *ethout;
+   char *ethin;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023638:	01000084 	movi	r4,2
+ 802363c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   outpkt = pk_alloc(arpsize);
+ 8023640:	01000c04 	movi	r4,48
+ 8023644:	80284340 	call	8028434 <pk_alloc>
+ 8023648:	e0bfff15 	stw	r2,-4(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802364c:	01000084 	movi	r4,2
+ 8023650:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (!outpkt)
+ 8023654:	e0bfff17 	ldw	r2,-4(fp)
+ 8023658:	1000021e 	bne	r2,zero,8023664 <arpReply+0x40>
+   {
+      dtrap();
+ 802365c:	8028cd40 	call	8028cd4 <dtrap>
+      return;
+ 8023660:	00009b06 	br	80238d0 <arpReply+0x2ac>
+   }
+
+   outpkt->net = pkt->net;    /* send back out the iface it came from */
+ 8023664:	e0bff917 	ldw	r2,-28(fp)
+ 8023668:	10c00617 	ldw	r3,24(r2)
+ 802366c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023670:	10c00615 	stw	r3,24(r2)
+
+   ethin = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS);
+ 8023674:	e0bff917 	ldw	r2,-28(fp)
+ 8023678:	10800317 	ldw	r2,12(r2)
+ 802367c:	10bffc84 	addi	r2,r2,-14
+ 8023680:	e0bffe15 	stw	r2,-8(fp)
+   ethout = outpkt->nb_buff + ETHHDR_BIAS;
+ 8023684:	e0bfff17 	ldw	r2,-4(fp)
+ 8023688:	10800117 	ldw	r2,4(r2)
+ 802368c:	10800084 	addi	r2,r2,2
+ 8023690:	e0bffd15 	stw	r2,-12(fp)
+      snap->type = ET_ARP;
+   }
+   else
+#endif   /* IEEE_802_3 */
+   {
+      ET_TYPE_SET(ethout, ntohs(ET_ARP));   /* 0x0806 - ARP type on ethernet */
+ 8023694:	e0bffd17 	ldw	r2,-12(fp)
+ 8023698:	10800304 	addi	r2,r2,12
+ 802369c:	00c00204 	movi	r3,8
+ 80236a0:	10c00005 	stb	r3,0(r2)
+ 80236a4:	e0bffd17 	ldw	r2,-12(fp)
+ 80236a8:	10800344 	addi	r2,r2,13
+ 80236ac:	00c00184 	movi	r3,6
+ 80236b0:	10c00005 	stb	r3,0(r2)
+      in = (struct arp_hdr *)(pkt->nb_prot);
+ 80236b4:	e0bff917 	ldw	r2,-28(fp)
+ 80236b8:	10800317 	ldw	r2,12(r2)
+ 80236bc:	e0bffc15 	stw	r2,-16(fp)
+      out = (struct arp_hdr *)(outpkt->nb_buff + ETHHDR_SIZE);
+ 80236c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80236c4:	10800117 	ldw	r2,4(r2)
+ 80236c8:	10800404 	addi	r2,r2,16
+ 80236cc:	e0bffb15 	stw	r2,-20(fp)
+      outpkt->nb_plen = arpsize;
+ 80236d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80236d4:	00c00c04 	movi	r3,48
+ 80236d8:	10c00415 	stw	r3,16(r2)
+
+   /* prepare outgoing arp packet */
+#ifdef IEEE_802_3
+   out->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   out->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+ 80236dc:	e0bffb17 	ldw	r2,-20(fp)
+ 80236e0:	00c04004 	movi	r3,256
+ 80236e4:	10c0000d 	sth	r3,0(r2)
+#endif /* IEEE_802_3 */
+
+   out->ar_pro = ARPIP;
+ 80236e8:	e0bffb17 	ldw	r2,-20(fp)
+ 80236ec:	00c00204 	movi	r3,8
+ 80236f0:	10c0008d 	sth	r3,2(r2)
+   out->ar_hln = 6;
+ 80236f4:	e0bffb17 	ldw	r2,-20(fp)
+ 80236f8:	00c00184 	movi	r3,6
+ 80236fc:	10c00105 	stb	r3,4(r2)
+   out->ar_pln = 4;
+ 8023700:	e0bffb17 	ldw	r2,-20(fp)
+ 8023704:	00c00104 	movi	r3,4
+ 8023708:	10c00145 	stb	r3,5(r2)
+   out->ar_op = ARREP;
+ 802370c:	e0bffb17 	ldw	r2,-20(fp)
+ 8023710:	00c08004 	movi	r3,512
+ 8023714:	10c0018d 	sth	r3,6(r2)
+   out->ar_tpa = in->ar_spa;     /* swap IP addresses */
+ 8023718:	e0bffc17 	ldw	r2,-16(fp)
+ 802371c:	10c00417 	ldw	r3,16(r2)
+ 8023720:	e0bffb17 	ldw	r2,-20(fp)
+ 8023724:	10c00715 	stw	r3,28(r2)
+   out->ar_spa = in->ar_tpa;
+ 8023728:	e0bffc17 	ldw	r2,-16(fp)
+ 802372c:	10c00717 	ldw	r3,28(r2)
+ 8023730:	e0bffb17 	ldw	r2,-20(fp)
+ 8023734:	10c00415 	stw	r3,16(r2)
+   MEMMOVE(out->ar_tha, in->ar_sha, 6);    /* move his MAC address */
+ 8023738:	e0bffb17 	ldw	r2,-20(fp)
+ 802373c:	10c00504 	addi	r3,r2,20
+ 8023740:	e0bffc17 	ldw	r2,-16(fp)
+ 8023744:	10800204 	addi	r2,r2,8
+ 8023748:	01800184 	movi	r6,6
+ 802374c:	100b883a 	mov	r5,r2
+ 8023750:	1809883a 	mov	r4,r3
+ 8023754:	80087b80 	call	80087b8 <memmove>
+   MEMMOVE(out->ar_sha, outpkt->net->n_mib->ifPhysAddress, 6);  /* fill in our mac address */
+ 8023758:	e0bffb17 	ldw	r2,-20(fp)
+ 802375c:	10c00204 	addi	r3,r2,8
+ 8023760:	e0bfff17 	ldw	r2,-4(fp)
+ 8023764:	10800617 	ldw	r2,24(r2)
+ 8023768:	10802717 	ldw	r2,156(r2)
+ 802376c:	10800517 	ldw	r2,20(r2)
+ 8023770:	01800184 	movi	r6,6
+ 8023774:	100b883a 	mov	r5,r2
+ 8023778:	1809883a 	mov	r4,r3
+ 802377c:	80087b80 	call	80087b8 <memmove>
+
+   /* prepend ethernet unicast header to arp reply */
+   MEMMOVE(ethout + ET_DSTOFF, ethin + ET_SRCOFF, 6);
+ 8023780:	e0bffe17 	ldw	r2,-8(fp)
+ 8023784:	10800184 	addi	r2,r2,6
+ 8023788:	01800184 	movi	r6,6
+ 802378c:	100b883a 	mov	r5,r2
+ 8023790:	e13ffd17 	ldw	r4,-12(fp)
+ 8023794:	80087b80 	call	80087b8 <memmove>
+   MEMMOVE(ethout + ET_SRCOFF, outpkt->net->n_mib->ifPhysAddress, 6);
+ 8023798:	e0bffd17 	ldw	r2,-12(fp)
+ 802379c:	10c00184 	addi	r3,r2,6
+ 80237a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80237a4:	10800617 	ldw	r2,24(r2)
+ 80237a8:	10802717 	ldw	r2,156(r2)
+ 80237ac:	10800517 	ldw	r2,20(r2)
+ 80237b0:	01800184 	movi	r6,6
+ 80237b4:	100b883a 	mov	r5,r2
+ 80237b8:	1809883a 	mov	r4,r3
+ 80237bc:	80087b80 	call	80087b8 <memmove>
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)out;
+ 80237c0:	e0bffb17 	ldw	r2,-20(fp)
+ 80237c4:	e0bffa15 	stw	r2,-24(fp)
+      MEMMOVE(&arwp->data[AR_SHA], out->ar_sha, 6);
+ 80237c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80237cc:	10c00204 	addi	r3,r2,8
+ 80237d0:	e0bffb17 	ldw	r2,-20(fp)
+ 80237d4:	10800204 	addi	r2,r2,8
+ 80237d8:	01800184 	movi	r6,6
+ 80237dc:	100b883a 	mov	r5,r2
+ 80237e0:	1809883a 	mov	r4,r3
+ 80237e4:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_SPA], &out->ar_spa, 4);
+ 80237e8:	e0bffa17 	ldw	r2,-24(fp)
+ 80237ec:	10c00384 	addi	r3,r2,14
+ 80237f0:	e0bffb17 	ldw	r2,-20(fp)
+ 80237f4:	10800404 	addi	r2,r2,16
+ 80237f8:	01800104 	movi	r6,4
+ 80237fc:	100b883a 	mov	r5,r2
+ 8023800:	1809883a 	mov	r4,r3
+ 8023804:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_THA], out->ar_tha, 6);
+ 8023808:	e0bffa17 	ldw	r2,-24(fp)
+ 802380c:	10c00484 	addi	r3,r2,18
+ 8023810:	e0bffb17 	ldw	r2,-20(fp)
+ 8023814:	10800504 	addi	r2,r2,20
+ 8023818:	01800184 	movi	r6,6
+ 802381c:	100b883a 	mov	r5,r2
+ 8023820:	1809883a 	mov	r4,r3
+ 8023824:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_TPA], &out->ar_tpa, 4);
+ 8023828:	e0bffa17 	ldw	r2,-24(fp)
+ 802382c:	10c00604 	addi	r3,r2,24
+ 8023830:	e0bffb17 	ldw	r2,-20(fp)
+ 8023834:	10800704 	addi	r2,r2,28
+ 8023838:	01800104 	movi	r6,4
+ 802383c:	100b883a 	mov	r5,r2
+ 8023840:	1809883a 	mov	r4,r3
+ 8023844:	80087b80 	call	80087b8 <memmove>
+   }
+#endif   /* NO_CC_PACKING */
+
+   /* if a packet oriented send exists, use it: */
+   if (outpkt->net->pkt_send)
+ 8023848:	e0bfff17 	ldw	r2,-4(fp)
+ 802384c:	10800617 	ldw	r2,24(r2)
+ 8023850:	10800417 	ldw	r2,16(r2)
+ 8023854:	10000a26 	beq	r2,zero,8023880 <arpReply+0x25c>
+   {
+      outpkt->nb_prot = outpkt->nb_buff;
+ 8023858:	e0bfff17 	ldw	r2,-4(fp)
+ 802385c:	10c00117 	ldw	r3,4(r2)
+ 8023860:	e0bfff17 	ldw	r2,-4(fp)
+ 8023864:	10c00315 	stw	r3,12(r2)
+      outpkt->net->pkt_send(outpkt);
+ 8023868:	e0bfff17 	ldw	r2,-4(fp)
+ 802386c:	10800617 	ldw	r2,24(r2)
+ 8023870:	10800417 	ldw	r2,16(r2)
+ 8023874:	e13fff17 	ldw	r4,-4(fp)
+ 8023878:	103ee83a 	callr	r2
+ 802387c:	00001106 	br	80238c4 <arpReply+0x2a0>
+   }
+   else
+   {
+      outpkt->net->raw_send(pkt->net, outpkt->nb_buff, outpkt->nb_plen);
+ 8023880:	e0bfff17 	ldw	r2,-4(fp)
+ 8023884:	10800617 	ldw	r2,24(r2)
+ 8023888:	10800317 	ldw	r2,12(r2)
+ 802388c:	e0fff917 	ldw	r3,-28(fp)
+ 8023890:	19000617 	ldw	r4,24(r3)
+ 8023894:	e0ffff17 	ldw	r3,-4(fp)
+ 8023898:	19400117 	ldw	r5,4(r3)
+ 802389c:	e0ffff17 	ldw	r3,-4(fp)
+ 80238a0:	18c00417 	ldw	r3,16(r3)
+ 80238a4:	180d883a 	mov	r6,r3
+ 80238a8:	103ee83a 	callr	r2
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 80238ac:	01000084 	movi	r4,2
+ 80238b0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(outpkt);
+ 80238b4:	e13fff17 	ldw	r4,-4(fp)
+ 80238b8:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 80238bc:	01000084 	movi	r4,2
+ 80238c0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   }
+   /* input 'pkt' will be freed by caller */
+   arpRepsOut++;
+ 80238c4:	d0a06317 	ldw	r2,-32372(gp)
+ 80238c8:	10800044 	addi	r2,r2,1
+ 80238cc:	d0a06315 	stw	r2,-32372(gp)
+}
+ 80238d0:	e037883a 	mov	sp,fp
+ 80238d4:	dfc00117 	ldw	ra,4(sp)
+ 80238d8:	df000017 	ldw	fp,0(sp)
+ 80238dc:	dec00204 	addi	sp,sp,8
+ 80238e0:	f800283a 	ret
+
+080238e4 <arprcv>:
+ *                            else a negative error code. 
+ */
+
+int
+arprcv(PACKET pkt)
+{
+ 80238e4:	defff904 	addi	sp,sp,-28
+ 80238e8:	dfc00615 	stw	ra,24(sp)
+ 80238ec:	df000515 	stw	fp,20(sp)
+ 80238f0:	df000504 	addi	fp,sp,20
+ 80238f4:	e13ffb15 	stw	r4,-20(fp)
+   char *eth;
+#ifdef IEEE_802_3
+   int      ieee = FALSE;     /* TRUE if received packet is 802.3 */
+#endif
+
+   eth = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS);
+ 80238f8:	e0bffb17 	ldw	r2,-20(fp)
+ 80238fc:	10800317 	ldw	r2,12(r2)
+ 8023900:	10bffc84 	addi	r2,r2,-14
+ 8023904:	e0bffe15 	stw	r2,-8(fp)
+   arphdr = (struct arp_hdr *)(pkt->nb_prot);
+ 8023908:	e0bffb17 	ldw	r2,-20(fp)
+ 802390c:	10800317 	ldw	r2,12(r2)
+ 8023910:	e0bffd15 	stw	r2,-12(fp)
+#endif   /* IEEE_802_3_ONLY */
+#endif   /* IEEE_802_3 */
+
+#ifdef NO_CC_PACKING    /* force ARP fields to local CPU valid boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+ 8023914:	e0bffd17 	ldw	r2,-12(fp)
+ 8023918:	e0bffc15 	stw	r2,-16(fp)
+      MEMMOVE(&arphdr->ar_tpa, &arwp->data[AR_TPA], 4);
+ 802391c:	e0bffd17 	ldw	r2,-12(fp)
+ 8023920:	10c00704 	addi	r3,r2,28
+ 8023924:	e0bffc17 	ldw	r2,-16(fp)
+ 8023928:	10800604 	addi	r2,r2,24
+ 802392c:	01800104 	movi	r6,4
+ 8023930:	100b883a 	mov	r5,r2
+ 8023934:	1809883a 	mov	r4,r3
+ 8023938:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(arphdr->ar_tha, &arwp->data[AR_THA], 6);
+ 802393c:	e0bffd17 	ldw	r2,-12(fp)
+ 8023940:	10c00504 	addi	r3,r2,20
+ 8023944:	e0bffc17 	ldw	r2,-16(fp)
+ 8023948:	10800484 	addi	r2,r2,18
+ 802394c:	01800184 	movi	r6,6
+ 8023950:	100b883a 	mov	r5,r2
+ 8023954:	1809883a 	mov	r4,r3
+ 8023958:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arphdr->ar_spa, &arwp->data[AR_SPA], 4);
+ 802395c:	e0bffd17 	ldw	r2,-12(fp)
+ 8023960:	10c00404 	addi	r3,r2,16
+ 8023964:	e0bffc17 	ldw	r2,-16(fp)
+ 8023968:	10800384 	addi	r2,r2,14
+ 802396c:	01800104 	movi	r6,4
+ 8023970:	100b883a 	mov	r5,r2
+ 8023974:	1809883a 	mov	r4,r3
+ 8023978:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(arphdr->ar_sha, &arwp->data[AR_SHA], 6);
+ 802397c:	e0bffd17 	ldw	r2,-12(fp)
+ 8023980:	10c00204 	addi	r3,r2,8
+ 8023984:	e0bffc17 	ldw	r2,-16(fp)
+ 8023988:	10800204 	addi	r2,r2,8
+ 802398c:	01800184 	movi	r6,6
+ 8023990:	100b883a 	mov	r5,r2
+ 8023994:	1809883a 	mov	r4,r3
+ 8023998:	80087b80 	call	80087b8 <memmove>
+#endif
+   USE_ARG(eth);
+
+   /* check ARP's target IP against our net's: */
+#ifdef IP_MULTICAST
+   if ((arphdr->ar_tpa != pkt->net->n_ipaddr) &&   /* if it's not for me.... */
+ 802399c:	e0bffd17 	ldw	r2,-12(fp)
+ 80239a0:	10c00717 	ldw	r3,28(r2)
+ 80239a4:	e0bffb17 	ldw	r2,-20(fp)
+ 80239a8:	10800617 	ldw	r2,24(r2)
+ 80239ac:	10800a17 	ldw	r2,40(r2)
+ 80239b0:	18801c26 	beq	r3,r2,8023a24 <arprcv+0x140>
+     (!IN_MULTICAST(ntohl(arphdr->ar_tpa))))
+ 80239b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80239b8:	10800717 	ldw	r2,28(r2)
+ 80239bc:	1006d63a 	srli	r3,r2,24
+ 80239c0:	e0bffd17 	ldw	r2,-12(fp)
+ 80239c4:	10800717 	ldw	r2,28(r2)
+ 80239c8:	1004d23a 	srli	r2,r2,8
+ 80239cc:	10bfc00c 	andi	r2,r2,65280
+ 80239d0:	1886b03a 	or	r3,r3,r2
+ 80239d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80239d8:	10800717 	ldw	r2,28(r2)
+ 80239dc:	1004923a 	slli	r2,r2,8
+ 80239e0:	10803fec 	andhi	r2,r2,255
+ 80239e4:	1886b03a 	or	r3,r3,r2
+ 80239e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80239ec:	10800717 	ldw	r2,28(r2)
+ 80239f0:	1004963a 	slli	r2,r2,24
+ 80239f4:	1884b03a 	or	r2,r3,r2
+ 80239f8:	10fc002c 	andhi	r3,r2,61440
+   if ((arphdr->ar_tpa != pkt->net->n_ipaddr) &&   /* if it's not for me.... */
+ 80239fc:	00b80034 	movhi	r2,57344
+ 8023a00:	18800826 	beq	r3,r2,8023a24 <arprcv+0x140>
+#else
+   if (arphdr->ar_tpa != pkt->net->n_ipaddr)
+#endif /* IP_MULTICAST */
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023a04:	01000084 	movi	r4,2
+ 8023a08:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);     /* not for us, dump & ret (proxy here later?) */
+ 8023a0c:	e13ffb17 	ldw	r4,-20(fp)
+ 8023a10:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023a14:	01000084 	movi	r4,2
+ 8023a18:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return (ENP_NOT_MINE);
+ 8023a1c:	00800084 	movi	r2,2
+ 8023a20:	00004406 	br	8023b34 <arprcv+0x250>
+   }
+
+   if (arphdr->ar_op == ARREQ)   /* is it an arp request? */
+ 8023a24:	e0bffd17 	ldw	r2,-12(fp)
+ 8023a28:	1080018b 	ldhu	r2,6(r2)
+ 8023a2c:	10bfffcc 	andi	r2,r2,65535
+ 8023a30:	10804018 	cmpnei	r2,r2,256
+ 8023a34:	10000d1e 	bne	r2,zero,8023a6c <arprcv+0x188>
+   {
+      arpReqsIn++;   /* count these */
+ 8023a38:	d0a06017 	ldw	r2,-32384(gp)
+ 8023a3c:	10800044 	addi	r2,r2,1
+ 8023a40:	d0a06015 	stw	r2,-32384(gp)
+      arpReply(pkt); /* send arp reply */
+ 8023a44:	e13ffb17 	ldw	r4,-20(fp)
+ 8023a48:	80236240 	call	8023624 <arpReply>
+      /* make partial ARP table entry */
+      make_arp_entry(arphdr->ar_spa, pkt->net);
+ 8023a4c:	e0bffd17 	ldw	r2,-12(fp)
+ 8023a50:	10c00417 	ldw	r3,16(r2)
+ 8023a54:	e0bffb17 	ldw	r2,-20(fp)
+ 8023a58:	10800617 	ldw	r2,24(r2)
+ 8023a5c:	100b883a 	mov	r5,r2
+ 8023a60:	1809883a 	mov	r4,r3
+ 8023a64:	80235280 	call	8023528 <make_arp_entry>
+ 8023a68:	00000306 	br	8023a78 <arprcv+0x194>
+      /* fall thru to arp reply logic to finish our table entry */
+   }
+   else     /* ARP reply, count and fall thru to logic to update table */
+   {
+      arpRepsIn++;
+ 8023a6c:	d0a06217 	ldw	r2,-32376(gp)
+ 8023a70:	10800044 	addi	r2,r2,1
+ 8023a74:	d0a06215 	stw	r2,-32376(gp)
+   }
+
+   /* scan table for matching entry */
+   /* check this for default gateway situations later, JB */
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 8023a78:	008201b4 	movhi	r2,2054
+ 8023a7c:	10b66604 	addi	r2,r2,-9832
+ 8023a80:	e0bfff15 	stw	r2,-4(fp)
+ 8023a84:	00002006 	br	8023b08 <arprcv+0x224>
+   {
+      if (tp->t_pro_addr == arphdr->ar_spa)     /* we found IP address, update entry */
+ 8023a88:	e0bfff17 	ldw	r2,-4(fp)
+ 8023a8c:	10c00017 	ldw	r3,0(r2)
+ 8023a90:	e0bffd17 	ldw	r2,-12(fp)
+ 8023a94:	10800417 	ldw	r2,16(r2)
+ 8023a98:	1880181e 	bne	r3,r2,8023afc <arprcv+0x218>
+            tp->flags |= ET_SNAP;
+         else
+            tp->flags |= ET_ETH2;      /* else it's ethernet II */
+#endif   /* IEEE_802_3 */
+
+         MEMMOVE(tp->t_phy_addr, arphdr->ar_sha, 6);   /* update MAC adddress */
+ 8023a9c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023aa0:	10c00104 	addi	r3,r2,4
+ 8023aa4:	e0bffd17 	ldw	r2,-12(fp)
+ 8023aa8:	10800204 	addi	r2,r2,8
+ 8023aac:	01800184 	movi	r6,6
+ 8023ab0:	100b883a 	mov	r5,r2
+ 8023ab4:	1809883a 	mov	r4,r3
+ 8023ab8:	80087b80 	call	80087b8 <memmove>
+         tp->lasttime = cticks;
+ 8023abc:	d0e07d17 	ldw	r3,-32268(gp)
+ 8023ac0:	e0bfff17 	ldw	r2,-4(fp)
+ 8023ac4:	10c00615 	stw	r3,24(r2)
+         if (tp->pending)     /* packet waiting for this IP entry? */
+ 8023ac8:	e0bfff17 	ldw	r2,-4(fp)
+ 8023acc:	10800417 	ldw	r2,16(r2)
+ 8023ad0:	10000226 	beq	r2,zero,8023adc <arprcv+0x1f8>
+         {
+            arp_send_pending(tp);
+ 8023ad4:	e13fff17 	ldw	r4,-4(fp)
+ 8023ad8:	8022ef40 	call	8022ef4 <arp_send_pending>
+         }
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023adc:	01000084 	movi	r4,2
+ 8023ae0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);
+ 8023ae4:	e13ffb17 	ldw	r4,-20(fp)
+ 8023ae8:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023aec:	01000084 	movi	r4,2
+ 8023af0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+         return (0);
+ 8023af4:	0005883a 	mov	r2,zero
+ 8023af8:	00000e06 	br	8023b34 <arprcv+0x250>
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 8023afc:	e0bfff17 	ldw	r2,-4(fp)
+ 8023b00:	10800804 	addi	r2,r2,32
+ 8023b04:	e0bfff15 	stw	r2,-4(fp)
+ 8023b08:	e0ffff17 	ldw	r3,-4(fp)
+ 8023b0c:	008201b4 	movhi	r2,2054
+ 8023b10:	10b6a604 	addi	r2,r2,-9576
+ 8023b14:	18bfdc36 	bltu	r3,r2,8023a88 <arprcv+0x1a4>
+
+#ifdef IEEE_802_3_ONLY
+drop:
+#endif /* IEEE_802_3_ONLY */
+   /* fall to here if packet is not in table */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023b18:	01000084 	movi	r4,2
+ 8023b1c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(pkt);
+ 8023b20:	e13ffb17 	ldw	r4,-20(fp)
+ 8023b24:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023b28:	01000084 	movi	r4,2
+ 8023b2c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   return ENP_NOT_MINE;
+ 8023b30:	00800084 	movi	r2,2
+}
+ 8023b34:	e037883a 	mov	sp,fp
+ 8023b38:	dfc00117 	ldw	ra,4(sp)
+ 8023b3c:	df000017 	ldw	fp,0(sp)
+ 8023b40:	dec00204 	addi	sp,sp,8
+ 8023b44:	f800283a 	ret
+
+08023b48 <send_via_arp>:
+ * change the PC's IP address. 
+ */
+
+int
+send_via_arp(PACKET pkt, ip_addr dest_ip)
+{
+ 8023b48:	defff804 	addi	sp,sp,-32
+ 8023b4c:	dfc00715 	stw	ra,28(sp)
+ 8023b50:	df000615 	stw	fp,24(sp)
+ 8023b54:	df000604 	addi	fp,sp,24
+ 8023b58:	e13ffb15 	stw	r4,-20(fp)
+ 8023b5c:	e17ffa15 	stw	r5,-24(fp)
+   struct arptabent *tp;
+   unsigned long lticks = cticks;
+ 8023b60:	d0a07d17 	ldw	r2,-32268(gp)
+ 8023b64:	e0bffc15 	stw	r2,-16(fp)
+   int err;
+
+   /* don't allow zero dest */
+   if (dest_ip == 0)
+ 8023b68:	e0bffa17 	ldw	r2,-24(fp)
+ 8023b6c:	1000081e 	bne	r2,zero,8023b90 <send_via_arp+0x48>
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023b70:	01000084 	movi	r4,2
+ 8023b74:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);
+ 8023b78:	e13ffb17 	ldw	r4,-20(fp)
+ 8023b7c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023b80:	01000084 	movi	r4,2
+ 8023b84:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return SEND_DROPPED; 
+ 8023b88:	00bffa84 	movi	r2,-22
+ 8023b8c:	00004806 	br	8023cb0 <send_via_arp+0x168>
+   }
+
+   /* Force refresh of cache once a second */
+   if ((lticks - cachetime) > TPS)
+ 8023b90:	d0a05f17 	ldw	r2,-32388(gp)
+ 8023b94:	e0fffc17 	ldw	r3,-16(fp)
+ 8023b98:	1885c83a 	sub	r2,r3,r2
+ 8023b9c:	10801970 	cmpltui	r2,r2,101
+ 8023ba0:	1000011e 	bne	r2,zero,8023ba8 <send_via_arp+0x60>
+      arpcache = (struct arptabent *)NULL;
+ 8023ba4:	d0205e15 	stw	zero,-32392(gp)
+
+   /* look at the last ARP entry used. Good chance it's ours: */
+   if (arpcache && (arpcache->t_pro_addr == dest_ip))
+ 8023ba8:	d0a05e17 	ldw	r2,-32392(gp)
+ 8023bac:	10000726 	beq	r2,zero,8023bcc <send_via_arp+0x84>
+ 8023bb0:	d0a05e17 	ldw	r2,-32392(gp)
+ 8023bb4:	10800017 	ldw	r2,0(r2)
+ 8023bb8:	e0fffa17 	ldw	r3,-24(fp)
+ 8023bbc:	1880031e 	bne	r3,r2,8023bcc <send_via_arp+0x84>
+      tp = arpcache;
+ 8023bc0:	d0a05e17 	ldw	r2,-32392(gp)
+ 8023bc4:	e0bfff15 	stw	r2,-4(fp)
+ 8023bc8:	00000306 	br	8023bd8 <send_via_arp+0x90>
+   else
+   {
+      /* scan arp table for an existing entry */
+      tp = find_oldest_arp(dest_ip);
+ 8023bcc:	e13ffa17 	ldw	r4,-24(fp)
+ 8023bd0:	80233bc0 	call	80233bc <find_oldest_arp>
+ 8023bd4:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   if (tp->t_pro_addr == dest_ip)   /* we found our entry */
+ 8023bd8:	e0bfff17 	ldw	r2,-4(fp)
+ 8023bdc:	10800017 	ldw	r2,0(r2)
+ 8023be0:	e0fffa17 	ldw	r3,-24(fp)
+ 8023be4:	18802d1e 	bne	r3,r2,8023c9c <send_via_arp+0x154>
+   {
+      if (tp->pending)  /* arp already pending for this IP? */
+ 8023be8:	e0bfff17 	ldw	r2,-4(fp)
+ 8023bec:	10800417 	ldw	r2,16(r2)
+ 8023bf0:	10002126 	beq	r2,zero,8023c78 <send_via_arp+0x130>
+      {
+         if (lilfreeq.q_len < 2)
+ 8023bf4:	008201b4 	movhi	r2,2054
+ 8023bf8:	10b79817 	ldw	r2,-8608(r2)
+ 8023bfc:	10800088 	cmpgei	r2,r2,2
+ 8023c00:	1000091e 	bne	r2,zero,8023c28 <send_via_arp+0xe0>
+         {
+            /* system is depleted of resources - free the
+             * pkt instead of queueing it - so that we are in a
+             * position to receive an arp reply 
+             */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023c04:	01000084 	movi	r4,2
+ 8023c08:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(pkt);  /* sorry, we have to dump this one.. */
+ 8023c0c:	e13ffb17 	ldw	r4,-20(fp)
+ 8023c10:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023c14:	01000084 	movi	r4,2
+ 8023c18:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            err = SEND_DROPPED;    /* pkts already waiting for this IP entry */
+ 8023c1c:	00bffa84 	movi	r2,-22
+ 8023c20:	e0bffe15 	stw	r2,-8(fp)
+ 8023c24:	00002106 	br	8023cac <send_via_arp+0x164>
+         }
+         else
+         {
+            PACKET tmppkt=tp->pending;
+ 8023c28:	e0bfff17 	ldw	r2,-4(fp)
+ 8023c2c:	10800417 	ldw	r2,16(r2)
+ 8023c30:	e0bffd15 	stw	r2,-12(fp)
+
+            /* queue the packet in pending list */
+            while (tmppkt->next)     /* traverse to the last packet */
+ 8023c34:	00000306 	br	8023c44 <send_via_arp+0xfc>
+               tmppkt = tmppkt->next;
+ 8023c38:	e0bffd17 	ldw	r2,-12(fp)
+ 8023c3c:	10800017 	ldw	r2,0(r2)
+ 8023c40:	e0bffd15 	stw	r2,-12(fp)
+            while (tmppkt->next)     /* traverse to the last packet */
+ 8023c44:	e0bffd17 	ldw	r2,-12(fp)
+ 8023c48:	10800017 	ldw	r2,0(r2)
+ 8023c4c:	103ffa1e 	bne	r2,zero,8023c38 <send_via_arp+0xf0>
+            tmppkt->next = pkt;      /* add new pkt to end of list */
+ 8023c50:	e0bffd17 	ldw	r2,-12(fp)
+ 8023c54:	e0fffb17 	ldw	r3,-20(fp)
+ 8023c58:	10c00015 	stw	r3,0(r2)
+            if (pkt->next)
+ 8023c5c:	e0bffb17 	ldw	r2,-20(fp)
+ 8023c60:	10800017 	ldw	r2,0(r2)
+ 8023c64:	10000126 	beq	r2,zero,8023c6c <send_via_arp+0x124>
+            {
+               dtrap();              /* chain of pkts to be sent ??? */
+ 8023c68:	8028cd40 	call	8028cd4 <dtrap>
+            }
+            err = ENP_SEND_PENDING; /* packet queued pending ARP reply */
+ 8023c6c:	00800044 	movi	r2,1
+ 8023c70:	e0bffe15 	stw	r2,-8(fp)
+ 8023c74:	00000d06 	br	8023cac <send_via_arp+0x164>
+         }
+      }
+      else  /* just send it */
+      {
+         arpcache = tp;       /* cache this entry */
+ 8023c78:	e0bfff17 	ldw	r2,-4(fp)
+ 8023c7c:	d0a05e15 	stw	r2,-32392(gp)
+         cachetime = lticks;  /* mark time we cached */
+ 8023c80:	e0bffc17 	ldw	r2,-16(fp)
+ 8023c84:	d0a05f15 	stw	r2,-32388(gp)
+         err = et_send(pkt, tp);
+ 8023c88:	e17fff17 	ldw	r5,-4(fp)
+ 8023c8c:	e13ffb17 	ldw	r4,-20(fp)
+ 8023c90:	8022cec0 	call	8022cec <et_send>
+ 8023c94:	e0bffe15 	stw	r2,-8(fp)
+ 8023c98:	00000406 	br	8023cac <send_via_arp+0x164>
+      }
+   }
+   else
+      /* start the ARP process for this IP address */
+      err = send_arp(pkt, dest_ip);
+ 8023c9c:	e17ffa17 	ldw	r5,-24(fp)
+ 8023ca0:	e13ffb17 	ldw	r4,-20(fp)
+ 8023ca4:	8022f680 	call	8022f68 <send_arp>
+ 8023ca8:	e0bffe15 	stw	r2,-8(fp)
+
+   return (err);
+ 8023cac:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8023cb0:	e037883a 	mov	sp,fp
+ 8023cb4:	dfc00117 	ldw	ra,4(sp)
+ 8023cb8:	df000017 	ldw	fp,0(sp)
+ 8023cbc:	dec00204 	addi	sp,sp,8
+ 8023cc0:	f800283a 	ret
+
+08023cc4 <cb_arpent_tmo>:
+ *
+ * If there are no more unresolved entries, cancel the timer.
+ */
+void
+cb_arpent_tmo(long arg)
+{
+ 8023cc4:	defffa04 	addi	sp,sp,-24
+ 8023cc8:	dfc00515 	stw	ra,20(sp)
+ 8023ccc:	df000415 	stw	fp,16(sp)
+ 8023cd0:	df000404 	addi	fp,sp,16
+ 8023cd4:	e13ffc15 	stw	r4,-16(fp)
+   struct arptabent *tp;
+   int arp_count = 0;
+ 8023cd8:	e03ffe15 	stw	zero,-8(fp)
+   unsigned long lticks = cticks;
+ 8023cdc:	d0a07d17 	ldw	r2,-32268(gp)
+ 8023ce0:	e0bffd15 	stw	r2,-12(fp)
+
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 8023ce4:	008201b4 	movhi	r2,2054
+ 8023ce8:	10b66604 	addi	r2,r2,-9832
+ 8023cec:	e0bfff15 	stw	r2,-4(fp)
+ 8023cf0:	00002706 	br	8023d90 <cb_arpent_tmo+0xcc>
+   {
+      if (tp->t_pro_addr != 0)
+ 8023cf4:	e0bfff17 	ldw	r2,-4(fp)
+ 8023cf8:	10800017 	ldw	r2,0(r2)
+ 8023cfc:	10002126 	beq	r2,zero,8023d84 <cb_arpent_tmo+0xc0>
+      {
+         /* age out old, pending entries */
+         if (tp->pending && ((lticks - tp->createtime) > TPS))
+ 8023d00:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d04:	10800417 	ldw	r2,16(r2)
+ 8023d08:	10000b26 	beq	r2,zero,8023d38 <cb_arpent_tmo+0x74>
+ 8023d0c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d10:	10800517 	ldw	r2,20(r2)
+ 8023d14:	e0fffd17 	ldw	r3,-12(fp)
+ 8023d18:	1885c83a 	sub	r2,r3,r2
+ 8023d1c:	10801970 	cmpltui	r2,r2,101
+ 8023d20:	1000051e 	bne	r2,zero,8023d38 <cb_arpent_tmo+0x74>
+         {
+            /* purge if pending for more than one second */
+            arp_free_pending(tp);   /* free pending packets */
+ 8023d24:	e13fff17 	ldw	r4,-4(fp)
+ 8023d28:	8022e6c0 	call	8022e6c <arp_free_pending>
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+ 8023d2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d30:	10000015 	stw	zero,0(r2)
+ 8023d34:	00001306 	br	8023d84 <cb_arpent_tmo+0xc0>
+         }
+         else if (((int)(lticks - tp->createtime) >= arp_ageout) &&
+ 8023d38:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d3c:	10800517 	ldw	r2,20(r2)
+ 8023d40:	e0fffd17 	ldw	r3,-12(fp)
+ 8023d44:	1885c83a 	sub	r2,r3,r2
+ 8023d48:	1007883a 	mov	r3,r2
+ 8023d4c:	d0a01117 	ldw	r2,-32700(gp)
+ 8023d50:	18800916 	blt	r3,r2,8023d78 <cb_arpent_tmo+0xb4>
+                  ((int)(lticks - tp->lasttime)   >= TPS))
+ 8023d54:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d58:	10800617 	ldw	r2,24(r2)
+ 8023d5c:	e0fffd17 	ldw	r3,-12(fp)
+ 8023d60:	1885c83a 	sub	r2,r3,r2
+         else if (((int)(lticks - tp->createtime) >= arp_ageout) &&
+ 8023d64:	10801910 	cmplti	r2,r2,100
+ 8023d68:	1000031e 	bne	r2,zero,8023d78 <cb_arpent_tmo+0xb4>
+         {
+            /* entry has "expired" and has not been reference in 1 sec. */
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+ 8023d6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d70:	10000015 	stw	zero,0(r2)
+ 8023d74:	00000306 	br	8023d84 <cb_arpent_tmo+0xc0>
+         }
+         else
+            arp_count++;
+ 8023d78:	e0bffe17 	ldw	r2,-8(fp)
+ 8023d7c:	10800044 	addi	r2,r2,1
+ 8023d80:	e0bffe15 	stw	r2,-8(fp)
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+ 8023d84:	e0bfff17 	ldw	r2,-4(fp)
+ 8023d88:	10800804 	addi	r2,r2,32
+ 8023d8c:	e0bfff15 	stw	r2,-4(fp)
+ 8023d90:	e0ffff17 	ldw	r3,-4(fp)
+ 8023d94:	008201b4 	movhi	r2,2054
+ 8023d98:	10b6a604 	addi	r2,r2,-9576
+ 8023d9c:	18bfd536 	bltu	r3,r2,8023cf4 <cb_arpent_tmo+0x30>
+      }
+   }
+
+   /* if there are no more "pending" entries, kill the timer */
+   if (arp_count == 0)
+ 8023da0:	e0bffe17 	ldw	r2,-8(fp)
+ 8023da4:	1000041e 	bne	r2,zero,8023db8 <cb_arpent_tmo+0xf4>
+   {
+      in_timerkill(arp_timer);
+ 8023da8:	d0a05d17 	ldw	r2,-32396(gp)
+ 8023dac:	1009883a 	mov	r4,r2
+ 8023db0:	8038da00 	call	8038da0 <in_timerkill>
+      arp_timer = 0;
+ 8023db4:	d0205d15 	stw	zero,-32396(gp)
+   }
+      
+   USE_ARG(arg);
+}
+ 8023db8:	0001883a 	nop
+ 8023dbc:	e037883a 	mov	sp,fp
+ 8023dc0:	dfc00117 	ldw	ra,4(sp)
+ 8023dc4:	df000017 	ldw	fp,0(sp)
+ 8023dc8:	dec00204 	addi	sp,sp,8
+ 8023dcc:	f800283a 	ret
+
+08023dd0 <grat_arp>:
+ * RETURNS: Returns 0 if OK, or the usual ENP_ errors 
+ */
+
+int
+grat_arp(NET net, int flag)
+{
+ 8023dd0:	defff704 	addi	sp,sp,-36
+ 8023dd4:	dfc00815 	stw	ra,32(sp)
+ 8023dd8:	df000715 	stw	fp,28(sp)
+ 8023ddc:	df000704 	addi	fp,sp,28
+ 8023de0:	e13ffa15 	stw	r4,-24(fp)
+ 8023de4:	e17ff915 	stw	r5,-28(fp)
+   char * ethhdr;
+   struct arp_hdr *  arphdr;
+   IFMIB etif = net->n_mib;    /* mib info for this ethernet interface */
+ 8023de8:	e0bffa17 	ldw	r2,-24(fp)
+ 8023dec:	10802717 	ldw	r2,156(r2)
+ 8023df0:	e0bfff15 	stw	r2,-4(fp)
+   PACKET arppkt;
+
+   /* get a packet for an ARP request */
+   LOCK_NET_RESOURCE(FREEQ_RESID); 
+ 8023df4:	01000084 	movi	r4,2
+ 8023df8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   arppkt = pk_alloc(arpsize);
+ 8023dfc:	01000c04 	movi	r4,48
+ 8023e00:	80284340 	call	8028434 <pk_alloc>
+ 8023e04:	e0bffe15 	stw	r2,-8(fp)
+   if (!arppkt)
+ 8023e08:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e0c:	1000041e 	bne	r2,zero,8023e20 <grat_arp+0x50>
+   {
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023e10:	01000084 	movi	r4,2
+ 8023e14:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_RESOURCE;
+ 8023e18:	00bffa84 	movi	r2,-22
+ 8023e1c:	00009506 	br	8024074 <grat_arp+0x2a4>
+   }
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8023e20:	01000084 	movi	r4,2
+ 8023e24:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   arppkt->nb_prot = arppkt->nb_buff;
+ 8023e28:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e2c:	10c00117 	ldw	r3,4(r2)
+ 8023e30:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e34:	10c00315 	stw	r3,12(r2)
+   arppkt->nb_plen = arpsize;
+ 8023e38:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e3c:	00c00c04 	movi	r3,48
+ 8023e40:	10c00415 	stw	r3,16(r2)
+   arppkt->net = net;
+ 8023e44:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e48:	e0fffa17 	ldw	r3,-24(fp)
+ 8023e4c:	10c00615 	stw	r3,24(r2)
+
+   /* build arp request packet */
+   ethhdr = arppkt->nb_buff + ETHHDR_BIAS;     /* ethernet header at start of buffer */
+ 8023e50:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e54:	10800117 	ldw	r2,4(r2)
+ 8023e58:	10800084 	addi	r2,r2,2
+ 8023e5c:	e0bffd15 	stw	r2,-12(fp)
+   arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */
+ 8023e60:	e0bffe17 	ldw	r2,-8(fp)
+ 8023e64:	10800117 	ldw	r2,4(r2)
+ 8023e68:	10800404 	addi	r2,r2,16
+ 8023e6c:	e0bffc15 	stw	r2,-16(fp)
+
+#ifdef IEEE_802_3
+   arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   arphdr->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+ 8023e70:	e0bffc17 	ldw	r2,-16(fp)
+ 8023e74:	00c04004 	movi	r3,256
+ 8023e78:	10c0000d 	sth	r3,0(r2)
+#endif /* IEEE_802_3 */
+
+   arphdr->ar_pro = ARPIP;
+ 8023e7c:	e0bffc17 	ldw	r2,-16(fp)
+ 8023e80:	00c00204 	movi	r3,8
+ 8023e84:	10c0008d 	sth	r3,2(r2)
+   arphdr->ar_hln = 6;
+ 8023e88:	e0bffc17 	ldw	r2,-16(fp)
+ 8023e8c:	00c00184 	movi	r3,6
+ 8023e90:	10c00105 	stb	r3,4(r2)
+   arphdr->ar_pln = 4;
+ 8023e94:	e0bffc17 	ldw	r2,-16(fp)
+ 8023e98:	00c00104 	movi	r3,4
+ 8023e9c:	10c00145 	stb	r3,5(r2)
+   
+   /* ARP req? */
+   if (flag == 0)
+ 8023ea0:	e0bff917 	ldw	r2,-28(fp)
+ 8023ea4:	1000041e 	bne	r2,zero,8023eb8 <grat_arp+0xe8>
+      /* yup */
+      arphdr->ar_op = ARREQ;
+ 8023ea8:	e0bffc17 	ldw	r2,-16(fp)
+ 8023eac:	00c04004 	movi	r3,256
+ 8023eb0:	10c0018d 	sth	r3,6(r2)
+ 8023eb4:	00000306 	br	8023ec4 <grat_arp+0xf4>
+   else
+     /* nope */
+      arphdr->ar_op = ARREP;
+ 8023eb8:	e0bffc17 	ldw	r2,-16(fp)
+ 8023ebc:	00c08004 	movi	r3,512
+ 8023ec0:	10c0018d 	sth	r3,6(r2)
+      
+   arphdr->ar_tpa = net->n_ipaddr;        /* target's IP address */
+ 8023ec4:	e0bffa17 	ldw	r2,-24(fp)
+ 8023ec8:	10c00a17 	ldw	r3,40(r2)
+ 8023ecc:	e0bffc17 	ldw	r2,-16(fp)
+ 8023ed0:	10c00715 	stw	r3,28(r2)
+   arphdr->ar_spa = net->n_ipaddr;   /* my IP address */
+ 8023ed4:	e0bffa17 	ldw	r2,-24(fp)
+ 8023ed8:	10c00a17 	ldw	r3,40(r2)
+ 8023edc:	e0bffc17 	ldw	r2,-16(fp)
+ 8023ee0:	10c00415 	stw	r3,16(r2)
+   MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6);
+ 8023ee4:	e0bffc17 	ldw	r2,-16(fp)
+ 8023ee8:	10c00204 	addi	r3,r2,8
+ 8023eec:	e0bfff17 	ldw	r2,-4(fp)
+ 8023ef0:	10800517 	ldw	r2,20(r2)
+ 8023ef4:	01800184 	movi	r6,6
+ 8023ef8:	100b883a 	mov	r5,r2
+ 8023efc:	1809883a 	mov	r4,r3
+ 8023f00:	80087b80 	call	80087b8 <memmove>
+   MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6);     /* destination to broadcast (all FFs) */
+ 8023f04:	01800184 	movi	r6,6
+ 8023f08:	01403fc4 	movi	r5,255
+ 8023f0c:	e13ffd17 	ldw	r4,-12(fp)
+ 8023f10:	80088e40 	call	80088e4 <memset>
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);
+ 8023f14:	e0bffd17 	ldw	r2,-12(fp)
+ 8023f18:	10c00184 	addi	r3,r2,6
+ 8023f1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8023f20:	10800517 	ldw	r2,20(r2)
+ 8023f24:	01800184 	movi	r6,6
+ 8023f28:	100b883a 	mov	r5,r2
+ 8023f2c:	1809883a 	mov	r4,r3
+ 8023f30:	80087b80 	call	80087b8 <memmove>
+   ET_TYPE_SET(ethhdr, ntohs(ET_ARP));
+ 8023f34:	e0bffd17 	ldw	r2,-12(fp)
+ 8023f38:	10800304 	addi	r2,r2,12
+ 8023f3c:	00c00204 	movi	r3,8
+ 8023f40:	10c00005 	stb	r3,0(r2)
+ 8023f44:	e0bffd17 	ldw	r2,-12(fp)
+ 8023f48:	10800344 	addi	r2,r2,13
+ 8023f4c:	00c00184 	movi	r3,6
+ 8023f50:	10c00005 	stb	r3,0(r2)
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+ 8023f54:	e0bffc17 	ldw	r2,-16(fp)
+ 8023f58:	e0bffb15 	stw	r2,-20(fp)
+      MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6);
+ 8023f5c:	e0bffb17 	ldw	r2,-20(fp)
+ 8023f60:	10c00204 	addi	r3,r2,8
+ 8023f64:	e0bffc17 	ldw	r2,-16(fp)
+ 8023f68:	10800204 	addi	r2,r2,8
+ 8023f6c:	01800184 	movi	r6,6
+ 8023f70:	100b883a 	mov	r5,r2
+ 8023f74:	1809883a 	mov	r4,r3
+ 8023f78:	80087b80 	call	80087b8 <memmove>
+      MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4);
+ 8023f7c:	e0bffb17 	ldw	r2,-20(fp)
+ 8023f80:	10c00384 	addi	r3,r2,14
+ 8023f84:	e0bffc17 	ldw	r2,-16(fp)
+ 8023f88:	10800404 	addi	r2,r2,16
+ 8023f8c:	01800104 	movi	r6,4
+ 8023f90:	100b883a 	mov	r5,r2
+ 8023f94:	1809883a 	mov	r4,r3
+ 8023f98:	80087b80 	call	80087b8 <memmove>
+
+   /* ARP req? */
+   if (flag == 0)
+ 8023f9c:	e0bff917 	ldw	r2,-28(fp)
+ 8023fa0:	1000091e 	bne	r2,zero,8023fc8 <grat_arp+0x1f8>
+      /* yup */      
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6);
+ 8023fa4:	e0bffb17 	ldw	r2,-20(fp)
+ 8023fa8:	10c00484 	addi	r3,r2,18
+ 8023fac:	e0bffc17 	ldw	r2,-16(fp)
+ 8023fb0:	10800504 	addi	r2,r2,20
+ 8023fb4:	01800184 	movi	r6,6
+ 8023fb8:	100b883a 	mov	r5,r2
+ 8023fbc:	1809883a 	mov	r4,r3
+ 8023fc0:	80087b80 	call	80087b8 <memmove>
+ 8023fc4:	00000806 	br	8023fe8 <grat_arp+0x218>
+   else
+      /* nope */
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_sha, 6);
+ 8023fc8:	e0bffb17 	ldw	r2,-20(fp)
+ 8023fcc:	10c00484 	addi	r3,r2,18
+ 8023fd0:	e0bffc17 	ldw	r2,-16(fp)
+ 8023fd4:	10800204 	addi	r2,r2,8
+ 8023fd8:	01800184 	movi	r6,6
+ 8023fdc:	100b883a 	mov	r5,r2
+ 8023fe0:	1809883a 	mov	r4,r3
+ 8023fe4:	80087b80 	call	80087b8 <memmove>
+      
+      MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4);
+ 8023fe8:	e0bffb17 	ldw	r2,-20(fp)
+ 8023fec:	10c00604 	addi	r3,r2,24
+ 8023ff0:	e0bffc17 	ldw	r2,-16(fp)
+ 8023ff4:	10800704 	addi	r2,r2,28
+ 8023ff8:	01800104 	movi	r6,4
+ 8023ffc:	100b883a 	mov	r5,r2
+ 8024000:	1809883a 	mov	r4,r3
+ 8024004:	80087b80 	call	80087b8 <memmove>
+   }
+#endif   /* IEEE_802_3 */
+
+#ifndef IEEE_802_3_ONLY
+   /* send arp request - if a packet oriented send exists, use it: */
+   if (net->pkt_send)
+ 8024008:	e0bffa17 	ldw	r2,-24(fp)
+ 802400c:	10800417 	ldw	r2,16(r2)
+ 8024010:	10000526 	beq	r2,zero,8024028 <grat_arp+0x258>
+      net->pkt_send(arppkt);  /* driver should free arppkt later */
+ 8024014:	e0bffa17 	ldw	r2,-24(fp)
+ 8024018:	10800417 	ldw	r2,16(r2)
+ 802401c:	e13ffe17 	ldw	r4,-8(fp)
+ 8024020:	103ee83a 	callr	r2
+ 8024024:	00000f06 	br	8024064 <grat_arp+0x294>
+   else  /* use old raw send */
+   {
+      net->raw_send(arppkt->net, arppkt->nb_buff, arpsize);
+ 8024028:	e0bffa17 	ldw	r2,-24(fp)
+ 802402c:	10800317 	ldw	r2,12(r2)
+ 8024030:	e0fffe17 	ldw	r3,-8(fp)
+ 8024034:	19000617 	ldw	r4,24(r3)
+ 8024038:	e0fffe17 	ldw	r3,-8(fp)
+ 802403c:	18c00117 	ldw	r3,4(r3)
+ 8024040:	01800c04 	movi	r6,48
+ 8024044:	180b883a 	mov	r5,r3
+ 8024048:	103ee83a 	callr	r2
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802404c:	01000084 	movi	r4,2
+ 8024050:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(arppkt);
+ 8024054:	e13ffe17 	ldw	r4,-8(fp)
+ 8024058:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802405c:	01000084 	movi	r4,2
+ 8024060:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   }
+   arpReqsOut++;
+ 8024064:	d0a06117 	ldw	r2,-32380(gp)
+ 8024068:	10800044 	addi	r2,r2,1
+ 802406c:	d0a06115 	stw	r2,-32380(gp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(arppkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif  /* IEEE_802_3_ONLY */
+   
+   return ENP_SEND_PENDING;
+ 8024070:	00800044 	movi	r2,1
+}
+ 8024074:	e037883a 	mov	sp,fp
+ 8024078:	dfc00117 	ldw	ra,4(sp)
+ 802407c:	df000017 	ldw	fp,0(sp)
+ 8024080:	dec00204 	addi	sp,sp,8
+ 8024084:	f800283a 	ret
+
+08024088 <if_getbynum>:
+ * RETURNS: Returns NET pointer, or NULL if out of range
+ */
+
+NET
+if_getbynum(int ifnum)
+{
+ 8024088:	defffc04 	addi	sp,sp,-16
+ 802408c:	dfc00315 	stw	ra,12(sp)
+ 8024090:	df000215 	stw	fp,8(sp)
+ 8024094:	df000204 	addi	fp,sp,8
+ 8024098:	e13ffe15 	stw	r4,-8(fp)
+   NET ifp;
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802409c:	008201b4 	movhi	r2,2054
+ 80240a0:	10b6a617 	ldw	r2,-9576(r2)
+ 80240a4:	e0bfff15 	stw	r2,-4(fp)
+ 80240a8:	00000906 	br	80240d0 <if_getbynum+0x48>
+   {
+      if(ifnum-- == 0)
+ 80240ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80240b0:	10ffffc4 	addi	r3,r2,-1
+ 80240b4:	e0fffe15 	stw	r3,-8(fp)
+ 80240b8:	1000021e 	bne	r2,zero,80240c4 <if_getbynum+0x3c>
+         return ifp;
+ 80240bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80240c0:	00000706 	br	80240e0 <if_getbynum+0x58>
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 80240c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80240c8:	10800017 	ldw	r2,0(r2)
+ 80240cc:	e0bfff15 	stw	r2,-4(fp)
+ 80240d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80240d4:	103ff51e 	bne	r2,zero,80240ac <if_getbynum+0x24>
+   }
+   dtrap();
+ 80240d8:	8028cd40 	call	8028cd4 <dtrap>
+   return NULL;   /* list is not long enough */
+ 80240dc:	0005883a 	mov	r2,zero
+}
+ 80240e0:	e037883a 	mov	sp,fp
+ 80240e4:	dfc00117 	ldw	ra,4(sp)
+ 80240e8:	df000017 	ldw	fp,0(sp)
+ 80240ec:	dec00204 	addi	sp,sp,8
+ 80240f0:	f800283a 	ret
+
+080240f4 <isbcast>:
+ * RETURNS:  Returns TRUE if broadcast, else false. 
+ */
+
+int
+isbcast(NET ifc, unsigned char * addr)
+{
+ 80240f4:	defffd04 	addi	sp,sp,-12
+ 80240f8:	df000215 	stw	fp,8(sp)
+ 80240fc:	df000204 	addi	fp,sp,8
+ 8024100:	e13fff15 	stw	r4,-4(fp)
+ 8024104:	e17ffe15 	stw	r5,-8(fp)
+#if (ALIGN_TYPE > 2)
+   /* On systems with 32bit alignment requirements we have to make
+    * sure our tests are aligned. Specifically, this results in "data
+    * abort" errors on the Samsung/ARM port. 
+    */
+   if((u_long)addr & (ALIGN_TYPE - 1))
+ 8024108:	e0bffe17 	ldw	r2,-8(fp)
+ 802410c:	108000cc 	andi	r2,r2,3
+ 8024110:	10000e26 	beq	r2,zero,802414c <isbcast+0x58>
+   {
+      /* check first two bytes */
+      if ((u_short)*(u_short*)(addr) != 0xFFFF)
+ 8024114:	e0bffe17 	ldw	r2,-8(fp)
+ 8024118:	1080000b 	ldhu	r2,0(r2)
+ 802411c:	10ffffcc 	andi	r3,r2,65535
+ 8024120:	00bfffd4 	movui	r2,65535
+ 8024124:	18800226 	beq	r3,r2,8024130 <isbcast+0x3c>
+         return(FALSE);
+ 8024128:	0005883a 	mov	r2,zero
+ 802412c:	00002206 	br	80241b8 <isbcast+0xc4>
+      if ((u_long)(*(u_long*)(addr + 2)) != 0xFFFFFFFF)
+ 8024130:	e0bffe17 	ldw	r2,-8(fp)
+ 8024134:	10800084 	addi	r2,r2,2
+ 8024138:	10800017 	ldw	r2,0(r2)
+ 802413c:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8024140:	1000101e 	bne	r2,zero,8024184 <isbcast+0x90>
+         return FALSE;
+ 8024144:	0005883a 	mov	r2,zero
+ 8024148:	00001b06 	br	80241b8 <isbcast+0xc4>
+#endif /* ALIGN_TYPE > 4 */
+   {
+      /* check first four bytes for all ones. Since this is the fastest
+       * test, do it first
+       */
+      if ((u_long)(*(u_long*)addr) != 0xFFFFFFFF)
+ 802414c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024150:	10800017 	ldw	r2,0(r2)
+ 8024154:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8024158:	1000021e 	bne	r2,zero,8024164 <isbcast+0x70>
+         return FALSE;
+ 802415c:	0005883a 	mov	r2,zero
+ 8024160:	00001506 	br	80241b8 <isbcast+0xc4>
+
+      /* check last two bytes */
+      if ((u_short)*(u_short*)(addr+4) != 0xFFFF)
+ 8024164:	e0bffe17 	ldw	r2,-8(fp)
+ 8024168:	10800104 	addi	r2,r2,4
+ 802416c:	1080000b 	ldhu	r2,0(r2)
+ 8024170:	10ffffcc 	andi	r3,r2,65535
+ 8024174:	00bfffd4 	movui	r2,65535
+ 8024178:	18800226 	beq	r3,r2,8024184 <isbcast+0x90>
+         return(FALSE);
+ 802417c:	0005883a 	mov	r2,zero
+ 8024180:	00000d06 	br	80241b8 <isbcast+0xc4>
+   }
+   
+   /* now reject any line type packets which don't support broadcast */
+   if ((ifc->n_mib->ifType == PPP) ||
+ 8024184:	e0bfff17 	ldw	r2,-4(fp)
+ 8024188:	10802717 	ldw	r2,156(r2)
+ 802418c:	10800217 	ldw	r2,8(r2)
+ 8024190:	108005e0 	cmpeqi	r2,r2,23
+ 8024194:	1000051e 	bne	r2,zero,80241ac <isbcast+0xb8>
+       (ifc->n_mib->ifType == SLIP))
+ 8024198:	e0bfff17 	ldw	r2,-4(fp)
+ 802419c:	10802717 	ldw	r2,156(r2)
+ 80241a0:	10800217 	ldw	r2,8(r2)
+   if ((ifc->n_mib->ifType == PPP) ||
+ 80241a4:	10800718 	cmpnei	r2,r2,28
+ 80241a8:	1000021e 	bne	r2,zero,80241b4 <isbcast+0xc0>
+   {
+      return FALSE;
+ 80241ac:	0005883a 	mov	r2,zero
+ 80241b0:	00000106 	br	80241b8 <isbcast+0xc4>
+   }
+
+   /* passed all tests, must be broadcast */
+   return(TRUE);
+ 80241b4:	00800044 	movi	r2,1
+}
+ 80241b8:	e037883a 	mov	sp,fp
+ 80241bc:	df000017 	ldw	fp,0(sp)
+ 80241c0:	dec00104 	addi	sp,sp,4
+ 80241c4:	f800283a 	ret
+
+080241c8 <reg_type>:
+ * RETURNS: Returns 0 if OK, else non-zero error code. 
+ */
+
+int
+reg_type(unshort type)
+{
+ 80241c8:	defffb04 	addi	sp,sp,-20
+ 80241cc:	dfc00415 	stw	ra,16(sp)
+ 80241d0:	df000315 	stw	fp,12(sp)
+ 80241d4:	df000304 	addi	fp,sp,12
+ 80241d8:	2005883a 	mov	r2,r4
+ 80241dc:	e0bffd0d 	sth	r2,-12(fp)
+   if (i >= PLLISTLEN)
+      return ENP_RESOURCE;
+#endif   /* DYNAMIC_IFACES */
+
+   /* loop thru list of nets, making them all look at new type */
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 80241e0:	008201b4 	movhi	r2,2054
+ 80241e4:	10b6a617 	ldw	r2,-9576(r2)
+ 80241e8:	e0bfff15 	stw	r2,-4(fp)
+ 80241ec:	00001106 	br	8024234 <reg_type+0x6c>
+   {
+      if (ifp->n_reg_type)    /* make sure call exists */
+ 80241f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80241f4:	10800617 	ldw	r2,24(r2)
+ 80241f8:	10000b26 	beq	r2,zero,8024228 <reg_type+0x60>
+      {
+         e = (ifp->n_reg_type)(type, ifp);
+ 80241fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8024200:	10800617 	ldw	r2,24(r2)
+ 8024204:	e0fffd0b 	ldhu	r3,-12(fp)
+ 8024208:	e17fff17 	ldw	r5,-4(fp)
+ 802420c:	1809883a 	mov	r4,r3
+ 8024210:	103ee83a 	callr	r2
+ 8024214:	e0bffe15 	stw	r2,-8(fp)
+         if (e)
+ 8024218:	e0bffe17 	ldw	r2,-8(fp)
+ 802421c:	10000226 	beq	r2,zero,8024228 <reg_type+0x60>
+            return e;   /* bails out if error */
+ 8024220:	e0bffe17 	ldw	r2,-8(fp)
+ 8024224:	00000606 	br	8024240 <reg_type+0x78>
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8024228:	e0bfff17 	ldw	r2,-4(fp)
+ 802422c:	10800017 	ldw	r2,0(r2)
+ 8024230:	e0bfff15 	stw	r2,-4(fp)
+ 8024234:	e0bfff17 	ldw	r2,-4(fp)
+ 8024238:	103fed1e 	bne	r2,zero,80241f0 <reg_type+0x28>
+      }
+   }
+   return 0;   /* OK code */
+ 802423c:	0005883a 	mov	r2,zero
+}
+ 8024240:	e037883a 	mov	sp,fp
+ 8024244:	dfc00117 	ldw	ra,4(sp)
+ 8024248:	df000017 	ldw	fp,0(sp)
+ 802424c:	dec00204 	addi	sp,sp,8
+ 8024250:	f800283a 	ret
+
+08024254 <if_killsocks>:
+ */
+
+      /* kill this NETs sockets */
+void
+if_killsocks(NET ifp)
+{
+ 8024254:	defffa04 	addi	sp,sp,-24
+ 8024258:	dfc00515 	stw	ra,20(sp)
+ 802425c:	df000415 	stw	fp,16(sp)
+ 8024260:	df000404 	addi	fp,sp,16
+ 8024264:	e13ffc15 	stw	r4,-16(fp)
+   struct socket * so;
+   struct socket * next;
+   NET      so_ifp;     /* interface of sockets in list */
+
+   /* reset any sockets with this iface IP address */
+   so = (struct socket *)(soq.q_head);
+ 8024268:	008201b4 	movhi	r2,2054
+ 802426c:	10b87117 	ldw	r2,-7740(r2)
+ 8024270:	e0bfff15 	stw	r2,-4(fp)
+   while(so)
+ 8024274:	00001306 	br	80242c4 <if_killsocks+0x70>
+   {
+      if(so->so_pcb)
+ 8024278:	e0bfff17 	ldw	r2,-4(fp)
+ 802427c:	10800117 	ldw	r2,4(r2)
+ 8024280:	10000526 	beq	r2,zero,8024298 <if_killsocks+0x44>
+         so_ifp = so->so_pcb->ifp;
+ 8024284:	e0bfff17 	ldw	r2,-4(fp)
+ 8024288:	10800117 	ldw	r2,4(r2)
+ 802428c:	10800a17 	ldw	r2,40(r2)
+ 8024290:	e0bffe15 	stw	r2,-8(fp)
+ 8024294:	00000106 	br	802429c <if_killsocks+0x48>
+      else
+         so_ifp = NULL;
+ 8024298:	e03ffe15 	stw	zero,-8(fp)
+      next = (struct socket *)so->next;
+ 802429c:	e0bfff17 	ldw	r2,-4(fp)
+ 80242a0:	10800017 	ldw	r2,0(r2)
+ 80242a4:	e0bffd15 	stw	r2,-12(fp)
+      if (so_ifp == ifp)
+ 80242a8:	e0fffe17 	ldw	r3,-8(fp)
+ 80242ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80242b0:	1880021e 	bne	r3,r2,80242bc <if_killsocks+0x68>
+      {
+         /* this is a direct heavy-handed close. A reset is sent
+          * and all data is lost. The user should really have closed
+          * all the sockets gracfully first.... 
+          */
+         soabort(so);
+ 80242b4:	e13fff17 	ldw	r4,-4(fp)
+ 80242b8:	802d6fc0 	call	802d6fc <soabort>
+      }
+      so = next;
+ 80242bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80242c0:	e0bfff15 	stw	r2,-4(fp)
+   while(so)
+ 80242c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80242c8:	103feb1e 	bne	r2,zero,8024278 <if_killsocks+0x24>
+   }
+}
+ 80242cc:	0001883a 	nop
+ 80242d0:	e037883a 	mov	sp,fp
+ 80242d4:	dfc00117 	ldw	ra,4(sp)
+ 80242d8:	df000017 	ldw	fp,0(sp)
+ 80242dc:	dec00204 	addi	sp,sp,8
+ 80242e0:	f800283a 	ret
+
+080242e4 <Netinit>:
+ * a non-zero error code
+ */
+
+int
+Netinit()
+{
+ 80242e4:	defffc04 	addi	sp,sp,-16
+ 80242e8:	dfc00315 	stw	ra,12(sp)
+ 80242ec:	df000215 	stw	fp,8(sp)
+ 80242f0:	df000204 	addi	fp,sp,8
+#ifndef MULTI_HOMED
+   ifNumber = 1;     /* prevents weird behavior below... */
+#endif
+
+   /* set our largest header size and frames size */
+   for (i = 0; i < (int)ifNumber; i++)
+ 80242f4:	e03fff15 	stw	zero,-4(fp)
+ 80242f8:	00003c06 	br	80243ec <Netinit+0x108>
+   {
+      /* sanity check on mtu, et.al. We added this because earlier 
+       * drivers were sloppy about setting them, but new
+       * logic depends on these sizes.
+       */
+      if (nets[i]->n_mib->ifType == ETHERNET)   /* ethernet? */
+ 80242fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8024300:	100690ba 	slli	r3,r2,2
+ 8024304:	008201b4 	movhi	r2,2054
+ 8024308:	1885883a 	add	r2,r3,r2
+ 802430c:	10b77017 	ldw	r2,-8768(r2)
+ 8024310:	10802717 	ldw	r2,156(r2)
+ 8024314:	10800217 	ldw	r2,8(r2)
+ 8024318:	10800198 	cmpnei	r2,r2,6
+ 802431c:	10001c1e 	bne	r2,zero,8024390 <Netinit+0xac>
+      {
+         if (nets[i]->n_mtu == 0)   /* let device code override */
+ 8024320:	e0bfff17 	ldw	r2,-4(fp)
+ 8024324:	100690ba 	slli	r3,r2,2
+ 8024328:	008201b4 	movhi	r2,2054
+ 802432c:	1885883a 	add	r2,r3,r2
+ 8024330:	10b77017 	ldw	r2,-8768(r2)
+ 8024334:	10800917 	ldw	r2,36(r2)
+ 8024338:	1000071e 	bne	r2,zero,8024358 <Netinit+0x74>
+            nets[i]->n_mtu = 1514;
+ 802433c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024340:	100690ba 	slli	r3,r2,2
+ 8024344:	008201b4 	movhi	r2,2054
+ 8024348:	1885883a 	add	r2,r3,r2
+ 802434c:	10b77017 	ldw	r2,-8768(r2)
+ 8024350:	00c17a84 	movi	r3,1514
+ 8024354:	10c00915 	stw	r3,36(r2)
+
+         if (nets[i]->n_lnh == 0)
+ 8024358:	e0bfff17 	ldw	r2,-4(fp)
+ 802435c:	100690ba 	slli	r3,r2,2
+ 8024360:	008201b4 	movhi	r2,2054
+ 8024364:	1885883a 	add	r2,r3,r2
+ 8024368:	10b77017 	ldw	r2,-8768(r2)
+ 802436c:	10800817 	ldw	r2,32(r2)
+ 8024370:	1000071e 	bne	r2,zero,8024390 <Netinit+0xac>
+         {
+#ifdef IEEE_802_3
+            nets[i]->n_lnh = ETHHDR_SIZE + sizeof(struct snap_hdr);
+#else
+            nets[i]->n_lnh = ETHHDR_SIZE;
+ 8024374:	e0bfff17 	ldw	r2,-4(fp)
+ 8024378:	100690ba 	slli	r3,r2,2
+ 802437c:	008201b4 	movhi	r2,2054
+ 8024380:	1885883a 	add	r2,r3,r2
+ 8024384:	10b77017 	ldw	r2,-8768(r2)
+ 8024388:	00c00404 	movi	r3,16
+ 802438c:	10c00815 	stw	r3,32(r2)
+      {
+         continue;
+      }
+#endif   /* IP_V6 */
+
+      MaxLnh = max(MaxLnh, nets[i]->n_lnh);
+ 8024390:	e0bfff17 	ldw	r2,-4(fp)
+ 8024394:	100690ba 	slli	r3,r2,2
+ 8024398:	008201b4 	movhi	r2,2054
+ 802439c:	1885883a 	add	r2,r3,r2
+ 80243a0:	10b77017 	ldw	r2,-8768(r2)
+ 80243a4:	10800817 	ldw	r2,32(r2)
+ 80243a8:	d0e06417 	ldw	r3,-32368(gp)
+ 80243ac:	10c0010e 	bge	r2,r3,80243b4 <Netinit+0xd0>
+ 80243b0:	1805883a 	mov	r2,r3
+ 80243b4:	d0a06415 	stw	r2,-32368(gp)
+      MaxMtu = max(MaxMtu, nets[i]->n_mtu);
+ 80243b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80243bc:	100690ba 	slli	r3,r2,2
+ 80243c0:	008201b4 	movhi	r2,2054
+ 80243c4:	1885883a 	add	r2,r3,r2
+ 80243c8:	10b77017 	ldw	r2,-8768(r2)
+ 80243cc:	10800917 	ldw	r2,36(r2)
+ 80243d0:	d0e06517 	ldw	r3,-32364(gp)
+ 80243d4:	10c0010e 	bge	r2,r3,80243dc <Netinit+0xf8>
+ 80243d8:	1805883a 	mov	r2,r3
+ 80243dc:	d0a06515 	stw	r2,-32364(gp)
+   for (i = 0; i < (int)ifNumber; i++)
+ 80243e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80243e4:	10800044 	addi	r2,r2,1
+ 80243e8:	e0bfff15 	stw	r2,-4(fp)
+ 80243ec:	d0a06717 	ldw	r2,-32356(gp)
+ 80243f0:	1007883a 	mov	r3,r2
+ 80243f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80243f8:	10ffc016 	blt	r2,r3,80242fc <Netinit+0x18>
+   }
+
+   /* set up the received packet queue */
+   rcvdq.q_head = rcvdq.q_tail = NULL;
+ 80243fc:	008201b4 	movhi	r2,2054
+ 8024400:	1036ac15 	stw	zero,-9552(r2)
+ 8024404:	008201b4 	movhi	r2,2054
+ 8024408:	10f6ac17 	ldw	r3,-9552(r2)
+ 802440c:	008201b4 	movhi	r2,2054
+ 8024410:	10f6ab15 	stw	r3,-9556(r2)
+   rcvdq.q_max = rcvdq.q_min = rcvdq.q_len = 0;
+ 8024414:	008201b4 	movhi	r2,2054
+ 8024418:	1036ad15 	stw	zero,-9548(r2)
+ 802441c:	008201b4 	movhi	r2,2054
+ 8024420:	10f6ad17 	ldw	r3,-9548(r2)
+ 8024424:	008201b4 	movhi	r2,2054
+ 8024428:	10f6af15 	stw	r3,-9540(r2)
+ 802442c:	008201b4 	movhi	r2,2054
+ 8024430:	10f6af17 	ldw	r3,-9540(r2)
+ 8024434:	008201b4 	movhi	r2,2054
+ 8024438:	10f6ae15 	stw	r3,-9544(r2)
+
+   /* initialize freeq */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802443c:	01000084 	movi	r4,2
+ 8024440:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   e = pk_init();
+ 8024444:	80281a80 	call	80281a8 <pk_init>
+ 8024448:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802444c:	01000084 	movi	r4,2
+ 8024450:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (e)   /* report error (memory ran out?) */
+ 8024454:	e0bffe17 	ldw	r2,-8(fp)
+ 8024458:	10000226 	beq	r2,zero,8024464 <Netinit+0x180>
+      return e;
+ 802445c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024460:	0000cf06 	br	80247a0 <Netinit+0x4bc>
+
+   /* packet buffers in freeq are now all set. */
+   exit_hook(netclose);       /* Clean up nets when we are unloaded */
+ 8024464:	010200b4 	movhi	r4,2050
+ 8024468:	21123904 	addi	r4,r4,18660
+ 802446c:	80251e40 	call	80251e4 <exit_hook>
+
+   /* now do the per-IP interface initializations */
+   for (i = 0; i < (int)ifNumber; i++)
+ 8024470:	e03fff15 	stw	zero,-4(fp)
+ 8024474:	0000c506 	br	802478c <Netinit+0x4a8>
+   {
+      if (nets[i]->n_init != NULL)  /* If iface has init routine... */
+ 8024478:	e0bfff17 	ldw	r2,-4(fp)
+ 802447c:	100690ba 	slli	r3,r2,2
+ 8024480:	008201b4 	movhi	r2,2054
+ 8024484:	1885883a 	add	r2,r3,r2
+ 8024488:	10b77017 	ldw	r2,-8768(r2)
+ 802448c:	10800217 	ldw	r2,8(r2)
+ 8024490:	10007726 	beq	r2,zero,8024670 <Netinit+0x38c>
+      {
+         if ((e = (*nets[i]->n_init)(i)) != 0)  /* call init routine */
+ 8024494:	e0bfff17 	ldw	r2,-4(fp)
+ 8024498:	100690ba 	slli	r3,r2,2
+ 802449c:	008201b4 	movhi	r2,2054
+ 80244a0:	1885883a 	add	r2,r3,r2
+ 80244a4:	10b77017 	ldw	r2,-8768(r2)
+ 80244a8:	10800217 	ldw	r2,8(r2)
+ 80244ac:	e13fff17 	ldw	r4,-4(fp)
+ 80244b0:	103ee83a 	callr	r2
+ 80244b4:	e0bffe15 	stw	r2,-8(fp)
+ 80244b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80244bc:	10000e26 	beq	r2,zero,80244f8 <Netinit+0x214>
+         {
+            dprintf("init error %d on net[%d]\n", e, i);
+ 80244c0:	e1bfff17 	ldw	r6,-4(fp)
+ 80244c4:	e17ffe17 	ldw	r5,-8(fp)
+ 80244c8:	01020174 	movhi	r4,2053
+ 80244cc:	2126bd04 	addi	r4,r4,-25868
+ 80244d0:	8002c780 	call	8002c78 <printf>
+            nets[i]->n_mib->ifOperStatus = NI_DOWN;
+ 80244d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80244d8:	100690ba 	slli	r3,r2,2
+ 80244dc:	008201b4 	movhi	r2,2054
+ 80244e0:	1885883a 	add	r2,r3,r2
+ 80244e4:	10b77017 	ldw	r2,-8768(r2)
+ 80244e8:	10802717 	ldw	r2,156(r2)
+ 80244ec:	00c00084 	movi	r3,2
+ 80244f0:	10c00715 	stw	r3,28(r2)
+            continue;   /* ignore ifaces which fail */
+ 80244f4:	0000a206 	br	8024780 <Netinit+0x49c>
+         }
+         /* If interface is ethernet, set bcast flag bit. This
+          * should really be done by the init routine, but we handle it
+          * here to support MAC drivers which predate the flags field.
+          */
+         if(nets[i]->n_mib->ifType == ETHERNET)
+ 80244f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80244fc:	100690ba 	slli	r3,r2,2
+ 8024500:	008201b4 	movhi	r2,2054
+ 8024504:	1885883a 	add	r2,r3,r2
+ 8024508:	10b77017 	ldw	r2,-8768(r2)
+ 802450c:	10802717 	ldw	r2,156(r2)
+ 8024510:	10800217 	ldw	r2,8(r2)
+ 8024514:	10800198 	cmpnei	r2,r2,6
+ 8024518:	10000d1e 	bne	r2,zero,8024550 <Netinit+0x26c>
+            nets[i]->n_flags |= NF_BCAST;
+ 802451c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024520:	100690ba 	slli	r3,r2,2
+ 8024524:	008201b4 	movhi	r2,2054
+ 8024528:	1885883a 	add	r2,r3,r2
+ 802452c:	10b77017 	ldw	r2,-8768(r2)
+ 8024530:	10c02a17 	ldw	r3,168(r2)
+ 8024534:	e0bfff17 	ldw	r2,-4(fp)
+ 8024538:	100890ba 	slli	r4,r2,2
+ 802453c:	008201b4 	movhi	r2,2054
+ 8024540:	2085883a 	add	r2,r4,r2
+ 8024544:	10b77017 	ldw	r2,-8768(r2)
+ 8024548:	18c00054 	ori	r3,r3,1
+ 802454c:	10c02a15 	stw	r3,168(r2)
+
+         /* set ifAdminStatus in case init() routine forgot to. IfOperStatus
+          * is not nessecarily up at this point, as in the case of a modem which
+          * is now in autoanswer mode.
+          */
+         nets[i]->n_mib->ifAdminStatus = NI_UP;
+ 8024550:	e0bfff17 	ldw	r2,-4(fp)
+ 8024554:	100690ba 	slli	r3,r2,2
+ 8024558:	008201b4 	movhi	r2,2054
+ 802455c:	1885883a 	add	r2,r3,r2
+ 8024560:	10b77017 	ldw	r2,-8768(r2)
+ 8024564:	10802717 	ldw	r2,156(r2)
+ 8024568:	00c00044 	movi	r3,1
+ 802456c:	10c00615 	stw	r3,24(r2)
+
+         /* assign default names to unnamed ifaces */
+         if(nets[i]->name[0] == 0)     /* no name set by prep or init */
+ 8024570:	e0bfff17 	ldw	r2,-4(fp)
+ 8024574:	100690ba 	slli	r3,r2,2
+ 8024578:	008201b4 	movhi	r2,2054
+ 802457c:	1885883a 	add	r2,r3,r2
+ 8024580:	10b77017 	ldw	r2,-8768(r2)
+ 8024584:	10800103 	ldbu	r2,4(r2)
+ 8024588:	10803fcc 	andi	r2,r2,255
+ 802458c:	1080201c 	xori	r2,r2,128
+ 8024590:	10bfe004 	addi	r2,r2,-128
+ 8024594:	1000361e 	bne	r2,zero,8024670 <Netinit+0x38c>
+         {
+            if(nets[i]->n_mib->ifType == ETHERNET)
+ 8024598:	e0bfff17 	ldw	r2,-4(fp)
+ 802459c:	100690ba 	slli	r3,r2,2
+ 80245a0:	008201b4 	movhi	r2,2054
+ 80245a4:	1885883a 	add	r2,r3,r2
+ 80245a8:	10b77017 	ldw	r2,-8768(r2)
+ 80245ac:	10802717 	ldw	r2,156(r2)
+ 80245b0:	10800217 	ldw	r2,8(r2)
+ 80245b4:	10800198 	cmpnei	r2,r2,6
+ 80245b8:	10000f1e 	bne	r2,zero,80245f8 <Netinit+0x314>
+            {
+               nets[i]->name[0] = 'e';    /* "et1", "et2", etc. */
+ 80245bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80245c0:	100690ba 	slli	r3,r2,2
+ 80245c4:	008201b4 	movhi	r2,2054
+ 80245c8:	1885883a 	add	r2,r3,r2
+ 80245cc:	10b77017 	ldw	r2,-8768(r2)
+ 80245d0:	00c01944 	movi	r3,101
+ 80245d4:	10c00105 	stb	r3,4(r2)
+               nets[i]->name[1] = 't';
+ 80245d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80245dc:	100690ba 	slli	r3,r2,2
+ 80245e0:	008201b4 	movhi	r2,2054
+ 80245e4:	1885883a 	add	r2,r3,r2
+ 80245e8:	10b77017 	ldw	r2,-8768(r2)
+ 80245ec:	00c01d04 	movi	r3,116
+ 80245f0:	10c00145 	stb	r3,5(r2)
+ 80245f4:	00000e06 	br	8024630 <Netinit+0x34c>
+            }
+            else
+            {
+               nets[i]->name[0] = 'i';    /* "if1", "if2", etc. */
+ 80245f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80245fc:	100690ba 	slli	r3,r2,2
+ 8024600:	008201b4 	movhi	r2,2054
+ 8024604:	1885883a 	add	r2,r3,r2
+ 8024608:	10b77017 	ldw	r2,-8768(r2)
+ 802460c:	00c01a44 	movi	r3,105
+ 8024610:	10c00105 	stb	r3,4(r2)
+               nets[i]->name[1] = 'f';
+ 8024614:	e0bfff17 	ldw	r2,-4(fp)
+ 8024618:	100690ba 	slli	r3,r2,2
+ 802461c:	008201b4 	movhi	r2,2054
+ 8024620:	1885883a 	add	r2,r3,r2
+ 8024624:	10b77017 	ldw	r2,-8768(r2)
+ 8024628:	00c01984 	movi	r3,102
+ 802462c:	10c00145 	stb	r3,5(r2)
+            }
+            nets[i]->name[2] = (char)(i + '1');
+ 8024630:	e0bfff17 	ldw	r2,-4(fp)
+ 8024634:	10800c44 	addi	r2,r2,49
+ 8024638:	1009883a 	mov	r4,r2
+ 802463c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024640:	100690ba 	slli	r3,r2,2
+ 8024644:	008201b4 	movhi	r2,2054
+ 8024648:	1885883a 	add	r2,r3,r2
+ 802464c:	10b77017 	ldw	r2,-8768(r2)
+ 8024650:	2007883a 	mov	r3,r4
+ 8024654:	10c00185 	stb	r3,6(r2)
+            nets[i]->name[3] = '\0';
+ 8024658:	e0bfff17 	ldw	r2,-4(fp)
+ 802465c:	100690ba 	slli	r3,r2,2
+ 8024660:	008201b4 	movhi	r2,2054
+ 8024664:	1885883a 	add	r2,r3,r2
+ 8024668:	10b77017 	ldw	r2,-8768(r2)
+ 802466c:	100001c5 	stb	zero,7(r2)
+         }
+      }
+      /* check on subnet routing - if no mask then make one */
+      fixup_subnet_mask(i);      /* make mask for this net */
+ 8024670:	e13fff17 	ldw	r4,-4(fp)
+ 8024674:	80247b40 	call	80247b4 <fixup_subnet_mask>
+
+      /* build broadcast addresses */
+      if(nets[i]->n_ipaddr != 0)
+ 8024678:	e0bfff17 	ldw	r2,-4(fp)
+ 802467c:	100690ba 	slli	r3,r2,2
+ 8024680:	008201b4 	movhi	r2,2054
+ 8024684:	1885883a 	add	r2,r3,r2
+ 8024688:	10b77017 	ldw	r2,-8768(r2)
+ 802468c:	10800a17 	ldw	r2,40(r2)
+ 8024690:	10003b26 	beq	r2,zero,8024780 <Netinit+0x49c>
+      {
+         nets[i]->n_netbr = nets[i]->n_ipaddr | ~nets[i]->snmask;
+ 8024694:	e0bfff17 	ldw	r2,-4(fp)
+ 8024698:	100690ba 	slli	r3,r2,2
+ 802469c:	008201b4 	movhi	r2,2054
+ 80246a0:	1885883a 	add	r2,r3,r2
+ 80246a4:	10b77017 	ldw	r2,-8768(r2)
+ 80246a8:	11000a17 	ldw	r4,40(r2)
+ 80246ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80246b0:	100690ba 	slli	r3,r2,2
+ 80246b4:	008201b4 	movhi	r2,2054
+ 80246b8:	1885883a 	add	r2,r3,r2
+ 80246bc:	10b77017 	ldw	r2,-8768(r2)
+ 80246c0:	10800c17 	ldw	r2,48(r2)
+ 80246c4:	0086303a 	nor	r3,zero,r2
+ 80246c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80246cc:	100a90ba 	slli	r5,r2,2
+ 80246d0:	008201b4 	movhi	r2,2054
+ 80246d4:	2885883a 	add	r2,r5,r2
+ 80246d8:	10b77017 	ldw	r2,-8768(r2)
+ 80246dc:	20c6b03a 	or	r3,r4,r3
+ 80246e0:	10c00e15 	stw	r3,56(r2)
+         nets[i]->n_netbr42 = nets[i]->n_ipaddr & nets[i]->snmask;
+ 80246e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80246e8:	100690ba 	slli	r3,r2,2
+ 80246ec:	008201b4 	movhi	r2,2054
+ 80246f0:	1885883a 	add	r2,r3,r2
+ 80246f4:	10b77017 	ldw	r2,-8768(r2)
+ 80246f8:	11000a17 	ldw	r4,40(r2)
+ 80246fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8024700:	100690ba 	slli	r3,r2,2
+ 8024704:	008201b4 	movhi	r2,2054
+ 8024708:	1885883a 	add	r2,r3,r2
+ 802470c:	10b77017 	ldw	r2,-8768(r2)
+ 8024710:	10c00c17 	ldw	r3,48(r2)
+ 8024714:	e0bfff17 	ldw	r2,-4(fp)
+ 8024718:	100a90ba 	slli	r5,r2,2
+ 802471c:	008201b4 	movhi	r2,2054
+ 8024720:	2885883a 	add	r2,r5,r2
+ 8024724:	10b77017 	ldw	r2,-8768(r2)
+ 8024728:	20c6703a 	and	r3,r4,r3
+ 802472c:	10c00f15 	stw	r3,60(r2)
+         nets[i]->n_subnetbr = nets[i]->n_ipaddr | ~nets[i]->snmask;
+ 8024730:	e0bfff17 	ldw	r2,-4(fp)
+ 8024734:	100690ba 	slli	r3,r2,2
+ 8024738:	008201b4 	movhi	r2,2054
+ 802473c:	1885883a 	add	r2,r3,r2
+ 8024740:	10b77017 	ldw	r2,-8768(r2)
+ 8024744:	11000a17 	ldw	r4,40(r2)
+ 8024748:	e0bfff17 	ldw	r2,-4(fp)
+ 802474c:	100690ba 	slli	r3,r2,2
+ 8024750:	008201b4 	movhi	r2,2054
+ 8024754:	1885883a 	add	r2,r3,r2
+ 8024758:	10b77017 	ldw	r2,-8768(r2)
+ 802475c:	10800c17 	ldw	r2,48(r2)
+ 8024760:	0086303a 	nor	r3,zero,r2
+ 8024764:	e0bfff17 	ldw	r2,-4(fp)
+ 8024768:	100a90ba 	slli	r5,r2,2
+ 802476c:	008201b4 	movhi	r2,2054
+ 8024770:	2885883a 	add	r2,r5,r2
+ 8024774:	10b77017 	ldw	r2,-8768(r2)
+ 8024778:	20c6b03a 	or	r3,r4,r3
+ 802477c:	10c01015 	stw	r3,64(r2)
+   for (i = 0; i < (int)ifNumber; i++)
+ 8024780:	e0bfff17 	ldw	r2,-4(fp)
+ 8024784:	10800044 	addi	r2,r2,1
+ 8024788:	e0bfff15 	stw	r2,-4(fp)
+ 802478c:	d0a06717 	ldw	r2,-32356(gp)
+ 8024790:	1007883a 	mov	r3,r2
+ 8024794:	e0bfff17 	ldw	r2,-4(fp)
+ 8024798:	10ff3716 	blt	r2,r3,8024478 <Netinit+0x194>
+#if defined(DYNAMIC_IFACES) && defined(IN_MENUS)
+   /* Install dynamic iface menu */
+   install_menu(&dynif_menu[0]);
+#endif /* DYNAMIC_IFACES && IN_MENUS */
+
+   return(0);
+ 802479c:	0005883a 	mov	r2,zero
+}
+ 80247a0:	e037883a 	mov	sp,fp
+ 80247a4:	dfc00117 	ldw	ra,4(sp)
+ 80247a8:	df000017 	ldw	fp,0(sp)
+ 80247ac:	dec00204 	addi	sp,sp,8
+ 80247b0:	f800283a 	ret
+
+080247b4 <fixup_subnet_mask>:
+ * RETURNS: 
+ */
+
+void
+fixup_subnet_mask(int netnum)      /* which of the nets[] to do. */
+{
+ 80247b4:	defffc04 	addi	sp,sp,-16
+ 80247b8:	dfc00315 	stw	ra,12(sp)
+ 80247bc:	df000215 	stw	fp,8(sp)
+ 80247c0:	df000204 	addi	fp,sp,8
+ 80247c4:	e13ffe15 	stw	r4,-8(fp)
+   u_long   smask;
+
+   if (nets[netnum]->snmask)  /* if mask is already set, don't bother */
+ 80247c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80247cc:	100690ba 	slli	r3,r2,2
+ 80247d0:	008201b4 	movhi	r2,2054
+ 80247d4:	1885883a 	add	r2,r3,r2
+ 80247d8:	10b77017 	ldw	r2,-8768(r2)
+ 80247dc:	10800c17 	ldw	r2,48(r2)
+ 80247e0:	10003a1e 	bne	r2,zero,80248cc <fixup_subnet_mask+0x118>
+      return;
+
+   /* things depending on IP address class: */
+   if ((nets[netnum]->n_ipaddr & AMASK) == AADDR)
+ 80247e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80247e8:	100690ba 	slli	r3,r2,2
+ 80247ec:	008201b4 	movhi	r2,2054
+ 80247f0:	1885883a 	add	r2,r3,r2
+ 80247f4:	10b77017 	ldw	r2,-8768(r2)
+ 80247f8:	10800a17 	ldw	r2,40(r2)
+ 80247fc:	1080200c 	andi	r2,r2,128
+ 8024800:	1000031e 	bne	r2,zero,8024810 <fixup_subnet_mask+0x5c>
+      smask = 0xFF000000L;
+ 8024804:	00bfc034 	movhi	r2,65280
+ 8024808:	e0bfff15 	stw	r2,-4(fp)
+ 802480c:	00001b06 	br	802487c <fixup_subnet_mask+0xc8>
+   else if((nets[netnum]->n_ipaddr & BMASK) == BADDR)
+ 8024810:	e0bffe17 	ldw	r2,-8(fp)
+ 8024814:	100690ba 	slli	r3,r2,2
+ 8024818:	008201b4 	movhi	r2,2054
+ 802481c:	1885883a 	add	r2,r3,r2
+ 8024820:	10b77017 	ldw	r2,-8768(r2)
+ 8024824:	10800a17 	ldw	r2,40(r2)
+ 8024828:	1080300c 	andi	r2,r2,192
+ 802482c:	10802018 	cmpnei	r2,r2,128
+ 8024830:	1000031e 	bne	r2,zero,8024840 <fixup_subnet_mask+0x8c>
+      smask = 0xFFFF0000L;
+ 8024834:	00bffff4 	movhi	r2,65535
+ 8024838:	e0bfff15 	stw	r2,-4(fp)
+ 802483c:	00000f06 	br	802487c <fixup_subnet_mask+0xc8>
+   else if((nets[netnum]->n_ipaddr & CMASK) == CADDR)
+ 8024840:	e0bffe17 	ldw	r2,-8(fp)
+ 8024844:	100690ba 	slli	r3,r2,2
+ 8024848:	008201b4 	movhi	r2,2054
+ 802484c:	1885883a 	add	r2,r3,r2
+ 8024850:	10b77017 	ldw	r2,-8768(r2)
+ 8024854:	10800a17 	ldw	r2,40(r2)
+ 8024858:	1080380c 	andi	r2,r2,224
+ 802485c:	10803018 	cmpnei	r2,r2,192
+ 8024860:	1000031e 	bne	r2,zero,8024870 <fixup_subnet_mask+0xbc>
+      smask = 0xFFFFFF00L;
+ 8024864:	00bfc004 	movi	r2,-256
+ 8024868:	e0bfff15 	stw	r2,-4(fp)
+ 802486c:	00000306 	br	802487c <fixup_subnet_mask+0xc8>
+   else
+   {
+      dtrap();    /* bad logic or setup values */
+ 8024870:	8028cd40 	call	8028cd4 <dtrap>
+      smask = 0xFFFFFF00L;
+ 8024874:	00bfc004 	movi	r2,-256
+ 8024878:	e0bfff15 	stw	r2,-4(fp)
+   }
+   nets[netnum]->snmask = htonl(smask);
+ 802487c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024880:	1006d63a 	srli	r3,r2,24
+ 8024884:	e0bfff17 	ldw	r2,-4(fp)
+ 8024888:	1004d23a 	srli	r2,r2,8
+ 802488c:	10bfc00c 	andi	r2,r2,65280
+ 8024890:	1886b03a 	or	r3,r3,r2
+ 8024894:	e0bfff17 	ldw	r2,-4(fp)
+ 8024898:	1004923a 	slli	r2,r2,8
+ 802489c:	10803fec 	andhi	r2,r2,255
+ 80248a0:	1888b03a 	or	r4,r3,r2
+ 80248a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80248a8:	1006963a 	slli	r3,r2,24
+ 80248ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80248b0:	100a90ba 	slli	r5,r2,2
+ 80248b4:	008201b4 	movhi	r2,2054
+ 80248b8:	2885883a 	add	r2,r5,r2
+ 80248bc:	10b77017 	ldw	r2,-8768(r2)
+ 80248c0:	20c6b03a 	or	r3,r4,r3
+ 80248c4:	10c00c15 	stw	r3,48(r2)
+ 80248c8:	00000106 	br	80248d0 <fixup_subnet_mask+0x11c>
+      return;
+ 80248cc:	0001883a 	nop
+}
+ 80248d0:	e037883a 	mov	sp,fp
+ 80248d4:	dfc00117 	ldw	ra,4(sp)
+ 80248d8:	df000017 	ldw	fp,0(sp)
+ 80248dc:	dec00204 	addi	sp,sp,8
+ 80248e0:	f800283a 	ret
+
+080248e4 <netclose>:
+ * RETURNS: 
+ */
+
+void
+netclose()
+{
+ 80248e4:	defffc04 	addi	sp,sp,-16
+ 80248e8:	dfc00315 	stw	ra,12(sp)
+ 80248ec:	df000215 	stw	fp,8(sp)
+ 80248f0:	df000204 	addi	fp,sp,8
+   NET ifp;
+   int index = 0;
+ 80248f4:	e03ffe15 	stw	zero,-8(fp)
+
+#ifdef NPDEBUG
+   if (NDEBUG & INFOMSG)   dprintf("netclose() called\n");
+ 80248f8:	d0a06617 	ldw	r2,-32360(gp)
+ 80248fc:	1080010c 	andi	r2,r2,4
+ 8024900:	10000326 	beq	r2,zero,8024910 <netclose+0x2c>
+ 8024904:	01020174 	movhi	r4,2053
+ 8024908:	2126c404 	addi	r4,r4,-25840
+ 802490c:	8002d9c0 	call	8002d9c <puts>
+#endif
+
+   for (ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next)
+ 8024910:	008201b4 	movhi	r2,2054
+ 8024914:	10b6a617 	ldw	r2,-9576(r2)
+ 8024918:	e0bfff15 	stw	r2,-4(fp)
+ 802491c:	00002106 	br	80249a4 <netclose+0xc0>
+   {
+      if (ifp->n_close)
+ 8024920:	e0bfff17 	ldw	r2,-4(fp)
+ 8024924:	10800517 	ldw	r2,20(r2)
+ 8024928:	10000f26 	beq	r2,zero,8024968 <netclose+0x84>
+      {
+         dprintf("netclose: closing iface %s\n", ifp->n_mib->ifDescr);
+ 802492c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024930:	10802717 	ldw	r2,156(r2)
+ 8024934:	10800117 	ldw	r2,4(r2)
+ 8024938:	100b883a 	mov	r5,r2
+ 802493c:	01020174 	movhi	r4,2053
+ 8024940:	2126c904 	addi	r4,r4,-25820
+ 8024944:	8002c780 	call	8002c78 <printf>
+         (*(ifp->n_close))(index++);
+ 8024948:	e0bfff17 	ldw	r2,-4(fp)
+ 802494c:	10c00517 	ldw	r3,20(r2)
+ 8024950:	e0bffe17 	ldw	r2,-8(fp)
+ 8024954:	11000044 	addi	r4,r2,1
+ 8024958:	e13ffe15 	stw	r4,-8(fp)
+ 802495c:	1009883a 	mov	r4,r2
+ 8024960:	183ee83a 	callr	r3
+ 8024964:	00000c06 	br	8024998 <netclose+0xb4>
+      }
+      else
+      {
+#ifdef NPDEBUG
+         if (NDEBUG & INFOMSG) dprintf("net %s: no close routine!\n", ifp->name);
+ 8024968:	d0a06617 	ldw	r2,-32360(gp)
+ 802496c:	1080010c 	andi	r2,r2,4
+ 8024970:	10000626 	beq	r2,zero,802498c <netclose+0xa8>
+ 8024974:	e0bfff17 	ldw	r2,-4(fp)
+ 8024978:	10800104 	addi	r2,r2,4
+ 802497c:	100b883a 	mov	r5,r2
+ 8024980:	01020174 	movhi	r4,2053
+ 8024984:	2126d004 	addi	r4,r4,-25792
+ 8024988:	8002c780 	call	8002c78 <printf>
+#endif
+         index++;
+ 802498c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024990:	10800044 	addi	r2,r2,1
+ 8024994:	e0bffe15 	stw	r2,-8(fp)
+   for (ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next)
+ 8024998:	e0bfff17 	ldw	r2,-4(fp)
+ 802499c:	10800017 	ldw	r2,0(r2)
+ 80249a0:	e0bfff15 	stw	r2,-4(fp)
+ 80249a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80249a8:	103fdd1e 	bne	r2,zero,8024920 <netclose+0x3c>
+      }
+   }
+}
+ 80249ac:	0001883a 	nop
+ 80249b0:	e037883a 	mov	sp,fp
+ 80249b4:	dfc00117 	ldw	ra,4(sp)
+ 80249b8:	df000017 	ldw	fp,0(sp)
+ 80249bc:	dec00204 	addi	sp,sp,8
+ 80249c0:	f800283a 	ret
+
+080249c4 <pktdemux>:
+ * RETURNS: void
+ */
+
+void
+pktdemux()
+{
+ 80249c4:	defff904 	addi	sp,sp,-28
+ 80249c8:	dfc00615 	stw	ra,24(sp)
+ 80249cc:	df000515 	stw	fp,20(sp)
+ 80249d0:	df000504 	addi	fp,sp,20
+   NET      ifc;                /* interface packet came from */
+   IFMIB    mib;
+   int      pkts;
+   char *   eth;
+
+   pkts = 0;   /* packets per loop */
+ 80249d4:	e03fff15 	stw	zero,-4(fp)
+
+   while (rcvdq.q_len)
+ 80249d8:	0000d906 	br	8024d40 <pktdemux+0x37c>
+   {
+      /* If we are low on free packets, don't hog CPU cycles */
+      if (pkts++ > bigfreeq.q_len)
+ 80249dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80249e0:	10c00044 	addi	r3,r2,1
+ 80249e4:	e0ffff15 	stw	r3,-4(fp)
+ 80249e8:	00c201b4 	movhi	r3,2054
+ 80249ec:	18f7dd17 	ldw	r3,-8332(r3)
+ 80249f0:	1880020e 	bge	r3,r2,80249fc <pktdemux+0x38>
+      {
+#ifdef SUPERLOOP
+         return;        /* don't hog stack on superloop */
+#else    /* SUPERLOOP */
+         tk_yield(); /* let application tasks process received packets */
+ 80249f4:	8027ce40 	call	8027ce4 <tk_yield>
+         pkts = 0;   /* reset counter */
+ 80249f8:	e03fff15 	stw	zero,-4(fp)
+#endif   /* SUPERLOOP else */
+      }
+
+      /* If we get receive interupt from the net during this
+      lock, the MAC driver needs to wait or reschedule */
+      LOCK_NET_RESOURCE(RXQ_RESID);
+ 80249fc:	01000044 	movi	r4,1
+ 8024a00:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pkt = (PACKET)q_deq(&rcvdq);
+ 8024a04:	010201b4 	movhi	r4,2054
+ 8024a08:	2136ab04 	addi	r4,r4,-9556
+ 8024a0c:	80288d80 	call	80288d8 <getq>
+ 8024a10:	e0bffe15 	stw	r2,-8(fp)
+      UNLOCK_NET_RESOURCE(RXQ_RESID);
+ 8024a14:	01000044 	movi	r4,1
+ 8024a18:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      if (!pkt) panic("pktdemux: got null pkt");
+ 8024a1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024a20:	1000031e 	bne	r2,zero,8024a30 <pktdemux+0x6c>
+ 8024a24:	01020174 	movhi	r4,2053
+ 8024a28:	2126d704 	addi	r4,r4,-25764
+ 8024a2c:	80271780 	call	8027178 <panic>
+      ifc = pkt->net;
+ 8024a30:	e0bffe17 	ldw	r2,-8(fp)
+ 8024a34:	10800617 	ldw	r2,24(r2)
+ 8024a38:	e0bffd15 	stw	r2,-12(fp)
+
+      mib = ifc->n_mib;
+ 8024a3c:	e0bffd17 	ldw	r2,-12(fp)
+ 8024a40:	10802717 	ldw	r2,156(r2)
+ 8024a44:	e0bffc15 	stw	r2,-16(fp)
+      /* maintain mib stats for unicast and broadcast */
+      if (isbcast(ifc, (u_char*)pkt->nb_buff + ETHHDR_BIAS))
+ 8024a48:	e0bffe17 	ldw	r2,-8(fp)
+ 8024a4c:	10800117 	ldw	r2,4(r2)
+ 8024a50:	10800084 	addi	r2,r2,2
+ 8024a54:	100b883a 	mov	r5,r2
+ 8024a58:	e13ffd17 	ldw	r4,-12(fp)
+ 8024a5c:	80240f40 	call	80240f4 <isbcast>
+ 8024a60:	10000626 	beq	r2,zero,8024a7c <pktdemux+0xb8>
+         mib->ifInNUcastPkts++;
+ 8024a64:	e0bffc17 	ldw	r2,-16(fp)
+ 8024a68:	10800b17 	ldw	r2,44(r2)
+ 8024a6c:	10c00044 	addi	r3,r2,1
+ 8024a70:	e0bffc17 	ldw	r2,-16(fp)
+ 8024a74:	10c00b15 	stw	r3,44(r2)
+ 8024a78:	00000506 	br	8024a90 <pktdemux+0xcc>
+      else
+         mib->ifInUcastPkts++;
+ 8024a7c:	e0bffc17 	ldw	r2,-16(fp)
+ 8024a80:	10800a17 	ldw	r2,40(r2)
+ 8024a84:	10c00044 	addi	r3,r2,1
+ 8024a88:	e0bffc17 	ldw	r2,-16(fp)
+ 8024a8c:	10c00a15 	stw	r3,40(r2)
+
+      if(mib->ifAdminStatus == NI_DOWN)
+ 8024a90:	e0bffc17 	ldw	r2,-16(fp)
+ 8024a94:	10800617 	ldw	r2,24(r2)
+ 8024a98:	10800098 	cmpnei	r2,r2,2
+ 8024a9c:	10000c1e 	bne	r2,zero,8024ad0 <pktdemux+0x10c>
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024aa0:	01000084 	movi	r4,2
+ 8024aa4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);  /* dump packet from downed interface */
+ 8024aa8:	e13ffe17 	ldw	r4,-8(fp)
+ 8024aac:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024ab0:	01000084 	movi	r4,2
+ 8024ab4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         mib->ifInDiscards++;
+ 8024ab8:	e0bffc17 	ldw	r2,-16(fp)
+ 8024abc:	10800c17 	ldw	r2,48(r2)
+ 8024ac0:	10c00044 	addi	r3,r2,1
+ 8024ac4:	e0bffc17 	ldw	r2,-16(fp)
+ 8024ac8:	10c00c15 	stw	r3,48(r2)
+         continue;      /* next packet */
+ 8024acc:	00009c06 	br	8024d40 <pktdemux+0x37c>
+      }
+
+#ifdef NPDEBUG
+      if (*(pkt->nb_buff - ALIGN_TYPE) != 'M' ||
+ 8024ad0:	e0bffe17 	ldw	r2,-8(fp)
+ 8024ad4:	10800117 	ldw	r2,4(r2)
+ 8024ad8:	10bfff04 	addi	r2,r2,-4
+ 8024adc:	10800003 	ldbu	r2,0(r2)
+ 8024ae0:	10803fcc 	andi	r2,r2,255
+ 8024ae4:	1080201c 	xori	r2,r2,128
+ 8024ae8:	10bfe004 	addi	r2,r2,-128
+ 8024aec:	10801358 	cmpnei	r2,r2,77
+ 8024af0:	10000b1e 	bne	r2,zero,8024b20 <pktdemux+0x15c>
+          *(pkt->nb_buff + pkt->nb_blen) != 'M')
+ 8024af4:	e0bffe17 	ldw	r2,-8(fp)
+ 8024af8:	10c00117 	ldw	r3,4(r2)
+ 8024afc:	e0bffe17 	ldw	r2,-8(fp)
+ 8024b00:	10800217 	ldw	r2,8(r2)
+ 8024b04:	1885883a 	add	r2,r3,r2
+ 8024b08:	10800003 	ldbu	r2,0(r2)
+      if (*(pkt->nb_buff - ALIGN_TYPE) != 'M' ||
+ 8024b0c:	10803fcc 	andi	r2,r2,255
+ 8024b10:	1080201c 	xori	r2,r2,128
+ 8024b14:	10bfe004 	addi	r2,r2,-128
+ 8024b18:	10801360 	cmpeqi	r2,r2,77
+ 8024b1c:	1000041e 	bne	r2,zero,8024b30 <pktdemux+0x16c>
+      {
+         dtrap();
+ 8024b20:	8028cd40 	call	8028cd4 <dtrap>
+         panic("pktdemux: corrupt pkt");
+ 8024b24:	01020174 	movhi	r4,2053
+ 8024b28:	2126dd04 	addi	r4,r4,-25740
+ 8024b2c:	80271780 	call	8027178 <panic>
+         }
+      }
+#endif   /* LOSSY_IO */
+
+      /* see if driver set pkt->nb_prot and pkt->type */
+      if((ifc->n_flags & NF_NBPROT) == 0)
+ 8024b30:	e0bffd17 	ldw	r2,-12(fp)
+ 8024b34:	10802a17 	ldw	r2,168(r2)
+ 8024b38:	1080020c 	andi	r2,r2,8
+ 8024b3c:	1000491e 	bne	r2,zero,8024c64 <pktdemux+0x2a0>
+          * probably the right thing to do, but because of this historic
+          * inconsistency we don't try to fix it here - the longer size
+          * turns out to be harmless since the IP layer fixes the size
+          * based on the IP header length field.
+          */
+         switch(ifc->n_mib->ifType)
+ 8024b40:	e0bffd17 	ldw	r2,-12(fp)
+ 8024b44:	10802717 	ldw	r2,156(r2)
+ 8024b48:	10800217 	ldw	r2,8(r2)
+ 8024b4c:	10800198 	cmpnei	r2,r2,6
+ 8024b50:	1000361e 	bne	r2,zero,8024c2c <pktdemux+0x268>
+         {
+         case ETHERNET:
+            /* get pointer to ethernet header */
+            eth = (pkt->nb_buff + ETHHDR_BIAS);
+ 8024b54:	e0bffe17 	ldw	r2,-8(fp)
+ 8024b58:	10800117 	ldw	r2,4(r2)
+ 8024b5c:	10800084 	addi	r2,r2,2
+ 8024b60:	e0bffb15 	stw	r2,-20(fp)
+            {
+               pkt->type = htons((unshort)ET_TYPE_GET(eth));
+               pkt->nb_prot = pkt->nb_buff + ETHHDR_SIZE;
+            }
+#else
+            pkt->type = htons((unshort)ET_TYPE_GET(eth));
+ 8024b64:	e0bffb17 	ldw	r2,-20(fp)
+ 8024b68:	10800304 	addi	r2,r2,12
+ 8024b6c:	10800003 	ldbu	r2,0(r2)
+ 8024b70:	10803fcc 	andi	r2,r2,255
+ 8024b74:	1080201c 	xori	r2,r2,128
+ 8024b78:	10bfe004 	addi	r2,r2,-128
+ 8024b7c:	1004923a 	slli	r2,r2,8
+ 8024b80:	1007883a 	mov	r3,r2
+ 8024b84:	e0bffb17 	ldw	r2,-20(fp)
+ 8024b88:	10800344 	addi	r2,r2,13
+ 8024b8c:	10800003 	ldbu	r2,0(r2)
+ 8024b90:	10803fcc 	andi	r2,r2,255
+ 8024b94:	1080201c 	xori	r2,r2,128
+ 8024b98:	10bfe004 	addi	r2,r2,-128
+ 8024b9c:	10803fcc 	andi	r2,r2,255
+ 8024ba0:	1885883a 	add	r2,r3,r2
+ 8024ba4:	10bfffcc 	andi	r2,r2,65535
+ 8024ba8:	1004d23a 	srli	r2,r2,8
+ 8024bac:	1007883a 	mov	r3,r2
+ 8024bb0:	e0bffb17 	ldw	r2,-20(fp)
+ 8024bb4:	10800304 	addi	r2,r2,12
+ 8024bb8:	10800003 	ldbu	r2,0(r2)
+ 8024bbc:	10803fcc 	andi	r2,r2,255
+ 8024bc0:	1080201c 	xori	r2,r2,128
+ 8024bc4:	10bfe004 	addi	r2,r2,-128
+ 8024bc8:	1004923a 	slli	r2,r2,8
+ 8024bcc:	1009883a 	mov	r4,r2
+ 8024bd0:	e0bffb17 	ldw	r2,-20(fp)
+ 8024bd4:	10800344 	addi	r2,r2,13
+ 8024bd8:	10800003 	ldbu	r2,0(r2)
+ 8024bdc:	10803fcc 	andi	r2,r2,255
+ 8024be0:	1080201c 	xori	r2,r2,128
+ 8024be4:	10bfe004 	addi	r2,r2,-128
+ 8024be8:	10803fcc 	andi	r2,r2,255
+ 8024bec:	2085883a 	add	r2,r4,r2
+ 8024bf0:	10bfffcc 	andi	r2,r2,65535
+ 8024bf4:	1004923a 	slli	r2,r2,8
+ 8024bf8:	1884b03a 	or	r2,r3,r2
+ 8024bfc:	1007883a 	mov	r3,r2
+ 8024c00:	e0bffe17 	ldw	r2,-8(fp)
+ 8024c04:	10c0080d 	sth	r3,32(r2)
+            pkt->nb_prot = pkt->nb_buff + pkt->net->n_lnh;
+ 8024c08:	e0bffe17 	ldw	r2,-8(fp)
+ 8024c0c:	10800117 	ldw	r2,4(r2)
+ 8024c10:	e0fffe17 	ldw	r3,-8(fp)
+ 8024c14:	18c00617 	ldw	r3,24(r3)
+ 8024c18:	18c00817 	ldw	r3,32(r3)
+ 8024c1c:	10c7883a 	add	r3,r2,r3
+ 8024c20:	e0bffe17 	ldw	r2,-8(fp)
+ 8024c24:	10c00315 	stw	r3,12(r2)
+#endif   /* IEEE_802_3 */
+            break;
+ 8024c28:	00000f06 	br	8024c68 <pktdemux+0x2a4>
+         case PPPOE:
+            /* do not change type yet, for PPPoE */
+            break;
+#endif   /* USE_PPPOE */
+         default:    /* driver bug? */
+            dprintf("pktdemux: bad Iface type %ld\n",ifc->n_mib->ifType);
+ 8024c2c:	e0bffd17 	ldw	r2,-12(fp)
+ 8024c30:	10802717 	ldw	r2,156(r2)
+ 8024c34:	10800217 	ldw	r2,8(r2)
+ 8024c38:	100b883a 	mov	r5,r2
+ 8024c3c:	01020174 	movhi	r4,2053
+ 8024c40:	2126e304 	addi	r4,r4,-25716
+ 8024c44:	8002c780 	call	8002c78 <printf>
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024c48:	01000084 	movi	r4,2
+ 8024c4c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(pkt);
+ 8024c50:	e13ffe17 	ldw	r4,-8(fp)
+ 8024c54:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024c58:	01000084 	movi	r4,2
+ 8024c5c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            continue;
+ 8024c60:	00003706 	br	8024d40 <pktdemux+0x37c>
+         }
+      }
+ 8024c64:	0001883a 	nop
+
+      /* pkt->nb_prot and pkt->type are now set. pass pkt to upper layer */
+      switch(pkt->type)
+ 8024c68:	e0bffe17 	ldw	r2,-8(fp)
+ 8024c6c:	1080080b 	ldhu	r2,32(r2)
+ 8024c70:	10bfffcc 	andi	r2,r2,65535
+ 8024c74:	10c00220 	cmpeqi	r3,r2,8
+ 8024c78:	1800031e 	bne	r3,zero,8024c88 <pktdemux+0x2c4>
+ 8024c7c:	10818220 	cmpeqi	r2,r2,1544
+ 8024c80:	1000081e 	bne	r2,zero,8024ca4 <pktdemux+0x2e0>
+ 8024c84:	00000e06 	br	8024cc0 <pktdemux+0x2fc>
+      {
+      case IPTP:     /* IP type */
+         LOCK_NET_RESOURCE(NET_RESID);
+ 8024c88:	0009883a 	mov	r4,zero
+ 8024c8c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+#ifdef SHARED_IPADDRS
+         add_share_route(pkt);
+#endif /* SHARED_IPADDRS */
+#ifdef IP_V4
+         ip_rcv(pkt);
+ 8024c90:	e13ffe17 	ldw	r4,-8(fp)
+ 8024c94:	803b6680 	call	803b668 <ip_rcv>
+            /* don't care, it's IPv4 */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif
+		UNLOCK_NET_RESOURCE(NET_RESID);
+ 8024c98:	0009883a 	mov	r4,zero
+ 8024c9c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         break;
+ 8024ca0:	00002606 	br	8024d3c <pktdemux+0x378>
+#ifdef INCLUDE_ARP
+      case ARPTP:       /* ARP type */
+         LOCK_NET_RESOURCE(NET_RESID);
+ 8024ca4:	0009883a 	mov	r4,zero
+ 8024ca8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         arprcv(pkt);
+ 8024cac:	e13ffe17 	ldw	r4,-8(fp)
+ 8024cb0:	80238e40 	call	80238e4 <arprcv>
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 8024cb4:	0009883a 	mov	r4,zero
+ 8024cb8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         break;
+ 8024cbc:	00001f06 	br	8024d3c <pktdemux+0x378>
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         break;
+#endif
+      default:
+#ifdef NPDEBUG
+         if (NDEBUG & UPCTRACE)
+ 8024cc0:	d0a06617 	ldw	r2,-32360(gp)
+ 8024cc4:	1081000c 	andi	r2,r2,1024
+ 8024cc8:	10001026 	beq	r2,zero,8024d0c <pktdemux+0x348>
+            dprintf("pktdemux: bad pkt type 0x%04x\n", ntohs(pkt->type));
+ 8024ccc:	e0bffe17 	ldw	r2,-8(fp)
+ 8024cd0:	1080080b 	ldhu	r2,32(r2)
+ 8024cd4:	10bfffcc 	andi	r2,r2,65535
+ 8024cd8:	1004d23a 	srli	r2,r2,8
+ 8024cdc:	10bfffcc 	andi	r2,r2,65535
+ 8024ce0:	10c03fcc 	andi	r3,r2,255
+ 8024ce4:	e0bffe17 	ldw	r2,-8(fp)
+ 8024ce8:	1080080b 	ldhu	r2,32(r2)
+ 8024cec:	10bfffcc 	andi	r2,r2,65535
+ 8024cf0:	1004923a 	slli	r2,r2,8
+ 8024cf4:	10bfffcc 	andi	r2,r2,65535
+ 8024cf8:	1884b03a 	or	r2,r3,r2
+ 8024cfc:	100b883a 	mov	r5,r2
+ 8024d00:	01020174 	movhi	r4,2053
+ 8024d04:	2126eb04 	addi	r4,r4,-25684
+ 8024d08:	8002c780 	call	8002c78 <printf>
+#endif   /* NPDEBUG */
+         ifc->n_mib->ifInUnknownProtos++;
+ 8024d0c:	e0bffd17 	ldw	r2,-12(fp)
+ 8024d10:	10802717 	ldw	r2,156(r2)
+ 8024d14:	10c00e17 	ldw	r3,56(r2)
+ 8024d18:	18c00044 	addi	r3,r3,1
+ 8024d1c:	10c00e15 	stw	r3,56(r2)
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024d20:	01000084 	movi	r4,2
+ 8024d24:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);           /* return to free buffer */
+ 8024d28:	e13ffe17 	ldw	r4,-8(fp)
+ 8024d2c:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024d30:	01000084 	movi	r4,2
+ 8024d34:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         break;
+ 8024d38:	0001883a 	nop
+      }
+      continue;
+ 8024d3c:	0001883a 	nop
+   while (rcvdq.q_len)
+ 8024d40:	008201b4 	movhi	r2,2054
+ 8024d44:	10b6ad17 	ldw	r2,-9548(r2)
+ 8024d48:	103f241e 	bne	r2,zero,80249dc <pktdemux+0x18>
+   }
+}
+ 8024d4c:	0001883a 	nop
+ 8024d50:	e037883a 	mov	sp,fp
+ 8024d54:	dfc00117 	ldw	ra,4(sp)
+ 8024d58:	df000017 	ldw	fp,0(sp)
+ 8024d5c:	dec00204 	addi	sp,sp,8
+ 8024d60:	f800283a 	ret
+
+08024d64 <c_older>:
+ * RETURNS: the older of the two passed tick counts
+ */
+
+u_long
+c_older(u_long ct1, u_long ct2)
+{
+ 8024d64:	defffd04 	addi	sp,sp,-12
+ 8024d68:	df000215 	stw	fp,8(sp)
+ 8024d6c:	df000204 	addi	fp,sp,8
+ 8024d70:	e13fff15 	stw	r4,-4(fp)
+ 8024d74:	e17ffe15 	stw	r5,-8(fp)
+
+   if (!(cticks & 0x80000000) || /* cticks has not wrapped recently, or */
+ 8024d78:	d0a07d17 	ldw	r2,-32268(gp)
+ 8024d7c:	10000c0e 	bge	r2,zero,8024db0 <c_older+0x4c>
+       (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */
+ 8024d80:	d0e07d17 	ldw	r3,-32268(gp)
+   if (!(cticks & 0x80000000) || /* cticks has not wrapped recently, or */
+ 8024d84:	e0bfff17 	ldw	r2,-4(fp)
+ 8024d88:	18800336 	bltu	r3,r2,8024d98 <c_older+0x34>
+       (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */
+ 8024d8c:	d0e07d17 	ldw	r3,-32268(gp)
+ 8024d90:	e0bffe17 	ldw	r2,-8(fp)
+ 8024d94:	1880062e 	bgeu	r3,r2,8024db0 <c_older+0x4c>
+       (ct1 >= cticks && ct2 >= cticks))   /* both are above cticks */
+ 8024d98:	d0a07d17 	ldw	r2,-32268(gp)
+       (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */
+ 8024d9c:	e0ffff17 	ldw	r3,-4(fp)
+ 8024da0:	18800a36 	bltu	r3,r2,8024dcc <c_older+0x68>
+       (ct1 >= cticks && ct2 >= cticks))   /* both are above cticks */
+ 8024da4:	d0a07d17 	ldw	r2,-32268(gp)
+ 8024da8:	e0fffe17 	ldw	r3,-8(fp)
+ 8024dac:	18800736 	bltu	r3,r2,8024dcc <c_older+0x68>
+   {
+      if (ct1 < ct2)
+ 8024db0:	e0ffff17 	ldw	r3,-4(fp)
+ 8024db4:	e0bffe17 	ldw	r2,-8(fp)
+ 8024db8:	1880022e 	bgeu	r3,r2,8024dc4 <c_older+0x60>
+         return(ct1);      /* then smaller is oldest */
+ 8024dbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8024dc0:	00000806 	br	8024de4 <c_older+0x80>
+      else 
+         return(ct2);
+ 8024dc4:	e0bffe17 	ldw	r2,-8(fp)
+ 8024dc8:	00000606 	br	8024de4 <c_older+0x80>
+   }
+
+   /* else one is less than cticks, and one is greater.
+   the larger value is then the oldest */
+   if (ct1 >= ct2)
+ 8024dcc:	e0ffff17 	ldw	r3,-4(fp)
+ 8024dd0:	e0bffe17 	ldw	r2,-8(fp)
+ 8024dd4:	18800236 	bltu	r3,r2,8024de0 <c_older+0x7c>
+      return(ct1);
+ 8024dd8:	e0bfff17 	ldw	r2,-4(fp)
+ 8024ddc:	00000106 	br	8024de4 <c_older+0x80>
+   else
+      return(ct2);
+ 8024de0:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8024de4:	e037883a 	mov	sp,fp
+ 8024de8:	df000017 	ldw	fp,0(sp)
+ 8024dec:	dec00104 	addi	sp,sp,4
+ 8024df0:	f800283a 	ret
+
+08024df4 <ip2mac>:
+ */
+
+int
+ip2mac(PACKET pkt,         /* the packet itself, all set but for dest MAC address */
+   ip_addr  dest_ip)    /* the IP host or gateway to get MAC addr for */
+{
+ 8024df4:	defffb04 	addi	sp,sp,-20
+ 8024df8:	dfc00415 	stw	ra,16(sp)
+ 8024dfc:	df000315 	stw	fp,12(sp)
+ 8024e00:	df000304 	addi	fp,sp,12
+ 8024e04:	e13ffe15 	stw	r4,-8(fp)
+ 8024e08:	e17ffd15 	stw	r5,-12(fp)
+   IFMIB ifmib = pkt->net->n_mib;   /* mib info for this interface */
+ 8024e0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024e10:	10800617 	ldw	r2,24(r2)
+ 8024e14:	10802717 	ldw	r2,156(r2)
+ 8024e18:	e0bfff15 	stw	r2,-4(fp)
+
+   /* Always punt if iface ifAdminStatus is DOWN. ifOperStatus may 
+    * be down too, but our packet may be the event required to bring 
+    * it up - so don't worry about ifOperStatus here.
+    */
+   if(ifmib->ifAdminStatus == NI_DOWN)
+ 8024e1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e20:	10800617 	ldw	r2,24(r2)
+ 8024e24:	10800098 	cmpnei	r2,r2,2
+ 8024e28:	1000081e 	bne	r2,zero,8024e4c <ip2mac+0x58>
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024e2c:	01000084 	movi	r4,2
+ 8024e30:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);
+ 8024e34:	e13ffe17 	ldw	r4,-8(fp)
+ 8024e38:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024e3c:	01000084 	movi	r4,2
+ 8024e40:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return(ENP_NO_ROUTE);
+ 8024e44:	00bff7c4 	movi	r2,-33
+ 8024e48:	00004806 	br	8024f6c <ip2mac+0x178>
+         return ENP_NOBUFFER;
+   }
+#endif   /* LINKED_PKTS */
+
+   /* some interfaces (ie SLIP) just get the raw IP frame - no ARP needed */
+   if ((pkt->net->n_lnh == 0) ||    /* no MAC header */
+ 8024e4c:	e0bffe17 	ldw	r2,-8(fp)
+ 8024e50:	10800617 	ldw	r2,24(r2)
+ 8024e54:	10800817 	ldw	r2,32(r2)
+ 8024e58:	10000826 	beq	r2,zero,8024e7c <ip2mac+0x88>
+       (ifmib->ifType == PPP) ||     /* or PPP or SLIP... */
+ 8024e5c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e60:	10800217 	ldw	r2,8(r2)
+   if ((pkt->net->n_lnh == 0) ||    /* no MAC header */
+ 8024e64:	108005e0 	cmpeqi	r2,r2,23
+ 8024e68:	1000041e 	bne	r2,zero,8024e7c <ip2mac+0x88>
+       (ifmib->ifType == SLIP))
+ 8024e6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e70:	10800217 	ldw	r2,8(r2)
+       (ifmib->ifType == PPP) ||     /* or PPP or SLIP... */
+ 8024e74:	10800718 	cmpnei	r2,r2,28
+ 8024e78:	1000291e 	bne	r2,zero,8024f20 <ip2mac+0x12c>
+   {
+      ifmib->ifOutUcastPkts++;   /* maintain MIB counters */
+ 8024e7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e80:	10801017 	ldw	r2,64(r2)
+ 8024e84:	10c00044 	addi	r3,r2,1
+ 8024e88:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e8c:	10c01015 	stw	r3,64(r2)
+      ifmib->ifOutOctets += pkt->nb_plen;
+ 8024e90:	e0bfff17 	ldw	r2,-4(fp)
+ 8024e94:	10c00f17 	ldw	r3,60(r2)
+ 8024e98:	e0bffe17 	ldw	r2,-8(fp)
+ 8024e9c:	10800417 	ldw	r2,16(r2)
+ 8024ea0:	1887883a 	add	r3,r3,r2
+ 8024ea4:	e0bfff17 	ldw	r2,-4(fp)
+ 8024ea8:	10c00f15 	stw	r3,60(r2)
+
+      /* send packet on media */
+      if (pkt->net->pkt_send) /* favor using packet send */
+ 8024eac:	e0bffe17 	ldw	r2,-8(fp)
+ 8024eb0:	10800617 	ldw	r2,24(r2)
+ 8024eb4:	10800417 	ldw	r2,16(r2)
+ 8024eb8:	10000626 	beq	r2,zero,8024ed4 <ip2mac+0xe0>
+         pkt->net->pkt_send(pkt);   /* pkt will be freed by MAC code */
+ 8024ebc:	e0bffe17 	ldw	r2,-8(fp)
+ 8024ec0:	10800617 	ldw	r2,24(r2)
+ 8024ec4:	10800417 	ldw	r2,16(r2)
+ 8024ec8:	e13ffe17 	ldw	r4,-8(fp)
+ 8024ecc:	103ee83a 	callr	r2
+ 8024ed0:	00001106 	br	8024f18 <ip2mac+0x124>
+      else  /* no packet send; try raw send */
+      {
+         pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen);
+ 8024ed4:	e0bffe17 	ldw	r2,-8(fp)
+ 8024ed8:	10800617 	ldw	r2,24(r2)
+ 8024edc:	10800317 	ldw	r2,12(r2)
+ 8024ee0:	e0fffe17 	ldw	r3,-8(fp)
+ 8024ee4:	19000617 	ldw	r4,24(r3)
+ 8024ee8:	e0fffe17 	ldw	r3,-8(fp)
+ 8024eec:	19400317 	ldw	r5,12(r3)
+ 8024ef0:	e0fffe17 	ldw	r3,-8(fp)
+ 8024ef4:	18c00417 	ldw	r3,16(r3)
+ 8024ef8:	180d883a 	mov	r6,r3
+ 8024efc:	103ee83a 	callr	r2
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024f00:	01000084 	movi	r4,2
+ 8024f04:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);
+ 8024f08:	e13ffe17 	ldw	r4,-8(fp)
+ 8024f0c:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024f10:	01000084 	movi	r4,2
+ 8024f14:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      }
+      return(SUCCESS);
+ 8024f18:	0005883a 	mov	r2,zero
+ 8024f1c:	00001306 	br	8024f6c <ip2mac+0x178>
+   }
+
+   /* don't allow unicast sends if NIC iface has no IP address. This
+    * is to prevent DHCP clients from sending prior to assignment.
+    */
+   if (pkt->net->n_ipaddr == 0L)
+ 8024f20:	e0bffe17 	ldw	r2,-8(fp)
+ 8024f24:	10800617 	ldw	r2,24(r2)
+ 8024f28:	10800a17 	ldw	r2,40(r2)
+ 8024f2c:	10000c1e 	bne	r2,zero,8024f60 <ip2mac+0x16c>
+   {
+      if (pkt->fhost != 0xFFFFFFFF) /* check for broadcast packet */
+ 8024f30:	e0bffe17 	ldw	r2,-8(fp)
+ 8024f34:	10800717 	ldw	r2,28(r2)
+ 8024f38:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8024f3c:	1000081e 	bne	r2,zero,8024f60 <ip2mac+0x16c>
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024f40:	01000084 	movi	r4,2
+ 8024f44:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);
+ 8024f48:	e13ffe17 	ldw	r4,-8(fp)
+ 8024f4c:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8024f50:	01000084 	movi	r4,2
+ 8024f54:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return ENP_SENDERR;
+ 8024f58:	00bff884 	movi	r2,-30
+ 8024f5c:	00000306 	br	8024f6c <ip2mac+0x178>
+      }
+   }
+
+#ifdef INCLUDE_ARP   /* must be ethernet or token ring */
+   return(send_via_arp(pkt, dest_ip));
+ 8024f60:	e17ffd17 	ldw	r5,-12(fp)
+ 8024f64:	e13ffe17 	ldw	r4,-8(fp)
+ 8024f68:	8023b480 	call	8023b48 <send_via_arp>
+#else
+   dtrap();    /* Bad option combination? */
+   return ENP_NO_IFACE; /* sent to unknown interface type */
+#endif   /* INCLUDE_ARP */
+}
+ 8024f6c:	e037883a 	mov	sp,fp
+ 8024f70:	dfc00117 	ldw	ra,4(sp)
+ 8024f74:	df000017 	ldw	fp,0(sp)
+ 8024f78:	dec00204 	addi	sp,sp,8
+ 8024f7c:	f800283a 	ret
+
+08024f80 <ip_startup>:
+ * RETURNS: returns NULL if OK, or text of an error message 
+ */
+
+char *   
+ip_startup()
+{
+ 8024f80:	defffc04 	addi	sp,sp,-16
+ 8024f84:	dfc00315 	stw	ra,12(sp)
+ 8024f88:	df000215 	stw	fp,8(sp)
+ 8024f8c:	df000204 	addi	fp,sp,8
+   int   e; /* error holder */
+   int   i;
+
+   /* thread nets[] and attach mib data to nets[] arrays */
+   for (i = 0; i < STATIC_NETS; i++)
+ 8024f90:	e03fff15 	stw	zero,-4(fp)
+ 8024f94:	00002206 	br	8025020 <ip_startup+0xa0>
+   {
+      nets[i] = &netstatic[i];   /* set up array of pointers */
+ 8024f98:	e0bfff17 	ldw	r2,-4(fp)
+ 8024f9c:	10c03024 	muli	r3,r2,192
+ 8024fa0:	008201b4 	movhi	r2,2054
+ 8024fa4:	10b6b004 	addi	r2,r2,-9536
+ 8024fa8:	1887883a 	add	r3,r3,r2
+ 8024fac:	e0bfff17 	ldw	r2,-4(fp)
+ 8024fb0:	100890ba 	slli	r4,r2,2
+ 8024fb4:	008201b4 	movhi	r2,2054
+ 8024fb8:	2085883a 	add	r2,r4,r2
+ 8024fbc:	10f77015 	stw	r3,-8768(r2)
+      nets[i]->n_mib = &nets[i]->mib;   /* set mib pointer */
+ 8024fc0:	e0bfff17 	ldw	r2,-4(fp)
+ 8024fc4:	100690ba 	slli	r3,r2,2
+ 8024fc8:	008201b4 	movhi	r2,2054
+ 8024fcc:	1885883a 	add	r2,r3,r2
+ 8024fd0:	10f77017 	ldw	r3,-8768(r2)
+ 8024fd4:	e0bfff17 	ldw	r2,-4(fp)
+ 8024fd8:	100890ba 	slli	r4,r2,2
+ 8024fdc:	008201b4 	movhi	r2,2054
+ 8024fe0:	2085883a 	add	r2,r4,r2
+ 8024fe4:	10b77017 	ldw	r2,-8768(r2)
+ 8024fe8:	18c01204 	addi	r3,r3,72
+ 8024fec:	10c02715 	stw	r3,156(r2)
+
+      /* add static iface to end of nets list */
+      putq(&netlist, nets[i]);
+ 8024ff0:	e0bfff17 	ldw	r2,-4(fp)
+ 8024ff4:	100690ba 	slli	r3,r2,2
+ 8024ff8:	008201b4 	movhi	r2,2054
+ 8024ffc:	1885883a 	add	r2,r3,r2
+ 8025000:	10b77017 	ldw	r2,-8768(r2)
+ 8025004:	100b883a 	mov	r5,r2
+ 8025008:	010201b4 	movhi	r4,2054
+ 802500c:	2136a604 	addi	r4,r4,-9576
+ 8025010:	80289900 	call	8028990 <putq>
+   for (i = 0; i < STATIC_NETS; i++)
+ 8025014:	e0bfff17 	ldw	r2,-4(fp)
+ 8025018:	10800044 	addi	r2,r2,1
+ 802501c:	e0bfff15 	stw	r2,-4(fp)
+ 8025020:	e0bfff17 	ldw	r2,-4(fp)
+ 8025024:	10800110 	cmplti	r2,r2,4
+ 8025028:	103fdb1e 	bne	r2,zero,8024f98 <ip_startup+0x18>
+   }
+
+   /* call port routine to locate and init network interfaces. */
+   ifNumber = (unsigned)prep_ifaces(ifNumber);
+ 802502c:	d0a06717 	ldw	r2,-32356(gp)
+ 8025030:	1009883a 	mov	r4,r2
+ 8025034:	803c5680 	call	803c568 <prep_ifaces>
+ 8025038:	d0a06715 	stw	r2,-32356(gp)
+
+   if (ifNumber < 1)    /* no static interfaces? */
+ 802503c:	d0a06717 	ldw	r2,-32356(gp)
+ 8025040:	1000031e 	bne	r2,zero,8025050 <ip_startup+0xd0>
+#ifdef DYNAMIC_IFACES
+      /* print a debug message and hope user knows what he's doing */
+      dprintf("unable to find any working interfaces");
+#else /* static ifaces only */
+      /* no static and no dynamic interfaces is probably a bug... */
+      return("unable to find any working interfaces");
+ 8025044:	00820174 	movhi	r2,2053
+ 8025048:	10a6fc04 	addi	r2,r2,-25616
+ 802504c:	00006006 	br	80251d0 <ip_startup+0x250>
+#endif   /* DYNAMIC_IFACES */
+   }
+
+   /* throw away any unused static nets */
+   for (i = ifNumber; i < STATIC_NETS; i++)
+ 8025050:	d0a06717 	ldw	r2,-32356(gp)
+ 8025054:	e0bfff15 	stw	r2,-4(fp)
+ 8025058:	00001106 	br	80250a0 <ip_startup+0x120>
+   {
+      qdel(&netlist, (qp)nets[i]);  /* remove from queue */
+ 802505c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025060:	100690ba 	slli	r3,r2,2
+ 8025064:	008201b4 	movhi	r2,2054
+ 8025068:	1885883a 	add	r2,r3,r2
+ 802506c:	10b77017 	ldw	r2,-8768(r2)
+ 8025070:	100b883a 	mov	r5,r2
+ 8025074:	010201b4 	movhi	r4,2054
+ 8025078:	2136a604 	addi	r4,r4,-9576
+ 802507c:	8028a400 	call	8028a40 <qdel>
+      nets[i] = NULL;               /* remove from array */
+ 8025080:	e0bfff17 	ldw	r2,-4(fp)
+ 8025084:	100690ba 	slli	r3,r2,2
+ 8025088:	008201b4 	movhi	r2,2054
+ 802508c:	1885883a 	add	r2,r3,r2
+ 8025090:	10377015 	stw	zero,-8768(r2)
+   for (i = ifNumber; i < STATIC_NETS; i++)
+ 8025094:	e0bfff17 	ldw	r2,-4(fp)
+ 8025098:	10800044 	addi	r2,r2,1
+ 802509c:	e0bfff15 	stw	r2,-4(fp)
+ 80250a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80250a4:	10800110 	cmplti	r2,r2,4
+ 80250a8:	103fec1e 	bne	r2,zero,802505c <ip_startup+0xdc>
+   /* The sequence of events when initing the net & interface systems 
+    * is very important. Be very carefull about altering the order of 
+    * the following statements. 
+    */
+   /* once these are done, we should call ip_exit before quiting IP */
+   clock_init();           /* start clock system */
+ 80250ac:	8028de00 	call	8028de0 <clock_init>
+   exit_hook(clock_c);
+ 80250b0:	010200f4 	movhi	r4,2051
+ 80250b4:	21238604 	addi	r4,r4,-29160
+ 80250b8:	80251e40 	call	80251e4 <exit_hook>
+
+   e = Netinit();    /* start net interface(s) */
+ 80250bc:	80242e40 	call	80242e4 <Netinit>
+ 80250c0:	e0bffe15 	stw	r2,-8(fp)
+   if (e)
+ 80250c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80250c8:	10000326 	beq	r2,zero,80250d8 <ip_startup+0x158>
+   {
+      return("unable to initialize net");
+ 80250cc:	00820174 	movhi	r2,2053
+ 80250d0:	10a70604 	addi	r2,r2,-25576
+ 80250d4:	00003e06 	br	80251d0 <ip_startup+0x250>
+   }
+
+#ifdef INCLUDE_ARP
+   e = etainit();          /* startup ARP layer */
+ 80250d8:	8022ca40 	call	8022ca4 <etainit>
+ 80250dc:	e0bffe15 	stw	r2,-8(fp)
+   if (e)
+ 80250e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80250e4:	10000426 	beq	r2,zero,80250f8 <ip_startup+0x178>
+   {
+      ip_exit();
+ 80250e8:	802524c0 	call	802524c <ip_exit>
+      return("unable to initialize arp");
+ 80250ec:	00820174 	movhi	r2,2053
+ 80250f0:	10a70d04 	addi	r2,r2,-25548
+ 80250f4:	00003606 	br	80251d0 <ip_startup+0x250>
+   }
+#endif
+
+#ifdef IP_V4
+   e = ip_init();       /* start up IP layer */
+ 80250f8:	803a0700 	call	803a070 <ip_init>
+ 80250fc:	e0bffe15 	stw	r2,-8(fp)
+   if (e)
+ 8025100:	e0bffe17 	ldw	r2,-8(fp)
+ 8025104:	10000426 	beq	r2,zero,8025118 <ip_startup+0x198>
+   {
+      ip_exit();
+ 8025108:	802524c0 	call	802524c <ip_exit>
+      return("unable to initialize IP");
+ 802510c:	00820174 	movhi	r2,2053
+ 8025110:	10a71404 	addi	r2,r2,-25520
+ 8025114:	00002e06 	br	80251d0 <ip_startup+0x250>
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   /* Join the All hosts group on every interface that IP multicast is
+    * supported
+    */
+   e = igmp_init();         /* Initialize igmp */
+ 8025118:	802537c0 	call	802537c <igmp_init>
+ 802511c:	e0bffe15 	stw	r2,-8(fp)
+   if (e)
+ 8025120:	e0bffe17 	ldw	r2,-8(fp)
+ 8025124:	10000326 	beq	r2,zero,8025134 <ip_startup+0x1b4>
+   {
+      ip_exit();
+ 8025128:	802524c0 	call	802524c <ip_exit>
+      return(ipmcfail_str);
+ 802512c:	d0a01217 	ldw	r2,-32696(gp)
+ 8025130:	00002706 	br	80251d0 <ip_startup+0x250>
+   }
+
+   for (i = 0; i < (int)ifNumber; i++)
+ 8025134:	e03fff15 	stw	zero,-4(fp)
+ 8025138:	00001706 	br	8025198 <ip_startup+0x218>
+   {
+      if (nets[i]->n_mcastlist != NULL)
+ 802513c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025140:	100690ba 	slli	r3,r2,2
+ 8025144:	008201b4 	movhi	r2,2054
+ 8025148:	1885883a 	add	r2,r3,r2
+ 802514c:	10b77017 	ldw	r2,-8768(r2)
+ 8025150:	10802b17 	ldw	r2,172(r2)
+ 8025154:	10000d26 	beq	r2,zero,802518c <ip_startup+0x20c>
+         if ((in_addmulti(&igmp_all_hosts_group, nets[i], 4) == NULL))
+ 8025158:	e0bfff17 	ldw	r2,-4(fp)
+ 802515c:	100690ba 	slli	r3,r2,2
+ 8025160:	008201b4 	movhi	r2,2054
+ 8025164:	1885883a 	add	r2,r3,r2
+ 8025168:	10b77017 	ldw	r2,-8768(r2)
+ 802516c:	01800104 	movi	r6,4
+ 8025170:	100b883a 	mov	r5,r2
+ 8025174:	d1206b04 	addi	r4,gp,-32340
+ 8025178:	803c2ac0 	call	803c2ac <in_addmulti>
+ 802517c:	1000031e 	bne	r2,zero,802518c <ip_startup+0x20c>
+      {
+         ip_exit();
+ 8025180:	802524c0 	call	802524c <ip_exit>
+         return(ipmcfail_str);
+ 8025184:	d0a01217 	ldw	r2,-32696(gp)
+ 8025188:	00001106 	br	80251d0 <ip_startup+0x250>
+   for (i = 0; i < (int)ifNumber; i++)
+ 802518c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025190:	10800044 	addi	r2,r2,1
+ 8025194:	e0bfff15 	stw	r2,-4(fp)
+ 8025198:	d0a06717 	ldw	r2,-32356(gp)
+ 802519c:	1007883a 	mov	r3,r2
+ 80251a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80251a4:	10ffe516 	blt	r2,r3,802513c <ip_startup+0x1bc>
+      }
+   }
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */   
+
+#ifdef INCLUDE_TCP
+   e = tcpinit();
+ 80251a8:	803637c0 	call	803637c <tcpinit>
+ 80251ac:	e0bffe15 	stw	r2,-8(fp)
+   if (e)
+ 80251b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80251b4:	10000426 	beq	r2,zero,80251c8 <ip_startup+0x248>
+   {
+      ip_exit();
+ 80251b8:	802524c0 	call	802524c <ip_exit>
+      return("unable to initialize TCP");
+ 80251bc:	00820174 	movhi	r2,2053
+ 80251c0:	10a71a04 	addi	r2,r2,-25496
+ 80251c4:	00000206 	br	80251d0 <ip_startup+0x250>
+   /* setup event map for (UDP and TCP) socket library's events (such as 
+    * those used by tcp_sleep () and tcp_wakeup ()).  These events either 
+    * map into operating system primitives such as events or semaphores, 
+    * or into task suspend and task resume mechanisms.
+    */
+   evtmap_setup ();
+ 80251c8:	803c6100 	call	803c610 <evtmap_setup>
+      return("unable to initialize IP Filter table");
+   else
+      exit_hook(ipf_cleanup);
+#endif
+
+   return(NULL);     /* we got through with no errors */
+ 80251cc:	0005883a 	mov	r2,zero
+}
+ 80251d0:	e037883a 	mov	sp,fp
+ 80251d4:	dfc00117 	ldw	ra,4(sp)
+ 80251d8:	df000017 	ldw	fp,0(sp)
+ 80251dc:	dec00204 	addi	sp,sp,8
+ 80251e0:	f800283a 	ret
+
+080251e4 <exit_hook>:
+ * RETURNS: 
+ */
+
+void
+exit_hook(void (*func)(void))
+{
+ 80251e4:	defffd04 	addi	sp,sp,-12
+ 80251e8:	dfc00215 	stw	ra,8(sp)
+ 80251ec:	df000115 	stw	fp,4(sp)
+ 80251f0:	df000104 	addi	fp,sp,4
+ 80251f4:	e13fff15 	stw	r4,-4(fp)
+   if (nclosers >= (NUMCLOSERS-1))
+ 80251f8:	d0a06817 	ldw	r2,-32352(gp)
+ 80251fc:	10800390 	cmplti	r2,r2,14
+ 8025200:	1000031e 	bne	r2,zero,8025210 <exit_hook+0x2c>
+      panic("exit_hook");
+ 8025204:	01020174 	movhi	r4,2053
+ 8025208:	21272104 	addi	r4,r4,-25468
+ 802520c:	80271780 	call	8027178 <panic>
+
+   closers[++nclosers] = func;
+ 8025210:	d0a06817 	ldw	r2,-32352(gp)
+ 8025214:	10800044 	addi	r2,r2,1
+ 8025218:	d0a06815 	stw	r2,-32352(gp)
+ 802521c:	d0a06817 	ldw	r2,-32352(gp)
+ 8025220:	100890ba 	slli	r4,r2,2
+ 8025224:	e0ffff17 	ldw	r3,-4(fp)
+ 8025228:	00820174 	movhi	r2,2053
+ 802522c:	2085883a 	add	r2,r4,r2
+ 8025230:	10f36e15 	stw	r3,-12872(r2)
+}
+ 8025234:	0001883a 	nop
+ 8025238:	e037883a 	mov	sp,fp
+ 802523c:	dfc00117 	ldw	ra,4(sp)
+ 8025240:	df000017 	ldw	fp,0(sp)
+ 8025244:	dec00204 	addi	sp,sp,8
+ 8025248:	f800283a 	ret
+
+0802524c <ip_exit>:
+ * RETURNS: void
+ */
+
+void
+ip_exit()
+{
+ 802524c:	defffd04 	addi	sp,sp,-12
+ 8025250:	dfc00215 	stw	ra,8(sp)
+ 8025254:	df000115 	stw	fp,4(sp)
+ 8025258:	df000104 	addi	fp,sp,4
+   int   n;
+
+   for (n=nclosers; n; n--)
+ 802525c:	d0a06817 	ldw	r2,-32352(gp)
+ 8025260:	e0bfff15 	stw	r2,-4(fp)
+ 8025264:	00001d06 	br	80252dc <ip_exit+0x90>
+   {
+#ifdef NPDEBUG
+      dprintf("ip_exit: calling func %p\n", closers[n]);
+ 8025268:	e0bfff17 	ldw	r2,-4(fp)
+ 802526c:	100690ba 	slli	r3,r2,2
+ 8025270:	00820174 	movhi	r2,2053
+ 8025274:	1885883a 	add	r2,r3,r2
+ 8025278:	10b36e17 	ldw	r2,-12872(r2)
+ 802527c:	100b883a 	mov	r5,r2
+ 8025280:	01020174 	movhi	r4,2053
+ 8025284:	21272404 	addi	r4,r4,-25456
+ 8025288:	8002c780 	call	8002c78 <printf>
+#endif
+      if(closers[n])
+ 802528c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025290:	100690ba 	slli	r3,r2,2
+ 8025294:	00820174 	movhi	r2,2053
+ 8025298:	1885883a 	add	r2,r3,r2
+ 802529c:	10b36e17 	ldw	r2,-12872(r2)
+ 80252a0:	10000b26 	beq	r2,zero,80252d0 <ip_exit+0x84>
+      {
+         (*closers[n])();
+ 80252a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80252a8:	100690ba 	slli	r3,r2,2
+ 80252ac:	00820174 	movhi	r2,2053
+ 80252b0:	1885883a 	add	r2,r3,r2
+ 80252b4:	10b36e17 	ldw	r2,-12872(r2)
+ 80252b8:	103ee83a 	callr	r2
+         closers[n] = NULL;
+ 80252bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80252c0:	100690ba 	slli	r3,r2,2
+ 80252c4:	00820174 	movhi	r2,2053
+ 80252c8:	1885883a 	add	r2,r3,r2
+ 80252cc:	10336e15 	stw	zero,-12872(r2)
+   for (n=nclosers; n; n--)
+ 80252d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80252d4:	10bfffc4 	addi	r2,r2,-1
+ 80252d8:	e0bfff15 	stw	r2,-4(fp)
+ 80252dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80252e0:	103fe11e 	bne	r2,zero,8025268 <ip_exit+0x1c>
+      }
+   }
+}
+ 80252e4:	0001883a 	nop
+ 80252e8:	e037883a 	mov	sp,fp
+ 80252ec:	dfc00117 	ldw	ra,4(sp)
+ 80252f0:	df000017 	ldw	fp,0(sp)
+ 80252f4:	dec00204 	addi	sp,sp,8
+ 80252f8:	f800283a 	ret
+
+080252fc <if_netnumber>:
+ * RETURNS: net index for passed net pointer
+ */
+
+int
+if_netnumber(NET nptr)
+{
+ 80252fc:	defffb04 	addi	sp,sp,-20
+ 8025300:	dfc00415 	stw	ra,16(sp)
+ 8025304:	df000315 	stw	fp,12(sp)
+ 8025308:	df000304 	addi	fp,sp,12
+ 802530c:	e13ffd15 	stw	r4,-12(fp)
+   unsigned i;
+   NET ifp;
+
+   for(ifp = (NET)(netlist.q_head), i = 0; ifp; ifp = ifp->n_next, i++)
+ 8025310:	008201b4 	movhi	r2,2054
+ 8025314:	10b6a617 	ldw	r2,-9576(r2)
+ 8025318:	e0bffe15 	stw	r2,-8(fp)
+ 802531c:	e03fff15 	stw	zero,-4(fp)
+ 8025320:	00000b06 	br	8025350 <if_netnumber+0x54>
+   {
+      if(ifp == nptr)
+ 8025324:	e0fffe17 	ldw	r3,-8(fp)
+ 8025328:	e0bffd17 	ldw	r2,-12(fp)
+ 802532c:	1880021e 	bne	r3,r2,8025338 <if_netnumber+0x3c>
+        return (int)i;
+ 8025330:	e0bfff17 	ldw	r2,-4(fp)
+ 8025334:	00000c06 	br	8025368 <if_netnumber+0x6c>
+   for(ifp = (NET)(netlist.q_head), i = 0; ifp; ifp = ifp->n_next, i++)
+ 8025338:	e0bffe17 	ldw	r2,-8(fp)
+ 802533c:	10800017 	ldw	r2,0(r2)
+ 8025340:	e0bffe15 	stw	r2,-8(fp)
+ 8025344:	e0bfff17 	ldw	r2,-4(fp)
+ 8025348:	10800044 	addi	r2,r2,1
+ 802534c:	e0bfff15 	stw	r2,-4(fp)
+ 8025350:	e0bffe17 	ldw	r2,-8(fp)
+ 8025354:	103ff31e 	bne	r2,zero,8025324 <if_netnumber+0x28>
+   }
+
+   panic("bad net ptr");
+ 8025358:	01020174 	movhi	r4,2053
+ 802535c:	21272b04 	addi	r4,r4,-25428
+ 8025360:	80271780 	call	8027178 <panic>
+   return 0;
+ 8025364:	0005883a 	mov	r2,zero
+}
+ 8025368:	e037883a 	mov	sp,fp
+ 802536c:	dfc00117 	ldw	ra,4(sp)
+ 8025370:	df000017 	ldw	fp,0(sp)
+ 8025374:	dec00204 	addi	sp,sp,8
+ 8025378:	f800283a 	ret
+
+0802537c <igmp_init>:
+ *
+ * OUTPUT: None.
+ */
+
+int igmp_init(void)
+{
+ 802537c:	defffe04 	addi	sp,sp,-8
+ 8025380:	df000115 	stw	fp,4(sp)
+ 8025384:	df000104 	addi	fp,sp,4
+   NET ifp;
+
+   /*
+    * To avoid byte-swapping the same value over and over again.
+    */
+   igmp_all_hosts_group = htonl(INADDR_ALLHOSTS_GROUP);
+ 8025388:	00804034 	movhi	r2,256
+ 802538c:	10803804 	addi	r2,r2,224
+ 8025390:	d0a06b15 	stw	r2,-32340(gp)
+   igmp_all_rtrs_group = htonl(INADDR_ALLRTRS_GROUP);
+ 8025394:	00808034 	movhi	r2,512
+ 8025398:	10803804 	addi	r2,r2,224
+ 802539c:	d0a06c15 	stw	r2,-32336(gp)
+   /* note that the IGMP operational mode configuration for a
+    * given link (i.e., whether it should run IGMPv1 or IGMPv2)
+    * has already been validated, so no additional checks are 
+    * required here. 
+    */
+   for (ifp = (NET) netlist.q_head; ifp; ifp = ifp->n_next)
+ 80253a0:	008201b4 	movhi	r2,2054
+ 80253a4:	10b6a617 	ldw	r2,-9576(r2)
+ 80253a8:	e0bfff15 	stw	r2,-4(fp)
+ 80253ac:	00001006 	br	80253f0 <igmp_init+0x74>
+   {
+      if (ifp->igmp_oper_mode == IGMP_MODE_V1)
+ 80253b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80253b4:	10802f03 	ldbu	r2,188(r2)
+ 80253b8:	10803fcc 	andi	r2,r2,255
+ 80253bc:	10800058 	cmpnei	r2,r2,1
+ 80253c0:	1000041e 	bne	r2,zero,80253d4 <igmp_init+0x58>
+      {
+         ifp->igmpv1_rtr_present = 1;
+ 80253c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80253c8:	00c00044 	movi	r3,1
+ 80253cc:	10c02d05 	stb	r3,180(r2)
+ 80253d0:	00000406 	br	80253e4 <igmp_init+0x68>
+      }
+      else
+      {
+         ifp->igmpv1_rtr_present = 0;
+ 80253d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80253d8:	10002d05 	stb	zero,180(r2)
+         /* not really required, only referred to if IGMPv1 router is 
+          * "present" */
+         ifp->igmpv1_query_rcvd_time = 0;
+ 80253dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80253e0:	10002e15 	stw	zero,184(r2)
+   for (ifp = (NET) netlist.q_head; ifp; ifp = ifp->n_next)
+ 80253e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80253e8:	10800017 	ldw	r2,0(r2)
+ 80253ec:	e0bfff15 	stw	r2,-4(fp)
+ 80253f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80253f4:	103fee1e 	bne	r2,zero,80253b0 <igmp_init+0x34>
+   }
+
+   /*
+    * Call igmp_fasttimo PR_FASTHZ (5) times per second
+    */
+   igmp_cticks = cticks + TPS/PR_FASTHZ;
+ 80253f8:	d0a07d17 	ldw	r2,-32268(gp)
+ 80253fc:	10800504 	addi	r2,r2,20
+ 8025400:	d0a06a15 	stw	r2,-32344(gp)
+
+   /* there are no timers running initially */
+   igmp_timers_are_running = 0;
+ 8025404:	d0206915 	stw	zero,-32348(gp)
+
+   return IGMP_OK;
+ 8025408:	0005883a 	mov	r2,zero
+}
+ 802540c:	e037883a 	mov	sp,fp
+ 8025410:	df000017 	ldw	fp,0(sp)
+ 8025414:	dec00104 	addi	sp,sp,4
+ 8025418:	f800283a 	ret
+
+0802541c <igmp_input>:
+ * returned if the operating mode is not correctly configured
+ * to a valid IGMP operating mode.
+ */
+
+int igmp_input (PACKET p)
+{
+ 802541c:	defffb04 	addi	sp,sp,-20
+ 8025420:	dfc00415 	stw	ra,16(sp)
+ 8025424:	df000315 	stw	fp,12(sp)
+ 8025428:	df000304 	addi	fp,sp,12
+ 802542c:	e13ffd15 	stw	r4,-12(fp)
+   u_char mode;
+   int rc;
+     
+   ++igmpstats.igmp_total_rcvd;
+ 8025430:	008201b4 	movhi	r2,2054
+ 8025434:	10b77417 	ldw	r2,-8752(r2)
+ 8025438:	10c00044 	addi	r3,r2,1
+ 802543c:	008201b4 	movhi	r2,2054
+ 8025440:	10f77415 	stw	r3,-8752(r2)
+   
+   /* validate the received packet; if validation fails,
+    * drop the packet and return */
+   if ((rc = igmp_validate (p)) != IGMP_OK) goto end;
+ 8025444:	e13ffd17 	ldw	r4,-12(fp)
+ 8025448:	8025b840 	call	8025b84 <igmp_validate>
+ 802544c:	e0bfff15 	stw	r2,-4(fp)
+ 8025450:	e0bfff17 	ldw	r2,-4(fp)
+ 8025454:	1000181e 	bne	r2,zero,80254b8 <igmp_input+0x9c>
+
+   /* determine the operating mode for IGMP on the ingress link */
+   mode = p->net->igmp_oper_mode;
+ 8025458:	e0bffd17 	ldw	r2,-12(fp)
+ 802545c:	10800617 	ldw	r2,24(r2)
+ 8025460:	10802f03 	ldbu	r2,188(r2)
+ 8025464:	e0bffec5 	stb	r2,-5(fp)
+   
+   /* feed packet to IGMPv1 or IGMPv2 code based on the operating
+    * mode of the ingress link */
+   switch (mode)
+ 8025468:	e0bffec3 	ldbu	r2,-5(fp)
+ 802546c:	10c00060 	cmpeqi	r3,r2,1
+ 8025470:	1800031e 	bne	r3,zero,8025480 <igmp_input+0x64>
+ 8025474:	108000a0 	cmpeqi	r2,r2,2
+ 8025478:	1000041e 	bne	r2,zero,802548c <igmp_input+0x70>
+ 802547c:	00000606 	br	8025498 <igmp_input+0x7c>
+   {
+#ifdef IGMP_V1   
+      case IGMP_MODE_V1:   
+         return (igmpv1_input (p)); 
+ 8025480:	e13ffd17 	ldw	r4,-12(fp)
+ 8025484:	803ddfc0 	call	803ddfc <igmpv1_input>
+ 8025488:	00001306 	br	80254d8 <igmp_input+0xbc>
+#endif
+#ifdef IGMP_V2         
+      case IGMP_MODE_V2:       
+         return (igmpv2_input (p));
+ 802548c:	e13ffd17 	ldw	r4,-12(fp)
+ 8025490:	803e0640 	call	803e064 <igmpv2_input>
+ 8025494:	00001006 	br	80254d8 <igmp_input+0xbc>
+#endif
+      default:
+         ++igmpstats.igmp_bad_oper_mode;     
+ 8025498:	008201b4 	movhi	r2,2054
+ 802549c:	10b78117 	ldw	r2,-8700(r2)
+ 80254a0:	10c00044 	addi	r3,r2,1
+ 80254a4:	008201b4 	movhi	r2,2054
+ 80254a8:	10f78115 	stw	r3,-8700(r2)
+         rc = IGMP_ERR;
+ 80254ac:	00bfffc4 	movi	r2,-1
+ 80254b0:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 80254b4:	00000106 	br	80254bc <igmp_input+0xa0>
+   if ((rc = igmp_validate (p)) != IGMP_OK) goto end;
+ 80254b8:	0001883a 	nop
+   }
+   
+end:   
+   /* return packet buffer back to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 80254bc:	01000084 	movi	r4,2
+ 80254c0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 80254c4:	e13ffd17 	ldw	r4,-12(fp)
+ 80254c8:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 80254cc:	01000084 	movi	r4,2
+ 80254d0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      
+   return rc;
+ 80254d4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80254d8:	e037883a 	mov	sp,fp
+ 80254dc:	dfc00117 	ldw	ra,4(sp)
+ 80254e0:	df000017 	ldw	fp,0(sp)
+ 80254e4:	dec00204 	addi	sp,sp,8
+ 80254e8:	f800283a 	ret
+
+080254ec <igmp_fasttimo>:
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_fasttimo (void)
+{
+ 80254ec:	defffc04 	addi	sp,sp,-16
+ 80254f0:	dfc00315 	stw	ra,12(sp)
+ 80254f4:	df000215 	stw	fp,8(sp)
+ 80254f8:	df000204 	addi	fp,sp,8
+   struct in_multi * inm;
+   NET ifp;
+     
+   LOCK_NET_RESOURCE (NET_RESID);
+ 80254fc:	0009883a 	mov	r4,zero
+ 8025500:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   
+   /*
+    * Quick check to see if any work needs to be done, in order
+    * to minimize the overhead of fasttimo processing.
+    */
+   if (!igmp_timers_are_running)
+ 8025504:	d0a06917 	ldw	r2,-32348(gp)
+ 8025508:	1000031e 	bne	r2,zero,8025518 <igmp_fasttimo+0x2c>
+   {
+      UNLOCK_NET_RESOURCE (NET_RESID);
+ 802550c:	0009883a 	mov	r4,zero
+ 8025510:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return;
+ 8025514:	00004c06 	br	8025648 <igmp_fasttimo+0x15c>
+   }
+
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8025518:	008201b4 	movhi	r2,2054
+ 802551c:	10b6a617 	ldw	r2,-9576(r2)
+ 8025520:	e0bffe15 	stw	r2,-8(fp)
+ 8025524:	00004006 	br	8025628 <igmp_fasttimo+0x13c>
+   {
+      for (inm = ifp->mc_list; inm; inm = inm->inm_next)
+ 8025528:	e0bffe17 	ldw	r2,-8(fp)
+ 802552c:	10802c17 	ldw	r2,176(r2)
+ 8025530:	e0bfff15 	stw	r2,-4(fp)
+ 8025534:	00003706 	br	8025614 <igmp_fasttimo+0x128>
+      {
+         /* skip IPv6 entries */
+         if (inm->inm_addr == 0) 
+ 8025538:	e0bfff17 	ldw	r2,-4(fp)
+ 802553c:	10800017 	ldw	r2,0(r2)
+ 8025540:	10003026 	beq	r2,zero,8025604 <igmp_fasttimo+0x118>
+               continue;
+
+         if (inm->inm_timer == 0)   /* timer not set */
+ 8025544:	e0bfff17 	ldw	r2,-4(fp)
+ 8025548:	10800317 	ldw	r2,12(r2)
+ 802554c:	10002e26 	beq	r2,zero,8025608 <igmp_fasttimo+0x11c>
+         {
+            /* do nothing */
+         }
+         else if (--inm->inm_timer == 0)  /* timer expired */
+ 8025550:	e0bfff17 	ldw	r2,-4(fp)
+ 8025554:	10800317 	ldw	r2,12(r2)
+ 8025558:	10ffffc4 	addi	r3,r2,-1
+ 802555c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025560:	10c00315 	stw	r3,12(r2)
+ 8025564:	e0bfff17 	ldw	r2,-4(fp)
+ 8025568:	10800317 	ldw	r2,12(r2)
+ 802556c:	1000261e 	bne	r2,zero,8025608 <igmp_fasttimo+0x11c>
+         {
+            /* send membership report in appropriate format */
+            if (ifp->igmpv1_rtr_present)
+ 8025570:	e0bffe17 	ldw	r2,-8(fp)
+ 8025574:	10802d03 	ldbu	r2,180(r2)
+ 8025578:	10803fcc 	andi	r2,r2,255
+ 802557c:	10000426 	beq	r2,zero,8025590 <igmp_fasttimo+0xa4>
+            {
+               /* always true for IGMPv1, may be true for IGMPv2 */
+               igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm);
+ 8025580:	e17fff17 	ldw	r5,-4(fp)
+ 8025584:	01000484 	movi	r4,18
+ 8025588:	802565c0 	call	802565c <igmp_send>
+ 802558c:	00000306 	br	802559c <igmp_fasttimo+0xb0>
+            }
+            else
+            {
+               igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm);
+ 8025590:	e17fff17 	ldw	r5,-4(fp)
+ 8025594:	01000584 	movi	r4,22
+ 8025598:	802565c0 	call	802565c <igmp_send>
+
+            /* for IGMPv2, indicate that we were the last to send 
+             * a Report for this multicast group (relevant for 
+             * IGMPv2 only).  also check to see if we should mark 
+             * the IGMPv1 router as "absent". */
+            if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+ 802559c:	e0bffe17 	ldw	r2,-8(fp)
+ 80255a0:	10802f03 	ldbu	r2,188(r2)
+ 80255a4:	10803fcc 	andi	r2,r2,255
+ 80255a8:	10800098 	cmpnei	r2,r2,2
+ 80255ac:	1000111e 	bne	r2,zero,80255f4 <igmp_fasttimo+0x108>
+            {
+               inm->last2send_report = IGMP_TRUE;
+ 80255b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80255b4:	00c00044 	movi	r3,1
+ 80255b8:	10c00405 	stb	r3,16(r2)
+               
+               if (ifp->igmpv1_rtr_present)
+ 80255bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80255c0:	10802d03 	ldbu	r2,180(r2)
+ 80255c4:	10803fcc 	andi	r2,r2,255
+ 80255c8:	10000a26 	beq	r2,zero,80255f4 <igmp_fasttimo+0x108>
+               {
+                  if (cticks > (ifp->igmpv1_query_rcvd_time + (IGMPv1_RTR_PRESENT_TMO * TPS)))
+ 80255cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80255d0:	10c02e17 	ldw	r3,184(r2)
+ 80255d4:	00a71014 	movui	r2,40000
+ 80255d8:	1887883a 	add	r3,r3,r2
+ 80255dc:	d0a07d17 	ldw	r2,-32268(gp)
+ 80255e0:	1880042e 	bgeu	r3,r2,80255f4 <igmp_fasttimo+0x108>
+                     /* we haven't heard from the IGMPv1 router for a duration
+                      * greater than or equal to Version 1 Router Present Timeout 
+                      * (400 seconds), and will now update the igmpv1_rtr_present 
+                      * variable to reflect that.
+                      */
+                     ifp->igmpv1_rtr_present = IGMP_FALSE;
+ 80255e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80255e8:	10002d05 	stb	zero,180(r2)
+                     ifp->igmpv1_query_rcvd_time = 0;
+ 80255ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80255f0:	10002e15 	stw	zero,184(r2)
+                  }
+               }  
+            }
+
+            /* decrement the count of running IGMP timers */
+            --igmp_timers_are_running;
+ 80255f4:	d0a06917 	ldw	r2,-32348(gp)
+ 80255f8:	10bfffc4 	addi	r2,r2,-1
+ 80255fc:	d0a06915 	stw	r2,-32348(gp)
+ 8025600:	00000106 	br	8025608 <igmp_fasttimo+0x11c>
+               continue;
+ 8025604:	0001883a 	nop
+      for (inm = ifp->mc_list; inm; inm = inm->inm_next)
+ 8025608:	e0bfff17 	ldw	r2,-4(fp)
+ 802560c:	10800517 	ldw	r2,20(r2)
+ 8025610:	e0bfff15 	stw	r2,-4(fp)
+ 8025614:	e0bfff17 	ldw	r2,-4(fp)
+ 8025618:	103fc71e 	bne	r2,zero,8025538 <igmp_fasttimo+0x4c>
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802561c:	e0bffe17 	ldw	r2,-8(fp)
+ 8025620:	10800017 	ldw	r2,0(r2)
+ 8025624:	e0bffe15 	stw	r2,-8(fp)
+ 8025628:	e0bffe17 	ldw	r2,-8(fp)
+ 802562c:	103fbe1e 	bne	r2,zero,8025528 <igmp_fasttimo+0x3c>
+      }     
+   }
+
+   /* Setup time for the next call into igmp_fasttimo ()
+    * (200 ms later). */
+   igmp_cticks = cticks + TPS/PR_FASTHZ;
+ 8025630:	d0a07d17 	ldw	r2,-32268(gp)
+ 8025634:	10800504 	addi	r2,r2,20
+ 8025638:	d0a06a15 	stw	r2,-32344(gp)
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+ 802563c:	0009883a 	mov	r4,zero
+ 8025640:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   
+   return;
+ 8025644:	0001883a 	nop
+}
+ 8025648:	e037883a 	mov	sp,fp
+ 802564c:	dfc00117 	ldw	ra,4(sp)
+ 8025650:	df000017 	ldw	fp,0(sp)
+ 8025654:	dec00204 	addi	sp,sp,8
+ 8025658:	f800283a 	ret
+
+0802565c <igmp_send>:
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_send (u_char type, struct in_multi * inm)
+{
+ 802565c:	deffde04 	addi	sp,sp,-136
+ 8025660:	dfc02115 	stw	ra,132(sp)
+ 8025664:	df002015 	stw	fp,128(sp)
+ 8025668:	df002004 	addi	fp,sp,128
+ 802566c:	2005883a 	mov	r2,r4
+ 8025670:	e17fe015 	stw	r5,-128(fp)
+ 8025674:	e0bfe105 	stb	r2,-124(fp)
+   struct igmp * igmp;
+   struct ip_moptions * imop;
+   struct ip_moptions simo;
+   struct ip * pip;
+   u_char * tmpp;
+   u_char opts [2] = {IP_RTR_ALERT_OPT, EOL_OPT};
+ 8025678:	00800504 	movi	r2,20
+ 802567c:	e0bfe285 	stb	r2,-118(fp)
+ 8025680:	e03fe2c5 	stb	zero,-117(fp)
+   u_char reqd_len;
+
+   /* compute length of buffer required for outgoing packet.
+    * also account for the length of the IP Router Alert 
+    * option, if required. */   
+   reqd_len = MaxLnh + sizeof (struct ip) + sizeof (struct igmp);
+ 8025684:	d0a06417 	ldw	r2,-32368(gp)
+ 8025688:	10800704 	addi	r2,r2,28
+ 802568c:	e0bffdc5 	stb	r2,-9(fp)
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+ 8025690:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025694:	108005e0 	cmpeqi	r2,r2,23
+ 8025698:	1000031e 	bne	r2,zero,80256a8 <igmp_send+0x4c>
+ 802569c:	e0bfe103 	ldbu	r2,-124(fp)
+ 80256a0:	10800598 	cmpnei	r2,r2,22
+ 80256a4:	1000031e 	bne	r2,zero,80256b4 <igmp_send+0x58>
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      reqd_len += IP_RTR_ALERT_OPT_SIZE;
+ 80256a8:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80256ac:	10800104 	addi	r2,r2,4
+ 80256b0:	e0bffdc5 	stb	r2,-9(fp)
+   }
+
+   /* obtain a packet to send the IGMP message */
+   LOCK_NET_RESOURCE (FREEQ_RESID);
+ 80256b4:	01000084 	movi	r4,2
+ 80256b8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   p = pk_alloc (reqd_len);
+ 80256bc:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80256c0:	1009883a 	mov	r4,r2
+ 80256c4:	80284340 	call	8028434 <pk_alloc>
+ 80256c8:	e0bffc15 	stw	r2,-16(fp)
+   UNLOCK_NET_RESOURCE (FREEQ_RESID);
+ 80256cc:	01000084 	movi	r4,2
+ 80256d0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   
+   /* log an error and return if the allocation fails */   
+   if (!p)
+ 80256d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80256d8:	1000061e 	bne	r2,zero,80256f4 <igmp_send+0x98>
+   {
+      ++igmpstats.igmp_pkt_alloc_fail;
+ 80256dc:	008201b4 	movhi	r2,2054
+ 80256e0:	10b78017 	ldw	r2,-8704(r2)
+ 80256e4:	10c00044 	addi	r3,r2,1
+ 80256e8:	008201b4 	movhi	r2,2054
+ 80256ec:	10f78015 	stw	r3,-8704(r2)
+ 80256f0:	00007406 	br	80258c4 <igmp_send+0x268>
+      return;
+   }
+
+   /* Need to fill in the source and destination ip addresses */
+   pip = (struct ip *) p->nb_prot;
+ 80256f4:	e0bffc17 	ldw	r2,-16(fp)
+ 80256f8:	10800317 	ldw	r2,12(r2)
+ 80256fc:	e0bffb15 	stw	r2,-20(fp)
+   pip->ip_src = inm->inm_netp->n_ipaddr;
+ 8025700:	e0bfe017 	ldw	r2,-128(fp)
+ 8025704:	10800117 	ldw	r2,4(r2)
+ 8025708:	10c00a17 	ldw	r3,40(r2)
+ 802570c:	e0bffb17 	ldw	r2,-20(fp)
+ 8025710:	10c00315 	stw	r3,12(r2)
+   /* Leave Group messages are sent to the all-routers multicast group */
+   if (type == IGMPv2_LEAVE_GROUP)
+ 8025714:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025718:	108005d8 	cmpnei	r2,r2,23
+ 802571c:	1000041e 	bne	r2,zero,8025730 <igmp_send+0xd4>
+   {
+      /* igmp_all_rtrs_group is already in network byte order */
+      pip->ip_dest = igmp_all_rtrs_group;
+ 8025720:	d0e06c17 	ldw	r3,-32336(gp)
+ 8025724:	e0bffb17 	ldw	r2,-20(fp)
+ 8025728:	10c00415 	stw	r3,16(r2)
+ 802572c:	00000406 	br	8025740 <igmp_send+0xe4>
+   }
+   else
+      pip->ip_dest = inm->inm_addr;
+ 8025730:	e0bfe017 	ldw	r2,-128(fp)
+ 8025734:	10c00017 	ldw	r3,0(r2)
+ 8025738:	e0bffb17 	ldw	r2,-20(fp)
+ 802573c:	10c00415 	stw	r3,16(r2)
+   
+   p->fhost = pip->ip_dest;
+ 8025740:	e0bffb17 	ldw	r2,-20(fp)
+ 8025744:	10c00417 	ldw	r3,16(r2)
+ 8025748:	e0bffc17 	ldw	r2,-16(fp)
+ 802574c:	10c00715 	stw	r3,28(r2)
+
+   tmpp = (((u_char *) p->nb_prot) + sizeof (struct ip));
+ 8025750:	e0bffc17 	ldw	r2,-16(fp)
+ 8025754:	10800317 	ldw	r2,12(r2)
+ 8025758:	10800504 	addi	r2,r2,20
+ 802575c:	e0bfff15 	stw	r2,-4(fp)
+
+   /* when transmitting an IGMP packet, our IGMP module will insert
+    * data for the Router Alert option in the following types of
+    * packets: Version 2 Membership Report (0x16) and Leave Group 
+    * (0x17) */
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+ 8025760:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025764:	108005e0 	cmpeqi	r2,r2,23
+ 8025768:	1000031e 	bne	r2,zero,8025778 <igmp_send+0x11c>
+ 802576c:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025770:	10800598 	cmpnei	r2,r2,22
+ 8025774:	1000061e 	bne	r2,zero,8025790 <igmp_send+0x134>
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      /* provide space for ip_write2 () to write option-related data */
+      tmpp += IP_RTR_ALERT_OPT_SIZE;
+ 8025778:	e0bfff17 	ldw	r2,-4(fp)
+ 802577c:	10800104 	addi	r2,r2,4
+ 8025780:	e0bfff15 	stw	r2,-4(fp)
+      optp = &(opts [0]); /* one option (IP Router Alert) */
+ 8025784:	e0bfe284 	addi	r2,fp,-118
+ 8025788:	e0bffe15 	stw	r2,-8(fp)
+ 802578c:	00000306 	br	802579c <igmp_send+0x140>
+   }
+   /* outgoing packet does not require any options */
+   else 
+      optp = &(opts [1]);
+ 8025790:	e0bfe284 	addi	r2,fp,-118
+ 8025794:	10800044 	addi	r2,r2,1
+ 8025798:	e0bffe15 	stw	r2,-8(fp)
+   /* point to the start of the IGMP header */
+   igmp = (struct igmp *) tmpp;
+ 802579c:	e0bfff17 	ldw	r2,-4(fp)
+ 80257a0:	e0bffa15 	stw	r2,-24(fp)
+   
+   igmp->igmp_type = type;
+ 80257a4:	e0bffa17 	ldw	r2,-24(fp)
+ 80257a8:	e0ffe103 	ldbu	r3,-124(fp)
+ 80257ac:	10c00005 	stb	r3,0(r2)
+   igmp->igmp_code = 0;
+ 80257b0:	e0bffa17 	ldw	r2,-24(fp)
+ 80257b4:	10000045 	stb	zero,1(r2)
+   
+   /* all messages (Report or Leave) have Group Address field 
+    * set to the group being reported or left */
+   igmp->igmp_group = inm->inm_addr;
+ 80257b8:	e0bfe017 	ldw	r2,-128(fp)
+ 80257bc:	10c00017 	ldw	r3,0(r2)
+ 80257c0:	e0bffa17 	ldw	r2,-24(fp)
+ 80257c4:	10c00115 	stw	r3,4(r2)
+   igmp->igmp_cksum = 0;
+ 80257c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80257cc:	1000008d 	sth	zero,2(r2)
+   igmp->igmp_cksum = ~cksum((void*)igmp, IGMP_MINLEN>>1);
+ 80257d0:	01400104 	movi	r5,4
+ 80257d4:	e13ffa17 	ldw	r4,-24(fp)
+ 80257d8:	8026d7c0 	call	8026d7c <cksum>
+ 80257dc:	0084303a 	nor	r2,zero,r2
+ 80257e0:	1007883a 	mov	r3,r2
+ 80257e4:	e0bffa17 	ldw	r2,-24(fp)
+ 80257e8:	10c0008d 	sth	r3,2(r2)
+
+   imop = &simo;
+ 80257ec:	e0bfe304 	addi	r2,fp,-116
+ 80257f0:	e0bff915 	stw	r2,-28(fp)
+   MEMSET(imop, 0, sizeof(simo));
+ 80257f4:	01801604 	movi	r6,88
+ 80257f8:	000b883a 	mov	r5,zero
+ 80257fc:	e13ff917 	ldw	r4,-28(fp)
+ 8025800:	80088e40 	call	80088e4 <memset>
+   imop->imo_multicast_netp = inm->inm_netp;
+ 8025804:	e0bfe017 	ldw	r2,-128(fp)
+ 8025808:	10c00117 	ldw	r3,4(r2)
+ 802580c:	e0bff917 	ldw	r2,-28(fp)
+ 8025810:	10c00015 	stw	r3,0(r2)
+   imop->imo_multicast_ttl = 1;
+ 8025814:	e0bff917 	ldw	r2,-28(fp)
+ 8025818:	00c00044 	movi	r3,1
+ 802581c:	10c00105 	stb	r3,4(r2)
+   /* we do not want our own reports to be looped back */
+   imop->imo_multicast_loop = 0;
+ 8025820:	e0bff917 	ldw	r2,-28(fp)
+ 8025824:	10000145 	stb	zero,5(r2)
+
+   /* set nb_prot to point to the beginning of the IGMP data,
+    * and nb_plen to the length of the IGMP data, and attach
+    * the multicast options structure to the outgoing packet */
+   p->nb_prot = (char *) tmpp;
+ 8025828:	e0bffc17 	ldw	r2,-16(fp)
+ 802582c:	e0ffff17 	ldw	r3,-4(fp)
+ 8025830:	10c00315 	stw	r3,12(r2)
+   p->nb_plen = sizeof(struct igmp);
+ 8025834:	e0bffc17 	ldw	r2,-16(fp)
+ 8025838:	00c00204 	movi	r3,8
+ 802583c:	10c00415 	stw	r3,16(r2)
+   p->imo = imop;
+ 8025840:	e0bffc17 	ldw	r2,-16(fp)
+ 8025844:	e0fff917 	ldw	r3,-28(fp)
+ 8025848:	10c00b15 	stw	r3,44(r2)
+   
+   ip_write2 (IGMP_PROT, p, optp);
+ 802584c:	e1bffe17 	ldw	r6,-8(fp)
+ 8025850:	e17ffc17 	ldw	r5,-16(fp)
+ 8025854:	01000084 	movi	r4,2
+ 8025858:	803abf80 	call	803abf8 <ip_write2>
+
+   if (type == IGMPv2_LEAVE_GROUP)
+ 802585c:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025860:	108005d8 	cmpnei	r2,r2,23
+ 8025864:	1000061e 	bne	r2,zero,8025880 <igmp_send+0x224>
+      ++igmpstats.igmpv2mode_v2_leave_msgs_sent;
+ 8025868:	008201b4 	movhi	r2,2054
+ 802586c:	10b78b17 	ldw	r2,-8660(r2)
+ 8025870:	10c00044 	addi	r3,r2,1
+ 8025874:	008201b4 	movhi	r2,2054
+ 8025878:	10f78b15 	stw	r3,-8660(r2)
+ 802587c:	00001106 	br	80258c4 <igmp_send+0x268>
+   else if (type == IGMPv2_MEMBERSHIP_REPORT)
+ 8025880:	e0bfe103 	ldbu	r2,-124(fp)
+ 8025884:	10800598 	cmpnei	r2,r2,22
+ 8025888:	1000061e 	bne	r2,zero,80258a4 <igmp_send+0x248>
+      ++igmpstats.igmpv2mode_v2_reports_sent;
+ 802588c:	008201b4 	movhi	r2,2054
+ 8025890:	10b78c17 	ldw	r2,-8656(r2)
+ 8025894:	10c00044 	addi	r3,r2,1
+ 8025898:	008201b4 	movhi	r2,2054
+ 802589c:	10f78c15 	stw	r3,-8656(r2)
+ 80258a0:	00000806 	br	80258c4 <igmp_send+0x268>
+   else if (type == IGMP_HOST_MEMBERSHIP_REPORT)
+ 80258a4:	e0bfe103 	ldbu	r2,-124(fp)
+ 80258a8:	10800498 	cmpnei	r2,r2,18
+ 80258ac:	1000051e 	bne	r2,zero,80258c4 <igmp_send+0x268>
+      ++igmpstats.igmp_v1_reports_sent;
+ 80258b0:	008201b4 	movhi	r2,2054
+ 80258b4:	10b78a17 	ldw	r2,-8664(r2)
+ 80258b8:	10c00044 	addi	r3,r2,1
+ 80258bc:	008201b4 	movhi	r2,2054
+ 80258c0:	10f78a15 	stw	r3,-8664(r2)
+}
+ 80258c4:	e037883a 	mov	sp,fp
+ 80258c8:	dfc00117 	ldw	ra,4(sp)
+ 80258cc:	df000017 	ldw	fp,0(sp)
+ 80258d0:	dec00204 	addi	sp,sp,8
+ 80258d4:	f800283a 	ret
+
+080258d8 <igmp_joingroup>:
+ *
+ * OUTPUT: None.
+ */
+ 
+void igmp_joingroup(struct in_multi * inm)
+{
+ 80258d8:	defffc04 	addi	sp,sp,-16
+ 80258dc:	dfc00315 	stw	ra,12(sp)
+ 80258e0:	df000215 	stw	fp,8(sp)
+ 80258e4:	df000204 	addi	fp,sp,8
+ 80258e8:	e13ffe15 	stw	r4,-8(fp)
+   NET ifp;
+
+   /* extract the network interface to which this multicast
+    * address is "attached" */
+   ifp = inm->inm_netp;
+ 80258ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80258f0:	10800117 	ldw	r2,4(r2)
+ 80258f4:	e0bfff15 	stw	r2,-4(fp)
+
+   if (inm->inm_addr == igmp_all_hosts_group)
+ 80258f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80258fc:	10c00017 	ldw	r3,0(r2)
+ 8025900:	d0a06b17 	ldw	r2,-32340(gp)
+ 8025904:	1880031e 	bne	r3,r2,8025914 <igmp_joingroup+0x3c>
+   {
+      inm->inm_timer = 0;
+ 8025908:	e0bffe17 	ldw	r2,-8(fp)
+ 802590c:	10000315 	stw	zero,12(r2)
+      }
+
+      ++igmp_timers_are_running;
+   }
+   
+   return;
+ 8025910:	00007706 	br	8025af0 <igmp_joingroup+0x218>
+      if (ifp->igmpv1_rtr_present)
+ 8025914:	e0bfff17 	ldw	r2,-4(fp)
+ 8025918:	10802d03 	ldbu	r2,180(r2)
+ 802591c:	10803fcc 	andi	r2,r2,255
+ 8025920:	10003426 	beq	r2,zero,80259f4 <igmp_joingroup+0x11c>
+         igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm);
+ 8025924:	e17ffe17 	ldw	r5,-8(fp)
+ 8025928:	01000484 	movi	r4,18
+ 802592c:	802565c0 	call	802565c <igmp_send>
+         inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr);
+ 8025930:	008201b4 	movhi	r2,2054
+ 8025934:	10f95117 	ldw	r3,-6844(r2)
+ 8025938:	008201b4 	movhi	r2,2054
+ 802593c:	10b77017 	ldw	r2,-8768(r2)
+ 8025940:	10800a17 	ldw	r2,40(r2)
+ 8025944:	1008d63a 	srli	r4,r2,24
+ 8025948:	008201b4 	movhi	r2,2054
+ 802594c:	10b77017 	ldw	r2,-8768(r2)
+ 8025950:	10800a17 	ldw	r2,40(r2)
+ 8025954:	1004d23a 	srli	r2,r2,8
+ 8025958:	10bfc00c 	andi	r2,r2,65280
+ 802595c:	2088b03a 	or	r4,r4,r2
+ 8025960:	008201b4 	movhi	r2,2054
+ 8025964:	10b77017 	ldw	r2,-8768(r2)
+ 8025968:	10800a17 	ldw	r2,40(r2)
+ 802596c:	1004923a 	slli	r2,r2,8
+ 8025970:	10803fec 	andhi	r2,r2,255
+ 8025974:	2088b03a 	or	r4,r4,r2
+ 8025978:	008201b4 	movhi	r2,2054
+ 802597c:	10b77017 	ldw	r2,-8768(r2)
+ 8025980:	10800a17 	ldw	r2,40(r2)
+ 8025984:	1004963a 	slli	r2,r2,24
+ 8025988:	2084b03a 	or	r2,r4,r2
+ 802598c:	1887883a 	add	r3,r3,r2
+ 8025990:	e0bffe17 	ldw	r2,-8(fp)
+ 8025994:	10800017 	ldw	r2,0(r2)
+ 8025998:	1008d63a 	srli	r4,r2,24
+ 802599c:	e0bffe17 	ldw	r2,-8(fp)
+ 80259a0:	10800017 	ldw	r2,0(r2)
+ 80259a4:	1004d23a 	srli	r2,r2,8
+ 80259a8:	10bfc00c 	andi	r2,r2,65280
+ 80259ac:	2088b03a 	or	r4,r4,r2
+ 80259b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80259b4:	10800017 	ldw	r2,0(r2)
+ 80259b8:	1004923a 	slli	r2,r2,8
+ 80259bc:	10803fec 	andhi	r2,r2,255
+ 80259c0:	2088b03a 	or	r4,r4,r2
+ 80259c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80259c8:	10800017 	ldw	r2,0(r2)
+ 80259cc:	1004963a 	slli	r2,r2,24
+ 80259d0:	2084b03a 	or	r2,r4,r2
+ 80259d4:	1885883a 	add	r2,r3,r2
+ 80259d8:	01400c84 	movi	r5,50
+ 80259dc:	1009883a 	mov	r4,r2
+ 80259e0:	800d05c0 	call	800d05c <__umodsi3>
+ 80259e4:	10c00044 	addi	r3,r2,1
+ 80259e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80259ec:	10c00315 	stw	r3,12(r2)
+ 80259f0:	00003306 	br	8025ac0 <igmp_joingroup+0x1e8>
+         igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm);
+ 80259f4:	e17ffe17 	ldw	r5,-8(fp)
+ 80259f8:	01000584 	movi	r4,22
+ 80259fc:	802565c0 	call	802565c <igmp_send>
+         inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY ((UNSOLIC_RPT_INTERVAL * PR_FASTHZ), inm->inm_addr);
+ 8025a00:	008201b4 	movhi	r2,2054
+ 8025a04:	10f95117 	ldw	r3,-6844(r2)
+ 8025a08:	008201b4 	movhi	r2,2054
+ 8025a0c:	10b77017 	ldw	r2,-8768(r2)
+ 8025a10:	10800a17 	ldw	r2,40(r2)
+ 8025a14:	1008d63a 	srli	r4,r2,24
+ 8025a18:	008201b4 	movhi	r2,2054
+ 8025a1c:	10b77017 	ldw	r2,-8768(r2)
+ 8025a20:	10800a17 	ldw	r2,40(r2)
+ 8025a24:	1004d23a 	srli	r2,r2,8
+ 8025a28:	10bfc00c 	andi	r2,r2,65280
+ 8025a2c:	2088b03a 	or	r4,r4,r2
+ 8025a30:	008201b4 	movhi	r2,2054
+ 8025a34:	10b77017 	ldw	r2,-8768(r2)
+ 8025a38:	10800a17 	ldw	r2,40(r2)
+ 8025a3c:	1004923a 	slli	r2,r2,8
+ 8025a40:	10803fec 	andhi	r2,r2,255
+ 8025a44:	2088b03a 	or	r4,r4,r2
+ 8025a48:	008201b4 	movhi	r2,2054
+ 8025a4c:	10b77017 	ldw	r2,-8768(r2)
+ 8025a50:	10800a17 	ldw	r2,40(r2)
+ 8025a54:	1004963a 	slli	r2,r2,24
+ 8025a58:	2084b03a 	or	r2,r4,r2
+ 8025a5c:	1887883a 	add	r3,r3,r2
+ 8025a60:	e0bffe17 	ldw	r2,-8(fp)
+ 8025a64:	10800017 	ldw	r2,0(r2)
+ 8025a68:	1008d63a 	srli	r4,r2,24
+ 8025a6c:	e0bffe17 	ldw	r2,-8(fp)
+ 8025a70:	10800017 	ldw	r2,0(r2)
+ 8025a74:	1004d23a 	srli	r2,r2,8
+ 8025a78:	10bfc00c 	andi	r2,r2,65280
+ 8025a7c:	2088b03a 	or	r4,r4,r2
+ 8025a80:	e0bffe17 	ldw	r2,-8(fp)
+ 8025a84:	10800017 	ldw	r2,0(r2)
+ 8025a88:	1004923a 	slli	r2,r2,8
+ 8025a8c:	10803fec 	andhi	r2,r2,255
+ 8025a90:	2088b03a 	or	r4,r4,r2
+ 8025a94:	e0bffe17 	ldw	r2,-8(fp)
+ 8025a98:	10800017 	ldw	r2,0(r2)
+ 8025a9c:	1004963a 	slli	r2,r2,24
+ 8025aa0:	2084b03a 	or	r2,r4,r2
+ 8025aa4:	1885883a 	add	r2,r3,r2
+ 8025aa8:	01400c84 	movi	r5,50
+ 8025aac:	1009883a 	mov	r4,r2
+ 8025ab0:	800d05c0 	call	800d05c <__umodsi3>
+ 8025ab4:	10c00044 	addi	r3,r2,1
+ 8025ab8:	e0bffe17 	ldw	r2,-8(fp)
+ 8025abc:	10c00315 	stw	r3,12(r2)
+      if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+ 8025ac0:	e0bfff17 	ldw	r2,-4(fp)
+ 8025ac4:	10802f03 	ldbu	r2,188(r2)
+ 8025ac8:	10803fcc 	andi	r2,r2,255
+ 8025acc:	10800098 	cmpnei	r2,r2,2
+ 8025ad0:	1000031e 	bne	r2,zero,8025ae0 <igmp_joingroup+0x208>
+         inm->last2send_report = IGMP_TRUE;
+ 8025ad4:	e0bffe17 	ldw	r2,-8(fp)
+ 8025ad8:	00c00044 	movi	r3,1
+ 8025adc:	10c00405 	stb	r3,16(r2)
+      ++igmp_timers_are_running;
+ 8025ae0:	d0a06917 	ldw	r2,-32348(gp)
+ 8025ae4:	10800044 	addi	r2,r2,1
+ 8025ae8:	d0a06915 	stw	r2,-32348(gp)
+   return;
+ 8025aec:	0001883a 	nop
+}     
+ 8025af0:	e037883a 	mov	sp,fp
+ 8025af4:	dfc00117 	ldw	ra,4(sp)
+ 8025af8:	df000017 	ldw	fp,0(sp)
+ 8025afc:	dec00204 	addi	sp,sp,8
+ 8025b00:	f800283a 	ret
+
+08025b04 <igmp_leavegroup>:
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_leavegroup (struct in_multi * inm)
+{
+ 8025b04:	defffc04 	addi	sp,sp,-16
+ 8025b08:	dfc00315 	stw	ra,12(sp)
+ 8025b0c:	df000215 	stw	fp,8(sp)
+ 8025b10:	df000204 	addi	fp,sp,8
+ 8025b14:	e13ffe15 	stw	r4,-8(fp)
+   NET ifp;
+
+   ifp = inm->inm_netp;
+ 8025b18:	e0bffe17 	ldw	r2,-8(fp)
+ 8025b1c:	10800117 	ldw	r2,4(r2)
+ 8025b20:	e0bfff15 	stw	r2,-4(fp)
+
+   if ((ifp->igmp_oper_mode == IGMP_MODE_V2) && 
+ 8025b24:	e0bfff17 	ldw	r2,-4(fp)
+ 8025b28:	10802f03 	ldbu	r2,188(r2)
+ 8025b2c:	10803fcc 	andi	r2,r2,255
+ 8025b30:	10800098 	cmpnei	r2,r2,2
+ 8025b34:	10000d1e 	bne	r2,zero,8025b6c <igmp_leavegroup+0x68>
+       !ifp->igmpv1_rtr_present)
+ 8025b38:	e0bfff17 	ldw	r2,-4(fp)
+ 8025b3c:	10802d03 	ldbu	r2,180(r2)
+   if ((ifp->igmp_oper_mode == IGMP_MODE_V2) && 
+ 8025b40:	10803fcc 	andi	r2,r2,255
+ 8025b44:	1000091e 	bne	r2,zero,8025b6c <igmp_leavegroup+0x68>
+   {
+      if (inm->last2send_report == IGMP_TRUE)
+ 8025b48:	e0bffe17 	ldw	r2,-8(fp)
+ 8025b4c:	10800403 	ldbu	r2,16(r2)
+ 8025b50:	10803fcc 	andi	r2,r2,255
+ 8025b54:	10800058 	cmpnei	r2,r2,1
+ 8025b58:	1000041e 	bne	r2,zero,8025b6c <igmp_leavegroup+0x68>
+         igmp_send (IGMPv2_LEAVE_GROUP, inm);
+ 8025b5c:	e17ffe17 	ldw	r5,-8(fp)
+ 8025b60:	010005c4 	movi	r4,23
+ 8025b64:	802565c0 	call	802565c <igmp_send>
+   }
+   
+   return;
+ 8025b68:	0001883a 	nop
+ 8025b6c:	0001883a 	nop
+}
+ 8025b70:	e037883a 	mov	sp,fp
+ 8025b74:	dfc00117 	ldw	ra,4(sp)
+ 8025b78:	df000017 	ldw	fp,0(sp)
+ 8025b7c:	dec00204 	addi	sp,sp,8
+ 8025b80:	f800283a 	ret
+
+08025b84 <igmp_validate>:
+ *         validation fails; otherwise, it returns
+ *         IGMP_OK.
+ */
+
+int igmp_validate (PACKET p)
+{
+ 8025b84:	defff604 	addi	sp,sp,-40
+ 8025b88:	dfc00915 	stw	ra,36(sp)
+ 8025b8c:	df000815 	stw	fp,32(sp)
+ 8025b90:	df000804 	addi	fp,sp,32
+ 8025b94:	e13ff815 	stw	r4,-32(fp)
+   u_short xsum;  
+   u_char type;
+   ip_addr mcgrp_addr;
+   u_char resp_time;
+
+   pip = ip_head (p);
+ 8025b98:	e0bff817 	ldw	r2,-32(fp)
+ 8025b9c:	10800317 	ldw	r2,12(r2)
+ 8025ba0:	e0bfff15 	stw	r2,-4(fp)
+
+   /* compute length of IGMP packet (after accounting for IP header, 
+    * including the IP Router Alert option (if present)) */
+   igmplen = p->nb_plen - ip_hlen (pip);
+ 8025ba4:	e0bff817 	ldw	r2,-32(fp)
+ 8025ba8:	10c00417 	ldw	r3,16(r2)
+ 8025bac:	e0bfff17 	ldw	r2,-4(fp)
+ 8025bb0:	10800003 	ldbu	r2,0(r2)
+ 8025bb4:	10803fcc 	andi	r2,r2,255
+ 8025bb8:	100490ba 	slli	r2,r2,2
+ 8025bbc:	10800f0c 	andi	r2,r2,60
+ 8025bc0:	1885c83a 	sub	r2,r3,r2
+ 8025bc4:	e0bffe15 	stw	r2,-8(fp)
+
+   /* validate length (IGMP_MINLEN is 8 bytes) */
+   if (igmplen != IGMP_MINLEN) 
+ 8025bc8:	e0bffe17 	ldw	r2,-8(fp)
+ 8025bcc:	10800220 	cmpeqi	r2,r2,8
+ 8025bd0:	1000071e 	bne	r2,zero,8025bf0 <igmp_validate+0x6c>
+   {
+      ++igmpstats.igmp_badlen_rcvd;
+ 8025bd4:	008201b4 	movhi	r2,2054
+ 8025bd8:	10b77e17 	ldw	r2,-8712(r2)
+ 8025bdc:	10c00044 	addi	r3,r2,1
+ 8025be0:	008201b4 	movhi	r2,2054
+ 8025be4:	10f77e15 	stw	r3,-8712(r2)
+      return ENP_BAD_HEADER;
+ 8025be8:	00bff804 	movi	r2,-32
+ 8025bec:	00009706 	br	8025e4c <igmp_validate+0x2c8>
+   }
+
+   /* validate checksum */
+   igmp = (struct igmp *) (ip_data (pip));
+ 8025bf0:	e0bfff17 	ldw	r2,-4(fp)
+ 8025bf4:	10800003 	ldbu	r2,0(r2)
+ 8025bf8:	10803fcc 	andi	r2,r2,255
+ 8025bfc:	100490ba 	slli	r2,r2,2
+ 8025c00:	10800f0c 	andi	r2,r2,60
+ 8025c04:	e0ffff17 	ldw	r3,-4(fp)
+ 8025c08:	1885883a 	add	r2,r3,r2
+ 8025c0c:	e0bffd15 	stw	r2,-12(fp)
+   osum = igmp->igmp_cksum;
+ 8025c10:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c14:	1080008b 	ldhu	r2,2(r2)
+ 8025c18:	e0bffc8d 	sth	r2,-14(fp)
+   igmp->igmp_cksum = 0;
+ 8025c1c:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c20:	1000008d 	sth	zero,2(r2)
+   xsum = ~cksum(igmp, igmplen>>1);
+ 8025c24:	e0bffe17 	ldw	r2,-8(fp)
+ 8025c28:	1005d07a 	srai	r2,r2,1
+ 8025c2c:	100b883a 	mov	r5,r2
+ 8025c30:	e13ffd17 	ldw	r4,-12(fp)
+ 8025c34:	8026d7c0 	call	8026d7c <cksum>
+ 8025c38:	0084303a 	nor	r2,zero,r2
+ 8025c3c:	e0bffc0d 	sth	r2,-16(fp)
+   if (xsum != osum)
+ 8025c40:	e0fffc0b 	ldhu	r3,-16(fp)
+ 8025c44:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8025c48:	18800a26 	beq	r3,r2,8025c74 <igmp_validate+0xf0>
+   {
+      igmp->igmp_cksum = osum;
+ 8025c4c:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c50:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8025c54:	10c0008d 	sth	r3,2(r2)
+      ++igmpstats.igmp_badsum_rcvd;
+ 8025c58:	008201b4 	movhi	r2,2054
+ 8025c5c:	10b77f17 	ldw	r2,-8708(r2)
+ 8025c60:	10c00044 	addi	r3,r2,1
+ 8025c64:	008201b4 	movhi	r2,2054
+ 8025c68:	10f77f15 	stw	r3,-8708(r2)
+      return ENP_BAD_HEADER;
+ 8025c6c:	00bff804 	movi	r2,-32
+ 8025c70:	00007606 	br	8025e4c <igmp_validate+0x2c8>
+   }
+   
+   /* extract the IGMP packet type, Group Address, and Max Response Time 
+    * (unused for IGMPv1) fields from received packet */
+   type = igmp->igmp_type;
+ 8025c74:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c78:	10800003 	ldbu	r2,0(r2)
+ 8025c7c:	e0bffbc5 	stb	r2,-17(fp)
+   mcgrp_addr = ntohl(igmp->igmp_group); 
+ 8025c80:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c84:	10800117 	ldw	r2,4(r2)
+ 8025c88:	1006d63a 	srli	r3,r2,24
+ 8025c8c:	e0bffd17 	ldw	r2,-12(fp)
+ 8025c90:	10800117 	ldw	r2,4(r2)
+ 8025c94:	1004d23a 	srli	r2,r2,8
+ 8025c98:	10bfc00c 	andi	r2,r2,65280
+ 8025c9c:	1886b03a 	or	r3,r3,r2
+ 8025ca0:	e0bffd17 	ldw	r2,-12(fp)
+ 8025ca4:	10800117 	ldw	r2,4(r2)
+ 8025ca8:	1004923a 	slli	r2,r2,8
+ 8025cac:	10803fec 	andhi	r2,r2,255
+ 8025cb0:	1886b03a 	or	r3,r3,r2
+ 8025cb4:	e0bffd17 	ldw	r2,-12(fp)
+ 8025cb8:	10800117 	ldw	r2,4(r2)
+ 8025cbc:	1004963a 	slli	r2,r2,24
+ 8025cc0:	1884b03a 	or	r2,r3,r2
+ 8025cc4:	e0bffa15 	stw	r2,-24(fp)
+   resp_time = igmp->igmp_code;
+ 8025cc8:	e0bffd17 	ldw	r2,-12(fp)
+ 8025ccc:	10800043 	ldbu	r2,1(r2)
+ 8025cd0:	e0bff9c5 	stb	r2,-25(fp)
+      
+   if (type == IGMP_HOST_MEMBERSHIP_QUERY)
+ 8025cd4:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025cd8:	10800458 	cmpnei	r2,r2,17
+ 8025cdc:	10002c1e 	bne	r2,zero,8025d90 <igmp_validate+0x20c>
+   {
+      if ((resp_time == 0) || /* IGMPv1 Query */
+ 8025ce0:	e0bff9c3 	ldbu	r2,-25(fp)
+ 8025ce4:	10000426 	beq	r2,zero,8025cf8 <igmp_validate+0x174>
+ 8025ce8:	e0bff9c3 	ldbu	r2,-25(fp)
+ 8025cec:	10000d26 	beq	r2,zero,8025d24 <igmp_validate+0x1a0>
+          ((resp_time > 0) && (mcgrp_addr == 0))) /* IGMPv2 General Query */     
+ 8025cf0:	e0bffa17 	ldw	r2,-24(fp)
+ 8025cf4:	10000b1e 	bne	r2,zero,8025d24 <igmp_validate+0x1a0>
+      {
+         /* if this is a IGMPv1 Host Membership Query or a IGMPv2 
+          * General Query, it must be addressed to the all-hosts 
+          * group */
+         if (pip->ip_dest != igmp_all_hosts_group) 
+ 8025cf8:	e0bfff17 	ldw	r2,-4(fp)
+ 8025cfc:	10c00417 	ldw	r3,16(r2)
+ 8025d00:	d0a06b17 	ldw	r2,-32340(gp)
+ 8025d04:	18800726 	beq	r3,r2,8025d24 <igmp_validate+0x1a0>
+         {
+            ++igmpstats.igmp_bad_queries_rcvd;
+ 8025d08:	008201b4 	movhi	r2,2054
+ 8025d0c:	10b78217 	ldw	r2,-8696(r2)
+ 8025d10:	10c00044 	addi	r3,r2,1
+ 8025d14:	008201b4 	movhi	r2,2054
+ 8025d18:	10f78215 	stw	r3,-8696(r2)
+            return ENP_BAD_HEADER;
+ 8025d1c:	00bff804 	movi	r2,-32
+ 8025d20:	00004a06 	br	8025e4c <igmp_validate+0x2c8>
+         }     
+      }
+      
+      if ((resp_time > 0) && (mcgrp_addr != 0))
+ 8025d24:	e0bff9c3 	ldbu	r2,-25(fp)
+ 8025d28:	10001926 	beq	r2,zero,8025d90 <igmp_validate+0x20c>
+ 8025d2c:	e0bffa17 	ldw	r2,-24(fp)
+ 8025d30:	10001726 	beq	r2,zero,8025d90 <igmp_validate+0x20c>
+      {
+         /* this is a IGMPv2 Group-Specific Query. */
+         if (p->net->igmp_oper_mode == IGMP_MODE_V1)
+ 8025d34:	e0bff817 	ldw	r2,-32(fp)
+ 8025d38:	10800617 	ldw	r2,24(r2)
+ 8025d3c:	10802f03 	ldbu	r2,188(r2)
+ 8025d40:	10803fcc 	andi	r2,r2,255
+ 8025d44:	10800058 	cmpnei	r2,r2,1
+ 8025d48:	1000021e 	bne	r2,zero,8025d54 <igmp_validate+0x1d0>
+         {
+            /* IGMPv1 code does not understand a IGMPv2 Group-
+             * Specific Query */
+            return ENP_BAD_HEADER; 
+ 8025d4c:	00bff804 	movi	r2,-32
+ 8025d50:	00003e06 	br	8025e4c <igmp_validate+0x2c8>
+         /* check to make sure that the group address field carries
+          * a valid multicast address; if it doesn't, we
+          * drop the packet.  Also drop packets that
+          * carry the multicast address for the all-hosts
+          * group. */
+         if ((!IN_MULTICAST(mcgrp_addr)) ||
+ 8025d54:	e0bffa17 	ldw	r2,-24(fp)
+ 8025d58:	10fc002c 	andhi	r3,r2,61440
+ 8025d5c:	00b80034 	movhi	r2,57344
+ 8025d60:	1880041e 	bne	r3,r2,8025d74 <igmp_validate+0x1f0>
+             /* igmp_all_hosts_group is already in network byte order */
+             (igmp->igmp_group == igmp_all_hosts_group))
+ 8025d64:	e0bffd17 	ldw	r2,-12(fp)
+ 8025d68:	10c00117 	ldw	r3,4(r2)
+ 8025d6c:	d0a06b17 	ldw	r2,-32340(gp)
+         if ((!IN_MULTICAST(mcgrp_addr)) ||
+ 8025d70:	1880071e 	bne	r3,r2,8025d90 <igmp_validate+0x20c>
+         {
+            ++igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd;
+ 8025d74:	008201b4 	movhi	r2,2054
+ 8025d78:	10b78517 	ldw	r2,-8684(r2)
+ 8025d7c:	10c00044 	addi	r3,r2,1
+ 8025d80:	008201b4 	movhi	r2,2054
+ 8025d84:	10f78515 	stw	r3,-8684(r2)
+            /* caller will free received packet */
+            return ENP_BAD_HEADER;
+ 8025d88:	00bff804 	movi	r2,-32
+ 8025d8c:	00002f06 	br	8025e4c <igmp_validate+0x2c8>
+   
+   /* check to ensure that a received IGMPv1 or v2 Report has the 
+    * same IP host group address in its IP destination field and 
+    * its IGMP group address field, and that the group address is
+    * a valid multicast address */
+   if ((type == IGMP_HOST_MEMBERSHIP_REPORT) ||
+ 8025d90:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025d94:	108004a0 	cmpeqi	r2,r2,18
+ 8025d98:	1000031e 	bne	r2,zero,8025da8 <igmp_validate+0x224>
+ 8025d9c:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025da0:	10800598 	cmpnei	r2,r2,22
+ 8025da4:	1000101e 	bne	r2,zero,8025de8 <igmp_validate+0x264>
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      if ((igmp->igmp_group != pip->ip_dest) ||
+ 8025da8:	e0bffd17 	ldw	r2,-12(fp)
+ 8025dac:	10c00117 	ldw	r3,4(r2)
+ 8025db0:	e0bfff17 	ldw	r2,-4(fp)
+ 8025db4:	10800417 	ldw	r2,16(r2)
+ 8025db8:	1880041e 	bne	r3,r2,8025dcc <igmp_validate+0x248>
+          (!IN_MULTICAST(mcgrp_addr)))
+ 8025dbc:	e0bffa17 	ldw	r2,-24(fp)
+ 8025dc0:	10fc002c 	andhi	r3,r2,61440
+      if ((igmp->igmp_group != pip->ip_dest) ||
+ 8025dc4:	00b80034 	movhi	r2,57344
+ 8025dc8:	18800726 	beq	r3,r2,8025de8 <igmp_validate+0x264>
+      {
+         ++igmpstats.igmp_bad_reports_rcvd;
+ 8025dcc:	008201b4 	movhi	r2,2054
+ 8025dd0:	10b78317 	ldw	r2,-8692(r2)
+ 8025dd4:	10c00044 	addi	r3,r2,1
+ 8025dd8:	008201b4 	movhi	r2,2054
+ 8025ddc:	10f78315 	stw	r3,-8692(r2)
+         return ENP_BAD_HEADER;    
+ 8025de0:	00bff804 	movi	r2,-32
+ 8025de4:	00001906 	br	8025e4c <igmp_validate+0x2c8>
+
+    * Version 1 Host Membership Reports and Version 1 Host Membership Query
+    * packets will not be checked for the IP Router Alert option.
+    */
+#ifdef IGMP_V2    
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+ 8025de8:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025dec:	108005e0 	cmpeqi	r2,r2,23
+ 8025df0:	10000a1e 	bne	r2,zero,8025e1c <igmp_validate+0x298>
+ 8025df4:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025df8:	108005a0 	cmpeqi	r2,r2,22
+ 8025dfc:	1000071e 	bne	r2,zero,8025e1c <igmp_validate+0x298>
+       (type == IGMPv2_MEMBERSHIP_REPORT) ||
+ 8025e00:	e0bffbc3 	ldbu	r2,-17(fp)
+ 8025e04:	10800458 	cmpnei	r2,r2,17
+ 8025e08:	10000f1e 	bne	r2,zero,8025e48 <igmp_validate+0x2c4>
+       ((type == IGMP_HOST_MEMBERSHIP_QUERY) && (igmp->igmp_code > 0)))
+ 8025e0c:	e0bffd17 	ldw	r2,-12(fp)
+ 8025e10:	10800043 	ldbu	r2,1(r2)
+ 8025e14:	10803fcc 	andi	r2,r2,255
+ 8025e18:	10000b26 	beq	r2,zero,8025e48 <igmp_validate+0x2c4>
+       
+   {
+      if (!igmpv2_chk4_rtr_alert_opt (pip))
+ 8025e1c:	e13fff17 	ldw	r4,-4(fp)
+ 8025e20:	803e5740 	call	803e574 <igmpv2_chk4_rtr_alert_opt>
+ 8025e24:	10803fcc 	andi	r2,r2,255
+ 8025e28:	1000071e 	bne	r2,zero,8025e48 <igmp_validate+0x2c4>
+      { 
+         ++igmpstats.igmpv2mode_v2_rtr_alert_missing;
+ 8025e2c:	008201b4 	movhi	r2,2054
+ 8025e30:	10b78817 	ldw	r2,-8672(r2)
+ 8025e34:	10c00044 	addi	r3,r2,1
+ 8025e38:	008201b4 	movhi	r2,2054
+ 8025e3c:	10f78815 	stw	r3,-8672(r2)
+         return ENP_BAD_HEADER;
+ 8025e40:	00bff804 	movi	r2,-32
+ 8025e44:	00000106 	br	8025e4c <igmp_validate+0x2c8>
+      }
+   }
+#endif   
+
+   /* validation successful */
+   return IGMP_OK;
+ 8025e48:	0005883a 	mov	r2,zero
+}
+ 8025e4c:	e037883a 	mov	sp,fp
+ 8025e50:	dfc00117 	ldw	ra,4(sp)
+ 8025e54:	df000017 	ldw	fp,0(sp)
+ 8025e58:	dec00204 	addi	sp,sp,8
+ 8025e5c:	f800283a 	ret
+
+08025e60 <igmp_print_stats>:
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+   
+int igmp_print_stats (void * pio)
+{  
+ 8025e60:	defffa04 	addi	sp,sp,-24
+ 8025e64:	dfc00515 	stw	ra,20(sp)
+ 8025e68:	df000415 	stw	fp,16(sp)
+ 8025e6c:	df000404 	addi	fp,sp,16
+ 8025e70:	e13ffe15 	stw	r4,-8(fp)
+   NET ifp;
+  
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8025e74:	008201b4 	movhi	r2,2054
+ 8025e78:	10b6a617 	ldw	r2,-9576(r2)
+ 8025e7c:	e0bfff15 	stw	r2,-4(fp)
+ 8025e80:	00003b06 	br	8025f70 <igmp_print_stats+0x110>
+   {
+      ns_printf (pio, "%s: mode: %u [%s] ", 
+                 ifp->name, 
+ 8025e84:	e0bfff17 	ldw	r2,-4(fp)
+ 8025e88:	10c00104 	addi	r3,r2,4
+                 ifp->igmp_oper_mode, 
+ 8025e8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8025e90:	10802f03 	ldbu	r2,188(r2)
+      ns_printf (pio, "%s: mode: %u [%s] ", 
+ 8025e94:	11003fcc 	andi	r4,r2,255
+                 ((ifp->igmp_oper_mode == IGMP_MODE_V1)? "v1":"v2"));
+ 8025e98:	e0bfff17 	ldw	r2,-4(fp)
+ 8025e9c:	10802f03 	ldbu	r2,188(r2)
+      ns_printf (pio, "%s: mode: %u [%s] ", 
+ 8025ea0:	10803fcc 	andi	r2,r2,255
+ 8025ea4:	10800058 	cmpnei	r2,r2,1
+ 8025ea8:	1000031e 	bne	r2,zero,8025eb8 <igmp_print_stats+0x58>
+ 8025eac:	00820174 	movhi	r2,2053
+ 8025eb0:	10a72e04 	addi	r2,r2,-25416
+ 8025eb4:	00000206 	br	8025ec0 <igmp_print_stats+0x60>
+ 8025eb8:	00820174 	movhi	r2,2053
+ 8025ebc:	10a72f04 	addi	r2,r2,-25412
+ 8025ec0:	d8800015 	stw	r2,0(sp)
+ 8025ec4:	200f883a 	mov	r7,r4
+ 8025ec8:	180d883a 	mov	r6,r3
+ 8025ecc:	01420174 	movhi	r5,2053
+ 8025ed0:	29673004 	addi	r5,r5,-25408
+ 8025ed4:	e13ffe17 	ldw	r4,-8(fp)
+ 8025ed8:	80273900 	call	8027390 <ns_printf>
+      /* if a link has been configured for IGMPv2, display the status
+       * of the v1 router-related variables too */
+      if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+ 8025edc:	e0bfff17 	ldw	r2,-4(fp)
+ 8025ee0:	10802f03 	ldbu	r2,188(r2)
+ 8025ee4:	10803fcc 	andi	r2,r2,255
+ 8025ee8:	10800098 	cmpnei	r2,r2,2
+ 8025eec:	1000191e 	bne	r2,zero,8025f54 <igmp_print_stats+0xf4>
+      {           
+         ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n",
+                    ifp->igmpv1_rtr_present,
+ 8025ef0:	e0bfff17 	ldw	r2,-4(fp)
+ 8025ef4:	10802d03 	ldbu	r2,180(r2)
+         ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n",
+ 8025ef8:	11403fcc 	andi	r5,r2,255
+                    ((ifp->igmpv1_rtr_present == IGMP_TRUE)? "present" : "absent"),
+ 8025efc:	e0bfff17 	ldw	r2,-4(fp)
+ 8025f00:	10802d03 	ldbu	r2,180(r2)
+         ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n",
+ 8025f04:	10803fcc 	andi	r2,r2,255
+ 8025f08:	10800058 	cmpnei	r2,r2,1
+ 8025f0c:	1000031e 	bne	r2,zero,8025f1c <igmp_print_stats+0xbc>
+ 8025f10:	00820174 	movhi	r2,2053
+ 8025f14:	10a73504 	addi	r2,r2,-25388
+ 8025f18:	00000206 	br	8025f24 <igmp_print_stats+0xc4>
+ 8025f1c:	00820174 	movhi	r2,2053
+ 8025f20:	10a73704 	addi	r2,r2,-25380
+ 8025f24:	e0ffff17 	ldw	r3,-4(fp)
+ 8025f28:	18c02e17 	ldw	r3,184(r3)
+ 8025f2c:	d1207d17 	ldw	r4,-32268(gp)
+ 8025f30:	d9000115 	stw	r4,4(sp)
+ 8025f34:	d8c00015 	stw	r3,0(sp)
+ 8025f38:	100f883a 	mov	r7,r2
+ 8025f3c:	280d883a 	mov	r6,r5
+ 8025f40:	01420174 	movhi	r5,2053
+ 8025f44:	29673904 	addi	r5,r5,-25372
+ 8025f48:	e13ffe17 	ldw	r4,-8(fp)
+ 8025f4c:	80273900 	call	8027390 <ns_printf>
+ 8025f50:	00000406 	br	8025f64 <igmp_print_stats+0x104>
+                    ifp->igmpv1_query_rcvd_time,
+                    cticks);
+      }
+      else ns_printf (pio, "\n");
+ 8025f54:	01420174 	movhi	r5,2053
+ 8025f58:	29674404 	addi	r5,r5,-25328
+ 8025f5c:	e13ffe17 	ldw	r4,-8(fp)
+ 8025f60:	80273900 	call	8027390 <ns_printf>
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8025f64:	e0bfff17 	ldw	r2,-4(fp)
+ 8025f68:	10800017 	ldw	r2,0(r2)
+ 8025f6c:	e0bfff15 	stw	r2,-4(fp)
+ 8025f70:	e0bfff17 	ldw	r2,-4(fp)
+ 8025f74:	103fc31e 	bne	r2,zero,8025e84 <igmp_print_stats+0x24>
+   }   
+
+   /* rx and timer statistics */
+   ns_printf (pio, "[Rx ] IGMP messages rcvd: %lu, timers running: %lu\n", igmpstats.igmp_total_rcvd, igmp_timers_are_running);
+ 8025f78:	008201b4 	movhi	r2,2054
+ 8025f7c:	10b77417 	ldw	r2,-8752(r2)
+ 8025f80:	d0e06917 	ldw	r3,-32348(gp)
+ 8025f84:	180f883a 	mov	r7,r3
+ 8025f88:	100d883a 	mov	r6,r2
+ 8025f8c:	01420174 	movhi	r5,2053
+ 8025f90:	29674504 	addi	r5,r5,-25324
+ 8025f94:	e13ffe17 	ldw	r4,-8(fp)
+ 8025f98:	80273900 	call	8027390 <ns_printf>
+   
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v1-mode links): %lu\n", igmpstats.igmpv1mode_v1_queries_rcvd);
+ 8025f9c:	008201b4 	movhi	r2,2054
+ 8025fa0:	10b77517 	ldw	r2,-8748(r2)
+ 8025fa4:	100d883a 	mov	r6,r2
+ 8025fa8:	01420174 	movhi	r5,2053
+ 8025fac:	29675204 	addi	r5,r5,-25272
+ 8025fb0:	e13ffe17 	ldw	r4,-8(fp)
+ 8025fb4:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Reports rcvd: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd);
+ 8025fb8:	008201b4 	movhi	r2,2054
+ 8025fbc:	10b77617 	ldw	r2,-8744(r2)
+ 8025fc0:	100d883a 	mov	r6,r2
+ 8025fc4:	01420174 	movhi	r5,2053
+ 8025fc8:	29676304 	addi	r5,r5,-25204
+ 8025fcc:	e13ffe17 	ldw	r4,-8(fp)
+ 8025fd0:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer);
+ 8025fd4:	008201b4 	movhi	r2,2054
+ 8025fd8:	10b77717 	ldw	r2,-8740(r2)
+ 8025fdc:	100d883a 	mov	r6,r2
+ 8025fe0:	01420174 	movhi	r5,2053
+ 8025fe4:	29676f04 	addi	r5,r5,-25156
+ 8025fe8:	e13ffe17 	ldw	r4,-8(fp)
+ 8025fec:	80273900 	call	8027390 <ns_printf>
+      
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v2-mode links): %lu\n", igmpstats.igmpv2mode_v1_queries_rcvd);
+ 8025ff0:	008201b4 	movhi	r2,2054
+ 8025ff4:	10b77817 	ldw	r2,-8736(r2)
+ 8025ff8:	100d883a 	mov	r6,r2
+ 8025ffc:	01420174 	movhi	r5,2053
+ 8026000:	29678204 	addi	r5,r5,-25080
+ 8026004:	e13ffe17 	ldw	r4,-8(fp)
+ 8026008:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMPv2 General Queries rcvd: %lu, Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_general_queries_rcvd, igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd);
+ 802600c:	008201b4 	movhi	r2,2054
+ 8026010:	10f77917 	ldw	r3,-8732(r2)
+ 8026014:	008201b4 	movhi	r2,2054
+ 8026018:	10b77a17 	ldw	r2,-8728(r2)
+ 802601c:	100f883a 	mov	r7,r2
+ 8026020:	180d883a 	mov	r6,r3
+ 8026024:	01420174 	movhi	r5,2053
+ 8026028:	29679304 	addi	r5,r5,-25012
+ 802602c:	e13ffe17 	ldw	r4,-8(fp)
+ 8026030:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer);   
+ 8026034:	008201b4 	movhi	r2,2054
+ 8026038:	10b77b17 	ldw	r2,-8724(r2)
+ 802603c:	100d883a 	mov	r6,r2
+ 8026040:	01420174 	movhi	r5,2053
+ 8026044:	29676f04 	addi	r5,r5,-25156
+ 8026048:	e13ffe17 	ldw	r4,-8(fp)
+ 802604c:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd with no local timer: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_no_timer);
+ 8026050:	008201b4 	movhi	r2,2054
+ 8026054:	10b77c17 	ldw	r2,-8720(r2)
+ 8026058:	100d883a 	mov	r6,r2
+ 802605c:	01420174 	movhi	r5,2053
+ 8026060:	2967a604 	addi	r5,r5,-24936
+ 8026064:	e13ffe17 	ldw	r4,-8(fp)
+ 8026068:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Rx ] IGMPv2 Leave Group messages rcvd: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_rcvd);
+ 802606c:	008201b4 	movhi	r2,2054
+ 8026070:	10b77d17 	ldw	r2,-8716(r2)
+ 8026074:	100d883a 	mov	r6,r2
+ 8026078:	01420174 	movhi	r5,2053
+ 802607c:	2967b704 	addi	r5,r5,-24868
+ 8026080:	e13ffe17 	ldw	r4,-8(fp)
+ 8026084:	80273900 	call	8027390 <ns_printf>
+   
+   /* tx statistics */
+   ns_printf (pio, "[Tx ] IGMPv2 Leave Group messages sent: %lu, Membership Reports sent: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_sent, igmpstats.igmpv2mode_v2_reports_sent);
+ 8026088:	008201b4 	movhi	r2,2054
+ 802608c:	10f78b17 	ldw	r3,-8660(r2)
+ 8026090:	008201b4 	movhi	r2,2054
+ 8026094:	10b78c17 	ldw	r2,-8656(r2)
+ 8026098:	100f883a 	mov	r7,r2
+ 802609c:	180d883a 	mov	r6,r3
+ 80260a0:	01420174 	movhi	r5,2053
+ 80260a4:	2967c304 	addi	r5,r5,-24820
+ 80260a8:	e13ffe17 	ldw	r4,-8(fp)
+ 80260ac:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Tx ] IGMPv1 Host Membership Reports sent: %lu\n", igmpstats.igmp_v1_reports_sent);
+ 80260b0:	008201b4 	movhi	r2,2054
+ 80260b4:	10b78a17 	ldw	r2,-8664(r2)
+ 80260b8:	100d883a 	mov	r6,r2
+ 80260bc:	01420174 	movhi	r5,2053
+ 80260c0:	2967d604 	addi	r5,r5,-24744
+ 80260c4:	e13ffe17 	ldw	r4,-8(fp)
+ 80260c8:	80273900 	call	8027390 <ns_printf>
+
+   /* error statistics */
+   ns_printf (pio, "[Err] IGMP packets rcvd with bad length: %lu\n", igmpstats.igmp_badlen_rcvd);
+ 80260cc:	008201b4 	movhi	r2,2054
+ 80260d0:	10b77e17 	ldw	r2,-8712(r2)
+ 80260d4:	100d883a 	mov	r6,r2
+ 80260d8:	01420174 	movhi	r5,2053
+ 80260dc:	2967e204 	addi	r5,r5,-24696
+ 80260e0:	e13ffe17 	ldw	r4,-8(fp)
+ 80260e4:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] IGMP packets rcvd with bad checksum: %lu\n", igmpstats.igmp_badsum_rcvd);
+ 80260e8:	008201b4 	movhi	r2,2054
+ 80260ec:	10b77f17 	ldw	r2,-8708(r2)
+ 80260f0:	100d883a 	mov	r6,r2
+ 80260f4:	01420174 	movhi	r5,2053
+ 80260f8:	2967ee04 	addi	r5,r5,-24648
+ 80260fc:	e13ffe17 	ldw	r4,-8(fp)
+ 8026100:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] Packet buffer allocation failures: %lu, Bad IGMP Oper Mode config: %lu\n",igmpstats.igmp_pkt_alloc_fail, igmpstats.igmp_bad_oper_mode);
+ 8026104:	008201b4 	movhi	r2,2054
+ 8026108:	10f78017 	ldw	r3,-8704(r2)
+ 802610c:	008201b4 	movhi	r2,2054
+ 8026110:	10b78117 	ldw	r2,-8700(r2)
+ 8026114:	100f883a 	mov	r7,r2
+ 8026118:	180d883a 	mov	r6,r3
+ 802611c:	01420174 	movhi	r5,2053
+ 8026120:	2967fa04 	addi	r5,r5,-24600
+ 8026124:	e13ffe17 	ldw	r4,-8(fp)
+ 8026128:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] Bad IGMP Queries rcvd: %lu, Bad IGMP Reports rcvd: %lu\n", igmpstats.igmp_bad_queries_rcvd, igmpstats.igmp_bad_reports_rcvd); 
+ 802612c:	008201b4 	movhi	r2,2054
+ 8026130:	10f78217 	ldw	r3,-8696(r2)
+ 8026134:	008201b4 	movhi	r2,2054
+ 8026138:	10b78317 	ldw	r2,-8692(r2)
+ 802613c:	100f883a 	mov	r7,r2
+ 8026140:	180d883a 	mov	r6,r3
+ 8026144:	01420174 	movhi	r5,2053
+ 8026148:	29680e04 	addi	r5,r5,-24520
+ 802614c:	e13ffe17 	ldw	r4,-8(fp)
+ 8026150:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] Bad IGMPv2 Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd);
+ 8026154:	008201b4 	movhi	r2,2054
+ 8026158:	10b78517 	ldw	r2,-8684(r2)
+ 802615c:	100d883a 	mov	r6,r2
+ 8026160:	01420174 	movhi	r5,2053
+ 8026164:	29681e04 	addi	r5,r5,-24456
+ 8026168:	e13ffe17 	ldw	r4,-8(fp)
+ 802616c:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] IGMPv2 Group-Specific Queries rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd);
+ 8026170:	008201b4 	movhi	r2,2054
+ 8026174:	10b78617 	ldw	r2,-8680(r2)
+ 8026178:	100d883a 	mov	r6,r2
+ 802617c:	01420174 	movhi	r5,2053
+ 8026180:	29682b04 	addi	r5,r5,-24404
+ 8026184:	e13ffe17 	ldw	r4,-8(fp)
+ 8026188:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] IGMP Membership Reports rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd);
+ 802618c:	008201b4 	movhi	r2,2054
+ 8026190:	10b78717 	ldw	r2,-8676(r2)
+ 8026194:	100d883a 	mov	r6,r2
+ 8026198:	01420174 	movhi	r5,2053
+ 802619c:	29683e04 	addi	r5,r5,-24328
+ 80261a0:	e13ffe17 	ldw	r4,-8(fp)
+ 80261a4:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] Number of IGMPv2 messages rcvd without Router Alert option: %lu\n", igmpstats.igmpv2mode_v2_rtr_alert_missing); 
+ 80261a8:	008201b4 	movhi	r2,2054
+ 80261ac:	10b78817 	ldw	r2,-8672(r2)
+ 80261b0:	100d883a 	mov	r6,r2
+ 80261b4:	01420174 	movhi	r5,2053
+ 80261b8:	29684f04 	addi	r5,r5,-24260
+ 80261bc:	e13ffe17 	ldw	r4,-8(fp)
+ 80261c0:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v1-mode links: %lu\n", igmpstats.igmpv1mode_unknown_pkttype);
+ 80261c4:	008201b4 	movhi	r2,2054
+ 80261c8:	10b78417 	ldw	r2,-8688(r2)
+ 80261cc:	100d883a 	mov	r6,r2
+ 80261d0:	01420174 	movhi	r5,2053
+ 80261d4:	29686104 	addi	r5,r5,-24188
+ 80261d8:	e13ffe17 	ldw	r4,-8(fp)
+ 80261dc:	80273900 	call	8027390 <ns_printf>
+   ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v2-mode links: %lu\n", igmpstats.igmpv2mode_unknown_pkttype);
+ 80261e0:	008201b4 	movhi	r2,2054
+ 80261e4:	10b78917 	ldw	r2,-8668(r2)
+ 80261e8:	100d883a 	mov	r6,r2
+ 80261ec:	01420174 	movhi	r5,2053
+ 80261f0:	29687104 	addi	r5,r5,-24124
+ 80261f4:	e13ffe17 	ldw	r4,-8(fp)
+ 80261f8:	80273900 	call	8027390 <ns_printf>
+   
+   return IGMP_OK;
+ 80261fc:	0005883a 	mov	r2,zero
+}
+ 8026200:	e037883a 	mov	sp,fp
+ 8026204:	dfc00117 	ldw	ra,4(sp)
+ 8026208:	df000017 	ldw	fp,0(sp)
+ 802620c:	dec00204 	addi	sp,sp,8
+ 8026210:	f800283a 	ret
+
+08026214 <bsd_accept>:
+ *          The error is available via bsd_errno(s).
+ */
+BSD_SOCKET
+bsd_accept(BSD_SOCKET s,
+           struct sockaddr * addr, int * addrlen)
+{
+ 8026214:	defff404 	addi	sp,sp,-48
+ 8026218:	dfc00b15 	stw	ra,44(sp)
+ 802621c:	df000a15 	stw	fp,40(sp)
+ 8026220:	df000a04 	addi	fp,sp,40
+ 8026224:	e13ff815 	stw	r4,-32(fp)
+ 8026228:	e17ff715 	stw	r5,-36(fp)
+ 802622c:	e1bff615 	stw	r6,-40(fp)
+   struct socket * so;
+   struct sockaddr laddr;
+   long lret;
+
+   so = LONG2SO(s);
+ 8026230:	e0bff817 	ldw	r2,-32(fp)
+ 8026234:	10bffc04 	addi	r2,r2,-16
+ 8026238:	100490ba 	slli	r2,r2,2
+ 802623c:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026240:	008201b4 	movhi	r2,2054
+ 8026244:	10b87104 	addi	r2,r2,-7740
+ 8026248:	e0bfff15 	stw	r2,-4(fp)
+ 802624c:	00000606 	br	8026268 <bsd_accept+0x54>
+ 8026250:	e0ffff17 	ldw	r3,-4(fp)
+ 8026254:	e0bffe17 	ldw	r2,-8(fp)
+ 8026258:	18800626 	beq	r3,r2,8026274 <bsd_accept+0x60>
+ 802625c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026260:	10800017 	ldw	r2,0(r2)
+ 8026264:	e0bfff15 	stw	r2,-4(fp)
+ 8026268:	e0bfff17 	ldw	r2,-4(fp)
+ 802626c:	103ff81e 	bne	r2,zero,8026250 <bsd_accept+0x3c>
+ 8026270:	00000106 	br	8026278 <bsd_accept+0x64>
+ 8026274:	0001883a 	nop
+ 8026278:	e0ffff17 	ldw	r3,-4(fp)
+ 802627c:	e0bffe17 	ldw	r2,-8(fp)
+ 8026280:	18800326 	beq	r3,r2,8026290 <bsd_accept+0x7c>
+ 8026284:	8028cd40 	call	8028cd4 <dtrap>
+ 8026288:	00bfffc4 	movi	r2,-1
+ 802628c:	00002406 	br	8026320 <bsd_accept+0x10c>
+
+   /* if we were given a buffer for the peer's address, also get the
+    * buffer's length 
+    */
+   if (addr != NULL)
+ 8026290:	e0bff717 	ldw	r2,-36(fp)
+ 8026294:	10000726 	beq	r2,zero,80262b4 <bsd_accept+0xa0>
+   {
+      if (addrlen == 0)
+ 8026298:	e0bff617 	ldw	r2,-40(fp)
+ 802629c:	1000051e 	bne	r2,zero,80262b4 <bsd_accept+0xa0>
+      {
+         so->so_error = EFAULT;
+ 80262a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80262a4:	00c00384 	movi	r3,14
+ 80262a8:	10c00615 	stw	r3,24(r2)
+         return -1;
+ 80262ac:	00bfffc4 	movi	r2,-1
+ 80262b0:	00001b06 	br	8026320 <bsd_accept+0x10c>
+      }
+   }
+
+   lret = t_accept(s, &laddr, addrlen);
+ 80262b4:	e0bff904 	addi	r2,fp,-28
+ 80262b8:	e1bff617 	ldw	r6,-40(fp)
+ 80262bc:	100b883a 	mov	r5,r2
+ 80262c0:	e13ff817 	ldw	r4,-32(fp)
+ 80262c4:	802bd240 	call	802bd24 <t_accept>
+ 80262c8:	e0bffd15 	stw	r2,-12(fp)
+    * address: copy the peer's address back into the buffer, but limit
+    * the copy to the lesser of the buffer's length and sizeof(struct
+    * sockaddr_in), which is all that t_accept() can return as a peer
+    * address.  
+    */
+   if ((lret != -1) && (addr != NULL))
+ 80262cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80262d0:	10bfffe0 	cmpeqi	r2,r2,-1
+ 80262d4:	1000111e 	bne	r2,zero,802631c <bsd_accept+0x108>
+ 80262d8:	e0bff717 	ldw	r2,-36(fp)
+ 80262dc:	10000f26 	beq	r2,zero,802631c <bsd_accept+0x108>
+   {
+      if (*addrlen > sizeof(struct sockaddr_in))
+ 80262e0:	e0bff617 	ldw	r2,-40(fp)
+ 80262e4:	10800017 	ldw	r2,0(r2)
+ 80262e8:	10800470 	cmpltui	r2,r2,17
+ 80262ec:	1000031e 	bne	r2,zero,80262fc <bsd_accept+0xe8>
+         *addrlen = sizeof(struct sockaddr_in);
+ 80262f0:	e0bff617 	ldw	r2,-40(fp)
+ 80262f4:	00c00404 	movi	r3,16
+ 80262f8:	10c00015 	stw	r3,0(r2)
+      MEMCPY(addr, &laddr, *addrlen);
+ 80262fc:	e0bff617 	ldw	r2,-40(fp)
+ 8026300:	10800017 	ldw	r2,0(r2)
+ 8026304:	1007883a 	mov	r3,r2
+ 8026308:	e0bff904 	addi	r2,fp,-28
+ 802630c:	180d883a 	mov	r6,r3
+ 8026310:	100b883a 	mov	r5,r2
+ 8026314:	e13ff717 	ldw	r4,-36(fp)
+ 8026318:	80086b80 	call	80086b8 <memcpy>
+   }
+
+   return lret;
+ 802631c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8026320:	e037883a 	mov	sp,fp
+ 8026324:	dfc00117 	ldw	ra,4(sp)
+ 8026328:	df000017 	ldw	fp,0(sp)
+ 802632c:	dec00204 	addi	sp,sp,8
+ 8026330:	f800283a 	ret
+
+08026334 <bsd_getpeername>:
+ *          available via bsd_errno(s).
+ */
+int
+bsd_getpeername(BSD_SOCKET s,
+                struct sockaddr * name, int * namelen)
+{
+ 8026334:	defff304 	addi	sp,sp,-52
+ 8026338:	dfc00c15 	stw	ra,48(sp)
+ 802633c:	df000b15 	stw	fp,44(sp)
+ 8026340:	df000b04 	addi	fp,sp,44
+ 8026344:	e13ff715 	stw	r4,-36(fp)
+ 8026348:	e17ff615 	stw	r5,-40(fp)
+ 802634c:	e1bff515 	stw	r6,-44(fp)
+   struct socket * so;
+   struct sockaddr lname;
+   int lnamelen;
+   int lret;
+
+   so = LONG2SO(s);
+ 8026350:	e0bff717 	ldw	r2,-36(fp)
+ 8026354:	10bffc04 	addi	r2,r2,-16
+ 8026358:	100490ba 	slli	r2,r2,2
+ 802635c:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026360:	008201b4 	movhi	r2,2054
+ 8026364:	10b87104 	addi	r2,r2,-7740
+ 8026368:	e0bfff15 	stw	r2,-4(fp)
+ 802636c:	00000606 	br	8026388 <bsd_getpeername+0x54>
+ 8026370:	e0ffff17 	ldw	r3,-4(fp)
+ 8026374:	e0bffe17 	ldw	r2,-8(fp)
+ 8026378:	18800626 	beq	r3,r2,8026394 <bsd_getpeername+0x60>
+ 802637c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026380:	10800017 	ldw	r2,0(r2)
+ 8026384:	e0bfff15 	stw	r2,-4(fp)
+ 8026388:	e0bfff17 	ldw	r2,-4(fp)
+ 802638c:	103ff81e 	bne	r2,zero,8026370 <bsd_getpeername+0x3c>
+ 8026390:	00000106 	br	8026398 <bsd_getpeername+0x64>
+ 8026394:	0001883a 	nop
+ 8026398:	e0ffff17 	ldw	r3,-4(fp)
+ 802639c:	e0bffe17 	ldw	r2,-8(fp)
+ 80263a0:	18800326 	beq	r3,r2,80263b0 <bsd_getpeername+0x7c>
+ 80263a4:	8028cd40 	call	8028cd4 <dtrap>
+ 80263a8:	00bfffc4 	movi	r2,-1
+ 80263ac:	00002406 	br	8026440 <bsd_getpeername+0x10c>
+
+   /* if the buffer length is bogus, fail */
+   if (namelen == NULL)
+ 80263b0:	e0bff517 	ldw	r2,-44(fp)
+ 80263b4:	1000051e 	bne	r2,zero,80263cc <bsd_getpeername+0x98>
+   {
+      so->so_error = EFAULT;
+ 80263b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80263bc:	00c00384 	movi	r3,14
+ 80263c0:	10c00615 	stw	r3,24(r2)
+      return -1;
+ 80263c4:	00bfffc4 	movi	r2,-1
+ 80263c8:	00001d06 	br	8026440 <bsd_getpeername+0x10c>
+   }
+   lnamelen = *namelen;
+ 80263cc:	e0bff517 	ldw	r2,-44(fp)
+ 80263d0:	10800017 	ldw	r2,0(r2)
+ 80263d4:	e0bff815 	stw	r2,-32(fp)
+
+   lret = t_getpeername(s, &lname, &lnamelen);
+ 80263d8:	e0fff804 	addi	r3,fp,-32
+ 80263dc:	e0bff904 	addi	r2,fp,-28
+ 80263e0:	180d883a 	mov	r6,r3
+ 80263e4:	100b883a 	mov	r5,r2
+ 80263e8:	e13ff717 	ldw	r4,-36(fp)
+ 80263ec:	802c1e40 	call	802c1e4 <t_getpeername>
+ 80263f0:	e0bffd15 	stw	r2,-12(fp)
+    * t_getpeername() can return as a peer address, and pass the
+    * copied length back to the caller.  
+    * For IPV6 addresses, or for dual IPV4/IPV6 stack, 
+    * the max size is sizeof(struct sockaddr_in6)
+    */
+   if (lret != -1)
+ 80263f4:	e0bffd17 	ldw	r2,-12(fp)
+ 80263f8:	10bfffe0 	cmpeqi	r2,r2,-1
+ 80263fc:	10000f1e 	bne	r2,zero,802643c <bsd_getpeername+0x108>
+   {
+#ifndef IP_V6
+      if (lnamelen > sizeof(struct sockaddr_in))
+ 8026400:	e0bff817 	ldw	r2,-32(fp)
+ 8026404:	10800470 	cmpltui	r2,r2,17
+ 8026408:	1000021e 	bne	r2,zero,8026414 <bsd_getpeername+0xe0>
+         lnamelen = sizeof(struct sockaddr_in);
+ 802640c:	00800404 	movi	r2,16
+ 8026410:	e0bff815 	stw	r2,-32(fp)
+#else
+      if (lnamelen > sizeof(struct sockaddr_in6))
+         lnamelen = sizeof(struct sockaddr_in6);
+
+#endif
+      MEMCPY(name, &lname, lnamelen);
+ 8026414:	e0bff817 	ldw	r2,-32(fp)
+ 8026418:	1007883a 	mov	r3,r2
+ 802641c:	e0bff904 	addi	r2,fp,-28
+ 8026420:	180d883a 	mov	r6,r3
+ 8026424:	100b883a 	mov	r5,r2
+ 8026428:	e13ff617 	ldw	r4,-40(fp)
+ 802642c:	80086b80 	call	80086b8 <memcpy>
+      *namelen = lnamelen;
+ 8026430:	e0fff817 	ldw	r3,-32(fp)
+ 8026434:	e0bff517 	ldw	r2,-44(fp)
+ 8026438:	10c00015 	stw	r3,0(r2)
+   }
+
+   return lret;
+ 802643c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8026440:	e037883a 	mov	sp,fp
+ 8026444:	dfc00117 	ldw	ra,4(sp)
+ 8026448:	df000017 	ldw	fp,0(sp)
+ 802644c:	dec00204 	addi	sp,sp,8
+ 8026450:	f800283a 	ret
+
+08026454 <bsd_getsockname>:
+ *          available via bsd_errno(s).
+ */
+int
+bsd_getsockname(BSD_SOCKET s,
+                struct sockaddr * name, int * namelen)
+{
+ 8026454:	defff304 	addi	sp,sp,-52
+ 8026458:	dfc00c15 	stw	ra,48(sp)
+ 802645c:	df000b15 	stw	fp,44(sp)
+ 8026460:	df000b04 	addi	fp,sp,44
+ 8026464:	e13ff715 	stw	r4,-36(fp)
+ 8026468:	e17ff615 	stw	r5,-40(fp)
+ 802646c:	e1bff515 	stw	r6,-44(fp)
+   struct socket * so;
+   struct sockaddr lname;
+   int lnamelen;
+   int lret;
+
+   so = LONG2SO(s);
+ 8026470:	e0bff717 	ldw	r2,-36(fp)
+ 8026474:	10bffc04 	addi	r2,r2,-16
+ 8026478:	100490ba 	slli	r2,r2,2
+ 802647c:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026480:	008201b4 	movhi	r2,2054
+ 8026484:	10b87104 	addi	r2,r2,-7740
+ 8026488:	e0bfff15 	stw	r2,-4(fp)
+ 802648c:	00000606 	br	80264a8 <bsd_getsockname+0x54>
+ 8026490:	e0ffff17 	ldw	r3,-4(fp)
+ 8026494:	e0bffe17 	ldw	r2,-8(fp)
+ 8026498:	18800626 	beq	r3,r2,80264b4 <bsd_getsockname+0x60>
+ 802649c:	e0bfff17 	ldw	r2,-4(fp)
+ 80264a0:	10800017 	ldw	r2,0(r2)
+ 80264a4:	e0bfff15 	stw	r2,-4(fp)
+ 80264a8:	e0bfff17 	ldw	r2,-4(fp)
+ 80264ac:	103ff81e 	bne	r2,zero,8026490 <bsd_getsockname+0x3c>
+ 80264b0:	00000106 	br	80264b8 <bsd_getsockname+0x64>
+ 80264b4:	0001883a 	nop
+ 80264b8:	e0ffff17 	ldw	r3,-4(fp)
+ 80264bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80264c0:	18800326 	beq	r3,r2,80264d0 <bsd_getsockname+0x7c>
+ 80264c4:	8028cd40 	call	8028cd4 <dtrap>
+ 80264c8:	00bfffc4 	movi	r2,-1
+ 80264cc:	00002406 	br	8026560 <bsd_getsockname+0x10c>
+
+   /* if the buffer length is bogus, fail */
+   if (namelen == NULL)
+ 80264d0:	e0bff517 	ldw	r2,-44(fp)
+ 80264d4:	1000051e 	bne	r2,zero,80264ec <bsd_getsockname+0x98>
+   {
+      so->so_error = EFAULT;
+ 80264d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80264dc:	00c00384 	movi	r3,14
+ 80264e0:	10c00615 	stw	r3,24(r2)
+      return -1;
+ 80264e4:	00bfffc4 	movi	r2,-1
+ 80264e8:	00001d06 	br	8026560 <bsd_getsockname+0x10c>
+   }
+   lnamelen = *namelen;
+ 80264ec:	e0bff517 	ldw	r2,-44(fp)
+ 80264f0:	10800017 	ldw	r2,0(r2)
+ 80264f4:	e0bff815 	stw	r2,-32(fp)
+
+   lret = t_getsockname(s, &lname, &lnamelen);
+ 80264f8:	e0fff804 	addi	r3,fp,-32
+ 80264fc:	e0bff904 	addi	r2,fp,-28
+ 8026500:	180d883a 	mov	r6,r3
+ 8026504:	100b883a 	mov	r5,r2
+ 8026508:	e13ff717 	ldw	r4,-36(fp)
+ 802650c:	802c2280 	call	802c228 <t_getsockname>
+ 8026510:	e0bffd15 	stw	r2,-12(fp)
+    * copied length back to the caller.  
+    * For IPV6 addresses, or for a dual IPV4/IPV6 stack, 
+    * the max size copied is sizeof(struct sockaddr_in6)
+    *
+    */
+   if (lret != -1)
+ 8026514:	e0bffd17 	ldw	r2,-12(fp)
+ 8026518:	10bfffe0 	cmpeqi	r2,r2,-1
+ 802651c:	10000f1e 	bne	r2,zero,802655c <bsd_getsockname+0x108>
+   {
+#ifndef IP_V6
+      if (lnamelen > sizeof(struct sockaddr_in))
+ 8026520:	e0bff817 	ldw	r2,-32(fp)
+ 8026524:	10800470 	cmpltui	r2,r2,17
+ 8026528:	1000021e 	bne	r2,zero,8026534 <bsd_getsockname+0xe0>
+         lnamelen = sizeof(struct sockaddr_in);
+ 802652c:	00800404 	movi	r2,16
+ 8026530:	e0bff815 	stw	r2,-32(fp)
+#else
+      if (lnamelen > sizeof(struct sockaddr_in6))
+         lnamelen = sizeof(struct sockaddr_in6);
+#endif
+      MEMCPY(name, &lname, lnamelen);
+ 8026534:	e0bff817 	ldw	r2,-32(fp)
+ 8026538:	1007883a 	mov	r3,r2
+ 802653c:	e0bff904 	addi	r2,fp,-28
+ 8026540:	180d883a 	mov	r6,r3
+ 8026544:	100b883a 	mov	r5,r2
+ 8026548:	e13ff617 	ldw	r4,-40(fp)
+ 802654c:	80086b80 	call	80086b8 <memcpy>
+      *namelen = lnamelen;
+ 8026550:	e0fff817 	ldw	r3,-32(fp)
+ 8026554:	e0bff517 	ldw	r2,-44(fp)
+ 8026558:	10c00015 	stw	r3,0(r2)
+   }
+
+   return lret;
+ 802655c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8026560:	e037883a 	mov	sp,fp
+ 8026564:	dfc00117 	ldw	ra,4(sp)
+ 8026568:	df000017 	ldw	fp,0(sp)
+ 802656c:	dec00204 	addi	sp,sp,8
+ 8026570:	f800283a 	ret
+
+08026574 <bsd_i_sockoptlen>:
+ * RETURNS: minimum length of the named socket option, in bytes
+ */
+int 
+bsd_i_sockoptlen(int level,
+                 int name)
+{
+ 8026574:	defffd04 	addi	sp,sp,-12
+ 8026578:	df000215 	stw	fp,8(sp)
+ 802657c:	df000204 	addi	fp,sp,8
+ 8026580:	e13fff15 	stw	r4,-4(fp)
+ 8026584:	e17ffe15 	stw	r5,-8(fp)
+   USE_ARG(level);
+
+   switch (name)
+ 8026588:	e0bffe17 	ldw	r2,-8(fp)
+ 802658c:	10802020 	cmpeqi	r2,r2,128
+ 8026590:	1000491e 	bne	r2,zero,80266b8 <bsd_i_sockoptlen+0x144>
+ 8026594:	e0bffe17 	ldw	r2,-8(fp)
+ 8026598:	10802048 	cmpgei	r2,r2,129
+ 802659c:	1000251e 	bne	r2,zero,8026634 <bsd_i_sockoptlen+0xc0>
+ 80265a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80265a4:	10800308 	cmpgei	r2,r2,12
+ 80265a8:	1000141e 	bne	r2,zero,80265fc <bsd_i_sockoptlen+0x88>
+ 80265ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80265b0:	10800288 	cmpgei	r2,r2,10
+ 80265b4:	1000481e 	bne	r2,zero,80266d8 <bsd_i_sockoptlen+0x164>
+ 80265b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80265bc:	10800120 	cmpeqi	r2,r2,4
+ 80265c0:	1000411e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 80265c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80265c8:	10800148 	cmpgei	r2,r2,5
+ 80265cc:	1000041e 	bne	r2,zero,80265e0 <bsd_i_sockoptlen+0x6c>
+ 80265d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80265d4:	108000e0 	cmpeqi	r2,r2,3
+ 80265d8:	1000431e 	bne	r2,zero,80266e8 <bsd_i_sockoptlen+0x174>
+ 80265dc:	00004406 	br	80266f0 <bsd_i_sockoptlen+0x17c>
+ 80265e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80265e4:	10800220 	cmpeqi	r2,r2,8
+ 80265e8:	1000371e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 80265ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80265f0:	10800260 	cmpeqi	r2,r2,9
+ 80265f4:	1000361e 	bne	r2,zero,80266d0 <bsd_i_sockoptlen+0x15c>
+ 80265f8:	00003d06 	br	80266f0 <bsd_i_sockoptlen+0x17c>
+ 80265fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8026600:	10800420 	cmpeqi	r2,r2,16
+ 8026604:	1000301e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 8026608:	e0bffe17 	ldw	r2,-8(fp)
+ 802660c:	10800448 	cmpgei	r2,r2,17
+ 8026610:	1000041e 	bne	r2,zero,8026624 <bsd_i_sockoptlen+0xb0>
+ 8026614:	e0bffe17 	ldw	r2,-8(fp)
+ 8026618:	10800388 	cmpgei	r2,r2,14
+ 802661c:	1000341e 	bne	r2,zero,80266f0 <bsd_i_sockoptlen+0x17c>
+ 8026620:	00002f06 	br	80266e0 <bsd_i_sockoptlen+0x16c>
+ 8026624:	e0bffe17 	ldw	r2,-8(fp)
+ 8026628:	10800820 	cmpeqi	r2,r2,32
+ 802662c:	1000261e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 8026630:	00002f06 	br	80266f0 <bsd_i_sockoptlen+0x17c>
+ 8026634:	e0bffe17 	ldw	r2,-8(fp)
+ 8026638:	108401c8 	cmpgei	r2,r2,4103
+ 802663c:	10000e1e 	bne	r2,zero,8026678 <bsd_i_sockoptlen+0x104>
+ 8026640:	e0bffe17 	ldw	r2,-8(fp)
+ 8026644:	10840148 	cmpgei	r2,r2,4101
+ 8026648:	10001d1e 	bne	r2,zero,80266c0 <bsd_i_sockoptlen+0x14c>
+ 802664c:	e0bffe17 	ldw	r2,-8(fp)
+ 8026650:	10804020 	cmpeqi	r2,r2,256
+ 8026654:	10001c1e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 8026658:	e0bffe17 	ldw	r2,-8(fp)
+ 802665c:	10804010 	cmplti	r2,r2,256
+ 8026660:	1000231e 	bne	r2,zero,80266f0 <bsd_i_sockoptlen+0x17c>
+ 8026664:	e0bffe17 	ldw	r2,-8(fp)
+ 8026668:	10bbffc4 	addi	r2,r2,-4097
+ 802666c:	108000a8 	cmpgeui	r2,r2,2
+ 8026670:	10001f1e 	bne	r2,zero,80266f0 <bsd_i_sockoptlen+0x17c>
+ 8026674:	00001406 	br	80266c8 <bsd_i_sockoptlen+0x154>
+ 8026678:	e0bffe17 	ldw	r2,-8(fp)
+ 802667c:	10840588 	cmpgei	r2,r2,4118
+ 8026680:	1000071e 	bne	r2,zero,80266a0 <bsd_i_sockoptlen+0x12c>
+ 8026684:	e0bffe17 	ldw	r2,-8(fp)
+ 8026688:	10840508 	cmpgei	r2,r2,4116
+ 802668c:	1000081e 	bne	r2,zero,80266b0 <bsd_i_sockoptlen+0x13c>
+ 8026690:	e0bffe17 	ldw	r2,-8(fp)
+ 8026694:	10840248 	cmpgei	r2,r2,4105
+ 8026698:	1000151e 	bne	r2,zero,80266f0 <bsd_i_sockoptlen+0x17c>
+ 802669c:	00000a06 	br	80266c8 <bsd_i_sockoptlen+0x154>
+ 80266a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80266a4:	108405a0 	cmpeqi	r2,r2,4118
+ 80266a8:	1000071e 	bne	r2,zero,80266c8 <bsd_i_sockoptlen+0x154>
+ 80266ac:	00001006 	br	80266f0 <bsd_i_sockoptlen+0x17c>
+   {
+   case SO_BIO:
+   case SO_NBIO:
+      /* these don't use an option value */
+      return 0;
+ 80266b0:	0005883a 	mov	r2,zero
+ 80266b4:	00000f06 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   case SO_LINGER:
+      /* this option is a struct linger */
+      return sizeof(struct linger);
+ 80266b8:	00800204 	movi	r2,8
+ 80266bc:	00000d06 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   case SO_RCVTIMEO:
+   case SO_SNDTIMEO:
+      /* these options are type short */
+      return sizeof(short);
+ 80266c0:	00800084 	movi	r2,2
+ 80266c4:	00000b06 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   case SO_RCVBUF:
+   case SO_NONBLOCK:
+   case SO_ERROR:
+   case SO_TYPE:
+      /* these options are type int */
+      return sizeof(int);
+ 80266c8:	00800104 	movi	r2,4
+ 80266cc:	00000906 	br	80266f4 <bsd_i_sockoptlen+0x180>
+      return sizeof(int (*)());
+#endif /* TCP_ZEROCOPY */
+#ifdef IP_MULTICAST
+   case IP_MULTICAST_IF:
+      /* this option is type ip_addr */
+      return sizeof(ip_addr);
+ 80266d0:	00800104 	movi	r2,4
+ 80266d4:	00000706 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+      /* these options are type u_char */
+      return sizeof(u_char);
+ 80266d8:	00800044 	movi	r2,1
+ 80266dc:	00000506 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   case IP_ADD_MEMBERSHIP:
+   case IP_DROP_MEMBERSHIP:
+      /* these options are struct ip_mreq */
+      return sizeof(struct ip_mreq);
+ 80266e0:	00800204 	movi	r2,8
+ 80266e4:	00000306 	br	80266f4 <bsd_i_sockoptlen+0x180>
+ * IP_TTL_OPT == SOREUSEADDR. This causes a build erro
+ * due to duplicate cases. Removing this one. They both
+ * return the same value (sizeof(int)).
+ */
+  // case IP_TTL_OPT:
+      return sizeof(int);
+ 80266e8:	00800104 	movi	r2,4
+ 80266ec:	00000106 	br	80266f4 <bsd_i_sockoptlen+0x180>
+   default:
+      /* we don't know what type these options are */
+      return 0;
+ 80266f0:	0005883a 	mov	r2,zero
+   }
+   
+}
+ 80266f4:	e037883a 	mov	sp,fp
+ 80266f8:	df000017 	ldw	fp,0(sp)
+ 80266fc:	dec00104 	addi	sp,sp,4
+ 8026700:	f800283a 	ret
+
+08026704 <bsd_getsockopt>:
+int
+bsd_getsockopt(BSD_SOCKET s,
+               int level,
+               int name,
+               void * opt, int * optlen)
+{
+ 8026704:	defff504 	addi	sp,sp,-44
+ 8026708:	dfc00a15 	stw	ra,40(sp)
+ 802670c:	df000915 	stw	fp,36(sp)
+ 8026710:	df000904 	addi	fp,sp,36
+ 8026714:	e13ffb15 	stw	r4,-20(fp)
+ 8026718:	e17ffa15 	stw	r5,-24(fp)
+ 802671c:	e1bff915 	stw	r6,-28(fp)
+ 8026720:	e1fff815 	stw	r7,-32(fp)
+   struct socket * so;
+   int loptlen;
+   int e;
+
+   so = LONG2SO(s);
+ 8026724:	e0bffb17 	ldw	r2,-20(fp)
+ 8026728:	10bffc04 	addi	r2,r2,-16
+ 802672c:	100490ba 	slli	r2,r2,2
+ 8026730:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026734:	008201b4 	movhi	r2,2054
+ 8026738:	10b87104 	addi	r2,r2,-7740
+ 802673c:	e0bfff15 	stw	r2,-4(fp)
+ 8026740:	00000606 	br	802675c <bsd_getsockopt+0x58>
+ 8026744:	e0ffff17 	ldw	r3,-4(fp)
+ 8026748:	e0bffe17 	ldw	r2,-8(fp)
+ 802674c:	18800626 	beq	r3,r2,8026768 <bsd_getsockopt+0x64>
+ 8026750:	e0bfff17 	ldw	r2,-4(fp)
+ 8026754:	10800017 	ldw	r2,0(r2)
+ 8026758:	e0bfff15 	stw	r2,-4(fp)
+ 802675c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026760:	103ff81e 	bne	r2,zero,8026744 <bsd_getsockopt+0x40>
+ 8026764:	00000106 	br	802676c <bsd_getsockopt+0x68>
+ 8026768:	0001883a 	nop
+ 802676c:	e0ffff17 	ldw	r3,-4(fp)
+ 8026770:	e0bffe17 	ldw	r2,-8(fp)
+ 8026774:	18800326 	beq	r3,r2,8026784 <bsd_getsockopt+0x80>
+ 8026778:	8028cd40 	call	8028cd4 <dtrap>
+ 802677c:	00bfffc4 	movi	r2,-1
+ 8026780:	00001d06 	br	80267f8 <bsd_getsockopt+0xf4>
+
+   /* make sure supplied option value is big enough for the 
+    * named option, else fail w/error EFAULT
+    */
+   loptlen = bsd_i_sockoptlen(level, name);
+ 8026784:	e17ff917 	ldw	r5,-28(fp)
+ 8026788:	e13ffa17 	ldw	r4,-24(fp)
+ 802678c:	80265740 	call	8026574 <bsd_i_sockoptlen>
+ 8026790:	e0bffd15 	stw	r2,-12(fp)
+   if ((optlen == NULL) || (*optlen < loptlen))
+ 8026794:	e0800217 	ldw	r2,8(fp)
+ 8026798:	10000426 	beq	r2,zero,80267ac <bsd_getsockopt+0xa8>
+ 802679c:	e0800217 	ldw	r2,8(fp)
+ 80267a0:	10c00017 	ldw	r3,0(r2)
+ 80267a4:	e0bffd17 	ldw	r2,-12(fp)
+ 80267a8:	1880050e 	bge	r3,r2,80267c0 <bsd_getsockopt+0xbc>
+   {
+      so->so_error = EFAULT;
+ 80267ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80267b0:	00c00384 	movi	r3,14
+ 80267b4:	10c00615 	stw	r3,24(r2)
+      return -1;
+ 80267b8:	00bfffc4 	movi	r2,-1
+ 80267bc:	00000e06 	br	80267f8 <bsd_getsockopt+0xf4>
+   }
+
+   e = t_getsockopt(s, level, name, opt, loptlen);
+ 80267c0:	e0bffd17 	ldw	r2,-12(fp)
+ 80267c4:	d8800015 	stw	r2,0(sp)
+ 80267c8:	e1fff817 	ldw	r7,-32(fp)
+ 80267cc:	e1bff917 	ldw	r6,-28(fp)
+ 80267d0:	e17ffa17 	ldw	r5,-24(fp)
+ 80267d4:	e13ffb17 	ldw	r4,-20(fp)
+ 80267d8:	802c60c0 	call	802c60c <t_getsockopt>
+ 80267dc:	e0bffc15 	stw	r2,-16(fp)
+
+   /* if it worked, copy the option length back for the caller's use */
+   if (e == 0)
+ 80267e0:	e0bffc17 	ldw	r2,-16(fp)
+ 80267e4:	1000031e 	bne	r2,zero,80267f4 <bsd_getsockopt+0xf0>
+   {
+      *optlen = loptlen;
+ 80267e8:	e0800217 	ldw	r2,8(fp)
+ 80267ec:	e0fffd17 	ldw	r3,-12(fp)
+ 80267f0:	10c00015 	stw	r3,0(r2)
+   }
+
+   return e;
+ 80267f4:	e0bffc17 	ldw	r2,-16(fp)
+   
+}
+ 80267f8:	e037883a 	mov	sp,fp
+ 80267fc:	dfc00117 	ldw	ra,4(sp)
+ 8026800:	df000017 	ldw	fp,0(sp)
+ 8026804:	dec00204 	addi	sp,sp,8
+ 8026808:	f800283a 	ret
+
+0802680c <bsd_ioctl>:
+ *          available via bsd_errno(s).
+ */
+int
+bsd_ioctl(BSD_SOCKET s, 
+          unsigned long request, ...)
+{
+ 802680c:	defff504 	addi	sp,sp,-44
+ 8026810:	dfc00815 	stw	ra,32(sp)
+ 8026814:	df000715 	stw	fp,28(sp)
+ 8026818:	df000704 	addi	fp,sp,28
+ 802681c:	e13ffb15 	stw	r4,-20(fp)
+ 8026820:	e17ffa15 	stw	r5,-24(fp)
+ 8026824:	e1800215 	stw	r6,8(fp)
+ 8026828:	e1c00315 	stw	r7,12(fp)
+   struct socket * so;
+   va_list argptr;
+   int iarg;
+
+   so = LONG2SO(s);
+ 802682c:	e0bffb17 	ldw	r2,-20(fp)
+ 8026830:	10bffc04 	addi	r2,r2,-16
+ 8026834:	100490ba 	slli	r2,r2,2
+ 8026838:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802683c:	008201b4 	movhi	r2,2054
+ 8026840:	10b87104 	addi	r2,r2,-7740
+ 8026844:	e0bfff15 	stw	r2,-4(fp)
+ 8026848:	00000606 	br	8026864 <bsd_ioctl+0x58>
+ 802684c:	e0ffff17 	ldw	r3,-4(fp)
+ 8026850:	e0bffe17 	ldw	r2,-8(fp)
+ 8026854:	18800626 	beq	r3,r2,8026870 <bsd_ioctl+0x64>
+ 8026858:	e0bfff17 	ldw	r2,-4(fp)
+ 802685c:	10800017 	ldw	r2,0(r2)
+ 8026860:	e0bfff15 	stw	r2,-4(fp)
+ 8026864:	e0bfff17 	ldw	r2,-4(fp)
+ 8026868:	103ff81e 	bne	r2,zero,802684c <bsd_ioctl+0x40>
+ 802686c:	00000106 	br	8026874 <bsd_ioctl+0x68>
+ 8026870:	0001883a 	nop
+ 8026874:	e0ffff17 	ldw	r3,-4(fp)
+ 8026878:	e0bffe17 	ldw	r2,-8(fp)
+ 802687c:	18800326 	beq	r3,r2,802688c <bsd_ioctl+0x80>
+ 8026880:	8028cd40 	call	8028cd4 <dtrap>
+ 8026884:	00bfffc4 	movi	r2,-1
+ 8026888:	00001706 	br	80268e8 <bsd_ioctl+0xdc>
+
+   va_start(argptr, request);
+ 802688c:	e0800204 	addi	r2,fp,8
+ 8026890:	e0bffd15 	stw	r2,-12(fp)
+
+   switch (request)
+ 8026894:	e0bffa17 	ldw	r2,-24(fp)
+ 8026898:	10840598 	cmpnei	r2,r2,4118
+ 802689c:	10000e1e 	bne	r2,zero,80268d8 <bsd_ioctl+0xcc>
+   {
+   case FIONBIO:
+      iarg = va_arg(argptr, int);
+ 80268a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80268a4:	10c00104 	addi	r3,r2,4
+ 80268a8:	e0fffd15 	stw	r3,-12(fp)
+ 80268ac:	10800017 	ldw	r2,0(r2)
+ 80268b0:	e0bffc15 	stw	r2,-16(fp)
+      va_end(argptr);
+      return t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, &iarg, sizeof(iarg));
+ 80268b4:	e0fffc04 	addi	r3,fp,-16
+ 80268b8:	00800104 	movi	r2,4
+ 80268bc:	d8800015 	stw	r2,0(sp)
+ 80268c0:	180f883a 	mov	r7,r3
+ 80268c4:	01840584 	movi	r6,4118
+ 80268c8:	017fffc4 	movi	r5,-1
+ 80268cc:	e13ffb17 	ldw	r4,-20(fp)
+ 80268d0:	802c44c0 	call	802c44c <t_setsockopt>
+ 80268d4:	00000406 	br	80268e8 <bsd_ioctl+0xdc>
+   default:
+      so->so_error = EINVAL;
+ 80268d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80268dc:	00c00584 	movi	r3,22
+ 80268e0:	10c00615 	stw	r3,24(r2)
+      return -1;
+ 80268e4:	00bfffc4 	movi	r2,-1
+   }
+}
+ 80268e8:	e037883a 	mov	sp,fp
+ 80268ec:	dfc00117 	ldw	ra,4(sp)
+ 80268f0:	df000017 	ldw	fp,0(sp)
+ 80268f4:	dec00404 	addi	sp,sp,16
+ 80268f8:	f800283a 	ret
+
+080268fc <bsd_inet_ntoa>:
+ * RETURNS: pointer to null-terminated string containing dotted-decimal
+ *          printable representation of in
+ */
+char *
+bsd_inet_ntoa(struct in_addr in)
+{
+ 80268fc:	defffd04 	addi	sp,sp,-12
+ 8026900:	dfc00215 	stw	ra,8(sp)
+ 8026904:	df000115 	stw	fp,4(sp)
+ 8026908:	df000104 	addi	fp,sp,4
+ 802690c:	e13fff15 	stw	r4,-4(fp)
+   return print_ipad(in.s_addr);
+ 8026910:	e0bfff17 	ldw	r2,-4(fp)
+ 8026914:	1009883a 	mov	r4,r2
+ 8026918:	8026fbc0 	call	8026fbc <print_ipad>
+}
+ 802691c:	e037883a 	mov	sp,fp
+ 8026920:	dfc00117 	ldw	ra,4(sp)
+ 8026924:	df000017 	ldw	fp,0(sp)
+ 8026928:	dec00204 	addi	sp,sp,8
+ 802692c:	f800283a 	ret
+
+08026930 <bsd_recvfrom>:
+bsd_recvfrom(BSD_SOCKET s,
+             void * buf,
+             BSD_SIZE_T len,
+             int flags,
+             struct sockaddr * from, int * fromlen)
+{
+ 8026930:	defff004 	addi	sp,sp,-64
+ 8026934:	dfc00f15 	stw	ra,60(sp)
+ 8026938:	df000e15 	stw	fp,56(sp)
+ 802693c:	df000e04 	addi	fp,sp,56
+ 8026940:	e13ff715 	stw	r4,-36(fp)
+ 8026944:	e17ff615 	stw	r5,-40(fp)
+ 8026948:	e1bff515 	stw	r6,-44(fp)
+ 802694c:	e1fff415 	stw	r7,-48(fp)
+   struct socket * so;
+   struct sockaddr lfrom;
+   int lfromlen = 0;
+ 8026950:	e03ff815 	stw	zero,-32(fp)
+   int lret;
+
+   so = LONG2SO(s);
+ 8026954:	e0bff717 	ldw	r2,-36(fp)
+ 8026958:	10bffc04 	addi	r2,r2,-16
+ 802695c:	100490ba 	slli	r2,r2,2
+ 8026960:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026964:	008201b4 	movhi	r2,2054
+ 8026968:	10b87104 	addi	r2,r2,-7740
+ 802696c:	e0bfff15 	stw	r2,-4(fp)
+ 8026970:	00000606 	br	802698c <bsd_recvfrom+0x5c>
+ 8026974:	e0ffff17 	ldw	r3,-4(fp)
+ 8026978:	e0bffe17 	ldw	r2,-8(fp)
+ 802697c:	18800626 	beq	r3,r2,8026998 <bsd_recvfrom+0x68>
+ 8026980:	e0bfff17 	ldw	r2,-4(fp)
+ 8026984:	10800017 	ldw	r2,0(r2)
+ 8026988:	e0bfff15 	stw	r2,-4(fp)
+ 802698c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026990:	103ff81e 	bne	r2,zero,8026974 <bsd_recvfrom+0x44>
+ 8026994:	00000106 	br	802699c <bsd_recvfrom+0x6c>
+ 8026998:	0001883a 	nop
+ 802699c:	e0ffff17 	ldw	r3,-4(fp)
+ 80269a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80269a4:	18800326 	beq	r3,r2,80269b4 <bsd_recvfrom+0x84>
+ 80269a8:	8028cd40 	call	8028cd4 <dtrap>
+ 80269ac:	00bfffc4 	movi	r2,-1
+ 80269b0:	00002b06 	br	8026a60 <bsd_recvfrom+0x130>
+
+   /* if we were given a buffer for the peer's address, also get the
+    * buffer's length 
+    */
+   if (from != NULL)
+ 80269b4:	e0800217 	ldw	r2,8(fp)
+ 80269b8:	10000a26 	beq	r2,zero,80269e4 <bsd_recvfrom+0xb4>
+   {
+      if (fromlen == NULL)
+ 80269bc:	e0800317 	ldw	r2,12(fp)
+ 80269c0:	1000051e 	bne	r2,zero,80269d8 <bsd_recvfrom+0xa8>
+      {
+         so->so_error = EFAULT;
+ 80269c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80269c8:	00c00384 	movi	r3,14
+ 80269cc:	10c00615 	stw	r3,24(r2)
+         return -1;
+ 80269d0:	00bfffc4 	movi	r2,-1
+ 80269d4:	00002206 	br	8026a60 <bsd_recvfrom+0x130>
+      }
+      lfromlen = *fromlen;
+ 80269d8:	e0800317 	ldw	r2,12(fp)
+ 80269dc:	10800017 	ldw	r2,0(r2)
+ 80269e0:	e0bff815 	stw	r2,-32(fp)
+   }
+
+   lret = t_recvfrom(s, (char *)buf, len, flags, &lfrom, &lfromlen );
+ 80269e4:	e0bff804 	addi	r2,fp,-32
+ 80269e8:	d8800115 	stw	r2,4(sp)
+ 80269ec:	e0bff904 	addi	r2,fp,-28
+ 80269f0:	d8800015 	stw	r2,0(sp)
+ 80269f4:	e1fff417 	ldw	r7,-48(fp)
+ 80269f8:	e1bff517 	ldw	r6,-44(fp)
+ 80269fc:	e17ff617 	ldw	r5,-40(fp)
+ 8026a00:	e13ff717 	ldw	r4,-36(fp)
+ 8026a04:	802c8700 	call	802c870 <t_recvfrom>
+ 8026a08:	e0bffd15 	stw	r2,-12(fp)
+    * sockaddr_in), which is all that t_recvfrom() can return as a peer
+    * name.
+    * For IPV6 addresses or dual IPV4/IPV6 stack, the max size copied
+    * is sizeof(struct sockaddr_in6)
+    */
+   if ((lret != -1) && (from != NULL))
+ 8026a0c:	e0bffd17 	ldw	r2,-12(fp)
+ 8026a10:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8026a14:	1000111e 	bne	r2,zero,8026a5c <bsd_recvfrom+0x12c>
+ 8026a18:	e0800217 	ldw	r2,8(fp)
+ 8026a1c:	10000f26 	beq	r2,zero,8026a5c <bsd_recvfrom+0x12c>
+   {
+#ifndef IP_V6
+      if (lfromlen > sizeof(struct sockaddr_in))
+ 8026a20:	e0bff817 	ldw	r2,-32(fp)
+ 8026a24:	10800470 	cmpltui	r2,r2,17
+ 8026a28:	1000021e 	bne	r2,zero,8026a34 <bsd_recvfrom+0x104>
+         lfromlen = sizeof(struct sockaddr_in);
+ 8026a2c:	00800404 	movi	r2,16
+ 8026a30:	e0bff815 	stw	r2,-32(fp)
+#else
+      if (lfromlen > sizeof(struct sockaddr_in6))
+         lfromlen = sizeof(struct sockaddr_in6);
+
+#endif
+      MEMCPY(from, &lfrom, lfromlen);
+ 8026a34:	e0bff817 	ldw	r2,-32(fp)
+ 8026a38:	1007883a 	mov	r3,r2
+ 8026a3c:	e0bff904 	addi	r2,fp,-28
+ 8026a40:	180d883a 	mov	r6,r3
+ 8026a44:	100b883a 	mov	r5,r2
+ 8026a48:	e1000217 	ldw	r4,8(fp)
+ 8026a4c:	80086b80 	call	80086b8 <memcpy>
+      *fromlen = lfromlen;
+ 8026a50:	e0fff817 	ldw	r3,-32(fp)
+ 8026a54:	e0800317 	ldw	r2,12(fp)
+ 8026a58:	10c00015 	stw	r3,0(r2)
+   }
+
+   return lret;
+ 8026a5c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8026a60:	e037883a 	mov	sp,fp
+ 8026a64:	dfc00117 	ldw	ra,4(sp)
+ 8026a68:	df000017 	ldw	fp,0(sp)
+ 8026a6c:	dec00204 	addi	sp,sp,8
+ 8026a70:	f800283a 	ret
+
+08026a74 <bsd_select>:
+bsd_select(int nfds,
+           fd_set * readfds,
+           fd_set * writefds,
+           fd_set * exceptfds,
+           BSD_TIMEVAL_T * timeout)
+{
+ 8026a74:	defff804 	addi	sp,sp,-32
+ 8026a78:	dfc00715 	stw	ra,28(sp)
+ 8026a7c:	df000615 	stw	fp,24(sp)
+ 8026a80:	df000604 	addi	fp,sp,24
+ 8026a84:	e13ffd15 	stw	r4,-12(fp)
+ 8026a88:	e17ffc15 	stw	r5,-16(fp)
+ 8026a8c:	e1bffb15 	stw	r6,-20(fp)
+ 8026a90:	e1fffa15 	stw	r7,-24(fp)
+   long ltv;    /* timeout expressed in ticks */
+   long tps;    /* local copy of TPS */
+
+   USE_ARG(nfds);
+
+   if (timeout != NULL)
+ 8026a94:	e0800217 	ldw	r2,8(fp)
+ 8026a98:	10004c26 	beq	r2,zero,8026bcc <bsd_select+0x158>
+       * million (i.e. any number of microseconds up to one second).
+       * So we scale tv_usec from microseconds to something reasonable
+       * based on TPS, multiply it by TPS, then scale it the rest of
+       * the way to ticks-per-second.
+       */
+      tps = TPS;
+ 8026a9c:	00801904 	movi	r2,100
+ 8026aa0:	e0bffe15 	stw	r2,-8(fp)
+      if (tps >= 1000)
+ 8026aa4:	e0bffe17 	ldw	r2,-8(fp)
+ 8026aa8:	1080fa10 	cmplti	r2,r2,1000
+ 8026aac:	10000e1e 	bne	r2,zero,8026ae8 <bsd_select+0x74>
+      {
+         ltv = (((timeout->tv_usec + 50) / 100) * tps) / 10000;
+ 8026ab0:	e0800217 	ldw	r2,8(fp)
+ 8026ab4:	10800217 	ldw	r2,8(r2)
+ 8026ab8:	10800c84 	addi	r2,r2,50
+ 8026abc:	01401904 	movi	r5,100
+ 8026ac0:	1009883a 	mov	r4,r2
+ 8026ac4:	800cf000 	call	800cf00 <__divsi3>
+ 8026ac8:	1007883a 	mov	r3,r2
+ 8026acc:	e0bffe17 	ldw	r2,-8(fp)
+ 8026ad0:	1885383a 	mul	r2,r3,r2
+ 8026ad4:	0149c404 	movi	r5,10000
+ 8026ad8:	1009883a 	mov	r4,r2
+ 8026adc:	800cf000 	call	800cf00 <__divsi3>
+ 8026ae0:	e0bfff15 	stw	r2,-4(fp)
+ 8026ae4:	00003106 	br	8026bac <bsd_select+0x138>
+      }
+      else if (tps >= 100)
+ 8026ae8:	e0bffe17 	ldw	r2,-8(fp)
+ 8026aec:	10801910 	cmplti	r2,r2,100
+ 8026af0:	10000e1e 	bne	r2,zero,8026b2c <bsd_select+0xb8>
+      {
+         ltv = (((timeout->tv_usec + 500) / 1000) * tps) / 1000;
+ 8026af4:	e0800217 	ldw	r2,8(fp)
+ 8026af8:	10800217 	ldw	r2,8(r2)
+ 8026afc:	10807d04 	addi	r2,r2,500
+ 8026b00:	0140fa04 	movi	r5,1000
+ 8026b04:	1009883a 	mov	r4,r2
+ 8026b08:	800cf000 	call	800cf00 <__divsi3>
+ 8026b0c:	1007883a 	mov	r3,r2
+ 8026b10:	e0bffe17 	ldw	r2,-8(fp)
+ 8026b14:	1885383a 	mul	r2,r3,r2
+ 8026b18:	0140fa04 	movi	r5,1000
+ 8026b1c:	1009883a 	mov	r4,r2
+ 8026b20:	800cf000 	call	800cf00 <__divsi3>
+ 8026b24:	e0bfff15 	stw	r2,-4(fp)
+ 8026b28:	00002006 	br	8026bac <bsd_select+0x138>
+      }
+      else if (tps >= 10)
+ 8026b2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8026b30:	10800290 	cmplti	r2,r2,10
+ 8026b34:	10000e1e 	bne	r2,zero,8026b70 <bsd_select+0xfc>
+      {
+         ltv = (((timeout->tv_usec + 5000) / 10000) * tps) / 100;
+ 8026b38:	e0800217 	ldw	r2,8(fp)
+ 8026b3c:	10800217 	ldw	r2,8(r2)
+ 8026b40:	1084e204 	addi	r2,r2,5000
+ 8026b44:	0149c404 	movi	r5,10000
+ 8026b48:	1009883a 	mov	r4,r2
+ 8026b4c:	800cf000 	call	800cf00 <__divsi3>
+ 8026b50:	1007883a 	mov	r3,r2
+ 8026b54:	e0bffe17 	ldw	r2,-8(fp)
+ 8026b58:	1885383a 	mul	r2,r3,r2
+ 8026b5c:	01401904 	movi	r5,100
+ 8026b60:	1009883a 	mov	r4,r2
+ 8026b64:	800cf000 	call	800cf00 <__divsi3>
+ 8026b68:	e0bfff15 	stw	r2,-4(fp)
+ 8026b6c:	00000f06 	br	8026bac <bsd_select+0x138>
+      }
+      else
+      {
+         ltv = (((timeout->tv_usec + 50000) / 100000) * tps) / 10;
+ 8026b70:	e0800217 	ldw	r2,8(fp)
+ 8026b74:	10c00217 	ldw	r3,8(r2)
+ 8026b78:	00b0d414 	movui	r2,50000
+ 8026b7c:	1885883a 	add	r2,r3,r2
+ 8026b80:	014000b4 	movhi	r5,2
+ 8026b84:	2961a804 	addi	r5,r5,-31072
+ 8026b88:	1009883a 	mov	r4,r2
+ 8026b8c:	800cf000 	call	800cf00 <__divsi3>
+ 8026b90:	1007883a 	mov	r3,r2
+ 8026b94:	e0bffe17 	ldw	r2,-8(fp)
+ 8026b98:	1885383a 	mul	r2,r3,r2
+ 8026b9c:	01400284 	movi	r5,10
+ 8026ba0:	1009883a 	mov	r4,r2
+ 8026ba4:	800cf000 	call	800cf00 <__divsi3>
+ 8026ba8:	e0bfff15 	stw	r2,-4(fp)
+      }
+      ltv += (timeout->tv_sec * TPS);
+ 8026bac:	e1000217 	ldw	r4,8(fp)
+ 8026bb0:	20800017 	ldw	r2,0(r4)
+ 8026bb4:	20c00117 	ldw	r3,4(r4)
+ 8026bb8:	10c01924 	muli	r3,r2,100
+ 8026bbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8026bc0:	1885883a 	add	r2,r3,r2
+ 8026bc4:	e0bfff15 	stw	r2,-4(fp)
+ 8026bc8:	00000206 	br	8026bd4 <bsd_select+0x160>
+   }
+   else {
+      /*
+       * NULL timeout: wait indefinitely in t_select()
+       */
+      ltv = -1;
+ 8026bcc:	00bfffc4 	movi	r2,-1
+ 8026bd0:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   return (t_select(readfds, writefds, exceptfds, ltv));
+ 8026bd4:	e1ffff17 	ldw	r7,-4(fp)
+ 8026bd8:	e1bffa17 	ldw	r6,-24(fp)
+ 8026bdc:	e17ffb17 	ldw	r5,-20(fp)
+ 8026be0:	e13ffc17 	ldw	r4,-16(fp)
+ 8026be4:	80303f80 	call	80303f8 <t_select>
+}
+ 8026be8:	e037883a 	mov	sp,fp
+ 8026bec:	dfc00117 	ldw	ra,4(sp)
+ 8026bf0:	df000017 	ldw	fp,0(sp)
+ 8026bf4:	dec00204 	addi	sp,sp,8
+ 8026bf8:	f800283a 	ret
+
+08026bfc <bsd_setsockopt>:
+int 
+bsd_setsockopt(BSD_SOCKET s,
+               int level,
+               int name,
+               void * opt, int optlen)
+{
+ 8026bfc:	defff704 	addi	sp,sp,-36
+ 8026c00:	dfc00815 	stw	ra,32(sp)
+ 8026c04:	df000715 	stw	fp,28(sp)
+ 8026c08:	df000704 	addi	fp,sp,28
+ 8026c0c:	e13ffd15 	stw	r4,-12(fp)
+ 8026c10:	e17ffc15 	stw	r5,-16(fp)
+ 8026c14:	e1bffb15 	stw	r6,-20(fp)
+ 8026c18:	e1fffa15 	stw	r7,-24(fp)
+   struct socket * so;
+
+   so = LONG2SO(s);
+ 8026c1c:	e0bffd17 	ldw	r2,-12(fp)
+ 8026c20:	10bffc04 	addi	r2,r2,-16
+ 8026c24:	100490ba 	slli	r2,r2,2
+ 8026c28:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 8026c2c:	008201b4 	movhi	r2,2054
+ 8026c30:	10b87104 	addi	r2,r2,-7740
+ 8026c34:	e0bfff15 	stw	r2,-4(fp)
+ 8026c38:	00000606 	br	8026c54 <bsd_setsockopt+0x58>
+ 8026c3c:	e0ffff17 	ldw	r3,-4(fp)
+ 8026c40:	e0bffe17 	ldw	r2,-8(fp)
+ 8026c44:	18800626 	beq	r3,r2,8026c60 <bsd_setsockopt+0x64>
+ 8026c48:	e0bfff17 	ldw	r2,-4(fp)
+ 8026c4c:	10800017 	ldw	r2,0(r2)
+ 8026c50:	e0bfff15 	stw	r2,-4(fp)
+ 8026c54:	e0bfff17 	ldw	r2,-4(fp)
+ 8026c58:	103ff81e 	bne	r2,zero,8026c3c <bsd_setsockopt+0x40>
+ 8026c5c:	00000106 	br	8026c64 <bsd_setsockopt+0x68>
+ 8026c60:	0001883a 	nop
+ 8026c64:	e0ffff17 	ldw	r3,-4(fp)
+ 8026c68:	e0bffe17 	ldw	r2,-8(fp)
+ 8026c6c:	18800326 	beq	r3,r2,8026c7c <bsd_setsockopt+0x80>
+ 8026c70:	8028cd40 	call	8028cd4 <dtrap>
+ 8026c74:	00bfffc4 	movi	r2,-1
+ 8026c78:	00001206 	br	8026cc4 <bsd_setsockopt+0xc8>
+
+   /* make sure supplied option value is big enough for the 
+    * named option, else fail w/error EFAULT
+    */
+   if (optlen < bsd_i_sockoptlen(level, name))
+ 8026c7c:	e17ffb17 	ldw	r5,-20(fp)
+ 8026c80:	e13ffc17 	ldw	r4,-16(fp)
+ 8026c84:	80265740 	call	8026574 <bsd_i_sockoptlen>
+ 8026c88:	1007883a 	mov	r3,r2
+ 8026c8c:	e0800217 	ldw	r2,8(fp)
+ 8026c90:	10c0050e 	bge	r2,r3,8026ca8 <bsd_setsockopt+0xac>
+   {
+      so->so_error = EFAULT;
+ 8026c94:	e0bffe17 	ldw	r2,-8(fp)
+ 8026c98:	00c00384 	movi	r3,14
+ 8026c9c:	10c00615 	stw	r3,24(r2)
+      return -1;
+ 8026ca0:	00bfffc4 	movi	r2,-1
+ 8026ca4:	00000706 	br	8026cc4 <bsd_setsockopt+0xc8>
+   }
+
+   return t_setsockopt(s, level, name, opt, optlen);
+ 8026ca8:	e0800217 	ldw	r2,8(fp)
+ 8026cac:	d8800015 	stw	r2,0(sp)
+ 8026cb0:	e1fffa17 	ldw	r7,-24(fp)
+ 8026cb4:	e1bffb17 	ldw	r6,-20(fp)
+ 8026cb8:	e17ffc17 	ldw	r5,-16(fp)
+ 8026cbc:	e13ffd17 	ldw	r4,-12(fp)
+ 8026cc0:	802c44c0 	call	802c44c <t_setsockopt>
+}
+ 8026cc4:	e037883a 	mov	sp,fp
+ 8026cc8:	dfc00117 	ldw	ra,4(sp)
+ 8026ccc:	df000017 	ldw	fp,0(sp)
+ 8026cd0:	dec00204 	addi	sp,sp,8
+ 8026cd4:	f800283a 	ret
+
+08026cd8 <ccksum>:
+ * be done in 16-bit chunks.
+ */
+
+unsigned short
+ccksum (void *ptr, unsigned words)
+{
+ 8026cd8:	defffa04 	addi	sp,sp,-24
+ 8026cdc:	df000515 	stw	fp,20(sp)
+ 8026ce0:	df000504 	addi	fp,sp,20
+ 8026ce4:	e13ffc15 	stw	r4,-16(fp)
+ 8026ce8:	e17ffb15 	stw	r5,-20(fp)
+   unsigned short *addr = (unsigned short *)ptr;
+ 8026cec:	e0bffc17 	ldw	r2,-16(fp)
+ 8026cf0:	e0bfff15 	stw	r2,-4(fp)
+   unsigned long sum = 0;
+ 8026cf4:	e03ffe15 	stw	zero,-8(fp)
+   int count = (int)words;
+ 8026cf8:	e0bffb17 	ldw	r2,-20(fp)
+ 8026cfc:	e0bffd15 	stw	r2,-12(fp)
+
+   while (--count >= 0)
+ 8026d00:	00000806 	br	8026d24 <ccksum+0x4c>
+   {
+      /*  This is the inner loop */
+      sum += *addr++;
+ 8026d04:	e0bfff17 	ldw	r2,-4(fp)
+ 8026d08:	10c00084 	addi	r3,r2,2
+ 8026d0c:	e0ffff15 	stw	r3,-4(fp)
+ 8026d10:	1080000b 	ldhu	r2,0(r2)
+ 8026d14:	10bfffcc 	andi	r2,r2,65535
+ 8026d18:	e0fffe17 	ldw	r3,-8(fp)
+ 8026d1c:	1885883a 	add	r2,r3,r2
+ 8026d20:	e0bffe15 	stw	r2,-8(fp)
+   while (--count >= 0)
+ 8026d24:	e0bffd17 	ldw	r2,-12(fp)
+ 8026d28:	10bfffc4 	addi	r2,r2,-1
+ 8026d2c:	e0bffd15 	stw	r2,-12(fp)
+ 8026d30:	e0bffd17 	ldw	r2,-12(fp)
+ 8026d34:	103ff30e 	bge	r2,zero,8026d04 <ccksum+0x2c>
+   }
+
+   /*  Fold 32-bit sum to 16 bits */
+   sum = (sum & 0xffff) + (sum >> 16);
+ 8026d38:	e0bffe17 	ldw	r2,-8(fp)
+ 8026d3c:	10ffffcc 	andi	r3,r2,65535
+ 8026d40:	e0bffe17 	ldw	r2,-8(fp)
+ 8026d44:	1004d43a 	srli	r2,r2,16
+ 8026d48:	1885883a 	add	r2,r3,r2
+ 8026d4c:	e0bffe15 	stw	r2,-8(fp)
+   sum = (sum & 0xffff) + (sum >> 16);
+ 8026d50:	e0bffe17 	ldw	r2,-8(fp)
+ 8026d54:	10ffffcc 	andi	r3,r2,65535
+ 8026d58:	e0bffe17 	ldw	r2,-8(fp)
+ 8026d5c:	1004d43a 	srli	r2,r2,16
+ 8026d60:	1885883a 	add	r2,r3,r2
+ 8026d64:	e0bffe15 	stw	r2,-8(fp)
+
+   /* checksum = ~sum; *//* removed for MIT IP stack */
+   return ((unsigned short)sum);
+ 8026d68:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8026d6c:	e037883a 	mov	sp,fp
+ 8026d70:	df000017 	ldw	fp,0(sp)
+ 8026d74:	dec00104 	addi	sp,sp,4
+ 8026d78:	f800283a 	ret
+
+08026d7c <cksum>:
+ *    3 = user-supplied alternate implementation
+ */
+
+unsigned short
+cksum (void *ptr, unsigned count)
+{
+ 8026d7c:	defffc04 	addi	sp,sp,-16
+ 8026d80:	dfc00315 	stw	ra,12(sp)
+ 8026d84:	df000215 	stw	fp,8(sp)
+ 8026d88:	df000204 	addi	fp,sp,8
+ 8026d8c:	e13fff15 	stw	r4,-4(fp)
+ 8026d90:	e17ffe15 	stw	r5,-8(fp)
+   switch (cksum_select)
+ 8026d94:	d0a01317 	ldw	r2,-32692(gp)
+ 8026d98:	108000a0 	cmpeqi	r2,r2,2
+ 8026d9c:	1000041e 	bne	r2,zero,8026db0 <cksum+0x34>
+   {
+      case 1:
+      default:
+         return (ccksum(ptr, count));
+ 8026da0:	e17ffe17 	ldw	r5,-8(fp)
+ 8026da4:	e13fff17 	ldw	r4,-4(fp)
+ 8026da8:	8026cd80 	call	8026cd8 <ccksum>
+ 8026dac:	00000306 	br	8026dbc <cksum+0x40>
+ #ifndef C_CHECKSUM
+      case 2:
+         return (asm_cksum(ptr, count));
+ 8026db0:	e17ffe17 	ldw	r5,-8(fp)
+ 8026db4:	e13fff17 	ldw	r4,-4(fp)
+ 8026db8:	8028b400 	call	8028b40 <asm_cksum>
+#else
+#endif
+         return (alt_cksum(ptr, count));
+#endif
+   }
+}
+ 8026dbc:	e037883a 	mov	sp,fp
+ 8026dc0:	dfc00117 	ldw	ra,4(sp)
+ 8026dc4:	df000017 	ldw	fp,0(sp)
+ 8026dc8:	dec00204 	addi	sp,sp,8
+ 8026dcc:	f800283a 	ret
+
+08026dd0 <do_trap>:
+ * RETURNS: 0
+ */
+
+int
+do_trap(void)
+{
+ 8026dd0:	defffe04 	addi	sp,sp,-8
+ 8026dd4:	dfc00115 	stw	ra,4(sp)
+ 8026dd8:	df000015 	stw	fp,0(sp)
+ 8026ddc:	d839883a 	mov	fp,sp
+   dtrap();
+ 8026de0:	8028cd40 	call	8028cd4 <dtrap>
+   return 0;
+ 8026de4:	0005883a 	mov	r2,zero
+}
+ 8026de8:	e037883a 	mov	sp,fp
+ 8026dec:	dfc00117 	ldw	ra,4(sp)
+ 8026df0:	df000017 	ldw	fp,0(sp)
+ 8026df4:	dec00204 	addi	sp,sp,8
+ 8026df8:	f800283a 	ret
+
+08026dfc <nextarg>:
+ * RETURNS:  pointer to next arg in string 
+ */
+
+char *   
+nextarg(char * argp)
+{
+ 8026dfc:	defffe04 	addi	sp,sp,-8
+ 8026e00:	df000115 	stw	fp,4(sp)
+ 8026e04:	df000104 	addi	fp,sp,4
+ 8026e08:	e13fff15 	stw	r4,-4(fp)
+   while (*argp > ' ')argp++; /* scan past current arg */
+ 8026e0c:	00000306 	br	8026e1c <nextarg+0x20>
+ 8026e10:	e0bfff17 	ldw	r2,-4(fp)
+ 8026e14:	10800044 	addi	r2,r2,1
+ 8026e18:	e0bfff15 	stw	r2,-4(fp)
+ 8026e1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026e20:	10800003 	ldbu	r2,0(r2)
+ 8026e24:	10803fcc 	andi	r2,r2,255
+ 8026e28:	1080201c 	xori	r2,r2,128
+ 8026e2c:	10bfe004 	addi	r2,r2,-128
+ 8026e30:	10800848 	cmpgei	r2,r2,33
+ 8026e34:	103ff61e 	bne	r2,zero,8026e10 <nextarg+0x14>
+      while (*argp == ' ')argp++;   /* scan past spaces */
+ 8026e38:	00000306 	br	8026e48 <nextarg+0x4c>
+ 8026e3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8026e40:	10800044 	addi	r2,r2,1
+ 8026e44:	e0bfff15 	stw	r2,-4(fp)
+ 8026e48:	e0bfff17 	ldw	r2,-4(fp)
+ 8026e4c:	10800003 	ldbu	r2,0(r2)
+ 8026e50:	10803fcc 	andi	r2,r2,255
+ 8026e54:	1080201c 	xori	r2,r2,128
+ 8026e58:	10bfe004 	addi	r2,r2,-128
+ 8026e5c:	10800820 	cmpeqi	r2,r2,32
+ 8026e60:	103ff61e 	bne	r2,zero,8026e3c <nextarg+0x40>
+      return (argp);
+ 8026e64:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8026e68:	e037883a 	mov	sp,fp
+ 8026e6c:	df000017 	ldw	fp,0(sp)
+ 8026e70:	dec00104 	addi	sp,sp,4
+ 8026e74:	f800283a 	ret
+
+08026e78 <hexdump>:
+
+#define  HEX_BYTES_PER_LINE   16
+
+void
+hexdump(void * pio, void * buffer, unsigned len)
+{
+ 8026e78:	defff804 	addi	sp,sp,-32
+ 8026e7c:	dfc00715 	stw	ra,28(sp)
+ 8026e80:	df000615 	stw	fp,24(sp)
+ 8026e84:	df000604 	addi	fp,sp,24
+ 8026e88:	e13ffc15 	stw	r4,-16(fp)
+ 8026e8c:	e17ffb15 	stw	r5,-20(fp)
+ 8026e90:	e1bffa15 	stw	r6,-24(fp)
+   u_char * data  =  (u_char *)buffer;
+ 8026e94:	e0bffb17 	ldw	r2,-20(fp)
+ 8026e98:	e0bfff15 	stw	r2,-4(fp)
+   unsigned int count;
+   char  c;
+
+   while (len)
+ 8026e9c:	00003f06 	br	8026f9c <hexdump+0x124>
+   {
+      /* display data in hex */
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+ 8026ea0:	e03ffe15 	stw	zero,-8(fp)
+ 8026ea4:	00000d06 	br	8026edc <hexdump+0x64>
+         ns_printf(pio, "%02x ", *(data + count));
+ 8026ea8:	e0ffff17 	ldw	r3,-4(fp)
+ 8026eac:	e0bffe17 	ldw	r2,-8(fp)
+ 8026eb0:	1885883a 	add	r2,r3,r2
+ 8026eb4:	10800003 	ldbu	r2,0(r2)
+ 8026eb8:	10803fcc 	andi	r2,r2,255
+ 8026ebc:	100d883a 	mov	r6,r2
+ 8026ec0:	01420174 	movhi	r5,2053
+ 8026ec4:	29688104 	addi	r5,r5,-24060
+ 8026ec8:	e13ffc17 	ldw	r4,-16(fp)
+ 8026ecc:	80273900 	call	8027390 <ns_printf>
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+ 8026ed0:	e0bffe17 	ldw	r2,-8(fp)
+ 8026ed4:	10800044 	addi	r2,r2,1
+ 8026ed8:	e0bffe15 	stw	r2,-8(fp)
+ 8026edc:	e0bffe17 	ldw	r2,-8(fp)
+ 8026ee0:	10800428 	cmpgeui	r2,r2,16
+ 8026ee4:	1000031e 	bne	r2,zero,8026ef4 <hexdump+0x7c>
+ 8026ee8:	e0fffe17 	ldw	r3,-8(fp)
+ 8026eec:	e0bffa17 	ldw	r2,-24(fp)
+ 8026ef0:	18bfed36 	bltu	r3,r2,8026ea8 <hexdump+0x30>
+      /* display data in ascii */
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+ 8026ef4:	e03ffe15 	stw	zero,-8(fp)
+ 8026ef8:	00001606 	br	8026f54 <hexdump+0xdc>
+      {
+         c = *(data + count);
+ 8026efc:	e0ffff17 	ldw	r3,-4(fp)
+ 8026f00:	e0bffe17 	ldw	r2,-8(fp)
+ 8026f04:	1885883a 	add	r2,r3,r2
+ 8026f08:	10800003 	ldbu	r2,0(r2)
+ 8026f0c:	e0bffdc5 	stb	r2,-9(fp)
+         ns_printf(pio, "%c", ((c >= 0x20) && (c < 0x7f)) ? c : '.');
+ 8026f10:	e0bffdc7 	ldb	r2,-9(fp)
+ 8026f14:	10800810 	cmplti	r2,r2,32
+ 8026f18:	1000051e 	bne	r2,zero,8026f30 <hexdump+0xb8>
+ 8026f1c:	e0bffdc7 	ldb	r2,-9(fp)
+ 8026f20:	10801fe0 	cmpeqi	r2,r2,127
+ 8026f24:	1000021e 	bne	r2,zero,8026f30 <hexdump+0xb8>
+ 8026f28:	e0bffdc7 	ldb	r2,-9(fp)
+ 8026f2c:	00000106 	br	8026f34 <hexdump+0xbc>
+ 8026f30:	00800b84 	movi	r2,46
+ 8026f34:	100d883a 	mov	r6,r2
+ 8026f38:	01420174 	movhi	r5,2053
+ 8026f3c:	29688304 	addi	r5,r5,-24052
+ 8026f40:	e13ffc17 	ldw	r4,-16(fp)
+ 8026f44:	80273900 	call	8027390 <ns_printf>
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+ 8026f48:	e0bffe17 	ldw	r2,-8(fp)
+ 8026f4c:	10800044 	addi	r2,r2,1
+ 8026f50:	e0bffe15 	stw	r2,-8(fp)
+ 8026f54:	e0bffe17 	ldw	r2,-8(fp)
+ 8026f58:	10800428 	cmpgeui	r2,r2,16
+ 8026f5c:	1000031e 	bne	r2,zero,8026f6c <hexdump+0xf4>
+ 8026f60:	e0fffe17 	ldw	r3,-8(fp)
+ 8026f64:	e0bffa17 	ldw	r2,-24(fp)
+ 8026f68:	18bfe436 	bltu	r3,r2,8026efc <hexdump+0x84>
+      }
+      ns_printf(pio,"\n");
+ 8026f6c:	01420174 	movhi	r5,2053
+ 8026f70:	29688404 	addi	r5,r5,-24048
+ 8026f74:	e13ffc17 	ldw	r4,-16(fp)
+ 8026f78:	80273900 	call	8027390 <ns_printf>
+      len -= count;
+ 8026f7c:	e0fffa17 	ldw	r3,-24(fp)
+ 8026f80:	e0bffe17 	ldw	r2,-8(fp)
+ 8026f84:	1885c83a 	sub	r2,r3,r2
+ 8026f88:	e0bffa15 	stw	r2,-24(fp)
+      data += count;
+ 8026f8c:	e0ffff17 	ldw	r3,-4(fp)
+ 8026f90:	e0bffe17 	ldw	r2,-8(fp)
+ 8026f94:	1885883a 	add	r2,r3,r2
+ 8026f98:	e0bfff15 	stw	r2,-4(fp)
+   while (len)
+ 8026f9c:	e0bffa17 	ldw	r2,-24(fp)
+ 8026fa0:	103fbf1e 	bne	r2,zero,8026ea0 <hexdump+0x28>
+   }
+}
+ 8026fa4:	0001883a 	nop
+ 8026fa8:	e037883a 	mov	sp,fp
+ 8026fac:	dfc00117 	ldw	ra,4(sp)
+ 8026fb0:	df000017 	ldw	fp,0(sp)
+ 8026fb4:	dec00204 	addi	sp,sp,8
+ 8026fb8:	f800283a 	ret
+
+08026fbc <print_ipad>:
+
+char     ipreturn[18];     /* buffer for return */
+
+char *   
+print_ipad(unsigned long ipaddr)
+{
+ 8026fbc:	defffa04 	addi	sp,sp,-24
+ 8026fc0:	dfc00515 	stw	ra,20(sp)
+ 8026fc4:	df000415 	stw	fp,16(sp)
+ 8026fc8:	df000404 	addi	fp,sp,16
+ 8026fcc:	e13ffe15 	stw	r4,-8(fp)
+   struct l2b  ip;
+
+   ip.ip.iplong = ipaddr;
+ 8026fd0:	e0bffe17 	ldw	r2,-8(fp)
+ 8026fd4:	e0bfff15 	stw	r2,-4(fp)
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+    ip.ip.ipchar[0],
+ 8026fd8:	e0bfff03 	ldbu	r2,-4(fp)
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+ 8026fdc:	11003fcc 	andi	r4,r2,255
+    ip.ip.ipchar[1],
+ 8026fe0:	e0bfff43 	ldbu	r2,-3(fp)
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+ 8026fe4:	11403fcc 	andi	r5,r2,255
+    ip.ip.ipchar[2],
+ 8026fe8:	e0bfff83 	ldbu	r2,-2(fp)
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+ 8026fec:	10803fcc 	andi	r2,r2,255
+    ip.ip.ipchar[3]);
+ 8026ff0:	e0ffffc3 	ldbu	r3,-1(fp)
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+ 8026ff4:	18c03fcc 	andi	r3,r3,255
+ 8026ff8:	d8c00115 	stw	r3,4(sp)
+ 8026ffc:	d8800015 	stw	r2,0(sp)
+ 8027000:	280f883a 	mov	r7,r5
+ 8027004:	200d883a 	mov	r6,r4
+ 8027008:	01420174 	movhi	r5,2053
+ 802700c:	29688504 	addi	r5,r5,-24044
+ 8027010:	010201b4 	movhi	r4,2054
+ 8027014:	21379184 	addi	r4,r4,-8634
+ 8027018:	8042d980 	call	8042d98 <sprintf>
+
+   return ipreturn;
+ 802701c:	008201b4 	movhi	r2,2054
+ 8027020:	10b79184 	addi	r2,r2,-8634
+}
+ 8027024:	e037883a 	mov	sp,fp
+ 8027028:	dfc00117 	ldw	ra,4(sp)
+ 802702c:	df000017 	ldw	fp,0(sp)
+ 8027030:	dec00204 	addi	sp,sp,8
+ 8027034:	f800283a 	ret
+
+08027038 <print_uptime>:
+
+static char tistring[24];     /* buffer for return */
+
+char *   
+print_uptime(unsigned long timetick)
+{
+ 8027038:	defff804 	addi	sp,sp,-32
+ 802703c:	dfc00715 	stw	ra,28(sp)
+ 8027040:	df000615 	stw	fp,24(sp)
+ 8027044:	df000604 	addi	fp,sp,24
+ 8027048:	e13ffc15 	stw	r4,-16(fp)
+   unsigned seconds, minutes, hours;
+
+   timetick = timetick/100;   /* turn timetick into seconds */
+ 802704c:	e0bffc17 	ldw	r2,-16(fp)
+ 8027050:	01401904 	movi	r5,100
+ 8027054:	1009883a 	mov	r4,r2
+ 8027058:	800cff80 	call	800cff8 <__udivsi3>
+ 802705c:	e0bffc15 	stw	r2,-16(fp)
+   seconds = (unsigned)(timetick%60);
+ 8027060:	e0bffc17 	ldw	r2,-16(fp)
+ 8027064:	01400f04 	movi	r5,60
+ 8027068:	1009883a 	mov	r4,r2
+ 802706c:	800d05c0 	call	800d05c <__umodsi3>
+ 8027070:	e0bfff15 	stw	r2,-4(fp)
+   timetick = timetick/60;    /* turn timetick into minutes */
+ 8027074:	e0bffc17 	ldw	r2,-16(fp)
+ 8027078:	01400f04 	movi	r5,60
+ 802707c:	1009883a 	mov	r4,r2
+ 8027080:	800cff80 	call	800cff8 <__udivsi3>
+ 8027084:	e0bffc15 	stw	r2,-16(fp)
+   minutes = (unsigned)(timetick%60);
+ 8027088:	e0bffc17 	ldw	r2,-16(fp)
+ 802708c:	01400f04 	movi	r5,60
+ 8027090:	1009883a 	mov	r4,r2
+ 8027094:	800d05c0 	call	800d05c <__umodsi3>
+ 8027098:	e0bffe15 	stw	r2,-8(fp)
+   timetick = timetick/60;    /* turn timetick into hours */
+ 802709c:	e0bffc17 	ldw	r2,-16(fp)
+ 80270a0:	01400f04 	movi	r5,60
+ 80270a4:	1009883a 	mov	r4,r2
+ 80270a8:	800cff80 	call	800cff8 <__udivsi3>
+ 80270ac:	e0bffc15 	stw	r2,-16(fp)
+   hours = (unsigned)(timetick%24);
+ 80270b0:	e0bffc17 	ldw	r2,-16(fp)
+ 80270b4:	01400604 	movi	r5,24
+ 80270b8:	1009883a 	mov	r4,r2
+ 80270bc:	800d05c0 	call	800d05c <__umodsi3>
+ 80270c0:	e0bffd15 	stw	r2,-12(fp)
+   timetick = timetick/24;    /* turn timetick into days */
+ 80270c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80270c8:	01400604 	movi	r5,24
+ 80270cc:	1009883a 	mov	r4,r2
+ 80270d0:	800cff80 	call	800cff8 <__udivsi3>
+ 80270d4:	e0bffc15 	stw	r2,-16(fp)
+
+   if (timetick)  /* Is there a whole number of days? */
+ 80270d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80270dc:	10000c26 	beq	r2,zero,8027110 <print_uptime+0xd8>
+      sprintf(tistring, "%ld days, %dh:%dm:%ds", 
+ 80270e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80270e4:	d8800115 	stw	r2,4(sp)
+ 80270e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80270ec:	d8800015 	stw	r2,0(sp)
+ 80270f0:	e1fffd17 	ldw	r7,-12(fp)
+ 80270f4:	e1bffc17 	ldw	r6,-16(fp)
+ 80270f8:	01420174 	movhi	r5,2053
+ 80270fc:	29688804 	addi	r5,r5,-24032
+ 8027100:	01020174 	movhi	r4,2053
+ 8027104:	21337d04 	addi	r4,r4,-12812
+ 8027108:	8042d980 	call	8042d98 <sprintf>
+ 802710c:	00001306 	br	802715c <print_uptime+0x124>
+    timetick, hours, minutes, seconds);
+   else if (hours)
+ 8027110:	e0bffd17 	ldw	r2,-12(fp)
+ 8027114:	10000a26 	beq	r2,zero,8027140 <print_uptime+0x108>
+      sprintf(tistring, "%d hours, %dm:%ds", hours, minutes, seconds);
+ 8027118:	e0bfff17 	ldw	r2,-4(fp)
+ 802711c:	d8800015 	stw	r2,0(sp)
+ 8027120:	e1fffe17 	ldw	r7,-8(fp)
+ 8027124:	e1bffd17 	ldw	r6,-12(fp)
+ 8027128:	01420174 	movhi	r5,2053
+ 802712c:	29688e04 	addi	r5,r5,-24008
+ 8027130:	01020174 	movhi	r4,2053
+ 8027134:	21337d04 	addi	r4,r4,-12812
+ 8027138:	8042d980 	call	8042d98 <sprintf>
+ 802713c:	00000706 	br	802715c <print_uptime+0x124>
+   else
+      sprintf(tistring, "%d minutes, %d sec.", minutes, seconds);
+ 8027140:	e1ffff17 	ldw	r7,-4(fp)
+ 8027144:	e1bffe17 	ldw	r6,-8(fp)
+ 8027148:	01420174 	movhi	r5,2053
+ 802714c:	29689304 	addi	r5,r5,-23988
+ 8027150:	01020174 	movhi	r4,2053
+ 8027154:	21337d04 	addi	r4,r4,-12812
+ 8027158:	8042d980 	call	8042d98 <sprintf>
+   return tistring;
+ 802715c:	00820174 	movhi	r2,2053
+ 8027160:	10b37d04 	addi	r2,r2,-12812
+}
+ 8027164:	e037883a 	mov	sp,fp
+ 8027168:	dfc00117 	ldw	ra,4(sp)
+ 802716c:	df000017 	ldw	fp,0(sp)
+ 8027170:	dec00204 	addi	sp,sp,8
+ 8027174:	f800283a 	ret
+
+08027178 <panic>:
+/* allow to be ifdeffed out on systems which already have a panic */
+#ifndef PANIC_ALREADY
+
+void
+panic(char * msg)
+{
+ 8027178:	defffd04 	addi	sp,sp,-12
+ 802717c:	dfc00215 	stw	ra,8(sp)
+ 8027180:	df000115 	stw	fp,4(sp)
+ 8027184:	df000104 	addi	fp,sp,4
+ 8027188:	e13fff15 	stw	r4,-4(fp)
+   dprintf("panic: %s\n", msg);
+ 802718c:	e17fff17 	ldw	r5,-4(fp)
+ 8027190:	01020174 	movhi	r4,2053
+ 8027194:	21289804 	addi	r4,r4,-23968
+ 8027198:	8002c780 	call	8002c78 <printf>
+   dtrap();                   /* try to hook debugger */
+ 802719c:	8028cd40 	call	8028cd4 <dtrap>
+   netexit(1);                /* try to clean up */
+ 80271a0:	01000044 	movi	r4,1
+ 80271a4:	803c5e80 	call	803c5e8 <netexit>
+}
+ 80271a8:	0001883a 	nop
+ 80271ac:	e037883a 	mov	sp,fp
+ 80271b0:	dfc00117 	ldw	ra,4(sp)
+ 80271b4:	df000017 	ldw	fp,0(sp)
+ 80271b8:	dec00204 	addi	sp,sp,8
+ 80271bc:	f800283a 	ret
+
+080271c0 <print_eth>:
+
+char     eth_prt_buf[18];  /* buffer for return */
+
+char *   
+print_eth(char * addr, char spacer)
+{
+ 80271c0:	defffb04 	addi	sp,sp,-20
+ 80271c4:	df000415 	stw	fp,16(sp)
+ 80271c8:	df000404 	addi	fp,sp,16
+ 80271cc:	e13ffd15 	stw	r4,-12(fp)
+ 80271d0:	2805883a 	mov	r2,r5
+ 80271d4:	e0bffc05 	stb	r2,-16(fp)
+   int   i;
+   char *   out   =  eth_prt_buf;
+ 80271d8:	008201b4 	movhi	r2,2054
+ 80271dc:	10b78d04 	addi	r2,r2,-8652
+ 80271e0:	e0bffe15 	stw	r2,-8(fp)
+
+   /* loop through 6 bytes of ethernet address */
+   for (i = 0; i < 6; i++)
+ 80271e4:	e03fff15 	stw	zero,-4(fp)
+ 80271e8:	00003f06 	br	80272e8 <print_eth+0x128>
+   {
+      /* high nibble */
+      *out = (char)(((*addr >> 4) & 0x0f) + 0x30);
+ 80271ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80271f0:	10800003 	ldbu	r2,0(r2)
+ 80271f4:	10803fcc 	andi	r2,r2,255
+ 80271f8:	1004d13a 	srli	r2,r2,4
+ 80271fc:	10800c04 	addi	r2,r2,48
+ 8027200:	1007883a 	mov	r3,r2
+ 8027204:	e0bffe17 	ldw	r2,-8(fp)
+ 8027208:	10c00005 	stb	r3,0(r2)
+      if (*out > '9')   /* need to make it A-F? */
+ 802720c:	e0bffe17 	ldw	r2,-8(fp)
+ 8027210:	10800003 	ldbu	r2,0(r2)
+ 8027214:	10803fcc 	andi	r2,r2,255
+ 8027218:	1080201c 	xori	r2,r2,128
+ 802721c:	10bfe004 	addi	r2,r2,-128
+ 8027220:	10800e90 	cmplti	r2,r2,58
+ 8027224:	1000061e 	bne	r2,zero,8027240 <print_eth+0x80>
+         (*out) += 7;
+ 8027228:	e0bffe17 	ldw	r2,-8(fp)
+ 802722c:	10800003 	ldbu	r2,0(r2)
+ 8027230:	108001c4 	addi	r2,r2,7
+ 8027234:	1007883a 	mov	r3,r2
+ 8027238:	e0bffe17 	ldw	r2,-8(fp)
+ 802723c:	10c00005 	stb	r3,0(r2)
+      out++;
+ 8027240:	e0bffe17 	ldw	r2,-8(fp)
+ 8027244:	10800044 	addi	r2,r2,1
+ 8027248:	e0bffe15 	stw	r2,-8(fp)
+
+      /* low nibble */
+      *out = (char)((*addr & 0x0f) + 0x30);  /* low nibble to digit */
+ 802724c:	e0bffd17 	ldw	r2,-12(fp)
+ 8027250:	10800003 	ldbu	r2,0(r2)
+ 8027254:	108003cc 	andi	r2,r2,15
+ 8027258:	10800c04 	addi	r2,r2,48
+ 802725c:	1007883a 	mov	r3,r2
+ 8027260:	e0bffe17 	ldw	r2,-8(fp)
+ 8027264:	10c00005 	stb	r3,0(r2)
+      if (*out > '9')   /* need to make it A-F? */
+ 8027268:	e0bffe17 	ldw	r2,-8(fp)
+ 802726c:	10800003 	ldbu	r2,0(r2)
+ 8027270:	10803fcc 	andi	r2,r2,255
+ 8027274:	1080201c 	xori	r2,r2,128
+ 8027278:	10bfe004 	addi	r2,r2,-128
+ 802727c:	10800e90 	cmplti	r2,r2,58
+ 8027280:	1000061e 	bne	r2,zero,802729c <print_eth+0xdc>
+         (*out) += 7;   /* eg 0x3a -> 0x41 ('A') */
+ 8027284:	e0bffe17 	ldw	r2,-8(fp)
+ 8027288:	10800003 	ldbu	r2,0(r2)
+ 802728c:	108001c4 	addi	r2,r2,7
+ 8027290:	1007883a 	mov	r3,r2
+ 8027294:	e0bffe17 	ldw	r2,-8(fp)
+ 8027298:	10c00005 	stb	r3,0(r2)
+      out++;
+ 802729c:	e0bffe17 	ldw	r2,-8(fp)
+ 80272a0:	10800044 	addi	r2,r2,1
+ 80272a4:	e0bffe15 	stw	r2,-8(fp)
+
+      /* optional spacer character */
+      if (spacer && i < 5)
+ 80272a8:	e0bffc07 	ldb	r2,-16(fp)
+ 80272ac:	10000826 	beq	r2,zero,80272d0 <print_eth+0x110>
+ 80272b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80272b4:	10800148 	cmpgei	r2,r2,5
+ 80272b8:	1000051e 	bne	r2,zero,80272d0 <print_eth+0x110>
+         *out++ = spacer;
+ 80272bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80272c0:	10c00044 	addi	r3,r2,1
+ 80272c4:	e0fffe15 	stw	r3,-8(fp)
+ 80272c8:	e0fffc03 	ldbu	r3,-16(fp)
+ 80272cc:	10c00005 	stb	r3,0(r2)
+      addr++;
+ 80272d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80272d4:	10800044 	addi	r2,r2,1
+ 80272d8:	e0bffd15 	stw	r2,-12(fp)
+   for (i = 0; i < 6; i++)
+ 80272dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80272e0:	10800044 	addi	r2,r2,1
+ 80272e4:	e0bfff15 	stw	r2,-4(fp)
+ 80272e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80272ec:	10800190 	cmplti	r2,r2,6
+ 80272f0:	103fbe1e 	bne	r2,zero,80271ec <print_eth+0x2c>
+   }
+   *out = 0;
+ 80272f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80272f8:	10000005 	stb	zero,0(r2)
+   return eth_prt_buf;
+ 80272fc:	008201b4 	movhi	r2,2054
+ 8027300:	10b78d04 	addi	r2,r2,-8652
+}
+ 8027304:	e037883a 	mov	sp,fp
+ 8027308:	df000017 	ldw	fp,0(sp)
+ 802730c:	dec00104 	addi	sp,sp,4
+ 8027310:	f800283a 	ret
+
+08027314 <uslash>:
+ * RETURNS:  pointer to formatted text
+ */
+
+char *   
+uslash(char * path)
+{
+ 8027314:	defffd04 	addi	sp,sp,-12
+ 8027318:	df000215 	stw	fp,8(sp)
+ 802731c:	df000204 	addi	fp,sp,8
+ 8027320:	e13ffe15 	stw	r4,-8(fp)
+   char *   cp;
+
+   for (cp = path; *cp; cp++)
+ 8027324:	e0bffe17 	ldw	r2,-8(fp)
+ 8027328:	e0bfff15 	stw	r2,-4(fp)
+ 802732c:	00000d06 	br	8027364 <uslash+0x50>
+      if (*cp == '\\')
+ 8027330:	e0bfff17 	ldw	r2,-4(fp)
+ 8027334:	10800003 	ldbu	r2,0(r2)
+ 8027338:	10803fcc 	andi	r2,r2,255
+ 802733c:	1080201c 	xori	r2,r2,128
+ 8027340:	10bfe004 	addi	r2,r2,-128
+ 8027344:	10801718 	cmpnei	r2,r2,92
+ 8027348:	1000031e 	bne	r2,zero,8027358 <uslash+0x44>
+      *cp = '/';
+ 802734c:	e0bfff17 	ldw	r2,-4(fp)
+ 8027350:	00c00bc4 	movi	r3,47
+ 8027354:	10c00005 	stb	r3,0(r2)
+   for (cp = path; *cp; cp++)
+ 8027358:	e0bfff17 	ldw	r2,-4(fp)
+ 802735c:	10800044 	addi	r2,r2,1
+ 8027360:	e0bfff15 	stw	r2,-4(fp)
+ 8027364:	e0bfff17 	ldw	r2,-4(fp)
+ 8027368:	10800003 	ldbu	r2,0(r2)
+ 802736c:	10803fcc 	andi	r2,r2,255
+ 8027370:	1080201c 	xori	r2,r2,128
+ 8027374:	10bfe004 	addi	r2,r2,-128
+ 8027378:	103fed1e 	bne	r2,zero,8027330 <uslash+0x1c>
+   return path;
+ 802737c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8027380:	e037883a 	mov	sp,fp
+ 8027384:	df000017 	ldw	fp,0(sp)
+ 8027388:	dec00104 	addi	sp,sp,4
+ 802738c:	f800283a 	ret
+
+08027390 <ns_printf>:
+ */
+#ifndef ns_printf
+
+int 
+ns_printf(void * vio, char * format, ...)
+{
+ 8027390:	defff304 	addi	sp,sp,-52
+ 8027394:	dfc00a15 	stw	ra,40(sp)
+ 8027398:	df000915 	stw	fp,36(sp)
+ 802739c:	dc400815 	stw	r17,32(sp)
+ 80273a0:	dc000715 	stw	r16,28(sp)
+ 80273a4:	df000904 	addi	fp,sp,36
+ 80273a8:	e13ff815 	stw	r4,-32(fp)
+ 80273ac:	e17ff715 	stw	r5,-36(fp)
+ 80273b0:	e1800215 	stw	r6,8(fp)
+ 80273b4:	e1c00315 	stw	r7,12(fp)
+   char *   outbuf=NULL;
+ 80273b8:	e03ffc15 	stw	zero,-16(fp)
+   int   ret_value   ;
+   int   buf_size =  MAXIOSIZE   ;
+ 80273bc:	00802704 	movi	r2,156
+ 80273c0:	e0bffd15 	stw	r2,-12(fp)
+   GEN_IO pio = (GEN_IO)vio;  /* convert void* to our IO device type */
+ 80273c4:	e0bff817 	ldw	r2,-32(fp)
+ 80273c8:	e0bffb15 	stw	r2,-20(fp)
+   int * next_arg=(int *)  &format;
+   next_arg +=  sizeof(char *)/sizeof(int) ;
+#endif   /* NATIVE_PRINTF || PRINTF_STRING */
+
+   /* a NULL pio means just dump the output to stdout */
+   if (pio == NULL)
+ 80273cc:	e0bffb17 	ldw	r2,-20(fp)
+ 80273d0:	1000091e 	bne	r2,zero,80273f8 <ns_printf+0x68>
+   {
+#ifdef NATIVE_PRINTF
+      /* use the target system's ANSI routines */
+      va_start(argList,format);
+ 80273d4:	e0800204 	addi	r2,fp,8
+ 80273d8:	e0bff915 	stw	r2,-28(fp)
+      ret_value = vprintf(format,argList);
+ 80273dc:	e0bff917 	ldw	r2,-28(fp)
+ 80273e0:	100b883a 	mov	r5,r2
+ 80273e4:	e13ff717 	ldw	r4,-36(fp)
+ 80273e8:	80454580 	call	8045458 <vprintf>
+ 80273ec:	e0bffa15 	stw	r2,-24(fp)
+      va_end(argList);
+      return ret_value;
+ 80273f0:	e0bffa17 	ldw	r2,-24(fp)
+ 80273f4:	00003b06 	br	80274e4 <ns_printf+0x154>
+      return strlen(format);
+#endif   /* NATIVE_PRINTF */
+   }
+
+   /* Check if the output function is set */
+   if (pio->out == NULL)
+ 80273f8:	e0bffb17 	ldw	r2,-20(fp)
+ 80273fc:	10800117 	ldw	r2,4(r2)
+ 8027400:	1000021e 	bne	r2,zero,802740c <ns_printf+0x7c>
+   {
+      /* Programming mistake. Output function not set. */
+      return -1;
+ 8027404:	00bfffc4 	movi	r2,-1
+ 8027408:	00003606 	br	80274e4 <ns_printf+0x154>
+
+   /* Allocate memory for the output string 
+    * If the format string is greater than MAXIOSIZE, then
+    * we surely need to allocate a bigger block
+    */
+   ret_value = strlen(format); 
+ 802740c:	e13ff717 	ldw	r4,-36(fp)
+ 8027410:	8002dac0 	call	8002dac <strlen>
+ 8027414:	e0bffa15 	stw	r2,-24(fp)
+   if (ret_value >= MAXIOSIZE)
+ 8027418:	e0bffa17 	ldw	r2,-24(fp)
+ 802741c:	10802710 	cmplti	r2,r2,156
+ 8027420:	1000041e 	bne	r2,zero,8027434 <ns_printf+0xa4>
+   {
+      buf_size += ret_value ;
+ 8027424:	e0fffd17 	ldw	r3,-12(fp)
+ 8027428:	e0bffa17 	ldw	r2,-24(fp)
+ 802742c:	1885883a 	add	r2,r3,r2
+ 8027430:	e0bffd15 	stw	r2,-12(fp)
+   }
+
+   outbuf=(char *)npalloc(buf_size); 
+ 8027434:	e0bffd17 	ldw	r2,-12(fp)
+ 8027438:	1009883a 	mov	r4,r2
+ 802743c:	802982c0 	call	802982c <npalloc>
+ 8027440:	e0bffc15 	stw	r2,-16(fp)
+
+   if (outbuf == NULL)
+ 8027444:	e0bffc17 	ldw	r2,-16(fp)
+ 8027448:	1000021e 	bne	r2,zero,8027454 <ns_printf+0xc4>
+   {
+      return -2;
+ 802744c:	00bfff84 	movi	r2,-2
+ 8027450:	00002406 	br	80274e4 <ns_printf+0x154>
+
+   /* Now populate the output string */
+
+#ifdef NATIVE_PRINTF
+   /* use the target system's ANSI routines */
+   va_start(argList,format);
+ 8027454:	e0800204 	addi	r2,fp,8
+ 8027458:	e0bff915 	stw	r2,-28(fp)
+   ret_value = vsprintf(outbuf,format,argList);
+ 802745c:	e0bff917 	ldw	r2,-28(fp)
+ 8027460:	100d883a 	mov	r6,r2
+ 8027464:	e17ff717 	ldw	r5,-36(fp)
+ 8027468:	e13ffc17 	ldw	r4,-16(fp)
+ 802746c:	80454d00 	call	80454d0 <vsprintf>
+ 8027470:	e0bffa15 	stw	r2,-24(fp)
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+
+#ifdef NATIVE_PRINTF
+   /* Check if we have overwritten the output buffer */
+   if ((int)strlen(outbuf) > buf_size)
+ 8027474:	e13ffc17 	ldw	r4,-16(fp)
+ 8027478:	8002dac0 	call	8002dac <strlen>
+ 802747c:	1007883a 	mov	r3,r2
+ 8027480:	e0bffd17 	ldw	r2,-12(fp)
+ 8027484:	10c0080e 	bge	r2,r3,80274a8 <ns_printf+0x118>
+       */
+      /* Yes , we have overwritten. Truncate the output string.
+       * Some memory in the heap has been corrupted, but it is too
+       * late to rectify.
+       */
+      panic("ns_printf:Buffer overflow");
+ 8027488:	01020174 	movhi	r4,2053
+ 802748c:	21289b04 	addi	r4,r4,-23956
+ 8027490:	80271780 	call	8027178 <panic>
+      outbuf[buf_size-1]=0;   /* Null terminate the string */
+ 8027494:	e0bffd17 	ldw	r2,-12(fp)
+ 8027498:	10bfffc4 	addi	r2,r2,-1
+ 802749c:	e0fffc17 	ldw	r3,-16(fp)
+ 80274a0:	1885883a 	add	r2,r3,r2
+ 80274a4:	10000005 	stb	zero,0(r2)
+   }
+#endif
+
+   ret_value =(pio->out)(pio->id,outbuf,strlen(outbuf)) ;
+ 80274a8:	e0bffb17 	ldw	r2,-20(fp)
+ 80274ac:	14000117 	ldw	r16,4(r2)
+ 80274b0:	e0bffb17 	ldw	r2,-20(fp)
+ 80274b4:	14400217 	ldw	r17,8(r2)
+ 80274b8:	e13ffc17 	ldw	r4,-16(fp)
+ 80274bc:	8002dac0 	call	8002dac <strlen>
+ 80274c0:	100d883a 	mov	r6,r2
+ 80274c4:	e17ffc17 	ldw	r5,-16(fp)
+ 80274c8:	8809883a 	mov	r4,r17
+ 80274cc:	803ee83a 	callr	r16
+ 80274d0:	e0bffa15 	stw	r2,-24(fp)
+
+   /* Free memory for the output string */
+   npfree(outbuf); 
+ 80274d4:	e13ffc17 	ldw	r4,-16(fp)
+ 80274d8:	80298600 	call	8029860 <npfree>
+
+   /* since ns_printf() can get called repeatedly down in the bowels 
+    * of a single command interpretting function, spin tk_yield() so 
+    * that some packets get a chance to get received 
+    */
+   tk_yield();
+ 80274dc:	8027ce40 	call	8027ce4 <tk_yield>
+
+   return ret_value ;
+ 80274e0:	e0bffa17 	ldw	r2,-24(fp)
+}
+ 80274e4:	e6fffe04 	addi	sp,fp,-8
+ 80274e8:	dfc00317 	ldw	ra,12(sp)
+ 80274ec:	df000217 	ldw	fp,8(sp)
+ 80274f0:	dc400117 	ldw	r17,4(sp)
+ 80274f4:	dc000017 	ldw	r16,0(sp)
+ 80274f8:	dec00604 	addi	sp,sp,24
+ 80274fc:	f800283a 	ret
+
+08027500 <std_out>:
+ *
+ * RETURNS: Number of bytes send to standard output. 
+ */
+
+int std_out(long s, char * buf, int len)
+{
+ 8027500:	defffb04 	addi	sp,sp,-20
+ 8027504:	dfc00415 	stw	ra,16(sp)
+ 8027508:	df000315 	stw	fp,12(sp)
+ 802750c:	df000304 	addi	fp,sp,12
+ 8027510:	e13fff15 	stw	r4,-4(fp)
+ 8027514:	e17ffe15 	stw	r5,-8(fp)
+ 8027518:	e1bffd15 	stw	r6,-12(fp)
+   /* puts(buf); - This does newline expansion return 
+    * write(0,buf,len); - This doesn't printf(buf); - This has 
+    * problems when printf format strings (eg %s) is part of data. 
+    */
+   printf("%s",buf);
+ 802751c:	e17ffe17 	ldw	r5,-8(fp)
+ 8027520:	01020174 	movhi	r4,2053
+ 8027524:	2128a204 	addi	r4,r4,-23928
+ 8027528:	8002c780 	call	8002c78 <printf>
+   USE_ARG(s);
+   return len;
+ 802752c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8027530:	e037883a 	mov	sp,fp
+ 8027534:	dfc00117 	ldw	ra,4(sp)
+ 8027538:	df000017 	ldw	fp,0(sp)
+ 802753c:	dec00204 	addi	sp,sp,8
+ 8027540:	f800283a 	ret
+
+08027544 <con_page>:
+ * RETURNS: 1 if we got a break, 0 to keep printing
+ */
+
+int
+con_page(void * vio, int lines)
+{
+ 8027544:	defffa04 	addi	sp,sp,-24
+ 8027548:	dfc00515 	stw	ra,20(sp)
+ 802754c:	df000415 	stw	fp,16(sp)
+ 8027550:	df000404 	addi	fp,sp,16
+ 8027554:	e13ffd15 	stw	r4,-12(fp)
+ 8027558:	e17ffc15 	stw	r5,-16(fp)
+   int   ch;
+   GEN_IO pio = (GEN_IO)vio;  /* convert void* to our IO device type */
+ 802755c:	e0bffd17 	ldw	r2,-12(fp)
+ 8027560:	e0bfff15 	stw	r2,-4(fp)
+
+   if (lines % 20 == 0)   /* Time to get user input */
+ 8027564:	e0bffc17 	ldw	r2,-16(fp)
+ 8027568:	01400504 	movi	r5,20
+ 802756c:	1009883a 	mov	r4,r2
+ 8027570:	800cf800 	call	800cf80 <__modsi3>
+ 8027574:	1000231e 	bne	r2,zero,8027604 <con_page+0xc0>
+   {
+      if (pio && pio->getch)   /*if i/p func is supplied*/
+ 8027578:	e0bfff17 	ldw	r2,-4(fp)
+ 802757c:	10002126 	beq	r2,zero,8027604 <con_page+0xc0>
+ 8027580:	e0bfff17 	ldw	r2,-4(fp)
+ 8027584:	10800317 	ldw	r2,12(r2)
+ 8027588:	10001e26 	beq	r2,zero,8027604 <con_page+0xc0>
+      {
+         ns_printf(pio,"....press any key for more (ESC to break)....");
+ 802758c:	01420174 	movhi	r5,2053
+ 8027590:	2968a304 	addi	r5,r5,-23924
+ 8027594:	e13fff17 	ldw	r4,-4(fp)
+ 8027598:	80273900 	call	8027390 <ns_printf>
+
+         do 
+         {
+            ch = (pio->getch)(pio->id);
+ 802759c:	e0bfff17 	ldw	r2,-4(fp)
+ 80275a0:	10800317 	ldw	r2,12(r2)
+ 80275a4:	e0ffff17 	ldw	r3,-4(fp)
+ 80275a8:	18c00217 	ldw	r3,8(r3)
+ 80275ac:	1809883a 	mov	r4,r3
+ 80275b0:	103ee83a 	callr	r2
+ 80275b4:	e0bffe15 	stw	r2,-8(fp)
+            if (ch == 0)
+ 80275b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80275bc:	1000011e 	bne	r2,zero,80275c4 <con_page+0x80>
+               tk_yield();    /* Give timeslice to other processes */
+ 80275c0:	8027ce40 	call	8027ce4 <tk_yield>
+         } while (ch == 0) ;
+ 80275c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80275c8:	103ff426 	beq	r2,zero,802759c <con_page+0x58>
+
+            /* if there is fatal error, we don't want to do any I/O */
+         if (ch == -1)   /* fatal error */
+ 80275cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80275d0:	10bfffd8 	cmpnei	r2,r2,-1
+ 80275d4:	1000021e 	bne	r2,zero,80275e0 <con_page+0x9c>
+            return 1 ;
+ 80275d8:	00800044 	movi	r2,1
+ 80275dc:	00000a06 	br	8027608 <con_page+0xc4>
+
+         ns_printf(pio,"\n");
+ 80275e0:	01420174 	movhi	r5,2053
+ 80275e4:	29688404 	addi	r5,r5,-24048
+ 80275e8:	e13fff17 	ldw	r4,-4(fp)
+ 80275ec:	80273900 	call	8027390 <ns_printf>
+         if (ch == 27)   /* ESC key pressed */
+ 80275f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80275f4:	108006d8 	cmpnei	r2,r2,27
+ 80275f8:	1000021e 	bne	r2,zero,8027604 <con_page+0xc0>
+            return 1 ;
+ 80275fc:	00800044 	movi	r2,1
+ 8027600:	00000106 	br	8027608 <con_page+0xc4>
+      }
+   }
+   return  0;
+ 8027604:	0005883a 	mov	r2,zero
+}
+ 8027608:	e037883a 	mov	sp,fp
+ 802760c:	dfc00117 	ldw	ra,4(sp)
+ 8027610:	df000017 	ldw	fp,0(sp)
+ 8027614:	dec00204 	addi	sp,sp,8
+ 8027618:	f800283a 	ret
+
+0802761c <parse_args>:
+
+char **parse_args(char *buf, int argc, int *pargc_index)
+{
+ 802761c:	defff704 	addi	sp,sp,-36
+ 8027620:	dfc00815 	stw	ra,32(sp)
+ 8027624:	df000715 	stw	fp,28(sp)
+ 8027628:	df000704 	addi	fp,sp,28
+ 802762c:	e13ffb15 	stw	r4,-20(fp)
+ 8027630:	e17ffa15 	stw	r5,-24(fp)
+ 8027634:	e1bff915 	stw	r6,-28(fp)
+   /* This routine assumes buf is a null terminated string */
+   int i;
+   int len;
+   char *bp = buf;
+ 8027638:	e0bffb17 	ldw	r2,-20(fp)
+ 802763c:	e0bffe15 	stw	r2,-8(fp)
+   char **pargv = NULL;
+ 8027640:	e03ffd15 	stw	zero,-12(fp)
+   *pargc_index = 0;
+ 8027644:	e0bff917 	ldw	r2,-28(fp)
+ 8027648:	10000015 	stw	zero,0(r2)
+   if (buf == NULL)
+ 802764c:	e0bffb17 	ldw	r2,-20(fp)
+ 8027650:	1000021e 	bne	r2,zero,802765c <parse_args+0x40>
+   {
+      return (NULL);
+ 8027654:	0005883a 	mov	r2,zero
+ 8027658:	00006906 	br	8027800 <parse_args+0x1e4>
+   }
+   len = strlen(buf);
+ 802765c:	e13ffb17 	ldw	r4,-20(fp)
+ 8027660:	8002dac0 	call	8002dac <strlen>
+ 8027664:	e0bffc15 	stw	r2,-16(fp)
+   if (len <= 0)
+ 8027668:	e0bffc17 	ldw	r2,-16(fp)
+ 802766c:	00800216 	blt	zero,r2,8027678 <parse_args+0x5c>
+   {
+      return (NULL);
+ 8027670:	0005883a 	mov	r2,zero
+ 8027674:	00006206 	br	8027800 <parse_args+0x1e4>
+   }
+   pargv = (char **) npalloc(argc * sizeof(char *));
+ 8027678:	e0bffa17 	ldw	r2,-24(fp)
+ 802767c:	100490ba 	slli	r2,r2,2
+ 8027680:	1009883a 	mov	r4,r2
+ 8027684:	802982c0 	call	802982c <npalloc>
+ 8027688:	e0bffd15 	stw	r2,-12(fp)
+   if (pargv == NULL)
+ 802768c:	e0bffd17 	ldw	r2,-12(fp)
+ 8027690:	1000051e 	bne	r2,zero,80276a8 <parse_args+0x8c>
+   {
+      return (NULL);
+ 8027694:	0005883a 	mov	r2,zero
+ 8027698:	00005906 	br	8027800 <parse_args+0x1e4>
+   }
+   /* skip the initial blanks if any */
+   while (*bp == ' ')
+   {
+      bp++;
+ 802769c:	e0bffe17 	ldw	r2,-8(fp)
+ 80276a0:	10800044 	addi	r2,r2,1
+ 80276a4:	e0bffe15 	stw	r2,-8(fp)
+   while (*bp == ' ')
+ 80276a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80276ac:	10800003 	ldbu	r2,0(r2)
+ 80276b0:	10803fcc 	andi	r2,r2,255
+ 80276b4:	1080201c 	xori	r2,r2,128
+ 80276b8:	10bfe004 	addi	r2,r2,-128
+ 80276bc:	10800820 	cmpeqi	r2,r2,32
+ 80276c0:	103ff61e 	bne	r2,zero,802769c <parse_args+0x80>
+   }
+   while ((*bp != '\0') && ((*pargc_index) < argc))
+ 80276c4:	00002e06 	br	8027780 <parse_args+0x164>
+   {
+      pargv[(*pargc_index)] = bp;
+ 80276c8:	e0bff917 	ldw	r2,-28(fp)
+ 80276cc:	10800017 	ldw	r2,0(r2)
+ 80276d0:	100490ba 	slli	r2,r2,2
+ 80276d4:	e0fffd17 	ldw	r3,-12(fp)
+ 80276d8:	1885883a 	add	r2,r3,r2
+ 80276dc:	e0fffe17 	ldw	r3,-8(fp)
+ 80276e0:	10c00015 	stw	r3,0(r2)
+      (*pargc_index)++;
+ 80276e4:	e0bff917 	ldw	r2,-28(fp)
+ 80276e8:	10800017 	ldw	r2,0(r2)
+ 80276ec:	10c00044 	addi	r3,r2,1
+ 80276f0:	e0bff917 	ldw	r2,-28(fp)
+ 80276f4:	10c00015 	stw	r3,0(r2)
+      while (*bp != ' ' && *bp != '\0')
+ 80276f8:	00000306 	br	8027708 <parse_args+0xec>
+      {
+         bp++; 
+ 80276fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8027700:	10800044 	addi	r2,r2,1
+ 8027704:	e0bffe15 	stw	r2,-8(fp)
+      while (*bp != ' ' && *bp != '\0')
+ 8027708:	e0bffe17 	ldw	r2,-8(fp)
+ 802770c:	10800003 	ldbu	r2,0(r2)
+ 8027710:	10803fcc 	andi	r2,r2,255
+ 8027714:	1080201c 	xori	r2,r2,128
+ 8027718:	10bfe004 	addi	r2,r2,-128
+ 802771c:	10800820 	cmpeqi	r2,r2,32
+ 8027720:	10000a1e 	bne	r2,zero,802774c <parse_args+0x130>
+ 8027724:	e0bffe17 	ldw	r2,-8(fp)
+ 8027728:	10800003 	ldbu	r2,0(r2)
+ 802772c:	10803fcc 	andi	r2,r2,255
+ 8027730:	1080201c 	xori	r2,r2,128
+ 8027734:	10bfe004 	addi	r2,r2,-128
+ 8027738:	103ff01e 	bne	r2,zero,80276fc <parse_args+0xe0>
+      }
+      while (*bp == ' ' && *bp != '\0')
+ 802773c:	00000306 	br	802774c <parse_args+0x130>
+      {
+         bp++; 
+ 8027740:	e0bffe17 	ldw	r2,-8(fp)
+ 8027744:	10800044 	addi	r2,r2,1
+ 8027748:	e0bffe15 	stw	r2,-8(fp)
+      while (*bp == ' ' && *bp != '\0')
+ 802774c:	e0bffe17 	ldw	r2,-8(fp)
+ 8027750:	10800003 	ldbu	r2,0(r2)
+ 8027754:	10803fcc 	andi	r2,r2,255
+ 8027758:	1080201c 	xori	r2,r2,128
+ 802775c:	10bfe004 	addi	r2,r2,-128
+ 8027760:	10800818 	cmpnei	r2,r2,32
+ 8027764:	1000061e 	bne	r2,zero,8027780 <parse_args+0x164>
+ 8027768:	e0bffe17 	ldw	r2,-8(fp)
+ 802776c:	10800003 	ldbu	r2,0(r2)
+ 8027770:	10803fcc 	andi	r2,r2,255
+ 8027774:	1080201c 	xori	r2,r2,128
+ 8027778:	10bfe004 	addi	r2,r2,-128
+ 802777c:	103ff01e 	bne	r2,zero,8027740 <parse_args+0x124>
+   while ((*bp != '\0') && ((*pargc_index) < argc))
+ 8027780:	e0bffe17 	ldw	r2,-8(fp)
+ 8027784:	10800003 	ldbu	r2,0(r2)
+ 8027788:	10803fcc 	andi	r2,r2,255
+ 802778c:	1080201c 	xori	r2,r2,128
+ 8027790:	10bfe004 	addi	r2,r2,-128
+ 8027794:	10000426 	beq	r2,zero,80277a8 <parse_args+0x18c>
+ 8027798:	e0bff917 	ldw	r2,-28(fp)
+ 802779c:	10c00017 	ldw	r3,0(r2)
+ 80277a0:	e0bffa17 	ldw	r2,-24(fp)
+ 80277a4:	18bfc816 	blt	r3,r2,80276c8 <parse_args+0xac>
+      }
+   }
+   for (i = 0; i < len; i++)
+ 80277a8:	e03fff15 	stw	zero,-4(fp)
+ 80277ac:	00001006 	br	80277f0 <parse_args+0x1d4>
+   {
+      if (buf[i] == ' ')
+ 80277b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80277b4:	e0fffb17 	ldw	r3,-20(fp)
+ 80277b8:	1885883a 	add	r2,r3,r2
+ 80277bc:	10800003 	ldbu	r2,0(r2)
+ 80277c0:	10803fcc 	andi	r2,r2,255
+ 80277c4:	1080201c 	xori	r2,r2,128
+ 80277c8:	10bfe004 	addi	r2,r2,-128
+ 80277cc:	10800818 	cmpnei	r2,r2,32
+ 80277d0:	1000041e 	bne	r2,zero,80277e4 <parse_args+0x1c8>
+         buf[i] = '\0';
+ 80277d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80277d8:	e0fffb17 	ldw	r3,-20(fp)
+ 80277dc:	1885883a 	add	r2,r3,r2
+ 80277e0:	10000005 	stb	zero,0(r2)
+   for (i = 0; i < len; i++)
+ 80277e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80277e8:	10800044 	addi	r2,r2,1
+ 80277ec:	e0bfff15 	stw	r2,-4(fp)
+ 80277f0:	e0ffff17 	ldw	r3,-4(fp)
+ 80277f4:	e0bffc17 	ldw	r2,-16(fp)
+ 80277f8:	18bfed16 	blt	r3,r2,80277b0 <parse_args+0x194>
+   {
+      printf("pargv[%d] = %s\n", i, pargv[i]);
+   }
+#endif
+
+   return (pargv);
+ 80277fc:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8027800:	e037883a 	mov	sp,fp
+ 8027804:	dfc00117 	ldw	ra,4(sp)
+ 8027808:	df000017 	ldw	fp,0(sp)
+ 802780c:	dec00204 	addi	sp,sp,8
+ 8027810:	f800283a 	ret
+
+08027814 <netmain>:
+ * RETURNS: 
+ */
+
+int
+netmain(void)
+{
+ 8027814:	defffc04 	addi	sp,sp,-16
+ 8027818:	dfc00315 	stw	ra,12(sp)
+ 802781c:	df000215 	stw	fp,8(sp)
+ 8027820:	df000204 	addi	fp,sp,8
+   int   i;
+   int   e;
+
+   iniche_net_ready = FALSE;
+ 8027824:	d0206f15 	stw	zero,-32324(gp)
+
+   e = prep_modules();
+ 8027828:	8038a5c0 	call	8038a5c <prep_modules>
+ 802782c:	e0bffe15 	stw	r2,-8(fp)
+
+   /* Create the threads for net, timer, and apps */
+   for (i = 0; i < num_net_tasks; i++)
+ 8027830:	e03fff15 	stw	zero,-4(fp)
+ 8027834:	00001a06 	br	80278a0 <netmain+0x8c>
+   {
+      e = TK_NEWTASK(&nettasks[i]);
+ 8027838:	e0bfff17 	ldw	r2,-4(fp)
+ 802783c:	10c00624 	muli	r3,r2,24
+ 8027840:	00820174 	movhi	r2,2053
+ 8027844:	10b1ec04 	addi	r2,r2,-14416
+ 8027848:	1885883a 	add	r2,r3,r2
+ 802784c:	1009883a 	mov	r4,r2
+ 8027850:	80290740 	call	8029074 <TK_NEWTASK>
+ 8027854:	e0bffe15 	stw	r2,-8(fp)
+      if (e != 0)
+ 8027858:	e0bffe17 	ldw	r2,-8(fp)
+ 802785c:	10000d26 	beq	r2,zero,8027894 <netmain+0x80>
+      {
+         dprintf("task create error\n");
+ 8027860:	01020174 	movhi	r4,2053
+ 8027864:	2128b504 	addi	r4,r4,-23852
+ 8027868:	8002d9c0 	call	8002d9c <puts>
+         panic((char *)&nettasks[i].name);
+ 802786c:	e0bfff17 	ldw	r2,-4(fp)
+ 8027870:	10800624 	muli	r2,r2,24
+ 8027874:	10c00104 	addi	r3,r2,4
+ 8027878:	00820174 	movhi	r2,2053
+ 802787c:	10b1ec04 	addi	r2,r2,-14416
+ 8027880:	1885883a 	add	r2,r3,r2
+ 8027884:	1009883a 	mov	r4,r2
+ 8027888:	80271780 	call	8027178 <panic>
+         return -1;  /* compiler warnings */
+ 802788c:	00bfffc4 	movi	r2,-1
+ 8027890:	00001306 	br	80278e0 <netmain+0xcc>
+   for (i = 0; i < num_net_tasks; i++)
+ 8027894:	e0bfff17 	ldw	r2,-4(fp)
+ 8027898:	10800044 	addi	r2,r2,1
+ 802789c:	e0bfff15 	stw	r2,-4(fp)
+ 80278a0:	d0a01417 	ldw	r2,-32688(gp)
+ 80278a4:	e0ffff17 	ldw	r3,-4(fp)
+ 80278a8:	18bfe316 	blt	r3,r2,8027838 <netmain+0x24>
+      }
+   }
+   
+   e = create_apptasks();
+ 80278ac:	8038e380 	call	8038e38 <create_apptasks>
+ 80278b0:	e0bffe15 	stw	r2,-8(fp)
+   if (e != 0) 
+ 80278b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80278b8:	10000826 	beq	r2,zero,80278dc <netmain+0xc8>
+   {
+      dprintf("task create error\n");
+ 80278bc:	01020174 	movhi	r4,2053
+ 80278c0:	2128b504 	addi	r4,r4,-23852
+ 80278c4:	8002d9c0 	call	8002d9c <puts>
+      panic("netmain");
+ 80278c8:	01020174 	movhi	r4,2053
+ 80278cc:	2128ba04 	addi	r4,r4,-23832
+ 80278d0:	80271780 	call	8027178 <panic>
+      return -1;  /* compiler warnings */
+ 80278d4:	00bfffc4 	movi	r2,-1
+ 80278d8:	00000106 	br	80278e0 <netmain+0xcc>
+#ifdef MAIN_TASK_IS_NET
+   tk_netmain(TK_NETMAINPARM);
+   panic("net task return");
+   return -1;
+#else
+   return 0;
+ 80278dc:	0005883a 	mov	r2,zero
+#endif
+#endif   /* NO_INET_STACK */
+}
+ 80278e0:	e037883a 	mov	sp,fp
+ 80278e4:	dfc00117 	ldw	ra,4(sp)
+ 80278e8:	df000017 	ldw	fp,0(sp)
+ 80278ec:	dec00204 	addi	sp,sp,8
+ 80278f0:	f800283a 	ret
+
+080278f4 <tk_netmain>:
+ * RETURNS: n/a
+ */
+
+#ifndef NO_INET_STACK
+TK_ENTRY(tk_netmain)
+{
+ 80278f4:	defffc04 	addi	sp,sp,-16
+ 80278f8:	dfc00315 	stw	ra,12(sp)
+ 80278fc:	df000215 	stw	fp,8(sp)
+ 8027900:	df000204 	addi	fp,sp,8
+ 8027904:	e13ffe15 	stw	r4,-8(fp)
+   netmain_init(); /* initialize all modules */
+ 8027908:	80386dc0 	call	80386dc <netmain_init>
+
+   iniche_net_ready = TRUE;    /* let the other threads spin */
+ 802790c:	00800044 	movi	r2,1
+ 8027910:	d0a06f15 	stw	r2,-32324(gp)
+
+   for (;;)
+   {
+      TK_NETRX_BLOCK();
+ 8027914:	d0a08017 	ldw	r2,-32256(gp)
+ 8027918:	e0ffffc4 	addi	r3,fp,-1
+ 802791c:	180d883a 	mov	r6,r3
+ 8027920:	01401904 	movi	r5,100
+ 8027924:	1009883a 	mov	r4,r2
+ 8027928:	8015a600 	call	8015a60 <OSSemPend>
+ 802792c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8027930:	10803fcc 	andi	r2,r2,255
+ 8027934:	10000526 	beq	r2,zero,802794c <tk_netmain+0x58>
+ 8027938:	e0bfffc3 	ldbu	r2,-1(fp)
+ 802793c:	10803fcc 	andi	r2,r2,255
+ 8027940:	108002a0 	cmpeqi	r2,r2,10
+ 8027944:	1000011e 	bne	r2,zero,802794c <tk_netmain+0x58>
+ 8027948:	8028cd40 	call	8028cd4 <dtrap>
+      netmain_wakes++;  /* count wakeups */
+ 802794c:	d0a06d17 	ldw	r2,-32332(gp)
+ 8027950:	10800044 	addi	r2,r2,1
+ 8027954:	d0a06d15 	stw	r2,-32332(gp)
+
+      /* see if there's newly received network packets */
+      if (rcvdq.q_len)
+ 8027958:	008201b4 	movhi	r2,2054
+ 802795c:	10b6ad17 	ldw	r2,-9548(r2)
+ 8027960:	103fec26 	beq	r2,zero,8027914 <tk_netmain+0x20>
+         pktdemux();
+ 8027964:	80249c40 	call	80249c4 <pktdemux>
+      TK_NETRX_BLOCK();
+ 8027968:	003fea06 	br	8027914 <tk_netmain+0x20>
+
+0802796c <tk_nettick>:
+extern   int dhc_second(void);
+#endif
+
+#ifndef NO_INET_TICK
+TK_ENTRY(tk_nettick)
+{
+ 802796c:	defffd04 	addi	sp,sp,-12
+ 8027970:	dfc00215 	stw	ra,8(sp)
+ 8027974:	df000115 	stw	fp,4(sp)
+ 8027978:	df000104 	addi	fp,sp,4
+ 802797c:	e13fff15 	stw	r4,-4(fp)
+   /* wait till the stack is initialized */
+   while (!iniche_net_ready)
+ 8027980:	00000206 	br	802798c <tk_nettick+0x20>
+       * run to restart it.
+       */
+#ifdef DHCP_CLIENT
+      dhc_second();
+#endif
+      TK_SLEEP(1);
+ 8027984:	01000084 	movi	r4,2
+ 8027988:	801730c0 	call	801730c <OSTimeDly>
+   while (!iniche_net_ready)
+ 802798c:	d0a06f17 	ldw	r2,-32324(gp)
+ 8027990:	103ffc26 	beq	r2,zero,8027984 <tk_nettick+0x18>
+   }
+
+   for (;;)
+   {
+      TK_SLEEP(SYS_SHORT_SLEEP);
+ 8027994:	01000084 	movi	r4,2
+ 8027998:	801730c0 	call	801730c <OSTimeDly>
+      nettick_wakes++;  /* count wakeups */
+ 802799c:	d0a06e17 	ldw	r2,-32328(gp)
+ 80279a0:	10800044 	addi	r2,r2,1
+ 80279a4:	d0a06e15 	stw	r2,-32328(gp)
+      inet_timer();  /* let various timeouts occur */
+ 80279a8:	8038ab00 	call	8038ab0 <inet_timer>
+      TK_SLEEP(SYS_SHORT_SLEEP);
+ 80279ac:	003ff906 	br	8027994 <tk_nettick+0x28>
+
+080279b0 <TK_OSTimeDly>:
+u_char   TK_OSTaskQuery(void);
+
+
+
+void TK_OSTimeDly(void)
+{
+ 80279b0:	defffe04 	addi	sp,sp,-8
+ 80279b4:	dfc00115 	stw	ra,4(sp)
+ 80279b8:	df000015 	stw	fp,0(sp)
+ 80279bc:	d839883a 	mov	fp,sp
+   OSTimeDly(2);
+ 80279c0:	01000084 	movi	r4,2
+ 80279c4:	801730c0 	call	801730c <OSTimeDly>
+}
+ 80279c8:	0001883a 	nop
+ 80279cc:	e037883a 	mov	sp,fp
+ 80279d0:	dfc00117 	ldw	ra,4(sp)
+ 80279d4:	df000017 	ldw	fp,0(sp)
+ 80279d8:	dec00204 	addi	sp,sp,8
+ 80279dc:	f800283a 	ret
+
+080279e0 <TK_OSTaskResume>:
+
+
+
+void TK_OSTaskResume(u_char * Id)
+{
+ 80279e0:	defffc04 	addi	sp,sp,-16
+ 80279e4:	dfc00315 	stw	ra,12(sp)
+ 80279e8:	df000215 	stw	fp,8(sp)
+ 80279ec:	df000204 	addi	fp,sp,8
+ 80279f0:	e13ffe15 	stw	r4,-8(fp)
+INT8U err;
+
+   err = OSTaskResume(*Id);
+ 80279f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80279f8:	10800003 	ldbu	r2,0(r2)
+ 80279fc:	10803fcc 	andi	r2,r2,255
+ 8027a00:	1009883a 	mov	r4,r2
+ 8027a04:	8016ec00 	call	8016ec0 <OSTaskResume>
+ 8027a08:	e0bfffc5 	stb	r2,-1(fp)
+   
+#ifdef NPDEBUG
+   if ((err != OS_NO_ERR) && (err != OS_TASK_NOT_SUSPENDED))
+ 8027a0c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8027a10:	10000a26 	beq	r2,zero,8027a3c <TK_OSTaskResume+0x5c>
+ 8027a14:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8027a18:	10801120 	cmpeqi	r2,r2,68
+ 8027a1c:	1000071e 	bne	r2,zero,8027a3c <TK_OSTaskResume+0x5c>
+   {
+      dprintf("ChronOS API call failure, to Resume Suspended Task!\n");
+ 8027a20:	01020174 	movhi	r4,2053
+ 8027a24:	2128bc04 	addi	r4,r4,-23824
+ 8027a28:	8002d9c0 	call	8002d9c <puts>
+      dtrap();
+ 8027a2c:	8028cd40 	call	8028cd4 <dtrap>
+      panic("TK_OSTaskResume");      
+ 8027a30:	01020174 	movhi	r4,2053
+ 8027a34:	2128c904 	addi	r4,r4,-23772
+ 8027a38:	80271780 	call	8027178 <panic>
+   }
+#endif
+}
+ 8027a3c:	0001883a 	nop
+ 8027a40:	e037883a 	mov	sp,fp
+ 8027a44:	dfc00117 	ldw	ra,4(sp)
+ 8027a48:	df000017 	ldw	fp,0(sp)
+ 8027a4c:	dec00204 	addi	sp,sp,8
+ 8027a50:	f800283a 	ret
+
+08027a54 <tcp_sleep>:
+ *
+ * RETURN: none
+ */
+void
+tcp_sleep(void * event)
+{
+ 8027a54:	defffb04 	addi	sp,sp,-20
+ 8027a58:	dfc00415 	stw	ra,16(sp)
+ 8027a5c:	df000315 	stw	fp,12(sp)
+ 8027a60:	df000304 	addi	fp,sp,12
+ 8027a64:	e13ffd15 	stw	r4,-12(fp)
+   int i;
+   INT8U err;
+
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 8027a68:	e03fff15 	stw	zero,-4(fp)
+ 8027a6c:	00003d06 	br	8027b64 <tcp_sleep+0x110>
+   {
+      if (global_TCPwakeup_set[i].soc_event == NULL)
+ 8027a70:	e0bfff17 	ldw	r2,-4(fp)
+ 8027a74:	10c00324 	muli	r3,r2,12
+ 8027a78:	008201b4 	movhi	r2,2054
+ 8027a7c:	1885883a 	add	r2,r3,r2
+ 8027a80:	10b82017 	ldw	r2,-8064(r2)
+ 8027a84:	1000341e 	bne	r2,zero,8027b58 <tcp_sleep+0x104>
+      {
+         global_TCPwakeup_set[i].soc_event = event;
+ 8027a88:	e0bfff17 	ldw	r2,-4(fp)
+ 8027a8c:	11000324 	muli	r4,r2,12
+ 8027a90:	e0fffd17 	ldw	r3,-12(fp)
+ 8027a94:	008201b4 	movhi	r2,2054
+ 8027a98:	2085883a 	add	r2,r4,r2
+ 8027a9c:	10f82015 	stw	r3,-8064(r2)
+         global_TCPwakeup_set[i].ctick = cticks;
+ 8027aa0:	d0e07d17 	ldw	r3,-32268(gp)
+ 8027aa4:	e0bfff17 	ldw	r2,-4(fp)
+ 8027aa8:	11000324 	muli	r4,r2,12
+ 8027aac:	008201b4 	movhi	r2,2054
+ 8027ab0:	2085883a 	add	r2,r4,r2
+ 8027ab4:	10f81f15 	stw	r3,-8068(r2)
+         if (i > global_TCPwakeup_setIndx)
+ 8027ab8:	d0e07c17 	ldw	r3,-32272(gp)
+ 8027abc:	e0bfff17 	ldw	r2,-4(fp)
+ 8027ac0:	1880020e 	bge	r3,r2,8027acc <tcp_sleep+0x78>
+            global_TCPwakeup_setIndx = i;
+ 8027ac4:	e0bfff17 	ldw	r2,-4(fp)
+ 8027ac8:	d0a07c15 	stw	r2,-32272(gp)
+
+         tcp_sleep_count++;
+ 8027acc:	d0a07817 	ldw	r2,-32288(gp)
+ 8027ad0:	10800044 	addi	r2,r2,1
+ 8027ad4:	d0a07815 	stw	r2,-32288(gp)
+
+         /* Give up the lock before going to sleep. This can
+          * potentially cause a context switch to the task
+          * signaling the event.
+          */
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 8027ad8:	0009883a 	mov	r4,zero
+ 8027adc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+         /* don't wait forever in case we miss the event */
+         OSSemPend(global_TCPwakeup_set[i].semaphore, TPS, &err);
+ 8027ae0:	e0bfff17 	ldw	r2,-4(fp)
+ 8027ae4:	10c00324 	muli	r3,r2,12
+ 8027ae8:	008201b4 	movhi	r2,2054
+ 8027aec:	1885883a 	add	r2,r3,r2
+ 8027af0:	10b82117 	ldw	r2,-8060(r2)
+ 8027af4:	e0fffec4 	addi	r3,fp,-5
+ 8027af8:	180d883a 	mov	r6,r3
+ 8027afc:	01401904 	movi	r5,100
+ 8027b00:	1009883a 	mov	r4,r2
+ 8027b04:	8015a600 	call	8015a60 <OSSemPend>
+         if (err == 10)
+ 8027b08:	e0bffec3 	ldbu	r2,-5(fp)
+ 8027b0c:	10803fcc 	andi	r2,r2,255
+ 8027b10:	10800298 	cmpnei	r2,r2,10
+ 8027b14:	10000d1e 	bne	r2,zero,8027b4c <tcp_sleep+0xf8>
+         {
+            ++tcp_sleep_timeout;
+ 8027b18:	d0a07117 	ldw	r2,-32316(gp)
+ 8027b1c:	10800044 	addi	r2,r2,1
+ 8027b20:	d0a07115 	stw	r2,-32316(gp)
+
+            /* clear the entry */
+            global_TCPwakeup_set[i].ctick = 0;
+ 8027b24:	e0bfff17 	ldw	r2,-4(fp)
+ 8027b28:	10c00324 	muli	r3,r2,12
+ 8027b2c:	008201b4 	movhi	r2,2054
+ 8027b30:	1885883a 	add	r2,r3,r2
+ 8027b34:	10381f15 	stw	zero,-8068(r2)
+            global_TCPwakeup_set[i].soc_event = NULL;
+ 8027b38:	e0bfff17 	ldw	r2,-4(fp)
+ 8027b3c:	10c00324 	muli	r3,r2,12
+ 8027b40:	008201b4 	movhi	r2,2054
+ 8027b44:	1885883a 	add	r2,r3,r2
+ 8027b48:	10382015 	stw	zero,-8064(r2)
+         }
+
+         /* Regain the lock */
+         LOCK_NET_RESOURCE(NET_RESID);
+ 8027b4c:	0009883a 	mov	r4,zero
+ 8027b50:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+ 8027b54:	00000d06 	br	8027b8c <tcp_sleep+0x138>
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 8027b58:	e0bfff17 	ldw	r2,-4(fp)
+ 8027b5c:	10800044 	addi	r2,r2,1
+ 8027b60:	e0bfff15 	stw	r2,-4(fp)
+ 8027b64:	e0bfff17 	ldw	r2,-4(fp)
+ 8027b68:	10800510 	cmplti	r2,r2,20
+ 8027b6c:	103fc01e 	bne	r2,zero,8027a70 <tcp_sleep+0x1c>
+
+   /* The table is full. Try calling TK_YIELD() and hope for the best.
+    * The user should increase the size of the table.
+    * We'll record the max index for debugging purposes.
+    */
+   global_TCPwakeup_setIndx = i;
+ 8027b70:	e0bfff17 	ldw	r2,-4(fp)
+ 8027b74:	d0a07c15 	stw	r2,-32272(gp)
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 8027b78:	0009883a 	mov	r4,zero
+ 8027b7c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   TK_YIELD();
+ 8027b80:	8027ce40 	call	8027ce4 <tk_yield>
+   LOCK_NET_RESOURCE(NET_RESID);
+ 8027b84:	0009883a 	mov	r4,zero
+ 8027b88:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+}
+ 8027b8c:	e037883a 	mov	sp,fp
+ 8027b90:	dfc00117 	ldw	ra,4(sp)
+ 8027b94:	df000017 	ldw	fp,0(sp)
+ 8027b98:	dec00204 	addi	sp,sp,8
+ 8027b9c:	f800283a 	ret
+
+08027ba0 <tcp_wakeup>:
+ *
+ * RETURN: none
+ */
+void
+tcp_wakeup(void *event)
+{
+ 8027ba0:	defffc04 	addi	sp,sp,-16
+ 8027ba4:	dfc00315 	stw	ra,12(sp)
+ 8027ba8:	df000215 	stw	fp,8(sp)
+ 8027bac:	df000204 	addi	fp,sp,8
+ 8027bb0:	e13ffe15 	stw	r4,-8(fp)
+   int i;
+
+   OSSchedLock();
+ 8027bb4:	80109080 	call	8010908 <OSSchedLock>
+
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 8027bb8:	e03fff15 	stw	zero,-4(fp)
+ 8027bbc:	00002406 	br	8027c50 <tcp_wakeup+0xb0>
+   {
+      if ((global_TCPwakeup_set[i].ctick != 0) &&
+ 8027bc0:	e0bfff17 	ldw	r2,-4(fp)
+ 8027bc4:	10c00324 	muli	r3,r2,12
+ 8027bc8:	008201b4 	movhi	r2,2054
+ 8027bcc:	1885883a 	add	r2,r3,r2
+ 8027bd0:	10b81f17 	ldw	r2,-8068(r2)
+ 8027bd4:	10001b26 	beq	r2,zero,8027c44 <tcp_wakeup+0xa4>
+          (global_TCPwakeup_set[i].soc_event == event))
+ 8027bd8:	e0bfff17 	ldw	r2,-4(fp)
+ 8027bdc:	10c00324 	muli	r3,r2,12
+ 8027be0:	008201b4 	movhi	r2,2054
+ 8027be4:	1885883a 	add	r2,r3,r2
+ 8027be8:	10b82017 	ldw	r2,-8064(r2)
+      if ((global_TCPwakeup_set[i].ctick != 0) &&
+ 8027bec:	e0fffe17 	ldw	r3,-8(fp)
+ 8027bf0:	1880141e 	bne	r3,r2,8027c44 <tcp_wakeup+0xa4>
+      {
+         /* signal the event */
+         OSSemPost(global_TCPwakeup_set[i].semaphore);
+ 8027bf4:	e0bfff17 	ldw	r2,-4(fp)
+ 8027bf8:	10c00324 	muli	r3,r2,12
+ 8027bfc:	008201b4 	movhi	r2,2054
+ 8027c00:	1885883a 	add	r2,r3,r2
+ 8027c04:	10b82117 	ldw	r2,-8060(r2)
+ 8027c08:	1009883a 	mov	r4,r2
+ 8027c0c:	8015d840 	call	8015d84 <OSSemPost>
+
+         /* clear the entry */
+         global_TCPwakeup_set[i].ctick = 0;
+ 8027c10:	e0bfff17 	ldw	r2,-4(fp)
+ 8027c14:	10c00324 	muli	r3,r2,12
+ 8027c18:	008201b4 	movhi	r2,2054
+ 8027c1c:	1885883a 	add	r2,r3,r2
+ 8027c20:	10381f15 	stw	zero,-8068(r2)
+         global_TCPwakeup_set[i].soc_event = NULL;
+ 8027c24:	e0bfff17 	ldw	r2,-4(fp)
+ 8027c28:	10c00324 	muli	r3,r2,12
+ 8027c2c:	008201b4 	movhi	r2,2054
+ 8027c30:	1885883a 	add	r2,r3,r2
+ 8027c34:	10382015 	stw	zero,-8064(r2)
+
+         tcp_wakeup_count++;
+ 8027c38:	d0a07917 	ldw	r2,-32284(gp)
+ 8027c3c:	10800044 	addi	r2,r2,1
+ 8027c40:	d0a07915 	stw	r2,-32284(gp)
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 8027c44:	e0bfff17 	ldw	r2,-4(fp)
+ 8027c48:	10800044 	addi	r2,r2,1
+ 8027c4c:	e0bfff15 	stw	r2,-4(fp)
+ 8027c50:	e0bfff17 	ldw	r2,-4(fp)
+ 8027c54:	10800510 	cmplti	r2,r2,20
+ 8027c58:	103fd91e 	bne	r2,zero,8027bc0 <tcp_wakeup+0x20>
+      }
+   }
+
+   OSSchedUnlock();
+ 8027c5c:	80109940 	call	8010994 <OSSchedUnlock>
+}
+ 8027c60:	0001883a 	nop
+ 8027c64:	e037883a 	mov	sp,fp
+ 8027c68:	dfc00117 	ldw	ra,4(sp)
+ 8027c6c:	df000017 	ldw	fp,0(sp)
+ 8027c70:	dec00204 	addi	sp,sp,8
+ 8027c74:	f800283a 	ret
+
+08027c78 <TK_OSTaskQuery>:
+
+
+
+u_char TK_OSTaskQuery(void)
+{
+ 8027c78:	deffe204 	addi	sp,sp,-120
+ 8027c7c:	dfc01d15 	stw	ra,116(sp)
+ 8027c80:	df001c15 	stw	fp,112(sp)
+ 8027c84:	df001c04 	addi	fp,sp,112
+   OS_TCB task_data;
+   INT8U err, task_prio;
+
+   err = OSTaskQuery(OS_PRIO_SELF, &task_data);
+ 8027c88:	e0bfe404 	addi	r2,fp,-112
+ 8027c8c:	100b883a 	mov	r5,r2
+ 8027c90:	01003fc4 	movi	r4,255
+ 8027c94:	80172200 	call	8017220 <OSTaskQuery>
+ 8027c98:	e0bfffc5 	stb	r2,-1(fp)
+
+   if (err == OS_NO_ERR)
+ 8027c9c:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8027ca0:	1000041e 	bne	r2,zero,8027cb4 <TK_OSTaskQuery+0x3c>
+   {
+      task_prio = task_data.OSTCBPrio;
+ 8027ca4:	e0bff083 	ldbu	r2,-62(fp)
+ 8027ca8:	e0bfff85 	stb	r2,-2(fp)
+      dprintf("ChronOS API call failure, unable to identify task!");
+      panic("TK_OSTaskQuery");
+      return 0;
+   }
+   
+   return task_prio;
+ 8027cac:	e0bfff83 	ldbu	r2,-2(fp)
+ 8027cb0:	00000706 	br	8027cd0 <TK_OSTaskQuery+0x58>
+      dprintf("ChronOS API call failure, unable to identify task!");
+ 8027cb4:	01020174 	movhi	r4,2053
+ 8027cb8:	2128cd04 	addi	r4,r4,-23756
+ 8027cbc:	8002c780 	call	8002c78 <printf>
+      panic("TK_OSTaskQuery");
+ 8027cc0:	01020174 	movhi	r4,2053
+ 8027cc4:	2128da04 	addi	r4,r4,-23704
+ 8027cc8:	80271780 	call	8027178 <panic>
+      return 0;
+ 8027ccc:	0005883a 	mov	r2,zero
+}
+ 8027cd0:	e037883a 	mov	sp,fp
+ 8027cd4:	dfc00117 	ldw	ra,4(sp)
+ 8027cd8:	df000017 	ldw	fp,0(sp)
+ 8027cdc:	dec00204 	addi	sp,sp,8
+ 8027ce0:	f800283a 	ret
+
+08027ce4 <tk_yield>:
+
+
+
+void
+tk_yield(void)
+{
+ 8027ce4:	defffe04 	addi	sp,sp,-8
+ 8027ce8:	dfc00115 	stw	ra,4(sp)
+ 8027cec:	df000015 	stw	fp,0(sp)
+ 8027cf0:	d839883a 	mov	fp,sp
+   /* To ensure cycles to the lower priority tasks we should really
+    * delay by two ticks, but that really hurts performance on some
+    * long-tick targets. One tick works better overall....
+    */
+   OSTimeDly(1);
+ 8027cf4:	01000044 	movi	r4,1
+ 8027cf8:	801730c0 	call	801730c <OSTimeDly>
+}
+ 8027cfc:	0001883a 	nop
+ 8027d00:	e037883a 	mov	sp,fp
+ 8027d04:	dfc00117 	ldw	ra,4(sp)
+ 8027d08:	df000017 	ldw	fp,0(sp)
+ 8027d0c:	dec00204 	addi	sp,sp,8
+ 8027d10:	f800283a 	ret
+
+08027d14 <tk_stats>:
+extern struct inet_taskinfo * nettask;
+extern int num_net_tasks;
+
+int
+tk_stats(void * pio)
+{
+ 8027d14:	deffef04 	addi	sp,sp,-68
+ 8027d18:	dfc01015 	stw	ra,64(sp)
+ 8027d1c:	df000f15 	stw	fp,60(sp)
+ 8027d20:	df000f04 	addi	fp,sp,60
+ 8027d24:	e13ff215 	stw	r4,-56(fp)
+   int      stackuse;
+   char     name[OS_TASK_NAME_SIZE+1];
+   INT8U    err;
+   
+
+   ns_printf(pio, "ChronOS RTOS stats:\n");
+ 8027d28:	01420174 	movhi	r5,2053
+ 8027d2c:	2968de04 	addi	r5,r5,-23688
+ 8027d30:	e13ff217 	ldw	r4,-56(fp)
+ 8027d34:	80273900 	call	8027390 <ns_printf>
+
+#ifdef NO_INICHE_EXTENSIONS
+   ns_printf(pio, "Context switches; Delay:  %lu\n",
+ 8027d38:	d0a04f17 	ldw	r2,-32452(gp)
+ 8027d3c:	100d883a 	mov	r6,r2
+ 8027d40:	01420174 	movhi	r5,2053
+ 8027d44:	2968e404 	addi	r5,r5,-23664
+ 8027d48:	e13ff217 	ldw	r4,-56(fp)
+ 8027d4c:	80273900 	call	8027390 <ns_printf>
+#else
+   ns_printf(pio, "Context switches; Delay:  %lu, Interrupt: %lu\n",
+      OSCtxSwCtr, OSCtxIntCtr);
+#endif
+
+   ns_printf(pio, "       name     prio. state    wakeups stack-size stack-use \n");
+ 8027d50:	01420174 	movhi	r5,2053
+ 8027d54:	2968ec04 	addi	r5,r5,-23632
+ 8027d58:	e13ff217 	ldw	r4,-56(fp)
+ 8027d5c:	80273900 	call	8027390 <ns_printf>
+
+   
+   for (t = 0; t <= OS_LOWEST_PRIO ; t++)
+ 8027d60:	e03fff15 	stw	zero,-4(fp)
+ 8027d64:	00005006 	br	8027ea8 <tk_stats+0x194>
+   {
+      /* get pointer to TCB and see if entry is in use and not a mutex */
+      tcb = OSTCBPrioTbl[t];
+ 8027d68:	e0bfff17 	ldw	r2,-4(fp)
+ 8027d6c:	100690ba 	slli	r3,r2,2
+ 8027d70:	008201b4 	movhi	r2,2054
+ 8027d74:	1885883a 	add	r2,r3,r2
+ 8027d78:	10b55d17 	ldw	r2,-10892(r2)
+ 8027d7c:	e0bffd15 	stw	r2,-12(fp)
+      if ((tcb == NULL) || (tcb == (OS_TCB *)1))
+ 8027d80:	e0bffd17 	ldw	r2,-12(fp)
+ 8027d84:	10004426 	beq	r2,zero,8027e98 <tk_stats+0x184>
+ 8027d88:	e0bffd17 	ldw	r2,-12(fp)
+ 8027d8c:	10800058 	cmpnei	r2,r2,1
+ 8027d90:	10004126 	beq	r2,zero,8027e98 <tk_stats+0x184>
+         continue;
+
+      OSTaskNameGet(tcb->OSTCBPrio, (INT8U *)&name, &err);
+ 8027d94:	e0bffd17 	ldw	r2,-12(fp)
+ 8027d98:	10800c83 	ldbu	r2,50(r2)
+ 8027d9c:	10803fcc 	andi	r2,r2,255
+ 8027da0:	e13ff384 	addi	r4,fp,-50
+ 8027da4:	e0fff3c4 	addi	r3,fp,-49
+ 8027da8:	200d883a 	mov	r6,r4
+ 8027dac:	180b883a 	mov	r5,r3
+ 8027db0:	1009883a 	mov	r4,r2
+ 8027db4:	8016c2c0 	call	8016c2c <OSTaskNameGet>
+
+#ifdef NO_INICHE_EXTENSIONS
+      ns_printf(pio, "%15s %2d    0x%04x,    ---   ",
+                     name, tcb->OSTCBPrio, tcb->OSTCBStat);
+ 8027db8:	e0bffd17 	ldw	r2,-12(fp)
+ 8027dbc:	10800c83 	ldbu	r2,50(r2)
+      ns_printf(pio, "%15s %2d    0x%04x,    ---   ",
+ 8027dc0:	11003fcc 	andi	r4,r2,255
+                     name, tcb->OSTCBPrio, tcb->OSTCBStat);
+ 8027dc4:	e0bffd17 	ldw	r2,-12(fp)
+ 8027dc8:	10800c03 	ldbu	r2,48(r2)
+      ns_printf(pio, "%15s %2d    0x%04x,    ---   ",
+ 8027dcc:	10803fcc 	andi	r2,r2,255
+ 8027dd0:	e0fff3c4 	addi	r3,fp,-49
+ 8027dd4:	d8800015 	stw	r2,0(sp)
+ 8027dd8:	200f883a 	mov	r7,r4
+ 8027ddc:	180d883a 	mov	r6,r3
+ 8027de0:	01420174 	movhi	r5,2053
+ 8027de4:	2968fc04 	addi	r5,r5,-23568
+ 8027de8:	e13ff217 	ldw	r4,-56(fp)
+ 8027dec:	80273900 	call	8027390 <ns_printf>
+      /* Find lowest non-zero value in stack so we can estimate the
+       * unused portion. Subtracting this from size gives us the used
+       * portion of the stack.
+       */
+#if OS_TASK_CREATE_EXT_EN > 0
+      if(tcb->OSTCBStkBottom && tcb->OSTCBStkSize)
+ 8027df0:	e0bffd17 	ldw	r2,-12(fp)
+ 8027df4:	10800217 	ldw	r2,8(r2)
+ 8027df8:	10002226 	beq	r2,zero,8027e84 <tk_stats+0x170>
+ 8027dfc:	e0bffd17 	ldw	r2,-12(fp)
+ 8027e00:	10800317 	ldw	r2,12(r2)
+ 8027e04:	10001f26 	beq	r2,zero,8027e84 <tk_stats+0x170>
+      {
+         sp = tcb->OSTCBStkBottom + 1;
+ 8027e08:	e0bffd17 	ldw	r2,-12(fp)
+ 8027e0c:	10800217 	ldw	r2,8(r2)
+ 8027e10:	10800104 	addi	r2,r2,4
+ 8027e14:	e0bffe15 	stw	r2,-8(fp)
+         while(*sp == 0)
+ 8027e18:	00000306 	br	8027e28 <tk_stats+0x114>
+            sp++;
+ 8027e1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8027e20:	10800104 	addi	r2,r2,4
+ 8027e24:	e0bffe15 	stw	r2,-8(fp)
+         while(*sp == 0)
+ 8027e28:	e0bffe17 	ldw	r2,-8(fp)
+ 8027e2c:	10800017 	ldw	r2,0(r2)
+ 8027e30:	103ffa26 	beq	r2,zero,8027e1c <tk_stats+0x108>
+         /* This OS traditionally keeps the size in OS_STK (int) units rather
+          * than bytes, so convert back to bytes for display.
+          */
+         stackuse = (tcb->OSTCBStkSize - (sp - tcb->OSTCBStkBottom)) * sizeof(OS_STK);
+ 8027e34:	e0bffd17 	ldw	r2,-12(fp)
+ 8027e38:	10800317 	ldw	r2,12(r2)
+ 8027e3c:	e0fffd17 	ldw	r3,-12(fp)
+ 8027e40:	18c00217 	ldw	r3,8(r3)
+ 8027e44:	e13ffe17 	ldw	r4,-8(fp)
+ 8027e48:	20c7c83a 	sub	r3,r4,r3
+ 8027e4c:	1807d0ba 	srai	r3,r3,2
+ 8027e50:	10c5c83a 	sub	r2,r2,r3
+ 8027e54:	100490ba 	slli	r2,r2,2
+ 8027e58:	e0bffc15 	stw	r2,-16(fp)
+         ns_printf(pio, "%6d,      %6d\n",
+            tcb->OSTCBStkSize * sizeof(OS_STK),  stackuse);
+ 8027e5c:	e0bffd17 	ldw	r2,-12(fp)
+ 8027e60:	10800317 	ldw	r2,12(r2)
+         ns_printf(pio, "%6d,      %6d\n",
+ 8027e64:	100490ba 	slli	r2,r2,2
+ 8027e68:	e1fffc17 	ldw	r7,-16(fp)
+ 8027e6c:	100d883a 	mov	r6,r2
+ 8027e70:	01420174 	movhi	r5,2053
+ 8027e74:	29690404 	addi	r5,r5,-23536
+ 8027e78:	e13ff217 	ldw	r4,-56(fp)
+ 8027e7c:	80273900 	call	8027390 <ns_printf>
+ 8027e80:	00000606 	br	8027e9c <tk_stats+0x188>
+      }
+      else
+#endif
+      {
+         ns_printf(pio, "No stack data\n");
+ 8027e84:	01420174 	movhi	r5,2053
+ 8027e88:	29690804 	addi	r5,r5,-23520
+ 8027e8c:	e13ff217 	ldw	r4,-56(fp)
+ 8027e90:	80273900 	call	8027390 <ns_printf>
+ 8027e94:	00000106 	br	8027e9c <tk_stats+0x188>
+         continue;
+ 8027e98:	0001883a 	nop
+   for (t = 0; t <= OS_LOWEST_PRIO ; t++)
+ 8027e9c:	e0bfff17 	ldw	r2,-4(fp)
+ 8027ea0:	10800044 	addi	r2,r2,1
+ 8027ea4:	e0bfff15 	stw	r2,-4(fp)
+ 8027ea8:	e0bfff17 	ldw	r2,-4(fp)
+ 8027eac:	10800550 	cmplti	r2,r2,21
+ 8027eb0:	103fad1e 	bne	r2,zero,8027d68 <tk_stats+0x54>
+      }
+   }
+
+   ns_printf(pio, "tcp_sleep_count = %lu, tcp_wakeup_count = %lu\n",
+ 8027eb4:	d0a07817 	ldw	r2,-32288(gp)
+ 8027eb8:	d0e07917 	ldw	r3,-32284(gp)
+ 8027ebc:	180f883a 	mov	r7,r3
+ 8027ec0:	100d883a 	mov	r6,r2
+ 8027ec4:	01420174 	movhi	r5,2053
+ 8027ec8:	29690c04 	addi	r5,r5,-23504
+ 8027ecc:	e13ff217 	ldw	r4,-56(fp)
+ 8027ed0:	80273900 	call	8027390 <ns_printf>
+                  tcp_sleep_count, tcp_wakeup_count);
+   ns_printf(pio, "global_TCPwakeup_setIndx = %d, tcp_sleep_timeout = %lu\n",
+ 8027ed4:	d0a07c17 	ldw	r2,-32272(gp)
+ 8027ed8:	d0e07117 	ldw	r3,-32316(gp)
+ 8027edc:	180f883a 	mov	r7,r3
+ 8027ee0:	100d883a 	mov	r6,r2
+ 8027ee4:	01420174 	movhi	r5,2053
+ 8027ee8:	29691804 	addi	r5,r5,-23456
+ 8027eec:	e13ff217 	ldw	r4,-56(fp)
+ 8027ef0:	80273900 	call	8027390 <ns_printf>
+                  global_TCPwakeup_setIndx, tcp_sleep_timeout);
+
+   return 0;
+ 8027ef4:	0005883a 	mov	r2,zero
+}
+ 8027ef8:	e037883a 	mov	sp,fp
+ 8027efc:	dfc00117 	ldw	ra,4(sp)
+ 8027f00:	df000017 	ldw	fp,0(sp)
+ 8027f04:	dec00204 	addi	sp,sp,8
+ 8027f08:	f800283a 	ret
+
+08027f0c <icmpEcho>:
+int
+icmpEcho(ip_addr host,  /* host to ping - 32 bit, network-endian */
+   char *   data,       /* ping data, NULL if don't care */
+   unsigned datalen,     /* length of data to attach to ping request */
+   unshort  pingseq)    /* ping sequence number */
+{
+ 8027f0c:	defff504 	addi	sp,sp,-44
+ 8027f10:	dfc00a15 	stw	ra,40(sp)
+ 8027f14:	df000915 	stw	fp,36(sp)
+ 8027f18:	df000904 	addi	fp,sp,36
+ 8027f1c:	e13ffa15 	stw	r4,-24(fp)
+ 8027f20:	e17ff915 	stw	r5,-28(fp)
+ 8027f24:	e1bff815 	stw	r6,-32(fp)
+ 8027f28:	3805883a 	mov	r2,r7
+ 8027f2c:	e0bff70d 	sth	r2,-36(fp)
+   PACKET   p;
+   int      ip_err;
+   struct ping *  e;
+   struct ip *    pip;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8027f30:	01000084 	movi	r4,2
+ 8027f34:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   p = pk_alloc(PINGHDRSLEN + datalen);
+ 8027f38:	e0bff817 	ldw	r2,-32(fp)
+ 8027f3c:	10800b04 	addi	r2,r2,44
+ 8027f40:	1009883a 	mov	r4,r2
+ 8027f44:	80284340 	call	8028434 <pk_alloc>
+ 8027f48:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8027f4c:	01000084 	movi	r4,2
+ 8027f50:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (!p)
+ 8027f54:	e0bffe17 	ldw	r2,-8(fp)
+ 8027f58:	1000081e 	bne	r2,zero,8027f7c <icmpEcho+0x70>
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & IPTRACE)
+ 8027f5c:	d0a06617 	ldw	r2,-32360(gp)
+ 8027f60:	1080800c 	andi	r2,r2,512
+ 8027f64:	10000326 	beq	r2,zero,8027f74 <icmpEcho+0x68>
+         dprintf("icmp: can't alloc packet\n");
+ 8027f68:	01020174 	movhi	r4,2053
+ 8027f6c:	21292d04 	addi	r4,r4,-23372
+ 8027f70:	8002d9c0 	call	8002d9c <puts>
+#endif
+      return(ENP_NOBUFFER);
+ 8027f74:	00bffac4 	movi	r2,-21
+ 8027f78:	00008606 	br	8028194 <icmpEcho+0x288>
+   }
+
+   p->nb_prot = p->nb_buff + PINGHDRSLEN;
+ 8027f7c:	e0bffe17 	ldw	r2,-8(fp)
+ 8027f80:	10800117 	ldw	r2,4(r2)
+ 8027f84:	10c00b04 	addi	r3,r2,44
+ 8027f88:	e0bffe17 	ldw	r2,-8(fp)
+ 8027f8c:	10c00315 	stw	r3,12(r2)
+   p->nb_plen = datalen;
+ 8027f90:	e0bffe17 	ldw	r2,-8(fp)
+ 8027f94:	e0fff817 	ldw	r3,-32(fp)
+ 8027f98:	10c00415 	stw	r3,16(r2)
+   p->fhost = host;
+ 8027f9c:	e0bffe17 	ldw	r2,-8(fp)
+ 8027fa0:	e0fffa17 	ldw	r3,-24(fp)
+ 8027fa4:	10c00715 	stw	r3,28(r2)
+
+   if(host == 0xFFFFFFFF)  /* broadcast? */
+ 8027fa8:	e0bffa17 	ldw	r2,-24(fp)
+ 8027fac:	10bfffd8 	cmpnei	r2,r2,-1
+ 8027fb0:	1000041e 	bne	r2,zero,8027fc4 <icmpEcho+0xb8>
+      p->net = nets[0];    /* then use first iface */
+ 8027fb4:	008201b4 	movhi	r2,2054
+ 8027fb8:	10f77017 	ldw	r3,-8768(r2)
+ 8027fbc:	e0bffe17 	ldw	r2,-8(fp)
+ 8027fc0:	10c00615 	stw	r3,24(r2)
+
+   /* copy in data field */
+   if (data)
+ 8027fc4:	e0bff917 	ldw	r2,-28(fp)
+ 8027fc8:	10000726 	beq	r2,zero,8027fe8 <icmpEcho+0xdc>
+   {
+      MEMCPY(p->nb_prot, data, datalen);
+ 8027fcc:	e0bffe17 	ldw	r2,-8(fp)
+ 8027fd0:	10800317 	ldw	r2,12(r2)
+ 8027fd4:	e1bff817 	ldw	r6,-32(fp)
+ 8027fd8:	e17ff917 	ldw	r5,-28(fp)
+ 8027fdc:	1009883a 	mov	r4,r2
+ 8027fe0:	80086b80 	call	80086b8 <memcpy>
+ 8027fe4:	00001706 	br	8028044 <icmpEcho+0x138>
+   }
+   else  /* caller didn't specify data */
+   {
+      unsigned   donedata;
+      strcpy(p->nb_prot, pingdata);
+ 8027fe8:	e0bffe17 	ldw	r2,-8(fp)
+ 8027fec:	10800317 	ldw	r2,12(r2)
+ 8027ff0:	d0e01517 	ldw	r3,-32684(gp)
+ 8027ff4:	180b883a 	mov	r5,r3
+ 8027ff8:	1009883a 	mov	r4,r2
+ 8027ffc:	8042f600 	call	8042f60 <strcpy>
+      donedata = (unsigned)strlen(pingdata);
+ 8028000:	d0a01517 	ldw	r2,-32684(gp)
+ 8028004:	1009883a 	mov	r4,r2
+ 8028008:	8002dac0 	call	8002dac <strlen>
+ 802800c:	e0bfff15 	stw	r2,-4(fp)
+      while (donedata < datalen)
+ 8028010:	00000906 	br	8028038 <icmpEcho+0x12c>
+      {
+         *(p->nb_prot + donedata) = (char)((donedata) & 0x00FF);
+ 8028014:	e0bffe17 	ldw	r2,-8(fp)
+ 8028018:	10c00317 	ldw	r3,12(r2)
+ 802801c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028020:	1885883a 	add	r2,r3,r2
+ 8028024:	e0ffff17 	ldw	r3,-4(fp)
+ 8028028:	10c00005 	stb	r3,0(r2)
+         donedata++;
+ 802802c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028030:	10800044 	addi	r2,r2,1
+ 8028034:	e0bfff15 	stw	r2,-4(fp)
+      while (donedata < datalen)
+ 8028038:	e0ffff17 	ldw	r3,-4(fp)
+ 802803c:	e0bff817 	ldw	r2,-32(fp)
+ 8028040:	18bff436 	bltu	r3,r2,8028014 <icmpEcho+0x108>
+      }
+   }
+
+   /* adjust packet pointers to icmp ping header */
+   p->nb_prot -= sizeof(struct ping);
+ 8028044:	e0bffe17 	ldw	r2,-8(fp)
+ 8028048:	10800317 	ldw	r2,12(r2)
+ 802804c:	10fffe04 	addi	r3,r2,-8
+ 8028050:	e0bffe17 	ldw	r2,-8(fp)
+ 8028054:	10c00315 	stw	r3,12(r2)
+   p->nb_plen += sizeof(struct ping);
+ 8028058:	e0bffe17 	ldw	r2,-8(fp)
+ 802805c:	10800417 	ldw	r2,16(r2)
+ 8028060:	10c00204 	addi	r3,r2,8
+ 8028064:	e0bffe17 	ldw	r2,-8(fp)
+ 8028068:	10c00415 	stw	r3,16(r2)
+
+   /* fill in icmp ping header */
+   e = (struct ping *)p->nb_prot;
+ 802806c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028070:	10800317 	ldw	r2,12(r2)
+ 8028074:	e0bffd15 	stw	r2,-12(fp)
+   e->ptype = ECHOREQ;
+ 8028078:	e0bffd17 	ldw	r2,-12(fp)
+ 802807c:	00c00204 	movi	r3,8
+ 8028080:	10c00005 	stb	r3,0(r2)
+   e->pcode = 0;
+ 8028084:	e0bffd17 	ldw	r2,-12(fp)
+ 8028088:	10000045 	stb	zero,1(r2)
+   e->pid = 0;
+ 802808c:	e0bffd17 	ldw	r2,-12(fp)
+ 8028090:	1000010d 	sth	zero,4(r2)
+   e->pseq = pingseq;
+ 8028094:	e0bffd17 	ldw	r2,-12(fp)
+ 8028098:	e0fff70b 	ldhu	r3,-36(fp)
+ 802809c:	10c0018d 	sth	r3,6(r2)
+
+   /* Calculate the checksum */
+   e->pchksum = 0;
+ 80280a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80280a4:	1000008d 	sth	zero,2(r2)
+   if (datalen & 1)  /* if data size is odd, pad with a zero */
+ 80280a8:	e0bff817 	ldw	r2,-32(fp)
+ 80280ac:	1080004c 	andi	r2,r2,1
+ 80280b0:	10000526 	beq	r2,zero,80280c8 <icmpEcho+0x1bc>
+      *((char*)(e+1) + datalen) = 0;
+ 80280b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80280b8:	10c00204 	addi	r3,r2,8
+ 80280bc:	e0bff817 	ldw	r2,-32(fp)
+ 80280c0:	1885883a 	add	r2,r3,r2
+ 80280c4:	10000005 	stb	zero,0(r2)
+
+   e->pchksum = ~cksum(e, (ICMPSIZE+datalen+1)>>1);
+ 80280c8:	e0bff817 	ldw	r2,-32(fp)
+ 80280cc:	10800244 	addi	r2,r2,9
+ 80280d0:	1004d07a 	srli	r2,r2,1
+ 80280d4:	100b883a 	mov	r5,r2
+ 80280d8:	e13ffd17 	ldw	r4,-12(fp)
+ 80280dc:	8026d7c0 	call	8026d7c <cksum>
+ 80280e0:	0084303a 	nor	r2,zero,r2
+ 80280e4:	1007883a 	mov	r3,r2
+ 80280e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80280ec:	10c0008d 	sth	r3,2(r2)
+
+   /* need to fill in IP addresses at this layer too */
+   pip = (struct ip *)(p->nb_prot - sizeof(struct ip));
+ 80280f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80280f4:	10800317 	ldw	r2,12(r2)
+ 80280f8:	10bffb04 	addi	r2,r2,-20
+ 80280fc:	e0bffc15 	stw	r2,-16(fp)
+   pip->ip_src = ip_mymach(host);
+ 8028100:	e13ffa17 	ldw	r4,-24(fp)
+ 8028104:	803b0280 	call	803b028 <ip_mymach>
+ 8028108:	1007883a 	mov	r3,r2
+ 802810c:	e0bffc17 	ldw	r2,-16(fp)
+ 8028110:	10c00315 	stw	r3,12(r2)
+   pip->ip_dest = host;
+ 8028114:	e0bffc17 	ldw	r2,-16(fp)
+ 8028118:	e0fffa17 	ldw	r3,-24(fp)
+ 802811c:	10c00415 	stw	r3,16(r2)
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 8028120:	0009883a 	mov	r4,zero
+ 8028124:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   ip_err = ip_write(ICMP_PROT, p);    /* send down to IP layer */
+ 8028128:	e17ffe17 	ldw	r5,-8(fp)
+ 802812c:	01000044 	movi	r4,1
+ 8028130:	803a9e80 	call	803a9e8 <ip_write>
+ 8028134:	e0bffb15 	stw	r2,-20(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 8028138:	0009883a 	mov	r4,zero
+ 802813c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   /* Errors are negative. A zero means send was OK. a positive number
+    * usually means we had to ARP. Assume this will work and count a send.
+    */
+   if(ip_err < 0)
+ 8028140:	e0bffb17 	ldw	r2,-20(fp)
+ 8028144:	1000080e 	bge	r2,zero,8028168 <icmpEcho+0x25c>
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & NETERR)
+ 8028148:	d0a06617 	ldw	r2,-32360(gp)
+ 802814c:	1080020c 	andi	r2,r2,8
+ 8028150:	10000326 	beq	r2,zero,8028160 <icmpEcho+0x254>
+         dprintf("icmp: can't send echo request\n");
+ 8028154:	01020174 	movhi	r4,2053
+ 8028158:	21293404 	addi	r4,r4,-23344
+ 802815c:	8002d9c0 	call	8002d9c <puts>
+#endif
+      /* rfc 1156 seems to say not to count these. (pg 48) -JB- */
+      /* LOCK_NET_RESOURCE(FREEQ_RESID); */
+      /* pk_free(p); */
+      /* UNLOCK_NET_RESOURCE(FREEQ_RESID); */
+      return(ip_err);
+ 8028160:	e0bffb17 	ldw	r2,-20(fp)
+ 8028164:	00000b06 	br	8028194 <icmpEcho+0x288>
+   }
+   /* fall to here if we sent echo request OK */
+   icmp_mib.icmpOutMsgs++;
+ 8028168:	008201b4 	movhi	r2,2054
+ 802816c:	10b94217 	ldw	r2,-6904(r2)
+ 8028170:	10c00044 	addi	r3,r2,1
+ 8028174:	008201b4 	movhi	r2,2054
+ 8028178:	10f94215 	stw	r3,-6904(r2)
+   icmp_mib.icmpOutEchos++;
+ 802817c:	008201b4 	movhi	r2,2054
+ 8028180:	10b94917 	ldw	r2,-6876(r2)
+ 8028184:	10c00044 	addi	r3,r2,1
+ 8028188:	008201b4 	movhi	r2,2054
+ 802818c:	10f94915 	stw	r3,-6876(r2)
+
+   return(0);
+ 8028190:	0005883a 	mov	r2,zero
+}
+ 8028194:	e037883a 	mov	sp,fp
+ 8028198:	dfc00117 	ldw	ra,4(sp)
+ 802819c:	df000017 	ldw	fp,0(sp)
+ 80281a0:	dec00204 	addi	sp,sp,8
+ 80281a4:	f800283a 	ret
+
+080281a8 <pk_init>:
+ * for a PACKET buffer or a data buffer fails, or if there is an inconsistency
+ * between (bigbufs + lilbufs) and MAXPACKETS) it returns -1. 
+ */
+
+int pk_init (void)
+{
+ 80281a8:	defff804 	addi	sp,sp,-32
+ 80281ac:	dfc00715 	stw	ra,28(sp)
+ 80281b0:	df000615 	stw	fp,24(sp)
+ 80281b4:	df000604 	addi	fp,sp,24
+   PACKET packet;
+   unsigned i;
+   unsigned numpkts = bigbufs + lilbufs;
+ 80281b8:	d0e01817 	ldw	r3,-32672(gp)
+ 80281bc:	d0a01617 	ldw	r2,-32680(gp)
+ 80281c0:	1885883a 	add	r2,r3,r2
+ 80281c4:	e0bffc15 	stw	r2,-16(fp)
+   u_char align_req;
+   
+#ifdef ALIGN_BUFS
+   align_req = ALIGN_BUFS;
+#else
+   align_req = 0;
+ 80281c8:	e03ffbc5 	stb	zero,-17(fp)
+#endif
+
+   for (i = 0; i < numpkts; i++)
+ 80281cc:	e03fff15 	stw	zero,-4(fp)
+ 80281d0:	00007806 	br	80283b4 <pk_init+0x20c>
+   {
+      packet = (PACKET)NB_ALLOC(sizeof(struct netbuf));
+ 80281d4:	01000d04 	movi	r4,52
+ 80281d8:	802982c0 	call	802982c <npalloc>
+ 80281dc:	e0bffa15 	stw	r2,-24(fp)
+      if (packet == NULL)
+ 80281e0:	e0bffa17 	ldw	r2,-24(fp)
+ 80281e4:	10008026 	beq	r2,zero,80283e8 <pk_init+0x240>
+         goto no_pkt_buf;
+
+#ifdef NPDEBUG
+      if (i >= MAXPACKETS)
+ 80281e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80281ec:	10800f30 	cmpltui	r2,r2,60
+ 80281f0:	1000051e 	bne	r2,zero,8028208 <pk_init+0x60>
+      {
+         dprintf("pk_init: bad define\n");
+ 80281f4:	01020174 	movhi	r4,2053
+ 80281f8:	21293c04 	addi	r4,r4,-23312
+ 80281fc:	8002d9c0 	call	8002d9c <puts>
+         return -1;
+ 8028200:	00bfffc4 	movi	r2,-1
+ 8028204:	00008606 	br	8028420 <pk_init+0x278>
+      }
+      pktlog[i] = packet;     /* save for debugging */
+ 8028208:	e0bfff17 	ldw	r2,-4(fp)
+ 802820c:	100890ba 	slli	r4,r2,2
+ 8028210:	e0fffa17 	ldw	r3,-24(fp)
+ 8028214:	008201b4 	movhi	r2,2054
+ 8028218:	2085883a 	add	r2,r4,r2
+ 802821c:	10f79f15 	stw	r3,-8580(r2)
+#endif
+
+      packet->nb_tstamp = 0L;
+ 8028220:	e0bffa17 	ldw	r2,-24(fp)
+ 8028224:	10000515 	stw	zero,20(r2)
+
+      if (i < bigbufs)
+ 8028228:	d0a01817 	ldw	r2,-32672(gp)
+ 802822c:	e0ffff17 	ldw	r3,-4(fp)
+ 8028230:	18802f2e 	bgeu	r3,r2,80282f0 <pk_init+0x148>
+#ifdef NPDEBUG
+         {
+            int j;
+
+            /* for DEBUG compiles, bracket the data area with special chars */
+            packet->nb_buff = (char *)BB_ALLOC(bigbufsiz+ALIGN_TYPE+1);
+ 8028234:	d0a01917 	ldw	r2,-32668(gp)
+ 8028238:	10800144 	addi	r2,r2,5
+ 802823c:	1009883a 	mov	r4,r2
+ 8028240:	80298a00 	call	80298a0 <ncpalloc>
+ 8028244:	1007883a 	mov	r3,r2
+ 8028248:	e0bffa17 	ldw	r2,-24(fp)
+ 802824c:	10c00115 	stw	r3,4(r2)
+            if (!(packet->nb_buff))
+ 8028250:	e0bffa17 	ldw	r2,-24(fp)
+ 8028254:	10800117 	ldw	r2,4(r2)
+ 8028258:	10006526 	beq	r2,zero,80283f0 <pk_init+0x248>
+               goto no_pkt_buf;
+
+            /* Add memory markers for sanity check */
+            for(j = 0; j < ALIGN_TYPE; j++)
+ 802825c:	e03ffe15 	stw	zero,-8(fp)
+ 8028260:	00000906 	br	8028288 <pk_init+0xe0>
+               *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */
+ 8028264:	e0bffa17 	ldw	r2,-24(fp)
+ 8028268:	10c00117 	ldw	r3,4(r2)
+ 802826c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028270:	1885883a 	add	r2,r3,r2
+ 8028274:	00c01344 	movi	r3,77
+ 8028278:	10c00005 	stb	r3,0(r2)
+            for(j = 0; j < ALIGN_TYPE; j++)
+ 802827c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028280:	10800044 	addi	r2,r2,1
+ 8028284:	e0bffe15 	stw	r2,-8(fp)
+ 8028288:	e0bffe17 	ldw	r2,-8(fp)
+ 802828c:	10800110 	cmplti	r2,r2,4
+ 8028290:	103ff41e 	bne	r2,zero,8028264 <pk_init+0xbc>
+
+            *(packet->nb_buff + bigbufsiz + ALIGN_TYPE) = 'M';
+ 8028294:	e0bffa17 	ldw	r2,-24(fp)
+ 8028298:	10c00117 	ldw	r3,4(r2)
+ 802829c:	d0a01917 	ldw	r2,-32668(gp)
+ 80282a0:	10800104 	addi	r2,r2,4
+ 80282a4:	1885883a 	add	r2,r3,r2
+ 80282a8:	00c01344 	movi	r3,77
+ 80282ac:	10c00005 	stb	r3,0(r2)
+            packet->nb_buff += ALIGN_TYPE;   /* bump buf past MMs */
+ 80282b0:	e0bffa17 	ldw	r2,-24(fp)
+ 80282b4:	10800117 	ldw	r2,4(r2)
+ 80282b8:	10c00104 	addi	r3,r2,4
+ 80282bc:	e0bffa17 	ldw	r2,-24(fp)
+ 80282c0:	10c00115 	stw	r3,4(r2)
+#ifdef ALIGN_BUFS
+         /* align start of buffer pointer to desired offset */
+         packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1)));
+#endif
+#endif
+         if (!(packet->nb_buff))
+ 80282c4:	e0bffa17 	ldw	r2,-24(fp)
+ 80282c8:	10800117 	ldw	r2,4(r2)
+ 80282cc:	10004a26 	beq	r2,zero,80283f8 <pk_init+0x250>
+            goto no_pkt_buf;
+         packet->nb_blen = bigbufsiz;
+ 80282d0:	d0e01917 	ldw	r3,-32668(gp)
+ 80282d4:	e0bffa17 	ldw	r2,-24(fp)
+ 80282d8:	10c00215 	stw	r3,8(r2)
+         q_add(&bigfreeq, packet);        /* save it in big pkt free queue */
+ 80282dc:	e17ffa17 	ldw	r5,-24(fp)
+ 80282e0:	010201b4 	movhi	r4,2054
+ 80282e4:	2137db04 	addi	r4,r4,-8340
+ 80282e8:	80289900 	call	8028990 <putq>
+ 80282ec:	00002e06 	br	80283a8 <pk_init+0x200>
+#ifdef NPDEBUG
+         {
+            int j;
+
+            /* for DEBUG compiles, bracket the data area with special chars */
+            packet->nb_buff = (char *)LB_ALLOC(lilbufsiz+ALIGN_TYPE+1);
+ 80282f0:	d0a01717 	ldw	r2,-32676(gp)
+ 80282f4:	10800144 	addi	r2,r2,5
+ 80282f8:	1009883a 	mov	r4,r2
+ 80282fc:	80298a00 	call	80298a0 <ncpalloc>
+ 8028300:	1007883a 	mov	r3,r2
+ 8028304:	e0bffa17 	ldw	r2,-24(fp)
+ 8028308:	10c00115 	stw	r3,4(r2)
+            if (!(packet->nb_buff))
+ 802830c:	e0bffa17 	ldw	r2,-24(fp)
+ 8028310:	10800117 	ldw	r2,4(r2)
+ 8028314:	10003a26 	beq	r2,zero,8028400 <pk_init+0x258>
+               goto no_pkt_buf;
+
+            /* Add memory markers for sanity check */
+            for(j = 0; j < ALIGN_TYPE; j++)
+ 8028318:	e03ffd15 	stw	zero,-12(fp)
+ 802831c:	00000906 	br	8028344 <pk_init+0x19c>
+               *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */
+ 8028320:	e0bffa17 	ldw	r2,-24(fp)
+ 8028324:	10c00117 	ldw	r3,4(r2)
+ 8028328:	e0bffd17 	ldw	r2,-12(fp)
+ 802832c:	1885883a 	add	r2,r3,r2
+ 8028330:	00c01344 	movi	r3,77
+ 8028334:	10c00005 	stb	r3,0(r2)
+            for(j = 0; j < ALIGN_TYPE; j++)
+ 8028338:	e0bffd17 	ldw	r2,-12(fp)
+ 802833c:	10800044 	addi	r2,r2,1
+ 8028340:	e0bffd15 	stw	r2,-12(fp)
+ 8028344:	e0bffd17 	ldw	r2,-12(fp)
+ 8028348:	10800110 	cmplti	r2,r2,4
+ 802834c:	103ff41e 	bne	r2,zero,8028320 <pk_init+0x178>
+
+            *(packet->nb_buff + lilbufsiz + ALIGN_TYPE) = 'M';
+ 8028350:	e0bffa17 	ldw	r2,-24(fp)
+ 8028354:	10c00117 	ldw	r3,4(r2)
+ 8028358:	d0a01717 	ldw	r2,-32676(gp)
+ 802835c:	10800104 	addi	r2,r2,4
+ 8028360:	1885883a 	add	r2,r3,r2
+ 8028364:	00c01344 	movi	r3,77
+ 8028368:	10c00005 	stb	r3,0(r2)
+            packet->nb_buff += ALIGN_TYPE;
+ 802836c:	e0bffa17 	ldw	r2,-24(fp)
+ 8028370:	10800117 	ldw	r2,4(r2)
+ 8028374:	10c00104 	addi	r3,r2,4
+ 8028378:	e0bffa17 	ldw	r2,-24(fp)
+ 802837c:	10c00115 	stw	r3,4(r2)
+#ifdef ALIGN_BUFS
+         /* align start of buffer pointer to desired offset */
+         packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1)));
+#endif
+#endif
+         if (!(packet->nb_buff))
+ 8028380:	e0bffa17 	ldw	r2,-24(fp)
+ 8028384:	10800117 	ldw	r2,4(r2)
+ 8028388:	10001f26 	beq	r2,zero,8028408 <pk_init+0x260>
+            goto no_pkt_buf;
+         packet->nb_blen = lilbufsiz;
+ 802838c:	d0e01717 	ldw	r3,-32676(gp)
+ 8028390:	e0bffa17 	ldw	r2,-24(fp)
+ 8028394:	10c00215 	stw	r3,8(r2)
+         q_add(&lilfreeq, packet);        /* save it in little free queue */
+ 8028398:	e17ffa17 	ldw	r5,-24(fp)
+ 802839c:	010201b4 	movhi	r4,2054
+ 80283a0:	21379604 	addi	r4,r4,-8616
+ 80283a4:	80289900 	call	8028990 <putq>
+   for (i = 0; i < numpkts; i++)
+ 80283a8:	e0bfff17 	ldw	r2,-4(fp)
+ 80283ac:	10800044 	addi	r2,r2,1
+ 80283b0:	e0bfff15 	stw	r2,-4(fp)
+ 80283b4:	e0ffff17 	ldw	r3,-4(fp)
+ 80283b8:	e0bffc17 	ldw	r2,-16(fp)
+ 80283bc:	18bf8536 	bltu	r3,r2,80281d4 <pk_init+0x2c>
+      }
+   }
+   bigfreeq.q_min = bigbufs;
+ 80283c0:	d0a01817 	ldw	r2,-32672(gp)
+ 80283c4:	1007883a 	mov	r3,r2
+ 80283c8:	008201b4 	movhi	r2,2054
+ 80283cc:	10f7df15 	stw	r3,-8324(r2)
+   lilfreeq.q_min = lilbufs;
+ 80283d0:	d0a01617 	ldw	r2,-32680(gp)
+ 80283d4:	1007883a 	mov	r3,r2
+ 80283d8:	008201b4 	movhi	r2,2054
+ 80283dc:	10f79a15 	stw	r3,-8600(r2)
+   heap_curr_mem_hi_watermark = 0;
+   /* set the heap's access type to blocking */
+   heap_type = HEAP_ACCESS_BLOCKING;
+#endif
+
+   return 0;
+ 80283e0:	0005883a 	mov	r2,zero
+ 80283e4:	00000e06 	br	8028420 <pk_init+0x278>
+         goto no_pkt_buf;
+ 80283e8:	0001883a 	nop
+ 80283ec:	00000706 	br	802840c <pk_init+0x264>
+               goto no_pkt_buf;
+ 80283f0:	0001883a 	nop
+ 80283f4:	00000506 	br	802840c <pk_init+0x264>
+            goto no_pkt_buf;
+ 80283f8:	0001883a 	nop
+ 80283fc:	00000306 	br	802840c <pk_init+0x264>
+               goto no_pkt_buf;
+ 8028400:	0001883a 	nop
+ 8028404:	00000106 	br	802840c <pk_init+0x264>
+            goto no_pkt_buf;
+ 8028408:	0001883a 	nop
+
+no_pkt_buf:
+#ifdef NPDEBUG
+   dprintf("Netinit: calloc failed getting buffer %d\n", i);
+ 802840c:	e17fff17 	ldw	r5,-4(fp)
+ 8028410:	01020174 	movhi	r4,2053
+ 8028414:	21294104 	addi	r4,r4,-23292
+ 8028418:	8002c780 	call	8002c78 <printf>
+#endif
+   return(-1);
+ 802841c:	00bfffc4 	movi	r2,-1
+}
+ 8028420:	e037883a 	mov	sp,fp
+ 8028424:	dfc00117 	ldw	ra,4(sp)
+ 8028428:	df000017 	ldw	fp,0(sp)
+ 802842c:	dec00204 	addi	sp,sp,8
+ 8028430:	f800283a 	ret
+
+08028434 <pk_alloc>:
+ * OUTPUT: 0 if the request cannot be satisfied, or a pointer to the struct
+ * netbuf structure that corresponds to the just allocated data buffer.
+ */
+
+PACKET pk_alloc(unsigned len)
+{
+ 8028434:	defffc04 	addi	sp,sp,-16
+ 8028438:	dfc00315 	stw	ra,12(sp)
+ 802843c:	df000215 	stw	fp,8(sp)
+ 8028440:	df000204 	addi	fp,sp,8
+ 8028444:	e13ffe15 	stw	r4,-8(fp)
+   PACKET p;
+
+   if (len > bigbufsiz) /* caller wants oversize buffer? */
+ 8028448:	d0e01917 	ldw	r3,-32668(gp)
+ 802844c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028450:	1880022e 	bgeu	r3,r2,802845c <pk_alloc+0x28>
+   {
+#ifdef HEAPBUFS
+      if ((p = pk_alloc_heapbuf (len)) == NULL)
+         return NULL;
+#else
+      return(NULL);
+ 8028454:	0005883a 	mov	r2,zero
+ 8028458:	00002106 	br	80284e0 <pk_alloc+0xac>
+#endif
+   }
+   else
+   {
+      if ((len > lilbufsiz) || (lilfreeq.q_len == 0)) /* must use a big buffer */
+ 802845c:	d0e01717 	ldw	r3,-32676(gp)
+ 8028460:	e0bffe17 	ldw	r2,-8(fp)
+ 8028464:	18800336 	bltu	r3,r2,8028474 <pk_alloc+0x40>
+ 8028468:	008201b4 	movhi	r2,2054
+ 802846c:	10b79817 	ldw	r2,-8608(r2)
+ 8028470:	1000051e 	bne	r2,zero,8028488 <pk_alloc+0x54>
+         p = (PACKET)getq(&bigfreeq);
+ 8028474:	010201b4 	movhi	r4,2054
+ 8028478:	2137db04 	addi	r4,r4,-8340
+ 802847c:	80288d80 	call	80288d8 <getq>
+ 8028480:	e0bfff15 	stw	r2,-4(fp)
+ 8028484:	00000406 	br	8028498 <pk_alloc+0x64>
+      else
+         p = (PACKET)getq(&lilfreeq);
+ 8028488:	010201b4 	movhi	r4,2054
+ 802848c:	21379604 	addi	r4,r4,-8616
+ 8028490:	80288d80 	call	80288d8 <getq>
+ 8028494:	e0bfff15 	stw	r2,-4(fp)
+
+      if (!p)
+ 8028498:	e0bfff17 	ldw	r2,-4(fp)
+ 802849c:	1000021e 	bne	r2,zero,80284a8 <pk_alloc+0x74>
+         return NULL;
+ 80284a0:	0005883a 	mov	r2,zero
+ 80284a4:	00000e06 	br	80284e0 <pk_alloc+0xac>
+   }
+
+   p->nb_prot = p->nb_buff + MaxLnh;   /* point past biggest mac header */
+ 80284a8:	e0bfff17 	ldw	r2,-4(fp)
+ 80284ac:	10800117 	ldw	r2,4(r2)
+ 80284b0:	d0e06417 	ldw	r3,-32368(gp)
+ 80284b4:	10c7883a 	add	r3,r2,r3
+ 80284b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80284bc:	10c00315 	stw	r3,12(r2)
+   p->nb_plen = 0;   /* no protocol data there yet */
+ 80284c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80284c4:	10000415 	stw	zero,16(r2)
+   p->net = NULL;
+ 80284c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80284cc:	10000615 	stw	zero,24(r2)
+   p->nexthop = NULL;      /* no next hop  */
+   p->nb_pmtu = 1240;      /* Set minimum IPv6 Path MTU */
+#endif   /* IP_V6 */
+#endif /* LINKED_PKTS */
+
+   p->inuse = 1;  /* initially buffer in use by 1 user */
+ 80284d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80284d4:	00c00044 	movi	r3,1
+ 80284d8:	10c00915 	stw	r3,36(r2)
+
+   /* note that 'type' and 'fhost' fields are not set in pk_alloc () */
+   return(p);
+ 80284dc:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80284e0:	e037883a 	mov	sp,fp
+ 80284e4:	dfc00117 	ldw	ra,4(sp)
+ 80284e8:	df000017 	ldw	fp,0(sp)
+ 80284ec:	dec00204 	addi	sp,sp,8
+ 80284f0:	f800283a 	ret
+
+080284f4 <pk_validate>:
+ * OUTPUT: 0 if the buffer being freed was successfully validated, or
+ * -1 if the validation failed.
+ */
+
+int pk_validate(PACKET pkt)   /* check if pk_free() can free the pkt */
+{
+ 80284f4:	defffb04 	addi	sp,sp,-20
+ 80284f8:	dfc00415 	stw	ra,16(sp)
+ 80284fc:	df000315 	stw	fp,12(sp)
+ 8028500:	df000304 	addi	fp,sp,12
+ 8028504:	e13ffd15 	stw	r4,-12(fp)
+   /* If packet link is non-zero, then this packet is
+    * part of a chain and deleted this packet would break
+    * the chain and cause memory leak for subsequent pkts.
+    * Note that heapbufs do not use the 'next' field at all.
+    */
+   if ((pkt->next) && (pkt->inuse >= 1))
+ 8028508:	e0bffd17 	ldw	r2,-12(fp)
+ 802850c:	10800017 	ldw	r2,0(r2)
+ 8028510:	10000c26 	beq	r2,zero,8028544 <pk_validate+0x50>
+ 8028514:	e0bffd17 	ldw	r2,-12(fp)
+ 8028518:	10800917 	ldw	r2,36(r2)
+ 802851c:	10000926 	beq	r2,zero,8028544 <pk_validate+0x50>
+   {
+      INCR_SHARED_VAR (memestats, INCONSISTENT_LOCATION_ERR, 1);   
+ 8028520:	8028e940 	call	8028e94 <irq_Mask>
+ 8028524:	008201b4 	movhi	r2,2054
+ 8028528:	10b79e17 	ldw	r2,-8584(r2)
+ 802852c:	10c00044 	addi	r3,r2,1
+ 8028530:	008201b4 	movhi	r2,2054
+ 8028534:	10f79e15 	stw	r3,-8584(r2)
+ 8028538:	8028ef40 	call	8028ef4 <irq_Unmask>
+      return -1;
+ 802853c:	00bfffc4 	movi	r2,-1
+ 8028540:	00007c06 	br	8028734 <pk_validate+0x240>
+   }
+   else  
+#endif /* HEAPBUFS */
+   {
+      /* check if the packet is already in a freeq */
+      if (pkt->nb_blen == bigbufsiz)  /* check in bigfreeq */
+ 8028544:	e0bffd17 	ldw	r2,-12(fp)
+ 8028548:	10c00217 	ldw	r3,8(r2)
+ 802854c:	d0a01917 	ldw	r2,-32668(gp)
+ 8028550:	18801d1e 	bne	r3,r2,80285c8 <pk_validate+0xd4>
+      {
+         ENTER_CRIT_SECTION(&bigfreeq);
+ 8028554:	8028e940 	call	8028e94 <irq_Mask>
+         for (p=(PACKET)bigfreeq.q_head; p; p = p->next)
+ 8028558:	008201b4 	movhi	r2,2054
+ 802855c:	10b7db17 	ldw	r2,-8340(r2)
+ 8028560:	e0bfff15 	stw	r2,-4(fp)
+ 8028564:	00001406 	br	80285b8 <pk_validate+0xc4>
+            if (p == pkt)
+ 8028568:	e0ffff17 	ldw	r3,-4(fp)
+ 802856c:	e0bffd17 	ldw	r2,-12(fp)
+ 8028570:	18800e1e 	bne	r3,r2,80285ac <pk_validate+0xb8>
+            {
+               dprintf("pk_free: buffer %p already in bigfreeq\n", pkt);
+ 8028574:	e17ffd17 	ldw	r5,-12(fp)
+ 8028578:	01020174 	movhi	r4,2053
+ 802857c:	21294c04 	addi	r4,r4,-23248
+ 8028580:	8002c780 	call	8002c78 <printf>
+               EXIT_CRIT_SECTION(&bigfreeq);
+ 8028584:	8028ef40 	call	8028ef4 <irq_Unmask>
+               INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1);
+ 8028588:	8028e940 	call	8028e94 <irq_Mask>
+ 802858c:	008201b4 	movhi	r2,2054
+ 8028590:	10b79d17 	ldw	r2,-8588(r2)
+ 8028594:	10c00044 	addi	r3,r2,1
+ 8028598:	008201b4 	movhi	r2,2054
+ 802859c:	10f79d15 	stw	r3,-8588(r2)
+ 80285a0:	8028ef40 	call	8028ef4 <irq_Unmask>
+               return -1;
+ 80285a4:	00bfffc4 	movi	r2,-1
+ 80285a8:	00006206 	br	8028734 <pk_validate+0x240>
+         for (p=(PACKET)bigfreeq.q_head; p; p = p->next)
+ 80285ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80285b0:	10800017 	ldw	r2,0(r2)
+ 80285b4:	e0bfff15 	stw	r2,-4(fp)
+ 80285b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80285bc:	103fea1e 	bne	r2,zero,8028568 <pk_validate+0x74>
+            }
+         EXIT_CRIT_SECTION(&bigfreeq);
+ 80285c0:	8028ef40 	call	8028ef4 <irq_Unmask>
+ 80285c4:	00002a06 	br	8028670 <pk_validate+0x17c>
+      }
+      else if (pkt->nb_blen == lilbufsiz)  /* check in lilfreeq */
+ 80285c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80285cc:	10c00217 	ldw	r3,8(r2)
+ 80285d0:	d0a01717 	ldw	r2,-32676(gp)
+ 80285d4:	18801d1e 	bne	r3,r2,802864c <pk_validate+0x158>
+      {
+         ENTER_CRIT_SECTION(&lilfreeq);
+ 80285d8:	8028e940 	call	8028e94 <irq_Mask>
+         for (p=(PACKET)lilfreeq.q_head; p; p = p->next)
+ 80285dc:	008201b4 	movhi	r2,2054
+ 80285e0:	10b79617 	ldw	r2,-8616(r2)
+ 80285e4:	e0bfff15 	stw	r2,-4(fp)
+ 80285e8:	00001406 	br	802863c <pk_validate+0x148>
+            if (p == pkt)
+ 80285ec:	e0ffff17 	ldw	r3,-4(fp)
+ 80285f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80285f4:	18800e1e 	bne	r3,r2,8028630 <pk_validate+0x13c>
+         {
+            dprintf("pk_free: buffer %p already in lilfreeq\n", pkt);
+ 80285f8:	e17ffd17 	ldw	r5,-12(fp)
+ 80285fc:	01020174 	movhi	r4,2053
+ 8028600:	21295604 	addi	r4,r4,-23208
+ 8028604:	8002c780 	call	8002c78 <printf>
+            EXIT_CRIT_SECTION(&lilfreeq);
+ 8028608:	8028ef40 	call	8028ef4 <irq_Unmask>
+            INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1);
+ 802860c:	8028e940 	call	8028e94 <irq_Mask>
+ 8028610:	008201b4 	movhi	r2,2054
+ 8028614:	10b79d17 	ldw	r2,-8588(r2)
+ 8028618:	10c00044 	addi	r3,r2,1
+ 802861c:	008201b4 	movhi	r2,2054
+ 8028620:	10f79d15 	stw	r3,-8588(r2)
+ 8028624:	8028ef40 	call	8028ef4 <irq_Unmask>
+            return -1;
+ 8028628:	00bfffc4 	movi	r2,-1
+ 802862c:	00004106 	br	8028734 <pk_validate+0x240>
+         for (p=(PACKET)lilfreeq.q_head; p; p = p->next)
+ 8028630:	e0bfff17 	ldw	r2,-4(fp)
+ 8028634:	10800017 	ldw	r2,0(r2)
+ 8028638:	e0bfff15 	stw	r2,-4(fp)
+ 802863c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028640:	103fea1e 	bne	r2,zero,80285ec <pk_validate+0xf8>
+         }
+         EXIT_CRIT_SECTION(&lilfreeq);
+ 8028644:	8028ef40 	call	8028ef4 <irq_Unmask>
+ 8028648:	00000906 	br	8028670 <pk_validate+0x17c>
+      }
+      else
+      {
+         /* log an error */
+         INCR_SHARED_VAR (memestats, BAD_REGULAR_BUF_LEN_ERR, 1);
+ 802864c:	8028e940 	call	8028e94 <irq_Mask>
+ 8028650:	008201b4 	movhi	r2,2054
+ 8028654:	10b79b17 	ldw	r2,-8596(r2)
+ 8028658:	10c00044 	addi	r3,r2,1
+ 802865c:	008201b4 	movhi	r2,2054
+ 8028660:	10f79b15 	stw	r3,-8596(r2)
+ 8028664:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return -1;
+ 8028668:	00bfffc4 	movi	r2,-1
+ 802866c:	00003106 	br	8028734 <pk_validate+0x240>
+   }
+
+#ifdef NPDEBUG
+   /* check for corruption of memory markers (the guard bands are only
+    * present when NPDEBUG is defined) */
+   for (j = ALIGN_TYPE; j > 0; j--)
+ 8028670:	00800104 	movi	r2,4
+ 8028674:	e0bffe15 	stw	r2,-8(fp)
+ 8028678:	00001706 	br	80286d8 <pk_validate+0x1e4>
+   {
+      if (*(pkt->nb_buff - j) != 'M')
+ 802867c:	e0bffd17 	ldw	r2,-12(fp)
+ 8028680:	10c00117 	ldw	r3,4(r2)
+ 8028684:	e0bffe17 	ldw	r2,-8(fp)
+ 8028688:	0085c83a 	sub	r2,zero,r2
+ 802868c:	1885883a 	add	r2,r3,r2
+ 8028690:	10800003 	ldbu	r2,0(r2)
+ 8028694:	10803fcc 	andi	r2,r2,255
+ 8028698:	1080201c 	xori	r2,r2,128
+ 802869c:	10bfe004 	addi	r2,r2,-128
+ 80286a0:	10801360 	cmpeqi	r2,r2,77
+ 80286a4:	1000091e 	bne	r2,zero,80286cc <pk_validate+0x1d8>
+      {
+         INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1);
+ 80286a8:	8028e940 	call	8028e94 <irq_Mask>
+ 80286ac:	008201b4 	movhi	r2,2054
+ 80286b0:	10b79c17 	ldw	r2,-8592(r2)
+ 80286b4:	10c00044 	addi	r3,r2,1
+ 80286b8:	008201b4 	movhi	r2,2054
+ 80286bc:	10f79c15 	stw	r3,-8592(r2)
+ 80286c0:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return -1;
+ 80286c4:	00bfffc4 	movi	r2,-1
+ 80286c8:	00001a06 	br	8028734 <pk_validate+0x240>
+   for (j = ALIGN_TYPE; j > 0; j--)
+ 80286cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80286d0:	10bfffc4 	addi	r2,r2,-1
+ 80286d4:	e0bffe15 	stw	r2,-8(fp)
+ 80286d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80286dc:	00bfe716 	blt	zero,r2,802867c <pk_validate+0x188>
+      }
+   }
+   if (*(pkt->nb_buff + pkt->nb_blen) != 'M')
+ 80286e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80286e4:	10c00117 	ldw	r3,4(r2)
+ 80286e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80286ec:	10800217 	ldw	r2,8(r2)
+ 80286f0:	1885883a 	add	r2,r3,r2
+ 80286f4:	10800003 	ldbu	r2,0(r2)
+ 80286f8:	10803fcc 	andi	r2,r2,255
+ 80286fc:	1080201c 	xori	r2,r2,128
+ 8028700:	10bfe004 	addi	r2,r2,-128
+ 8028704:	10801360 	cmpeqi	r2,r2,77
+ 8028708:	1000091e 	bne	r2,zero,8028730 <pk_validate+0x23c>
+   {
+      INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1);
+ 802870c:	8028e940 	call	8028e94 <irq_Mask>
+ 8028710:	008201b4 	movhi	r2,2054
+ 8028714:	10b79c17 	ldw	r2,-8592(r2)
+ 8028718:	10c00044 	addi	r3,r2,1
+ 802871c:	008201b4 	movhi	r2,2054
+ 8028720:	10f79c15 	stw	r3,-8592(r2)
+ 8028724:	8028ef40 	call	8028ef4 <irq_Unmask>
+      return -1;
+ 8028728:	00bfffc4 	movi	r2,-1
+ 802872c:	00000106 	br	8028734 <pk_validate+0x240>
+   }
+#endif /* NPDEBUG */
+
+   return 0;
+ 8028730:	0005883a 	mov	r2,zero
+}
+ 8028734:	e037883a 	mov	sp,fp
+ 8028738:	dfc00117 	ldw	ra,4(sp)
+ 802873c:	df000017 	ldw	fp,0(sp)
+ 8028740:	dec00204 	addi	sp,sp,8
+ 8028744:	f800283a 	ret
+
+08028748 <pk_free>:
+ *
+ * OUTPUT: None.
+ */
+
+void pk_free(PACKET pkt)   /* PACKET to place in free queue */
+{
+ 8028748:	defffc04 	addi	sp,sp,-16
+ 802874c:	dfc00315 	stw	ra,12(sp)
+ 8028750:	df000215 	stw	fp,8(sp)
+ 8028754:	df000204 	addi	fp,sp,8
+ 8028758:	e13ffe15 	stw	r4,-8(fp)
+      PACKET pknext;
+      pknext = pkt->pk_next;
+#endif /* LINKED_PKTS */
+
+      /* validate the pkt before freeing */
+      e = pk_validate(pkt);
+ 802875c:	e13ffe17 	ldw	r4,-8(fp)
+ 8028760:	80284f40 	call	80284f4 <pk_validate>
+ 8028764:	e0bfff15 	stw	r2,-4(fp)
+      if (e)
+ 8028768:	e0bfff17 	ldw	r2,-4(fp)
+ 802876c:	1000191e 	bne	r2,zero,80287d4 <pk_free+0x8c>
+            continue; /* skip this pkt, examine the next pkt */
+         }
+#endif
+         return;
+      }
+      if (pkt->inuse-- > 1)   /* more than 1 owner? */
+ 8028770:	e0bffe17 	ldw	r2,-8(fp)
+ 8028774:	10800917 	ldw	r2,36(r2)
+ 8028778:	113fffc4 	addi	r4,r2,-1
+ 802877c:	e0fffe17 	ldw	r3,-8(fp)
+ 8028780:	19000915 	stw	r4,36(r3)
+ 8028784:	108000b0 	cmpltui	r2,r2,2
+ 8028788:	10001426 	beq	r2,zero,80287dc <pk_free+0x94>
+         pk_free_heapbuf (pkt);
+      }
+      else 
+#endif /* HEAPBUFS */
+      {
+         if (pkt->nb_blen == bigbufsiz)
+ 802878c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028790:	10c00217 	ldw	r3,8(r2)
+ 8028794:	d0a01917 	ldw	r2,-32668(gp)
+ 8028798:	1880051e 	bne	r3,r2,80287b0 <pk_free+0x68>
+            q_add(&bigfreeq, (qp)pkt);
+ 802879c:	e17ffe17 	ldw	r5,-8(fp)
+ 80287a0:	010201b4 	movhi	r4,2054
+ 80287a4:	2137db04 	addi	r4,r4,-8340
+ 80287a8:	80289900 	call	8028990 <putq>
+ 80287ac:	00000c06 	br	80287e0 <pk_free+0x98>
+         else if (pkt->nb_blen == lilbufsiz)
+ 80287b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80287b4:	10c00217 	ldw	r3,8(r2)
+ 80287b8:	d0a01717 	ldw	r2,-32676(gp)
+ 80287bc:	1880081e 	bne	r3,r2,80287e0 <pk_free+0x98>
+            q_add(&lilfreeq, (qp)pkt);
+ 80287c0:	e17ffe17 	ldw	r5,-8(fp)
+ 80287c4:	010201b4 	movhi	r4,2054
+ 80287c8:	21379604 	addi	r4,r4,-8616
+ 80287cc:	80289900 	call	8028990 <putq>
+ 80287d0:	00000306 	br	80287e0 <pk_free+0x98>
+         return;
+ 80287d4:	0001883a 	nop
+ 80287d8:	00000106 	br	80287e0 <pk_free+0x98>
+         return;  /* packet was cloned, don't delete yet */
+ 80287dc:	0001883a 	nop
+#ifdef LINKED_PKTS
+      pkt = pknext;
+   }
+#endif 
+
+}
+ 80287e0:	e037883a 	mov	sp,fp
+ 80287e4:	dfc00117 	ldw	ra,4(sp)
+ 80287e8:	df000017 	ldw	fp,0(sp)
+ 80287ec:	dec00204 	addi	sp,sp,8
+ 80287f0:	f800283a 	ret
+
+080287f4 <pk_get_max_intrsafe_buf_len>:
+ *
+ * OUTPUT: This function always returns the length of a big buffer (bigbufsiz).
+ */
+
+unsigned pk_get_max_intrsafe_buf_len(void)
+{
+ 80287f4:	deffff04 	addi	sp,sp,-4
+ 80287f8:	df000015 	stw	fp,0(sp)
+ 80287fc:	d839883a 	mov	fp,sp
+   return bigbufsiz;
+ 8028800:	d0a01917 	ldw	r2,-32668(gp)
+}
+ 8028804:	e037883a 	mov	sp,fp
+ 8028808:	df000017 	ldw	fp,0(sp)
+ 802880c:	dec00104 	addi	sp,sp,4
+ 8028810:	f800283a 	ret
+
+08028814 <dump_buf_estats>:
+ *
+ * OUTPUT: This function always returns 0.
+ */
+
+int dump_buf_estats (void * pio)
+{
+ 8028814:	defff904 	addi	sp,sp,-28
+ 8028818:	dfc00615 	stw	ra,24(sp)
+ 802881c:	df000515 	stw	fp,20(sp)
+ 8028820:	df000504 	addi	fp,sp,20
+ 8028824:	e13ffb15 	stw	r4,-20(fp)
+   u_long mlocal [MEMERR_NUM_STATS];
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8028828:	01000084 	movi	r4,2
+ 802882c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   ENTER_CRIT_SECTION(&memestats);
+ 8028830:	8028e940 	call	8028e94 <irq_Mask>
+   MEMCPY (&mlocal, &memestats, sizeof(memestats));
+ 8028834:	008201b4 	movhi	r2,2054
+ 8028838:	10b79b17 	ldw	r2,-8596(r2)
+ 802883c:	e0bffc15 	stw	r2,-16(fp)
+ 8028840:	008201b4 	movhi	r2,2054
+ 8028844:	10b79c17 	ldw	r2,-8592(r2)
+ 8028848:	e0bffd15 	stw	r2,-12(fp)
+ 802884c:	008201b4 	movhi	r2,2054
+ 8028850:	10b79d17 	ldw	r2,-8588(r2)
+ 8028854:	e0bffe15 	stw	r2,-8(fp)
+ 8028858:	008201b4 	movhi	r2,2054
+ 802885c:	10b79e17 	ldw	r2,-8584(r2)
+ 8028860:	e0bfff15 	stw	r2,-4(fp)
+   EXIT_CRIT_SECTION(&memestats);
+ 8028864:	8028ef40 	call	8028ef4 <irq_Unmask>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8028868:	01000084 	movi	r4,2
+ 802886c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   ns_printf(pio, "Regular buffer error statistics:\n");
+ 8028870:	01420174 	movhi	r5,2053
+ 8028874:	29696004 	addi	r5,r5,-23168
+ 8028878:	e13ffb17 	ldw	r4,-20(fp)
+ 802887c:	80273900 	call	8027390 <ns_printf>
+   ns_printf(pio, "Bad buffer length %lu, Guard band violations %lu\n",mlocal[BAD_REGULAR_BUF_LEN_ERR],mlocal[GUARD_BAND_VIOLATED_ERR]);
+ 8028880:	e0bffc17 	ldw	r2,-16(fp)
+ 8028884:	e0fffd17 	ldw	r3,-12(fp)
+ 8028888:	180f883a 	mov	r7,r3
+ 802888c:	100d883a 	mov	r6,r2
+ 8028890:	01420174 	movhi	r5,2053
+ 8028894:	29696904 	addi	r5,r5,-23132
+ 8028898:	e13ffb17 	ldw	r4,-20(fp)
+ 802889c:	80273900 	call	8027390 <ns_printf>
+   ns_printf(pio, "Multiple frees %lu, Inconsistent location %lu\n",mlocal[MULTIPLE_FREE_ERR],mlocal[INCONSISTENT_LOCATION_ERR]);
+ 80288a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80288a4:	e0ffff17 	ldw	r3,-4(fp)
+ 80288a8:	180f883a 	mov	r7,r3
+ 80288ac:	100d883a 	mov	r6,r2
+ 80288b0:	01420174 	movhi	r5,2053
+ 80288b4:	29697604 	addi	r5,r5,-23080
+ 80288b8:	e13ffb17 	ldw	r4,-20(fp)
+ 80288bc:	80273900 	call	8027390 <ns_printf>
+
+   return 0;
+ 80288c0:	0005883a 	mov	r2,zero
+}
+ 80288c4:	e037883a 	mov	sp,fp
+ 80288c8:	dfc00117 	ldw	ra,4(sp)
+ 80288cc:	df000017 	ldw	fp,0(sp)
+ 80288d0:	dec00204 	addi	sp,sp,8
+ 80288d4:	f800283a 	ret
+
+080288d8 <getq>:
+ * RETURNS: pointer to the first element if any, or 0 if the queue is empty.
+ */
+
+void*
+getq(queue * q)
+{
+ 80288d8:	defffc04 	addi	sp,sp,-16
+ 80288dc:	dfc00315 	stw	ra,12(sp)
+ 80288e0:	df000215 	stw	fp,8(sp)
+ 80288e4:	df000204 	addi	fp,sp,8
+ 80288e8:	e13ffe15 	stw	r4,-8(fp)
+   q_elt   temp;        /* temp for result */
+
+
+   ENTER_CRIT_SECTION(q);     /* shut off ints, save old state */   
+ 80288ec:	8028e940 	call	8028e94 <irq_Mask>
+
+   LOCKNET_CHECK(q);          /* make sure queue is protected */
+
+   if ((temp = q->q_head) == 0)  /* queue empty? */
+ 80288f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80288f4:	10800017 	ldw	r2,0(r2)
+ 80288f8:	e0bfff15 	stw	r2,-4(fp)
+ 80288fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8028900:	1000031e 	bne	r2,zero,8028910 <getq+0x38>
+   {
+      EXIT_CRIT_SECTION(q);
+ 8028904:	8028ef40 	call	8028ef4 <irq_Unmask>
+      return (0);             /* yes, show none */
+ 8028908:	0005883a 	mov	r2,zero
+ 802890c:	00001b06 	br	802897c <getq+0xa4>
+   }
+
+   q->q_head = temp->qe_next; /* else unlink */
+ 8028910:	e0bfff17 	ldw	r2,-4(fp)
+ 8028914:	10c00017 	ldw	r3,0(r2)
+ 8028918:	e0bffe17 	ldw	r2,-8(fp)
+ 802891c:	10c00015 	stw	r3,0(r2)
+   temp->qe_next = 0;         /* avoid dangling pointers */
+ 8028920:	e0bfff17 	ldw	r2,-4(fp)
+ 8028924:	10000015 	stw	zero,0(r2)
+   if (q->q_head == 0)        /* queue empty? */
+ 8028928:	e0bffe17 	ldw	r2,-8(fp)
+ 802892c:	10800017 	ldw	r2,0(r2)
+ 8028930:	1000021e 	bne	r2,zero,802893c <getq+0x64>
+      q->q_tail = 0;          /* yes, update tail pointer too */
+ 8028934:	e0bffe17 	ldw	r2,-8(fp)
+ 8028938:	10000115 	stw	zero,4(r2)
+   q->q_len--;                /* update queue length */
+ 802893c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028940:	10800217 	ldw	r2,8(r2)
+ 8028944:	10ffffc4 	addi	r3,r2,-1
+ 8028948:	e0bffe17 	ldw	r2,-8(fp)
+ 802894c:	10c00215 	stw	r3,8(r2)
+   if (q->q_len < q->q_min)
+ 8028950:	e0bffe17 	ldw	r2,-8(fp)
+ 8028954:	10c00217 	ldw	r3,8(r2)
+ 8028958:	e0bffe17 	ldw	r2,-8(fp)
+ 802895c:	10800417 	ldw	r2,16(r2)
+ 8028960:	1880040e 	bge	r3,r2,8028974 <getq+0x9c>
+      q->q_min = q->q_len;
+ 8028964:	e0bffe17 	ldw	r2,-8(fp)
+ 8028968:	10c00217 	ldw	r3,8(r2)
+ 802896c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028970:	10c00415 	stw	r3,16(r2)
+
+   QUEUE_CHECK(q);         /* make sure queue is not corrupted */
+
+   EXIT_CRIT_SECTION(q);   /* restore caller's int state */
+ 8028974:	8028ef40 	call	8028ef4 <irq_Unmask>
+
+   return ((void*)temp);
+ 8028978:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802897c:	e037883a 	mov	sp,fp
+ 8028980:	dfc00117 	ldw	ra,4(sp)
+ 8028984:	df000017 	ldw	fp,0(sp)
+ 8028988:	dec00204 	addi	sp,sp,8
+ 802898c:	f800283a 	ret
+
+08028990 <putq>:
+
+void
+putq(
+   queue   *   q,       /* the queue */
+   void *   elt)        /* element to delete */
+{
+ 8028990:	defffc04 	addi	sp,sp,-16
+ 8028994:	dfc00315 	stw	ra,12(sp)
+ 8028998:	df000215 	stw	fp,8(sp)
+ 802899c:	df000204 	addi	fp,sp,8
+ 80289a0:	e13fff15 	stw	r4,-4(fp)
+ 80289a4:	e17ffe15 	stw	r5,-8(fp)
+   ENTER_CRIT_SECTION(q);
+ 80289a8:	8028e940 	call	8028e94 <irq_Mask>
+   LOCKNET_CHECK(q);       /* make sure queue is protected */
+   q_addt(q, (qp)elt);     /* use macro to do work */
+ 80289ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80289b0:	10000015 	stw	zero,0(r2)
+ 80289b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80289b8:	10800017 	ldw	r2,0(r2)
+ 80289bc:	1000041e 	bne	r2,zero,80289d0 <putq+0x40>
+ 80289c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80289c4:	e0fffe17 	ldw	r3,-8(fp)
+ 80289c8:	10c00015 	stw	r3,0(r2)
+ 80289cc:	00000406 	br	80289e0 <putq+0x50>
+ 80289d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80289d4:	10800117 	ldw	r2,4(r2)
+ 80289d8:	e0fffe17 	ldw	r3,-8(fp)
+ 80289dc:	10c00015 	stw	r3,0(r2)
+ 80289e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80289e4:	e0fffe17 	ldw	r3,-8(fp)
+ 80289e8:	10c00115 	stw	r3,4(r2)
+ 80289ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80289f0:	10800217 	ldw	r2,8(r2)
+ 80289f4:	10c00044 	addi	r3,r2,1
+ 80289f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80289fc:	10c00215 	stw	r3,8(r2)
+ 8028a00:	e0bfff17 	ldw	r2,-4(fp)
+ 8028a04:	10800217 	ldw	r2,8(r2)
+ 8028a08:	e0ffff17 	ldw	r3,-4(fp)
+ 8028a0c:	18c00317 	ldw	r3,12(r3)
+ 8028a10:	1880040e 	bge	r3,r2,8028a24 <putq+0x94>
+ 8028a14:	e0bfff17 	ldw	r2,-4(fp)
+ 8028a18:	10c00217 	ldw	r3,8(r2)
+ 8028a1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028a20:	10c00315 	stw	r3,12(r2)
+   QUEUE_CHECK(q);         /* make sure queue is not corrupted */
+   EXIT_CRIT_SECTION(q);   /* restore int state */
+ 8028a24:	8028ef40 	call	8028ef4 <irq_Unmask>
+}
+ 8028a28:	0001883a 	nop
+ 8028a2c:	e037883a 	mov	sp,fp
+ 8028a30:	dfc00117 	ldw	ra,4(sp)
+ 8028a34:	df000017 	ldw	fp,0(sp)
+ 8028a38:	dec00204 	addi	sp,sp,8
+ 8028a3c:	f800283a 	ret
+
+08028a40 <qdel>:
+ * RETURNS: Return pointer to queue member if found, else NULL. 
+ */
+
+qp
+qdel(queue * q, void * elt)
+{
+ 8028a40:	defffa04 	addi	sp,sp,-24
+ 8028a44:	dfc00515 	stw	ra,20(sp)
+ 8028a48:	df000415 	stw	fp,16(sp)
+ 8028a4c:	df000404 	addi	fp,sp,16
+ 8028a50:	e13ffd15 	stw	r4,-12(fp)
+ 8028a54:	e17ffc15 	stw	r5,-16(fp)
+   qp qptr;
+   qp qlast;
+
+   /* search queue for element passed */
+   ENTER_CRIT_SECTION(q);
+ 8028a58:	8028e940 	call	8028e94 <irq_Mask>
+   qptr = q->q_head;
+ 8028a5c:	e0bffd17 	ldw	r2,-12(fp)
+ 8028a60:	10800017 	ldw	r2,0(r2)
+ 8028a64:	e0bfff15 	stw	r2,-4(fp)
+   qlast = NULL;
+ 8028a68:	e03ffe15 	stw	zero,-8(fp)
+   while (qptr)
+ 8028a6c:	00002b06 	br	8028b1c <qdel+0xdc>
+   {
+      if (qptr == (qp)elt)
+ 8028a70:	e0ffff17 	ldw	r3,-4(fp)
+ 8028a74:	e0bffc17 	ldw	r2,-16(fp)
+ 8028a78:	1880231e 	bne	r3,r2,8028b08 <qdel+0xc8>
+      {
+         /* found our item; dequeue it */
+         if (qlast)
+ 8028a7c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028a80:	10000526 	beq	r2,zero,8028a98 <qdel+0x58>
+            qlast->qe_next = qptr->qe_next;
+ 8028a84:	e0bfff17 	ldw	r2,-4(fp)
+ 8028a88:	10c00017 	ldw	r3,0(r2)
+ 8028a8c:	e0bffe17 	ldw	r2,-8(fp)
+ 8028a90:	10c00015 	stw	r3,0(r2)
+ 8028a94:	00000406 	br	8028aa8 <qdel+0x68>
+         else     /* item was at head of queqe */
+            q->q_head = qptr->qe_next;
+ 8028a98:	e0bfff17 	ldw	r2,-4(fp)
+ 8028a9c:	10c00017 	ldw	r3,0(r2)
+ 8028aa0:	e0bffd17 	ldw	r2,-12(fp)
+ 8028aa4:	10c00015 	stw	r3,0(r2)
+
+         /* fix queue tail pointer if needed */
+         if (q->q_tail == (qp)elt)
+ 8028aa8:	e0bffd17 	ldw	r2,-12(fp)
+ 8028aac:	10800117 	ldw	r2,4(r2)
+ 8028ab0:	e0fffc17 	ldw	r3,-16(fp)
+ 8028ab4:	1880031e 	bne	r3,r2,8028ac4 <qdel+0x84>
+            q->q_tail = qlast;
+ 8028ab8:	e0bffd17 	ldw	r2,-12(fp)
+ 8028abc:	e0fffe17 	ldw	r3,-8(fp)
+ 8028ac0:	10c00115 	stw	r3,4(r2)
+
+         /* fix queue counters */
+         q->q_len--;
+ 8028ac4:	e0bffd17 	ldw	r2,-12(fp)
+ 8028ac8:	10800217 	ldw	r2,8(r2)
+ 8028acc:	10ffffc4 	addi	r3,r2,-1
+ 8028ad0:	e0bffd17 	ldw	r2,-12(fp)
+ 8028ad4:	10c00215 	stw	r3,8(r2)
+         if (q->q_len < q->q_min)
+ 8028ad8:	e0bffd17 	ldw	r2,-12(fp)
+ 8028adc:	10c00217 	ldw	r3,8(r2)
+ 8028ae0:	e0bffd17 	ldw	r2,-12(fp)
+ 8028ae4:	10800417 	ldw	r2,16(r2)
+ 8028ae8:	1880040e 	bge	r3,r2,8028afc <qdel+0xbc>
+            q->q_min = q->q_len;
+ 8028aec:	e0bffd17 	ldw	r2,-12(fp)
+ 8028af0:	10c00217 	ldw	r3,8(r2)
+ 8028af4:	e0bffd17 	ldw	r2,-12(fp)
+ 8028af8:	10c00415 	stw	r3,16(r2)
+         EXIT_CRIT_SECTION(q);   /* restore int state */
+ 8028afc:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return (qp)elt;   /* success exit point */
+ 8028b00:	e0bffc17 	ldw	r2,-16(fp)
+ 8028b04:	00000906 	br	8028b2c <qdel+0xec>
+      }
+      qlast = qptr;
+ 8028b08:	e0bfff17 	ldw	r2,-4(fp)
+ 8028b0c:	e0bffe15 	stw	r2,-8(fp)
+      qptr = qptr->qe_next;
+ 8028b10:	e0bfff17 	ldw	r2,-4(fp)
+ 8028b14:	10800017 	ldw	r2,0(r2)
+ 8028b18:	e0bfff15 	stw	r2,-4(fp)
+   while (qptr)
+ 8028b1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028b20:	103fd31e 	bne	r2,zero,8028a70 <qdel+0x30>
+   }
+   EXIT_CRIT_SECTION(q);   /* restore int state */
+ 8028b24:	8028ef40 	call	8028ef4 <irq_Unmask>
+   return NULL;   /* item not found in queue */
+ 8028b28:	0005883a 	mov	r2,zero
+}
+ 8028b2c:	e037883a 	mov	sp,fp
+ 8028b30:	dfc00117 	ldw	ra,4(sp)
+ 8028b34:	df000017 	ldw	fp,0(sp)
+ 8028b38:	dec00204 	addi	sp,sp,8
+ 8028b3c:	f800283a 	ret
+
+08028b40 <asm_cksum>:
+      .text
+
+      .global	  asm_cksum
+
+asm_cksum:
+      mov   r2, zero		       /* accumulator = 0 */
+ 8028b40:	0005883a 	mov	r2,zero
+      ble   r5, zero, done	       /* count <= 0 ? */
+ 8028b44:	0140620e 	bge	zero,r5,8028cd0 <done>
+
+      mov   r6, zero		       /* carry accumulator */
+ 8028b48:	000d883a 	mov	r6,zero
+
+      andi  r3, r4, 2		       /* ptr 32-bit aligned? */
+ 8028b4c:	20c0008c 	andi	r3,r4,2
+      beq   r3, zero, asm1
+ 8028b50:	18000326 	beq	r3,zero,8028b60 <asm1>
+      ldhu  r2, (r4)		       /* no - process first 16-bits */
+ 8028b54:	2080000b 	ldhu	r2,0(r4)
+      addi  r4, r4, 2
+ 8028b58:	21000084 	addi	r4,r4,2
+      subi  r5, r5, 1
+ 8028b5c:	297fffc4 	addi	r5,r5,-1
+
+08028b60 <asm1>:
+ 8028b60:	02c200f4 	movhi	r11,2051
+/*
+ * adjust ptr by ((count/2) mod 16) * 4 bytes
+ * jump to location: loop0 - (count/2 mod 16) * 4 instructions
+ */
+asm1:
+      movia r11, loop0
+ 8028b64:	5ae32304 	addi	r11,r11,-29556
+      andi  r9, r5, 1		       /* r9 = last halfword flag */
+ 8028b68:	2a40004c 	andi	r9,r5,1
+      srai  r5, r5, 1		       /* count = number of words */
+ 8028b6c:	280bd07a 	srai	r5,r5,1
+      andi  r10, r5, 0xf	       /* modulo 16 */
+ 8028b70:	2a8003cc 	andi	r10,r5,15
+      slli  r10, r10, 2		       /*      * 4 bytes per word */
+ 8028b74:	501490ba 	slli	r10,r10,2
+      add   r4, r10, r4		       /* adjust ptr */
+ 8028b78:	5109883a 	add	r4,r10,r4
+      slli  r10, r10, 2		       /*      * 4 instructions per 4 bytes */
+ 8028b7c:	501490ba 	slli	r10,r10,2
+      sub   r11, r11, r10
+ 8028b80:	5a97c83a 	sub	r11,r11,r10
+      jmp   r11
+ 8028b84:	5800683a 	jmp	r11
+
+08028b88 <loop>:
+      
+loop:
+      addi  r4, r4, 64		       /* increment data pointer */
+ 8028b88:	21001004 	addi	r4,r4,64
+
+      ldw   r7, -64(r4)
+ 8028b8c:	21fff017 	ldw	r7,-64(r4)
+      add   r2, r7, r2
+ 8028b90:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028b94:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028b98:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -60(r4)
+ 8028b9c:	21fff117 	ldw	r7,-60(r4)
+      add   r2, r7, r2
+ 8028ba0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028ba4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028ba8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -56(r4)
+ 8028bac:	21fff217 	ldw	r7,-56(r4)
+      add   r2, r7, r2
+ 8028bb0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028bb4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028bb8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -52(r4)
+ 8028bbc:	21fff317 	ldw	r7,-52(r4)
+      add   r2, r7, r2
+ 8028bc0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028bc4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028bc8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -48(r4)
+ 8028bcc:	21fff417 	ldw	r7,-48(r4)
+      add   r2, r7, r2
+ 8028bd0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028bd4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028bd8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -44(r4)
+ 8028bdc:	21fff517 	ldw	r7,-44(r4)
+      add   r2, r7, r2
+ 8028be0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028be4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028be8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -40(r4)
+ 8028bec:	21fff617 	ldw	r7,-40(r4)
+      add   r2, r7, r2
+ 8028bf0:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028bf4:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028bf8:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -36(r4)
+ 8028bfc:	21fff717 	ldw	r7,-36(r4)
+      add   r2, r7, r2
+ 8028c00:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c04:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c08:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -32(r4)
+ 8028c0c:	21fff817 	ldw	r7,-32(r4)
+      add   r2, r7, r2
+ 8028c10:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c14:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c18:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -28(r4)
+ 8028c1c:	21fff917 	ldw	r7,-28(r4)
+      add   r2, r7, r2
+ 8028c20:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c24:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c28:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -24(r4)
+ 8028c2c:	21fffa17 	ldw	r7,-24(r4)
+      add   r2, r7, r2
+ 8028c30:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c34:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c38:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -20(r4)
+ 8028c3c:	21fffb17 	ldw	r7,-20(r4)
+      add   r2, r7, r2
+ 8028c40:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c44:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c48:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -16(r4)
+ 8028c4c:	21fffc17 	ldw	r7,-16(r4)
+      add   r2, r7, r2
+ 8028c50:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c54:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c58:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -12(r4)
+ 8028c5c:	21fffd17 	ldw	r7,-12(r4)
+      add   r2, r7, r2
+ 8028c60:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c64:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c68:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -8(r4)
+ 8028c6c:	21fffe17 	ldw	r7,-8(r4)
+      add   r2, r7, r2
+ 8028c70:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c74:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c78:	418d883a 	add	r6,r8,r6
+
+      ldw   r7, -4(r4)
+ 8028c7c:	21ffff17 	ldw	r7,-4(r4)
+      add   r2, r7, r2
+ 8028c80:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028c84:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028c88:	418d883a 	add	r6,r8,r6
+
+08028c8c <loop0>:
+loop0:
+      subi  r5, r5, 16
+ 8028c8c:	297ffc04 	addi	r5,r5,-16
+      bge   r5, zero, loop
+ 8028c90:	283fbd0e 	bge	r5,zero,8028b88 <loop>
+/*
+ * process last halfword (if any)
+ */
+      beq   r9, zero, fold
+ 8028c94:	48000426 	beq	r9,zero,8028ca8 <fold>
+      ldhu  r7, 0(r4)
+ 8028c98:	21c0000b 	ldhu	r7,0(r4)
+      add   r2, r7, r2
+ 8028c9c:	3885883a 	add	r2,r7,r2
+      cmpltu r8, r2, r7
+ 8028ca0:	11d1803a 	cmpltu	r8,r2,r7
+      add   r6, r8, r6
+ 8028ca4:	418d883a 	add	r6,r8,r6
+
+08028ca8 <fold>:
+      
+fold:
+      srli  r7, r2, 16
+ 8028ca8:	100ed43a 	srli	r7,r2,16
+      andi  r2, r2, 0xffff
+ 8028cac:	10bfffcc 	andi	r2,r2,65535
+      add   r2, r7, r2		    /* add the upper and lower halfwords */
+ 8028cb0:	3885883a 	add	r2,r7,r2
+      add   r2, r6, r2		    /* add the carries */
+ 8028cb4:	3085883a 	add	r2,r6,r2
+/* the accumulator is 18 bits */
+      srli  r7, r2, 16
+ 8028cb8:	100ed43a 	srli	r7,r2,16
+      andi  r2, r2, 0xffff
+ 8028cbc:	10bfffcc 	andi	r2,r2,65535
+      add   r2, r7, r2		    /* add 2 carry bits to lower halfword */
+ 8028cc0:	3885883a 	add	r2,r7,r2
+/* the accumulator is 17 bits */
+      srli  r7, r2, 16
+ 8028cc4:	100ed43a 	srli	r7,r2,16
+      andi  r2, r2, 0xffff
+ 8028cc8:	10bfffcc 	andi	r2,r2,65535
+      add   r2, r7, r2		    /* add carry to lower halfword */
+ 8028ccc:	3885883a 	add	r2,r7,r2
+
+08028cd0 <done>:
+
+done:
+      ret			    		/* r2 = 16-bit checksum */
+ 8028cd0:	f800283a 	ret
+
+08028cd4 <dtrap>:
+void irq_Unmask(void);
+
+/* dtrap() - function to trap to debugger */
+void
+dtrap(void)
+{
+ 8028cd4:	defffe04 	addi	sp,sp,-8
+ 8028cd8:	dfc00115 	stw	ra,4(sp)
+ 8028cdc:	df000015 	stw	fp,0(sp)
+ 8028ce0:	d839883a 	mov	fp,sp
+   printf("dtrap - needs breakpoint\n");
+ 8028ce4:	01020174 	movhi	r4,2053
+ 8028ce8:	21298204 	addi	r4,r4,-23032
+ 8028cec:	8002d9c0 	call	8002d9c <puts>
+}
+ 8028cf0:	0001883a 	nop
+ 8028cf4:	e037883a 	mov	sp,fp
+ 8028cf8:	dfc00117 	ldw	ra,4(sp)
+ 8028cfc:	df000017 	ldw	fp,0(sp)
+ 8028d00:	dec00204 	addi	sp,sp,8
+ 8028d04:	f800283a 	ret
+
+08028d08 <kbhit>:
+
+int
+kbhit()
+{
+ 8028d08:	defffd04 	addi	sp,sp,-12
+ 8028d0c:	dfc00215 	stw	ra,8(sp)
+ 8028d10:	df000115 	stw	fp,4(sp)
+ 8028d14:	df000104 	addi	fp,sp,4
+   static int kbd_init = 0;
+   int   kb;
+   
+   if (!kbd_init)
+ 8028d18:	d0a07517 	ldw	r2,-32300(gp)
+ 8028d1c:	10000b1e 	bne	r2,zero,8028d4c <kbhit+0x44>
+      /* we really should read the flags, OR in O_NONBLOCK, and write
+       * the flags back to STDIN, but the NIOS-II/HAL implementation
+       * will only let us modify O_NONBLOCK and O_APPEND, so we'll
+       * just write the new flag value.
+       */
+      if (fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK) != 0)
+ 8028d20:	01900004 	movi	r6,16384
+ 8028d24:	01400104 	movi	r5,4
+ 8028d28:	0009883a 	mov	r4,zero
+ 8028d2c:	8038ed80 	call	8038ed8 <fcntl>
+ 8028d30:	10000426 	beq	r2,zero,8028d44 <kbhit+0x3c>
+      {
+         printf("F_SETFL failed.\n");
+ 8028d34:	01020174 	movhi	r4,2053
+ 8028d38:	21298904 	addi	r4,r4,-23004
+ 8028d3c:	8002d9c0 	call	8002d9c <puts>
+         dtrap();
+ 8028d40:	8028cd40 	call	8028cd4 <dtrap>
+      }
+      kbd_init = 1; 
+ 8028d44:	00800044 	movi	r2,1
+ 8028d48:	d0a07515 	stw	r2,-32300(gp)
+   }
+
+   /* we have to do a read to see if there is a character available.
+    * we save the character, if there was one, to be read later. */
+   if (kb_last == EOF)
+ 8028d4c:	d0a01a17 	ldw	r2,-32664(gp)
+ 8028d50:	10bfffd8 	cmpnei	r2,r2,-1
+ 8028d54:	1000081e 	bne	r2,zero,8028d78 <kbhit+0x70>
+   {
+      kb = getchar();
+ 8028d58:	8002c380 	call	8002c38 <getchar>
+ 8028d5c:	e0bfff15 	stw	r2,-4(fp)
+      if (kb < 0)       /* any error means no character present */
+ 8028d60:	e0bfff17 	ldw	r2,-4(fp)
+ 8028d64:	1000020e 	bge	r2,zero,8028d70 <kbhit+0x68>
+         return (FALSE);
+ 8028d68:	0005883a 	mov	r2,zero
+ 8028d6c:	00000306 	br	8028d7c <kbhit+0x74>
+         
+      /* there was a character, and we read it. */
+      kb_last = kb;
+ 8028d70:	e0bfff17 	ldw	r2,-4(fp)
+ 8028d74:	d0a01a15 	stw	r2,-32664(gp)
+   }
+
+   return (TRUE);
+ 8028d78:	00800044 	movi	r2,1
+}
+ 8028d7c:	e037883a 	mov	sp,fp
+ 8028d80:	dfc00117 	ldw	ra,4(sp)
+ 8028d84:	df000017 	ldw	fp,0(sp)
+ 8028d88:	dec00204 	addi	sp,sp,8
+ 8028d8c:	f800283a 	ret
+
+08028d90 <getch>:
+
+int 
+getch()
+{
+ 8028d90:	defffd04 	addi	sp,sp,-12
+ 8028d94:	dfc00215 	stw	ra,8(sp)
+ 8028d98:	df000115 	stw	fp,4(sp)
+ 8028d9c:	df000104 	addi	fp,sp,4
+int chr;
+
+   if(kb_last != EOF)
+ 8028da0:	d0a01a17 	ldw	r2,-32664(gp)
+ 8028da4:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8028da8:	1000051e 	bne	r2,zero,8028dc0 <getch+0x30>
+   {
+      chr = kb_last;
+ 8028dac:	d0a01a17 	ldw	r2,-32664(gp)
+ 8028db0:	e0bfff15 	stw	r2,-4(fp)
+      kb_last = EOF;
+ 8028db4:	00bfffc4 	movi	r2,-1
+ 8028db8:	d0a01a15 	stw	r2,-32664(gp)
+ 8028dbc:	00000206 	br	8028dc8 <getch+0x38>
+   }
+   else
+      chr = getchar();
+ 8028dc0:	8002c380 	call	8002c38 <getchar>
+ 8028dc4:	e0bfff15 	stw	r2,-4(fp)
+
+   return chr;
+ 8028dc8:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8028dcc:	e037883a 	mov	sp,fp
+ 8028dd0:	dfc00117 	ldw	ra,4(sp)
+ 8028dd4:	df000017 	ldw	fp,0(sp)
+ 8028dd8:	dec00204 	addi	sp,sp,8
+ 8028ddc:	f800283a 	ret
+
+08028de0 <clock_init>:
+int OS_TPS;
+int cticks_factor;
+int cticks_initialized = 0;
+
+void clock_init(void)
+{
+ 8028de0:	deffff04 	addi	sp,sp,-4
+ 8028de4:	df000015 	stw	fp,0(sp)
+ 8028de8:	d839883a 	mov	fp,sp
+   OS_TPS = OS_TICKS_PER_SEC;
+ 8028dec:	00801904 	movi	r2,100
+ 8028df0:	d0a07715 	stw	r2,-32292(gp)
+   cticks_factor = 0;
+ 8028df4:	d0207615 	stw	zero,-32296(gp)
+   cticks = 0;
+ 8028df8:	d0207d15 	stw	zero,-32268(gp)
+   cticks_initialized = 1;
+ 8028dfc:	00800044 	movi	r2,1
+ 8028e00:	d0a07215 	stw	r2,-32312(gp)
+}
+ 8028e04:	0001883a 	nop
+ 8028e08:	e037883a 	mov	sp,fp
+ 8028e0c:	df000017 	ldw	fp,0(sp)
+ 8028e10:	dec00104 	addi	sp,sp,4
+ 8028e14:	f800283a 	ret
+
+08028e18 <clock_c>:
+
+/* undo effects of clock_init (i.e. restore ISR vector) 
+ * NO OP since using RTOS's timer.
+ */
+void clock_c(void)
+{
+ 8028e18:	deffff04 	addi	sp,sp,-4
+ 8028e1c:	df000015 	stw	fp,0(sp)
+ 8028e20:	d839883a 	mov	fp,sp
+   /* null */ ;
+}
+ 8028e24:	0001883a 	nop
+ 8028e28:	e037883a 	mov	sp,fp
+ 8028e2c:	df000017 	ldw	fp,0(sp)
+ 8028e30:	dec00104 	addi	sp,sp,4
+ 8028e34:	f800283a 	ret
+
+08028e38 <cticks_hook>:
+ * Use the uCOS-II/Altera HAL BSP's timer and scale cticks as per TPS.
+ */
+
+void
+cticks_hook(void)
+{
+ 8028e38:	deffff04 	addi	sp,sp,-4
+ 8028e3c:	df000015 	stw	fp,0(sp)
+ 8028e40:	d839883a 	mov	fp,sp
+   if (cticks_initialized) 
+ 8028e44:	d0a07217 	ldw	r2,-32312(gp)
+ 8028e48:	10000d26 	beq	r2,zero,8028e80 <cticks_hook+0x48>
+   {
+      cticks_factor += TPS;
+ 8028e4c:	d0a07617 	ldw	r2,-32296(gp)
+ 8028e50:	10801904 	addi	r2,r2,100
+ 8028e54:	d0a07615 	stw	r2,-32296(gp)
+      if (cticks_factor >= OS_TPS)
+ 8028e58:	d0e07617 	ldw	r3,-32296(gp)
+ 8028e5c:	d0a07717 	ldw	r2,-32292(gp)
+ 8028e60:	18800716 	blt	r3,r2,8028e80 <cticks_hook+0x48>
+      {
+         cticks++;
+ 8028e64:	d0a07d17 	ldw	r2,-32268(gp)
+ 8028e68:	10800044 	addi	r2,r2,1
+ 8028e6c:	d0a07d15 	stw	r2,-32268(gp)
+         cticks_factor -= OS_TPS;
+ 8028e70:	d0e07617 	ldw	r3,-32296(gp)
+ 8028e74:	d0a07717 	ldw	r2,-32292(gp)
+ 8028e78:	1885c83a 	sub	r2,r3,r2
+ 8028e7c:	d0a07615 	stw	r2,-32296(gp)
+#ifdef USE_LCD
+         update_display();
+#endif
+      }
+   }
+}
+ 8028e80:	0001883a 	nop
+ 8028e84:	e037883a 	mov	sp,fp
+ 8028e88:	df000017 	ldw	fp,0(sp)
+ 8028e8c:	dec00104 	addi	sp,sp,4
+ 8028e90:	f800283a 	ret
+
+08028e94 <irq_Mask>:
+ * ENTER_CRIT_SECTION() and enable them in EXIT_CRIT_SECTION()
+ * because calls to ENTER_CRIT_SECTION() can be nested."
+ */
+void
+irq_Mask(void)
+{
+ 8028e94:	defffd04 	addi	sp,sp,-12
+ 8028e98:	df000215 	stw	fp,8(sp)
+ 8028e9c:	df000204 	addi	fp,sp,8
+  NIOS2_READ_STATUS (context);
+ 8028ea0:	0005303a 	rdctl	r2,status
+ 8028ea4:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8028ea8:	e0fffe17 	ldw	r3,-8(fp)
+ 8028eac:	00bfff84 	movi	r2,-2
+ 8028eb0:	1884703a 	and	r2,r3,r2
+ 8028eb4:	1001703a 	wrctl	status,r2
+  return context;
+ 8028eb8:	e0bffe17 	ldw	r2,-8(fp)
+   alt_irq_context  local_cpu_statusreg;
+
+   local_cpu_statusreg = alt_irq_disable_all();
+ 8028ebc:	e0bfff15 	stw	r2,-4(fp)
+	
+   if (++irq_level == 1)
+ 8028ec0:	d0a07317 	ldw	r2,-32308(gp)
+ 8028ec4:	10800044 	addi	r2,r2,1
+ 8028ec8:	d0a07315 	stw	r2,-32308(gp)
+ 8028ecc:	d0a07317 	ldw	r2,-32308(gp)
+ 8028ed0:	10800058 	cmpnei	r2,r2,1
+ 8028ed4:	1000021e 	bne	r2,zero,8028ee0 <irq_Mask+0x4c>
+   {
+      cpu_statusreg = local_cpu_statusreg;
+ 8028ed8:	e0bfff17 	ldw	r2,-4(fp)
+ 8028edc:	d0a07415 	stw	r2,-32304(gp)
+   }
+}
+ 8028ee0:	0001883a 	nop
+ 8028ee4:	e037883a 	mov	sp,fp
+ 8028ee8:	df000017 	ldw	fp,0(sp)
+ 8028eec:	dec00104 	addi	sp,sp,4
+ 8028ef0:	f800283a 	ret
+
+08028ef4 <irq_Unmask>:
+
+
+/* Re-Enable Interrupts */
+void
+irq_Unmask(void)
+{
+ 8028ef4:	defffe04 	addi	sp,sp,-8
+ 8028ef8:	df000115 	stw	fp,4(sp)
+ 8028efc:	df000104 	addi	fp,sp,4
+   if (--irq_level == 0)
+ 8028f00:	d0a07317 	ldw	r2,-32308(gp)
+ 8028f04:	10bfffc4 	addi	r2,r2,-1
+ 8028f08:	d0a07315 	stw	r2,-32308(gp)
+ 8028f0c:	d0a07317 	ldw	r2,-32308(gp)
+ 8028f10:	1000041e 	bne	r2,zero,8028f24 <irq_Unmask+0x30>
+   {
+      alt_irq_enable_all(cpu_statusreg);
+ 8028f14:	d0a07417 	ldw	r2,-32304(gp)
+ 8028f18:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8028f1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8028f20:	1001703a 	wrctl	status,r2
+   }
+}
+ 8028f24:	0001883a 	nop
+ 8028f28:	e037883a 	mov	sp,fp
+ 8028f2c:	df000017 	ldw	fp,0(sp)
+ 8028f30:	dec00104 	addi	sp,sp,4
+ 8028f34:	f800283a 	ret
+
+08028f38 <LOCK_NET_RESOURCE>:
+extern void irq_Mask(void);
+extern void irq_Unmask(void);
+
+void
+LOCK_NET_RESOURCE(int resid)
+{
+ 8028f38:	defffb04 	addi	sp,sp,-20
+ 8028f3c:	dfc00415 	stw	ra,16(sp)
+ 8028f40:	df000315 	stw	fp,12(sp)
+ 8028f44:	df000304 	addi	fp,sp,12
+ 8028f48:	e13ffd15 	stw	r4,-12(fp)
+   INT8U error = 0;
+ 8028f4c:	e03ffec5 	stb	zero,-5(fp)
+   int   errct = 0;
+ 8028f50:	e03fff15 	stw	zero,-4(fp)
+
+   if ((0 <= resid) && (resid <= MAX_RESID))
+ 8028f54:	e0bffd17 	ldw	r2,-12(fp)
+ 8028f58:	10002016 	blt	r2,zero,8028fdc <LOCK_NET_RESOURCE+0xa4>
+ 8028f5c:	e0bffd17 	ldw	r2,-12(fp)
+ 8028f60:	10800408 	cmpgei	r2,r2,16
+ 8028f64:	10001d1e 	bne	r2,zero,8028fdc <LOCK_NET_RESOURCE+0xa4>
+   {
+      do
+      {
+         OSSemPend(resid_semaphore[resid], 0, &error);
+ 8028f68:	e0bffd17 	ldw	r2,-12(fp)
+ 8028f6c:	100690ba 	slli	r3,r2,2
+ 8028f70:	008201b4 	movhi	r2,2054
+ 8028f74:	1885883a 	add	r2,r3,r2
+ 8028f78:	10b85b17 	ldw	r2,-7828(r2)
+ 8028f7c:	e0fffec4 	addi	r3,fp,-5
+ 8028f80:	180d883a 	mov	r6,r3
+ 8028f84:	000b883a 	mov	r5,zero
+ 8028f88:	1009883a 	mov	r4,r2
+ 8028f8c:	8015a600 	call	8015a60 <OSSemPend>
+         /* 
+          * Sometimes we get a "timeout" error even though we passed a zero
+          * to indicate we'll wait forever. When this happens, try again:
+          */
+         if ((error == 10) && (++errct > 1000))
+ 8028f90:	e0bffec3 	ldbu	r2,-5(fp)
+ 8028f94:	10803fcc 	andi	r2,r2,255
+ 8028f98:	10800298 	cmpnei	r2,r2,10
+ 8028f9c:	10000a1e 	bne	r2,zero,8028fc8 <LOCK_NET_RESOURCE+0x90>
+ 8028fa0:	e0bfff17 	ldw	r2,-4(fp)
+ 8028fa4:	10800044 	addi	r2,r2,1
+ 8028fa8:	e0bfff15 	stw	r2,-4(fp)
+ 8028fac:	e0bfff17 	ldw	r2,-4(fp)
+ 8028fb0:	1080fa50 	cmplti	r2,r2,1001
+ 8028fb4:	1000041e 	bne	r2,zero,8028fc8 <LOCK_NET_RESOURCE+0x90>
+         {
+            panic("lock NET");   /* fatal */
+ 8028fb8:	01020174 	movhi	r4,2053
+ 8028fbc:	21298d04 	addi	r4,r4,-22988
+ 8028fc0:	80271780 	call	8027178 <panic>
+ 8028fc4:	00000606 	br	8028fe0 <LOCK_NET_RESOURCE+0xa8>
+            return;
+         }
+      } while (error == 10);
+ 8028fc8:	e0bffec3 	ldbu	r2,-5(fp)
+ 8028fcc:	10803fcc 	andi	r2,r2,255
+ 8028fd0:	108002a0 	cmpeqi	r2,r2,10
+ 8028fd4:	103fe41e 	bne	r2,zero,8028f68 <LOCK_NET_RESOURCE+0x30>
+   if ((0 <= resid) && (resid <= MAX_RESID))
+ 8028fd8:	00000106 	br	8028fe0 <LOCK_NET_RESOURCE+0xa8>
+   }
+   else
+      dtrap();
+ 8028fdc:	8028cd40 	call	8028cd4 <dtrap>
+}
+ 8028fe0:	e037883a 	mov	sp,fp
+ 8028fe4:	dfc00117 	ldw	ra,4(sp)
+ 8028fe8:	df000017 	ldw	fp,0(sp)
+ 8028fec:	dec00204 	addi	sp,sp,8
+ 8028ff0:	f800283a 	ret
+
+08028ff4 <UNLOCK_NET_RESOURCE>:
+
+void
+UNLOCK_NET_RESOURCE(int resid)
+{
+ 8028ff4:	defffc04 	addi	sp,sp,-16
+ 8028ff8:	dfc00315 	stw	ra,12(sp)
+ 8028ffc:	df000215 	stw	fp,8(sp)
+ 8029000:	df000204 	addi	fp,sp,8
+ 8029004:	e13ffe15 	stw	r4,-8(fp)
+   INT8U error = 0;
+ 8029008:	e03fffc5 	stb	zero,-1(fp)
+
+   if ((0 <= resid) && (resid <= MAX_RESID))
+ 802900c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029010:	10001116 	blt	r2,zero,8029058 <UNLOCK_NET_RESOURCE+0x64>
+ 8029014:	e0bffe17 	ldw	r2,-8(fp)
+ 8029018:	10800408 	cmpgei	r2,r2,16
+ 802901c:	10000e1e 	bne	r2,zero,8029058 <UNLOCK_NET_RESOURCE+0x64>
+   {
+      error = OSSemPost(resid_semaphore[resid]);
+ 8029020:	e0bffe17 	ldw	r2,-8(fp)
+ 8029024:	100690ba 	slli	r3,r2,2
+ 8029028:	008201b4 	movhi	r2,2054
+ 802902c:	1885883a 	add	r2,r3,r2
+ 8029030:	10b85b17 	ldw	r2,-7828(r2)
+ 8029034:	1009883a 	mov	r4,r2
+ 8029038:	8015d840 	call	8015d84 <OSSemPost>
+ 802903c:	e0bfffc5 	stb	r2,-1(fp)
+      if (error != OS_NO_ERR)
+ 8029040:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8029044:	10000526 	beq	r2,zero,802905c <UNLOCK_NET_RESOURCE+0x68>
+      {
+         panic("unlock NET");
+ 8029048:	01020174 	movhi	r4,2053
+ 802904c:	21299004 	addi	r4,r4,-22976
+ 8029050:	80271780 	call	8027178 <panic>
+      if (error != OS_NO_ERR)
+ 8029054:	00000106 	br	802905c <UNLOCK_NET_RESOURCE+0x68>
+      }
+   }
+   else
+      dtrap();
+ 8029058:	8028cd40 	call	8028cd4 <dtrap>
+}
+ 802905c:	0001883a 	nop
+ 8029060:	e037883a 	mov	sp,fp
+ 8029064:	dfc00117 	ldw	ra,4(sp)
+ 8029068:	df000017 	ldw	fp,0(sp)
+ 802906c:	dec00204 	addi	sp,sp,8
+ 8029070:	f800283a 	ret
+
+08029074 <TK_NEWTASK>:
+extern long     nettick_wakes;
+
+
+int
+TK_NEWTASK(struct inet_taskinfo * nettask)
+{
+ 8029074:	deffee04 	addi	sp,sp,-72
+ 8029078:	dfc01115 	stw	ra,68(sp)
+ 802907c:	df001015 	stw	fp,64(sp)
+ 8029080:	df001004 	addi	fp,sp,64
+ 8029084:	e13ff515 	stw	r4,-44(fp)
+   INT8U    error;
+   OS_STK * stack;
+
+   stack = (OS_STK*)npalloc(nettask->stacksize);
+ 8029088:	e0bff517 	ldw	r2,-44(fp)
+ 802908c:	10800417 	ldw	r2,16(r2)
+ 8029090:	1009883a 	mov	r4,r2
+ 8029094:	802982c0 	call	802982c <npalloc>
+ 8029098:	e0bfff15 	stw	r2,-4(fp)
+   if(!stack)
+ 802909c:	e0bfff17 	ldw	r2,-4(fp)
+ 80290a0:	1000031e 	bne	r2,zero,80290b0 <TK_NEWTASK+0x3c>
+      panic("stack alloc");
+ 80290a4:	01020174 	movhi	r4,2053
+ 80290a8:	21299304 	addi	r4,r4,-22964
+ 80290ac:	80271780 	call	8027178 <panic>
+
+#if OS_TASK_CREATE_EXT_EN > 0
+   error = OSTaskCreateExt(
+ 80290b0:	e0bff517 	ldw	r2,-44(fp)
+ 80290b4:	12000217 	ldw	r8,8(r2)
+      nettask->entry,
+      NULL,
+      stack + (nettask->stacksize/sizeof(OS_STK)) - 1,
+ 80290b8:	e0bff517 	ldw	r2,-44(fp)
+ 80290bc:	10800417 	ldw	r2,16(r2)
+ 80290c0:	1007883a 	mov	r3,r2
+ 80290c4:	00bfff04 	movi	r2,-4
+ 80290c8:	1884703a 	and	r2,r3,r2
+ 80290cc:	10bfff04 	addi	r2,r2,-4
+   error = OSTaskCreateExt(
+ 80290d0:	e0ffff17 	ldw	r3,-4(fp)
+ 80290d4:	188b883a 	add	r5,r3,r2
+      nettask->priority,
+ 80290d8:	e0bff517 	ldw	r2,-44(fp)
+ 80290dc:	10800317 	ldw	r2,12(r2)
+   error = OSTaskCreateExt(
+ 80290e0:	11803fcc 	andi	r6,r2,255
+      nettask->priority,
+ 80290e4:	e0bff517 	ldw	r2,-44(fp)
+ 80290e8:	10800317 	ldw	r2,12(r2)
+   error = OSTaskCreateExt(
+ 80290ec:	10bfffcc 	andi	r2,r2,65535
+      stack, 
+      (INT32U)nettask->stacksize / sizeof(OS_STK),
+ 80290f0:	e0fff517 	ldw	r3,-44(fp)
+ 80290f4:	18c00417 	ldw	r3,16(r3)
+   error = OSTaskCreateExt(
+ 80290f8:	1806d0ba 	srli	r3,r3,2
+ 80290fc:	010000c4 	movi	r4,3
+ 8029100:	d9000415 	stw	r4,16(sp)
+ 8029104:	d8000315 	stw	zero,12(sp)
+ 8029108:	d8c00215 	stw	r3,8(sp)
+ 802910c:	e0ffff17 	ldw	r3,-4(fp)
+ 8029110:	d8c00115 	stw	r3,4(sp)
+ 8029114:	d8800015 	stw	r2,0(sp)
+ 8029118:	300f883a 	mov	r7,r6
+ 802911c:	280d883a 	mov	r6,r5
+ 8029120:	000b883a 	mov	r5,zero
+ 8029124:	4009883a 	mov	r4,r8
+ 8029128:	801664c0 	call	801664c <OSTaskCreateExt>
+ 802912c:	e0bffec5 	stb	r2,-5(fp)
+      stack + (nettask->stacksize/sizeof(OS_STK)) - 1,
+      nettask->priority);
+#endif
+   /* If we go here, then there's another task using our priority */
+   /* Tell the user and exit with an error */
+   if (error == OS_PRIO_EXIST)
+ 8029130:	e0bffec3 	ldbu	r2,-5(fp)
+ 8029134:	10803fcc 	andi	r2,r2,255
+ 8029138:	10800a18 	cmpnei	r2,r2,40
+ 802913c:	10001c1e 	bne	r2,zero,80291b0 <TK_NEWTASK+0x13c>
+   { 
+     char curr_task[OS_TASK_NAME_SIZE];
+     INT8U err;
+     OSTaskNameGet(nettask->priority, (INT8U*)curr_task, &err);
+ 8029140:	e0bff517 	ldw	r2,-44(fp)
+ 8029144:	10800317 	ldw	r2,12(r2)
+ 8029148:	10803fcc 	andi	r2,r2,255
+ 802914c:	e13ffe84 	addi	r4,fp,-6
+ 8029150:	e0fff684 	addi	r3,fp,-38
+ 8029154:	200d883a 	mov	r6,r4
+ 8029158:	180b883a 	mov	r5,r3
+ 802915c:	1009883a 	mov	r4,r2
+ 8029160:	8016c2c0 	call	8016c2c <OSTaskNameGet>
+     curr_task[OS_TASK_NAME_SIZE-1]=0;
+ 8029164:	e03ffe45 	stb	zero,-7(fp)
+    
+     printf("Priority requested for task \"%s\" (Prio:%d) conflicts with "\
+ 8029168:	e0bff517 	ldw	r2,-44(fp)
+ 802916c:	10c00117 	ldw	r3,4(r2)
+ 8029170:	e0bff517 	ldw	r2,-44(fp)
+ 8029174:	11000317 	ldw	r4,12(r2)
+ 8029178:	e0bff517 	ldw	r2,-44(fp)
+ 802917c:	10800317 	ldw	r2,12(r2)
+ 8029180:	e17ff684 	addi	r5,fp,-38
+ 8029184:	d8800015 	stw	r2,0(sp)
+ 8029188:	280f883a 	mov	r7,r5
+ 802918c:	200d883a 	mov	r6,r4
+ 8029190:	180b883a 	mov	r5,r3
+ 8029194:	01020174 	movhi	r4,2053
+ 8029198:	21299604 	addi	r4,r4,-22952
+ 802919c:	8002c780 	call	8002c78 <printf>
+            "already running task \"%s\" (Prio: %d)\n",
+             nettask->name, nettask->priority, curr_task, nettask->priority);
+             
+     printf("You may wish to check your task priority settings in "\
+ 80291a0:	01020174 	movhi	r4,2053
+ 80291a4:	2129ae04 	addi	r4,r4,-22856
+ 80291a8:	8002d9c0 	call	8002d9c <puts>
+ 80291ac:	00002006 	br	8029230 <TK_NEWTASK+0x1bc>
+            "\"<bsp path>\\iniche\\src\\h\\nios2\\ipport.h\" against "\
+            "the priority settings in your application and recompile.\n\n");
+   }
+   else if (error == OS_PRIO_INVALID)
+ 80291b0:	e0bffec3 	ldbu	r2,-5(fp)
+ 80291b4:	10803fcc 	andi	r2,r2,255
+ 80291b8:	10800a98 	cmpnei	r2,r2,42
+ 80291bc:	10000e1e 	bne	r2,zero,80291f8 <TK_NEWTASK+0x184>
+   {
+     printf("Priority requested for task \"%s\" (Prio:%d) exceeds "\
+ 80291c0:	e0bff517 	ldw	r2,-44(fp)
+ 80291c4:	10c00117 	ldw	r3,4(r2)
+ 80291c8:	e0bff517 	ldw	r2,-44(fp)
+ 80291cc:	10800317 	ldw	r2,12(r2)
+ 80291d0:	01c00504 	movi	r7,20
+ 80291d4:	100d883a 	mov	r6,r2
+ 80291d8:	180b883a 	mov	r5,r3
+ 80291dc:	01020174 	movhi	r4,2053
+ 80291e0:	2129d604 	addi	r4,r4,-22696
+ 80291e4:	8002c780 	call	8002c78 <printf>
+            "available priority levels in the system (OS_LOWEST_PRIO = %d)\n\n",
+             nettask->name, nettask->priority, OS_LOWEST_PRIO);
+             
+     printf("Please modify the tasks priority level, or modify the "\
+ 80291e8:	01020174 	movhi	r4,2053
+ 80291ec:	2129f304 	addi	r4,r4,-22580
+ 80291f0:	8002d9c0 	call	8002d9c <puts>
+ 80291f4:	00000e06 	br	8029230 <TK_NEWTASK+0x1bc>
+            "\"Lowest assignable priority\" setting in the MicroC/OS-II "\
+            "component\n");
+   }
+   else if (error != OS_NO_ERR)
+ 80291f8:	e0bffec3 	ldbu	r2,-5(fp)
+ 80291fc:	10803fcc 	andi	r2,r2,255
+ 8029200:	10000b26 	beq	r2,zero,8029230 <TK_NEWTASK+0x1bc>
+   {                          /* All other errors are fatal */
+      printf("Task create error /(MicroC/OS-II error code:%d/) on %s\n",
+ 8029204:	e0bffec3 	ldbu	r2,-5(fp)
+ 8029208:	10c03fcc 	andi	r3,r2,255
+ 802920c:	e0bff517 	ldw	r2,-44(fp)
+ 8029210:	10800117 	ldw	r2,4(r2)
+ 8029214:	100d883a 	mov	r6,r2
+ 8029218:	180b883a 	mov	r5,r3
+ 802921c:	01020174 	movhi	r4,2053
+ 8029220:	212a1204 	addi	r4,r4,-22456
+ 8029224:	8002c780 	call	8002c78 <printf>
+             error, nettask->name);
+      return (-1);
+ 8029228:	00bfffc4 	movi	r2,-1
+ 802922c:	00001c06 	br	80292a0 <TK_NEWTASK+0x22c>
+   }
+
+   /* Include the task name, so that uc/osII (os aware) debuggers can
+    * display it.
+    */
+   OSTaskNameSet(nettask->priority, (INT8U*)&nettask->name[0], &error);
+ 8029230:	e0bff517 	ldw	r2,-44(fp)
+ 8029234:	10800317 	ldw	r2,12(r2)
+ 8029238:	10c03fcc 	andi	r3,r2,255
+ 802923c:	e0bff517 	ldw	r2,-44(fp)
+ 8029240:	10800117 	ldw	r2,4(r2)
+ 8029244:	e13ffec4 	addi	r4,fp,-5
+ 8029248:	200d883a 	mov	r6,r4
+ 802924c:	100b883a 	mov	r5,r2
+ 8029250:	1809883a 	mov	r4,r3
+ 8029254:	8016d640 	call	8016d64 <OSTaskNameSet>
+
+   nettask->stackbase = (char*)stack;
+ 8029258:	e0bff517 	ldw	r2,-44(fp)
+ 802925c:	e0ffff17 	ldw	r3,-4(fp)
+ 8029260:	10c00515 	stw	r3,20(r2)
+   *nettask->tk_ptr = (INT8U)nettask->priority;  
+ 8029264:	e0bff517 	ldw	r2,-44(fp)
+ 8029268:	10c00317 	ldw	r3,12(r2)
+ 802926c:	e0bff517 	ldw	r2,-44(fp)
+ 8029270:	10800017 	ldw	r2,0(r2)
+ 8029274:	10c00005 	stb	r3,0(r2)
+
+   printf("Created \"%s\" task (Prio: %d)\n",
+ 8029278:	e0bff517 	ldw	r2,-44(fp)
+ 802927c:	10c00117 	ldw	r3,4(r2)
+ 8029280:	e0bff517 	ldw	r2,-44(fp)
+ 8029284:	10800317 	ldw	r2,12(r2)
+ 8029288:	100d883a 	mov	r6,r2
+ 802928c:	180b883a 	mov	r5,r3
+ 8029290:	01020174 	movhi	r4,2053
+ 8029294:	212a2004 	addi	r4,r4,-22400
+ 8029298:	8002c780 	call	8002c78 <printf>
+         (char *)nettask->name, nettask->priority);
+
+   return (0);
+ 802929c:	0005883a 	mov	r2,zero
+}
+ 80292a0:	e037883a 	mov	sp,fp
+ 80292a4:	dfc00117 	ldw	ra,4(sp)
+ 80292a8:	df000017 	ldw	fp,0(sp)
+ 80292ac:	dec00204 	addi	sp,sp,8
+ 80292b0:	f800283a 	ret
+
+080292b4 <wait_app_sem>:
+ * event (e.g., configuration inputs from user, initiation of a new session,
+ * or a periodic timeout notification.
+ */
+void
+wait_app_sem(unsigned long semid)
+{
+ 80292b4:	defffb04 	addi	sp,sp,-20
+ 80292b8:	dfc00415 	stw	ra,16(sp)
+ 80292bc:	df000315 	stw	fp,12(sp)
+ 80292c0:	df000304 	addi	fp,sp,12
+ 80292c4:	e13ffd15 	stw	r4,-12(fp)
+   INT8U error = 0;
+ 80292c8:	e03ffec5 	stb	zero,-5(fp)
+   int   errct = 0;
+ 80292cc:	e03fff15 	stw	zero,-4(fp)
+
+   if ((0 <= semid) && (semid <= MAX_SEMID))
+ 80292d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80292d4:	108001a8 	cmpgeui	r2,r2,6
+ 80292d8:	10001d1e 	bne	r2,zero,8029350 <wait_app_sem+0x9c>
+   {
+      do
+      {
+         OSSemPend(app_semaphore[semid], 0, &error);
+ 80292dc:	e0bffd17 	ldw	r2,-12(fp)
+ 80292e0:	100690ba 	slli	r3,r2,2
+ 80292e4:	008201b4 	movhi	r2,2054
+ 80292e8:	1885883a 	add	r2,r3,r2
+ 80292ec:	10b86b17 	ldw	r2,-7764(r2)
+ 80292f0:	e0fffec4 	addi	r3,fp,-5
+ 80292f4:	180d883a 	mov	r6,r3
+ 80292f8:	000b883a 	mov	r5,zero
+ 80292fc:	1009883a 	mov	r4,r2
+ 8029300:	8015a600 	call	8015a60 <OSSemPend>
+         /* 
+          * Sometimes we get a "timeout" error even though we passed a zero
+          * to indicate we'll wait forever. When this happens, try again:
+          */
+         if ((error == 10) && (++errct > 1000))
+ 8029304:	e0bffec3 	ldbu	r2,-5(fp)
+ 8029308:	10803fcc 	andi	r2,r2,255
+ 802930c:	10800298 	cmpnei	r2,r2,10
+ 8029310:	10000a1e 	bne	r2,zero,802933c <wait_app_sem+0x88>
+ 8029314:	e0bfff17 	ldw	r2,-4(fp)
+ 8029318:	10800044 	addi	r2,r2,1
+ 802931c:	e0bfff15 	stw	r2,-4(fp)
+ 8029320:	e0bfff17 	ldw	r2,-4(fp)
+ 8029324:	1080fa50 	cmplti	r2,r2,1001
+ 8029328:	1000041e 	bne	r2,zero,802933c <wait_app_sem+0x88>
+         {
+            panic("lock NET");   /* fatal */
+ 802932c:	01020174 	movhi	r4,2053
+ 8029330:	21298d04 	addi	r4,r4,-22988
+ 8029334:	80271780 	call	8027178 <panic>
+ 8029338:	00000606 	br	8029354 <wait_app_sem+0xa0>
+            return;
+         }
+      } while (error == 10);
+ 802933c:	e0bffec3 	ldbu	r2,-5(fp)
+ 8029340:	10803fcc 	andi	r2,r2,255
+ 8029344:	108002a0 	cmpeqi	r2,r2,10
+ 8029348:	103fe41e 	bne	r2,zero,80292dc <wait_app_sem+0x28>
+ 802934c:	00000106 	br	8029354 <wait_app_sem+0xa0>
+   }
+   else
+      dtrap();
+ 8029350:	8028cd40 	call	8028cd4 <dtrap>
+}
+ 8029354:	e037883a 	mov	sp,fp
+ 8029358:	dfc00117 	ldw	ra,4(sp)
+ 802935c:	df000017 	ldw	fp,0(sp)
+ 8029360:	dec00204 	addi	sp,sp,8
+ 8029364:	f800283a 	ret
+
+08029368 <post_app_sem>:
+ * notification. It signals the corresponding application event.
+ */
+
+void
+post_app_sem(unsigned long semid)
+{
+ 8029368:	defffc04 	addi	sp,sp,-16
+ 802936c:	dfc00315 	stw	ra,12(sp)
+ 8029370:	df000215 	stw	fp,8(sp)
+ 8029374:	df000204 	addi	fp,sp,8
+ 8029378:	e13ffe15 	stw	r4,-8(fp)
+   INT8U error;
+
+   if ((0 <= semid) && (semid <= MAX_SEMID))
+ 802937c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029380:	108001a8 	cmpgeui	r2,r2,6
+ 8029384:	10000e1e 	bne	r2,zero,80293c0 <post_app_sem+0x58>
+   {
+      error = OSSemPost(app_semaphore[semid]);
+ 8029388:	e0bffe17 	ldw	r2,-8(fp)
+ 802938c:	100690ba 	slli	r3,r2,2
+ 8029390:	008201b4 	movhi	r2,2054
+ 8029394:	1885883a 	add	r2,r3,r2
+ 8029398:	10b86b17 	ldw	r2,-7764(r2)
+ 802939c:	1009883a 	mov	r4,r2
+ 80293a0:	8015d840 	call	8015d84 <OSSemPost>
+ 80293a4:	e0bfffc5 	stb	r2,-1(fp)
+      if (error != OS_NO_ERR)
+ 80293a8:	e0bfffc3 	ldbu	r2,-1(fp)
+ 80293ac:	10000526 	beq	r2,zero,80293c4 <post_app_sem+0x5c>
+      {
+         panic("unlock NET");
+ 80293b0:	01020174 	movhi	r4,2053
+ 80293b4:	21299004 	addi	r4,r4,-22976
+ 80293b8:	80271780 	call	8027178 <panic>
+      }
+   }
+   else
+      dtrap();
+}
+ 80293bc:	00000106 	br	80293c4 <post_app_sem+0x5c>
+      dtrap();
+ 80293c0:	8028cd40 	call	8028cd4 <dtrap>
+}
+ 80293c4:	0001883a 	nop
+ 80293c8:	e037883a 	mov	sp,fp
+ 80293cc:	dfc00117 	ldw	ra,4(sp)
+ 80293d0:	df000017 	ldw	fp,0(sp)
+ 80293d4:	dec00204 	addi	sp,sp,8
+ 80293d8:	f800283a 	ret
+
+080293dc <alt_iniche_init>:
+#ifndef SUPERLOOP
+
+extern OS_EVENT *resid_semaphore[MAX_RESID+1];
+
+void alt_iniche_init(void)
+{
+ 80293dc:	defffd04 	addi	sp,sp,-12
+ 80293e0:	dfc00215 	stw	ra,8(sp)
+ 80293e4:	df000115 	stw	fp,4(sp)
+ 80293e8:	df000104 	addi	fp,sp,4
+   int i;
+
+   /* initialize the npalloc() heap semaphore */
+   mheap_sem_ptr = OSSemCreate(1);
+ 80293ec:	01000044 	movi	r4,1
+ 80293f0:	80157740 	call	8015774 <OSSemCreate>
+ 80293f4:	d0a07f15 	stw	r2,-32260(gp)
+   if (!mheap_sem_ptr)
+ 80293f8:	d0a07f17 	ldw	r2,-32260(gp)
+ 80293fc:	1000031e 	bne	r2,zero,802940c <alt_iniche_init+0x30>
+      panic("mheap_sem_ptr create err"); 
+ 8029400:	01020174 	movhi	r4,2053
+ 8029404:	212a2804 	addi	r4,r4,-22368
+ 8029408:	80271780 	call	8027178 <panic>
+
+   rcvdq_sem_ptr = OSSemCreate(0);
+ 802940c:	0009883a 	mov	r4,zero
+ 8029410:	80157740 	call	8015774 <OSSemCreate>
+ 8029414:	d0a08015 	stw	r2,-32256(gp)
+   if (!rcvdq_sem_ptr)
+ 8029418:	d0a08017 	ldw	r2,-32256(gp)
+ 802941c:	1000031e 	bne	r2,zero,802942c <alt_iniche_init+0x50>
+      panic("rcvdq_sem_ptr create err"); 
+ 8029420:	01020174 	movhi	r4,2053
+ 8029424:	212a2f04 	addi	r4,r4,-22340
+ 8029428:	80271780 	call	8027178 <panic>
+
+#ifdef OS_PREEMPTIVE
+   for (i = 0; i <= MAX_RESID; i++)
+ 802942c:	e03fff15 	stw	zero,-4(fp)
+ 8029430:	00001406 	br	8029484 <alt_iniche_init+0xa8>
+   {
+      resid_semaphore[i] = OSSemCreate(1);
+ 8029434:	01000044 	movi	r4,1
+ 8029438:	80157740 	call	8015774 <OSSemCreate>
+ 802943c:	1009883a 	mov	r4,r2
+ 8029440:	e0bfff17 	ldw	r2,-4(fp)
+ 8029444:	100690ba 	slli	r3,r2,2
+ 8029448:	008201b4 	movhi	r2,2054
+ 802944c:	1885883a 	add	r2,r3,r2
+ 8029450:	11385b15 	stw	r4,-7828(r2)
+      if (!resid_semaphore[i])
+ 8029454:	e0bfff17 	ldw	r2,-4(fp)
+ 8029458:	100690ba 	slli	r3,r2,2
+ 802945c:	008201b4 	movhi	r2,2054
+ 8029460:	1885883a 	add	r2,r3,r2
+ 8029464:	10b85b17 	ldw	r2,-7828(r2)
+ 8029468:	1000031e 	bne	r2,zero,8029478 <alt_iniche_init+0x9c>
+         panic("resid_semaphore create err");  
+ 802946c:	01020174 	movhi	r4,2053
+ 8029470:	212a3604 	addi	r4,r4,-22312
+ 8029474:	80271780 	call	8027178 <panic>
+   for (i = 0; i <= MAX_RESID; i++)
+ 8029478:	e0bfff17 	ldw	r2,-4(fp)
+ 802947c:	10800044 	addi	r2,r2,1
+ 8029480:	e0bfff15 	stw	r2,-4(fp)
+ 8029484:	e0bfff17 	ldw	r2,-4(fp)
+ 8029488:	10800410 	cmplti	r2,r2,16
+ 802948c:	103fe91e 	bne	r2,zero,8029434 <alt_iniche_init+0x58>
+   }
+   for (i = 0; i <= MAX_SEMID; i++)
+ 8029490:	e03fff15 	stw	zero,-4(fp)
+ 8029494:	00001406 	br	80294e8 <alt_iniche_init+0x10c>
+   {
+      app_semaphore[i] = OSSemCreate(1);
+ 8029498:	01000044 	movi	r4,1
+ 802949c:	80157740 	call	8015774 <OSSemCreate>
+ 80294a0:	1009883a 	mov	r4,r2
+ 80294a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80294a8:	100690ba 	slli	r3,r2,2
+ 80294ac:	008201b4 	movhi	r2,2054
+ 80294b0:	1885883a 	add	r2,r3,r2
+ 80294b4:	11386b15 	stw	r4,-7764(r2)
+      if (!app_semaphore[i])
+ 80294b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80294bc:	100690ba 	slli	r3,r2,2
+ 80294c0:	008201b4 	movhi	r2,2054
+ 80294c4:	1885883a 	add	r2,r3,r2
+ 80294c8:	10b86b17 	ldw	r2,-7764(r2)
+ 80294cc:	1000031e 	bne	r2,zero,80294dc <alt_iniche_init+0x100>
+         panic("app_semaphore create err");  
+ 80294d0:	01020174 	movhi	r4,2053
+ 80294d4:	212a3d04 	addi	r4,r4,-22284
+ 80294d8:	80271780 	call	8027178 <panic>
+   for (i = 0; i <= MAX_SEMID; i++)
+ 80294dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80294e0:	10800044 	addi	r2,r2,1
+ 80294e4:	e0bfff15 	stw	r2,-4(fp)
+ 80294e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80294ec:	10800190 	cmplti	r2,r2,6
+ 80294f0:	103fe91e 	bne	r2,zero,8029498 <alt_iniche_init+0xbc>
+
+#ifndef TCPWAKE_RTOS
+   /* 
+    * clear global_TCPwakeup_set
+    */
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 80294f4:	e03fff15 	stw	zero,-4(fp)
+ 80294f8:	00001e06 	br	8029574 <alt_iniche_init+0x198>
+   {
+      global_TCPwakeup_set[i].ctick = 0;
+ 80294fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8029500:	10c00324 	muli	r3,r2,12
+ 8029504:	008201b4 	movhi	r2,2054
+ 8029508:	1885883a 	add	r2,r3,r2
+ 802950c:	10381f15 	stw	zero,-8068(r2)
+      global_TCPwakeup_set[i].soc_event = NULL;
+ 8029510:	e0bfff17 	ldw	r2,-4(fp)
+ 8029514:	10c00324 	muli	r3,r2,12
+ 8029518:	008201b4 	movhi	r2,2054
+ 802951c:	1885883a 	add	r2,r3,r2
+ 8029520:	10382015 	stw	zero,-8064(r2)
+      global_TCPwakeup_set[i].semaphore = OSSemCreate(0);
+ 8029524:	0009883a 	mov	r4,zero
+ 8029528:	80157740 	call	8015774 <OSSemCreate>
+ 802952c:	1009883a 	mov	r4,r2
+ 8029530:	e0bfff17 	ldw	r2,-4(fp)
+ 8029534:	10c00324 	muli	r3,r2,12
+ 8029538:	008201b4 	movhi	r2,2054
+ 802953c:	1885883a 	add	r2,r3,r2
+ 8029540:	11382115 	stw	r4,-8060(r2)
+      if (!global_TCPwakeup_set[i].semaphore)
+ 8029544:	e0bfff17 	ldw	r2,-4(fp)
+ 8029548:	10c00324 	muli	r3,r2,12
+ 802954c:	008201b4 	movhi	r2,2054
+ 8029550:	1885883a 	add	r2,r3,r2
+ 8029554:	10b82117 	ldw	r2,-8060(r2)
+ 8029558:	1000031e 	bne	r2,zero,8029568 <alt_iniche_init+0x18c>
+         panic("globwake_semaphore create err");  
+ 802955c:	01020174 	movhi	r4,2053
+ 8029560:	212a4404 	addi	r4,r4,-22256
+ 8029564:	80271780 	call	8027178 <panic>
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+ 8029568:	e0bfff17 	ldw	r2,-4(fp)
+ 802956c:	10800044 	addi	r2,r2,1
+ 8029570:	e0bfff15 	stw	r2,-4(fp)
+ 8029574:	e0bfff17 	ldw	r2,-4(fp)
+ 8029578:	10800510 	cmplti	r2,r2,20
+ 802957c:	103fdf1e 	bne	r2,zero,80294fc <alt_iniche_init+0x120>
+   }
+   global_TCPwakeup_setIndx = 0;
+ 8029580:	d0207c15 	stw	zero,-32272(gp)
+#endif  /* TCPWAKE_RTOS */
+}
+ 8029584:	0001883a 	nop
+ 8029588:	e037883a 	mov	sp,fp
+ 802958c:	dfc00117 	ldw	ra,4(sp)
+ 8029590:	df000017 	ldw	fp,0(sp)
+ 8029594:	dec00204 	addi	sp,sp,8
+ 8029598:	f800283a 	ret
+
+0802959c <pre_task_setup>:
+ * Return NULL if OK, else brief error message
+ */
+
+char *
+pre_task_setup()
+{
+ 802959c:	deffff04 	addi	sp,sp,-4
+ 80295a0:	df000015 	stw	fp,0(sp)
+ 80295a4:	d839883a 	mov	fp,sp
+   write_leds(0);
+   write_7seg_raw(0x0000);
+#endif
+
+   /* preset buffer counts; may be overridden from command line */
+   bigbufs = MAXBIGPKTS;
+ 80295a8:	00800784 	movi	r2,30
+ 80295ac:	d0a01815 	stw	r2,-32672(gp)
+   lilbufs = MAXLILPKTS;
+ 80295b0:	00800784 	movi	r2,30
+ 80295b4:	d0a01615 	stw	r2,-32680(gp)
+   bigbufsiz = BIGBUFSIZE;
+ 80295b8:	00818004 	movi	r2,1536
+ 80295bc:	d0a01915 	stw	r2,-32668(gp)
+   lilbufsiz = LILBUFSIZE;
+ 80295c0:	00802004 	movi	r2,128
+ 80295c4:	d0a01715 	stw	r2,-32676(gp)
+
+   /* Install callback to prep_armintcp from prep_ifaces() */
+   port_prep = prep_armintcp;
+ 80295c8:	008200f4 	movhi	r2,2051
+ 80295cc:	10a58204 	addi	r2,r2,-27128
+ 80295d0:	d0a09615 	stw	r2,-32168(gp)
+#endif   /* NOTDEF */
+
+#endif   /* USE_PPP */
+
+
+   return NULL;
+ 80295d4:	0005883a 	mov	r2,zero
+}
+ 80295d8:	e037883a 	mov	sp,fp
+ 80295dc:	df000017 	ldw	fp,0(sp)
+ 80295e0:	dec00104 	addi	sp,sp,4
+ 80295e4:	f800283a 	ret
+
+080295e8 <post_task_setup>:
+ * Return NULL if OK, else brief error message
+ */
+
+char *
+post_task_setup()
+{
+ 80295e8:	deffff04 	addi	sp,sp,-4
+ 80295ec:	df000015 	stw	fp,0(sp)
+ 80295f0:	d839883a 	mov	fp,sp
+   return NULL;
+ 80295f4:	0005883a 	mov	r2,zero
+}
+ 80295f8:	e037883a 	mov	sp,fp
+ 80295fc:	df000017 	ldw	fp,0(sp)
+ 8029600:	dec00104 	addi	sp,sp,4
+ 8029604:	f800283a 	ret
+
+08029608 <prep_armintcp>:
+
+#endif  /* INCLUDE_NVPARMS */
+
+int 
+prep_armintcp(int ifaces_found)
+{
+ 8029608:	defffd04 	addi	sp,sp,-12
+ 802960c:	dfc00215 	stw	ra,8(sp)
+ 8029610:	df000115 	stw	fp,4(sp)
+ 8029614:	df000104 	addi	fp,sp,4
+ 8029618:	e13fff15 	stw	r4,-4(fp)
+ * Call iniche_devices_init, in alt_iniche_dev.c, 
+ * to step through all devices and all their respective
+ * low-level initialization routines.
+ */
+#ifdef ALT_INICHE
+   ifaces_found = iniche_devices_init(ifaces_found);
+ 802961c:	e13fff17 	ldw	r4,-4(fp)
+ 8029620:	8022aa80 	call	8022aa8 <iniche_devices_init>
+ 8029624:	e0bfff15 	stw	r2,-4(fp)
+
+#ifdef USE_SLIP
+   ifaces_found = prep_slip(ifaces_found);
+#endif
+
+   return ifaces_found;
+ 8029628:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802962c:	e037883a 	mov	sp,fp
+ 8029630:	dfc00117 	ldw	ra,4(sp)
+ 8029634:	df000017 	ldw	fp,0(sp)
+ 8029638:	dec00204 	addi	sp,sp,8
+ 802963c:	f800283a 	ret
+
+08029640 <npalloc_base>:
+#endif
+
+
+char *
+npalloc_base(unsigned size, int cacheable)
+{
+ 8029640:	defff804 	addi	sp,sp,-32
+ 8029644:	dfc00715 	stw	ra,28(sp)
+ 8029648:	df000615 	stw	fp,24(sp)
+ 802964c:	df000604 	addi	fp,sp,24
+ 8029650:	e13ffb15 	stw	r4,-20(fp)
+ 8029654:	e17ffa15 	stw	r5,-24(fp)
+char * ptr;
+void *(*alloc_rtn)(size_t size) = cacheable ? malloc : alt_uncached_malloc;
+ 8029658:	e0bffa17 	ldw	r2,-24(fp)
+ 802965c:	10000326 	beq	r2,zero,802966c <npalloc_base+0x2c>
+ 8029660:	00820134 	movhi	r2,2052
+ 8029664:	108b2604 	addi	r2,r2,11416
+ 8029668:	00000206 	br	8029674 <npalloc_base+0x34>
+ 802966c:	00820134 	movhi	r2,2052
+ 8029670:	10a02904 	addi	r2,r2,-32604
+ 8029674:	e0bffe15 	stw	r2,-8(fp)
+#ifdef UCOS_II
+   INT8U err;
+#endif
+
+#ifdef UCOS_II
+   OSSemPend(mheap_sem_ptr, 0, &err);
+ 8029678:	d0a07f17 	ldw	r2,-32260(gp)
+ 802967c:	e0fffcc4 	addi	r3,fp,-13
+ 8029680:	180d883a 	mov	r6,r3
+ 8029684:	000b883a 	mov	r5,zero
+ 8029688:	1009883a 	mov	r4,r2
+ 802968c:	8015a600 	call	8015a60 <OSSemPend>
+   if(err)
+ 8029690:	e0bffcc3 	ldbu	r2,-13(fp)
+ 8029694:	10803fcc 	andi	r2,r2,255
+ 8029698:	10001626 	beq	r2,zero,80296f4 <npalloc_base+0xb4>
+   {
+      int errct = 0;
+ 802969c:	e03fff15 	stw	zero,-4(fp)
+
+      /* sometimes we get a "timeout" error even though we passed a zero
+       * to indicate we'll wait forever. When this happens, try again:
+       */
+      while(err == 10)
+ 80296a0:	00001006 	br	80296e4 <npalloc_base+0xa4>
+      {
+         if(errct++ > 1000)
+ 80296a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80296a8:	10c00044 	addi	r3,r2,1
+ 80296ac:	e0ffff15 	stw	r3,-4(fp)
+ 80296b0:	1080fa50 	cmplti	r2,r2,1001
+ 80296b4:	1000051e 	bne	r2,zero,80296cc <npalloc_base+0x8c>
+         {
+            panic("npalloc");    /* fatal? */
+ 80296b8:	01020174 	movhi	r4,2053
+ 80296bc:	212a4c04 	addi	r4,r4,-22224
+ 80296c0:	80271780 	call	8027178 <panic>
+            return NULL;
+ 80296c4:	0005883a 	mov	r2,zero
+ 80296c8:	00001b06 	br	8029738 <npalloc_base+0xf8>
+         }
+         OSSemPend(mheap_sem_ptr, 0, &err);
+ 80296cc:	d0a07f17 	ldw	r2,-32260(gp)
+ 80296d0:	e0fffcc4 	addi	r3,fp,-13
+ 80296d4:	180d883a 	mov	r6,r3
+ 80296d8:	000b883a 	mov	r5,zero
+ 80296dc:	1009883a 	mov	r4,r2
+ 80296e0:	8015a600 	call	8015a60 <OSSemPend>
+      while(err == 10)
+ 80296e4:	e0bffcc3 	ldbu	r2,-13(fp)
+ 80296e8:	10803fcc 	andi	r2,r2,255
+ 80296ec:	108002a0 	cmpeqi	r2,r2,10
+ 80296f0:	103fec1e 	bne	r2,zero,80296a4 <npalloc_base+0x64>
+#endif
+
+#ifdef   MEM_WRAPPERS
+   ptr = wrap_alloc(size, alloc_rtn);
+#else
+   ptr = (*alloc_rtn)(size);
+ 80296f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80296f8:	e13ffb17 	ldw	r4,-20(fp)
+ 80296fc:	103ee83a 	callr	r2
+ 8029700:	e0bffd15 	stw	r2,-12(fp)
+#endif
+
+#ifdef UCOS_II 
+   err = OSSemPost(mheap_sem_ptr);
+ 8029704:	d0a07f17 	ldw	r2,-32260(gp)
+ 8029708:	1009883a 	mov	r4,r2
+ 802970c:	8015d840 	call	8015d84 <OSSemPost>
+ 8029710:	e0bffcc5 	stb	r2,-13(fp)
+#endif
+   
+   if(!ptr)
+ 8029714:	e0bffd17 	ldw	r2,-12(fp)
+ 8029718:	1000021e 	bne	r2,zero,8029724 <npalloc_base+0xe4>
+      return NULL;
+ 802971c:	0005883a 	mov	r2,zero
+ 8029720:	00000506 	br	8029738 <npalloc_base+0xf8>
+
+   MEMSET(ptr, 0, size);
+ 8029724:	e1bffb17 	ldw	r6,-20(fp)
+ 8029728:	000b883a 	mov	r5,zero
+ 802972c:	e13ffd17 	ldw	r4,-12(fp)
+ 8029730:	80088e40 	call	80088e4 <memset>
+   return ptr;      
+ 8029734:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8029738:	e037883a 	mov	sp,fp
+ 802973c:	dfc00117 	ldw	ra,4(sp)
+ 8029740:	df000017 	ldw	fp,0(sp)
+ 8029744:	dec00204 	addi	sp,sp,8
+ 8029748:	f800283a 	ret
+
+0802974c <npfree_base>:
+
+void
+npfree_base(void *ptr, int cacheable)
+{
+ 802974c:	defff904 	addi	sp,sp,-28
+ 8029750:	dfc00615 	stw	ra,24(sp)
+ 8029754:	df000515 	stw	fp,20(sp)
+ 8029758:	df000504 	addi	fp,sp,20
+ 802975c:	e13ffc15 	stw	r4,-16(fp)
+ 8029760:	e17ffb15 	stw	r5,-20(fp)
+   void (*free_rtn)(void *ptr) = cacheable ? free : alt_uncached_free;
+ 8029764:	e0bffb17 	ldw	r2,-20(fp)
+ 8029768:	10000326 	beq	r2,zero,8029778 <npfree_base+0x2c>
+ 802976c:	00820134 	movhi	r2,2052
+ 8029770:	108b2a04 	addi	r2,r2,11432
+ 8029774:	00000206 	br	8029780 <npfree_base+0x34>
+ 8029778:	00820134 	movhi	r2,2052
+ 802977c:	10a01804 	addi	r2,r2,-32672
+ 8029780:	e0bffe15 	stw	r2,-8(fp)
+#ifdef UCOS_II
+   INT8U err;
+
+   OSSemPend(mheap_sem_ptr, 0, &err);
+ 8029784:	d0a07f17 	ldw	r2,-32260(gp)
+ 8029788:	e0fffdc4 	addi	r3,fp,-9
+ 802978c:	180d883a 	mov	r6,r3
+ 8029790:	000b883a 	mov	r5,zero
+ 8029794:	1009883a 	mov	r4,r2
+ 8029798:	8015a600 	call	8015a60 <OSSemPend>
+   if (err)
+ 802979c:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80297a0:	10803fcc 	andi	r2,r2,255
+ 80297a4:	10001526 	beq	r2,zero,80297fc <npfree_base+0xb0>
+   {
+      int errct = 0;
+ 80297a8:	e03fff15 	stw	zero,-4(fp)
+
+      /* sometimes we get a "timeout" error even though we passed a zero
+       * to indicate we'll wait forever. When this happens, try again:
+       */
+      while (err == 10)
+ 80297ac:	00000f06 	br	80297ec <npfree_base+0xa0>
+      {
+         if (errct++ > 1000)
+ 80297b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80297b4:	10c00044 	addi	r3,r2,1
+ 80297b8:	e0ffff15 	stw	r3,-4(fp)
+ 80297bc:	1080fa50 	cmplti	r2,r2,1001
+ 80297c0:	1000041e 	bne	r2,zero,80297d4 <npfree_base+0x88>
+         {
+            panic("npfree");    /* fatal? */
+ 80297c4:	01020174 	movhi	r4,2053
+ 80297c8:	212a4e04 	addi	r4,r4,-22216
+ 80297cc:	80271780 	call	8027178 <panic>
+ 80297d0:	00001106 	br	8029818 <npfree_base+0xcc>
+            return;
+         }
+         OSSemPend(mheap_sem_ptr, 0, &err);
+ 80297d4:	d0a07f17 	ldw	r2,-32260(gp)
+ 80297d8:	e0fffdc4 	addi	r3,fp,-9
+ 80297dc:	180d883a 	mov	r6,r3
+ 80297e0:	000b883a 	mov	r5,zero
+ 80297e4:	1009883a 	mov	r4,r2
+ 80297e8:	8015a600 	call	8015a60 <OSSemPend>
+      while (err == 10)
+ 80297ec:	e0bffdc3 	ldbu	r2,-9(fp)
+ 80297f0:	10803fcc 	andi	r2,r2,255
+ 80297f4:	108002a0 	cmpeqi	r2,r2,10
+ 80297f8:	103fed1e 	bne	r2,zero,80297b0 <npfree_base+0x64>
+   }
+   
+#ifdef   MEM_WRAPPERS
+   wrap_free((char*)ptr, free_rtn);
+#else
+   (*free_rtn)(ptr);
+ 80297fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8029800:	e13ffc17 	ldw	r4,-16(fp)
+ 8029804:	103ee83a 	callr	r2
+#endif
+
+   err = OSSemPost(mheap_sem_ptr);
+ 8029808:	d0a07f17 	ldw	r2,-32260(gp)
+ 802980c:	1009883a 	mov	r4,r2
+ 8029810:	8015d840 	call	8015d84 <OSSemPost>
+ 8029814:	e0bffdc5 	stb	r2,-9(fp)
+#else
+   (*free_rtn)(ptr);
+#endif
+#endif
+
+}
+ 8029818:	e037883a 	mov	sp,fp
+ 802981c:	dfc00117 	ldw	ra,4(sp)
+ 8029820:	df000017 	ldw	fp,0(sp)
+ 8029824:	dec00204 	addi	sp,sp,8
+ 8029828:	f800283a 	ret
+
+0802982c <npalloc>:
+
+char *
+npalloc(unsigned size)
+{
+ 802982c:	defffd04 	addi	sp,sp,-12
+ 8029830:	dfc00215 	stw	ra,8(sp)
+ 8029834:	df000115 	stw	fp,4(sp)
+ 8029838:	df000104 	addi	fp,sp,4
+ 802983c:	e13fff15 	stw	r4,-4(fp)
+   return npalloc_base(size, 1);
+ 8029840:	01400044 	movi	r5,1
+ 8029844:	e13fff17 	ldw	r4,-4(fp)
+ 8029848:	80296400 	call	8029640 <npalloc_base>
+}
+ 802984c:	e037883a 	mov	sp,fp
+ 8029850:	dfc00117 	ldw	ra,4(sp)
+ 8029854:	df000017 	ldw	fp,0(sp)
+ 8029858:	dec00204 	addi	sp,sp,8
+ 802985c:	f800283a 	ret
+
+08029860 <npfree>:
+
+void
+npfree(void *ptr)
+{
+ 8029860:	defffd04 	addi	sp,sp,-12
+ 8029864:	dfc00215 	stw	ra,8(sp)
+ 8029868:	df000115 	stw	fp,4(sp)
+ 802986c:	df000104 	addi	fp,sp,4
+ 8029870:	e13fff15 	stw	r4,-4(fp)
+   if(ptr) {
+ 8029874:	e0bfff17 	ldw	r2,-4(fp)
+ 8029878:	10000326 	beq	r2,zero,8029888 <npfree+0x28>
+      npfree_base(ptr, 1);
+ 802987c:	01400044 	movi	r5,1
+ 8029880:	e13fff17 	ldw	r4,-4(fp)
+ 8029884:	802974c0 	call	802974c <npfree_base>
+   }
+}
+ 8029888:	0001883a 	nop
+ 802988c:	e037883a 	mov	sp,fp
+ 8029890:	dfc00117 	ldw	ra,4(sp)
+ 8029894:	df000017 	ldw	fp,0(sp)
+ 8029898:	dec00204 	addi	sp,sp,8
+ 802989c:	f800283a 	ret
+
+080298a0 <ncpalloc>:
+ * contains macro definitions that assign specific memory
+ * allocation calls to these routines.
+ */
+#ifdef ALT_INICHE
+char * ncpalloc(unsigned size)
+{
+ 80298a0:	defffd04 	addi	sp,sp,-12
+ 80298a4:	dfc00215 	stw	ra,8(sp)
+ 80298a8:	df000115 	stw	fp,4(sp)
+ 80298ac:	df000104 	addi	fp,sp,4
+ 80298b0:	e13fff15 	stw	r4,-4(fp)
+   return npalloc_base(size, 0);
+ 80298b4:	000b883a 	mov	r5,zero
+ 80298b8:	e13fff17 	ldw	r4,-4(fp)
+ 80298bc:	80296400 	call	8029640 <npalloc_base>
+}
+ 80298c0:	e037883a 	mov	sp,fp
+ 80298c4:	dfc00117 	ldw	ra,4(sp)
+ 80298c8:	df000017 	ldw	fp,0(sp)
+ 80298cc:	dec00204 	addi	sp,sp,8
+ 80298d0:	f800283a 	ret
+
+080298d4 <ncpfree>:
+
+void ncpfree(void *ptr)
+{
+ 80298d4:	defffd04 	addi	sp,sp,-12
+ 80298d8:	dfc00215 	stw	ra,8(sp)
+ 80298dc:	df000115 	stw	fp,4(sp)
+ 80298e0:	df000104 	addi	fp,sp,4
+ 80298e4:	e13fff15 	stw	r4,-4(fp)
+   if(ptr) {
+ 80298e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80298ec:	10000326 	beq	r2,zero,80298fc <ncpfree+0x28>
+      npfree_base(ptr, 0);
+ 80298f0:	000b883a 	mov	r5,zero
+ 80298f4:	e13fff17 	ldw	r4,-4(fp)
+ 80298f8:	802974c0 	call	802974c <npfree_base>
+   }
+}
+ 80298fc:	0001883a 	nop
+ 8029900:	e037883a 	mov	sp,fp
+ 8029904:	dfc00117 	ldw	ra,4(sp)
+ 8029908:	df000017 	ldw	fp,0(sp)
+ 802990c:	dec00204 	addi	sp,sp,8
+ 8029910:	f800283a 	ret
+
+08029914 <pffindtype>:
+ * RETURNS: 
+ */
+
+struct protosw *  
+pffindtype(int domain, int type)
+{
+ 8029914:	defffc04 	addi	sp,sp,-16
+ 8029918:	dfc00315 	stw	ra,12(sp)
+ 802991c:	df000215 	stw	fp,8(sp)
+ 8029920:	df000204 	addi	fp,sp,8
+ 8029924:	e13fff15 	stw	r4,-4(fp)
+ 8029928:	e17ffe15 	stw	r5,-8(fp)
+
+   /* check that the passed domain is vaid for the build */
+   if (domain != AF_INET)
+ 802992c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029930:	108000a0 	cmpeqi	r2,r2,2
+ 8029934:	1000031e 	bne	r2,zero,8029944 <pffindtype+0x30>
+   {
+#ifdef IP_V6
+      if(domain != AF_INET6)
+#endif
+      {
+         dtrap();    /* programming error */
+ 8029938:	8028cd40 	call	8028cd4 <dtrap>
+         return NULL;
+ 802993c:	0005883a 	mov	r2,zero
+ 8029940:	00001306 	br	8029990 <pffindtype+0x7c>
+      }
+   }
+
+   if (type == SOCK_STREAM)
+ 8029944:	e0bffe17 	ldw	r2,-8(fp)
+ 8029948:	10800058 	cmpnei	r2,r2,1
+ 802994c:	1000031e 	bne	r2,zero,802995c <pffindtype+0x48>
+      return &tcp_protosw;
+ 8029950:	00820174 	movhi	r2,2053
+ 8029954:	10b1f804 	addi	r2,r2,-14368
+ 8029958:	00000d06 	br	8029990 <pffindtype+0x7c>
+#ifdef UDP_SOCKETS
+   else if(type == SOCK_DGRAM)
+ 802995c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029960:	10800098 	cmpnei	r2,r2,2
+ 8029964:	1000031e 	bne	r2,zero,8029974 <pffindtype+0x60>
+      return &udp_protosw;
+ 8029968:	00820174 	movhi	r2,2053
+ 802996c:	10b1fe04 	addi	r2,r2,-14344
+ 8029970:	00000706 	br	8029990 <pffindtype+0x7c>
+#endif   /* UDP_SOCKETS */
+#ifdef IP_RAW
+   else if(type == SOCK_RAW)
+ 8029974:	e0bffe17 	ldw	r2,-8(fp)
+ 8029978:	108000d8 	cmpnei	r2,r2,3
+ 802997c:	1000031e 	bne	r2,zero,802998c <pffindtype+0x78>
+      return &rawip_protosw;
+ 8029980:	00820174 	movhi	r2,2053
+ 8029984:	10b20404 	addi	r2,r2,-14320
+ 8029988:	00000106 	br	8029990 <pffindtype+0x7c>
+#endif  /* IP_RAW */
+   else
+      return NULL;
+ 802998c:	0005883a 	mov	r2,zero
+}
+ 8029990:	e037883a 	mov	sp,fp
+ 8029994:	dfc00117 	ldw	ra,4(sp)
+ 8029998:	df000017 	ldw	fp,0(sp)
+ 802999c:	dec00204 	addi	sp,sp,8
+ 80299a0:	f800283a 	ret
+
+080299a4 <pffindproto>:
+ * RETURNS: 
+ */
+
+struct protosw *  
+pffindproto(int domain, int protocol, int type)
+{
+ 80299a4:	defffb04 	addi	sp,sp,-20
+ 80299a8:	dfc00415 	stw	ra,16(sp)
+ 80299ac:	df000315 	stw	fp,12(sp)
+ 80299b0:	df000304 	addi	fp,sp,12
+ 80299b4:	e13fff15 	stw	r4,-4(fp)
+ 80299b8:	e17ffe15 	stw	r5,-8(fp)
+ 80299bc:	e1bffd15 	stw	r6,-12(fp)
+#ifdef IP_RAW
+   if (type == SOCK_RAW)
+ 80299c0:	e0bffd17 	ldw	r2,-12(fp)
+ 80299c4:	108000d8 	cmpnei	r2,r2,3
+ 80299c8:	1000041e 	bne	r2,zero,80299dc <pffindproto+0x38>
+      return(pffindtype(domain, type));
+ 80299cc:	e17ffd17 	ldw	r5,-12(fp)
+ 80299d0:	e13fff17 	ldw	r4,-4(fp)
+ 80299d4:	80299140 	call	8029914 <pffindtype>
+ 80299d8:	00002006 	br	8029a5c <pffindproto+0xb8>
+#endif
+
+   switch (protocol)
+ 80299dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80299e0:	108001a0 	cmpeqi	r2,r2,6
+ 80299e4:	1000061e 	bne	r2,zero,8029a00 <pffindproto+0x5c>
+ 80299e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80299ec:	10800460 	cmpeqi	r2,r2,17
+ 80299f0:	1000091e 	bne	r2,zero,8029a18 <pffindproto+0x74>
+ 80299f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80299f8:	10001026 	beq	r2,zero,8029a3c <pffindproto+0x98>
+ 80299fc:	00000c06 	br	8029a30 <pffindproto+0x8c>
+   {
+#ifdef BSD_SOCKETS
+   case IPPROTO_TCP:
+      if (type == SOCK_STREAM)
+ 8029a00:	e0bffd17 	ldw	r2,-12(fp)
+ 8029a04:	10800058 	cmpnei	r2,r2,1
+ 8029a08:	10000e26 	beq	r2,zero,8029a44 <pffindproto+0xa0>
+         break;
+      /* IPPROTO_TCP protocol on non-SOCK_STREAM type socket */
+      dtrap();
+ 8029a0c:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 8029a10:	0005883a 	mov	r2,zero
+ 8029a14:	00001106 	br	8029a5c <pffindproto+0xb8>
+   case IPPROTO_UDP:
+      if (type == SOCK_DGRAM)
+ 8029a18:	e0bffd17 	ldw	r2,-12(fp)
+ 8029a1c:	10800098 	cmpnei	r2,r2,2
+ 8029a20:	10000a26 	beq	r2,zero,8029a4c <pffindproto+0xa8>
+         break;
+      /* IPPROTO_UDP protocol on non-SOCK_DGRAM type socket */
+      dtrap();
+ 8029a24:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 8029a28:	0005883a 	mov	r2,zero
+ 8029a2c:	00000b06 	br	8029a5c <pffindproto+0xb8>
+   case 0:
+      /* let protocol default based on socket type */
+      break;
+   default:
+      /* unknown/unsupported protocol on socket */
+      dtrap();
+ 8029a30:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 8029a34:	0005883a 	mov	r2,zero
+ 8029a38:	00000806 	br	8029a5c <pffindproto+0xb8>
+      break;
+ 8029a3c:	0001883a 	nop
+ 8029a40:	00000306 	br	8029a50 <pffindproto+0xac>
+         break;
+ 8029a44:	0001883a 	nop
+ 8029a48:	00000106 	br	8029a50 <pffindproto+0xac>
+         break;
+ 8029a4c:	0001883a 	nop
+   }
+   return(pffindtype(domain, type));   /* map to findtype */
+ 8029a50:	e17ffd17 	ldw	r5,-12(fp)
+ 8029a54:	e13fff17 	ldw	r4,-4(fp)
+ 8029a58:	80299140 	call	8029914 <pffindtype>
+}
+ 8029a5c:	e037883a 	mov	sp,fp
+ 8029a60:	dfc00117 	ldw	ra,4(sp)
+ 8029a64:	df000017 	ldw	fp,0(sp)
+ 8029a68:	dec00204 	addi	sp,sp,8
+ 8029a6c:	f800283a 	ret
+
+08029a70 <m_getnbuf>:
+ * RETURNS: 
+ */
+
+struct mbuf *  
+m_getnbuf(int type, int len)
+{
+ 8029a70:	defffa04 	addi	sp,sp,-24
+ 8029a74:	dfc00515 	stw	ra,20(sp)
+ 8029a78:	df000415 	stw	fp,16(sp)
+ 8029a7c:	df000404 	addi	fp,sp,16
+ 8029a80:	e13ffd15 	stw	r4,-12(fp)
+ 8029a84:	e17ffc15 	stw	r5,-16(fp)
+   struct mbuf *  m;
+   PACKET pkt = NULL;
+ 8029a88:	e03fff15 	stw	zero,-4(fp)
+
+#ifdef NPDEBUG
+   if (type < MT_RXDATA || type > MT_IFADDR)
+ 8029a8c:	e0bffd17 	ldw	r2,-12(fp)
+ 8029a90:	0080030e 	bge	zero,r2,8029aa0 <m_getnbuf+0x30>
+ 8029a94:	e0bffd17 	ldw	r2,-12(fp)
+ 8029a98:	10800390 	cmplti	r2,r2,14
+ 8029a9c:	1000011e 	bne	r2,zero,8029aa4 <m_getnbuf+0x34>
+   {
+      dtrap(); /* is this OK? */
+ 8029aa0:	8028cd40 	call	8028cd4 <dtrap>
+   }
+#endif
+
+   /* if caller has data (len >= 0), we need to allocate 
+    * a packet buffer; else all we need is the mbuf */
+   if (len != 0)
+ 8029aa4:	e0bffc17 	ldw	r2,-16(fp)
+ 8029aa8:	10000d26 	beq	r2,zero,8029ae0 <m_getnbuf+0x70>
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029aac:	01000084 	movi	r4,2
+ 8029ab0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pkt = pk_alloc(len + HDRSLEN);
+ 8029ab4:	e0bffc17 	ldw	r2,-16(fp)
+ 8029ab8:	10800e04 	addi	r2,r2,56
+ 8029abc:	1009883a 	mov	r4,r2
+ 8029ac0:	80284340 	call	8028434 <pk_alloc>
+ 8029ac4:	e0bfff15 	stw	r2,-4(fp)
+
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029ac8:	01000084 	movi	r4,2
+ 8029acc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      if (!pkt)
+ 8029ad0:	e0bfff17 	ldw	r2,-4(fp)
+ 8029ad4:	1000021e 	bne	r2,zero,8029ae0 <m_getnbuf+0x70>
+         return NULL;
+ 8029ad8:	0005883a 	mov	r2,zero
+ 8029adc:	00004106 	br	8029be4 <m_getnbuf+0x174>
+   }
+
+   m = (struct mbuf *)getq(&mfreeq);
+ 8029ae0:	010201b4 	movhi	r4,2054
+ 8029ae4:	21388a04 	addi	r4,r4,-7640
+ 8029ae8:	80288d80 	call	80288d8 <getq>
+ 8029aec:	e0bffe15 	stw	r2,-8(fp)
+   if (!m)
+ 8029af0:	e0bffe17 	ldw	r2,-8(fp)
+ 8029af4:	10000a1e 	bne	r2,zero,8029b20 <m_getnbuf+0xb0>
+   {
+      if (pkt) 
+ 8029af8:	e0bfff17 	ldw	r2,-4(fp)
+ 8029afc:	10000626 	beq	r2,zero,8029b18 <m_getnbuf+0xa8>
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029b00:	01000084 	movi	r4,2
+ 8029b04:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(pkt);
+ 8029b08:	e13fff17 	ldw	r4,-4(fp)
+ 8029b0c:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029b10:	01000084 	movi	r4,2
+ 8029b14:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      }
+      return NULL;
+ 8029b18:	0005883a 	mov	r2,zero
+ 8029b1c:	00003106 	br	8029be4 <m_getnbuf+0x174>
+   }
+   m->m_type = type;
+ 8029b20:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b24:	e0fffd17 	ldw	r3,-12(fp)
+ 8029b28:	10c00815 	stw	r3,32(r2)
+   if (len == 0)
+ 8029b2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8029b30:	1000071e 	bne	r2,zero,8029b50 <m_getnbuf+0xe0>
+   {
+      m->pkt = NULL;
+ 8029b34:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b38:	10000115 	stw	zero,4(r2)
+      m->m_base = NULL;    /* caller better fill these in! */
+ 8029b3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b40:	10000415 	stw	zero,16(r2)
+      m->m_memsz = 0;
+ 8029b44:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b48:	10000515 	stw	zero,20(r2)
+ 8029b4c:	00001506 	br	8029ba4 <m_getnbuf+0x134>
+   }
+   else
+   {
+      m->pkt = pkt;
+ 8029b50:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b54:	e0ffff17 	ldw	r3,-4(fp)
+ 8029b58:	10c00115 	stw	r3,4(r2)
+      /* set m_data to the part where tcp data should go */
+      m->m_base = m->m_data = pkt->nb_prot = pkt->nb_buff + HDRSLEN;
+ 8029b5c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029b60:	10800117 	ldw	r2,4(r2)
+ 8029b64:	10c00e04 	addi	r3,r2,56
+ 8029b68:	e0bfff17 	ldw	r2,-4(fp)
+ 8029b6c:	10c00315 	stw	r3,12(r2)
+ 8029b70:	e0bfff17 	ldw	r2,-4(fp)
+ 8029b74:	10c00317 	ldw	r3,12(r2)
+ 8029b78:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b7c:	10c00315 	stw	r3,12(r2)
+ 8029b80:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b84:	10c00317 	ldw	r3,12(r2)
+ 8029b88:	e0bffe17 	ldw	r2,-8(fp)
+ 8029b8c:	10c00415 	stw	r3,16(r2)
+      m->m_memsz = pkt->nb_blen - HDRSLEN;
+ 8029b90:	e0bfff17 	ldw	r2,-4(fp)
+ 8029b94:	10800217 	ldw	r2,8(r2)
+ 8029b98:	10fff204 	addi	r3,r2,-56
+ 8029b9c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029ba0:	10c00515 	stw	r3,20(r2)
+   }
+   m->m_len = 0;
+ 8029ba4:	e0bffe17 	ldw	r2,-8(fp)
+ 8029ba8:	10000215 	stw	zero,8(r2)
+   m->m_next = m->m_act = NULL;
+ 8029bac:	e0bffe17 	ldw	r2,-8(fp)
+ 8029bb0:	10000715 	stw	zero,28(r2)
+ 8029bb4:	e0bffe17 	ldw	r2,-8(fp)
+ 8029bb8:	10c00717 	ldw	r3,28(r2)
+ 8029bbc:	e0bffe17 	ldw	r2,-8(fp)
+ 8029bc0:	10c00615 	stw	r3,24(r2)
+   mbstat.allocs++;        /* maintain local statistics */
+ 8029bc4:	d0a08317 	ldw	r2,-32244(gp)
+ 8029bc8:	10800044 	addi	r2,r2,1
+ 8029bcc:	d0a08315 	stw	r2,-32244(gp)
+   putq(&mbufq, (qp)m);
+ 8029bd0:	e17ffe17 	ldw	r5,-8(fp)
+ 8029bd4:	010201b4 	movhi	r4,2054
+ 8029bd8:	21388504 	addi	r4,r4,-7660
+ 8029bdc:	80289900 	call	8028990 <putq>
+   return m;
+ 8029be0:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8029be4:	e037883a 	mov	sp,fp
+ 8029be8:	dfc00117 	ldw	ra,4(sp)
+ 8029bec:	df000017 	ldw	fp,0(sp)
+ 8029bf0:	dec00204 	addi	sp,sp,8
+ 8029bf4:	f800283a 	ret
+
+08029bf8 <m_free>:
+ */
+
+
+struct mbuf *  
+m_free(struct mbuf * m)
+{
+ 8029bf8:	defffc04 	addi	sp,sp,-16
+ 8029bfc:	dfc00315 	stw	ra,12(sp)
+ 8029c00:	df000215 	stw	fp,8(sp)
+ 8029c04:	df000204 	addi	fp,sp,8
+ 8029c08:	e13ffe15 	stw	r4,-8(fp)
+   struct mbuf *  nextptr;
+
+#ifdef NPDEBUG
+   if (mbufq.q_len < 1)
+ 8029c0c:	008201b4 	movhi	r2,2054
+ 8029c10:	10b88717 	ldw	r2,-7652(r2)
+ 8029c14:	00800316 	blt	zero,r2,8029c24 <m_free+0x2c>
+      panic("mfree: q_len");
+ 8029c18:	01020174 	movhi	r4,2053
+ 8029c1c:	212a5004 	addi	r4,r4,-22208
+ 8029c20:	80271780 	call	8027178 <panic>
+
+   if (m->m_type < MT_RXDATA || m->m_type > MT_IFADDR)
+ 8029c24:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c28:	10800817 	ldw	r2,32(r2)
+ 8029c2c:	0080040e 	bge	zero,r2,8029c40 <m_free+0x48>
+ 8029c30:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c34:	10800817 	ldw	r2,32(r2)
+ 8029c38:	10800390 	cmplti	r2,r2,14
+ 8029c3c:	10000a1e 	bne	r2,zero,8029c68 <m_free+0x70>
+   {
+      if (m->m_type == MT_FREE)
+ 8029c40:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c44:	10800817 	ldw	r2,32(r2)
+ 8029c48:	1000041e 	bne	r2,zero,8029c5c <m_free+0x64>
+      {
+         dtrap(); /* debug double free of mbuf by tcp_in() */
+ 8029c4c:	8028cd40 	call	8028cd4 <dtrap>
+         return m->m_next; /* seems harmless, though.... */
+ 8029c50:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c54:	10800617 	ldw	r2,24(r2)
+ 8029c58:	00002306 	br	8029ce8 <m_free+0xf0>
+      }
+      else
+         panic("m_free: type");
+ 8029c5c:	01020174 	movhi	r4,2053
+ 8029c60:	212a5404 	addi	r4,r4,-22192
+ 8029c64:	80271780 	call	8027178 <panic>
+   }
+#endif   /* NPDEBUG */
+
+   nextptr = m->m_next;    /* remember value to return */
+ 8029c68:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c6c:	10800617 	ldw	r2,24(r2)
+ 8029c70:	e0bfff15 	stw	r2,-4(fp)
+
+   if (qdel(&mbufq, m) == NULL)
+ 8029c74:	e17ffe17 	ldw	r5,-8(fp)
+ 8029c78:	010201b4 	movhi	r4,2054
+ 8029c7c:	21388504 	addi	r4,r4,-7660
+ 8029c80:	8028a400 	call	8028a40 <qdel>
+ 8029c84:	1000031e 	bne	r2,zero,8029c94 <m_free+0x9c>
+      panic("m_free: missing");
+ 8029c88:	01020174 	movhi	r4,2053
+ 8029c8c:	212a5804 	addi	r4,r4,-22176
+ 8029c90:	80271780 	call	8027178 <panic>
+
+   m->m_type = MT_FREE;    /* this may seem silly, but helps error checking */
+ 8029c94:	e0bffe17 	ldw	r2,-8(fp)
+ 8029c98:	10000815 	stw	zero,32(r2)
+
+   if (m->pkt)
+ 8029c9c:	e0bffe17 	ldw	r2,-8(fp)
+ 8029ca0:	10800117 	ldw	r2,4(r2)
+ 8029ca4:	10000826 	beq	r2,zero,8029cc8 <m_free+0xd0>
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029ca8:	01000084 	movi	r4,2
+ 8029cac:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(m->pkt);     /* free up the netport buffer */
+ 8029cb0:	e0bffe17 	ldw	r2,-8(fp)
+ 8029cb4:	10800117 	ldw	r2,4(r2)
+ 8029cb8:	1009883a 	mov	r4,r2
+ 8029cbc:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8029cc0:	01000084 	movi	r4,2
+ 8029cc4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   }
+   mbstat.frees++;
+ 8029cc8:	d0a08417 	ldw	r2,-32240(gp)
+ 8029ccc:	10800044 	addi	r2,r2,1
+ 8029cd0:	d0a08415 	stw	r2,-32240(gp)
+   putq(&mfreeq, (qp)m);
+ 8029cd4:	e17ffe17 	ldw	r5,-8(fp)
+ 8029cd8:	010201b4 	movhi	r4,2054
+ 8029cdc:	21388a04 	addi	r4,r4,-7640
+ 8029ce0:	80289900 	call	8028990 <putq>
+   return nextptr;
+ 8029ce4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8029ce8:	e037883a 	mov	sp,fp
+ 8029cec:	dfc00117 	ldw	ra,4(sp)
+ 8029cf0:	df000017 	ldw	fp,0(sp)
+ 8029cf4:	dec00204 	addi	sp,sp,8
+ 8029cf8:	f800283a 	ret
+
+08029cfc <m_freem>:
+ * RETURNS: 
+ */
+
+void
+m_freem(struct mbuf * m)
+{
+ 8029cfc:	defffd04 	addi	sp,sp,-12
+ 8029d00:	dfc00215 	stw	ra,8(sp)
+ 8029d04:	df000115 	stw	fp,4(sp)
+ 8029d08:	df000104 	addi	fp,sp,4
+ 8029d0c:	e13fff15 	stw	r4,-4(fp)
+   while (m != NULL)
+ 8029d10:	00000306 	br	8029d20 <m_freem+0x24>
+      m = m_free(m);
+ 8029d14:	e13fff17 	ldw	r4,-4(fp)
+ 8029d18:	8029bf80 	call	8029bf8 <m_free>
+ 8029d1c:	e0bfff15 	stw	r2,-4(fp)
+   while (m != NULL)
+ 8029d20:	e0bfff17 	ldw	r2,-4(fp)
+ 8029d24:	103ffb1e 	bne	r2,zero,8029d14 <m_freem+0x18>
+}
+ 8029d28:	0001883a 	nop
+ 8029d2c:	e037883a 	mov	sp,fp
+ 8029d30:	dfc00117 	ldw	ra,4(sp)
+ 8029d34:	df000017 	ldw	fp,0(sp)
+ 8029d38:	dec00204 	addi	sp,sp,8
+ 8029d3c:	f800283a 	ret
+
+08029d40 <m_copy>:
+ * RETURNS: 
+ */
+
+struct mbuf *  
+m_copy(struct mbuf * m, int off, int len)
+{
+ 8029d40:	defff704 	addi	sp,sp,-36
+ 8029d44:	dfc00815 	stw	ra,32(sp)
+ 8029d48:	df000715 	stw	fp,28(sp)
+ 8029d4c:	df000704 	addi	fp,sp,28
+ 8029d50:	e13ffb15 	stw	r4,-20(fp)
+ 8029d54:	e17ffa15 	stw	r5,-24(fp)
+ 8029d58:	e1bff915 	stw	r6,-28(fp)
+   struct mbuf *  nb, * head, *  tail;
+   int   tocopy;
+
+   if (len == 0)  /* nothing to do */
+ 8029d5c:	e0bff917 	ldw	r2,-28(fp)
+ 8029d60:	1000021e 	bne	r2,zero,8029d6c <m_copy+0x2c>
+      return NULL;
+ 8029d64:	0005883a 	mov	r2,zero
+ 8029d68:	0000a606 	br	802a004 <m_copy+0x2c4>
+
+#ifdef NPDEBUG
+   /* sanity test parms */
+   if (off < 0 || (len < 0 && len != M_COPYALL))
+ 8029d6c:	e0bffa17 	ldw	r2,-24(fp)
+ 8029d70:	10000516 	blt	r2,zero,8029d88 <m_copy+0x48>
+ 8029d74:	e0bff917 	ldw	r2,-28(fp)
+ 8029d78:	1000180e 	bge	r2,zero,8029ddc <m_copy+0x9c>
+ 8029d7c:	e0bff917 	ldw	r2,-28(fp)
+ 8029d80:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8029d84:	1000151e 	bne	r2,zero,8029ddc <m_copy+0x9c>
+   {
+      dtrap();
+ 8029d88:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 8029d8c:	0005883a 	mov	r2,zero
+ 8029d90:	00009c06 	br	802a004 <m_copy+0x2c4>
+#endif   /* NPDEBUG */
+
+   /* move forward through mbuf q to "off" point */
+   while (off > 0) 
+   {
+      if (!m)
+ 8029d94:	e0bffb17 	ldw	r2,-20(fp)
+ 8029d98:	1000031e 	bne	r2,zero,8029da8 <m_copy+0x68>
+      {
+         dtrap();
+ 8029d9c:	8028cd40 	call	8028cd4 <dtrap>
+         return NULL;
+ 8029da0:	0005883a 	mov	r2,zero
+ 8029da4:	00009706 	br	802a004 <m_copy+0x2c4>
+      }
+      if (off < (int)m->m_len)
+ 8029da8:	e0bffb17 	ldw	r2,-20(fp)
+ 8029dac:	10800217 	ldw	r2,8(r2)
+ 8029db0:	1007883a 	mov	r3,r2
+ 8029db4:	e0bffa17 	ldw	r2,-24(fp)
+ 8029db8:	10c00b16 	blt	r2,r3,8029de8 <m_copy+0xa8>
+         break;
+      off -= m->m_len;
+ 8029dbc:	e0fffa17 	ldw	r3,-24(fp)
+ 8029dc0:	e0bffb17 	ldw	r2,-20(fp)
+ 8029dc4:	10800217 	ldw	r2,8(r2)
+ 8029dc8:	1885c83a 	sub	r2,r3,r2
+ 8029dcc:	e0bffa15 	stw	r2,-24(fp)
+      m = m->m_next;
+ 8029dd0:	e0bffb17 	ldw	r2,-20(fp)
+ 8029dd4:	10800617 	ldw	r2,24(r2)
+ 8029dd8:	e0bffb15 	stw	r2,-20(fp)
+   while (off > 0) 
+ 8029ddc:	e0bffa17 	ldw	r2,-24(fp)
+ 8029de0:	00bfec16 	blt	zero,r2,8029d94 <m_copy+0x54>
+ 8029de4:	00000106 	br	8029dec <m_copy+0xac>
+         break;
+ 8029de8:	0001883a 	nop
+   }
+
+   head = tail = NULL;
+ 8029dec:	e03ffd15 	stw	zero,-12(fp)
+ 8029df0:	e0bffd17 	ldw	r2,-12(fp)
+ 8029df4:	e0bffe15 	stw	r2,-8(fp)
+
+   while (len > 0)
+ 8029df8:	00007806 	br	8029fdc <m_copy+0x29c>
+   {
+      if (m == NULL) /* at end of queue? */
+ 8029dfc:	e0bffb17 	ldw	r2,-20(fp)
+ 8029e00:	1000051e 	bne	r2,zero,8029e18 <m_copy+0xd8>
+      {
+         panic("m_copy: bad len");
+ 8029e04:	01020174 	movhi	r4,2053
+ 8029e08:	212a5c04 	addi	r4,r4,-22160
+ 8029e0c:	80271780 	call	8027178 <panic>
+         return NULL;
+ 8029e10:	0005883a 	mov	r2,zero
+ 8029e14:	00007b06 	br	802a004 <m_copy+0x2c4>
+      }
+      tocopy = (int)MIN(len, (int)(m->m_len - off));
+ 8029e18:	e0bffb17 	ldw	r2,-20(fp)
+ 8029e1c:	10c00217 	ldw	r3,8(r2)
+ 8029e20:	e0bffa17 	ldw	r2,-24(fp)
+ 8029e24:	1885c83a 	sub	r2,r3,r2
+ 8029e28:	1007883a 	mov	r3,r2
+ 8029e2c:	e0bff917 	ldw	r2,-28(fp)
+ 8029e30:	1880010e 	bge	r3,r2,8029e38 <m_copy+0xf8>
+ 8029e34:	1805883a 	mov	r2,r3
+ 8029e38:	e0bffc15 	stw	r2,-16(fp)
+       * ALIGN_TYPE, so if the offset isn't aligned, we must 
+       * copy the buffer instead of cloning it.
+       * Also, don't permit multiple clones; they sometimes
+       * lead to corrupted data.
+       */
+      if ((off & (ALIGN_TYPE - 1)) ||
+ 8029e3c:	e0bffa17 	ldw	r2,-24(fp)
+ 8029e40:	108000cc 	andi	r2,r2,3
+ 8029e44:	1000051e 	bne	r2,zero,8029e5c <m_copy+0x11c>
+          (m->pkt->inuse != 1))
+ 8029e48:	e0bffb17 	ldw	r2,-20(fp)
+ 8029e4c:	10800117 	ldw	r2,4(r2)
+ 8029e50:	10800917 	ldw	r2,36(r2)
+      if ((off & (ALIGN_TYPE - 1)) ||
+ 8029e54:	10800060 	cmpeqi	r2,r2,1
+ 8029e58:	1000211e 	bne	r2,zero,8029ee0 <m_copy+0x1a0>
+      {
+         if ((nb = m_getwithdata (m->m_type, tocopy)) == NULL)
+ 8029e5c:	e0bffb17 	ldw	r2,-20(fp)
+ 8029e60:	10800817 	ldw	r2,32(r2)
+ 8029e64:	e17ffc17 	ldw	r5,-16(fp)
+ 8029e68:	1009883a 	mov	r4,r2
+ 8029e6c:	8029a700 	call	8029a70 <m_getnbuf>
+ 8029e70:	e0bfff15 	stw	r2,-4(fp)
+ 8029e74:	e0bfff17 	ldw	r2,-4(fp)
+ 8029e78:	10005c26 	beq	r2,zero,8029fec <m_copy+0x2ac>
+            goto nospace;
+         MEMCPY(nb->m_data, m->m_data+off, tocopy);
+ 8029e7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029e80:	11000317 	ldw	r4,12(r2)
+ 8029e84:	e0bffb17 	ldw	r2,-20(fp)
+ 8029e88:	10c00317 	ldw	r3,12(r2)
+ 8029e8c:	e0bffa17 	ldw	r2,-24(fp)
+ 8029e90:	1885883a 	add	r2,r3,r2
+ 8029e94:	e0fffc17 	ldw	r3,-16(fp)
+ 8029e98:	180d883a 	mov	r6,r3
+ 8029e9c:	100b883a 	mov	r5,r2
+ 8029ea0:	80086b80 	call	80086b8 <memcpy>
+         nb->m_len = tocopy;  /* set length of data we just moved into new mbuf */
+ 8029ea4:	e0fffc17 	ldw	r3,-16(fp)
+ 8029ea8:	e0bfff17 	ldw	r2,-4(fp)
+ 8029eac:	10c00215 	stw	r3,8(r2)
+
+         tcpstat.tcps_mcopies++;
+ 8029eb0:	008201b4 	movhi	r2,2054
+ 8029eb4:	10b8d217 	ldw	r2,-7352(r2)
+ 8029eb8:	10c00044 	addi	r3,r2,1
+ 8029ebc:	008201b4 	movhi	r2,2054
+ 8029ec0:	10f8d215 	stw	r3,-7352(r2)
+         tcpstat.tcps_mcopiedbytes += tocopy;
+ 8029ec4:	008201b4 	movhi	r2,2054
+ 8029ec8:	10f8d417 	ldw	r3,-7344(r2)
+ 8029ecc:	e0bffc17 	ldw	r2,-16(fp)
+ 8029ed0:	1887883a 	add	r3,r3,r2
+ 8029ed4:	008201b4 	movhi	r2,2054
+ 8029ed8:	10f8d415 	stw	r3,-7344(r2)
+ 8029edc:	00002d06 	br	8029f94 <m_copy+0x254>
+      {
+         /* Rather than memcpy every mbuf's data, "clone" the data by 
+          * making a duplicate of the mbufs involved and bumping the 
+          * inuse count of the actual packet structs
+          */
+         if ((nb = m_getwithdata (m->m_type, 0)) == NULL)
+ 8029ee0:	e0bffb17 	ldw	r2,-20(fp)
+ 8029ee4:	10800817 	ldw	r2,32(r2)
+ 8029ee8:	000b883a 	mov	r5,zero
+ 8029eec:	1009883a 	mov	r4,r2
+ 8029ef0:	8029a700 	call	8029a70 <m_getnbuf>
+ 8029ef4:	e0bfff15 	stw	r2,-4(fp)
+ 8029ef8:	e0bfff17 	ldw	r2,-4(fp)
+ 8029efc:	10003d26 	beq	r2,zero,8029ff4 <m_copy+0x2b4>
+            goto nospace;
+
+         m->pkt->inuse++;     /* bump pkt use count to clone it */
+ 8029f00:	e0bffb17 	ldw	r2,-20(fp)
+ 8029f04:	10800117 	ldw	r2,4(r2)
+ 8029f08:	10c00917 	ldw	r3,36(r2)
+ 8029f0c:	18c00044 	addi	r3,r3,1
+ 8029f10:	10c00915 	stw	r3,36(r2)
+
+         /* set up new mbuf with pointers to cloned packet */
+         nb->pkt = m->pkt;
+ 8029f14:	e0bffb17 	ldw	r2,-20(fp)
+ 8029f18:	10c00117 	ldw	r3,4(r2)
+ 8029f1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029f20:	10c00115 	stw	r3,4(r2)
+         nb->m_base = m->m_base;
+ 8029f24:	e0bffb17 	ldw	r2,-20(fp)
+ 8029f28:	10c00417 	ldw	r3,16(r2)
+ 8029f2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029f30:	10c00415 	stw	r3,16(r2)
+         nb->m_memsz = m->m_memsz;
+ 8029f34:	e0bffb17 	ldw	r2,-20(fp)
+ 8029f38:	10c00517 	ldw	r3,20(r2)
+ 8029f3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8029f40:	10c00515 	stw	r3,20(r2)
+         nb->m_data = m->m_data + off;
+ 8029f44:	e0bffb17 	ldw	r2,-20(fp)
+ 8029f48:	10c00317 	ldw	r3,12(r2)
+ 8029f4c:	e0bffa17 	ldw	r2,-24(fp)
+ 8029f50:	1887883a 	add	r3,r3,r2
+ 8029f54:	e0bfff17 	ldw	r2,-4(fp)
+ 8029f58:	10c00315 	stw	r3,12(r2)
+         nb->m_len = tocopy;
+ 8029f5c:	e0fffc17 	ldw	r3,-16(fp)
+ 8029f60:	e0bfff17 	ldw	r2,-4(fp)
+ 8029f64:	10c00215 	stw	r3,8(r2)
+
+         tcpstat.tcps_mclones++;
+ 8029f68:	008201b4 	movhi	r2,2054
+ 8029f6c:	10b8d317 	ldw	r2,-7348(r2)
+ 8029f70:	10c00044 	addi	r3,r2,1
+ 8029f74:	008201b4 	movhi	r2,2054
+ 8029f78:	10f8d315 	stw	r3,-7348(r2)
+         tcpstat.tcps_mclonedbytes += tocopy;
+ 8029f7c:	008201b4 	movhi	r2,2054
+ 8029f80:	10f8d517 	ldw	r3,-7340(r2)
+ 8029f84:	e0bffc17 	ldw	r2,-16(fp)
+ 8029f88:	1887883a 	add	r3,r3,r2
+ 8029f8c:	008201b4 	movhi	r2,2054
+ 8029f90:	10f8d515 	stw	r3,-7340(r2)
+      }
+
+      len -= tocopy;
+ 8029f94:	e0fff917 	ldw	r3,-28(fp)
+ 8029f98:	e0bffc17 	ldw	r2,-16(fp)
+ 8029f9c:	1885c83a 	sub	r2,r3,r2
+ 8029fa0:	e0bff915 	stw	r2,-28(fp)
+      off = 0;
+ 8029fa4:	e03ffa15 	stw	zero,-24(fp)
+      if (tail)      /* head & tail are set by first pass thru loop */
+ 8029fa8:	e0bffd17 	ldw	r2,-12(fp)
+ 8029fac:	10000426 	beq	r2,zero,8029fc0 <m_copy+0x280>
+         tail->m_next = nb;
+ 8029fb0:	e0bffd17 	ldw	r2,-12(fp)
+ 8029fb4:	e0ffff17 	ldw	r3,-4(fp)
+ 8029fb8:	10c00615 	stw	r3,24(r2)
+ 8029fbc:	00000206 	br	8029fc8 <m_copy+0x288>
+      else
+         head = nb;
+ 8029fc0:	e0bfff17 	ldw	r2,-4(fp)
+ 8029fc4:	e0bffe15 	stw	r2,-8(fp)
+      tail = nb;     /* always make new mbuf the tail */
+ 8029fc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8029fcc:	e0bffd15 	stw	r2,-12(fp)
+      m = m->m_next;
+ 8029fd0:	e0bffb17 	ldw	r2,-20(fp)
+ 8029fd4:	10800617 	ldw	r2,24(r2)
+ 8029fd8:	e0bffb15 	stw	r2,-20(fp)
+   while (len > 0)
+ 8029fdc:	e0bff917 	ldw	r2,-28(fp)
+ 8029fe0:	00bf8616 	blt	zero,r2,8029dfc <m_copy+0xbc>
+
+   }
+
+   return head;
+ 8029fe4:	e0bffe17 	ldw	r2,-8(fp)
+ 8029fe8:	00000606 	br	802a004 <m_copy+0x2c4>
+            goto nospace;
+ 8029fec:	0001883a 	nop
+ 8029ff0:	00000106 	br	8029ff8 <m_copy+0x2b8>
+            goto nospace;
+ 8029ff4:	0001883a 	nop
+
+nospace:
+   m_freem (head);
+ 8029ff8:	e13ffe17 	ldw	r4,-8(fp)
+ 8029ffc:	8029cfc0 	call	8029cfc <m_freem>
+   return NULL;
+ 802a000:	0005883a 	mov	r2,zero
+}
+ 802a004:	e037883a 	mov	sp,fp
+ 802a008:	dfc00117 	ldw	ra,4(sp)
+ 802a00c:	df000017 	ldw	fp,0(sp)
+ 802a010:	dec00204 	addi	sp,sp,8
+ 802a014:	f800283a 	ret
+
+0802a018 <m_adj>:
+ * RETURNS: 
+ */
+
+void
+m_adj(struct mbuf * mp, int len)
+{
+ 802a018:	defffb04 	addi	sp,sp,-20
+ 802a01c:	df000415 	stw	fp,16(sp)
+ 802a020:	df000404 	addi	fp,sp,16
+ 802a024:	e13ffd15 	stw	r4,-12(fp)
+ 802a028:	e17ffc15 	stw	r5,-16(fp)
+   struct mbuf *  m;
+   int   count;
+
+   if ((m = mp) == NULL)
+ 802a02c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a030:	e0bfff15 	stw	r2,-4(fp)
+ 802a034:	e0bfff17 	ldw	r2,-4(fp)
+ 802a038:	10006226 	beq	r2,zero,802a1c4 <m_adj+0x1ac>
+      return;
+
+   if (len >= 0) 
+ 802a03c:	e0bffc17 	ldw	r2,-16(fp)
+ 802a040:	10002216 	blt	r2,zero,802a0cc <m_adj+0xb4>
+   {
+      while (m != NULL && len > 0) 
+ 802a044:	00001c06 	br	802a0b8 <m_adj+0xa0>
+      {
+         if (m->m_len <= (unsigned)len)
+ 802a048:	e0bfff17 	ldw	r2,-4(fp)
+ 802a04c:	10800217 	ldw	r2,8(r2)
+ 802a050:	e0fffc17 	ldw	r3,-16(fp)
+ 802a054:	18800b36 	bltu	r3,r2,802a084 <m_adj+0x6c>
+         {
+            len -= m->m_len;
+ 802a058:	e0fffc17 	ldw	r3,-16(fp)
+ 802a05c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a060:	10800217 	ldw	r2,8(r2)
+ 802a064:	1885c83a 	sub	r2,r3,r2
+ 802a068:	e0bffc15 	stw	r2,-16(fp)
+            m->m_len = 0;
+ 802a06c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a070:	10000215 	stw	zero,8(r2)
+            m = m->m_next;
+ 802a074:	e0bfff17 	ldw	r2,-4(fp)
+ 802a078:	10800617 	ldw	r2,24(r2)
+ 802a07c:	e0bfff15 	stw	r2,-4(fp)
+ 802a080:	00000d06 	br	802a0b8 <m_adj+0xa0>
+         }
+         else
+         {
+            m->m_len -= len;
+ 802a084:	e0bfff17 	ldw	r2,-4(fp)
+ 802a088:	10c00217 	ldw	r3,8(r2)
+ 802a08c:	e0bffc17 	ldw	r2,-16(fp)
+ 802a090:	1887c83a 	sub	r3,r3,r2
+ 802a094:	e0bfff17 	ldw	r2,-4(fp)
+ 802a098:	10c00215 	stw	r3,8(r2)
+            m->m_data += len;
+ 802a09c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a0a0:	10c00317 	ldw	r3,12(r2)
+ 802a0a4:	e0bffc17 	ldw	r2,-16(fp)
+ 802a0a8:	1887883a 	add	r3,r3,r2
+ 802a0ac:	e0bfff17 	ldw	r2,-4(fp)
+ 802a0b0:	10c00315 	stw	r3,12(r2)
+            break;
+ 802a0b4:	00004406 	br	802a1c8 <m_adj+0x1b0>
+      while (m != NULL && len > 0) 
+ 802a0b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a0bc:	10004226 	beq	r2,zero,802a1c8 <m_adj+0x1b0>
+ 802a0c0:	e0bffc17 	ldw	r2,-16(fp)
+ 802a0c4:	00bfe016 	blt	zero,r2,802a048 <m_adj+0x30>
+ 802a0c8:	00003f06 	br	802a1c8 <m_adj+0x1b0>
+       * calculating its length and finding the last mbuf.
+       * If the adjustment only affects this mbuf, then just
+       * adjust and return.  Otherwise, rescan and truncate
+       * after the remaining size.
+       */
+      len = -len;
+ 802a0cc:	e0bffc17 	ldw	r2,-16(fp)
+ 802a0d0:	0085c83a 	sub	r2,zero,r2
+ 802a0d4:	e0bffc15 	stw	r2,-16(fp)
+      count = 0;
+ 802a0d8:	e03ffe15 	stw	zero,-8(fp)
+      for (;;) 
+      {
+         count += m->m_len;
+ 802a0dc:	e0bfff17 	ldw	r2,-4(fp)
+ 802a0e0:	10c00217 	ldw	r3,8(r2)
+ 802a0e4:	e0bffe17 	ldw	r2,-8(fp)
+ 802a0e8:	1885883a 	add	r2,r3,r2
+ 802a0ec:	e0bffe15 	stw	r2,-8(fp)
+         if (m->m_next == (struct mbuf *)0)
+ 802a0f0:	e0bfff17 	ldw	r2,-4(fp)
+ 802a0f4:	10800617 	ldw	r2,24(r2)
+ 802a0f8:	10000426 	beq	r2,zero,802a10c <m_adj+0xf4>
+            break;
+         m = m->m_next;
+ 802a0fc:	e0bfff17 	ldw	r2,-4(fp)
+ 802a100:	10800617 	ldw	r2,24(r2)
+ 802a104:	e0bfff15 	stw	r2,-4(fp)
+         count += m->m_len;
+ 802a108:	003ff406 	br	802a0dc <m_adj+0xc4>
+            break;
+ 802a10c:	0001883a 	nop
+      }
+      if (m->m_len >= (unsigned)len)
+ 802a110:	e0bfff17 	ldw	r2,-4(fp)
+ 802a114:	10c00217 	ldw	r3,8(r2)
+ 802a118:	e0bffc17 	ldw	r2,-16(fp)
+ 802a11c:	18800736 	bltu	r3,r2,802a13c <m_adj+0x124>
+      {
+         m->m_len -= len;
+ 802a120:	e0bfff17 	ldw	r2,-4(fp)
+ 802a124:	10c00217 	ldw	r3,8(r2)
+ 802a128:	e0bffc17 	ldw	r2,-16(fp)
+ 802a12c:	1887c83a 	sub	r3,r3,r2
+ 802a130:	e0bfff17 	ldw	r2,-4(fp)
+ 802a134:	10c00215 	stw	r3,8(r2)
+         return;
+ 802a138:	00002306 	br	802a1c8 <m_adj+0x1b0>
+      }
+      count -= len;
+ 802a13c:	e0fffe17 	ldw	r3,-8(fp)
+ 802a140:	e0bffc17 	ldw	r2,-16(fp)
+ 802a144:	1885c83a 	sub	r2,r3,r2
+ 802a148:	e0bffe15 	stw	r2,-8(fp)
+      /*
+       * Correct length for chain is "count".
+       * Find the mbuf with last data, adjust its length,
+       * and toss data from remaining mbufs on chain.
+       */
+      for (m = mp; m; m = m->m_next)
+ 802a14c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a150:	e0bfff15 	stw	r2,-4(fp)
+ 802a154:	00001006 	br	802a198 <m_adj+0x180>
+      {
+         if (m->m_len >= (unsigned)count)
+ 802a158:	e0bfff17 	ldw	r2,-4(fp)
+ 802a15c:	10c00217 	ldw	r3,8(r2)
+ 802a160:	e0bffe17 	ldw	r2,-8(fp)
+ 802a164:	18800436 	bltu	r3,r2,802a178 <m_adj+0x160>
+         {
+            m->m_len = count;
+ 802a168:	e0fffe17 	ldw	r3,-8(fp)
+ 802a16c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a170:	10c00215 	stw	r3,8(r2)
+            break;
+ 802a174:	00000a06 	br	802a1a0 <m_adj+0x188>
+         }
+         count -= m->m_len;
+ 802a178:	e0fffe17 	ldw	r3,-8(fp)
+ 802a17c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a180:	10800217 	ldw	r2,8(r2)
+ 802a184:	1885c83a 	sub	r2,r3,r2
+ 802a188:	e0bffe15 	stw	r2,-8(fp)
+      for (m = mp; m; m = m->m_next)
+ 802a18c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a190:	10800617 	ldw	r2,24(r2)
+ 802a194:	e0bfff15 	stw	r2,-4(fp)
+ 802a198:	e0bfff17 	ldw	r2,-4(fp)
+ 802a19c:	103fee1e 	bne	r2,zero,802a158 <m_adj+0x140>
+      }
+      while ((m = m->m_next) != (struct mbuf *)NULL)
+ 802a1a0:	00000206 	br	802a1ac <m_adj+0x194>
+         m->m_len = 0;
+ 802a1a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802a1a8:	10000215 	stw	zero,8(r2)
+      while ((m = m->m_next) != (struct mbuf *)NULL)
+ 802a1ac:	e0bfff17 	ldw	r2,-4(fp)
+ 802a1b0:	10800617 	ldw	r2,24(r2)
+ 802a1b4:	e0bfff15 	stw	r2,-4(fp)
+ 802a1b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a1bc:	103ff91e 	bne	r2,zero,802a1a4 <m_adj+0x18c>
+ 802a1c0:	00000106 	br	802a1c8 <m_adj+0x1b0>
+      return;
+ 802a1c4:	0001883a 	nop
+   }
+}
+ 802a1c8:	e037883a 	mov	sp,fp
+ 802a1cc:	df000017 	ldw	fp,0(sp)
+ 802a1d0:	dec00104 	addi	sp,sp,4
+ 802a1d4:	f800283a 	ret
+
+0802a1d8 <mbuf_len>:
+ * RETURNS: 
+ */
+
+int
+mbuf_len (struct mbuf * m)
+{
+ 802a1d8:	defffd04 	addi	sp,sp,-12
+ 802a1dc:	df000215 	stw	fp,8(sp)
+ 802a1e0:	df000204 	addi	fp,sp,8
+ 802a1e4:	e13ffe15 	stw	r4,-8(fp)
+   int   len   =  0;
+ 802a1e8:	e03fff15 	stw	zero,-4(fp)
+
+   while (m)
+ 802a1ec:	00000806 	br	802a210 <mbuf_len+0x38>
+   {
+      len += m->m_len;
+ 802a1f0:	e0bffe17 	ldw	r2,-8(fp)
+ 802a1f4:	10c00217 	ldw	r3,8(r2)
+ 802a1f8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a1fc:	1885883a 	add	r2,r3,r2
+ 802a200:	e0bfff15 	stw	r2,-4(fp)
+      m = m->m_next;
+ 802a204:	e0bffe17 	ldw	r2,-8(fp)
+ 802a208:	10800617 	ldw	r2,24(r2)
+ 802a20c:	e0bffe15 	stw	r2,-8(fp)
+   while (m)
+ 802a210:	e0bffe17 	ldw	r2,-8(fp)
+ 802a214:	103ff61e 	bne	r2,zero,802a1f0 <mbuf_len+0x18>
+   }
+   return len;
+ 802a218:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802a21c:	e037883a 	mov	sp,fp
+ 802a220:	df000017 	ldw	fp,0(sp)
+ 802a224:	dec00104 	addi	sp,sp,4
+ 802a228:	f800283a 	ret
+
+0802a22c <dtom>:
+ * RETURNS: 
+ */
+
+struct mbuf *  
+dtom(void * data)
+{
+ 802a22c:	defffb04 	addi	sp,sp,-20
+ 802a230:	dfc00415 	stw	ra,16(sp)
+ 802a234:	df000315 	stw	fp,12(sp)
+ 802a238:	df000304 	addi	fp,sp,12
+ 802a23c:	e13ffd15 	stw	r4,-12(fp)
+   qp qptr;
+   struct mbuf *  m;
+
+   for (qptr = mbufq.q_head; qptr; qptr = qptr->qe_next)
+ 802a240:	008201b4 	movhi	r2,2054
+ 802a244:	10b88517 	ldw	r2,-7660(r2)
+ 802a248:	e0bfff15 	stw	r2,-4(fp)
+ 802a24c:	00001206 	br	802a298 <dtom+0x6c>
+   {
+      m = (struct mbuf *)qptr;
+ 802a250:	e0bfff17 	ldw	r2,-4(fp)
+ 802a254:	e0bffe15 	stw	r2,-8(fp)
+
+      if (IN_RANGE(m->m_base, m->m_memsz, (char*)data))
+ 802a258:	e0bffe17 	ldw	r2,-8(fp)
+ 802a25c:	10800417 	ldw	r2,16(r2)
+ 802a260:	e0fffd17 	ldw	r3,-12(fp)
+ 802a264:	18800936 	bltu	r3,r2,802a28c <dtom+0x60>
+ 802a268:	e0bffe17 	ldw	r2,-8(fp)
+ 802a26c:	10c00417 	ldw	r3,16(r2)
+ 802a270:	e0bffe17 	ldw	r2,-8(fp)
+ 802a274:	10800517 	ldw	r2,20(r2)
+ 802a278:	1885883a 	add	r2,r3,r2
+ 802a27c:	e0fffd17 	ldw	r3,-12(fp)
+ 802a280:	1880022e 	bgeu	r3,r2,802a28c <dtom+0x60>
+         return (struct mbuf *)qptr;
+ 802a284:	e0bfff17 	ldw	r2,-4(fp)
+ 802a288:	00000906 	br	802a2b0 <dtom+0x84>
+   for (qptr = mbufq.q_head; qptr; qptr = qptr->qe_next)
+ 802a28c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a290:	10800017 	ldw	r2,0(r2)
+ 802a294:	e0bfff15 	stw	r2,-4(fp)
+ 802a298:	e0bfff17 	ldw	r2,-4(fp)
+ 802a29c:	103fec1e 	bne	r2,zero,802a250 <dtom+0x24>
+      else
+         continue;
+
+   }
+
+   panic("dtom");    /* data not found in any "in use" mbuf */
+ 802a2a0:	01020174 	movhi	r4,2053
+ 802a2a4:	212a6004 	addi	r4,r4,-22144
+ 802a2a8:	80271780 	call	8027178 <panic>
+   return NULL;
+ 802a2ac:	0005883a 	mov	r2,zero
+}
+ 802a2b0:	e037883a 	mov	sp,fp
+ 802a2b4:	dfc00117 	ldw	ra,4(sp)
+ 802a2b8:	df000017 	ldw	fp,0(sp)
+ 802a2bc:	dec00204 	addi	sp,sp,8
+ 802a2c0:	f800283a 	ret
+
+0802a2c4 <remque>:
+};
+
+
+void
+remque (void * arg)
+{
+ 802a2c4:	defffd04 	addi	sp,sp,-12
+ 802a2c8:	df000215 	stw	fp,8(sp)
+ 802a2cc:	df000204 	addi	fp,sp,8
+ 802a2d0:	e13ffe15 	stw	r4,-8(fp)
+   struct bsdq *  old;
+
+   old = (struct bsdq *)arg;
+ 802a2d4:	e0bffe17 	ldw	r2,-8(fp)
+ 802a2d8:	e0bfff15 	stw	r2,-4(fp)
+   if (!old->prev) return;
+ 802a2dc:	e0bfff17 	ldw	r2,-4(fp)
+ 802a2e0:	10800117 	ldw	r2,4(r2)
+ 802a2e4:	10000e26 	beq	r2,zero,802a320 <remque+0x5c>
+      old->prev->next = old->next;
+ 802a2e8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a2ec:	10800117 	ldw	r2,4(r2)
+ 802a2f0:	e0ffff17 	ldw	r3,-4(fp)
+ 802a2f4:	18c00017 	ldw	r3,0(r3)
+ 802a2f8:	10c00015 	stw	r3,0(r2)
+   if (old->next)
+ 802a2fc:	e0bfff17 	ldw	r2,-4(fp)
+ 802a300:	10800017 	ldw	r2,0(r2)
+ 802a304:	10000726 	beq	r2,zero,802a324 <remque+0x60>
+      old->next->prev = old->prev;
+ 802a308:	e0bfff17 	ldw	r2,-4(fp)
+ 802a30c:	10800017 	ldw	r2,0(r2)
+ 802a310:	e0ffff17 	ldw	r3,-4(fp)
+ 802a314:	18c00117 	ldw	r3,4(r3)
+ 802a318:	10c00115 	stw	r3,4(r2)
+ 802a31c:	00000106 	br	802a324 <remque+0x60>
+   if (!old->prev) return;
+ 802a320:	0001883a 	nop
+}
+ 802a324:	e037883a 	mov	sp,fp
+ 802a328:	df000017 	ldw	fp,0(sp)
+ 802a32c:	dec00104 	addi	sp,sp,4
+ 802a330:	f800283a 	ret
+
+0802a334 <insque>:
+ * RETURNS: 
+ */
+
+void
+insque(void * n, void * p)
+{
+ 802a334:	defffb04 	addi	sp,sp,-20
+ 802a338:	df000415 	stw	fp,16(sp)
+ 802a33c:	df000404 	addi	fp,sp,16
+ 802a340:	e13ffd15 	stw	r4,-12(fp)
+ 802a344:	e17ffc15 	stw	r5,-16(fp)
+   struct bsdq *  newe, *  prev;
+
+   newe = (struct bsdq *)n;
+ 802a348:	e0bffd17 	ldw	r2,-12(fp)
+ 802a34c:	e0bfff15 	stw	r2,-4(fp)
+   prev = (struct bsdq *)p;
+ 802a350:	e0bffc17 	ldw	r2,-16(fp)
+ 802a354:	e0bffe15 	stw	r2,-8(fp)
+   newe->next = prev->next;
+ 802a358:	e0bffe17 	ldw	r2,-8(fp)
+ 802a35c:	10c00017 	ldw	r3,0(r2)
+ 802a360:	e0bfff17 	ldw	r2,-4(fp)
+ 802a364:	10c00015 	stw	r3,0(r2)
+   newe->prev = prev;
+ 802a368:	e0bfff17 	ldw	r2,-4(fp)
+ 802a36c:	e0fffe17 	ldw	r3,-8(fp)
+ 802a370:	10c00115 	stw	r3,4(r2)
+   prev->next = newe;
+ 802a374:	e0bffe17 	ldw	r2,-8(fp)
+ 802a378:	e0ffff17 	ldw	r3,-4(fp)
+ 802a37c:	10c00015 	stw	r3,0(r2)
+   if (newe->next)
+ 802a380:	e0bfff17 	ldw	r2,-4(fp)
+ 802a384:	10800017 	ldw	r2,0(r2)
+ 802a388:	10000426 	beq	r2,zero,802a39c <insque+0x68>
+      newe->next->prev = newe;
+ 802a38c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a390:	10800017 	ldw	r2,0(r2)
+ 802a394:	e0ffff17 	ldw	r3,-4(fp)
+ 802a398:	10c00115 	stw	r3,4(r2)
+}
+ 802a39c:	0001883a 	nop
+ 802a3a0:	e037883a 	mov	sp,fp
+ 802a3a4:	df000017 	ldw	fp,0(sp)
+ 802a3a8:	dec00104 	addi	sp,sp,4
+ 802a3ac:	f800283a 	ret
+
+0802a3b0 <nptcp_init>:
+ * RETURNS: Returns 0 if OK, else non-zero error code. 
+ */
+
+int
+nptcp_init()
+{
+ 802a3b0:	defffb04 	addi	sp,sp,-20
+ 802a3b4:	dfc00415 	stw	ra,16(sp)
+ 802a3b8:	df000315 	stw	fp,12(sp)
+ 802a3bc:	df000304 	addi	fp,sp,12
+    * buffers, soreceive() can't complete and the packet buffers stay 
+    * on the queue, so we allocate 3 extra mbufs in the hope that 
+    * this will allow soreceive() to complete and free up the packet 
+    * buffers. yes, its kind of an ugly hack and 3 is a wild guess.
+    */
+   unsigned bufcount = (lilbufs + bigbufs) * 2 + 3;
+ 802a3c0:	d0e01617 	ldw	r3,-32680(gp)
+ 802a3c4:	d0a01817 	ldw	r2,-32672(gp)
+ 802a3c8:	1885883a 	add	r2,r3,r2
+ 802a3cc:	1085883a 	add	r2,r2,r2
+ 802a3d0:	108000c4 	addi	r2,r2,3
+ 802a3d4:	e0bffe15 	stw	r2,-8(fp)
+   struct mbuf *  m; /* scratch mbuf for mfreeq init */
+
+   MEMSET(&soq, 0, sizeof(soq));    /* Set socket queue to NULLs */
+ 802a3d8:	01800504 	movi	r6,20
+ 802a3dc:	000b883a 	mov	r5,zero
+ 802a3e0:	010201b4 	movhi	r4,2054
+ 802a3e4:	21387104 	addi	r4,r4,-7740
+ 802a3e8:	80088e40 	call	80088e4 <memset>
+   MEMSET(&mbufq, 0, sizeof(mbufq));
+ 802a3ec:	01800504 	movi	r6,20
+ 802a3f0:	000b883a 	mov	r5,zero
+ 802a3f4:	010201b4 	movhi	r4,2054
+ 802a3f8:	21388504 	addi	r4,r4,-7660
+ 802a3fc:	80088e40 	call	80088e4 <memset>
+   MEMSET(&mfreeq, 0, sizeof(mfreeq));
+ 802a400:	01800504 	movi	r6,20
+ 802a404:	000b883a 	mov	r5,zero
+ 802a408:	010201b4 	movhi	r4,2054
+ 802a40c:	21388a04 	addi	r4,r4,-7640
+ 802a410:	80088e40 	call	80088e4 <memset>
+   for (i = 0; i < (int)bufcount; i++)
+ 802a414:	e03fff15 	stw	zero,-4(fp)
+ 802a418:	00001506 	br	802a470 <nptcp_init+0xc0>
+   {
+      m = MBU_ALLOC(sizeof(struct mbuf));
+ 802a41c:	01000904 	movi	r4,36
+ 802a420:	802982c0 	call	802982c <npalloc>
+ 802a424:	e0bffd15 	stw	r2,-12(fp)
+      if (!m)  /* malloc error, bail out */
+ 802a428:	e0bffd17 	ldw	r2,-12(fp)
+ 802a42c:	1000031e 	bne	r2,zero,802a43c <nptcp_init+0x8c>
+         panic("tcpinit");
+ 802a430:	01020174 	movhi	r4,2053
+ 802a434:	212a6204 	addi	r4,r4,-22136
+ 802a438:	80271780 	call	8027178 <panic>
+      m->m_type = MT_FREE;
+ 802a43c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a440:	10000815 	stw	zero,32(r2)
+      m->m_len = 0;
+ 802a444:	e0bffd17 	ldw	r2,-12(fp)
+ 802a448:	10000215 	stw	zero,8(r2)
+      m->m_data = NULL;
+ 802a44c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a450:	10000315 	stw	zero,12(r2)
+      putq(&mfreeq, (qp)m);
+ 802a454:	e17ffd17 	ldw	r5,-12(fp)
+ 802a458:	010201b4 	movhi	r4,2054
+ 802a45c:	21388a04 	addi	r4,r4,-7640
+ 802a460:	80289900 	call	8028990 <putq>
+   for (i = 0; i < (int)bufcount; i++)
+ 802a464:	e0bfff17 	ldw	r2,-4(fp)
+ 802a468:	10800044 	addi	r2,r2,1
+ 802a46c:	e0bfff15 	stw	r2,-4(fp)
+ 802a470:	e0bffe17 	ldw	r2,-8(fp)
+ 802a474:	e0ffff17 	ldw	r3,-4(fp)
+ 802a478:	18bfe816 	blt	r3,r2,802a41c <nptcp_init+0x6c>
+   }
+   mfreeq.q_min = (int)bufcount;   /* this should match q_max and q_len */
+ 802a47c:	e0fffe17 	ldw	r3,-8(fp)
+ 802a480:	008201b4 	movhi	r2,2054
+ 802a484:	10f88e15 	stw	r3,-7624(r2)
+   tcpmib.tcpRtoAlgorithm = 4;     /* Van Jacobson's algorithm */
+   tcpmib.tcpRtoMin = TCPTV_MIN * 1000;      /* PR_SLOWHZ */
+   tcpmib.tcpRtoMax = TCPTV_REXMTMAX * 1000; /* PR_SLOWHZ */
+#endif
+
+   tcp_init();    /* call the BSD init in tcp_usr.c */
+ 802a488:	80349f80 	call	80349f8 <tcp_init>
+
+#ifdef TCP_MENUS
+   install_menu(&tcpmenu[0]);
+#endif   /* IN_MENUS */
+
+   return 0;   /* good return */
+ 802a48c:	0005883a 	mov	r2,zero
+}
+ 802a490:	e037883a 	mov	sp,fp
+ 802a494:	dfc00117 	ldw	ra,4(sp)
+ 802a498:	df000017 	ldw	fp,0(sp)
+ 802a49c:	dec00204 	addi	sp,sp,8
+ 802a4a0:	f800283a 	ret
+
+0802a4a4 <tcp_rcv>:
+
+#ifdef IP_V4
+ 
+int
+tcp_rcv(PACKET pkt)     /* NOTE: pkt has nb_prot pointing to IP header */
+{
+ 802a4a4:	defff904 	addi	sp,sp,-28
+ 802a4a8:	dfc00615 	stw	ra,24(sp)
+ 802a4ac:	df000515 	stw	fp,20(sp)
+ 802a4b0:	df000504 	addi	fp,sp,20
+ 802a4b4:	e13ffb15 	stw	r4,-20(fp)
+
+   /* For TCP, the netport IP layer is modified to set nb_prot to the 
+    * start of the IP header (not TCP). We need to do some further
+    * mods which the BSD code expects:
+    */
+   bip = (struct ip *)pkt->nb_prot;    /* get ip header */
+ 802a4b8:	e0bffb17 	ldw	r2,-20(fp)
+ 802a4bc:	10800317 	ldw	r2,12(r2)
+ 802a4c0:	e0bfff15 	stw	r2,-4(fp)
+   len = ntohs(bip->ip_len);  /* get length in local endian */
+ 802a4c4:	e0bfff17 	ldw	r2,-4(fp)
+ 802a4c8:	1080008b 	ldhu	r2,2(r2)
+ 802a4cc:	10bfffcc 	andi	r2,r2,65535
+ 802a4d0:	1004d23a 	srli	r2,r2,8
+ 802a4d4:	1007883a 	mov	r3,r2
+ 802a4d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a4dc:	1080008b 	ldhu	r2,2(r2)
+ 802a4e0:	10bfffcc 	andi	r2,r2,65535
+ 802a4e4:	1004923a 	slli	r2,r2,8
+ 802a4e8:	1884b03a 	or	r2,r3,r2
+ 802a4ec:	e0bffe8d 	sth	r2,-6(fp)
+
+   /* verify checksum of received packet */
+
+   tcpp = (struct tcphdr *)ip_data(bip);
+ 802a4f0:	e0bfff17 	ldw	r2,-4(fp)
+ 802a4f4:	10800003 	ldbu	r2,0(r2)
+ 802a4f8:	10803fcc 	andi	r2,r2,255
+ 802a4fc:	100490ba 	slli	r2,r2,2
+ 802a500:	10800f0c 	andi	r2,r2,60
+ 802a504:	e0ffff17 	ldw	r3,-4(fp)
+ 802a508:	1885883a 	add	r2,r3,r2
+ 802a50c:	e0bffd15 	stw	r2,-12(fp)
+   if (tcp_cksum(bip) != tcpp->th_sum)
+ 802a510:	e13fff17 	ldw	r4,-4(fp)
+ 802a514:	80400c00 	call	80400c0 <tcp_cksum>
+ 802a518:	1007883a 	mov	r3,r2
+ 802a51c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a520:	1080040b 	ldhu	r2,16(r2)
+ 802a524:	18ffffcc 	andi	r3,r3,65535
+ 802a528:	10bfffcc 	andi	r2,r2,65535
+ 802a52c:	18801226 	beq	r3,r2,802a578 <tcp_rcv+0xd4>
+   {
+      TCP_MIB_INC(tcpInErrs);    /* keep MIB stats */
+ 802a530:	008201b4 	movhi	r2,2054
+ 802a534:	10b88317 	ldw	r2,-7668(r2)
+ 802a538:	10c00044 	addi	r3,r2,1
+ 802a53c:	008201b4 	movhi	r2,2054
+ 802a540:	10f88315 	stw	r3,-7668(r2)
+      tcpstat.tcps_rcvbadsum++;  /* keep BSD stats */
+ 802a544:	008201b4 	movhi	r2,2054
+ 802a548:	10b8c017 	ldw	r2,-7424(r2)
+ 802a54c:	10c00044 	addi	r3,r2,1
+ 802a550:	008201b4 	movhi	r2,2054
+ 802a554:	10f8c015 	stw	r3,-7424(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a558:	01000084 	movi	r4,2
+ 802a55c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);  /* punt packet */
+ 802a560:	e13ffb17 	ldw	r4,-20(fp)
+ 802a564:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a568:	01000084 	movi	r4,2
+ 802a56c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_BAD_HEADER;
+ 802a570:	00bff804 	movi	r2,-32
+ 802a574:	00003306 	br	802a644 <tcp_rcv+0x1a0>
+   }
+
+   m_in = m_getnbuf(MT_RXDATA, 0);
+ 802a578:	000b883a 	mov	r5,zero
+ 802a57c:	01000044 	movi	r4,1
+ 802a580:	8029a700 	call	8029a70 <m_getnbuf>
+ 802a584:	e0bffc15 	stw	r2,-16(fp)
+   if (!m_in){
+ 802a588:	e0bffc17 	ldw	r2,-16(fp)
+ 802a58c:	1000081e 	bne	r2,zero,802a5b0 <tcp_rcv+0x10c>
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a590:	01000084 	movi	r4,2
+ 802a594:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(pkt);
+ 802a598:	e13ffb17 	ldw	r4,-20(fp)
+ 802a59c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a5a0:	01000084 	movi	r4,2
+ 802a5a4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_RESOURCE;  
+ 802a5a8:	00bffa84 	movi	r2,-22
+ 802a5ac:	00002506 	br	802a644 <tcp_rcv+0x1a0>
+   }
+
+   IN_PROFILER(PF_TCP, PF_ENTRY);      /* measure time in TCP */
+
+   /* subtract IP header length from total IP packet length */
+   len -= ((unshort)(bip->ip_ver_ihl & 0x0f) << 2);
+ 802a5b0:	e0bfff17 	ldw	r2,-4(fp)
+ 802a5b4:	10800003 	ldbu	r2,0(r2)
+ 802a5b8:	10803fcc 	andi	r2,r2,255
+ 802a5bc:	100490ba 	slli	r2,r2,2
+ 802a5c0:	10800f0c 	andi	r2,r2,60
+ 802a5c4:	1007883a 	mov	r3,r2
+ 802a5c8:	e0bffe8b 	ldhu	r2,-6(fp)
+ 802a5cc:	10c5c83a 	sub	r2,r2,r3
+ 802a5d0:	e0bffe8d 	sth	r2,-6(fp)
+   bip->ip_len = len;   /* put TCP length in struct for TCP code to use */
+ 802a5d4:	e0bfff17 	ldw	r2,-4(fp)
+ 802a5d8:	e0fffe8b 	ldhu	r3,-6(fp)
+ 802a5dc:	10c0008d 	sth	r3,2(r2)
+
+   /* set mbuf to point to start of IP header (not TCP) */
+   m_in->pkt = pkt;
+ 802a5e0:	e0bffc17 	ldw	r2,-16(fp)
+ 802a5e4:	e0fffb17 	ldw	r3,-20(fp)
+ 802a5e8:	10c00115 	stw	r3,4(r2)
+   m_in->m_data = pkt->nb_prot;
+ 802a5ec:	e0bffb17 	ldw	r2,-20(fp)
+ 802a5f0:	10c00317 	ldw	r3,12(r2)
+ 802a5f4:	e0bffc17 	ldw	r2,-16(fp)
+ 802a5f8:	10c00315 	stw	r3,12(r2)
+   m_in->m_len = pkt->nb_plen;
+ 802a5fc:	e0bffb17 	ldw	r2,-20(fp)
+ 802a600:	10c00417 	ldw	r3,16(r2)
+ 802a604:	e0bffc17 	ldw	r2,-16(fp)
+ 802a608:	10c00215 	stw	r3,8(r2)
+   m_in->m_base = pkt->nb_buff;     /* ??? */
+ 802a60c:	e0bffb17 	ldw	r2,-20(fp)
+ 802a610:	10c00117 	ldw	r3,4(r2)
+ 802a614:	e0bffc17 	ldw	r2,-16(fp)
+ 802a618:	10c00415 	stw	r3,16(r2)
+   m_in->m_memsz = pkt->nb_blen;    /* ??? */
+ 802a61c:	e0bffb17 	ldw	r2,-20(fp)
+ 802a620:	10c00217 	ldw	r3,8(r2)
+ 802a624:	e0bffc17 	ldw	r2,-16(fp)
+ 802a628:	10c00515 	stw	r3,20(r2)
+
+   tcp_input(m_in, pkt->net);
+ 802a62c:	e0bffb17 	ldw	r2,-20(fp)
+ 802a630:	10800617 	ldw	r2,24(r2)
+ 802a634:	100b883a 	mov	r5,r2
+ 802a638:	e13ffc17 	ldw	r4,-16(fp)
+ 802a63c:	80310500 	call	8031050 <tcp_input>
+
+   IN_PROFILER(PF_TCP, PF_EXIT);      /* measure time in TCP */
+
+   return 0;
+ 802a640:	0005883a 	mov	r2,zero
+}
+ 802a644:	e037883a 	mov	sp,fp
+ 802a648:	dfc00117 	ldw	ra,4(sp)
+ 802a64c:	df000017 	ldw	fp,0(sp)
+ 802a650:	dec00204 	addi	sp,sp,8
+ 802a654:	f800283a 	ret
+
+0802a658 <ip_output>:
+ * RETURNS: 
+ */
+
+int
+ip_output(struct mbuf * data, struct   ip_socopts * so_optsPack) /* mbuf chain with data to send */
+{
+ 802a658:	defff404 	addi	sp,sp,-48
+ 802a65c:	dfc00b15 	stw	ra,44(sp)
+ 802a660:	df000a15 	stw	fp,40(sp)
+ 802a664:	df000a04 	addi	fp,sp,40
+ 802a668:	e13ff715 	stw	r4,-36(fp)
+ 802a66c:	e17ff615 	stw	r5,-40(fp)
+    * little copying as possible. Typically the mbufs will be either 
+    * 1) a single mbuf with iptcp header info only (e.g.tcp ACK 
+    * packet), or 2) iptcp header with data mbuf chained to it, or 3) 
+    * #2) with a tiny option data mbuf between header and data. 
+    */
+   if ((data->m_next))
+ 802a670:	e0bff717 	ldw	r2,-36(fp)
+ 802a674:	10800617 	ldw	r2,24(r2)
+ 802a678:	10010226 	beq	r2,zero,802aa84 <ip_output+0x42c>
+   {
+      m1 = data;
+ 802a67c:	e0bff717 	ldw	r2,-36(fp)
+ 802a680:	e0bfff15 	stw	r2,-4(fp)
+      m2 = data->m_next;
+ 802a684:	e0bff717 	ldw	r2,-36(fp)
+ 802a688:	10800617 	ldw	r2,24(r2)
+ 802a68c:	e0bffe15 	stw	r2,-8(fp)
+
+      /* If m2 is small (e.g. options), copy it to m1 and free it */
+      while (m2 && (m2->m_len < 10))
+ 802a690:	00003306 	br	802a760 <ip_output+0x108>
+      {
+         pkt = m1->pkt;
+ 802a694:	e0bfff17 	ldw	r2,-4(fp)
+ 802a698:	10800117 	ldw	r2,4(r2)
+ 802a69c:	e0bffb15 	stw	r2,-20(fp)
+         if ((pkt->nb_buff + pkt->nb_blen) > /* make sure m2 will fit in m1 */
+ 802a6a0:	e0bffb17 	ldw	r2,-20(fp)
+ 802a6a4:	10c00117 	ldw	r3,4(r2)
+ 802a6a8:	e0bffb17 	ldw	r2,-20(fp)
+ 802a6ac:	10800217 	ldw	r2,8(r2)
+ 802a6b0:	1885883a 	add	r2,r3,r2
+             (m1->m_data + m1->m_len + m2->m_len))
+ 802a6b4:	e0ffff17 	ldw	r3,-4(fp)
+ 802a6b8:	19000317 	ldw	r4,12(r3)
+ 802a6bc:	e0ffff17 	ldw	r3,-4(fp)
+ 802a6c0:	19400217 	ldw	r5,8(r3)
+ 802a6c4:	e0fffe17 	ldw	r3,-8(fp)
+ 802a6c8:	18c00217 	ldw	r3,8(r3)
+ 802a6cc:	28c7883a 	add	r3,r5,r3
+ 802a6d0:	20c7883a 	add	r3,r4,r3
+         if ((pkt->nb_buff + pkt->nb_blen) > /* make sure m2 will fit in m1 */
+ 802a6d4:	1880292e 	bgeu	r3,r2,802a77c <ip_output+0x124>
+         {
+            MEMCPY((m1->m_data + m1->m_len), m2->m_data, m2->m_len);
+ 802a6d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a6dc:	10c00317 	ldw	r3,12(r2)
+ 802a6e0:	e0bfff17 	ldw	r2,-4(fp)
+ 802a6e4:	10800217 	ldw	r2,8(r2)
+ 802a6e8:	1887883a 	add	r3,r3,r2
+ 802a6ec:	e0bffe17 	ldw	r2,-8(fp)
+ 802a6f0:	11000317 	ldw	r4,12(r2)
+ 802a6f4:	e0bffe17 	ldw	r2,-8(fp)
+ 802a6f8:	10800217 	ldw	r2,8(r2)
+ 802a6fc:	100d883a 	mov	r6,r2
+ 802a700:	200b883a 	mov	r5,r4
+ 802a704:	1809883a 	mov	r4,r3
+ 802a708:	80086b80 	call	80086b8 <memcpy>
+            m1->m_len += m2->m_len;
+ 802a70c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a710:	10c00217 	ldw	r3,8(r2)
+ 802a714:	e0bffe17 	ldw	r2,-8(fp)
+ 802a718:	10800217 	ldw	r2,8(r2)
+ 802a71c:	1887883a 	add	r3,r3,r2
+ 802a720:	e0bfff17 	ldw	r2,-4(fp)
+ 802a724:	10c00215 	stw	r3,8(r2)
+            m1->m_next = m2->m_next;
+ 802a728:	e0bffe17 	ldw	r2,-8(fp)
+ 802a72c:	10c00617 	ldw	r3,24(r2)
+ 802a730:	e0bfff17 	ldw	r2,-4(fp)
+ 802a734:	10c00615 	stw	r3,24(r2)
+            m_free(m2);    /* free this m2.... */
+ 802a738:	e13ffe17 	ldw	r4,-8(fp)
+ 802a73c:	8029bf80 	call	8029bf8 <m_free>
+            m2 = m1->m_next;  /* ...and thread the next one */
+ 802a740:	e0bfff17 	ldw	r2,-4(fp)
+ 802a744:	10800617 	ldw	r2,24(r2)
+ 802a748:	e0bffe15 	stw	r2,-8(fp)
+            tcpstat.tcps_oappends++;
+ 802a74c:	008201b4 	movhi	r2,2054
+ 802a750:	10b8d717 	ldw	r2,-7332(r2)
+ 802a754:	10c00044 	addi	r3,r2,1
+ 802a758:	008201b4 	movhi	r2,2054
+ 802a75c:	10f8d715 	stw	r3,-7332(r2)
+      while (m2 && (m2->m_len < 10))
+ 802a760:	e0bffe17 	ldw	r2,-8(fp)
+ 802a764:	10005726 	beq	r2,zero,802a8c4 <ip_output+0x26c>
+ 802a768:	e0bffe17 	ldw	r2,-8(fp)
+ 802a76c:	10800217 	ldw	r2,8(r2)
+ 802a770:	108002b0 	cmpltui	r2,r2,10
+ 802a774:	103fc71e 	bne	r2,zero,802a694 <ip_output+0x3c>
+ 802a778:	00005206 	br	802a8c4 <ip_output+0x26c>
+         }
+         else     /* if won't fit, fall to next copy */
+            break;
+ 802a77c:	0001883a 	nop
+      }
+
+      while (m2)  /* If we still have two or more buffers, more copying: */
+ 802a780:	00005006 	br	802a8c4 <ip_output+0x26c>
+      {
+         /* try prepending m1 to m2, first see if it fits: */
+         e = m2->m_data - m2->pkt->nb_buff;  /* e is prepend space */
+ 802a784:	e0bffe17 	ldw	r2,-8(fp)
+ 802a788:	10c00317 	ldw	r3,12(r2)
+ 802a78c:	e0bffe17 	ldw	r2,-8(fp)
+ 802a790:	10800117 	ldw	r2,4(r2)
+ 802a794:	10800117 	ldw	r2,4(r2)
+ 802a798:	1885c83a 	sub	r2,r3,r2
+ 802a79c:	e0bffa15 	stw	r2,-24(fp)
+         if (e < MaxLnh)
+ 802a7a0:	d0a06417 	ldw	r2,-32368(gp)
+ 802a7a4:	e0fffa17 	ldw	r3,-24(fp)
+ 802a7a8:	1880090e 	bge	r3,r2,802a7d0 <ip_output+0x178>
+         { 
+#ifdef NPDEBUG
+            dprintf("nptcp: MaxLnh:%d, e:%d\n", MaxLnh, e);
+ 802a7ac:	d0a06417 	ldw	r2,-32368(gp)
+ 802a7b0:	e1bffa17 	ldw	r6,-24(fp)
+ 802a7b4:	100b883a 	mov	r5,r2
+ 802a7b8:	01020174 	movhi	r4,2053
+ 802a7bc:	212a6404 	addi	r4,r4,-22128
+ 802a7c0:	8002c780 	call	8002c78 <printf>
+#endif
+            panic("tcp_out:mbuf-nbuf");   /* sanity check */
+ 802a7c4:	01020174 	movhi	r4,2053
+ 802a7c8:	212a6a04 	addi	r4,r4,-22104
+ 802a7cc:	80271780 	call	8027178 <panic>
+         }
+
+         if ((m1->m_len < (unsigned)(e - MaxLnh))  /* leave room for MAC */
+ 802a7d0:	e0bfff17 	ldw	r2,-4(fp)
+ 802a7d4:	10800217 	ldw	r2,8(r2)
+ 802a7d8:	d0e06417 	ldw	r3,-32368(gp)
+ 802a7dc:	e13ffa17 	ldw	r4,-24(fp)
+ 802a7e0:	20c7c83a 	sub	r3,r4,r3
+ 802a7e4:	10c0392e 	bgeu	r2,r3,802a8cc <ip_output+0x274>
+             && ((m1->m_len & (ALIGN_TYPE - 1)) == 0)  /* and stay aligned */
+ 802a7e8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a7ec:	10800217 	ldw	r2,8(r2)
+ 802a7f0:	108000cc 	andi	r2,r2,3
+ 802a7f4:	1000351e 	bne	r2,zero,802a8cc <ip_output+0x274>
+             && ((m2->m_data - m2->pkt->nb_buff) == HDRSLEN))   /* be at start */
+ 802a7f8:	e0bffe17 	ldw	r2,-8(fp)
+ 802a7fc:	10c00317 	ldw	r3,12(r2)
+ 802a800:	e0bffe17 	ldw	r2,-8(fp)
+ 802a804:	10800117 	ldw	r2,4(r2)
+ 802a808:	10800117 	ldw	r2,4(r2)
+ 802a80c:	1885c83a 	sub	r2,r3,r2
+ 802a810:	10800e18 	cmpnei	r2,r2,56
+ 802a814:	10002d1e 	bne	r2,zero,802a8cc <ip_output+0x274>
+         {
+            MEMCPY((m2->m_data - m1->m_len), m1->m_data, m1->m_len);
+ 802a818:	e0bffe17 	ldw	r2,-8(fp)
+ 802a81c:	10c00317 	ldw	r3,12(r2)
+ 802a820:	e0bfff17 	ldw	r2,-4(fp)
+ 802a824:	10800217 	ldw	r2,8(r2)
+ 802a828:	0085c83a 	sub	r2,zero,r2
+ 802a82c:	1887883a 	add	r3,r3,r2
+ 802a830:	e0bfff17 	ldw	r2,-4(fp)
+ 802a834:	11000317 	ldw	r4,12(r2)
+ 802a838:	e0bfff17 	ldw	r2,-4(fp)
+ 802a83c:	10800217 	ldw	r2,8(r2)
+ 802a840:	100d883a 	mov	r6,r2
+ 802a844:	200b883a 	mov	r5,r4
+ 802a848:	1809883a 	mov	r4,r3
+ 802a84c:	80086b80 	call	80086b8 <memcpy>
+            m2->m_data -= m1->m_len;   /* fix target to reflect prepend */
+ 802a850:	e0bffe17 	ldw	r2,-8(fp)
+ 802a854:	10c00317 	ldw	r3,12(r2)
+ 802a858:	e0bfff17 	ldw	r2,-4(fp)
+ 802a85c:	10800217 	ldw	r2,8(r2)
+ 802a860:	0085c83a 	sub	r2,zero,r2
+ 802a864:	1887883a 	add	r3,r3,r2
+ 802a868:	e0bffe17 	ldw	r2,-8(fp)
+ 802a86c:	10c00315 	stw	r3,12(r2)
+            m2->m_len += m1->m_len;
+ 802a870:	e0bffe17 	ldw	r2,-8(fp)
+ 802a874:	10c00217 	ldw	r3,8(r2)
+ 802a878:	e0bfff17 	ldw	r2,-4(fp)
+ 802a87c:	10800217 	ldw	r2,8(r2)
+ 802a880:	1887883a 	add	r3,r3,r2
+ 802a884:	e0bffe17 	ldw	r2,-8(fp)
+ 802a888:	10c00215 	stw	r3,8(r2)
+            m_free(m1);    /* free head (copied) mbuf */
+ 802a88c:	e13fff17 	ldw	r4,-4(fp)
+ 802a890:	8029bf80 	call	8029bf8 <m_free>
+            data = m1 = m2;   /* move other mbufs up the chain */
+ 802a894:	e0bffe17 	ldw	r2,-8(fp)
+ 802a898:	e0bfff15 	stw	r2,-4(fp)
+ 802a89c:	e0bfff17 	ldw	r2,-4(fp)
+ 802a8a0:	e0bff715 	stw	r2,-36(fp)
+            m2 = m2->m_next;  /* loop to while(m2) test */
+ 802a8a4:	e0bffe17 	ldw	r2,-8(fp)
+ 802a8a8:	10800617 	ldw	r2,24(r2)
+ 802a8ac:	e0bffe15 	stw	r2,-8(fp)
+            tcpstat.tcps_oprepends++;
+ 802a8b0:	008201b4 	movhi	r2,2054
+ 802a8b4:	10b8d617 	ldw	r2,-7336(r2)
+ 802a8b8:	10c00044 	addi	r3,r2,1
+ 802a8bc:	008201b4 	movhi	r2,2054
+ 802a8c0:	10f8d615 	stw	r3,-7336(r2)
+      while (m2)  /* If we still have two or more buffers, more copying: */
+ 802a8c4:	e0bffe17 	ldw	r2,-8(fp)
+ 802a8c8:	103fae1e 	bne	r2,zero,802a784 <ip_output+0x12c>
+         }
+         else     /* if won't fit, fall to next copy */
+            break;
+      }
+
+      if (m2)  /* If all else fails, brute force copy: */
+ 802a8cc:	e0bffe17 	ldw	r2,-8(fp)
+ 802a8d0:	10006c26 	beq	r2,zero,802aa84 <ip_output+0x42c>
+      {
+         total = 0;
+ 802a8d4:	e03ffc15 	stw	zero,-16(fp)
+         for (mtmp = m1; mtmp; mtmp = mtmp->m_next)
+ 802a8d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802a8dc:	e0bffd15 	stw	r2,-12(fp)
+ 802a8e0:	00000806 	br	802a904 <ip_output+0x2ac>
+            total += mtmp->m_len;
+ 802a8e4:	e0bffd17 	ldw	r2,-12(fp)
+ 802a8e8:	10c00217 	ldw	r3,8(r2)
+ 802a8ec:	e0bffc17 	ldw	r2,-16(fp)
+ 802a8f0:	1885883a 	add	r2,r3,r2
+ 802a8f4:	e0bffc15 	stw	r2,-16(fp)
+         for (mtmp = m1; mtmp; mtmp = mtmp->m_next)
+ 802a8f8:	e0bffd17 	ldw	r2,-12(fp)
+ 802a8fc:	10800617 	ldw	r2,24(r2)
+ 802a900:	e0bffd15 	stw	r2,-12(fp)
+ 802a904:	e0bffd17 	ldw	r2,-12(fp)
+ 802a908:	103ff61e 	bne	r2,zero,802a8e4 <ip_output+0x28c>
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a90c:	01000084 	movi	r4,2
+ 802a910:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pkt = pk_alloc(total + HDRSLEN);
+ 802a914:	e0bffc17 	ldw	r2,-16(fp)
+ 802a918:	10800e04 	addi	r2,r2,56
+ 802a91c:	1009883a 	mov	r4,r2
+ 802a920:	80284340 	call	8028434 <pk_alloc>
+ 802a924:	e0bffb15 	stw	r2,-20(fp)
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802a928:	01000084 	movi	r4,2
+ 802a92c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         if (!pkt)
+ 802a930:	e0bffb17 	ldw	r2,-20(fp)
+ 802a934:	1000021e 	bne	r2,zero,802a940 <ip_output+0x2e8>
+            return ENOBUFS;
+ 802a938:	00801a44 	movi	r2,105
+ 802a93c:	0000a306 	br	802abcc <ip_output+0x574>
+         pkt->nb_prot = pkt->nb_buff + MaxLnh;
+ 802a940:	e0bffb17 	ldw	r2,-20(fp)
+ 802a944:	10800117 	ldw	r2,4(r2)
+ 802a948:	d0e06417 	ldw	r3,-32368(gp)
+ 802a94c:	10c7883a 	add	r3,r2,r3
+ 802a950:	e0bffb17 	ldw	r2,-20(fp)
+ 802a954:	10c00315 	stw	r3,12(r2)
+
+         mtmp = m1;
+ 802a958:	e0bfff17 	ldw	r2,-4(fp)
+ 802a95c:	e0bffd15 	stw	r2,-12(fp)
+         while (mtmp)
+ 802a960:	00002706 	br	802aa00 <ip_output+0x3a8>
+         {
+            MEMCPY(pkt->nb_prot, mtmp->m_data, mtmp->m_len);
+ 802a964:	e0bffb17 	ldw	r2,-20(fp)
+ 802a968:	10c00317 	ldw	r3,12(r2)
+ 802a96c:	e0bffd17 	ldw	r2,-12(fp)
+ 802a970:	11000317 	ldw	r4,12(r2)
+ 802a974:	e0bffd17 	ldw	r2,-12(fp)
+ 802a978:	10800217 	ldw	r2,8(r2)
+ 802a97c:	100d883a 	mov	r6,r2
+ 802a980:	200b883a 	mov	r5,r4
+ 802a984:	1809883a 	mov	r4,r3
+ 802a988:	80086b80 	call	80086b8 <memcpy>
+            pkt->nb_prot += mtmp->m_len;
+ 802a98c:	e0bffb17 	ldw	r2,-20(fp)
+ 802a990:	10c00317 	ldw	r3,12(r2)
+ 802a994:	e0bffd17 	ldw	r2,-12(fp)
+ 802a998:	10800217 	ldw	r2,8(r2)
+ 802a99c:	1887883a 	add	r3,r3,r2
+ 802a9a0:	e0bffb17 	ldw	r2,-20(fp)
+ 802a9a4:	10c00315 	stw	r3,12(r2)
+            pkt->nb_plen += mtmp->m_len;
+ 802a9a8:	e0bffb17 	ldw	r2,-20(fp)
+ 802a9ac:	10c00417 	ldw	r3,16(r2)
+ 802a9b0:	e0bffd17 	ldw	r2,-12(fp)
+ 802a9b4:	10800217 	ldw	r2,8(r2)
+ 802a9b8:	1887883a 	add	r3,r3,r2
+ 802a9bc:	e0bffb17 	ldw	r2,-20(fp)
+ 802a9c0:	10c00415 	stw	r3,16(r2)
+            m2 = mtmp;
+ 802a9c4:	e0bffd17 	ldw	r2,-12(fp)
+ 802a9c8:	e0bffe15 	stw	r2,-8(fp)
+            mtmp = mtmp->m_next;
+ 802a9cc:	e0bffd17 	ldw	r2,-12(fp)
+ 802a9d0:	10800617 	ldw	r2,24(r2)
+ 802a9d4:	e0bffd15 	stw	r2,-12(fp)
+            if (m2 != data)   /* save original head */
+ 802a9d8:	e0fffe17 	ldw	r3,-8(fp)
+ 802a9dc:	e0bff717 	ldw	r2,-36(fp)
+ 802a9e0:	18800226 	beq	r3,r2,802a9ec <ip_output+0x394>
+               m_free(m2);
+ 802a9e4:	e13ffe17 	ldw	r4,-8(fp)
+ 802a9e8:	8029bf80 	call	8029bf8 <m_free>
+            tcpstat.tcps_ocopies++;
+ 802a9ec:	008201b4 	movhi	r2,2054
+ 802a9f0:	10b8d817 	ldw	r2,-7328(r2)
+ 802a9f4:	10c00044 	addi	r3,r2,1
+ 802a9f8:	008201b4 	movhi	r2,2054
+ 802a9fc:	10f8d815 	stw	r3,-7328(r2)
+         while (mtmp)
+ 802aa00:	e0bffd17 	ldw	r2,-12(fp)
+ 802aa04:	103fd71e 	bne	r2,zero,802a964 <ip_output+0x30c>
+         }
+         pkt->nb_prot -= total;     /* fix data pointer */
+ 802aa08:	e0bffb17 	ldw	r2,-20(fp)
+ 802aa0c:	10c00317 	ldw	r3,12(r2)
+ 802aa10:	e0bffc17 	ldw	r2,-16(fp)
+ 802aa14:	0085c83a 	sub	r2,zero,r2
+ 802aa18:	1887883a 	add	r3,r3,r2
+ 802aa1c:	e0bffb17 	ldw	r2,-20(fp)
+ 802aa20:	10c00315 	stw	r3,12(r2)
+
+         /* release the original mbufs packet install the new one */
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802aa24:	01000084 	movi	r4,2
+ 802aa28:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(data->pkt);
+ 802aa2c:	e0bff717 	ldw	r2,-36(fp)
+ 802aa30:	10800117 	ldw	r2,4(r2)
+ 802aa34:	1009883a 	mov	r4,r2
+ 802aa38:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802aa3c:	01000084 	movi	r4,2
+ 802aa40:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         data->pkt = pkt;
+ 802aa44:	e0bff717 	ldw	r2,-36(fp)
+ 802aa48:	e0fffb17 	ldw	r3,-20(fp)
+ 802aa4c:	10c00115 	stw	r3,4(r2)
+         data->m_len = pkt->nb_plen;
+ 802aa50:	e0bffb17 	ldw	r2,-20(fp)
+ 802aa54:	10c00417 	ldw	r3,16(r2)
+ 802aa58:	e0bff717 	ldw	r2,-36(fp)
+ 802aa5c:	10c00215 	stw	r3,8(r2)
+         data->m_next = NULL;
+ 802aa60:	e0bff717 	ldw	r2,-36(fp)
+ 802aa64:	10000615 	stw	zero,24(r2)
+         data->m_data = pkt->nb_prot;
+ 802aa68:	e0bffb17 	ldw	r2,-20(fp)
+ 802aa6c:	10c00317 	ldw	r3,12(r2)
+ 802aa70:	e0bff717 	ldw	r2,-36(fp)
+ 802aa74:	10c00315 	stw	r3,12(r2)
+         data->m_len = total;
+ 802aa78:	e0fffc17 	ldw	r3,-16(fp)
+ 802aa7c:	e0bff717 	ldw	r2,-36(fp)
+ 802aa80:	10c00215 	stw	r3,8(r2)
+      }
+   }
+
+   if ((data->m_data < (data->pkt->nb_buff + MaxLnh)))
+ 802aa84:	e0bff717 	ldw	r2,-36(fp)
+ 802aa88:	10c00317 	ldw	r3,12(r2)
+ 802aa8c:	e0bff717 	ldw	r2,-36(fp)
+ 802aa90:	10800117 	ldw	r2,4(r2)
+ 802aa94:	10800117 	ldw	r2,4(r2)
+ 802aa98:	d1206417 	ldw	r4,-32368(gp)
+ 802aa9c:	1105883a 	add	r2,r2,r4
+ 802aaa0:	1880032e 	bgeu	r3,r2,802aab0 <ip_output+0x458>
+      panic("ip_output: overflow");
+ 802aaa4:	01020174 	movhi	r4,2053
+ 802aaa8:	212a6f04 	addi	r4,r4,-22084
+ 802aaac:	80271780 	call	8027178 <panic>
+
+   pkt = data->pkt;
+ 802aab0:	e0bff717 	ldw	r2,-36(fp)
+ 802aab4:	10800117 	ldw	r2,4(r2)
+ 802aab8:	e0bffb15 	stw	r2,-20(fp)
+
+   /* do we have options? */
+   if (so_optsPack)
+ 802aabc:	e0bff617 	ldw	r2,-40(fp)
+ 802aac0:	10000326 	beq	r2,zero,802aad0 <ip_output+0x478>
+	   pkt->soxopts = so_optsPack;   /* yup */
+ 802aac4:	e0bffb17 	ldw	r2,-20(fp)
+ 802aac8:	e0fff617 	ldw	r3,-40(fp)
+ 802aacc:	10c00c15 	stw	r3,48(r2)
+      panic("ip_output: no so_optsPack for the IPv6 scope");     
+   }
+#endif
+
+   /* fill in dest host for IP layer */
+   bip = (struct ip *)data->m_data;
+ 802aad0:	e0bff717 	ldw	r2,-36(fp)
+ 802aad4:	10800317 	ldw	r2,12(r2)
+ 802aad8:	e0bff915 	stw	r2,-28(fp)
+   pkt->fhost = bip->ip_dest;
+ 802aadc:	e0bff917 	ldw	r2,-28(fp)
+ 802aae0:	10c00417 	ldw	r3,16(r2)
+ 802aae4:	e0bffb17 	ldw	r2,-20(fp)
+ 802aae8:	10c00715 	stw	r3,28(r2)
+
+   /* make enough IP header for cksum calculation */
+   bip->ip_ver_ihl = 0x45;
+ 802aaec:	e0bff917 	ldw	r2,-28(fp)
+ 802aaf0:	00c01144 	movi	r3,69
+ 802aaf4:	10c00005 	stb	r3,0(r2)
+   bip->ip_len = htons(bip->ip_len);   /* make net endian for calculation */
+ 802aaf8:	e0bff917 	ldw	r2,-28(fp)
+ 802aafc:	1080008b 	ldhu	r2,2(r2)
+ 802ab00:	10bfffcc 	andi	r2,r2,65535
+ 802ab04:	1004d23a 	srli	r2,r2,8
+ 802ab08:	1007883a 	mov	r3,r2
+ 802ab0c:	e0bff917 	ldw	r2,-28(fp)
+ 802ab10:	1080008b 	ldhu	r2,2(r2)
+ 802ab14:	10bfffcc 	andi	r2,r2,65535
+ 802ab18:	1004923a 	slli	r2,r2,8
+ 802ab1c:	1884b03a 	or	r2,r3,r2
+ 802ab20:	1007883a 	mov	r3,r2
+ 802ab24:	e0bff917 	ldw	r2,-28(fp)
+ 802ab28:	10c0008d 	sth	r3,2(r2)
+   tcpp = (struct tcphdr *)ip_data(bip);
+ 802ab2c:	e0bff917 	ldw	r2,-28(fp)
+ 802ab30:	10800003 	ldbu	r2,0(r2)
+ 802ab34:	10803fcc 	andi	r2,r2,255
+ 802ab38:	100490ba 	slli	r2,r2,2
+ 802ab3c:	10800f0c 	andi	r2,r2,60
+ 802ab40:	e0fff917 	ldw	r3,-28(fp)
+ 802ab44:	1885883a 	add	r2,r3,r2
+ 802ab48:	e0bff815 	stw	r2,-32(fp)
+#ifdef CSUM_DEMO
+   if (!(tcpp->th_flags & TH_SYN))
+   tcpp->th_flags |= TH_PUSH;     /* force the PSH flag in TCP hdr */
+#endif
+   tcpp->th_sum = tcp_cksum(bip);
+ 802ab4c:	e13ff917 	ldw	r4,-28(fp)
+ 802ab50:	80400c00 	call	80400c0 <tcp_cksum>
+ 802ab54:	1007883a 	mov	r3,r2
+ 802ab58:	e0bff817 	ldw	r2,-32(fp)
+ 802ab5c:	10c0040d 	sth	r3,16(r2)
+
+   pkt->nb_prot = (char*)(bip + 1);    /* point past IP header */
+ 802ab60:	e0bff917 	ldw	r2,-28(fp)
+ 802ab64:	10c00504 	addi	r3,r2,20
+ 802ab68:	e0bffb17 	ldw	r2,-20(fp)
+ 802ab6c:	10c00315 	stw	r3,12(r2)
+   pkt->nb_plen = data->m_len - sizeof(struct ip);
+ 802ab70:	e0bff717 	ldw	r2,-36(fp)
+ 802ab74:	10800217 	ldw	r2,8(r2)
+ 802ab78:	10fffb04 	addi	r3,r2,-20
+ 802ab7c:	e0bffb17 	ldw	r2,-20(fp)
+ 802ab80:	10c00415 	stw	r3,16(r2)
+
+   e = ip_write(IPPROTO_TCP, pkt);
+ 802ab84:	e17ffb17 	ldw	r5,-20(fp)
+ 802ab88:	01000184 	movi	r4,6
+ 802ab8c:	803a9e80 	call	803a9e8 <ip_write>
+ 802ab90:	e0bffa15 	stw	r2,-24(fp)
+
+   /* ip_write() is now responsable for data->pkt, so... */
+   data->pkt = NULL;
+ 802ab94:	e0bff717 	ldw	r2,-36(fp)
+ 802ab98:	10000115 	stw	zero,4(r2)
+   m_freem(data);
+ 802ab9c:	e13ff717 	ldw	r4,-36(fp)
+ 802aba0:	8029cfc0 	call	8029cfc <m_freem>
+
+   if (e < 0)
+ 802aba4:	e0bffa17 	ldw	r2,-24(fp)
+ 802aba8:	1000070e 	bge	r2,zero,802abc8 <ip_output+0x570>
+   {
+      /* don't report dropped sends, it causes socket applications to 
+      bail when a TCP retry will fix the problem */
+      if (e == SEND_DROPPED)
+ 802abac:	e0bffa17 	ldw	r2,-24(fp)
+ 802abb0:	10bffa98 	cmpnei	r2,r2,-22
+ 802abb4:	1000021e 	bne	r2,zero,802abc0 <ip_output+0x568>
+         return 0;
+ 802abb8:	0005883a 	mov	r2,zero
+ 802abbc:	00000306 	br	802abcc <ip_output+0x574>
+      return e;
+ 802abc0:	e0bffa17 	ldw	r2,-24(fp)
+ 802abc4:	00000106 	br	802abcc <ip_output+0x574>
+   }
+   else
+      return 0;
+ 802abc8:	0005883a 	mov	r2,zero
+}
+ 802abcc:	e037883a 	mov	sp,fp
+ 802abd0:	dfc00117 	ldw	ra,4(sp)
+ 802abd4:	df000017 	ldw	fp,0(sp)
+ 802abd8:	dec00204 	addi	sp,sp,8
+ 802abdc:	f800283a 	ret
+
+0802abe0 <in_broadcast>:
+ * RETURNS: TRUE if broadcast, else FALSE
+ */
+
+int
+in_broadcast(u_long ipaddr)   /* passed in net endian */
+{
+ 802abe0:	defffe04 	addi	sp,sp,-8
+ 802abe4:	df000115 	stw	fp,4(sp)
+ 802abe8:	df000104 	addi	fp,sp,4
+ 802abec:	e13fff15 	stw	r4,-4(fp)
+   if (ipaddr == 0xffffffff)
+ 802abf0:	e0bfff17 	ldw	r2,-4(fp)
+ 802abf4:	10bfffd8 	cmpnei	r2,r2,-1
+ 802abf8:	1000021e 	bne	r2,zero,802ac04 <in_broadcast+0x24>
+      return TRUE;
+ 802abfc:	00800044 	movi	r2,1
+ 802ac00:	00000106 	br	802ac08 <in_broadcast+0x28>
+
+   return FALSE;
+ 802ac04:	0005883a 	mov	r2,zero
+}
+ 802ac08:	e037883a 	mov	sp,fp
+ 802ac0c:	df000017 	ldw	fp,0(sp)
+ 802ac10:	dec00104 	addi	sp,sp,4
+ 802ac14:	f800283a 	ret
+
+0802ac18 <np_stripoptions>:
+ * RETURNS: void
+ */
+
+void
+np_stripoptions(struct ip * ti, struct mbuf * m)
+{
+ 802ac18:	defffb04 	addi	sp,sp,-20
+ 802ac1c:	dfc00415 	stw	ra,16(sp)
+ 802ac20:	df000315 	stw	fp,12(sp)
+ 802ac24:	df000304 	addi	fp,sp,12
+ 802ac28:	e13ffe15 	stw	r4,-8(fp)
+ 802ac2c:	e17ffd15 	stw	r5,-12(fp)
+   int   ihlen;
+
+   /* get the IP header length in octets */
+   ihlen = (ti->ip_ver_ihl & 0x0f) << 2;
+ 802ac30:	e0bffe17 	ldw	r2,-8(fp)
+ 802ac34:	10800003 	ldbu	r2,0(r2)
+ 802ac38:	10803fcc 	andi	r2,r2,255
+ 802ac3c:	100490ba 	slli	r2,r2,2
+ 802ac40:	10800f0c 	andi	r2,r2,60
+ 802ac44:	e0bfff15 	stw	r2,-4(fp)
+
+   /* if it's <= 20 octets, there are no IP header options to strip */
+   if (ihlen <= 20)
+ 802ac48:	e0bfff17 	ldw	r2,-4(fp)
+ 802ac4c:	10800548 	cmpgei	r2,r2,21
+ 802ac50:	10002726 	beq	r2,zero,802acf0 <np_stripoptions+0xd8>
+      return;
+
+   /* figure out how much to strip: we want to keep the 20-octet IP header */
+   ihlen -= 20;
+ 802ac54:	e0bfff17 	ldw	r2,-4(fp)
+ 802ac58:	10bffb04 	addi	r2,r2,-20
+ 802ac5c:	e0bfff15 	stw	r2,-4(fp)
+
+   /* remove the stripped options from the IP datagram length */
+   ti->ip_len -= ihlen;
+ 802ac60:	e0bffe17 	ldw	r2,-8(fp)
+ 802ac64:	1080008b 	ldhu	r2,2(r2)
+ 802ac68:	e0ffff17 	ldw	r3,-4(fp)
+ 802ac6c:	10c5c83a 	sub	r2,r2,r3
+ 802ac70:	1007883a 	mov	r3,r2
+ 802ac74:	e0bffe17 	ldw	r2,-8(fp)
+ 802ac78:	10c0008d 	sth	r3,2(r2)
+
+   /* and from the IP header length (which will be 5*4 octets long) */
+   ti->ip_ver_ihl = (ti->ip_ver_ihl & 0xf0) | 5;
+ 802ac7c:	e0bffe17 	ldw	r2,-8(fp)
+ 802ac80:	10800003 	ldbu	r2,0(r2)
+ 802ac84:	1007883a 	mov	r3,r2
+ 802ac88:	00bffc04 	movi	r2,-16
+ 802ac8c:	1884703a 	and	r2,r3,r2
+ 802ac90:	10800154 	ori	r2,r2,5
+ 802ac94:	1007883a 	mov	r3,r2
+ 802ac98:	e0bffe17 	ldw	r2,-8(fp)
+ 802ac9c:	10c00005 	stb	r3,0(r2)
+
+   /* move the 20-octet IP header up against the IP payload */
+   MEMMOVE( ((char*)ti) + ihlen, ti, 20);
+ 802aca0:	e0bfff17 	ldw	r2,-4(fp)
+ 802aca4:	e0fffe17 	ldw	r3,-8(fp)
+ 802aca8:	1885883a 	add	r2,r3,r2
+ 802acac:	01800504 	movi	r6,20
+ 802acb0:	e17ffe17 	ldw	r5,-8(fp)
+ 802acb4:	1009883a 	mov	r4,r2
+ 802acb8:	80087b80 	call	80087b8 <memmove>
+   m->m_len -= ihlen;
+ 802acbc:	e0bffd17 	ldw	r2,-12(fp)
+ 802acc0:	10c00217 	ldw	r3,8(r2)
+ 802acc4:	e0bfff17 	ldw	r2,-4(fp)
+ 802acc8:	1887c83a 	sub	r3,r3,r2
+ 802accc:	e0bffd17 	ldw	r2,-12(fp)
+ 802acd0:	10c00215 	stw	r3,8(r2)
+   m->m_data += ihlen;
+ 802acd4:	e0bffd17 	ldw	r2,-12(fp)
+ 802acd8:	10c00317 	ldw	r3,12(r2)
+ 802acdc:	e0bfff17 	ldw	r2,-4(fp)
+ 802ace0:	1887883a 	add	r3,r3,r2
+ 802ace4:	e0bffd17 	ldw	r2,-12(fp)
+ 802ace8:	10c00315 	stw	r3,12(r2)
+ 802acec:	00000106 	br	802acf4 <np_stripoptions+0xdc>
+      return;
+ 802acf0:	0001883a 	nop
+}
+ 802acf4:	e037883a 	mov	sp,fp
+ 802acf8:	dfc00117 	ldw	ra,4(sp)
+ 802acfc:	df000017 	ldw	fp,0(sp)
+ 802ad00:	dec00204 	addi	sp,sp,8
+ 802ad04:	f800283a 	ret
+
+0802ad08 <so_icmpdu>:
+ * RETURNS: 
+ */
+
+void
+so_icmpdu(PACKET p, struct destun * pdp)
+{
+ 802ad08:	defff304 	addi	sp,sp,-52
+ 802ad0c:	dfc00c15 	stw	ra,48(sp)
+ 802ad10:	df000b15 	stw	fp,44(sp)
+ 802ad14:	df000b04 	addi	fp,sp,44
+ 802ad18:	e13ff815 	stw	r4,-32(fp)
+ 802ad1c:	e17ff715 	stw	r5,-36(fp)
+   struct inpcb * inp;
+   struct socket *   so;
+   struct tcpcb * tp;
+
+   /* extract information about packet which generated DU */
+   fhost = htonl(pdp->dip.ip_dest);
+ 802ad20:	e0bff717 	ldw	r2,-36(fp)
+ 802ad24:	10800617 	ldw	r2,24(r2)
+ 802ad28:	1006d63a 	srli	r3,r2,24
+ 802ad2c:	e0bff717 	ldw	r2,-36(fp)
+ 802ad30:	10800617 	ldw	r2,24(r2)
+ 802ad34:	1004d23a 	srli	r2,r2,8
+ 802ad38:	10bfc00c 	andi	r2,r2,65280
+ 802ad3c:	1886b03a 	or	r3,r3,r2
+ 802ad40:	e0bff717 	ldw	r2,-36(fp)
+ 802ad44:	10800617 	ldw	r2,24(r2)
+ 802ad48:	1004923a 	slli	r2,r2,8
+ 802ad4c:	10803fec 	andhi	r2,r2,255
+ 802ad50:	1886b03a 	or	r3,r3,r2
+ 802ad54:	e0bff717 	ldw	r2,-36(fp)
+ 802ad58:	10800617 	ldw	r2,24(r2)
+ 802ad5c:	1004963a 	slli	r2,r2,24
+ 802ad60:	1884b03a 	or	r2,r3,r2
+ 802ad64:	e0bffe15 	stw	r2,-8(fp)
+   lhost = htonl(pdp->dip.ip_src);
+ 802ad68:	e0bff717 	ldw	r2,-36(fp)
+ 802ad6c:	10800517 	ldw	r2,20(r2)
+ 802ad70:	1006d63a 	srli	r3,r2,24
+ 802ad74:	e0bff717 	ldw	r2,-36(fp)
+ 802ad78:	10800517 	ldw	r2,20(r2)
+ 802ad7c:	1004d23a 	srli	r2,r2,8
+ 802ad80:	10bfc00c 	andi	r2,r2,65280
+ 802ad84:	1886b03a 	or	r3,r3,r2
+ 802ad88:	e0bff717 	ldw	r2,-36(fp)
+ 802ad8c:	10800517 	ldw	r2,20(r2)
+ 802ad90:	1004923a 	slli	r2,r2,8
+ 802ad94:	10803fec 	andhi	r2,r2,255
+ 802ad98:	1886b03a 	or	r3,r3,r2
+ 802ad9c:	e0bff717 	ldw	r2,-36(fp)
+ 802ada0:	10800517 	ldw	r2,20(r2)
+ 802ada4:	1004963a 	slli	r2,r2,24
+ 802ada8:	1884b03a 	or	r2,r3,r2
+ 802adac:	e0bffd15 	stw	r2,-12(fp)
+   lport = htons(*(unshort*)(&pdp->ddata[0]));
+ 802adb0:	e0bff717 	ldw	r2,-36(fp)
+ 802adb4:	10800704 	addi	r2,r2,28
+ 802adb8:	1080000b 	ldhu	r2,0(r2)
+ 802adbc:	10bfffcc 	andi	r2,r2,65535
+ 802adc0:	1004d23a 	srli	r2,r2,8
+ 802adc4:	1007883a 	mov	r3,r2
+ 802adc8:	e0bff717 	ldw	r2,-36(fp)
+ 802adcc:	10800704 	addi	r2,r2,28
+ 802add0:	1080000b 	ldhu	r2,0(r2)
+ 802add4:	10bfffcc 	andi	r2,r2,65535
+ 802add8:	1004923a 	slli	r2,r2,8
+ 802addc:	1884b03a 	or	r2,r3,r2
+ 802ade0:	e0bffc8d 	sth	r2,-14(fp)
+   fport = htons(*(unshort*)(&pdp->ddata[2]));
+ 802ade4:	e0bff717 	ldw	r2,-36(fp)
+ 802ade8:	10800784 	addi	r2,r2,30
+ 802adec:	1080000b 	ldhu	r2,0(r2)
+ 802adf0:	10bfffcc 	andi	r2,r2,65535
+ 802adf4:	1004d23a 	srli	r2,r2,8
+ 802adf8:	1007883a 	mov	r3,r2
+ 802adfc:	e0bff717 	ldw	r2,-36(fp)
+ 802ae00:	10800784 	addi	r2,r2,30
+ 802ae04:	1080000b 	ldhu	r2,0(r2)
+ 802ae08:	10bfffcc 	andi	r2,r2,65535
+ 802ae0c:	1004923a 	slli	r2,r2,8
+ 802ae10:	1884b03a 	or	r2,r3,r2
+ 802ae14:	e0bffc0d 	sth	r2,-16(fp)
+#ifndef IP_PMTU
+   /* if it's a datagram-too-big message, ignore it -- As the
+    * build isn't using PMTU Discovery this packet is most 
+    * probably a Denial of Service Attack.
+    */
+    if(pdp->dcode == DSTFRAG)
+ 802ae18:	e0bff717 	ldw	r2,-36(fp)
+ 802ae1c:	10800043 	ldbu	r2,1(r2)
+ 802ae20:	10803fcc 	andi	r2,r2,255
+ 802ae24:	1080201c 	xori	r2,r2,128
+ 802ae28:	10bfe004 	addi	r2,r2,-128
+ 802ae2c:	10800118 	cmpnei	r2,r2,4
+ 802ae30:	10006e26 	beq	r2,zero,802afec <so_icmpdu+0x2e4>
+       goto done;
+    }
+#endif   /* IP_PMTU */
+
+   /* if it's a TCP connection, clean it up */
+   if (pdp->dip.ip_prot == TCPTP)
+ 802ae34:	e0bff717 	ldw	r2,-36(fp)
+ 802ae38:	10800443 	ldbu	r2,17(r2)
+ 802ae3c:	10803fcc 	andi	r2,r2,255
+ 802ae40:	10800198 	cmpnei	r2,r2,6
+ 802ae44:	1000221e 	bne	r2,zero,802aed0 <so_icmpdu+0x1c8>
+   {
+      /* find associated data structs and socket */
+      inp = in_pcblookup(&tcb, fhost, fport, lhost, lport, INPLOOKUP_WILDCARD);
+ 802ae48:	e13ffc0b 	ldhu	r4,-16(fp)
+ 802ae4c:	e0bffc8b 	ldhu	r2,-14(fp)
+ 802ae50:	00c00044 	movi	r3,1
+ 802ae54:	d8c00115 	stw	r3,4(sp)
+ 802ae58:	d8800015 	stw	r2,0(sp)
+ 802ae5c:	e1fffd17 	ldw	r7,-12(fp)
+ 802ae60:	200d883a 	mov	r6,r4
+ 802ae64:	e17ffe17 	ldw	r5,-8(fp)
+ 802ae68:	010201b4 	movhi	r4,2054
+ 802ae6c:	21389904 	addi	r4,r4,-7580
+ 802ae70:	8040b600 	call	8040b60 <in_pcblookup>
+ 802ae74:	e0bffb15 	stw	r2,-20(fp)
+      if (inp == 0)
+ 802ae78:	e0bffb17 	ldw	r2,-20(fp)
+ 802ae7c:	10005d26 	beq	r2,zero,802aff4 <so_icmpdu+0x2ec>
+         goto done;
+      so = inp->inp_socket;
+ 802ae80:	e0bffb17 	ldw	r2,-20(fp)
+ 802ae84:	10800817 	ldw	r2,32(r2)
+ 802ae88:	e0bffa15 	stw	r2,-24(fp)
+      if (so == 0)
+ 802ae8c:	e0bffa17 	ldw	r2,-24(fp)
+ 802ae90:	10005a26 	beq	r2,zero,802affc <so_icmpdu+0x2f4>
+         goto done;
+      tp = intotcpcb(inp);
+ 802ae94:	e0bffb17 	ldw	r2,-20(fp)
+ 802ae98:	10800917 	ldw	r2,36(r2)
+ 802ae9c:	e0bff915 	stw	r2,-28(fp)
+      if (tp)
+ 802aea0:	e0bff917 	ldw	r2,-28(fp)
+ 802aea4:	10000626 	beq	r2,zero,802aec0 <so_icmpdu+0x1b8>
+      {
+         if (tp->t_state <= TCPS_LISTEN)
+ 802aea8:	e0bff917 	ldw	r2,-28(fp)
+ 802aeac:	10800217 	ldw	r2,8(r2)
+ 802aeb0:	10800088 	cmpgei	r2,r2,2
+ 802aeb4:	10005326 	beq	r2,zero,802b004 <so_icmpdu+0x2fc>
+               goto done;
+        }
+   }
+#endif
+
+         tcp_close(tp);
+ 802aeb8:	e13ff917 	ldw	r4,-28(fp)
+ 802aebc:	80350e80 	call	80350e8 <tcp_close>
+      }
+      so->so_error = ECONNREFUSED;  /* set error for socket owner */
+ 802aec0:	e0bffa17 	ldw	r2,-24(fp)
+ 802aec4:	00c01bc4 	movi	r3,111
+ 802aec8:	10c00615 	stw	r3,24(r2)
+ 802aecc:	00005406 	br	802b020 <so_icmpdu+0x318>
+   }   
+#ifdef UDP_SOCKETS   /* this sockets layer supports UDP too */
+   else if(pdp->dip.ip_prot == UDP_PROT)
+ 802aed0:	e0bff717 	ldw	r2,-36(fp)
+ 802aed4:	10800443 	ldbu	r2,17(r2)
+ 802aed8:	10803fcc 	andi	r2,r2,255
+ 802aedc:	10800458 	cmpnei	r2,r2,17
+ 802aee0:	10004a1e 	bne	r2,zero,802b00c <so_icmpdu+0x304>
+   {
+      UDPCONN tmp;
+      /* search udp table (which keeps hosts in net endian) */
+      for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 802aee4:	d0a09e17 	ldw	r2,-32136(gp)
+ 802aee8:	e0bfff15 	stw	r2,-4(fp)
+ 802aeec:	00002106 	br	802af74 <so_icmpdu+0x26c>
+         if ((tmp->u_fport == fport || tmp->u_fport == 0) &&
+ 802aef0:	e0bfff17 	ldw	r2,-4(fp)
+ 802aef4:	1080020b 	ldhu	r2,8(r2)
+ 802aef8:	e0fffc0b 	ldhu	r3,-16(fp)
+ 802aefc:	10bfffcc 	andi	r2,r2,65535
+ 802af00:	18800426 	beq	r3,r2,802af14 <so_icmpdu+0x20c>
+ 802af04:	e0bfff17 	ldw	r2,-4(fp)
+ 802af08:	1080020b 	ldhu	r2,8(r2)
+ 802af0c:	10bfffcc 	andi	r2,r2,65535
+ 802af10:	1000151e 	bne	r2,zero,802af68 <so_icmpdu+0x260>
+             (tmp->u_fhost == htonl(fhost)) &&
+ 802af14:	e0bfff17 	ldw	r2,-4(fp)
+ 802af18:	10c00417 	ldw	r3,16(r2)
+ 802af1c:	e0bffe17 	ldw	r2,-8(fp)
+ 802af20:	1008d63a 	srli	r4,r2,24
+ 802af24:	e0bffe17 	ldw	r2,-8(fp)
+ 802af28:	1004d23a 	srli	r2,r2,8
+ 802af2c:	10bfc00c 	andi	r2,r2,65280
+ 802af30:	2088b03a 	or	r4,r4,r2
+ 802af34:	e0bffe17 	ldw	r2,-8(fp)
+ 802af38:	1004923a 	slli	r2,r2,8
+ 802af3c:	10803fec 	andhi	r2,r2,255
+ 802af40:	2088b03a 	or	r4,r4,r2
+ 802af44:	e0bffe17 	ldw	r2,-8(fp)
+ 802af48:	1004963a 	slli	r2,r2,24
+ 802af4c:	2084b03a 	or	r2,r4,r2
+         if ((tmp->u_fport == fport || tmp->u_fport == 0) &&
+ 802af50:	1880051e 	bne	r3,r2,802af68 <so_icmpdu+0x260>
+             (tmp->u_lport == lport))
+ 802af54:	e0bfff17 	ldw	r2,-4(fp)
+ 802af58:	1080018b 	ldhu	r2,6(r2)
+             (tmp->u_fhost == htonl(fhost)) &&
+ 802af5c:	e0fffc8b 	ldhu	r3,-14(fp)
+ 802af60:	10bfffcc 	andi	r2,r2,65535
+ 802af64:	18800626 	beq	r3,r2,802af80 <so_icmpdu+0x278>
+      for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 802af68:	e0bfff17 	ldw	r2,-4(fp)
+ 802af6c:	10800017 	ldw	r2,0(r2)
+ 802af70:	e0bfff15 	stw	r2,-4(fp)
+ 802af74:	e0bfff17 	ldw	r2,-4(fp)
+ 802af78:	103fdd1e 	bne	r2,zero,802aef0 <so_icmpdu+0x1e8>
+ 802af7c:	00000106 	br	802af84 <so_icmpdu+0x27c>
+         {
+            break;   /* found our UDP table entry */
+ 802af80:	0001883a 	nop
+         }
+      if (!tmp) 
+ 802af84:	e0bfff17 	ldw	r2,-4(fp)
+ 802af88:	10002226 	beq	r2,zero,802b014 <so_icmpdu+0x30c>
+         goto done;
+      so = (struct socket *)tmp->u_data;
+ 802af8c:	e0bfff17 	ldw	r2,-4(fp)
+ 802af90:	10800617 	ldw	r2,24(r2)
+ 802af94:	e0bffa15 	stw	r2,-24(fp)
+      /* May be non-socket (lightweight) UDP connection. */
+      if (so->so_type != SOCK_DGRAM)
+ 802af98:	e0bffa17 	ldw	r2,-24(fp)
+ 802af9c:	10800983 	ldbu	r2,38(r2)
+ 802afa0:	10803fcc 	andi	r2,r2,255
+ 802afa4:	1080201c 	xori	r2,r2,128
+ 802afa8:	10bfe004 	addi	r2,r2,-128
+ 802afac:	108000a0 	cmpeqi	r2,r2,2
+ 802afb0:	10001a26 	beq	r2,zero,802b01c <so_icmpdu+0x314>
+         goto done;
+      so->so_error = ECONNREFUSED;  /* set error for socket owner */
+ 802afb4:	e0bffa17 	ldw	r2,-24(fp)
+ 802afb8:	00c01bc4 	movi	r3,111
+ 802afbc:	10c00615 	stw	r3,24(r2)
+      /* do a select() notify on socket here */
+      sorwakeup(so);
+ 802afc0:	e0bffa17 	ldw	r2,-24(fp)
+ 802afc4:	10800a04 	addi	r2,r2,40
+ 802afc8:	100b883a 	mov	r5,r2
+ 802afcc:	e13ffa17 	ldw	r4,-24(fp)
+ 802afd0:	802f94c0 	call	802f94c <sbwakeup>
+      sowwakeup(so);
+ 802afd4:	e0bffa17 	ldw	r2,-24(fp)
+ 802afd8:	10801204 	addi	r2,r2,72
+ 802afdc:	100b883a 	mov	r5,r2
+ 802afe0:	e13ffa17 	ldw	r4,-24(fp)
+ 802afe4:	802f94c0 	call	802f94c <sbwakeup>
+ 802afe8:	00000d06 	br	802b020 <so_icmpdu+0x318>
+       goto done;
+ 802afec:	0001883a 	nop
+ 802aff0:	00000b06 	br	802b020 <so_icmpdu+0x318>
+         goto done;
+ 802aff4:	0001883a 	nop
+ 802aff8:	00000906 	br	802b020 <so_icmpdu+0x318>
+         goto done;
+ 802affc:	0001883a 	nop
+ 802b000:	00000706 	br	802b020 <so_icmpdu+0x318>
+            goto done;
+ 802b004:	0001883a 	nop
+ 802b008:	00000506 	br	802b020 <so_icmpdu+0x318>
+   }
+#endif   /* UDP_SOCKETS */
+   else
+      goto done;
+ 802b00c:	0001883a 	nop
+ 802b010:	00000306 	br	802b020 <so_icmpdu+0x318>
+         goto done;
+ 802b014:	0001883a 	nop
+ 802b018:	00000106 	br	802b020 <so_icmpdu+0x318>
+         goto done;
+ 802b01c:	0001883a 	nop
+   if (pdp->dcode == DSTFRAG)
+      pmtucache_set(pdp->dip.ip_dest, htons(pdp->dno2));
+#endif   /* IP_PMTU */
+
+done:
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 802b020:	01000084 	movi	r4,2
+ 802b024:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p); /* done with original packet */
+ 802b028:	e13ff817 	ldw	r4,-32(fp)
+ 802b02c:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 802b030:	01000084 	movi	r4,2
+ 802b034:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return;
+ 802b038:	0001883a 	nop
+}
+ 802b03c:	e037883a 	mov	sp,fp
+ 802b040:	dfc00117 	ldw	ra,4(sp)
+ 802b044:	df000017 	ldw	fp,0(sp)
+ 802b048:	dec00204 	addi	sp,sp,8
+ 802b04c:	f800283a 	ret
+
+0802b050 <tcp_tick>:
+unsigned long nextslow = 0L;     /* next slow tcp timer time */
+static int in_tcptick = 0;       /* reentry gaurd */
+
+void
+tcp_tick()
+{
+ 802b050:	defffe04 	addi	sp,sp,-8
+ 802b054:	dfc00115 	stw	ra,4(sp)
+ 802b058:	df000015 	stw	fp,0(sp)
+ 802b05c:	d839883a 	mov	fp,sp
+   /* guard against re-entry */
+   if (in_tcptick)
+ 802b060:	d0a08217 	ldw	r2,-32248(gp)
+ 802b064:	1000121e 	bne	r2,zero,802b0b0 <tcp_tick+0x60>
+      return;
+   in_tcptick++;
+ 802b068:	d0a08217 	ldw	r2,-32248(gp)
+ 802b06c:	10800044 	addi	r2,r2,1
+ 802b070:	d0a08215 	stw	r2,-32248(gp)
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802b074:	0009883a 	mov	r4,zero
+ 802b078:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   if (cticks >= nextslow) /* time to do it again */
+ 802b07c:	d0e07d17 	ldw	r3,-32268(gp)
+ 802b080:	d0a08117 	ldw	r2,-32252(gp)
+ 802b084:	18800436 	bltu	r3,r2,802b098 <tcp_tick+0x48>
+   {
+      tcp_slowtimo();      /* call routine in BSD tcp_timr.c */
+ 802b088:	80353080 	call	8035308 <tcp_slowtimo>
+#ifdef CSUM_DEMO
+      nextslow = cticks + (TPS/5);  /* another 200 ms */
+#else
+      nextslow = cticks + (TPS/2);  /* another 500 ms */
+ 802b08c:	d0a07d17 	ldw	r2,-32268(gp)
+ 802b090:	10800c84 	addi	r2,r2,50
+ 802b094:	d0a08115 	stw	r2,-32252(gp)
+
+#ifdef DO_DELAY_ACKS
+   tcp_fasttimo();
+#endif   /* DO_DELAY_ACKS */
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b098:	0009883a 	mov	r4,zero
+ 802b09c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   in_tcptick--;
+ 802b0a0:	d0a08217 	ldw	r2,-32248(gp)
+ 802b0a4:	10bfffc4 	addi	r2,r2,-1
+ 802b0a8:	d0a08215 	stw	r2,-32248(gp)
+ 802b0ac:	00000106 	br	802b0b4 <tcp_tick+0x64>
+      return;
+ 802b0b0:	0001883a 	nop
+}
+ 802b0b4:	e037883a 	mov	sp,fp
+ 802b0b8:	dfc00117 	ldw	ra,4(sp)
+ 802b0bc:	df000017 	ldw	fp,0(sp)
+ 802b0c0:	dec00204 	addi	sp,sp,8
+ 802b0c4:	f800283a 	ret
+
+0802b0c8 <rawip_lookup>:
+ *          or NULL if no matching raw IP endpoint is found.
+ */
+
+struct ipraw_ep *
+rawip_lookup(struct socket * so)
+{
+ 802b0c8:	defffd04 	addi	sp,sp,-12
+ 802b0cc:	df000215 	stw	fp,8(sp)
+ 802b0d0:	df000204 	addi	fp,sp,8
+ 802b0d4:	e13ffe15 	stw	r4,-8(fp)
+   struct ipraw_ep * tmp;
+
+   for (tmp = ipraw_eps; tmp; tmp = tmp->ipr_next)
+ 802b0d8:	d0a09b17 	ldw	r2,-32148(gp)
+ 802b0dc:	e0bfff15 	stw	r2,-4(fp)
+ 802b0e0:	00000906 	br	802b108 <rawip_lookup+0x40>
+      if (tmp->ipr_data == (void*)so)
+ 802b0e4:	e0bfff17 	ldw	r2,-4(fp)
+ 802b0e8:	10800417 	ldw	r2,16(r2)
+ 802b0ec:	e0fffe17 	ldw	r3,-8(fp)
+ 802b0f0:	1880021e 	bne	r3,r2,802b0fc <rawip_lookup+0x34>
+      return (tmp);
+ 802b0f4:	e0bfff17 	ldw	r2,-4(fp)
+ 802b0f8:	00000606 	br	802b114 <rawip_lookup+0x4c>
+   for (tmp = ipraw_eps; tmp; tmp = tmp->ipr_next)
+ 802b0fc:	e0bfff17 	ldw	r2,-4(fp)
+ 802b100:	10800017 	ldw	r2,0(r2)
+ 802b104:	e0bfff15 	stw	r2,-4(fp)
+ 802b108:	e0bfff17 	ldw	r2,-4(fp)
+ 802b10c:	103ff51e 	bne	r2,zero,802b0e4 <rawip_lookup+0x1c>
+
+   return NULL;   /* didn't find it */
+ 802b110:	0005883a 	mov	r2,zero
+}
+ 802b114:	e037883a 	mov	sp,fp
+ 802b118:	df000017 	ldw	fp,0(sp)
+ 802b11c:	dec00104 	addi	sp,sp,4
+ 802b120:	f800283a 	ret
+
+0802b124 <rawip_soinput>:
+ *          indicates that the packet has not been accepted.
+ */
+
+int
+rawip_soinput(PACKET pkt, void * so_ptr)
+{
+ 802b124:	defff504 	addi	sp,sp,-44
+ 802b128:	dfc00a15 	stw	ra,40(sp)
+ 802b12c:	df000915 	stw	fp,36(sp)
+ 802b130:	df000904 	addi	fp,sp,36
+ 802b134:	e13ff815 	stw	r4,-32(fp)
+ 802b138:	e17ff715 	stw	r5,-36(fp)
+   struct mbuf *  m_in;    /* packet/data mbuf */
+   struct socket *   so =  (struct  socket *)so_ptr;
+ 802b13c:	e0bff717 	ldw	r2,-36(fp)
+ 802b140:	e0bfff15 	stw	r2,-4(fp)
+   struct sockaddr_in   sin;
+
+   LOCK_NET_RESOURCE(NET_RESID); 
+ 802b144:	0009883a 	mov	r4,zero
+ 802b148:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* make sure we're not flooding input buffers */
+   if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat)
+ 802b14c:	e0bfff17 	ldw	r2,-4(fp)
+ 802b150:	10c00a17 	ldw	r3,40(r2)
+ 802b154:	e0bff817 	ldw	r2,-32(fp)
+ 802b158:	10800417 	ldw	r2,16(r2)
+ 802b15c:	1887883a 	add	r3,r3,r2
+ 802b160:	e0bfff17 	ldw	r2,-4(fp)
+ 802b164:	10800b17 	ldw	r2,44(r2)
+ 802b168:	18800436 	bltu	r3,r2,802b17c <rawip_soinput+0x58>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b16c:	0009883a 	mov	r4,zero
+ 802b170:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 802b174:	00801a44 	movi	r2,105
+ 802b178:	00005606 	br	802b2d4 <rawip_soinput+0x1b0>
+   }
+
+   /* alloc mbuf for received data */
+   m_in = m_getnbuf(MT_RXDATA, 0);
+ 802b17c:	000b883a 	mov	r5,zero
+ 802b180:	01000044 	movi	r4,1
+ 802b184:	8029a700 	call	8029a70 <m_getnbuf>
+ 802b188:	e0bffe15 	stw	r2,-8(fp)
+   if (!m_in)
+ 802b18c:	e0bffe17 	ldw	r2,-8(fp)
+ 802b190:	1000041e 	bne	r2,zero,802b1a4 <rawip_soinput+0x80>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b194:	0009883a 	mov	r4,zero
+ 802b198:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 802b19c:	00801a44 	movi	r2,105
+ 802b1a0:	00004c06 	br	802b2d4 <rawip_soinput+0x1b0>
+   }
+
+   /* set data mbuf to point to start of IP header */
+   m_in->pkt = pkt;
+ 802b1a4:	e0bffe17 	ldw	r2,-8(fp)
+ 802b1a8:	e0fff817 	ldw	r3,-32(fp)
+ 802b1ac:	10c00115 	stw	r3,4(r2)
+   m_in->m_base = pkt->nb_buff;
+ 802b1b0:	e0bff817 	ldw	r2,-32(fp)
+ 802b1b4:	10c00117 	ldw	r3,4(r2)
+ 802b1b8:	e0bffe17 	ldw	r2,-8(fp)
+ 802b1bc:	10c00415 	stw	r3,16(r2)
+   m_in->m_memsz = pkt->nb_blen;
+ 802b1c0:	e0bff817 	ldw	r2,-32(fp)
+ 802b1c4:	10c00217 	ldw	r3,8(r2)
+ 802b1c8:	e0bffe17 	ldw	r2,-8(fp)
+ 802b1cc:	10c00515 	stw	r3,20(r2)
+   m_in->m_data = pkt->nb_prot;
+ 802b1d0:	e0bff817 	ldw	r2,-32(fp)
+ 802b1d4:	10c00317 	ldw	r3,12(r2)
+ 802b1d8:	e0bffe17 	ldw	r2,-8(fp)
+ 802b1dc:	10c00315 	stw	r3,12(r2)
+   m_in->m_len = pkt->nb_plen;
+ 802b1e0:	e0bff817 	ldw	r2,-32(fp)
+ 802b1e4:	10c00417 	ldw	r3,16(r2)
+ 802b1e8:	e0bffe17 	ldw	r2,-8(fp)
+ 802b1ec:	10c00215 	stw	r3,8(r2)
+
+   /* if this socket doesn't have IP_HDRINCL set, adjust the
+    * mbuf to skip past the IP header
+    */
+   if (!(so->so_options & SO_HDRINCL))
+ 802b1f0:	e0bfff17 	ldw	r2,-4(fp)
+ 802b1f4:	10800417 	ldw	r2,16(r2)
+ 802b1f8:	1088000c 	andi	r2,r2,8192
+ 802b1fc:	1000131e 	bne	r2,zero,802b24c <rawip_soinput+0x128>
+   {
+      unsigned int ihl = 
+         (((struct ip *)(pkt->nb_prot))->ip_ver_ihl & 0x0f) << 2;
+ 802b200:	e0bff817 	ldw	r2,-32(fp)
+ 802b204:	10800317 	ldw	r2,12(r2)
+ 802b208:	10800003 	ldbu	r2,0(r2)
+ 802b20c:	10803fcc 	andi	r2,r2,255
+ 802b210:	100490ba 	slli	r2,r2,2
+      unsigned int ihl = 
+ 802b214:	10800f0c 	andi	r2,r2,60
+ 802b218:	e0bffd15 	stw	r2,-12(fp)
+      m_in->m_data += ihl;
+ 802b21c:	e0bffe17 	ldw	r2,-8(fp)
+ 802b220:	10c00317 	ldw	r3,12(r2)
+ 802b224:	e0bffd17 	ldw	r2,-12(fp)
+ 802b228:	1887883a 	add	r3,r3,r2
+ 802b22c:	e0bffe17 	ldw	r2,-8(fp)
+ 802b230:	10c00315 	stw	r3,12(r2)
+      m_in->m_len -= ihl;
+ 802b234:	e0bffe17 	ldw	r2,-8(fp)
+ 802b238:	10c00217 	ldw	r3,8(r2)
+ 802b23c:	e0bffd17 	ldw	r2,-12(fp)
+ 802b240:	1887c83a 	sub	r3,r3,r2
+ 802b244:	e0bffe17 	ldw	r2,-8(fp)
+ 802b248:	10c00215 	stw	r3,8(r2)
+   }
+
+   /* fill in net address info for pass to socket append()ers */
+   sin.sin_addr.s_addr = pkt->fhost;
+ 802b24c:	e0bff817 	ldw	r2,-32(fp)
+ 802b250:	10800717 	ldw	r2,28(r2)
+ 802b254:	e0bffa15 	stw	r2,-24(fp)
+   sin.sin_port = 0;
+ 802b258:	e03ff98d 	sth	zero,-26(fp)
+   sin.sin_family = AF_INET;
+ 802b25c:	00800084 	movi	r2,2
+ 802b260:	e0bff90d 	sth	r2,-28(fp)
+
+   /* attempt to append address information to mbuf */
+   if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in))
+ 802b264:	e0bfff17 	ldw	r2,-4(fp)
+ 802b268:	10800a04 	addi	r2,r2,40
+ 802b26c:	e0fff904 	addi	r3,fp,-28
+ 802b270:	e1bffe17 	ldw	r6,-8(fp)
+ 802b274:	180b883a 	mov	r5,r3
+ 802b278:	1009883a 	mov	r4,r2
+ 802b27c:	802fc740 	call	802fc74 <sbappendaddr>
+ 802b280:	1000081e 	bne	r2,zero,802b2a4 <rawip_soinput+0x180>
+   {
+      /* set the pkt field in the mbuf to NULL so m_free() below wont 
+       * free the packet buffer, because that is left to the 
+       * underlying stack
+       */
+      m_in->pkt = NULL;
+ 802b284:	e0bffe17 	ldw	r2,-8(fp)
+ 802b288:	10000115 	stw	zero,4(r2)
+      /* free only the mbuf itself */
+      m_free(m_in);
+ 802b28c:	e13ffe17 	ldw	r4,-8(fp)
+ 802b290:	8029bf80 	call	8029bf8 <m_free>
+      /* return error condition so caller can free the packet buffer */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b294:	0009883a 	mov	r4,zero
+ 802b298:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 802b29c:	00801a44 	movi	r2,105
+ 802b2a0:	00000c06 	br	802b2d4 <rawip_soinput+0x1b0>
+   }
+
+   tcp_wakeup(&so->so_rcv);   /* wake anyone waiting for this */
+ 802b2a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802b2a8:	10800a04 	addi	r2,r2,40
+ 802b2ac:	1009883a 	mov	r4,r2
+ 802b2b0:	8027ba00 	call	8027ba0 <tcp_wakeup>
+
+   sorwakeup(so);    /* wake up selects too */
+ 802b2b4:	e0bfff17 	ldw	r2,-4(fp)
+ 802b2b8:	10800a04 	addi	r2,r2,40
+ 802b2bc:	100b883a 	mov	r5,r2
+ 802b2c0:	e13fff17 	ldw	r4,-4(fp)
+ 802b2c4:	802f94c0 	call	802f94c <sbwakeup>
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b2c8:	0009883a 	mov	r4,zero
+ 802b2cc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return 0;
+ 802b2d0:	0005883a 	mov	r2,zero
+}
+ 802b2d4:	e037883a 	mov	sp,fp
+ 802b2d8:	dfc00117 	ldw	ra,4(sp)
+ 802b2dc:	df000017 	ldw	fp,0(sp)
+ 802b2e0:	dec00204 	addi	sp,sp,8
+ 802b2e4:	f800283a 	ret
+
+0802b2e8 <rawip_usrreq>:
+
+int
+rawip_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+ 802b2e8:	deffef04 	addi	sp,sp,-68
+ 802b2ec:	dfc01015 	stw	ra,64(sp)
+ 802b2f0:	df000f15 	stw	fp,60(sp)
+ 802b2f4:	dc000e15 	stw	r16,56(sp)
+ 802b2f8:	df000f04 	addi	fp,sp,60
+ 802b2fc:	e13ff415 	stw	r4,-48(fp)
+ 802b300:	e17ff315 	stw	r5,-52(fp)
+ 802b304:	e1bff215 	stw	r6,-56(fp)
+   u_char prot;
+   struct ip * pip;
+   int   req;
+   NET   ifp;     /* ptr to network interface structure */
+
+   req = so->so_req;    /* get request from socket struct */
+ 802b308:	e0bff417 	ldw	r2,-48(fp)
+ 802b30c:	10800717 	ldw	r2,28(r2)
+ 802b310:	e0bffa15 	stw	r2,-24(fp)
+
+   switch (req) 
+ 802b314:	e0bffa17 	ldw	r2,-24(fp)
+ 802b318:	10800468 	cmpgeui	r2,r2,17
+ 802b31c:	1001b91e 	bne	r2,zero,802ba04 <rawip_usrreq+0x71c>
+ 802b320:	e0bffa17 	ldw	r2,-24(fp)
+ 802b324:	100690ba 	slli	r3,r2,2
+ 802b328:	008200f4 	movhi	r2,2051
+ 802b32c:	1885883a 	add	r2,r3,r2
+ 802b330:	10acce17 	ldw	r2,-19656(r2)
+ 802b334:	1000683a 	jmp	r2
+ 802b338:	0802b37c 	xorhi	zero,at,2765
+ 802b33c:	0802b404 	addi	zero,at,2768
+ 802b340:	0802b440 	call	802b44 <OSCtxSw_SWITCH_PC+0x802b04>
+ 802b344:	0802ba04 	addi	zero,at,2792
+ 802b348:	0802b440 	call	802b44 <OSCtxSw_SWITCH_PC+0x802b04>
+ 802b34c:	0802ba04 	addi	zero,at,2792
+ 802b350:	0802b9f8 	rdprs	zero,at,2791
+ 802b354:	0802ba04 	addi	zero,at,2792
+ 802b358:	0802b9f8 	rdprs	zero,at,2791
+ 802b35c:	0802b5c8 	cmpgei	zero,at,2775
+ 802b360:	0802ba04 	addi	zero,at,2792
+ 802b364:	0802ba04 	addi	zero,at,2792
+ 802b368:	0802ba04 	addi	zero,at,2792
+ 802b36c:	0802ba04 	addi	zero,at,2792
+ 802b370:	0802ba04 	addi	zero,at,2792
+ 802b374:	0802b964 	muli	zero,at,2789
+ 802b378:	0802b964 	muli	zero,at,2789
+   {
+   case PRU_ATTACH:
+      /* fake small windows so sockets asks us to move data */
+      so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = 
+         ip_raw_maxalloc(so->so_options & SO_HDRINCL);
+ 802b37c:	e0bff417 	ldw	r2,-48(fp)
+ 802b380:	10800417 	ldw	r2,16(r2)
+ 802b384:	1088000c 	andi	r2,r2,8192
+ 802b388:	1009883a 	mov	r4,r2
+ 802b38c:	803cae00 	call	803cae0 <ip_raw_maxalloc>
+ 802b390:	1007883a 	mov	r3,r2
+      so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = 
+ 802b394:	e0bff417 	ldw	r2,-48(fp)
+ 802b398:	10c01315 	stw	r3,76(r2)
+ 802b39c:	e0bff417 	ldw	r2,-48(fp)
+ 802b3a0:	10c01317 	ldw	r3,76(r2)
+ 802b3a4:	e0bff417 	ldw	r2,-48(fp)
+ 802b3a8:	10c00b15 	stw	r3,44(r2)
+      /* make a raw IP endpoint */
+      prot = (u_char)(MBUF2LONG(nam));
+ 802b3ac:	e0bff217 	ldw	r2,-56(fp)
+ 802b3b0:	e0bff9c5 	stb	r2,-25(fp)
+      /* unlock the net resource; IP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b3b4:	0009883a 	mov	r4,zero
+ 802b3b8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      ep = ip_raw_open(prot, 0L, 0L, rawip_soinput, so);
+ 802b3bc:	e0fff9c3 	ldbu	r3,-25(fp)
+ 802b3c0:	e0bff417 	ldw	r2,-48(fp)
+ 802b3c4:	d8800015 	stw	r2,0(sp)
+ 802b3c8:	01c200f4 	movhi	r7,2051
+ 802b3cc:	39ec4904 	addi	r7,r7,-20188
+ 802b3d0:	000d883a 	mov	r6,zero
+ 802b3d4:	000b883a 	mov	r5,zero
+ 802b3d8:	1809883a 	mov	r4,r3
+ 802b3dc:	803c63c0 	call	803c63c <ip_raw_open>
+ 802b3e0:	e0bff815 	stw	r2,-32(fp)
+      LOCK_NET_RESOURCE(NET_RESID);
+ 802b3e4:	0009883a 	mov	r4,zero
+ 802b3e8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      if (!ep)
+ 802b3ec:	e0bff817 	ldw	r2,-32(fp)
+ 802b3f0:	1000021e 	bne	r2,zero,802b3fc <rawip_usrreq+0x114>
+         return(EINVAL);
+ 802b3f4:	00800584 	movi	r2,22
+ 802b3f8:	00018306 	br	802ba08 <rawip_usrreq+0x720>
+      return 0;
+ 802b3fc:	0005883a 	mov	r2,zero
+ 802b400:	00018106 	br	802ba08 <rawip_usrreq+0x720>
+   case PRU_DETACH:
+      /* delete the raw IP endpoint */
+      ep = rawip_lookup(so);
+ 802b404:	e13ff417 	ldw	r4,-48(fp)
+ 802b408:	802b0c80 	call	802b0c8 <rawip_lookup>
+ 802b40c:	e0bff815 	stw	r2,-32(fp)
+      if (!ep)
+ 802b410:	e0bff817 	ldw	r2,-32(fp)
+ 802b414:	1000021e 	bne	r2,zero,802b420 <rawip_usrreq+0x138>
+         return(EINVAL);
+ 802b418:	00800584 	movi	r2,22
+ 802b41c:	00017a06 	br	802ba08 <rawip_usrreq+0x720>
+      /* unlock the net resource; IP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b420:	0009883a 	mov	r4,zero
+ 802b424:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      ip_raw_close(ep);
+ 802b428:	e13ff817 	ldw	r4,-32(fp)
+ 802b42c:	803c7140 	call	803c714 <ip_raw_close>
+      LOCK_NET_RESOURCE(NET_RESID);
+ 802b430:	0009883a 	mov	r4,zero
+ 802b434:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      return 0;
+ 802b438:	0005883a 	mov	r2,zero
+ 802b43c:	00017206 	br	802ba08 <rawip_usrreq+0x720>
+       * a default address for sending
+       */
+      /* fall through to shared bind logic */
+   case PRU_BIND:
+      /* do bind parameters lookups and tests */
+      if (nam == NULL)
+ 802b440:	e0bff217 	ldw	r2,-56(fp)
+ 802b444:	1000021e 	bne	r2,zero,802b450 <rawip_usrreq+0x168>
+         return(EINVAL);
+ 802b448:	00800584 	movi	r2,22
+ 802b44c:	00016e06 	br	802ba08 <rawip_usrreq+0x720>
+      sin = mtod(nam, struct sockaddr_in *);
+ 802b450:	e0bff217 	ldw	r2,-56(fp)
+ 802b454:	10800317 	ldw	r2,12(r2)
+ 802b458:	e0bff715 	stw	r2,-36(fp)
+      if (sin == NULL)
+ 802b45c:	e0bff717 	ldw	r2,-36(fp)
+ 802b460:	1000021e 	bne	r2,zero,802b46c <rawip_usrreq+0x184>
+         return(EINVAL);
+ 802b464:	00800584 	movi	r2,22
+ 802b468:	00016706 	br	802ba08 <rawip_usrreq+0x720>
+      if (nam->m_len != sizeof (*sin))
+ 802b46c:	e0bff217 	ldw	r2,-56(fp)
+ 802b470:	10800217 	ldw	r2,8(r2)
+ 802b474:	10800420 	cmpeqi	r2,r2,16
+ 802b478:	1000021e 	bne	r2,zero,802b484 <rawip_usrreq+0x19c>
+         return(EINVAL);
+ 802b47c:	00800584 	movi	r2,22
+ 802b480:	00016106 	br	802ba08 <rawip_usrreq+0x720>
+      ep = rawip_lookup(so);
+ 802b484:	e13ff417 	ldw	r4,-48(fp)
+ 802b488:	802b0c80 	call	802b0c8 <rawip_lookup>
+ 802b48c:	e0bff815 	stw	r2,-32(fp)
+      if (!ep)
+ 802b490:	e0bff817 	ldw	r2,-32(fp)
+ 802b494:	1000021e 	bne	r2,zero,802b4a0 <rawip_usrreq+0x1b8>
+         return(EINVAL);
+ 802b498:	00800584 	movi	r2,22
+ 802b49c:	00015a06 	br	802ba08 <rawip_usrreq+0x720>
+      if (req == PRU_BIND)
+ 802b4a0:	e0bffa17 	ldw	r2,-24(fp)
+ 802b4a4:	10800098 	cmpnei	r2,r2,2
+ 802b4a8:	10001f1e 	bne	r2,zero,802b528 <rawip_usrreq+0x240>
+          * if the caller-supplied address is INADDR_ANY,
+          * don't bind to a specific address; else, 
+          * make sure the caller-supplied address is
+          * an interface IP address and if so, bind to that
+          */
+         if (sin->sin_addr.s_addr == INADDR_ANY)
+ 802b4ac:	e0bff717 	ldw	r2,-36(fp)
+ 802b4b0:	10800117 	ldw	r2,4(r2)
+ 802b4b4:	1000021e 	bne	r2,zero,802b4c0 <rawip_usrreq+0x1d8>
+         {
+            lhost = 0L;
+ 802b4b8:	e03ffc15 	stw	zero,-16(fp)
+ 802b4bc:	00001606 	br	802b518 <rawip_usrreq+0x230>
+         }
+         else
+         {
+            lhost = sin->sin_addr.s_addr;
+ 802b4c0:	e0bff717 	ldw	r2,-36(fp)
+ 802b4c4:	10800117 	ldw	r2,4(r2)
+ 802b4c8:	e0bffc15 	stw	r2,-16(fp)
+            /* verify that lhost is a local interface address */
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b4cc:	008201b4 	movhi	r2,2054
+ 802b4d0:	10b6a617 	ldw	r2,-9576(r2)
+ 802b4d4:	e0bffb15 	stw	r2,-20(fp)
+ 802b4d8:	00000706 	br	802b4f8 <rawip_usrreq+0x210>
+               if (ifp->n_ipaddr == lhost)
+ 802b4dc:	e0bffb17 	ldw	r2,-20(fp)
+ 802b4e0:	10800a17 	ldw	r2,40(r2)
+ 802b4e4:	e0fffc17 	ldw	r3,-16(fp)
+ 802b4e8:	18800626 	beq	r3,r2,802b504 <rawip_usrreq+0x21c>
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b4ec:	e0bffb17 	ldw	r2,-20(fp)
+ 802b4f0:	10800017 	ldw	r2,0(r2)
+ 802b4f4:	e0bffb15 	stw	r2,-20(fp)
+ 802b4f8:	e0bffb17 	ldw	r2,-20(fp)
+ 802b4fc:	103ff71e 	bne	r2,zero,802b4dc <rawip_usrreq+0x1f4>
+ 802b500:	00000106 	br	802b508 <rawip_usrreq+0x220>
+                  break;
+ 802b504:	0001883a 	nop
+            if (ifp == NULL)
+ 802b508:	e0bffb17 	ldw	r2,-20(fp)
+ 802b50c:	1000021e 	bne	r2,zero,802b518 <rawip_usrreq+0x230>
+               return(EADDRNOTAVAIL);
+ 802b510:	00801f44 	movi	r2,125
+ 802b514:	00013c06 	br	802ba08 <rawip_usrreq+0x720>
+         }
+
+         /* bind the endpoint */
+         ep->ipr_laddr = lhost;
+ 802b518:	e0bff817 	ldw	r2,-32(fp)
+ 802b51c:	e0fffc17 	ldw	r3,-16(fp)
+ 802b520:	10c00115 	stw	r3,4(r2)
+ 802b524:	00002606 	br	802b5c0 <rawip_usrreq+0x2d8>
+          *
+          * if the caller-supplied address is INADDR_ANY,
+          * use the wildcard address; else, use the caller-
+          * supplied address
+          */
+         if (sin->sin_addr.s_addr == INADDR_ANY)
+ 802b528:	e0bff717 	ldw	r2,-36(fp)
+ 802b52c:	10800117 	ldw	r2,4(r2)
+ 802b530:	1000021e 	bne	r2,zero,802b53c <rawip_usrreq+0x254>
+            fhost = 0L;
+ 802b534:	e03ffd15 	stw	zero,-12(fp)
+ 802b538:	00000306 	br	802b548 <rawip_usrreq+0x260>
+         else
+            fhost = sin->sin_addr.s_addr;
+ 802b53c:	e0bff717 	ldw	r2,-36(fp)
+ 802b540:	10800117 	ldw	r2,4(r2)
+ 802b544:	e0bffd15 	stw	r2,-12(fp)
+         /* connect the IP endpoint */
+         ep->ipr_faddr = fhost;
+ 802b548:	e0bff817 	ldw	r2,-32(fp)
+ 802b54c:	e0fffd17 	ldw	r3,-12(fp)
+ 802b550:	10c00215 	stw	r3,8(r2)
+         /* mark the socket as connected or disconnected, as appropriate */
+         if (fhost != 0L) {
+ 802b554:	e0bffd17 	ldw	r2,-12(fp)
+ 802b558:	10000e26 	beq	r2,zero,802b594 <rawip_usrreq+0x2ac>
+            so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+ 802b55c:	e0bff417 	ldw	r2,-48(fp)
+ 802b560:	10c0088b 	ldhu	r3,34(r2)
+ 802b564:	00bffcc4 	movi	r2,-13
+ 802b568:	1884703a 	and	r2,r3,r2
+ 802b56c:	1007883a 	mov	r3,r2
+ 802b570:	e0bff417 	ldw	r2,-48(fp)
+ 802b574:	10c0088d 	sth	r3,34(r2)
+            so->so_state |= SS_ISCONNECTED;
+ 802b578:	e0bff417 	ldw	r2,-48(fp)
+ 802b57c:	1080088b 	ldhu	r2,34(r2)
+ 802b580:	10800094 	ori	r2,r2,2
+ 802b584:	1007883a 	mov	r3,r2
+ 802b588:	e0bff417 	ldw	r2,-48(fp)
+ 802b58c:	10c0088d 	sth	r3,34(r2)
+ 802b590:	00000706 	br	802b5b0 <rawip_usrreq+0x2c8>
+         }
+         else
+         {
+            so->so_state &= ~SS_ISCONNECTED;
+ 802b594:	e0bff417 	ldw	r2,-48(fp)
+ 802b598:	10c0088b 	ldhu	r3,34(r2)
+ 802b59c:	00bfff44 	movi	r2,-3
+ 802b5a0:	1884703a 	and	r2,r3,r2
+ 802b5a4:	1007883a 	mov	r3,r2
+ 802b5a8:	e0bff417 	ldw	r2,-48(fp)
+ 802b5ac:	10c0088d 	sth	r3,34(r2)
+         }
+         /* since socket was in listen state, packets may be queued */
+         sbflush(&so->so_rcv);   /* dump these now */
+ 802b5b0:	e0bff417 	ldw	r2,-48(fp)
+ 802b5b4:	10800a04 	addi	r2,r2,40
+ 802b5b8:	1009883a 	mov	r4,r2
+ 802b5bc:	803002c0 	call	803002c <sbflush>
+      }
+      return 0;
+ 802b5c0:	0005883a 	mov	r2,zero
+ 802b5c4:	00011006 	br	802ba08 <rawip_usrreq+0x720>
+   case PRU_SEND:
+      /* do parameter lookups and tests */
+      if (!m)  /* no data passed? */
+ 802b5c8:	e0bff317 	ldw	r2,-52(fp)
+ 802b5cc:	1000021e 	bne	r2,zero,802b5d8 <rawip_usrreq+0x2f0>
+         return(EINVAL);
+ 802b5d0:	00800584 	movi	r2,22
+ 802b5d4:	00010c06 	br	802ba08 <rawip_usrreq+0x720>
+
+      ep = rawip_lookup(so);
+ 802b5d8:	e13ff417 	ldw	r4,-48(fp)
+ 802b5dc:	802b0c80 	call	802b0c8 <rawip_lookup>
+ 802b5e0:	e0bff815 	stw	r2,-32(fp)
+      if (!ep)
+ 802b5e4:	e0bff817 	ldw	r2,-32(fp)
+ 802b5e8:	1000041e 	bne	r2,zero,802b5fc <rawip_usrreq+0x314>
+      {
+         m_free(m);
+ 802b5ec:	e13ff317 	ldw	r4,-52(fp)
+ 802b5f0:	8029bf80 	call	8029bf8 <m_free>
+         /* may be bogus socket, but more likely the connection may 
+         have closed due to ICMP dest unreachable from other side. */
+         return(ECONNREFUSED);
+ 802b5f4:	00801bc4 	movi	r2,111
+ 802b5f8:	00010306 	br	802ba08 <rawip_usrreq+0x720>
+      }
+
+      if (nam == NULL)  /* no sendto() info passed, must be send() */
+ 802b5fc:	e0bff217 	ldw	r2,-56(fp)
+ 802b600:	10000b1e 	bne	r2,zero,802b630 <rawip_usrreq+0x348>
+      {
+         if (!(so->so_state & SS_ISCONNECTED))
+ 802b604:	e0bff417 	ldw	r2,-48(fp)
+ 802b608:	1080088b 	ldhu	r2,34(r2)
+ 802b60c:	10bfffcc 	andi	r2,r2,65535
+ 802b610:	1080008c 	andi	r2,r2,2
+ 802b614:	1000021e 	bne	r2,zero,802b620 <rawip_usrreq+0x338>
+            return (ENOTCONN);
+ 802b618:	00802004 	movi	r2,128
+ 802b61c:	0000fa06 	br	802ba08 <rawip_usrreq+0x720>
+         fhost = ep->ipr_faddr;
+ 802b620:	e0bff817 	ldw	r2,-32(fp)
+ 802b624:	10800217 	ldw	r2,8(r2)
+ 802b628:	e0bffd15 	stw	r2,-12(fp)
+ 802b62c:	00001406 	br	802b680 <rawip_usrreq+0x398>
+      }
+      else 
+      {
+         if (so->so_state & SS_ISCONNECTED)
+ 802b630:	e0bff417 	ldw	r2,-48(fp)
+ 802b634:	1080088b 	ldhu	r2,34(r2)
+ 802b638:	10bfffcc 	andi	r2,r2,65535
+ 802b63c:	1080008c 	andi	r2,r2,2
+ 802b640:	10000226 	beq	r2,zero,802b64c <rawip_usrreq+0x364>
+            return (EISCONN);
+ 802b644:	00801fc4 	movi	r2,127
+ 802b648:	0000ef06 	br	802ba08 <rawip_usrreq+0x720>
+         if (nam->m_len != sizeof (*sin))
+ 802b64c:	e0bff217 	ldw	r2,-56(fp)
+ 802b650:	10800217 	ldw	r2,8(r2)
+ 802b654:	10800420 	cmpeqi	r2,r2,16
+ 802b658:	1000031e 	bne	r2,zero,802b668 <rawip_usrreq+0x380>
+         {
+            dtrap();
+ 802b65c:	8028cd40 	call	8028cd4 <dtrap>
+            return (EINVAL);
+ 802b660:	00800584 	movi	r2,22
+ 802b664:	0000e806 	br	802ba08 <rawip_usrreq+0x720>
+         }
+         sin = mtod(nam, struct sockaddr_in *);
+ 802b668:	e0bff217 	ldw	r2,-56(fp)
+ 802b66c:	10800317 	ldw	r2,12(r2)
+ 802b670:	e0bff715 	stw	r2,-36(fp)
+         fhost = sin->sin_addr.s_addr;
+ 802b674:	e0bff717 	ldw	r2,-36(fp)
+ 802b678:	10800117 	ldw	r2,4(r2)
+ 802b67c:	e0bffd15 	stw	r2,-12(fp)
+
+      /* since our pkt->nb_buff size is tied to max packet size, we 
+       * assume our raw IP datagrams are always in one mbuf and that the 
+       * mbuf -- but check anyway
+       */
+      if (m->m_len > (unsigned)ip_raw_maxalloc(so->so_options & SO_HDRINCL))
+ 802b680:	e0bff317 	ldw	r2,-52(fp)
+ 802b684:	14000217 	ldw	r16,8(r2)
+ 802b688:	e0bff417 	ldw	r2,-48(fp)
+ 802b68c:	10800417 	ldw	r2,16(r2)
+ 802b690:	1088000c 	andi	r2,r2,8192
+ 802b694:	1009883a 	mov	r4,r2
+ 802b698:	803cae00 	call	803cae0 <ip_raw_maxalloc>
+ 802b69c:	1400032e 	bgeu	r2,r16,802b6ac <rawip_usrreq+0x3c4>
+      {
+         dtrap(); /* should never happen */
+ 802b6a0:	8028cd40 	call	8028cd4 <dtrap>
+         return EMSGSIZE;  /* try to recover */
+ 802b6a4:	00801e84 	movi	r2,122
+ 802b6a8:	0000d706 	br	802ba08 <rawip_usrreq+0x720>
+      }
+      /* get a packet buffer for send */
+      pkt = ip_raw_alloc(m->m_len, so->so_options & SO_HDRINCL);
+ 802b6ac:	e0bff317 	ldw	r2,-52(fp)
+ 802b6b0:	10800217 	ldw	r2,8(r2)
+ 802b6b4:	1007883a 	mov	r3,r2
+ 802b6b8:	e0bff417 	ldw	r2,-48(fp)
+ 802b6bc:	10800417 	ldw	r2,16(r2)
+ 802b6c0:	1088000c 	andi	r2,r2,8192
+ 802b6c4:	100b883a 	mov	r5,r2
+ 802b6c8:	1809883a 	mov	r4,r3
+ 802b6cc:	803c9e40 	call	803c9e4 <ip_raw_alloc>
+ 802b6d0:	e0bff615 	stw	r2,-40(fp)
+      if (!pkt)
+ 802b6d4:	e0bff617 	ldw	r2,-40(fp)
+ 802b6d8:	1000041e 	bne	r2,zero,802b6ec <rawip_usrreq+0x404>
+      {
+         m_free(m);
+ 802b6dc:	e13ff317 	ldw	r4,-52(fp)
+ 802b6e0:	8029bf80 	call	8029bf8 <m_free>
+         return ENOBUFS;   /* report buffer shortages */
+ 802b6e4:	00801a44 	movi	r2,105
+ 802b6e8:	0000c706 	br	802ba08 <rawip_usrreq+0x720>
+      }
+      MEMCPY(pkt->nb_prot, m->m_data, m->m_len);
+ 802b6ec:	e0bff617 	ldw	r2,-40(fp)
+ 802b6f0:	10c00317 	ldw	r3,12(r2)
+ 802b6f4:	e0bff317 	ldw	r2,-52(fp)
+ 802b6f8:	11000317 	ldw	r4,12(r2)
+ 802b6fc:	e0bff317 	ldw	r2,-52(fp)
+ 802b700:	10800217 	ldw	r2,8(r2)
+ 802b704:	100d883a 	mov	r6,r2
+ 802b708:	200b883a 	mov	r5,r4
+ 802b70c:	1809883a 	mov	r4,r3
+ 802b710:	80086b80 	call	80086b8 <memcpy>
+      pkt->nb_plen = m->m_len;
+ 802b714:	e0bff317 	ldw	r2,-52(fp)
+ 802b718:	10c00217 	ldw	r3,8(r2)
+ 802b71c:	e0bff617 	ldw	r2,-40(fp)
+ 802b720:	10c00415 	stw	r3,16(r2)
+      /* finished with mbuf, free it now */
+      m_free(m);
+ 802b724:	e13ff317 	ldw	r4,-52(fp)
+ 802b728:	8029bf80 	call	8029bf8 <m_free>
+      pkt->fhost = fhost;
+ 802b72c:	e0bff617 	ldw	r2,-40(fp)
+ 802b730:	e0fffd17 	ldw	r3,-12(fp)
+ 802b734:	10c00715 	stw	r3,28(r2)
+       * is up; if (after all that) we don't have an interface then we
+       * fail with error EADDRNOTAVAIL; and finally, if we're built
+       * for a single-homed configuration where there's only one
+       * interface, we might as well use it, so we do.  
+       */
+      if (fhost == 0xffffffff)
+ 802b738:	e0bffd17 	ldw	r2,-12(fp)
+ 802b73c:	10bfffd8 	cmpnei	r2,r2,-1
+ 802b740:	1000471e 	bne	r2,zero,802b860 <rawip_usrreq+0x578>
+      {
+#ifdef MULTI_HOMED
+         if (ep->ipr_laddr != 0L)
+ 802b744:	e0bff817 	ldw	r2,-32(fp)
+ 802b748:	10800117 	ldw	r2,4(r2)
+ 802b74c:	10000f26 	beq	r2,zero,802b78c <rawip_usrreq+0x4a4>
+         {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b750:	008201b4 	movhi	r2,2054
+ 802b754:	10b6a617 	ldw	r2,-9576(r2)
+ 802b758:	e0bffb15 	stw	r2,-20(fp)
+ 802b75c:	00000806 	br	802b780 <rawip_usrreq+0x498>
+               if (ifp->n_ipaddr == ep->ipr_laddr)
+ 802b760:	e0bffb17 	ldw	r2,-20(fp)
+ 802b764:	10c00a17 	ldw	r3,40(r2)
+ 802b768:	e0bff817 	ldw	r2,-32(fp)
+ 802b76c:	10800117 	ldw	r2,4(r2)
+ 802b770:	18801c26 	beq	r3,r2,802b7e4 <rawip_usrreq+0x4fc>
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b774:	e0bffb17 	ldw	r2,-20(fp)
+ 802b778:	10800017 	ldw	r2,0(r2)
+ 802b77c:	e0bffb15 	stw	r2,-20(fp)
+ 802b780:	e0bffb17 	ldw	r2,-20(fp)
+ 802b784:	103ff61e 	bne	r2,zero,802b760 <rawip_usrreq+0x478>
+ 802b788:	00001906 	br	802b7f0 <rawip_usrreq+0x508>
+                  break;
+         }
+         else {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b78c:	008201b4 	movhi	r2,2054
+ 802b790:	10b6a617 	ldw	r2,-9576(r2)
+ 802b794:	e0bffb15 	stw	r2,-20(fp)
+ 802b798:	00000f06 	br	802b7d8 <rawip_usrreq+0x4f0>
+               if ((ifp->n_flags & NF_BCAST) &&
+ 802b79c:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7a0:	10802a17 	ldw	r2,168(r2)
+ 802b7a4:	1080004c 	andi	r2,r2,1
+ 802b7a8:	10000826 	beq	r2,zero,802b7cc <rawip_usrreq+0x4e4>
+                   (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 802b7ac:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7b0:	10802717 	ldw	r2,156(r2)
+               if ((ifp->n_flags & NF_BCAST) &&
+ 802b7b4:	10000526 	beq	r2,zero,802b7cc <rawip_usrreq+0x4e4>
+                   (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 802b7b8:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7bc:	10802717 	ldw	r2,156(r2)
+ 802b7c0:	10800617 	ldw	r2,24(r2)
+ 802b7c4:	10800058 	cmpnei	r2,r2,1
+ 802b7c8:	10000826 	beq	r2,zero,802b7ec <rawip_usrreq+0x504>
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b7cc:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7d0:	10800017 	ldw	r2,0(r2)
+ 802b7d4:	e0bffb15 	stw	r2,-20(fp)
+ 802b7d8:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7dc:	103fef1e 	bne	r2,zero,802b79c <rawip_usrreq+0x4b4>
+ 802b7e0:	00000306 	br	802b7f0 <rawip_usrreq+0x508>
+                  break;
+ 802b7e4:	0001883a 	nop
+ 802b7e8:	00000106 	br	802b7f0 <rawip_usrreq+0x508>
+                  break;
+ 802b7ec:	0001883a 	nop
+         }
+         if (ifp == NULL)
+ 802b7f0:	e0bffb17 	ldw	r2,-20(fp)
+ 802b7f4:	1000171e 	bne	r2,zero,802b854 <rawip_usrreq+0x56c>
+         {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b7f8:	008201b4 	movhi	r2,2054
+ 802b7fc:	10b6a617 	ldw	r2,-9576(r2)
+ 802b800:	e0bffb15 	stw	r2,-20(fp)
+ 802b804:	00000b06 	br	802b834 <rawip_usrreq+0x54c>
+               if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 802b808:	e0bffb17 	ldw	r2,-20(fp)
+ 802b80c:	10802717 	ldw	r2,156(r2)
+ 802b810:	10000526 	beq	r2,zero,802b828 <rawip_usrreq+0x540>
+ 802b814:	e0bffb17 	ldw	r2,-20(fp)
+ 802b818:	10802717 	ldw	r2,156(r2)
+ 802b81c:	10800617 	ldw	r2,24(r2)
+ 802b820:	10800058 	cmpnei	r2,r2,1
+ 802b824:	10000626 	beq	r2,zero,802b840 <rawip_usrreq+0x558>
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 802b828:	e0bffb17 	ldw	r2,-20(fp)
+ 802b82c:	10800017 	ldw	r2,0(r2)
+ 802b830:	e0bffb15 	stw	r2,-20(fp)
+ 802b834:	e0bffb17 	ldw	r2,-20(fp)
+ 802b838:	103ff31e 	bne	r2,zero,802b808 <rawip_usrreq+0x520>
+ 802b83c:	00000106 	br	802b844 <rawip_usrreq+0x55c>
+                  break;
+ 802b840:	0001883a 	nop
+            if (ifp == NULL)
+ 802b844:	e0bffb17 	ldw	r2,-20(fp)
+ 802b848:	1000021e 	bne	r2,zero,802b854 <rawip_usrreq+0x56c>
+               return(EADDRNOTAVAIL);
+ 802b84c:	00801f44 	movi	r2,125
+ 802b850:	00006d06 	br	802ba08 <rawip_usrreq+0x720>
+         }
+         pkt->net = ifp;
+ 802b854:	e0bff617 	ldw	r2,-40(fp)
+ 802b858:	e0fffb17 	ldw	r3,-20(fp)
+ 802b85c:	10c00615 	stw	r3,24(r2)
+#ifdef IP_MULTICAST
+
+      /* If the socket has an IP moptions structure for multicast options,
+       * place a pointer to this structure in the PACKET structure.
+       */
+      if (so->inp_moptions)
+ 802b860:	e0bff417 	ldw	r2,-48(fp)
+ 802b864:	10800317 	ldw	r2,12(r2)
+ 802b868:	10000426 	beq	r2,zero,802b87c <rawip_usrreq+0x594>
+         pkt->imo = so->inp_moptions;
+ 802b86c:	e0bff417 	ldw	r2,-48(fp)
+ 802b870:	10c00317 	ldw	r3,12(r2)
+ 802b874:	e0bff617 	ldw	r2,-40(fp)
+ 802b878:	10c00b15 	stw	r3,44(r2)
+
+#endif   /* IP_MULTICAST */
+
+      if (so->so_options & SO_HDRINCL)
+ 802b87c:	e0bff417 	ldw	r2,-48(fp)
+ 802b880:	10800417 	ldw	r2,16(r2)
+ 802b884:	1088000c 	andi	r2,r2,8192
+ 802b888:	10000826 	beq	r2,zero,802b8ac <rawip_usrreq+0x5c4>
+      {
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b88c:	0009883a 	mov	r4,zero
+ 802b890:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         e = ip_raw_write(pkt);
+ 802b894:	e13ff617 	ldw	r4,-40(fp)
+ 802b898:	803af6c0 	call	803af6c <ip_raw_write>
+ 802b89c:	e0bffe15 	stw	r2,-8(fp)
+         LOCK_NET_RESOURCE(NET_RESID);
+ 802b8a0:	0009883a 	mov	r4,zero
+ 802b8a4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+ 802b8a8:	00002806 	br	802b94c <rawip_usrreq+0x664>
+      }
+      else
+      {
+         pip = (struct ip *)(pkt->nb_prot - IPHSIZ);
+ 802b8ac:	e0bff617 	ldw	r2,-40(fp)
+ 802b8b0:	10800317 	ldw	r2,12(r2)
+ 802b8b4:	10bffb04 	addi	r2,r2,-20
+ 802b8b8:	e0bff515 	stw	r2,-44(fp)
+         if (ep->ipr_laddr)
+ 802b8bc:	e0bff817 	ldw	r2,-32(fp)
+ 802b8c0:	10800117 	ldw	r2,4(r2)
+ 802b8c4:	10000526 	beq	r2,zero,802b8dc <rawip_usrreq+0x5f4>
+            pip->ip_src = ep->ipr_laddr;
+ 802b8c8:	e0bff817 	ldw	r2,-32(fp)
+ 802b8cc:	10c00117 	ldw	r3,4(r2)
+ 802b8d0:	e0bff517 	ldw	r2,-44(fp)
+ 802b8d4:	10c00315 	stw	r3,12(r2)
+ 802b8d8:	00000e06 	br	802b914 <rawip_usrreq+0x62c>
+         else
+         {
+            if (fhost == 0xffffffff)
+ 802b8dc:	e0bffd17 	ldw	r2,-12(fp)
+ 802b8e0:	10bfffd8 	cmpnei	r2,r2,-1
+ 802b8e4:	1000061e 	bne	r2,zero,802b900 <rawip_usrreq+0x618>
+               pip->ip_src = pkt->net->n_ipaddr;
+ 802b8e8:	e0bff617 	ldw	r2,-40(fp)
+ 802b8ec:	10800617 	ldw	r2,24(r2)
+ 802b8f0:	10c00a17 	ldw	r3,40(r2)
+ 802b8f4:	e0bff517 	ldw	r2,-44(fp)
+ 802b8f8:	10c00315 	stw	r3,12(r2)
+ 802b8fc:	00000506 	br	802b914 <rawip_usrreq+0x62c>
+            else
+               pip->ip_src = ip_mymach(fhost);
+ 802b900:	e13ffd17 	ldw	r4,-12(fp)
+ 802b904:	803b0280 	call	803b028 <ip_mymach>
+ 802b908:	1007883a 	mov	r3,r2
+ 802b90c:	e0bff517 	ldw	r2,-44(fp)
+ 802b910:	10c00315 	stw	r3,12(r2)
+         }
+         pip->ip_dest = fhost;
+ 802b914:	e0bff517 	ldw	r2,-44(fp)
+ 802b918:	e0fffd17 	ldw	r3,-12(fp)
+ 802b91c:	10c00415 	stw	r3,16(r2)
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 802b920:	0009883a 	mov	r4,zero
+ 802b924:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         e = ip_write(ep->ipr_prot, pkt);
+ 802b928:	e0bff817 	ldw	r2,-32(fp)
+ 802b92c:	10800503 	ldbu	r2,20(r2)
+ 802b930:	10803fcc 	andi	r2,r2,255
+ 802b934:	e17ff617 	ldw	r5,-40(fp)
+ 802b938:	1009883a 	mov	r4,r2
+ 802b93c:	803a9e80 	call	803a9e8 <ip_write>
+ 802b940:	e0bffe15 	stw	r2,-8(fp)
+         LOCK_NET_RESOURCE(NET_RESID);
+ 802b944:	0009883a 	mov	r4,zero
+ 802b948:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      }         
+      if (e < 0) 
+ 802b94c:	e0bffe17 	ldw	r2,-8(fp)
+ 802b950:	1000020e 	bge	r2,zero,802b95c <rawip_usrreq+0x674>
+         return(e);
+ 802b954:	e0bffe17 	ldw	r2,-8(fp)
+ 802b958:	00002b06 	br	802ba08 <rawip_usrreq+0x720>
+      return 0;
+ 802b95c:	0005883a 	mov	r2,zero
+ 802b960:	00002906 	br	802ba08 <rawip_usrreq+0x720>
+   case PRU_SOCKADDR:
+      /* fall through to share PRU_PEERADDR prefix */
+   case PRU_PEERADDR:
+      if (nam == NULL)
+ 802b964:	e0bff217 	ldw	r2,-56(fp)
+ 802b968:	1000021e 	bne	r2,zero,802b974 <rawip_usrreq+0x68c>
+         return(EINVAL);
+ 802b96c:	00800584 	movi	r2,22
+ 802b970:	00002506 	br	802ba08 <rawip_usrreq+0x720>
+      sin = mtod(nam, struct sockaddr_in *);
+ 802b974:	e0bff217 	ldw	r2,-56(fp)
+ 802b978:	10800317 	ldw	r2,12(r2)
+ 802b97c:	e0bff715 	stw	r2,-36(fp)
+      if (sin == NULL)
+ 802b980:	e0bff717 	ldw	r2,-36(fp)
+ 802b984:	1000021e 	bne	r2,zero,802b990 <rawip_usrreq+0x6a8>
+         return(EINVAL);
+ 802b988:	00800584 	movi	r2,22
+ 802b98c:	00001e06 	br	802ba08 <rawip_usrreq+0x720>
+      ep = rawip_lookup(so);
+ 802b990:	e13ff417 	ldw	r4,-48(fp)
+ 802b994:	802b0c80 	call	802b0c8 <rawip_lookup>
+ 802b998:	e0bff815 	stw	r2,-32(fp)
+      if (!ep)
+ 802b99c:	e0bff817 	ldw	r2,-32(fp)
+ 802b9a0:	1000021e 	bne	r2,zero,802b9ac <rawip_usrreq+0x6c4>
+         return(EINVAL);
+ 802b9a4:	00800584 	movi	r2,22
+ 802b9a8:	00001706 	br	802ba08 <rawip_usrreq+0x720>
+      sin->sin_port = 0;
+ 802b9ac:	e0bff717 	ldw	r2,-36(fp)
+ 802b9b0:	1000008d 	sth	zero,2(r2)
+      nam->m_len = sizeof(*sin);
+ 802b9b4:	e0bff217 	ldw	r2,-56(fp)
+ 802b9b8:	00c00404 	movi	r3,16
+ 802b9bc:	10c00215 	stw	r3,8(r2)
+      if (req == PRU_SOCKADDR)
+ 802b9c0:	e0bffa17 	ldw	r2,-24(fp)
+ 802b9c4:	108003d8 	cmpnei	r2,r2,15
+ 802b9c8:	1000051e 	bne	r2,zero,802b9e0 <rawip_usrreq+0x6f8>
+      {
+         sin->sin_addr.s_addr = ep->ipr_laddr;
+ 802b9cc:	e0bff817 	ldw	r2,-32(fp)
+ 802b9d0:	10c00117 	ldw	r3,4(r2)
+ 802b9d4:	e0bff717 	ldw	r2,-36(fp)
+ 802b9d8:	10c00115 	stw	r3,4(r2)
+ 802b9dc:	00000406 	br	802b9f0 <rawip_usrreq+0x708>
+      }
+      else /* PRU_PEERADDR */
+      {
+         sin->sin_addr.s_addr = ep->ipr_faddr;
+ 802b9e0:	e0bff817 	ldw	r2,-32(fp)
+ 802b9e4:	10c00217 	ldw	r3,8(r2)
+ 802b9e8:	e0bff717 	ldw	r2,-36(fp)
+ 802b9ec:	10c00115 	stw	r3,4(r2)
+      }
+      return 0;
+ 802b9f0:	0005883a 	mov	r2,zero
+ 802b9f4:	00000406 	br	802ba08 <rawip_usrreq+0x720>
+   case PRU_DISCONNECT:
+   case PRU_RCVD:
+      dtrap();
+ 802b9f8:	8028cd40 	call	8028cd4 <dtrap>
+      return 0;
+ 802b9fc:	0005883a 	mov	r2,zero
+ 802ba00:	00000106 	br	802ba08 <rawip_usrreq+0x720>
+   case PRU_LISTEN:     /* don't support these for raw IP */
+   case PRU_ACCEPT:
+   default:
+      return EOPNOTSUPP;
+ 802ba04:	008017c4 	movi	r2,95
+   }
+}
+ 802ba08:	e6ffff04 	addi	sp,fp,-4
+ 802ba0c:	dfc00217 	ldw	ra,8(sp)
+ 802ba10:	df000117 	ldw	fp,4(sp)
+ 802ba14:	dc000017 	ldw	r16,0(sp)
+ 802ba18:	dec00304 	addi	sp,sp,12
+ 802ba1c:	f800283a 	ret
+
+0802ba20 <DOMAIN_CHECK>:
+ */
+
+#ifdef NPDEBUG
+void
+DOMAIN_CHECK(struct socket * so, int size)
+{
+ 802ba20:	defffc04 	addi	sp,sp,-16
+ 802ba24:	dfc00315 	stw	ra,12(sp)
+ 802ba28:	df000215 	stw	fp,8(sp)
+ 802ba2c:	df000204 	addi	fp,sp,8
+ 802ba30:	e13fff15 	stw	r4,-4(fp)
+ 802ba34:	e17ffe15 	stw	r5,-8(fp)
+#ifdef IP_V4
+   if((so->so_domain == AF_INET) &&
+ 802ba38:	e0bfff17 	ldw	r2,-4(fp)
+ 802ba3c:	10800517 	ldw	r2,20(r2)
+ 802ba40:	10800098 	cmpnei	r2,r2,2
+ 802ba44:	1000041e 	bne	r2,zero,802ba58 <DOMAIN_CHECK+0x38>
+      (size < sizeof(struct sockaddr_in)))
+ 802ba48:	e0bffe17 	ldw	r2,-8(fp)
+   if((so->so_domain == AF_INET) &&
+ 802ba4c:	10800428 	cmpgeui	r2,r2,16
+ 802ba50:	1000011e 	bne	r2,zero,802ba58 <DOMAIN_CHECK+0x38>
+   {
+      dtrap(); /* programmer passed wrong structure */
+ 802ba54:	8028cd40 	call	8028cd4 <dtrap>
+      (size != sizeof(struct sockaddr_in6)))
+   {
+      dtrap(); /* programmer passed wrong structure */
+   }
+#endif   /* IP_V6 */
+}
+ 802ba58:	0001883a 	nop
+ 802ba5c:	e037883a 	mov	sp,fp
+ 802ba60:	dfc00117 	ldw	ra,4(sp)
+ 802ba64:	df000017 	ldw	fp,0(sp)
+ 802ba68:	dec00204 	addi	sp,sp,8
+ 802ba6c:	f800283a 	ret
+
+0802ba70 <t_socket>:
+
+long
+t_socket(int family, 
+   int   type, 
+   int   proto)
+{
+ 802ba70:	defffa04 	addi	sp,sp,-24
+ 802ba74:	dfc00515 	stw	ra,20(sp)
+ 802ba78:	df000415 	stw	fp,16(sp)
+ 802ba7c:	df000404 	addi	fp,sp,16
+ 802ba80:	e13ffe15 	stw	r4,-8(fp)
+ 802ba84:	e17ffd15 	stw	r5,-12(fp)
+ 802ba88:	e1bffc15 	stw	r6,-16(fp)
+   struct socket *   so;
+
+   INET_TRACE (INETM_SOCKET, ("SOCK:sock:family %d, typ %d, proto %d\n",
+    family, type, proto));
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802ba8c:	0009883a 	mov	r4,zero
+ 802ba90:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   if ((so = socreate (family, type, proto)) == NULL) 
+ 802ba94:	e1bffc17 	ldw	r6,-16(fp)
+ 802ba98:	e17ffd17 	ldw	r5,-12(fp)
+ 802ba9c:	e13ffe17 	ldw	r4,-8(fp)
+ 802baa0:	802d0500 	call	802d050 <socreate>
+ 802baa4:	e0bfff15 	stw	r2,-4(fp)
+ 802baa8:	e0bfff17 	ldw	r2,-4(fp)
+ 802baac:	1000041e 	bne	r2,zero,802bac0 <t_socket+0x50>
+   {  /* can't really return error info since no socket.... */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bab0:	0009883a 	mov	r4,zero
+ 802bab4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return SOCKET_ERROR;
+ 802bab8:	00bfffc4 	movi	r2,-1
+ 802babc:	00000706 	br	802badc <t_socket+0x6c>
+   }
+   SOC_RANGE(so);
+   so->so_error = 0;
+ 802bac0:	e0bfff17 	ldw	r2,-4(fp)
+ 802bac4:	10000615 	stw	zero,24(r2)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bac8:	0009883a 	mov	r4,zero
+ 802bacc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return SO2LONG(so);
+ 802bad0:	e0bfff17 	ldw	r2,-4(fp)
+ 802bad4:	1004d0ba 	srli	r2,r2,2
+ 802bad8:	10800404 	addi	r2,r2,16
+}
+ 802badc:	e037883a 	mov	sp,fp
+ 802bae0:	dfc00117 	ldw	ra,4(sp)
+ 802bae4:	df000017 	ldw	fp,0(sp)
+ 802bae8:	dec00204 	addi	sp,sp,8
+ 802baec:	f800283a 	ret
+
+0802baf0 <t_bind>:
+
+int
+t_bind (long s, 
+   struct sockaddr * addr,
+   int addrlen)
+{
+ 802baf0:	defff204 	addi	sp,sp,-56
+ 802baf4:	dfc00d15 	stw	ra,52(sp)
+ 802baf8:	df000c15 	stw	fp,48(sp)
+ 802bafc:	df000c04 	addi	fp,sp,48
+ 802bb00:	e13ff615 	stw	r4,-40(fp)
+ 802bb04:	e17ff515 	stw	r5,-44(fp)
+ 802bb08:	e1bff415 	stw	r6,-48(fp)
+   struct sockaddr   sa;
+   struct sockaddr * sap;
+   struct socket *   so;
+   int               err;
+
+   so = LONG2SO(s);  /* convert long to socket */
+ 802bb0c:	e0bff617 	ldw	r2,-40(fp)
+ 802bb10:	10bffc04 	addi	r2,r2,-16
+ 802bb14:	100490ba 	slli	r2,r2,2
+ 802bb18:	e0bffd15 	stw	r2,-12(fp)
+   SOC_CHECK(so);
+ 802bb1c:	008201b4 	movhi	r2,2054
+ 802bb20:	10b87104 	addi	r2,r2,-7740
+ 802bb24:	e0bffe15 	stw	r2,-8(fp)
+ 802bb28:	00000606 	br	802bb44 <t_bind+0x54>
+ 802bb2c:	e0fffe17 	ldw	r3,-8(fp)
+ 802bb30:	e0bffd17 	ldw	r2,-12(fp)
+ 802bb34:	18800626 	beq	r3,r2,802bb50 <t_bind+0x60>
+ 802bb38:	e0bffe17 	ldw	r2,-8(fp)
+ 802bb3c:	10800017 	ldw	r2,0(r2)
+ 802bb40:	e0bffe15 	stw	r2,-8(fp)
+ 802bb44:	e0bffe17 	ldw	r2,-8(fp)
+ 802bb48:	103ff81e 	bne	r2,zero,802bb2c <t_bind+0x3c>
+ 802bb4c:	00000106 	br	802bb54 <t_bind+0x64>
+ 802bb50:	0001883a 	nop
+ 802bb54:	e0fffe17 	ldw	r3,-8(fp)
+ 802bb58:	e0bffd17 	ldw	r2,-12(fp)
+ 802bb5c:	18800326 	beq	r3,r2,802bb6c <t_bind+0x7c>
+ 802bb60:	8028cd40 	call	8028cd4 <dtrap>
+ 802bb64:	00bfffc4 	movi	r2,-1
+ 802bb68:	00003406 	br	802bc3c <t_bind+0x14c>
+   DOMAIN_CHECK(so, addrlen);
+ 802bb6c:	e17ff417 	ldw	r5,-48(fp)
+ 802bb70:	e13ffd17 	ldw	r4,-12(fp)
+ 802bb74:	802ba200 	call	802ba20 <DOMAIN_CHECK>
+
+   so->so_error = 0;
+ 802bb78:	e0bffd17 	ldw	r2,-12(fp)
+ 802bb7c:	10000615 	stw	zero,24(r2)
+   if (addr == (struct sockaddr *)NULL) 
+ 802bb80:	e0bff517 	ldw	r2,-44(fp)
+ 802bb84:	10000d1e 	bne	r2,zero,802bbbc <t_bind+0xcc>
+   {
+      MEMSET ((void *)&sa, 0, sizeof(sa));
+ 802bb88:	e0bff704 	addi	r2,fp,-36
+ 802bb8c:	01800404 	movi	r6,16
+ 802bb90:	000b883a 	mov	r5,zero
+ 802bb94:	1009883a 	mov	r4,r2
+ 802bb98:	80088e40 	call	80088e4 <memset>
+      addrlen = sizeof(sa);
+ 802bb9c:	00800404 	movi	r2,16
+ 802bba0:	e0bff415 	stw	r2,-48(fp)
+      sa.sa_family = so->so_domain;
+ 802bba4:	e0bffd17 	ldw	r2,-12(fp)
+ 802bba8:	10800517 	ldw	r2,20(r2)
+ 802bbac:	e0bff70d 	sth	r2,-36(fp)
+      sap = &sa;
+ 802bbb0:	e0bff704 	addi	r2,fp,-36
+ 802bbb4:	e0bfff15 	stw	r2,-4(fp)
+ 802bbb8:	00000206 	br	802bbc4 <t_bind+0xd4>
+   } else
+      sap = addr;
+ 802bbbc:	e0bff517 	ldw	r2,-44(fp)
+ 802bbc0:	e0bfff15 	stw	r2,-4(fp)
+
+   if ((nam = sockargs (sap, addrlen, MT_SONAME)) == NULL) 
+ 802bbc4:	01800244 	movi	r6,9
+ 802bbc8:	e17ff417 	ldw	r5,-48(fp)
+ 802bbcc:	e13fff17 	ldw	r4,-4(fp)
+ 802bbd0:	802cf300 	call	802cf30 <sockargs>
+ 802bbd4:	e0bffc15 	stw	r2,-16(fp)
+ 802bbd8:	e0bffc17 	ldw	r2,-16(fp)
+ 802bbdc:	1000051e 	bne	r2,zero,802bbf4 <t_bind+0x104>
+   {
+      so->so_error = ENOMEM;
+ 802bbe0:	e0bffd17 	ldw	r2,-12(fp)
+ 802bbe4:	00c00304 	movi	r3,12
+ 802bbe8:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802bbec:	00bfffc4 	movi	r2,-1
+ 802bbf0:	00001206 	br	802bc3c <t_bind+0x14c>
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802bbf4:	0009883a 	mov	r4,zero
+ 802bbf8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   err = sobind (so, nam);
+ 802bbfc:	e17ffc17 	ldw	r5,-16(fp)
+ 802bc00:	e13ffd17 	ldw	r4,-12(fp)
+ 802bc04:	802d1f80 	call	802d1f8 <sobind>
+ 802bc08:	e0bffb15 	stw	r2,-20(fp)
+   m_freem(nam);
+ 802bc0c:	e13ffc17 	ldw	r4,-16(fp)
+ 802bc10:	8029cfc0 	call	8029cfc <m_freem>
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bc14:	0009883a 	mov	r4,zero
+ 802bc18:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (err) 
+ 802bc1c:	e0bffb17 	ldw	r2,-20(fp)
+ 802bc20:	10000526 	beq	r2,zero,802bc38 <t_bind+0x148>
+   {
+      so->so_error = err;
+ 802bc24:	e0bffd17 	ldw	r2,-12(fp)
+ 802bc28:	e0fffb17 	ldw	r3,-20(fp)
+ 802bc2c:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802bc30:	00bfffc4 	movi	r2,-1
+ 802bc34:	00000106 	br	802bc3c <t_bind+0x14c>
+   }
+   return 0;
+ 802bc38:	0005883a 	mov	r2,zero
+}
+ 802bc3c:	e037883a 	mov	sp,fp
+ 802bc40:	dfc00117 	ldw	ra,4(sp)
+ 802bc44:	df000017 	ldw	fp,0(sp)
+ 802bc48:	dec00204 	addi	sp,sp,8
+ 802bc4c:	f800283a 	ret
+
+0802bc50 <t_listen>:
+ */
+
+int
+t_listen(long s, 
+   int   backlog)
+{
+ 802bc50:	defff904 	addi	sp,sp,-28
+ 802bc54:	dfc00615 	stw	ra,24(sp)
+ 802bc58:	df000515 	stw	fp,20(sp)
+ 802bc5c:	df000504 	addi	fp,sp,20
+ 802bc60:	e13ffc15 	stw	r4,-16(fp)
+ 802bc64:	e17ffb15 	stw	r5,-20(fp)
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);  /* convert long to socket */
+ 802bc68:	e0bffc17 	ldw	r2,-16(fp)
+ 802bc6c:	10bffc04 	addi	r2,r2,-16
+ 802bc70:	100490ba 	slli	r2,r2,2
+ 802bc74:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802bc78:	008201b4 	movhi	r2,2054
+ 802bc7c:	10b87104 	addi	r2,r2,-7740
+ 802bc80:	e0bfff15 	stw	r2,-4(fp)
+ 802bc84:	00000606 	br	802bca0 <t_listen+0x50>
+ 802bc88:	e0ffff17 	ldw	r3,-4(fp)
+ 802bc8c:	e0bffe17 	ldw	r2,-8(fp)
+ 802bc90:	18800626 	beq	r3,r2,802bcac <t_listen+0x5c>
+ 802bc94:	e0bfff17 	ldw	r2,-4(fp)
+ 802bc98:	10800017 	ldw	r2,0(r2)
+ 802bc9c:	e0bfff15 	stw	r2,-4(fp)
+ 802bca0:	e0bfff17 	ldw	r2,-4(fp)
+ 802bca4:	103ff81e 	bne	r2,zero,802bc88 <t_listen+0x38>
+ 802bca8:	00000106 	br	802bcb0 <t_listen+0x60>
+ 802bcac:	0001883a 	nop
+ 802bcb0:	e0ffff17 	ldw	r3,-4(fp)
+ 802bcb4:	e0bffe17 	ldw	r2,-8(fp)
+ 802bcb8:	18800326 	beq	r3,r2,802bcc8 <t_listen+0x78>
+ 802bcbc:	8028cd40 	call	8028cd4 <dtrap>
+ 802bcc0:	00bfffc4 	movi	r2,-1
+ 802bcc4:	00001206 	br	802bd10 <t_listen+0xc0>
+   so->so_error = 0;
+ 802bcc8:	e0bffe17 	ldw	r2,-8(fp)
+ 802bccc:	10000615 	stw	zero,24(r2)
+   INET_TRACE (INETM_SOCKET, ("SOCK:listen:qlen %d\n", backlog));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802bcd0:	0009883a 	mov	r4,zero
+ 802bcd4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   err = solisten (so, backlog);
+ 802bcd8:	e17ffb17 	ldw	r5,-20(fp)
+ 802bcdc:	e13ffe17 	ldw	r4,-8(fp)
+ 802bce0:	802d2540 	call	802d254 <solisten>
+ 802bce4:	e0bffd15 	stw	r2,-12(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bce8:	0009883a 	mov	r4,zero
+ 802bcec:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (err != 0) 
+ 802bcf0:	e0bffd17 	ldw	r2,-12(fp)
+ 802bcf4:	10000526 	beq	r2,zero,802bd0c <t_listen+0xbc>
+   {
+      so->so_error = err;
+ 802bcf8:	e0bffe17 	ldw	r2,-8(fp)
+ 802bcfc:	e0fffd17 	ldw	r3,-12(fp)
+ 802bd00:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802bd04:	00bfffc4 	movi	r2,-1
+ 802bd08:	00000106 	br	802bd10 <t_listen+0xc0>
+   }
+   return 0;
+ 802bd0c:	0005883a 	mov	r2,zero
+}
+ 802bd10:	e037883a 	mov	sp,fp
+ 802bd14:	dfc00117 	ldw	ra,4(sp)
+ 802bd18:	df000017 	ldw	fp,0(sp)
+ 802bd1c:	dec00204 	addi	sp,sp,8
+ 802bd20:	f800283a 	ret
+
+0802bd24 <t_accept>:
+
+long
+t_accept(long s, 
+   struct sockaddr * addr,
+   int * addrlen)
+{
+ 802bd24:	defff704 	addi	sp,sp,-36
+ 802bd28:	dfc00815 	stw	ra,32(sp)
+ 802bd2c:	df000715 	stw	fp,28(sp)
+ 802bd30:	df000704 	addi	fp,sp,28
+ 802bd34:	e13ffb15 	stw	r4,-20(fp)
+ 802bd38:	e17ffa15 	stw	r5,-24(fp)
+ 802bd3c:	e1bff915 	stw	r6,-28(fp)
+   char logbuf[10];
+#endif
+   struct socket *   so;
+   struct mbuf *  nam;
+
+   so = LONG2SO(s);
+ 802bd40:	e0bffb17 	ldw	r2,-20(fp)
+ 802bd44:	10bffc04 	addi	r2,r2,-16
+ 802bd48:	100490ba 	slli	r2,r2,2
+ 802bd4c:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802bd50:	008201b4 	movhi	r2,2054
+ 802bd54:	10b87104 	addi	r2,r2,-7740
+ 802bd58:	e0bfff15 	stw	r2,-4(fp)
+ 802bd5c:	00000606 	br	802bd78 <t_accept+0x54>
+ 802bd60:	e0ffff17 	ldw	r3,-4(fp)
+ 802bd64:	e0bffe17 	ldw	r2,-8(fp)
+ 802bd68:	18800626 	beq	r3,r2,802bd84 <t_accept+0x60>
+ 802bd6c:	e0bfff17 	ldw	r2,-4(fp)
+ 802bd70:	10800017 	ldw	r2,0(r2)
+ 802bd74:	e0bfff15 	stw	r2,-4(fp)
+ 802bd78:	e0bfff17 	ldw	r2,-4(fp)
+ 802bd7c:	103ff81e 	bne	r2,zero,802bd60 <t_accept+0x3c>
+ 802bd80:	00000106 	br	802bd88 <t_accept+0x64>
+ 802bd84:	0001883a 	nop
+ 802bd88:	e0ffff17 	ldw	r3,-4(fp)
+ 802bd8c:	e0bffe17 	ldw	r2,-8(fp)
+ 802bd90:	18800326 	beq	r3,r2,802bda0 <t_accept+0x7c>
+ 802bd94:	8028cd40 	call	8028cd4 <dtrap>
+ 802bd98:	00bfffc4 	movi	r2,-1
+ 802bd9c:	00007006 	br	802bf60 <t_accept+0x23c>
+   DOMAIN_CHECK(so, *addrlen);
+ 802bda0:	e0bff917 	ldw	r2,-28(fp)
+ 802bda4:	10800017 	ldw	r2,0(r2)
+ 802bda8:	100b883a 	mov	r5,r2
+ 802bdac:	e13ffe17 	ldw	r4,-8(fp)
+ 802bdb0:	802ba200 	call	802ba20 <DOMAIN_CHECK>
+
+   so->so_error = 0;
+ 802bdb4:	e0bffe17 	ldw	r2,-8(fp)
+ 802bdb8:	10000615 	stw	zero,24(r2)
+   INET_TRACE (INETM_SOCKET,
+      ("INET:accept:so %x so_qlen %d so_state %x\n", so, so->so_qlen, so->so_state));
+   if ((so->so_options & SO_ACCEPTCONN) == 0)
+ 802bdbc:	e0bffe17 	ldw	r2,-8(fp)
+ 802bdc0:	10800417 	ldw	r2,16(r2)
+ 802bdc4:	1080008c 	andi	r2,r2,2
+ 802bdc8:	1000051e 	bne	r2,zero,802bde0 <t_accept+0xbc>
+   {
+      so->so_error = EINVAL;
+ 802bdcc:	e0bffe17 	ldw	r2,-8(fp)
+ 802bdd0:	00c00584 	movi	r3,22
+ 802bdd4:	10c00615 	stw	r3,24(r2)
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+ 802bdd8:	00bfffc4 	movi	r2,-1
+ 802bddc:	00006006 	br	802bf60 <t_accept+0x23c>
+   }
+   if ((so->so_state & SS_NBIO) && so->so_qlen == 0)
+ 802bde0:	e0bffe17 	ldw	r2,-8(fp)
+ 802bde4:	1080088b 	ldhu	r2,34(r2)
+ 802bde8:	10bfffcc 	andi	r2,r2,65535
+ 802bdec:	1080400c 	andi	r2,r2,256
+ 802bdf0:	10000b26 	beq	r2,zero,802be20 <t_accept+0xfc>
+ 802bdf4:	e0bffe17 	ldw	r2,-8(fp)
+ 802bdf8:	10801e43 	ldbu	r2,121(r2)
+ 802bdfc:	10803fcc 	andi	r2,r2,255
+ 802be00:	1080201c 	xori	r2,r2,128
+ 802be04:	10bfe004 	addi	r2,r2,-128
+ 802be08:	1000051e 	bne	r2,zero,802be20 <t_accept+0xfc>
+   {
+      so->so_error = EWOULDBLOCK;
+ 802be0c:	e0bffe17 	ldw	r2,-8(fp)
+ 802be10:	00c002c4 	movi	r3,11
+ 802be14:	10c00615 	stw	r3,24(r2)
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+ 802be18:	00bfffc4 	movi	r2,-1
+ 802be1c:	00005006 	br	802bf60 <t_accept+0x23c>
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802be20:	0009883a 	mov	r4,zero
+ 802be24:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   while (so->so_qlen == 0 && so->so_error == 0)
+ 802be28:	00001006 	br	802be6c <t_accept+0x148>
+   {
+      if (so->so_state & SS_CANTRCVMORE)
+ 802be2c:	e0bffe17 	ldw	r2,-8(fp)
+ 802be30:	1080088b 	ldhu	r2,34(r2)
+ 802be34:	10bfffcc 	andi	r2,r2,65535
+ 802be38:	1080080c 	andi	r2,r2,32
+ 802be3c:	10000726 	beq	r2,zero,802be5c <t_accept+0x138>
+      {
+         so->so_error = ECONNABORTED;
+ 802be40:	e0bffe17 	ldw	r2,-8(fp)
+ 802be44:	00c01c44 	movi	r3,113
+ 802be48:	10c00615 	stw	r3,24(r2)
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 802be4c:	0009883a 	mov	r4,zero
+ 802be50:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return SOCKET_ERROR;
+ 802be54:	00bfffc4 	movi	r2,-1
+ 802be58:	00004106 	br	802bf60 <t_accept+0x23c>
+      }
+      tcp_sleep ((char *)&so->so_timeo);
+ 802be5c:	e0bffe17 	ldw	r2,-8(fp)
+ 802be60:	10800904 	addi	r2,r2,36
+ 802be64:	1009883a 	mov	r4,r2
+ 802be68:	8027a540 	call	8027a54 <tcp_sleep>
+   while (so->so_qlen == 0 && so->so_error == 0)
+ 802be6c:	e0bffe17 	ldw	r2,-8(fp)
+ 802be70:	10801e43 	ldbu	r2,121(r2)
+ 802be74:	10803fcc 	andi	r2,r2,255
+ 802be78:	1080201c 	xori	r2,r2,128
+ 802be7c:	10bfe004 	addi	r2,r2,-128
+ 802be80:	1000031e 	bne	r2,zero,802be90 <t_accept+0x16c>
+ 802be84:	e0bffe17 	ldw	r2,-8(fp)
+ 802be88:	10800617 	ldw	r2,24(r2)
+ 802be8c:	103fe726 	beq	r2,zero,802be2c <t_accept+0x108>
+   }
+   if (so->so_error)
+ 802be90:	e0bffe17 	ldw	r2,-8(fp)
+ 802be94:	10800617 	ldw	r2,24(r2)
+ 802be98:	10000426 	beq	r2,zero,802beac <t_accept+0x188>
+   {
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802be9c:	0009883a 	mov	r4,zero
+ 802bea0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return SOCKET_ERROR;
+ 802bea4:	00bfffc4 	movi	r2,-1
+ 802bea8:	00002d06 	br	802bf60 <t_accept+0x23c>
+   }
+   nam = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+ 802beac:	01400404 	movi	r5,16
+ 802beb0:	01000244 	movi	r4,9
+ 802beb4:	8029a700 	call	8029a70 <m_getnbuf>
+ 802beb8:	e0bffd15 	stw	r2,-12(fp)
+   if (nam == NULL) 
+ 802bebc:	e0bffd17 	ldw	r2,-12(fp)
+ 802bec0:	1000071e 	bne	r2,zero,802bee0 <t_accept+0x1bc>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bec4:	0009883a 	mov	r4,zero
+ 802bec8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      so->so_error = ENOMEM;
+ 802becc:	e0bffe17 	ldw	r2,-8(fp)
+ 802bed0:	00c00304 	movi	r3,12
+ 802bed4:	10c00615 	stw	r3,24(r2)
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+ 802bed8:	00bfffc4 	movi	r2,-1
+ 802bedc:	00002006 	br	802bf60 <t_accept+0x23c>
+   }
+   { 
+      struct socket *aso = so->so_q;
+ 802bee0:	e0bffe17 	ldw	r2,-8(fp)
+ 802bee4:	10801d17 	ldw	r2,116(r2)
+ 802bee8:	e0bffc15 	stw	r2,-16(fp)
+      if (soqremque (aso, 1) == 0)
+ 802beec:	01400044 	movi	r5,1
+ 802bef0:	e13ffc17 	ldw	r4,-16(fp)
+ 802bef4:	802f6ec0 	call	802f6ec <soqremque>
+ 802bef8:	1000031e 	bne	r2,zero,802bf08 <t_accept+0x1e4>
+         panic("accept");
+ 802befc:	01020174 	movhi	r4,2053
+ 802bf00:	212a7404 	addi	r4,r4,-22064
+ 802bf04:	80271780 	call	8027178 <panic>
+      so = aso;
+ 802bf08:	e0bffc17 	ldw	r2,-16(fp)
+ 802bf0c:	e0bffe15 	stw	r2,-8(fp)
+   }
+   (void)soaccept (so, nam);
+ 802bf10:	e17ffd17 	ldw	r5,-12(fp)
+ 802bf14:	e13ffe17 	ldw	r4,-8(fp)
+ 802bf18:	802d74c0 	call	802d74c <soaccept>
+      INET_TRACE (INETM_SOCKET, ("INET:accept:done so %lx port %d addr %lx\n",
+       so, sin->sin_port, sin->sin_addr.s_addr));
+   }
+#endif   /* TRACE_INET */
+   /* return the addressing info in the passed structure */
+   if (addr != NULL)
+ 802bf1c:	e0bffa17 	ldw	r2,-24(fp)
+ 802bf20:	10000826 	beq	r2,zero,802bf44 <t_accept+0x220>
+      MEMCPY(addr, nam->m_data, *addrlen);
+ 802bf24:	e0bffd17 	ldw	r2,-12(fp)
+ 802bf28:	10c00317 	ldw	r3,12(r2)
+ 802bf2c:	e0bff917 	ldw	r2,-28(fp)
+ 802bf30:	10800017 	ldw	r2,0(r2)
+ 802bf34:	100d883a 	mov	r6,r2
+ 802bf38:	180b883a 	mov	r5,r3
+ 802bf3c:	e13ffa17 	ldw	r4,-24(fp)
+ 802bf40:	80086b80 	call	80086b8 <memcpy>
+   m_freem (nam);
+ 802bf44:	e13ffd17 	ldw	r4,-12(fp)
+ 802bf48:	8029cfc0 	call	8029cfc <m_freem>
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802bf4c:	0009883a 	mov	r4,zero
+ 802bf50:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   SOC_RANGE(so);
+   return SO2LONG(so);
+ 802bf54:	e0bffe17 	ldw	r2,-8(fp)
+ 802bf58:	1004d0ba 	srli	r2,r2,2
+ 802bf5c:	10800404 	addi	r2,r2,16
+}
+ 802bf60:	e037883a 	mov	sp,fp
+ 802bf64:	dfc00117 	ldw	ra,4(sp)
+ 802bf68:	df000017 	ldw	fp,0(sp)
+ 802bf6c:	dec00204 	addi	sp,sp,8
+ 802bf70:	f800283a 	ret
+
+0802bf74 <t_connect>:
+
+int
+t_connect(long s, 
+   struct sockaddr * addr,
+   int   addrlen)
+{
+ 802bf74:	defff804 	addi	sp,sp,-32
+ 802bf78:	dfc00715 	stw	ra,28(sp)
+ 802bf7c:	df000615 	stw	fp,24(sp)
+ 802bf80:	df000604 	addi	fp,sp,24
+ 802bf84:	e13ffc15 	stw	r4,-16(fp)
+ 802bf88:	e17ffb15 	stw	r5,-20(fp)
+ 802bf8c:	e1bffa15 	stw	r6,-24(fp)
+   struct socket *   so;
+   struct mbuf *  nam;
+
+   so = LONG2SO(s);
+ 802bf90:	e0bffc17 	ldw	r2,-16(fp)
+ 802bf94:	10bffc04 	addi	r2,r2,-16
+ 802bf98:	100490ba 	slli	r2,r2,2
+ 802bf9c:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802bfa0:	008201b4 	movhi	r2,2054
+ 802bfa4:	10b87104 	addi	r2,r2,-7740
+ 802bfa8:	e0bfff15 	stw	r2,-4(fp)
+ 802bfac:	00000606 	br	802bfc8 <t_connect+0x54>
+ 802bfb0:	e0ffff17 	ldw	r3,-4(fp)
+ 802bfb4:	e0bffe17 	ldw	r2,-8(fp)
+ 802bfb8:	18800626 	beq	r3,r2,802bfd4 <t_connect+0x60>
+ 802bfbc:	e0bfff17 	ldw	r2,-4(fp)
+ 802bfc0:	10800017 	ldw	r2,0(r2)
+ 802bfc4:	e0bfff15 	stw	r2,-4(fp)
+ 802bfc8:	e0bfff17 	ldw	r2,-4(fp)
+ 802bfcc:	103ff81e 	bne	r2,zero,802bfb0 <t_connect+0x3c>
+ 802bfd0:	00000106 	br	802bfd8 <t_connect+0x64>
+ 802bfd4:	0001883a 	nop
+ 802bfd8:	e0ffff17 	ldw	r3,-4(fp)
+ 802bfdc:	e0bffe17 	ldw	r2,-8(fp)
+ 802bfe0:	18800326 	beq	r3,r2,802bff0 <t_connect+0x7c>
+ 802bfe4:	8028cd40 	call	8028cd4 <dtrap>
+ 802bfe8:	00bfffc4 	movi	r2,-1
+ 802bfec:	00007806 	br	802c1d0 <t_connect+0x25c>
+   DOMAIN_CHECK(so, addrlen);
+ 802bff0:	e17ffa17 	ldw	r5,-24(fp)
+ 802bff4:	e13ffe17 	ldw	r4,-8(fp)
+ 802bff8:	802ba200 	call	802ba20 <DOMAIN_CHECK>
+
+#ifdef NB_CONNECT
+   /* need to test non blocking connect bits in case this is a 
+      poll of a previous request */
+   if (so->so_state & SS_NBIO)
+ 802bffc:	e0bffe17 	ldw	r2,-8(fp)
+ 802c000:	1080088b 	ldhu	r2,34(r2)
+ 802c004:	10bfffcc 	andi	r2,r2,65535
+ 802c008:	1080400c 	andi	r2,r2,256
+ 802c00c:	10002426 	beq	r2,zero,802c0a0 <t_connect+0x12c>
+   {
+      if (so->so_state & SS_ISCONNECTING) /* still trying */
+ 802c010:	e0bffe17 	ldw	r2,-8(fp)
+ 802c014:	1080088b 	ldhu	r2,34(r2)
+ 802c018:	10bfffcc 	andi	r2,r2,65535
+ 802c01c:	1080010c 	andi	r2,r2,4
+ 802c020:	10000526 	beq	r2,zero,802c038 <t_connect+0xc4>
+      {
+         so->so_error = EINPROGRESS;
+ 802c024:	e0bffe17 	ldw	r2,-8(fp)
+ 802c028:	00c01dc4 	movi	r3,119
+ 802c02c:	10c00615 	stw	r3,24(r2)
+         return SOCKET_ERROR;
+ 802c030:	00bfffc4 	movi	r2,-1
+ 802c034:	00006606 	br	802c1d0 <t_connect+0x25c>
+      }
+      if (so->so_state & SS_ISCONNECTED)  /* connected OK */
+ 802c038:	e0bffe17 	ldw	r2,-8(fp)
+ 802c03c:	1080088b 	ldhu	r2,34(r2)
+ 802c040:	10bfffcc 	andi	r2,r2,65535
+ 802c044:	1080008c 	andi	r2,r2,2
+ 802c048:	10000426 	beq	r2,zero,802c05c <t_connect+0xe8>
+      {
+         so->so_error = 0;
+ 802c04c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c050:	10000615 	stw	zero,24(r2)
+         return 0;
+ 802c054:	0005883a 	mov	r2,zero
+ 802c058:	00005d06 	br	802c1d0 <t_connect+0x25c>
+      }
+      if (so->so_state & SS_WASCONNECTING)
+ 802c05c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c060:	1080088b 	ldhu	r2,34(r2)
+ 802c064:	10bfffcc 	andi	r2,r2,65535
+ 802c068:	1088000c 	andi	r2,r2,8192
+ 802c06c:	10000c26 	beq	r2,zero,802c0a0 <t_connect+0x12c>
+      {
+         so->so_state &= ~SS_WASCONNECTING;
+ 802c070:	e0bffe17 	ldw	r2,-8(fp)
+ 802c074:	10c0088b 	ldhu	r3,34(r2)
+ 802c078:	00b7ffc4 	movi	r2,-8193
+ 802c07c:	1884703a 	and	r2,r3,r2
+ 802c080:	1007883a 	mov	r3,r2
+ 802c084:	e0bffe17 	ldw	r2,-8(fp)
+ 802c088:	10c0088d 	sth	r3,34(r2)
+         if (so->so_error) /* connect error - maybe timeout */
+ 802c08c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c090:	10800617 	ldw	r2,24(r2)
+ 802c094:	10000226 	beq	r2,zero,802c0a0 <t_connect+0x12c>
+            return SOCKET_ERROR;
+ 802c098:	00bfffc4 	movi	r2,-1
+ 802c09c:	00004c06 	br	802c1d0 <t_connect+0x25c>
+      }
+   }
+#endif   /*  NB_CONNECT */
+
+   so->so_error = 0;
+ 802c0a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802c0a4:	10000615 	stw	zero,24(r2)
+
+   if ((nam = sockargs (addr, addrlen, MT_SONAME))
+ 802c0a8:	01800244 	movi	r6,9
+ 802c0ac:	e17ffa17 	ldw	r5,-24(fp)
+ 802c0b0:	e13ffb17 	ldw	r4,-20(fp)
+ 802c0b4:	802cf300 	call	802cf30 <sockargs>
+ 802c0b8:	e0bffd15 	stw	r2,-12(fp)
+ 802c0bc:	e0bffd17 	ldw	r2,-12(fp)
+ 802c0c0:	1000051e 	bne	r2,zero,802c0d8 <t_connect+0x164>
+       == NULL)
+   {
+      so->so_error = ENOMEM;
+ 802c0c4:	e0bffe17 	ldw	r2,-8(fp)
+ 802c0c8:	00c00304 	movi	r3,12
+ 802c0cc:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802c0d0:	00bfffc4 	movi	r2,-1
+ 802c0d4:	00003e06 	br	802c1d0 <t_connect+0x25c>
+      INET_TRACE (INETM_SOCKET, ("INET: connect, port %d addr %lx\n",
+       sin->sin_port, sin->sin_addr.s_addr));
+   }
+#endif   /* TRACE_DEBUG */
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802c0d8:	0009883a 	mov	r4,zero
+ 802c0dc:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   if ((so->so_error = soconnect (so, nam)) != 0)
+ 802c0e0:	e17ffd17 	ldw	r5,-12(fp)
+ 802c0e4:	e13ffe17 	ldw	r4,-8(fp)
+ 802c0e8:	802d7e40 	call	802d7e4 <soconnect>
+ 802c0ec:	1007883a 	mov	r3,r2
+ 802c0f0:	e0bffe17 	ldw	r2,-8(fp)
+ 802c0f4:	10c00615 	stw	r3,24(r2)
+ 802c0f8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c0fc:	10800617 	ldw	r2,24(r2)
+ 802c100:	10001b1e 	bne	r2,zero,802c170 <t_connect+0x1fc>
+      goto bad;
+
+#ifdef NB_CONNECT
+   /* need to test non blocking connect bits after soconnect() call */
+   if ((so->so_state & SS_NBIO)&& (so->so_state & SS_ISCONNECTING))
+ 802c104:	e0bffe17 	ldw	r2,-8(fp)
+ 802c108:	1080088b 	ldhu	r2,34(r2)
+ 802c10c:	10bfffcc 	andi	r2,r2,65535
+ 802c110:	1080400c 	andi	r2,r2,256
+ 802c114:	10000d26 	beq	r2,zero,802c14c <t_connect+0x1d8>
+ 802c118:	e0bffe17 	ldw	r2,-8(fp)
+ 802c11c:	1080088b 	ldhu	r2,34(r2)
+ 802c120:	10bfffcc 	andi	r2,r2,65535
+ 802c124:	1080010c 	andi	r2,r2,4
+ 802c128:	10000826 	beq	r2,zero,802c14c <t_connect+0x1d8>
+   {
+      so->so_error = EINPROGRESS;
+ 802c12c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c130:	00c01dc4 	movi	r3,119
+ 802c134:	10c00615 	stw	r3,24(r2)
+      goto bad;
+ 802c138:	00001006 	br	802c17c <t_connect+0x208>
+   INET_TRACE (INETM_SOCKET, ("INET: connect, so %x so_state %x so_error %d\n",
+    so, so->so_state, so->so_error));
+
+   while ((so->so_state & SS_ISCONNECTING) && so->so_error == 0) 
+   {
+      tcp_sleep ((char *)&so->so_timeo);
+ 802c13c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c140:	10800904 	addi	r2,r2,36
+ 802c144:	1009883a 	mov	r4,r2
+ 802c148:	8027a540 	call	8027a54 <tcp_sleep>
+   while ((so->so_state & SS_ISCONNECTING) && so->so_error == 0) 
+ 802c14c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c150:	1080088b 	ldhu	r2,34(r2)
+ 802c154:	10bfffcc 	andi	r2,r2,65535
+ 802c158:	1080010c 	andi	r2,r2,4
+ 802c15c:	10000626 	beq	r2,zero,802c178 <t_connect+0x204>
+ 802c160:	e0bffe17 	ldw	r2,-8(fp)
+ 802c164:	10800617 	ldw	r2,24(r2)
+ 802c168:	103ff426 	beq	r2,zero,802c13c <t_connect+0x1c8>
+   }
+bad:
+ 802c16c:	00000206 	br	802c178 <t_connect+0x204>
+      goto bad;
+ 802c170:	0001883a 	nop
+ 802c174:	00000106 	br	802c17c <t_connect+0x208>
+bad:
+ 802c178:	0001883a 	nop
+   if (so->so_error != EINPROGRESS)
+ 802c17c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c180:	10800617 	ldw	r2,24(r2)
+ 802c184:	10801de0 	cmpeqi	r2,r2,119
+ 802c188:	1000071e 	bne	r2,zero,802c1a8 <t_connect+0x234>
+      so->so_state &= ~(SS_ISCONNECTING|SS_WASCONNECTING);
+ 802c18c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c190:	10c0088b 	ldhu	r3,34(r2)
+ 802c194:	00b7fec4 	movi	r2,-8197
+ 802c198:	1884703a 	and	r2,r3,r2
+ 802c19c:	1007883a 	mov	r3,r2
+ 802c1a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802c1a4:	10c0088d 	sth	r3,34(r2)
+   m_freem (nam);
+ 802c1a8:	e13ffd17 	ldw	r4,-12(fp)
+ 802c1ac:	8029cfc0 	call	8029cfc <m_freem>
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c1b0:	0009883a 	mov	r4,zero
+ 802c1b4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (so->so_error)
+ 802c1b8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c1bc:	10800617 	ldw	r2,24(r2)
+ 802c1c0:	10000226 	beq	r2,zero,802c1cc <t_connect+0x258>
+   {
+/*      printf("t_connect(): so_error = %d\n", so->so_error);*/
+      return SOCKET_ERROR;
+ 802c1c4:	00bfffc4 	movi	r2,-1
+ 802c1c8:	00000106 	br	802c1d0 <t_connect+0x25c>
+
+   }
+      return 0;
+ 802c1cc:	0005883a 	mov	r2,zero
+}
+ 802c1d0:	e037883a 	mov	sp,fp
+ 802c1d4:	dfc00117 	ldw	ra,4(sp)
+ 802c1d8:	df000017 	ldw	fp,0(sp)
+ 802c1dc:	dec00204 	addi	sp,sp,8
+ 802c1e0:	f800283a 	ret
+
+0802c1e4 <t_getpeername>:
+ * RETURNS: 
+ */
+
+int
+t_getpeername(long s, struct sockaddr * addr, int * addrlen)
+{
+ 802c1e4:	defffb04 	addi	sp,sp,-20
+ 802c1e8:	dfc00415 	stw	ra,16(sp)
+ 802c1ec:	df000315 	stw	fp,12(sp)
+ 802c1f0:	df000304 	addi	fp,sp,12
+ 802c1f4:	e13fff15 	stw	r4,-4(fp)
+ 802c1f8:	e17ffe15 	stw	r5,-8(fp)
+ 802c1fc:	e1bffd15 	stw	r6,-12(fp)
+   return(t_getname(s, addr, addrlen, PRU_PEERADDR));
+ 802c200:	01c00404 	movi	r7,16
+ 802c204:	e1bffd17 	ldw	r6,-12(fp)
+ 802c208:	e17ffe17 	ldw	r5,-8(fp)
+ 802c20c:	e13fff17 	ldw	r4,-4(fp)
+ 802c210:	802c26c0 	call	802c26c <t_getname>
+}
+ 802c214:	e037883a 	mov	sp,fp
+ 802c218:	dfc00117 	ldw	ra,4(sp)
+ 802c21c:	df000017 	ldw	fp,0(sp)
+ 802c220:	dec00204 	addi	sp,sp,8
+ 802c224:	f800283a 	ret
+
+0802c228 <t_getsockname>:
+ * RETURNS: 
+ */
+
+int 
+t_getsockname(long s, struct sockaddr * addr, int * addrlen)
+{
+ 802c228:	defffb04 	addi	sp,sp,-20
+ 802c22c:	dfc00415 	stw	ra,16(sp)
+ 802c230:	df000315 	stw	fp,12(sp)
+ 802c234:	df000304 	addi	fp,sp,12
+ 802c238:	e13fff15 	stw	r4,-4(fp)
+ 802c23c:	e17ffe15 	stw	r5,-8(fp)
+ 802c240:	e1bffd15 	stw	r6,-12(fp)
+   return(t_getname(s, addr, addrlen, PRU_SOCKADDR));
+ 802c244:	01c003c4 	movi	r7,15
+ 802c248:	e1bffd17 	ldw	r6,-12(fp)
+ 802c24c:	e17ffe17 	ldw	r5,-8(fp)
+ 802c250:	e13fff17 	ldw	r4,-4(fp)
+ 802c254:	802c26c0 	call	802c26c <t_getname>
+}
+ 802c258:	e037883a 	mov	sp,fp
+ 802c25c:	dfc00117 	ldw	ra,4(sp)
+ 802c260:	df000017 	ldw	fp,0(sp)
+ 802c264:	dec00204 	addi	sp,sp,8
+ 802c268:	f800283a 	ret
+
+0802c26c <t_getname>:
+ * RETURNS: 
+ */
+
+static int
+t_getname(long s, struct sockaddr * addr, int * addrlen, int opcode)
+{
+ 802c26c:	defff604 	addi	sp,sp,-40
+ 802c270:	dfc00915 	stw	ra,36(sp)
+ 802c274:	df000815 	stw	fp,32(sp)
+ 802c278:	df000804 	addi	fp,sp,32
+ 802c27c:	e13ffb15 	stw	r4,-20(fp)
+ 802c280:	e17ffa15 	stw	r5,-24(fp)
+ 802c284:	e1bff915 	stw	r6,-28(fp)
+ 802c288:	e1fff815 	stw	r7,-32(fp)
+   struct socket *   so;
+   struct mbuf *  m;
+   int   err;
+
+   so = LONG2SO(s);
+ 802c28c:	e0bffb17 	ldw	r2,-20(fp)
+ 802c290:	10bffc04 	addi	r2,r2,-16
+ 802c294:	100490ba 	slli	r2,r2,2
+ 802c298:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802c29c:	008201b4 	movhi	r2,2054
+ 802c2a0:	10b87104 	addi	r2,r2,-7740
+ 802c2a4:	e0bfff15 	stw	r2,-4(fp)
+ 802c2a8:	00000606 	br	802c2c4 <t_getname+0x58>
+ 802c2ac:	e0ffff17 	ldw	r3,-4(fp)
+ 802c2b0:	e0bffe17 	ldw	r2,-8(fp)
+ 802c2b4:	18800626 	beq	r3,r2,802c2d0 <t_getname+0x64>
+ 802c2b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802c2bc:	10800017 	ldw	r2,0(r2)
+ 802c2c0:	e0bfff15 	stw	r2,-4(fp)
+ 802c2c4:	e0bfff17 	ldw	r2,-4(fp)
+ 802c2c8:	103ff81e 	bne	r2,zero,802c2ac <t_getname+0x40>
+ 802c2cc:	00000106 	br	802c2d4 <t_getname+0x68>
+ 802c2d0:	0001883a 	nop
+ 802c2d4:	e0ffff17 	ldw	r3,-4(fp)
+ 802c2d8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c2dc:	18800326 	beq	r3,r2,802c2ec <t_getname+0x80>
+ 802c2e0:	8028cd40 	call	8028cd4 <dtrap>
+ 802c2e4:	00bfffc4 	movi	r2,-1
+ 802c2e8:	00005306 	br	802c438 <t_getname+0x1cc>
+
+   so->so_error = 0;
+ 802c2ec:	e0bffe17 	ldw	r2,-8(fp)
+ 802c2f0:	10000615 	stw	zero,24(r2)
+   INET_TRACE (INETM_SOCKET, ("INET:get[sock|peer]name so %x\n", so));
+   if((opcode == PRU_PEERADDR) && (so->so_state & SS_ISCONNECTED) == 0)
+ 802c2f4:	e0bff817 	ldw	r2,-32(fp)
+ 802c2f8:	10800418 	cmpnei	r2,r2,16
+ 802c2fc:	10000a1e 	bne	r2,zero,802c328 <t_getname+0xbc>
+ 802c300:	e0bffe17 	ldw	r2,-8(fp)
+ 802c304:	1080088b 	ldhu	r2,34(r2)
+ 802c308:	10bfffcc 	andi	r2,r2,65535
+ 802c30c:	1080008c 	andi	r2,r2,2
+ 802c310:	1000051e 	bne	r2,zero,802c328 <t_getname+0xbc>
+   {
+      so->so_error = ENOTCONN;
+ 802c314:	e0bffe17 	ldw	r2,-8(fp)
+ 802c318:	00c02004 	movi	r3,128
+ 802c31c:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802c320:	00bfffc4 	movi	r2,-1
+ 802c324:	00004406 	br	802c438 <t_getname+0x1cc>
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802c328:	0009883a 	mov	r4,zero
+ 802c32c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+ 802c330:	01400404 	movi	r5,16
+ 802c334:	01000244 	movi	r4,9
+ 802c338:	8029a700 	call	8029a70 <m_getnbuf>
+ 802c33c:	e0bffd15 	stw	r2,-12(fp)
+   if (m == NULL) 
+ 802c340:	e0bffd17 	ldw	r2,-12(fp)
+ 802c344:	1000071e 	bne	r2,zero,802c364 <t_getname+0xf8>
+   {
+      so->so_error = ENOMEM;
+ 802c348:	e0bffe17 	ldw	r2,-8(fp)
+ 802c34c:	00c00304 	movi	r3,12
+ 802c350:	10c00615 	stw	r3,24(r2)
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c354:	0009883a 	mov	r4,zero
+ 802c358:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return SOCKET_ERROR;
+ 802c35c:	00bfffc4 	movi	r2,-1
+ 802c360:	00003506 	br	802c438 <t_getname+0x1cc>
+   }
+   so->so_req = opcode;
+ 802c364:	e0bffe17 	ldw	r2,-8(fp)
+ 802c368:	e0fff817 	ldw	r3,-32(fp)
+ 802c36c:	10c00715 	stw	r3,28(r2)
+   if ((err = (*so->so_proto->pr_usrreq)(so, 0, m)) != 0)
+ 802c370:	e0bffe17 	ldw	r2,-8(fp)
+ 802c374:	10800217 	ldw	r2,8(r2)
+ 802c378:	10800317 	ldw	r2,12(r2)
+ 802c37c:	e1bffd17 	ldw	r6,-12(fp)
+ 802c380:	000b883a 	mov	r5,zero
+ 802c384:	e13ffe17 	ldw	r4,-8(fp)
+ 802c388:	103ee83a 	callr	r2
+ 802c38c:	e0bffc15 	stw	r2,-16(fp)
+ 802c390:	e0bffc17 	ldw	r2,-16(fp)
+ 802c394:	1000191e 	bne	r2,zero,802c3fc <t_getname+0x190>
+      goto bad;
+
+#ifdef IP_V4
+   if(so->so_domain == AF_INET)
+ 802c398:	e0bffe17 	ldw	r2,-8(fp)
+ 802c39c:	10800517 	ldw	r2,20(r2)
+ 802c3a0:	10800098 	cmpnei	r2,r2,2
+ 802c3a4:	1000171e 	bne	r2,zero,802c404 <t_getname+0x198>
+   {
+      if(*addrlen < sizeof(struct sockaddr_in))
+ 802c3a8:	e0bff917 	ldw	r2,-28(fp)
+ 802c3ac:	10800017 	ldw	r2,0(r2)
+ 802c3b0:	10800428 	cmpgeui	r2,r2,16
+ 802c3b4:	1000071e 	bne	r2,zero,802c3d4 <t_getname+0x168>
+      {
+         dtrap();    /* programming error */
+ 802c3b8:	8028cd40 	call	8028cd4 <dtrap>
+         m_freem(m);
+ 802c3bc:	e13ffd17 	ldw	r4,-12(fp)
+ 802c3c0:	8029cfc0 	call	8029cfc <m_freem>
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c3c4:	0009883a 	mov	r4,zero
+ 802c3c8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return EINVAL;
+ 802c3cc:	00800584 	movi	r2,22
+ 802c3d0:	00001906 	br	802c438 <t_getname+0x1cc>
+      }
+      MEMCPY(addr, m->m_data, sizeof(struct sockaddr_in));
+ 802c3d4:	e0bffd17 	ldw	r2,-12(fp)
+ 802c3d8:	10800317 	ldw	r2,12(r2)
+ 802c3dc:	01800404 	movi	r6,16
+ 802c3e0:	100b883a 	mov	r5,r2
+ 802c3e4:	e13ffa17 	ldw	r4,-24(fp)
+ 802c3e8:	80086b80 	call	80086b8 <memcpy>
+      *addrlen = sizeof(struct sockaddr_in);
+ 802c3ec:	e0bff917 	ldw	r2,-28(fp)
+ 802c3f0:	00c00404 	movi	r3,16
+ 802c3f4:	10c00015 	stw	r3,0(r2)
+ 802c3f8:	00000306 	br	802c408 <t_getname+0x19c>
+      goto bad;
+ 802c3fc:	0001883a 	nop
+ 802c400:	00000106 	br	802c408 <t_getname+0x19c>
+      *addrlen = sizeof(struct sockaddr_in6);
+   }
+#endif   /* IP_V6 */
+
+
+bad:
+ 802c404:	0001883a 	nop
+   m_freem(m);
+ 802c408:	e13ffd17 	ldw	r4,-12(fp)
+ 802c40c:	8029cfc0 	call	8029cfc <m_freem>
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c410:	0009883a 	mov	r4,zero
+ 802c414:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (err) 
+ 802c418:	e0bffc17 	ldw	r2,-16(fp)
+ 802c41c:	10000526 	beq	r2,zero,802c434 <t_getname+0x1c8>
+   {
+      so->so_error = err;
+ 802c420:	e0bffe17 	ldw	r2,-8(fp)
+ 802c424:	e0fffc17 	ldw	r3,-16(fp)
+ 802c428:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802c42c:	00bfffc4 	movi	r2,-1
+ 802c430:	00000106 	br	802c438 <t_getname+0x1cc>
+   }
+   return 0;
+ 802c434:	0005883a 	mov	r2,zero
+}
+ 802c438:	e037883a 	mov	sp,fp
+ 802c43c:	dfc00117 	ldw	ra,4(sp)
+ 802c440:	df000017 	ldw	fp,0(sp)
+ 802c444:	dec00204 	addi	sp,sp,8
+ 802c448:	f800283a 	ret
+
+0802c44c <t_setsockopt>:
+t_setsockopt(long s,
+   int   level,
+   int   name,
+   void * arg,
+   int arglen)
+{
+ 802c44c:	defff704 	addi	sp,sp,-36
+ 802c450:	dfc00815 	stw	ra,32(sp)
+ 802c454:	df000715 	stw	fp,28(sp)
+ 802c458:	df000704 	addi	fp,sp,28
+ 802c45c:	e13ffc15 	stw	r4,-16(fp)
+ 802c460:	e17ffb15 	stw	r5,-20(fp)
+ 802c464:	e1bffa15 	stw	r6,-24(fp)
+ 802c468:	e1fff915 	stw	r7,-28(fp)
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+ 802c46c:	e0bffc17 	ldw	r2,-16(fp)
+ 802c470:	10bffc04 	addi	r2,r2,-16
+ 802c474:	100490ba 	slli	r2,r2,2
+ 802c478:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802c47c:	008201b4 	movhi	r2,2054
+ 802c480:	10b87104 	addi	r2,r2,-7740
+ 802c484:	e0bfff15 	stw	r2,-4(fp)
+ 802c488:	00000606 	br	802c4a4 <t_setsockopt+0x58>
+ 802c48c:	e0ffff17 	ldw	r3,-4(fp)
+ 802c490:	e0bffe17 	ldw	r2,-8(fp)
+ 802c494:	18800626 	beq	r3,r2,802c4b0 <t_setsockopt+0x64>
+ 802c498:	e0bfff17 	ldw	r2,-4(fp)
+ 802c49c:	10800017 	ldw	r2,0(r2)
+ 802c4a0:	e0bfff15 	stw	r2,-4(fp)
+ 802c4a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802c4a8:	103ff81e 	bne	r2,zero,802c48c <t_setsockopt+0x40>
+ 802c4ac:	00000106 	br	802c4b4 <t_setsockopt+0x68>
+ 802c4b0:	0001883a 	nop
+ 802c4b4:	e0ffff17 	ldw	r3,-4(fp)
+ 802c4b8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c4bc:	18800326 	beq	r3,r2,802c4cc <t_setsockopt+0x80>
+ 802c4c0:	8028cd40 	call	8028cd4 <dtrap>
+ 802c4c4:	00bfffc4 	movi	r2,-1
+ 802c4c8:	00004b06 	br	802c5f8 <t_setsockopt+0x1ac>
+   USE_ARG(arglen);
+
+   LOCK_NET_RESOURCE (NET_RESID);
+ 802c4cc:	0009883a 	mov	r4,zero
+ 802c4d0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   so->so_error = 0;
+ 802c4d4:	e0bffe17 	ldw	r2,-8(fp)
+ 802c4d8:	10000615 	stw	zero,24(r2)
+   INET_TRACE (INETM_SOCKET,
+    ("INET: setsockopt: name %x val %x valsize %d\n",
+    name, val));
+
+   /* is it a level IP_OPTIONS call? */
+   if (level != IP_OPTIONS)
+ 802c4dc:	e0bffb17 	ldw	r2,-20(fp)
+ 802c4e0:	10800060 	cmpeqi	r2,r2,1
+ 802c4e4:	10000e1e 	bne	r2,zero,802c520 <t_setsockopt+0xd4>
+   {
+      if ((err = sosetopt (so, name, arg)) != 0) 
+ 802c4e8:	e1bff917 	ldw	r6,-28(fp)
+ 802c4ec:	e17ffa17 	ldw	r5,-24(fp)
+ 802c4f0:	e13ffe17 	ldw	r4,-8(fp)
+ 802c4f4:	802e7800 	call	802e780 <sosetopt>
+ 802c4f8:	e0bffd15 	stw	r2,-12(fp)
+ 802c4fc:	e0bffd17 	ldw	r2,-12(fp)
+ 802c500:	10003a26 	beq	r2,zero,802c5ec <t_setsockopt+0x1a0>
+      {
+         so->so_error = err;
+ 802c504:	e0bffe17 	ldw	r2,-8(fp)
+ 802c508:	e0fffd17 	ldw	r3,-12(fp)
+ 802c50c:	10c00615 	stw	r3,24(r2)
+         UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c510:	0009883a 	mov	r4,zero
+ 802c514:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return SOCKET_ERROR;
+ 802c518:	00bfffc4 	movi	r2,-1
+ 802c51c:	00003606 	br	802c5f8 <t_setsockopt+0x1ac>
+   {
+   /* level 1 options are for the IP packet level.
+    * the info is carried in the socket CB, then put 
+    * into the PACKET.
+    */
+      if (!so->so_optsPack)
+ 802c520:	e0bffe17 	ldw	r2,-8(fp)
+ 802c524:	10801f17 	ldw	r2,124(r2)
+ 802c528:	10000f1e 	bne	r2,zero,802c568 <t_setsockopt+0x11c>
+      {
+         so->so_optsPack = (struct ip_socopts *) SOCOPT_ALLOC (sizeof(struct ip_socopts *));
+ 802c52c:	01000104 	movi	r4,4
+ 802c530:	802982c0 	call	802982c <npalloc>
+ 802c534:	1007883a 	mov	r3,r2
+ 802c538:	e0bffe17 	ldw	r2,-8(fp)
+ 802c53c:	10c01f15 	stw	r3,124(r2)
+         if (!so->so_optsPack) 
+ 802c540:	e0bffe17 	ldw	r2,-8(fp)
+ 802c544:	10801f17 	ldw	r2,124(r2)
+ 802c548:	1000071e 	bne	r2,zero,802c568 <t_setsockopt+0x11c>
+         {
+            so->so_error = ENOMEM;
+ 802c54c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c550:	00c00304 	movi	r3,12
+ 802c554:	10c00615 	stw	r3,24(r2)
+            UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c558:	0009883a 	mov	r4,zero
+ 802c55c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            return SOCKET_ERROR;
+ 802c560:	00bfffc4 	movi	r2,-1
+ 802c564:	00002406 	br	802c5f8 <t_setsockopt+0x1ac>
+         }
+      }
+      
+      if (name == IP_TTL_OPT)
+ 802c568:	e0bffa17 	ldw	r2,-24(fp)
+ 802c56c:	10800118 	cmpnei	r2,r2,4
+ 802c570:	1000061e 	bne	r2,zero,802c58c <t_setsockopt+0x140>
+         so->so_optsPack->ip_ttl = (u_char)(*(int *)arg);
+ 802c574:	e0bff917 	ldw	r2,-28(fp)
+ 802c578:	10c00017 	ldw	r3,0(r2)
+ 802c57c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c580:	10801f17 	ldw	r2,124(r2)
+ 802c584:	10c00045 	stb	r3,1(r2)
+ 802c588:	00001806 	br	802c5ec <t_setsockopt+0x1a0>
+      else
+      if (name == IP_TOS)
+ 802c58c:	e0bffa17 	ldw	r2,-24(fp)
+ 802c590:	108000d8 	cmpnei	r2,r2,3
+ 802c594:	1000061e 	bne	r2,zero,802c5b0 <t_setsockopt+0x164>
+         so->so_optsPack->ip_tos = (u_char)(*(int *)arg);
+ 802c598:	e0bff917 	ldw	r2,-28(fp)
+ 802c59c:	10c00017 	ldw	r3,0(r2)
+ 802c5a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802c5a4:	10801f17 	ldw	r2,124(r2)
+ 802c5a8:	10c00005 	stb	r3,0(r2)
+ 802c5ac:	00000f06 	br	802c5ec <t_setsockopt+0x1a0>
+	   else
+	   if (name == IP_SCOPEID)
+ 802c5b0:	e0bffa17 	ldw	r2,-24(fp)
+ 802c5b4:	10800398 	cmpnei	r2,r2,14
+ 802c5b8:	1000081e 	bne	r2,zero,802c5dc <t_setsockopt+0x190>
+            so->so_optsPack->ip_scopeid = (u_char)(*(u_int *)arg);
+ 802c5bc:	e0bff917 	ldw	r2,-28(fp)
+ 802c5c0:	10800017 	ldw	r2,0(r2)
+ 802c5c4:	1007883a 	mov	r3,r2
+ 802c5c8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c5cc:	10801f17 	ldw	r2,124(r2)
+ 802c5d0:	18c03fcc 	andi	r3,r3,255
+ 802c5d4:	10c00115 	stw	r3,4(r2)
+ 802c5d8:	00000406 	br	802c5ec <t_setsockopt+0x1a0>
+      else
+      {
+         UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c5dc:	0009883a 	mov	r4,zero
+ 802c5e0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return SOCKET_ERROR;
+ 802c5e4:	00bfffc4 	movi	r2,-1
+ 802c5e8:	00000306 	br	802c5f8 <t_setsockopt+0x1ac>
+      }   
+   }
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c5ec:	0009883a 	mov	r4,zero
+ 802c5f0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return 0;
+ 802c5f4:	0005883a 	mov	r2,zero
+}
+ 802c5f8:	e037883a 	mov	sp,fp
+ 802c5fc:	dfc00117 	ldw	ra,4(sp)
+ 802c600:	df000017 	ldw	fp,0(sp)
+ 802c604:	dec00204 	addi	sp,sp,8
+ 802c608:	f800283a 	ret
+
+0802c60c <t_getsockopt>:
+   int   level,
+   int   name,
+   void *   arg,
+   int   arglen)
+
+{
+ 802c60c:	defff704 	addi	sp,sp,-36
+ 802c610:	dfc00815 	stw	ra,32(sp)
+ 802c614:	df000715 	stw	fp,28(sp)
+ 802c618:	df000704 	addi	fp,sp,28
+ 802c61c:	e13ffc15 	stw	r4,-16(fp)
+ 802c620:	e17ffb15 	stw	r5,-20(fp)
+ 802c624:	e1bffa15 	stw	r6,-24(fp)
+ 802c628:	e1fff915 	stw	r7,-28(fp)
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+ 802c62c:	e0bffc17 	ldw	r2,-16(fp)
+ 802c630:	10bffc04 	addi	r2,r2,-16
+ 802c634:	100490ba 	slli	r2,r2,2
+ 802c638:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802c63c:	008201b4 	movhi	r2,2054
+ 802c640:	10b87104 	addi	r2,r2,-7740
+ 802c644:	e0bfff15 	stw	r2,-4(fp)
+ 802c648:	00000606 	br	802c664 <t_getsockopt+0x58>
+ 802c64c:	e0ffff17 	ldw	r3,-4(fp)
+ 802c650:	e0bffe17 	ldw	r2,-8(fp)
+ 802c654:	18800626 	beq	r3,r2,802c670 <t_getsockopt+0x64>
+ 802c658:	e0bfff17 	ldw	r2,-4(fp)
+ 802c65c:	10800017 	ldw	r2,0(r2)
+ 802c660:	e0bfff15 	stw	r2,-4(fp)
+ 802c664:	e0bfff17 	ldw	r2,-4(fp)
+ 802c668:	103ff81e 	bne	r2,zero,802c64c <t_getsockopt+0x40>
+ 802c66c:	00000106 	br	802c674 <t_getsockopt+0x68>
+ 802c670:	0001883a 	nop
+ 802c674:	e0ffff17 	ldw	r3,-4(fp)
+ 802c678:	e0bffe17 	ldw	r2,-8(fp)
+ 802c67c:	18800326 	beq	r3,r2,802c68c <t_getsockopt+0x80>
+ 802c680:	8028cd40 	call	8028cd4 <dtrap>
+ 802c684:	00bfffc4 	movi	r2,-1
+ 802c688:	00003d06 	br	802c780 <t_getsockopt+0x174>
+   USE_ARG(level);
+   USE_ARG(arglen);
+
+   LOCK_NET_RESOURCE (NET_RESID);
+ 802c68c:	0009883a 	mov	r4,zero
+ 802c690:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   INET_TRACE (INETM_SOCKET,
+    ("INET: getsockopt: name %x val %x valsize %d\n",
+    name, val));
+
+   /* is it a level IP_OPTIONS call? */
+   if (level != IP_OPTIONS)
+ 802c694:	e0bffb17 	ldw	r2,-20(fp)
+ 802c698:	10800060 	cmpeqi	r2,r2,1
+ 802c69c:	10000e1e 	bne	r2,zero,802c6d8 <t_getsockopt+0xcc>
+   {
+      if ((err = sogetopt (so, name, arg)) != 0) 
+ 802c6a0:	e1bff917 	ldw	r6,-28(fp)
+ 802c6a4:	e17ffa17 	ldw	r5,-24(fp)
+ 802c6a8:	e13ffe17 	ldw	r4,-8(fp)
+ 802c6ac:	802ec0c0 	call	802ec0c <sogetopt>
+ 802c6b0:	e0bffd15 	stw	r2,-12(fp)
+ 802c6b4:	e0bffd17 	ldw	r2,-12(fp)
+ 802c6b8:	10002c26 	beq	r2,zero,802c76c <t_getsockopt+0x160>
+      {
+         so->so_error = err;
+ 802c6bc:	e0bffe17 	ldw	r2,-8(fp)
+ 802c6c0:	e0fffd17 	ldw	r3,-12(fp)
+ 802c6c4:	10c00615 	stw	r3,24(r2)
+         UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c6c8:	0009883a 	mov	r4,zero
+ 802c6cc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return SOCKET_ERROR;
+ 802c6d0:	00bfffc4 	movi	r2,-1
+ 802c6d4:	00002a06 	br	802c780 <t_getsockopt+0x174>
+   {
+      /* level 1 options are for the IP packet level.
+       * the info is carried in the socket CB, then put 
+       * into the PACKET.
+       */
+      if (name == IP_TTL_OPT)
+ 802c6d8:	e0bffa17 	ldw	r2,-24(fp)
+ 802c6dc:	10800118 	cmpnei	r2,r2,4
+ 802c6e0:	10000e1e 	bne	r2,zero,802c71c <t_getsockopt+0x110>
+      {
+         if (!so->so_optsPack) *(int *)arg = IP_TTL;
+ 802c6e4:	e0bffe17 	ldw	r2,-8(fp)
+ 802c6e8:	10801f17 	ldw	r2,124(r2)
+ 802c6ec:	1000041e 	bne	r2,zero,802c700 <t_getsockopt+0xf4>
+ 802c6f0:	e0bff917 	ldw	r2,-28(fp)
+ 802c6f4:	00c01004 	movi	r3,64
+ 802c6f8:	10c00015 	stw	r3,0(r2)
+ 802c6fc:	00001b06 	br	802c76c <t_getsockopt+0x160>
+         else *(int *)arg = (int)so->so_optsPack->ip_ttl;
+ 802c700:	e0bffe17 	ldw	r2,-8(fp)
+ 802c704:	10801f17 	ldw	r2,124(r2)
+ 802c708:	10800043 	ldbu	r2,1(r2)
+ 802c70c:	10c03fcc 	andi	r3,r2,255
+ 802c710:	e0bff917 	ldw	r2,-28(fp)
+ 802c714:	10c00015 	stw	r3,0(r2)
+ 802c718:	00001406 	br	802c76c <t_getsockopt+0x160>
+      }
+      else if (name == IP_TOS)
+ 802c71c:	e0bffa17 	ldw	r2,-24(fp)
+ 802c720:	108000d8 	cmpnei	r2,r2,3
+ 802c724:	10000d1e 	bne	r2,zero,802c75c <t_getsockopt+0x150>
+      {
+         if (!so->so_optsPack) *(int *)arg = IP_TOS_DEFVAL;
+ 802c728:	e0bffe17 	ldw	r2,-8(fp)
+ 802c72c:	10801f17 	ldw	r2,124(r2)
+ 802c730:	1000031e 	bne	r2,zero,802c740 <t_getsockopt+0x134>
+ 802c734:	e0bff917 	ldw	r2,-28(fp)
+ 802c738:	10000015 	stw	zero,0(r2)
+ 802c73c:	00000b06 	br	802c76c <t_getsockopt+0x160>
+         else *(int *)arg = (int)so->so_optsPack->ip_tos;
+ 802c740:	e0bffe17 	ldw	r2,-8(fp)
+ 802c744:	10801f17 	ldw	r2,124(r2)
+ 802c748:	10800003 	ldbu	r2,0(r2)
+ 802c74c:	10c03fcc 	andi	r3,r2,255
+ 802c750:	e0bff917 	ldw	r2,-28(fp)
+ 802c754:	10c00015 	stw	r3,0(r2)
+ 802c758:	00000406 	br	802c76c <t_getsockopt+0x160>
+      }
+      else
+      {
+         UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c75c:	0009883a 	mov	r4,zero
+ 802c760:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return SOCKET_ERROR;
+ 802c764:	00bfffc4 	movi	r2,-1
+ 802c768:	00000506 	br	802c780 <t_getsockopt+0x174>
+      }
+   }   
+   so->so_error = 0;
+ 802c76c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c770:	10000615 	stw	zero,24(r2)
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+ 802c774:	0009883a 	mov	r4,zero
+ 802c778:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return 0;
+ 802c77c:	0005883a 	mov	r2,zero
+}
+ 802c780:	e037883a 	mov	sp,fp
+ 802c784:	dfc00117 	ldw	ra,4(sp)
+ 802c788:	df000017 	ldw	fp,0(sp)
+ 802c78c:	dec00204 	addi	sp,sp,8
+ 802c790:	f800283a 	ret
+
+0802c794 <t_recv>:
+int
+t_recv (long s, 
+   char *   buf,
+   int   len, 
+   int   flag)
+{
+ 802c794:	defff604 	addi	sp,sp,-40
+ 802c798:	dfc00915 	stw	ra,36(sp)
+ 802c79c:	df000815 	stw	fp,32(sp)
+ 802c7a0:	df000804 	addi	fp,sp,32
+ 802c7a4:	e13ffc15 	stw	r4,-16(fp)
+ 802c7a8:	e17ffb15 	stw	r5,-20(fp)
+ 802c7ac:	e1bffa15 	stw	r6,-24(fp)
+ 802c7b0:	e1fff915 	stw	r7,-28(fp)
+#ifdef SOCKDEBUG
+   char logbuf[10];
+#endif
+   struct socket *   so;
+   int   err;
+   int   sendlen = len;
+ 802c7b4:	e0bffa17 	ldw	r2,-24(fp)
+ 802c7b8:	e0bfff15 	stw	r2,-4(fp)
+
+   so = LONG2SO(s);
+ 802c7bc:	e0bffc17 	ldw	r2,-16(fp)
+ 802c7c0:	10bffc04 	addi	r2,r2,-16
+ 802c7c4:	100490ba 	slli	r2,r2,2
+ 802c7c8:	e0bffe15 	stw	r2,-8(fp)
+#ifdef SOC_CHECK_ALWAYS
+   SOC_CHECK(so);
+#endif
+   if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+ 802c7cc:	e0bffe17 	ldw	r2,-8(fp)
+ 802c7d0:	1080088b 	ldhu	r2,34(r2)
+ 802c7d4:	10bfffcc 	andi	r2,r2,65535
+ 802c7d8:	1080038c 	andi	r2,r2,14
+ 802c7dc:	108000a0 	cmpeqi	r2,r2,2
+ 802c7e0:	1000051e 	bne	r2,zero,802c7f8 <t_recv+0x64>
+   {
+      so->so_error = EPIPE;
+ 802c7e4:	e0bffe17 	ldw	r2,-8(fp)
+ 802c7e8:	00c00804 	movi	r3,32
+ 802c7ec:	10c00615 	stw	r3,24(r2)
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_recv: %d", so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+ 802c7f0:	00bfffc4 	movi	r2,-1
+ 802c7f4:	00001906 	br	802c85c <t_recv+0xc8>
+   }
+   so->so_error = 0;
+ 802c7f8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c7fc:	10000615 	stw	zero,24(r2)
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802c800:	0009883a 	mov	r4,zero
+ 802c804:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   IN_PROFILER(PF_TCP, PF_ENTRY);        /* measure time in TCP */
+   INET_TRACE (INETM_IO, ("INET:recv: so %x, len %d\n", so, len));
+   err = soreceive(so, NULL, buf, &len, flag);
+ 802c808:	e0fffa04 	addi	r3,fp,-24
+ 802c80c:	e0bff917 	ldw	r2,-28(fp)
+ 802c810:	d8800015 	stw	r2,0(sp)
+ 802c814:	180f883a 	mov	r7,r3
+ 802c818:	e1bffb17 	ldw	r6,-20(fp)
+ 802c81c:	000b883a 	mov	r5,zero
+ 802c820:	e13ffe17 	ldw	r4,-8(fp)
+ 802c824:	802de940 	call	802de94 <soreceive>
+ 802c828:	e0bffd15 	stw	r2,-12(fp)
+   IN_PROFILER(PF_TCP, PF_EXIT);        /* measure time in TCP */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c82c:	0009883a 	mov	r4,zero
+ 802c830:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if(err)
+ 802c834:	e0bffd17 	ldw	r2,-12(fp)
+ 802c838:	10000526 	beq	r2,zero,802c850 <t_recv+0xbc>
+   {
+      so->so_error = err;
+ 802c83c:	e0bffe17 	ldw	r2,-8(fp)
+ 802c840:	e0fffd17 	ldw	r3,-12(fp)
+ 802c844:	10c00615 	stw	r3,24(r2)
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_recv: %d", so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+ 802c848:	00bfffc4 	movi	r2,-1
+ 802c84c:	00000306 	br	802c85c <t_recv+0xc8>
+   }
+
+   /* return bytes we sent - the amount we wanted to send minus
+    * the amount left in the buffer.
+    */
+   return (sendlen - len);
+ 802c850:	e0bffa17 	ldw	r2,-24(fp)
+ 802c854:	e0ffff17 	ldw	r3,-4(fp)
+ 802c858:	1885c83a 	sub	r2,r3,r2
+}
+ 802c85c:	e037883a 	mov	sp,fp
+ 802c860:	dfc00117 	ldw	ra,4(sp)
+ 802c864:	df000017 	ldw	fp,0(sp)
+ 802c868:	dec00204 	addi	sp,sp,8
+ 802c86c:	f800283a 	ret
+
+0802c870 <t_recvfrom>:
+   char *   buf,
+   int   len, 
+   int   flags,
+   struct sockaddr * from,
+   int * fromlen)
+{
+ 802c870:	defff404 	addi	sp,sp,-48
+ 802c874:	dfc00b15 	stw	ra,44(sp)
+ 802c878:	df000a15 	stw	fp,40(sp)
+ 802c87c:	df000a04 	addi	fp,sp,40
+ 802c880:	e13ffa15 	stw	r4,-24(fp)
+ 802c884:	e17ff915 	stw	r5,-28(fp)
+ 802c888:	e1bff815 	stw	r6,-32(fp)
+ 802c88c:	e1fff715 	stw	r7,-36(fp)
+   struct socket *   so;
+   struct mbuf *     sender = NULL;
+ 802c890:	e03ffb15 	stw	zero,-20(fp)
+   int   err;
+   int   sendlen = len;
+ 802c894:	e0bff817 	ldw	r2,-32(fp)
+ 802c898:	e0bffe15 	stw	r2,-8(fp)
+
+   so = LONG2SO(s);
+ 802c89c:	e0bffa17 	ldw	r2,-24(fp)
+ 802c8a0:	10bffc04 	addi	r2,r2,-16
+ 802c8a4:	100490ba 	slli	r2,r2,2
+ 802c8a8:	e0bffd15 	stw	r2,-12(fp)
+   SOC_CHECK(so);
+ 802c8ac:	008201b4 	movhi	r2,2054
+ 802c8b0:	10b87104 	addi	r2,r2,-7740
+ 802c8b4:	e0bfff15 	stw	r2,-4(fp)
+ 802c8b8:	00000606 	br	802c8d4 <t_recvfrom+0x64>
+ 802c8bc:	e0ffff17 	ldw	r3,-4(fp)
+ 802c8c0:	e0bffd17 	ldw	r2,-12(fp)
+ 802c8c4:	18800626 	beq	r3,r2,802c8e0 <t_recvfrom+0x70>
+ 802c8c8:	e0bfff17 	ldw	r2,-4(fp)
+ 802c8cc:	10800017 	ldw	r2,0(r2)
+ 802c8d0:	e0bfff15 	stw	r2,-4(fp)
+ 802c8d4:	e0bfff17 	ldw	r2,-4(fp)
+ 802c8d8:	103ff81e 	bne	r2,zero,802c8bc <t_recvfrom+0x4c>
+ 802c8dc:	00000106 	br	802c8e4 <t_recvfrom+0x74>
+ 802c8e0:	0001883a 	nop
+ 802c8e4:	e0ffff17 	ldw	r3,-4(fp)
+ 802c8e8:	e0bffd17 	ldw	r2,-12(fp)
+ 802c8ec:	18800326 	beq	r3,r2,802c8fc <t_recvfrom+0x8c>
+ 802c8f0:	8028cd40 	call	8028cd4 <dtrap>
+ 802c8f4:	00bfffc4 	movi	r2,-1
+ 802c8f8:	00002706 	br	802c998 <t_recvfrom+0x128>
+   so->so_error = 0;
+ 802c8fc:	e0bffd17 	ldw	r2,-12(fp)
+ 802c900:	10000615 	stw	zero,24(r2)
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802c904:	0009883a 	mov	r4,zero
+ 802c908:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   err = soreceive(so, &sender, buf, &len, flags);
+ 802c90c:	e13ff804 	addi	r4,fp,-32
+ 802c910:	e0fffb04 	addi	r3,fp,-20
+ 802c914:	e0bff717 	ldw	r2,-36(fp)
+ 802c918:	d8800015 	stw	r2,0(sp)
+ 802c91c:	200f883a 	mov	r7,r4
+ 802c920:	e1bff917 	ldw	r6,-28(fp)
+ 802c924:	180b883a 	mov	r5,r3
+ 802c928:	e13ffd17 	ldw	r4,-12(fp)
+ 802c92c:	802de940 	call	802de94 <soreceive>
+ 802c930:	e0bffc15 	stw	r2,-16(fp)
+
+   /* copy sender info from mbuf to sockaddr */
+   if (sender)
+ 802c934:	e0bffb17 	ldw	r2,-20(fp)
+ 802c938:	10000b26 	beq	r2,zero,802c968 <t_recvfrom+0xf8>
+   {
+      MEMCPY(from, (mtod(sender, struct sockaddr *)), *fromlen );
+ 802c93c:	e0bffb17 	ldw	r2,-20(fp)
+ 802c940:	10c00317 	ldw	r3,12(r2)
+ 802c944:	e0800317 	ldw	r2,12(fp)
+ 802c948:	10800017 	ldw	r2,0(r2)
+ 802c94c:	100d883a 	mov	r6,r2
+ 802c950:	180b883a 	mov	r5,r3
+ 802c954:	e1000217 	ldw	r4,8(fp)
+ 802c958:	80086b80 	call	80086b8 <memcpy>
+      m_freem (sender);
+ 802c95c:	e0bffb17 	ldw	r2,-20(fp)
+ 802c960:	1009883a 	mov	r4,r2
+ 802c964:	8029cfc0 	call	8029cfc <m_freem>
+   }
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802c968:	0009883a 	mov	r4,zero
+ 802c96c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if(err)
+ 802c970:	e0bffc17 	ldw	r2,-16(fp)
+ 802c974:	10000526 	beq	r2,zero,802c98c <t_recvfrom+0x11c>
+   {
+      so->so_error = err;
+ 802c978:	e0bffd17 	ldw	r2,-12(fp)
+ 802c97c:	e0fffc17 	ldw	r3,-16(fp)
+ 802c980:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802c984:	00bfffc4 	movi	r2,-1
+ 802c988:	00000306 	br	802c998 <t_recvfrom+0x128>
+   }
+
+   /* OK return: amount of data actually sent */
+   return (sendlen - len);
+ 802c98c:	e0bff817 	ldw	r2,-32(fp)
+ 802c990:	e0fffe17 	ldw	r3,-8(fp)
+ 802c994:	1885c83a 	sub	r2,r3,r2
+}
+ 802c998:	e037883a 	mov	sp,fp
+ 802c99c:	dfc00117 	ldw	ra,4(sp)
+ 802c9a0:	df000017 	ldw	fp,0(sp)
+ 802c9a4:	dec00204 	addi	sp,sp,8
+ 802c9a8:	f800283a 	ret
+
+0802c9ac <t_sendto>:
+   char *   buf,
+   int   len, 
+   int   flags,
+   struct sockaddr * to,
+   int   tolen)
+{
+ 802c9ac:	defff404 	addi	sp,sp,-48
+ 802c9b0:	dfc00b15 	stw	ra,44(sp)
+ 802c9b4:	df000a15 	stw	fp,40(sp)
+ 802c9b8:	df000a04 	addi	fp,sp,40
+ 802c9bc:	e13ffa15 	stw	r4,-24(fp)
+ 802c9c0:	e17ff915 	stw	r5,-28(fp)
+ 802c9c4:	e1bff815 	stw	r6,-32(fp)
+ 802c9c8:	e1fff715 	stw	r7,-36(fp)
+   struct socket *   so;
+   int   sendlen;
+   int   err;
+   struct mbuf *     name;
+
+   so = LONG2SO(s);
+ 802c9cc:	e0bffa17 	ldw	r2,-24(fp)
+ 802c9d0:	10bffc04 	addi	r2,r2,-16
+ 802c9d4:	100490ba 	slli	r2,r2,2
+ 802c9d8:	e0bffd15 	stw	r2,-12(fp)
+   SOC_CHECK(so);
+ 802c9dc:	008201b4 	movhi	r2,2054
+ 802c9e0:	10b87104 	addi	r2,r2,-7740
+ 802c9e4:	e0bffe15 	stw	r2,-8(fp)
+ 802c9e8:	00000606 	br	802ca04 <t_sendto+0x58>
+ 802c9ec:	e0fffe17 	ldw	r3,-8(fp)
+ 802c9f0:	e0bffd17 	ldw	r2,-12(fp)
+ 802c9f4:	18800626 	beq	r3,r2,802ca10 <t_sendto+0x64>
+ 802c9f8:	e0bffe17 	ldw	r2,-8(fp)
+ 802c9fc:	10800017 	ldw	r2,0(r2)
+ 802ca00:	e0bffe15 	stw	r2,-8(fp)
+ 802ca04:	e0bffe17 	ldw	r2,-8(fp)
+ 802ca08:	103ff81e 	bne	r2,zero,802c9ec <t_sendto+0x40>
+ 802ca0c:	00000106 	br	802ca14 <t_sendto+0x68>
+ 802ca10:	0001883a 	nop
+ 802ca14:	e0fffe17 	ldw	r3,-8(fp)
+ 802ca18:	e0bffd17 	ldw	r2,-12(fp)
+ 802ca1c:	18800326 	beq	r3,r2,802ca2c <t_sendto+0x80>
+ 802ca20:	8028cd40 	call	8028cd4 <dtrap>
+ 802ca24:	00bfffc4 	movi	r2,-1
+ 802ca28:	00005706 	br	802cb88 <t_sendto+0x1dc>
+   so->so_error = 0;
+ 802ca2c:	e0bffd17 	ldw	r2,-12(fp)
+ 802ca30:	10000615 	stw	zero,24(r2)
+
+   switch (so->so_type)
+ 802ca34:	e0bffd17 	ldw	r2,-12(fp)
+ 802ca38:	10800983 	ldbu	r2,38(r2)
+ 802ca3c:	10803fcc 	andi	r2,r2,255
+ 802ca40:	1080201c 	xori	r2,r2,128
+ 802ca44:	10bfe004 	addi	r2,r2,-128
+ 802ca48:	10c000a0 	cmpeqi	r3,r2,2
+ 802ca4c:	18000a1e 	bne	r3,zero,802ca78 <t_sendto+0xcc>
+ 802ca50:	10c000e0 	cmpeqi	r3,r2,3
+ 802ca54:	18000b1e 	bne	r3,zero,802ca84 <t_sendto+0xd8>
+ 802ca58:	10800058 	cmpnei	r2,r2,1
+ 802ca5c:	1000101e 	bne	r2,zero,802caa0 <t_sendto+0xf4>
+   {
+   case SOCK_STREAM:
+      /* this is a stream socket, so pass this request through
+       * t_send() for its large-send support.
+       */
+      return t_send(s, buf, len, flags);
+ 802ca60:	e1fff717 	ldw	r7,-36(fp)
+ 802ca64:	e1bff817 	ldw	r6,-32(fp)
+ 802ca68:	e17ff917 	ldw	r5,-28(fp)
+ 802ca6c:	e13ffa17 	ldw	r4,-24(fp)
+ 802ca70:	802cb9c0 	call	802cb9c <t_send>
+ 802ca74:	00004406 	br	802cb88 <t_sendto+0x1dc>
+      /*NOTREACHED*/
+   case SOCK_DGRAM:
+      /* datagram (UDP) socket -- prepare to check length */
+      sendlen = udp_maxalloc();
+ 802ca78:	803dd940 	call	803dd94 <udp_maxalloc>
+ 802ca7c:	e0bffb15 	stw	r2,-20(fp)
+      break;
+ 802ca80:	00000d06 	br	802cab8 <t_sendto+0x10c>
+#ifdef IP_RAW
+   case SOCK_RAW:
+      /* raw socket -- prepare to check length */
+      sendlen = ip_raw_maxalloc(so->so_options & SO_HDRINCL);
+ 802ca84:	e0bffd17 	ldw	r2,-12(fp)
+ 802ca88:	10800417 	ldw	r2,16(r2)
+ 802ca8c:	1088000c 	andi	r2,r2,8192
+ 802ca90:	1009883a 	mov	r4,r2
+ 802ca94:	803cae00 	call	803cae0 <ip_raw_maxalloc>
+ 802ca98:	e0bffb15 	stw	r2,-20(fp)
+      break;
+ 802ca9c:	00000606 	br	802cab8 <t_sendto+0x10c>
+#endif /* IP_RAW */
+   default:
+      /* socket has unknown type */
+      dtrap();
+ 802caa0:	8028cd40 	call	8028cd4 <dtrap>
+      so->so_error = EFAULT;
+ 802caa4:	e0bffd17 	ldw	r2,-12(fp)
+ 802caa8:	00c00384 	movi	r3,14
+ 802caac:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802cab0:	00bfffc4 	movi	r2,-1
+ 802cab4:	00003406 	br	802cb88 <t_sendto+0x1dc>
+   /* fall through for non-stream sockets: SOCK_DGRAM (UDP) and
+    * SOCK_RAW (raw IP)
+    */
+
+   /* check length against underlying stack's maximum */
+   if (len > sendlen)
+ 802cab8:	e0fffb17 	ldw	r3,-20(fp)
+ 802cabc:	e0bff817 	ldw	r2,-32(fp)
+ 802cac0:	1880050e 	bge	r3,r2,802cad8 <t_sendto+0x12c>
+   {
+      so->so_error = EMSGSIZE;
+ 802cac4:	e0bffd17 	ldw	r2,-12(fp)
+ 802cac8:	00c01e84 	movi	r3,122
+ 802cacc:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802cad0:	00bfffc4 	movi	r2,-1
+ 802cad4:	00002c06 	br	802cb88 <t_sendto+0x1dc>
+   /* if a sockaddr was passed, wrap it in an mbuf and pas it into the
+    * bowels of the BSD code; else assume this is a bound UDP socket
+    * and this call came from t_send() below.
+    */
+
+   if (to)  /* sockaddr was passed */
+ 802cad8:	e0800217 	ldw	r2,8(fp)
+ 802cadc:	10000c26 	beq	r2,zero,802cb10 <t_sendto+0x164>
+   {
+      name = sockargs(to, tolen, MT_SONAME);
+ 802cae0:	01800244 	movi	r6,9
+ 802cae4:	e1400317 	ldw	r5,12(fp)
+ 802cae8:	e1000217 	ldw	r4,8(fp)
+ 802caec:	802cf300 	call	802cf30 <sockargs>
+ 802caf0:	e0bfff15 	stw	r2,-4(fp)
+      if(name == NULL)
+ 802caf4:	e0bfff17 	ldw	r2,-4(fp)
+ 802caf8:	1000061e 	bne	r2,zero,802cb14 <t_sendto+0x168>
+      {
+         so->so_error = ENOMEM;
+ 802cafc:	e0bffd17 	ldw	r2,-12(fp)
+ 802cb00:	00c00304 	movi	r3,12
+ 802cb04:	10c00615 	stw	r3,24(r2)
+         return SOCKET_ERROR;
+ 802cb08:	00bfffc4 	movi	r2,-1
+ 802cb0c:	00001e06 	br	802cb88 <t_sendto+0x1dc>
+      }
+   }
+   else     /* hope user called bind() first... */
+      name = NULL;
+ 802cb10:	e03fff15 	stw	zero,-4(fp)
+   
+   sendlen = len;
+ 802cb14:	e0bff817 	ldw	r2,-32(fp)
+ 802cb18:	e0bffb15 	stw	r2,-20(fp)
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802cb1c:	0009883a 	mov	r4,zero
+ 802cb20:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   err = sosend (so, name, buf, &sendlen, flags);
+ 802cb24:	e0fffb04 	addi	r3,fp,-20
+ 802cb28:	e0bff717 	ldw	r2,-36(fp)
+ 802cb2c:	d8800015 	stw	r2,0(sp)
+ 802cb30:	180f883a 	mov	r7,r3
+ 802cb34:	e1bff917 	ldw	r6,-28(fp)
+ 802cb38:	e17fff17 	ldw	r5,-4(fp)
+ 802cb3c:	e13ffd17 	ldw	r4,-12(fp)
+ 802cb40:	802d9340 	call	802d934 <sosend>
+ 802cb44:	e0bffc15 	stw	r2,-16(fp)
+
+   if (name)
+ 802cb48:	e0bfff17 	ldw	r2,-4(fp)
+ 802cb4c:	10000226 	beq	r2,zero,802cb58 <t_sendto+0x1ac>
+      m_freem(name);
+ 802cb50:	e13fff17 	ldw	r4,-4(fp)
+ 802cb54:	8029cfc0 	call	8029cfc <m_freem>
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802cb58:	0009883a 	mov	r4,zero
+ 802cb5c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (err != 0)
+ 802cb60:	e0bffc17 	ldw	r2,-16(fp)
+ 802cb64:	10000526 	beq	r2,zero,802cb7c <t_sendto+0x1d0>
+   {
+      so->so_error = err;
+ 802cb68:	e0bffd17 	ldw	r2,-12(fp)
+ 802cb6c:	e0fffc17 	ldw	r3,-16(fp)
+ 802cb70:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802cb74:	00bfffc4 	movi	r2,-1
+ 802cb78:	00000306 	br	802cb88 <t_sendto+0x1dc>
+   }
+
+   return (len - sendlen);
+ 802cb7c:	e0bffb17 	ldw	r2,-20(fp)
+ 802cb80:	e0fff817 	ldw	r3,-32(fp)
+ 802cb84:	1885c83a 	sub	r2,r3,r2
+}
+ 802cb88:	e037883a 	mov	sp,fp
+ 802cb8c:	dfc00117 	ldw	ra,4(sp)
+ 802cb90:	df000017 	ldw	fp,0(sp)
+ 802cb94:	dec00204 	addi	sp,sp,8
+ 802cb98:	f800283a 	ret
+
+0802cb9c <t_send>:
+int
+t_send(long s, 
+   char *   buf,
+   int      len, 
+   int      flags)
+{
+ 802cb9c:	defff104 	addi	sp,sp,-60
+ 802cba0:	dfc00e15 	stw	ra,56(sp)
+ 802cba4:	df000d15 	stw	fp,52(sp)
+ 802cba8:	df000d04 	addi	fp,sp,52
+ 802cbac:	e13ff815 	stw	r4,-32(fp)
+ 802cbb0:	e17ff715 	stw	r5,-36(fp)
+ 802cbb4:	e1bff615 	stw	r6,-40(fp)
+ 802cbb8:	e1fff515 	stw	r7,-44(fp)
+   struct socket *   so;
+   int   e;       /* error holder */
+   int   total_sent  =  0;
+ 802cbbc:	e03fff15 	stw	zero,-4(fp)
+   int   maxpkt;
+   int   sendlen;
+   int   sent;
+
+   so = LONG2SO(s);
+ 802cbc0:	e0bff817 	ldw	r2,-32(fp)
+ 802cbc4:	10bffc04 	addi	r2,r2,-16
+ 802cbc8:	100490ba 	slli	r2,r2,2
+ 802cbcc:	e0bffd15 	stw	r2,-12(fp)
+#ifdef SOC_CHECK_ALWAYS
+   SOC_CHECK(so);
+#endif
+   if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+ 802cbd0:	e0bffd17 	ldw	r2,-12(fp)
+ 802cbd4:	1080088b 	ldhu	r2,34(r2)
+ 802cbd8:	10bfffcc 	andi	r2,r2,65535
+ 802cbdc:	1080038c 	andi	r2,r2,14
+ 802cbe0:	108000a0 	cmpeqi	r2,r2,2
+ 802cbe4:	1000051e 	bne	r2,zero,802cbfc <t_send+0x60>
+   {
+      so->so_error = EPIPE;
+ 802cbe8:	e0bffd17 	ldw	r2,-12(fp)
+ 802cbec:	00c00804 	movi	r3,32
+ 802cbf0:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802cbf4:	00bfffc4 	movi	r2,-1
+ 802cbf8:	00006306 	br	802cd88 <t_send+0x1ec>
+   }
+   so->so_error = 0;
+ 802cbfc:	e0bffd17 	ldw	r2,-12(fp)
+ 802cc00:	10000615 	stw	zero,24(r2)
+
+   /* If this is not a stream socket, assume it is bound and pass to
+    * t_sendto() with a null sockaddr
+    */
+   if (so->so_type != SOCK_STREAM)
+ 802cc04:	e0bffd17 	ldw	r2,-12(fp)
+ 802cc08:	10800983 	ldbu	r2,38(r2)
+ 802cc0c:	10803fcc 	andi	r2,r2,255
+ 802cc10:	1080201c 	xori	r2,r2,128
+ 802cc14:	10bfe004 	addi	r2,r2,-128
+ 802cc18:	10800060 	cmpeqi	r2,r2,1
+ 802cc1c:	1000081e 	bne	r2,zero,802cc40 <t_send+0xa4>
+      return(t_sendto(s, buf, len, flags, NULL, 0));
+ 802cc20:	d8000115 	stw	zero,4(sp)
+ 802cc24:	d8000015 	stw	zero,0(sp)
+ 802cc28:	e1fff517 	ldw	r7,-44(fp)
+ 802cc2c:	e1bff617 	ldw	r6,-40(fp)
+ 802cc30:	e17ff717 	ldw	r5,-36(fp)
+ 802cc34:	e13ff817 	ldw	r4,-32(fp)
+ 802cc38:	802c9ac0 	call	802c9ac <t_sendto>
+ 802cc3c:	00005206 	br	802cd88 <t_send+0x1ec>
+
+   maxpkt = TCP_MSS;
+ 802cc40:	00816d04 	movi	r2,1460
+ 802cc44:	e0bffe15 	stw	r2,-8(fp)
+   if(so->so_pcb)
+ 802cc48:	e0bffd17 	ldw	r2,-12(fp)
+ 802cc4c:	10800117 	ldw	r2,4(r2)
+ 802cc50:	10004826 	beq	r2,zero,802cd74 <t_send+0x1d8>
+   { 
+      struct tcpcb * tp;
+      tp = intotcpcb(so->so_pcb);   /* get tcp structure with mss */
+ 802cc54:	e0bffd17 	ldw	r2,-12(fp)
+ 802cc58:	10800117 	ldw	r2,4(r2)
+ 802cc5c:	10800917 	ldw	r2,36(r2)
+ 802cc60:	e0bffc15 	stw	r2,-16(fp)
+      if(tp->t_maxseg)              /* Make sure it's set */
+ 802cc64:	e0bffc17 	ldw	r2,-16(fp)
+ 802cc68:	10800a0b 	ldhu	r2,40(r2)
+ 802cc6c:	10bfffcc 	andi	r2,r2,65535
+ 802cc70:	10004026 	beq	r2,zero,802cd74 <t_send+0x1d8>
+         maxpkt = tp->t_maxseg;
+ 802cc74:	e0bffc17 	ldw	r2,-16(fp)
+ 802cc78:	10800a0b 	ldhu	r2,40(r2)
+ 802cc7c:	10bfffcc 	andi	r2,r2,65535
+ 802cc80:	e0bffe15 	stw	r2,-8(fp)
+   }
+
+   IN_PROFILER(PF_TCP, PF_ENTRY);       /* measure time in TCP */
+
+   while (len)
+ 802cc84:	00003b06 	br	802cd74 <t_send+0x1d8>
+   {
+      if (len > maxpkt)
+ 802cc88:	e0bff617 	ldw	r2,-40(fp)
+ 802cc8c:	e0fffe17 	ldw	r3,-8(fp)
+ 802cc90:	1880030e 	bge	r3,r2,802cca0 <t_send+0x104>
+         sendlen = maxpkt;  /* take biggest block we can */
+ 802cc94:	e0bffe17 	ldw	r2,-8(fp)
+ 802cc98:	e0bff915 	stw	r2,-28(fp)
+ 802cc9c:	00000206 	br	802cca8 <t_send+0x10c>
+      else
+         sendlen = len;
+ 802cca0:	e0bff617 	ldw	r2,-40(fp)
+ 802cca4:	e0bff915 	stw	r2,-28(fp)
+      sent = sendlen;
+ 802cca8:	e0bff917 	ldw	r2,-28(fp)
+ 802ccac:	e0bffb15 	stw	r2,-20(fp)
+
+      LOCK_NET_RESOURCE(NET_RESID);
+ 802ccb0:	0009883a 	mov	r4,zero
+ 802ccb4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      e = sosend (so, NULL, buf, &sendlen, flags);
+ 802ccb8:	e0fff904 	addi	r3,fp,-28
+ 802ccbc:	e0bff517 	ldw	r2,-44(fp)
+ 802ccc0:	d8800015 	stw	r2,0(sp)
+ 802ccc4:	180f883a 	mov	r7,r3
+ 802ccc8:	e1bff717 	ldw	r6,-36(fp)
+ 802cccc:	000b883a 	mov	r5,zero
+ 802ccd0:	e13ffd17 	ldw	r4,-12(fp)
+ 802ccd4:	802d9340 	call	802d934 <sosend>
+ 802ccd8:	e0bffa15 	stw	r2,-24(fp)
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 802ccdc:	0009883a 	mov	r4,zero
+ 802cce0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+ 
+      if (e != 0)  /* sock_sendit failed? */
+ 802cce4:	e0bffa17 	ldw	r2,-24(fp)
+ 802cce8:	10001026 	beq	r2,zero,802cd2c <t_send+0x190>
+      {
+         /* if we simply ran out of bufs, report back to caller. */
+         if ((e == ENOBUFS) || (e == EWOULDBLOCK))
+ 802ccec:	e0bffa17 	ldw	r2,-24(fp)
+ 802ccf0:	10801a60 	cmpeqi	r2,r2,105
+ 802ccf4:	1000031e 	bne	r2,zero,802cd04 <t_send+0x168>
+ 802ccf8:	e0bffa17 	ldw	r2,-24(fp)
+ 802ccfc:	108002d8 	cmpnei	r2,r2,11
+ 802cd00:	1000051e 	bne	r2,zero,802cd18 <t_send+0x17c>
+            /* if we actually sent something before running out
+             * of buffers, report what we sent; 
+             * else, report the error and let the application 
+             * retry the call later
+             */
+            if (total_sent != 0)
+ 802cd04:	e0bfff17 	ldw	r2,-4(fp)
+ 802cd08:	10000326 	beq	r2,zero,802cd18 <t_send+0x17c>
+            {
+               so->so_error = 0;
+ 802cd0c:	e0bffd17 	ldw	r2,-12(fp)
+ 802cd10:	10000615 	stw	zero,24(r2)
+               break;      /* break out of while(len) loop */
+ 802cd14:	00001b06 	br	802cd84 <t_send+0x1e8>
+            }
+         }
+         so->so_error = e;
+ 802cd18:	e0bffd17 	ldw	r2,-12(fp)
+ 802cd1c:	e0fffa17 	ldw	r3,-24(fp)
+ 802cd20:	10c00615 	stw	r3,24(r2)
+         return SOCKET_ERROR;
+ 802cd24:	00bfffc4 	movi	r2,-1
+ 802cd28:	00001706 	br	802cd88 <t_send+0x1ec>
+      }
+      /* if we can't send anymore, return now */
+      if (sendlen != 0)
+ 802cd2c:	e0bff917 	ldw	r2,-28(fp)
+ 802cd30:	1000131e 	bne	r2,zero,802cd80 <t_send+0x1e4>
+         break;         /* break out of while(len) loop */
+
+      /* adjust numbers & pointers, and go do next send loop */
+      sent -= sendlen;        /* subtract anything that didn't get sent */
+ 802cd34:	e0bff917 	ldw	r2,-28(fp)
+ 802cd38:	e0fffb17 	ldw	r3,-20(fp)
+ 802cd3c:	1885c83a 	sub	r2,r3,r2
+ 802cd40:	e0bffb15 	stw	r2,-20(fp)
+      buf += sent;
+ 802cd44:	e0bffb17 	ldw	r2,-20(fp)
+ 802cd48:	e0fff717 	ldw	r3,-36(fp)
+ 802cd4c:	1885883a 	add	r2,r3,r2
+ 802cd50:	e0bff715 	stw	r2,-36(fp)
+      len -= sent;
+ 802cd54:	e0fff617 	ldw	r3,-40(fp)
+ 802cd58:	e0bffb17 	ldw	r2,-20(fp)
+ 802cd5c:	1885c83a 	sub	r2,r3,r2
+ 802cd60:	e0bff615 	stw	r2,-40(fp)
+      total_sent += sent;
+ 802cd64:	e0ffff17 	ldw	r3,-4(fp)
+ 802cd68:	e0bffb17 	ldw	r2,-20(fp)
+ 802cd6c:	1885883a 	add	r2,r3,r2
+ 802cd70:	e0bfff15 	stw	r2,-4(fp)
+   while (len)
+ 802cd74:	e0bff617 	ldw	r2,-40(fp)
+ 802cd78:	103fc31e 	bne	r2,zero,802cc88 <t_send+0xec>
+ 802cd7c:	00000106 	br	802cd84 <t_send+0x1e8>
+         break;         /* break out of while(len) loop */
+ 802cd80:	0001883a 	nop
+   }
+
+   IN_PROFILER(PF_TCP, PF_EXIT);        /* measure time in TCP */
+   return total_sent;
+ 802cd84:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802cd88:	e037883a 	mov	sp,fp
+ 802cd8c:	dfc00117 	ldw	ra,4(sp)
+ 802cd90:	df000017 	ldw	fp,0(sp)
+ 802cd94:	dec00204 	addi	sp,sp,8
+ 802cd98:	f800283a 	ret
+
+0802cd9c <t_shutdown>:
+ * RETURNS: 
+ */
+
+int
+t_shutdown(long s, int   how)
+{
+ 802cd9c:	defff904 	addi	sp,sp,-28
+ 802cda0:	dfc00615 	stw	ra,24(sp)
+ 802cda4:	df000515 	stw	fp,20(sp)
+ 802cda8:	df000504 	addi	fp,sp,20
+ 802cdac:	e13ffc15 	stw	r4,-16(fp)
+ 802cdb0:	e17ffb15 	stw	r5,-20(fp)
+   struct socket *so;
+   int   err;
+
+   so = LONG2SO(s);
+ 802cdb4:	e0bffc17 	ldw	r2,-16(fp)
+ 802cdb8:	10bffc04 	addi	r2,r2,-16
+ 802cdbc:	100490ba 	slli	r2,r2,2
+ 802cdc0:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802cdc4:	008201b4 	movhi	r2,2054
+ 802cdc8:	10b87104 	addi	r2,r2,-7740
+ 802cdcc:	e0bfff15 	stw	r2,-4(fp)
+ 802cdd0:	00000606 	br	802cdec <t_shutdown+0x50>
+ 802cdd4:	e0ffff17 	ldw	r3,-4(fp)
+ 802cdd8:	e0bffe17 	ldw	r2,-8(fp)
+ 802cddc:	18800626 	beq	r3,r2,802cdf8 <t_shutdown+0x5c>
+ 802cde0:	e0bfff17 	ldw	r2,-4(fp)
+ 802cde4:	10800017 	ldw	r2,0(r2)
+ 802cde8:	e0bfff15 	stw	r2,-4(fp)
+ 802cdec:	e0bfff17 	ldw	r2,-4(fp)
+ 802cdf0:	103ff81e 	bne	r2,zero,802cdd4 <t_shutdown+0x38>
+ 802cdf4:	00000106 	br	802cdfc <t_shutdown+0x60>
+ 802cdf8:	0001883a 	nop
+ 802cdfc:	e0ffff17 	ldw	r3,-4(fp)
+ 802ce00:	e0bffe17 	ldw	r2,-8(fp)
+ 802ce04:	18800326 	beq	r3,r2,802ce14 <t_shutdown+0x78>
+ 802ce08:	8028cd40 	call	8028cd4 <dtrap>
+ 802ce0c:	00bfffc4 	movi	r2,-1
+ 802ce10:	00001206 	br	802ce5c <t_shutdown+0xc0>
+   so->so_error = 0;
+ 802ce14:	e0bffe17 	ldw	r2,-8(fp)
+ 802ce18:	10000615 	stw	zero,24(r2)
+   INET_TRACE (INETM_SOCKET, ("INET:shutdown so %x how %d\n", so, how));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802ce1c:	0009883a 	mov	r4,zero
+ 802ce20:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   err = soshutdown(so, how);
+ 802ce24:	e17ffb17 	ldw	r5,-20(fp)
+ 802ce28:	e13ffe17 	ldw	r4,-8(fp)
+ 802ce2c:	802e5ec0 	call	802e5ec <soshutdown>
+ 802ce30:	e0bffd15 	stw	r2,-12(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802ce34:	0009883a 	mov	r4,zero
+ 802ce38:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (err != 0)
+ 802ce3c:	e0bffd17 	ldw	r2,-12(fp)
+ 802ce40:	10000526 	beq	r2,zero,802ce58 <t_shutdown+0xbc>
+   {
+      so->so_error = err;
+ 802ce44:	e0bffe17 	ldw	r2,-8(fp)
+ 802ce48:	e0fffd17 	ldw	r3,-12(fp)
+ 802ce4c:	10c00615 	stw	r3,24(r2)
+      return SOCKET_ERROR;
+ 802ce50:	00bfffc4 	movi	r2,-1
+ 802ce54:	00000106 	br	802ce5c <t_shutdown+0xc0>
+   }
+   return 0;
+ 802ce58:	0005883a 	mov	r2,zero
+}
+ 802ce5c:	e037883a 	mov	sp,fp
+ 802ce60:	dfc00117 	ldw	ra,4(sp)
+ 802ce64:	df000017 	ldw	fp,0(sp)
+ 802ce68:	dec00204 	addi	sp,sp,8
+ 802ce6c:	f800283a 	ret
+
+0802ce70 <t_socketclose>:
+ * RETURNS: 
+ */
+
+int
+t_socketclose(long s)
+{
+ 802ce70:	defffa04 	addi	sp,sp,-24
+ 802ce74:	dfc00515 	stw	ra,20(sp)
+ 802ce78:	df000415 	stw	fp,16(sp)
+ 802ce7c:	df000404 	addi	fp,sp,16
+ 802ce80:	e13ffc15 	stw	r4,-16(fp)
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+ 802ce84:	e0bffc17 	ldw	r2,-16(fp)
+ 802ce88:	10bffc04 	addi	r2,r2,-16
+ 802ce8c:	100490ba 	slli	r2,r2,2
+ 802ce90:	e0bffe15 	stw	r2,-8(fp)
+   SOC_CHECK(so);
+ 802ce94:	008201b4 	movhi	r2,2054
+ 802ce98:	10b87104 	addi	r2,r2,-7740
+ 802ce9c:	e0bfff15 	stw	r2,-4(fp)
+ 802cea0:	00000606 	br	802cebc <t_socketclose+0x4c>
+ 802cea4:	e0ffff17 	ldw	r3,-4(fp)
+ 802cea8:	e0bffe17 	ldw	r2,-8(fp)
+ 802ceac:	18800626 	beq	r3,r2,802cec8 <t_socketclose+0x58>
+ 802ceb0:	e0bfff17 	ldw	r2,-4(fp)
+ 802ceb4:	10800017 	ldw	r2,0(r2)
+ 802ceb8:	e0bfff15 	stw	r2,-4(fp)
+ 802cebc:	e0bfff17 	ldw	r2,-4(fp)
+ 802cec0:	103ff81e 	bne	r2,zero,802cea4 <t_socketclose+0x34>
+ 802cec4:	00000106 	br	802cecc <t_socketclose+0x5c>
+ 802cec8:	0001883a 	nop
+ 802cecc:	e0ffff17 	ldw	r3,-4(fp)
+ 802ced0:	e0bffe17 	ldw	r2,-8(fp)
+ 802ced4:	18800326 	beq	r3,r2,802cee4 <t_socketclose+0x74>
+ 802ced8:	8028cd40 	call	8028cd4 <dtrap>
+ 802cedc:	00bfffc4 	movi	r2,-1
+ 802cee0:	00000e06 	br	802cf1c <t_socketclose+0xac>
+   so->so_error = 0;
+ 802cee4:	e0bffe17 	ldw	r2,-8(fp)
+ 802cee8:	10000615 	stw	zero,24(r2)
+   INET_TRACE ((INETM_CLOSE|INETM_SOCKET), ("INET:close, so %lx\n",so));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 802ceec:	0009883a 	mov	r4,zero
+ 802cef0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   err = soclose(so);
+ 802cef4:	e13ffe17 	ldw	r4,-8(fp)
+ 802cef8:	802d4340 	call	802d434 <soclose>
+ 802cefc:	e0bffd15 	stw	r2,-12(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802cf00:	0009883a 	mov	r4,zero
+ 802cf04:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (err != 0) 
+ 802cf08:	e0bffd17 	ldw	r2,-12(fp)
+ 802cf0c:	10000226 	beq	r2,zero,802cf18 <t_socketclose+0xa8>
+   {
+      /* do not do the following assignment since the socket structure
+         addressed by so has been freed by this point, jharan 12-10-98 */
+      /*      so->so_error = err;   */
+      return SOCKET_ERROR;
+ 802cf10:	00bfffc4 	movi	r2,-1
+ 802cf14:	00000106 	br	802cf1c <t_socketclose+0xac>
+   }
+   return 0;
+ 802cf18:	0005883a 	mov	r2,zero
+}
+ 802cf1c:	e037883a 	mov	sp,fp
+ 802cf20:	dfc00117 	ldw	ra,4(sp)
+ 802cf24:	df000017 	ldw	fp,0(sp)
+ 802cf28:	dec00204 	addi	sp,sp,8
+ 802cf2c:	f800283a 	ret
+
+0802cf30 <sockargs>:
+
+static struct mbuf  * 
+sockargs (void * arg, 
+   int   arglen, 
+   int   type)
+{
+ 802cf30:	defffa04 	addi	sp,sp,-24
+ 802cf34:	dfc00515 	stw	ra,20(sp)
+ 802cf38:	df000415 	stw	fp,16(sp)
+ 802cf3c:	df000404 	addi	fp,sp,16
+ 802cf40:	e13ffe15 	stw	r4,-8(fp)
+ 802cf44:	e17ffd15 	stw	r5,-12(fp)
+ 802cf48:	e1bffc15 	stw	r6,-16(fp)
+   struct mbuf *  m;
+
+   LOCK_NET_RESOURCE(NET_RESID);    /* protect mfreeq */
+ 802cf4c:	0009883a 	mov	r4,zero
+ 802cf50:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   m = m_getwithdata (type, arglen);
+ 802cf54:	e17ffd17 	ldw	r5,-12(fp)
+ 802cf58:	e13ffc17 	ldw	r4,-16(fp)
+ 802cf5c:	8029a700 	call	8029a70 <m_getnbuf>
+ 802cf60:	e0bfff15 	stw	r2,-4(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802cf64:	0009883a 	mov	r4,zero
+ 802cf68:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (m == NULL)
+ 802cf6c:	e0bfff17 	ldw	r2,-4(fp)
+ 802cf70:	1000021e 	bne	r2,zero,802cf7c <sockargs+0x4c>
+      return NULL;
+ 802cf74:	0005883a 	mov	r2,zero
+ 802cf78:	00000b06 	br	802cfa8 <sockargs+0x78>
+   m->m_len = arglen;
+ 802cf7c:	e0fffd17 	ldw	r3,-12(fp)
+ 802cf80:	e0bfff17 	ldw	r2,-4(fp)
+ 802cf84:	10c00215 	stw	r3,8(r2)
+   MEMCPY(mtod (m, char *), arg, arglen);
+ 802cf88:	e0bfff17 	ldw	r2,-4(fp)
+ 802cf8c:	10800317 	ldw	r2,12(r2)
+ 802cf90:	e0fffd17 	ldw	r3,-12(fp)
+ 802cf94:	180d883a 	mov	r6,r3
+ 802cf98:	e17ffe17 	ldw	r5,-8(fp)
+ 802cf9c:	1009883a 	mov	r4,r2
+ 802cfa0:	80086b80 	call	80086b8 <memcpy>
+   return m;
+ 802cfa4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802cfa8:	e037883a 	mov	sp,fp
+ 802cfac:	dfc00117 	ldw	ra,4(sp)
+ 802cfb0:	df000017 	ldw	fp,0(sp)
+ 802cfb4:	dec00204 	addi	sp,sp,8
+ 802cfb8:	f800283a 	ret
+
+0802cfbc <t_errno>:
+ *                            ENOTSOCK if socket not found
+ */
+
+int
+t_errno(long s)
+{
+ 802cfbc:	defffa04 	addi	sp,sp,-24
+ 802cfc0:	dfc00515 	stw	ra,20(sp)
+ 802cfc4:	df000415 	stw	fp,16(sp)
+ 802cfc8:	df000404 	addi	fp,sp,16
+ 802cfcc:	e13ffc15 	stw	r4,-16(fp)
+   struct socket *so = LONG2SO(s);
+ 802cfd0:	e0bffc17 	ldw	r2,-16(fp)
+ 802cfd4:	10bffc04 	addi	r2,r2,-16
+ 802cfd8:	100490ba 	slli	r2,r2,2
+ 802cfdc:	e0bffd15 	stw	r2,-12(fp)
+   struct socket *tmp;
+   int errcode = ENOTSOCK;
+ 802cfe0:	00801b04 	movi	r2,108
+ 802cfe4:	e0bffe15 	stw	r2,-8(fp)
+
+   LOCK_NET_RESOURCE(NET_RESID);    /* protect soq */
+ 802cfe8:	0009883a 	mov	r4,zero
+ 802cfec:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* search socket queue for passed socket. This routine should
+    * not use SOC_CHECK since it can be ifdeffed out, and we must
+    * be ready to return EPIPE if the socket does not exist.
+    */
+   for (tmp = (struct socket *)(&soq); tmp; tmp = tmp->next)
+ 802cff0:	008201b4 	movhi	r2,2054
+ 802cff4:	10b87104 	addi	r2,r2,-7740
+ 802cff8:	e0bfff15 	stw	r2,-4(fp)
+ 802cffc:	00000a06 	br	802d028 <t_errno+0x6c>
+   {
+      if (tmp == so)  /* found socket, return error */
+ 802d000:	e0ffff17 	ldw	r3,-4(fp)
+ 802d004:	e0bffd17 	ldw	r2,-12(fp)
+ 802d008:	1880041e 	bne	r3,r2,802d01c <t_errno+0x60>
+      {
+         errcode = so->so_error;
+ 802d00c:	e0bffd17 	ldw	r2,-12(fp)
+ 802d010:	10800617 	ldw	r2,24(r2)
+ 802d014:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 802d018:	00000506 	br	802d030 <t_errno+0x74>
+   for (tmp = (struct socket *)(&soq); tmp; tmp = tmp->next)
+ 802d01c:	e0bfff17 	ldw	r2,-4(fp)
+ 802d020:	10800017 	ldw	r2,0(r2)
+ 802d024:	e0bfff15 	stw	r2,-4(fp)
+ 802d028:	e0bfff17 	ldw	r2,-4(fp)
+ 802d02c:	103ff41e 	bne	r2,zero,802d000 <t_errno+0x44>
+      }
+   }
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 802d030:	0009883a 	mov	r4,zero
+ 802d034:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   return errcode;
+ 802d038:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 802d03c:	e037883a 	mov	sp,fp
+ 802d040:	dfc00117 	ldw	ra,4(sp)
+ 802d044:	df000017 	ldw	fp,0(sp)
+ 802d048:	dec00204 	addi	sp,sp,8
+ 802d04c:	f800283a 	ret
+
+0802d050 <socreate>:
+ * RETURNS: 
+ */
+
+struct socket *   
+socreate (int dom, int type, int proto)
+{
+ 802d050:	defff704 	addi	sp,sp,-36
+ 802d054:	dfc00815 	stw	ra,32(sp)
+ 802d058:	df000715 	stw	fp,28(sp)
+ 802d05c:	df000704 	addi	fp,sp,28
+ 802d060:	e13ffb15 	stw	r4,-20(fp)
+ 802d064:	e17ffa15 	stw	r5,-24(fp)
+ 802d068:	e1bff915 	stw	r6,-28(fp)
+   struct protosw *prp;
+   struct socket *so;
+   int   error;
+   int rc;
+
+   if (proto)
+ 802d06c:	e0bff917 	ldw	r2,-28(fp)
+ 802d070:	10000626 	beq	r2,zero,802d08c <socreate+0x3c>
+      prp = pffindproto(dom, proto, type);
+ 802d074:	e1bffa17 	ldw	r6,-24(fp)
+ 802d078:	e17ff917 	ldw	r5,-28(fp)
+ 802d07c:	e13ffb17 	ldw	r4,-20(fp)
+ 802d080:	80299a40 	call	80299a4 <pffindproto>
+ 802d084:	e0bfff15 	stw	r2,-4(fp)
+ 802d088:	00000406 	br	802d09c <socreate+0x4c>
+   else
+      prp = pffindtype(dom, type);
+ 802d08c:	e17ffa17 	ldw	r5,-24(fp)
+ 802d090:	e13ffb17 	ldw	r4,-20(fp)
+ 802d094:	80299140 	call	8029914 <pffindtype>
+ 802d098:	e0bfff15 	stw	r2,-4(fp)
+   if (prp == 0)
+ 802d09c:	e0bfff17 	ldw	r2,-4(fp)
+ 802d0a0:	1000021e 	bne	r2,zero,802d0ac <socreate+0x5c>
+      return NULL;
+ 802d0a4:	0005883a 	mov	r2,zero
+ 802d0a8:	00004e06 	br	802d1e4 <socreate+0x194>
+   if (prp->pr_type != type)
+ 802d0ac:	e0bfff17 	ldw	r2,-4(fp)
+ 802d0b0:	1080000b 	ldhu	r2,0(r2)
+ 802d0b4:	10bfffcc 	andi	r2,r2,65535
+ 802d0b8:	10a0001c 	xori	r2,r2,32768
+ 802d0bc:	10a00004 	addi	r2,r2,-32768
+ 802d0c0:	e0fffa17 	ldw	r3,-24(fp)
+ 802d0c4:	18800226 	beq	r3,r2,802d0d0 <socreate+0x80>
+      return NULL;
+ 802d0c8:	0005883a 	mov	r2,zero
+ 802d0cc:	00004506 	br	802d1e4 <socreate+0x194>
+   if ((so = SOC_ALLOC (sizeof (*so))) == NULL)
+ 802d0d0:	01002104 	movi	r4,132
+ 802d0d4:	802982c0 	call	802982c <npalloc>
+ 802d0d8:	e0bffe15 	stw	r2,-8(fp)
+ 802d0dc:	e0bffe17 	ldw	r2,-8(fp)
+ 802d0e0:	1000021e 	bne	r2,zero,802d0ec <socreate+0x9c>
+      return NULL;
+ 802d0e4:	0005883a 	mov	r2,zero
+ 802d0e8:	00003e06 	br	802d1e4 <socreate+0x194>
+   so->next = NULL;
+ 802d0ec:	e0bffe17 	ldw	r2,-8(fp)
+ 802d0f0:	10000015 	stw	zero,0(r2)
+   putq(&soq,(qp)so);
+ 802d0f4:	e17ffe17 	ldw	r5,-8(fp)
+ 802d0f8:	010201b4 	movhi	r4,2054
+ 802d0fc:	21387104 	addi	r4,r4,-7740
+ 802d100:	80289900 	call	8028990 <putq>
+
+   so->so_options = socket_defaults;
+ 802d104:	d0a01c0b 	ldhu	r2,-32656(gp)
+ 802d108:	10ffffcc 	andi	r3,r2,65535
+ 802d10c:	e0bffe17 	ldw	r2,-8(fp)
+ 802d110:	10c00415 	stw	r3,16(r2)
+   so->so_domain = dom;
+ 802d114:	e0bffe17 	ldw	r2,-8(fp)
+ 802d118:	e0fffb17 	ldw	r3,-20(fp)
+ 802d11c:	10c00515 	stw	r3,20(r2)
+   so->so_state = 0;
+ 802d120:	e0bffe17 	ldw	r2,-8(fp)
+ 802d124:	1000088d 	sth	zero,34(r2)
+   so->so_type = (char)type;
+ 802d128:	e0bffa17 	ldw	r2,-24(fp)
+ 802d12c:	1007883a 	mov	r3,r2
+ 802d130:	e0bffe17 	ldw	r2,-8(fp)
+ 802d134:	10c00985 	stb	r3,38(r2)
+   so->so_proto = prp;
+ 802d138:	e0bffe17 	ldw	r2,-8(fp)
+ 802d13c:	e0ffff17 	ldw	r3,-4(fp)
+ 802d140:	10c00215 	stw	r3,8(r2)
+
+#ifdef IP_MULTICAST
+   so->inp_moptions = NULL;
+ 802d144:	e0bffe17 	ldw	r2,-8(fp)
+ 802d148:	10000315 	stw	zero,12(r2)
+#endif   /* IP_MULTICAST */
+
+   so->so_req = PRU_ATTACH;
+ 802d14c:	e0bffe17 	ldw	r2,-8(fp)
+ 802d150:	10000715 	stw	zero,28(r2)
+   error = (*prp->pr_usrreq)(so,(struct mbuf *)0, LONG2MBUF((long)proto));
+ 802d154:	e0bfff17 	ldw	r2,-4(fp)
+ 802d158:	10800317 	ldw	r2,12(r2)
+ 802d15c:	e0fff917 	ldw	r3,-28(fp)
+ 802d160:	180d883a 	mov	r6,r3
+ 802d164:	000b883a 	mov	r5,zero
+ 802d168:	e13ffe17 	ldw	r4,-8(fp)
+ 802d16c:	103ee83a 	callr	r2
+ 802d170:	e0bffd15 	stw	r2,-12(fp)
+   if (error) goto bad;
+ 802d174:	e0bffd17 	ldw	r2,-12(fp)
+ 802d178:	10000a1e 	bne	r2,zero,802d1a4 <socreate+0x154>
+
+   if (so_evtmap)
+ 802d17c:	d0a09a03 	ldbu	r2,-32152(gp)
+ 802d180:	10803fcc 	andi	r2,r2,255
+ 802d184:	10001626 	beq	r2,zero,802d1e0 <socreate+0x190>
+   {                       
+      rc = (*so_evtmap_create) (so);
+ 802d188:	d0a09817 	ldw	r2,-32160(gp)
+ 802d18c:	e13ffe17 	ldw	r4,-8(fp)
+ 802d190:	103ee83a 	callr	r2
+ 802d194:	e0bffc15 	stw	r2,-16(fp)
+      if (rc != 0)
+ 802d198:	e0bffc17 	ldw	r2,-16(fp)
+ 802d19c:	10000c26 	beq	r2,zero,802d1d0 <socreate+0x180>
+      {
+bad:   
+ 802d1a0:	00000106 	br	802d1a8 <socreate+0x158>
+   if (error) goto bad;
+ 802d1a4:	0001883a 	nop
+         so->so_state |= SS_NOFDREF;
+ 802d1a8:	e0bffe17 	ldw	r2,-8(fp)
+ 802d1ac:	1080088b 	ldhu	r2,34(r2)
+ 802d1b0:	10800054 	ori	r2,r2,1
+ 802d1b4:	1007883a 	mov	r3,r2
+ 802d1b8:	e0bffe17 	ldw	r2,-8(fp)
+ 802d1bc:	10c0088d 	sth	r3,34(r2)
+         sofree (so);
+ 802d1c0:	e13ffe17 	ldw	r4,-8(fp)
+ 802d1c4:	802d3240 	call	802d324 <sofree>
+         return NULL;   
+ 802d1c8:	0005883a 	mov	r2,zero
+ 802d1cc:	00000506 	br	802d1e4 <socreate+0x194>
+      /*
+       * Altera Niche Stack Nios port modification:
+       * Remove (void *) cast since -> owner is now TK_OBJECT
+       * to fix build warning.
+       */
+      so->owner = TK_THIS;
+ 802d1d0:	8027c780 	call	8027c78 <TK_OSTaskQuery>
+ 802d1d4:	1007883a 	mov	r3,r2
+ 802d1d8:	e0bffe17 	ldw	r2,-8(fp)
+ 802d1dc:	10c02005 	stb	r3,128(r2)
+   }
+
+   return so;
+ 802d1e0:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 802d1e4:	e037883a 	mov	sp,fp
+ 802d1e8:	dfc00117 	ldw	ra,4(sp)
+ 802d1ec:	df000017 	ldw	fp,0(sp)
+ 802d1f0:	dec00204 	addi	sp,sp,8
+ 802d1f4:	f800283a 	ret
+
+0802d1f8 <sobind>:
+ */
+
+int
+sobind(struct socket * so, 
+   struct mbuf *  nam)
+{
+ 802d1f8:	defffb04 	addi	sp,sp,-20
+ 802d1fc:	dfc00415 	stw	ra,16(sp)
+ 802d200:	df000315 	stw	fp,12(sp)
+ 802d204:	df000304 	addi	fp,sp,12
+ 802d208:	e13ffe15 	stw	r4,-8(fp)
+ 802d20c:	e17ffd15 	stw	r5,-12(fp)
+   int   error;
+
+   so->so_req = PRU_BIND;
+ 802d210:	e0bffe17 	ldw	r2,-8(fp)
+ 802d214:	00c00084 	movi	r3,2
+ 802d218:	10c00715 	stw	r3,28(r2)
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+ 802d21c:	e0bffe17 	ldw	r2,-8(fp)
+ 802d220:	10800217 	ldw	r2,8(r2)
+ 802d224:	10800317 	ldw	r2,12(r2)
+ 802d228:	e1bffd17 	ldw	r6,-12(fp)
+ 802d22c:	000b883a 	mov	r5,zero
+ 802d230:	e13ffe17 	ldw	r4,-8(fp)
+ 802d234:	103ee83a 	callr	r2
+ 802d238:	e0bfff15 	stw	r2,-4(fp)
+   return (error);
+ 802d23c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802d240:	e037883a 	mov	sp,fp
+ 802d244:	dfc00117 	ldw	ra,4(sp)
+ 802d248:	df000017 	ldw	fp,0(sp)
+ 802d24c:	dec00204 	addi	sp,sp,8
+ 802d250:	f800283a 	ret
+
+0802d254 <solisten>:
+ */
+
+int
+solisten(struct socket * so, 
+   int   backlog)
+{
+ 802d254:	defffb04 	addi	sp,sp,-20
+ 802d258:	dfc00415 	stw	ra,16(sp)
+ 802d25c:	df000315 	stw	fp,12(sp)
+ 802d260:	df000304 	addi	fp,sp,12
+ 802d264:	e13ffe15 	stw	r4,-8(fp)
+ 802d268:	e17ffd15 	stw	r5,-12(fp)
+   int   error;
+
+   so->so_req = PRU_LISTEN;
+ 802d26c:	e0bffe17 	ldw	r2,-8(fp)
+ 802d270:	00c000c4 	movi	r3,3
+ 802d274:	10c00715 	stw	r3,28(r2)
+   error = (*so->so_proto->pr_usrreq)(so,
+ 802d278:	e0bffe17 	ldw	r2,-8(fp)
+ 802d27c:	10800217 	ldw	r2,8(r2)
+ 802d280:	10800317 	ldw	r2,12(r2)
+ 802d284:	000d883a 	mov	r6,zero
+ 802d288:	000b883a 	mov	r5,zero
+ 802d28c:	e13ffe17 	ldw	r4,-8(fp)
+ 802d290:	103ee83a 	callr	r2
+ 802d294:	e0bfff15 	stw	r2,-4(fp)
+    (struct mbuf *)0, (struct mbuf *)0);
+   if (error) 
+ 802d298:	e0bfff17 	ldw	r2,-4(fp)
+ 802d29c:	10000226 	beq	r2,zero,802d2a8 <solisten+0x54>
+   {
+      return (error);
+ 802d2a0:	e0bfff17 	ldw	r2,-4(fp)
+ 802d2a4:	00001a06 	br	802d310 <solisten+0xbc>
+   }
+   if (so->so_q == 0) 
+ 802d2a8:	e0bffe17 	ldw	r2,-8(fp)
+ 802d2ac:	10801d17 	ldw	r2,116(r2)
+ 802d2b0:	10000b1e 	bne	r2,zero,802d2e0 <solisten+0x8c>
+   {
+      so->so_q = so;
+ 802d2b4:	e0bffe17 	ldw	r2,-8(fp)
+ 802d2b8:	e0fffe17 	ldw	r3,-8(fp)
+ 802d2bc:	10c01d15 	stw	r3,116(r2)
+      so->so_q0 = so;
+ 802d2c0:	e0bffe17 	ldw	r2,-8(fp)
+ 802d2c4:	e0fffe17 	ldw	r3,-8(fp)
+ 802d2c8:	10c01c15 	stw	r3,112(r2)
+      so->so_options |= SO_ACCEPTCONN;
+ 802d2cc:	e0bffe17 	ldw	r2,-8(fp)
+ 802d2d0:	10800417 	ldw	r2,16(r2)
+ 802d2d4:	10c00094 	ori	r3,r2,2
+ 802d2d8:	e0bffe17 	ldw	r2,-8(fp)
+ 802d2dc:	10c00415 	stw	r3,16(r2)
+   }
+   if (backlog < 0)
+ 802d2e0:	e0bffd17 	ldw	r2,-12(fp)
+ 802d2e4:	1000010e 	bge	r2,zero,802d2ec <solisten+0x98>
+      backlog = 0;
+ 802d2e8:	e03ffd15 	stw	zero,-12(fp)
+   so->so_qlimit = (char)MIN(backlog, SOMAXCONN);
+ 802d2ec:	e0bffd17 	ldw	r2,-12(fp)
+ 802d2f0:	10800188 	cmpgei	r2,r2,6
+ 802d2f4:	1000021e 	bne	r2,zero,802d300 <solisten+0xac>
+ 802d2f8:	e0bffd17 	ldw	r2,-12(fp)
+ 802d2fc:	00000106 	br	802d304 <solisten+0xb0>
+ 802d300:	00800144 	movi	r2,5
+ 802d304:	e0fffe17 	ldw	r3,-8(fp)
+ 802d308:	18801e85 	stb	r2,122(r3)
+   return 0;
+ 802d30c:	0005883a 	mov	r2,zero
+}
+ 802d310:	e037883a 	mov	sp,fp
+ 802d314:	dfc00117 	ldw	ra,4(sp)
+ 802d318:	df000017 	ldw	fp,0(sp)
+ 802d31c:	dec00204 	addi	sp,sp,8
+ 802d320:	f800283a 	ret
+
+0802d324 <sofree>:
+ * RETURNS: 
+ */
+
+void
+sofree(struct socket * so)
+{
+ 802d324:	defffd04 	addi	sp,sp,-12
+ 802d328:	dfc00215 	stw	ra,8(sp)
+ 802d32c:	df000115 	stw	fp,4(sp)
+ 802d330:	df000104 	addi	fp,sp,4
+ 802d334:	e13fff15 	stw	r4,-4(fp)
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: sofree, so %lx so_pcb %lx so_state %x so_head %lx\n",
+    so, so->so_pcb, so->so_state, so->so_head));
+
+   if (so->so_pcb || (so->so_state & SS_NOFDREF) == 0)
+ 802d338:	e0bfff17 	ldw	r2,-4(fp)
+ 802d33c:	10800117 	ldw	r2,4(r2)
+ 802d340:	1000361e 	bne	r2,zero,802d41c <sofree+0xf8>
+ 802d344:	e0bfff17 	ldw	r2,-4(fp)
+ 802d348:	1080088b 	ldhu	r2,34(r2)
+ 802d34c:	10bfffcc 	andi	r2,r2,65535
+ 802d350:	1080004c 	andi	r2,r2,1
+ 802d354:	10003126 	beq	r2,zero,802d41c <sofree+0xf8>
+      return;
+   if (so->so_head) 
+ 802d358:	e0bfff17 	ldw	r2,-4(fp)
+ 802d35c:	10801b17 	ldw	r2,108(r2)
+ 802d360:	10000d26 	beq	r2,zero,802d398 <sofree+0x74>
+   {
+      if (!soqremque(so, 0) && !soqremque(so, 1))
+ 802d364:	000b883a 	mov	r5,zero
+ 802d368:	e13fff17 	ldw	r4,-4(fp)
+ 802d36c:	802f6ec0 	call	802f6ec <soqremque>
+ 802d370:	1000071e 	bne	r2,zero,802d390 <sofree+0x6c>
+ 802d374:	01400044 	movi	r5,1
+ 802d378:	e13fff17 	ldw	r4,-4(fp)
+ 802d37c:	802f6ec0 	call	802f6ec <soqremque>
+ 802d380:	1000031e 	bne	r2,zero,802d390 <sofree+0x6c>
+         panic("sofree");
+ 802d384:	01020174 	movhi	r4,2053
+ 802d388:	212a7604 	addi	r4,r4,-22056
+ 802d38c:	80271780 	call	8027178 <panic>
+      so->so_head = 0;
+ 802d390:	e0bfff17 	ldw	r2,-4(fp)
+ 802d394:	10001b15 	stw	zero,108(r2)
+   }
+   sbrelease(&so->so_snd);
+ 802d398:	e0bfff17 	ldw	r2,-4(fp)
+ 802d39c:	10801204 	addi	r2,r2,72
+ 802d3a0:	1009883a 	mov	r4,r2
+ 802d3a4:	802fab00 	call	802fab0 <sbrelease>
+   sorflush(so);
+ 802d3a8:	e13fff17 	ldw	r4,-4(fp)
+ 802d3ac:	802e6840 	call	802e684 <sorflush>
+      _socket_free_entry (so);
+#endif   /* SAVE_SOCK_ENDPOINTS */
+
+#ifdef IP_MULTICAST
+   /* multicast opts? */
+   if (so->inp_moptions)
+ 802d3b0:	e0bfff17 	ldw	r2,-4(fp)
+ 802d3b4:	10800317 	ldw	r2,12(r2)
+ 802d3b8:	10000426 	beq	r2,zero,802d3cc <sofree+0xa8>
+	   ip_freemoptions(so->inp_moptions);
+ 802d3bc:	e0bfff17 	ldw	r2,-4(fp)
+ 802d3c0:	10800317 	ldw	r2,12(r2)
+ 802d3c4:	1009883a 	mov	r4,r2
+ 802d3c8:	803ee740 	call	803ee74 <ip_freemoptions>
+#endif   /* IP_MULTICAST */
+
+   /* IP_TOS opts? */
+   if (so->so_optsPack)
+ 802d3cc:	e0bfff17 	ldw	r2,-4(fp)
+ 802d3d0:	10801f17 	ldw	r2,124(r2)
+ 802d3d4:	10000426 	beq	r2,zero,802d3e8 <sofree+0xc4>
+      SOCOPT_FREE(so->so_optsPack);
+ 802d3d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802d3dc:	10801f17 	ldw	r2,124(r2)
+ 802d3e0:	1009883a 	mov	r4,r2
+ 802d3e4:	80298600 	call	8029860 <npfree>
+	   
+   qdel(&soq, so);   /* Delete the socket entry from the queue */
+ 802d3e8:	e17fff17 	ldw	r5,-4(fp)
+ 802d3ec:	010201b4 	movhi	r4,2054
+ 802d3f0:	21387104 	addi	r4,r4,-7740
+ 802d3f4:	8028a400 	call	8028a40 <qdel>
+   
+   if (so_evtmap)  
+ 802d3f8:	d0a09a03 	ldbu	r2,-32152(gp)
+ 802d3fc:	10803fcc 	andi	r2,r2,255
+ 802d400:	10000326 	beq	r2,zero,802d410 <sofree+0xec>
+      (*so_evtmap_delete) (so);
+ 802d404:	d0a09917 	ldw	r2,-32156(gp)
+ 802d408:	e13fff17 	ldw	r4,-4(fp)
+ 802d40c:	103ee83a 	callr	r2
+   
+   SOC_FREE(so);
+ 802d410:	e13fff17 	ldw	r4,-4(fp)
+ 802d414:	80298600 	call	8029860 <npfree>
+ 802d418:	00000106 	br	802d420 <sofree+0xfc>
+      return;
+ 802d41c:	0001883a 	nop
+}
+ 802d420:	e037883a 	mov	sp,fp
+ 802d424:	dfc00117 	ldw	ra,4(sp)
+ 802d428:	df000017 	ldw	fp,0(sp)
+ 802d42c:	dec00204 	addi	sp,sp,8
+ 802d430:	f800283a 	ret
+
+0802d434 <soclose>:
+ * RETURNS: 
+ */
+
+int
+soclose(struct socket * so)
+{
+ 802d434:	defff904 	addi	sp,sp,-28
+ 802d438:	dfc00615 	stw	ra,24(sp)
+ 802d43c:	df000515 	stw	fp,20(sp)
+ 802d440:	df000504 	addi	fp,sp,20
+ 802d444:	e13ffb15 	stw	r4,-20(fp)
+   int   error =  0;
+ 802d448:	e03fff15 	stw	zero,-4(fp)
+   unsigned long endtime;
+
+   /* Check whether the closing socket is in the socket queue.  If it is
+    * not, return a EINVAL error code to the caller.
+    */
+   for ((tmpso=(struct socket *)soq.q_head);tmpso != NULL;tmpso=tmpso->next)
+ 802d44c:	008201b4 	movhi	r2,2054
+ 802d450:	10b87117 	ldw	r2,-7740(r2)
+ 802d454:	e0bffe15 	stw	r2,-8(fp)
+ 802d458:	00000606 	br	802d474 <soclose+0x40>
+   {
+      if (so == tmpso)
+ 802d45c:	e0fffb17 	ldw	r3,-20(fp)
+ 802d460:	e0bffe17 	ldw	r2,-8(fp)
+ 802d464:	18800626 	beq	r3,r2,802d480 <soclose+0x4c>
+   for ((tmpso=(struct socket *)soq.q_head);tmpso != NULL;tmpso=tmpso->next)
+ 802d468:	e0bffe17 	ldw	r2,-8(fp)
+ 802d46c:	10800017 	ldw	r2,0(r2)
+ 802d470:	e0bffe15 	stw	r2,-8(fp)
+ 802d474:	e0bffe17 	ldw	r2,-8(fp)
+ 802d478:	103ff81e 	bne	r2,zero,802d45c <soclose+0x28>
+ 802d47c:	00000106 	br	802d484 <soclose+0x50>
+         break;
+ 802d480:	0001883a 	nop
+   }
+   if ( tmpso == NULL)
+ 802d484:	e0bffe17 	ldw	r2,-8(fp)
+ 802d488:	1000021e 	bne	r2,zero,802d494 <soclose+0x60>
+      return EINVAL;
+ 802d48c:	00800584 	movi	r2,22
+ 802d490:	00009506 	br	802d6e8 <soclose+0x2b4>
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: soclose, so %lx  so_pcb %lx so_state %x so_q %lx\n",
+    so, so->so_pcb, so->so_state, so->so_q));
+   if (so->so_options & SO_ACCEPTCONN)
+ 802d494:	e0bffb17 	ldw	r2,-20(fp)
+ 802d498:	10800417 	ldw	r2,16(r2)
+ 802d49c:	1080008c 	andi	r2,r2,2
+ 802d4a0:	10001226 	beq	r2,zero,802d4ec <soclose+0xb8>
+   {
+      while (so->so_q0 != so)
+ 802d4a4:	00000406 	br	802d4b8 <soclose+0x84>
+         (void) soabort(so->so_q0);
+ 802d4a8:	e0bffb17 	ldw	r2,-20(fp)
+ 802d4ac:	10801c17 	ldw	r2,112(r2)
+ 802d4b0:	1009883a 	mov	r4,r2
+ 802d4b4:	802d6fc0 	call	802d6fc <soabort>
+      while (so->so_q0 != so)
+ 802d4b8:	e0bffb17 	ldw	r2,-20(fp)
+ 802d4bc:	10801c17 	ldw	r2,112(r2)
+ 802d4c0:	e0fffb17 	ldw	r3,-20(fp)
+ 802d4c4:	18bff81e 	bne	r3,r2,802d4a8 <soclose+0x74>
+      while (so->so_q != so)
+ 802d4c8:	00000406 	br	802d4dc <soclose+0xa8>
+         (void) soabort(so->so_q);
+ 802d4cc:	e0bffb17 	ldw	r2,-20(fp)
+ 802d4d0:	10801d17 	ldw	r2,116(r2)
+ 802d4d4:	1009883a 	mov	r4,r2
+ 802d4d8:	802d6fc0 	call	802d6fc <soabort>
+      while (so->so_q != so)
+ 802d4dc:	e0bffb17 	ldw	r2,-20(fp)
+ 802d4e0:	10801d17 	ldw	r2,116(r2)
+ 802d4e4:	e0fffb17 	ldw	r3,-20(fp)
+ 802d4e8:	18bff81e 	bne	r3,r2,802d4cc <soclose+0x98>
+   }
+   /* for datagram-oriented sockets, dispense with further tests */
+   if (so->so_type != SOCK_STREAM)
+ 802d4ec:	e0bffb17 	ldw	r2,-20(fp)
+ 802d4f0:	10800983 	ldbu	r2,38(r2)
+ 802d4f4:	10803fcc 	andi	r2,r2,255
+ 802d4f8:	1080201c 	xori	r2,r2,128
+ 802d4fc:	10bfe004 	addi	r2,r2,-128
+ 802d500:	10800060 	cmpeqi	r2,r2,1
+ 802d504:	10000c1e 	bne	r2,zero,802d538 <soclose+0x104>
+   { 
+      so->so_req = PRU_DETACH;
+ 802d508:	e0bffb17 	ldw	r2,-20(fp)
+ 802d50c:	00c00044 	movi	r3,1
+ 802d510:	10c00715 	stw	r3,28(r2)
+      error = (*so->so_proto->pr_usrreq)(so,
+ 802d514:	e0bffb17 	ldw	r2,-20(fp)
+ 802d518:	10800217 	ldw	r2,8(r2)
+ 802d51c:	10800317 	ldw	r2,12(r2)
+ 802d520:	000d883a 	mov	r6,zero
+ 802d524:	000b883a 	mov	r5,zero
+ 802d528:	e13ffb17 	ldw	r4,-20(fp)
+ 802d52c:	103ee83a 	callr	r2
+ 802d530:	e0bfff15 	stw	r2,-4(fp)
+       (struct mbuf *)0, (struct mbuf *)0);
+      goto discard;
+ 802d534:	00005d06 	br	802d6ac <soclose+0x278>
+   }
+
+   if (so->so_pcb == 0)
+ 802d538:	e0bffb17 	ldw	r2,-20(fp)
+ 802d53c:	10800117 	ldw	r2,4(r2)
+ 802d540:	10005726 	beq	r2,zero,802d6a0 <soclose+0x26c>
+      goto discard;
+   if (so->so_state & SS_ISCONNECTED) 
+ 802d544:	e0bffb17 	ldw	r2,-20(fp)
+ 802d548:	1080088b 	ldhu	r2,34(r2)
+ 802d54c:	10bfffcc 	andi	r2,r2,65535
+ 802d550:	1080008c 	andi	r2,r2,2
+ 802d554:	10003a26 	beq	r2,zero,802d640 <soclose+0x20c>
+   {
+      if ((so->so_state & SS_ISDISCONNECTING) == 0) 
+ 802d558:	e0bffb17 	ldw	r2,-20(fp)
+ 802d55c:	1080088b 	ldhu	r2,34(r2)
+ 802d560:	10bfffcc 	andi	r2,r2,65535
+ 802d564:	1080020c 	andi	r2,r2,8
+ 802d568:	1000051e 	bne	r2,zero,802d580 <soclose+0x14c>
+      {
+         error = sodisconnect(so);
+ 802d56c:	e13ffb17 	ldw	r4,-20(fp)
+ 802d570:	802d89c0 	call	802d89c <sodisconnect>
+ 802d574:	e0bfff15 	stw	r2,-4(fp)
+         if (error)
+ 802d578:	e0bfff17 	ldw	r2,-4(fp)
+ 802d57c:	1000321e 	bne	r2,zero,802d648 <soclose+0x214>
+            goto drop;
+      }
+      if (so->so_options & SO_LINGER) 
+ 802d580:	e0bffb17 	ldw	r2,-20(fp)
+ 802d584:	10800417 	ldw	r2,16(r2)
+ 802d588:	1080200c 	andi	r2,r2,128
+ 802d58c:	10002126 	beq	r2,zero,802d614 <soclose+0x1e0>
+      {
+         if ((so->so_state & SS_ISDISCONNECTING) &&
+ 802d590:	e0bffb17 	ldw	r2,-20(fp)
+ 802d594:	1080088b 	ldhu	r2,34(r2)
+ 802d598:	10bfffcc 	andi	r2,r2,65535
+ 802d59c:	1080020c 	andi	r2,r2,8
+ 802d5a0:	10000526 	beq	r2,zero,802d5b8 <soclose+0x184>
+             (so->so_state & SS_NBIO))
+ 802d5a4:	e0bffb17 	ldw	r2,-20(fp)
+ 802d5a8:	1080088b 	ldhu	r2,34(r2)
+ 802d5ac:	10bfffcc 	andi	r2,r2,65535
+ 802d5b0:	1080400c 	andi	r2,r2,256
+         if ((so->so_state & SS_ISDISCONNECTING) &&
+ 802d5b4:	1000261e 	bne	r2,zero,802d650 <soclose+0x21c>
+         {
+            goto drop;
+         }
+         endtime = cticks + (unsigned long)so->so_linger * TPS;         
+ 802d5b8:	e0bffb17 	ldw	r2,-20(fp)
+ 802d5bc:	1080080b 	ldhu	r2,32(r2)
+ 802d5c0:	10bfffcc 	andi	r2,r2,65535
+ 802d5c4:	10a0001c 	xori	r2,r2,32768
+ 802d5c8:	10a00004 	addi	r2,r2,-32768
+ 802d5cc:	10c01924 	muli	r3,r2,100
+ 802d5d0:	d0a07d17 	ldw	r2,-32268(gp)
+ 802d5d4:	1885883a 	add	r2,r3,r2
+ 802d5d8:	e0bffd15 	stw	r2,-12(fp)
+         while ((so->so_state & SS_ISCONNECTED) && (cticks < endtime))
+ 802d5dc:	00000406 	br	802d5f0 <soclose+0x1bc>
+         {
+            tcp_sleep((char *)&so->so_timeo);
+ 802d5e0:	e0bffb17 	ldw	r2,-20(fp)
+ 802d5e4:	10800904 	addi	r2,r2,36
+ 802d5e8:	1009883a 	mov	r4,r2
+ 802d5ec:	8027a540 	call	8027a54 <tcp_sleep>
+         while ((so->so_state & SS_ISCONNECTED) && (cticks < endtime))
+ 802d5f0:	e0bffb17 	ldw	r2,-20(fp)
+ 802d5f4:	1080088b 	ldhu	r2,34(r2)
+ 802d5f8:	10bfffcc 	andi	r2,r2,65535
+ 802d5fc:	1080008c 	andi	r2,r2,2
+ 802d600:	10001426 	beq	r2,zero,802d654 <soclose+0x220>
+ 802d604:	d0e07d17 	ldw	r3,-32268(gp)
+ 802d608:	e0bffd17 	ldw	r2,-12(fp)
+ 802d60c:	18bff436 	bltu	r3,r2,802d5e0 <soclose+0x1ac>
+ 802d610:	00001006 	br	802d654 <soclose+0x220>
+      {
+         /* If socket still has send data just return now, leaving the 
+          * socket intact so the data can be sent. Socket should be cleaned
+          * up later by timers.
+          */
+         if(so->so_snd.sb_cc)
+ 802d614:	e0bffb17 	ldw	r2,-20(fp)
+ 802d618:	10801217 	ldw	r2,72(r2)
+ 802d61c:	10000826 	beq	r2,zero,802d640 <soclose+0x20c>
+         {
+            so->so_state |= SS_NOFDREF;   /* mark as OK to close */
+ 802d620:	e0bffb17 	ldw	r2,-20(fp)
+ 802d624:	1080088b 	ldhu	r2,34(r2)
+ 802d628:	10800054 	ori	r2,r2,1
+ 802d62c:	1007883a 	mov	r3,r2
+ 802d630:	e0bffb17 	ldw	r2,-20(fp)
+ 802d634:	10c0088d 	sth	r3,34(r2)
+            return 0;
+ 802d638:	0005883a 	mov	r2,zero
+ 802d63c:	00002a06 	br	802d6e8 <soclose+0x2b4>
+         }
+      }
+   }
+drop:
+ 802d640:	0001883a 	nop
+ 802d644:	00000306 	br	802d654 <soclose+0x220>
+            goto drop;
+ 802d648:	0001883a 	nop
+ 802d64c:	00000106 	br	802d654 <soclose+0x220>
+            goto drop;
+ 802d650:	0001883a 	nop
+   if (so->so_pcb) 
+ 802d654:	e0bffb17 	ldw	r2,-20(fp)
+ 802d658:	10800117 	ldw	r2,4(r2)
+ 802d65c:	10001226 	beq	r2,zero,802d6a8 <soclose+0x274>
+   {
+      int   error2;
+      so->so_req = PRU_DETACH;
+ 802d660:	e0bffb17 	ldw	r2,-20(fp)
+ 802d664:	00c00044 	movi	r3,1
+ 802d668:	10c00715 	stw	r3,28(r2)
+      error2 = (*so->so_proto->pr_usrreq)(so,
+ 802d66c:	e0bffb17 	ldw	r2,-20(fp)
+ 802d670:	10800217 	ldw	r2,8(r2)
+ 802d674:	10800317 	ldw	r2,12(r2)
+ 802d678:	000d883a 	mov	r6,zero
+ 802d67c:	000b883a 	mov	r5,zero
+ 802d680:	e13ffb17 	ldw	r4,-20(fp)
+ 802d684:	103ee83a 	callr	r2
+ 802d688:	e0bffc15 	stw	r2,-16(fp)
+       (struct mbuf *)0, (struct mbuf *)0);
+      if (error == 0)
+ 802d68c:	e0bfff17 	ldw	r2,-4(fp)
+ 802d690:	1000051e 	bne	r2,zero,802d6a8 <soclose+0x274>
+         error = error2;
+ 802d694:	e0bffc17 	ldw	r2,-16(fp)
+ 802d698:	e0bfff15 	stw	r2,-4(fp)
+ 802d69c:	00000306 	br	802d6ac <soclose+0x278>
+      goto discard;
+ 802d6a0:	0001883a 	nop
+ 802d6a4:	00000106 	br	802d6ac <soclose+0x278>
+   }
+discard:
+ 802d6a8:	0001883a 	nop
+   if (so->so_state & SS_NOFDREF)
+ 802d6ac:	e0bffb17 	ldw	r2,-20(fp)
+ 802d6b0:	1080088b 	ldhu	r2,34(r2)
+ 802d6b4:	10bfffcc 	andi	r2,r2,65535
+ 802d6b8:	1080004c 	andi	r2,r2,1
+ 802d6bc:	10000126 	beq	r2,zero,802d6c4 <soclose+0x290>
+   {
+      /* panic("soclose");  - non-fatal - degrade to dtrap() for now */
+      dtrap();
+ 802d6c0:	8028cd40 	call	8028cd4 <dtrap>
+   }
+   so->so_state |= SS_NOFDREF;
+ 802d6c4:	e0bffb17 	ldw	r2,-20(fp)
+ 802d6c8:	1080088b 	ldhu	r2,34(r2)
+ 802d6cc:	10800054 	ori	r2,r2,1
+ 802d6d0:	1007883a 	mov	r3,r2
+ 802d6d4:	e0bffb17 	ldw	r2,-20(fp)
+ 802d6d8:	10c0088d 	sth	r3,34(r2)
+   sofree(so);
+ 802d6dc:	e13ffb17 	ldw	r4,-20(fp)
+ 802d6e0:	802d3240 	call	802d324 <sofree>
+   return (error);
+ 802d6e4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802d6e8:	e037883a 	mov	sp,fp
+ 802d6ec:	dfc00117 	ldw	ra,4(sp)
+ 802d6f0:	df000017 	ldw	fp,0(sp)
+ 802d6f4:	dec00204 	addi	sp,sp,8
+ 802d6f8:	f800283a 	ret
+
+0802d6fc <soabort>:
+ * RETURNS: 
+ */
+
+int
+soabort(struct socket * so)
+{
+ 802d6fc:	defffd04 	addi	sp,sp,-12
+ 802d700:	dfc00215 	stw	ra,8(sp)
+ 802d704:	df000115 	stw	fp,4(sp)
+ 802d708:	df000104 	addi	fp,sp,4
+ 802d70c:	e13fff15 	stw	r4,-4(fp)
+   so->so_req = PRU_ABORT;
+ 802d710:	e0bfff17 	ldw	r2,-4(fp)
+ 802d714:	00c00284 	movi	r3,10
+ 802d718:	10c00715 	stw	r3,28(r2)
+   return(*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0);
+ 802d71c:	e0bfff17 	ldw	r2,-4(fp)
+ 802d720:	10800217 	ldw	r2,8(r2)
+ 802d724:	10800317 	ldw	r2,12(r2)
+ 802d728:	000d883a 	mov	r6,zero
+ 802d72c:	000b883a 	mov	r5,zero
+ 802d730:	e13fff17 	ldw	r4,-4(fp)
+ 802d734:	103ee83a 	callr	r2
+}
+ 802d738:	e037883a 	mov	sp,fp
+ 802d73c:	dfc00117 	ldw	ra,4(sp)
+ 802d740:	df000017 	ldw	fp,0(sp)
+ 802d744:	dec00204 	addi	sp,sp,8
+ 802d748:	f800283a 	ret
+
+0802d74c <soaccept>:
+ */
+
+int
+soaccept(struct socket * so, 
+   struct mbuf *  nam)
+{
+ 802d74c:	defffb04 	addi	sp,sp,-20
+ 802d750:	dfc00415 	stw	ra,16(sp)
+ 802d754:	df000315 	stw	fp,12(sp)
+ 802d758:	df000304 	addi	fp,sp,12
+ 802d75c:	e13ffe15 	stw	r4,-8(fp)
+ 802d760:	e17ffd15 	stw	r5,-12(fp)
+   int   error;
+
+   if ((so->so_state & SS_NOFDREF) == 0)
+ 802d764:	e0bffe17 	ldw	r2,-8(fp)
+ 802d768:	1080088b 	ldhu	r2,34(r2)
+ 802d76c:	10bfffcc 	andi	r2,r2,65535
+ 802d770:	1080004c 	andi	r2,r2,1
+ 802d774:	1000031e 	bne	r2,zero,802d784 <soaccept+0x38>
+      panic("soaccept");
+ 802d778:	01020174 	movhi	r4,2053
+ 802d77c:	212a7804 	addi	r4,r4,-22048
+ 802d780:	80271780 	call	8027178 <panic>
+   so->so_state &= ~SS_NOFDREF;
+ 802d784:	e0bffe17 	ldw	r2,-8(fp)
+ 802d788:	10c0088b 	ldhu	r3,34(r2)
+ 802d78c:	00bfff84 	movi	r2,-2
+ 802d790:	1884703a 	and	r2,r3,r2
+ 802d794:	1007883a 	mov	r3,r2
+ 802d798:	e0bffe17 	ldw	r2,-8(fp)
+ 802d79c:	10c0088d 	sth	r3,34(r2)
+   so->so_req = PRU_ACCEPT;
+ 802d7a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802d7a4:	00c00144 	movi	r3,5
+ 802d7a8:	10c00715 	stw	r3,28(r2)
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+ 802d7ac:	e0bffe17 	ldw	r2,-8(fp)
+ 802d7b0:	10800217 	ldw	r2,8(r2)
+ 802d7b4:	10800317 	ldw	r2,12(r2)
+ 802d7b8:	e1bffd17 	ldw	r6,-12(fp)
+ 802d7bc:	000b883a 	mov	r5,zero
+ 802d7c0:	e13ffe17 	ldw	r4,-8(fp)
+ 802d7c4:	103ee83a 	callr	r2
+ 802d7c8:	e0bfff15 	stw	r2,-4(fp)
+
+   return (error);
+ 802d7cc:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802d7d0:	e037883a 	mov	sp,fp
+ 802d7d4:	dfc00117 	ldw	ra,4(sp)
+ 802d7d8:	df000017 	ldw	fp,0(sp)
+ 802d7dc:	dec00204 	addi	sp,sp,8
+ 802d7e0:	f800283a 	ret
+
+0802d7e4 <soconnect>:
+ */
+
+int
+soconnect(struct socket * so, 
+   struct mbuf *  nam)
+{
+ 802d7e4:	defffb04 	addi	sp,sp,-20
+ 802d7e8:	dfc00415 	stw	ra,16(sp)
+ 802d7ec:	df000315 	stw	fp,12(sp)
+ 802d7f0:	df000304 	addi	fp,sp,12
+ 802d7f4:	e13ffe15 	stw	r4,-8(fp)
+ 802d7f8:	e17ffd15 	stw	r5,-12(fp)
+   int   error;
+
+   if (so->so_options & SO_ACCEPTCONN)
+ 802d7fc:	e0bffe17 	ldw	r2,-8(fp)
+ 802d800:	10800417 	ldw	r2,16(r2)
+ 802d804:	1080008c 	andi	r2,r2,2
+ 802d808:	10000226 	beq	r2,zero,802d814 <soconnect+0x30>
+      return (EOPNOTSUPP);
+ 802d80c:	008017c4 	movi	r2,95
+ 802d810:	00001d06 	br	802d888 <soconnect+0xa4>
+    * If protocol is connection-based, can only connect once.
+    * Otherwise, if connected, try to disconnect first.
+    * This allows user to disconnect by connecting to, e.g.,
+    * a null address.
+    */
+   if (so->so_state & (SS_ISCONNECTED|SS_ISCONNECTING) &&
+ 802d814:	e0bffe17 	ldw	r2,-8(fp)
+ 802d818:	1080088b 	ldhu	r2,34(r2)
+ 802d81c:	10bfffcc 	andi	r2,r2,65535
+ 802d820:	1080018c 	andi	r2,r2,6
+ 802d824:	10000c26 	beq	r2,zero,802d858 <soconnect+0x74>
+       ((so->so_proto->pr_flags & PR_CONNREQUIRED) ||
+ 802d828:	e0bffe17 	ldw	r2,-8(fp)
+ 802d82c:	10800217 	ldw	r2,8(r2)
+ 802d830:	1080010b 	ldhu	r2,4(r2)
+ 802d834:	10bfffcc 	andi	r2,r2,65535
+ 802d838:	1080010c 	andi	r2,r2,4
+   if (so->so_state & (SS_ISCONNECTED|SS_ISCONNECTING) &&
+ 802d83c:	1000031e 	bne	r2,zero,802d84c <soconnect+0x68>
+       (sodisconnect(so) != 0)))
+ 802d840:	e13ffe17 	ldw	r4,-8(fp)
+ 802d844:	802d89c0 	call	802d89c <sodisconnect>
+       ((so->so_proto->pr_flags & PR_CONNREQUIRED) ||
+ 802d848:	10000326 	beq	r2,zero,802d858 <soconnect+0x74>
+   {
+      error = EISCONN;
+ 802d84c:	00801fc4 	movi	r2,127
+ 802d850:	e0bfff15 	stw	r2,-4(fp)
+ 802d854:	00000b06 	br	802d884 <soconnect+0xa0>
+   }
+   else
+   {
+      so->so_req = PRU_CONNECT;
+ 802d858:	e0bffe17 	ldw	r2,-8(fp)
+ 802d85c:	00c00104 	movi	r3,4
+ 802d860:	10c00715 	stw	r3,28(r2)
+      error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+ 802d864:	e0bffe17 	ldw	r2,-8(fp)
+ 802d868:	10800217 	ldw	r2,8(r2)
+ 802d86c:	10800317 	ldw	r2,12(r2)
+ 802d870:	e1bffd17 	ldw	r6,-12(fp)
+ 802d874:	000b883a 	mov	r5,zero
+ 802d878:	e13ffe17 	ldw	r4,-8(fp)
+ 802d87c:	103ee83a 	callr	r2
+ 802d880:	e0bfff15 	stw	r2,-4(fp)
+   }
+   return error;
+ 802d884:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802d888:	e037883a 	mov	sp,fp
+ 802d88c:	dfc00117 	ldw	ra,4(sp)
+ 802d890:	df000017 	ldw	fp,0(sp)
+ 802d894:	dec00204 	addi	sp,sp,8
+ 802d898:	f800283a 	ret
+
+0802d89c <sodisconnect>:
+ * RETURNS: 
+ */
+
+int
+sodisconnect(struct socket * so)
+{
+ 802d89c:	defffc04 	addi	sp,sp,-16
+ 802d8a0:	dfc00315 	stw	ra,12(sp)
+ 802d8a4:	df000215 	stw	fp,8(sp)
+ 802d8a8:	df000204 	addi	fp,sp,8
+ 802d8ac:	e13ffe15 	stw	r4,-8(fp)
+   int   error;
+
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: sodisconnect, so %lx so_state %x\n", so, so->so_state));
+
+   if ((so->so_state & SS_ISCONNECTED) == 0) 
+ 802d8b0:	e0bffe17 	ldw	r2,-8(fp)
+ 802d8b4:	1080088b 	ldhu	r2,34(r2)
+ 802d8b8:	10bfffcc 	andi	r2,r2,65535
+ 802d8bc:	1080008c 	andi	r2,r2,2
+ 802d8c0:	1000031e 	bne	r2,zero,802d8d0 <sodisconnect+0x34>
+   {
+      error = ENOTCONN;
+ 802d8c4:	00802004 	movi	r2,128
+ 802d8c8:	e0bfff15 	stw	r2,-4(fp)
+      goto bad;
+ 802d8cc:	00001306 	br	802d91c <sodisconnect+0x80>
+   }
+   if (so->so_state & SS_ISDISCONNECTING) 
+ 802d8d0:	e0bffe17 	ldw	r2,-8(fp)
+ 802d8d4:	1080088b 	ldhu	r2,34(r2)
+ 802d8d8:	10bfffcc 	andi	r2,r2,65535
+ 802d8dc:	1080020c 	andi	r2,r2,8
+ 802d8e0:	10000326 	beq	r2,zero,802d8f0 <sodisconnect+0x54>
+   {
+      error = EALREADY;
+ 802d8e4:	00801e04 	movi	r2,120
+ 802d8e8:	e0bfff15 	stw	r2,-4(fp)
+      goto bad;
+ 802d8ec:	00000b06 	br	802d91c <sodisconnect+0x80>
+   }
+   so->so_req = PRU_DISCONNECT;
+ 802d8f0:	e0bffe17 	ldw	r2,-8(fp)
+ 802d8f4:	00c00184 	movi	r3,6
+ 802d8f8:	10c00715 	stw	r3,28(r2)
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0);
+ 802d8fc:	e0bffe17 	ldw	r2,-8(fp)
+ 802d900:	10800217 	ldw	r2,8(r2)
+ 802d904:	10800317 	ldw	r2,12(r2)
+ 802d908:	000d883a 	mov	r6,zero
+ 802d90c:	000b883a 	mov	r5,zero
+ 802d910:	e13ffe17 	ldw	r4,-8(fp)
+ 802d914:	103ee83a 	callr	r2
+ 802d918:	e0bfff15 	stw	r2,-4(fp)
+
+bad:
+   return (error);
+ 802d91c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802d920:	e037883a 	mov	sp,fp
+ 802d924:	dfc00117 	ldw	ra,4(sp)
+ 802d928:	df000017 	ldw	fp,0(sp)
+ 802d92c:	dec00204 	addi	sp,sp,8
+ 802d930:	f800283a 	ret
+
+0802d934 <sosend>:
+sosend(struct socket *so, 
+       struct mbuf *nam,      /* sockaddr, if UDP socket, NULL if TCP */
+       char  *data,           /* data to send */
+       int   *data_length,    /* IN/OUT  length of (remaining) data */
+       int   flags)
+{
+ 802d934:	defff204 	addi	sp,sp,-56
+ 802d938:	dfc00d15 	stw	ra,52(sp)
+ 802d93c:	df000c15 	stw	fp,48(sp)
+ 802d940:	df000c04 	addi	fp,sp,48
+ 802d944:	e13ff715 	stw	r4,-36(fp)
+ 802d948:	e17ff615 	stw	r5,-40(fp)
+ 802d94c:	e1bff515 	stw	r6,-44(fp)
+ 802d950:	e1fff415 	stw	r7,-48(fp)
+   struct mbuf *head = (struct mbuf *)NULL;
+ 802d954:	e03fff15 	stw	zero,-4(fp)
+   struct mbuf *m;
+   int   space;
+   int   resid;
+   int   len;
+   int   error = 0;
+ 802d958:	e03ffb15 	stw	zero,-20(fp)
+   int   dontroute;
+   int   first = 1;
+ 802d95c:	00800044 	movi	r2,1
+ 802d960:	e0bffa15 	stw	r2,-24(fp)
+
+   resid = *data_length;
+ 802d964:	e0bff417 	ldw	r2,-48(fp)
+ 802d968:	10800017 	ldw	r2,0(r2)
+ 802d96c:	e0bffc15 	stw	r2,-16(fp)
+    * However, space must be signed, as it might be less than 0
+    * if we over-committed, and we must use a signed comparison
+    * of space and resid.  On the other hand, a negative resid
+    * causes us to loop sending 0-length segments to the protocol.
+    */
+   if (resid < 0)
+ 802d970:	e0bffc17 	ldw	r2,-16(fp)
+ 802d974:	1000020e 	bge	r2,zero,802d980 <sosend+0x4c>
+      return (EINVAL);
+ 802d978:	00800584 	movi	r2,22
+ 802d97c:	00014006 	br	802de80 <sosend+0x54c>
+
+   INET_TRACE (INETM_IO, ("INET:sosend: so %lx resid %d sb_hiwat %d so_state %x\n",
+               so, resid, so->so_snd.sb_hiwat, so->so_state));
+
+   if (sosendallatonce(so) && (resid > (int)so->so_snd.sb_hiwat))
+ 802d980:	e0bff717 	ldw	r2,-36(fp)
+ 802d984:	10800217 	ldw	r2,8(r2)
+ 802d988:	1080010b 	ldhu	r2,4(r2)
+ 802d98c:	10bfffcc 	andi	r2,r2,65535
+ 802d990:	1080004c 	andi	r2,r2,1
+ 802d994:	10000726 	beq	r2,zero,802d9b4 <sosend+0x80>
+ 802d998:	e0bff717 	ldw	r2,-36(fp)
+ 802d99c:	10801317 	ldw	r2,76(r2)
+ 802d9a0:	1007883a 	mov	r3,r2
+ 802d9a4:	e0bffc17 	ldw	r2,-16(fp)
+ 802d9a8:	1880020e 	bge	r3,r2,802d9b4 <sosend+0x80>
+      return (EMSGSIZE);
+ 802d9ac:	00801e84 	movi	r2,122
+ 802d9b0:	00013306 	br	802de80 <sosend+0x54c>
+
+   dontroute = (flags & MSG_DONTROUTE) &&
+ 802d9b4:	e0800217 	ldw	r2,8(fp)
+ 802d9b8:	1080010c 	andi	r2,r2,4
+               ((so->so_options & SO_DONTROUTE) == 0) &&
+ 802d9bc:	10000c26 	beq	r2,zero,802d9f0 <sosend+0xbc>
+ 802d9c0:	e0bff717 	ldw	r2,-36(fp)
+ 802d9c4:	10800417 	ldw	r2,16(r2)
+ 802d9c8:	1080040c 	andi	r2,r2,16
+   dontroute = (flags & MSG_DONTROUTE) &&
+ 802d9cc:	1000081e 	bne	r2,zero,802d9f0 <sosend+0xbc>
+               (so->so_proto->pr_flags & PR_ATOMIC);
+ 802d9d0:	e0bff717 	ldw	r2,-36(fp)
+ 802d9d4:	10800217 	ldw	r2,8(r2)
+ 802d9d8:	1080010b 	ldhu	r2,4(r2)
+ 802d9dc:	10bfffcc 	andi	r2,r2,65535
+ 802d9e0:	1080004c 	andi	r2,r2,1
+               ((so->so_options & SO_DONTROUTE) == 0) &&
+ 802d9e4:	10000226 	beq	r2,zero,802d9f0 <sosend+0xbc>
+ 802d9e8:	00800044 	movi	r2,1
+ 802d9ec:	00000106 	br	802d9f4 <sosend+0xc0>
+ 802d9f0:	0005883a 	mov	r2,zero
+   dontroute = (flags & MSG_DONTROUTE) &&
+ 802d9f4:	e0bff915 	stw	r2,-28(fp)
+
+#define     snderr(errno)     {  error =  errno;   goto  release; }
+
+restart:
+   sblock(&so->so_snd);
+ 802d9f8:	00000406 	br	802da0c <sosend+0xd8>
+ 802d9fc:	e0bff717 	ldw	r2,-36(fp)
+ 802da00:	10801904 	addi	r2,r2,100
+ 802da04:	1009883a 	mov	r4,r2
+ 802da08:	8027a540 	call	8027a54 <tcp_sleep>
+ 802da0c:	e0bff717 	ldw	r2,-36(fp)
+ 802da10:	1080190b 	ldhu	r2,100(r2)
+ 802da14:	10bfffcc 	andi	r2,r2,65535
+ 802da18:	1080004c 	andi	r2,r2,1
+ 802da1c:	103ff71e 	bne	r2,zero,802d9fc <sosend+0xc8>
+ 802da20:	e0bff717 	ldw	r2,-36(fp)
+ 802da24:	1080190b 	ldhu	r2,100(r2)
+ 802da28:	10800054 	ori	r2,r2,1
+ 802da2c:	1007883a 	mov	r3,r2
+ 802da30:	e0bff717 	ldw	r2,-36(fp)
+ 802da34:	10c0190d 	sth	r3,100(r2)
+   do 
+   {
+      if (so->so_error) 
+ 802da38:	e0bff717 	ldw	r2,-36(fp)
+ 802da3c:	10800617 	ldw	r2,24(r2)
+ 802da40:	10000626 	beq	r2,zero,802da5c <sosend+0x128>
+      {
+         error = so->so_error;
+ 802da44:	e0bff717 	ldw	r2,-36(fp)
+ 802da48:	10800617 	ldw	r2,24(r2)
+ 802da4c:	e0bffb15 	stw	r2,-20(fp)
+         so->so_error = 0;          /* ??? */
+ 802da50:	e0bff717 	ldw	r2,-36(fp)
+ 802da54:	10000615 	stw	zero,24(r2)
+         goto release;
+ 802da58:	0000f906 	br	802de40 <sosend+0x50c>
+      }
+      if (so->so_state & SS_CANTSENDMORE)
+ 802da5c:	e0bff717 	ldw	r2,-36(fp)
+ 802da60:	1080088b 	ldhu	r2,34(r2)
+ 802da64:	10bfffcc 	andi	r2,r2,65535
+ 802da68:	1080040c 	andi	r2,r2,16
+ 802da6c:	10000326 	beq	r2,zero,802da7c <sosend+0x148>
+         snderr(EPIPE);
+ 802da70:	00800804 	movi	r2,32
+ 802da74:	e0bffb15 	stw	r2,-20(fp)
+ 802da78:	0000f106 	br	802de40 <sosend+0x50c>
+      if ((so->so_state & SS_ISCONNECTED) == 0) 
+ 802da7c:	e0bff717 	ldw	r2,-36(fp)
+ 802da80:	1080088b 	ldhu	r2,34(r2)
+ 802da84:	10bfffcc 	andi	r2,r2,65535
+ 802da88:	1080008c 	andi	r2,r2,2
+ 802da8c:	10000e1e 	bne	r2,zero,802dac8 <sosend+0x194>
+      {
+         if (so->so_proto->pr_flags & PR_CONNREQUIRED)
+ 802da90:	e0bff717 	ldw	r2,-36(fp)
+ 802da94:	10800217 	ldw	r2,8(r2)
+ 802da98:	1080010b 	ldhu	r2,4(r2)
+ 802da9c:	10bfffcc 	andi	r2,r2,65535
+ 802daa0:	1080010c 	andi	r2,r2,4
+ 802daa4:	10000326 	beq	r2,zero,802dab4 <sosend+0x180>
+            snderr(ENOTCONN);
+ 802daa8:	00802004 	movi	r2,128
+ 802daac:	e0bffb15 	stw	r2,-20(fp)
+ 802dab0:	0000e306 	br	802de40 <sosend+0x50c>
+         if (nam == 0)
+ 802dab4:	e0bff617 	ldw	r2,-40(fp)
+ 802dab8:	1000031e 	bne	r2,zero,802dac8 <sosend+0x194>
+            snderr(EDESTADDRREQ);
+ 802dabc:	00801e44 	movi	r2,121
+ 802dac0:	e0bffb15 	stw	r2,-20(fp)
+ 802dac4:	0000de06 	br	802de40 <sosend+0x50c>
+      }
+      if (flags & MSG_OOB)
+ 802dac8:	e0800217 	ldw	r2,8(fp)
+ 802dacc:	1080004c 	andi	r2,r2,1
+ 802dad0:	10000326 	beq	r2,zero,802dae0 <sosend+0x1ac>
+         space = 1024;
+ 802dad4:	00810004 	movi	r2,1024
+ 802dad8:	e0bffd15 	stw	r2,-12(fp)
+ 802dadc:	00004706 	br	802dbfc <sosend+0x2c8>
+      else 
+      {
+         space = (int)sbspace(&so->so_snd);
+ 802dae0:	e0bff717 	ldw	r2,-36(fp)
+ 802dae4:	10801317 	ldw	r2,76(r2)
+ 802dae8:	1007883a 	mov	r3,r2
+ 802daec:	e0bff717 	ldw	r2,-36(fp)
+ 802daf0:	10801217 	ldw	r2,72(r2)
+ 802daf4:	1885c83a 	sub	r2,r3,r2
+ 802daf8:	10000616 	blt	r2,zero,802db14 <sosend+0x1e0>
+ 802dafc:	e0bff717 	ldw	r2,-36(fp)
+ 802db00:	10c01317 	ldw	r3,76(r2)
+ 802db04:	e0bff717 	ldw	r2,-36(fp)
+ 802db08:	10801217 	ldw	r2,72(r2)
+ 802db0c:	1885c83a 	sub	r2,r3,r2
+ 802db10:	00000106 	br	802db18 <sosend+0x1e4>
+ 802db14:	0005883a 	mov	r2,zero
+ 802db18:	e0bffd15 	stw	r2,-12(fp)
+         if ((sosendallatonce(so) && (space < resid)) ||
+ 802db1c:	e0bff717 	ldw	r2,-36(fp)
+ 802db20:	10800217 	ldw	r2,8(r2)
+ 802db24:	1080010b 	ldhu	r2,4(r2)
+ 802db28:	10bfffcc 	andi	r2,r2,65535
+ 802db2c:	1080004c 	andi	r2,r2,1
+ 802db30:	10000326 	beq	r2,zero,802db40 <sosend+0x20c>
+ 802db34:	e0fffd17 	ldw	r3,-12(fp)
+ 802db38:	e0bffc17 	ldw	r2,-16(fp)
+ 802db3c:	18801216 	blt	r3,r2,802db88 <sosend+0x254>
+ 802db40:	e0bffc17 	ldw	r2,-16(fp)
+ 802db44:	10815e10 	cmplti	r2,r2,1400
+ 802db48:	10002c1e 	bne	r2,zero,802dbfc <sosend+0x2c8>
+             ((resid >= CLBYTES) && (space < CLBYTES) &&
+ 802db4c:	e0bffd17 	ldw	r2,-12(fp)
+ 802db50:	10815e08 	cmpgei	r2,r2,1400
+ 802db54:	1000291e 	bne	r2,zero,802dbfc <sosend+0x2c8>
+              (so->so_snd.sb_cc >= CLBYTES) &&
+ 802db58:	e0bff717 	ldw	r2,-36(fp)
+ 802db5c:	10801217 	ldw	r2,72(r2)
+             ((resid >= CLBYTES) && (space < CLBYTES) &&
+ 802db60:	10815e30 	cmpltui	r2,r2,1400
+ 802db64:	1000251e 	bne	r2,zero,802dbfc <sosend+0x2c8>
+              ((so->so_state & SS_NBIO) == 0) &&
+ 802db68:	e0bff717 	ldw	r2,-36(fp)
+ 802db6c:	1080088b 	ldhu	r2,34(r2)
+ 802db70:	10bfffcc 	andi	r2,r2,65535
+ 802db74:	1080400c 	andi	r2,r2,256
+              (so->so_snd.sb_cc >= CLBYTES) &&
+ 802db78:	1000201e 	bne	r2,zero,802dbfc <sosend+0x2c8>
+              ((flags & MSG_DONTWAIT) == 0)))
+ 802db7c:	e0800217 	ldw	r2,8(fp)
+ 802db80:	1080080c 	andi	r2,r2,32
+              ((so->so_state & SS_NBIO) == 0) &&
+ 802db84:	10001d1e 	bne	r2,zero,802dbfc <sosend+0x2c8>
+         {
+            if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT))
+ 802db88:	e0bff717 	ldw	r2,-36(fp)
+ 802db8c:	1080088b 	ldhu	r2,34(r2)
+ 802db90:	10bfffcc 	andi	r2,r2,65535
+ 802db94:	1080400c 	andi	r2,r2,256
+ 802db98:	1000031e 	bne	r2,zero,802dba8 <sosend+0x274>
+ 802db9c:	e0800217 	ldw	r2,8(fp)
+ 802dba0:	1080080c 	andi	r2,r2,32
+ 802dba4:	10000526 	beq	r2,zero,802dbbc <sosend+0x288>
+            {
+               if (first)
+ 802dba8:	e0bffa17 	ldw	r2,-24(fp)
+ 802dbac:	10009d26 	beq	r2,zero,802de24 <sosend+0x4f0>
+                  error = EWOULDBLOCK;
+ 802dbb0:	008002c4 	movi	r2,11
+ 802dbb4:	e0bffb15 	stw	r2,-20(fp)
+               goto release;
+ 802dbb8:	00009a06 	br	802de24 <sosend+0x4f0>
+            }
+            sbunlock(&so->so_snd);
+ 802dbbc:	e0bff717 	ldw	r2,-36(fp)
+ 802dbc0:	10c0190b 	ldhu	r3,100(r2)
+ 802dbc4:	00bfff84 	movi	r2,-2
+ 802dbc8:	1884703a 	and	r2,r3,r2
+ 802dbcc:	1007883a 	mov	r3,r2
+ 802dbd0:	e0bff717 	ldw	r2,-36(fp)
+ 802dbd4:	10c0190d 	sth	r3,100(r2)
+ 802dbd8:	e0bff717 	ldw	r2,-36(fp)
+ 802dbdc:	10801904 	addi	r2,r2,100
+ 802dbe0:	1009883a 	mov	r4,r2
+ 802dbe4:	8027ba00 	call	8027ba0 <tcp_wakeup>
+            sbwait(&so->so_snd);
+ 802dbe8:	e0bff717 	ldw	r2,-36(fp)
+ 802dbec:	10801204 	addi	r2,r2,72
+ 802dbf0:	1009883a 	mov	r4,r2
+ 802dbf4:	802f8e00 	call	802f8e0 <sbwait>
+            goto restart;
+ 802dbf8:	003f7f06 	br	802d9f8 <sosend+0xc4>
+         }
+      }
+      if ( space <= 0 ) 
+ 802dbfc:	e0bffd17 	ldw	r2,-12(fp)
+ 802dc00:	00805e16 	blt	zero,r2,802dd7c <sosend+0x448>
+      {
+         /* no space in socket send buffer - see if we can wait */
+         if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT))
+ 802dc04:	e0bff717 	ldw	r2,-36(fp)
+ 802dc08:	1080088b 	ldhu	r2,34(r2)
+ 802dc0c:	10bfffcc 	andi	r2,r2,65535
+ 802dc10:	1080400c 	andi	r2,r2,256
+ 802dc14:	1000031e 	bne	r2,zero,802dc24 <sosend+0x2f0>
+ 802dc18:	e0800217 	ldw	r2,8(fp)
+ 802dc1c:	1080080c 	andi	r2,r2,32
+ 802dc20:	10000526 	beq	r2,zero,802dc38 <sosend+0x304>
+         {
+            if (first)     /* report first error */
+ 802dc24:	e0bffa17 	ldw	r2,-24(fp)
+ 802dc28:	10008026 	beq	r2,zero,802de2c <sosend+0x4f8>
+               error = EWOULDBLOCK;
+ 802dc2c:	008002c4 	movi	r2,11
+ 802dc30:	e0bffb15 	stw	r2,-20(fp)
+            goto release;
+ 802dc34:	00007d06 	br	802de2c <sosend+0x4f8>
+         }
+         /* If blocking socket, let someone else run */
+         sbunlock(&so->so_snd);
+ 802dc38:	e0bff717 	ldw	r2,-36(fp)
+ 802dc3c:	10c0190b 	ldhu	r3,100(r2)
+ 802dc40:	00bfff84 	movi	r2,-2
+ 802dc44:	1884703a 	and	r2,r3,r2
+ 802dc48:	1007883a 	mov	r3,r2
+ 802dc4c:	e0bff717 	ldw	r2,-36(fp)
+ 802dc50:	10c0190d 	sth	r3,100(r2)
+ 802dc54:	e0bff717 	ldw	r2,-36(fp)
+ 802dc58:	10801904 	addi	r2,r2,100
+ 802dc5c:	1009883a 	mov	r4,r2
+ 802dc60:	8027ba00 	call	8027ba0 <tcp_wakeup>
+         sbwait(&so->so_snd);
+ 802dc64:	e0bff717 	ldw	r2,-36(fp)
+ 802dc68:	10801204 	addi	r2,r2,72
+ 802dc6c:	1009883a 	mov	r4,r2
+ 802dc70:	802f8e00 	call	802f8e0 <sbwait>
+         goto restart;
+ 802dc74:	003f6006 	br	802d9f8 <sosend+0xc4>
+      }
+
+      while (space > 0) 
+      {
+         len = resid;
+ 802dc78:	e0bffc17 	ldw	r2,-16(fp)
+ 802dc7c:	e0bff815 	stw	r2,-32(fp)
+         if ( so->so_type == SOCK_STREAM )
+ 802dc80:	e0bff717 	ldw	r2,-36(fp)
+ 802dc84:	10800983 	ldbu	r2,38(r2)
+ 802dc88:	10803fcc 	andi	r2,r2,255
+ 802dc8c:	1080201c 	xori	r2,r2,128
+ 802dc90:	10bfe004 	addi	r2,r2,-128
+ 802dc94:	10800058 	cmpnei	r2,r2,1
+ 802dc98:	1000171e 	bne	r2,zero,802dcf8 <sosend+0x3c4>
+         {
+            m = m_getwithdata(MT_TXDATA, len);
+ 802dc9c:	e17ff817 	ldw	r5,-32(fp)
+ 802dca0:	01000084 	movi	r4,2
+ 802dca4:	8029a700 	call	8029a70 <m_getnbuf>
+ 802dca8:	e0bffe15 	stw	r2,-8(fp)
+            if (!m)   
+ 802dcac:	e0bffe17 	ldw	r2,-8(fp)
+ 802dcb0:	1000031e 	bne	r2,zero,802dcc0 <sosend+0x38c>
+               snderr(ENOBUFS);
+ 802dcb4:	00801a44 	movi	r2,105
+ 802dcb8:	e0bffb15 	stw	r2,-20(fp)
+ 802dcbc:	00006006 	br	802de40 <sosend+0x50c>
+            MEMCPY(m->m_data, data, len);
+ 802dcc0:	e0bffe17 	ldw	r2,-8(fp)
+ 802dcc4:	10800317 	ldw	r2,12(r2)
+ 802dcc8:	e0fff817 	ldw	r3,-32(fp)
+ 802dccc:	180d883a 	mov	r6,r3
+ 802dcd0:	e17ff517 	ldw	r5,-44(fp)
+ 802dcd4:	1009883a 	mov	r4,r2
+ 802dcd8:	80086b80 	call	80086b8 <memcpy>
+            so->so_snd.sb_flags |= SB_MBCOMP;   /* allow compression */
+ 802dcdc:	e0bff717 	ldw	r2,-36(fp)
+ 802dce0:	1080190b 	ldhu	r2,100(r2)
+ 802dce4:	10802014 	ori	r2,r2,128
+ 802dce8:	1007883a 	mov	r3,r2
+ 802dcec:	e0bff717 	ldw	r2,-36(fp)
+ 802dcf0:	10c0190d 	sth	r3,100(r2)
+ 802dcf4:	00000706 	br	802dd14 <sosend+0x3e0>
+         }
+         else
+         {
+            m = m_get (M_WAIT, MT_TXDATA);
+ 802dcf8:	000b883a 	mov	r5,zero
+ 802dcfc:	01000084 	movi	r4,2
+ 802dd00:	8029a700 	call	8029a70 <m_getnbuf>
+ 802dd04:	e0bffe15 	stw	r2,-8(fp)
+            m->m_data = data;
+ 802dd08:	e0bffe17 	ldw	r2,-8(fp)
+ 802dd0c:	e0fff517 	ldw	r3,-44(fp)
+ 802dd10:	10c00315 	stw	r3,12(r2)
+         }
+         INET_TRACE (INETM_IO,
+          ("sosend:got %d bytes so %lx mlen %d, off %d mtod %x\n",
+             len, so, m->m_len, m->m_off, mtod (m, caddr_t)));
+
+         *data_length -= len;
+ 802dd14:	e0bff417 	ldw	r2,-48(fp)
+ 802dd18:	10c00017 	ldw	r3,0(r2)
+ 802dd1c:	e0bff817 	ldw	r2,-32(fp)
+ 802dd20:	1887c83a 	sub	r3,r3,r2
+ 802dd24:	e0bff417 	ldw	r2,-48(fp)
+ 802dd28:	10c00015 	stw	r3,0(r2)
+         resid -= len;
+ 802dd2c:	e0fffc17 	ldw	r3,-16(fp)
+ 802dd30:	e0bff817 	ldw	r2,-32(fp)
+ 802dd34:	1885c83a 	sub	r2,r3,r2
+ 802dd38:	e0bffc15 	stw	r2,-16(fp)
+         data += len;
+ 802dd3c:	e0bff817 	ldw	r2,-32(fp)
+ 802dd40:	e0fff517 	ldw	r3,-44(fp)
+ 802dd44:	1885883a 	add	r2,r3,r2
+ 802dd48:	e0bff515 	stw	r2,-44(fp)
+         m->m_len = len;
+ 802dd4c:	e0fff817 	ldw	r3,-32(fp)
+ 802dd50:	e0bffe17 	ldw	r2,-8(fp)
+ 802dd54:	10c00215 	stw	r3,8(r2)
+         if (head == (struct mbuf *)NULL)
+ 802dd58:	e0bfff17 	ldw	r2,-4(fp)
+ 802dd5c:	1000021e 	bne	r2,zero,802dd68 <sosend+0x434>
+            head = m;
+ 802dd60:	e0bffe17 	ldw	r2,-8(fp)
+ 802dd64:	e0bfff15 	stw	r2,-4(fp)
+         if (error)
+ 802dd68:	e0bffb17 	ldw	r2,-20(fp)
+ 802dd6c:	1000311e 	bne	r2,zero,802de34 <sosend+0x500>
+            goto release;
+         if (*data_length <= 0)
+ 802dd70:	e0bff417 	ldw	r2,-48(fp)
+ 802dd74:	10800017 	ldw	r2,0(r2)
+ 802dd78:	0080030e 	bge	zero,r2,802dd88 <sosend+0x454>
+      while (space > 0) 
+ 802dd7c:	e0bffd17 	ldw	r2,-12(fp)
+ 802dd80:	00bfbd16 	blt	zero,r2,802dc78 <sosend+0x344>
+ 802dd84:	00000106 	br	802dd8c <sosend+0x458>
+            break;
+ 802dd88:	0001883a 	nop
+      }
+
+      if (dontroute)
+ 802dd8c:	e0bff917 	ldw	r2,-28(fp)
+ 802dd90:	10000526 	beq	r2,zero,802dda8 <sosend+0x474>
+         so->so_options |= SO_DONTROUTE;
+ 802dd94:	e0bff717 	ldw	r2,-36(fp)
+ 802dd98:	10800417 	ldw	r2,16(r2)
+ 802dd9c:	10c00414 	ori	r3,r2,16
+ 802dda0:	e0bff717 	ldw	r2,-36(fp)
+ 802dda4:	10c00415 	stw	r3,16(r2)
+
+      so->so_req = (flags & MSG_OOB) ? PRU_SENDOOB : PRU_SEND;
+ 802dda8:	e0800217 	ldw	r2,8(fp)
+ 802ddac:	1080004c 	andi	r2,r2,1
+ 802ddb0:	10000226 	beq	r2,zero,802ddbc <sosend+0x488>
+ 802ddb4:	00800384 	movi	r2,14
+ 802ddb8:	00000106 	br	802ddc0 <sosend+0x48c>
+ 802ddbc:	00800244 	movi	r2,9
+ 802ddc0:	e0fff717 	ldw	r3,-36(fp)
+ 802ddc4:	18800715 	stw	r2,28(r3)
+      error = (*so->so_proto->pr_usrreq)(so, head, nam);
+ 802ddc8:	e0bff717 	ldw	r2,-36(fp)
+ 802ddcc:	10800217 	ldw	r2,8(r2)
+ 802ddd0:	10800317 	ldw	r2,12(r2)
+ 802ddd4:	e1bff617 	ldw	r6,-40(fp)
+ 802ddd8:	e17fff17 	ldw	r5,-4(fp)
+ 802dddc:	e13ff717 	ldw	r4,-36(fp)
+ 802dde0:	103ee83a 	callr	r2
+ 802dde4:	e0bffb15 	stw	r2,-20(fp)
+
+      if (dontroute)
+ 802dde8:	e0bff917 	ldw	r2,-28(fp)
+ 802ddec:	10000626 	beq	r2,zero,802de08 <sosend+0x4d4>
+         so->so_options &= ~SO_DONTROUTE;
+ 802ddf0:	e0bff717 	ldw	r2,-36(fp)
+ 802ddf4:	10c00417 	ldw	r3,16(r2)
+ 802ddf8:	00bffbc4 	movi	r2,-17
+ 802ddfc:	1886703a 	and	r3,r3,r2
+ 802de00:	e0bff717 	ldw	r2,-36(fp)
+ 802de04:	10c00415 	stw	r3,16(r2)
+
+      head = (struct mbuf *)NULL;
+ 802de08:	e03fff15 	stw	zero,-4(fp)
+      first = 0;
+ 802de0c:	e03ffa15 	stw	zero,-24(fp)
+   } while ((resid != 0) && (error == 0));
+ 802de10:	e0bffc17 	ldw	r2,-16(fp)
+ 802de14:	10000926 	beq	r2,zero,802de3c <sosend+0x508>
+ 802de18:	e0bffb17 	ldw	r2,-20(fp)
+ 802de1c:	103f0626 	beq	r2,zero,802da38 <sosend+0x104>
+
+release:
+ 802de20:	00000606 	br	802de3c <sosend+0x508>
+               goto release;
+ 802de24:	0001883a 	nop
+ 802de28:	00000506 	br	802de40 <sosend+0x50c>
+            goto release;
+ 802de2c:	0001883a 	nop
+ 802de30:	00000306 	br	802de40 <sosend+0x50c>
+            goto release;
+ 802de34:	0001883a 	nop
+ 802de38:	00000106 	br	802de40 <sosend+0x50c>
+release:
+ 802de3c:	0001883a 	nop
+   sbunlock(&so->so_snd);  
+ 802de40:	e0bff717 	ldw	r2,-36(fp)
+ 802de44:	10c0190b 	ldhu	r3,100(r2)
+ 802de48:	00bfff84 	movi	r2,-2
+ 802de4c:	1884703a 	and	r2,r3,r2
+ 802de50:	1007883a 	mov	r3,r2
+ 802de54:	e0bff717 	ldw	r2,-36(fp)
+ 802de58:	10c0190d 	sth	r3,100(r2)
+ 802de5c:	e0bff717 	ldw	r2,-36(fp)
+ 802de60:	10801904 	addi	r2,r2,100
+ 802de64:	1009883a 	mov	r4,r2
+ 802de68:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   if (head)
+ 802de6c:	e0bfff17 	ldw	r2,-4(fp)
+ 802de70:	10000226 	beq	r2,zero,802de7c <sosend+0x548>
+      m_freem(head);
+ 802de74:	e13fff17 	ldw	r4,-4(fp)
+ 802de78:	8029cfc0 	call	8029cfc <m_freem>
+   return error;
+ 802de7c:	e0bffb17 	ldw	r2,-20(fp)
+}
+ 802de80:	e037883a 	mov	sp,fp
+ 802de84:	dfc00117 	ldw	ra,4(sp)
+ 802de88:	df000017 	ldw	fp,0(sp)
+ 802de8c:	dec00204 	addi	sp,sp,8
+ 802de90:	f800283a 	ret
+
+0802de94 <soreceive>:
+soreceive(struct socket * so, 
+   struct mbuf **aname,
+   char * data,
+   int * datalen,
+   int   flags)
+{
+ 802de94:	defff204 	addi	sp,sp,-56
+ 802de98:	dfc00d15 	stw	ra,52(sp)
+ 802de9c:	df000c15 	stw	fp,48(sp)
+ 802dea0:	df000c04 	addi	fp,sp,48
+ 802dea4:	e13ff715 	stw	r4,-36(fp)
+ 802dea8:	e17ff615 	stw	r5,-40(fp)
+ 802deac:	e1bff515 	stw	r6,-44(fp)
+ 802deb0:	e1fff415 	stw	r7,-48(fp)
+   struct mbuf *  m;
+   int   len;
+   int   error =  0;
+ 802deb4:	e03ffd15 	stw	zero,-12(fp)
+   int   offset;
+   struct protosw *  pr =  so->so_proto;
+ 802deb8:	e0bff717 	ldw	r2,-36(fp)
+ 802debc:	10800217 	ldw	r2,8(r2)
+ 802dec0:	e0bff915 	stw	r2,-28(fp)
+   struct mbuf *  nextrecord;
+   int   moff;
+   int   lflags;
+
+   if (aname)
+ 802dec4:	e0bff617 	ldw	r2,-40(fp)
+ 802dec8:	10000226 	beq	r2,zero,802ded4 <soreceive+0x40>
+      *aname = 0;
+ 802decc:	e0bff617 	ldw	r2,-40(fp)
+ 802ded0:	10000015 	stw	zero,0(r2)
+   if (flags & MSG_OOB) 
+ 802ded4:	e0800217 	ldw	r2,8(fp)
+ 802ded8:	1080004c 	andi	r2,r2,1
+ 802dedc:	10004126 	beq	r2,zero,802dfe4 <soreceive+0x150>
+   {
+      m = m_get (M_WAIT, MT_RXDATA);
+ 802dee0:	000b883a 	mov	r5,zero
+ 802dee4:	01000044 	movi	r4,1
+ 802dee8:	8029a700 	call	8029a70 <m_getnbuf>
+ 802deec:	e0bfff15 	stw	r2,-4(fp)
+      if (m == NULL)
+ 802def0:	e0bfff17 	ldw	r2,-4(fp)
+ 802def4:	1000021e 	bne	r2,zero,802df00 <soreceive+0x6c>
+         return ENOBUFS;
+ 802def8:	00801a44 	movi	r2,105
+ 802defc:	0001b606 	br	802e5d8 <soreceive+0x744>
+      lflags = flags & MSG_PEEK;
+ 802df00:	e0800217 	ldw	r2,8(fp)
+ 802df04:	1080008c 	andi	r2,r2,2
+ 802df08:	e0bff815 	stw	r2,-32(fp)
+
+      so->so_req = PRU_RCVOOB;
+ 802df0c:	e0bff717 	ldw	r2,-36(fp)
+ 802df10:	00c00344 	movi	r3,13
+ 802df14:	10c00715 	stw	r3,28(r2)
+      error = (*pr->pr_usrreq)(so, m, LONG2MBUF((long)lflags));
+ 802df18:	e0bff917 	ldw	r2,-28(fp)
+ 802df1c:	10800317 	ldw	r2,12(r2)
+ 802df20:	e0fff817 	ldw	r3,-32(fp)
+ 802df24:	180d883a 	mov	r6,r3
+ 802df28:	e17fff17 	ldw	r5,-4(fp)
+ 802df2c:	e13ff717 	ldw	r4,-36(fp)
+ 802df30:	103ee83a 	callr	r2
+ 802df34:	e0bffd15 	stw	r2,-12(fp)
+      if (error == 0)
+ 802df38:	e0bffd17 	ldw	r2,-12(fp)
+ 802df3c:	1000231e 	bne	r2,zero,802dfcc <soreceive+0x138>
+      {
+         do 
+         {
+            len = *datalen;
+ 802df40:	e0bff417 	ldw	r2,-48(fp)
+ 802df44:	10800017 	ldw	r2,0(r2)
+ 802df48:	e0bffe15 	stw	r2,-8(fp)
+            if (len > (int)m->m_len)
+ 802df4c:	e0bfff17 	ldw	r2,-4(fp)
+ 802df50:	10800217 	ldw	r2,8(r2)
+ 802df54:	1007883a 	mov	r3,r2
+ 802df58:	e0bffe17 	ldw	r2,-8(fp)
+ 802df5c:	1880030e 	bge	r3,r2,802df6c <soreceive+0xd8>
+               len = m->m_len;
+ 802df60:	e0bfff17 	ldw	r2,-4(fp)
+ 802df64:	10800217 	ldw	r2,8(r2)
+ 802df68:	e0bffe15 	stw	r2,-8(fp)
+
+            MEMCPY(data, mtod(m, char*), len);
+ 802df6c:	e0bfff17 	ldw	r2,-4(fp)
+ 802df70:	10800317 	ldw	r2,12(r2)
+ 802df74:	e0fffe17 	ldw	r3,-8(fp)
+ 802df78:	180d883a 	mov	r6,r3
+ 802df7c:	100b883a 	mov	r5,r2
+ 802df80:	e13ff517 	ldw	r4,-44(fp)
+ 802df84:	80086b80 	call	80086b8 <memcpy>
+            data += len;
+ 802df88:	e0bffe17 	ldw	r2,-8(fp)
+ 802df8c:	e0fff517 	ldw	r3,-44(fp)
+ 802df90:	1885883a 	add	r2,r3,r2
+ 802df94:	e0bff515 	stw	r2,-44(fp)
+            *datalen = len;
+ 802df98:	e0bff417 	ldw	r2,-48(fp)
+ 802df9c:	e0fffe17 	ldw	r3,-8(fp)
+ 802dfa0:	10c00015 	stw	r3,0(r2)
+            m = m_free(m);
+ 802dfa4:	e13fff17 	ldw	r4,-4(fp)
+ 802dfa8:	8029bf80 	call	8029bf8 <m_free>
+ 802dfac:	e0bfff15 	stw	r2,-4(fp)
+         } while (*datalen && (error == 0) && m);
+ 802dfb0:	e0bff417 	ldw	r2,-48(fp)
+ 802dfb4:	10800017 	ldw	r2,0(r2)
+ 802dfb8:	10000426 	beq	r2,zero,802dfcc <soreceive+0x138>
+ 802dfbc:	e0bffd17 	ldw	r2,-12(fp)
+ 802dfc0:	1000021e 	bne	r2,zero,802dfcc <soreceive+0x138>
+ 802dfc4:	e0bfff17 	ldw	r2,-4(fp)
+ 802dfc8:	103fdd1e 	bne	r2,zero,802df40 <soreceive+0xac>
+      }
+
+      if (m)
+ 802dfcc:	e0bfff17 	ldw	r2,-4(fp)
+ 802dfd0:	10000226 	beq	r2,zero,802dfdc <soreceive+0x148>
+         m_freem(m);
+ 802dfd4:	e13fff17 	ldw	r4,-4(fp)
+ 802dfd8:	8029cfc0 	call	8029cfc <m_freem>
+      return (error);
+ 802dfdc:	e0bffd17 	ldw	r2,-12(fp)
+ 802dfe0:	00017d06 	br	802e5d8 <soreceive+0x744>
+   }
+
+restart:
+ 802dfe4:	0001883a 	nop
+   sblock (&so->so_rcv);
+ 802dfe8:	00000406 	br	802dffc <soreceive+0x168>
+ 802dfec:	e0bff717 	ldw	r2,-36(fp)
+ 802dff0:	10801104 	addi	r2,r2,68
+ 802dff4:	1009883a 	mov	r4,r2
+ 802dff8:	8027a540 	call	8027a54 <tcp_sleep>
+ 802dffc:	e0bff717 	ldw	r2,-36(fp)
+ 802e000:	1080110b 	ldhu	r2,68(r2)
+ 802e004:	10bfffcc 	andi	r2,r2,65535
+ 802e008:	1080004c 	andi	r2,r2,1
+ 802e00c:	103ff71e 	bne	r2,zero,802dfec <soreceive+0x158>
+ 802e010:	e0bff717 	ldw	r2,-36(fp)
+ 802e014:	1080110b 	ldhu	r2,68(r2)
+ 802e018:	10800054 	ori	r2,r2,1
+ 802e01c:	1007883a 	mov	r3,r2
+ 802e020:	e0bff717 	ldw	r2,-36(fp)
+ 802e024:	10c0110d 	sth	r3,68(r2)
+   INET_TRACE (INETM_IO,
+    ("INET:soreceive sbcc %d soerror %d so_state %d *datalen %d\n",
+    so->so_rcv.sb_cc, so->so_error, so->so_state, *datalen));
+
+   /* If no data is ready, see if we should wait or return */
+   if (so->so_rcv.sb_cc == 0) 
+ 802e028:	e0bff717 	ldw	r2,-36(fp)
+ 802e02c:	10800a17 	ldw	r2,40(r2)
+ 802e030:	10003a1e 	bne	r2,zero,802e11c <soreceive+0x288>
+   {
+      if (so->so_error) 
+ 802e034:	e0bff717 	ldw	r2,-36(fp)
+ 802e038:	10800617 	ldw	r2,24(r2)
+ 802e03c:	10000626 	beq	r2,zero,802e058 <soreceive+0x1c4>
+      {
+         error = so->so_error;
+ 802e040:	e0bff717 	ldw	r2,-36(fp)
+ 802e044:	10800617 	ldw	r2,24(r2)
+ 802e048:	e0bffd15 	stw	r2,-12(fp)
+         so->so_error = 0;
+ 802e04c:	e0bff717 	ldw	r2,-36(fp)
+ 802e050:	10000615 	stw	zero,24(r2)
+         goto release;
+ 802e054:	00015406 	br	802e5a8 <soreceive+0x714>
+      }
+      if (so->so_state & SS_CANTRCVMORE)
+ 802e058:	e0bff717 	ldw	r2,-36(fp)
+ 802e05c:	1080088b 	ldhu	r2,34(r2)
+ 802e060:	10bfffcc 	andi	r2,r2,65535
+ 802e064:	1080080c 	andi	r2,r2,32
+ 802e068:	10014a1e 	bne	r2,zero,802e594 <soreceive+0x700>
+         goto release;
+      if ((so->so_state & SS_ISCONNECTED) == 0 &&
+ 802e06c:	e0bff717 	ldw	r2,-36(fp)
+ 802e070:	1080088b 	ldhu	r2,34(r2)
+ 802e074:	10bfffcc 	andi	r2,r2,65535
+ 802e078:	1080008c 	andi	r2,r2,2
+ 802e07c:	1000091e 	bne	r2,zero,802e0a4 <soreceive+0x210>
+          (so->so_proto->pr_flags & PR_CONNREQUIRED)) 
+ 802e080:	e0bff717 	ldw	r2,-36(fp)
+ 802e084:	10800217 	ldw	r2,8(r2)
+ 802e088:	1080010b 	ldhu	r2,4(r2)
+ 802e08c:	10bfffcc 	andi	r2,r2,65535
+ 802e090:	1080010c 	andi	r2,r2,4
+      if ((so->so_state & SS_ISCONNECTED) == 0 &&
+ 802e094:	10000326 	beq	r2,zero,802e0a4 <soreceive+0x210>
+      {
+         error = ENOTCONN;
+ 802e098:	00802004 	movi	r2,128
+ 802e09c:	e0bffd15 	stw	r2,-12(fp)
+         goto release;
+ 802e0a0:	00014106 	br	802e5a8 <soreceive+0x714>
+      }
+      if (*datalen == 0)
+ 802e0a4:	e0bff417 	ldw	r2,-48(fp)
+ 802e0a8:	10800017 	ldw	r2,0(r2)
+ 802e0ac:	10013b26 	beq	r2,zero,802e59c <soreceive+0x708>
+         goto release;
+      if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT)) 
+ 802e0b0:	e0bff717 	ldw	r2,-36(fp)
+ 802e0b4:	1080088b 	ldhu	r2,34(r2)
+ 802e0b8:	10bfffcc 	andi	r2,r2,65535
+ 802e0bc:	1080400c 	andi	r2,r2,256
+ 802e0c0:	1000031e 	bne	r2,zero,802e0d0 <soreceive+0x23c>
+ 802e0c4:	e0800217 	ldw	r2,8(fp)
+ 802e0c8:	1080080c 	andi	r2,r2,32
+ 802e0cc:	10000326 	beq	r2,zero,802e0dc <soreceive+0x248>
+      {
+         error = EWOULDBLOCK;
+ 802e0d0:	008002c4 	movi	r2,11
+ 802e0d4:	e0bffd15 	stw	r2,-12(fp)
+         goto release;
+ 802e0d8:	00013306 	br	802e5a8 <soreceive+0x714>
+      }
+      sbunlock(&so->so_rcv);
+ 802e0dc:	e0bff717 	ldw	r2,-36(fp)
+ 802e0e0:	10c0110b 	ldhu	r3,68(r2)
+ 802e0e4:	00bfff84 	movi	r2,-2
+ 802e0e8:	1884703a 	and	r2,r3,r2
+ 802e0ec:	1007883a 	mov	r3,r2
+ 802e0f0:	e0bff717 	ldw	r2,-36(fp)
+ 802e0f4:	10c0110d 	sth	r3,68(r2)
+ 802e0f8:	e0bff717 	ldw	r2,-36(fp)
+ 802e0fc:	10801104 	addi	r2,r2,68
+ 802e100:	1009883a 	mov	r4,r2
+ 802e104:	8027ba00 	call	8027ba0 <tcp_wakeup>
+      sbwait(&so->so_rcv);
+ 802e108:	e0bff717 	ldw	r2,-36(fp)
+ 802e10c:	10800a04 	addi	r2,r2,40
+ 802e110:	1009883a 	mov	r4,r2
+ 802e114:	802f8e00 	call	802f8e0 <sbwait>
+      goto restart;
+ 802e118:	003fb306 	br	802dfe8 <soreceive+0x154>
+   }
+   m = so->so_rcv.sb_mb;
+ 802e11c:	e0bff717 	ldw	r2,-36(fp)
+ 802e120:	10801017 	ldw	r2,64(r2)
+ 802e124:	e0bfff15 	stw	r2,-4(fp)
+   if (m == 0)
+ 802e128:	e0bfff17 	ldw	r2,-4(fp)
+ 802e12c:	1000031e 	bne	r2,zero,802e13c <soreceive+0x2a8>
+      panic("sorecv 1");
+ 802e130:	01020174 	movhi	r4,2053
+ 802e134:	212a7b04 	addi	r4,r4,-22036
+ 802e138:	80271780 	call	8027178 <panic>
+   nextrecord = m->m_act;
+ 802e13c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e140:	10800717 	ldw	r2,28(r2)
+ 802e144:	e0bffb15 	stw	r2,-20(fp)
+   if (pr->pr_flags & PR_ADDR) 
+ 802e148:	e0bff917 	ldw	r2,-28(fp)
+ 802e14c:	1080010b 	ldhu	r2,4(r2)
+ 802e150:	10bfffcc 	andi	r2,r2,65535
+ 802e154:	1080008c 	andi	r2,r2,2
+ 802e158:	10004226 	beq	r2,zero,802e264 <soreceive+0x3d0>
+   {
+      if (m->m_type != MT_SONAME) 
+ 802e15c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e160:	10800817 	ldw	r2,32(r2)
+ 802e164:	10800260 	cmpeqi	r2,r2,9
+ 802e168:	1000091e 	bne	r2,zero,802e190 <soreceive+0x2fc>
+      {
+         dprintf ("sorecv:type %d not nam", m->m_type);
+ 802e16c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e170:	10800817 	ldw	r2,32(r2)
+ 802e174:	100b883a 	mov	r5,r2
+ 802e178:	01020174 	movhi	r4,2053
+ 802e17c:	212a7e04 	addi	r4,r4,-22024
+ 802e180:	8002c780 	call	8002c78 <printf>
+         panic("sorecv 2");
+ 802e184:	01020174 	movhi	r4,2053
+ 802e188:	212a8404 	addi	r4,r4,-22000
+ 802e18c:	80271780 	call	8027178 <panic>
+      }
+      if (flags & MSG_PEEK) 
+ 802e190:	e0800217 	ldw	r2,8(fp)
+ 802e194:	1080008c 	andi	r2,r2,2
+ 802e198:	10000f26 	beq	r2,zero,802e1d8 <soreceive+0x344>
+      {
+         if (aname)
+ 802e19c:	e0bff617 	ldw	r2,-40(fp)
+ 802e1a0:	10000926 	beq	r2,zero,802e1c8 <soreceive+0x334>
+            *aname = m_copy (m, 0, m->m_len);
+ 802e1a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802e1a8:	10800217 	ldw	r2,8(r2)
+ 802e1ac:	100d883a 	mov	r6,r2
+ 802e1b0:	000b883a 	mov	r5,zero
+ 802e1b4:	e13fff17 	ldw	r4,-4(fp)
+ 802e1b8:	8029d400 	call	8029d40 <m_copy>
+ 802e1bc:	1007883a 	mov	r3,r2
+ 802e1c0:	e0bff617 	ldw	r2,-40(fp)
+ 802e1c4:	10c00015 	stw	r3,0(r2)
+         m = m->m_next;
+ 802e1c8:	e0bfff17 	ldw	r2,-4(fp)
+ 802e1cc:	10800617 	ldw	r2,24(r2)
+ 802e1d0:	e0bfff15 	stw	r2,-4(fp)
+ 802e1d4:	00002306 	br	802e264 <soreceive+0x3d0>
+      } else 
+      {
+         sbfree (&so->so_rcv, m);
+ 802e1d8:	e0bff717 	ldw	r2,-36(fp)
+ 802e1dc:	10c00a17 	ldw	r3,40(r2)
+ 802e1e0:	e0bfff17 	ldw	r2,-4(fp)
+ 802e1e4:	10800217 	ldw	r2,8(r2)
+ 802e1e8:	1887c83a 	sub	r3,r3,r2
+ 802e1ec:	e0bff717 	ldw	r2,-36(fp)
+ 802e1f0:	10c00a15 	stw	r3,40(r2)
+         if (aname) 
+ 802e1f4:	e0bff617 	ldw	r2,-40(fp)
+ 802e1f8:	10000d26 	beq	r2,zero,802e230 <soreceive+0x39c>
+         {
+            *aname = m;
+ 802e1fc:	e0bff617 	ldw	r2,-40(fp)
+ 802e200:	e0ffff17 	ldw	r3,-4(fp)
+ 802e204:	10c00015 	stw	r3,0(r2)
+            m = m->m_next;
+ 802e208:	e0bfff17 	ldw	r2,-4(fp)
+ 802e20c:	10800617 	ldw	r2,24(r2)
+ 802e210:	e0bfff15 	stw	r2,-4(fp)
+            (*aname)->m_next = 0;
+ 802e214:	e0bff617 	ldw	r2,-40(fp)
+ 802e218:	10800017 	ldw	r2,0(r2)
+ 802e21c:	10000615 	stw	zero,24(r2)
+            so->so_rcv.sb_mb = m;
+ 802e220:	e0bff717 	ldw	r2,-36(fp)
+ 802e224:	e0ffff17 	ldw	r3,-4(fp)
+ 802e228:	10c01015 	stw	r3,64(r2)
+ 802e22c:	00000806 	br	802e250 <soreceive+0x3bc>
+         } else 
+         {
+            MFREE(m, so->so_rcv.sb_mb);
+ 802e230:	e13fff17 	ldw	r4,-4(fp)
+ 802e234:	8029bf80 	call	8029bf8 <m_free>
+ 802e238:	1007883a 	mov	r3,r2
+ 802e23c:	e0bff717 	ldw	r2,-36(fp)
+ 802e240:	10c01015 	stw	r3,64(r2)
+            m = so->so_rcv.sb_mb;
+ 802e244:	e0bff717 	ldw	r2,-36(fp)
+ 802e248:	10801017 	ldw	r2,64(r2)
+ 802e24c:	e0bfff15 	stw	r2,-4(fp)
+         }
+         if (m)
+ 802e250:	e0bfff17 	ldw	r2,-4(fp)
+ 802e254:	10000326 	beq	r2,zero,802e264 <soreceive+0x3d0>
+            m->m_act = nextrecord;
+ 802e258:	e0bfff17 	ldw	r2,-4(fp)
+ 802e25c:	e0fffb17 	ldw	r3,-20(fp)
+ 802e260:	10c00715 	stw	r3,28(r2)
+      }
+   }
+   moff = 0;
+ 802e264:	e03ffa15 	stw	zero,-24(fp)
+   offset = 0;
+ 802e268:	e03ffc15 	stw	zero,-16(fp)
+   while (m && (*datalen > 0) && (error == 0))
+ 802e26c:	00009e06 	br	802e4e8 <soreceive+0x654>
+   {
+      if (m->m_type != MT_RXDATA && m->m_type != MT_HEADER)
+ 802e270:	e0bfff17 	ldw	r2,-4(fp)
+ 802e274:	10800817 	ldw	r2,32(r2)
+ 802e278:	10800060 	cmpeqi	r2,r2,1
+ 802e27c:	1000071e 	bne	r2,zero,802e29c <soreceive+0x408>
+ 802e280:	e0bfff17 	ldw	r2,-4(fp)
+ 802e284:	10800817 	ldw	r2,32(r2)
+ 802e288:	108000e0 	cmpeqi	r2,r2,3
+ 802e28c:	1000031e 	bne	r2,zero,802e29c <soreceive+0x408>
+         panic("sorecv 3");
+ 802e290:	01020174 	movhi	r4,2053
+ 802e294:	212a8704 	addi	r4,r4,-21988
+ 802e298:	80271780 	call	8027178 <panic>
+      len = *datalen;
+ 802e29c:	e0bff417 	ldw	r2,-48(fp)
+ 802e2a0:	10800017 	ldw	r2,0(r2)
+ 802e2a4:	e0bffe15 	stw	r2,-8(fp)
+      so->so_state &= ~SS_RCVATMARK;
+ 802e2a8:	e0bff717 	ldw	r2,-36(fp)
+ 802e2ac:	10c0088b 	ldhu	r3,34(r2)
+ 802e2b0:	00bfefc4 	movi	r2,-65
+ 802e2b4:	1884703a 	and	r2,r3,r2
+ 802e2b8:	1007883a 	mov	r3,r2
+ 802e2bc:	e0bff717 	ldw	r2,-36(fp)
+ 802e2c0:	10c0088d 	sth	r3,34(r2)
+      if (so->so_oobmark && (len > (int)(so->so_oobmark - offset)))
+ 802e2c4:	e0bff717 	ldw	r2,-36(fp)
+ 802e2c8:	10801a17 	ldw	r2,104(r2)
+ 802e2cc:	10000c26 	beq	r2,zero,802e300 <soreceive+0x46c>
+ 802e2d0:	e0bff717 	ldw	r2,-36(fp)
+ 802e2d4:	10c01a17 	ldw	r3,104(r2)
+ 802e2d8:	e0bffc17 	ldw	r2,-16(fp)
+ 802e2dc:	1885c83a 	sub	r2,r3,r2
+ 802e2e0:	1007883a 	mov	r3,r2
+ 802e2e4:	e0bffe17 	ldw	r2,-8(fp)
+ 802e2e8:	1880050e 	bge	r3,r2,802e300 <soreceive+0x46c>
+         len = (int)(so->so_oobmark - offset);
+ 802e2ec:	e0bff717 	ldw	r2,-36(fp)
+ 802e2f0:	10c01a17 	ldw	r3,104(r2)
+ 802e2f4:	e0bffc17 	ldw	r2,-16(fp)
+ 802e2f8:	1885c83a 	sub	r2,r3,r2
+ 802e2fc:	e0bffe15 	stw	r2,-8(fp)
+      if (len > (int)(m->m_len - moff))
+ 802e300:	e0bfff17 	ldw	r2,-4(fp)
+ 802e304:	10c00217 	ldw	r3,8(r2)
+ 802e308:	e0bffa17 	ldw	r2,-24(fp)
+ 802e30c:	1885c83a 	sub	r2,r3,r2
+ 802e310:	1007883a 	mov	r3,r2
+ 802e314:	e0bffe17 	ldw	r2,-8(fp)
+ 802e318:	1880050e 	bge	r3,r2,802e330 <soreceive+0x49c>
+         len = m->m_len - moff;
+ 802e31c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e320:	10c00217 	ldw	r3,8(r2)
+ 802e324:	e0bffa17 	ldw	r2,-24(fp)
+ 802e328:	1885c83a 	sub	r2,r3,r2
+ 802e32c:	e0bffe15 	stw	r2,-8(fp)
+       * it points to next record) when we drop priority;
+       * we must note any additions to the sockbuf when we
+       * block interrupts again.
+       */
+
+      MEMCPY(data, (mtod(m, char *) + moff), len);
+ 802e330:	e0bfff17 	ldw	r2,-4(fp)
+ 802e334:	10c00317 	ldw	r3,12(r2)
+ 802e338:	e0bffa17 	ldw	r2,-24(fp)
+ 802e33c:	1885883a 	add	r2,r3,r2
+ 802e340:	e0fffe17 	ldw	r3,-8(fp)
+ 802e344:	180d883a 	mov	r6,r3
+ 802e348:	100b883a 	mov	r5,r2
+ 802e34c:	e13ff517 	ldw	r4,-44(fp)
+ 802e350:	80086b80 	call	80086b8 <memcpy>
+      data += len;
+ 802e354:	e0bffe17 	ldw	r2,-8(fp)
+ 802e358:	e0fff517 	ldw	r3,-44(fp)
+ 802e35c:	1885883a 	add	r2,r3,r2
+ 802e360:	e0bff515 	stw	r2,-44(fp)
+      *datalen -= len;
+ 802e364:	e0bff417 	ldw	r2,-48(fp)
+ 802e368:	10c00017 	ldw	r3,0(r2)
+ 802e36c:	e0bffe17 	ldw	r2,-8(fp)
+ 802e370:	1887c83a 	sub	r3,r3,r2
+ 802e374:	e0bff417 	ldw	r2,-48(fp)
+ 802e378:	10c00015 	stw	r3,0(r2)
+
+      if (len == (int)(m->m_len - moff))
+ 802e37c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e380:	10c00217 	ldw	r3,8(r2)
+ 802e384:	e0bffa17 	ldw	r2,-24(fp)
+ 802e388:	1885c83a 	sub	r2,r3,r2
+ 802e38c:	1007883a 	mov	r3,r2
+ 802e390:	e0bffe17 	ldw	r2,-8(fp)
+ 802e394:	10c0201e 	bne	r2,r3,802e418 <soreceive+0x584>
+      {
+         if (flags & MSG_PEEK) 
+ 802e398:	e0800217 	ldw	r2,8(fp)
+ 802e39c:	1080008c 	andi	r2,r2,2
+ 802e3a0:	10000526 	beq	r2,zero,802e3b8 <soreceive+0x524>
+         {
+            m = m->m_next;
+ 802e3a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802e3a8:	10800617 	ldw	r2,24(r2)
+ 802e3ac:	e0bfff15 	stw	r2,-4(fp)
+            moff = 0;
+ 802e3b0:	e03ffa15 	stw	zero,-24(fp)
+ 802e3b4:	00003206 	br	802e480 <soreceive+0x5ec>
+         } else 
+         {
+            nextrecord = m->m_act;
+ 802e3b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802e3bc:	10800717 	ldw	r2,28(r2)
+ 802e3c0:	e0bffb15 	stw	r2,-20(fp)
+            sbfree(&so->so_rcv, m);
+ 802e3c4:	e0bff717 	ldw	r2,-36(fp)
+ 802e3c8:	10c00a17 	ldw	r3,40(r2)
+ 802e3cc:	e0bfff17 	ldw	r2,-4(fp)
+ 802e3d0:	10800217 	ldw	r2,8(r2)
+ 802e3d4:	1887c83a 	sub	r3,r3,r2
+ 802e3d8:	e0bff717 	ldw	r2,-36(fp)
+ 802e3dc:	10c00a15 	stw	r3,40(r2)
+            {
+               MFREE(m, so->so_rcv.sb_mb);
+ 802e3e0:	e13fff17 	ldw	r4,-4(fp)
+ 802e3e4:	8029bf80 	call	8029bf8 <m_free>
+ 802e3e8:	1007883a 	mov	r3,r2
+ 802e3ec:	e0bff717 	ldw	r2,-36(fp)
+ 802e3f0:	10c01015 	stw	r3,64(r2)
+               m = so->so_rcv.sb_mb;
+ 802e3f4:	e0bff717 	ldw	r2,-36(fp)
+ 802e3f8:	10801017 	ldw	r2,64(r2)
+ 802e3fc:	e0bfff15 	stw	r2,-4(fp)
+            }
+            if (m)
+ 802e400:	e0bfff17 	ldw	r2,-4(fp)
+ 802e404:	10001e26 	beq	r2,zero,802e480 <soreceive+0x5ec>
+               m->m_act = nextrecord;
+ 802e408:	e0bfff17 	ldw	r2,-4(fp)
+ 802e40c:	e0fffb17 	ldw	r3,-20(fp)
+ 802e410:	10c00715 	stw	r3,28(r2)
+ 802e414:	00001a06 	br	802e480 <soreceive+0x5ec>
+         }
+      } else 
+      {
+         if (flags & MSG_PEEK)
+ 802e418:	e0800217 	ldw	r2,8(fp)
+ 802e41c:	1080008c 	andi	r2,r2,2
+ 802e420:	10000526 	beq	r2,zero,802e438 <soreceive+0x5a4>
+            moff += len;
+ 802e424:	e0fffa17 	ldw	r3,-24(fp)
+ 802e428:	e0bffe17 	ldw	r2,-8(fp)
+ 802e42c:	1885883a 	add	r2,r3,r2
+ 802e430:	e0bffa15 	stw	r2,-24(fp)
+ 802e434:	00001206 	br	802e480 <soreceive+0x5ec>
+         else 
+         {
+            m->m_data += len;
+ 802e438:	e0bfff17 	ldw	r2,-4(fp)
+ 802e43c:	10c00317 	ldw	r3,12(r2)
+ 802e440:	e0bffe17 	ldw	r2,-8(fp)
+ 802e444:	1887883a 	add	r3,r3,r2
+ 802e448:	e0bfff17 	ldw	r2,-4(fp)
+ 802e44c:	10c00315 	stw	r3,12(r2)
+            m->m_len -= len;
+ 802e450:	e0bfff17 	ldw	r2,-4(fp)
+ 802e454:	10c00217 	ldw	r3,8(r2)
+ 802e458:	e0bffe17 	ldw	r2,-8(fp)
+ 802e45c:	1887c83a 	sub	r3,r3,r2
+ 802e460:	e0bfff17 	ldw	r2,-4(fp)
+ 802e464:	10c00215 	stw	r3,8(r2)
+            so->so_rcv.sb_cc -= len;
+ 802e468:	e0bff717 	ldw	r2,-36(fp)
+ 802e46c:	10c00a17 	ldw	r3,40(r2)
+ 802e470:	e0bffe17 	ldw	r2,-8(fp)
+ 802e474:	1887c83a 	sub	r3,r3,r2
+ 802e478:	e0bff717 	ldw	r2,-36(fp)
+ 802e47c:	10c00a15 	stw	r3,40(r2)
+         }
+      }
+      if (so->so_oobmark) 
+ 802e480:	e0bff717 	ldw	r2,-36(fp)
+ 802e484:	10801a17 	ldw	r2,104(r2)
+ 802e488:	10001726 	beq	r2,zero,802e4e8 <soreceive+0x654>
+      {
+         if ((flags & MSG_PEEK) == 0) 
+ 802e48c:	e0800217 	ldw	r2,8(fp)
+ 802e490:	1080008c 	andi	r2,r2,2
+ 802e494:	1000101e 	bne	r2,zero,802e4d8 <soreceive+0x644>
+         {
+            so->so_oobmark -= len;
+ 802e498:	e0bff717 	ldw	r2,-36(fp)
+ 802e49c:	10c01a17 	ldw	r3,104(r2)
+ 802e4a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802e4a4:	1887c83a 	sub	r3,r3,r2
+ 802e4a8:	e0bff717 	ldw	r2,-36(fp)
+ 802e4ac:	10c01a15 	stw	r3,104(r2)
+            if (so->so_oobmark == 0) 
+ 802e4b0:	e0bff717 	ldw	r2,-36(fp)
+ 802e4b4:	10801a17 	ldw	r2,104(r2)
+ 802e4b8:	10000b1e 	bne	r2,zero,802e4e8 <soreceive+0x654>
+            {
+               so->so_state |= SS_RCVATMARK;
+ 802e4bc:	e0bff717 	ldw	r2,-36(fp)
+ 802e4c0:	1080088b 	ldhu	r2,34(r2)
+ 802e4c4:	10801014 	ori	r2,r2,64
+ 802e4c8:	1007883a 	mov	r3,r2
+ 802e4cc:	e0bff717 	ldw	r2,-36(fp)
+ 802e4d0:	10c0088d 	sth	r3,34(r2)
+               break;
+ 802e4d4:	00000b06 	br	802e504 <soreceive+0x670>
+            }
+         } else
+            offset += len;
+ 802e4d8:	e0fffc17 	ldw	r3,-16(fp)
+ 802e4dc:	e0bffe17 	ldw	r2,-8(fp)
+ 802e4e0:	1885883a 	add	r2,r3,r2
+ 802e4e4:	e0bffc15 	stw	r2,-16(fp)
+   while (m && (*datalen > 0) && (error == 0))
+ 802e4e8:	e0bfff17 	ldw	r2,-4(fp)
+ 802e4ec:	10000526 	beq	r2,zero,802e504 <soreceive+0x670>
+ 802e4f0:	e0bff417 	ldw	r2,-48(fp)
+ 802e4f4:	10800017 	ldw	r2,0(r2)
+ 802e4f8:	0080020e 	bge	zero,r2,802e504 <soreceive+0x670>
+ 802e4fc:	e0bffd17 	ldw	r2,-12(fp)
+ 802e500:	103f5b26 	beq	r2,zero,802e270 <soreceive+0x3dc>
+      }
+   }
+
+   if ((flags & MSG_PEEK) == 0) 
+ 802e504:	e0800217 	ldw	r2,8(fp)
+ 802e508:	1080008c 	andi	r2,r2,2
+ 802e50c:	1000251e 	bne	r2,zero,802e5a4 <soreceive+0x710>
+   {
+      if (m == 0)
+ 802e510:	e0bfff17 	ldw	r2,-4(fp)
+ 802e514:	1000041e 	bne	r2,zero,802e528 <soreceive+0x694>
+         so->so_rcv.sb_mb = nextrecord;
+ 802e518:	e0bff717 	ldw	r2,-36(fp)
+ 802e51c:	e0fffb17 	ldw	r3,-20(fp)
+ 802e520:	10c01015 	stw	r3,64(r2)
+ 802e524:	00000906 	br	802e54c <soreceive+0x6b8>
+      else if (pr->pr_flags & PR_ATOMIC)
+ 802e528:	e0bff917 	ldw	r2,-28(fp)
+ 802e52c:	1080010b 	ldhu	r2,4(r2)
+ 802e530:	10bfffcc 	andi	r2,r2,65535
+ 802e534:	1080004c 	andi	r2,r2,1
+ 802e538:	10000426 	beq	r2,zero,802e54c <soreceive+0x6b8>
+         (void) sbdroprecord(&so->so_rcv);
+ 802e53c:	e0bff717 	ldw	r2,-36(fp)
+ 802e540:	10800a04 	addi	r2,r2,40
+ 802e544:	1009883a 	mov	r4,r2
+ 802e548:	80303680 	call	8030368 <sbdroprecord>
+      if (pr->pr_flags & PR_WANTRCVD && so->so_pcb)
+ 802e54c:	e0bff917 	ldw	r2,-28(fp)
+ 802e550:	1080010b 	ldhu	r2,4(r2)
+ 802e554:	10bfffcc 	andi	r2,r2,65535
+ 802e558:	1080020c 	andi	r2,r2,8
+ 802e55c:	10001126 	beq	r2,zero,802e5a4 <soreceive+0x710>
+ 802e560:	e0bff717 	ldw	r2,-36(fp)
+ 802e564:	10800117 	ldw	r2,4(r2)
+ 802e568:	10000e26 	beq	r2,zero,802e5a4 <soreceive+0x710>
+      {
+         so->so_req = PRU_RCVD;
+ 802e56c:	e0bff717 	ldw	r2,-36(fp)
+ 802e570:	00c00204 	movi	r3,8
+ 802e574:	10c00715 	stw	r3,28(r2)
+         (*pr->pr_usrreq)(so, (struct mbuf *)0,
+ 802e578:	e0bff917 	ldw	r2,-28(fp)
+ 802e57c:	10800317 	ldw	r2,12(r2)
+ 802e580:	000d883a 	mov	r6,zero
+ 802e584:	000b883a 	mov	r5,zero
+ 802e588:	e13ff717 	ldw	r4,-36(fp)
+ 802e58c:	103ee83a 	callr	r2
+ 802e590:	00000506 	br	802e5a8 <soreceive+0x714>
+         goto release;
+ 802e594:	0001883a 	nop
+ 802e598:	00000306 	br	802e5a8 <soreceive+0x714>
+         goto release;
+ 802e59c:	0001883a 	nop
+ 802e5a0:	00000106 	br	802e5a8 <soreceive+0x714>
+          (struct mbuf *)0);
+      }
+   }
+release:
+ 802e5a4:	0001883a 	nop
+   sbunlock(&so->so_rcv);
+ 802e5a8:	e0bff717 	ldw	r2,-36(fp)
+ 802e5ac:	10c0110b 	ldhu	r3,68(r2)
+ 802e5b0:	00bfff84 	movi	r2,-2
+ 802e5b4:	1884703a 	and	r2,r3,r2
+ 802e5b8:	1007883a 	mov	r3,r2
+ 802e5bc:	e0bff717 	ldw	r2,-36(fp)
+ 802e5c0:	10c0110d 	sth	r3,68(r2)
+ 802e5c4:	e0bff717 	ldw	r2,-36(fp)
+ 802e5c8:	10801104 	addi	r2,r2,68
+ 802e5cc:	1009883a 	mov	r4,r2
+ 802e5d0:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   return (error);
+ 802e5d4:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 802e5d8:	e037883a 	mov	sp,fp
+ 802e5dc:	dfc00117 	ldw	ra,4(sp)
+ 802e5e0:	df000017 	ldw	fp,0(sp)
+ 802e5e4:	dec00204 	addi	sp,sp,8
+ 802e5e8:	f800283a 	ret
+
+0802e5ec <soshutdown>:
+ *
+ * RETURNS: int               0 if successful, else error code
+ */
+int
+soshutdown(struct socket *so, int how)
+{
+ 802e5ec:	defffc04 	addi	sp,sp,-16
+ 802e5f0:	dfc00315 	stw	ra,12(sp)
+ 802e5f4:	df000215 	stw	fp,8(sp)
+ 802e5f8:	df000204 	addi	fp,sp,8
+ 802e5fc:	e13fff15 	stw	r4,-4(fp)
+ 802e600:	e17ffe15 	stw	r5,-8(fp)
+   how++;   /* convert 0,1,2 into 1,2,3 */
+ 802e604:	e0bffe17 	ldw	r2,-8(fp)
+ 802e608:	10800044 	addi	r2,r2,1
+ 802e60c:	e0bffe15 	stw	r2,-8(fp)
+   if (how & 1)   /* caller wanted READ or BOTH */
+ 802e610:	e0bffe17 	ldw	r2,-8(fp)
+ 802e614:	1080004c 	andi	r2,r2,1
+ 802e618:	10000226 	beq	r2,zero,802e624 <soshutdown+0x38>
+      sorflush(so);
+ 802e61c:	e13fff17 	ldw	r4,-4(fp)
+ 802e620:	802e6840 	call	802e684 <sorflush>
+
+   if (how & 2)   /* caller wanted WRITE or BOTH */
+ 802e624:	e0bffe17 	ldw	r2,-8(fp)
+ 802e628:	1080008c 	andi	r2,r2,2
+ 802e62c:	10000f26 	beq	r2,zero,802e66c <soshutdown+0x80>
+   {
+      sbflush(&so->so_snd); /* flush the socket send queue */
+ 802e630:	e0bfff17 	ldw	r2,-4(fp)
+ 802e634:	10801204 	addi	r2,r2,72
+ 802e638:	1009883a 	mov	r4,r2
+ 802e63c:	803002c0 	call	803002c <sbflush>
+      so->so_req = PRU_SHUTDOWN;
+ 802e640:	e0bfff17 	ldw	r2,-4(fp)
+ 802e644:	00c001c4 	movi	r3,7
+ 802e648:	10c00715 	stw	r3,28(r2)
+      return ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0));
+ 802e64c:	e0bfff17 	ldw	r2,-4(fp)
+ 802e650:	10800217 	ldw	r2,8(r2)
+ 802e654:	10800317 	ldw	r2,12(r2)
+ 802e658:	000d883a 	mov	r6,zero
+ 802e65c:	000b883a 	mov	r5,zero
+ 802e660:	e13fff17 	ldw	r4,-4(fp)
+ 802e664:	103ee83a 	callr	r2
+ 802e668:	00000106 	br	802e670 <soshutdown+0x84>
+   }
+
+   return 0;
+ 802e66c:	0005883a 	mov	r2,zero
+}
+ 802e670:	e037883a 	mov	sp,fp
+ 802e674:	dfc00117 	ldw	ra,4(sp)
+ 802e678:	df000017 	ldw	fp,0(sp)
+ 802e67c:	dec00204 	addi	sp,sp,8
+ 802e680:	f800283a 	ret
+
+0802e684 <sorflush>:
+ * socket receive buffer is discarded. Wakeup any processes waiting
+ * on the socket.
+ */
+void
+sorflush(struct socket * so)
+{
+ 802e684:	defffb04 	addi	sp,sp,-20
+ 802e688:	dfc00415 	stw	ra,16(sp)
+ 802e68c:	df000315 	stw	fp,12(sp)
+ 802e690:	df000304 	addi	fp,sp,12
+ 802e694:	e13ffd15 	stw	r4,-12(fp)
+   struct sockbuf *sb =  &so->so_rcv;
+ 802e698:	e0bffd17 	ldw	r2,-12(fp)
+ 802e69c:	10800a04 	addi	r2,r2,40
+ 802e6a0:	e0bfff15 	stw	r2,-4(fp)
+   int   s;
+
+   sblock(sb);
+ 802e6a4:	00000406 	br	802e6b8 <sorflush+0x34>
+ 802e6a8:	e0bfff17 	ldw	r2,-4(fp)
+ 802e6ac:	10800704 	addi	r2,r2,28
+ 802e6b0:	1009883a 	mov	r4,r2
+ 802e6b4:	8027a540 	call	8027a54 <tcp_sleep>
+ 802e6b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802e6bc:	1080070b 	ldhu	r2,28(r2)
+ 802e6c0:	10bfffcc 	andi	r2,r2,65535
+ 802e6c4:	1080004c 	andi	r2,r2,1
+ 802e6c8:	103ff71e 	bne	r2,zero,802e6a8 <sorflush+0x24>
+ 802e6cc:	e0bfff17 	ldw	r2,-4(fp)
+ 802e6d0:	1080070b 	ldhu	r2,28(r2)
+ 802e6d4:	10800054 	ori	r2,r2,1
+ 802e6d8:	1007883a 	mov	r3,r2
+ 802e6dc:	e0bfff17 	ldw	r2,-4(fp)
+ 802e6e0:	10c0070d 	sth	r3,28(r2)
+   socantrcvmore(so);
+ 802e6e4:	e13ffd17 	ldw	r4,-12(fp)
+ 802e6e8:	802f84c0 	call	802f84c <socantrcvmore>
+   sbunlock(sb);
+ 802e6ec:	e0bfff17 	ldw	r2,-4(fp)
+ 802e6f0:	10c0070b 	ldhu	r3,28(r2)
+ 802e6f4:	00bfff84 	movi	r2,-2
+ 802e6f8:	1884703a 	and	r2,r3,r2
+ 802e6fc:	1007883a 	mov	r3,r2
+ 802e700:	e0bfff17 	ldw	r2,-4(fp)
+ 802e704:	10c0070d 	sth	r3,28(r2)
+ 802e708:	e0bfff17 	ldw	r2,-4(fp)
+ 802e70c:	10800704 	addi	r2,r2,28
+ 802e710:	1009883a 	mov	r4,r2
+ 802e714:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   sbrelease(sb);
+ 802e718:	e13fff17 	ldw	r4,-4(fp)
+ 802e71c:	802fab00 	call	802fab0 <sbrelease>
+   MEMSET((char *)sb, 0, sizeof (*sb));
+ 802e720:	01800804 	movi	r6,32
+ 802e724:	000b883a 	mov	r5,zero
+ 802e728:	e13fff17 	ldw	r4,-4(fp)
+ 802e72c:	80088e40 	call	80088e4 <memset>
+   s = so->so_error;
+ 802e730:	e0bffd17 	ldw	r2,-12(fp)
+ 802e734:	10800617 	ldw	r2,24(r2)
+ 802e738:	e0bffe15 	stw	r2,-8(fp)
+   so->so_error = ESHUTDOWN;
+ 802e73c:	e0bffd17 	ldw	r2,-12(fp)
+ 802e740:	00c01b84 	movi	r3,110
+ 802e744:	10c00615 	stw	r3,24(r2)
+   sorwakeup(so);
+ 802e748:	e0bffd17 	ldw	r2,-12(fp)
+ 802e74c:	10800a04 	addi	r2,r2,40
+ 802e750:	100b883a 	mov	r5,r2
+ 802e754:	e13ffd17 	ldw	r4,-12(fp)
+ 802e758:	802f94c0 	call	802f94c <sbwakeup>
+   so->so_error = s;
+ 802e75c:	e0bffd17 	ldw	r2,-12(fp)
+ 802e760:	e0fffe17 	ldw	r3,-8(fp)
+ 802e764:	10c00615 	stw	r3,24(r2)
+}
+ 802e768:	0001883a 	nop
+ 802e76c:	e037883a 	mov	sp,fp
+ 802e770:	dfc00117 	ldw	ra,4(sp)
+ 802e774:	df000017 	ldw	fp,0(sp)
+ 802e778:	dec00204 	addi	sp,sp,8
+ 802e77c:	f800283a 	ret
+
+0802e780 <sosetopt>:
+
+int
+sosetopt(struct socket * so, 
+   int   optname,
+   void *   arg)
+{
+ 802e780:	defff604 	addi	sp,sp,-40
+ 802e784:	dfc00915 	stw	ra,36(sp)
+ 802e788:	df000815 	stw	fp,32(sp)
+ 802e78c:	df000804 	addi	fp,sp,32
+ 802e790:	e13ffa15 	stw	r4,-24(fp)
+ 802e794:	e17ff915 	stw	r5,-28(fp)
+ 802e798:	e1bff815 	stw	r6,-32(fp)
+   int   error =  0;
+ 802e79c:	e03fff15 	stw	zero,-4(fp)
+
+   switch (optname) 
+ 802e7a0:	e0bff917 	ldw	r2,-28(fp)
+ 802e7a4:	10808020 	cmpeqi	r2,r2,512
+ 802e7a8:	1000521e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e7ac:	e0bff917 	ldw	r2,-28(fp)
+ 802e7b0:	10808048 	cmpgei	r2,r2,513
+ 802e7b4:	1000211e 	bne	r2,zero,802e83c <sosetopt+0xbc>
+ 802e7b8:	e0bff917 	ldw	r2,-28(fp)
+ 802e7bc:	10800388 	cmpgei	r2,r2,14
+ 802e7c0:	10000d1e 	bne	r2,zero,802e7f8 <sosetopt+0x78>
+ 802e7c4:	e0bff917 	ldw	r2,-28(fp)
+ 802e7c8:	10800248 	cmpgei	r2,r2,9
+ 802e7cc:	1000971e 	bne	r2,zero,802ea2c <sosetopt+0x2ac>
+ 802e7d0:	e0bff917 	ldw	r2,-28(fp)
+ 802e7d4:	10800120 	cmpeqi	r2,r2,4
+ 802e7d8:	1000461e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e7dc:	e0bff917 	ldw	r2,-28(fp)
+ 802e7e0:	10800220 	cmpeqi	r2,r2,8
+ 802e7e4:	1000431e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e7e8:	e0bff917 	ldw	r2,-28(fp)
+ 802e7ec:	108000a0 	cmpeqi	r2,r2,2
+ 802e7f0:	1000941e 	bne	r2,zero,802ea44 <sosetopt+0x2c4>
+ 802e7f4:	0000fb06 	br	802ebe4 <sosetopt+0x464>
+ 802e7f8:	e0bff917 	ldw	r2,-28(fp)
+ 802e7fc:	10800820 	cmpeqi	r2,r2,32
+ 802e800:	10003c1e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e804:	e0bff917 	ldw	r2,-28(fp)
+ 802e808:	10800848 	cmpgei	r2,r2,33
+ 802e80c:	1000041e 	bne	r2,zero,802e820 <sosetopt+0xa0>
+ 802e810:	e0bff917 	ldw	r2,-28(fp)
+ 802e814:	10800420 	cmpeqi	r2,r2,16
+ 802e818:	1000361e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e81c:	0000f106 	br	802ebe4 <sosetopt+0x464>
+ 802e820:	e0bff917 	ldw	r2,-28(fp)
+ 802e824:	10802020 	cmpeqi	r2,r2,128
+ 802e828:	10002d1e 	bne	r2,zero,802e8e0 <sosetopt+0x160>
+ 802e82c:	e0bff917 	ldw	r2,-28(fp)
+ 802e830:	10804020 	cmpeqi	r2,r2,256
+ 802e834:	10002f1e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e838:	0000ea06 	br	802ebe4 <sosetopt+0x464>
+ 802e83c:	e0bff917 	ldw	r2,-28(fp)
+ 802e840:	10840520 	cmpeqi	r2,r2,4116
+ 802e844:	1000531e 	bne	r2,zero,802e994 <sosetopt+0x214>
+ 802e848:	e0bff917 	ldw	r2,-28(fp)
+ 802e84c:	10840548 	cmpgei	r2,r2,4117
+ 802e850:	10000f1e 	bne	r2,zero,802e890 <sosetopt+0x110>
+ 802e854:	e0bff917 	ldw	r2,-28(fp)
+ 802e858:	108401a0 	cmpeqi	r2,r2,4102
+ 802e85c:	1000481e 	bne	r2,zero,802e980 <sosetopt+0x200>
+ 802e860:	e0bff917 	ldw	r2,-28(fp)
+ 802e864:	108401c8 	cmpgei	r2,r2,4103
+ 802e868:	1000051e 	bne	r2,zero,802e880 <sosetopt+0x100>
+ 802e86c:	e0bff917 	ldw	r2,-28(fp)
+ 802e870:	10bbffc4 	addi	r2,r2,-4097
+ 802e874:	108000a8 	cmpgeui	r2,r2,2
+ 802e878:	1000da1e 	bne	r2,zero,802ebe4 <sosetopt+0x464>
+ 802e87c:	00002f06 	br	802e93c <sosetopt+0x1bc>
+ 802e880:	e0bff917 	ldw	r2,-28(fp)
+ 802e884:	10840420 	cmpeqi	r2,r2,4112
+ 802e888:	1000af1e 	bne	r2,zero,802eb48 <sosetopt+0x3c8>
+ 802e88c:	0000d506 	br	802ebe4 <sosetopt+0x464>
+ 802e890:	e0bff917 	ldw	r2,-28(fp)
+ 802e894:	108800e0 	cmpeqi	r2,r2,8195
+ 802e898:	1000ab1e 	bne	r2,zero,802eb48 <sosetopt+0x3c8>
+ 802e89c:	e0bff917 	ldw	r2,-28(fp)
+ 802e8a0:	10880108 	cmpgei	r2,r2,8196
+ 802e8a4:	1000071e 	bne	r2,zero,802e8c4 <sosetopt+0x144>
+ 802e8a8:	e0bff917 	ldw	r2,-28(fp)
+ 802e8ac:	10840560 	cmpeqi	r2,r2,4117
+ 802e8b0:	10003f1e 	bne	r2,zero,802e9b0 <sosetopt+0x230>
+ 802e8b4:	e0bff917 	ldw	r2,-28(fp)
+ 802e8b8:	108405a0 	cmpeqi	r2,r2,4118
+ 802e8bc:	1000441e 	bne	r2,zero,802e9d0 <sosetopt+0x250>
+ 802e8c0:	0000c806 	br	802ebe4 <sosetopt+0x464>
+ 802e8c4:	e0bff917 	ldw	r2,-28(fp)
+ 802e8c8:	10880120 	cmpeqi	r2,r2,8196
+ 802e8cc:	1000721e 	bne	r2,zero,802ea98 <sosetopt+0x318>
+ 802e8d0:	e0bff917 	ldw	r2,-28(fp)
+ 802e8d4:	10900020 	cmpeqi	r2,r2,16384
+ 802e8d8:	1000061e 	bne	r2,zero,802e8f4 <sosetopt+0x174>
+ 802e8dc:	0000c106 	br	802ebe4 <sosetopt+0x464>
+   {
+   case SO_LINGER:
+      so->so_linger = (short)((struct linger *)arg)->l_linger;
+ 802e8e0:	e0bff817 	ldw	r2,-32(fp)
+ 802e8e4:	10800117 	ldw	r2,4(r2)
+ 802e8e8:	1007883a 	mov	r3,r2
+ 802e8ec:	e0bffa17 	ldw	r2,-24(fp)
+ 802e8f0:	10c0080d 	sth	r3,32(r2)
+   case SO_TCPSACK:
+   case SO_NOSLOWSTART:
+#ifdef SUPPORT_SO_FULLMSS
+   case SO_FULLMSS:
+#endif
+      if (*(int *)arg) 
+ 802e8f4:	e0bff817 	ldw	r2,-32(fp)
+ 802e8f8:	10800017 	ldw	r2,0(r2)
+ 802e8fc:	10000726 	beq	r2,zero,802e91c <sosetopt+0x19c>
+         so->so_options |= optname;
+ 802e900:	e0bffa17 	ldw	r2,-24(fp)
+ 802e904:	10c00417 	ldw	r3,16(r2)
+ 802e908:	e0bff917 	ldw	r2,-28(fp)
+ 802e90c:	1886b03a 	or	r3,r3,r2
+ 802e910:	e0bffa17 	ldw	r2,-24(fp)
+ 802e914:	10c00415 	stw	r3,16(r2)
+      else
+         so->so_options &= ~optname;
+      break;
+ 802e918:	0000b606 	br	802ebf4 <sosetopt+0x474>
+         so->so_options &= ~optname;
+ 802e91c:	e0bffa17 	ldw	r2,-24(fp)
+ 802e920:	10800417 	ldw	r2,16(r2)
+ 802e924:	e0fff917 	ldw	r3,-28(fp)
+ 802e928:	00c6303a 	nor	r3,zero,r3
+ 802e92c:	10c6703a 	and	r3,r2,r3
+ 802e930:	e0bffa17 	ldw	r2,-24(fp)
+ 802e934:	10c00415 	stw	r3,16(r2)
+      break;
+ 802e938:	0000ae06 	br	802ebf4 <sosetopt+0x474>
+      break;
+#endif /* TCP_BIGCWND */
+
+   case SO_SNDBUF:
+   case SO_RCVBUF:
+      if (sbreserve(optname == SO_SNDBUF ?
+ 802e93c:	e0bff917 	ldw	r2,-28(fp)
+ 802e940:	10840058 	cmpnei	r2,r2,4097
+ 802e944:	1000031e 	bne	r2,zero,802e954 <sosetopt+0x1d4>
+ 802e948:	e0bffa17 	ldw	r2,-24(fp)
+ 802e94c:	10801204 	addi	r2,r2,72
+ 802e950:	00000206 	br	802e95c <sosetopt+0x1dc>
+ 802e954:	e0bffa17 	ldw	r2,-24(fp)
+ 802e958:	10800a04 	addi	r2,r2,40
+          &so->so_snd : &so->so_rcv,
+          (u_long) * (int *)arg) == 0) 
+ 802e95c:	e0fff817 	ldw	r3,-32(fp)
+ 802e960:	18c00017 	ldw	r3,0(r3)
+      if (sbreserve(optname == SO_SNDBUF ?
+ 802e964:	180b883a 	mov	r5,r3
+ 802e968:	1009883a 	mov	r4,r2
+ 802e96c:	802fa600 	call	802fa60 <sbreserve>
+ 802e970:	10009f1e 	bne	r2,zero,802ebf0 <sosetopt+0x470>
+      {
+         error = ENOBUFS;
+ 802e974:	00801a44 	movi	r2,105
+ 802e978:	e0bfff15 	stw	r2,-4(fp)
+         goto bad;
+ 802e97c:	00009d06 	br	802ebf4 <sosetopt+0x474>
+      }
+      break;
+
+   case SO_RCVTIMEO:
+      so->so_rcv.sb_timeo = *(short *)arg;
+ 802e980:	e0bff817 	ldw	r2,-32(fp)
+ 802e984:	10c0000b 	ldhu	r3,0(r2)
+ 802e988:	e0bffa17 	ldw	r2,-24(fp)
+ 802e98c:	10c0118d 	sth	r3,70(r2)
+      break;
+ 802e990:	00009806 	br	802ebf4 <sosetopt+0x474>
+
+   case SO_NBIO:     /* set socket into NON-blocking mode */
+      so->so_state |= SS_NBIO;
+ 802e994:	e0bffa17 	ldw	r2,-24(fp)
+ 802e998:	1080088b 	ldhu	r2,34(r2)
+ 802e99c:	10804014 	ori	r2,r2,256
+ 802e9a0:	1007883a 	mov	r3,r2
+ 802e9a4:	e0bffa17 	ldw	r2,-24(fp)
+ 802e9a8:	10c0088d 	sth	r3,34(r2)
+      break;
+ 802e9ac:	00009106 	br	802ebf4 <sosetopt+0x474>
+
+   case SO_BIO:   /* set socket into blocking mode */
+      so->so_state &= ~SS_NBIO;
+ 802e9b0:	e0bffa17 	ldw	r2,-24(fp)
+ 802e9b4:	10c0088b 	ldhu	r3,34(r2)
+ 802e9b8:	00bfbfc4 	movi	r2,-257
+ 802e9bc:	1884703a 	and	r2,r3,r2
+ 802e9c0:	1007883a 	mov	r3,r2
+ 802e9c4:	e0bffa17 	ldw	r2,-24(fp)
+ 802e9c8:	10c0088d 	sth	r3,34(r2)
+      break;
+ 802e9cc:	00008906 	br	802ebf4 <sosetopt+0x474>
+
+   case SO_NONBLOCK:    /* set blocking mode according to arg */
+      /* sanity check the arg parameter */
+      if (!arg)
+ 802e9d0:	e0bff817 	ldw	r2,-32(fp)
+ 802e9d4:	1000031e 	bne	r2,zero,802e9e4 <sosetopt+0x264>
+      {
+         error = ENP_PARAM;
+ 802e9d8:	00bffd84 	movi	r2,-10
+ 802e9dc:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802e9e0:	00008406 	br	802ebf4 <sosetopt+0x474>
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (*(int *) arg)
+ 802e9e4:	e0bff817 	ldw	r2,-32(fp)
+ 802e9e8:	10800017 	ldw	r2,0(r2)
+ 802e9ec:	10000726 	beq	r2,zero,802ea0c <sosetopt+0x28c>
+         so->so_state |= SS_NBIO;   /* set non-blocking mode */
+ 802e9f0:	e0bffa17 	ldw	r2,-24(fp)
+ 802e9f4:	1080088b 	ldhu	r2,34(r2)
+ 802e9f8:	10804014 	ori	r2,r2,256
+ 802e9fc:	1007883a 	mov	r3,r2
+ 802ea00:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea04:	10c0088d 	sth	r3,34(r2)
+      else
+         so->so_state &= ~SS_NBIO;  /* set blocking mode */
+      break;
+ 802ea08:	00007a06 	br	802ebf4 <sosetopt+0x474>
+         so->so_state &= ~SS_NBIO;  /* set blocking mode */
+ 802ea0c:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea10:	10c0088b 	ldhu	r3,34(r2)
+ 802ea14:	00bfbfc4 	movi	r2,-257
+ 802ea18:	1884703a 	and	r2,r3,r2
+ 802ea1c:	1007883a 	mov	r3,r2
+ 802ea20:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea24:	10c0088d 	sth	r3,34(r2)
+      break;
+ 802ea28:	00007206 	br	802ebf4 <sosetopt+0x474>
+   case IP_MULTICAST_IF:
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+   case IP_ADD_MEMBERSHIP:
+   case IP_DROP_MEMBERSHIP:
+      error = ip_setmoptions(optname, so, arg);
+ 802ea2c:	e1bff817 	ldw	r6,-32(fp)
+ 802ea30:	e17ffa17 	ldw	r5,-24(fp)
+ 802ea34:	e13ff917 	ldw	r4,-28(fp)
+ 802ea38:	803e7c40 	call	803e7c4 <ip_setmoptions>
+ 802ea3c:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 802ea40:	00006c06 	br	802ebf4 <sosetopt+0x474>
+
+#ifdef IP_RAW
+
+   case IP_HDRINCL:
+      /* try to make sure that the argument pointer is valid */
+      if (arg == NULL)
+ 802ea44:	e0bff817 	ldw	r2,-32(fp)
+ 802ea48:	1000031e 	bne	r2,zero,802ea58 <sosetopt+0x2d8>
+      {
+         error = ENP_PARAM;
+ 802ea4c:	00bffd84 	movi	r2,-10
+ 802ea50:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802ea54:	00006706 	br	802ebf4 <sosetopt+0x474>
+      }
+      /* set the socket option flag based on the pointed-to argument */
+      if (*(int *)arg)
+ 802ea58:	e0bff817 	ldw	r2,-32(fp)
+ 802ea5c:	10800017 	ldw	r2,0(r2)
+ 802ea60:	10000626 	beq	r2,zero,802ea7c <sosetopt+0x2fc>
+         so->so_options |= SO_HDRINCL;
+ 802ea64:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea68:	10800417 	ldw	r2,16(r2)
+ 802ea6c:	10c80014 	ori	r3,r2,8192
+ 802ea70:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea74:	10c00415 	stw	r3,16(r2)
+      else
+         so->so_options &= ~SO_HDRINCL;
+      break;
+ 802ea78:	00005e06 	br	802ebf4 <sosetopt+0x474>
+         so->so_options &= ~SO_HDRINCL;
+ 802ea7c:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea80:	10c00417 	ldw	r3,16(r2)
+ 802ea84:	00b7ffc4 	movi	r2,-8193
+ 802ea88:	1886703a 	and	r3,r3,r2
+ 802ea8c:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea90:	10c00415 	stw	r3,16(r2)
+      break;
+ 802ea94:	00005706 	br	802ebf4 <sosetopt+0x474>
+   case TCP_NODELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+ 802ea98:	e0bffa17 	ldw	r2,-24(fp)
+ 802ea9c:	10800983 	ldbu	r2,38(r2)
+ 802eaa0:	10803fcc 	andi	r2,r2,255
+ 802eaa4:	1080201c 	xori	r2,r2,128
+ 802eaa8:	10bfe004 	addi	r2,r2,-128
+ 802eaac:	10800060 	cmpeqi	r2,r2,1
+ 802eab0:	1000031e 	bne	r2,zero,802eac0 <sosetopt+0x340>
+      {
+         error = EINVAL;
+ 802eab4:	00800584 	movi	r2,22
+ 802eab8:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802eabc:	00004d06 	br	802ebf4 <sosetopt+0x474>
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+ 802eac0:	e0bffa17 	ldw	r2,-24(fp)
+ 802eac4:	10800117 	ldw	r2,4(r2)
+ 802eac8:	e0bffe15 	stw	r2,-8(fp)
+      tp = intotcpcb(inp);
+ 802eacc:	e0bffe17 	ldw	r2,-8(fp)
+ 802ead0:	10800917 	ldw	r2,36(r2)
+ 802ead4:	e0bffd15 	stw	r2,-12(fp)
+      if(!tp)
+ 802ead8:	e0bffd17 	ldw	r2,-12(fp)
+ 802eadc:	1000031e 	bne	r2,zero,802eaec <sosetopt+0x36c>
+      {
+         error = ENOTCONN;
+ 802eae0:	00802004 	movi	r2,128
+ 802eae4:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802eae8:	00004206 	br	802ebf4 <sosetopt+0x474>
+      }
+      /* try to make sure that the argument pointer is valid */
+      if (arg == NULL)
+ 802eaec:	e0bff817 	ldw	r2,-32(fp)
+ 802eaf0:	1000031e 	bne	r2,zero,802eb00 <sosetopt+0x380>
+      {
+         error = ENP_PARAM;
+ 802eaf4:	00bffd84 	movi	r2,-10
+ 802eaf8:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802eafc:	00003d06 	br	802ebf4 <sosetopt+0x474>
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (*(int *) arg)
+ 802eb00:	e0bff817 	ldw	r2,-32(fp)
+ 802eb04:	10800017 	ldw	r2,0(r2)
+ 802eb08:	10000726 	beq	r2,zero,802eb28 <sosetopt+0x3a8>
+         tp->t_flags |= TF_NODELAY;   /* Disable Nagle Algorithm */
+ 802eb0c:	e0bffd17 	ldw	r2,-12(fp)
+ 802eb10:	10800b0b 	ldhu	r2,44(r2)
+ 802eb14:	10800114 	ori	r2,r2,4
+ 802eb18:	1007883a 	mov	r3,r2
+ 802eb1c:	e0bffd17 	ldw	r2,-12(fp)
+ 802eb20:	10c00b0d 	sth	r3,44(r2)
+      else
+         tp->t_flags &= ~TF_NODELAY;  /* Enable Nagle Algorithm */
+
+      break;
+ 802eb24:	00003306 	br	802ebf4 <sosetopt+0x474>
+         tp->t_flags &= ~TF_NODELAY;  /* Enable Nagle Algorithm */
+ 802eb28:	e0bffd17 	ldw	r2,-12(fp)
+ 802eb2c:	10c00b0b 	ldhu	r3,44(r2)
+ 802eb30:	00bffec4 	movi	r2,-5
+ 802eb34:	1884703a 	and	r2,r3,r2
+ 802eb38:	1007883a 	mov	r3,r2
+ 802eb3c:	e0bffd17 	ldw	r2,-12(fp)
+ 802eb40:	10c00b0d 	sth	r3,44(r2)
+      break;
+ 802eb44:	00002b06 	br	802ebf4 <sosetopt+0x474>
+   case TCP_MAXSEG:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+ 802eb48:	e0bffa17 	ldw	r2,-24(fp)
+ 802eb4c:	10800983 	ldbu	r2,38(r2)
+ 802eb50:	10803fcc 	andi	r2,r2,255
+ 802eb54:	1080201c 	xori	r2,r2,128
+ 802eb58:	10bfe004 	addi	r2,r2,-128
+ 802eb5c:	10800060 	cmpeqi	r2,r2,1
+ 802eb60:	1000031e 	bne	r2,zero,802eb70 <sosetopt+0x3f0>
+      {
+         error = EINVAL;
+ 802eb64:	00800584 	movi	r2,22
+ 802eb68:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802eb6c:	00002106 	br	802ebf4 <sosetopt+0x474>
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+ 802eb70:	e0bffa17 	ldw	r2,-24(fp)
+ 802eb74:	10800117 	ldw	r2,4(r2)
+ 802eb78:	e0bffc15 	stw	r2,-16(fp)
+      tp = intotcpcb(inp);
+ 802eb7c:	e0bffc17 	ldw	r2,-16(fp)
+ 802eb80:	10800917 	ldw	r2,36(r2)
+ 802eb84:	e0bffb15 	stw	r2,-20(fp)
+      if(!tp)
+ 802eb88:	e0bffb17 	ldw	r2,-20(fp)
+ 802eb8c:	1000031e 	bne	r2,zero,802eb9c <sosetopt+0x41c>
+      {
+         error = ENOTCONN;
+ 802eb90:	00802004 	movi	r2,128
+ 802eb94:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802eb98:	00001606 	br	802ebf4 <sosetopt+0x474>
+      }
+      if (tp->t_state != TCPS_CLOSED)
+ 802eb9c:	e0bffb17 	ldw	r2,-20(fp)
+ 802eba0:	10800217 	ldw	r2,8(r2)
+ 802eba4:	10000326 	beq	r2,zero,802ebb4 <sosetopt+0x434>
+      {
+         error = EINVAL;
+ 802eba8:	00800584 	movi	r2,22
+ 802ebac:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802ebb0:	00001006 	br	802ebf4 <sosetopt+0x474>
+      }
+      tp->t_maxseg = *(int*)(arg);    /* set TCP MSS */
+ 802ebb4:	e0bff817 	ldw	r2,-32(fp)
+ 802ebb8:	10800017 	ldw	r2,0(r2)
+ 802ebbc:	1007883a 	mov	r3,r2
+ 802ebc0:	e0bffb17 	ldw	r2,-20(fp)
+ 802ebc4:	10c00a0d 	sth	r3,40(r2)
+      tp->t_flags |= TF_MAXSEG;   /* mark as user set max seg */
+ 802ebc8:	e0bffb17 	ldw	r2,-20(fp)
+ 802ebcc:	10800b0b 	ldhu	r2,44(r2)
+ 802ebd0:	10810014 	ori	r2,r2,1024
+ 802ebd4:	1007883a 	mov	r3,r2
+ 802ebd8:	e0bffb17 	ldw	r2,-20(fp)
+ 802ebdc:	10c00b0d 	sth	r3,44(r2)
+      break;
+ 802ebe0:	00000406 	br	802ebf4 <sosetopt+0x474>
+   }
+   default:
+      error = ENOPROTOOPT;
+ 802ebe4:	00801b44 	movi	r2,109
+ 802ebe8:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 802ebec:	00000106 	br	802ebf4 <sosetopt+0x474>
+      break;
+ 802ebf0:	0001883a 	nop
+   }
+bad:
+   return (error);
+ 802ebf4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802ebf8:	e037883a 	mov	sp,fp
+ 802ebfc:	dfc00117 	ldw	ra,4(sp)
+ 802ec00:	df000017 	ldw	fp,0(sp)
+ 802ec04:	dec00204 	addi	sp,sp,8
+ 802ec08:	f800283a 	ret
+
+0802ec0c <sogetopt>:
+
+int
+sogetopt(struct socket * so, 
+   int   optname,
+   void *   val)
+{
+ 802ec0c:	defff504 	addi	sp,sp,-44
+ 802ec10:	dfc00a15 	stw	ra,40(sp)
+ 802ec14:	df000915 	stw	fp,36(sp)
+ 802ec18:	df000904 	addi	fp,sp,36
+ 802ec1c:	e13ff915 	stw	r4,-28(fp)
+ 802ec20:	e17ff815 	stw	r5,-32(fp)
+ 802ec24:	e1bff715 	stw	r6,-36(fp)
+   int   error =  0;
+ 802ec28:	e03fff15 	stw	zero,-4(fp)
+
+   /* sanity check the val parameter */
+   if (!val)
+ 802ec2c:	e0bff717 	ldw	r2,-36(fp)
+ 802ec30:	1000021e 	bne	r2,zero,802ec3c <sogetopt+0x30>
+   {
+      return ENP_PARAM;
+ 802ec34:	00bffd84 	movi	r2,-10
+ 802ec38:	00013706 	br	802f118 <sogetopt+0x50c>
+   }
+
+   switch (optname) 
+ 802ec3c:	e0bff817 	ldw	r2,-32(fp)
+ 802ec40:	108400e0 	cmpeqi	r2,r2,4099
+ 802ec44:	10008e1e 	bne	r2,zero,802ee80 <sogetopt+0x274>
+ 802ec48:	e0bff817 	ldw	r2,-32(fp)
+ 802ec4c:	10840108 	cmpgei	r2,r2,4100
+ 802ec50:	10002e1e 	bne	r2,zero,802ed0c <sogetopt+0x100>
+ 802ec54:	e0bff817 	ldw	r2,-32(fp)
+ 802ec58:	10800420 	cmpeqi	r2,r2,16
+ 802ec5c:	1000801e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ec60:	e0bff817 	ldw	r2,-32(fp)
+ 802ec64:	10800448 	cmpgei	r2,r2,17
+ 802ec68:	1000111e 	bne	r2,zero,802ecb0 <sogetopt+0xa4>
+ 802ec6c:	e0bff817 	ldw	r2,-32(fp)
+ 802ec70:	10800220 	cmpeqi	r2,r2,8
+ 802ec74:	10007a1e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ec78:	e0bff817 	ldw	r2,-32(fp)
+ 802ec7c:	10800248 	cmpgei	r2,r2,9
+ 802ec80:	1000071e 	bne	r2,zero,802eca0 <sogetopt+0x94>
+ 802ec84:	e0bff817 	ldw	r2,-32(fp)
+ 802ec88:	108000a0 	cmpeqi	r2,r2,2
+ 802ec8c:	1000ee1e 	bne	r2,zero,802f048 <sogetopt+0x43c>
+ 802ec90:	e0bff817 	ldw	r2,-32(fp)
+ 802ec94:	10800120 	cmpeqi	r2,r2,4
+ 802ec98:	1000711e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ec9c:	00011b06 	br	802f10c <sogetopt+0x500>
+ 802eca0:	e0bff817 	ldw	r2,-32(fp)
+ 802eca4:	10800308 	cmpgei	r2,r2,12
+ 802eca8:	1001181e 	bne	r2,zero,802f10c <sogetopt+0x500>
+ 802ecac:	0000e006 	br	802f030 <sogetopt+0x424>
+ 802ecb0:	e0bff817 	ldw	r2,-32(fp)
+ 802ecb4:	10804020 	cmpeqi	r2,r2,256
+ 802ecb8:	1000691e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ecbc:	e0bff817 	ldw	r2,-32(fp)
+ 802ecc0:	10804048 	cmpgei	r2,r2,257
+ 802ecc4:	1000071e 	bne	r2,zero,802ece4 <sogetopt+0xd8>
+ 802ecc8:	e0bff817 	ldw	r2,-32(fp)
+ 802eccc:	10800820 	cmpeqi	r2,r2,32
+ 802ecd0:	1000631e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ecd4:	e0bff817 	ldw	r2,-32(fp)
+ 802ecd8:	10802020 	cmpeqi	r2,r2,128
+ 802ecdc:	1000511e 	bne	r2,zero,802ee24 <sogetopt+0x218>
+ 802ece0:	00010a06 	br	802f10c <sogetopt+0x500>
+ 802ece4:	e0bff817 	ldw	r2,-32(fp)
+ 802ece8:	10840060 	cmpeqi	r2,r2,4097
+ 802ecec:	1000701e 	bne	r2,zero,802eeb0 <sogetopt+0x2a4>
+ 802ecf0:	e0bff817 	ldw	r2,-32(fp)
+ 802ecf4:	10840088 	cmpgei	r2,r2,4098
+ 802ecf8:	1000731e 	bne	r2,zero,802eec8 <sogetopt+0x2bc>
+ 802ecfc:	e0bff817 	ldw	r2,-32(fp)
+ 802ed00:	10808020 	cmpeqi	r2,r2,512
+ 802ed04:	1000561e 	bne	r2,zero,802ee60 <sogetopt+0x254>
+ 802ed08:	00010006 	br	802f10c <sogetopt+0x500>
+ 802ed0c:	e0bff817 	ldw	r2,-32(fp)
+ 802ed10:	10840420 	cmpeqi	r2,r2,4112
+ 802ed14:	10008d1e 	bne	r2,zero,802ef4c <sogetopt+0x340>
+ 802ed18:	e0bff817 	ldw	r2,-32(fp)
+ 802ed1c:	10840448 	cmpgei	r2,r2,4113
+ 802ed20:	1000171e 	bne	r2,zero,802ed80 <sogetopt+0x174>
+ 802ed24:	e0bff817 	ldw	r2,-32(fp)
+ 802ed28:	108401a0 	cmpeqi	r2,r2,4102
+ 802ed2c:	1000a71e 	bne	r2,zero,802efcc <sogetopt+0x3c0>
+ 802ed30:	e0bff817 	ldw	r2,-32(fp)
+ 802ed34:	108401c8 	cmpgei	r2,r2,4103
+ 802ed38:	1000071e 	bne	r2,zero,802ed58 <sogetopt+0x14c>
+ 802ed3c:	e0bff817 	ldw	r2,-32(fp)
+ 802ed40:	10840120 	cmpeqi	r2,r2,4100
+ 802ed44:	1000541e 	bne	r2,zero,802ee98 <sogetopt+0x28c>
+ 802ed48:	e0bff817 	ldw	r2,-32(fp)
+ 802ed4c:	10840160 	cmpeqi	r2,r2,4101
+ 802ed50:	1000991e 	bne	r2,zero,802efb8 <sogetopt+0x3ac>
+ 802ed54:	0000ed06 	br	802f10c <sogetopt+0x500>
+ 802ed58:	e0bff817 	ldw	r2,-32(fp)
+ 802ed5c:	10840220 	cmpeqi	r2,r2,4104
+ 802ed60:	10006b1e 	bne	r2,zero,802ef10 <sogetopt+0x304>
+ 802ed64:	e0bff817 	ldw	r2,-32(fp)
+ 802ed68:	10840210 	cmplti	r2,r2,4104
+ 802ed6c:	1000701e 	bne	r2,zero,802ef30 <sogetopt+0x324>
+ 802ed70:	e0bff817 	ldw	r2,-32(fp)
+ 802ed74:	10840260 	cmpeqi	r2,r2,4105
+ 802ed78:	1000991e 	bne	r2,zero,802efe0 <sogetopt+0x3d4>
+ 802ed7c:	0000e306 	br	802f10c <sogetopt+0x500>
+ 802ed80:	e0bff817 	ldw	r2,-32(fp)
+ 802ed84:	108404e0 	cmpeqi	r2,r2,4115
+ 802ed88:	1000141e 	bne	r2,zero,802eddc <sogetopt+0x1d0>
+ 802ed8c:	e0bff817 	ldw	r2,-32(fp)
+ 802ed90:	10840508 	cmpgei	r2,r2,4116
+ 802ed94:	1000071e 	bne	r2,zero,802edb4 <sogetopt+0x1a8>
+ 802ed98:	e0bff817 	ldw	r2,-32(fp)
+ 802ed9c:	10840460 	cmpeqi	r2,r2,4113
+ 802eda0:	10004f1e 	bne	r2,zero,802eee0 <sogetopt+0x2d4>
+ 802eda4:	e0bff817 	ldw	r2,-32(fp)
+ 802eda8:	108404a0 	cmpeqi	r2,r2,4114
+ 802edac:	1000521e 	bne	r2,zero,802eef8 <sogetopt+0x2ec>
+ 802edb0:	0000d606 	br	802f10c <sogetopt+0x500>
+ 802edb4:	e0bff817 	ldw	r2,-32(fp)
+ 802edb8:	108800e0 	cmpeqi	r2,r2,8195
+ 802edbc:	1000631e 	bne	r2,zero,802ef4c <sogetopt+0x340>
+ 802edc0:	e0bff817 	ldw	r2,-32(fp)
+ 802edc4:	10880120 	cmpeqi	r2,r2,8196
+ 802edc8:	1000aa1e 	bne	r2,zero,802f074 <sogetopt+0x468>
+ 802edcc:	e0bff817 	ldw	r2,-32(fp)
+ 802edd0:	108405a0 	cmpeqi	r2,r2,4118
+ 802edd4:	10008a1e 	bne	r2,zero,802f000 <sogetopt+0x3f4>
+ 802edd8:	0000cc06 	br	802f10c <sogetopt+0x500>
+   {
+   case SO_MYADDR:
+      /* Get my IP address. */
+      if (so->so_state & SS_ISCONNECTED)
+ 802eddc:	e0bff917 	ldw	r2,-28(fp)
+ 802ede0:	1080088b 	ldhu	r2,34(r2)
+ 802ede4:	10bfffcc 	andi	r2,r2,65535
+ 802ede8:	1080008c 	andi	r2,r2,2
+ 802edec:	10000726 	beq	r2,zero,802ee0c <sogetopt+0x200>
+      {
+         *(u_long *)val = so->so_pcb->ifp->n_ipaddr;
+ 802edf0:	e0bff917 	ldw	r2,-28(fp)
+ 802edf4:	10800117 	ldw	r2,4(r2)
+ 802edf8:	10800a17 	ldw	r2,40(r2)
+ 802edfc:	10c00a17 	ldw	r3,40(r2)
+ 802ee00:	e0bff717 	ldw	r2,-36(fp)
+ 802ee04:	10c00015 	stw	r3,0(r2)
+      }
+      else  /* not connected, use first iface */
+         *(u_long *)val = nets[0]->n_ipaddr;
+      break;
+ 802ee08:	0000c206 	br	802f114 <sogetopt+0x508>
+         *(u_long *)val = nets[0]->n_ipaddr;
+ 802ee0c:	008201b4 	movhi	r2,2054
+ 802ee10:	10b77017 	ldw	r2,-8768(r2)
+ 802ee14:	10c00a17 	ldw	r3,40(r2)
+ 802ee18:	e0bff717 	ldw	r2,-36(fp)
+ 802ee1c:	10c00015 	stw	r3,0(r2)
+      break;
+ 802ee20:	0000bc06 	br	802f114 <sogetopt+0x508>
+   case SO_LINGER:
+      {
+         struct linger *   l  =  (struct  linger *)val;
+ 802ee24:	e0bff717 	ldw	r2,-36(fp)
+ 802ee28:	e0bffe15 	stw	r2,-8(fp)
+         l->l_onoff = so->so_options & SO_LINGER;
+ 802ee2c:	e0bff917 	ldw	r2,-28(fp)
+ 802ee30:	10800417 	ldw	r2,16(r2)
+ 802ee34:	10c0200c 	andi	r3,r2,128
+ 802ee38:	e0bffe17 	ldw	r2,-8(fp)
+ 802ee3c:	10c00015 	stw	r3,0(r2)
+         l->l_linger = so->so_linger;
+ 802ee40:	e0bff917 	ldw	r2,-28(fp)
+ 802ee44:	1080080b 	ldhu	r2,32(r2)
+ 802ee48:	10ffffcc 	andi	r3,r2,65535
+ 802ee4c:	18e0001c 	xori	r3,r3,32768
+ 802ee50:	18e00004 	addi	r3,r3,-32768
+ 802ee54:	e0bffe17 	ldw	r2,-8(fp)
+ 802ee58:	10c00115 	stw	r3,4(r2)
+      }
+      break;
+ 802ee5c:	0000ad06 	br	802f114 <sogetopt+0x508>
+   case SO_OOBINLINE:
+   case SO_DONTROUTE:
+   case SO_REUSEADDR:
+   case SO_BROADCAST:
+   case SO_TCPSACK:
+      *(int *)val = so->so_options & optname;
+ 802ee60:	e0bff917 	ldw	r2,-28(fp)
+ 802ee64:	10c00417 	ldw	r3,16(r2)
+ 802ee68:	e0bff817 	ldw	r2,-32(fp)
+ 802ee6c:	1884703a 	and	r2,r3,r2
+ 802ee70:	1007883a 	mov	r3,r2
+ 802ee74:	e0bff717 	ldw	r2,-36(fp)
+ 802ee78:	10c00015 	stw	r3,0(r2)
+      break;
+ 802ee7c:	0000a506 	br	802f114 <sogetopt+0x508>
+
+   case SO_SNDLOWAT:
+      *(int *)val = (int)so->so_snd.sb_lowat;
+ 802ee80:	e0bff917 	ldw	r2,-28(fp)
+ 802ee84:	10801617 	ldw	r2,88(r2)
+ 802ee88:	1007883a 	mov	r3,r2
+ 802ee8c:	e0bff717 	ldw	r2,-36(fp)
+ 802ee90:	10c00015 	stw	r3,0(r2)
+      break;
+ 802ee94:	00009f06 	br	802f114 <sogetopt+0x508>
+
+   case SO_RCVLOWAT:
+      *(int *)val = (int)so->so_rcv.sb_lowat;
+ 802ee98:	e0bff917 	ldw	r2,-28(fp)
+ 802ee9c:	10800e17 	ldw	r2,56(r2)
+ 802eea0:	1007883a 	mov	r3,r2
+ 802eea4:	e0bff717 	ldw	r2,-36(fp)
+ 802eea8:	10c00015 	stw	r3,0(r2)
+      break;
+ 802eeac:	00009906 	br	802f114 <sogetopt+0x508>
+
+   case SO_SNDBUF:
+      *(int *)val = (int)so->so_snd.sb_hiwat;
+ 802eeb0:	e0bff917 	ldw	r2,-28(fp)
+ 802eeb4:	10801317 	ldw	r2,76(r2)
+ 802eeb8:	1007883a 	mov	r3,r2
+ 802eebc:	e0bff717 	ldw	r2,-36(fp)
+ 802eec0:	10c00015 	stw	r3,0(r2)
+      break;
+ 802eec4:	00009306 	br	802f114 <sogetopt+0x508>
+
+   case SO_RCVBUF:
+      *(int *)val = (int)so->so_rcv.sb_hiwat;
+ 802eec8:	e0bff917 	ldw	r2,-28(fp)
+ 802eecc:	10800b17 	ldw	r2,44(r2)
+ 802eed0:	1007883a 	mov	r3,r2
+ 802eed4:	e0bff717 	ldw	r2,-36(fp)
+ 802eed8:	10c00015 	stw	r3,0(r2)
+      break;
+ 802eedc:	00008d06 	br	802f114 <sogetopt+0x508>
+
+   case SO_RXDATA:   /* added, JB */
+      *(int *)val = (int)so->so_rcv.sb_cc;
+ 802eee0:	e0bff917 	ldw	r2,-28(fp)
+ 802eee4:	10800a17 	ldw	r2,40(r2)
+ 802eee8:	1007883a 	mov	r3,r2
+ 802eeec:	e0bff717 	ldw	r2,-36(fp)
+ 802eef0:	10c00015 	stw	r3,0(r2)
+      break;
+ 802eef4:	00008706 	br	802f114 <sogetopt+0x508>
+
+   case SO_TXDATA:   /* added for rel 1.8 */
+      *(int *)val = (int)so->so_snd.sb_cc;
+ 802eef8:	e0bff917 	ldw	r2,-28(fp)
+ 802eefc:	10801217 	ldw	r2,72(r2)
+ 802ef00:	1007883a 	mov	r3,r2
+ 802ef04:	e0bff717 	ldw	r2,-36(fp)
+ 802ef08:	10c00015 	stw	r3,0(r2)
+      break;
+ 802ef0c:	00008106 	br	802f114 <sogetopt+0x508>
+
+   case SO_TYPE:
+      *(int *)val = so->so_type;
+ 802ef10:	e0bff917 	ldw	r2,-28(fp)
+ 802ef14:	10800983 	ldbu	r2,38(r2)
+ 802ef18:	10c03fcc 	andi	r3,r2,255
+ 802ef1c:	18c0201c 	xori	r3,r3,128
+ 802ef20:	18ffe004 	addi	r3,r3,-128
+ 802ef24:	e0bff717 	ldw	r2,-36(fp)
+ 802ef28:	10c00015 	stw	r3,0(r2)
+      break;
+ 802ef2c:	00007906 	br	802f114 <sogetopt+0x508>
+
+   case SO_ERROR:
+      *(int *)val = so->so_error;
+ 802ef30:	e0bff917 	ldw	r2,-28(fp)
+ 802ef34:	10c00617 	ldw	r3,24(r2)
+ 802ef38:	e0bff717 	ldw	r2,-36(fp)
+ 802ef3c:	10c00015 	stw	r3,0(r2)
+      so->so_error = 0;
+ 802ef40:	e0bff917 	ldw	r2,-28(fp)
+ 802ef44:	10000615 	stw	zero,24(r2)
+      break;
+ 802ef48:	00007206 	br	802f114 <sogetopt+0x508>
+   case TCP_MAXSEG:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+ 802ef4c:	e0bff917 	ldw	r2,-28(fp)
+ 802ef50:	10800983 	ldbu	r2,38(r2)
+ 802ef54:	10803fcc 	andi	r2,r2,255
+ 802ef58:	1080201c 	xori	r2,r2,128
+ 802ef5c:	10bfe004 	addi	r2,r2,-128
+ 802ef60:	10800060 	cmpeqi	r2,r2,1
+ 802ef64:	1000031e 	bne	r2,zero,802ef74 <sogetopt+0x368>
+      {
+         error = EINVAL;
+ 802ef68:	00800584 	movi	r2,22
+ 802ef6c:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802ef70:	00006806 	br	802f114 <sogetopt+0x508>
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+ 802ef74:	e0bff917 	ldw	r2,-28(fp)
+ 802ef78:	10800117 	ldw	r2,4(r2)
+ 802ef7c:	e0bffd15 	stw	r2,-12(fp)
+      tp = intotcpcb(inp);
+ 802ef80:	e0bffd17 	ldw	r2,-12(fp)
+ 802ef84:	10800917 	ldw	r2,36(r2)
+ 802ef88:	e0bffc15 	stw	r2,-16(fp)
+      if(!tp)
+ 802ef8c:	e0bffc17 	ldw	r2,-16(fp)
+ 802ef90:	1000031e 	bne	r2,zero,802efa0 <sogetopt+0x394>
+      {
+         error = ENOTCONN;
+ 802ef94:	00802004 	movi	r2,128
+ 802ef98:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802ef9c:	00005d06 	br	802f114 <sogetopt+0x508>
+      }
+      *(int *)val = tp->t_maxseg;     /* Fill in TCP MSS for current socket */
+ 802efa0:	e0bffc17 	ldw	r2,-16(fp)
+ 802efa4:	10800a0b 	ldhu	r2,40(r2)
+ 802efa8:	10ffffcc 	andi	r3,r2,65535
+ 802efac:	e0bff717 	ldw	r2,-36(fp)
+ 802efb0:	10c00015 	stw	r3,0(r2)
+      break;
+ 802efb4:	00005706 	br	802f114 <sogetopt+0x508>
+   }
+ 
+   case SO_SNDTIMEO:
+      *(short*)val = so->so_snd.sb_timeo;
+ 802efb8:	e0bff917 	ldw	r2,-28(fp)
+ 802efbc:	10c0198b 	ldhu	r3,102(r2)
+ 802efc0:	e0bff717 	ldw	r2,-36(fp)
+ 802efc4:	10c0000d 	sth	r3,0(r2)
+      break;
+ 802efc8:	00005206 	br	802f114 <sogetopt+0x508>
+
+   case SO_RCVTIMEO:
+      *(short*)val = so->so_rcv.sb_timeo;
+ 802efcc:	e0bff917 	ldw	r2,-28(fp)
+ 802efd0:	10c0118b 	ldhu	r3,70(r2)
+ 802efd4:	e0bff717 	ldw	r2,-36(fp)
+ 802efd8:	10c0000d 	sth	r3,0(r2)
+      break;
+ 802efdc:	00004d06 	br	802f114 <sogetopt+0x508>
+
+   case SO_HOPCNT:
+      *(int *)val = so->so_hopcnt;
+ 802efe0:	e0bff917 	ldw	r2,-28(fp)
+ 802efe4:	108009c3 	ldbu	r2,39(r2)
+ 802efe8:	10c03fcc 	andi	r3,r2,255
+ 802efec:	18c0201c 	xori	r3,r3,128
+ 802eff0:	18ffe004 	addi	r3,r3,-128
+ 802eff4:	e0bff717 	ldw	r2,-36(fp)
+ 802eff8:	10c00015 	stw	r3,0(r2)
+      break;
+ 802effc:	00004506 	br	802f114 <sogetopt+0x508>
+
+   case SO_NONBLOCK:    /* get blocking mode according to val */
+      /* if the non-blocking I/O bit is set in the state */
+      if (so->so_state & SS_NBIO)
+ 802f000:	e0bff917 	ldw	r2,-28(fp)
+ 802f004:	1080088b 	ldhu	r2,34(r2)
+ 802f008:	10bfffcc 	andi	r2,r2,65535
+ 802f00c:	1080400c 	andi	r2,r2,256
+ 802f010:	10000426 	beq	r2,zero,802f024 <sogetopt+0x418>
+         *(int *)val = 1;   /* return 1 in val */
+ 802f014:	e0bff717 	ldw	r2,-36(fp)
+ 802f018:	00c00044 	movi	r3,1
+ 802f01c:	10c00015 	stw	r3,0(r2)
+      else
+         *(int *)val = 0;     /* return 0 in val */
+      break;
+ 802f020:	00003c06 	br	802f114 <sogetopt+0x508>
+         *(int *)val = 0;     /* return 0 in val */
+ 802f024:	e0bff717 	ldw	r2,-36(fp)
+ 802f028:	10000015 	stw	zero,0(r2)
+      break;
+ 802f02c:	00003906 	br	802f114 <sogetopt+0x508>
+#ifdef IP_MULTICAST
+
+   case IP_MULTICAST_IF:
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+      error = ip_getmoptions(optname, so, val);
+ 802f030:	e1bff717 	ldw	r6,-36(fp)
+ 802f034:	e17ff917 	ldw	r5,-28(fp)
+ 802f038:	e13ff817 	ldw	r4,-32(fp)
+ 802f03c:	803ed640 	call	803ed64 <ip_getmoptions>
+ 802f040:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 802f044:	00003306 	br	802f114 <sogetopt+0x508>
+
+#ifdef IP_RAW
+
+   case IP_HDRINCL:
+      /* indicate based on header-include flag in socket state */
+      if (so->so_options & SO_HDRINCL)
+ 802f048:	e0bff917 	ldw	r2,-28(fp)
+ 802f04c:	10800417 	ldw	r2,16(r2)
+ 802f050:	1088000c 	andi	r2,r2,8192
+ 802f054:	10000426 	beq	r2,zero,802f068 <sogetopt+0x45c>
+         *(int *)val = 1;
+ 802f058:	e0bff717 	ldw	r2,-36(fp)
+ 802f05c:	00c00044 	movi	r3,1
+ 802f060:	10c00015 	stw	r3,0(r2)
+      else
+         *(int *)val = 0;
+      break;
+ 802f064:	00002b06 	br	802f114 <sogetopt+0x508>
+         *(int *)val = 0;
+ 802f068:	e0bff717 	ldw	r2,-36(fp)
+ 802f06c:	10000015 	stw	zero,0(r2)
+      break;
+ 802f070:	00002806 	br	802f114 <sogetopt+0x508>
+   case TCP_NODELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+ 802f074:	e0bff917 	ldw	r2,-28(fp)
+ 802f078:	10800983 	ldbu	r2,38(r2)
+ 802f07c:	10803fcc 	andi	r2,r2,255
+ 802f080:	1080201c 	xori	r2,r2,128
+ 802f084:	10bfe004 	addi	r2,r2,-128
+ 802f088:	10800060 	cmpeqi	r2,r2,1
+ 802f08c:	1000031e 	bne	r2,zero,802f09c <sogetopt+0x490>
+      {
+         error = EINVAL;
+ 802f090:	00800584 	movi	r2,22
+ 802f094:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802f098:	00001e06 	br	802f114 <sogetopt+0x508>
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+ 802f09c:	e0bff917 	ldw	r2,-28(fp)
+ 802f0a0:	10800117 	ldw	r2,4(r2)
+ 802f0a4:	e0bffb15 	stw	r2,-20(fp)
+      tp = intotcpcb(inp);
+ 802f0a8:	e0bffb17 	ldw	r2,-20(fp)
+ 802f0ac:	10800917 	ldw	r2,36(r2)
+ 802f0b0:	e0bffa15 	stw	r2,-24(fp)
+      if (!tp)
+ 802f0b4:	e0bffa17 	ldw	r2,-24(fp)
+ 802f0b8:	1000031e 	bne	r2,zero,802f0c8 <sogetopt+0x4bc>
+      {
+         error = ENOTCONN;
+ 802f0bc:	00802004 	movi	r2,128
+ 802f0c0:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802f0c4:	00001306 	br	802f114 <sogetopt+0x508>
+      }
+      /* try to make sure that the argument pointer is valid */
+      if (val == NULL)
+ 802f0c8:	e0bff717 	ldw	r2,-36(fp)
+ 802f0cc:	1000031e 	bne	r2,zero,802f0dc <sogetopt+0x4d0>
+      {
+         error = ENP_PARAM;
+ 802f0d0:	00bffd84 	movi	r2,-10
+ 802f0d4:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 802f0d8:	00000e06 	br	802f114 <sogetopt+0x508>
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (tp->t_flags & TF_NODELAY)
+ 802f0dc:	e0bffa17 	ldw	r2,-24(fp)
+ 802f0e0:	10800b0b 	ldhu	r2,44(r2)
+ 802f0e4:	10bfffcc 	andi	r2,r2,65535
+ 802f0e8:	1080010c 	andi	r2,r2,4
+ 802f0ec:	10000426 	beq	r2,zero,802f100 <sogetopt+0x4f4>
+         *(int *)val = 1;  /* Nagle Algorithm is Enabled */
+ 802f0f0:	e0bff717 	ldw	r2,-36(fp)
+ 802f0f4:	00c00044 	movi	r3,1
+ 802f0f8:	10c00015 	stw	r3,0(r2)
+      else
+         *(int *)val = 0;  /* Nagle Algorithm is NOT Enabled */
+
+      break;
+ 802f0fc:	00000506 	br	802f114 <sogetopt+0x508>
+         *(int *)val = 0;  /* Nagle Algorithm is NOT Enabled */
+ 802f100:	e0bff717 	ldw	r2,-36(fp)
+ 802f104:	10000015 	stw	zero,0(r2)
+      break;
+ 802f108:	00000206 	br	802f114 <sogetopt+0x508>
+   }
+
+   default:
+      return ENOPROTOOPT;
+ 802f10c:	00801b44 	movi	r2,109
+ 802f110:	00000106 	br	802f118 <sogetopt+0x50c>
+   }
+   return error;     /* no error */
+ 802f114:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 802f118:	e037883a 	mov	sp,fp
+ 802f11c:	dfc00117 	ldw	ra,4(sp)
+ 802f120:	df000017 	ldw	fp,0(sp)
+ 802f124:	dec00204 	addi	sp,sp,8
+ 802f128:	f800283a 	ret
+
+0802f12c <sohasoutofband>:
+ * RETURNS: 
+ */
+
+void
+sohasoutofband(struct socket * so)
+{
+ 802f12c:	defffd04 	addi	sp,sp,-12
+ 802f130:	dfc00215 	stw	ra,8(sp)
+ 802f134:	df000115 	stw	fp,4(sp)
+ 802f138:	df000104 	addi	fp,sp,4
+ 802f13c:	e13fff15 	stw	r4,-4(fp)
+   so->so_error = EHAVEOOB;   /* WILL be picked up by the socket */
+ 802f140:	e0bfff17 	ldw	r2,-4(fp)
+ 802f144:	00c03644 	movi	r3,217
+ 802f148:	10c00615 	stw	r3,24(r2)
+   sorwakeup (so);
+ 802f14c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f150:	10800a04 	addi	r2,r2,40
+ 802f154:	100b883a 	mov	r5,r2
+ 802f158:	e13fff17 	ldw	r4,-4(fp)
+ 802f15c:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f160:	0001883a 	nop
+ 802f164:	e037883a 	mov	sp,fp
+ 802f168:	dfc00117 	ldw	ra,4(sp)
+ 802f16c:	df000017 	ldw	fp,0(sp)
+ 802f170:	dec00204 	addi	sp,sp,8
+ 802f174:	f800283a 	ret
+
+0802f178 <soisconnecting>:
+ * RETURNS: 
+ */
+
+void
+soisconnecting(struct socket * so)
+{
+ 802f178:	defffd04 	addi	sp,sp,-12
+ 802f17c:	dfc00215 	stw	ra,8(sp)
+ 802f180:	df000115 	stw	fp,4(sp)
+ 802f184:	df000104 	addi	fp,sp,4
+ 802f188:	e13fff15 	stw	r4,-4(fp)
+   so->so_state &= ~(SS_ISCONNECTED|SS_ISDISCONNECTING);
+ 802f18c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f190:	10c0088b 	ldhu	r3,34(r2)
+ 802f194:	00bffd44 	movi	r2,-11
+ 802f198:	1884703a 	and	r2,r3,r2
+ 802f19c:	1007883a 	mov	r3,r2
+ 802f1a0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f1a4:	10c0088d 	sth	r3,34(r2)
+   so->so_state |= SS_ISCONNECTING;
+ 802f1a8:	e0bfff17 	ldw	r2,-4(fp)
+ 802f1ac:	1080088b 	ldhu	r2,34(r2)
+ 802f1b0:	10800114 	ori	r2,r2,4
+ 802f1b4:	1007883a 	mov	r3,r2
+ 802f1b8:	e0bfff17 	ldw	r2,-4(fp)
+ 802f1bc:	10c0088d 	sth	r3,34(r2)
+   tcp_wakeup ((char *)&so->so_timeo);
+ 802f1c0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f1c4:	10800904 	addi	r2,r2,36
+ 802f1c8:	1009883a 	mov	r4,r2
+ 802f1cc:	8027ba00 	call	8027ba0 <tcp_wakeup>
+}
+ 802f1d0:	0001883a 	nop
+ 802f1d4:	e037883a 	mov	sp,fp
+ 802f1d8:	dfc00117 	ldw	ra,4(sp)
+ 802f1dc:	df000017 	ldw	fp,0(sp)
+ 802f1e0:	dec00204 	addi	sp,sp,8
+ 802f1e4:	f800283a 	ret
+
+0802f1e8 <soisconnected>:
+ * RETURNS: 
+ */
+
+void
+soisconnected(struct socket * so)
+{
+ 802f1e8:	defffc04 	addi	sp,sp,-16
+ 802f1ec:	dfc00315 	stw	ra,12(sp)
+ 802f1f0:	df000215 	stw	fp,8(sp)
+ 802f1f4:	df000204 	addi	fp,sp,8
+ 802f1f8:	e13ffe15 	stw	r4,-8(fp)
+   struct socket *   head  =  so->so_head;
+ 802f1fc:	e0bffe17 	ldw	r2,-8(fp)
+ 802f200:	10801b17 	ldw	r2,108(r2)
+ 802f204:	e0bfff15 	stw	r2,-4(fp)
+
+   if (head) 
+ 802f208:	e0bfff17 	ldw	r2,-4(fp)
+ 802f20c:	10001426 	beq	r2,zero,802f260 <soisconnected+0x78>
+   {
+      if (soqremque(so, 0) == 0)
+ 802f210:	000b883a 	mov	r5,zero
+ 802f214:	e13ffe17 	ldw	r4,-8(fp)
+ 802f218:	802f6ec0 	call	802f6ec <soqremque>
+ 802f21c:	1000031e 	bne	r2,zero,802f22c <soisconnected+0x44>
+         panic("soisconnected");
+ 802f220:	01020174 	movhi	r4,2053
+ 802f224:	212a8a04 	addi	r4,r4,-21976
+ 802f228:	80271780 	call	8027178 <panic>
+      soqinsque(head, so, 1);
+ 802f22c:	01800044 	movi	r6,1
+ 802f230:	e17ffe17 	ldw	r5,-8(fp)
+ 802f234:	e13fff17 	ldw	r4,-4(fp)
+ 802f238:	802f6400 	call	802f640 <soqinsque>
+      sorwakeup(head);
+ 802f23c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f240:	10800a04 	addi	r2,r2,40
+ 802f244:	100b883a 	mov	r5,r2
+ 802f248:	e13fff17 	ldw	r4,-4(fp)
+ 802f24c:	802f94c0 	call	802f94c <sbwakeup>
+      tcp_wakeup ((char *)&head->so_timeo);
+ 802f250:	e0bfff17 	ldw	r2,-4(fp)
+ 802f254:	10800904 	addi	r2,r2,36
+ 802f258:	1009883a 	mov	r4,r2
+ 802f25c:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   }
+
+   so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+ 802f260:	e0bffe17 	ldw	r2,-8(fp)
+ 802f264:	10c0088b 	ldhu	r3,34(r2)
+ 802f268:	00bffcc4 	movi	r2,-13
+ 802f26c:	1884703a 	and	r2,r3,r2
+ 802f270:	1007883a 	mov	r3,r2
+ 802f274:	e0bffe17 	ldw	r2,-8(fp)
+ 802f278:	10c0088d 	sth	r3,34(r2)
+   so->so_state |= SS_ISCONNECTED;
+ 802f27c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f280:	1080088b 	ldhu	r2,34(r2)
+ 802f284:	10800094 	ori	r2,r2,2
+ 802f288:	1007883a 	mov	r3,r2
+ 802f28c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f290:	10c0088d 	sth	r3,34(r2)
+   so->so_error = 0;
+ 802f294:	e0bffe17 	ldw	r2,-8(fp)
+ 802f298:	10000615 	stw	zero,24(r2)
+   tcp_wakeup  ((char *)&so->so_timeo);
+ 802f29c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f2a0:	10800904 	addi	r2,r2,36
+ 802f2a4:	1009883a 	mov	r4,r2
+ 802f2a8:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   sorwakeup (so);
+ 802f2ac:	e0bffe17 	ldw	r2,-8(fp)
+ 802f2b0:	10800a04 	addi	r2,r2,40
+ 802f2b4:	100b883a 	mov	r5,r2
+ 802f2b8:	e13ffe17 	ldw	r4,-8(fp)
+ 802f2bc:	802f94c0 	call	802f94c <sbwakeup>
+   sowwakeup (so);
+ 802f2c0:	e0bffe17 	ldw	r2,-8(fp)
+ 802f2c4:	10801204 	addi	r2,r2,72
+ 802f2c8:	100b883a 	mov	r5,r2
+ 802f2cc:	e13ffe17 	ldw	r4,-8(fp)
+ 802f2d0:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f2d4:	0001883a 	nop
+ 802f2d8:	e037883a 	mov	sp,fp
+ 802f2dc:	dfc00117 	ldw	ra,4(sp)
+ 802f2e0:	df000017 	ldw	fp,0(sp)
+ 802f2e4:	dec00204 	addi	sp,sp,8
+ 802f2e8:	f800283a 	ret
+
+0802f2ec <soisdisconnecting>:
+ * RETURNS: 
+ */
+
+void
+soisdisconnecting(struct socket * so)
+{
+ 802f2ec:	defffd04 	addi	sp,sp,-12
+ 802f2f0:	dfc00215 	stw	ra,8(sp)
+ 802f2f4:	df000115 	stw	fp,4(sp)
+ 802f2f8:	df000104 	addi	fp,sp,4
+ 802f2fc:	e13fff15 	stw	r4,-4(fp)
+   so->so_state &= ~SS_ISCONNECTING;
+ 802f300:	e0bfff17 	ldw	r2,-4(fp)
+ 802f304:	10c0088b 	ldhu	r3,34(r2)
+ 802f308:	00bffec4 	movi	r2,-5
+ 802f30c:	1884703a 	and	r2,r3,r2
+ 802f310:	1007883a 	mov	r3,r2
+ 802f314:	e0bfff17 	ldw	r2,-4(fp)
+ 802f318:	10c0088d 	sth	r3,34(r2)
+   so->so_state |= (SS_ISDISCONNECTING|SS_CANTRCVMORE|SS_CANTSENDMORE);
+ 802f31c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f320:	1080088b 	ldhu	r2,34(r2)
+ 802f324:	10800e14 	ori	r2,r2,56
+ 802f328:	1007883a 	mov	r3,r2
+ 802f32c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f330:	10c0088d 	sth	r3,34(r2)
+   tcp_wakeup  ((char *)&so->so_timeo);   
+ 802f334:	e0bfff17 	ldw	r2,-4(fp)
+ 802f338:	10800904 	addi	r2,r2,36
+ 802f33c:	1009883a 	mov	r4,r2
+ 802f340:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   sowwakeup (so);
+ 802f344:	e0bfff17 	ldw	r2,-4(fp)
+ 802f348:	10801204 	addi	r2,r2,72
+ 802f34c:	100b883a 	mov	r5,r2
+ 802f350:	e13fff17 	ldw	r4,-4(fp)
+ 802f354:	802f94c0 	call	802f94c <sbwakeup>
+   sorwakeup (so);
+ 802f358:	e0bfff17 	ldw	r2,-4(fp)
+ 802f35c:	10800a04 	addi	r2,r2,40
+ 802f360:	100b883a 	mov	r5,r2
+ 802f364:	e13fff17 	ldw	r4,-4(fp)
+ 802f368:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f36c:	0001883a 	nop
+ 802f370:	e037883a 	mov	sp,fp
+ 802f374:	dfc00117 	ldw	ra,4(sp)
+ 802f378:	df000017 	ldw	fp,0(sp)
+ 802f37c:	dec00204 	addi	sp,sp,8
+ 802f380:	f800283a 	ret
+
+0802f384 <soisdisconnected>:
+ * RETURNS: 
+ */
+
+void
+soisdisconnected(struct socket * so)
+{
+ 802f384:	defffd04 	addi	sp,sp,-12
+ 802f388:	dfc00215 	stw	ra,8(sp)
+ 802f38c:	df000115 	stw	fp,4(sp)
+ 802f390:	df000104 	addi	fp,sp,4
+ 802f394:	e13fff15 	stw	r4,-4(fp)
+   if (so->so_state & SS_ISCONNECTING)
+ 802f398:	e0bfff17 	ldw	r2,-4(fp)
+ 802f39c:	1080088b 	ldhu	r2,34(r2)
+ 802f3a0:	10bfffcc 	andi	r2,r2,65535
+ 802f3a4:	1080010c 	andi	r2,r2,4
+ 802f3a8:	10000626 	beq	r2,zero,802f3c4 <soisdisconnected+0x40>
+      so->so_state |= SS_WASCONNECTING;
+ 802f3ac:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3b0:	1080088b 	ldhu	r2,34(r2)
+ 802f3b4:	10880014 	ori	r2,r2,8192
+ 802f3b8:	1007883a 	mov	r3,r2
+ 802f3bc:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3c0:	10c0088d 	sth	r3,34(r2)
+   so->so_state &= ~(SS_ISCONNECTING|SS_ISCONNECTED|SS_ISDISCONNECTING);
+ 802f3c4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3c8:	10c0088b 	ldhu	r3,34(r2)
+ 802f3cc:	00bffc44 	movi	r2,-15
+ 802f3d0:	1884703a 	and	r2,r3,r2
+ 802f3d4:	1007883a 	mov	r3,r2
+ 802f3d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3dc:	10c0088d 	sth	r3,34(r2)
+   so->so_state |= (SS_CANTRCVMORE|SS_CANTSENDMORE);
+ 802f3e0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3e4:	1080088b 	ldhu	r2,34(r2)
+ 802f3e8:	10800c14 	ori	r2,r2,48
+ 802f3ec:	1007883a 	mov	r3,r2
+ 802f3f0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3f4:	10c0088d 	sth	r3,34(r2)
+   tcp_wakeup ((char *)&so->so_timeo);
+ 802f3f8:	e0bfff17 	ldw	r2,-4(fp)
+ 802f3fc:	10800904 	addi	r2,r2,36
+ 802f400:	1009883a 	mov	r4,r2
+ 802f404:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   sowwakeup (so);
+ 802f408:	e0bfff17 	ldw	r2,-4(fp)
+ 802f40c:	10801204 	addi	r2,r2,72
+ 802f410:	100b883a 	mov	r5,r2
+ 802f414:	e13fff17 	ldw	r4,-4(fp)
+ 802f418:	802f94c0 	call	802f94c <sbwakeup>
+   sorwakeup (so);
+ 802f41c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f420:	10800a04 	addi	r2,r2,40
+ 802f424:	100b883a 	mov	r5,r2
+ 802f428:	e13fff17 	ldw	r4,-4(fp)
+ 802f42c:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f430:	0001883a 	nop
+ 802f434:	e037883a 	mov	sp,fp
+ 802f438:	dfc00117 	ldw	ra,4(sp)
+ 802f43c:	df000017 	ldw	fp,0(sp)
+ 802f440:	dec00204 	addi	sp,sp,8
+ 802f444:	f800283a 	ret
+
+0802f448 <sonewconn>:
+ * RETURNS: 
+ */
+
+struct socket *   
+sonewconn(struct socket * head)
+{
+ 802f448:	defffb04 	addi	sp,sp,-20
+ 802f44c:	dfc00415 	stw	ra,16(sp)
+ 802f450:	df000315 	stw	fp,12(sp)
+ 802f454:	df000304 	addi	fp,sp,12
+ 802f458:	e13ffd15 	stw	r4,-12(fp)
+   struct socket *   so;
+   int rc;  
+
+   if (head->so_qlen + head->so_q0len > 3 * head->so_qlimit / 2)
+ 802f45c:	e0bffd17 	ldw	r2,-12(fp)
+ 802f460:	10801e43 	ldbu	r2,121(r2)
+ 802f464:	10c03fcc 	andi	r3,r2,255
+ 802f468:	18c0201c 	xori	r3,r3,128
+ 802f46c:	18ffe004 	addi	r3,r3,-128
+ 802f470:	e0bffd17 	ldw	r2,-12(fp)
+ 802f474:	10801e03 	ldbu	r2,120(r2)
+ 802f478:	10803fcc 	andi	r2,r2,255
+ 802f47c:	1080201c 	xori	r2,r2,128
+ 802f480:	10bfe004 	addi	r2,r2,-128
+ 802f484:	1887883a 	add	r3,r3,r2
+ 802f488:	e0bffd17 	ldw	r2,-12(fp)
+ 802f48c:	10801e83 	ldbu	r2,122(r2)
+ 802f490:	10803fcc 	andi	r2,r2,255
+ 802f494:	1080201c 	xori	r2,r2,128
+ 802f498:	10bfe004 	addi	r2,r2,-128
+ 802f49c:	108000e4 	muli	r2,r2,3
+ 802f4a0:	1008d7fa 	srli	r4,r2,31
+ 802f4a4:	2085883a 	add	r2,r4,r2
+ 802f4a8:	1005d07a 	srai	r2,r2,1
+ 802f4ac:	10c05b16 	blt	r2,r3,802f61c <sonewconn+0x1d4>
+      goto bad;
+   if ((so = SOC_ALLOC (sizeof (*so))) == NULL)
+ 802f4b0:	01002104 	movi	r4,132
+ 802f4b4:	802982c0 	call	802982c <npalloc>
+ 802f4b8:	e0bfff15 	stw	r2,-4(fp)
+ 802f4bc:	e0bfff17 	ldw	r2,-4(fp)
+ 802f4c0:	10005826 	beq	r2,zero,802f624 <sonewconn+0x1dc>
+      goto bad;
+   so->next = NULL;
+ 802f4c4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f4c8:	10000015 	stw	zero,0(r2)
+   putq(&soq,(qp)so);      /* Place newly created socket in a queue */
+ 802f4cc:	e17fff17 	ldw	r5,-4(fp)
+ 802f4d0:	010201b4 	movhi	r4,2054
+ 802f4d4:	21387104 	addi	r4,r4,-7740
+ 802f4d8:	80289900 	call	8028990 <putq>
+   so->so_type = head->so_type;
+ 802f4dc:	e0bffd17 	ldw	r2,-12(fp)
+ 802f4e0:	10c00983 	ldbu	r3,38(r2)
+ 802f4e4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f4e8:	10c00985 	stb	r3,38(r2)
+   so->so_options = head->so_options &~ (unshort)SO_ACCEPTCONN;
+ 802f4ec:	e0bffd17 	ldw	r2,-12(fp)
+ 802f4f0:	10c00417 	ldw	r3,16(r2)
+ 802f4f4:	00bfff44 	movi	r2,-3
+ 802f4f8:	1886703a 	and	r3,r3,r2
+ 802f4fc:	e0bfff17 	ldw	r2,-4(fp)
+ 802f500:	10c00415 	stw	r3,16(r2)
+   so->so_linger = head->so_linger;
+ 802f504:	e0bffd17 	ldw	r2,-12(fp)
+ 802f508:	10c0080b 	ldhu	r3,32(r2)
+ 802f50c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f510:	10c0080d 	sth	r3,32(r2)
+   so->so_state = head->so_state | (unshort)SS_NOFDREF;
+ 802f514:	e0bffd17 	ldw	r2,-12(fp)
+ 802f518:	1080088b 	ldhu	r2,34(r2)
+ 802f51c:	10800054 	ori	r2,r2,1
+ 802f520:	1007883a 	mov	r3,r2
+ 802f524:	e0bfff17 	ldw	r2,-4(fp)
+ 802f528:	10c0088d 	sth	r3,34(r2)
+   so->so_proto = head->so_proto;
+ 802f52c:	e0bffd17 	ldw	r2,-12(fp)
+ 802f530:	10c00217 	ldw	r3,8(r2)
+ 802f534:	e0bfff17 	ldw	r2,-4(fp)
+ 802f538:	10c00215 	stw	r3,8(r2)
+   so->so_timeo = head->so_timeo;
+ 802f53c:	e0bffd17 	ldw	r2,-12(fp)
+ 802f540:	10c0090b 	ldhu	r3,36(r2)
+ 802f544:	e0bfff17 	ldw	r2,-4(fp)
+ 802f548:	10c0090d 	sth	r3,36(r2)
+   so->so_rcv.sb_hiwat = (u_int)tcp_recvspace;
+ 802f54c:	d0e02117 	ldw	r3,-32636(gp)
+ 802f550:	e0bfff17 	ldw	r2,-4(fp)
+ 802f554:	10c00b15 	stw	r3,44(r2)
+   so->so_snd.sb_hiwat = (u_int)tcp_sendspace;
+ 802f558:	d0e02017 	ldw	r3,-32640(gp)
+ 802f55c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f560:	10c01315 	stw	r3,76(r2)
+   soqinsque (head, so, 0);
+ 802f564:	000d883a 	mov	r6,zero
+ 802f568:	e17fff17 	ldw	r5,-4(fp)
+ 802f56c:	e13ffd17 	ldw	r4,-12(fp)
+ 802f570:	802f6400 	call	802f640 <soqinsque>
+   so->so_req = PRU_ATTACH;
+ 802f574:	e0bfff17 	ldw	r2,-4(fp)
+ 802f578:	10000715 	stw	zero,28(r2)
+   so->so_domain = head->so_domain;
+ 802f57c:	e0bffd17 	ldw	r2,-12(fp)
+ 802f580:	10c00517 	ldw	r3,20(r2)
+ 802f584:	e0bfff17 	ldw	r2,-4(fp)
+ 802f588:	10c00515 	stw	r3,20(r2)
+
+   if ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0))
+ 802f58c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f590:	10800217 	ldw	r2,8(r2)
+ 802f594:	10800317 	ldw	r2,12(r2)
+ 802f598:	000d883a 	mov	r6,zero
+ 802f59c:	000b883a 	mov	r5,zero
+ 802f5a0:	e13fff17 	ldw	r4,-4(fp)
+ 802f5a4:	103ee83a 	callr	r2
+ 802f5a8:	10000f1e 	bne	r2,zero,802f5e8 <sonewconn+0x1a0>
+      goto bad2;
+   if (so_evtmap)
+ 802f5ac:	d0a09a03 	ldbu	r2,-32152(gp)
+ 802f5b0:	10803fcc 	andi	r2,r2,255
+ 802f5b4:	10000a26 	beq	r2,zero,802f5e0 <sonewconn+0x198>
+   {
+      rc = (*so_evtmap_create) (so);                       
+ 802f5b8:	d0a09817 	ldw	r2,-32160(gp)
+ 802f5bc:	e13fff17 	ldw	r4,-4(fp)
+ 802f5c0:	103ee83a 	callr	r2
+ 802f5c4:	e0bffe15 	stw	r2,-8(fp)
+      if (rc != 0) goto bad2;
+ 802f5c8:	e0bffe17 	ldw	r2,-8(fp)
+ 802f5cc:	1000081e 	bne	r2,zero,802f5f0 <sonewconn+0x1a8>
+      so->owner = head->owner;
+ 802f5d0:	e0bffd17 	ldw	r2,-12(fp)
+ 802f5d4:	10c02003 	ldbu	r3,128(r2)
+ 802f5d8:	e0bfff17 	ldw	r2,-4(fp)
+ 802f5dc:	10c02005 	stb	r3,128(r2)
+   }
+   return (so);
+ 802f5e0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f5e4:	00001106 	br	802f62c <sonewconn+0x1e4>
+      goto bad2;
+ 802f5e8:	0001883a 	nop
+ 802f5ec:	00000106 	br	802f5f4 <sonewconn+0x1ac>
+      if (rc != 0) goto bad2;
+ 802f5f0:	0001883a 	nop
+   
+bad2:
+   (void) soqremque (so, 0);
+ 802f5f4:	000b883a 	mov	r5,zero
+ 802f5f8:	e13fff17 	ldw	r4,-4(fp)
+ 802f5fc:	802f6ec0 	call	802f6ec <soqremque>
+   qdel(&soq, so);   /* Delete the socket entry from the queue */
+ 802f600:	e17fff17 	ldw	r5,-4(fp)
+ 802f604:	010201b4 	movhi	r4,2054
+ 802f608:	21387104 	addi	r4,r4,-7740
+ 802f60c:	8028a400 	call	8028a40 <qdel>
+   SOC_FREE(so);  /* Free the socket structure */
+ 802f610:	e13fff17 	ldw	r4,-4(fp)
+ 802f614:	80298600 	call	8029860 <npfree>
+ 802f618:	00000306 	br	802f628 <sonewconn+0x1e0>
+      goto bad;
+ 802f61c:	0001883a 	nop
+ 802f620:	00000106 	br	802f628 <sonewconn+0x1e0>
+      goto bad;
+ 802f624:	0001883a 	nop
+bad:
+   return ((struct socket *)0);
+ 802f628:	0005883a 	mov	r2,zero
+}
+ 802f62c:	e037883a 	mov	sp,fp
+ 802f630:	dfc00117 	ldw	ra,4(sp)
+ 802f634:	df000017 	ldw	fp,0(sp)
+ 802f638:	dec00204 	addi	sp,sp,8
+ 802f63c:	f800283a 	ret
+
+0802f640 <soqinsque>:
+
+void
+soqinsque(struct socket * head, 
+   struct socket *   so,
+   int   q)
+{
+ 802f640:	defffc04 	addi	sp,sp,-16
+ 802f644:	df000315 	stw	fp,12(sp)
+ 802f648:	df000304 	addi	fp,sp,12
+ 802f64c:	e13fff15 	stw	r4,-4(fp)
+ 802f650:	e17ffe15 	stw	r5,-8(fp)
+ 802f654:	e1bffd15 	stw	r6,-12(fp)
+   so->so_head = head;
+ 802f658:	e0bffe17 	ldw	r2,-8(fp)
+ 802f65c:	e0ffff17 	ldw	r3,-4(fp)
+ 802f660:	10c01b15 	stw	r3,108(r2)
+   if (q == 0) 
+ 802f664:	e0bffd17 	ldw	r2,-12(fp)
+ 802f668:	10000e1e 	bne	r2,zero,802f6a4 <soqinsque+0x64>
+   {
+      head->so_q0len++;
+ 802f66c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f670:	10801e03 	ldbu	r2,120(r2)
+ 802f674:	10800044 	addi	r2,r2,1
+ 802f678:	1007883a 	mov	r3,r2
+ 802f67c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f680:	10c01e05 	stb	r3,120(r2)
+      so->so_q0 = head->so_q0;
+ 802f684:	e0bfff17 	ldw	r2,-4(fp)
+ 802f688:	10c01c17 	ldw	r3,112(r2)
+ 802f68c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f690:	10c01c15 	stw	r3,112(r2)
+      head->so_q0 = so;
+ 802f694:	e0bfff17 	ldw	r2,-4(fp)
+ 802f698:	e0fffe17 	ldw	r3,-8(fp)
+ 802f69c:	10c01c15 	stw	r3,112(r2)
+   {
+      head->so_qlen++;
+      so->so_q = head->so_q;
+      head->so_q = so;
+   }
+}
+ 802f6a0:	00000d06 	br	802f6d8 <soqinsque+0x98>
+      head->so_qlen++;
+ 802f6a4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f6a8:	10801e43 	ldbu	r2,121(r2)
+ 802f6ac:	10800044 	addi	r2,r2,1
+ 802f6b0:	1007883a 	mov	r3,r2
+ 802f6b4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f6b8:	10c01e45 	stb	r3,121(r2)
+      so->so_q = head->so_q;
+ 802f6bc:	e0bfff17 	ldw	r2,-4(fp)
+ 802f6c0:	10c01d17 	ldw	r3,116(r2)
+ 802f6c4:	e0bffe17 	ldw	r2,-8(fp)
+ 802f6c8:	10c01d15 	stw	r3,116(r2)
+      head->so_q = so;
+ 802f6cc:	e0bfff17 	ldw	r2,-4(fp)
+ 802f6d0:	e0fffe17 	ldw	r3,-8(fp)
+ 802f6d4:	10c01d15 	stw	r3,116(r2)
+}
+ 802f6d8:	0001883a 	nop
+ 802f6dc:	e037883a 	mov	sp,fp
+ 802f6e0:	df000017 	ldw	fp,0(sp)
+ 802f6e4:	dec00104 	addi	sp,sp,4
+ 802f6e8:	f800283a 	ret
+
+0802f6ec <soqremque>:
+ * RETURNS: 
+ */
+
+int
+soqremque(struct socket * so, int q)
+{
+ 802f6ec:	defffa04 	addi	sp,sp,-24
+ 802f6f0:	df000515 	stw	fp,20(sp)
+ 802f6f4:	df000504 	addi	fp,sp,20
+ 802f6f8:	e13ffc15 	stw	r4,-16(fp)
+ 802f6fc:	e17ffb15 	stw	r5,-20(fp)
+   struct socket *   head, *  prev, *  next;
+
+   head = so->so_head;
+ 802f700:	e0bffc17 	ldw	r2,-16(fp)
+ 802f704:	10801b17 	ldw	r2,108(r2)
+ 802f708:	e0bffe15 	stw	r2,-8(fp)
+   prev = head;
+ 802f70c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f710:	e0bfff15 	stw	r2,-4(fp)
+   for (;;) 
+   {
+      next = q ? prev->so_q : prev->so_q0;
+ 802f714:	e0bffb17 	ldw	r2,-20(fp)
+ 802f718:	10000326 	beq	r2,zero,802f728 <soqremque+0x3c>
+ 802f71c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f720:	10801d17 	ldw	r2,116(r2)
+ 802f724:	00000206 	br	802f730 <soqremque+0x44>
+ 802f728:	e0bfff17 	ldw	r2,-4(fp)
+ 802f72c:	10801c17 	ldw	r2,112(r2)
+ 802f730:	e0bffd15 	stw	r2,-12(fp)
+      if (next == so)
+ 802f734:	e0fffd17 	ldw	r3,-12(fp)
+ 802f738:	e0bffc17 	ldw	r2,-16(fp)
+ 802f73c:	18800826 	beq	r3,r2,802f760 <soqremque+0x74>
+         break;
+      if (next == head)
+ 802f740:	e0fffd17 	ldw	r3,-12(fp)
+ 802f744:	e0bffe17 	ldw	r2,-8(fp)
+ 802f748:	1880021e 	bne	r3,r2,802f754 <soqremque+0x68>
+         return (0);
+ 802f74c:	0005883a 	mov	r2,zero
+ 802f750:	00002406 	br	802f7e4 <soqremque+0xf8>
+      prev = next;
+ 802f754:	e0bffd17 	ldw	r2,-12(fp)
+ 802f758:	e0bfff15 	stw	r2,-4(fp)
+      next = q ? prev->so_q : prev->so_q0;
+ 802f75c:	003fed06 	br	802f714 <soqremque+0x28>
+         break;
+ 802f760:	0001883a 	nop
+   }
+   if (q == 0) 
+ 802f764:	e0bffb17 	ldw	r2,-20(fp)
+ 802f768:	10000b1e 	bne	r2,zero,802f798 <soqremque+0xac>
+   {
+      prev->so_q0 = next->so_q0;
+ 802f76c:	e0bffd17 	ldw	r2,-12(fp)
+ 802f770:	10c01c17 	ldw	r3,112(r2)
+ 802f774:	e0bfff17 	ldw	r2,-4(fp)
+ 802f778:	10c01c15 	stw	r3,112(r2)
+      head->so_q0len--;
+ 802f77c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f780:	10801e03 	ldbu	r2,120(r2)
+ 802f784:	10bfffc4 	addi	r2,r2,-1
+ 802f788:	1007883a 	mov	r3,r2
+ 802f78c:	e0bffe17 	ldw	r2,-8(fp)
+ 802f790:	10c01e05 	stb	r3,120(r2)
+ 802f794:	00000a06 	br	802f7c0 <soqremque+0xd4>
+   } else 
+   {
+      prev->so_q = next->so_q;
+ 802f798:	e0bffd17 	ldw	r2,-12(fp)
+ 802f79c:	10c01d17 	ldw	r3,116(r2)
+ 802f7a0:	e0bfff17 	ldw	r2,-4(fp)
+ 802f7a4:	10c01d15 	stw	r3,116(r2)
+      head->so_qlen--;
+ 802f7a8:	e0bffe17 	ldw	r2,-8(fp)
+ 802f7ac:	10801e43 	ldbu	r2,121(r2)
+ 802f7b0:	10bfffc4 	addi	r2,r2,-1
+ 802f7b4:	1007883a 	mov	r3,r2
+ 802f7b8:	e0bffe17 	ldw	r2,-8(fp)
+ 802f7bc:	10c01e45 	stb	r3,121(r2)
+   }
+   next->so_q0 = next->so_q = 0;
+ 802f7c0:	e0bffd17 	ldw	r2,-12(fp)
+ 802f7c4:	10001d15 	stw	zero,116(r2)
+ 802f7c8:	e0bffd17 	ldw	r2,-12(fp)
+ 802f7cc:	10c01d17 	ldw	r3,116(r2)
+ 802f7d0:	e0bffd17 	ldw	r2,-12(fp)
+ 802f7d4:	10c01c15 	stw	r3,112(r2)
+   next->so_head = 0;
+ 802f7d8:	e0bffd17 	ldw	r2,-12(fp)
+ 802f7dc:	10001b15 	stw	zero,108(r2)
+   return 1;
+ 802f7e0:	00800044 	movi	r2,1
+}
+ 802f7e4:	e037883a 	mov	sp,fp
+ 802f7e8:	df000017 	ldw	fp,0(sp)
+ 802f7ec:	dec00104 	addi	sp,sp,4
+ 802f7f0:	f800283a 	ret
+
+0802f7f4 <socantsendmore>:
+ * RETURNS: 
+ */
+
+void
+socantsendmore(struct socket * so)
+{
+ 802f7f4:	defffd04 	addi	sp,sp,-12
+ 802f7f8:	dfc00215 	stw	ra,8(sp)
+ 802f7fc:	df000115 	stw	fp,4(sp)
+ 802f800:	df000104 	addi	fp,sp,4
+ 802f804:	e13fff15 	stw	r4,-4(fp)
+   so->so_state |= SS_CANTSENDMORE;
+ 802f808:	e0bfff17 	ldw	r2,-4(fp)
+ 802f80c:	1080088b 	ldhu	r2,34(r2)
+ 802f810:	10800414 	ori	r2,r2,16
+ 802f814:	1007883a 	mov	r3,r2
+ 802f818:	e0bfff17 	ldw	r2,-4(fp)
+ 802f81c:	10c0088d 	sth	r3,34(r2)
+   sowwakeup(so);
+ 802f820:	e0bfff17 	ldw	r2,-4(fp)
+ 802f824:	10801204 	addi	r2,r2,72
+ 802f828:	100b883a 	mov	r5,r2
+ 802f82c:	e13fff17 	ldw	r4,-4(fp)
+ 802f830:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f834:	0001883a 	nop
+ 802f838:	e037883a 	mov	sp,fp
+ 802f83c:	dfc00117 	ldw	ra,4(sp)
+ 802f840:	df000017 	ldw	fp,0(sp)
+ 802f844:	dec00204 	addi	sp,sp,8
+ 802f848:	f800283a 	ret
+
+0802f84c <socantrcvmore>:
+ * RETURNS: 
+ */
+
+void
+socantrcvmore(struct socket * so)
+{
+ 802f84c:	defffd04 	addi	sp,sp,-12
+ 802f850:	dfc00215 	stw	ra,8(sp)
+ 802f854:	df000115 	stw	fp,4(sp)
+ 802f858:	df000104 	addi	fp,sp,4
+ 802f85c:	e13fff15 	stw	r4,-4(fp)
+   so->so_state |= SS_CANTRCVMORE;
+ 802f860:	e0bfff17 	ldw	r2,-4(fp)
+ 802f864:	1080088b 	ldhu	r2,34(r2)
+ 802f868:	10800814 	ori	r2,r2,32
+ 802f86c:	1007883a 	mov	r3,r2
+ 802f870:	e0bfff17 	ldw	r2,-4(fp)
+ 802f874:	10c0088d 	sth	r3,34(r2)
+   sorwakeup(so);
+ 802f878:	e0bfff17 	ldw	r2,-4(fp)
+ 802f87c:	10800a04 	addi	r2,r2,40
+ 802f880:	100b883a 	mov	r5,r2
+ 802f884:	e13fff17 	ldw	r4,-4(fp)
+ 802f888:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 802f88c:	0001883a 	nop
+ 802f890:	e037883a 	mov	sp,fp
+ 802f894:	dfc00117 	ldw	ra,4(sp)
+ 802f898:	df000017 	ldw	fp,0(sp)
+ 802f89c:	dec00204 	addi	sp,sp,8
+ 802f8a0:	f800283a 	ret
+
+0802f8a4 <sbselqueue>:
+ * RETURNS: 
+ */
+
+void
+sbselqueue(struct sockbuf * sb)
+{
+ 802f8a4:	defffe04 	addi	sp,sp,-8
+ 802f8a8:	df000115 	stw	fp,4(sp)
+ 802f8ac:	df000104 	addi	fp,sp,4
+ 802f8b0:	e13fff15 	stw	r4,-4(fp)
+   sb->sb_flags |= SB_SEL;
+ 802f8b4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f8b8:	1080070b 	ldhu	r2,28(r2)
+ 802f8bc:	10800214 	ori	r2,r2,8
+ 802f8c0:	1007883a 	mov	r3,r2
+ 802f8c4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f8c8:	10c0070d 	sth	r3,28(r2)
+}
+ 802f8cc:	0001883a 	nop
+ 802f8d0:	e037883a 	mov	sp,fp
+ 802f8d4:	df000017 	ldw	fp,0(sp)
+ 802f8d8:	dec00104 	addi	sp,sp,4
+ 802f8dc:	f800283a 	ret
+
+0802f8e0 <sbwait>:
+ * RETURNS: 
+ */
+
+void
+sbwait(struct sockbuf * sb)
+{
+ 802f8e0:	defffd04 	addi	sp,sp,-12
+ 802f8e4:	dfc00215 	stw	ra,8(sp)
+ 802f8e8:	df000115 	stw	fp,4(sp)
+ 802f8ec:	df000104 	addi	fp,sp,4
+ 802f8f0:	e13fff15 	stw	r4,-4(fp)
+   sb->sb_flags |= SB_WAIT;
+ 802f8f4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f8f8:	1080070b 	ldhu	r2,28(r2)
+ 802f8fc:	10800114 	ori	r2,r2,4
+ 802f900:	1007883a 	mov	r3,r2
+ 802f904:	e0bfff17 	ldw	r2,-4(fp)
+ 802f908:	10c0070d 	sth	r3,28(r2)
+   tcp_sleep ((char *)&sb->sb_cc);
+ 802f90c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f910:	1009883a 	mov	r4,r2
+ 802f914:	8027a540 	call	8027a54 <tcp_sleep>
+   sb->sb_flags &= ~SB_WAIT;
+ 802f918:	e0bfff17 	ldw	r2,-4(fp)
+ 802f91c:	10c0070b 	ldhu	r3,28(r2)
+ 802f920:	00bffec4 	movi	r2,-5
+ 802f924:	1884703a 	and	r2,r3,r2
+ 802f928:	1007883a 	mov	r3,r2
+ 802f92c:	e0bfff17 	ldw	r2,-4(fp)
+ 802f930:	10c0070d 	sth	r3,28(r2)
+}
+ 802f934:	0001883a 	nop
+ 802f938:	e037883a 	mov	sp,fp
+ 802f93c:	dfc00117 	ldw	ra,4(sp)
+ 802f940:	df000017 	ldw	fp,0(sp)
+ 802f944:	dec00204 	addi	sp,sp,8
+ 802f948:	f800283a 	ret
+
+0802f94c <sbwakeup>:
+ * RETURNS: 
+ */
+
+void
+sbwakeup(struct socket * so, struct sockbuf * sb)
+{
+ 802f94c:	defffc04 	addi	sp,sp,-16
+ 802f950:	dfc00315 	stw	ra,12(sp)
+ 802f954:	df000215 	stw	fp,8(sp)
+ 802f958:	df000204 	addi	fp,sp,8
+ 802f95c:	e13fff15 	stw	r4,-4(fp)
+ 802f960:	e17ffe15 	stw	r5,-8(fp)
+   if (sb->sb_flags & SB_SEL) 
+ 802f964:	e0bffe17 	ldw	r2,-8(fp)
+ 802f968:	1080070b 	ldhu	r2,28(r2)
+ 802f96c:	10bfffcc 	andi	r2,r2,65535
+ 802f970:	1080020c 	andi	r2,r2,8
+ 802f974:	10000a26 	beq	r2,zero,802f9a0 <sbwakeup+0x54>
+   {
+      select_wait = 0;
+ 802f978:	d020850d 	sth	zero,-32236(gp)
+#ifndef SOCK_MAP_EVENTS
+      tcp_wakeup ((char *)&select_wait);
+ 802f97c:	d1208504 	addi	r4,gp,-32236
+ 802f980:	8027ba00 	call	8027ba0 <tcp_wakeup>
+#else
+      tcp_wakeup2 (so->owner);
+#endif      
+      sb->sb_flags &= ~SB_SEL;
+ 802f984:	e0bffe17 	ldw	r2,-8(fp)
+ 802f988:	10c0070b 	ldhu	r3,28(r2)
+ 802f98c:	00bffdc4 	movi	r2,-9
+ 802f990:	1884703a 	and	r2,r3,r2
+ 802f994:	1007883a 	mov	r3,r2
+ 802f998:	e0bffe17 	ldw	r2,-8(fp)
+ 802f99c:	10c0070d 	sth	r3,28(r2)
+#ifdef SOCK_WAKEALWAYS  /* Always wake the socket? */
+   /* Systems Like Green Hills Integrity RTOS, need to process socket
+      input even if looks like no one is blocked on the socket */
+   tcp_wakeup ((char *)&sb->sb_cc); /* signal wake on socket */
+#else /* older BSD style code - only call tcp_wakeup if blocked */
+   if (sb->sb_flags & SB_WAIT)   /* is sockbuf's WAIT flag set? */
+ 802f9a0:	e0bffe17 	ldw	r2,-8(fp)
+ 802f9a4:	1080070b 	ldhu	r2,28(r2)
+ 802f9a8:	10bfffcc 	andi	r2,r2,65535
+ 802f9ac:	1080010c 	andi	r2,r2,4
+ 802f9b0:	10000326 	beq	r2,zero,802f9c0 <sbwakeup+0x74>
+   {
+      tcp_wakeup ((char *)&sb->sb_cc);   /* call port wakeup routine */
+ 802f9b4:	e0bffe17 	ldw	r2,-8(fp)
+ 802f9b8:	1009883a 	mov	r4,r2
+ 802f9bc:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   }
+#endif   /* SOCK_WAKEALWAYS */
+}
+ 802f9c0:	0001883a 	nop
+ 802f9c4:	e037883a 	mov	sp,fp
+ 802f9c8:	dfc00117 	ldw	ra,4(sp)
+ 802f9cc:	df000017 	ldw	fp,0(sp)
+ 802f9d0:	dec00204 	addi	sp,sp,8
+ 802f9d4:	f800283a 	ret
+
+0802f9d8 <soreserve>:
+
+int
+soreserve(struct socket * so, 
+   u_long   sndcc, 
+   u_long   rcvcc)
+{
+ 802f9d8:	defffb04 	addi	sp,sp,-20
+ 802f9dc:	dfc00415 	stw	ra,16(sp)
+ 802f9e0:	df000315 	stw	fp,12(sp)
+ 802f9e4:	df000304 	addi	fp,sp,12
+ 802f9e8:	e13fff15 	stw	r4,-4(fp)
+ 802f9ec:	e17ffe15 	stw	r5,-8(fp)
+ 802f9f0:	e1bffd15 	stw	r6,-12(fp)
+   if (sbreserve(&so->so_snd, sndcc) == 0)
+ 802f9f4:	e0bfff17 	ldw	r2,-4(fp)
+ 802f9f8:	10801204 	addi	r2,r2,72
+ 802f9fc:	e17ffe17 	ldw	r5,-8(fp)
+ 802fa00:	1009883a 	mov	r4,r2
+ 802fa04:	802fa600 	call	802fa60 <sbreserve>
+ 802fa08:	10000e26 	beq	r2,zero,802fa44 <soreserve+0x6c>
+      goto bad;
+   if (sbreserve(&so->so_rcv, rcvcc) == 0)
+ 802fa0c:	e0bfff17 	ldw	r2,-4(fp)
+ 802fa10:	10800a04 	addi	r2,r2,40
+ 802fa14:	e17ffd17 	ldw	r5,-12(fp)
+ 802fa18:	1009883a 	mov	r4,r2
+ 802fa1c:	802fa600 	call	802fa60 <sbreserve>
+ 802fa20:	10000226 	beq	r2,zero,802fa2c <soreserve+0x54>
+      goto bad2;
+   return (0);
+ 802fa24:	0005883a 	mov	r2,zero
+ 802fa28:	00000806 	br	802fa4c <soreserve+0x74>
+      goto bad2;
+ 802fa2c:	0001883a 	nop
+bad2:
+   sbrelease(&so->so_snd);
+ 802fa30:	e0bfff17 	ldw	r2,-4(fp)
+ 802fa34:	10801204 	addi	r2,r2,72
+ 802fa38:	1009883a 	mov	r4,r2
+ 802fa3c:	802fab00 	call	802fab0 <sbrelease>
+ 802fa40:	00000106 	br	802fa48 <soreserve+0x70>
+      goto bad;
+ 802fa44:	0001883a 	nop
+bad:
+   return (ENOBUFS);
+ 802fa48:	00801a44 	movi	r2,105
+}
+ 802fa4c:	e037883a 	mov	sp,fp
+ 802fa50:	dfc00117 	ldw	ra,4(sp)
+ 802fa54:	df000017 	ldw	fp,0(sp)
+ 802fa58:	dec00204 	addi	sp,sp,8
+ 802fa5c:	f800283a 	ret
+
+0802fa60 <sbreserve>:
+ * RETURNS: 
+ */
+
+int
+sbreserve(struct sockbuf * sb, u_long cc)
+{
+ 802fa60:	defffd04 	addi	sp,sp,-12
+ 802fa64:	df000215 	stw	fp,8(sp)
+ 802fa68:	df000204 	addi	fp,sp,8
+ 802fa6c:	e13fff15 	stw	r4,-4(fp)
+ 802fa70:	e17ffe15 	stw	r5,-8(fp)
+#ifdef COMPILER_32BIT
+   if (cc > (u_long)SB_MAX * CLBYTES / (2 * MSIZE + CLBYTES))
+      return (0);
+#endif
+   sb->sb_hiwat = cc;
+ 802fa74:	e0bfff17 	ldw	r2,-4(fp)
+ 802fa78:	e0fffe17 	ldw	r3,-8(fp)
+ 802fa7c:	10c00115 	stw	r3,4(r2)
+   sb->sb_mbmax = MIN(cc * 2, SB_MAX);
+ 802fa80:	e0bffe17 	ldw	r2,-8(fp)
+ 802fa84:	1085883a 	add	r2,r2,r2
+ 802fa88:	10d00070 	cmpltui	r3,r2,16385
+ 802fa8c:	1800011e 	bne	r3,zero,802fa94 <sbreserve+0x34>
+ 802fa90:	00900004 	movi	r2,16384
+ 802fa94:	e0ffff17 	ldw	r3,-4(fp)
+ 802fa98:	18800315 	stw	r2,12(r3)
+   return (1);
+ 802fa9c:	00800044 	movi	r2,1
+}
+ 802faa0:	e037883a 	mov	sp,fp
+ 802faa4:	df000017 	ldw	fp,0(sp)
+ 802faa8:	dec00104 	addi	sp,sp,4
+ 802faac:	f800283a 	ret
+
+0802fab0 <sbrelease>:
+ * RETURNS: 
+ */
+
+void
+sbrelease(struct sockbuf * sb)
+{
+ 802fab0:	defffd04 	addi	sp,sp,-12
+ 802fab4:	dfc00215 	stw	ra,8(sp)
+ 802fab8:	df000115 	stw	fp,4(sp)
+ 802fabc:	df000104 	addi	fp,sp,4
+ 802fac0:	e13fff15 	stw	r4,-4(fp)
+   sbflush(sb);
+ 802fac4:	e13fff17 	ldw	r4,-4(fp)
+ 802fac8:	803002c0 	call	803002c <sbflush>
+   sb->sb_hiwat = sb->sb_mbmax = 0;
+ 802facc:	e0bfff17 	ldw	r2,-4(fp)
+ 802fad0:	10000315 	stw	zero,12(r2)
+ 802fad4:	e0bfff17 	ldw	r2,-4(fp)
+ 802fad8:	10c00317 	ldw	r3,12(r2)
+ 802fadc:	e0bfff17 	ldw	r2,-4(fp)
+ 802fae0:	10c00115 	stw	r3,4(r2)
+}
+ 802fae4:	0001883a 	nop
+ 802fae8:	e037883a 	mov	sp,fp
+ 802faec:	dfc00117 	ldw	ra,4(sp)
+ 802faf0:	df000017 	ldw	fp,0(sp)
+ 802faf4:	dec00204 	addi	sp,sp,8
+ 802faf8:	f800283a 	ret
+
+0802fafc <sbappend>:
+ * RETURNS: 
+ */
+
+void
+sbappend(struct sockbuf * sb, struct mbuf * m)
+{
+ 802fafc:	defffb04 	addi	sp,sp,-20
+ 802fb00:	dfc00415 	stw	ra,16(sp)
+ 802fb04:	df000315 	stw	fp,12(sp)
+ 802fb08:	df000304 	addi	fp,sp,12
+ 802fb0c:	e13ffe15 	stw	r4,-8(fp)
+ 802fb10:	e17ffd15 	stw	r5,-12(fp)
+   struct mbuf *  n;
+
+   if (m == 0)
+ 802fb14:	e0bffd17 	ldw	r2,-12(fp)
+ 802fb18:	10001a26 	beq	r2,zero,802fb84 <sbappend+0x88>
+      return;
+   ENTER_CRIT_SECTION(sb);
+ 802fb1c:	8028e940 	call	8028e94 <irq_Mask>
+   if ((n = sb->sb_mb) != NULL) 
+ 802fb20:	e0bffe17 	ldw	r2,-8(fp)
+ 802fb24:	10800617 	ldw	r2,24(r2)
+ 802fb28:	e0bfff15 	stw	r2,-4(fp)
+ 802fb2c:	e0bfff17 	ldw	r2,-4(fp)
+ 802fb30:	10000e26 	beq	r2,zero,802fb6c <sbappend+0x70>
+   {
+      while (n->m_act)
+ 802fb34:	00000306 	br	802fb44 <sbappend+0x48>
+         n = n->m_act;
+ 802fb38:	e0bfff17 	ldw	r2,-4(fp)
+ 802fb3c:	10800717 	ldw	r2,28(r2)
+ 802fb40:	e0bfff15 	stw	r2,-4(fp)
+      while (n->m_act)
+ 802fb44:	e0bfff17 	ldw	r2,-4(fp)
+ 802fb48:	10800717 	ldw	r2,28(r2)
+ 802fb4c:	103ffa1e 	bne	r2,zero,802fb38 <sbappend+0x3c>
+      while (n->m_next)
+ 802fb50:	00000306 	br	802fb60 <sbappend+0x64>
+         n = n->m_next;
+ 802fb54:	e0bfff17 	ldw	r2,-4(fp)
+ 802fb58:	10800617 	ldw	r2,24(r2)
+ 802fb5c:	e0bfff15 	stw	r2,-4(fp)
+      while (n->m_next)
+ 802fb60:	e0bfff17 	ldw	r2,-4(fp)
+ 802fb64:	10800617 	ldw	r2,24(r2)
+ 802fb68:	103ffa1e 	bne	r2,zero,802fb54 <sbappend+0x58>
+   }
+   sbcompress(sb, m, n);
+ 802fb6c:	e1bfff17 	ldw	r6,-4(fp)
+ 802fb70:	e17ffd17 	ldw	r5,-12(fp)
+ 802fb74:	e13ffe17 	ldw	r4,-8(fp)
+ 802fb78:	802fe500 	call	802fe50 <sbcompress>
+   EXIT_CRIT_SECTION(sb);
+ 802fb7c:	8028ef40 	call	8028ef4 <irq_Unmask>
+ 802fb80:	00000106 	br	802fb88 <sbappend+0x8c>
+      return;
+ 802fb84:	0001883a 	nop
+}
+ 802fb88:	e037883a 	mov	sp,fp
+ 802fb8c:	dfc00117 	ldw	ra,4(sp)
+ 802fb90:	df000017 	ldw	fp,0(sp)
+ 802fb94:	dec00204 	addi	sp,sp,8
+ 802fb98:	f800283a 	ret
+
+0802fb9c <sbappendrecord>:
+ */
+
+void
+sbappendrecord(struct sockbuf * sb, 
+   struct mbuf *  m0)
+{
+ 802fb9c:	defffb04 	addi	sp,sp,-20
+ 802fba0:	dfc00415 	stw	ra,16(sp)
+ 802fba4:	df000315 	stw	fp,12(sp)
+ 802fba8:	df000304 	addi	fp,sp,12
+ 802fbac:	e13ffe15 	stw	r4,-8(fp)
+ 802fbb0:	e17ffd15 	stw	r5,-12(fp)
+   struct mbuf *  m;
+
+   if (m0 == 0)
+ 802fbb4:	e0bffd17 	ldw	r2,-12(fp)
+ 802fbb8:	10002826 	beq	r2,zero,802fc5c <sbappendrecord+0xc0>
+      return;
+   ENTER_CRIT_SECTION(sb);    /* protect so_rcv operations */
+ 802fbbc:	8028e940 	call	8028e94 <irq_Mask>
+   if ((m = sb->sb_mb) != NULL)
+ 802fbc0:	e0bffe17 	ldw	r2,-8(fp)
+ 802fbc4:	10800617 	ldw	r2,24(r2)
+ 802fbc8:	e0bfff15 	stw	r2,-4(fp)
+ 802fbcc:	e0bfff17 	ldw	r2,-4(fp)
+ 802fbd0:	10000726 	beq	r2,zero,802fbf0 <sbappendrecord+0x54>
+      while (m->m_act)
+ 802fbd4:	00000306 	br	802fbe4 <sbappendrecord+0x48>
+      m = m->m_act;
+ 802fbd8:	e0bfff17 	ldw	r2,-4(fp)
+ 802fbdc:	10800717 	ldw	r2,28(r2)
+ 802fbe0:	e0bfff15 	stw	r2,-4(fp)
+      while (m->m_act)
+ 802fbe4:	e0bfff17 	ldw	r2,-4(fp)
+ 802fbe8:	10800717 	ldw	r2,28(r2)
+ 802fbec:	103ffa1e 	bne	r2,zero,802fbd8 <sbappendrecord+0x3c>
+   /*
+    * Put the first mbuf on the queue.
+    * Note this permits zero length records.
+    */
+   sballoc(sb, m0);
+ 802fbf0:	e0bffe17 	ldw	r2,-8(fp)
+ 802fbf4:	10c00017 	ldw	r3,0(r2)
+ 802fbf8:	e0bffd17 	ldw	r2,-12(fp)
+ 802fbfc:	10800217 	ldw	r2,8(r2)
+ 802fc00:	1887883a 	add	r3,r3,r2
+ 802fc04:	e0bffe17 	ldw	r2,-8(fp)
+ 802fc08:	10c00015 	stw	r3,0(r2)
+   if (m)
+ 802fc0c:	e0bfff17 	ldw	r2,-4(fp)
+ 802fc10:	10000426 	beq	r2,zero,802fc24 <sbappendrecord+0x88>
+      m->m_act = m0;
+ 802fc14:	e0bfff17 	ldw	r2,-4(fp)
+ 802fc18:	e0fffd17 	ldw	r3,-12(fp)
+ 802fc1c:	10c00715 	stw	r3,28(r2)
+ 802fc20:	00000306 	br	802fc30 <sbappendrecord+0x94>
+   else
+      sb->sb_mb = m0;
+ 802fc24:	e0bffe17 	ldw	r2,-8(fp)
+ 802fc28:	e0fffd17 	ldw	r3,-12(fp)
+ 802fc2c:	10c00615 	stw	r3,24(r2)
+   m = m0->m_next;
+ 802fc30:	e0bffd17 	ldw	r2,-12(fp)
+ 802fc34:	10800617 	ldw	r2,24(r2)
+ 802fc38:	e0bfff15 	stw	r2,-4(fp)
+   m0->m_next = 0;
+ 802fc3c:	e0bffd17 	ldw	r2,-12(fp)
+ 802fc40:	10000615 	stw	zero,24(r2)
+   sbcompress(sb, m, m0);
+ 802fc44:	e1bffd17 	ldw	r6,-12(fp)
+ 802fc48:	e17fff17 	ldw	r5,-4(fp)
+ 802fc4c:	e13ffe17 	ldw	r4,-8(fp)
+ 802fc50:	802fe500 	call	802fe50 <sbcompress>
+   EXIT_CRIT_SECTION(sb);
+ 802fc54:	8028ef40 	call	8028ef4 <irq_Unmask>
+ 802fc58:	00000106 	br	802fc60 <sbappendrecord+0xc4>
+      return;
+ 802fc5c:	0001883a 	nop
+}
+ 802fc60:	e037883a 	mov	sp,fp
+ 802fc64:	dfc00117 	ldw	ra,4(sp)
+ 802fc68:	df000017 	ldw	fp,0(sp)
+ 802fc6c:	dec00204 	addi	sp,sp,8
+ 802fc70:	f800283a 	ret
+
+0802fc74 <sbappendaddr>:
+
+int
+sbappendaddr(struct sockbuf * sb, 
+   struct sockaddr * asa,
+   struct mbuf *  m0)
+{
+ 802fc74:	defff804 	addi	sp,sp,-32
+ 802fc78:	dfc00715 	stw	ra,28(sp)
+ 802fc7c:	df000615 	stw	fp,24(sp)
+ 802fc80:	df000604 	addi	fp,sp,24
+ 802fc84:	e13ffc15 	stw	r4,-16(fp)
+ 802fc88:	e17ffb15 	stw	r5,-20(fp)
+ 802fc8c:	e1bffa15 	stw	r6,-24(fp)
+   struct mbuf *  m, *  n;
+   int   space =  sizeof   (*asa);
+ 802fc90:	00800404 	movi	r2,16
+ 802fc94:	e0bffd15 	stw	r2,-12(fp)
+
+   ENTER_CRIT_SECTION(sb);
+ 802fc98:	8028e940 	call	8028e94 <irq_Mask>
+   for (m = m0; m; m = m->m_next)
+ 802fc9c:	e0bffa17 	ldw	r2,-24(fp)
+ 802fca0:	e0bfff15 	stw	r2,-4(fp)
+ 802fca4:	00000806 	br	802fcc8 <sbappendaddr+0x54>
+      space += m->m_len;
+ 802fca8:	e0bfff17 	ldw	r2,-4(fp)
+ 802fcac:	10c00217 	ldw	r3,8(r2)
+ 802fcb0:	e0bffd17 	ldw	r2,-12(fp)
+ 802fcb4:	1885883a 	add	r2,r3,r2
+ 802fcb8:	e0bffd15 	stw	r2,-12(fp)
+   for (m = m0; m; m = m->m_next)
+ 802fcbc:	e0bfff17 	ldw	r2,-4(fp)
+ 802fcc0:	10800617 	ldw	r2,24(r2)
+ 802fcc4:	e0bfff15 	stw	r2,-4(fp)
+ 802fcc8:	e0bfff17 	ldw	r2,-4(fp)
+ 802fccc:	103ff61e 	bne	r2,zero,802fca8 <sbappendaddr+0x34>
+   if (space > (int)sbspace(sb))
+ 802fcd0:	e0bffc17 	ldw	r2,-16(fp)
+ 802fcd4:	10800117 	ldw	r2,4(r2)
+ 802fcd8:	1007883a 	mov	r3,r2
+ 802fcdc:	e0bffc17 	ldw	r2,-16(fp)
+ 802fce0:	10800017 	ldw	r2,0(r2)
+ 802fce4:	1885c83a 	sub	r2,r3,r2
+ 802fce8:	10000716 	blt	r2,zero,802fd08 <sbappendaddr+0x94>
+ 802fcec:	e0bffc17 	ldw	r2,-16(fp)
+ 802fcf0:	10c00117 	ldw	r3,4(r2)
+ 802fcf4:	e0bffc17 	ldw	r2,-16(fp)
+ 802fcf8:	10800017 	ldw	r2,0(r2)
+ 802fcfc:	1885c83a 	sub	r2,r3,r2
+ 802fd00:	1007883a 	mov	r3,r2
+ 802fd04:	00000106 	br	802fd0c <sbappendaddr+0x98>
+ 802fd08:	0007883a 	mov	r3,zero
+ 802fd0c:	e0bffd17 	ldw	r2,-12(fp)
+ 802fd10:	1880030e 	bge	r3,r2,802fd20 <sbappendaddr+0xac>
+   {
+      EXIT_CRIT_SECTION(sb);
+ 802fd14:	8028ef40 	call	8028ef4 <irq_Unmask>
+      return (0);
+ 802fd18:	0005883a 	mov	r2,zero
+ 802fd1c:	00004706 	br	802fe3c <sbappendaddr+0x1c8>
+   }
+   if ((m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr))) == NULL)
+ 802fd20:	01400404 	movi	r5,16
+ 802fd24:	01000244 	movi	r4,9
+ 802fd28:	8029a700 	call	8029a70 <m_getnbuf>
+ 802fd2c:	e0bfff15 	stw	r2,-4(fp)
+ 802fd30:	e0bfff17 	ldw	r2,-4(fp)
+ 802fd34:	1000031e 	bne	r2,zero,802fd44 <sbappendaddr+0xd0>
+   {
+      EXIT_CRIT_SECTION(sb);
+ 802fd38:	8028ef40 	call	8028ef4 <irq_Unmask>
+      return 0;
+ 802fd3c:	0005883a 	mov	r2,zero
+ 802fd40:	00003e06 	br	802fe3c <sbappendaddr+0x1c8>
+   }
+   *mtod(m, struct sockaddr *) = *asa;
+ 802fd44:	e0bfff17 	ldw	r2,-4(fp)
+ 802fd48:	10800317 	ldw	r2,12(r2)
+ 802fd4c:	e0fffb17 	ldw	r3,-20(fp)
+ 802fd50:	1900000b 	ldhu	r4,0(r3)
+ 802fd54:	1100000d 	sth	r4,0(r2)
+ 802fd58:	1900008b 	ldhu	r4,2(r3)
+ 802fd5c:	1100008d 	sth	r4,2(r2)
+ 802fd60:	1900010b 	ldhu	r4,4(r3)
+ 802fd64:	1100010d 	sth	r4,4(r2)
+ 802fd68:	1900018b 	ldhu	r4,6(r3)
+ 802fd6c:	1100018d 	sth	r4,6(r2)
+ 802fd70:	1900020b 	ldhu	r4,8(r3)
+ 802fd74:	1100020d 	sth	r4,8(r2)
+ 802fd78:	1900028b 	ldhu	r4,10(r3)
+ 802fd7c:	1100028d 	sth	r4,10(r2)
+ 802fd80:	1900030b 	ldhu	r4,12(r3)
+ 802fd84:	1100030d 	sth	r4,12(r2)
+ 802fd88:	18c0038b 	ldhu	r3,14(r3)
+ 802fd8c:	10c0038d 	sth	r3,14(r2)
+   m->m_len = sizeof (*asa);
+ 802fd90:	e0bfff17 	ldw	r2,-4(fp)
+ 802fd94:	00c00404 	movi	r3,16
+ 802fd98:	10c00215 	stw	r3,8(r2)
+   sballoc (sb, m);
+ 802fd9c:	e0bffc17 	ldw	r2,-16(fp)
+ 802fda0:	10c00017 	ldw	r3,0(r2)
+ 802fda4:	e0bfff17 	ldw	r2,-4(fp)
+ 802fda8:	10800217 	ldw	r2,8(r2)
+ 802fdac:	1887883a 	add	r3,r3,r2
+ 802fdb0:	e0bffc17 	ldw	r2,-16(fp)
+ 802fdb4:	10c00015 	stw	r3,0(r2)
+   if ((n = sb->sb_mb) != NULL) 
+ 802fdb8:	e0bffc17 	ldw	r2,-16(fp)
+ 802fdbc:	10800617 	ldw	r2,24(r2)
+ 802fdc0:	e0bffe15 	stw	r2,-8(fp)
+ 802fdc4:	e0bffe17 	ldw	r2,-8(fp)
+ 802fdc8:	10000b26 	beq	r2,zero,802fdf8 <sbappendaddr+0x184>
+   {
+      while (n->m_act)
+ 802fdcc:	00000306 	br	802fddc <sbappendaddr+0x168>
+         n = n->m_act;
+ 802fdd0:	e0bffe17 	ldw	r2,-8(fp)
+ 802fdd4:	10800717 	ldw	r2,28(r2)
+ 802fdd8:	e0bffe15 	stw	r2,-8(fp)
+      while (n->m_act)
+ 802fddc:	e0bffe17 	ldw	r2,-8(fp)
+ 802fde0:	10800717 	ldw	r2,28(r2)
+ 802fde4:	103ffa1e 	bne	r2,zero,802fdd0 <sbappendaddr+0x15c>
+      n->m_act = m;
+ 802fde8:	e0bffe17 	ldw	r2,-8(fp)
+ 802fdec:	e0ffff17 	ldw	r3,-4(fp)
+ 802fdf0:	10c00715 	stw	r3,28(r2)
+ 802fdf4:	00000306 	br	802fe04 <sbappendaddr+0x190>
+   } else
+      sb->sb_mb = m;
+ 802fdf8:	e0bffc17 	ldw	r2,-16(fp)
+ 802fdfc:	e0ffff17 	ldw	r3,-4(fp)
+ 802fe00:	10c00615 	stw	r3,24(r2)
+   if (m->m_next)
+ 802fe04:	e0bfff17 	ldw	r2,-4(fp)
+ 802fe08:	10800617 	ldw	r2,24(r2)
+ 802fe0c:	10000326 	beq	r2,zero,802fe1c <sbappendaddr+0x1a8>
+      m = m->m_next;
+ 802fe10:	e0bfff17 	ldw	r2,-4(fp)
+ 802fe14:	10800617 	ldw	r2,24(r2)
+ 802fe18:	e0bfff15 	stw	r2,-4(fp)
+   if (m0)
+ 802fe1c:	e0bffa17 	ldw	r2,-24(fp)
+ 802fe20:	10000426 	beq	r2,zero,802fe34 <sbappendaddr+0x1c0>
+      sbcompress(sb, m0, m);
+ 802fe24:	e1bfff17 	ldw	r6,-4(fp)
+ 802fe28:	e17ffa17 	ldw	r5,-24(fp)
+ 802fe2c:	e13ffc17 	ldw	r4,-16(fp)
+ 802fe30:	802fe500 	call	802fe50 <sbcompress>
+
+   EXIT_CRIT_SECTION(sb);
+ 802fe34:	8028ef40 	call	8028ef4 <irq_Unmask>
+   return (1);
+ 802fe38:	00800044 	movi	r2,1
+}
+ 802fe3c:	e037883a 	mov	sp,fp
+ 802fe40:	dfc00117 	ldw	ra,4(sp)
+ 802fe44:	df000017 	ldw	fp,0(sp)
+ 802fe48:	dec00204 	addi	sp,sp,8
+ 802fe4c:	f800283a 	ret
+
+0802fe50 <sbcompress>:
+
+void
+sbcompress(struct sockbuf * sb, 
+   struct mbuf *  m,
+   struct mbuf *  n)
+{
+ 802fe50:	defffb04 	addi	sp,sp,-20
+ 802fe54:	dfc00415 	stw	ra,16(sp)
+ 802fe58:	df000315 	stw	fp,12(sp)
+ 802fe5c:	df000304 	addi	fp,sp,12
+ 802fe60:	e13fff15 	stw	r4,-4(fp)
+ 802fe64:	e17ffe15 	stw	r5,-8(fp)
+ 802fe68:	e1bffd15 	stw	r6,-12(fp)
+
+   while (m) 
+ 802fe6c:	00006706 	br	803000c <sbcompress+0x1bc>
+   {
+      if (m->m_len == 0) 
+ 802fe70:	e0bffe17 	ldw	r2,-8(fp)
+ 802fe74:	10800217 	ldw	r2,8(r2)
+ 802fe78:	1000041e 	bne	r2,zero,802fe8c <sbcompress+0x3c>
+      {
+         m = m_free(m);
+ 802fe7c:	e13ffe17 	ldw	r4,-8(fp)
+ 802fe80:	8029bf80 	call	8029bf8 <m_free>
+ 802fe84:	e0bffe15 	stw	r2,-8(fp)
+         continue;
+ 802fe88:	00006006 	br	803000c <sbcompress+0x1bc>
+      }
+      if (m->m_type != MT_RXDATA && 
+ 802fe8c:	e0bffe17 	ldw	r2,-8(fp)
+ 802fe90:	10800817 	ldw	r2,32(r2)
+ 802fe94:	10800060 	cmpeqi	r2,r2,1
+ 802fe98:	1000111e 	bne	r2,zero,802fee0 <sbcompress+0x90>
+          m->m_type != MT_TXDATA && 
+ 802fe9c:	e0bffe17 	ldw	r2,-8(fp)
+ 802fea0:	10800817 	ldw	r2,32(r2)
+      if (m->m_type != MT_RXDATA && 
+ 802fea4:	108000a0 	cmpeqi	r2,r2,2
+ 802fea8:	10000d1e 	bne	r2,zero,802fee0 <sbcompress+0x90>
+          m->m_type != MT_SONAME) 
+ 802feac:	e0bffe17 	ldw	r2,-8(fp)
+ 802feb0:	10800817 	ldw	r2,32(r2)
+          m->m_type != MT_TXDATA && 
+ 802feb4:	10800260 	cmpeqi	r2,r2,9
+ 802feb8:	1000091e 	bne	r2,zero,802fee0 <sbcompress+0x90>
+      {
+         dprintf ("sbcomp:bad type %d\n", m->m_type);
+ 802febc:	e0bffe17 	ldw	r2,-8(fp)
+ 802fec0:	10800817 	ldw	r2,32(r2)
+ 802fec4:	100b883a 	mov	r5,r2
+ 802fec8:	01020174 	movhi	r4,2053
+ 802fecc:	212a8e04 	addi	r4,r4,-21960
+ 802fed0:	8002c780 	call	8002c78 <printf>
+         panic ("sbcomp:bad");
+ 802fed4:	01020174 	movhi	r4,2053
+ 802fed8:	212a9304 	addi	r4,r4,-21940
+ 802fedc:	80271780 	call	8027178 <panic>
+      /* If there is room for all the data in M in N, then
+       * just copy the data to N.  Note that sbdrop will 
+       * increment the n->m_data pointer, so that we must
+       * correct n->m_memsz.
+       */
+      if ( n && (sb->sb_flags & SB_MBCOMP) &&
+ 802fee0:	e0bffd17 	ldw	r2,-12(fp)
+ 802fee4:	10003226 	beq	r2,zero,802ffb0 <sbcompress+0x160>
+ 802fee8:	e0bfff17 	ldw	r2,-4(fp)
+ 802feec:	1080070b 	ldhu	r2,28(r2)
+ 802fef0:	10bfffcc 	andi	r2,r2,65535
+ 802fef4:	1080200c 	andi	r2,r2,128
+ 802fef8:	10002d26 	beq	r2,zero,802ffb0 <sbcompress+0x160>
+          ((n->m_len + m->m_len) <
+ 802fefc:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff00:	10c00217 	ldw	r3,8(r2)
+ 802ff04:	e0bffe17 	ldw	r2,-8(fp)
+ 802ff08:	10800217 	ldw	r2,8(r2)
+ 802ff0c:	1887883a 	add	r3,r3,r2
+          n->m_memsz - (n->m_data - n->m_base) ) ) 
+ 802ff10:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff14:	10800517 	ldw	r2,20(r2)
+ 802ff18:	e13ffd17 	ldw	r4,-12(fp)
+ 802ff1c:	21400317 	ldw	r5,12(r4)
+ 802ff20:	e13ffd17 	ldw	r4,-12(fp)
+ 802ff24:	21000417 	ldw	r4,16(r4)
+ 802ff28:	2909c83a 	sub	r4,r5,r4
+ 802ff2c:	1105c83a 	sub	r2,r2,r4
+      if ( n && (sb->sb_flags & SB_MBCOMP) &&
+ 802ff30:	18801f2e 	bgeu	r3,r2,802ffb0 <sbcompress+0x160>
+      {
+         MEMCPY(n->m_data+n->m_len, m->m_data, m->m_len);
+ 802ff34:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff38:	10c00317 	ldw	r3,12(r2)
+ 802ff3c:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff40:	10800217 	ldw	r2,8(r2)
+ 802ff44:	1887883a 	add	r3,r3,r2
+ 802ff48:	e0bffe17 	ldw	r2,-8(fp)
+ 802ff4c:	11000317 	ldw	r4,12(r2)
+ 802ff50:	e0bffe17 	ldw	r2,-8(fp)
+ 802ff54:	10800217 	ldw	r2,8(r2)
+ 802ff58:	100d883a 	mov	r6,r2
+ 802ff5c:	200b883a 	mov	r5,r4
+ 802ff60:	1809883a 	mov	r4,r3
+ 802ff64:	80086b80 	call	80086b8 <memcpy>
+         sballoc(sb, m);
+ 802ff68:	e0bfff17 	ldw	r2,-4(fp)
+ 802ff6c:	10c00017 	ldw	r3,0(r2)
+ 802ff70:	e0bffe17 	ldw	r2,-8(fp)
+ 802ff74:	10800217 	ldw	r2,8(r2)
+ 802ff78:	1887883a 	add	r3,r3,r2
+ 802ff7c:	e0bfff17 	ldw	r2,-4(fp)
+ 802ff80:	10c00015 	stw	r3,0(r2)
+         n->m_len += m->m_len;
+ 802ff84:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff88:	10c00217 	ldw	r3,8(r2)
+ 802ff8c:	e0bffe17 	ldw	r2,-8(fp)
+ 802ff90:	10800217 	ldw	r2,8(r2)
+ 802ff94:	1887883a 	add	r3,r3,r2
+ 802ff98:	e0bffd17 	ldw	r2,-12(fp)
+ 802ff9c:	10c00215 	stw	r3,8(r2)
+         m = m_free(m);
+ 802ffa0:	e13ffe17 	ldw	r4,-8(fp)
+ 802ffa4:	8029bf80 	call	8029bf8 <m_free>
+ 802ffa8:	e0bffe15 	stw	r2,-8(fp)
+         continue;
+ 802ffac:	00001706 	br	803000c <sbcompress+0x1bc>
+      }
+      sballoc(sb, m);
+ 802ffb0:	e0bfff17 	ldw	r2,-4(fp)
+ 802ffb4:	10c00017 	ldw	r3,0(r2)
+ 802ffb8:	e0bffe17 	ldw	r2,-8(fp)
+ 802ffbc:	10800217 	ldw	r2,8(r2)
+ 802ffc0:	1887883a 	add	r3,r3,r2
+ 802ffc4:	e0bfff17 	ldw	r2,-4(fp)
+ 802ffc8:	10c00015 	stw	r3,0(r2)
+      if (n)
+ 802ffcc:	e0bffd17 	ldw	r2,-12(fp)
+ 802ffd0:	10000426 	beq	r2,zero,802ffe4 <sbcompress+0x194>
+         n->m_next = m;
+ 802ffd4:	e0bffd17 	ldw	r2,-12(fp)
+ 802ffd8:	e0fffe17 	ldw	r3,-8(fp)
+ 802ffdc:	10c00615 	stw	r3,24(r2)
+ 802ffe0:	00000306 	br	802fff0 <sbcompress+0x1a0>
+      else
+         sb->sb_mb = m;
+ 802ffe4:	e0bfff17 	ldw	r2,-4(fp)
+ 802ffe8:	e0fffe17 	ldw	r3,-8(fp)
+ 802ffec:	10c00615 	stw	r3,24(r2)
+      n = m;
+ 802fff0:	e0bffe17 	ldw	r2,-8(fp)
+ 802fff4:	e0bffd15 	stw	r2,-12(fp)
+      m = m->m_next;
+ 802fff8:	e0bffe17 	ldw	r2,-8(fp)
+ 802fffc:	10800617 	ldw	r2,24(r2)
+ 8030000:	e0bffe15 	stw	r2,-8(fp)
+      n->m_next = 0;
+ 8030004:	e0bffd17 	ldw	r2,-12(fp)
+ 8030008:	10000615 	stw	zero,24(r2)
+   while (m) 
+ 803000c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030010:	103f971e 	bne	r2,zero,802fe70 <sbcompress+0x20>
+   }
+}
+ 8030014:	0001883a 	nop
+ 8030018:	e037883a 	mov	sp,fp
+ 803001c:	dfc00117 	ldw	ra,4(sp)
+ 8030020:	df000017 	ldw	fp,0(sp)
+ 8030024:	dec00204 	addi	sp,sp,8
+ 8030028:	f800283a 	ret
+
+0803002c <sbflush>:
+ * RETURNS: 
+ */
+
+void
+sbflush(struct sockbuf * sb)
+{
+ 803002c:	defffd04 	addi	sp,sp,-12
+ 8030030:	dfc00215 	stw	ra,8(sp)
+ 8030034:	df000115 	stw	fp,4(sp)
+ 8030038:	df000104 	addi	fp,sp,4
+ 803003c:	e13fff15 	stw	r4,-4(fp)
+   ENTER_CRIT_SECTION(sb);
+ 8030040:	8028e940 	call	8028e94 <irq_Mask>
+   if (sb->sb_flags & SB_LOCK)
+ 8030044:	e0bfff17 	ldw	r2,-4(fp)
+ 8030048:	1080070b 	ldhu	r2,28(r2)
+ 803004c:	10bfffcc 	andi	r2,r2,65535
+ 8030050:	1080004c 	andi	r2,r2,1
+ 8030054:	10000926 	beq	r2,zero,803007c <sbflush+0x50>
+      panic("sbflush");
+ 8030058:	01020174 	movhi	r4,2053
+ 803005c:	212a9604 	addi	r4,r4,-21928
+ 8030060:	80271780 	call	8027178 <panic>
+   while ((sb->sb_mbcnt) || (sb->sb_cc))
+ 8030064:	00000506 	br	803007c <sbflush+0x50>
+      sbdrop (sb, (int)sb->sb_cc);
+ 8030068:	e0bfff17 	ldw	r2,-4(fp)
+ 803006c:	10800017 	ldw	r2,0(r2)
+ 8030070:	100b883a 	mov	r5,r2
+ 8030074:	e13fff17 	ldw	r4,-4(fp)
+ 8030078:	80300b00 	call	80300b0 <sbdrop>
+   while ((sb->sb_mbcnt) || (sb->sb_cc))
+ 803007c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030080:	10800217 	ldw	r2,8(r2)
+ 8030084:	103ff81e 	bne	r2,zero,8030068 <sbflush+0x3c>
+ 8030088:	e0bfff17 	ldw	r2,-4(fp)
+ 803008c:	10800017 	ldw	r2,0(r2)
+ 8030090:	103ff51e 	bne	r2,zero,8030068 <sbflush+0x3c>
+   EXIT_CRIT_SECTION(sb);
+ 8030094:	8028ef40 	call	8028ef4 <irq_Unmask>
+}
+ 8030098:	0001883a 	nop
+ 803009c:	e037883a 	mov	sp,fp
+ 80300a0:	dfc00117 	ldw	ra,4(sp)
+ 80300a4:	df000017 	ldw	fp,0(sp)
+ 80300a8:	dec00204 	addi	sp,sp,8
+ 80300ac:	f800283a 	ret
+
+080300b0 <sbdrop>:
+ * RETURNS: 
+ */
+
+void
+sbdrop(struct sockbuf * sb, int len)
+{
+ 80300b0:	defff904 	addi	sp,sp,-28
+ 80300b4:	dfc00615 	stw	ra,24(sp)
+ 80300b8:	df000515 	stw	fp,20(sp)
+ 80300bc:	df000504 	addi	fp,sp,20
+ 80300c0:	e13ffc15 	stw	r4,-16(fp)
+ 80300c4:	e17ffb15 	stw	r5,-20(fp)
+   struct mbuf *  m, *  mn;
+   struct mbuf *  next;
+
+   ENTER_CRIT_SECTION(sb);
+ 80300c8:	8028e940 	call	8028e94 <irq_Mask>
+   if ((m = sb->sb_mb) != NULL)
+ 80300cc:	e0bffc17 	ldw	r2,-16(fp)
+ 80300d0:	10800617 	ldw	r2,24(r2)
+ 80300d4:	e0bfff15 	stw	r2,-4(fp)
+ 80300d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80300dc:	10000426 	beq	r2,zero,80300f0 <sbdrop+0x40>
+      next = m->m_act;
+ 80300e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80300e4:	10800717 	ldw	r2,28(r2)
+ 80300e8:	e0bffe15 	stw	r2,-8(fp)
+ 80300ec:	00003706 	br	80301cc <sbdrop+0x11c>
+   else
+      next = NULL;
+ 80300f0:	e03ffe15 	stw	zero,-8(fp)
+   while (len > 0) 
+ 80300f4:	00003506 	br	80301cc <sbdrop+0x11c>
+   {
+      if (m == 0) 
+ 80300f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80300fc:	10000b1e 	bne	r2,zero,803012c <sbdrop+0x7c>
+      {
+         if (next == 0)
+ 8030100:	e0bffe17 	ldw	r2,-8(fp)
+ 8030104:	1000031e 	bne	r2,zero,8030114 <sbdrop+0x64>
+            panic("sbdrop");
+ 8030108:	01020174 	movhi	r4,2053
+ 803010c:	212a9804 	addi	r4,r4,-21920
+ 8030110:	80271780 	call	8027178 <panic>
+         m = next;
+ 8030114:	e0bffe17 	ldw	r2,-8(fp)
+ 8030118:	e0bfff15 	stw	r2,-4(fp)
+         next = m->m_act;
+ 803011c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030120:	10800717 	ldw	r2,28(r2)
+ 8030124:	e0bffe15 	stw	r2,-8(fp)
+         continue;
+ 8030128:	00002806 	br	80301cc <sbdrop+0x11c>
+      }
+      if (m->m_len > (unsigned)len) 
+ 803012c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030130:	10800217 	ldw	r2,8(r2)
+ 8030134:	e0fffb17 	ldw	r3,-20(fp)
+ 8030138:	1880132e 	bgeu	r3,r2,8030188 <sbdrop+0xd8>
+      {
+         m->m_len -= len;
+ 803013c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030140:	10c00217 	ldw	r3,8(r2)
+ 8030144:	e0bffb17 	ldw	r2,-20(fp)
+ 8030148:	1887c83a 	sub	r3,r3,r2
+ 803014c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030150:	10c00215 	stw	r3,8(r2)
+         m->m_data += len;
+ 8030154:	e0bfff17 	ldw	r2,-4(fp)
+ 8030158:	10c00317 	ldw	r3,12(r2)
+ 803015c:	e0bffb17 	ldw	r2,-20(fp)
+ 8030160:	1887883a 	add	r3,r3,r2
+ 8030164:	e0bfff17 	ldw	r2,-4(fp)
+ 8030168:	10c00315 	stw	r3,12(r2)
+         sb->sb_cc -= len;
+ 803016c:	e0bffc17 	ldw	r2,-16(fp)
+ 8030170:	10c00017 	ldw	r3,0(r2)
+ 8030174:	e0bffb17 	ldw	r2,-20(fp)
+ 8030178:	1887c83a 	sub	r3,r3,r2
+ 803017c:	e0bffc17 	ldw	r2,-16(fp)
+ 8030180:	10c00015 	stw	r3,0(r2)
+         break;
+ 8030184:	00001306 	br	80301d4 <sbdrop+0x124>
+      }
+      len -= m->m_len;
+ 8030188:	e0fffb17 	ldw	r3,-20(fp)
+ 803018c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030190:	10800217 	ldw	r2,8(r2)
+ 8030194:	1885c83a 	sub	r2,r3,r2
+ 8030198:	e0bffb15 	stw	r2,-20(fp)
+      sbfree (sb, m);
+ 803019c:	e0bffc17 	ldw	r2,-16(fp)
+ 80301a0:	10c00017 	ldw	r3,0(r2)
+ 80301a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80301a8:	10800217 	ldw	r2,8(r2)
+ 80301ac:	1887c83a 	sub	r3,r3,r2
+ 80301b0:	e0bffc17 	ldw	r2,-16(fp)
+ 80301b4:	10c00015 	stw	r3,0(r2)
+      MFREE(m, mn);
+ 80301b8:	e13fff17 	ldw	r4,-4(fp)
+ 80301bc:	8029bf80 	call	8029bf8 <m_free>
+ 80301c0:	e0bffd15 	stw	r2,-12(fp)
+      m = mn;
+ 80301c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80301c8:	e0bfff15 	stw	r2,-4(fp)
+   while (len > 0) 
+ 80301cc:	e0bffb17 	ldw	r2,-20(fp)
+ 80301d0:	00bfc916 	blt	zero,r2,80300f8 <sbdrop+0x48>
+   }
+   while (m && m->m_len == 0) 
+ 80301d4:	00000c06 	br	8030208 <sbdrop+0x158>
+   {
+      sbfree(sb, m);
+ 80301d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80301dc:	10c00017 	ldw	r3,0(r2)
+ 80301e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80301e4:	10800217 	ldw	r2,8(r2)
+ 80301e8:	1887c83a 	sub	r3,r3,r2
+ 80301ec:	e0bffc17 	ldw	r2,-16(fp)
+ 80301f0:	10c00015 	stw	r3,0(r2)
+      MFREE(m, mn);
+ 80301f4:	e13fff17 	ldw	r4,-4(fp)
+ 80301f8:	8029bf80 	call	8029bf8 <m_free>
+ 80301fc:	e0bffd15 	stw	r2,-12(fp)
+      m = mn;
+ 8030200:	e0bffd17 	ldw	r2,-12(fp)
+ 8030204:	e0bfff15 	stw	r2,-4(fp)
+   while (m && m->m_len == 0) 
+ 8030208:	e0bfff17 	ldw	r2,-4(fp)
+ 803020c:	10000326 	beq	r2,zero,803021c <sbdrop+0x16c>
+ 8030210:	e0bfff17 	ldw	r2,-4(fp)
+ 8030214:	10800217 	ldw	r2,8(r2)
+ 8030218:	103fef26 	beq	r2,zero,80301d8 <sbdrop+0x128>
+   }
+   if (m) 
+ 803021c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030220:	10000726 	beq	r2,zero,8030240 <sbdrop+0x190>
+   {
+      sb->sb_mb = m;
+ 8030224:	e0bffc17 	ldw	r2,-16(fp)
+ 8030228:	e0ffff17 	ldw	r3,-4(fp)
+ 803022c:	10c00615 	stw	r3,24(r2)
+      m->m_act = next;
+ 8030230:	e0bfff17 	ldw	r2,-4(fp)
+ 8030234:	e0fffe17 	ldw	r3,-8(fp)
+ 8030238:	10c00715 	stw	r3,28(r2)
+ 803023c:	00000306 	br	803024c <sbdrop+0x19c>
+   } else
+      sb->sb_mb = next;
+ 8030240:	e0bffc17 	ldw	r2,-16(fp)
+ 8030244:	e0fffe17 	ldw	r3,-8(fp)
+ 8030248:	10c00615 	stw	r3,24(r2)
+   EXIT_CRIT_SECTION(sb);
+ 803024c:	8028ef40 	call	8028ef4 <irq_Unmask>
+}
+ 8030250:	0001883a 	nop
+ 8030254:	e037883a 	mov	sp,fp
+ 8030258:	dfc00117 	ldw	ra,4(sp)
+ 803025c:	df000017 	ldw	fp,0(sp)
+ 8030260:	dec00204 	addi	sp,sp,8
+ 8030264:	f800283a 	ret
+
+08030268 <sbdropend>:
+ * RETURNS: 
+ */
+
+void
+sbdropend(struct sockbuf * sb, struct mbuf * m)
+{
+ 8030268:	defff904 	addi	sp,sp,-28
+ 803026c:	dfc00615 	stw	ra,24(sp)
+ 8030270:	df000515 	stw	fp,20(sp)
+ 8030274:	df000504 	addi	fp,sp,20
+ 8030278:	e13ffc15 	stw	r4,-16(fp)
+ 803027c:	e17ffb15 	stw	r5,-20(fp)
+   struct mbuf *  nmb, *   pmb;
+   int   len;
+   ENTER_CRIT_SECTION(sb);
+ 8030280:	8028e940 	call	8028e94 <irq_Mask>
+   len = mbuf_len(m);
+ 8030284:	e13ffb17 	ldw	r4,-20(fp)
+ 8030288:	802a1d80 	call	802a1d8 <mbuf_len>
+ 803028c:	e0bffd15 	stw	r2,-12(fp)
+   if (len > 0)
+ 8030290:	e0bffd17 	ldw	r2,-12(fp)
+ 8030294:	0080070e 	bge	zero,r2,80302b4 <sbdropend+0x4c>
+      m_adj(sb->sb_mb, -len); /* Adjust the lengths of the mbuf chain */
+ 8030298:	e0bffc17 	ldw	r2,-16(fp)
+ 803029c:	10c00617 	ldw	r3,24(r2)
+ 80302a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80302a4:	0085c83a 	sub	r2,zero,r2
+ 80302a8:	100b883a 	mov	r5,r2
+ 80302ac:	1809883a 	mov	r4,r3
+ 80302b0:	802a0180 	call	802a018 <m_adj>
+   nmb = sb->sb_mb;
+ 80302b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80302b8:	10800617 	ldw	r2,24(r2)
+ 80302bc:	e0bfff15 	stw	r2,-4(fp)
+   pmb = NULL;
+ 80302c0:	e03ffe15 	stw	zero,-8(fp)
+   if (sb->sb_mb->m_len == 0)
+ 80302c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80302c8:	10800617 	ldw	r2,24(r2)
+ 80302cc:	10800217 	ldw	r2,8(r2)
+ 80302d0:	1000081e 	bne	r2,zero,80302f4 <sbdropend+0x8c>
+      sb->sb_mb = NULL;
+ 80302d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80302d8:	10000615 	stw	zero,24(r2)
+   while (nmb && (nmb->m_len !=0))  /* Release mbufs that have a 0 len */
+ 80302dc:	00000506 	br	80302f4 <sbdropend+0x8c>
+   {
+      pmb = nmb;  /* Remember previous */
+ 80302e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80302e4:	e0bffe15 	stw	r2,-8(fp)
+      nmb = nmb->m_next;    
+ 80302e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80302ec:	10800617 	ldw	r2,24(r2)
+ 80302f0:	e0bfff15 	stw	r2,-4(fp)
+   while (nmb && (nmb->m_len !=0))  /* Release mbufs that have a 0 len */
+ 80302f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80302f8:	10000326 	beq	r2,zero,8030308 <sbdropend+0xa0>
+ 80302fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030300:	10800217 	ldw	r2,8(r2)
+ 8030304:	103ff61e 	bne	r2,zero,80302e0 <sbdropend+0x78>
+   }
+   if (nmb && (nmb->m_len == 0)) /* Assume once 0 len found, all the rest */
+ 8030308:	e0bfff17 	ldw	r2,-4(fp)
+ 803030c:	10000926 	beq	r2,zero,8030334 <sbdropend+0xcc>
+ 8030310:	e0bfff17 	ldw	r2,-4(fp)
+ 8030314:	10800217 	ldw	r2,8(r2)
+ 8030318:	1000061e 	bne	r2,zero,8030334 <sbdropend+0xcc>
+   {                             /* are zeroes */ 
+      if (pmb != NULL)
+ 803031c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030320:	10000226 	beq	r2,zero,803032c <sbdropend+0xc4>
+         pmb->m_next = NULL;
+ 8030324:	e0bffe17 	ldw	r2,-8(fp)
+ 8030328:	10000615 	stw	zero,24(r2)
+      m_freem(nmb);            
+ 803032c:	e13fff17 	ldw	r4,-4(fp)
+ 8030330:	8029cfc0 	call	8029cfc <m_freem>
+   }
+   sb->sb_cc -= len;       /* Do a sbfree using the len */
+ 8030334:	e0bffc17 	ldw	r2,-16(fp)
+ 8030338:	10c00017 	ldw	r3,0(r2)
+ 803033c:	e0bffd17 	ldw	r2,-12(fp)
+ 8030340:	1887c83a 	sub	r3,r3,r2
+ 8030344:	e0bffc17 	ldw	r2,-16(fp)
+ 8030348:	10c00015 	stw	r3,0(r2)
+   EXIT_CRIT_SECTION(sb);
+ 803034c:	8028ef40 	call	8028ef4 <irq_Unmask>
+}
+ 8030350:	0001883a 	nop
+ 8030354:	e037883a 	mov	sp,fp
+ 8030358:	dfc00117 	ldw	ra,4(sp)
+ 803035c:	df000017 	ldw	fp,0(sp)
+ 8030360:	dec00204 	addi	sp,sp,8
+ 8030364:	f800283a 	ret
+
+08030368 <sbdroprecord>:
+ * RETURNS: 
+ */
+
+void
+sbdroprecord(struct sockbuf * sb)
+{
+ 8030368:	defffb04 	addi	sp,sp,-20
+ 803036c:	dfc00415 	stw	ra,16(sp)
+ 8030370:	df000315 	stw	fp,12(sp)
+ 8030374:	df000304 	addi	fp,sp,12
+ 8030378:	e13ffd15 	stw	r4,-12(fp)
+   struct mbuf *  m, *  mn;
+
+   ENTER_CRIT_SECTION(sb);
+ 803037c:	8028e940 	call	8028e94 <irq_Mask>
+   m = sb->sb_mb;
+ 8030380:	e0bffd17 	ldw	r2,-12(fp)
+ 8030384:	10800617 	ldw	r2,24(r2)
+ 8030388:	e0bfff15 	stw	r2,-4(fp)
+   if (m)
+ 803038c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030390:	10001226 	beq	r2,zero,80303dc <sbdroprecord+0x74>
+   {  sb->sb_mb = m->m_act;
+ 8030394:	e0bfff17 	ldw	r2,-4(fp)
+ 8030398:	10c00717 	ldw	r3,28(r2)
+ 803039c:	e0bffd17 	ldw	r2,-12(fp)
+ 80303a0:	10c00615 	stw	r3,24(r2)
+      do 
+      {  sbfree(sb, m);
+ 80303a4:	e0bffd17 	ldw	r2,-12(fp)
+ 80303a8:	10c00017 	ldw	r3,0(r2)
+ 80303ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80303b0:	10800217 	ldw	r2,8(r2)
+ 80303b4:	1887c83a 	sub	r3,r3,r2
+ 80303b8:	e0bffd17 	ldw	r2,-12(fp)
+ 80303bc:	10c00015 	stw	r3,0(r2)
+         MFREE(m, mn);
+ 80303c0:	e13fff17 	ldw	r4,-4(fp)
+ 80303c4:	8029bf80 	call	8029bf8 <m_free>
+ 80303c8:	e0bffe15 	stw	r2,-8(fp)
+      } while ((m = mn) != NULL);
+ 80303cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80303d0:	e0bfff15 	stw	r2,-4(fp)
+ 80303d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80303d8:	103ff21e 	bne	r2,zero,80303a4 <sbdroprecord+0x3c>
+         }
+   EXIT_CRIT_SECTION(sb);
+ 80303dc:	8028ef40 	call	8028ef4 <irq_Unmask>
+}
+ 80303e0:	0001883a 	nop
+ 80303e4:	e037883a 	mov	sp,fp
+ 80303e8:	dfc00117 	ldw	ra,4(sp)
+ 80303ec:	df000017 	ldw	fp,0(sp)
+ 80303f0:	dec00204 	addi	sp,sp,8
+ 80303f4:	f800283a 	ret
+
+080303f8 <t_select>:
+int
+t_select(fd_set * in,   /* lists of sockets to watch */
+   fd_set * out,
+   fd_set * ex,
+   long  tv)   /* ticks to wait */
+{
+ 80303f8:	defe7204 	addi	sp,sp,-1592
+ 80303fc:	dfc18d15 	stw	ra,1588(sp)
+ 8030400:	df018c15 	stw	fp,1584(sp)
+ 8030404:	df018c04 	addi	fp,sp,1584
+ 8030408:	e13e7715 	stw	r4,-1572(fp)
+ 803040c:	e17e7615 	stw	r5,-1576(fp)
+ 8030410:	e1be7515 	stw	r6,-1580(fp)
+ 8030414:	e1fe7415 	stw	r7,-1584(fp)
+   fd_set obits[3], ibits [3];
+   u_long   tmo;
+   int   retval   =  0;
+ 8030418:	e03fff15 	stw	zero,-4(fp)
+
+   MEMSET(&obits, 0, sizeof(obits));
+ 803041c:	e0bf3b04 	addi	r2,fp,-788
+ 8030420:	0180c304 	movi	r6,780
+ 8030424:	000b883a 	mov	r5,zero
+ 8030428:	1009883a 	mov	r4,r2
+ 803042c:	80088e40 	call	80088e4 <memset>
+   MEMSET(&ibits, 0, sizeof(ibits));
+ 8030430:	e0be7804 	addi	r2,fp,-1568
+ 8030434:	0180c304 	movi	r6,780
+ 8030438:	000b883a 	mov	r5,zero
+ 803043c:	1009883a 	mov	r4,r2
+ 8030440:	80088e40 	call	80088e4 <memset>
+
+   if (in)
+ 8030444:	e0be7717 	ldw	r2,-1572(fp)
+ 8030448:	10000526 	beq	r2,zero,8030460 <t_select+0x68>
+      MEMCPY(&ibits[0], in, sizeof(fd_set));
+ 803044c:	e0be7804 	addi	r2,fp,-1568
+ 8030450:	01804104 	movi	r6,260
+ 8030454:	e17e7717 	ldw	r5,-1572(fp)
+ 8030458:	1009883a 	mov	r4,r2
+ 803045c:	80086b80 	call	80086b8 <memcpy>
+   if (out)
+ 8030460:	e0be7617 	ldw	r2,-1576(fp)
+ 8030464:	10000626 	beq	r2,zero,8030480 <t_select+0x88>
+      MEMCPY(&ibits[1], out, sizeof(fd_set));
+ 8030468:	e0be7804 	addi	r2,fp,-1568
+ 803046c:	10804104 	addi	r2,r2,260
+ 8030470:	01804104 	movi	r6,260
+ 8030474:	e17e7617 	ldw	r5,-1576(fp)
+ 8030478:	1009883a 	mov	r4,r2
+ 803047c:	80086b80 	call	80086b8 <memcpy>
+   if (ex)
+ 8030480:	e0be7517 	ldw	r2,-1580(fp)
+ 8030484:	10000626 	beq	r2,zero,80304a0 <t_select+0xa8>
+      MEMCPY(&ibits[2], ex, sizeof(fd_set));
+ 8030488:	e0be7804 	addi	r2,fp,-1568
+ 803048c:	10808204 	addi	r2,r2,520
+ 8030490:	01804104 	movi	r6,260
+ 8030494:	e17e7517 	ldw	r5,-1580(fp)
+ 8030498:	1009883a 	mov	r4,r2
+ 803049c:	80086b80 	call	80086b8 <memcpy>
+   tmo = cticks + tv;
+ 80304a0:	d0e07d17 	ldw	r3,-32268(gp)
+ 80304a4:	e0be7417 	ldw	r2,-1584(fp)
+ 80304a8:	1885883a 	add	r2,r3,r2
+ 80304ac:	e0bffe15 	stw	r2,-8(fp)
+
+   /* if all the fd_sets are empty, just block;  else do a real select() */
+   if ((ibits[0].fd_count == 0) && (ibits[1].fd_count == 0) &&
+ 80304b0:	e0be7817 	ldw	r2,-1568(fp)
+ 80304b4:	10000c1e 	bne	r2,zero,80304e8 <t_select+0xf0>
+ 80304b8:	e0beb917 	ldw	r2,-1308(fp)
+ 80304bc:	10000a1e 	bne	r2,zero,80304e8 <t_select+0xf0>
+       (ibits[2].fd_count == 0))
+ 80304c0:	e0befa17 	ldw	r2,-1048(fp)
+   if ((ibits[0].fd_count == 0) && (ibits[1].fd_count == 0) &&
+ 80304c4:	1000081e 	bne	r2,zero,80304e8 <t_select+0xf0>
+   {
+      if (tv > 0)      /* make sure we don't block on nothing forever */
+ 80304c8:	e0be7417 	ldw	r2,-1584(fp)
+ 80304cc:	00801f0e 	bge	zero,r2,803054c <t_select+0x154>
+         while (tmo > cticks)
+         {
+            tk_yield();
+         }
+#else
+         TK_SLEEP(tv);
+ 80304d0:	e0be7417 	ldw	r2,-1584(fp)
+ 80304d4:	10800044 	addi	r2,r2,1
+ 80304d8:	10bfffcc 	andi	r2,r2,65535
+ 80304dc:	1009883a 	mov	r4,r2
+ 80304e0:	801730c0 	call	801730c <OSTimeDly>
+      if (tv > 0)      /* make sure we don't block on nothing forever */
+ 80304e4:	00001906 	br	803054c <t_select+0x154>
+
+      /* Lock the net semaphore before going into selscan. Upon
+       * return we will either call tcp_sleep(), which unlocks the
+       * semaphore, or fall into the unlock statement.
+       */
+      LOCK_NET_RESOURCE(NET_RESID);
+ 80304e8:	0009883a 	mov	r4,zero
+ 80304ec:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      while ((retval = sock_selscan(ibits, obits)) == 0)
+ 80304f0:	00000a06 	br	803051c <t_select+0x124>
+      {
+         if (tv != -1L) 
+ 80304f4:	e0be7417 	ldw	r2,-1584(fp)
+ 80304f8:	10bfffe0 	cmpeqi	r2,r2,-1
+ 80304fc:	1000031e 	bne	r2,zero,803050c <t_select+0x114>
+         {
+            if (tmo <= cticks)
+ 8030500:	d0e07d17 	ldw	r3,-32268(gp)
+ 8030504:	e0bffe17 	ldw	r2,-8(fp)
+ 8030508:	18800d2e 	bgeu	r3,r2,8030540 <t_select+0x148>
+               break;
+         }
+         select_wait = 1;
+ 803050c:	00800044 	movi	r2,1
+ 8030510:	d0a0850d 	sth	r2,-32236(gp)
+         tcp_sleep (&select_wait);
+ 8030514:	d1208504 	addi	r4,gp,-32236
+ 8030518:	8027a540 	call	8027a54 <tcp_sleep>
+      while ((retval = sock_selscan(ibits, obits)) == 0)
+ 803051c:	e0ff3b04 	addi	r3,fp,-788
+ 8030520:	e0be7804 	addi	r2,fp,-1568
+ 8030524:	180b883a 	mov	r5,r3
+ 8030528:	1009883a 	mov	r4,r2
+ 803052c:	80305c80 	call	80305c8 <sock_selscan>
+ 8030530:	e0bfff15 	stw	r2,-4(fp)
+ 8030534:	e0bfff17 	ldw	r2,-4(fp)
+ 8030538:	103fee26 	beq	r2,zero,80304f4 <t_select+0xfc>
+ 803053c:	00000106 	br	8030544 <t_select+0x14c>
+               break;
+ 8030540:	0001883a 	nop
+      }
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 8030544:	0009883a 	mov	r4,zero
+ 8030548:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   }
+
+   if (retval >= 0)
+ 803054c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030550:	10001716 	blt	r2,zero,80305b0 <t_select+0x1b8>
+   {
+      if (in)
+ 8030554:	e0be7717 	ldw	r2,-1572(fp)
+ 8030558:	10000526 	beq	r2,zero,8030570 <t_select+0x178>
+         MEMCPY(in, &obits[0], sizeof(fd_set));
+ 803055c:	e0bf3b04 	addi	r2,fp,-788
+ 8030560:	01804104 	movi	r6,260
+ 8030564:	100b883a 	mov	r5,r2
+ 8030568:	e13e7717 	ldw	r4,-1572(fp)
+ 803056c:	80086b80 	call	80086b8 <memcpy>
+      if (out)
+ 8030570:	e0be7617 	ldw	r2,-1576(fp)
+ 8030574:	10000626 	beq	r2,zero,8030590 <t_select+0x198>
+         MEMCPY(out, &obits[1], sizeof(fd_set));
+ 8030578:	e0bf3b04 	addi	r2,fp,-788
+ 803057c:	10804104 	addi	r2,r2,260
+ 8030580:	01804104 	movi	r6,260
+ 8030584:	100b883a 	mov	r5,r2
+ 8030588:	e13e7617 	ldw	r4,-1576(fp)
+ 803058c:	80086b80 	call	80086b8 <memcpy>
+      if (ex)
+ 8030590:	e0be7517 	ldw	r2,-1580(fp)
+ 8030594:	10000626 	beq	r2,zero,80305b0 <t_select+0x1b8>
+         MEMCPY(ex, &obits[2], sizeof(fd_set));
+ 8030598:	e0bf3b04 	addi	r2,fp,-788
+ 803059c:	10808204 	addi	r2,r2,520
+ 80305a0:	01804104 	movi	r6,260
+ 80305a4:	100b883a 	mov	r5,r2
+ 80305a8:	e13e7517 	ldw	r4,-1580(fp)
+ 80305ac:	80086b80 	call	80086b8 <memcpy>
+   }
+   return retval;
+ 80305b0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80305b4:	e037883a 	mov	sp,fp
+ 80305b8:	dfc00117 	ldw	ra,4(sp)
+ 80305bc:	df000017 	ldw	fp,0(sp)
+ 80305c0:	dec00204 	addi	sp,sp,8
+ 80305c4:	f800283a 	ret
+
+080305c8 <sock_selscan>:
+ * RETURNS: 
+ */
+
+int
+sock_selscan(fd_set * ibits, fd_set * obits)
+{
+ 80305c8:	defff604 	addi	sp,sp,-40
+ 80305cc:	dfc00915 	stw	ra,36(sp)
+ 80305d0:	df000815 	stw	fp,32(sp)
+ 80305d4:	df000804 	addi	fp,sp,32
+ 80305d8:	e13ff915 	stw	r4,-28(fp)
+ 80305dc:	e17ff815 	stw	r5,-32(fp)
+   fd_set *in, *out;
+   int   which;
+   int   sock;
+   int   flag  =  0;
+ 80305e0:	e03ffd15 	stw	zero,-12(fp)
+   int   num_sel  =  0;
+ 80305e4:	e03ffc15 	stw	zero,-16(fp)
+
+   for (which = 0; which < 3; which++)
+ 80305e8:	e03fff15 	stw	zero,-4(fp)
+ 80305ec:	00003d06 	br	80306e4 <sock_selscan+0x11c>
+   {
+      switch (which)
+ 80305f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80305f4:	10800060 	cmpeqi	r2,r2,1
+ 80305f8:	1000081e 	bne	r2,zero,803061c <sock_selscan+0x54>
+ 80305fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030600:	108000a0 	cmpeqi	r2,r2,2
+ 8030604:	1000081e 	bne	r2,zero,8030628 <sock_selscan+0x60>
+ 8030608:	e0bfff17 	ldw	r2,-4(fp)
+ 803060c:	1000081e 	bne	r2,zero,8030630 <sock_selscan+0x68>
+      {
+      case 0:
+         flag = SOREAD; break;
+ 8030610:	00800044 	movi	r2,1
+ 8030614:	e0bffd15 	stw	r2,-12(fp)
+ 8030618:	00000506 	br	8030630 <sock_selscan+0x68>
+
+      case 1:
+         flag = SOWRITE; break;
+ 803061c:	00800084 	movi	r2,2
+ 8030620:	e0bffd15 	stw	r2,-12(fp)
+ 8030624:	00000206 	br	8030630 <sock_selscan+0x68>
+
+      case 2:
+         flag = 0; break;
+ 8030628:	e03ffd15 	stw	zero,-12(fp)
+ 803062c:	0001883a 	nop
+      }
+      in = &ibits [which];
+ 8030630:	e0bfff17 	ldw	r2,-4(fp)
+ 8030634:	10804124 	muli	r2,r2,260
+ 8030638:	e0fff917 	ldw	r3,-28(fp)
+ 803063c:	1885883a 	add	r2,r3,r2
+ 8030640:	e0bffb15 	stw	r2,-20(fp)
+      out = &obits [which];
+ 8030644:	e0bfff17 	ldw	r2,-4(fp)
+ 8030648:	10804124 	muli	r2,r2,260
+ 803064c:	e0fff817 	ldw	r3,-32(fp)
+ 8030650:	1885883a 	add	r2,r3,r2
+ 8030654:	e0bffa15 	stw	r2,-24(fp)
+      for (sock = 0; sock < (int)in->fd_count; sock++)
+ 8030658:	e03ffe15 	stw	zero,-8(fp)
+ 803065c:	00001906 	br	80306c4 <sock_selscan+0xfc>
+      {
+         if (sock_select (in->fd_array[sock], flag))
+ 8030660:	e0fffb17 	ldw	r3,-20(fp)
+ 8030664:	e0bffe17 	ldw	r2,-8(fp)
+ 8030668:	10800044 	addi	r2,r2,1
+ 803066c:	100490ba 	slli	r2,r2,2
+ 8030670:	1885883a 	add	r2,r3,r2
+ 8030674:	10800017 	ldw	r2,0(r2)
+ 8030678:	e17ffd17 	ldw	r5,-12(fp)
+ 803067c:	1009883a 	mov	r4,r2
+ 8030680:	80307080 	call	8030708 <sock_select>
+ 8030684:	10000c26 	beq	r2,zero,80306b8 <sock_selscan+0xf0>
+         {
+            FD_SET(in->fd_array[sock], out);
+ 8030688:	e0fffb17 	ldw	r3,-20(fp)
+ 803068c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030690:	10800044 	addi	r2,r2,1
+ 8030694:	100490ba 	slli	r2,r2,2
+ 8030698:	1885883a 	add	r2,r3,r2
+ 803069c:	10800017 	ldw	r2,0(r2)
+ 80306a0:	e17ffa17 	ldw	r5,-24(fp)
+ 80306a4:	1009883a 	mov	r4,r2
+ 80306a8:	8030b180 	call	8030b18 <ifd_set>
+            num_sel++;
+ 80306ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80306b0:	10800044 	addi	r2,r2,1
+ 80306b4:	e0bffc15 	stw	r2,-16(fp)
+      for (sock = 0; sock < (int)in->fd_count; sock++)
+ 80306b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80306bc:	10800044 	addi	r2,r2,1
+ 80306c0:	e0bffe15 	stw	r2,-8(fp)
+ 80306c4:	e0bffb17 	ldw	r2,-20(fp)
+ 80306c8:	10800017 	ldw	r2,0(r2)
+ 80306cc:	1007883a 	mov	r3,r2
+ 80306d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80306d4:	10ffe216 	blt	r2,r3,8030660 <sock_selscan+0x98>
+   for (which = 0; which < 3; which++)
+ 80306d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80306dc:	10800044 	addi	r2,r2,1
+ 80306e0:	e0bfff15 	stw	r2,-4(fp)
+ 80306e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80306e8:	108000d0 	cmplti	r2,r2,3
+ 80306ec:	103fc01e 	bne	r2,zero,80305f0 <sock_selscan+0x28>
+         }
+      }
+   }
+   return num_sel;
+ 80306f0:	e0bffc17 	ldw	r2,-16(fp)
+}
+ 80306f4:	e037883a 	mov	sp,fp
+ 80306f8:	dfc00117 	ldw	ra,4(sp)
+ 80306fc:	df000017 	ldw	fp,0(sp)
+ 8030700:	dec00204 	addi	sp,sp,8
+ 8030704:	f800283a 	ret
+
+08030708 <sock_select>:
+ * RETURNS: 
+ */
+
+int
+sock_select(long sock, int flag)
+{
+ 8030708:	defffa04 	addi	sp,sp,-24
+ 803070c:	dfc00515 	stw	ra,20(sp)
+ 8030710:	df000415 	stw	fp,16(sp)
+ 8030714:	df000404 	addi	fp,sp,16
+ 8030718:	e13ffd15 	stw	r4,-12(fp)
+ 803071c:	e17ffc15 	stw	r5,-16(fp)
+   struct socket *   so;
+   int   ready =  0;
+ 8030720:	e03fff15 	stw	zero,-4(fp)
+
+   so = LONG2SO(sock);
+ 8030724:	e0bffd17 	ldw	r2,-12(fp)
+ 8030728:	10bffc04 	addi	r2,r2,-16
+ 803072c:	100490ba 	slli	r2,r2,2
+ 8030730:	e0bffe15 	stw	r2,-8(fp)
+
+   switch (flag) 
+ 8030734:	e0bffc17 	ldw	r2,-16(fp)
+ 8030738:	10800060 	cmpeqi	r2,r2,1
+ 803073c:	1000061e 	bne	r2,zero,8030758 <sock_select+0x50>
+ 8030740:	e0bffc17 	ldw	r2,-16(fp)
+ 8030744:	108000a0 	cmpeqi	r2,r2,2
+ 8030748:	1000211e 	bne	r2,zero,80307d0 <sock_select+0xc8>
+ 803074c:	e0bffc17 	ldw	r2,-16(fp)
+ 8030750:	10004326 	beq	r2,zero,8030860 <sock_select+0x158>
+ 8030754:	00006006 	br	80308d8 <sock_select+0x1d0>
+   {
+   case SOREAD:
+      /* can we read something from so? */
+      if (so->so_rcv.sb_cc)
+ 8030758:	e0bffe17 	ldw	r2,-8(fp)
+ 803075c:	10800a17 	ldw	r2,40(r2)
+ 8030760:	10000326 	beq	r2,zero,8030770 <sock_select+0x68>
+      {
+         ready = 1;
+ 8030764:	00800044 	movi	r2,1
+ 8030768:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 803076c:	00005a06 	br	80308d8 <sock_select+0x1d0>
+      }
+      if (so->so_state & SS_CANTRCVMORE)
+ 8030770:	e0bffe17 	ldw	r2,-8(fp)
+ 8030774:	1080088b 	ldhu	r2,34(r2)
+ 8030778:	10bfffcc 	andi	r2,r2,65535
+ 803077c:	1080080c 	andi	r2,r2,32
+ 8030780:	10000326 	beq	r2,zero,8030790 <sock_select+0x88>
+      {  ready = 1;
+ 8030784:	00800044 	movi	r2,1
+ 8030788:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 803078c:	00005206 	br	80308d8 <sock_select+0x1d0>
+      }
+      if (so->so_qlen)  /* attach is ready */
+ 8030790:	e0bffe17 	ldw	r2,-8(fp)
+ 8030794:	10801e43 	ldbu	r2,121(r2)
+ 8030798:	10803fcc 	andi	r2,r2,255
+ 803079c:	1080201c 	xori	r2,r2,128
+ 80307a0:	10bfe004 	addi	r2,r2,-128
+ 80307a4:	10000326 	beq	r2,zero,80307b4 <sock_select+0xac>
+      {
+         ready = 1;
+ 80307a8:	00800044 	movi	r2,1
+ 80307ac:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 80307b0:	00004906 	br	80308d8 <sock_select+0x1d0>
+         }
+      }
+#endif   /* TCP_ZEROCOPY */
+
+      /* fall to here if so is not ready to read */
+      so->so_rcv.sb_flags |= SB_SEL;   /* set flag for select wakeup */
+ 80307b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80307b8:	1080110b 	ldhu	r2,68(r2)
+ 80307bc:	10800214 	ori	r2,r2,8
+ 80307c0:	1007883a 	mov	r3,r2
+ 80307c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80307c8:	10c0110d 	sth	r3,68(r2)
+      break;
+ 80307cc:	00004206 	br	80308d8 <sock_select+0x1d0>
+
+   case SOWRITE:
+      if ((sbspace(&(so)->so_snd) > 0) && 
+ 80307d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80307d4:	10801317 	ldw	r2,76(r2)
+ 80307d8:	1007883a 	mov	r3,r2
+ 80307dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80307e0:	10801217 	ldw	r2,72(r2)
+ 80307e4:	1885c83a 	sub	r2,r3,r2
+ 80307e8:	10001816 	blt	r2,zero,803084c <sock_select+0x144>
+ 80307ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80307f0:	10c01317 	ldw	r3,76(r2)
+ 80307f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80307f8:	10801217 	ldw	r2,72(r2)
+ 80307fc:	18801326 	beq	r3,r2,803084c <sock_select+0x144>
+          ((((so)->so_state&SS_ISCONNECTED) || 
+ 8030800:	e0bffe17 	ldw	r2,-8(fp)
+ 8030804:	1080088b 	ldhu	r2,34(r2)
+ 8030808:	10bfffcc 	andi	r2,r2,65535
+ 803080c:	1080008c 	andi	r2,r2,2
+      if ((sbspace(&(so)->so_snd) > 0) && 
+ 8030810:	10000b1e 	bne	r2,zero,8030840 <sock_select+0x138>
+            ((so)->so_proto->pr_flags&PR_CONNREQUIRED)==0) || 
+ 8030814:	e0bffe17 	ldw	r2,-8(fp)
+ 8030818:	10800217 	ldw	r2,8(r2)
+ 803081c:	1080010b 	ldhu	r2,4(r2)
+ 8030820:	10bfffcc 	andi	r2,r2,65535
+ 8030824:	1080010c 	andi	r2,r2,4
+          ((((so)->so_state&SS_ISCONNECTED) || 
+ 8030828:	10000526 	beq	r2,zero,8030840 <sock_select+0x138>
+           ((so)->so_state & SS_CANTSENDMORE)))
+ 803082c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030830:	1080088b 	ldhu	r2,34(r2)
+ 8030834:	10bfffcc 	andi	r2,r2,65535
+ 8030838:	1080040c 	andi	r2,r2,16
+            ((so)->so_proto->pr_flags&PR_CONNREQUIRED)==0) || 
+ 803083c:	10000326 	beq	r2,zero,803084c <sock_select+0x144>
+      {
+         ready = 1;
+ 8030840:	00800044 	movi	r2,1
+ 8030844:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 8030848:	00002306 	br	80308d8 <sock_select+0x1d0>
+      }
+      sbselqueue (&so->so_snd);
+ 803084c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030850:	10801204 	addi	r2,r2,72
+ 8030854:	1009883a 	mov	r4,r2
+ 8030858:	802f8a40 	call	802f8a4 <sbselqueue>
+      break;
+ 803085c:	00001e06 	br	80308d8 <sock_select+0x1d0>
+
+   case 0:
+      if (so->so_oobmark || (so->so_state & SS_RCVATMARK))
+ 8030860:	e0bffe17 	ldw	r2,-8(fp)
+ 8030864:	10801a17 	ldw	r2,104(r2)
+ 8030868:	1000051e 	bne	r2,zero,8030880 <sock_select+0x178>
+ 803086c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030870:	1080088b 	ldhu	r2,34(r2)
+ 8030874:	10bfffcc 	andi	r2,r2,65535
+ 8030878:	1080100c 	andi	r2,r2,64
+ 803087c:	10000326 	beq	r2,zero,803088c <sock_select+0x184>
+      {
+         ready = 1;
+ 8030880:	00800044 	movi	r2,1
+ 8030884:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 8030888:	00001306 	br	80308d8 <sock_select+0x1d0>
+      }
+      if (so->so_error &&
+ 803088c:	e0bffe17 	ldw	r2,-8(fp)
+ 8030890:	10800617 	ldw	r2,24(r2)
+ 8030894:	10000b26 	beq	r2,zero,80308c4 <sock_select+0x1bc>
+          (so->so_error != EINPROGRESS) &&
+ 8030898:	e0bffe17 	ldw	r2,-8(fp)
+ 803089c:	10800617 	ldw	r2,24(r2)
+      if (so->so_error &&
+ 80308a0:	10801de0 	cmpeqi	r2,r2,119
+ 80308a4:	1000071e 	bne	r2,zero,80308c4 <sock_select+0x1bc>
+          (so->so_error != EWOULDBLOCK))
+ 80308a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80308ac:	10800617 	ldw	r2,24(r2)
+          (so->so_error != EINPROGRESS) &&
+ 80308b0:	108002e0 	cmpeqi	r2,r2,11
+ 80308b4:	1000031e 	bne	r2,zero,80308c4 <sock_select+0x1bc>
+      {
+         ready = 1;
+ 80308b8:	00800044 	movi	r2,1
+ 80308bc:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 80308c0:	00000506 	br	80308d8 <sock_select+0x1d0>
+      }
+      sbselqueue(&so->so_rcv);
+ 80308c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80308c8:	10800a04 	addi	r2,r2,40
+ 80308cc:	1009883a 	mov	r4,r2
+ 80308d0:	802f8a40 	call	802f8a4 <sbselqueue>
+      break;
+ 80308d4:	0001883a 	nop
+   }
+
+   return ready;
+ 80308d8:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80308dc:	e037883a 	mov	sp,fp
+ 80308e0:	dfc00117 	ldw	ra,4(sp)
+ 80308e4:	df000017 	ldw	fp,0(sp)
+ 80308e8:	dec00204 	addi	sp,sp,8
+ 80308ec:	f800283a 	ret
+
+080308f0 <in_pcbnotify>:
+void
+in_pcbnotify(struct inpcb * head, 
+   struct in_addr *  dst,
+   int   errnum,
+   void (*notify) __P ((struct inpcb *)))
+{
+ 80308f0:	defff804 	addi	sp,sp,-32
+ 80308f4:	dfc00715 	stw	ra,28(sp)
+ 80308f8:	df000615 	stw	fp,24(sp)
+ 80308fc:	df000604 	addi	fp,sp,24
+ 8030900:	e13ffd15 	stw	r4,-12(fp)
+ 8030904:	e17ffc15 	stw	r5,-16(fp)
+ 8030908:	e1bffb15 	stw	r6,-20(fp)
+ 803090c:	e1fffa15 	stw	r7,-24(fp)
+   struct inpcb * inp, *   oinp;
+
+   for (inp = head->inp_next; inp != head;) 
+ 8030910:	e0bffd17 	ldw	r2,-12(fp)
+ 8030914:	10800017 	ldw	r2,0(r2)
+ 8030918:	e0bfff15 	stw	r2,-4(fp)
+ 803091c:	00001c06 	br	8030990 <in_pcbnotify+0xa0>
+   {
+      if (inp->inp_faddr.s_addr != dst->s_addr ||
+ 8030920:	e0bfff17 	ldw	r2,-4(fp)
+ 8030924:	10c00317 	ldw	r3,12(r2)
+ 8030928:	e0bffc17 	ldw	r2,-16(fp)
+ 803092c:	10800017 	ldw	r2,0(r2)
+ 8030930:	1880031e 	bne	r3,r2,8030940 <in_pcbnotify+0x50>
+          inp->inp_socket == 0) 
+ 8030934:	e0bfff17 	ldw	r2,-4(fp)
+ 8030938:	10800817 	ldw	r2,32(r2)
+      if (inp->inp_faddr.s_addr != dst->s_addr ||
+ 803093c:	1000041e 	bne	r2,zero,8030950 <in_pcbnotify+0x60>
+      {
+         inp = inp->inp_next;
+ 8030940:	e0bfff17 	ldw	r2,-4(fp)
+ 8030944:	10800017 	ldw	r2,0(r2)
+ 8030948:	e0bfff15 	stw	r2,-4(fp)
+         continue;
+ 803094c:	00001006 	br	8030990 <in_pcbnotify+0xa0>
+      }
+      if (errnum) 
+ 8030950:	e0bffb17 	ldw	r2,-20(fp)
+ 8030954:	10000426 	beq	r2,zero,8030968 <in_pcbnotify+0x78>
+         inp->inp_socket->so_error = errnum;
+ 8030958:	e0bfff17 	ldw	r2,-4(fp)
+ 803095c:	10800817 	ldw	r2,32(r2)
+ 8030960:	e0fffb17 	ldw	r3,-20(fp)
+ 8030964:	10c00615 	stw	r3,24(r2)
+      oinp = inp;
+ 8030968:	e0bfff17 	ldw	r2,-4(fp)
+ 803096c:	e0bffe15 	stw	r2,-8(fp)
+      inp = inp->inp_next;
+ 8030970:	e0bfff17 	ldw	r2,-4(fp)
+ 8030974:	10800017 	ldw	r2,0(r2)
+ 8030978:	e0bfff15 	stw	r2,-4(fp)
+      if (notify)
+ 803097c:	e0bffa17 	ldw	r2,-24(fp)
+ 8030980:	10000326 	beq	r2,zero,8030990 <in_pcbnotify+0xa0>
+         (*notify)(oinp);
+ 8030984:	e0bffa17 	ldw	r2,-24(fp)
+ 8030988:	e13ffe17 	ldw	r4,-8(fp)
+ 803098c:	103ee83a 	callr	r2
+   for (inp = head->inp_next; inp != head;) 
+ 8030990:	e0ffff17 	ldw	r3,-4(fp)
+ 8030994:	e0bffd17 	ldw	r2,-12(fp)
+ 8030998:	18bfe11e 	bne	r3,r2,8030920 <in_pcbnotify+0x30>
+   }
+}
+ 803099c:	0001883a 	nop
+ 80309a0:	e037883a 	mov	sp,fp
+ 80309a4:	dfc00117 	ldw	ra,4(sp)
+ 80309a8:	df000017 	ldw	fp,0(sp)
+ 80309ac:	dec00204 	addi	sp,sp,8
+ 80309b0:	f800283a 	ret
+
+080309b4 <tcp_notify>:
+ * RETURNS: 
+ */
+
+void
+tcp_notify(struct inpcb * inp)
+{
+ 80309b4:	defffd04 	addi	sp,sp,-12
+ 80309b8:	dfc00215 	stw	ra,8(sp)
+ 80309bc:	df000115 	stw	fp,4(sp)
+ 80309c0:	df000104 	addi	fp,sp,4
+ 80309c4:	e13fff15 	stw	r4,-4(fp)
+   tcp_wakeup(&inp->inp_socket->so_timeo);
+ 80309c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80309cc:	10800817 	ldw	r2,32(r2)
+ 80309d0:	10800904 	addi	r2,r2,36
+ 80309d4:	1009883a 	mov	r4,r2
+ 80309d8:	8027ba00 	call	8027ba0 <tcp_wakeup>
+   sorwakeup(inp->inp_socket);
+ 80309dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80309e0:	10c00817 	ldw	r3,32(r2)
+ 80309e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80309e8:	10800817 	ldw	r2,32(r2)
+ 80309ec:	10800a04 	addi	r2,r2,40
+ 80309f0:	100b883a 	mov	r5,r2
+ 80309f4:	1809883a 	mov	r4,r3
+ 80309f8:	802f94c0 	call	802f94c <sbwakeup>
+   sowwakeup(inp->inp_socket);
+ 80309fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030a00:	10c00817 	ldw	r3,32(r2)
+ 8030a04:	e0bfff17 	ldw	r2,-4(fp)
+ 8030a08:	10800817 	ldw	r2,32(r2)
+ 8030a0c:	10801204 	addi	r2,r2,72
+ 8030a10:	100b883a 	mov	r5,r2
+ 8030a14:	1809883a 	mov	r4,r3
+ 8030a18:	802f94c0 	call	802f94c <sbwakeup>
+}
+ 8030a1c:	0001883a 	nop
+ 8030a20:	e037883a 	mov	sp,fp
+ 8030a24:	dfc00117 	ldw	ra,4(sp)
+ 8030a28:	df000017 	ldw	fp,0(sp)
+ 8030a2c:	dec00204 	addi	sp,sp,8
+ 8030a30:	f800283a 	ret
+
+08030a34 <ifd_clr>:
+ * compacts the fd_set.
+ */
+
+void
+ifd_clr(long sock, fd_set *set)
+{
+ 8030a34:	defffb04 	addi	sp,sp,-20
+ 8030a38:	dfc00415 	stw	ra,16(sp)
+ 8030a3c:	df000315 	stw	fp,12(sp)
+ 8030a40:	df000304 	addi	fp,sp,12
+ 8030a44:	e13ffe15 	stw	r4,-8(fp)
+ 8030a48:	e17ffd15 	stw	r5,-12(fp)
+   u_int i;
+
+   for (i = 0; i < set->fd_count ; i++) 
+ 8030a4c:	e03fff15 	stw	zero,-4(fp)
+ 8030a50:	00002706 	br	8030af0 <ifd_clr+0xbc>
+   {
+      if (set->fd_array[i] == sock)
+ 8030a54:	e0fffd17 	ldw	r3,-12(fp)
+ 8030a58:	e0bfff17 	ldw	r2,-4(fp)
+ 8030a5c:	10800044 	addi	r2,r2,1
+ 8030a60:	100490ba 	slli	r2,r2,2
+ 8030a64:	1885883a 	add	r2,r3,r2
+ 8030a68:	10800017 	ldw	r2,0(r2)
+ 8030a6c:	e0fffe17 	ldw	r3,-8(fp)
+ 8030a70:	18801c1e 	bne	r3,r2,8030ae4 <ifd_clr+0xb0>
+      {
+         while (i + 1 < set->fd_count)
+ 8030a74:	00001006 	br	8030ab8 <ifd_clr+0x84>
+         {
+            set->fd_array[i] = set->fd_array[i + 1];
+ 8030a78:	e0bfff17 	ldw	r2,-4(fp)
+ 8030a7c:	10800044 	addi	r2,r2,1
+ 8030a80:	e0fffd17 	ldw	r3,-12(fp)
+ 8030a84:	10800044 	addi	r2,r2,1
+ 8030a88:	100490ba 	slli	r2,r2,2
+ 8030a8c:	1885883a 	add	r2,r3,r2
+ 8030a90:	10c00017 	ldw	r3,0(r2)
+ 8030a94:	e13ffd17 	ldw	r4,-12(fp)
+ 8030a98:	e0bfff17 	ldw	r2,-4(fp)
+ 8030a9c:	10800044 	addi	r2,r2,1
+ 8030aa0:	100490ba 	slli	r2,r2,2
+ 8030aa4:	2085883a 	add	r2,r4,r2
+ 8030aa8:	10c00015 	stw	r3,0(r2)
+            i++;
+ 8030aac:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ab0:	10800044 	addi	r2,r2,1
+ 8030ab4:	e0bfff15 	stw	r2,-4(fp)
+         while (i + 1 < set->fd_count)
+ 8030ab8:	e0bfff17 	ldw	r2,-4(fp)
+ 8030abc:	10c00044 	addi	r3,r2,1
+ 8030ac0:	e0bffd17 	ldw	r2,-12(fp)
+ 8030ac4:	10800017 	ldw	r2,0(r2)
+ 8030ac8:	18bfeb36 	bltu	r3,r2,8030a78 <ifd_clr+0x44>
+         }
+         set->fd_count--;
+ 8030acc:	e0bffd17 	ldw	r2,-12(fp)
+ 8030ad0:	10800017 	ldw	r2,0(r2)
+ 8030ad4:	10ffffc4 	addi	r3,r2,-1
+ 8030ad8:	e0bffd17 	ldw	r2,-12(fp)
+ 8030adc:	10c00015 	stw	r3,0(r2)
+         return;
+ 8030ae0:	00000806 	br	8030b04 <ifd_clr+0xd0>
+   for (i = 0; i < set->fd_count ; i++) 
+ 8030ae4:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ae8:	10800044 	addi	r2,r2,1
+ 8030aec:	e0bfff15 	stw	r2,-4(fp)
+ 8030af0:	e0bffd17 	ldw	r2,-12(fp)
+ 8030af4:	10800017 	ldw	r2,0(r2)
+ 8030af8:	e0ffff17 	ldw	r3,-4(fp)
+ 8030afc:	18bfd536 	bltu	r3,r2,8030a54 <ifd_clr+0x20>
+      }
+   }
+
+#ifdef NPDEBUG
+   dtrap(); /* socket wasn't found in array */
+ 8030b00:	8028cd40 	call	8028cd4 <dtrap>
+#endif
+}
+ 8030b04:	e037883a 	mov	sp,fp
+ 8030b08:	dfc00117 	ldw	ra,4(sp)
+ 8030b0c:	df000017 	ldw	fp,0(sp)
+ 8030b10:	dec00204 	addi	sp,sp,8
+ 8030b14:	f800283a 	ret
+
+08030b18 <ifd_set>:
+ * called if the fd_set structure is already full.
+ */
+
+void
+ifd_set(long sock, fd_set *set)
+{
+ 8030b18:	defffc04 	addi	sp,sp,-16
+ 8030b1c:	dfc00315 	stw	ra,12(sp)
+ 8030b20:	df000215 	stw	fp,8(sp)
+ 8030b24:	df000204 	addi	fp,sp,8
+ 8030b28:	e13fff15 	stw	r4,-4(fp)
+ 8030b2c:	e17ffe15 	stw	r5,-8(fp)
+   if (set->fd_count < FD_SETSIZE)
+ 8030b30:	e0bffe17 	ldw	r2,-8(fp)
+ 8030b34:	10800017 	ldw	r2,0(r2)
+ 8030b38:	10801028 	cmpgeui	r2,r2,64
+ 8030b3c:	10000c1e 	bne	r2,zero,8030b70 <ifd_set+0x58>
+      set->fd_array[set->fd_count++] = sock;
+ 8030b40:	e0bffe17 	ldw	r2,-8(fp)
+ 8030b44:	10800017 	ldw	r2,0(r2)
+ 8030b48:	11000044 	addi	r4,r2,1
+ 8030b4c:	e0fffe17 	ldw	r3,-8(fp)
+ 8030b50:	19000015 	stw	r4,0(r3)
+ 8030b54:	e0fffe17 	ldw	r3,-8(fp)
+ 8030b58:	10800044 	addi	r2,r2,1
+ 8030b5c:	100490ba 	slli	r2,r2,2
+ 8030b60:	1885883a 	add	r2,r3,r2
+ 8030b64:	e0ffff17 	ldw	r3,-4(fp)
+ 8030b68:	10c00015 	stw	r3,0(r2)
+#ifdef NPDEBUG
+   else
+      dtrap();
+#endif
+}
+ 8030b6c:	00000106 	br	8030b74 <ifd_set+0x5c>
+      dtrap();
+ 8030b70:	8028cd40 	call	8028cd4 <dtrap>
+}
+ 8030b74:	0001883a 	nop
+ 8030b78:	e037883a 	mov	sp,fp
+ 8030b7c:	dfc00117 	ldw	ra,4(sp)
+ 8030b80:	df000017 	ldw	fp,0(sp)
+ 8030b84:	dec00204 	addi	sp,sp,8
+ 8030b88:	f800283a 	ret
+
+08030b8c <ifd_isset>:
+ * Tests if a socket is a member of a file descriptor set.
+ */
+
+int   /* actually, boolean */
+ifd_isset(long sock, fd_set *set)
+{
+ 8030b8c:	defffc04 	addi	sp,sp,-16
+ 8030b90:	df000315 	stw	fp,12(sp)
+ 8030b94:	df000304 	addi	fp,sp,12
+ 8030b98:	e13ffe15 	stw	r4,-8(fp)
+ 8030b9c:	e17ffd15 	stw	r5,-12(fp)
+   u_int   i;
+
+   for (i = 0; i < set->fd_count ; i++)
+ 8030ba0:	e03fff15 	stw	zero,-4(fp)
+ 8030ba4:	00000d06 	br	8030bdc <ifd_isset+0x50>
+   {
+      if (set->fd_array[i] == sock)
+ 8030ba8:	e0fffd17 	ldw	r3,-12(fp)
+ 8030bac:	e0bfff17 	ldw	r2,-4(fp)
+ 8030bb0:	10800044 	addi	r2,r2,1
+ 8030bb4:	100490ba 	slli	r2,r2,2
+ 8030bb8:	1885883a 	add	r2,r3,r2
+ 8030bbc:	10800017 	ldw	r2,0(r2)
+ 8030bc0:	e0fffe17 	ldw	r3,-8(fp)
+ 8030bc4:	1880021e 	bne	r3,r2,8030bd0 <ifd_isset+0x44>
+         return TRUE;
+ 8030bc8:	00800044 	movi	r2,1
+ 8030bcc:	00000806 	br	8030bf0 <ifd_isset+0x64>
+   for (i = 0; i < set->fd_count ; i++)
+ 8030bd0:	e0bfff17 	ldw	r2,-4(fp)
+ 8030bd4:	10800044 	addi	r2,r2,1
+ 8030bd8:	e0bfff15 	stw	r2,-4(fp)
+ 8030bdc:	e0bffd17 	ldw	r2,-12(fp)
+ 8030be0:	10800017 	ldw	r2,0(r2)
+ 8030be4:	e0ffff17 	ldw	r3,-4(fp)
+ 8030be8:	18bfef36 	bltu	r3,r2,8030ba8 <ifd_isset+0x1c>
+   }
+   return FALSE;
+ 8030bec:	0005883a 	mov	r2,zero
+}
+ 8030bf0:	e037883a 	mov	sp,fp
+ 8030bf4:	df000017 	ldw	fp,0(sp)
+ 8030bf8:	dec00104 	addi	sp,sp,4
+ 8030bfc:	f800283a 	ret
+
+08030c00 <ifd_get>:
+ * NOTE: This is not part of the original FD_XXX() functionality.
+ */
+
+long
+ifd_get(unsigned i, fd_set *set)
+{
+ 8030c00:	defffc04 	addi	sp,sp,-16
+ 8030c04:	dfc00315 	stw	ra,12(sp)
+ 8030c08:	df000215 	stw	fp,8(sp)
+ 8030c0c:	df000204 	addi	fp,sp,8
+ 8030c10:	e13fff15 	stw	r4,-4(fp)
+ 8030c14:	e17ffe15 	stw	r5,-8(fp)
+   if (i < set->fd_count)
+ 8030c18:	e0bffe17 	ldw	r2,-8(fp)
+ 8030c1c:	10800017 	ldw	r2,0(r2)
+ 8030c20:	e0ffff17 	ldw	r3,-4(fp)
+ 8030c24:	1880072e 	bgeu	r3,r2,8030c44 <ifd_get+0x44>
+      return set->fd_array[i];
+ 8030c28:	e0fffe17 	ldw	r3,-8(fp)
+ 8030c2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030c30:	10800044 	addi	r2,r2,1
+ 8030c34:	100490ba 	slli	r2,r2,2
+ 8030c38:	1885883a 	add	r2,r3,r2
+ 8030c3c:	10800017 	ldw	r2,0(r2)
+ 8030c40:	00000206 	br	8030c4c <ifd_get+0x4c>
+   else
+   {
+#ifdef NPDEBUG
+      dtrap();
+ 8030c44:	8028cd40 	call	8028cd4 <dtrap>
+#endif
+      return INVALID_SOCKET;
+ 8030c48:	00bfffc4 	movi	r2,-1
+   }
+}
+ 8030c4c:	e037883a 	mov	sp,fp
+ 8030c50:	dfc00117 	ldw	ra,4(sp)
+ 8030c54:	df000017 	ldw	fp,0(sp)
+ 8030c58:	dec00204 	addi	sp,sp,8
+ 8030c5c:	f800283a 	ret
+
+08030c60 <tcp_reass>:
+
+int
+tcp_reass(struct tcpcb * tp, 
+   struct tcpiphdr * ti,
+   struct mbuf *  ti_mbuf)
+{
+ 8030c60:	defff504 	addi	sp,sp,-44
+ 8030c64:	dfc00a15 	stw	ra,40(sp)
+ 8030c68:	df000915 	stw	fp,36(sp)
+ 8030c6c:	df000904 	addi	fp,sp,36
+ 8030c70:	e13ff915 	stw	r4,-28(fp)
+ 8030c74:	e17ff815 	stw	r5,-32(fp)
+ 8030c78:	e1bff715 	stw	r6,-36(fp)
+   struct tcpiphdr * q;
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+ 8030c7c:	e0bff917 	ldw	r2,-28(fp)
+ 8030c80:	10800d17 	ldw	r2,52(r2)
+ 8030c84:	10800817 	ldw	r2,32(r2)
+ 8030c88:	e0bffe15 	stw	r2,-8(fp)
+
+   /*
+    * Call with ti==0 after become established to
+    * force pre-ESTABLISHED data up to user socket.
+    */
+   if (ti == 0)
+ 8030c8c:	e0bff817 	ldw	r2,-32(fp)
+ 8030c90:	10009c26 	beq	r2,zero,8030f04 <tcp_reass+0x2a4>
+      goto present;
+
+   /*
+    * Find a segment which begins after this one does.
+    */
+   for (q = tp->seg_next; q != (struct tcpiphdr *)tp;
+ 8030c94:	e0bff917 	ldw	r2,-28(fp)
+ 8030c98:	10800017 	ldw	r2,0(r2)
+ 8030c9c:	e0bfff15 	stw	r2,-4(fp)
+ 8030ca0:	00000906 	br	8030cc8 <tcp_reass+0x68>
+       q = (struct tcpiphdr *)q->ti_next)
+   {
+      if (SEQ_GT(q->ti_seq, ti->ti_seq))
+ 8030ca4:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ca8:	10c00617 	ldw	r3,24(r2)
+ 8030cac:	e0bff817 	ldw	r2,-32(fp)
+ 8030cb0:	10800617 	ldw	r2,24(r2)
+ 8030cb4:	1885c83a 	sub	r2,r3,r2
+ 8030cb8:	00800716 	blt	zero,r2,8030cd8 <tcp_reass+0x78>
+       q = (struct tcpiphdr *)q->ti_next)
+ 8030cbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030cc0:	10800017 	ldw	r2,0(r2)
+ 8030cc4:	e0bfff15 	stw	r2,-4(fp)
+   for (q = tp->seg_next; q != (struct tcpiphdr *)tp;
+ 8030cc8:	e0ffff17 	ldw	r3,-4(fp)
+ 8030ccc:	e0bff917 	ldw	r2,-28(fp)
+ 8030cd0:	18bff41e 	bne	r3,r2,8030ca4 <tcp_reass+0x44>
+ 8030cd4:	00000106 	br	8030cdc <tcp_reass+0x7c>
+      break;
+ 8030cd8:	0001883a 	nop
+   /*
+    * If there is a preceding segment, it may provide some of
+    * our data already.  If so, drop the data from the incoming
+    * segment.  If it provides all of our data, drop us.
+    */
+   if ((struct tcpiphdr *)q->ti_prev != (struct tcpiphdr *)tp) 
+ 8030cdc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ce0:	10800117 	ldw	r2,4(r2)
+ 8030ce4:	e0fff917 	ldw	r3,-28(fp)
+ 8030ce8:	18803b26 	beq	r3,r2,8030dd8 <tcp_reass+0x178>
+   {
+      long  i;
+      q = (struct tcpiphdr *)q->ti_prev;
+ 8030cec:	e0bfff17 	ldw	r2,-4(fp)
+ 8030cf0:	10800117 	ldw	r2,4(r2)
+ 8030cf4:	e0bfff15 	stw	r2,-4(fp)
+      /* conversion to int (in i) handles seq wraparound */
+      i = q->ti_seq + q->ti_len - ti->ti_seq;
+ 8030cf8:	e0bfff17 	ldw	r2,-4(fp)
+ 8030cfc:	10c00617 	ldw	r3,24(r2)
+ 8030d00:	e0bfff17 	ldw	r2,-4(fp)
+ 8030d04:	1080028b 	ldhu	r2,10(r2)
+ 8030d08:	10bfffcc 	andi	r2,r2,65535
+ 8030d0c:	1887883a 	add	r3,r3,r2
+ 8030d10:	e0bff817 	ldw	r2,-32(fp)
+ 8030d14:	10800617 	ldw	r2,24(r2)
+ 8030d18:	1885c83a 	sub	r2,r3,r2
+ 8030d1c:	e0bffd15 	stw	r2,-12(fp)
+      if (i > 0) 
+ 8030d20:	e0bffd17 	ldw	r2,-12(fp)
+ 8030d24:	0080290e 	bge	zero,r2,8030dcc <tcp_reass+0x16c>
+      {
+         if (i >= (long)ti->ti_len) 
+ 8030d28:	e0bff817 	ldw	r2,-32(fp)
+ 8030d2c:	1080028b 	ldhu	r2,10(r2)
+ 8030d30:	10bfffcc 	andi	r2,r2,65535
+ 8030d34:	e0fffd17 	ldw	r3,-12(fp)
+ 8030d38:	18801416 	blt	r3,r2,8030d8c <tcp_reass+0x12c>
+         {
+            tcpstat.tcps_rcvduppack++;
+ 8030d3c:	008201b4 	movhi	r2,2054
+ 8030d40:	10b8c317 	ldw	r2,-7412(r2)
+ 8030d44:	10c00044 	addi	r3,r2,1
+ 8030d48:	008201b4 	movhi	r2,2054
+ 8030d4c:	10f8c315 	stw	r3,-7412(r2)
+            tcpstat.tcps_rcvdupbyte += ti->ti_len;
+ 8030d50:	008201b4 	movhi	r2,2054
+ 8030d54:	10f8c417 	ldw	r3,-7408(r2)
+ 8030d58:	e0bff817 	ldw	r2,-32(fp)
+ 8030d5c:	1080028b 	ldhu	r2,10(r2)
+ 8030d60:	10bfffcc 	andi	r2,r2,65535
+ 8030d64:	1887883a 	add	r3,r3,r2
+ 8030d68:	008201b4 	movhi	r2,2054
+ 8030d6c:	10f8c415 	stw	r3,-7408(r2)
+            GOTO_DROP;
+ 8030d70:	008025c4 	movi	r2,151
+ 8030d74:	d0a08715 	stw	r2,-32228(gp)
+ 8030d78:	0001883a 	nop
+   } while (ti != (struct tcpiphdr *)tp && ti->ti_seq == tp->rcv_nxt);
+      sorwakeup(so);
+   return (flags);
+drop:
+   /**m_freem (dtom(ti));**/
+   m_freem (ti_mbuf);
+ 8030d7c:	e13ff717 	ldw	r4,-36(fp)
+ 8030d80:	8029cfc0 	call	8029cfc <m_freem>
+   return (0);
+ 8030d84:	0005883a 	mov	r2,zero
+ 8030d88:	0000ac06 	br	803103c <tcp_reass+0x3dc>
+         m_adj (ti_mbuf, (int)i);
+ 8030d8c:	e17ffd17 	ldw	r5,-12(fp)
+ 8030d90:	e13ff717 	ldw	r4,-36(fp)
+ 8030d94:	802a0180 	call	802a018 <m_adj>
+         ti->ti_len -= (short)i;
+ 8030d98:	e0bff817 	ldw	r2,-32(fp)
+ 8030d9c:	1080028b 	ldhu	r2,10(r2)
+ 8030da0:	e0fffd17 	ldw	r3,-12(fp)
+ 8030da4:	10c5c83a 	sub	r2,r2,r3
+ 8030da8:	1007883a 	mov	r3,r2
+ 8030dac:	e0bff817 	ldw	r2,-32(fp)
+ 8030db0:	10c0028d 	sth	r3,10(r2)
+         ti->ti_seq += (tcp_seq)i;
+ 8030db4:	e0bff817 	ldw	r2,-32(fp)
+ 8030db8:	10c00617 	ldw	r3,24(r2)
+ 8030dbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8030dc0:	1887883a 	add	r3,r3,r2
+ 8030dc4:	e0bff817 	ldw	r2,-32(fp)
+ 8030dc8:	10c00615 	stw	r3,24(r2)
+      q = (struct tcpiphdr *)(q->ti_next);
+ 8030dcc:	e0bfff17 	ldw	r2,-4(fp)
+ 8030dd0:	10800017 	ldw	r2,0(r2)
+ 8030dd4:	e0bfff15 	stw	r2,-4(fp)
+   tcpstat.tcps_rcvoopack++;
+ 8030dd8:	008201b4 	movhi	r2,2054
+ 8030ddc:	10b8c717 	ldw	r2,-7396(r2)
+ 8030de0:	10c00044 	addi	r3,r2,1
+ 8030de4:	008201b4 	movhi	r2,2054
+ 8030de8:	10f8c715 	stw	r3,-7396(r2)
+   tcpstat.tcps_rcvoobyte += ti->ti_len;
+ 8030dec:	008201b4 	movhi	r2,2054
+ 8030df0:	10f8c817 	ldw	r3,-7392(r2)
+ 8030df4:	e0bff817 	ldw	r2,-32(fp)
+ 8030df8:	1080028b 	ldhu	r2,10(r2)
+ 8030dfc:	10bfffcc 	andi	r2,r2,65535
+ 8030e00:	1887883a 	add	r3,r3,r2
+ 8030e04:	008201b4 	movhi	r2,2054
+ 8030e08:	10f8c815 	stw	r3,-7392(r2)
+   while (q != (struct tcpiphdr *)tp) 
+ 8030e0c:	00003206 	br	8030ed8 <tcp_reass+0x278>
+      int   i  =  (int)((ti->ti_seq +  ti->ti_len) -  q->ti_seq);
+ 8030e10:	e0bff817 	ldw	r2,-32(fp)
+ 8030e14:	10c00617 	ldw	r3,24(r2)
+ 8030e18:	e0bff817 	ldw	r2,-32(fp)
+ 8030e1c:	1080028b 	ldhu	r2,10(r2)
+ 8030e20:	10bfffcc 	andi	r2,r2,65535
+ 8030e24:	1887883a 	add	r3,r3,r2
+ 8030e28:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e2c:	10800617 	ldw	r2,24(r2)
+ 8030e30:	1885c83a 	sub	r2,r3,r2
+ 8030e34:	e0bffc15 	stw	r2,-16(fp)
+      if (i <= 0)
+ 8030e38:	e0bffc17 	ldw	r2,-16(fp)
+ 8030e3c:	00802a0e 	bge	zero,r2,8030ee8 <tcp_reass+0x288>
+      if (i < (int)(q->ti_len))
+ 8030e40:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e44:	1080028b 	ldhu	r2,10(r2)
+ 8030e48:	10bfffcc 	andi	r2,r2,65535
+ 8030e4c:	e0fffc17 	ldw	r3,-16(fp)
+ 8030e50:	1880130e 	bge	r3,r2,8030ea0 <tcp_reass+0x240>
+         q->ti_seq += i;
+ 8030e54:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e58:	10c00617 	ldw	r3,24(r2)
+ 8030e5c:	e0bffc17 	ldw	r2,-16(fp)
+ 8030e60:	1887883a 	add	r3,r3,r2
+ 8030e64:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e68:	10c00615 	stw	r3,24(r2)
+         q->ti_len -= (u_short)i;
+ 8030e6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e70:	1080028b 	ldhu	r2,10(r2)
+ 8030e74:	e0fffc17 	ldw	r3,-16(fp)
+ 8030e78:	10c5c83a 	sub	r2,r2,r3
+ 8030e7c:	1007883a 	mov	r3,r2
+ 8030e80:	e0bfff17 	ldw	r2,-4(fp)
+ 8030e84:	10c0028d 	sth	r3,10(r2)
+         m_adj (dtom(q), (int)i);
+ 8030e88:	e13fff17 	ldw	r4,-4(fp)
+ 8030e8c:	802a22c0 	call	802a22c <dtom>
+ 8030e90:	e17ffc17 	ldw	r5,-16(fp)
+ 8030e94:	1009883a 	mov	r4,r2
+ 8030e98:	802a0180 	call	802a018 <m_adj>
+         break;
+ 8030e9c:	00001306 	br	8030eec <tcp_reass+0x28c>
+      q = (struct tcpiphdr *)q->ti_next;
+ 8030ea0:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ea4:	10800017 	ldw	r2,0(r2)
+ 8030ea8:	e0bfff15 	stw	r2,-4(fp)
+      m = dtom(q->ti_prev);
+ 8030eac:	e0bfff17 	ldw	r2,-4(fp)
+ 8030eb0:	10800117 	ldw	r2,4(r2)
+ 8030eb4:	1009883a 	mov	r4,r2
+ 8030eb8:	802a22c0 	call	802a22c <dtom>
+ 8030ebc:	e0bffb15 	stw	r2,-20(fp)
+      remque (q->ti_prev);
+ 8030ec0:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ec4:	10800117 	ldw	r2,4(r2)
+ 8030ec8:	1009883a 	mov	r4,r2
+ 8030ecc:	802a2c40 	call	802a2c4 <remque>
+      m_freem (m);
+ 8030ed0:	e13ffb17 	ldw	r4,-20(fp)
+ 8030ed4:	8029cfc0 	call	8029cfc <m_freem>
+   while (q != (struct tcpiphdr *)tp) 
+ 8030ed8:	e0ffff17 	ldw	r3,-4(fp)
+ 8030edc:	e0bff917 	ldw	r2,-28(fp)
+ 8030ee0:	18bfcb1e 	bne	r3,r2,8030e10 <tcp_reass+0x1b0>
+ 8030ee4:	00000106 	br	8030eec <tcp_reass+0x28c>
+         break;
+ 8030ee8:	0001883a 	nop
+   insque(ti, q->ti_prev);
+ 8030eec:	e0bfff17 	ldw	r2,-4(fp)
+ 8030ef0:	10800117 	ldw	r2,4(r2)
+ 8030ef4:	100b883a 	mov	r5,r2
+ 8030ef8:	e13ff817 	ldw	r4,-32(fp)
+ 8030efc:	802a3340 	call	802a334 <insque>
+ 8030f00:	00000106 	br	8030f08 <tcp_reass+0x2a8>
+      goto present;
+ 8030f04:	0001883a 	nop
+   if (TCPS_HAVERCVDSYN (tp->t_state) == 0)
+ 8030f08:	e0bff917 	ldw	r2,-28(fp)
+ 8030f0c:	10800217 	ldw	r2,8(r2)
+ 8030f10:	108000c8 	cmpgei	r2,r2,3
+ 8030f14:	1000021e 	bne	r2,zero,8030f20 <tcp_reass+0x2c0>
+      return (0);
+ 8030f18:	0005883a 	mov	r2,zero
+ 8030f1c:	00004706 	br	803103c <tcp_reass+0x3dc>
+   ti = tp->seg_next;
+ 8030f20:	e0bff917 	ldw	r2,-28(fp)
+ 8030f24:	10800017 	ldw	r2,0(r2)
+ 8030f28:	e0bff815 	stw	r2,-32(fp)
+   if (ti == (struct tcpiphdr *)tp || ti->ti_seq != tp->rcv_nxt)
+ 8030f2c:	e0fff817 	ldw	r3,-32(fp)
+ 8030f30:	e0bff917 	ldw	r2,-28(fp)
+ 8030f34:	18800526 	beq	r3,r2,8030f4c <tcp_reass+0x2ec>
+ 8030f38:	e0bff817 	ldw	r2,-32(fp)
+ 8030f3c:	10c00617 	ldw	r3,24(r2)
+ 8030f40:	e0bff917 	ldw	r2,-28(fp)
+ 8030f44:	10801617 	ldw	r2,88(r2)
+ 8030f48:	18800226 	beq	r3,r2,8030f54 <tcp_reass+0x2f4>
+      return (0);
+ 8030f4c:	0005883a 	mov	r2,zero
+ 8030f50:	00003a06 	br	803103c <tcp_reass+0x3dc>
+   if (tp->t_state == TCPS_SYN_RECEIVED && ti->ti_len)
+ 8030f54:	e0bff917 	ldw	r2,-28(fp)
+ 8030f58:	10800217 	ldw	r2,8(r2)
+ 8030f5c:	108000d8 	cmpnei	r2,r2,3
+ 8030f60:	1000061e 	bne	r2,zero,8030f7c <tcp_reass+0x31c>
+ 8030f64:	e0bff817 	ldw	r2,-32(fp)
+ 8030f68:	1080028b 	ldhu	r2,10(r2)
+ 8030f6c:	10bfffcc 	andi	r2,r2,65535
+ 8030f70:	10000226 	beq	r2,zero,8030f7c <tcp_reass+0x31c>
+      return (0);
+ 8030f74:	0005883a 	mov	r2,zero
+ 8030f78:	00003006 	br	803103c <tcp_reass+0x3dc>
+      tp->rcv_nxt += ti->ti_len;
+ 8030f7c:	e0bff917 	ldw	r2,-28(fp)
+ 8030f80:	10c01617 	ldw	r3,88(r2)
+ 8030f84:	e0bff817 	ldw	r2,-32(fp)
+ 8030f88:	1080028b 	ldhu	r2,10(r2)
+ 8030f8c:	10bfffcc 	andi	r2,r2,65535
+ 8030f90:	1887883a 	add	r3,r3,r2
+ 8030f94:	e0bff917 	ldw	r2,-28(fp)
+ 8030f98:	10c01615 	stw	r3,88(r2)
+      flags = ti->ti_flags & TH_FIN;
+ 8030f9c:	e0bff817 	ldw	r2,-32(fp)
+ 8030fa0:	10800843 	ldbu	r2,33(r2)
+ 8030fa4:	10803fcc 	andi	r2,r2,255
+ 8030fa8:	1080004c 	andi	r2,r2,1
+ 8030fac:	e0bffa15 	stw	r2,-24(fp)
+      remque(ti);
+ 8030fb0:	e13ff817 	ldw	r4,-32(fp)
+ 8030fb4:	802a2c40 	call	802a2c4 <remque>
+      m = dtom(ti);
+ 8030fb8:	e13ff817 	ldw	r4,-32(fp)
+ 8030fbc:	802a22c0 	call	802a22c <dtom>
+ 8030fc0:	e0bffb15 	stw	r2,-20(fp)
+      ti = (struct tcpiphdr *)ti->ti_next;
+ 8030fc4:	e0bff817 	ldw	r2,-32(fp)
+ 8030fc8:	10800017 	ldw	r2,0(r2)
+ 8030fcc:	e0bff815 	stw	r2,-32(fp)
+      if (so->so_state & SS_CANTRCVMORE)
+ 8030fd0:	e0bffe17 	ldw	r2,-8(fp)
+ 8030fd4:	1080088b 	ldhu	r2,34(r2)
+ 8030fd8:	10bfffcc 	andi	r2,r2,65535
+ 8030fdc:	1080080c 	andi	r2,r2,32
+ 8030fe0:	10000326 	beq	r2,zero,8030ff0 <tcp_reass+0x390>
+         m_freem (m);
+ 8030fe4:	e13ffb17 	ldw	r4,-20(fp)
+ 8030fe8:	8029cfc0 	call	8029cfc <m_freem>
+ 8030fec:	00000506 	br	8031004 <tcp_reass+0x3a4>
+         sbappend (&so->so_rcv, m);
+ 8030ff0:	e0bffe17 	ldw	r2,-8(fp)
+ 8030ff4:	10800a04 	addi	r2,r2,40
+ 8030ff8:	e17ffb17 	ldw	r5,-20(fp)
+ 8030ffc:	1009883a 	mov	r4,r2
+ 8031000:	802fafc0 	call	802fafc <sbappend>
+   } while (ti != (struct tcpiphdr *)tp && ti->ti_seq == tp->rcv_nxt);
+ 8031004:	e0fff817 	ldw	r3,-32(fp)
+ 8031008:	e0bff917 	ldw	r2,-28(fp)
+ 803100c:	18800526 	beq	r3,r2,8031024 <tcp_reass+0x3c4>
+ 8031010:	e0bff817 	ldw	r2,-32(fp)
+ 8031014:	10c00617 	ldw	r3,24(r2)
+ 8031018:	e0bff917 	ldw	r2,-28(fp)
+ 803101c:	10801617 	ldw	r2,88(r2)
+ 8031020:	18bfd626 	beq	r3,r2,8030f7c <tcp_reass+0x31c>
+      sorwakeup(so);
+ 8031024:	e0bffe17 	ldw	r2,-8(fp)
+ 8031028:	10800a04 	addi	r2,r2,40
+ 803102c:	100b883a 	mov	r5,r2
+ 8031030:	e13ffe17 	ldw	r4,-8(fp)
+ 8031034:	802f94c0 	call	802f94c <sbwakeup>
+   return (flags);
+ 8031038:	e0bffa17 	ldw	r2,-24(fp)
+}
+ 803103c:	e037883a 	mov	sp,fp
+ 8031040:	dfc00117 	ldw	ra,4(sp)
+ 8031044:	df000017 	ldw	fp,0(sp)
+ 8031048:	dec00204 	addi	sp,sp,8
+ 803104c:	f800283a 	ret
+
+08031050 <tcp_input>:
+ * RETURNS: void
+ */
+
+void
+tcp_input(struct mbuf * m, NET ifp)
+{
+ 8031050:	deffdf04 	addi	sp,sp,-132
+ 8031054:	dfc02015 	stw	ra,128(sp)
+ 8031058:	df001f15 	stw	fp,124(sp)
+ 803105c:	df001f04 	addi	fp,sp,124
+ 8031060:	e13fe415 	stw	r4,-112(fp)
+ 8031064:	e17fe315 	stw	r5,-116(fp)
+   ip6_addr    ip6_src;
+   ip6_addr    ip6_dst;
+#endif   /* IP_V6 */
+   struct tcpiphdr * ti;
+   struct inpcb * inp;
+   struct mbuf *  om =  0;
+ 8031068:	e03ffd15 	stw	zero,-12(fp)
+   int   len,  tlen, off;
+   struct tcpcb * tp =  0;
+ 803106c:	e03ffc15 	stw	zero,-16(fp)
+   int   tiflags;
+   struct socket *   so =  NULL;
+ 8031070:	e03ffa15 	stw	zero,-24(fp)
+   int   todrop,  acked,   ourfinisacked, needoutput  =  0;
+ 8031074:	e03ff715 	stw	zero,-36(fp)
+   int   dropsocket  =  0;
+ 8031078:	e03ff615 	stw	zero,-40(fp)
+   long  iss   =  0;
+ 803107c:	e03ff515 	stw	zero,-44(fp)
+#ifdef DO_TCPTRACE
+   int   ostate;
+#endif
+
+
+   tcpstat.tcps_rcvtotal++;
+ 8031080:	008201b4 	movhi	r2,2054
+ 8031084:	10b8bd17 	ldw	r2,-7436(r2)
+ 8031088:	10c00044 	addi	r3,r2,1
+ 803108c:	008201b4 	movhi	r2,2054
+ 8031090:	10f8bd15 	stw	r3,-7436(r2)
+   TCP_MIB_INC(tcpInSegs);    /* keep MIB stats */
+ 8031094:	008201b4 	movhi	r2,2054
+ 8031098:	10b87f17 	ldw	r2,-7684(r2)
+ 803109c:	10c00044 	addi	r3,r2,1
+ 80310a0:	008201b4 	movhi	r2,2054
+ 80310a4:	10f87f15 	stw	r3,-7684(r2)
+   {
+      /*
+       * Get IP and TCP header together in first mbuf.
+       * Note: IP leaves IP header in first mbuf.
+       */
+      pip = mtod(m, struct ip *);
+ 80310a8:	e0bfe417 	ldw	r2,-112(fp)
+ 80310ac:	10800317 	ldw	r2,12(r2)
+ 80310b0:	e0bfff15 	stw	r2,-4(fp)
+      if (pip->ip_ver_ihl > 0x45)   /* IP v4, 5 dword hdr len */
+ 80310b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80310b8:	10800003 	ldbu	r2,0(r2)
+ 80310bc:	10803fcc 	andi	r2,r2,255
+ 80310c0:	108011b0 	cmpltui	r2,r2,70
+ 80310c4:	1000061e 	bne	r2,zero,80310e0 <tcp_input+0x90>
+      {
+         np_stripoptions(pip, (struct mbuf *)m);
+ 80310c8:	e17fe417 	ldw	r5,-112(fp)
+ 80310cc:	e13fff17 	ldw	r4,-4(fp)
+ 80310d0:	802ac180 	call	802ac18 <np_stripoptions>
+         pip = mtod(m, struct ip *);
+ 80310d4:	e0bfe417 	ldw	r2,-112(fp)
+ 80310d8:	10800317 	ldw	r2,12(r2)
+ 80310dc:	e0bfff15 	stw	r2,-4(fp)
+      }
+      if (m->m_len < ((sizeof (struct ip) + sizeof (struct tcphdr))))
+ 80310e0:	e0bfe417 	ldw	r2,-112(fp)
+ 80310e4:	10800217 	ldw	r2,8(r2)
+ 80310e8:	10800a28 	cmpgeui	r2,r2,40
+ 80310ec:	1000061e 	bne	r2,zero,8031108 <tcp_input+0xb8>
+      {
+         tcpstat.tcps_rcvshort++;
+ 80310f0:	008201b4 	movhi	r2,2054
+ 80310f4:	10b8c217 	ldw	r2,-7416(r2)
+ 80310f8:	10c00044 	addi	r3,r2,1
+ 80310fc:	008201b4 	movhi	r2,2054
+ 8031100:	10f8c215 	stw	r3,-7416(r2)
+         return;
+ 8031104:	00085206 	br	8033250 <tcp_input+0x2200>
+      }
+      tlen = pip->ip_len;     /* this was fudged by IP layer */
+ 8031108:	e0bfff17 	ldw	r2,-4(fp)
+ 803110c:	1080008b 	ldhu	r2,2(r2)
+ 8031110:	10bfffcc 	andi	r2,r2,65535
+ 8031114:	e0bff115 	stw	r2,-60(fp)
+      /* The following is needed in the cases where the size of the
+       * overlay structure is larger than the size of the ip header.
+       * This can happen if the ih_next and ih_prev pointers in the
+       * overlay structure are larger than 32 bit pointers.
+       */
+      ti = (struct tcpiphdr *)(m->m_data + sizeof(struct ip) - 
+ 8031118:	e0bfe417 	ldw	r2,-112(fp)
+ 803111c:	10800317 	ldw	r2,12(r2)
+ 8031120:	e0bff015 	stw	r2,-64(fp)
+         sizeof(struct ipovly));
+      if ((char *)ti < m->pkt->nb_buff)
+ 8031124:	e0bfe417 	ldw	r2,-112(fp)
+ 8031128:	10800117 	ldw	r2,4(r2)
+ 803112c:	10800117 	ldw	r2,4(r2)
+ 8031130:	e0fff017 	ldw	r3,-64(fp)
+ 8031134:	1880032e 	bgeu	r3,r2,8031144 <tcp_input+0xf4>
+      {
+         panic("tcp_input");
+ 8031138:	01020174 	movhi	r4,2053
+ 803113c:	212a9a04 	addi	r4,r4,-21912
+ 8031140:	80271780 	call	8027178 <panic>
+   /*
+    * Check that TCP offset makes sense,
+    * pull out TCP options and adjust length.
+    */
+
+   off = GET_TH_OFF(ti->ti_t) << 2;
+ 8031144:	e0bff017 	ldw	r2,-64(fp)
+ 8031148:	10800803 	ldbu	r2,32(r2)
+ 803114c:	10803fcc 	andi	r2,r2,255
+ 8031150:	1004d13a 	srli	r2,r2,4
+ 8031154:	10803fcc 	andi	r2,r2,255
+ 8031158:	100490ba 	slli	r2,r2,2
+ 803115c:	e0bfef15 	stw	r2,-68(fp)
+   if (off < sizeof (struct tcphdr) || off > tlen) 
+ 8031160:	e0bfef17 	ldw	r2,-68(fp)
+ 8031164:	10800530 	cmpltui	r2,r2,20
+ 8031168:	1000031e 	bne	r2,zero,8031178 <tcp_input+0x128>
+ 803116c:	e0bfef17 	ldw	r2,-68(fp)
+ 8031170:	e0fff117 	ldw	r3,-60(fp)
+ 8031174:	18800d0e 	bge	r3,r2,80311ac <tcp_input+0x15c>
+   {
+#ifdef DO_TCPTRACE
+      tcp_trace("tcp off: src %x off %d\n", ti->ti_src, off);
+#endif
+      tcpstat.tcps_rcvbadoff++;
+ 8031178:	008201b4 	movhi	r2,2054
+ 803117c:	10b8c117 	ldw	r2,-7420(r2)
+ 8031180:	10c00044 	addi	r3,r2,1
+ 8031184:	008201b4 	movhi	r2,2054
+ 8031188:	10f8c115 	stw	r3,-7420(r2)
+      TCP_MIB_INC(tcpInErrs);   /* keep MIB stats */
+ 803118c:	008201b4 	movhi	r2,2054
+ 8031190:	10b88317 	ldw	r2,-7668(r2)
+ 8031194:	10c00044 	addi	r3,r2,1
+ 8031198:	008201b4 	movhi	r2,2054
+ 803119c:	10f88315 	stw	r3,-7668(r2)
+      GOTO_DROP;
+ 80311a0:	00805784 	movi	r2,350
+ 80311a4:	d0a08715 	stw	r2,-32228(gp)
+ 80311a8:	00081406 	br	80331fc <tcp_input+0x21ac>
+   }
+   tlen -= (int)off;
+ 80311ac:	e0fff117 	ldw	r3,-60(fp)
+ 80311b0:	e0bfef17 	ldw	r2,-68(fp)
+ 80311b4:	1885c83a 	sub	r2,r3,r2
+ 80311b8:	e0bff115 	stw	r2,-60(fp)
+   ti->ti_len = (u_short)tlen;
+ 80311bc:	e0bff117 	ldw	r2,-60(fp)
+ 80311c0:	1007883a 	mov	r3,r2
+ 80311c4:	e0bff017 	ldw	r2,-64(fp)
+ 80311c8:	10c0028d 	sth	r3,10(r2)
+   if (off > sizeof (struct tcphdr)) 
+ 80311cc:	e0bfef17 	ldw	r2,-68(fp)
+ 80311d0:	10800570 	cmpltui	r2,r2,21
+ 80311d4:	1000331e 	bne	r2,zero,80312a4 <tcp_input+0x254>
+   {
+      int olen;      /* length of options field */
+      u_char * op;   /* scratch option pointer */
+
+      olen = off - sizeof (struct tcphdr);   /* get options length */
+ 80311d8:	e0bfef17 	ldw	r2,-68(fp)
+ 80311dc:	10bffb04 	addi	r2,r2,-20
+ 80311e0:	e0bfee15 	stw	r2,-72(fp)
+      om = m_getwithdata (MT_RXDATA, olen);  /* get mbuf for opts */
+ 80311e4:	e17fee17 	ldw	r5,-72(fp)
+ 80311e8:	01000044 	movi	r4,1
+ 80311ec:	8029a700 	call	8029a70 <m_getnbuf>
+ 80311f0:	e0bffd15 	stw	r2,-12(fp)
+      if (om == 0)
+ 80311f4:	e0bffd17 	ldw	r2,-12(fp)
+ 80311f8:	1000031e 	bne	r2,zero,8031208 <tcp_input+0x1b8>
+         GOTO_DROP;
+ 80311fc:	00805a84 	movi	r2,362
+ 8031200:	d0a08715 	stw	r2,-32228(gp)
+ 8031204:	0007fd06 	br	80331fc <tcp_input+0x21ac>
+      om->m_len = olen;       /* set mbuf length */
+ 8031208:	e0ffee17 	ldw	r3,-72(fp)
+ 803120c:	e0bffd17 	ldw	r2,-12(fp)
+ 8031210:	10c00215 	stw	r3,8(r2)
+      /* set pointer to options field at end of TCP header */
+      if(m->pkt->type == htons(0x86DD))   /* IPv6 packet */
+ 8031214:	e0bfe417 	ldw	r2,-112(fp)
+ 8031218:	10800117 	ldw	r2,4(r2)
+ 803121c:	1080080b 	ldhu	r2,32(r2)
+ 8031220:	10ffffcc 	andi	r3,r2,65535
+ 8031224:	00b76194 	movui	r2,56710
+ 8031228:	1880051e 	bne	r3,r2,8031240 <tcp_input+0x1f0>
+         op = (u_char*)(m->m_data + 20);  /* past TCP header */
+ 803122c:	e0bfe417 	ldw	r2,-112(fp)
+ 8031230:	10800317 	ldw	r2,12(r2)
+ 8031234:	10800504 	addi	r2,r2,20
+ 8031238:	e0bff415 	stw	r2,-48(fp)
+ 803123c:	00000406 	br	8031250 <tcp_input+0x200>
+      else
+         op = (u_char*)(m->m_data + 40);  /* past IP + TCP */
+ 8031240:	e0bfe417 	ldw	r2,-112(fp)
+ 8031244:	10800317 	ldw	r2,12(r2)
+ 8031248:	10800a04 	addi	r2,r2,40
+ 803124c:	e0bff415 	stw	r2,-48(fp)
+      MEMCPY(om->m_data, op, olen); /* copy to new mbuf */
+ 8031250:	e0bffd17 	ldw	r2,-12(fp)
+ 8031254:	10800317 	ldw	r2,12(r2)
+ 8031258:	e0ffee17 	ldw	r3,-72(fp)
+ 803125c:	180d883a 	mov	r6,r3
+ 8031260:	e17ff417 	ldw	r5,-48(fp)
+ 8031264:	1009883a 	mov	r4,r2
+ 8031268:	80086b80 	call	80086b8 <memcpy>
+
+      /* strip options from data mbuf. This actually just cuts the first 
+       * m_len bytes from the TCP header, but it leaves the mbuf members 
+       * set so the adjustment below does the right thing.
+       */
+      m->m_data += om->m_len;
+ 803126c:	e0bfe417 	ldw	r2,-112(fp)
+ 8031270:	10c00317 	ldw	r3,12(r2)
+ 8031274:	e0bffd17 	ldw	r2,-12(fp)
+ 8031278:	10800217 	ldw	r2,8(r2)
+ 803127c:	1887883a 	add	r3,r3,r2
+ 8031280:	e0bfe417 	ldw	r2,-112(fp)
+ 8031284:	10c00315 	stw	r3,12(r2)
+      m->m_len -= om->m_len;
+ 8031288:	e0bfe417 	ldw	r2,-112(fp)
+ 803128c:	10c00217 	ldw	r3,8(r2)
+ 8031290:	e0bffd17 	ldw	r2,-12(fp)
+ 8031294:	10800217 	ldw	r2,8(r2)
+ 8031298:	1887c83a 	sub	r3,r3,r2
+ 803129c:	e0bfe417 	ldw	r2,-112(fp)
+ 80312a0:	10c00215 	stw	r3,8(r2)
+   }
+   tiflags = ti->ti_flags;
+ 80312a4:	e0bff017 	ldw	r2,-64(fp)
+ 80312a8:	10800843 	ldbu	r2,33(r2)
+ 80312ac:	10803fcc 	andi	r2,r2,255
+ 80312b0:	e0bffb15 	stw	r2,-20(fp)
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   /* Convert TCP protocol specific fields to host format. */
+   ti->ti_seq = ntohl(ti->ti_seq);
+ 80312b4:	e0bff017 	ldw	r2,-64(fp)
+ 80312b8:	10800617 	ldw	r2,24(r2)
+ 80312bc:	1006d63a 	srli	r3,r2,24
+ 80312c0:	e0bff017 	ldw	r2,-64(fp)
+ 80312c4:	10800617 	ldw	r2,24(r2)
+ 80312c8:	1004d23a 	srli	r2,r2,8
+ 80312cc:	10bfc00c 	andi	r2,r2,65280
+ 80312d0:	1886b03a 	or	r3,r3,r2
+ 80312d4:	e0bff017 	ldw	r2,-64(fp)
+ 80312d8:	10800617 	ldw	r2,24(r2)
+ 80312dc:	1004923a 	slli	r2,r2,8
+ 80312e0:	10803fec 	andhi	r2,r2,255
+ 80312e4:	1886b03a 	or	r3,r3,r2
+ 80312e8:	e0bff017 	ldw	r2,-64(fp)
+ 80312ec:	10800617 	ldw	r2,24(r2)
+ 80312f0:	1004963a 	slli	r2,r2,24
+ 80312f4:	1886b03a 	or	r3,r3,r2
+ 80312f8:	e0bff017 	ldw	r2,-64(fp)
+ 80312fc:	10c00615 	stw	r3,24(r2)
+   ti->ti_ack = ntohl(ti->ti_ack);
+ 8031300:	e0bff017 	ldw	r2,-64(fp)
+ 8031304:	10800717 	ldw	r2,28(r2)
+ 8031308:	1006d63a 	srli	r3,r2,24
+ 803130c:	e0bff017 	ldw	r2,-64(fp)
+ 8031310:	10800717 	ldw	r2,28(r2)
+ 8031314:	1004d23a 	srli	r2,r2,8
+ 8031318:	10bfc00c 	andi	r2,r2,65280
+ 803131c:	1886b03a 	or	r3,r3,r2
+ 8031320:	e0bff017 	ldw	r2,-64(fp)
+ 8031324:	10800717 	ldw	r2,28(r2)
+ 8031328:	1004923a 	slli	r2,r2,8
+ 803132c:	10803fec 	andhi	r2,r2,255
+ 8031330:	1886b03a 	or	r3,r3,r2
+ 8031334:	e0bff017 	ldw	r2,-64(fp)
+ 8031338:	10800717 	ldw	r2,28(r2)
+ 803133c:	1004963a 	slli	r2,r2,24
+ 8031340:	1886b03a 	or	r3,r3,r2
+ 8031344:	e0bff017 	ldw	r2,-64(fp)
+ 8031348:	10c00715 	stw	r3,28(r2)
+   ti->ti_urp = ntohs(ti->ti_urp);
+ 803134c:	e0bff017 	ldw	r2,-64(fp)
+ 8031350:	1080098b 	ldhu	r2,38(r2)
+ 8031354:	10bfffcc 	andi	r2,r2,65535
+ 8031358:	1004d23a 	srli	r2,r2,8
+ 803135c:	1007883a 	mov	r3,r2
+ 8031360:	e0bff017 	ldw	r2,-64(fp)
+ 8031364:	1080098b 	ldhu	r2,38(r2)
+ 8031368:	10bfffcc 	andi	r2,r2,65535
+ 803136c:	1004923a 	slli	r2,r2,8
+ 8031370:	1884b03a 	or	r2,r3,r2
+ 8031374:	1007883a 	mov	r3,r2
+ 8031378:	e0bff017 	ldw	r2,-64(fp)
+ 803137c:	10c0098d 	sth	r3,38(r2)
+   /*
+    * Locate pcb for segment.
+    */
+findpcb:
+
+   switch(m->pkt->type)
+ 8031380:	e0bfe417 	ldw	r2,-112(fp)
+ 8031384:	10800117 	ldw	r2,4(r2)
+ 8031388:	1080080b 	ldhu	r2,32(r2)
+ 803138c:	10bfffcc 	andi	r2,r2,65535
+ 8031390:	10800218 	cmpnei	r2,r2,8
+ 8031394:	1000221e 	bne	r2,zero,8031420 <tcp_input+0x3d0>
+   {
+#ifdef IP_V4
+   case  IPTP:   /* IPv4 packet */
+      /* Drop TCP and IP headers; TCP options were dropped above. */
+      m->m_data += 40;
+ 8031398:	e0bfe417 	ldw	r2,-112(fp)
+ 803139c:	10800317 	ldw	r2,12(r2)
+ 80313a0:	10c00a04 	addi	r3,r2,40
+ 80313a4:	e0bfe417 	ldw	r2,-112(fp)
+ 80313a8:	10c00315 	stw	r3,12(r2)
+      m->m_len -= 40;
+ 80313ac:	e0bfe417 	ldw	r2,-112(fp)
+ 80313b0:	10800217 	ldw	r2,8(r2)
+ 80313b4:	10fff604 	addi	r3,r2,-40
+ 80313b8:	e0bfe417 	ldw	r2,-112(fp)
+ 80313bc:	10c00215 	stw	r3,8(r2)
+
+      inp = in_pcblookup(&tcb, ti->ti_src.s_addr, ti->ti_sport, 
+ 80313c0:	e0bff017 	ldw	r2,-64(fp)
+ 80313c4:	11000317 	ldw	r4,12(r2)
+ 80313c8:	e0bff017 	ldw	r2,-64(fp)
+ 80313cc:	1080050b 	ldhu	r2,20(r2)
+ 80313d0:	117fffcc 	andi	r5,r2,65535
+ 80313d4:	e0bff017 	ldw	r2,-64(fp)
+ 80313d8:	11800417 	ldw	r6,16(r2)
+         ti->ti_dst.s_addr, ti->ti_dport, INPLOOKUP_WILDCARD);
+ 80313dc:	e0bff017 	ldw	r2,-64(fp)
+ 80313e0:	1080058b 	ldhu	r2,22(r2)
+      inp = in_pcblookup(&tcb, ti->ti_src.s_addr, ti->ti_sport, 
+ 80313e4:	10bfffcc 	andi	r2,r2,65535
+ 80313e8:	00c00044 	movi	r3,1
+ 80313ec:	d8c00115 	stw	r3,4(sp)
+ 80313f0:	d8800015 	stw	r2,0(sp)
+ 80313f4:	300f883a 	mov	r7,r6
+ 80313f8:	280d883a 	mov	r6,r5
+ 80313fc:	200b883a 	mov	r5,r4
+ 8031400:	010201b4 	movhi	r4,2054
+ 8031404:	21389904 	addi	r4,r4,-7580
+ 8031408:	8040b600 	call	8040b60 <in_pcblookup>
+ 803140c:	e0bffe15 	stw	r2,-8(fp)
+      break;
+ 8031410:	0001883a 	nop
+    * If the state is CLOSED (i.e., TCB does not exist) then
+    * all data in the incoming segment is discarded.
+    * If the TCB exists but is in CLOSED state, it is embryonic,
+    * but should either do a listen or a connect soon.
+    */
+   if (inp == 0)
+ 8031414:	e0bffe17 	ldw	r2,-8(fp)
+ 8031418:	1000061e 	bne	r2,zero,8031434 <tcp_input+0x3e4>
+ 803141c:	00000206 	br	8031428 <tcp_input+0x3d8>
+      dtrap();
+ 8031420:	8028cd40 	call	8028cd4 <dtrap>
+      return;
+ 8031424:	00078a06 	br	8033250 <tcp_input+0x2200>
+      GOTO_DROPWITHRESET;
+ 8031428:	00806b04 	movi	r2,428
+ 803142c:	d0a08715 	stw	r2,-32228(gp)
+ 8031430:	00073306 	br	8033100 <tcp_input+0x20b0>
+   tp = intotcpcb (inp);
+ 8031434:	e0bffe17 	ldw	r2,-8(fp)
+ 8031438:	10800917 	ldw	r2,36(r2)
+ 803143c:	e0bffc15 	stw	r2,-16(fp)
+   if (tp == 0)
+ 8031440:	e0bffc17 	ldw	r2,-16(fp)
+ 8031444:	1000031e 	bne	r2,zero,8031454 <tcp_input+0x404>
+      GOTO_DROPWITHRESET;
+ 8031448:	00806bc4 	movi	r2,431
+ 803144c:	d0a08715 	stw	r2,-32228(gp)
+ 8031450:	00072b06 	br	8033100 <tcp_input+0x20b0>
+   if (tp->t_state == TCPS_CLOSED)
+ 8031454:	e0bffc17 	ldw	r2,-16(fp)
+ 8031458:	10800217 	ldw	r2,8(r2)
+ 803145c:	1000031e 	bne	r2,zero,803146c <tcp_input+0x41c>
+      GOTO_DROP;
+ 8031460:	00806c44 	movi	r2,433
+ 8031464:	d0a08715 	stw	r2,-32228(gp)
+ 8031468:	00076406 	br	80331fc <tcp_input+0x21ac>
+   so = inp->inp_socket;
+ 803146c:	e0bffe17 	ldw	r2,-8(fp)
+ 8031470:	10800817 	ldw	r2,32(r2)
+ 8031474:	e0bffa15 	stw	r2,-24(fp)
+      tcp_saveti = *ti;
+   }
+#endif
+
+   /* figure out the size of the other guy's receive window */
+   rx_win = (tcp_win)(ntohs(ti->ti_win));    /* convert endian */
+ 8031478:	e0bff017 	ldw	r2,-64(fp)
+ 803147c:	1080088b 	ldhu	r2,34(r2)
+ 8031480:	10bfffcc 	andi	r2,r2,65535
+ 8031484:	1004d23a 	srli	r2,r2,8
+ 8031488:	10bfffcc 	andi	r2,r2,65535
+ 803148c:	10c03fcc 	andi	r3,r2,255
+ 8031490:	e0bff017 	ldw	r2,-64(fp)
+ 8031494:	1080088b 	ldhu	r2,34(r2)
+ 8031498:	10bfffcc 	andi	r2,r2,65535
+ 803149c:	1004923a 	slli	r2,r2,8
+ 80314a0:	10bfffcc 	andi	r2,r2,65535
+ 80314a4:	1884b03a 	or	r2,r3,r2
+ 80314a8:	e0bfed15 	stw	r2,-76(fp)
+   {
+      rx_win <<= tp->snd_wind_scale;         /* apply scale */
+   }
+#endif /* TCP_WIN_SCALE */
+
+   if (so->so_options & SO_ACCEPTCONN) 
+ 80314ac:	e0bffa17 	ldw	r2,-24(fp)
+ 80314b0:	10800417 	ldw	r2,16(r2)
+ 80314b4:	1080008c 	andi	r2,r2,2
+ 80314b8:	10002c26 	beq	r2,zero,803156c <tcp_input+0x51c>
+   {
+      so = sonewconn(so);
+ 80314bc:	e13ffa17 	ldw	r4,-24(fp)
+ 80314c0:	802f4480 	call	802f448 <sonewconn>
+ 80314c4:	e0bffa15 	stw	r2,-24(fp)
+      if (so == 0)
+ 80314c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80314cc:	1000031e 	bne	r2,zero,80314dc <tcp_input+0x48c>
+         GOTO_DROP;
+ 80314d0:	00807344 	movi	r2,461
+ 80314d4:	d0a08715 	stw	r2,-32228(gp)
+ 80314d8:	00074806 	br	80331fc <tcp_input+0x21ac>
+       * flag dropsocket to see if the temporary
+       * socket created here should be discarded.
+       * We mark the socket as discardable until
+       * we're committed to it below in TCPS_LISTEN.
+       */
+      dropsocket++;
+ 80314dc:	e0bff617 	ldw	r2,-40(fp)
+ 80314e0:	10800044 	addi	r2,r2,1
+ 80314e4:	e0bff615 	stw	r2,-40(fp)
+
+      inp = (struct inpcb *)so->so_pcb;
+ 80314e8:	e0bffa17 	ldw	r2,-24(fp)
+ 80314ec:	10800117 	ldw	r2,4(r2)
+ 80314f0:	e0bffe15 	stw	r2,-8(fp)
+      inp->ifp = ifp;      /* save iface to peer */
+ 80314f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80314f8:	e0ffe317 	ldw	r3,-116(fp)
+ 80314fc:	10c00a15 	stw	r3,40(r2)
+
+      switch(so->so_domain)
+ 8031500:	e0bffa17 	ldw	r2,-24(fp)
+ 8031504:	10800517 	ldw	r2,20(r2)
+ 8031508:	10800098 	cmpnei	r2,r2,2
+ 803150c:	10000d1e 	bne	r2,zero,8031544 <tcp_input+0x4f4>
+      {
+#ifdef IP_V4
+      case AF_INET:
+         inp->inp_laddr = ti->ti_dst;
+ 8031510:	e0bffe17 	ldw	r2,-8(fp)
+ 8031514:	e0fff017 	ldw	r3,-64(fp)
+ 8031518:	18c00417 	ldw	r3,16(r3)
+ 803151c:	10c00415 	stw	r3,16(r2)
+#ifdef IP_PMTU
+         inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr);
+#else    /* not compiled for pathmtu, guess based on iface */
+         inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40);
+ 8031520:	e0bfe317 	ldw	r2,-116(fp)
+ 8031524:	10c00917 	ldw	r3,36(r2)
+ 8031528:	e0bfe317 	ldw	r2,-116(fp)
+ 803152c:	10800817 	ldw	r2,32(r2)
+ 8031530:	10800a04 	addi	r2,r2,40
+ 8031534:	1887c83a 	sub	r3,r3,r2
+ 8031538:	e0bffe17 	ldw	r2,-8(fp)
+ 803153c:	10c00615 	stw	r3,24(r2)
+#endif   /* IP_PMTU */
+         break;
+ 8031540:	0001883a 	nop
+         inp->inp_pmtu = ip6_pmtulookup(&ip6_src, ifp);
+         break;
+#endif   /* end v6 */
+      }
+
+      inp->inp_lport = ti->ti_dport;
+ 8031544:	e0bff017 	ldw	r2,-64(fp)
+ 8031548:	10c0058b 	ldhu	r3,22(r2)
+ 803154c:	e0bffe17 	ldw	r2,-8(fp)
+ 8031550:	10c0078d 	sth	r3,30(r2)
+      tp = intotcpcb(inp);
+ 8031554:	e0bffe17 	ldw	r2,-8(fp)
+ 8031558:	10800917 	ldw	r2,36(r2)
+ 803155c:	e0bffc15 	stw	r2,-16(fp)
+      tp->t_state = TCPS_LISTEN;
+ 8031560:	e0bffc17 	ldw	r2,-16(fp)
+ 8031564:	00c00044 	movi	r3,1
+ 8031568:	10c00215 	stw	r3,8(r2)
+
+   /*
+    * Segment received on connection.
+    * Reset idle time and keep-alive timer.
+    */
+   tp->t_idle = 0;
+ 803156c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031570:	10001d15 	stw	zero,116(r2)
+   tp->t_timer[TCPT_KEEP] = tcp_keepidle;
+ 8031574:	d0e01e17 	ldw	r3,-32648(gp)
+ 8031578:	e0bffc17 	ldw	r2,-16(fp)
+ 803157c:	10c00515 	stw	r3,20(r2)
+
+   /*
+    * Process options if not in LISTEN state,
+    * else do it below (after getting remote address).
+    */
+   if (om && tp->t_state != TCPS_LISTEN) 
+ 8031580:	e0bffd17 	ldw	r2,-12(fp)
+ 8031584:	10000926 	beq	r2,zero,80315ac <tcp_input+0x55c>
+ 8031588:	e0bffc17 	ldw	r2,-16(fp)
+ 803158c:	10800217 	ldw	r2,8(r2)
+ 8031590:	10800060 	cmpeqi	r2,r2,1
+ 8031594:	1000051e 	bne	r2,zero,80315ac <tcp_input+0x55c>
+   {
+      tcp_dooptions(tp, om, ti);
+ 8031598:	e1bff017 	ldw	r6,-64(fp)
+ 803159c:	e17ffd17 	ldw	r5,-12(fp)
+ 80315a0:	e13ffc17 	ldw	r4,-16(fp)
+ 80315a4:	80332640 	call	8033264 <tcp_dooptions>
+      om = 0;
+ 80315a8:	e03ffd15 	stw	zero,-12(fp)
+   }
+
+   acked = (int)(ti->ti_ack - tp->snd_una);
+ 80315ac:	e0bff017 	ldw	r2,-64(fp)
+ 80315b0:	10c00717 	ldw	r3,28(r2)
+ 80315b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80315b8:	10800e17 	ldw	r2,56(r2)
+ 80315bc:	1885c83a 	sub	r2,r3,r2
+ 80315c0:	e0bfec15 	stw	r2,-80(fp)
+    * Receive window is amount of space in rcv queue,
+    * but not less than advertised window.
+    */
+   { long win;
+
+      win = (long)sbspace(&so->so_rcv);
+ 80315c4:	e0bffa17 	ldw	r2,-24(fp)
+ 80315c8:	10800b17 	ldw	r2,44(r2)
+ 80315cc:	1007883a 	mov	r3,r2
+ 80315d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80315d4:	10800a17 	ldw	r2,40(r2)
+ 80315d8:	1885c83a 	sub	r2,r3,r2
+ 80315dc:	10000616 	blt	r2,zero,80315f8 <tcp_input+0x5a8>
+ 80315e0:	e0bffa17 	ldw	r2,-24(fp)
+ 80315e4:	10c00b17 	ldw	r3,44(r2)
+ 80315e8:	e0bffa17 	ldw	r2,-24(fp)
+ 80315ec:	10800a17 	ldw	r2,40(r2)
+ 80315f0:	1885c83a 	sub	r2,r3,r2
+ 80315f4:	00000106 	br	80315fc <tcp_input+0x5ac>
+ 80315f8:	0005883a 	mov	r2,zero
+ 80315fc:	e0bff315 	stw	r2,-52(fp)
+      if (win < 0)
+ 8031600:	e0bff317 	ldw	r2,-52(fp)
+ 8031604:	1000010e 	bge	r2,zero,803160c <tcp_input+0x5bc>
+         win = 0;
+ 8031608:	e03ff315 	stw	zero,-52(fp)
+      tp->rcv_wnd = (tcp_win)MAX((u_long)win, (tp->rcv_adv - tp->rcv_nxt));
+ 803160c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031610:	10c01917 	ldw	r3,100(r2)
+ 8031614:	e0bffc17 	ldw	r2,-16(fp)
+ 8031618:	10801617 	ldw	r2,88(r2)
+ 803161c:	1885c83a 	sub	r2,r3,r2
+ 8031620:	e0fff317 	ldw	r3,-52(fp)
+ 8031624:	10c0012e 	bgeu	r2,r3,803162c <tcp_input+0x5dc>
+ 8031628:	1805883a 	mov	r2,r3
+ 803162c:	e0fffc17 	ldw	r3,-16(fp)
+ 8031630:	18801515 	stw	r2,84(r3)
+    * is non-zero and the ack didn't move, we're the
+    * receiver side.  If we're getting packets in-order
+    * (the reassembly queue is empty), add the data to
+    * the socket buffer and note that we need a delayed ack.
+    */
+   if ((tp->t_state == TCPS_ESTABLISHED) &&
+ 8031634:	e0bffc17 	ldw	r2,-16(fp)
+ 8031638:	10800217 	ldw	r2,8(r2)
+ 803163c:	10800118 	cmpnei	r2,r2,4
+ 8031640:	1000f41e 	bne	r2,zero,8031a14 <tcp_input+0x9c4>
+       ((tiflags & (TH_SYN|TH_FIN|TH_RST|TH_URG|TH_ACK)) == TH_ACK) &&
+ 8031644:	e0bffb17 	ldw	r2,-20(fp)
+ 8031648:	10800dcc 	andi	r2,r2,55
+   if ((tp->t_state == TCPS_ESTABLISHED) &&
+ 803164c:	10800418 	cmpnei	r2,r2,16
+ 8031650:	1000f01e 	bne	r2,zero,8031a14 <tcp_input+0x9c4>
+       (ti->ti_seq == tp->rcv_nxt) &&
+ 8031654:	e0bff017 	ldw	r2,-64(fp)
+ 8031658:	10c00617 	ldw	r3,24(r2)
+ 803165c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031660:	10801617 	ldw	r2,88(r2)
+       ((tiflags & (TH_SYN|TH_FIN|TH_RST|TH_URG|TH_ACK)) == TH_ACK) &&
+ 8031664:	1880eb1e 	bne	r3,r2,8031a14 <tcp_input+0x9c4>
+       (ti->ti_seq == tp->rcv_nxt) &&
+ 8031668:	e0bfed17 	ldw	r2,-76(fp)
+ 803166c:	1000e926 	beq	r2,zero,8031a14 <tcp_input+0x9c4>
+       (rx_win && rx_win == tp->snd_wnd) &&
+ 8031670:	e0bffc17 	ldw	r2,-16(fp)
+ 8031674:	10801417 	ldw	r2,80(r2)
+ 8031678:	e0ffed17 	ldw	r3,-76(fp)
+ 803167c:	1880e51e 	bne	r3,r2,8031a14 <tcp_input+0x9c4>
+       (tp->snd_nxt == tp->snd_max))
+ 8031680:	e0bffc17 	ldw	r2,-16(fp)
+ 8031684:	10c00f17 	ldw	r3,60(r2)
+ 8031688:	e0bffc17 	ldw	r2,-16(fp)
+ 803168c:	10801a17 	ldw	r2,104(r2)
+       (rx_win && rx_win == tp->snd_wnd) &&
+ 8031690:	1880e01e 	bne	r3,r2,8031a14 <tcp_input+0x9c4>
+   {
+      if (ti->ti_len == 0)
+ 8031694:	e0bff017 	ldw	r2,-64(fp)
+ 8031698:	1080028b 	ldhu	r2,10(r2)
+ 803169c:	10bfffcc 	andi	r2,r2,65535
+ 80316a0:	10005b1e 	bne	r2,zero,8031810 <tcp_input+0x7c0>
+      {
+         if (SEQ_GT(ti->ti_ack, tp->snd_una) &&
+ 80316a4:	e0bff017 	ldw	r2,-64(fp)
+ 80316a8:	10c00717 	ldw	r3,28(r2)
+ 80316ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80316b0:	10800e17 	ldw	r2,56(r2)
+ 80316b4:	1885c83a 	sub	r2,r3,r2
+ 80316b8:	0080d60e 	bge	zero,r2,8031a14 <tcp_input+0x9c4>
+             SEQ_LEQ(ti->ti_ack, tp->snd_max) &&
+ 80316bc:	e0bff017 	ldw	r2,-64(fp)
+ 80316c0:	10c00717 	ldw	r3,28(r2)
+ 80316c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80316c8:	10801a17 	ldw	r2,104(r2)
+ 80316cc:	1885c83a 	sub	r2,r3,r2
+         if (SEQ_GT(ti->ti_ack, tp->snd_una) &&
+ 80316d0:	0080d016 	blt	zero,r2,8031a14 <tcp_input+0x9c4>
+             tp->snd_cwnd >= tp->snd_wnd) 
+ 80316d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80316d8:	10c01b17 	ldw	r3,108(r2)
+ 80316dc:	e0bffc17 	ldw	r2,-16(fp)
+ 80316e0:	10801417 	ldw	r2,80(r2)
+             SEQ_LEQ(ti->ti_ack, tp->snd_max) &&
+ 80316e4:	1880cb36 	bltu	r3,r2,8031a14 <tcp_input+0x9c4>
+         {
+            /*
+             * this is a pure ack for outstanding data.
+             */
+            ++tcpstat.tcps_predack;
+ 80316e8:	008201b4 	movhi	r2,2054
+ 80316ec:	10b8d917 	ldw	r2,-7324(r2)
+ 80316f0:	10c00044 	addi	r3,r2,1
+ 80316f4:	008201b4 	movhi	r2,2054
+ 80316f8:	10f8d915 	stw	r3,-7324(r2)
+            if (tp->t_rttick && 
+ 80316fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8031700:	10801e17 	ldw	r2,120(r2)
+ 8031704:	10000826 	beq	r2,zero,8031728 <tcp_input+0x6d8>
+#ifdef TCP_TIMESTAMP
+               ((tp->t_flags & TF_TIMESTAMP) == 0) && 
+#endif /* TCP_TIMESTAMP */
+               (SEQ_GT(ti->ti_ack, tp->t_rtseq)))
+ 8031708:	e0bff017 	ldw	r2,-64(fp)
+ 803170c:	10c00717 	ldw	r3,28(r2)
+ 8031710:	e0bffc17 	ldw	r2,-16(fp)
+ 8031714:	10801f17 	ldw	r2,124(r2)
+ 8031718:	1885c83a 	sub	r2,r3,r2
+            if (tp->t_rttick && 
+ 803171c:	0080020e 	bge	zero,r2,8031728 <tcp_input+0x6d8>
+            {
+               tcp_xmit_timer(tp);
+ 8031720:	e13ffc17 	ldw	r4,-16(fp)
+ 8031724:	80335180 	call	8033518 <tcp_xmit_timer>
+            }
+
+            tcpstat.tcps_rcvackpack++;
+ 8031728:	008201b4 	movhi	r2,2054
+ 803172c:	10b8cf17 	ldw	r2,-7364(r2)
+ 8031730:	10c00044 	addi	r3,r2,1
+ 8031734:	008201b4 	movhi	r2,2054
+ 8031738:	10f8cf15 	stw	r3,-7364(r2)
+            tcpstat.tcps_rcvackbyte += acked;
+ 803173c:	008201b4 	movhi	r2,2054
+ 8031740:	10f8d017 	ldw	r3,-7360(r2)
+ 8031744:	e0bfec17 	ldw	r2,-80(fp)
+ 8031748:	1887883a 	add	r3,r3,r2
+ 803174c:	008201b4 	movhi	r2,2054
+ 8031750:	10f8d015 	stw	r3,-7360(r2)
+            sbdrop(&so->so_snd, acked);
+ 8031754:	e0bffa17 	ldw	r2,-24(fp)
+ 8031758:	10801204 	addi	r2,r2,72
+ 803175c:	e17fec17 	ldw	r5,-80(fp)
+ 8031760:	1009883a 	mov	r4,r2
+ 8031764:	80300b00 	call	80300b0 <sbdrop>
+            tp->snd_una = ti->ti_ack;
+ 8031768:	e0bff017 	ldw	r2,-64(fp)
+ 803176c:	10c00717 	ldw	r3,28(r2)
+ 8031770:	e0bffc17 	ldw	r2,-16(fp)
+ 8031774:	10c00e15 	stw	r3,56(r2)
+            m_freem(m);
+ 8031778:	e13fe417 	ldw	r4,-112(fp)
+ 803177c:	8029cfc0 	call	8029cfc <m_freem>
+             * If process is waiting for space,
+             * wakeup/selwakeup/signal.  If data
+             * are ready to send, let tcp_output
+             * decide between more output or persist.
+             */
+            if (tp->snd_una == tp->snd_max)
+ 8031780:	e0bffc17 	ldw	r2,-16(fp)
+ 8031784:	10c00e17 	ldw	r3,56(r2)
+ 8031788:	e0bffc17 	ldw	r2,-16(fp)
+ 803178c:	10801a17 	ldw	r2,104(r2)
+ 8031790:	1880031e 	bne	r3,r2,80317a0 <tcp_input+0x750>
+               tp->t_timer[TCPT_REXMT] = 0;
+ 8031794:	e0bffc17 	ldw	r2,-16(fp)
+ 8031798:	10000315 	stw	zero,12(r2)
+ 803179c:	00000706 	br	80317bc <tcp_input+0x76c>
+            else if (tp->t_timer[TCPT_PERSIST] == 0)
+ 80317a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80317a4:	10800417 	ldw	r2,16(r2)
+ 80317a8:	1000041e 	bne	r2,zero,80317bc <tcp_input+0x76c>
+               tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+ 80317ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80317b0:	10c00817 	ldw	r3,32(r2)
+ 80317b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80317b8:	10c00315 	stw	r3,12(r2)
+
+            if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL))
+ 80317bc:	e0bffa17 	ldw	r2,-24(fp)
+ 80317c0:	1080190b 	ldhu	r2,100(r2)
+ 80317c4:	10bfffcc 	andi	r2,r2,65535
+ 80317c8:	1080030c 	andi	r2,r2,12
+ 80317cc:	10000526 	beq	r2,zero,80317e4 <tcp_input+0x794>
+               sowwakeup(so);
+ 80317d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80317d4:	10801204 	addi	r2,r2,72
+ 80317d8:	100b883a 	mov	r5,r2
+ 80317dc:	e13ffa17 	ldw	r4,-24(fp)
+ 80317e0:	802f94c0 	call	802f94c <sbwakeup>
+
+            /* If there is more data in the send buffer, and some is
+             * still unsent, then call tcp_output() to try to send it
+             */
+            if (so->so_snd.sb_cc > (tp->snd_nxt - tp->snd_una))
+ 80317e4:	e0bffa17 	ldw	r2,-24(fp)
+ 80317e8:	10801217 	ldw	r2,72(r2)
+ 80317ec:	e0fffc17 	ldw	r3,-16(fp)
+ 80317f0:	19000f17 	ldw	r4,60(r3)
+ 80317f4:	e0fffc17 	ldw	r3,-16(fp)
+ 80317f8:	18c00e17 	ldw	r3,56(r3)
+ 80317fc:	20c7c83a 	sub	r3,r4,r3
+ 8031800:	18868a2e 	bgeu	r3,r2,803322c <tcp_input+0x21dc>
+               (void) tcp_output(tp);
+ 8031804:	e13ffc17 	ldw	r4,-16(fp)
+ 8031808:	80338940 	call	8033894 <tcp_output>
+            return;
+ 803180c:	00068706 	br	803322c <tcp_input+0x21dc>
+         }
+      }
+      else if (ti->ti_ack == tp->snd_una &&
+ 8031810:	e0bff017 	ldw	r2,-64(fp)
+ 8031814:	10c00717 	ldw	r3,28(r2)
+ 8031818:	e0bffc17 	ldw	r2,-16(fp)
+ 803181c:	10800e17 	ldw	r2,56(r2)
+ 8031820:	18807c1e 	bne	r3,r2,8031a14 <tcp_input+0x9c4>
+          tp->seg_next == (struct tcpiphdr *)tp &&
+ 8031824:	e0bffc17 	ldw	r2,-16(fp)
+ 8031828:	10800017 	ldw	r2,0(r2)
+      else if (ti->ti_ack == tp->snd_una &&
+ 803182c:	e0fffc17 	ldw	r3,-16(fp)
+ 8031830:	1880781e 	bne	r3,r2,8031a14 <tcp_input+0x9c4>
+          ti->ti_len <= sbspace(&so->so_rcv))
+ 8031834:	e0bff017 	ldw	r2,-64(fp)
+ 8031838:	1080028b 	ldhu	r2,10(r2)
+ 803183c:	10ffffcc 	andi	r3,r2,65535
+ 8031840:	e0bffa17 	ldw	r2,-24(fp)
+ 8031844:	10800b17 	ldw	r2,44(r2)
+ 8031848:	1009883a 	mov	r4,r2
+ 803184c:	e0bffa17 	ldw	r2,-24(fp)
+ 8031850:	10800a17 	ldw	r2,40(r2)
+ 8031854:	2085c83a 	sub	r2,r4,r2
+ 8031858:	10000616 	blt	r2,zero,8031874 <tcp_input+0x824>
+ 803185c:	e0bffa17 	ldw	r2,-24(fp)
+ 8031860:	11000b17 	ldw	r4,44(r2)
+ 8031864:	e0bffa17 	ldw	r2,-24(fp)
+ 8031868:	10800a17 	ldw	r2,40(r2)
+ 803186c:	2085c83a 	sub	r2,r4,r2
+ 8031870:	00000106 	br	8031878 <tcp_input+0x828>
+ 8031874:	0005883a 	mov	r2,zero
+          tp->seg_next == (struct tcpiphdr *)tp &&
+ 8031878:	10c06636 	bltu	r2,r3,8031a14 <tcp_input+0x9c4>
+#endif   /* TCP_ZEROCOPY */
+
+         /* this may also be a garden-variety probe received because
+          * the socket sendbuf was full.
+          */
+         if(tp->rcv_wnd == 0)
+ 803187c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031880:	10801517 	ldw	r2,84(r2)
+ 8031884:	10000a1e 	bne	r2,zero,80318b0 <tcp_input+0x860>
+             * info in this seg, but Windows NT 4.0 has a nasty bug where it
+             * will hammer us mericilessly with these probes (one customer
+             * reports thousands per second) so we just dump it ASAP to
+             * save cycles.
+             */
+            tcpstat.tcps_rcvwinprobe++;
+ 8031888:	008201b4 	movhi	r2,2054
+ 803188c:	10b8cc17 	ldw	r2,-7376(r2)
+ 8031890:	10c00044 	addi	r3,r2,1
+ 8031894:	008201b4 	movhi	r2,2054
+ 8031898:	10f8cc15 	stw	r3,-7376(r2)
+            m_freem (m);      /* free the received mbuf */
+ 803189c:	e13fe417 	ldw	r4,-112(fp)
+ 80318a0:	8029cfc0 	call	8029cfc <m_freem>
+            tcp_output(tp);   /* send the ack now... */
+ 80318a4:	e13ffc17 	ldw	r4,-16(fp)
+ 80318a8:	80338940 	call	8033894 <tcp_output>
+            return;
+ 80318ac:	00066806 	br	8033250 <tcp_input+0x2200>
+         /*
+          * this is a pure, in-sequence data packet
+          * with nothing on the reassembly queue and
+          * we have enough buffer space to take it.
+          */
+         ++tcpstat.tcps_preddat;
+ 80318b0:	008201b4 	movhi	r2,2054
+ 80318b4:	10b8da17 	ldw	r2,-7320(r2)
+ 80318b8:	10c00044 	addi	r3,r2,1
+ 80318bc:	008201b4 	movhi	r2,2054
+ 80318c0:	10f8da15 	stw	r3,-7320(r2)
+         tp->rcv_nxt += ti->ti_len;
+ 80318c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80318c8:	10c01617 	ldw	r3,88(r2)
+ 80318cc:	e0bff017 	ldw	r2,-64(fp)
+ 80318d0:	1080028b 	ldhu	r2,10(r2)
+ 80318d4:	10bfffcc 	andi	r2,r2,65535
+ 80318d8:	1887883a 	add	r3,r3,r2
+ 80318dc:	e0bffc17 	ldw	r2,-16(fp)
+ 80318e0:	10c01615 	stw	r3,88(r2)
+         tcpstat.tcps_rcvpack++;
+ 80318e4:	008201b4 	movhi	r2,2054
+ 80318e8:	10b8be17 	ldw	r2,-7432(r2)
+ 80318ec:	10c00044 	addi	r3,r2,1
+ 80318f0:	008201b4 	movhi	r2,2054
+ 80318f4:	10f8be15 	stw	r3,-7432(r2)
+         tcpstat.tcps_rcvbyte += ti->ti_len;
+ 80318f8:	008201b4 	movhi	r2,2054
+ 80318fc:	10f8bf17 	ldw	r3,-7428(r2)
+ 8031900:	e0bff017 	ldw	r2,-64(fp)
+ 8031904:	1080028b 	ldhu	r2,10(r2)
+ 8031908:	10bfffcc 	andi	r2,r2,65535
+ 803190c:	1887883a 	add	r3,r3,r2
+ 8031910:	008201b4 	movhi	r2,2054
+ 8031914:	10f8bf15 	stw	r3,-7428(r2)
+         /*
+          * Add data to socket buffer.
+          */
+         sbappend(&so->so_rcv, m);
+ 8031918:	e0bffa17 	ldw	r2,-24(fp)
+ 803191c:	10800a04 	addi	r2,r2,40
+ 8031920:	e17fe417 	ldw	r5,-112(fp)
+ 8031924:	1009883a 	mov	r4,r2
+ 8031928:	802fafc0 	call	802fafc <sbappend>
+         sorwakeup(so);
+ 803192c:	e0bffa17 	ldw	r2,-24(fp)
+ 8031930:	10800a04 	addi	r2,r2,40
+ 8031934:	100b883a 	mov	r5,r2
+ 8031938:	e13ffa17 	ldw	r4,-24(fp)
+ 803193c:	802f94c0 	call	802f94c <sbwakeup>
+         /*
+          * If this is a short packet, then ACK now - with Nagel
+          *   congestion avoidance sender won't send more until
+          *   he gets an ACK.
+          */
+         if (tiflags & TH_PUSH)
+ 8031940:	e0bffb17 	ldw	r2,-20(fp)
+ 8031944:	1080020c 	andi	r2,r2,8
+ 8031948:	10000726 	beq	r2,zero,8031968 <tcp_input+0x918>
+            tp->t_flags |= TF_ACKNOW;
+ 803194c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031950:	10800b0b 	ldhu	r2,44(r2)
+ 8031954:	10800054 	ori	r2,r2,1
+ 8031958:	1007883a 	mov	r3,r2
+ 803195c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031960:	10c00b0d 	sth	r3,44(r2)
+ 8031964:	00000606 	br	8031980 <tcp_input+0x930>
+         else
+            tp->t_flags |= TF_DELACK;
+ 8031968:	e0bffc17 	ldw	r2,-16(fp)
+ 803196c:	10800b0b 	ldhu	r2,44(r2)
+ 8031970:	10800094 	ori	r2,r2,2
+ 8031974:	1007883a 	mov	r3,r2
+ 8031978:	e0bffc17 	ldw	r2,-16(fp)
+ 803197c:	10c00b0d 	sth	r3,44(r2)
+
+         /* see if we need to send an ack */
+         adv = (int)(tp->rcv_wnd - (tcp_win)(tp->rcv_adv - tp->rcv_nxt));
+ 8031980:	e0bffc17 	ldw	r2,-16(fp)
+ 8031984:	10c01517 	ldw	r3,84(r2)
+ 8031988:	e0bffc17 	ldw	r2,-16(fp)
+ 803198c:	11001617 	ldw	r4,88(r2)
+ 8031990:	e0bffc17 	ldw	r2,-16(fp)
+ 8031994:	10801917 	ldw	r2,100(r2)
+ 8031998:	2085c83a 	sub	r2,r4,r2
+ 803199c:	1885883a 	add	r2,r3,r2
+ 80319a0:	e0bfeb15 	stw	r2,-84(fp)
+
+         if ((adv >= (int)(tp->t_maxseg * 2)) ||
+ 80319a4:	e0bffc17 	ldw	r2,-16(fp)
+ 80319a8:	10800a0b 	ldhu	r2,40(r2)
+ 80319ac:	10bfffcc 	andi	r2,r2,65535
+ 80319b0:	1085883a 	add	r2,r2,r2
+ 80319b4:	1007883a 	mov	r3,r2
+ 80319b8:	e0bfeb17 	ldw	r2,-84(fp)
+ 80319bc:	10c0050e 	bge	r2,r3,80319d4 <tcp_input+0x984>
+             (tp->t_flags & TF_ACKNOW))
+ 80319c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80319c4:	10800b0b 	ldhu	r2,44(r2)
+ 80319c8:	10bfffcc 	andi	r2,r2,65535
+ 80319cc:	1080004c 	andi	r2,r2,1
+         if ((adv >= (int)(tp->t_maxseg * 2)) ||
+ 80319d0:	10061826 	beq	r2,zero,8033234 <tcp_input+0x21e4>
+               tp->t_flags &= ~TF_ACKNOW;
+               return;
+            }
+#endif   /* DO_DELAY_ACKS */
+
+            tp->t_flags |= TF_ACKNOW;
+ 80319d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80319d8:	10800b0b 	ldhu	r2,44(r2)
+ 80319dc:	10800054 	ori	r2,r2,1
+ 80319e0:	1007883a 	mov	r3,r2
+ 80319e4:	e0bffc17 	ldw	r2,-16(fp)
+ 80319e8:	10c00b0d 	sth	r3,44(r2)
+            tp->t_flags &= ~TF_DELACK;
+ 80319ec:	e0bffc17 	ldw	r2,-16(fp)
+ 80319f0:	10c00b0b 	ldhu	r3,44(r2)
+ 80319f4:	00bfff44 	movi	r2,-3
+ 80319f8:	1884703a 	and	r2,r3,r2
+ 80319fc:	1007883a 	mov	r3,r2
+ 8031a00:	e0bffc17 	ldw	r2,-16(fp)
+ 8031a04:	10c00b0d 	sth	r3,44(r2)
+            tcp_output(tp);   /* send the ack now... */
+ 8031a08:	e13ffc17 	ldw	r4,-16(fp)
+ 8031a0c:	80338940 	call	8033894 <tcp_output>
+         }
+
+         return;
+ 8031a10:	00060806 	br	8033234 <tcp_input+0x21e4>
+      }
+   }
+
+   switch (tp->t_state) 
+ 8031a14:	e0bffc17 	ldw	r2,-16(fp)
+ 8031a18:	10800217 	ldw	r2,8(r2)
+ 8031a1c:	10c00060 	cmpeqi	r3,r2,1
+ 8031a20:	1800031e 	bne	r3,zero,8031a30 <tcp_input+0x9e0>
+ 8031a24:	108000a0 	cmpeqi	r2,r2,2
+ 8031a28:	1000a81e 	bne	r2,zero,8031ccc <tcp_input+0xc7c>
+ 8031a2c:	00017606 	br	8032008 <tcp_input+0xfb8>
+    */
+   case TCPS_LISTEN: 
+   {
+         struct mbuf *  am;
+
+         if (tiflags & TH_RST)
+ 8031a30:	e0bffb17 	ldw	r2,-20(fp)
+ 8031a34:	1080010c 	andi	r2,r2,4
+ 8031a38:	10000326 	beq	r2,zero,8031a48 <tcp_input+0x9f8>
+            GOTO_DROP;
+ 8031a3c:	0080bec4 	movi	r2,763
+ 8031a40:	d0a08715 	stw	r2,-32228(gp)
+ 8031a44:	0005ed06 	br	80331fc <tcp_input+0x21ac>
+         if (tiflags & TH_ACK)
+ 8031a48:	e0bffb17 	ldw	r2,-20(fp)
+ 8031a4c:	1080040c 	andi	r2,r2,16
+ 8031a50:	10000326 	beq	r2,zero,8031a60 <tcp_input+0xa10>
+            GOTO_DROPWITHRESET;
+ 8031a54:	0080bf44 	movi	r2,765
+ 8031a58:	d0a08715 	stw	r2,-32228(gp)
+ 8031a5c:	0005a806 	br	8033100 <tcp_input+0x20b0>
+         if ((tiflags & TH_SYN) == 0)
+ 8031a60:	e0bffb17 	ldw	r2,-20(fp)
+ 8031a64:	1080008c 	andi	r2,r2,2
+ 8031a68:	1000031e 	bne	r2,zero,8031a78 <tcp_input+0xa28>
+            GOTO_DROP;
+ 8031a6c:	0080bfc4 	movi	r2,767
+ 8031a70:	d0a08715 	stw	r2,-32228(gp)
+ 8031a74:	0005e106 	br	80331fc <tcp_input+0x21ac>
+         if(in_broadcast(ti->ti_dst.s_addr))
+ 8031a78:	e0bff017 	ldw	r2,-64(fp)
+ 8031a7c:	10800417 	ldw	r2,16(r2)
+ 8031a80:	1009883a 	mov	r4,r2
+ 8031a84:	802abe00 	call	802abe0 <in_broadcast>
+ 8031a88:	10000326 	beq	r2,zero,8031a98 <tcp_input+0xa48>
+            GOTO_DROP;
+ 8031a8c:	0080c044 	movi	r2,769
+ 8031a90:	d0a08715 	stw	r2,-32228(gp)
+ 8031a94:	0005d906 	br	80331fc <tcp_input+0x21ac>
+         am = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+ 8031a98:	01400404 	movi	r5,16
+ 8031a9c:	01000244 	movi	r4,9
+ 8031aa0:	8029a700 	call	8029a70 <m_getnbuf>
+ 8031aa4:	e0bfea15 	stw	r2,-88(fp)
+         if (am == NULL)
+ 8031aa8:	e0bfea17 	ldw	r2,-88(fp)
+ 8031aac:	1000031e 	bne	r2,zero,8031abc <tcp_input+0xa6c>
+            GOTO_DROP;
+ 8031ab0:	0080c104 	movi	r2,772
+ 8031ab4:	d0a08715 	stw	r2,-32228(gp)
+ 8031ab8:	0005d006 	br	80331fc <tcp_input+0x21ac>
+
+#ifdef IP_V4
+         if(inp->inp_socket->so_domain == AF_INET)
+ 8031abc:	e0bffe17 	ldw	r2,-8(fp)
+ 8031ac0:	10800817 	ldw	r2,32(r2)
+ 8031ac4:	10800517 	ldw	r2,20(r2)
+ 8031ac8:	10800098 	cmpnei	r2,r2,2
+ 8031acc:	10002c1e 	bne	r2,zero,8031b80 <tcp_input+0xb30>
+         {
+         struct sockaddr_in * sin;
+         am->m_len = sizeof (struct sockaddr_in);
+ 8031ad0:	e0bfea17 	ldw	r2,-88(fp)
+ 8031ad4:	00c00404 	movi	r3,16
+ 8031ad8:	10c00215 	stw	r3,8(r2)
+         sin = mtod(am, struct sockaddr_in *);
+ 8031adc:	e0bfea17 	ldw	r2,-88(fp)
+ 8031ae0:	10800317 	ldw	r2,12(r2)
+ 8031ae4:	e0bfe915 	stw	r2,-92(fp)
+         sin->sin_family = AF_INET;
+ 8031ae8:	e0bfe917 	ldw	r2,-92(fp)
+ 8031aec:	00c00084 	movi	r3,2
+ 8031af0:	10c0000d 	sth	r3,0(r2)
+         sin->sin_addr = ti->ti_src;
+ 8031af4:	e0bfe917 	ldw	r2,-92(fp)
+ 8031af8:	e0fff017 	ldw	r3,-64(fp)
+ 8031afc:	18c00317 	ldw	r3,12(r3)
+ 8031b00:	10c00115 	stw	r3,4(r2)
+         sin->sin_port = ti->ti_sport;
+ 8031b04:	e0bff017 	ldw	r2,-64(fp)
+ 8031b08:	10c0050b 	ldhu	r3,20(r2)
+ 8031b0c:	e0bfe917 	ldw	r2,-92(fp)
+ 8031b10:	10c0008d 	sth	r3,2(r2)
+         /* Assuming pcbconnect will work, we put the sender's address in 
+          * the inp_laddr (after saving a local laddr copy). If the connect
+          * fails we restore the inpcb before going to drop:
+          */
+         laddr = inp->inp_laddr;    /* save tmp laddr */
+ 8031b14:	e0bffe17 	ldw	r2,-8(fp)
+ 8031b18:	10800417 	ldw	r2,16(r2)
+ 8031b1c:	e0bfe515 	stw	r2,-108(fp)
+         if (inp->inp_laddr.s_addr == INADDR_ANY)
+ 8031b20:	e0bffe17 	ldw	r2,-8(fp)
+ 8031b24:	10800417 	ldw	r2,16(r2)
+ 8031b28:	1000041e 	bne	r2,zero,8031b3c <tcp_input+0xaec>
+            inp->inp_laddr = ti->ti_dst;
+ 8031b2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8031b30:	e0fff017 	ldw	r3,-64(fp)
+ 8031b34:	18c00417 	ldw	r3,16(r3)
+ 8031b38:	10c00415 	stw	r3,16(r2)
+         if (in_pcbconnect (inp, am)) 
+ 8031b3c:	e17fea17 	ldw	r5,-88(fp)
+ 8031b40:	e13ffe17 	ldw	r4,-8(fp)
+ 8031b44:	804081c0 	call	804081c <in_pcbconnect>
+ 8031b48:	10000826 	beq	r2,zero,8031b6c <tcp_input+0xb1c>
+         {
+            inp->inp_laddr = laddr;
+ 8031b4c:	e0bffe17 	ldw	r2,-8(fp)
+ 8031b50:	e0ffe517 	ldw	r3,-108(fp)
+ 8031b54:	10c00415 	stw	r3,16(r2)
+            (void) m_free(am);
+ 8031b58:	e13fea17 	ldw	r4,-88(fp)
+ 8031b5c:	8029bf80 	call	8029bf8 <m_free>
+            GOTO_DROP;
+ 8031b60:	0080c684 	movi	r2,794
+ 8031b64:	d0a08715 	stw	r2,-32228(gp)
+ 8031b68:	0005a406 	br	80331fc <tcp_input+0x21ac>
+         }
+         
+         inp->ifp = ifp;      /* set interface for conn.*/
+ 8031b6c:	e0bffe17 	ldw	r2,-8(fp)
+ 8031b70:	e0ffe317 	ldw	r3,-116(fp)
+ 8031b74:	10c00a15 	stw	r3,40(r2)
+         
+         (void) m_free (am);
+ 8031b78:	e13fea17 	ldw	r4,-88(fp)
+ 8031b7c:	8029bf80 	call	8029bf8 <m_free>
+            }
+            (void) m_free(am);
+         }
+#endif   /* end v6 */
+
+         tp->t_template = tcp_template(tp);
+ 8031b80:	e13ffc17 	ldw	r4,-16(fp)
+ 8031b84:	8034a400 	call	8034a40 <tcp_template>
+ 8031b88:	1007883a 	mov	r3,r2
+ 8031b8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031b90:	10c00c15 	stw	r3,48(r2)
+         if (tp->t_template == 0) 
+ 8031b94:	e0bffc17 	ldw	r2,-16(fp)
+ 8031b98:	10800c17 	ldw	r2,48(r2)
+ 8031b9c:	1000071e 	bne	r2,zero,8031bbc <tcp_input+0xb6c>
+         {
+            SETTP(tp, tcp_drop(tp, ENOBUFS));
+ 8031ba0:	01401a44 	movi	r5,105
+ 8031ba4:	e13ffc17 	ldw	r4,-16(fp)
+ 8031ba8:	803504c0 	call	803504c <tcp_drop>
+            dropsocket = 0;      /* socket is already gone */
+ 8031bac:	e03ff615 	stw	zero,-40(fp)
+            GOTO_DROP;
+ 8031bb0:	0080d1c4 	movi	r2,839
+ 8031bb4:	d0a08715 	stw	r2,-32228(gp)
+ 8031bb8:	00059006 	br	80331fc <tcp_input+0x21ac>
+         }
+         if (om) 
+ 8031bbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8031bc0:	10000526 	beq	r2,zero,8031bd8 <tcp_input+0xb88>
+         {
+            tcp_dooptions(tp, om, ti);
+ 8031bc4:	e1bff017 	ldw	r6,-64(fp)
+ 8031bc8:	e17ffd17 	ldw	r5,-12(fp)
+ 8031bcc:	e13ffc17 	ldw	r4,-16(fp)
+ 8031bd0:	80332640 	call	8033264 <tcp_dooptions>
+            om = 0;
+ 8031bd4:	e03ffd15 	stw	zero,-12(fp)
+         }
+         if (iss)
+ 8031bd8:	e0bff517 	ldw	r2,-44(fp)
+ 8031bdc:	10000426 	beq	r2,zero,8031bf0 <tcp_input+0xba0>
+            tp->iss = iss;
+ 8031be0:	e0fff517 	ldw	r3,-44(fp)
+ 8031be4:	e0bffc17 	ldw	r2,-16(fp)
+ 8031be8:	10c01315 	stw	r3,76(r2)
+ 8031bec:	00000306 	br	8031bfc <tcp_input+0xbac>
+         else
+            tp->iss = tcp_iss;
+ 8031bf0:	d0e08a17 	ldw	r3,-32216(gp)
+ 8031bf4:	e0bffc17 	ldw	r2,-16(fp)
+ 8031bf8:	10c01315 	stw	r3,76(r2)
+         tcp_iss += (unsigned)(TCP_ISSINCR/2);
+ 8031bfc:	d0e08a17 	ldw	r3,-32216(gp)
+ 8031c00:	00be9fd4 	movui	r2,64127
+ 8031c04:	1885883a 	add	r2,r3,r2
+ 8031c08:	d0a08a15 	stw	r2,-32216(gp)
+         tp->irs = ti->ti_seq;
+ 8031c0c:	e0bff017 	ldw	r2,-64(fp)
+ 8031c10:	10c00617 	ldw	r3,24(r2)
+ 8031c14:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c18:	10c01815 	stw	r3,96(r2)
+         tcp_sendseqinit(tp);
+ 8031c1c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c20:	10c01317 	ldw	r3,76(r2)
+ 8031c24:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c28:	10c01015 	stw	r3,64(r2)
+ 8031c2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c30:	10c01017 	ldw	r3,64(r2)
+ 8031c34:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c38:	10c01a15 	stw	r3,104(r2)
+ 8031c3c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c40:	10c01a17 	ldw	r3,104(r2)
+ 8031c44:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c48:	10c00f15 	stw	r3,60(r2)
+ 8031c4c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c50:	10c00f17 	ldw	r3,60(r2)
+ 8031c54:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c58:	10c00e15 	stw	r3,56(r2)
+         tcp_rcvseqinit(tp);
+ 8031c5c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c60:	10801817 	ldw	r2,96(r2)
+ 8031c64:	10c00044 	addi	r3,r2,1
+ 8031c68:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c6c:	10c01615 	stw	r3,88(r2)
+ 8031c70:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c74:	10c01617 	ldw	r3,88(r2)
+ 8031c78:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c7c:	10c01915 	stw	r3,100(r2)
+         tp->t_flags |= TF_ACKNOW;
+ 8031c80:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c84:	10800b0b 	ldhu	r2,44(r2)
+ 8031c88:	10800054 	ori	r2,r2,1
+ 8031c8c:	1007883a 	mov	r3,r2
+ 8031c90:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c94:	10c00b0d 	sth	r3,44(r2)
+         tp->t_state = TCPS_SYN_RECEIVED;
+ 8031c98:	e0bffc17 	ldw	r2,-16(fp)
+ 8031c9c:	00c000c4 	movi	r3,3
+ 8031ca0:	10c00215 	stw	r3,8(r2)
+         tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT;
+ 8031ca4:	e0bffc17 	ldw	r2,-16(fp)
+ 8031ca8:	00c02584 	movi	r3,150
+ 8031cac:	10c00515 	stw	r3,20(r2)
+         dropsocket = 0;      /* committed to socket */
+ 8031cb0:	e03ff615 	stw	zero,-40(fp)
+         tcpstat.tcps_accepts++;
+ 8031cb4:	008201b4 	movhi	r2,2054
+ 8031cb8:	10b8a517 	ldw	r2,-7532(r2)
+ 8031cbc:	10c00044 	addi	r3,r2,1
+ 8031cc0:	008201b4 	movhi	r2,2054
+ 8031cc4:	10f8a515 	stw	r3,-7532(r2)
+         goto trimthenstep6;
+ 8031cc8:	00008e06 	br	8031f04 <tcp_input+0xeb4>
+    *   if SYN has been acked change to ESTABLISHED else SYN_RCVD state
+    *   arrange for segment to be acked (eventually)
+    *   continue processing rest of data/controls, beginning with URG
+    */
+   case TCPS_SYN_SENT:
+      inp->ifp = ifp;
+ 8031ccc:	e0bffe17 	ldw	r2,-8(fp)
+ 8031cd0:	e0ffe317 	ldw	r3,-116(fp)
+ 8031cd4:	10c00a15 	stw	r3,40(r2)
+      if ((tiflags & TH_ACK) &&
+ 8031cd8:	e0bffb17 	ldw	r2,-20(fp)
+ 8031cdc:	1080040c 	andi	r2,r2,16
+ 8031ce0:	10000f26 	beq	r2,zero,8031d20 <tcp_input+0xcd0>
+          (SEQ_LEQ(ti->ti_ack, tp->iss) ||
+ 8031ce4:	e0bff017 	ldw	r2,-64(fp)
+ 8031ce8:	10c00717 	ldw	r3,28(r2)
+ 8031cec:	e0bffc17 	ldw	r2,-16(fp)
+ 8031cf0:	10801317 	ldw	r2,76(r2)
+ 8031cf4:	1885c83a 	sub	r2,r3,r2
+      if ((tiflags & TH_ACK) &&
+ 8031cf8:	0080060e 	bge	zero,r2,8031d14 <tcp_input+0xcc4>
+          SEQ_GT(ti->ti_ack, tp->snd_max)))
+ 8031cfc:	e0bff017 	ldw	r2,-64(fp)
+ 8031d00:	10c00717 	ldw	r3,28(r2)
+ 8031d04:	e0bffc17 	ldw	r2,-16(fp)
+ 8031d08:	10801a17 	ldw	r2,104(r2)
+ 8031d0c:	1885c83a 	sub	r2,r3,r2
+          (SEQ_LEQ(ti->ti_ack, tp->iss) ||
+ 8031d10:	0080030e 	bge	zero,r2,8031d20 <tcp_input+0xcd0>
+      {
+         GOTO_DROPWITHRESET;
+ 8031d14:	0080dc04 	movi	r2,880
+ 8031d18:	d0a08715 	stw	r2,-32228(gp)
+ 8031d1c:	0004f806 	br	8033100 <tcp_input+0x20b0>
+      }
+      if (tiflags & TH_RST) 
+ 8031d20:	e0bffb17 	ldw	r2,-20(fp)
+ 8031d24:	1080010c 	andi	r2,r2,4
+ 8031d28:	10000926 	beq	r2,zero,8031d50 <tcp_input+0xd00>
+      {
+         if (tiflags & TH_ACK)
+ 8031d2c:	e0bffb17 	ldw	r2,-20(fp)
+ 8031d30:	1080040c 	andi	r2,r2,16
+ 8031d34:	10000326 	beq	r2,zero,8031d44 <tcp_input+0xcf4>
+            SETTP(tp, tcp_drop(tp, ECONNREFUSED));
+ 8031d38:	01401bc4 	movi	r5,111
+ 8031d3c:	e13ffc17 	ldw	r4,-16(fp)
+ 8031d40:	803504c0 	call	803504c <tcp_drop>
+         GOTO_DROP;
+ 8031d44:	0080dd84 	movi	r2,886
+ 8031d48:	d0a08715 	stw	r2,-32228(gp)
+ 8031d4c:	00052b06 	br	80331fc <tcp_input+0x21ac>
+      }
+      if ((tiflags & TH_SYN) == 0)
+ 8031d50:	e0bffb17 	ldw	r2,-20(fp)
+ 8031d54:	1080008c 	andi	r2,r2,2
+ 8031d58:	1000031e 	bne	r2,zero,8031d68 <tcp_input+0xd18>
+         GOTO_DROP;
+ 8031d5c:	0080de44 	movi	r2,889
+ 8031d60:	d0a08715 	stw	r2,-32228(gp)
+ 8031d64:	00052506 	br	80331fc <tcp_input+0x21ac>
+      if (tiflags & TH_ACK) 
+ 8031d68:	e0bffb17 	ldw	r2,-20(fp)
+ 8031d6c:	1080040c 	andi	r2,r2,16
+ 8031d70:	10000e26 	beq	r2,zero,8031dac <tcp_input+0xd5c>
+      {
+         tp->snd_una = ti->ti_ack;
+ 8031d74:	e0bff017 	ldw	r2,-64(fp)
+ 8031d78:	10c00717 	ldw	r3,28(r2)
+ 8031d7c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031d80:	10c00e15 	stw	r3,56(r2)
+         if (SEQ_LT(tp->snd_nxt, tp->snd_una))
+ 8031d84:	e0bffc17 	ldw	r2,-16(fp)
+ 8031d88:	10c00f17 	ldw	r3,60(r2)
+ 8031d8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031d90:	10800e17 	ldw	r2,56(r2)
+ 8031d94:	1885c83a 	sub	r2,r3,r2
+ 8031d98:	1000040e 	bge	r2,zero,8031dac <tcp_input+0xd5c>
+            tp->snd_nxt = tp->snd_una;
+ 8031d9c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031da0:	10c00e17 	ldw	r3,56(r2)
+ 8031da4:	e0bffc17 	ldw	r2,-16(fp)
+ 8031da8:	10c00f15 	stw	r3,60(r2)
+      }
+      tp->t_timer[TCPT_REXMT] = 0;
+ 8031dac:	e0bffc17 	ldw	r2,-16(fp)
+ 8031db0:	10000315 	stw	zero,12(r2)
+      tp->irs = ti->ti_seq;
+ 8031db4:	e0bff017 	ldw	r2,-64(fp)
+ 8031db8:	10c00617 	ldw	r3,24(r2)
+ 8031dbc:	e0bffc17 	ldw	r2,-16(fp)
+ 8031dc0:	10c01815 	stw	r3,96(r2)
+      tcp_rcvseqinit(tp);
+ 8031dc4:	e0bffc17 	ldw	r2,-16(fp)
+ 8031dc8:	10801817 	ldw	r2,96(r2)
+ 8031dcc:	10c00044 	addi	r3,r2,1
+ 8031dd0:	e0bffc17 	ldw	r2,-16(fp)
+ 8031dd4:	10c01615 	stw	r3,88(r2)
+ 8031dd8:	e0bffc17 	ldw	r2,-16(fp)
+ 8031ddc:	10c01617 	ldw	r3,88(r2)
+ 8031de0:	e0bffc17 	ldw	r2,-16(fp)
+ 8031de4:	10c01915 	stw	r3,100(r2)
+      if (inp->inp_laddr.s_addr != ti->ti_dst.s_addr) 
+ 8031de8:	e0bffe17 	ldw	r2,-8(fp)
+ 8031dec:	10c00417 	ldw	r3,16(r2)
+ 8031df0:	e0bff017 	ldw	r2,-64(fp)
+ 8031df4:	10800417 	ldw	r2,16(r2)
+ 8031df8:	18801726 	beq	r3,r2,8031e58 <tcp_input+0xe08>
+          * the IP interface may have changed address since we sent our SYN
+          * (e.g. PPP brings link up as a result of said SYN and gets new
+          * address via IPCP); if so we need to update the inpcb and the
+          * TCP header template with the new address.
+          */
+         if ((m->pkt->net != NULL)
+ 8031dfc:	e0bfe417 	ldw	r2,-112(fp)
+ 8031e00:	10800117 	ldw	r2,4(r2)
+ 8031e04:	10800617 	ldw	r2,24(r2)
+ 8031e08:	10001326 	beq	r2,zero,8031e58 <tcp_input+0xe08>
+             && (m->pkt->net->n_ipaddr == ti->ti_dst.s_addr)) 
+ 8031e0c:	e0bfe417 	ldw	r2,-112(fp)
+ 8031e10:	10800117 	ldw	r2,4(r2)
+ 8031e14:	10800617 	ldw	r2,24(r2)
+ 8031e18:	10c00a17 	ldw	r3,40(r2)
+ 8031e1c:	e0bff017 	ldw	r2,-64(fp)
+ 8031e20:	10800417 	ldw	r2,16(r2)
+ 8031e24:	18800c1e 	bne	r3,r2,8031e58 <tcp_input+0xe08>
+      /* send an ack */
+         {
+            inp->inp_laddr = ti->ti_dst;
+ 8031e28:	e0bffe17 	ldw	r2,-8(fp)
+ 8031e2c:	e0fff017 	ldw	r3,-64(fp)
+ 8031e30:	18c00417 	ldw	r3,16(r3)
+ 8031e34:	10c00415 	stw	r3,16(r2)
+            if (tp->t_template != NULL)
+ 8031e38:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e3c:	10800c17 	ldw	r2,48(r2)
+ 8031e40:	10000526 	beq	r2,zero,8031e58 <tcp_input+0xe08>
+               tp->t_template->ti_src = ti->ti_dst;
+ 8031e44:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e48:	10800c17 	ldw	r2,48(r2)
+ 8031e4c:	e0fff017 	ldw	r3,-64(fp)
+ 8031e50:	18c00417 	ldw	r3,16(r3)
+ 8031e54:	10c00315 	stw	r3,12(r2)
+         }
+      }
+      tp->t_flags |= TF_ACKNOW;
+ 8031e58:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e5c:	10800b0b 	ldhu	r2,44(r2)
+ 8031e60:	10800054 	ori	r2,r2,1
+ 8031e64:	1007883a 	mov	r3,r2
+ 8031e68:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e6c:	10c00b0d 	sth	r3,44(r2)
+      if (tiflags & TH_ACK && SEQ_GT(tp->snd_una, tp->iss)) 
+ 8031e70:	e0bffb17 	ldw	r2,-20(fp)
+ 8031e74:	1080040c 	andi	r2,r2,16
+ 8031e78:	10001f26 	beq	r2,zero,8031ef8 <tcp_input+0xea8>
+ 8031e7c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e80:	10c00e17 	ldw	r3,56(r2)
+ 8031e84:	e0bffc17 	ldw	r2,-16(fp)
+ 8031e88:	10801317 	ldw	r2,76(r2)
+ 8031e8c:	1885c83a 	sub	r2,r3,r2
+ 8031e90:	0080190e 	bge	zero,r2,8031ef8 <tcp_input+0xea8>
+      {
+         tcpstat.tcps_connects++;
+ 8031e94:	008201b4 	movhi	r2,2054
+ 8031e98:	10b8a617 	ldw	r2,-7528(r2)
+ 8031e9c:	10c00044 	addi	r3,r2,1
+ 8031ea0:	008201b4 	movhi	r2,2054
+ 8031ea4:	10f8a615 	stw	r3,-7528(r2)
+         tp->t_state = TCPS_ESTABLISHED;
+ 8031ea8:	e0bffc17 	ldw	r2,-16(fp)
+ 8031eac:	00c00104 	movi	r3,4
+ 8031eb0:	10c00215 	stw	r3,8(r2)
+         soisconnected (so);
+ 8031eb4:	e13ffa17 	ldw	r4,-24(fp)
+ 8031eb8:	802f1e80 	call	802f1e8 <soisconnected>
+         tp->t_maxseg = tcp_mss(so);
+ 8031ebc:	e13ffa17 	ldw	r4,-24(fp)
+ 8031ec0:	803379c0 	call	803379c <tcp_mss>
+ 8031ec4:	1007883a 	mov	r3,r2
+ 8031ec8:	e0bffc17 	ldw	r2,-16(fp)
+ 8031ecc:	10c00a0d 	sth	r3,40(r2)
+         (void) tcp_reass (tp, (struct tcpiphdr *)0, m);
+ 8031ed0:	e1bfe417 	ldw	r6,-112(fp)
+ 8031ed4:	000b883a 	mov	r5,zero
+ 8031ed8:	e13ffc17 	ldw	r4,-16(fp)
+ 8031edc:	8030c600 	call	8030c60 <tcp_reass>
+         /*
+          * if we didn't have to retransmit the SYN,
+          * use its rtt as our initial srtt & rtt var.
+          */
+         if (tp->t_rttick) 
+ 8031ee0:	e0bffc17 	ldw	r2,-16(fp)
+ 8031ee4:	10801e17 	ldw	r2,120(r2)
+ 8031ee8:	10000626 	beq	r2,zero,8031f04 <tcp_input+0xeb4>
+         {
+            tcp_xmit_timer(tp);
+ 8031eec:	e13ffc17 	ldw	r4,-16(fp)
+ 8031ef0:	80335180 	call	8033518 <tcp_xmit_timer>
+         if (tp->t_rttick) 
+ 8031ef4:	00000306 	br	8031f04 <tcp_input+0xeb4>
+         }
+      } else
+         tp->t_state = TCPS_SYN_RECEIVED;
+ 8031ef8:	e0bffc17 	ldw	r2,-16(fp)
+ 8031efc:	00c000c4 	movi	r3,3
+ 8031f00:	10c00215 	stw	r3,8(r2)
+      /*
+       * Advance ti->ti_seq to correspond to first data byte.
+       * If data, trim to stay within window,
+       * dropping FIN if necessary.
+       */
+      ti->ti_seq++;
+ 8031f04:	e0bff017 	ldw	r2,-64(fp)
+ 8031f08:	10800617 	ldw	r2,24(r2)
+ 8031f0c:	10c00044 	addi	r3,r2,1
+ 8031f10:	e0bff017 	ldw	r2,-64(fp)
+ 8031f14:	10c00615 	stw	r3,24(r2)
+      if ((tcp_win)ti->ti_len > tp->rcv_wnd) 
+ 8031f18:	e0bff017 	ldw	r2,-64(fp)
+ 8031f1c:	1080028b 	ldhu	r2,10(r2)
+ 8031f20:	10bfffcc 	andi	r2,r2,65535
+ 8031f24:	e0fffc17 	ldw	r3,-16(fp)
+ 8031f28:	18c01517 	ldw	r3,84(r3)
+ 8031f2c:	18802c2e 	bgeu	r3,r2,8031fe0 <tcp_input+0xf90>
+      {
+         todrop = ti->ti_len - (u_short)tp->rcv_wnd;
+ 8031f30:	e0bff017 	ldw	r2,-64(fp)
+ 8031f34:	1080028b 	ldhu	r2,10(r2)
+ 8031f38:	10ffffcc 	andi	r3,r2,65535
+ 8031f3c:	e0bffc17 	ldw	r2,-16(fp)
+ 8031f40:	10801517 	ldw	r2,84(r2)
+ 8031f44:	10bfffcc 	andi	r2,r2,65535
+ 8031f48:	1885c83a 	sub	r2,r3,r2
+ 8031f4c:	e0bff915 	stw	r2,-28(fp)
+         /* XXX work around 4.2 m_adj bug */
+         if (m->m_len) 
+ 8031f50:	e0bfe417 	ldw	r2,-112(fp)
+ 8031f54:	10800217 	ldw	r2,8(r2)
+ 8031f58:	10000626 	beq	r2,zero,8031f74 <tcp_input+0xf24>
+         {
+            m_adj(m, -todrop);
+ 8031f5c:	e0bff917 	ldw	r2,-28(fp)
+ 8031f60:	0085c83a 	sub	r2,zero,r2
+ 8031f64:	100b883a 	mov	r5,r2
+ 8031f68:	e13fe417 	ldw	r4,-112(fp)
+ 8031f6c:	802a0180 	call	802a018 <m_adj>
+ 8031f70:	00000706 	br	8031f90 <tcp_input+0xf40>
+         }
+         else 
+         {
+            /* skip tcp/ip header in first mbuf */
+            m_adj(m->m_next, -todrop);
+ 8031f74:	e0bfe417 	ldw	r2,-112(fp)
+ 8031f78:	10c00617 	ldw	r3,24(r2)
+ 8031f7c:	e0bff917 	ldw	r2,-28(fp)
+ 8031f80:	0085c83a 	sub	r2,zero,r2
+ 8031f84:	100b883a 	mov	r5,r2
+ 8031f88:	1809883a 	mov	r4,r3
+ 8031f8c:	802a0180 	call	802a018 <m_adj>
+         }
+         ti->ti_len = (u_short)tp->rcv_wnd;
+ 8031f90:	e0bffc17 	ldw	r2,-16(fp)
+ 8031f94:	10801517 	ldw	r2,84(r2)
+ 8031f98:	1007883a 	mov	r3,r2
+ 8031f9c:	e0bff017 	ldw	r2,-64(fp)
+ 8031fa0:	10c0028d 	sth	r3,10(r2)
+         tiflags &= ~TH_FIN;
+ 8031fa4:	e0fffb17 	ldw	r3,-20(fp)
+ 8031fa8:	00bfff84 	movi	r2,-2
+ 8031fac:	1884703a 	and	r2,r3,r2
+ 8031fb0:	e0bffb15 	stw	r2,-20(fp)
+         tcpstat.tcps_rcvpackafterwin++;
+ 8031fb4:	008201b4 	movhi	r2,2054
+ 8031fb8:	10b8c917 	ldw	r2,-7388(r2)
+ 8031fbc:	10c00044 	addi	r3,r2,1
+ 8031fc0:	008201b4 	movhi	r2,2054
+ 8031fc4:	10f8c915 	stw	r3,-7388(r2)
+         tcpstat.tcps_rcvbyteafterwin += todrop;
+ 8031fc8:	008201b4 	movhi	r2,2054
+ 8031fcc:	10f8ca17 	ldw	r3,-7384(r2)
+ 8031fd0:	e0bff917 	ldw	r2,-28(fp)
+ 8031fd4:	1887883a 	add	r3,r3,r2
+ 8031fd8:	008201b4 	movhi	r2,2054
+ 8031fdc:	10f8ca15 	stw	r3,-7384(r2)
+      }
+      tp->snd_wl1 = ti->ti_seq - 1;
+ 8031fe0:	e0bff017 	ldw	r2,-64(fp)
+ 8031fe4:	10800617 	ldw	r2,24(r2)
+ 8031fe8:	10ffffc4 	addi	r3,r2,-1
+ 8031fec:	e0bffc17 	ldw	r2,-16(fp)
+ 8031ff0:	10c01115 	stw	r3,68(r2)
+      tp->rcv_up = ti->ti_seq;
+ 8031ff4:	e0bff017 	ldw	r2,-64(fp)
+ 8031ff8:	10c00617 	ldw	r3,24(r2)
+ 8031ffc:	e0bffc17 	ldw	r2,-16(fp)
+ 8032000:	10c01715 	stw	r3,92(r2)
+      goto step6;
+ 8032004:	0002cb06 	br	8032b34 <tcp_input+0x1ae4>
+    * States other than LISTEN or SYN_SENT.
+    * First check that at least some bytes of segment are within 
+    * receive window.  If segment begins before rcv_nxt,
+    * drop leading data (and SYN); if nothing left, just ack.
+    */
+   todrop = (int)(tp->rcv_nxt - ti->ti_seq);
+ 8032008:	e0bffc17 	ldw	r2,-16(fp)
+ 803200c:	10c01617 	ldw	r3,88(r2)
+ 8032010:	e0bff017 	ldw	r2,-64(fp)
+ 8032014:	10800617 	ldw	r2,24(r2)
+ 8032018:	1885c83a 	sub	r2,r3,r2
+ 803201c:	e0bff915 	stw	r2,-28(fp)
+   if (todrop > 0) 
+ 8032020:	e0bff917 	ldw	r2,-28(fp)
+ 8032024:	0080890e 	bge	zero,r2,803224c <tcp_input+0x11fc>
+   {
+      if (tiflags & TH_SYN) 
+ 8032028:	e0bffb17 	ldw	r2,-20(fp)
+ 803202c:	1080008c 	andi	r2,r2,2
+ 8032030:	10001c26 	beq	r2,zero,80320a4 <tcp_input+0x1054>
+      {
+         tiflags &= ~TH_SYN;
+ 8032034:	e0fffb17 	ldw	r3,-20(fp)
+ 8032038:	00bfff44 	movi	r2,-3
+ 803203c:	1884703a 	and	r2,r3,r2
+ 8032040:	e0bffb15 	stw	r2,-20(fp)
+         ti->ti_seq++;
+ 8032044:	e0bff017 	ldw	r2,-64(fp)
+ 8032048:	10800617 	ldw	r2,24(r2)
+ 803204c:	10c00044 	addi	r3,r2,1
+ 8032050:	e0bff017 	ldw	r2,-64(fp)
+ 8032054:	10c00615 	stw	r3,24(r2)
+         if (ti->ti_urp > 1) 
+ 8032058:	e0bff017 	ldw	r2,-64(fp)
+ 803205c:	1080098b 	ldhu	r2,38(r2)
+ 8032060:	10bfffcc 	andi	r2,r2,65535
+ 8032064:	108000b0 	cmpltui	r2,r2,2
+ 8032068:	1000071e 	bne	r2,zero,8032088 <tcp_input+0x1038>
+            ti->ti_urp--;
+ 803206c:	e0bff017 	ldw	r2,-64(fp)
+ 8032070:	1080098b 	ldhu	r2,38(r2)
+ 8032074:	10bfffc4 	addi	r2,r2,-1
+ 8032078:	1007883a 	mov	r3,r2
+ 803207c:	e0bff017 	ldw	r2,-64(fp)
+ 8032080:	10c0098d 	sth	r3,38(r2)
+ 8032084:	00000406 	br	8032098 <tcp_input+0x1048>
+         else
+            tiflags &= ~TH_URG;
+ 8032088:	e0fffb17 	ldw	r3,-20(fp)
+ 803208c:	00bff7c4 	movi	r2,-33
+ 8032090:	1884703a 	and	r2,r3,r2
+ 8032094:	e0bffb15 	stw	r2,-20(fp)
+         todrop--;
+ 8032098:	e0bff917 	ldw	r2,-28(fp)
+ 803209c:	10bfffc4 	addi	r2,r2,-1
+ 80320a0:	e0bff915 	stw	r2,-28(fp)
+      /*
+       * Altera Niche Stack Nios port modification:
+       * Add parenthesis to remove implicit order of operaton
+       * & possible build warning.
+       */
+      if ((todrop > (int)ti->ti_len) ||
+ 80320a4:	e0bff017 	ldw	r2,-64(fp)
+ 80320a8:	1080028b 	ldhu	r2,10(r2)
+ 80320ac:	10ffffcc 	andi	r3,r2,65535
+ 80320b0:	e0bff917 	ldw	r2,-28(fp)
+ 80320b4:	18800816 	blt	r3,r2,80320d8 <tcp_input+0x1088>
+          ((todrop == (int)ti->ti_len) && 
+ 80320b8:	e0bff017 	ldw	r2,-64(fp)
+ 80320bc:	1080028b 	ldhu	r2,10(r2)
+ 80320c0:	10bfffcc 	andi	r2,r2,65535
+      if ((todrop > (int)ti->ti_len) ||
+ 80320c4:	e0fff917 	ldw	r3,-28(fp)
+ 80320c8:	1880311e 	bne	r3,r2,8032190 <tcp_input+0x1140>
+          (tiflags&TH_FIN) == 0)) 
+ 80320cc:	e0bffb17 	ldw	r2,-20(fp)
+ 80320d0:	1080004c 	andi	r2,r2,1
+          ((todrop == (int)ti->ti_len) && 
+ 80320d4:	10002e1e 	bne	r2,zero,8032190 <tcp_input+0x1140>
+      {
+         tcpstat.tcps_rcvduppack++;
+ 80320d8:	008201b4 	movhi	r2,2054
+ 80320dc:	10b8c317 	ldw	r2,-7412(r2)
+ 80320e0:	10c00044 	addi	r3,r2,1
+ 80320e4:	008201b4 	movhi	r2,2054
+ 80320e8:	10f8c315 	stw	r3,-7412(r2)
+         tcpstat.tcps_rcvdupbyte += ti->ti_len;
+ 80320ec:	008201b4 	movhi	r2,2054
+ 80320f0:	10f8c417 	ldw	r3,-7408(r2)
+ 80320f4:	e0bff017 	ldw	r2,-64(fp)
+ 80320f8:	1080028b 	ldhu	r2,10(r2)
+ 80320fc:	10bfffcc 	andi	r2,r2,65535
+ 8032100:	1887883a 	add	r3,r3,r2
+ 8032104:	008201b4 	movhi	r2,2054
+ 8032108:	10f8c415 	stw	r3,-7408(r2)
+          *    it, but check the ACK or we will get into FIN
+          *    wars if our FINs crossed (both CLOSING).
+          * In either case, send ACK to resynchronize,
+          * but keep on processing for RST or ACK.
+          */
+         if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) ||
+ 803210c:	e0bffb17 	ldw	r2,-20(fp)
+ 8032110:	1080004c 	andi	r2,r2,1
+ 8032114:	10000626 	beq	r2,zero,8032130 <tcp_input+0x10e0>
+ 8032118:	e0bff017 	ldw	r2,-64(fp)
+ 803211c:	1080028b 	ldhu	r2,10(r2)
+ 8032120:	10bfffcc 	andi	r2,r2,65535
+ 8032124:	10800044 	addi	r2,r2,1
+ 8032128:	e0fff917 	ldw	r3,-28(fp)
+ 803212c:	18800926 	beq	r3,r2,8032154 <tcp_input+0x1104>
+            (tiflags & TH_RST && ti->ti_seq == tp->rcv_nxt - 1))
+ 8032130:	e0bffb17 	ldw	r2,-20(fp)
+ 8032134:	1080010c 	andi	r2,r2,4
+         if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) ||
+ 8032138:	1003dd26 	beq	r2,zero,80330b0 <tcp_input+0x2060>
+            (tiflags & TH_RST && ti->ti_seq == tp->rcv_nxt - 1))
+ 803213c:	e0bff017 	ldw	r2,-64(fp)
+ 8032140:	10c00617 	ldw	r3,24(r2)
+ 8032144:	e0bffc17 	ldw	r2,-16(fp)
+ 8032148:	10801617 	ldw	r2,88(r2)
+ 803214c:	10bfffc4 	addi	r2,r2,-1
+ 8032150:	1883d71e 	bne	r3,r2,80330b0 <tcp_input+0x2060>
+         {
+            todrop = ti->ti_len;
+ 8032154:	e0bff017 	ldw	r2,-64(fp)
+ 8032158:	1080028b 	ldhu	r2,10(r2)
+ 803215c:	10bfffcc 	andi	r2,r2,65535
+ 8032160:	e0bff915 	stw	r2,-28(fp)
+            tiflags &= ~TH_FIN;
+ 8032164:	e0fffb17 	ldw	r3,-20(fp)
+ 8032168:	00bfff84 	movi	r2,-2
+ 803216c:	1884703a 	and	r2,r3,r2
+ 8032170:	e0bffb15 	stw	r2,-20(fp)
+            tp->t_flags |= TF_ACKNOW;
+ 8032174:	e0bffc17 	ldw	r2,-16(fp)
+ 8032178:	10800b0b 	ldhu	r2,44(r2)
+ 803217c:	10800054 	ori	r2,r2,1
+ 8032180:	1007883a 	mov	r3,r2
+ 8032184:	e0bffc17 	ldw	r2,-16(fp)
+ 8032188:	10c00b0d 	sth	r3,44(r2)
+         if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) ||
+ 803218c:	00000b06 	br	80321bc <tcp_input+0x116c>
+         else
+            goto dropafterack;
+      }
+      else 
+      {
+         tcpstat.tcps_rcvpartduppack++;
+ 8032190:	008201b4 	movhi	r2,2054
+ 8032194:	10b8c517 	ldw	r2,-7404(r2)
+ 8032198:	10c00044 	addi	r3,r2,1
+ 803219c:	008201b4 	movhi	r2,2054
+ 80321a0:	10f8c515 	stw	r3,-7404(r2)
+         tcpstat.tcps_rcvpartdupbyte += todrop;
+ 80321a4:	008201b4 	movhi	r2,2054
+ 80321a8:	10f8c617 	ldw	r3,-7400(r2)
+ 80321ac:	e0bff917 	ldw	r2,-28(fp)
+ 80321b0:	1887883a 	add	r3,r3,r2
+ 80321b4:	008201b4 	movhi	r2,2054
+ 80321b8:	10f8c615 	stw	r3,-7400(r2)
+      }
+      m_adj(m, todrop);
+ 80321bc:	e17ff917 	ldw	r5,-28(fp)
+ 80321c0:	e13fe417 	ldw	r4,-112(fp)
+ 80321c4:	802a0180 	call	802a018 <m_adj>
+      ti->ti_seq += todrop;
+ 80321c8:	e0bff017 	ldw	r2,-64(fp)
+ 80321cc:	10c00617 	ldw	r3,24(r2)
+ 80321d0:	e0bff917 	ldw	r2,-28(fp)
+ 80321d4:	1887883a 	add	r3,r3,r2
+ 80321d8:	e0bff017 	ldw	r2,-64(fp)
+ 80321dc:	10c00615 	stw	r3,24(r2)
+      ti->ti_len -= (u_short)todrop;
+ 80321e0:	e0bff017 	ldw	r2,-64(fp)
+ 80321e4:	1080028b 	ldhu	r2,10(r2)
+ 80321e8:	e0fff917 	ldw	r3,-28(fp)
+ 80321ec:	10c5c83a 	sub	r2,r2,r3
+ 80321f0:	1007883a 	mov	r3,r2
+ 80321f4:	e0bff017 	ldw	r2,-64(fp)
+ 80321f8:	10c0028d 	sth	r3,10(r2)
+      if (ti->ti_urp > (u_short)todrop)
+ 80321fc:	e0bff017 	ldw	r2,-64(fp)
+ 8032200:	1080098b 	ldhu	r2,38(r2)
+ 8032204:	e0fff917 	ldw	r3,-28(fp)
+ 8032208:	10bfffcc 	andi	r2,r2,65535
+ 803220c:	18ffffcc 	andi	r3,r3,65535
+ 8032210:	1880082e 	bgeu	r3,r2,8032234 <tcp_input+0x11e4>
+         ti->ti_urp -= (u_short)todrop;
+ 8032214:	e0bff017 	ldw	r2,-64(fp)
+ 8032218:	1080098b 	ldhu	r2,38(r2)
+ 803221c:	e0fff917 	ldw	r3,-28(fp)
+ 8032220:	10c5c83a 	sub	r2,r2,r3
+ 8032224:	1007883a 	mov	r3,r2
+ 8032228:	e0bff017 	ldw	r2,-64(fp)
+ 803222c:	10c0098d 	sth	r3,38(r2)
+ 8032230:	00000606 	br	803224c <tcp_input+0x11fc>
+      else 
+      {
+         tiflags &= ~TH_URG;
+ 8032234:	e0fffb17 	ldw	r3,-20(fp)
+ 8032238:	00bff7c4 	movi	r2,-33
+ 803223c:	1884703a 	and	r2,r3,r2
+ 8032240:	e0bffb15 	stw	r2,-20(fp)
+         ti->ti_urp = 0;
+ 8032244:	e0bff017 	ldw	r2,-64(fp)
+ 8032248:	1000098d 	sth	zero,38(r2)
+
+   /*
+    * If new data are received on a connection after the
+    * user processes are gone, then RST the other end.
+    */
+   if ((so->so_state & SS_NOFDREF) &&
+ 803224c:	e0bffa17 	ldw	r2,-24(fp)
+ 8032250:	1080088b 	ldhu	r2,34(r2)
+ 8032254:	10bfffcc 	andi	r2,r2,65535
+ 8032258:	1080004c 	andi	r2,r2,1
+ 803225c:	10001326 	beq	r2,zero,80322ac <tcp_input+0x125c>
+       tp->t_state > TCPS_CLOSE_WAIT && ti->ti_len) 
+ 8032260:	e0bffc17 	ldw	r2,-16(fp)
+ 8032264:	10800217 	ldw	r2,8(r2)
+   if ((so->so_state & SS_NOFDREF) &&
+ 8032268:	10800190 	cmplti	r2,r2,6
+ 803226c:	10000f1e 	bne	r2,zero,80322ac <tcp_input+0x125c>
+       tp->t_state > TCPS_CLOSE_WAIT && ti->ti_len) 
+ 8032270:	e0bff017 	ldw	r2,-64(fp)
+ 8032274:	1080028b 	ldhu	r2,10(r2)
+ 8032278:	10bfffcc 	andi	r2,r2,65535
+ 803227c:	10000b26 	beq	r2,zero,80322ac <tcp_input+0x125c>
+   {
+      tp = tcp_close(tp);
+ 8032280:	e13ffc17 	ldw	r4,-16(fp)
+ 8032284:	80350e80 	call	80350e8 <tcp_close>
+ 8032288:	e0bffc15 	stw	r2,-16(fp)
+      tcpstat.tcps_rcvafterclose++;
+ 803228c:	008201b4 	movhi	r2,2054
+ 8032290:	10b8cb17 	ldw	r2,-7380(r2)
+ 8032294:	10c00044 	addi	r3,r2,1
+ 8032298:	008201b4 	movhi	r2,2054
+ 803229c:	10f8cb15 	stw	r3,-7380(r2)
+      GOTO_DROPWITHRESET;
+ 80322a0:	00810444 	movi	r2,1041
+ 80322a4:	d0a08715 	stw	r2,-32228(gp)
+ 80322a8:	00039506 	br	8033100 <tcp_input+0x20b0>
+
+   /*
+    * If segment ends after window, drop trailing data
+    * (and PUSH and FIN); if nothing left, just ACK.
+    */
+   todrop = (int)((ti->ti_seq + (short)ti->ti_len) - (tp->rcv_nxt+tp->rcv_wnd));
+ 80322ac:	e0bff017 	ldw	r2,-64(fp)
+ 80322b0:	10c00617 	ldw	r3,24(r2)
+ 80322b4:	e0bff017 	ldw	r2,-64(fp)
+ 80322b8:	1080028b 	ldhu	r2,10(r2)
+ 80322bc:	10bfffcc 	andi	r2,r2,65535
+ 80322c0:	10a0001c 	xori	r2,r2,32768
+ 80322c4:	10a00004 	addi	r2,r2,-32768
+ 80322c8:	1887883a 	add	r3,r3,r2
+ 80322cc:	e0bffc17 	ldw	r2,-16(fp)
+ 80322d0:	11001617 	ldw	r4,88(r2)
+ 80322d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80322d8:	10801517 	ldw	r2,84(r2)
+ 80322dc:	2085883a 	add	r2,r4,r2
+ 80322e0:	1885c83a 	sub	r2,r3,r2
+ 80322e4:	e0bff915 	stw	r2,-28(fp)
+   if (todrop > 0) 
+ 80322e8:	e0bff917 	ldw	r2,-28(fp)
+ 80322ec:	0080610e 	bge	zero,r2,8032474 <tcp_input+0x1424>
+   {
+      tcpstat.tcps_rcvpackafterwin++;
+ 80322f0:	008201b4 	movhi	r2,2054
+ 80322f4:	10b8c917 	ldw	r2,-7388(r2)
+ 80322f8:	10c00044 	addi	r3,r2,1
+ 80322fc:	008201b4 	movhi	r2,2054
+ 8032300:	10f8c915 	stw	r3,-7388(r2)
+      if (todrop >= (int)ti->ti_len) 
+ 8032304:	e0bff017 	ldw	r2,-64(fp)
+ 8032308:	1080028b 	ldhu	r2,10(r2)
+ 803230c:	10bfffcc 	andi	r2,r2,65535
+ 8032310:	e0fff917 	ldw	r3,-28(fp)
+ 8032314:	18803616 	blt	r3,r2,80323f0 <tcp_input+0x13a0>
+      {
+         tcpstat.tcps_rcvbyteafterwin += ti->ti_len;
+ 8032318:	008201b4 	movhi	r2,2054
+ 803231c:	10f8ca17 	ldw	r3,-7384(r2)
+ 8032320:	e0bff017 	ldw	r2,-64(fp)
+ 8032324:	1080028b 	ldhu	r2,10(r2)
+ 8032328:	10bfffcc 	andi	r2,r2,65535
+ 803232c:	1887883a 	add	r3,r3,r2
+ 8032330:	008201b4 	movhi	r2,2054
+ 8032334:	10f8ca15 	stw	r3,-7384(r2)
+          * If a new connection request is received
+          * while in TIME_WAIT, drop the old connection
+          * and start over if the sequence numbers
+          * are above the previous ones.
+          */
+         if (tiflags & TH_SYN &&
+ 8032338:	e0bffb17 	ldw	r2,-20(fp)
+ 803233c:	1080008c 	andi	r2,r2,2
+ 8032340:	10001726 	beq	r2,zero,80323a0 <tcp_input+0x1350>
+             tp->t_state == TCPS_TIME_WAIT &&
+ 8032344:	e0bffc17 	ldw	r2,-16(fp)
+ 8032348:	10800217 	ldw	r2,8(r2)
+         if (tiflags & TH_SYN &&
+ 803234c:	10800298 	cmpnei	r2,r2,10
+ 8032350:	1000131e 	bne	r2,zero,80323a0 <tcp_input+0x1350>
+             SEQ_GT(ti->ti_seq, tp->rcv_nxt)) 
+ 8032354:	e0bff017 	ldw	r2,-64(fp)
+ 8032358:	10c00617 	ldw	r3,24(r2)
+ 803235c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032360:	10801617 	ldw	r2,88(r2)
+ 8032364:	1885c83a 	sub	r2,r3,r2
+             tp->t_state == TCPS_TIME_WAIT &&
+ 8032368:	00800d0e 	bge	zero,r2,80323a0 <tcp_input+0x1350>
+         {
+            iss = (tcp_seq)(tp->rcv_nxt + (TCP_ISSINCR));
+ 803236c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032370:	10c01617 	ldw	r3,88(r2)
+ 8032374:	008000b4 	movhi	r2,2
+ 8032378:	10bd3fc4 	addi	r2,r2,-2817
+ 803237c:	1885883a 	add	r2,r3,r2
+ 8032380:	e0bff515 	stw	r2,-44(fp)
+            if (iss & 0xff000000)
+ 8032384:	e0bff517 	ldw	r2,-44(fp)
+ 8032388:	10bfc02c 	andhi	r2,r2,65280
+ 803238c:	10000126 	beq	r2,zero,8032394 <tcp_input+0x1344>
+            {
+               iss = 0L;
+ 8032390:	e03ff515 	stw	zero,-44(fp)
+            }
+            (void) tcp_close(tp);
+ 8032394:	e13ffc17 	ldw	r4,-16(fp)
+ 8032398:	80350e80 	call	80350e8 <tcp_close>
+            goto findpcb;
+ 803239c:	003bf806 	br	8031380 <tcp_input+0x330>
+          * window edge, and have to drop data and PUSH from
+          * incoming segments.  Continue processing, but
+          * remember to ack.  Otherwise, drop segment
+          * and ack.
+          */
+         if ((tp->rcv_wnd == 0) && (ti->ti_seq == tp->rcv_nxt))
+ 80323a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80323a4:	10801517 	ldw	r2,84(r2)
+ 80323a8:	1003431e 	bne	r2,zero,80330b8 <tcp_input+0x2068>
+ 80323ac:	e0bff017 	ldw	r2,-64(fp)
+ 80323b0:	10c00617 	ldw	r3,24(r2)
+ 80323b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80323b8:	10801617 	ldw	r2,88(r2)
+ 80323bc:	18833e1e 	bne	r3,r2,80330b8 <tcp_input+0x2068>
+         {
+            tp->t_flags |= TF_ACKNOW;
+ 80323c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80323c4:	10800b0b 	ldhu	r2,44(r2)
+ 80323c8:	10800054 	ori	r2,r2,1
+ 80323cc:	1007883a 	mov	r3,r2
+ 80323d0:	e0bffc17 	ldw	r2,-16(fp)
+ 80323d4:	10c00b0d 	sth	r3,44(r2)
+            tcpstat.tcps_rcvwinprobe++;
+ 80323d8:	008201b4 	movhi	r2,2054
+ 80323dc:	10b8cc17 	ldw	r2,-7376(r2)
+ 80323e0:	10c00044 	addi	r3,r2,1
+ 80323e4:	008201b4 	movhi	r2,2054
+ 80323e8:	10f8cc15 	stw	r3,-7376(r2)
+ 80323ec:	00000606 	br	8032408 <tcp_input+0x13b8>
+         } else
+            goto dropafterack;
+      } else
+         tcpstat.tcps_rcvbyteafterwin += todrop;
+ 80323f0:	008201b4 	movhi	r2,2054
+ 80323f4:	10f8ca17 	ldw	r3,-7384(r2)
+ 80323f8:	e0bff917 	ldw	r2,-28(fp)
+ 80323fc:	1887883a 	add	r3,r3,r2
+ 8032400:	008201b4 	movhi	r2,2054
+ 8032404:	10f8ca15 	stw	r3,-7384(r2)
+      /* XXX work around m_adj bug */
+      if (m->m_len) 
+ 8032408:	e0bfe417 	ldw	r2,-112(fp)
+ 803240c:	10800217 	ldw	r2,8(r2)
+ 8032410:	10000626 	beq	r2,zero,803242c <tcp_input+0x13dc>
+      {
+         m_adj(m, -todrop);
+ 8032414:	e0bff917 	ldw	r2,-28(fp)
+ 8032418:	0085c83a 	sub	r2,zero,r2
+ 803241c:	100b883a 	mov	r5,r2
+ 8032420:	e13fe417 	ldw	r4,-112(fp)
+ 8032424:	802a0180 	call	802a018 <m_adj>
+ 8032428:	00000706 	br	8032448 <tcp_input+0x13f8>
+      }
+      else 
+      {
+         /* skip tcp/ip header in first mbuf */
+         m_adj(m->m_next, -todrop);
+ 803242c:	e0bfe417 	ldw	r2,-112(fp)
+ 8032430:	10c00617 	ldw	r3,24(r2)
+ 8032434:	e0bff917 	ldw	r2,-28(fp)
+ 8032438:	0085c83a 	sub	r2,zero,r2
+ 803243c:	100b883a 	mov	r5,r2
+ 8032440:	1809883a 	mov	r4,r3
+ 8032444:	802a0180 	call	802a018 <m_adj>
+      }
+      ti->ti_len -= (u_short)todrop;
+ 8032448:	e0bff017 	ldw	r2,-64(fp)
+ 803244c:	1080028b 	ldhu	r2,10(r2)
+ 8032450:	e0fff917 	ldw	r3,-28(fp)
+ 8032454:	10c5c83a 	sub	r2,r2,r3
+ 8032458:	1007883a 	mov	r3,r2
+ 803245c:	e0bff017 	ldw	r2,-64(fp)
+ 8032460:	10c0028d 	sth	r3,10(r2)
+      tiflags &= ~(TH_PUSH|TH_FIN);
+ 8032464:	e0fffb17 	ldw	r3,-20(fp)
+ 8032468:	00bffd84 	movi	r2,-10
+ 803246c:	1884703a 	and	r2,r3,r2
+ 8032470:	e0bffb15 	stw	r2,-20(fp)
+      tiflags &= ~TH_RST;  /* clear reset flag */
+      goto dropafterack;   /* send an ack and drop current packet */
+   }
+#endif /* DOS_RST */
+
+   if (tiflags&TH_RST) 
+ 8032474:	e0bffb17 	ldw	r2,-20(fp)
+ 8032478:	1080010c 	andi	r2,r2,4
+ 803247c:	10002f26 	beq	r2,zero,803253c <tcp_input+0x14ec>
+   {
+      switch (tp->t_state) 
+ 8032480:	e0bffc17 	ldw	r2,-16(fp)
+ 8032484:	10800217 	ldw	r2,8(r2)
+ 8032488:	10bfff44 	addi	r2,r2,-3
+ 803248c:	10c00228 	cmpgeui	r3,r2,8
+ 8032490:	18002a1e 	bne	r3,zero,803253c <tcp_input+0x14ec>
+ 8032494:	100690ba 	slli	r3,r2,2
+ 8032498:	008200f4 	movhi	r2,2051
+ 803249c:	1885883a 	add	r2,r3,r2
+ 80324a0:	10892a17 	ldw	r2,9384(r2)
+ 80324a4:	1000683a 	jmp	r2
+ 80324a8:	080324c8 	cmpgei	zero,at,3219
+ 80324ac:	080324d8 	cmpnei	zero,at,3219
+ 80324b0:	080324ec 	andhi	zero,at,3219
+ 80324b4:	080324ec 	andhi	zero,at,3219
+ 80324b8:	08032528 	cmpgeui	zero,at,3220
+ 80324bc:	08032528 	cmpgeui	zero,at,3220
+ 80324c0:	080324ec 	andhi	zero,at,3219
+ 80324c4:	08032528 	cmpgeui	zero,at,3220
+      {
+   
+      case TCPS_SYN_RECEIVED:
+         so->so_error = ECONNREFUSED;
+ 80324c8:	e0bffa17 	ldw	r2,-24(fp)
+ 80324cc:	00c01bc4 	movi	r3,111
+ 80324d0:	10c00615 	stw	r3,24(r2)
+         goto close;
+ 80324d4:	00000806 	br	80324f8 <tcp_input+0x14a8>
+   
+      case TCPS_ESTABLISHED:
+         TCP_MIB_INC(tcpEstabResets);     /* keep MIB stats */
+ 80324d8:	008201b4 	movhi	r2,2054
+ 80324dc:	10b87d17 	ldw	r2,-7692(r2)
+ 80324e0:	10c00044 	addi	r3,r2,1
+ 80324e4:	008201b4 	movhi	r2,2054
+ 80324e8:	10f87d15 	stw	r3,-7692(r2)
+      case TCPS_FIN_WAIT_1:
+      case TCPS_FIN_WAIT_2:
+      case TCPS_CLOSE_WAIT:
+         so->so_error = ECONNRESET;
+ 80324ec:	e0bffa17 	ldw	r2,-24(fp)
+ 80324f0:	00c01a04 	movi	r3,104
+ 80324f4:	10c00615 	stw	r3,24(r2)
+         close:
+         tp->t_state = TCPS_CLOSED;
+ 80324f8:	e0bffc17 	ldw	r2,-16(fp)
+ 80324fc:	10000215 	stw	zero,8(r2)
+         tcpstat.tcps_drops++;
+ 8032500:	008201b4 	movhi	r2,2054
+ 8032504:	10b8a717 	ldw	r2,-7524(r2)
+ 8032508:	10c00044 	addi	r3,r2,1
+ 803250c:	008201b4 	movhi	r2,2054
+ 8032510:	10f8a715 	stw	r3,-7524(r2)
+         SETTP(tp, tcp_close(tp));
+ 8032514:	e13ffc17 	ldw	r4,-16(fp)
+ 8032518:	80350e80 	call	80350e8 <tcp_close>
+#ifdef TCP_ZEROCOPY
+         if (so->rx_upcall)
+            so->rx_upcall(so, NULL, ECONNRESET);
+#endif   /* TCP_ZEROCOPY */
+         GOTO_DROP;
+ 803251c:	00812204 	movi	r2,1160
+ 8032520:	d0a08715 	stw	r2,-32228(gp)
+ 8032524:	00033506 	br	80331fc <tcp_input+0x21ac>
+   
+      case TCPS_CLOSING:
+      case TCPS_LAST_ACK:
+      case TCPS_TIME_WAIT:
+         SETTP(tp, tcp_close(tp));
+ 8032528:	e13ffc17 	ldw	r4,-16(fp)
+ 803252c:	80350e80 	call	80350e8 <tcp_close>
+         GOTO_DROP;
+ 8032530:	00812384 	movi	r2,1166
+ 8032534:	d0a08715 	stw	r2,-32228(gp)
+ 8032538:	00033006 	br	80331fc <tcp_input+0x21ac>
+     tcp_trace("rcvd SYN in established state - ignoring SYN.\n");
+#endif
+      GOTO_DROP;
+   }
+#else
+   if (tiflags & TH_SYN) 
+ 803253c:	e0bffb17 	ldw	r2,-20(fp)
+ 8032540:	1080008c 	andi	r2,r2,2
+ 8032544:	10000726 	beq	r2,zero,8032564 <tcp_input+0x1514>
+   {
+      tp = tcp_drop(tp, ECONNRESET);
+ 8032548:	01401a04 	movi	r5,104
+ 803254c:	e13ffc17 	ldw	r4,-16(fp)
+ 8032550:	803504c0 	call	803504c <tcp_drop>
+ 8032554:	e0bffc15 	stw	r2,-16(fp)
+      GOTO_DROPWITHRESET;
+ 8032558:	00812b04 	movi	r2,1196
+ 803255c:	d0a08715 	stw	r2,-32228(gp)
+ 8032560:	0002e706 	br	8033100 <tcp_input+0x20b0>
+#endif /* end of else of DOS_SYN */
+
+   /*
+    * If the ACK bit is off we drop the segment and return.
+    */
+   if ((tiflags & TH_ACK) == 0)
+ 8032564:	e0bffb17 	ldw	r2,-20(fp)
+ 8032568:	1080040c 	andi	r2,r2,16
+ 803256c:	1000031e 	bne	r2,zero,803257c <tcp_input+0x152c>
+      GOTO_DROP;
+ 8032570:	00812d04 	movi	r2,1204
+ 8032574:	d0a08715 	stw	r2,-32228(gp)
+ 8032578:	00032006 	br	80331fc <tcp_input+0x21ac>
+
+   /*
+    * Ack processing.
+    */
+   switch (tp->t_state) 
+ 803257c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032580:	10800217 	ldw	r2,8(r2)
+ 8032584:	10c000e0 	cmpeqi	r3,r2,3
+ 8032588:	1800051e 	bne	r3,zero,80325a0 <tcp_input+0x1550>
+ 803258c:	10c000d0 	cmplti	r3,r2,3
+ 8032590:	1801681e 	bne	r3,zero,8032b34 <tcp_input+0x1ae4>
+ 8032594:	108002c8 	cmpgei	r2,r2,11
+ 8032598:	1001661e 	bne	r2,zero,8032b34 <tcp_input+0x1ae4>
+ 803259c:	00002c06 	br	8032650 <tcp_input+0x1600>
+    * In SYN_RECEIVED state if the ack ACKs our SYN then enter
+    * ESTABLISHED state and continue processing, otherwise
+    * send an RST.
+    */
+   case TCPS_SYN_RECEIVED:
+      if (SEQ_GT(tp->snd_una, ti->ti_ack) ||
+ 80325a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80325a4:	10c00e17 	ldw	r3,56(r2)
+ 80325a8:	e0bff017 	ldw	r2,-64(fp)
+ 80325ac:	10800717 	ldw	r2,28(r2)
+ 80325b0:	1885c83a 	sub	r2,r3,r2
+ 80325b4:	00800616 	blt	zero,r2,80325d0 <tcp_input+0x1580>
+          SEQ_GT(ti->ti_ack, tp->snd_max))
+ 80325b8:	e0bff017 	ldw	r2,-64(fp)
+ 80325bc:	10c00717 	ldw	r3,28(r2)
+ 80325c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80325c4:	10801a17 	ldw	r2,104(r2)
+ 80325c8:	1885c83a 	sub	r2,r3,r2
+      if (SEQ_GT(tp->snd_una, ti->ti_ack) ||
+ 80325cc:	0080080e 	bge	zero,r2,80325f0 <tcp_input+0x15a0>
+      {
+         TCP_MIB_INC(tcpEstabResets);     /* keep MIB stats */
+ 80325d0:	008201b4 	movhi	r2,2054
+ 80325d4:	10b87d17 	ldw	r2,-7692(r2)
+ 80325d8:	10c00044 	addi	r3,r2,1
+ 80325dc:	008201b4 	movhi	r2,2054
+ 80325e0:	10f87d15 	stw	r3,-7692(r2)
+         GOTO_DROPWITHRESET;
+ 80325e4:	00813184 	movi	r2,1222
+ 80325e8:	d0a08715 	stw	r2,-32228(gp)
+ 80325ec:	0002c406 	br	8033100 <tcp_input+0x20b0>
+      }
+      tcpstat.tcps_connects++;
+ 80325f0:	008201b4 	movhi	r2,2054
+ 80325f4:	10b8a617 	ldw	r2,-7528(r2)
+ 80325f8:	10c00044 	addi	r3,r2,1
+ 80325fc:	008201b4 	movhi	r2,2054
+ 8032600:	10f8a615 	stw	r3,-7528(r2)
+      tp->t_state = TCPS_ESTABLISHED;
+ 8032604:	e0bffc17 	ldw	r2,-16(fp)
+ 8032608:	00c00104 	movi	r3,4
+ 803260c:	10c00215 	stw	r3,8(r2)
+      soisconnected(so);
+ 8032610:	e13ffa17 	ldw	r4,-24(fp)
+ 8032614:	802f1e80 	call	802f1e8 <soisconnected>
+      tp->t_maxseg = tcp_mss(so);
+ 8032618:	e13ffa17 	ldw	r4,-24(fp)
+ 803261c:	803379c0 	call	803379c <tcp_mss>
+ 8032620:	1007883a 	mov	r3,r2
+ 8032624:	e0bffc17 	ldw	r2,-16(fp)
+ 8032628:	10c00a0d 	sth	r3,40(r2)
+      (void) tcp_reass(tp, (struct tcpiphdr *)0, m);
+ 803262c:	e1bfe417 	ldw	r6,-112(fp)
+ 8032630:	000b883a 	mov	r5,zero
+ 8032634:	e13ffc17 	ldw	r4,-16(fp)
+ 8032638:	8030c600 	call	8030c60 <tcp_reass>
+      tp->snd_wl1 = ti->ti_seq - 1;
+ 803263c:	e0bff017 	ldw	r2,-64(fp)
+ 8032640:	10800617 	ldw	r2,24(r2)
+ 8032644:	10ffffc4 	addi	r3,r2,-1
+ 8032648:	e0bffc17 	ldw	r2,-16(fp)
+ 803264c:	10c01115 	stw	r3,68(r2)
+   case TCPS_CLOSE_WAIT:
+   case TCPS_CLOSING:
+   case TCPS_LAST_ACK:
+   case TCPS_TIME_WAIT:
+
+      if (SEQ_LEQ(ti->ti_ack, tp->snd_una)) 
+ 8032650:	e0bff017 	ldw	r2,-64(fp)
+ 8032654:	10c00717 	ldw	r3,28(r2)
+ 8032658:	e0bffc17 	ldw	r2,-16(fp)
+ 803265c:	10800e17 	ldw	r2,56(r2)
+ 8032660:	1885c83a 	sub	r2,r3,r2
+ 8032664:	00806116 	blt	zero,r2,80327ec <tcp_input+0x179c>
+      {
+         if (ti->ti_len == 0 && rx_win == tp->snd_wnd) 
+ 8032668:	e0bff017 	ldw	r2,-64(fp)
+ 803266c:	1080028b 	ldhu	r2,10(r2)
+ 8032670:	10bfffcc 	andi	r2,r2,65535
+ 8032674:	1000581e 	bne	r2,zero,80327d8 <tcp_input+0x1788>
+ 8032678:	e0bffc17 	ldw	r2,-16(fp)
+ 803267c:	10801417 	ldw	r2,80(r2)
+ 8032680:	e0ffed17 	ldw	r3,-76(fp)
+ 8032684:	1880541e 	bne	r3,r2,80327d8 <tcp_input+0x1788>
+         {
+            tcpstat.tcps_rcvdupack++;
+ 8032688:	008201b4 	movhi	r2,2054
+ 803268c:	10b8cd17 	ldw	r2,-7372(r2)
+ 8032690:	10c00044 	addi	r3,r2,1
+ 8032694:	008201b4 	movhi	r2,2054
+ 8032698:	10f8cd15 	stw	r3,-7372(r2)
+             * ack and the exp-to-linear thresh
+             * set for half the current window
+             * size (since we know we're losing at
+             * the current window size).
+             */
+            if (tp->t_timer[TCPT_REXMT] == 0 ||
+ 803269c:	e0bffc17 	ldw	r2,-16(fp)
+ 80326a0:	10800317 	ldw	r2,12(r2)
+ 80326a4:	10000526 	beq	r2,zero,80326bc <tcp_input+0x166c>
+                ti->ti_ack != tp->snd_una)
+ 80326a8:	e0bff017 	ldw	r2,-64(fp)
+ 80326ac:	10c00717 	ldw	r3,28(r2)
+ 80326b0:	e0bffc17 	ldw	r2,-16(fp)
+ 80326b4:	10800e17 	ldw	r2,56(r2)
+            if (tp->t_timer[TCPT_REXMT] == 0 ||
+ 80326b8:	18800326 	beq	r3,r2,80326c8 <tcp_input+0x1678>
+            {
+               tp->t_dupacks = 0;
+ 80326bc:	e0bffc17 	ldw	r2,-16(fp)
+ 80326c0:	10000915 	stw	zero,36(r2)
+            if (tp->t_timer[TCPT_REXMT] == 0 ||
+ 80326c4:	00004706 	br	80327e4 <tcp_input+0x1794>
+            }
+            else if (++tp->t_dupacks == tcprexmtthresh) 
+ 80326c8:	e0bffc17 	ldw	r2,-16(fp)
+ 80326cc:	10800917 	ldw	r2,36(r2)
+ 80326d0:	10c00044 	addi	r3,r2,1
+ 80326d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80326d8:	10c00915 	stw	r3,36(r2)
+ 80326dc:	e0bffc17 	ldw	r2,-16(fp)
+ 80326e0:	10c00917 	ldw	r3,36(r2)
+ 80326e4:	d0a01c83 	ldbu	r2,-32654(gp)
+ 80326e8:	10803fcc 	andi	r2,r2,255
+ 80326ec:	1080201c 	xori	r2,r2,128
+ 80326f0:	10bfe004 	addi	r2,r2,-128
+ 80326f4:	18803b1e 	bne	r3,r2,80327e4 <tcp_input+0x1794>
+            {
+               tcp_seq onxt = tp->snd_nxt;
+ 80326f8:	e0bffc17 	ldw	r2,-16(fp)
+ 80326fc:	10800f17 	ldw	r2,60(r2)
+ 8032700:	e0bfe815 	stw	r2,-96(fp)
+               u_short  win   =
+               MIN(tp->snd_wnd, tp->snd_cwnd) / 2 /
+ 8032704:	e0bffc17 	ldw	r2,-16(fp)
+ 8032708:	11001417 	ldw	r4,80(r2)
+ 803270c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032710:	10c01b17 	ldw	r3,108(r2)
+ 8032714:	2005883a 	mov	r2,r4
+ 8032718:	1880012e 	bgeu	r3,r2,8032720 <tcp_input+0x16d0>
+ 803271c:	1805883a 	mov	r2,r3
+ 8032720:	1006d07a 	srli	r3,r2,1
+               tp->t_maxseg;
+ 8032724:	e0bffc17 	ldw	r2,-16(fp)
+ 8032728:	10800a0b 	ldhu	r2,40(r2)
+ 803272c:	10bfffcc 	andi	r2,r2,65535
+               MIN(tp->snd_wnd, tp->snd_cwnd) / 2 /
+ 8032730:	100b883a 	mov	r5,r2
+ 8032734:	1809883a 	mov	r4,r3
+ 8032738:	800cff80 	call	800cff8 <__udivsi3>
+               u_short  win   =
+ 803273c:	e0bff28d 	sth	r2,-54(fp)
+
+               if (win < 2)
+ 8032740:	e0bff28b 	ldhu	r2,-54(fp)
+ 8032744:	108000a8 	cmpgeui	r2,r2,2
+ 8032748:	1000021e 	bne	r2,zero,8032754 <tcp_input+0x1704>
+                  win = 2;
+ 803274c:	00800084 	movi	r2,2
+ 8032750:	e0bff28d 	sth	r2,-54(fp)
+               tp->snd_ssthresh = (u_short)(win * tp->t_maxseg);
+ 8032754:	e0bffc17 	ldw	r2,-16(fp)
+ 8032758:	10800a0b 	ldhu	r2,40(r2)
+ 803275c:	e0fff28b 	ldhu	r3,-54(fp)
+ 8032760:	1885383a 	mul	r2,r3,r2
+ 8032764:	10ffffcc 	andi	r3,r2,65535
+ 8032768:	e0bffc17 	ldw	r2,-16(fp)
+ 803276c:	10c01c15 	stw	r3,112(r2)
+
+               tp->t_timer[TCPT_REXMT] = 0;
+ 8032770:	e0bffc17 	ldw	r2,-16(fp)
+ 8032774:	10000315 	stw	zero,12(r2)
+               tp->t_rttick = 0;
+ 8032778:	e0bffc17 	ldw	r2,-16(fp)
+ 803277c:	10001e15 	stw	zero,120(r2)
+               tp->snd_nxt = ti->ti_ack;
+ 8032780:	e0bff017 	ldw	r2,-64(fp)
+ 8032784:	10c00717 	ldw	r3,28(r2)
+ 8032788:	e0bffc17 	ldw	r2,-16(fp)
+ 803278c:	10c00f15 	stw	r3,60(r2)
+               tp->snd_cwnd = tp->t_maxseg;
+ 8032790:	e0bffc17 	ldw	r2,-16(fp)
+ 8032794:	10800a0b 	ldhu	r2,40(r2)
+ 8032798:	10ffffcc 	andi	r3,r2,65535
+ 803279c:	e0bffc17 	ldw	r2,-16(fp)
+ 80327a0:	10c01b15 	stw	r3,108(r2)
+               (void) tcp_output(tp);
+ 80327a4:	e13ffc17 	ldw	r4,-16(fp)
+ 80327a8:	80338940 	call	8033894 <tcp_output>
+
+               if (SEQ_GT(onxt, tp->snd_nxt))
+ 80327ac:	e0bffc17 	ldw	r2,-16(fp)
+ 80327b0:	10800f17 	ldw	r2,60(r2)
+ 80327b4:	e0ffe817 	ldw	r3,-96(fp)
+ 80327b8:	1885c83a 	sub	r2,r3,r2
+ 80327bc:	0080030e 	bge	zero,r2,80327cc <tcp_input+0x177c>
+                  tp->snd_nxt = onxt;
+ 80327c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80327c4:	e0ffe817 	ldw	r3,-96(fp)
+ 80327c8:	10c00f15 	stw	r3,60(r2)
+               GOTO_DROP;
+ 80327cc:	00814544 	movi	r2,1301
+ 80327d0:	d0a08715 	stw	r2,-32228(gp)
+ 80327d4:	00028906 	br	80331fc <tcp_input+0x21ac>
+            }
+         } else
+            tp->t_dupacks = 0;
+ 80327d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80327dc:	10000915 	stw	zero,36(r2)
+         break;
+ 80327e0:	0000d406 	br	8032b34 <tcp_input+0x1ae4>
+            if (tp->t_timer[TCPT_REXMT] == 0 ||
+ 80327e4:	0001883a 	nop
+         break;
+ 80327e8:	0000d206 	br	8032b34 <tcp_input+0x1ae4>
+      }
+      tp->t_dupacks = 0;
+ 80327ec:	e0bffc17 	ldw	r2,-16(fp)
+ 80327f0:	10000915 	stw	zero,36(r2)
+      if (SEQ_GT(ti->ti_ack, tp->snd_max)) 
+ 80327f4:	e0bff017 	ldw	r2,-64(fp)
+ 80327f8:	10c00717 	ldw	r3,28(r2)
+ 80327fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8032800:	10801a17 	ldw	r2,104(r2)
+ 8032804:	1885c83a 	sub	r2,r3,r2
+ 8032808:	0080060e 	bge	zero,r2,8032824 <tcp_input+0x17d4>
+      {
+         tcpstat.tcps_rcvacktoomuch++;
+ 803280c:	008201b4 	movhi	r2,2054
+ 8032810:	10b8ce17 	ldw	r2,-7368(r2)
+ 8032814:	10c00044 	addi	r3,r2,1
+ 8032818:	008201b4 	movhi	r2,2054
+ 803281c:	10f8ce15 	stw	r3,-7368(r2)
+         goto dropafterack;
+ 8032820:	00022606 	br	80330bc <tcp_input+0x206c>
+      }
+      acked = (int)(ti->ti_ack - tp->snd_una);
+ 8032824:	e0bff017 	ldw	r2,-64(fp)
+ 8032828:	10c00717 	ldw	r3,28(r2)
+ 803282c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032830:	10800e17 	ldw	r2,56(r2)
+ 8032834:	1885c83a 	sub	r2,r3,r2
+ 8032838:	e0bfec15 	stw	r2,-80(fp)
+      tcpstat.tcps_rcvackpack++;
+ 803283c:	008201b4 	movhi	r2,2054
+ 8032840:	10b8cf17 	ldw	r2,-7364(r2)
+ 8032844:	10c00044 	addi	r3,r2,1
+ 8032848:	008201b4 	movhi	r2,2054
+ 803284c:	10f8cf15 	stw	r3,-7364(r2)
+      tcpstat.tcps_rcvackbyte += acked;
+ 8032850:	008201b4 	movhi	r2,2054
+ 8032854:	10f8d017 	ldw	r3,-7360(r2)
+ 8032858:	e0bfec17 	ldw	r2,-80(fp)
+ 803285c:	1887883a 	add	r3,r3,r2
+ 8032860:	008201b4 	movhi	r2,2054
+ 8032864:	10f8d015 	stw	r3,-7360(r2)
+       * number was acked, update smoothed round trip time.
+       * Since we now have an rtt measurement, cancel the
+       * timer backoff (cf., Phil Karn's retransmit alg.).
+       * Recompute the initial retransmit timer.
+       */
+      if((tp->t_rttick) && 
+ 8032868:	e0bffc17 	ldw	r2,-16(fp)
+ 803286c:	10801e17 	ldw	r2,120(r2)
+ 8032870:	10000826 	beq	r2,zero,8032894 <tcp_input+0x1844>
+#ifdef TCP_TIMESTAMP
+         ((tp->t_flags & TF_TIMESTAMP) == 0) && 
+#endif /* TCP_TIMESTAMP */
+         (SEQ_GT(ti->ti_ack, tp->t_rtseq)))
+ 8032874:	e0bff017 	ldw	r2,-64(fp)
+ 8032878:	10c00717 	ldw	r3,28(r2)
+ 803287c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032880:	10801f17 	ldw	r2,124(r2)
+ 8032884:	1885c83a 	sub	r2,r3,r2
+      if((tp->t_rttick) && 
+ 8032888:	0080020e 	bge	zero,r2,8032894 <tcp_input+0x1844>
+         tcp_xmit_timer(tp);
+ 803288c:	e13ffc17 	ldw	r4,-16(fp)
+ 8032890:	80335180 	call	8033518 <tcp_xmit_timer>
+       * If all outstanding data is acked, stop retransmit
+       * timer and remember to restart (more output or persist).
+       * If there is more data to be acked, restart retransmit
+       * timer, using current (possibly backed-off) value.
+       */
+      if (ti->ti_ack == tp->snd_max) 
+ 8032894:	e0bff017 	ldw	r2,-64(fp)
+ 8032898:	10c00717 	ldw	r3,28(r2)
+ 803289c:	e0bffc17 	ldw	r2,-16(fp)
+ 80328a0:	10801a17 	ldw	r2,104(r2)
+ 80328a4:	1880051e 	bne	r3,r2,80328bc <tcp_input+0x186c>
+      {
+         tp->t_timer[TCPT_REXMT] = 0;
+ 80328a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80328ac:	10000315 	stw	zero,12(r2)
+         needoutput = 1;
+ 80328b0:	00800044 	movi	r2,1
+ 80328b4:	e0bff715 	stw	r2,-36(fp)
+ 80328b8:	00000706 	br	80328d8 <tcp_input+0x1888>
+      } else if (tp->t_timer[TCPT_PERSIST] == 0)
+ 80328bc:	e0bffc17 	ldw	r2,-16(fp)
+ 80328c0:	10800417 	ldw	r2,16(r2)
+ 80328c4:	1000041e 	bne	r2,zero,80328d8 <tcp_input+0x1888>
+         tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+ 80328c8:	e0bffc17 	ldw	r2,-16(fp)
+ 80328cc:	10c00817 	ldw	r3,32(r2)
+ 80328d0:	e0bffc17 	ldw	r2,-16(fp)
+ 80328d4:	10c00315 	stw	r3,12(r2)
+       * in flight, open exponentially (maxseg per packet).
+       * Otherwise open linearly (maxseg per window,
+       * or maxseg^2 / cwnd per packet).
+       */
+      {
+         tcp_win  cw =  tp->snd_cwnd;
+ 80328d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80328dc:	10801b17 	ldw	r2,108(r2)
+ 80328e0:	e0bfe715 	stw	r2,-100(fp)
+         u_short  incr  =  tp->t_maxseg;
+ 80328e4:	e0bffc17 	ldw	r2,-16(fp)
+ 80328e8:	10800a0b 	ldhu	r2,40(r2)
+ 80328ec:	e0bff20d 	sth	r2,-56(fp)
+
+         if (cw > tp->snd_ssthresh)
+ 80328f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80328f4:	10c01c17 	ldw	r3,112(r2)
+ 80328f8:	e0bfe717 	ldw	r2,-100(fp)
+ 80328fc:	18800a2e 	bgeu	r3,r2,8032928 <tcp_input+0x18d8>
+            incr = MAX( (incr * incr / cw), (ALIGN_TYPE << 2) );
+ 8032900:	e0fff20b 	ldhu	r3,-56(fp)
+ 8032904:	e0bff20b 	ldhu	r2,-56(fp)
+ 8032908:	1885383a 	mul	r2,r3,r2
+ 803290c:	e17fe717 	ldw	r5,-100(fp)
+ 8032910:	1009883a 	mov	r4,r2
+ 8032914:	800cff80 	call	800cff8 <__udivsi3>
+ 8032918:	10c00428 	cmpgeui	r3,r2,16
+ 803291c:	1800011e 	bne	r3,zero,8032924 <tcp_input+0x18d4>
+ 8032920:	00800404 	movi	r2,16
+ 8032924:	e0bff20d 	sth	r2,-56(fp)
+
+         tp->snd_cwnd = MIN(cw + (u_short)incr, (IP_MAXPACKET));
+ 8032928:	e0fff20b 	ldhu	r3,-56(fp)
+ 803292c:	e0bfe717 	ldw	r2,-100(fp)
+ 8032930:	1885883a 	add	r2,r3,r2
+ 8032934:	10d80070 	cmpltui	r3,r2,24577
+ 8032938:	1800011e 	bne	r3,zero,8032940 <tcp_input+0x18f0>
+ 803293c:	00980004 	movi	r2,24576
+ 8032940:	e0fffc17 	ldw	r3,-16(fp)
+ 8032944:	18801b15 	stw	r2,108(r3)
+      }
+      if (acked > (int)so->so_snd.sb_cc) 
+ 8032948:	e0bffa17 	ldw	r2,-24(fp)
+ 803294c:	10801217 	ldw	r2,72(r2)
+ 8032950:	1007883a 	mov	r3,r2
+ 8032954:	e0bfec17 	ldw	r2,-80(fp)
+ 8032958:	1880120e 	bge	r3,r2,80329a4 <tcp_input+0x1954>
+      {
+         tp->snd_wnd -= (u_short)so->so_snd.sb_cc;
+ 803295c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032960:	10c01417 	ldw	r3,80(r2)
+ 8032964:	e0bffa17 	ldw	r2,-24(fp)
+ 8032968:	10801217 	ldw	r2,72(r2)
+ 803296c:	10bfffcc 	andi	r2,r2,65535
+ 8032970:	1887c83a 	sub	r3,r3,r2
+ 8032974:	e0bffc17 	ldw	r2,-16(fp)
+ 8032978:	10c01415 	stw	r3,80(r2)
+         sbdrop(&so->so_snd, (int)so->so_snd.sb_cc);
+ 803297c:	e0bffa17 	ldw	r2,-24(fp)
+ 8032980:	10c01204 	addi	r3,r2,72
+ 8032984:	e0bffa17 	ldw	r2,-24(fp)
+ 8032988:	10801217 	ldw	r2,72(r2)
+ 803298c:	100b883a 	mov	r5,r2
+ 8032990:	1809883a 	mov	r4,r3
+ 8032994:	80300b00 	call	80300b0 <sbdrop>
+         ourfinisacked = 1;
+ 8032998:	00800044 	movi	r2,1
+ 803299c:	e0bff815 	stw	r2,-32(fp)
+ 80329a0:	00000d06 	br	80329d8 <tcp_input+0x1988>
+      } 
+      else 
+      {
+         sbdrop(&so->so_snd, acked);
+ 80329a4:	e0bffa17 	ldw	r2,-24(fp)
+ 80329a8:	10801204 	addi	r2,r2,72
+ 80329ac:	e17fec17 	ldw	r5,-80(fp)
+ 80329b0:	1009883a 	mov	r4,r2
+ 80329b4:	80300b00 	call	80300b0 <sbdrop>
+         tp->snd_wnd -= (u_short)acked;
+ 80329b8:	e0bffc17 	ldw	r2,-16(fp)
+ 80329bc:	10c01417 	ldw	r3,80(r2)
+ 80329c0:	e0bfec17 	ldw	r2,-80(fp)
+ 80329c4:	10bfffcc 	andi	r2,r2,65535
+ 80329c8:	1887c83a 	sub	r3,r3,r2
+ 80329cc:	e0bffc17 	ldw	r2,-16(fp)
+ 80329d0:	10c01415 	stw	r3,80(r2)
+         ourfinisacked = 0;
+ 80329d4:	e03ff815 	stw	zero,-32(fp)
+      }
+
+      if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL))
+ 80329d8:	e0bffa17 	ldw	r2,-24(fp)
+ 80329dc:	1080190b 	ldhu	r2,100(r2)
+ 80329e0:	10bfffcc 	andi	r2,r2,65535
+ 80329e4:	1080030c 	andi	r2,r2,12
+ 80329e8:	10000526 	beq	r2,zero,8032a00 <tcp_input+0x19b0>
+         sowwakeup(so);
+ 80329ec:	e0bffa17 	ldw	r2,-24(fp)
+ 80329f0:	10801204 	addi	r2,r2,72
+ 80329f4:	100b883a 	mov	r5,r2
+ 80329f8:	e13ffa17 	ldw	r4,-24(fp)
+ 80329fc:	802f94c0 	call	802f94c <sbwakeup>
+
+      tp->snd_una = ti->ti_ack;
+ 8032a00:	e0bff017 	ldw	r2,-64(fp)
+ 8032a04:	10c00717 	ldw	r3,28(r2)
+ 8032a08:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a0c:	10c00e15 	stw	r3,56(r2)
+      if (SEQ_LT(tp->snd_nxt, tp->snd_una))
+ 8032a10:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a14:	10c00f17 	ldw	r3,60(r2)
+ 8032a18:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a1c:	10800e17 	ldw	r2,56(r2)
+ 8032a20:	1885c83a 	sub	r2,r3,r2
+ 8032a24:	1000040e 	bge	r2,zero,8032a38 <tcp_input+0x19e8>
+         tp->snd_nxt = tp->snd_una;
+ 8032a28:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a2c:	10c00e17 	ldw	r3,56(r2)
+ 8032a30:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a34:	10c00f15 	stw	r3,60(r2)
+
+
+      switch (tp->t_state) 
+ 8032a38:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a3c:	10800217 	ldw	r2,8(r2)
+ 8032a40:	10c001e0 	cmpeqi	r3,r2,7
+ 8032a44:	18001a1e 	bne	r3,zero,8032ab0 <tcp_input+0x1a60>
+ 8032a48:	10c00208 	cmpgei	r3,r2,8
+ 8032a4c:	1800031e 	bne	r3,zero,8032a5c <tcp_input+0x1a0c>
+ 8032a50:	108001a0 	cmpeqi	r2,r2,6
+ 8032a54:	1000061e 	bne	r2,zero,8032a70 <tcp_input+0x1a20>
+ 8032a58:	00003606 	br	8032b34 <tcp_input+0x1ae4>
+ 8032a5c:	10c00220 	cmpeqi	r3,r2,8
+ 8032a60:	1800221e 	bne	r3,zero,8032aec <tcp_input+0x1a9c>
+ 8032a64:	108002a0 	cmpeqi	r2,r2,10
+ 8032a68:	1000271e 	bne	r2,zero,8032b08 <tcp_input+0x1ab8>
+ 8032a6c:	00003106 	br	8032b34 <tcp_input+0x1ae4>
+       * In FIN_WAIT_1 STATE in addition to the processing
+       * for the ESTABLISHED state if our FIN is now acknowledged
+       * then enter FIN_WAIT_2.
+       */
+      case TCPS_FIN_WAIT_1:
+         if (ourfinisacked) 
+ 8032a70:	e0bff817 	ldw	r2,-32(fp)
+ 8032a74:	10002a26 	beq	r2,zero,8032b20 <tcp_input+0x1ad0>
+             * data, then closing user can proceed.
+             * Starting the timer is contrary to the
+             * specification, but if we don't get a FIN
+             * we'll hang forever.
+             */
+            if (so->so_state & SS_CANTRCVMORE) 
+ 8032a78:	e0bffa17 	ldw	r2,-24(fp)
+ 8032a7c:	1080088b 	ldhu	r2,34(r2)
+ 8032a80:	10bfffcc 	andi	r2,r2,65535
+ 8032a84:	1080080c 	andi	r2,r2,32
+ 8032a88:	10000526 	beq	r2,zero,8032aa0 <tcp_input+0x1a50>
+            {
+               soisdisconnected(so);
+ 8032a8c:	e13ffa17 	ldw	r4,-24(fp)
+ 8032a90:	802f3840 	call	802f384 <soisdisconnected>
+               tp->t_timer[TCPT_2MSL] = tcp_maxidle;
+ 8032a94:	d0e08917 	ldw	r3,-32220(gp)
+ 8032a98:	e0bffc17 	ldw	r2,-16(fp)
+ 8032a9c:	10c00615 	stw	r3,24(r2)
+            }
+            tp->t_state = TCPS_FIN_WAIT_2;
+ 8032aa0:	e0bffc17 	ldw	r2,-16(fp)
+ 8032aa4:	00c00244 	movi	r3,9
+ 8032aa8:	10c00215 	stw	r3,8(r2)
+         }
+         break;
+ 8032aac:	00001c06 	br	8032b20 <tcp_input+0x1ad0>
+       * the ESTABLISHED state if the ACK acknowledges our FIN
+       * then enter the TIME-WAIT state, otherwise ignore
+       * the segment.
+       */
+      case TCPS_CLOSING:
+         if (ourfinisacked) 
+ 8032ab0:	e0bff817 	ldw	r2,-32(fp)
+ 8032ab4:	10001c26 	beq	r2,zero,8032b28 <tcp_input+0x1ad8>
+         {
+            tp->t_state = TCPS_TIME_WAIT;
+ 8032ab8:	e0bffc17 	ldw	r2,-16(fp)
+ 8032abc:	00c00284 	movi	r3,10
+ 8032ac0:	10c00215 	stw	r3,8(r2)
+            tcp_canceltimers(tp);
+ 8032ac4:	e13ffc17 	ldw	r4,-16(fp)
+ 8032ac8:	80355640 	call	8035564 <tcp_canceltimers>
+            tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+ 8032acc:	d0a01b17 	ldw	r2,-32660(gp)
+ 8032ad0:	1085883a 	add	r2,r2,r2
+ 8032ad4:	1007883a 	mov	r3,r2
+ 8032ad8:	e0bffc17 	ldw	r2,-16(fp)
+ 8032adc:	10c00615 	stw	r3,24(r2)
+            soisdisconnected(so);
+ 8032ae0:	e13ffa17 	ldw	r4,-24(fp)
+ 8032ae4:	802f3840 	call	802f384 <soisdisconnected>
+         }
+         break;
+ 8032ae8:	00000f06 	br	8032b28 <tcp_input+0x1ad8>
+       * and/or to be acked, as well as for the ack of our FIN.
+       * If our FIN is now acknowledged, delete the TCB,
+       * enter the closed state and return.
+       */
+      case TCPS_LAST_ACK:
+         if (ourfinisacked) 
+ 8032aec:	e0bff817 	ldw	r2,-32(fp)
+ 8032af0:	10000f26 	beq	r2,zero,8032b30 <tcp_input+0x1ae0>
+         {
+            SETTP(tp, tcp_close(tp));
+ 8032af4:	e13ffc17 	ldw	r4,-16(fp)
+ 8032af8:	80350e80 	call	80350e8 <tcp_close>
+            GOTO_DROP;
+ 8032afc:	00816644 	movi	r2,1433
+ 8032b00:	d0a08715 	stw	r2,-32228(gp)
+ 8032b04:	0001bd06 	br	80331fc <tcp_input+0x21ac>
+       * In TIME_WAIT state the only thing that should arrive
+       * is a retransmission of the remote FIN.  Acknowledge
+       * it and restart the finack timer.
+       */
+      case TCPS_TIME_WAIT:
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+ 8032b08:	d0a01b17 	ldw	r2,-32660(gp)
+ 8032b0c:	1085883a 	add	r2,r2,r2
+ 8032b10:	1007883a 	mov	r3,r2
+ 8032b14:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b18:	10c00615 	stw	r3,24(r2)
+         goto dropafterack;
+ 8032b1c:	00016706 	br	80330bc <tcp_input+0x206c>
+         break;
+ 8032b20:	0001883a 	nop
+ 8032b24:	00000306 	br	8032b34 <tcp_input+0x1ae4>
+         break;
+ 8032b28:	0001883a 	nop
+ 8032b2c:	00000106 	br	8032b34 <tcp_input+0x1ae4>
+         break;
+ 8032b30:	0001883a 	nop
+step6:
+   /*
+    * Update window information.
+    * Don't look at window if no ACK: TAC's send garbage on first SYN.
+    */
+   if ((tiflags & TH_ACK) &&
+ 8032b34:	e0bffb17 	ldw	r2,-20(fp)
+ 8032b38:	1080040c 	andi	r2,r2,16
+ 8032b3c:	10004226 	beq	r2,zero,8032c48 <tcp_input+0x1bf8>
+       /*
+        * Altera Niche Stack Nios port modification:
+        * Add parenthesis to remove implicit order of operation
+        * & possible build warnings.
+        */
+       (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq &&
+ 8032b40:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b44:	10c01117 	ldw	r3,68(r2)
+ 8032b48:	e0bff017 	ldw	r2,-64(fp)
+ 8032b4c:	10800617 	ldw	r2,24(r2)
+ 8032b50:	1885c83a 	sub	r2,r3,r2
+   if ((tiflags & TH_ACK) &&
+ 8032b54:	10001416 	blt	r2,zero,8032ba8 <tcp_input+0x1b58>
+       (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq &&
+ 8032b58:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b5c:	10c01117 	ldw	r3,68(r2)
+ 8032b60:	e0bff017 	ldw	r2,-64(fp)
+ 8032b64:	10800617 	ldw	r2,24(r2)
+ 8032b68:	1880371e 	bne	r3,r2,8032c48 <tcp_input+0x1bf8>
+       (SEQ_LT(tp->snd_wl2, ti->ti_ack) ||
+ 8032b6c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b70:	10c01217 	ldw	r3,72(r2)
+ 8032b74:	e0bff017 	ldw	r2,-64(fp)
+ 8032b78:	10800717 	ldw	r2,28(r2)
+ 8032b7c:	1885c83a 	sub	r2,r3,r2
+       (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq &&
+ 8032b80:	10000916 	blt	r2,zero,8032ba8 <tcp_input+0x1b58>
+       ((tp->snd_wl2 == ti->ti_ack) && (rx_win > tp->snd_wnd)))))) 
+ 8032b84:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b88:	10c01217 	ldw	r3,72(r2)
+ 8032b8c:	e0bff017 	ldw	r2,-64(fp)
+ 8032b90:	10800717 	ldw	r2,28(r2)
+       (SEQ_LT(tp->snd_wl2, ti->ti_ack) ||
+ 8032b94:	18802c1e 	bne	r3,r2,8032c48 <tcp_input+0x1bf8>
+       ((tp->snd_wl2 == ti->ti_ack) && (rx_win > tp->snd_wnd)))))) 
+ 8032b98:	e0bffc17 	ldw	r2,-16(fp)
+ 8032b9c:	10c01417 	ldw	r3,80(r2)
+ 8032ba0:	e0bfed17 	ldw	r2,-76(fp)
+ 8032ba4:	1880282e 	bgeu	r3,r2,8032c48 <tcp_input+0x1bf8>
+   {
+      /* keep track of pure window updates */
+      if ((ti->ti_len == 0) &&
+ 8032ba8:	e0bff017 	ldw	r2,-64(fp)
+ 8032bac:	1080028b 	ldhu	r2,10(r2)
+ 8032bb0:	10bfffcc 	andi	r2,r2,65535
+ 8032bb4:	10000e1e 	bne	r2,zero,8032bf0 <tcp_input+0x1ba0>
+          (tp->snd_wl2 == ti->ti_ack) &&
+ 8032bb8:	e0bffc17 	ldw	r2,-16(fp)
+ 8032bbc:	10c01217 	ldw	r3,72(r2)
+ 8032bc0:	e0bff017 	ldw	r2,-64(fp)
+ 8032bc4:	10800717 	ldw	r2,28(r2)
+      if ((ti->ti_len == 0) &&
+ 8032bc8:	1880091e 	bne	r3,r2,8032bf0 <tcp_input+0x1ba0>
+          (rx_win > tp->snd_wnd))
+ 8032bcc:	e0bffc17 	ldw	r2,-16(fp)
+ 8032bd0:	10c01417 	ldw	r3,80(r2)
+          (tp->snd_wl2 == ti->ti_ack) &&
+ 8032bd4:	e0bfed17 	ldw	r2,-76(fp)
+ 8032bd8:	1880052e 	bgeu	r3,r2,8032bf0 <tcp_input+0x1ba0>
+      {
+         tcpstat.tcps_rcvwinupd++;
+ 8032bdc:	008201b4 	movhi	r2,2054
+ 8032be0:	10b8d117 	ldw	r2,-7356(r2)
+ 8032be4:	10c00044 	addi	r3,r2,1
+ 8032be8:	008201b4 	movhi	r2,2054
+ 8032bec:	10f8d115 	stw	r3,-7356(r2)
+      }
+      tp->snd_wnd = rx_win;
+ 8032bf0:	e0bffc17 	ldw	r2,-16(fp)
+ 8032bf4:	e0ffed17 	ldw	r3,-76(fp)
+ 8032bf8:	10c01415 	stw	r3,80(r2)
+      tp->snd_wl1 = ti->ti_seq;
+ 8032bfc:	e0bff017 	ldw	r2,-64(fp)
+ 8032c00:	10c00617 	ldw	r3,24(r2)
+ 8032c04:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c08:	10c01115 	stw	r3,68(r2)
+      tp->snd_wl2 = ti->ti_ack;
+ 8032c0c:	e0bff017 	ldw	r2,-64(fp)
+ 8032c10:	10c00717 	ldw	r3,28(r2)
+ 8032c14:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c18:	10c01215 	stw	r3,72(r2)
+      if (tp->snd_wnd > tp->max_sndwnd)
+ 8032c1c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c20:	10801417 	ldw	r2,80(r2)
+ 8032c24:	e0fffc17 	ldw	r3,-16(fp)
+ 8032c28:	18c02317 	ldw	r3,140(r3)
+ 8032c2c:	1880042e 	bgeu	r3,r2,8032c40 <tcp_input+0x1bf0>
+         tp->max_sndwnd = tp->snd_wnd;
+ 8032c30:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c34:	10c01417 	ldw	r3,80(r2)
+ 8032c38:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c3c:	10c02315 	stw	r3,140(r2)
+      needoutput = 1;
+ 8032c40:	00800044 	movi	r2,1
+ 8032c44:	e0bff715 	stw	r2,-36(fp)
+   }
+
+   /*
+    * Process segments with URG.
+    */
+   if ((tiflags & TH_URG) && ti->ti_urp &&
+ 8032c48:	e0bffb17 	ldw	r2,-20(fp)
+ 8032c4c:	1080080c 	andi	r2,r2,32
+ 8032c50:	10005626 	beq	r2,zero,8032dac <tcp_input+0x1d5c>
+ 8032c54:	e0bff017 	ldw	r2,-64(fp)
+ 8032c58:	1080098b 	ldhu	r2,38(r2)
+ 8032c5c:	10bfffcc 	andi	r2,r2,65535
+ 8032c60:	10005226 	beq	r2,zero,8032dac <tcp_input+0x1d5c>
+       TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+ 8032c64:	e0bffc17 	ldw	r2,-16(fp)
+ 8032c68:	10800217 	ldw	r2,8(r2)
+   if ((tiflags & TH_URG) && ti->ti_urp &&
+ 8032c6c:	10800288 	cmpgei	r2,r2,10
+ 8032c70:	10004e1e 	bne	r2,zero,8032dac <tcp_input+0x1d5c>
+       * This is a kludge, but if we receive and accept
+       * random urgent pointers, we'll crash in
+       * soreceive.  It's hard to imagine someone
+       * actually wanting to send this much urgent data.
+       */
+      if (ti->ti_urp + so->so_rcv.sb_cc > SB_MAX) 
+ 8032c74:	e0bff017 	ldw	r2,-64(fp)
+ 8032c78:	1080098b 	ldhu	r2,38(r2)
+ 8032c7c:	10ffffcc 	andi	r3,r2,65535
+ 8032c80:	e0bffa17 	ldw	r2,-24(fp)
+ 8032c84:	10800a17 	ldw	r2,40(r2)
+ 8032c88:	1885883a 	add	r2,r3,r2
+ 8032c8c:	10900070 	cmpltui	r2,r2,16385
+ 8032c90:	1000071e 	bne	r2,zero,8032cb0 <tcp_input+0x1c60>
+      {
+         ti->ti_urp = 0;         /* XXX */
+ 8032c94:	e0bff017 	ldw	r2,-64(fp)
+ 8032c98:	1000098d 	sth	zero,38(r2)
+         tiflags &= ~TH_URG;     /* XXX */
+ 8032c9c:	e0fffb17 	ldw	r3,-20(fp)
+ 8032ca0:	00bff7c4 	movi	r2,-33
+ 8032ca4:	1884703a 	and	r2,r3,r2
+ 8032ca8:	e0bffb15 	stw	r2,-20(fp)
+         goto dodata;         /* XXX */
+ 8032cac:	00004d06 	br	8032de4 <tcp_input+0x1d94>
+       * of urgent data.  We continue, however,
+       * to consider it to indicate the first octet
+       * of data past the urgent section
+       * as the original spec states.
+       */
+      if (SEQ_GT(ti->ti_seq+ti->ti_urp, tp->rcv_up)) 
+ 8032cb0:	e0bff017 	ldw	r2,-64(fp)
+ 8032cb4:	10c00617 	ldw	r3,24(r2)
+ 8032cb8:	e0bff017 	ldw	r2,-64(fp)
+ 8032cbc:	1080098b 	ldhu	r2,38(r2)
+ 8032cc0:	10bfffcc 	andi	r2,r2,65535
+ 8032cc4:	1887883a 	add	r3,r3,r2
+ 8032cc8:	e0bffc17 	ldw	r2,-16(fp)
+ 8032ccc:	10801717 	ldw	r2,92(r2)
+ 8032cd0:	1885c83a 	sub	r2,r3,r2
+ 8032cd4:	0080250e 	bge	zero,r2,8032d6c <tcp_input+0x1d1c>
+      {
+         tp->rcv_up = ti->ti_seq + ti->ti_urp;
+ 8032cd8:	e0bff017 	ldw	r2,-64(fp)
+ 8032cdc:	10c00617 	ldw	r3,24(r2)
+ 8032ce0:	e0bff017 	ldw	r2,-64(fp)
+ 8032ce4:	1080098b 	ldhu	r2,38(r2)
+ 8032ce8:	10bfffcc 	andi	r2,r2,65535
+ 8032cec:	1887883a 	add	r3,r3,r2
+ 8032cf0:	e0bffc17 	ldw	r2,-16(fp)
+ 8032cf4:	10c01715 	stw	r3,92(r2)
+         so->so_oobmark = so->so_rcv.sb_cc +
+ 8032cf8:	e0bffa17 	ldw	r2,-24(fp)
+ 8032cfc:	10c00a17 	ldw	r3,40(r2)
+         (tp->rcv_up - tp->rcv_nxt) - 1;
+ 8032d00:	e0bffc17 	ldw	r2,-16(fp)
+ 8032d04:	11001717 	ldw	r4,92(r2)
+ 8032d08:	e0bffc17 	ldw	r2,-16(fp)
+ 8032d0c:	10801617 	ldw	r2,88(r2)
+ 8032d10:	2085c83a 	sub	r2,r4,r2
+         so->so_oobmark = so->so_rcv.sb_cc +
+ 8032d14:	1885883a 	add	r2,r3,r2
+         (tp->rcv_up - tp->rcv_nxt) - 1;
+ 8032d18:	10ffffc4 	addi	r3,r2,-1
+         so->so_oobmark = so->so_rcv.sb_cc +
+ 8032d1c:	e0bffa17 	ldw	r2,-24(fp)
+ 8032d20:	10c01a15 	stw	r3,104(r2)
+         if (so->so_oobmark == 0)
+ 8032d24:	e0bffa17 	ldw	r2,-24(fp)
+ 8032d28:	10801a17 	ldw	r2,104(r2)
+ 8032d2c:	1000061e 	bne	r2,zero,8032d48 <tcp_input+0x1cf8>
+            so->so_state |= SS_RCVATMARK;
+ 8032d30:	e0bffa17 	ldw	r2,-24(fp)
+ 8032d34:	1080088b 	ldhu	r2,34(r2)
+ 8032d38:	10801014 	ori	r2,r2,64
+ 8032d3c:	1007883a 	mov	r3,r2
+ 8032d40:	e0bffa17 	ldw	r2,-24(fp)
+ 8032d44:	10c0088d 	sth	r3,34(r2)
+         sohasoutofband(so);
+ 8032d48:	e13ffa17 	ldw	r4,-24(fp)
+ 8032d4c:	802f12c0 	call	802f12c <sohasoutofband>
+         tp->t_oobflags &= ~(TCPOOB_HAVEDATA | TCPOOB_HADDATA);
+ 8032d50:	e0bffc17 	ldw	r2,-16(fp)
+ 8032d54:	10c02403 	ldbu	r3,144(r2)
+ 8032d58:	00bfff04 	movi	r2,-4
+ 8032d5c:	1884703a 	and	r2,r3,r2
+ 8032d60:	1007883a 	mov	r3,r2
+ 8032d64:	e0bffc17 	ldw	r2,-16(fp)
+ 8032d68:	10c02405 	stb	r3,144(r2)
+       * Remove out of band data so doesn't get presented to user.
+       * This can happen independent of advancing the URG pointer,
+       * but if two URG's are pending at once, some out-of-band
+       * data may creep in... ick.
+       */
+      if ( (ti->ti_urp <= ti->ti_len)
+ 8032d6c:	e0bff017 	ldw	r2,-64(fp)
+ 8032d70:	1100098b 	ldhu	r4,38(r2)
+ 8032d74:	e0bff017 	ldw	r2,-64(fp)
+ 8032d78:	10c0028b 	ldhu	r3,10(r2)
+ 8032d7c:	20bfffcc 	andi	r2,r4,65535
+ 8032d80:	18ffffcc 	andi	r3,r3,65535
+ 8032d84:	18801436 	bltu	r3,r2,8032dd8 <tcp_input+0x1d88>
+#ifdef SO_OOBINLINE
+       && (so->so_options & SO_OOBINLINE) == 0
+ 8032d88:	e0bffa17 	ldw	r2,-24(fp)
+ 8032d8c:	10800417 	ldw	r2,16(r2)
+ 8032d90:	1080400c 	andi	r2,r2,256
+ 8032d94:	1000101e 	bne	r2,zero,8032dd8 <tcp_input+0x1d88>
+#endif
+       )
+      {
+         tcp_pulloutofband(so, ti, m);
+ 8032d98:	e1bfe417 	ldw	r6,-112(fp)
+ 8032d9c:	e17ff017 	ldw	r5,-64(fp)
+ 8032da0:	e13ffa17 	ldw	r4,-24(fp)
+ 8032da4:	80333ec0 	call	80333ec <tcp_pulloutofband>
+      if ( (ti->ti_urp <= ti->ti_len)
+ 8032da8:	00000b06 	br	8032dd8 <tcp_input+0x1d88>
+      /*
+       * If no out of band data is expected,
+       * pull receive urgent pointer along
+       * with the receive window.
+       */
+   if (SEQ_GT(tp->rcv_nxt, tp->rcv_up))
+ 8032dac:	e0bffc17 	ldw	r2,-16(fp)
+ 8032db0:	10c01617 	ldw	r3,88(r2)
+ 8032db4:	e0bffc17 	ldw	r2,-16(fp)
+ 8032db8:	10801717 	ldw	r2,92(r2)
+ 8032dbc:	1885c83a 	sub	r2,r3,r2
+ 8032dc0:	0080070e 	bge	zero,r2,8032de0 <tcp_input+0x1d90>
+      tp->rcv_up = tp->rcv_nxt;
+ 8032dc4:	e0bffc17 	ldw	r2,-16(fp)
+ 8032dc8:	10c01617 	ldw	r3,88(r2)
+ 8032dcc:	e0bffc17 	ldw	r2,-16(fp)
+ 8032dd0:	10c01715 	stw	r3,92(r2)
+ 8032dd4:	00000306 	br	8032de4 <tcp_input+0x1d94>
+      if ( (ti->ti_urp <= ti->ti_len)
+ 8032dd8:	0001883a 	nop
+ 8032ddc:	00000106 	br	8032de4 <tcp_input+0x1d94>
+dodata:                       /* XXX */
+ 8032de0:	0001883a 	nop
+    * This process logically involves adjusting tp->rcv_wnd as data
+    * is presented to the user (this happens in tcp_usrreq.c,
+    * case PRU_RCVD).  If a FIN has already been received on this
+    * connection then we just ignore the text.
+    */
+   if ((ti->ti_len || (tiflags&TH_FIN)) &&
+ 8032de4:	e0bff017 	ldw	r2,-64(fp)
+ 8032de8:	1080028b 	ldhu	r2,10(r2)
+ 8032dec:	10bfffcc 	andi	r2,r2,65535
+ 8032df0:	1000031e 	bne	r2,zero,8032e00 <tcp_input+0x1db0>
+ 8032df4:	e0bffb17 	ldw	r2,-20(fp)
+ 8032df8:	1080004c 	andi	r2,r2,1
+ 8032dfc:	10005a26 	beq	r2,zero,8032f68 <tcp_input+0x1f18>
+       TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+ 8032e00:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e04:	10800217 	ldw	r2,8(r2)
+   if ((ti->ti_len || (tiflags&TH_FIN)) &&
+ 8032e08:	10800288 	cmpgei	r2,r2,10
+ 8032e0c:	1000561e 	bne	r2,zero,8032f68 <tcp_input+0x1f18>
+   {
+
+      /* Do the common segment reassembly case inline */
+      if((ti->ti_seq == tp->rcv_nxt) &&
+ 8032e10:	e0bff017 	ldw	r2,-64(fp)
+ 8032e14:	10c00617 	ldw	r3,24(r2)
+ 8032e18:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e1c:	10801617 	ldw	r2,88(r2)
+ 8032e20:	1880331e 	bne	r3,r2,8032ef0 <tcp_input+0x1ea0>
+         (tp->seg_next == (struct tcpiphdr *)(tp) ) &&
+ 8032e24:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e28:	10800017 	ldw	r2,0(r2)
+      if((ti->ti_seq == tp->rcv_nxt) &&
+ 8032e2c:	e0fffc17 	ldw	r3,-16(fp)
+ 8032e30:	18802f1e 	bne	r3,r2,8032ef0 <tcp_input+0x1ea0>
+         (tp->t_state == TCPS_ESTABLISHED))
+ 8032e34:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e38:	10800217 	ldw	r2,8(r2)
+         (tp->seg_next == (struct tcpiphdr *)(tp) ) &&
+ 8032e3c:	10800118 	cmpnei	r2,r2,4
+ 8032e40:	10002b1e 	bne	r2,zero,8032ef0 <tcp_input+0x1ea0>
+         else
+         {
+            tp->t_flags |= TF_ACKNOW;
+         }
+#else    /* not DO_DELAY_ACKS */
+            tp->t_flags |= TF_ACKNOW;
+ 8032e44:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e48:	10800b0b 	ldhu	r2,44(r2)
+ 8032e4c:	10800054 	ori	r2,r2,1
+ 8032e50:	1007883a 	mov	r3,r2
+ 8032e54:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e58:	10c00b0d 	sth	r3,44(r2)
+#endif   /* DO_DELAY_ACKS */
+
+         tp->rcv_nxt += ti->ti_len;
+ 8032e5c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e60:	10c01617 	ldw	r3,88(r2)
+ 8032e64:	e0bff017 	ldw	r2,-64(fp)
+ 8032e68:	1080028b 	ldhu	r2,10(r2)
+ 8032e6c:	10bfffcc 	andi	r2,r2,65535
+ 8032e70:	1887883a 	add	r3,r3,r2
+ 8032e74:	e0bffc17 	ldw	r2,-16(fp)
+ 8032e78:	10c01615 	stw	r3,88(r2)
+         tiflags = ti->ti_flags & TH_FIN;
+ 8032e7c:	e0bff017 	ldw	r2,-64(fp)
+ 8032e80:	10800843 	ldbu	r2,33(r2)
+ 8032e84:	10803fcc 	andi	r2,r2,255
+ 8032e88:	1080004c 	andi	r2,r2,1
+ 8032e8c:	e0bffb15 	stw	r2,-20(fp)
+         tcpstat.tcps_rcvpack++;
+ 8032e90:	008201b4 	movhi	r2,2054
+ 8032e94:	10b8be17 	ldw	r2,-7432(r2)
+ 8032e98:	10c00044 	addi	r3,r2,1
+ 8032e9c:	008201b4 	movhi	r2,2054
+ 8032ea0:	10f8be15 	stw	r3,-7432(r2)
+         tcpstat.tcps_rcvbyte += ti->ti_len;
+ 8032ea4:	008201b4 	movhi	r2,2054
+ 8032ea8:	10f8bf17 	ldw	r3,-7428(r2)
+ 8032eac:	e0bff017 	ldw	r2,-64(fp)
+ 8032eb0:	1080028b 	ldhu	r2,10(r2)
+ 8032eb4:	10bfffcc 	andi	r2,r2,65535
+ 8032eb8:	1887883a 	add	r3,r3,r2
+ 8032ebc:	008201b4 	movhi	r2,2054
+ 8032ec0:	10f8bf15 	stw	r3,-7428(r2)
+         sbappend(&so->so_rcv, (m));
+ 8032ec4:	e0bffa17 	ldw	r2,-24(fp)
+ 8032ec8:	10800a04 	addi	r2,r2,40
+ 8032ecc:	e17fe417 	ldw	r5,-112(fp)
+ 8032ed0:	1009883a 	mov	r4,r2
+ 8032ed4:	802fafc0 	call	802fafc <sbappend>
+         sorwakeup(so);
+ 8032ed8:	e0bffa17 	ldw	r2,-24(fp)
+ 8032edc:	10800a04 	addi	r2,r2,40
+ 8032ee0:	100b883a 	mov	r5,r2
+ 8032ee4:	e13ffa17 	ldw	r4,-24(fp)
+ 8032ee8:	802f94c0 	call	802f94c <sbwakeup>
+ 8032eec:	00000b06 	br	8032f1c <tcp_input+0x1ecc>
+#endif /* TCP_SACK */
+      }
+      else     /* received out of sequence segment */
+      {
+         /* Drop it in the reassmbly queue */
+         tiflags = tcp_reass(tp, ti, m);
+ 8032ef0:	e1bfe417 	ldw	r6,-112(fp)
+ 8032ef4:	e17ff017 	ldw	r5,-64(fp)
+ 8032ef8:	e13ffc17 	ldw	r4,-16(fp)
+ 8032efc:	8030c600 	call	8030c60 <tcp_reass>
+ 8032f00:	e0bffb15 	stw	r2,-20(fp)
+         tp->t_flags |= TF_ACKNOW;
+ 8032f04:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f08:	10800b0b 	ldhu	r2,44(r2)
+ 8032f0c:	10800054 	ori	r2,r2,1
+ 8032f10:	1007883a 	mov	r3,r2
+ 8032f14:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f18:	10c00b0d 	sth	r3,44(r2)
+      /*
+       * Note the amount of data that peer has sent into
+       * our window, in order to estimate the sender's
+       * buffer size.
+       */
+      len = (int)(so->so_rcv.sb_hiwat - (tp->rcv_adv - tp->rcv_nxt));
+ 8032f1c:	e0bffa17 	ldw	r2,-24(fp)
+ 8032f20:	10c00b17 	ldw	r3,44(r2)
+ 8032f24:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f28:	11001617 	ldw	r4,88(r2)
+ 8032f2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f30:	10801917 	ldw	r2,100(r2)
+ 8032f34:	2085c83a 	sub	r2,r4,r2
+ 8032f38:	1885883a 	add	r2,r3,r2
+ 8032f3c:	e0bfe615 	stw	r2,-104(fp)
+      if (len > (int)tp->max_rcvd)
+ 8032f40:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f44:	10802217 	ldw	r2,136(r2)
+ 8032f48:	1007883a 	mov	r3,r2
+ 8032f4c:	e0bfe617 	ldw	r2,-104(fp)
+ 8032f50:	18800b0e 	bge	r3,r2,8032f80 <tcp_input+0x1f30>
+         tp->max_rcvd = (u_short)len;
+ 8032f54:	e0bfe617 	ldw	r2,-104(fp)
+ 8032f58:	10ffffcc 	andi	r3,r2,65535
+ 8032f5c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f60:	10c02215 	stw	r3,136(r2)
+      if (len > (int)tp->max_rcvd)
+ 8032f64:	00000606 	br	8032f80 <tcp_input+0x1f30>
+      }
+#endif   /* TCP_ZEROCOPY */
+   } 
+   else
+   {
+      m_freem(m);
+ 8032f68:	e13fe417 	ldw	r4,-112(fp)
+ 8032f6c:	8029cfc0 	call	8029cfc <m_freem>
+      tiflags &= ~TH_FIN;
+ 8032f70:	e0fffb17 	ldw	r3,-20(fp)
+ 8032f74:	00bfff84 	movi	r2,-2
+ 8032f78:	1884703a 	and	r2,r3,r2
+ 8032f7c:	e0bffb15 	stw	r2,-20(fp)
+
+   /*
+    * If FIN is received ACK the FIN and let the user know
+    * that the connection is closing.
+    */
+   if (tiflags & TH_FIN) 
+ 8032f80:	e0bffb17 	ldw	r2,-20(fp)
+ 8032f84:	1080004c 	andi	r2,r2,1
+ 8032f88:	10003e26 	beq	r2,zero,8033084 <tcp_input+0x2034>
+   {
+      if (TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+ 8032f8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8032f90:	10800217 	ldw	r2,8(r2)
+ 8032f94:	10800288 	cmpgei	r2,r2,10
+ 8032f98:	10000d1e 	bne	r2,zero,8032fd0 <tcp_input+0x1f80>
+      {
+         socantrcvmore(so);
+ 8032f9c:	e13ffa17 	ldw	r4,-24(fp)
+ 8032fa0:	802f84c0 	call	802f84c <socantrcvmore>
+         tp->t_flags |= TF_ACKNOW;
+ 8032fa4:	e0bffc17 	ldw	r2,-16(fp)
+ 8032fa8:	10800b0b 	ldhu	r2,44(r2)
+ 8032fac:	10800054 	ori	r2,r2,1
+ 8032fb0:	1007883a 	mov	r3,r2
+ 8032fb4:	e0bffc17 	ldw	r2,-16(fp)
+ 8032fb8:	10c00b0d 	sth	r3,44(r2)
+         tp->rcv_nxt++;
+ 8032fbc:	e0bffc17 	ldw	r2,-16(fp)
+ 8032fc0:	10801617 	ldw	r2,88(r2)
+ 8032fc4:	10c00044 	addi	r3,r2,1
+ 8032fc8:	e0bffc17 	ldw	r2,-16(fp)
+ 8032fcc:	10c01615 	stw	r3,88(r2)
+      }
+      switch (tp->t_state) 
+ 8032fd0:	e0bffc17 	ldw	r2,-16(fp)
+ 8032fd4:	10800217 	ldw	r2,8(r2)
+ 8032fd8:	10bfff44 	addi	r2,r2,-3
+ 8032fdc:	10c00228 	cmpgeui	r3,r2,8
+ 8032fe0:	1800291e 	bne	r3,zero,8033088 <tcp_input+0x2038>
+ 8032fe4:	100690ba 	slli	r3,r2,2
+ 8032fe8:	008200f4 	movhi	r2,2051
+ 8032fec:	1885883a 	add	r2,r3,r2
+ 8032ff0:	108bfe17 	ldw	r2,12280(r2)
+ 8032ff4:	1000683a 	jmp	r2
+ 8032ff8:	08033018 	cmpnei	zero,at,3264
+ 8032ffc:	08033018 	cmpnei	zero,at,3264
+ 8033000:	08033088 	cmpgei	zero,at,3266
+ 8033004:	08033028 	cmpgeui	zero,at,3264
+ 8033008:	08033088 	cmpgei	zero,at,3266
+ 803300c:	08033088 	cmpgei	zero,at,3266
+ 8033010:	08033038 	rdprs	zero,at,3264
+ 8033014:	0803306c 	andhi	zero,at,3265
+       * In SYN_RECEIVED and ESTABLISHED STATES
+       * enter the CLOSE_WAIT state.
+       */
+      case TCPS_SYN_RECEIVED:
+      case TCPS_ESTABLISHED:
+         tp->t_state = TCPS_CLOSE_WAIT;
+ 8033018:	e0bffc17 	ldw	r2,-16(fp)
+ 803301c:	00c00144 	movi	r3,5
+ 8033020:	10c00215 	stw	r3,8(r2)
+         break;
+ 8033024:	00001806 	br	8033088 <tcp_input+0x2038>
+       /*
+       * If still in FIN_WAIT_1 STATE FIN has not been acked so
+       * enter the CLOSING state.
+       */
+      case TCPS_FIN_WAIT_1:
+         tp->t_state = TCPS_CLOSING;
+ 8033028:	e0bffc17 	ldw	r2,-16(fp)
+ 803302c:	00c001c4 	movi	r3,7
+ 8033030:	10c00215 	stw	r3,8(r2)
+         break;
+ 8033034:	00001406 	br	8033088 <tcp_input+0x2038>
+       * In FIN_WAIT_2 state enter the TIME_WAIT state,
+       * starting the time-wait timer, turning off the other 
+       * standard timers.
+       */
+      case TCPS_FIN_WAIT_2:
+         tp->t_state = TCPS_TIME_WAIT;
+ 8033038:	e0bffc17 	ldw	r2,-16(fp)
+ 803303c:	00c00284 	movi	r3,10
+ 8033040:	10c00215 	stw	r3,8(r2)
+         tcp_canceltimers(tp);
+ 8033044:	e13ffc17 	ldw	r4,-16(fp)
+ 8033048:	80355640 	call	8035564 <tcp_canceltimers>
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+ 803304c:	d0a01b17 	ldw	r2,-32660(gp)
+ 8033050:	1085883a 	add	r2,r2,r2
+ 8033054:	1007883a 	mov	r3,r2
+ 8033058:	e0bffc17 	ldw	r2,-16(fp)
+ 803305c:	10c00615 	stw	r3,24(r2)
+         soisdisconnected(so);
+ 8033060:	e13ffa17 	ldw	r4,-24(fp)
+ 8033064:	802f3840 	call	802f384 <soisdisconnected>
+         break;
+ 8033068:	00000706 	br	8033088 <tcp_input+0x2038>
+
+      /*
+       * In TIME_WAIT state restart the 2 MSL time_wait timer.
+       */
+      case TCPS_TIME_WAIT:
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+ 803306c:	d0a01b17 	ldw	r2,-32660(gp)
+ 8033070:	1085883a 	add	r2,r2,r2
+ 8033074:	1007883a 	mov	r3,r2
+ 8033078:	e0bffc17 	ldw	r2,-16(fp)
+ 803307c:	10c00615 	stw	r3,24(r2)
+         break;
+ 8033080:	00000106 	br	8033088 <tcp_input+0x2038>
+      }
+   }
+ 8033084:	0001883a 	nop
+    ostate, tp, &tcp_saveti);
+#endif
+   /*
+    * Return any desired output.
+    */
+   if (needoutput || (tp->t_flags & TF_ACKNOW))
+ 8033088:	e0bff717 	ldw	r2,-36(fp)
+ 803308c:	1000051e 	bne	r2,zero,80330a4 <tcp_input+0x2054>
+ 8033090:	e0bffc17 	ldw	r2,-16(fp)
+ 8033094:	10800b0b 	ldhu	r2,44(r2)
+ 8033098:	10bfffcc 	andi	r2,r2,65535
+ 803309c:	1080004c 	andi	r2,r2,1
+ 80330a0:	10006626 	beq	r2,zero,803323c <tcp_input+0x21ec>
+      (void) tcp_output(tp);
+ 80330a4:	e13ffc17 	ldw	r4,-16(fp)
+ 80330a8:	80338940 	call	8033894 <tcp_output>
+   return;
+ 80330ac:	00006306 	br	803323c <tcp_input+0x21ec>
+            goto dropafterack;
+ 80330b0:	0001883a 	nop
+ 80330b4:	00000106 	br	80330bc <tcp_input+0x206c>
+            goto dropafterack;
+ 80330b8:	0001883a 	nop
+dropafterack:
+   /*
+    * Generate an ACK dropping incoming segment if it occupies
+    * sequence space, where the ACK reflects our state.
+    */
+   if (tiflags & TH_RST)
+ 80330bc:	e0bffb17 	ldw	r2,-20(fp)
+ 80330c0:	1080010c 	andi	r2,r2,4
+ 80330c4:	10000326 	beq	r2,zero,80330d4 <tcp_input+0x2084>
+      GOTO_DROP;
+ 80330c8:	0081a904 	movi	r2,1700
+ 80330cc:	d0a08715 	stw	r2,-32228(gp)
+ 80330d0:	00004a06 	br	80331fc <tcp_input+0x21ac>
+   m_freem (m);
+ 80330d4:	e13fe417 	ldw	r4,-112(fp)
+ 80330d8:	8029cfc0 	call	8029cfc <m_freem>
+   tp->t_flags |= TF_ACKNOW;
+ 80330dc:	e0bffc17 	ldw	r2,-16(fp)
+ 80330e0:	10800b0b 	ldhu	r2,44(r2)
+ 80330e4:	10800054 	ori	r2,r2,1
+ 80330e8:	1007883a 	mov	r3,r2
+ 80330ec:	e0bffc17 	ldw	r2,-16(fp)
+ 80330f0:	10c00b0d 	sth	r3,44(r2)
+   (void) tcp_output (tp);
+ 80330f4:	e13ffc17 	ldw	r4,-16(fp)
+ 80330f8:	80338940 	call	8033894 <tcp_output>
+   return;
+ 80330fc:	00005406 	br	8033250 <tcp_input+0x2200>
+
+dropwithreset:
+   TCP_MIB_INC(tcpInErrs);    /* keep MIB stats */
+ 8033100:	008201b4 	movhi	r2,2054
+ 8033104:	10b88317 	ldw	r2,-7668(r2)
+ 8033108:	10c00044 	addi	r3,r2,1
+ 803310c:	008201b4 	movhi	r2,2054
+ 8033110:	10f88315 	stw	r3,-7668(r2)
+   if (om) 
+ 8033114:	e0bffd17 	ldw	r2,-12(fp)
+ 8033118:	10000326 	beq	r2,zero,8033128 <tcp_input+0x20d8>
+   {
+      (void) m_free(om);
+ 803311c:	e13ffd17 	ldw	r4,-12(fp)
+ 8033120:	8029bf80 	call	8029bf8 <m_free>
+      om = 0;
+ 8033124:	e03ffd15 	stw	zero,-12(fp)
+   }
+
+   /* Don't reset resets */
+   if (tiflags & TH_RST)
+ 8033128:	e0bffb17 	ldw	r2,-20(fp)
+ 803312c:	1080010c 	andi	r2,r2,4
+ 8033130:	10000326 	beq	r2,zero,8033140 <tcp_input+0x20f0>
+      GOTO_DROP;
+ 8033134:	0081ad04 	movi	r2,1716
+ 8033138:	d0a08715 	stw	r2,-32228(gp)
+ 803313c:	00002f06 	br	80331fc <tcp_input+0x21ac>
+    * Generate a RST, dropping incoming segment.
+    * Make ACK acceptable to originator of segment.
+    * Don't bother to respond if destination was broadcast.
+    */
+#ifdef IP_V4
+   if (in_broadcast(ti->ti_dst.s_addr))
+ 8033140:	e0bff017 	ldw	r2,-64(fp)
+ 8033144:	10800417 	ldw	r2,16(r2)
+ 8033148:	1009883a 	mov	r4,r2
+ 803314c:	802abe00 	call	802abe0 <in_broadcast>
+ 8033150:	10000326 	beq	r2,zero,8033160 <tcp_input+0x2110>
+      GOTO_DROP;
+ 8033154:	0081af44 	movi	r2,1725
+ 8033158:	d0a08715 	stw	r2,-32228(gp)
+ 803315c:	00002706 	br	80331fc <tcp_input+0x21ac>
+      IP6CPY(&(m->pkt->ip6_hdr->ip_src), &ip6_src);
+      IP6CPY(&(m->pkt->ip6_hdr->ip_dest), &ip6_dst);
+   }
+#endif   /* IP_V6 */
+
+   if (tiflags & TH_ACK)
+ 8033160:	e0bffb17 	ldw	r2,-20(fp)
+ 8033164:	1080040c 	andi	r2,r2,16
+ 8033168:	10000c26 	beq	r2,zero,803319c <tcp_input+0x214c>
+      tcp_respond (tp, ti, (tcp_seq)0, ti->ti_ack, TH_RST, m);
+ 803316c:	e0bff017 	ldw	r2,-64(fp)
+ 8033170:	10c00717 	ldw	r3,28(r2)
+ 8033174:	e0bfe417 	ldw	r2,-112(fp)
+ 8033178:	d8800115 	stw	r2,4(sp)
+ 803317c:	00800104 	movi	r2,4
+ 8033180:	d8800015 	stw	r2,0(sp)
+ 8033184:	180f883a 	mov	r7,r3
+ 8033188:	000d883a 	mov	r6,zero
+ 803318c:	e17ff017 	ldw	r5,-64(fp)
+ 8033190:	e13ffc17 	ldw	r4,-16(fp)
+ 8033194:	8034b480 	call	8034b48 <tcp_respond>
+ 8033198:	00001306 	br	80331e8 <tcp_input+0x2198>
+   else
+   {
+      if (tiflags & TH_SYN)
+ 803319c:	e0bffb17 	ldw	r2,-20(fp)
+ 80331a0:	1080008c 	andi	r2,r2,2
+ 80331a4:	10000526 	beq	r2,zero,80331bc <tcp_input+0x216c>
+         ti->ti_seq++;
+ 80331a8:	e0bff017 	ldw	r2,-64(fp)
+ 80331ac:	10800617 	ldw	r2,24(r2)
+ 80331b0:	10c00044 	addi	r3,r2,1
+ 80331b4:	e0bff017 	ldw	r2,-64(fp)
+ 80331b8:	10c00615 	stw	r3,24(r2)
+      tcp_respond(tp, ti, ti->ti_seq, (tcp_seq)0, TH_RST|TH_ACK, m);
+ 80331bc:	e0bff017 	ldw	r2,-64(fp)
+ 80331c0:	10c00617 	ldw	r3,24(r2)
+ 80331c4:	e0bfe417 	ldw	r2,-112(fp)
+ 80331c8:	d8800115 	stw	r2,4(sp)
+ 80331cc:	00800504 	movi	r2,20
+ 80331d0:	d8800015 	stw	r2,0(sp)
+ 80331d4:	000f883a 	mov	r7,zero
+ 80331d8:	180d883a 	mov	r6,r3
+ 80331dc:	e17ff017 	ldw	r5,-64(fp)
+ 80331e0:	e13ffc17 	ldw	r4,-16(fp)
+ 80331e4:	8034b480 	call	8034b48 <tcp_respond>
+   }
+   /* destroy temporarily created socket */
+   if (dropsocket)
+ 80331e8:	e0bff617 	ldw	r2,-40(fp)
+ 80331ec:	10001526 	beq	r2,zero,8033244 <tcp_input+0x21f4>
+      (void) soabort(so);
+ 80331f0:	e13ffa17 	ldw	r4,-24(fp)
+ 80331f4:	802d6fc0 	call	802d6fc <soabort>
+   return;
+ 80331f8:	00001206 	br	8033244 <tcp_input+0x21f4>
+
+drop:
+   if (om)
+ 80331fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8033200:	10000226 	beq	r2,zero,803320c <tcp_input+0x21bc>
+      (void) m_free(om);
+ 8033204:	e13ffd17 	ldw	r4,-12(fp)
+ 8033208:	8029bf80 	call	8029bf8 <m_free>
+#ifdef DO_TCPTRACE
+   if (tp && (tp->t_inpcb->inp_socket->so_options & SO_DEBUG))
+      tcp_trace("drop: state %d, tcpcb: %x, saveti: %x",
+    ostate, tp, &tcp_saveti);
+#endif
+   m_freem(m);
+ 803320c:	e13fe417 	ldw	r4,-112(fp)
+ 8033210:	8029cfc0 	call	8029cfc <m_freem>
+   /* destroy temporarily created socket */
+   if (dropsocket)
+ 8033214:	e0bff617 	ldw	r2,-40(fp)
+ 8033218:	10000c26 	beq	r2,zero,803324c <tcp_input+0x21fc>
+      (void) soabort(so);
+ 803321c:	e13ffa17 	ldw	r4,-24(fp)
+ 8033220:	802d6fc0 	call	802d6fc <soabort>
+   return;
+ 8033224:	0001883a 	nop
+ 8033228:	00000806 	br	803324c <tcp_input+0x21fc>
+            return;
+ 803322c:	0001883a 	nop
+ 8033230:	00000706 	br	8033250 <tcp_input+0x2200>
+         return;
+ 8033234:	0001883a 	nop
+ 8033238:	00000506 	br	8033250 <tcp_input+0x2200>
+   return;
+ 803323c:	0001883a 	nop
+ 8033240:	00000306 	br	8033250 <tcp_input+0x2200>
+   return;
+ 8033244:	0001883a 	nop
+ 8033248:	00000106 	br	8033250 <tcp_input+0x2200>
+   return;
+ 803324c:	0001883a 	nop
+}
+ 8033250:	e037883a 	mov	sp,fp
+ 8033254:	dfc00117 	ldw	ra,4(sp)
+ 8033258:	df000017 	ldw	fp,0(sp)
+ 803325c:	dec00204 	addi	sp,sp,8
+ 8033260:	f800283a 	ret
+
+08033264 <tcp_dooptions>:
+
+void
+tcp_dooptions(struct tcpcb * tp, 
+   struct mbuf *  om,
+   struct tcpiphdr * ti)
+{
+ 8033264:	defff504 	addi	sp,sp,-44
+ 8033268:	dfc00a15 	stw	ra,40(sp)
+ 803326c:	df000915 	stw	fp,36(sp)
+ 8033270:	df000904 	addi	fp,sp,36
+ 8033274:	e13ff915 	stw	r4,-28(fp)
+ 8033278:	e17ff815 	stw	r5,-32(fp)
+ 803327c:	e1bff715 	stw	r6,-36(fp)
+   u_char * cp;   /* pointer into option buffer */
+   int   opt;     /* current option code */
+   int   optlen;  /* length of current option */
+   int   cnt;     /* byte count left in header */
+   struct socket * so = tp->t_inpcb->inp_socket;
+ 8033280:	e0bff917 	ldw	r2,-28(fp)
+ 8033284:	10800d17 	ldw	r2,52(r2)
+ 8033288:	10800817 	ldw	r2,32(r2)
+ 803328c:	e0bffc15 	stw	r2,-16(fp)
+#ifdef TCP_TIMESTAMP
+   int   gotstamp = FALSE;    /* TRUE if we got a timestamp */
+#endif   /* TCP_TIMESTAMP */
+
+
+   cp = mtod(om, u_char *);
+ 8033290:	e0bff817 	ldw	r2,-32(fp)
+ 8033294:	10800317 	ldw	r2,12(r2)
+ 8033298:	e0bfff15 	stw	r2,-4(fp)
+   cnt = om->m_len;
+ 803329c:	e0bff817 	ldw	r2,-32(fp)
+ 80332a0:	10800217 	ldw	r2,8(r2)
+ 80332a4:	e0bffd15 	stw	r2,-12(fp)
+   for (; cnt > 0; cnt -= optlen, cp += optlen) 
+ 80332a8:	00004206 	br	80333b4 <tcp_dooptions+0x150>
+   {
+      opt = cp[0];
+ 80332ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80332b0:	10800003 	ldbu	r2,0(r2)
+ 80332b4:	10803fcc 	andi	r2,r2,255
+ 80332b8:	e0bffb15 	stw	r2,-20(fp)
+      if (opt == TCPOPT_EOL)
+ 80332bc:	e0bffb17 	ldw	r2,-20(fp)
+ 80332c0:	10003f26 	beq	r2,zero,80333c0 <tcp_dooptions+0x15c>
+         break;
+      if (opt == TCPOPT_NOP)
+ 80332c4:	e0bffb17 	ldw	r2,-20(fp)
+ 80332c8:	10800058 	cmpnei	r2,r2,1
+ 80332cc:	1000031e 	bne	r2,zero,80332dc <tcp_dooptions+0x78>
+         optlen = 1;
+ 80332d0:	00800044 	movi	r2,1
+ 80332d4:	e0bffe15 	stw	r2,-8(fp)
+ 80332d8:	00000706 	br	80332f8 <tcp_dooptions+0x94>
+      else 
+      {
+         optlen = cp[1];
+ 80332dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80332e0:	10800044 	addi	r2,r2,1
+ 80332e4:	10800003 	ldbu	r2,0(r2)
+ 80332e8:	10803fcc 	andi	r2,r2,255
+ 80332ec:	e0bffe15 	stw	r2,-8(fp)
+         if (optlen <= 0)
+ 80332f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80332f4:	0080340e 	bge	zero,r2,80333c8 <tcp_dooptions+0x164>
+            break;
+      }
+
+      switch (opt) 
+ 80332f8:	e0bffb17 	ldw	r2,-20(fp)
+ 80332fc:	10800098 	cmpnei	r2,r2,2
+ 8033300:	10001f1e 	bne	r2,zero,8033380 <tcp_dooptions+0x11c>
+      {
+      case TCPOPT_MAXSEG:
+      {
+         u_short mssval;
+         if (optlen != 4)
+ 8033304:	e0bffe17 	ldw	r2,-8(fp)
+ 8033308:	10800120 	cmpeqi	r2,r2,4
+ 803330c:	10001e26 	beq	r2,zero,8033388 <tcp_dooptions+0x124>
+            continue;
+         if (!(ti->ti_flags & TH_SYN))    /* MSS only on SYN */
+ 8033310:	e0bff717 	ldw	r2,-36(fp)
+ 8033314:	10800843 	ldbu	r2,33(r2)
+ 8033318:	10803fcc 	andi	r2,r2,255
+ 803331c:	1080008c 	andi	r2,r2,2
+ 8033320:	10001b26 	beq	r2,zero,8033390 <tcp_dooptions+0x12c>
+            continue;
+         mssval = *(u_short *)(cp + 2);
+ 8033324:	e0bfff17 	ldw	r2,-4(fp)
+ 8033328:	1080008b 	ldhu	r2,2(r2)
+ 803332c:	e0bffa8d 	sth	r2,-22(fp)
+         mssval = ntohs(mssval);
+ 8033330:	e0bffa8b 	ldhu	r2,-22(fp)
+ 8033334:	1004d23a 	srli	r2,r2,8
+ 8033338:	1007883a 	mov	r3,r2
+ 803333c:	e0bffa8b 	ldhu	r2,-22(fp)
+ 8033340:	1004923a 	slli	r2,r2,8
+ 8033344:	1884b03a 	or	r2,r3,r2
+ 8033348:	e0bffa8d 	sth	r2,-22(fp)
+         tp->t_maxseg = (u_short)MIN(mssval, (u_short)tcp_mss(so));
+ 803334c:	e13ffc17 	ldw	r4,-16(fp)
+ 8033350:	803379c0 	call	803379c <tcp_mss>
+ 8033354:	1007883a 	mov	r3,r2
+ 8033358:	e0bffa8b 	ldhu	r2,-22(fp)
+ 803335c:	18ffffcc 	andi	r3,r3,65535
+ 8033360:	1880032e 	bgeu	r3,r2,8033370 <tcp_dooptions+0x10c>
+ 8033364:	e13ffc17 	ldw	r4,-16(fp)
+ 8033368:	803379c0 	call	803379c <tcp_mss>
+ 803336c:	00000106 	br	8033374 <tcp_dooptions+0x110>
+ 8033370:	e0bffa8b 	ldhu	r2,-22(fp)
+ 8033374:	e0fff917 	ldw	r3,-28(fp)
+ 8033378:	18800a0d 	sth	r2,40(r3)
+         break;
+ 803337c:	00000506 	br	8033394 <tcp_dooptions+0x130>
+         }
+         break;
+#endif   /* TCP_TIMESTAMP */
+
+      default:
+         break;
+ 8033380:	0001883a 	nop
+ 8033384:	00000306 	br	8033394 <tcp_dooptions+0x130>
+            continue;
+ 8033388:	0001883a 	nop
+ 803338c:	00000106 	br	8033394 <tcp_dooptions+0x130>
+            continue;
+ 8033390:	0001883a 	nop
+   for (; cnt > 0; cnt -= optlen, cp += optlen) 
+ 8033394:	e0fffd17 	ldw	r3,-12(fp)
+ 8033398:	e0bffe17 	ldw	r2,-8(fp)
+ 803339c:	1885c83a 	sub	r2,r3,r2
+ 80333a0:	e0bffd15 	stw	r2,-12(fp)
+ 80333a4:	e0bffe17 	ldw	r2,-8(fp)
+ 80333a8:	e0ffff17 	ldw	r3,-4(fp)
+ 80333ac:	1885883a 	add	r2,r3,r2
+ 80333b0:	e0bfff15 	stw	r2,-4(fp)
+ 80333b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80333b8:	00bfbc16 	blt	zero,r2,80332ac <tcp_dooptions+0x48>
+ 80333bc:	00000306 	br	80333cc <tcp_dooptions+0x168>
+         break;
+ 80333c0:	0001883a 	nop
+ 80333c4:	00000106 	br	80333cc <tcp_dooptions+0x168>
+            break;
+ 80333c8:	0001883a 	nop
+      }
+   }
+   (void) m_free(om);
+ 80333cc:	e13ff817 	ldw	r4,-32(fp)
+ 80333d0:	8029bf80 	call	8029bf8 <m_free>
+      if(!gotstamp)
+         tp->t_flags &= ~TF_TIMESTAMP;
+   }
+#endif /* TCP_TIMESTAMP */
+
+   return;
+ 80333d4:	0001883a 	nop
+}
+ 80333d8:	e037883a 	mov	sp,fp
+ 80333dc:	dfc00117 	ldw	ra,4(sp)
+ 80333e0:	df000017 	ldw	fp,0(sp)
+ 80333e4:	dec00204 	addi	sp,sp,8
+ 80333e8:	f800283a 	ret
+
+080333ec <tcp_pulloutofband>:
+
+void
+tcp_pulloutofband(struct socket * so, 
+   struct tcpiphdr * ti,
+   struct mbuf *  m)
+{
+ 80333ec:	defff804 	addi	sp,sp,-32
+ 80333f0:	dfc00715 	stw	ra,28(sp)
+ 80333f4:	df000615 	stw	fp,24(sp)
+ 80333f8:	df000604 	addi	fp,sp,24
+ 80333fc:	e13ffc15 	stw	r4,-16(fp)
+ 8033400:	e17ffb15 	stw	r5,-20(fp)
+ 8033404:	e1bffa15 	stw	r6,-24(fp)
+   int   cnt   =  ti->ti_urp  -  1;
+ 8033408:	e0bffb17 	ldw	r2,-20(fp)
+ 803340c:	1080098b 	ldhu	r2,38(r2)
+ 8033410:	10bfffcc 	andi	r2,r2,65535
+ 8033414:	10bfffc4 	addi	r2,r2,-1
+ 8033418:	e0bfff15 	stw	r2,-4(fp)
+
+   /**m = dtom(ti);**/
+   while (cnt >= 0) 
+ 803341c:	00003206 	br	80334e8 <tcp_pulloutofband+0xfc>
+   {
+      if (m->m_len > (unsigned)cnt) 
+ 8033420:	e0bffa17 	ldw	r2,-24(fp)
+ 8033424:	10800217 	ldw	r2,8(r2)
+ 8033428:	e0ffff17 	ldw	r3,-4(fp)
+ 803342c:	1880242e 	bgeu	r3,r2,80334c0 <tcp_pulloutofband+0xd4>
+      {
+         char *   cp =  mtod(m,  char *) +  cnt;
+ 8033430:	e0bffa17 	ldw	r2,-24(fp)
+ 8033434:	10c00317 	ldw	r3,12(r2)
+ 8033438:	e0bfff17 	ldw	r2,-4(fp)
+ 803343c:	1885883a 	add	r2,r3,r2
+ 8033440:	e0bffe15 	stw	r2,-8(fp)
+         struct tcpcb * tp =  sototcpcb(so);
+ 8033444:	e0bffc17 	ldw	r2,-16(fp)
+ 8033448:	10800117 	ldw	r2,4(r2)
+ 803344c:	10800917 	ldw	r2,36(r2)
+ 8033450:	e0bffd15 	stw	r2,-12(fp)
+
+         tp->t_iobc = *cp;
+ 8033454:	e0bffe17 	ldw	r2,-8(fp)
+ 8033458:	10c00003 	ldbu	r3,0(r2)
+ 803345c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033460:	10c02445 	stb	r3,145(r2)
+         tp->t_oobflags |= TCPOOB_HAVEDATA;
+ 8033464:	e0bffd17 	ldw	r2,-12(fp)
+ 8033468:	10802403 	ldbu	r2,144(r2)
+ 803346c:	10800054 	ori	r2,r2,1
+ 8033470:	1007883a 	mov	r3,r2
+ 8033474:	e0bffd17 	ldw	r2,-12(fp)
+ 8033478:	10c02405 	stb	r3,144(r2)
+         MEMCPY(cp, cp+1, (unsigned)(m->m_len - cnt - 1));
+ 803347c:	e0bffe17 	ldw	r2,-8(fp)
+ 8033480:	11000044 	addi	r4,r2,1
+ 8033484:	e0bffa17 	ldw	r2,-24(fp)
+ 8033488:	10c00217 	ldw	r3,8(r2)
+ 803348c:	e0bfff17 	ldw	r2,-4(fp)
+ 8033490:	1885c83a 	sub	r2,r3,r2
+ 8033494:	10bfffc4 	addi	r2,r2,-1
+ 8033498:	100d883a 	mov	r6,r2
+ 803349c:	200b883a 	mov	r5,r4
+ 80334a0:	e13ffe17 	ldw	r4,-8(fp)
+ 80334a4:	80086b80 	call	80086b8 <memcpy>
+         m->m_len--;
+ 80334a8:	e0bffa17 	ldw	r2,-24(fp)
+ 80334ac:	10800217 	ldw	r2,8(r2)
+ 80334b0:	10ffffc4 	addi	r3,r2,-1
+ 80334b4:	e0bffa17 	ldw	r2,-24(fp)
+ 80334b8:	10c00215 	stw	r3,8(r2)
+         return;
+ 80334bc:	00001106 	br	8033504 <tcp_pulloutofband+0x118>
+      }
+      cnt -= m->m_len;
+ 80334c0:	e0ffff17 	ldw	r3,-4(fp)
+ 80334c4:	e0bffa17 	ldw	r2,-24(fp)
+ 80334c8:	10800217 	ldw	r2,8(r2)
+ 80334cc:	1885c83a 	sub	r2,r3,r2
+ 80334d0:	e0bfff15 	stw	r2,-4(fp)
+      m = m->m_next;
+ 80334d4:	e0bffa17 	ldw	r2,-24(fp)
+ 80334d8:	10800617 	ldw	r2,24(r2)
+ 80334dc:	e0bffa15 	stw	r2,-24(fp)
+      if (m == 0)
+ 80334e0:	e0bffa17 	ldw	r2,-24(fp)
+ 80334e4:	10000326 	beq	r2,zero,80334f4 <tcp_pulloutofband+0x108>
+   while (cnt >= 0) 
+ 80334e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80334ec:	103fcc0e 	bge	r2,zero,8033420 <tcp_pulloutofband+0x34>
+ 80334f0:	00000106 	br	80334f8 <tcp_pulloutofband+0x10c>
+         break;
+ 80334f4:	0001883a 	nop
+   }
+   panic("tcp_pulloutofband");
+ 80334f8:	01020174 	movhi	r4,2053
+ 80334fc:	212a9d04 	addi	r4,r4,-21900
+ 8033500:	80271780 	call	8027178 <panic>
+}
+ 8033504:	e037883a 	mov	sp,fp
+ 8033508:	dfc00117 	ldw	ra,4(sp)
+ 803350c:	df000017 	ldw	fp,0(sp)
+ 8033510:	dec00204 	addi	sp,sp,8
+ 8033514:	f800283a 	ret
+
+08033518 <tcp_xmit_timer>:
+ * RETURNS: 
+ */
+
+void
+tcp_xmit_timer(struct tcpcb * tp)
+{
+ 8033518:	defffb04 	addi	sp,sp,-20
+ 803351c:	dfc00415 	stw	ra,16(sp)
+ 8033520:	df000315 	stw	fp,12(sp)
+ 8033524:	df000304 	addi	fp,sp,12
+ 8033528:	e13ffd15 	stw	r4,-12(fp)
+   int delta;
+   int rtt;
+
+#ifdef NPDEBUG
+   if(tp->t_rttick == 0){ dtrap(); return; }
+ 803352c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033530:	10801e17 	ldw	r2,120(r2)
+ 8033534:	1000021e 	bne	r2,zero,8033540 <tcp_xmit_timer+0x28>
+ 8033538:	8028cd40 	call	8028cd4 <dtrap>
+ 803353c:	00008006 	br	8033740 <tcp_xmit_timer+0x228>
+#endif
+
+   tcpstat.tcps_rttupdated++;
+ 8033540:	008201b4 	movhi	r2,2054
+ 8033544:	10b8ab17 	ldw	r2,-7508(r2)
+ 8033548:	10c00044 	addi	r3,r2,1
+ 803354c:	008201b4 	movhi	r2,2054
+ 8033550:	10f8ab15 	stw	r3,-7508(r2)
+
+   /* get  this rtt. Convert from cticks to TCP slow ticks */
+   rtt = (int)((cticks - tp->t_rttick) / (TPS/2));
+ 8033554:	d0e07d17 	ldw	r3,-32268(gp)
+ 8033558:	e0bffd17 	ldw	r2,-12(fp)
+ 803355c:	10801e17 	ldw	r2,120(r2)
+ 8033560:	1885c83a 	sub	r2,r3,r2
+ 8033564:	01400c84 	movi	r5,50
+ 8033568:	1009883a 	mov	r4,r2
+ 803356c:	800cff80 	call	800cff8 <__udivsi3>
+ 8033570:	e0bffe15 	stw	r2,-8(fp)
+   if(tp->t_srtt != 0)
+ 8033574:	e0bffd17 	ldw	r2,-12(fp)
+ 8033578:	10802017 	ldw	r2,128(r2)
+ 803357c:	10004426 	beq	r2,zero,8033690 <tcp_xmit_timer+0x178>
+   {
+      if(rtt == 0)      /* fast path for small round trip */
+ 8033580:	e0bffe17 	ldw	r2,-8(fp)
+ 8033584:	1000131e 	bne	r2,zero,80335d4 <tcp_xmit_timer+0xbc>
+      {
+         /* if either the rtt or varience is over 1, reduce it. */
+         if(tp->t_srtt > 1)
+ 8033588:	e0bffd17 	ldw	r2,-12(fp)
+ 803358c:	10802017 	ldw	r2,128(r2)
+ 8033590:	10800090 	cmplti	r2,r2,2
+ 8033594:	1000051e 	bne	r2,zero,80335ac <tcp_xmit_timer+0x94>
+            tp->t_srtt--;
+ 8033598:	e0bffd17 	ldw	r2,-12(fp)
+ 803359c:	10802017 	ldw	r2,128(r2)
+ 80335a0:	10ffffc4 	addi	r3,r2,-1
+ 80335a4:	e0bffd17 	ldw	r2,-12(fp)
+ 80335a8:	10c02015 	stw	r3,128(r2)
+         if(tp->t_rttvar > 1)
+ 80335ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80335b0:	10802117 	ldw	r2,132(r2)
+ 80335b4:	10800090 	cmplti	r2,r2,2
+ 80335b8:	1000421e 	bne	r2,zero,80336c4 <tcp_xmit_timer+0x1ac>
+            tp->t_rttvar--;
+ 80335bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80335c0:	10802117 	ldw	r2,132(r2)
+ 80335c4:	10ffffc4 	addi	r3,r2,-1
+ 80335c8:	e0bffd17 	ldw	r2,-12(fp)
+ 80335cc:	10c02115 	stw	r3,132(r2)
+ 80335d0:	00003c06 	br	80336c4 <tcp_xmit_timer+0x1ac>
+       * The following magic is equivalent
+       * to the smoothing algorithm in rfc793
+       * with an alpha of .875
+       * (srtt = rtt/8 + srtt*7/8 in fixed point).
+       */
+      delta = ((rtt - 1) << 2) - (int)(tp->t_srtt >> 3);
+ 80335d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80335d8:	10bfffc4 	addi	r2,r2,-1
+ 80335dc:	100690ba 	slli	r3,r2,2
+ 80335e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80335e4:	10802017 	ldw	r2,128(r2)
+ 80335e8:	1005d0fa 	srai	r2,r2,3
+ 80335ec:	1885c83a 	sub	r2,r3,r2
+ 80335f0:	e0bfff15 	stw	r2,-4(fp)
+      if ((tp->t_srtt += delta) <= 0)
+ 80335f4:	e0bffd17 	ldw	r2,-12(fp)
+ 80335f8:	10c02017 	ldw	r3,128(r2)
+ 80335fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8033600:	1887883a 	add	r3,r3,r2
+ 8033604:	e0bffd17 	ldw	r2,-12(fp)
+ 8033608:	10c02015 	stw	r3,128(r2)
+ 803360c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033610:	10802017 	ldw	r2,128(r2)
+ 8033614:	00800316 	blt	zero,r2,8033624 <tcp_xmit_timer+0x10c>
+         tp->t_srtt = 1;
+ 8033618:	e0bffd17 	ldw	r2,-12(fp)
+ 803361c:	00c00044 	movi	r3,1
+ 8033620:	10c02015 	stw	r3,128(r2)
+       * (scaled by 4).  The following is equivalent
+       * to rfc793 smoothing with an alpha of .75
+       * (rttvar = rttvar*3/4 + |delta| / 4).
+       * This replaces rfc793's wired-in beta.
+       */
+      if (delta < 0)
+ 8033624:	e0bfff17 	ldw	r2,-4(fp)
+ 8033628:	1000030e 	bge	r2,zero,8033638 <tcp_xmit_timer+0x120>
+         delta = -delta;
+ 803362c:	e0bfff17 	ldw	r2,-4(fp)
+ 8033630:	0085c83a 	sub	r2,zero,r2
+ 8033634:	e0bfff15 	stw	r2,-4(fp)
+      delta -= (short)(tp->t_rttvar >> 1);
+ 8033638:	e0bffd17 	ldw	r2,-12(fp)
+ 803363c:	10802117 	ldw	r2,132(r2)
+ 8033640:	1005d07a 	srai	r2,r2,1
+ 8033644:	10bfffcc 	andi	r2,r2,65535
+ 8033648:	10a0001c 	xori	r2,r2,32768
+ 803364c:	10a00004 	addi	r2,r2,-32768
+ 8033650:	e0ffff17 	ldw	r3,-4(fp)
+ 8033654:	1885c83a 	sub	r2,r3,r2
+ 8033658:	e0bfff15 	stw	r2,-4(fp)
+      if ((tp->t_rttvar += delta) <= 0)
+ 803365c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033660:	10c02117 	ldw	r3,132(r2)
+ 8033664:	e0bfff17 	ldw	r2,-4(fp)
+ 8033668:	1887883a 	add	r3,r3,r2
+ 803366c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033670:	10c02115 	stw	r3,132(r2)
+ 8033674:	e0bffd17 	ldw	r2,-12(fp)
+ 8033678:	10802117 	ldw	r2,132(r2)
+ 803367c:	00801116 	blt	zero,r2,80336c4 <tcp_xmit_timer+0x1ac>
+         tp->t_rttvar = 1;
+ 8033680:	e0bffd17 	ldw	r2,-12(fp)
+ 8033684:	00c00044 	movi	r3,1
+ 8033688:	10c02115 	stw	r3,132(r2)
+ 803368c:	00000d06 	br	80336c4 <tcp_xmit_timer+0x1ac>
+       * No rtt measurement yet - use the
+       * unsmoothed rtt.  Set the variance
+       * to half the rtt (so our first
+       * retransmit happens at 2*rtt)
+       */
+      if(rtt < 1)
+ 8033690:	e0bffe17 	ldw	r2,-8(fp)
+ 8033694:	00800216 	blt	zero,r2,80336a0 <tcp_xmit_timer+0x188>
+         rtt = 1;
+ 8033698:	00800044 	movi	r2,1
+ 803369c:	e0bffe15 	stw	r2,-8(fp)
+      tp->t_srtt = rtt << 3;
+ 80336a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80336a4:	100690fa 	slli	r3,r2,3
+ 80336a8:	e0bffd17 	ldw	r2,-12(fp)
+ 80336ac:	10c02015 	stw	r3,128(r2)
+      tp->t_rttvar = rtt << 1;
+ 80336b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80336b4:	1085883a 	add	r2,r2,r2
+ 80336b8:	1007883a 	mov	r3,r2
+ 80336bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80336c0:	10c02115 	stw	r3,132(r2)
+   }
+   tp->t_rttick = 0;       /* clear RT timer */
+ 80336c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80336c8:	10001e15 	stw	zero,120(r2)
+   tp->t_rxtshift = 0;
+ 80336cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80336d0:	10000715 	stw	zero,28(r2)
+   TCPT_RANGESET(tp->t_rxtcur, 
+ 80336d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80336d8:	10802017 	ldw	r2,128(r2)
+ 80336dc:	1007d0ba 	srai	r3,r2,2
+ 80336e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80336e4:	10802117 	ldw	r2,132(r2)
+ 80336e8:	1885883a 	add	r2,r3,r2
+ 80336ec:	1005d07a 	srai	r2,r2,1
+ 80336f0:	10ffffcc 	andi	r3,r2,65535
+ 80336f4:	18e0001c 	xori	r3,r3,32768
+ 80336f8:	18e00004 	addi	r3,r3,-32768
+ 80336fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8033700:	10c00815 	stw	r3,32(r2)
+ 8033704:	e0bffd17 	ldw	r2,-12(fp)
+ 8033708:	10800817 	ldw	r2,32(r2)
+ 803370c:	10800088 	cmpgei	r2,r2,2
+ 8033710:	1000041e 	bne	r2,zero,8033724 <tcp_xmit_timer+0x20c>
+ 8033714:	e0bffd17 	ldw	r2,-12(fp)
+ 8033718:	00c00084 	movi	r3,2
+ 803371c:	10c00815 	stw	r3,32(r2)
+ 8033720:	00000706 	br	8033740 <tcp_xmit_timer+0x228>
+ 8033724:	e0bffd17 	ldw	r2,-12(fp)
+ 8033728:	10800817 	ldw	r2,32(r2)
+ 803372c:	10802050 	cmplti	r2,r2,129
+ 8033730:	1000031e 	bne	r2,zero,8033740 <tcp_xmit_timer+0x228>
+ 8033734:	e0bffd17 	ldw	r2,-12(fp)
+ 8033738:	00c02004 	movi	r3,128
+ 803373c:	10c00815 	stw	r3,32(r2)
+    ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1,
+    TCPTV_MIN, TCPTV_REXMTMAX);
+}
+ 8033740:	e037883a 	mov	sp,fp
+ 8033744:	dfc00117 	ldw	ra,4(sp)
+ 8033748:	df000017 	ldw	fp,0(sp)
+ 803374c:	dec00204 	addi	sp,sp,8
+ 8033750:	f800283a 	ret
+
+08033754 <ip4_tcpmss>:
+
+
+#ifdef IP_V4
+int
+ip4_tcpmss(struct socket * so)
+{
+ 8033754:	defffd04 	addi	sp,sp,-12
+ 8033758:	df000215 	stw	fp,8(sp)
+ 803375c:	df000204 	addi	fp,sp,8
+ 8033760:	e13ffe15 	stw	r4,-8(fp)
+   NET ifp;
+
+   ifp = so->so_pcb->ifp;
+ 8033764:	e0bffe17 	ldw	r2,-8(fp)
+ 8033768:	10800117 	ldw	r2,4(r2)
+ 803376c:	10800a17 	ldw	r2,40(r2)
+ 8033770:	e0bfff15 	stw	r2,-4(fp)
+   return(ifp->n_mtu - (40 + ifp->n_lnh));
+ 8033774:	e0bfff17 	ldw	r2,-4(fp)
+ 8033778:	10c00917 	ldw	r3,36(r2)
+ 803377c:	e0bfff17 	ldw	r2,-4(fp)
+ 8033780:	10800817 	ldw	r2,32(r2)
+ 8033784:	10800a04 	addi	r2,r2,40
+ 8033788:	1885c83a 	sub	r2,r3,r2
+}
+ 803378c:	e037883a 	mov	sp,fp
+ 8033790:	df000017 	ldw	fp,0(sp)
+ 8033794:	dec00104 	addi	sp,sp,4
+ 8033798:	f800283a 	ret
+
+0803379c <tcp_mss>:
+ */
+
+
+int
+tcp_mss(struct socket * so)
+{
+ 803379c:	defffa04 	addi	sp,sp,-24
+ 80337a0:	dfc00515 	stw	ra,20(sp)
+ 80337a4:	df000415 	stw	fp,16(sp)
+ 80337a8:	df000404 	addi	fp,sp,16
+ 80337ac:	e13ffc15 	stw	r4,-16(fp)
+   struct tcpcb * tp;
+#ifdef IP_V6
+   NET  ifp = 0;
+#endif
+
+   if ((so == NULL) ||
+ 80337b0:	e0bffc17 	ldw	r2,-16(fp)
+ 80337b4:	10000726 	beq	r2,zero,80337d4 <tcp_mss+0x38>
+       (so->so_pcb == NULL) ||
+ 80337b8:	e0bffc17 	ldw	r2,-16(fp)
+ 80337bc:	10800117 	ldw	r2,4(r2)
+   if ((so == NULL) ||
+ 80337c0:	10000426 	beq	r2,zero,80337d4 <tcp_mss+0x38>
+       (so->so_pcb->ifp == NULL))
+ 80337c4:	e0bffc17 	ldw	r2,-16(fp)
+ 80337c8:	10800117 	ldw	r2,4(r2)
+ 80337cc:	10800a17 	ldw	r2,40(r2)
+       (so->so_pcb == NULL) ||
+ 80337d0:	1000061e 	bne	r2,zero,80337ec <tcp_mss+0x50>
+   {
+      if (so->so_domain == AF_INET)  /* IPv4 */
+ 80337d4:	e0bffc17 	ldw	r2,-16(fp)
+ 80337d8:	10800517 	ldw	r2,20(r2)
+ 80337dc:	10800098 	cmpnei	r2,r2,2
+ 80337e0:	1000021e 	bne	r2,zero,80337ec <tcp_mss+0x50>
+         return TCP_MSS;            /* user defined */
+ 80337e4:	00816d04 	movi	r2,1460
+ 80337e8:	00002506 	br	8033880 <tcp_mss+0xe4>
+#endif   /* IP_V6 */
+
+
+#ifdef IP_V4   /* Begin messy domain defines */
+#ifndef IP_V6  /* V4 only version */
+   mss = ip4_tcpmss(so);
+ 80337ec:	e13ffc17 	ldw	r4,-16(fp)
+ 80337f0:	80337540 	call	8033754 <ip4_tcpmss>
+ 80337f4:	e0bfff15 	stw	r2,-4(fp)
+#endif         /* end of dual mode */
+#else          /* no IP_v4, assume V6 only */
+      mss = ip6_tcpmss(so, ifp);
+#endif         /* end messy domain defines */
+
+   if (mss > TCP_MSS)    /* check upper limit from compile */
+ 80337f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80337fc:	10816d50 	cmplti	r2,r2,1461
+ 8033800:	1000021e 	bne	r2,zero,803380c <tcp_mss+0x70>
+      mss = TCP_MSS;
+ 8033804:	00816d04 	movi	r2,1460
+ 8033808:	e0bfff15 	stw	r2,-4(fp)
+
+   /* check upper limit which may be set by setsockopt() */
+   inp = (struct inpcb *)so->so_pcb;         /* Map socket to IP cb */
+ 803380c:	e0bffc17 	ldw	r2,-16(fp)
+ 8033810:	10800117 	ldw	r2,4(r2)
+ 8033814:	e0bffe15 	stw	r2,-8(fp)
+   tp = (struct tcpcb *)inp->inp_ppcb;       /* Map IP to TCP cb */
+ 8033818:	e0bffe17 	ldw	r2,-8(fp)
+ 803381c:	10800917 	ldw	r2,36(r2)
+ 8033820:	e0bffd15 	stw	r2,-12(fp)
+   
+   /* has user set max seg? */
+   if (tp->t_flags & TF_MAXSEG)
+ 8033824:	e0bffd17 	ldw	r2,-12(fp)
+ 8033828:	10800b0b 	ldhu	r2,44(r2)
+ 803382c:	10bfffcc 	andi	r2,r2,65535
+ 8033830:	1081000c 	andi	r2,r2,1024
+ 8033834:	10000426 	beq	r2,zero,8033848 <tcp_mss+0xac>
+      return tp->t_maxseg;    /* yup */
+ 8033838:	e0bffd17 	ldw	r2,-12(fp)
+ 803383c:	10800a0b 	ldhu	r2,40(r2)
+ 8033840:	10bfffcc 	andi	r2,r2,65535
+ 8033844:	00000e06 	br	8033880 <tcp_mss+0xe4>
+      
+   if (tp->t_maxseg && (mss > tp->t_maxseg))  /* check tcp's mss */
+ 8033848:	e0bffd17 	ldw	r2,-12(fp)
+ 803384c:	10800a0b 	ldhu	r2,40(r2)
+ 8033850:	10bfffcc 	andi	r2,r2,65535
+ 8033854:	10000926 	beq	r2,zero,803387c <tcp_mss+0xe0>
+ 8033858:	e0bffd17 	ldw	r2,-12(fp)
+ 803385c:	10800a0b 	ldhu	r2,40(r2)
+ 8033860:	10ffffcc 	andi	r3,r2,65535
+ 8033864:	e0bfff17 	ldw	r2,-4(fp)
+ 8033868:	1880040e 	bge	r3,r2,803387c <tcp_mss+0xe0>
+   {
+      mss = tp->t_maxseg;        /* limit new MSS to set MSS */
+ 803386c:	e0bffd17 	ldw	r2,-12(fp)
+ 8033870:	10800a0b 	ldhu	r2,40(r2)
+ 8033874:	10bfffcc 	andi	r2,r2,65535
+ 8033878:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   return mss;
+ 803387c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8033880:	e037883a 	mov	sp,fp
+ 8033884:	dfc00117 	ldw	ra,4(sp)
+ 8033888:	df000017 	ldw	fp,0(sp)
+ 803388c:	dec00204 	addi	sp,sp,8
+ 8033890:	f800283a 	ret
+
+08033894 <tcp_output>:
+ * RETURNS: 0 if OK, else a sockets error code.
+ */
+
+int
+tcp_output(struct tcpcb * tp)
+{
+ 8033894:	deffe804 	addi	sp,sp,-96
+ 8033898:	dfc01715 	stw	ra,92(sp)
+ 803389c:	df001615 	stw	fp,88(sp)
+ 80338a0:	df001604 	addi	fp,sp,88
+ 80338a4:	e13fea15 	stw	r4,-88(fp)
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+ 80338a8:	e0bfea17 	ldw	r2,-88(fp)
+ 80338ac:	10800d17 	ldw	r2,52(r2)
+ 80338b0:	10800817 	ldw	r2,32(r2)
+ 80338b4:	e0bff715 	stw	r2,-36(fp)
+   int   len;
+   long  win;
+   int   off,  flags,   error;
+   struct mbuf *  m;
+   struct tcpiphdr * ti;
+   unsigned optlen = 0;
+ 80338b8:	e03ffb15 	stw	zero,-20(fp)
+    * Determine length of data that should be transmitted,
+    * and flags that will be used.
+    * If there is some data or critical controls (SYN, RST)
+    * to send, then transmit; otherwise, investigate further.
+    */
+   idle = (tp->snd_max == tp->snd_una);
+ 80338bc:	e0bfea17 	ldw	r2,-88(fp)
+ 80338c0:	10c01a17 	ldw	r3,104(r2)
+ 80338c4:	e0bfea17 	ldw	r2,-88(fp)
+ 80338c8:	10800e17 	ldw	r2,56(r2)
+ 80338cc:	1885003a 	cmpeq	r2,r3,r2
+ 80338d0:	10803fcc 	andi	r2,r2,255
+ 80338d4:	e0bff615 	stw	r2,-40(fp)
+
+again:
+   sendalot = 0;
+ 80338d8:	e03ffa15 	stw	zero,-24(fp)
+   off = (int)(tp->snd_nxt - tp->snd_una);
+ 80338dc:	e0bfea17 	ldw	r2,-88(fp)
+ 80338e0:	10c00f17 	ldw	r3,60(r2)
+ 80338e4:	e0bfea17 	ldw	r2,-88(fp)
+ 80338e8:	10800e17 	ldw	r2,56(r2)
+ 80338ec:	1885c83a 	sub	r2,r3,r2
+ 80338f0:	e0bff515 	stw	r2,-44(fp)
+   win = (long)tp->snd_wnd;   /* set basic send window */
+ 80338f4:	e0bfea17 	ldw	r2,-88(fp)
+ 80338f8:	10801417 	ldw	r2,80(r2)
+ 80338fc:	e0bffe15 	stw	r2,-8(fp)
+   if (win > (long)tp->snd_cwnd) /* see if we need congestion control */
+ 8033900:	e0bfea17 	ldw	r2,-88(fp)
+ 8033904:	10801b17 	ldw	r2,108(r2)
+ 8033908:	1007883a 	mov	r3,r2
+ 803390c:	e0bffe17 	ldw	r2,-8(fp)
+ 8033910:	1880060e 	bge	r3,r2,803392c <tcp_output+0x98>
+   {
+      win = (int)(tp->snd_cwnd & ~(ALIGN_TYPE-1)); /* keep data aligned */
+ 8033914:	e0bfea17 	ldw	r2,-88(fp)
+ 8033918:	10801b17 	ldw	r2,108(r2)
+ 803391c:	1007883a 	mov	r3,r2
+ 8033920:	00bfff04 	movi	r2,-4
+ 8033924:	1884703a 	and	r2,r3,r2
+ 8033928:	e0bffe15 	stw	r2,-8(fp)
+    * If in persist timeout with window of 0, send 1 byte.
+    * Otherwise, if window is small but nonzero
+    * and timer expired, we will send what we can
+    * and go to transmit state.
+    */
+   if (tp->t_force) 
+ 803392c:	e0bfea17 	ldw	r2,-88(fp)
+ 8033930:	10800a83 	ldbu	r2,42(r2)
+ 8033934:	10803fcc 	andi	r2,r2,255
+ 8033938:	1080201c 	xori	r2,r2,128
+ 803393c:	10bfe004 	addi	r2,r2,-128
+ 8033940:	10000926 	beq	r2,zero,8033968 <tcp_output+0xd4>
+   {
+      if (win == 0)
+ 8033944:	e0bffe17 	ldw	r2,-8(fp)
+ 8033948:	1000031e 	bne	r2,zero,8033958 <tcp_output+0xc4>
+         win = 1;
+ 803394c:	00800044 	movi	r2,1
+ 8033950:	e0bffe15 	stw	r2,-8(fp)
+ 8033954:	00000406 	br	8033968 <tcp_output+0xd4>
+      else 
+      {
+         tp->t_timer[TCPT_PERSIST] = 0;
+ 8033958:	e0bfea17 	ldw	r2,-88(fp)
+ 803395c:	10000415 	stw	zero,16(r2)
+         tp->t_rxtshift = 0;
+ 8033960:	e0bfea17 	ldw	r2,-88(fp)
+ 8033964:	10000715 	stw	zero,28(r2)
+   }
+   else
+#endif /* TCP_SACK */
+   {
+      /* set length of packets which are not sack resends */
+      len = (int)MIN(so->so_snd.sb_cc, (unsigned)win) - off;
+ 8033968:	e0bff717 	ldw	r2,-36(fp)
+ 803396c:	10801217 	ldw	r2,72(r2)
+ 8033970:	e0fffe17 	ldw	r3,-8(fp)
+ 8033974:	1880012e 	bgeu	r3,r2,803397c <tcp_output+0xe8>
+ 8033978:	1805883a 	mov	r2,r3
+ 803397c:	1007883a 	mov	r3,r2
+ 8033980:	e0bff517 	ldw	r2,-44(fp)
+ 8033984:	1885c83a 	sub	r2,r3,r2
+ 8033988:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   flags = tcp_outflags[tp->t_state];
+ 803398c:	e0bfea17 	ldw	r2,-88(fp)
+ 8033990:	10c00217 	ldw	r3,8(r2)
+ 8033994:	00820174 	movhi	r2,2053
+ 8033998:	1885883a 	add	r2,r3,r2
+ 803399c:	10b20a03 	ldbu	r2,-14296(r2)
+ 80339a0:	10803fcc 	andi	r2,r2,255
+ 80339a4:	e0bffd15 	stw	r2,-12(fp)
+   }
+#else
+   /* If other options not defined this build then don't bother to call bld_options() except 
+    * on SYN packets
+    */
+   if(flags & TH_SYN)
+ 80339a8:	e0bffd17 	ldw	r2,-12(fp)
+ 80339ac:	1080008c 	andi	r2,r2,2
+ 80339b0:	10000926 	beq	r2,zero,80339d8 <tcp_output+0x144>
+   {
+      optlen = bld_options(tp, &tcp_optionbuf[optlen], flags, so);
+ 80339b4:	e0fffb17 	ldw	r3,-20(fp)
+ 80339b8:	d0a08804 	addi	r2,gp,-32224
+ 80339bc:	1885883a 	add	r2,r3,r2
+ 80339c0:	e1fff717 	ldw	r7,-36(fp)
+ 80339c4:	e1bffd17 	ldw	r6,-12(fp)
+ 80339c8:	100b883a 	mov	r5,r2
+ 80339cc:	e13fea17 	ldw	r4,-88(fp)
+ 80339d0:	803492c0 	call	803492c <bld_options>
+ 80339d4:	e0bffb15 	stw	r2,-20(fp)
+   }
+#endif
+
+   if (len < 0)
+ 80339d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80339dc:	1000090e 	bge	r2,zero,8033a04 <tcp_output+0x170>
+       * cancel pending retransmit and pull snd_nxt
+       * back to (closed) window.  We will enter persist
+       * state below.  If the window didn't close completely,
+       * just wait for an ACK.
+       */
+      len = 0;
+ 80339e0:	e03fff15 	stw	zero,-4(fp)
+      if (win == 0) 
+ 80339e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80339e8:	1000061e 	bne	r2,zero,8033a04 <tcp_output+0x170>
+      {
+         tp->t_timer[TCPT_REXMT] = 0;
+ 80339ec:	e0bfea17 	ldw	r2,-88(fp)
+ 80339f0:	10000315 	stw	zero,12(r2)
+         tp->snd_nxt = tp->snd_una;
+ 80339f4:	e0bfea17 	ldw	r2,-88(fp)
+ 80339f8:	10c00e17 	ldw	r3,56(r2)
+ 80339fc:	e0bfea17 	ldw	r2,-88(fp)
+ 8033a00:	10c00f15 	stw	r3,60(r2)
+      }
+   }
+
+   if (len > (int)tp->t_maxseg)
+ 8033a04:	e0bfea17 	ldw	r2,-88(fp)
+ 8033a08:	10800a0b 	ldhu	r2,40(r2)
+ 8033a0c:	10ffffcc 	andi	r3,r2,65535
+ 8033a10:	e0bfff17 	ldw	r2,-4(fp)
+ 8033a14:	1880060e 	bge	r3,r2,8033a30 <tcp_output+0x19c>
+   {
+      len = tp->t_maxseg;
+ 8033a18:	e0bfea17 	ldw	r2,-88(fp)
+ 8033a1c:	10800a0b 	ldhu	r2,40(r2)
+ 8033a20:	10bfffcc 	andi	r2,r2,65535
+ 8033a24:	e0bfff15 	stw	r2,-4(fp)
+      sendalot = 1;
+ 8033a28:	00800044 	movi	r2,1
+ 8033a2c:	e0bffa15 	stw	r2,-24(fp)
+   /* We don't need a pmtu test for IPv6. V6 code limits t_maxseg to
+    * the Path MTU, so the test above the v4 ifdef above covers us.
+    */
+#endif /* IP_V4 */
+
+   if (SEQ_LT(tp->snd_nxt + len, tp->snd_una + so->so_snd.sb_cc))
+ 8033a30:	e0bfea17 	ldw	r2,-88(fp)
+ 8033a34:	10c00f17 	ldw	r3,60(r2)
+ 8033a38:	e0bfff17 	ldw	r2,-4(fp)
+ 8033a3c:	1887883a 	add	r3,r3,r2
+ 8033a40:	e0bfea17 	ldw	r2,-88(fp)
+ 8033a44:	11000e17 	ldw	r4,56(r2)
+ 8033a48:	e0bff717 	ldw	r2,-36(fp)
+ 8033a4c:	10801217 	ldw	r2,72(r2)
+ 8033a50:	2085883a 	add	r2,r4,r2
+ 8033a54:	1885c83a 	sub	r2,r3,r2
+ 8033a58:	1000040e 	bge	r2,zero,8033a6c <tcp_output+0x1d8>
+      flags &= ~TH_FIN;
+ 8033a5c:	e0fffd17 	ldw	r3,-12(fp)
+ 8033a60:	00bfff84 	movi	r2,-2
+ 8033a64:	1884703a 	and	r2,r3,r2
+ 8033a68:	e0bffd15 	stw	r2,-12(fp)
+   win = (long)(sbspace(&so->so_rcv));
+ 8033a6c:	e0bff717 	ldw	r2,-36(fp)
+ 8033a70:	10800b17 	ldw	r2,44(r2)
+ 8033a74:	1007883a 	mov	r3,r2
+ 8033a78:	e0bff717 	ldw	r2,-36(fp)
+ 8033a7c:	10800a17 	ldw	r2,40(r2)
+ 8033a80:	1885c83a 	sub	r2,r3,r2
+ 8033a84:	10000616 	blt	r2,zero,8033aa0 <tcp_output+0x20c>
+ 8033a88:	e0bff717 	ldw	r2,-36(fp)
+ 8033a8c:	10c00b17 	ldw	r3,44(r2)
+ 8033a90:	e0bff717 	ldw	r2,-36(fp)
+ 8033a94:	10800a17 	ldw	r2,40(r2)
+ 8033a98:	1885c83a 	sub	r2,r3,r2
+ 8033a9c:	00000106 	br	8033aa4 <tcp_output+0x210>
+ 8033aa0:	0005883a 	mov	r2,zero
+ 8033aa4:	e0bffe15 	stw	r2,-8(fp)
+   /*
+    * If our state indicates that FIN should be sent
+    * and we have not yet done so, or we're retransmitting the FIN,
+    * then we need to send.
+    */
+   if ((flags & TH_FIN) &&
+ 8033aa8:	e0bffd17 	ldw	r2,-12(fp)
+ 8033aac:	1080004c 	andi	r2,r2,1
+ 8033ab0:	10000d26 	beq	r2,zero,8033ae8 <tcp_output+0x254>
+       (so->so_snd.sb_cc == 0) &&
+ 8033ab4:	e0bff717 	ldw	r2,-36(fp)
+ 8033ab8:	10801217 	ldw	r2,72(r2)
+   if ((flags & TH_FIN) &&
+ 8033abc:	10000a1e 	bne	r2,zero,8033ae8 <tcp_output+0x254>
+       ((tp->t_flags & TF_SENTFIN) == 0 || tp->snd_nxt == tp->snd_una))
+ 8033ac0:	e0bfea17 	ldw	r2,-88(fp)
+ 8033ac4:	10800b0b 	ldhu	r2,44(r2)
+ 8033ac8:	10bfffcc 	andi	r2,r2,65535
+ 8033acc:	1080040c 	andi	r2,r2,16
+       (so->so_snd.sb_cc == 0) &&
+ 8033ad0:	10006626 	beq	r2,zero,8033c6c <tcp_output+0x3d8>
+       ((tp->t_flags & TF_SENTFIN) == 0 || tp->snd_nxt == tp->snd_una))
+ 8033ad4:	e0bfea17 	ldw	r2,-88(fp)
+ 8033ad8:	10c00f17 	ldw	r3,60(r2)
+ 8033adc:	e0bfea17 	ldw	r2,-88(fp)
+ 8033ae0:	10800e17 	ldw	r2,56(r2)
+ 8033ae4:	18806126 	beq	r3,r2,8033c6c <tcp_output+0x3d8>
+      goto send;
+   }
+   /*
+    * Send if we owe peer an ACK.
+    */
+   if (tp->t_flags & TF_ACKNOW)
+ 8033ae8:	e0bfea17 	ldw	r2,-88(fp)
+ 8033aec:	10800b0b 	ldhu	r2,44(r2)
+ 8033af0:	10bfffcc 	andi	r2,r2,65535
+ 8033af4:	1080004c 	andi	r2,r2,1
+ 8033af8:	10005e1e 	bne	r2,zero,8033c74 <tcp_output+0x3e0>
+      goto send;
+   if (flags & (TH_SYN|TH_RST))
+ 8033afc:	e0bffd17 	ldw	r2,-12(fp)
+ 8033b00:	1080018c 	andi	r2,r2,6
+ 8033b04:	10005d1e 	bne	r2,zero,8033c7c <tcp_output+0x3e8>
+      goto send;
+   if (SEQ_GT(tp->snd_up, tp->snd_una))
+ 8033b08:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b0c:	10c01017 	ldw	r3,64(r2)
+ 8033b10:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b14:	10800e17 	ldw	r2,56(r2)
+ 8033b18:	1885c83a 	sub	r2,r3,r2
+ 8033b1c:	00805916 	blt	zero,r2,8033c84 <tcp_output+0x3f0>
+    * If peer's buffer is tiny, then send
+    * when window is at least half open.
+    * If retransmitting (possibly after persist timer forced us
+    * to send into a small window), then must resend.
+    */
+   if (len)
+ 8033b20:	e0bfff17 	ldw	r2,-4(fp)
+ 8033b24:	10002426 	beq	r2,zero,8033bb8 <tcp_output+0x324>
+   {
+      if (len == (int)tp->t_maxseg)
+ 8033b28:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b2c:	10800a0b 	ldhu	r2,40(r2)
+ 8033b30:	10bfffcc 	andi	r2,r2,65535
+ 8033b34:	e0ffff17 	ldw	r3,-4(fp)
+ 8033b38:	18805426 	beq	r3,r2,8033c8c <tcp_output+0x3f8>
+         goto send;
+      if ((idle || tp->t_flags & TF_NODELAY) &&
+ 8033b3c:	e0bff617 	ldw	r2,-40(fp)
+ 8033b40:	1000051e 	bne	r2,zero,8033b58 <tcp_output+0x2c4>
+ 8033b44:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b48:	10800b0b 	ldhu	r2,44(r2)
+ 8033b4c:	10bfffcc 	andi	r2,r2,65535
+ 8033b50:	1080010c 	andi	r2,r2,4
+ 8033b54:	10000626 	beq	r2,zero,8033b70 <tcp_output+0x2dc>
+          len + off >= (int)so->so_snd.sb_cc)
+ 8033b58:	e0ffff17 	ldw	r3,-4(fp)
+ 8033b5c:	e0bff517 	ldw	r2,-44(fp)
+ 8033b60:	1885883a 	add	r2,r3,r2
+ 8033b64:	e0fff717 	ldw	r3,-36(fp)
+ 8033b68:	18c01217 	ldw	r3,72(r3)
+      if ((idle || tp->t_flags & TF_NODELAY) &&
+ 8033b6c:	10c0490e 	bge	r2,r3,8033c94 <tcp_output+0x400>
+      {
+         goto send;
+      }
+      if (tp->t_force)
+ 8033b70:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b74:	10800a83 	ldbu	r2,42(r2)
+ 8033b78:	10803fcc 	andi	r2,r2,255
+ 8033b7c:	1080201c 	xori	r2,r2,128
+ 8033b80:	10bfe004 	addi	r2,r2,-128
+ 8033b84:	1000451e 	bne	r2,zero,8033c9c <tcp_output+0x408>
+         goto send;
+      if (len >= (int)(tp->max_sndwnd / 2))
+ 8033b88:	e0bfea17 	ldw	r2,-88(fp)
+ 8033b8c:	10802317 	ldw	r2,140(r2)
+ 8033b90:	1004d07a 	srli	r2,r2,1
+ 8033b94:	1007883a 	mov	r3,r2
+ 8033b98:	e0bfff17 	ldw	r2,-4(fp)
+ 8033b9c:	10c0410e 	bge	r2,r3,8033ca4 <tcp_output+0x410>
+         goto send;
+      if (SEQ_LT(tp->snd_nxt, tp->snd_max))
+ 8033ba0:	e0bfea17 	ldw	r2,-88(fp)
+ 8033ba4:	10c00f17 	ldw	r3,60(r2)
+ 8033ba8:	e0bfea17 	ldw	r2,-88(fp)
+ 8033bac:	10801a17 	ldw	r2,104(r2)
+ 8033bb0:	1885c83a 	sub	r2,r3,r2
+ 8033bb4:	10003d16 	blt	r2,zero,8033cac <tcp_output+0x418>
+    * known to peer (as advertised window less
+    * next expected input).  If the difference is at least two
+    * max size segments or at least 35% of the maximum possible
+    * window, then want to send a window update to peer.
+    */
+   if (win > 0)
+ 8033bb8:	e0bffe17 	ldw	r2,-8(fp)
+ 8033bbc:	00801c0e 	bge	zero,r2,8033c30 <tcp_output+0x39c>
+   {
+      int   adv   =  (int)win -  (int)(tp->rcv_adv -  tp->rcv_nxt);
+ 8033bc0:	e0bfea17 	ldw	r2,-88(fp)
+ 8033bc4:	10c01917 	ldw	r3,100(r2)
+ 8033bc8:	e0bfea17 	ldw	r2,-88(fp)
+ 8033bcc:	10801617 	ldw	r2,88(r2)
+ 8033bd0:	1885c83a 	sub	r2,r3,r2
+ 8033bd4:	1007883a 	mov	r3,r2
+ 8033bd8:	e0bffe17 	ldw	r2,-8(fp)
+ 8033bdc:	10c5c83a 	sub	r2,r2,r3
+ 8033be0:	e0bff415 	stw	r2,-48(fp)
+
+      if (so->so_rcv.sb_cc == 0 && adv >= (int)(tp->t_maxseg * 2))
+ 8033be4:	e0bff717 	ldw	r2,-36(fp)
+ 8033be8:	10800a17 	ldw	r2,40(r2)
+ 8033bec:	1000071e 	bne	r2,zero,8033c0c <tcp_output+0x378>
+ 8033bf0:	e0bfea17 	ldw	r2,-88(fp)
+ 8033bf4:	10800a0b 	ldhu	r2,40(r2)
+ 8033bf8:	10bfffcc 	andi	r2,r2,65535
+ 8033bfc:	1085883a 	add	r2,r2,r2
+ 8033c00:	1007883a 	mov	r3,r2
+ 8033c04:	e0bff417 	ldw	r2,-48(fp)
+ 8033c08:	10c02a0e 	bge	r2,r3,8033cb4 <tcp_output+0x420>
+         goto send;
+      if (100 * (u_int)adv / so->so_rcv.sb_hiwat >= 35)
+ 8033c0c:	e0bff417 	ldw	r2,-48(fp)
+ 8033c10:	10c01924 	muli	r3,r2,100
+ 8033c14:	e0bff717 	ldw	r2,-36(fp)
+ 8033c18:	10800b17 	ldw	r2,44(r2)
+ 8033c1c:	100b883a 	mov	r5,r2
+ 8033c20:	1809883a 	mov	r4,r3
+ 8033c24:	800cff80 	call	800cff8 <__udivsi3>
+ 8033c28:	108008f0 	cmpltui	r2,r2,35
+ 8033c2c:	10002326 	beq	r2,zero,8033cbc <tcp_output+0x428>
+    * retransmit or persist is pending, then go to persist state.
+    * If nothing happens soon, send when timer expires:
+    * if window is nonzero, transmit what we can,
+    * otherwise force out a byte.
+    */
+   if (so->so_snd.sb_cc && tp->t_timer[TCPT_REXMT] == 0 &&
+ 8033c30:	e0bff717 	ldw	r2,-36(fp)
+ 8033c34:	10801217 	ldw	r2,72(r2)
+ 8033c38:	10000a26 	beq	r2,zero,8033c64 <tcp_output+0x3d0>
+ 8033c3c:	e0bfea17 	ldw	r2,-88(fp)
+ 8033c40:	10800317 	ldw	r2,12(r2)
+ 8033c44:	1000071e 	bne	r2,zero,8033c64 <tcp_output+0x3d0>
+       tp->t_timer[TCPT_PERSIST] == 0) 
+ 8033c48:	e0bfea17 	ldw	r2,-88(fp)
+ 8033c4c:	10800417 	ldw	r2,16(r2)
+   if (so->so_snd.sb_cc && tp->t_timer[TCPT_REXMT] == 0 &&
+ 8033c50:	1000041e 	bne	r2,zero,8033c64 <tcp_output+0x3d0>
+   {
+      tp->t_rxtshift = 0;
+ 8033c54:	e0bfea17 	ldw	r2,-88(fp)
+ 8033c58:	10000715 	stw	zero,28(r2)
+      tcp_setpersist(tp);
+ 8033c5c:	e13fea17 	ldw	r4,-88(fp)
+ 8033c60:	80348300 	call	8034830 <tcp_setpersist>
+   }
+
+   /*
+    * No reason to send a segment, just return.
+    */
+   return (0);
+ 8033c64:	0005883a 	mov	r2,zero
+ 8033c68:	0002ec06 	br	803481c <tcp_output+0xf88>
+      goto send;
+ 8033c6c:	0001883a 	nop
+ 8033c70:	00001306 	br	8033cc0 <tcp_output+0x42c>
+      goto send;
+ 8033c74:	0001883a 	nop
+ 8033c78:	00001106 	br	8033cc0 <tcp_output+0x42c>
+      goto send;
+ 8033c7c:	0001883a 	nop
+ 8033c80:	00000f06 	br	8033cc0 <tcp_output+0x42c>
+      goto send;
+ 8033c84:	0001883a 	nop
+ 8033c88:	00000d06 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033c8c:	0001883a 	nop
+ 8033c90:	00000b06 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033c94:	0001883a 	nop
+ 8033c98:	00000906 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033c9c:	0001883a 	nop
+ 8033ca0:	00000706 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033ca4:	0001883a 	nop
+ 8033ca8:	00000506 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033cac:	0001883a 	nop
+ 8033cb0:	00000306 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033cb4:	0001883a 	nop
+ 8033cb8:	00000106 	br	8033cc0 <tcp_output+0x42c>
+         goto send;
+ 8033cbc:	0001883a 	nop
+
+send:
+   ENTER_CRIT_SECTION(tp);
+ 8033cc0:	8028e940 	call	8028e94 <irq_Mask>
+
+   /* Limit send length to the current buffer so as to
+    * avoid doing the "mbuf shuffle" in m_copy().
+    */
+   bufoff = off;
+ 8033cc4:	e0bff517 	ldw	r2,-44(fp)
+ 8033cc8:	e0bff815 	stw	r2,-32(fp)
+   sendm = so->so_snd.sb_mb;
+ 8033ccc:	e0bff717 	ldw	r2,-36(fp)
+ 8033cd0:	10801817 	ldw	r2,96(r2)
+ 8033cd4:	e0bff915 	stw	r2,-28(fp)
+   if (len)
+ 8033cd8:	e0bfff17 	ldw	r2,-4(fp)
+ 8033cdc:	10005526 	beq	r2,zero,8033e34 <tcp_output+0x5a0>
+   {
+      /* find mbuf containing data to send (at "off") */
+      while (sendm)  /* loop through socket send list */
+ 8033ce0:	00000a06 	br	8033d0c <tcp_output+0x478>
+      {
+         bufoff -= sendm->m_len;
+ 8033ce4:	e0fff817 	ldw	r3,-32(fp)
+ 8033ce8:	e0bff917 	ldw	r2,-28(fp)
+ 8033cec:	10800217 	ldw	r2,8(r2)
+ 8033cf0:	1885c83a 	sub	r2,r3,r2
+ 8033cf4:	e0bff815 	stw	r2,-32(fp)
+         if (bufoff < 0)   /* if off is in this buffer, break */
+ 8033cf8:	e0bff817 	ldw	r2,-32(fp)
+ 8033cfc:	10000616 	blt	r2,zero,8033d18 <tcp_output+0x484>
+            break;
+         sendm = sendm->m_next;
+ 8033d00:	e0bff917 	ldw	r2,-28(fp)
+ 8033d04:	10800617 	ldw	r2,24(r2)
+ 8033d08:	e0bff915 	stw	r2,-28(fp)
+      while (sendm)  /* loop through socket send list */
+ 8033d0c:	e0bff917 	ldw	r2,-28(fp)
+ 8033d10:	103ff41e 	bne	r2,zero,8033ce4 <tcp_output+0x450>
+ 8033d14:	00000106 	br	8033d1c <tcp_output+0x488>
+            break;
+ 8033d18:	0001883a 	nop
+      }
+      if (!sendm) { dtrap();  /* shouldn't happen */ }
+ 8033d1c:	e0bff917 	ldw	r2,-28(fp)
+ 8033d20:	1000011e 	bne	r2,zero,8033d28 <tcp_output+0x494>
+ 8033d24:	8028cd40 	call	8028cd4 <dtrap>
+      bufoff += sendm->m_len; /* index to next data to send in msend */
+ 8033d28:	e0bff917 	ldw	r2,-28(fp)
+ 8033d2c:	10c00217 	ldw	r3,8(r2)
+ 8033d30:	e0bff817 	ldw	r2,-32(fp)
+ 8033d34:	1885883a 	add	r2,r3,r2
+ 8033d38:	e0bff815 	stw	r2,-32(fp)
+
+      /* if socket has multiple unsent mbufs, set flag for send to loop */
+      if ((sendm->m_next) && (len > (int)sendm->m_len))
+ 8033d3c:	e0bff917 	ldw	r2,-28(fp)
+ 8033d40:	10800617 	ldw	r2,24(r2)
+ 8033d44:	10000b26 	beq	r2,zero,8033d74 <tcp_output+0x4e0>
+ 8033d48:	e0bff917 	ldw	r2,-28(fp)
+ 8033d4c:	10800217 	ldw	r2,8(r2)
+ 8033d50:	1007883a 	mov	r3,r2
+ 8033d54:	e0bfff17 	ldw	r2,-4(fp)
+ 8033d58:	1880060e 	bge	r3,r2,8033d74 <tcp_output+0x4e0>
+      {
+         flags &= ~TH_FIN; /* don't FIN on segment prior to last */
+ 8033d5c:	e0fffd17 	ldw	r3,-12(fp)
+ 8033d60:	00bfff84 	movi	r2,-2
+ 8033d64:	1884703a 	and	r2,r3,r2
+ 8033d68:	e0bffd15 	stw	r2,-12(fp)
+         sendalot = 1;     /* set to send more segments */
+ 8033d6c:	00800044 	movi	r2,1
+ 8033d70:	e0bffa15 	stw	r2,-24(fp)
+      }
+      if((flags & TH_FIN) && (so->so_snd.sb_cc > (unsigned)len))
+ 8033d74:	e0bffd17 	ldw	r2,-12(fp)
+ 8033d78:	1080004c 	andi	r2,r2,1
+ 8033d7c:	10000826 	beq	r2,zero,8033da0 <tcp_output+0x50c>
+ 8033d80:	e0bff717 	ldw	r2,-36(fp)
+ 8033d84:	10801217 	ldw	r2,72(r2)
+ 8033d88:	e0ffff17 	ldw	r3,-4(fp)
+ 8033d8c:	1880042e 	bgeu	r3,r2,8033da0 <tcp_output+0x50c>
+      {
+         /* This can happen on slow links (PPP) which retry the last 
+          * segment - the one with the FIN bit attached to data.
+          */
+         flags &= ~TH_FIN; /* don't FIN on segment prior to last */
+ 8033d90:	e0fffd17 	ldw	r3,-12(fp)
+ 8033d94:	00bfff84 	movi	r2,-2
+ 8033d98:	1884703a 	and	r2,r3,r2
+ 8033d9c:	e0bffd15 	stw	r2,-12(fp)
+      }
+
+      /* only send the rest of msend */
+      len = min(len, (int)sendm->m_len);
+ 8033da0:	e0bff917 	ldw	r2,-28(fp)
+ 8033da4:	10800217 	ldw	r2,8(r2)
+ 8033da8:	1007883a 	mov	r3,r2
+ 8033dac:	e0bfff17 	ldw	r2,-4(fp)
+ 8033db0:	1880010e 	bge	r3,r2,8033db8 <tcp_output+0x524>
+ 8033db4:	1805883a 	mov	r2,r3
+ 8033db8:	e0bfff15 	stw	r2,-4(fp)
+       * Similarly, if sendm->m_data is not aligned with respect to 
+       * sendm->m_base and ALIGN_TYPE, we will copy the data to 
+       * ensure that it (and the then-prepended IP/TCP headers) will 
+       * be aligned according to ALIGN_TYPE. 
+       */
+      if ((bufoff != 0) ||       /* data not front aligned in send mbuf? */
+ 8033dbc:	e0bff817 	ldw	r2,-32(fp)
+ 8033dc0:	1000071e 	bne	r2,zero,8033de0 <tcp_output+0x54c>
+          (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) != 0))
+ 8033dc4:	e0bff917 	ldw	r2,-28(fp)
+ 8033dc8:	10c00317 	ldw	r3,12(r2)
+ 8033dcc:	e0bff917 	ldw	r2,-28(fp)
+ 8033dd0:	10800417 	ldw	r2,16(r2)
+ 8033dd4:	1885c83a 	sub	r2,r3,r2
+ 8033dd8:	108000cc 	andi	r2,r2,3
+      if ((bufoff != 0) ||       /* data not front aligned in send mbuf? */
+ 8033ddc:	10001526 	beq	r2,zero,8033e34 <tcp_output+0x5a0>
+      {
+         len = min(len, (int)(sendm->m_len - bufoff));   /* limit len again */
+ 8033de0:	e0bff917 	ldw	r2,-28(fp)
+ 8033de4:	10c00217 	ldw	r3,8(r2)
+ 8033de8:	e0bff817 	ldw	r2,-32(fp)
+ 8033dec:	1885c83a 	sub	r2,r3,r2
+ 8033df0:	1007883a 	mov	r3,r2
+ 8033df4:	e0bfff17 	ldw	r2,-4(fp)
+ 8033df8:	1880010e 	bge	r3,r2,8033e00 <tcp_output+0x56c>
+ 8033dfc:	1805883a 	mov	r2,r3
+ 8033e00:	e0bfff15 	stw	r2,-4(fp)
+          * of the m_data buffer then we can't use it in place, else we
+          * might write the IP/TCP header over data that has not yet
+          * been acked. In this case we must make sure our send
+          * fits into a little buffer and send what we can.
+          */
+         if ((len > (int)(lilbufsiz - HDRSLEN)) && /* length is bigger the small buffer? */
+ 8033e04:	d0a01717 	ldw	r2,-32676(gp)
+ 8033e08:	10bff204 	addi	r2,r2,-56
+ 8033e0c:	1007883a 	mov	r3,r2
+ 8033e10:	e0bfff17 	ldw	r2,-4(fp)
+ 8033e14:	1880070e 	bge	r3,r2,8033e34 <tcp_output+0x5a0>
+             (bigfreeq.q_len < 2))      /* and we are low on big buffers */
+ 8033e18:	008201b4 	movhi	r2,2054
+ 8033e1c:	10b7dd17 	ldw	r2,-8332(r2)
+         if ((len > (int)(lilbufsiz - HDRSLEN)) && /* length is bigger the small buffer? */
+ 8033e20:	10800088 	cmpgei	r2,r2,2
+ 8033e24:	1000031e 	bne	r2,zero,8033e34 <tcp_output+0x5a0>
+         {
+            len = lilbufsiz - HDRSLEN;
+ 8033e28:	d0a01717 	ldw	r2,-32676(gp)
+ 8033e2c:	10bff204 	addi	r2,r2,-56
+ 8033e30:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   /* if send data is sufficiently aligned in packet, prepend TCP/IP header
+    * in the space provided. 
+    */
+   if (len && (bufoff == 0) && 
+ 8033e34:	e0bfff17 	ldw	r2,-4(fp)
+ 8033e38:	10003526 	beq	r2,zero,8033f10 <tcp_output+0x67c>
+ 8033e3c:	e0bff817 	ldw	r2,-32(fp)
+ 8033e40:	1000331e 	bne	r2,zero,8033f10 <tcp_output+0x67c>
+       (sendm->pkt->inuse == 1) &&
+ 8033e44:	e0bff917 	ldw	r2,-28(fp)
+ 8033e48:	10800117 	ldw	r2,4(r2)
+ 8033e4c:	10800917 	ldw	r2,36(r2)
+   if (len && (bufoff == 0) && 
+ 8033e50:	10800058 	cmpnei	r2,r2,1
+ 8033e54:	10002e1e 	bne	r2,zero,8033f10 <tcp_output+0x67c>
+       (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) == 0) && 
+ 8033e58:	e0bff917 	ldw	r2,-28(fp)
+ 8033e5c:	10c00317 	ldw	r3,12(r2)
+ 8033e60:	e0bff917 	ldw	r2,-28(fp)
+ 8033e64:	10800417 	ldw	r2,16(r2)
+ 8033e68:	1885c83a 	sub	r2,r3,r2
+ 8033e6c:	108000cc 	andi	r2,r2,3
+       (sendm->pkt->inuse == 1) &&
+ 8033e70:	1000271e 	bne	r2,zero,8033f10 <tcp_output+0x67c>
+       (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) == 0) && 
+ 8033e74:	e0bffb17 	ldw	r2,-20(fp)
+ 8033e78:	1000251e 	bne	r2,zero,8033f10 <tcp_output+0x67c>
+       (optlen == 0))
+   {
+      /* get an empty mbuf to "clone" the data */
+      m = m_getnbuf(MT_TXDATA, 0);
+ 8033e7c:	000b883a 	mov	r5,zero
+ 8033e80:	01000084 	movi	r4,2
+ 8033e84:	8029a700 	call	8029a70 <m_getnbuf>
+ 8033e88:	e0bffc15 	stw	r2,-16(fp)
+      if (!m)
+ 8033e8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8033e90:	1000031e 	bne	r2,zero,8033ea0 <tcp_output+0x60c>
+      {
+         EXIT_CRIT_SECTION(tp);
+ 8033e94:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return (ENOBUFS);
+ 8033e98:	00801a44 	movi	r2,105
+ 8033e9c:	00025f06 	br	803481c <tcp_output+0xf88>
+      }
+      m->pkt = sendm->pkt; /* copy packet location in new mbuf */
+ 8033ea0:	e0bff917 	ldw	r2,-28(fp)
+ 8033ea4:	10c00117 	ldw	r3,4(r2)
+ 8033ea8:	e0bffc17 	ldw	r2,-16(fp)
+ 8033eac:	10c00115 	stw	r3,4(r2)
+      m->pkt->inuse++;     /* bump packet's use count */
+ 8033eb0:	e0bffc17 	ldw	r2,-16(fp)
+ 8033eb4:	10800117 	ldw	r2,4(r2)
+ 8033eb8:	10c00917 	ldw	r3,36(r2)
+ 8033ebc:	18c00044 	addi	r3,r3,1
+ 8033ec0:	10c00915 	stw	r3,36(r2)
+      m->m_base = sendm->m_base; /* clone mbuf members */
+ 8033ec4:	e0bff917 	ldw	r2,-28(fp)
+ 8033ec8:	10c00417 	ldw	r3,16(r2)
+ 8033ecc:	e0bffc17 	ldw	r2,-16(fp)
+ 8033ed0:	10c00415 	stw	r3,16(r2)
+      m->m_memsz = sendm->m_memsz;
+ 8033ed4:	e0bff917 	ldw	r2,-28(fp)
+ 8033ed8:	10c00517 	ldw	r3,20(r2)
+ 8033edc:	e0bffc17 	ldw	r2,-16(fp)
+ 8033ee0:	10c00515 	stw	r3,20(r2)
+      m->m_len = len + TCPIPHDRSZ;  /* adjust clone for header */
+ 8033ee4:	e0bfff17 	ldw	r2,-4(fp)
+ 8033ee8:	10800a04 	addi	r2,r2,40
+ 8033eec:	1007883a 	mov	r3,r2
+ 8033ef0:	e0bffc17 	ldw	r2,-16(fp)
+ 8033ef4:	10c00215 	stw	r3,8(r2)
+      m->m_data = sendm->m_data - TCPIPHDRSZ;
+ 8033ef8:	e0bff917 	ldw	r2,-28(fp)
+ 8033efc:	10800317 	ldw	r2,12(r2)
+ 8033f00:	10fff604 	addi	r3,r2,-40
+ 8033f04:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f08:	10c00315 	stw	r3,12(r2)
+ 8033f0c:	00002706 	br	8033fac <tcp_output+0x718>
+   {
+      /* Grab a header mbuf, attaching a copy of data to be 
+       * transmitted, and initialize the header from 
+       * the template for sends on this connection.
+       */
+      m = m_getwithdata (MT_HEADER, IFNETHDR_SIZE + TCPIPHDRSZ);
+ 8033f10:	d0a06417 	ldw	r2,-32368(gp)
+ 8033f14:	10800a04 	addi	r2,r2,40
+ 8033f18:	100b883a 	mov	r5,r2
+ 8033f1c:	010000c4 	movi	r4,3
+ 8033f20:	8029a700 	call	8029a70 <m_getnbuf>
+ 8033f24:	e0bffc15 	stw	r2,-16(fp)
+      if (m ==(struct mbuf *)NULL)
+ 8033f28:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f2c:	1000031e 	bne	r2,zero,8033f3c <tcp_output+0x6a8>
+      {
+         EXIT_CRIT_SECTION(tp);
+ 8033f30:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return ENOBUFS;
+ 8033f34:	00801a44 	movi	r2,105
+ 8033f38:	00023806 	br	803481c <tcp_output+0xf88>
+      }
+
+      m->m_len = TCPIPHDRSZ;
+ 8033f3c:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f40:	00c00a04 	movi	r3,40
+ 8033f44:	10c00215 	stw	r3,8(r2)
+      m->m_data += IFNETHDR_SIZE;/* Move this to sizeof tcpip hdr leave*/
+ 8033f48:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f4c:	10800317 	ldw	r2,12(r2)
+ 8033f50:	d0e06417 	ldw	r3,-32368(gp)
+ 8033f54:	10c7883a 	add	r3,r2,r3
+ 8033f58:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f5c:	10c00315 	stw	r3,12(r2)
+      /* 14 bytes for ethernet header      */
+
+      if (len) /* attach any data to send */
+ 8033f60:	e0bfff17 	ldw	r2,-4(fp)
+ 8033f64:	10001126 	beq	r2,zero,8033fac <tcp_output+0x718>
+      {
+         m->m_next = m_copy(so->so_snd.sb_mb, off, (int) len);
+ 8033f68:	e0bff717 	ldw	r2,-36(fp)
+ 8033f6c:	10801817 	ldw	r2,96(r2)
+ 8033f70:	e1bfff17 	ldw	r6,-4(fp)
+ 8033f74:	e17ff517 	ldw	r5,-44(fp)
+ 8033f78:	1009883a 	mov	r4,r2
+ 8033f7c:	8029d400 	call	8029d40 <m_copy>
+ 8033f80:	1007883a 	mov	r3,r2
+ 8033f84:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f88:	10c00615 	stw	r3,24(r2)
+         if (m->m_next == 0)
+ 8033f8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8033f90:	10800617 	ldw	r2,24(r2)
+ 8033f94:	1000051e 	bne	r2,zero,8033fac <tcp_output+0x718>
+         {
+            m_freem(m);
+ 8033f98:	e13ffc17 	ldw	r4,-16(fp)
+ 8033f9c:	8029cfc0 	call	8029cfc <m_freem>
+            EXIT_CRIT_SECTION(tp);
+ 8033fa0:	8028ef40 	call	8028ef4 <irq_Unmask>
+            return ENOBUFS;
+ 8033fa4:	00801a44 	movi	r2,105
+ 8033fa8:	00021c06 	br	803481c <tcp_output+0xf88>
+         }
+      }
+   }
+   EXIT_CRIT_SECTION(tp);
+ 8033fac:	8028ef40 	call	8028ef4 <irq_Unmask>
+
+   if (len) 
+ 8033fb0:	e0bfff17 	ldw	r2,-4(fp)
+ 8033fb4:	10002d26 	beq	r2,zero,803406c <tcp_output+0x7d8>
+   {
+      if (tp->t_force && len == 1)
+ 8033fb8:	e0bfea17 	ldw	r2,-88(fp)
+ 8033fbc:	10800a83 	ldbu	r2,42(r2)
+ 8033fc0:	10803fcc 	andi	r2,r2,255
+ 8033fc4:	1080201c 	xori	r2,r2,128
+ 8033fc8:	10bfe004 	addi	r2,r2,-128
+ 8033fcc:	10000926 	beq	r2,zero,8033ff4 <tcp_output+0x760>
+ 8033fd0:	e0bfff17 	ldw	r2,-4(fp)
+ 8033fd4:	10800058 	cmpnei	r2,r2,1
+ 8033fd8:	1000061e 	bne	r2,zero,8033ff4 <tcp_output+0x760>
+         tcpstat.tcps_sndprobe++;
+ 8033fdc:	008201b4 	movhi	r2,2054
+ 8033fe0:	10b8b917 	ldw	r2,-7452(r2)
+ 8033fe4:	10c00044 	addi	r3,r2,1
+ 8033fe8:	008201b4 	movhi	r2,2054
+ 8033fec:	10f8b915 	stw	r3,-7452(r2)
+ 8033ff0:	00004306 	br	8034100 <tcp_output+0x86c>
+      else if (SEQ_LT(tp->snd_nxt, tp->snd_max)) 
+ 8033ff4:	e0bfea17 	ldw	r2,-88(fp)
+ 8033ff8:	10c00f17 	ldw	r3,60(r2)
+ 8033ffc:	e0bfea17 	ldw	r2,-88(fp)
+ 8034000:	10801a17 	ldw	r2,104(r2)
+ 8034004:	1885c83a 	sub	r2,r3,r2
+ 8034008:	10000c0e 	bge	r2,zero,803403c <tcp_output+0x7a8>
+      {
+         tcpstat.tcps_sndrexmitpack++;
+ 803400c:	008201b4 	movhi	r2,2054
+ 8034010:	10b8b617 	ldw	r2,-7464(r2)
+ 8034014:	10c00044 	addi	r3,r2,1
+ 8034018:	008201b4 	movhi	r2,2054
+ 803401c:	10f8b615 	stw	r3,-7464(r2)
+         tcpstat.tcps_sndrexmitbyte += len;
+ 8034020:	008201b4 	movhi	r2,2054
+ 8034024:	10f8b717 	ldw	r3,-7460(r2)
+ 8034028:	e0bfff17 	ldw	r2,-4(fp)
+ 803402c:	1887883a 	add	r3,r3,r2
+ 8034030:	008201b4 	movhi	r2,2054
+ 8034034:	10f8b715 	stw	r3,-7460(r2)
+ 8034038:	00003106 	br	8034100 <tcp_output+0x86c>
+         tcpstat.tcps_sackresend++;
+#endif
+      } 
+      else 
+      {
+         tcpstat.tcps_sndpack++;
+ 803403c:	008201b4 	movhi	r2,2054
+ 8034040:	10b8b417 	ldw	r2,-7472(r2)
+ 8034044:	10c00044 	addi	r3,r2,1
+ 8034048:	008201b4 	movhi	r2,2054
+ 803404c:	10f8b415 	stw	r3,-7472(r2)
+         tcpstat.tcps_sndbyte += len;
+ 8034050:	008201b4 	movhi	r2,2054
+ 8034054:	10f8b517 	ldw	r3,-7468(r2)
+ 8034058:	e0bfff17 	ldw	r2,-4(fp)
+ 803405c:	1887883a 	add	r3,r3,r2
+ 8034060:	008201b4 	movhi	r2,2054
+ 8034064:	10f8b515 	stw	r3,-7468(r2)
+ 8034068:	00002506 	br	8034100 <tcp_output+0x86c>
+      }
+   }
+   else if (tp->t_flags & TF_ACKNOW)
+ 803406c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034070:	10800b0b 	ldhu	r2,44(r2)
+ 8034074:	10bfffcc 	andi	r2,r2,65535
+ 8034078:	1080004c 	andi	r2,r2,1
+ 803407c:	10000626 	beq	r2,zero,8034098 <tcp_output+0x804>
+   {
+      tcpstat.tcps_sndacks++;
+ 8034080:	008201b4 	movhi	r2,2054
+ 8034084:	10b8b817 	ldw	r2,-7456(r2)
+ 8034088:	10c00044 	addi	r3,r2,1
+ 803408c:	008201b4 	movhi	r2,2054
+ 8034090:	10f8b815 	stw	r3,-7456(r2)
+ 8034094:	00001a06 	br	8034100 <tcp_output+0x86c>
+   }
+   else if (flags & (TH_SYN|TH_FIN|TH_RST))
+ 8034098:	e0bffd17 	ldw	r2,-12(fp)
+ 803409c:	108001cc 	andi	r2,r2,7
+ 80340a0:	10000626 	beq	r2,zero,80340bc <tcp_output+0x828>
+      tcpstat.tcps_sndctrl++;
+ 80340a4:	008201b4 	movhi	r2,2054
+ 80340a8:	10b8bc17 	ldw	r2,-7440(r2)
+ 80340ac:	10c00044 	addi	r3,r2,1
+ 80340b0:	008201b4 	movhi	r2,2054
+ 80340b4:	10f8bc15 	stw	r3,-7440(r2)
+ 80340b8:	00001106 	br	8034100 <tcp_output+0x86c>
+   else if (SEQ_GT(tp->snd_up, tp->snd_una))
+ 80340bc:	e0bfea17 	ldw	r2,-88(fp)
+ 80340c0:	10c01017 	ldw	r3,64(r2)
+ 80340c4:	e0bfea17 	ldw	r2,-88(fp)
+ 80340c8:	10800e17 	ldw	r2,56(r2)
+ 80340cc:	1885c83a 	sub	r2,r3,r2
+ 80340d0:	0080060e 	bge	zero,r2,80340ec <tcp_output+0x858>
+      tcpstat.tcps_sndurg++;
+ 80340d4:	008201b4 	movhi	r2,2054
+ 80340d8:	10b8ba17 	ldw	r2,-7448(r2)
+ 80340dc:	10c00044 	addi	r3,r2,1
+ 80340e0:	008201b4 	movhi	r2,2054
+ 80340e4:	10f8ba15 	stw	r3,-7448(r2)
+ 80340e8:	00000506 	br	8034100 <tcp_output+0x86c>
+   else
+      tcpstat.tcps_sndwinup++;
+ 80340ec:	008201b4 	movhi	r2,2054
+ 80340f0:	10b8bb17 	ldw	r2,-7444(r2)
+ 80340f4:	10c00044 	addi	r3,r2,1
+ 80340f8:	008201b4 	movhi	r2,2054
+ 80340fc:	10f8bb15 	stw	r3,-7444(r2)
+
+   ti = (struct tcpiphdr *)(m->m_data+sizeof(struct ip)-sizeof(struct ipovly));
+ 8034100:	e0bffc17 	ldw	r2,-16(fp)
+ 8034104:	10800317 	ldw	r2,12(r2)
+ 8034108:	e0bff315 	stw	r2,-52(fp)
+   if ((char *)ti < m->pkt->nb_buff)
+ 803410c:	e0bffc17 	ldw	r2,-16(fp)
+ 8034110:	10800117 	ldw	r2,4(r2)
+ 8034114:	10800117 	ldw	r2,4(r2)
+ 8034118:	e0fff317 	ldw	r3,-52(fp)
+ 803411c:	1880032e 	bgeu	r3,r2,803412c <tcp_output+0x898>
+   {
+      panic("tcp_out- packet ptr underflow\n");
+ 8034120:	01020174 	movhi	r4,2053
+ 8034124:	212aa204 	addi	r4,r4,-21880
+ 8034128:	80271780 	call	8027178 <panic>
+   }
+   tcp_mbuf = m;        /* flag TCP header mbuf */
+ 803412c:	e0bffc17 	ldw	r2,-16(fp)
+ 8034130:	e0bff215 	stw	r2,-56(fp)
+      tcp_mbuf->m_data += sizeof(struct ipovly);
+      tcp_mbuf->m_len -= sizeof(struct ipovly);
+   }
+#endif   /* end IP_V6 */
+
+   if (tp->t_template == 0)
+ 8034134:	e0bfea17 	ldw	r2,-88(fp)
+ 8034138:	10800c17 	ldw	r2,48(r2)
+ 803413c:	1000031e 	bne	r2,zero,803414c <tcp_output+0x8b8>
+      panic("tcp_output");
+ 8034140:	01020174 	movhi	r4,2053
+ 8034144:	212aaa04 	addi	r4,r4,-21848
+ 8034148:	80271780 	call	8027178 <panic>
+
+   MEMCPY((char*)ti, (char*)tp->t_template, sizeof(struct tcpiphdr));
+ 803414c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034150:	10800c17 	ldw	r2,48(r2)
+ 8034154:	01800a04 	movi	r6,40
+ 8034158:	100b883a 	mov	r5,r2
+ 803415c:	e13ff317 	ldw	r4,-52(fp)
+ 8034160:	80086b80 	call	80086b8 <memcpy>
+   /*
+    * Fill in fields, remembering maximum advertised
+    * window for use in delaying messages about window sizes.
+    * If resending a FIN, be sure not to use a new sequence number.
+    */
+   if (flags & TH_FIN && tp->t_flags & TF_SENTFIN && 
+ 8034164:	e0bffd17 	ldw	r2,-12(fp)
+ 8034168:	1080004c 	andi	r2,r2,1
+ 803416c:	10000f26 	beq	r2,zero,80341ac <tcp_output+0x918>
+ 8034170:	e0bfea17 	ldw	r2,-88(fp)
+ 8034174:	10800b0b 	ldhu	r2,44(r2)
+ 8034178:	10bfffcc 	andi	r2,r2,65535
+ 803417c:	1080040c 	andi	r2,r2,16
+ 8034180:	10000a26 	beq	r2,zero,80341ac <tcp_output+0x918>
+       tp->snd_nxt == tp->snd_max)
+ 8034184:	e0bfea17 	ldw	r2,-88(fp)
+ 8034188:	10c00f17 	ldw	r3,60(r2)
+ 803418c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034190:	10801a17 	ldw	r2,104(r2)
+   if (flags & TH_FIN && tp->t_flags & TF_SENTFIN && 
+ 8034194:	1880051e 	bne	r3,r2,80341ac <tcp_output+0x918>
+   {
+      tp->snd_nxt--;
+ 8034198:	e0bfea17 	ldw	r2,-88(fp)
+ 803419c:	10800f17 	ldw	r2,60(r2)
+ 80341a0:	10ffffc4 	addi	r3,r2,-1
+ 80341a4:	e0bfea17 	ldw	r2,-88(fp)
+ 80341a8:	10c00f15 	stw	r3,60(r2)
+   }
+
+   ti->ti_seq = htonl(tp->snd_nxt);
+ 80341ac:	e0bfea17 	ldw	r2,-88(fp)
+ 80341b0:	10800f17 	ldw	r2,60(r2)
+ 80341b4:	1006d63a 	srli	r3,r2,24
+ 80341b8:	e0bfea17 	ldw	r2,-88(fp)
+ 80341bc:	10800f17 	ldw	r2,60(r2)
+ 80341c0:	1004d23a 	srli	r2,r2,8
+ 80341c4:	10bfc00c 	andi	r2,r2,65280
+ 80341c8:	1886b03a 	or	r3,r3,r2
+ 80341cc:	e0bfea17 	ldw	r2,-88(fp)
+ 80341d0:	10800f17 	ldw	r2,60(r2)
+ 80341d4:	1004923a 	slli	r2,r2,8
+ 80341d8:	10803fec 	andhi	r2,r2,255
+ 80341dc:	1886b03a 	or	r3,r3,r2
+ 80341e0:	e0bfea17 	ldw	r2,-88(fp)
+ 80341e4:	10800f17 	ldw	r2,60(r2)
+ 80341e8:	1004963a 	slli	r2,r2,24
+ 80341ec:	1886b03a 	or	r3,r3,r2
+ 80341f0:	e0bff317 	ldw	r2,-52(fp)
+ 80341f4:	10c00615 	stw	r3,24(r2)
+   ti->ti_ack = htonl(tp->rcv_nxt);
+ 80341f8:	e0bfea17 	ldw	r2,-88(fp)
+ 80341fc:	10801617 	ldw	r2,88(r2)
+ 8034200:	1006d63a 	srli	r3,r2,24
+ 8034204:	e0bfea17 	ldw	r2,-88(fp)
+ 8034208:	10801617 	ldw	r2,88(r2)
+ 803420c:	1004d23a 	srli	r2,r2,8
+ 8034210:	10bfc00c 	andi	r2,r2,65280
+ 8034214:	1886b03a 	or	r3,r3,r2
+ 8034218:	e0bfea17 	ldw	r2,-88(fp)
+ 803421c:	10801617 	ldw	r2,88(r2)
+ 8034220:	1004923a 	slli	r2,r2,8
+ 8034224:	10803fec 	andhi	r2,r2,255
+ 8034228:	1886b03a 	or	r3,r3,r2
+ 803422c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034230:	10801617 	ldw	r2,88(r2)
+ 8034234:	1004963a 	slli	r2,r2,24
+ 8034238:	1886b03a 	or	r3,r3,r2
+ 803423c:	e0bff317 	ldw	r2,-52(fp)
+ 8034240:	10c00715 	stw	r3,28(r2)
+    * a retransmission, and the original SYN caused PPP to start
+    * bringing the interface up, and PPP has got a new IP address
+    * via IPCP), update the template and the inpcb with the new 
+    * address.
+    */
+   if (flags & TH_SYN)
+ 8034244:	e0bffd17 	ldw	r2,-12(fp)
+ 8034248:	1080008c 	andi	r2,r2,2
+ 803424c:	10002326 	beq	r2,zero,80342dc <tcp_output+0xa48>
+   {
+      struct inpcb * inp;
+      inp = (struct inpcb *)so->so_pcb;
+ 8034250:	e0bff717 	ldw	r2,-36(fp)
+ 8034254:	10800117 	ldw	r2,4(r2)
+ 8034258:	e0bff115 	stw	r2,-60(fp)
+
+      switch(so->so_domain)
+ 803425c:	e0bff717 	ldw	r2,-36(fp)
+ 8034260:	10800517 	ldw	r2,20(r2)
+ 8034264:	10800098 	cmpnei	r2,r2,2
+ 8034268:	10001a1e 	bne	r2,zero,80342d4 <tcp_output+0xa40>
+         }
+         }
+#endif   /* INCLUDE_PPP */
+
+         /* If this is a SYN (not a SYN/ACK) then set the pmtu */
+         if((flags & TH_ACK) == 0)
+ 803426c:	e0bffd17 	ldw	r2,-12(fp)
+ 8034270:	1080040c 	andi	r2,r2,16
+ 8034274:	10001b1e 	bne	r2,zero,80342e4 <tcp_output+0xa50>
+            inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr);
+#else    /* not compiled for pathmtu, guess based on iface */
+            {
+               NET ifp;
+               /* find iface for route. Pass "src" as nexthop return */
+               ifp = iproute(ti->ti_dst.s_addr, &src);
+ 8034278:	e0bff317 	ldw	r2,-52(fp)
+ 803427c:	10800417 	ldw	r2,16(r2)
+ 8034280:	e0ffeb04 	addi	r3,fp,-84
+ 8034284:	180b883a 	mov	r5,r3
+ 8034288:	1009883a 	mov	r4,r2
+ 803428c:	803b3700 	call	803b370 <iproute>
+ 8034290:	e0bff015 	stw	r2,-64(fp)
+               if(ifp)
+ 8034294:	e0bff017 	ldw	r2,-64(fp)
+ 8034298:	10000926 	beq	r2,zero,80342c0 <tcp_output+0xa2c>
+                  inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40);
+ 803429c:	e0bff017 	ldw	r2,-64(fp)
+ 80342a0:	10c00917 	ldw	r3,36(r2)
+ 80342a4:	e0bff017 	ldw	r2,-64(fp)
+ 80342a8:	10800817 	ldw	r2,32(r2)
+ 80342ac:	10800a04 	addi	r2,r2,40
+ 80342b0:	1887c83a 	sub	r3,r3,r2
+ 80342b4:	e0bff117 	ldw	r2,-60(fp)
+ 80342b8:	10c00615 	stw	r3,24(r2)
+               else
+                  inp->inp_pmtu = 580;  /* Ugh. */
+            }
+#endif   /* IP_PMTU */
+         }
+         break;
+ 80342bc:	00000906 	br	80342e4 <tcp_output+0xa50>
+                  inp->inp_pmtu = 580;  /* Ugh. */
+ 80342c0:	e0bff117 	ldw	r2,-60(fp)
+ 80342c4:	00c09104 	movi	r3,580
+ 80342c8:	10c00615 	stw	r3,24(r2)
+         break;
+ 80342cc:	0001883a 	nop
+ 80342d0:	00000406 	br	80342e4 <tcp_output+0xa50>
+         }
+         break;
+      }
+#endif   /* IP_V6 */
+      default:
+         dtrap();    /* bad domain setting */
+ 80342d4:	8028cd40 	call	8028cd4 <dtrap>
+ 80342d8:	00000306 	br	80342e8 <tcp_output+0xa54>
+      }
+   }
+ 80342dc:	0001883a 	nop
+ 80342e0:	00000106 	br	80342e8 <tcp_output+0xa54>
+         break;
+ 80342e4:	0001883a 	nop
+
+   /* fill in options if any are set */
+   if (optlen)
+ 80342e8:	e0bffb17 	ldw	r2,-20(fp)
+ 80342ec:	10002b26 	beq	r2,zero,803439c <tcp_output+0xb08>
+   {
+      struct mbuf * mopt;
+
+      mopt = m_getwithdata(MT_TXDATA, MAXOPTLEN);
+ 80342f0:	01404004 	movi	r5,256
+ 80342f4:	01000084 	movi	r4,2
+ 80342f8:	8029a700 	call	8029a70 <m_getnbuf>
+ 80342fc:	e0bfef15 	stw	r2,-68(fp)
+      if (mopt == NULL) 
+ 8034300:	e0bfef17 	ldw	r2,-68(fp)
+ 8034304:	1000041e 	bne	r2,zero,8034318 <tcp_output+0xa84>
+      {
+         m_freem(m);
+ 8034308:	e13ffc17 	ldw	r4,-16(fp)
+ 803430c:	8029cfc0 	call	8029cfc <m_freem>
+         return (ENOBUFS);
+ 8034310:	00801a44 	movi	r2,105
+ 8034314:	00014106 	br	803481c <tcp_output+0xf88>
+      }
+
+      /* insert options mbuf after after tmp_mbuf */
+      mopt->m_next = tcp_mbuf->m_next;
+ 8034318:	e0bff217 	ldw	r2,-56(fp)
+ 803431c:	10c00617 	ldw	r3,24(r2)
+ 8034320:	e0bfef17 	ldw	r2,-68(fp)
+ 8034324:	10c00615 	stw	r3,24(r2)
+      tcp_mbuf->m_next = mopt;
+ 8034328:	e0bff217 	ldw	r2,-56(fp)
+ 803432c:	e0ffef17 	ldw	r3,-68(fp)
+ 8034330:	10c00615 	stw	r3,24(r2)
+
+      /* extend options to aligned address */
+      while(optlen & 0x03)
+ 8034334:	00000606 	br	8034350 <tcp_output+0xabc>
+         tcp_optionbuf[optlen++] = TCPOPT_EOL;
+ 8034338:	e0bffb17 	ldw	r2,-20(fp)
+ 803433c:	10c00044 	addi	r3,r2,1
+ 8034340:	e0fffb15 	stw	r3,-20(fp)
+ 8034344:	d0e08804 	addi	r3,gp,-32224
+ 8034348:	10c5883a 	add	r2,r2,r3
+ 803434c:	10000005 	stb	zero,0(r2)
+      while(optlen & 0x03)
+ 8034350:	e0bffb17 	ldw	r2,-20(fp)
+ 8034354:	108000cc 	andi	r2,r2,3
+ 8034358:	103ff71e 	bne	r2,zero,8034338 <tcp_output+0xaa4>
+
+      MEMCPY(mtod(mopt, char *), tcp_optionbuf, optlen);
+ 803435c:	e0bfef17 	ldw	r2,-68(fp)
+ 8034360:	10800317 	ldw	r2,12(r2)
+ 8034364:	e1bffb17 	ldw	r6,-20(fp)
+ 8034368:	d1608804 	addi	r5,gp,-32224
+ 803436c:	1009883a 	mov	r4,r2
+ 8034370:	80086b80 	call	80086b8 <memcpy>
+      mopt->m_len = optlen;
+ 8034374:	e0bfef17 	ldw	r2,-68(fp)
+ 8034378:	e0fffb17 	ldw	r3,-20(fp)
+ 803437c:	10c00215 	stw	r3,8(r2)
+      /* use portable macro to set tcp data offset bits */
+      SET_TH_OFF(ti->ti_t, ((sizeof (struct tcphdr) + optlen) >> 2));
+ 8034380:	e0bffb17 	ldw	r2,-20(fp)
+ 8034384:	10800504 	addi	r2,r2,20
+ 8034388:	1004d0ba 	srli	r2,r2,2
+ 803438c:	1004913a 	slli	r2,r2,4
+ 8034390:	1007883a 	mov	r3,r2
+ 8034394:	e0bff317 	ldw	r2,-52(fp)
+ 8034398:	10c00805 	stb	r3,32(r2)
+   }
+
+   ti->ti_flags = (u_char)flags;
+ 803439c:	e0bffd17 	ldw	r2,-12(fp)
+ 80343a0:	1007883a 	mov	r3,r2
+ 80343a4:	e0bff317 	ldw	r2,-52(fp)
+ 80343a8:	10c00845 	stb	r3,33(r2)
+   /*
+    * Calculate receive window. Don't shrink window,
+    * but avoid silly window syndrome.
+    */
+   if (win < (long)(so->so_rcv.sb_hiwat / 4) && win < (long)tp->t_maxseg)
+ 80343ac:	e0bff717 	ldw	r2,-36(fp)
+ 80343b0:	10800b17 	ldw	r2,44(r2)
+ 80343b4:	1004d0ba 	srli	r2,r2,2
+ 80343b8:	1007883a 	mov	r3,r2
+ 80343bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80343c0:	10c0060e 	bge	r2,r3,80343dc <tcp_output+0xb48>
+ 80343c4:	e0bfea17 	ldw	r2,-88(fp)
+ 80343c8:	10800a0b 	ldhu	r2,40(r2)
+ 80343cc:	10bfffcc 	andi	r2,r2,65535
+ 80343d0:	e0fffe17 	ldw	r3,-8(fp)
+ 80343d4:	1880010e 	bge	r3,r2,80343dc <tcp_output+0xb48>
+      win = 0;
+ 80343d8:	e03ffe15 	stw	zero,-8(fp)
+   if (win < (long)(tp->rcv_adv - tp->rcv_nxt))
+ 80343dc:	e0bfea17 	ldw	r2,-88(fp)
+ 80343e0:	10c01917 	ldw	r3,100(r2)
+ 80343e4:	e0bfea17 	ldw	r2,-88(fp)
+ 80343e8:	10801617 	ldw	r2,88(r2)
+ 80343ec:	1885c83a 	sub	r2,r3,r2
+ 80343f0:	1007883a 	mov	r3,r2
+ 80343f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80343f8:	10c0060e 	bge	r2,r3,8034414 <tcp_output+0xb80>
+      win = (long)(tp->rcv_adv - tp->rcv_nxt);
+ 80343fc:	e0bfea17 	ldw	r2,-88(fp)
+ 8034400:	10c01917 	ldw	r3,100(r2)
+ 8034404:	e0bfea17 	ldw	r2,-88(fp)
+ 8034408:	10801617 	ldw	r2,88(r2)
+ 803440c:	1885c83a 	sub	r2,r3,r2
+ 8034410:	e0bffe15 	stw	r2,-8(fp)
+
+   /* do check for Iniche buffer limits -JB- */
+   if (bigfreeq.q_len == 0)   /* If queue length is 0, set window to 0 */
+ 8034414:	008201b4 	movhi	r2,2054
+ 8034418:	10b7dd17 	ldw	r2,-8332(r2)
+ 803441c:	1000021e 	bne	r2,zero,8034428 <tcp_output+0xb94>
+   {
+      win = 0;
+ 8034420:	e03ffe15 	stw	zero,-8(fp)
+ 8034424:	00000e06 	br	8034460 <tcp_output+0xbcc>
+   }
+   else if(win > (((long)bigfreeq.q_len - 1) * (long)bigbufsiz))
+ 8034428:	008201b4 	movhi	r2,2054
+ 803442c:	10b7dd17 	ldw	r2,-8332(r2)
+ 8034430:	10bfffc4 	addi	r2,r2,-1
+ 8034434:	d0e01917 	ldw	r3,-32668(gp)
+ 8034438:	10c7383a 	mul	r3,r2,r3
+ 803443c:	e0bffe17 	ldw	r2,-8(fp)
+ 8034440:	1880070e 	bge	r3,r2,8034460 <tcp_output+0xbcc>
+   {
+      win = ((long)bigfreeq.q_len - 1) * bigbufsiz;
+ 8034444:	008201b4 	movhi	r2,2054
+ 8034448:	10b7dd17 	ldw	r2,-8332(r2)
+ 803444c:	10bfffc4 	addi	r2,r2,-1
+ 8034450:	1007883a 	mov	r3,r2
+ 8034454:	d0a01917 	ldw	r2,-32668(gp)
+ 8034458:	1885383a 	mul	r2,r3,r2
+ 803445c:	e0bffe15 	stw	r2,-8(fp)
+      ti->ti_win = htons((u_short)(win >> tp->rcv_wind_scale)); /* apply scale */
+   }
+   else
+#endif /* TCP_WIN_SCALE */
+   {
+      ti->ti_win = htons((u_short)win);
+ 8034460:	e0bffe17 	ldw	r2,-8(fp)
+ 8034464:	10bfffcc 	andi	r2,r2,65535
+ 8034468:	1004d23a 	srli	r2,r2,8
+ 803446c:	1007883a 	mov	r3,r2
+ 8034470:	e0bffe17 	ldw	r2,-8(fp)
+ 8034474:	10bfffcc 	andi	r2,r2,65535
+ 8034478:	1004923a 	slli	r2,r2,8
+ 803447c:	1884b03a 	or	r2,r3,r2
+ 8034480:	1007883a 	mov	r3,r2
+ 8034484:	e0bff317 	ldw	r2,-52(fp)
+ 8034488:	10c0088d 	sth	r3,34(r2)
+   }
+
+   if (SEQ_GT(tp->snd_up, tp->snd_nxt)) 
+ 803448c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034490:	10c01017 	ldw	r3,64(r2)
+ 8034494:	e0bfea17 	ldw	r2,-88(fp)
+ 8034498:	10800f17 	ldw	r2,60(r2)
+ 803449c:	1885c83a 	sub	r2,r3,r2
+ 80344a0:	00801c0e 	bge	zero,r2,8034514 <tcp_output+0xc80>
+   {
+      ti->ti_urp = htons((u_short)(tp->snd_up - tp->snd_nxt));
+ 80344a4:	e0bfea17 	ldw	r2,-88(fp)
+ 80344a8:	10801017 	ldw	r2,64(r2)
+ 80344ac:	1007883a 	mov	r3,r2
+ 80344b0:	e0bfea17 	ldw	r2,-88(fp)
+ 80344b4:	10800f17 	ldw	r2,60(r2)
+ 80344b8:	1885c83a 	sub	r2,r3,r2
+ 80344bc:	10bfffcc 	andi	r2,r2,65535
+ 80344c0:	1004d23a 	srli	r2,r2,8
+ 80344c4:	1007883a 	mov	r3,r2
+ 80344c8:	e0bfea17 	ldw	r2,-88(fp)
+ 80344cc:	10801017 	ldw	r2,64(r2)
+ 80344d0:	1009883a 	mov	r4,r2
+ 80344d4:	e0bfea17 	ldw	r2,-88(fp)
+ 80344d8:	10800f17 	ldw	r2,60(r2)
+ 80344dc:	2085c83a 	sub	r2,r4,r2
+ 80344e0:	10bfffcc 	andi	r2,r2,65535
+ 80344e4:	1004923a 	slli	r2,r2,8
+ 80344e8:	1884b03a 	or	r2,r3,r2
+ 80344ec:	1007883a 	mov	r3,r2
+ 80344f0:	e0bff317 	ldw	r2,-52(fp)
+ 80344f4:	10c0098d 	sth	r3,38(r2)
+      ti->ti_flags |= TH_URG;
+ 80344f8:	e0bff317 	ldw	r2,-52(fp)
+ 80344fc:	10800843 	ldbu	r2,33(r2)
+ 8034500:	10800814 	ori	r2,r2,32
+ 8034504:	1007883a 	mov	r3,r2
+ 8034508:	e0bff317 	ldw	r2,-52(fp)
+ 803450c:	10c00845 	stb	r3,33(r2)
+ 8034510:	00000406 	br	8034524 <tcp_output+0xc90>
+       * If no urgent pointer to send, then we pull
+       * the urgent pointer to the left edge of the send window
+       * so that it doesn't drift into the send window on sequence
+       * number wraparound.
+       */
+      tp->snd_up = tp->snd_una;        /* drag it along */
+ 8034514:	e0bfea17 	ldw	r2,-88(fp)
+ 8034518:	10c00e17 	ldw	r3,56(r2)
+ 803451c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034520:	10c01015 	stw	r3,64(r2)
+   /*
+    * If anything to send and we can send it all, set PUSH.
+    * (This will keep happy those implementations which only
+    * give data to the user when a buffer fills or a PUSH comes in.)
+    */
+   if (len && off+len == (int)so->so_snd.sb_cc)
+ 8034524:	e0bfff17 	ldw	r2,-4(fp)
+ 8034528:	10000c26 	beq	r2,zero,803455c <tcp_output+0xcc8>
+ 803452c:	e0fff517 	ldw	r3,-44(fp)
+ 8034530:	e0bfff17 	ldw	r2,-4(fp)
+ 8034534:	1885883a 	add	r2,r3,r2
+ 8034538:	e0fff717 	ldw	r3,-36(fp)
+ 803453c:	18c01217 	ldw	r3,72(r3)
+ 8034540:	10c0061e 	bne	r2,r3,803455c <tcp_output+0xcc8>
+      ti->ti_flags |= TH_PUSH;
+ 8034544:	e0bff317 	ldw	r2,-52(fp)
+ 8034548:	10800843 	ldbu	r2,33(r2)
+ 803454c:	10800214 	ori	r2,r2,8
+ 8034550:	1007883a 	mov	r3,r2
+ 8034554:	e0bff317 	ldw	r2,-52(fp)
+ 8034558:	10c00845 	stb	r3,33(r2)
+
+   /*
+    * In transmit state, time the transmission and arrange for
+    * the retransmit.  In persist state, just set snd_max.
+    */
+   if (tp->t_force == 0 || tp->t_timer[TCPT_PERSIST] == 0) 
+ 803455c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034560:	10800a83 	ldbu	r2,42(r2)
+ 8034564:	10803fcc 	andi	r2,r2,255
+ 8034568:	1080201c 	xori	r2,r2,128
+ 803456c:	10bfe004 	addi	r2,r2,-128
+ 8034570:	10000326 	beq	r2,zero,8034580 <tcp_output+0xcec>
+ 8034574:	e0bfea17 	ldw	r2,-88(fp)
+ 8034578:	10800417 	ldw	r2,16(r2)
+ 803457c:	10004b1e 	bne	r2,zero,80346ac <tcp_output+0xe18>
+   {
+      tcp_seq startseq = tp->snd_nxt;
+ 8034580:	e0bfea17 	ldw	r2,-88(fp)
+ 8034584:	10800f17 	ldw	r2,60(r2)
+ 8034588:	e0bfee15 	stw	r2,-72(fp)
+
+      /*
+       * Advance snd_nxt over sequence space of this segment.
+       */
+      if (flags & TH_SYN)
+ 803458c:	e0bffd17 	ldw	r2,-12(fp)
+ 8034590:	1080008c 	andi	r2,r2,2
+ 8034594:	10000526 	beq	r2,zero,80345ac <tcp_output+0xd18>
+         tp->snd_nxt++;
+ 8034598:	e0bfea17 	ldw	r2,-88(fp)
+ 803459c:	10800f17 	ldw	r2,60(r2)
+ 80345a0:	10c00044 	addi	r3,r2,1
+ 80345a4:	e0bfea17 	ldw	r2,-88(fp)
+ 80345a8:	10c00f15 	stw	r3,60(r2)
+
+      if (flags & TH_FIN)
+ 80345ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80345b0:	1080004c 	andi	r2,r2,1
+ 80345b4:	10000b26 	beq	r2,zero,80345e4 <tcp_output+0xd50>
+      {
+         tp->snd_nxt++;
+ 80345b8:	e0bfea17 	ldw	r2,-88(fp)
+ 80345bc:	10800f17 	ldw	r2,60(r2)
+ 80345c0:	10c00044 	addi	r3,r2,1
+ 80345c4:	e0bfea17 	ldw	r2,-88(fp)
+ 80345c8:	10c00f15 	stw	r3,60(r2)
+         tp->t_flags |= TF_SENTFIN;
+ 80345cc:	e0bfea17 	ldw	r2,-88(fp)
+ 80345d0:	10800b0b 	ldhu	r2,44(r2)
+ 80345d4:	10800414 	ori	r2,r2,16
+ 80345d8:	1007883a 	mov	r3,r2
+ 80345dc:	e0bfea17 	ldw	r2,-88(fp)
+ 80345e0:	10c00b0d 	sth	r3,44(r2)
+      }
+      tp->snd_nxt += len;
+ 80345e4:	e0bfea17 	ldw	r2,-88(fp)
+ 80345e8:	10c00f17 	ldw	r3,60(r2)
+ 80345ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80345f0:	1887883a 	add	r3,r3,r2
+ 80345f4:	e0bfea17 	ldw	r2,-88(fp)
+ 80345f8:	10c00f15 	stw	r3,60(r2)
+      if (SEQ_GT(tp->snd_nxt, tp->snd_max)) 
+ 80345fc:	e0bfea17 	ldw	r2,-88(fp)
+ 8034600:	10c00f17 	ldw	r3,60(r2)
+ 8034604:	e0bfea17 	ldw	r2,-88(fp)
+ 8034608:	10801a17 	ldw	r2,104(r2)
+ 803460c:	1885c83a 	sub	r2,r3,r2
+ 8034610:	0080120e 	bge	zero,r2,803465c <tcp_output+0xdc8>
+      {
+         tp->snd_max = tp->snd_nxt;
+ 8034614:	e0bfea17 	ldw	r2,-88(fp)
+ 8034618:	10c00f17 	ldw	r3,60(r2)
+ 803461c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034620:	10c01a15 	stw	r3,104(r2)
+         /*
+          * Time this transmission if not a retransmission and
+          * not currently timing anything.
+          */
+         if (tp->t_rttick == 0) 
+ 8034624:	e0bfea17 	ldw	r2,-88(fp)
+ 8034628:	10801e17 	ldw	r2,120(r2)
+ 803462c:	10000b1e 	bne	r2,zero,803465c <tcp_output+0xdc8>
+         {
+            tp->t_rttick = cticks;
+ 8034630:	d0e07d17 	ldw	r3,-32268(gp)
+ 8034634:	e0bfea17 	ldw	r2,-88(fp)
+ 8034638:	10c01e15 	stw	r3,120(r2)
+            tp->t_rtseq = startseq;
+ 803463c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034640:	e0ffee17 	ldw	r3,-72(fp)
+ 8034644:	10c01f15 	stw	r3,124(r2)
+            tcpstat.tcps_segstimed++;
+ 8034648:	008201b4 	movhi	r2,2054
+ 803464c:	10b8aa17 	ldw	r2,-7512(r2)
+ 8034650:	10c00044 	addi	r3,r2,1
+ 8034654:	008201b4 	movhi	r2,2054
+ 8034658:	10f8aa15 	stw	r3,-7512(r2)
+       * Initial value for retransmit timer is smoothed
+       * round-trip time + 2 * round-trip time variance.
+       * Initialize shift counter which is used for backoff
+       * of retransmit time.
+       */
+      if (tp->t_timer[TCPT_REXMT] == 0 &&
+ 803465c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034660:	10800317 	ldw	r2,12(r2)
+ 8034664:	1000201e 	bne	r2,zero,80346e8 <tcp_output+0xe54>
+          tp->snd_nxt != tp->snd_una) 
+ 8034668:	e0bfea17 	ldw	r2,-88(fp)
+ 803466c:	10c00f17 	ldw	r3,60(r2)
+ 8034670:	e0bfea17 	ldw	r2,-88(fp)
+ 8034674:	10800e17 	ldw	r2,56(r2)
+      if (tp->t_timer[TCPT_REXMT] == 0 &&
+ 8034678:	18801b26 	beq	r3,r2,80346e8 <tcp_output+0xe54>
+      {
+         tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+ 803467c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034680:	10c00817 	ldw	r3,32(r2)
+ 8034684:	e0bfea17 	ldw	r2,-88(fp)
+ 8034688:	10c00315 	stw	r3,12(r2)
+         if (tp->t_timer[TCPT_PERSIST]) 
+ 803468c:	e0bfea17 	ldw	r2,-88(fp)
+ 8034690:	10800417 	ldw	r2,16(r2)
+ 8034694:	10001426 	beq	r2,zero,80346e8 <tcp_output+0xe54>
+         {
+            tp->t_timer[TCPT_PERSIST] = 0;
+ 8034698:	e0bfea17 	ldw	r2,-88(fp)
+ 803469c:	10000415 	stw	zero,16(r2)
+            tp->t_rxtshift = 0;
+ 80346a0:	e0bfea17 	ldw	r2,-88(fp)
+ 80346a4:	10000715 	stw	zero,28(r2)
+   {
+ 80346a8:	00000f06 	br	80346e8 <tcp_output+0xe54>
+         }
+      }
+   }
+   else
+   {
+      if (SEQ_GT(tp->snd_nxt + len, tp->snd_max))
+ 80346ac:	e0bfea17 	ldw	r2,-88(fp)
+ 80346b0:	10c00f17 	ldw	r3,60(r2)
+ 80346b4:	e0bfff17 	ldw	r2,-4(fp)
+ 80346b8:	1887883a 	add	r3,r3,r2
+ 80346bc:	e0bfea17 	ldw	r2,-88(fp)
+ 80346c0:	10801a17 	ldw	r2,104(r2)
+ 80346c4:	1885c83a 	sub	r2,r3,r2
+ 80346c8:	0080080e 	bge	zero,r2,80346ec <tcp_output+0xe58>
+         tp->snd_max = tp->snd_nxt + len;
+ 80346cc:	e0bfea17 	ldw	r2,-88(fp)
+ 80346d0:	10c00f17 	ldw	r3,60(r2)
+ 80346d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80346d8:	1887883a 	add	r3,r3,r2
+ 80346dc:	e0bfea17 	ldw	r2,-88(fp)
+ 80346e0:	10c01a15 	stw	r3,104(r2)
+ 80346e4:	00000106 	br	80346ec <tcp_output+0xe58>
+   {
+ 80346e8:	0001883a 	nop
+   tcp_trace("tcp_output: sending, state %d, tcpcb: %x",
+    tp->t_state, tp );
+#endif
+
+#ifdef MUTE_WARNS
+   error = 0;
+ 80346ec:	e03fed15 	stw	zero,-76(fp)
+   if(so->so_domain != AF_INET6)
+#endif   /* IP_V6 */
+   {
+      struct ip * pip;
+   
+      pip = mtod(m, struct ip *);
+ 80346f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80346f4:	10800317 	ldw	r2,12(r2)
+ 80346f8:	e0bfec15 	stw	r2,-80(fp)
+      /* Fill in IP length and send to IP level. */
+      pip->ip_len = (u_short)(TCPIPHDRSZ + optlen + len);
+ 80346fc:	e0bffb17 	ldw	r2,-20(fp)
+ 8034700:	1007883a 	mov	r3,r2
+ 8034704:	e0bfff17 	ldw	r2,-4(fp)
+ 8034708:	1885883a 	add	r2,r3,r2
+ 803470c:	10800a04 	addi	r2,r2,40
+ 8034710:	1007883a 	mov	r3,r2
+ 8034714:	e0bfec17 	ldw	r2,-80(fp)
+ 8034718:	10c0008d 	sth	r3,2(r2)
+      error = ip_output(m, so->so_optsPack);
+ 803471c:	e0bff717 	ldw	r2,-36(fp)
+ 8034720:	10801f17 	ldw	r2,124(r2)
+ 8034724:	100b883a 	mov	r5,r2
+ 8034728:	e13ffc17 	ldw	r4,-16(fp)
+ 803472c:	802a6580 	call	802a658 <ip_output>
+ 8034730:	e0bfed15 	stw	r2,-76(fp)
+                    (sizeof(struct ipv6) + sizeof(struct tcphdr) + optlen + len),
+                    (struct   ip_socopts *)0);          
+   }
+#endif   /* IP_V6 */
+
+   if (error)
+ 8034734:	e0bfed17 	ldw	r2,-76(fp)
+ 8034738:	10001326 	beq	r2,zero,8034788 <tcp_output+0xef4>
+   {
+      if (error == ENOBUFS)   /* ip_output needed a copy buffer it couldn't get */
+ 803473c:	e0bfed17 	ldw	r2,-76(fp)
+ 8034740:	10801a58 	cmpnei	r2,r2,105
+ 8034744:	10000e1e 	bne	r2,zero,8034780 <tcp_output+0xeec>
+      {
+         if (m->m_type == MT_FREE)  /* ip_output() probably freed first mbuf */
+ 8034748:	e0bffc17 	ldw	r2,-16(fp)
+ 803474c:	10800817 	ldw	r2,32(r2)
+ 8034750:	1000031e 	bne	r2,zero,8034760 <tcp_output+0xecc>
+            m = m->m_next;
+ 8034754:	e0bffc17 	ldw	r2,-16(fp)
+ 8034758:	10800617 	ldw	r2,24(r2)
+ 803475c:	e0bffc15 	stw	r2,-16(fp)
+         m_freem(m); /* free the mbuf chain */
+ 8034760:	e13ffc17 	ldw	r4,-16(fp)
+ 8034764:	8029cfc0 	call	8029cfc <m_freem>
+         tcp_quench(tp->t_inpcb);
+ 8034768:	e0bfea17 	ldw	r2,-88(fp)
+ 803476c:	10800d17 	ldw	r2,52(r2)
+ 8034770:	1009883a 	mov	r4,r2
+ 8034774:	80351d00 	call	80351d0 <tcp_quench>
+         return (error);
+ 8034778:	e0bfed17 	ldw	r2,-76(fp)
+ 803477c:	00002706 	br	803481c <tcp_output+0xf88>
+      }
+      return (error);
+ 8034780:	e0bfed17 	ldw	r2,-76(fp)
+ 8034784:	00002506 	br	803481c <tcp_output+0xf88>
+
+   /*
+    * Data sent (as far as we can tell).
+    */
+
+   TCP_MIB_INC(tcpOutSegs);   /* keep MIB stats */
+ 8034788:	008201b4 	movhi	r2,2054
+ 803478c:	10b88017 	ldw	r2,-7680(r2)
+ 8034790:	10c00044 	addi	r3,r2,1
+ 8034794:	008201b4 	movhi	r2,2054
+ 8034798:	10f88015 	stw	r3,-7680(r2)
+   tcpstat.tcps_sndtotal++;
+ 803479c:	008201b4 	movhi	r2,2054
+ 80347a0:	10b8b317 	ldw	r2,-7476(r2)
+ 80347a4:	10c00044 	addi	r3,r2,1
+ 80347a8:	008201b4 	movhi	r2,2054
+ 80347ac:	10f8b315 	stw	r3,-7476(r2)
+   /*
+    * If this advertises a larger window than any other segment,
+    * then remember the size of the advertised window.
+    * Any pending ACK has now been sent.
+    */
+   if (win > 0 && SEQ_GT(tp->rcv_nxt+win, tp->rcv_adv))
+ 80347b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80347b4:	00800e0e 	bge	zero,r2,80347f0 <tcp_output+0xf5c>
+ 80347b8:	e0bfea17 	ldw	r2,-88(fp)
+ 80347bc:	10c01617 	ldw	r3,88(r2)
+ 80347c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80347c4:	1887883a 	add	r3,r3,r2
+ 80347c8:	e0bfea17 	ldw	r2,-88(fp)
+ 80347cc:	10801917 	ldw	r2,100(r2)
+ 80347d0:	1885c83a 	sub	r2,r3,r2
+ 80347d4:	0080060e 	bge	zero,r2,80347f0 <tcp_output+0xf5c>
+      tp->rcv_adv = tp->rcv_nxt + (unsigned)win;
+ 80347d8:	e0bfea17 	ldw	r2,-88(fp)
+ 80347dc:	10c01617 	ldw	r3,88(r2)
+ 80347e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80347e4:	1887883a 	add	r3,r3,r2
+ 80347e8:	e0bfea17 	ldw	r2,-88(fp)
+ 80347ec:	10c01915 	stw	r3,100(r2)
+   tp->t_flags &= ~(TF_ACKNOW|TF_SACKNOW|TF_DELACK);
+ 80347f0:	e0bfea17 	ldw	r2,-88(fp)
+ 80347f4:	10c00b0b 	ldhu	r3,44(r2)
+ 80347f8:	00bfef04 	movi	r2,-68
+ 80347fc:	1884703a 	and	r2,r3,r2
+ 8034800:	1007883a 	mov	r3,r2
+ 8034804:	e0bfea17 	ldw	r2,-88(fp)
+ 8034808:	10c00b0d 	sth	r3,44(r2)
+   if (sendalot)
+ 803480c:	e0bffa17 	ldw	r2,-24(fp)
+ 8034810:	10000126 	beq	r2,zero,8034818 <tcp_output+0xf84>
+      goto again;
+ 8034814:	003c3006 	br	80338d8 <tcp_output+0x44>
+   return (0);
+ 8034818:	0005883a 	mov	r2,zero
+}
+ 803481c:	e037883a 	mov	sp,fp
+ 8034820:	dfc00117 	ldw	ra,4(sp)
+ 8034824:	df000017 	ldw	fp,0(sp)
+ 8034828:	dec00204 	addi	sp,sp,8
+ 803482c:	f800283a 	ret
+
+08034830 <tcp_setpersist>:
+ * RETURNS: NA
+ */
+
+void
+tcp_setpersist(struct tcpcb * tp)
+{
+ 8034830:	defffc04 	addi	sp,sp,-16
+ 8034834:	dfc00315 	stw	ra,12(sp)
+ 8034838:	df000215 	stw	fp,8(sp)
+ 803483c:	df000204 	addi	fp,sp,8
+ 8034840:	e13ffe15 	stw	r4,-8(fp)
+   int   t;
+
+   t = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1;
+ 8034844:	e0bffe17 	ldw	r2,-8(fp)
+ 8034848:	10802017 	ldw	r2,128(r2)
+ 803484c:	1007d0ba 	srai	r3,r2,2
+ 8034850:	e0bffe17 	ldw	r2,-8(fp)
+ 8034854:	10802117 	ldw	r2,132(r2)
+ 8034858:	1885883a 	add	r2,r3,r2
+ 803485c:	1005d07a 	srai	r2,r2,1
+ 8034860:	e0bfff15 	stw	r2,-4(fp)
+
+   if (tp->t_timer[TCPT_REXMT])
+ 8034864:	e0bffe17 	ldw	r2,-8(fp)
+ 8034868:	10800317 	ldw	r2,12(r2)
+ 803486c:	10000326 	beq	r2,zero,803487c <tcp_setpersist+0x4c>
+      panic("tcp_output REXMT");
+ 8034870:	01020174 	movhi	r4,2053
+ 8034874:	212aad04 	addi	r4,r4,-21836
+ 8034878:	80271780 	call	8027178 <panic>
+   /*
+    * Start/restart persistance timer.
+    */
+   TCPT_RANGESET(tp->t_timer[TCPT_PERSIST],
+ 803487c:	e0bfff17 	ldw	r2,-4(fp)
+ 8034880:	1009883a 	mov	r4,r2
+ 8034884:	e0bffe17 	ldw	r2,-8(fp)
+ 8034888:	10c00717 	ldw	r3,28(r2)
+ 803488c:	00820174 	movhi	r2,2053
+ 8034890:	1885883a 	add	r2,r3,r2
+ 8034894:	10b20cc3 	ldbu	r2,-14285(r2)
+ 8034898:	10803fcc 	andi	r2,r2,255
+ 803489c:	2085383a 	mul	r2,r4,r2
+ 80348a0:	10ffffcc 	andi	r3,r2,65535
+ 80348a4:	18e0001c 	xori	r3,r3,32768
+ 80348a8:	18e00004 	addi	r3,r3,-32768
+ 80348ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80348b0:	10c00415 	stw	r3,16(r2)
+ 80348b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80348b8:	10800417 	ldw	r2,16(r2)
+ 80348bc:	10800288 	cmpgei	r2,r2,10
+ 80348c0:	1000041e 	bne	r2,zero,80348d4 <tcp_setpersist+0xa4>
+ 80348c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80348c8:	00c00284 	movi	r3,10
+ 80348cc:	10c00415 	stw	r3,16(r2)
+ 80348d0:	00000706 	br	80348f0 <tcp_setpersist+0xc0>
+ 80348d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80348d8:	10800417 	ldw	r2,16(r2)
+ 80348dc:	10801e50 	cmplti	r2,r2,121
+ 80348e0:	1000031e 	bne	r2,zero,80348f0 <tcp_setpersist+0xc0>
+ 80348e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80348e8:	00c01e04 	movi	r3,120
+ 80348ec:	10c00415 	stw	r3,16(r2)
+    t * tcp_backoff[tp->t_rxtshift],
+    TCPTV_PERSMIN, TCPTV_PERSMAX);
+   if (tp->t_rxtshift < TCP_MAXRXTSHIFT)
+ 80348f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80348f4:	10800717 	ldw	r2,28(r2)
+ 80348f8:	10800308 	cmpgei	r2,r2,12
+ 80348fc:	1000051e 	bne	r2,zero,8034914 <tcp_setpersist+0xe4>
+      tp->t_rxtshift++;
+ 8034900:	e0bffe17 	ldw	r2,-8(fp)
+ 8034904:	10800717 	ldw	r2,28(r2)
+ 8034908:	10c00044 	addi	r3,r2,1
+ 803490c:	e0bffe17 	ldw	r2,-8(fp)
+ 8034910:	10c00715 	stw	r3,28(r2)
+
+}
+ 8034914:	0001883a 	nop
+ 8034918:	e037883a 	mov	sp,fp
+ 803491c:	dfc00117 	ldw	ra,4(sp)
+ 8034920:	df000017 	ldw	fp,0(sp)
+ 8034924:	dec00204 	addi	sp,sp,8
+ 8034928:	f800283a 	ret
+
+0803492c <bld_options>:
+ * RETURNS: length of option data added to buffer
+ */
+
+static int
+bld_options(struct tcpcb * tp, u_char * cp, int flags, struct socket * so)
+{
+ 803492c:	defff804 	addi	sp,sp,-32
+ 8034930:	dfc00715 	stw	ra,28(sp)
+ 8034934:	df000615 	stw	fp,24(sp)
+ 8034938:	df000604 	addi	fp,sp,24
+ 803493c:	e13ffd15 	stw	r4,-12(fp)
+ 8034940:	e17ffc15 	stw	r5,-16(fp)
+ 8034944:	e1bffb15 	stw	r6,-20(fp)
+ 8034948:	e1fffa15 	stw	r7,-24(fp)
+   int      len;
+   u_short  mss;
+
+   if(tp->t_flags & TF_NOOPT)    /* no options allowed? */
+ 803494c:	e0bffd17 	ldw	r2,-12(fp)
+ 8034950:	10800b0b 	ldhu	r2,44(r2)
+ 8034954:	10bfffcc 	andi	r2,r2,65535
+ 8034958:	1080020c 	andi	r2,r2,8
+ 803495c:	10000226 	beq	r2,zero,8034968 <bld_options+0x3c>
+      return 0;
+ 8034960:	0005883a 	mov	r2,zero
+ 8034964:	00001f06 	br	80349e4 <bld_options+0xb8>
+
+   /* Alway put MSS option on SYN packets */
+   if (flags & TH_SYN)
+ 8034968:	e0bffb17 	ldw	r2,-20(fp)
+ 803496c:	1080008c 	andi	r2,r2,2
+ 8034970:	10001a26 	beq	r2,zero,80349dc <bld_options+0xb0>
+   {
+      mss   =  (u_short)tcp_mss(so);
+ 8034974:	e13ffa17 	ldw	r4,-24(fp)
+ 8034978:	803379c0 	call	803379c <tcp_mss>
+ 803497c:	e0bffe8d 	sth	r2,-6(fp)
+
+      /* always send MSS option on SYN, fill in MSS parm */
+      *(cp + 0) = TCPOPT_MAXSEG;
+ 8034980:	e0bffc17 	ldw	r2,-16(fp)
+ 8034984:	00c00084 	movi	r3,2
+ 8034988:	10c00005 	stb	r3,0(r2)
+      *(cp + 1) = MSSOPT_LEN;               /* length byte */
+ 803498c:	e0bffc17 	ldw	r2,-16(fp)
+ 8034990:	10800044 	addi	r2,r2,1
+ 8034994:	00c00104 	movi	r3,4
+ 8034998:	10c00005 	stb	r3,0(r2)
+      *(cp + 2)  = (u_char) ((mss & 0xff00) >> 8);
+ 803499c:	e0bffe8b 	ldhu	r2,-6(fp)
+ 80349a0:	1004d23a 	srli	r2,r2,8
+ 80349a4:	1007883a 	mov	r3,r2
+ 80349a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80349ac:	10800084 	addi	r2,r2,2
+ 80349b0:	10c00005 	stb	r3,0(r2)
+      *(cp + 3)  = (u_char) (mss & 0xff);
+ 80349b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80349b8:	108000c4 	addi	r2,r2,3
+ 80349bc:	e0fffe8b 	ldhu	r3,-6(fp)
+ 80349c0:	10c00005 	stb	r3,0(r2)
+      len = 4;
+ 80349c4:	00800104 	movi	r2,4
+ 80349c8:	e0bfff15 	stw	r2,-4(fp)
+      cp += 4;
+ 80349cc:	e0bffc17 	ldw	r2,-16(fp)
+ 80349d0:	10800104 	addi	r2,r2,4
+ 80349d4:	e0bffc15 	stw	r2,-16(fp)
+ 80349d8:	00000106 	br	80349e0 <bld_options+0xb4>
+   }
+   else
+      len = 0;
+ 80349dc:	e03fff15 	stw	zero,-4(fp)
+      len += 10;
+   }
+#endif   /* TCP_TIMESTAMP */
+
+   USE_ARG(so);
+   return len;
+ 80349e0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80349e4:	e037883a 	mov	sp,fp
+ 80349e8:	dfc00117 	ldw	ra,4(sp)
+ 80349ec:	df000017 	ldw	fp,0(sp)
+ 80349f0:	dec00204 	addi	sp,sp,8
+ 80349f4:	f800283a 	ret
+
+080349f8 <tcp_init>:
+ * RETURNS: 
+ */
+
+void
+tcp_init()
+{
+ 80349f8:	deffff04 	addi	sp,sp,-4
+ 80349fc:	df000015 	stw	fp,0(sp)
+ 8034a00:	d839883a 	mov	fp,sp
+   tcp_iss = 1;      /* wrong */
+ 8034a04:	00800044 	movi	r2,1
+ 8034a08:	d0a08a15 	stw	r2,-32216(gp)
+   tcb.inp_next = tcb.inp_prev = &tcb;
+ 8034a0c:	008201b4 	movhi	r2,2054
+ 8034a10:	10b89904 	addi	r2,r2,-7580
+ 8034a14:	00c201b4 	movhi	r3,2054
+ 8034a18:	18b89a15 	stw	r2,-7576(r3)
+ 8034a1c:	008201b4 	movhi	r2,2054
+ 8034a20:	10f89a17 	ldw	r3,-7576(r2)
+ 8034a24:	008201b4 	movhi	r2,2054
+ 8034a28:	10f89915 	stw	r3,-7580(r2)
+}
+ 8034a2c:	0001883a 	nop
+ 8034a30:	e037883a 	mov	sp,fp
+ 8034a34:	df000017 	ldw	fp,0(sp)
+ 8034a38:	dec00104 	addi	sp,sp,4
+ 8034a3c:	f800283a 	ret
+
+08034a40 <tcp_template>:
+ * RETURNS: 
+ */
+
+struct tcpiphdr * 
+tcp_template(struct tcpcb * tp)
+{
+ 8034a40:	defffb04 	addi	sp,sp,-20
+ 8034a44:	dfc00415 	stw	ra,16(sp)
+ 8034a48:	df000315 	stw	fp,12(sp)
+ 8034a4c:	df000304 	addi	fp,sp,12
+ 8034a50:	e13ffd15 	stw	r4,-12(fp)
+   struct inpcb * inp   =  tp->t_inpcb;
+ 8034a54:	e0bffd17 	ldw	r2,-12(fp)
+ 8034a58:	10800d17 	ldw	r2,52(r2)
+ 8034a5c:	e0bffe15 	stw	r2,-8(fp)
+   struct tcpiphdr * n;
+
+   if ((n = tp->t_template) == 0)
+ 8034a60:	e0bffd17 	ldw	r2,-12(fp)
+ 8034a64:	10800c17 	ldw	r2,48(r2)
+ 8034a68:	e0bfff15 	stw	r2,-4(fp)
+ 8034a6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8034a70:	1000071e 	bne	r2,zero,8034a90 <tcp_template+0x50>
+   {
+      n = (struct tcpiphdr *)TPH_ALLOC (sizeof (*n));
+ 8034a74:	01000a04 	movi	r4,40
+ 8034a78:	802982c0 	call	802982c <npalloc>
+ 8034a7c:	e0bfff15 	stw	r2,-4(fp)
+      if (n == NULL)
+ 8034a80:	e0bfff17 	ldw	r2,-4(fp)
+ 8034a84:	1000021e 	bne	r2,zero,8034a90 <tcp_template+0x50>
+         return (0);
+ 8034a88:	0005883a 	mov	r2,zero
+ 8034a8c:	00002906 	br	8034b34 <tcp_template+0xf4>
+   }
+   n->ti_next = n->ti_prev = 0;
+ 8034a90:	e0bfff17 	ldw	r2,-4(fp)
+ 8034a94:	10000115 	stw	zero,4(r2)
+ 8034a98:	e0bfff17 	ldw	r2,-4(fp)
+ 8034a9c:	10c00117 	ldw	r3,4(r2)
+ 8034aa0:	e0bfff17 	ldw	r2,-4(fp)
+ 8034aa4:	10c00015 	stw	r3,0(r2)
+   n->ti_len = htons(sizeof (struct tcpiphdr) - sizeof (struct ip));
+ 8034aa8:	e0bfff17 	ldw	r2,-4(fp)
+ 8034aac:	00c50004 	movi	r3,5120
+ 8034ab0:	10c0028d 	sth	r3,10(r2)
+   n->ti_src = inp->inp_laddr;
+ 8034ab4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034ab8:	e0fffe17 	ldw	r3,-8(fp)
+ 8034abc:	18c00417 	ldw	r3,16(r3)
+ 8034ac0:	10c00315 	stw	r3,12(r2)
+   n->ti_dst = inp->inp_faddr;
+ 8034ac4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034ac8:	e0fffe17 	ldw	r3,-8(fp)
+ 8034acc:	18c00317 	ldw	r3,12(r3)
+ 8034ad0:	10c00415 	stw	r3,16(r2)
+   n->ti_sport = inp->inp_lport;
+ 8034ad4:	e0bffe17 	ldw	r2,-8(fp)
+ 8034ad8:	10c0078b 	ldhu	r3,30(r2)
+ 8034adc:	e0bfff17 	ldw	r2,-4(fp)
+ 8034ae0:	10c0050d 	sth	r3,20(r2)
+   n->ti_dport = inp->inp_fport;
+ 8034ae4:	e0bffe17 	ldw	r2,-8(fp)
+ 8034ae8:	10c0070b 	ldhu	r3,28(r2)
+ 8034aec:	e0bfff17 	ldw	r2,-4(fp)
+ 8034af0:	10c0058d 	sth	r3,22(r2)
+   n->ti_seq = 0;
+ 8034af4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034af8:	10000615 	stw	zero,24(r2)
+   n->ti_ack = 0;
+ 8034afc:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b00:	10000715 	stw	zero,28(r2)
+   n->ti_t.th_doff = (5 << 4);   /* NetPort */
+ 8034b04:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b08:	00c01404 	movi	r3,80
+ 8034b0c:	10c00805 	stb	r3,32(r2)
+   n->ti_flags = 0;
+ 8034b10:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b14:	10000845 	stb	zero,33(r2)
+   n->ti_win = 0;
+ 8034b18:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b1c:	1000088d 	sth	zero,34(r2)
+   n->ti_sum = 0;
+ 8034b20:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b24:	1000090d 	sth	zero,36(r2)
+   n->ti_urp = 0;
+ 8034b28:	e0bfff17 	ldw	r2,-4(fp)
+ 8034b2c:	1000098d 	sth	zero,38(r2)
+   return (n);
+ 8034b30:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8034b34:	e037883a 	mov	sp,fp
+ 8034b38:	dfc00117 	ldw	ra,4(sp)
+ 8034b3c:	df000017 	ldw	fp,0(sp)
+ 8034b40:	dec00204 	addi	sp,sp,8
+ 8034b44:	f800283a 	ret
+
+08034b48 <tcp_respond>:
+   struct tcpiphdr * ti,
+   tcp_seq  ack,
+   tcp_seq  seq,
+   int   flags,
+   struct mbuf *  ti_mbuf)
+{
+ 8034b48:	defff204 	addi	sp,sp,-56
+ 8034b4c:	dfc00d15 	stw	ra,52(sp)
+ 8034b50:	df000c15 	stw	fp,48(sp)
+ 8034b54:	df000c04 	addi	fp,sp,48
+ 8034b58:	e13ff715 	stw	r4,-36(fp)
+ 8034b5c:	e17ff615 	stw	r5,-40(fp)
+ 8034b60:	e1bff515 	stw	r6,-44(fp)
+ 8034b64:	e1fff415 	stw	r7,-48(fp)
+   int      tlen;       /* tcp data len - 0 or 1 */
+   int      domain;     /* AF_INET or AF_INET6 */
+   int      win = 0;    /* window to use in sent packet */
+ 8034b68:	e03ffd15 	stw	zero,-12(fp)
+   struct mbuf *  m;    /* mbuf to send */
+   struct tcpiphdr * tmp_thdr;   /* scratch */
+
+   if (tp)
+ 8034b6c:	e0bff717 	ldw	r2,-36(fp)
+ 8034b70:	10001726 	beq	r2,zero,8034bd0 <tcp_respond+0x88>
+      win = (int)sbspace(&tp->t_inpcb->inp_socket->so_rcv);
+ 8034b74:	e0bff717 	ldw	r2,-36(fp)
+ 8034b78:	10800d17 	ldw	r2,52(r2)
+ 8034b7c:	10800817 	ldw	r2,32(r2)
+ 8034b80:	10800b17 	ldw	r2,44(r2)
+ 8034b84:	1007883a 	mov	r3,r2
+ 8034b88:	e0bff717 	ldw	r2,-36(fp)
+ 8034b8c:	10800d17 	ldw	r2,52(r2)
+ 8034b90:	10800817 	ldw	r2,32(r2)
+ 8034b94:	10800a17 	ldw	r2,40(r2)
+ 8034b98:	1885c83a 	sub	r2,r3,r2
+ 8034b9c:	10000a16 	blt	r2,zero,8034bc8 <tcp_respond+0x80>
+ 8034ba0:	e0bff717 	ldw	r2,-36(fp)
+ 8034ba4:	10800d17 	ldw	r2,52(r2)
+ 8034ba8:	10800817 	ldw	r2,32(r2)
+ 8034bac:	10c00b17 	ldw	r3,44(r2)
+ 8034bb0:	e0bff717 	ldw	r2,-36(fp)
+ 8034bb4:	10800d17 	ldw	r2,52(r2)
+ 8034bb8:	10800817 	ldw	r2,32(r2)
+ 8034bbc:	10800a17 	ldw	r2,40(r2)
+ 8034bc0:	1885c83a 	sub	r2,r3,r2
+ 8034bc4:	00000106 	br	8034bcc <tcp_respond+0x84>
+ 8034bc8:	0005883a 	mov	r2,zero
+ 8034bcc:	e0bffd15 	stw	r2,-12(fp)
+
+   /* Figure out of we can recycle the passed buffer or if we need a 
+    * new one. Construct the easy parts of the the TCP and IP headers.
+    */
+   if (flags == 0)   /* sending keepalive from timer */
+ 8034bd0:	e0800217 	ldw	r2,8(fp)
+ 8034bd4:	1000261e 	bne	r2,zero,8034c70 <tcp_respond+0x128>
+   {
+      /* no flags == need a new buffer */
+      m = m_getwithdata (MT_HEADER, 64);
+ 8034bd8:	01401004 	movi	r5,64
+ 8034bdc:	010000c4 	movi	r4,3
+ 8034be0:	8029a700 	call	8029a70 <m_getnbuf>
+ 8034be4:	e0bffc15 	stw	r2,-16(fp)
+      if (m == NULL)
+ 8034be8:	e0bffc17 	ldw	r2,-16(fp)
+ 8034bec:	1000ce26 	beq	r2,zero,8034f28 <tcp_respond+0x3e0>
+         return;
+      tlen = 1;   /* Keepalives have one byte of data */
+ 8034bf0:	00800044 	movi	r2,1
+ 8034bf4:	e0bfff15 	stw	r2,-4(fp)
+      m->m_len = TCPIPHDRSZ + tlen;
+ 8034bf8:	e0bfff17 	ldw	r2,-4(fp)
+ 8034bfc:	10800a04 	addi	r2,r2,40
+ 8034c00:	1007883a 	mov	r3,r2
+ 8034c04:	e0bffc17 	ldw	r2,-16(fp)
+ 8034c08:	10c00215 	stw	r3,8(r2)
+      /*
+       * Copy template contents into the mbuf and set ti to point
+       * to the header structure in the mbuf.
+       */
+      tmp_thdr = (struct tcpiphdr *)((char *)m->m_data+sizeof(struct ip)
+ 8034c0c:	e0bffc17 	ldw	r2,-16(fp)
+ 8034c10:	10800317 	ldw	r2,12(r2)
+ 8034c14:	e0bffb15 	stw	r2,-20(fp)
+         - sizeof(struct ipovly));
+      if ((char *)tmp_thdr < m->pkt->nb_buff)
+ 8034c18:	e0bffc17 	ldw	r2,-16(fp)
+ 8034c1c:	10800117 	ldw	r2,4(r2)
+ 8034c20:	10800117 	ldw	r2,4(r2)
+ 8034c24:	e0fffb17 	ldw	r3,-20(fp)
+ 8034c28:	1880032e 	bgeu	r3,r2,8034c38 <tcp_respond+0xf0>
+      {
+         panic("tcp_respond- packet ptr underflow\n");
+ 8034c2c:	01020174 	movhi	r4,2053
+ 8034c30:	212ab204 	addi	r4,r4,-21816
+ 8034c34:	80271780 	call	8027178 <panic>
+      }
+      MEMCPY(tmp_thdr, ti, sizeof(struct tcpiphdr));
+ 8034c38:	01800a04 	movi	r6,40
+ 8034c3c:	e17ff617 	ldw	r5,-40(fp)
+ 8034c40:	e13ffb17 	ldw	r4,-20(fp)
+ 8034c44:	80086b80 	call	80086b8 <memcpy>
+      ti = tmp_thdr;
+ 8034c48:	e0bffb17 	ldw	r2,-20(fp)
+ 8034c4c:	e0bff615 	stw	r2,-40(fp)
+      flags = TH_ACK;
+ 8034c50:	00800404 	movi	r2,16
+ 8034c54:	e0800215 	stw	r2,8(fp)
+      domain = tp->t_inpcb->inp_socket->so_domain;
+ 8034c58:	e0bff717 	ldw	r2,-36(fp)
+ 8034c5c:	10800d17 	ldw	r2,52(r2)
+ 8034c60:	10800817 	ldw	r2,32(r2)
+ 8034c64:	10800517 	ldw	r2,20(r2)
+ 8034c68:	e0bffe15 	stw	r2,-8(fp)
+ 8034c6c:	00003906 	br	8034d54 <tcp_respond+0x20c>
+   }
+   else  /* Flag was passed (e.g. reset); recycle passed mbuf */
+   {
+      m = ti_mbuf;   /*dtom(ti);*/
+ 8034c70:	e0800317 	ldw	r2,12(fp)
+ 8034c74:	e0bffc15 	stw	r2,-16(fp)
+      if(m->pkt->type == IPTP)   /* IPv4 packet */
+ 8034c78:	e0bffc17 	ldw	r2,-16(fp)
+ 8034c7c:	10800117 	ldw	r2,4(r2)
+ 8034c80:	1080080b 	ldhu	r2,32(r2)
+ 8034c84:	10bfffcc 	andi	r2,r2,65535
+ 8034c88:	10800218 	cmpnei	r2,r2,8
+ 8034c8c:	1000031e 	bne	r2,zero,8034c9c <tcp_respond+0x154>
+         domain = AF_INET;
+ 8034c90:	00800084 	movi	r2,2
+ 8034c94:	e0bffe15 	stw	r2,-8(fp)
+ 8034c98:	00000206 	br	8034ca4 <tcp_respond+0x15c>
+      else
+         domain = AF_INET6;
+ 8034c9c:	008000c4 	movi	r2,3
+ 8034ca0:	e0bffe15 	stw	r2,-8(fp)
+
+      m_freem(m->m_next);
+ 8034ca4:	e0bffc17 	ldw	r2,-16(fp)
+ 8034ca8:	10800617 	ldw	r2,24(r2)
+ 8034cac:	1009883a 	mov	r4,r2
+ 8034cb0:	8029cfc0 	call	8029cfc <m_freem>
+      m->m_next = 0;
+ 8034cb4:	e0bffc17 	ldw	r2,-16(fp)
+ 8034cb8:	10000615 	stw	zero,24(r2)
+      tlen = 0;         /* NO data */
+ 8034cbc:	e03fff15 	stw	zero,-4(fp)
+      m->m_len = TCPIPHDRSZ;
+ 8034cc0:	e0bffc17 	ldw	r2,-16(fp)
+ 8034cc4:	00c00a04 	movi	r3,40
+ 8034cc8:	10c00215 	stw	r3,8(r2)
+      xchg(ti->ti_dport, ti->ti_sport, u_short);
+ 8034ccc:	e0bff617 	ldw	r2,-40(fp)
+ 8034cd0:	1080058b 	ldhu	r2,22(r2)
+ 8034cd4:	e0bffa8d 	sth	r2,-22(fp)
+ 8034cd8:	e0bff617 	ldw	r2,-40(fp)
+ 8034cdc:	10c0050b 	ldhu	r3,20(r2)
+ 8034ce0:	e0bff617 	ldw	r2,-40(fp)
+ 8034ce4:	10c0058d 	sth	r3,22(r2)
+ 8034ce8:	e0bff617 	ldw	r2,-40(fp)
+ 8034cec:	e0fffa8b 	ldhu	r3,-22(fp)
+ 8034cf0:	10c0050d 	sth	r3,20(r2)
+      if(m->pkt->type == IPTP)
+ 8034cf4:	e0bffc17 	ldw	r2,-16(fp)
+ 8034cf8:	10800117 	ldw	r2,4(r2)
+ 8034cfc:	1080080b 	ldhu	r2,32(r2)
+ 8034d00:	10bfffcc 	andi	r2,r2,65535
+ 8034d04:	10800218 	cmpnei	r2,r2,8
+ 8034d08:	10000a1e 	bne	r2,zero,8034d34 <tcp_respond+0x1ec>
+         xchg(ti->ti_dst.s_addr, ti->ti_src.s_addr, u_long);
+ 8034d0c:	e0bff617 	ldw	r2,-40(fp)
+ 8034d10:	10800417 	ldw	r2,16(r2)
+ 8034d14:	e0bff915 	stw	r2,-28(fp)
+ 8034d18:	e0bff617 	ldw	r2,-40(fp)
+ 8034d1c:	10c00317 	ldw	r3,12(r2)
+ 8034d20:	e0bff617 	ldw	r2,-40(fp)
+ 8034d24:	10c00415 	stw	r3,16(r2)
+ 8034d28:	e0bff617 	ldw	r2,-40(fp)
+ 8034d2c:	e0fff917 	ldw	r3,-28(fp)
+ 8034d30:	10c00315 	stw	r3,12(r2)
+      if (flags & TH_RST)  /* count resets in MIB */
+ 8034d34:	e0800217 	ldw	r2,8(fp)
+ 8034d38:	1080010c 	andi	r2,r2,4
+ 8034d3c:	10000526 	beq	r2,zero,8034d54 <tcp_respond+0x20c>
+         TCP_MIB_INC(tcpOutRsts);   /* keep MIB stats */
+ 8034d40:	008201b4 	movhi	r2,2054
+ 8034d44:	10b88417 	ldw	r2,-7664(r2)
+ 8034d48:	10c00044 	addi	r3,r2,1
+ 8034d4c:	008201b4 	movhi	r2,2054
+ 8034d50:	10f88415 	stw	r3,-7664(r2)
+   }
+
+   /* finish constructing the TCP header */
+   ti->ti_seq = htonl(seq);
+ 8034d54:	e0bff417 	ldw	r2,-48(fp)
+ 8034d58:	1006d63a 	srli	r3,r2,24
+ 8034d5c:	e0bff417 	ldw	r2,-48(fp)
+ 8034d60:	1004d23a 	srli	r2,r2,8
+ 8034d64:	10bfc00c 	andi	r2,r2,65280
+ 8034d68:	1886b03a 	or	r3,r3,r2
+ 8034d6c:	e0bff417 	ldw	r2,-48(fp)
+ 8034d70:	1004923a 	slli	r2,r2,8
+ 8034d74:	10803fec 	andhi	r2,r2,255
+ 8034d78:	1886b03a 	or	r3,r3,r2
+ 8034d7c:	e0bff417 	ldw	r2,-48(fp)
+ 8034d80:	1004963a 	slli	r2,r2,24
+ 8034d84:	1886b03a 	or	r3,r3,r2
+ 8034d88:	e0bff617 	ldw	r2,-40(fp)
+ 8034d8c:	10c00615 	stw	r3,24(r2)
+   ti->ti_ack = htonl(ack);
+ 8034d90:	e0bff517 	ldw	r2,-44(fp)
+ 8034d94:	1006d63a 	srli	r3,r2,24
+ 8034d98:	e0bff517 	ldw	r2,-44(fp)
+ 8034d9c:	1004d23a 	srli	r2,r2,8
+ 8034da0:	10bfc00c 	andi	r2,r2,65280
+ 8034da4:	1886b03a 	or	r3,r3,r2
+ 8034da8:	e0bff517 	ldw	r2,-44(fp)
+ 8034dac:	1004923a 	slli	r2,r2,8
+ 8034db0:	10803fec 	andhi	r2,r2,255
+ 8034db4:	1886b03a 	or	r3,r3,r2
+ 8034db8:	e0bff517 	ldw	r2,-44(fp)
+ 8034dbc:	1004963a 	slli	r2,r2,24
+ 8034dc0:	1886b03a 	or	r3,r3,r2
+ 8034dc4:	e0bff617 	ldw	r2,-40(fp)
+ 8034dc8:	10c00715 	stw	r3,28(r2)
+   ti->ti_t.th_doff = 0x50;      /* NetPort: init data offset bits */
+ 8034dcc:	e0bff617 	ldw	r2,-40(fp)
+ 8034dd0:	00c01404 	movi	r3,80
+ 8034dd4:	10c00805 	stb	r3,32(r2)
+   ti->ti_flags = (u_char)flags;
+ 8034dd8:	e0800217 	ldw	r2,8(fp)
+ 8034ddc:	1007883a 	mov	r3,r2
+ 8034de0:	e0bff617 	ldw	r2,-40(fp)
+ 8034de4:	10c00845 	stb	r3,33(r2)
+   ti->ti_win = htons((u_short)win);
+ 8034de8:	e0bffd17 	ldw	r2,-12(fp)
+ 8034dec:	10bfffcc 	andi	r2,r2,65535
+ 8034df0:	1004d23a 	srli	r2,r2,8
+ 8034df4:	1007883a 	mov	r3,r2
+ 8034df8:	e0bffd17 	ldw	r2,-12(fp)
+ 8034dfc:	10bfffcc 	andi	r2,r2,65535
+ 8034e00:	1004923a 	slli	r2,r2,8
+ 8034e04:	1884b03a 	or	r2,r3,r2
+ 8034e08:	1007883a 	mov	r3,r2
+ 8034e0c:	e0bff617 	ldw	r2,-40(fp)
+ 8034e10:	10c0088d 	sth	r3,34(r2)
+   ti->ti_urp = 0;
+ 8034e14:	e0bff617 	ldw	r2,-40(fp)
+ 8034e18:	1000098d 	sth	zero,38(r2)
+
+   /* Finish constructing IP header and send, based on IP type in use */
+   switch(domain)
+ 8034e1c:	e0bffe17 	ldw	r2,-8(fp)
+ 8034e20:	10800098 	cmpnei	r2,r2,2
+ 8034e24:	10003c1e 	bne	r2,zero,8034f18 <tcp_respond+0x3d0>
+#ifdef IP_V4
+      case AF_INET:
+      {
+         struct ip * pip;
+
+         pip = (struct ip *)((char*)ti+sizeof(struct ipovly)-sizeof(struct ip));
+ 8034e28:	e0bff617 	ldw	r2,-40(fp)
+ 8034e2c:	e0bff815 	stw	r2,-32(fp)
+
+         pip->ip_len = (unshort)(TCPIPHDRSZ + tlen);
+ 8034e30:	e0bfff17 	ldw	r2,-4(fp)
+ 8034e34:	10800a04 	addi	r2,r2,40
+ 8034e38:	1007883a 	mov	r3,r2
+ 8034e3c:	e0bff817 	ldw	r2,-32(fp)
+ 8034e40:	10c0008d 	sth	r3,2(r2)
+         /* If our system's max. MAC header size is geater than the size 
+          * of the MAC header in the received packet then we need to 
+          * adjust the IP header offset to allow for this. Since the packets 
+          * are only headers they should always fit.
+          */
+         if(pip >= (struct ip *)(m->pkt->nb_buff + MaxLnh))
+ 8034e44:	e0bffc17 	ldw	r2,-16(fp)
+ 8034e48:	10800117 	ldw	r2,4(r2)
+ 8034e4c:	10800117 	ldw	r2,4(r2)
+ 8034e50:	d0e06417 	ldw	r3,-32368(gp)
+ 8034e54:	10c5883a 	add	r2,r2,r3
+ 8034e58:	e0fff817 	ldw	r3,-32(fp)
+ 8034e5c:	18800436 	bltu	r3,r2,8034e70 <tcp_respond+0x328>
+         {
+            m->m_data = (char*)pip; /* headers will fit, just set pointer */
+ 8034e60:	e0bffc17 	ldw	r2,-16(fp)
+ 8034e64:	e0fff817 	ldw	r3,-32(fp)
+ 8034e68:	10c00315 	stw	r3,12(r2)
+ 8034e6c:	00001206 	br	8034eb8 <tcp_respond+0x370>
+         }
+         else     /* MAC may not fit, adjust pointer and move headers back */
+         {
+            m->m_data = m->pkt->nb_prot = m->pkt->nb_buff + MaxLnh;  /* new ptr */
+ 8034e70:	e0bffc17 	ldw	r2,-16(fp)
+ 8034e74:	10800117 	ldw	r2,4(r2)
+ 8034e78:	10c00117 	ldw	r3,4(r2)
+ 8034e7c:	d0a06417 	ldw	r2,-32368(gp)
+ 8034e80:	1009883a 	mov	r4,r2
+ 8034e84:	e0bffc17 	ldw	r2,-16(fp)
+ 8034e88:	10800117 	ldw	r2,4(r2)
+ 8034e8c:	1907883a 	add	r3,r3,r4
+ 8034e90:	10c00315 	stw	r3,12(r2)
+ 8034e94:	10c00317 	ldw	r3,12(r2)
+ 8034e98:	e0bffc17 	ldw	r2,-16(fp)
+ 8034e9c:	10c00315 	stw	r3,12(r2)
+            MEMMOVE(m->m_data, pip, TCPIPHDRSZ);  /* move back tcp/ip headers */
+ 8034ea0:	e0bffc17 	ldw	r2,-16(fp)
+ 8034ea4:	10800317 	ldw	r2,12(r2)
+ 8034ea8:	01800a04 	movi	r6,40
+ 8034eac:	e17ff817 	ldw	r5,-32(fp)
+ 8034eb0:	1009883a 	mov	r4,r2
+ 8034eb4:	80087b80 	call	80087b8 <memmove>
+
+         /*
+          * In the case of a SYN DOS attack, many RST|ACK replies
+          *   have no tp structure and need to be freed.
+          */
+         if (!tp)
+ 8034eb8:	e0bff717 	ldw	r2,-36(fp)
+ 8034ebc:	1000031e 	bne	r2,zero,8034ecc <tcp_respond+0x384>
+              m_freem(m);
+ 8034ec0:	e13ffc17 	ldw	r4,-16(fp)
+ 8034ec4:	8029cfc0 	call	8029cfc <m_freem>
+				ip_output(m, tp->t_inpcb->inp_socket->so_optsPack);
+			 else
+				ip_output(m, (struct   ip_socopts *)NULL);
+		 }
+
+         break;
+ 8034ec8:	00001506 	br	8034f20 <tcp_respond+0x3d8>
+			 if ((tp->t_inpcb) && (tp->t_inpcb->inp_socket))
+ 8034ecc:	e0bff717 	ldw	r2,-36(fp)
+ 8034ed0:	10800d17 	ldw	r2,52(r2)
+ 8034ed4:	10000c26 	beq	r2,zero,8034f08 <tcp_respond+0x3c0>
+ 8034ed8:	e0bff717 	ldw	r2,-36(fp)
+ 8034edc:	10800d17 	ldw	r2,52(r2)
+ 8034ee0:	10800817 	ldw	r2,32(r2)
+ 8034ee4:	10000826 	beq	r2,zero,8034f08 <tcp_respond+0x3c0>
+				ip_output(m, tp->t_inpcb->inp_socket->so_optsPack);
+ 8034ee8:	e0bff717 	ldw	r2,-36(fp)
+ 8034eec:	10800d17 	ldw	r2,52(r2)
+ 8034ef0:	10800817 	ldw	r2,32(r2)
+ 8034ef4:	10801f17 	ldw	r2,124(r2)
+ 8034ef8:	100b883a 	mov	r5,r2
+ 8034efc:	e13ffc17 	ldw	r4,-16(fp)
+ 8034f00:	802a6580 	call	802a658 <ip_output>
+         break;
+ 8034f04:	00000606 	br	8034f20 <tcp_respond+0x3d8>
+				ip_output(m, (struct   ip_socopts *)NULL);
+ 8034f08:	000b883a 	mov	r5,zero
+ 8034f0c:	e13ffc17 	ldw	r4,-16(fp)
+ 8034f10:	802a6580 	call	802a658 <ip_output>
+         break;
+ 8034f14:	00000206 	br	8034f20 <tcp_respond+0x3d8>
+
+         break;
+      }
+#endif   /* IP_V6 */
+      default:
+         dtrap();
+ 8034f18:	8028cd40 	call	8028cd4 <dtrap>
+         break;
+ 8034f1c:	0001883a 	nop
+   }
+   return;
+ 8034f20:	0001883a 	nop
+ 8034f24:	00000106 	br	8034f2c <tcp_respond+0x3e4>
+         return;
+ 8034f28:	0001883a 	nop
+}
+ 8034f2c:	e037883a 	mov	sp,fp
+ 8034f30:	dfc00117 	ldw	ra,4(sp)
+ 8034f34:	df000017 	ldw	fp,0(sp)
+ 8034f38:	dec00204 	addi	sp,sp,8
+ 8034f3c:	f800283a 	ret
+
+08034f40 <tcp_newtcpcb>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_newtcpcb(struct inpcb * inp)
+{
+ 8034f40:	defffb04 	addi	sp,sp,-20
+ 8034f44:	dfc00415 	stw	ra,16(sp)
+ 8034f48:	df000315 	stw	fp,12(sp)
+ 8034f4c:	df000304 	addi	fp,sp,12
+ 8034f50:	e13ffd15 	stw	r4,-12(fp)
+   struct tcpcb * tp;
+   short t_time;
+
+   tp = TCB_ALLOC(sizeof (*tp));
+ 8034f54:	01002504 	movi	r4,148
+ 8034f58:	802982c0 	call	802982c <npalloc>
+ 8034f5c:	e0bfff15 	stw	r2,-4(fp)
+   if (tp == NULL)
+ 8034f60:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f64:	1000021e 	bne	r2,zero,8034f70 <tcp_newtcpcb+0x30>
+      return (struct tcpcb *)NULL;
+ 8034f68:	0005883a 	mov	r2,zero
+ 8034f6c:	00003206 	br	8035038 <tcp_newtcpcb+0xf8>
+   tp->seg_next = tp->seg_prev = (struct tcpiphdr *)tp;
+ 8034f70:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f74:	e0ffff17 	ldw	r3,-4(fp)
+ 8034f78:	10c00115 	stw	r3,4(r2)
+ 8034f7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f80:	10c00117 	ldw	r3,4(r2)
+ 8034f84:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f88:	10c00015 	stw	r3,0(r2)
+   tp->t_maxseg = TCP_MSS;
+ 8034f8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f90:	00c16d04 	movi	r3,1460
+ 8034f94:	10c00a0d 	sth	r3,40(r2)
+   tp->t_flags = 0;        /* sends options! */
+ 8034f98:	e0bfff17 	ldw	r2,-4(fp)
+ 8034f9c:	10000b0d 	sth	zero,44(r2)
+   tp->t_inpcb = inp;
+ 8034fa0:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fa4:	e0fffd17 	ldw	r3,-12(fp)
+ 8034fa8:	10c00d15 	stw	r3,52(r2)
+   /*
+    * Init srtt to TCPTV_SRTTBASE (0), so we can tell that we have no
+    * rtt estimate.  Set rttvar so that srtt + 2 * rttvar gives
+    * reasonable initial retransmit time.
+    */
+   tp->t_srtt = TCPTV_SRTTBASE;
+ 8034fac:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fb0:	10002015 	stw	zero,128(r2)
+   tp->t_rttvar = TCPTV_SRTTDFLT << 2;
+ 8034fb4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fb8:	00c00604 	movi	r3,24
+ 8034fbc:	10c02115 	stw	r3,132(r2)
+
+   t_time = ((TCPTV_SRTTBASE >> 2) + (TCPTV_SRTTDFLT << 2)) >> 1;
+ 8034fc0:	00800304 	movi	r2,12
+ 8034fc4:	e0bffe8d 	sth	r2,-6(fp)
+   TCPT_RANGESET(tp->t_rxtcur, t_time, TCPTV_MIN, TCPTV_REXMTMAX);
+ 8034fc8:	e0fffe8f 	ldh	r3,-6(fp)
+ 8034fcc:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fd0:	10c00815 	stw	r3,32(r2)
+ 8034fd4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fd8:	10800817 	ldw	r2,32(r2)
+ 8034fdc:	10800088 	cmpgei	r2,r2,2
+ 8034fe0:	1000041e 	bne	r2,zero,8034ff4 <tcp_newtcpcb+0xb4>
+ 8034fe4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034fe8:	00c00084 	movi	r3,2
+ 8034fec:	10c00815 	stw	r3,32(r2)
+ 8034ff0:	00000706 	br	8035010 <tcp_newtcpcb+0xd0>
+ 8034ff4:	e0bfff17 	ldw	r2,-4(fp)
+ 8034ff8:	10800817 	ldw	r2,32(r2)
+ 8034ffc:	10802050 	cmplti	r2,r2,129
+ 8035000:	1000031e 	bne	r2,zero,8035010 <tcp_newtcpcb+0xd0>
+ 8035004:	e0bfff17 	ldw	r2,-4(fp)
+ 8035008:	00c02004 	movi	r3,128
+ 803500c:	10c00815 	stw	r3,32(r2)
+
+   /* Set initial congestion window - RFC-2581, pg 4. */
+   tp->snd_cwnd = 2 * TCP_MSS;
+ 8035010:	e0bfff17 	ldw	r2,-4(fp)
+ 8035014:	00c2da04 	movi	r3,2920
+ 8035018:	10c01b15 	stw	r3,108(r2)
+
+#ifdef DO_DELAY_ACKS
+   tp->t_delacktime = 1;
+#endif   /* DO_DELAY_ACKS */
+
+   tp->snd_ssthresh = 65535;  /* Start with high slow-start threshold */
+ 803501c:	e0bfff17 	ldw	r2,-4(fp)
+ 8035020:	00ffffd4 	movui	r3,65535
+ 8035024:	10c01c15 	stw	r3,112(r2)
+
+   inp->inp_ppcb = (char *)tp;
+ 8035028:	e0bffd17 	ldw	r2,-12(fp)
+ 803502c:	e0ffff17 	ldw	r3,-4(fp)
+ 8035030:	10c00915 	stw	r3,36(r2)
+   return (tp);
+ 8035034:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8035038:	e037883a 	mov	sp,fp
+ 803503c:	dfc00117 	ldw	ra,4(sp)
+ 8035040:	df000017 	ldw	fp,0(sp)
+ 8035044:	dec00204 	addi	sp,sp,8
+ 8035048:	f800283a 	ret
+
+0803504c <tcp_drop>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_drop(struct tcpcb * tp, int err)
+{
+ 803504c:	defffb04 	addi	sp,sp,-20
+ 8035050:	dfc00415 	stw	ra,16(sp)
+ 8035054:	df000315 	stw	fp,12(sp)
+ 8035058:	df000304 	addi	fp,sp,12
+ 803505c:	e13ffe15 	stw	r4,-8(fp)
+ 8035060:	e17ffd15 	stw	r5,-12(fp)
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+ 8035064:	e0bffe17 	ldw	r2,-8(fp)
+ 8035068:	10800d17 	ldw	r2,52(r2)
+ 803506c:	10800817 	ldw	r2,32(r2)
+ 8035070:	e0bfff15 	stw	r2,-4(fp)
+
+   if (TCPS_HAVERCVDSYN(tp->t_state)) 
+ 8035074:	e0bffe17 	ldw	r2,-8(fp)
+ 8035078:	10800217 	ldw	r2,8(r2)
+ 803507c:	108000d0 	cmplti	r2,r2,3
+ 8035080:	10000a1e 	bne	r2,zero,80350ac <tcp_drop+0x60>
+   {
+      tp->t_state = TCPS_CLOSED;
+ 8035084:	e0bffe17 	ldw	r2,-8(fp)
+ 8035088:	10000215 	stw	zero,8(r2)
+      (void) tcp_output(tp);
+ 803508c:	e13ffe17 	ldw	r4,-8(fp)
+ 8035090:	80338940 	call	8033894 <tcp_output>
+      tcpstat.tcps_drops++;
+ 8035094:	008201b4 	movhi	r2,2054
+ 8035098:	10b8a717 	ldw	r2,-7524(r2)
+ 803509c:	10c00044 	addi	r3,r2,1
+ 80350a0:	008201b4 	movhi	r2,2054
+ 80350a4:	10f8a715 	stw	r3,-7524(r2)
+ 80350a8:	00000506 	br	80350c0 <tcp_drop+0x74>
+   }
+   else
+      tcpstat.tcps_conndrops++;
+ 80350ac:	008201b4 	movhi	r2,2054
+ 80350b0:	10b8a817 	ldw	r2,-7520(r2)
+ 80350b4:	10c00044 	addi	r3,r2,1
+ 80350b8:	008201b4 	movhi	r2,2054
+ 80350bc:	10f8a815 	stw	r3,-7520(r2)
+   so->so_error = err;
+ 80350c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80350c4:	e0fffd17 	ldw	r3,-12(fp)
+ 80350c8:	10c00615 	stw	r3,24(r2)
+#ifdef TCP_ZEROCOPY
+   if (so->rx_upcall)
+      so->rx_upcall(so, NULL, err);
+#endif   /* TCP_ZEROCOPY */
+   return (tcp_close(tp));
+ 80350cc:	e13ffe17 	ldw	r4,-8(fp)
+ 80350d0:	80350e80 	call	80350e8 <tcp_close>
+}
+ 80350d4:	e037883a 	mov	sp,fp
+ 80350d8:	dfc00117 	ldw	ra,4(sp)
+ 80350dc:	df000017 	ldw	fp,0(sp)
+ 80350e0:	dec00204 	addi	sp,sp,8
+ 80350e4:	f800283a 	ret
+
+080350e8 <tcp_close>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_close(struct tcpcb * tp)
+{
+ 80350e8:	defff904 	addi	sp,sp,-28
+ 80350ec:	dfc00615 	stw	ra,24(sp)
+ 80350f0:	df000515 	stw	fp,20(sp)
+ 80350f4:	df000504 	addi	fp,sp,20
+ 80350f8:	e13ffb15 	stw	r4,-20(fp)
+   struct tcpiphdr * t;
+   struct inpcb * inp   =  tp->t_inpcb;
+ 80350fc:	e0bffb17 	ldw	r2,-20(fp)
+ 8035100:	10800d17 	ldw	r2,52(r2)
+ 8035104:	e0bffe15 	stw	r2,-8(fp)
+   struct socket *   so =  inp->inp_socket;
+ 8035108:	e0bffe17 	ldw	r2,-8(fp)
+ 803510c:	10800817 	ldw	r2,32(r2)
+ 8035110:	e0bffd15 	stw	r2,-12(fp)
+   struct mbuf *  m;
+
+   t = tp->seg_next;
+ 8035114:	e0bffb17 	ldw	r2,-20(fp)
+ 8035118:	10800017 	ldw	r2,0(r2)
+ 803511c:	e0bfff15 	stw	r2,-4(fp)
+   while (t != (struct tcpiphdr *)tp) 
+ 8035120:	00000e06 	br	803515c <tcp_close+0x74>
+   {
+      t = (struct tcpiphdr *)t->ti_next;
+ 8035124:	e0bfff17 	ldw	r2,-4(fp)
+ 8035128:	10800017 	ldw	r2,0(r2)
+ 803512c:	e0bfff15 	stw	r2,-4(fp)
+      m = dtom(t->ti_prev);
+ 8035130:	e0bfff17 	ldw	r2,-4(fp)
+ 8035134:	10800117 	ldw	r2,4(r2)
+ 8035138:	1009883a 	mov	r4,r2
+ 803513c:	802a22c0 	call	802a22c <dtom>
+ 8035140:	e0bffc15 	stw	r2,-16(fp)
+      remque(t->ti_prev);
+ 8035144:	e0bfff17 	ldw	r2,-4(fp)
+ 8035148:	10800117 	ldw	r2,4(r2)
+ 803514c:	1009883a 	mov	r4,r2
+ 8035150:	802a2c40 	call	802a2c4 <remque>
+      m_freem (m);
+ 8035154:	e13ffc17 	ldw	r4,-16(fp)
+ 8035158:	8029cfc0 	call	8029cfc <m_freem>
+   while (t != (struct tcpiphdr *)tp) 
+ 803515c:	e0ffff17 	ldw	r3,-4(fp)
+ 8035160:	e0bffb17 	ldw	r2,-20(fp)
+ 8035164:	18bfef1e 	bne	r3,r2,8035124 <tcp_close+0x3c>
+   }
+   if (tp->t_template)
+ 8035168:	e0bffb17 	ldw	r2,-20(fp)
+ 803516c:	10800c17 	ldw	r2,48(r2)
+ 8035170:	10000426 	beq	r2,zero,8035184 <tcp_close+0x9c>
+      TPH_FREE (tp->t_template);
+ 8035174:	e0bffb17 	ldw	r2,-20(fp)
+ 8035178:	10800c17 	ldw	r2,48(r2)
+ 803517c:	1009883a 	mov	r4,r2
+ 8035180:	80298600 	call	8029860 <npfree>
+   TCB_FREE (tp);
+ 8035184:	e13ffb17 	ldw	r4,-20(fp)
+ 8035188:	80298600 	call	8029860 <npfree>
+   inp->inp_ppcb = 0;
+ 803518c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035190:	10000915 	stw	zero,36(r2)
+   soisdisconnected(so);
+ 8035194:	e13ffd17 	ldw	r4,-12(fp)
+ 8035198:	802f3840 	call	802f384 <soisdisconnected>
+   in_pcbdetach(inp);
+ 803519c:	e13ffe17 	ldw	r4,-8(fp)
+ 80351a0:	80405b40 	call	80405b4 <in_pcbdetach>
+   tcpstat.tcps_closed++;
+ 80351a4:	008201b4 	movhi	r2,2054
+ 80351a8:	10b8a917 	ldw	r2,-7516(r2)
+ 80351ac:	10c00044 	addi	r3,r2,1
+ 80351b0:	008201b4 	movhi	r2,2054
+ 80351b4:	10f8a915 	stw	r3,-7516(r2)
+   return ((struct tcpcb *)0);
+ 80351b8:	0005883a 	mov	r2,zero
+}
+ 80351bc:	e037883a 	mov	sp,fp
+ 80351c0:	dfc00117 	ldw	ra,4(sp)
+ 80351c4:	df000017 	ldw	fp,0(sp)
+ 80351c8:	dec00204 	addi	sp,sp,8
+ 80351cc:	f800283a 	ret
+
+080351d0 <tcp_quench>:
+ * RETURNS: 
+ */
+
+void
+tcp_quench(struct inpcb * inp)
+{
+ 80351d0:	defffd04 	addi	sp,sp,-12
+ 80351d4:	df000215 	stw	fp,8(sp)
+ 80351d8:	df000204 	addi	fp,sp,8
+ 80351dc:	e13ffe15 	stw	r4,-8(fp)
+   struct tcpcb * tp =  intotcpcb(inp);
+ 80351e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80351e4:	10800917 	ldw	r2,36(r2)
+ 80351e8:	e0bfff15 	stw	r2,-4(fp)
+
+   if (tp)
+ 80351ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80351f0:	10000526 	beq	r2,zero,8035208 <tcp_quench+0x38>
+      tp->snd_cwnd = tp->t_maxseg;
+ 80351f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80351f8:	10800a0b 	ldhu	r2,40(r2)
+ 80351fc:	10ffffcc 	andi	r3,r2,65535
+ 8035200:	e0bfff17 	ldw	r2,-4(fp)
+ 8035204:	10c01b15 	stw	r3,108(r2)
+}
+ 8035208:	0001883a 	nop
+ 803520c:	e037883a 	mov	sp,fp
+ 8035210:	df000017 	ldw	fp,0(sp)
+ 8035214:	dec00104 	addi	sp,sp,4
+ 8035218:	f800283a 	ret
+
+0803521c <tcp_putseq>:
+
+/* tcp_putseq()  */
+
+u_char *
+tcp_putseq(u_char * cp, tcp_seq seq)
+{
+ 803521c:	defffc04 	addi	sp,sp,-16
+ 8035220:	df000315 	stw	fp,12(sp)
+ 8035224:	df000304 	addi	fp,sp,12
+ 8035228:	e13ffe15 	stw	r4,-8(fp)
+ 803522c:	e17ffd15 	stw	r5,-12(fp)
+   int   i;
+
+   cp += 3;                /* do low byte first */
+ 8035230:	e0bffe17 	ldw	r2,-8(fp)
+ 8035234:	108000c4 	addi	r2,r2,3
+ 8035238:	e0bffe15 	stw	r2,-8(fp)
+   for(i = 0; i< 4; i++)   /* put 4 bytes into buffer */
+ 803523c:	e03fff15 	stw	zero,-4(fp)
+ 8035240:	00000b06 	br	8035270 <tcp_putseq+0x54>
+   {
+      *cp-- = (u_char)(seq & 0xFF);  /* back through buffer */
+ 8035244:	e0bffe17 	ldw	r2,-8(fp)
+ 8035248:	10ffffc4 	addi	r3,r2,-1
+ 803524c:	e0fffe15 	stw	r3,-8(fp)
+ 8035250:	e0fffd17 	ldw	r3,-12(fp)
+ 8035254:	10c00005 	stb	r3,0(r2)
+      seq >>= 8;
+ 8035258:	e0bffd17 	ldw	r2,-12(fp)
+ 803525c:	1004d23a 	srli	r2,r2,8
+ 8035260:	e0bffd15 	stw	r2,-12(fp)
+   for(i = 0; i< 4; i++)   /* put 4 bytes into buffer */
+ 8035264:	e0bfff17 	ldw	r2,-4(fp)
+ 8035268:	10800044 	addi	r2,r2,1
+ 803526c:	e0bfff15 	stw	r2,-4(fp)
+ 8035270:	e0bfff17 	ldw	r2,-4(fp)
+ 8035274:	10800110 	cmplti	r2,r2,4
+ 8035278:	103ff21e 	bne	r2,zero,8035244 <tcp_putseq+0x28>
+   }
+   return (cp + 5);
+ 803527c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035280:	10800144 	addi	r2,r2,5
+}
+ 8035284:	e037883a 	mov	sp,fp
+ 8035288:	df000017 	ldw	fp,0(sp)
+ 803528c:	dec00104 	addi	sp,sp,4
+ 8035290:	f800283a 	ret
+
+08035294 <tcp_getseq>:
+ * RETURNS: a long in local endian
+ */
+
+u_long
+tcp_getseq(u_char * cp)
+{
+ 8035294:	defffc04 	addi	sp,sp,-16
+ 8035298:	df000315 	stw	fp,12(sp)
+ 803529c:	df000304 	addi	fp,sp,12
+ 80352a0:	e13ffd15 	stw	r4,-12(fp)
+   int i;
+   ulong seq = 0;
+ 80352a4:	e03ffe15 	stw	zero,-8(fp)
+
+   for(i = 0; i < 4; i++)
+ 80352a8:	e03fff15 	stw	zero,-4(fp)
+ 80352ac:	00000e06 	br	80352e8 <tcp_getseq+0x54>
+   {
+      seq <<= 8;
+ 80352b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80352b4:	1004923a 	slli	r2,r2,8
+ 80352b8:	e0bffe15 	stw	r2,-8(fp)
+      seq += (u_long)*(cp++);
+ 80352bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80352c0:	10c00044 	addi	r3,r2,1
+ 80352c4:	e0fffd15 	stw	r3,-12(fp)
+ 80352c8:	10800003 	ldbu	r2,0(r2)
+ 80352cc:	10803fcc 	andi	r2,r2,255
+ 80352d0:	e0fffe17 	ldw	r3,-8(fp)
+ 80352d4:	1885883a 	add	r2,r3,r2
+ 80352d8:	e0bffe15 	stw	r2,-8(fp)
+   for(i = 0; i < 4; i++)
+ 80352dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80352e0:	10800044 	addi	r2,r2,1
+ 80352e4:	e0bfff15 	stw	r2,-4(fp)
+ 80352e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80352ec:	10800110 	cmplti	r2,r2,4
+ 80352f0:	103fef1e 	bne	r2,zero,80352b0 <tcp_getseq+0x1c>
+   }
+   return seq;
+ 80352f4:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 80352f8:	e037883a 	mov	sp,fp
+ 80352fc:	df000017 	ldw	fp,0(sp)
+ 8035300:	dec00104 	addi	sp,sp,4
+ 8035304:	f800283a 	ret
+
+08035308 <tcp_slowtimo>:
+ * RETURNS: 
+ */
+
+void
+tcp_slowtimo(void)
+{
+ 8035308:	defff704 	addi	sp,sp,-36
+ 803530c:	dfc00815 	stw	ra,32(sp)
+ 8035310:	df000715 	stw	fp,28(sp)
+ 8035314:	df000704 	addi	fp,sp,28
+   struct tcpcb * tp;
+   int   i;
+   struct socket * so, * sonext;
+   struct sockbuf *  sb;
+
+   tcp_maxidle = TCPTV_KEEPCNT * tcp_keepintvl;
+ 8035318:	d0a01f17 	ldw	r2,-32644(gp)
+ 803531c:	100490fa 	slli	r2,r2,3
+ 8035320:	d0a08915 	stw	r2,-32220(gp)
+
+   /* search through open sockets */
+   for (so = (struct socket *)soq.q_head; so != NULL; so = sonext)
+ 8035324:	008201b4 	movhi	r2,2054
+ 8035328:	10b87117 	ldw	r2,-7740(r2)
+ 803532c:	e0bffe15 	stw	r2,-8(fp)
+ 8035330:	00007c06 	br	8035524 <tcp_slowtimo+0x21c>
+   {
+      sonext = so->next;
+ 8035334:	e0bffe17 	ldw	r2,-8(fp)
+ 8035338:	10800017 	ldw	r2,0(r2)
+ 803533c:	e0bffd15 	stw	r2,-12(fp)
+
+      /* for SOCK_STREAM (TCP) sockets, we must do slow-timeout 
+       * processing and (optionally) processing of pending 
+       * zero-copy socket upcalls.
+       */
+      if (so->so_type == SOCK_STREAM)
+ 8035340:	e0bffe17 	ldw	r2,-8(fp)
+ 8035344:	10800983 	ldbu	r2,38(r2)
+ 8035348:	10803fcc 	andi	r2,r2,255
+ 803534c:	1080201c 	xori	r2,r2,128
+ 8035350:	10bfe004 	addi	r2,r2,-128
+ 8035354:	10800058 	cmpnei	r2,r2,1
+ 8035358:	1000421e 	bne	r2,zero,8035464 <tcp_slowtimo+0x15c>
+      {
+         ip = so->so_pcb;
+ 803535c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035360:	10800117 	ldw	r2,4(r2)
+ 8035364:	e0bffc15 	stw	r2,-16(fp)
+         if (!ip)
+ 8035368:	e0bffc17 	ldw	r2,-16(fp)
+ 803536c:	10006626 	beq	r2,zero,8035508 <tcp_slowtimo+0x200>
+            continue;
+         ipnxt = ip->inp_next;
+ 8035370:	e0bffc17 	ldw	r2,-16(fp)
+ 8035374:	10800017 	ldw	r2,0(r2)
+ 8035378:	e0bffb15 	stw	r2,-20(fp)
+
+         tp = intotcpcb(so->so_pcb);
+ 803537c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035380:	10800117 	ldw	r2,4(r2)
+ 8035384:	10800917 	ldw	r2,36(r2)
+ 8035388:	e0bffa15 	stw	r2,-24(fp)
+         if (!tp)
+ 803538c:	e0bffa17 	ldw	r2,-24(fp)
+ 8035390:	10005f26 	beq	r2,zero,8035510 <tcp_slowtimo+0x208>
+            continue;
+
+         for (i = 0; i < TCPT_NTIMERS; i++) 
+ 8035394:	e03fff15 	stw	zero,-4(fp)
+ 8035398:	00002a06 	br	8035444 <tcp_slowtimo+0x13c>
+         {
+            if (tp->t_timer[i] && --tp->t_timer[i] == 0) 
+ 803539c:	e0fffa17 	ldw	r3,-24(fp)
+ 80353a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80353a4:	108000c4 	addi	r2,r2,3
+ 80353a8:	100490ba 	slli	r2,r2,2
+ 80353ac:	1885883a 	add	r2,r3,r2
+ 80353b0:	10800017 	ldw	r2,0(r2)
+ 80353b4:	10002026 	beq	r2,zero,8035438 <tcp_slowtimo+0x130>
+ 80353b8:	e0fffa17 	ldw	r3,-24(fp)
+ 80353bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80353c0:	108000c4 	addi	r2,r2,3
+ 80353c4:	100490ba 	slli	r2,r2,2
+ 80353c8:	1885883a 	add	r2,r3,r2
+ 80353cc:	10800017 	ldw	r2,0(r2)
+ 80353d0:	10ffffc4 	addi	r3,r2,-1
+ 80353d4:	e13ffa17 	ldw	r4,-24(fp)
+ 80353d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80353dc:	108000c4 	addi	r2,r2,3
+ 80353e0:	100490ba 	slli	r2,r2,2
+ 80353e4:	2085883a 	add	r2,r4,r2
+ 80353e8:	10c00015 	stw	r3,0(r2)
+ 80353ec:	e0fffa17 	ldw	r3,-24(fp)
+ 80353f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80353f4:	108000c4 	addi	r2,r2,3
+ 80353f8:	100490ba 	slli	r2,r2,2
+ 80353fc:	1885883a 	add	r2,r3,r2
+ 8035400:	10800017 	ldw	r2,0(r2)
+ 8035404:	10000c1e 	bne	r2,zero,8035438 <tcp_slowtimo+0x130>
+            {
+               /* call usrreq to do actual work */
+               so->so_req = PRU_SLOWTIMO;
+ 8035408:	e0bffe17 	ldw	r2,-8(fp)
+ 803540c:	00c004c4 	movi	r3,19
+ 8035410:	10c00715 	stw	r3,28(r2)
+               (void) tcp_usrreq(so, (struct mbuf *)0, 
+ 8035414:	e0bfff17 	ldw	r2,-4(fp)
+ 8035418:	100d883a 	mov	r6,r2
+ 803541c:	000b883a 	mov	r5,zero
+ 8035420:	e13ffe17 	ldw	r4,-8(fp)
+ 8035424:	8035a140 	call	8035a14 <tcp_usrreq>
+                                 LONG2MBUF((long)i));
+
+               /* If ip disappeared on us, handle it */
+               if (ipnxt->inp_prev != ip)
+ 8035428:	e0bffb17 	ldw	r2,-20(fp)
+ 803542c:	10800117 	ldw	r2,4(r2)
+ 8035430:	e0fffc17 	ldw	r3,-16(fp)
+ 8035434:	1880381e 	bne	r3,r2,8035518 <tcp_slowtimo+0x210>
+         for (i = 0; i < TCPT_NTIMERS; i++) 
+ 8035438:	e0bfff17 	ldw	r2,-4(fp)
+ 803543c:	10800044 	addi	r2,r2,1
+ 8035440:	e0bfff15 	stw	r2,-4(fp)
+ 8035444:	e0bfff17 	ldw	r2,-4(fp)
+ 8035448:	10800110 	cmplti	r2,r2,4
+ 803544c:	103fd31e 	bne	r2,zero,803539c <tcp_slowtimo+0x94>
+               }
+            }
+         }
+#endif   /* TCP_ZEROCOPY */
+
+         tp->t_idle++;
+ 8035450:	e0bffa17 	ldw	r2,-24(fp)
+ 8035454:	10801d17 	ldw	r2,116(r2)
+ 8035458:	10c00044 	addi	r3,r2,1
+ 803545c:	e0bffa17 	ldw	r2,-24(fp)
+ 8035460:	10c01d15 	stw	r3,116(r2)
+      }
+
+      /* wake up anyone sleeping in a select() involving this socket */
+      sb = &so->so_rcv;
+ 8035464:	e0bffe17 	ldw	r2,-8(fp)
+ 8035468:	10800a04 	addi	r2,r2,40
+ 803546c:	e0bff915 	stw	r2,-28(fp)
+      if (sb->sb_flags & SB_SEL) 
+ 8035470:	e0bff917 	ldw	r2,-28(fp)
+ 8035474:	1080070b 	ldhu	r2,28(r2)
+ 8035478:	10bfffcc 	andi	r2,r2,65535
+ 803547c:	1080020c 	andi	r2,r2,8
+ 8035480:	10000a26 	beq	r2,zero,80354ac <tcp_slowtimo+0x1a4>
+      {
+         select_wait = 0;
+ 8035484:	d020850d 	sth	zero,-32236(gp)
+#ifndef SOCK_MAP_EVENTS
+         tcp_wakeup ((char *)&select_wait);
+ 8035488:	d1208504 	addi	r4,gp,-32236
+ 803548c:	8027ba00 	call	8027ba0 <tcp_wakeup>
+#else
+         tcp_wakeup2 (so->owner);
+#endif
+         sb->sb_flags &= ~SB_SEL;
+ 8035490:	e0bff917 	ldw	r2,-28(fp)
+ 8035494:	10c0070b 	ldhu	r3,28(r2)
+ 8035498:	00bffdc4 	movi	r2,-9
+ 803549c:	1884703a 	and	r2,r3,r2
+ 80354a0:	1007883a 	mov	r3,r2
+ 80354a4:	e0bff917 	ldw	r2,-28(fp)
+ 80354a8:	10c0070d 	sth	r3,28(r2)
+      }
+      sb = &so->so_snd;
+ 80354ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80354b0:	10801204 	addi	r2,r2,72
+ 80354b4:	e0bff915 	stw	r2,-28(fp)
+      if (sb->sb_flags & SB_SEL) 
+ 80354b8:	e0bff917 	ldw	r2,-28(fp)
+ 80354bc:	1080070b 	ldhu	r2,28(r2)
+ 80354c0:	10bfffcc 	andi	r2,r2,65535
+ 80354c4:	1080020c 	andi	r2,r2,8
+ 80354c8:	10000a26 	beq	r2,zero,80354f4 <tcp_slowtimo+0x1ec>
+      {
+         select_wait = 0;         
+ 80354cc:	d020850d 	sth	zero,-32236(gp)
+#ifndef SOCK_MAP_EVENTS
+         tcp_wakeup ((char *)&select_wait);
+ 80354d0:	d1208504 	addi	r4,gp,-32236
+ 80354d4:	8027ba00 	call	8027ba0 <tcp_wakeup>
+#else
+         tcp_wakeup2 (so->owner);
+#endif
+         sb->sb_flags &= ~SB_SEL;
+ 80354d8:	e0bff917 	ldw	r2,-28(fp)
+ 80354dc:	10c0070b 	ldhu	r3,28(r2)
+ 80354e0:	00bffdc4 	movi	r2,-9
+ 80354e4:	1884703a 	and	r2,r3,r2
+ 80354e8:	1007883a 	mov	r3,r2
+ 80354ec:	e0bff917 	ldw	r2,-28(fp)
+ 80354f0:	10c0070d 	sth	r3,28(r2)
+      }
+
+      /* wake any thread with a timer going for a connection state change */     
+      tcp_wakeup((char*)&so->so_timeo);
+ 80354f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80354f8:	10800904 	addi	r2,r2,36
+ 80354fc:	1009883a 	mov	r4,r2
+ 8035500:	8027ba00 	call	8027ba0 <tcp_wakeup>
+ 8035504:	00000506 	br	803551c <tcp_slowtimo+0x214>
+            continue;
+ 8035508:	0001883a 	nop
+ 803550c:	00000306 	br	803551c <tcp_slowtimo+0x214>
+            continue;
+ 8035510:	0001883a 	nop
+ 8035514:	00000106 	br	803551c <tcp_slowtimo+0x214>
+                  goto tpgone;
+ 8035518:	0001883a 	nop
+   for (so = (struct socket *)soq.q_head; so != NULL; so = sonext)
+ 803551c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035520:	e0bffe15 	stw	r2,-8(fp)
+ 8035524:	e0bffe17 	ldw	r2,-8(fp)
+ 8035528:	103f821e 	bne	r2,zero,8035334 <tcp_slowtimo+0x2c>
+
+tpgone:
+      ;
+   }
+
+   tcp_iss += (unsigned)(TCP_ISSINCR/PR_SLOWHZ);      /* increment iss */
+ 803552c:	d0e08a17 	ldw	r3,-32216(gp)
+ 8035530:	00be9fd4 	movui	r2,64127
+ 8035534:	1885883a 	add	r2,r3,r2
+ 8035538:	d0a08a15 	stw	r2,-32216(gp)
+
+   if (tcp_iss & 0xff000000)
+ 803553c:	d0a08a17 	ldw	r2,-32216(gp)
+ 8035540:	10bfc02c 	andhi	r2,r2,65280
+ 8035544:	10000126 	beq	r2,zero,803554c <tcp_slowtimo+0x244>
+      tcp_iss = 0L;
+ 8035548:	d0208a15 	stw	zero,-32216(gp)
+}
+ 803554c:	0001883a 	nop
+ 8035550:	e037883a 	mov	sp,fp
+ 8035554:	dfc00117 	ldw	ra,4(sp)
+ 8035558:	df000017 	ldw	fp,0(sp)
+ 803555c:	dec00204 	addi	sp,sp,8
+ 8035560:	f800283a 	ret
+
+08035564 <tcp_canceltimers>:
+ * RETURNS: 
+ */
+
+void
+tcp_canceltimers(struct tcpcb * tp)
+{
+ 8035564:	defffd04 	addi	sp,sp,-12
+ 8035568:	df000215 	stw	fp,8(sp)
+ 803556c:	df000204 	addi	fp,sp,8
+ 8035570:	e13ffe15 	stw	r4,-8(fp)
+   int   i;
+
+   for (i = 0; i < TCPT_NTIMERS; i++)
+ 8035574:	e03fff15 	stw	zero,-4(fp)
+ 8035578:	00000906 	br	80355a0 <tcp_canceltimers+0x3c>
+      tp->t_timer[i] = 0;
+ 803557c:	e0fffe17 	ldw	r3,-8(fp)
+ 8035580:	e0bfff17 	ldw	r2,-4(fp)
+ 8035584:	108000c4 	addi	r2,r2,3
+ 8035588:	100490ba 	slli	r2,r2,2
+ 803558c:	1885883a 	add	r2,r3,r2
+ 8035590:	10000015 	stw	zero,0(r2)
+   for (i = 0; i < TCPT_NTIMERS; i++)
+ 8035594:	e0bfff17 	ldw	r2,-4(fp)
+ 8035598:	10800044 	addi	r2,r2,1
+ 803559c:	e0bfff15 	stw	r2,-4(fp)
+ 80355a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80355a4:	10800110 	cmplti	r2,r2,4
+ 80355a8:	103ff41e 	bne	r2,zero,803557c <tcp_canceltimers+0x18>
+}
+ 80355ac:	0001883a 	nop
+ 80355b0:	e037883a 	mov	sp,fp
+ 80355b4:	df000017 	ldw	fp,0(sp)
+ 80355b8:	dec00104 	addi	sp,sp,4
+ 80355bc:	f800283a 	ret
+
+080355c0 <tcp_timers>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_timers(struct tcpcb * tp, int timer)
+{
+ 80355c0:	defff804 	addi	sp,sp,-32
+ 80355c4:	dfc00715 	stw	ra,28(sp)
+ 80355c8:	df000615 	stw	fp,24(sp)
+ 80355cc:	df000604 	addi	fp,sp,24
+ 80355d0:	e13ffd15 	stw	r4,-12(fp)
+ 80355d4:	e17ffc15 	stw	r5,-16(fp)
+   int   rexmt;
+
+   switch (timer) 
+ 80355d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80355dc:	10800060 	cmpeqi	r2,r2,1
+ 80355e0:	1000af1e 	bne	r2,zero,80358a0 <tcp_timers+0x2e0>
+ 80355e4:	e0bffc17 	ldw	r2,-16(fp)
+ 80355e8:	10800088 	cmpgei	r2,r2,2
+ 80355ec:	1000031e 	bne	r2,zero,80355fc <tcp_timers+0x3c>
+ 80355f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80355f4:	10001a26 	beq	r2,zero,8035660 <tcp_timers+0xa0>
+ 80355f8:	00010006 	br	80359fc <tcp_timers+0x43c>
+ 80355fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8035600:	108000a0 	cmpeqi	r2,r2,2
+ 8035604:	1000b51e 	bne	r2,zero,80358dc <tcp_timers+0x31c>
+ 8035608:	e0bffc17 	ldw	r2,-16(fp)
+ 803560c:	108000d8 	cmpnei	r2,r2,3
+ 8035610:	1000fa1e 	bne	r2,zero,80359fc <tcp_timers+0x43c>
+    * still waiting for peer to close and connection has been idle
+    * too long, or if 2MSL time is up from TIME_WAIT, delete connection
+    * control block.  Otherwise, check again in a bit.
+    */
+   case TCPT_2MSL:
+      if (tp->t_state != TCPS_TIME_WAIT &&
+ 8035614:	e0bffd17 	ldw	r2,-12(fp)
+ 8035618:	10800217 	ldw	r2,8(r2)
+ 803561c:	108002a0 	cmpeqi	r2,r2,10
+ 8035620:	10000b1e 	bne	r2,zero,8035650 <tcp_timers+0x90>
+          tp->t_idle <= tcp_maxidle)
+ 8035624:	e0bffd17 	ldw	r2,-12(fp)
+ 8035628:	10801d17 	ldw	r2,116(r2)
+ 803562c:	d0e08917 	ldw	r3,-32220(gp)
+      if (tp->t_state != TCPS_TIME_WAIT &&
+ 8035630:	18800716 	blt	r3,r2,8035650 <tcp_timers+0x90>
+      {
+         tp->t_timer[TCPT_2MSL] = (short)tcp_keepintvl;
+ 8035634:	d0a01f17 	ldw	r2,-32644(gp)
+ 8035638:	10ffffcc 	andi	r3,r2,65535
+ 803563c:	18e0001c 	xori	r3,r3,32768
+ 8035640:	18e00004 	addi	r3,r3,-32768
+ 8035644:	e0bffd17 	ldw	r2,-12(fp)
+ 8035648:	10c00615 	stw	r3,24(r2)
+      }
+      else
+         tp = tcp_close(tp);
+      break;
+ 803564c:	0000eb06 	br	80359fc <tcp_timers+0x43c>
+         tp = tcp_close(tp);
+ 8035650:	e13ffd17 	ldw	r4,-12(fp)
+ 8035654:	80350e80 	call	80350e8 <tcp_close>
+ 8035658:	e0bffd15 	stw	r2,-12(fp)
+      break;
+ 803565c:	0000e706 	br	80359fc <tcp_timers+0x43c>
+    * Retransmission timer went off.  Message has not
+    * been acked within retransmit interval.  Back off
+    * to a longer retransmit interval and retransmit one segment.
+    */
+   case TCPT_REXMT:
+      TCP_MIB_INC(tcpRetransSegs);     /* keep MIB stats */
+ 8035660:	008201b4 	movhi	r2,2054
+ 8035664:	10b88117 	ldw	r2,-7676(r2)
+ 8035668:	10c00044 	addi	r3,r2,1
+ 803566c:	008201b4 	movhi	r2,2054
+ 8035670:	10f88115 	stw	r3,-7676(r2)
+      if (++tp->t_rxtshift > TCP_MAXRXTSHIFT) 
+ 8035674:	e0bffd17 	ldw	r2,-12(fp)
+ 8035678:	10800717 	ldw	r2,28(r2)
+ 803567c:	10c00044 	addi	r3,r2,1
+ 8035680:	e0bffd17 	ldw	r2,-12(fp)
+ 8035684:	10c00715 	stw	r3,28(r2)
+ 8035688:	e0bffd17 	ldw	r2,-12(fp)
+ 803568c:	10800717 	ldw	r2,28(r2)
+ 8035690:	10800350 	cmplti	r2,r2,13
+ 8035694:	10000d1e 	bne	r2,zero,80356cc <tcp_timers+0x10c>
+      {
+         tp->t_rxtshift = TCP_MAXRXTSHIFT;
+ 8035698:	e0bffd17 	ldw	r2,-12(fp)
+ 803569c:	00c00304 	movi	r3,12
+ 80356a0:	10c00715 	stw	r3,28(r2)
+         tcpstat.tcps_timeoutdrop++;
+ 80356a4:	008201b4 	movhi	r2,2054
+ 80356a8:	10b8ad17 	ldw	r2,-7500(r2)
+ 80356ac:	10c00044 	addi	r3,r2,1
+ 80356b0:	008201b4 	movhi	r2,2054
+ 80356b4:	10f8ad15 	stw	r3,-7500(r2)
+         tp = tcp_drop(tp, ETIMEDOUT);
+ 80356b8:	01401d04 	movi	r5,116
+ 80356bc:	e13ffd17 	ldw	r4,-12(fp)
+ 80356c0:	803504c0 	call	803504c <tcp_drop>
+ 80356c4:	e0bffd15 	stw	r2,-12(fp)
+         break;
+ 80356c8:	0000cc06 	br	80359fc <tcp_timers+0x43c>
+      }
+      tcpstat.tcps_rexmttimeo++;
+ 80356cc:	008201b4 	movhi	r2,2054
+ 80356d0:	10b8ae17 	ldw	r2,-7496(r2)
+ 80356d4:	10c00044 	addi	r3,r2,1
+ 80356d8:	008201b4 	movhi	r2,2054
+ 80356dc:	10f8ae15 	stw	r3,-7496(r2)
+      rexmt = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1;
+ 80356e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80356e4:	10802017 	ldw	r2,128(r2)
+ 80356e8:	1007d0ba 	srai	r3,r2,2
+ 80356ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80356f0:	10802117 	ldw	r2,132(r2)
+ 80356f4:	1885883a 	add	r2,r3,r2
+ 80356f8:	1005d07a 	srai	r2,r2,1
+ 80356fc:	e0bffe15 	stw	r2,-8(fp)
+      rexmt *= tcp_backoff[tp->t_rxtshift];
+ 8035700:	e0bffd17 	ldw	r2,-12(fp)
+ 8035704:	10c00717 	ldw	r3,28(r2)
+ 8035708:	00820174 	movhi	r2,2053
+ 803570c:	1885883a 	add	r2,r3,r2
+ 8035710:	10b20cc3 	ldbu	r2,-14285(r2)
+ 8035714:	10803fcc 	andi	r2,r2,255
+ 8035718:	e0fffe17 	ldw	r3,-8(fp)
+ 803571c:	1885383a 	mul	r2,r3,r2
+ 8035720:	e0bffe15 	stw	r2,-8(fp)
+      TCPT_RANGESET(tp->t_rxtcur, rexmt, TCPTV_MIN, TCPTV_REXMTMAX);
+ 8035724:	e0bffe17 	ldw	r2,-8(fp)
+ 8035728:	10ffffcc 	andi	r3,r2,65535
+ 803572c:	18e0001c 	xori	r3,r3,32768
+ 8035730:	18e00004 	addi	r3,r3,-32768
+ 8035734:	e0bffd17 	ldw	r2,-12(fp)
+ 8035738:	10c00815 	stw	r3,32(r2)
+ 803573c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035740:	10800817 	ldw	r2,32(r2)
+ 8035744:	10800088 	cmpgei	r2,r2,2
+ 8035748:	1000041e 	bne	r2,zero,803575c <tcp_timers+0x19c>
+ 803574c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035750:	00c00084 	movi	r3,2
+ 8035754:	10c00815 	stw	r3,32(r2)
+ 8035758:	00000706 	br	8035778 <tcp_timers+0x1b8>
+ 803575c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035760:	10800817 	ldw	r2,32(r2)
+ 8035764:	10802050 	cmplti	r2,r2,129
+ 8035768:	1000031e 	bne	r2,zero,8035778 <tcp_timers+0x1b8>
+ 803576c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035770:	00c02004 	movi	r3,128
+ 8035774:	10c00815 	stw	r3,32(r2)
+      tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+ 8035778:	e0bffd17 	ldw	r2,-12(fp)
+ 803577c:	10c00817 	ldw	r3,32(r2)
+ 8035780:	e0bffd17 	ldw	r2,-12(fp)
+ 8035784:	10c00315 	stw	r3,12(r2)
+       * so we'll take the next rtt measurement as our srtt;
+       * move the current srtt into rttvar to keep the current
+       * retransmit times until then. Don't clobber with rtt
+       * if we got it from a timestamp option.
+       */
+      if((tp->t_rxtshift > TCP_MAXRXTSHIFT / 4) &&
+ 8035788:	e0bffd17 	ldw	r2,-12(fp)
+ 803578c:	10800717 	ldw	r2,28(r2)
+ 8035790:	10800110 	cmplti	r2,r2,4
+ 8035794:	10000f1e 	bne	r2,zero,80357d4 <tcp_timers+0x214>
+         ((tp->t_flags & TF_TIMESTAMP) == 0))
+ 8035798:	e0bffd17 	ldw	r2,-12(fp)
+ 803579c:	10800b0b 	ldhu	r2,44(r2)
+ 80357a0:	10bfffcc 	andi	r2,r2,65535
+ 80357a4:	1080400c 	andi	r2,r2,256
+      if((tp->t_rxtshift > TCP_MAXRXTSHIFT / 4) &&
+ 80357a8:	10000a1e 	bne	r2,zero,80357d4 <tcp_timers+0x214>
+      {
+         tp->t_rttvar += (tp->t_srtt >> 2);
+ 80357ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80357b0:	10c02117 	ldw	r3,132(r2)
+ 80357b4:	e0bffd17 	ldw	r2,-12(fp)
+ 80357b8:	10802017 	ldw	r2,128(r2)
+ 80357bc:	1005d0ba 	srai	r2,r2,2
+ 80357c0:	1887883a 	add	r3,r3,r2
+ 80357c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80357c8:	10c02115 	stw	r3,132(r2)
+         tp->t_srtt = 0;
+ 80357cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80357d0:	10002015 	stw	zero,128(r2)
+      }
+      tp->snd_nxt = tp->snd_una;
+ 80357d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80357d8:	10c00e17 	ldw	r3,56(r2)
+ 80357dc:	e0bffd17 	ldw	r2,-12(fp)
+ 80357e0:	10c00f15 	stw	r3,60(r2)
+      /*
+       * If timing a segment in this window, stop the timer.
+       */
+      tp->t_rttick = 0;
+ 80357e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80357e8:	10001e15 	stw	zero,120(r2)
+       * to go below this.)
+       *
+       * Vers 1.9 - Skip slow start if the SO_NOSLOWSTART socket option
+       * is set.
+       */
+      if((tp->t_inpcb->inp_socket->so_options & SO_NOSLOWSTART) == 0)
+ 80357ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80357f0:	10800d17 	ldw	r2,52(r2)
+ 80357f4:	10800817 	ldw	r2,32(r2)
+ 80357f8:	10800417 	ldw	r2,16(r2)
+ 80357fc:	1090000c 	andi	r2,r2,16384
+ 8035800:	1000241e 	bne	r2,zero,8035894 <tcp_timers+0x2d4>
+      {
+         u_int win = MIN(tp->snd_wnd, tp->snd_cwnd);
+ 8035804:	e0bffd17 	ldw	r2,-12(fp)
+ 8035808:	11001417 	ldw	r4,80(r2)
+ 803580c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035810:	10c01b17 	ldw	r3,108(r2)
+ 8035814:	2005883a 	mov	r2,r4
+ 8035818:	1880012e 	bgeu	r3,r2,8035820 <tcp_timers+0x260>
+ 803581c:	1805883a 	mov	r2,r3
+ 8035820:	e0bfff15 	stw	r2,-4(fp)
+         win = win / 2 / tp->t_maxseg;
+ 8035824:	e0bfff17 	ldw	r2,-4(fp)
+ 8035828:	1006d07a 	srli	r3,r2,1
+ 803582c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035830:	10800a0b 	ldhu	r2,40(r2)
+ 8035834:	10bfffcc 	andi	r2,r2,65535
+ 8035838:	100b883a 	mov	r5,r2
+ 803583c:	1809883a 	mov	r4,r3
+ 8035840:	800cff80 	call	800cff8 <__udivsi3>
+ 8035844:	e0bfff15 	stw	r2,-4(fp)
+         if (win < 2)
+ 8035848:	e0bfff17 	ldw	r2,-4(fp)
+ 803584c:	108000a8 	cmpgeui	r2,r2,2
+ 8035850:	1000021e 	bne	r2,zero,803585c <tcp_timers+0x29c>
+            win = 2;
+ 8035854:	00800084 	movi	r2,2
+ 8035858:	e0bfff15 	stw	r2,-4(fp)
+         tp->snd_cwnd = tp->t_maxseg;
+ 803585c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035860:	10800a0b 	ldhu	r2,40(r2)
+ 8035864:	10ffffcc 	andi	r3,r2,65535
+ 8035868:	e0bffd17 	ldw	r2,-12(fp)
+ 803586c:	10c01b15 	stw	r3,108(r2)
+         tp->snd_ssthresh = (u_short)win * tp->t_maxseg;
+ 8035870:	e0bfff17 	ldw	r2,-4(fp)
+ 8035874:	10ffffcc 	andi	r3,r2,65535
+ 8035878:	e0bffd17 	ldw	r2,-12(fp)
+ 803587c:	10800a0b 	ldhu	r2,40(r2)
+ 8035880:	10bfffcc 	andi	r2,r2,65535
+ 8035884:	1885383a 	mul	r2,r3,r2
+ 8035888:	1007883a 	mov	r3,r2
+ 803588c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035890:	10c01c15 	stw	r3,112(r2)
+      }
+      (void) tcp_output(tp);
+ 8035894:	e13ffd17 	ldw	r4,-12(fp)
+ 8035898:	80338940 	call	8033894 <tcp_output>
+      break;
+ 803589c:	00005706 	br	80359fc <tcp_timers+0x43c>
+   /*
+    * Persistance timer into zero window.
+    * Force a byte to be output, if possible.
+    */
+   case TCPT_PERSIST:
+      tcpstat.tcps_persisttimeo++;
+ 80358a0:	008201b4 	movhi	r2,2054
+ 80358a4:	10b8af17 	ldw	r2,-7492(r2)
+ 80358a8:	10c00044 	addi	r3,r2,1
+ 80358ac:	008201b4 	movhi	r2,2054
+ 80358b0:	10f8af15 	stw	r3,-7492(r2)
+      tcp_setpersist(tp);
+ 80358b4:	e13ffd17 	ldw	r4,-12(fp)
+ 80358b8:	80348300 	call	8034830 <tcp_setpersist>
+      tp->t_force = 1;
+ 80358bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80358c0:	00c00044 	movi	r3,1
+ 80358c4:	10c00a85 	stb	r3,42(r2)
+      (void) tcp_output(tp);
+ 80358c8:	e13ffd17 	ldw	r4,-12(fp)
+ 80358cc:	80338940 	call	8033894 <tcp_output>
+      tp->t_force = 0;
+ 80358d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80358d4:	10000a85 	stb	zero,42(r2)
+      break;
+ 80358d8:	00004806 	br	80359fc <tcp_timers+0x43c>
+   /*
+    * Keep-alive timer went off; send something
+    * or drop connection if idle for too long.
+    */
+   case TCPT_KEEP:
+      tcpstat.tcps_keeptimeo++;
+ 80358dc:	008201b4 	movhi	r2,2054
+ 80358e0:	10b8b017 	ldw	r2,-7488(r2)
+ 80358e4:	10c00044 	addi	r3,r2,1
+ 80358e8:	008201b4 	movhi	r2,2054
+ 80358ec:	10f8b015 	stw	r3,-7488(r2)
+      if (tp->t_state < TCPS_ESTABLISHED)
+ 80358f0:	e0bffd17 	ldw	r2,-12(fp)
+ 80358f4:	10800217 	ldw	r2,8(r2)
+ 80358f8:	10800108 	cmpgei	r2,r2,4
+ 80358fc:	10003226 	beq	r2,zero,80359c8 <tcp_timers+0x408>
+         goto dropit;
+      if (tp->t_inpcb->inp_socket->so_options & SO_KEEPALIVE &&
+ 8035900:	e0bffd17 	ldw	r2,-12(fp)
+ 8035904:	10800d17 	ldw	r2,52(r2)
+ 8035908:	10800817 	ldw	r2,32(r2)
+ 803590c:	10800417 	ldw	r2,16(r2)
+ 8035910:	1080020c 	andi	r2,r2,8
+ 8035914:	10002526 	beq	r2,zero,80359ac <tcp_timers+0x3ec>
+          tp->t_state <= TCPS_CLOSE_WAIT) 
+ 8035918:	e0bffd17 	ldw	r2,-12(fp)
+ 803591c:	10800217 	ldw	r2,8(r2)
+      if (tp->t_inpcb->inp_socket->so_options & SO_KEEPALIVE &&
+ 8035920:	10800188 	cmpgei	r2,r2,6
+ 8035924:	1000211e 	bne	r2,zero,80359ac <tcp_timers+0x3ec>
+      {
+         if (tp->t_idle >= tcp_keepidle + tcp_maxidle)
+ 8035928:	e0bffd17 	ldw	r2,-12(fp)
+ 803592c:	10c01d17 	ldw	r3,116(r2)
+ 8035930:	d1201e17 	ldw	r4,-32648(gp)
+ 8035934:	d0a08917 	ldw	r2,-32220(gp)
+ 8035938:	2085883a 	add	r2,r4,r2
+ 803593c:	1880240e 	bge	r3,r2,80359d0 <tcp_timers+0x410>
+          * causes the transmitted zero-length segment
+          * to lie outside the receive window;
+          * by the protocol spec, this requires the
+          * correspondent TCP to respond.
+          */
+         tcpstat.tcps_keepprobe++;
+ 8035940:	008201b4 	movhi	r2,2054
+ 8035944:	10b8b117 	ldw	r2,-7484(r2)
+ 8035948:	10c00044 	addi	r3,r2,1
+ 803594c:	008201b4 	movhi	r2,2054
+ 8035950:	10f8b115 	stw	r3,-7484(r2)
+
+         /*
+          * The keepalive packet must have nonzero length
+          * to get a 4.2 host to respond.
+          */
+         tcp_respond(tp, tp->t_template, tp->rcv_nxt - 1,
+ 8035954:	e0bffd17 	ldw	r2,-12(fp)
+ 8035958:	10c00c17 	ldw	r3,48(r2)
+ 803595c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035960:	10801617 	ldw	r2,88(r2)
+ 8035964:	113fffc4 	addi	r4,r2,-1
+            tp->snd_una - 1, 0, (struct mbuf *)NULL);
+ 8035968:	e0bffd17 	ldw	r2,-12(fp)
+ 803596c:	10800e17 	ldw	r2,56(r2)
+         tcp_respond(tp, tp->t_template, tp->rcv_nxt - 1,
+ 8035970:	10bfffc4 	addi	r2,r2,-1
+ 8035974:	d8000115 	stw	zero,4(sp)
+ 8035978:	d8000015 	stw	zero,0(sp)
+ 803597c:	100f883a 	mov	r7,r2
+ 8035980:	200d883a 	mov	r6,r4
+ 8035984:	180b883a 	mov	r5,r3
+ 8035988:	e13ffd17 	ldw	r4,-12(fp)
+ 803598c:	8034b480 	call	8034b48 <tcp_respond>
+
+         tp->t_timer[TCPT_KEEP] = (short)tcp_keepintvl;
+ 8035990:	d0a01f17 	ldw	r2,-32644(gp)
+ 8035994:	10ffffcc 	andi	r3,r2,65535
+ 8035998:	18e0001c 	xori	r3,r3,32768
+ 803599c:	18e00004 	addi	r3,r3,-32768
+ 80359a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80359a4:	10c00515 	stw	r3,20(r2)
+      }
+      else
+         tp->t_timer[TCPT_KEEP] = (short)tcp_keepidle;
+      break;
+ 80359a8:	00001406 	br	80359fc <tcp_timers+0x43c>
+         tp->t_timer[TCPT_KEEP] = (short)tcp_keepidle;
+ 80359ac:	d0a01e17 	ldw	r2,-32648(gp)
+ 80359b0:	10ffffcc 	andi	r3,r2,65535
+ 80359b4:	18e0001c 	xori	r3,r3,32768
+ 80359b8:	18e00004 	addi	r3,r3,-32768
+ 80359bc:	e0bffd17 	ldw	r2,-12(fp)
+ 80359c0:	10c00515 	stw	r3,20(r2)
+      break;
+ 80359c4:	00000d06 	br	80359fc <tcp_timers+0x43c>
+         goto dropit;
+ 80359c8:	0001883a 	nop
+ 80359cc:	00000106 	br	80359d4 <tcp_timers+0x414>
+            goto dropit;
+ 80359d0:	0001883a 	nop
+      dropit:
+      tcpstat.tcps_keepdrops++;
+ 80359d4:	008201b4 	movhi	r2,2054
+ 80359d8:	10b8b217 	ldw	r2,-7480(r2)
+ 80359dc:	10c00044 	addi	r3,r2,1
+ 80359e0:	008201b4 	movhi	r2,2054
+ 80359e4:	10f8b215 	stw	r3,-7480(r2)
+      tp = tcp_drop (tp, ETIMEDOUT);
+ 80359e8:	01401d04 	movi	r5,116
+ 80359ec:	e13ffd17 	ldw	r4,-12(fp)
+ 80359f0:	803504c0 	call	803504c <tcp_drop>
+ 80359f4:	e0bffd15 	stw	r2,-12(fp)
+      break;
+ 80359f8:	0001883a 	nop
+   }
+   return tp;
+ 80359fc:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8035a00:	e037883a 	mov	sp,fp
+ 8035a04:	dfc00117 	ldw	ra,4(sp)
+ 8035a08:	df000017 	ldw	fp,0(sp)
+ 8035a0c:	dec00204 	addi	sp,sp,8
+ 8035a10:	f800283a 	ret
+
+08035a14 <tcp_usrreq>:
+
+int
+tcp_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+ 8035a14:	defff604 	addi	sp,sp,-40
+ 8035a18:	dfc00915 	stw	ra,36(sp)
+ 8035a1c:	df000815 	stw	fp,32(sp)
+ 8035a20:	df000804 	addi	fp,sp,32
+ 8035a24:	e13ffa15 	stw	r4,-24(fp)
+ 8035a28:	e17ff915 	stw	r5,-28(fp)
+ 8035a2c:	e1bff815 	stw	r6,-32(fp)
+   struct inpcb * inp;
+   struct tcpcb * tp;
+   int   error =  0;
+ 8035a30:	e03ffe15 	stw	zero,-8(fp)
+
+#ifdef DO_TCPTRACE
+   int   ostate;
+#endif
+
+   req = so->so_req;    /* get request from socket struct */
+ 8035a34:	e0bffa17 	ldw	r2,-24(fp)
+ 8035a38:	10800717 	ldw	r2,28(r2)
+ 8035a3c:	e0bffd15 	stw	r2,-12(fp)
+   inp = sotoinpcb(so);
+ 8035a40:	e0bffa17 	ldw	r2,-24(fp)
+ 8035a44:	10800117 	ldw	r2,4(r2)
+ 8035a48:	e0bffc15 	stw	r2,-16(fp)
+   /*
+    * When a TCP is attached to a socket, then there will be
+    * a (struct inpcb) pointed at by the socket, and this
+    * structure will point at a subsidary (struct tcpcb).
+    */
+   if (inp == 0 && req != PRU_ATTACH) 
+ 8035a4c:	e0bffc17 	ldw	r2,-16(fp)
+ 8035a50:	1000041e 	bne	r2,zero,8035a64 <tcp_usrreq+0x50>
+ 8035a54:	e0bffd17 	ldw	r2,-12(fp)
+ 8035a58:	10000226 	beq	r2,zero,8035a64 <tcp_usrreq+0x50>
+   {
+      return (EINVAL);
+ 8035a5c:	00800584 	movi	r2,22
+ 8035a60:	00019506 	br	80360b8 <tcp_usrreq+0x6a4>
+   }
+
+   if (inp)
+ 8035a64:	e0bffc17 	ldw	r2,-16(fp)
+ 8035a68:	10000426 	beq	r2,zero,8035a7c <tcp_usrreq+0x68>
+      tp = intotcpcb(inp);
+ 8035a6c:	e0bffc17 	ldw	r2,-16(fp)
+ 8035a70:	10800917 	ldw	r2,36(r2)
+ 8035a74:	e0bfff15 	stw	r2,-4(fp)
+ 8035a78:	00000706 	br	8035a98 <tcp_usrreq+0x84>
+   else  /* inp and tp not set, make sure this is OK: */
+   { 
+      if (req == PRU_ATTACH)
+ 8035a7c:	e0bffd17 	ldw	r2,-12(fp)
+ 8035a80:	1000021e 	bne	r2,zero,8035a8c <tcp_usrreq+0x78>
+         tp = NULL;  /* stifle compiler warnings about using unassigned tp*/
+ 8035a84:	e03fff15 	stw	zero,-4(fp)
+ 8035a88:	00000306 	br	8035a98 <tcp_usrreq+0x84>
+      else
+      {
+         dtrap(); /* programming error? */
+ 8035a8c:	8028cd40 	call	8028cd4 <dtrap>
+         return EINVAL;
+ 8035a90:	00800584 	movi	r2,22
+ 8035a94:	00018806 	br	80360b8 <tcp_usrreq+0x6a4>
+      }
+   }
+
+   switch (req) 
+ 8035a98:	e0bffd17 	ldw	r2,-12(fp)
+ 8035a9c:	10800528 	cmpgeui	r2,r2,20
+ 8035aa0:	10016f1e 	bne	r2,zero,8036060 <tcp_usrreq+0x64c>
+ 8035aa4:	e0bffd17 	ldw	r2,-12(fp)
+ 8035aa8:	100690ba 	slli	r3,r2,2
+ 8035aac:	008200f4 	movhi	r2,2051
+ 8035ab0:	1885883a 	add	r2,r3,r2
+ 8035ab4:	1096af17 	ldw	r2,23228(r2)
+ 8035ab8:	1000683a 	jmp	r2
+ 8035abc:	08035b0c 	andi	zero,at,3436
+ 8035ac0:	08035b6c 	andhi	zero,at,3437
+ 8035ac4:	08035b94 	ori	zero,at,3438
+ 8035ac8:	08035bcc 	andi	zero,at,3439
+ 8035acc:	08035c04 	addi	zero,at,3440
+ 8035ad0:	08035d4c 	andi	zero,at,3445
+ 8035ad4:	08035d40 	call	8035d4 <OSCtxSw_SWITCH_PC+0x803594>
+ 8035ad8:	08035df4 	orhi	zero,at,3447
+ 8035adc:	08035e20 	cmpeqi	zero,at,3448
+ 8035ae0:	08035e2c 	andhi	zero,at,3448
+ 8035ae4:	08035e88 	cmpgei	zero,at,3450
+ 8035ae8:	08036060 	cmpeqi	zero,at,3457
+ 8035aec:	08035e98 	cmpnei	zero,at,3450
+ 8035af0:	08035ea4 	muli	zero,at,3450
+ 8035af4:	08035f5c 	xori	zero,at,3453
+ 8035af8:	0803602c 	andhi	zero,at,3456
+ 8035afc:	0803603c 	xorhi	zero,at,3456
+ 8035b00:	08035d34 	orhi	zero,at,3444
+ 8035b04:	08036060 	cmpeqi	zero,at,3457
+ 8035b08:	0803604c 	andi	zero,at,3457
+   /*
+    * TCP attaches to socket via PRU_ATTACH, reserving space,
+    * and an internet control block.
+    */
+   case PRU_ATTACH:
+      if (inp) 
+ 8035b0c:	e0bffc17 	ldw	r2,-16(fp)
+ 8035b10:	10000326 	beq	r2,zero,8035b20 <tcp_usrreq+0x10c>
+      {
+         error = EISCONN;
+ 8035b14:	00801fc4 	movi	r2,127
+ 8035b18:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035b1c:	00016506 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+      error = tcp_attach(so);
+ 8035b20:	e13ffa17 	ldw	r4,-24(fp)
+ 8035b24:	80360cc0 	call	80360cc <tcp_attach>
+ 8035b28:	e0bffe15 	stw	r2,-8(fp)
+      if (error)
+ 8035b2c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035b30:	10014f1e 	bne	r2,zero,8036070 <tcp_usrreq+0x65c>
+         break;
+      if ((so->so_options & SO_LINGER) && so->so_linger == 0)
+ 8035b34:	e0bffa17 	ldw	r2,-24(fp)
+ 8035b38:	10800417 	ldw	r2,16(r2)
+ 8035b3c:	1080200c 	andi	r2,r2,128
+ 8035b40:	10014d26 	beq	r2,zero,8036078 <tcp_usrreq+0x664>
+ 8035b44:	e0bffa17 	ldw	r2,-24(fp)
+ 8035b48:	1080080b 	ldhu	r2,32(r2)
+ 8035b4c:	10bfffcc 	andi	r2,r2,65535
+ 8035b50:	10a0001c 	xori	r2,r2,32768
+ 8035b54:	10a00004 	addi	r2,r2,-32768
+ 8035b58:	1001471e 	bne	r2,zero,8036078 <tcp_usrreq+0x664>
+         so->so_linger = TCP_LINGERTIME;
+ 8035b5c:	e0bffa17 	ldw	r2,-24(fp)
+ 8035b60:	00c01e04 	movi	r3,120
+ 8035b64:	10c0080d 	sth	r3,32(r2)
+#ifdef   DO_TCPTRACE
+      SETTP(tp, sototcpcb(so));
+#endif
+      break;
+ 8035b68:	00014306 	br	8036078 <tcp_usrreq+0x664>
+    * do this directly: have to initiate a PRU_DISCONNECT,
+    * which may finish later; embryonic TCB's can just
+    * be discarded here.
+    */
+   case PRU_DETACH:
+      if (tp->t_state > TCPS_LISTEN)
+ 8035b6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8035b70:	10800217 	ldw	r2,8(r2)
+ 8035b74:	10800090 	cmplti	r2,r2,2
+ 8035b78:	1000031e 	bne	r2,zero,8035b88 <tcp_usrreq+0x174>
+         SETTP(tp, tcp_disconnect(tp));
+ 8035b7c:	e13fff17 	ldw	r4,-4(fp)
+ 8035b80:	80361e40 	call	80361e4 <tcp_disconnect>
+      else
+         SETTP(tp, tcp_close(tp));
+      break;
+ 8035b84:	00014b06 	br	80360b4 <tcp_usrreq+0x6a0>
+         SETTP(tp, tcp_close(tp));
+ 8035b88:	e13fff17 	ldw	r4,-4(fp)
+ 8035b8c:	80350e80 	call	80350e8 <tcp_close>
+      break;
+ 8035b90:	00014806 	br	80360b4 <tcp_usrreq+0x6a0>
+      /* bind is quite different for IPv4 and v6, so we use two 
+       * seperate pcbbind routines. so_domain was checked for 
+       * validity way up in t_bind()
+       */
+#ifdef IP_V4
+      if(inp->inp_socket->so_domain == AF_INET)
+ 8035b94:	e0bffc17 	ldw	r2,-16(fp)
+ 8035b98:	10800817 	ldw	r2,32(r2)
+ 8035b9c:	10800517 	ldw	r2,20(r2)
+ 8035ba0:	10800098 	cmpnei	r2,r2,2
+ 8035ba4:	1000051e 	bne	r2,zero,8035bbc <tcp_usrreq+0x1a8>
+      {
+         error = in_pcbbind(inp, nam);
+ 8035ba8:	e17ff817 	ldw	r5,-32(fp)
+ 8035bac:	e13ffc17 	ldw	r4,-16(fp)
+ 8035bb0:	804060c0 	call	804060c <in_pcbbind>
+ 8035bb4:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035bb8:	00013e06 	br	80360b4 <tcp_usrreq+0x6a0>
+      {
+         error = ip6_pcbbind(inp, nam);
+         break;
+      }
+#endif /* IP_V6 */
+      dtrap();    /* not v4 or v6? */
+ 8035bbc:	8028cd40 	call	8028cd4 <dtrap>
+      error = EINVAL;
+ 8035bc0:	00800584 	movi	r2,22
+ 8035bc4:	e0bffe15 	stw	r2,-8(fp)
+      break;
+ 8035bc8:	00013a06 	br	80360b4 <tcp_usrreq+0x6a0>
+   /*
+    * Prepare to accept connections.
+    */
+   case PRU_LISTEN:
+      if (inp->inp_lport == 0)
+ 8035bcc:	e0bffc17 	ldw	r2,-16(fp)
+ 8035bd0:	1080078b 	ldhu	r2,30(r2)
+ 8035bd4:	10bfffcc 	andi	r2,r2,65535
+ 8035bd8:	1000041e 	bne	r2,zero,8035bec <tcp_usrreq+0x1d8>
+         error = in_pcbbind(inp, (struct mbuf *)0);
+ 8035bdc:	000b883a 	mov	r5,zero
+ 8035be0:	e13ffc17 	ldw	r4,-16(fp)
+ 8035be4:	804060c0 	call	804060c <in_pcbbind>
+ 8035be8:	e0bffe15 	stw	r2,-8(fp)
+      if (error == 0)
+ 8035bec:	e0bffe17 	ldw	r2,-8(fp)
+ 8035bf0:	1001231e 	bne	r2,zero,8036080 <tcp_usrreq+0x66c>
+         tp->t_state = TCPS_LISTEN;
+ 8035bf4:	e0bfff17 	ldw	r2,-4(fp)
+ 8035bf8:	00c00044 	movi	r3,1
+ 8035bfc:	10c00215 	stw	r3,8(r2)
+      break;
+ 8035c00:	00011f06 	br	8036080 <tcp_usrreq+0x66c>
+    * Enter SYN_SENT state, and mark socket as connecting.
+    * Start keep-alive timer, and seed output sequence space.
+    * Send initial segment on connection.
+    */
+   case PRU_CONNECT:
+      if (inp->inp_lport == 0) 
+ 8035c04:	e0bffc17 	ldw	r2,-16(fp)
+ 8035c08:	1080078b 	ldhu	r2,30(r2)
+ 8035c0c:	10bfffcc 	andi	r2,r2,65535
+ 8035c10:	1000061e 	bne	r2,zero,8035c2c <tcp_usrreq+0x218>
+      {
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      error = in_pcbbind(inp, (struct mbuf *)0);
+ 8035c14:	000b883a 	mov	r5,zero
+ 8035c18:	e13ffc17 	ldw	r4,-16(fp)
+ 8035c1c:	804060c0 	call	804060c <in_pcbbind>
+ 8035c20:	e0bffe15 	stw	r2,-8(fp)
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+      error = ip6_pcbbind(inp, (struct mbuf *)0);
+#endif   /* end v6 only */
+
+         if (error)
+ 8035c24:	e0bffe17 	ldw	r2,-8(fp)
+ 8035c28:	1001171e 	bne	r2,zero,8036088 <tcp_usrreq+0x674>
+            break;
+      }
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      error = in_pcbconnect(inp, nam);
+ 8035c2c:	e17ff817 	ldw	r5,-32(fp)
+ 8035c30:	e13ffc17 	ldw	r4,-16(fp)
+ 8035c34:	804081c0 	call	804081c <in_pcbconnect>
+ 8035c38:	e0bffe15 	stw	r2,-8(fp)
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+      error = ip6_pcbconnect(inp, nam);
+#endif   /* end v6 only */
+
+      if (error)
+ 8035c3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8035c40:	1001131e 	bne	r2,zero,8036090 <tcp_usrreq+0x67c>
+         break;
+      tp->t_template = tcp_template(tp);
+ 8035c44:	e13fff17 	ldw	r4,-4(fp)
+ 8035c48:	8034a400 	call	8034a40 <tcp_template>
+ 8035c4c:	1007883a 	mov	r3,r2
+ 8035c50:	e0bfff17 	ldw	r2,-4(fp)
+ 8035c54:	10c00c15 	stw	r3,48(r2)
+      if (tp->t_template == 0) 
+ 8035c58:	e0bfff17 	ldw	r2,-4(fp)
+ 8035c5c:	10800c17 	ldw	r2,48(r2)
+ 8035c60:	1000051e 	bne	r2,zero,8035c78 <tcp_usrreq+0x264>
+      {
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+         in_pcbdisconnect(inp);
+ 8035c64:	e13ffc17 	ldw	r4,-16(fp)
+ 8035c68:	80409fc0 	call	80409fc <in_pcbdisconnect>
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+         ip6_pcbdisconnect(inp);
+#endif   /* end v6 only */
+
+         error = ENOBUFS;
+ 8035c6c:	00801a44 	movi	r2,105
+ 8035c70:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035c74:	00010f06 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+
+      soisconnecting(so);
+ 8035c78:	e13ffa17 	ldw	r4,-24(fp)
+ 8035c7c:	802f1780 	call	802f178 <soisconnecting>
+      tcpstat.tcps_connattempt++;
+ 8035c80:	008201b4 	movhi	r2,2054
+ 8035c84:	10b8a417 	ldw	r2,-7536(r2)
+ 8035c88:	10c00044 	addi	r3,r2,1
+ 8035c8c:	008201b4 	movhi	r2,2054
+ 8035c90:	10f8a415 	stw	r3,-7536(r2)
+      tp->t_state = TCPS_SYN_SENT;
+ 8035c94:	e0bfff17 	ldw	r2,-4(fp)
+ 8035c98:	00c00084 	movi	r3,2
+ 8035c9c:	10c00215 	stw	r3,8(r2)
+      tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT;
+ 8035ca0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035ca4:	00c02584 	movi	r3,150
+ 8035ca8:	10c00515 	stw	r3,20(r2)
+      tp->iss = tcp_iss; 
+ 8035cac:	d0e08a17 	ldw	r3,-32216(gp)
+ 8035cb0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cb4:	10c01315 	stw	r3,76(r2)
+      tcp_iss += (tcp_seq)(TCP_ISSINCR/2);
+ 8035cb8:	d0e08a17 	ldw	r3,-32216(gp)
+ 8035cbc:	00be9fd4 	movui	r2,64127
+ 8035cc0:	1885883a 	add	r2,r3,r2
+ 8035cc4:	d0a08a15 	stw	r2,-32216(gp)
+      tcp_sendseqinit(tp);
+ 8035cc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8035ccc:	10c01317 	ldw	r3,76(r2)
+ 8035cd0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cd4:	10c01015 	stw	r3,64(r2)
+ 8035cd8:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cdc:	10c01017 	ldw	r3,64(r2)
+ 8035ce0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035ce4:	10c01a15 	stw	r3,104(r2)
+ 8035ce8:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cec:	10c01a17 	ldw	r3,104(r2)
+ 8035cf0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cf4:	10c00f15 	stw	r3,60(r2)
+ 8035cf8:	e0bfff17 	ldw	r2,-4(fp)
+ 8035cfc:	10c00f17 	ldw	r3,60(r2)
+ 8035d00:	e0bfff17 	ldw	r2,-4(fp)
+ 8035d04:	10c00e15 	stw	r3,56(r2)
+      error = tcp_output(tp);
+ 8035d08:	e13fff17 	ldw	r4,-4(fp)
+ 8035d0c:	80338940 	call	8033894 <tcp_output>
+ 8035d10:	e0bffe15 	stw	r2,-8(fp)
+      if (!error)
+ 8035d14:	e0bffe17 	ldw	r2,-8(fp)
+ 8035d18:	1000df1e 	bne	r2,zero,8036098 <tcp_usrreq+0x684>
+         TCP_MIB_INC(tcpActiveOpens);     /* keep MIB stats */
+ 8035d1c:	008201b4 	movhi	r2,2054
+ 8035d20:	10b87a17 	ldw	r2,-7704(r2)
+ 8035d24:	10c00044 	addi	r3,r2,1
+ 8035d28:	008201b4 	movhi	r2,2054
+ 8035d2c:	10f87a15 	stw	r3,-7704(r2)
+      break;
+ 8035d30:	0000d906 	br	8036098 <tcp_usrreq+0x684>
+
+   /*
+    * Create a TCP connection between two sockets.
+    */
+   case PRU_CONNECT2:
+      error = EOPNOTSUPP;
+ 8035d34:	008017c4 	movi	r2,95
+ 8035d38:	e0bffe15 	stw	r2,-8(fp)
+      break;
+ 8035d3c:	0000dd06 	br	80360b4 <tcp_usrreq+0x6a0>
+    * when peer sends FIN and acks ours.
+    *
+    * SHOULD IMPLEMENT LATER PRU_CONNECT VIA REALLOC TCPCB.
+    */
+   case PRU_DISCONNECT:
+      SETTP(tp, tcp_disconnect(tp));
+ 8035d40:	e13fff17 	ldw	r4,-4(fp)
+ 8035d44:	80361e40 	call	80361e4 <tcp_disconnect>
+      break;
+ 8035d48:	0000da06 	br	80360b4 <tcp_usrreq+0x6a0>
+    * done at higher levels; just return the address
+    * of the peer, storing through addr.
+    */
+   case PRU_ACCEPT: 
+   {
+         struct sockaddr_in * sin   =  mtod(nam,   struct sockaddr_in *);
+ 8035d4c:	e0bff817 	ldw	r2,-32(fp)
+ 8035d50:	10800317 	ldw	r2,12(r2)
+ 8035d54:	e0bffb15 	stw	r2,-20(fp)
+            IP6CPY(&sin6->sin6_addr, &inp->ip6_faddr);
+         }
+#endif
+
+#ifdef IP_V4
+         if (so->so_domain == AF_INET)
+ 8035d58:	e0bffa17 	ldw	r2,-24(fp)
+ 8035d5c:	10800517 	ldw	r2,20(r2)
+ 8035d60:	10800098 	cmpnei	r2,r2,2
+ 8035d64:	10000e1e 	bne	r2,zero,8035da0 <tcp_usrreq+0x38c>
+         {
+            nam->m_len = sizeof (struct sockaddr_in);
+ 8035d68:	e0bff817 	ldw	r2,-32(fp)
+ 8035d6c:	00c00404 	movi	r3,16
+ 8035d70:	10c00215 	stw	r3,8(r2)
+            sin->sin_family = AF_INET;
+ 8035d74:	e0bffb17 	ldw	r2,-20(fp)
+ 8035d78:	00c00084 	movi	r3,2
+ 8035d7c:	10c0000d 	sth	r3,0(r2)
+            sin->sin_port = inp->inp_fport;
+ 8035d80:	e0bffc17 	ldw	r2,-16(fp)
+ 8035d84:	10c0070b 	ldhu	r3,28(r2)
+ 8035d88:	e0bffb17 	ldw	r2,-20(fp)
+ 8035d8c:	10c0008d 	sth	r3,2(r2)
+            sin->sin_addr = inp->inp_faddr;
+ 8035d90:	e0bffb17 	ldw	r2,-20(fp)
+ 8035d94:	e0fffc17 	ldw	r3,-16(fp)
+ 8035d98:	18c00317 	ldw	r3,12(r3)
+ 8035d9c:	10c00115 	stw	r3,4(r2)
+         }
+#endif
+         if ( !(so->so_domain == AF_INET) &&
+ 8035da0:	e0bffa17 	ldw	r2,-24(fp)
+ 8035da4:	10800517 	ldw	r2,20(r2)
+ 8035da8:	108000a0 	cmpeqi	r2,r2,2
+ 8035dac:	10000b1e 	bne	r2,zero,8035ddc <tcp_usrreq+0x3c8>
+              !(so->so_domain == AF_INET6)
+ 8035db0:	e0bffa17 	ldw	r2,-24(fp)
+ 8035db4:	10800517 	ldw	r2,20(r2)
+         if ( !(so->so_domain == AF_INET) &&
+ 8035db8:	108000e0 	cmpeqi	r2,r2,3
+ 8035dbc:	1000071e 	bne	r2,zero,8035ddc <tcp_usrreq+0x3c8>
+             )
+         {
+            dprintf("*** PRU_ACCEPT bad domain = %d\n", so->so_domain);
+ 8035dc0:	e0bffa17 	ldw	r2,-24(fp)
+ 8035dc4:	10800517 	ldw	r2,20(r2)
+ 8035dc8:	100b883a 	mov	r5,r2
+ 8035dcc:	01020174 	movhi	r4,2053
+ 8035dd0:	212abb04 	addi	r4,r4,-21780
+ 8035dd4:	8002c780 	call	8002c78 <printf>
+            dtrap();
+ 8035dd8:	8028cd40 	call	8028cd4 <dtrap>
+         } 
+         TCP_MIB_INC(tcpPassiveOpens);    /* keep MIB stats */
+ 8035ddc:	008201b4 	movhi	r2,2054
+ 8035de0:	10b87b17 	ldw	r2,-7700(r2)
+ 8035de4:	10c00044 	addi	r3,r2,1
+ 8035de8:	008201b4 	movhi	r2,2054
+ 8035dec:	10f87b15 	stw	r3,-7700(r2)
+         break;
+ 8035df0:	0000b006 	br	80360b4 <tcp_usrreq+0x6a0>
+
+   /*
+    * Mark the connection as being incapable of further output.
+    */
+   case PRU_SHUTDOWN:
+      socantsendmore(so);
+ 8035df4:	e13ffa17 	ldw	r4,-24(fp)
+ 8035df8:	802f7f40 	call	802f7f4 <socantsendmore>
+      tp = tcp_usrclosed(tp);
+ 8035dfc:	e13fff17 	ldw	r4,-4(fp)
+ 8035e00:	80362b00 	call	80362b0 <tcp_usrclosed>
+ 8035e04:	e0bfff15 	stw	r2,-4(fp)
+      if (tp)
+ 8035e08:	e0bfff17 	ldw	r2,-4(fp)
+ 8035e0c:	1000a426 	beq	r2,zero,80360a0 <tcp_usrreq+0x68c>
+         error = tcp_output(tp);
+ 8035e10:	e13fff17 	ldw	r4,-4(fp)
+ 8035e14:	80338940 	call	8033894 <tcp_output>
+ 8035e18:	e0bffe15 	stw	r2,-8(fp)
+      break;
+ 8035e1c:	0000a006 	br	80360a0 <tcp_usrreq+0x68c>
+
+   /*
+    * After a receive, possibly send window update to peer.
+    */
+   case PRU_RCVD:
+      (void) tcp_output(tp);
+ 8035e20:	e13fff17 	ldw	r4,-4(fp)
+ 8035e24:	80338940 	call	8033894 <tcp_output>
+      break;
+ 8035e28:	0000a206 	br	80360b4 <tcp_usrreq+0x6a0>
+   /*
+    * Do a send by putting data in output queue and updating urgent
+    * marker if URG set.  Possibly send more data.
+    */
+   case PRU_SEND:
+      if (so->so_pcb == NULL)
+ 8035e2c:	e0bffa17 	ldw	r2,-24(fp)
+ 8035e30:	10800117 	ldw	r2,4(r2)
+ 8035e34:	1000031e 	bne	r2,zero,8035e44 <tcp_usrreq+0x430>
+      {                    /* Return EPIPE error if socket is not connected */
+         error = EPIPE;
+ 8035e38:	00800804 	movi	r2,32
+ 8035e3c:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035e40:	00009c06 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+      sbappend(&so->so_snd, m);
+ 8035e44:	e0bffa17 	ldw	r2,-24(fp)
+ 8035e48:	10801204 	addi	r2,r2,72
+ 8035e4c:	e17ff917 	ldw	r5,-28(fp)
+ 8035e50:	1009883a 	mov	r4,r2
+ 8035e54:	802fafc0 	call	802fafc <sbappend>
+      error = tcp_output(tp);
+ 8035e58:	e13fff17 	ldw	r4,-4(fp)
+ 8035e5c:	80338940 	call	8033894 <tcp_output>
+ 8035e60:	e0bffe15 	stw	r2,-8(fp)
+      if (error == ENOBUFS)
+ 8035e64:	e0bffe17 	ldw	r2,-8(fp)
+ 8035e68:	10801a58 	cmpnei	r2,r2,105
+ 8035e6c:	10008e1e 	bne	r2,zero,80360a8 <tcp_usrreq+0x694>
+         sbdropend(&so->so_snd,m);  /* Remove data from socket buffer */
+ 8035e70:	e0bffa17 	ldw	r2,-24(fp)
+ 8035e74:	10801204 	addi	r2,r2,72
+ 8035e78:	e17ff917 	ldw	r5,-28(fp)
+ 8035e7c:	1009883a 	mov	r4,r2
+ 8035e80:	80302680 	call	8030268 <sbdropend>
+      break;
+ 8035e84:	00008806 	br	80360a8 <tcp_usrreq+0x694>
+
+   /*
+    * Abort the TCP.
+    */
+   case PRU_ABORT:
+      SETTP(tp, tcp_drop(tp, ECONNABORTED));
+ 8035e88:	01401c44 	movi	r5,113
+ 8035e8c:	e13fff17 	ldw	r4,-4(fp)
+ 8035e90:	803504c0 	call	803504c <tcp_drop>
+      break;
+ 8035e94:	00008706 	br	80360b4 <tcp_usrreq+0x6a0>
+
+   case PRU_SENSE:
+      /*      ((struct stat *) m)->st_blksize = so->so_snd.sb_hiwat; */
+      dtrap();    /* does this ever happen? */
+ 8035e98:	8028cd40 	call	8028cd4 <dtrap>
+      return (0);
+ 8035e9c:	0005883a 	mov	r2,zero
+ 8035ea0:	00008506 	br	80360b8 <tcp_usrreq+0x6a4>
+
+   case PRU_RCVOOB:
+      if ((so->so_oobmark == 0 &&
+ 8035ea4:	e0bffa17 	ldw	r2,-24(fp)
+ 8035ea8:	10801a17 	ldw	r2,104(r2)
+ 8035eac:	1000051e 	bne	r2,zero,8035ec4 <tcp_usrreq+0x4b0>
+          (so->so_state & SS_RCVATMARK) == 0) ||
+ 8035eb0:	e0bffa17 	ldw	r2,-24(fp)
+ 8035eb4:	1080088b 	ldhu	r2,34(r2)
+ 8035eb8:	10bfffcc 	andi	r2,r2,65535
+ 8035ebc:	1080100c 	andi	r2,r2,64
+      if ((so->so_oobmark == 0 &&
+ 8035ec0:	10000926 	beq	r2,zero,8035ee8 <tcp_usrreq+0x4d4>
+#ifdef SO_OOBINLINE
+       so->so_options & SO_OOBINLINE ||
+ 8035ec4:	e0bffa17 	ldw	r2,-24(fp)
+ 8035ec8:	10800417 	ldw	r2,16(r2)
+ 8035ecc:	1080400c 	andi	r2,r2,256
+          (so->so_state & SS_RCVATMARK) == 0) ||
+ 8035ed0:	1000051e 	bne	r2,zero,8035ee8 <tcp_usrreq+0x4d4>
+#endif
+       tp->t_oobflags & TCPOOB_HADDATA) 
+ 8035ed4:	e0bfff17 	ldw	r2,-4(fp)
+ 8035ed8:	10802403 	ldbu	r2,144(r2)
+ 8035edc:	10803fcc 	andi	r2,r2,255
+ 8035ee0:	1080008c 	andi	r2,r2,2
+       so->so_options & SO_OOBINLINE ||
+ 8035ee4:	10000326 	beq	r2,zero,8035ef4 <tcp_usrreq+0x4e0>
+       {
+         error = EINVAL;
+ 8035ee8:	00800584 	movi	r2,22
+ 8035eec:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035ef0:	00007006 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+      if ((tp->t_oobflags & TCPOOB_HAVEDATA) == 0) 
+ 8035ef4:	e0bfff17 	ldw	r2,-4(fp)
+ 8035ef8:	10802403 	ldbu	r2,144(r2)
+ 8035efc:	10803fcc 	andi	r2,r2,255
+ 8035f00:	1080004c 	andi	r2,r2,1
+ 8035f04:	1000031e 	bne	r2,zero,8035f14 <tcp_usrreq+0x500>
+      {
+         error = EWOULDBLOCK;
+ 8035f08:	008002c4 	movi	r2,11
+ 8035f0c:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035f10:	00006806 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+      m->m_len = 1;
+ 8035f14:	e0bff917 	ldw	r2,-28(fp)
+ 8035f18:	00c00044 	movi	r3,1
+ 8035f1c:	10c00215 	stw	r3,8(r2)
+      *mtod(m, char *) = tp->t_iobc;
+ 8035f20:	e0bff917 	ldw	r2,-28(fp)
+ 8035f24:	10800317 	ldw	r2,12(r2)
+ 8035f28:	e0ffff17 	ldw	r3,-4(fp)
+ 8035f2c:	18c02443 	ldbu	r3,145(r3)
+ 8035f30:	10c00005 	stb	r3,0(r2)
+      if ((MBUF2LONG(nam) & MSG_PEEK) == 0)
+ 8035f34:	e0bff817 	ldw	r2,-32(fp)
+ 8035f38:	1080008c 	andi	r2,r2,2
+ 8035f3c:	10005c1e 	bne	r2,zero,80360b0 <tcp_usrreq+0x69c>
+         tp->t_oobflags ^= (TCPOOB_HAVEDATA | TCPOOB_HADDATA);
+ 8035f40:	e0bfff17 	ldw	r2,-4(fp)
+ 8035f44:	10802403 	ldbu	r2,144(r2)
+ 8035f48:	108000dc 	xori	r2,r2,3
+ 8035f4c:	1007883a 	mov	r3,r2
+ 8035f50:	e0bfff17 	ldw	r2,-4(fp)
+ 8035f54:	10c02405 	stb	r3,144(r2)
+      break;
+ 8035f58:	00005506 	br	80360b0 <tcp_usrreq+0x69c>
+
+   case PRU_SENDOOB:
+      if (so->so_pcb == NULL)
+ 8035f5c:	e0bffa17 	ldw	r2,-24(fp)
+ 8035f60:	10800117 	ldw	r2,4(r2)
+ 8035f64:	1000031e 	bne	r2,zero,8035f74 <tcp_usrreq+0x560>
+      {                    /* Return EPIPE error if socket is not connected */
+         error = EPIPE;
+ 8035f68:	00800804 	movi	r2,32
+ 8035f6c:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035f70:	00005006 	br	80360b4 <tcp_usrreq+0x6a0>
+      }
+      if (sbspace(&so->so_snd) == 0) 
+ 8035f74:	e0bffa17 	ldw	r2,-24(fp)
+ 8035f78:	10801317 	ldw	r2,76(r2)
+ 8035f7c:	1007883a 	mov	r3,r2
+ 8035f80:	e0bffa17 	ldw	r2,-24(fp)
+ 8035f84:	10801217 	ldw	r2,72(r2)
+ 8035f88:	1885c83a 	sub	r2,r3,r2
+ 8035f8c:	10000516 	blt	r2,zero,8035fa4 <tcp_usrreq+0x590>
+ 8035f90:	e0bffa17 	ldw	r2,-24(fp)
+ 8035f94:	10c01317 	ldw	r3,76(r2)
+ 8035f98:	e0bffa17 	ldw	r2,-24(fp)
+ 8035f9c:	10801217 	ldw	r2,72(r2)
+ 8035fa0:	1880051e 	bne	r3,r2,8035fb8 <tcp_usrreq+0x5a4>
+      {
+         m_freem(m);
+ 8035fa4:	e13ff917 	ldw	r4,-28(fp)
+ 8035fa8:	8029cfc0 	call	8029cfc <m_freem>
+         error = ENOBUFS;
+ 8035fac:	00801a44 	movi	r2,105
+ 8035fb0:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 8035fb4:	00003f06 	br	80360b4 <tcp_usrreq+0x6a0>
+       * of urgent data.  We continue, however,
+       * to consider it to indicate the first octet
+       * of data past the urgent section.
+       * Otherwise, snd_up should be one lower.
+       */
+      sbappend(&so->so_snd, m);
+ 8035fb8:	e0bffa17 	ldw	r2,-24(fp)
+ 8035fbc:	10801204 	addi	r2,r2,72
+ 8035fc0:	e17ff917 	ldw	r5,-28(fp)
+ 8035fc4:	1009883a 	mov	r4,r2
+ 8035fc8:	802fafc0 	call	802fafc <sbappend>
+      tp->snd_up = tp->snd_una + so->so_snd.sb_cc;
+ 8035fcc:	e0bfff17 	ldw	r2,-4(fp)
+ 8035fd0:	10c00e17 	ldw	r3,56(r2)
+ 8035fd4:	e0bffa17 	ldw	r2,-24(fp)
+ 8035fd8:	10801217 	ldw	r2,72(r2)
+ 8035fdc:	1887883a 	add	r3,r3,r2
+ 8035fe0:	e0bfff17 	ldw	r2,-4(fp)
+ 8035fe4:	10c01015 	stw	r3,64(r2)
+      tp->t_force = 1;
+ 8035fe8:	e0bfff17 	ldw	r2,-4(fp)
+ 8035fec:	00c00044 	movi	r3,1
+ 8035ff0:	10c00a85 	stb	r3,42(r2)
+      error = tcp_output(tp);
+ 8035ff4:	e13fff17 	ldw	r4,-4(fp)
+ 8035ff8:	80338940 	call	8033894 <tcp_output>
+ 8035ffc:	e0bffe15 	stw	r2,-8(fp)
+      if (error == ENOBUFS)
+ 8036000:	e0bffe17 	ldw	r2,-8(fp)
+ 8036004:	10801a58 	cmpnei	r2,r2,105
+ 8036008:	1000051e 	bne	r2,zero,8036020 <tcp_usrreq+0x60c>
+         sbdropend(&so->so_snd,m);  /* Remove data from socket buffer */
+ 803600c:	e0bffa17 	ldw	r2,-24(fp)
+ 8036010:	10801204 	addi	r2,r2,72
+ 8036014:	e17ff917 	ldw	r5,-28(fp)
+ 8036018:	1009883a 	mov	r4,r2
+ 803601c:	80302680 	call	8030268 <sbdropend>
+      tp->t_force = 0;
+ 8036020:	e0bfff17 	ldw	r2,-4(fp)
+ 8036024:	10000a85 	stb	zero,42(r2)
+      break;
+ 8036028:	00002206 	br	80360b4 <tcp_usrreq+0x6a0>
+   case PRU_SOCKADDR:
+
+   /* sockaddr and peeraddr have to switch based on IP type */
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      in_setsockaddr(inp, nam);
+ 803602c:	e17ff817 	ldw	r5,-32(fp)
+ 8036030:	e13ffc17 	ldw	r4,-16(fp)
+ 8036034:	8040a580 	call	8040a58 <in_setsockaddr>
+         in_setsockaddr(inp, nam);
+#endif   /* dual mode */
+#else    /* IP_V6 */
+         ip6_setsockaddr(inp, nam);
+#endif
+      break;         
+ 8036038:	00001e06 	br	80360b4 <tcp_usrreq+0x6a0>
+
+   case PRU_PEERADDR:
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      in_setpeeraddr(inp, nam);
+ 803603c:	e17ff817 	ldw	r5,-32(fp)
+ 8036040:	e13ffc17 	ldw	r4,-16(fp)
+ 8036044:	8040adc0 	call	8040adc <in_setpeeraddr>
+         in_setpeeraddr(inp, nam);
+#endif   /* dual mode */
+#else    /* IP_V6 */
+         ip6_setpeeraddr(inp, nam);
+#endif
+      break;
+ 8036048:	00001a06 	br	80360b4 <tcp_usrreq+0x6a0>
+
+   case PRU_SLOWTIMO:
+      SETTP(tp, tcp_timers(tp, (int)MBUF2LONG(nam)));
+ 803604c:	e0bff817 	ldw	r2,-32(fp)
+ 8036050:	100b883a 	mov	r5,r2
+ 8036054:	e13fff17 	ldw	r4,-4(fp)
+ 8036058:	80355c00 	call	80355c0 <tcp_timers>
+#ifdef DO_TCPTRACE
+      req |= (long)nam << 8;        /* for debug's sake */
+#endif
+      break;
+ 803605c:	00001506 	br	80360b4 <tcp_usrreq+0x6a0>
+
+      default:
+      panic("tcp_usrreq");
+ 8036060:	01020174 	movhi	r4,2053
+ 8036064:	212ac304 	addi	r4,r4,-21748
+ 8036068:	80271780 	call	8027178 <panic>
+ 803606c:	00001106 	br	80360b4 <tcp_usrreq+0x6a0>
+         break;
+ 8036070:	0001883a 	nop
+ 8036074:	00000f06 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 8036078:	0001883a 	nop
+ 803607c:	00000d06 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 8036080:	0001883a 	nop
+ 8036084:	00000b06 	br	80360b4 <tcp_usrreq+0x6a0>
+            break;
+ 8036088:	0001883a 	nop
+ 803608c:	00000906 	br	80360b4 <tcp_usrreq+0x6a0>
+         break;
+ 8036090:	0001883a 	nop
+ 8036094:	00000706 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 8036098:	0001883a 	nop
+ 803609c:	00000506 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 80360a0:	0001883a 	nop
+ 80360a4:	00000306 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 80360a8:	0001883a 	nop
+ 80360ac:	00000106 	br	80360b4 <tcp_usrreq+0x6a0>
+      break;
+ 80360b0:	0001883a 	nop
+#ifdef DO_TCPTRACE
+   if (tp && (so->so_options & SO_DEBUG))
+      tcp_trace("usrreq: state: %d, tcpcb: %x, req: %d",
+    ostate, tp, req);
+#endif
+   return (error);
+ 80360b4:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 80360b8:	e037883a 	mov	sp,fp
+ 80360bc:	dfc00117 	ldw	ra,4(sp)
+ 80360c0:	df000017 	ldw	fp,0(sp)
+ 80360c4:	dec00204 	addi	sp,sp,8
+ 80360c8:	f800283a 	ret
+
+080360cc <tcp_attach>:
+ * RETURNS: 0 if OK, or nonzero error code.
+ */
+
+int
+tcp_attach(struct socket * so)
+{
+ 80360cc:	defff904 	addi	sp,sp,-28
+ 80360d0:	dfc00615 	stw	ra,24(sp)
+ 80360d4:	df000515 	stw	fp,20(sp)
+ 80360d8:	df000504 	addi	fp,sp,20
+ 80360dc:	e13ffb15 	stw	r4,-20(fp)
+   struct tcpcb * tp;
+   struct inpcb * inp;
+   int   error;
+
+   if (so->so_snd.sb_hiwat == 0 || so->so_rcv.sb_hiwat == 0) 
+ 80360e0:	e0bffb17 	ldw	r2,-20(fp)
+ 80360e4:	10801317 	ldw	r2,76(r2)
+ 80360e8:	10000326 	beq	r2,zero,80360f8 <tcp_attach+0x2c>
+ 80360ec:	e0bffb17 	ldw	r2,-20(fp)
+ 80360f0:	10800b17 	ldw	r2,44(r2)
+ 80360f4:	10000b1e 	bne	r2,zero,8036124 <tcp_attach+0x58>
+   {
+      error = soreserve(so, tcp_sendspace, tcp_recvspace);
+ 80360f8:	d0a02017 	ldw	r2,-32640(gp)
+ 80360fc:	d0e02117 	ldw	r3,-32636(gp)
+ 8036100:	180d883a 	mov	r6,r3
+ 8036104:	100b883a 	mov	r5,r2
+ 8036108:	e13ffb17 	ldw	r4,-20(fp)
+ 803610c:	802f9d80 	call	802f9d8 <soreserve>
+ 8036110:	e0bfff15 	stw	r2,-4(fp)
+      if (error)
+ 8036114:	e0bfff17 	ldw	r2,-4(fp)
+ 8036118:	10000226 	beq	r2,zero,8036124 <tcp_attach+0x58>
+         return (error);
+ 803611c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036120:	00002b06 	br	80361d0 <tcp_attach+0x104>
+   }
+   error = in_pcballoc(so, &tcb);
+ 8036124:	014201b4 	movhi	r5,2054
+ 8036128:	29789904 	addi	r5,r5,-7580
+ 803612c:	e13ffb17 	ldw	r4,-20(fp)
+ 8036130:	804052c0 	call	804052c <in_pcballoc>
+ 8036134:	e0bfff15 	stw	r2,-4(fp)
+   if (error)
+ 8036138:	e0bfff17 	ldw	r2,-4(fp)
+ 803613c:	10000226 	beq	r2,zero,8036148 <tcp_attach+0x7c>
+      return (error);
+ 8036140:	e0bfff17 	ldw	r2,-4(fp)
+ 8036144:	00002206 	br	80361d0 <tcp_attach+0x104>
+   inp = sotoinpcb(so);
+ 8036148:	e0bffb17 	ldw	r2,-20(fp)
+ 803614c:	10800117 	ldw	r2,4(r2)
+ 8036150:	e0bffe15 	stw	r2,-8(fp)
+   tp = tcp_newtcpcb(inp);
+ 8036154:	e13ffe17 	ldw	r4,-8(fp)
+ 8036158:	8034f400 	call	8034f40 <tcp_newtcpcb>
+ 803615c:	e0bffd15 	stw	r2,-12(fp)
+   if (tp == 0) 
+ 8036160:	e0bffd17 	ldw	r2,-12(fp)
+ 8036164:	1000171e 	bne	r2,zero,80361c4 <tcp_attach+0xf8>
+   {
+      int   nofd  =  so->so_state   &  SS_NOFDREF; /* XXX */
+ 8036168:	e0bffb17 	ldw	r2,-20(fp)
+ 803616c:	1080088b 	ldhu	r2,34(r2)
+ 8036170:	10bfffcc 	andi	r2,r2,65535
+ 8036174:	1080004c 	andi	r2,r2,1
+ 8036178:	e0bffc15 	stw	r2,-16(fp)
+
+      so->so_state &= ~SS_NOFDREF;     /* don't free the socket yet */
+ 803617c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036180:	10c0088b 	ldhu	r3,34(r2)
+ 8036184:	00bfff84 	movi	r2,-2
+ 8036188:	1884703a 	and	r2,r3,r2
+ 803618c:	1007883a 	mov	r3,r2
+ 8036190:	e0bffb17 	ldw	r2,-20(fp)
+ 8036194:	10c0088d 	sth	r3,34(r2)
+      in_pcbdetach(inp);
+ 8036198:	e13ffe17 	ldw	r4,-8(fp)
+ 803619c:	80405b40 	call	80405b4 <in_pcbdetach>
+      so->so_state |= nofd;
+ 80361a0:	e0bffb17 	ldw	r2,-20(fp)
+ 80361a4:	1080088b 	ldhu	r2,34(r2)
+ 80361a8:	e0fffc17 	ldw	r3,-16(fp)
+ 80361ac:	10c4b03a 	or	r2,r2,r3
+ 80361b0:	1007883a 	mov	r3,r2
+ 80361b4:	e0bffb17 	ldw	r2,-20(fp)
+ 80361b8:	10c0088d 	sth	r3,34(r2)
+      return (ENOBUFS);
+ 80361bc:	00801a44 	movi	r2,105
+ 80361c0:	00000306 	br	80361d0 <tcp_attach+0x104>
+   }
+   tp->t_state = TCPS_CLOSED;
+ 80361c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80361c8:	10000215 	stw	zero,8(r2)
+   return (0);
+ 80361cc:	0005883a 	mov	r2,zero
+}
+ 80361d0:	e037883a 	mov	sp,fp
+ 80361d4:	dfc00117 	ldw	ra,4(sp)
+ 80361d8:	df000017 	ldw	fp,0(sp)
+ 80361dc:	dec00204 	addi	sp,sp,8
+ 80361e0:	f800283a 	ret
+
+080361e4 <tcp_disconnect>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_disconnect(struct tcpcb * tp)
+{
+ 80361e4:	defffc04 	addi	sp,sp,-16
+ 80361e8:	dfc00315 	stw	ra,12(sp)
+ 80361ec:	df000215 	stw	fp,8(sp)
+ 80361f0:	df000204 	addi	fp,sp,8
+ 80361f4:	e13ffe15 	stw	r4,-8(fp)
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+ 80361f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80361fc:	10800d17 	ldw	r2,52(r2)
+ 8036200:	10800817 	ldw	r2,32(r2)
+ 8036204:	e0bfff15 	stw	r2,-4(fp)
+
+   if (tp->t_state < TCPS_ESTABLISHED)
+ 8036208:	e0bffe17 	ldw	r2,-8(fp)
+ 803620c:	10800217 	ldw	r2,8(r2)
+ 8036210:	10800108 	cmpgei	r2,r2,4
+ 8036214:	1000041e 	bne	r2,zero,8036228 <tcp_disconnect+0x44>
+      tp = tcp_close(tp);
+ 8036218:	e13ffe17 	ldw	r4,-8(fp)
+ 803621c:	80350e80 	call	80350e8 <tcp_close>
+ 8036220:	e0bffe15 	stw	r2,-8(fp)
+ 8036224:	00001c06 	br	8036298 <tcp_disconnect+0xb4>
+   else if ((so->so_options & SO_LINGER) && so->so_linger == 0)
+ 8036228:	e0bfff17 	ldw	r2,-4(fp)
+ 803622c:	10800417 	ldw	r2,16(r2)
+ 8036230:	1080200c 	andi	r2,r2,128
+ 8036234:	10000b26 	beq	r2,zero,8036264 <tcp_disconnect+0x80>
+ 8036238:	e0bfff17 	ldw	r2,-4(fp)
+ 803623c:	1080080b 	ldhu	r2,32(r2)
+ 8036240:	10bfffcc 	andi	r2,r2,65535
+ 8036244:	10a0001c 	xori	r2,r2,32768
+ 8036248:	10a00004 	addi	r2,r2,-32768
+ 803624c:	1000051e 	bne	r2,zero,8036264 <tcp_disconnect+0x80>
+      tp = tcp_drop(tp, 0);
+ 8036250:	000b883a 	mov	r5,zero
+ 8036254:	e13ffe17 	ldw	r4,-8(fp)
+ 8036258:	803504c0 	call	803504c <tcp_drop>
+ 803625c:	e0bffe15 	stw	r2,-8(fp)
+ 8036260:	00000d06 	br	8036298 <tcp_disconnect+0xb4>
+   else 
+   {
+      soisdisconnecting(so);
+ 8036264:	e13fff17 	ldw	r4,-4(fp)
+ 8036268:	802f2ec0 	call	802f2ec <soisdisconnecting>
+      sbflush(&so->so_rcv);
+ 803626c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036270:	10800a04 	addi	r2,r2,40
+ 8036274:	1009883a 	mov	r4,r2
+ 8036278:	803002c0 	call	803002c <sbflush>
+      tp = tcp_usrclosed(tp);
+ 803627c:	e13ffe17 	ldw	r4,-8(fp)
+ 8036280:	80362b00 	call	80362b0 <tcp_usrclosed>
+ 8036284:	e0bffe15 	stw	r2,-8(fp)
+      if (tp)
+ 8036288:	e0bffe17 	ldw	r2,-8(fp)
+ 803628c:	10000226 	beq	r2,zero,8036298 <tcp_disconnect+0xb4>
+         (void) tcp_output(tp);
+ 8036290:	e13ffe17 	ldw	r4,-8(fp)
+ 8036294:	80338940 	call	8033894 <tcp_output>
+   }
+   return (tp);
+ 8036298:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803629c:	e037883a 	mov	sp,fp
+ 80362a0:	dfc00117 	ldw	ra,4(sp)
+ 80362a4:	df000017 	ldw	fp,0(sp)
+ 80362a8:	dec00204 	addi	sp,sp,8
+ 80362ac:	f800283a 	ret
+
+080362b0 <tcp_usrclosed>:
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_usrclosed(struct tcpcb * tp)
+{
+ 80362b0:	defffd04 	addi	sp,sp,-12
+ 80362b4:	dfc00215 	stw	ra,8(sp)
+ 80362b8:	df000115 	stw	fp,4(sp)
+ 80362bc:	df000104 	addi	fp,sp,4
+ 80362c0:	e13fff15 	stw	r4,-4(fp)
+
+   switch (tp->t_state) 
+ 80362c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80362c8:	10800217 	ldw	r2,8(r2)
+ 80362cc:	10c001a8 	cmpgeui	r3,r2,6
+ 80362d0:	1800191e 	bne	r3,zero,8036338 <tcp_usrclosed+0x88>
+ 80362d4:	100690ba 	slli	r3,r2,2
+ 80362d8:	008200f4 	movhi	r2,2051
+ 80362dc:	1885883a 	add	r2,r3,r2
+ 80362e0:	1098ba17 	ldw	r2,25320(r2)
+ 80362e4:	1000683a 	jmp	r2
+ 80362e8:	08036300 	call	803630 <OSCtxSw_SWITCH_PC+0x8035f0>
+ 80362ec:	08036300 	call	803630 <OSCtxSw_SWITCH_PC+0x8035f0>
+ 80362f0:	08036300 	call	803630 <OSCtxSw_SWITCH_PC+0x8035f0>
+ 80362f4:	08036318 	cmpnei	zero,at,3468
+ 80362f8:	08036318 	cmpnei	zero,at,3468
+ 80362fc:	08036328 	cmpgeui	zero,at,3468
+   {
+   case TCPS_CLOSED:
+   case TCPS_LISTEN:
+   case TCPS_SYN_SENT:
+      tp->t_state = TCPS_CLOSED;
+ 8036300:	e0bfff17 	ldw	r2,-4(fp)
+ 8036304:	10000215 	stw	zero,8(r2)
+      tp = tcp_close(tp);
+ 8036308:	e13fff17 	ldw	r4,-4(fp)
+ 803630c:	80350e80 	call	80350e8 <tcp_close>
+ 8036310:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 8036314:	00000806 	br	8036338 <tcp_usrclosed+0x88>
+
+   case TCPS_SYN_RECEIVED:
+   case TCPS_ESTABLISHED:
+      tp->t_state = TCPS_FIN_WAIT_1;
+ 8036318:	e0bfff17 	ldw	r2,-4(fp)
+ 803631c:	00c00184 	movi	r3,6
+ 8036320:	10c00215 	stw	r3,8(r2)
+      break;
+ 8036324:	00000406 	br	8036338 <tcp_usrclosed+0x88>
+
+   case TCPS_CLOSE_WAIT:
+      tp->t_state = TCPS_LAST_ACK;
+ 8036328:	e0bfff17 	ldw	r2,-4(fp)
+ 803632c:	00c00204 	movi	r3,8
+ 8036330:	10c00215 	stw	r3,8(r2)
+      break;
+ 8036334:	0001883a 	nop
+   }
+   if (tp && tp->t_state >= TCPS_FIN_WAIT_2)
+ 8036338:	e0bfff17 	ldw	r2,-4(fp)
+ 803633c:	10000926 	beq	r2,zero,8036364 <tcp_usrclosed+0xb4>
+ 8036340:	e0bfff17 	ldw	r2,-4(fp)
+ 8036344:	10800217 	ldw	r2,8(r2)
+ 8036348:	10800250 	cmplti	r2,r2,9
+ 803634c:	1000051e 	bne	r2,zero,8036364 <tcp_usrclosed+0xb4>
+      soisdisconnected(tp->t_inpcb->inp_socket);
+ 8036350:	e0bfff17 	ldw	r2,-4(fp)
+ 8036354:	10800d17 	ldw	r2,52(r2)
+ 8036358:	10800817 	ldw	r2,32(r2)
+ 803635c:	1009883a 	mov	r4,r2
+ 8036360:	802f3840 	call	802f384 <soisdisconnected>
+   return (tp);
+ 8036364:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8036368:	e037883a 	mov	sp,fp
+ 803636c:	dfc00117 	ldw	ra,4(sp)
+ 8036370:	df000017 	ldw	fp,0(sp)
+ 8036374:	dec00204 	addi	sp,sp,8
+ 8036378:	f800283a 	ret
+
+0803637c <tcpinit>:
+ * RETURNS: 0 if OK, else one of the ENP_ error codes
+ */
+
+int
+tcpinit(void)
+{
+ 803637c:	defffd04 	addi	sp,sp,-12
+ 8036380:	dfc00215 	stw	ra,8(sp)
+ 8036384:	df000115 	stw	fp,4(sp)
+ 8036388:	df000104 	addi	fp,sp,4
+   tcp_sendspace = (TCP_MSS) * 2;
+   tcp_recvspace = (TCP_MSS) * 2;
+   TCPTV_MSL =    (4 * PR_SLOWHZ);     /* max seg lifetime default */
+#endif
+
+   e = nptcp_init();    /* call the NetPort init in nptcp.c */
+ 803638c:	802a3b00 	call	802a3b0 <nptcp_init>
+ 8036390:	e0bfff15 	stw	r2,-4(fp)
+   if (e)
+ 8036394:	e0bfff17 	ldw	r2,-4(fp)
+ 8036398:	10000226 	beq	r2,zero,80363a4 <tcpinit+0x28>
+      return e;
+ 803639c:	e0bfff17 	ldw	r2,-4(fp)
+ 80363a0:	00000106 	br	80363a8 <tcpinit+0x2c>
+
+   return 0;   /* good return */
+ 80363a4:	0005883a 	mov	r2,zero
+}
+ 80363a8:	e037883a 	mov	sp,fp
+ 80363ac:	dfc00117 	ldw	ra,4(sp)
+ 80363b0:	df000017 	ldw	fp,0(sp)
+ 80363b4:	dec00204 	addi	sp,sp,8
+ 80363b8:	f800283a 	ret
+
+080363bc <udp_lookup>:
+ * RETURNS: 
+ */
+
+UDPCONN
+udp_lookup(struct socket * so)
+{
+ 80363bc:	defffd04 	addi	sp,sp,-12
+ 80363c0:	df000215 	stw	fp,8(sp)
+ 80363c4:	df000204 	addi	fp,sp,8
+ 80363c8:	e13ffe15 	stw	r4,-8(fp)
+   UDPCONN tmp;
+
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 80363cc:	d0a09e17 	ldw	r2,-32136(gp)
+ 80363d0:	e0bfff15 	stw	r2,-4(fp)
+ 80363d4:	00000906 	br	80363fc <udp_lookup+0x40>
+      if (tmp->u_data == (void*)so)
+ 80363d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80363dc:	10800617 	ldw	r2,24(r2)
+ 80363e0:	e0fffe17 	ldw	r3,-8(fp)
+ 80363e4:	1880021e 	bne	r3,r2,80363f0 <udp_lookup+0x34>
+      return (tmp);
+ 80363e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80363ec:	00000606 	br	8036408 <udp_lookup+0x4c>
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 80363f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80363f4:	10800017 	ldw	r2,0(r2)
+ 80363f8:	e0bfff15 	stw	r2,-4(fp)
+ 80363fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8036400:	103ff51e 	bne	r2,zero,80363d8 <udp_lookup+0x1c>
+
+   return NULL;   /* didn't find it */
+ 8036404:	0005883a 	mov	r2,zero
+}
+ 8036408:	e037883a 	mov	sp,fp
+ 803640c:	df000017 	ldw	fp,0(sp)
+ 8036410:	dec00104 	addi	sp,sp,4
+ 8036414:	f800283a 	ret
+
+08036418 <udp_soinput>:
+ * RETURNS: 
+ */
+
+int
+udp_soinput(PACKET pkt, void * so_ptr)
+{
+ 8036418:	defff504 	addi	sp,sp,-44
+ 803641c:	dfc00a15 	stw	ra,40(sp)
+ 8036420:	df000915 	stw	fp,36(sp)
+ 8036424:	df000904 	addi	fp,sp,36
+ 8036428:	e13ff815 	stw	r4,-32(fp)
+ 803642c:	e17ff715 	stw	r5,-36(fp)
+   struct mbuf *  m_in;    /* packet/data mbuf */
+   struct socket *   so =  (struct  socket *)so_ptr;
+ 8036430:	e0bff717 	ldw	r2,-36(fp)
+ 8036434:	e0bfff15 	stw	r2,-4(fp)
+   struct sockaddr_in   sin;
+   struct udp *   udpp;
+
+   LOCK_NET_RESOURCE(NET_RESID); 
+ 8036438:	0009883a 	mov	r4,zero
+ 803643c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* make sure we're not flooding input buffers */
+   if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat)
+ 8036440:	e0bfff17 	ldw	r2,-4(fp)
+ 8036444:	10c00a17 	ldw	r3,40(r2)
+ 8036448:	e0bff817 	ldw	r2,-32(fp)
+ 803644c:	10800417 	ldw	r2,16(r2)
+ 8036450:	1887883a 	add	r3,r3,r2
+ 8036454:	e0bfff17 	ldw	r2,-4(fp)
+ 8036458:	10800b17 	ldw	r2,44(r2)
+ 803645c:	18800436 	bltu	r3,r2,8036470 <udp_soinput+0x58>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 8036460:	0009883a 	mov	r4,zero
+ 8036464:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 8036468:	00801a44 	movi	r2,105
+ 803646c:	00004d06 	br	80365a4 <udp_soinput+0x18c>
+   }
+
+   /* alloc mbuf for received data */
+   m_in = m_getnbuf(MT_RXDATA, 0);
+ 8036470:	000b883a 	mov	r5,zero
+ 8036474:	01000044 	movi	r4,1
+ 8036478:	8029a700 	call	8029a70 <m_getnbuf>
+ 803647c:	e0bffe15 	stw	r2,-8(fp)
+   if (!m_in)
+ 8036480:	e0bffe17 	ldw	r2,-8(fp)
+ 8036484:	1000041e 	bne	r2,zero,8036498 <udp_soinput+0x80>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 8036488:	0009883a 	mov	r4,zero
+ 803648c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 8036490:	00801a44 	movi	r2,105
+ 8036494:	00004306 	br	80365a4 <udp_soinput+0x18c>
+   }
+
+   /* set data mbuf to point to start of UDP data */
+   m_in->pkt = pkt;
+ 8036498:	e0bffe17 	ldw	r2,-8(fp)
+ 803649c:	e0fff817 	ldw	r3,-32(fp)
+ 80364a0:	10c00115 	stw	r3,4(r2)
+   m_in->m_data = pkt->nb_prot;
+ 80364a4:	e0bff817 	ldw	r2,-32(fp)
+ 80364a8:	10c00317 	ldw	r3,12(r2)
+ 80364ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80364b0:	10c00315 	stw	r3,12(r2)
+   m_in->m_len = pkt->nb_plen;
+ 80364b4:	e0bff817 	ldw	r2,-32(fp)
+ 80364b8:	10c00417 	ldw	r3,16(r2)
+ 80364bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80364c0:	10c00215 	stw	r3,8(r2)
+   m_in->m_base = pkt->nb_buff;
+ 80364c4:	e0bff817 	ldw	r2,-32(fp)
+ 80364c8:	10c00117 	ldw	r3,4(r2)
+ 80364cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80364d0:	10c00415 	stw	r3,16(r2)
+   m_in->m_memsz = pkt->nb_blen;
+ 80364d4:	e0bff817 	ldw	r2,-32(fp)
+ 80364d8:	10c00217 	ldw	r3,8(r2)
+ 80364dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80364e0:	10c00515 	stw	r3,20(r2)
+
+   /* fill in net address info for pass to socket append()ers */
+   sin.sin_addr.s_addr = pkt->fhost;
+ 80364e4:	e0bff817 	ldw	r2,-32(fp)
+ 80364e8:	10800717 	ldw	r2,28(r2)
+ 80364ec:	e0bffa15 	stw	r2,-24(fp)
+   udpp = (struct udp *)(pkt->nb_prot - sizeof(struct udp));
+ 80364f0:	e0bff817 	ldw	r2,-32(fp)
+ 80364f4:	10800317 	ldw	r2,12(r2)
+ 80364f8:	10bffe04 	addi	r2,r2,-8
+ 80364fc:	e0bffd15 	stw	r2,-12(fp)
+   sin.sin_port = htons(udpp->ud_srcp);
+ 8036500:	e0bffd17 	ldw	r2,-12(fp)
+ 8036504:	1080000b 	ldhu	r2,0(r2)
+ 8036508:	10bfffcc 	andi	r2,r2,65535
+ 803650c:	1004d23a 	srli	r2,r2,8
+ 8036510:	1007883a 	mov	r3,r2
+ 8036514:	e0bffd17 	ldw	r2,-12(fp)
+ 8036518:	1080000b 	ldhu	r2,0(r2)
+ 803651c:	10bfffcc 	andi	r2,r2,65535
+ 8036520:	1004923a 	slli	r2,r2,8
+ 8036524:	1884b03a 	or	r2,r3,r2
+ 8036528:	e0bff98d 	sth	r2,-26(fp)
+   sin.sin_family = AF_INET;
+ 803652c:	00800084 	movi	r2,2
+ 8036530:	e0bff90d 	sth	r2,-28(fp)
+
+   /* attempt to append address information to mbuf */
+   if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in))
+ 8036534:	e0bfff17 	ldw	r2,-4(fp)
+ 8036538:	10800a04 	addi	r2,r2,40
+ 803653c:	e0fff904 	addi	r3,fp,-28
+ 8036540:	e1bffe17 	ldw	r6,-8(fp)
+ 8036544:	180b883a 	mov	r5,r3
+ 8036548:	1009883a 	mov	r4,r2
+ 803654c:	802fc740 	call	802fc74 <sbappendaddr>
+ 8036550:	1000081e 	bne	r2,zero,8036574 <udp_soinput+0x15c>
+   {
+      /* set the pkt field in the mbuf to NULL so m_free() below wont 
+       * free the packet buffer, because that is left to the 
+       */
+      m_in->pkt = NULL;
+ 8036554:	e0bffe17 	ldw	r2,-8(fp)
+ 8036558:	10000115 	stw	zero,4(r2)
+      /* free only the mbuf itself */
+      m_free(m_in);
+ 803655c:	e13ffe17 	ldw	r4,-8(fp)
+ 8036560:	8029bf80 	call	8029bf8 <m_free>
+      /* return error condition so caller can free the packet buffer */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 8036564:	0009883a 	mov	r4,zero
+ 8036568:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENOBUFS;
+ 803656c:	00801a44 	movi	r2,105
+ 8036570:	00000c06 	br	80365a4 <udp_soinput+0x18c>
+   }
+
+   tcp_wakeup(&so->so_rcv);   /* wake anyone waiting for this */
+ 8036574:	e0bfff17 	ldw	r2,-4(fp)
+ 8036578:	10800a04 	addi	r2,r2,40
+ 803657c:	1009883a 	mov	r4,r2
+ 8036580:	8027ba00 	call	8027ba0 <tcp_wakeup>
+
+   sorwakeup(so);    /* wake up selects too */
+ 8036584:	e0bfff17 	ldw	r2,-4(fp)
+ 8036588:	10800a04 	addi	r2,r2,40
+ 803658c:	100b883a 	mov	r5,r2
+ 8036590:	e13fff17 	ldw	r4,-4(fp)
+ 8036594:	802f94c0 	call	802f94c <sbwakeup>
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 8036598:	0009883a 	mov	r4,zero
+ 803659c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return 0;
+ 80365a0:	0005883a 	mov	r2,zero
+}
+ 80365a4:	e037883a 	mov	sp,fp
+ 80365a8:	dfc00117 	ldw	ra,4(sp)
+ 80365ac:	df000017 	ldw	fp,0(sp)
+ 80365b0:	dec00204 	addi	sp,sp,8
+ 80365b4:	f800283a 	ret
+
+080365b8 <udp_usrreq>:
+
+int
+udp_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+ 80365b8:	defff804 	addi	sp,sp,-32
+ 80365bc:	dfc00715 	stw	ra,28(sp)
+ 80365c0:	df000615 	stw	fp,24(sp)
+ 80365c4:	df000604 	addi	fp,sp,24
+ 80365c8:	e13ffd15 	stw	r4,-12(fp)
+ 80365cc:	e17ffc15 	stw	r5,-16(fp)
+ 80365d0:	e1bffb15 	stw	r6,-20(fp)
+   UDPCONN udpconn = (UDPCONN)NULL;
+ 80365d4:	e03fff15 	stw	zero,-4(fp)
+   int   req;
+
+   req = so->so_req;    /* get request from socket struct */
+ 80365d8:	e0bffd17 	ldw	r2,-12(fp)
+ 80365dc:	10800717 	ldw	r2,28(r2)
+ 80365e0:	e0bffe15 	stw	r2,-8(fp)
+
+   switch (req) 
+ 80365e4:	e0bffe17 	ldw	r2,-8(fp)
+ 80365e8:	10800468 	cmpgeui	r2,r2,17
+ 80365ec:	10007a1e 	bne	r2,zero,80367d8 <udp_usrreq+0x220>
+ 80365f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80365f4:	100690ba 	slli	r3,r2,2
+ 80365f8:	008200f4 	movhi	r2,2051
+ 80365fc:	1885883a 	add	r2,r3,r2
+ 8036600:	10998217 	ldw	r2,26120(r2)
+ 8036604:	1000683a 	jmp	r2
+ 8036608:	0803664c 	andi	zero,at,3481
+ 803660c:	080366d0 	cmplti	zero,at,3483
+ 8036610:	0803670c 	andi	zero,at,3484
+ 8036614:	080367d8 	cmpnei	zero,at,3487
+ 8036618:	0803670c 	andi	zero,at,3484
+ 803661c:	080367d8 	cmpnei	zero,at,3487
+ 8036620:	080367cc 	andi	zero,at,3487
+ 8036624:	080367d8 	cmpnei	zero,at,3487
+ 8036628:	080367cc 	andi	zero,at,3487
+ 803662c:	0803674c 	andi	zero,at,3485
+ 8036630:	080367d8 	cmpnei	zero,at,3487
+ 8036634:	080367d8 	cmpnei	zero,at,3487
+ 8036638:	080367d8 	cmpnei	zero,at,3487
+ 803663c:	080367d8 	cmpnei	zero,at,3487
+ 8036640:	080367d8 	cmpnei	zero,at,3487
+ 8036644:	0803678c 	andi	zero,at,3486
+ 8036648:	0803678c 	andi	zero,at,3486
+   {
+   case PRU_ATTACH:
+      /* fake small windows so sockets asks us to move data */
+      so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = udp_maxalloc();
+ 803664c:	803dd940 	call	803dd94 <udp_maxalloc>
+ 8036650:	1007883a 	mov	r3,r2
+ 8036654:	e0bffd17 	ldw	r2,-12(fp)
+ 8036658:	10c01315 	stw	r3,76(r2)
+ 803665c:	e0bffd17 	ldw	r2,-12(fp)
+ 8036660:	10c01317 	ldw	r3,76(r2)
+ 8036664:	e0bffd17 	ldw	r2,-12(fp)
+ 8036668:	10c00b15 	stw	r3,44(r2)
+
+#ifdef IP_V4
+      /* make a NetPort UDP connection */
+      /* unlock the net resource; UDP will immediatly re-lock it */
+      if (so->so_domain  == AF_INET){
+ 803666c:	e0bffd17 	ldw	r2,-12(fp)
+ 8036670:	10800517 	ldw	r2,20(r2)
+ 8036674:	10800098 	cmpnei	r2,r2,2
+ 8036678:	10000f1e 	bne	r2,zero,80366b8 <udp_usrreq+0x100>
+        UNLOCK_NET_RESOURCE(NET_RESID);
+ 803667c:	0009883a 	mov	r4,zero
+ 8036680:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+        udpconn = udp_open(0L, 0, udp_socket(), udp_soinput, so);
+ 8036684:	803dc280 	call	803dc28 <udp_socket>
+ 8036688:	10ffffcc 	andi	r3,r2,65535
+ 803668c:	e0bffd17 	ldw	r2,-12(fp)
+ 8036690:	d8800015 	stw	r2,0(sp)
+ 8036694:	01c200f4 	movhi	r7,2051
+ 8036698:	39d90604 	addi	r7,r7,25624
+ 803669c:	180d883a 	mov	r6,r3
+ 80366a0:	000b883a 	mov	r5,zero
+ 80366a4:	0009883a 	mov	r4,zero
+ 80366a8:	80402540 	call	8040254 <udp_open>
+ 80366ac:	e0bfff15 	stw	r2,-4(fp)
+        LOCK_NET_RESOURCE(NET_RESID);
+ 80366b0:	0009883a 	mov	r4,zero
+ 80366b4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+        UNLOCK_NET_RESOURCE(NET_RESID);
+        udpconn = udp6_open(0L, 0, udp_socket(), udp6_soinput, so);
+        LOCK_NET_RESOURCE(NET_RESID);
+      }
+#endif
+      if (!udpconn)
+ 80366b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80366bc:	1000021e 	bne	r2,zero,80366c8 <udp_usrreq+0x110>
+         return(EINVAL);
+ 80366c0:	00800584 	movi	r2,22
+ 80366c4:	00004506 	br	80367dc <udp_usrreq+0x224>
+      return 0;
+ 80366c8:	0005883a 	mov	r2,zero
+ 80366cc:	00004306 	br	80367dc <udp_usrreq+0x224>
+   case PRU_DETACH:
+      /* delete the NetPort UDP connection */
+      udpconn = udp_lookup(so);
+ 80366d0:	e13ffd17 	ldw	r4,-12(fp)
+ 80366d4:	80363bc0 	call	80363bc <udp_lookup>
+ 80366d8:	e0bfff15 	stw	r2,-4(fp)
+      if (!udpconn)
+ 80366dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80366e0:	1000021e 	bne	r2,zero,80366ec <udp_usrreq+0x134>
+         return(EINVAL);
+ 80366e4:	00800584 	movi	r2,22
+ 80366e8:	00003c06 	br	80367dc <udp_usrreq+0x224>
+      /* unlock the net resource; UDP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 80366ec:	0009883a 	mov	r4,zero
+ 80366f0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      udp_close(udpconn);
+ 80366f4:	e13fff17 	ldw	r4,-4(fp)
+ 80366f8:	80404540 	call	8040454 <udp_close>
+      LOCK_NET_RESOURCE(NET_RESID);
+ 80366fc:	0009883a 	mov	r4,zero
+ 8036700:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      return 0;
+ 8036704:	0005883a 	mov	r2,zero
+ 8036708:	00003406 	br	80367dc <udp_usrreq+0x224>
+   case PRU_CONNECT:
+      /* Install foreign port for UDP, making a virtual connection */
+      /* fall to shared bind logic */
+   case PRU_BIND:
+      /* do bind parameters lookups and tests */
+      if (nam == NULL)
+ 803670c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036710:	1000021e 	bne	r2,zero,803671c <udp_usrreq+0x164>
+         return(EINVAL);
+ 8036714:	00800584 	movi	r2,22
+ 8036718:	00003006 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+ 803671c:	e0bffd17 	ldw	r2,-12(fp)
+ 8036720:	10800517 	ldw	r2,20(r2)
+ 8036724:	10800098 	cmpnei	r2,r2,2
+ 8036728:	1000051e 	bne	r2,zero,8036740 <udp_usrreq+0x188>
+        return udp4_sockbind(so, nam, req );
+ 803672c:	e1bffe17 	ldw	r6,-8(fp)
+ 8036730:	e17ffb17 	ldw	r5,-20(fp)
+ 8036734:	e13ffd17 	ldw	r4,-12(fp)
+ 8036738:	80367f00 	call	80367f0 <udp4_sockbind>
+ 803673c:	00002706 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_sockbind(so, nam, req);
+      }
+#endif
+      dtrap();   /* invalid address */
+ 8036740:	8028cd40 	call	8028cd4 <dtrap>
+      return EINVAL;
+ 8036744:	00800584 	movi	r2,22
+ 8036748:	00002406 	br	80367dc <udp_usrreq+0x224>
+   case PRU_SEND:
+      /* do parameter lookups and tests */
+      if (!m)  /* no data passed? */
+ 803674c:	e0bffc17 	ldw	r2,-16(fp)
+ 8036750:	1000021e 	bne	r2,zero,803675c <udp_usrreq+0x1a4>
+         return(EINVAL);
+ 8036754:	00800584 	movi	r2,22
+ 8036758:	00002006 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+ 803675c:	e0bffd17 	ldw	r2,-12(fp)
+ 8036760:	10800517 	ldw	r2,20(r2)
+ 8036764:	10800098 	cmpnei	r2,r2,2
+ 8036768:	1000051e 	bne	r2,zero,8036780 <udp_usrreq+0x1c8>
+        return udp4_socksend(so, m, nam );
+ 803676c:	e1bffb17 	ldw	r6,-20(fp)
+ 8036770:	e17ffc17 	ldw	r5,-16(fp)
+ 8036774:	e13ffd17 	ldw	r4,-12(fp)
+ 8036778:	8036ac00 	call	8036ac0 <udp4_socksend>
+ 803677c:	00001706 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_socksend(so, m, nam);
+      }
+#endif
+      dtrap();   /* invalid address */
+ 8036780:	8028cd40 	call	8028cd4 <dtrap>
+      return EINVAL;
+ 8036784:	00800584 	movi	r2,22
+ 8036788:	00001406 	br	80367dc <udp_usrreq+0x224>
+
+   case PRU_SOCKADDR:
+      /* fall through to share PRU_PEERADDR prefix */
+   case PRU_PEERADDR:
+      if (nam == NULL)
+ 803678c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036790:	1000021e 	bne	r2,zero,803679c <udp_usrreq+0x1e4>
+         return(EINVAL);
+ 8036794:	00800584 	movi	r2,22
+ 8036798:	00001006 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+ 803679c:	e0bffd17 	ldw	r2,-12(fp)
+ 80367a0:	10800517 	ldw	r2,20(r2)
+ 80367a4:	10800098 	cmpnei	r2,r2,2
+ 80367a8:	1000051e 	bne	r2,zero,80367c0 <udp_usrreq+0x208>
+        return udp4_sockaddr(so, nam, req );
+ 80367ac:	e1bffe17 	ldw	r6,-8(fp)
+ 80367b0:	e17ffb17 	ldw	r5,-20(fp)
+ 80367b4:	e13ffd17 	ldw	r4,-12(fp)
+ 80367b8:	8036e340 	call	8036e34 <udp4_sockaddr>
+ 80367bc:	00000706 	br	80367dc <udp_usrreq+0x224>
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_sockaddr(so, nam, req);
+      }
+#endif
+      dtrap();   /* invalid address */
+ 80367c0:	8028cd40 	call	8028cd4 <dtrap>
+      return EINVAL;
+ 80367c4:	00800584 	movi	r2,22
+ 80367c8:	00000406 	br	80367dc <udp_usrreq+0x224>
+
+   case PRU_DISCONNECT:
+   case PRU_RCVD:
+      dtrap();
+ 80367cc:	8028cd40 	call	8028cd4 <dtrap>
+      return 0;
+ 80367d0:	0005883a 	mov	r2,zero
+ 80367d4:	00000106 	br	80367dc <udp_usrreq+0x224>
+   case PRU_LISTEN:     /* don't support these for UDP */
+   case PRU_ACCEPT:
+   default:
+      return EOPNOTSUPP;
+ 80367d8:	008017c4 	movi	r2,95
+   }
+}
+ 80367dc:	e037883a 	mov	sp,fp
+ 80367e0:	dfc00117 	ldw	ra,4(sp)
+ 80367e4:	df000017 	ldw	fp,0(sp)
+ 80367e8:	dec00204 	addi	sp,sp,8
+ 80367ec:	f800283a 	ret
+
+080367f0 <udp4_sockbind>:
+
+#ifdef IP_V4
+int udp4_sockbind(struct socket *so, struct mbuf *nam, int req ) 
+{
+ 80367f0:	defff304 	addi	sp,sp,-52
+ 80367f4:	dfc00c15 	stw	ra,48(sp)
+ 80367f8:	df000b15 	stw	fp,44(sp)
+ 80367fc:	df000b04 	addi	fp,sp,44
+ 8036800:	e13ff715 	stw	r4,-36(fp)
+ 8036804:	e17ff615 	stw	r5,-40(fp)
+ 8036808:	e1bff515 	stw	r6,-44(fp)
+  u_short  lport;   /* local port (local byte order) */
+  ip_addr fhost; /* host to send to/recv from (network byte order) */
+  ip_addr lhost; /* local IP address to bind to (network byte order) */
+  NET ifp;
+
+  sin = mtod(nam, struct sockaddr_in *);
+ 803680c:	e0bff617 	ldw	r2,-40(fp)
+ 8036810:	10800317 	ldw	r2,12(r2)
+ 8036814:	e0bffa15 	stw	r2,-24(fp)
+  if (sin == NULL)
+ 8036818:	e0bffa17 	ldw	r2,-24(fp)
+ 803681c:	1000021e 	bne	r2,zero,8036828 <udp4_sockbind+0x38>
+    return(EINVAL);
+ 8036820:	00800584 	movi	r2,22
+ 8036824:	0000a106 	br	8036aac <udp4_sockbind+0x2bc>
+  if (nam->m_len != sizeof (*sin))
+ 8036828:	e0bff617 	ldw	r2,-40(fp)
+ 803682c:	10800217 	ldw	r2,8(r2)
+ 8036830:	10800420 	cmpeqi	r2,r2,16
+ 8036834:	1000021e 	bne	r2,zero,8036840 <udp4_sockbind+0x50>
+    return(EINVAL);
+ 8036838:	00800584 	movi	r2,22
+ 803683c:	00009b06 	br	8036aac <udp4_sockbind+0x2bc>
+  udpconn = udp_lookup(so);
+ 8036840:	e13ff717 	ldw	r4,-36(fp)
+ 8036844:	80363bc0 	call	80363bc <udp_lookup>
+ 8036848:	e0bff915 	stw	r2,-28(fp)
+  if (!udpconn)
+ 803684c:	e0bff917 	ldw	r2,-28(fp)
+ 8036850:	1000021e 	bne	r2,zero,803685c <udp4_sockbind+0x6c>
+     return(EINVAL);
+ 8036854:	00800584 	movi	r2,22
+ 8036858:	00009406 	br	8036aac <udp4_sockbind+0x2bc>
+  if (req == PRU_BIND)
+ 803685c:	e0bff517 	ldw	r2,-44(fp)
+ 8036860:	10800098 	cmpnei	r2,r2,2
+ 8036864:	1000521e 	bne	r2,zero,80369b0 <udp4_sockbind+0x1c0>
+     * if the caller-supplied port is 0, try to get
+     * the port from the UDP endpoint, or pick a new
+     * unique port; else, use the caller-supplied
+     * port
+     */
+    if (sin->sin_port == 0)
+ 8036868:	e0bffa17 	ldw	r2,-24(fp)
+ 803686c:	1080008b 	ldhu	r2,2(r2)
+ 8036870:	10bfffcc 	andi	r2,r2,65535
+ 8036874:	10000b1e 	bne	r2,zero,80368a4 <udp4_sockbind+0xb4>
+    {
+      if (udpconn->u_lport != 0)
+ 8036878:	e0bff917 	ldw	r2,-28(fp)
+ 803687c:	1080018b 	ldhu	r2,6(r2)
+ 8036880:	10bfffcc 	andi	r2,r2,65535
+ 8036884:	10000426 	beq	r2,zero,8036898 <udp4_sockbind+0xa8>
+        lport = udpconn->u_lport;
+ 8036888:	e0bff917 	ldw	r2,-28(fp)
+ 803688c:	1080018b 	ldhu	r2,6(r2)
+ 8036890:	e0bffe8d 	sth	r2,-6(fp)
+ 8036894:	00000e06 	br	80368d0 <udp4_sockbind+0xe0>
+      else
+        lport = udp_socket();
+ 8036898:	803dc280 	call	803dc28 <udp_socket>
+ 803689c:	e0bffe8d 	sth	r2,-6(fp)
+ 80368a0:	00000b06 	br	80368d0 <udp4_sockbind+0xe0>
+    }
+    else
+    {
+      lport = ntohs(sin->sin_port);
+ 80368a4:	e0bffa17 	ldw	r2,-24(fp)
+ 80368a8:	1080008b 	ldhu	r2,2(r2)
+ 80368ac:	10bfffcc 	andi	r2,r2,65535
+ 80368b0:	1004d23a 	srli	r2,r2,8
+ 80368b4:	1007883a 	mov	r3,r2
+ 80368b8:	e0bffa17 	ldw	r2,-24(fp)
+ 80368bc:	1080008b 	ldhu	r2,2(r2)
+ 80368c0:	10bfffcc 	andi	r2,r2,65535
+ 80368c4:	1004923a 	slli	r2,r2,8
+ 80368c8:	1884b03a 	or	r2,r3,r2
+ 80368cc:	e0bffe8d 	sth	r2,-6(fp)
+    /* if the caller-supplied address is INADDR_ANY,
+     * don't bind to a specific address; else, 
+     * make sure the caller-supplied address is
+     * an interface IP address and if so, bind to that
+     */
+    if (sin->sin_addr.s_addr == INADDR_ANY)
+ 80368d0:	e0bffa17 	ldw	r2,-24(fp)
+ 80368d4:	10800117 	ldw	r2,4(r2)
+ 80368d8:	1000021e 	bne	r2,zero,80368e4 <udp4_sockbind+0xf4>
+    {
+      lhost = 0L;
+ 80368dc:	e03ffc15 	stw	zero,-16(fp)
+ 80368e0:	00001606 	br	803693c <udp4_sockbind+0x14c>
+    }
+    else
+    {
+      lhost = sin->sin_addr.s_addr;
+ 80368e4:	e0bffa17 	ldw	r2,-24(fp)
+ 80368e8:	10800117 	ldw	r2,4(r2)
+ 80368ec:	e0bffc15 	stw	r2,-16(fp)
+#ifndef UDP_SKIP_LCL_ADDR_CHECK
+      /* verify that lhost is a local interface address */
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 80368f0:	008201b4 	movhi	r2,2054
+ 80368f4:	10b6a617 	ldw	r2,-9576(r2)
+ 80368f8:	e0bffb15 	stw	r2,-20(fp)
+ 80368fc:	00000706 	br	803691c <udp4_sockbind+0x12c>
+        if (ifp->n_ipaddr == lhost)
+ 8036900:	e0bffb17 	ldw	r2,-20(fp)
+ 8036904:	10800a17 	ldw	r2,40(r2)
+ 8036908:	e0fffc17 	ldw	r3,-16(fp)
+ 803690c:	18800626 	beq	r3,r2,8036928 <udp4_sockbind+0x138>
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036910:	e0bffb17 	ldw	r2,-20(fp)
+ 8036914:	10800017 	ldw	r2,0(r2)
+ 8036918:	e0bffb15 	stw	r2,-20(fp)
+ 803691c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036920:	103ff71e 	bne	r2,zero,8036900 <udp4_sockbind+0x110>
+ 8036924:	00000106 	br	803692c <udp4_sockbind+0x13c>
+          break;
+ 8036928:	0001883a 	nop
+      if (ifp == NULL)
+ 803692c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036930:	1000021e 	bne	r2,zero,803693c <udp4_sockbind+0x14c>
+        return(EADDRNOTAVAIL);
+ 8036934:	00801f44 	movi	r2,125
+ 8036938:	00005c06 	br	8036aac <udp4_sockbind+0x2bc>
+    }
+
+    /* make sure we're not about to collide with an
+     * existing binding
+     */
+    if (!(so->so_options & SO_REUSEADDR))
+ 803693c:	e0bff717 	ldw	r2,-36(fp)
+ 8036940:	10800417 	ldw	r2,16(r2)
+ 8036944:	1080010c 	andi	r2,r2,4
+ 8036948:	1000121e 	bne	r2,zero,8036994 <udp4_sockbind+0x1a4>
+      for (udptmp = firstudp; udptmp; udptmp = udptmp->u_next)
+ 803694c:	d0a09e17 	ldw	r2,-32136(gp)
+ 8036950:	e0bfff15 	stw	r2,-4(fp)
+ 8036954:	00000d06 	br	803698c <udp4_sockbind+0x19c>
+        if ((udptmp->u_lport == lport) && (udptmp != udpconn))
+ 8036958:	e0bfff17 	ldw	r2,-4(fp)
+ 803695c:	1080018b 	ldhu	r2,6(r2)
+ 8036960:	e0fffe8b 	ldhu	r3,-6(fp)
+ 8036964:	10bfffcc 	andi	r2,r2,65535
+ 8036968:	1880051e 	bne	r3,r2,8036980 <udp4_sockbind+0x190>
+ 803696c:	e0ffff17 	ldw	r3,-4(fp)
+ 8036970:	e0bff917 	ldw	r2,-28(fp)
+ 8036974:	18800226 	beq	r3,r2,8036980 <udp4_sockbind+0x190>
+          return(EADDRINUSE);
+ 8036978:	00801c04 	movi	r2,112
+ 803697c:	00004b06 	br	8036aac <udp4_sockbind+0x2bc>
+      for (udptmp = firstudp; udptmp; udptmp = udptmp->u_next)
+ 8036980:	e0bfff17 	ldw	r2,-4(fp)
+ 8036984:	10800017 	ldw	r2,0(r2)
+ 8036988:	e0bfff15 	stw	r2,-4(fp)
+ 803698c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036990:	103ff11e 	bne	r2,zero,8036958 <udp4_sockbind+0x168>
+    /* bind the UDP endpoint */
+    udpconn->u_lport = lport;
+ 8036994:	e0bff917 	ldw	r2,-28(fp)
+ 8036998:	e0fffe8b 	ldhu	r3,-6(fp)
+ 803699c:	10c0018d 	sth	r3,6(r2)
+    udpconn->u_lhost = lhost;
+ 80369a0:	e0bff917 	ldw	r2,-28(fp)
+ 80369a4:	e0fffc17 	ldw	r3,-16(fp)
+ 80369a8:	10c00315 	stw	r3,12(r2)
+ 80369ac:	00003e06 	br	8036aa8 <udp4_sockbind+0x2b8>
+  else /* PRU_CONNECT */
+  {
+    /* connect the socket to a remote IP address and
+     * UDP port.
+     */
+    fport = ntohs(sin->sin_port);
+ 80369b0:	e0bffa17 	ldw	r2,-24(fp)
+ 80369b4:	1080008b 	ldhu	r2,2(r2)
+ 80369b8:	10bfffcc 	andi	r2,r2,65535
+ 80369bc:	1004d23a 	srli	r2,r2,8
+ 80369c0:	1007883a 	mov	r3,r2
+ 80369c4:	e0bffa17 	ldw	r2,-24(fp)
+ 80369c8:	1080008b 	ldhu	r2,2(r2)
+ 80369cc:	10bfffcc 	andi	r2,r2,65535
+ 80369d0:	1004923a 	slli	r2,r2,8
+ 80369d4:	1884b03a 	or	r2,r3,r2
+ 80369d8:	e0bff88d 	sth	r2,-30(fp)
+    /* if the caller-supplied address is INADDR_ANY,
+     * use the wildcard address; else, use the caller-
+     * supplied address
+     */
+    if (sin->sin_addr.s_addr == INADDR_ANY)
+ 80369dc:	e0bffa17 	ldw	r2,-24(fp)
+ 80369e0:	10800117 	ldw	r2,4(r2)
+ 80369e4:	1000021e 	bne	r2,zero,80369f0 <udp4_sockbind+0x200>
+      fhost = 0L;
+ 80369e8:	e03ffd15 	stw	zero,-12(fp)
+ 80369ec:	00000306 	br	80369fc <udp4_sockbind+0x20c>
+    else
+      fhost = sin->sin_addr.s_addr;
+ 80369f0:	e0bffa17 	ldw	r2,-24(fp)
+ 80369f4:	10800117 	ldw	r2,4(r2)
+ 80369f8:	e0bffd15 	stw	r2,-12(fp)
+    /* prepare to bind the socket to the appropriate 
+     * local interface address for the to-be-connected 
+     * peer
+     */
+    lhost = ip_mymach(fhost);
+ 80369fc:	e13ffd17 	ldw	r4,-12(fp)
+ 8036a00:	803b0280 	call	803b028 <ip_mymach>
+ 8036a04:	e0bffc15 	stw	r2,-16(fp)
+    if (lhost == 0)
+ 8036a08:	e0bffc17 	ldw	r2,-16(fp)
+ 8036a0c:	1000021e 	bne	r2,zero,8036a18 <udp4_sockbind+0x228>
+      return(ENETUNREACH);
+ 8036a10:	00801c84 	movi	r2,114
+ 8036a14:	00002506 	br	8036aac <udp4_sockbind+0x2bc>
+    /* if the socket hasn't been bound to a local
+     * port yet, do so now
+     */
+    lport = udpconn->u_lport;
+ 8036a18:	e0bff917 	ldw	r2,-28(fp)
+ 8036a1c:	1080018b 	ldhu	r2,6(r2)
+ 8036a20:	e0bffe8d 	sth	r2,-6(fp)
+    if (lport == 0)
+ 8036a24:	e0bffe8b 	ldhu	r2,-6(fp)
+ 8036a28:	1000021e 	bne	r2,zero,8036a34 <udp4_sockbind+0x244>
+      lport = udp_socket();
+ 8036a2c:	803dc280 	call	803dc28 <udp_socket>
+ 8036a30:	e0bffe8d 	sth	r2,-6(fp)
+    /* bind and connect the UDP endpoint */
+    udpconn->u_lhost = lhost;
+ 8036a34:	e0bff917 	ldw	r2,-28(fp)
+ 8036a38:	e0fffc17 	ldw	r3,-16(fp)
+ 8036a3c:	10c00315 	stw	r3,12(r2)
+    udpconn->u_lport = lport;
+ 8036a40:	e0bff917 	ldw	r2,-28(fp)
+ 8036a44:	e0fffe8b 	ldhu	r3,-6(fp)
+ 8036a48:	10c0018d 	sth	r3,6(r2)
+    udpconn->u_fhost = fhost;
+ 8036a4c:	e0bff917 	ldw	r2,-28(fp)
+ 8036a50:	e0fffd17 	ldw	r3,-12(fp)
+ 8036a54:	10c00415 	stw	r3,16(r2)
+    udpconn->u_fport = fport;
+ 8036a58:	e0bff917 	ldw	r2,-28(fp)
+ 8036a5c:	e0fff88b 	ldhu	r3,-30(fp)
+ 8036a60:	10c0020d 	sth	r3,8(r2)
+    /* mark the socket as connected */
+    so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+ 8036a64:	e0bff717 	ldw	r2,-36(fp)
+ 8036a68:	10c0088b 	ldhu	r3,34(r2)
+ 8036a6c:	00bffcc4 	movi	r2,-13
+ 8036a70:	1884703a 	and	r2,r3,r2
+ 8036a74:	1007883a 	mov	r3,r2
+ 8036a78:	e0bff717 	ldw	r2,-36(fp)
+ 8036a7c:	10c0088d 	sth	r3,34(r2)
+    so->so_state |= SS_ISCONNECTED;
+ 8036a80:	e0bff717 	ldw	r2,-36(fp)
+ 8036a84:	1080088b 	ldhu	r2,34(r2)
+ 8036a88:	10800094 	ori	r2,r2,2
+ 8036a8c:	1007883a 	mov	r3,r2
+ 8036a90:	e0bff717 	ldw	r2,-36(fp)
+ 8036a94:	10c0088d 	sth	r3,34(r2)
+    /* since socket was in listen state, packets may be queued */
+    sbflush(&so->so_rcv);   /* dump these now */
+ 8036a98:	e0bff717 	ldw	r2,-36(fp)
+ 8036a9c:	10800a04 	addi	r2,r2,40
+ 8036aa0:	1009883a 	mov	r4,r2
+ 8036aa4:	803002c0 	call	803002c <sbflush>
+  }
+  return 0;
+ 8036aa8:	0005883a 	mov	r2,zero
+}
+ 8036aac:	e037883a 	mov	sp,fp
+ 8036ab0:	dfc00117 	ldw	ra,4(sp)
+ 8036ab4:	df000017 	ldw	fp,0(sp)
+ 8036ab8:	dec00204 	addi	sp,sp,8
+ 8036abc:	f800283a 	ret
+
+08036ac0 <udp4_socksend>:
+
+int udp4_socksend(struct socket *so, struct mbuf *m, 
+		struct mbuf *nam ) 
+{
+ 8036ac0:	defff304 	addi	sp,sp,-52
+ 8036ac4:	dfc00c15 	stw	ra,48(sp)
+ 8036ac8:	df000b15 	stw	fp,44(sp)
+ 8036acc:	dc000a15 	stw	r16,40(sp)
+ 8036ad0:	df000b04 	addi	fp,sp,44
+ 8036ad4:	e13ff715 	stw	r4,-36(fp)
+ 8036ad8:	e17ff615 	stw	r5,-40(fp)
+ 8036adc:	e1bff515 	stw	r6,-44(fp)
+  PACKET pkt;
+#ifdef MULTI_HOMED
+  NET ifp;
+#endif
+
+  udpconn = udp_lookup(so);
+ 8036ae0:	e13ff717 	ldw	r4,-36(fp)
+ 8036ae4:	80363bc0 	call	80363bc <udp_lookup>
+ 8036ae8:	e0bffb15 	stw	r2,-20(fp)
+  if (!udpconn)
+ 8036aec:	e0bffb17 	ldw	r2,-20(fp)
+ 8036af0:	1000041e 	bne	r2,zero,8036b04 <udp4_socksend+0x44>
+  {
+    m_free(m);
+ 8036af4:	e13ff617 	ldw	r4,-40(fp)
+ 8036af8:	8029bf80 	call	8029bf8 <m_free>
+    /* may be bogus socket, but more likely the connection may 
+       have closed due to ICMP dest unreachable from other side. */
+    return(ECONNREFUSED);
+ 8036afc:	00801bc4 	movi	r2,111
+ 8036b00:	0000c606 	br	8036e1c <udp4_socksend+0x35c>
+  }
+
+  if (nam == NULL)  /* no sendto() info passed, must be send() */
+ 8036b04:	e0bff517 	ldw	r2,-44(fp)
+ 8036b08:	10000e1e 	bne	r2,zero,8036b44 <udp4_socksend+0x84>
+  { 
+    if (so->so_state & SS_ISCONNECTED)
+ 8036b0c:	e0bff717 	ldw	r2,-36(fp)
+ 8036b10:	1080088b 	ldhu	r2,34(r2)
+ 8036b14:	10bfffcc 	andi	r2,r2,65535
+ 8036b18:	1080008c 	andi	r2,r2,2
+ 8036b1c:	10000726 	beq	r2,zero,8036b3c <udp4_socksend+0x7c>
+    {
+      fport = udpconn->u_fport;
+ 8036b20:	e0bffb17 	ldw	r2,-20(fp)
+ 8036b24:	1080020b 	ldhu	r2,8(r2)
+ 8036b28:	e0bffe8d 	sth	r2,-6(fp)
+      fhost = udpconn->u_fhost;
+ 8036b2c:	e0bffb17 	ldw	r2,-20(fp)
+ 8036b30:	10800417 	ldw	r2,16(r2)
+ 8036b34:	e0bffd15 	stw	r2,-12(fp)
+ 8036b38:	00002806 	br	8036bdc <udp4_socksend+0x11c>
+    }
+    else
+      return (EINVAL);
+ 8036b3c:	00800584 	movi	r2,22
+ 8036b40:	0000b606 	br	8036e1c <udp4_socksend+0x35c>
+  }
+  else if(nam->m_len != sizeof (*sin))
+ 8036b44:	e0bff517 	ldw	r2,-44(fp)
+ 8036b48:	10800217 	ldw	r2,8(r2)
+ 8036b4c:	10800420 	cmpeqi	r2,r2,16
+ 8036b50:	1000031e 	bne	r2,zero,8036b60 <udp4_socksend+0xa0>
+  {
+    dtrap();
+ 8036b54:	8028cd40 	call	8028cd4 <dtrap>
+    return (EINVAL);
+ 8036b58:	00800584 	movi	r2,22
+ 8036b5c:	0000af06 	br	8036e1c <udp4_socksend+0x35c>
+  }
+  else
+  {
+    sin = mtod(nam, struct sockaddr_in *);
+ 8036b60:	e0bff517 	ldw	r2,-44(fp)
+ 8036b64:	10800317 	ldw	r2,12(r2)
+ 8036b68:	e0bffa15 	stw	r2,-24(fp)
+    fhost = sin->sin_addr.s_addr;
+ 8036b6c:	e0bffa17 	ldw	r2,-24(fp)
+ 8036b70:	10800117 	ldw	r2,4(r2)
+ 8036b74:	e0bffd15 	stw	r2,-12(fp)
+    /* use caller's fport if specified, ours may be a wildcard */
+    if (sin->sin_port)   /* caller gets to change fport on the fly */
+ 8036b78:	e0bffa17 	ldw	r2,-24(fp)
+ 8036b7c:	1080008b 	ldhu	r2,2(r2)
+ 8036b80:	10bfffcc 	andi	r2,r2,65535
+ 8036b84:	10000c26 	beq	r2,zero,8036bb8 <udp4_socksend+0xf8>
+      fport = ntohs(sin->sin_port);
+ 8036b88:	e0bffa17 	ldw	r2,-24(fp)
+ 8036b8c:	1080008b 	ldhu	r2,2(r2)
+ 8036b90:	10bfffcc 	andi	r2,r2,65535
+ 8036b94:	1004d23a 	srli	r2,r2,8
+ 8036b98:	1007883a 	mov	r3,r2
+ 8036b9c:	e0bffa17 	ldw	r2,-24(fp)
+ 8036ba0:	1080008b 	ldhu	r2,2(r2)
+ 8036ba4:	10bfffcc 	andi	r2,r2,65535
+ 8036ba8:	1004923a 	slli	r2,r2,8
+ 8036bac:	1884b03a 	or	r2,r3,r2
+ 8036bb0:	e0bffe8d 	sth	r2,-6(fp)
+ 8036bb4:	00000906 	br	8036bdc <udp4_socksend+0x11c>
+    else  /* use port already set in UDP connection */
+    {
+      if (udpconn->u_fport == 0) /* don't send to port 0 */
+ 8036bb8:	e0bffb17 	ldw	r2,-20(fp)
+ 8036bbc:	1080020b 	ldhu	r2,8(r2)
+ 8036bc0:	10bfffcc 	andi	r2,r2,65535
+ 8036bc4:	1000021e 	bne	r2,zero,8036bd0 <udp4_socksend+0x110>
+        return (EINVAL);
+ 8036bc8:	00800584 	movi	r2,22
+ 8036bcc:	00009306 	br	8036e1c <udp4_socksend+0x35c>
+      fport = udpconn->u_fport;
+ 8036bd0:	e0bffb17 	ldw	r2,-20(fp)
+ 8036bd4:	1080020b 	ldhu	r2,8(r2)
+ 8036bd8:	e0bffe8d 	sth	r2,-6(fp)
+
+  /* since our pkt->nb_buff size is tied to max packet size, we 
+   * assume our UDP datagrams are always in one mbuf and that the 
+   * mbuf 
+   */
+  if (m->m_len > (unsigned)udp_maxalloc()) /* but check anyway:*/
+ 8036bdc:	e0bff617 	ldw	r2,-40(fp)
+ 8036be0:	14000217 	ldw	r16,8(r2)
+ 8036be4:	803dd940 	call	803dd94 <udp_maxalloc>
+ 8036be8:	1400032e 	bgeu	r2,r16,8036bf8 <udp4_socksend+0x138>
+  {
+    dtrap(); /* should never happen */
+ 8036bec:	8028cd40 	call	8028cd4 <dtrap>
+    return EMSGSIZE;  /* try to recover */
+ 8036bf0:	00801e84 	movi	r2,122
+ 8036bf4:	00008906 	br	8036e1c <udp4_socksend+0x35c>
+  }
+  pkt = udp_alloc(m->m_len, 0);    /* get a NetPort buffer for send */
+ 8036bf8:	e0bff617 	ldw	r2,-40(fp)
+ 8036bfc:	10800217 	ldw	r2,8(r2)
+ 8036c00:	000b883a 	mov	r5,zero
+ 8036c04:	1009883a 	mov	r4,r2
+ 8036c08:	803dcd80 	call	803dcd8 <udp_alloc>
+ 8036c0c:	e0bff915 	stw	r2,-28(fp)
+  if (!pkt)
+ 8036c10:	e0bff917 	ldw	r2,-28(fp)
+ 8036c14:	1000041e 	bne	r2,zero,8036c28 <udp4_socksend+0x168>
+  {
+    m_free(m);
+ 8036c18:	e13ff617 	ldw	r4,-40(fp)
+ 8036c1c:	8029bf80 	call	8029bf8 <m_free>
+    return ENOBUFS;   /* report buffer shortages */
+ 8036c20:	00801a44 	movi	r2,105
+ 8036c24:	00007d06 	br	8036e1c <udp4_socksend+0x35c>
+  }
+  MEMCPY(pkt->nb_prot, m->m_data, m->m_len);
+ 8036c28:	e0bff917 	ldw	r2,-28(fp)
+ 8036c2c:	10c00317 	ldw	r3,12(r2)
+ 8036c30:	e0bff617 	ldw	r2,-40(fp)
+ 8036c34:	11000317 	ldw	r4,12(r2)
+ 8036c38:	e0bff617 	ldw	r2,-40(fp)
+ 8036c3c:	10800217 	ldw	r2,8(r2)
+ 8036c40:	100d883a 	mov	r6,r2
+ 8036c44:	200b883a 	mov	r5,r4
+ 8036c48:	1809883a 	mov	r4,r3
+ 8036c4c:	80086b80 	call	80086b8 <memcpy>
+  pkt->nb_plen = m->m_len;
+ 8036c50:	e0bff617 	ldw	r2,-40(fp)
+ 8036c54:	10c00217 	ldw	r3,8(r2)
+ 8036c58:	e0bff917 	ldw	r2,-28(fp)
+ 8036c5c:	10c00415 	stw	r3,16(r2)
+  /* finished with mbuf, free it now */
+  m_free(m);
+ 8036c60:	e13ff617 	ldw	r4,-40(fp)
+ 8036c64:	8029bf80 	call	8029bf8 <m_free>
+  pkt->fhost = fhost;
+ 8036c68:	e0bff917 	ldw	r2,-28(fp)
+ 8036c6c:	e0fffd17 	ldw	r3,-12(fp)
+ 8036c70:	10c00715 	stw	r3,28(r2)
+     * is up; if (after all that) we don't have an interface then we
+     * fail with error EADDRNOTAVAIL; and finally, if we're built
+     * for a single-homed configuration where there's only one
+     * interface, we might as well use it, so we do.  
+   */
+  if (fhost == 0xffffffff)
+ 8036c74:	e0bffd17 	ldw	r2,-12(fp)
+ 8036c78:	10bfffd8 	cmpnei	r2,r2,-1
+ 8036c7c:	1000471e 	bne	r2,zero,8036d9c <udp4_socksend+0x2dc>
+  {
+#ifdef MULTI_HOMED
+    if (udpconn->u_lhost != 0L)
+ 8036c80:	e0bffb17 	ldw	r2,-20(fp)
+ 8036c84:	10800317 	ldw	r2,12(r2)
+ 8036c88:	10000f26 	beq	r2,zero,8036cc8 <udp4_socksend+0x208>
+    {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036c8c:	008201b4 	movhi	r2,2054
+ 8036c90:	10b6a617 	ldw	r2,-9576(r2)
+ 8036c94:	e0bffc15 	stw	r2,-16(fp)
+ 8036c98:	00000806 	br	8036cbc <udp4_socksend+0x1fc>
+        if (ifp->n_ipaddr == udpconn->u_lhost)
+ 8036c9c:	e0bffc17 	ldw	r2,-16(fp)
+ 8036ca0:	10c00a17 	ldw	r3,40(r2)
+ 8036ca4:	e0bffb17 	ldw	r2,-20(fp)
+ 8036ca8:	10800317 	ldw	r2,12(r2)
+ 8036cac:	18801c26 	beq	r3,r2,8036d20 <udp4_socksend+0x260>
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036cb0:	e0bffc17 	ldw	r2,-16(fp)
+ 8036cb4:	10800017 	ldw	r2,0(r2)
+ 8036cb8:	e0bffc15 	stw	r2,-16(fp)
+ 8036cbc:	e0bffc17 	ldw	r2,-16(fp)
+ 8036cc0:	103ff61e 	bne	r2,zero,8036c9c <udp4_socksend+0x1dc>
+ 8036cc4:	00001906 	br	8036d2c <udp4_socksend+0x26c>
+          break;
+    }
+    else {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036cc8:	008201b4 	movhi	r2,2054
+ 8036ccc:	10b6a617 	ldw	r2,-9576(r2)
+ 8036cd0:	e0bffc15 	stw	r2,-16(fp)
+ 8036cd4:	00000f06 	br	8036d14 <udp4_socksend+0x254>
+        if ((ifp->n_flags & NF_BCAST) &&
+ 8036cd8:	e0bffc17 	ldw	r2,-16(fp)
+ 8036cdc:	10802a17 	ldw	r2,168(r2)
+ 8036ce0:	1080004c 	andi	r2,r2,1
+ 8036ce4:	10000826 	beq	r2,zero,8036d08 <udp4_socksend+0x248>
+          (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 8036ce8:	e0bffc17 	ldw	r2,-16(fp)
+ 8036cec:	10802717 	ldw	r2,156(r2)
+        if ((ifp->n_flags & NF_BCAST) &&
+ 8036cf0:	10000526 	beq	r2,zero,8036d08 <udp4_socksend+0x248>
+          (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 8036cf4:	e0bffc17 	ldw	r2,-16(fp)
+ 8036cf8:	10802717 	ldw	r2,156(r2)
+ 8036cfc:	10800617 	ldw	r2,24(r2)
+ 8036d00:	10800058 	cmpnei	r2,r2,1
+ 8036d04:	10000826 	beq	r2,zero,8036d28 <udp4_socksend+0x268>
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036d08:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d0c:	10800017 	ldw	r2,0(r2)
+ 8036d10:	e0bffc15 	stw	r2,-16(fp)
+ 8036d14:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d18:	103fef1e 	bne	r2,zero,8036cd8 <udp4_socksend+0x218>
+ 8036d1c:	00000306 	br	8036d2c <udp4_socksend+0x26c>
+          break;
+ 8036d20:	0001883a 	nop
+ 8036d24:	00000106 	br	8036d2c <udp4_socksend+0x26c>
+           break;
+ 8036d28:	0001883a 	nop
+    }
+    if (ifp == NULL)
+ 8036d2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d30:	1000171e 	bne	r2,zero,8036d90 <udp4_socksend+0x2d0>
+    {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036d34:	008201b4 	movhi	r2,2054
+ 8036d38:	10b6a617 	ldw	r2,-9576(r2)
+ 8036d3c:	e0bffc15 	stw	r2,-16(fp)
+ 8036d40:	00000b06 	br	8036d70 <udp4_socksend+0x2b0>
+        if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+ 8036d44:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d48:	10802717 	ldw	r2,156(r2)
+ 8036d4c:	10000526 	beq	r2,zero,8036d64 <udp4_socksend+0x2a4>
+ 8036d50:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d54:	10802717 	ldw	r2,156(r2)
+ 8036d58:	10800617 	ldw	r2,24(r2)
+ 8036d5c:	10800058 	cmpnei	r2,r2,1
+ 8036d60:	10000626 	beq	r2,zero,8036d7c <udp4_socksend+0x2bc>
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+ 8036d64:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d68:	10800017 	ldw	r2,0(r2)
+ 8036d6c:	e0bffc15 	stw	r2,-16(fp)
+ 8036d70:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d74:	103ff31e 	bne	r2,zero,8036d44 <udp4_socksend+0x284>
+ 8036d78:	00000106 	br	8036d80 <udp4_socksend+0x2c0>
+          break;
+ 8036d7c:	0001883a 	nop
+      if (ifp == NULL)
+ 8036d80:	e0bffc17 	ldw	r2,-16(fp)
+ 8036d84:	1000021e 	bne	r2,zero,8036d90 <udp4_socksend+0x2d0>
+        return(EADDRNOTAVAIL);
+ 8036d88:	00801f44 	movi	r2,125
+ 8036d8c:	00002306 	br	8036e1c <udp4_socksend+0x35c>
+    }
+    pkt->net = ifp;
+ 8036d90:	e0bff917 	ldw	r2,-28(fp)
+ 8036d94:	e0fffc17 	ldw	r3,-16(fp)
+ 8036d98:	10c00615 	stw	r3,24(r2)
+#ifdef IP_MULTICAST
+
+  /* If the socket has an IP moptions structure for multicast options,
+   * place a pointer to this structure in the PACKET structure.
+   */
+  if (so->inp_moptions)
+ 8036d9c:	e0bff717 	ldw	r2,-36(fp)
+ 8036da0:	10800317 	ldw	r2,12(r2)
+ 8036da4:	10000426 	beq	r2,zero,8036db8 <udp4_socksend+0x2f8>
+     pkt->imo = so->inp_moptions;
+ 8036da8:	e0bff717 	ldw	r2,-36(fp)
+ 8036dac:	10c00317 	ldw	r3,12(r2)
+ 8036db0:	e0bff917 	ldw	r2,-28(fp)
+ 8036db4:	10c00b15 	stw	r3,44(r2)
+
+#endif   /* IP_MULTICAST */
+
+   /* have we set options? */
+   if (so->so_optsPack)
+ 8036db8:	e0bff717 	ldw	r2,-36(fp)
+ 8036dbc:	10801f17 	ldw	r2,124(r2)
+ 8036dc0:	10000426 	beq	r2,zero,8036dd4 <udp4_socksend+0x314>
+	   pkt->soxopts = so->so_optsPack; /* yup - copy to pkt */
+ 8036dc4:	e0bff717 	ldw	r2,-36(fp)
+ 8036dc8:	10c01f17 	ldw	r3,124(r2)
+ 8036dcc:	e0bff917 	ldw	r2,-28(fp)
+ 8036dd0:	10c00c15 	stw	r3,48(r2)
+
+  /* unlock the net resource; UDP will immediately re-lock it */
+  UNLOCK_NET_RESOURCE(NET_RESID);
+ 8036dd4:	0009883a 	mov	r4,zero
+ 8036dd8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+  e = udp_send(fport, udpconn->u_lport, pkt);
+ 8036ddc:	e0fffe8b 	ldhu	r3,-6(fp)
+ 8036de0:	e0bffb17 	ldw	r2,-20(fp)
+ 8036de4:	1080018b 	ldhu	r2,6(r2)
+ 8036de8:	10bfffcc 	andi	r2,r2,65535
+ 8036dec:	e1bff917 	ldw	r6,-28(fp)
+ 8036df0:	100b883a 	mov	r5,r2
+ 8036df4:	1809883a 	mov	r4,r3
+ 8036df8:	803d8a00 	call	803d8a0 <udp_send>
+ 8036dfc:	e0bff815 	stw	r2,-32(fp)
+  LOCK_NET_RESOURCE(NET_RESID);
+ 8036e00:	0009883a 	mov	r4,zero
+ 8036e04:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+  if (e < 0) 
+ 8036e08:	e0bff817 	ldw	r2,-32(fp)
+ 8036e0c:	1000020e 	bge	r2,zero,8036e18 <udp4_socksend+0x358>
+     return(e);
+ 8036e10:	e0bff817 	ldw	r2,-32(fp)
+ 8036e14:	00000106 	br	8036e1c <udp4_socksend+0x35c>
+  return 0;
+ 8036e18:	0005883a 	mov	r2,zero
+}
+ 8036e1c:	e6ffff04 	addi	sp,fp,-4
+ 8036e20:	dfc00217 	ldw	ra,8(sp)
+ 8036e24:	df000117 	ldw	fp,4(sp)
+ 8036e28:	dc000017 	ldw	r16,0(sp)
+ 8036e2c:	dec00304 	addi	sp,sp,12
+ 8036e30:	f800283a 	ret
+
+08036e34 <udp4_sockaddr>:
+
+int udp4_sockaddr(struct socket *so, struct mbuf *nam , int req)
+{
+ 8036e34:	defff904 	addi	sp,sp,-28
+ 8036e38:	dfc00615 	stw	ra,24(sp)
+ 8036e3c:	df000515 	stw	fp,20(sp)
+ 8036e40:	df000504 	addi	fp,sp,20
+ 8036e44:	e13ffd15 	stw	r4,-12(fp)
+ 8036e48:	e17ffc15 	stw	r5,-16(fp)
+ 8036e4c:	e1bffb15 	stw	r6,-20(fp)
+  struct sockaddr_in * sin;
+  UDPCONN udpconn;
+
+  sin = mtod(nam, struct sockaddr_in *);
+ 8036e50:	e0bffc17 	ldw	r2,-16(fp)
+ 8036e54:	10800317 	ldw	r2,12(r2)
+ 8036e58:	e0bfff15 	stw	r2,-4(fp)
+  if (sin == NULL)
+ 8036e5c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036e60:	1000021e 	bne	r2,zero,8036e6c <udp4_sockaddr+0x38>
+     return(EINVAL);
+ 8036e64:	00800584 	movi	r2,22
+ 8036e68:	00003706 	br	8036f48 <udp4_sockaddr+0x114>
+  udpconn = udp_lookup(so);
+ 8036e6c:	e13ffd17 	ldw	r4,-12(fp)
+ 8036e70:	80363bc0 	call	80363bc <udp_lookup>
+ 8036e74:	e0bffe15 	stw	r2,-8(fp)
+  if (!udpconn)
+ 8036e78:	e0bffe17 	ldw	r2,-8(fp)
+ 8036e7c:	1000021e 	bne	r2,zero,8036e88 <udp4_sockaddr+0x54>
+     return(EINVAL);
+ 8036e80:	00800584 	movi	r2,22
+ 8036e84:	00003006 	br	8036f48 <udp4_sockaddr+0x114>
+  nam->m_len = sizeof(*sin);
+ 8036e88:	e0bffc17 	ldw	r2,-16(fp)
+ 8036e8c:	00c00404 	movi	r3,16
+ 8036e90:	10c00215 	stw	r3,8(r2)
+  if (req == PRU_SOCKADDR)
+ 8036e94:	e0bffb17 	ldw	r2,-20(fp)
+ 8036e98:	108003d8 	cmpnei	r2,r2,15
+ 8036e9c:	1000151e 	bne	r2,zero,8036ef4 <udp4_sockaddr+0xc0>
+  {
+     sin->sin_family = AF_INET;
+ 8036ea0:	e0bfff17 	ldw	r2,-4(fp)
+ 8036ea4:	00c00084 	movi	r3,2
+ 8036ea8:	10c0000d 	sth	r3,0(r2)
+     sin->sin_port = htons(udpconn->u_lport);
+ 8036eac:	e0bffe17 	ldw	r2,-8(fp)
+ 8036eb0:	1080018b 	ldhu	r2,6(r2)
+ 8036eb4:	10bfffcc 	andi	r2,r2,65535
+ 8036eb8:	1004d23a 	srli	r2,r2,8
+ 8036ebc:	1007883a 	mov	r3,r2
+ 8036ec0:	e0bffe17 	ldw	r2,-8(fp)
+ 8036ec4:	1080018b 	ldhu	r2,6(r2)
+ 8036ec8:	10bfffcc 	andi	r2,r2,65535
+ 8036ecc:	1004923a 	slli	r2,r2,8
+ 8036ed0:	1884b03a 	or	r2,r3,r2
+ 8036ed4:	1007883a 	mov	r3,r2
+ 8036ed8:	e0bfff17 	ldw	r2,-4(fp)
+ 8036edc:	10c0008d 	sth	r3,2(r2)
+     sin->sin_addr.s_addr = udpconn->u_lhost;
+ 8036ee0:	e0bffe17 	ldw	r2,-8(fp)
+ 8036ee4:	10c00317 	ldw	r3,12(r2)
+ 8036ee8:	e0bfff17 	ldw	r2,-4(fp)
+ 8036eec:	10c00115 	stw	r3,4(r2)
+ 8036ef0:	00001406 	br	8036f44 <udp4_sockaddr+0x110>
+  }
+  else /* PRU_PEERADDR */
+  {
+    sin->sin_family = AF_INET;
+ 8036ef4:	e0bfff17 	ldw	r2,-4(fp)
+ 8036ef8:	00c00084 	movi	r3,2
+ 8036efc:	10c0000d 	sth	r3,0(r2)
+    sin->sin_port = htons(udpconn->u_fport);
+ 8036f00:	e0bffe17 	ldw	r2,-8(fp)
+ 8036f04:	1080020b 	ldhu	r2,8(r2)
+ 8036f08:	10bfffcc 	andi	r2,r2,65535
+ 8036f0c:	1004d23a 	srli	r2,r2,8
+ 8036f10:	1007883a 	mov	r3,r2
+ 8036f14:	e0bffe17 	ldw	r2,-8(fp)
+ 8036f18:	1080020b 	ldhu	r2,8(r2)
+ 8036f1c:	10bfffcc 	andi	r2,r2,65535
+ 8036f20:	1004923a 	slli	r2,r2,8
+ 8036f24:	1884b03a 	or	r2,r3,r2
+ 8036f28:	1007883a 	mov	r3,r2
+ 8036f2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036f30:	10c0008d 	sth	r3,2(r2)
+    sin->sin_addr.s_addr = udpconn->u_fhost;
+ 8036f34:	e0bffe17 	ldw	r2,-8(fp)
+ 8036f38:	10c00417 	ldw	r3,16(r2)
+ 8036f3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8036f40:	10c00115 	stw	r3,4(r2)
+  }
+  return 0;
+ 8036f44:	0005883a 	mov	r2,zero
+}
+ 8036f48:	e037883a 	mov	sp,fp
+ 8036f4c:	dfc00117 	ldw	ra,4(sp)
+ 8036f50:	df000017 	ldw	fp,0(sp)
+ 8036f54:	dec00204 	addi	sp,sp,8
+ 8036f58:	f800283a 	ret
+
+08036f5c <alt_busy_sleep>:
+#include "alt_types.h"
+
+#include "priv/alt_busy_sleep.h"
+
+unsigned int alt_busy_sleep (unsigned int us)
+{
+ 8036f5c:	defffa04 	addi	sp,sp,-24
+ 8036f60:	dfc00515 	stw	ra,20(sp)
+ 8036f64:	df000415 	stw	fp,16(sp)
+ 8036f68:	df000404 	addi	fp,sp,16
+ 8036f6c:	e13ffc15 	stw	r4,-16(fp)
+  {
+    cycles_per_loop = 9;
+  }
+  else  
+  {
+    cycles_per_loop = 3;
+ 8036f70:	008000c4 	movi	r2,3
+ 8036f74:	e0bffe15 	stw	r2,-8(fp)
+  }
+  
+
+  big_loops = us / (INT_MAX/
+  (ALT_CPU_FREQ/(cycles_per_loop * 1000000)));
+ 8036f78:	e0fffe17 	ldw	r3,-8(fp)
+ 8036f7c:	008003f4 	movhi	r2,15
+ 8036f80:	10909004 	addi	r2,r2,16960
+ 8036f84:	1885383a 	mul	r2,r3,r2
+ 8036f88:	100b883a 	mov	r5,r2
+ 8036f8c:	0100bef4 	movhi	r4,763
+ 8036f90:	213c2004 	addi	r4,r4,-3968
+ 8036f94:	800cff80 	call	800cff8 <__udivsi3>
+  big_loops = us / (INT_MAX/
+ 8036f98:	100b883a 	mov	r5,r2
+ 8036f9c:	01200034 	movhi	r4,32768
+ 8036fa0:	213fffc4 	addi	r4,r4,-1
+ 8036fa4:	800cff80 	call	800cff8 <__udivsi3>
+ 8036fa8:	100b883a 	mov	r5,r2
+ 8036fac:	e13ffc17 	ldw	r4,-16(fp)
+ 8036fb0:	800cff80 	call	800cff8 <__udivsi3>
+ 8036fb4:	e0bffd15 	stw	r2,-12(fp)
+
+  if (big_loops)
+ 8036fb8:	e0bffd17 	ldw	r2,-12(fp)
+ 8036fbc:	10002a26 	beq	r2,zero,8037068 <alt_busy_sleep+0x10c>
+  {
+    for(i=0;i<big_loops;i++)
+ 8036fc0:	e03fff15 	stw	zero,-4(fp)
+ 8036fc4:	00001706 	br	8037024 <alt_busy_sleep+0xc8>
+      /*
+      * Do NOT Try to single step the asm statement below 
+      * (single step will never return)
+      * Step out of this function or set a breakpoint after the asm statements
+      */
+      __asm__ volatile (
+ 8036fc8:	00a00034 	movhi	r2,32768
+ 8036fcc:	10bfffc4 	addi	r2,r2,-1
+ 8036fd0:	10bfffc4 	addi	r2,r2,-1
+ 8036fd4:	103ffe1e 	bne	r2,zero,8036fd0 <alt_busy_sleep+0x74>
+        "\n\t.pushsection .debug_alt_sim_info"
+        "\n\t.int 4, 0, 0b, 1b"
+        "\n\t.popsection"
+        :: "r" (INT_MAX));
+      us -= (INT_MAX/(ALT_CPU_FREQ/
+      (cycles_per_loop * 1000000)));
+ 8036fd8:	e0fffe17 	ldw	r3,-8(fp)
+ 8036fdc:	008003f4 	movhi	r2,15
+ 8036fe0:	10909004 	addi	r2,r2,16960
+ 8036fe4:	1885383a 	mul	r2,r3,r2
+      us -= (INT_MAX/(ALT_CPU_FREQ/
+ 8036fe8:	100b883a 	mov	r5,r2
+ 8036fec:	0100bef4 	movhi	r4,763
+ 8036ff0:	213c2004 	addi	r4,r4,-3968
+ 8036ff4:	800cff80 	call	800cff8 <__udivsi3>
+ 8036ff8:	100b883a 	mov	r5,r2
+ 8036ffc:	01200034 	movhi	r4,32768
+ 8037000:	213fffc4 	addi	r4,r4,-1
+ 8037004:	800cff80 	call	800cff8 <__udivsi3>
+ 8037008:	1007883a 	mov	r3,r2
+ 803700c:	e0bffc17 	ldw	r2,-16(fp)
+ 8037010:	10c5c83a 	sub	r2,r2,r3
+ 8037014:	e0bffc15 	stw	r2,-16(fp)
+    for(i=0;i<big_loops;i++)
+ 8037018:	e0bfff17 	ldw	r2,-4(fp)
+ 803701c:	10800044 	addi	r2,r2,1
+ 8037020:	e0bfff15 	stw	r2,-4(fp)
+ 8037024:	e0ffff17 	ldw	r3,-4(fp)
+ 8037028:	e0bffd17 	ldw	r2,-12(fp)
+ 803702c:	18bfe616 	blt	r3,r2,8036fc8 <alt_busy_sleep+0x6c>
+      "\n\tbne %0,zero,0b"
+      "\n1:"
+      "\n\t.pushsection .debug_alt_sim_info"
+      "\n\t.int 4, 0, 0b, 1b"
+      "\n\t.popsection"
+      :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
+ 8037030:	e0fffe17 	ldw	r3,-8(fp)
+ 8037034:	008003f4 	movhi	r2,15
+ 8037038:	10909004 	addi	r2,r2,16960
+ 803703c:	1885383a 	mul	r2,r3,r2
+ 8037040:	100b883a 	mov	r5,r2
+ 8037044:	0100bef4 	movhi	r4,763
+ 8037048:	213c2004 	addi	r4,r4,-3968
+ 803704c:	800cff80 	call	800cff8 <__udivsi3>
+ 8037050:	1007883a 	mov	r3,r2
+ 8037054:	e0bffc17 	ldw	r2,-16(fp)
+ 8037058:	1885383a 	mul	r2,r3,r2
+    __asm__ volatile (
+ 803705c:	10bfffc4 	addi	r2,r2,-1
+ 8037060:	103ffe1e 	bne	r2,zero,803705c <alt_busy_sleep+0x100>
+ 8037064:	00000d06 	br	803709c <alt_busy_sleep+0x140>
+      "\n\tbgt %0,zero,0b"
+      "\n1:"
+      "\n\t.pushsection .debug_alt_sim_info"
+      "\n\t.int 4, 0, 0b, 1b"
+      "\n\t.popsection"
+      :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
+ 8037068:	e0fffe17 	ldw	r3,-8(fp)
+ 803706c:	008003f4 	movhi	r2,15
+ 8037070:	10909004 	addi	r2,r2,16960
+ 8037074:	1885383a 	mul	r2,r3,r2
+ 8037078:	100b883a 	mov	r5,r2
+ 803707c:	0100bef4 	movhi	r4,763
+ 8037080:	213c2004 	addi	r4,r4,-3968
+ 8037084:	800cff80 	call	800cff8 <__udivsi3>
+ 8037088:	1007883a 	mov	r3,r2
+ 803708c:	e0bffc17 	ldw	r2,-16(fp)
+ 8037090:	1885383a 	mul	r2,r3,r2
+    __asm__ volatile (
+ 8037094:	10bfffc4 	addi	r2,r2,-1
+ 8037098:	00bffe16 	blt	zero,r2,8037094 <alt_busy_sleep+0x138>
+  }
+#endif /* #ifndef ALT_SIM_OPTIMIZE */
+  return 0;
+ 803709c:	0005883a 	mov	r2,zero
+}
+ 80370a0:	e037883a 	mov	sp,fp
+ 80370a4:	dfc00117 	ldw	ra,4(sp)
+ 80370a8:	df000017 	ldw	fp,0(sp)
+ 80370ac:	dec00204 	addi	sp,sp,8
+ 80370b0:	f800283a 	ret
+
+080370b4 <alt_get_errno>:
+{
+ 80370b4:	defffe04 	addi	sp,sp,-8
+ 80370b8:	dfc00115 	stw	ra,4(sp)
+ 80370bc:	df000015 	stw	fp,0(sp)
+ 80370c0:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 80370c4:	d0a02717 	ldw	r2,-32612(gp)
+ 80370c8:	10000326 	beq	r2,zero,80370d8 <alt_get_errno+0x24>
+ 80370cc:	d0a02717 	ldw	r2,-32612(gp)
+ 80370d0:	103ee83a 	callr	r2
+ 80370d4:	00000106 	br	80370dc <alt_get_errno+0x28>
+ 80370d8:	d0a04204 	addi	r2,gp,-32504
+}
+ 80370dc:	e037883a 	mov	sp,fp
+ 80370e0:	dfc00117 	ldw	ra,4(sp)
+ 80370e4:	df000017 	ldw	fp,0(sp)
+ 80370e8:	dec00204 	addi	sp,sp,8
+ 80370ec:	f800283a 	ret
+
+080370f0 <alt_close>:
+ *
+ * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h
+ */
+ 
+int ALT_CLOSE (int fildes)
+{
+ 80370f0:	defffb04 	addi	sp,sp,-20
+ 80370f4:	dfc00415 	stw	ra,16(sp)
+ 80370f8:	df000315 	stw	fp,12(sp)
+ 80370fc:	df000304 	addi	fp,sp,12
+ 8037100:	e13ffd15 	stw	r4,-12(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (fildes < 0) ? NULL : &alt_fd_list[fildes];
+ 8037104:	e0bffd17 	ldw	r2,-12(fp)
+ 8037108:	10000616 	blt	r2,zero,8037124 <alt_close+0x34>
+ 803710c:	e0bffd17 	ldw	r2,-12(fp)
+ 8037110:	10c00324 	muli	r3,r2,12
+ 8037114:	00820174 	movhi	r2,2053
+ 8037118:	10b21a04 	addi	r2,r2,-14232
+ 803711c:	1885883a 	add	r2,r3,r2
+ 8037120:	00000106 	br	8037128 <alt_close+0x38>
+ 8037124:	0005883a 	mov	r2,zero
+ 8037128:	e0bfff15 	stw	r2,-4(fp)
+
+  if (fd)
+ 803712c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037130:	10001926 	beq	r2,zero,8037198 <alt_close+0xa8>
+    /*
+     * If the associated file system/device has a close function, call it so 
+     * that any necessary cleanup code can run.
+     */
+
+    rval = (fd->dev->close) ? fd->dev->close(fd) : 0;
+ 8037134:	e0bfff17 	ldw	r2,-4(fp)
+ 8037138:	10800017 	ldw	r2,0(r2)
+ 803713c:	10800417 	ldw	r2,16(r2)
+ 8037140:	10000626 	beq	r2,zero,803715c <alt_close+0x6c>
+ 8037144:	e0bfff17 	ldw	r2,-4(fp)
+ 8037148:	10800017 	ldw	r2,0(r2)
+ 803714c:	10800417 	ldw	r2,16(r2)
+ 8037150:	e13fff17 	ldw	r4,-4(fp)
+ 8037154:	103ee83a 	callr	r2
+ 8037158:	00000106 	br	8037160 <alt_close+0x70>
+ 803715c:	0005883a 	mov	r2,zero
+ 8037160:	e0bffe15 	stw	r2,-8(fp)
+
+    /* Free the file descriptor structure and return. */
+
+    alt_release_fd (fildes);
+ 8037164:	e13ffd17 	ldw	r4,-12(fp)
+ 8037168:	8037e300 	call	8037e30 <alt_release_fd>
+    if (rval < 0)
+ 803716c:	e0bffe17 	ldw	r2,-8(fp)
+ 8037170:	1000070e 	bge	r2,zero,8037190 <alt_close+0xa0>
+    {
+      ALT_ERRNO = -rval;
+ 8037174:	80370b40 	call	80370b4 <alt_get_errno>
+ 8037178:	1007883a 	mov	r3,r2
+ 803717c:	e0bffe17 	ldw	r2,-8(fp)
+ 8037180:	0085c83a 	sub	r2,zero,r2
+ 8037184:	18800015 	stw	r2,0(r3)
+      return -1;
+ 8037188:	00bfffc4 	movi	r2,-1
+ 803718c:	00000706 	br	80371ac <alt_close+0xbc>
+    }
+    return 0;
+ 8037190:	0005883a 	mov	r2,zero
+ 8037194:	00000506 	br	80371ac <alt_close+0xbc>
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+ 8037198:	80370b40 	call	80370b4 <alt_get_errno>
+ 803719c:	1007883a 	mov	r3,r2
+ 80371a0:	00801444 	movi	r2,81
+ 80371a4:	18800015 	stw	r2,0(r3)
+    return -1;
+ 80371a8:	00bfffc4 	movi	r2,-1
+  }
+}
+ 80371ac:	e037883a 	mov	sp,fp
+ 80371b0:	dfc00117 	ldw	ra,4(sp)
+ 80371b4:	df000017 	ldw	fp,0(sp)
+ 80371b8:	dec00204 	addi	sp,sp,8
+ 80371bc:	f800283a 	ret
+
+080371c0 <alt_dcache_flush>:
+ *
+ * Any dirty lines in the data cache are written back to memory.
+ */
+
+void alt_dcache_flush (void* start, alt_u32 len)
+{
+ 80371c0:	defffb04 	addi	sp,sp,-20
+ 80371c4:	df000415 	stw	fp,16(sp)
+ 80371c8:	df000404 	addi	fp,sp,16
+ 80371cc:	e13ffd15 	stw	r4,-12(fp)
+ 80371d0:	e17ffc15 	stw	r5,-16(fp)
+#if NIOS2_DCACHE_SIZE > 0
+
+  char* i;
+  char* end = ((char*) start) + len; 
+ 80371d4:	e0fffd17 	ldw	r3,-12(fp)
+ 80371d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80371dc:	1885883a 	add	r2,r3,r2
+ 80371e0:	e0bffe15 	stw	r2,-8(fp)
+
+  for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE)
+ 80371e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80371e8:	e0bfff15 	stw	r2,-4(fp)
+ 80371ec:	00000506 	br	8037204 <alt_dcache_flush+0x44>
+  { 
+    ALT_FLUSH_DATA(i); 
+ 80371f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80371f4:	1000001b 	flushda	0(r2)
+  for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE)
+ 80371f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80371fc:	10800804 	addi	r2,r2,32
+ 8037200:	e0bfff15 	stw	r2,-4(fp)
+ 8037204:	e0ffff17 	ldw	r3,-4(fp)
+ 8037208:	e0bffe17 	ldw	r2,-8(fp)
+ 803720c:	18bff836 	bltu	r3,r2,80371f0 <alt_dcache_flush+0x30>
+   * For an unaligned flush request, we've got one more line left.
+   * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a 
+   * multiple of 2 (which it always is).
+   */
+
+  if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1))
+ 8037210:	e0bffd17 	ldw	r2,-12(fp)
+ 8037214:	108007cc 	andi	r2,r2,31
+ 8037218:	10000226 	beq	r2,zero,8037224 <alt_dcache_flush+0x64>
+  {
+    ALT_FLUSH_DATA(i);
+ 803721c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037220:	1000001b 	flushda	0(r2)
+  }
+
+#endif /* NIOS2_DCACHE_SIZE > 0 */
+}
+ 8037224:	0001883a 	nop
+ 8037228:	e037883a 	mov	sp,fp
+ 803722c:	df000017 	ldw	fp,0(sp)
+ 8037230:	dec00104 	addi	sp,sp,4
+ 8037234:	f800283a 	ret
+
+08037238 <alt_dev_null_write>:
+ * by the alt_dev_null device. It simple discards all data passed to it, and
+ * indicates that the data has been successfully transmitted.
+ */
+
+static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len)
+{
+ 8037238:	defffc04 	addi	sp,sp,-16
+ 803723c:	df000315 	stw	fp,12(sp)
+ 8037240:	df000304 	addi	fp,sp,12
+ 8037244:	e13fff15 	stw	r4,-4(fp)
+ 8037248:	e17ffe15 	stw	r5,-8(fp)
+ 803724c:	e1bffd15 	stw	r6,-12(fp)
+  return len;
+ 8037250:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8037254:	e037883a 	mov	sp,fp
+ 8037258:	df000017 	ldw	fp,0(sp)
+ 803725c:	dec00104 	addi	sp,sp,4
+ 8037260:	f800283a 	ret
+
+08037264 <alt_get_errno>:
+{
+ 8037264:	defffe04 	addi	sp,sp,-8
+ 8037268:	dfc00115 	stw	ra,4(sp)
+ 803726c:	df000015 	stw	fp,0(sp)
+ 8037270:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 8037274:	d0a02717 	ldw	r2,-32612(gp)
+ 8037278:	10000326 	beq	r2,zero,8037288 <alt_get_errno+0x24>
+ 803727c:	d0a02717 	ldw	r2,-32612(gp)
+ 8037280:	103ee83a 	callr	r2
+ 8037284:	00000106 	br	803728c <alt_get_errno+0x28>
+ 8037288:	d0a04204 	addi	r2,gp,-32504
+}
+ 803728c:	e037883a 	mov	sp,fp
+ 8037290:	dfc00117 	ldw	ra,4(sp)
+ 8037294:	df000017 	ldw	fp,0(sp)
+ 8037298:	dec00204 	addi	sp,sp,8
+ 803729c:	f800283a 	ret
+
+080372a0 <alt_dev_llist_insert>:
+/*
+ *
+ */
+
+int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list)
+{
+ 80372a0:	defffa04 	addi	sp,sp,-24
+ 80372a4:	dfc00515 	stw	ra,20(sp)
+ 80372a8:	df000415 	stw	fp,16(sp)
+ 80372ac:	df000404 	addi	fp,sp,16
+ 80372b0:	e13ffd15 	stw	r4,-12(fp)
+ 80372b4:	e17ffc15 	stw	r5,-16(fp)
+  /*
+   * check that the device exists, and that it has a valid name.
+   */
+
+  if (!dev || !dev->name)
+ 80372b8:	e0bffd17 	ldw	r2,-12(fp)
+ 80372bc:	10000326 	beq	r2,zero,80372cc <alt_dev_llist_insert+0x2c>
+ 80372c0:	e0bffd17 	ldw	r2,-12(fp)
+ 80372c4:	10800217 	ldw	r2,8(r2)
+ 80372c8:	1000061e 	bne	r2,zero,80372e4 <alt_dev_llist_insert+0x44>
+  {
+    ALT_ERRNO = EINVAL;
+ 80372cc:	80372640 	call	8037264 <alt_get_errno>
+ 80372d0:	1007883a 	mov	r3,r2
+ 80372d4:	00800584 	movi	r2,22
+ 80372d8:	18800015 	stw	r2,0(r3)
+    return -EINVAL;
+ 80372dc:	00bffa84 	movi	r2,-22
+ 80372e0:	00001306 	br	8037330 <alt_dev_llist_insert+0x90>
+  
+  /*
+   * register the device.
+   */
+  
+  alt_llist_insert(list, &dev->llist);
+ 80372e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80372e8:	e0fffc17 	ldw	r3,-16(fp)
+ 80372ec:	e0ffff15 	stw	r3,-4(fp)
+ 80372f0:	e0bffe15 	stw	r2,-8(fp)
+  entry->previous = list;
+ 80372f4:	e0bffe17 	ldw	r2,-8(fp)
+ 80372f8:	e0ffff17 	ldw	r3,-4(fp)
+ 80372fc:	10c00115 	stw	r3,4(r2)
+  entry->next     = list->next;
+ 8037300:	e0bfff17 	ldw	r2,-4(fp)
+ 8037304:	10c00017 	ldw	r3,0(r2)
+ 8037308:	e0bffe17 	ldw	r2,-8(fp)
+ 803730c:	10c00015 	stw	r3,0(r2)
+  list->next->previous = entry;
+ 8037310:	e0bfff17 	ldw	r2,-4(fp)
+ 8037314:	10800017 	ldw	r2,0(r2)
+ 8037318:	e0fffe17 	ldw	r3,-8(fp)
+ 803731c:	10c00115 	stw	r3,4(r2)
+  list->next           = entry;
+ 8037320:	e0bfff17 	ldw	r2,-4(fp)
+ 8037324:	e0fffe17 	ldw	r3,-8(fp)
+ 8037328:	10c00015 	stw	r3,0(r2)
+
+  return 0;  
+ 803732c:	0005883a 	mov	r2,zero
+}
+ 8037330:	e037883a 	mov	sp,fp
+ 8037334:	dfc00117 	ldw	ra,4(sp)
+ 8037338:	df000017 	ldw	fp,0(sp)
+ 803733c:	dec00204 	addi	sp,sp,8
+ 8037340:	f800283a 	ret
+
+08037344 <_do_ctors>:
+/*
+ * Run the C++ static constructors.
+ */
+
+void _do_ctors(void)
+{
+ 8037344:	defffd04 	addi	sp,sp,-12
+ 8037348:	dfc00215 	stw	ra,8(sp)
+ 803734c:	df000115 	stw	fp,4(sp)
+ 8037350:	df000104 	addi	fp,sp,4
+  constructor* ctor;
+
+  for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
+ 8037354:	00820134 	movhi	r2,2052
+ 8037358:	109a6904 	addi	r2,r2,27044
+ 803735c:	e0bfff15 	stw	r2,-4(fp)
+ 8037360:	00000606 	br	803737c <_do_ctors+0x38>
+        (*ctor) (); 
+ 8037364:	e0bfff17 	ldw	r2,-4(fp)
+ 8037368:	10800017 	ldw	r2,0(r2)
+ 803736c:	103ee83a 	callr	r2
+  for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
+ 8037370:	e0bfff17 	ldw	r2,-4(fp)
+ 8037374:	10bfff04 	addi	r2,r2,-4
+ 8037378:	e0bfff15 	stw	r2,-4(fp)
+ 803737c:	e0ffff17 	ldw	r3,-4(fp)
+ 8037380:	00820134 	movhi	r2,2052
+ 8037384:	109a6a04 	addi	r2,r2,27048
+ 8037388:	18bff62e 	bgeu	r3,r2,8037364 <_do_ctors+0x20>
+}
+ 803738c:	0001883a 	nop
+ 8037390:	e037883a 	mov	sp,fp
+ 8037394:	dfc00117 	ldw	ra,4(sp)
+ 8037398:	df000017 	ldw	fp,0(sp)
+ 803739c:	dec00204 	addi	sp,sp,8
+ 80373a0:	f800283a 	ret
+
+080373a4 <_do_dtors>:
+/*
+ * Run the C++ static destructors.
+ */
+
+void _do_dtors(void)
+{
+ 80373a4:	defffd04 	addi	sp,sp,-12
+ 80373a8:	dfc00215 	stw	ra,8(sp)
+ 80373ac:	df000115 	stw	fp,4(sp)
+ 80373b0:	df000104 	addi	fp,sp,4
+  destructor* dtor;
+
+  for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
+ 80373b4:	00820134 	movhi	r2,2052
+ 80373b8:	109a6904 	addi	r2,r2,27044
+ 80373bc:	e0bfff15 	stw	r2,-4(fp)
+ 80373c0:	00000606 	br	80373dc <_do_dtors+0x38>
+        (*dtor) (); 
+ 80373c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80373c8:	10800017 	ldw	r2,0(r2)
+ 80373cc:	103ee83a 	callr	r2
+  for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
+ 80373d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80373d4:	10bfff04 	addi	r2,r2,-4
+ 80373d8:	e0bfff15 	stw	r2,-4(fp)
+ 80373dc:	e0ffff17 	ldw	r3,-4(fp)
+ 80373e0:	00820134 	movhi	r2,2052
+ 80373e4:	109a6a04 	addi	r2,r2,27048
+ 80373e8:	18bff62e 	bgeu	r3,r2,80373c4 <_do_dtors+0x20>
+}
+ 80373ec:	0001883a 	nop
+ 80373f0:	e037883a 	mov	sp,fp
+ 80373f4:	dfc00117 	ldw	ra,4(sp)
+ 80373f8:	df000017 	ldw	fp,0(sp)
+ 80373fc:	dec00204 	addi	sp,sp,8
+ 8037400:	f800283a 	ret
+
+08037404 <alt_find_dev>:
+ * "name" must be an exact match for the devices registered name for a match to
+ * be found.
+ */
+ 
+alt_dev* alt_find_dev(const char* name, alt_llist* llist)
+{
+ 8037404:	defffa04 	addi	sp,sp,-24
+ 8037408:	dfc00515 	stw	ra,20(sp)
+ 803740c:	df000415 	stw	fp,16(sp)
+ 8037410:	df000404 	addi	fp,sp,16
+ 8037414:	e13ffd15 	stw	r4,-12(fp)
+ 8037418:	e17ffc15 	stw	r5,-16(fp)
+  alt_dev* next = (alt_dev*) llist->next;
+ 803741c:	e0bffc17 	ldw	r2,-16(fp)
+ 8037420:	10800017 	ldw	r2,0(r2)
+ 8037424:	e0bfff15 	stw	r2,-4(fp)
+  alt_32 len;
+
+  len  = strlen(name) + 1;
+ 8037428:	e13ffd17 	ldw	r4,-12(fp)
+ 803742c:	8002dac0 	call	8002dac <strlen>
+ 8037430:	10800044 	addi	r2,r2,1
+ 8037434:	e0bffe15 	stw	r2,-8(fp)
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+
+  while (next != (alt_dev*) llist)
+ 8037438:	00000d06 	br	8037470 <alt_find_dev+0x6c>
+    /* 
+     * memcmp() is used here rather than strcmp() in order to reduce the size
+     * of the executable.
+     */
+
+    if (!memcmp (next->name, name, len))
+ 803743c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037440:	10800217 	ldw	r2,8(r2)
+ 8037444:	e0fffe17 	ldw	r3,-8(fp)
+ 8037448:	180d883a 	mov	r6,r3
+ 803744c:	e17ffd17 	ldw	r5,-12(fp)
+ 8037450:	1009883a 	mov	r4,r2
+ 8037454:	8042cb80 	call	8042cb8 <memcmp>
+ 8037458:	1000021e 	bne	r2,zero,8037464 <alt_find_dev+0x60>
+    {
+      /* match found */
+
+      return next;
+ 803745c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037460:	00000706 	br	8037480 <alt_find_dev+0x7c>
+    }
+    next = (alt_dev*) next->llist.next;
+ 8037464:	e0bfff17 	ldw	r2,-4(fp)
+ 8037468:	10800017 	ldw	r2,0(r2)
+ 803746c:	e0bfff15 	stw	r2,-4(fp)
+  while (next != (alt_dev*) llist)
+ 8037470:	e0ffff17 	ldw	r3,-4(fp)
+ 8037474:	e0bffc17 	ldw	r2,-16(fp)
+ 8037478:	18bff01e 	bne	r3,r2,803743c <alt_find_dev+0x38>
+  }
+  
+  /* No match found */
+  
+  return NULL;
+ 803747c:	0005883a 	mov	r2,zero
+}
+ 8037480:	e037883a 	mov	sp,fp
+ 8037484:	dfc00117 	ldw	ra,4(sp)
+ 8037488:	df000017 	ldw	fp,0(sp)
+ 803748c:	dec00204 	addi	sp,sp,8
+ 8037490:	f800283a 	ret
+
+08037494 <alt_ic_isr_register>:
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+ 8037494:	defff904 	addi	sp,sp,-28
+ 8037498:	dfc00615 	stw	ra,24(sp)
+ 803749c:	df000515 	stw	fp,20(sp)
+ 80374a0:	df000504 	addi	fp,sp,20
+ 80374a4:	e13fff15 	stw	r4,-4(fp)
+ 80374a8:	e17ffe15 	stw	r5,-8(fp)
+ 80374ac:	e1bffd15 	stw	r6,-12(fp)
+ 80374b0:	e1fffc15 	stw	r7,-16(fp)
+    return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags);
+ 80374b4:	e0800217 	ldw	r2,8(fp)
+ 80374b8:	d8800015 	stw	r2,0(sp)
+ 80374bc:	e1fffc17 	ldw	r7,-16(fp)
+ 80374c0:	e1bffd17 	ldw	r6,-12(fp)
+ 80374c4:	e17ffe17 	ldw	r5,-8(fp)
+ 80374c8:	e13fff17 	ldw	r4,-4(fp)
+ 80374cc:	80376440 	call	8037644 <alt_iic_isr_register>
+}  
+ 80374d0:	e037883a 	mov	sp,fp
+ 80374d4:	dfc00117 	ldw	ra,4(sp)
+ 80374d8:	df000017 	ldw	fp,0(sp)
+ 80374dc:	dec00204 	addi	sp,sp,8
+ 80374e0:	f800283a 	ret
+
+080374e4 <alt_ic_irq_enable>:
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq)
+{
+ 80374e4:	defff904 	addi	sp,sp,-28
+ 80374e8:	df000615 	stw	fp,24(sp)
+ 80374ec:	df000604 	addi	fp,sp,24
+ 80374f0:	e13ffb15 	stw	r4,-20(fp)
+ 80374f4:	e17ffa15 	stw	r5,-24(fp)
+ 80374f8:	e0bffa17 	ldw	r2,-24(fp)
+ 80374fc:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8037500:	0005303a 	rdctl	r2,status
+ 8037504:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8037508:	e0fffe17 	ldw	r3,-8(fp)
+ 803750c:	00bfff84 	movi	r2,-2
+ 8037510:	1884703a 	and	r2,r3,r2
+ 8037514:	1001703a 	wrctl	status,r2
+  return context;
+ 8037518:	e0bffe17 	ldw	r2,-8(fp)
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id)
+{
+  alt_irq_context  status;
+  extern volatile alt_u32 alt_irq_active;
+
+  status = alt_irq_disable_all ();
+ 803751c:	e0bffd15 	stw	r2,-12(fp)
+
+  alt_irq_active |= (1 << id);
+ 8037520:	00c00044 	movi	r3,1
+ 8037524:	e0bfff17 	ldw	r2,-4(fp)
+ 8037528:	1884983a 	sll	r2,r3,r2
+ 803752c:	1007883a 	mov	r3,r2
+ 8037530:	d0a08c17 	ldw	r2,-32208(gp)
+ 8037534:	1884b03a 	or	r2,r3,r2
+ 8037538:	d0a08c15 	stw	r2,-32208(gp)
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+ 803753c:	d0a08c17 	ldw	r2,-32208(gp)
+ 8037540:	100170fa 	wrctl	ienable,r2
+ 8037544:	e0bffd17 	ldw	r2,-12(fp)
+ 8037548:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 803754c:	e0bffc17 	ldw	r2,-16(fp)
+ 8037550:	1001703a 	wrctl	status,r2
+
+  alt_irq_enable_all(status);
+
+  return 0;
+ 8037554:	0005883a 	mov	r2,zero
+    return alt_irq_enable(irq);
+ 8037558:	0001883a 	nop
+}
+ 803755c:	e037883a 	mov	sp,fp
+ 8037560:	df000017 	ldw	fp,0(sp)
+ 8037564:	dec00104 	addi	sp,sp,4
+ 8037568:	f800283a 	ret
+
+0803756c <alt_ic_irq_disable>:
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq)
+{
+ 803756c:	defff904 	addi	sp,sp,-28
+ 8037570:	df000615 	stw	fp,24(sp)
+ 8037574:	df000604 	addi	fp,sp,24
+ 8037578:	e13ffb15 	stw	r4,-20(fp)
+ 803757c:	e17ffa15 	stw	r5,-24(fp)
+ 8037580:	e0bffa17 	ldw	r2,-24(fp)
+ 8037584:	e0bfff15 	stw	r2,-4(fp)
+  NIOS2_READ_STATUS (context);
+ 8037588:	0005303a 	rdctl	r2,status
+ 803758c:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8037590:	e0fffe17 	ldw	r3,-8(fp)
+ 8037594:	00bfff84 	movi	r2,-2
+ 8037598:	1884703a 	and	r2,r3,r2
+ 803759c:	1001703a 	wrctl	status,r2
+  return context;
+ 80375a0:	e0bffe17 	ldw	r2,-8(fp)
+  status = alt_irq_disable_all ();
+ 80375a4:	e0bffd15 	stw	r2,-12(fp)
+  alt_irq_active &= ~(1 << id);
+ 80375a8:	00c00044 	movi	r3,1
+ 80375ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80375b0:	1884983a 	sll	r2,r3,r2
+ 80375b4:	0084303a 	nor	r2,zero,r2
+ 80375b8:	1007883a 	mov	r3,r2
+ 80375bc:	d0a08c17 	ldw	r2,-32208(gp)
+ 80375c0:	1884703a 	and	r2,r3,r2
+ 80375c4:	d0a08c15 	stw	r2,-32208(gp)
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+ 80375c8:	d0a08c17 	ldw	r2,-32208(gp)
+ 80375cc:	100170fa 	wrctl	ienable,r2
+ 80375d0:	e0bffd17 	ldw	r2,-12(fp)
+ 80375d4:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context);
+ 80375d8:	e0bffc17 	ldw	r2,-16(fp)
+ 80375dc:	1001703a 	wrctl	status,r2
+  return 0;
+ 80375e0:	0005883a 	mov	r2,zero
+    return alt_irq_disable(irq);
+ 80375e4:	0001883a 	nop
+}
+ 80375e8:	e037883a 	mov	sp,fp
+ 80375ec:	df000017 	ldw	fp,0(sp)
+ 80375f0:	dec00104 	addi	sp,sp,4
+ 80375f4:	f800283a 	ret
+
+080375f8 <alt_ic_irq_enabled>:
+  * @param irq              IRQ number
+  * @return                 Zero if corresponding interrupt is disabled and
+  *                         non-zero otherwise.
+  */
+alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq)
+{
+ 80375f8:	defffc04 	addi	sp,sp,-16
+ 80375fc:	df000315 	stw	fp,12(sp)
+ 8037600:	df000304 	addi	fp,sp,12
+ 8037604:	e13ffe15 	stw	r4,-8(fp)
+ 8037608:	e17ffd15 	stw	r5,-12(fp)
+    alt_u32 irq_enabled;
+
+    NIOS2_READ_IENABLE(irq_enabled);
+ 803760c:	000530fa 	rdctl	r2,ienable
+ 8037610:	e0bfff15 	stw	r2,-4(fp)
+
+    return (irq_enabled & (1 << irq)) ? 1: 0;
+ 8037614:	00c00044 	movi	r3,1
+ 8037618:	e0bffd17 	ldw	r2,-12(fp)
+ 803761c:	1884983a 	sll	r2,r3,r2
+ 8037620:	1007883a 	mov	r3,r2
+ 8037624:	e0bfff17 	ldw	r2,-4(fp)
+ 8037628:	1884703a 	and	r2,r3,r2
+ 803762c:	1004c03a 	cmpne	r2,r2,zero
+ 8037630:	10803fcc 	andi	r2,r2,255
+}
+ 8037634:	e037883a 	mov	sp,fp
+ 8037638:	df000017 	ldw	fp,0(sp)
+ 803763c:	dec00104 	addi	sp,sp,4
+ 8037640:	f800283a 	ret
+
+08037644 <alt_iic_isr_register>:
+  * @param flags            
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+ 8037644:	defff504 	addi	sp,sp,-44
+ 8037648:	dfc00a15 	stw	ra,40(sp)
+ 803764c:	df000915 	stw	fp,36(sp)
+ 8037650:	df000904 	addi	fp,sp,36
+ 8037654:	e13ffa15 	stw	r4,-24(fp)
+ 8037658:	e17ff915 	stw	r5,-28(fp)
+ 803765c:	e1bff815 	stw	r6,-32(fp)
+ 8037660:	e1fff715 	stw	r7,-36(fp)
+  int rc = -EINVAL;  
+ 8037664:	00bffa84 	movi	r2,-22
+ 8037668:	e0bfff15 	stw	r2,-4(fp)
+  int id = irq;             /* IRQ interpreted as the interrupt ID. */
+ 803766c:	e0bff917 	ldw	r2,-28(fp)
+ 8037670:	e0bffe15 	stw	r2,-8(fp)
+  alt_irq_context status;
+
+  if (id < ALT_NIRQ)
+ 8037674:	e0bffe17 	ldw	r2,-8(fp)
+ 8037678:	10800808 	cmpgei	r2,r2,32
+ 803767c:	1000241e 	bne	r2,zero,8037710 <alt_iic_isr_register+0xcc>
+  NIOS2_READ_STATUS (context);
+ 8037680:	0005303a 	rdctl	r2,status
+ 8037684:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8037688:	e0fffc17 	ldw	r3,-16(fp)
+ 803768c:	00bfff84 	movi	r2,-2
+ 8037690:	1884703a 	and	r2,r3,r2
+ 8037694:	1001703a 	wrctl	status,r2
+  return context;
+ 8037698:	e0bffc17 	ldw	r2,-16(fp)
+     * interrupts are disabled while the handler tables are updated to ensure
+     * that an interrupt doesn't occur while the tables are in an inconsistant
+     * state.
+     */
+
+    status = alt_irq_disable_all();
+ 803769c:	e0bffd15 	stw	r2,-12(fp)
+
+    alt_irq[id].handler = isr;
+ 80376a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80376a4:	100890fa 	slli	r4,r2,3
+ 80376a8:	e0fff817 	ldw	r3,-32(fp)
+ 80376ac:	008201b4 	movhi	r2,2054
+ 80376b0:	2085883a 	add	r2,r4,r2
+ 80376b4:	10f8dc15 	stw	r3,-7312(r2)
+    alt_irq[id].context = isr_context;
+ 80376b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80376bc:	100890fa 	slli	r4,r2,3
+ 80376c0:	e0fff717 	ldw	r3,-36(fp)
+ 80376c4:	008201b4 	movhi	r2,2054
+ 80376c8:	2085883a 	add	r2,r4,r2
+ 80376cc:	10f8dd15 	stw	r3,-7308(r2)
+
+    rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
+ 80376d0:	e0bff817 	ldw	r2,-32(fp)
+ 80376d4:	10000526 	beq	r2,zero,80376ec <alt_iic_isr_register+0xa8>
+ 80376d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80376dc:	100b883a 	mov	r5,r2
+ 80376e0:	e13ffa17 	ldw	r4,-24(fp)
+ 80376e4:	80374e40 	call	80374e4 <alt_ic_irq_enable>
+ 80376e8:	00000406 	br	80376fc <alt_iic_isr_register+0xb8>
+ 80376ec:	e0bffe17 	ldw	r2,-8(fp)
+ 80376f0:	100b883a 	mov	r5,r2
+ 80376f4:	e13ffa17 	ldw	r4,-24(fp)
+ 80376f8:	803756c0 	call	803756c <alt_ic_irq_disable>
+ 80376fc:	e0bfff15 	stw	r2,-4(fp)
+ 8037700:	e0bffd17 	ldw	r2,-12(fp)
+ 8037704:	e0bffb15 	stw	r2,-20(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8037708:	e0bffb17 	ldw	r2,-20(fp)
+ 803770c:	1001703a 	wrctl	status,r2
+
+    alt_irq_enable_all(status);
+  }
+
+  return rc; 
+ 8037710:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8037714:	e037883a 	mov	sp,fp
+ 8037718:	dfc00117 	ldw	ra,4(sp)
+ 803771c:	df000017 	ldw	fp,0(sp)
+ 8037720:	dec00204 	addi	sp,sp,8
+ 8037724:	f800283a 	ret
+
+08037728 <alt_open_fd>:
+ * If the device can not be succesfully opened, then the input file descriptor
+ * remains unchanged.
+ */
+
+static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode)
+{
+ 8037728:	defff904 	addi	sp,sp,-28
+ 803772c:	dfc00615 	stw	ra,24(sp)
+ 8037730:	df000515 	stw	fp,20(sp)
+ 8037734:	df000504 	addi	fp,sp,20
+ 8037738:	e13ffe15 	stw	r4,-8(fp)
+ 803773c:	e17ffd15 	stw	r5,-12(fp)
+ 8037740:	e1bffc15 	stw	r6,-16(fp)
+ 8037744:	e1fffb15 	stw	r7,-20(fp)
+  int old;
+
+  old = open (name, flags, mode);
+ 8037748:	e1bffb17 	ldw	r6,-20(fp)
+ 803774c:	e17ffc17 	ldw	r5,-16(fp)
+ 8037750:	e13ffd17 	ldw	r4,-12(fp)
+ 8037754:	80379480 	call	8037948 <open>
+ 8037758:	e0bfff15 	stw	r2,-4(fp)
+
+  if (old >= 0)
+ 803775c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037760:	10001716 	blt	r2,zero,80377c0 <alt_open_fd+0x98>
+  {
+    fd->dev      = alt_fd_list[old].dev;
+ 8037764:	e0bfff17 	ldw	r2,-4(fp)
+ 8037768:	10c00324 	muli	r3,r2,12
+ 803776c:	00820174 	movhi	r2,2053
+ 8037770:	1885883a 	add	r2,r3,r2
+ 8037774:	10f21a17 	ldw	r3,-14232(r2)
+ 8037778:	e0bffe17 	ldw	r2,-8(fp)
+ 803777c:	10c00015 	stw	r3,0(r2)
+    fd->priv     = alt_fd_list[old].priv;
+ 8037780:	e0bfff17 	ldw	r2,-4(fp)
+ 8037784:	10c00324 	muli	r3,r2,12
+ 8037788:	00820174 	movhi	r2,2053
+ 803778c:	1885883a 	add	r2,r3,r2
+ 8037790:	10f21b17 	ldw	r3,-14228(r2)
+ 8037794:	e0bffe17 	ldw	r2,-8(fp)
+ 8037798:	10c00115 	stw	r3,4(r2)
+    fd->fd_flags = alt_fd_list[old].fd_flags;
+ 803779c:	e0bfff17 	ldw	r2,-4(fp)
+ 80377a0:	10c00324 	muli	r3,r2,12
+ 80377a4:	00820174 	movhi	r2,2053
+ 80377a8:	1885883a 	add	r2,r3,r2
+ 80377ac:	10f21c17 	ldw	r3,-14224(r2)
+ 80377b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80377b4:	10c00215 	stw	r3,8(r2)
+
+    alt_release_fd (old);
+ 80377b8:	e13fff17 	ldw	r4,-4(fp)
+ 80377bc:	8037e300 	call	8037e30 <alt_release_fd>
+  }
+} 
+ 80377c0:	0001883a 	nop
+ 80377c4:	e037883a 	mov	sp,fp
+ 80377c8:	dfc00117 	ldw	ra,4(sp)
+ 80377cc:	df000017 	ldw	fp,0(sp)
+ 80377d0:	dec00204 	addi	sp,sp,8
+ 80377d4:	f800283a 	ret
+
+080377d8 <alt_io_redirect>:
+ */
+ 
+void alt_io_redirect(const char* stdout_dev, 
+                     const char* stdin_dev, 
+                     const char* stderr_dev)
+{
+ 80377d8:	defffb04 	addi	sp,sp,-20
+ 80377dc:	dfc00415 	stw	ra,16(sp)
+ 80377e0:	df000315 	stw	fp,12(sp)
+ 80377e4:	df000304 	addi	fp,sp,12
+ 80377e8:	e13fff15 	stw	r4,-4(fp)
+ 80377ec:	e17ffe15 	stw	r5,-8(fp)
+ 80377f0:	e1bffd15 	stw	r6,-12(fp)
+  /* Redirect the channels */
+
+  alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777);
+ 80377f4:	01c07fc4 	movi	r7,511
+ 80377f8:	01800044 	movi	r6,1
+ 80377fc:	e17fff17 	ldw	r5,-4(fp)
+ 8037800:	01020174 	movhi	r4,2053
+ 8037804:	21321d04 	addi	r4,r4,-14220
+ 8037808:	80377280 	call	8037728 <alt_open_fd>
+  alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777);
+ 803780c:	01c07fc4 	movi	r7,511
+ 8037810:	000d883a 	mov	r6,zero
+ 8037814:	e17ffe17 	ldw	r5,-8(fp)
+ 8037818:	01020174 	movhi	r4,2053
+ 803781c:	21321a04 	addi	r4,r4,-14232
+ 8037820:	80377280 	call	8037728 <alt_open_fd>
+  alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777);
+ 8037824:	01c07fc4 	movi	r7,511
+ 8037828:	01800044 	movi	r6,1
+ 803782c:	e17ffd17 	ldw	r5,-12(fp)
+ 8037830:	01020174 	movhi	r4,2053
+ 8037834:	21322004 	addi	r4,r4,-14208
+ 8037838:	80377280 	call	8037728 <alt_open_fd>
+}  
+ 803783c:	0001883a 	nop
+ 8037840:	e037883a 	mov	sp,fp
+ 8037844:	dfc00117 	ldw	ra,4(sp)
+ 8037848:	df000017 	ldw	fp,0(sp)
+ 803784c:	dec00204 	addi	sp,sp,8
+ 8037850:	f800283a 	ret
+
+08037854 <alt_get_errno>:
+{
+ 8037854:	defffe04 	addi	sp,sp,-8
+ 8037858:	dfc00115 	stw	ra,4(sp)
+ 803785c:	df000015 	stw	fp,0(sp)
+ 8037860:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 8037864:	d0a02717 	ldw	r2,-32612(gp)
+ 8037868:	10000326 	beq	r2,zero,8037878 <alt_get_errno+0x24>
+ 803786c:	d0a02717 	ldw	r2,-32612(gp)
+ 8037870:	103ee83a 	callr	r2
+ 8037874:	00000106 	br	803787c <alt_get_errno+0x28>
+ 8037878:	d0a04204 	addi	r2,gp,-32504
+}
+ 803787c:	e037883a 	mov	sp,fp
+ 8037880:	dfc00117 	ldw	ra,4(sp)
+ 8037884:	df000017 	ldw	fp,0(sp)
+ 8037888:	dec00204 	addi	sp,sp,8
+ 803788c:	f800283a 	ret
+
+08037890 <alt_file_locked>:
+ * performed for devices. Filesystems are required to handle the ioctl() call
+ * themselves, and report the error from the filesystems open() function. 
+ */ 
+
+static int alt_file_locked (alt_fd* fd)
+{
+ 8037890:	defffd04 	addi	sp,sp,-12
+ 8037894:	df000215 	stw	fp,8(sp)
+ 8037898:	df000204 	addi	fp,sp,8
+ 803789c:	e13ffe15 	stw	r4,-8(fp)
+
+  /*
+   * Mark the file descriptor as belonging to a device.
+   */
+
+  fd->fd_flags |= ALT_FD_DEV;
+ 80378a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80378a4:	10800217 	ldw	r2,8(r2)
+ 80378a8:	10d00034 	orhi	r3,r2,16384
+ 80378ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80378b0:	10c00215 	stw	r3,8(r2)
+  /*
+   * Loop through all current file descriptors searching for one that's locked
+   * for exclusive access. If a match is found, generate an error.
+   */
+
+  for (i = 0; i <= alt_max_fd; i++)
+ 80378b4:	e03fff15 	stw	zero,-4(fp)
+ 80378b8:	00001a06 	br	8037924 <alt_file_locked+0x94>
+  {
+    if ((alt_fd_list[i].dev == fd->dev) &&
+ 80378bc:	e0bfff17 	ldw	r2,-4(fp)
+ 80378c0:	10c00324 	muli	r3,r2,12
+ 80378c4:	00820174 	movhi	r2,2053
+ 80378c8:	1885883a 	add	r2,r3,r2
+ 80378cc:	10f21a17 	ldw	r3,-14232(r2)
+ 80378d0:	e0bffe17 	ldw	r2,-8(fp)
+ 80378d4:	10800017 	ldw	r2,0(r2)
+ 80378d8:	18800f1e 	bne	r3,r2,8037918 <alt_file_locked+0x88>
+        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+ 80378dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80378e0:	10c00324 	muli	r3,r2,12
+ 80378e4:	00820174 	movhi	r2,2053
+ 80378e8:	1885883a 	add	r2,r3,r2
+ 80378ec:	10b21c17 	ldw	r2,-14224(r2)
+    if ((alt_fd_list[i].dev == fd->dev) &&
+ 80378f0:	1000090e 	bge	r2,zero,8037918 <alt_file_locked+0x88>
+        (&alt_fd_list[i] != fd))
+ 80378f4:	e0bfff17 	ldw	r2,-4(fp)
+ 80378f8:	10c00324 	muli	r3,r2,12
+ 80378fc:	00820174 	movhi	r2,2053
+ 8037900:	10b21a04 	addi	r2,r2,-14232
+ 8037904:	1885883a 	add	r2,r3,r2
+        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+ 8037908:	e0fffe17 	ldw	r3,-8(fp)
+ 803790c:	18800226 	beq	r3,r2,8037918 <alt_file_locked+0x88>
+    {
+      return -EACCES;
+ 8037910:	00bffcc4 	movi	r2,-13
+ 8037914:	00000806 	br	8037938 <alt_file_locked+0xa8>
+  for (i = 0; i <= alt_max_fd; i++)
+ 8037918:	e0bfff17 	ldw	r2,-4(fp)
+ 803791c:	10800044 	addi	r2,r2,1
+ 8037920:	e0bfff15 	stw	r2,-4(fp)
+ 8037924:	d0a02617 	ldw	r2,-32616(gp)
+ 8037928:	1007883a 	mov	r3,r2
+ 803792c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037930:	18bfe22e 	bgeu	r3,r2,80378bc <alt_file_locked+0x2c>
+    }
+  }
+  
+  /* The device is not locked */
+ 
+  return 0;
+ 8037934:	0005883a 	mov	r2,zero
+}
+ 8037938:	e037883a 	mov	sp,fp
+ 803793c:	df000017 	ldw	fp,0(sp)
+ 8037940:	dec00104 	addi	sp,sp,4
+ 8037944:	f800283a 	ret
+
+08037948 <open>:
+ *
+ * ALT_OPEN is mapped onto the open() system call in alt_syscall.h
+ */
+ 
+int ALT_OPEN (const char* file, int flags, int mode)
+{ 
+ 8037948:	defff604 	addi	sp,sp,-40
+ 803794c:	dfc00915 	stw	ra,36(sp)
+ 8037950:	df000815 	stw	fp,32(sp)
+ 8037954:	df000804 	addi	fp,sp,32
+ 8037958:	e13ffa15 	stw	r4,-24(fp)
+ 803795c:	e17ff915 	stw	r5,-28(fp)
+ 8037960:	e1bff815 	stw	r6,-32(fp)
+  alt_dev* dev;
+  alt_fd*  fd;
+  int index  = -1;
+ 8037964:	00bfffc4 	movi	r2,-1
+ 8037968:	e0bffe15 	stw	r2,-8(fp)
+  int status = -ENODEV;
+ 803796c:	00bffb44 	movi	r2,-19
+ 8037970:	e0bffd15 	stw	r2,-12(fp)
+  int isafs = 0;
+ 8037974:	e03ffc15 	stw	zero,-16(fp)
+  /* 
+   * Check the device list, to see if a device with a matching name is 
+   * registered.
+   */
+  
+  if (!(dev = alt_find_dev (file, &alt_dev_list)))
+ 8037978:	d1602404 	addi	r5,gp,-32624
+ 803797c:	e13ffa17 	ldw	r4,-24(fp)
+ 8037980:	80374040 	call	8037404 <alt_find_dev>
+ 8037984:	e0bfff15 	stw	r2,-4(fp)
+ 8037988:	e0bfff17 	ldw	r2,-4(fp)
+ 803798c:	1000051e 	bne	r2,zero,80379a4 <open+0x5c>
+  {
+    /* No matching device, so try the filesystem list */
+
+    dev   = alt_find_file (file);
+ 8037990:	e13ffa17 	ldw	r4,-24(fp)
+ 8037994:	80428180 	call	8042818 <alt_find_file>
+ 8037998:	e0bfff15 	stw	r2,-4(fp)
+    isafs = 1;
+ 803799c:	00800044 	movi	r2,1
+ 80379a0:	e0bffc15 	stw	r2,-16(fp)
+
+  /* 
+   * If a matching device or filesystem is found, allocate a file descriptor. 
+   */
+
+  if (dev)
+ 80379a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80379a8:	10002926 	beq	r2,zero,8037a50 <open+0x108>
+  {
+    if ((index = alt_get_fd (dev)) < 0)
+ 80379ac:	e13fff17 	ldw	r4,-4(fp)
+ 80379b0:	80429200 	call	8042920 <alt_get_fd>
+ 80379b4:	e0bffe15 	stw	r2,-8(fp)
+ 80379b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80379bc:	1000030e 	bge	r2,zero,80379cc <open+0x84>
+    {
+      status = index;
+ 80379c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80379c4:	e0bffd15 	stw	r2,-12(fp)
+ 80379c8:	00002306 	br	8037a58 <open+0x110>
+    }
+    else
+    {
+      fd = &alt_fd_list[index];
+ 80379cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80379d0:	10c00324 	muli	r3,r2,12
+ 80379d4:	00820174 	movhi	r2,2053
+ 80379d8:	10b21a04 	addi	r2,r2,-14232
+ 80379dc:	1885883a 	add	r2,r3,r2
+ 80379e0:	e0bffb15 	stw	r2,-20(fp)
+      fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK);
+ 80379e4:	e0fff917 	ldw	r3,-28(fp)
+ 80379e8:	00900034 	movhi	r2,16384
+ 80379ec:	10bfffc4 	addi	r2,r2,-1
+ 80379f0:	1886703a 	and	r3,r3,r2
+ 80379f4:	e0bffb17 	ldw	r2,-20(fp)
+ 80379f8:	10c00215 	stw	r3,8(r2)
+      
+      /* If this is a device, ensure it isn't already locked */
+
+      if (isafs || ((status = alt_file_locked (fd)) >= 0))
+ 80379fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8037a00:	1000051e 	bne	r2,zero,8037a18 <open+0xd0>
+ 8037a04:	e13ffb17 	ldw	r4,-20(fp)
+ 8037a08:	80378900 	call	8037890 <alt_file_locked>
+ 8037a0c:	e0bffd15 	stw	r2,-12(fp)
+ 8037a10:	e0bffd17 	ldw	r2,-12(fp)
+ 8037a14:	10001016 	blt	r2,zero,8037a58 <open+0x110>
+        /* 
+         * If the device or filesystem provides an open() callback function,
+         * call it now to perform any device/filesystem specific operations.
+         */
+    
+        status = (dev->open) ? dev->open(fd, file, flags, mode): 0;
+ 8037a18:	e0bfff17 	ldw	r2,-4(fp)
+ 8037a1c:	10800317 	ldw	r2,12(r2)
+ 8037a20:	10000826 	beq	r2,zero,8037a44 <open+0xfc>
+ 8037a24:	e0bfff17 	ldw	r2,-4(fp)
+ 8037a28:	10800317 	ldw	r2,12(r2)
+ 8037a2c:	e1fff817 	ldw	r7,-32(fp)
+ 8037a30:	e1bff917 	ldw	r6,-28(fp)
+ 8037a34:	e17ffa17 	ldw	r5,-24(fp)
+ 8037a38:	e13ffb17 	ldw	r4,-20(fp)
+ 8037a3c:	103ee83a 	callr	r2
+ 8037a40:	00000106 	br	8037a48 <open+0x100>
+ 8037a44:	0005883a 	mov	r2,zero
+ 8037a48:	e0bffd15 	stw	r2,-12(fp)
+ 8037a4c:	00000206 	br	8037a58 <open+0x110>
+      }
+    }
+  }
+  else
+  {
+    status = -ENODEV;
+ 8037a50:	00bffb44 	movi	r2,-19
+ 8037a54:	e0bffd15 	stw	r2,-12(fp)
+  }
+
+  /* Allocation failed, so clean up and return an error */ 
+
+  if (status < 0)
+ 8037a58:	e0bffd17 	ldw	r2,-12(fp)
+ 8037a5c:	1000090e 	bge	r2,zero,8037a84 <open+0x13c>
+  {
+    alt_release_fd (index);  
+ 8037a60:	e13ffe17 	ldw	r4,-8(fp)
+ 8037a64:	8037e300 	call	8037e30 <alt_release_fd>
+    ALT_ERRNO = -status;
+ 8037a68:	80378540 	call	8037854 <alt_get_errno>
+ 8037a6c:	1007883a 	mov	r3,r2
+ 8037a70:	e0bffd17 	ldw	r2,-12(fp)
+ 8037a74:	0085c83a 	sub	r2,zero,r2
+ 8037a78:	18800015 	stw	r2,0(r3)
+    return -1;
+ 8037a7c:	00bfffc4 	movi	r2,-1
+ 8037a80:	00000106 	br	8037a88 <open+0x140>
+  }
+  
+  /* return the reference upon success */
+
+  return index;
+ 8037a84:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8037a88:	e037883a 	mov	sp,fp
+ 8037a8c:	dfc00117 	ldw	ra,4(sp)
+ 8037a90:	df000017 	ldw	fp,0(sp)
+ 8037a94:	dec00204 	addi	sp,sp,8
+ 8037a98:	f800283a 	ret
+
+08037a9c <alt_printf>:
+/* 
+ * ALT printf function 
+ */
+void 
+alt_printf(const char* fmt, ... )
+{
+ 8037a9c:	defff204 	addi	sp,sp,-56
+ 8037aa0:	dfc00a15 	stw	ra,40(sp)
+ 8037aa4:	df000915 	stw	fp,36(sp)
+ 8037aa8:	df000904 	addi	fp,sp,36
+ 8037aac:	e13ff715 	stw	r4,-36(fp)
+ 8037ab0:	e1400215 	stw	r5,8(fp)
+ 8037ab4:	e1800315 	stw	r6,12(fp)
+ 8037ab8:	e1c00415 	stw	r7,16(fp)
+	va_list args;
+	va_start(args, fmt);
+ 8037abc:	e0800204 	addi	r2,fp,8
+ 8037ac0:	e0bff815 	stw	r2,-32(fp)
+    const char *w;
+    char c;
+
+    /* Process format string. */
+    w = fmt;
+ 8037ac4:	e0bff717 	ldw	r2,-36(fp)
+ 8037ac8:	e0bfff15 	stw	r2,-4(fp)
+    while ((c = *w++) != 0)
+ 8037acc:	00006f06 	br	8037c8c <alt_printf+0x1f0>
+    {
+        /* If not a format escape character, just print  */
+        /* character.  Otherwise, process format string. */
+        if (c != '%')
+ 8037ad0:	e0bffec7 	ldb	r2,-5(fp)
+ 8037ad4:	10800960 	cmpeqi	r2,r2,37
+ 8037ad8:	1000041e 	bne	r2,zero,8037aec <alt_printf+0x50>
+        {
+            alt_putchar(c);
+ 8037adc:	e0bffec7 	ldb	r2,-5(fp)
+ 8037ae0:	1009883a 	mov	r4,r2
+ 8037ae4:	8037cc80 	call	8037cc8 <alt_putchar>
+ 8037ae8:	00006806 	br	8037c8c <alt_printf+0x1f0>
+        }
+        else
+        {
+            /* Get format character.  If none     */
+            /* available, processing is complete. */
+            if ((c = *w++) != 0)
+ 8037aec:	e0bfff17 	ldw	r2,-4(fp)
+ 8037af0:	10c00044 	addi	r3,r2,1
+ 8037af4:	e0ffff15 	stw	r3,-4(fp)
+ 8037af8:	10800003 	ldbu	r2,0(r2)
+ 8037afc:	e0bffec5 	stb	r2,-5(fp)
+ 8037b00:	e0bffec7 	ldb	r2,-5(fp)
+ 8037b04:	10006926 	beq	r2,zero,8037cac <alt_printf+0x210>
+            {
+                if (c == '%')
+ 8037b08:	e0bffec7 	ldb	r2,-5(fp)
+ 8037b0c:	10800958 	cmpnei	r2,r2,37
+ 8037b10:	1000041e 	bne	r2,zero,8037b24 <alt_printf+0x88>
+                {
+                    /* Process "%" escape sequence. */
+                    alt_putchar(c);
+ 8037b14:	e0bffec7 	ldb	r2,-5(fp)
+ 8037b18:	1009883a 	mov	r4,r2
+ 8037b1c:	8037cc80 	call	8037cc8 <alt_putchar>
+ 8037b20:	00005a06 	br	8037c8c <alt_printf+0x1f0>
+                } 
+                else if (c == 'c')
+ 8037b24:	e0bffec7 	ldb	r2,-5(fp)
+ 8037b28:	108018d8 	cmpnei	r2,r2,99
+ 8037b2c:	1000081e 	bne	r2,zero,8037b50 <alt_printf+0xb4>
+                {
+                    int v = va_arg(args, int);
+ 8037b30:	e0bff817 	ldw	r2,-32(fp)
+ 8037b34:	10c00104 	addi	r3,r2,4
+ 8037b38:	e0fff815 	stw	r3,-32(fp)
+ 8037b3c:	10800017 	ldw	r2,0(r2)
+ 8037b40:	e0bffb15 	stw	r2,-20(fp)
+                    alt_putchar(v);
+ 8037b44:	e13ffb17 	ldw	r4,-20(fp)
+ 8037b48:	8037cc80 	call	8037cc8 <alt_putchar>
+ 8037b4c:	00004f06 	br	8037c8c <alt_printf+0x1f0>
+                }
+                else if (c == 'x')
+ 8037b50:	e0bffec7 	ldb	r2,-5(fp)
+ 8037b54:	10801e18 	cmpnei	r2,r2,120
+ 8037b58:	1000341e 	bne	r2,zero,8037c2c <alt_printf+0x190>
+                {
+                    /* Process hexadecimal number format. */
+                    unsigned long v = va_arg(args, unsigned long);
+ 8037b5c:	e0bff817 	ldw	r2,-32(fp)
+ 8037b60:	10c00104 	addi	r3,r2,4
+ 8037b64:	e0fff815 	stw	r3,-32(fp)
+ 8037b68:	10800017 	ldw	r2,0(r2)
+ 8037b6c:	e0bffa15 	stw	r2,-24(fp)
+                    unsigned long digit;
+                    int digit_shift;
+
+                    /* If the number value is zero, just print and continue. */
+                    if (v == 0)
+ 8037b70:	e0bffa17 	ldw	r2,-24(fp)
+ 8037b74:	1000031e 	bne	r2,zero,8037b84 <alt_printf+0xe8>
+                    {
+                        alt_putchar('0');
+ 8037b78:	01000c04 	movi	r4,48
+ 8037b7c:	8037cc80 	call	8037cc8 <alt_putchar>
+                        continue;
+ 8037b80:	00004206 	br	8037c8c <alt_printf+0x1f0>
+                    }
+
+                    /* Find first non-zero digit. */
+                    digit_shift = 28;
+ 8037b84:	00800704 	movi	r2,28
+ 8037b88:	e0bffd15 	stw	r2,-12(fp)
+                    while (!(v & (0xF << digit_shift)))
+ 8037b8c:	00000306 	br	8037b9c <alt_printf+0x100>
+                        digit_shift -= 4;
+ 8037b90:	e0bffd17 	ldw	r2,-12(fp)
+ 8037b94:	10bfff04 	addi	r2,r2,-4
+ 8037b98:	e0bffd15 	stw	r2,-12(fp)
+                    while (!(v & (0xF << digit_shift)))
+ 8037b9c:	00c003c4 	movi	r3,15
+ 8037ba0:	e0bffd17 	ldw	r2,-12(fp)
+ 8037ba4:	1884983a 	sll	r2,r3,r2
+ 8037ba8:	1007883a 	mov	r3,r2
+ 8037bac:	e0bffa17 	ldw	r2,-24(fp)
+ 8037bb0:	1884703a 	and	r2,r3,r2
+ 8037bb4:	103ff626 	beq	r2,zero,8037b90 <alt_printf+0xf4>
+
+                    /* Print digits. */
+                    for (; digit_shift >= 0; digit_shift -= 4)
+ 8037bb8:	00001906 	br	8037c20 <alt_printf+0x184>
+                    {
+                        digit = (v & (0xF << digit_shift)) >> digit_shift;
+ 8037bbc:	00c003c4 	movi	r3,15
+ 8037bc0:	e0bffd17 	ldw	r2,-12(fp)
+ 8037bc4:	1884983a 	sll	r2,r3,r2
+ 8037bc8:	1007883a 	mov	r3,r2
+ 8037bcc:	e0bffa17 	ldw	r2,-24(fp)
+ 8037bd0:	1886703a 	and	r3,r3,r2
+ 8037bd4:	e0bffd17 	ldw	r2,-12(fp)
+ 8037bd8:	1884d83a 	srl	r2,r3,r2
+ 8037bdc:	e0bff915 	stw	r2,-28(fp)
+                        if (digit <= 9)
+ 8037be0:	e0bff917 	ldw	r2,-28(fp)
+ 8037be4:	108002a8 	cmpgeui	r2,r2,10
+ 8037be8:	1000041e 	bne	r2,zero,8037bfc <alt_printf+0x160>
+                            c = '0' + digit;
+ 8037bec:	e0bff917 	ldw	r2,-28(fp)
+ 8037bf0:	10800c04 	addi	r2,r2,48
+ 8037bf4:	e0bffec5 	stb	r2,-5(fp)
+ 8037bf8:	00000306 	br	8037c08 <alt_printf+0x16c>
+                        else
+                            c = 'a' + digit - 10;
+ 8037bfc:	e0bff917 	ldw	r2,-28(fp)
+ 8037c00:	108015c4 	addi	r2,r2,87
+ 8037c04:	e0bffec5 	stb	r2,-5(fp)
+                        alt_putchar(c);
+ 8037c08:	e0bffec7 	ldb	r2,-5(fp)
+ 8037c0c:	1009883a 	mov	r4,r2
+ 8037c10:	8037cc80 	call	8037cc8 <alt_putchar>
+                    for (; digit_shift >= 0; digit_shift -= 4)
+ 8037c14:	e0bffd17 	ldw	r2,-12(fp)
+ 8037c18:	10bfff04 	addi	r2,r2,-4
+ 8037c1c:	e0bffd15 	stw	r2,-12(fp)
+ 8037c20:	e0bffd17 	ldw	r2,-12(fp)
+ 8037c24:	103fe50e 	bge	r2,zero,8037bbc <alt_printf+0x120>
+ 8037c28:	00001806 	br	8037c8c <alt_printf+0x1f0>
+                    }
+                }
+                else if (c == 's')
+ 8037c2c:	e0bffec7 	ldb	r2,-5(fp)
+ 8037c30:	10801cd8 	cmpnei	r2,r2,115
+ 8037c34:	1000151e 	bne	r2,zero,8037c8c <alt_printf+0x1f0>
+                {
+                    /* Process string format. */
+                    char *s = va_arg(args, char *);
+ 8037c38:	e0bff817 	ldw	r2,-32(fp)
+ 8037c3c:	10c00104 	addi	r3,r2,4
+ 8037c40:	e0fff815 	stw	r3,-32(fp)
+ 8037c44:	10800017 	ldw	r2,0(r2)
+ 8037c48:	e0bffc15 	stw	r2,-16(fp)
+
+                    while(*s)
+ 8037c4c:	00000906 	br	8037c74 <alt_printf+0x1d8>
+                      alt_putchar(*s++);
+ 8037c50:	e0bffc17 	ldw	r2,-16(fp)
+ 8037c54:	10c00044 	addi	r3,r2,1
+ 8037c58:	e0fffc15 	stw	r3,-16(fp)
+ 8037c5c:	10800003 	ldbu	r2,0(r2)
+ 8037c60:	10803fcc 	andi	r2,r2,255
+ 8037c64:	1080201c 	xori	r2,r2,128
+ 8037c68:	10bfe004 	addi	r2,r2,-128
+ 8037c6c:	1009883a 	mov	r4,r2
+ 8037c70:	8037cc80 	call	8037cc8 <alt_putchar>
+                    while(*s)
+ 8037c74:	e0bffc17 	ldw	r2,-16(fp)
+ 8037c78:	10800003 	ldbu	r2,0(r2)
+ 8037c7c:	10803fcc 	andi	r2,r2,255
+ 8037c80:	1080201c 	xori	r2,r2,128
+ 8037c84:	10bfe004 	addi	r2,r2,-128
+ 8037c88:	103ff11e 	bne	r2,zero,8037c50 <alt_printf+0x1b4>
+    while ((c = *w++) != 0)
+ 8037c8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037c90:	10c00044 	addi	r3,r2,1
+ 8037c94:	e0ffff15 	stw	r3,-4(fp)
+ 8037c98:	10800003 	ldbu	r2,0(r2)
+ 8037c9c:	e0bffec5 	stb	r2,-5(fp)
+ 8037ca0:	e0bffec7 	ldb	r2,-5(fp)
+ 8037ca4:	103f8a1e 	bne	r2,zero,8037ad0 <alt_printf+0x34>
+        }
+    }
+#ifdef ALT_SEMIHOSTING
+    alt_putbufflush();
+#endif
+}
+ 8037ca8:	00000106 	br	8037cb0 <alt_printf+0x214>
+                break;
+ 8037cac:	0001883a 	nop
+}
+ 8037cb0:	0001883a 	nop
+ 8037cb4:	e037883a 	mov	sp,fp
+ 8037cb8:	dfc00117 	ldw	ra,4(sp)
+ 8037cbc:	df000017 	ldw	fp,0(sp)
+ 8037cc0:	dec00504 	addi	sp,sp,20
+ 8037cc4:	f800283a 	ret
+
+08037cc8 <alt_putchar>:
+ * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available.
+ * Otherwise, uses newlib provided putchar() routine.
+ */
+int 
+alt_putchar(int c)
+{
+ 8037cc8:	defffd04 	addi	sp,sp,-12
+ 8037ccc:	dfc00215 	stw	ra,8(sp)
+ 8037cd0:	df000115 	stw	fp,4(sp)
+ 8037cd4:	df000104 	addi	fp,sp,4
+ 8037cd8:	e13fff15 	stw	r4,-4(fp)
+    if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) {
+        return -1;
+    }
+    return c;
+#else
+    return putchar(c);
+ 8037cdc:	e13fff17 	ldw	r4,-4(fp)
+ 8037ce0:	8002cb80 	call	8002cb8 <putchar>
+#endif
+#endif
+}
+ 8037ce4:	e037883a 	mov	sp,fp
+ 8037ce8:	dfc00117 	ldw	ra,4(sp)
+ 8037cec:	df000017 	ldw	fp,0(sp)
+ 8037cf0:	dec00204 	addi	sp,sp,8
+ 8037cf4:	f800283a 	ret
+
+08037cf8 <alt_get_errno>:
+{
+ 8037cf8:	defffe04 	addi	sp,sp,-8
+ 8037cfc:	dfc00115 	stw	ra,4(sp)
+ 8037d00:	df000015 	stw	fp,0(sp)
+ 8037d04:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 8037d08:	d0a02717 	ldw	r2,-32612(gp)
+ 8037d0c:	10000326 	beq	r2,zero,8037d1c <alt_get_errno+0x24>
+ 8037d10:	d0a02717 	ldw	r2,-32612(gp)
+ 8037d14:	103ee83a 	callr	r2
+ 8037d18:	00000106 	br	8037d20 <alt_get_errno+0x28>
+ 8037d1c:	d0a04204 	addi	r2,gp,-32504
+}
+ 8037d20:	e037883a 	mov	sp,fp
+ 8037d24:	dfc00117 	ldw	ra,4(sp)
+ 8037d28:	df000017 	ldw	fp,0(sp)
+ 8037d2c:	dec00204 	addi	sp,sp,8
+ 8037d30:	f800283a 	ret
+
+08037d34 <alt_read>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_READ (int file, void *ptr, size_t len)
+{
+ 8037d34:	defff904 	addi	sp,sp,-28
+ 8037d38:	dfc00615 	stw	ra,24(sp)
+ 8037d3c:	df000515 	stw	fp,20(sp)
+ 8037d40:	df000504 	addi	fp,sp,20
+ 8037d44:	e13ffd15 	stw	r4,-12(fp)
+ 8037d48:	e17ffc15 	stw	r5,-16(fp)
+ 8037d4c:	e1bffb15 	stw	r6,-20(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 8037d50:	e0bffd17 	ldw	r2,-12(fp)
+ 8037d54:	10000616 	blt	r2,zero,8037d70 <alt_read+0x3c>
+ 8037d58:	e0bffd17 	ldw	r2,-12(fp)
+ 8037d5c:	10c00324 	muli	r3,r2,12
+ 8037d60:	00820174 	movhi	r2,2053
+ 8037d64:	10b21a04 	addi	r2,r2,-14232
+ 8037d68:	1885883a 	add	r2,r3,r2
+ 8037d6c:	00000106 	br	8037d74 <alt_read+0x40>
+ 8037d70:	0005883a 	mov	r2,zero
+ 8037d74:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+ 8037d78:	e0bfff17 	ldw	r2,-4(fp)
+ 8037d7c:	10002226 	beq	r2,zero,8037e08 <alt_read+0xd4>
+     * If the file has not been opened with read access, or if the driver does
+     * not provide an implementation of read(), generate an error. Otherwise
+     * call the drivers read() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
+ 8037d80:	e0bfff17 	ldw	r2,-4(fp)
+ 8037d84:	10800217 	ldw	r2,8(r2)
+ 8037d88:	108000cc 	andi	r2,r2,3
+ 8037d8c:	10800060 	cmpeqi	r2,r2,1
+ 8037d90:	1000181e 	bne	r2,zero,8037df4 <alt_read+0xc0>
+        (fd->dev->read))
+ 8037d94:	e0bfff17 	ldw	r2,-4(fp)
+ 8037d98:	10800017 	ldw	r2,0(r2)
+ 8037d9c:	10800517 	ldw	r2,20(r2)
+    if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
+ 8037da0:	10001426 	beq	r2,zero,8037df4 <alt_read+0xc0>
+      {
+        if ((rval = fd->dev->read(fd, ptr, len)) < 0)
+ 8037da4:	e0bfff17 	ldw	r2,-4(fp)
+ 8037da8:	10800017 	ldw	r2,0(r2)
+ 8037dac:	10800517 	ldw	r2,20(r2)
+ 8037db0:	e0fffb17 	ldw	r3,-20(fp)
+ 8037db4:	180d883a 	mov	r6,r3
+ 8037db8:	e17ffc17 	ldw	r5,-16(fp)
+ 8037dbc:	e13fff17 	ldw	r4,-4(fp)
+ 8037dc0:	103ee83a 	callr	r2
+ 8037dc4:	e0bffe15 	stw	r2,-8(fp)
+ 8037dc8:	e0bffe17 	ldw	r2,-8(fp)
+ 8037dcc:	1000070e 	bge	r2,zero,8037dec <alt_read+0xb8>
+        {
+          ALT_ERRNO = -rval;
+ 8037dd0:	8037cf80 	call	8037cf8 <alt_get_errno>
+ 8037dd4:	1007883a 	mov	r3,r2
+ 8037dd8:	e0bffe17 	ldw	r2,-8(fp)
+ 8037ddc:	0085c83a 	sub	r2,zero,r2
+ 8037de0:	18800015 	stw	r2,0(r3)
+          return -1;
+ 8037de4:	00bfffc4 	movi	r2,-1
+ 8037de8:	00000c06 	br	8037e1c <alt_read+0xe8>
+        }
+        return rval;
+ 8037dec:	e0bffe17 	ldw	r2,-8(fp)
+ 8037df0:	00000a06 	br	8037e1c <alt_read+0xe8>
+      }
+      else
+      {
+        ALT_ERRNO = EACCES;
+ 8037df4:	8037cf80 	call	8037cf8 <alt_get_errno>
+ 8037df8:	1007883a 	mov	r3,r2
+ 8037dfc:	00800344 	movi	r2,13
+ 8037e00:	18800015 	stw	r2,0(r3)
+ 8037e04:	00000406 	br	8037e18 <alt_read+0xe4>
+      }
+    }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+ 8037e08:	8037cf80 	call	8037cf8 <alt_get_errno>
+ 8037e0c:	1007883a 	mov	r3,r2
+ 8037e10:	00801444 	movi	r2,81
+ 8037e14:	18800015 	stw	r2,0(r3)
+  }
+  return -1;
+ 8037e18:	00bfffc4 	movi	r2,-1
+}
+ 8037e1c:	e037883a 	mov	sp,fp
+ 8037e20:	dfc00117 	ldw	ra,4(sp)
+ 8037e24:	df000017 	ldw	fp,0(sp)
+ 8037e28:	dec00204 	addi	sp,sp,8
+ 8037e2c:	f800283a 	ret
+
+08037e30 <alt_release_fd>:
+ * File descriptors correcponding to standard in, standard out and standard 
+ * error cannont be released backed to the pool. They are always reserved.
+ */
+
+void alt_release_fd (int fd)
+{
+ 8037e30:	defffe04 	addi	sp,sp,-8
+ 8037e34:	df000115 	stw	fp,4(sp)
+ 8037e38:	df000104 	addi	fp,sp,4
+ 8037e3c:	e13fff15 	stw	r4,-4(fp)
+  if (fd > 2)
+ 8037e40:	e0bfff17 	ldw	r2,-4(fp)
+ 8037e44:	108000d0 	cmplti	r2,r2,3
+ 8037e48:	10000a1e 	bne	r2,zero,8037e74 <alt_release_fd+0x44>
+  {
+    alt_fd_list[fd].fd_flags = 0;
+ 8037e4c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037e50:	10c00324 	muli	r3,r2,12
+ 8037e54:	00820174 	movhi	r2,2053
+ 8037e58:	1885883a 	add	r2,r3,r2
+ 8037e5c:	10321c15 	stw	zero,-14224(r2)
+    alt_fd_list[fd].dev      = 0;
+ 8037e60:	e0bfff17 	ldw	r2,-4(fp)
+ 8037e64:	10c00324 	muli	r3,r2,12
+ 8037e68:	00820174 	movhi	r2,2053
+ 8037e6c:	1885883a 	add	r2,r3,r2
+ 8037e70:	10321a15 	stw	zero,-14232(r2)
+  }
+}
+ 8037e74:	0001883a 	nop
+ 8037e78:	e037883a 	mov	sp,fp
+ 8037e7c:	df000017 	ldw	fp,0(sp)
+ 8037e80:	dec00104 	addi	sp,sp,4
+ 8037e84:	f800283a 	ret
+
+08037e88 <alt_remap_cached>:
+ * Return a pointer that should be used to access the cached memory.
+ */
+
+void* 
+alt_remap_cached(volatile void* ptr, alt_u32 len)
+{
+ 8037e88:	defffd04 	addi	sp,sp,-12
+ 8037e8c:	df000215 	stw	fp,8(sp)
+ 8037e90:	df000204 	addi	fp,sp,8
+ 8037e94:	e13fff15 	stw	r4,-4(fp)
+ 8037e98:	e17ffe15 	stw	r5,-8(fp)
+#if ALT_CPU_DCACHE_SIZE > 0
+#ifdef ALT_CPU_DCACHE_BYPASS_MASK
+  return (void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK);
+ 8037e9c:	e0ffff17 	ldw	r3,-4(fp)
+ 8037ea0:	00a00034 	movhi	r2,32768
+ 8037ea4:	10bfffc4 	addi	r2,r2,-1
+ 8037ea8:	1884703a 	and	r2,r3,r2
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Nothing needs to be done to the pointer. */
+  return (void*) ptr;
+#endif /* No data cache */
+}
+ 8037eac:	e037883a 	mov	sp,fp
+ 8037eb0:	df000017 	ldw	fp,0(sp)
+ 8037eb4:	dec00104 	addi	sp,sp,4
+ 8037eb8:	f800283a 	ret
+
+08037ebc <alt_alarm_stop>:
+ * alarms. Alternatively an alarm can unregister itself by returning zero when 
+ * the alarm executes.
+ */
+
+void alt_alarm_stop (alt_alarm* alarm)
+{
+ 8037ebc:	defffa04 	addi	sp,sp,-24
+ 8037ec0:	df000515 	stw	fp,20(sp)
+ 8037ec4:	df000504 	addi	fp,sp,20
+ 8037ec8:	e13ffb15 	stw	r4,-20(fp)
+  NIOS2_READ_STATUS (context);
+ 8037ecc:	0005303a 	rdctl	r2,status
+ 8037ed0:	e0bffc15 	stw	r2,-16(fp)
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+ 8037ed4:	e0fffc17 	ldw	r3,-16(fp)
+ 8037ed8:	00bfff84 	movi	r2,-2
+ 8037edc:	1884703a 	and	r2,r3,r2
+ 8037ee0:	1001703a 	wrctl	status,r2
+  return context;
+ 8037ee4:	e0bffc17 	ldw	r2,-16(fp)
+  alt_irq_context irq_context;
+
+  irq_context = alt_irq_disable_all();
+ 8037ee8:	e0bfff15 	stw	r2,-4(fp)
+  alt_llist_remove (&alarm->llist);
+ 8037eec:	e0bffb17 	ldw	r2,-20(fp)
+ 8037ef0:	e0bffd15 	stw	r2,-12(fp)
+ * input argument is the element to remove.
+ */
+     
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry)
+{
+  entry->next->previous = entry->previous;
+ 8037ef4:	e0bffd17 	ldw	r2,-12(fp)
+ 8037ef8:	10800017 	ldw	r2,0(r2)
+ 8037efc:	e0fffd17 	ldw	r3,-12(fp)
+ 8037f00:	18c00117 	ldw	r3,4(r3)
+ 8037f04:	10c00115 	stw	r3,4(r2)
+  entry->previous->next = entry->next;
+ 8037f08:	e0bffd17 	ldw	r2,-12(fp)
+ 8037f0c:	10800117 	ldw	r2,4(r2)
+ 8037f10:	e0fffd17 	ldw	r3,-12(fp)
+ 8037f14:	18c00017 	ldw	r3,0(r3)
+ 8037f18:	10c00015 	stw	r3,0(r2)
+  /* 
+   * Set the entry to point to itself, so that any further calls to
+   * alt_llist_remove() are harmless.
+   */
+
+  entry->previous = entry;
+ 8037f1c:	e0bffd17 	ldw	r2,-12(fp)
+ 8037f20:	e0fffd17 	ldw	r3,-12(fp)
+ 8037f24:	10c00115 	stw	r3,4(r2)
+  entry->next     = entry;
+ 8037f28:	e0bffd17 	ldw	r2,-12(fp)
+ 8037f2c:	e0fffd17 	ldw	r3,-12(fp)
+ 8037f30:	10c00015 	stw	r3,0(r2)
+ 8037f34:	e0bfff17 	ldw	r2,-4(fp)
+ 8037f38:	e0bffe15 	stw	r2,-8(fp)
+  NIOS2_WRITE_STATUS (context);
+ 8037f3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8037f40:	1001703a 	wrctl	status,r2
+  alt_irq_enable_all (irq_context);
+}
+ 8037f44:	0001883a 	nop
+ 8037f48:	e037883a 	mov	sp,fp
+ 8037f4c:	df000017 	ldw	fp,0(sp)
+ 8037f50:	dec00104 	addi	sp,sp,4
+ 8037f54:	f800283a 	ret
+
+08037f58 <alt_tick>:
+ * 
+ * alt_tick() is expected to run at interrupt level.
+ */
+
+void alt_tick (void)
+{
+ 8037f58:	defffb04 	addi	sp,sp,-20
+ 8037f5c:	dfc00415 	stw	ra,16(sp)
+ 8037f60:	df000315 	stw	fp,12(sp)
+ 8037f64:	df000304 	addi	fp,sp,12
+  alt_alarm* next;
+  alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next;
+ 8037f68:	d0a02917 	ldw	r2,-32604(gp)
+ 8037f6c:	e0bfff15 	stw	r2,-4(fp)
+
+  alt_u32    next_callback;
+
+  /* update the tick counter */
+
+  _alt_nticks++;
+ 8037f70:	d0a08e17 	ldw	r2,-32200(gp)
+ 8037f74:	10800044 	addi	r2,r2,1
+ 8037f78:	d0a08e15 	stw	r2,-32200(gp)
+
+  /* process the registered callbacks */
+
+  while (alarm != (alt_alarm*) &alt_alarm_list)
+ 8037f7c:	00002e06 	br	8038038 <alt_tick+0xe0>
+  {
+    next = (alt_alarm*) alarm->llist.next;
+ 8037f80:	e0bfff17 	ldw	r2,-4(fp)
+ 8037f84:	10800017 	ldw	r2,0(r2)
+ 8037f88:	e0bffe15 	stw	r2,-8(fp)
+    /* 
+     * Upon the tick-counter rolling over it is safe to clear the 
+     * roll-over flag; once the flag is cleared this (or subsequnt)
+     * tick events are enabled to generate an alarm event. 
+     */
+    if ((alarm->rollover) && (_alt_nticks == 0))
+ 8037f8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8037f90:	10800403 	ldbu	r2,16(r2)
+ 8037f94:	10803fcc 	andi	r2,r2,255
+ 8037f98:	10000426 	beq	r2,zero,8037fac <alt_tick+0x54>
+ 8037f9c:	d0a08e17 	ldw	r2,-32200(gp)
+ 8037fa0:	1000021e 	bne	r2,zero,8037fac <alt_tick+0x54>
+    {
+      alarm->rollover = 0;
+ 8037fa4:	e0bfff17 	ldw	r2,-4(fp)
+ 8037fa8:	10000405 	stb	zero,16(r2)
+    }
+    
+    /* if the alarm period has expired, make the callback */    
+    if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0))
+ 8037fac:	e0bfff17 	ldw	r2,-4(fp)
+ 8037fb0:	10800217 	ldw	r2,8(r2)
+ 8037fb4:	d0e08e17 	ldw	r3,-32200(gp)
+ 8037fb8:	18801d36 	bltu	r3,r2,8038030 <alt_tick+0xd8>
+ 8037fbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8037fc0:	10800403 	ldbu	r2,16(r2)
+ 8037fc4:	10803fcc 	andi	r2,r2,255
+ 8037fc8:	1000191e 	bne	r2,zero,8038030 <alt_tick+0xd8>
+    {
+      next_callback = alarm->callback (alarm->context);
+ 8037fcc:	e0bfff17 	ldw	r2,-4(fp)
+ 8037fd0:	10800317 	ldw	r2,12(r2)
+ 8037fd4:	e0ffff17 	ldw	r3,-4(fp)
+ 8037fd8:	18c00517 	ldw	r3,20(r3)
+ 8037fdc:	1809883a 	mov	r4,r3
+ 8037fe0:	103ee83a 	callr	r2
+ 8037fe4:	e0bffd15 	stw	r2,-12(fp)
+
+      /* deactivate the alarm if the return value is zero */
+
+      if (next_callback == 0)
+ 8037fe8:	e0bffd17 	ldw	r2,-12(fp)
+ 8037fec:	1000031e 	bne	r2,zero,8037ffc <alt_tick+0xa4>
+      {
+        alt_alarm_stop (alarm);
+ 8037ff0:	e13fff17 	ldw	r4,-4(fp)
+ 8037ff4:	8037ebc0 	call	8037ebc <alt_alarm_stop>
+ 8037ff8:	00000d06 	br	8038030 <alt_tick+0xd8>
+      }
+      else
+      {
+        alarm->time += next_callback;
+ 8037ffc:	e0bfff17 	ldw	r2,-4(fp)
+ 8038000:	10c00217 	ldw	r3,8(r2)
+ 8038004:	e0bffd17 	ldw	r2,-12(fp)
+ 8038008:	1887883a 	add	r3,r3,r2
+ 803800c:	e0bfff17 	ldw	r2,-4(fp)
+ 8038010:	10c00215 	stw	r3,8(r2)
+        /* 
+         * If the desired alarm time causes a roll-over, set the rollover
+         * flag. This will prevent the subsequent tick event from causing
+         * an alarm too early.
+         */
+        if(alarm->time < _alt_nticks)
+ 8038014:	e0bfff17 	ldw	r2,-4(fp)
+ 8038018:	10c00217 	ldw	r3,8(r2)
+ 803801c:	d0a08e17 	ldw	r2,-32200(gp)
+ 8038020:	1880032e 	bgeu	r3,r2,8038030 <alt_tick+0xd8>
+        {
+          alarm->rollover = 1;
+ 8038024:	e0bfff17 	ldw	r2,-4(fp)
+ 8038028:	00c00044 	movi	r3,1
+ 803802c:	10c00405 	stb	r3,16(r2)
+        }
+      }
+    }
+    alarm = next;
+ 8038030:	e0bffe17 	ldw	r2,-8(fp)
+ 8038034:	e0bfff15 	stw	r2,-4(fp)
+  while (alarm != (alt_alarm*) &alt_alarm_list)
+ 8038038:	e0ffff17 	ldw	r3,-4(fp)
+ 803803c:	d0a02904 	addi	r2,gp,-32604
+ 8038040:	18bfcf1e 	bne	r3,r2,8037f80 <alt_tick+0x28>
+
+  /* 
+   * Update the operating system specific timer facilities.
+   */
+
+  ALT_OS_TIME_TICK();
+ 8038044:	8010ad80 	call	8010ad8 <OSTimeTick>
+}
+ 8038048:	0001883a 	nop
+ 803804c:	e037883a 	mov	sp,fp
+ 8038050:	dfc00117 	ldw	ra,4(sp)
+ 8038054:	df000017 	ldw	fp,0(sp)
+ 8038058:	dec00204 	addi	sp,sp,8
+ 803805c:	f800283a 	ret
+
+08038060 <alt_uncached_free>:
+ * Free a block of uncached memory.
+ */
+
+void 
+alt_uncached_free(volatile void* ptr)
+{
+ 8038060:	defffd04 	addi	sp,sp,-12
+ 8038064:	dfc00215 	stw	ra,8(sp)
+ 8038068:	df000115 	stw	fp,4(sp)
+ 803806c:	df000104 	addi	fp,sp,4
+ 8038070:	e13fff15 	stw	r4,-4(fp)
+#if ALT_CPU_DCACHE_SIZE > 0
+#ifdef ALT_CPU_DCACHE_BYPASS_MASK
+  free((void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK));
+ 8038074:	e0ffff17 	ldw	r3,-4(fp)
+ 8038078:	00a00034 	movhi	r2,32768
+ 803807c:	10bfffc4 	addi	r2,r2,-1
+ 8038080:	1884703a 	and	r2,r3,r2
+ 8038084:	1009883a 	mov	r4,r2
+ 8038088:	8042ca80 	call	8042ca8 <free>
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Nothing needs to be done to the pointer. */
+  free((void*)ptr);
+#endif /* No data cache */
+}
+ 803808c:	0001883a 	nop
+ 8038090:	e037883a 	mov	sp,fp
+ 8038094:	dfc00117 	ldw	ra,4(sp)
+ 8038098:	df000017 	ldw	fp,0(sp)
+ 803809c:	dec00204 	addi	sp,sp,8
+ 80380a0:	f800283a 	ret
+
+080380a4 <alt_uncached_malloc>:
+ * Return pointer to the block of memory or NULL if can't allocate it.
+ */
+
+volatile void* 
+alt_uncached_malloc(size_t size)
+{
+ 80380a4:	defffa04 	addi	sp,sp,-24
+ 80380a8:	dfc00515 	stw	ra,20(sp)
+ 80380ac:	df000415 	stw	fp,16(sp)
+ 80380b0:	df000404 	addi	fp,sp,16
+ 80380b4:	e13ffc15 	stw	r4,-16(fp)
+
+  void* ptr;
+
+  /* Round up size to an integer number of data cache lines. Required to guarantee that
+   * cacheable and non-cacheable data won't be mixed on the same cache line. */ 
+  const size_t num_lines = (size + ALT_CPU_DCACHE_LINE_SIZE - 1) / ALT_CPU_DCACHE_LINE_SIZE;
+ 80380b8:	e0bffc17 	ldw	r2,-16(fp)
+ 80380bc:	108007c4 	addi	r2,r2,31
+ 80380c0:	1004d17a 	srli	r2,r2,5
+ 80380c4:	e0bfff15 	stw	r2,-4(fp)
+  const size_t aligned_size = num_lines * ALT_CPU_DCACHE_LINE_SIZE;
+ 80380c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80380cc:	1004917a 	slli	r2,r2,5
+ 80380d0:	e0bffe15 	stw	r2,-8(fp)
+
+  /* Use memalign() Newlib routine to allocate starting on a data cache aligned address.
+   * Required to guarantee that cacheable and non-cacheable data won't be mixed on the
+   * same cache line. */ 
+  ptr = memalign(ALT_CPU_DCACHE_LINE_SIZE, aligned_size);
+ 80380d4:	e17ffe17 	ldw	r5,-8(fp)
+ 80380d8:	01000804 	movi	r4,32
+ 80380dc:	8042af00 	call	8042af0 <memalign>
+ 80380e0:	e0bffd15 	stw	r2,-12(fp)
+
+  if (ptr == NULL) {
+ 80380e4:	e0bffd17 	ldw	r2,-12(fp)
+ 80380e8:	1000021e 	bne	r2,zero,80380f4 <alt_uncached_malloc+0x50>
+    return NULL; /* Out of memory */
+ 80380ec:	0005883a 	mov	r2,zero
+ 80380f0:	00000506 	br	8038108 <alt_uncached_malloc+0x64>
+  }
+
+  /* Ensure that the memory region isn't in the data cache. */
+  alt_dcache_flush(ptr, aligned_size);
+ 80380f4:	e17ffe17 	ldw	r5,-8(fp)
+ 80380f8:	e13ffd17 	ldw	r4,-12(fp)
+ 80380fc:	80371c00 	call	80371c0 <alt_dcache_flush>
+
+  return (volatile void*) (((alt_u32)ptr) | ALT_CPU_DCACHE_BYPASS_MASK);
+ 8038100:	e0bffd17 	ldw	r2,-12(fp)
+ 8038104:	10a00034 	orhi	r2,r2,32768
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Just use regular malloc. */
+  return malloc(size);
+#endif /* No data cache */
+}
+ 8038108:	e037883a 	mov	sp,fp
+ 803810c:	dfc00117 	ldw	ra,4(sp)
+ 8038110:	df000017 	ldw	fp,0(sp)
+ 8038114:	dec00204 	addi	sp,sp,8
+ 8038118:	f800283a 	ret
+
+0803811c <usleep>:
+#if defined (__GNUC__) && __GNUC__ >= 4
+int ALT_USLEEP (useconds_t us)
+#else
+unsigned int ALT_USLEEP (unsigned int us)
+#endif
+{
+ 803811c:	defffa04 	addi	sp,sp,-24
+ 8038120:	dfc00515 	stw	ra,20(sp)
+ 8038124:	df000415 	stw	fp,16(sp)
+ 8038128:	dc000315 	stw	r16,12(sp)
+ 803812c:	df000404 	addi	fp,sp,16
+ 8038130:	e13ffc15 	stw	r4,-16(fp)
+   * If the O/S hasn't started yet, then we delay using a busy loop, rather than
+   * OSTimeDly (since this would fail). The use of a busy loop is acceptable,
+   * since the system is still running in a single-threaded mode.
+   */ 
+
+  if (OSRunning == OS_FALSE)
+ 8038134:	d0a04b43 	ldbu	r2,-32467(gp)
+ 8038138:	10803fcc 	andi	r2,r2,255
+ 803813c:	1000031e 	bne	r2,zero,803814c <usleep+0x30>
+  {
+    return alt_busy_sleep (us);
+ 8038140:	e13ffc17 	ldw	r4,-16(fp)
+ 8038144:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+ 8038148:	00003306 	br	8038218 <usleep+0xfc>
+  return _alt_tick_rate;
+ 803814c:	d0a08d17 	ldw	r2,-32204(gp)
+
+  /* 
+   * Calculate the number of whole system clock ticks to delay.
+   */
+
+  tick_rate = alt_ticks_per_second ();
+ 8038150:	e0bffd15 	stw	r2,-12(fp)
+  ticks     = (us/ALT_US)* tick_rate + ((us%ALT_US)*tick_rate)/ALT_US;
+ 8038154:	e0bffc17 	ldw	r2,-16(fp)
+ 8038158:	014003f4 	movhi	r5,15
+ 803815c:	29509004 	addi	r5,r5,16960
+ 8038160:	1009883a 	mov	r4,r2
+ 8038164:	800cff80 	call	800cff8 <__udivsi3>
+ 8038168:	1007883a 	mov	r3,r2
+ 803816c:	e0bffd17 	ldw	r2,-12(fp)
+ 8038170:	18a1383a 	mul	r16,r3,r2
+ 8038174:	e0bffc17 	ldw	r2,-16(fp)
+ 8038178:	014003f4 	movhi	r5,15
+ 803817c:	29509004 	addi	r5,r5,16960
+ 8038180:	1009883a 	mov	r4,r2
+ 8038184:	800d05c0 	call	800d05c <__umodsi3>
+ 8038188:	1007883a 	mov	r3,r2
+ 803818c:	e0bffd17 	ldw	r2,-12(fp)
+ 8038190:	1885383a 	mul	r2,r3,r2
+ 8038194:	014003f4 	movhi	r5,15
+ 8038198:	29509004 	addi	r5,r5,16960
+ 803819c:	1009883a 	mov	r4,r2
+ 80381a0:	800cff80 	call	800cff8 <__udivsi3>
+ 80381a4:	8085883a 	add	r2,r16,r2
+ 80381a8:	e0bffe15 	stw	r2,-8(fp)
+   * OSTimeDly can only delay for a maximum of 0xffff ticks, so if the requested
+   * delay is greater than that, we need to break it down into a number of
+   * seperate delays.
+   */
+
+  while (ticks > 0xffff)
+ 80381ac:	00000706 	br	80381cc <usleep+0xb0>
+  {
+    OSTimeDly(0xffff);
+ 80381b0:	013fffd4 	movui	r4,65535
+ 80381b4:	801730c0 	call	801730c <OSTimeDly>
+    ticks -= 0xffff;
+ 80381b8:	e0fffe17 	ldw	r3,-8(fp)
+ 80381bc:	00bffff4 	movhi	r2,65535
+ 80381c0:	10800044 	addi	r2,r2,1
+ 80381c4:	1885883a 	add	r2,r3,r2
+ 80381c8:	e0bffe15 	stw	r2,-8(fp)
+  while (ticks > 0xffff)
+ 80381cc:	e0bffe17 	ldw	r2,-8(fp)
+ 80381d0:	00ffffd4 	movui	r3,65535
+ 80381d4:	18bff636 	bltu	r3,r2,80381b0 <usleep+0x94>
+  }
+
+  OSTimeDly ((INT16U) (ticks));
+ 80381d8:	e0bffe17 	ldw	r2,-8(fp)
+ 80381dc:	10bfffcc 	andi	r2,r2,65535
+ 80381e0:	1009883a 	mov	r4,r2
+ 80381e4:	801730c0 	call	801730c <OSTimeDly>
+  /*
+   * Now delay by the remainder using a busy loop. This is here in order to
+   * provide very short delays of less than one clock tick.
+   */
+
+  alt_busy_sleep (us%(ALT_US/tick_rate));  
+ 80381e8:	e17ffd17 	ldw	r5,-12(fp)
+ 80381ec:	010003f4 	movhi	r4,15
+ 80381f0:	21109004 	addi	r4,r4,16960
+ 80381f4:	800cff80 	call	800cff8 <__udivsi3>
+ 80381f8:	1007883a 	mov	r3,r2
+ 80381fc:	e0bffc17 	ldw	r2,-16(fp)
+ 8038200:	180b883a 	mov	r5,r3
+ 8038204:	1009883a 	mov	r4,r2
+ 8038208:	800d05c0 	call	800d05c <__umodsi3>
+ 803820c:	1009883a 	mov	r4,r2
+ 8038210:	8036f5c0 	call	8036f5c <alt_busy_sleep>
+
+  return 0;  
+ 8038214:	0005883a 	mov	r2,zero
+}
+ 8038218:	e6ffff04 	addi	sp,fp,-4
+ 803821c:	dfc00217 	ldw	ra,8(sp)
+ 8038220:	df000117 	ldw	fp,4(sp)
+ 8038224:	dc000017 	ldw	r16,0(sp)
+ 8038228:	dec00304 	addi	sp,sp,12
+ 803822c:	f800283a 	ret
+
+08038230 <alt_get_errno>:
+{
+ 8038230:	defffe04 	addi	sp,sp,-8
+ 8038234:	dfc00115 	stw	ra,4(sp)
+ 8038238:	df000015 	stw	fp,0(sp)
+ 803823c:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 8038240:	d0a02717 	ldw	r2,-32612(gp)
+ 8038244:	10000326 	beq	r2,zero,8038254 <alt_get_errno+0x24>
+ 8038248:	d0a02717 	ldw	r2,-32612(gp)
+ 803824c:	103ee83a 	callr	r2
+ 8038250:	00000106 	br	8038258 <alt_get_errno+0x28>
+ 8038254:	d0a04204 	addi	r2,gp,-32504
+}
+ 8038258:	e037883a 	mov	sp,fp
+ 803825c:	dfc00117 	ldw	ra,4(sp)
+ 8038260:	df000017 	ldw	fp,0(sp)
+ 8038264:	dec00204 	addi	sp,sp,8
+ 8038268:	f800283a 	ret
+
+0803826c <alt_write>:
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_WRITE (int file, const void *ptr, size_t len)
+{
+ 803826c:	defff904 	addi	sp,sp,-28
+ 8038270:	dfc00615 	stw	ra,24(sp)
+ 8038274:	df000515 	stw	fp,20(sp)
+ 8038278:	df000504 	addi	fp,sp,20
+ 803827c:	e13ffd15 	stw	r4,-12(fp)
+ 8038280:	e17ffc15 	stw	r5,-16(fp)
+ 8038284:	e1bffb15 	stw	r6,-20(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 8038288:	e0bffd17 	ldw	r2,-12(fp)
+ 803828c:	10000616 	blt	r2,zero,80382a8 <alt_write+0x3c>
+ 8038290:	e0bffd17 	ldw	r2,-12(fp)
+ 8038294:	10c00324 	muli	r3,r2,12
+ 8038298:	00820174 	movhi	r2,2053
+ 803829c:	10b21a04 	addi	r2,r2,-14232
+ 80382a0:	1885883a 	add	r2,r3,r2
+ 80382a4:	00000106 	br	80382ac <alt_write+0x40>
+ 80382a8:	0005883a 	mov	r2,zero
+ 80382ac:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+ 80382b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80382b4:	10002126 	beq	r2,zero,803833c <alt_write+0xd0>
+     * If the file has not been opened with write access, or if the driver does
+     * not provide an implementation of write(), generate an error. Otherwise
+     * call the drivers write() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write)
+ 80382b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80382bc:	10800217 	ldw	r2,8(r2)
+ 80382c0:	108000cc 	andi	r2,r2,3
+ 80382c4:	10001826 	beq	r2,zero,8038328 <alt_write+0xbc>
+ 80382c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80382cc:	10800017 	ldw	r2,0(r2)
+ 80382d0:	10800617 	ldw	r2,24(r2)
+ 80382d4:	10001426 	beq	r2,zero,8038328 <alt_write+0xbc>
+    {
+      
+      /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
+      ALT_LOG_WRITE_FUNCTION(ptr,len);
+
+      if ((rval = fd->dev->write(fd, ptr, len)) < 0)
+ 80382d8:	e0bfff17 	ldw	r2,-4(fp)
+ 80382dc:	10800017 	ldw	r2,0(r2)
+ 80382e0:	10800617 	ldw	r2,24(r2)
+ 80382e4:	e0fffb17 	ldw	r3,-20(fp)
+ 80382e8:	180d883a 	mov	r6,r3
+ 80382ec:	e17ffc17 	ldw	r5,-16(fp)
+ 80382f0:	e13fff17 	ldw	r4,-4(fp)
+ 80382f4:	103ee83a 	callr	r2
+ 80382f8:	e0bffe15 	stw	r2,-8(fp)
+ 80382fc:	e0bffe17 	ldw	r2,-8(fp)
+ 8038300:	1000070e 	bge	r2,zero,8038320 <alt_write+0xb4>
+      {
+        ALT_ERRNO = -rval;
+ 8038304:	80382300 	call	8038230 <alt_get_errno>
+ 8038308:	1007883a 	mov	r3,r2
+ 803830c:	e0bffe17 	ldw	r2,-8(fp)
+ 8038310:	0085c83a 	sub	r2,zero,r2
+ 8038314:	18800015 	stw	r2,0(r3)
+        return -1;
+ 8038318:	00bfffc4 	movi	r2,-1
+ 803831c:	00000c06 	br	8038350 <alt_write+0xe4>
+      }
+      return rval;
+ 8038320:	e0bffe17 	ldw	r2,-8(fp)
+ 8038324:	00000a06 	br	8038350 <alt_write+0xe4>
+    }
+    else
+    {
+      ALT_ERRNO = EACCES;
+ 8038328:	80382300 	call	8038230 <alt_get_errno>
+ 803832c:	1007883a 	mov	r3,r2
+ 8038330:	00800344 	movi	r2,13
+ 8038334:	18800015 	stw	r2,0(r3)
+ 8038338:	00000406 	br	803834c <alt_write+0xe0>
+    }
+  }
+  else  
+  {
+    ALT_ERRNO = EBADFD;
+ 803833c:	80382300 	call	8038230 <alt_get_errno>
+ 8038340:	1007883a 	mov	r3,r2
+ 8038344:	00801444 	movi	r2,81
+ 8038348:	18800015 	stw	r2,0(r3)
+  }
+  return -1;
+ 803834c:	00bfffc4 	movi	r2,-1
+}
+ 8038350:	e037883a 	mov	sp,fp
+ 8038354:	dfc00117 	ldw	ra,4(sp)
+ 8038358:	df000017 	ldw	fp,0(sp)
+ 803835c:	dec00204 	addi	sp,sp,8
+ 8038360:	f800283a 	ret
+
+08038364 <altera_nios2_gen2_irq_init>:
+/*
+ * To initialize the internal interrupt controller, just clear the IENABLE
+ * register so that all possible IRQs are disabled.
+ */
+void altera_nios2_gen2_irq_init(void) 
+{
+ 8038364:	deffff04 	addi	sp,sp,-4
+ 8038368:	df000015 	stw	fp,0(sp)
+ 803836c:	d839883a 	mov	fp,sp
+    NIOS2_WRITE_IENABLE(0);
+ 8038370:	000170fa 	wrctl	ienable,zero
+}
+ 8038374:	0001883a 	nop
+ 8038378:	e037883a 	mov	sp,fp
+ 803837c:	df000017 	ldw	fp,0(sp)
+ 8038380:	dec00104 	addi	sp,sp,4
+ 8038384:	f800283a 	ret
+
+08038388 <OSCtxSw>:
+
+      /* 
+       * Save the remaining registers to the stack. 
+       */
+
+      addi sp, sp, -44
+ 8038388:	defff504 	addi	sp,sp,-44
+      bltu  sp, et, .Lstack_overflow
+
+#endif
+
+#if OS_THREAD_SAFE_NEWLIB
+      ldw r3, %gprel(_impure_ptr)(gp)   /* load the pointer */
+ 803838c:	d0e00117 	ldw	r3,-32764(gp)
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+      ldw r4, %gprel(OSTCBCur)(gp)
+ 8038390:	d1205817 	ldw	r4,-32416(gp)
+
+      stw ra,  0(sp)
+ 8038394:	dfc00015 	stw	ra,0(sp)
+      stw fp,  4(sp)
+ 8038398:	df000115 	stw	fp,4(sp)
+      stw r23, 8(sp)
+ 803839c:	ddc00215 	stw	r23,8(sp)
+      stw r22, 12(sp)
+ 80383a0:	dd800315 	stw	r22,12(sp)
+      stw r21, 16(sp)
+ 80383a4:	dd400415 	stw	r21,16(sp)
+      stw r20, 20(sp)
+ 80383a8:	dd000515 	stw	r20,20(sp)
+      stw r19, 24(sp)
+ 80383ac:	dcc00615 	stw	r19,24(sp)
+      stw r18, 28(sp)
+ 80383b0:	dc800715 	stw	r18,28(sp)
+      stw r17, 32(sp)
+ 80383b4:	dc400815 	stw	r17,32(sp)
+      stw r16, 36(sp)
+ 80383b8:	dc000915 	stw	r16,36(sp)
+       * store the current value of _impure_ptr so it can be restored
+       * later; _impure_ptr is asigned on a per task basis. It is used
+       * by Newlib to achieve reentrancy.	
+       */
+
+      stw r3, 40(sp)                  /* save the impure pointer */
+ 80383bc:	d8c00a15 	stw	r3,40(sp)
+      /* 
+       * Save the current tasks stack pointer into the current tasks OS_TCB.
+       * i.e. OSTCBCur->OSTCBStkPtr = sp;
+       */
+
+      stw sp, (r4)                  /* save the stack pointer (OSTCBStkPtr */
+ 80383c0:	26c00015 	stw	sp,0(r4)
+
+      /*
+       * Call the user definable OSTaskSWHook()
+       */
+
+      call OSTaskSwHook
+ 80383c4:	80385ec0 	call	80385ec <OSTaskSwHook>
+      /*
+       * OSTCBCur = OSTCBHighRdy; 
+       * OSPrioCur = OSPrioHighRdy; 
+       */
+
+      ldw r4, %gprel(OSTCBHighRdy)(gp)
+ 80383c8:	d1205317 	ldw	r4,-32436(gp)
+      ldb r5, %gprel(OSPrioHighRdy)(gp)
+ 80383cc:	d1604d07 	ldb	r5,-32460(gp)
+
+      stw r4, %gprel(OSTCBCur)(gp)     /* set the current task to be the new task */
+ 80383d0:	d1205815 	stw	r4,-32416(gp)
+      stb r5, %gprel(OSPrioCur)(gp)    /* store the new task's priority as the current */
+ 80383d4:	d1604d45 	stb	r5,-32459(gp)
+
+      /*
+       * Set the stack pointer to point to the new task's stack
+       */
+
+      ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */
+ 80383d8:	26c00017 	ldw	sp,0(r4)
+      /*
+       * restore the value of _impure_ptr ; _impure_ptr is asigned on a 
+       * per task basis. It is used by Newlib to achieve reentrancy.	
+       */
+
+      ldw r3, 40(sp)                  /* load the new impure pointer */
+ 80383dc:	d8c00a17 	ldw	r3,40(sp)
+
+      /*
+       * Restore the saved registers for the new task.
+       */
+
+      ldw ra,  0(sp)
+ 80383e0:	dfc00017 	ldw	ra,0(sp)
+      ldw fp,  4(sp)
+ 80383e4:	df000117 	ldw	fp,4(sp)
+      ldw r23, 8(sp)
+ 80383e8:	ddc00217 	ldw	r23,8(sp)
+      ldw r22, 12(sp)
+ 80383ec:	dd800317 	ldw	r22,12(sp)
+      ldw r21, 16(sp)
+ 80383f0:	dd400417 	ldw	r21,16(sp)
+      ldw r20, 20(sp)
+ 80383f4:	dd000517 	ldw	r20,20(sp)
+      ldw r19, 24(sp)
+ 80383f8:	dcc00617 	ldw	r19,24(sp)
+      ldw r18, 28(sp)
+ 80383fc:	dc800717 	ldw	r18,28(sp)
+      ldw r17, 32(sp)
+ 8038400:	dc400817 	ldw	r17,32(sp)
+      ldw r16, 36(sp)
+ 8038404:	dc000917 	ldw	r16,36(sp)
+
+#if OS_THREAD_SAFE_NEWLIB
+
+      stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */
+ 8038408:	d0e00115 	stw	r3,-32764(gp)
+
+      stw et, %gprel(alt_stack_limit_value)(gp)
+
+#endif
+
+      addi sp, sp, 44
+ 803840c:	dec00b04 	addi	sp,sp,44
+
+      /*
+       * resume execution of the new task.
+       */
+
+      ret
+ 8038410:	f800283a 	ret
+
+08038414 <OSStartHighRdy>:
+
+      /*
+       * disable interrupts so that the scheduler doesn't run while
+       * we're initialising this task.
+       */  
+      rdctl r18, status
+ 8038414:	0025303a 	rdctl	r18,status
+      subi  r17, zero, 2   /* r17 = 0xfffffffe */
+ 8038418:	047fff84 	movi	r17,-2
+      and   r18, r18, r17
+ 803841c:	9464703a 	and	r18,r18,r17
+      wrctl status, r18
+ 8038420:	9001703a 	wrctl	status,r18
+
+      /*
+       * Call the user definable OSTaskSWHook()
+       */
+
+      call OSTaskSwHook
+ 8038424:	80385ec0 	call	80385ec <OSTaskSwHook>
+
+      /* 
+       * set OSRunning = TRUE.
+       */
+
+      movi r18, 1                    /* set r18 to the value 'TRUE' */
+ 8038428:	04800044 	movi	r18,1
+      stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */
+ 803842c:	d4a04b45 	stb	r18,-32467(gp)
+
+      /*
+       * start execution of the new task.
+       */
+
+      br 9b
+ 8038430:	003fe506 	br	80383c8 <OSCtxSw+0x40>
+
+08038434 <OSStartTsk>:
+
+OSStartTsk:
+      /* This instruction is never executed.  Its here to make the
+       * backtrace work right 
+       */
+      movi sp, 0
+ 8038434:	06c00004 	movi	sp,0
+
+      /* Enable interrupts */
+      rdctl r2, status
+ 8038438:	0005303a 	rdctl	r2,status
+      ori   r2, r2, 0x1
+ 803843c:	10800054 	ori	r2,r2,1
+      wrctl status, r2
+ 8038440:	1001703a 	wrctl	status,r2
+
+      ldw r2, 4(sp)
+ 8038444:	d8800117 	ldw	r2,4(sp)
+      ldw r4, 0(sp)
+ 8038448:	d9000017 	ldw	r4,0(sp)
+
+      addi sp, sp, 8
+ 803844c:	dec00204 	addi	sp,sp,8
+
+      callr r2
+ 8038450:	103ee83a 	callr	r2
+
+      nop
+ 8038454:	0001883a 	nop
+
+08038458 <OSTaskStkInit>:
+ *              been placed on the stack in the proper order.
+ *
+ ***********************************************************************************************/
+
+OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt)
+{
+ 8038458:	defff704 	addi	sp,sp,-36
+ 803845c:	dfc00815 	stw	ra,32(sp)
+ 8038460:	df000715 	stw	fp,28(sp)
+ 8038464:	df000704 	addi	fp,sp,28
+ 8038468:	e13ffc15 	stw	r4,-16(fp)
+ 803846c:	e17ffb15 	stw	r5,-20(fp)
+ 8038470:	e1bffa15 	stw	r6,-24(fp)
+ 8038474:	3805883a 	mov	r2,r7
+ 8038478:	e0bff90d 	sth	r2,-28(fp)
+    * create and initialise the impure pointer used for Newlib thread local storage.
+    * This is only done if the C library is being used in a thread safe mode. Otherwise
+    * a single reent structure is used for all threads, which saves memory.
+    */
+
+   local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent));
+ 803847c:	e0fffa17 	ldw	r3,-24(fp)
+ 8038480:	00bfff04 	movi	r2,-4
+ 8038484:	1884703a 	and	r2,r3,r2
+ 8038488:	10bef704 	addi	r2,r2,-1060
+ 803848c:	e0bfff15 	stw	r2,-4(fp)
+
+   _REENT_INIT_PTR (local_impure_ptr);
+ 8038490:	01810904 	movi	r6,1060
+ 8038494:	000b883a 	mov	r5,zero
+ 8038498:	e13fff17 	ldw	r4,-4(fp)
+ 803849c:	80088e40 	call	80088e4 <memset>
+ 80384a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80384a4:	10c0bb04 	addi	r3,r2,748
+ 80384a8:	e0bfff17 	ldw	r2,-4(fp)
+ 80384ac:	10c00115 	stw	r3,4(r2)
+ 80384b0:	e0bfff17 	ldw	r2,-4(fp)
+ 80384b4:	10c0d504 	addi	r3,r2,852
+ 80384b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80384bc:	10c00215 	stw	r3,8(r2)
+ 80384c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80384c4:	10c0ef04 	addi	r3,r2,956
+ 80384c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80384cc:	10c00315 	stw	r3,12(r2)
+ 80384d0:	e0bfff17 	ldw	r2,-4(fp)
+ 80384d4:	00c00044 	movi	r3,1
+ 80384d8:	10c02915 	stw	r3,164(r2)
+ 80384dc:	10002a15 	stw	zero,168(r2)
+ 80384e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80384e4:	00ccc384 	movi	r3,13070
+ 80384e8:	10c02b0d 	sth	r3,172(r2)
+ 80384ec:	e0bfff17 	ldw	r2,-4(fp)
+ 80384f0:	00eaf344 	movi	r3,-21555
+ 80384f4:	10c02b8d 	sth	r3,174(r2)
+ 80384f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80384fc:	00c48d04 	movi	r3,4660
+ 8038500:	10c02c0d 	sth	r3,176(r2)
+ 8038504:	e0bfff17 	ldw	r2,-4(fp)
+ 8038508:	00f99b44 	movi	r3,-6547
+ 803850c:	10c02c8d 	sth	r3,178(r2)
+ 8038510:	e0bfff17 	ldw	r2,-4(fp)
+ 8038514:	00f7bb04 	movi	r3,-8468
+ 8038518:	10c02d0d 	sth	r3,180(r2)
+ 803851c:	e0bfff17 	ldw	r2,-4(fp)
+ 8038520:	00c00144 	movi	r3,5
+ 8038524:	10c02d8d 	sth	r3,182(r2)
+ 8038528:	e0bfff17 	ldw	r2,-4(fp)
+ 803852c:	00c002c4 	movi	r3,11
+ 8038530:	10c02e0d 	sth	r3,184(r2)
+   /* 
+    * create a stack frame at the top of the stack (leaving space for the 
+    * reentrant data structure).
+    */
+
+   frame_pointer = (INT32U*) local_impure_ptr;
+ 8038534:	e0bfff17 	ldw	r2,-4(fp)
+ 8038538:	e0bffe15 	stw	r2,-8(fp)
+#else
+   frame_pointer =   (INT32U*) (((INT32U)(pstk)) & ~0x3);
+#endif /* OS_THREAD_SAFE_NEWLIB */
+   stk = frame_pointer - 13;
+ 803853c:	e0bffe17 	ldw	r2,-8(fp)
+ 8038540:	10bff304 	addi	r2,r2,-52
+ 8038544:	e0bffd15 	stw	r2,-12(fp)
+
+   /* Now fill the stack frame. */
+
+   stk[12] = (INT32U)task;            /* task address (ra) */
+ 8038548:	e0bffd17 	ldw	r2,-12(fp)
+ 803854c:	10800c04 	addi	r2,r2,48
+ 8038550:	e0fffc17 	ldw	r3,-16(fp)
+ 8038554:	10c00015 	stw	r3,0(r2)
+   stk[11] = (INT32U) pdata;          /* first register argument (r4) */
+ 8038558:	e0bffd17 	ldw	r2,-12(fp)
+ 803855c:	10800b04 	addi	r2,r2,44
+ 8038560:	e0fffb17 	ldw	r3,-20(fp)
+ 8038564:	10c00015 	stw	r3,0(r2)
+
+#if OS_THREAD_SAFE_NEWLIB
+   stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */
+ 8038568:	e0bffd17 	ldw	r2,-12(fp)
+ 803856c:	10800a04 	addi	r2,r2,40
+ 8038570:	e0ffff17 	ldw	r3,-4(fp)
+ 8038574:	10c00015 	stw	r3,0(r2)
+#endif /* OS_THREAD_SAFE_NEWLIB */
+   stk[0]  = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */  
+ 8038578:	00820134 	movhi	r2,2052
+ 803857c:	10a10d04 	addi	r2,r2,-31692
+ 8038580:	10c00104 	addi	r3,r2,4
+ 8038584:	e0bffd17 	ldw	r2,-12(fp)
+ 8038588:	10c00015 	stw	r3,0(r2)
+    */
+   __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext)));
+   __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio)));
+   __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr)));
+  
+   return((OS_STK *)stk);
+ 803858c:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 8038590:	e037883a 	mov	sp,fp
+ 8038594:	dfc00117 	ldw	ra,4(sp)
+ 8038598:	df000017 	ldw	fp,0(sp)
+ 803859c:	dec00204 	addi	sp,sp,8
+ 80385a0:	f800283a 	ret
+
+080385a4 <OSTaskCreateHook>:
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+void OSTaskCreateHook (OS_TCB *ptcb)
+{
+ 80385a4:	defffe04 	addi	sp,sp,-8
+ 80385a8:	df000115 	stw	fp,4(sp)
+ 80385ac:	df000104 	addi	fp,sp,4
+ 80385b0:	e13fff15 	stw	r4,-4(fp)
+    ptcb = ptcb;                       /* Prevent compiler warning */
+}
+ 80385b4:	0001883a 	nop
+ 80385b8:	e037883a 	mov	sp,fp
+ 80385bc:	df000017 	ldw	fp,0(sp)
+ 80385c0:	dec00104 	addi	sp,sp,4
+ 80385c4:	f800283a 	ret
+
+080385c8 <OSTaskDelHook>:
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+void OSTaskDelHook (OS_TCB *ptcb)
+{
+ 80385c8:	defffe04 	addi	sp,sp,-8
+ 80385cc:	df000115 	stw	fp,4(sp)
+ 80385d0:	df000104 	addi	fp,sp,4
+ 80385d4:	e13fff15 	stw	r4,-4(fp)
+    ptcb = ptcb;                       /* Prevent compiler warning                                     */
+}
+ 80385d8:	0001883a 	nop
+ 80385dc:	e037883a 	mov	sp,fp
+ 80385e0:	df000017 	ldw	fp,0(sp)
+ 80385e4:	dec00104 	addi	sp,sp,4
+ 80385e8:	f800283a 	ret
+
+080385ec <OSTaskSwHook>:
+*                 will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                 task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+void OSTaskSwHook (void)
+{
+ 80385ec:	deffff04 	addi	sp,sp,-4
+ 80385f0:	df000015 	stw	fp,0(sp)
+ 80385f4:	d839883a 	mov	fp,sp
+}
+ 80385f8:	0001883a 	nop
+ 80385fc:	e037883a 	mov	sp,fp
+ 8038600:	df000017 	ldw	fp,0(sp)
+ 8038604:	dec00104 	addi	sp,sp,4
+ 8038608:	f800283a 	ret
+
+0803860c <OSTaskStatHook>:
+*
+* Arguments  : none
+*********************************************************************************************************
+*/
+void OSTaskStatHook (void)
+{
+ 803860c:	deffff04 	addi	sp,sp,-4
+ 8038610:	df000015 	stw	fp,0(sp)
+ 8038614:	d839883a 	mov	fp,sp
+}
+ 8038618:	0001883a 	nop
+ 803861c:	e037883a 	mov	sp,fp
+ 8038620:	df000017 	ldw	fp,0(sp)
+ 8038624:	dec00104 	addi	sp,sp,4
+ 8038628:	f800283a 	ret
+
+0803862c <OSTimeTickHook>:
+#ifdef ALT_INICHE
+void cticks_hook(void);
+#endif
+
+void OSTimeTickHook (void)
+{
+ 803862c:	defffe04 	addi	sp,sp,-8
+ 8038630:	dfc00115 	stw	ra,4(sp)
+ 8038634:	df000015 	stw	fp,0(sp)
+ 8038638:	d839883a 	mov	fp,sp
+    }
+#endif  
+    
+#ifdef ALT_INICHE
+    /* Service the Interniche timer */
+    cticks_hook();
+ 803863c:	8028e380 	call	8028e38 <cticks_hook>
+#endif
+}
+ 8038640:	0001883a 	nop
+ 8038644:	e037883a 	mov	sp,fp
+ 8038648:	dfc00117 	ldw	ra,4(sp)
+ 803864c:	df000017 	ldw	fp,0(sp)
+ 8038650:	dec00204 	addi	sp,sp,8
+ 8038654:	f800283a 	ret
+
+08038658 <OSInitHookBegin>:
+
+void OSInitHookBegin(void)
+{
+ 8038658:	deffff04 	addi	sp,sp,-4
+ 803865c:	df000015 	stw	fp,0(sp)
+ 8038660:	d839883a 	mov	fp,sp
+#if OS_TMR_EN > 0
+    OSTmrCtr = 0;
+#endif
+}
+ 8038664:	0001883a 	nop
+ 8038668:	e037883a 	mov	sp,fp
+ 803866c:	df000017 	ldw	fp,0(sp)
+ 8038670:	dec00104 	addi	sp,sp,4
+ 8038674:	f800283a 	ret
+
+08038678 <OSInitHookEnd>:
+
+void OSInitHookEnd(void)
+{
+ 8038678:	deffff04 	addi	sp,sp,-4
+ 803867c:	df000015 	stw	fp,0(sp)
+ 8038680:	d839883a 	mov	fp,sp
+}
+ 8038684:	0001883a 	nop
+ 8038688:	e037883a 	mov	sp,fp
+ 803868c:	df000017 	ldw	fp,0(sp)
+ 8038690:	dec00104 	addi	sp,sp,4
+ 8038694:	f800283a 	ret
+
+08038698 <OSTaskIdleHook>:
+
+void OSTaskIdleHook(void)
+{
+ 8038698:	deffff04 	addi	sp,sp,-4
+ 803869c:	df000015 	stw	fp,0(sp)
+ 80386a0:	d839883a 	mov	fp,sp
+}
+ 80386a4:	0001883a 	nop
+ 80386a8:	e037883a 	mov	sp,fp
+ 80386ac:	df000017 	ldw	fp,0(sp)
+ 80386b0:	dec00104 	addi	sp,sp,4
+ 80386b4:	f800283a 	ret
+
+080386b8 <OSTCBInitHook>:
+
+void OSTCBInitHook(OS_TCB *ptcb)
+{
+ 80386b8:	defffe04 	addi	sp,sp,-8
+ 80386bc:	df000115 	stw	fp,4(sp)
+ 80386c0:	df000104 	addi	fp,sp,4
+ 80386c4:	e13fff15 	stw	r4,-4(fp)
+}
+ 80386c8:	0001883a 	nop
+ 80386cc:	e037883a 	mov	sp,fp
+ 80386d0:	df000017 	ldw	fp,0(sp)
+ 80386d4:	dec00104 	addi	sp,sp,4
+ 80386d8:	f800283a 	ret
+
+080386dc <netmain_init>:
+ * RETURNS: 
+ */
+
+void 
+netmain_init(void)
+{
+ 80386dc:	defffb04 	addi	sp,sp,-20
+ 80386e0:	dfc00415 	stw	ra,16(sp)
+ 80386e4:	df000315 	stw	fp,12(sp)
+ 80386e8:	dc000215 	stw	r16,8(sp)
+ 80386ec:	df000304 	addi	fp,sp,12
+   int   e = 0;
+ 80386f0:	e03ffe15 	stw	zero,-8(fp)
+   char *   msg;
+#ifdef IP_V6
+   ip6_addr host;
+#endif
+
+   printf("%s\n", name);
+ 80386f4:	d0a02b17 	ldw	r2,-32596(gp)
+ 80386f8:	1009883a 	mov	r4,r2
+ 80386fc:	8002d9c0 	call	8002d9c <puts>
+   printf("Copyright 1996-2008 by InterNiche Technologies. All rights reserved. \n");
+ 8038700:	01020174 	movhi	r4,2053
+ 8038704:	212ad404 	addi	r4,r4,-21680
+ 8038708:	8002d9c0 	call	8002d9c <puts>
+#ifdef IN_MENUS
+   install_version("allports3.1");
+#endif
+#ifndef SUPERLOOP
+   /* call this to do pre-task setup including intialization of port_prep */
+   msg = pre_task_setup();
+ 803870c:	802959c0 	call	802959c <pre_task_setup>
+ 8038710:	e0bffd15 	stw	r2,-12(fp)
+   if (msg)
+ 8038714:	e0bffd17 	ldw	r2,-12(fp)
+ 8038718:	10000226 	beq	r2,zero,8038724 <netmain_init+0x48>
+      panic(msg);
+ 803871c:	e13ffd17 	ldw	r4,-12(fp)
+ 8038720:	80271780 	call	8027178 <panic>
+      printf("global_log_create() failed\n");
+   }
+   glog_with_type(LOG_TYPE_INFO, "INICHE LOG initialized", 1);
+#endif
+
+   msg = ip_startup();
+ 8038724:	8024f800 	call	8024f80 <ip_startup>
+ 8038728:	e0bffd15 	stw	r2,-12(fp)
+   if (msg)
+ 803872c:	e0bffd17 	ldw	r2,-12(fp)
+ 8038730:	10000726 	beq	r2,zero,8038750 <netmain_init+0x74>
+   {
+      printf("inet startup error: %s\n", msg);
+ 8038734:	e17ffd17 	ldw	r5,-12(fp)
+ 8038738:	01020174 	movhi	r4,2053
+ 803873c:	212ae604 	addi	r4,r4,-21608
+ 8038740:	8002c780 	call	8002c78 <printf>
+      panic("IP");
+ 8038744:	01020174 	movhi	r4,2053
+ 8038748:	212aec04 	addi	r4,r4,-21584
+ 803874c:	80271780 	call	8027178 <panic>
+   }
+
+#if defined(MEMDEV_SIZE) && defined(VFS_FILES)
+   init_memdev(); /* init the mem and null test devices */
+ 8038750:	803f5980 	call	803f598 <init_memdev>
+#endif
+
+#ifdef IP_MULTICAST
+#ifdef INCLUDE_TCP
+   /* call the IP multicast test program */
+   u_mctest_init();
+ 8038754:	803eef80 	call	803eef8 <u_mctest_init>
+
+   /* clear debugging flags. Port can optionally turn them
+    * back on in post_task_setup();
+    * NDEBUG = UPCTRACE | IPTRACE | TPTRACE ;  
+    */
+   NDEBUG = 0;    
+ 8038758:	d0206615 	stw	zero,-32360(gp)
+
+   /* print IP address of the first interface - for user's benefit */
+   printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name,
+ 803875c:	008201b4 	movhi	r2,2054
+ 8038760:	10b6a617 	ldw	r2,-9576(r2)
+ 8038764:	14000104 	addi	r16,r2,4
+      print_ipad(((NET)(netlist.q_head))->n_ipaddr));
+ 8038768:	008201b4 	movhi	r2,2054
+ 803876c:	10b6a617 	ldw	r2,-9576(r2)
+   printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name,
+ 8038770:	10800a17 	ldw	r2,40(r2)
+ 8038774:	1009883a 	mov	r4,r2
+ 8038778:	8026fbc0 	call	8026fbc <print_ipad>
+ 803877c:	100d883a 	mov	r6,r2
+ 8038780:	800b883a 	mov	r5,r16
+ 8038784:	01020174 	movhi	r4,2053
+ 8038788:	212aed04 	addi	r4,r4,-21580
+ 803878c:	8002c780 	call	8002c78 <printf>
+ 
+#ifndef SUPERLOOP
+   /* call this per-target routine after basic tasks & net are up */
+   msg = post_task_setup();
+ 8038790:	80295e80 	call	80295e8 <post_task_setup>
+ 8038794:	e0bffd15 	stw	r2,-12(fp)
+   if (msg)
+ 8038798:	e0bffd17 	ldw	r2,-12(fp)
+ 803879c:	10000226 	beq	r2,zero,80387a8 <netmain_init+0xcc>
+      panic(msg);
+ 80387a0:	e13ffd17 	ldw	r4,-12(fp)
+ 80387a4:	80271780 	call	8027178 <panic>
+      panic("prep_modules");
+   }
+#endif
+   USE_ARG(e);    /* Avoid compiler warnings */
+
+} /* end of netmain_init() */
+ 80387a8:	0001883a 	nop
+ 80387ac:	e6ffff04 	addi	sp,fp,-4
+ 80387b0:	dfc00217 	ldw	ra,8(sp)
+ 80387b4:	df000117 	ldw	fp,4(sp)
+ 80387b8:	dc000017 	ldw	r16,0(sp)
+ 80387bc:	dec00304 	addi	sp,sp,12
+ 80387c0:	f800283a 	ret
+
+080387c4 <icmp_port_du>:
+ * RETURNS: 
+ */
+
+void
+icmp_port_du(PACKET p, struct destun * pdp)
+{
+ 80387c4:	defffb04 	addi	sp,sp,-20
+ 80387c8:	dfc00415 	stw	ra,16(sp)
+ 80387cc:	df000315 	stw	fp,12(sp)
+ 80387d0:	dc000215 	stw	r16,8(sp)
+ 80387d4:	df000304 	addi	fp,sp,12
+ 80387d8:	e13ffe15 	stw	r4,-8(fp)
+ 80387dc:	e17ffd15 	stw	r5,-12(fp)
+   dprintf("got ICMP %s UNREACHABLE from %s\n", 
+      icmpdu_types[(int)(pdp->dtype)], print_ipad(p->fhost) );
+ 80387e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80387e4:	10800003 	ldbu	r2,0(r2)
+ 80387e8:	10803fcc 	andi	r2,r2,255
+ 80387ec:	1080201c 	xori	r2,r2,128
+ 80387f0:	10bfe004 	addi	r2,r2,-128
+   dprintf("got ICMP %s UNREACHABLE from %s\n", 
+ 80387f4:	100690ba 	slli	r3,r2,2
+ 80387f8:	00820174 	movhi	r2,2053
+ 80387fc:	1885883a 	add	r2,r3,r2
+ 8038800:	14324a17 	ldw	r16,-14040(r2)
+ 8038804:	e0bffe17 	ldw	r2,-8(fp)
+ 8038808:	10800717 	ldw	r2,28(r2)
+ 803880c:	1009883a 	mov	r4,r2
+ 8038810:	8026fbc0 	call	8026fbc <print_ipad>
+ 8038814:	100d883a 	mov	r6,r2
+ 8038818:	800b883a 	mov	r5,r16
+ 803881c:	01020174 	movhi	r4,2053
+ 8038820:	212afd04 	addi	r4,r4,-21516
+ 8038824:	8002c780 	call	8002c78 <printf>
+   dprintf(prompt);
+ 8038828:	d0a02c17 	ldw	r2,-32592(gp)
+ 803882c:	1009883a 	mov	r4,r2
+ 8038830:	8002c780 	call	8002c78 <printf>
+}
+ 8038834:	0001883a 	nop
+ 8038838:	e6ffff04 	addi	sp,fp,-4
+ 803883c:	dfc00217 	ldw	ra,8(sp)
+ 8038840:	df000117 	ldw	fp,4(sp)
+ 8038844:	dc000017 	ldw	r16,0(sp)
+ 8038848:	dec00304 	addi	sp,sp,12
+ 803884c:	f800283a 	ret
+
+08038850 <station_state>:
+ * RETURNS: 
+ */
+
+int
+station_state(void * pio)
+{
+ 8038850:	defff904 	addi	sp,sp,-28
+ 8038854:	dfc00615 	stw	ra,24(sp)
+ 8038858:	df000515 	stw	fp,20(sp)
+ 803885c:	dc000415 	stw	r16,16(sp)
+ 8038860:	df000504 	addi	fp,sp,20
+ 8038864:	e13ffc15 	stw	r4,-16(fp)
+   int i;
+   
+#ifndef NO_INET_STACK
+   NET ifp;
+
+   for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++)
+ 8038868:	e03ffe15 	stw	zero,-8(fp)
+ 803886c:	008201b4 	movhi	r2,2054
+ 8038870:	10b6a617 	ldw	r2,-9576(r2)
+ 8038874:	e0bffd15 	stw	r2,-12(fp)
+ 8038878:	00002506 	br	8038910 <station_state+0xc0>
+   {
+      ns_printf(pio, "iface %d-%s IP addr:%s  ", 
+       i, ifp->name, print_ipad(ifp->n_ipaddr) );
+ 803887c:	e0bffd17 	ldw	r2,-12(fp)
+ 8038880:	14000104 	addi	r16,r2,4
+      ns_printf(pio, "iface %d-%s IP addr:%s  ", 
+ 8038884:	e0bffd17 	ldw	r2,-12(fp)
+ 8038888:	10800a17 	ldw	r2,40(r2)
+ 803888c:	1009883a 	mov	r4,r2
+ 8038890:	8026fbc0 	call	8026fbc <print_ipad>
+ 8038894:	d8800015 	stw	r2,0(sp)
+ 8038898:	800f883a 	mov	r7,r16
+ 803889c:	e1bffe17 	ldw	r6,-8(fp)
+ 80388a0:	01420174 	movhi	r5,2053
+ 80388a4:	296b0604 	addi	r5,r5,-21480
+ 80388a8:	e13ffc17 	ldw	r4,-16(fp)
+ 80388ac:	80273900 	call	8027390 <ns_printf>
+      ns_printf(pio, "subnet:%s  ", print_ipad(ifp->snmask) );
+ 80388b0:	e0bffd17 	ldw	r2,-12(fp)
+ 80388b4:	10800c17 	ldw	r2,48(r2)
+ 80388b8:	1009883a 	mov	r4,r2
+ 80388bc:	8026fbc0 	call	8026fbc <print_ipad>
+ 80388c0:	100d883a 	mov	r6,r2
+ 80388c4:	01420174 	movhi	r5,2053
+ 80388c8:	296b0d04 	addi	r5,r5,-21452
+ 80388cc:	e13ffc17 	ldw	r4,-16(fp)
+ 80388d0:	80273900 	call	8027390 <ns_printf>
+      ns_printf(pio, "gateway:%s\n", print_ipad(ifp->n_defgw) );
+ 80388d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80388d8:	10800d17 	ldw	r2,52(r2)
+ 80388dc:	1009883a 	mov	r4,r2
+ 80388e0:	8026fbc0 	call	8026fbc <print_ipad>
+ 80388e4:	100d883a 	mov	r6,r2
+ 80388e8:	01420174 	movhi	r5,2053
+ 80388ec:	296b1004 	addi	r5,r5,-21440
+ 80388f0:	e13ffc17 	ldw	r4,-16(fp)
+ 80388f4:	80273900 	call	8027390 <ns_printf>
+   for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++)
+ 80388f8:	e0bffd17 	ldw	r2,-12(fp)
+ 80388fc:	10800017 	ldw	r2,0(r2)
+ 8038900:	e0bffd15 	stw	r2,-12(fp)
+ 8038904:	e0bffe17 	ldw	r2,-8(fp)
+ 8038908:	10800044 	addi	r2,r2,1
+ 803890c:	e0bffe15 	stw	r2,-8(fp)
+ 8038910:	e0bffd17 	ldw	r2,-12(fp)
+ 8038914:	103fd91e 	bne	r2,zero,803887c <station_state+0x2c>
+   }
+#endif   /* NO_INET_STACK */
+
+   ns_printf(pio, "current tick count %lu\n", cticks);
+ 8038918:	d0a07d17 	ldw	r2,-32268(gp)
+ 803891c:	100d883a 	mov	r6,r2
+ 8038920:	01420174 	movhi	r5,2053
+ 8038924:	296b1304 	addi	r5,r5,-21428
+ 8038928:	e13ffc17 	ldw	r4,-16(fp)
+ 803892c:	80273900 	call	8027390 <ns_printf>
+
+   ns_printf(pio, "common delay parameter:  %lu ticks (%lu ms).\n", pingdelay, (pingdelay * TIMEFOR1TICK));
+ 8038930:	d0e02d17 	ldw	r3,-32588(gp)
+ 8038934:	d0a02d17 	ldw	r2,-32588(gp)
+ 8038938:	108002a4 	muli	r2,r2,10
+ 803893c:	100f883a 	mov	r7,r2
+ 8038940:	180d883a 	mov	r6,r3
+ 8038944:	01420174 	movhi	r5,2053
+ 8038948:	296b1904 	addi	r5,r5,-21404
+ 803894c:	e13ffc17 	ldw	r4,-16(fp)
+ 8038950:	80273900 	call	8027390 <ns_printf>
+   ns_printf(pio, "common host parameter: %s\n", print_ipad(activehost));
+ 8038954:	d0a08f17 	ldw	r2,-32196(gp)
+ 8038958:	1009883a 	mov	r4,r2
+ 803895c:	8026fbc0 	call	8026fbc <print_ipad>
+ 8038960:	100d883a 	mov	r6,r2
+ 8038964:	01420174 	movhi	r5,2053
+ 8038968:	296b2504 	addi	r5,r5,-21356
+ 803896c:	e13ffc17 	ldw	r4,-16(fp)
+ 8038970:	80273900 	call	8027390 <ns_printf>
+   ns_printf(pio, "common length parameter: %d\n", deflength);
+ 8038974:	d0a02e17 	ldw	r2,-32584(gp)
+ 8038978:	100d883a 	mov	r6,r2
+ 803897c:	01420174 	movhi	r5,2053
+ 8038980:	296b2c04 	addi	r5,r5,-21328
+ 8038984:	e13ffc17 	ldw	r4,-16(fp)
+ 8038988:	80273900 	call	8027390 <ns_printf>
+#ifdef USE_PPP
+   ns_printf(pio, "current dial-in user name is %s\n", pppcfg.username);
+   ns_printf(pio, "current dial-in password is %s\n", pppcfg.password);
+#endif   /* USE_PPP */
+
+   task_stats(pio);
+ 803898c:	e13ffc17 	ldw	r4,-16(fp)
+ 8038990:	8038e5c0 	call	8038e5c <task_stats>
+
+   return 0;
+ 8038994:	0005883a 	mov	r2,zero
+}
+ 8038998:	e6ffff04 	addi	sp,fp,-4
+ 803899c:	dfc00217 	ldw	ra,8(sp)
+ 80389a0:	df000117 	ldw	fp,4(sp)
+ 80389a4:	dc000017 	ldw	r16,0(sp)
+ 80389a8:	dec00304 	addi	sp,sp,12
+ 80389ac:	f800283a 	ret
+
+080389b0 <sysuptime>:
+ * RETURNS: 
+ */
+
+unsigned long
+sysuptime()
+{
+ 80389b0:	defffe04 	addi	sp,sp,-8
+ 80389b4:	dfc00115 	stw	ra,4(sp)
+ 80389b8:	df000015 	stw	fp,0(sp)
+ 80389bc:	d839883a 	mov	fp,sp
+   return ((cticks/TPS)*100);    /* 100ths of a sec since boot time */
+ 80389c0:	d0a07d17 	ldw	r2,-32268(gp)
+ 80389c4:	01401904 	movi	r5,100
+ 80389c8:	1009883a 	mov	r4,r2
+ 80389cc:	800cff80 	call	800cff8 <__udivsi3>
+ 80389d0:	10801924 	muli	r2,r2,100
+}
+ 80389d4:	e037883a 	mov	sp,fp
+ 80389d8:	dfc00117 	ldw	ra,4(sp)
+ 80389dc:	df000017 	ldw	fp,0(sp)
+ 80389e0:	dec00204 	addi	sp,sp,8
+ 80389e4:	f800283a 	ret
+
+080389e8 <packet_check>:
+
+static int inside_pktdemux = 0; 
+
+void
+packet_check(void)
+{
+ 80389e8:	defffe04 	addi	sp,sp,-8
+ 80389ec:	dfc00115 	stw	ra,4(sp)
+ 80389f0:	df000015 	stw	fp,0(sp)
+ 80389f4:	d839883a 	mov	fp,sp
+   if(inside_pktdemux != 0)   /* check re-entrancy flag */
+ 80389f8:	d0a09017 	ldw	r2,-32192(gp)
+ 80389fc:	1000081e 	bne	r2,zero,8038a20 <packet_check+0x38>
+      return;           /* do not re-enter pktdemux(), packet will wait... */
+   inside_pktdemux++;   /* set re-entrany flag */
+ 8038a00:	d0a09017 	ldw	r2,-32192(gp)
+ 8038a04:	10800044 	addi	r2,r2,1
+ 8038a08:	d0a09015 	stw	r2,-32192(gp)
+   pktdemux();          /* process low level packet input */
+ 8038a0c:	80249c40 	call	80249c4 <pktdemux>
+   inside_pktdemux--;   /* clear re-entrany flag */
+ 8038a10:	d0a09017 	ldw	r2,-32192(gp)
+ 8038a14:	10bfffc4 	addi	r2,r2,-1
+ 8038a18:	d0a09015 	stw	r2,-32192(gp)
+ 8038a1c:	00000106 	br	8038a24 <packet_check+0x3c>
+      return;           /* do not re-enter pktdemux(), packet will wait... */
+ 8038a20:	0001883a 	nop
+}
+ 8038a24:	e037883a 	mov	sp,fp
+ 8038a28:	dfc00117 	ldw	ra,4(sp)
+ 8038a2c:	df000017 	ldw	fp,0(sp)
+ 8038a30:	dec00204 	addi	sp,sp,8
+ 8038a34:	f800283a 	ret
+
+08038a38 <mcastlist>:
+ * RETURNS: 
+ */
+
+int
+mcastlist(struct in_multi * multi_ptr)
+{
+ 8038a38:	defffe04 	addi	sp,sp,-8
+ 8038a3c:	df000115 	stw	fp,4(sp)
+ 8038a40:	df000104 	addi	fp,sp,4
+ 8038a44:	e13fff15 	stw	r4,-4(fp)
+   USE_ARG(multi_ptr);
+
+   return 0;
+ 8038a48:	0005883a 	mov	r2,zero
+}
+ 8038a4c:	e037883a 	mov	sp,fp
+ 8038a50:	df000017 	ldw	fp,0(sp)
+ 8038a54:	dec00104 	addi	sp,sp,4
+ 8038a58:	f800283a 	ret
+
+08038a5c <prep_modules>:
+#ifdef USE_MODEM
+extern   int   prep_modem(void);
+#endif   /* USE_MODEM */
+
+int prep_modules(void)
+{
+ 8038a5c:	defffd04 	addi	sp,sp,-12
+ 8038a60:	dfc00215 	stw	ra,8(sp)
+ 8038a64:	df000115 	stw	fp,4(sp)
+ 8038a68:	df000104 	addi	fp,sp,4
+#ifdef IP_V6
+   ip6_addr host;
+   int i;
+#endif
+
+int e = 0;
+ 8038a6c:	e03fff15 	stw	zero,-4(fp)
+      panic("prep_modules");
+   }
+#endif   /* SMTP_ALERTS */
+
+#ifdef VFS_FILES
+   e = prep_vfs();
+ 8038a70:	80426940 	call	8042694 <prep_vfs>
+ 8038a74:	e0bfff15 	stw	r2,-4(fp)
+   if (e != 0)
+ 8038a78:	e0bfff17 	ldw	r2,-4(fp)
+ 8038a7c:	10000626 	beq	r2,zero,8038a98 <prep_modules+0x3c>
+   {
+      dprintf("VFS Module prep failed\n");
+ 8038a80:	01020174 	movhi	r4,2053
+ 8038a84:	212b3404 	addi	r4,r4,-21296
+ 8038a88:	8002d9c0 	call	8002d9c <puts>
+      panic("prep_modules");
+ 8038a8c:	01020174 	movhi	r4,2053
+ 8038a90:	212b3a04 	addi	r4,r4,-21272
+ 8038a94:	80271780 	call	8027178 <panic>
+   {
+      dprintf("sslapp_init() failed\n");
+      panic("prep_modules");
+   }
+#endif
+   return 0;
+ 8038a98:	0005883a 	mov	r2,zero
+}
+ 8038a9c:	e037883a 	mov	sp,fp
+ 8038aa0:	dfc00117 	ldw	ra,4(sp)
+ 8038aa4:	df000017 	ldw	fp,0(sp)
+ 8038aa8:	dec00204 	addi	sp,sp,8
+ 8038aac:	f800283a 	ret
+
+08038ab0 <inet_timer>:
+ * RETURNS: 
+ */
+
+void
+inet_timer(void)
+{
+ 8038ab0:	defffe04 	addi	sp,sp,-8
+ 8038ab4:	dfc00115 	stw	ra,4(sp)
+ 8038ab8:	df000015 	stw	fp,0(sp)
+ 8038abc:	d839883a 	mov	fp,sp
+   if (ire_cticks < cticks)
+      ip_reasm_process_timer_tick ();
+#endif
+
+#ifdef INCLUDE_TCP
+   tcp_tick();          /* run TCP timers */
+ 8038ac0:	802b0500 	call	802b050 <tcp_tick>
+#endif
+
+#ifdef INICHE_TIMERS    /* interval timers? */
+   check_interval_timers();
+ 8038ac4:	8038b280 	call	8038b28 <check_interval_timers>
+#endif
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   /* Call igmp timeout routine */
+   if (igmp_cticks < cticks)  /* Call igmp timeout routine 5 times per sec */
+ 8038ac8:	d0e06a17 	ldw	r3,-32344(gp)
+ 8038acc:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038ad0:	1880012e 	bgeu	r3,r2,8038ad8 <inet_timer+0x28>
+      igmp_fasttimo();
+ 8038ad4:	80254ec0 	call	80254ec <igmp_fasttimo>
+#endif
+
+
+
+   /* Some timer routines only need calling once a second: */
+   if ((nextppp < cticks) ||  /* next call to PPP is due */
+ 8038ad8:	d0e09117 	ldw	r3,-32188(gp)
+ 8038adc:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038ae0:	18800436 	bltu	r3,r2,8038af4 <inet_timer+0x44>
+       (nextppp > (cticks+(10*TPS))) )  /* for when cticks wraps */
+ 8038ae4:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038ae8:	10c0fa04 	addi	r3,r2,1000
+ 8038aec:	d0a09117 	ldw	r2,-32188(gp)
+   if ((nextppp < cticks) ||  /* next call to PPP is due */
+ 8038af0:	1880072e 	bgeu	r3,r2,8038b10 <inet_timer+0x60>
+   {
+      nextppp = cticks + TPS;
+ 8038af4:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038af8:	10801904 	addi	r2,r2,100
+ 8038afc:	d0a09115 	stw	r2,-32188(gp)
+
+      if (port_1s_callout != NULL)
+ 8038b00:	d0a09217 	ldw	r2,-32184(gp)
+ 8038b04:	10000226 	beq	r2,zero,8038b10 <inet_timer+0x60>
+         (*port_1s_callout)();
+ 8038b08:	d0a09217 	ldw	r2,-32184(gp)
+ 8038b0c:	103ee83a 	callr	r2
+#endif
+#ifdef IPSEC
+      IPSecTimer();
+#endif
+   }
+}
+ 8038b10:	0001883a 	nop
+ 8038b14:	e037883a 	mov	sp,fp
+ 8038b18:	dfc00117 	ldw	ra,4(sp)
+ 8038b1c:	df000017 	ldw	fp,0(sp)
+ 8038b20:	dec00204 	addi	sp,sp,8
+ 8038b24:	f800283a 	ret
+
+08038b28 <check_interval_timers>:
+
+static int numtimers = 0;     /* number of active timers */
+
+static void
+check_interval_timers(void)
+{
+ 8038b28:	defffc04 	addi	sp,sp,-16
+ 8038b2c:	dfc00315 	stw	ra,12(sp)
+ 8038b30:	df000215 	stw	fp,8(sp)
+ 8038b34:	df000204 	addi	fp,sp,8
+   int   i;
+   int   found = 0;  /* number of valid timers found */
+ 8038b38:	e03ffe15 	stw	zero,-8(fp)
+
+   /* if no timers, just return */
+   if (numtimers > 0)
+ 8038b3c:	d0a09317 	ldw	r2,-32180(gp)
+ 8038b40:	0080460e 	bge	zero,r2,8038c5c <check_interval_timers+0x134>
+   {
+      /* loop throught the timer list looking for active timers ready to fire */
+      for (i = 0; i < NUM_INTIMERS; i++)
+ 8038b44:	e03fff15 	stw	zero,-4(fp)
+ 8038b48:	00003f06 	br	8038c48 <check_interval_timers+0x120>
+      {
+         if (intimers[i].callback)   /* is this timer active? */
+ 8038b4c:	e0bfff17 	ldw	r2,-4(fp)
+ 8038b50:	10c00524 	muli	r3,r2,20
+ 8038b54:	008201b4 	movhi	r2,2054
+ 8038b58:	1885883a 	add	r2,r3,r2
+ 8038b5c:	10b91c17 	ldw	r2,-7056(r2)
+ 8038b60:	10003626 	beq	r2,zero,8038c3c <check_interval_timers+0x114>
+	 {
+            if ((intimers[i].tmo < cticks) && (!intimers[i].inuse))  /* timer ready fire? */
+ 8038b64:	e0bfff17 	ldw	r2,-4(fp)
+ 8038b68:	10c00524 	muli	r3,r2,20
+ 8038b6c:	008201b4 	movhi	r2,2054
+ 8038b70:	1885883a 	add	r2,r3,r2
+ 8038b74:	10f91f17 	ldw	r3,-7044(r2)
+ 8038b78:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038b7c:	1880292e 	bgeu	r3,r2,8038c24 <check_interval_timers+0xfc>
+ 8038b80:	e0bfff17 	ldw	r2,-4(fp)
+ 8038b84:	10c00524 	muli	r3,r2,20
+ 8038b88:	008201b4 	movhi	r2,2054
+ 8038b8c:	1885883a 	add	r2,r3,r2
+ 8038b90:	10b92017 	ldw	r2,-7040(r2)
+ 8038b94:	1000231e 	bne	r2,zero,8038c24 <check_interval_timers+0xfc>
+            {
+               intimers[i].tmo = intimers[i].interval + cticks;   /* set next tmo */
+ 8038b98:	e0bfff17 	ldw	r2,-4(fp)
+ 8038b9c:	10c00524 	muli	r3,r2,20
+ 8038ba0:	008201b4 	movhi	r2,2054
+ 8038ba4:	1885883a 	add	r2,r3,r2
+ 8038ba8:	10f91e17 	ldw	r3,-7048(r2)
+ 8038bac:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038bb0:	1887883a 	add	r3,r3,r2
+ 8038bb4:	e0bfff17 	ldw	r2,-4(fp)
+ 8038bb8:	11000524 	muli	r4,r2,20
+ 8038bbc:	008201b4 	movhi	r2,2054
+ 8038bc0:	2085883a 	add	r2,r4,r2
+ 8038bc4:	10f91f15 	stw	r3,-7044(r2)
+               intimers[i].inuse = TRUE;
+ 8038bc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8038bcc:	11000524 	muli	r4,r2,20
+ 8038bd0:	00c00044 	movi	r3,1
+ 8038bd4:	008201b4 	movhi	r2,2054
+ 8038bd8:	2085883a 	add	r2,r4,r2
+ 8038bdc:	10f92015 	stw	r3,-7040(r2)
+               intimers[i].callback(intimers[i].parm);      /* call user routine */
+ 8038be0:	e0bfff17 	ldw	r2,-4(fp)
+ 8038be4:	10c00524 	muli	r3,r2,20
+ 8038be8:	008201b4 	movhi	r2,2054
+ 8038bec:	1885883a 	add	r2,r3,r2
+ 8038bf0:	10f91c17 	ldw	r3,-7056(r2)
+ 8038bf4:	e0bfff17 	ldw	r2,-4(fp)
+ 8038bf8:	11000524 	muli	r4,r2,20
+ 8038bfc:	008201b4 	movhi	r2,2054
+ 8038c00:	2085883a 	add	r2,r4,r2
+ 8038c04:	10b91d17 	ldw	r2,-7052(r2)
+ 8038c08:	1009883a 	mov	r4,r2
+ 8038c0c:	183ee83a 	callr	r3
+               intimers[i].inuse = FALSE;
+ 8038c10:	e0bfff17 	ldw	r2,-4(fp)
+ 8038c14:	10c00524 	muli	r3,r2,20
+ 8038c18:	008201b4 	movhi	r2,2054
+ 8038c1c:	1885883a 	add	r2,r3,r2
+ 8038c20:	10392015 	stw	zero,-7040(r2)
+            }
+            /* If we've examined all the active timers, we're done */
+            if (++found >= numtimers)
+ 8038c24:	e0bffe17 	ldw	r2,-8(fp)
+ 8038c28:	10800044 	addi	r2,r2,1
+ 8038c2c:	e0bffe15 	stw	r2,-8(fp)
+ 8038c30:	d0a09317 	ldw	r2,-32180(gp)
+ 8038c34:	e0fffe17 	ldw	r3,-8(fp)
+ 8038c38:	1880070e 	bge	r3,r2,8038c58 <check_interval_timers+0x130>
+      for (i = 0; i < NUM_INTIMERS; i++)
+ 8038c3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8038c40:	10800044 	addi	r2,r2,1
+ 8038c44:	e0bfff15 	stw	r2,-4(fp)
+ 8038c48:	e0bfff17 	ldw	r2,-4(fp)
+ 8038c4c:	10800150 	cmplti	r2,r2,5
+ 8038c50:	103fbe1e 	bne	r2,zero,8038b4c <check_interval_timers+0x24>
+               break;
+         }
+      }
+   }
+}
+ 8038c54:	00000106 	br	8038c5c <check_interval_timers+0x134>
+               break;
+ 8038c58:	0001883a 	nop
+}
+ 8038c5c:	0001883a 	nop
+ 8038c60:	e037883a 	mov	sp,fp
+ 8038c64:	dfc00117 	ldw	ra,4(sp)
+ 8038c68:	df000017 	ldw	fp,0(sp)
+ 8038c6c:	dec00204 	addi	sp,sp,8
+ 8038c70:	f800283a 	ret
+
+08038c74 <in_timerset>:
+ * RETURNS: timer ID if OK, else if table is full.
+ */
+
+long
+in_timerset(void (*callback)(long), long msecs, long parm)
+{
+ 8038c74:	defffa04 	addi	sp,sp,-24
+ 8038c78:	dfc00515 	stw	ra,20(sp)
+ 8038c7c:	df000415 	stw	fp,16(sp)
+ 8038c80:	df000404 	addi	fp,sp,16
+ 8038c84:	e13ffe15 	stw	r4,-8(fp)
+ 8038c88:	e17ffd15 	stw	r5,-12(fp)
+ 8038c8c:	e1bffc15 	stw	r6,-16(fp)
+   int   i;
+
+   for(i = 0; i < NUM_INTIMERS; i++)
+ 8038c90:	e03fff15 	stw	zero,-4(fp)
+ 8038c94:	00003906 	br	8038d7c <in_timerset+0x108>
+   {
+      if(intimers[i].callback == NULL)
+ 8038c98:	e0bfff17 	ldw	r2,-4(fp)
+ 8038c9c:	10c00524 	muli	r3,r2,20
+ 8038ca0:	008201b4 	movhi	r2,2054
+ 8038ca4:	1885883a 	add	r2,r3,r2
+ 8038ca8:	10b91c17 	ldw	r2,-7056(r2)
+ 8038cac:	1000301e 	bne	r2,zero,8038d70 <in_timerset+0xfc>
+      {
+         /* found empty table entry, set up new timer */
+         intimers[i].callback = callback;
+ 8038cb0:	e0bfff17 	ldw	r2,-4(fp)
+ 8038cb4:	11000524 	muli	r4,r2,20
+ 8038cb8:	e0fffe17 	ldw	r3,-8(fp)
+ 8038cbc:	008201b4 	movhi	r2,2054
+ 8038cc0:	2085883a 	add	r2,r4,r2
+ 8038cc4:	10f91c15 	stw	r3,-7056(r2)
+         intimers[i].parm = parm;
+ 8038cc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8038ccc:	11000524 	muli	r4,r2,20
+ 8038cd0:	e0fffc17 	ldw	r3,-16(fp)
+ 8038cd4:	008201b4 	movhi	r2,2054
+ 8038cd8:	2085883a 	add	r2,r4,r2
+ 8038cdc:	10f91d15 	stw	r3,-7052(r2)
+         /* set interval, in TPS (cticks) units */
+         intimers[i].interval = (msecs * TPS)/1000;
+ 8038ce0:	e0bffd17 	ldw	r2,-12(fp)
+ 8038ce4:	01400284 	movi	r5,10
+ 8038ce8:	1009883a 	mov	r4,r2
+ 8038cec:	800cf000 	call	800cf00 <__divsi3>
+ 8038cf0:	1009883a 	mov	r4,r2
+ 8038cf4:	e0bfff17 	ldw	r2,-4(fp)
+ 8038cf8:	10c00524 	muli	r3,r2,20
+ 8038cfc:	008201b4 	movhi	r2,2054
+ 8038d00:	1885883a 	add	r2,r3,r2
+ 8038d04:	11391e15 	stw	r4,-7048(r2)
+         intimers[i].tmo = intimers[i].interval + cticks;   /* first tmo */
+ 8038d08:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d0c:	10c00524 	muli	r3,r2,20
+ 8038d10:	008201b4 	movhi	r2,2054
+ 8038d14:	1885883a 	add	r2,r3,r2
+ 8038d18:	10f91e17 	ldw	r3,-7048(r2)
+ 8038d1c:	d0a07d17 	ldw	r2,-32268(gp)
+ 8038d20:	1887883a 	add	r3,r3,r2
+ 8038d24:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d28:	11000524 	muli	r4,r2,20
+ 8038d2c:	008201b4 	movhi	r2,2054
+ 8038d30:	2085883a 	add	r2,r4,r2
+ 8038d34:	10f91f15 	stw	r3,-7044(r2)
+		 intimers[i].inuse = FALSE;
+ 8038d38:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d3c:	10c00524 	muli	r3,r2,20
+ 8038d40:	008201b4 	movhi	r2,2054
+ 8038d44:	1885883a 	add	r2,r3,r2
+ 8038d48:	10392015 	stw	zero,-7040(r2)
+         numtimers++;
+ 8038d4c:	d0a09317 	ldw	r2,-32180(gp)
+ 8038d50:	10800044 	addi	r2,r2,1
+ 8038d54:	d0a09315 	stw	r2,-32180(gp)
+         return (long)&intimers[i];
+ 8038d58:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d5c:	10c00524 	muli	r3,r2,20
+ 8038d60:	008201b4 	movhi	r2,2054
+ 8038d64:	10b91c04 	addi	r2,r2,-7056
+ 8038d68:	1885883a 	add	r2,r3,r2
+ 8038d6c:	00000706 	br	8038d8c <in_timerset+0x118>
+   for(i = 0; i < NUM_INTIMERS; i++)
+ 8038d70:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d74:	10800044 	addi	r2,r2,1
+ 8038d78:	e0bfff15 	stw	r2,-4(fp)
+ 8038d7c:	e0bfff17 	ldw	r2,-4(fp)
+ 8038d80:	10800150 	cmplti	r2,r2,5
+ 8038d84:	103fc41e 	bne	r2,zero,8038c98 <in_timerset+0x24>
+      }
+   }
+   return 0;
+ 8038d88:	0005883a 	mov	r2,zero
+}
+ 8038d8c:	e037883a 	mov	sp,fp
+ 8038d90:	dfc00117 	ldw	ra,4(sp)
+ 8038d94:	df000017 	ldw	fp,0(sp)
+ 8038d98:	dec00204 	addi	sp,sp,8
+ 8038d9c:	f800283a 	ret
+
+08038da0 <in_timerkill>:
+ */
+
+
+int
+in_timerkill(long timer)
+{
+ 8038da0:	defffc04 	addi	sp,sp,-16
+ 8038da4:	dfc00315 	stw	ra,12(sp)
+ 8038da8:	df000215 	stw	fp,8(sp)
+ 8038dac:	df000204 	addi	fp,sp,8
+ 8038db0:	e13ffe15 	stw	r4,-8(fp)
+   int   i;
+
+   for(i = 0; i < NUM_INTIMERS; i++)
+ 8038db4:	e03fff15 	stw	zero,-4(fp)
+ 8038db8:	00001506 	br	8038e10 <in_timerkill+0x70>
+   {
+      if(timer == (long)&intimers[i])
+ 8038dbc:	e0bfff17 	ldw	r2,-4(fp)
+ 8038dc0:	10c00524 	muli	r3,r2,20
+ 8038dc4:	008201b4 	movhi	r2,2054
+ 8038dc8:	10b91c04 	addi	r2,r2,-7056
+ 8038dcc:	1885883a 	add	r2,r3,r2
+ 8038dd0:	1007883a 	mov	r3,r2
+ 8038dd4:	e0bffe17 	ldw	r2,-8(fp)
+ 8038dd8:	10c00a1e 	bne	r2,r3,8038e04 <in_timerkill+0x64>
+      {
+         intimers[i].callback = NULL;
+ 8038ddc:	e0bfff17 	ldw	r2,-4(fp)
+ 8038de0:	10c00524 	muli	r3,r2,20
+ 8038de4:	008201b4 	movhi	r2,2054
+ 8038de8:	1885883a 	add	r2,r3,r2
+ 8038dec:	10391c15 	stw	zero,-7056(r2)
+         numtimers--;
+ 8038df0:	d0a09317 	ldw	r2,-32180(gp)
+ 8038df4:	10bfffc4 	addi	r2,r2,-1
+ 8038df8:	d0a09315 	stw	r2,-32180(gp)
+         return 0;      /* OK return */
+ 8038dfc:	0005883a 	mov	r2,zero
+ 8038e00:	00000806 	br	8038e24 <in_timerkill+0x84>
+   for(i = 0; i < NUM_INTIMERS; i++)
+ 8038e04:	e0bfff17 	ldw	r2,-4(fp)
+ 8038e08:	10800044 	addi	r2,r2,1
+ 8038e0c:	e0bfff15 	stw	r2,-4(fp)
+ 8038e10:	e0bfff17 	ldw	r2,-4(fp)
+ 8038e14:	10800150 	cmplti	r2,r2,5
+ 8038e18:	103fe81e 	bne	r2,zero,8038dbc <in_timerkill+0x1c>
+      }
+   }
+   dtrap();    /* timer to kill not found */
+ 8038e1c:	8028cd40 	call	8028cd4 <dtrap>
+   return ENP_PARAM;
+ 8038e20:	00bffd84 	movi	r2,-10
+}
+ 8038e24:	e037883a 	mov	sp,fp
+ 8038e28:	dfc00117 	ldw	ra,4(sp)
+ 8038e2c:	df000017 	ldw	fp,0(sp)
+ 8038e30:	dec00204 	addi	sp,sp,8
+ 8038e34:	f800283a 	ret
+
+08038e38 <create_apptasks>:
+#endif
+/* per-application thread definitions */
+
+int
+create_apptasks(void)
+{
+ 8038e38:	defffe04 	addi	sp,sp,-8
+ 8038e3c:	df000115 	stw	fp,4(sp)
+ 8038e40:	df000104 	addi	fp,sp,4
+int e = 0;
+ 8038e44:	e03fff15 	stw	zero,-4(fp)
+#endif
+/* 
+ * Altera Niche Stack Nios port modification:
+ * return error code, if any 
+ */
+   return e;
+ 8038e48:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8038e4c:	e037883a 	mov	sp,fp
+ 8038e50:	df000017 	ldw	fp,0(sp)
+ 8038e54:	dec00104 	addi	sp,sp,4
+ 8038e58:	f800283a 	ret
+
+08038e5c <task_stats>:
+ */
+
+
+void
+task_stats(void * pio)
+{
+ 8038e5c:	defffd04 	addi	sp,sp,-12
+ 8038e60:	dfc00215 	stw	ra,8(sp)
+ 8038e64:	df000115 	stw	fp,4(sp)
+ 8038e68:	df000104 	addi	fp,sp,4
+ 8038e6c:	e13fff15 	stw	r4,-4(fp)
+   ns_printf(pio, "Task wakeups:");
+ 8038e70:	01420174 	movhi	r5,2053
+ 8038e74:	296b3e04 	addi	r5,r5,-21256
+ 8038e78:	e13fff17 	ldw	r4,-4(fp)
+ 8038e7c:	80273900 	call	8027390 <ns_printf>
+
+#ifndef NO_INET_STACK
+   ns_printf(pio, "netmain: %lu\n", netmain_wakes);
+ 8038e80:	d0a06d17 	ldw	r2,-32332(gp)
+ 8038e84:	100d883a 	mov	r6,r2
+ 8038e88:	01420174 	movhi	r5,2053
+ 8038e8c:	296b4204 	addi	r5,r5,-21240
+ 8038e90:	e13fff17 	ldw	r4,-4(fp)
+ 8038e94:	80273900 	call	8027390 <ns_printf>
+#endif
+#ifndef NO_INET_TICK
+   ns_printf(pio, "nettick: %lu\n", nettick_wakes);
+ 8038e98:	d0a06e17 	ldw	r2,-32328(gp)
+ 8038e9c:	100d883a 	mov	r6,r2
+ 8038ea0:	01420174 	movhi	r5,2053
+ 8038ea4:	296b4604 	addi	r5,r5,-21224
+ 8038ea8:	e13fff17 	ldw	r4,-4(fp)
+ 8038eac:	80273900 	call	8027390 <ns_printf>
+   ns_printf(pio, "browtask: %lu  ", browtask_wakes);
+#endif
+#ifdef INCLUDE_SSLAPP
+   ns_printf(pio, "INCLUDE_SSLAPP: %lu  ", sslapp_wakes);
+#endif
+   ns_printf(pio, "\n");
+ 8038eb0:	01420174 	movhi	r5,2053
+ 8038eb4:	296b4a04 	addi	r5,r5,-21208
+ 8038eb8:	e13fff17 	ldw	r4,-4(fp)
+ 8038ebc:	80273900 	call	8027390 <ns_printf>
+}
+ 8038ec0:	0001883a 	nop
+ 8038ec4:	e037883a 	mov	sp,fp
+ 8038ec8:	dfc00117 	ldw	ra,4(sp)
+ 8038ecc:	df000017 	ldw	fp,0(sp)
+ 8038ed0:	dec00204 	addi	sp,sp,8
+ 8038ed4:	f800283a 	ret
+
+08038ed8 <fcntl>:
+ * (for files and device drivers) or calls the InterNiche bsd_ioctl for 
+ * sockets.
+ */
+ 
+int fcntl (int file, int cmd, ...)
+{
+ 8038ed8:	defff804 	addi	sp,sp,-32
+ 8038edc:	dfc00515 	stw	ra,20(sp)
+ 8038ee0:	df000415 	stw	fp,16(sp)
+ 8038ee4:	df000404 	addi	fp,sp,16
+ 8038ee8:	e13ffd15 	stw	r4,-12(fp)
+ 8038eec:	e17ffc15 	stw	r5,-16(fp)
+ 8038ef0:	e1800215 	stw	r6,8(fp)
+ 8038ef4:	e1c00315 	stw	r7,12(fp)
+  long     flags;
+  va_list  argp;
+
+  if (file < ALT_MAX_FD)
+ 8038ef8:	e0bffd17 	ldw	r2,-12(fp)
+ 8038efc:	10800408 	cmpgei	r2,r2,16
+ 8038f00:	10000c1e 	bne	r2,zero,8038f34 <fcntl+0x5c>
+  {
+    va_start(argp, cmd);
+ 8038f04:	e0800204 	addi	r2,fp,8
+ 8038f08:	e0bffe15 	stw	r2,-8(fp)
+    flags = va_arg(argp, long);
+ 8038f0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8038f10:	10c00104 	addi	r3,r2,4
+ 8038f14:	e0fffe15 	stw	r3,-8(fp)
+ 8038f18:	10800017 	ldw	r2,0(r2)
+ 8038f1c:	e0bfff15 	stw	r2,-4(fp)
+    va_end(argp);
+    return alt_fcntl(file, cmd, flags);
+ 8038f20:	e1bfff17 	ldw	r6,-4(fp)
+ 8038f24:	e17ffc17 	ldw	r5,-16(fp)
+ 8038f28:	e13ffd17 	ldw	r4,-12(fp)
+ 8038f2c:	80426f40 	call	80426f4 <alt_fcntl>
+ 8038f30:	00000c06 	br	8038f64 <fcntl+0x8c>
+  }
+  else
+  {
+    va_start(argp, cmd);
+ 8038f34:	e0800204 	addi	r2,fp,8
+ 8038f38:	e0bffe15 	stw	r2,-8(fp)
+    flags = va_arg(argp, long);
+ 8038f3c:	e0bffe17 	ldw	r2,-8(fp)
+ 8038f40:	10c00104 	addi	r3,r2,4
+ 8038f44:	e0fffe15 	stw	r3,-8(fp)
+ 8038f48:	10800017 	ldw	r2,0(r2)
+ 8038f4c:	e0bfff15 	stw	r2,-4(fp)
+    va_end(argp);
+    return bsd_ioctl(file, cmd, flags);
+ 8038f50:	e0bffc17 	ldw	r2,-16(fp)
+ 8038f54:	e1bfff17 	ldw	r6,-4(fp)
+ 8038f58:	100b883a 	mov	r5,r2
+ 8038f5c:	e13ffd17 	ldw	r4,-12(fp)
+ 8038f60:	802680c0 	call	802680c <bsd_ioctl>
+  }
+}
+ 8038f64:	e037883a 	mov	sp,fp
+ 8038f68:	dfc00117 	ldw	ra,4(sp)
+ 8038f6c:	df000017 	ldw	fp,0(sp)
+ 8038f70:	dec00404 	addi	sp,sp,16
+ 8038f74:	f800283a 	ret
+
+08038f78 <icmprcv>:
+};
+#endif /* USER_PING_TSTAMP */
+
+int
+icmprcv(PACKET p)      /* the incoming packet */
+{
+ 8038f78:	deffef04 	addi	sp,sp,-68
+ 8038f7c:	dfc01015 	stw	ra,64(sp)
+ 8038f80:	df000f15 	stw	fp,60(sp)
+ 8038f84:	dc400e15 	stw	r17,56(sp)
+ 8038f88:	dc000d15 	stw	r16,52(sp)
+ 8038f8c:	df000f04 	addi	fp,sp,60
+ 8038f90:	e13ff315 	stw	r4,-52(fp)
+   unsigned short xsum;
+#ifdef FULL_ICMP
+   struct redirect * rd;
+   struct destun *   pdp;
+#endif   /* FULL_ICMP */
+   char sav_ch = 0;
+ 8038f94:	e03ffdc5 	stb	zero,-9(fp)
+   int i;
+
+   icmp_mib.icmpInMsgs++;                 /* received one more icmp */
+ 8038f98:	008201b4 	movhi	r2,2054
+ 8038f9c:	10b93517 	ldw	r2,-6956(r2)
+ 8038fa0:	10c00044 	addi	r3,r2,1
+ 8038fa4:	008201b4 	movhi	r2,2054
+ 8038fa8:	10f93515 	stw	r3,-6956(r2)
+
+   pip = ip_head(p);                      /* find IP header */
+ 8038fac:	e0bff317 	ldw	r2,-52(fp)
+ 8038fb0:	10800317 	ldw	r2,12(r2)
+ 8038fb4:	e0bffc15 	stw	r2,-16(fp)
+   len = p->nb_plen - (ip_hlen(pip));     /* strip IP header length */
+ 8038fb8:	e0bff317 	ldw	r2,-52(fp)
+ 8038fbc:	10c00417 	ldw	r3,16(r2)
+ 8038fc0:	e0bffc17 	ldw	r2,-16(fp)
+ 8038fc4:	10800003 	ldbu	r2,0(r2)
+ 8038fc8:	10803fcc 	andi	r2,r2,255
+ 8038fcc:	100490ba 	slli	r2,r2,2
+ 8038fd0:	10800f0c 	andi	r2,r2,60
+ 8038fd4:	1885c83a 	sub	r2,r3,r2
+ 8038fd8:	e0bffb15 	stw	r2,-20(fp)
+   host = p->fhost;                       /* filled in by IP layer */
+ 8038fdc:	e0bff317 	ldw	r2,-52(fp)
+ 8038fe0:	10800717 	ldw	r2,28(r2)
+ 8038fe4:	e0bffa15 	stw	r2,-24(fp)
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 8038fe8:	d0a06617 	ldw	r2,-32360(gp)
+ 8038fec:	1081000c 	andi	r2,r2,1024
+ 8038ff0:	10001526 	beq	r2,zero,8039048 <icmprcv+0xd0>
+ 8038ff4:	d0a06617 	ldw	r2,-32360(gp)
+ 8038ff8:	1080800c 	andi	r2,r2,512
+ 8038ffc:	10001226 	beq	r2,zero,8039048 <icmprcv+0xd0>
+      dprintf("ICMP: p[%u] from %u.%u.%u.%u\n", len, PUSH_IPADDR(host));
+ 8039000:	e0bffa17 	ldw	r2,-24(fp)
+ 8039004:	11003fcc 	andi	r4,r2,255
+ 8039008:	e0bffa17 	ldw	r2,-24(fp)
+ 803900c:	1004d23a 	srli	r2,r2,8
+ 8039010:	11403fcc 	andi	r5,r2,255
+ 8039014:	e0bffa17 	ldw	r2,-24(fp)
+ 8039018:	1004d43a 	srli	r2,r2,16
+ 803901c:	10803fcc 	andi	r2,r2,255
+ 8039020:	e0fffa17 	ldw	r3,-24(fp)
+ 8039024:	1806d63a 	srli	r3,r3,24
+ 8039028:	d8c00115 	stw	r3,4(sp)
+ 803902c:	d8800015 	stw	r2,0(sp)
+ 8039030:	280f883a 	mov	r7,r5
+ 8039034:	200d883a 	mov	r6,r4
+ 8039038:	e17ffb17 	ldw	r5,-20(fp)
+ 803903c:	01020174 	movhi	r4,2053
+ 8039040:	212b4b04 	addi	r4,r4,-21204
+ 8039044:	8002c780 	call	8002c78 <printf>
+#endif
+
+   e = (struct ping *)ip_data(pip);       /* finally, extract ICMP header */
+ 8039048:	e0bffc17 	ldw	r2,-16(fp)
+ 803904c:	10800003 	ldbu	r2,0(r2)
+ 8039050:	10803fcc 	andi	r2,r2,255
+ 8039054:	100490ba 	slli	r2,r2,2
+ 8039058:	10800f0c 	andi	r2,r2,60
+ 803905c:	e0fffc17 	ldw	r3,-16(fp)
+ 8039060:	1885883a 	add	r2,r3,r2
+ 8039064:	e0bff915 	stw	r2,-28(fp)
+
+   osum = e->pchksum;
+ 8039068:	e0bff917 	ldw	r2,-28(fp)
+ 803906c:	1080008b 	ldhu	r2,2(r2)
+ 8039070:	e0bff88d 	sth	r2,-30(fp)
+   e->pchksum = 0;
+ 8039074:	e0bff917 	ldw	r2,-28(fp)
+ 8039078:	1000008d 	sth	zero,2(r2)
+
+   if (len&1)
+ 803907c:	e0bffb17 	ldw	r2,-20(fp)
+ 8039080:	1080004c 	andi	r2,r2,1
+ 8039084:	10000926 	beq	r2,zero,80390ac <icmprcv+0x134>
+   {
+      sav_ch = *(((char *) e) + len);
+ 8039088:	e0fff917 	ldw	r3,-28(fp)
+ 803908c:	e0bffb17 	ldw	r2,-20(fp)
+ 8039090:	1885883a 	add	r2,r3,r2
+ 8039094:	10800003 	ldbu	r2,0(r2)
+ 8039098:	e0bffdc5 	stb	r2,-9(fp)
+      ((char *)e)[len] = 0;
+ 803909c:	e0fff917 	ldw	r3,-28(fp)
+ 80390a0:	e0bffb17 	ldw	r2,-20(fp)
+ 80390a4:	1885883a 	add	r2,r3,r2
+ 80390a8:	10000005 	stb	zero,0(r2)
+   }
+
+   xsum = ~cksum(e, (len+1)>>1);
+ 80390ac:	e0bffb17 	ldw	r2,-20(fp)
+ 80390b0:	10800044 	addi	r2,r2,1
+ 80390b4:	1004d07a 	srli	r2,r2,1
+ 80390b8:	100b883a 	mov	r5,r2
+ 80390bc:	e13ff917 	ldw	r4,-28(fp)
+ 80390c0:	8026d7c0 	call	8026d7c <cksum>
+ 80390c4:	0084303a 	nor	r2,zero,r2
+ 80390c8:	e0bff80d 	sth	r2,-32(fp)
+   if (len&1) *(((char *) e) + len) = sav_ch;
+ 80390cc:	e0bffb17 	ldw	r2,-20(fp)
+ 80390d0:	1080004c 	andi	r2,r2,1
+ 80390d4:	10000526 	beq	r2,zero,80390ec <icmprcv+0x174>
+ 80390d8:	e0fff917 	ldw	r3,-28(fp)
+ 80390dc:	e0bffb17 	ldw	r2,-20(fp)
+ 80390e0:	1885883a 	add	r2,r3,r2
+ 80390e4:	e0fffdc3 	ldbu	r3,-9(fp)
+ 80390e8:	10c00005 	stb	r3,0(r2)
+   if (xsum != osum)
+ 80390ec:	e0fff80b 	ldhu	r3,-32(fp)
+ 80390f0:	e0bff88b 	ldhu	r2,-30(fp)
+ 80390f4:	18802226 	beq	r3,r2,8039180 <icmprcv+0x208>
+   {
+      e->pchksum = osum;
+ 80390f8:	e0bff917 	ldw	r2,-28(fp)
+ 80390fc:	e0fff88b 	ldhu	r3,-30(fp)
+ 8039100:	10c0008d 	sth	r3,2(r2)
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 8039104:	d0a06617 	ldw	r2,-32360(gp)
+ 8039108:	1081000c 	andi	r2,r2,1024
+ 803910c:	10000f26 	beq	r2,zero,803914c <icmprcv+0x1d4>
+ 8039110:	d0a06617 	ldw	r2,-32360(gp)
+ 8039114:	1080800c 	andi	r2,r2,512
+ 8039118:	10000c26 	beq	r2,zero,803914c <icmprcv+0x1d4>
+      {
+         dprintf("ICMP: Bad xsum %04x should have been %04x\n",
+ 803911c:	e0bff88b 	ldhu	r2,-30(fp)
+ 8039120:	e0fff80b 	ldhu	r3,-32(fp)
+ 8039124:	180d883a 	mov	r6,r3
+ 8039128:	100b883a 	mov	r5,r2
+ 803912c:	01020174 	movhi	r4,2053
+ 8039130:	212b5304 	addi	r4,r4,-21172
+ 8039134:	8002c780 	call	8002c78 <printf>
+          osum, xsum);
+         if (NDEBUG & DUMP) ip_dump(p);
+ 8039138:	d0a06617 	ldw	r2,-32360(gp)
+ 803913c:	1080008c 	andi	r2,r2,2
+ 8039140:	10000226 	beq	r2,zero,803914c <icmprcv+0x1d4>
+ 8039144:	e13ff317 	ldw	r4,-52(fp)
+ 8039148:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif
+      icmp_mib.icmpInErrors++;
+ 803914c:	008201b4 	movhi	r2,2054
+ 8039150:	10b93617 	ldw	r2,-6952(r2)
+ 8039154:	10c00044 	addi	r3,r2,1
+ 8039158:	008201b4 	movhi	r2,2054
+ 803915c:	10f93615 	stw	r3,-6952(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039160:	01000084 	movi	r4,2
+ 8039164:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 8039168:	e13ff317 	ldw	r4,-52(fp)
+ 803916c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039170:	01000084 	movi	r4,2
+ 8039174:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_BAD_HEADER;
+ 8039178:	00bff804 	movi	r2,-32
+ 803917c:	00022e06 	br	8039a38 <icmprcv+0xac0>
+   }
+
+   e->pchksum = osum;
+ 8039180:	e0bff917 	ldw	r2,-28(fp)
+ 8039184:	e0fff88b 	ldhu	r3,-30(fp)
+ 8039188:	10c0008d 	sth	r3,2(r2)
+
+   switch (e->ptype) 
+ 803918c:	e0bff917 	ldw	r2,-28(fp)
+ 8039190:	10800003 	ldbu	r2,0(r2)
+ 8039194:	10803fcc 	andi	r2,r2,255
+ 8039198:	1080201c 	xori	r2,r2,128
+ 803919c:	10bfe004 	addi	r2,r2,-128
+ 80391a0:	10c00428 	cmpgeui	r3,r2,16
+ 80391a4:	18020a1e 	bne	r3,zero,80399d0 <icmprcv+0xa58>
+ 80391a8:	100690ba 	slli	r3,r2,2
+ 80391ac:	00820134 	movhi	r2,2052
+ 80391b0:	1885883a 	add	r2,r3,r2
+ 80391b4:	10a46f17 	ldw	r2,-28228(r2)
+ 80391b8:	1000683a 	jmp	r2
+ 80391bc:	08039454 	ori	zero,at,3665
+ 80391c0:	080399d0 	cmplti	zero,at,3687
+ 80391c4:	080399d0 	cmplti	zero,at,3687
+ 80391c8:	08039474 	orhi	zero,at,3665
+ 80391cc:	08039568 	cmpgeui	zero,at,3669
+ 80391d0:	080395fc 	xorhi	zero,at,3671
+ 80391d4:	080399d0 	cmplti	zero,at,3687
+ 80391d8:	080399d0 	cmplti	zero,at,3687
+ 80391dc:	080391fc 	xorhi	zero,at,3655
+ 80391e0:	080399d0 	cmplti	zero,at,3687
+ 80391e4:	080399d0 	cmplti	zero,at,3687
+ 80391e8:	08039728 	cmpgeui	zero,at,3676
+ 80391ec:	08039828 	cmpgeui	zero,at,3680
+ 80391f0:	08039884 	addi	zero,at,3682
+ 80391f4:	080399d0 	cmplti	zero,at,3687
+ 80391f8:	0803999c 	xori	zero,at,3686
+   {
+   case ECHOREQ:  /* got ping request, send reply */
+      icmp_mib.icmpInEchos++;
+ 80391fc:	008201b4 	movhi	r2,2054
+ 8039200:	10b93c17 	ldw	r2,-6928(r2)
+ 8039204:	10c00044 	addi	r3,r2,1
+ 8039208:	008201b4 	movhi	r2,2054
+ 803920c:	10f93c15 	stw	r3,-6928(r2)
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 8039210:	d0a06617 	ldw	r2,-32360(gp)
+ 8039214:	1081000c 	andi	r2,r2,1024
+ 8039218:	10001426 	beq	r2,zero,803926c <icmprcv+0x2f4>
+ 803921c:	d0a06617 	ldw	r2,-32360(gp)
+ 8039220:	1080800c 	andi	r2,r2,512
+ 8039224:	10001126 	beq	r2,zero,803926c <icmprcv+0x2f4>
+         dprintf("ICMP: echo reply to %u.%u.%u.%u\n", PUSH_IPADDR(host));
+ 8039228:	e0bffa17 	ldw	r2,-24(fp)
+ 803922c:	10c03fcc 	andi	r3,r2,255
+ 8039230:	e0bffa17 	ldw	r2,-24(fp)
+ 8039234:	1004d23a 	srli	r2,r2,8
+ 8039238:	11003fcc 	andi	r4,r2,255
+ 803923c:	e0bffa17 	ldw	r2,-24(fp)
+ 8039240:	1004d43a 	srli	r2,r2,16
+ 8039244:	11403fcc 	andi	r5,r2,255
+ 8039248:	e0bffa17 	ldw	r2,-24(fp)
+ 803924c:	1004d63a 	srli	r2,r2,24
+ 8039250:	d8800015 	stw	r2,0(sp)
+ 8039254:	280f883a 	mov	r7,r5
+ 8039258:	200d883a 	mov	r6,r4
+ 803925c:	180b883a 	mov	r5,r3
+ 8039260:	01020174 	movhi	r4,2053
+ 8039264:	212b5e04 	addi	r4,r4,-21128
+ 8039268:	8002c780 	call	8002c78 <printf>
+#endif
+      e->ptype = ECHOREP;
+ 803926c:	e0bff917 	ldw	r2,-28(fp)
+ 8039270:	10000005 	stb	zero,0(r2)
+      e->pchksum = 0;
+ 8039274:	e0bff917 	ldw	r2,-28(fp)
+ 8039278:	1000008d 	sth	zero,2(r2)
+      if (len&1)  /* pad odd length packets for checksum routine */
+ 803927c:	e0bffb17 	ldw	r2,-20(fp)
+ 8039280:	1080004c 	andi	r2,r2,1
+ 8039284:	10000926 	beq	r2,zero,80392ac <icmprcv+0x334>
+      {
+         sav_ch = *(((char *) e) + len);
+ 8039288:	e0fff917 	ldw	r3,-28(fp)
+ 803928c:	e0bffb17 	ldw	r2,-20(fp)
+ 8039290:	1885883a 	add	r2,r3,r2
+ 8039294:	10800003 	ldbu	r2,0(r2)
+ 8039298:	e0bffdc5 	stb	r2,-9(fp)
+         ((char *)e)[len] = 0;
+ 803929c:	e0fff917 	ldw	r3,-28(fp)
+ 80392a0:	e0bffb17 	ldw	r2,-20(fp)
+ 80392a4:	1885883a 	add	r2,r3,r2
+ 80392a8:	10000005 	stb	zero,0(r2)
+      }
+
+      e->pchksum = ~cksum(e, (len+1)>>1);
+ 80392ac:	e0bffb17 	ldw	r2,-20(fp)
+ 80392b0:	10800044 	addi	r2,r2,1
+ 80392b4:	1004d07a 	srli	r2,r2,1
+ 80392b8:	100b883a 	mov	r5,r2
+ 80392bc:	e13ff917 	ldw	r4,-28(fp)
+ 80392c0:	8026d7c0 	call	8026d7c <cksum>
+ 80392c4:	0084303a 	nor	r2,zero,r2
+ 80392c8:	1007883a 	mov	r3,r2
+ 80392cc:	e0bff917 	ldw	r2,-28(fp)
+ 80392d0:	10c0008d 	sth	r3,2(r2)
+      if (len&1) *(((char *) e) + len) = sav_ch;
+ 80392d4:	e0bffb17 	ldw	r2,-20(fp)
+ 80392d8:	1080004c 	andi	r2,r2,1
+ 80392dc:	10000526 	beq	r2,zero,80392f4 <icmprcv+0x37c>
+ 80392e0:	e0fff917 	ldw	r3,-28(fp)
+ 80392e4:	e0bffb17 	ldw	r2,-20(fp)
+ 80392e8:	1885883a 	add	r2,r3,r2
+ 80392ec:	e0fffdc3 	ldbu	r3,-9(fp)
+ 80392f0:	10c00005 	stb	r3,0(r2)
+      /* check to see if the destination is the IPv4 broadcast address,
+       * or if the destination is a multicast group address, or if the
+       * destination address is the subnet-directed broadcast 
+       */
+      if ((pip->ip_dest == 0xffffffff) || 
+ 80392f4:	e0bffc17 	ldw	r2,-16(fp)
+ 80392f8:	10800417 	ldw	r2,16(r2)
+ 80392fc:	10bfffe0 	cmpeqi	r2,r2,-1
+ 8039300:	10001f1e 	bne	r2,zero,8039380 <icmprcv+0x408>
+#ifdef IP_MULTICAST
+          (IN_MULTICAST(ntohl(pip->ip_dest))) ||
+ 8039304:	e0bffc17 	ldw	r2,-16(fp)
+ 8039308:	10800417 	ldw	r2,16(r2)
+ 803930c:	1006d63a 	srli	r3,r2,24
+ 8039310:	e0bffc17 	ldw	r2,-16(fp)
+ 8039314:	10800417 	ldw	r2,16(r2)
+ 8039318:	1004d23a 	srli	r2,r2,8
+ 803931c:	10bfc00c 	andi	r2,r2,65280
+ 8039320:	1886b03a 	or	r3,r3,r2
+ 8039324:	e0bffc17 	ldw	r2,-16(fp)
+ 8039328:	10800417 	ldw	r2,16(r2)
+ 803932c:	1004923a 	slli	r2,r2,8
+ 8039330:	10803fec 	andhi	r2,r2,255
+ 8039334:	1886b03a 	or	r3,r3,r2
+ 8039338:	e0bffc17 	ldw	r2,-16(fp)
+ 803933c:	10800417 	ldw	r2,16(r2)
+ 8039340:	1004963a 	slli	r2,r2,24
+ 8039344:	1884b03a 	or	r2,r3,r2
+ 8039348:	10fc002c 	andhi	r3,r2,61440
+      if ((pip->ip_dest == 0xffffffff) || 
+ 803934c:	00b80034 	movhi	r2,57344
+ 8039350:	18800b26 	beq	r3,r2,8039380 <icmprcv+0x408>
+#endif
+          (pip->ip_dest == (p->net->n_ipaddr | (~(p->net->snmask)))))
+ 8039354:	e0bffc17 	ldw	r2,-16(fp)
+ 8039358:	10c00417 	ldw	r3,16(r2)
+ 803935c:	e0bff317 	ldw	r2,-52(fp)
+ 8039360:	10800617 	ldw	r2,24(r2)
+ 8039364:	11000a17 	ldw	r4,40(r2)
+ 8039368:	e0bff317 	ldw	r2,-52(fp)
+ 803936c:	10800617 	ldw	r2,24(r2)
+ 8039370:	10800c17 	ldw	r2,48(r2)
+ 8039374:	0084303a 	nor	r2,zero,r2
+ 8039378:	2084b03a 	or	r2,r4,r2
+          (IN_MULTICAST(ntohl(pip->ip_dest))) ||
+ 803937c:	1880061e 	bne	r3,r2,8039398 <icmprcv+0x420>
+      {
+         pip->ip_src = p->net->n_ipaddr;
+ 8039380:	e0bff317 	ldw	r2,-52(fp)
+ 8039384:	10800617 	ldw	r2,24(r2)
+ 8039388:	10c00a17 	ldw	r3,40(r2)
+ 803938c:	e0bffc17 	ldw	r2,-16(fp)
+ 8039390:	10c00315 	stw	r3,12(r2)
+ 8039394:	00000406 	br	80393a8 <icmprcv+0x430>
+      }
+      else pip->ip_src = pip->ip_dest;
+ 8039398:	e0bffc17 	ldw	r2,-16(fp)
+ 803939c:	10c00417 	ldw	r3,16(r2)
+ 80393a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80393a4:	10c00315 	stw	r3,12(r2)
+
+      pip->ip_dest = host;
+ 80393a8:	e0bffc17 	ldw	r2,-16(fp)
+ 80393ac:	e0fffa17 	ldw	r3,-24(fp)
+ 80393b0:	10c00415 	stw	r3,16(r2)
+      icmp_mib.icmpOutEchoReps++;
+ 80393b4:	008201b4 	movhi	r2,2054
+ 80393b8:	10b94a17 	ldw	r2,-6872(r2)
+ 80393bc:	10c00044 	addi	r3,r2,1
+ 80393c0:	008201b4 	movhi	r2,2054
+ 80393c4:	10f94a15 	stw	r3,-6872(r2)
+      icmp_mib.icmpOutMsgs++;
+ 80393c8:	008201b4 	movhi	r2,2054
+ 80393cc:	10b94217 	ldw	r2,-6904(r2)
+ 80393d0:	10c00044 	addi	r3,r2,1
+ 80393d4:	008201b4 	movhi	r2,2054
+ 80393d8:	10f94215 	stw	r3,-6904(r2)
+      p->fhost = host;
+ 80393dc:	e0bff317 	ldw	r2,-52(fp)
+ 80393e0:	e0fffa17 	ldw	r3,-24(fp)
+ 80393e4:	10c00715 	stw	r3,28(r2)
+      p->nb_prot += ip_hlen(pip);      /* move pointer past IP to ICMP */
+ 80393e8:	e0bff317 	ldw	r2,-52(fp)
+ 80393ec:	10c00317 	ldw	r3,12(r2)
+ 80393f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80393f4:	10800003 	ldbu	r2,0(r2)
+ 80393f8:	10803fcc 	andi	r2,r2,255
+ 80393fc:	100490ba 	slli	r2,r2,2
+ 8039400:	10800f0c 	andi	r2,r2,60
+ 8039404:	1887883a 	add	r3,r3,r2
+ 8039408:	e0bff317 	ldw	r2,-52(fp)
+ 803940c:	10c00315 	stw	r3,12(r2)
+      p->nb_plen = len;
+ 8039410:	e0bff317 	ldw	r2,-52(fp)
+ 8039414:	e0fffb17 	ldw	r3,-20(fp)
+ 8039418:	10c00415 	stw	r3,16(r2)
+
+      i = ip_write(ICMP_PROT, p);
+ 803941c:	e17ff317 	ldw	r5,-52(fp)
+ 8039420:	01000044 	movi	r4,1
+ 8039424:	803a9e80 	call	803a9e8 <ip_write>
+ 8039428:	e0bff715 	stw	r2,-36(fp)
+      if (i < 0)
+ 803942c:	e0bff717 	ldw	r2,-36(fp)
+ 8039430:	1000060e 	bge	r2,zero,803944c <icmprcv+0x4d4>
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (UPCTRACE))
+ 8039434:	d0a06617 	ldw	r2,-32360(gp)
+ 8039438:	1081000c 	andi	r2,r2,1024
+ 803943c:	10000326 	beq	r2,zero,803944c <icmprcv+0x4d4>
+            dprintf("icmp: reply failed\n");
+ 8039440:	01020174 	movhi	r4,2053
+ 8039444:	212b6704 	addi	r4,r4,-21092
+ 8039448:	8002d9c0 	call	8002d9c <puts>
+#endif
+      }
+      /* reused p will be freed by net->xxx_send() */
+      return 0;
+ 803944c:	0005883a 	mov	r2,zero
+ 8039450:	00017906 	br	8039a38 <icmprcv+0xac0>
+   case ECHOREP:
+      icmp_mib.icmpInEchoReps++;
+ 8039454:	008201b4 	movhi	r2,2054
+ 8039458:	10b93d17 	ldw	r2,-6924(r2)
+ 803945c:	10c00044 	addi	r3,r2,1
+ 8039460:	008201b4 	movhi	r2,2054
+ 8039464:	10f93d15 	stw	r3,-6924(r2)
+      
+/* 
+ * Altera Niche Stack Nios port modification
+ */
+#if defined(ALT_INICHE) && !defined(PING_APP) && defined(IP_RAW)
+      return(ip_raw_input(p));
+ 8039468:	e13ff317 	ldw	r4,-52(fp)
+ 803946c:	803c7d00 	call	803c7d0 <ip_raw_input>
+ 8039470:	00017106 	br	8039a38 <icmprcv+0xac0>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return(0);
+#endif   /* PING_APP */
+#ifdef FULL_ICMP
+   case DESTIN:
+      icmp_mib.icmpInDestUnreachs++;
+ 8039474:	008201b4 	movhi	r2,2054
+ 8039478:	10b93717 	ldw	r2,-6948(r2)
+ 803947c:	10c00044 	addi	r3,r2,1
+ 8039480:	008201b4 	movhi	r2,2054
+ 8039484:	10f93715 	stw	r3,-6948(r2)
+      pdp = (struct destun *)e;
+ 8039488:	e0bff917 	ldw	r2,-28(fp)
+ 803948c:	e0bff615 	stw	r2,-40(fp)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 8039490:	d0a06617 	ldw	r2,-32360(gp)
+ 8039494:	1081000c 	andi	r2,r2,1024
+ 8039498:	10002f26 	beq	r2,zero,8039558 <icmprcv+0x5e0>
+      {
+         dprintf("ICMP: got dest unreachable type ");
+ 803949c:	01020174 	movhi	r4,2053
+ 80394a0:	212b6c04 	addi	r4,r4,-21072
+ 80394a4:	8002c780 	call	8002c78 <printf>
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+ 80394a8:	e0bff617 	ldw	r2,-40(fp)
+ 80394ac:	10800043 	ldbu	r2,1(r2)
+ 80394b0:	11003fcc 	andi	r4,r2,255
+ 80394b4:	2100201c 	xori	r4,r4,128
+ 80394b8:	213fe004 	addi	r4,r4,-128
+          PUSH_IPADDR(pdp->dip.ip_dest));
+ 80394bc:	e0bff617 	ldw	r2,-40(fp)
+ 80394c0:	10800617 	ldw	r2,24(r2)
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+ 80394c4:	11403fcc 	andi	r5,r2,255
+          PUSH_IPADDR(pdp->dip.ip_dest));
+ 80394c8:	e0bff617 	ldw	r2,-40(fp)
+ 80394cc:	10800617 	ldw	r2,24(r2)
+ 80394d0:	1004d23a 	srli	r2,r2,8
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+ 80394d4:	11803fcc 	andi	r6,r2,255
+          PUSH_IPADDR(pdp->dip.ip_dest));
+ 80394d8:	e0bff617 	ldw	r2,-40(fp)
+ 80394dc:	10800617 	ldw	r2,24(r2)
+ 80394e0:	1004d43a 	srli	r2,r2,16
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+ 80394e4:	10803fcc 	andi	r2,r2,255
+          PUSH_IPADDR(pdp->dip.ip_dest));
+ 80394e8:	e0fff617 	ldw	r3,-40(fp)
+ 80394ec:	18c00617 	ldw	r3,24(r3)
+ 80394f0:	1806d63a 	srli	r3,r3,24
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+ 80394f4:	d8c00115 	stw	r3,4(sp)
+ 80394f8:	d8800015 	stw	r2,0(sp)
+ 80394fc:	300f883a 	mov	r7,r6
+ 8039500:	280d883a 	mov	r6,r5
+ 8039504:	200b883a 	mov	r5,r4
+ 8039508:	01020174 	movhi	r4,2053
+ 803950c:	212b7504 	addi	r4,r4,-21036
+ 8039510:	8002c780 	call	8002c78 <printf>
+         dprintf("from %u.%u.%u.%u\n", PUSH_IPADDR(host));
+ 8039514:	e0bffa17 	ldw	r2,-24(fp)
+ 8039518:	10c03fcc 	andi	r3,r2,255
+ 803951c:	e0bffa17 	ldw	r2,-24(fp)
+ 8039520:	1004d23a 	srli	r2,r2,8
+ 8039524:	11003fcc 	andi	r4,r2,255
+ 8039528:	e0bffa17 	ldw	r2,-24(fp)
+ 803952c:	1004d43a 	srli	r2,r2,16
+ 8039530:	11403fcc 	andi	r5,r2,255
+ 8039534:	e0bffa17 	ldw	r2,-24(fp)
+ 8039538:	1004d63a 	srli	r2,r2,24
+ 803953c:	d8800015 	stw	r2,0(sp)
+ 8039540:	280f883a 	mov	r7,r5
+ 8039544:	200d883a 	mov	r6,r4
+ 8039548:	180b883a 	mov	r5,r3
+ 803954c:	01020174 	movhi	r4,2053
+ 8039550:	212b7a04 	addi	r4,r4,-21016
+ 8039554:	8002c780 	call	8002c78 <printf>
+      }
+#endif   /* NPDEBUG */
+      icmp_du(p, pdp);
+ 8039558:	e17ff617 	ldw	r5,-40(fp)
+ 803955c:	e13ff317 	ldw	r4,-52(fp)
+ 8039560:	803a01c0 	call	803a01c <icmp_du>
+      break;
+ 8039564:	00013306 	br	8039a34 <icmprcv+0xabc>
+   case SOURCEQ:
+      icmp_mib.icmpInSrcQuenchs++;
+ 8039568:	008201b4 	movhi	r2,2054
+ 803956c:	10b93a17 	ldw	r2,-6936(r2)
+ 8039570:	10c00044 	addi	r3,r2,1
+ 8039574:	008201b4 	movhi	r2,2054
+ 8039578:	10f93a15 	stw	r3,-6936(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 803957c:	d0a06617 	ldw	r2,-32360(gp)
+ 8039580:	1081000c 	andi	r2,r2,1024
+ 8039584:	10001626 	beq	r2,zero,80395e0 <icmprcv+0x668>
+      {
+         dprintf("ICMP: source quench from %u.%u.%u.%u\n", PUSH_IPADDR(host));
+ 8039588:	e0bffa17 	ldw	r2,-24(fp)
+ 803958c:	10c03fcc 	andi	r3,r2,255
+ 8039590:	e0bffa17 	ldw	r2,-24(fp)
+ 8039594:	1004d23a 	srli	r2,r2,8
+ 8039598:	11003fcc 	andi	r4,r2,255
+ 803959c:	e0bffa17 	ldw	r2,-24(fp)
+ 80395a0:	1004d43a 	srli	r2,r2,16
+ 80395a4:	11403fcc 	andi	r5,r2,255
+ 80395a8:	e0bffa17 	ldw	r2,-24(fp)
+ 80395ac:	1004d63a 	srli	r2,r2,24
+ 80395b0:	d8800015 	stw	r2,0(sp)
+ 80395b4:	280f883a 	mov	r7,r5
+ 80395b8:	200d883a 	mov	r6,r4
+ 80395bc:	180b883a 	mov	r5,r3
+ 80395c0:	01020174 	movhi	r4,2053
+ 80395c4:	212b7f04 	addi	r4,r4,-20996
+ 80395c8:	8002c780 	call	8002c78 <printf>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 80395cc:	d0a06617 	ldw	r2,-32360(gp)
+ 80395d0:	1080008c 	andi	r2,r2,2
+ 80395d4:	10000226 	beq	r2,zero,80395e0 <icmprcv+0x668>
+ 80395d8:	e13ff317 	ldw	r4,-52(fp)
+ 80395dc:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 80395e0:	01000084 	movi	r4,2
+ 80395e4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 80395e8:	e13ff317 	ldw	r4,-52(fp)
+ 80395ec:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 80395f0:	01000084 	movi	r4,2
+ 80395f4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      break;
+ 80395f8:	00010e06 	br	8039a34 <icmprcv+0xabc>
+   case REDIR:          /* got an icmp redirect */
+      icmp_mib.icmpInRedirects++;
+ 80395fc:	008201b4 	movhi	r2,2054
+ 8039600:	10b93b17 	ldw	r2,-6932(r2)
+ 8039604:	10c00044 	addi	r3,r2,1
+ 8039608:	008201b4 	movhi	r2,2054
+ 803960c:	10f93b15 	stw	r3,-6932(r2)
+      rd = (struct redirect *)e;
+ 8039610:	e0bff917 	ldw	r2,-28(fp)
+ 8039614:	e0bff515 	stw	r2,-44(fp)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 8039618:	d0a06617 	ldw	r2,-32360(gp)
+ 803961c:	1081000c 	andi	r2,r2,1024
+ 8039620:	10002a26 	beq	r2,zero,80396cc <icmprcv+0x754>
+      {
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+          PUSH_IPADDR(rd->rdip.ip_dest));
+ 8039624:	e0bff517 	ldw	r2,-44(fp)
+ 8039628:	10800617 	ldw	r2,24(r2)
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+ 803962c:	10c03fcc 	andi	r3,r2,255
+          PUSH_IPADDR(rd->rdip.ip_dest));
+ 8039630:	e0bff517 	ldw	r2,-44(fp)
+ 8039634:	10800617 	ldw	r2,24(r2)
+ 8039638:	1004d23a 	srli	r2,r2,8
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+ 803963c:	11003fcc 	andi	r4,r2,255
+          PUSH_IPADDR(rd->rdip.ip_dest));
+ 8039640:	e0bff517 	ldw	r2,-44(fp)
+ 8039644:	10800617 	ldw	r2,24(r2)
+ 8039648:	1004d43a 	srli	r2,r2,16
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+ 803964c:	11403fcc 	andi	r5,r2,255
+          PUSH_IPADDR(rd->rdip.ip_dest));
+ 8039650:	e0bff517 	ldw	r2,-44(fp)
+ 8039654:	10800617 	ldw	r2,24(r2)
+ 8039658:	1004d63a 	srli	r2,r2,24
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+ 803965c:	d8800015 	stw	r2,0(sp)
+ 8039660:	280f883a 	mov	r7,r5
+ 8039664:	200d883a 	mov	r6,r4
+ 8039668:	180b883a 	mov	r5,r3
+ 803966c:	01020174 	movhi	r4,2053
+ 8039670:	212b8904 	addi	r4,r4,-20956
+ 8039674:	8002c780 	call	8002c78 <printf>
+         dprintf("to %u.%u.%u.%u\n", PUSH_IPADDR(rd->rdgw));
+ 8039678:	e0bff517 	ldw	r2,-44(fp)
+ 803967c:	10800117 	ldw	r2,4(r2)
+ 8039680:	10c03fcc 	andi	r3,r2,255
+ 8039684:	e0bff517 	ldw	r2,-44(fp)
+ 8039688:	10800117 	ldw	r2,4(r2)
+ 803968c:	1004d23a 	srli	r2,r2,8
+ 8039690:	11003fcc 	andi	r4,r2,255
+ 8039694:	e0bff517 	ldw	r2,-44(fp)
+ 8039698:	10800117 	ldw	r2,4(r2)
+ 803969c:	1004d43a 	srli	r2,r2,16
+ 80396a0:	11403fcc 	andi	r5,r2,255
+ 80396a4:	e0bff517 	ldw	r2,-44(fp)
+ 80396a8:	10800117 	ldw	r2,4(r2)
+ 80396ac:	1004d63a 	srli	r2,r2,24
+ 80396b0:	d8800015 	stw	r2,0(sp)
+ 80396b4:	280f883a 	mov	r7,r5
+ 80396b8:	200d883a 	mov	r6,r4
+ 80396bc:	180b883a 	mov	r5,r3
+ 80396c0:	01020174 	movhi	r4,2053
+ 80396c4:	212b9304 	addi	r4,r4,-20916
+ 80396c8:	8002c780 	call	8002c78 <printf>
+      }
+#endif   /* NPDEBUG */
+#ifdef IP_ROUTING
+      /* try to add/update route table */
+      add_route(rd->rdip.ip_dest, 0xFFFFFFFF, rd->rdgw, 
+ 80396cc:	e0bff517 	ldw	r2,-44(fp)
+ 80396d0:	14000617 	ldw	r16,24(r2)
+ 80396d4:	e0bff517 	ldw	r2,-44(fp)
+ 80396d8:	14400117 	ldw	r17,4(r2)
+ 80396dc:	e0bff317 	ldw	r2,-52(fp)
+ 80396e0:	10800617 	ldw	r2,24(r2)
+ 80396e4:	1009883a 	mov	r4,r2
+ 80396e8:	80252fc0 	call	80252fc <if_netnumber>
+ 80396ec:	1007883a 	mov	r3,r2
+ 80396f0:	00800104 	movi	r2,4
+ 80396f4:	d8800015 	stw	r2,0(sp)
+ 80396f8:	180f883a 	mov	r7,r3
+ 80396fc:	880d883a 	mov	r6,r17
+ 8039700:	017fffc4 	movi	r5,-1
+ 8039704:	8009883a 	mov	r4,r16
+ 8039708:	803cc7c0 	call	803cc7c <add_route>
+       net_num(p->net), IPRP_ICMP);
+#endif   /* IP_ROUTING */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803970c:	01000084 	movi	r4,2
+ 8039710:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 8039714:	e13ff317 	ldw	r4,-52(fp)
+ 8039718:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803971c:	01000084 	movi	r4,2
+ 8039720:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      break;
+ 8039724:	0000c306 	br	8039a34 <icmprcv+0xabc>
+   case TIMEX:
+      icmp_mib.icmpInTimeExcds++;
+ 8039728:	008201b4 	movhi	r2,2054
+ 803972c:	10b93817 	ldw	r2,-6944(r2)
+ 8039730:	10c00044 	addi	r3,r2,1
+ 8039734:	008201b4 	movhi	r2,2054
+ 8039738:	10f93815 	stw	r3,-6944(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 803973c:	d0a06617 	ldw	r2,-32360(gp)
+ 8039740:	1081000c 	andi	r2,r2,1024
+ 8039744:	10003126 	beq	r2,zero,803980c <icmprcv+0x894>
+      {
+         struct timex * pt =  (struct  timex *)e;
+ 8039748:	e0bff917 	ldw	r2,-28(fp)
+ 803974c:	e0bff415 	stw	r2,-48(fp)
+
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+          PUSH_IPADDR(p->fhost));
+ 8039750:	e0bff317 	ldw	r2,-52(fp)
+ 8039754:	10800717 	ldw	r2,28(r2)
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+ 8039758:	10c03fcc 	andi	r3,r2,255
+          PUSH_IPADDR(p->fhost));
+ 803975c:	e0bff317 	ldw	r2,-52(fp)
+ 8039760:	10800717 	ldw	r2,28(r2)
+ 8039764:	1004d23a 	srli	r2,r2,8
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+ 8039768:	11003fcc 	andi	r4,r2,255
+          PUSH_IPADDR(p->fhost));
+ 803976c:	e0bff317 	ldw	r2,-52(fp)
+ 8039770:	10800717 	ldw	r2,28(r2)
+ 8039774:	1004d43a 	srli	r2,r2,16
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+ 8039778:	11403fcc 	andi	r5,r2,255
+          PUSH_IPADDR(p->fhost));
+ 803977c:	e0bff317 	ldw	r2,-52(fp)
+ 8039780:	10800717 	ldw	r2,28(r2)
+ 8039784:	1004d63a 	srli	r2,r2,24
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+ 8039788:	d8800015 	stw	r2,0(sp)
+ 803978c:	280f883a 	mov	r7,r5
+ 8039790:	200d883a 	mov	r6,r4
+ 8039794:	180b883a 	mov	r5,r3
+ 8039798:	01020174 	movhi	r4,2053
+ 803979c:	212b9704 	addi	r4,r4,-20900
+ 80397a0:	8002c780 	call	8002c78 <printf>
+         dprintf(" about %u.%u.%u.%u\n", PUSH_IPADDR(pt->tip.ip_dest));
+ 80397a4:	e0bff417 	ldw	r2,-48(fp)
+ 80397a8:	10800617 	ldw	r2,24(r2)
+ 80397ac:	10c03fcc 	andi	r3,r2,255
+ 80397b0:	e0bff417 	ldw	r2,-48(fp)
+ 80397b4:	10800617 	ldw	r2,24(r2)
+ 80397b8:	1004d23a 	srli	r2,r2,8
+ 80397bc:	11003fcc 	andi	r4,r2,255
+ 80397c0:	e0bff417 	ldw	r2,-48(fp)
+ 80397c4:	10800617 	ldw	r2,24(r2)
+ 80397c8:	1004d43a 	srli	r2,r2,16
+ 80397cc:	11403fcc 	andi	r5,r2,255
+ 80397d0:	e0bff417 	ldw	r2,-48(fp)
+ 80397d4:	10800617 	ldw	r2,24(r2)
+ 80397d8:	1004d63a 	srli	r2,r2,24
+ 80397dc:	d8800015 	stw	r2,0(sp)
+ 80397e0:	280f883a 	mov	r7,r5
+ 80397e4:	200d883a 	mov	r6,r4
+ 80397e8:	180b883a 	mov	r5,r3
+ 80397ec:	01020174 	movhi	r4,2053
+ 80397f0:	212ba004 	addi	r4,r4,-20864
+ 80397f4:	8002c780 	call	8002c78 <printf>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 80397f8:	d0a06617 	ldw	r2,-32360(gp)
+ 80397fc:	1080008c 	andi	r2,r2,2
+ 8039800:	10000226 	beq	r2,zero,803980c <icmprcv+0x894>
+ 8039804:	e13ff317 	ldw	r4,-52(fp)
+ 8039808:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803980c:	01000084 	movi	r4,2
+ 8039810:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 8039814:	e13ff317 	ldw	r4,-52(fp)
+ 8039818:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803981c:	01000084 	movi	r4,2
+ 8039820:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      break;
+ 8039824:	00008306 	br	8039a34 <icmprcv+0xabc>
+   case PARAM:
+      icmp_mib.icmpInParmProbs++;
+ 8039828:	008201b4 	movhi	r2,2054
+ 803982c:	10b93917 	ldw	r2,-6940(r2)
+ 8039830:	10c00044 	addi	r3,r2,1
+ 8039834:	008201b4 	movhi	r2,2054
+ 8039838:	10f93915 	stw	r3,-6940(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 803983c:	d0a06617 	ldw	r2,-32360(gp)
+ 8039840:	1081000c 	andi	r2,r2,1024
+ 8039844:	10000326 	beq	r2,zero,8039854 <icmprcv+0x8dc>
+         dprintf("ICMP: got param problem message\n");
+ 8039848:	01020174 	movhi	r4,2053
+ 803984c:	212ba504 	addi	r4,r4,-20844
+ 8039850:	8002d9c0 	call	8002d9c <puts>
+      if (NDEBUG & DUMP)
+ 8039854:	d0a06617 	ldw	r2,-32360(gp)
+ 8039858:	1080008c 	andi	r2,r2,2
+ 803985c:	10000226 	beq	r2,zero,8039868 <icmprcv+0x8f0>
+      {
+         ip_dump(p);
+ 8039860:	e13ff317 	ldw	r4,-52(fp)
+ 8039864:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039868:	01000084 	movi	r4,2
+ 803986c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 8039870:	e13ff317 	ldw	r4,-52(fp)
+ 8039874:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039878:	01000084 	movi	r4,2
+ 803987c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      break;
+ 8039880:	00006c06 	br	8039a34 <icmprcv+0xabc>
+   case TIMEREQ:
+      icmp_mib.icmpInTimestamps++;
+ 8039884:	008201b4 	movhi	r2,2054
+ 8039888:	10b93e17 	ldw	r2,-6920(r2)
+ 803988c:	10c00044 	addi	r3,r2,1
+ 8039890:	008201b4 	movhi	r2,2054
+ 8039894:	10f93e15 	stw	r3,-6920(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 8039898:	d0a06617 	ldw	r2,-32360(gp)
+ 803989c:	1081000c 	andi	r2,r2,1024
+ 80398a0:	10000326 	beq	r2,zero,80398b0 <icmprcv+0x938>
+         dprintf("ICMP: got timestamp request\n");
+ 80398a4:	01020174 	movhi	r4,2053
+ 80398a8:	212bad04 	addi	r4,r4,-20812
+ 80398ac:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      e->ptype = TIMEREP;
+ 80398b0:	e0bff917 	ldw	r2,-28(fp)
+ 80398b4:	00c00384 	movi	r3,14
+ 80398b8:	10c00005 	stb	r3,0(r2)
+      e->pchksum = 0;
+ 80398bc:	e0bff917 	ldw	r2,-28(fp)
+ 80398c0:	1000008d 	sth	zero,2(r2)
+		   */
+		  sstmp->dtstamp[1] = sstmp->dtstamp[2] = user_UTCtime();
+	  }
+#endif /* USER_PING_TSTAMP */
+
+      e->pchksum = ~cksum(e, sizeof(struct tstamp)>>1);
+ 80398c4:	01400284 	movi	r5,10
+ 80398c8:	e13ff917 	ldw	r4,-28(fp)
+ 80398cc:	8026d7c0 	call	8026d7c <cksum>
+ 80398d0:	0084303a 	nor	r2,zero,r2
+ 80398d4:	1007883a 	mov	r3,r2
+ 80398d8:	e0bff917 	ldw	r2,-28(fp)
+ 80398dc:	10c0008d 	sth	r3,2(r2)
+      pip->ip_src = pip->ip_dest;
+ 80398e0:	e0bffc17 	ldw	r2,-16(fp)
+ 80398e4:	10c00417 	ldw	r3,16(r2)
+ 80398e8:	e0bffc17 	ldw	r2,-16(fp)
+ 80398ec:	10c00315 	stw	r3,12(r2)
+      pip->ip_dest = host;
+ 80398f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80398f4:	e0fffa17 	ldw	r3,-24(fp)
+ 80398f8:	10c00415 	stw	r3,16(r2)
+      icmp_mib.icmpOutMsgs++;
+ 80398fc:	008201b4 	movhi	r2,2054
+ 8039900:	10b94217 	ldw	r2,-6904(r2)
+ 8039904:	10c00044 	addi	r3,r2,1
+ 8039908:	008201b4 	movhi	r2,2054
+ 803990c:	10f94215 	stw	r3,-6904(r2)
+      icmp_mib.icmpOutTimestampReps++;
+ 8039910:	008201b4 	movhi	r2,2054
+ 8039914:	10b94c17 	ldw	r2,-6864(r2)
+ 8039918:	10c00044 	addi	r3,r2,1
+ 803991c:	008201b4 	movhi	r2,2054
+ 8039920:	10f94c15 	stw	r3,-6864(r2)
+      p->nb_prot += ip_hlen(pip);      /* move pointer past IP to ICMP */
+ 8039924:	e0bff317 	ldw	r2,-52(fp)
+ 8039928:	10c00317 	ldw	r3,12(r2)
+ 803992c:	e0bffc17 	ldw	r2,-16(fp)
+ 8039930:	10800003 	ldbu	r2,0(r2)
+ 8039934:	10803fcc 	andi	r2,r2,255
+ 8039938:	100490ba 	slli	r2,r2,2
+ 803993c:	10800f0c 	andi	r2,r2,60
+ 8039940:	1887883a 	add	r3,r3,r2
+ 8039944:	e0bff317 	ldw	r2,-52(fp)
+ 8039948:	10c00315 	stw	r3,12(r2)
+      p->nb_plen = sizeof(struct tstamp);
+ 803994c:	e0bff317 	ldw	r2,-52(fp)
+ 8039950:	00c00504 	movi	r3,20
+ 8039954:	10c00415 	stw	r3,16(r2)
+      p->fhost = host;
+ 8039958:	e0bff317 	ldw	r2,-52(fp)
+ 803995c:	e0fffa17 	ldw	r3,-24(fp)
+ 8039960:	10c00715 	stw	r3,28(r2)
+      i = ip_write(ICMP_PROT, p);
+ 8039964:	e17ff317 	ldw	r5,-52(fp)
+ 8039968:	01000044 	movi	r4,1
+ 803996c:	803a9e80 	call	803a9e8 <ip_write>
+ 8039970:	e0bff715 	stw	r2,-36(fp)
+      if (i < 0)
+ 8039974:	e0bff717 	ldw	r2,-36(fp)
+ 8039978:	1000060e 	bge	r2,zero,8039994 <icmprcv+0xa1c>
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & UPCTRACE)
+ 803997c:	d0a06617 	ldw	r2,-32360(gp)
+ 8039980:	1081000c 	andi	r2,r2,1024
+ 8039984:	10000326 	beq	r2,zero,8039994 <icmprcv+0xa1c>
+            dprintf("icmp: can't send timestamp reply\n");
+ 8039988:	01020174 	movhi	r4,2053
+ 803998c:	212bb404 	addi	r4,r4,-20784
+ 8039990:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      }
+      /* re-used packet was pk_free()d by net->send() */
+      return (0);
+ 8039994:	0005883a 	mov	r2,zero
+ 8039998:	00002706 	br	8039a38 <icmprcv+0xac0>
+   case INFO:
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 803999c:	d0a06617 	ldw	r2,-32360(gp)
+ 80399a0:	1081000c 	andi	r2,r2,1024
+ 80399a4:	10000326 	beq	r2,zero,80399b4 <icmprcv+0xa3c>
+         dprintf("icmp: got info request\n");
+ 80399a8:	01020174 	movhi	r4,2053
+ 80399ac:	212bbd04 	addi	r4,r4,-20748
+ 80399b0:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 80399b4:	01000084 	movi	r4,2
+ 80399b8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 80399bc:	e13ff317 	ldw	r4,-52(fp)
+ 80399c0:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 80399c4:	01000084 	movi	r4,2
+ 80399c8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      break;
+ 80399cc:	00001906 	br	8039a34 <icmprcv+0xabc>
+#endif   /* FULL_ICMP */
+   default:
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+ 80399d0:	d0a06617 	ldw	r2,-32360(gp)
+ 80399d4:	1081000c 	andi	r2,r2,1024
+ 80399d8:	10000e26 	beq	r2,zero,8039a14 <icmprcv+0xa9c>
+      {
+         dprintf("icmp: unhandled type %u\n", e->ptype);
+ 80399dc:	e0bff917 	ldw	r2,-28(fp)
+ 80399e0:	10800003 	ldbu	r2,0(r2)
+ 80399e4:	10803fcc 	andi	r2,r2,255
+ 80399e8:	1080201c 	xori	r2,r2,128
+ 80399ec:	10bfe004 	addi	r2,r2,-128
+ 80399f0:	100b883a 	mov	r5,r2
+ 80399f4:	01020174 	movhi	r4,2053
+ 80399f8:	212bc304 	addi	r4,r4,-20724
+ 80399fc:	8002c780 	call	8002c78 <printf>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 8039a00:	d0a06617 	ldw	r2,-32360(gp)
+ 8039a04:	1080008c 	andi	r2,r2,2
+ 8039a08:	10000226 	beq	r2,zero,8039a14 <icmprcv+0xa9c>
+ 8039a0c:	e13ff317 	ldw	r4,-52(fp)
+ 8039a10:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039a14:	01000084 	movi	r4,2
+ 8039a18:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 8039a1c:	e13ff317 	ldw	r4,-52(fp)
+ 8039a20:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039a24:	01000084 	movi	r4,2
+ 8039a28:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ENP_NOT_MINE;
+ 8039a2c:	00800084 	movi	r2,2
+ 8039a30:	00000106 	br	8039a38 <icmprcv+0xac0>
+   }
+#ifdef FULL_ICMP
+   return ENP_NOT_MINE;
+ 8039a34:	00800084 	movi	r2,2
+#endif   /* FULL_ICMP */
+}
+ 8039a38:	e6fffe04 	addi	sp,fp,-8
+ 8039a3c:	dfc00317 	ldw	ra,12(sp)
+ 8039a40:	df000217 	ldw	fp,8(sp)
+ 8039a44:	dc400117 	ldw	r17,4(sp)
+ 8039a48:	dc000017 	ldw	r16,0(sp)
+ 8039a4c:	dec00404 	addi	sp,sp,16
+ 8039a50:	f800283a 	ret
+
+08039a54 <icmp_destun>:
+icmp_destun(ip_addr host,  /* host to complain to */
+   ip_addr src_addr, /* source address for outgoing ICMP/IP packet header */
+   struct ip * ip,   /* IP header of offending packet */
+   unsigned typecode,    /* type & code of DU to send (PROT, PORT, HOST) */
+   NET   net)        /* interface that this packet came in on */
+{
+ 8039a54:	defff404 	addi	sp,sp,-48
+ 8039a58:	dfc00b15 	stw	ra,44(sp)
+ 8039a5c:	df000a15 	stw	fp,40(sp)
+ 8039a60:	df000a04 	addi	fp,sp,40
+ 8039a64:	e13ffb15 	stw	r4,-20(fp)
+ 8039a68:	e17ffa15 	stw	r5,-24(fp)
+ 8039a6c:	e1bff915 	stw	r6,-28(fp)
+ 8039a70:	e1fff815 	stw	r7,-32(fp)
+   struct destun *   d;
+   struct ip * pip;
+   int   i;
+
+#ifdef NPDEBUG
+   if (NDEBUG & PROTERR)
+ 8039a74:	d0a06617 	ldw	r2,-32360(gp)
+ 8039a78:	1080040c 	andi	r2,r2,16
+ 8039a7c:	10001826 	beq	r2,zero,8039ae0 <icmp_destun+0x8c>
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+      dsts[typecode & 0xFF], PUSH_IPADDR(host));
+ 8039a80:	e0bff817 	ldw	r2,-32(fp)
+ 8039a84:	10803fcc 	andi	r2,r2,255
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+ 8039a88:	100690ba 	slli	r3,r2,2
+ 8039a8c:	00820174 	movhi	r2,2053
+ 8039a90:	1885883a 	add	r2,r3,r2
+ 8039a94:	11325017 	ldw	r4,-14016(r2)
+ 8039a98:	e0bffb17 	ldw	r2,-20(fp)
+ 8039a9c:	11403fcc 	andi	r5,r2,255
+      dsts[typecode & 0xFF], PUSH_IPADDR(host));
+ 8039aa0:	e0bffb17 	ldw	r2,-20(fp)
+ 8039aa4:	1004d23a 	srli	r2,r2,8
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+ 8039aa8:	11803fcc 	andi	r6,r2,255
+      dsts[typecode & 0xFF], PUSH_IPADDR(host));
+ 8039aac:	e0bffb17 	ldw	r2,-20(fp)
+ 8039ab0:	1004d43a 	srli	r2,r2,16
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+ 8039ab4:	10803fcc 	andi	r2,r2,255
+      dsts[typecode & 0xFF], PUSH_IPADDR(host));
+ 8039ab8:	e0fffb17 	ldw	r3,-20(fp)
+ 8039abc:	1806d63a 	srli	r3,r3,24
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+ 8039ac0:	d8c00115 	stw	r3,4(sp)
+ 8039ac4:	d8800015 	stw	r2,0(sp)
+ 8039ac8:	300f883a 	mov	r7,r6
+ 8039acc:	280d883a 	mov	r6,r5
+ 8039ad0:	200b883a 	mov	r5,r4
+ 8039ad4:	01020174 	movhi	r4,2053
+ 8039ad8:	212bdd04 	addi	r4,r4,-20620
+ 8039adc:	8002c780 	call	8002c78 <printf>
+#endif   /* NPDEBUG */
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039ae0:	01000084 	movi	r4,2
+ 8039ae4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   p = pk_alloc(512 + IPHSIZ);   /* get packet to send icmp dest unreachable */
+ 8039ae8:	01008504 	movi	r4,532
+ 8039aec:	80284340 	call	8028434 <pk_alloc>
+ 8039af0:	e0bfff15 	stw	r2,-4(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039af4:	01000084 	movi	r4,2
+ 8039af8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (p == NULL)
+ 8039afc:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b00:	10000c1e 	bne	r2,zero,8039b34 <icmp_destun+0xe0>
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & IPTRACE)
+ 8039b04:	d0a06617 	ldw	r2,-32360(gp)
+ 8039b08:	1080800c 	andi	r2,r2,512
+ 8039b0c:	10000326 	beq	r2,zero,8039b1c <icmp_destun+0xc8>
+         dprintf("icmp: can't alloc pkt\n");
+ 8039b10:	01020174 	movhi	r4,2053
+ 8039b14:	212bea04 	addi	r4,r4,-20568
+ 8039b18:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      icmp_mib.icmpOutErrors++;
+ 8039b1c:	008201b4 	movhi	r2,2054
+ 8039b20:	10b94317 	ldw	r2,-6900(r2)
+ 8039b24:	10c00044 	addi	r3,r2,1
+ 8039b28:	008201b4 	movhi	r2,2054
+ 8039b2c:	10f94315 	stw	r3,-6900(r2)
+      return;
+ 8039b30:	00007906 	br	8039d18 <icmp_destun+0x2c4>
+   }
+
+   /* build the addresses in the IP header */
+   pip = (struct ip *)p->nb_prot;
+ 8039b34:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b38:	10800317 	ldw	r2,12(r2)
+ 8039b3c:	e0bffe15 	stw	r2,-8(fp)
+   pip->ip_src = src_addr;
+ 8039b40:	e0bffe17 	ldw	r2,-8(fp)
+ 8039b44:	e0fffa17 	ldw	r3,-24(fp)
+ 8039b48:	10c00315 	stw	r3,12(r2)
+   pip->ip_dest = host;
+ 8039b4c:	e0bffe17 	ldw	r2,-8(fp)
+ 8039b50:	e0fffb17 	ldw	r3,-20(fp)
+ 8039b54:	10c00415 	stw	r3,16(r2)
+
+   /* allow space for icmp header */
+   p->nb_prot += sizeof(struct ip);
+ 8039b58:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b5c:	10800317 	ldw	r2,12(r2)
+ 8039b60:	10c00504 	addi	r3,r2,20
+ 8039b64:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b68:	10c00315 	stw	r3,12(r2)
+   p->nb_plen -= sizeof(struct ip);
+ 8039b6c:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b70:	10800417 	ldw	r2,16(r2)
+ 8039b74:	10fffb04 	addi	r3,r2,-20
+ 8039b78:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b7c:	10c00415 	stw	r3,16(r2)
+   p->net = net;     /* Put in the interface that this packet came in on */
+ 8039b80:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b84:	e0c00217 	ldw	r3,8(fp)
+ 8039b88:	10c00615 	stw	r3,24(r2)
+
+   d = (struct destun *)p->nb_prot;
+ 8039b8c:	e0bfff17 	ldw	r2,-4(fp)
+ 8039b90:	10800317 	ldw	r2,12(r2)
+ 8039b94:	e0bffd15 	stw	r2,-12(fp)
+
+   if (typecode & 0xFF00)               /* if the type was sent */
+ 8039b98:	e0bff817 	ldw	r2,-32(fp)
+ 8039b9c:	10bfc00c 	andi	r2,r2,65280
+ 8039ba0:	10000626 	beq	r2,zero,8039bbc <icmp_destun+0x168>
+      d->dtype = (char)(typecode >>8);  /* then use it */
+ 8039ba4:	e0bff817 	ldw	r2,-32(fp)
+ 8039ba8:	1004d23a 	srli	r2,r2,8
+ 8039bac:	1007883a 	mov	r3,r2
+ 8039bb0:	e0bffd17 	ldw	r2,-12(fp)
+ 8039bb4:	10c00005 	stb	r3,0(r2)
+ 8039bb8:	00000306 	br	8039bc8 <icmp_destun+0x174>
+   else                                 /* else use default */
+      d->dtype = DESTIN;
+ 8039bbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8039bc0:	00c000c4 	movi	r3,3
+ 8039bc4:	10c00005 	stb	r3,0(r2)
+   d->dcode = (char)(typecode & 0xFF);
+ 8039bc8:	e0bff817 	ldw	r2,-32(fp)
+ 8039bcc:	1007883a 	mov	r3,r2
+ 8039bd0:	e0bffd17 	ldw	r2,-12(fp)
+ 8039bd4:	10c00045 	stb	r3,1(r2)
+   d->dno1 = d->dno2 = 0;
+ 8039bd8:	e0bffd17 	ldw	r2,-12(fp)
+ 8039bdc:	1000018d 	sth	zero,6(r2)
+ 8039be0:	e0bffd17 	ldw	r2,-12(fp)
+ 8039be4:	10c0018b 	ldhu	r3,6(r2)
+ 8039be8:	e0bffd17 	ldw	r2,-12(fp)
+ 8039bec:	10c0010d 	sth	r3,4(r2)
+#ifndef ICMP_SUPPRESS_PMTU
+   if ((typecode & 0xFF) == DSTFRAG)
+ 8039bf0:	e0bff817 	ldw	r2,-32(fp)
+ 8039bf4:	10803fcc 	andi	r2,r2,255
+ 8039bf8:	10800118 	cmpnei	r2,r2,4
+ 8039bfc:	1000121e 	bne	r2,zero,8039c48 <icmp_destun+0x1f4>
+      d->dno2 = htons(net->n_mtu - net->n_lnh);
+ 8039c00:	e0800217 	ldw	r2,8(fp)
+ 8039c04:	10c00917 	ldw	r3,36(r2)
+ 8039c08:	e0800217 	ldw	r2,8(fp)
+ 8039c0c:	10800817 	ldw	r2,32(r2)
+ 8039c10:	1885c83a 	sub	r2,r3,r2
+ 8039c14:	1005d23a 	srai	r2,r2,8
+ 8039c18:	10803fcc 	andi	r2,r2,255
+ 8039c1c:	1009883a 	mov	r4,r2
+ 8039c20:	e0800217 	ldw	r2,8(fp)
+ 8039c24:	10c00917 	ldw	r3,36(r2)
+ 8039c28:	e0800217 	ldw	r2,8(fp)
+ 8039c2c:	10800817 	ldw	r2,32(r2)
+ 8039c30:	1885c83a 	sub	r2,r3,r2
+ 8039c34:	1004923a 	slli	r2,r2,8
+ 8039c38:	2084b03a 	or	r2,r4,r2
+ 8039c3c:	1007883a 	mov	r3,r2
+ 8039c40:	e0bffd17 	ldw	r2,-12(fp)
+ 8039c44:	10c0018d 	sth	r3,6(r2)
+#endif    /* ICMP_SUPPRESS_PMTU */
+   MEMCPY(&d->dip, ip, (sizeof(struct ip) + ICMPDUDATA));
+ 8039c48:	e0bffd17 	ldw	r2,-12(fp)
+ 8039c4c:	10800204 	addi	r2,r2,8
+ 8039c50:	01800704 	movi	r6,28
+ 8039c54:	e17ff917 	ldw	r5,-28(fp)
+ 8039c58:	1009883a 	mov	r4,r2
+ 8039c5c:	80086b80 	call	80086b8 <memcpy>
+
+   d->dchksum = 0;
+ 8039c60:	e0bffd17 	ldw	r2,-12(fp)
+ 8039c64:	1000008d 	sth	zero,2(r2)
+   d->dchksum = ~cksum(d, sizeof(struct destun)>>1);
+ 8039c68:	01400484 	movi	r5,18
+ 8039c6c:	e13ffd17 	ldw	r4,-12(fp)
+ 8039c70:	8026d7c0 	call	8026d7c <cksum>
+ 8039c74:	0084303a 	nor	r2,zero,r2
+ 8039c78:	1007883a 	mov	r3,r2
+ 8039c7c:	e0bffd17 	ldw	r2,-12(fp)
+ 8039c80:	10c0008d 	sth	r3,2(r2)
+
+   p->nb_plen =  sizeof(struct destun);
+ 8039c84:	e0bfff17 	ldw	r2,-4(fp)
+ 8039c88:	00c00904 	movi	r3,36
+ 8039c8c:	10c00415 	stw	r3,16(r2)
+   p->fhost = host;
+ 8039c90:	e0bfff17 	ldw	r2,-4(fp)
+ 8039c94:	e0fffb17 	ldw	r3,-20(fp)
+ 8039c98:	10c00715 	stw	r3,28(r2)
+   i = ip_write(ICMP_PROT, p);
+ 8039c9c:	e17fff17 	ldw	r5,-4(fp)
+ 8039ca0:	01000044 	movi	r4,1
+ 8039ca4:	803a9e80 	call	803a9e8 <ip_write>
+ 8039ca8:	e0bffc15 	stw	r2,-16(fp)
+   if (i < 0)
+ 8039cac:	e0bffc17 	ldw	r2,-16(fp)
+ 8039cb0:	10000c0e 	bge	r2,zero,8039ce4 <icmp_destun+0x290>
+   {
+      icmp_mib.icmpOutErrors++;
+ 8039cb4:	008201b4 	movhi	r2,2054
+ 8039cb8:	10b94317 	ldw	r2,-6900(r2)
+ 8039cbc:	10c00044 	addi	r3,r2,1
+ 8039cc0:	008201b4 	movhi	r2,2054
+ 8039cc4:	10f94315 	stw	r3,-6900(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & (IPTRACE|NETERR|PROTERR))
+ 8039cc8:	d0a06617 	ldw	r2,-32360(gp)
+ 8039ccc:	1080860c 	andi	r2,r2,536
+ 8039cd0:	10001026 	beq	r2,zero,8039d14 <icmp_destun+0x2c0>
+         dprintf("ICMP: Can't send dest unreachable\n");
+ 8039cd4:	01020174 	movhi	r4,2053
+ 8039cd8:	212bf004 	addi	r4,r4,-20544
+ 8039cdc:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG  */
+      return;
+ 8039ce0:	00000c06 	br	8039d14 <icmp_destun+0x2c0>
+   }
+   icmp_mib.icmpOutMsgs++;
+ 8039ce4:	008201b4 	movhi	r2,2054
+ 8039ce8:	10b94217 	ldw	r2,-6904(r2)
+ 8039cec:	10c00044 	addi	r3,r2,1
+ 8039cf0:	008201b4 	movhi	r2,2054
+ 8039cf4:	10f94215 	stw	r3,-6904(r2)
+   icmp_mib.icmpOutDestUnreachs++;
+ 8039cf8:	008201b4 	movhi	r2,2054
+ 8039cfc:	10b94417 	ldw	r2,-6896(r2)
+ 8039d00:	10c00044 	addi	r3,r2,1
+ 8039d04:	008201b4 	movhi	r2,2054
+ 8039d08:	10f94415 	stw	r3,-6896(r2)
+   return;
+ 8039d0c:	0001883a 	nop
+ 8039d10:	00000106 	br	8039d18 <icmp_destun+0x2c4>
+      return;
+ 8039d14:	0001883a 	nop
+}
+ 8039d18:	e037883a 	mov	sp,fp
+ 8039d1c:	dfc00117 	ldw	ra,4(sp)
+ 8039d20:	df000017 	ldw	fp,0(sp)
+ 8039d24:	dec00204 	addi	sp,sp,8
+ 8039d28:	f800283a 	ret
+
+08039d2c <icmp_timex>:
+ *
+ * RETURNS: void
+ */
+
+void icmp_timex (struct ip * ip, char code) 
+{
+ 8039d2c:	defff504 	addi	sp,sp,-44
+ 8039d30:	dfc00a15 	stw	ra,40(sp)
+ 8039d34:	df000915 	stw	fp,36(sp)
+ 8039d38:	df000904 	addi	fp,sp,36
+ 8039d3c:	e13ffa15 	stw	r4,-24(fp)
+ 8039d40:	2805883a 	mov	r2,r5
+ 8039d44:	e0bff905 	stb	r2,-28(fp)
+   struct ip * pip;
+   int i;
+   u_char icmp_pkt_len;
+
+#ifdef NPDEBUG
+   if (NDEBUG & PROTERR)
+ 8039d48:	d0a06617 	ldw	r2,-32360(gp)
+ 8039d4c:	1080040c 	andi	r2,r2,16
+ 8039d50:	10003026 	beq	r2,zero,8039e14 <icmp_timex+0xe8>
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+ 8039d54:	e17ff907 	ldb	r5,-28(fp)
+       code, PUSH_IPADDR((ntohs(ip->ip_src))));
+ 8039d58:	e0bffa17 	ldw	r2,-24(fp)
+ 8039d5c:	10800317 	ldw	r2,12(r2)
+ 8039d60:	1004d23a 	srli	r2,r2,8
+ 8039d64:	10c03fcc 	andi	r3,r2,255
+ 8039d68:	e0bffa17 	ldw	r2,-24(fp)
+ 8039d6c:	10800317 	ldw	r2,12(r2)
+ 8039d70:	1004923a 	slli	r2,r2,8
+ 8039d74:	10bfffcc 	andi	r2,r2,65535
+ 8039d78:	1884b03a 	or	r2,r3,r2
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+ 8039d7c:	11803fcc 	andi	r6,r2,255
+       code, PUSH_IPADDR((ntohs(ip->ip_src))));
+ 8039d80:	e0bffa17 	ldw	r2,-24(fp)
+ 8039d84:	10800317 	ldw	r2,12(r2)
+ 8039d88:	1004d23a 	srli	r2,r2,8
+ 8039d8c:	10c03fcc 	andi	r3,r2,255
+ 8039d90:	e0bffa17 	ldw	r2,-24(fp)
+ 8039d94:	10800317 	ldw	r2,12(r2)
+ 8039d98:	1004923a 	slli	r2,r2,8
+ 8039d9c:	10bfffcc 	andi	r2,r2,65535
+ 8039da0:	1884b03a 	or	r2,r3,r2
+ 8039da4:	1004d23a 	srli	r2,r2,8
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+ 8039da8:	11c03fcc 	andi	r7,r2,255
+       code, PUSH_IPADDR((ntohs(ip->ip_src))));
+ 8039dac:	e0bffa17 	ldw	r2,-24(fp)
+ 8039db0:	10800317 	ldw	r2,12(r2)
+ 8039db4:	1004d23a 	srli	r2,r2,8
+ 8039db8:	10c03fcc 	andi	r3,r2,255
+ 8039dbc:	e0bffa17 	ldw	r2,-24(fp)
+ 8039dc0:	10800317 	ldw	r2,12(r2)
+ 8039dc4:	1004923a 	slli	r2,r2,8
+ 8039dc8:	10bfffcc 	andi	r2,r2,65535
+ 8039dcc:	1884b03a 	or	r2,r3,r2
+ 8039dd0:	1004d43a 	srli	r2,r2,16
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+ 8039dd4:	10803fcc 	andi	r2,r2,255
+       code, PUSH_IPADDR((ntohs(ip->ip_src))));
+ 8039dd8:	e0fffa17 	ldw	r3,-24(fp)
+ 8039ddc:	18c00317 	ldw	r3,12(r3)
+ 8039de0:	1806d23a 	srli	r3,r3,8
+ 8039de4:	19003fcc 	andi	r4,r3,255
+ 8039de8:	e0fffa17 	ldw	r3,-24(fp)
+ 8039dec:	18c00317 	ldw	r3,12(r3)
+ 8039df0:	1806923a 	slli	r3,r3,8
+ 8039df4:	18ffffcc 	andi	r3,r3,65535
+ 8039df8:	20c6b03a 	or	r3,r4,r3
+ 8039dfc:	1806d63a 	srli	r3,r3,24
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+ 8039e00:	d8c00115 	stw	r3,4(sp)
+ 8039e04:	d8800015 	stw	r2,0(sp)
+ 8039e08:	01020174 	movhi	r4,2053
+ 8039e0c:	212bf904 	addi	r4,r4,-20508
+ 8039e10:	8002c780 	call	8002c78 <printf>
+#endif   /* NPDEBUG */
+
+   icmp_pkt_len = ICMPTIMEX_HDR_LEN + ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN;
+ 8039e14:	e0bffa17 	ldw	r2,-24(fp)
+ 8039e18:	10800003 	ldbu	r2,0(r2)
+ 8039e1c:	10803fcc 	andi	r2,r2,255
+ 8039e20:	100490ba 	slli	r2,r2,2
+ 8039e24:	10800f0c 	andi	r2,r2,60
+ 8039e28:	10800404 	addi	r2,r2,16
+ 8039e2c:	e0bfffc5 	stb	r2,-1(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039e30:	01000084 	movi	r4,2
+ 8039e34:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+    * length of the "outer" IP header, length of the ICMP header (ICMPTIMEX_HDR_LEN,
+    * 8 bytes), length of the "inner" IP header, and length of "user" data 
+    * (ICMPTIMEX_PAYLOAD_DATA_LEN, 8 bytes) (just past the "inner" IP header).  The 
+    * latter two items are from the packet that the ICMP Time Exceeded message is 
+    * being sent in response to. */
+   p = pk_alloc(MaxLnh + IPHSIZ + icmp_pkt_len);
+ 8039e38:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8039e3c:	d0e06417 	ldw	r3,-32368(gp)
+ 8039e40:	10c5883a 	add	r2,r2,r3
+ 8039e44:	10800504 	addi	r2,r2,20
+ 8039e48:	1009883a 	mov	r4,r2
+ 8039e4c:	80284340 	call	8028434 <pk_alloc>
+ 8039e50:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 8039e54:	01000084 	movi	r4,2
+ 8039e58:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (p == NULL)
+ 8039e5c:	e0bffe17 	ldw	r2,-8(fp)
+ 8039e60:	10000c1e 	bne	r2,zero,8039e94 <icmp_timex+0x168>
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & IPTRACE)
+ 8039e64:	d0a06617 	ldw	r2,-32360(gp)
+ 8039e68:	1080800c 	andi	r2,r2,512
+ 8039e6c:	10000326 	beq	r2,zero,8039e7c <icmp_timex+0x150>
+         dprintf("icmp: can't alloc pkt\n");
+ 8039e70:	01020174 	movhi	r4,2053
+ 8039e74:	212bea04 	addi	r4,r4,-20568
+ 8039e78:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      icmp_mib.icmpOutErrors++;
+ 8039e7c:	008201b4 	movhi	r2,2054
+ 8039e80:	10b94317 	ldw	r2,-6900(r2)
+ 8039e84:	10c00044 	addi	r3,r2,1
+ 8039e88:	008201b4 	movhi	r2,2054
+ 8039e8c:	10f94315 	stw	r3,-6900(r2)
+      return;
+ 8039e90:	00005d06 	br	803a008 <icmp_timex+0x2dc>
+   }
+
+   /* build the addresses in the IP header */
+   pip = (struct ip *)p->nb_prot;
+ 8039e94:	e0bffe17 	ldw	r2,-8(fp)
+ 8039e98:	10800317 	ldw	r2,12(r2)
+ 8039e9c:	e0bffd15 	stw	r2,-12(fp)
+   /* source IP address of packet is our address (i.e., destination IP address 
+    * in the datagram whose reassembly timed out) */
+   pip->ip_src = ip->ip_dest;
+ 8039ea0:	e0bffa17 	ldw	r2,-24(fp)
+ 8039ea4:	10c00417 	ldw	r3,16(r2)
+ 8039ea8:	e0bffd17 	ldw	r2,-12(fp)
+ 8039eac:	10c00315 	stw	r3,12(r2)
+   /* the destination address is the same as the source IP address of the 
+    * datagram whose reassembly timed out */
+   pip->ip_dest = ip->ip_src;
+ 8039eb0:	e0bffa17 	ldw	r2,-24(fp)
+ 8039eb4:	10c00317 	ldw	r3,12(r2)
+ 8039eb8:	e0bffd17 	ldw	r2,-12(fp)
+ 8039ebc:	10c00415 	stw	r3,16(r2)
+
+   /* move past space for IP header to get to start of ICMP header */
+   p->nb_prot += sizeof(struct ip);
+ 8039ec0:	e0bffe17 	ldw	r2,-8(fp)
+ 8039ec4:	10800317 	ldw	r2,12(r2)
+ 8039ec8:	10c00504 	addi	r3,r2,20
+ 8039ecc:	e0bffe17 	ldw	r2,-8(fp)
+ 8039ed0:	10c00315 	stw	r3,12(r2)
+
+   tx = (struct timex *) p->nb_prot;
+ 8039ed4:	e0bffe17 	ldw	r2,-8(fp)
+ 8039ed8:	10800317 	ldw	r2,12(r2)
+ 8039edc:	e0bffc15 	stw	r2,-16(fp)
+
+   tx->ttype = TIMEX;
+ 8039ee0:	e0bffc17 	ldw	r2,-16(fp)
+ 8039ee4:	00c002c4 	movi	r3,11
+ 8039ee8:	10c00005 	stb	r3,0(r2)
+   tx->tcode = code;
+ 8039eec:	e0bffc17 	ldw	r2,-16(fp)
+ 8039ef0:	e0fff903 	ldbu	r3,-28(fp)
+ 8039ef4:	10c00045 	stb	r3,1(r2)
+   tx->tno1 = tx->tno2 = 0;
+ 8039ef8:	e0bffc17 	ldw	r2,-16(fp)
+ 8039efc:	1000018d 	sth	zero,6(r2)
+ 8039f00:	e0bffc17 	ldw	r2,-16(fp)
+ 8039f04:	10c0018b 	ldhu	r3,6(r2)
+ 8039f08:	e0bffc17 	ldw	r2,-16(fp)
+ 8039f0c:	10c0010d 	sth	r3,4(r2)
+   MEMCPY(&tx->tip, ip, (ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN));
+ 8039f10:	e0bffc17 	ldw	r2,-16(fp)
+ 8039f14:	10c00204 	addi	r3,r2,8
+ 8039f18:	e0bffa17 	ldw	r2,-24(fp)
+ 8039f1c:	10800003 	ldbu	r2,0(r2)
+ 8039f20:	10803fcc 	andi	r2,r2,255
+ 8039f24:	100490ba 	slli	r2,r2,2
+ 8039f28:	10800f0c 	andi	r2,r2,60
+ 8039f2c:	10800204 	addi	r2,r2,8
+ 8039f30:	100d883a 	mov	r6,r2
+ 8039f34:	e17ffa17 	ldw	r5,-24(fp)
+ 8039f38:	1809883a 	mov	r4,r3
+ 8039f3c:	80086b80 	call	80086b8 <memcpy>
+
+   tx->tchksum = 0;
+ 8039f40:	e0bffc17 	ldw	r2,-16(fp)
+ 8039f44:	1000008d 	sth	zero,2(r2)
+   tx->tchksum = ~cksum(tx, (icmp_pkt_len>>1));
+ 8039f48:	e0bfffc3 	ldbu	r2,-1(fp)
+ 8039f4c:	1004d07a 	srli	r2,r2,1
+ 8039f50:	10803fcc 	andi	r2,r2,255
+ 8039f54:	100b883a 	mov	r5,r2
+ 8039f58:	e13ffc17 	ldw	r4,-16(fp)
+ 8039f5c:	8026d7c0 	call	8026d7c <cksum>
+ 8039f60:	0084303a 	nor	r2,zero,r2
+ 8039f64:	1007883a 	mov	r3,r2
+ 8039f68:	e0bffc17 	ldw	r2,-16(fp)
+ 8039f6c:	10c0008d 	sth	r3,2(r2)
+
+   p->nb_plen = icmp_pkt_len;
+ 8039f70:	e0ffffc3 	ldbu	r3,-1(fp)
+ 8039f74:	e0bffe17 	ldw	r2,-8(fp)
+ 8039f78:	10c00415 	stw	r3,16(r2)
+   /* p->fhost is expected to be in network byte order */
+   p->fhost = pip->ip_dest;
+ 8039f7c:	e0bffd17 	ldw	r2,-12(fp)
+ 8039f80:	10c00417 	ldw	r3,16(r2)
+ 8039f84:	e0bffe17 	ldw	r2,-8(fp)
+ 8039f88:	10c00715 	stw	r3,28(r2)
+   i = ip_write(ICMP_PROT, p);
+ 8039f8c:	e17ffe17 	ldw	r5,-8(fp)
+ 8039f90:	01000044 	movi	r4,1
+ 8039f94:	803a9e80 	call	803a9e8 <ip_write>
+ 8039f98:	e0bffb15 	stw	r2,-20(fp)
+   if (i < 0)
+ 8039f9c:	e0bffb17 	ldw	r2,-20(fp)
+ 8039fa0:	10000c0e 	bge	r2,zero,8039fd4 <icmp_timex+0x2a8>
+   {
+      icmp_mib.icmpOutErrors++;
+ 8039fa4:	008201b4 	movhi	r2,2054
+ 8039fa8:	10b94317 	ldw	r2,-6900(r2)
+ 8039fac:	10c00044 	addi	r3,r2,1
+ 8039fb0:	008201b4 	movhi	r2,2054
+ 8039fb4:	10f94315 	stw	r3,-6900(r2)
+#ifdef   NPDEBUG
+      if (NDEBUG & (IPTRACE|NETERR|PROTERR))
+ 8039fb8:	d0a06617 	ldw	r2,-32360(gp)
+ 8039fbc:	1080860c 	andi	r2,r2,536
+ 8039fc0:	10001026 	beq	r2,zero,803a004 <icmp_timex+0x2d8>
+         dprintf("ICMP: Can't send Time Exceeded\n");
+ 8039fc4:	01020174 	movhi	r4,2053
+ 8039fc8:	212c0904 	addi	r4,r4,-20444
+ 8039fcc:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG  */
+      return;
+ 8039fd0:	00000c06 	br	803a004 <icmp_timex+0x2d8>
+   }
+   icmp_mib.icmpOutMsgs++;
+ 8039fd4:	008201b4 	movhi	r2,2054
+ 8039fd8:	10b94217 	ldw	r2,-6904(r2)
+ 8039fdc:	10c00044 	addi	r3,r2,1
+ 8039fe0:	008201b4 	movhi	r2,2054
+ 8039fe4:	10f94215 	stw	r3,-6904(r2)
+   icmp_mib.icmpOutTimeExcds++;
+ 8039fe8:	008201b4 	movhi	r2,2054
+ 8039fec:	10b94517 	ldw	r2,-6892(r2)
+ 8039ff0:	10c00044 	addi	r3,r2,1
+ 8039ff4:	008201b4 	movhi	r2,2054
+ 8039ff8:	10f94515 	stw	r3,-6892(r2)
+   return;
+ 8039ffc:	0001883a 	nop
+ 803a000:	00000106 	br	803a008 <icmp_timex+0x2dc>
+      return;
+ 803a004:	0001883a 	nop
+}
+ 803a008:	e037883a 	mov	sp,fp
+ 803a00c:	dfc00117 	ldw	ra,4(sp)
+ 803a010:	df000017 	ldw	fp,0(sp)
+ 803a014:	dec00204 	addi	sp,sp,8
+ 803a018:	f800283a 	ret
+
+0803a01c <icmp_du>:
+ * RETURNS: void
+ */
+
+void  
+icmp_du(PACKET p, struct destun * pdp)
+{
+ 803a01c:	defffc04 	addi	sp,sp,-16
+ 803a020:	dfc00315 	stw	ra,12(sp)
+ 803a024:	df000215 	stw	fp,8(sp)
+ 803a028:	df000204 	addi	fp,sp,8
+ 803a02c:	e13fff15 	stw	r4,-4(fp)
+ 803a030:	e17ffe15 	stw	r5,-8(fp)
+   /* see if user app wants notification first */
+   if (icmpdu_hook)
+ 803a034:	d0a09417 	ldw	r2,-32176(gp)
+ 803a038:	10000426 	beq	r2,zero,803a04c <icmp_du+0x30>
+      icmpdu_hook(p, pdp);
+ 803a03c:	d0a09417 	ldw	r2,-32176(gp)
+ 803a040:	e17ffe17 	ldw	r5,-8(fp)
+ 803a044:	e13fff17 	ldw	r4,-4(fp)
+ 803a048:	103ee83a 	callr	r2
+
+#ifdef INCLUDE_TCP
+   /* Tell the sockets layer so it can correct the problem. */
+   so_icmpdu(p, pdp);   /* this call should free packet p */
+ 803a04c:	e17ffe17 	ldw	r5,-8(fp)
+ 803a050:	e13fff17 	ldw	r4,-4(fp)
+ 803a054:	802ad080 	call	802ad08 <so_icmpdu>
+done:
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p); /* else just free packet */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif   /* INCLUDE_TCP */
+}
+ 803a058:	0001883a 	nop
+ 803a05c:	e037883a 	mov	sp,fp
+ 803a060:	dfc00117 	ldw	ra,4(sp)
+ 803a064:	df000017 	ldw	fp,0(sp)
+ 803a068:	dec00204 	addi	sp,sp,8
+ 803a06c:	f800283a 	ret
+
+0803a070 <ip_init>:
+ * OK, else returns a non-zero error code. 
+ */
+
+int
+ip_init(void)
+{
+ 803a070:	defffe04 	addi	sp,sp,-8
+ 803a074:	dfc00115 	stw	ra,4(sp)
+ 803a078:	df000015 	stw	fp,0(sp)
+ 803a07c:	d839883a 	mov	fp,sp
+
+   /* register IP type with link layer drivers */
+   if (reg_type(IP_TYPE) != 0)
+ 803a080:	01000204 	movi	r4,8
+ 803a084:	80241c80 	call	80241c8 <reg_type>
+ 803a088:	10000526 	beq	r2,zero,803a0a0 <ip_init+0x30>
+   {   
+#ifdef NPDEBUG
+      dprintf("IP_INIT: unable to register type with MAC driver\n");
+ 803a08c:	01020174 	movhi	r4,2053
+ 803a090:	212c1104 	addi	r4,r4,-20412
+ 803a094:	8002d9c0 	call	8002d9c <puts>
+#endif
+      return(1);
+ 803a098:	00800044 	movi	r2,1
+ 803a09c:	00002506 	br	803a134 <ip_init+0xc4>
+   }
+
+   /* initialize the IP mib */
+   MEMSET(&ip_mib, 0, sizeof(ip_mib));
+ 803a0a0:	01801404 	movi	r6,80
+ 803a0a4:	000b883a 	mov	r5,zero
+ 803a0a8:	010201b4 	movhi	r4,2054
+ 803a0ac:	21394f04 	addi	r4,r4,-6852
+ 803a0b0:	80088e40 	call	80088e4 <memset>
+   ip_mib.ipForwarding = 2;   /* default to host, not gateway (router) */
+ 803a0b4:	00c00084 	movi	r3,2
+ 803a0b8:	008201b4 	movhi	r2,2054
+ 803a0bc:	10f94f15 	stw	r3,-6852(r2)
+   ip_mib.ipDefaultTTL = IP_TTL;
+ 803a0c0:	00c01004 	movi	r3,64
+ 803a0c4:	008201b4 	movhi	r2,2054
+ 803a0c8:	10f95015 	stw	r3,-6848(r2)
+
+#ifdef IP_ROUTING
+   /* alloc space for the route table */
+   rt_mib = (struct RtMib*)RT_ALLOC(ipRoutes * sizeof(struct RtMib));
+ 803a0cc:	d0a03017 	ldw	r2,-32576(gp)
+ 803a0d0:	10800f24 	muli	r2,r2,60
+ 803a0d4:	1009883a 	mov	r4,r2
+ 803a0d8:	802982c0 	call	802982c <npalloc>
+ 803a0dc:	d0a09515 	stw	r2,-32172(gp)
+   if (!rt_mib)
+ 803a0e0:	d0a09517 	ldw	r2,-32172(gp)
+ 803a0e4:	1000051e 	bne	r2,zero,803a0fc <ip_init+0x8c>
+   {
+#ifdef NPDEBUG
+      dprintf("IP_INIT ERROR: can't alloc route table\n");
+ 803a0e8:	01020174 	movhi	r4,2053
+ 803a0ec:	212c1e04 	addi	r4,r4,-20360
+ 803a0f0:	8002d9c0 	call	8002d9c <puts>
+#endif   /* NPDEBUG */
+      return(ENP_NOMEM);
+ 803a0f4:	00bffb04 	movi	r2,-20
+ 803a0f8:	00000e06 	br	803a134 <ip_init+0xc4>
+   }
+
+  MEMSET(rt_mib,0, ipRoutes * sizeof(struct RtMib)) ;
+ 803a0fc:	d0e09517 	ldw	r3,-32172(gp)
+ 803a100:	d0a03017 	ldw	r2,-32576(gp)
+ 803a104:	10800f24 	muli	r2,r2,60
+ 803a108:	100d883a 	mov	r6,r2
+ 803a10c:	000b883a 	mov	r5,zero
+ 803a110:	1809883a 	mov	r4,r3
+ 803a114:	80088e40 	call	80088e4 <memset>
+  ip_mib.ipForwarding = 1;   /* override default, be gateway (router) */
+ 803a118:	00c00044 	movi	r3,1
+ 803a11c:	008201b4 	movhi	r2,2054
+ 803a120:	10f94f15 	stw	r3,-6852(r2)
+#endif   /* IP_ROUTING */
+
+   /* set IP reassembly timeout */
+   ip_mib.ipReasmTimeout = IRE_TMO;
+ 803a124:	00c01e04 	movi	r3,120
+ 803a128:	008201b4 	movhi	r2,2054
+ 803a12c:	10f95b15 	stw	r3,-6804(r2)
+      return(1);
+   }
+#endif   /* IPSEC */
+
+   /* everything opened OK return 0 */
+   return(SUCCESS);
+ 803a130:	0005883a 	mov	r2,zero
+}
+ 803a134:	e037883a 	mov	sp,fp
+ 803a138:	dfc00117 	ldw	ra,4(sp)
+ 803a13c:	df000017 	ldw	fp,0(sp)
+ 803a140:	dec00204 	addi	sp,sp,8
+ 803a144:	f800283a 	ret
+
+0803a148 <ip_bldhead>:
+ * RETURNS: void
+ */
+
+void
+ip_bldhead(PACKET p, unsigned pid, u_char prot, unshort fragword)
+{
+ 803a148:	defff804 	addi	sp,sp,-32
+ 803a14c:	dfc00715 	stw	ra,28(sp)
+ 803a150:	df000615 	stw	fp,24(sp)
+ 803a154:	df000604 	addi	fp,sp,24
+ 803a158:	e13ffd15 	stw	r4,-12(fp)
+ 803a15c:	e17ffc15 	stw	r5,-16(fp)
+ 803a160:	3005883a 	mov	r2,r6
+ 803a164:	3807883a 	mov	r3,r7
+ 803a168:	e0bffb05 	stb	r2,-20(fp)
+ 803a16c:	1805883a 	mov	r2,r3
+ 803a170:	e0bffa0d 	sth	r2,-24(fp)
+   struct ip * pip;
+   struct ip_socopts *sopts;
+
+   /* prepend IP header to packet data */
+   p->nb_prot -= sizeof(struct ip);       /* this assumes no send options! */
+ 803a174:	e0bffd17 	ldw	r2,-12(fp)
+ 803a178:	10800317 	ldw	r2,12(r2)
+ 803a17c:	10fffb04 	addi	r3,r2,-20
+ 803a180:	e0bffd17 	ldw	r2,-12(fp)
+ 803a184:	10c00315 	stw	r3,12(r2)
+   p->nb_plen += sizeof(struct ip);
+ 803a188:	e0bffd17 	ldw	r2,-12(fp)
+ 803a18c:	10800417 	ldw	r2,16(r2)
+ 803a190:	10c00504 	addi	r3,r2,20
+ 803a194:	e0bffd17 	ldw	r2,-12(fp)
+ 803a198:	10c00415 	stw	r3,16(r2)
+
+   pip = (struct ip*)p->nb_prot;
+ 803a19c:	e0bffd17 	ldw	r2,-12(fp)
+ 803a1a0:	10800317 	ldw	r2,12(r2)
+ 803a1a4:	e0bfff15 	stw	r2,-4(fp)
+
+   pip->ip_ver_ihl = 0x45;       /* 2 nibbles; VER:4, IHL:5. */
+ 803a1a8:	e0bfff17 	ldw	r2,-4(fp)
+ 803a1ac:	00c01144 	movi	r3,69
+ 803a1b0:	10c00005 	stb	r3,0(r2)
+   pip->ip_flgs_foff = fragword; /* fragment flags and offset */
+ 803a1b4:	e0bfff17 	ldw	r2,-4(fp)
+ 803a1b8:	e0fffa0b 	ldhu	r3,-24(fp)
+ 803a1bc:	10c0018d 	sth	r3,6(r2)
+   pip->ip_id = htons((unshort)pid);   /* IP datagram ID */
+ 803a1c0:	e0bffc17 	ldw	r2,-16(fp)
+ 803a1c4:	10bfffcc 	andi	r2,r2,65535
+ 803a1c8:	1004d23a 	srli	r2,r2,8
+ 803a1cc:	1007883a 	mov	r3,r2
+ 803a1d0:	e0bffc17 	ldw	r2,-16(fp)
+ 803a1d4:	10bfffcc 	andi	r2,r2,65535
+ 803a1d8:	1004923a 	slli	r2,r2,8
+ 803a1dc:	1884b03a 	or	r2,r3,r2
+ 803a1e0:	1007883a 	mov	r3,r2
+ 803a1e4:	e0bfff17 	ldw	r2,-4(fp)
+ 803a1e8:	10c0010d 	sth	r3,4(r2)
+   pip->ip_len = htons((unshort)p->nb_plen);
+ 803a1ec:	e0bffd17 	ldw	r2,-12(fp)
+ 803a1f0:	10800417 	ldw	r2,16(r2)
+ 803a1f4:	10bfffcc 	andi	r2,r2,65535
+ 803a1f8:	1004d23a 	srli	r2,r2,8
+ 803a1fc:	1007883a 	mov	r3,r2
+ 803a200:	e0bffd17 	ldw	r2,-12(fp)
+ 803a204:	10800417 	ldw	r2,16(r2)
+ 803a208:	10bfffcc 	andi	r2,r2,65535
+ 803a20c:	1004923a 	slli	r2,r2,8
+ 803a210:	1884b03a 	or	r2,r3,r2
+ 803a214:	1007883a 	mov	r3,r2
+ 803a218:	e0bfff17 	ldw	r2,-4(fp)
+ 803a21c:	10c0008d 	sth	r3,2(r2)
+   pip->ip_prot = prot;          /* install protocol ID (TCP, UDP, etc) */
+ 803a220:	e0bfff17 	ldw	r2,-4(fp)
+ 803a224:	e0fffb03 	ldbu	r3,-20(fp)
+ 803a228:	10c00245 	stb	r3,9(r2)
+
+   /* have IP_TOS or IP_TTL been set? */
+   if ((sopts = p->soxopts))
+ 803a22c:	e0bffd17 	ldw	r2,-12(fp)
+ 803a230:	10800c17 	ldw	r2,48(r2)
+ 803a234:	e0bffe15 	stw	r2,-8(fp)
+ 803a238:	e0bffe17 	ldw	r2,-8(fp)
+ 803a23c:	10001126 	beq	r2,zero,803a284 <ip_bldhead+0x13c>
+   {
+	  /* yup */
+	  if (sopts->ip_ttl)
+ 803a240:	e0bffe17 	ldw	r2,-8(fp)
+ 803a244:	10800043 	ldbu	r2,1(r2)
+ 803a248:	10803fcc 	andi	r2,r2,255
+ 803a24c:	10000526 	beq	r2,zero,803a264 <ip_bldhead+0x11c>
+         pip->ip_time = sopts->ip_ttl;
+ 803a250:	e0bffe17 	ldw	r2,-8(fp)
+ 803a254:	10c00043 	ldbu	r3,1(r2)
+ 803a258:	e0bfff17 	ldw	r2,-4(fp)
+ 803a25c:	10c00205 	stb	r3,8(r2)
+ 803a260:	00000306 	br	803a270 <ip_bldhead+0x128>
+	  else
+         pip->ip_time = (u_char)IP_TTL;     /* default number of hops, really */
+ 803a264:	e0bfff17 	ldw	r2,-4(fp)
+ 803a268:	00c01004 	movi	r3,64
+ 803a26c:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = sopts->ip_tos;
+ 803a270:	e0bffe17 	ldw	r2,-8(fp)
+ 803a274:	10c00003 	ldbu	r3,0(r2)
+ 803a278:	e0bfff17 	ldw	r2,-4(fp)
+ 803a27c:	10c00045 	stb	r3,1(r2)
+ 803a280:	00000506 	br	803a298 <ip_bldhead+0x150>
+   }
+   else
+   {
+	  /* nope */
+      pip->ip_time = (u_char)IP_TTL;       /* default number of hops, really */
+ 803a284:	e0bfff17 	ldw	r2,-4(fp)
+ 803a288:	00c01004 	movi	r3,64
+ 803a28c:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = IP_TOS_DEFVAL;
+ 803a290:	e0bfff17 	ldw	r2,-4(fp)
+ 803a294:	10000045 	stb	zero,1(r2)
+   }
+   
+   pip->ip_chksum = IPXSUM;      /* clear checksum field for summing */
+ 803a298:	e0bfff17 	ldw	r2,-4(fp)
+ 803a29c:	1000028d 	sth	zero,10(r2)
+   pip->ip_chksum = ~cksum(pip, 10);
+ 803a2a0:	01400284 	movi	r5,10
+ 803a2a4:	e13fff17 	ldw	r4,-4(fp)
+ 803a2a8:	8026d7c0 	call	8026d7c <cksum>
+ 803a2ac:	0084303a 	nor	r2,zero,r2
+ 803a2b0:	1007883a 	mov	r3,r2
+ 803a2b4:	e0bfff17 	ldw	r2,-4(fp)
+ 803a2b8:	10c0028d 	sth	r3,10(r2)
+}
+ 803a2bc:	0001883a 	nop
+ 803a2c0:	e037883a 	mov	sp,fp
+ 803a2c4:	dfc00117 	ldw	ra,4(sp)
+ 803a2c8:	df000017 	ldw	fp,0(sp)
+ 803a2cc:	dec00204 	addi	sp,sp,8
+ 803a2d0:	f800283a 	ret
+
+0803a2d4 <ip_write_internal>:
+ * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if 
+ * waiting for ARP, else negative error code if error detected. 
+ */
+int
+ip_write_internal(PACKET p)
+{
+ 803a2d4:	defff104 	addi	sp,sp,-60
+ 803a2d8:	dfc00e15 	stw	ra,56(sp)
+ 803a2dc:	df000d15 	stw	fp,52(sp)
+ 803a2e0:	df000d04 	addi	fp,sp,52
+ 803a2e4:	e13ff615 	stw	r4,-40(fp)
+   PACKET newpkt;
+   unsigned maxbuflen;
+
+#ifdef IP_MULTICAST
+   /* If destination address is multicast, process multicast options */
+   if (IN_MULTICAST(ntohl(p->fhost)))
+ 803a2e8:	e0bff617 	ldw	r2,-40(fp)
+ 803a2ec:	10800717 	ldw	r2,28(r2)
+ 803a2f0:	1006d63a 	srli	r3,r2,24
+ 803a2f4:	e0bff617 	ldw	r2,-40(fp)
+ 803a2f8:	10800717 	ldw	r2,28(r2)
+ 803a2fc:	1004d23a 	srli	r2,r2,8
+ 803a300:	10bfc00c 	andi	r2,r2,65280
+ 803a304:	1886b03a 	or	r3,r3,r2
+ 803a308:	e0bff617 	ldw	r2,-40(fp)
+ 803a30c:	10800717 	ldw	r2,28(r2)
+ 803a310:	1004923a 	slli	r2,r2,8
+ 803a314:	10803fec 	andhi	r2,r2,255
+ 803a318:	1886b03a 	or	r3,r3,r2
+ 803a31c:	e0bff617 	ldw	r2,-40(fp)
+ 803a320:	10800717 	ldw	r2,28(r2)
+ 803a324:	1004963a 	slli	r2,r2,24
+ 803a328:	1884b03a 	or	r2,r3,r2
+ 803a32c:	10fc002c 	andhi	r3,r2,61440
+ 803a330:	00b80034 	movhi	r2,57344
+ 803a334:	1880a21e 	bne	r3,r2,803a5c0 <ip_write_internal+0x2ec>
+   {
+      if (p->imo != NULL)
+ 803a338:	e0bff617 	ldw	r2,-40(fp)
+ 803a33c:	10800b17 	ldw	r2,44(r2)
+ 803a340:	10001426 	beq	r2,zero,803a394 <ip_write_internal+0xc0>
+         if (p->imo->imo_multicast_netp)
+ 803a344:	e0bff617 	ldw	r2,-40(fp)
+ 803a348:	10800b17 	ldw	r2,44(r2)
+ 803a34c:	10800017 	ldw	r2,0(r2)
+ 803a350:	10000626 	beq	r2,zero,803a36c <ip_write_internal+0x98>
+            p->net = p->imo->imo_multicast_netp;
+ 803a354:	e0bff617 	ldw	r2,-40(fp)
+ 803a358:	10800b17 	ldw	r2,44(r2)
+ 803a35c:	10c00017 	ldw	r3,0(r2)
+ 803a360:	e0bff617 	ldw	r2,-40(fp)
+ 803a364:	10c00615 	stw	r3,24(r2)
+ 803a368:	00002106 	br	803a3f0 <ip_write_internal+0x11c>
+         else
+            p->net = iproute(p->fhost, &firsthop);
+ 803a36c:	e0bff617 	ldw	r2,-40(fp)
+ 803a370:	10800717 	ldw	r2,28(r2)
+ 803a374:	e0fff704 	addi	r3,fp,-36
+ 803a378:	180b883a 	mov	r5,r3
+ 803a37c:	1009883a 	mov	r4,r2
+ 803a380:	803b3700 	call	803b370 <iproute>
+ 803a384:	1007883a 	mov	r3,r2
+ 803a388:	e0bff617 	ldw	r2,-40(fp)
+ 803a38c:	10c00615 	stw	r3,24(r2)
+ 803a390:	00001706 	br	803a3f0 <ip_write_internal+0x11c>
+      else
+      {
+         for (i = 0; i < ifNumber; i++)
+ 803a394:	e03fff15 	stw	zero,-4(fp)
+ 803a398:	00001206 	br	803a3e4 <ip_write_internal+0x110>
+            if (nets[i]->n_mcastlist)
+ 803a39c:	e0bfff17 	ldw	r2,-4(fp)
+ 803a3a0:	100690ba 	slli	r3,r2,2
+ 803a3a4:	008201b4 	movhi	r2,2054
+ 803a3a8:	1885883a 	add	r2,r3,r2
+ 803a3ac:	10b77017 	ldw	r2,-8768(r2)
+ 803a3b0:	10802b17 	ldw	r2,172(r2)
+ 803a3b4:	10000826 	beq	r2,zero,803a3d8 <ip_write_internal+0x104>
+            {
+               p->net = nets[i];
+ 803a3b8:	e0bfff17 	ldw	r2,-4(fp)
+ 803a3bc:	100690ba 	slli	r3,r2,2
+ 803a3c0:	008201b4 	movhi	r2,2054
+ 803a3c4:	1885883a 	add	r2,r3,r2
+ 803a3c8:	10f77017 	ldw	r3,-8768(r2)
+ 803a3cc:	e0bff617 	ldw	r2,-40(fp)
+ 803a3d0:	10c00615 	stw	r3,24(r2)
+               break;
+ 803a3d4:	00000606 	br	803a3f0 <ip_write_internal+0x11c>
+         for (i = 0; i < ifNumber; i++)
+ 803a3d8:	e0bfff17 	ldw	r2,-4(fp)
+ 803a3dc:	10800044 	addi	r2,r2,1
+ 803a3e0:	e0bfff15 	stw	r2,-4(fp)
+ 803a3e4:	d0a06717 	ldw	r2,-32356(gp)
+ 803a3e8:	e0ffff17 	ldw	r3,-4(fp)
+ 803a3ec:	18bfeb36 	bltu	r3,r2,803a39c <ip_write_internal+0xc8>
+            }
+      }
+
+      /* Confirm that the outgoing interface supports multicast. */
+      if ((p->net == NULL) || (p->net->n_mcastlist) == NULL)
+ 803a3f0:	e0bff617 	ldw	r2,-40(fp)
+ 803a3f4:	10800617 	ldw	r2,24(r2)
+ 803a3f8:	10000426 	beq	r2,zero,803a40c <ip_write_internal+0x138>
+ 803a3fc:	e0bff617 	ldw	r2,-40(fp)
+ 803a400:	10800617 	ldw	r2,24(r2)
+ 803a404:	10802b17 	ldw	r2,172(r2)
+ 803a408:	10002a1e 	bne	r2,zero,803a4b4 <ip_write_internal+0x1e0>
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (IPTRACE|PROTERR))
+ 803a40c:	d0a06617 	ldw	r2,-32360(gp)
+ 803a410:	1080840c 	andi	r2,r2,528
+ 803a414:	10001a26 	beq	r2,zero,803a480 <ip_write_internal+0x1ac>
+         {
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a418:	e0bff617 	ldw	r2,-40(fp)
+ 803a41c:	11400417 	ldw	r5,16(r2)
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a420:	e0bff617 	ldw	r2,-40(fp)
+ 803a424:	10800717 	ldw	r2,28(r2)
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a428:	11803fcc 	andi	r6,r2,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a42c:	e0bff617 	ldw	r2,-40(fp)
+ 803a430:	10800717 	ldw	r2,28(r2)
+ 803a434:	1004d23a 	srli	r2,r2,8
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a438:	10803fcc 	andi	r2,r2,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a43c:	e0fff617 	ldw	r3,-40(fp)
+ 803a440:	18c00717 	ldw	r3,28(r3)
+ 803a444:	1806d43a 	srli	r3,r3,16
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a448:	18c03fcc 	andi	r3,r3,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a44c:	e13ff617 	ldw	r4,-40(fp)
+ 803a450:	21000717 	ldw	r4,28(r4)
+ 803a454:	2008d63a 	srli	r4,r4,24
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a458:	d9000215 	stw	r4,8(sp)
+ 803a45c:	d8c00115 	stw	r3,4(sp)
+ 803a460:	d8800015 	stw	r2,0(sp)
+ 803a464:	300f883a 	mov	r7,r6
+ 803a468:	280d883a 	mov	r6,r5
+ 803a46c:	e17ff617 	ldw	r5,-40(fp)
+ 803a470:	01020174 	movhi	r4,2053
+ 803a474:	212c2804 	addi	r4,r4,-20320
+ 803a478:	8002c780 	call	8002c78 <printf>
+            dtrap();
+ 803a47c:	8028cd40 	call	8028cd4 <dtrap>
+         }
+#endif
+         ip_mib.ipOutNoRoutes++;
+ 803a480:	008201b4 	movhi	r2,2054
+ 803a484:	10b95a17 	ldw	r2,-6808(r2)
+ 803a488:	10c00044 	addi	r3,r2,1
+ 803a48c:	008201b4 	movhi	r2,2054
+ 803a490:	10f95a15 	stw	r3,-6808(r2)
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a494:	01000084 	movi	r4,2
+ 803a498:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803a49c:	e13ff617 	ldw	r4,-40(fp)
+ 803a4a0:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a4a4:	01000084 	movi	r4,2
+ 803a4a8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NO_ROUTE);
+ 803a4ac:	00bff7c4 	movi	r2,-33
+ 803a4b0:	00014806 	br	803a9d4 <ip_write_internal+0x700>
+       * If we belong to the destination multicast group
+       * on the outgoing interface, and the caller did not
+       * forbid loopback, put a copy of the packet on the
+       * received queue.
+       */
+      inm = lookup_mcast(p->fhost, p->net);
+ 803a4b4:	e0bff617 	ldw	r2,-40(fp)
+ 803a4b8:	10c00717 	ldw	r3,28(r2)
+ 803a4bc:	e0bff617 	ldw	r2,-40(fp)
+ 803a4c0:	10800617 	ldw	r2,24(r2)
+ 803a4c4:	100b883a 	mov	r5,r2
+ 803a4c8:	1809883a 	mov	r4,r3
+ 803a4cc:	803c5040 	call	803c504 <lookup_mcast>
+ 803a4d0:	e0bffd15 	stw	r2,-12(fp)
+      if ((inm != NULL) &&
+ 803a4d4:	e0bffd17 	ldw	r2,-12(fp)
+ 803a4d8:	10001b26 	beq	r2,zero,803a548 <ip_write_internal+0x274>
+          ((p->imo == NULL) || p->imo->imo_multicast_loop)) 
+ 803a4dc:	e0bff617 	ldw	r2,-40(fp)
+ 803a4e0:	10800b17 	ldw	r2,44(r2)
+      if ((inm != NULL) &&
+ 803a4e4:	10000526 	beq	r2,zero,803a4fc <ip_write_internal+0x228>
+          ((p->imo == NULL) || p->imo->imo_multicast_loop)) 
+ 803a4e8:	e0bff617 	ldw	r2,-40(fp)
+ 803a4ec:	10800b17 	ldw	r2,44(r2)
+ 803a4f0:	10800143 	ldbu	r2,5(r2)
+ 803a4f4:	10803fcc 	andi	r2,r2,255
+ 803a4f8:	10001326 	beq	r2,zero,803a548 <ip_write_internal+0x274>
+      {
+         p->type = IPTP;
+ 803a4fc:	e0bff617 	ldw	r2,-40(fp)
+ 803a500:	00c00204 	movi	r3,8
+ 803a504:	10c0080d 	sth	r3,32(r2)
+         pkt2 = ip_copypkt(p);
+ 803a508:	e13ff617 	ldw	r4,-40(fp)
+ 803a50c:	803b53c0 	call	803b53c <ip_copypkt>
+ 803a510:	e0bffc15 	stw	r2,-16(fp)
+         if (pkt2)
+ 803a514:	e0bffc17 	ldw	r2,-16(fp)
+ 803a518:	10000b26 	beq	r2,zero,803a548 <ip_write_internal+0x274>
+         {
+            LOCK_NET_RESOURCE(RXQ_RESID);
+ 803a51c:	01000044 	movi	r4,1
+ 803a520:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            putq(&rcvdq, (q_elt)pkt2);
+ 803a524:	e17ffc17 	ldw	r5,-16(fp)
+ 803a528:	010201b4 	movhi	r4,2054
+ 803a52c:	2136ab04 	addi	r4,r4,-9556
+ 803a530:	80289900 	call	8028990 <putq>
+            UNLOCK_NET_RESOURCE(RXQ_RESID);
+ 803a534:	01000044 	movi	r4,1
+ 803a538:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            SignalPktDemux();
+ 803a53c:	d0a08017 	ldw	r2,-32256(gp)
+ 803a540:	1009883a 	mov	r4,r2
+ 803a544:	8015d840 	call	8015d84 <OSSemPost>
+       * Also, multicasts addressed to the loopback interface
+       * are not sent -- a copy will already have been looped
+       * back above if this host actually belongs to the
+       * destination group on the loopback interface.
+       */
+      pip = (struct ip *)(p->nb_prot);
+ 803a548:	e0bff617 	ldw	r2,-40(fp)
+ 803a54c:	10800317 	ldw	r2,12(r2)
+ 803a550:	e0bffb15 	stw	r2,-20(fp)
+      if ((pip->ip_time == 0) || 
+ 803a554:	e0bffb17 	ldw	r2,-20(fp)
+ 803a558:	10800203 	ldbu	r2,8(r2)
+ 803a55c:	10803fcc 	andi	r2,r2,255
+ 803a560:	10000b26 	beq	r2,zero,803a590 <ip_write_internal+0x2bc>
+          ((p->fhost & htonl(0xFF000000)) == IPLBA) || 
+ 803a564:	e0bff617 	ldw	r2,-40(fp)
+ 803a568:	10800717 	ldw	r2,28(r2)
+ 803a56c:	10803fcc 	andi	r2,r2,255
+      if ((pip->ip_time == 0) || 
+ 803a570:	10801fe0 	cmpeqi	r2,r2,127
+ 803a574:	1000061e 	bne	r2,zero,803a590 <ip_write_internal+0x2bc>
+          (p->fhost == p->net->n_ipaddr))
+ 803a578:	e0bff617 	ldw	r2,-40(fp)
+ 803a57c:	10c00717 	ldw	r3,28(r2)
+ 803a580:	e0bff617 	ldw	r2,-40(fp)
+ 803a584:	10800617 	ldw	r2,24(r2)
+ 803a588:	10800a17 	ldw	r2,40(r2)
+          ((p->fhost & htonl(0xFF000000)) == IPLBA) || 
+ 803a58c:	1880081e 	bne	r3,r2,803a5b0 <ip_write_internal+0x2dc>
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a590:	01000084 	movi	r4,2
+ 803a594:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803a598:	e13ff617 	ldw	r4,-40(fp)
+ 803a59c:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a5a0:	01000084 	movi	r4,2
+ 803a5a4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return(SUCCESS);
+ 803a5a8:	0005883a 	mov	r2,zero
+ 803a5ac:	00010906 	br	803a9d4 <ip_write_internal+0x700>
+      }
+
+      firsthop = p->fhost;
+ 803a5b0:	e0bff617 	ldw	r2,-40(fp)
+ 803a5b4:	10800717 	ldw	r2,28(r2)
+ 803a5b8:	e0bff715 	stw	r2,-36(fp)
+
+      goto sendit;
+ 803a5bc:	00003f06 	br	803a6bc <ip_write_internal+0x3e8>
+   }
+
+#endif /* IP_MULTICAST */
+
+   /* if this is a broadcast packet, use the caller-selected network */
+   if (p->fhost == 0xFFFFFFFF)
+ 803a5c0:	e0bff617 	ldw	r2,-40(fp)
+ 803a5c4:	10800717 	ldw	r2,28(r2)
+ 803a5c8:	10bfffd8 	cmpnei	r2,r2,-1
+ 803a5cc:	1000041e 	bne	r2,zero,803a5e0 <ip_write_internal+0x30c>
+   {
+      firsthop = p->fhost;
+ 803a5d0:	e0bff617 	ldw	r2,-40(fp)
+ 803a5d4:	10800717 	ldw	r2,28(r2)
+ 803a5d8:	e0bff715 	stw	r2,-36(fp)
+ 803a5dc:	00003706 	br	803a6bc <ip_write_internal+0x3e8>
+   }
+   else
+   {
+      p->net = iproute(p->fhost, &firsthop);
+ 803a5e0:	e0bff617 	ldw	r2,-40(fp)
+ 803a5e4:	10800717 	ldw	r2,28(r2)
+ 803a5e8:	e0fff704 	addi	r3,fp,-36
+ 803a5ec:	180b883a 	mov	r5,r3
+ 803a5f0:	1009883a 	mov	r4,r2
+ 803a5f4:	803b3700 	call	803b370 <iproute>
+ 803a5f8:	1007883a 	mov	r3,r2
+ 803a5fc:	e0bff617 	ldw	r2,-40(fp)
+ 803a600:	10c00615 	stw	r3,24(r2)
+      if (p->net == NULL)
+ 803a604:	e0bff617 	ldw	r2,-40(fp)
+ 803a608:	10800617 	ldw	r2,24(r2)
+ 803a60c:	10002a1e 	bne	r2,zero,803a6b8 <ip_write_internal+0x3e4>
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (IPTRACE|PROTERR))
+ 803a610:	d0a06617 	ldw	r2,-32360(gp)
+ 803a614:	1080840c 	andi	r2,r2,528
+ 803a618:	10001a26 	beq	r2,zero,803a684 <ip_write_internal+0x3b0>
+         {
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a61c:	e0bff617 	ldw	r2,-40(fp)
+ 803a620:	11400417 	ldw	r5,16(r2)
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a624:	e0bff617 	ldw	r2,-40(fp)
+ 803a628:	10800717 	ldw	r2,28(r2)
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a62c:	11803fcc 	andi	r6,r2,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a630:	e0bff617 	ldw	r2,-40(fp)
+ 803a634:	10800717 	ldw	r2,28(r2)
+ 803a638:	1004d23a 	srli	r2,r2,8
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a63c:	10803fcc 	andi	r2,r2,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a640:	e0fff617 	ldw	r3,-40(fp)
+ 803a644:	18c00717 	ldw	r3,28(r3)
+ 803a648:	1806d43a 	srli	r3,r3,16
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a64c:	18c03fcc 	andi	r3,r3,255
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a650:	e13ff617 	ldw	r4,-40(fp)
+ 803a654:	21000717 	ldw	r4,28(r4)
+ 803a658:	2008d63a 	srli	r4,r4,24
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+ 803a65c:	d9000215 	stw	r4,8(sp)
+ 803a660:	d8c00115 	stw	r3,4(sp)
+ 803a664:	d8800015 	stw	r2,0(sp)
+ 803a668:	300f883a 	mov	r7,r6
+ 803a66c:	280d883a 	mov	r6,r5
+ 803a670:	e17ff617 	ldw	r5,-40(fp)
+ 803a674:	01020174 	movhi	r4,2053
+ 803a678:	212c2804 	addi	r4,r4,-20320
+ 803a67c:	8002c780 	call	8002c78 <printf>
+            dtrap();
+ 803a680:	8028cd40 	call	8028cd4 <dtrap>
+         }
+#endif   /* NPDEBUG */
+         ip_mib.ipOutNoRoutes++;
+ 803a684:	008201b4 	movhi	r2,2054
+ 803a688:	10b95a17 	ldw	r2,-6808(r2)
+ 803a68c:	10c00044 	addi	r3,r2,1
+ 803a690:	008201b4 	movhi	r2,2054
+ 803a694:	10f95a15 	stw	r3,-6808(r2)
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a698:	01000084 	movi	r4,2
+ 803a69c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803a6a0:	e13ff617 	ldw	r4,-40(fp)
+ 803a6a4:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a6a8:	01000084 	movi	r4,2
+ 803a6ac:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NO_ROUTE);
+ 803a6b0:	00bff7c4 	movi	r2,-33
+ 803a6b4:	0000c706 	br	803a9d4 <ip_write_internal+0x700>
+      }
+   }
+
+#ifdef   IP_MULTICAST
+sendit:  /* label used for multicast packets to skip routing logic */
+ 803a6b8:	0001883a 	nop
+#endif   /* IP_MULTICAST */
+
+#ifdef   NPDEBUG
+   if (NDEBUG & IPTRACE)
+ 803a6bc:	d0a06617 	ldw	r2,-32360(gp)
+ 803a6c0:	1080800c 	andi	r2,r2,512
+ 803a6c4:	10002926 	beq	r2,zero,803a76c <ip_write_internal+0x498>
+   {
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+ 803a6c8:	e0bff617 	ldw	r2,-40(fp)
+ 803a6cc:	11000417 	ldw	r4,16(r2)
+       p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a6d0:	e0bff617 	ldw	r2,-40(fp)
+ 803a6d4:	10800717 	ldw	r2,28(r2)
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+ 803a6d8:	11403fcc 	andi	r5,r2,255
+       p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a6dc:	e0bff617 	ldw	r2,-40(fp)
+ 803a6e0:	10800717 	ldw	r2,28(r2)
+ 803a6e4:	1004d23a 	srli	r2,r2,8
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+ 803a6e8:	11803fcc 	andi	r6,r2,255
+       p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a6ec:	e0bff617 	ldw	r2,-40(fp)
+ 803a6f0:	10800717 	ldw	r2,28(r2)
+ 803a6f4:	1004d43a 	srli	r2,r2,16
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+ 803a6f8:	10803fcc 	andi	r2,r2,255
+       p->nb_plen, PUSH_IPADDR(p->fhost));
+ 803a6fc:	e0fff617 	ldw	r3,-40(fp)
+ 803a700:	18c00717 	ldw	r3,28(r3)
+ 803a704:	1806d63a 	srli	r3,r3,24
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+ 803a708:	d8c00115 	stw	r3,4(sp)
+ 803a70c:	d8800015 	stw	r2,0(sp)
+ 803a710:	300f883a 	mov	r7,r6
+ 803a714:	280d883a 	mov	r6,r5
+ 803a718:	200b883a 	mov	r5,r4
+ 803a71c:	01020174 	movhi	r4,2053
+ 803a720:	212c3804 	addi	r4,r4,-20256
+ 803a724:	8002c780 	call	8002c78 <printf>
+      dprintf(" route %u.%u.%u.%u\n", PUSH_IPADDR(firsthop));
+ 803a728:	e0bff717 	ldw	r2,-36(fp)
+ 803a72c:	10c03fcc 	andi	r3,r2,255
+ 803a730:	e0bff717 	ldw	r2,-36(fp)
+ 803a734:	1004d23a 	srli	r2,r2,8
+ 803a738:	11003fcc 	andi	r4,r2,255
+ 803a73c:	e0bff717 	ldw	r2,-36(fp)
+ 803a740:	1004d43a 	srli	r2,r2,16
+ 803a744:	11403fcc 	andi	r5,r2,255
+ 803a748:	e0bff717 	ldw	r2,-36(fp)
+ 803a74c:	1004d63a 	srli	r2,r2,24
+ 803a750:	d8800015 	stw	r2,0(sp)
+ 803a754:	280f883a 	mov	r7,r5
+ 803a758:	200d883a 	mov	r6,r4
+ 803a75c:	180b883a 	mov	r5,r3
+ 803a760:	01020174 	movhi	r4,2053
+ 803a764:	212c4104 	addi	r4,r4,-20220
+ 803a768:	8002c780 	call	8002c78 <printf>
+#endif   /* IPSEC */
+
+   /* If the packet is being sent to the same interface it will be sent
+    * from, short-cut things and just put it on the received queue.
+    */
+   if ((p->net->n_ipaddr == p->fhost) &&
+ 803a76c:	e0bff617 	ldw	r2,-40(fp)
+ 803a770:	10800617 	ldw	r2,24(r2)
+ 803a774:	10c00a17 	ldw	r3,40(r2)
+ 803a778:	e0bff617 	ldw	r2,-40(fp)
+ 803a77c:	10800717 	ldw	r2,28(r2)
+ 803a780:	1880271e 	bne	r3,r2,803a820 <ip_write_internal+0x54c>
+       ((p->fhost & htonl(0xff000000)) != htonl(0x7f000000)))
+ 803a784:	e0bff617 	ldw	r2,-40(fp)
+ 803a788:	10800717 	ldw	r2,28(r2)
+ 803a78c:	10803fcc 	andi	r2,r2,255
+   if ((p->net->n_ipaddr == p->fhost) &&
+ 803a790:	10801fe0 	cmpeqi	r2,r2,127
+ 803a794:	1000221e 	bne	r2,zero,803a820 <ip_write_internal+0x54c>
+   {
+      if (!(p->net->n_flags & NF_NBPROT))
+ 803a798:	e0bff617 	ldw	r2,-40(fp)
+ 803a79c:	10800617 	ldw	r2,24(r2)
+ 803a7a0:	10802a17 	ldw	r2,168(r2)
+ 803a7a4:	1080020c 	andi	r2,r2,8
+ 803a7a8:	1000091e 	bne	r2,zero,803a7d0 <ip_write_internal+0x4fc>
+          * IP or ARP protocol header) and nb_type to the protocol
+          * type, and set the NF_NBPROT flag in its interfaces'
+          * n_flags fields.
+          */
+#ifdef NPDEBUG
+         dtrap();
+ 803a7ac:	8028cd40 	call	8028cd4 <dtrap>
+#endif
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a7b0:	01000084 	movi	r4,2
+ 803a7b4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803a7b8:	e13ff617 	ldw	r4,-40(fp)
+ 803a7bc:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a7c0:	01000084 	movi	r4,2
+ 803a7c4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return ENP_LOGIC;
+ 803a7c8:	00bffd44 	movi	r2,-11
+ 803a7cc:	00008106 	br	803a9d4 <ip_write_internal+0x700>
+      }
+      p->type = IPTP;
+ 803a7d0:	e0bff617 	ldw	r2,-40(fp)
+ 803a7d4:	00c00204 	movi	r3,8
+ 803a7d8:	10c0080d 	sth	r3,32(r2)
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 803a7dc:	0009883a 	mov	r4,zero
+ 803a7e0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      LOCK_NET_RESOURCE(RXQ_RESID);
+ 803a7e4:	01000044 	movi	r4,1
+ 803a7e8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      putq(&rcvdq, (q_elt)p);
+ 803a7ec:	e17ff617 	ldw	r5,-40(fp)
+ 803a7f0:	010201b4 	movhi	r4,2054
+ 803a7f4:	2136ab04 	addi	r4,r4,-9556
+ 803a7f8:	80289900 	call	8028990 <putq>
+      UNLOCK_NET_RESOURCE(RXQ_RESID);
+ 803a7fc:	01000044 	movi	r4,1
+ 803a800:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      LOCK_NET_RESOURCE(NET_RESID);
+ 803a804:	0009883a 	mov	r4,zero
+ 803a808:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+
+      SignalPktDemux();
+ 803a80c:	d0a08017 	ldw	r2,-32256(gp)
+ 803a810:	1009883a 	mov	r4,r2
+ 803a814:	8015d840 	call	8015d84 <OSSemPost>
+
+      return SUCCESS;
+ 803a818:	0005883a 	mov	r2,zero
+ 803a81c:	00006d06 	br	803a9d4 <ip_write_internal+0x700>
+   }
+
+   /* determine if the buffer that needs to be transmitted is interrupt-safe */
+   intrsafe_buf = ((p->flags & PKF_INTRUNSAFE) ? 0 : 1);
+ 803a820:	e0bff617 	ldw	r2,-40(fp)
+ 803a824:	10800a17 	ldw	r2,40(r2)
+ 803a828:	1080040c 	andi	r2,r2,16
+ 803a82c:	1005003a 	cmpeq	r2,r2,zero
+ 803a830:	e0bffac5 	stb	r2,-21(fp)
+   /* obtain the length of the largest interrupt-safe buffer that can be 
+    * allocated via pk_alloc () */
+   maxbuflen = pk_get_max_intrsafe_buf_len ();
+ 803a834:	80287f40 	call	80287f4 <pk_get_max_intrsafe_buf_len>
+ 803a838:	e0bff915 	stw	r2,-28(fp)
+    * the original buffer is interrupt-safe, we just need to consider the
+    * MTU of the egress interface.  If the original buffer is interrupt-
+    * unsafe, we compute the MIN of the largest interrupt-safe buffer that
+    * we can use and the MTU of the egress interface (since we must satisfy
+    * both constraints) */
+   if (!intrsafe_buf)
+ 803a83c:	e0bffac3 	ldbu	r2,-21(fp)
+ 803a840:	1000091e 	bne	r2,zero,803a868 <ip_write_internal+0x594>
+       limit = MIN(maxbuflen,p->net->n_mtu);
+ 803a844:	e0bff617 	ldw	r2,-40(fp)
+ 803a848:	10800617 	ldw	r2,24(r2)
+ 803a84c:	10800917 	ldw	r2,36(r2)
+ 803a850:	1007883a 	mov	r3,r2
+ 803a854:	e0bff917 	ldw	r2,-28(fp)
+ 803a858:	1880012e 	bgeu	r3,r2,803a860 <ip_write_internal+0x58c>
+ 803a85c:	1805883a 	mov	r2,r3
+ 803a860:	e0bffe15 	stw	r2,-8(fp)
+ 803a864:	00000406 	br	803a878 <ip_write_internal+0x5a4>
+   else
+       limit = p->net->n_mtu;
+ 803a868:	e0bff617 	ldw	r2,-40(fp)
+ 803a86c:	10800617 	ldw	r2,24(r2)
+ 803a870:	10800917 	ldw	r2,36(r2)
+ 803a874:	e0bffe15 	stw	r2,-8(fp)
+
+   if ((p->nb_plen + p->net->n_lnh) > limit)
+ 803a878:	e0bff617 	ldw	r2,-40(fp)
+ 803a87c:	10800417 	ldw	r2,16(r2)
+ 803a880:	e0fff617 	ldw	r3,-40(fp)
+ 803a884:	18c00617 	ldw	r3,24(r3)
+ 803a888:	18c00817 	ldw	r3,32(r3)
+ 803a88c:	10c5883a 	add	r2,r2,r3
+ 803a890:	e0fffe17 	ldw	r3,-8(fp)
+ 803a894:	1880092e 	bgeu	r3,r2,803a8bc <ip_write_internal+0x5e8>
+      int err;
+      err = ip_fragment(p, firsthop);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(err);
+#else
+      dtrap();    /* this should be caught by programmers during development */
+ 803a898:	8028cd40 	call	8028cd4 <dtrap>
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a89c:	01000084 	movi	r4,2
+ 803a8a0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 803a8a4:	e13ff617 	ldw	r4,-40(fp)
+ 803a8a8:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a8ac:	01000084 	movi	r4,2
+ 803a8b0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_LOGIC;
+ 803a8b4:	00bffd44 	movi	r2,-11
+ 803a8b8:	00004606 	br	803a9d4 <ip_write_internal+0x700>
+   }
+   else
+   {
+      /* fragmentation is not required; check to see if we need to copy out of
+       * an interrupt-unsafe buffer */ 
+      if (!intrsafe_buf)
+ 803a8bc:	e0bffac3 	ldbu	r2,-21(fp)
+ 803a8c0:	1000401e 	bne	r2,zero,803a9c4 <ip_write_internal+0x6f0>
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a8c4:	01000084 	movi	r4,2
+ 803a8c8:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         newpkt = pk_alloc(p->nb_plen + p->net->n_lnh);
+ 803a8cc:	e0bff617 	ldw	r2,-40(fp)
+ 803a8d0:	10800417 	ldw	r2,16(r2)
+ 803a8d4:	e0fff617 	ldw	r3,-40(fp)
+ 803a8d8:	18c00617 	ldw	r3,24(r3)
+ 803a8dc:	18c00817 	ldw	r3,32(r3)
+ 803a8e0:	10c5883a 	add	r2,r2,r3
+ 803a8e4:	1009883a 	mov	r4,r2
+ 803a8e8:	80284340 	call	8028434 <pk_alloc>
+ 803a8ec:	e0bff815 	stw	r2,-32(fp)
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a8f0:	01000084 	movi	r4,2
+ 803a8f4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         if (newpkt == 0)
+ 803a8f8:	e0bff817 	ldw	r2,-32(fp)
+ 803a8fc:	1000081e 	bne	r2,zero,803a920 <ip_write_internal+0x64c>
+         {
+            /* can't allocate interrupt-safe buffer, so free the packet that 
+             * we are working with */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a900:	01000084 	movi	r4,2
+ 803a904:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(p);
+ 803a908:	e13ff617 	ldw	r4,-40(fp)
+ 803a90c:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a910:	01000084 	movi	r4,2
+ 803a914:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NOBUFFER;
+ 803a918:	00bffac4 	movi	r2,-21
+ 803a91c:	00002d06 	br	803a9d4 <ip_write_internal+0x700>
+         }
+         else
+         {
+            /* copy from interrupt-unsafe buffer into interrupt-safe buffer */
+            newpkt->nb_prot = newpkt->nb_buff + p->net->n_lnh;
+ 803a920:	e0bff817 	ldw	r2,-32(fp)
+ 803a924:	10800117 	ldw	r2,4(r2)
+ 803a928:	e0fff617 	ldw	r3,-40(fp)
+ 803a92c:	18c00617 	ldw	r3,24(r3)
+ 803a930:	18c00817 	ldw	r3,32(r3)
+ 803a934:	10c7883a 	add	r3,r2,r3
+ 803a938:	e0bff817 	ldw	r2,-32(fp)
+ 803a93c:	10c00315 	stw	r3,12(r2)
+            MEMCPY(newpkt->nb_prot, p->nb_prot, p->nb_plen);
+ 803a940:	e0bff817 	ldw	r2,-32(fp)
+ 803a944:	10c00317 	ldw	r3,12(r2)
+ 803a948:	e0bff617 	ldw	r2,-40(fp)
+ 803a94c:	11000317 	ldw	r4,12(r2)
+ 803a950:	e0bff617 	ldw	r2,-40(fp)
+ 803a954:	10800417 	ldw	r2,16(r2)
+ 803a958:	100d883a 	mov	r6,r2
+ 803a95c:	200b883a 	mov	r5,r4
+ 803a960:	1809883a 	mov	r4,r3
+ 803a964:	80086b80 	call	80086b8 <memcpy>
+            /* setup various fields in the newly allocated PACKET structure */
+            newpkt->nb_plen = p->nb_plen;
+ 803a968:	e0bff617 	ldw	r2,-40(fp)
+ 803a96c:	10c00417 	ldw	r3,16(r2)
+ 803a970:	e0bff817 	ldw	r2,-32(fp)
+ 803a974:	10c00415 	stw	r3,16(r2)
+            newpkt->net = p->net;
+ 803a978:	e0bff617 	ldw	r2,-40(fp)
+ 803a97c:	10c00617 	ldw	r3,24(r2)
+ 803a980:	e0bff817 	ldw	r2,-32(fp)
+ 803a984:	10c00615 	stw	r3,24(r2)
+            newpkt->fhost = p->fhost;
+ 803a988:	e0bff617 	ldw	r2,-40(fp)
+ 803a98c:	10c00717 	ldw	r3,28(r2)
+ 803a990:	e0bff817 	ldw	r2,-32(fp)
+ 803a994:	10c00715 	stw	r3,28(r2)
+            /* free the original packet since it is no longer needed */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a998:	01000084 	movi	r4,2
+ 803a99c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(p);
+ 803a9a0:	e13ff617 	ldw	r4,-40(fp)
+ 803a9a4:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803a9a8:	01000084 	movi	r4,2
+ 803a9ac:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            IN_PROFILER(PF_IP, PF_EXIT);
+            /* send packet to MAC layer. This will try to resolve MAC layer addressing 
+             * and send packet. ip2mac() can return SUCCESS, PENDING, or error codes. 
+             */
+            return(ip2mac(newpkt, firsthop));
+ 803a9b0:	e0bff717 	ldw	r2,-36(fp)
+ 803a9b4:	100b883a 	mov	r5,r2
+ 803a9b8:	e13ff817 	ldw	r4,-32(fp)
+ 803a9bc:	8024df40 	call	8024df4 <ip2mac>
+ 803a9c0:	00000406 	br	803a9d4 <ip_write_internal+0x700>
+      else
+      {
+         /* since the packet is in an interrupt-safe buffer, it can be passed to 
+          * ip2mac () without any additional work. */
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return(ip2mac(p, firsthop));
+ 803a9c4:	e0bff717 	ldw	r2,-36(fp)
+ 803a9c8:	100b883a 	mov	r5,r2
+ 803a9cc:	e13ff617 	ldw	r4,-40(fp)
+ 803a9d0:	8024df40 	call	8024df4 <ip2mac>
+      }
+   }
+}
+ 803a9d4:	e037883a 	mov	sp,fp
+ 803a9d8:	dfc00117 	ldw	ra,4(sp)
+ 803a9dc:	df000017 	ldw	fp,0(sp)
+ 803a9e0:	dec00204 	addi	sp,sp,8
+ 803a9e4:	f800283a 	ret
+
+0803a9e8 <ip_write>:
+
+int
+ip_write(
+   u_char   prot,
+   PACKET   p)
+{
+ 803a9e8:	defff904 	addi	sp,sp,-28
+ 803a9ec:	dfc00615 	stw	ra,24(sp)
+ 803a9f0:	df000515 	stw	fp,20(sp)
+ 803a9f4:	df000504 	addi	fp,sp,20
+ 803a9f8:	2005883a 	mov	r2,r4
+ 803a9fc:	e17ffb15 	stw	r5,-20(fp)
+ 803aa00:	e0bffc05 	stb	r2,-16(fp)
+   u_char ttl;
+   struct ip_socopts *sopts;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+ 803aa04:	008201b4 	movhi	r2,2054
+ 803aa08:	10b95817 	ldw	r2,-6816(r2)
+ 803aa0c:	10c00044 	addi	r3,r2,1
+ 803aa10:	008201b4 	movhi	r2,2054
+ 803aa14:	10f95815 	stw	r3,-6816(r2)
+
+   /* make room for IP header, and form a pointer to it (pip) */
+   p->nb_prot -= sizeof(struct ip);
+ 803aa18:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa1c:	10800317 	ldw	r2,12(r2)
+ 803aa20:	10fffb04 	addi	r3,r2,-20
+ 803aa24:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa28:	10c00315 	stw	r3,12(r2)
+   p->nb_plen += sizeof(struct ip);
+ 803aa2c:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa30:	10800417 	ldw	r2,16(r2)
+ 803aa34:	10c00504 	addi	r3,r2,20
+ 803aa38:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa3c:	10c00415 	stw	r3,16(r2)
+   pip = (struct ip*)(p->nb_prot);
+ 803aa40:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa44:	10800317 	ldw	r2,12(r2)
+ 803aa48:	e0bffe15 	stw	r2,-8(fp)
+
+   /* build the initial IP header:
+    * IP source address (ip_src) and IP destination address (ip_dest)
+    * should already have been filled in by upper-layer protocol
+    */
+   pip->ip_ver_ihl = 0x45;       /* 2 nibbles; VER:4, IHL:5. */
+ 803aa4c:	e0bffe17 	ldw	r2,-8(fp)
+ 803aa50:	00c01144 	movi	r3,69
+ 803aa54:	10c00005 	stb	r3,0(r2)
+   pip->ip_flgs_foff = 0;        /* clear fragmentation info field */
+ 803aa58:	e0bffe17 	ldw	r2,-8(fp)
+ 803aa5c:	1000018d 	sth	zero,6(r2)
+   pip->ip_id = htons((unshort)uid);
+ 803aa60:	d0a02f17 	ldw	r2,-32580(gp)
+ 803aa64:	10bfffcc 	andi	r2,r2,65535
+ 803aa68:	1004d23a 	srli	r2,r2,8
+ 803aa6c:	1007883a 	mov	r3,r2
+ 803aa70:	d0a02f17 	ldw	r2,-32580(gp)
+ 803aa74:	10bfffcc 	andi	r2,r2,65535
+ 803aa78:	1004923a 	slli	r2,r2,8
+ 803aa7c:	1884b03a 	or	r2,r3,r2
+ 803aa80:	1007883a 	mov	r3,r2
+ 803aa84:	e0bffe17 	ldw	r2,-8(fp)
+ 803aa88:	10c0010d 	sth	r3,4(r2)
+   uid++;
+ 803aa8c:	d0a02f17 	ldw	r2,-32580(gp)
+ 803aa90:	10800044 	addi	r2,r2,1
+ 803aa94:	d0a02f15 	stw	r2,-32580(gp)
+   pip->ip_len = htons((unshort)(p->nb_plen));
+ 803aa98:	e0bffb17 	ldw	r2,-20(fp)
+ 803aa9c:	10800417 	ldw	r2,16(r2)
+ 803aaa0:	10bfffcc 	andi	r2,r2,65535
+ 803aaa4:	1004d23a 	srli	r2,r2,8
+ 803aaa8:	1007883a 	mov	r3,r2
+ 803aaac:	e0bffb17 	ldw	r2,-20(fp)
+ 803aab0:	10800417 	ldw	r2,16(r2)
+ 803aab4:	10bfffcc 	andi	r2,r2,65535
+ 803aab8:	1004923a 	slli	r2,r2,8
+ 803aabc:	1884b03a 	or	r2,r3,r2
+ 803aac0:	1007883a 	mov	r3,r2
+ 803aac4:	e0bffe17 	ldw	r2,-8(fp)
+ 803aac8:	10c0008d 	sth	r3,2(r2)
+   pip->ip_prot = prot;
+ 803aacc:	e0bffe17 	ldw	r2,-8(fp)
+ 803aad0:	e0fffc03 	ldbu	r3,-16(fp)
+ 803aad4:	10c00245 	stb	r3,9(r2)
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+ 803aad8:	e0bffe17 	ldw	r2,-8(fp)
+ 803aadc:	1000028d 	sth	zero,10(r2)
+   ttl = IP_TTL;
+ 803aae0:	00801004 	movi	r2,64
+ 803aae4:	e0bfffc5 	stb	r2,-1(fp)
+#ifdef IP_MULTICAST
+   if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL))
+ 803aae8:	e0bffb17 	ldw	r2,-20(fp)
+ 803aaec:	10800717 	ldw	r2,28(r2)
+ 803aaf0:	1006d63a 	srli	r3,r2,24
+ 803aaf4:	e0bffb17 	ldw	r2,-20(fp)
+ 803aaf8:	10800717 	ldw	r2,28(r2)
+ 803aafc:	1004d23a 	srli	r2,r2,8
+ 803ab00:	10bfc00c 	andi	r2,r2,65280
+ 803ab04:	1886b03a 	or	r3,r3,r2
+ 803ab08:	e0bffb17 	ldw	r2,-20(fp)
+ 803ab0c:	10800717 	ldw	r2,28(r2)
+ 803ab10:	1004923a 	slli	r2,r2,8
+ 803ab14:	10803fec 	andhi	r2,r2,255
+ 803ab18:	1886b03a 	or	r3,r3,r2
+ 803ab1c:	e0bffb17 	ldw	r2,-20(fp)
+ 803ab20:	10800717 	ldw	r2,28(r2)
+ 803ab24:	1004963a 	slli	r2,r2,24
+ 803ab28:	1884b03a 	or	r2,r3,r2
+ 803ab2c:	10fc002c 	andhi	r3,r2,61440
+ 803ab30:	00b80034 	movhi	r2,57344
+ 803ab34:	1880071e 	bne	r3,r2,803ab54 <ip_write+0x16c>
+ 803ab38:	e0bffb17 	ldw	r2,-20(fp)
+ 803ab3c:	10800b17 	ldw	r2,44(r2)
+ 803ab40:	10000426 	beq	r2,zero,803ab54 <ip_write+0x16c>
+      ttl = p->imo->imo_multicast_ttl;
+ 803ab44:	e0bffb17 	ldw	r2,-20(fp)
+ 803ab48:	10800b17 	ldw	r2,44(r2)
+ 803ab4c:	10800103 	ldbu	r2,4(r2)
+ 803ab50:	e0bfffc5 	stb	r2,-1(fp)
+#endif /* IP_MULTICAST */
+
+   /* have IP_TOS or IP_TTL been set? */
+   if ((sopts = p->soxopts))
+ 803ab54:	e0bffb17 	ldw	r2,-20(fp)
+ 803ab58:	10800c17 	ldw	r2,48(r2)
+ 803ab5c:	e0bffd15 	stw	r2,-12(fp)
+ 803ab60:	e0bffd17 	ldw	r2,-12(fp)
+ 803ab64:	10001126 	beq	r2,zero,803abac <ip_write+0x1c4>
+   {
+	  /* yup */
+	  if (sopts->ip_ttl)
+ 803ab68:	e0bffd17 	ldw	r2,-12(fp)
+ 803ab6c:	10800043 	ldbu	r2,1(r2)
+ 803ab70:	10803fcc 	andi	r2,r2,255
+ 803ab74:	10000526 	beq	r2,zero,803ab8c <ip_write+0x1a4>
+         pip->ip_time = sopts->ip_ttl;
+ 803ab78:	e0bffd17 	ldw	r2,-12(fp)
+ 803ab7c:	10c00043 	ldbu	r3,1(r2)
+ 803ab80:	e0bffe17 	ldw	r2,-8(fp)
+ 803ab84:	10c00205 	stb	r3,8(r2)
+ 803ab88:	00000306 	br	803ab98 <ip_write+0x1b0>
+	  else
+         pip->ip_time = ttl;
+ 803ab8c:	e0bffe17 	ldw	r2,-8(fp)
+ 803ab90:	e0ffffc3 	ldbu	r3,-1(fp)
+ 803ab94:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = sopts->ip_tos;
+ 803ab98:	e0bffd17 	ldw	r2,-12(fp)
+ 803ab9c:	10c00003 	ldbu	r3,0(r2)
+ 803aba0:	e0bffe17 	ldw	r2,-8(fp)
+ 803aba4:	10c00045 	stb	r3,1(r2)
+ 803aba8:	00000506 	br	803abc0 <ip_write+0x1d8>
+   }
+   else
+   {
+	  /* nope */
+      pip->ip_time = ttl;
+ 803abac:	e0bffe17 	ldw	r2,-8(fp)
+ 803abb0:	e0ffffc3 	ldbu	r3,-1(fp)
+ 803abb4:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = IP_TOS_DEFVAL;
+ 803abb8:	e0bffe17 	ldw	r2,-8(fp)
+ 803abbc:	10000045 	stb	zero,1(r2)
+   }
+   
+   /* checksum the IP header */
+   pip->ip_chksum = ~cksum(pip, 10);
+ 803abc0:	01400284 	movi	r5,10
+ 803abc4:	e13ffe17 	ldw	r4,-8(fp)
+ 803abc8:	8026d7c0 	call	8026d7c <cksum>
+ 803abcc:	0084303a 	nor	r2,zero,r2
+ 803abd0:	1007883a 	mov	r3,r2
+ 803abd4:	e0bffe17 	ldw	r2,-8(fp)
+ 803abd8:	10c0028d 	sth	r3,10(r2)
+
+   /* do the actual write */
+   return (ip_write_internal(p));
+ 803abdc:	e13ffb17 	ldw	r4,-20(fp)
+ 803abe0:	803a2d40 	call	803a2d4 <ip_write_internal>
+}
+ 803abe4:	e037883a 	mov	sp,fp
+ 803abe8:	dfc00117 	ldw	ra,4(sp)
+ 803abec:	df000017 	ldw	fp,0(sp)
+ 803abf0:	dec00204 	addi	sp,sp,8
+ 803abf4:	f800283a 	ret
+
+0803abf8 <ip_write2>:
+ * OUTPUT: This function returns the return code from 
+ *         ip_write_internal ().
+ */
+
+int ip_write2 (u_char prot, PACKET p, u_char * optp)
+{
+ 803abf8:	defff604 	addi	sp,sp,-40
+ 803abfc:	dfc00915 	stw	ra,36(sp)
+ 803ac00:	df000815 	stw	fp,32(sp)
+ 803ac04:	df000804 	addi	fp,sp,32
+ 803ac08:	2005883a 	mov	r2,r4
+ 803ac0c:	e17ff915 	stw	r5,-28(fp)
+ 803ac10:	e1bff815 	stw	r6,-32(fp)
+ 803ac14:	e0bffa05 	stb	r2,-24(fp)
+   struct ip * pip;
+   u_char ttl;
+   struct ip_socopts * sopts;
+   u_char iphlen = sizeof (struct ip);
+ 803ac18:	00800504 	movi	r2,20
+ 803ac1c:	e0bfff85 	stb	r2,-2(fp)
+   u_char iphlen_pad;
+   u_char i;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+ 803ac20:	008201b4 	movhi	r2,2054
+ 803ac24:	10b95817 	ldw	r2,-6816(r2)
+ 803ac28:	10c00044 	addi	r3,r2,1
+ 803ac2c:	008201b4 	movhi	r2,2054
+ 803ac30:	10f95815 	stw	r3,-6816(r2)
+
+   /* compute the total length of the options requested */
+   for (tmpp = optp; (*tmpp) != EOL_OPT; ++tmpp)
+ 803ac34:	e0bff817 	ldw	r2,-32(fp)
+ 803ac38:	e0bffe15 	stw	r2,-8(fp)
+ 803ac3c:	00000d06 	br	803ac74 <ip_write2+0x7c>
+   {
+      /* account for options, if any (caller has already created
+       * adequate space for the requested option) */
+      switch (*tmpp)
+ 803ac40:	e0bffe17 	ldw	r2,-8(fp)
+ 803ac44:	10800003 	ldbu	r2,0(r2)
+ 803ac48:	10803fcc 	andi	r2,r2,255
+ 803ac4c:	10800518 	cmpnei	r2,r2,20
+ 803ac50:	1000041e 	bne	r2,zero,803ac64 <ip_write2+0x6c>
+      {
+         case IP_RTR_ALERT_OPT:
+            iphlen += IP_RTR_ALERT_OPT_SIZE;
+ 803ac54:	e0bfff83 	ldbu	r2,-2(fp)
+ 803ac58:	10800104 	addi	r2,r2,4
+ 803ac5c:	e0bfff85 	stb	r2,-2(fp)
+            break;
+ 803ac60:	00000106 	br	803ac68 <ip_write2+0x70>
+         default:
+            break;
+ 803ac64:	0001883a 	nop
+   for (tmpp = optp; (*tmpp) != EOL_OPT; ++tmpp)
+ 803ac68:	e0bffe17 	ldw	r2,-8(fp)
+ 803ac6c:	10800044 	addi	r2,r2,1
+ 803ac70:	e0bffe15 	stw	r2,-8(fp)
+ 803ac74:	e0bffe17 	ldw	r2,-8(fp)
+ 803ac78:	10800003 	ldbu	r2,0(r2)
+ 803ac7c:	10803fcc 	andi	r2,r2,255
+ 803ac80:	103fef1e 	bne	r2,zero,803ac40 <ip_write2+0x48>
+   }
+
+   /* compute the amount of padding required, if any (to ensure
+    * that the IP header (including options) ends on a dword
+    * (four byte) boundary */
+   if (iphlen & 0x3)
+ 803ac84:	e0bfff83 	ldbu	r2,-2(fp)
+ 803ac88:	108000cc 	andi	r2,r2,3
+ 803ac8c:	10000726 	beq	r2,zero,803acac <ip_write2+0xb4>
+      iphlen_pad = 4 - (iphlen & 0x3);
+ 803ac90:	e0bfff83 	ldbu	r2,-2(fp)
+ 803ac94:	108000cc 	andi	r2,r2,3
+ 803ac98:	1007883a 	mov	r3,r2
+ 803ac9c:	00800104 	movi	r2,4
+ 803aca0:	10c5c83a 	sub	r2,r2,r3
+ 803aca4:	e0bffdc5 	stb	r2,-9(fp)
+ 803aca8:	00000106 	br	803acb0 <ip_write2+0xb8>
+   else iphlen_pad = 0; /* no header padding required */
+ 803acac:	e03ffdc5 	stb	zero,-9(fp)
+   /* the packet passed to ip_write2 () has its nb_prot set to
+    * point to start of the protocol's (e.g., IGMP) data, and 
+    * nb_plen set to the length of that data.  locate start of 
+    * the IP header (account for IP options), and form a pointer 
+    * to it (pip) */
+   p->nb_prot -= (iphlen + iphlen_pad);
+ 803acb0:	e0bff917 	ldw	r2,-28(fp)
+ 803acb4:	10c00317 	ldw	r3,12(r2)
+ 803acb8:	e13fff83 	ldbu	r4,-2(fp)
+ 803acbc:	e0bffdc3 	ldbu	r2,-9(fp)
+ 803acc0:	2085883a 	add	r2,r4,r2
+ 803acc4:	0085c83a 	sub	r2,zero,r2
+ 803acc8:	1887883a 	add	r3,r3,r2
+ 803accc:	e0bff917 	ldw	r2,-28(fp)
+ 803acd0:	10c00315 	stw	r3,12(r2)
+   /* add padding length to the total length of the IP datagram */
+   p->nb_plen += (iphlen + iphlen_pad);
+ 803acd4:	e0bff917 	ldw	r2,-28(fp)
+ 803acd8:	10800417 	ldw	r2,16(r2)
+ 803acdc:	e13fff83 	ldbu	r4,-2(fp)
+ 803ace0:	e0fffdc3 	ldbu	r3,-9(fp)
+ 803ace4:	20c7883a 	add	r3,r4,r3
+ 803ace8:	10c7883a 	add	r3,r2,r3
+ 803acec:	e0bff917 	ldw	r2,-28(fp)
+ 803acf0:	10c00415 	stw	r3,16(r2)
+   pip = (struct ip *) (p->nb_prot);
+ 803acf4:	e0bff917 	ldw	r2,-28(fp)
+ 803acf8:	10800317 	ldw	r2,12(r2)
+ 803acfc:	e0bffc15 	stw	r2,-16(fp)
+
+   /* build the initial IP header:
+    * IP source address (ip_src) and IP destination address (ip_dest)
+    * should already have been filled in by upper-layer protocol
+    */
+   pip->ip_ver_ihl = ((IP_VER << 4) | ((iphlen + iphlen_pad) >> 2));
+ 803ad00:	e0ffff83 	ldbu	r3,-2(fp)
+ 803ad04:	e0bffdc3 	ldbu	r2,-9(fp)
+ 803ad08:	1885883a 	add	r2,r3,r2
+ 803ad0c:	1005d0ba 	srai	r2,r2,2
+ 803ad10:	10801014 	ori	r2,r2,64
+ 803ad14:	1007883a 	mov	r3,r2
+ 803ad18:	e0bffc17 	ldw	r2,-16(fp)
+ 803ad1c:	10c00005 	stb	r3,0(r2)
+   pip->ip_flgs_foff = 0; /* clear fragmentation info field */
+ 803ad20:	e0bffc17 	ldw	r2,-16(fp)
+ 803ad24:	1000018d 	sth	zero,6(r2)
+   pip->ip_id = htons((unshort)uid);
+ 803ad28:	d0a02f17 	ldw	r2,-32580(gp)
+ 803ad2c:	10bfffcc 	andi	r2,r2,65535
+ 803ad30:	1004d23a 	srli	r2,r2,8
+ 803ad34:	1007883a 	mov	r3,r2
+ 803ad38:	d0a02f17 	ldw	r2,-32580(gp)
+ 803ad3c:	10bfffcc 	andi	r2,r2,65535
+ 803ad40:	1004923a 	slli	r2,r2,8
+ 803ad44:	1884b03a 	or	r2,r3,r2
+ 803ad48:	1007883a 	mov	r3,r2
+ 803ad4c:	e0bffc17 	ldw	r2,-16(fp)
+ 803ad50:	10c0010d 	sth	r3,4(r2)
+   uid++;
+ 803ad54:	d0a02f17 	ldw	r2,-32580(gp)
+ 803ad58:	10800044 	addi	r2,r2,1
+ 803ad5c:	d0a02f15 	stw	r2,-32580(gp)
+   pip->ip_len = htons((unshort)(p->nb_plen));
+ 803ad60:	e0bff917 	ldw	r2,-28(fp)
+ 803ad64:	10800417 	ldw	r2,16(r2)
+ 803ad68:	10bfffcc 	andi	r2,r2,65535
+ 803ad6c:	1004d23a 	srli	r2,r2,8
+ 803ad70:	1007883a 	mov	r3,r2
+ 803ad74:	e0bff917 	ldw	r2,-28(fp)
+ 803ad78:	10800417 	ldw	r2,16(r2)
+ 803ad7c:	10bfffcc 	andi	r2,r2,65535
+ 803ad80:	1004923a 	slli	r2,r2,8
+ 803ad84:	1884b03a 	or	r2,r3,r2
+ 803ad88:	1007883a 	mov	r3,r2
+ 803ad8c:	e0bffc17 	ldw	r2,-16(fp)
+ 803ad90:	10c0008d 	sth	r3,2(r2)
+   pip->ip_prot = prot;
+ 803ad94:	e0bffc17 	ldw	r2,-16(fp)
+ 803ad98:	e0fffa03 	ldbu	r3,-24(fp)
+ 803ad9c:	10c00245 	stb	r3,9(r2)
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+ 803ada0:	e0bffc17 	ldw	r2,-16(fp)
+ 803ada4:	1000028d 	sth	zero,10(r2)
+   ttl = IP_TTL;
+ 803ada8:	00801004 	movi	r2,64
+ 803adac:	e0bfffc5 	stb	r2,-1(fp)
+#ifdef IP_MULTICAST
+   if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL))
+ 803adb0:	e0bff917 	ldw	r2,-28(fp)
+ 803adb4:	10800717 	ldw	r2,28(r2)
+ 803adb8:	1006d63a 	srli	r3,r2,24
+ 803adbc:	e0bff917 	ldw	r2,-28(fp)
+ 803adc0:	10800717 	ldw	r2,28(r2)
+ 803adc4:	1004d23a 	srli	r2,r2,8
+ 803adc8:	10bfc00c 	andi	r2,r2,65280
+ 803adcc:	1886b03a 	or	r3,r3,r2
+ 803add0:	e0bff917 	ldw	r2,-28(fp)
+ 803add4:	10800717 	ldw	r2,28(r2)
+ 803add8:	1004923a 	slli	r2,r2,8
+ 803addc:	10803fec 	andhi	r2,r2,255
+ 803ade0:	1886b03a 	or	r3,r3,r2
+ 803ade4:	e0bff917 	ldw	r2,-28(fp)
+ 803ade8:	10800717 	ldw	r2,28(r2)
+ 803adec:	1004963a 	slli	r2,r2,24
+ 803adf0:	1884b03a 	or	r2,r3,r2
+ 803adf4:	10fc002c 	andhi	r3,r2,61440
+ 803adf8:	00b80034 	movhi	r2,57344
+ 803adfc:	1880071e 	bne	r3,r2,803ae1c <ip_write2+0x224>
+ 803ae00:	e0bff917 	ldw	r2,-28(fp)
+ 803ae04:	10800b17 	ldw	r2,44(r2)
+ 803ae08:	10000426 	beq	r2,zero,803ae1c <ip_write2+0x224>
+      ttl = p->imo->imo_multicast_ttl;
+ 803ae0c:	e0bff917 	ldw	r2,-28(fp)
+ 803ae10:	10800b17 	ldw	r2,44(r2)
+ 803ae14:	10800103 	ldbu	r2,4(r2)
+ 803ae18:	e0bfffc5 	stb	r2,-1(fp)
+#endif /* IP_MULTICAST */
+
+   /* have TOS or TTL been set (via socket options)? */
+   if ((sopts = p->soxopts))
+ 803ae1c:	e0bff917 	ldw	r2,-28(fp)
+ 803ae20:	10800c17 	ldw	r2,48(r2)
+ 803ae24:	e0bffb15 	stw	r2,-20(fp)
+ 803ae28:	e0bffb17 	ldw	r2,-20(fp)
+ 803ae2c:	10001126 	beq	r2,zero,803ae74 <ip_write2+0x27c>
+   {
+      if (sopts->ip_ttl)
+ 803ae30:	e0bffb17 	ldw	r2,-20(fp)
+ 803ae34:	10800043 	ldbu	r2,1(r2)
+ 803ae38:	10803fcc 	andi	r2,r2,255
+ 803ae3c:	10000526 	beq	r2,zero,803ae54 <ip_write2+0x25c>
+         pip->ip_time = sopts->ip_ttl;
+ 803ae40:	e0bffb17 	ldw	r2,-20(fp)
+ 803ae44:	10c00043 	ldbu	r3,1(r2)
+ 803ae48:	e0bffc17 	ldw	r2,-16(fp)
+ 803ae4c:	10c00205 	stb	r3,8(r2)
+ 803ae50:	00000306 	br	803ae60 <ip_write2+0x268>
+      else
+         pip->ip_time = ttl;
+ 803ae54:	e0bffc17 	ldw	r2,-16(fp)
+ 803ae58:	e0ffffc3 	ldbu	r3,-1(fp)
+ 803ae5c:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = sopts->ip_tos;
+ 803ae60:	e0bffb17 	ldw	r2,-20(fp)
+ 803ae64:	10c00003 	ldbu	r3,0(r2)
+ 803ae68:	e0bffc17 	ldw	r2,-16(fp)
+ 803ae6c:	10c00045 	stb	r3,1(r2)
+ 803ae70:	00000506 	br	803ae88 <ip_write2+0x290>
+   }
+   else
+   {
+      pip->ip_time = ttl;
+ 803ae74:	e0bffc17 	ldw	r2,-16(fp)
+ 803ae78:	e0ffffc3 	ldbu	r3,-1(fp)
+ 803ae7c:	10c00205 	stb	r3,8(r2)
+      pip->ip_tos = IP_TOS_DEFVAL;
+ 803ae80:	e0bffc17 	ldw	r2,-16(fp)
+ 803ae84:	10000045 	stb	zero,1(r2)
+   }
+
+   /* point to the start of the IP options, and insert the options */
+   for (tmpp = (u_char *)(p->nb_prot + sizeof(struct ip)); *optp != EOL_OPT; ++optp)
+ 803ae88:	e0bff917 	ldw	r2,-28(fp)
+ 803ae8c:	10800317 	ldw	r2,12(r2)
+ 803ae90:	10800504 	addi	r2,r2,20
+ 803ae94:	e0bffe15 	stw	r2,-8(fp)
+ 803ae98:	00001006 	br	803aedc <ip_write2+0x2e4>
+   {
+      /* caller has already provided adequate space for the requested options */
+      switch (*optp)
+ 803ae9c:	e0bff817 	ldw	r2,-32(fp)
+ 803aea0:	10800003 	ldbu	r2,0(r2)
+ 803aea4:	10803fcc 	andi	r2,r2,255
+ 803aea8:	10800518 	cmpnei	r2,r2,20
+ 803aeac:	1000071e 	bne	r2,zero,803aecc <ip_write2+0x2d4>
+      {
+         case IP_RTR_ALERT_OPT:
+            *((u_long *) tmpp) = htonl (IP_RTR_ALERT_OPT_DATA);
+ 803aeb0:	e0bffe17 	ldw	r2,-8(fp)
+ 803aeb4:	00c12504 	movi	r3,1172
+ 803aeb8:	10c00015 	stw	r3,0(r2)
+            /* this option is 4 bytes long */
+            tmpp += IP_RTR_ALERT_OPT_SIZE;
+ 803aebc:	e0bffe17 	ldw	r2,-8(fp)
+ 803aec0:	10800104 	addi	r2,r2,4
+ 803aec4:	e0bffe15 	stw	r2,-8(fp)
+            break;
+ 803aec8:	00000106 	br	803aed0 <ip_write2+0x2d8>
+         default:
+            break;
+ 803aecc:	0001883a 	nop
+   for (tmpp = (u_char *)(p->nb_prot + sizeof(struct ip)); *optp != EOL_OPT; ++optp)
+ 803aed0:	e0bff817 	ldw	r2,-32(fp)
+ 803aed4:	10800044 	addi	r2,r2,1
+ 803aed8:	e0bff815 	stw	r2,-32(fp)
+ 803aedc:	e0bff817 	ldw	r2,-32(fp)
+ 803aee0:	10800003 	ldbu	r2,0(r2)
+ 803aee4:	10803fcc 	andi	r2,r2,255
+ 803aee8:	103fec1e 	bne	r2,zero,803ae9c <ip_write2+0x2a4>
+      }
+   }
+
+   /* add one (or more) one-byte long End of Option options (if required) */
+   for (i = 0; i < iphlen_pad; ++i) *(tmpp + i) = 0;
+ 803aeec:	e03ffd85 	stb	zero,-10(fp)
+ 803aef0:	00000706 	br	803af10 <ip_write2+0x318>
+ 803aef4:	e0bffd83 	ldbu	r2,-10(fp)
+ 803aef8:	e0fffe17 	ldw	r3,-8(fp)
+ 803aefc:	1885883a 	add	r2,r3,r2
+ 803af00:	10000005 	stb	zero,0(r2)
+ 803af04:	e0bffd83 	ldbu	r2,-10(fp)
+ 803af08:	10800044 	addi	r2,r2,1
+ 803af0c:	e0bffd85 	stb	r2,-10(fp)
+ 803af10:	e0fffd83 	ldbu	r3,-10(fp)
+ 803af14:	e0bffdc3 	ldbu	r2,-9(fp)
+ 803af18:	18bff636 	bltu	r3,r2,803aef4 <ip_write2+0x2fc>
+   
+   /* checksum the IP header */
+   pip->ip_chksum = ~cksum (pip, ((iphlen + iphlen_pad)/2));
+ 803af1c:	e0ffff83 	ldbu	r3,-2(fp)
+ 803af20:	e0bffdc3 	ldbu	r2,-9(fp)
+ 803af24:	1885883a 	add	r2,r3,r2
+ 803af28:	1006d7fa 	srli	r3,r2,31
+ 803af2c:	1885883a 	add	r2,r3,r2
+ 803af30:	1005d07a 	srai	r2,r2,1
+ 803af34:	100b883a 	mov	r5,r2
+ 803af38:	e13ffc17 	ldw	r4,-16(fp)
+ 803af3c:	8026d7c0 	call	8026d7c <cksum>
+ 803af40:	0084303a 	nor	r2,zero,r2
+ 803af44:	1007883a 	mov	r3,r2
+ 803af48:	e0bffc17 	ldw	r2,-16(fp)
+ 803af4c:	10c0028d 	sth	r3,10(r2)
+
+   /* do the actual write */
+   return (ip_write_internal (p));
+ 803af50:	e13ff917 	ldw	r4,-28(fp)
+ 803af54:	803a2d40 	call	803a2d4 <ip_write_internal>
+}
+ 803af58:	e037883a 	mov	sp,fp
+ 803af5c:	dfc00117 	ldw	ra,4(sp)
+ 803af60:	df000017 	ldw	fp,0(sp)
+ 803af64:	dec00204 	addi	sp,sp,8
+ 803af68:	f800283a 	ret
+
+0803af6c <ip_raw_write>:
+ * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if 
+ * waiting for ARP, else negative error code if error detected. 
+ */
+int
+ip_raw_write(PACKET p)
+{
+ 803af6c:	defffc04 	addi	sp,sp,-16
+ 803af70:	dfc00315 	stw	ra,12(sp)
+ 803af74:	df000215 	stw	fp,8(sp)
+ 803af78:	df000204 	addi	fp,sp,8
+ 803af7c:	e13ffe15 	stw	r4,-8(fp)
+   struct ip * pip;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+ 803af80:	008201b4 	movhi	r2,2054
+ 803af84:	10b95817 	ldw	r2,-6816(r2)
+ 803af88:	10c00044 	addi	r3,r2,1
+ 803af8c:	008201b4 	movhi	r2,2054
+ 803af90:	10f95815 	stw	r3,-6816(r2)
+
+   /* form a pointer to IP header (pip) */
+   pip = (struct ip*)(p->nb_prot);
+ 803af94:	e0bffe17 	ldw	r2,-8(fp)
+ 803af98:	10800317 	ldw	r2,12(r2)
+ 803af9c:	e0bfff15 	stw	r2,-4(fp)
+   
+   /* if there's no IP id, give it one */
+   if (pip->ip_id == 0)
+ 803afa0:	e0bfff17 	ldw	r2,-4(fp)
+ 803afa4:	1080010b 	ldhu	r2,4(r2)
+ 803afa8:	10bfffcc 	andi	r2,r2,65535
+ 803afac:	10000e1e 	bne	r2,zero,803afe8 <ip_raw_write+0x7c>
+   {
+      pip->ip_id = htons((unshort)uid);
+ 803afb0:	d0a02f17 	ldw	r2,-32580(gp)
+ 803afb4:	10bfffcc 	andi	r2,r2,65535
+ 803afb8:	1004d23a 	srli	r2,r2,8
+ 803afbc:	1007883a 	mov	r3,r2
+ 803afc0:	d0a02f17 	ldw	r2,-32580(gp)
+ 803afc4:	10bfffcc 	andi	r2,r2,65535
+ 803afc8:	1004923a 	slli	r2,r2,8
+ 803afcc:	1884b03a 	or	r2,r3,r2
+ 803afd0:	1007883a 	mov	r3,r2
+ 803afd4:	e0bfff17 	ldw	r2,-4(fp)
+ 803afd8:	10c0010d 	sth	r3,4(r2)
+      uid++;
+ 803afdc:	d0a02f17 	ldw	r2,-32580(gp)
+ 803afe0:	10800044 	addi	r2,r2,1
+ 803afe4:	d0a02f15 	stw	r2,-32580(gp)
+   }
+
+   /* checksum the IP header */
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+ 803afe8:	e0bfff17 	ldw	r2,-4(fp)
+ 803afec:	1000028d 	sth	zero,10(r2)
+   pip->ip_chksum = ~cksum(pip, 10);
+ 803aff0:	01400284 	movi	r5,10
+ 803aff4:	e13fff17 	ldw	r4,-4(fp)
+ 803aff8:	8026d7c0 	call	8026d7c <cksum>
+ 803affc:	0084303a 	nor	r2,zero,r2
+ 803b000:	1007883a 	mov	r3,r2
+ 803b004:	e0bfff17 	ldw	r2,-4(fp)
+ 803b008:	10c0028d 	sth	r3,10(r2)
+
+   /* do the actual write */
+   return (ip_write_internal(p));
+ 803b00c:	e13ffe17 	ldw	r4,-8(fp)
+ 803b010:	803a2d40 	call	803a2d4 <ip_write_internal>
+}
+ 803b014:	e037883a 	mov	sp,fp
+ 803b018:	dfc00117 	ldw	ra,4(sp)
+ 803b01c:	df000017 	ldw	fp,0(sp)
+ 803b020:	dec00204 	addi	sp,sp,8
+ 803b024:	f800283a 	ret
+
+0803b028 <ip_mymach>:
+ * certain foreign host. 
+ */
+
+ip_addr
+ip_mymach(ip_addr host)
+{
+ 803b028:	defffa04 	addi	sp,sp,-24
+ 803b02c:	dfc00515 	stw	ra,20(sp)
+ 803b030:	df000415 	stw	fp,16(sp)
+ 803b034:	df000404 	addi	fp,sp,16
+ 803b038:	e13ffd15 	stw	r4,-12(fp)
+
+#ifndef MULTI_HOMED /* single static interface */
+   USE_ARG(host);
+   return(nets[0]->n_ipaddr);   /* always use address from only net */
+#else   /* MULTI_HOMED */
+   tnet = iproute(host, &temp);
+ 803b03c:	e0bffe04 	addi	r2,fp,-8
+ 803b040:	100b883a 	mov	r5,r2
+ 803b044:	e13ffd17 	ldw	r4,-12(fp)
+ 803b048:	803b3700 	call	803b370 <iproute>
+ 803b04c:	e0bfff15 	stw	r2,-4(fp)
+   if (tnet == 0)
+ 803b050:	e0bfff17 	ldw	r2,-4(fp)
+ 803b054:	1000161e 	bne	r2,zero,803b0b0 <ip_mymach+0x88>
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & (PROTERR|INFOMSG))
+ 803b058:	d0a06617 	ldw	r2,-32360(gp)
+ 803b05c:	1080050c 	andi	r2,r2,20
+ 803b060:	10001126 	beq	r2,zero,803b0a8 <ip_mymach+0x80>
+         dprintf("IP: Couldn't route to %u.%u.%u.%u\n", PUSH_IPADDR(host));
+ 803b064:	e0bffd17 	ldw	r2,-12(fp)
+ 803b068:	10c03fcc 	andi	r3,r2,255
+ 803b06c:	e0bffd17 	ldw	r2,-12(fp)
+ 803b070:	1004d23a 	srli	r2,r2,8
+ 803b074:	11003fcc 	andi	r4,r2,255
+ 803b078:	e0bffd17 	ldw	r2,-12(fp)
+ 803b07c:	1004d43a 	srli	r2,r2,16
+ 803b080:	11403fcc 	andi	r5,r2,255
+ 803b084:	e0bffd17 	ldw	r2,-12(fp)
+ 803b088:	1004d63a 	srli	r2,r2,24
+ 803b08c:	d8800015 	stw	r2,0(sp)
+ 803b090:	280f883a 	mov	r7,r5
+ 803b094:	200d883a 	mov	r6,r4
+ 803b098:	180b883a 	mov	r5,r3
+ 803b09c:	01020174 	movhi	r4,2053
+ 803b0a0:	212c4604 	addi	r4,r4,-20200
+ 803b0a4:	8002c780 	call	8002c78 <printf>
+#endif   /* NPDEBUG */
+      return 0L;
+ 803b0a8:	0005883a 	mov	r2,zero
+ 803b0ac:	00000206 	br	803b0b8 <ip_mymach+0x90>
+   }
+   return tnet->n_ipaddr;
+ 803b0b0:	e0bfff17 	ldw	r2,-4(fp)
+ 803b0b4:	10800a17 	ldw	r2,40(r2)
+#endif /* MULTI_HOMED */
+}
+ 803b0b8:	e037883a 	mov	sp,fp
+ 803b0bc:	dfc00117 	ldw	ra,4(sp)
+ 803b0c0:	df000017 	ldw	fp,0(sp)
+ 803b0c4:	dec00204 	addi	sp,sp,8
+ 803b0c8:	f800283a 	ret
+
+0803b0cc <ip_dump>:
+ * RETURNS: void
+ */
+
+void
+ip_dump(PACKET p)
+{
+ 803b0cc:	defff704 	addi	sp,sp,-36
+ 803b0d0:	dfc00815 	stw	ra,32(sp)
+ 803b0d4:	df000715 	stw	fp,28(sp)
+ 803b0d8:	df000704 	addi	fp,sp,28
+ 803b0dc:	e13ffc15 	stw	r4,-16(fp)
+   struct ip * pip;
+   unsigned char * cp;
+   unsigned short xsum, osum;
+
+   pip = ip_head(p);
+ 803b0e0:	e0bffc17 	ldw	r2,-16(fp)
+ 803b0e4:	10800317 	ldw	r2,12(r2)
+ 803b0e8:	e0bfff15 	stw	r2,-4(fp)
+   osum = pip->ip_chksum;
+ 803b0ec:	e0bfff17 	ldw	r2,-4(fp)
+ 803b0f0:	1080028b 	ldhu	r2,10(r2)
+ 803b0f4:	e0bffe8d 	sth	r2,-6(fp)
+   pip->ip_chksum = 0;
+ 803b0f8:	e0bfff17 	ldw	r2,-4(fp)
+ 803b0fc:	1000028d 	sth	zero,10(r2)
+   xsum = ~cksum(pip, ip_hlen(pip) >> 1);
+ 803b100:	e0bfff17 	ldw	r2,-4(fp)
+ 803b104:	10800003 	ldbu	r2,0(r2)
+ 803b108:	10803fcc 	andi	r2,r2,255
+ 803b10c:	100490ba 	slli	r2,r2,2
+ 803b110:	1005d07a 	srai	r2,r2,1
+ 803b114:	1080078c 	andi	r2,r2,30
+ 803b118:	100b883a 	mov	r5,r2
+ 803b11c:	e13fff17 	ldw	r4,-4(fp)
+ 803b120:	8026d7c0 	call	8026d7c <cksum>
+ 803b124:	0084303a 	nor	r2,zero,r2
+ 803b128:	e0bffe0d 	sth	r2,-8(fp)
+
+   if (osum != xsum)          /* trap here if checksum is wrong */
+ 803b12c:	e0fffe8b 	ldhu	r3,-6(fp)
+ 803b130:	e0bffe0b 	ldhu	r2,-8(fp)
+ 803b134:	18800126 	beq	r3,r2,803b13c <ip_dump+0x70>
+   {
+      dtrap();
+ 803b138:	8028cd40 	call	8028cd4 <dtrap>
+   /* dtrap() is fatal in the default Windows implementation, so
+    * we comment it out */
+   dtrap();       /* use debugger to view variables & packet */
+#endif
+
+   ns_printf(NULL ,"IP packet header:\n");
+ 803b13c:	01420174 	movhi	r5,2053
+ 803b140:	296c4f04 	addi	r5,r5,-20164
+ 803b144:	0009883a 	mov	r4,zero
+ 803b148:	80273900 	call	8027390 <ns_printf>
+   cp = (unsigned char *)pip;    /* make char pointer for bitmasks */
+ 803b14c:	e0bfff17 	ldw	r2,-4(fp)
+ 803b150:	e0bffd15 	stw	r2,-12(fp)
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+    *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id));
+ 803b154:	e0bffd17 	ldw	r2,-12(fp)
+ 803b158:	10800003 	ldbu	r2,0(r2)
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+ 803b15c:	11403fcc 	andi	r5,r2,255
+    *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id));
+ 803b160:	e0bffd17 	ldw	r2,-12(fp)
+ 803b164:	10800044 	addi	r2,r2,1
+ 803b168:	10800003 	ldbu	r2,0(r2)
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+ 803b16c:	11803fcc 	andi	r6,r2,255
+    *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id));
+ 803b170:	e0bfff17 	ldw	r2,-4(fp)
+ 803b174:	1080008b 	ldhu	r2,2(r2)
+ 803b178:	10bfffcc 	andi	r2,r2,65535
+ 803b17c:	1004d23a 	srli	r2,r2,8
+ 803b180:	10bfffcc 	andi	r2,r2,65535
+ 803b184:	10c03fcc 	andi	r3,r2,255
+ 803b188:	e0bfff17 	ldw	r2,-4(fp)
+ 803b18c:	1080008b 	ldhu	r2,2(r2)
+ 803b190:	10bfffcc 	andi	r2,r2,65535
+ 803b194:	1004923a 	slli	r2,r2,8
+ 803b198:	10bfffcc 	andi	r2,r2,65535
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+ 803b19c:	1884b03a 	or	r2,r3,r2
+    *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id));
+ 803b1a0:	e0ffff17 	ldw	r3,-4(fp)
+ 803b1a4:	18c0010b 	ldhu	r3,4(r3)
+ 803b1a8:	18ffffcc 	andi	r3,r3,65535
+ 803b1ac:	1806d23a 	srli	r3,r3,8
+ 803b1b0:	18ffffcc 	andi	r3,r3,65535
+ 803b1b4:	19003fcc 	andi	r4,r3,255
+ 803b1b8:	e0ffff17 	ldw	r3,-4(fp)
+ 803b1bc:	18c0010b 	ldhu	r3,4(r3)
+ 803b1c0:	18ffffcc 	andi	r3,r3,65535
+ 803b1c4:	1806923a 	slli	r3,r3,8
+ 803b1c8:	18ffffcc 	andi	r3,r3,65535
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+ 803b1cc:	20c6b03a 	or	r3,r4,r3
+ 803b1d0:	d8c00115 	stw	r3,4(sp)
+ 803b1d4:	d8800015 	stw	r2,0(sp)
+ 803b1d8:	300f883a 	mov	r7,r6
+ 803b1dc:	280d883a 	mov	r6,r5
+ 803b1e0:	01420174 	movhi	r5,2053
+ 803b1e4:	296c5404 	addi	r5,r5,-20144
+ 803b1e8:	0009883a 	mov	r4,zero
+ 803b1ec:	80273900 	call	8027390 <ns_printf>
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+    htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, 
+ 803b1f0:	e0bffd17 	ldw	r2,-12(fp)
+ 803b1f4:	10800184 	addi	r2,r2,6
+ 803b1f8:	1080000b 	ldhu	r2,0(r2)
+ 803b1fc:	10bfffcc 	andi	r2,r2,65535
+ 803b200:	1004d23a 	srli	r2,r2,8
+ 803b204:	10bfffcc 	andi	r2,r2,65535
+ 803b208:	10c03fcc 	andi	r3,r2,255
+ 803b20c:	e0bffd17 	ldw	r2,-12(fp)
+ 803b210:	10800184 	addi	r2,r2,6
+ 803b214:	1080000b 	ldhu	r2,0(r2)
+ 803b218:	10bfffcc 	andi	r2,r2,65535
+ 803b21c:	1004923a 	slli	r2,r2,8
+ 803b220:	10bfffcc 	andi	r2,r2,65535
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+ 803b224:	188cb03a 	or	r6,r3,r2
+    htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, 
+ 803b228:	e0bfff17 	ldw	r2,-4(fp)
+ 803b22c:	10800203 	ldbu	r2,8(r2)
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+ 803b230:	11c03fcc 	andi	r7,r2,255
+    htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, 
+ 803b234:	e0bfff17 	ldw	r2,-4(fp)
+ 803b238:	10800243 	ldbu	r2,9(r2)
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+ 803b23c:	10c03fcc 	andi	r3,r2,255
+    htons(osum), (osum==xsum)?"ok":"bad");
+ 803b240:	e0bffe8b 	ldhu	r2,-6(fp)
+ 803b244:	1004d23a 	srli	r2,r2,8
+ 803b248:	10bfffcc 	andi	r2,r2,65535
+ 803b24c:	11003fcc 	andi	r4,r2,255
+ 803b250:	e0bffe8b 	ldhu	r2,-6(fp)
+ 803b254:	1004923a 	slli	r2,r2,8
+ 803b258:	10bfffcc 	andi	r2,r2,65535
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+ 803b25c:	2088b03a 	or	r4,r4,r2
+ 803b260:	e17ffe8b 	ldhu	r5,-6(fp)
+ 803b264:	e0bffe0b 	ldhu	r2,-8(fp)
+ 803b268:	2880031e 	bne	r5,r2,803b278 <ip_dump+0x1ac>
+ 803b26c:	00820174 	movhi	r2,2053
+ 803b270:	10ac6004 	addi	r2,r2,-20096
+ 803b274:	00000206 	br	803b280 <ip_dump+0x1b4>
+ 803b278:	00820174 	movhi	r2,2053
+ 803b27c:	10ac6104 	addi	r2,r2,-20092
+ 803b280:	d8800215 	stw	r2,8(sp)
+ 803b284:	d9000115 	stw	r4,4(sp)
+ 803b288:	d8c00015 	stw	r3,0(sp)
+ 803b28c:	01420174 	movhi	r5,2053
+ 803b290:	296c6204 	addi	r5,r5,-20088
+ 803b294:	0009883a 	mov	r4,zero
+ 803b298:	80273900 	call	8027390 <ns_printf>
+   ns_printf(NULL ,"src: %u.%u.%u.%u  ", PUSH_IPADDR(pip->ip_src));
+ 803b29c:	e0bfff17 	ldw	r2,-4(fp)
+ 803b2a0:	10800317 	ldw	r2,12(r2)
+ 803b2a4:	11003fcc 	andi	r4,r2,255
+ 803b2a8:	e0bfff17 	ldw	r2,-4(fp)
+ 803b2ac:	10800317 	ldw	r2,12(r2)
+ 803b2b0:	1004d23a 	srli	r2,r2,8
+ 803b2b4:	11403fcc 	andi	r5,r2,255
+ 803b2b8:	e0bfff17 	ldw	r2,-4(fp)
+ 803b2bc:	10800317 	ldw	r2,12(r2)
+ 803b2c0:	1004d43a 	srli	r2,r2,16
+ 803b2c4:	10803fcc 	andi	r2,r2,255
+ 803b2c8:	e0ffff17 	ldw	r3,-4(fp)
+ 803b2cc:	18c00317 	ldw	r3,12(r3)
+ 803b2d0:	1806d63a 	srli	r3,r3,24
+ 803b2d4:	d8c00115 	stw	r3,4(sp)
+ 803b2d8:	d8800015 	stw	r2,0(sp)
+ 803b2dc:	280f883a 	mov	r7,r5
+ 803b2e0:	200d883a 	mov	r6,r4
+ 803b2e4:	01420174 	movhi	r5,2053
+ 803b2e8:	296c7204 	addi	r5,r5,-20024
+ 803b2ec:	0009883a 	mov	r4,zero
+ 803b2f0:	80273900 	call	8027390 <ns_printf>
+   ns_printf(NULL ,"dest: %u.%u.%u.%u\n", PUSH_IPADDR(pip->ip_dest));
+ 803b2f4:	e0bfff17 	ldw	r2,-4(fp)
+ 803b2f8:	10800417 	ldw	r2,16(r2)
+ 803b2fc:	11003fcc 	andi	r4,r2,255
+ 803b300:	e0bfff17 	ldw	r2,-4(fp)
+ 803b304:	10800417 	ldw	r2,16(r2)
+ 803b308:	1004d23a 	srli	r2,r2,8
+ 803b30c:	11403fcc 	andi	r5,r2,255
+ 803b310:	e0bfff17 	ldw	r2,-4(fp)
+ 803b314:	10800417 	ldw	r2,16(r2)
+ 803b318:	1004d43a 	srli	r2,r2,16
+ 803b31c:	10803fcc 	andi	r2,r2,255
+ 803b320:	e0ffff17 	ldw	r3,-4(fp)
+ 803b324:	18c00417 	ldw	r3,16(r3)
+ 803b328:	1806d63a 	srli	r3,r3,24
+ 803b32c:	d8c00115 	stw	r3,4(sp)
+ 803b330:	d8800015 	stw	r2,0(sp)
+ 803b334:	280f883a 	mov	r7,r5
+ 803b338:	200d883a 	mov	r6,r4
+ 803b33c:	01420174 	movhi	r5,2053
+ 803b340:	296c7704 	addi	r5,r5,-20004
+ 803b344:	0009883a 	mov	r4,zero
+ 803b348:	80273900 	call	8027390 <ns_printf>
+
+   pip->ip_chksum = osum;     /* fix what we clobbered */
+ 803b34c:	e0bfff17 	ldw	r2,-4(fp)
+ 803b350:	e0fffe8b 	ldhu	r3,-6(fp)
+ 803b354:	10c0028d 	sth	r3,10(r2)
+}
+ 803b358:	0001883a 	nop
+ 803b35c:	e037883a 	mov	sp,fp
+ 803b360:	dfc00117 	ldw	ra,4(sp)
+ 803b364:	df000017 	ldw	fp,0(sp)
+ 803b368:	dec00204 	addi	sp,sp,8
+ 803b36c:	f800283a 	ret
+
+0803b370 <iproute>:
+ * RETURNS: Returns NULL when unable to route, else returns a NET pointer.
+ */
+
+NET
+iproute(ip_addr host, ip_addr * hop1)
+{
+ 803b370:	defff804 	addi	sp,sp,-32
+ 803b374:	dfc00715 	stw	ra,28(sp)
+ 803b378:	df000615 	stw	fp,24(sp)
+ 803b37c:	df000604 	addi	fp,sp,24
+ 803b380:	e13ffc15 	stw	r4,-16(fp)
+ 803b384:	e17ffb15 	stw	r5,-20(fp)
+   NET      ifp;
+#ifdef IP_ROUTING
+   RTMIB    rtp;
+#endif   /* IP_ROUTING */
+
+   if (host == 0L)      /* Sanity check parameter. */
+ 803b388:	e0bffc17 	ldw	r2,-16(fp)
+ 803b38c:	1000021e 	bne	r2,zero,803b398 <iproute+0x28>
+      return NULL;
+ 803b390:	0005883a 	mov	r2,zero
+ 803b394:	00006406 	br	803b528 <iproute+0x1b8>
+    * stack has been initialized (tk_yield() gets called out of the 
+    * dialer code as part of PPP initialization), one symptom of 
+    * which is the routing table not being present yet. if this 
+    * happens, quit. 
+    */
+   if (rt_mib == NULL)
+ 803b398:	d0a09517 	ldw	r2,-32172(gp)
+ 803b39c:	1000021e 	bne	r2,zero,803b3a8 <iproute+0x38>
+      return NULL;
+ 803b3a0:	0005883a 	mov	r2,zero
+ 803b3a4:	00006006 	br	803b528 <iproute+0x1b8>
+#endif   /* BTREE_ROUTING */
+
+   /* see if the host matches the cached route */
+   if (cachedRoute)     /* don't test this if route is null  */
+ 803b3a8:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b3ac:	10000e26 	beq	r2,zero,803b3e8 <iproute+0x78>
+   {
+      if (cachedRoute->ipRouteDest == host)    /* exact match */
+ 803b3b0:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b3b4:	10800017 	ldw	r2,0(r2)
+ 803b3b8:	e0fffc17 	ldw	r3,-16(fp)
+ 803b3bc:	18800a1e 	bne	r3,r2,803b3e8 <iproute+0x78>
+      {
+         *hop1 = cachedRoute->ipRouteNextHop;   /* fill in nexthop IP addr */
+ 803b3c0:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b3c4:	10c00617 	ldw	r3,24(r2)
+ 803b3c8:	e0bffb17 	ldw	r2,-20(fp)
+ 803b3cc:	10c00015 	stw	r3,0(r2)
+         cachedRoute->ipRouteAge = cticks;      /* timestamp route entry */
+ 803b3d0:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b3d4:	d0e07d17 	ldw	r3,-32268(gp)
+ 803b3d8:	10c00915 	stw	r3,36(r2)
+         return(cachedRoute->ifp); /* net to send on */
+ 803b3dc:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b3e0:	10800e17 	ldw	r2,56(r2)
+ 803b3e4:	00005006 	br	803b528 <iproute+0x1b8>
+      }
+   }
+
+   rtp = rt_lookup(host);
+ 803b3e8:	e13ffc17 	ldw	r4,-16(fp)
+ 803b3ec:	803cb280 	call	803cb28 <rt_lookup>
+ 803b3f0:	e0bffd15 	stw	r2,-12(fp)
+   if(rtp)
+ 803b3f4:	e0bffd17 	ldw	r2,-12(fp)
+ 803b3f8:	10000926 	beq	r2,zero,803b420 <iproute+0xb0>
+   {
+      cachedRoute = rtp;
+ 803b3fc:	e0bffd17 	ldw	r2,-12(fp)
+ 803b400:	d0a09c15 	stw	r2,-32144(gp)
+      *hop1 = rtp->ipRouteNextHop;  /* fill in IP dest (next hop) */
+ 803b404:	e0bffd17 	ldw	r2,-12(fp)
+ 803b408:	10c00617 	ldw	r3,24(r2)
+ 803b40c:	e0bffb17 	ldw	r2,-20(fp)
+ 803b410:	10c00015 	stw	r3,0(r2)
+      return(rtp->ifp);             /* return pointer to net */
+ 803b414:	e0bffd17 	ldw	r2,-12(fp)
+ 803b418:	10800e17 	ldw	r2,56(r2)
+ 803b41c:	00004206 	br	803b528 <iproute+0x1b8>
+    * the initial state for the for loop that iterates through the
+    * list), but only build the iterator for multi-homed systems
+    * because single-homed systems are often memory-limited systems as
+    * well.  
+    */
+   ifp = (NET)(netlist.q_head);
+ 803b420:	008201b4 	movhi	r2,2054
+ 803b424:	10b6a617 	ldw	r2,-9576(r2)
+ 803b428:	e0bffe15 	stw	r2,-8(fp)
+   i = 0;
+ 803b42c:	e03fff15 	stw	zero,-4(fp)
+#ifdef MULTI_HOMED
+   for(; ifp; ifp = ifp->n_next, i++)
+ 803b430:	00002406 	br	803b4c4 <iproute+0x154>
+#endif /* MULTI_HOMED */
+   {
+      if((ifp->snmask != 0) &&      /* skip ifaces with no IP or subnet mask set */
+ 803b434:	e0bffe17 	ldw	r2,-8(fp)
+ 803b438:	10800c17 	ldw	r2,48(r2)
+ 803b43c:	10001b26 	beq	r2,zero,803b4ac <iproute+0x13c>
+         (ifp->n_ipaddr != 0) && 
+ 803b440:	e0bffe17 	ldw	r2,-8(fp)
+ 803b444:	10800a17 	ldw	r2,40(r2)
+      if((ifp->snmask != 0) &&      /* skip ifaces with no IP or subnet mask set */
+ 803b448:	10001826 	beq	r2,zero,803b4ac <iproute+0x13c>
+         ((ifp->n_ipaddr & ifp->snmask) == (host & ifp->snmask)))
+ 803b44c:	e0bffe17 	ldw	r2,-8(fp)
+ 803b450:	10c00a17 	ldw	r3,40(r2)
+ 803b454:	e0bffc17 	ldw	r2,-16(fp)
+ 803b458:	1886f03a 	xor	r3,r3,r2
+ 803b45c:	e0bffe17 	ldw	r2,-8(fp)
+ 803b460:	10800c17 	ldw	r2,48(r2)
+ 803b464:	1884703a 	and	r2,r3,r2
+         (ifp->n_ipaddr != 0) && 
+ 803b468:	1000101e 	bne	r2,zero,803b4ac <iproute+0x13c>
+      {
+#ifdef IP_ROUTING
+         /* make a cached Route entry for next time */
+         cachedRoute = add_route(host, 0xFFFFFFFF, host, i, IPRP_OTHER);
+ 803b46c:	00800044 	movi	r2,1
+ 803b470:	d8800015 	stw	r2,0(sp)
+ 803b474:	e1ffff17 	ldw	r7,-4(fp)
+ 803b478:	e1bffc17 	ldw	r6,-16(fp)
+ 803b47c:	017fffc4 	movi	r5,-1
+ 803b480:	e13ffc17 	ldw	r4,-16(fp)
+ 803b484:	803cc7c0 	call	803cc7c <add_route>
+ 803b488:	d0a09c15 	stw	r2,-32144(gp)
+#ifdef NPDEBUG
+         if (cachedRoute == NULL)
+ 803b48c:	d0a09c17 	ldw	r2,-32144(gp)
+ 803b490:	1000011e 	bne	r2,zero,803b498 <iproute+0x128>
+            dtrap();
+ 803b494:	8028cd40 	call	8028cd4 <dtrap>
+#endif   /* NPDEBUG */
+#endif   /* IP_ROUTING */
+         *hop1 = host;
+ 803b498:	e0bffb17 	ldw	r2,-20(fp)
+ 803b49c:	e0fffc17 	ldw	r3,-16(fp)
+ 803b4a0:	10c00015 	stw	r3,0(r2)
+         return ifp;
+ 803b4a4:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4a8:	00001f06 	br	803b528 <iproute+0x1b8>
+   for(; ifp; ifp = ifp->n_next, i++)
+ 803b4ac:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4b0:	10800017 	ldw	r2,0(r2)
+ 803b4b4:	e0bffe15 	stw	r2,-8(fp)
+ 803b4b8:	e0bfff17 	ldw	r2,-4(fp)
+ 803b4bc:	10800044 	addi	r2,r2,1
+ 803b4c0:	e0bfff15 	stw	r2,-4(fp)
+ 803b4c4:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4c8:	103fda1e 	bne	r2,zero,803b434 <iproute+0xc4>
+#endif   /* IP_LOOPBACK */
+
+   /* The host isn't on a net I'm on, so send it to the default 
+    * gateway on the first net which has one. 
+    */
+   ifp = (NET)(netlist.q_head);
+ 803b4cc:	008201b4 	movhi	r2,2054
+ 803b4d0:	10b6a617 	ldw	r2,-9576(r2)
+ 803b4d4:	e0bffe15 	stw	r2,-8(fp)
+#ifdef MULTI_HOMED
+   for(; ifp; ifp = ifp->n_next)
+ 803b4d8:	00000c06 	br	803b50c <iproute+0x19c>
+#endif   /* MULTI_HOMED */
+   {
+      /* Check if this net has a gateway */
+      if(ifp->n_defgw)
+ 803b4dc:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4e0:	10800d17 	ldw	r2,52(r2)
+ 803b4e4:	10000626 	beq	r2,zero,803b500 <iproute+0x190>
+      {
+         *hop1 = ifp->n_defgw;
+ 803b4e8:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4ec:	10c00d17 	ldw	r3,52(r2)
+ 803b4f0:	e0bffb17 	ldw	r2,-20(fp)
+ 803b4f4:	10c00015 	stw	r3,0(r2)
+         return ifp;
+ 803b4f8:	e0bffe17 	ldw	r2,-8(fp)
+ 803b4fc:	00000a06 	br	803b528 <iproute+0x1b8>
+   for(; ifp; ifp = ifp->n_next)
+ 803b500:	e0bffe17 	ldw	r2,-8(fp)
+ 803b504:	10800017 	ldw	r2,0(r2)
+ 803b508:	e0bffe15 	stw	r2,-8(fp)
+ 803b50c:	e0bffe17 	ldw	r2,-8(fp)
+ 803b510:	103ff21e 	bne	r2,zero,803b4dc <iproute+0x16c>
+   /* if no gateway is set, then change the first hop address to the 
+    * host we're trying to route to. this is just a kluge to make 
+    * this work with arp routing. otherwise, we would try to return 
+    * some sort of error indication. 
+    */
+   *hop1 = host;
+ 803b514:	e0bffb17 	ldw	r2,-20(fp)
+ 803b518:	e0fffc17 	ldw	r3,-16(fp)
+ 803b51c:	10c00015 	stw	r3,0(r2)
+   return((NET)(netlist.q_head));
+ 803b520:	008201b4 	movhi	r2,2054
+ 803b524:	10b6a617 	ldw	r2,-9576(r2)
+#endif   /* STRICT_SUBNETTING */
+}
+ 803b528:	e037883a 	mov	sp,fp
+ 803b52c:	dfc00117 	ldw	ra,4(sp)
+ 803b530:	df000017 	ldw	fp,0(sp)
+ 803b534:	dec00204 	addi	sp,sp,8
+ 803b538:	f800283a 	ret
+
+0803b53c <ip_copypkt>:
+ * RETURNS: a pointer to the new copy of the packet,
+ *          or NULL if no packet buffer could be allocated
+ */
+PACKET
+ip_copypkt(PACKET p)
+{
+ 803b53c:	defffb04 	addi	sp,sp,-20
+ 803b540:	dfc00415 	stw	ra,16(sp)
+ 803b544:	df000315 	stw	fp,12(sp)
+ 803b548:	df000304 	addi	fp,sp,12
+ 803b54c:	e13ffd15 	stw	r4,-12(fp)
+   int len;
+
+   /* figure out how much we need to copy from the packet, 
+    * and allocate a new buffer to hold it 
+    */
+   len = p->nb_plen + (p->nb_prot - p->nb_buff);
+ 803b550:	e0bffd17 	ldw	r2,-12(fp)
+ 803b554:	10800417 	ldw	r2,16(r2)
+ 803b558:	e0fffd17 	ldw	r3,-12(fp)
+ 803b55c:	19000317 	ldw	r4,12(r3)
+ 803b560:	e0fffd17 	ldw	r3,-12(fp)
+ 803b564:	18c00117 	ldw	r3,4(r3)
+ 803b568:	20c7c83a 	sub	r3,r4,r3
+ 803b56c:	10c5883a 	add	r2,r2,r3
+ 803b570:	e0bfff15 	stw	r2,-4(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b574:	01000084 	movi	r4,2
+ 803b578:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   np = pk_alloc(len);
+ 803b57c:	e0bfff17 	ldw	r2,-4(fp)
+ 803b580:	1009883a 	mov	r4,r2
+ 803b584:	80284340 	call	8028434 <pk_alloc>
+ 803b588:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b58c:	01000084 	movi	r4,2
+ 803b590:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (np == NULL)
+ 803b594:	e0bffe17 	ldw	r2,-8(fp)
+ 803b598:	1000061e 	bne	r2,zero,803b5b4 <ip_copypkt+0x78>
+   {
+#ifdef NPDEBUG
+      dprintf("ip_copypkt(): unable to obtain packet (len %d)\n", len);
+ 803b59c:	e17fff17 	ldw	r5,-4(fp)
+ 803b5a0:	01020174 	movhi	r4,2053
+ 803b5a4:	212c7c04 	addi	r4,r4,-19984
+ 803b5a8:	8002c780 	call	8002c78 <printf>
+#endif
+      return NULL;
+ 803b5ac:	0005883a 	mov	r2,zero
+ 803b5b0:	00002806 	br	803b654 <ip_copypkt+0x118>
+   }
+
+   /* copy packet data into new buffer */
+   MEMCPY(np->nb_buff, p->nb_buff, len);
+ 803b5b4:	e0bffe17 	ldw	r2,-8(fp)
+ 803b5b8:	10c00117 	ldw	r3,4(r2)
+ 803b5bc:	e0bffd17 	ldw	r2,-12(fp)
+ 803b5c0:	10800117 	ldw	r2,4(r2)
+ 803b5c4:	e13fff17 	ldw	r4,-4(fp)
+ 803b5c8:	200d883a 	mov	r6,r4
+ 803b5cc:	100b883a 	mov	r5,r2
+ 803b5d0:	1809883a 	mov	r4,r3
+ 803b5d4:	80086b80 	call	80086b8 <memcpy>
+
+   /* copy relevant packet fields */
+   np->nb_prot = np->nb_buff + (p->nb_prot - p->nb_buff);
+ 803b5d8:	e0bffe17 	ldw	r2,-8(fp)
+ 803b5dc:	10800117 	ldw	r2,4(r2)
+ 803b5e0:	e0fffd17 	ldw	r3,-12(fp)
+ 803b5e4:	19000317 	ldw	r4,12(r3)
+ 803b5e8:	e0fffd17 	ldw	r3,-12(fp)
+ 803b5ec:	18c00117 	ldw	r3,4(r3)
+ 803b5f0:	20c7c83a 	sub	r3,r4,r3
+ 803b5f4:	10c7883a 	add	r3,r2,r3
+ 803b5f8:	e0bffe17 	ldw	r2,-8(fp)
+ 803b5fc:	10c00315 	stw	r3,12(r2)
+   np->nb_plen = p->nb_plen;
+ 803b600:	e0bffd17 	ldw	r2,-12(fp)
+ 803b604:	10c00417 	ldw	r3,16(r2)
+ 803b608:	e0bffe17 	ldw	r2,-8(fp)
+ 803b60c:	10c00415 	stw	r3,16(r2)
+   np->net = p->net;
+ 803b610:	e0bffd17 	ldw	r2,-12(fp)
+ 803b614:	10c00617 	ldw	r3,24(r2)
+ 803b618:	e0bffe17 	ldw	r2,-8(fp)
+ 803b61c:	10c00615 	stw	r3,24(r2)
+   np->fhost = p->fhost;
+ 803b620:	e0bffd17 	ldw	r2,-12(fp)
+ 803b624:	10c00717 	ldw	r3,28(r2)
+ 803b628:	e0bffe17 	ldw	r2,-8(fp)
+ 803b62c:	10c00715 	stw	r3,28(r2)
+   np->type = p->type;
+ 803b630:	e0bffd17 	ldw	r2,-12(fp)
+ 803b634:	10c0080b 	ldhu	r3,32(r2)
+ 803b638:	e0bffe17 	ldw	r2,-8(fp)
+ 803b63c:	10c0080d 	sth	r3,32(r2)
+   np->nb_tstamp = p->nb_tstamp;
+ 803b640:	e0bffd17 	ldw	r2,-12(fp)
+ 803b644:	10c00517 	ldw	r3,20(r2)
+ 803b648:	e0bffe17 	ldw	r2,-8(fp)
+ 803b64c:	10c00515 	stw	r3,20(r2)
+
+   /* return pointer to the copy */
+   return np;
+ 803b650:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803b654:	e037883a 	mov	sp,fp
+ 803b658:	dfc00117 	ldw	ra,4(sp)
+ 803b65c:	df000017 	ldw	fp,0(sp)
+ 803b660:	dec00204 	addi	sp,sp,8
+ 803b664:	f800283a 	ret
+
+0803b668 <ip_rcv>:
+ * RETURNS: 
+ */
+
+int
+ip_rcv(PACKET p)
+{
+ 803b668:	defff404 	addi	sp,sp,-48
+ 803b66c:	dfc00b15 	stw	ra,44(sp)
+ 803b670:	df000a15 	stw	fp,40(sp)
+ 803b674:	dc000915 	stw	r16,36(sp)
+ 803b678:	df000a04 	addi	fp,sp,40
+ 803b67c:	e13ff615 	stw	r4,-40(fp)
+   unsigned hdrlen;  /* length of IP header including options */
+   unsigned len;     /* total length including IP header */
+   unsigned short int num_pkts;
+   PACKET * pktp;
+   unsigned char i;
+   int rcvrc = -1;
+ 803b680:	00bfffc4 	movi	r2,-1
+ 803b684:	e0bffd15 	stw	r2,-12(fp)
+   unsigned char rc_ret;
+#endif
+
+
+#ifdef NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803b688:	d0a06617 	ldw	r2,-32360(gp)
+ 803b68c:	1081000c 	andi	r2,r2,1024
+ 803b690:	10000e26 	beq	r2,zero,803b6cc <ip_rcv+0x64>
+ 803b694:	d0a06617 	ldw	r2,-32360(gp)
+ 803b698:	1080800c 	andi	r2,r2,512
+ 803b69c:	10000b26 	beq	r2,zero,803b6cc <ip_rcv+0x64>
+      dprintf("ip_rcv: got packet, len:%d, if:%d\n",
+         p->nb_plen, net_num(p->net));
+ 803b6a0:	e0bff617 	ldw	r2,-40(fp)
+      dprintf("ip_rcv: got packet, len:%d, if:%d\n",
+ 803b6a4:	14000417 	ldw	r16,16(r2)
+         p->nb_plen, net_num(p->net));
+ 803b6a8:	e0bff617 	ldw	r2,-40(fp)
+      dprintf("ip_rcv: got packet, len:%d, if:%d\n",
+ 803b6ac:	10800617 	ldw	r2,24(r2)
+ 803b6b0:	1009883a 	mov	r4,r2
+ 803b6b4:	80252fc0 	call	80252fc <if_netnumber>
+ 803b6b8:	100d883a 	mov	r6,r2
+ 803b6bc:	800b883a 	mov	r5,r16
+ 803b6c0:	01020174 	movhi	r4,2053
+ 803b6c4:	212c8804 	addi	r4,r4,-19936
+ 803b6c8:	8002c780 	call	8002c78 <printf>
+#endif
+
+   IN_PROFILER(PF_IP, PF_ENTRY);
+
+   ip_mib.ipInReceives++;
+ 803b6cc:	008201b4 	movhi	r2,2054
+ 803b6d0:	10b95117 	ldw	r2,-6844(r2)
+ 803b6d4:	10c00044 	addi	r3,r2,1
+ 803b6d8:	008201b4 	movhi	r2,2054
+ 803b6dc:	10f95115 	stw	r3,-6844(r2)
+   pip = ip_head(p);
+ 803b6e0:	e0bff617 	ldw	r2,-40(fp)
+ 803b6e4:	10800317 	ldw	r2,12(r2)
+ 803b6e8:	e0bffc15 	stw	r2,-16(fp)
+
+   /* test received MAC len against IP header len */
+   if (p->nb_plen < (unsigned)htons(pip->ip_len))
+ 803b6ec:	e0bff617 	ldw	r2,-40(fp)
+ 803b6f0:	10800417 	ldw	r2,16(r2)
+ 803b6f4:	e0fffc17 	ldw	r3,-16(fp)
+ 803b6f8:	18c0008b 	ldhu	r3,2(r3)
+ 803b6fc:	18ffffcc 	andi	r3,r3,65535
+ 803b700:	1806d23a 	srli	r3,r3,8
+ 803b704:	18ffffcc 	andi	r3,r3,65535
+ 803b708:	19003fcc 	andi	r4,r3,255
+ 803b70c:	e0fffc17 	ldw	r3,-16(fp)
+ 803b710:	18c0008b 	ldhu	r3,2(r3)
+ 803b714:	18ffffcc 	andi	r3,r3,65535
+ 803b718:	1806923a 	slli	r3,r3,8
+ 803b71c:	18ffffcc 	andi	r3,r3,65535
+ 803b720:	20c6b03a 	or	r3,r4,r3
+ 803b724:	10c01d2e 	bgeu	r2,r3,803b79c <ip_rcv+0x134>
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803b728:	d0a06617 	ldw	r2,-32360(gp)
+ 803b72c:	1081000c 	andi	r2,r2,1024
+ 803b730:	10000c26 	beq	r2,zero,803b764 <ip_rcv+0xfc>
+ 803b734:	d0a06617 	ldw	r2,-32360(gp)
+ 803b738:	1080800c 	andi	r2,r2,512
+ 803b73c:	10000926 	beq	r2,zero,803b764 <ip_rcv+0xfc>
+      {
+         dprintf("ip_rcv: bad pkt len\n");
+ 803b740:	01020174 	movhi	r4,2053
+ 803b744:	212c9104 	addi	r4,r4,-19900
+ 803b748:	8002d9c0 	call	8002d9c <puts>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 803b74c:	d0a06617 	ldw	r2,-32360(gp)
+ 803b750:	1080008c 	andi	r2,r2,2
+ 803b754:	10000326 	beq	r2,zero,803b764 <ip_rcv+0xfc>
+ 803b758:	e0bff617 	ldw	r2,-40(fp)
+ 803b75c:	1009883a 	mov	r4,r2
+ 803b760:	803b0cc0 	call	803b0cc <ip_dump>
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+ 803b764:	008201b4 	movhi	r2,2054
+ 803b768:	10b95217 	ldw	r2,-6840(r2)
+ 803b76c:	10c00044 	addi	r3,r2,1
+ 803b770:	008201b4 	movhi	r2,2054
+ 803b774:	10f95215 	stw	r3,-6840(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b778:	01000084 	movi	r4,2
+ 803b77c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 803b780:	e0bff617 	ldw	r2,-40(fp)
+ 803b784:	1009883a 	mov	r4,r2
+ 803b788:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b78c:	01000084 	movi	r4,2
+ 803b790:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+ 803b794:	00bff804 	movi	r2,-32
+ 803b798:	00008206 	br	803b9a4 <ip_rcv+0x33c>
+   }
+
+   /* use length from IP header; MAC value may be padded */
+   len = htons(pip->ip_len);
+ 803b79c:	e0bffc17 	ldw	r2,-16(fp)
+ 803b7a0:	1080008b 	ldhu	r2,2(r2)
+ 803b7a4:	10bfffcc 	andi	r2,r2,65535
+ 803b7a8:	1004d23a 	srli	r2,r2,8
+ 803b7ac:	10bfffcc 	andi	r2,r2,65535
+ 803b7b0:	10c03fcc 	andi	r3,r2,255
+ 803b7b4:	e0bffc17 	ldw	r2,-16(fp)
+ 803b7b8:	1080008b 	ldhu	r2,2(r2)
+ 803b7bc:	10bfffcc 	andi	r2,r2,65535
+ 803b7c0:	1004923a 	slli	r2,r2,8
+ 803b7c4:	10bfffcc 	andi	r2,r2,65535
+ 803b7c8:	1884b03a 	or	r2,r3,r2
+ 803b7cc:	e0bffb15 	stw	r2,-20(fp)
+   p->nb_plen = len;       /* fix pkt len */
+ 803b7d0:	e0bff617 	ldw	r2,-40(fp)
+ 803b7d4:	e0fffb17 	ldw	r3,-20(fp)
+ 803b7d8:	10c00415 	stw	r3,16(r2)
+
+   if ( ((pip->ip_ver_ihl & 0xf0) >> 4) != IP_VER)
+ 803b7dc:	e0bffc17 	ldw	r2,-16(fp)
+ 803b7e0:	10800003 	ldbu	r2,0(r2)
+ 803b7e4:	10803fcc 	andi	r2,r2,255
+ 803b7e8:	1004d13a 	srli	r2,r2,4
+ 803b7ec:	10803fcc 	andi	r2,r2,255
+ 803b7f0:	10800120 	cmpeqi	r2,r2,4
+ 803b7f4:	10001d1e 	bne	r2,zero,803b86c <ip_rcv+0x204>
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803b7f8:	d0a06617 	ldw	r2,-32360(gp)
+ 803b7fc:	1081000c 	andi	r2,r2,1024
+ 803b800:	10000c26 	beq	r2,zero,803b834 <ip_rcv+0x1cc>
+ 803b804:	d0a06617 	ldw	r2,-32360(gp)
+ 803b808:	1080800c 	andi	r2,r2,512
+ 803b80c:	10000926 	beq	r2,zero,803b834 <ip_rcv+0x1cc>
+      {
+         dprintf("ip_rcv: bad version number\n");
+ 803b810:	01020174 	movhi	r4,2053
+ 803b814:	212c9604 	addi	r4,r4,-19880
+ 803b818:	8002d9c0 	call	8002d9c <puts>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 803b81c:	d0a06617 	ldw	r2,-32360(gp)
+ 803b820:	1080008c 	andi	r2,r2,2
+ 803b824:	10000326 	beq	r2,zero,803b834 <ip_rcv+0x1cc>
+ 803b828:	e0bff617 	ldw	r2,-40(fp)
+ 803b82c:	1009883a 	mov	r4,r2
+ 803b830:	803b0cc0 	call	803b0cc <ip_dump>
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+ 803b834:	008201b4 	movhi	r2,2054
+ 803b838:	10b95217 	ldw	r2,-6840(r2)
+ 803b83c:	10c00044 	addi	r3,r2,1
+ 803b840:	008201b4 	movhi	r2,2054
+ 803b844:	10f95215 	stw	r3,-6840(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b848:	01000084 	movi	r4,2
+ 803b84c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 803b850:	e0bff617 	ldw	r2,-40(fp)
+ 803b854:	1009883a 	mov	r4,r2
+ 803b858:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b85c:	01000084 	movi	r4,2
+ 803b860:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+ 803b864:	00bff804 	movi	r2,-32
+ 803b868:	00004e06 	br	803b9a4 <ip_rcv+0x33c>
+   }
+
+   csum = pip->ip_chksum;
+ 803b86c:	e0bffc17 	ldw	r2,-16(fp)
+ 803b870:	1080028b 	ldhu	r2,10(r2)
+ 803b874:	e0bffa8d 	sth	r2,-22(fp)
+   pip->ip_chksum = 0;
+ 803b878:	e0bffc17 	ldw	r2,-16(fp)
+ 803b87c:	1000028d 	sth	zero,10(r2)
+   hdrlen = ip_hlen(pip);
+ 803b880:	e0bffc17 	ldw	r2,-16(fp)
+ 803b884:	10800003 	ldbu	r2,0(r2)
+ 803b888:	10803fcc 	andi	r2,r2,255
+ 803b88c:	100490ba 	slli	r2,r2,2
+ 803b890:	10800f0c 	andi	r2,r2,60
+ 803b894:	e0bff915 	stw	r2,-28(fp)
+   tempsum = ~cksum(pip, hdrlen >> 1);
+ 803b898:	e0bff917 	ldw	r2,-28(fp)
+ 803b89c:	1004d07a 	srli	r2,r2,1
+ 803b8a0:	100b883a 	mov	r5,r2
+ 803b8a4:	e13ffc17 	ldw	r4,-16(fp)
+ 803b8a8:	8026d7c0 	call	8026d7c <cksum>
+ 803b8ac:	0084303a 	nor	r2,zero,r2
+ 803b8b0:	e0bff88d 	sth	r2,-30(fp)
+
+   if (csum != tempsum)
+ 803b8b4:	e0fffa8b 	ldhu	r3,-22(fp)
+ 803b8b8:	e0bff88b 	ldhu	r2,-30(fp)
+ 803b8bc:	18802026 	beq	r3,r2,803b940 <ip_rcv+0x2d8>
+   {
+      pip->ip_chksum = csum;
+ 803b8c0:	e0bffc17 	ldw	r2,-16(fp)
+ 803b8c4:	e0fffa8b 	ldhu	r3,-22(fp)
+ 803b8c8:	10c0028d 	sth	r3,10(r2)
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803b8cc:	d0a06617 	ldw	r2,-32360(gp)
+ 803b8d0:	1081000c 	andi	r2,r2,1024
+ 803b8d4:	10000c26 	beq	r2,zero,803b908 <ip_rcv+0x2a0>
+ 803b8d8:	d0a06617 	ldw	r2,-32360(gp)
+ 803b8dc:	1080800c 	andi	r2,r2,512
+ 803b8e0:	10000926 	beq	r2,zero,803b908 <ip_rcv+0x2a0>
+      {
+         dprintf("ip_rcv: bad xsum\n");
+ 803b8e4:	01020174 	movhi	r4,2053
+ 803b8e8:	212c9d04 	addi	r4,r4,-19852
+ 803b8ec:	8002d9c0 	call	8002d9c <puts>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 803b8f0:	d0a06617 	ldw	r2,-32360(gp)
+ 803b8f4:	1080008c 	andi	r2,r2,2
+ 803b8f8:	10000326 	beq	r2,zero,803b908 <ip_rcv+0x2a0>
+ 803b8fc:	e0bff617 	ldw	r2,-40(fp)
+ 803b900:	1009883a 	mov	r4,r2
+ 803b904:	803b0cc0 	call	803b0cc <ip_dump>
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+ 803b908:	008201b4 	movhi	r2,2054
+ 803b90c:	10b95217 	ldw	r2,-6840(r2)
+ 803b910:	10c00044 	addi	r3,r2,1
+ 803b914:	008201b4 	movhi	r2,2054
+ 803b918:	10f95215 	stw	r3,-6840(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b91c:	01000084 	movi	r4,2
+ 803b920:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 803b924:	e0bff617 	ldw	r2,-40(fp)
+ 803b928:	1009883a 	mov	r4,r2
+ 803b92c:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803b930:	01000084 	movi	r4,2
+ 803b934:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+ 803b938:	00bff804 	movi	r2,-32
+ 803b93c:	00001906 	br	803b9a4 <ip_rcv+0x33c>
+   }
+
+   pip->ip_chksum = csum;
+ 803b940:	e0bffc17 	ldw	r2,-16(fp)
+ 803b944:	e0fffa8b 	ldhu	r3,-22(fp)
+ 803b948:	10c0028d 	sth	r3,10(r2)
+#endif
+
+    /* start off by assuming that we will only process the "current" packet;
+     * these values may get overwritten by the NAT module if it returns
+     * more than one packet back to this function (ip_rcv ()) */
+    num_pkts = 1;
+ 803b94c:	00800044 	movi	r2,1
+ 803b950:	e0bff80d 	sth	r2,-32(fp)
+    pktp = &p;
+ 803b954:	e0bff604 	addi	r2,fp,-40
+ 803b958:	e0bff715 	stw	r2,-36(fp)
+    * by other modules */
+#endif   /* NATRT */
+
+   /* we need to process 'num_pkts' packets.  Pointers to these packets are stored
+    * in storage @ 'pktp' */
+   for (i = 0; i < num_pkts; ++i)
+ 803b95c:	e03ffec5 	stb	zero,-5(fp)
+ 803b960:	00000b06 	br	803b990 <ip_rcv+0x328>
+   {
+      rcvrc = ip_rcv_phase2 (*(pktp + i));
+ 803b964:	e0bffec3 	ldbu	r2,-5(fp)
+ 803b968:	100490ba 	slli	r2,r2,2
+ 803b96c:	e0fff717 	ldw	r3,-36(fp)
+ 803b970:	1885883a 	add	r2,r3,r2
+ 803b974:	10800017 	ldw	r2,0(r2)
+ 803b978:	1009883a 	mov	r4,r2
+ 803b97c:	803b9bc0 	call	803b9bc <ip_rcv_phase2>
+ 803b980:	e0bffd15 	stw	r2,-12(fp)
+   for (i = 0; i < num_pkts; ++i)
+ 803b984:	e0bffec3 	ldbu	r2,-5(fp)
+ 803b988:	10800044 	addi	r2,r2,1
+ 803b98c:	e0bffec5 	stb	r2,-5(fp)
+ 803b990:	e0fffec3 	ldbu	r3,-5(fp)
+ 803b994:	e0bff80b 	ldhu	r2,-32(fp)
+ 803b998:	18ffffcc 	andi	r3,r3,65535
+ 803b99c:	18bff136 	bltu	r3,r2,803b964 <ip_rcv+0x2fc>
+   if (pktp != &p) nat_free (pktp);
+#endif /* NATRT */
+
+   /* when multiple packets are processed in the loop above, the return code
+    * contains the return code for the last packet */
+   return rcvrc;
+ 803b9a0:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 803b9a4:	e6ffff04 	addi	sp,fp,-4
+ 803b9a8:	dfc00217 	ldw	ra,8(sp)
+ 803b9ac:	df000117 	ldw	fp,4(sp)
+ 803b9b0:	dc000017 	ldw	r16,0(sp)
+ 803b9b4:	dec00304 	addi	sp,sp,12
+ 803b9b8:	f800283a 	ret
+
+0803b9bc <ip_rcv_phase2>:
+
+
+int ip_rcv_phase2 (PACKET p)
+{
+ 803b9bc:	defff604 	addi	sp,sp,-40
+ 803b9c0:	dfc00915 	stw	ra,36(sp)
+ 803b9c4:	df000815 	stw	fp,32(sp)
+ 803b9c8:	df000804 	addi	fp,sp,32
+ 803b9cc:	e13ff915 	stw	r4,-28(fp)
+
+   struct ip * pip;     /* the internet header */
+   NET nt;
+   unsigned short tempsum;
+
+   pip = ip_head(p);
+ 803b9d0:	e0bff917 	ldw	r2,-28(fp)
+ 803b9d4:	10800317 	ldw	r2,12(r2)
+ 803b9d8:	e0bfff15 	stw	r2,-4(fp)
+   nt = p->net;      /* which interface it came in on */
+ 803b9dc:	e0bff917 	ldw	r2,-28(fp)
+ 803b9e0:	10800617 	ldw	r2,24(r2)
+ 803b9e4:	e0bffe15 	stw	r2,-8(fp)
+
+#ifdef IP_MULTICAST
+
+   if (IN_MULTICAST(ntohl(pip->ip_dest))) 
+ 803b9e8:	e0bfff17 	ldw	r2,-4(fp)
+ 803b9ec:	10800417 	ldw	r2,16(r2)
+ 803b9f0:	1006d63a 	srli	r3,r2,24
+ 803b9f4:	e0bfff17 	ldw	r2,-4(fp)
+ 803b9f8:	10800417 	ldw	r2,16(r2)
+ 803b9fc:	1004d23a 	srli	r2,r2,8
+ 803ba00:	10bfc00c 	andi	r2,r2,65280
+ 803ba04:	1886b03a 	or	r3,r3,r2
+ 803ba08:	e0bfff17 	ldw	r2,-4(fp)
+ 803ba0c:	10800417 	ldw	r2,16(r2)
+ 803ba10:	1004923a 	slli	r2,r2,8
+ 803ba14:	10803fec 	andhi	r2,r2,255
+ 803ba18:	1886b03a 	or	r3,r3,r2
+ 803ba1c:	e0bfff17 	ldw	r2,-4(fp)
+ 803ba20:	10800417 	ldw	r2,16(r2)
+ 803ba24:	1004963a 	slli	r2,r2,24
+ 803ba28:	1884b03a 	or	r2,r3,r2
+ 803ba2c:	10fc002c 	andhi	r3,r2,61440
+ 803ba30:	00b80034 	movhi	r2,57344
+ 803ba34:	1880151e 	bne	r3,r2,803ba8c <ip_rcv_phase2+0xd0>
+      struct in_multi * inm;
+      /*
+       * See if we belong to the destination multicast group on the
+       * arrival interface.
+       */
+      inm = lookup_mcast(pip->ip_dest, nt);
+ 803ba38:	e0bfff17 	ldw	r2,-4(fp)
+ 803ba3c:	10800417 	ldw	r2,16(r2)
+ 803ba40:	e17ffe17 	ldw	r5,-8(fp)
+ 803ba44:	1009883a 	mov	r4,r2
+ 803ba48:	803c5040 	call	803c504 <lookup_mcast>
+ 803ba4c:	e0bffd15 	stw	r2,-12(fp)
+      if (inm == NULL) 
+ 803ba50:	e0bffd17 	ldw	r2,-12(fp)
+ 803ba54:	1000dc1e 	bne	r2,zero,803bdc8 <ip_rcv_phase2+0x40c>
+      {
+         ip_mib.ipOutNoRoutes++;
+ 803ba58:	008201b4 	movhi	r2,2054
+ 803ba5c:	10b95a17 	ldw	r2,-6808(r2)
+ 803ba60:	10c00044 	addi	r3,r2,1
+ 803ba64:	008201b4 	movhi	r2,2054
+ 803ba68:	10f95a15 	stw	r3,-6808(r2)
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803ba6c:	01000084 	movi	r4,2
+ 803ba70:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803ba74:	e13ff917 	ldw	r4,-28(fp)
+ 803ba78:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803ba7c:	01000084 	movi	r4,2
+ 803ba80:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NOT_MINE);
+ 803ba84:	00800084 	movi	r2,2
+ 803ba88:	00011a06 	br	803bef4 <ip_rcv_phase2+0x538>
+      else
+         goto ours;
+   }
+#endif   /* IP_MULTICAST */
+
+   if ((pip->ip_dest != nt->n_ipaddr) &&  /* Quick check on our own addr */
+ 803ba8c:	e0bfff17 	ldw	r2,-4(fp)
+ 803ba90:	10c00417 	ldw	r3,16(r2)
+ 803ba94:	e0bffe17 	ldw	r2,-8(fp)
+ 803ba98:	10800a17 	ldw	r2,40(r2)
+ 803ba9c:	1880cc26 	beq	r3,r2,803bdd0 <ip_rcv_phase2+0x414>
+       (pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+ 803baa0:	e0bfff17 	ldw	r2,-4(fp)
+ 803baa4:	10800417 	ldw	r2,16(r2)
+   if ((pip->ip_dest != nt->n_ipaddr) &&  /* Quick check on our own addr */
+ 803baa8:	10bfffe0 	cmpeqi	r2,r2,-1
+ 803baac:	1000c81e 	bne	r2,zero,803bdd0 <ip_rcv_phase2+0x414>
+       (pip->ip_dest != nt->n_netbr) &&   /* All subnet broadcast */
+ 803bab0:	e0bfff17 	ldw	r2,-4(fp)
+ 803bab4:	10c00417 	ldw	r3,16(r2)
+ 803bab8:	e0bffe17 	ldw	r2,-8(fp)
+ 803babc:	10800e17 	ldw	r2,56(r2)
+       (pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+ 803bac0:	1880c326 	beq	r3,r2,803bdd0 <ip_rcv_phase2+0x414>
+       (pip->ip_dest != nt->n_netbr42) && /* All subnet bcast (4.2bsd) */
+ 803bac4:	e0bfff17 	ldw	r2,-4(fp)
+ 803bac8:	10c00417 	ldw	r3,16(r2)
+ 803bacc:	e0bffe17 	ldw	r2,-8(fp)
+ 803bad0:	10800f17 	ldw	r2,60(r2)
+       (pip->ip_dest != nt->n_netbr) &&   /* All subnet broadcast */
+ 803bad4:	1880be26 	beq	r3,r2,803bdd0 <ip_rcv_phase2+0x414>
+       (pip->ip_dest != nt->n_subnetbr) &&/* Our subnet broadcast */
+ 803bad8:	e0bfff17 	ldw	r2,-4(fp)
+ 803badc:	10c00417 	ldw	r3,16(r2)
+ 803bae0:	e0bffe17 	ldw	r2,-8(fp)
+ 803bae4:	10801017 	ldw	r2,64(r2)
+       (pip->ip_dest != nt->n_netbr42) && /* All subnet bcast (4.2bsd) */
+ 803bae8:	1880b926 	beq	r3,r2,803bdd0 <ip_rcv_phase2+0x414>
+       (nt->n_ipaddr & ~nt->snmask))      /* Know our own host address? */
+ 803baec:	e0bffe17 	ldw	r2,-8(fp)
+ 803baf0:	10c00a17 	ldw	r3,40(r2)
+ 803baf4:	e0bffe17 	ldw	r2,-8(fp)
+ 803baf8:	10800c17 	ldw	r2,48(r2)
+ 803bafc:	0084303a 	nor	r2,zero,r2
+ 803bb00:	1884703a 	and	r2,r3,r2
+       (pip->ip_dest != nt->n_subnetbr) &&/* Our subnet broadcast */
+ 803bb04:	1000b226 	beq	r2,zero,803bdd0 <ip_rcv_phase2+0x414>
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803bb08:	d0a06617 	ldw	r2,-32360(gp)
+ 803bb0c:	1081000c 	andi	r2,r2,1024
+ 803bb10:	10001826 	beq	r2,zero,803bb74 <ip_rcv_phase2+0x1b8>
+ 803bb14:	d0a06617 	ldw	r2,-32360(gp)
+ 803bb18:	1080800c 	andi	r2,r2,512
+ 803bb1c:	10001526 	beq	r2,zero,803bb74 <ip_rcv_phase2+0x1b8>
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+       PUSH_IPADDR(pip->ip_dest));
+ 803bb20:	e0bfff17 	ldw	r2,-4(fp)
+ 803bb24:	10800417 	ldw	r2,16(r2)
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+ 803bb28:	10c03fcc 	andi	r3,r2,255
+       PUSH_IPADDR(pip->ip_dest));
+ 803bb2c:	e0bfff17 	ldw	r2,-4(fp)
+ 803bb30:	10800417 	ldw	r2,16(r2)
+ 803bb34:	1004d23a 	srli	r2,r2,8
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+ 803bb38:	11003fcc 	andi	r4,r2,255
+       PUSH_IPADDR(pip->ip_dest));
+ 803bb3c:	e0bfff17 	ldw	r2,-4(fp)
+ 803bb40:	10800417 	ldw	r2,16(r2)
+ 803bb44:	1004d43a 	srli	r2,r2,16
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+ 803bb48:	11403fcc 	andi	r5,r2,255
+       PUSH_IPADDR(pip->ip_dest));
+ 803bb4c:	e0bfff17 	ldw	r2,-4(fp)
+ 803bb50:	10800417 	ldw	r2,16(r2)
+ 803bb54:	1004d63a 	srli	r2,r2,24
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+ 803bb58:	d8800015 	stw	r2,0(sp)
+ 803bb5c:	280f883a 	mov	r7,r5
+ 803bb60:	200d883a 	mov	r6,r4
+ 803bb64:	180b883a 	mov	r5,r3
+ 803bb68:	01020174 	movhi	r4,2053
+ 803bb6c:	212ca204 	addi	r4,r4,-19832
+ 803bb70:	8002c780 	call	8002c78 <printf>
+
+#ifdef IP_ROUTING    /* if multi-homed router, try to route */
+      /* Do routing only if ipForwarding is enabled in the IP MIB. This
+       * is the switch for routing whether SNMP is used or not.
+       */
+      if (ip_mib.ipForwarding == 2)
+ 803bb74:	008201b4 	movhi	r2,2054
+ 803bb78:	10b94f17 	ldw	r2,-6852(r2)
+ 803bb7c:	10800098 	cmpnei	r2,r2,2
+ 803bb80:	10000d1e 	bne	r2,zero,803bbb8 <ip_rcv_phase2+0x1fc>
+      {
+         ip_mib.ipOutDiscards++; /* Is this the right counter for these? */
+ 803bb84:	008201b4 	movhi	r2,2054
+ 803bb88:	10b95917 	ldw	r2,-6812(r2)
+ 803bb8c:	10c00044 	addi	r3,r2,1
+ 803bb90:	008201b4 	movhi	r2,2054
+ 803bb94:	10f95915 	stw	r3,-6812(r2)
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bb98:	01000084 	movi	r4,2
+ 803bb9c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+         pk_free(p);
+ 803bba0:	e13ff917 	ldw	r4,-28(fp)
+ 803bba4:	80287480 	call	8028748 <pk_free>
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bba8:	01000084 	movi	r4,2
+ 803bbac:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return ENP_NO_ROUTE;
+ 803bbb0:	00bff7c4 	movi	r2,-33
+ 803bbb4:	0000cf06 	br	803bef4 <ip_rcv_phase2+0x538>
+         NET outnet;
+#ifdef IP_FRAGMENTS
+         int err;
+#endif
+
+         ip_mib.ipForwDatagrams++;  /* Count MIB-2 route attempts here */
+ 803bbb8:	008201b4 	movhi	r2,2054
+ 803bbbc:	10b95417 	ldw	r2,-6832(r2)
+ 803bbc0:	10c00044 	addi	r3,r2,1
+ 803bbc4:	008201b4 	movhi	r2,2054
+ 803bbc8:	10f95415 	stw	r3,-6832(r2)
+         if (pip->ip_time <= 1)     /* Time to Live (hopcount) expired? */
+ 803bbcc:	e0bfff17 	ldw	r2,-4(fp)
+ 803bbd0:	10800203 	ldbu	r2,8(r2)
+ 803bbd4:	10803fcc 	andi	r2,r2,255
+ 803bbd8:	108000a8 	cmpgeui	r2,r2,2
+ 803bbdc:	10001a1e 	bne	r2,zero,803bc48 <ip_rcv_phase2+0x28c>
+         {
+            ip_mib.ipOutDiscards++; /* Is this the right counter for these? */
+ 803bbe0:	008201b4 	movhi	r2,2054
+ 803bbe4:	10b95917 	ldw	r2,-6812(r2)
+ 803bbe8:	10c00044 	addi	r3,r2,1
+ 803bbec:	008201b4 	movhi	r2,2054
+ 803bbf0:	10f95915 	stw	r3,-6812(r2)
+#ifdef FULL_ICMP
+            icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, (TIMEX <<8), p->net);
+ 803bbf4:	e0bfff17 	ldw	r2,-4(fp)
+ 803bbf8:	10c00317 	ldw	r3,12(r2)
+ 803bbfc:	e0bff917 	ldw	r2,-28(fp)
+ 803bc00:	10800617 	ldw	r2,24(r2)
+ 803bc04:	11000a17 	ldw	r4,40(r2)
+ 803bc08:	e0bff917 	ldw	r2,-28(fp)
+ 803bc0c:	10800617 	ldw	r2,24(r2)
+ 803bc10:	d8800015 	stw	r2,0(sp)
+ 803bc14:	01c2c004 	movi	r7,2816
+ 803bc18:	e1bfff17 	ldw	r6,-4(fp)
+ 803bc1c:	200b883a 	mov	r5,r4
+ 803bc20:	1809883a 	mov	r4,r3
+ 803bc24:	8039a540 	call	8039a54 <icmp_destun>
+#endif   /* FULL_ICMP */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bc28:	01000084 	movi	r4,2
+ 803bc2c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(p);
+ 803bc30:	e13ff917 	ldw	r4,-28(fp)
+ 803bc34:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bc38:	01000084 	movi	r4,2
+ 803bc3c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NO_ROUTE;
+ 803bc40:	00bff7c4 	movi	r2,-33
+ 803bc44:	0000ab06 	br	803bef4 <ip_rcv_phase2+0x538>
+         }
+
+         p->fhost = pip->ip_dest;   /* set packet's target IP in net endian */
+ 803bc48:	e0bfff17 	ldw	r2,-4(fp)
+ 803bc4c:	10c00417 	ldw	r3,16(r2)
+ 803bc50:	e0bff917 	ldw	r2,-28(fp)
+ 803bc54:	10c00715 	stw	r3,28(r2)
+         if ((outnet = iproute(p->fhost, &firsthop)) == NULL)  /* find route */
+ 803bc58:	e0bff917 	ldw	r2,-28(fp)
+ 803bc5c:	10800717 	ldw	r2,28(r2)
+ 803bc60:	e0fffa04 	addi	r3,fp,-24
+ 803bc64:	180b883a 	mov	r5,r3
+ 803bc68:	1009883a 	mov	r4,r2
+ 803bc6c:	803b3700 	call	803b370 <iproute>
+ 803bc70:	e0bffc15 	stw	r2,-16(fp)
+ 803bc74:	e0bffc17 	ldw	r2,-16(fp)
+ 803bc78:	10000d1e 	bne	r2,zero,803bcb0 <ip_rcv_phase2+0x2f4>
+         {
+            ip_mib.ipOutNoRoutes++; /* count unroutable pkts */
+ 803bc7c:	008201b4 	movhi	r2,2054
+ 803bc80:	10b95a17 	ldw	r2,-6808(r2)
+ 803bc84:	10c00044 	addi	r3,r2,1
+ 803bc88:	008201b4 	movhi	r2,2054
+ 803bc8c:	10f95a15 	stw	r3,-6808(r2)
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bc90:	01000084 	movi	r4,2
+ 803bc94:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(p);
+ 803bc98:	e13ff917 	ldw	r4,-28(fp)
+ 803bc9c:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bca0:	01000084 	movi	r4,2
+ 803bca4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NO_ROUTE;
+ 803bca8:	00bff7c4 	movi	r2,-33
+ 803bcac:	00009106 	br	803bef4 <ip_rcv_phase2+0x538>
+         /* Check to see if the packet was is addressed to one of our IP
+          * addresses other than the interface it was received on. If so,
+          * routing should have returned that interface and we can trap this
+          * situation by checking the interfaces IP address.
+          */
+         if(pip->ip_dest == outnet->n_ipaddr)
+ 803bcb0:	e0bfff17 	ldw	r2,-4(fp)
+ 803bcb4:	10c00417 	ldw	r3,16(r2)
+ 803bcb8:	e0bffc17 	ldw	r2,-16(fp)
+ 803bcbc:	10800a17 	ldw	r2,40(r2)
+ 803bcc0:	18804526 	beq	r3,r2,803bdd8 <ip_rcv_phase2+0x41c>
+            goto ours;
+
+         /* Make sure the packet is not a subnet broadcast for either the
+          * source or destination network.
+          */
+         if((pip->ip_dest == outnet->n_netbr) ||
+ 803bcc4:	e0bfff17 	ldw	r2,-4(fp)
+ 803bcc8:	10c00417 	ldw	r3,16(r2)
+ 803bccc:	e0bffc17 	ldw	r2,-16(fp)
+ 803bcd0:	10800e17 	ldw	r2,56(r2)
+ 803bcd4:	18804226 	beq	r3,r2,803bde0 <ip_rcv_phase2+0x424>
+            (pip->ip_dest == p->net->n_netbr))
+ 803bcd8:	e0bfff17 	ldw	r2,-4(fp)
+ 803bcdc:	10c00417 	ldw	r3,16(r2)
+ 803bce0:	e0bff917 	ldw	r2,-28(fp)
+ 803bce4:	10800617 	ldw	r2,24(r2)
+ 803bce8:	10800e17 	ldw	r2,56(r2)
+         if((pip->ip_dest == outnet->n_netbr) ||
+ 803bcec:	18803c26 	beq	r3,r2,803bde0 <ip_rcv_phase2+0x424>
+         {
+            goto ours;            
+         }
+
+         /* Routed OK, prepare to send */
+         p->net = outnet;           /* set iface to send on */
+ 803bcf0:	e0bff917 	ldw	r2,-28(fp)
+ 803bcf4:	e0fffc17 	ldw	r3,-16(fp)
+ 803bcf8:	10c00615 	stw	r3,24(r2)
+            }
+         }
+#endif   /* IPSEC */
+
+         /* see if packet is too big for media of dest net */
+         if ((p->nb_plen + p->net->n_lnh) > (unsigned)outnet->n_mtu)
+ 803bcfc:	e0bff917 	ldw	r2,-28(fp)
+ 803bd00:	10800417 	ldw	r2,16(r2)
+ 803bd04:	e0fff917 	ldw	r3,-28(fp)
+ 803bd08:	18c00617 	ldw	r3,24(r3)
+ 803bd0c:	18c00817 	ldw	r3,32(r3)
+ 803bd10:	10c5883a 	add	r2,r2,r3
+ 803bd14:	e0fffc17 	ldw	r3,-16(fp)
+ 803bd18:	18c00917 	ldw	r3,36(r3)
+ 803bd1c:	1880162e 	bgeu	r3,r2,803bd78 <ip_rcv_phase2+0x3bc>
+            pip->ip_time--;            /* datagram's hop count */
+            err = ip_fragment(p, firsthop);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return(err);
+#else /* IP fragments not supported? Bad news....*/
+            dtrap(); /* this should be caught by programmers during development */
+ 803bd20:	8028cd40 	call	8028cd4 <dtrap>
+#ifdef FULL_ICMP
+            icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTFRAG, p->net);
+ 803bd24:	e0bfff17 	ldw	r2,-4(fp)
+ 803bd28:	10c00317 	ldw	r3,12(r2)
+ 803bd2c:	e0bff917 	ldw	r2,-28(fp)
+ 803bd30:	10800617 	ldw	r2,24(r2)
+ 803bd34:	11000a17 	ldw	r4,40(r2)
+ 803bd38:	e0bff917 	ldw	r2,-28(fp)
+ 803bd3c:	10800617 	ldw	r2,24(r2)
+ 803bd40:	d8800015 	stw	r2,0(sp)
+ 803bd44:	01c00104 	movi	r7,4
+ 803bd48:	e1bfff17 	ldw	r6,-4(fp)
+ 803bd4c:	200b883a 	mov	r5,r4
+ 803bd50:	1809883a 	mov	r4,r3
+ 803bd54:	8039a540 	call	8039a54 <icmp_destun>
+#endif   /* FULL_ICMP */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bd58:	01000084 	movi	r4,2
+ 803bd5c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+            pk_free(p);
+ 803bd60:	e13ff917 	ldw	r4,-28(fp)
+ 803bd64:	80287480 	call	8028748 <pk_free>
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bd68:	01000084 	movi	r4,2
+ 803bd6c:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+            return ENP_LOGIC;
+ 803bd70:	00bffd44 	movi	r2,-11
+ 803bd74:	00005f06 	br	803bef4 <ip_rcv_phase2+0x538>
+#endif   /* IP_FRAGMENTS */
+         }
+         pip->ip_time--;            /* datagram's hop count */
+ 803bd78:	e0bfff17 	ldw	r2,-4(fp)
+ 803bd7c:	10800203 	ldbu	r2,8(r2)
+ 803bd80:	10bfffc4 	addi	r2,r2,-1
+ 803bd84:	1007883a 	mov	r3,r2
+ 803bd88:	e0bfff17 	ldw	r2,-4(fp)
+ 803bd8c:	10c00205 	stb	r3,8(r2)
+         pip->ip_chksum = IPXSUM;   /* clear checksum field for summing */
+ 803bd90:	e0bfff17 	ldw	r2,-4(fp)
+ 803bd94:	1000028d 	sth	zero,10(r2)
+         pip->ip_chksum = ~cksum(pip, 10);   /* new xsum */
+ 803bd98:	01400284 	movi	r5,10
+ 803bd9c:	e13fff17 	ldw	r4,-4(fp)
+ 803bda0:	8026d7c0 	call	8026d7c <cksum>
+ 803bda4:	0084303a 	nor	r2,zero,r2
+ 803bda8:	1007883a 	mov	r3,r2
+ 803bdac:	e0bfff17 	ldw	r2,-4(fp)
+ 803bdb0:	10c0028d 	sth	r3,10(r2)
+         IN_PROFILER(PF_IP, PF_EXIT);
+#ifdef RF_SIMULATION
+         if(rfsim_routing)
+            return(rfsim_send(p, firsthop));
+#endif   /* RF_SIMULATION */
+         return(ip2mac(p, firsthop));
+ 803bdb4:	e0bffa17 	ldw	r2,-24(fp)
+ 803bdb8:	100b883a 	mov	r5,r2
+ 803bdbc:	e13ff917 	ldw	r4,-28(fp)
+ 803bdc0:	8024df40 	call	8024df4 <ip2mac>
+ 803bdc4:	00004b06 	br	803bef4 <ip_rcv_phase2+0x538>
+         goto ours;
+ 803bdc8:	0001883a 	nop
+ 803bdcc:	00000506 	br	803bde4 <ip_rcv_phase2+0x428>
+      return(ENP_NOT_MINE);
+#endif
+   }
+
+#if defined (IP_MULTICAST) || defined (IP_ROUTING)
+ours:
+ 803bdd0:	0001883a 	nop
+ 803bdd4:	00000306 	br	803bde4 <ip_rcv_phase2+0x428>
+            goto ours;
+ 803bdd8:	0001883a 	nop
+ 803bddc:	00000106 	br	803bde4 <ip_rcv_phase2+0x428>
+            goto ours;            
+ 803bde0:	0001883a 	nop
+#endif
+
+   /* Test for fragment: */
+   tempsum = htons(pip->ip_flgs_foff); /* borrow cksum variable */
+ 803bde4:	e0bfff17 	ldw	r2,-4(fp)
+ 803bde8:	1080018b 	ldhu	r2,6(r2)
+ 803bdec:	10bfffcc 	andi	r2,r2,65535
+ 803bdf0:	1004d23a 	srli	r2,r2,8
+ 803bdf4:	1007883a 	mov	r3,r2
+ 803bdf8:	e0bfff17 	ldw	r2,-4(fp)
+ 803bdfc:	1080018b 	ldhu	r2,6(r2)
+ 803be00:	10bfffcc 	andi	r2,r2,65535
+ 803be04:	1004923a 	slli	r2,r2,8
+ 803be08:	1884b03a 	or	r2,r3,r2
+ 803be0c:	e0bffb8d 	sth	r2,-18(fp)
+   if ((tempsum & IP_FLG_MF) ||  /* IP flag for "More Fragments" set? */
+ 803be10:	e0bffb8b 	ldhu	r2,-18(fp)
+ 803be14:	1088000c 	andi	r2,r2,8192
+ 803be18:	1000051e 	bne	r2,zero,803be30 <ip_rcv_phase2+0x474>
+       (tempsum & ~IP_FLG_MASK))  /* or offset to last frag? */
+ 803be1c:	e0fffb8b 	ldhu	r3,-18(fp)
+ 803be20:	00bffff4 	movhi	r2,65535
+ 803be24:	1087ffc4 	addi	r2,r2,8191
+ 803be28:	1884703a 	and	r2,r3,r2
+   if ((tempsum & IP_FLG_MF) ||  /* IP flag for "More Fragments" set? */
+ 803be2c:	10002f26 	beq	r2,zero,803beec <ip_rcv_phase2+0x530>
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803be30:	d0a06617 	ldw	r2,-32360(gp)
+ 803be34:	1081000c 	andi	r2,r2,1024
+ 803be38:	10001a26 	beq	r2,zero,803bea4 <ip_rcv_phase2+0x4e8>
+ 803be3c:	d0a06617 	ldw	r2,-32360(gp)
+ 803be40:	1080800c 	andi	r2,r2,512
+ 803be44:	10001726 	beq	r2,zero,803bea4 <ip_rcv_phase2+0x4e8>
+      {
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+          PUSH_IPADDR(pip->ip_src));
+ 803be48:	e0bfff17 	ldw	r2,-4(fp)
+ 803be4c:	10800317 	ldw	r2,12(r2)
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+ 803be50:	10c03fcc 	andi	r3,r2,255
+          PUSH_IPADDR(pip->ip_src));
+ 803be54:	e0bfff17 	ldw	r2,-4(fp)
+ 803be58:	10800317 	ldw	r2,12(r2)
+ 803be5c:	1004d23a 	srli	r2,r2,8
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+ 803be60:	11003fcc 	andi	r4,r2,255
+          PUSH_IPADDR(pip->ip_src));
+ 803be64:	e0bfff17 	ldw	r2,-4(fp)
+ 803be68:	10800317 	ldw	r2,12(r2)
+ 803be6c:	1004d43a 	srli	r2,r2,16
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+ 803be70:	11403fcc 	andi	r5,r2,255
+          PUSH_IPADDR(pip->ip_src));
+ 803be74:	e0bfff17 	ldw	r2,-4(fp)
+ 803be78:	10800317 	ldw	r2,12(r2)
+ 803be7c:	1004d63a 	srli	r2,r2,24
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+ 803be80:	d8800015 	stw	r2,0(sp)
+ 803be84:	280f883a 	mov	r7,r5
+ 803be88:	200d883a 	mov	r6,r4
+ 803be8c:	180b883a 	mov	r5,r3
+ 803be90:	01020174 	movhi	r4,2053
+ 803be94:	212cae04 	addi	r4,r4,-19784
+ 803be98:	8002c780 	call	8002c78 <printf>
+         ip_dump(p);
+ 803be9c:	e13ff917 	ldw	r4,-28(fp)
+ 803bea0:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif
+      ip_mib.ipReasmReqds++;     /* got a reassemble request; ie a frag */
+ 803bea4:	008201b4 	movhi	r2,2054
+ 803bea8:	10b95c17 	ldw	r2,-6800(r2)
+ 803beac:	10c00044 	addi	r3,r2,1
+ 803beb0:	008201b4 	movhi	r2,2054
+ 803beb4:	10f95c15 	stw	r3,-6800(r2)
+#ifdef IP_FRAGMENTS
+      return(ip_reassm(p));
+#else
+      ip_mib.ipReasmFails++;     /* we don't do these */
+ 803beb8:	008201b4 	movhi	r2,2054
+ 803bebc:	10b95e17 	ldw	r2,-6792(r2)
+ 803bec0:	10c00044 	addi	r3,r2,1
+ 803bec4:	008201b4 	movhi	r2,2054
+ 803bec8:	10f95e15 	stw	r3,-6792(r2)
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803becc:	01000084 	movi	r4,2
+ 803bed0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      pk_free(p);
+ 803bed4:	e13ff917 	ldw	r4,-28(fp)
+ 803bed8:	80287480 	call	8028748 <pk_free>
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803bedc:	01000084 	movi	r4,2
+ 803bee0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_NOT_MINE;    /* perhaps should be ENP_BAD_HEADER? */
+ 803bee4:	00800084 	movi	r2,2
+ 803bee8:	00000206 	br	803bef4 <ip_rcv_phase2+0x538>
+   {
+      return ENP_LOGIC;
+   }
+#endif /* IPSEC */
+
+   return(ip_demux(p));    /* demux to correct to upper layer */
+ 803beec:	e13ff917 	ldw	r4,-28(fp)
+ 803bef0:	803bf080 	call	803bf08 <ip_demux>
+}
+ 803bef4:	e037883a 	mov	sp,fp
+ 803bef8:	dfc00117 	ldw	ra,4(sp)
+ 803befc:	df000017 	ldw	fp,0(sp)
+ 803bf00:	dec00204 	addi	sp,sp,8
+ 803bf04:	f800283a 	ret
+
+0803bf08 <ip_demux>:
+ * RETURNS: Same return values as ip_rcv(). 
+ */
+
+int
+ip_demux(PACKET p)
+{
+ 803bf08:	defff904 	addi	sp,sp,-28
+ 803bf0c:	dfc00615 	stw	ra,24(sp)
+ 803bf10:	df000515 	stw	fp,20(sp)
+ 803bf14:	df000504 	addi	fp,sp,20
+ 803bf18:	e13ffd15 	stw	r4,-12(fp)
+   int   err;
+
+   /* The packet is verified; the header is correct. Now we have
+    * to demultiplex it among our internet connections.
+    */
+   pip = (struct ip *)(p->nb_prot);
+ 803bf1c:	e0bffd17 	ldw	r2,-12(fp)
+ 803bf20:	10800317 	ldw	r2,12(r2)
+ 803bf24:	e0bffe15 	stw	r2,-8(fp)
+
+#ifdef NPDEBUG
+   /* make sure the caller set p->nb_prot */
+   if(pip->ip_ver_ihl != 0x45)
+ 803bf28:	e0bffe17 	ldw	r2,-8(fp)
+ 803bf2c:	10800003 	ldbu	r2,0(r2)
+ 803bf30:	10803fcc 	andi	r2,r2,255
+ 803bf34:	10801160 	cmpeqi	r2,r2,69
+ 803bf38:	1000131e 	bne	r2,zero,803bf88 <ip_demux+0x80>
+   {
+      if((pip->ip_ver_ihl < 0x45) ||
+ 803bf3c:	e0bffe17 	ldw	r2,-8(fp)
+ 803bf40:	10800003 	ldbu	r2,0(r2)
+ 803bf44:	10803fcc 	andi	r2,r2,255
+ 803bf48:	10801170 	cmpltui	r2,r2,69
+ 803bf4c:	1000051e 	bne	r2,zero,803bf64 <ip_demux+0x5c>
+         (pip->ip_ver_ihl > 0x47))
+ 803bf50:	e0bffe17 	ldw	r2,-8(fp)
+ 803bf54:	10800003 	ldbu	r2,0(r2)
+      if((pip->ip_ver_ihl < 0x45) ||
+ 803bf58:	10803fcc 	andi	r2,r2,255
+ 803bf5c:	10801230 	cmpltui	r2,r2,72
+ 803bf60:	1000091e 	bne	r2,zero,803bf88 <ip_demux+0x80>
+      {
+         dprintf("ip_demux: bad IP type 0x%x\n", pip->ip_ver_ihl);
+ 803bf64:	e0bffe17 	ldw	r2,-8(fp)
+ 803bf68:	10800003 	ldbu	r2,0(r2)
+ 803bf6c:	10803fcc 	andi	r2,r2,255
+ 803bf70:	100b883a 	mov	r5,r2
+ 803bf74:	01020174 	movhi	r4,2053
+ 803bf78:	212cb704 	addi	r4,r4,-19748
+ 803bf7c:	8002c780 	call	8002c78 <printf>
+         return ENP_LOGIC;
+ 803bf80:	00bffd44 	movi	r2,-11
+ 803bf84:	0000c406 	br	803c298 <ip_demux+0x390>
+
+   /* for profiling purposes count the upper layers (UDP, ICMP) in the IP
+    * profile bucket. TCP will insert it's own nested profile calls 
+    */
+   IN_PROFILER(PF_IP, PF_ENTRY);
+   p->fhost = pip->ip_src;
+ 803bf88:	e0bffe17 	ldw	r2,-8(fp)
+ 803bf8c:	10c00317 	ldw	r3,12(r2)
+ 803bf90:	e0bffd17 	ldw	r2,-12(fp)
+ 803bf94:	10c00715 	stw	r3,28(r2)
+
+#ifdef NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803bf98:	d0a06617 	ldw	r2,-32360(gp)
+ 803bf9c:	1081000c 	andi	r2,r2,1024
+ 803bfa0:	10002126 	beq	r2,zero,803c028 <ip_demux+0x120>
+ 803bfa4:	d0a06617 	ldw	r2,-32360(gp)
+ 803bfa8:	1080800c 	andi	r2,r2,512
+ 803bfac:	10001e26 	beq	r2,zero,803c028 <ip_demux+0x120>
+   {
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+ 803bfb0:	e0bffe17 	ldw	r2,-8(fp)
+ 803bfb4:	10800243 	ldbu	r2,9(r2)
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+ 803bfb8:	11003fcc 	andi	r4,r2,255
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+ 803bfbc:	e0bffe17 	ldw	r2,-8(fp)
+ 803bfc0:	10800317 	ldw	r2,12(r2)
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+ 803bfc4:	11403fcc 	andi	r5,r2,255
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+ 803bfc8:	e0bffe17 	ldw	r2,-8(fp)
+ 803bfcc:	10800317 	ldw	r2,12(r2)
+ 803bfd0:	1004d23a 	srli	r2,r2,8
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+ 803bfd4:	11803fcc 	andi	r6,r2,255
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+ 803bfd8:	e0bffe17 	ldw	r2,-8(fp)
+ 803bfdc:	10800317 	ldw	r2,12(r2)
+ 803bfe0:	1004d43a 	srli	r2,r2,16
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+ 803bfe4:	10803fcc 	andi	r2,r2,255
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+ 803bfe8:	e0fffe17 	ldw	r3,-8(fp)
+ 803bfec:	18c00317 	ldw	r3,12(r3)
+ 803bff0:	1806d63a 	srli	r3,r3,24
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+ 803bff4:	d8c00115 	stw	r3,4(sp)
+ 803bff8:	d8800015 	stw	r2,0(sp)
+ 803bffc:	300f883a 	mov	r7,r6
+ 803c000:	280d883a 	mov	r6,r5
+ 803c004:	200b883a 	mov	r5,r4
+ 803c008:	01020174 	movhi	r4,2053
+ 803c00c:	212cbe04 	addi	r4,r4,-19720
+ 803c010:	8002c780 	call	8002c78 <printf>
+      if (NDEBUG & DUMP) ip_dump(p);
+ 803c014:	d0a06617 	ldw	r2,-32360(gp)
+ 803c018:	1080008c 	andi	r2,r2,2
+ 803c01c:	10000226 	beq	r2,zero,803c028 <ip_demux+0x120>
+ 803c020:	e13ffd17 	ldw	r4,-12(fp)
+ 803c024:	803b0cc0 	call	803b0cc <ip_dump>
+   }
+#endif
+
+   switch (pip->ip_prot)
+ 803c028:	e0bffe17 	ldw	r2,-8(fp)
+ 803c02c:	10800243 	ldbu	r2,9(r2)
+ 803c030:	10803fcc 	andi	r2,r2,255
+ 803c034:	10c000a0 	cmpeqi	r3,r2,2
+ 803c038:	18001b1e 	bne	r3,zero,803c0a8 <ip_demux+0x1a0>
+ 803c03c:	10c000c8 	cmpgei	r3,r2,3
+ 803c040:	1800031e 	bne	r3,zero,803c050 <ip_demux+0x148>
+ 803c044:	10800060 	cmpeqi	r2,r2,1
+ 803c048:	10000e1e 	bne	r2,zero,803c084 <ip_demux+0x17c>
+ 803c04c:	00002806 	br	803c0f0 <ip_demux+0x1e8>
+ 803c050:	10c001a0 	cmpeqi	r3,r2,6
+ 803c054:	18001d1e 	bne	r3,zero,803c0cc <ip_demux+0x1c4>
+ 803c058:	10800458 	cmpnei	r2,r2,17
+ 803c05c:	1000241e 	bne	r2,zero,803c0f0 <ip_demux+0x1e8>
+   {
+   case UDP_PROT:
+      ip_mib.ipInDelivers++;
+ 803c060:	008201b4 	movhi	r2,2054
+ 803c064:	10b95717 	ldw	r2,-6820(r2)
+ 803c068:	10c00044 	addi	r3,r2,1
+ 803c06c:	008201b4 	movhi	r2,2054
+ 803c070:	10f95715 	stw	r3,-6820(r2)
+      err = udpdemux(p);
+ 803c074:	e13ffd17 	ldw	r4,-12(fp)
+ 803c078:	803d1340 	call	803d134 <udpdemux>
+ 803c07c:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 803c080:	00002406 	br	803c114 <ip_demux+0x20c>
+   case ICMP_PROT:
+      ip_mib.ipInDelivers++;
+ 803c084:	008201b4 	movhi	r2,2054
+ 803c088:	10b95717 	ldw	r2,-6820(r2)
+ 803c08c:	10c00044 	addi	r3,r2,1
+ 803c090:	008201b4 	movhi	r2,2054
+ 803c094:	10f95715 	stw	r3,-6820(r2)
+      err = icmprcv(p);
+ 803c098:	e13ffd17 	ldw	r4,-12(fp)
+ 803c09c:	8038f780 	call	8038f78 <icmprcv>
+ 803c0a0:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 803c0a4:	00001b06 	br	803c114 <ip_demux+0x20c>
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   case IGMP_PROT:
+      ip_mib.ipInDelivers++;
+ 803c0a8:	008201b4 	movhi	r2,2054
+ 803c0ac:	10b95717 	ldw	r2,-6820(r2)
+ 803c0b0:	10c00044 	addi	r3,r2,1
+ 803c0b4:	008201b4 	movhi	r2,2054
+ 803c0b8:	10f95715 	stw	r3,-6820(r2)
+      err = igmp_input(p);
+ 803c0bc:	e13ffd17 	ldw	r4,-12(fp)
+ 803c0c0:	802541c0 	call	802541c <igmp_input>
+ 803c0c4:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 803c0c8:	00001206 	br	803c114 <ip_demux+0x20c>
+#endif   /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+#ifdef INCLUDE_TCP
+   case TCP_PROT:
+      ip_mib.ipInDelivers++;
+ 803c0cc:	008201b4 	movhi	r2,2054
+ 803c0d0:	10b95717 	ldw	r2,-6820(r2)
+ 803c0d4:	10c00044 	addi	r3,r2,1
+ 803c0d8:	008201b4 	movhi	r2,2054
+ 803c0dc:	10f95715 	stw	r3,-6820(r2)
+      err = tcp_rcv(p);
+ 803c0e0:	e13ffd17 	ldw	r4,-12(fp)
+ 803c0e4:	802a4a40 	call	802a4a4 <tcp_rcv>
+ 803c0e8:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 803c0ec:	00000906 	br	803c114 <ip_demux+0x20c>
+      err = v6t_rcv(p);
+      break;
+#endif /* IPV6_TUNNEL */
+   default: /* unknown upper protocol */
+#ifdef IP_RAW
+      ip_mib.ipInDelivers++;
+ 803c0f0:	008201b4 	movhi	r2,2054
+ 803c0f4:	10b95717 	ldw	r2,-6820(r2)
+ 803c0f8:	10c00044 	addi	r3,r2,1
+ 803c0fc:	008201b4 	movhi	r2,2054
+ 803c100:	10f95715 	stw	r3,-6820(r2)
+      err = ip_raw_input(p);
+ 803c104:	e13ffd17 	ldw	r4,-12(fp)
+ 803c108:	803c7d00 	call	803c7d0 <ip_raw_input>
+ 803c10c:	e0bfff15 	stw	r2,-4(fp)
+      break;
+ 803c110:	0001883a 	nop
+#endif /* IP_RAW */
+   }
+
+   IN_PROFILER(PF_IP, PF_EXIT);
+
+   if(err != ENP_PARAM)
+ 803c114:	e0bfff17 	ldw	r2,-4(fp)
+ 803c118:	10bffda0 	cmpeqi	r2,r2,-10
+ 803c11c:	1000021e 	bne	r2,zero,803c128 <ip_demux+0x220>
+   {
+      return err;
+ 803c120:	e0bfff17 	ldw	r2,-4(fp)
+ 803c124:	00005c06 	br	803c298 <ip_demux+0x390>
+
+#ifdef FULL_ICMP
+   /* nobody's listening for this packet. Unless it was broadcast or 
+    * multicast, send a destination unreachable. 
+    */
+   if ((pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+ 803c128:	e0bffe17 	ldw	r2,-8(fp)
+ 803c12c:	10800417 	ldw	r2,16(r2)
+ 803c130:	10bfffe0 	cmpeqi	r2,r2,-1
+ 803c134:	10004c1e 	bne	r2,zero,803c268 <ip_demux+0x360>
+#ifdef IP_MULTICAST
+       (!(IN_MULTICAST(ntohl(pip->ip_dest)))) && /* multicast address */
+ 803c138:	e0bffe17 	ldw	r2,-8(fp)
+ 803c13c:	10800417 	ldw	r2,16(r2)
+ 803c140:	1006d63a 	srli	r3,r2,24
+ 803c144:	e0bffe17 	ldw	r2,-8(fp)
+ 803c148:	10800417 	ldw	r2,16(r2)
+ 803c14c:	1004d23a 	srli	r2,r2,8
+ 803c150:	10bfc00c 	andi	r2,r2,65280
+ 803c154:	1886b03a 	or	r3,r3,r2
+ 803c158:	e0bffe17 	ldw	r2,-8(fp)
+ 803c15c:	10800417 	ldw	r2,16(r2)
+ 803c160:	1004923a 	slli	r2,r2,8
+ 803c164:	10803fec 	andhi	r2,r2,255
+ 803c168:	1886b03a 	or	r3,r3,r2
+ 803c16c:	e0bffe17 	ldw	r2,-8(fp)
+ 803c170:	10800417 	ldw	r2,16(r2)
+ 803c174:	1004963a 	slli	r2,r2,24
+ 803c178:	1884b03a 	or	r2,r3,r2
+ 803c17c:	10fc002c 	andhi	r3,r2,61440
+   if ((pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+ 803c180:	00b80034 	movhi	r2,57344
+ 803c184:	18803826 	beq	r3,r2,803c268 <ip_demux+0x360>
+#endif /* IP_MULTICAST */
+       (pip->ip_dest != p->net->n_netbr) &&   /* All subnet broadcast */
+ 803c188:	e0bffe17 	ldw	r2,-8(fp)
+ 803c18c:	10c00417 	ldw	r3,16(r2)
+ 803c190:	e0bffd17 	ldw	r2,-12(fp)
+ 803c194:	10800617 	ldw	r2,24(r2)
+ 803c198:	10800e17 	ldw	r2,56(r2)
+       (!(IN_MULTICAST(ntohl(pip->ip_dest)))) && /* multicast address */
+ 803c19c:	18803226 	beq	r3,r2,803c268 <ip_demux+0x360>
+       (pip->ip_dest != p->net->n_netbr42) && /* All subnet bcast (4.2bsd) */
+ 803c1a0:	e0bffe17 	ldw	r2,-8(fp)
+ 803c1a4:	10c00417 	ldw	r3,16(r2)
+ 803c1a8:	e0bffd17 	ldw	r2,-12(fp)
+ 803c1ac:	10800617 	ldw	r2,24(r2)
+ 803c1b0:	10800f17 	ldw	r2,60(r2)
+       (pip->ip_dest != p->net->n_netbr) &&   /* All subnet broadcast */
+ 803c1b4:	18802c26 	beq	r3,r2,803c268 <ip_demux+0x360>
+       (pip->ip_dest != p->net->n_subnetbr) &&   /* Our subnet broadcast */
+ 803c1b8:	e0bffe17 	ldw	r2,-8(fp)
+ 803c1bc:	10c00417 	ldw	r3,16(r2)
+ 803c1c0:	e0bffd17 	ldw	r2,-12(fp)
+ 803c1c4:	10800617 	ldw	r2,24(r2)
+ 803c1c8:	10801017 	ldw	r2,64(r2)
+       (pip->ip_dest != p->net->n_netbr42) && /* All subnet bcast (4.2bsd) */
+ 803c1cc:	18802626 	beq	r3,r2,803c268 <ip_demux+0x360>
+       (p->net->n_ipaddr ^ p->net->n_subnetbr))  /* Know our own host address? */
+ 803c1d0:	e0bffd17 	ldw	r2,-12(fp)
+ 803c1d4:	10800617 	ldw	r2,24(r2)
+ 803c1d8:	10c00a17 	ldw	r3,40(r2)
+ 803c1dc:	e0bffd17 	ldw	r2,-12(fp)
+ 803c1e0:	10800617 	ldw	r2,24(r2)
+ 803c1e4:	10801017 	ldw	r2,64(r2)
+       (pip->ip_dest != p->net->n_subnetbr) &&   /* Our subnet broadcast */
+ 803c1e8:	18801f26 	beq	r3,r2,803c268 <ip_demux+0x360>
+   {
+
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+ 803c1ec:	d0a06617 	ldw	r2,-32360(gp)
+ 803c1f0:	1081000c 	andi	r2,r2,1024
+ 803c1f4:	10000f26 	beq	r2,zero,803c234 <ip_demux+0x32c>
+ 803c1f8:	d0a06617 	ldw	r2,-32360(gp)
+ 803c1fc:	1080800c 	andi	r2,r2,512
+ 803c200:	10000c26 	beq	r2,zero,803c234 <ip_demux+0x32c>
+      {
+         dprintf("ip_demux: unhandled prot %u\n", pip->ip_prot);
+ 803c204:	e0bffe17 	ldw	r2,-8(fp)
+ 803c208:	10800243 	ldbu	r2,9(r2)
+ 803c20c:	10803fcc 	andi	r2,r2,255
+ 803c210:	100b883a 	mov	r5,r2
+ 803c214:	01020174 	movhi	r4,2053
+ 803c218:	212cc804 	addi	r4,r4,-19680
+ 803c21c:	8002c780 	call	8002c78 <printf>
+         if (NDEBUG & DUMP) ip_dump(p);
+ 803c220:	d0a06617 	ldw	r2,-32360(gp)
+ 803c224:	1080008c 	andi	r2,r2,2
+ 803c228:	10000226 	beq	r2,zero,803c234 <ip_demux+0x32c>
+ 803c22c:	e13ffd17 	ldw	r4,-12(fp)
+ 803c230:	803b0cc0 	call	803b0cc <ip_dump>
+      }
+#endif   /* NPDEBUG */
+      icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTPROT, p->net);
+ 803c234:	e0bffe17 	ldw	r2,-8(fp)
+ 803c238:	10c00317 	ldw	r3,12(r2)
+ 803c23c:	e0bffd17 	ldw	r2,-12(fp)
+ 803c240:	10800617 	ldw	r2,24(r2)
+ 803c244:	11000a17 	ldw	r4,40(r2)
+ 803c248:	e0bffd17 	ldw	r2,-12(fp)
+ 803c24c:	10800617 	ldw	r2,24(r2)
+ 803c250:	d8800015 	stw	r2,0(sp)
+ 803c254:	01c00084 	movi	r7,2
+ 803c258:	e1bffe17 	ldw	r6,-8(fp)
+ 803c25c:	200b883a 	mov	r5,r4
+ 803c260:	1809883a 	mov	r4,r3
+ 803c264:	8039a540 	call	8039a54 <icmp_destun>
+   }
+#endif   /* FULL_ICMP */
+
+   ip_mib.ipUnknownProtos++;
+ 803c268:	008201b4 	movhi	r2,2054
+ 803c26c:	10b95517 	ldw	r2,-6828(r2)
+ 803c270:	10c00044 	addi	r3,r2,1
+ 803c274:	008201b4 	movhi	r2,2054
+ 803c278:	10f95515 	stw	r3,-6828(r2)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803c27c:	01000084 	movi	r4,2
+ 803c280:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 803c284:	e13ffd17 	ldw	r4,-12(fp)
+ 803c288:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803c28c:	01000084 	movi	r4,2
+ 803c290:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return ENP_NOT_MINE;
+ 803c294:	00800084 	movi	r2,2
+}
+ 803c298:	e037883a 	mov	sp,fp
+ 803c29c:	dfc00117 	ldw	ra,4(sp)
+ 803c2a0:	df000017 	ldw	fp,0(sp)
+ 803c2a4:	dec00204 	addi	sp,sp,8
+ 803c2a8:	f800283a 	ret
+
+0803c2ac <in_addmulti>:
+ * RETURNS: 
+ */
+
+struct in_multi * 
+in_addmulti(ip_addr *ap, struct net *netp, int addrtype)
+{
+ 803c2ac:	defff904 	addi	sp,sp,-28
+ 803c2b0:	dfc00615 	stw	ra,24(sp)
+ 803c2b4:	df000515 	stw	fp,20(sp)
+ 803c2b8:	df000504 	addi	fp,sp,20
+ 803c2bc:	e13ffd15 	stw	r4,-12(fp)
+ 803c2c0:	e17ffc15 	stw	r5,-16(fp)
+ 803c2c4:	e1bffb15 	stw	r6,-20(fp)
+   struct in_multi *inm = (struct in_multi *)NULL;
+ 803c2c8:	e03fff15 	stw	zero,-4(fp)
+   int error;
+
+   /* check for good addr. */
+   if ((ap == (ip_addr *)NULL) || (*ap == 0))
+ 803c2cc:	e0bffd17 	ldw	r2,-12(fp)
+ 803c2d0:	10000326 	beq	r2,zero,803c2e0 <in_addmulti+0x34>
+ 803c2d4:	e0bffd17 	ldw	r2,-12(fp)
+ 803c2d8:	10800017 	ldw	r2,0(r2)
+ 803c2dc:	1000021e 	bne	r2,zero,803c2e8 <in_addmulti+0x3c>
+      return ((struct in_multi *)NULL);  
+ 803c2e0:	0005883a 	mov	r2,zero
+ 803c2e4:	00003f06 	br	803c3e4 <in_addmulti+0x138>
+
+   ENTER_CRIT_SECTION(netp);
+ 803c2e8:	8028e940 	call	8028e94 <irq_Mask>
+#ifdef IP_V6
+   if(addrtype == 6)
+      inm = v6_lookup_mcast((ip6_addr*)ap, netp);
+#endif
+#ifdef IP_V4
+   if(addrtype != 6)
+ 803c2ec:	e0bffb17 	ldw	r2,-20(fp)
+ 803c2f0:	108001a0 	cmpeqi	r2,r2,6
+ 803c2f4:	1000061e 	bne	r2,zero,803c310 <in_addmulti+0x64>
+      inm = lookup_mcast(*ap, netp);
+ 803c2f8:	e0bffd17 	ldw	r2,-12(fp)
+ 803c2fc:	10800017 	ldw	r2,0(r2)
+ 803c300:	e17ffc17 	ldw	r5,-16(fp)
+ 803c304:	1009883a 	mov	r4,r2
+ 803c308:	803c5040 	call	803c504 <lookup_mcast>
+ 803c30c:	e0bfff15 	stw	r2,-4(fp)
+#endif
+
+   if (inm != (struct in_multi *)NULL) 
+ 803c310:	e0bfff17 	ldw	r2,-4(fp)
+ 803c314:	10000626 	beq	r2,zero,803c330 <in_addmulti+0x84>
+   {
+      /* Found it; just increment the reference count. */
+      ++inm->inm_refcount;
+ 803c318:	e0bfff17 	ldw	r2,-4(fp)
+ 803c31c:	10800217 	ldw	r2,8(r2)
+ 803c320:	10c00044 	addi	r3,r2,1
+ 803c324:	e0bfff17 	ldw	r2,-4(fp)
+ 803c328:	10c00215 	stw	r3,8(r2)
+ 803c32c:	00002b06 	br	803c3dc <in_addmulti+0x130>
+   {
+      /*
+       * New address; allocate a new multicast record
+       * and link it into the interface's multicast list.
+       */
+      inm = (struct in_multi *)INM_ALLOC(sizeof(*inm));
+ 803c330:	01000604 	movi	r4,24
+ 803c334:	802982c0 	call	802982c <npalloc>
+ 803c338:	e0bfff15 	stw	r2,-4(fp)
+
+      if (inm == (struct in_multi *)NULL) 
+ 803c33c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c340:	1000031e 	bne	r2,zero,803c350 <in_addmulti+0xa4>
+      {
+         EXIT_CRIT_SECTION(netp);
+ 803c344:	8028ef40 	call	8028ef4 <irq_Unmask>
+         return ((struct in_multi *)NULL);
+ 803c348:	0005883a 	mov	r2,zero
+ 803c34c:	00002506 	br	803c3e4 <in_addmulti+0x138>
+#ifdef IP_V6
+      if(addrtype == 6)
+         IP6CPY(&inm->ip6addr, (struct in6_addr *)ap);
+#endif
+#ifdef IP_V4
+      if(addrtype != 6)
+ 803c350:	e0bffb17 	ldw	r2,-20(fp)
+ 803c354:	108001a0 	cmpeqi	r2,r2,6
+ 803c358:	1000041e 	bne	r2,zero,803c36c <in_addmulti+0xc0>
+         inm->inm_addr = *ap;
+ 803c35c:	e0bffd17 	ldw	r2,-12(fp)
+ 803c360:	10c00017 	ldw	r3,0(r2)
+ 803c364:	e0bfff17 	ldw	r2,-4(fp)
+ 803c368:	10c00015 	stw	r3,0(r2)
+#endif
+      inm->inm_netp = netp;
+ 803c36c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c370:	e0fffc17 	ldw	r3,-16(fp)
+ 803c374:	10c00115 	stw	r3,4(r2)
+      inm->inm_refcount = 1;
+ 803c378:	e0bfff17 	ldw	r2,-4(fp)
+ 803c37c:	00c00044 	movi	r3,1
+ 803c380:	10c00215 	stw	r3,8(r2)
+      inm->inm_next = netp->mc_list;
+ 803c384:	e0bffc17 	ldw	r2,-16(fp)
+ 803c388:	10c02c17 	ldw	r3,176(r2)
+ 803c38c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c390:	10c00515 	stw	r3,20(r2)
+      netp->mc_list = inm;
+ 803c394:	e0bffc17 	ldw	r2,-16(fp)
+ 803c398:	e0ffff17 	ldw	r3,-4(fp)
+ 803c39c:	10c02c15 	stw	r3,176(r2)
+      /*
+       * If net has a multicast address registration routine then ask
+       * the network driver to update its multicast reception
+       * filter appropriately for the new address.
+       */
+      if(netp->n_mcastlist)
+ 803c3a0:	e0bffc17 	ldw	r2,-16(fp)
+ 803c3a4:	10802b17 	ldw	r2,172(r2)
+ 803c3a8:	10000626 	beq	r2,zero,803c3c4 <in_addmulti+0x118>
+         error = netp->n_mcastlist(inm);
+ 803c3ac:	e0bffc17 	ldw	r2,-16(fp)
+ 803c3b0:	10802b17 	ldw	r2,172(r2)
+ 803c3b4:	e13fff17 	ldw	r4,-4(fp)
+ 803c3b8:	103ee83a 	callr	r2
+ 803c3bc:	e0bffe15 	stw	r2,-8(fp)
+ 803c3c0:	00000106 	br	803c3c8 <in_addmulti+0x11c>
+      else
+         error = 0;
+ 803c3c4:	e03ffe15 	stw	zero,-8(fp)
+#if defined (IGMP_V1) || defined (IGMP_V2)
+      /*
+       * Let IGMP know that we have joined a new IP multicast group.
+       */
+      if (inm->inm_addr) igmp_joingroup(inm);
+ 803c3c8:	e0bfff17 	ldw	r2,-4(fp)
+ 803c3cc:	10800017 	ldw	r2,0(r2)
+ 803c3d0:	10000226 	beq	r2,zero,803c3dc <in_addmulti+0x130>
+ 803c3d4:	e13fff17 	ldw	r4,-4(fp)
+ 803c3d8:	80258d80 	call	80258d8 <igmp_joingroup>
+#endif      
+   }
+
+   EXIT_CRIT_SECTION(netp);
+ 803c3dc:	8028ef40 	call	8028ef4 <irq_Unmask>
+   USE_ARG(error);
+
+   return (inm);
+ 803c3e0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803c3e4:	e037883a 	mov	sp,fp
+ 803c3e8:	dfc00117 	ldw	ra,4(sp)
+ 803c3ec:	df000017 	ldw	fp,0(sp)
+ 803c3f0:	dec00204 	addi	sp,sp,8
+ 803c3f4:	f800283a 	ret
+
+0803c3f8 <in_delmulti>:
+ * RETURNS: 
+ */
+
+void
+in_delmulti(struct in_multi * inm)
+{
+ 803c3f8:	defffa04 	addi	sp,sp,-24
+ 803c3fc:	dfc00515 	stw	ra,20(sp)
+ 803c400:	df000415 	stw	fp,16(sp)
+ 803c404:	df000404 	addi	fp,sp,16
+ 803c408:	e13ffc15 	stw	r4,-16(fp)
+   struct in_multi * p;
+   NET         netp = inm->inm_netp;
+ 803c40c:	e0bffc17 	ldw	r2,-16(fp)
+ 803c410:	10800117 	ldw	r2,4(r2)
+ 803c414:	e0bffd15 	stw	r2,-12(fp)
+   int error;
+
+   ENTER_CRIT_SECTION(inm);
+ 803c418:	8028e940 	call	8028e94 <irq_Mask>
+   if (--inm->inm_refcount == 0) 
+ 803c41c:	e0bffc17 	ldw	r2,-16(fp)
+ 803c420:	10800217 	ldw	r2,8(r2)
+ 803c424:	10ffffc4 	addi	r3,r2,-1
+ 803c428:	e0bffc17 	ldw	r2,-16(fp)
+ 803c42c:	10c00215 	stw	r3,8(r2)
+ 803c430:	e0bffc17 	ldw	r2,-16(fp)
+ 803c434:	10800217 	ldw	r2,8(r2)
+ 803c438:	10002b1e 	bne	r2,zero,803c4e8 <in_delmulti+0xf0>
+   {
+      /* Unlink from list.  */
+      for (p = netp->mc_list; p; p = p->inm_next)
+ 803c43c:	e0bffd17 	ldw	r2,-12(fp)
+ 803c440:	10802c17 	ldw	r2,176(r2)
+ 803c444:	e0bfff15 	stw	r2,-4(fp)
+ 803c448:	00001406 	br	803c49c <in_delmulti+0xa4>
+      {
+         if(p == inm)   /* inm is first in mc_list */
+ 803c44c:	e0ffff17 	ldw	r3,-4(fp)
+ 803c450:	e0bffc17 	ldw	r2,-16(fp)
+ 803c454:	1880051e 	bne	r3,r2,803c46c <in_delmulti+0x74>
+         {
+            netp->mc_list = p->inm_next;  /* unlink */
+ 803c458:	e0bfff17 	ldw	r2,-4(fp)
+ 803c45c:	10c00517 	ldw	r3,20(r2)
+ 803c460:	e0bffd17 	ldw	r2,-12(fp)
+ 803c464:	10c02c15 	stw	r3,176(r2)
+            break;
+ 803c468:	00000e06 	br	803c4a4 <in_delmulti+0xac>
+         }
+         else if(p->inm_next == inm)   /* inm is next */
+ 803c46c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c470:	10800517 	ldw	r2,20(r2)
+ 803c474:	e0fffc17 	ldw	r3,-16(fp)
+ 803c478:	1880051e 	bne	r3,r2,803c490 <in_delmulti+0x98>
+         {
+            p->inm_next = inm->inm_next;  /* unlink */
+ 803c47c:	e0bffc17 	ldw	r2,-16(fp)
+ 803c480:	10c00517 	ldw	r3,20(r2)
+ 803c484:	e0bfff17 	ldw	r2,-4(fp)
+ 803c488:	10c00515 	stw	r3,20(r2)
+            break;
+ 803c48c:	00000506 	br	803c4a4 <in_delmulti+0xac>
+      for (p = netp->mc_list; p; p = p->inm_next)
+ 803c490:	e0bfff17 	ldw	r2,-4(fp)
+ 803c494:	10800517 	ldw	r2,20(r2)
+ 803c498:	e0bfff15 	stw	r2,-4(fp)
+ 803c49c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c4a0:	103fea1e 	bne	r2,zero,803c44c <in_delmulti+0x54>
+      /*
+       * If net has a multicast address registration routine then ask
+       * the network driver to update its multicast reception
+       * filter appropriately for the deleted address.
+       */
+      if(netp->n_mcastlist)
+ 803c4a4:	e0bffd17 	ldw	r2,-12(fp)
+ 803c4a8:	10802b17 	ldw	r2,172(r2)
+ 803c4ac:	10000626 	beq	r2,zero,803c4c8 <in_delmulti+0xd0>
+         error = netp->n_mcastlist(inm);
+ 803c4b0:	e0bffd17 	ldw	r2,-12(fp)
+ 803c4b4:	10802b17 	ldw	r2,172(r2)
+ 803c4b8:	e13ffc17 	ldw	r4,-16(fp)
+ 803c4bc:	103ee83a 	callr	r2
+ 803c4c0:	e0bffe15 	stw	r2,-8(fp)
+ 803c4c4:	00000106 	br	803c4cc <in_delmulti+0xd4>
+      else
+         error = 0;
+ 803c4c8:	e03ffe15 	stw	zero,-8(fp)
+#if defined (IGMP_V2)
+      /*
+       * No remaining claims to this record; let IGMP know that
+       * we are leaving the multicast group.
+       */
+      if (inm->inm_addr) igmp_leavegroup(inm);
+ 803c4cc:	e0bffc17 	ldw	r2,-16(fp)
+ 803c4d0:	10800017 	ldw	r2,0(r2)
+ 803c4d4:	10000226 	beq	r2,zero,803c4e0 <in_delmulti+0xe8>
+ 803c4d8:	e13ffc17 	ldw	r4,-16(fp)
+ 803c4dc:	8025b040 	call	8025b04 <igmp_leavegroup>
+#endif      
+
+      IM_FREE(inm);
+ 803c4e0:	e13ffc17 	ldw	r4,-16(fp)
+ 803c4e4:	80298600 	call	8029860 <npfree>
+   }
+
+   EXIT_CRIT_SECTION(inm);
+ 803c4e8:	8028ef40 	call	8028ef4 <irq_Unmask>
+   USE_ARG(error);
+}
+ 803c4ec:	0001883a 	nop
+ 803c4f0:	e037883a 	mov	sp,fp
+ 803c4f4:	dfc00117 	ldw	ra,4(sp)
+ 803c4f8:	df000017 	ldw	fp,0(sp)
+ 803c4fc:	dec00204 	addi	sp,sp,8
+ 803c500:	f800283a 	ret
+
+0803c504 <lookup_mcast>:
+ * RETURNS: pointer to mcast addr structure, or NULL if not found.
+ */
+
+struct in_multi *
+lookup_mcast(ip_addr addr, NET netp)
+{
+ 803c504:	defffc04 	addi	sp,sp,-16
+ 803c508:	df000315 	stw	fp,12(sp)
+ 803c50c:	df000304 	addi	fp,sp,12
+ 803c510:	e13ffe15 	stw	r4,-8(fp)
+ 803c514:	e17ffd15 	stw	r5,-12(fp)
+   struct in_multi * imp;
+
+   for (imp = netp->mc_list; imp; imp = imp->inm_next)
+ 803c518:	e0bffd17 	ldw	r2,-12(fp)
+ 803c51c:	10802c17 	ldw	r2,176(r2)
+ 803c520:	e0bfff15 	stw	r2,-4(fp)
+ 803c524:	00000906 	br	803c54c <lookup_mcast+0x48>
+   {
+      if(imp->inm_addr == addr)
+ 803c528:	e0bfff17 	ldw	r2,-4(fp)
+ 803c52c:	10800017 	ldw	r2,0(r2)
+ 803c530:	e0fffe17 	ldw	r3,-8(fp)
+ 803c534:	1880021e 	bne	r3,r2,803c540 <lookup_mcast+0x3c>
+         return imp;
+ 803c538:	e0bfff17 	ldw	r2,-4(fp)
+ 803c53c:	00000606 	br	803c558 <lookup_mcast+0x54>
+   for (imp = netp->mc_list; imp; imp = imp->inm_next)
+ 803c540:	e0bfff17 	ldw	r2,-4(fp)
+ 803c544:	10800517 	ldw	r2,20(r2)
+ 803c548:	e0bfff15 	stw	r2,-4(fp)
+ 803c54c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c550:	103ff51e 	bne	r2,zero,803c528 <lookup_mcast+0x24>
+   }
+   return NULL;   /* addr not found in mcast list */
+ 803c554:	0005883a 	mov	r2,zero
+}
+ 803c558:	e037883a 	mov	sp,fp
+ 803c55c:	df000017 	ldw	fp,0(sp)
+ 803c560:	dec00104 	addi	sp,sp,4
+ 803c564:	f800283a 	ret
+
+0803c568 <prep_ifaces>:
+ * passed value. 
+ */
+
+int
+prep_ifaces(int ifaces_found)
+{
+ 803c568:	defffd04 	addi	sp,sp,-12
+ 803c56c:	dfc00215 	stw	ra,8(sp)
+ 803c570:	df000115 	stw	fp,4(sp)
+ 803c574:	df000104 	addi	fp,sp,4
+ 803c578:	e13fff15 	stw	r4,-4(fp)
+   if (port_prep)
+ 803c57c:	d0a09617 	ldw	r2,-32168(gp)
+ 803c580:	10000426 	beq	r2,zero,803c594 <prep_ifaces+0x2c>
+      ifaces_found = port_prep(ifaces_found);
+ 803c584:	d0a09617 	ldw	r2,-32168(gp)
+ 803c588:	e13fff17 	ldw	r4,-4(fp)
+ 803c58c:	103ee83a 	callr	r2
+ 803c590:	e0bfff15 	stw	r2,-4(fp)
+
+#ifdef MAC_LOOPBACK
+   ifaces_found = prep_lb(ifaces_found);
+#endif   /* MAC_LOOPBACK */
+
+   ifNumber = ifaces_found;   /* set global interface counter */
+ 803c594:	e0bfff17 	ldw	r2,-4(fp)
+ 803c598:	d0a06715 	stw	r2,-32356(gp)
+
+   initmsg("prepped %u interface%s, initializing...\n", 
+ 803c59c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c5a0:	10800058 	cmpnei	r2,r2,1
+ 803c5a4:	1000031e 	bne	r2,zero,803c5b4 <prep_ifaces+0x4c>
+ 803c5a8:	00820174 	movhi	r2,2053
+ 803c5ac:	10acd004 	addi	r2,r2,-19648
+ 803c5b0:	00000206 	br	803c5bc <prep_ifaces+0x54>
+ 803c5b4:	00820174 	movhi	r2,2053
+ 803c5b8:	10acd104 	addi	r2,r2,-19644
+ 803c5bc:	100d883a 	mov	r6,r2
+ 803c5c0:	e17fff17 	ldw	r5,-4(fp)
+ 803c5c4:	01020174 	movhi	r4,2053
+ 803c5c8:	212cd204 	addi	r4,r4,-19640
+ 803c5cc:	8002c780 	call	8002c78 <printf>
+      ifaces_found, ifaces_found==1?"":"s");
+
+   return ifaces_found;
+ 803c5d0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803c5d4:	e037883a 	mov	sp,fp
+ 803c5d8:	dfc00117 	ldw	ra,4(sp)
+ 803c5dc:	df000017 	ldw	fp,0(sp)
+ 803c5e0:	dec00204 	addi	sp,sp,8
+ 803c5e4:	f800283a 	ret
+
+0803c5e8 <netexit>:
+ * RETURNS: SHould not return
+ */
+
+void
+netexit(int err)      /* exit error level */
+{
+ 803c5e8:	defffd04 	addi	sp,sp,-12
+ 803c5ec:	dfc00215 	stw	ra,8(sp)
+ 803c5f0:	df000115 	stw	fp,4(sp)
+ 803c5f4:	df000104 	addi	fp,sp,4
+ 803c5f8:	e13fff15 	stw	r4,-4(fp)
+   net_system_exit = TRUE; /* set flag for shutting down */
+ 803c5fc:	00800044 	movi	r2,1
+ 803c600:	d0a09715 	stw	r2,-32164(gp)
+   ip_exit();  /* do the exit_hook()ed stuff */
+ 803c604:	802524c0 	call	802524c <ip_exit>
+
+   PORT_EXIT_FUNC(err);    /* should not return! */
+ 803c608:	e13fff17 	ldw	r4,-4(fp)
+ 803c60c:	8042abc0 	call	8042abc <exit>
+
+0803c610 <evtmap_setup>:
+ * INPUT: None.
+ * OUTPUT: None
+ */
+ 
+void evtmap_setup (void)
+{
+ 803c610:	deffff04 	addi	sp,sp,-4
+ 803c614:	df000015 	stw	fp,0(sp)
+ 803c618:	d839883a 	mov	fp,sp
+#ifdef SOCK_MAP_EVENTS
+   so_evtmap = TRUE;
+   so_evtmap_create = evtmap_create;
+   so_evtmap_delete = evtmap_delete;
+#else
+   so_evtmap = FALSE;
+ 803c61c:	d0209a05 	stb	zero,-32152(gp)
+   so_evtmap_create = 0;
+ 803c620:	d0209815 	stw	zero,-32160(gp)
+   so_evtmap_delete = 0;
+ 803c624:	d0209915 	stw	zero,-32156(gp)
+#endif   /* SOCK_MAP_EVENTS */ 
+
+}
+ 803c628:	0001883a 	nop
+ 803c62c:	e037883a 	mov	sp,fp
+ 803c630:	df000017 	ldw	fp,0(sp)
+ 803c634:	dec00104 	addi	sp,sp,4
+ 803c638:	f800283a 	ret
+
+0803c63c <ip_raw_open>:
+ip_raw_open(u_char prot,
+            ip_addr laddr,
+            ip_addr faddr,
+            int (*handler)(PACKET, void *),
+            void * data)
+{
+ 803c63c:	defff904 	addi	sp,sp,-28
+ 803c640:	dfc00615 	stw	ra,24(sp)
+ 803c644:	df000515 	stw	fp,20(sp)
+ 803c648:	df000504 	addi	fp,sp,20
+ 803c64c:	2005883a 	mov	r2,r4
+ 803c650:	e17ffd15 	stw	r5,-12(fp)
+ 803c654:	e1bffc15 	stw	r6,-16(fp)
+ 803c658:	e1fffb15 	stw	r7,-20(fp)
+ 803c65c:	e0bffe05 	stb	r2,-8(fp)
+   struct ipraw_ep * ep;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 803c660:	0009883a 	mov	r4,zero
+ 803c664:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* allocate a structure for the endpoint */
+   ep = (struct ipraw_ep *)IEP_ALLOC(sizeof(struct ipraw_ep));
+ 803c668:	01000604 	movi	r4,24
+ 803c66c:	802982c0 	call	802982c <npalloc>
+ 803c670:	e0bfff15 	stw	r2,-4(fp)
+   if (ep == NULL)
+ 803c674:	e0bfff17 	ldw	r2,-4(fp)
+ 803c678:	10000a1e 	bne	r2,zero,803c6a4 <ip_raw_open+0x68>
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & INFOMSG)
+ 803c67c:	d0a06617 	ldw	r2,-32360(gp)
+ 803c680:	1080010c 	andi	r2,r2,4
+ 803c684:	10000326 	beq	r2,zero,803c694 <ip_raw_open+0x58>
+         dprintf("IP: Couldn't allocate ep storage.\n");
+ 803c688:	01020174 	movhi	r4,2053
+ 803c68c:	212cdd04 	addi	r4,r4,-19596
+ 803c690:	8002d9c0 	call	8002d9c <puts>
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c694:	0009883a 	mov	r4,zero
+ 803c698:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return ep;
+ 803c69c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6a0:	00001706 	br	803c700 <ip_raw_open+0xc4>
+   }
+
+   /* fill it in with the caller's requested binding */
+   ep->ipr_laddr = laddr;
+ 803c6a4:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6a8:	e0fffd17 	ldw	r3,-12(fp)
+ 803c6ac:	10c00115 	stw	r3,4(r2)
+   ep->ipr_faddr = faddr;
+ 803c6b0:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6b4:	e0fffc17 	ldw	r3,-16(fp)
+ 803c6b8:	10c00215 	stw	r3,8(r2)
+   ep->ipr_prot = prot;
+ 803c6bc:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6c0:	e0fffe03 	ldbu	r3,-8(fp)
+ 803c6c4:	10c00505 	stb	r3,20(r2)
+   ep->ipr_rcv = handler;
+ 803c6c8:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6cc:	e0fffb17 	ldw	r3,-20(fp)
+ 803c6d0:	10c00315 	stw	r3,12(r2)
+   ep->ipr_data = data;
+ 803c6d4:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6d8:	e0c00217 	ldw	r3,8(fp)
+ 803c6dc:	10c00415 	stw	r3,16(r2)
+
+   /* link it into the list 
+    * (at the head, because that's simple and fast) 
+    */
+   ep->ipr_next = ipraw_eps;
+ 803c6e0:	d0e09b17 	ldw	r3,-32148(gp)
+ 803c6e4:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6e8:	10c00015 	stw	r3,0(r2)
+   ipraw_eps = ep;
+ 803c6ec:	e0bfff17 	ldw	r2,-4(fp)
+ 803c6f0:	d0a09b15 	stw	r2,-32148(gp)
+
+   /* and return the pointer to the endpoint */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c6f4:	0009883a 	mov	r4,zero
+ 803c6f8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return ep;
+ 803c6fc:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803c700:	e037883a 	mov	sp,fp
+ 803c704:	dfc00117 	ldw	ra,4(sp)
+ 803c708:	df000017 	ldw	fp,0(sp)
+ 803c70c:	dec00204 	addi	sp,sp,8
+ 803c710:	f800283a 	ret
+
+0803c714 <ip_raw_close>:
+ *                               that is to be closed
+ * RETURNS: void
+ */
+void
+ip_raw_close(struct ipraw_ep * ep)
+{
+ 803c714:	defffb04 	addi	sp,sp,-20
+ 803c718:	dfc00415 	stw	ra,16(sp)
+ 803c71c:	df000315 	stw	fp,12(sp)
+ 803c720:	df000304 	addi	fp,sp,12
+ 803c724:	e13ffd15 	stw	r4,-12(fp)
+   struct ipraw_ep * prev_ep;
+   struct ipraw_ep * curr_ep;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 803c728:	0009883a 	mov	r4,zero
+ 803c72c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+
+   /* search the list of endpoints for the one we're supposed to close */
+   for (prev_ep = NULL, curr_ep = ipraw_eps;
+ 803c730:	e03fff15 	stw	zero,-4(fp)
+ 803c734:	d0a09b17 	ldw	r2,-32148(gp)
+ 803c738:	e0bffe15 	stw	r2,-8(fp)
+ 803c73c:	00000806 	br	803c760 <ip_raw_close+0x4c>
+        curr_ep != NULL;
+        curr_ep = curr_ep->ipr_next)
+   {
+      if (curr_ep == ep)
+ 803c740:	e0fffe17 	ldw	r3,-8(fp)
+ 803c744:	e0bffd17 	ldw	r2,-12(fp)
+ 803c748:	18800826 	beq	r3,r2,803c76c <ip_raw_close+0x58>
+         break;
+      prev_ep = curr_ep;
+ 803c74c:	e0bffe17 	ldw	r2,-8(fp)
+ 803c750:	e0bfff15 	stw	r2,-4(fp)
+        curr_ep = curr_ep->ipr_next)
+ 803c754:	e0bffe17 	ldw	r2,-8(fp)
+ 803c758:	10800017 	ldw	r2,0(r2)
+ 803c75c:	e0bffe15 	stw	r2,-8(fp)
+   for (prev_ep = NULL, curr_ep = ipraw_eps;
+ 803c760:	e0bffe17 	ldw	r2,-8(fp)
+ 803c764:	103ff61e 	bne	r2,zero,803c740 <ip_raw_close+0x2c>
+ 803c768:	00000106 	br	803c770 <ip_raw_close+0x5c>
+         break;
+ 803c76c:	0001883a 	nop
+   }
+
+   /* if we didn't find it, we can't close it, so just return */
+   if (curr_ep == NULL)
+ 803c770:	e0bffe17 	ldw	r2,-8(fp)
+ 803c774:	1000041e 	bne	r2,zero,803c788 <ip_raw_close+0x74>
+   {
+#ifdef NPDEBUG
+      /* caller passed pointer to endpoint not in list 
+       * -- not fatal, but may be programming error
+       */
+      dtrap();
+ 803c778:	8028cd40 	call	8028cd4 <dtrap>
+#endif /* NPDEBUG */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c77c:	0009883a 	mov	r4,zero
+ 803c780:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return;
+ 803c784:	00000d06 	br	803c7bc <ip_raw_close+0xa8>
+   }
+
+   /* unlink it from the list */
+   if (prev_ep)
+ 803c788:	e0bfff17 	ldw	r2,-4(fp)
+ 803c78c:	10000426 	beq	r2,zero,803c7a0 <ip_raw_close+0x8c>
+      prev_ep = curr_ep->ipr_next;
+ 803c790:	e0bffe17 	ldw	r2,-8(fp)
+ 803c794:	10800017 	ldw	r2,0(r2)
+ 803c798:	e0bfff15 	stw	r2,-4(fp)
+ 803c79c:	00000306 	br	803c7ac <ip_raw_close+0x98>
+   else
+      ipraw_eps = curr_ep->ipr_next;
+ 803c7a0:	e0bffe17 	ldw	r2,-8(fp)
+ 803c7a4:	10800017 	ldw	r2,0(r2)
+ 803c7a8:	d0a09b15 	stw	r2,-32148(gp)
+
+   /* free its storage */
+   IEP_FREE(curr_ep);
+ 803c7ac:	e13ffe17 	ldw	r4,-8(fp)
+ 803c7b0:	80298600 	call	8029860 <npfree>
+
+   /* and return */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c7b4:	0009883a 	mov	r4,zero
+ 803c7b8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+}
+ 803c7bc:	e037883a 	mov	sp,fp
+ 803c7c0:	dfc00117 	ldw	ra,4(sp)
+ 803c7c4:	df000017 	ldw	fp,0(sp)
+ 803c7c8:	dec00204 	addi	sp,sp,8
+ 803c7cc:	f800283a 	ret
+
+0803c7d0 <ip_raw_input>:
+ *          freed); else an error code indicating that the
+ *          received packet was not accepted/processed
+ */
+int
+ip_raw_input(PACKET p)
+{
+ 803c7d0:	defff604 	addi	sp,sp,-40
+ 803c7d4:	dfc00915 	stw	ra,36(sp)
+ 803c7d8:	df000815 	stw	fp,32(sp)
+ 803c7dc:	df000804 	addi	fp,sp,32
+ 803c7e0:	e13ff815 	stw	r4,-32(fp)
+   struct ip * pip;              /* the internet header */
+   struct ipraw_ep * ep;
+   struct ipraw_ep * next_ep;
+   struct ipraw_ep * matched_ep = NULL;
+ 803c7e4:	e03ffe15 	stw	zero,-8(fp)
+   int err;
+   int delivered;
+
+   /* start out expecting to not deliver the packet */
+   delivered = 0;
+ 803c7e8:	e03ffc15 	stw	zero,-16(fp)
+
+   /* get a pointer to the received packet's IP header */
+   pip = (struct ip *)(p->nb_prot);
+ 803c7ec:	e0bff817 	ldw	r2,-32(fp)
+ 803c7f0:	10800317 	ldw	r2,12(r2)
+ 803c7f4:	e0bffb15 	stw	r2,-20(fp)
+
+   /* search the list of raw-IP endpoints for matches */
+   for (ep = ipraw_eps; ep != NULL; ep = next_ep)
+ 803c7f8:	d0a09b17 	ldw	r2,-32148(gp)
+ 803c7fc:	e0bfff15 	stw	r2,-4(fp)
+ 803c800:	00004c06 	br	803c934 <ip_raw_input+0x164>
+   {
+      /* keep track of next endpoint -- defense against upcall
+       * function closing its own endpoint
+       */
+      next_ep = ep->ipr_next;
+ 803c804:	e0bfff17 	ldw	r2,-4(fp)
+ 803c808:	10800017 	ldw	r2,0(r2)
+ 803c80c:	e0bffa15 	stw	r2,-24(fp)
+
+      /* if this packet doesn't match the endpoint's filters (IP
+       * protocol ID, locally-bound address, connected-peer address)
+       * then skip ahead to next endpoint
+       */
+      if (ep->ipr_prot && ep->ipr_prot != pip->ip_prot)
+ 803c810:	e0bfff17 	ldw	r2,-4(fp)
+ 803c814:	10800503 	ldbu	r2,20(r2)
+ 803c818:	10803fcc 	andi	r2,r2,255
+ 803c81c:	10000726 	beq	r2,zero,803c83c <ip_raw_input+0x6c>
+ 803c820:	e0bfff17 	ldw	r2,-4(fp)
+ 803c824:	10c00503 	ldbu	r3,20(r2)
+ 803c828:	e0bffb17 	ldw	r2,-20(fp)
+ 803c82c:	10800243 	ldbu	r2,9(r2)
+ 803c830:	18c03fcc 	andi	r3,r3,255
+ 803c834:	10803fcc 	andi	r2,r2,255
+ 803c838:	1880371e 	bne	r3,r2,803c918 <ip_raw_input+0x148>
+         continue;
+      if (ep->ipr_laddr && ep->ipr_laddr != pip->ip_dest)
+ 803c83c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c840:	10800117 	ldw	r2,4(r2)
+ 803c844:	10000526 	beq	r2,zero,803c85c <ip_raw_input+0x8c>
+ 803c848:	e0bfff17 	ldw	r2,-4(fp)
+ 803c84c:	10c00117 	ldw	r3,4(r2)
+ 803c850:	e0bffb17 	ldw	r2,-20(fp)
+ 803c854:	10800417 	ldw	r2,16(r2)
+ 803c858:	1880311e 	bne	r3,r2,803c920 <ip_raw_input+0x150>
+         continue;
+      if (ep->ipr_faddr && ep->ipr_faddr != pip->ip_src)
+ 803c85c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c860:	10800217 	ldw	r2,8(r2)
+ 803c864:	10000526 	beq	r2,zero,803c87c <ip_raw_input+0xac>
+ 803c868:	e0bfff17 	ldw	r2,-4(fp)
+ 803c86c:	10c00217 	ldw	r3,8(r2)
+ 803c870:	e0bffb17 	ldw	r2,-20(fp)
+ 803c874:	10800317 	ldw	r2,12(r2)
+ 803c878:	18802b1e 	bne	r3,r2,803c928 <ip_raw_input+0x158>
+         continue;
+
+      /* if the endpoint has a receive upcall function, 
+       * keep track of the endpoint
+       */
+      if (ep->ipr_rcv != NULL)
+ 803c87c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c880:	10800317 	ldw	r2,12(r2)
+ 803c884:	10002926 	beq	r2,zero,803c92c <ip_raw_input+0x15c>
+          * copy the packet into a new buffer,
+          * and pass the new copy to the previously matched 
+          * endpoint's upcall function 
+          * before we forget the previous endpoint
+          */
+         if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL))
+ 803c888:	e0bffe17 	ldw	r2,-8(fp)
+ 803c88c:	10001f26 	beq	r2,zero,803c90c <ip_raw_input+0x13c>
+ 803c890:	e0bffe17 	ldw	r2,-8(fp)
+ 803c894:	10800317 	ldw	r2,12(r2)
+ 803c898:	10001c26 	beq	r2,zero,803c90c <ip_raw_input+0x13c>
+         {
+            PACKET p2;
+
+            p2 = ip_copypkt(p);
+ 803c89c:	e13ff817 	ldw	r4,-32(fp)
+ 803c8a0:	803b53c0 	call	803b53c <ip_copypkt>
+ 803c8a4:	e0bff915 	stw	r2,-28(fp)
+            if (p2)
+ 803c8a8:	e0bff917 	ldw	r2,-28(fp)
+ 803c8ac:	10001726 	beq	r2,zero,803c90c <ip_raw_input+0x13c>
+            {
+               UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c8b0:	0009883a 	mov	r4,zero
+ 803c8b4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+               err = ((*matched_ep->ipr_rcv)(p2, matched_ep->ipr_data));
+ 803c8b8:	e0bffe17 	ldw	r2,-8(fp)
+ 803c8bc:	10800317 	ldw	r2,12(r2)
+ 803c8c0:	e0fffe17 	ldw	r3,-8(fp)
+ 803c8c4:	18c00417 	ldw	r3,16(r3)
+ 803c8c8:	180b883a 	mov	r5,r3
+ 803c8cc:	e13ff917 	ldw	r4,-28(fp)
+ 803c8d0:	103ee83a 	callr	r2
+ 803c8d4:	e0bffd15 	stw	r2,-12(fp)
+               LOCK_NET_RESOURCE(NET_RESID);
+ 803c8d8:	0009883a 	mov	r4,zero
+ 803c8dc:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+               if (err)
+ 803c8e0:	e0bffd17 	ldw	r2,-12(fp)
+ 803c8e4:	10000726 	beq	r2,zero,803c904 <ip_raw_input+0x134>
+               {
+                  LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803c8e8:	01000084 	movi	r4,2
+ 803c8ec:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+                  pk_free(p2);
+ 803c8f0:	e13ff917 	ldw	r4,-28(fp)
+ 803c8f4:	80287480 	call	8028748 <pk_free>
+                  UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803c8f8:	01000084 	movi	r4,2
+ 803c8fc:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+ 803c900:	00000206 	br	803c90c <ip_raw_input+0x13c>
+               }
+               else
+                  delivered = 1;
+ 803c904:	00800044 	movi	r2,1
+ 803c908:	e0bffc15 	stw	r2,-16(fp)
+            }
+         }
+         matched_ep = ep;
+ 803c90c:	e0bfff17 	ldw	r2,-4(fp)
+ 803c910:	e0bffe15 	stw	r2,-8(fp)
+ 803c914:	00000506 	br	803c92c <ip_raw_input+0x15c>
+         continue;
+ 803c918:	0001883a 	nop
+ 803c91c:	00000306 	br	803c92c <ip_raw_input+0x15c>
+         continue;
+ 803c920:	0001883a 	nop
+ 803c924:	00000106 	br	803c92c <ip_raw_input+0x15c>
+         continue;
+ 803c928:	0001883a 	nop
+   for (ep = ipraw_eps; ep != NULL; ep = next_ep)
+ 803c92c:	e0bffa17 	ldw	r2,-24(fp)
+ 803c930:	e0bfff15 	stw	r2,-4(fp)
+ 803c934:	e0bfff17 	ldw	r2,-4(fp)
+ 803c938:	103fb21e 	bne	r2,zero,803c804 <ip_raw_input+0x34>
+   /* if we matched an endpoint, 
+    * pass the packet to its upcall function
+    * otherwise, return ENP_PARAM to indicate that the
+    * packet was not processed and freed
+    */
+   if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL))
+ 803c93c:	e0bffe17 	ldw	r2,-8(fp)
+ 803c940:	10001426 	beq	r2,zero,803c994 <ip_raw_input+0x1c4>
+ 803c944:	e0bffe17 	ldw	r2,-8(fp)
+ 803c948:	10800317 	ldw	r2,12(r2)
+ 803c94c:	10001126 	beq	r2,zero,803c994 <ip_raw_input+0x1c4>
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 803c950:	0009883a 	mov	r4,zero
+ 803c954:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      err = ((*matched_ep->ipr_rcv)(p, matched_ep->ipr_data));
+ 803c958:	e0bffe17 	ldw	r2,-8(fp)
+ 803c95c:	10800317 	ldw	r2,12(r2)
+ 803c960:	e0fffe17 	ldw	r3,-8(fp)
+ 803c964:	18c00417 	ldw	r3,16(r3)
+ 803c968:	180b883a 	mov	r5,r3
+ 803c96c:	e13ff817 	ldw	r4,-32(fp)
+ 803c970:	103ee83a 	callr	r2
+ 803c974:	e0bffd15 	stw	r2,-12(fp)
+      LOCK_NET_RESOURCE(NET_RESID);
+ 803c978:	0009883a 	mov	r4,zero
+ 803c97c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+      if (err == 0)
+ 803c980:	e0bffd17 	ldw	r2,-12(fp)
+ 803c984:	10000a1e 	bne	r2,zero,803c9b0 <ip_raw_input+0x1e0>
+         delivered = 1;
+ 803c988:	00800044 	movi	r2,1
+ 803c98c:	e0bffc15 	stw	r2,-16(fp)
+      if (err == 0)
+ 803c990:	00000706 	br	803c9b0 <ip_raw_input+0x1e0>
+   }
+   else
+   {
+      err = ENP_PARAM;
+ 803c994:	00bffd84 	movi	r2,-10
+ 803c998:	e0bffd15 	stw	r2,-12(fp)
+      ip_mib.ipUnknownProtos++;
+ 803c99c:	008201b4 	movhi	r2,2054
+ 803c9a0:	10b95517 	ldw	r2,-6828(r2)
+ 803c9a4:	10c00044 	addi	r3,r2,1
+ 803c9a8:	008201b4 	movhi	r2,2054
+ 803c9ac:	10f95515 	stw	r3,-6828(r2)
+   }
+
+   if (!delivered)
+ 803c9b0:	e0bffc17 	ldw	r2,-16(fp)
+ 803c9b4:	1000051e 	bne	r2,zero,803c9cc <ip_raw_input+0x1fc>
+      ip_mib.ipInDelivers--;
+ 803c9b8:	008201b4 	movhi	r2,2054
+ 803c9bc:	10b95717 	ldw	r2,-6820(r2)
+ 803c9c0:	10ffffc4 	addi	r3,r2,-1
+ 803c9c4:	008201b4 	movhi	r2,2054
+ 803c9c8:	10f95715 	stw	r3,-6820(r2)
+
+   return err;
+ 803c9cc:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 803c9d0:	e037883a 	mov	sp,fp
+ 803c9d4:	dfc00117 	ldw	ra,4(sp)
+ 803c9d8:	df000017 	ldw	fp,0(sp)
+ 803c9dc:	dec00204 	addi	sp,sp,8
+ 803c9e0:	f800283a 	ret
+
+0803c9e4 <ip_raw_alloc>:
+ *          inclhdr is zero.
+ */
+
+PACKET
+ip_raw_alloc(int reqlen, int hdrincl)
+{
+ 803c9e4:	defffa04 	addi	sp,sp,-24
+ 803c9e8:	dfc00515 	stw	ra,20(sp)
+ 803c9ec:	df000415 	stw	fp,16(sp)
+ 803c9f0:	df000404 	addi	fp,sp,16
+ 803c9f4:	e13ffd15 	stw	r4,-12(fp)
+ 803c9f8:	e17ffc15 	stw	r5,-16(fp)
+   int len;
+   PACKET p;
+
+   len = (reqlen + 1) & ~1;
+ 803c9fc:	e0bffd17 	ldw	r2,-12(fp)
+ 803ca00:	10c00044 	addi	r3,r2,1
+ 803ca04:	00bfff84 	movi	r2,-2
+ 803ca08:	1884703a 	and	r2,r3,r2
+ 803ca0c:	e0bfff15 	stw	r2,-4(fp)
+   if (!hdrincl)
+ 803ca10:	e0bffc17 	ldw	r2,-16(fp)
+ 803ca14:	1000031e 	bne	r2,zero,803ca24 <ip_raw_alloc+0x40>
+      len += IPHSIZ;
+ 803ca18:	e0bfff17 	ldw	r2,-4(fp)
+ 803ca1c:	10800504 	addi	r2,r2,20
+ 803ca20:	e0bfff15 	stw	r2,-4(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803ca24:	01000084 	movi	r4,2
+ 803ca28:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   p = pk_alloc(len + MaxLnh);
+ 803ca2c:	d0e06417 	ldw	r3,-32368(gp)
+ 803ca30:	e0bfff17 	ldw	r2,-4(fp)
+ 803ca34:	1885883a 	add	r2,r3,r2
+ 803ca38:	1009883a 	mov	r4,r2
+ 803ca3c:	80284340 	call	8028434 <pk_alloc>
+ 803ca40:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803ca44:	01000084 	movi	r4,2
+ 803ca48:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   if (p)
+ 803ca4c:	e0bffe17 	ldw	r2,-8(fp)
+ 803ca50:	10000c26 	beq	r2,zero,803ca84 <ip_raw_alloc+0xa0>
+   {
+      if (!hdrincl)
+ 803ca54:	e0bffc17 	ldw	r2,-16(fp)
+ 803ca58:	10000a1e 	bne	r2,zero,803ca84 <ip_raw_alloc+0xa0>
+      {
+         p->nb_prot += IPHSIZ;
+ 803ca5c:	e0bffe17 	ldw	r2,-8(fp)
+ 803ca60:	10800317 	ldw	r2,12(r2)
+ 803ca64:	10c00504 	addi	r3,r2,20
+ 803ca68:	e0bffe17 	ldw	r2,-8(fp)
+ 803ca6c:	10c00315 	stw	r3,12(r2)
+         p->nb_plen -= IPHSIZ;
+ 803ca70:	e0bffe17 	ldw	r2,-8(fp)
+ 803ca74:	10800417 	ldw	r2,16(r2)
+ 803ca78:	10fffb04 	addi	r3,r2,-20
+ 803ca7c:	e0bffe17 	ldw	r2,-8(fp)
+ 803ca80:	10c00415 	stw	r3,16(r2)
+      }
+   }
+   return p;
+ 803ca84:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803ca88:	e037883a 	mov	sp,fp
+ 803ca8c:	dfc00117 	ldw	ra,4(sp)
+ 803ca90:	df000017 	ldw	fp,0(sp)
+ 803ca94:	dec00204 	addi	sp,sp,8
+ 803ca98:	f800283a 	ret
+
+0803ca9c <ip_raw_free>:
+ * RETURNS: void
+ */
+
+void
+ip_raw_free(PACKET p)
+{
+ 803ca9c:	defffd04 	addi	sp,sp,-12
+ 803caa0:	dfc00215 	stw	ra,8(sp)
+ 803caa4:	df000115 	stw	fp,4(sp)
+ 803caa8:	df000104 	addi	fp,sp,4
+ 803caac:	e13fff15 	stw	r4,-4(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803cab0:	01000084 	movi	r4,2
+ 803cab4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 803cab8:	e13fff17 	ldw	r4,-4(fp)
+ 803cabc:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803cac0:	01000084 	movi	r4,2
+ 803cac4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+}
+ 803cac8:	0001883a 	nop
+ 803cacc:	e037883a 	mov	sp,fp
+ 803cad0:	dfc00117 	ldw	ra,4(sp)
+ 803cad4:	df000017 	ldw	fp,0(sp)
+ 803cad8:	dec00204 	addi	sp,sp,8
+ 803cadc:	f800283a 	ret
+
+0803cae0 <ip_raw_maxalloc>:
+ *          for 
+ */
+
+int
+ip_raw_maxalloc(int hdrincl)
+{
+ 803cae0:	defffd04 	addi	sp,sp,-12
+ 803cae4:	df000215 	stw	fp,8(sp)
+ 803cae8:	df000204 	addi	fp,sp,8
+ 803caec:	e13ffe15 	stw	r4,-8(fp)
+   int len;
+
+   len = bigbufsiz - MaxLnh;
+ 803caf0:	d0a01917 	ldw	r2,-32668(gp)
+ 803caf4:	d0e06417 	ldw	r3,-32368(gp)
+ 803caf8:	10c5c83a 	sub	r2,r2,r3
+ 803cafc:	e0bfff15 	stw	r2,-4(fp)
+   if (!hdrincl)
+ 803cb00:	e0bffe17 	ldw	r2,-8(fp)
+ 803cb04:	1000031e 	bne	r2,zero,803cb14 <ip_raw_maxalloc+0x34>
+      len -= IPHSIZ;
+ 803cb08:	e0bfff17 	ldw	r2,-4(fp)
+ 803cb0c:	10bffb04 	addi	r2,r2,-20
+ 803cb10:	e0bfff15 	stw	r2,-4(fp)
+   return len;
+ 803cb14:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803cb18:	e037883a 	mov	sp,fp
+ 803cb1c:	df000017 	ldw	fp,0(sp)
+ 803cb20:	dec00104 	addi	sp,sp,4
+ 803cb24:	f800283a 	ret
+
+0803cb28 <rt_lookup>:
+ * entry was found.
+ */
+
+RTMIB
+rt_lookup(ip_addr host)
+{
+ 803cb28:	defff804 	addi	sp,sp,-32
+ 803cb2c:	df000715 	stw	fp,28(sp)
+ 803cb30:	df000704 	addi	fp,sp,28
+ 803cb34:	e13ff915 	stw	r4,-28(fp)
+   RTMIB    rtp;
+   RTMIB    netmatch;
+   unsigned char max_bits_matched = 0;
+ 803cb38:	e03ffdc5 	stb	zero,-9(fp)
+   unsigned char curr_bits_matched;
+   ip_addr  entry_mask;
+   unsigned long int bitcount_mask;
+   unsigned long int extracted_bit;
+
+   netmatch = NULL;
+ 803cb3c:	e03ffe15 	stw	zero,-8(fp)
+
+   /* see if it's in the route table. */
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803cb40:	d0a09517 	ldw	r2,-32172(gp)
+ 803cb44:	e0bfff15 	stw	r2,-4(fp)
+ 803cb48:	00003a06 	br	803cc34 <rt_lookup+0x10c>
+   {
+      if (rtp->ipRouteNextHop == 0L)   /* skip over empty entries */
+ 803cb4c:	e0bfff17 	ldw	r2,-4(fp)
+ 803cb50:	10800617 	ldw	r2,24(r2)
+ 803cb54:	10003326 	beq	r2,zero,803cc24 <rt_lookup+0xfc>
+#ifdef RIP_SUPPORT
+      /* skip RIP private entries */
+      if (rtp->ipRouteFlags & RIP_PRIVATE)
+         continue;
+#endif
+      entry_mask = rtp->ipRouteMask;
+ 803cb58:	e0bfff17 	ldw	r2,-4(fp)
+ 803cb5c:	10800a17 	ldw	r2,40(r2)
+ 803cb60:	e0bffb15 	stw	r2,-20(fp)
+      /* check to see if we have a match in the route table */
+      if ((rtp->ipRouteDest & entry_mask) == (host & entry_mask))
+ 803cb64:	e0bfff17 	ldw	r2,-4(fp)
+ 803cb68:	10c00017 	ldw	r3,0(r2)
+ 803cb6c:	e0bff917 	ldw	r2,-28(fp)
+ 803cb70:	1886f03a 	xor	r3,r3,r2
+ 803cb74:	e0bffb17 	ldw	r2,-20(fp)
+ 803cb78:	1884703a 	and	r2,r3,r2
+ 803cb7c:	10002a1e 	bne	r2,zero,803cc28 <rt_lookup+0x100>
+      {
+         /* check to see if current match is better than the previous best
+          * by computing the number of bits that matched */
+         for (curr_bits_matched = 0, bitcount_mask = 0x80000000; bitcount_mask > 0; bitcount_mask >>= 1)
+ 803cb80:	e03ffd85 	stb	zero,-10(fp)
+ 803cb84:	00a00034 	movhi	r2,32768
+ 803cb88:	e0bffc15 	stw	r2,-16(fp)
+ 803cb8c:	00001806 	br	803cbf0 <rt_lookup+0xc8>
+         {
+            extracted_bit = (ntohl(entry_mask)) & bitcount_mask;
+ 803cb90:	e0bffb17 	ldw	r2,-20(fp)
+ 803cb94:	1006d63a 	srli	r3,r2,24
+ 803cb98:	e0bffb17 	ldw	r2,-20(fp)
+ 803cb9c:	1004d23a 	srli	r2,r2,8
+ 803cba0:	10bfc00c 	andi	r2,r2,65280
+ 803cba4:	1886b03a 	or	r3,r3,r2
+ 803cba8:	e0bffb17 	ldw	r2,-20(fp)
+ 803cbac:	1004923a 	slli	r2,r2,8
+ 803cbb0:	10803fec 	andhi	r2,r2,255
+ 803cbb4:	1886b03a 	or	r3,r3,r2
+ 803cbb8:	e0bffb17 	ldw	r2,-20(fp)
+ 803cbbc:	1004963a 	slli	r2,r2,24
+ 803cbc0:	1884b03a 	or	r2,r3,r2
+ 803cbc4:	e0fffc17 	ldw	r3,-16(fp)
+ 803cbc8:	1884703a 	and	r2,r3,r2
+ 803cbcc:	e0bffa15 	stw	r2,-24(fp)
+            if (extracted_bit) ++curr_bits_matched;
+ 803cbd0:	e0bffa17 	ldw	r2,-24(fp)
+ 803cbd4:	10000326 	beq	r2,zero,803cbe4 <rt_lookup+0xbc>
+ 803cbd8:	e0bffd83 	ldbu	r2,-10(fp)
+ 803cbdc:	10800044 	addi	r2,r2,1
+ 803cbe0:	e0bffd85 	stb	r2,-10(fp)
+         for (curr_bits_matched = 0, bitcount_mask = 0x80000000; bitcount_mask > 0; bitcount_mask >>= 1)
+ 803cbe4:	e0bffc17 	ldw	r2,-16(fp)
+ 803cbe8:	1004d07a 	srli	r2,r2,1
+ 803cbec:	e0bffc15 	stw	r2,-16(fp)
+ 803cbf0:	e0bffc17 	ldw	r2,-16(fp)
+ 803cbf4:	103fe61e 	bne	r2,zero,803cb90 <rt_lookup+0x68>
+         }
+         if (curr_bits_matched > max_bits_matched)
+ 803cbf8:	e0bffd83 	ldbu	r2,-10(fp)
+ 803cbfc:	e0fffdc3 	ldbu	r3,-9(fp)
+ 803cc00:	1880092e 	bgeu	r3,r2,803cc28 <rt_lookup+0x100>
+         {
+            /* save a pointer to the best match */
+            max_bits_matched = curr_bits_matched;
+ 803cc04:	e0bffd83 	ldbu	r2,-10(fp)
+ 803cc08:	e0bffdc5 	stb	r2,-9(fp)
+            netmatch = rtp;
+ 803cc0c:	e0bfff17 	ldw	r2,-4(fp)
+ 803cc10:	e0bffe15 	stw	r2,-8(fp)
+            /* if all 32 bits match, stop searching the route table */
+            if (max_bits_matched == 32)
+ 803cc14:	e0bffdc3 	ldbu	r2,-9(fp)
+ 803cc18:	10800818 	cmpnei	r2,r2,32
+ 803cc1c:	10000c26 	beq	r2,zero,803cc50 <rt_lookup+0x128>
+ 803cc20:	00000106 	br	803cc28 <rt_lookup+0x100>
+         continue;
+ 803cc24:	0001883a 	nop
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803cc28:	e0bfff17 	ldw	r2,-4(fp)
+ 803cc2c:	10800f04 	addi	r2,r2,60
+ 803cc30:	e0bfff15 	stw	r2,-4(fp)
+ 803cc34:	d0e09517 	ldw	r3,-32172(gp)
+ 803cc38:	d0a03017 	ldw	r2,-32576(gp)
+ 803cc3c:	10800f24 	muli	r2,r2,60
+ 803cc40:	1885883a 	add	r2,r3,r2
+ 803cc44:	e0ffff17 	ldw	r3,-4(fp)
+ 803cc48:	18bfc036 	bltu	r3,r2,803cb4c <rt_lookup+0x24>
+ 803cc4c:	00000106 	br	803cc54 <rt_lookup+0x12c>
+               break;
+ 803cc50:	0001883a 	nop
+         }
+      }
+   }
+
+   if (netmatch)
+ 803cc54:	e0bffe17 	ldw	r2,-8(fp)
+ 803cc58:	10000326 	beq	r2,zero,803cc68 <rt_lookup+0x140>
+      netmatch->ipRouteAge = cticks;   /* timestamp entry we used */
+ 803cc5c:	d0e07d17 	ldw	r3,-32268(gp)
+ 803cc60:	e0bffe17 	ldw	r2,-8(fp)
+ 803cc64:	10c00915 	stw	r3,36(r2)
+
+   return netmatch;
+ 803cc68:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803cc6c:	e037883a 	mov	sp,fp
+ 803cc70:	df000017 	ldw	fp,0(sp)
+ 803cc74:	dec00104 	addi	sp,sp,4
+ 803cc78:	f800283a 	ret
+
+0803cc7c <add_route>:
+   ip_addr  dest,       /* ultimate destination */
+   ip_addr  mask,       /* net mask, 0xFFFFFFFF if dest is host address */
+   ip_addr  nexthop,    /* where to forward to */
+   int      iface,      /* interface (net) for nexthop */
+   int      prot)       /* how we know it: icmp, table, etc */
+{
+ 803cc7c:	defff704 	addi	sp,sp,-36
+ 803cc80:	dfc00815 	stw	ra,32(sp)
+ 803cc84:	df000715 	stw	fp,28(sp)
+ 803cc88:	df000704 	addi	fp,sp,28
+ 803cc8c:	e13ffc15 	stw	r4,-16(fp)
+ 803cc90:	e17ffb15 	stw	r5,-20(fp)
+ 803cc94:	e1bffa15 	stw	r6,-24(fp)
+ 803cc98:	e1fff915 	stw	r7,-28(fp)
+   RTMIB rtp;           /* scratch route table entrry pointer */
+   RTMIB newrt;         /* best entry for new route */
+   struct net * ifp;    /* interface (net) for nexthop */
+
+   newrt = NULL;     /* may be replaced with empty or more expendable entry */
+ 803cc9c:	e03ffe15 	stw	zero,-8(fp)
+					 
+   /* set the route interface pointer according to the index passed. This allows 
+    * the passed index to be used to access dynamic interfaces, which do not appear 
+    * in the nets[] array.
+    */
+   ifp = if_getbynum(iface);
+ 803cca0:	e13ff917 	ldw	r4,-28(fp)
+ 803cca4:	80240880 	call	8024088 <if_getbynum>
+ 803cca8:	e0bffd15 	stw	r2,-12(fp)
+   if(!ifp)
+ 803ccac:	e0bffd17 	ldw	r2,-12(fp)
+ 803ccb0:	1000021e 	bne	r2,zero,803ccbc <add_route+0x40>
+      return NULL;
+ 803ccb4:	0005883a 	mov	r2,zero
+ 803ccb8:	0000d406 	br	803d00c <add_route+0x390>
+
+   if (rt_mib == NULL)
+ 803ccbc:	d0a09517 	ldw	r2,-32172(gp)
+ 803ccc0:	1000021e 	bne	r2,zero,803cccc <add_route+0x50>
+      return NULL;
+ 803ccc4:	0005883a 	mov	r2,zero
+ 803ccc8:	0000d006 	br	803d00c <add_route+0x390>
+
+   /* Don't add null masks or IP addresses - they give false positives on
+    * net matches and don't belong here anyway.
+    */
+   if((dest == 0) || (mask == 0))
+ 803cccc:	e0bffc17 	ldw	r2,-16(fp)
+ 803ccd0:	10000226 	beq	r2,zero,803ccdc <add_route+0x60>
+ 803ccd4:	e0bffb17 	ldw	r2,-20(fp)
+ 803ccd8:	1000221e 	bne	r2,zero,803cd64 <add_route+0xe8>
+   {
+      dtrap();    /* bad configuration? */
+ 803ccdc:	8028cd40 	call	8028cd4 <dtrap>
+      dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n",
+	      htonl(dest), htonl(mask) );
+ 803cce0:	e0bffc17 	ldw	r2,-16(fp)
+ 803cce4:	1006d63a 	srli	r3,r2,24
+ 803cce8:	e0bffc17 	ldw	r2,-16(fp)
+ 803ccec:	1004d23a 	srli	r2,r2,8
+ 803ccf0:	10bfc00c 	andi	r2,r2,65280
+ 803ccf4:	1886b03a 	or	r3,r3,r2
+ 803ccf8:	e0bffc17 	ldw	r2,-16(fp)
+ 803ccfc:	1004923a 	slli	r2,r2,8
+ 803cd00:	10803fec 	andhi	r2,r2,255
+ 803cd04:	1886b03a 	or	r3,r3,r2
+ 803cd08:	e0bffc17 	ldw	r2,-16(fp)
+ 803cd0c:	1004963a 	slli	r2,r2,24
+      dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n",
+ 803cd10:	1888b03a 	or	r4,r3,r2
+	      htonl(dest), htonl(mask) );
+ 803cd14:	e0bffb17 	ldw	r2,-20(fp)
+ 803cd18:	1006d63a 	srli	r3,r2,24
+ 803cd1c:	e0bffb17 	ldw	r2,-20(fp)
+ 803cd20:	1004d23a 	srli	r2,r2,8
+ 803cd24:	10bfc00c 	andi	r2,r2,65280
+ 803cd28:	1886b03a 	or	r3,r3,r2
+ 803cd2c:	e0bffb17 	ldw	r2,-20(fp)
+ 803cd30:	1004923a 	slli	r2,r2,8
+ 803cd34:	10803fec 	andhi	r2,r2,255
+ 803cd38:	1886b03a 	or	r3,r3,r2
+ 803cd3c:	e0bffb17 	ldw	r2,-20(fp)
+ 803cd40:	1004963a 	slli	r2,r2,24
+      dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n",
+ 803cd44:	1884b03a 	or	r2,r3,r2
+ 803cd48:	100d883a 	mov	r6,r2
+ 803cd4c:	200b883a 	mov	r5,r4
+ 803cd50:	01020174 	movhi	r4,2053
+ 803cd54:	212ce604 	addi	r4,r4,-19560
+ 803cd58:	8002c780 	call	8002c78 <printf>
+      return NULL;
+ 803cd5c:	0005883a 	mov	r2,zero
+ 803cd60:	0000aa06 	br	803d00c <add_route+0x390>
+   }
+
+
+
+   /* if it's already in the route table, just update it. */
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803cd64:	d0a09517 	ldw	r2,-32172(gp)
+ 803cd68:	e0bfff15 	stw	r2,-4(fp)
+ 803cd6c:	00006406 	br	803cf00 <add_route+0x284>
+   {
+      if (rtp->ipRouteDest == dest) /* found existing entry for target */
+ 803cd70:	e0bfff17 	ldw	r2,-4(fp)
+ 803cd74:	10800017 	ldw	r2,0(r2)
+ 803cd78:	e0fffc17 	ldw	r3,-16(fp)
+ 803cd7c:	1880151e 	bne	r3,r2,803cdd4 <add_route+0x158>
+      {
+         rtp->ipRouteNextHop = nexthop;      /* fix entry */
+ 803cd80:	e0bfff17 	ldw	r2,-4(fp)
+ 803cd84:	e0fffa17 	ldw	r3,-24(fp)
+ 803cd88:	10c00615 	stw	r3,24(r2)
+         rtp->ipRouteAge = cticks;           /* timestamp it */
+ 803cd8c:	d0e07d17 	ldw	r3,-32268(gp)
+ 803cd90:	e0bfff17 	ldw	r2,-4(fp)
+ 803cd94:	10c00915 	stw	r3,36(r2)
+         /* set the rfc1213 1-based SNMP-ish interface index */
+         rtp->ipRouteIfIndex = (long)(iface) + 1;
+ 803cd98:	e0bff917 	ldw	r2,-28(fp)
+ 803cd9c:	10c00044 	addi	r3,r2,1
+ 803cda0:	e0bfff17 	ldw	r2,-4(fp)
+ 803cda4:	10c00115 	stw	r3,4(r2)
+         rtp->ipRouteProto = prot;           /* icmp, or whatever */
+ 803cda8:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdac:	e0c00217 	ldw	r3,8(fp)
+ 803cdb0:	10c00815 	stw	r3,32(r2)
+         rtp->ipRouteMask = mask;
+ 803cdb4:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdb8:	e0fffb17 	ldw	r3,-20(fp)
+ 803cdbc:	10c00a15 	stw	r3,40(r2)
+         rtp->ifp = ifp;
+ 803cdc0:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdc4:	e0fffd17 	ldw	r3,-12(fp)
+ 803cdc8:	10c00e15 	stw	r3,56(r2)
+         return(rtp);   /* just update and exit */
+ 803cdcc:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdd0:	00008e06 	br	803d00c <add_route+0x390>
+      }
+      /* if we didn't find empty slot yet, look for good slot to recycle */
+      if (!newrt || (newrt->ipRouteProto != 0))
+ 803cdd4:	e0bffe17 	ldw	r2,-8(fp)
+ 803cdd8:	10000326 	beq	r2,zero,803cde8 <add_route+0x16c>
+ 803cddc:	e0bffe17 	ldw	r2,-8(fp)
+ 803cde0:	10800817 	ldw	r2,32(r2)
+ 803cde4:	10004326 	beq	r2,zero,803cef4 <add_route+0x278>
+      {
+         if (!rtp->ipRouteNextHop)  /* found empty slot for use */
+ 803cde8:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdec:	10800617 	ldw	r2,24(r2)
+ 803cdf0:	1000051e 	bne	r2,zero,803ce08 <add_route+0x18c>
+         {
+            newrt = rtp;   /* record empty route for use */
+ 803cdf4:	e0bfff17 	ldw	r2,-4(fp)
+ 803cdf8:	e0bffe15 	stw	r2,-8(fp)
+            newrt->ipRouteProto = 0;
+ 803cdfc:	e0bffe17 	ldw	r2,-8(fp)
+ 803ce00:	10000815 	stw	zero,32(r2)
+            continue;
+ 803ce04:	00003b06 	br	803cef4 <add_route+0x278>
+         }
+         /* else see if the new route has higher priority than this slot: */
+         if (rtp_priority[prot] >= rtp_priority[rtp->ipRouteProto])
+ 803ce08:	e0c00217 	ldw	r3,8(fp)
+ 803ce0c:	00820174 	movhi	r2,2053
+ 803ce10:	1885883a 	add	r2,r3,r2
+ 803ce14:	11325603 	ldbu	r4,-13992(r2)
+ 803ce18:	e0bfff17 	ldw	r2,-4(fp)
+ 803ce1c:	10c00817 	ldw	r3,32(r2)
+ 803ce20:	00820174 	movhi	r2,2053
+ 803ce24:	1885883a 	add	r2,r3,r2
+ 803ce28:	10b25603 	ldbu	r2,-13992(r2)
+ 803ce2c:	20c03fcc 	andi	r3,r4,255
+ 803ce30:	10803fcc 	andi	r2,r2,255
+ 803ce34:	18802f36 	bltu	r3,r2,803cef4 <add_route+0x278>
+         {
+            if (!newrt)
+ 803ce38:	e0bffe17 	ldw	r2,-8(fp)
+ 803ce3c:	1000031e 	bne	r2,zero,803ce4c <add_route+0x1d0>
+            {
+               newrt = rtp;
+ 803ce40:	e0bfff17 	ldw	r2,-4(fp)
+ 803ce44:	e0bffe15 	stw	r2,-8(fp)
+               continue;
+ 803ce48:	00002a06 	br	803cef4 <add_route+0x278>
+            }
+
+            /* see if rtp is less important then newrtp */
+            if (rtp_priority[rtp->ipRouteProto] < 
+ 803ce4c:	e0bfff17 	ldw	r2,-4(fp)
+ 803ce50:	10c00817 	ldw	r3,32(r2)
+ 803ce54:	00820174 	movhi	r2,2053
+ 803ce58:	1885883a 	add	r2,r3,r2
+ 803ce5c:	11325603 	ldbu	r4,-13992(r2)
+                rtp_priority[newrt->ipRouteProto])
+ 803ce60:	e0bffe17 	ldw	r2,-8(fp)
+ 803ce64:	10c00817 	ldw	r3,32(r2)
+ 803ce68:	00820174 	movhi	r2,2053
+ 803ce6c:	1885883a 	add	r2,r3,r2
+ 803ce70:	10b25603 	ldbu	r2,-13992(r2)
+            if (rtp_priority[rtp->ipRouteProto] < 
+ 803ce74:	20c03fcc 	andi	r3,r4,255
+ 803ce78:	10803fcc 	andi	r2,r2,255
+ 803ce7c:	1880032e 	bgeu	r3,r2,803ce8c <add_route+0x210>
+            {
+               newrt = rtp;   /* save lower priority entry for recycle */
+ 803ce80:	e0bfff17 	ldw	r2,-4(fp)
+ 803ce84:	e0bffe15 	stw	r2,-8(fp)
+ 803ce88:	00001a06 	br	803cef4 <add_route+0x278>
+            }
+            else if(rtp_priority[rtp->ipRouteProto] == 
+ 803ce8c:	e0bfff17 	ldw	r2,-4(fp)
+ 803ce90:	10c00817 	ldw	r3,32(r2)
+ 803ce94:	00820174 	movhi	r2,2053
+ 803ce98:	1885883a 	add	r2,r3,r2
+ 803ce9c:	11325603 	ldbu	r4,-13992(r2)
+                rtp_priority[newrt->ipRouteProto])
+ 803cea0:	e0bffe17 	ldw	r2,-8(fp)
+ 803cea4:	10c00817 	ldw	r3,32(r2)
+ 803cea8:	00820174 	movhi	r2,2053
+ 803ceac:	1885883a 	add	r2,r3,r2
+ 803ceb0:	10b25603 	ldbu	r2,-13992(r2)
+            else if(rtp_priority[rtp->ipRouteProto] == 
+ 803ceb4:	20c03fcc 	andi	r3,r4,255
+ 803ceb8:	10803fcc 	andi	r2,r2,255
+ 803cebc:	18800d1e 	bne	r3,r2,803cef4 <add_route+0x278>
+            {
+               /* if equal priority, keep the older entry for deletion */
+               if (c_older(rtp->ipRouteAge, newrt->ipRouteAge) == rtp->ipRouteAge)
+ 803cec0:	e0bfff17 	ldw	r2,-4(fp)
+ 803cec4:	10c00917 	ldw	r3,36(r2)
+ 803cec8:	e0bffe17 	ldw	r2,-8(fp)
+ 803cecc:	10800917 	ldw	r2,36(r2)
+ 803ced0:	100b883a 	mov	r5,r2
+ 803ced4:	1809883a 	mov	r4,r3
+ 803ced8:	8024d640 	call	8024d64 <c_older>
+ 803cedc:	1007883a 	mov	r3,r2
+ 803cee0:	e0bfff17 	ldw	r2,-4(fp)
+ 803cee4:	10800917 	ldw	r2,36(r2)
+ 803cee8:	1880021e 	bne	r3,r2,803cef4 <add_route+0x278>
+                  newrt = rtp;   /* got an older one */
+ 803ceec:	e0bfff17 	ldw	r2,-4(fp)
+ 803cef0:	e0bffe15 	stw	r2,-8(fp)
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803cef4:	e0bfff17 	ldw	r2,-4(fp)
+ 803cef8:	10800f04 	addi	r2,r2,60
+ 803cefc:	e0bfff15 	stw	r2,-4(fp)
+ 803cf00:	d0e09517 	ldw	r3,-32172(gp)
+ 803cf04:	d0a03017 	ldw	r2,-32576(gp)
+ 803cf08:	10800f24 	muli	r2,r2,60
+ 803cf0c:	1885883a 	add	r2,r3,r2
+ 803cf10:	e0ffff17 	ldw	r3,-4(fp)
+ 803cf14:	18bf9636 	bltu	r3,r2,803cd70 <add_route+0xf4>
+         }
+      }
+   }
+
+   /* fall to here if not in table: create a new route */
+   if (newrt)  /* did we find an empty or lower priority route entry? */
+ 803cf18:	e0bffe17 	ldw	r2,-8(fp)
+ 803cf1c:	10002826 	beq	r2,zero,803cfc0 <add_route+0x344>
+      rtp = newrt;   /* create new entry in lowest priority slot */
+ 803cf20:	e0bffe17 	ldw	r2,-8(fp)
+ 803cf24:	e0bfff15 	stw	r2,-4(fp)
+   else  /* all slots have higher priority, new entry looses */
+      return NULL;
+
+   /* set default value in new route entry, caller can modiy further. */
+   rtp->ifp = ifp;
+ 803cf28:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf2c:	e0fffd17 	ldw	r3,-12(fp)
+ 803cf30:	10c00e15 	stw	r3,56(r2)
+   rtp->ipRouteDest = dest;
+ 803cf34:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf38:	e0fffc17 	ldw	r3,-16(fp)
+ 803cf3c:	10c00015 	stw	r3,0(r2)
+   rtp->ipRouteIfIndex = (long)(if_netnumber(ifp)) + 1; /* set interface number */
+ 803cf40:	e13ffd17 	ldw	r4,-12(fp)
+ 803cf44:	80252fc0 	call	80252fc <if_netnumber>
+ 803cf48:	10c00044 	addi	r3,r2,1
+ 803cf4c:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf50:	10c00115 	stw	r3,4(r2)
+   rtp->ipRouteMetric1 = ip_mib.ipDefaultTTL;
+ 803cf54:	008201b4 	movhi	r2,2054
+ 803cf58:	10b95017 	ldw	r2,-6848(r2)
+ 803cf5c:	1007883a 	mov	r3,r2
+ 803cf60:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf64:	10c00215 	stw	r3,8(r2)
+   rtp->ipRouteMetric2 = -1;
+ 803cf68:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf6c:	00ffffc4 	movi	r3,-1
+ 803cf70:	10c00315 	stw	r3,12(r2)
+   rtp->ipRouteMetric3 = -1;
+ 803cf74:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf78:	00ffffc4 	movi	r3,-1
+ 803cf7c:	10c00415 	stw	r3,16(r2)
+   rtp->ipRouteMetric4 = -1;
+ 803cf80:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf84:	00ffffc4 	movi	r3,-1
+ 803cf88:	10c00515 	stw	r3,20(r2)
+   rtp->ipRouteNextHop = nexthop;
+ 803cf8c:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf90:	e0fffa17 	ldw	r3,-24(fp)
+ 803cf94:	10c00615 	stw	r3,24(r2)
+   rtp->ipRouteProto = prot;                 /* icmp, or whatever */
+ 803cf98:	e0bfff17 	ldw	r2,-4(fp)
+ 803cf9c:	e0c00217 	ldw	r3,8(fp)
+ 803cfa0:	10c00815 	stw	r3,32(r2)
+
+   if ((dest & mask) == (nexthop & mask))
+ 803cfa4:	e0fffc17 	ldw	r3,-16(fp)
+ 803cfa8:	e0bffa17 	ldw	r2,-24(fp)
+ 803cfac:	1886f03a 	xor	r3,r3,r2
+ 803cfb0:	e0bffb17 	ldw	r2,-20(fp)
+ 803cfb4:	1884703a 	and	r2,r3,r2
+ 803cfb8:	1000071e 	bne	r2,zero,803cfd8 <add_route+0x35c>
+ 803cfbc:	00000206 	br	803cfc8 <add_route+0x34c>
+      return NULL;
+ 803cfc0:	0005883a 	mov	r2,zero
+ 803cfc4:	00001106 	br	803d00c <add_route+0x390>
+      rtp->ipRouteType = IPRT_DIRECT;
+ 803cfc8:	e0bfff17 	ldw	r2,-4(fp)
+ 803cfcc:	00c000c4 	movi	r3,3
+ 803cfd0:	10c00715 	stw	r3,28(r2)
+ 803cfd4:	00000306 	br	803cfe4 <add_route+0x368>
+   else
+      rtp->ipRouteType = IPRT_INDIRECT;
+ 803cfd8:	e0bfff17 	ldw	r2,-4(fp)
+ 803cfdc:	00c00104 	movi	r3,4
+ 803cfe0:	10c00715 	stw	r3,28(r2)
+
+   rtp->ipRouteAge = cticks;        /* timestamp it */
+ 803cfe4:	d0e07d17 	ldw	r3,-32268(gp)
+ 803cfe8:	e0bfff17 	ldw	r2,-4(fp)
+ 803cfec:	10c00915 	stw	r3,36(r2)
+   rtp->ipRouteMask = mask;
+ 803cff0:	e0bfff17 	ldw	r2,-4(fp)
+ 803cff4:	e0fffb17 	ldw	r3,-20(fp)
+ 803cff8:	10c00a15 	stw	r3,40(r2)
+   rtp->ipRouteMetric5 = -1;
+ 803cffc:	e0bfff17 	ldw	r2,-4(fp)
+ 803d000:	00ffffc4 	movi	r3,-1
+ 803d004:	10c00b15 	stw	r3,44(r2)
+   return(rtp);
+ 803d008:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803d00c:	e037883a 	mov	sp,fp
+ 803d010:	dfc00117 	ldw	ra,4(sp)
+ 803d014:	df000017 	ldw	fp,0(sp)
+ 803d018:	dec00204 	addi	sp,sp,8
+ 803d01c:	f800283a 	ret
+
+0803d020 <del_route>:
+ * RETURNS: Returns number of route table entries deleted. 
+ */
+
+int
+del_route(ip_addr dest, ip_addr mask, int iface)
+{
+ 803d020:	defff804 	addi	sp,sp,-32
+ 803d024:	dfc00715 	stw	ra,28(sp)
+ 803d028:	df000615 	stw	fp,24(sp)
+ 803d02c:	df000604 	addi	fp,sp,24
+ 803d030:	e13ffc15 	stw	r4,-16(fp)
+ 803d034:	e17ffb15 	stw	r5,-20(fp)
+ 803d038:	e1bffa15 	stw	r6,-24(fp)
+   RTMIB rtp;
+   int   retval   =  0;
+ 803d03c:	e03ffe15 	stw	zero,-8(fp)
+
+   /* set the route interface pointer according to the index passed. This allows 
+    * the passed index to be used to access dynamic interfaces, which do not appear 
+    * in the nets[] array.
+    */
+   if(iface == -1)
+ 803d040:	e0bffa17 	ldw	r2,-24(fp)
+ 803d044:	10bfffd8 	cmpnei	r2,r2,-1
+ 803d048:	1000021e 	bne	r2,zero,803d054 <del_route+0x34>
+      ifp = NULL;    /* wildcard */
+ 803d04c:	e03ffd15 	stw	zero,-12(fp)
+ 803d050:	00000306 	br	803d060 <del_route+0x40>
+   else
+      ifp = if_getbynum(iface);
+ 803d054:	e13ffa17 	ldw	r4,-24(fp)
+ 803d058:	80240880 	call	8024088 <if_getbynum>
+ 803d05c:	e0bffd15 	stw	r2,-12(fp)
+
+   if (rt_mib == NULL)     /* Make sure we're up */
+ 803d060:	d0a09517 	ldw	r2,-32172(gp)
+ 803d064:	1000021e 	bne	r2,zero,803d070 <del_route+0x50>
+      return 0;
+ 803d068:	0005883a 	mov	r2,zero
+ 803d06c:	00002c06 	br	803d120 <del_route+0x100>
+
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803d070:	d0a09517 	ldw	r2,-32172(gp)
+ 803d074:	e0bfff15 	stw	r2,-4(fp)
+ 803d078:	00002206 	br	803d104 <del_route+0xe4>
+   {
+      if (!rtp->ipRouteNextHop)  /* empty slot */
+ 803d07c:	e0bfff17 	ldw	r2,-4(fp)
+ 803d080:	10800617 	ldw	r2,24(r2)
+ 803d084:	10001926 	beq	r2,zero,803d0ec <del_route+0xcc>
+         continue;
+      if(ifp != NULL && ifp != rtp->ifp)
+ 803d088:	e0bffd17 	ldw	r2,-12(fp)
+ 803d08c:	10000426 	beq	r2,zero,803d0a0 <del_route+0x80>
+ 803d090:	e0bfff17 	ldw	r2,-4(fp)
+ 803d094:	10800e17 	ldw	r2,56(r2)
+ 803d098:	e0fffd17 	ldw	r3,-12(fp)
+ 803d09c:	1880151e 	bne	r3,r2,803d0f4 <del_route+0xd4>
+         continue;   /* interface didn't match */
+      if ((rtp->ipRouteDest & mask) == (dest & mask))
+ 803d0a0:	e0bfff17 	ldw	r2,-4(fp)
+ 803d0a4:	10c00017 	ldw	r3,0(r2)
+ 803d0a8:	e0bffc17 	ldw	r2,-16(fp)
+ 803d0ac:	1886f03a 	xor	r3,r3,r2
+ 803d0b0:	e0bffb17 	ldw	r2,-20(fp)
+ 803d0b4:	1884703a 	and	r2,r3,r2
+ 803d0b8:	1000071e 	bne	r2,zero,803d0d8 <del_route+0xb8>
+      {
+         MEMSET(rtp, 0, sizeof(*rtp)); /* clear entry */
+ 803d0bc:	01800f04 	movi	r6,60
+ 803d0c0:	000b883a 	mov	r5,zero
+ 803d0c4:	e13fff17 	ldw	r4,-4(fp)
+ 803d0c8:	80088e40 	call	80088e4 <memset>
+         retval++;
+ 803d0cc:	e0bffe17 	ldw	r2,-8(fp)
+ 803d0d0:	10800044 	addi	r2,r2,1
+ 803d0d4:	e0bffe15 	stw	r2,-8(fp)
+      }
+      if (cachedRoute == rtp) /* clear cache if it's being deleted */
+ 803d0d8:	d0a09c17 	ldw	r2,-32144(gp)
+ 803d0dc:	e0ffff17 	ldw	r3,-4(fp)
+ 803d0e0:	1880051e 	bne	r3,r2,803d0f8 <del_route+0xd8>
+         cachedRoute = NULL;
+ 803d0e4:	d0209c15 	stw	zero,-32144(gp)
+ 803d0e8:	00000306 	br	803d0f8 <del_route+0xd8>
+         continue;
+ 803d0ec:	0001883a 	nop
+ 803d0f0:	00000106 	br	803d0f8 <del_route+0xd8>
+         continue;   /* interface didn't match */
+ 803d0f4:	0001883a 	nop
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+ 803d0f8:	e0bfff17 	ldw	r2,-4(fp)
+ 803d0fc:	10800f04 	addi	r2,r2,60
+ 803d100:	e0bfff15 	stw	r2,-4(fp)
+ 803d104:	d0e09517 	ldw	r3,-32172(gp)
+ 803d108:	d0a03017 	ldw	r2,-32576(gp)
+ 803d10c:	10800f24 	muli	r2,r2,60
+ 803d110:	1885883a 	add	r2,r3,r2
+ 803d114:	e0ffff17 	ldw	r3,-4(fp)
+ 803d118:	18bfd836 	bltu	r3,r2,803d07c <del_route+0x5c>
+   }
+   return retval;
+ 803d11c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803d120:	e037883a 	mov	sp,fp
+ 803d124:	dfc00117 	ldw	ra,4(sp)
+ 803d128:	df000017 	ldw	fp,0(sp)
+ 803d12c:	dec00204 	addi	sp,sp,8
+ 803d130:	f800283a 	ret
+
+0803d134 <udpdemux>:
+ * RETURNS: 0 if OK or ENP error code
+ */
+
+int
+udpdemux(PACKET p)
+{
+ 803d134:	deffec04 	addi	sp,sp,-80
+ 803d138:	dfc01315 	stw	ra,76(sp)
+ 803d13c:	df001215 	stw	fp,72(sp)
+ 803d140:	df001204 	addi	fp,sp,72
+ 803d144:	e13ff215 	stw	r4,-56(fp)
+   unsigned short osum, xsum; /* scratch checksum holders */
+   unsigned plen; /* packet length */
+   int   e;    /* general error holder */
+
+   /* First let's verify that it's a valid UDP packet. */
+   pip = ip_head(p);       /* we'll need IP header info */
+ 803d148:	e0bff217 	ldw	r2,-56(fp)
+ 803d14c:	10800317 	ldw	r2,12(r2)
+ 803d150:	e0bffb15 	stw	r2,-20(fp)
+   pup = (struct udp*)ip_data(pip);   /*  also need UDP header */
+ 803d154:	e0bffb17 	ldw	r2,-20(fp)
+ 803d158:	10800003 	ldbu	r2,0(r2)
+ 803d15c:	10803fcc 	andi	r2,r2,255
+ 803d160:	100490ba 	slli	r2,r2,2
+ 803d164:	10800f0c 	andi	r2,r2,60
+ 803d168:	e0fffb17 	ldw	r3,-20(fp)
+ 803d16c:	1885883a 	add	r2,r3,r2
+ 803d170:	e0bffa15 	stw	r2,-24(fp)
+   plen = htons(pup->ud_len);
+ 803d174:	e0bffa17 	ldw	r2,-24(fp)
+ 803d178:	1080010b 	ldhu	r2,4(r2)
+ 803d17c:	10bfffcc 	andi	r2,r2,65535
+ 803d180:	1004d23a 	srli	r2,r2,8
+ 803d184:	10bfffcc 	andi	r2,r2,65535
+ 803d188:	10c03fcc 	andi	r3,r2,255
+ 803d18c:	e0bffa17 	ldw	r2,-24(fp)
+ 803d190:	1080010b 	ldhu	r2,4(r2)
+ 803d194:	10bfffcc 	andi	r2,r2,65535
+ 803d198:	1004923a 	slli	r2,r2,8
+ 803d19c:	10bfffcc 	andi	r2,r2,65535
+ 803d1a0:	1884b03a 	or	r2,r3,r2
+ 803d1a4:	e0bff915 	stw	r2,-28(fp)
+
+   if (plen > p->nb_plen)
+ 803d1a8:	e0bff217 	ldw	r2,-56(fp)
+ 803d1ac:	10c00417 	ldw	r3,16(r2)
+ 803d1b0:	e0bff917 	ldw	r2,-28(fp)
+ 803d1b4:	1880232e 	bgeu	r3,r2,803d244 <udpdemux+0x110>
+#ifdef   NPDEBUG
+/* 
+ * Altera Niche Stack Nios port modification:
+ * cast arg to unsigned long to remove build warning
+ */
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+ 803d1b8:	d0a06617 	ldw	r2,-32360(gp)
+ 803d1bc:	1081000c 	andi	r2,r2,1024
+ 803d1c0:	10001726 	beq	r2,zero,803d220 <udpdemux+0xec>
+ 803d1c4:	d0a06617 	ldw	r2,-32360(gp)
+ 803d1c8:	1080400c 	andi	r2,r2,256
+ 803d1cc:	10001426 	beq	r2,zero,803d220 <udpdemux+0xec>
+         dprintf("UDP: bad len pkt: rcvd: %u, hdr: %u.\n",
+ 803d1d0:	e0bff217 	ldw	r2,-56(fp)
+ 803d1d4:	11000417 	ldw	r4,16(r2)
+                 p->nb_plen, (unsigned int)(htons(pup->ud_len) + UDPLEN));
+ 803d1d8:	e0bffa17 	ldw	r2,-24(fp)
+ 803d1dc:	1080010b 	ldhu	r2,4(r2)
+ 803d1e0:	10bfffcc 	andi	r2,r2,65535
+ 803d1e4:	1004d23a 	srli	r2,r2,8
+ 803d1e8:	10bfffcc 	andi	r2,r2,65535
+ 803d1ec:	10c03fcc 	andi	r3,r2,255
+ 803d1f0:	e0bffa17 	ldw	r2,-24(fp)
+ 803d1f4:	1080010b 	ldhu	r2,4(r2)
+ 803d1f8:	10bfffcc 	andi	r2,r2,65535
+ 803d1fc:	1004923a 	slli	r2,r2,8
+ 803d200:	10bfffcc 	andi	r2,r2,65535
+ 803d204:	1884b03a 	or	r2,r3,r2
+         dprintf("UDP: bad len pkt: rcvd: %u, hdr: %u.\n",
+ 803d208:	10800204 	addi	r2,r2,8
+ 803d20c:	100d883a 	mov	r6,r2
+ 803d210:	200b883a 	mov	r5,r4
+ 803d214:	01020174 	movhi	r4,2053
+ 803d218:	212cf404 	addi	r4,r4,-19504
+ 803d21c:	8002c780 	call	8002c78 <printf>
+#endif
+      udp_mib.udpInErrors++;
+ 803d220:	008201b4 	movhi	r2,2054
+ 803d224:	10b96517 	ldw	r2,-6764(r2)
+ 803d228:	10c00044 	addi	r3,r2,1
+ 803d22c:	008201b4 	movhi	r2,2054
+ 803d230:	10f96515 	stw	r3,-6764(r2)
+      udp_free(p);
+ 803d234:	e13ff217 	ldw	r4,-56(fp)
+ 803d238:	803ddb80 	call	803ddb8 <udp_free>
+      return ENP_BAD_HEADER;
+ 803d23c:	00bff804 	movi	r2,-32
+ 803d240:	00019206 	br	803d88c <udpdemux+0x758>
+   }
+
+   osum = pup->ud_cksum;
+ 803d244:	e0bffa17 	ldw	r2,-24(fp)
+ 803d248:	1080018b 	ldhu	r2,6(r2)
+ 803d24c:	e0bff88d 	sth	r2,-30(fp)
+   /* did other guy use checksumming? */
+   if (osum)
+ 803d250:	e0bff88b 	ldhu	r2,-30(fp)
+ 803d254:	10005626 	beq	r2,zero,803d3b0 <udpdemux+0x27c>
+   {
+      if (plen & 1) ((char *)pup)[plen] = 0;
+ 803d258:	e0bff917 	ldw	r2,-28(fp)
+ 803d25c:	1080004c 	andi	r2,r2,1
+ 803d260:	10000426 	beq	r2,zero,803d274 <udpdemux+0x140>
+ 803d264:	e0fffa17 	ldw	r3,-24(fp)
+ 803d268:	e0bff917 	ldw	r2,-28(fp)
+ 803d26c:	1885883a 	add	r2,r3,r2
+ 803d270:	10000005 	stb	zero,0(r2)
+         php.ph_src = p->fhost;
+ 803d274:	e0bff217 	ldw	r2,-56(fp)
+ 803d278:	10800717 	ldw	r2,28(r2)
+ 803d27c:	e0bff315 	stw	r2,-52(fp)
+      php.ph_dest = pip->ip_dest;
+ 803d280:	e0bffb17 	ldw	r2,-20(fp)
+ 803d284:	10800417 	ldw	r2,16(r2)
+ 803d288:	e0bff415 	stw	r2,-48(fp)
+      php.ph_zero = 0;
+ 803d28c:	e03ff505 	stb	zero,-44(fp)
+      php.ph_prot = UDP_PROT;
+ 803d290:	00800444 	movi	r2,17
+ 803d294:	e0bff545 	stb	r2,-43(fp)
+      php.ph_len  = pup->ud_len;
+ 803d298:	e0bffa17 	ldw	r2,-24(fp)
+ 803d29c:	1080010b 	ldhu	r2,4(r2)
+ 803d2a0:	e0bff58d 	sth	r2,-42(fp)
+
+      pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1);
+ 803d2a4:	e0bff304 	addi	r2,fp,-52
+ 803d2a8:	01400184 	movi	r5,6
+ 803d2ac:	1009883a 	mov	r4,r2
+ 803d2b0:	8026d7c0 	call	8026d7c <cksum>
+ 803d2b4:	1007883a 	mov	r3,r2
+ 803d2b8:	e0bffa17 	ldw	r2,-24(fp)
+ 803d2bc:	10c0018d 	sth	r3,6(r2)
+      xsum = ~cksum(pup, (plen+1)>>1);
+ 803d2c0:	e0bff917 	ldw	r2,-28(fp)
+ 803d2c4:	10800044 	addi	r2,r2,1
+ 803d2c8:	1004d07a 	srli	r2,r2,1
+ 803d2cc:	100b883a 	mov	r5,r2
+ 803d2d0:	e13ffa17 	ldw	r4,-24(fp)
+ 803d2d4:	8026d7c0 	call	8026d7c <cksum>
+ 803d2d8:	0084303a 	nor	r2,zero,r2
+ 803d2dc:	e0bffe8d 	sth	r2,-6(fp)
+      if (!xsum)
+ 803d2e0:	e0bffe8b 	ldhu	r2,-6(fp)
+ 803d2e4:	1000021e 	bne	r2,zero,803d2f0 <udpdemux+0x1bc>
+         xsum = 0xffff;
+ 803d2e8:	00bfffc4 	movi	r2,-1
+ 803d2ec:	e0bffe8d 	sth	r2,-6(fp)
+      pup->ud_cksum = osum;
+ 803d2f0:	e0bffa17 	ldw	r2,-24(fp)
+ 803d2f4:	e0fff88b 	ldhu	r3,-30(fp)
+ 803d2f8:	10c0018d 	sth	r3,6(r2)
+      if (xsum != osum)
+ 803d2fc:	e0fffe8b 	ldhu	r3,-6(fp)
+ 803d300:	e0bff88b 	ldhu	r2,-30(fp)
+ 803d304:	18802a26 	beq	r3,r2,803d3b0 <udpdemux+0x27c>
+      {
+#ifdef   NPDEBUG
+         if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+ 803d308:	d0a06617 	ldw	r2,-32360(gp)
+ 803d30c:	1081000c 	andi	r2,r2,1024
+ 803d310:	10001e26 	beq	r2,zero,803d38c <udpdemux+0x258>
+ 803d314:	d0a06617 	ldw	r2,-32360(gp)
+ 803d318:	1080400c 	andi	r2,r2,256
+ 803d31c:	10001b26 	beq	r2,zero,803d38c <udpdemux+0x258>
+         {
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+ 803d320:	e17ff88b 	ldhu	r5,-30(fp)
+ 803d324:	e1bffe8b 	ldhu	r6,-6(fp)
+                    osum, xsum, PUSH_IPADDR(p->fhost));
+ 803d328:	e0bff217 	ldw	r2,-56(fp)
+ 803d32c:	10800717 	ldw	r2,28(r2)
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+ 803d330:	11c03fcc 	andi	r7,r2,255
+                    osum, xsum, PUSH_IPADDR(p->fhost));
+ 803d334:	e0bff217 	ldw	r2,-56(fp)
+ 803d338:	10800717 	ldw	r2,28(r2)
+ 803d33c:	1004d23a 	srli	r2,r2,8
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+ 803d340:	10803fcc 	andi	r2,r2,255
+                    osum, xsum, PUSH_IPADDR(p->fhost));
+ 803d344:	e0fff217 	ldw	r3,-56(fp)
+ 803d348:	18c00717 	ldw	r3,28(r3)
+ 803d34c:	1806d43a 	srli	r3,r3,16
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+ 803d350:	18c03fcc 	andi	r3,r3,255
+                    osum, xsum, PUSH_IPADDR(p->fhost));
+ 803d354:	e13ff217 	ldw	r4,-56(fp)
+ 803d358:	21000717 	ldw	r4,28(r4)
+ 803d35c:	2008d63a 	srli	r4,r4,24
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+ 803d360:	d9000215 	stw	r4,8(sp)
+ 803d364:	d8c00115 	stw	r3,4(sp)
+ 803d368:	d8800015 	stw	r2,0(sp)
+ 803d36c:	01020174 	movhi	r4,2053
+ 803d370:	212cfe04 	addi	r4,r4,-19464
+ 803d374:	8002c780 	call	8002c78 <printf>
+            if (NDEBUG & DUMP)
+ 803d378:	d0a06617 	ldw	r2,-32360(gp)
+ 803d37c:	1080008c 	andi	r2,r2,2
+ 803d380:	10000226 	beq	r2,zero,803d38c <udpdemux+0x258>
+               ip_dump(p);
+ 803d384:	e13ff217 	ldw	r4,-56(fp)
+ 803d388:	803b0cc0 	call	803b0cc <ip_dump>
+         }
+#endif
+         udp_mib.udpInErrors++;
+ 803d38c:	008201b4 	movhi	r2,2054
+ 803d390:	10b96517 	ldw	r2,-6764(r2)
+ 803d394:	10c00044 	addi	r3,r2,1
+ 803d398:	008201b4 	movhi	r2,2054
+ 803d39c:	10f96515 	stw	r3,-6764(r2)
+         udp_free(p);
+ 803d3a0:	e13ff217 	ldw	r4,-56(fp)
+ 803d3a4:	803ddb80 	call	803ddb8 <udp_free>
+         return ENP_BAD_HEADER;
+ 803d3a8:	00bff804 	movi	r2,-32
+ 803d3ac:	00013706 	br	803d88c <udpdemux+0x758>
+      }
+   }
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+ 803d3b0:	e13ffa17 	ldw	r4,-24(fp)
+ 803d3b4:	803db340 	call	803db34 <udpswap>
+#endif
+
+   /* Prior to upcall, adjust nb_prot for size of IP and UDP headers */
+   e = (sizeof(struct udp) + ip_hlen(pip));
+ 803d3b8:	e0bffb17 	ldw	r2,-20(fp)
+ 803d3bc:	10800003 	ldbu	r2,0(r2)
+ 803d3c0:	10803fcc 	andi	r2,r2,255
+ 803d3c4:	100490ba 	slli	r2,r2,2
+ 803d3c8:	10800f0c 	andi	r2,r2,60
+ 803d3cc:	10800204 	addi	r2,r2,8
+ 803d3d0:	e0bffd15 	stw	r2,-12(fp)
+   p->nb_plen -= e;
+ 803d3d4:	e0bff217 	ldw	r2,-56(fp)
+ 803d3d8:	10c00417 	ldw	r3,16(r2)
+ 803d3dc:	e0bffd17 	ldw	r2,-12(fp)
+ 803d3e0:	1887c83a 	sub	r3,r3,r2
+ 803d3e4:	e0bff217 	ldw	r2,-56(fp)
+ 803d3e8:	10c00415 	stw	r3,16(r2)
+   p->nb_prot += e;
+ 803d3ec:	e0bff217 	ldw	r2,-56(fp)
+ 803d3f0:	10c00317 	ldw	r3,12(r2)
+ 803d3f4:	e0bffd17 	ldw	r2,-12(fp)
+ 803d3f8:	1887883a 	add	r3,r3,r2
+ 803d3fc:	e0bff217 	ldw	r2,-56(fp)
+ 803d400:	10c00315 	stw	r3,12(r2)
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+ 803d404:	d0a06617 	ldw	r2,-32360(gp)
+ 803d408:	1081000c 	andi	r2,r2,1024
+ 803d40c:	10001f26 	beq	r2,zero,803d48c <udpdemux+0x358>
+ 803d410:	d0a06617 	ldw	r2,-32360(gp)
+ 803d414:	1080400c 	andi	r2,r2,256
+ 803d418:	10001c26 	beq	r2,zero,803d48c <udpdemux+0x358>
+   {
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+ 803d41c:	e0bff217 	ldw	r2,-56(fp)
+ 803d420:	10800717 	ldw	r2,28(r2)
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+ 803d424:	11803fcc 	andi	r6,r2,255
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+ 803d428:	e0bff217 	ldw	r2,-56(fp)
+ 803d42c:	10800717 	ldw	r2,28(r2)
+ 803d430:	1004d23a 	srli	r2,r2,8
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+ 803d434:	11c03fcc 	andi	r7,r2,255
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+ 803d438:	e0bff217 	ldw	r2,-56(fp)
+ 803d43c:	10800717 	ldw	r2,28(r2)
+ 803d440:	1004d43a 	srli	r2,r2,16
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+ 803d444:	10803fcc 	andi	r2,r2,255
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+ 803d448:	e0fff217 	ldw	r3,-56(fp)
+ 803d44c:	18c00717 	ldw	r3,28(r3)
+ 803d450:	1806d63a 	srli	r3,r3,24
+ 803d454:	e13ffa17 	ldw	r4,-24(fp)
+ 803d458:	2100000b 	ldhu	r4,0(r4)
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+ 803d45c:	213fffcc 	andi	r4,r4,65535
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+ 803d460:	e17ffa17 	ldw	r5,-24(fp)
+ 803d464:	2940008b 	ldhu	r5,2(r5)
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+ 803d468:	297fffcc 	andi	r5,r5,65535
+ 803d46c:	d9400315 	stw	r5,12(sp)
+ 803d470:	d9000215 	stw	r4,8(sp)
+ 803d474:	d8c00115 	stw	r3,4(sp)
+ 803d478:	d8800015 	stw	r2,0(sp)
+ 803d47c:	e17ff917 	ldw	r5,-28(fp)
+ 803d480:	01020174 	movhi	r4,2053
+ 803d484:	212d0c04 	addi	r4,r4,-19408
+ 803d488:	8002c780 	call	8002c78 <printf>
+#endif   /* INCLUDE_SNMPV3 */
+#endif   /* PREBIND_AGENT */
+
+   /* run through the demux table and try to upcall it */
+
+   for (con = firstudp; con; con = con->u_next)
+ 803d48c:	d0a09e17 	ldw	r2,-32136(gp)
+ 803d490:	e0bfff15 	stw	r2,-4(fp)
+ 803d494:	0000aa06 	br	803d740 <udpdemux+0x60c>
+         continue;
+#endif
+
+      /* enforce all three aspects of tuple matching. Old code
+      assumed lport was unique, which is not always so. */
+      if (con->u_lport && (con->u_lport != pup->ud_dstp))
+ 803d498:	e0bfff17 	ldw	r2,-4(fp)
+ 803d49c:	1080018b 	ldhu	r2,6(r2)
+ 803d4a0:	10bfffcc 	andi	r2,r2,65535
+ 803d4a4:	10000726 	beq	r2,zero,803d4c4 <udpdemux+0x390>
+ 803d4a8:	e0bfff17 	ldw	r2,-4(fp)
+ 803d4ac:	10c0018b 	ldhu	r3,6(r2)
+ 803d4b0:	e0bffa17 	ldw	r2,-24(fp)
+ 803d4b4:	1080008b 	ldhu	r2,2(r2)
+ 803d4b8:	18ffffcc 	andi	r3,r3,65535
+ 803d4bc:	10bfffcc 	andi	r2,r2,65535
+ 803d4c0:	1880951e 	bne	r3,r2,803d718 <udpdemux+0x5e4>
+         continue;
+      if (con->u_fport && (con->u_fport != pup->ud_srcp))
+ 803d4c4:	e0bfff17 	ldw	r2,-4(fp)
+ 803d4c8:	1080020b 	ldhu	r2,8(r2)
+ 803d4cc:	10bfffcc 	andi	r2,r2,65535
+ 803d4d0:	10000726 	beq	r2,zero,803d4f0 <udpdemux+0x3bc>
+ 803d4d4:	e0bfff17 	ldw	r2,-4(fp)
+ 803d4d8:	10c0020b 	ldhu	r3,8(r2)
+ 803d4dc:	e0bffa17 	ldw	r2,-24(fp)
+ 803d4e0:	1080000b 	ldhu	r2,0(r2)
+ 803d4e4:	18ffffcc 	andi	r3,r3,65535
+ 803d4e8:	10bfffcc 	andi	r2,r2,65535
+ 803d4ec:	18808c1e 	bne	r3,r2,803d720 <udpdemux+0x5ec>
+         continue;
+      if (con->u_fhost && (con->u_fhost != p->fhost))
+ 803d4f0:	e0bfff17 	ldw	r2,-4(fp)
+ 803d4f4:	10800417 	ldw	r2,16(r2)
+ 803d4f8:	10000526 	beq	r2,zero,803d510 <udpdemux+0x3dc>
+ 803d4fc:	e0bfff17 	ldw	r2,-4(fp)
+ 803d500:	10c00417 	ldw	r3,16(r2)
+ 803d504:	e0bff217 	ldw	r2,-56(fp)
+ 803d508:	10800717 	ldw	r2,28(r2)
+ 803d50c:	1880861e 	bne	r3,r2,803d728 <udpdemux+0x5f4>
+#ifdef IP_MULTICAST
+      /* In the case of multicast, check if there is multicast membership
+       * attached to this socket and if so, is the incoming packet
+       * addressed to the multicast address
+       */
+      if (IN_MULTICAST(ntohl(pip->ip_dest)))
+ 803d510:	e0bffb17 	ldw	r2,-20(fp)
+ 803d514:	10800417 	ldw	r2,16(r2)
+ 803d518:	1006d63a 	srli	r3,r2,24
+ 803d51c:	e0bffb17 	ldw	r2,-20(fp)
+ 803d520:	10800417 	ldw	r2,16(r2)
+ 803d524:	1004d23a 	srli	r2,r2,8
+ 803d528:	10bfc00c 	andi	r2,r2,65280
+ 803d52c:	1886b03a 	or	r3,r3,r2
+ 803d530:	e0bffb17 	ldw	r2,-20(fp)
+ 803d534:	10800417 	ldw	r2,16(r2)
+ 803d538:	1004923a 	slli	r2,r2,8
+ 803d53c:	10803fec 	andhi	r2,r2,255
+ 803d540:	1886b03a 	or	r3,r3,r2
+ 803d544:	e0bffb17 	ldw	r2,-20(fp)
+ 803d548:	10800417 	ldw	r2,16(r2)
+ 803d54c:	1004963a 	slli	r2,r2,24
+ 803d550:	1884b03a 	or	r2,r3,r2
+ 803d554:	10fc002c 	andhi	r3,r2,61440
+ 803d558:	00b80034 	movhi	r2,57344
+ 803d55c:	18802d1e 	bne	r3,r2,803d614 <udpdemux+0x4e0>
+      {
+         struct socket *soptr = (struct socket *)con->u_data;
+ 803d560:	e0bfff17 	ldw	r2,-4(fp)
+ 803d564:	10800617 	ldw	r2,24(r2)
+ 803d568:	e0bff715 	stw	r2,-36(fp)
+
+         if ((con->u_rcv == udp_soinput) && (soptr->inp_moptions != NULL))
+ 803d56c:	e0bfff17 	ldw	r2,-4(fp)
+ 803d570:	10c00517 	ldw	r3,20(r2)
+ 803d574:	008200f4 	movhi	r2,2051
+ 803d578:	10990604 	addi	r2,r2,25624
+ 803d57c:	1880251e 	bne	r3,r2,803d614 <udpdemux+0x4e0>
+ 803d580:	e0bff717 	ldw	r2,-36(fp)
+ 803d584:	10800317 	ldw	r2,12(r2)
+ 803d588:	10002226 	beq	r2,zero,803d614 <udpdemux+0x4e0>
+         {
+            u_short  i;
+            struct ip_moptions *imo = soptr->inp_moptions;
+ 803d58c:	e0bff717 	ldw	r2,-36(fp)
+ 803d590:	10800317 	ldw	r2,12(r2)
+ 803d594:	e0bff615 	stw	r2,-40(fp)
+
+            for (i = 0; i < imo->imo_num_memberships; ++i)
+ 803d598:	e03ffc8d 	sth	zero,-14(fp)
+ 803d59c:	00001706 	br	803d5fc <udpdemux+0x4c8>
+            {
+               if ((imo->imo_membership[i]->inm_netp == p->net) &&
+ 803d5a0:	e0bffc8b 	ldhu	r2,-14(fp)
+ 803d5a4:	e0fff617 	ldw	r3,-40(fp)
+ 803d5a8:	10800084 	addi	r2,r2,2
+ 803d5ac:	100490ba 	slli	r2,r2,2
+ 803d5b0:	1885883a 	add	r2,r3,r2
+ 803d5b4:	10800017 	ldw	r2,0(r2)
+ 803d5b8:	10c00117 	ldw	r3,4(r2)
+ 803d5bc:	e0bff217 	ldw	r2,-56(fp)
+ 803d5c0:	10800617 	ldw	r2,24(r2)
+ 803d5c4:	18800a1e 	bne	r3,r2,803d5f0 <udpdemux+0x4bc>
+                   (imo->imo_membership[i]->inm_addr == pip->ip_dest))
+ 803d5c8:	e0bffc8b 	ldhu	r2,-14(fp)
+ 803d5cc:	e0fff617 	ldw	r3,-40(fp)
+ 803d5d0:	10800084 	addi	r2,r2,2
+ 803d5d4:	100490ba 	slli	r2,r2,2
+ 803d5d8:	1885883a 	add	r2,r3,r2
+ 803d5dc:	10800017 	ldw	r2,0(r2)
+ 803d5e0:	10c00017 	ldw	r3,0(r2)
+ 803d5e4:	e0bffb17 	ldw	r2,-20(fp)
+ 803d5e8:	10800417 	ldw	r2,16(r2)
+               if ((imo->imo_membership[i]->inm_netp == p->net) &&
+ 803d5ec:	18800b26 	beq	r3,r2,803d61c <udpdemux+0x4e8>
+            for (i = 0; i < imo->imo_num_memberships; ++i)
+ 803d5f0:	e0bffc8b 	ldhu	r2,-14(fp)
+ 803d5f4:	10800044 	addi	r2,r2,1
+ 803d5f8:	e0bffc8d 	sth	r2,-14(fp)
+ 803d5fc:	e0bff617 	ldw	r2,-40(fp)
+ 803d600:	1080018b 	ldhu	r2,6(r2)
+ 803d604:	e0fffc8b 	ldhu	r3,-14(fp)
+ 803d608:	10bfffcc 	andi	r2,r2,65535
+ 803d60c:	18bfe436 	bltu	r3,r2,803d5a0 <udpdemux+0x46c>
+               {
+                  goto found;
+               }
+            }
+            continue;
+ 803d610:	00004806 	br	803d734 <udpdemux+0x600>
+         }
+      }
+      found:
+ 803d614:	0001883a 	nop
+ 803d618:	00000106 	br	803d620 <udpdemux+0x4ec>
+                  goto found;
+ 803d61c:	0001883a 	nop
+#endif /* INCLUDE_TCP */
+
+      /* if this endpoint has been bound to a local interface address,
+       * make sure the packet was received on that interface address
+       */
+      if (!IN_MULTICAST(ntohl(pip->ip_dest)))
+ 803d620:	e0bffb17 	ldw	r2,-20(fp)
+ 803d624:	10800417 	ldw	r2,16(r2)
+ 803d628:	1006d63a 	srli	r3,r2,24
+ 803d62c:	e0bffb17 	ldw	r2,-20(fp)
+ 803d630:	10800417 	ldw	r2,16(r2)
+ 803d634:	1004d23a 	srli	r2,r2,8
+ 803d638:	10bfc00c 	andi	r2,r2,65280
+ 803d63c:	1886b03a 	or	r3,r3,r2
+ 803d640:	e0bffb17 	ldw	r2,-20(fp)
+ 803d644:	10800417 	ldw	r2,16(r2)
+ 803d648:	1004923a 	slli	r2,r2,8
+ 803d64c:	10803fec 	andhi	r2,r2,255
+ 803d650:	1886b03a 	or	r3,r3,r2
+ 803d654:	e0bffb17 	ldw	r2,-20(fp)
+ 803d658:	10800417 	ldw	r2,16(r2)
+ 803d65c:	1004963a 	slli	r2,r2,24
+ 803d660:	1884b03a 	or	r2,r3,r2
+ 803d664:	10fc002c 	andhi	r3,r2,61440
+ 803d668:	00b80034 	movhi	r2,57344
+ 803d66c:	18800826 	beq	r3,r2,803d690 <udpdemux+0x55c>
+      {
+         if ((con->u_lhost != 0) && (con->u_lhost != pip->ip_dest)) 
+ 803d670:	e0bfff17 	ldw	r2,-4(fp)
+ 803d674:	10800317 	ldw	r2,12(r2)
+ 803d678:	10000526 	beq	r2,zero,803d690 <udpdemux+0x55c>
+ 803d67c:	e0bfff17 	ldw	r2,-4(fp)
+ 803d680:	10c00317 	ldw	r3,12(r2)
+ 803d684:	e0bffb17 	ldw	r2,-20(fp)
+ 803d688:	10800417 	ldw	r2,16(r2)
+ 803d68c:	1880281e 	bne	r3,r2,803d730 <udpdemux+0x5fc>
+            continue;
+      }
+
+      /* fall to here if we found it */
+      udp_mib.udpInDatagrams++;
+ 803d690:	008201b4 	movhi	r2,2054
+ 803d694:	10b96317 	ldw	r2,-6772(r2)
+ 803d698:	10c00044 	addi	r3,r2,1
+ 803d69c:	008201b4 	movhi	r2,2054
+ 803d6a0:	10f96315 	stw	r3,-6772(r2)
+      if (con->u_rcv)         /* if upcall address is set... */
+ 803d6a4:	e0bfff17 	ldw	r2,-4(fp)
+ 803d6a8:	10800517 	ldw	r2,20(r2)
+ 803d6ac:	10000d26 	beq	r2,zero,803d6e4 <udpdemux+0x5b0>
+      {
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 803d6b0:	0009883a 	mov	r4,zero
+ 803d6b4:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         e = ((*con->u_rcv)(p, con->u_data));   /* upcall it */
+ 803d6b8:	e0bfff17 	ldw	r2,-4(fp)
+ 803d6bc:	10800517 	ldw	r2,20(r2)
+ 803d6c0:	e0ffff17 	ldw	r3,-4(fp)
+ 803d6c4:	18c00617 	ldw	r3,24(r3)
+ 803d6c8:	180b883a 	mov	r5,r3
+ 803d6cc:	e13ff217 	ldw	r4,-56(fp)
+ 803d6d0:	103ee83a 	callr	r2
+ 803d6d4:	e0bffd15 	stw	r2,-12(fp)
+         LOCK_NET_RESOURCE(NET_RESID);
+ 803d6d8:	0009883a 	mov	r4,zero
+ 803d6dc:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+ 803d6e0:	00000206 	br	803d6ec <udpdemux+0x5b8>
+      }
+      else
+         e = ENP_LOGIC;
+ 803d6e4:	00bffd44 	movi	r2,-11
+ 803d6e8:	e0bffd15 	stw	r2,-12(fp)
+
+      /* if error occurred in upcall or there was no upcall hander
+         its up to this routine to free the packet buffer */
+      if (e)
+ 803d6ec:	e0bffd17 	ldw	r2,-12(fp)
+ 803d6f0:	10000726 	beq	r2,zero,803d710 <udpdemux+0x5dc>
+      {
+         udp_mib.udpInErrors++;
+ 803d6f4:	008201b4 	movhi	r2,2054
+ 803d6f8:	10b96517 	ldw	r2,-6764(r2)
+ 803d6fc:	10c00044 	addi	r3,r2,1
+ 803d700:	008201b4 	movhi	r2,2054
+ 803d704:	10f96515 	stw	r3,-6764(r2)
+         udp_free(p);
+ 803d708:	e13ff217 	ldw	r4,-56(fp)
+ 803d70c:	803ddb80 	call	803ddb8 <udp_free>
+      }
+
+      return(e);
+ 803d710:	e0bffd17 	ldw	r2,-12(fp)
+ 803d714:	00005d06 	br	803d88c <udpdemux+0x758>
+         continue;
+ 803d718:	0001883a 	nop
+ 803d71c:	00000506 	br	803d734 <udpdemux+0x600>
+         continue;
+ 803d720:	0001883a 	nop
+ 803d724:	00000306 	br	803d734 <udpdemux+0x600>
+         continue;
+ 803d728:	0001883a 	nop
+ 803d72c:	00000106 	br	803d734 <udpdemux+0x600>
+            continue;
+ 803d730:	0001883a 	nop
+   for (con = firstudp; con; con = con->u_next)
+ 803d734:	e0bfff17 	ldw	r2,-4(fp)
+ 803d738:	10800017 	ldw	r2,0(r2)
+ 803d73c:	e0bfff15 	stw	r2,-4(fp)
+ 803d740:	e0bfff17 	ldw	r2,-4(fp)
+ 803d744:	103f541e 	bne	r2,zero,803d498 <udpdemux+0x364>
+
+   /* Fall to here if packet is not for us. Check if the packet was 
+    * sent to an ip broadcast address. If it was, don't send a 
+    * destination unreachable. 
+    */
+   if ((pip->ip_dest == 0xffffffffL) ||   /* Physical cable broadcast addr*/
+ 803d748:	e0bffb17 	ldw	r2,-20(fp)
+ 803d74c:	10800417 	ldw	r2,16(r2)
+ 803d750:	10bfffe0 	cmpeqi	r2,r2,-1
+ 803d754:	1000121e 	bne	r2,zero,803d7a0 <udpdemux+0x66c>
+       (pip->ip_dest == p->net->n_netbr) ||   /* All subnet broadcast */
+ 803d758:	e0bffb17 	ldw	r2,-20(fp)
+ 803d75c:	10c00417 	ldw	r3,16(r2)
+ 803d760:	e0bff217 	ldw	r2,-56(fp)
+ 803d764:	10800617 	ldw	r2,24(r2)
+ 803d768:	10800e17 	ldw	r2,56(r2)
+   if ((pip->ip_dest == 0xffffffffL) ||   /* Physical cable broadcast addr*/
+ 803d76c:	18800c26 	beq	r3,r2,803d7a0 <udpdemux+0x66c>
+       (pip->ip_dest == p->net->n_netbr42) || /* All subnet bcast (4.2bsd) */
+ 803d770:	e0bffb17 	ldw	r2,-20(fp)
+ 803d774:	10c00417 	ldw	r3,16(r2)
+ 803d778:	e0bff217 	ldw	r2,-56(fp)
+ 803d77c:	10800617 	ldw	r2,24(r2)
+ 803d780:	10800f17 	ldw	r2,60(r2)
+       (pip->ip_dest == p->net->n_netbr) ||   /* All subnet broadcast */
+ 803d784:	18800626 	beq	r3,r2,803d7a0 <udpdemux+0x66c>
+       (pip->ip_dest == p->net->n_subnetbr))  /* Our subnet broadcast */
+ 803d788:	e0bffb17 	ldw	r2,-20(fp)
+ 803d78c:	10c00417 	ldw	r3,16(r2)
+ 803d790:	e0bff217 	ldw	r2,-56(fp)
+ 803d794:	10800617 	ldw	r2,24(r2)
+ 803d798:	10801017 	ldw	r2,64(r2)
+       (pip->ip_dest == p->net->n_netbr42) || /* All subnet bcast (4.2bsd) */
+ 803d79c:	1880121e 	bne	r3,r2,803d7e8 <udpdemux+0x6b4>
+   {
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+ 803d7a0:	d0a06617 	ldw	r2,-32360(gp)
+ 803d7a4:	1081000c 	andi	r2,r2,1024
+ 803d7a8:	10000626 	beq	r2,zero,803d7c4 <udpdemux+0x690>
+ 803d7ac:	d0a06617 	ldw	r2,-32360(gp)
+ 803d7b0:	1080400c 	andi	r2,r2,256
+ 803d7b4:	10000326 	beq	r2,zero,803d7c4 <udpdemux+0x690>
+         dprintf("UDP: ignoring ip broadcast\n");
+ 803d7b8:	01020174 	movhi	r4,2053
+ 803d7bc:	212d1604 	addi	r4,r4,-19368
+ 803d7c0:	8002d9c0 	call	8002d9c <puts>
+#endif
+      udp_mib.udpInErrors++;
+ 803d7c4:	008201b4 	movhi	r2,2054
+ 803d7c8:	10b96517 	ldw	r2,-6764(r2)
+ 803d7cc:	10c00044 	addi	r3,r2,1
+ 803d7d0:	008201b4 	movhi	r2,2054
+ 803d7d4:	10f96515 	stw	r3,-6764(r2)
+      udp_free(p);
+ 803d7d8:	e13ff217 	ldw	r4,-56(fp)
+ 803d7dc:	803ddb80 	call	803ddb8 <udp_free>
+      return ENP_NOT_MINE;
+ 803d7e0:	00800084 	movi	r2,2
+ 803d7e4:	00002906 	br	803d88c <udpdemux+0x758>
+   }
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+ 803d7e8:	d0a06617 	ldw	r2,-32360(gp)
+ 803d7ec:	1081000c 	andi	r2,r2,1024
+ 803d7f0:	10000f26 	beq	r2,zero,803d830 <udpdemux+0x6fc>
+ 803d7f4:	d0a06617 	ldw	r2,-32360(gp)
+ 803d7f8:	1080400c 	andi	r2,r2,256
+ 803d7fc:	10000c26 	beq	r2,zero,803d830 <udpdemux+0x6fc>
+   {
+      dprintf("UDP: unexpected port %04x\n", pup->ud_dstp);
+ 803d800:	e0bffa17 	ldw	r2,-24(fp)
+ 803d804:	1080008b 	ldhu	r2,2(r2)
+ 803d808:	10bfffcc 	andi	r2,r2,65535
+ 803d80c:	100b883a 	mov	r5,r2
+ 803d810:	01020174 	movhi	r4,2053
+ 803d814:	212d1d04 	addi	r4,r4,-19340
+ 803d818:	8002c780 	call	8002c78 <printf>
+      if (NDEBUG & DUMP) 
+ 803d81c:	d0a06617 	ldw	r2,-32360(gp)
+ 803d820:	1080008c 	andi	r2,r2,2
+ 803d824:	10000226 	beq	r2,zero,803d830 <udpdemux+0x6fc>
+         ip_dump(p);
+ 803d828:	e13ff217 	ldw	r4,-56(fp)
+ 803d82c:	803b0cc0 	call	803b0cc <ip_dump>
+#ifdef FULL_ICMP
+   /* send destination unreachable.  Swap back all the swapped information */
+   /* so that the destun packet format is correct */
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+ 803d830:	e13ffa17 	ldw	r4,-24(fp)
+ 803d834:	803db340 	call	803db34 <udpswap>
+#endif   /* BYTE_ORDER */
+   
+   icmp_destun(p->fhost, p->net->n_ipaddr, pip, DSTPORT, p->net);
+ 803d838:	e0bff217 	ldw	r2,-56(fp)
+ 803d83c:	10c00717 	ldw	r3,28(r2)
+ 803d840:	e0bff217 	ldw	r2,-56(fp)
+ 803d844:	10800617 	ldw	r2,24(r2)
+ 803d848:	11000a17 	ldw	r4,40(r2)
+ 803d84c:	e0bff217 	ldw	r2,-56(fp)
+ 803d850:	10800617 	ldw	r2,24(r2)
+ 803d854:	d8800015 	stw	r2,0(sp)
+ 803d858:	01c000c4 	movi	r7,3
+ 803d85c:	e1bffb17 	ldw	r6,-20(fp)
+ 803d860:	200b883a 	mov	r5,r4
+ 803d864:	1809883a 	mov	r4,r3
+ 803d868:	8039a540 	call	8039a54 <icmp_destun>
+#endif   /* FULL_ICMP */
+
+   udp_mib.udpNoPorts++;
+ 803d86c:	008201b4 	movhi	r2,2054
+ 803d870:	10b96417 	ldw	r2,-6768(r2)
+ 803d874:	10c00044 	addi	r3,r2,1
+ 803d878:	008201b4 	movhi	r2,2054
+ 803d87c:	10f96415 	stw	r3,-6768(r2)
+   udp_free(p);
+ 803d880:	e13ff217 	ldw	r4,-56(fp)
+ 803d884:	803ddb80 	call	803ddb8 <udp_free>
+   return ENP_NOT_MINE;
+ 803d888:	00800084 	movi	r2,2
+}
+ 803d88c:	e037883a 	mov	sp,fp
+ 803d890:	dfc00117 	ldw	ra,4(sp)
+ 803d894:	df000017 	ldw	fp,0(sp)
+ 803d898:	dec00204 	addi	sp,sp,8
+ 803d89c:	f800283a 	ret
+
+0803d8a0 <udp_send>:
+ * detected. 
+ */
+
+int
+udp_send(unshort fport, unshort lport, PACKET p)
+{
+ 803d8a0:	deffef04 	addi	sp,sp,-68
+ 803d8a4:	dfc01015 	stw	ra,64(sp)
+ 803d8a8:	df000f15 	stw	fp,60(sp)
+ 803d8ac:	df000f04 	addi	fp,sp,60
+ 803d8b0:	2005883a 	mov	r2,r4
+ 803d8b4:	2807883a 	mov	r3,r5
+ 803d8b8:	e1bff515 	stw	r6,-44(fp)
+ 803d8bc:	e0bff70d 	sth	r2,-36(fp)
+ 803d8c0:	1805883a 	mov	r2,r3
+ 803d8c4:	e0bff60d 	sth	r2,-40(fp)
+   int         udplen;
+   int         e;
+   ip_addr     src_ip;    /* source IP, for checksumming purposes */
+
+#ifdef   NPDEBUG
+   if (NDEBUG & (INFOMSG|TPTRACE))
+ 803d8c8:	d0a06617 	ldw	r2,-32360(gp)
+ 803d8cc:	1080410c 	andi	r2,r2,260
+ 803d8d0:	10001a26 	beq	r2,zero,803d93c <udp_send+0x9c>
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+ 803d8d4:	e0bff517 	ldw	r2,-44(fp)
+ 803d8d8:	12000417 	ldw	r8,16(r2)
+ 803d8dc:	e1bff60b 	ldhu	r6,-40(fp)
+    PUSH_IPADDR(p->fhost), fport);
+ 803d8e0:	e0bff517 	ldw	r2,-44(fp)
+ 803d8e4:	10800717 	ldw	r2,28(r2)
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+ 803d8e8:	11c03fcc 	andi	r7,r2,255
+    PUSH_IPADDR(p->fhost), fport);
+ 803d8ec:	e0bff517 	ldw	r2,-44(fp)
+ 803d8f0:	10800717 	ldw	r2,28(r2)
+ 803d8f4:	1004d23a 	srli	r2,r2,8
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+ 803d8f8:	10803fcc 	andi	r2,r2,255
+    PUSH_IPADDR(p->fhost), fport);
+ 803d8fc:	e0fff517 	ldw	r3,-44(fp)
+ 803d900:	18c00717 	ldw	r3,28(r3)
+ 803d904:	1806d43a 	srli	r3,r3,16
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+ 803d908:	18c03fcc 	andi	r3,r3,255
+    PUSH_IPADDR(p->fhost), fport);
+ 803d90c:	e13ff517 	ldw	r4,-44(fp)
+ 803d910:	21000717 	ldw	r4,28(r4)
+ 803d914:	2008d63a 	srli	r4,r4,24
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+ 803d918:	e17ff70b 	ldhu	r5,-36(fp)
+ 803d91c:	d9400315 	stw	r5,12(sp)
+ 803d920:	d9000215 	stw	r4,8(sp)
+ 803d924:	d8c00115 	stw	r3,4(sp)
+ 803d928:	d8800015 	stw	r2,0(sp)
+ 803d92c:	400b883a 	mov	r5,r8
+ 803d930:	01020174 	movhi	r4,2053
+ 803d934:	212d2404 	addi	r4,r4,-19312
+ 803d938:	8002c780 	call	8002c78 <printf>
+#endif
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 803d93c:	0009883a 	mov	r4,zero
+ 803d940:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   /* prepend UDP header to upper layer's data */
+   p->nb_prot -= sizeof(struct udp);
+ 803d944:	e0bff517 	ldw	r2,-44(fp)
+ 803d948:	10800317 	ldw	r2,12(r2)
+ 803d94c:	10fffe04 	addi	r3,r2,-8
+ 803d950:	e0bff517 	ldw	r2,-44(fp)
+ 803d954:	10c00315 	stw	r3,12(r2)
+   pup = (struct udp*)p->nb_prot;
+ 803d958:	e0bff517 	ldw	r2,-44(fp)
+ 803d95c:	10800317 	ldw	r2,12(r2)
+ 803d960:	e0bffe15 	stw	r2,-8(fp)
+   udplen = p->nb_plen + sizeof(struct udp);
+ 803d964:	e0bff517 	ldw	r2,-44(fp)
+ 803d968:	10800417 	ldw	r2,16(r2)
+ 803d96c:	10800204 	addi	r2,r2,8
+ 803d970:	e0bffd15 	stw	r2,-12(fp)
+   p->nb_plen = udplen;
+ 803d974:	e0fffd17 	ldw	r3,-12(fp)
+ 803d978:	e0bff517 	ldw	r2,-44(fp)
+ 803d97c:	10c00415 	stw	r3,16(r2)
+   if (udplen & 1) ((char *)pup)[udplen] = 0;
+ 803d980:	e0bffd17 	ldw	r2,-12(fp)
+ 803d984:	1080004c 	andi	r2,r2,1
+ 803d988:	10000426 	beq	r2,zero,803d99c <udp_send+0xfc>
+ 803d98c:	e0bffd17 	ldw	r2,-12(fp)
+ 803d990:	e0fffe17 	ldw	r3,-8(fp)
+ 803d994:	1885883a 	add	r2,r3,r2
+ 803d998:	10000005 	stb	zero,0(r2)
+
+      pup->ud_len = (unshort)udplen;   /* fill in the UDP header */
+ 803d99c:	e0bffd17 	ldw	r2,-12(fp)
+ 803d9a0:	1007883a 	mov	r3,r2
+ 803d9a4:	e0bffe17 	ldw	r2,-8(fp)
+ 803d9a8:	10c0010d 	sth	r3,4(r2)
+   pup->ud_srcp = lport;
+ 803d9ac:	e0bffe17 	ldw	r2,-8(fp)
+ 803d9b0:	e0fff60b 	ldhu	r3,-40(fp)
+ 803d9b4:	10c0000d 	sth	r3,0(r2)
+   pup->ud_dstp = fport;
+ 803d9b8:	e0bffe17 	ldw	r2,-8(fp)
+ 803d9bc:	e0fff70b 	ldhu	r3,-36(fp)
+ 803d9c0:	10c0008d 	sth	r3,2(r2)
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+ 803d9c4:	e13ffe17 	ldw	r4,-8(fp)
+ 803d9c8:	803db340 	call	803db34 <udpswap>
+#endif   /* BYTE_ORDER */
+   
+#ifdef MULTI_HOMED
+   /* getting the source IP address for a broadcast is a bit tricky: */
+   if (p->fhost == 0xffffffff)
+ 803d9cc:	e0bff517 	ldw	r2,-44(fp)
+ 803d9d0:	10800717 	ldw	r2,28(r2)
+ 803d9d4:	10bfffd8 	cmpnei	r2,r2,-1
+ 803d9d8:	10000f1e 	bne	r2,zero,803da18 <udp_send+0x178>
+   {
+      if (!p->net)
+ 803d9dc:	e0bff517 	ldw	r2,-44(fp)
+ 803d9e0:	10800617 	ldw	r2,24(r2)
+ 803d9e4:	1000071e 	bne	r2,zero,803da04 <udp_send+0x164>
+      {
+         dtrap();    /* programmer forgot to select iface */
+ 803d9e8:	8028cd40 	call	8028cd4 <dtrap>
+         /* it would appear that the callers of udp_send() expect it
+            to do cleanup on failure, so free the packet buffer here */
+         udp_free(p);
+ 803d9ec:	e13ff517 	ldw	r4,-44(fp)
+ 803d9f0:	803ddb80 	call	803ddb8 <udp_free>
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 803d9f4:	0009883a 	mov	r4,zero
+ 803d9f8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return ENP_NO_IFACE;
+ 803d9fc:	00bff784 	movi	r2,-34
+ 803da00:	00004706 	br	803db20 <udp_send+0x280>
+      }
+      src_ip = p->net->n_ipaddr;
+ 803da04:	e0bff517 	ldw	r2,-44(fp)
+ 803da08:	10800617 	ldw	r2,24(r2)
+ 803da0c:	10800a17 	ldw	r2,40(r2)
+ 803da10:	e0bfff15 	stw	r2,-4(fp)
+ 803da14:	00000506 	br	803da2c <udp_send+0x18c>
+   /* set the IP addresses in the IP header. The pseudo header used for
+    * checksumming overlays the addresses on the IP header area in the
+    * buffer, so setting them there (which we need to do for cksum
+    * anyway) sets up for IP too.
+    */
+   src_ip = ip_mymach(p->fhost);
+ 803da18:	e0bff517 	ldw	r2,-44(fp)
+ 803da1c:	10800717 	ldw	r2,28(r2)
+ 803da20:	1009883a 	mov	r4,r2
+ 803da24:	803b0280 	call	803b028 <ip_mymach>
+ 803da28:	e0bfff15 	stw	r2,-4(fp)
+   php.ph_src = src_ip;
+ 803da2c:	e0bfff17 	ldw	r2,-4(fp)
+ 803da30:	e0bff815 	stw	r2,-32(fp)
+   php.ph_dest = p->fhost;
+ 803da34:	e0bff517 	ldw	r2,-44(fp)
+ 803da38:	10800717 	ldw	r2,28(r2)
+ 803da3c:	e0bff915 	stw	r2,-28(fp)
+#ifdef NO_UDP_CKSUM
+   /* If no UDP checksum support, just zero the checksum field */
+   pup->ud_cksum = 0;
+#else
+   /* finish filling in the pseudo header required for checksumming */
+   php.ph_zero = 0;
+ 803da40:	e03ffa05 	stb	zero,-24(fp)
+   php.ph_prot = UDP_PROT;
+ 803da44:	00800444 	movi	r2,17
+ 803da48:	e0bffa45 	stb	r2,-23(fp)
+   php.ph_len = pup->ud_len;
+ 803da4c:	e0bffe17 	ldw	r2,-8(fp)
+ 803da50:	1080010b 	ldhu	r2,4(r2)
+ 803da54:	e0bffa8d 	sth	r2,-22(fp)
+   pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1);
+ 803da58:	e0bff804 	addi	r2,fp,-32
+ 803da5c:	01400184 	movi	r5,6
+ 803da60:	1009883a 	mov	r4,r2
+ 803da64:	8026d7c0 	call	8026d7c <cksum>
+ 803da68:	1007883a 	mov	r3,r2
+ 803da6c:	e0bffe17 	ldw	r2,-8(fp)
+ 803da70:	10c0018d 	sth	r3,6(r2)
+   pup->ud_cksum = ~cksum(pup, (udplen+1)>>1);
+ 803da74:	e0bffd17 	ldw	r2,-12(fp)
+ 803da78:	10800044 	addi	r2,r2,1
+ 803da7c:	1005d07a 	srai	r2,r2,1
+ 803da80:	100b883a 	mov	r5,r2
+ 803da84:	e13ffe17 	ldw	r4,-8(fp)
+ 803da88:	8026d7c0 	call	8026d7c <cksum>
+ 803da8c:	0084303a 	nor	r2,zero,r2
+ 803da90:	1007883a 	mov	r3,r2
+ 803da94:	e0bffe17 	ldw	r2,-8(fp)
+ 803da98:	10c0018d 	sth	r3,6(r2)
+   if (pup->ud_cksum == 0)
+ 803da9c:	e0bffe17 	ldw	r2,-8(fp)
+ 803daa0:	1080018b 	ldhu	r2,6(r2)
+ 803daa4:	10bfffcc 	andi	r2,r2,65535
+ 803daa8:	1000031e 	bne	r2,zero,803dab8 <udp_send+0x218>
+      pup->ud_cksum = 0xffff;
+ 803daac:	e0bffe17 	ldw	r2,-8(fp)
+ 803dab0:	00ffffc4 	movi	r3,-1
+ 803dab4:	10c0018d 	sth	r3,6(r2)
+#endif
+
+   /* need to fill in IP addresses at this layer too */
+   pip = (struct ip *)(p->nb_prot - sizeof(struct ip));
+ 803dab8:	e0bff517 	ldw	r2,-44(fp)
+ 803dabc:	10800317 	ldw	r2,12(r2)
+ 803dac0:	10bffb04 	addi	r2,r2,-20
+ 803dac4:	e0bffc15 	stw	r2,-16(fp)
+   pip->ip_src = src_ip;
+ 803dac8:	e0bffc17 	ldw	r2,-16(fp)
+ 803dacc:	e0ffff17 	ldw	r3,-4(fp)
+ 803dad0:	10c00315 	stw	r3,12(r2)
+   pip->ip_dest = p->fhost;
+ 803dad4:	e0bff517 	ldw	r2,-44(fp)
+ 803dad8:	10c00717 	ldw	r3,28(r2)
+ 803dadc:	e0bffc17 	ldw	r2,-16(fp)
+ 803dae0:	10c00415 	stw	r3,16(r2)
+
+   udp_mib.udpOutDatagrams++;
+ 803dae4:	008201b4 	movhi	r2,2054
+ 803dae8:	10b96617 	ldw	r2,-6760(r2)
+ 803daec:	10c00044 	addi	r3,r2,1
+ 803daf0:	008201b4 	movhi	r2,2054
+ 803daf4:	10f96615 	stw	r3,-6760(r2)
+
+   p->nb_plen = udplen;       /* nb_prot was adjusted above */
+ 803daf8:	e0fffd17 	ldw	r3,-12(fp)
+ 803dafc:	e0bff517 	ldw	r2,-44(fp)
+ 803db00:	10c00415 	stw	r3,16(r2)
+   e = ip_write(UDP_PROT, p);
+ 803db04:	e17ff517 	ldw	r5,-44(fp)
+ 803db08:	01000444 	movi	r4,17
+ 803db0c:	803a9e80 	call	803a9e8 <ip_write>
+ 803db10:	e0bffb15 	stw	r2,-20(fp)
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 803db14:	0009883a 	mov	r4,zero
+ 803db18:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return e;
+ 803db1c:	e0bffb17 	ldw	r2,-20(fp)
+}
+ 803db20:	e037883a 	mov	sp,fp
+ 803db24:	dfc00117 	ldw	ra,4(sp)
+ 803db28:	df000017 	ldw	fp,0(sp)
+ 803db2c:	dec00204 	addi	sp,sp,8
+ 803db30:	f800283a 	ret
+
+0803db34 <udpswap>:
+ */
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+void
+udpswap(struct udp *pup)
+{
+ 803db34:	defffe04 	addi	sp,sp,-8
+ 803db38:	df000115 	stw	fp,4(sp)
+ 803db3c:	df000104 	addi	fp,sp,4
+ 803db40:	e13fff15 	stw	r4,-4(fp)
+
+   pup->ud_srcp = htons(pup->ud_srcp);
+ 803db44:	e0bfff17 	ldw	r2,-4(fp)
+ 803db48:	1080000b 	ldhu	r2,0(r2)
+ 803db4c:	10bfffcc 	andi	r2,r2,65535
+ 803db50:	1004d23a 	srli	r2,r2,8
+ 803db54:	1007883a 	mov	r3,r2
+ 803db58:	e0bfff17 	ldw	r2,-4(fp)
+ 803db5c:	1080000b 	ldhu	r2,0(r2)
+ 803db60:	10bfffcc 	andi	r2,r2,65535
+ 803db64:	1004923a 	slli	r2,r2,8
+ 803db68:	1884b03a 	or	r2,r3,r2
+ 803db6c:	1007883a 	mov	r3,r2
+ 803db70:	e0bfff17 	ldw	r2,-4(fp)
+ 803db74:	10c0000d 	sth	r3,0(r2)
+   pup->ud_dstp = htons(pup->ud_dstp);
+ 803db78:	e0bfff17 	ldw	r2,-4(fp)
+ 803db7c:	1080008b 	ldhu	r2,2(r2)
+ 803db80:	10bfffcc 	andi	r2,r2,65535
+ 803db84:	1004d23a 	srli	r2,r2,8
+ 803db88:	1007883a 	mov	r3,r2
+ 803db8c:	e0bfff17 	ldw	r2,-4(fp)
+ 803db90:	1080008b 	ldhu	r2,2(r2)
+ 803db94:	10bfffcc 	andi	r2,r2,65535
+ 803db98:	1004923a 	slli	r2,r2,8
+ 803db9c:	1884b03a 	or	r2,r3,r2
+ 803dba0:	1007883a 	mov	r3,r2
+ 803dba4:	e0bfff17 	ldw	r2,-4(fp)
+ 803dba8:	10c0008d 	sth	r3,2(r2)
+   pup->ud_len = htons(pup->ud_len);
+ 803dbac:	e0bfff17 	ldw	r2,-4(fp)
+ 803dbb0:	1080010b 	ldhu	r2,4(r2)
+ 803dbb4:	10bfffcc 	andi	r2,r2,65535
+ 803dbb8:	1004d23a 	srli	r2,r2,8
+ 803dbbc:	1007883a 	mov	r3,r2
+ 803dbc0:	e0bfff17 	ldw	r2,-4(fp)
+ 803dbc4:	1080010b 	ldhu	r2,4(r2)
+ 803dbc8:	10bfffcc 	andi	r2,r2,65535
+ 803dbcc:	1004923a 	slli	r2,r2,8
+ 803dbd0:	1884b03a 	or	r2,r3,r2
+ 803dbd4:	1007883a 	mov	r3,r2
+ 803dbd8:	e0bfff17 	ldw	r2,-4(fp)
+ 803dbdc:	10c0010d 	sth	r3,4(r2)
+   pup->ud_cksum = htons(pup->ud_cksum);
+ 803dbe0:	e0bfff17 	ldw	r2,-4(fp)
+ 803dbe4:	1080018b 	ldhu	r2,6(r2)
+ 803dbe8:	10bfffcc 	andi	r2,r2,65535
+ 803dbec:	1004d23a 	srli	r2,r2,8
+ 803dbf0:	1007883a 	mov	r3,r2
+ 803dbf4:	e0bfff17 	ldw	r2,-4(fp)
+ 803dbf8:	1080018b 	ldhu	r2,6(r2)
+ 803dbfc:	10bfffcc 	andi	r2,r2,65535
+ 803dc00:	1004923a 	slli	r2,r2,8
+ 803dc04:	1884b03a 	or	r2,r3,r2
+ 803dc08:	1007883a 	mov	r3,r2
+ 803dc0c:	e0bfff17 	ldw	r2,-4(fp)
+ 803dc10:	10c0018d 	sth	r3,6(r2)
+}
+ 803dc14:	0001883a 	nop
+ 803dc18:	e037883a 	mov	sp,fp
+ 803dc1c:	df000017 	ldw	fp,0(sp)
+ 803dc20:	dec00104 	addi	sp,sp,4
+ 803dc24:	f800283a 	ret
+
+0803dc28 <udp_socket>:
+#define  MINSOCKET   1200
+static unshort usocket = 0;   /* next socket to grab */
+
+unshort
+udp_socket(void)
+{
+ 803dc28:	defffe04 	addi	sp,sp,-8
+ 803dc2c:	df000115 	stw	fp,4(sp)
+ 803dc30:	df000104 	addi	fp,sp,4
+   UDPCONN tmp;
+
+   if (usocket < MINSOCKET)
+ 803dc34:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dc38:	10bfffcc 	andi	r2,r2,65535
+ 803dc3c:	10812c28 	cmpgeui	r2,r2,1200
+ 803dc40:	10000a1e 	bne	r2,zero,803dc6c <udp_socket+0x44>
+   {
+      /* logic for for init and after wraps */
+      usocket = (unshort)(cticks & 0x7fff);
+ 803dc44:	d0a07d17 	ldw	r2,-32268(gp)
+ 803dc48:	109fffcc 	andi	r2,r2,32767
+ 803dc4c:	d0a09d0d 	sth	r2,-32140(gp)
+      if (usocket < MINSOCKET)
+ 803dc50:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dc54:	10bfffcc 	andi	r2,r2,65535
+ 803dc58:	10812c28 	cmpgeui	r2,r2,1200
+ 803dc5c:	1000031e 	bne	r2,zero,803dc6c <udp_socket+0x44>
+         usocket += MINSOCKET;
+ 803dc60:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dc64:	10812c04 	addi	r2,r2,1200
+ 803dc68:	d0a09d0d 	sth	r2,-32140(gp)
+   }
+   /* scan existing connections, making sure socket isn't in use */
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 803dc6c:	d0a09e17 	ldw	r2,-32136(gp)
+ 803dc70:	e0bfff15 	stw	r2,-4(fp)
+ 803dc74:	00000f06 	br	803dcb4 <udp_socket+0x8c>
+   {
+      if (tmp->u_lport == usocket)
+ 803dc78:	e0bfff17 	ldw	r2,-4(fp)
+ 803dc7c:	10c0018b 	ldhu	r3,6(r2)
+ 803dc80:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dc84:	18ffffcc 	andi	r3,r3,65535
+ 803dc88:	10bfffcc 	andi	r2,r2,65535
+ 803dc8c:	1880061e 	bne	r3,r2,803dca8 <udp_socket+0x80>
+      {
+         usocket++;     /* bump socket number */
+ 803dc90:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dc94:	10800044 	addi	r2,r2,1
+ 803dc98:	d0a09d0d 	sth	r2,-32140(gp)
+         tmp = firstudp;   /* restart scan */
+ 803dc9c:	d0a09e17 	ldw	r2,-32136(gp)
+ 803dca0:	e0bfff15 	stw	r2,-4(fp)
+         continue;
+ 803dca4:	0001883a 	nop
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+ 803dca8:	e0bfff17 	ldw	r2,-4(fp)
+ 803dcac:	10800017 	ldw	r2,0(r2)
+ 803dcb0:	e0bfff15 	stw	r2,-4(fp)
+ 803dcb4:	e0bfff17 	ldw	r2,-4(fp)
+ 803dcb8:	103fef1e 	bne	r2,zero,803dc78 <udp_socket+0x50>
+      }
+   }
+   return usocket++;
+ 803dcbc:	d0a09d0b 	ldhu	r2,-32140(gp)
+ 803dcc0:	10c00044 	addi	r3,r2,1
+ 803dcc4:	d0e09d0d 	sth	r3,-32140(gp)
+}
+ 803dcc8:	e037883a 	mov	sp,fp
+ 803dccc:	df000017 	ldw	fp,0(sp)
+ 803dcd0:	dec00104 	addi	sp,sp,4
+ 803dcd4:	f800283a 	ret
+
+0803dcd8 <udp_alloc>:
+ * RETURNS:  Returns buffer, or NULL in no buffer was available. 
+ */
+
+PACKET
+udp_alloc(int datalen, int optlen)
+{
+ 803dcd8:	defffa04 	addi	sp,sp,-24
+ 803dcdc:	dfc00515 	stw	ra,20(sp)
+ 803dce0:	df000415 	stw	fp,16(sp)
+ 803dce4:	df000404 	addi	fp,sp,16
+ 803dce8:	e13ffd15 	stw	r4,-12(fp)
+ 803dcec:	e17ffc15 	stw	r5,-16(fp)
+   int   len;
+   PACKET p;
+
+   len = (datalen + sizeof(struct udp) + 1) & ~1;
+ 803dcf0:	e0bffd17 	ldw	r2,-12(fp)
+ 803dcf4:	10800244 	addi	r2,r2,9
+ 803dcf8:	1007883a 	mov	r3,r2
+ 803dcfc:	00bfff84 	movi	r2,-2
+ 803dd00:	1884703a 	and	r2,r3,r2
+ 803dd04:	e0bfff15 	stw	r2,-4(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803dd08:	01000084 	movi	r4,2
+ 803dd0c:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   p = pk_alloc(len + UDPHDRSLEN + optlen);
+ 803dd10:	e0bfff17 	ldw	r2,-4(fp)
+ 803dd14:	10c00904 	addi	r3,r2,36
+ 803dd18:	e0bffc17 	ldw	r2,-16(fp)
+ 803dd1c:	1885883a 	add	r2,r3,r2
+ 803dd20:	1009883a 	mov	r4,r2
+ 803dd24:	80284340 	call	8028434 <pk_alloc>
+ 803dd28:	e0bffe15 	stw	r2,-8(fp)
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803dd2c:	01000084 	movi	r4,2
+ 803dd30:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+
+   if (p != (PACKET)NULL)
+ 803dd34:	e0bffe17 	ldw	r2,-8(fp)
+ 803dd38:	10001026 	beq	r2,zero,803dd7c <udp_alloc+0xa4>
+   {
+      /* set prot pointers past end of UDP header  */
+      len = sizeof(struct ip) + (optlen >> 2) + sizeof(struct udp);
+ 803dd3c:	e0bffc17 	ldw	r2,-16(fp)
+ 803dd40:	1005d0ba 	srai	r2,r2,2
+ 803dd44:	10800704 	addi	r2,r2,28
+ 803dd48:	e0bfff15 	stw	r2,-4(fp)
+      p->nb_prot += len;
+ 803dd4c:	e0bffe17 	ldw	r2,-8(fp)
+ 803dd50:	10c00317 	ldw	r3,12(r2)
+ 803dd54:	e0bfff17 	ldw	r2,-4(fp)
+ 803dd58:	1887883a 	add	r3,r3,r2
+ 803dd5c:	e0bffe17 	ldw	r2,-8(fp)
+ 803dd60:	10c00315 	stw	r3,12(r2)
+      p->nb_plen -= len;
+ 803dd64:	e0bffe17 	ldw	r2,-8(fp)
+ 803dd68:	10c00417 	ldw	r3,16(r2)
+ 803dd6c:	e0bfff17 	ldw	r2,-4(fp)
+ 803dd70:	1887c83a 	sub	r3,r3,r2
+ 803dd74:	e0bffe17 	ldw	r2,-8(fp)
+ 803dd78:	10c00415 	stw	r3,16(r2)
+   }
+
+   return (p);
+ 803dd7c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803dd80:	e037883a 	mov	sp,fp
+ 803dd84:	dfc00117 	ldw	ra,4(sp)
+ 803dd88:	df000017 	ldw	fp,0(sp)
+ 803dd8c:	dec00204 	addi	sp,sp,8
+ 803dd90:	f800283a 	ret
+
+0803dd94 <udp_maxalloc>:
+ *          returned value, the allocation will fail
+ */
+
+int
+udp_maxalloc(void)
+{
+ 803dd94:	deffff04 	addi	sp,sp,-4
+ 803dd98:	df000015 	stw	fp,0(sp)
+ 803dd9c:	d839883a 	mov	fp,sp
+    * created is ((2^16 - 1) - (size of IP and UDP headers)) */
+   return (0xFFFF - (sizeof (struct ip) + sizeof (struct udp)));
+#else
+   /* if heap buffers are not available, the largest size of a UDP datagram
+    * is constrained by what will fit inside a big buffer */
+   return (bigbufsiz - UDPHDRSLEN);
+ 803dda0:	d0a01917 	ldw	r2,-32668(gp)
+ 803dda4:	10bff704 	addi	r2,r2,-36
+#endif
+}
+ 803dda8:	e037883a 	mov	sp,fp
+ 803ddac:	df000017 	ldw	fp,0(sp)
+ 803ddb0:	dec00104 	addi	sp,sp,4
+ 803ddb4:	f800283a 	ret
+
+0803ddb8 <udp_free>:
+ * RETURNS: void
+ */
+
+void
+udp_free(PACKET p)
+{
+ 803ddb8:	defffd04 	addi	sp,sp,-12
+ 803ddbc:	dfc00215 	stw	ra,8(sp)
+ 803ddc0:	df000115 	stw	fp,4(sp)
+ 803ddc4:	df000104 	addi	fp,sp,4
+ 803ddc8:	e13fff15 	stw	r4,-4(fp)
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803ddcc:	01000084 	movi	r4,2
+ 803ddd0:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 803ddd4:	e13fff17 	ldw	r4,-4(fp)
+ 803ddd8:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803dddc:	01000084 	movi	r4,2
+ 803dde0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+}
+ 803dde4:	0001883a 	nop
+ 803dde8:	e037883a 	mov	sp,fp
+ 803ddec:	dfc00117 	ldw	ra,4(sp)
+ 803ddf0:	df000017 	ldw	fp,0(sp)
+ 803ddf4:	dec00204 	addi	sp,sp,8
+ 803ddf8:	f800283a 	ret
+
+0803ddfc <igmpv1_input>:
+ * OUTPUT: This function returns IGMP_ERR if it is passed an "unknown"
+ * packet type.  Otherwise, it returns IGMP_OK.
+ */
+
+int igmpv1_input(PACKET p)
+{
+ 803ddfc:	defff804 	addi	sp,sp,-32
+ 803de00:	dfc00715 	stw	ra,28(sp)
+ 803de04:	df000615 	stw	fp,24(sp)
+ 803de08:	df000604 	addi	fp,sp,24
+ 803de0c:	e13ffa15 	stw	r4,-24(fp)
+   struct igmp *  igmp;
+   struct ip *    pip;
+   struct in_multi * inm;
+   NET netp  = p->net;
+ 803de10:	e0bffa17 	ldw	r2,-24(fp)
+ 803de14:	10800617 	ldw	r2,24(r2)
+ 803de18:	e0bffd15 	stw	r2,-12(fp)
+   int rc;
+         
+   pip = ip_head (p);
+ 803de1c:	e0bffa17 	ldw	r2,-24(fp)
+ 803de20:	10800317 	ldw	r2,12(r2)
+ 803de24:	e0bffc15 	stw	r2,-16(fp)
+   igmp = (struct igmp *) (ip_data (pip));
+ 803de28:	e0bffc17 	ldw	r2,-16(fp)
+ 803de2c:	10800003 	ldbu	r2,0(r2)
+ 803de30:	10803fcc 	andi	r2,r2,255
+ 803de34:	100490ba 	slli	r2,r2,2
+ 803de38:	10800f0c 	andi	r2,r2,60
+ 803de3c:	e0fffc17 	ldw	r3,-16(fp)
+ 803de40:	1885883a 	add	r2,r3,r2
+ 803de44:	e0bffb15 	stw	r2,-20(fp)
+
+   switch (igmp->igmp_type) 
+ 803de48:	e0bffb17 	ldw	r2,-20(fp)
+ 803de4c:	10800003 	ldbu	r2,0(r2)
+ 803de50:	10803fcc 	andi	r2,r2,255
+ 803de54:	10c00460 	cmpeqi	r3,r2,17
+ 803de58:	1800031e 	bne	r3,zero,803de68 <igmpv1_input+0x6c>
+ 803de5c:	108004a0 	cmpeqi	r2,r2,18
+ 803de60:	1000501e 	bne	r2,zero,803dfa4 <igmpv1_input+0x1a8>
+ 803de64:	00006b06 	br	803e014 <igmpv1_input+0x218>
+   {
+   case IGMP_HOST_MEMBERSHIP_QUERY:
+      ++igmpstats.igmpv1mode_v1_queries_rcvd;
+ 803de68:	008201b4 	movhi	r2,2054
+ 803de6c:	10b77517 	ldw	r2,-8748(r2)
+ 803de70:	10c00044 	addi	r3,r2,1
+ 803de74:	008201b4 	movhi	r2,2054
+ 803de78:	10f77515 	stw	r3,-8748(r2)
+       * Start the timers in all of our membership records for
+       * the interface on which the query arrived, except those
+       * that are already running and those that belong to the
+       * "all-hosts" group.
+       */
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+ 803de7c:	e0bffd17 	ldw	r2,-12(fp)
+ 803de80:	10802c17 	ldw	r2,176(r2)
+ 803de84:	e0bfff15 	stw	r2,-4(fp)
+ 803de88:	00004206 	br	803df94 <igmpv1_input+0x198>
+      {
+         /* skip all IPv6 entries - they are indicated by 
+          * an IPv4 address field of 0 */
+         if (inm->inm_addr == 0)
+ 803de8c:	e0bfff17 	ldw	r2,-4(fp)
+ 803de90:	10800017 	ldw	r2,0(r2)
+ 803de94:	10003b26 	beq	r2,zero,803df84 <igmpv1_input+0x188>
+            continue;
+         /* skip IPv4 multicast address of 224.0.0.1 (note that
+          * the IPv4 address stored in inm_addr is in network 
+          * byte order */
+         if (inm->inm_addr != igmp_all_hosts_group)
+ 803de98:	e0bfff17 	ldw	r2,-4(fp)
+ 803de9c:	10c00017 	ldw	r3,0(r2)
+ 803dea0:	d0a06b17 	ldw	r2,-32340(gp)
+ 803dea4:	18803826 	beq	r3,r2,803df88 <igmpv1_input+0x18c>
+         {
+            if (inm->inm_timer == 0)
+ 803dea8:	e0bfff17 	ldw	r2,-4(fp)
+ 803deac:	10800317 	ldw	r2,12(r2)
+ 803deb0:	1000351e 	bne	r2,zero,803df88 <igmpv1_input+0x18c>
+            {
+               inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr);
+ 803deb4:	008201b4 	movhi	r2,2054
+ 803deb8:	10f95117 	ldw	r3,-6844(r2)
+ 803debc:	008201b4 	movhi	r2,2054
+ 803dec0:	10b77017 	ldw	r2,-8768(r2)
+ 803dec4:	10800a17 	ldw	r2,40(r2)
+ 803dec8:	1008d63a 	srli	r4,r2,24
+ 803decc:	008201b4 	movhi	r2,2054
+ 803ded0:	10b77017 	ldw	r2,-8768(r2)
+ 803ded4:	10800a17 	ldw	r2,40(r2)
+ 803ded8:	1004d23a 	srli	r2,r2,8
+ 803dedc:	10bfc00c 	andi	r2,r2,65280
+ 803dee0:	2088b03a 	or	r4,r4,r2
+ 803dee4:	008201b4 	movhi	r2,2054
+ 803dee8:	10b77017 	ldw	r2,-8768(r2)
+ 803deec:	10800a17 	ldw	r2,40(r2)
+ 803def0:	1004923a 	slli	r2,r2,8
+ 803def4:	10803fec 	andhi	r2,r2,255
+ 803def8:	2088b03a 	or	r4,r4,r2
+ 803defc:	008201b4 	movhi	r2,2054
+ 803df00:	10b77017 	ldw	r2,-8768(r2)
+ 803df04:	10800a17 	ldw	r2,40(r2)
+ 803df08:	1004963a 	slli	r2,r2,24
+ 803df0c:	2084b03a 	or	r2,r4,r2
+ 803df10:	1887883a 	add	r3,r3,r2
+ 803df14:	e0bfff17 	ldw	r2,-4(fp)
+ 803df18:	10800017 	ldw	r2,0(r2)
+ 803df1c:	1008d63a 	srli	r4,r2,24
+ 803df20:	e0bfff17 	ldw	r2,-4(fp)
+ 803df24:	10800017 	ldw	r2,0(r2)
+ 803df28:	1004d23a 	srli	r2,r2,8
+ 803df2c:	10bfc00c 	andi	r2,r2,65280
+ 803df30:	2088b03a 	or	r4,r4,r2
+ 803df34:	e0bfff17 	ldw	r2,-4(fp)
+ 803df38:	10800017 	ldw	r2,0(r2)
+ 803df3c:	1004923a 	slli	r2,r2,8
+ 803df40:	10803fec 	andhi	r2,r2,255
+ 803df44:	2088b03a 	or	r4,r4,r2
+ 803df48:	e0bfff17 	ldw	r2,-4(fp)
+ 803df4c:	10800017 	ldw	r2,0(r2)
+ 803df50:	1004963a 	slli	r2,r2,24
+ 803df54:	2084b03a 	or	r2,r4,r2
+ 803df58:	1885883a 	add	r2,r3,r2
+ 803df5c:	01400c84 	movi	r5,50
+ 803df60:	1009883a 	mov	r4,r2
+ 803df64:	800d05c0 	call	800d05c <__umodsi3>
+ 803df68:	10c00044 	addi	r3,r2,1
+ 803df6c:	e0bfff17 	ldw	r2,-4(fp)
+ 803df70:	10c00315 	stw	r3,12(r2)
+               /* increment the count of running timers */
+               ++igmp_timers_are_running;            
+ 803df74:	d0a06917 	ldw	r2,-32348(gp)
+ 803df78:	10800044 	addi	r2,r2,1
+ 803df7c:	d0a06915 	stw	r2,-32348(gp)
+ 803df80:	00000106 	br	803df88 <igmpv1_input+0x18c>
+            continue;
+ 803df84:	0001883a 	nop
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+ 803df88:	e0bfff17 	ldw	r2,-4(fp)
+ 803df8c:	10800517 	ldw	r2,20(r2)
+ 803df90:	e0bfff15 	stw	r2,-4(fp)
+ 803df94:	e0bfff17 	ldw	r2,-4(fp)
+ 803df98:	103fbc1e 	bne	r2,zero,803de8c <igmpv1_input+0x90>
+            }   
+         }
+      }
+      rc = IGMP_OK;
+ 803df9c:	e03ffe15 	stw	zero,-8(fp)
+      break;
+ 803dfa0:	00002406 	br	803e034 <igmpv1_input+0x238>
+
+   case IGMP_HOST_MEMBERSHIP_REPORT:
+      ++igmpstats.igmpv1mode_v1_reports_rcvd;
+ 803dfa4:	008201b4 	movhi	r2,2054
+ 803dfa8:	10b77617 	ldw	r2,-8744(r2)
+ 803dfac:	10c00044 	addi	r3,r2,1
+ 803dfb0:	008201b4 	movhi	r2,2054
+ 803dfb4:	10f77615 	stw	r3,-8744(r2)
+      /*
+       * If we belong to the group being reported and have a 
+       * running timer for that group, stop our timer for that 
+       * group.
+       */
+      inm = lookup_mcast(igmp->igmp_group, netp);
+ 803dfb8:	e0bffb17 	ldw	r2,-20(fp)
+ 803dfbc:	10800117 	ldw	r2,4(r2)
+ 803dfc0:	e17ffd17 	ldw	r5,-12(fp)
+ 803dfc4:	1009883a 	mov	r4,r2
+ 803dfc8:	803c5040 	call	803c504 <lookup_mcast>
+ 803dfcc:	e0bfff15 	stw	r2,-4(fp)
+      if (inm != NULL) 
+ 803dfd0:	e0bfff17 	ldw	r2,-4(fp)
+ 803dfd4:	10000d26 	beq	r2,zero,803e00c <igmpv1_input+0x210>
+      {
+         if (inm->inm_timer > 0)
+ 803dfd8:	e0bfff17 	ldw	r2,-4(fp)
+ 803dfdc:	10800317 	ldw	r2,12(r2)
+ 803dfe0:	10000a26 	beq	r2,zero,803e00c <igmpv1_input+0x210>
+         {
+            inm->inm_timer = 0;
+ 803dfe4:	e0bfff17 	ldw	r2,-4(fp)
+ 803dfe8:	10000315 	stw	zero,12(r2)
+            /* decrement the count of running timers */
+            --igmp_timers_are_running;
+ 803dfec:	d0a06917 	ldw	r2,-32348(gp)
+ 803dff0:	10bfffc4 	addi	r2,r2,-1
+ 803dff4:	d0a06915 	stw	r2,-32348(gp)
+            ++igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer;
+ 803dff8:	008201b4 	movhi	r2,2054
+ 803dffc:	10b77717 	ldw	r2,-8740(r2)
+ 803e000:	10c00044 	addi	r3,r2,1
+ 803e004:	008201b4 	movhi	r2,2054
+ 803e008:	10f77715 	stw	r3,-8740(r2)
+         }
+      }
+      rc = IGMP_OK;
+ 803e00c:	e03ffe15 	stw	zero,-8(fp)
+      break;
+ 803e010:	00000806 	br	803e034 <igmpv1_input+0x238>
+      
+   default:
+      ++igmpstats.igmpv1mode_unknown_pkttype;
+ 803e014:	008201b4 	movhi	r2,2054
+ 803e018:	10b78417 	ldw	r2,-8688(r2)
+ 803e01c:	10c00044 	addi	r3,r2,1
+ 803e020:	008201b4 	movhi	r2,2054
+ 803e024:	10f78415 	stw	r3,-8688(r2)
+      rc = IGMP_ERR;
+ 803e028:	00bfffc4 	movi	r2,-1
+ 803e02c:	e0bffe15 	stw	r2,-8(fp)
+      break;   
+ 803e030:	0001883a 	nop
+   }
+
+   /* we're done with the received packet; return packet buffer back 
+    * to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803e034:	01000084 	movi	r4,2
+ 803e038:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 803e03c:	e13ffa17 	ldw	r4,-24(fp)
+ 803e040:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803e044:	01000084 	movi	r4,2
+ 803e048:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      
+   return rc;
+ 803e04c:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803e050:	e037883a 	mov	sp,fp
+ 803e054:	dfc00117 	ldw	ra,4(sp)
+ 803e058:	df000017 	ldw	fp,0(sp)
+ 803e05c:	dec00204 	addi	sp,sp,8
+ 803e060:	f800283a 	ret
+
+0803e064 <igmpv2_input>:
+ * from igmpv2_process_report (), IGMP_OK (for a received Leave Group
+ * message only), or IGMP_ERR (for a message of an "unknown" type).
+ */
+
+int igmpv2_input (PACKET p)
+{
+ 803e064:	defff904 	addi	sp,sp,-28
+ 803e068:	dfc00615 	stw	ra,24(sp)
+ 803e06c:	df000515 	stw	fp,20(sp)
+ 803e070:	df000504 	addi	fp,sp,20
+ 803e074:	e13ffb15 	stw	r4,-20(fp)
+   struct igmp * igmp;
+   struct ip * pip;
+   u_char type;
+   int rc;
+
+   pip = ip_head (p);    
+ 803e078:	e0bffb17 	ldw	r2,-20(fp)
+ 803e07c:	10800317 	ldw	r2,12(r2)
+ 803e080:	e0bffe15 	stw	r2,-8(fp)
+   igmp = (struct igmp *) (ip_data (pip));   
+ 803e084:	e0bffe17 	ldw	r2,-8(fp)
+ 803e088:	10800003 	ldbu	r2,0(r2)
+ 803e08c:	10803fcc 	andi	r2,r2,255
+ 803e090:	100490ba 	slli	r2,r2,2
+ 803e094:	10800f0c 	andi	r2,r2,60
+ 803e098:	e0fffe17 	ldw	r3,-8(fp)
+ 803e09c:	1885883a 	add	r2,r3,r2
+ 803e0a0:	e0bffd15 	stw	r2,-12(fp)
+   /* extract the IGMP packet type from received packet */
+   type = igmp->igmp_type;
+ 803e0a4:	e0bffd17 	ldw	r2,-12(fp)
+ 803e0a8:	10800003 	ldbu	r2,0(r2)
+ 803e0ac:	e0bffcc5 	stb	r2,-13(fp)
+
+   switch (type) 
+ 803e0b0:	e0bffcc3 	ldbu	r2,-13(fp)
+ 803e0b4:	10c004a0 	cmpeqi	r3,r2,18
+ 803e0b8:	18000e1e 	bne	r3,zero,803e0f4 <igmpv2_input+0x90>
+ 803e0bc:	10c004c8 	cmpgei	r3,r2,19
+ 803e0c0:	1800031e 	bne	r3,zero,803e0d0 <igmpv2_input+0x6c>
+ 803e0c4:	10800460 	cmpeqi	r2,r2,17
+ 803e0c8:	1000061e 	bne	r2,zero,803e0e4 <igmpv2_input+0x80>
+ 803e0cc:	00001406 	br	803e120 <igmpv2_input+0xbc>
+ 803e0d0:	10c005a0 	cmpeqi	r3,r2,22
+ 803e0d4:	1800071e 	bne	r3,zero,803e0f4 <igmpv2_input+0x90>
+ 803e0d8:	108005e0 	cmpeqi	r2,r2,23
+ 803e0dc:	1000091e 	bne	r2,zero,803e104 <igmpv2_input+0xa0>
+ 803e0e0:	00000f06 	br	803e120 <igmpv2_input+0xbc>
+   {
+      case IGMP_HOST_MEMBERSHIP_QUERY:
+         rc = igmpv2_process_query (p);
+ 803e0e4:	e13ffb17 	ldw	r4,-20(fp)
+ 803e0e8:	803e2840 	call	803e284 <igmpv2_process_query>
+ 803e0ec:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 803e0f0:	00001306 	br	803e140 <igmpv2_input+0xdc>
+
+      case IGMP_HOST_MEMBERSHIP_REPORT:
+      case IGMPv2_MEMBERSHIP_REPORT:
+         rc = igmpv2_process_report (p);
+ 803e0f4:	e13ffb17 	ldw	r4,-20(fp)
+ 803e0f8:	803e1700 	call	803e170 <igmpv2_process_report>
+ 803e0fc:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 803e100:	00000f06 	br	803e140 <igmpv2_input+0xdc>
+          * expect to receive such messages.  However, according to
+          * RFC 2236, some implementations of an older version of the 
+          * IGMPv2 specification send leave messages to the group 
+          * being left.  If we do receive such a message, we will 
+          * drop it. */       
+         ++igmpstats.igmpv2mode_v2_leave_msgs_rcvd;
+ 803e104:	008201b4 	movhi	r2,2054
+ 803e108:	10b77d17 	ldw	r2,-8716(r2)
+ 803e10c:	10c00044 	addi	r3,r2,1
+ 803e110:	008201b4 	movhi	r2,2054
+ 803e114:	10f77d15 	stw	r3,-8716(r2)
+         rc = IGMP_OK;
+ 803e118:	e03fff15 	stw	zero,-4(fp)
+         break;               
+ 803e11c:	00000806 	br	803e140 <igmpv2_input+0xdc>
+
+      default:     
+         ++igmpstats.igmpv2mode_unknown_pkttype;
+ 803e120:	008201b4 	movhi	r2,2054
+ 803e124:	10b78917 	ldw	r2,-8668(r2)
+ 803e128:	10c00044 	addi	r3,r2,1
+ 803e12c:	008201b4 	movhi	r2,2054
+ 803e130:	10f78915 	stw	r3,-8668(r2)
+         rc = IGMP_ERR;         
+ 803e134:	00bfffc4 	movi	r2,-1
+ 803e138:	e0bfff15 	stw	r2,-4(fp)
+         break;
+ 803e13c:	0001883a 	nop
+   } /* end SWITCH */
+
+   /* we're done processing the received packet; return packet buffer 
+    * back to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+ 803e140:	01000084 	movi	r4,2
+ 803e144:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   pk_free(p);
+ 803e148:	e13ffb17 	ldw	r4,-20(fp)
+ 803e14c:	80287480 	call	8028748 <pk_free>
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+ 803e150:	01000084 	movi	r4,2
+ 803e154:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   
+   return rc;
+ 803e158:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803e15c:	e037883a 	mov	sp,fp
+ 803e160:	dfc00117 	ldw	ra,4(sp)
+ 803e164:	df000017 	ldw	fp,0(sp)
+ 803e168:	dec00204 	addi	sp,sp,8
+ 803e16c:	f800283a 	ret
+
+0803e170 <igmpv2_process_report>:
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+
+int igmpv2_process_report (PACKET p)
+{
+ 803e170:	defff904 	addi	sp,sp,-28
+ 803e174:	dfc00615 	stw	ra,24(sp)
+ 803e178:	df000515 	stw	fp,20(sp)
+ 803e17c:	df000504 	addi	fp,sp,20
+ 803e180:	e13ffb15 	stw	r4,-20(fp)
+   struct igmp * igmp;
+   struct ip * pip;
+   NET netp;
+   struct in_multi * inm;
+
+   netp = p->net;
+ 803e184:	e0bffb17 	ldw	r2,-20(fp)
+ 803e188:	10800617 	ldw	r2,24(r2)
+ 803e18c:	e0bfff15 	stw	r2,-4(fp)
+   pip = ip_head (p);
+ 803e190:	e0bffb17 	ldw	r2,-20(fp)
+ 803e194:	10800317 	ldw	r2,12(r2)
+ 803e198:	e0bffe15 	stw	r2,-8(fp)
+   igmp = (struct igmp *) (ip_data (pip));   
+ 803e19c:	e0bffe17 	ldw	r2,-8(fp)
+ 803e1a0:	10800003 	ldbu	r2,0(r2)
+ 803e1a4:	10803fcc 	andi	r2,r2,255
+ 803e1a8:	100490ba 	slli	r2,r2,2
+ 803e1ac:	10800f0c 	andi	r2,r2,60
+ 803e1b0:	e0fffe17 	ldw	r3,-8(fp)
+ 803e1b4:	1885883a 	add	r2,r3,r2
+ 803e1b8:	e0bffd15 	stw	r2,-12(fp)
+    * processing IGMPv2 packets (it has "downgraded" itself because
+    * there are IGMPv1 routers on that network); however, we do not
+    * know that, and hence we don't cancel our timer (for the 
+    * subsequent transmission of a IGMPv1 report).
+    */
+   inm = lookup_mcast(igmp->igmp_group, netp);
+ 803e1bc:	e0bffd17 	ldw	r2,-12(fp)
+ 803e1c0:	10800117 	ldw	r2,4(r2)
+ 803e1c4:	e17fff17 	ldw	r5,-4(fp)
+ 803e1c8:	1009883a 	mov	r4,r2
+ 803e1cc:	803c5040 	call	803c504 <lookup_mcast>
+ 803e1d0:	e0bffc15 	stw	r2,-16(fp)
+   if (inm != NULL) 
+ 803e1d4:	e0bffc17 	ldw	r2,-16(fp)
+ 803e1d8:	10001f26 	beq	r2,zero,803e258 <igmpv2_process_report+0xe8>
+   {
+      if (inm->inm_timer != 0)
+ 803e1dc:	e0bffc17 	ldw	r2,-16(fp)
+ 803e1e0:	10800317 	ldw	r2,12(r2)
+ 803e1e4:	10001626 	beq	r2,zero,803e240 <igmpv2_process_report+0xd0>
+      {
+         /* we have a timer running */
+         if (!(netp->igmpv1_rtr_present && 
+ 803e1e8:	e0bfff17 	ldw	r2,-4(fp)
+ 803e1ec:	10802d03 	ldbu	r2,180(r2)
+ 803e1f0:	10803fcc 	andi	r2,r2,255
+ 803e1f4:	10000526 	beq	r2,zero,803e20c <igmpv2_process_report+0x9c>
+             igmp->igmp_type == IGMPv2_MEMBERSHIP_REPORT))
+ 803e1f8:	e0bffd17 	ldw	r2,-12(fp)
+ 803e1fc:	10800003 	ldbu	r2,0(r2)
+         if (!(netp->igmpv1_rtr_present && 
+ 803e200:	10803fcc 	andi	r2,r2,255
+ 803e204:	108005a0 	cmpeqi	r2,r2,22
+ 803e208:	1000181e 	bne	r2,zero,803e26c <igmpv2_process_report+0xfc>
+         {
+            /* cancel timer */
+            inm->inm_timer = 0;
+ 803e20c:	e0bffc17 	ldw	r2,-16(fp)
+ 803e210:	10000315 	stw	zero,12(r2)
+            /* decrement the count of running timers */
+            --igmp_timers_are_running;
+ 803e214:	d0a06917 	ldw	r2,-32348(gp)
+ 803e218:	10bfffc4 	addi	r2,r2,-1
+ 803e21c:	d0a06915 	stw	r2,-32348(gp)
+            /* indicate that we are not the last host to send a 
+             * report for this group */
+            inm->last2send_report = IGMP_FALSE;
+ 803e220:	e0bffc17 	ldw	r2,-16(fp)
+ 803e224:	10000405 	stb	zero,16(r2)
+            ++igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer;
+ 803e228:	008201b4 	movhi	r2,2054
+ 803e22c:	10b77b17 	ldw	r2,-8724(r2)
+ 803e230:	10c00044 	addi	r3,r2,1
+ 803e234:	008201b4 	movhi	r2,2054
+ 803e238:	10f77b15 	stw	r3,-8724(r2)
+ 803e23c:	00000b06 	br	803e26c <igmpv2_process_report+0xfc>
+      else
+      {
+         /* we don't have a timer running; perhaps the source
+          * host has just joined the group, and has sent an
+          * unsolicited report */
+         ++igmpstats.igmpv2mode_v12_reports_rcvd_no_timer;   
+ 803e240:	008201b4 	movhi	r2,2054
+ 803e244:	10b77c17 	ldw	r2,-8720(r2)
+ 803e248:	10c00044 	addi	r3,r2,1
+ 803e24c:	008201b4 	movhi	r2,2054
+ 803e250:	10f77c15 	stw	r3,-8720(r2)
+ 803e254:	00000506 	br	803e26c <igmpv2_process_report+0xfc>
+       * on that interface.  Even if imperfect filtering at the 
+       * device level causes reports for unregistered groups to 
+       * be passed up to the IP module, ip_rcv_phase2 () is 
+       * responsible for dropping them, and so we should never
+       * receive such packets. */
+      ++igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd;
+ 803e258:	008201b4 	movhi	r2,2054
+ 803e25c:	10b78717 	ldw	r2,-8676(r2)
+ 803e260:	10c00044 	addi	r3,r2,1
+ 803e264:	008201b4 	movhi	r2,2054
+ 803e268:	10f78715 	stw	r3,-8676(r2)
+   }
+   
+   return IGMP_OK;   
+ 803e26c:	0005883a 	mov	r2,zero
+}
+ 803e270:	e037883a 	mov	sp,fp
+ 803e274:	dfc00117 	ldw	ra,4(sp)
+ 803e278:	df000017 	ldw	fp,0(sp)
+ 803e27c:	dec00204 	addi	sp,sp,8
+ 803e280:	f800283a 	ret
+
+0803e284 <igmpv2_process_query>:
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+
+int igmpv2_process_query (PACKET p)
+{
+ 803e284:	defff804 	addi	sp,sp,-32
+ 803e288:	dfc00715 	stw	ra,28(sp)
+ 803e28c:	df000615 	stw	fp,24(sp)
+ 803e290:	df000604 	addi	fp,sp,24
+ 803e294:	e13ffa15 	stw	r4,-24(fp)
+   NET netp;
+   u_short max_resp_time;
+   u_char process_all;
+   struct in_multi * inm;
+
+   netp = p->net;
+ 803e298:	e0bffa17 	ldw	r2,-24(fp)
+ 803e29c:	10800617 	ldw	r2,24(r2)
+ 803e2a0:	e0bffd15 	stw	r2,-12(fp)
+   pip = ip_head (p);
+ 803e2a4:	e0bffa17 	ldw	r2,-24(fp)
+ 803e2a8:	10800317 	ldw	r2,12(r2)
+ 803e2ac:	e0bffc15 	stw	r2,-16(fp)
+   igmp = (struct igmp *) (ip_data (pip));
+ 803e2b0:	e0bffc17 	ldw	r2,-16(fp)
+ 803e2b4:	10800003 	ldbu	r2,0(r2)
+ 803e2b8:	10803fcc 	andi	r2,r2,255
+ 803e2bc:	100490ba 	slli	r2,r2,2
+ 803e2c0:	10800f0c 	andi	r2,r2,60
+ 803e2c4:	e0fffc17 	ldw	r3,-16(fp)
+ 803e2c8:	1885883a 	add	r2,r3,r2
+ 803e2cc:	e0bffb15 	stw	r2,-20(fp)
+
+   if (igmp->igmp_code == 0)
+ 803e2d0:	e0bffb17 	ldw	r2,-20(fp)
+ 803e2d4:	10800043 	ldbu	r2,1(r2)
+ 803e2d8:	10803fcc 	andi	r2,r2,255
+ 803e2dc:	1000101e 	bne	r2,zero,803e320 <igmpv2_process_query+0x9c>
+   {
+      /* this is a IGMPv1 Host Membership Query */
+      netp->igmpv1_rtr_present = IGMP_TRUE;
+ 803e2e0:	e0bffd17 	ldw	r2,-12(fp)
+ 803e2e4:	00c00044 	movi	r3,1
+ 803e2e8:	10c02d05 	stb	r3,180(r2)
+      netp->igmpv1_query_rcvd_time = cticks;      
+ 803e2ec:	d0e07d17 	ldw	r3,-32268(gp)
+ 803e2f0:	e0bffd17 	ldw	r2,-12(fp)
+ 803e2f4:	10c02e15 	stw	r3,184(r2)
+      ++igmpstats.igmpv2mode_v1_queries_rcvd;
+ 803e2f8:	008201b4 	movhi	r2,2054
+ 803e2fc:	10b77817 	ldw	r2,-8736(r2)
+ 803e300:	10c00044 	addi	r3,r2,1
+ 803e304:	008201b4 	movhi	r2,2054
+ 803e308:	10f77815 	stw	r3,-8736(r2)
+      /* set maximum time to respond to the equivalent of 10 
+       * seconds worth of "ticks" (the timeout routine is
+       * intended to be invoked PR_FASTHZ (5) times a second,
+       * so each tick is equal to 200 ms) */
+      max_resp_time = IGMP_MAX_HOST_REPORT_DELAY * PR_FASTHZ;
+ 803e30c:	00800c84 	movi	r2,50
+ 803e310:	e0bfff8d 	sth	r2,-2(fp)
+      process_all = IGMP_TRUE;
+ 803e314:	00800044 	movi	r2,1
+ 803e318:	e0bfff45 	stb	r2,-3(fp)
+ 803e31c:	00001806 	br	803e380 <igmpv2_process_query+0xfc>
+   }
+   else
+   {
+      /* this is either a IGMPv2 General Query or 
+       * a IGMPv2 Group-Specific Query */
+      if (igmp->igmp_group == 0)
+ 803e320:	e0bffb17 	ldw	r2,-20(fp)
+ 803e324:	10800117 	ldw	r2,4(r2)
+ 803e328:	1000081e 	bne	r2,zero,803e34c <igmpv2_process_query+0xc8>
+      {
+         /* this is a IGMPv2 General Query */
+         ++igmpstats.igmpv2mode_v2_general_queries_rcvd;
+ 803e32c:	008201b4 	movhi	r2,2054
+ 803e330:	10b77917 	ldw	r2,-8732(r2)
+ 803e334:	10c00044 	addi	r3,r2,1
+ 803e338:	008201b4 	movhi	r2,2054
+ 803e33c:	10f77915 	stw	r3,-8732(r2)
+         process_all = IGMP_TRUE;
+ 803e340:	00800044 	movi	r2,1
+ 803e344:	e0bfff45 	stb	r2,-3(fp)
+ 803e348:	00000606 	br	803e364 <igmpv2_process_query+0xe0>
+      }
+      else
+      {
+         /* this is a IGMPv2 Group-Specific Query */       
+         ++igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd;
+ 803e34c:	008201b4 	movhi	r2,2054
+ 803e350:	10b77a17 	ldw	r2,-8728(r2)
+ 803e354:	10c00044 	addi	r3,r2,1
+ 803e358:	008201b4 	movhi	r2,2054
+ 803e35c:	10f77a15 	stw	r3,-8728(r2)
+         process_all = IGMP_FALSE;
+ 803e360:	e03fff45 	stb	zero,-3(fp)
+       * IGMPv2 General Query or a IGMPv2 Group-Specific Query,
+       * set maximum time to respond to value extracted 
+       * from received message. The value in the message
+       * is in tenths of a second.  max_resp_time is in
+       * units of ticks (where one tick is 200 ms) */
+      max_resp_time = (igmp->igmp_code * PR_FASTHZ) / 10;
+ 803e364:	e0bffb17 	ldw	r2,-20(fp)
+ 803e368:	10800043 	ldbu	r2,1(r2)
+ 803e36c:	10803fcc 	andi	r2,r2,255
+ 803e370:	1006d7fa 	srli	r3,r2,31
+ 803e374:	1885883a 	add	r2,r3,r2
+ 803e378:	1005d07a 	srai	r2,r2,1
+ 803e37c:	e0bfff8d 	sth	r2,-2(fp)
+   
+   /* process all entries in a link's multicast address linked
+    * list (pointed to by mc_list) as part of the response to
+    * the received IGMPv1 Host Membership Query or IGMPv2 General
+    * Query message */
+   if (process_all)
+ 803e380:	e0bfff43 	ldbu	r2,-3(fp)
+ 803e384:	10001726 	beq	r2,zero,803e3e4 <igmpv2_process_query+0x160>
+   {
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+ 803e388:	e0bffd17 	ldw	r2,-12(fp)
+ 803e38c:	10802c17 	ldw	r2,176(r2)
+ 803e390:	e0bffe15 	stw	r2,-8(fp)
+ 803e394:	00001006 	br	803e3d8 <igmpv2_process_query+0x154>
+      {
+         /* skip all IPv6 entries - they are indicated by 
+          * an IPv4 address field of 0 */
+         if (!(inm->inm_addr)) continue;
+ 803e398:	e0bffe17 	ldw	r2,-8(fp)
+ 803e39c:	10800017 	ldw	r2,0(r2)
+ 803e3a0:	10000926 	beq	r2,zero,803e3c8 <igmpv2_process_query+0x144>
+         /* skip IPv4 multicast address of 224.0.0.1 (note that
+          * the IPv4 address stored in inm_addr is in network 
+          * byte order */
+         if (inm->inm_addr != igmp_all_hosts_group)
+ 803e3a4:	e0bffe17 	ldw	r2,-8(fp)
+ 803e3a8:	10c00017 	ldw	r3,0(r2)
+ 803e3ac:	d0a06b17 	ldw	r2,-32340(gp)
+ 803e3b0:	18800626 	beq	r3,r2,803e3cc <igmpv2_process_query+0x148>
+            igmpv2_chk_set_timer (inm, max_resp_time);
+ 803e3b4:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e3b8:	100b883a 	mov	r5,r2
+ 803e3bc:	e13ffe17 	ldw	r4,-8(fp)
+ 803e3c0:	803e4440 	call	803e444 <igmpv2_chk_set_timer>
+ 803e3c4:	00000106 	br	803e3cc <igmpv2_process_query+0x148>
+         if (!(inm->inm_addr)) continue;
+ 803e3c8:	0001883a 	nop
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+ 803e3cc:	e0bffe17 	ldw	r2,-8(fp)
+ 803e3d0:	10800517 	ldw	r2,20(r2)
+ 803e3d4:	e0bffe15 	stw	r2,-8(fp)
+ 803e3d8:	e0bffe17 	ldw	r2,-8(fp)
+ 803e3dc:	103fee1e 	bne	r2,zero,803e398 <igmpv2_process_query+0x114>
+ 803e3e0:	00001206 	br	803e42c <igmpv2_process_query+0x1a8>
+   {
+      /* process one (for IGMPv2 Group-Specific Query) entry (the 
+       * one that corresponds to the address listed in the received 
+       * query) - it should be present in the link's multicast
+       * address list */
+      inm = lookup_mcast(igmp->igmp_group, netp);
+ 803e3e4:	e0bffb17 	ldw	r2,-20(fp)
+ 803e3e8:	10800117 	ldw	r2,4(r2)
+ 803e3ec:	e17ffd17 	ldw	r5,-12(fp)
+ 803e3f0:	1009883a 	mov	r4,r2
+ 803e3f4:	803c5040 	call	803c504 <lookup_mcast>
+ 803e3f8:	e0bffe15 	stw	r2,-8(fp)
+      if (inm != NULL)
+ 803e3fc:	e0bffe17 	ldw	r2,-8(fp)
+ 803e400:	10000526 	beq	r2,zero,803e418 <igmpv2_process_query+0x194>
+         igmpv2_chk_set_timer (inm, max_resp_time);
+ 803e404:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e408:	100b883a 	mov	r5,r2
+ 803e40c:	e13ffe17 	ldw	r4,-8(fp)
+ 803e410:	803e4440 	call	803e444 <igmpv2_chk_set_timer>
+ 803e414:	00000506 	br	803e42c <igmpv2_process_query+0x1a8>
+      else ++igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd;
+ 803e418:	008201b4 	movhi	r2,2054
+ 803e41c:	10b78617 	ldw	r2,-8680(r2)
+ 803e420:	10c00044 	addi	r3,r2,1
+ 803e424:	008201b4 	movhi	r2,2054
+ 803e428:	10f78615 	stw	r3,-8680(r2)
+   } /* end ELSE (process ALL) */
+   
+   /* return success; caller will the received packet back to the 
+    * free pool */
+   return IGMP_OK;
+ 803e42c:	0005883a 	mov	r2,zero
+}
+ 803e430:	e037883a 	mov	sp,fp
+ 803e434:	dfc00117 	ldw	ra,4(sp)
+ 803e438:	df000017 	ldw	fp,0(sp)
+ 803e43c:	dec00204 	addi	sp,sp,8
+ 803e440:	f800283a 	ret
+
+0803e444 <igmpv2_chk_set_timer>:
+ *
+ * OUTPUT: None.
+ */
+
+void igmpv2_chk_set_timer (struct in_multi * inm, u_short max_resp_time)
+{  
+ 803e444:	defffc04 	addi	sp,sp,-16
+ 803e448:	dfc00315 	stw	ra,12(sp)
+ 803e44c:	df000215 	stw	fp,8(sp)
+ 803e450:	df000204 	addi	fp,sp,8
+ 803e454:	e13fff15 	stw	r4,-4(fp)
+ 803e458:	2805883a 	mov	r2,r5
+ 803e45c:	e0bffe0d 	sth	r2,-8(fp)
+
+    * Otherwise, the current timer for this group is scheduled 
+    * to expire within the duration indicated in the Query 
+    * message, so we let it continue. 
+    */
+   if ((inm->inm_timer > max_resp_time) ||
+ 803e460:	e0bfff17 	ldw	r2,-4(fp)
+ 803e464:	10800317 	ldw	r2,12(r2)
+ 803e468:	e0fffe0b 	ldhu	r3,-8(fp)
+ 803e46c:	18800336 	bltu	r3,r2,803e47c <igmpv2_chk_set_timer+0x38>
+       (inm->inm_timer == 0))
+ 803e470:	e0bfff17 	ldw	r2,-4(fp)
+ 803e474:	10800317 	ldw	r2,12(r2)
+   if ((inm->inm_timer > max_resp_time) ||
+ 803e478:	1000381e 	bne	r2,zero,803e55c <igmpv2_chk_set_timer+0x118>
+   {
+      if (inm->inm_timer == 0) ++igmp_timers_are_running;
+ 803e47c:	e0bfff17 	ldw	r2,-4(fp)
+ 803e480:	10800317 	ldw	r2,12(r2)
+ 803e484:	1000031e 	bne	r2,zero,803e494 <igmpv2_chk_set_timer+0x50>
+ 803e488:	d0a06917 	ldw	r2,-32348(gp)
+ 803e48c:	10800044 	addi	r2,r2,1
+ 803e490:	d0a06915 	stw	r2,-32348(gp)
+      inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY (max_resp_time, inm->inm_addr);                     
+ 803e494:	008201b4 	movhi	r2,2054
+ 803e498:	10f95117 	ldw	r3,-6844(r2)
+ 803e49c:	008201b4 	movhi	r2,2054
+ 803e4a0:	10b77017 	ldw	r2,-8768(r2)
+ 803e4a4:	10800a17 	ldw	r2,40(r2)
+ 803e4a8:	1008d63a 	srli	r4,r2,24
+ 803e4ac:	008201b4 	movhi	r2,2054
+ 803e4b0:	10b77017 	ldw	r2,-8768(r2)
+ 803e4b4:	10800a17 	ldw	r2,40(r2)
+ 803e4b8:	1004d23a 	srli	r2,r2,8
+ 803e4bc:	10bfc00c 	andi	r2,r2,65280
+ 803e4c0:	2088b03a 	or	r4,r4,r2
+ 803e4c4:	008201b4 	movhi	r2,2054
+ 803e4c8:	10b77017 	ldw	r2,-8768(r2)
+ 803e4cc:	10800a17 	ldw	r2,40(r2)
+ 803e4d0:	1004923a 	slli	r2,r2,8
+ 803e4d4:	10803fec 	andhi	r2,r2,255
+ 803e4d8:	2088b03a 	or	r4,r4,r2
+ 803e4dc:	008201b4 	movhi	r2,2054
+ 803e4e0:	10b77017 	ldw	r2,-8768(r2)
+ 803e4e4:	10800a17 	ldw	r2,40(r2)
+ 803e4e8:	1004963a 	slli	r2,r2,24
+ 803e4ec:	2084b03a 	or	r2,r4,r2
+ 803e4f0:	1887883a 	add	r3,r3,r2
+ 803e4f4:	e0bfff17 	ldw	r2,-4(fp)
+ 803e4f8:	10800017 	ldw	r2,0(r2)
+ 803e4fc:	1008d63a 	srli	r4,r2,24
+ 803e500:	e0bfff17 	ldw	r2,-4(fp)
+ 803e504:	10800017 	ldw	r2,0(r2)
+ 803e508:	1004d23a 	srli	r2,r2,8
+ 803e50c:	10bfc00c 	andi	r2,r2,65280
+ 803e510:	2088b03a 	or	r4,r4,r2
+ 803e514:	e0bfff17 	ldw	r2,-4(fp)
+ 803e518:	10800017 	ldw	r2,0(r2)
+ 803e51c:	1004923a 	slli	r2,r2,8
+ 803e520:	10803fec 	andhi	r2,r2,255
+ 803e524:	2088b03a 	or	r4,r4,r2
+ 803e528:	e0bfff17 	ldw	r2,-4(fp)
+ 803e52c:	10800017 	ldw	r2,0(r2)
+ 803e530:	1004963a 	slli	r2,r2,24
+ 803e534:	2084b03a 	or	r2,r4,r2
+ 803e538:	1885883a 	add	r2,r3,r2
+ 803e53c:	e0fffe0b 	ldhu	r3,-8(fp)
+ 803e540:	180b883a 	mov	r5,r3
+ 803e544:	1009883a 	mov	r4,r2
+ 803e548:	800d05c0 	call	800d05c <__umodsi3>
+ 803e54c:	10c00044 	addi	r3,r2,1
+ 803e550:	e0bfff17 	ldw	r2,-4(fp)
+ 803e554:	10c00315 	stw	r3,12(r2)
+   }
+
+   return;
+ 803e558:	0001883a 	nop
+ 803e55c:	0001883a 	nop
+}
+ 803e560:	e037883a 	mov	sp,fp
+ 803e564:	dfc00117 	ldw	ra,4(sp)
+ 803e568:	df000017 	ldw	fp,0(sp)
+ 803e56c:	dec00204 	addi	sp,sp,8
+ 803e570:	f800283a 	ret
+
+0803e574 <igmpv2_chk4_rtr_alert_opt>:
+ *         the IP Router Alert option in the received
+ *         packet, and IGMP_FALSE otherwise.
+ */
+
+u_char igmpv2_chk4_rtr_alert_opt (struct ip * pip)
+{
+ 803e574:	defffb04 	addi	sp,sp,-20
+ 803e578:	df000415 	stw	fp,16(sp)
+ 803e57c:	df000404 	addi	fp,sp,16
+ 803e580:	e13ffc15 	stw	r4,-16(fp)
+   u_long * rtr_alert_optp;
+   u_char total_optlen;
+   u_char optlen;
+   u_char optval;
+
+   total_optlen = ip_hlen (pip) - sizeof (struct ip);
+ 803e584:	e0bffc17 	ldw	r2,-16(fp)
+ 803e588:	10800003 	ldbu	r2,0(r2)
+ 803e58c:	100490ba 	slli	r2,r2,2
+ 803e590:	10800f0c 	andi	r2,r2,60
+ 803e594:	10bffb04 	addi	r2,r2,-20
+ 803e598:	e0bffec5 	stb	r2,-5(fp)
+
+   if (total_optlen > 0)
+ 803e59c:	e0bffec3 	ldbu	r2,-5(fp)
+ 803e5a0:	10003e26 	beq	r2,zero,803e69c <igmpv2_chk4_rtr_alert_opt+0x128>
+   {
+      /* point to just past the end of the IP header */
+      optp = (u_char *) (pip + 1);
+ 803e5a4:	e0bffc17 	ldw	r2,-16(fp)
+ 803e5a8:	10800504 	addi	r2,r2,20
+ 803e5ac:	e0bfff15 	stw	r2,-4(fp)
+  
+      while (total_optlen > 0)
+ 803e5b0:	00003806 	br	803e694 <igmpv2_chk4_rtr_alert_opt+0x120>
+      {
+         /* only the lowermost 5 bits are significant */    
+         optval = (*optp) & IPOPT_TYPE_MASK;
+ 803e5b4:	e0bfff17 	ldw	r2,-4(fp)
+ 803e5b8:	10800003 	ldbu	r2,0(r2)
+ 803e5bc:	108007cc 	andi	r2,r2,31
+ 803e5c0:	e0bffe45 	stb	r2,-7(fp)
+         switch (optval)
+ 803e5c4:	e0bffe43 	ldbu	r2,-7(fp)
+ 803e5c8:	10c00060 	cmpeqi	r3,r2,1
+ 803e5cc:	1800071e 	bne	r3,zero,803e5ec <igmpv2_chk4_rtr_alert_opt+0x78>
+ 803e5d0:	10c00520 	cmpeqi	r3,r2,20
+ 803e5d4:	1800081e 	bne	r3,zero,803e5f8 <igmpv2_chk4_rtr_alert_opt+0x84>
+ 803e5d8:	1000201e 	bne	r2,zero,803e65c <igmpv2_chk4_rtr_alert_opt+0xe8>
+         {
+            case EOL_OPT:
+               /* we've encountered the End of Option List option, 
+                * and so setting optlen isn't necessary */
+               optlen = 1;
+ 803e5dc:	00800044 	movi	r2,1
+ 803e5e0:	e0bffe85 	stb	r2,-6(fp)
+               /* we're done - we couldn't locate the IP Router Alert 
+                * option in this IP header */
+               return IGMP_FALSE;
+ 803e5e4:	0005883a 	mov	r2,zero
+ 803e5e8:	00002d06 	br	803e6a0 <igmpv2_chk4_rtr_alert_opt+0x12c>
+         
+            case NOOP_OPT:
+               /* skip past the one byte of the No Operation option */
+               optlen = 1;
+ 803e5ec:	00800044 	movi	r2,1
+ 803e5f0:	e0bffe85 	stb	r2,-6(fp)
+               break;
+ 803e5f4:	00001f06 	br	803e674 <igmpv2_chk4_rtr_alert_opt+0x100>
+         
+            case IP_RTR_ALERT_OPT:
+               rtr_alert_optp = (u_long *) optp; 
+ 803e5f8:	e0bfff17 	ldw	r2,-4(fp)
+ 803e5fc:	e0bffd15 	stw	r2,-12(fp)
+               if ((ntohl (*rtr_alert_optp)) == IP_RTR_ALERT_OPT_DATA)
+ 803e600:	e0bffd17 	ldw	r2,-12(fp)
+ 803e604:	10800017 	ldw	r2,0(r2)
+ 803e608:	1006d63a 	srli	r3,r2,24
+ 803e60c:	e0bffd17 	ldw	r2,-12(fp)
+ 803e610:	10800017 	ldw	r2,0(r2)
+ 803e614:	1004d23a 	srli	r2,r2,8
+ 803e618:	10bfc00c 	andi	r2,r2,65280
+ 803e61c:	1886b03a 	or	r3,r3,r2
+ 803e620:	e0bffd17 	ldw	r2,-12(fp)
+ 803e624:	10800017 	ldw	r2,0(r2)
+ 803e628:	1004923a 	slli	r2,r2,8
+ 803e62c:	10803fec 	andhi	r2,r2,255
+ 803e630:	1886b03a 	or	r3,r3,r2
+ 803e634:	e0bffd17 	ldw	r2,-12(fp)
+ 803e638:	10800017 	ldw	r2,0(r2)
+ 803e63c:	1004963a 	slli	r2,r2,24
+ 803e640:	1886b03a 	or	r3,r3,r2
+ 803e644:	00a50134 	movhi	r2,37892
+ 803e648:	1880021e 	bne	r3,r2,803e654 <igmpv2_chk4_rtr_alert_opt+0xe0>
+                  /* found the option, return success */
+                  return IGMP_TRUE;
+ 803e64c:	00800044 	movi	r2,1
+ 803e650:	00001306 	br	803e6a0 <igmpv2_chk4_rtr_alert_opt+0x12c>
+               else return IGMP_FALSE;
+ 803e654:	0005883a 	mov	r2,zero
+ 803e658:	00001106 	br	803e6a0 <igmpv2_chk4_rtr_alert_opt+0x12c>
+          
+            default:
+               /* extract the length of the current option, and compute
+                * the total length of this option */
+               optlen = (*(optp + 1)) + 2;
+ 803e65c:	e0bfff17 	ldw	r2,-4(fp)
+ 803e660:	10800044 	addi	r2,r2,1
+ 803e664:	10800003 	ldbu	r2,0(r2)
+ 803e668:	10800084 	addi	r2,r2,2
+ 803e66c:	e0bffe85 	stb	r2,-6(fp)
+               break;
+ 803e670:	0001883a 	nop
+         }
+         
+         /* skip past the bytes associated with the current option to 
+          * point to the next option. */
+         optp += optlen;
+ 803e674:	e0bffe83 	ldbu	r2,-6(fp)
+ 803e678:	e0ffff17 	ldw	r3,-4(fp)
+ 803e67c:	1885883a 	add	r2,r3,r2
+ 803e680:	e0bfff15 	stw	r2,-4(fp)
+         total_optlen -= optlen;
+ 803e684:	e0fffec3 	ldbu	r3,-5(fp)
+ 803e688:	e0bffe83 	ldbu	r2,-6(fp)
+ 803e68c:	1885c83a 	sub	r2,r3,r2
+ 803e690:	e0bffec5 	stb	r2,-5(fp)
+      while (total_optlen > 0)
+ 803e694:	e0bffec3 	ldbu	r2,-5(fp)
+ 803e698:	103fc61e 	bne	r2,zero,803e5b4 <igmpv2_chk4_rtr_alert_opt+0x40>
+      } /* end WHILE */
+   }
+
+   /* didn't find IP Alert option in IP header of rcvd packet */
+   return IGMP_FALSE;
+ 803e69c:	0005883a 	mov	r2,zero
+}
+ 803e6a0:	e037883a 	mov	sp,fp
+ 803e6a4:	df000017 	ldw	fp,0(sp)
+ 803e6a8:	dec00104 	addi	sp,sp,4
+ 803e6ac:	f800283a 	ret
+
+0803e6b0 <IPADDR_TO_NETP>:
+ * RETURNS: 
+ */
+
+void
+IPADDR_TO_NETP(ip_addr addr, NET* netp)
+{
+ 803e6b0:	defffc04 	addi	sp,sp,-16
+ 803e6b4:	df000315 	stw	fp,12(sp)
+ 803e6b8:	df000304 	addi	fp,sp,12
+ 803e6bc:	e13ffe15 	stw	r4,-8(fp)
+ 803e6c0:	e17ffd15 	stw	r5,-12(fp)
+   u_short  idx   =  0;
+ 803e6c4:	e03fff8d 	sth	zero,-2(fp)
+   *netp = nets[idx];
+ 803e6c8:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e6cc:	100690ba 	slli	r3,r2,2
+ 803e6d0:	008201b4 	movhi	r2,2054
+ 803e6d4:	1885883a 	add	r2,r3,r2
+ 803e6d8:	10f77017 	ldw	r3,-8768(r2)
+ 803e6dc:	e0bffd17 	ldw	r2,-12(fp)
+ 803e6e0:	10c00015 	stw	r3,0(r2)
+/*
+ * If ip address is not specified, return the first intfc that supports
+ * multicast
+ */
+   if (addr == AADDR) 
+ 803e6e4:	e0bffe17 	ldw	r2,-8(fp)
+ 803e6e8:	1000281e 	bne	r2,zero,803e78c <IPADDR_TO_NETP+0xdc>
+   {
+      for (idx = 0; idx < ifNumber; idx++)
+ 803e6ec:	e03fff8d 	sth	zero,-2(fp)
+ 803e6f0:	00001206 	br	803e73c <IPADDR_TO_NETP+0x8c>
+      {
+         if (nets[idx]->n_mcastlist)
+ 803e6f4:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e6f8:	100690ba 	slli	r3,r2,2
+ 803e6fc:	008201b4 	movhi	r2,2054
+ 803e700:	1885883a 	add	r2,r3,r2
+ 803e704:	10b77017 	ldw	r2,-8768(r2)
+ 803e708:	10802b17 	ldw	r2,172(r2)
+ 803e70c:	10000826 	beq	r2,zero,803e730 <IPADDR_TO_NETP+0x80>
+         {
+            *netp = nets[idx];
+ 803e710:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e714:	100690ba 	slli	r3,r2,2
+ 803e718:	008201b4 	movhi	r2,2054
+ 803e71c:	1885883a 	add	r2,r3,r2
+ 803e720:	10f77017 	ldw	r3,-8768(r2)
+ 803e724:	e0bffd17 	ldw	r2,-12(fp)
+ 803e728:	10c00015 	stw	r3,0(r2)
+            break;
+ 803e72c:	00002006 	br	803e7b0 <IPADDR_TO_NETP+0x100>
+      for (idx = 0; idx < ifNumber; idx++)
+ 803e730:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e734:	10800044 	addi	r2,r2,1
+ 803e738:	e0bfff8d 	sth	r2,-2(fp)
+ 803e73c:	e0ffff8b 	ldhu	r3,-2(fp)
+ 803e740:	d0a06717 	ldw	r2,-32356(gp)
+ 803e744:	18bfeb36 	bltu	r3,r2,803e6f4 <IPADDR_TO_NETP+0x44>
+         }
+         else
+            *netp = nets[idx];
+      }
+   }
+}
+ 803e748:	00001906 	br	803e7b0 <IPADDR_TO_NETP+0x100>
+         idx++;
+ 803e74c:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e750:	10800044 	addi	r2,r2,1
+ 803e754:	e0bfff8d 	sth	r2,-2(fp)
+         if (idx >= ifNumber)
+ 803e758:	e0ffff8b 	ldhu	r3,-2(fp)
+ 803e75c:	d0a06717 	ldw	r2,-32356(gp)
+ 803e760:	18800336 	bltu	r3,r2,803e770 <IPADDR_TO_NETP+0xc0>
+            *netp = NULL;
+ 803e764:	e0bffd17 	ldw	r2,-12(fp)
+ 803e768:	10000015 	stw	zero,0(r2)
+            break;
+ 803e76c:	00001006 	br	803e7b0 <IPADDR_TO_NETP+0x100>
+            *netp = nets[idx];
+ 803e770:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803e774:	100690ba 	slli	r3,r2,2
+ 803e778:	008201b4 	movhi	r2,2054
+ 803e77c:	1885883a 	add	r2,r3,r2
+ 803e780:	10f77017 	ldw	r3,-8768(r2)
+ 803e784:	e0bffd17 	ldw	r2,-12(fp)
+ 803e788:	10c00015 	stw	r3,0(r2)
+      while ((*netp != NULL) && ((*netp)->n_ipaddr != addr))
+ 803e78c:	e0bffd17 	ldw	r2,-12(fp)
+ 803e790:	10800017 	ldw	r2,0(r2)
+ 803e794:	10000626 	beq	r2,zero,803e7b0 <IPADDR_TO_NETP+0x100>
+ 803e798:	e0bffd17 	ldw	r2,-12(fp)
+ 803e79c:	10800017 	ldw	r2,0(r2)
+ 803e7a0:	10800a17 	ldw	r2,40(r2)
+ 803e7a4:	e0fffe17 	ldw	r3,-8(fp)
+ 803e7a8:	18bfe81e 	bne	r3,r2,803e74c <IPADDR_TO_NETP+0x9c>
+}
+ 803e7ac:	00000006 	br	803e7b0 <IPADDR_TO_NETP+0x100>
+ 803e7b0:	0001883a 	nop
+ 803e7b4:	e037883a 	mov	sp,fp
+ 803e7b8:	df000017 	ldw	fp,0(sp)
+ 803e7bc:	dec00104 	addi	sp,sp,4
+ 803e7c0:	f800283a 	ret
+
+0803e7c4 <ip_setmoptions>:
+ * RETURNS: 
+ */
+
+int
+ip_setmoptions(int optname, struct socket * so, void * val)
+{
+ 803e7c4:	defff304 	addi	sp,sp,-52
+ 803e7c8:	dfc00c15 	stw	ra,48(sp)
+ 803e7cc:	df000b15 	stw	fp,44(sp)
+ 803e7d0:	dc000a15 	stw	r16,40(sp)
+ 803e7d4:	df000b04 	addi	fp,sp,44
+ 803e7d8:	e13ff715 	stw	r4,-36(fp)
+ 803e7dc:	e17ff615 	stw	r5,-40(fp)
+ 803e7e0:	e1bff515 	stw	r6,-44(fp)
+   int   error =  0;
+ 803e7e4:	e03ffe15 	stw	zero,-8(fp)
+   u_short  i;
+   struct ip_mreq *  mreq;
+   struct net *   netp  =  NULL;
+ 803e7e8:	e03ff815 	stw	zero,-32(fp)
+   struct ip_moptions * imo   =  so->inp_moptions;
+ 803e7ec:	e0bff617 	ldw	r2,-40(fp)
+ 803e7f0:	10800317 	ldw	r2,12(r2)
+ 803e7f4:	e0bffc15 	stw	r2,-16(fp)
+   struct ip_moptions **imop  =  &so->inp_moptions;
+ 803e7f8:	e0bff617 	ldw	r2,-40(fp)
+ 803e7fc:	10800304 	addi	r2,r2,12
+ 803e800:	e0bffb15 	stw	r2,-20(fp)
+   ip_addr addr;
+
+
+   if (imo == NULL) 
+ 803e804:	e0bffc17 	ldw	r2,-16(fp)
+ 803e808:	1000141e 	bne	r2,zero,803e85c <ip_setmoptions+0x98>
+   {
+   /*
+    * No multicast option buffer attached to the pcb;
+    * allocate one and initialize to default values.
+    */
+      imo = (struct ip_moptions*)IM_ALLOC(sizeof(*imo));
+ 803e80c:	01001604 	movi	r4,88
+ 803e810:	802982c0 	call	802982c <npalloc>
+ 803e814:	e0bffc15 	stw	r2,-16(fp)
+
+      if (imo == NULL)
+ 803e818:	e0bffc17 	ldw	r2,-16(fp)
+ 803e81c:	1000021e 	bne	r2,zero,803e828 <ip_setmoptions+0x64>
+         return (ENOBUFS);
+ 803e820:	00801a44 	movi	r2,105
+ 803e824:	00014906 	br	803ed4c <ip_setmoptions+0x588>
+      *imop = imo;
+ 803e828:	e0bffb17 	ldw	r2,-20(fp)
+ 803e82c:	e0fffc17 	ldw	r3,-16(fp)
+ 803e830:	10c00015 	stw	r3,0(r2)
+      imo->imo_multicast_netp = NULL;
+ 803e834:	e0bffc17 	ldw	r2,-16(fp)
+ 803e838:	10000015 	stw	zero,0(r2)
+      imo->imo_multicast_ttl = IP_DEFAULT_MULTICAST_TTL;
+ 803e83c:	e0bffc17 	ldw	r2,-16(fp)
+ 803e840:	00c00044 	movi	r3,1
+ 803e844:	10c00105 	stb	r3,4(r2)
+      imo->imo_multicast_loop = IP_DEFAULT_MULTICAST_LOOP;
+ 803e848:	e0bffc17 	ldw	r2,-16(fp)
+ 803e84c:	00c00044 	movi	r3,1
+ 803e850:	10c00145 	stb	r3,5(r2)
+      imo->imo_num_memberships = 0;
+ 803e854:	e0bffc17 	ldw	r2,-16(fp)
+ 803e858:	1000018d 	sth	zero,6(r2)
+   }
+
+   switch (optname) 
+ 803e85c:	e0bff717 	ldw	r2,-36(fp)
+ 803e860:	10bffdc4 	addi	r2,r2,-9
+ 803e864:	10c00168 	cmpgeui	r3,r2,5
+ 803e868:	18011c1e 	bne	r3,zero,803ecdc <ip_setmoptions+0x518>
+ 803e86c:	100690ba 	slli	r3,r2,2
+ 803e870:	00820134 	movhi	r2,2052
+ 803e874:	1885883a 	add	r2,r3,r2
+ 803e878:	10ba2017 	ldw	r2,-6016(r2)
+ 803e87c:	1000683a 	jmp	r2
+ 803e880:	0803e894 	ori	zero,at,4002
+ 803e884:	0803e8fc 	xorhi	zero,at,4003
+ 803e888:	0803e910 	cmplti	zero,at,4004
+ 803e88c:	0803e944 	addi	zero,at,4005
+ 803e890:	0803eb08 	cmpgei	zero,at,4012
+
+   case IP_MULTICAST_IF:
+      /*
+       * Select the interface for outgoing multicast packets.
+       */
+      addr = *(ip_addr *)val;
+ 803e894:	e0bff517 	ldw	r2,-44(fp)
+ 803e898:	10800017 	ldw	r2,0(r2)
+ 803e89c:	e0bffa15 	stw	r2,-24(fp)
+         /*
+          * AADDR is used to remove a previous selection.
+          * When no interface is selected, a default one is
+          * chosen every time a multicast packet is sent.
+          */
+      if (addr == AADDR) 
+ 803e8a0:	e0bffa17 	ldw	r2,-24(fp)
+ 803e8a4:	1000031e 	bne	r2,zero,803e8b4 <ip_setmoptions+0xf0>
+      {
+         imo->imo_multicast_netp = NULL;
+ 803e8a8:	e0bffc17 	ldw	r2,-16(fp)
+ 803e8ac:	10000015 	stw	zero,0(r2)
+         break;
+ 803e8b0:	00010e06 	br	803ecec <ip_setmoptions+0x528>
+         /*
+          * The selected interface is identified by its local
+          * IP address.  Find the interface and confirm that
+          * it supports multicasting.
+          */
+      IPADDR_TO_NETP(addr, &netp);
+ 803e8b4:	e0bff804 	addi	r2,fp,-32
+ 803e8b8:	100b883a 	mov	r5,r2
+ 803e8bc:	e13ffa17 	ldw	r4,-24(fp)
+ 803e8c0:	803e6b00 	call	803e6b0 <IPADDR_TO_NETP>
+      if ((netp == NULL) || (netp->n_mcastlist) == NULL) 
+ 803e8c4:	e0bff817 	ldw	r2,-32(fp)
+ 803e8c8:	10000326 	beq	r2,zero,803e8d8 <ip_setmoptions+0x114>
+ 803e8cc:	e0bff817 	ldw	r2,-32(fp)
+ 803e8d0:	10802b17 	ldw	r2,172(r2)
+ 803e8d4:	1000031e 	bne	r2,zero,803e8e4 <ip_setmoptions+0x120>
+      {
+         error = EADDRNOTAVAIL;
+ 803e8d8:	00801f44 	movi	r2,125
+ 803e8dc:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803e8e0:	00010206 	br	803ecec <ip_setmoptions+0x528>
+      }
+      if (addr != AADDR) 
+ 803e8e4:	e0bffa17 	ldw	r2,-24(fp)
+ 803e8e8:	1000ff26 	beq	r2,zero,803ece8 <ip_setmoptions+0x524>
+         imo->imo_multicast_netp = netp;
+ 803e8ec:	e0fff817 	ldw	r3,-32(fp)
+ 803e8f0:	e0bffc17 	ldw	r2,-16(fp)
+ 803e8f4:	10c00015 	stw	r3,0(r2)
+      break;
+ 803e8f8:	0000fb06 	br	803ece8 <ip_setmoptions+0x524>
+
+   case IP_MULTICAST_TTL:
+      /*
+       * Set the IP time-to-live for outgoing multicast packets.
+       */
+      imo->imo_multicast_ttl = *(u_char *)val;
+ 803e8fc:	e0bff517 	ldw	r2,-44(fp)
+ 803e900:	10c00003 	ldbu	r3,0(r2)
+ 803e904:	e0bffc17 	ldw	r2,-16(fp)
+ 803e908:	10c00105 	stb	r3,4(r2)
+      break;
+ 803e90c:	0000f706 	br	803ecec <ip_setmoptions+0x528>
+   case IP_MULTICAST_LOOP:
+      /*
+       * Set the loopback flag for outgoing multicast packets.
+       * Must be zero or one.
+       */
+      if (*(u_char *)val > 1) 
+ 803e910:	e0bff517 	ldw	r2,-44(fp)
+ 803e914:	10800003 	ldbu	r2,0(r2)
+ 803e918:	10803fcc 	andi	r2,r2,255
+ 803e91c:	108000b0 	cmpltui	r2,r2,2
+ 803e920:	1000031e 	bne	r2,zero,803e930 <ip_setmoptions+0x16c>
+      {
+         error = EINVAL;
+ 803e924:	00800584 	movi	r2,22
+ 803e928:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803e92c:	0000ef06 	br	803ecec <ip_setmoptions+0x528>
+      }
+      imo->imo_multicast_loop = *(u_char *)(val);
+ 803e930:	e0bff517 	ldw	r2,-44(fp)
+ 803e934:	10c00003 	ldbu	r3,0(r2)
+ 803e938:	e0bffc17 	ldw	r2,-16(fp)
+ 803e93c:	10c00145 	stb	r3,5(r2)
+      break;
+ 803e940:	0000ea06 	br	803ecec <ip_setmoptions+0x528>
+   case IP_ADD_MEMBERSHIP:
+      /*
+       * Add a multicast group membership.
+       * Group must be a valid IP multicast address.
+       */
+      mreq = (struct ip_mreq *)val;
+ 803e944:	e0bff517 	ldw	r2,-44(fp)
+ 803e948:	e0bff915 	stw	r2,-28(fp)
+      if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) 
+ 803e94c:	e0bff917 	ldw	r2,-28(fp)
+ 803e950:	10800017 	ldw	r2,0(r2)
+ 803e954:	1006d63a 	srli	r3,r2,24
+ 803e958:	e0bff917 	ldw	r2,-28(fp)
+ 803e95c:	10800017 	ldw	r2,0(r2)
+ 803e960:	1004d23a 	srli	r2,r2,8
+ 803e964:	10bfc00c 	andi	r2,r2,65280
+ 803e968:	1886b03a 	or	r3,r3,r2
+ 803e96c:	e0bff917 	ldw	r2,-28(fp)
+ 803e970:	10800017 	ldw	r2,0(r2)
+ 803e974:	1004923a 	slli	r2,r2,8
+ 803e978:	10803fec 	andhi	r2,r2,255
+ 803e97c:	1886b03a 	or	r3,r3,r2
+ 803e980:	e0bff917 	ldw	r2,-28(fp)
+ 803e984:	10800017 	ldw	r2,0(r2)
+ 803e988:	1004963a 	slli	r2,r2,24
+ 803e98c:	1884b03a 	or	r2,r3,r2
+ 803e990:	10fc002c 	andhi	r3,r2,61440
+ 803e994:	00b80034 	movhi	r2,57344
+ 803e998:	18800326 	beq	r3,r2,803e9a8 <ip_setmoptions+0x1e4>
+      {
+         error = EINVAL;
+ 803e99c:	00800584 	movi	r2,22
+ 803e9a0:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803e9a4:	0000d106 	br	803ecec <ip_setmoptions+0x528>
+       * If no interface address was provided, use the interface of
+       * the route to the given multicast address.
+       * For the Iniche stack implementation, look for a default
+       * interface that supports multicast.
+       */
+      IPADDR_TO_NETP(mreq->imr_interface, &netp);
+ 803e9a8:	e0bff917 	ldw	r2,-28(fp)
+ 803e9ac:	10800117 	ldw	r2,4(r2)
+ 803e9b0:	e0fff804 	addi	r3,fp,-32
+ 803e9b4:	180b883a 	mov	r5,r3
+ 803e9b8:	1009883a 	mov	r4,r2
+ 803e9bc:	803e6b00 	call	803e6b0 <IPADDR_TO_NETP>
+      /*
+       * See if we found an interface, and confirm that it
+       * supports multicast.
+       */
+      if (netp == NULL || (netp->n_mcastlist) == NULL) 
+ 803e9c0:	e0bff817 	ldw	r2,-32(fp)
+ 803e9c4:	10000326 	beq	r2,zero,803e9d4 <ip_setmoptions+0x210>
+ 803e9c8:	e0bff817 	ldw	r2,-32(fp)
+ 803e9cc:	10802b17 	ldw	r2,172(r2)
+ 803e9d0:	1000031e 	bne	r2,zero,803e9e0 <ip_setmoptions+0x21c>
+      {
+         error = EADDRNOTAVAIL;
+ 803e9d4:	00801f44 	movi	r2,125
+ 803e9d8:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803e9dc:	0000c306 	br	803ecec <ip_setmoptions+0x528>
+      }
+      /*
+       * See if the membership already exists or if all the
+       * membership slots are full.
+       */
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+ 803e9e0:	e03ffd8d 	sth	zero,-10(fp)
+ 803e9e4:	00001606 	br	803ea40 <ip_setmoptions+0x27c>
+      {
+         if (imo->imo_membership[i]->inm_netp == netp &&
+ 803e9e8:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803e9ec:	e0fffc17 	ldw	r3,-16(fp)
+ 803e9f0:	10800084 	addi	r2,r2,2
+ 803e9f4:	100490ba 	slli	r2,r2,2
+ 803e9f8:	1885883a 	add	r2,r3,r2
+ 803e9fc:	10800017 	ldw	r2,0(r2)
+ 803ea00:	10c00117 	ldw	r3,4(r2)
+ 803ea04:	e0bff817 	ldw	r2,-32(fp)
+ 803ea08:	18800a1e 	bne	r3,r2,803ea34 <ip_setmoptions+0x270>
+             imo->imo_membership[i]->inm_addr
+ 803ea0c:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ea10:	e0fffc17 	ldw	r3,-16(fp)
+ 803ea14:	10800084 	addi	r2,r2,2
+ 803ea18:	100490ba 	slli	r2,r2,2
+ 803ea1c:	1885883a 	add	r2,r3,r2
+ 803ea20:	10800017 	ldw	r2,0(r2)
+ 803ea24:	10c00017 	ldw	r3,0(r2)
+             == mreq->imr_multiaddr)
+ 803ea28:	e0bff917 	ldw	r2,-28(fp)
+ 803ea2c:	10800017 	ldw	r2,0(r2)
+         if (imo->imo_membership[i]->inm_netp == netp &&
+ 803ea30:	18800926 	beq	r3,r2,803ea58 <ip_setmoptions+0x294>
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+ 803ea34:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ea38:	10800044 	addi	r2,r2,1
+ 803ea3c:	e0bffd8d 	sth	r2,-10(fp)
+ 803ea40:	e0bffc17 	ldw	r2,-16(fp)
+ 803ea44:	1080018b 	ldhu	r2,6(r2)
+ 803ea48:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ea4c:	10bfffcc 	andi	r2,r2,65535
+ 803ea50:	18bfe536 	bltu	r3,r2,803e9e8 <ip_setmoptions+0x224>
+ 803ea54:	00000106 	br	803ea5c <ip_setmoptions+0x298>
+         {
+            break;
+ 803ea58:	0001883a 	nop
+         }
+      }
+      if (i < imo->imo_num_memberships) 
+ 803ea5c:	e0bffc17 	ldw	r2,-16(fp)
+ 803ea60:	1080018b 	ldhu	r2,6(r2)
+ 803ea64:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ea68:	10bfffcc 	andi	r2,r2,65535
+ 803ea6c:	1880032e 	bgeu	r3,r2,803ea7c <ip_setmoptions+0x2b8>
+      {
+         error = EADDRINUSE;
+ 803ea70:	00801c04 	movi	r2,112
+ 803ea74:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803ea78:	00009c06 	br	803ecec <ip_setmoptions+0x528>
+      }
+      if (i == IP_MAX_MEMBERSHIPS) 
+ 803ea7c:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ea80:	10800518 	cmpnei	r2,r2,20
+ 803ea84:	1000031e 	bne	r2,zero,803ea94 <ip_setmoptions+0x2d0>
+      {
+         error = ETOOMANYREFS;
+ 803ea88:	00802044 	movi	r2,129
+ 803ea8c:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803ea90:	00009606 	br	803ecec <ip_setmoptions+0x528>
+      /*
+       * Everything looks good; add a new record to the multicast
+       * address list for the given interface.
+       */
+      if ((imo->imo_membership[i] =
+          in_addmulti(&mreq->imr_multiaddr, netp, 4)) == NULL) 
+ 803ea94:	e0bff917 	ldw	r2,-28(fp)
+ 803ea98:	e0fff817 	ldw	r3,-32(fp)
+      if ((imo->imo_membership[i] =
+ 803ea9c:	e43ffd8b 	ldhu	r16,-10(fp)
+          in_addmulti(&mreq->imr_multiaddr, netp, 4)) == NULL) 
+ 803eaa0:	01800104 	movi	r6,4
+ 803eaa4:	180b883a 	mov	r5,r3
+ 803eaa8:	1009883a 	mov	r4,r2
+ 803eaac:	803c2ac0 	call	803c2ac <in_addmulti>
+ 803eab0:	1009883a 	mov	r4,r2
+      if ((imo->imo_membership[i] =
+ 803eab4:	e0fffc17 	ldw	r3,-16(fp)
+ 803eab8:	80800084 	addi	r2,r16,2
+ 803eabc:	100490ba 	slli	r2,r2,2
+ 803eac0:	1885883a 	add	r2,r3,r2
+ 803eac4:	11000015 	stw	r4,0(r2)
+ 803eac8:	e0fffc17 	ldw	r3,-16(fp)
+ 803eacc:	80800084 	addi	r2,r16,2
+ 803ead0:	100490ba 	slli	r2,r2,2
+ 803ead4:	1885883a 	add	r2,r3,r2
+ 803ead8:	10800017 	ldw	r2,0(r2)
+ 803eadc:	1000031e 	bne	r2,zero,803eaec <ip_setmoptions+0x328>
+      {
+         error = ENOBUFS;
+ 803eae0:	00801a44 	movi	r2,105
+ 803eae4:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803eae8:	00008006 	br	803ecec <ip_setmoptions+0x528>
+      }
+      ++imo->imo_num_memberships;
+ 803eaec:	e0bffc17 	ldw	r2,-16(fp)
+ 803eaf0:	1080018b 	ldhu	r2,6(r2)
+ 803eaf4:	10800044 	addi	r2,r2,1
+ 803eaf8:	1007883a 	mov	r3,r2
+ 803eafc:	e0bffc17 	ldw	r2,-16(fp)
+ 803eb00:	10c0018d 	sth	r3,6(r2)
+      break;
+ 803eb04:	00007906 	br	803ecec <ip_setmoptions+0x528>
+   case IP_DROP_MEMBERSHIP:
+      /*
+       * Drop a multicast group membership.
+       * Group must be a valid IP multicast address.
+       */
+      mreq = (struct ip_mreq *)val;
+ 803eb08:	e0bff517 	ldw	r2,-44(fp)
+ 803eb0c:	e0bff915 	stw	r2,-28(fp)
+      if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) 
+ 803eb10:	e0bff917 	ldw	r2,-28(fp)
+ 803eb14:	10800017 	ldw	r2,0(r2)
+ 803eb18:	1006d63a 	srli	r3,r2,24
+ 803eb1c:	e0bff917 	ldw	r2,-28(fp)
+ 803eb20:	10800017 	ldw	r2,0(r2)
+ 803eb24:	1004d23a 	srli	r2,r2,8
+ 803eb28:	10bfc00c 	andi	r2,r2,65280
+ 803eb2c:	1886b03a 	or	r3,r3,r2
+ 803eb30:	e0bff917 	ldw	r2,-28(fp)
+ 803eb34:	10800017 	ldw	r2,0(r2)
+ 803eb38:	1004923a 	slli	r2,r2,8
+ 803eb3c:	10803fec 	andhi	r2,r2,255
+ 803eb40:	1886b03a 	or	r3,r3,r2
+ 803eb44:	e0bff917 	ldw	r2,-28(fp)
+ 803eb48:	10800017 	ldw	r2,0(r2)
+ 803eb4c:	1004963a 	slli	r2,r2,24
+ 803eb50:	1884b03a 	or	r2,r3,r2
+ 803eb54:	10fc002c 	andhi	r3,r2,61440
+ 803eb58:	00b80034 	movhi	r2,57344
+ 803eb5c:	18800326 	beq	r3,r2,803eb6c <ip_setmoptions+0x3a8>
+      {
+         error = EINVAL;
+ 803eb60:	00800584 	movi	r2,22
+ 803eb64:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803eb68:	00006006 	br	803ecec <ip_setmoptions+0x528>
+       * If an interface address was specified, get a pointer
+       * to its ifnet structure. If an interface address was not
+       * specified, get a pointer to the first interface that
+       * supports multicast.
+       */
+      IPADDR_TO_NETP(mreq->imr_interface, &netp);
+ 803eb6c:	e0bff917 	ldw	r2,-28(fp)
+ 803eb70:	10800117 	ldw	r2,4(r2)
+ 803eb74:	e0fff804 	addi	r3,fp,-32
+ 803eb78:	180b883a 	mov	r5,r3
+ 803eb7c:	1009883a 	mov	r4,r2
+ 803eb80:	803e6b00 	call	803e6b0 <IPADDR_TO_NETP>
+      if (netp == NULL) 
+ 803eb84:	e0bff817 	ldw	r2,-32(fp)
+ 803eb88:	1000031e 	bne	r2,zero,803eb98 <ip_setmoptions+0x3d4>
+      {
+         error = EADDRNOTAVAIL;
+ 803eb8c:	00801f44 	movi	r2,125
+ 803eb90:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803eb94:	00005506 	br	803ecec <ip_setmoptions+0x528>
+      }
+
+      /*
+       * Find the membership in the membership array.
+       */
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+ 803eb98:	e03ffd8d 	sth	zero,-10(fp)
+ 803eb9c:	00001806 	br	803ec00 <ip_setmoptions+0x43c>
+      {
+         if ((netp == NULL ||
+ 803eba0:	e0bff817 	ldw	r2,-32(fp)
+ 803eba4:	10000926 	beq	r2,zero,803ebcc <ip_setmoptions+0x408>
+             imo->imo_membership[i]->inm_netp == netp) &&
+ 803eba8:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ebac:	e0fffc17 	ldw	r3,-16(fp)
+ 803ebb0:	10800084 	addi	r2,r2,2
+ 803ebb4:	100490ba 	slli	r2,r2,2
+ 803ebb8:	1885883a 	add	r2,r3,r2
+ 803ebbc:	10800017 	ldw	r2,0(r2)
+ 803ebc0:	10c00117 	ldw	r3,4(r2)
+ 803ebc4:	e0bff817 	ldw	r2,-32(fp)
+         if ((netp == NULL ||
+ 803ebc8:	18800a1e 	bne	r3,r2,803ebf4 <ip_setmoptions+0x430>
+             imo->imo_membership[i]->inm_addr ==
+ 803ebcc:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ebd0:	e0fffc17 	ldw	r3,-16(fp)
+ 803ebd4:	10800084 	addi	r2,r2,2
+ 803ebd8:	100490ba 	slli	r2,r2,2
+ 803ebdc:	1885883a 	add	r2,r3,r2
+ 803ebe0:	10800017 	ldw	r2,0(r2)
+ 803ebe4:	10c00017 	ldw	r3,0(r2)
+             mreq->imr_multiaddr)
+ 803ebe8:	e0bff917 	ldw	r2,-28(fp)
+ 803ebec:	10800017 	ldw	r2,0(r2)
+             imo->imo_membership[i]->inm_netp == netp) &&
+ 803ebf0:	18800926 	beq	r3,r2,803ec18 <ip_setmoptions+0x454>
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+ 803ebf4:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ebf8:	10800044 	addi	r2,r2,1
+ 803ebfc:	e0bffd8d 	sth	r2,-10(fp)
+ 803ec00:	e0bffc17 	ldw	r2,-16(fp)
+ 803ec04:	1080018b 	ldhu	r2,6(r2)
+ 803ec08:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ec0c:	10bfffcc 	andi	r2,r2,65535
+ 803ec10:	18bfe336 	bltu	r3,r2,803eba0 <ip_setmoptions+0x3dc>
+ 803ec14:	00000106 	br	803ec1c <ip_setmoptions+0x458>
+         {
+            break;
+ 803ec18:	0001883a 	nop
+         }
+      }
+      if (i == imo->imo_num_memberships) 
+ 803ec1c:	e0bffc17 	ldw	r2,-16(fp)
+ 803ec20:	1080018b 	ldhu	r2,6(r2)
+ 803ec24:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ec28:	10bfffcc 	andi	r2,r2,65535
+ 803ec2c:	1880031e 	bne	r3,r2,803ec3c <ip_setmoptions+0x478>
+      {
+         error = EADDRNOTAVAIL;
+ 803ec30:	00801f44 	movi	r2,125
+ 803ec34:	e0bffe15 	stw	r2,-8(fp)
+         break;
+ 803ec38:	00002c06 	br	803ecec <ip_setmoptions+0x528>
+      }
+      /*
+       * Give up the multicast address record to which the
+       * membership points.
+       */
+      in_delmulti(imo->imo_membership[i]);
+ 803ec3c:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ec40:	e0fffc17 	ldw	r3,-16(fp)
+ 803ec44:	10800084 	addi	r2,r2,2
+ 803ec48:	100490ba 	slli	r2,r2,2
+ 803ec4c:	1885883a 	add	r2,r3,r2
+ 803ec50:	10800017 	ldw	r2,0(r2)
+ 803ec54:	1009883a 	mov	r4,r2
+ 803ec58:	803c3f80 	call	803c3f8 <in_delmulti>
+      /*
+       * Remove the gap in the membership array.
+       */
+      for (++i; i < imo->imo_num_memberships; ++i)
+ 803ec5c:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ec60:	10800044 	addi	r2,r2,1
+ 803ec64:	e0bffd8d 	sth	r2,-10(fp)
+ 803ec68:	00001006 	br	803ecac <ip_setmoptions+0x4e8>
+         imo->imo_membership[i-1] = imo->imo_membership[i];
+ 803ec6c:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ec70:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803ec74:	10bfffc4 	addi	r2,r2,-1
+ 803ec78:	e13ffc17 	ldw	r4,-16(fp)
+ 803ec7c:	18c00084 	addi	r3,r3,2
+ 803ec80:	180690ba 	slli	r3,r3,2
+ 803ec84:	20c7883a 	add	r3,r4,r3
+ 803ec88:	18c00017 	ldw	r3,0(r3)
+ 803ec8c:	e13ffc17 	ldw	r4,-16(fp)
+ 803ec90:	10800084 	addi	r2,r2,2
+ 803ec94:	100490ba 	slli	r2,r2,2
+ 803ec98:	2085883a 	add	r2,r4,r2
+ 803ec9c:	10c00015 	stw	r3,0(r2)
+      for (++i; i < imo->imo_num_memberships; ++i)
+ 803eca0:	e0bffd8b 	ldhu	r2,-10(fp)
+ 803eca4:	10800044 	addi	r2,r2,1
+ 803eca8:	e0bffd8d 	sth	r2,-10(fp)
+ 803ecac:	e0bffc17 	ldw	r2,-16(fp)
+ 803ecb0:	1080018b 	ldhu	r2,6(r2)
+ 803ecb4:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ecb8:	10bfffcc 	andi	r2,r2,65535
+ 803ecbc:	18bfeb36 	bltu	r3,r2,803ec6c <ip_setmoptions+0x4a8>
+      --imo->imo_num_memberships;
+ 803ecc0:	e0bffc17 	ldw	r2,-16(fp)
+ 803ecc4:	1080018b 	ldhu	r2,6(r2)
+ 803ecc8:	10bfffc4 	addi	r2,r2,-1
+ 803eccc:	1007883a 	mov	r3,r2
+ 803ecd0:	e0bffc17 	ldw	r2,-16(fp)
+ 803ecd4:	10c0018d 	sth	r3,6(r2)
+      break;
+ 803ecd8:	00000406 	br	803ecec <ip_setmoptions+0x528>
+
+      default:
+      error = EOPNOTSUPP;
+ 803ecdc:	008017c4 	movi	r2,95
+ 803ece0:	e0bffe15 	stw	r2,-8(fp)
+      break;
+ 803ece4:	00000106 	br	803ecec <ip_setmoptions+0x528>
+      break;
+ 803ece8:	0001883a 	nop
+   }
+
+      /*
+       * If all options have default values, no need to keep the mbuf.
+       */
+   if (imo->imo_multicast_netp == NULL &&
+ 803ecec:	e0bffc17 	ldw	r2,-16(fp)
+ 803ecf0:	10800017 	ldw	r2,0(r2)
+ 803ecf4:	1000141e 	bne	r2,zero,803ed48 <ip_setmoptions+0x584>
+       imo->imo_multicast_ttl == IP_DEFAULT_MULTICAST_TTL &&
+ 803ecf8:	e0bffc17 	ldw	r2,-16(fp)
+ 803ecfc:	10800103 	ldbu	r2,4(r2)
+   if (imo->imo_multicast_netp == NULL &&
+ 803ed00:	10803fcc 	andi	r2,r2,255
+ 803ed04:	10800058 	cmpnei	r2,r2,1
+ 803ed08:	10000f1e 	bne	r2,zero,803ed48 <ip_setmoptions+0x584>
+       imo->imo_multicast_loop == IP_DEFAULT_MULTICAST_LOOP &&
+ 803ed0c:	e0bffc17 	ldw	r2,-16(fp)
+ 803ed10:	10800143 	ldbu	r2,5(r2)
+       imo->imo_multicast_ttl == IP_DEFAULT_MULTICAST_TTL &&
+ 803ed14:	10803fcc 	andi	r2,r2,255
+ 803ed18:	10800058 	cmpnei	r2,r2,1
+ 803ed1c:	10000a1e 	bne	r2,zero,803ed48 <ip_setmoptions+0x584>
+       imo->imo_num_memberships == 0) 
+ 803ed20:	e0bffc17 	ldw	r2,-16(fp)
+ 803ed24:	1080018b 	ldhu	r2,6(r2)
+       imo->imo_multicast_loop == IP_DEFAULT_MULTICAST_LOOP &&
+ 803ed28:	10bfffcc 	andi	r2,r2,65535
+ 803ed2c:	1000061e 	bne	r2,zero,803ed48 <ip_setmoptions+0x584>
+   {
+      IM_FREE(*imop);
+ 803ed30:	e0bffb17 	ldw	r2,-20(fp)
+ 803ed34:	10800017 	ldw	r2,0(r2)
+ 803ed38:	1009883a 	mov	r4,r2
+ 803ed3c:	80298600 	call	8029860 <npfree>
+      *imop = NULL;
+ 803ed40:	e0bffb17 	ldw	r2,-20(fp)
+ 803ed44:	10000015 	stw	zero,0(r2)
+   }
+   return (error);
+ 803ed48:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 803ed4c:	e6ffff04 	addi	sp,fp,-4
+ 803ed50:	dfc00217 	ldw	ra,8(sp)
+ 803ed54:	df000117 	ldw	fp,4(sp)
+ 803ed58:	dc000017 	ldw	r16,0(sp)
+ 803ed5c:	dec00304 	addi	sp,sp,12
+ 803ed60:	f800283a 	ret
+
+0803ed64 <ip_getmoptions>:
+ * RETURNS: 
+ */
+
+int
+ip_getmoptions(int optname, struct socket * so, void * val)
+{
+ 803ed64:	defff804 	addi	sp,sp,-32
+ 803ed68:	df000715 	stw	fp,28(sp)
+ 803ed6c:	df000704 	addi	fp,sp,28
+ 803ed70:	e13ffb15 	stw	r4,-20(fp)
+ 803ed74:	e17ffa15 	stw	r5,-24(fp)
+ 803ed78:	e1bff915 	stw	r6,-28(fp)
+   u_char * ttl;
+   u_char * loop;
+   ip_addr *addr;
+   struct ip_moptions*  imo   =  so->inp_moptions;
+ 803ed7c:	e0bffa17 	ldw	r2,-24(fp)
+ 803ed80:	10800317 	ldw	r2,12(r2)
+ 803ed84:	e0bfff15 	stw	r2,-4(fp)
+   /* The following code will be commented out for Iniche stack.
+    * Don't allocate a buffer here.
+    *
+    *        *mp = m_get(M_WAIT, MT_SOOPTS);
+    */
+   switch (optname) 
+ 803ed88:	e0bffb17 	ldw	r2,-20(fp)
+ 803ed8c:	108002a0 	cmpeqi	r2,r2,10
+ 803ed90:	1000171e 	bne	r2,zero,803edf0 <ip_getmoptions+0x8c>
+ 803ed94:	e0bffb17 	ldw	r2,-20(fp)
+ 803ed98:	108002e0 	cmpeqi	r2,r2,11
+ 803ed9c:	1000221e 	bne	r2,zero,803ee28 <ip_getmoptions+0xc4>
+ 803eda0:	e0bffb17 	ldw	r2,-20(fp)
+ 803eda4:	10800258 	cmpnei	r2,r2,9
+ 803eda8:	10002d1e 	bne	r2,zero,803ee60 <ip_getmoptions+0xfc>
+   {
+
+   case IP_MULTICAST_IF:
+      addr = (ip_addr *)(val);
+ 803edac:	e0bff917 	ldw	r2,-28(fp)
+ 803edb0:	e0bffe15 	stw	r2,-8(fp)
+      if (imo == NULL || imo->imo_multicast_netp == NULL)
+ 803edb4:	e0bfff17 	ldw	r2,-4(fp)
+ 803edb8:	10000326 	beq	r2,zero,803edc8 <ip_getmoptions+0x64>
+ 803edbc:	e0bfff17 	ldw	r2,-4(fp)
+ 803edc0:	10800017 	ldw	r2,0(r2)
+ 803edc4:	1000031e 	bne	r2,zero,803edd4 <ip_getmoptions+0x70>
+         *addr = AADDR;
+ 803edc8:	e0bffe17 	ldw	r2,-8(fp)
+ 803edcc:	10000015 	stw	zero,0(r2)
+ 803edd0:	00000506 	br	803ede8 <ip_getmoptions+0x84>
+      else
+         *addr = imo->imo_multicast_netp->n_ipaddr;
+ 803edd4:	e0bfff17 	ldw	r2,-4(fp)
+ 803edd8:	10800017 	ldw	r2,0(r2)
+ 803eddc:	10c00a17 	ldw	r3,40(r2)
+ 803ede0:	e0bffe17 	ldw	r2,-8(fp)
+ 803ede4:	10c00015 	stw	r3,0(r2)
+      return (0);
+ 803ede8:	0005883a 	mov	r2,zero
+ 803edec:	00001d06 	br	803ee64 <ip_getmoptions+0x100>
+
+   case IP_MULTICAST_TTL:
+      ttl = (u_char *)val;
+ 803edf0:	e0bff917 	ldw	r2,-28(fp)
+ 803edf4:	e0bffd15 	stw	r2,-12(fp)
+      if (imo == NULL)
+ 803edf8:	e0bfff17 	ldw	r2,-4(fp)
+ 803edfc:	1000041e 	bne	r2,zero,803ee10 <ip_getmoptions+0xac>
+         *ttl = IP_DEFAULT_MULTICAST_TTL;
+ 803ee00:	e0bffd17 	ldw	r2,-12(fp)
+ 803ee04:	00c00044 	movi	r3,1
+ 803ee08:	10c00005 	stb	r3,0(r2)
+ 803ee0c:	00000406 	br	803ee20 <ip_getmoptions+0xbc>
+      else
+         *ttl = imo->imo_multicast_ttl;
+ 803ee10:	e0bfff17 	ldw	r2,-4(fp)
+ 803ee14:	10c00103 	ldbu	r3,4(r2)
+ 803ee18:	e0bffd17 	ldw	r2,-12(fp)
+ 803ee1c:	10c00005 	stb	r3,0(r2)
+      return (0);
+ 803ee20:	0005883a 	mov	r2,zero
+ 803ee24:	00000f06 	br	803ee64 <ip_getmoptions+0x100>
+
+   case IP_MULTICAST_LOOP:
+      loop = (u_char *)val;
+ 803ee28:	e0bff917 	ldw	r2,-28(fp)
+ 803ee2c:	e0bffc15 	stw	r2,-16(fp)
+      if (imo == NULL)
+ 803ee30:	e0bfff17 	ldw	r2,-4(fp)
+ 803ee34:	1000041e 	bne	r2,zero,803ee48 <ip_getmoptions+0xe4>
+         *loop = IP_DEFAULT_MULTICAST_LOOP;
+ 803ee38:	e0bffc17 	ldw	r2,-16(fp)
+ 803ee3c:	00c00044 	movi	r3,1
+ 803ee40:	10c00005 	stb	r3,0(r2)
+ 803ee44:	00000406 	br	803ee58 <ip_getmoptions+0xf4>
+      else
+         *loop = imo->imo_multicast_loop;
+ 803ee48:	e0bfff17 	ldw	r2,-4(fp)
+ 803ee4c:	10c00143 	ldbu	r3,5(r2)
+ 803ee50:	e0bffc17 	ldw	r2,-16(fp)
+ 803ee54:	10c00005 	stb	r3,0(r2)
+      return (0);
+ 803ee58:	0005883a 	mov	r2,zero
+ 803ee5c:	00000106 	br	803ee64 <ip_getmoptions+0x100>
+
+      default:
+      return (EOPNOTSUPP);
+ 803ee60:	008017c4 	movi	r2,95
+   }
+}
+ 803ee64:	e037883a 	mov	sp,fp
+ 803ee68:	df000017 	ldw	fp,0(sp)
+ 803ee6c:	dec00104 	addi	sp,sp,4
+ 803ee70:	f800283a 	ret
+
+0803ee74 <ip_freemoptions>:
+ * RETURNS: 
+ */
+
+void
+ip_freemoptions(struct ip_moptions * imo)
+{
+ 803ee74:	defffc04 	addi	sp,sp,-16
+ 803ee78:	dfc00315 	stw	ra,12(sp)
+ 803ee7c:	df000215 	stw	fp,8(sp)
+ 803ee80:	df000204 	addi	fp,sp,8
+ 803ee84:	e13ffe15 	stw	r4,-8(fp)
+   u_short  i;
+
+   if (imo != NULL) 
+ 803ee88:	e0bffe17 	ldw	r2,-8(fp)
+ 803ee8c:	10001426 	beq	r2,zero,803eee0 <ip_freemoptions+0x6c>
+   {
+      for (i = 0; i < imo->imo_num_memberships; ++i)
+ 803ee90:	e03fff8d 	sth	zero,-2(fp)
+ 803ee94:	00000b06 	br	803eec4 <ip_freemoptions+0x50>
+         in_delmulti(imo->imo_membership[i]);
+ 803ee98:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803ee9c:	e0fffe17 	ldw	r3,-8(fp)
+ 803eea0:	10800084 	addi	r2,r2,2
+ 803eea4:	100490ba 	slli	r2,r2,2
+ 803eea8:	1885883a 	add	r2,r3,r2
+ 803eeac:	10800017 	ldw	r2,0(r2)
+ 803eeb0:	1009883a 	mov	r4,r2
+ 803eeb4:	803c3f80 	call	803c3f8 <in_delmulti>
+      for (i = 0; i < imo->imo_num_memberships; ++i)
+ 803eeb8:	e0bfff8b 	ldhu	r2,-2(fp)
+ 803eebc:	10800044 	addi	r2,r2,1
+ 803eec0:	e0bfff8d 	sth	r2,-2(fp)
+ 803eec4:	e0bffe17 	ldw	r2,-8(fp)
+ 803eec8:	1080018b 	ldhu	r2,6(r2)
+ 803eecc:	e0ffff8b 	ldhu	r3,-2(fp)
+ 803eed0:	10bfffcc 	andi	r2,r2,65535
+ 803eed4:	18bff036 	bltu	r3,r2,803ee98 <ip_freemoptions+0x24>
+      npfree(imo);
+ 803eed8:	e13ffe17 	ldw	r4,-8(fp)
+ 803eedc:	80298600 	call	8029860 <npfree>
+   }
+}
+ 803eee0:	0001883a 	nop
+ 803eee4:	e037883a 	mov	sp,fp
+ 803eee8:	dfc00117 	ldw	ra,4(sp)
+ 803eeec:	df000017 	ldw	fp,0(sp)
+ 803eef0:	dec00204 	addi	sp,sp,8
+ 803eef4:	f800283a 	ret
+
+0803eef8 <u_mctest_init>:
+ *
+ * RETURNS: 
+ */
+
+void u_mctest_init()
+{
+ 803eef8:	defffe04 	addi	sp,sp,-8
+ 803eefc:	dfc00115 	stw	ra,4(sp)
+ 803ef00:	df000015 	stw	fp,0(sp)
+ 803ef04:	d839883a 	mov	fp,sp
+   printf("mctest init called\n");
+ 803ef08:	01020174 	movhi	r4,2053
+ 803ef0c:	212d2e04 	addi	r4,r4,-19272
+ 803ef10:	8002d9c0 	call	8002d9c <puts>
+// altera changes end (cadler@altera.com)
+   install_menu(u_mctest_menu);
+// altera changes begin (cadler@altera.com)
+#endif //IN_MENUS
+// altera changes end (cadler@altera.com)
+}
+ 803ef14:	0001883a 	nop
+ 803ef18:	e037883a 	mov	sp,fp
+ 803ef1c:	dfc00117 	ldw	ra,4(sp)
+ 803ef20:	df000017 	ldw	fp,0(sp)
+ 803ef24:	dec00204 	addi	sp,sp,8
+ 803ef28:	f800283a 	ret
+
+0803ef2c <u_mctest_run>:
+ *
+ * RETURNS: 
+ */
+
+int u_mctest_run(void * pio)
+{
+ 803ef2c:	defede04 	addi	sp,sp,-1160
+ 803ef30:	dfc12115 	stw	ra,1156(sp)
+ 803ef34:	df012015 	stw	fp,1152(sp)
+ 803ef38:	df012004 	addi	fp,sp,1152
+ 803ef3c:	e13ee215 	stw	r4,-1144(fp)
+    struct sockaddr_in   stLocal, stTo, stFrom;
+    char  achIn[BUFSIZE];
+    char  achOut[] = "Message number:              ";
+ 803ef40:	e0fee884 	addi	r3,fp,-1118
+ 803ef44:	00820174 	movhi	r2,2053
+ 803ef48:	10adda04 	addi	r2,r2,-18584
+ 803ef4c:	01000784 	movi	r4,30
+ 803ef50:	200d883a 	mov	r6,r4
+ 803ef54:	100b883a 	mov	r5,r2
+ 803ef58:	1809883a 	mov	r4,r3
+ 803ef5c:	80086b80 	call	80086b8 <memcpy>
+    struct ip_mreq stMreq;
+    u_char cTmp;
+    unsigned long endtime;
+
+   /* get a datagram socket */
+   s = t_socket(AF_INET,SOCK_DGRAM, 0);
+ 803ef60:	000d883a 	mov	r6,zero
+ 803ef64:	01400084 	movi	r5,2
+ 803ef68:	01000084 	movi	r4,2
+ 803ef6c:	802ba700 	call	802ba70 <t_socket>
+ 803ef70:	e0bffe15 	stw	r2,-8(fp)
+
+   if (s == INVALID_SOCKET) 
+ 803ef74:	e0bffe17 	ldw	r2,-8(fp)
+ 803ef78:	10bfffd8 	cmpnei	r2,r2,-1
+ 803ef7c:	1000091e 	bne	r2,zero,803efa4 <u_mctest_run+0x78>
+   {
+      ns_printf (pio,"t_socket() failed, Err: %d\n", t_errno(s));
+ 803ef80:	e13ffe17 	ldw	r4,-8(fp)
+ 803ef84:	802cfbc0 	call	802cfbc <t_errno>
+ 803ef88:	100d883a 	mov	r6,r2
+ 803ef8c:	01420174 	movhi	r5,2053
+ 803ef90:	296d3304 	addi	r5,r5,-19252
+ 803ef94:	e13ee217 	ldw	r4,-1144(fp)
+ 803ef98:	80273900 	call	8027390 <ns_printf>
+      exit(1);
+ 803ef9c:	01000044 	movi	r4,1
+ 803efa0:	8042abc0 	call	8042abc <exit>
+   }
+
+   /* avoid EADDRINUSE error on bind() */ 
+   iTmp = 1;
+ 803efa4:	00800044 	movi	r2,1
+ 803efa8:	e0bee715 	stw	r2,-1124(fp)
+   iRet = t_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (char *)&iTmp, sizeof(iTmp));
+ 803efac:	e0fee704 	addi	r3,fp,-1124
+ 803efb0:	00800104 	movi	r2,4
+ 803efb4:	d8800015 	stw	r2,0(sp)
+ 803efb8:	180f883a 	mov	r7,r3
+ 803efbc:	01800104 	movi	r6,4
+ 803efc0:	017fffc4 	movi	r5,-1
+ 803efc4:	e13ffe17 	ldw	r4,-8(fp)
+ 803efc8:	802c44c0 	call	802c44c <t_setsockopt>
+ 803efcc:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803efd0:	e0bffd17 	ldw	r2,-12(fp)
+ 803efd4:	10bfffd8 	cmpnei	r2,r2,-1
+ 803efd8:	1000071e 	bne	r2,zero,803eff8 <u_mctest_run+0xcc>
+   {
+      ns_printf (pio,"t_setsockopt() SO_REUSEADDR failed, Err: %d\n",
+ 803efdc:	e13ffe17 	ldw	r4,-8(fp)
+ 803efe0:	802cfbc0 	call	802cfbc <t_errno>
+ 803efe4:	100d883a 	mov	r6,r2
+ 803efe8:	01420174 	movhi	r5,2053
+ 803efec:	296d3a04 	addi	r5,r5,-19224
+ 803eff0:	e13ee217 	ldw	r4,-1144(fp)
+ 803eff4:	80273900 	call	8027390 <ns_printf>
+       t_errno(s));
+   }
+
+   /* name the socket */
+   stLocal.sin_family =   AF_INET;
+ 803eff8:	00800084 	movi	r2,2
+ 803effc:	e0bff80d 	sth	r2,-32(fp)
+   stLocal.sin_addr.s_addr = htonl(INADDR_ANY);
+ 803f000:	e03ff915 	stw	zero,-28(fp)
+   stLocal.sin_port =   htons(TEST_PORT);
+ 803f004:	00a00344 	movi	r2,-32755
+ 803f008:	e0bff88d 	sth	r2,-30(fp)
+   iRet = t_bind(s, (struct sockaddr*) &stLocal, sizeof(struct sockaddr_in));
+ 803f00c:	e0bff804 	addi	r2,fp,-32
+ 803f010:	01800404 	movi	r6,16
+ 803f014:	100b883a 	mov	r5,r2
+ 803f018:	e13ffe17 	ldw	r4,-8(fp)
+ 803f01c:	802baf00 	call	802baf0 <t_bind>
+ 803f020:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803f024:	e0bffd17 	ldw	r2,-12(fp)
+ 803f028:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f02c:	1000061e 	bne	r2,zero,803f048 <u_mctest_run+0x11c>
+   {
+      printf ("t_bind() failed, Err: %d\n",
+ 803f030:	e13ffe17 	ldw	r4,-8(fp)
+ 803f034:	802cfbc0 	call	802cfbc <t_errno>
+ 803f038:	100b883a 	mov	r5,r2
+ 803f03c:	01020174 	movhi	r4,2053
+ 803f040:	212d4604 	addi	r4,r4,-19176
+ 803f044:	8002c780 	call	8002c78 <printf>
+       t_errno(s));
+   }
+
+   /* join the multicast group. TEST_ADDR */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR);
+ 803f048:	01820174 	movhi	r6,2053
+ 803f04c:	31ad4d04 	addi	r6,r6,-19148
+ 803f050:	01420174 	movhi	r5,2053
+ 803f054:	296d5004 	addi	r5,r5,-19136
+ 803f058:	e13ee217 	ldw	r4,-1144(fp)
+ 803f05c:	80273900 	call	8027390 <ns_printf>
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR);
+ 803f060:	01020174 	movhi	r4,2053
+ 803f064:	212d4d04 	addi	r4,r4,-19148
+ 803f068:	803fc380 	call	803fc38 <inet_addr>
+ 803f06c:	e0bee515 	stw	r2,-1132(fp)
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+ 803f070:	008201b4 	movhi	r2,2054
+ 803f074:	10b6ba17 	ldw	r2,-9496(r2)
+ 803f078:	e0bee615 	stw	r2,-1128(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP,
+ 803f07c:	e0fee504 	addi	r3,fp,-1132
+ 803f080:	00800204 	movi	r2,8
+ 803f084:	d8800015 	stw	r2,0(sp)
+ 803f088:	180f883a 	mov	r7,r3
+ 803f08c:	01800304 	movi	r6,12
+ 803f090:	000b883a 	mov	r5,zero
+ 803f094:	e13ffe17 	ldw	r4,-8(fp)
+ 803f098:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f09c:	e0bffd15 	stw	r2,-12(fp)
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+ 803f0a0:	e0bffd17 	ldw	r2,-12(fp)
+ 803f0a4:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f0a8:	1000071e 	bne	r2,zero,803f0c8 <u_mctest_run+0x19c>
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+ 803f0ac:	e13ffe17 	ldw	r4,-8(fp)
+ 803f0b0:	802cfbc0 	call	802cfbc <t_errno>
+ 803f0b4:	100d883a 	mov	r6,r2
+ 803f0b8:	01420174 	movhi	r5,2053
+ 803f0bc:	296d5804 	addi	r5,r5,-19104
+ 803f0c0:	e13ee217 	ldw	r4,-1144(fp)
+ 803f0c4:	80273900 	call	8027390 <ns_printf>
+                     t_errno(s));
+   } 
+   tk_yield();
+ 803f0c8:	8027ce40 	call	8027ce4 <tk_yield>
+
+   /* join the multicast group. TEST_ADDR1 */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR1);
+ 803f0cc:	01820174 	movhi	r6,2053
+ 803f0d0:	31ad6504 	addi	r6,r6,-19052
+ 803f0d4:	01420174 	movhi	r5,2053
+ 803f0d8:	296d5004 	addi	r5,r5,-19136
+ 803f0dc:	e13ee217 	ldw	r4,-1144(fp)
+ 803f0e0:	80273900 	call	8027390 <ns_printf>
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR1);
+ 803f0e4:	01020174 	movhi	r4,2053
+ 803f0e8:	212d6504 	addi	r4,r4,-19052
+ 803f0ec:	803fc380 	call	803fc38 <inet_addr>
+ 803f0f0:	e0bee515 	stw	r2,-1132(fp)
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+ 803f0f4:	008201b4 	movhi	r2,2054
+ 803f0f8:	10b6ba17 	ldw	r2,-9496(r2)
+ 803f0fc:	e0bee615 	stw	r2,-1128(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, 
+ 803f100:	e0fee504 	addi	r3,fp,-1132
+ 803f104:	00800204 	movi	r2,8
+ 803f108:	d8800015 	stw	r2,0(sp)
+ 803f10c:	180f883a 	mov	r7,r3
+ 803f110:	01800304 	movi	r6,12
+ 803f114:	000b883a 	mov	r5,zero
+ 803f118:	e13ffe17 	ldw	r4,-8(fp)
+ 803f11c:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f120:	e0bffd15 	stw	r2,-12(fp)
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+ 803f124:	e0bffd17 	ldw	r2,-12(fp)
+ 803f128:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f12c:	1000071e 	bne	r2,zero,803f14c <u_mctest_run+0x220>
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+ 803f130:	e13ffe17 	ldw	r4,-8(fp)
+ 803f134:	802cfbc0 	call	802cfbc <t_errno>
+ 803f138:	100d883a 	mov	r6,r2
+ 803f13c:	01420174 	movhi	r5,2053
+ 803f140:	296d5804 	addi	r5,r5,-19104
+ 803f144:	e13ee217 	ldw	r4,-1144(fp)
+ 803f148:	80273900 	call	8027390 <ns_printf>
+                     t_errno(s));
+   }
+   tk_yield();
+ 803f14c:	8027ce40 	call	8027ce4 <tk_yield>
+
+   /* join the multicast group. TEST_ADDR2 */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR2);
+ 803f150:	01820174 	movhi	r6,2053
+ 803f154:	31ad6804 	addi	r6,r6,-19040
+ 803f158:	01420174 	movhi	r5,2053
+ 803f15c:	296d5004 	addi	r5,r5,-19136
+ 803f160:	e13ee217 	ldw	r4,-1144(fp)
+ 803f164:	80273900 	call	8027390 <ns_printf>
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR2);
+ 803f168:	01020174 	movhi	r4,2053
+ 803f16c:	212d6804 	addi	r4,r4,-19040
+ 803f170:	803fc380 	call	803fc38 <inet_addr>
+ 803f174:	e0bee515 	stw	r2,-1132(fp)
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+ 803f178:	008201b4 	movhi	r2,2054
+ 803f17c:	10b6ba17 	ldw	r2,-9496(r2)
+ 803f180:	e0bee615 	stw	r2,-1128(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, 
+ 803f184:	e0fee504 	addi	r3,fp,-1132
+ 803f188:	00800204 	movi	r2,8
+ 803f18c:	d8800015 	stw	r2,0(sp)
+ 803f190:	180f883a 	mov	r7,r3
+ 803f194:	01800304 	movi	r6,12
+ 803f198:	000b883a 	mov	r5,zero
+ 803f19c:	e13ffe17 	ldw	r4,-8(fp)
+ 803f1a0:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f1a4:	e0bffd15 	stw	r2,-12(fp)
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+ 803f1a8:	e0bffd17 	ldw	r2,-12(fp)
+ 803f1ac:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f1b0:	1000071e 	bne	r2,zero,803f1d0 <u_mctest_run+0x2a4>
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+ 803f1b4:	e13ffe17 	ldw	r4,-8(fp)
+ 803f1b8:	802cfbc0 	call	802cfbc <t_errno>
+ 803f1bc:	100d883a 	mov	r6,r2
+ 803f1c0:	01420174 	movhi	r5,2053
+ 803f1c4:	296d5804 	addi	r5,r5,-19104
+ 803f1c8:	e13ee217 	ldw	r4,-1144(fp)
+ 803f1cc:	80273900 	call	8027390 <ns_printf>
+                     t_errno(s));
+   }
+   tk_yield();
+ 803f1d0:	8027ce40 	call	8027ce4 <tk_yield>
+
+   /* set TTL to traverse up to multiple routers */
+   cTmp = TTL_VALUE;
+ 803f1d4:	00800084 	movi	r2,2
+ 803f1d8:	e0bee4c5 	stb	r2,-1133(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_TTL, (char *)&cTmp, sizeof(cTmp));
+ 803f1dc:	e0fee4c4 	addi	r3,fp,-1133
+ 803f1e0:	00800044 	movi	r2,1
+ 803f1e4:	d8800015 	stw	r2,0(sp)
+ 803f1e8:	180f883a 	mov	r7,r3
+ 803f1ec:	01800284 	movi	r6,10
+ 803f1f0:	000b883a 	mov	r5,zero
+ 803f1f4:	e13ffe17 	ldw	r4,-8(fp)
+ 803f1f8:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f1fc:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803f200:	e0bffd17 	ldw	r2,-12(fp)
+ 803f204:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f208:	1000071e 	bne	r2,zero,803f228 <u_mctest_run+0x2fc>
+   {
+      ns_printf (pio,"t_setsockopt() IP_MULTICAST_TTL failed, Err: %d\n",
+ 803f20c:	e13ffe17 	ldw	r4,-8(fp)
+ 803f210:	802cfbc0 	call	802cfbc <t_errno>
+ 803f214:	100d883a 	mov	r6,r2
+ 803f218:	01420174 	movhi	r5,2053
+ 803f21c:	296d6b04 	addi	r5,r5,-19028
+ 803f220:	e13ee217 	ldw	r4,-1144(fp)
+ 803f224:	80273900 	call	8027390 <ns_printf>
+                     t_errno(s));
+   }
+
+   /* enable loopback */
+   cTmp = 1;
+ 803f228:	00800044 	movi	r2,1
+ 803f22c:	e0bee4c5 	stb	r2,-1133(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_LOOP, (char *)&cTmp, sizeof(cTmp));
+ 803f230:	e0fee4c4 	addi	r3,fp,-1133
+ 803f234:	00800044 	movi	r2,1
+ 803f238:	d8800015 	stw	r2,0(sp)
+ 803f23c:	180f883a 	mov	r7,r3
+ 803f240:	018002c4 	movi	r6,11
+ 803f244:	000b883a 	mov	r5,zero
+ 803f248:	e13ffe17 	ldw	r4,-8(fp)
+ 803f24c:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f250:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803f254:	e0bffd17 	ldw	r2,-12(fp)
+ 803f258:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f25c:	1000071e 	bne	r2,zero,803f27c <u_mctest_run+0x350>
+   {
+      ns_printf (pio,"t_setsockopt() IP_MULTICAST_LOOP failed, Err: %d\n",
+ 803f260:	e13ffe17 	ldw	r4,-8(fp)
+ 803f264:	802cfbc0 	call	802cfbc <t_errno>
+ 803f268:	100d883a 	mov	r6,r2
+ 803f26c:	01420174 	movhi	r5,2053
+ 803f270:	296d7804 	addi	r5,r5,-18976
+ 803f274:	e13ee217 	ldw	r4,-1144(fp)
+ 803f278:	80273900 	call	8027390 <ns_printf>
+                     t_errno(s));
+   }
+
+   /* assign our destination address */
+   stTo.sin_family =      AF_INET;
+ 803f27c:	00800084 	movi	r2,2
+ 803f280:	e0bff40d 	sth	r2,-48(fp)
+   stTo.sin_addr.s_addr = inet_addr(TEST_ADDR1);
+ 803f284:	01020174 	movhi	r4,2053
+ 803f288:	212d6504 	addi	r4,r4,-19052
+ 803f28c:	803fc380 	call	803fc38 <inet_addr>
+ 803f290:	e0bff515 	stw	r2,-44(fp)
+   stTo.sin_port =        htons(TEST_PORT);
+ 803f294:	00a00344 	movi	r2,-32755
+ 803f298:	e0bff48d 	sth	r2,-46(fp)
+   ns_printf (pio,"Now sending to (and receiving from) multicast group: %s\n",
+ 803f29c:	01820174 	movhi	r6,2053
+ 803f2a0:	31ad6504 	addi	r6,r6,-19052
+ 803f2a4:	01420174 	movhi	r5,2053
+ 803f2a8:	296d8504 	addi	r5,r5,-18924
+ 803f2ac:	e13ee217 	ldw	r4,-1144(fp)
+ 803f2b0:	80273900 	call	8027390 <ns_printf>
+                  TEST_ADDR1);
+
+   for (i = 0; i < LOOPMAX; i++)
+ 803f2b4:	e03fff15 	stw	zero,-4(fp)
+ 803f2b8:	00008606 	br	803f4d4 <u_mctest_run+0x5a8>
+   {
+      static int iCounter = 1;
+
+      /* send to the multicast address */
+      sprintf(&achOut[16], "%d", iCounter++);
+ 803f2bc:	d0a03117 	ldw	r2,-32572(gp)
+ 803f2c0:	10c00044 	addi	r3,r2,1
+ 803f2c4:	d0e03115 	stw	r3,-32572(gp)
+ 803f2c8:	e0fee884 	addi	r3,fp,-1118
+ 803f2cc:	18c00404 	addi	r3,r3,16
+ 803f2d0:	100d883a 	mov	r6,r2
+ 803f2d4:	01420174 	movhi	r5,2053
+ 803f2d8:	296d9404 	addi	r5,r5,-18864
+ 803f2dc:	1809883a 	mov	r4,r3
+ 803f2e0:	8042d980 	call	8042d98 <sprintf>
+      iRet = t_sendto(s, achOut, sizeof(achOut), 0, (struct sockaddr*)&stTo,
+ 803f2e4:	e0fee884 	addi	r3,fp,-1118
+ 803f2e8:	00800404 	movi	r2,16
+ 803f2ec:	d8800115 	stw	r2,4(sp)
+ 803f2f0:	e0bff404 	addi	r2,fp,-48
+ 803f2f4:	d8800015 	stw	r2,0(sp)
+ 803f2f8:	000f883a 	mov	r7,zero
+ 803f2fc:	01800784 	movi	r6,30
+ 803f300:	180b883a 	mov	r5,r3
+ 803f304:	e13ffe17 	ldw	r4,-8(fp)
+ 803f308:	802c9ac0 	call	802c9ac <t_sendto>
+ 803f30c:	e0bffd15 	stw	r2,-12(fp)
+                      sizeof(struct sockaddr_in));
+      if (iRet < 0) 
+ 803f310:	e0bffd17 	ldw	r2,-12(fp)
+ 803f314:	1000080e 	bge	r2,zero,803f338 <u_mctest_run+0x40c>
+      {
+         /*      perror("sendto() failed\n"); */
+         ns_printf (pio,"t_sendto() failed, Error: %d\n", t_errno(s));
+ 803f318:	e13ffe17 	ldw	r4,-8(fp)
+ 803f31c:	802cfbc0 	call	802cfbc <t_errno>
+ 803f320:	100d883a 	mov	r6,r2
+ 803f324:	01420174 	movhi	r5,2053
+ 803f328:	296d9504 	addi	r5,r5,-18860
+ 803f32c:	e13ee217 	ldw	r4,-1144(fp)
+ 803f330:	80273900 	call	8027390 <ns_printf>
+         /*     exit(1); */
+         goto exitloop;
+ 803f334:	00006b06 	br	803f4e4 <u_mctest_run+0x5b8>
+      }
+
+      /* make the socket non-blocking */
+      iTmp = 1;
+ 803f338:	00800044 	movi	r2,1
+ 803f33c:	e0bee715 	stw	r2,-1124(fp)
+      iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&iTmp, sizeof(iTmp));
+ 803f340:	e0fee704 	addi	r3,fp,-1124
+ 803f344:	00800104 	movi	r2,4
+ 803f348:	d8800015 	stw	r2,0(sp)
+ 803f34c:	180f883a 	mov	r7,r3
+ 803f350:	01840584 	movi	r6,4118
+ 803f354:	017fffc4 	movi	r5,-1
+ 803f358:	e13ffe17 	ldw	r4,-8(fp)
+ 803f35c:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f360:	e0bffd15 	stw	r2,-12(fp)
+      if (iRet == SOCKET_ERROR) 
+ 803f364:	e0bffd17 	ldw	r2,-12(fp)
+ 803f368:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f36c:	1000071e 	bne	r2,zero,803f38c <u_mctest_run+0x460>
+      {
+         ns_printf (pio,"t_setsockopt() SO_NONBLOCK (1) failed, Err: %d\n",
+ 803f370:	e13ffe17 	ldw	r4,-8(fp)
+ 803f374:	802cfbc0 	call	802cfbc <t_errno>
+ 803f378:	100d883a 	mov	r6,r2
+ 803f37c:	01420174 	movhi	r5,2053
+ 803f380:	296d9d04 	addi	r5,r5,-18828
+ 803f384:	e13ee217 	ldw	r4,-1144(fp)
+ 803f388:	80273900 	call	8027390 <ns_printf>
+                        t_errno(s));
+      }
+
+      /* loop around for 5 seconds waiting to receive datagrams */
+      endtime = cticks + (TPS * 5);
+ 803f38c:	d0a07d17 	ldw	r2,-32268(gp)
+ 803f390:	10807d04 	addi	r2,r2,500
+ 803f394:	e0bffc15 	stw	r2,-16(fp)
+
+      while (cticks < endtime)
+ 803f398:	00003406 	br	803f46c <u_mctest_run+0x540>
+      {
+         int sa_size = sizeof(struct sockaddr_in);
+ 803f39c:	00800404 	movi	r2,16
+ 803f3a0:	e0bee315 	stw	r2,-1140(fp)
+         tk_yield();
+ 803f3a4:	8027ce40 	call	8027ce4 <tk_yield>
+
+         iRet = t_recvfrom(s, achIn, BUFSIZE, 0, (struct sockaddr*)&stFrom, &sa_size);
+ 803f3a8:	e0fef004 	addi	r3,fp,-1088
+ 803f3ac:	e0bee304 	addi	r2,fp,-1140
+ 803f3b0:	d8800115 	stw	r2,4(sp)
+ 803f3b4:	e0bff004 	addi	r2,fp,-64
+ 803f3b8:	d8800015 	stw	r2,0(sp)
+ 803f3bc:	000f883a 	mov	r7,zero
+ 803f3c0:	01810004 	movi	r6,1024
+ 803f3c4:	180b883a 	mov	r5,r3
+ 803f3c8:	e13ffe17 	ldw	r4,-8(fp)
+ 803f3cc:	802c8700 	call	802c870 <t_recvfrom>
+ 803f3d0:	e0bffd15 	stw	r2,-12(fp)
+         if (iRet < 0) 
+ 803f3d4:	e0bffd17 	ldw	r2,-12(fp)
+ 803f3d8:	10000c0e 	bge	r2,zero,803f40c <u_mctest_run+0x4e0>
+         {
+            if (t_errno(s) != EWOULDBLOCK)
+ 803f3dc:	e13ffe17 	ldw	r4,-8(fp)
+ 803f3e0:	802cfbc0 	call	802cfbc <t_errno>
+ 803f3e4:	108002e0 	cmpeqi	r2,r2,11
+ 803f3e8:	1000081e 	bne	r2,zero,803f40c <u_mctest_run+0x4e0>
+            {
+               /*      perror("recvfrom() failed\n"); */
+               ns_printf (pio,"t_recvfrom() failed, Error: %d\n", t_errno(s));
+ 803f3ec:	e13ffe17 	ldw	r4,-8(fp)
+ 803f3f0:	802cfbc0 	call	802cfbc <t_errno>
+ 803f3f4:	100d883a 	mov	r6,r2
+ 803f3f8:	01420174 	movhi	r5,2053
+ 803f3fc:	296da904 	addi	r5,r5,-18780
+ 803f400:	e13ee217 	ldw	r4,-1144(fp)
+ 803f404:	80273900 	call	8027390 <ns_printf>
+ 803f408:	00003606 	br	803f4e4 <u_mctest_run+0x5b8>
+               /*     exit(1); */
+               goto exitloop;
+            }
+         }
+         if (iRet > 0)
+ 803f40c:	e0bffd17 	ldw	r2,-12(fp)
+ 803f410:	0080160e 	bge	zero,r2,803f46c <u_mctest_run+0x540>
+         {
+            ns_printf(pio,"From host:%s port:%d, %s\n",
+ 803f414:	e0bff117 	ldw	r2,-60(fp)
+ 803f418:	1009883a 	mov	r4,r2
+ 803f41c:	8026fbc0 	call	8026fbc <print_ipad>
+ 803f420:	1009883a 	mov	r4,r2
+             print_ipad(stFrom.sin_addr.s_addr),
+             ntohs(stFrom.sin_port), achIn);
+ 803f424:	e0bff08b 	ldhu	r2,-62(fp)
+ 803f428:	10bfffcc 	andi	r2,r2,65535
+ 803f42c:	1004d23a 	srli	r2,r2,8
+ 803f430:	10bfffcc 	andi	r2,r2,65535
+ 803f434:	10c03fcc 	andi	r3,r2,255
+ 803f438:	e0bff08b 	ldhu	r2,-62(fp)
+ 803f43c:	10bfffcc 	andi	r2,r2,65535
+ 803f440:	1004923a 	slli	r2,r2,8
+ 803f444:	10bfffcc 	andi	r2,r2,65535
+            ns_printf(pio,"From host:%s port:%d, %s\n",
+ 803f448:	1886b03a 	or	r3,r3,r2
+ 803f44c:	e0bef004 	addi	r2,fp,-1088
+ 803f450:	d8800015 	stw	r2,0(sp)
+ 803f454:	180f883a 	mov	r7,r3
+ 803f458:	200d883a 	mov	r6,r4
+ 803f45c:	01420174 	movhi	r5,2053
+ 803f460:	296db104 	addi	r5,r5,-18748
+ 803f464:	e13ee217 	ldw	r4,-1144(fp)
+ 803f468:	80273900 	call	8027390 <ns_printf>
+      while (cticks < endtime)
+ 803f46c:	d0e07d17 	ldw	r3,-32268(gp)
+ 803f470:	e0bffc17 	ldw	r2,-16(fp)
+ 803f474:	18bfc936 	bltu	r3,r2,803f39c <u_mctest_run+0x470>
+         }
+      }   /* end while (cticks...) */
+
+      /* make the socket blocking */
+      cTmp = 0;
+ 803f478:	e03ee4c5 	stb	zero,-1133(fp)
+      iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&cTmp, sizeof(cTmp));
+ 803f47c:	e0fee4c4 	addi	r3,fp,-1133
+ 803f480:	00800044 	movi	r2,1
+ 803f484:	d8800015 	stw	r2,0(sp)
+ 803f488:	180f883a 	mov	r7,r3
+ 803f48c:	01840584 	movi	r6,4118
+ 803f490:	017fffc4 	movi	r5,-1
+ 803f494:	e13ffe17 	ldw	r4,-8(fp)
+ 803f498:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f49c:	e0bffd15 	stw	r2,-12(fp)
+      if (iRet == SOCKET_ERROR) 
+ 803f4a0:	e0bffd17 	ldw	r2,-12(fp)
+ 803f4a4:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f4a8:	1000071e 	bne	r2,zero,803f4c8 <u_mctest_run+0x59c>
+      {
+         ns_printf (pio,"t_setsockopt() SO_NONBLOCK (0) failed, Err: %d\n",
+ 803f4ac:	e13ffe17 	ldw	r4,-8(fp)
+ 803f4b0:	802cfbc0 	call	802cfbc <t_errno>
+ 803f4b4:	100d883a 	mov	r6,r2
+ 803f4b8:	01420174 	movhi	r5,2053
+ 803f4bc:	296db804 	addi	r5,r5,-18720
+ 803f4c0:	e13ee217 	ldw	r4,-1144(fp)
+ 803f4c4:	80273900 	call	8027390 <ns_printf>
+   for (i = 0; i < LOOPMAX; i++)
+ 803f4c8:	e0bfff17 	ldw	r2,-4(fp)
+ 803f4cc:	10800044 	addi	r2,r2,1
+ 803f4d0:	e0bfff15 	stw	r2,-4(fp)
+ 803f4d4:	e0bfff17 	ldw	r2,-4(fp)
+ 803f4d8:	108000d0 	cmplti	r2,r2,3
+ 803f4dc:	103f771e 	bne	r2,zero,803f2bc <u_mctest_run+0x390>
+                        t_errno(s));
+      }
+   }   /* end for(;;) */
+
+exitloop:
+ 803f4e0:	0001883a 	nop
+   /* delete the multicast group. */
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR);
+ 803f4e4:	01020174 	movhi	r4,2053
+ 803f4e8:	212d4d04 	addi	r4,r4,-19148
+ 803f4ec:	803fc380 	call	803fc38 <inet_addr>
+ 803f4f0:	e0bee515 	stw	r2,-1132(fp)
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+ 803f4f4:	008201b4 	movhi	r2,2054
+ 803f4f8:	10b6ba17 	ldw	r2,-9496(r2)
+ 803f4fc:	e0bee615 	stw	r2,-1128(fp)
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_DROP_MEMBERSHIP, (char *)&stMreq, sizeof(stMreq));
+ 803f500:	e0fee504 	addi	r3,fp,-1132
+ 803f504:	00800204 	movi	r2,8
+ 803f508:	d8800015 	stw	r2,0(sp)
+ 803f50c:	180f883a 	mov	r7,r3
+ 803f510:	01800344 	movi	r6,13
+ 803f514:	000b883a 	mov	r5,zero
+ 803f518:	e13ffe17 	ldw	r4,-8(fp)
+ 803f51c:	802c44c0 	call	802c44c <t_setsockopt>
+ 803f520:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803f524:	e0bffd17 	ldw	r2,-12(fp)
+ 803f528:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f52c:	1000071e 	bne	r2,zero,803f54c <u_mctest_run+0x620>
+   {
+      ns_printf (pio,"t_setsockopt() IP_DROP_MEMBERSHIP failed, Err: %d\n",
+ 803f530:	e13ffe17 	ldw	r4,-8(fp)
+ 803f534:	802cfbc0 	call	802cfbc <t_errno>
+ 803f538:	100d883a 	mov	r6,r2
+ 803f53c:	01420174 	movhi	r5,2053
+ 803f540:	296dc404 	addi	r5,r5,-18672
+ 803f544:	e13ee217 	ldw	r4,-1144(fp)
+ 803f548:	80273900 	call	8027390 <ns_printf>
+   {
+      ns_printf (pio,"t_shutdown failed.  Err: %d\n", t_errno(s));
+   }
+#endif
+
+   iRet = t_socketclose(s);
+ 803f54c:	e13ffe17 	ldw	r4,-8(fp)
+ 803f550:	802ce700 	call	802ce70 <t_socketclose>
+ 803f554:	e0bffd15 	stw	r2,-12(fp)
+   if (iRet == SOCKET_ERROR) 
+ 803f558:	e0bffd17 	ldw	r2,-12(fp)
+ 803f55c:	10bfffd8 	cmpnei	r2,r2,-1
+ 803f560:	1000071e 	bne	r2,zero,803f580 <u_mctest_run+0x654>
+   {
+      ns_printf (pio,"t_socketclose() failed.  Err: %d\n", t_errno(s));
+ 803f564:	e13ffe17 	ldw	r4,-8(fp)
+ 803f568:	802cfbc0 	call	802cfbc <t_errno>
+ 803f56c:	100d883a 	mov	r6,r2
+ 803f570:	01420174 	movhi	r5,2053
+ 803f574:	296dd104 	addi	r5,r5,-18620
+ 803f578:	e13ee217 	ldw	r4,-1144(fp)
+ 803f57c:	80273900 	call	8027390 <ns_printf>
+   }
+
+   return(0);
+ 803f580:	0005883a 	mov	r2,zero
+}  /* end main() */  
+ 803f584:	e037883a 	mov	sp,fp
+ 803f588:	dfc00117 	ldw	ra,4(sp)
+ 803f58c:	df000017 	ldw	fp,0(sp)
+ 803f590:	dec00204 	addi	sp,sp,8
+ 803f594:	f800283a 	ret
+
+0803f598 <init_memdev>:
+ * RETURNS: 
+ */
+
+int
+init_memdev(void)
+{
+ 803f598:	deffff04 	addi	sp,sp,-4
+ 803f59c:	df000015 	stw	fp,0(sp)
+ 803f5a0:	d839883a 	mov	fp,sp
+   /* add our IO pointer to master list */
+   mdio.next = vfsystems;
+ 803f5a4:	d0e0a117 	ldw	r3,-32124(gp)
+ 803f5a8:	00820174 	movhi	r2,2053
+ 803f5ac:	10f25915 	stw	r3,-13980(r2)
+   vfsystems = &mdio;
+ 803f5b0:	00820174 	movhi	r2,2053
+ 803f5b4:	10b25904 	addi	r2,r2,-13980
+ 803f5b8:	d0a0a115 	stw	r2,-32124(gp)
+
+   /* add the memory device files to vfs list */
+   mdlist[0].next = vfsfiles;
+ 803f5bc:	d0e0a317 	ldw	r3,-32116(gp)
+ 803f5c0:	00820174 	movhi	r2,2053
+ 803f5c4:	10f26215 	stw	r3,-13944(r2)
+   vfsfiles = &mdlist[3];
+ 803f5c8:	00820174 	movhi	r2,2053
+ 803f5cc:	10b28304 	addi	r2,r2,-13812
+ 803f5d0:	d0a0a315 	stw	r2,-32116(gp)
+
+   return 0;
+ 803f5d4:	0005883a 	mov	r2,zero
+}
+ 803f5d8:	e037883a 	mov	sp,fp
+ 803f5dc:	df000017 	ldw	fp,0(sp)
+ 803f5e0:	dec00104 	addi	sp,sp,4
+ 803f5e4:	f800283a 	ret
+
+0803f5e8 <md_fopen>:
+ * RETURNS: 
+ */
+
+VFILE* 
+md_fopen(char * name, char * mode)
+{
+ 803f5e8:	defffd04 	addi	sp,sp,-12
+ 803f5ec:	df000215 	stw	fp,8(sp)
+ 803f5f0:	df000204 	addi	fp,sp,8
+ 803f5f4:	e13fff15 	stw	r4,-4(fp)
+ 803f5f8:	e17ffe15 	stw	r5,-8(fp)
+   USE_ARG(mode);
+   USE_ARG(name);
+   return NULL;
+ 803f5fc:	0005883a 	mov	r2,zero
+}
+ 803f600:	e037883a 	mov	sp,fp
+ 803f604:	df000017 	ldw	fp,0(sp)
+ 803f608:	dec00104 	addi	sp,sp,4
+ 803f60c:	f800283a 	ret
+
+0803f610 <md_fclose>:
+ * RETURNS: 
+ */
+
+void   
+md_fclose(VFILE * vfd)
+{
+ 803f610:	defffe04 	addi	sp,sp,-8
+ 803f614:	df000115 	stw	fp,4(sp)
+ 803f618:	df000104 	addi	fp,sp,4
+ 803f61c:	e13fff15 	stw	r4,-4(fp)
+   USE_ARG(vfd);
+}
+ 803f620:	0001883a 	nop
+ 803f624:	e037883a 	mov	sp,fp
+ 803f628:	df000017 	ldw	fp,0(sp)
+ 803f62c:	dec00104 	addi	sp,sp,4
+ 803f630:	f800283a 	ret
+
+0803f634 <md_fread>:
+ * RETURNS: 
+ */
+
+int    
+md_fread(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+ 803f634:	defff704 	addi	sp,sp,-36
+ 803f638:	dfc00815 	stw	ra,32(sp)
+ 803f63c:	df000715 	stw	fp,28(sp)
+ 803f640:	df000704 	addi	fp,sp,28
+ 803f644:	e13ffc15 	stw	r4,-16(fp)
+ 803f648:	e17ffb15 	stw	r5,-20(fp)
+ 803f64c:	e1bffa15 	stw	r6,-24(fp)
+ 803f650:	e1fff915 	stw	r7,-28(fp)
+   u_long   bcount;     /* number of bytes put in caller's buffer */
+   u_long   location;   /* current offset into file */
+   unsigned long file_size = MEMDEV_SIZE;
+ 803f654:	00800834 	movhi	r2,32
+ 803f658:	e0bffe15 	stw	r2,-8(fp)
+   if(vfd && vfd->file)
+ 803f65c:	e0bff917 	ldw	r2,-28(fp)
+ 803f660:	10000726 	beq	r2,zero,803f680 <md_fread+0x4c>
+ 803f664:	e0bff917 	ldw	r2,-28(fp)
+ 803f668:	10800117 	ldw	r2,4(r2)
+ 803f66c:	10000426 	beq	r2,zero,803f680 <md_fread+0x4c>
+   {
+      file_size = vfd->file->real_size; 
+ 803f670:	e0bff917 	ldw	r2,-28(fp)
+ 803f674:	10800117 	ldw	r2,4(r2)
+ 803f678:	10800717 	ldw	r2,28(r2)
+ 803f67c:	e0bffe15 	stw	r2,-8(fp)
+#ifdef SEG16_16   /* 16-bit x86 must include segment. */
+   if(vfd->cmploc == (u_char*)0xFFFFFFFF)   /* at EOF */
+      return 0;
+   location = (u_long)(((char huge *)vfd->cmploc) - ((char huge *)vfd->file->data));
+#else
+   location = (u_long)(vfd->cmploc - vfd->file->data);
+ 803f680:	e0bff917 	ldw	r2,-28(fp)
+ 803f684:	10c00217 	ldw	r3,8(r2)
+ 803f688:	e0bff917 	ldw	r2,-28(fp)
+ 803f68c:	10800117 	ldw	r2,4(r2)
+ 803f690:	10800617 	ldw	r2,24(r2)
+ 803f694:	1885c83a 	sub	r2,r3,r2
+ 803f698:	e0bffd15 	stw	r2,-12(fp)
+#endif   /* SEG16_16 */
+
+   bcount = (items * (u_long)size);     /* number of bytes to transfer */
+ 803f69c:	e0fffa17 	ldw	r3,-24(fp)
+ 803f6a0:	e0bffb17 	ldw	r2,-20(fp)
+ 803f6a4:	1885383a 	mul	r2,r3,r2
+ 803f6a8:	e0bfff15 	stw	r2,-4(fp)
+
+   /* if near end of memory, trim read count accordingly */
+   if ((location + bcount) > file_size)
+ 803f6ac:	e0fffd17 	ldw	r3,-12(fp)
+ 803f6b0:	e0bfff17 	ldw	r2,-4(fp)
+ 803f6b4:	1885883a 	add	r2,r3,r2
+ 803f6b8:	e0fffe17 	ldw	r3,-8(fp)
+ 803f6bc:	1880042e 	bgeu	r3,r2,803f6d0 <md_fread+0x9c>
+      bcount = ((u_long)file_size - location);
+ 803f6c0:	e0fffe17 	ldw	r3,-8(fp)
+ 803f6c4:	e0bffd17 	ldw	r2,-12(fp)
+ 803f6c8:	1885c83a 	sub	r2,r3,r2
+ 803f6cc:	e0bfff15 	stw	r2,-4(fp)
+
+   /* trap bogus size items and end-of-x86 memory conditions */
+   if((location >= file_size) ||
+ 803f6d0:	e0fffd17 	ldw	r3,-12(fp)
+ 803f6d4:	e0bffe17 	ldw	r2,-8(fp)
+ 803f6d8:	1880052e 	bgeu	r3,r2,803f6f0 <md_fread+0xbc>
+      (bcount  & 0xFFFF0000) ||
+ 803f6dc:	e0bfff17 	ldw	r2,-4(fp)
+ 803f6e0:	10bfffec 	andhi	r2,r2,65535
+   if((location >= file_size) ||
+ 803f6e4:	1000021e 	bne	r2,zero,803f6f0 <md_fread+0xbc>
+      (bcount  & 0xFFFF0000) ||
+ 803f6e8:	e0bfff17 	ldw	r2,-4(fp)
+ 803f6ec:	1000021e 	bne	r2,zero,803f6f8 <md_fread+0xc4>
+      (bcount == 0))
+   {
+      return 0;
+ 803f6f0:	0005883a 	mov	r2,zero
+ 803f6f4:	00002006 	br	803f778 <md_fread+0x144>
+   /* Use VF_NODATA if memory devices have a size, but no
+      data. This can be used to measure file read speed
+      without introducing an undefined data copy. */
+   /* VF_NODATA is defined in ../h/vfsfiles.h */
+   
+   if (!(vfd->file->flags & VF_NODATA))
+ 803f6f8:	e0bff917 	ldw	r2,-28(fp)
+ 803f6fc:	10800117 	ldw	r2,4(r2)
+ 803f700:	1080058b 	ldhu	r2,22(r2)
+ 803f704:	10bfffcc 	andi	r2,r2,65535
+ 803f708:	10a0001c 	xori	r2,r2,32768
+ 803f70c:	10a00004 	addi	r2,r2,-32768
+ 803f710:	10001016 	blt	r2,zero,803f754 <md_fread+0x120>
+   {
+      if (vfd->file->name[0] == 'm')   /* memory device */
+ 803f714:	e0bff917 	ldw	r2,-28(fp)
+ 803f718:	10800117 	ldw	r2,4(r2)
+ 803f71c:	10800103 	ldbu	r2,4(r2)
+ 803f720:	10803fcc 	andi	r2,r2,255
+ 803f724:	1080201c 	xori	r2,r2,128
+ 803f728:	10bfe004 	addi	r2,r2,-128
+ 803f72c:	10801b58 	cmpnei	r2,r2,109
+ 803f730:	1000081e 	bne	r2,zero,803f754 <md_fread+0x120>
+         MEMCPY(buf, vfd->cmploc + MEMDEV_BASE, (unsigned)bcount);
+ 803f734:	e0bff917 	ldw	r2,-28(fp)
+ 803f738:	10c00217 	ldw	r3,8(r2)
+ 803f73c:	00800834 	movhi	r2,32
+ 803f740:	1885883a 	add	r2,r3,r2
+ 803f744:	e1bfff17 	ldw	r6,-4(fp)
+ 803f748:	100b883a 	mov	r5,r2
+ 803f74c:	e13ffc17 	ldw	r4,-16(fp)
+ 803f750:	80086b80 	call	80086b8 <memcpy>
+         vfd->cmploc = (u_char *)cp;
+      else     /* read wrapped memory, set pointer to EOF value */
+         vfd->cmploc = (u_char*)(0xFFFFFFFF);  /* EOF */
+   }
+#else
+   vfd->cmploc += bcount;  /* adjust location */
+ 803f754:	e0bff917 	ldw	r2,-28(fp)
+ 803f758:	10c00217 	ldw	r3,8(r2)
+ 803f75c:	e0bfff17 	ldw	r2,-4(fp)
+ 803f760:	1887883a 	add	r3,r3,r2
+ 803f764:	e0bff917 	ldw	r2,-28(fp)
+ 803f768:	10c00215 	stw	r3,8(r2)
+#endif
+   
+   return ((int)bcount/size);
+ 803f76c:	e17ffb17 	ldw	r5,-20(fp)
+ 803f770:	e13fff17 	ldw	r4,-4(fp)
+ 803f774:	800cff80 	call	800cff8 <__udivsi3>
+}
+ 803f778:	e037883a 	mov	sp,fp
+ 803f77c:	dfc00117 	ldw	ra,4(sp)
+ 803f780:	df000017 	ldw	fp,0(sp)
+ 803f784:	dec00204 	addi	sp,sp,8
+ 803f788:	f800283a 	ret
+
+0803f78c <md_fwrite>:
+ * RETURNS: 
+ */
+
+int    
+md_fwrite(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+ 803f78c:	defffb04 	addi	sp,sp,-20
+ 803f790:	df000415 	stw	fp,16(sp)
+ 803f794:	df000404 	addi	fp,sp,16
+ 803f798:	e13fff15 	stw	r4,-4(fp)
+ 803f79c:	e17ffe15 	stw	r5,-8(fp)
+ 803f7a0:	e1bffd15 	stw	r6,-12(fp)
+ 803f7a4:	e1fffc15 	stw	r7,-16(fp)
+   if (vfd->file->name[0] == 'm')   /* memory device */
+ 803f7a8:	e0bffc17 	ldw	r2,-16(fp)
+ 803f7ac:	10800117 	ldw	r2,4(r2)
+ 803f7b0:	10800103 	ldbu	r2,4(r2)
+ 803f7b4:	10803fcc 	andi	r2,r2,255
+ 803f7b8:	1080201c 	xori	r2,r2,128
+ 803f7bc:	10bfe004 	addi	r2,r2,-128
+ 803f7c0:	10801b58 	cmpnei	r2,r2,109
+ 803f7c4:	1000021e 	bne	r2,zero,803f7d0 <md_fwrite+0x44>
+      return 0;   /* not writable device */
+ 803f7c8:	0005883a 	mov	r2,zero
+ 803f7cc:	00000906 	br	803f7f4 <md_fwrite+0x68>
+
+   vfd->cmploc += (items * size);   /* adjust location */
+ 803f7d0:	e0bffc17 	ldw	r2,-16(fp)
+ 803f7d4:	10c00217 	ldw	r3,8(r2)
+ 803f7d8:	e13ffd17 	ldw	r4,-12(fp)
+ 803f7dc:	e0bffe17 	ldw	r2,-8(fp)
+ 803f7e0:	2085383a 	mul	r2,r4,r2
+ 803f7e4:	1887883a 	add	r3,r3,r2
+ 803f7e8:	e0bffc17 	ldw	r2,-16(fp)
+ 803f7ec:	10c00215 	stw	r3,8(r2)
+
+   USE_ARG(buf);     /* supress compiler warnings */
+
+   return (items);
+ 803f7f0:	e0bffd17 	ldw	r2,-12(fp)
+}
+ 803f7f4:	e037883a 	mov	sp,fp
+ 803f7f8:	df000017 	ldw	fp,0(sp)
+ 803f7fc:	dec00104 	addi	sp,sp,4
+ 803f800:	f800283a 	ret
+
+0803f804 <md_fseek>:
+ * RETURNS: 
+ */
+
+int
+md_fseek(VFILE * vfd, long offset, int mode)
+{
+ 803f804:	defffc04 	addi	sp,sp,-16
+ 803f808:	df000315 	stw	fp,12(sp)
+ 803f80c:	df000304 	addi	fp,sp,12
+ 803f810:	e13fff15 	stw	r4,-4(fp)
+ 803f814:	e17ffe15 	stw	r5,-8(fp)
+ 803f818:	e1bffd15 	stw	r6,-12(fp)
+   USE_ARG(vfd);     /* supress compiler warnings */
+   USE_ARG(offset);
+   USE_ARG(mode);
+   return 0;
+ 803f81c:	0005883a 	mov	r2,zero
+}
+ 803f820:	e037883a 	mov	sp,fp
+ 803f824:	df000017 	ldw	fp,0(sp)
+ 803f828:	dec00104 	addi	sp,sp,4
+ 803f82c:	f800283a 	ret
+
+0803f830 <md_ftell>:
+ * RETURNS: 
+ */
+
+long   
+md_ftell(VFILE * vfd)
+{
+ 803f830:	defffe04 	addi	sp,sp,-8
+ 803f834:	df000115 	stw	fp,4(sp)
+ 803f838:	df000104 	addi	fp,sp,4
+ 803f83c:	e13fff15 	stw	r4,-4(fp)
+   USE_ARG(vfd);     /* supress compiler warnings */
+   return MEMDEV_SIZE;
+ 803f840:	00800834 	movhi	r2,32
+}
+ 803f844:	e037883a 	mov	sp,fp
+ 803f848:	df000017 	ldw	fp,0(sp)
+ 803f84c:	dec00104 	addi	sp,sp,4
+ 803f850:	f800283a 	ret
+
+0803f854 <md_fgetc>:
+ * RETURNS: 
+ */
+
+int    
+md_fgetc(VFILE * vfd)
+{
+ 803f854:	defffc04 	addi	sp,sp,-16
+ 803f858:	df000315 	stw	fp,12(sp)
+ 803f85c:	df000304 	addi	fp,sp,12
+ 803f860:	e13ffd15 	stw	r4,-12(fp)
+   unsigned location;   /* current offset infile */
+   int   retval   =  0;
+ 803f864:	e03fff15 	stw	zero,-4(fp)
+
+   location = vfd->cmploc - vfd->file->data;
+ 803f868:	e0bffd17 	ldw	r2,-12(fp)
+ 803f86c:	10c00217 	ldw	r3,8(r2)
+ 803f870:	e0bffd17 	ldw	r2,-12(fp)
+ 803f874:	10800117 	ldw	r2,4(r2)
+ 803f878:	10800617 	ldw	r2,24(r2)
+ 803f87c:	1885c83a 	sub	r2,r3,r2
+ 803f880:	e0bffe15 	stw	r2,-8(fp)
+   if (location >= vfd->file->real_size)     /* at end of file? */
+ 803f884:	e0bffd17 	ldw	r2,-12(fp)
+ 803f888:	10800117 	ldw	r2,4(r2)
+ 803f88c:	10800717 	ldw	r2,28(r2)
+ 803f890:	e0fffe17 	ldw	r3,-8(fp)
+ 803f894:	18800236 	bltu	r3,r2,803f8a0 <md_fgetc+0x4c>
+      return EOF;
+ 803f898:	00bfffc4 	movi	r2,-1
+ 803f89c:	00001a06 	br	803f908 <md_fgetc+0xb4>
+
+   if (!(vfd->file->flags & VF_NODATA))
+ 803f8a0:	e0bffd17 	ldw	r2,-12(fp)
+ 803f8a4:	10800117 	ldw	r2,4(r2)
+ 803f8a8:	1080058b 	ldhu	r2,22(r2)
+ 803f8ac:	10bfffcc 	andi	r2,r2,65535
+ 803f8b0:	10a0001c 	xori	r2,r2,32768
+ 803f8b4:	10a00004 	addi	r2,r2,-32768
+ 803f8b8:	10000d16 	blt	r2,zero,803f8f0 <md_fgetc+0x9c>
+   {
+      if (vfd->file->name[0] == 'm')   /* memory device */
+ 803f8bc:	e0bffd17 	ldw	r2,-12(fp)
+ 803f8c0:	10800117 	ldw	r2,4(r2)
+ 803f8c4:	10800103 	ldbu	r2,4(r2)
+ 803f8c8:	10803fcc 	andi	r2,r2,255
+ 803f8cc:	1080201c 	xori	r2,r2,128
+ 803f8d0:	10bfe004 	addi	r2,r2,-128
+ 803f8d4:	10801b58 	cmpnei	r2,r2,109
+ 803f8d8:	1000051e 	bne	r2,zero,803f8f0 <md_fgetc+0x9c>
+         retval = (int)(*vfd->cmploc) & 0xFF ;
+ 803f8dc:	e0bffd17 	ldw	r2,-12(fp)
+ 803f8e0:	10800217 	ldw	r2,8(r2)
+ 803f8e4:	10800003 	ldbu	r2,0(r2)
+ 803f8e8:	10803fcc 	andi	r2,r2,255
+ 803f8ec:	e0bfff15 	stw	r2,-4(fp)
+   }
+
+   /* else for null device or files without data, 
+      use whatever is in retval */
+
+   vfd->cmploc++;    /* adjust location */
+ 803f8f0:	e0bffd17 	ldw	r2,-12(fp)
+ 803f8f4:	10800217 	ldw	r2,8(r2)
+ 803f8f8:	10c00044 	addi	r3,r2,1
+ 803f8fc:	e0bffd17 	ldw	r2,-12(fp)
+ 803f900:	10c00215 	stw	r3,8(r2)
+   return retval;
+ 803f904:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 803f908:	e037883a 	mov	sp,fp
+ 803f90c:	df000017 	ldw	fp,0(sp)
+ 803f910:	dec00104 	addi	sp,sp,4
+ 803f914:	f800283a 	ret
+
+0803f918 <md_unlink>:
+ * RETURNS: 
+ */
+
+int    
+md_unlink(char * filename)
+{
+ 803f918:	defffe04 	addi	sp,sp,-8
+ 803f91c:	df000115 	stw	fp,4(sp)
+ 803f920:	df000104 	addi	fp,sp,4
+ 803f924:	e13fff15 	stw	r4,-4(fp)
+   USE_ARG(filename);     /* supress compiler warnings */
+   return 0;
+ 803f928:	0005883a 	mov	r2,zero
+}
+ 803f92c:	e037883a 	mov	sp,fp
+ 803f930:	df000017 	ldw	fp,0(sp)
+ 803f934:	dec00104 	addi	sp,sp,4
+ 803f938:	f800283a 	ret
+
+0803f93c <parse_ipad>:
+
+char *   
+parse_ipad(ip_addr * ipout,   /* pointer to IP address to set */
+   unsigned *  sbits,      /* default subnet bit number */
+   char *   stringin)      /* buffer with ascii to parse */
+{
+ 803f93c:	defff604 	addi	sp,sp,-40
+ 803f940:	dfc00915 	stw	ra,36(sp)
+ 803f944:	df000815 	stw	fp,32(sp)
+ 803f948:	df000804 	addi	fp,sp,32
+ 803f94c:	e13ffa15 	stw	r4,-24(fp)
+ 803f950:	e17ff915 	stw	r5,-28(fp)
+ 803f954:	e1bff815 	stw	r6,-32(fp)
+   char *   cp;
+   int   dots  =  0; /* periods imbedded in input string */
+ 803f958:	e03ffe15 	stw	zero,-8(fp)
+   union   
+   {
+      u_char   c[4];
+      u_long   l;
+   } retval;
+   char *   toobig   = "each number must be less than 255";
+ 803f95c:	00820174 	movhi	r2,2053
+ 803f960:	10ade204 	addi	r2,r2,-18552
+ 803f964:	e0bffd15 	stw	r2,-12(fp)
+
+   cp = stringin;
+ 803f968:	e0bff817 	ldw	r2,-32(fp)
+ 803f96c:	e0bfff15 	stw	r2,-4(fp)
+   while (*cp)
+ 803f970:	00002506 	br	803fa08 <parse_ipad+0xcc>
+   {
+      if (*cp > '9' || *cp < '.' || *cp == '/')
+ 803f974:	e0bfff17 	ldw	r2,-4(fp)
+ 803f978:	10800003 	ldbu	r2,0(r2)
+ 803f97c:	10803fcc 	andi	r2,r2,255
+ 803f980:	1080201c 	xori	r2,r2,128
+ 803f984:	10bfe004 	addi	r2,r2,-128
+ 803f988:	10800e88 	cmpgei	r2,r2,58
+ 803f98c:	10000e1e 	bne	r2,zero,803f9c8 <parse_ipad+0x8c>
+ 803f990:	e0bfff17 	ldw	r2,-4(fp)
+ 803f994:	10800003 	ldbu	r2,0(r2)
+ 803f998:	10803fcc 	andi	r2,r2,255
+ 803f99c:	1080201c 	xori	r2,r2,128
+ 803f9a0:	10bfe004 	addi	r2,r2,-128
+ 803f9a4:	10800b90 	cmplti	r2,r2,46
+ 803f9a8:	1000071e 	bne	r2,zero,803f9c8 <parse_ipad+0x8c>
+ 803f9ac:	e0bfff17 	ldw	r2,-4(fp)
+ 803f9b0:	10800003 	ldbu	r2,0(r2)
+ 803f9b4:	10803fcc 	andi	r2,r2,255
+ 803f9b8:	1080201c 	xori	r2,r2,128
+ 803f9bc:	10bfe004 	addi	r2,r2,-128
+ 803f9c0:	10800bd8 	cmpnei	r2,r2,47
+ 803f9c4:	1000031e 	bne	r2,zero,803f9d4 <parse_ipad+0x98>
+         return("all chars must be digits (0-9) or dots (.)");
+ 803f9c8:	00820174 	movhi	r2,2053
+ 803f9cc:	10adeb04 	addi	r2,r2,-18516
+ 803f9d0:	00009406 	br	803fc24 <parse_ipad+0x2e8>
+      if (*cp == '.')dots++;
+ 803f9d4:	e0bfff17 	ldw	r2,-4(fp)
+ 803f9d8:	10800003 	ldbu	r2,0(r2)
+ 803f9dc:	10803fcc 	andi	r2,r2,255
+ 803f9e0:	1080201c 	xori	r2,r2,128
+ 803f9e4:	10bfe004 	addi	r2,r2,-128
+ 803f9e8:	10800b98 	cmpnei	r2,r2,46
+ 803f9ec:	1000031e 	bne	r2,zero,803f9fc <parse_ipad+0xc0>
+ 803f9f0:	e0bffe17 	ldw	r2,-8(fp)
+ 803f9f4:	10800044 	addi	r2,r2,1
+ 803f9f8:	e0bffe15 	stw	r2,-8(fp)
+         cp++;
+ 803f9fc:	e0bfff17 	ldw	r2,-4(fp)
+ 803fa00:	10800044 	addi	r2,r2,1
+ 803fa04:	e0bfff15 	stw	r2,-4(fp)
+   while (*cp)
+ 803fa08:	e0bfff17 	ldw	r2,-4(fp)
+ 803fa0c:	10800003 	ldbu	r2,0(r2)
+ 803fa10:	10803fcc 	andi	r2,r2,255
+ 803fa14:	1080201c 	xori	r2,r2,128
+ 803fa18:	10bfe004 	addi	r2,r2,-128
+ 803fa1c:	103fd51e 	bne	r2,zero,803f974 <parse_ipad+0x38>
+   }
+
+   if ( dots < 1 || dots > 3 )
+ 803fa20:	e0bffe17 	ldw	r2,-8(fp)
+ 803fa24:	0080030e 	bge	zero,r2,803fa34 <parse_ipad+0xf8>
+ 803fa28:	e0bffe17 	ldw	r2,-8(fp)
+ 803fa2c:	10800110 	cmplti	r2,r2,4
+ 803fa30:	1000031e 	bne	r2,zero,803fa40 <parse_ipad+0x104>
+      return("string must contain 1 - 3 dots (.)");
+ 803fa34:	00820174 	movhi	r2,2053
+ 803fa38:	10adf604 	addi	r2,r2,-18472
+ 803fa3c:	00007906 	br	803fc24 <parse_ipad+0x2e8>
+
+   cp = stringin;
+ 803fa40:	e0bff817 	ldw	r2,-32(fp)
+ 803fa44:	e0bfff15 	stw	r2,-4(fp)
+   if ((number = atoi(cp)) > 255)   /* set net number */
+ 803fa48:	e13fff17 	ldw	r4,-4(fp)
+ 803fa4c:	8042aa40 	call	8042aa4 <atoi>
+ 803fa50:	e0bffc15 	stw	r2,-16(fp)
+ 803fa54:	e0bffc17 	ldw	r2,-16(fp)
+ 803fa58:	10804010 	cmplti	r2,r2,256
+ 803fa5c:	1000021e 	bne	r2,zero,803fa68 <parse_ipad+0x12c>
+      return(toobig);
+ 803fa60:	e0bffd17 	ldw	r2,-12(fp)
+ 803fa64:	00006f06 	br	803fc24 <parse_ipad+0x2e8>
+
+   retval.c[0] = (u_char)number;
+ 803fa68:	e0bffc17 	ldw	r2,-16(fp)
+ 803fa6c:	e0bffb05 	stb	r2,-20(fp)
+
+   while (*cp != '.')cp++; /* find dot (end of number) */
+ 803fa70:	00000306 	br	803fa80 <parse_ipad+0x144>
+ 803fa74:	e0bfff17 	ldw	r2,-4(fp)
+ 803fa78:	10800044 	addi	r2,r2,1
+ 803fa7c:	e0bfff15 	stw	r2,-4(fp)
+ 803fa80:	e0bfff17 	ldw	r2,-4(fp)
+ 803fa84:	10800003 	ldbu	r2,0(r2)
+ 803fa88:	10803fcc 	andi	r2,r2,255
+ 803fa8c:	1080201c 	xori	r2,r2,128
+ 803fa90:	10bfe004 	addi	r2,r2,-128
+ 803fa94:	10800b98 	cmpnei	r2,r2,46
+ 803fa98:	103ff61e 	bne	r2,zero,803fa74 <parse_ipad+0x138>
+      cp++;             /* point past dot */
+ 803fa9c:	e0bfff17 	ldw	r2,-4(fp)
+ 803faa0:	10800044 	addi	r2,r2,1
+ 803faa4:	e0bfff15 	stw	r2,-4(fp)
+
+   if (dots == 1 || dots == 2) retval.c[1] = 0;
+ 803faa8:	e0bffe17 	ldw	r2,-8(fp)
+ 803faac:	10800060 	cmpeqi	r2,r2,1
+ 803fab0:	1000031e 	bne	r2,zero,803fac0 <parse_ipad+0x184>
+ 803fab4:	e0bffe17 	ldw	r2,-8(fp)
+ 803fab8:	10800098 	cmpnei	r2,r2,2
+ 803fabc:	1000021e 	bne	r2,zero,803fac8 <parse_ipad+0x18c>
+ 803fac0:	e03ffb45 	stb	zero,-19(fp)
+ 803fac4:	00001806 	br	803fb28 <parse_ipad+0x1ec>
+      else
+   {
+      number = atoi(cp);
+ 803fac8:	e13fff17 	ldw	r4,-4(fp)
+ 803facc:	8042aa40 	call	8042aa4 <atoi>
+ 803fad0:	e0bffc15 	stw	r2,-16(fp)
+      while (*cp != '.')cp++; /* find dot (end of number) */
+ 803fad4:	00000306 	br	803fae4 <parse_ipad+0x1a8>
+ 803fad8:	e0bfff17 	ldw	r2,-4(fp)
+ 803fadc:	10800044 	addi	r2,r2,1
+ 803fae0:	e0bfff15 	stw	r2,-4(fp)
+ 803fae4:	e0bfff17 	ldw	r2,-4(fp)
+ 803fae8:	10800003 	ldbu	r2,0(r2)
+ 803faec:	10803fcc 	andi	r2,r2,255
+ 803faf0:	1080201c 	xori	r2,r2,128
+ 803faf4:	10bfe004 	addi	r2,r2,-128
+ 803faf8:	10800b98 	cmpnei	r2,r2,46
+ 803fafc:	103ff61e 	bne	r2,zero,803fad8 <parse_ipad+0x19c>
+         cp++;             /* point past dot */
+ 803fb00:	e0bfff17 	ldw	r2,-4(fp)
+ 803fb04:	10800044 	addi	r2,r2,1
+ 803fb08:	e0bfff15 	stw	r2,-4(fp)
+      if (number > 255) return(toobig);
+ 803fb0c:	e0bffc17 	ldw	r2,-16(fp)
+ 803fb10:	10804010 	cmplti	r2,r2,256
+ 803fb14:	1000021e 	bne	r2,zero,803fb20 <parse_ipad+0x1e4>
+ 803fb18:	e0bffd17 	ldw	r2,-12(fp)
+ 803fb1c:	00004106 	br	803fc24 <parse_ipad+0x2e8>
+         retval.c[1] = (u_char)number;
+ 803fb20:	e0bffc17 	ldw	r2,-16(fp)
+ 803fb24:	e0bffb45 	stb	r2,-19(fp)
+   }
+
+   if (dots == 1) retval.c[2] = 0;
+ 803fb28:	e0bffe17 	ldw	r2,-8(fp)
+ 803fb2c:	10800058 	cmpnei	r2,r2,1
+ 803fb30:	1000021e 	bne	r2,zero,803fb3c <parse_ipad+0x200>
+ 803fb34:	e03ffb85 	stb	zero,-18(fp)
+ 803fb38:	00001806 	br	803fb9c <parse_ipad+0x260>
+      else
+   {
+      number = atoi(cp);
+ 803fb3c:	e13fff17 	ldw	r4,-4(fp)
+ 803fb40:	8042aa40 	call	8042aa4 <atoi>
+ 803fb44:	e0bffc15 	stw	r2,-16(fp)
+      while (*cp != '.')cp++; /* find dot (end of number) */
+ 803fb48:	00000306 	br	803fb58 <parse_ipad+0x21c>
+ 803fb4c:	e0bfff17 	ldw	r2,-4(fp)
+ 803fb50:	10800044 	addi	r2,r2,1
+ 803fb54:	e0bfff15 	stw	r2,-4(fp)
+ 803fb58:	e0bfff17 	ldw	r2,-4(fp)
+ 803fb5c:	10800003 	ldbu	r2,0(r2)
+ 803fb60:	10803fcc 	andi	r2,r2,255
+ 803fb64:	1080201c 	xori	r2,r2,128
+ 803fb68:	10bfe004 	addi	r2,r2,-128
+ 803fb6c:	10800b98 	cmpnei	r2,r2,46
+ 803fb70:	103ff61e 	bne	r2,zero,803fb4c <parse_ipad+0x210>
+         cp++;             /* point past dot */
+ 803fb74:	e0bfff17 	ldw	r2,-4(fp)
+ 803fb78:	10800044 	addi	r2,r2,1
+ 803fb7c:	e0bfff15 	stw	r2,-4(fp)
+      if (number > 255) return(toobig);
+ 803fb80:	e0bffc17 	ldw	r2,-16(fp)
+ 803fb84:	10804010 	cmplti	r2,r2,256
+ 803fb88:	1000021e 	bne	r2,zero,803fb94 <parse_ipad+0x258>
+ 803fb8c:	e0bffd17 	ldw	r2,-12(fp)
+ 803fb90:	00002406 	br	803fc24 <parse_ipad+0x2e8>
+         retval.c[2] = (u_char)number;
+ 803fb94:	e0bffc17 	ldw	r2,-16(fp)
+ 803fb98:	e0bffb85 	stb	r2,-18(fp)
+   }
+
+   if ((number = atoi(cp)) > 255)
+ 803fb9c:	e13fff17 	ldw	r4,-4(fp)
+ 803fba0:	8042aa40 	call	8042aa4 <atoi>
+ 803fba4:	e0bffc15 	stw	r2,-16(fp)
+ 803fba8:	e0bffc17 	ldw	r2,-16(fp)
+ 803fbac:	10804010 	cmplti	r2,r2,256
+ 803fbb0:	1000021e 	bne	r2,zero,803fbbc <parse_ipad+0x280>
+      return(toobig);
+ 803fbb4:	e0bffd17 	ldw	r2,-12(fp)
+ 803fbb8:	00001a06 	br	803fc24 <parse_ipad+0x2e8>
+   retval.c[3] = (u_char)number;
+ 803fbbc:	e0bffc17 	ldw	r2,-16(fp)
+ 803fbc0:	e0bffbc5 	stb	r2,-17(fp)
+
+   if (retval.c[0] < 128) *sbits = 8;
+ 803fbc4:	e0bffb03 	ldbu	r2,-20(fp)
+ 803fbc8:	10803fcc 	andi	r2,r2,255
+ 803fbcc:	1080201c 	xori	r2,r2,128
+ 803fbd0:	10bfe004 	addi	r2,r2,-128
+ 803fbd4:	10000416 	blt	r2,zero,803fbe8 <parse_ipad+0x2ac>
+ 803fbd8:	e0bff917 	ldw	r2,-28(fp)
+ 803fbdc:	00c00204 	movi	r3,8
+ 803fbe0:	10c00015 	stw	r3,0(r2)
+ 803fbe4:	00000b06 	br	803fc14 <parse_ipad+0x2d8>
+      else if(retval.c[0] < 192) *sbits = 16;
+ 803fbe8:	e0bffb03 	ldbu	r2,-20(fp)
+ 803fbec:	10803fcc 	andi	r2,r2,255
+ 803fbf0:	10803028 	cmpgeui	r2,r2,192
+ 803fbf4:	1000041e 	bne	r2,zero,803fc08 <parse_ipad+0x2cc>
+ 803fbf8:	e0bff917 	ldw	r2,-28(fp)
+ 803fbfc:	00c00404 	movi	r3,16
+ 803fc00:	10c00015 	stw	r3,0(r2)
+ 803fc04:	00000306 	br	803fc14 <parse_ipad+0x2d8>
+      else *sbits = 24;
+ 803fc08:	e0bff917 	ldw	r2,-28(fp)
+ 803fc0c:	00c00604 	movi	r3,24
+ 803fc10:	10c00015 	stw	r3,0(r2)
+
+      *ipout = retval.l;      /* everything went OK, return number */
+ 803fc14:	e0fffb17 	ldw	r3,-20(fp)
+ 803fc18:	e0bffa17 	ldw	r2,-24(fp)
+ 803fc1c:	10c00015 	stw	r3,0(r2)
+   return(NULL);        /* return OK code (no error string) */
+ 803fc20:	0005883a 	mov	r2,zero
+}
+ 803fc24:	e037883a 	mov	sp,fp
+ 803fc28:	dfc00117 	ldw	ra,4(sp)
+ 803fc2c:	df000017 	ldw	fp,0(sp)
+ 803fc30:	dec00204 	addi	sp,sp,8
+ 803fc34:	f800283a 	ret
+
+0803fc38 <inet_addr>:
+ * RETURNS: u_long ipaddr
+ */
+
+u_long 
+inet_addr(char FAR * str)
+{
+ 803fc38:	defffb04 	addi	sp,sp,-20
+ 803fc3c:	dfc00415 	stw	ra,16(sp)
+ 803fc40:	df000315 	stw	fp,12(sp)
+ 803fc44:	df000304 	addi	fp,sp,12
+ 803fc48:	e13ffd15 	stw	r4,-12(fp)
+    * we need to make the conversion. Usually this function will be 
+    * used for debugging, so I think we can bear the STRCPY overhead.
+    */
+   static char nearBuf[30];
+
+   strcpy((char FAR *)nearBuf,str);
+ 803fc4c:	e17ffd17 	ldw	r5,-12(fp)
+ 803fc50:	01020174 	movhi	r4,2053
+ 803fc54:	21338304 	addi	r4,r4,-12788
+ 803fc58:	8042f600 	call	8042f60 <strcpy>
+   if ( parse_ipad(&ipaddr,&bits,nearBuf) == NULL )
+ 803fc5c:	e0fffe04 	addi	r3,fp,-8
+ 803fc60:	e0bfff04 	addi	r2,fp,-4
+ 803fc64:	01820174 	movhi	r6,2053
+ 803fc68:	31b38304 	addi	r6,r6,-12788
+ 803fc6c:	180b883a 	mov	r5,r3
+ 803fc70:	1009883a 	mov	r4,r2
+ 803fc74:	803f93c0 	call	803f93c <parse_ipad>
+ 803fc78:	1000021e 	bne	r2,zero,803fc84 <inet_addr+0x4c>
+   {
+      return ipaddr ;
+ 803fc7c:	e0bfff17 	ldw	r2,-4(fp)
+ 803fc80:	00000106 	br	803fc88 <inet_addr+0x50>
+   }
+   else
+   {
+      return (u_long)NULL ;
+ 803fc84:	0005883a 	mov	r2,zero
+   }
+}
+ 803fc88:	e037883a 	mov	sp,fp
+ 803fc8c:	dfc00117 	ldw	ra,4(sp)
+ 803fc90:	df000017 	ldw	fp,0(sp)
+ 803fc94:	dec00204 	addi	sp,sp,8
+ 803fc98:	f800283a 	ret
+
+0803fc9c <hextoa>:
+ * RETURNS: character 0-9 or A-F
+ */
+
+char
+hextoa(int val)
+{
+ 803fc9c:	defffe04 	addi	sp,sp,-8
+ 803fca0:	df000115 	stw	fp,4(sp)
+ 803fca4:	df000104 	addi	fp,sp,4
+ 803fca8:	e13fff15 	stw	r4,-4(fp)
+   val &= 0x0f;
+ 803fcac:	e0bfff17 	ldw	r2,-4(fp)
+ 803fcb0:	108003cc 	andi	r2,r2,15
+ 803fcb4:	e0bfff15 	stw	r2,-4(fp)
+   if(val < 10)
+ 803fcb8:	e0bfff17 	ldw	r2,-4(fp)
+ 803fcbc:	10800288 	cmpgei	r2,r2,10
+ 803fcc0:	1000031e 	bne	r2,zero,803fcd0 <hextoa+0x34>
+      return (char)(val + '0');
+ 803fcc4:	e0bfff17 	ldw	r2,-4(fp)
+ 803fcc8:	10800c04 	addi	r2,r2,48
+ 803fccc:	00000206 	br	803fcd8 <hextoa+0x3c>
+   else
+      return (char)(val + 55);   /* converts 10-15 -> "A-F" */
+ 803fcd0:	e0bfff17 	ldw	r2,-4(fp)
+ 803fcd4:	10800dc4 	addi	r2,r2,55
+}
+ 803fcd8:	e037883a 	mov	sp,fp
+ 803fcdc:	df000017 	ldw	fp,0(sp)
+ 803fce0:	dec00104 	addi	sp,sp,4
+ 803fce4:	f800283a 	ret
+
+0803fce8 <inet_pton>:
+
+char * pton_error = "";
+
+int
+inet_pton(int af, const char * src, void * dst)
+{
+ 803fce8:	defff804 	addi	sp,sp,-32
+ 803fcec:	dfc00715 	stw	ra,28(sp)
+ 803fcf0:	df000615 	stw	fp,24(sp)
+ 803fcf4:	df000604 	addi	fp,sp,24
+ 803fcf8:	e13ffc15 	stw	r4,-16(fp)
+ 803fcfc:	e17ffb15 	stw	r5,-20(fp)
+ 803fd00:	e1bffa15 	stw	r6,-24(fp)
+   int            words;   /* count of words written to dest */
+#endif
+
+#if defined(IP_V4) || defined(MINI_IP)
+   /* RFC 2133 wants us to support both types of address */
+   if(af == AF_INET)    /* wants a v4 address */
+ 803fd04:	e0bffc17 	ldw	r2,-16(fp)
+ 803fd08:	10800098 	cmpnei	r2,r2,2
+ 803fd0c:	1000151e 	bne	r2,zero,803fd64 <inet_pton+0x7c>
+   {
+      u_long ip4addr;
+      unsigned sbits;
+      char * err;
+      
+      err = parse_ipad(&ip4addr, &sbits, (char *) src);
+ 803fd10:	e0fffd04 	addi	r3,fp,-12
+ 803fd14:	e0bffe04 	addi	r2,fp,-8
+ 803fd18:	e1bffb17 	ldw	r6,-20(fp)
+ 803fd1c:	180b883a 	mov	r5,r3
+ 803fd20:	1009883a 	mov	r4,r2
+ 803fd24:	803f93c0 	call	803f93c <parse_ipad>
+ 803fd28:	e0bfff15 	stw	r2,-4(fp)
+      if(err == NULL)
+ 803fd2c:	e0bfff17 	ldw	r2,-4(fp)
+ 803fd30:	1000071e 	bne	r2,zero,803fd50 <inet_pton+0x68>
+      {
+         /* copy the parsed address into caller's buffer, and 
+          * return success
+          */
+         MEMCPY(dst, &ip4addr, sizeof (u_long));
+ 803fd34:	e0bffe04 	addi	r2,fp,-8
+ 803fd38:	01800104 	movi	r6,4
+ 803fd3c:	100b883a 	mov	r5,r2
+ 803fd40:	e13ffa17 	ldw	r4,-24(fp)
+ 803fd44:	80086b80 	call	80086b8 <memcpy>
+         return 0;
+ 803fd48:	0005883a 	mov	r2,zero
+ 803fd4c:	00000606 	br	803fd68 <inet_pton+0x80>
+      }
+      else
+      {
+         /* return failure */
+         pton_error = "IPv4 address parse failure";
+ 803fd50:	00820174 	movhi	r2,2053
+ 803fd54:	10ae0004 	addi	r2,r2,-18432
+ 803fd58:	d0a03315 	stw	r2,-32564(gp)
+         return 1;
+ 803fd5c:	00800044 	movi	r2,1
+ 803fd60:	00000106 	br	803fd68 <inet_pton+0x80>
+      pton_error = "too short - missing colon?";
+      return 1;
+   }
+   
+#endif /* IP_V6 */   
+   return 0;
+ 803fd64:	0005883a 	mov	r2,zero
+}
+ 803fd68:	e037883a 	mov	sp,fp
+ 803fd6c:	dfc00117 	ldw	ra,4(sp)
+ 803fd70:	df000017 	ldw	fp,0(sp)
+ 803fd74:	dec00204 	addi	sp,sp,8
+ 803fd78:	f800283a 	ret
+
+0803fd7c <inet_ntop>:
+ * address output (40 bytes).
+ */
+
+const char *
+inet_ntop(int af, const void *addr, char *str, size_t size)
+{
+ 803fd7c:	defff804 	addi	sp,sp,-32
+ 803fd80:	dfc00715 	stw	ra,28(sp)
+ 803fd84:	df000615 	stw	fp,24(sp)
+ 803fd88:	df000604 	addi	fp,sp,24
+ 803fd8c:	e13ffd15 	stw	r4,-12(fp)
+ 803fd90:	e17ffc15 	stw	r5,-16(fp)
+ 803fd94:	e1bffb15 	stw	r6,-20(fp)
+ 803fd98:	e1fffa15 	stw	r7,-24(fp)
+   char *cp;
+
+#if defined(IP_V4) || defined(MINI_IP)
+   if (af == AF_INET)
+ 803fd9c:	e0bffd17 	ldw	r2,-12(fp)
+ 803fda0:	10800098 	cmpnei	r2,r2,2
+ 803fda4:	1000101e 	bne	r2,zero,803fde8 <inet_ntop+0x6c>
+   {
+      u_long   ip4addr;
+
+      ip4addr = *(u_long*)addr;
+ 803fda8:	e0bffc17 	ldw	r2,-16(fp)
+ 803fdac:	10800017 	ldw	r2,0(r2)
+ 803fdb0:	e0bfff15 	stw	r2,-4(fp)
+      cp = print_ipad(ip4addr);
+ 803fdb4:	e13fff17 	ldw	r4,-4(fp)
+ 803fdb8:	8026fbc0 	call	8026fbc <print_ipad>
+ 803fdbc:	e0bffe15 	stw	r2,-8(fp)
+      if (strlen(cp) < size)
+ 803fdc0:	e13ffe17 	ldw	r4,-8(fp)
+ 803fdc4:	8002dac0 	call	8002dac <strlen>
+ 803fdc8:	1007883a 	mov	r3,r2
+ 803fdcc:	e0bffa17 	ldw	r2,-24(fp)
+ 803fdd0:	1880052e 	bgeu	r3,r2,803fde8 <inet_ntop+0x6c>
+      {
+         strcpy(str, cp);
+ 803fdd4:	e17ffe17 	ldw	r5,-8(fp)
+ 803fdd8:	e13ffb17 	ldw	r4,-20(fp)
+ 803fddc:	8042f600 	call	8042f60 <strcpy>
+         return (str);
+ 803fde0:	e0bffb17 	ldw	r2,-20(fp)
+ 803fde4:	00000106 	br	803fdec <inet_ntop+0x70>
+         return (str);
+      }
+   }
+#endif
+
+   return ((const char *)NULL);
+ 803fde8:	0005883a 	mov	r2,zero
+}
+ 803fdec:	e037883a 	mov	sp,fp
+ 803fdf0:	dfc00117 	ldw	ra,4(sp)
+ 803fdf4:	df000017 	ldw	fp,0(sp)
+ 803fdf8:	dec00204 	addi	sp,sp,8
+ 803fdfc:	f800283a 	ret
+
+0803fe00 <print46_addr>:
+ *
+ * RETURNS: Pointer to string with the address in readable format.
+ */
+
+char * print46_addr(struct sockaddr *ipaddr)
+{
+ 803fe00:	defffc04 	addi	sp,sp,-16
+ 803fe04:	dfc00315 	stw	ra,12(sp)
+ 803fe08:	df000215 	stw	fp,8(sp)
+ 803fe0c:	df000204 	addi	fp,sp,8
+ 803fe10:	e13ffe15 	stw	r4,-8(fp)
+   if (ipaddr->sa_family == AF_INET)
+ 803fe14:	e0bffe17 	ldw	r2,-8(fp)
+ 803fe18:	1080000b 	ldhu	r2,0(r2)
+ 803fe1c:	10bfffcc 	andi	r2,r2,65535
+ 803fe20:	10800098 	cmpnei	r2,r2,2
+ 803fe24:	1000071e 	bne	r2,zero,803fe44 <print46_addr+0x44>
+   {
+      struct sockaddr_in * addr = (struct sockaddr_in *)ipaddr;
+ 803fe28:	e0bffe17 	ldw	r2,-8(fp)
+ 803fe2c:	e0bfff15 	stw	r2,-4(fp)
+      return print_ipad(addr->sin_addr.s_addr);
+ 803fe30:	e0bfff17 	ldw	r2,-4(fp)
+ 803fe34:	10800117 	ldw	r2,4(r2)
+ 803fe38:	1009883a 	mov	r4,r2
+ 803fe3c:	8026fbc0 	call	8026fbc <print_ipad>
+ 803fe40:	00000106 	br	803fe48 <print46_addr+0x48>
+      static char namebuf[46];  /* max len of IPv6 addr */
+      return (char *)inet_ntop(AF_INET6,&addr->sin6_addr, namebuf, sizeof(namebuf));
+   }
+#endif
+
+   return NULL;
+ 803fe44:	0005883a 	mov	r2,zero
+}
+ 803fe48:	e037883a 	mov	sp,fp
+ 803fe4c:	dfc00117 	ldw	ra,4(sp)
+ 803fe50:	df000017 	ldw	fp,0(sp)
+ 803fe54:	dec00204 	addi	sp,sp,8
+ 803fe58:	f800283a 	ret
+
+0803fe5c <inet46_addr>:
+ *
+ */
+
+int 
+inet46_addr(char * str, struct sockaddr *address)
+{
+ 803fe5c:	defffb04 	addi	sp,sp,-20
+ 803fe60:	dfc00415 	stw	ra,16(sp)
+ 803fe64:	df000315 	stw	fp,12(sp)
+ 803fe68:	df000304 	addi	fp,sp,12
+ 803fe6c:	e13ffe15 	stw	r4,-8(fp)
+ 803fe70:	e17ffd15 	stw	r5,-12(fp)
+   /* Read the IPv4/IPv6 address */
+   address->sa_family = AF_INET; /* assume IPv4 address by default */
+ 803fe74:	e0bffd17 	ldw	r2,-12(fp)
+ 803fe78:	00c00084 	movi	r3,2
+ 803fe7c:	10c0000d 	sth	r3,0(r2)
+
+   if ((str[1] == '.') || (str[2] == '.') || (str[3] == '.'))
+ 803fe80:	e0bffe17 	ldw	r2,-8(fp)
+ 803fe84:	10800044 	addi	r2,r2,1
+ 803fe88:	10800003 	ldbu	r2,0(r2)
+ 803fe8c:	10803fcc 	andi	r2,r2,255
+ 803fe90:	1080201c 	xori	r2,r2,128
+ 803fe94:	10bfe004 	addi	r2,r2,-128
+ 803fe98:	10800ba0 	cmpeqi	r2,r2,46
+ 803fe9c:	1000101e 	bne	r2,zero,803fee0 <inet46_addr+0x84>
+ 803fea0:	e0bffe17 	ldw	r2,-8(fp)
+ 803fea4:	10800084 	addi	r2,r2,2
+ 803fea8:	10800003 	ldbu	r2,0(r2)
+ 803feac:	10803fcc 	andi	r2,r2,255
+ 803feb0:	1080201c 	xori	r2,r2,128
+ 803feb4:	10bfe004 	addi	r2,r2,-128
+ 803feb8:	10800ba0 	cmpeqi	r2,r2,46
+ 803febc:	1000081e 	bne	r2,zero,803fee0 <inet46_addr+0x84>
+ 803fec0:	e0bffe17 	ldw	r2,-8(fp)
+ 803fec4:	108000c4 	addi	r2,r2,3
+ 803fec8:	10800003 	ldbu	r2,0(r2)
+ 803fecc:	10803fcc 	andi	r2,r2,255
+ 803fed0:	1080201c 	xori	r2,r2,128
+ 803fed4:	10bfe004 	addi	r2,r2,-128
+ 803fed8:	10800b98 	cmpnei	r2,r2,46
+ 803fedc:	10000a1e 	bne	r2,zero,803ff08 <inet46_addr+0xac>
+   {
+      struct sockaddr_in *addr = (struct sockaddr_in *)address;
+ 803fee0:	e0bffd17 	ldw	r2,-12(fp)
+ 803fee4:	e0bfff15 	stw	r2,-4(fp)
+      addr->sin_addr.s_addr = inet_addr(str);
+ 803fee8:	e13ffe17 	ldw	r4,-8(fp)
+ 803feec:	803fc380 	call	803fc38 <inet_addr>
+ 803fef0:	1007883a 	mov	r3,r2
+ 803fef4:	e0bfff17 	ldw	r2,-4(fp)
+ 803fef8:	10c00115 	stw	r3,4(r2)
+      addr->sin_family = AF_INET;
+ 803fefc:	e0bfff17 	ldw	r2,-4(fp)
+ 803ff00:	00c00084 	movi	r3,2
+ 803ff04:	10c0000d 	sth	r3,0(r2)
+      inet_pton(AF_INET6, str, &addr->sin6_addr);
+      addr->sin6_family = AF_INET6;
+   }
+#endif
+
+   return 0;
+ 803ff08:	0005883a 	mov	r2,zero
+}
+ 803ff0c:	e037883a 	mov	sp,fp
+ 803ff10:	dfc00117 	ldw	ra,4(sp)
+ 803ff14:	df000017 	ldw	fp,0(sp)
+ 803ff18:	dec00204 	addi	sp,sp,8
+ 803ff1c:	f800283a 	ret
+
+0803ff20 <inet_setport>:
+ *
+ * RETURNS: -
+ */
+
+void inet_setport(struct sockaddr *addr,int port) 
+{
+ 803ff20:	defffc04 	addi	sp,sp,-16
+ 803ff24:	df000315 	stw	fp,12(sp)
+ 803ff28:	df000304 	addi	fp,sp,12
+ 803ff2c:	e13ffe15 	stw	r4,-8(fp)
+ 803ff30:	e17ffd15 	stw	r5,-12(fp)
+   if (addr->sa_family == AF_INET)
+ 803ff34:	e0bffe17 	ldw	r2,-8(fp)
+ 803ff38:	1080000b 	ldhu	r2,0(r2)
+ 803ff3c:	10bfffcc 	andi	r2,r2,65535
+ 803ff40:	10800098 	cmpnei	r2,r2,2
+ 803ff44:	10000c1e 	bne	r2,zero,803ff78 <inet_setport+0x58>
+   {
+      struct sockaddr_in *si = (struct sockaddr_in *)addr;
+ 803ff48:	e0bffe17 	ldw	r2,-8(fp)
+ 803ff4c:	e0bfff15 	stw	r2,-4(fp)
+      si->sin_port = htons(port);  
+ 803ff50:	e0bffd17 	ldw	r2,-12(fp)
+ 803ff54:	1005d23a 	srai	r2,r2,8
+ 803ff58:	10803fcc 	andi	r2,r2,255
+ 803ff5c:	1007883a 	mov	r3,r2
+ 803ff60:	e0bffd17 	ldw	r2,-12(fp)
+ 803ff64:	1004923a 	slli	r2,r2,8
+ 803ff68:	1884b03a 	or	r2,r3,r2
+ 803ff6c:	1007883a 	mov	r3,r2
+ 803ff70:	e0bfff17 	ldw	r2,-4(fp)
+ 803ff74:	10c0008d 	sth	r3,2(r2)
+      struct sockaddr_in6 *si = (struct sockaddr_in6 *)addr;
+      si->sin6_port = htons(port);
+   }
+#endif
+
+}
+ 803ff78:	0001883a 	nop
+ 803ff7c:	e037883a 	mov	sp,fp
+ 803ff80:	df000017 	ldw	fp,0(sp)
+ 803ff84:	dec00104 	addi	sp,sp,4
+ 803ff88:	f800283a 	ret
+
+0803ff8c <convert_ip>:
+ *Returns:
+ *
+ */
+
+unsigned long convert_ip(const char *p)
+{
+ 803ff8c:	defff904 	addi	sp,sp,-28
+ 803ff90:	df000615 	stw	fp,24(sp)
+ 803ff94:	df000604 	addi	fp,sp,24
+ 803ff98:	e13ffa15 	stw	r4,-24(fp)
+   const char *cp = p;
+ 803ff9c:	e0bffa17 	ldw	r2,-24(fp)
+ 803ffa0:	e0bfff15 	stw	r2,-4(fp)
+   unsigned long dw;
+   unsigned char *lpb = (unsigned char *) &dw;
+ 803ffa4:	e0bffb04 	addi	r2,fp,-20
+ 803ffa8:	e0bffc15 	stw	r2,-16(fp)
+   int n = 0;
+ 803ffac:	e03ffe15 	stw	zero,-8(fp)
+   unsigned short v = 0;
+ 803ffb0:	e03ffd8d 	sth	zero,-10(fp)
+   dw = 0;
+ 803ffb4:	e03ffb15 	stw	zero,-20(fp)
+   while(*cp)
+ 803ffb8:	00003106 	br	8040080 <convert_ip+0xf4>
+   {
+      if( *cp == '.')
+ 803ffbc:	e0bfff17 	ldw	r2,-4(fp)
+ 803ffc0:	10800003 	ldbu	r2,0(r2)
+ 803ffc4:	10803fcc 	andi	r2,r2,255
+ 803ffc8:	1080201c 	xori	r2,r2,128
+ 803ffcc:	10bfe004 	addi	r2,r2,-128
+ 803ffd0:	10800b98 	cmpnei	r2,r2,46
+ 803ffd4:	10000e1e 	bne	r2,zero,8040010 <convert_ip+0x84>
+      {
+         lpb[n] = (unsigned char) v;
+ 803ffd8:	e0bffe17 	ldw	r2,-8(fp)
+ 803ffdc:	e0fffc17 	ldw	r3,-16(fp)
+ 803ffe0:	1885883a 	add	r2,r3,r2
+ 803ffe4:	e0fffd8b 	ldhu	r3,-10(fp)
+ 803ffe8:	10c00005 	stb	r3,0(r2)
+         v = 0;
+ 803ffec:	e03ffd8d 	sth	zero,-10(fp)
+         n++;
+ 803fff0:	e0bffe17 	ldw	r2,-8(fp)
+ 803fff4:	10800044 	addi	r2,r2,1
+ 803fff8:	e0bffe15 	stw	r2,-8(fp)
+         if(n > 3)
+ 803fffc:	e0bffe17 	ldw	r2,-8(fp)
+ 8040000:	10800110 	cmplti	r2,r2,4
+ 8040004:	10001b1e 	bne	r2,zero,8040074 <convert_ip+0xe8>
+         {
+            return dw;
+ 8040008:	e0bffb17 	ldw	r2,-20(fp)
+ 804000c:	00002806 	br	80400b0 <convert_ip+0x124>
+         }
+      }
+      else if(((*cp >= '0') && (*cp <= '9')))
+ 8040010:	e0bfff17 	ldw	r2,-4(fp)
+ 8040014:	10800003 	ldbu	r2,0(r2)
+ 8040018:	10803fcc 	andi	r2,r2,255
+ 804001c:	1080201c 	xori	r2,r2,128
+ 8040020:	10bfe004 	addi	r2,r2,-128
+ 8040024:	10800c10 	cmplti	r2,r2,48
+ 8040028:	1000121e 	bne	r2,zero,8040074 <convert_ip+0xe8>
+ 804002c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040030:	10800003 	ldbu	r2,0(r2)
+ 8040034:	10803fcc 	andi	r2,r2,255
+ 8040038:	1080201c 	xori	r2,r2,128
+ 804003c:	10bfe004 	addi	r2,r2,-128
+ 8040040:	10800e88 	cmpgei	r2,r2,58
+ 8040044:	10000b1e 	bne	r2,zero,8040074 <convert_ip+0xe8>
+      {
+         v = (v * 10) + (*cp - '0');
+ 8040048:	e0bffd8b 	ldhu	r2,-10(fp)
+ 804004c:	108002a4 	muli	r2,r2,10
+ 8040050:	1007883a 	mov	r3,r2
+ 8040054:	e0bfff17 	ldw	r2,-4(fp)
+ 8040058:	10800003 	ldbu	r2,0(r2)
+ 804005c:	10803fcc 	andi	r2,r2,255
+ 8040060:	1080201c 	xori	r2,r2,128
+ 8040064:	10bfe004 	addi	r2,r2,-128
+ 8040068:	1885883a 	add	r2,r3,r2
+ 804006c:	10bff404 	addi	r2,r2,-48
+ 8040070:	e0bffd8d 	sth	r2,-10(fp)
+      }
+      cp++;
+ 8040074:	e0bfff17 	ldw	r2,-4(fp)
+ 8040078:	10800044 	addi	r2,r2,1
+ 804007c:	e0bfff15 	stw	r2,-4(fp)
+   while(*cp)
+ 8040080:	e0bfff17 	ldw	r2,-4(fp)
+ 8040084:	10800003 	ldbu	r2,0(r2)
+ 8040088:	10803fcc 	andi	r2,r2,255
+ 804008c:	1080201c 	xori	r2,r2,128
+ 8040090:	10bfe004 	addi	r2,r2,-128
+ 8040094:	103fc91e 	bne	r2,zero,803ffbc <convert_ip+0x30>
+   }
+   lpb[n] = (unsigned char) v;
+ 8040098:	e0bffe17 	ldw	r2,-8(fp)
+ 804009c:	e0fffc17 	ldw	r3,-16(fp)
+ 80400a0:	1885883a 	add	r2,r3,r2
+ 80400a4:	e0fffd8b 	ldhu	r3,-10(fp)
+ 80400a8:	10c00005 	stb	r3,0(r2)
+   return dw;
+ 80400ac:	e0bffb17 	ldw	r2,-20(fp)
+}  /* convert_ip() */
+ 80400b0:	e037883a 	mov	sp,fp
+ 80400b4:	df000017 	ldw	fp,0(sp)
+ 80400b8:	dec00104 	addi	sp,sp,4
+ 80400bc:	f800283a 	ret
+
+080400c0 <tcp_cksum>:
+ * RETURNS: 
+ */
+
+unshort
+tcp_cksum(struct ip * pip)
+{
+ 80400c0:	defff704 	addi	sp,sp,-36
+ 80400c4:	dfc00815 	stw	ra,32(sp)
+ 80400c8:	df000715 	stw	fp,28(sp)
+ 80400cc:	df000704 	addi	fp,sp,28
+ 80400d0:	e13ff915 	stw	r4,-28(fp)
+   unshort  oldsum;
+   unshort  newsum;
+   struct tcphdr * tp;
+
+#ifdef MUTE_WARNS    /* stifle compiler warnings */
+   tcpdata = (char *)NULL;
+ 80400d4:	e03ffe15 	stw	zero,-8(fp)
+#endif   /* MUTE_WARNS */
+
+   IN_PROFILER(PF_TSUM, PF_ENTRY);
+
+   oddchar = 0;
+ 80400d8:	e03ffdc5 	stb	zero,-9(fp)
+
+   iphlen = (unshort)ip_hlen(pip);
+ 80400dc:	e0bff917 	ldw	r2,-28(fp)
+ 80400e0:	10800003 	ldbu	r2,0(r2)
+ 80400e4:	10803fcc 	andi	r2,r2,255
+ 80400e8:	100490ba 	slli	r2,r2,2
+ 80400ec:	10800f0c 	andi	r2,r2,60
+ 80400f0:	e0bffc8d 	sth	r2,-14(fp)
+   tcplen = htons(pip->ip_len) - iphlen;
+ 80400f4:	e0bff917 	ldw	r2,-28(fp)
+ 80400f8:	1080008b 	ldhu	r2,2(r2)
+ 80400fc:	10bfffcc 	andi	r2,r2,65535
+ 8040100:	1004d23a 	srli	r2,r2,8
+ 8040104:	1007883a 	mov	r3,r2
+ 8040108:	e0bff917 	ldw	r2,-28(fp)
+ 804010c:	1080008b 	ldhu	r2,2(r2)
+ 8040110:	10bfffcc 	andi	r2,r2,65535
+ 8040114:	1004923a 	slli	r2,r2,8
+ 8040118:	1884b03a 	or	r2,r3,r2
+ 804011c:	1007883a 	mov	r3,r2
+ 8040120:	e0bffc8b 	ldhu	r2,-14(fp)
+ 8040124:	1885c83a 	sub	r2,r3,r2
+ 8040128:	e0bfff8d 	sth	r2,-2(fp)
+
+   tp = (struct tcphdr*)ip_data(pip);     /* get TCP header */
+ 804012c:	e0bff917 	ldw	r2,-28(fp)
+ 8040130:	10800003 	ldbu	r2,0(r2)
+ 8040134:	10803fcc 	andi	r2,r2,255
+ 8040138:	100490ba 	slli	r2,r2,2
+ 804013c:	10800f0c 	andi	r2,r2,60
+ 8040140:	e0fff917 	ldw	r3,-28(fp)
+ 8040144:	1885883a 	add	r2,r3,r2
+ 8040148:	e0bffb15 	stw	r2,-20(fp)
+   oldsum = tp->th_sum;       /* Save passed checksum */
+ 804014c:	e0bffb17 	ldw	r2,-20(fp)
+ 8040150:	1080040b 	ldhu	r2,16(r2)
+ 8040154:	e0bffa8d 	sth	r2,-22(fp)
+    * cannot overflow a 16 bit field) and put them in the cksum field. 
+    * We include the IP addresses by passing them to the lower level 
+    * fast sum routine. This results in their values being factored into 
+    * the sum and the cksum field contributes zero.
+    */
+   tp->th_sum = htons(tcplen + 6);
+ 8040158:	e0bfff8b 	ldhu	r2,-2(fp)
+ 804015c:	10800184 	addi	r2,r2,6
+ 8040160:	1005d23a 	srai	r2,r2,8
+ 8040164:	10803fcc 	andi	r2,r2,255
+ 8040168:	1007883a 	mov	r3,r2
+ 804016c:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8040170:	10800184 	addi	r2,r2,6
+ 8040174:	1004923a 	slli	r2,r2,8
+ 8040178:	1884b03a 	or	r2,r3,r2
+ 804017c:	1007883a 	mov	r3,r2
+ 8040180:	e0bffb17 	ldw	r2,-20(fp)
+ 8040184:	10c0040d 	sth	r3,16(r2)
+
+   /* zero pad odd sized packets for checksumming */
+   if (tcplen & 1)   
+ 8040188:	e0bfff8b 	ldhu	r2,-2(fp)
+ 804018c:	1080004c 	andi	r2,r2,1
+ 8040190:	10000e26 	beq	r2,zero,80401cc <tcp_cksum+0x10c>
+   {
+      tcpdata = ((char*)pip) + iphlen + tcplen;    /* end of packet */
+ 8040194:	e0fffc8b 	ldhu	r3,-14(fp)
+ 8040198:	e0bfff8b 	ldhu	r2,-2(fp)
+ 804019c:	1885883a 	add	r2,r3,r2
+ 80401a0:	e0fff917 	ldw	r3,-28(fp)
+ 80401a4:	1885883a 	add	r2,r3,r2
+ 80401a8:	e0bffe15 	stw	r2,-8(fp)
+      oddchar = *tcpdata;
+ 80401ac:	e0bffe17 	ldw	r2,-8(fp)
+ 80401b0:	10800003 	ldbu	r2,0(r2)
+ 80401b4:	e0bffdc5 	stb	r2,-9(fp)
+      *tcpdata = '\0';        /* zero out pad byte */
+ 80401b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80401bc:	10000005 	stb	zero,0(r2)
+      tcplen++;               /* bump length to pass to cksum() */
+ 80401c0:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80401c4:	10800044 	addi	r2,r2,1
+ 80401c8:	e0bfff8d 	sth	r2,-2(fp)
+
+   /* Pass a pointer to the beginning of the IP address area into the IP header
+    * the the low level sum routine. Add the size of these two IP addresses to
+    * the length, and convert the length to 16 bit words.
+    */
+   newsum = ~cksum(((char*)tp) - 8, (tcplen + 8) >> 1);
+ 80401cc:	e0bffb17 	ldw	r2,-20(fp)
+ 80401d0:	10fffe04 	addi	r3,r2,-8
+ 80401d4:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80401d8:	10800204 	addi	r2,r2,8
+ 80401dc:	1005d07a 	srai	r2,r2,1
+ 80401e0:	100b883a 	mov	r5,r2
+ 80401e4:	1809883a 	mov	r4,r3
+ 80401e8:	8026d7c0 	call	8026d7c <cksum>
+ 80401ec:	0084303a 	nor	r2,zero,r2
+ 80401f0:	e0bffd0d 	sth	r2,-12(fp)
+
+   /* If the old checksum is 0xffff, but the actual checksum is 0x0000,
+    * declare that to be a match.
+    */
+   if ((newsum != oldsum) && (oldsum == 0xffff) && (newsum == 0x0000))
+ 80401f4:	e0fffd0b 	ldhu	r3,-12(fp)
+ 80401f8:	e0bffa8b 	ldhu	r2,-22(fp)
+ 80401fc:	18800726 	beq	r3,r2,804021c <tcp_cksum+0x15c>
+ 8040200:	e0fffa8b 	ldhu	r3,-22(fp)
+ 8040204:	00bfffd4 	movui	r2,65535
+ 8040208:	1880041e 	bne	r3,r2,804021c <tcp_cksum+0x15c>
+ 804020c:	e0bffd0b 	ldhu	r2,-12(fp)
+ 8040210:	1000021e 	bne	r2,zero,804021c <tcp_cksum+0x15c>
+      newsum = 0xffff;
+ 8040214:	00bfffc4 	movi	r2,-1
+ 8040218:	e0bffd0d 	sth	r2,-12(fp)
+
+   /* restore what we clobbered */
+   tp->th_sum = oldsum;       /* put back passed checksum */
+ 804021c:	e0bffb17 	ldw	r2,-20(fp)
+ 8040220:	e0fffa8b 	ldhu	r3,-22(fp)
+ 8040224:	10c0040d 	sth	r3,16(r2)
+   if (oddchar)
+ 8040228:	e0bffdc7 	ldb	r2,-9(fp)
+ 804022c:	10000326 	beq	r2,zero,804023c <tcp_cksum+0x17c>
+      *tcpdata = oddchar;     /* restore odd byte if we zeroed it */
+ 8040230:	e0bffe17 	ldw	r2,-8(fp)
+ 8040234:	e0fffdc3 	ldbu	r3,-9(fp)
+ 8040238:	10c00005 	stb	r3,0(r2)
+
+   IN_PROFILER(PF_TSUM, PF_EXIT);
+
+   return newsum;
+ 804023c:	e0bffd0b 	ldhu	r2,-12(fp)
+}
+ 8040240:	e037883a 	mov	sp,fp
+ 8040244:	dfc00117 	ldw	ra,4(sp)
+ 8040248:	df000017 	ldw	fp,0(sp)
+ 804024c:	dec00204 	addi	sp,sp,8
+ 8040250:	f800283a 	ret
+
+08040254 <udp_open>:
+   ip_addr  fhost,      /* foreign host, 0L for any */
+   unshort  fsock,      /* foreign socket, 0 for any */
+   unshort  lsock,      /* local socket */
+   int (*handler)(PACKET, void*),   /* rcv upcall */
+   void *   data)       /* random data, returned on upcalls to aid demuxing */
+{
+ 8040254:	defff404 	addi	sp,sp,-48
+ 8040258:	dfc00b15 	stw	ra,44(sp)
+ 804025c:	df000a15 	stw	fp,40(sp)
+ 8040260:	df000a04 	addi	fp,sp,40
+ 8040264:	e13ffd15 	stw	r4,-12(fp)
+ 8040268:	2805883a 	mov	r2,r5
+ 804026c:	3007883a 	mov	r3,r6
+ 8040270:	e1fffa15 	stw	r7,-24(fp)
+ 8040274:	e0bffc0d 	sth	r2,-16(fp)
+ 8040278:	1805883a 	mov	r2,r3
+ 804027c:	e0bffb0d 	sth	r2,-20(fp)
+/*
+ * Altera Niche Stack Nios port modification:
+ * cast 'data' to remove build warning
+ */
+#ifdef   NPDEBUG
+   if (NDEBUG & INFOMSG)
+ 8040280:	d0a06617 	ldw	r2,-32360(gp)
+ 8040284:	1080010c 	andi	r2,r2,4
+ 8040288:	10001526 	beq	r2,zero,80402e0 <udp_open+0x8c>
+      dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n",
+ 804028c:	e0bffd17 	ldw	r2,-12(fp)
+ 8040290:	12003fcc 	andi	r8,r2,255
+    PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data);
+ 8040294:	e0bffd17 	ldw	r2,-12(fp)
+ 8040298:	1004d23a 	srli	r2,r2,8
+      dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n",
+ 804029c:	11803fcc 	andi	r6,r2,255
+    PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data);
+ 80402a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80402a4:	1004d43a 	srli	r2,r2,16
+      dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n",
+ 80402a8:	11c03fcc 	andi	r7,r2,255
+    PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data);
+ 80402ac:	e0bffd17 	ldw	r2,-12(fp)
+ 80402b0:	1004d63a 	srli	r2,r2,24
+      dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n",
+ 80402b4:	e0fffb0b 	ldhu	r3,-20(fp)
+ 80402b8:	e13ffc0b 	ldhu	r4,-16(fp)
+ 80402bc:	e1400217 	ldw	r5,8(fp)
+ 80402c0:	d9400315 	stw	r5,12(sp)
+ 80402c4:	d9000215 	stw	r4,8(sp)
+ 80402c8:	d8c00115 	stw	r3,4(sp)
+ 80402cc:	d8800015 	stw	r2,0(sp)
+ 80402d0:	400b883a 	mov	r5,r8
+ 80402d4:	01020174 	movhi	r4,2053
+ 80402d8:	212e0704 	addi	r4,r4,-18404
+ 80402dc:	8002c780 	call	8002c78 <printf>
+#endif
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 80402e0:	0009883a 	mov	r4,zero
+ 80402e4:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   ocon = NULL;
+ 80402e8:	e03ffe15 	stw	zero,-8(fp)
+   for (con = firstudp; con; con = con->u_next)
+ 80402ec:	d0a09e17 	ldw	r2,-32136(gp)
+ 80402f0:	e0bfff15 	stw	r2,-4(fp)
+ 80402f4:	00002006 	br	8040378 <udp_open+0x124>
+   {
+      ocon = con;       /* remember last con in list */
+ 80402f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80402fc:	e0bffe15 	stw	r2,-8(fp)
+      /* we only want to check UDP-over-IPv4 connections */
+      if (!(con->u_flags & UDPCF_V4))
+         continue;
+#endif
+
+      if (con->u_lport == lsock && con->u_fport == fsock &&
+ 8040300:	e0bfff17 	ldw	r2,-4(fp)
+ 8040304:	1080018b 	ldhu	r2,6(r2)
+ 8040308:	e0fffb0b 	ldhu	r3,-20(fp)
+ 804030c:	10bfffcc 	andi	r2,r2,65535
+ 8040310:	1880161e 	bne	r3,r2,804036c <udp_open+0x118>
+ 8040314:	e0bfff17 	ldw	r2,-4(fp)
+ 8040318:	1080020b 	ldhu	r2,8(r2)
+ 804031c:	e0fffc0b 	ldhu	r3,-16(fp)
+ 8040320:	10bfffcc 	andi	r2,r2,65535
+ 8040324:	1880111e 	bne	r3,r2,804036c <udp_open+0x118>
+          con->u_lhost == 0 && con->u_fhost == fhost)
+ 8040328:	e0bfff17 	ldw	r2,-4(fp)
+ 804032c:	10800317 	ldw	r2,12(r2)
+      if (con->u_lport == lsock && con->u_fport == fsock &&
+ 8040330:	10000e1e 	bne	r2,zero,804036c <udp_open+0x118>
+          con->u_lhost == 0 && con->u_fhost == fhost)
+ 8040334:	e0bfff17 	ldw	r2,-4(fp)
+ 8040338:	10800417 	ldw	r2,16(r2)
+ 804033c:	e0fffd17 	ldw	r3,-12(fp)
+ 8040340:	18800a1e 	bne	r3,r2,804036c <udp_open+0x118>
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (INFOMSG|PROTERR))
+ 8040344:	d0a06617 	ldw	r2,-32360(gp)
+ 8040348:	1080050c 	andi	r2,r2,20
+ 804034c:	10000326 	beq	r2,zero,804035c <udp_open+0x108>
+            dprintf("UDP: Connection already exists.\n");
+ 8040350:	01020174 	movhi	r4,2053
+ 8040354:	212e1604 	addi	r4,r4,-18344
+ 8040358:	8002d9c0 	call	8002d9c <puts>
+#endif
+         UNLOCK_NET_RESOURCE(NET_RESID);
+ 804035c:	0009883a 	mov	r4,zero
+ 8040360:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+         return(NULL);
+ 8040364:	0005883a 	mov	r2,zero
+ 8040368:	00003506 	br	8040440 <udp_open+0x1ec>
+   for (con = firstudp; con; con = con->u_next)
+ 804036c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040370:	10800017 	ldw	r2,0(r2)
+ 8040374:	e0bfff15 	stw	r2,-4(fp)
+ 8040378:	e0bfff17 	ldw	r2,-4(fp)
+ 804037c:	103fde1e 	bne	r2,zero,80402f8 <udp_open+0xa4>
+      }
+   }
+
+   con = (UDPCONN)UC_ALLOC(sizeof(struct udp_conn));
+ 8040380:	01000804 	movi	r4,32
+ 8040384:	802982c0 	call	802982c <npalloc>
+ 8040388:	e0bfff15 	stw	r2,-4(fp)
+   if (con == 0)
+ 804038c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040390:	10000a1e 	bne	r2,zero,80403bc <udp_open+0x168>
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & INFOMSG)
+ 8040394:	d0a06617 	ldw	r2,-32360(gp)
+ 8040398:	1080010c 	andi	r2,r2,4
+ 804039c:	10000326 	beq	r2,zero,80403ac <udp_open+0x158>
+         dprintf("UDP: Couldn't allocate conn storage.\n");
+ 80403a0:	01020174 	movhi	r4,2053
+ 80403a4:	212e1e04 	addi	r4,r4,-18312
+ 80403a8:	8002d9c0 	call	8002d9c <puts>
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 80403ac:	0009883a 	mov	r4,zero
+ 80403b0:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return(NULL);
+ 80403b4:	0005883a 	mov	r2,zero
+ 80403b8:	00002106 	br	8040440 <udp_open+0x1ec>
+   }
+
+   if (ocon)   /* ocon is end of list */
+ 80403bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80403c0:	10000426 	beq	r2,zero,80403d4 <udp_open+0x180>
+      ocon->u_next = con;  /* add new connection to end */
+ 80403c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80403c8:	e0ffff17 	ldw	r3,-4(fp)
+ 80403cc:	10c00015 	stw	r3,0(r2)
+ 80403d0:	00000206 	br	80403dc <udp_open+0x188>
+   else  /* no list, start one */
+      firstudp = con;
+ 80403d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80403d8:	d0a09e15 	stw	r2,-32136(gp)
+
+   con->u_next = 0;
+ 80403dc:	e0bfff17 	ldw	r2,-4(fp)
+ 80403e0:	10000015 	stw	zero,0(r2)
+
+   con->u_lport = lsock;      /* fill in connection info */
+ 80403e4:	e0bfff17 	ldw	r2,-4(fp)
+ 80403e8:	e0fffb0b 	ldhu	r3,-20(fp)
+ 80403ec:	10c0018d 	sth	r3,6(r2)
+   con->u_fport = fsock;
+ 80403f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80403f4:	e0fffc0b 	ldhu	r3,-16(fp)
+ 80403f8:	10c0020d 	sth	r3,8(r2)
+   con->u_lhost = 0;
+ 80403fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8040400:	10000315 	stw	zero,12(r2)
+   con->u_fhost = fhost;
+ 8040404:	e0bfff17 	ldw	r2,-4(fp)
+ 8040408:	e0fffd17 	ldw	r3,-12(fp)
+ 804040c:	10c00415 	stw	r3,16(r2)
+   con->u_rcv   = handler;
+ 8040410:	e0bfff17 	ldw	r2,-4(fp)
+ 8040414:	e0fffa17 	ldw	r3,-24(fp)
+ 8040418:	10c00515 	stw	r3,20(r2)
+   con->u_data  = data;
+ 804041c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040420:	e0c00217 	ldw	r3,8(fp)
+ 8040424:	10c00615 	stw	r3,24(r2)
+   con->u_flags = UDPCF_V4;
+ 8040428:	e0bfff17 	ldw	r2,-4(fp)
+ 804042c:	00c00044 	movi	r3,1
+ 8040430:	10c0010d 	sth	r3,4(r2)
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 8040434:	0009883a 	mov	r4,zero
+ 8040438:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+   return(con);
+ 804043c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8040440:	e037883a 	mov	sp,fp
+ 8040444:	dfc00117 	ldw	ra,4(sp)
+ 8040448:	df000017 	ldw	fp,0(sp)
+ 804044c:	dec00204 	addi	sp,sp,8
+ 8040450:	f800283a 	ret
+
+08040454 <udp_close>:
+ * RETURNS: void
+ */
+
+void
+udp_close(UDPCONN con)
+{
+ 8040454:	defffb04 	addi	sp,sp,-20
+ 8040458:	dfc00415 	stw	ra,16(sp)
+ 804045c:	df000315 	stw	fp,12(sp)
+ 8040460:	df000304 	addi	fp,sp,12
+ 8040464:	e13ffd15 	stw	r4,-12(fp)
+   UDPCONN pcon;
+   UDPCONN lcon;
+
+#ifdef NPDEBUG
+   if ((con == NULL) || (firstudp == NULL))
+ 8040468:	e0bffd17 	ldw	r2,-12(fp)
+ 804046c:	10000226 	beq	r2,zero,8040478 <udp_close+0x24>
+ 8040470:	d0a09e17 	ldw	r2,-32136(gp)
+ 8040474:	1000021e 	bne	r2,zero,8040480 <udp_close+0x2c>
+   {
+      dtrap(); /* bad programming! */
+ 8040478:	8028cd40 	call	8028cd4 <dtrap>
+      return;
+ 804047c:	00002606 	br	8040518 <udp_close+0xc4>
+   }
+#endif   /* NPDEBUG */
+
+   LOCK_NET_RESOURCE(NET_RESID);
+ 8040480:	0009883a 	mov	r4,zero
+ 8040484:	8028f380 	call	8028f38 <LOCK_NET_RESOURCE>
+   /* find connection in list and unlink it */
+   lcon = NULL;   /* clear ptr to last connection */
+ 8040488:	e03ffe15 	stw	zero,-8(fp)
+   for (pcon = firstudp; pcon; pcon = pcon->u_next)
+ 804048c:	d0a09e17 	ldw	r2,-32136(gp)
+ 8040490:	e0bfff15 	stw	r2,-4(fp)
+ 8040494:	00000806 	br	80404b8 <udp_close+0x64>
+   {
+      if (pcon == con)  /* found connection to delete */
+ 8040498:	e0ffff17 	ldw	r3,-4(fp)
+ 804049c:	e0bffd17 	ldw	r2,-12(fp)
+ 80404a0:	18800826 	beq	r3,r2,80404c4 <udp_close+0x70>
+      break;
+      lcon = pcon;   /* remember last connection */
+ 80404a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80404a8:	e0bffe15 	stw	r2,-8(fp)
+   for (pcon = firstudp; pcon; pcon = pcon->u_next)
+ 80404ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80404b0:	10800017 	ldw	r2,0(r2)
+ 80404b4:	e0bfff15 	stw	r2,-4(fp)
+ 80404b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80404bc:	103ff61e 	bne	r2,zero,8040498 <udp_close+0x44>
+ 80404c0:	00000106 	br	80404c8 <udp_close+0x74>
+      break;
+ 80404c4:	0001883a 	nop
+   }
+
+   if (!pcon)
+ 80404c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80404cc:	1000041e 	bne	r2,zero,80404e0 <udp_close+0x8c>
+   {
+      dtrap(); /* prog error - connenction not in list */
+ 80404d0:	8028cd40 	call	8028cd4 <dtrap>
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 80404d4:	0009883a 	mov	r4,zero
+ 80404d8:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+      return;
+ 80404dc:	00000e06 	br	8040518 <udp_close+0xc4>
+   }
+
+   if (lcon)   /* in con is not head of list */
+ 80404e0:	e0bffe17 	ldw	r2,-8(fp)
+ 80404e4:	10000526 	beq	r2,zero,80404fc <udp_close+0xa8>
+      lcon->u_next = con->u_next;   /* unlink */
+ 80404e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80404ec:	10c00017 	ldw	r3,0(r2)
+ 80404f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80404f4:	10c00015 	stw	r3,0(r2)
+ 80404f8:	00000306 	br	8040508 <udp_close+0xb4>
+   else
+      firstudp = con->u_next; /* remove from head */
+ 80404fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8040500:	10800017 	ldw	r2,0(r2)
+ 8040504:	d0a09e15 	stw	r2,-32136(gp)
+
+   UC_FREE(con);  /* free memory for structure */
+ 8040508:	e13ffd17 	ldw	r4,-12(fp)
+ 804050c:	80298600 	call	8029860 <npfree>
+   UNLOCK_NET_RESOURCE(NET_RESID);
+ 8040510:	0009883a 	mov	r4,zero
+ 8040514:	8028ff40 	call	8028ff4 <UNLOCK_NET_RESOURCE>
+}
+ 8040518:	e037883a 	mov	sp,fp
+ 804051c:	dfc00117 	ldw	ra,4(sp)
+ 8040520:	df000017 	ldw	fp,0(sp)
+ 8040524:	dec00204 	addi	sp,sp,8
+ 8040528:	f800283a 	ret
+
+0804052c <in_pcballoc>:
+ */
+
+int
+in_pcballoc(struct socket * so, 
+   struct inpcb * head)
+{
+ 804052c:	defffb04 	addi	sp,sp,-20
+ 8040530:	dfc00415 	stw	ra,16(sp)
+ 8040534:	df000315 	stw	fp,12(sp)
+ 8040538:	df000304 	addi	fp,sp,12
+ 804053c:	e13ffe15 	stw	r4,-8(fp)
+ 8040540:	e17ffd15 	stw	r5,-12(fp)
+   struct inpcb * inp;
+
+   inp = INP_ALLOC (sizeof (*inp));
+ 8040544:	01000b04 	movi	r4,44
+ 8040548:	802982c0 	call	802982c <npalloc>
+ 804054c:	e0bfff15 	stw	r2,-4(fp)
+   if (inp == 0)
+ 8040550:	e0bfff17 	ldw	r2,-4(fp)
+ 8040554:	1000021e 	bne	r2,zero,8040560 <in_pcballoc+0x34>
+      return ENOMEM;
+ 8040558:	00800304 	movi	r2,12
+ 804055c:	00001006 	br	80405a0 <in_pcballoc+0x74>
+   inp->inp_head = head;
+ 8040560:	e0bfff17 	ldw	r2,-4(fp)
+ 8040564:	e0fffd17 	ldw	r3,-12(fp)
+ 8040568:	10c00215 	stw	r3,8(r2)
+   inp->inp_socket = so;
+ 804056c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040570:	e0fffe17 	ldw	r3,-8(fp)
+ 8040574:	10c00815 	stw	r3,32(r2)
+
+   /* Set Path MTU to a very small default. It should get expanded 
+    * later by v4 or v6 specific SYN code. We don't want it zero 
+    * in case it doesn't get expanded promptly.
+    */
+   inp->inp_pmtu = 512;
+ 8040578:	e0bfff17 	ldw	r2,-4(fp)
+ 804057c:	00c08004 	movi	r3,512
+ 8040580:	10c00615 	stw	r3,24(r2)
+   insque(inp, head);
+ 8040584:	e17ffd17 	ldw	r5,-12(fp)
+ 8040588:	e13fff17 	ldw	r4,-4(fp)
+ 804058c:	802a3340 	call	802a334 <insque>
+   so->so_pcb = inp;
+ 8040590:	e0bffe17 	ldw	r2,-8(fp)
+ 8040594:	e0ffff17 	ldw	r3,-4(fp)
+ 8040598:	10c00115 	stw	r3,4(r2)
+   return 0;
+ 804059c:	0005883a 	mov	r2,zero
+}
+ 80405a0:	e037883a 	mov	sp,fp
+ 80405a4:	dfc00117 	ldw	ra,4(sp)
+ 80405a8:	df000017 	ldw	fp,0(sp)
+ 80405ac:	dec00204 	addi	sp,sp,8
+ 80405b0:	f800283a 	ret
+
+080405b4 <in_pcbdetach>:
+ * RETURNS: 
+ */
+
+void
+in_pcbdetach(struct inpcb * inp)
+{
+ 80405b4:	defffc04 	addi	sp,sp,-16
+ 80405b8:	dfc00315 	stw	ra,12(sp)
+ 80405bc:	df000215 	stw	fp,8(sp)
+ 80405c0:	df000204 	addi	fp,sp,8
+ 80405c4:	e13ffe15 	stw	r4,-8(fp)
+   struct socket *   so =  inp->inp_socket;
+ 80405c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80405cc:	10800817 	ldw	r2,32(r2)
+ 80405d0:	e0bfff15 	stw	r2,-4(fp)
+
+   so->so_pcb = 0;
+ 80405d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80405d8:	10000115 	stw	zero,4(r2)
+   sofree(so);
+ 80405dc:	e13fff17 	ldw	r4,-4(fp)
+ 80405e0:	802d3240 	call	802d324 <sofree>
+   remque(inp);
+ 80405e4:	e13ffe17 	ldw	r4,-8(fp)
+ 80405e8:	802a2c40 	call	802a2c4 <remque>
+   INP_FREE (inp);
+ 80405ec:	e13ffe17 	ldw	r4,-8(fp)
+ 80405f0:	80298600 	call	8029860 <npfree>
+}
+ 80405f4:	0001883a 	nop
+ 80405f8:	e037883a 	mov	sp,fp
+ 80405fc:	dfc00117 	ldw	ra,4(sp)
+ 8040600:	df000017 	ldw	fp,0(sp)
+ 8040604:	dec00204 	addi	sp,sp,8
+ 8040608:	f800283a 	ret
+
+0804060c <in_pcbbind>:
+
+int
+in_pcbbind(
+   struct inpcb * inp,
+   struct mbuf *  nam)
+{
+ 804060c:	defff504 	addi	sp,sp,-44
+ 8040610:	dfc00a15 	stw	ra,40(sp)
+ 8040614:	df000915 	stw	fp,36(sp)
+ 8040618:	df000904 	addi	fp,sp,36
+ 804061c:	e13ffa15 	stw	r4,-24(fp)
+ 8040620:	e17ff915 	stw	r5,-28(fp)
+   struct socket *   so =  inp->inp_socket;
+ 8040624:	e0bffa17 	ldw	r2,-24(fp)
+ 8040628:	10800817 	ldw	r2,32(r2)
+ 804062c:	e0bffd15 	stw	r2,-12(fp)
+   struct inpcb * head  =  inp->inp_head;
+ 8040630:	e0bffa17 	ldw	r2,-24(fp)
+ 8040634:	10800217 	ldw	r2,8(r2)
+ 8040638:	e0bffc15 	stw	r2,-16(fp)
+   struct sockaddr_in * sin;
+   u_short  lport =  0;
+ 804063c:	e03fff8d 	sth	zero,-2(fp)
+
+
+   if (inp->inp_lport || inp->inp_laddr.s_addr != INADDR_ANY)
+ 8040640:	e0bffa17 	ldw	r2,-24(fp)
+ 8040644:	1080078b 	ldhu	r2,30(r2)
+ 8040648:	10bfffcc 	andi	r2,r2,65535
+ 804064c:	1000031e 	bne	r2,zero,804065c <in_pcbbind+0x50>
+ 8040650:	e0bffa17 	ldw	r2,-24(fp)
+ 8040654:	10800417 	ldw	r2,16(r2)
+ 8040658:	10000226 	beq	r2,zero,8040664 <in_pcbbind+0x58>
+      return (EINVAL);
+ 804065c:	00800584 	movi	r2,22
+ 8040660:	00006906 	br	8040808 <in_pcbbind+0x1fc>
+   if (nam == 0)
+ 8040664:	e0bff917 	ldw	r2,-28(fp)
+ 8040668:	10003926 	beq	r2,zero,8040750 <in_pcbbind+0x144>
+      goto noname;
+   sin = mtod(nam, struct sockaddr_in *);
+ 804066c:	e0bff917 	ldw	r2,-28(fp)
+ 8040670:	10800317 	ldw	r2,12(r2)
+ 8040674:	e0bffb15 	stw	r2,-20(fp)
+   /*
+    * removed test here for "if (nam->m_len != sizeof (*sin))"
+    * since it really complicatges supporting dual IPv4/v6, and 
+    * the 2.0 stack now checks this in t_bind(). -JB-
+    */
+   if (sin->sin_addr.s_addr != INADDR_ANY) 
+ 8040678:	e0bffb17 	ldw	r2,-20(fp)
+ 804067c:	10800117 	ldw	r2,4(r2)
+ 8040680:	10000a26 	beq	r2,zero,80406ac <in_pcbbind+0xa0>
+   {
+      if (ip_mymach(sin->sin_addr.s_addr) != sin->sin_addr.s_addr)
+ 8040684:	e0bffb17 	ldw	r2,-20(fp)
+ 8040688:	10800117 	ldw	r2,4(r2)
+ 804068c:	1009883a 	mov	r4,r2
+ 8040690:	803b0280 	call	803b028 <ip_mymach>
+ 8040694:	1007883a 	mov	r3,r2
+ 8040698:	e0bffb17 	ldw	r2,-20(fp)
+ 804069c:	10800117 	ldw	r2,4(r2)
+ 80406a0:	18800226 	beq	r3,r2,80406ac <in_pcbbind+0xa0>
+      return (EADDRNOTAVAIL);
+ 80406a4:	00801f44 	movi	r2,125
+ 80406a8:	00005706 	br	8040808 <in_pcbbind+0x1fc>
+   }
+   lport = sin->sin_port;
+ 80406ac:	e0bffb17 	ldw	r2,-20(fp)
+ 80406b0:	1080008b 	ldhu	r2,2(r2)
+ 80406b4:	e0bfff8d 	sth	r2,-2(fp)
+   if (lport) 
+ 80406b8:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80406bc:	10001f26 	beq	r2,zero,804073c <in_pcbbind+0x130>
+   {
+      int   wild  =  0;
+ 80406c0:	e03ffe15 	stw	zero,-8(fp)
+
+      /* even GROSSER, but this is the Internet */
+      if ((so->so_options & SO_REUSEADDR) == 0 &&
+ 80406c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80406c8:	10800417 	ldw	r2,16(r2)
+ 80406cc:	1080010c 	andi	r2,r2,4
+ 80406d0:	10000c1e 	bne	r2,zero,8040704 <in_pcbbind+0xf8>
+          ((so->so_proto->pr_flags & PR_CONNREQUIRED) == 0 ||
+ 80406d4:	e0bffd17 	ldw	r2,-12(fp)
+ 80406d8:	10800217 	ldw	r2,8(r2)
+ 80406dc:	1080010b 	ldhu	r2,4(r2)
+ 80406e0:	10bfffcc 	andi	r2,r2,65535
+ 80406e4:	1080010c 	andi	r2,r2,4
+      if ((so->so_options & SO_REUSEADDR) == 0 &&
+ 80406e8:	10000426 	beq	r2,zero,80406fc <in_pcbbind+0xf0>
+          (so->so_options & SO_ACCEPTCONN) == 0))
+ 80406ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80406f0:	10800417 	ldw	r2,16(r2)
+ 80406f4:	1080008c 	andi	r2,r2,2
+          ((so->so_proto->pr_flags & PR_CONNREQUIRED) == 0 ||
+ 80406f8:	1000021e 	bne	r2,zero,8040704 <in_pcbbind+0xf8>
+      {
+         wild = INPLOOKUP_WILDCARD;
+ 80406fc:	00800044 	movi	r2,1
+ 8040700:	e0bffe15 	stw	r2,-8(fp)
+      }
+      if (in_pcblookup(head,
+ 8040704:	e0bffb17 	ldw	r2,-20(fp)
+ 8040708:	11000117 	ldw	r4,4(r2)
+ 804070c:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8040710:	e0fffe17 	ldw	r3,-8(fp)
+ 8040714:	d8c00115 	stw	r3,4(sp)
+ 8040718:	d8800015 	stw	r2,0(sp)
+ 804071c:	200f883a 	mov	r7,r4
+ 8040720:	000d883a 	mov	r6,zero
+ 8040724:	000b883a 	mov	r5,zero
+ 8040728:	e13ffc17 	ldw	r4,-16(fp)
+ 804072c:	8040b600 	call	8040b60 <in_pcblookup>
+ 8040730:	10000226 	beq	r2,zero,804073c <in_pcbbind+0x130>
+          0L, 0, sin->sin_addr.s_addr, lport, wild))
+      {
+         return (EADDRINUSE);
+ 8040734:	00801c04 	movi	r2,112
+ 8040738:	00003306 	br	8040808 <in_pcbbind+0x1fc>
+      }
+   }
+   inp->inp_laddr = sin->sin_addr;
+ 804073c:	e0bffa17 	ldw	r2,-24(fp)
+ 8040740:	e0fffb17 	ldw	r3,-20(fp)
+ 8040744:	18c00117 	ldw	r3,4(r3)
+ 8040748:	10c00415 	stw	r3,16(r2)
+ 804074c:	00000106 	br	8040754 <in_pcbbind+0x148>
+      goto noname;
+ 8040750:	0001883a 	nop
+noname:
+   if (lport == 0)
+ 8040754:	e0bfff8b 	ldhu	r2,-2(fp)
+ 8040758:	1000271e 	bne	r2,zero,80407f8 <in_pcbbind+0x1ec>
+   {
+      do 
+      {
+         if (head->inp_lport++ < IPPORT_RESERVED ||
+ 804075c:	e0bffc17 	ldw	r2,-16(fp)
+ 8040760:	1080078b 	ldhu	r2,30(r2)
+ 8040764:	10c00044 	addi	r3,r2,1
+ 8040768:	1809883a 	mov	r4,r3
+ 804076c:	e0fffc17 	ldw	r3,-16(fp)
+ 8040770:	1900078d 	sth	r4,30(r3)
+ 8040774:	10bfffcc 	andi	r2,r2,65535
+ 8040778:	10810030 	cmpltui	r2,r2,1024
+ 804077c:	1000051e 	bne	r2,zero,8040794 <in_pcbbind+0x188>
+             head->inp_lport > IPPORT_USERRESERVED)
+ 8040780:	e0bffc17 	ldw	r2,-16(fp)
+ 8040784:	1080078b 	ldhu	r2,30(r2)
+         if (head->inp_lport++ < IPPORT_RESERVED ||
+ 8040788:	10bfffcc 	andi	r2,r2,65535
+ 804078c:	1084e270 	cmpltui	r2,r2,5001
+ 8040790:	1000031e 	bne	r2,zero,80407a0 <in_pcbbind+0x194>
+         {
+            head->inp_lport = IPPORT_RESERVED;
+ 8040794:	e0bffc17 	ldw	r2,-16(fp)
+ 8040798:	00c10004 	movi	r3,1024
+ 804079c:	10c0078d 	sth	r3,30(r2)
+         }
+         lport = htons(head->inp_lport);
+ 80407a0:	e0bffc17 	ldw	r2,-16(fp)
+ 80407a4:	1080078b 	ldhu	r2,30(r2)
+ 80407a8:	10bfffcc 	andi	r2,r2,65535
+ 80407ac:	1004d23a 	srli	r2,r2,8
+ 80407b0:	1007883a 	mov	r3,r2
+ 80407b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80407b8:	1080078b 	ldhu	r2,30(r2)
+ 80407bc:	10bfffcc 	andi	r2,r2,65535
+ 80407c0:	1004923a 	slli	r2,r2,8
+ 80407c4:	1884b03a 	or	r2,r3,r2
+ 80407c8:	e0bfff8d 	sth	r2,-2(fp)
+      } while(in_pcblookup(head, 0L, 0, inp->inp_laddr.s_addr, lport, 0));
+ 80407cc:	e0bffa17 	ldw	r2,-24(fp)
+ 80407d0:	10c00417 	ldw	r3,16(r2)
+ 80407d4:	e0bfff8b 	ldhu	r2,-2(fp)
+ 80407d8:	d8000115 	stw	zero,4(sp)
+ 80407dc:	d8800015 	stw	r2,0(sp)
+ 80407e0:	180f883a 	mov	r7,r3
+ 80407e4:	000d883a 	mov	r6,zero
+ 80407e8:	000b883a 	mov	r5,zero
+ 80407ec:	e13ffc17 	ldw	r4,-16(fp)
+ 80407f0:	8040b600 	call	8040b60 <in_pcblookup>
+ 80407f4:	103fd91e 	bne	r2,zero,804075c <in_pcbbind+0x150>
+   }
+   inp->inp_lport = lport;
+ 80407f8:	e0bffa17 	ldw	r2,-24(fp)
+ 80407fc:	e0ffff8b 	ldhu	r3,-2(fp)
+ 8040800:	10c0078d 	sth	r3,30(r2)
+   return (0);
+ 8040804:	0005883a 	mov	r2,zero
+}
+ 8040808:	e037883a 	mov	sp,fp
+ 804080c:	dfc00117 	ldw	ra,4(sp)
+ 8040810:	df000017 	ldw	fp,0(sp)
+ 8040814:	dec00204 	addi	sp,sp,8
+ 8040818:	f800283a 	ret
+
+0804081c <in_pcbconnect>:
+ */
+
+int
+in_pcbconnect(struct inpcb * inp, 
+   struct mbuf *  nam)
+{
+ 804081c:	defff604 	addi	sp,sp,-40
+ 8040820:	dfc00915 	stw	ra,36(sp)
+ 8040824:	df000815 	stw	fp,32(sp)
+ 8040828:	df000804 	addi	fp,sp,32
+ 804082c:	e13ffb15 	stw	r4,-20(fp)
+ 8040830:	e17ffa15 	stw	r5,-24(fp)
+   unsigned long ifaddr;
+   struct sockaddr_in * sin   =  mtod(nam,   struct sockaddr_in *);
+ 8040834:	e0bffa17 	ldw	r2,-24(fp)
+ 8040838:	10800317 	ldw	r2,12(r2)
+ 804083c:	e0bffe15 	stw	r2,-8(fp)
+
+   if (nam->m_len < sizeof (*sin))
+ 8040840:	e0bffa17 	ldw	r2,-24(fp)
+ 8040844:	10800217 	ldw	r2,8(r2)
+ 8040848:	10800428 	cmpgeui	r2,r2,16
+ 804084c:	1000021e 	bne	r2,zero,8040858 <in_pcbconnect+0x3c>
+      return (EINVAL);
+ 8040850:	00800584 	movi	r2,22
+ 8040854:	00006406 	br	80409e8 <in_pcbconnect+0x1cc>
+   if (sin->sin_family != AF_INET)
+ 8040858:	e0bffe17 	ldw	r2,-8(fp)
+ 804085c:	1080000b 	ldhu	r2,0(r2)
+ 8040860:	10bfffcc 	andi	r2,r2,65535
+ 8040864:	10a0001c 	xori	r2,r2,32768
+ 8040868:	10a00004 	addi	r2,r2,-32768
+ 804086c:	108000a0 	cmpeqi	r2,r2,2
+ 8040870:	1000021e 	bne	r2,zero,804087c <in_pcbconnect+0x60>
+      return (EAFNOSUPPORT);
+ 8040874:	00801a84 	movi	r2,106
+ 8040878:	00005b06 	br	80409e8 <in_pcbconnect+0x1cc>
+   if (sin->sin_port == 0)
+ 804087c:	e0bffe17 	ldw	r2,-8(fp)
+ 8040880:	1080008b 	ldhu	r2,2(r2)
+ 8040884:	10bfffcc 	andi	r2,r2,65535
+ 8040888:	1000021e 	bne	r2,zero,8040894 <in_pcbconnect+0x78>
+      return (EADDRNOTAVAIL);
+ 804088c:	00801f44 	movi	r2,125
+ 8040890:	00005506 	br	80409e8 <in_pcbconnect+0x1cc>
+    * use the primary local address.
+    * If the supplied address is INADDR_BROADCAST,
+    * and the primary interface supports broadcast,
+    * choose the broadcast address for that interface.
+    */
+   if (sin->sin_addr.s_addr == INADDR_ANY)
+ 8040894:	e0bffe17 	ldw	r2,-8(fp)
+ 8040898:	10800117 	ldw	r2,4(r2)
+ 804089c:	10000d1e 	bne	r2,zero,80408d4 <in_pcbconnect+0xb8>
+   {
+      if (inp && inp->ifp)
+ 80408a0:	e0bffb17 	ldw	r2,-20(fp)
+ 80408a4:	10000926 	beq	r2,zero,80408cc <in_pcbconnect+0xb0>
+ 80408a8:	e0bffb17 	ldw	r2,-20(fp)
+ 80408ac:	10800a17 	ldw	r2,40(r2)
+ 80408b0:	10000626 	beq	r2,zero,80408cc <in_pcbconnect+0xb0>
+         sin->sin_addr.s_addr = inp->ifp->n_ipaddr;
+ 80408b4:	e0bffb17 	ldw	r2,-20(fp)
+ 80408b8:	10800a17 	ldw	r2,40(r2)
+ 80408bc:	10c00a17 	ldw	r3,40(r2)
+ 80408c0:	e0bffe17 	ldw	r2,-8(fp)
+ 80408c4:	10c00115 	stw	r3,4(r2)
+ 80408c8:	00000806 	br	80408ec <in_pcbconnect+0xd0>
+      else
+         return (EADDRNOTAVAIL);
+ 80408cc:	00801f44 	movi	r2,125
+ 80408d0:	00004506 	br	80409e8 <in_pcbconnect+0x1cc>
+   }
+   else if (sin->sin_addr.s_addr == INADDR_BROADCAST)
+ 80408d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80408d8:	10800117 	ldw	r2,4(r2)
+ 80408dc:	10bfffd8 	cmpnei	r2,r2,-1
+ 80408e0:	1000021e 	bne	r2,zero,80408ec <in_pcbconnect+0xd0>
+      return (EADDRNOTAVAIL);
+ 80408e4:	00801f44 	movi	r2,125
+ 80408e8:	00003f06 	br	80409e8 <in_pcbconnect+0x1cc>
+
+
+   if (inp->inp_laddr.s_addr == INADDR_ANY) 
+ 80408ec:	e0bffb17 	ldw	r2,-20(fp)
+ 80408f0:	10800417 	ldw	r2,16(r2)
+ 80408f4:	10000f1e 	bne	r2,zero,8040934 <in_pcbconnect+0x118>
+   {
+#ifdef MULTI_HOMED
+      ip_addr hop1;     /* dummy for pass to iproute() */
+      NET npnet;     /* the netport iface we can send on */
+      /* call netport stack's IP routing */
+      npnet = iproute(sin->sin_addr.s_addr, &hop1);
+ 80408f8:	e0bffe17 	ldw	r2,-8(fp)
+ 80408fc:	10800117 	ldw	r2,4(r2)
+ 8040900:	e0fffc04 	addi	r3,fp,-16
+ 8040904:	180b883a 	mov	r5,r3
+ 8040908:	1009883a 	mov	r4,r2
+ 804090c:	803b3700 	call	803b370 <iproute>
+ 8040910:	e0bffd15 	stw	r2,-12(fp)
+      if (!npnet)
+ 8040914:	e0bffd17 	ldw	r2,-12(fp)
+ 8040918:	1000021e 	bne	r2,zero,8040924 <in_pcbconnect+0x108>
+         return EADDRNOTAVAIL;
+ 804091c:	00801f44 	movi	r2,125
+ 8040920:	00003106 	br	80409e8 <in_pcbconnect+0x1cc>
+      ifaddr = npnet->n_ipaddr;  /* local address for this host */
+ 8040924:	e0bffd17 	ldw	r2,-12(fp)
+ 8040928:	10800a17 	ldw	r2,40(r2)
+ 804092c:	e0bfff15 	stw	r2,-4(fp)
+ 8040930:	00000306 	br	8040940 <in_pcbconnect+0x124>
+#else    /* not netport MULTI_HOMED, use 0th (only) iface */
+      ifaddr = nets[0]->n_ipaddr;
+#endif   /* MULTI_HOMED */
+   }
+   else  /* inp->inp_laddr.s_addr != INADDR_ANY */
+      ifaddr = inp->inp_laddr.s_addr;  /* use address passed */
+ 8040934:	e0bffb17 	ldw	r2,-20(fp)
+ 8040938:	10800417 	ldw	r2,16(r2)
+ 804093c:	e0bfff15 	stw	r2,-4(fp)
+
+   if (in_pcblookup(inp->inp_head,
+ 8040940:	e0bffb17 	ldw	r2,-20(fp)
+ 8040944:	10c00217 	ldw	r3,8(r2)
+ 8040948:	e0bffe17 	ldw	r2,-8(fp)
+ 804094c:	11000117 	ldw	r4,4(r2)
+       sin->sin_addr.s_addr,
+       sin->sin_port,
+ 8040950:	e0bffe17 	ldw	r2,-8(fp)
+ 8040954:	1080008b 	ldhu	r2,2(r2)
+   if (in_pcblookup(inp->inp_head,
+ 8040958:	117fffcc 	andi	r5,r2,65535
+       ifaddr,
+       inp->inp_lport,
+ 804095c:	e0bffb17 	ldw	r2,-20(fp)
+ 8040960:	1080078b 	ldhu	r2,30(r2)
+   if (in_pcblookup(inp->inp_head,
+ 8040964:	10bfffcc 	andi	r2,r2,65535
+ 8040968:	d8000115 	stw	zero,4(sp)
+ 804096c:	d8800015 	stw	r2,0(sp)
+ 8040970:	e1ffff17 	ldw	r7,-4(fp)
+ 8040974:	280d883a 	mov	r6,r5
+ 8040978:	200b883a 	mov	r5,r4
+ 804097c:	1809883a 	mov	r4,r3
+ 8040980:	8040b600 	call	8040b60 <in_pcblookup>
+ 8040984:	10000226 	beq	r2,zero,8040990 <in_pcbconnect+0x174>
+       0))
+   {
+      return (EADDRINUSE);
+ 8040988:	00801c04 	movi	r2,112
+ 804098c:	00001606 	br	80409e8 <in_pcbconnect+0x1cc>
+   }
+   if (inp->inp_laddr.s_addr == INADDR_ANY) 
+ 8040990:	e0bffb17 	ldw	r2,-20(fp)
+ 8040994:	10800417 	ldw	r2,16(r2)
+ 8040998:	10000a1e 	bne	r2,zero,80409c4 <in_pcbconnect+0x1a8>
+   {
+      if (inp->inp_lport == 0)
+ 804099c:	e0bffb17 	ldw	r2,-20(fp)
+ 80409a0:	1080078b 	ldhu	r2,30(r2)
+ 80409a4:	10bfffcc 	andi	r2,r2,65535
+ 80409a8:	1000031e 	bne	r2,zero,80409b8 <in_pcbconnect+0x19c>
+         (void)in_pcbbind(inp, (struct mbuf *)0);
+ 80409ac:	000b883a 	mov	r5,zero
+ 80409b0:	e13ffb17 	ldw	r4,-20(fp)
+ 80409b4:	804060c0 	call	804060c <in_pcbbind>
+      inp->inp_laddr.s_addr = ifaddr;
+ 80409b8:	e0bffb17 	ldw	r2,-20(fp)
+ 80409bc:	e0ffff17 	ldw	r3,-4(fp)
+ 80409c0:	10c00415 	stw	r3,16(r2)
+   }
+   inp->inp_faddr = sin->sin_addr;
+ 80409c4:	e0bffb17 	ldw	r2,-20(fp)
+ 80409c8:	e0fffe17 	ldw	r3,-8(fp)
+ 80409cc:	18c00117 	ldw	r3,4(r3)
+ 80409d0:	10c00315 	stw	r3,12(r2)
+   inp->inp_fport = sin->sin_port;
+ 80409d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80409d8:	10c0008b 	ldhu	r3,2(r2)
+ 80409dc:	e0bffb17 	ldw	r2,-20(fp)
+ 80409e0:	10c0070d 	sth	r3,28(r2)
+   return 0;
+ 80409e4:	0005883a 	mov	r2,zero
+}
+ 80409e8:	e037883a 	mov	sp,fp
+ 80409ec:	dfc00117 	ldw	ra,4(sp)
+ 80409f0:	df000017 	ldw	fp,0(sp)
+ 80409f4:	dec00204 	addi	sp,sp,8
+ 80409f8:	f800283a 	ret
+
+080409fc <in_pcbdisconnect>:
+ * RETURNS: 
+ */
+
+void
+in_pcbdisconnect(struct inpcb * inp)
+{
+ 80409fc:	defffd04 	addi	sp,sp,-12
+ 8040a00:	dfc00215 	stw	ra,8(sp)
+ 8040a04:	df000115 	stw	fp,4(sp)
+ 8040a08:	df000104 	addi	fp,sp,4
+ 8040a0c:	e13fff15 	stw	r4,-4(fp)
+
+   inp->inp_faddr.s_addr = INADDR_ANY;
+ 8040a10:	e0bfff17 	ldw	r2,-4(fp)
+ 8040a14:	10000315 	stw	zero,12(r2)
+   inp->inp_fport = 0;
+ 8040a18:	e0bfff17 	ldw	r2,-4(fp)
+ 8040a1c:	1000070d 	sth	zero,28(r2)
+   if (inp->inp_socket->so_state & SS_NOFDREF)
+ 8040a20:	e0bfff17 	ldw	r2,-4(fp)
+ 8040a24:	10800817 	ldw	r2,32(r2)
+ 8040a28:	1080088b 	ldhu	r2,34(r2)
+ 8040a2c:	10bfffcc 	andi	r2,r2,65535
+ 8040a30:	1080004c 	andi	r2,r2,1
+ 8040a34:	10000226 	beq	r2,zero,8040a40 <in_pcbdisconnect+0x44>
+      in_pcbdetach (inp);
+ 8040a38:	e13fff17 	ldw	r4,-4(fp)
+ 8040a3c:	80405b40 	call	80405b4 <in_pcbdetach>
+}
+ 8040a40:	0001883a 	nop
+ 8040a44:	e037883a 	mov	sp,fp
+ 8040a48:	dfc00117 	ldw	ra,4(sp)
+ 8040a4c:	df000017 	ldw	fp,0(sp)
+ 8040a50:	dec00204 	addi	sp,sp,8
+ 8040a54:	f800283a 	ret
+
+08040a58 <in_setsockaddr>:
+ */
+
+void
+in_setsockaddr(struct inpcb * inp, 
+   struct mbuf *  nam)
+{
+ 8040a58:	defffb04 	addi	sp,sp,-20
+ 8040a5c:	dfc00415 	stw	ra,16(sp)
+ 8040a60:	df000315 	stw	fp,12(sp)
+ 8040a64:	df000304 	addi	fp,sp,12
+ 8040a68:	e13ffe15 	stw	r4,-8(fp)
+ 8040a6c:	e17ffd15 	stw	r5,-12(fp)
+   struct sockaddr_in * sin;
+
+   nam->m_len = sizeof (*sin);
+ 8040a70:	e0bffd17 	ldw	r2,-12(fp)
+ 8040a74:	00c00404 	movi	r3,16
+ 8040a78:	10c00215 	stw	r3,8(r2)
+   sin = mtod(nam, struct sockaddr_in *);
+ 8040a7c:	e0bffd17 	ldw	r2,-12(fp)
+ 8040a80:	10800317 	ldw	r2,12(r2)
+ 8040a84:	e0bfff15 	stw	r2,-4(fp)
+   MEMSET(sin, 0, sizeof (*sin));
+ 8040a88:	01800404 	movi	r6,16
+ 8040a8c:	000b883a 	mov	r5,zero
+ 8040a90:	e13fff17 	ldw	r4,-4(fp)
+ 8040a94:	80088e40 	call	80088e4 <memset>
+   sin->sin_family = AF_INET;
+ 8040a98:	e0bfff17 	ldw	r2,-4(fp)
+ 8040a9c:	00c00084 	movi	r3,2
+ 8040aa0:	10c0000d 	sth	r3,0(r2)
+   sin->sin_port = inp->inp_lport;
+ 8040aa4:	e0bffe17 	ldw	r2,-8(fp)
+ 8040aa8:	10c0078b 	ldhu	r3,30(r2)
+ 8040aac:	e0bfff17 	ldw	r2,-4(fp)
+ 8040ab0:	10c0008d 	sth	r3,2(r2)
+   sin->sin_addr = inp->inp_laddr;
+ 8040ab4:	e0bfff17 	ldw	r2,-4(fp)
+ 8040ab8:	e0fffe17 	ldw	r3,-8(fp)
+ 8040abc:	18c00417 	ldw	r3,16(r3)
+ 8040ac0:	10c00115 	stw	r3,4(r2)
+}
+ 8040ac4:	0001883a 	nop
+ 8040ac8:	e037883a 	mov	sp,fp
+ 8040acc:	dfc00117 	ldw	ra,4(sp)
+ 8040ad0:	df000017 	ldw	fp,0(sp)
+ 8040ad4:	dec00204 	addi	sp,sp,8
+ 8040ad8:	f800283a 	ret
+
+08040adc <in_setpeeraddr>:
+
+void
+in_setpeeraddr(
+   struct inpcb * inp,
+   struct mbuf *  nam)
+{
+ 8040adc:	defffb04 	addi	sp,sp,-20
+ 8040ae0:	dfc00415 	stw	ra,16(sp)
+ 8040ae4:	df000315 	stw	fp,12(sp)
+ 8040ae8:	df000304 	addi	fp,sp,12
+ 8040aec:	e13ffe15 	stw	r4,-8(fp)
+ 8040af0:	e17ffd15 	stw	r5,-12(fp)
+   struct sockaddr_in * sin;
+
+   nam->m_len = sizeof (*sin);
+ 8040af4:	e0bffd17 	ldw	r2,-12(fp)
+ 8040af8:	00c00404 	movi	r3,16
+ 8040afc:	10c00215 	stw	r3,8(r2)
+   sin = mtod(nam, struct sockaddr_in *);
+ 8040b00:	e0bffd17 	ldw	r2,-12(fp)
+ 8040b04:	10800317 	ldw	r2,12(r2)
+ 8040b08:	e0bfff15 	stw	r2,-4(fp)
+   MEMSET(sin, 0, sizeof (*sin));
+ 8040b0c:	01800404 	movi	r6,16
+ 8040b10:	000b883a 	mov	r5,zero
+ 8040b14:	e13fff17 	ldw	r4,-4(fp)
+ 8040b18:	80088e40 	call	80088e4 <memset>
+   sin->sin_family = AF_INET;
+ 8040b1c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040b20:	00c00084 	movi	r3,2
+ 8040b24:	10c0000d 	sth	r3,0(r2)
+   sin->sin_port = inp->inp_fport;
+ 8040b28:	e0bffe17 	ldw	r2,-8(fp)
+ 8040b2c:	10c0070b 	ldhu	r3,28(r2)
+ 8040b30:	e0bfff17 	ldw	r2,-4(fp)
+ 8040b34:	10c0008d 	sth	r3,2(r2)
+   sin->sin_addr = inp->inp_faddr;
+ 8040b38:	e0bfff17 	ldw	r2,-4(fp)
+ 8040b3c:	e0fffe17 	ldw	r3,-8(fp)
+ 8040b40:	18c00317 	ldw	r3,12(r3)
+ 8040b44:	10c00115 	stw	r3,4(r2)
+}
+ 8040b48:	0001883a 	nop
+ 8040b4c:	e037883a 	mov	sp,fp
+ 8040b50:	dfc00117 	ldw	ra,4(sp)
+ 8040b54:	df000017 	ldw	fp,0(sp)
+ 8040b58:	dec00204 	addi	sp,sp,8
+ 8040b5c:	f800283a 	ret
+
+08040b60 <in_pcblookup>:
+   u_long   faddr, 
+   unshort  xfport,
+   u_long   laddr,
+   unshort  xlport,
+   int   flags)
+{
+ 8040b60:	defff504 	addi	sp,sp,-44
+ 8040b64:	df000a15 	stw	fp,40(sp)
+ 8040b68:	df000a04 	addi	fp,sp,40
+ 8040b6c:	e13ffa15 	stw	r4,-24(fp)
+ 8040b70:	e17ff915 	stw	r5,-28(fp)
+ 8040b74:	3007883a 	mov	r3,r6
+ 8040b78:	e1fff715 	stw	r7,-36(fp)
+ 8040b7c:	e0800117 	ldw	r2,4(fp)
+ 8040b80:	e0fff80d 	sth	r3,-32(fp)
+ 8040b84:	e0bff60d 	sth	r2,-40(fp)
+   struct inpcb * inp, *   match =  0;
+ 8040b88:	e03ffe15 	stw	zero,-8(fp)
+   unshort  fport =  xfport; 
+ 8040b8c:	e0bff80b 	ldhu	r2,-32(fp)
+ 8040b90:	e0bffb8d 	sth	r2,-18(fp)
+   unshort  lport =  xlport;
+ 8040b94:	e0bff60b 	ldhu	r2,-40(fp)
+ 8040b98:	e0bffb0d 	sth	r2,-20(fp)
+   int   matchwild   =  3;
+ 8040b9c:	008000c4 	movi	r2,3
+ 8040ba0:	e0bffd15 	stw	r2,-12(fp)
+   int   wildcard;
+
+   for (inp = head->inp_next; inp != head; inp = inp->inp_next) 
+ 8040ba4:	e0bffa17 	ldw	r2,-24(fp)
+ 8040ba8:	10800017 	ldw	r2,0(r2)
+ 8040bac:	e0bfff15 	stw	r2,-4(fp)
+ 8040bb0:	00004f06 	br	8040cf0 <in_pcblookup+0x190>
+   {
+      if (inp->inp_lport != lport)
+ 8040bb4:	e0bfff17 	ldw	r2,-4(fp)
+ 8040bb8:	1080078b 	ldhu	r2,30(r2)
+ 8040bbc:	e0fffb0b 	ldhu	r3,-20(fp)
+ 8040bc0:	10bfffcc 	andi	r2,r2,65535
+ 8040bc4:	1880401e 	bne	r3,r2,8040cc8 <in_pcblookup+0x168>
+         continue;
+
+      /* Skip non IPv4 sockets */
+      if(inp->inp_socket->so_domain != AF_INET)
+ 8040bc8:	e0bfff17 	ldw	r2,-4(fp)
+ 8040bcc:	10800817 	ldw	r2,32(r2)
+ 8040bd0:	10800517 	ldw	r2,20(r2)
+ 8040bd4:	108000a0 	cmpeqi	r2,r2,2
+ 8040bd8:	10003d26 	beq	r2,zero,8040cd0 <in_pcblookup+0x170>
+         continue;
+
+      wildcard = 0;
+ 8040bdc:	e03ffc15 	stw	zero,-16(fp)
+      if (inp->inp_laddr.s_addr != INADDR_ANY) 
+ 8040be0:	e0bfff17 	ldw	r2,-4(fp)
+ 8040be4:	10800417 	ldw	r2,16(r2)
+ 8040be8:	10000b26 	beq	r2,zero,8040c18 <in_pcblookup+0xb8>
+      {
+         if (laddr == INADDR_ANY)
+ 8040bec:	e0bff717 	ldw	r2,-36(fp)
+ 8040bf0:	1000041e 	bne	r2,zero,8040c04 <in_pcblookup+0xa4>
+            wildcard++;
+ 8040bf4:	e0bffc17 	ldw	r2,-16(fp)
+ 8040bf8:	10800044 	addi	r2,r2,1
+ 8040bfc:	e0bffc15 	stw	r2,-16(fp)
+ 8040c00:	00000a06 	br	8040c2c <in_pcblookup+0xcc>
+         else if (inp->inp_laddr.s_addr != laddr)
+ 8040c04:	e0bfff17 	ldw	r2,-4(fp)
+ 8040c08:	10800417 	ldw	r2,16(r2)
+ 8040c0c:	e0fff717 	ldw	r3,-36(fp)
+ 8040c10:	18800626 	beq	r3,r2,8040c2c <in_pcblookup+0xcc>
+            continue;
+ 8040c14:	00003306 	br	8040ce4 <in_pcblookup+0x184>
+      }
+      else 
+      {
+         if (laddr != INADDR_ANY)
+ 8040c18:	e0bff717 	ldw	r2,-36(fp)
+ 8040c1c:	10000326 	beq	r2,zero,8040c2c <in_pcblookup+0xcc>
+            wildcard++;
+ 8040c20:	e0bffc17 	ldw	r2,-16(fp)
+ 8040c24:	10800044 	addi	r2,r2,1
+ 8040c28:	e0bffc15 	stw	r2,-16(fp)
+      }
+      if (inp->inp_faddr.s_addr != INADDR_ANY) 
+ 8040c2c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040c30:	10800317 	ldw	r2,12(r2)
+ 8040c34:	10001026 	beq	r2,zero,8040c78 <in_pcblookup+0x118>
+      {
+         if (faddr == INADDR_ANY)
+ 8040c38:	e0bff917 	ldw	r2,-28(fp)
+ 8040c3c:	1000041e 	bne	r2,zero,8040c50 <in_pcblookup+0xf0>
+            wildcard++;
+ 8040c40:	e0bffc17 	ldw	r2,-16(fp)
+ 8040c44:	10800044 	addi	r2,r2,1
+ 8040c48:	e0bffc15 	stw	r2,-16(fp)
+ 8040c4c:	00000f06 	br	8040c8c <in_pcblookup+0x12c>
+         else if (inp->inp_faddr.s_addr != faddr ||
+ 8040c50:	e0bfff17 	ldw	r2,-4(fp)
+ 8040c54:	10800317 	ldw	r2,12(r2)
+ 8040c58:	e0fff917 	ldw	r3,-28(fp)
+ 8040c5c:	18801e1e 	bne	r3,r2,8040cd8 <in_pcblookup+0x178>
+             inp->inp_fport != fport)
+ 8040c60:	e0bfff17 	ldw	r2,-4(fp)
+ 8040c64:	1080070b 	ldhu	r2,28(r2)
+         else if (inp->inp_faddr.s_addr != faddr ||
+ 8040c68:	e0fffb8b 	ldhu	r3,-18(fp)
+ 8040c6c:	10bfffcc 	andi	r2,r2,65535
+ 8040c70:	18800626 	beq	r3,r2,8040c8c <in_pcblookup+0x12c>
+         {
+            continue;
+ 8040c74:	00001806 	br	8040cd8 <in_pcblookup+0x178>
+         }
+      } else 
+      {
+         if (faddr != INADDR_ANY)
+ 8040c78:	e0bff917 	ldw	r2,-28(fp)
+ 8040c7c:	10000326 	beq	r2,zero,8040c8c <in_pcblookup+0x12c>
+            wildcard++;
+ 8040c80:	e0bffc17 	ldw	r2,-16(fp)
+ 8040c84:	10800044 	addi	r2,r2,1
+ 8040c88:	e0bffc15 	stw	r2,-16(fp)
+      }
+      if (wildcard && (flags & INPLOOKUP_WILDCARD) == 0)
+ 8040c8c:	e0bffc17 	ldw	r2,-16(fp)
+ 8040c90:	10000326 	beq	r2,zero,8040ca0 <in_pcblookup+0x140>
+ 8040c94:	e0800217 	ldw	r2,8(fp)
+ 8040c98:	1080004c 	andi	r2,r2,1
+ 8040c9c:	10001026 	beq	r2,zero,8040ce0 <in_pcblookup+0x180>
+         continue;
+      if (wildcard < matchwild) 
+ 8040ca0:	e0fffc17 	ldw	r3,-16(fp)
+ 8040ca4:	e0bffd17 	ldw	r2,-12(fp)
+ 8040ca8:	18800e0e 	bge	r3,r2,8040ce4 <in_pcblookup+0x184>
+      {
+         match = inp;
+ 8040cac:	e0bfff17 	ldw	r2,-4(fp)
+ 8040cb0:	e0bffe15 	stw	r2,-8(fp)
+         matchwild = wildcard;
+ 8040cb4:	e0bffc17 	ldw	r2,-16(fp)
+ 8040cb8:	e0bffd15 	stw	r2,-12(fp)
+         if (matchwild == 0)
+ 8040cbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8040cc0:	10000f26 	beq	r2,zero,8040d00 <in_pcblookup+0x1a0>
+ 8040cc4:	00000706 	br	8040ce4 <in_pcblookup+0x184>
+         continue;
+ 8040cc8:	0001883a 	nop
+ 8040ccc:	00000506 	br	8040ce4 <in_pcblookup+0x184>
+         continue;
+ 8040cd0:	0001883a 	nop
+ 8040cd4:	00000306 	br	8040ce4 <in_pcblookup+0x184>
+            continue;
+ 8040cd8:	0001883a 	nop
+ 8040cdc:	00000106 	br	8040ce4 <in_pcblookup+0x184>
+         continue;
+ 8040ce0:	0001883a 	nop
+   for (inp = head->inp_next; inp != head; inp = inp->inp_next) 
+ 8040ce4:	e0bfff17 	ldw	r2,-4(fp)
+ 8040ce8:	10800017 	ldw	r2,0(r2)
+ 8040cec:	e0bfff15 	stw	r2,-4(fp)
+ 8040cf0:	e0ffff17 	ldw	r3,-4(fp)
+ 8040cf4:	e0bffa17 	ldw	r2,-24(fp)
+ 8040cf8:	18bfae1e 	bne	r3,r2,8040bb4 <in_pcblookup+0x54>
+ 8040cfc:	00000106 	br	8040d04 <in_pcblookup+0x1a4>
+            break;
+ 8040d00:	0001883a 	nop
+      }
+   }
+   if (match == NULL)
+ 8040d04:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d08:	1000021e 	bne	r2,zero,8040d14 <in_pcblookup+0x1b4>
+      return match;
+ 8040d0c:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d10:	00002406 	br	8040da4 <in_pcblookup+0x244>
+
+   if (head->inp_next == match)  /* got cache hit? */
+ 8040d14:	e0bffa17 	ldw	r2,-24(fp)
+ 8040d18:	10800017 	ldw	r2,0(r2)
+ 8040d1c:	e0fffe17 	ldw	r3,-8(fp)
+ 8040d20:	1880041e 	bne	r3,r2,8040d34 <in_pcblookup+0x1d4>
+   {
+      inpcb_cachehits++;
+ 8040d24:	d0a09f17 	ldw	r2,-32132(gp)
+ 8040d28:	10800044 	addi	r2,r2,1
+ 8040d2c:	d0a09f15 	stw	r2,-32132(gp)
+ 8040d30:	00001b06 	br	8040da0 <in_pcblookup+0x240>
+   }
+   else
+   {
+      inpcb_cachemiss++;
+ 8040d34:	d0a0a017 	ldw	r2,-32128(gp)
+ 8040d38:	10800044 	addi	r2,r2,1
+ 8040d3c:	d0a0a015 	stw	r2,-32128(gp)
+      /* "cache" the match to be first checked next time. */
+      match->inp_next->inp_prev = match->inp_prev; /*unlink match */
+ 8040d40:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d44:	10800017 	ldw	r2,0(r2)
+ 8040d48:	e0fffe17 	ldw	r3,-8(fp)
+ 8040d4c:	18c00117 	ldw	r3,4(r3)
+ 8040d50:	10c00115 	stw	r3,4(r2)
+      match->inp_prev->inp_next = match->inp_next;
+ 8040d54:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d58:	10800117 	ldw	r2,4(r2)
+ 8040d5c:	e0fffe17 	ldw	r3,-8(fp)
+ 8040d60:	18c00017 	ldw	r3,0(r3)
+ 8040d64:	10c00015 	stw	r3,0(r2)
+
+      /* relink match as head->inp_next */
+      match->inp_next = head->inp_next;
+ 8040d68:	e0bffa17 	ldw	r2,-24(fp)
+ 8040d6c:	10c00017 	ldw	r3,0(r2)
+ 8040d70:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d74:	10c00015 	stw	r3,0(r2)
+      head->inp_next = match;
+ 8040d78:	e0bffa17 	ldw	r2,-24(fp)
+ 8040d7c:	e0fffe17 	ldw	r3,-8(fp)
+ 8040d80:	10c00015 	stw	r3,0(r2)
+      match->inp_prev = head;
+ 8040d84:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d88:	e0fffa17 	ldw	r3,-24(fp)
+ 8040d8c:	10c00115 	stw	r3,4(r2)
+      match->inp_next->inp_prev = match;
+ 8040d90:	e0bffe17 	ldw	r2,-8(fp)
+ 8040d94:	10800017 	ldw	r2,0(r2)
+ 8040d98:	e0fffe17 	ldw	r3,-8(fp)
+ 8040d9c:	10c00115 	stw	r3,4(r2)
+   }
+   return (match);
+ 8040da0:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 8040da4:	e037883a 	mov	sp,fp
+ 8040da8:	df000017 	ldw	fp,0(sp)
+ 8040dac:	dec00104 	addi	sp,sp,4
+ 8040db0:	f800283a 	ret
+
+08040db4 <set_vfopen_error>:
+ *
+ * RETURNS: 
+ */
+
+void set_vfopen_error(int error)
+{
+ 8040db4:	defffe04 	addi	sp,sp,-8
+ 8040db8:	df000115 	stw	fp,4(sp)
+ 8040dbc:	df000104 	addi	fp,sp,4
+ 8040dc0:	e13fff15 	stw	r4,-4(fp)
+   vfopen_error = error;
+ 8040dc4:	e0bfff17 	ldw	r2,-4(fp)
+ 8040dc8:	d0a0a415 	stw	r2,-32112(gp)
+}
+ 8040dcc:	0001883a 	nop
+ 8040dd0:	e037883a 	mov	sp,fp
+ 8040dd4:	df000017 	ldw	fp,0(sp)
+ 8040dd8:	dec00104 	addi	sp,sp,4
+ 8040ddc:	f800283a 	ret
+
+08040de0 <get_vfopen_error>:
+ *
+ * RETURNS: 
+ */
+
+int get_vfopen_error()
+{
+ 8040de0:	deffff04 	addi	sp,sp,-4
+ 8040de4:	df000015 	stw	fp,0(sp)
+ 8040de8:	d839883a 	mov	fp,sp
+   return vfopen_error;
+ 8040dec:	d0a0a417 	ldw	r2,-32112(gp)
+}
+ 8040df0:	e037883a 	mov	sp,fp
+ 8040df4:	df000017 	ldw	fp,0(sp)
+ 8040df8:	dec00104 	addi	sp,sp,4
+ 8040dfc:	f800283a 	ret
+
+08040e00 <vf_alloc_and_link_vop>:
+ *
+ * RETURNS: 
+ */
+
+VFILE * vf_alloc_and_link_vop()
+{
+ 8040e00:	defffd04 	addi	sp,sp,-12
+ 8040e04:	dfc00215 	stw	ra,8(sp)
+ 8040e08:	df000115 	stw	fp,4(sp)
+ 8040e0c:	df000104 	addi	fp,sp,4
+   struct vfs_open * vop;
+
+   /* enforce maximum number of simultaneously open files */
+   if (vfs_open_files >= VFS_MAX_OPEN_FILES)
+ 8040e10:	d0a0a617 	ldw	r2,-32104(gp)
+ 8040e14:	10803ff0 	cmpltui	r2,r2,255
+ 8040e18:	1000021e 	bne	r2,zero,8040e24 <vf_alloc_and_link_vop+0x24>
+   {
+#ifdef VFS_VERBOSE
+      dprintf("vfs_open_files too big (%ld) in vf_alloc_and_link_vop()\n",
+       vfs_open_files);
+#endif   /* VFS_VERBOSE */
+      return NULL;
+ 8040e1c:	0005883a 	mov	r2,zero
+ 8040e20:	00000e06 	br	8040e5c <vf_alloc_and_link_vop+0x5c>
+   }
+
+   /* allocate a structure to represent the open file */
+   vop = VFS_VFS_OPEN_ALLOC();
+ 8040e24:	01000504 	movi	r4,20
+ 8040e28:	802982c0 	call	802982c <npalloc>
+ 8040e2c:	e0bfff15 	stw	r2,-4(fp)
+
+   /* if the allocation succeeded */
+   if (vop)
+ 8040e30:	e0bfff17 	ldw	r2,-4(fp)
+ 8040e34:	10000826 	beq	r2,zero,8040e58 <vf_alloc_and_link_vop+0x58>
+   {
+      /* add to the beginning of the list of open files */
+      vop->next = vfiles;
+ 8040e38:	d0e0a217 	ldw	r3,-32120(gp)
+ 8040e3c:	e0bfff17 	ldw	r2,-4(fp)
+ 8040e40:	10c00015 	stw	r3,0(r2)
+      vfiles = vop;
+ 8040e44:	e0bfff17 	ldw	r2,-4(fp)
+ 8040e48:	d0a0a215 	stw	r2,-32120(gp)
+      /* increment the count of open files */
+      vfs_open_files++;
+ 8040e4c:	d0a0a617 	ldw	r2,-32104(gp)
+ 8040e50:	10800044 	addi	r2,r2,1
+ 8040e54:	d0a0a615 	stw	r2,-32104(gp)
+#ifdef VFS_VERBOSE
+   else
+      dprintf("VFS_VFS_OPEN_ALLOC() failed in vf_alloc_and_link_vop()\n");
+#endif   /* VFS_VERBOSE */
+
+   return vop;
+ 8040e58:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8040e5c:	e037883a 	mov	sp,fp
+ 8040e60:	dfc00117 	ldw	ra,4(sp)
+ 8040e64:	df000017 	ldw	fp,0(sp)
+ 8040e68:	dec00204 	addi	sp,sp,8
+ 8040e6c:	f800283a 	ret
+
+08040e70 <vf_alloc_buffer>:
+ *
+ * RETURNS: 
+ */
+
+unsigned char * vf_alloc_buffer(unsigned long size)
+{
+ 8040e70:	defff904 	addi	sp,sp,-28
+ 8040e74:	dfc00615 	stw	ra,24(sp)
+ 8040e78:	df000515 	stw	fp,20(sp)
+ 8040e7c:	df000504 	addi	fp,sp,20
+ 8040e80:	e13ffb15 	stw	r4,-20(fp)
+   unsigned int long_size,int_size;
+#endif   /* MUTE_WARNS */
+
+   /* make sure the requested allocation does not exceed the total
+      memory space reserved for file buffers */
+   if ((vfs_total_rw_space + size) > VFS_MAX_TOTAL_RW_SPACE)
+ 8040e84:	d0e0a717 	ldw	r3,-32100(gp)
+ 8040e88:	e0bffb17 	ldw	r2,-20(fp)
+ 8040e8c:	1885883a 	add	r2,r3,r2
+ 8040e90:	00ffffd4 	movui	r3,65535
+ 8040e94:	1880022e 	bgeu	r3,r2,8040ea0 <vf_alloc_buffer+0x30>
+      return NULL;
+ 8040e98:	0005883a 	mov	r2,zero
+ 8040e9c:	00002106 	br	8040f24 <vf_alloc_buffer+0xb4>
+    * any bigger than what will fit in an unsigned int 
+    */
+#ifdef MUTE_WARNS
+   /* the idiotic hoops you got to jump through to suppress compiler
+      warnings */
+   long_size   =  sizeof(unsigned   long);
+ 8040ea0:	00800104 	movi	r2,4
+ 8040ea4:	e0bfff15 	stw	r2,-4(fp)
+   int_size = sizeof(unsigned int);
+ 8040ea8:	00800104 	movi	r2,4
+ 8040eac:	e0bffe15 	stw	r2,-8(fp)
+   if (long_size > int_size)
+ 8040eb0:	e0bfff17 	ldw	r2,-4(fp)
+ 8040eb4:	e0fffe17 	ldw	r3,-8(fp)
+ 8040eb8:	1880102e 	bgeu	r3,r2,8040efc <vf_alloc_buffer+0x8c>
+       * most systems where this "if" expression will evaluate to 
+       * true (2 byte ints, 4 byte longs). if any of those upper bits 
+       * are on in your requested size, you otta luck.
+       */
+#ifdef MUTE_WARNS
+      switch (int_size)
+ 8040ebc:	e0bffe17 	ldw	r2,-8(fp)
+ 8040ec0:	10800098 	cmpnei	r2,r2,2
+ 8040ec4:	1000081e 	bne	r2,zero,8040ee8 <vf_alloc_buffer+0x78>
+#else
+      switch (sizeof(unsigned int))
+#endif   /* MUTE_WARNS */
+      {
+      case 2 :
+         mem_mask = 0xffff0000;
+ 8040ec8:	00bffff4 	movhi	r2,65535
+ 8040ecc:	e0bffd15 	stw	r2,-12(fp)
+         break;
+ 8040ed0:	0001883a 	nop
+         default :
+            dtrap();    /* you have a weird compiler */
+         return NULL;
+      }
+
+      if (size & mem_mask)
+ 8040ed4:	e0fffb17 	ldw	r3,-20(fp)
+ 8040ed8:	e0bffd17 	ldw	r2,-12(fp)
+ 8040edc:	1884703a 	and	r2,r3,r2
+ 8040ee0:	10000626 	beq	r2,zero,8040efc <vf_alloc_buffer+0x8c>
+ 8040ee4:	00000306 	br	8040ef4 <vf_alloc_buffer+0x84>
+            dtrap();    /* you have a weird compiler */
+ 8040ee8:	8028cd40 	call	8028cd4 <dtrap>
+         return NULL;
+ 8040eec:	0005883a 	mov	r2,zero
+ 8040ef0:	00000c06 	br	8040f24 <vf_alloc_buffer+0xb4>
+         return NULL;
+ 8040ef4:	0005883a 	mov	r2,zero
+ 8040ef8:	00000a06 	br	8040f24 <vf_alloc_buffer+0xb4>
+   }
+
+   /* try to allocate a buffer of the requested size */
+   buffer = (unsigned char *) npalloc((unsigned int) size);
+ 8040efc:	e13ffb17 	ldw	r4,-20(fp)
+ 8040f00:	802982c0 	call	802982c <npalloc>
+ 8040f04:	e0bffc15 	stw	r2,-16(fp)
+
+   /* if the allocation succeeded */
+   if (buffer)
+ 8040f08:	e0bffc17 	ldw	r2,-16(fp)
+ 8040f0c:	10000426 	beq	r2,zero,8040f20 <vf_alloc_buffer+0xb0>
+   {
+      /* add size to the count of total buffer space allocated */
+      vfs_total_rw_space += size;
+ 8040f10:	d0e0a717 	ldw	r3,-32100(gp)
+ 8040f14:	e0bffb17 	ldw	r2,-20(fp)
+ 8040f18:	1885883a 	add	r2,r3,r2
+ 8040f1c:	d0a0a715 	stw	r2,-32100(gp)
+   }
+
+   return buffer;
+ 8040f20:	e0bffc17 	ldw	r2,-16(fp)
+}
+ 8040f24:	e037883a 	mov	sp,fp
+ 8040f28:	dfc00117 	ldw	ra,4(sp)
+ 8040f2c:	df000017 	ldw	fp,0(sp)
+ 8040f30:	dec00204 	addi	sp,sp,8
+ 8040f34:	f800283a 	ret
+
+08040f38 <vf_free_buffer>:
+ *
+ * RETURNS: 
+ */
+
+void vf_free_buffer(unsigned char * buffer, unsigned long size)
+{
+ 8040f38:	defffc04 	addi	sp,sp,-16
+ 8040f3c:	dfc00315 	stw	ra,12(sp)
+ 8040f40:	df000215 	stw	fp,8(sp)
+ 8040f44:	df000204 	addi	fp,sp,8
+ 8040f48:	e13fff15 	stw	r4,-4(fp)
+ 8040f4c:	e17ffe15 	stw	r5,-8(fp)
+   /* free the buffer */
+   if (buffer)
+ 8040f50:	e0bfff17 	ldw	r2,-4(fp)
+ 8040f54:	10000226 	beq	r2,zero,8040f60 <vf_free_buffer+0x28>
+      npfree(buffer);
+ 8040f58:	e13fff17 	ldw	r4,-4(fp)
+ 8040f5c:	80298600 	call	8029860 <npfree>
+
+   /* and subtract its size from the total buffer space count */
+   vfs_total_rw_space -= size;
+ 8040f60:	d0e0a717 	ldw	r3,-32100(gp)
+ 8040f64:	e0bffe17 	ldw	r2,-8(fp)
+ 8040f68:	1885c83a 	sub	r2,r3,r2
+ 8040f6c:	d0a0a715 	stw	r2,-32100(gp)
+}
+ 8040f70:	0001883a 	nop
+ 8040f74:	e037883a 	mov	sp,fp
+ 8040f78:	dfc00117 	ldw	ra,4(sp)
+ 8040f7c:	df000017 	ldw	fp,0(sp)
+ 8040f80:	dec00204 	addi	sp,sp,8
+ 8040f84:	f800283a 	ret
+
+08040f88 <vfopen_locked>:
+ * RETURNS: 
+ */
+
+VFILE *
+vfopen_locked(char * name, char * mode)
+{
+ 8040f88:	defff904 	addi	sp,sp,-28
+ 8040f8c:	dfc00615 	stw	ra,24(sp)
+ 8040f90:	df000515 	stw	fp,20(sp)
+ 8040f94:	df000504 	addi	fp,sp,20
+ 8040f98:	e13ffc15 	stw	r4,-16(fp)
+ 8040f9c:	e17ffb15 	stw	r5,-20(fp)
+   struct vfs_file * vfp;
+   struct vfs_open * vop;
+
+   /* clear any previous vfopen() error */
+   set_vfopen_error(0);
+ 8040fa0:	0009883a 	mov	r4,zero
+ 8040fa4:	8040db40 	call	8040db4 <set_vfopen_error>
+
+   /* the old code used to do special handling of '?' in files for 
+    * the benefit of the web server. the web server should be doing 
+    * this now. this is here to make sure that its doing it 
+    */
+   if (strchr(name,'?'))
+ 8040fa8:	01400fc4 	movi	r5,63
+ 8040fac:	e13ffc17 	ldw	r4,-16(fp)
+ 8040fb0:	8042dfc0 	call	8042dfc <strchr>
+ 8040fb4:	10000326 	beq	r2,zero,8040fc4 <vfopen_locked+0x3c>
+   {
+      dtrap();
+ 8040fb8:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 8040fbc:	0005883a 	mov	r2,zero
+ 8040fc0:	0000ba06 	br	80412ac <vfopen_locked+0x324>
+   }
+
+   /* determine if the file exists */
+   /* if the directory exists, vfp will point to its directory entry
+      structure else vfp will be NULL */
+   vfp = vfslookup_locked(name);
+ 8040fc4:	e13ffc17 	ldw	r4,-16(fp)
+ 8040fc8:	80422080 	call	8042208 <vfslookup_locked>
+ 8040fcc:	e0bffe15 	stw	r2,-8(fp)
+
+   /* if the file exists */
+   if (vfp)
+ 8040fd0:	e0bffe17 	ldw	r2,-8(fp)
+ 8040fd4:	10004a26 	beq	r2,zero,8041100 <vfopen_locked+0x178>
+
+#ifdef HT_RWVFS
+
+      /* if mode begins with 'w' we will truncate to end of file */
+      /* make sure the file is writable before proceeding */
+      if ((*mode == 'w') && !(vfp->flags & VF_WRITE))
+ 8040fd8:	e0bffb17 	ldw	r2,-20(fp)
+ 8040fdc:	10800003 	ldbu	r2,0(r2)
+ 8040fe0:	10803fcc 	andi	r2,r2,255
+ 8040fe4:	1080201c 	xori	r2,r2,128
+ 8040fe8:	10bfe004 	addi	r2,r2,-128
+ 8040fec:	10801dd8 	cmpnei	r2,r2,119
+ 8040ff0:	1000091e 	bne	r2,zero,8041018 <vfopen_locked+0x90>
+ 8040ff4:	e0bffe17 	ldw	r2,-8(fp)
+ 8040ff8:	1080058b 	ldhu	r2,22(r2)
+ 8040ffc:	10bfffcc 	andi	r2,r2,65535
+ 8041000:	1080080c 	andi	r2,r2,32
+ 8041004:	1000041e 	bne	r2,zero,8041018 <vfopen_locked+0x90>
+      {
+         set_vfopen_error(ENP_FILEIO);
+ 8041008:	013ff984 	movi	r4,-26
+ 804100c:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("mode w with no VF_WRITE\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 8041010:	0005883a 	mov	r2,zero
+ 8041014:	0000a506 	br	80412ac <vfopen_locked+0x324>
+      }
+
+#endif   /* HT_RWVFS */
+
+      /* allocate a VFILE structure to represent the open file */
+      vop = vf_alloc_and_link_vop();
+ 8041018:	8040e000 	call	8040e00 <vf_alloc_and_link_vop>
+ 804101c:	e0bffd15 	stw	r2,-12(fp)
+
+      /* check for failure */
+      if (!vop)
+ 8041020:	e0bffd17 	ldw	r2,-12(fp)
+ 8041024:	1000041e 	bne	r2,zero,8041038 <vfopen_locked+0xb0>
+      {
+         set_vfopen_error(ENP_NOMEM);
+ 8041028:	013ffb04 	movi	r4,-20
+ 804102c:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("vf_alloc_and_link_vop() failed 1\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 8041030:	0005883a 	mov	r2,zero
+ 8041034:	00009d06 	br	80412ac <vfopen_locked+0x324>
+      }
+
+      /* link to the file's directory entry structure */
+      vop->file = vfp;
+ 8041038:	e0bffd17 	ldw	r2,-12(fp)
+ 804103c:	e0fffe17 	ldw	r3,-8(fp)
+ 8041040:	10c00115 	stw	r3,4(r2)
+
+      /* by default start at the beginning of the file */
+      /* note that vfp->data could be NULL at this point since empty
+         files might have no data buffer allocated to them */
+      vop->cmploc = vfp->data;   /* start at beginning of file */
+ 8041044:	e0bffe17 	ldw	r2,-8(fp)
+ 8041048:	10c00617 	ldw	r3,24(r2)
+ 804104c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041050:	10c00215 	stw	r3,8(r2)
+
+#ifdef HT_RWVFS
+
+      /* if mode begins with 'a', seek to end of file */
+      if (*mode == 'a')
+ 8041054:	e0bffb17 	ldw	r2,-20(fp)
+ 8041058:	10800003 	ldbu	r2,0(r2)
+ 804105c:	10803fcc 	andi	r2,r2,255
+ 8041060:	1080201c 	xori	r2,r2,128
+ 8041064:	10bfe004 	addi	r2,r2,-128
+ 8041068:	10801858 	cmpnei	r2,r2,97
+ 804106c:	10000a1e 	bne	r2,zero,8041098 <vfopen_locked+0x110>
+      {
+         if (vfp->data)
+ 8041070:	e0bffe17 	ldw	r2,-8(fp)
+ 8041074:	10800617 	ldw	r2,24(r2)
+ 8041078:	10000726 	beq	r2,zero,8041098 <vfopen_locked+0x110>
+         {
+            vop->cmploc = vfp->data + vfp->comp_size;
+ 804107c:	e0bffe17 	ldw	r2,-8(fp)
+ 8041080:	10c00617 	ldw	r3,24(r2)
+ 8041084:	e0bffe17 	ldw	r2,-8(fp)
+ 8041088:	10800817 	ldw	r2,32(r2)
+ 804108c:	1887883a 	add	r3,r3,r2
+ 8041090:	e0bffd17 	ldw	r2,-12(fp)
+ 8041094:	10c00215 	stw	r3,8(r2)
+         }
+      }
+
+      /* if mode begins with 'w', truncate to end of file */
+      if (*mode == 'w')
+ 8041098:	e0bffb17 	ldw	r2,-20(fp)
+ 804109c:	10800003 	ldbu	r2,0(r2)
+ 80410a0:	10803fcc 	andi	r2,r2,255
+ 80410a4:	1080201c 	xori	r2,r2,128
+ 80410a8:	10bfe004 	addi	r2,r2,-128
+ 80410ac:	10801dd8 	cmpnei	r2,r2,119
+ 80410b0:	1000111e 	bne	r2,zero,80410f8 <vfopen_locked+0x170>
+      {
+         /* set the size of the file before compression to 0 */
+         vfp->real_size = 0;
+ 80410b4:	e0bffe17 	ldw	r2,-8(fp)
+ 80410b8:	10000715 	stw	zero,28(r2)
+         /* set the size of the compressed data to 0 */
+         vfp->comp_size = 0;
+ 80410bc:	e0bffe17 	ldw	r2,-8(fp)
+ 80410c0:	10000815 	stw	zero,32(r2)
+         /* note we leave the pointer to the file buffer and its length
+            alone since first writes will go to it */
+         /* flag that the file has been modified */
+         vfp->flags |= VF_STALE;
+ 80410c4:	e0bffe17 	ldw	r2,-8(fp)
+ 80410c8:	1080058b 	ldhu	r2,22(r2)
+ 80410cc:	10808014 	ori	r2,r2,512
+ 80410d0:	1007883a 	mov	r3,r2
+ 80410d4:	e0bffe17 	ldw	r2,-8(fp)
+ 80410d8:	10c0058d 	sth	r3,22(r2)
+
+         /* turn off the compression flag */
+         vfp->flags &= ~VF_HTMLCOMPRESSED;
+ 80410dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80410e0:	10c0058b 	ldhu	r3,22(r2)
+ 80410e4:	00bfff84 	movi	r2,-2
+ 80410e8:	1884703a 	and	r2,r3,r2
+ 80410ec:	1007883a 	mov	r3,r2
+ 80410f0:	e0bffe17 	ldw	r2,-8(fp)
+ 80410f4:	10c0058d 	sth	r3,22(r2)
+      }
+
+#endif   /* HT_RWVFS */
+
+      return vop;
+ 80410f8:	e0bffd17 	ldw	r2,-12(fp)
+ 80410fc:	00006b06 	br	80412ac <vfopen_locked+0x324>
+
+#ifdef HT_EXTDEV
+
+   /* if the mode implies that the file should be created if it
+      does not exist */
+   if (*mode != 'r')
+ 8041100:	e0bffb17 	ldw	r2,-20(fp)
+ 8041104:	10800003 	ldbu	r2,0(r2)
+ 8041108:	10803fcc 	andi	r2,r2,255
+ 804110c:	1080201c 	xori	r2,r2,128
+ 8041110:	10bfe004 	addi	r2,r2,-128
+ 8041114:	10801ca0 	cmpeqi	r2,r2,114
+ 8041118:	1000121e 	bne	r2,zero,8041164 <vfopen_locked+0x1dc>
+   {
+      /* see if one of the other systems wants to create this file */
+      /* if none of the below devices can open the file, continue on */
+      struct vfroutines *  vfs;
+
+      for (vfs = vfsystems; vfs; vfs = vfs->next)
+ 804111c:	d0a0a117 	ldw	r2,-32124(gp)
+ 8041120:	e0bfff15 	stw	r2,-4(fp)
+ 8041124:	00000d06 	br	804115c <vfopen_locked+0x1d4>
+      {
+         if ((vop = vfs->r_fopen(name, mode)) != NULL)
+ 8041128:	e0bfff17 	ldw	r2,-4(fp)
+ 804112c:	10800117 	ldw	r2,4(r2)
+ 8041130:	e17ffb17 	ldw	r5,-20(fp)
+ 8041134:	e13ffc17 	ldw	r4,-16(fp)
+ 8041138:	103ee83a 	callr	r2
+ 804113c:	e0bffd15 	stw	r2,-12(fp)
+ 8041140:	e0bffd17 	ldw	r2,-12(fp)
+ 8041144:	10000226 	beq	r2,zero,8041150 <vfopen_locked+0x1c8>
+         {
+            return vop;
+ 8041148:	e0bffd17 	ldw	r2,-12(fp)
+ 804114c:	00005706 	br	80412ac <vfopen_locked+0x324>
+      for (vfs = vfsystems; vfs; vfs = vfs->next)
+ 8041150:	e0bfff17 	ldw	r2,-4(fp)
+ 8041154:	10800017 	ldw	r2,0(r2)
+ 8041158:	e0bfff15 	stw	r2,-4(fp)
+ 804115c:	e0bfff17 	ldw	r2,-4(fp)
+ 8041160:	103ff11e 	bne	r2,zero,8041128 <vfopen_locked+0x1a0>
+
+#ifdef HT_RWVFS
+
+   /* if the mode implies that the file should be created if it
+      does not exist */
+   if (*mode != 'r')
+ 8041164:	e0bffb17 	ldw	r2,-20(fp)
+ 8041168:	10800003 	ldbu	r2,0(r2)
+ 804116c:	10803fcc 	andi	r2,r2,255
+ 8041170:	1080201c 	xori	r2,r2,128
+ 8041174:	10bfe004 	addi	r2,r2,-128
+ 8041178:	10801ca0 	cmpeqi	r2,r2,114
+ 804117c:	1000481e 	bne	r2,zero,80412a0 <vfopen_locked+0x318>
+   {
+      /* enforce maximum number of files */
+      if (vfs_total_dyna_files >= VFS_MAX_DYNA_FILES)
+ 8041180:	d0a0a817 	ldw	r2,-32096(gp)
+ 8041184:	10803ff0 	cmpltui	r2,r2,255
+ 8041188:	1000041e 	bne	r2,zero,804119c <vfopen_locked+0x214>
+      {
+         set_vfopen_error(ENP_NOMEM);
+ 804118c:	013ffb04 	movi	r4,-20
+ 8041190:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("vf_total_dyna_files too big in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 8041194:	0005883a 	mov	r2,zero
+ 8041198:	00004406 	br	80412ac <vfopen_locked+0x324>
+      }
+
+      /* make sure the file name is not too long for the VFS */
+      if (strlen(name) > FILENAMEMAX)
+ 804119c:	e13ffc17 	ldw	r4,-16(fp)
+ 80411a0:	8002dac0 	call	8002dac <strlen>
+ 80411a4:	10800470 	cmpltui	r2,r2,17
+ 80411a8:	1000041e 	bne	r2,zero,80411bc <vfopen_locked+0x234>
+      {
+         set_vfopen_error(ENP_PARAM);
+ 80411ac:	013ffd84 	movi	r4,-10
+ 80411b0:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("file name too long in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 80411b4:	0005883a 	mov	r2,zero
+ 80411b8:	00003c06 	br	80412ac <vfopen_locked+0x324>
+      }
+
+      /* allocate a vfs_file structure to hold the new file entry in */
+      vfp = VFS_VFS_FILE_ALLOC();
+ 80411bc:	01000b04 	movi	r4,44
+ 80411c0:	802982c0 	call	802982c <npalloc>
+ 80411c4:	e0bffe15 	stw	r2,-8(fp)
+
+      /* check for memory allocation failure */
+      if (!vfp)
+ 80411c8:	e0bffe17 	ldw	r2,-8(fp)
+ 80411cc:	1000041e 	bne	r2,zero,80411e0 <vfopen_locked+0x258>
+      {
+         set_vfopen_error(ENP_NOMEM);
+ 80411d0:	013ffb04 	movi	r4,-20
+ 80411d4:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("VFS_VFS_FILE_ALLOC() failed in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 80411d8:	0005883a 	mov	r2,zero
+ 80411dc:	00003306 	br	80412ac <vfopen_locked+0x324>
+      }
+
+      /* allocate a VFILE structure to represent the open file */
+      vop = vf_alloc_and_link_vop();
+ 80411e0:	8040e000 	call	8040e00 <vf_alloc_and_link_vop>
+ 80411e4:	e0bffd15 	stw	r2,-12(fp)
+
+      /* check for memory allocation failure */
+      if (!vop)
+ 80411e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80411ec:	1000061e 	bne	r2,zero,8041208 <vfopen_locked+0x280>
+      {
+         VFS_VFS_FILE_FREE(vfp); /* free the allocated vfs_file entry */
+ 80411f0:	e13ffe17 	ldw	r4,-8(fp)
+ 80411f4:	80298600 	call	8029860 <npfree>
+         set_vfopen_error(ENP_NOMEM);
+ 80411f8:	013ffb04 	movi	r4,-20
+ 80411fc:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+         dprintf("vf_alloc_and_link_vop() failed 2\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+ 8041200:	0005883a 	mov	r2,zero
+ 8041204:	00002906 	br	80412ac <vfopen_locked+0x324>
+      }
+
+      /* add the vfs_file structure to the head of the list */
+
+      vfp->next = vfsfiles;
+ 8041208:	d0e0a317 	ldw	r3,-32116(gp)
+ 804120c:	e0bffe17 	ldw	r2,-8(fp)
+ 8041210:	10c00015 	stw	r3,0(r2)
+      vfsfiles = vfp;
+ 8041214:	e0bffe17 	ldw	r2,-8(fp)
+ 8041218:	d0a0a315 	stw	r2,-32116(gp)
+
+      /* increment count of total files */
+      vfs_total_dyna_files++;
+ 804121c:	d0a0a817 	ldw	r2,-32096(gp)
+ 8041220:	10800044 	addi	r2,r2,1
+ 8041224:	d0a0a815 	stw	r2,-32096(gp)
+
+      /* remove leading directory separator before storing name */
+      if (*name == '/' || *name == '\\')
+ 8041228:	e0bffc17 	ldw	r2,-16(fp)
+ 804122c:	10800003 	ldbu	r2,0(r2)
+ 8041230:	10803fcc 	andi	r2,r2,255
+ 8041234:	1080201c 	xori	r2,r2,128
+ 8041238:	10bfe004 	addi	r2,r2,-128
+ 804123c:	10800be0 	cmpeqi	r2,r2,47
+ 8041240:	1000071e 	bne	r2,zero,8041260 <vfopen_locked+0x2d8>
+ 8041244:	e0bffc17 	ldw	r2,-16(fp)
+ 8041248:	10800003 	ldbu	r2,0(r2)
+ 804124c:	10803fcc 	andi	r2,r2,255
+ 8041250:	1080201c 	xori	r2,r2,128
+ 8041254:	10bfe004 	addi	r2,r2,-128
+ 8041258:	10801718 	cmpnei	r2,r2,92
+ 804125c:	1000031e 	bne	r2,zero,804126c <vfopen_locked+0x2e4>
+         name++;
+ 8041260:	e0bffc17 	ldw	r2,-16(fp)
+ 8041264:	10800044 	addi	r2,r2,1
+ 8041268:	e0bffc15 	stw	r2,-16(fp)
+
+      /* store the converted name in the directory entry structure */
+      strcpy(vfp->name,name);
+ 804126c:	e0bffe17 	ldw	r2,-8(fp)
+ 8041270:	10800104 	addi	r2,r2,4
+ 8041274:	e17ffc17 	ldw	r5,-16(fp)
+ 8041278:	1009883a 	mov	r4,r2
+ 804127c:	8042f600 	call	8042f60 <strcpy>
+
+      /* set the flags */
+      vfp->flags = VF_DYNAMICINFO   /* the directory entry was allocated */
+ 8041280:	e0bffe17 	ldw	r2,-8(fp)
+ 8041284:	00c0d804 	movi	r3,864
+ 8041288:	10c0058d 	sth	r3,22(r2)
+       * note that this means the data pointer contains a null 
+       * because we don't allocate any buffer to hold the data 
+       * in until the first write 
+       */
+      /* link to the file's directory entry structure */
+      vop->file = vfp;
+ 804128c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041290:	e0fffe17 	ldw	r3,-8(fp)
+ 8041294:	10c00115 	stw	r3,4(r2)
+      /* the cmploc and tag fields of the vop retain their NULLs from 
+       * npalloc(). cmploc contains NULL because there is no data 
+       * buffer to point to yet. tag contains NULL because no 
+       * decompression operation has started yet
+       */
+      return vop;
+ 8041298:	e0bffd17 	ldw	r2,-12(fp)
+ 804129c:	00000306 	br	80412ac <vfopen_locked+0x324>
+   /* pass the open to the local file system */
+   return (VFILE *) fopen(name,mode);
+
+#else
+
+   set_vfopen_error(ENP_NOFILE);
+ 80412a0:	013ff9c4 	movi	r4,-25
+ 80412a4:	8040db40 	call	8040db4 <set_vfopen_error>
+#ifdef VFS_VERBOSE
+   dprintf("fell thru to end of vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+   return NULL;
+ 80412a8:	0005883a 	mov	r2,zero
+
+#endif   /* HT_LOCALFS */
+}
+ 80412ac:	e037883a 	mov	sp,fp
+ 80412b0:	dfc00117 	ldw	ra,4(sp)
+ 80412b4:	df000017 	ldw	fp,0(sp)
+ 80412b8:	dec00204 	addi	sp,sp,8
+ 80412bc:	f800283a 	ret
+
+080412c0 <vfopen>:
+ * RETURNS: 
+ */
+
+VFILE *
+vfopen(char * name, char * mode)
+{
+ 80412c0:	defffb04 	addi	sp,sp,-20
+ 80412c4:	dfc00415 	stw	ra,16(sp)
+ 80412c8:	df000315 	stw	fp,12(sp)
+ 80412cc:	df000304 	addi	fp,sp,12
+ 80412d0:	e13ffe15 	stw	r4,-8(fp)
+ 80412d4:	e17ffd15 	stw	r5,-12(fp)
+   if (vfs_log_file_name)
+      dprintf("vfopen() passed >%s<,%s\n",name,mode);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+ 80412d8:	01000144 	movi	r4,5
+ 80412dc:	80292b40 	call	80292b4 <wait_app_sem>
+
+   vfd = vfopen_locked(name,mode);
+ 80412e0:	e17ffd17 	ldw	r5,-12(fp)
+ 80412e4:	e13ffe17 	ldw	r4,-8(fp)
+ 80412e8:	8040f880 	call	8040f88 <vfopen_locked>
+ 80412ec:	e0bfff15 	stw	r2,-4(fp)
+
+   vfs_unlock();
+ 80412f0:	01000144 	movi	r4,5
+ 80412f4:	80293680 	call	8029368 <post_app_sem>
+
+   return vfd;
+ 80412f8:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80412fc:	e037883a 	mov	sp,fp
+ 8041300:	dfc00117 	ldw	ra,4(sp)
+ 8041304:	df000017 	ldw	fp,0(sp)
+ 8041308:	dec00204 	addi	sp,sp,8
+ 804130c:	f800283a 	ret
+
+08041310 <vfclose_locked>:
+ * RETURNS: 
+ */
+
+void 
+vfclose_locked(VFILE * vfd)
+{
+ 8041310:	defff804 	addi	sp,sp,-32
+ 8041314:	dfc00715 	stw	ra,28(sp)
+ 8041318:	df000615 	stw	fp,24(sp)
+ 804131c:	df000604 	addi	fp,sp,24
+ 8041320:	e13ffa15 	stw	r4,-24(fp)
+   VFILE * vtmp;
+   VFILE * vlast;
+
+   vlast = NULL;
+ 8041324:	e03ffe15 	stw	zero,-8(fp)
+
+   /* see if vfd is in our list of open virtual files. We
+      can't use isvfile() since we need a pointer to last. */
+   vtmp = vfiles;
+ 8041328:	d0a0a217 	ldw	r2,-32120(gp)
+ 804132c:	e0bfff15 	stw	r2,-4(fp)
+   while (vtmp)
+ 8041330:	00000806 	br	8041354 <vfclose_locked+0x44>
+   {
+      /* if this is the one we are looking for, exist search loop */
+      if (vfd == vtmp)
+ 8041334:	e0fffa17 	ldw	r3,-24(fp)
+ 8041338:	e0bfff17 	ldw	r2,-4(fp)
+ 804133c:	18800826 	beq	r3,r2,8041360 <vfclose_locked+0x50>
+         break;
+
+      /* bump the next and previous pointers along to try the next one */
+      vlast = vtmp;
+ 8041340:	e0bfff17 	ldw	r2,-4(fp)
+ 8041344:	e0bffe15 	stw	r2,-8(fp)
+      vtmp = vtmp->next;
+ 8041348:	e0bfff17 	ldw	r2,-4(fp)
+ 804134c:	10800017 	ldw	r2,0(r2)
+ 8041350:	e0bfff15 	stw	r2,-4(fp)
+   while (vtmp)
+ 8041354:	e0bfff17 	ldw	r2,-4(fp)
+ 8041358:	103ff61e 	bne	r2,zero,8041334 <vfclose_locked+0x24>
+ 804135c:	00000106 	br	8041364 <vfclose_locked+0x54>
+         break;
+ 8041360:	0001883a 	nop
+   }
+
+   /* if the passed in handle was not in the list we maintain */
+   if (vfd != vtmp)
+ 8041364:	e0fffa17 	ldw	r3,-24(fp)
+ 8041368:	e0bfff17 	ldw	r2,-4(fp)
+ 804136c:	1880511e 	bne	r3,r2,80414b4 <vfclose_locked+0x1a4>
+
+   /* this not really a forever loop. it exists so we can break easily
+      and deal with all the ifdefs */
+   while (1)
+   {
+      struct vfs_file * vfp   =  vfd->file;
+ 8041370:	e0bffa17 	ldw	r2,-24(fp)
+ 8041374:	10800117 	ldw	r2,4(r2)
+ 8041378:	e0bffd15 	stw	r2,-12(fp)
+      /* vfd->file will be null if somebody unlinked the file after
+       * this handle was created to point to it. if the file itself 
+       * is gone there is nothing left to do, so break to list 
+       * deletion code at bottom of loop
+       */
+      if (vfp == NULL)
+ 804137c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041380:	10003826 	beq	r2,zero,8041464 <vfclose_locked+0x154>
+         break;
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfp->method)
+ 8041384:	e0bffd17 	ldw	r2,-12(fp)
+ 8041388:	10800a17 	ldw	r2,40(r2)
+ 804138c:	10000826 	beq	r2,zero,80413b0 <vfclose_locked+0xa0>
+      {
+         /* call that file system's fclose() */
+         struct vfroutines *  vfs   =  (struct  vfroutines*)(vfp->method);
+ 8041390:	e0bffd17 	ldw	r2,-12(fp)
+ 8041394:	10800a17 	ldw	r2,40(r2)
+ 8041398:	e0bffc15 	stw	r2,-16(fp)
+
+         vfs->r_fclose(vfd);
+ 804139c:	e0bffc17 	ldw	r2,-16(fp)
+ 80413a0:	10800217 	ldw	r2,8(r2)
+ 80413a4:	e13ffa17 	ldw	r4,-24(fp)
+ 80413a8:	103ee83a 	callr	r2
+         break;   /* break to list deletion code after end of phoney loop */
+ 80413ac:	00003006 	br	8041470 <vfclose_locked+0x160>
+
+      /* if the buffer containing the data was allocated dynamically, 
+       * and there are VFS_CLOSE_FRAG_FLOOR bytes of unused data 
+       * between the end of the file and the end of the buffer 
+       */
+      if ((vfp->flags & VF_DYNAMICDATA) &&
+ 80413b0:	e0bffd17 	ldw	r2,-12(fp)
+ 80413b4:	1080058b 	ldhu	r2,22(r2)
+ 80413b8:	10bfffcc 	andi	r2,r2,65535
+ 80413bc:	1080200c 	andi	r2,r2,128
+ 80413c0:	10002a26 	beq	r2,zero,804146c <vfclose_locked+0x15c>
+          ((vfp->buf_size - vfp->comp_size) > VFS_CLOSE_FRAG_FLOOR) &&
+ 80413c4:	e0bffd17 	ldw	r2,-12(fp)
+ 80413c8:	10c00917 	ldw	r3,36(r2)
+ 80413cc:	e0bffd17 	ldw	r2,-12(fp)
+ 80413d0:	10800817 	ldw	r2,32(r2)
+ 80413d4:	1885c83a 	sub	r2,r3,r2
+      if ((vfp->flags & VF_DYNAMICDATA) &&
+ 80413d8:	10804030 	cmpltui	r2,r2,256
+ 80413dc:	1000231e 	bne	r2,zero,804146c <vfclose_locked+0x15c>
+          vfp->data) /* this last test is a sanity check */
+ 80413e0:	e0bffd17 	ldw	r2,-12(fp)
+ 80413e4:	10800617 	ldw	r2,24(r2)
+          ((vfp->buf_size - vfp->comp_size) > VFS_CLOSE_FRAG_FLOOR) &&
+ 80413e8:	10002026 	beq	r2,zero,804146c <vfclose_locked+0x15c>
+      {
+         /* try to reclaim the unused data */
+
+         /* allocate a new buffer just big enough for the data */
+         new_buffer = vf_alloc_buffer(vfp->comp_size);
+ 80413ec:	e0bffd17 	ldw	r2,-12(fp)
+ 80413f0:	10800817 	ldw	r2,32(r2)
+ 80413f4:	1009883a 	mov	r4,r2
+ 80413f8:	8040e700 	call	8040e70 <vf_alloc_buffer>
+ 80413fc:	e0bffb15 	stw	r2,-20(fp)
+
+         /* if the allocation worked */
+         if (new_buffer)
+ 8041400:	e0bffb17 	ldw	r2,-20(fp)
+ 8041404:	10001926 	beq	r2,zero,804146c <vfclose_locked+0x15c>
+         {
+            /* copy the old buffer to the new one */
+            MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size));
+ 8041408:	e0bffd17 	ldw	r2,-12(fp)
+ 804140c:	10c00617 	ldw	r3,24(r2)
+ 8041410:	e0bffd17 	ldw	r2,-12(fp)
+ 8041414:	10800817 	ldw	r2,32(r2)
+ 8041418:	100d883a 	mov	r6,r2
+ 804141c:	180b883a 	mov	r5,r3
+ 8041420:	e13ffb17 	ldw	r4,-20(fp)
+ 8041424:	80086b80 	call	80086b8 <memcpy>
+            /* free the old buffer */
+            vf_free_buffer(vfp->data,vfp->buf_size);
+ 8041428:	e0bffd17 	ldw	r2,-12(fp)
+ 804142c:	10c00617 	ldw	r3,24(r2)
+ 8041430:	e0bffd17 	ldw	r2,-12(fp)
+ 8041434:	10800917 	ldw	r2,36(r2)
+ 8041438:	100b883a 	mov	r5,r2
+ 804143c:	1809883a 	mov	r4,r3
+ 8041440:	8040f380 	call	8040f38 <vf_free_buffer>
+            /* update the buffer pointer and size to reflect the
+               just big enough buffer */
+            vfp->data = new_buffer;
+ 8041444:	e0bffd17 	ldw	r2,-12(fp)
+ 8041448:	e0fffb17 	ldw	r3,-20(fp)
+ 804144c:	10c00615 	stw	r3,24(r2)
+            vfp->buf_size = vfp->comp_size;
+ 8041450:	e0bffd17 	ldw	r2,-12(fp)
+ 8041454:	10c00817 	ldw	r3,32(r2)
+ 8041458:	e0bffd17 	ldw	r2,-12(fp)
+ 804145c:	10c00915 	stw	r3,36(r2)
+#endif   /* VFS_AUTO_SYNC */
+
+#endif   /* HT_RWVFS */
+
+      /* break to list deletion code below */
+      break;
+ 8041460:	00000206 	br	804146c <vfclose_locked+0x15c>
+         break;
+ 8041464:	0001883a 	nop
+ 8041468:	00000106 	br	8041470 <vfclose_locked+0x160>
+      break;
+ 804146c:	0001883a 	nop
+
+   }
+
+   if (vlast)  /* unlink from list of open files */
+ 8041470:	e0bffe17 	ldw	r2,-8(fp)
+ 8041474:	10000526 	beq	r2,zero,804148c <vfclose_locked+0x17c>
+      vlast->next = vtmp->next;
+ 8041478:	e0bfff17 	ldw	r2,-4(fp)
+ 804147c:	10c00017 	ldw	r3,0(r2)
+ 8041480:	e0bffe17 	ldw	r2,-8(fp)
+ 8041484:	10c00015 	stw	r3,0(r2)
+ 8041488:	00000306 	br	8041498 <vfclose_locked+0x188>
+   else
+      vfiles = vtmp->next;
+ 804148c:	e0bfff17 	ldw	r2,-4(fp)
+ 8041490:	10800017 	ldw	r2,0(r2)
+ 8041494:	d0a0a215 	stw	r2,-32120(gp)
+
+   /* free structure addressed by open handle */
+   VFS_VFS_OPEN_FREE(vtmp);
+ 8041498:	e13fff17 	ldw	r4,-4(fp)
+ 804149c:	80298600 	call	8029860 <npfree>
+   /* decrement the number of open files */
+   vfs_open_files--;
+ 80414a0:	d0a0a617 	ldw	r2,-32104(gp)
+ 80414a4:	10bfffc4 	addi	r2,r2,-1
+ 80414a8:	d0a0a615 	stw	r2,-32104(gp)
+   return;
+ 80414ac:	0001883a 	nop
+ 80414b0:	00000106 	br	80414b8 <vfclose_locked+0x1a8>
+      return;
+ 80414b4:	0001883a 	nop
+}
+ 80414b8:	e037883a 	mov	sp,fp
+ 80414bc:	dfc00117 	ldw	ra,4(sp)
+ 80414c0:	df000017 	ldw	fp,0(sp)
+ 80414c4:	dec00204 	addi	sp,sp,8
+ 80414c8:	f800283a 	ret
+
+080414cc <vfclose>:
+ *
+ * RETURNS: 
+ */
+
+void vfclose(VFILE * vfd)
+{
+ 80414cc:	defffd04 	addi	sp,sp,-12
+ 80414d0:	dfc00215 	stw	ra,8(sp)
+ 80414d4:	df000115 	stw	fp,4(sp)
+ 80414d8:	df000104 	addi	fp,sp,4
+ 80414dc:	e13fff15 	stw	r4,-4(fp)
+   vfs_lock();
+ 80414e0:	01000144 	movi	r4,5
+ 80414e4:	80292b40 	call	80292b4 <wait_app_sem>
+
+   vfclose_locked(vfd);
+ 80414e8:	e13fff17 	ldw	r4,-4(fp)
+ 80414ec:	80413100 	call	8041310 <vfclose_locked>
+
+   vfs_unlock();
+ 80414f0:	01000144 	movi	r4,5
+ 80414f4:	80293680 	call	8029368 <post_app_sem>
+}
+ 80414f8:	0001883a 	nop
+ 80414fc:	e037883a 	mov	sp,fp
+ 8041500:	dfc00117 	ldw	ra,4(sp)
+ 8041504:	df000017 	ldw	fp,0(sp)
+ 8041508:	dec00204 	addi	sp,sp,8
+ 804150c:	f800283a 	ret
+
+08041510 <vfflush>:
+ *
+ * RETURNS: 
+ */
+
+int vfflush(VFILE * vfd)
+{
+ 8041510:	defffd04 	addi	sp,sp,-12
+ 8041514:	dfc00215 	stw	ra,8(sp)
+ 8041518:	df000115 	stw	fp,4(sp)
+ 804151c:	df000104 	addi	fp,sp,4
+ 8041520:	e13fff15 	stw	r4,-4(fp)
+   vfs_lock();
+ 8041524:	01000144 	movi	r4,5
+ 8041528:	80292b40 	call	80292b4 <wait_app_sem>
+
+   printf("vfflush(): This function needs to be implemented\n");
+ 804152c:	01020174 	movhi	r4,2053
+ 8041530:	212e2804 	addi	r4,r4,-18272
+ 8041534:	8002d9c0 	call	8002d9c <puts>
+
+   vfs_unlock();
+ 8041538:	01000144 	movi	r4,5
+ 804153c:	80293680 	call	8029368 <post_app_sem>
+   return(0);
+ 8041540:	0005883a 	mov	r2,zero
+}
+ 8041544:	e037883a 	mov	sp,fp
+ 8041548:	dfc00117 	ldw	ra,4(sp)
+ 804154c:	df000017 	ldw	fp,0(sp)
+ 8041550:	dec00204 	addi	sp,sp,8
+ 8041554:	f800283a 	ret
+
+08041558 <vfgets>:
+
+char * vfgets(char * s, int lim, VFILE * fp) 
+{
+ 8041558:	defff904 	addi	sp,sp,-28
+ 804155c:	dfc00615 	stw	ra,24(sp)
+ 8041560:	df000515 	stw	fp,20(sp)
+ 8041564:	df000504 	addi	fp,sp,20
+ 8041568:	e13ffd15 	stw	r4,-12(fp)
+ 804156c:	e17ffc15 	stw	r5,-16(fp)
+ 8041570:	e1bffb15 	stw	r6,-20(fp)
+   int   c   = EOF;
+ 8041574:	00bfffc4 	movi	r2,-1
+ 8041578:	e0bfff15 	stw	r2,-4(fp)
+   char* ret = s;
+ 804157c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041580:	e0bffe15 	stw	r2,-8(fp)
+
+   while ( --lim > 0 && (c = vgetc(fp)) != EOF)
+ 8041584:	00000b06 	br	80415b4 <vfgets+0x5c>
+      if (( *ret ++ = c) == '\n')
+ 8041588:	e0bffe17 	ldw	r2,-8(fp)
+ 804158c:	10c00044 	addi	r3,r2,1
+ 8041590:	e0fffe15 	stw	r3,-8(fp)
+ 8041594:	e0ffff17 	ldw	r3,-4(fp)
+ 8041598:	10c00005 	stb	r3,0(r2)
+ 804159c:	10800003 	ldbu	r2,0(r2)
+ 80415a0:	10803fcc 	andi	r2,r2,255
+ 80415a4:	1080201c 	xori	r2,r2,128
+ 80415a8:	10bfe004 	addi	r2,r2,-128
+ 80415ac:	10800298 	cmpnei	r2,r2,10
+ 80415b0:	10000c26 	beq	r2,zero,80415e4 <vfgets+0x8c>
+   while ( --lim > 0 && (c = vgetc(fp)) != EOF)
+ 80415b4:	e0bffc17 	ldw	r2,-16(fp)
+ 80415b8:	10bfffc4 	addi	r2,r2,-1
+ 80415bc:	e0bffc15 	stw	r2,-16(fp)
+ 80415c0:	e0bffc17 	ldw	r2,-16(fp)
+ 80415c4:	0080080e 	bge	zero,r2,80415e8 <vfgets+0x90>
+ 80415c8:	e13ffb17 	ldw	r4,-20(fp)
+ 80415cc:	80421c00 	call	80421c0 <vgetc>
+ 80415d0:	e0bfff15 	stw	r2,-4(fp)
+ 80415d4:	e0bfff17 	ldw	r2,-4(fp)
+ 80415d8:	10bfffd8 	cmpnei	r2,r2,-1
+ 80415dc:	103fea1e 	bne	r2,zero,8041588 <vfgets+0x30>
+ 80415e0:	00000106 	br	80415e8 <vfgets+0x90>
+         break;
+ 80415e4:	0001883a 	nop
+   *ret = '\0';
+ 80415e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80415ec:	10000005 	stb	zero,0(r2)
+   return ( c == EOF && ret == s) ? NULL : s;
+ 80415f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80415f4:	10bfffd8 	cmpnei	r2,r2,-1
+ 80415f8:	1000031e 	bne	r2,zero,8041608 <vfgets+0xb0>
+ 80415fc:	e0fffe17 	ldw	r3,-8(fp)
+ 8041600:	e0bffd17 	ldw	r2,-12(fp)
+ 8041604:	18800226 	beq	r3,r2,8041610 <vfgets+0xb8>
+ 8041608:	e0bffd17 	ldw	r2,-12(fp)
+ 804160c:	00000106 	br	8041614 <vfgets+0xbc>
+ 8041610:	0005883a 	mov	r2,zero
+}
+ 8041614:	e037883a 	mov	sp,fp
+ 8041618:	dfc00117 	ldw	ra,4(sp)
+ 804161c:	df000017 	ldw	fp,0(sp)
+ 8041620:	dec00204 	addi	sp,sp,8
+ 8041624:	f800283a 	ret
+
+08041628 <vfeof>:
+ *
+ * RETURNS: 1 if the file pointer is at EOF, otherwise 0
+ */
+ 
+int vfeof(VFILE * vfd)
+{
+ 8041628:	defffc04 	addi	sp,sp,-16
+ 804162c:	dfc00315 	stw	ra,12(sp)
+ 8041630:	df000215 	stw	fp,8(sp)
+ 8041634:	df000204 	addi	fp,sp,8
+ 8041638:	e13ffe15 	stw	r4,-8(fp)
+   int c = 0;
+ 804163c:	e03fff15 	stw	zero,-4(fp)
+
+#ifdef HT_LOCALFS
+   return(feof((FILE*)vfd));
+#endif
+   if ((c = vgetc(vfd)) == EOF )
+ 8041640:	e13ffe17 	ldw	r4,-8(fp)
+ 8041644:	80421c00 	call	80421c0 <vgetc>
+ 8041648:	e0bfff15 	stw	r2,-4(fp)
+ 804164c:	e0bfff17 	ldw	r2,-4(fp)
+ 8041650:	10bfffd8 	cmpnei	r2,r2,-1
+ 8041654:	1000021e 	bne	r2,zero,8041660 <vfeof+0x38>
+   {
+      return 1;
+ 8041658:	00800044 	movi	r2,1
+ 804165c:	00000106 	br	8041664 <vfeof+0x3c>
+   }   
+   return 0;
+ 8041660:	0005883a 	mov	r2,zero
+}
+ 8041664:	e037883a 	mov	sp,fp
+ 8041668:	dfc00117 	ldw	ra,4(sp)
+ 804166c:	df000017 	ldw	fp,0(sp)
+ 8041670:	dec00204 	addi	sp,sp,8
+ 8041674:	f800283a 	ret
+
+08041678 <vunlink_flag_open_files>:
+ *
+ * RETURNS: 
+ */
+
+void vunlink_flag_open_files(struct vfs_file * vfp)
+{
+ 8041678:	defffd04 	addi	sp,sp,-12
+ 804167c:	df000215 	stw	fp,8(sp)
+ 8041680:	df000204 	addi	fp,sp,8
+ 8041684:	e13ffe15 	stw	r4,-8(fp)
+   VFILE * vtmp;
+
+   /* for all open files */
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+ 8041688:	d0a0a217 	ldw	r2,-32120(gp)
+ 804168c:	e0bfff15 	stw	r2,-4(fp)
+ 8041690:	00000906 	br	80416b8 <vunlink_flag_open_files+0x40>
+   {
+      /* if the open file handle is referencing the file we are
+         deleting, set that reference to NULL */
+      if (vtmp->file == vfp)
+ 8041694:	e0bfff17 	ldw	r2,-4(fp)
+ 8041698:	10800117 	ldw	r2,4(r2)
+ 804169c:	e0fffe17 	ldw	r3,-8(fp)
+ 80416a0:	1880021e 	bne	r3,r2,80416ac <vunlink_flag_open_files+0x34>
+         vtmp->file = NULL;
+ 80416a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80416a8:	10000115 	stw	zero,4(r2)
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+ 80416ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80416b0:	10800017 	ldw	r2,0(r2)
+ 80416b4:	e0bfff15 	stw	r2,-4(fp)
+ 80416b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80416bc:	103ff51e 	bne	r2,zero,8041694 <vunlink_flag_open_files+0x1c>
+   }
+}
+ 80416c0:	0001883a 	nop
+ 80416c4:	e037883a 	mov	sp,fp
+ 80416c8:	df000017 	ldw	fp,0(sp)
+ 80416cc:	dec00104 	addi	sp,sp,4
+ 80416d0:	f800283a 	ret
+
+080416d4 <vunlink>:
+ * Change prototype from char * name to const char to
+ * follow C library standard.
+ */
+int
+vunlink(const char * const_name)
+{
+ 80416d4:	defff604 	addi	sp,sp,-40
+ 80416d8:	dfc00915 	stw	ra,36(sp)
+ 80416dc:	df000815 	stw	fp,32(sp)
+ 80416e0:	df000804 	addi	fp,sp,32
+ 80416e4:	e13ff815 	stw	r4,-32(fp)
+   struct vfs_file * vfp;
+   int   rc =  0;
+ 80416e8:	e03fff15 	stw	zero,-4(fp)
+/*
+ * Altera Niche Stack Nios port modification:
+ * Change prototype from char * name to const char to
+ * follow C library standard.
+ */
+   char * name = malloc(strlen(const_name)+1);
+ 80416ec:	e13ff817 	ldw	r4,-32(fp)
+ 80416f0:	8002dac0 	call	8002dac <strlen>
+ 80416f4:	10800044 	addi	r2,r2,1
+ 80416f8:	1009883a 	mov	r4,r2
+ 80416fc:	8042c980 	call	8042c98 <malloc>
+ 8041700:	e0bffc15 	stw	r2,-16(fp)
+   strcpy(name, const_name);
+ 8041704:	e17ff817 	ldw	r5,-32(fp)
+ 8041708:	e13ffc17 	ldw	r4,-16(fp)
+ 804170c:	8042f600 	call	8042f60 <strcpy>
+   if (vfs_log_file_name)
+      dprintf("vunlink() passed >%s<\n",name);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+ 8041710:	01000144 	movi	r4,5
+ 8041714:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* see if the converted name is one of the one's in our list */
+   /* if it isn't */
+   if ((vfp = vfslookup_locked(name)) == NULL)
+ 8041718:	e13ffc17 	ldw	r4,-16(fp)
+ 804171c:	80422080 	call	8042208 <vfslookup_locked>
+ 8041720:	e0bffb15 	stw	r2,-20(fp)
+ 8041724:	e0bffb17 	ldw	r2,-20(fp)
+ 8041728:	1000061e 	bne	r2,zero,8041744 <vunlink+0x70>
+   {
+      vfs_unlock();
+ 804172c:	01000144 	movi	r4,5
+ 8041730:	80293680 	call	8029368 <post_app_sem>
+#ifdef HT_LOCALFS
+      /* default to call on local system */
+      return remove(name);
+#else
+      /* no local file system, so return error condition */
+      free(name);
+ 8041734:	e13ffc17 	ldw	r4,-16(fp)
+ 8041738:	8042ca80 	call	8042ca8 <free>
+      return -1;
+ 804173c:	00bfffc4 	movi	r2,-1
+ 8041740:	00005f06 	br	80418c0 <vunlink+0x1ec>
+#ifdef   HT_RWVFS
+   /* save the next link pointer since in one path through the code, 
+    * the vfs_file structure gets freed before its unlinked from the 
+    * list
+    */
+   vfnext = vfp->next;
+ 8041744:	e0bffb17 	ldw	r2,-20(fp)
+ 8041748:	10800017 	ldw	r2,0(r2)
+ 804174c:	e0bffa15 	stw	r2,-24(fp)
+
+   /* search list of files to determine predecessor in list */
+   vflast = NULL;
+ 8041750:	e03ffd15 	stw	zero,-12(fp)
+   for (vtmp = vfsfiles; vtmp != NULL; vtmp = vtmp->next)
+ 8041754:	d0a0a317 	ldw	r2,-32116(gp)
+ 8041758:	e0bffe15 	stw	r2,-8(fp)
+ 804175c:	00000806 	br	8041780 <vunlink+0xac>
+   {
+      if (vtmp == vfp)
+ 8041760:	e0fffe17 	ldw	r3,-8(fp)
+ 8041764:	e0bffb17 	ldw	r2,-20(fp)
+ 8041768:	18800826 	beq	r3,r2,804178c <vunlink+0xb8>
+         break;
+      vflast = vtmp;
+ 804176c:	e0bffe17 	ldw	r2,-8(fp)
+ 8041770:	e0bffd15 	stw	r2,-12(fp)
+   for (vtmp = vfsfiles; vtmp != NULL; vtmp = vtmp->next)
+ 8041774:	e0bffe17 	ldw	r2,-8(fp)
+ 8041778:	10800017 	ldw	r2,0(r2)
+ 804177c:	e0bffe15 	stw	r2,-8(fp)
+ 8041780:	e0bffe17 	ldw	r2,-8(fp)
+ 8041784:	103ff61e 	bne	r2,zero,8041760 <vunlink+0x8c>
+ 8041788:	00000106 	br	8041790 <vunlink+0xbc>
+         break;
+ 804178c:	0001883a 	nop
+   }
+
+   /* this shouldn't happen since vfslookup_locked() already searched
+      the list, but just in case */
+   if (vtmp == NULL)
+ 8041790:	e0bffe17 	ldw	r2,-8(fp)
+ 8041794:	1000071e 	bne	r2,zero,80417b4 <vunlink+0xe0>
+   {
+      dtrap();
+ 8041798:	8028cd40 	call	8028cd4 <dtrap>
+      vfs_unlock();
+ 804179c:	01000144 	movi	r4,5
+ 80417a0:	80293680 	call	8029368 <post_app_sem>
+      free(name);
+ 80417a4:	e13ffc17 	ldw	r4,-16(fp)
+ 80417a8:	8042ca80 	call	8042ca8 <free>
+      return -1;
+ 80417ac:	00bfffc4 	movi	r2,-1
+ 80417b0:	00004306 	br	80418c0 <vunlink+0x1ec>
+   while (1)
+   {
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfp->method)
+ 80417b4:	e0bffb17 	ldw	r2,-20(fp)
+ 80417b8:	10800a17 	ldw	r2,40(r2)
+ 80417bc:	10000926 	beq	r2,zero,80417e4 <vunlink+0x110>
+      {
+         /* call that file system's unlink() */
+         struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfp->method);
+ 80417c0:	e0bffb17 	ldw	r2,-20(fp)
+ 80417c4:	10800a17 	ldw	r2,40(r2)
+ 80417c8:	e0bff915 	stw	r2,-28(fp)
+
+         rc = vfs->r_unlink(name);
+ 80417cc:	e0bff917 	ldw	r2,-28(fp)
+ 80417d0:	10800817 	ldw	r2,32(r2)
+ 80417d4:	e13ffc17 	ldw	r4,-16(fp)
+ 80417d8:	103ee83a 	callr	r2
+ 80417dc:	e0bfff15 	stw	r2,-4(fp)
+         break;   /* break to list deletion code after end of phoney loop */
+ 80417e0:	00002606 	br	804187c <vunlink+0x1a8>
+      }
+#endif   /* HT_EXTDEV */
+
+      /* if the file is not write enabled, return error condition */
+      if (!(vfp->flags & VF_WRITE))
+ 80417e4:	e0bffb17 	ldw	r2,-20(fp)
+ 80417e8:	1080058b 	ldhu	r2,22(r2)
+ 80417ec:	10bfffcc 	andi	r2,r2,65535
+ 80417f0:	1080080c 	andi	r2,r2,32
+ 80417f4:	1000061e 	bne	r2,zero,8041810 <vunlink+0x13c>
+      {
+         vfs_unlock();
+ 80417f8:	01000144 	movi	r4,5
+ 80417fc:	80293680 	call	8029368 <post_app_sem>
+         free(name);
+ 8041800:	e13ffc17 	ldw	r4,-16(fp)
+ 8041804:	8042ca80 	call	8042ca8 <free>
+         return -1;
+ 8041808:	00bfffc4 	movi	r2,-1
+ 804180c:	00002c06 	br	80418c0 <vunlink+0x1ec>
+      }
+
+      /* if the data buffer containing the file's data was dynamically
+         allocated and is not null */
+      if ((vfp->flags & VF_DYNAMICDATA) && (vfp->data))
+ 8041810:	e0bffb17 	ldw	r2,-20(fp)
+ 8041814:	1080058b 	ldhu	r2,22(r2)
+ 8041818:	10bfffcc 	andi	r2,r2,65535
+ 804181c:	1080200c 	andi	r2,r2,128
+ 8041820:	10000a26 	beq	r2,zero,804184c <vunlink+0x178>
+ 8041824:	e0bffb17 	ldw	r2,-20(fp)
+ 8041828:	10800617 	ldw	r2,24(r2)
+ 804182c:	10000726 	beq	r2,zero,804184c <vunlink+0x178>
+      {
+         /* free the buffer */
+         vf_free_buffer(vfp->data,vfp->buf_size);
+ 8041830:	e0bffb17 	ldw	r2,-20(fp)
+ 8041834:	10c00617 	ldw	r3,24(r2)
+ 8041838:	e0bffb17 	ldw	r2,-20(fp)
+ 804183c:	10800917 	ldw	r2,36(r2)
+ 8041840:	100b883a 	mov	r5,r2
+ 8041844:	1809883a 	mov	r4,r3
+ 8041848:	8040f380 	call	8040f38 <vf_free_buffer>
+      }
+
+      /* if the vfs_file structure itself was allocated dynamically */
+      if (vfp->flags & VF_DYNAMICINFO)
+ 804184c:	e0bffb17 	ldw	r2,-20(fp)
+ 8041850:	1080058b 	ldhu	r2,22(r2)
+ 8041854:	10bfffcc 	andi	r2,r2,65535
+ 8041858:	1080100c 	andi	r2,r2,64
+ 804185c:	10000526 	beq	r2,zero,8041874 <vunlink+0x1a0>
+      {
+         /* decrement count of total files */
+         vfs_total_dyna_files--;
+ 8041860:	d0a0a817 	ldw	r2,-32096(gp)
+ 8041864:	10bfffc4 	addi	r2,r2,-1
+ 8041868:	d0a0a815 	stw	r2,-32096(gp)
+
+         /* free the vfs_file structure */
+         VFS_VFS_FILE_FREE(vfp);
+ 804186c:	e13ffb17 	ldw	r4,-20(fp)
+ 8041870:	80298600 	call	8029860 <npfree>
+         the vfs_file has been deleted from the list */
+#ifdef VFS_AUTO_SYNC
+      do_sync = 1;
+#endif
+      /* we were successful at our unlink */
+      rc = 0;
+ 8041874:	e03fff15 	stw	zero,-4(fp)
+
+      break;
+ 8041878:	0001883a 	nop
+   }
+
+   /* delete the vfs_file structure from the list headed by vfsfiles */
+   if (vflast)
+ 804187c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041880:	10000426 	beq	r2,zero,8041894 <vunlink+0x1c0>
+      vflast->next = vfnext;
+ 8041884:	e0bffd17 	ldw	r2,-12(fp)
+ 8041888:	e0fffa17 	ldw	r3,-24(fp)
+ 804188c:	10c00015 	stw	r3,0(r2)
+ 8041890:	00000206 	br	804189c <vunlink+0x1c8>
+   else
+      vfsfiles = vfnext;
+ 8041894:	e0bffa17 	ldw	r2,-24(fp)
+ 8041898:	d0a0a315 	stw	r2,-32116(gp)
+
+   /* fix up references to deleted file in list of currently open VFILEs */
+   vunlink_flag_open_files(vfp);
+ 804189c:	e13ffb17 	ldw	r4,-20(fp)
+ 80418a0:	80416780 	call	8041678 <vunlink_flag_open_files>
+
+   /* flag that the directory is stale so vfs_sync() knows it has to do
+      something */
+   vfs_dir_stale = TRUE;
+ 80418a4:	00800044 	movi	r2,1
+ 80418a8:	d0a0a515 	stw	r2,-32108(gp)
+
+   /* unlinks not allowed on read-only VFS */
+   rc = -1;
+
+#endif   /* HT_RWVFS */
+   vfs_unlock();
+ 80418ac:	01000144 	movi	r4,5
+ 80418b0:	80293680 	call	8029368 <post_app_sem>
+   free(name);
+ 80418b4:	e13ffc17 	ldw	r4,-16(fp)
+ 80418b8:	8042ca80 	call	8042ca8 <free>
+   return rc;
+ 80418bc:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80418c0:	e037883a 	mov	sp,fp
+ 80418c4:	dfc00117 	ldw	ra,4(sp)
+ 80418c8:	df000017 	ldw	fp,0(sp)
+ 80418cc:	dec00204 	addi	sp,sp,8
+ 80418d0:	f800283a 	ret
+
+080418d4 <vfread>:
+ * RETURNS: 
+ */
+
+int 
+vfread(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+ 80418d4:	defff604 	addi	sp,sp,-40
+ 80418d8:	dfc00915 	stw	ra,36(sp)
+ 80418dc:	df000815 	stw	fp,32(sp)
+ 80418e0:	df000804 	addi	fp,sp,32
+ 80418e4:	e13ffb15 	stw	r4,-20(fp)
+ 80418e8:	e17ffa15 	stw	r5,-24(fp)
+ 80418ec:	e1bff915 	stw	r6,-28(fp)
+ 80418f0:	e1fff815 	stw	r7,-32(fp)
+   unsigned bcount;  /* number of bytes put in caller's buffer */
+
+   IN_PROFILER(PF_FS, PF_ENTRY);
+
+   /* lock the VFS */
+   vfs_lock();
+ 80418f4:	01000144 	movi	r4,5
+ 80418f8:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* if the file is in our list of open files */
+   if (isvfile_locked(vfd))
+ 80418fc:	e13ff817 	ldw	r4,-32(fp)
+ 8041900:	80425400 	call	8042540 <isvfile_locked>
+ 8041904:	10004d26 	beq	r2,zero,8041a3c <vfread+0x168>
+   {
+
+#ifdef HT_RWVFS
+      /* the caller is trying to read a handle to a file that's been
+         deleted, so he gets 0 data back */
+      if (vfd->file == NULL)
+ 8041908:	e0bff817 	ldw	r2,-32(fp)
+ 804190c:	10800117 	ldw	r2,4(r2)
+ 8041910:	1000041e 	bne	r2,zero,8041924 <vfread+0x50>
+      {
+         vfs_unlock();
+ 8041914:	01000144 	movi	r4,5
+ 8041918:	80293680 	call	8029368 <post_app_sem>
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return 0;
+ 804191c:	0005883a 	mov	r2,zero
+ 8041920:	00004906 	br	8041a48 <vfread+0x174>
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfd->file->method)
+ 8041924:	e0bff817 	ldw	r2,-32(fp)
+ 8041928:	10800117 	ldw	r2,4(r2)
+ 804192c:	10800a17 	ldw	r2,40(r2)
+ 8041930:	10001026 	beq	r2,zero,8041974 <vfread+0xa0>
+      {
+         struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfd->file->method);
+ 8041934:	e0bff817 	ldw	r2,-32(fp)
+ 8041938:	10800117 	ldw	r2,4(r2)
+ 804193c:	10800a17 	ldw	r2,40(r2)
+ 8041940:	e0bffe15 	stw	r2,-8(fp)
+         int   rc;
+
+         /* call that system's fread() */
+         rc = vfs->r_fread(buf,size,items,vfd);
+ 8041944:	e0bffe17 	ldw	r2,-8(fp)
+ 8041948:	10800317 	ldw	r2,12(r2)
+ 804194c:	e1fff817 	ldw	r7,-32(fp)
+ 8041950:	e1bff917 	ldw	r6,-28(fp)
+ 8041954:	e17ffa17 	ldw	r5,-24(fp)
+ 8041958:	e13ffb17 	ldw	r4,-20(fp)
+ 804195c:	103ee83a 	callr	r2
+ 8041960:	e0bffd15 	stw	r2,-12(fp)
+         vfs_unlock();
+ 8041964:	01000144 	movi	r4,5
+ 8041968:	80293680 	call	8029368 <post_app_sem>
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return rc;
+ 804196c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041970:	00003506 	br	8041a48 <vfread+0x174>
+#ifdef HT_RWVFS
+      /* the data pointer can be NULL if somebody tries to read from 
+       * a freshly created file, in which case there is no data in 
+       * the file, so return 0
+       */
+      if (!(vfd->file->data))
+ 8041974:	e0bff817 	ldw	r2,-32(fp)
+ 8041978:	10800117 	ldw	r2,4(r2)
+ 804197c:	10800617 	ldw	r2,24(r2)
+ 8041980:	1000041e 	bne	r2,zero,8041994 <vfread+0xc0>
+      {
+         vfs_unlock();
+ 8041984:	01000144 	movi	r4,5
+ 8041988:	80293680 	call	8029368 <post_app_sem>
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return 0;
+ 804198c:	0005883a 	mov	r2,zero
+ 8041990:	00002d06 	br	8041a48 <vfread+0x174>
+      }
+#endif   /* HT_RWVFS */
+
+      bcount = items * size;  /* number of bytes to transfer */
+ 8041994:	e0fff917 	ldw	r3,-28(fp)
+ 8041998:	e0bffa17 	ldw	r2,-24(fp)
+ 804199c:	1885383a 	mul	r2,r3,r2
+ 80419a0:	e0bfff15 	stw	r2,-4(fp)
+         return(items); /* filled user buffer, return # items copied */
+      }
+      else  /* else fall to faster non-compression code */
+#endif   /* HTML_COMPRESSION */
+      {  /* get here to do simple uncompressed data read */
+         unsigned location = vfd->cmploc - vfd->file->data;
+ 80419a4:	e0bff817 	ldw	r2,-32(fp)
+ 80419a8:	10c00217 	ldw	r3,8(r2)
+ 80419ac:	e0bff817 	ldw	r2,-32(fp)
+ 80419b0:	10800117 	ldw	r2,4(r2)
+ 80419b4:	10800617 	ldw	r2,24(r2)
+ 80419b8:	1885c83a 	sub	r2,r3,r2
+ 80419bc:	e0bffc15 	stw	r2,-16(fp)
+
+         if (((unsigned long)location + bcount) > vfd->file->comp_size)
+ 80419c0:	e0fffc17 	ldw	r3,-16(fp)
+ 80419c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80419c8:	1885883a 	add	r2,r3,r2
+ 80419cc:	e0fff817 	ldw	r3,-32(fp)
+ 80419d0:	18c00117 	ldw	r3,4(r3)
+ 80419d4:	18c00817 	ldw	r3,32(r3)
+ 80419d8:	1880062e 	bgeu	r3,r2,80419f4 <vfread+0x120>
+            bcount = (unsigned)(vfd->file->comp_size - location);
+ 80419dc:	e0bff817 	ldw	r2,-32(fp)
+ 80419e0:	10800117 	ldw	r2,4(r2)
+ 80419e4:	10c00817 	ldw	r3,32(r2)
+ 80419e8:	e0bffc17 	ldw	r2,-16(fp)
+ 80419ec:	1885c83a 	sub	r2,r3,r2
+ 80419f0:	e0bfff15 	stw	r2,-4(fp)
+         MEMCPY(buf, vfd->cmploc, bcount);
+ 80419f4:	e0bff817 	ldw	r2,-32(fp)
+ 80419f8:	10800217 	ldw	r2,8(r2)
+ 80419fc:	e1bfff17 	ldw	r6,-4(fp)
+ 8041a00:	100b883a 	mov	r5,r2
+ 8041a04:	e13ffb17 	ldw	r4,-20(fp)
+ 8041a08:	80086b80 	call	80086b8 <memcpy>
+         vfd->cmploc += bcount;
+ 8041a0c:	e0bff817 	ldw	r2,-32(fp)
+ 8041a10:	10c00217 	ldw	r3,8(r2)
+ 8041a14:	e0bfff17 	ldw	r2,-4(fp)
+ 8041a18:	1887883a 	add	r3,r3,r2
+ 8041a1c:	e0bff817 	ldw	r2,-32(fp)
+ 8041a20:	10c00215 	stw	r3,8(r2)
+      }
+      vfs_unlock();
+ 8041a24:	01000144 	movi	r4,5
+ 8041a28:	80293680 	call	8029368 <post_app_sem>
+      IN_PROFILER(PF_FS, PF_EXIT);
+      return (bcount/size);
+ 8041a2c:	e17ffa17 	ldw	r5,-24(fp)
+ 8041a30:	e13fff17 	ldw	r4,-4(fp)
+ 8041a34:	800cff80 	call	800cff8 <__udivsi3>
+ 8041a38:	00000306 	br	8041a48 <vfread+0x174>
+   }
+
+   vfs_unlock();
+ 8041a3c:	01000144 	movi	r4,5
+ 8041a40:	80293680 	call	8029368 <post_app_sem>
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(fread(buf, size, items, (FILE*)vfd));
+#else
+   return 0;
+ 8041a44:	0005883a 	mov	r2,zero
+#endif   /* HT_LOCALFS */
+}
+ 8041a48:	e037883a 	mov	sp,fp
+ 8041a4c:	dfc00117 	ldw	ra,4(sp)
+ 8041a50:	df000017 	ldw	fp,0(sp)
+ 8041a54:	dec00204 	addi	sp,sp,8
+ 8041a58:	f800283a 	ret
+
+08041a5c <vfwrite_locked>:
+ * RETURNS: 
+ */
+
+int 
+vfwrite_locked(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+ 8041a5c:	defff204 	addi	sp,sp,-56
+ 8041a60:	dfc00d15 	stw	ra,52(sp)
+ 8041a64:	df000c15 	stw	fp,48(sp)
+ 8041a68:	df000c04 	addi	fp,sp,48
+ 8041a6c:	e13ff715 	stw	r4,-36(fp)
+ 8041a70:	e17ff615 	stw	r5,-40(fp)
+ 8041a74:	e1bff515 	stw	r6,-44(fp)
+ 8041a78:	e1fff415 	stw	r7,-48(fp)
+   unsigned long current_offset;
+   struct vfs_file * vfp;
+#endif   /* HT_RWVFS */
+
+   /* if the file is not in our list of files */
+   if (!isvfile_locked(vfd))
+ 8041a7c:	e13ff417 	ldw	r4,-48(fp)
+ 8041a80:	80425400 	call	8042540 <isvfile_locked>
+ 8041a84:	1000021e 	bne	r2,zero,8041a90 <vfwrite_locked+0x34>
+   {
+#ifdef HT_LOCALFS
+      /* default to call on local system */
+      return(fwrite(buf, size, items, (FILE*)vfd));
+#else
+      return EBADF;
+ 8041a88:	00800244 	movi	r2,9
+ 8041a8c:	0000d906 	br	8041df4 <vfwrite_locked+0x398>
+   }
+   /* this file is in our list of files */
+
+#ifdef HT_EXTDEV
+   /* if the file was created by an external file system */
+   if (vfd->file->method)
+ 8041a90:	e0bff417 	ldw	r2,-48(fp)
+ 8041a94:	10800117 	ldw	r2,4(r2)
+ 8041a98:	10800a17 	ldw	r2,40(r2)
+ 8041a9c:	10000e26 	beq	r2,zero,8041ad8 <vfwrite_locked+0x7c>
+   {
+      struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfd->file->method);
+ 8041aa0:	e0bff417 	ldw	r2,-48(fp)
+ 8041aa4:	10800117 	ldw	r2,4(r2)
+ 8041aa8:	10800a17 	ldw	r2,40(r2)
+ 8041aac:	e0bfff15 	stw	r2,-4(fp)
+      int   rc;
+
+      /* call that system's fwrite() */
+      rc = vfs->r_fwrite(buf,size,items,vfd);
+ 8041ab0:	e0bfff17 	ldw	r2,-4(fp)
+ 8041ab4:	10800417 	ldw	r2,16(r2)
+ 8041ab8:	e1fff417 	ldw	r7,-48(fp)
+ 8041abc:	e1bff517 	ldw	r6,-44(fp)
+ 8041ac0:	e17ff617 	ldw	r5,-40(fp)
+ 8041ac4:	e13ff717 	ldw	r4,-36(fp)
+ 8041ac8:	103ee83a 	callr	r2
+ 8041acc:	e0bffe15 	stw	r2,-8(fp)
+      return rc;
+ 8041ad0:	e0bffe17 	ldw	r2,-8(fp)
+ 8041ad4:	0000c706 	br	8041df4 <vfwrite_locked+0x398>
+
+#else    /* HT_RWVFS */
+
+   /* the caller is trying to write to a file that's been deleted,
+      so he writes 0 data */
+   if (vfd->file == NULL)
+ 8041ad8:	e0bff417 	ldw	r2,-48(fp)
+ 8041adc:	10800117 	ldw	r2,4(r2)
+ 8041ae0:	1000021e 	bne	r2,zero,8041aec <vfwrite_locked+0x90>
+   {
+      return 0;
+ 8041ae4:	0005883a 	mov	r2,zero
+ 8041ae8:	0000c206 	br	8041df4 <vfwrite_locked+0x398>
+   }
+
+   vfp = vfd->file;
+ 8041aec:	e0bff417 	ldw	r2,-48(fp)
+ 8041af0:	10800117 	ldw	r2,4(r2)
+ 8041af4:	e0bffd15 	stw	r2,-12(fp)
+
+   /* if the file is not writable, return error condition */
+   if (!(vfp->flags & VF_WRITE))
+ 8041af8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041afc:	1080058b 	ldhu	r2,22(r2)
+ 8041b00:	10bfffcc 	andi	r2,r2,65535
+ 8041b04:	1080080c 	andi	r2,r2,32
+ 8041b08:	1000051e 	bne	r2,zero,8041b20 <vfwrite_locked+0xc4>
+   {
+      vfd->error = ENP_FILEIO;
+ 8041b0c:	e0bff417 	ldw	r2,-48(fp)
+ 8041b10:	00fff984 	movi	r3,-26
+ 8041b14:	10c00415 	stw	r3,16(r2)
+      return 0;
+ 8041b18:	0005883a 	mov	r2,zero
+ 8041b1c:	0000b506 	br	8041df4 <vfwrite_locked+0x398>
+   }
+
+   /* compute number of bytes to write */
+   bcount = size * items;
+ 8041b20:	e0fff617 	ldw	r3,-40(fp)
+ 8041b24:	e0bff517 	ldw	r2,-44(fp)
+ 8041b28:	1885383a 	mul	r2,r3,r2
+ 8041b2c:	e0bffc15 	stw	r2,-16(fp)
+
+   /* get rid of this degenerate case up front */
+   if (bcount == 0)
+ 8041b30:	e0bffc17 	ldw	r2,-16(fp)
+ 8041b34:	1000021e 	bne	r2,zero,8041b40 <vfwrite_locked+0xe4>
+   {
+      return 0;
+ 8041b38:	0005883a 	mov	r2,zero
+ 8041b3c:	0000ad06 	br	8041df4 <vfwrite_locked+0x398>
+   }
+
+   /* if the file currently has no data buffer */
+   if (vfp->data == NULL)
+ 8041b40:	e0bffd17 	ldw	r2,-12(fp)
+ 8041b44:	10800617 	ldw	r2,24(r2)
+ 8041b48:	10003d1e 	bne	r2,zero,8041c40 <vfwrite_locked+0x1e4>
+   {
+      /* compute the size of the buffer to be created */
+      /* we round up the size of the data to be written so we dont have
+         the overhead of a memory allocation on every write */
+      unsigned long buf_size = VFS_ROUND_UP((unsigned long)bcount);
+ 8041b4c:	e0bffc17 	ldw	r2,-16(fp)
+ 8041b50:	10ffffc4 	addi	r3,r2,-1
+ 8041b54:	00b80004 	movi	r2,-8192
+ 8041b58:	1884703a 	and	r2,r3,r2
+ 8041b5c:	10880004 	addi	r2,r2,8192
+ 8041b60:	e0bffb15 	stw	r2,-20(fp)
+
+      /* allocate a buffer of that size */
+      vfp->data = vf_alloc_buffer(buf_size);
+ 8041b64:	e13ffb17 	ldw	r4,-20(fp)
+ 8041b68:	8040e700 	call	8040e70 <vf_alloc_buffer>
+ 8041b6c:	1007883a 	mov	r3,r2
+ 8041b70:	e0bffd17 	ldw	r2,-12(fp)
+ 8041b74:	10c00615 	stw	r3,24(r2)
+
+      /* if the allocation failed */
+      if (!(vfp->data))
+ 8041b78:	e0bffd17 	ldw	r2,-12(fp)
+ 8041b7c:	10800617 	ldw	r2,24(r2)
+ 8041b80:	1000051e 	bne	r2,zero,8041b98 <vfwrite_locked+0x13c>
+      {
+         vfd->error = ENP_NOMEM;
+ 8041b84:	e0bff417 	ldw	r2,-48(fp)
+ 8041b88:	00fffb04 	movi	r3,-20
+ 8041b8c:	10c00415 	stw	r3,16(r2)
+         return 0;
+ 8041b90:	0005883a 	mov	r2,zero
+ 8041b94:	00009706 	br	8041df4 <vfwrite_locked+0x398>
+      }
+
+      /* store the size of the allocated buffer */
+      vfp->buf_size = buf_size;
+ 8041b98:	e0bffd17 	ldw	r2,-12(fp)
+ 8041b9c:	e0fffb17 	ldw	r3,-20(fp)
+ 8041ba0:	10c00915 	stw	r3,36(r2)
+
+      /* store the number of bytes written in the real and compressed
+         file sizes */
+      vfp->real_size = bcount;
+ 8041ba4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041ba8:	e0fffc17 	ldw	r3,-16(fp)
+ 8041bac:	10c00715 	stw	r3,28(r2)
+      vfp->comp_size = bcount;
+ 8041bb0:	e0bffd17 	ldw	r2,-12(fp)
+ 8041bb4:	e0fffc17 	ldw	r3,-16(fp)
+ 8041bb8:	10c00815 	stw	r3,32(r2)
+
+      /* set the file pointer to the first byte following the last
+         byte written */
+      vfd->cmploc = vfp->data + bcount;
+ 8041bbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8041bc0:	10c00617 	ldw	r3,24(r2)
+ 8041bc4:	e0bffc17 	ldw	r2,-16(fp)
+ 8041bc8:	1887883a 	add	r3,r3,r2
+ 8041bcc:	e0bff417 	ldw	r2,-48(fp)
+ 8041bd0:	10c00215 	stw	r3,8(r2)
+
+      /* turn off the compression flag */
+      vfp->flags &= ~VF_HTMLCOMPRESSED;
+ 8041bd4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041bd8:	10c0058b 	ldhu	r3,22(r2)
+ 8041bdc:	00bfff84 	movi	r2,-2
+ 8041be0:	1884703a 	and	r2,r3,r2
+ 8041be4:	1007883a 	mov	r3,r2
+ 8041be8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041bec:	10c0058d 	sth	r3,22(r2)
+
+      /* the data in the file is stale */
+      vfp->flags |= VF_STALE;
+ 8041bf0:	e0bffd17 	ldw	r2,-12(fp)
+ 8041bf4:	1080058b 	ldhu	r2,22(r2)
+ 8041bf8:	10808014 	ori	r2,r2,512
+ 8041bfc:	1007883a 	mov	r3,r2
+ 8041c00:	e0bffd17 	ldw	r2,-12(fp)
+ 8041c04:	10c0058d 	sth	r3,22(r2)
+
+      /* the buffer data was dynamically allocated */
+      vfp->flags |= VF_DYNAMICDATA;
+ 8041c08:	e0bffd17 	ldw	r2,-12(fp)
+ 8041c0c:	1080058b 	ldhu	r2,22(r2)
+ 8041c10:	10802014 	ori	r2,r2,128
+ 8041c14:	1007883a 	mov	r3,r2
+ 8041c18:	e0bffd17 	ldw	r2,-12(fp)
+ 8041c1c:	10c0058d 	sth	r3,22(r2)
+
+      /* copy the data to be written to the file buffer */
+      MEMCPY(vfp->data,buf,bcount);
+ 8041c20:	e0bffd17 	ldw	r2,-12(fp)
+ 8041c24:	10800617 	ldw	r2,24(r2)
+ 8041c28:	e1bffc17 	ldw	r6,-16(fp)
+ 8041c2c:	e17ff717 	ldw	r5,-36(fp)
+ 8041c30:	1009883a 	mov	r4,r2
+ 8041c34:	80086b80 	call	80086b8 <memcpy>
+
+      /* return the number of "items" written */
+      return items;
+ 8041c38:	e0bff517 	ldw	r2,-44(fp)
+ 8041c3c:	00006d06 	br	8041df4 <vfwrite_locked+0x398>
+   }
+
+   /* compute the current offset into the file */
+   current_offset = vfd->cmploc - vfp->data;
+ 8041c40:	e0bff417 	ldw	r2,-48(fp)
+ 8041c44:	10c00217 	ldw	r3,8(r2)
+ 8041c48:	e0bffd17 	ldw	r2,-12(fp)
+ 8041c4c:	10800617 	ldw	r2,24(r2)
+ 8041c50:	1885c83a 	sub	r2,r3,r2
+ 8041c54:	e0bffa15 	stw	r2,-24(fp)
+
+   /* if the data to be written wont fit into the file buffer */
+   if ((current_offset + bcount) > vfp->buf_size)
+ 8041c58:	e0fffa17 	ldw	r3,-24(fp)
+ 8041c5c:	e0bffc17 	ldw	r2,-16(fp)
+ 8041c60:	1885883a 	add	r2,r3,r2
+ 8041c64:	e0fffd17 	ldw	r3,-12(fp)
+ 8041c68:	18c00917 	ldw	r3,36(r3)
+ 8041c6c:	1880382e 	bgeu	r3,r2,8041d50 <vfwrite_locked+0x2f4>
+   {
+      /* compute the size of a new buffer to hold the data */
+      unsigned long new_buf_size = VFS_ROUND_UP(current_offset + bcount);
+ 8041c70:	e0fffa17 	ldw	r3,-24(fp)
+ 8041c74:	e0bffc17 	ldw	r2,-16(fp)
+ 8041c78:	1885883a 	add	r2,r3,r2
+ 8041c7c:	10ffffc4 	addi	r3,r2,-1
+ 8041c80:	00b80004 	movi	r2,-8192
+ 8041c84:	1884703a 	and	r2,r3,r2
+ 8041c88:	10880004 	addi	r2,r2,8192
+ 8041c8c:	e0bff915 	stw	r2,-28(fp)
+      unsigned char *new_buffer;
+
+      /* allocate a new buffer */
+      new_buffer = vf_alloc_buffer(new_buf_size);
+ 8041c90:	e13ff917 	ldw	r4,-28(fp)
+ 8041c94:	8040e700 	call	8040e70 <vf_alloc_buffer>
+ 8041c98:	e0bff815 	stw	r2,-32(fp)
+
+      /* check for allocation failure */
+      if (!new_buffer)
+ 8041c9c:	e0bff817 	ldw	r2,-32(fp)
+ 8041ca0:	1000051e 	bne	r2,zero,8041cb8 <vfwrite_locked+0x25c>
+      {
+         vfd->error = ENP_NOMEM;
+ 8041ca4:	e0bff417 	ldw	r2,-48(fp)
+ 8041ca8:	00fffb04 	movi	r3,-20
+ 8041cac:	10c00415 	stw	r3,16(r2)
+         return 0;
+ 8041cb0:	0005883a 	mov	r2,zero
+ 8041cb4:	00004f06 	br	8041df4 <vfwrite_locked+0x398>
+      }
+
+      /* copy the old buffer contents to the new buffer */
+      MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size));
+ 8041cb8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041cbc:	10c00617 	ldw	r3,24(r2)
+ 8041cc0:	e0bffd17 	ldw	r2,-12(fp)
+ 8041cc4:	10800817 	ldw	r2,32(r2)
+ 8041cc8:	100d883a 	mov	r6,r2
+ 8041ccc:	180b883a 	mov	r5,r3
+ 8041cd0:	e13ff817 	ldw	r4,-32(fp)
+ 8041cd4:	80086b80 	call	80086b8 <memcpy>
+
+      /* if the old buffer had been dynamically allocated */
+      if (vfp->flags & VF_DYNAMICDATA)
+ 8041cd8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041cdc:	1080058b 	ldhu	r2,22(r2)
+ 8041ce0:	10bfffcc 	andi	r2,r2,65535
+ 8041ce4:	1080200c 	andi	r2,r2,128
+ 8041ce8:	10000726 	beq	r2,zero,8041d08 <vfwrite_locked+0x2ac>
+      {
+         /* free it */
+         vf_free_buffer(vfp->data,vfp->buf_size);
+ 8041cec:	e0bffd17 	ldw	r2,-12(fp)
+ 8041cf0:	10c00617 	ldw	r3,24(r2)
+ 8041cf4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041cf8:	10800917 	ldw	r2,36(r2)
+ 8041cfc:	100b883a 	mov	r5,r2
+ 8041d00:	1809883a 	mov	r4,r3
+ 8041d04:	8040f380 	call	8040f38 <vf_free_buffer>
+      }
+
+      /* store the new buffer in the file structure */
+      vfp->data = new_buffer;
+ 8041d08:	e0bffd17 	ldw	r2,-12(fp)
+ 8041d0c:	e0fff817 	ldw	r3,-32(fp)
+ 8041d10:	10c00615 	stw	r3,24(r2)
+
+      /* store the new buffer size in the file structure */
+      vfp->buf_size = new_buf_size;
+ 8041d14:	e0bffd17 	ldw	r2,-12(fp)
+ 8041d18:	e0fff917 	ldw	r3,-28(fp)
+ 8041d1c:	10c00915 	stw	r3,36(r2)
+
+      /* the new buffer was dynamically allocated */
+      vfp->flags |= VF_DYNAMICDATA;
+ 8041d20:	e0bffd17 	ldw	r2,-12(fp)
+ 8041d24:	1080058b 	ldhu	r2,22(r2)
+ 8041d28:	10802014 	ori	r2,r2,128
+ 8041d2c:	1007883a 	mov	r3,r2
+ 8041d30:	e0bffd17 	ldw	r2,-12(fp)
+ 8041d34:	10c0058d 	sth	r3,22(r2)
+       * buffer note that this means the VFS does not support 
+       * simultaneous opens of the same file, since for that to work, 
+       * all the other cmploc's that point to this file would 
+       * have to be updated also 
+       */
+      vfd->cmploc = vfp->data + current_offset;
+ 8041d38:	e0bffd17 	ldw	r2,-12(fp)
+ 8041d3c:	10c00617 	ldw	r3,24(r2)
+ 8041d40:	e0bffa17 	ldw	r2,-24(fp)
+ 8041d44:	1887883a 	add	r3,r3,r2
+ 8041d48:	e0bff417 	ldw	r2,-48(fp)
+ 8041d4c:	10c00215 	stw	r3,8(r2)
+   }
+
+   /* copy the data to the current file pointer */
+   MEMCPY(vfd->cmploc,buf,bcount);
+ 8041d50:	e0bff417 	ldw	r2,-48(fp)
+ 8041d54:	10800217 	ldw	r2,8(r2)
+ 8041d58:	e1bffc17 	ldw	r6,-16(fp)
+ 8041d5c:	e17ff717 	ldw	r5,-36(fp)
+ 8041d60:	1009883a 	mov	r4,r2
+ 8041d64:	80086b80 	call	80086b8 <memcpy>
+
+   /* update the current file pointer */
+   vfd->cmploc += bcount;
+ 8041d68:	e0bff417 	ldw	r2,-48(fp)
+ 8041d6c:	10c00217 	ldw	r3,8(r2)
+ 8041d70:	e0bffc17 	ldw	r2,-16(fp)
+ 8041d74:	1887883a 	add	r3,r3,r2
+ 8041d78:	e0bff417 	ldw	r2,-48(fp)
+ 8041d7c:	10c00215 	stw	r3,8(r2)
+
+   /* if the resulting current offset is greater than the file size */
+   if (current_offset + bcount > vfp->comp_size)
+ 8041d80:	e0fffa17 	ldw	r3,-24(fp)
+ 8041d84:	e0bffc17 	ldw	r2,-16(fp)
+ 8041d88:	1885883a 	add	r2,r3,r2
+ 8041d8c:	e0fffd17 	ldw	r3,-12(fp)
+ 8041d90:	18c00817 	ldw	r3,32(r3)
+ 8041d94:	1880052e 	bgeu	r3,r2,8041dac <vfwrite_locked+0x350>
+   {
+      /* update the "compressed" file size */
+      vfp->comp_size = current_offset + bcount;
+ 8041d98:	e0fffa17 	ldw	r3,-24(fp)
+ 8041d9c:	e0bffc17 	ldw	r2,-16(fp)
+ 8041da0:	1887883a 	add	r3,r3,r2
+ 8041da4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041da8:	10c00815 	stw	r3,32(r2)
+   }
+
+   /* since we turn off the compression bit below, the "real" size and
+      the compressed size must be the same */
+   vfp->real_size = vfp->comp_size;
+ 8041dac:	e0bffd17 	ldw	r2,-12(fp)
+ 8041db0:	10c00817 	ldw	r3,32(r2)
+ 8041db4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041db8:	10c00715 	stw	r3,28(r2)
+
+   /* turn off the compression flag */
+   vfp->flags &= ~VF_HTMLCOMPRESSED;
+ 8041dbc:	e0bffd17 	ldw	r2,-12(fp)
+ 8041dc0:	10c0058b 	ldhu	r3,22(r2)
+ 8041dc4:	00bfff84 	movi	r2,-2
+ 8041dc8:	1884703a 	and	r2,r3,r2
+ 8041dcc:	1007883a 	mov	r3,r2
+ 8041dd0:	e0bffd17 	ldw	r2,-12(fp)
+ 8041dd4:	10c0058d 	sth	r3,22(r2)
+
+   /* the data in the file is stale */
+   vfp->flags |= VF_STALE;
+ 8041dd8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041ddc:	1080058b 	ldhu	r2,22(r2)
+ 8041de0:	10808014 	ori	r2,r2,512
+ 8041de4:	1007883a 	mov	r3,r2
+ 8041de8:	e0bffd17 	ldw	r2,-12(fp)
+ 8041dec:	10c0058d 	sth	r3,22(r2)
+
+   /* return the number of "items" written */
+   return items;
+ 8041df0:	e0bff517 	ldw	r2,-44(fp)
+
+#endif   /* HT_RWVFS */
+}
+ 8041df4:	e037883a 	mov	sp,fp
+ 8041df8:	dfc00117 	ldw	ra,4(sp)
+ 8041dfc:	df000017 	ldw	fp,0(sp)
+ 8041e00:	dec00204 	addi	sp,sp,8
+ 8041e04:	f800283a 	ret
+
+08041e08 <vfwrite>:
+ * RETURNS: 
+ */
+
+int
+vfwrite(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+ 8041e08:	defff904 	addi	sp,sp,-28
+ 8041e0c:	dfc00615 	stw	ra,24(sp)
+ 8041e10:	df000515 	stw	fp,20(sp)
+ 8041e14:	df000504 	addi	fp,sp,20
+ 8041e18:	e13ffe15 	stw	r4,-8(fp)
+ 8041e1c:	e17ffd15 	stw	r5,-12(fp)
+ 8041e20:	e1bffc15 	stw	r6,-16(fp)
+ 8041e24:	e1fffb15 	stw	r7,-20(fp)
+   int   rc;
+
+   IN_PROFILER(PF_FS, PF_ENTRY);
+
+   /* lock the VFS */
+   vfs_lock();
+ 8041e28:	01000144 	movi	r4,5
+ 8041e2c:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* do the write */
+   rc = vfwrite_locked(buf, size, items, vfd);
+ 8041e30:	e1fffb17 	ldw	r7,-20(fp)
+ 8041e34:	e1bffc17 	ldw	r6,-16(fp)
+ 8041e38:	e17ffd17 	ldw	r5,-12(fp)
+ 8041e3c:	e13ffe17 	ldw	r4,-8(fp)
+ 8041e40:	8041a5c0 	call	8041a5c <vfwrite_locked>
+ 8041e44:	e0bfff15 	stw	r2,-4(fp)
+
+   /* unlock the VFS */
+   vfs_unlock();
+ 8041e48:	01000144 	movi	r4,5
+ 8041e4c:	80293680 	call	8029368 <post_app_sem>
+
+   IN_PROFILER(PF_FS, PF_EXIT);
+
+   return rc;
+ 8041e50:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8041e54:	e037883a 	mov	sp,fp
+ 8041e58:	dfc00117 	ldw	ra,4(sp)
+ 8041e5c:	df000017 	ldw	fp,0(sp)
+ 8041e60:	dec00204 	addi	sp,sp,8
+ 8041e64:	f800283a 	ret
+
+08041e68 <vfseek>:
+ * RETURNS: 
+ */
+
+int 
+vfseek(VFILE * vfd, long offset, int mode)
+{
+ 8041e68:	defff904 	addi	sp,sp,-28
+ 8041e6c:	dfc00615 	stw	ra,24(sp)
+ 8041e70:	df000515 	stw	fp,20(sp)
+ 8041e74:	df000504 	addi	fp,sp,20
+ 8041e78:	e13ffd15 	stw	r4,-12(fp)
+ 8041e7c:	e17ffc15 	stw	r5,-16(fp)
+ 8041e80:	e1bffb15 	stw	r6,-20(fp)
+   /* lock the VFS */
+   vfs_lock();
+ 8041e84:	01000144 	movi	r4,5
+ 8041e88:	80292b40 	call	80292b4 <wait_app_sem>
+
+   if (isvfile_locked(vfd))
+ 8041e8c:	e13ffd17 	ldw	r4,-12(fp)
+ 8041e90:	80425400 	call	8042540 <isvfile_locked>
+ 8041e94:	10004126 	beq	r2,zero,8041f9c <vfseek+0x134>
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to seek a file that's been deleted,
+         so return an error indication */
+      if (vfd->file == NULL)
+ 8041e98:	e0bffd17 	ldw	r2,-12(fp)
+ 8041e9c:	10800117 	ldw	r2,4(r2)
+ 8041ea0:	1000041e 	bne	r2,zero,8041eb4 <vfseek+0x4c>
+      {
+         vfs_unlock();
+ 8041ea4:	01000144 	movi	r4,5
+ 8041ea8:	80293680 	call	8029368 <post_app_sem>
+         return -1;
+ 8041eac:	00bfffc4 	movi	r2,-1
+ 8041eb0:	00003d06 	br	8041fa8 <vfseek+0x140>
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+ 8041eb4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041eb8:	10800117 	ldw	r2,4(r2)
+ 8041ebc:	10800a17 	ldw	r2,40(r2)
+ 8041ec0:	10000f26 	beq	r2,zero,8041f00 <vfseek+0x98>
+      {
+         struct vfroutines *vfp = (struct vfroutines*)(vfd->file->method);
+ 8041ec4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041ec8:	10800117 	ldw	r2,4(r2)
+ 8041ecc:	10800a17 	ldw	r2,40(r2)
+ 8041ed0:	e0bfff15 	stw	r2,-4(fp)
+         int   rc;
+
+         rc = vfp->r_fseek(vfd, offset, mode);
+ 8041ed4:	e0bfff17 	ldw	r2,-4(fp)
+ 8041ed8:	10800517 	ldw	r2,20(r2)
+ 8041edc:	e1bffb17 	ldw	r6,-20(fp)
+ 8041ee0:	e17ffc17 	ldw	r5,-16(fp)
+ 8041ee4:	e13ffd17 	ldw	r4,-12(fp)
+ 8041ee8:	103ee83a 	callr	r2
+ 8041eec:	e0bffe15 	stw	r2,-8(fp)
+         vfs_unlock();
+ 8041ef0:	01000144 	movi	r4,5
+ 8041ef4:	80293680 	call	8029368 <post_app_sem>
+         return rc;
+ 8041ef8:	e0bffe17 	ldw	r2,-8(fp)
+ 8041efc:	00002a06 	br	8041fa8 <vfseek+0x140>
+      }
+#endif   /* HT_EXTDEV */
+      /* this vfseek() currently only supports seek to exact
+         end or begining of file */
+      switch (mode)
+ 8041f00:	e0bffb17 	ldw	r2,-20(fp)
+ 8041f04:	10800060 	cmpeqi	r2,r2,1
+ 8041f08:	10000d1e 	bne	r2,zero,8041f40 <vfseek+0xd8>
+ 8041f0c:	e0bffb17 	ldw	r2,-20(fp)
+ 8041f10:	108000a0 	cmpeqi	r2,r2,2
+ 8041f14:	1000111e 	bne	r2,zero,8041f5c <vfseek+0xf4>
+ 8041f18:	e0bffb17 	ldw	r2,-20(fp)
+ 8041f1c:	10001b1e 	bne	r2,zero,8041f8c <vfseek+0x124>
+      {
+      case SEEK_SET:
+         vfd->cmploc = vfd->file->data + offset;
+ 8041f20:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f24:	10800117 	ldw	r2,4(r2)
+ 8041f28:	10c00617 	ldw	r3,24(r2)
+ 8041f2c:	e0bffc17 	ldw	r2,-16(fp)
+ 8041f30:	1887883a 	add	r3,r3,r2
+ 8041f34:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f38:	10c00215 	stw	r3,8(r2)
+         break;
+ 8041f3c:	00001306 	br	8041f8c <vfseek+0x124>
+      case SEEK_CUR:
+         /* If the file is compressed, then the following
+          * adjustment is inaccurate. Currently we don't have
+          * any scenario where this happens. - handle later */
+         vfd->cmploc += offset; 
+ 8041f40:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f44:	10c00217 	ldw	r3,8(r2)
+ 8041f48:	e0bffc17 	ldw	r2,-16(fp)
+ 8041f4c:	1887883a 	add	r3,r3,r2
+ 8041f50:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f54:	10c00215 	stw	r3,8(r2)
+         break;
+ 8041f58:	00000c06 	br	8041f8c <vfseek+0x124>
+      case SEEK_END:
+         vfd->cmploc = vfd->file->data + vfd->file->comp_size + offset;
+ 8041f5c:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f60:	10800117 	ldw	r2,4(r2)
+ 8041f64:	10c00617 	ldw	r3,24(r2)
+ 8041f68:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f6c:	10800117 	ldw	r2,4(r2)
+ 8041f70:	11000817 	ldw	r4,32(r2)
+ 8041f74:	e0bffc17 	ldw	r2,-16(fp)
+ 8041f78:	2085883a 	add	r2,r4,r2
+ 8041f7c:	1887883a 	add	r3,r3,r2
+ 8041f80:	e0bffd17 	ldw	r2,-12(fp)
+ 8041f84:	10c00215 	stw	r3,8(r2)
+         break;
+ 8041f88:	0001883a 	nop
+      }
+      vfs_unlock();
+ 8041f8c:	01000144 	movi	r4,5
+ 8041f90:	80293680 	call	8029368 <post_app_sem>
+      return(0);
+ 8041f94:	0005883a 	mov	r2,zero
+ 8041f98:	00000306 	br	8041fa8 <vfseek+0x140>
+   }
+
+   vfs_unlock();
+ 8041f9c:	01000144 	movi	r4,5
+ 8041fa0:	80293680 	call	8029368 <post_app_sem>
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(fseek((FILE*)vfd, offset, mode));
+#else
+   return -1;
+ 8041fa4:	00bfffc4 	movi	r2,-1
+#endif   /* HT_LOCALFS */
+}
+ 8041fa8:	e037883a 	mov	sp,fp
+ 8041fac:	dfc00117 	ldw	ra,4(sp)
+ 8041fb0:	df000017 	ldw	fp,0(sp)
+ 8041fb4:	dec00204 	addi	sp,sp,8
+ 8041fb8:	f800283a 	ret
+
+08041fbc <vftell>:
+ * RETURNS: 
+ */
+
+long
+vftell(VFILE * vfd)
+{
+ 8041fbc:	defffb04 	addi	sp,sp,-20
+ 8041fc0:	dfc00415 	stw	ra,16(sp)
+ 8041fc4:	df000315 	stw	fp,12(sp)
+ 8041fc8:	df000304 	addi	fp,sp,12
+ 8041fcc:	e13ffd15 	stw	r4,-12(fp)
+   /* lock the VFS */
+   vfs_lock();
+ 8041fd0:	01000144 	movi	r4,5
+ 8041fd4:	80292b40 	call	80292b4 <wait_app_sem>
+
+   if (isvfile_locked(vfd))
+ 8041fd8:	e13ffd17 	ldw	r4,-12(fp)
+ 8041fdc:	80425400 	call	8042540 <isvfile_locked>
+ 8041fe0:	10003126 	beq	r2,zero,80420a8 <vftell+0xec>
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to ftell a deleted file,
+         so return an error condition */
+      if (vfd->file == NULL)
+ 8041fe4:	e0bffd17 	ldw	r2,-12(fp)
+ 8041fe8:	10800117 	ldw	r2,4(r2)
+ 8041fec:	1000041e 	bne	r2,zero,8042000 <vftell+0x44>
+      {
+         vfs_unlock();
+ 8041ff0:	01000144 	movi	r4,5
+ 8041ff4:	80293680 	call	8029368 <post_app_sem>
+         return -1;
+ 8041ff8:	00bfffc4 	movi	r2,-1
+ 8041ffc:	00002d06 	br	80420b4 <vftell+0xf8>
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+ 8042000:	e0bffd17 	ldw	r2,-12(fp)
+ 8042004:	10800117 	ldw	r2,4(r2)
+ 8042008:	10800a17 	ldw	r2,40(r2)
+ 804200c:	10000d26 	beq	r2,zero,8042044 <vftell+0x88>
+      {
+         struct vfroutines *  vfp   =  (struct  vfroutines*)   (vfd->file->method);
+ 8042010:	e0bffd17 	ldw	r2,-12(fp)
+ 8042014:	10800117 	ldw	r2,4(r2)
+ 8042018:	10800a17 	ldw	r2,40(r2)
+ 804201c:	e0bfff15 	stw	r2,-4(fp)
+         long  rc;
+
+         rc = vfp->r_ftell(vfd);
+ 8042020:	e0bfff17 	ldw	r2,-4(fp)
+ 8042024:	10800617 	ldw	r2,24(r2)
+ 8042028:	e13ffd17 	ldw	r4,-12(fp)
+ 804202c:	103ee83a 	callr	r2
+ 8042030:	e0bffe15 	stw	r2,-8(fp)
+         vfs_unlock();
+ 8042034:	01000144 	movi	r4,5
+ 8042038:	80293680 	call	8029368 <post_app_sem>
+         return rc;
+ 804203c:	e0bffe17 	ldw	r2,-8(fp)
+ 8042040:	00001c06 	br	80420b4 <vftell+0xf8>
+      }
+#endif   /* HT_EXTDEV */
+      /* if file has been fseeked to end, return uncompressed size.
+         else return current location in compression stream */
+      if (vfd->cmploc == vfd->file->data + vfd->file->comp_size)
+ 8042044:	e0bffd17 	ldw	r2,-12(fp)
+ 8042048:	10c00217 	ldw	r3,8(r2)
+ 804204c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042050:	10800117 	ldw	r2,4(r2)
+ 8042054:	11000617 	ldw	r4,24(r2)
+ 8042058:	e0bffd17 	ldw	r2,-12(fp)
+ 804205c:	10800117 	ldw	r2,4(r2)
+ 8042060:	10800817 	ldw	r2,32(r2)
+ 8042064:	2085883a 	add	r2,r4,r2
+ 8042068:	1880061e 	bne	r3,r2,8042084 <vftell+0xc8>
+      {
+         vfs_unlock();
+ 804206c:	01000144 	movi	r4,5
+ 8042070:	80293680 	call	8029368 <post_app_sem>
+
+         return vfd->file->comp_size;
+ 8042074:	e0bffd17 	ldw	r2,-12(fp)
+ 8042078:	10800117 	ldw	r2,4(r2)
+ 804207c:	10800817 	ldw	r2,32(r2)
+ 8042080:	00000c06 	br	80420b4 <vftell+0xf8>
+      }
+      else
+      {
+         vfs_unlock();
+ 8042084:	01000144 	movi	r4,5
+ 8042088:	80293680 	call	8029368 <post_app_sem>
+
+         return (vfd->cmploc - vfd->file->data);
+ 804208c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042090:	10c00217 	ldw	r3,8(r2)
+ 8042094:	e0bffd17 	ldw	r2,-12(fp)
+ 8042098:	10800117 	ldw	r2,4(r2)
+ 804209c:	10800617 	ldw	r2,24(r2)
+ 80420a0:	1885c83a 	sub	r2,r3,r2
+ 80420a4:	00000306 	br	80420b4 <vftell+0xf8>
+      }
+   }
+
+   vfs_unlock();
+ 80420a8:	01000144 	movi	r4,5
+ 80420ac:	80293680 	call	8029368 <post_app_sem>
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(ftell((FILE*)vfd));
+#else
+   return EBADF;
+ 80420b0:	00800244 	movi	r2,9
+#endif   /* HT_LOCALFS */
+}
+ 80420b4:	e037883a 	mov	sp,fp
+ 80420b8:	dfc00117 	ldw	ra,4(sp)
+ 80420bc:	df000017 	ldw	fp,0(sp)
+ 80420c0:	dec00204 	addi	sp,sp,8
+ 80420c4:	f800283a 	ret
+
+080420c8 <vgetc_locked>:
+ * RETURNS: 
+ */
+
+int
+vgetc_locked(VFILE * vfd)
+{
+ 80420c8:	defffb04 	addi	sp,sp,-20
+ 80420cc:	dfc00415 	stw	ra,16(sp)
+ 80420d0:	df000315 	stw	fp,12(sp)
+ 80420d4:	df000304 	addi	fp,sp,12
+ 80420d8:	e13ffd15 	stw	r4,-12(fp)
+   int   chr;
+
+   if (isvfile_locked(vfd))
+ 80420dc:	e13ffd17 	ldw	r4,-12(fp)
+ 80420e0:	80425400 	call	8042540 <isvfile_locked>
+ 80420e4:	10002f26 	beq	r2,zero,80421a4 <vgetc_locked+0xdc>
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to read a file that's been deleted,
+         so return an error condition */
+      if (vfd->file == NULL)
+ 80420e8:	e0bffd17 	ldw	r2,-12(fp)
+ 80420ec:	10800117 	ldw	r2,4(r2)
+ 80420f0:	1000021e 	bne	r2,zero,80420fc <vgetc_locked+0x34>
+      {
+         return EOF;
+ 80420f4:	00bfffc4 	movi	r2,-1
+ 80420f8:	00002c06 	br	80421ac <vgetc_locked+0xe4>
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+ 80420fc:	e0bffd17 	ldw	r2,-12(fp)
+ 8042100:	10800117 	ldw	r2,4(r2)
+ 8042104:	10800a17 	ldw	r2,40(r2)
+ 8042108:	10000926 	beq	r2,zero,8042130 <vgetc_locked+0x68>
+      {
+         struct vfroutines *  vfp   =  (struct  vfroutines*)   (vfd->file->method);
+ 804210c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042110:	10800117 	ldw	r2,4(r2)
+ 8042114:	10800a17 	ldw	r2,40(r2)
+ 8042118:	e0bffe15 	stw	r2,-8(fp)
+         return (vfp->r_fgetc(vfd));
+ 804211c:	e0bffe17 	ldw	r2,-8(fp)
+ 8042120:	10800717 	ldw	r2,28(r2)
+ 8042124:	e13ffd17 	ldw	r4,-12(fp)
+ 8042128:	103ee83a 	callr	r2
+ 804212c:	00001f06 	br	80421ac <vgetc_locked+0xe4>
+#endif   /* HT_EXTDEV */
+
+#ifdef HT_RWVFS
+      /* a freshly created file might not have a data buffer associated
+         with it yet */
+      if (vfd->file->data == NULL)
+ 8042130:	e0bffd17 	ldw	r2,-12(fp)
+ 8042134:	10800117 	ldw	r2,4(r2)
+ 8042138:	10800617 	ldw	r2,24(r2)
+ 804213c:	1000021e 	bne	r2,zero,8042148 <vgetc_locked+0x80>
+         return EOF;
+ 8042140:	00bfffc4 	movi	r2,-1
+ 8042144:	00001906 	br	80421ac <vgetc_locked+0xe4>
+      }
+      else  /* HTML compression flag not set */
+      {
+#endif   /* HTML_COMPRESSION */
+         /* Check to see if read has advanced to end of file */
+         if (vfd->cmploc >= (vfd->file->data + vfd->file->comp_size))
+ 8042148:	e0bffd17 	ldw	r2,-12(fp)
+ 804214c:	10c00217 	ldw	r3,8(r2)
+ 8042150:	e0bffd17 	ldw	r2,-12(fp)
+ 8042154:	10800117 	ldw	r2,4(r2)
+ 8042158:	11000617 	ldw	r4,24(r2)
+ 804215c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042160:	10800117 	ldw	r2,4(r2)
+ 8042164:	10800817 	ldw	r2,32(r2)
+ 8042168:	2085883a 	add	r2,r4,r2
+ 804216c:	18800336 	bltu	r3,r2,804217c <vgetc_locked+0xb4>
+            chr = EOF;
+ 8042170:	00bfffc4 	movi	r2,-1
+ 8042174:	e0bfff15 	stw	r2,-4(fp)
+ 8042178:	00000806 	br	804219c <vgetc_locked+0xd4>
+         else  /* else just get next char to return */
+            chr = *(vfd->cmploc++);
+ 804217c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042180:	10800217 	ldw	r2,8(r2)
+ 8042184:	11000044 	addi	r4,r2,1
+ 8042188:	e0fffd17 	ldw	r3,-12(fp)
+ 804218c:	19000215 	stw	r4,8(r3)
+ 8042190:	10800003 	ldbu	r2,0(r2)
+ 8042194:	10803fcc 	andi	r2,r2,255
+ 8042198:	e0bfff15 	stw	r2,-4(fp)
+#ifdef HTML_COMPRESSION
+      }  /* need to close brace form if...else; */
+#endif   /* HTML_COMPRESSION */
+
+      return chr;
+ 804219c:	e0bfff17 	ldw	r2,-4(fp)
+ 80421a0:	00000206 	br	80421ac <vgetc_locked+0xe4>
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(getc((FILE*)vfd));
+#else
+   dtrap(); /* can this happen? */
+ 80421a4:	8028cd40 	call	8028cd4 <dtrap>
+   return EOF;
+ 80421a8:	00bfffc4 	movi	r2,-1
+#endif   /* HT_LOCALFS */
+}
+ 80421ac:	e037883a 	mov	sp,fp
+ 80421b0:	dfc00117 	ldw	ra,4(sp)
+ 80421b4:	df000017 	ldw	fp,0(sp)
+ 80421b8:	dec00204 	addi	sp,sp,8
+ 80421bc:	f800283a 	ret
+
+080421c0 <vgetc>:
+ * RETURNS: 
+ */
+
+int
+vgetc(VFILE * vfd)
+{
+ 80421c0:	defffc04 	addi	sp,sp,-16
+ 80421c4:	dfc00315 	stw	ra,12(sp)
+ 80421c8:	df000215 	stw	fp,8(sp)
+ 80421cc:	df000204 	addi	fp,sp,8
+ 80421d0:	e13ffe15 	stw	r4,-8(fp)
+   int   rc;
+
+   /* lock the VFS */
+   vfs_lock();
+ 80421d4:	01000144 	movi	r4,5
+ 80421d8:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* get the character */
+   rc = vgetc_locked(vfd);
+ 80421dc:	e13ffe17 	ldw	r4,-8(fp)
+ 80421e0:	80420c80 	call	80420c8 <vgetc_locked>
+ 80421e4:	e0bfff15 	stw	r2,-4(fp)
+
+   /* unlock the VFS */
+   vfs_unlock();
+ 80421e8:	01000144 	movi	r4,5
+ 80421ec:	80293680 	call	8029368 <post_app_sem>
+   return rc;
+ 80421f0:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80421f4:	e037883a 	mov	sp,fp
+ 80421f8:	dfc00117 	ldw	ra,4(sp)
+ 80421fc:	df000017 	ldw	fp,0(sp)
+ 8042200:	dec00204 	addi	sp,sp,8
+ 8042204:	f800283a 	ret
+
+08042208 <vfslookup_locked>:
+ * RETURNS: 
+ */
+
+struct vfs_file * 
+vfslookup_locked(char * name)
+{
+ 8042208:	defffb04 	addi	sp,sp,-20
+ 804220c:	dfc00415 	stw	ra,16(sp)
+ 8042210:	df000315 	stw	fp,12(sp)
+ 8042214:	df000304 	addi	fp,sp,12
+ 8042218:	e13ffd15 	stw	r4,-12(fp)
+
+#ifdef VFS_STRIPPATH
+   char *   cp;
+
+   /* If root path is prepended to name, skip past it */
+   if (*name == '/' || *name == '\\')
+ 804221c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042220:	10800003 	ldbu	r2,0(r2)
+ 8042224:	10803fcc 	andi	r2,r2,255
+ 8042228:	1080201c 	xori	r2,r2,128
+ 804222c:	10bfe004 	addi	r2,r2,-128
+ 8042230:	10800be0 	cmpeqi	r2,r2,47
+ 8042234:	1000071e 	bne	r2,zero,8042254 <vfslookup_locked+0x4c>
+ 8042238:	e0bffd17 	ldw	r2,-12(fp)
+ 804223c:	10800003 	ldbu	r2,0(r2)
+ 8042240:	10803fcc 	andi	r2,r2,255
+ 8042244:	1080201c 	xori	r2,r2,128
+ 8042248:	10bfe004 	addi	r2,r2,-128
+ 804224c:	10801718 	cmpnei	r2,r2,92
+ 8042250:	1000191e 	bne	r2,zero,80422b8 <vfslookup_locked+0xb0>
+   {
+      cp = strippath(name);
+ 8042254:	e13ffd17 	ldw	r4,-12(fp)
+ 8042258:	80423740 	call	8042374 <strippath>
+ 804225c:	e0bffe15 	stw	r2,-8(fp)
+
+      if (!cp) /* strippath coundn't match our path */
+ 8042260:	e0bffe17 	ldw	r2,-8(fp)
+ 8042264:	1000121e 	bne	r2,zero,80422b0 <vfslookup_locked+0xa8>
+      {
+         /* Files like "/hub47.gif" need to be taken care of */
+         if (*name == '/' || *name == '\\')
+ 8042268:	e0bffd17 	ldw	r2,-12(fp)
+ 804226c:	10800003 	ldbu	r2,0(r2)
+ 8042270:	10803fcc 	andi	r2,r2,255
+ 8042274:	1080201c 	xori	r2,r2,128
+ 8042278:	10bfe004 	addi	r2,r2,-128
+ 804227c:	10800be0 	cmpeqi	r2,r2,47
+ 8042280:	1000071e 	bne	r2,zero,80422a0 <vfslookup_locked+0x98>
+ 8042284:	e0bffd17 	ldw	r2,-12(fp)
+ 8042288:	10800003 	ldbu	r2,0(r2)
+ 804228c:	10803fcc 	andi	r2,r2,255
+ 8042290:	1080201c 	xori	r2,r2,128
+ 8042294:	10bfe004 	addi	r2,r2,-128
+ 8042298:	10801718 	cmpnei	r2,r2,92
+ 804229c:	1000061e 	bne	r2,zero,80422b8 <vfslookup_locked+0xb0>
+            name++;
+ 80422a0:	e0bffd17 	ldw	r2,-12(fp)
+ 80422a4:	10800044 	addi	r2,r2,1
+ 80422a8:	e0bffd15 	stw	r2,-12(fp)
+ 80422ac:	00000206 	br	80422b8 <vfslookup_locked+0xb0>
+      }
+      else
+         name = cp ;
+ 80422b0:	e0bffe17 	ldw	r2,-8(fp)
+ 80422b4:	e0bffd15 	stw	r2,-12(fp)
+   }
+#endif   /* VFS_STRIPPATH */
+
+   /* see if there is a question mark in the file name */
+   if (strchr(name,'?'))
+ 80422b8:	01400fc4 	movi	r5,63
+ 80422bc:	e13ffd17 	ldw	r4,-12(fp)
+ 80422c0:	8042dfc0 	call	8042dfc <strchr>
+ 80422c4:	10000326 	beq	r2,zero,80422d4 <vfslookup_locked+0xcc>
+   {
+      dtrap(); /* is this still allowed? */
+ 80422c8:	8028cd40 	call	8028cd4 <dtrap>
+      return NULL;
+ 80422cc:	0005883a 	mov	r2,zero
+ 80422d0:	00001106 	br	8042318 <vfslookup_locked+0x110>
+   }
+
+   for (vp = vfsfiles; vp; vp = vp->next)    /* search vfs list for name */
+ 80422d4:	d0a0a317 	ldw	r2,-32116(gp)
+ 80422d8:	e0bfff15 	stw	r2,-4(fp)
+ 80422dc:	00000b06 	br	804230c <vfslookup_locked+0x104>
+   {
+      if (strcmp(name, vp->name) == 0)
+ 80422e0:	e0bfff17 	ldw	r2,-4(fp)
+ 80422e4:	10800104 	addi	r2,r2,4
+ 80422e8:	100b883a 	mov	r5,r2
+ 80422ec:	e13ffd17 	ldw	r4,-12(fp)
+ 80422f0:	800c2240 	call	800c224 <strcmp>
+ 80422f4:	1000021e 	bne	r2,zero,8042300 <vfslookup_locked+0xf8>
+         return vp;
+ 80422f8:	e0bfff17 	ldw	r2,-4(fp)
+ 80422fc:	00000606 	br	8042318 <vfslookup_locked+0x110>
+   for (vp = vfsfiles; vp; vp = vp->next)    /* search vfs list for name */
+ 8042300:	e0bfff17 	ldw	r2,-4(fp)
+ 8042304:	10800017 	ldw	r2,0(r2)
+ 8042308:	e0bfff15 	stw	r2,-4(fp)
+ 804230c:	e0bfff17 	ldw	r2,-4(fp)
+ 8042310:	103ff31e 	bne	r2,zero,80422e0 <vfslookup_locked+0xd8>
+   }
+
+   return NULL;   /* fall to here if not found in for loop */
+ 8042314:	0005883a 	mov	r2,zero
+}
+ 8042318:	e037883a 	mov	sp,fp
+ 804231c:	dfc00117 	ldw	ra,4(sp)
+ 8042320:	df000017 	ldw	fp,0(sp)
+ 8042324:	dec00204 	addi	sp,sp,8
+ 8042328:	f800283a 	ret
+
+0804232c <vfslookup>:
+ * RETURNS: 
+ */
+
+struct vfs_file * 
+vfslookup(char * name) 
+{
+ 804232c:	defffc04 	addi	sp,sp,-16
+ 8042330:	dfc00315 	stw	ra,12(sp)
+ 8042334:	df000215 	stw	fp,8(sp)
+ 8042338:	df000204 	addi	fp,sp,8
+ 804233c:	e13ffe15 	stw	r4,-8(fp)
+   if (vfs_log_file_name)
+      dprintf("vfslookup() passed >%s<\n",name);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+ 8042340:	01000144 	movi	r4,5
+ 8042344:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* do the lookup */
+   vp = vfslookup_locked(name);
+ 8042348:	e13ffe17 	ldw	r4,-8(fp)
+ 804234c:	80422080 	call	8042208 <vfslookup_locked>
+ 8042350:	e0bfff15 	stw	r2,-4(fp)
+
+   /* unlock the VFS */
+   vfs_unlock();
+ 8042354:	01000144 	movi	r4,5
+ 8042358:	80293680 	call	8029368 <post_app_sem>
+   return vp;
+ 804235c:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 8042360:	e037883a 	mov	sp,fp
+ 8042364:	dfc00117 	ldw	ra,4(sp)
+ 8042368:	df000017 	ldw	fp,0(sp)
+ 804236c:	dec00204 	addi	sp,sp,8
+ 8042370:	f800283a 	ret
+
+08042374 <strippath>:
+ * have the http_root_path prepended; or on any error. 
+ */
+
+char * 
+strippath(char * name)
+{
+ 8042374:	defff904 	addi	sp,sp,-28
+ 8042378:	dfc00615 	stw	ra,24(sp)
+ 804237c:	df000515 	stw	fp,20(sp)
+ 8042380:	df000504 	addi	fp,sp,20
+ 8042384:	e13ffb15 	stw	r4,-20(fp)
+   char *   path; /* pointer into system path */
+   char *   ptmp; /* another pointer into path */
+   char *   ntmp; /* pointer into name text */
+   int   dirlen;
+
+   ntmp = uslash(name);      /* uslash() is defined in misclib\in_utils.c */
+ 8042388:	e13ffb17 	ldw	r4,-20(fp)
+ 804238c:	80273140 	call	8027314 <uslash>
+ 8042390:	e0bffe15 	stw	r2,-8(fp)
+   path = http_root_path; /* The servers root path, at least one UNIX slash */
+ 8042394:	d0a03417 	ldw	r2,-32560(gp)
+ 8042398:	e0bfff15 	stw	r2,-4(fp)
+   while (*path && *ntmp)
+ 804239c:	00003a06 	br	8042488 <strippath+0x114>
+   {
+      while (*path == '/') path++;   /* strip leading slash */
+ 80423a0:	e0bfff17 	ldw	r2,-4(fp)
+ 80423a4:	10800044 	addi	r2,r2,1
+ 80423a8:	e0bfff15 	stw	r2,-4(fp)
+ 80423ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80423b0:	10800003 	ldbu	r2,0(r2)
+ 80423b4:	10803fcc 	andi	r2,r2,255
+ 80423b8:	1080201c 	xori	r2,r2,128
+ 80423bc:	10bfe004 	addi	r2,r2,-128
+ 80423c0:	10800be0 	cmpeqi	r2,r2,47
+ 80423c4:	103ff61e 	bne	r2,zero,80423a0 <strippath+0x2c>
+         if (*path == 0)
+ 80423c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80423cc:	10800003 	ldbu	r2,0(r2)
+ 80423d0:	10803fcc 	andi	r2,r2,255
+ 80423d4:	1080201c 	xori	r2,r2,128
+ 80423d8:	10bfe004 	addi	r2,r2,-128
+ 80423dc:	10003726 	beq	r2,zero,80424bc <strippath+0x148>
+         break;
+      /* find number of chars in this directory layer's name */
+      ptmp = strchr(path, '/');   /* location of next slash in path */
+ 80423e0:	01400bc4 	movi	r5,47
+ 80423e4:	e13fff17 	ldw	r4,-4(fp)
+ 80423e8:	8042dfc0 	call	8042dfc <strchr>
+ 80423ec:	e0bffc15 	stw	r2,-16(fp)
+      if (ptmp)
+ 80423f0:	e0bffc17 	ldw	r2,-16(fp)
+ 80423f4:	10000526 	beq	r2,zero,804240c <strippath+0x98>
+         dirlen = ptmp - path;
+ 80423f8:	e0fffc17 	ldw	r3,-16(fp)
+ 80423fc:	e0bfff17 	ldw	r2,-4(fp)
+ 8042400:	1885c83a 	sub	r2,r3,r2
+ 8042404:	e0bffd15 	stw	r2,-12(fp)
+ 8042408:	00000706 	br	8042428 <strippath+0xb4>
+      else
+         dirlen = strlen(path);
+ 804240c:	e13fff17 	ldw	r4,-4(fp)
+ 8042410:	8002dac0 	call	8002dac <strlen>
+ 8042414:	e0bffd15 	stw	r2,-12(fp)
+
+      while (*ntmp == '/') ntmp++;   /* strip leading slash */
+ 8042418:	00000306 	br	8042428 <strippath+0xb4>
+ 804241c:	e0bffe17 	ldw	r2,-8(fp)
+ 8042420:	10800044 	addi	r2,r2,1
+ 8042424:	e0bffe15 	stw	r2,-8(fp)
+ 8042428:	e0bffe17 	ldw	r2,-8(fp)
+ 804242c:	10800003 	ldbu	r2,0(r2)
+ 8042430:	10803fcc 	andi	r2,r2,255
+ 8042434:	1080201c 	xori	r2,r2,128
+ 8042438:	10bfe004 	addi	r2,r2,-128
+ 804243c:	10800be0 	cmpeqi	r2,r2,47
+ 8042440:	103ff61e 	bne	r2,zero,804241c <strippath+0xa8>
+         if (strncmp(ntmp, path, dirlen) == 0)
+ 8042444:	e0bffd17 	ldw	r2,-12(fp)
+ 8042448:	100d883a 	mov	r6,r2
+ 804244c:	e17fff17 	ldw	r5,-4(fp)
+ 8042450:	e13ffe17 	ldw	r4,-8(fp)
+ 8042454:	8042fec0 	call	8042fec <strncmp>
+ 8042458:	1000091e 	bne	r2,zero,8042480 <strippath+0x10c>
+      {
+         path += dirlen;
+ 804245c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042460:	e0ffff17 	ldw	r3,-4(fp)
+ 8042464:	1885883a 	add	r2,r3,r2
+ 8042468:	e0bfff15 	stw	r2,-4(fp)
+         ntmp += dirlen;
+ 804246c:	e0bffd17 	ldw	r2,-12(fp)
+ 8042470:	e0fffe17 	ldw	r3,-8(fp)
+ 8042474:	1885883a 	add	r2,r3,r2
+ 8042478:	e0bffe15 	stw	r2,-8(fp)
+ 804247c:	00000206 	br	8042488 <strippath+0x114>
+      }
+      else
+         return NULL;   /* didn't match */
+ 8042480:	0005883a 	mov	r2,zero
+ 8042484:	00002906 	br	804252c <strippath+0x1b8>
+   while (*path && *ntmp)
+ 8042488:	e0bfff17 	ldw	r2,-4(fp)
+ 804248c:	10800003 	ldbu	r2,0(r2)
+ 8042490:	10803fcc 	andi	r2,r2,255
+ 8042494:	1080201c 	xori	r2,r2,128
+ 8042498:	10bfe004 	addi	r2,r2,-128
+ 804249c:	10000826 	beq	r2,zero,80424c0 <strippath+0x14c>
+ 80424a0:	e0bffe17 	ldw	r2,-8(fp)
+ 80424a4:	10800003 	ldbu	r2,0(r2)
+ 80424a8:	10803fcc 	andi	r2,r2,255
+ 80424ac:	1080201c 	xori	r2,r2,128
+ 80424b0:	10bfe004 	addi	r2,r2,-128
+ 80424b4:	103fbd1e 	bne	r2,zero,80423ac <strippath+0x38>
+ 80424b8:	00000106 	br	80424c0 <strippath+0x14c>
+         break;
+ 80424bc:	0001883a 	nop
+   }
+   if (*path == '\0')
+ 80424c0:	e0bfff17 	ldw	r2,-4(fp)
+ 80424c4:	10800003 	ldbu	r2,0(r2)
+ 80424c8:	10803fcc 	andi	r2,r2,255
+ 80424cc:	1080201c 	xori	r2,r2,128
+ 80424d0:	10bfe004 	addi	r2,r2,-128
+ 80424d4:	1000141e 	bne	r2,zero,8042528 <strippath+0x1b4>
+   {
+      while (*ntmp == '\\' || *ntmp == '/')
+ 80424d8:	00000306 	br	80424e8 <strippath+0x174>
+         ntmp++;
+ 80424dc:	e0bffe17 	ldw	r2,-8(fp)
+ 80424e0:	10800044 	addi	r2,r2,1
+ 80424e4:	e0bffe15 	stw	r2,-8(fp)
+      while (*ntmp == '\\' || *ntmp == '/')
+ 80424e8:	e0bffe17 	ldw	r2,-8(fp)
+ 80424ec:	10800003 	ldbu	r2,0(r2)
+ 80424f0:	10803fcc 	andi	r2,r2,255
+ 80424f4:	1080201c 	xori	r2,r2,128
+ 80424f8:	10bfe004 	addi	r2,r2,-128
+ 80424fc:	10801720 	cmpeqi	r2,r2,92
+ 8042500:	103ff61e 	bne	r2,zero,80424dc <strippath+0x168>
+ 8042504:	e0bffe17 	ldw	r2,-8(fp)
+ 8042508:	10800003 	ldbu	r2,0(r2)
+ 804250c:	10803fcc 	andi	r2,r2,255
+ 8042510:	1080201c 	xori	r2,r2,128
+ 8042514:	10bfe004 	addi	r2,r2,-128
+ 8042518:	10800be0 	cmpeqi	r2,r2,47
+ 804251c:	103fef1e 	bne	r2,zero,80424dc <strippath+0x168>
+      return ntmp;
+ 8042520:	e0bffe17 	ldw	r2,-8(fp)
+ 8042524:	00000106 	br	804252c <strippath+0x1b8>
+   }
+   else
+      return NULL;
+ 8042528:	0005883a 	mov	r2,zero
+}
+ 804252c:	e037883a 	mov	sp,fp
+ 8042530:	dfc00117 	ldw	ra,4(sp)
+ 8042534:	df000017 	ldw	fp,0(sp)
+ 8042538:	dec00204 	addi	sp,sp,8
+ 804253c:	f800283a 	ret
+
+08042540 <isvfile_locked>:
+ * RETURNS: 
+ */
+
+int
+isvfile_locked(VFILE * vfp)
+{
+ 8042540:	defffd04 	addi	sp,sp,-12
+ 8042544:	df000215 	stw	fp,8(sp)
+ 8042548:	df000204 	addi	fp,sp,8
+ 804254c:	e13ffe15 	stw	r4,-8(fp)
+   VFILE * vtmp;
+
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+ 8042550:	d0a0a217 	ldw	r2,-32120(gp)
+ 8042554:	e0bfff15 	stw	r2,-4(fp)
+ 8042558:	00000806 	br	804257c <isvfile_locked+0x3c>
+      if (vtmp == vfp)
+ 804255c:	e0ffff17 	ldw	r3,-4(fp)
+ 8042560:	e0bffe17 	ldw	r2,-8(fp)
+ 8042564:	1880021e 	bne	r3,r2,8042570 <isvfile_locked+0x30>
+      return TRUE;
+ 8042568:	00800044 	movi	r2,1
+ 804256c:	00000606 	br	8042588 <isvfile_locked+0x48>
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+ 8042570:	e0bfff17 	ldw	r2,-4(fp)
+ 8042574:	10800017 	ldw	r2,0(r2)
+ 8042578:	e0bfff15 	stw	r2,-4(fp)
+ 804257c:	e0bfff17 	ldw	r2,-4(fp)
+ 8042580:	103ff61e 	bne	r2,zero,804255c <isvfile_locked+0x1c>
+
+   return FALSE;  /* passed pointer not found in list */
+ 8042584:	0005883a 	mov	r2,zero
+}
+ 8042588:	e037883a 	mov	sp,fp
+ 804258c:	df000017 	ldw	fp,0(sp)
+ 8042590:	dec00104 	addi	sp,sp,4
+ 8042594:	f800283a 	ret
+
+08042598 <isvfile>:
+ * RETURNS: 
+ */
+
+int
+isvfile(VFILE * vfp)
+{
+ 8042598:	defffc04 	addi	sp,sp,-16
+ 804259c:	dfc00315 	stw	ra,12(sp)
+ 80425a0:	df000215 	stw	fp,8(sp)
+ 80425a4:	df000204 	addi	fp,sp,8
+ 80425a8:	e13ffe15 	stw	r4,-8(fp)
+   int   rc;
+
+   /* lock the VFS */
+   vfs_lock();
+ 80425ac:	01000144 	movi	r4,5
+ 80425b0:	80292b40 	call	80292b4 <wait_app_sem>
+
+   /* do the lookup */
+   rc = isvfile_locked(vfp);
+ 80425b4:	e13ffe17 	ldw	r4,-8(fp)
+ 80425b8:	80425400 	call	8042540 <isvfile_locked>
+ 80425bc:	e0bfff15 	stw	r2,-4(fp)
+
+   /* unlock the VFS */
+   vfs_unlock();
+ 80425c0:	01000144 	movi	r4,5
+ 80425c4:	80293680 	call	8029368 <post_app_sem>
+   return rc;
+ 80425c8:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80425cc:	e037883a 	mov	sp,fp
+ 80425d0:	dfc00117 	ldw	ra,4(sp)
+ 80425d4:	df000017 	ldw	fp,0(sp)
+ 80425d8:	dec00204 	addi	sp,sp,8
+ 80425dc:	f800283a 	ret
+
+080425e0 <vferror>:
+ * RETURNS: 
+ */
+
+int
+vferror(VFILE * vfd)
+{
+ 80425e0:	defffd04 	addi	sp,sp,-12
+ 80425e4:	dfc00215 	stw	ra,8(sp)
+ 80425e8:	df000115 	stw	fp,4(sp)
+ 80425ec:	df000104 	addi	fp,sp,4
+ 80425f0:	e13fff15 	stw	r4,-4(fp)
+   /* lock the VFS */
+   vfs_lock();
+ 80425f4:	01000144 	movi	r4,5
+ 80425f8:	80292b40 	call	80292b4 <wait_app_sem>
+
+   if (isvfile_locked(vfd))
+ 80425fc:	e13fff17 	ldw	r4,-4(fp)
+ 8042600:	80425400 	call	8042540 <isvfile_locked>
+ 8042604:	10000526 	beq	r2,zero,804261c <vferror+0x3c>
+   {
+      vfs_unlock();
+ 8042608:	01000144 	movi	r4,5
+ 804260c:	80293680 	call	8029368 <post_app_sem>
+
+      return vfd->error;
+ 8042610:	e0bfff17 	ldw	r2,-4(fp)
+ 8042614:	10800417 	ldw	r2,16(r2)
+ 8042618:	00000306 	br	8042628 <vferror+0x48>
+   }
+
+   vfs_unlock();
+ 804261c:	01000144 	movi	r4,5
+ 8042620:	80293680 	call	8029368 <post_app_sem>
+
+#ifdef HT_LOCALFS
+   return(ferror((FILE*)vfd));
+#else /* not a VFILE, and no local FS */
+   return -1;  /* should this be an error? */
+ 8042624:	00bfffc4 	movi	r2,-1
+#endif   /* HT_LOCALFS */
+}
+ 8042628:	e037883a 	mov	sp,fp
+ 804262c:	dfc00117 	ldw	ra,4(sp)
+ 8042630:	df000017 	ldw	fp,0(sp)
+ 8042634:	dec00204 	addi	sp,sp,8
+ 8042638:	f800283a 	ret
+
+0804263c <vclearerr>:
+ *
+ * RETURNS: 
+ */
+
+void vclearerr(VFILE * vfd)
+{
+ 804263c:	defffd04 	addi	sp,sp,-12
+ 8042640:	dfc00215 	stw	ra,8(sp)
+ 8042644:	df000115 	stw	fp,4(sp)
+ 8042648:	df000104 	addi	fp,sp,4
+ 804264c:	e13fff15 	stw	r4,-4(fp)
+   /* lock the VFS */
+   vfs_lock();
+ 8042650:	01000144 	movi	r4,5
+ 8042654:	80292b40 	call	80292b4 <wait_app_sem>
+
+   if (isvfile_locked(vfd))
+ 8042658:	e13fff17 	ldw	r4,-4(fp)
+ 804265c:	80425400 	call	8042540 <isvfile_locked>
+ 8042660:	10000526 	beq	r2,zero,8042678 <vclearerr+0x3c>
+   {
+      vfs_unlock();
+ 8042664:	01000144 	movi	r4,5
+ 8042668:	80293680 	call	8029368 <post_app_sem>
+
+      vfd->error = 0;
+ 804266c:	e0bfff17 	ldw	r2,-4(fp)
+ 8042670:	10000415 	stw	zero,16(r2)
+      return;
+ 8042674:	00000206 	br	8042680 <vclearerr+0x44>
+   }
+
+   vfs_unlock();
+ 8042678:	01000144 	movi	r4,5
+ 804267c:	80293680 	call	8029368 <post_app_sem>
+
+#ifdef HT_LOCALFS
+   clearerr((FILE *) vfd);
+#endif   /* HT_LOCALFS */
+}
+ 8042680:	e037883a 	mov	sp,fp
+ 8042684:	dfc00117 	ldw	ra,4(sp)
+ 8042688:	df000017 	ldw	fp,0(sp)
+ 804268c:	dec00204 	addi	sp,sp,8
+ 8042690:	f800283a 	ret
+
+08042694 <prep_vfs>:
+ * PARAMS: NONE
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+int prep_vfs(void)
+{
+ 8042694:	defffe04 	addi	sp,sp,-8
+ 8042698:	df000115 	stw	fp,4(sp)
+ 804269c:	df000104 	addi	fp,sp,4
+int e = 0;
+ 80426a0:	e03fff15 	stw	zero,-4(fp)
+   {
+      dprintf("unable to install VFS NVPARMS, reconfigure nv_formats[]\n");
+      dtrap();
+   }
+#endif   /* INCLUDE_NVPARMS */
+   return e;
+ 80426a4:	e0bfff17 	ldw	r2,-4(fp)
+}
+ 80426a8:	e037883a 	mov	sp,fp
+ 80426ac:	df000017 	ldw	fp,0(sp)
+ 80426b0:	dec00104 	addi	sp,sp,4
+ 80426b4:	f800283a 	ret
+
+080426b8 <alt_get_errno>:
+{
+ 80426b8:	defffe04 	addi	sp,sp,-8
+ 80426bc:	dfc00115 	stw	ra,4(sp)
+ 80426c0:	df000015 	stw	fp,0(sp)
+ 80426c4:	d839883a 	mov	fp,sp
+  return ((alt_errno) ? alt_errno() : &errno);
+ 80426c8:	d0a02717 	ldw	r2,-32612(gp)
+ 80426cc:	10000326 	beq	r2,zero,80426dc <alt_get_errno+0x24>
+ 80426d0:	d0a02717 	ldw	r2,-32612(gp)
+ 80426d4:	103ee83a 	callr	r2
+ 80426d8:	00000106 	br	80426e0 <alt_get_errno+0x28>
+ 80426dc:	d0a04204 	addi	r2,gp,-32504
+}
+ 80426e0:	e037883a 	mov	sp,fp
+ 80426e4:	dfc00117 	ldw	ra,4(sp)
+ 80426e8:	df000017 	ldw	fp,0(sp)
+ 80426ec:	dec00204 	addi	sp,sp,8
+ 80426f0:	f800283a 	ret
+
+080426f4 <alt_fcntl>:
+ *
+ * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h
+ */
+ 
+int ALT_FCNTL (int file, int cmd, ...)
+{ 
+ 80426f4:	defff704 	addi	sp,sp,-36
+ 80426f8:	dfc00615 	stw	ra,24(sp)
+ 80426fc:	df000515 	stw	fp,20(sp)
+ 8042700:	df000504 	addi	fp,sp,20
+ 8042704:	e13ffc15 	stw	r4,-16(fp)
+ 8042708:	e17ffb15 	stw	r5,-20(fp)
+ 804270c:	e1800215 	stw	r6,8(fp)
+ 8042710:	e1c00315 	stw	r7,12(fp)
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+ 8042714:	e0bffc17 	ldw	r2,-16(fp)
+ 8042718:	10000616 	blt	r2,zero,8042734 <alt_fcntl+0x40>
+ 804271c:	e0bffc17 	ldw	r2,-16(fp)
+ 8042720:	10c00324 	muli	r3,r2,12
+ 8042724:	00820174 	movhi	r2,2053
+ 8042728:	10b21a04 	addi	r2,r2,-14232
+ 804272c:	1885883a 	add	r2,r3,r2
+ 8042730:	00000106 	br	8042738 <alt_fcntl+0x44>
+ 8042734:	0005883a 	mov	r2,zero
+ 8042738:	e0bfff15 	stw	r2,-4(fp)
+  
+  if (fd)
+ 804273c:	e0bfff17 	ldw	r2,-4(fp)
+ 8042740:	10002b26 	beq	r2,zero,80427f0 <alt_fcntl+0xfc>
+  {
+    switch (cmd)
+ 8042744:	e0bffb17 	ldw	r2,-20(fp)
+ 8042748:	108000e0 	cmpeqi	r2,r2,3
+ 804274c:	1000041e 	bne	r2,zero,8042760 <alt_fcntl+0x6c>
+ 8042750:	e0bffb17 	ldw	r2,-20(fp)
+ 8042754:	10800120 	cmpeqi	r2,r2,4
+ 8042758:	1000071e 	bne	r2,zero,8042778 <alt_fcntl+0x84>
+ 804275c:	00001e06 	br	80427d8 <alt_fcntl+0xe4>
+    {
+    case F_GETFL:
+      return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK);
+ 8042760:	e0bfff17 	ldw	r2,-4(fp)
+ 8042764:	10c00217 	ldw	r3,8(r2)
+ 8042768:	00900034 	movhi	r2,16384
+ 804276c:	10bfffc4 	addi	r2,r2,-1
+ 8042770:	1884703a 	and	r2,r3,r2
+ 8042774:	00002306 	br	8042804 <alt_fcntl+0x110>
+    case F_SETFL:
+      va_start(argp, cmd);
+ 8042778:	e0800204 	addi	r2,fp,8
+ 804277c:	e0bffd15 	stw	r2,-12(fp)
+      flags = va_arg(argp, long);
+ 8042780:	e0bffd17 	ldw	r2,-12(fp)
+ 8042784:	10c00104 	addi	r3,r2,4
+ 8042788:	e0fffd15 	stw	r3,-12(fp)
+ 804278c:	10800017 	ldw	r2,0(r2)
+ 8042790:	e0bffe15 	stw	r2,-8(fp)
+      fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK;
+ 8042794:	e0bfff17 	ldw	r2,-4(fp)
+ 8042798:	10c00217 	ldw	r3,8(r2)
+ 804279c:	00affdc4 	movi	r2,-16393
+ 80427a0:	1886703a 	and	r3,r3,r2
+ 80427a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80427a8:	10c00215 	stw	r3,8(r2)
+      fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK);
+ 80427ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80427b0:	10800217 	ldw	r2,8(r2)
+ 80427b4:	1007883a 	mov	r3,r2
+ 80427b8:	e0bffe17 	ldw	r2,-8(fp)
+ 80427bc:	1090020c 	andi	r2,r2,16392
+ 80427c0:	1884b03a 	or	r2,r3,r2
+ 80427c4:	1007883a 	mov	r3,r2
+ 80427c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80427cc:	10c00215 	stw	r3,8(r2)
+      va_end(argp);
+      return 0;
+ 80427d0:	0005883a 	mov	r2,zero
+ 80427d4:	00000b06 	br	8042804 <alt_fcntl+0x110>
+    default:
+      ALT_ERRNO = EINVAL;
+ 80427d8:	80426b80 	call	80426b8 <alt_get_errno>
+ 80427dc:	1007883a 	mov	r3,r2
+ 80427e0:	00800584 	movi	r2,22
+ 80427e4:	18800015 	stw	r2,0(r3)
+      return -1;
+ 80427e8:	00bfffc4 	movi	r2,-1
+ 80427ec:	00000506 	br	8042804 <alt_fcntl+0x110>
+    }
+  }
+
+  ALT_ERRNO = EBADFD;
+ 80427f0:	80426b80 	call	80426b8 <alt_get_errno>
+ 80427f4:	1007883a 	mov	r3,r2
+ 80427f8:	00801444 	movi	r2,81
+ 80427fc:	18800015 	stw	r2,0(r3)
+  return -1;
+ 8042800:	00bfffc4 	movi	r2,-1
+}
+ 8042804:	e037883a 	mov	sp,fp
+ 8042808:	dfc00117 	ldw	ra,4(sp)
+ 804280c:	df000017 	ldw	fp,0(sp)
+ 8042810:	dec00404 	addi	sp,sp,16
+ 8042814:	f800283a 	ret
+
+08042818 <alt_find_file>:
+ * either '/' or '\0' is the prefix of the filename. For example the filename:
+ * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". 
+ */
+ 
+alt_dev* alt_find_file (const char* name)
+{
+ 8042818:	defffb04 	addi	sp,sp,-20
+ 804281c:	dfc00415 	stw	ra,16(sp)
+ 8042820:	df000315 	stw	fp,12(sp)
+ 8042824:	df000304 	addi	fp,sp,12
+ 8042828:	e13ffd15 	stw	r4,-12(fp)
+  alt_dev* next = (alt_dev*) alt_fs_list.next;   
+ 804282c:	d0a02217 	ldw	r2,-32632(gp)
+ 8042830:	e0bfff15 	stw	r2,-4(fp)
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+ 
+  while (next != (alt_dev*) &alt_fs_list)
+ 8042834:	00003106 	br	80428fc <alt_find_file+0xe4>
+  {
+    len = strlen(next->name);
+ 8042838:	e0bfff17 	ldw	r2,-4(fp)
+ 804283c:	10800217 	ldw	r2,8(r2)
+ 8042840:	1009883a 	mov	r4,r2
+ 8042844:	8002dac0 	call	8002dac <strlen>
+ 8042848:	e0bffe15 	stw	r2,-8(fp)
+    
+    if (next->name[len-1] == '/')
+ 804284c:	e0bfff17 	ldw	r2,-4(fp)
+ 8042850:	10c00217 	ldw	r3,8(r2)
+ 8042854:	e0bffe17 	ldw	r2,-8(fp)
+ 8042858:	10bfffc4 	addi	r2,r2,-1
+ 804285c:	1885883a 	add	r2,r3,r2
+ 8042860:	10800003 	ldbu	r2,0(r2)
+ 8042864:	10803fcc 	andi	r2,r2,255
+ 8042868:	1080201c 	xori	r2,r2,128
+ 804286c:	10bfe004 	addi	r2,r2,-128
+ 8042870:	10800bd8 	cmpnei	r2,r2,47
+ 8042874:	1000031e 	bne	r2,zero,8042884 <alt_find_file+0x6c>
+    {
+      len -= 1;
+ 8042878:	e0bffe17 	ldw	r2,-8(fp)
+ 804287c:	10bfffc4 	addi	r2,r2,-1
+ 8042880:	e0bffe15 	stw	r2,-8(fp)
+    }
+
+    if (((name[len] == '/') || (name[len] == '\0')) && 
+ 8042884:	e0bffe17 	ldw	r2,-8(fp)
+ 8042888:	e0fffd17 	ldw	r3,-12(fp)
+ 804288c:	1885883a 	add	r2,r3,r2
+ 8042890:	10800003 	ldbu	r2,0(r2)
+ 8042894:	10803fcc 	andi	r2,r2,255
+ 8042898:	1080201c 	xori	r2,r2,128
+ 804289c:	10bfe004 	addi	r2,r2,-128
+ 80428a0:	10800be0 	cmpeqi	r2,r2,47
+ 80428a4:	1000081e 	bne	r2,zero,80428c8 <alt_find_file+0xb0>
+ 80428a8:	e0bffe17 	ldw	r2,-8(fp)
+ 80428ac:	e0fffd17 	ldw	r3,-12(fp)
+ 80428b0:	1885883a 	add	r2,r3,r2
+ 80428b4:	10800003 	ldbu	r2,0(r2)
+ 80428b8:	10803fcc 	andi	r2,r2,255
+ 80428bc:	1080201c 	xori	r2,r2,128
+ 80428c0:	10bfe004 	addi	r2,r2,-128
+ 80428c4:	10000a1e 	bne	r2,zero,80428f0 <alt_find_file+0xd8>
+        !memcmp (next->name, name, len))
+ 80428c8:	e0bfff17 	ldw	r2,-4(fp)
+ 80428cc:	10800217 	ldw	r2,8(r2)
+ 80428d0:	e0fffe17 	ldw	r3,-8(fp)
+ 80428d4:	180d883a 	mov	r6,r3
+ 80428d8:	e17ffd17 	ldw	r5,-12(fp)
+ 80428dc:	1009883a 	mov	r4,r2
+ 80428e0:	8042cb80 	call	8042cb8 <memcmp>
+    if (((name[len] == '/') || (name[len] == '\0')) && 
+ 80428e4:	1000021e 	bne	r2,zero,80428f0 <alt_find_file+0xd8>
+    {
+      /* match found */
+
+      return next;
+ 80428e8:	e0bfff17 	ldw	r2,-4(fp)
+ 80428ec:	00000706 	br	804290c <alt_find_file+0xf4>
+    }
+    next = (alt_dev*) next->llist.next;
+ 80428f0:	e0bfff17 	ldw	r2,-4(fp)
+ 80428f4:	10800017 	ldw	r2,0(r2)
+ 80428f8:	e0bfff15 	stw	r2,-4(fp)
+  while (next != (alt_dev*) &alt_fs_list)
+ 80428fc:	e0ffff17 	ldw	r3,-4(fp)
+ 8042900:	d0a02204 	addi	r2,gp,-32632
+ 8042904:	18bfcc1e 	bne	r3,r2,8042838 <alt_find_file+0x20>
+  }
+  
+  /* No match found */
+  
+  return NULL;     
+ 8042908:	0005883a 	mov	r2,zero
+}
+ 804290c:	e037883a 	mov	sp,fp
+ 8042910:	dfc00117 	ldw	ra,4(sp)
+ 8042914:	df000017 	ldw	fp,0(sp)
+ 8042918:	dec00204 	addi	sp,sp,8
+ 804291c:	f800283a 	ret
+
+08042920 <alt_get_fd>:
+ * the offset of the file descriptor within the file descriptor array). A
+ * negative value indicates failure.
+ */
+
+int alt_get_fd (alt_dev* dev)
+{
+ 8042920:	defff904 	addi	sp,sp,-28
+ 8042924:	dfc00615 	stw	ra,24(sp)
+ 8042928:	df000515 	stw	fp,20(sp)
+ 804292c:	df000504 	addi	fp,sp,20
+ 8042930:	e13ffb15 	stw	r4,-20(fp)
+  alt_32 i;
+  int rc = -EMFILE;
+ 8042934:	00bffa04 	movi	r2,-24
+ 8042938:	e0bffe15 	stw	r2,-8(fp)
+  /* 
+   * Take the alt_fd_list_lock semaphore in order to avoid races when 
+   * accessing the file descriptor pool.
+   */
+  
+  ALT_SEM_PEND(alt_fd_list_lock, 0);
+ 804293c:	d0a08b17 	ldw	r2,-32212(gp)
+ 8042940:	e0bffd15 	stw	r2,-12(fp)
+ 8042944:	e03ffc8d 	sth	zero,-14(fp)
+  OSSemPend (sem, timeout, &err);
+ 8042948:	e0bffc8b 	ldhu	r2,-14(fp)
+ 804294c:	e0fffc44 	addi	r3,fp,-15
+ 8042950:	180d883a 	mov	r6,r3
+ 8042954:	100b883a 	mov	r5,r2
+ 8042958:	e13ffd17 	ldw	r4,-12(fp)
+ 804295c:	8015a600 	call	8015a60 <OSSemPend>
+   * indicates the highest file descriptor ever allocated. This is used to
+   * improve efficency when searching the file descriptor list, and 
+   * therefore reduce contention on the alt_fd_list_lock semaphore. 
+   */
+
+  for (i = 0; i < ALT_MAX_FD; i++)
+ 8042960:	e03fff15 	stw	zero,-4(fp)
+ 8042964:	00001706 	br	80429c4 <alt_get_fd+0xa4>
+  {
+    if (!alt_fd_list[i].dev)
+ 8042968:	e0bfff17 	ldw	r2,-4(fp)
+ 804296c:	10c00324 	muli	r3,r2,12
+ 8042970:	00820174 	movhi	r2,2053
+ 8042974:	1885883a 	add	r2,r3,r2
+ 8042978:	10b21a17 	ldw	r2,-14232(r2)
+ 804297c:	10000e1e 	bne	r2,zero,80429b8 <alt_get_fd+0x98>
+    {
+      alt_fd_list[i].dev = dev;
+ 8042980:	e0bfff17 	ldw	r2,-4(fp)
+ 8042984:	11000324 	muli	r4,r2,12
+ 8042988:	e0fffb17 	ldw	r3,-20(fp)
+ 804298c:	00820174 	movhi	r2,2053
+ 8042990:	2085883a 	add	r2,r4,r2
+ 8042994:	10f21a15 	stw	r3,-14232(r2)
+      if (i > alt_max_fd)
+ 8042998:	d0e02617 	ldw	r3,-32616(gp)
+ 804299c:	e0bfff17 	ldw	r2,-4(fp)
+ 80429a0:	1880020e 	bge	r3,r2,80429ac <alt_get_fd+0x8c>
+      {
+        alt_max_fd = i;
+ 80429a4:	e0bfff17 	ldw	r2,-4(fp)
+ 80429a8:	d0a02615 	stw	r2,-32616(gp)
+      }
+      rc = i;
+ 80429ac:	e0bfff17 	ldw	r2,-4(fp)
+ 80429b0:	e0bffe15 	stw	r2,-8(fp)
+      goto alt_get_fd_exit;
+ 80429b4:	00000706 	br	80429d4 <alt_get_fd+0xb4>
+  for (i = 0; i < ALT_MAX_FD; i++)
+ 80429b8:	e0bfff17 	ldw	r2,-4(fp)
+ 80429bc:	10800044 	addi	r2,r2,1
+ 80429c0:	e0bfff15 	stw	r2,-4(fp)
+ 80429c4:	e0bfff17 	ldw	r2,-4(fp)
+ 80429c8:	10800410 	cmplti	r2,r2,16
+ 80429cc:	103fe61e 	bne	r2,zero,8042968 <alt_get_fd+0x48>
+    }
+  }
+
+ alt_get_fd_exit:
+ 80429d0:	0001883a 	nop
+  /*
+   * Release the alt_fd_list_lock semaphore now that we are done with the
+   * file descriptor pool.
+   */
+
+  ALT_SEM_POST(alt_fd_list_lock);
+ 80429d4:	d0a08b17 	ldw	r2,-32212(gp)
+ 80429d8:	1009883a 	mov	r4,r2
+ 80429dc:	8015d840 	call	8015d84 <OSSemPost>
+
+  return rc;
+ 80429e0:	e0bffe17 	ldw	r2,-8(fp)
+}
+ 80429e4:	e037883a 	mov	sp,fp
+ 80429e8:	dfc00117 	ldw	ra,4(sp)
+ 80429ec:	df000017 	ldw	fp,0(sp)
+ 80429f0:	dec00204 	addi	sp,sp,8
+ 80429f4:	f800283a 	ret
+
+080429f8 <alt_exception_cause_generated_bad_addr>:
+ * Return: 1: BADADDR (bad_addr argument to handler) is valid
+ *         0: BADADDR is not valid
+ */
+int 
+alt_exception_cause_generated_bad_addr(alt_exception_cause cause)
+{
+ 80429f8:	defffe04 	addi	sp,sp,-8
+ 80429fc:	df000115 	stw	fp,4(sp)
+ 8042a00:	df000104 	addi	fp,sp,4
+ 8042a04:	e13fff15 	stw	r4,-4(fp)
+  switch (cause) {
+ 8042a08:	e0bfff17 	ldw	r2,-4(fp)
+ 8042a0c:	10bffe84 	addi	r2,r2,-6
+ 8042a10:	10c00428 	cmpgeui	r3,r2,16
+ 8042a14:	1800191e 	bne	r3,zero,8042a7c <alt_exception_cause_generated_bad_addr+0x84>
+ 8042a18:	100690ba 	slli	r3,r2,2
+ 8042a1c:	00820134 	movhi	r2,2052
+ 8042a20:	1885883a 	add	r2,r3,r2
+ 8042a24:	108a8b17 	ldw	r2,10796(r2)
+ 8042a28:	1000683a 	jmp	r2
+ 8042a2c:	08042a6c 	andhi	zero,at,4265
+ 8042a30:	08042a6c 	andhi	zero,at,4265
+ 8042a34:	08042a7c 	xorhi	zero,at,4265
+ 8042a38:	08042a7c 	xorhi	zero,at,4265
+ 8042a3c:	08042a7c 	xorhi	zero,at,4265
+ 8042a40:	08042a6c 	andhi	zero,at,4265
+ 8042a44:	08042a74 	orhi	zero,at,4265
+ 8042a48:	08042a7c 	xorhi	zero,at,4265
+ 8042a4c:	08042a6c 	andhi	zero,at,4265
+ 8042a50:	08042a6c 	andhi	zero,at,4265
+ 8042a54:	08042a7c 	xorhi	zero,at,4265
+ 8042a58:	08042a6c 	andhi	zero,at,4265
+ 8042a5c:	08042a74 	orhi	zero,at,4265
+ 8042a60:	08042a7c 	xorhi	zero,at,4265
+ 8042a64:	08042a7c 	xorhi	zero,at,4265
+ 8042a68:	08042a6c 	andhi	zero,at,4265
+  case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC:
+  case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION:
+  case NIOS2_EXCEPTION_ECC_DATA_ERR:
+    return 1;
+ 8042a6c:	00800044 	movi	r2,1
+ 8042a70:	00000306 	br	8042a80 <alt_exception_cause_generated_bad_addr+0x88>
+
+  case NIOS2_EXCEPTION_TLB_MISS:
+  case NIOS2_EXCEPTION_ECC_TLB_ERR:
+    return 0;
+ 8042a74:	0005883a 	mov	r2,zero
+ 8042a78:	00000106 	br	8042a80 <alt_exception_cause_generated_bad_addr+0x88>
+
+  default:
+    return 0;
+ 8042a7c:	0005883a 	mov	r2,zero
+  }
+}
+ 8042a80:	e037883a 	mov	sp,fp
+ 8042a84:	df000017 	ldw	fp,0(sp)
+ 8042a88:	dec00104 	addi	sp,sp,4
+ 8042a8c:	f800283a 	ret
+
+08042a90 <atexit>:
+ 8042a90:	200b883a 	mov	r5,r4
+ 8042a94:	000f883a 	mov	r7,zero
+ 8042a98:	000d883a 	mov	r6,zero
+ 8042a9c:	0009883a 	mov	r4,zero
+ 8042aa0:	80454e81 	jmpi	80454e8 <__register_exitproc>
+
+08042aa4 <atoi>:
+ 8042aa4:	01800284 	movi	r6,10
+ 8042aa8:	000b883a 	mov	r5,zero
+ 8042aac:	80433281 	jmpi	8043328 <strtol>
+
+08042ab0 <_atoi_r>:
+ 8042ab0:	01c00284 	movi	r7,10
+ 8042ab4:	000d883a 	mov	r6,zero
+ 8042ab8:	804330c1 	jmpi	804330c <_strtol_r>
+
+08042abc <exit>:
+ 8042abc:	defffe04 	addi	sp,sp,-8
+ 8042ac0:	000b883a 	mov	r5,zero
+ 8042ac4:	dc000015 	stw	r16,0(sp)
+ 8042ac8:	dfc00115 	stw	ra,4(sp)
+ 8042acc:	2021883a 	mov	r16,r4
+ 8042ad0:	80455780 	call	8045578 <__call_exitprocs>
+ 8042ad4:	00820174 	movhi	r2,2053
+ 8042ad8:	1132ae17 	ldw	r4,-13640(r2)
+ 8042adc:	20800f17 	ldw	r2,60(r4)
+ 8042ae0:	10000126 	beq	r2,zero,8042ae8 <exit+0x2c>
+ 8042ae4:	103ee83a 	callr	r2
+ 8042ae8:	8009883a 	mov	r4,r16
+ 8042aec:	80469740 	call	8046974 <_exit>
+
+08042af0 <memalign>:
+ 8042af0:	00820174 	movhi	r2,2053
+ 8042af4:	280d883a 	mov	r6,r5
+ 8042af8:	200b883a 	mov	r5,r4
+ 8042afc:	1132af17 	ldw	r4,-13636(r2)
+ 8042b00:	8042b041 	jmpi	8042b04 <_memalign_r>
+
+08042b04 <_memalign_r>:
+ 8042b04:	28800268 	cmpgeui	r2,r5,9
+ 8042b08:	10005226 	beq	r2,zero,8042c54 <_memalign_r+0x150>
+ 8042b0c:	defffa04 	addi	sp,sp,-24
+ 8042b10:	dc400115 	stw	r17,4(sp)
+ 8042b14:	344002c4 	addi	r17,r6,11
+ 8042b18:	dcc00315 	stw	r19,12(sp)
+ 8042b1c:	dfc00515 	stw	ra,20(sp)
+ 8042b20:	dd000415 	stw	r20,16(sp)
+ 8042b24:	dc800215 	stw	r18,8(sp)
+ 8042b28:	dc000015 	stw	r16,0(sp)
+ 8042b2c:	888005f0 	cmpltui	r2,r17,23
+ 8042b30:	2027883a 	mov	r19,r4
+ 8042b34:	1000391e 	bne	r2,zero,8042c1c <_memalign_r+0x118>
+ 8042b38:	00bffe04 	movi	r2,-8
+ 8042b3c:	88a2703a 	and	r17,r17,r2
+ 8042b40:	88003816 	blt	r17,zero,8042c24 <_memalign_r+0x120>
+ 8042b44:	89803736 	bltu	r17,r6,8042c24 <_memalign_r+0x120>
+ 8042b48:	28800428 	cmpgeui	r2,r5,16
+ 8042b4c:	2821883a 	mov	r16,r5
+ 8042b50:	1000011e 	bne	r2,zero,8042b58 <_memalign_r+0x54>
+ 8042b54:	04000404 	movi	r16,16
+ 8042b58:	81400404 	addi	r5,r16,16
+ 8042b5c:	2c4b883a 	add	r5,r5,r17
+ 8042b60:	9809883a 	mov	r4,r19
+ 8042b64:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8042b68:	1025883a 	mov	r18,r2
+ 8042b6c:	10003026 	beq	r2,zero,8042c30 <_memalign_r+0x12c>
+ 8042b70:	9809883a 	mov	r4,r19
+ 8042b74:	800fe0c0 	call	800fe0c <__malloc_lock>
+ 8042b78:	800b883a 	mov	r5,r16
+ 8042b7c:	9009883a 	mov	r4,r18
+ 8042b80:	953ffe04 	addi	r20,r18,-8
+ 8042b84:	800d05c0 	call	800d05c <__umodsi3>
+ 8042b88:	10001b26 	beq	r2,zero,8042bf8 <_memalign_r+0xf4>
+ 8042b8c:	817fffc4 	addi	r5,r16,-1
+ 8042b90:	0405c83a 	sub	r2,zero,r16
+ 8042b94:	914b883a 	add	r5,r18,r5
+ 8042b98:	288a703a 	and	r5,r5,r2
+ 8042b9c:	297ffe04 	addi	r5,r5,-8
+ 8042ba0:	2d07c83a 	sub	r3,r5,r20
+ 8042ba4:	18800408 	cmpgei	r2,r3,16
+ 8042ba8:	10002c26 	beq	r2,zero,8042c5c <_memalign_r+0x158>
+ 8042bac:	2829883a 	mov	r20,r5
+ 8042bb0:	90bfff17 	ldw	r2,-4(r18)
+ 8042bb4:	013fff04 	movi	r4,-4
+ 8042bb8:	900b883a 	mov	r5,r18
+ 8042bbc:	1104703a 	and	r2,r2,r4
+ 8042bc0:	10c5c83a 	sub	r2,r2,r3
+ 8042bc4:	11000054 	ori	r4,r2,1
+ 8042bc8:	a1000115 	stw	r4,4(r20)
+ 8042bcc:	a085883a 	add	r2,r20,r2
+ 8042bd0:	11800117 	ldw	r6,4(r2)
+ 8042bd4:	9809883a 	mov	r4,r19
+ 8042bd8:	31800054 	ori	r6,r6,1
+ 8042bdc:	11800115 	stw	r6,4(r2)
+ 8042be0:	90bfff17 	ldw	r2,-4(r18)
+ 8042be4:	1080004c 	andi	r2,r2,1
+ 8042be8:	10c4b03a 	or	r2,r2,r3
+ 8042bec:	90bfff15 	stw	r2,-4(r18)
+ 8042bf0:	80071c40 	call	80071c4 <_free_r>
+ 8042bf4:	a4800204 	addi	r18,r20,8
+ 8042bf8:	a0800117 	ldw	r2,4(r20)
+ 8042bfc:	00ffff04 	movi	r3,-4
+ 8042c00:	10c4703a 	and	r2,r2,r3
+ 8042c04:	1445c83a 	sub	r2,r2,r17
+ 8042c08:	10c00410 	cmplti	r3,r2,16
+ 8042c0c:	18001726 	beq	r3,zero,8042c6c <_memalign_r+0x168>
+ 8042c10:	9809883a 	mov	r4,r19
+ 8042c14:	800ff2c0 	call	800ff2c <__malloc_unlock>
+ 8042c18:	00000506 	br	8042c30 <_memalign_r+0x12c>
+ 8042c1c:	04400404 	movi	r17,16
+ 8042c20:	89bfc92e 	bgeu	r17,r6,8042b48 <_memalign_r+0x44>
+ 8042c24:	00800304 	movi	r2,12
+ 8042c28:	98800015 	stw	r2,0(r19)
+ 8042c2c:	0025883a 	mov	r18,zero
+ 8042c30:	9005883a 	mov	r2,r18
+ 8042c34:	dfc00517 	ldw	ra,20(sp)
+ 8042c38:	dd000417 	ldw	r20,16(sp)
+ 8042c3c:	dcc00317 	ldw	r19,12(sp)
+ 8042c40:	dc800217 	ldw	r18,8(sp)
+ 8042c44:	dc400117 	ldw	r17,4(sp)
+ 8042c48:	dc000017 	ldw	r16,0(sp)
+ 8042c4c:	dec00604 	addi	sp,sp,24
+ 8042c50:	f800283a 	ret
+ 8042c54:	300b883a 	mov	r5,r6
+ 8042c58:	8007ddc1 	jmpi	8007ddc <_malloc_r>
+ 8042c5c:	2c0b883a 	add	r5,r5,r16
+ 8042c60:	2d07c83a 	sub	r3,r5,r20
+ 8042c64:	2829883a 	mov	r20,r5
+ 8042c68:	003fd106 	br	8042bb0 <_memalign_r+0xac>
+ 8042c6c:	a44b883a 	add	r5,r20,r17
+ 8042c70:	10800054 	ori	r2,r2,1
+ 8042c74:	28800115 	stw	r2,4(r5)
+ 8042c78:	a0800117 	ldw	r2,4(r20)
+ 8042c7c:	29400204 	addi	r5,r5,8
+ 8042c80:	9809883a 	mov	r4,r19
+ 8042c84:	1080004c 	andi	r2,r2,1
+ 8042c88:	1462b03a 	or	r17,r2,r17
+ 8042c8c:	a4400115 	stw	r17,4(r20)
+ 8042c90:	80071c40 	call	80071c4 <_free_r>
+ 8042c94:	003fde06 	br	8042c10 <_memalign_r+0x10c>
+
+08042c98 <malloc>:
+ 8042c98:	00820174 	movhi	r2,2053
+ 8042c9c:	200b883a 	mov	r5,r4
+ 8042ca0:	1132af17 	ldw	r4,-13636(r2)
+ 8042ca4:	8007ddc1 	jmpi	8007ddc <_malloc_r>
+
+08042ca8 <free>:
+ 8042ca8:	00820174 	movhi	r2,2053
+ 8042cac:	200b883a 	mov	r5,r4
+ 8042cb0:	1132af17 	ldw	r4,-13636(r2)
+ 8042cb4:	80071c41 	jmpi	80071c4 <_free_r>
+
+08042cb8 <memcmp>:
+ 8042cb8:	30800130 	cmpltui	r2,r6,4
+ 8042cbc:	10000b1e 	bne	r2,zero,8042cec <memcmp+0x34>
+ 8042cc0:	2144b03a 	or	r2,r4,r5
+ 8042cc4:	108000cc 	andi	r2,r2,3
+ 8042cc8:	10001a1e 	bne	r2,zero,8042d34 <memcmp+0x7c>
+ 8042ccc:	20c00017 	ldw	r3,0(r4)
+ 8042cd0:	28800017 	ldw	r2,0(r5)
+ 8042cd4:	1880171e 	bne	r3,r2,8042d34 <memcmp+0x7c>
+ 8042cd8:	31bfff04 	addi	r6,r6,-4
+ 8042cdc:	30800128 	cmpgeui	r2,r6,4
+ 8042ce0:	21000104 	addi	r4,r4,4
+ 8042ce4:	29400104 	addi	r5,r5,4
+ 8042ce8:	103ff81e 	bne	r2,zero,8042ccc <memcmp+0x14>
+ 8042cec:	30ffffc4 	addi	r3,r6,-1
+ 8042cf0:	30000e26 	beq	r6,zero,8042d2c <memcmp+0x74>
+ 8042cf4:	29800003 	ldbu	r6,0(r5)
+ 8042cf8:	20800003 	ldbu	r2,0(r4)
+ 8042cfc:	30800f1e 	bne	r6,r2,8042d3c <memcmp+0x84>
+ 8042d00:	18800044 	addi	r2,r3,1
+ 8042d04:	20c00044 	addi	r3,r4,1
+ 8042d08:	2089883a 	add	r4,r4,r2
+ 8042d0c:	00000506 	br	8042d24 <memcmp+0x6c>
+ 8042d10:	18800003 	ldbu	r2,0(r3)
+ 8042d14:	29800003 	ldbu	r6,0(r5)
+ 8042d18:	18c00044 	addi	r3,r3,1
+ 8042d1c:	10803fcc 	andi	r2,r2,255
+ 8042d20:	1180061e 	bne	r2,r6,8042d3c <memcmp+0x84>
+ 8042d24:	29400044 	addi	r5,r5,1
+ 8042d28:	193ff91e 	bne	r3,r4,8042d10 <memcmp+0x58>
+ 8042d2c:	0005883a 	mov	r2,zero
+ 8042d30:	f800283a 	ret
+ 8042d34:	30ffffc4 	addi	r3,r6,-1
+ 8042d38:	003fee06 	br	8042cf4 <memcmp+0x3c>
+ 8042d3c:	1185c83a 	sub	r2,r2,r6
+ 8042d40:	f800283a 	ret
+
+08042d44 <_sprintf_r>:
+ 8042d44:	deffe404 	addi	sp,sp,-112
+ 8042d48:	2811883a 	mov	r8,r5
+ 8042d4c:	dfc01a15 	stw	ra,104(sp)
+ 8042d50:	d9c01b15 	stw	r7,108(sp)
+ 8042d54:	00a00034 	movhi	r2,32768
+ 8042d58:	00fffff4 	movhi	r3,65535
+ 8042d5c:	10bfffc4 	addi	r2,r2,-1
+ 8042d60:	18c08204 	addi	r3,r3,520
+ 8042d64:	d9c01b04 	addi	r7,sp,108
+ 8042d68:	d80b883a 	mov	r5,sp
+ 8042d6c:	d8c00315 	stw	r3,12(sp)
+ 8042d70:	da000015 	stw	r8,0(sp)
+ 8042d74:	da000415 	stw	r8,16(sp)
+ 8042d78:	d8800515 	stw	r2,20(sp)
+ 8042d7c:	d8800215 	stw	r2,8(sp)
+ 8042d80:	80433400 	call	8043340 <___svfprintf_internal_r>
+ 8042d84:	d8c00017 	ldw	r3,0(sp)
+ 8042d88:	18000005 	stb	zero,0(r3)
+ 8042d8c:	dfc01a17 	ldw	ra,104(sp)
+ 8042d90:	dec01c04 	addi	sp,sp,112
+ 8042d94:	f800283a 	ret
+
+08042d98 <sprintf>:
+ 8042d98:	deffe304 	addi	sp,sp,-116
+ 8042d9c:	2011883a 	mov	r8,r4
+ 8042da0:	dfc01a15 	stw	ra,104(sp)
+ 8042da4:	d9801b15 	stw	r6,108(sp)
+ 8042da8:	d9c01c15 	stw	r7,112(sp)
+ 8042dac:	00820174 	movhi	r2,2053
+ 8042db0:	1132af17 	ldw	r4,-13636(r2)
+ 8042db4:	00fffff4 	movhi	r3,65535
+ 8042db8:	00a00034 	movhi	r2,32768
+ 8042dbc:	10bfffc4 	addi	r2,r2,-1
+ 8042dc0:	18c08204 	addi	r3,r3,520
+ 8042dc4:	280d883a 	mov	r6,r5
+ 8042dc8:	d9c01b04 	addi	r7,sp,108
+ 8042dcc:	d80b883a 	mov	r5,sp
+ 8042dd0:	d8c00315 	stw	r3,12(sp)
+ 8042dd4:	da000015 	stw	r8,0(sp)
+ 8042dd8:	da000415 	stw	r8,16(sp)
+ 8042ddc:	d8800515 	stw	r2,20(sp)
+ 8042de0:	d8800215 	stw	r2,8(sp)
+ 8042de4:	80433400 	call	8043340 <___svfprintf_internal_r>
+ 8042de8:	d8c00017 	ldw	r3,0(sp)
+ 8042dec:	18000005 	stb	zero,0(r3)
+ 8042df0:	dfc01a17 	ldw	ra,104(sp)
+ 8042df4:	dec01d04 	addi	sp,sp,116
+ 8042df8:	f800283a 	ret
+
+08042dfc <strchr>:
+ 8042dfc:	2a403fcc 	andi	r9,r5,255
+ 8042e00:	2811883a 	mov	r8,r5
+ 8042e04:	208000cc 	andi	r2,r4,3
+ 8042e08:	48003726 	beq	r9,zero,8042ee8 <strchr+0xec>
+ 8042e0c:	10000b26 	beq	r2,zero,8042e3c <strchr+0x40>
+ 8042e10:	20800003 	ldbu	r2,0(r4)
+ 8042e14:	10003226 	beq	r2,zero,8042ee0 <strchr+0xe4>
+ 8042e18:	48804f26 	beq	r9,r2,8042f58 <strchr+0x15c>
+ 8042e1c:	4807883a 	mov	r3,r9
+ 8042e20:	00000306 	br	8042e30 <strchr+0x34>
+ 8042e24:	20800003 	ldbu	r2,0(r4)
+ 8042e28:	10002d26 	beq	r2,zero,8042ee0 <strchr+0xe4>
+ 8042e2c:	10c04a26 	beq	r2,r3,8042f58 <strchr+0x15c>
+ 8042e30:	21000044 	addi	r4,r4,1
+ 8042e34:	208000cc 	andi	r2,r4,3
+ 8042e38:	103ffa1e 	bne	r2,zero,8042e24 <strchr+0x28>
+ 8042e3c:	29403fcc 	andi	r5,r5,255
+ 8042e40:	2804923a 	slli	r2,r5,8
+ 8042e44:	20c00017 	ldw	r3,0(r4)
+ 8042e48:	01ffbff4 	movhi	r7,65279
+ 8042e4c:	288ab03a 	or	r5,r5,r2
+ 8042e50:	2816943a 	slli	r11,r5,16
+ 8042e54:	39ffbfc4 	addi	r7,r7,-257
+ 8042e58:	19c5883a 	add	r2,r3,r7
+ 8042e5c:	5956b03a 	or	r11,r11,r5
+ 8042e60:	58caf03a 	xor	r5,r11,r3
+ 8042e64:	29cd883a 	add	r6,r5,r7
+ 8042e68:	00c6303a 	nor	r3,zero,r3
+ 8042e6c:	014a303a 	nor	r5,zero,r5
+ 8042e70:	10c4703a 	and	r2,r2,r3
+ 8042e74:	314a703a 	and	r5,r6,r5
+ 8042e78:	02a02074 	movhi	r10,32897
+ 8042e7c:	1144b03a 	or	r2,r2,r5
+ 8042e80:	52a02004 	addi	r10,r10,-32640
+ 8042e84:	1284703a 	and	r2,r2,r10
+ 8042e88:	10000c1e 	bne	r2,zero,8042ebc <strchr+0xc0>
+ 8042e8c:	21000104 	addi	r4,r4,4
+ 8042e90:	20c00017 	ldw	r3,0(r4)
+ 8042e94:	1acaf03a 	xor	r5,r3,r11
+ 8042e98:	19c5883a 	add	r2,r3,r7
+ 8042e9c:	29cd883a 	add	r6,r5,r7
+ 8042ea0:	00c6303a 	nor	r3,zero,r3
+ 8042ea4:	014a303a 	nor	r5,zero,r5
+ 8042ea8:	10c4703a 	and	r2,r2,r3
+ 8042eac:	314a703a 	and	r5,r6,r5
+ 8042eb0:	1144b03a 	or	r2,r2,r5
+ 8042eb4:	1284703a 	and	r2,r2,r10
+ 8042eb8:	103ff426 	beq	r2,zero,8042e8c <strchr+0x90>
+ 8042ebc:	20800003 	ldbu	r2,0(r4)
+ 8042ec0:	10000726 	beq	r2,zero,8042ee0 <strchr+0xe4>
+ 8042ec4:	48802426 	beq	r9,r2,8042f58 <strchr+0x15c>
+ 8042ec8:	42003fcc 	andi	r8,r8,255
+ 8042ecc:	00000106 	br	8042ed4 <strchr+0xd8>
+ 8042ed0:	12002126 	beq	r2,r8,8042f58 <strchr+0x15c>
+ 8042ed4:	21000044 	addi	r4,r4,1
+ 8042ed8:	20800003 	ldbu	r2,0(r4)
+ 8042edc:	103ffc1e 	bne	r2,zero,8042ed0 <strchr+0xd4>
+ 8042ee0:	0005883a 	mov	r2,zero
+ 8042ee4:	f800283a 	ret
+ 8042ee8:	10000526 	beq	r2,zero,8042f00 <strchr+0x104>
+ 8042eec:	20800003 	ldbu	r2,0(r4)
+ 8042ef0:	10001926 	beq	r2,zero,8042f58 <strchr+0x15c>
+ 8042ef4:	21000044 	addi	r4,r4,1
+ 8042ef8:	208000cc 	andi	r2,r4,3
+ 8042efc:	103ffb1e 	bne	r2,zero,8042eec <strchr+0xf0>
+ 8042f00:	20c00017 	ldw	r3,0(r4)
+ 8042f04:	01bfbff4 	movhi	r6,65279
+ 8042f08:	31bfbfc4 	addi	r6,r6,-257
+ 8042f0c:	1985883a 	add	r2,r3,r6
+ 8042f10:	01602074 	movhi	r5,32897
+ 8042f14:	00c6303a 	nor	r3,zero,r3
+ 8042f18:	10c4703a 	and	r2,r2,r3
+ 8042f1c:	29602004 	addi	r5,r5,-32640
+ 8042f20:	1144703a 	and	r2,r2,r5
+ 8042f24:	1000071e 	bne	r2,zero,8042f44 <strchr+0x148>
+ 8042f28:	21000104 	addi	r4,r4,4
+ 8042f2c:	20c00017 	ldw	r3,0(r4)
+ 8042f30:	1985883a 	add	r2,r3,r6
+ 8042f34:	00c6303a 	nor	r3,zero,r3
+ 8042f38:	10c4703a 	and	r2,r2,r3
+ 8042f3c:	1144703a 	and	r2,r2,r5
+ 8042f40:	103ff926 	beq	r2,zero,8042f28 <strchr+0x12c>
+ 8042f44:	20800003 	ldbu	r2,0(r4)
+ 8042f48:	10000326 	beq	r2,zero,8042f58 <strchr+0x15c>
+ 8042f4c:	21000044 	addi	r4,r4,1
+ 8042f50:	20800003 	ldbu	r2,0(r4)
+ 8042f54:	103ffd1e 	bne	r2,zero,8042f4c <strchr+0x150>
+ 8042f58:	2005883a 	mov	r2,r4
+ 8042f5c:	f800283a 	ret
+
+08042f60 <strcpy>:
+ 8042f60:	2906b03a 	or	r3,r5,r4
+ 8042f64:	18c000cc 	andi	r3,r3,3
+ 8042f68:	2005883a 	mov	r2,r4
+ 8042f6c:	18001d1e 	bne	r3,zero,8042fe4 <strcpy+0x84>
+ 8042f70:	29c00017 	ldw	r7,0(r5)
+ 8042f74:	02bfbff4 	movhi	r10,65279
+ 8042f78:	52bfbfc4 	addi	r10,r10,-257
+ 8042f7c:	3a87883a 	add	r3,r7,r10
+ 8042f80:	01c8303a 	nor	r4,zero,r7
+ 8042f84:	02602074 	movhi	r9,32897
+ 8042f88:	1906703a 	and	r3,r3,r4
+ 8042f8c:	4a602004 	addi	r9,r9,-32640
+ 8042f90:	1a46703a 	and	r3,r3,r9
+ 8042f94:	100d883a 	mov	r6,r2
+ 8042f98:	1800091e 	bne	r3,zero,8042fc0 <strcpy+0x60>
+ 8042f9c:	31800104 	addi	r6,r6,4
+ 8042fa0:	29400104 	addi	r5,r5,4
+ 8042fa4:	31ffff15 	stw	r7,-4(r6)
+ 8042fa8:	29c00017 	ldw	r7,0(r5)
+ 8042fac:	3a87883a 	add	r3,r7,r10
+ 8042fb0:	01d0303a 	nor	r8,zero,r7
+ 8042fb4:	1a06703a 	and	r3,r3,r8
+ 8042fb8:	1a46703a 	and	r3,r3,r9
+ 8042fbc:	183ff726 	beq	r3,zero,8042f9c <strcpy+0x3c>
+ 8042fc0:	29400044 	addi	r5,r5,1
+ 8042fc4:	28ffffc3 	ldbu	r3,-1(r5)
+ 8042fc8:	31800044 	addi	r6,r6,1
+ 8042fcc:	30ffffc5 	stb	r3,-1(r6)
+ 8042fd0:	18c03fcc 	andi	r3,r3,255
+ 8042fd4:	18c0201c 	xori	r3,r3,128
+ 8042fd8:	18ffe004 	addi	r3,r3,-128
+ 8042fdc:	183ff81e 	bne	r3,zero,8042fc0 <strcpy+0x60>
+ 8042fe0:	f800283a 	ret
+ 8042fe4:	200d883a 	mov	r6,r4
+ 8042fe8:	003ff506 	br	8042fc0 <strcpy+0x60>
+
+08042fec <strncmp>:
+ 8042fec:	30003726 	beq	r6,zero,80430cc <strncmp+0xe0>
+ 8042ff0:	2144b03a 	or	r2,r4,r5
+ 8042ff4:	108000cc 	andi	r2,r2,3
+ 8042ff8:	10001f1e 	bne	r2,zero,8043078 <strncmp+0x8c>
+ 8042ffc:	30800130 	cmpltui	r2,r6,4
+ 8043000:	10001d1e 	bne	r2,zero,8043078 <strncmp+0x8c>
+ 8043004:	20800017 	ldw	r2,0(r4)
+ 8043008:	28c00017 	ldw	r3,0(r5)
+ 804300c:	10c0311e 	bne	r2,r3,80430d4 <strncmp+0xe8>
+ 8043010:	31bfff04 	addi	r6,r6,-4
+ 8043014:	30002d26 	beq	r6,zero,80430cc <strncmp+0xe0>
+ 8043018:	02bfbff4 	movhi	r10,65279
+ 804301c:	52bfbfc4 	addi	r10,r10,-257
+ 8043020:	1287883a 	add	r3,r2,r10
+ 8043024:	02602074 	movhi	r9,32897
+ 8043028:	0084303a 	nor	r2,zero,r2
+ 804302c:	1884703a 	and	r2,r3,r2
+ 8043030:	4a602004 	addi	r9,r9,-32640
+ 8043034:	1244703a 	and	r2,r2,r9
+ 8043038:	10000b26 	beq	r2,zero,8043068 <strncmp+0x7c>
+ 804303c:	00002306 	br	80430cc <strncmp+0xe0>
+ 8043040:	20c00017 	ldw	r3,0(r4)
+ 8043044:	29c00017 	ldw	r7,0(r5)
+ 8043048:	1a85883a 	add	r2,r3,r10
+ 804304c:	00d0303a 	nor	r8,zero,r3
+ 8043050:	1204703a 	and	r2,r2,r8
+ 8043054:	1244703a 	and	r2,r2,r9
+ 8043058:	19c01e1e 	bne	r3,r7,80430d4 <strncmp+0xe8>
+ 804305c:	31bfff04 	addi	r6,r6,-4
+ 8043060:	30001a26 	beq	r6,zero,80430cc <strncmp+0xe0>
+ 8043064:	1000191e 	bne	r2,zero,80430cc <strncmp+0xe0>
+ 8043068:	30800130 	cmpltui	r2,r6,4
+ 804306c:	21000104 	addi	r4,r4,4
+ 8043070:	29400104 	addi	r5,r5,4
+ 8043074:	103ff226 	beq	r2,zero,8043040 <strncmp+0x54>
+ 8043078:	20800007 	ldb	r2,0(r4)
+ 804307c:	28c00007 	ldb	r3,0(r5)
+ 8043080:	31bfffc4 	addi	r6,r6,-1
+ 8043084:	10c00d1e 	bne	r2,r3,80430bc <strncmp+0xd0>
+ 8043088:	30001026 	beq	r6,zero,80430cc <strncmp+0xe0>
+ 804308c:	10000f26 	beq	r2,zero,80430cc <strncmp+0xe0>
+ 8043090:	20800044 	addi	r2,r4,1
+ 8043094:	218d883a 	add	r6,r4,r6
+ 8043098:	00000306 	br	80430a8 <strncmp+0xbc>
+ 804309c:	11800b26 	beq	r2,r6,80430cc <strncmp+0xe0>
+ 80430a0:	10800044 	addi	r2,r2,1
+ 80430a4:	18000926 	beq	r3,zero,80430cc <strncmp+0xe0>
+ 80430a8:	29400044 	addi	r5,r5,1
+ 80430ac:	10c00007 	ldb	r3,0(r2)
+ 80430b0:	29c00007 	ldb	r7,0(r5)
+ 80430b4:	1009883a 	mov	r4,r2
+ 80430b8:	19fff826 	beq	r3,r7,804309c <strncmp+0xb0>
+ 80430bc:	20800003 	ldbu	r2,0(r4)
+ 80430c0:	28c00003 	ldbu	r3,0(r5)
+ 80430c4:	10c5c83a 	sub	r2,r2,r3
+ 80430c8:	f800283a 	ret
+ 80430cc:	0005883a 	mov	r2,zero
+ 80430d0:	f800283a 	ret
+ 80430d4:	28c00007 	ldb	r3,0(r5)
+ 80430d8:	20800007 	ldb	r2,0(r4)
+ 80430dc:	31bfffc4 	addi	r6,r6,-1
+ 80430e0:	18bfea26 	beq	r3,r2,804308c <strncmp+0xa0>
+ 80430e4:	003ff506 	br	80430bc <strncmp+0xd0>
+
+080430e8 <_strtol_l.isra.0>:
+ 80430e8:	defff504 	addi	sp,sp,-44
+ 80430ec:	dd400615 	stw	r21,24(sp)
+ 80430f0:	dd000515 	stw	r20,20(sp)
+ 80430f4:	dcc00415 	stw	r19,16(sp)
+ 80430f8:	d9000015 	stw	r4,0(sp)
+ 80430fc:	dfc00a15 	stw	ra,40(sp)
+ 8043100:	df000915 	stw	fp,36(sp)
+ 8043104:	ddc00815 	stw	r23,32(sp)
+ 8043108:	dd800715 	stw	r22,28(sp)
+ 804310c:	dc800315 	stw	r18,12(sp)
+ 8043110:	dc400215 	stw	r17,8(sp)
+ 8043114:	dc000115 	stw	r16,4(sp)
+ 8043118:	2827883a 	mov	r19,r5
+ 804311c:	3029883a 	mov	r20,r6
+ 8043120:	382b883a 	mov	r21,r7
+ 8043124:	2809883a 	mov	r4,r5
+ 8043128:	00000106 	br	8043130 <_strtol_l.isra.0+0x48>
+ 804312c:	8009883a 	mov	r4,r16
+ 8043130:	24000044 	addi	r16,r4,1
+ 8043134:	80ffffc3 	ldbu	r3,-1(r16)
+ 8043138:	00820134 	movhi	r2,2052
+ 804313c:	1885883a 	add	r2,r3,r2
+ 8043140:	109c75c3 	ldbu	r2,29143(r2)
+ 8043144:	1080020c 	andi	r2,r2,8
+ 8043148:	103ff81e 	bne	r2,zero,804312c <_strtol_l.isra.0+0x44>
+ 804314c:	18800b58 	cmpnei	r2,r3,45
+ 8043150:	10005226 	beq	r2,zero,804329c <_strtol_l.isra.0+0x1b4>
+ 8043154:	18800ae0 	cmpeqi	r2,r3,43
+ 8043158:	1000251e 	bne	r2,zero,80431f0 <_strtol_l.isra.0+0x108>
+ 804315c:	1823883a 	mov	r17,r3
+ 8043160:	0039883a 	mov	fp,zero
+ 8043164:	a8002626 	beq	r21,zero,8043200 <_strtol_l.isra.0+0x118>
+ 8043168:	a8800420 	cmpeqi	r2,r21,16
+ 804316c:	10004f1e 	bne	r2,zero,80432ac <_strtol_l.isra.0+0x1c4>
+ 8043170:	a82d883a 	mov	r22,r21
+ 8043174:	05e00034 	movhi	r23,32768
+ 8043178:	e000011e 	bne	fp,zero,8043180 <_strtol_l.isra.0+0x98>
+ 804317c:	bdffffc4 	addi	r23,r23,-1
+ 8043180:	b00b883a 	mov	r5,r22
+ 8043184:	b809883a 	mov	r4,r23
+ 8043188:	800d05c0 	call	800d05c <__umodsi3>
+ 804318c:	b00b883a 	mov	r5,r22
+ 8043190:	b809883a 	mov	r4,r23
+ 8043194:	1025883a 	mov	r18,r2
+ 8043198:	800cff80 	call	800cff8 <__udivsi3>
+ 804319c:	100f883a 	mov	r7,r2
+ 80431a0:	000b883a 	mov	r5,zero
+ 80431a4:	0005883a 	mov	r2,zero
+ 80431a8:	88fff404 	addi	r3,r17,-48
+ 80431ac:	190002a8 	cmpgeui	r4,r3,10
+ 80431b0:	20000426 	beq	r4,zero,80431c4 <_strtol_l.isra.0+0xdc>
+ 80431b4:	88ffefc4 	addi	r3,r17,-65
+ 80431b8:	18c006a8 	cmpgeui	r3,r3,26
+ 80431bc:	1800181e 	bne	r3,zero,8043220 <_strtol_l.isra.0+0x138>
+ 80431c0:	88fff244 	addi	r3,r17,-55
+ 80431c4:	1d401b0e 	bge	r3,r21,8043234 <_strtol_l.isra.0+0x14c>
+ 80431c8:	293fffe0 	cmpeqi	r4,r5,-1
+ 80431cc:	2000051e 	bne	r4,zero,80431e4 <_strtol_l.isra.0+0xfc>
+ 80431d0:	38801136 	bltu	r7,r2,8043218 <_strtol_l.isra.0+0x130>
+ 80431d4:	38800f26 	beq	r7,r2,8043214 <_strtol_l.isra.0+0x12c>
+ 80431d8:	b089383a 	mul	r4,r22,r2
+ 80431dc:	01400044 	movi	r5,1
+ 80431e0:	1905883a 	add	r2,r3,r4
+ 80431e4:	84000044 	addi	r16,r16,1
+ 80431e8:	847fffc3 	ldbu	r17,-1(r16)
+ 80431ec:	003fee06 	br	80431a8 <_strtol_l.isra.0+0xc0>
+ 80431f0:	84400003 	ldbu	r17,0(r16)
+ 80431f4:	0039883a 	mov	fp,zero
+ 80431f8:	24000084 	addi	r16,r4,2
+ 80431fc:	a83fda1e 	bne	r21,zero,8043168 <_strtol_l.isra.0+0x80>
+ 8043200:	88800c20 	cmpeqi	r2,r17,48
+ 8043204:	1000361e 	bne	r2,zero,80432e0 <_strtol_l.isra.0+0x1f8>
+ 8043208:	05800284 	movi	r22,10
+ 804320c:	05400284 	movi	r21,10
+ 8043210:	003fd806 	br	8043174 <_strtol_l.isra.0+0x8c>
+ 8043214:	90fff00e 	bge	r18,r3,80431d8 <_strtol_l.isra.0+0xf0>
+ 8043218:	017fffc4 	movi	r5,-1
+ 804321c:	003ff106 	br	80431e4 <_strtol_l.isra.0+0xfc>
+ 8043220:	88ffe7c4 	addi	r3,r17,-97
+ 8043224:	18c006a8 	cmpgeui	r3,r3,26
+ 8043228:	1800021e 	bne	r3,zero,8043234 <_strtol_l.isra.0+0x14c>
+ 804322c:	88ffea44 	addi	r3,r17,-87
+ 8043230:	1d7fe516 	blt	r3,r21,80431c8 <_strtol_l.isra.0+0xe0>
+ 8043234:	28ffffd8 	cmpnei	r3,r5,-1
+ 8043238:	18001126 	beq	r3,zero,8043280 <_strtol_l.isra.0+0x198>
+ 804323c:	e0000126 	beq	fp,zero,8043244 <_strtol_l.isra.0+0x15c>
+ 8043240:	0085c83a 	sub	r2,zero,r2
+ 8043244:	a0000226 	beq	r20,zero,8043250 <_strtol_l.isra.0+0x168>
+ 8043248:	28002e1e 	bne	r5,zero,8043304 <_strtol_l.isra.0+0x21c>
+ 804324c:	a4c00015 	stw	r19,0(r20)
+ 8043250:	dfc00a17 	ldw	ra,40(sp)
+ 8043254:	df000917 	ldw	fp,36(sp)
+ 8043258:	ddc00817 	ldw	r23,32(sp)
+ 804325c:	dd800717 	ldw	r22,28(sp)
+ 8043260:	dd400617 	ldw	r21,24(sp)
+ 8043264:	dd000517 	ldw	r20,20(sp)
+ 8043268:	dcc00417 	ldw	r19,16(sp)
+ 804326c:	dc800317 	ldw	r18,12(sp)
+ 8043270:	dc400217 	ldw	r17,8(sp)
+ 8043274:	dc000117 	ldw	r16,4(sp)
+ 8043278:	dec00b04 	addi	sp,sp,44
+ 804327c:	f800283a 	ret
+ 8043280:	d8c00017 	ldw	r3,0(sp)
+ 8043284:	00800884 	movi	r2,34
+ 8043288:	18800015 	stw	r2,0(r3)
+ 804328c:	a0001b26 	beq	r20,zero,80432fc <_strtol_l.isra.0+0x214>
+ 8043290:	84ffffc4 	addi	r19,r16,-1
+ 8043294:	b805883a 	mov	r2,r23
+ 8043298:	003fec06 	br	804324c <_strtol_l.isra.0+0x164>
+ 804329c:	84400003 	ldbu	r17,0(r16)
+ 80432a0:	07000044 	movi	fp,1
+ 80432a4:	24000084 	addi	r16,r4,2
+ 80432a8:	003fae06 	br	8043164 <_strtol_l.isra.0+0x7c>
+ 80432ac:	88800c18 	cmpnei	r2,r17,48
+ 80432b0:	1000041e 	bne	r2,zero,80432c4 <_strtol_l.isra.0+0x1dc>
+ 80432b4:	80800003 	ldbu	r2,0(r16)
+ 80432b8:	108037cc 	andi	r2,r2,223
+ 80432bc:	10801620 	cmpeqi	r2,r2,88
+ 80432c0:	1000021e 	bne	r2,zero,80432cc <_strtol_l.isra.0+0x1e4>
+ 80432c4:	05800404 	movi	r22,16
+ 80432c8:	003faa06 	br	8043174 <_strtol_l.isra.0+0x8c>
+ 80432cc:	84400043 	ldbu	r17,1(r16)
+ 80432d0:	05800404 	movi	r22,16
+ 80432d4:	84000084 	addi	r16,r16,2
+ 80432d8:	05400404 	movi	r21,16
+ 80432dc:	003fa506 	br	8043174 <_strtol_l.isra.0+0x8c>
+ 80432e0:	80800003 	ldbu	r2,0(r16)
+ 80432e4:	108037cc 	andi	r2,r2,223
+ 80432e8:	10801620 	cmpeqi	r2,r2,88
+ 80432ec:	103ff71e 	bne	r2,zero,80432cc <_strtol_l.isra.0+0x1e4>
+ 80432f0:	05800204 	movi	r22,8
+ 80432f4:	05400204 	movi	r21,8
+ 80432f8:	003f9e06 	br	8043174 <_strtol_l.isra.0+0x8c>
+ 80432fc:	b805883a 	mov	r2,r23
+ 8043300:	003fd306 	br	8043250 <_strtol_l.isra.0+0x168>
+ 8043304:	102f883a 	mov	r23,r2
+ 8043308:	003fe106 	br	8043290 <_strtol_l.isra.0+0x1a8>
+
+0804330c <_strtol_r>:
+ 804330c:	80430e81 	jmpi	80430e8 <_strtol_l.isra.0>
+
+08043310 <strtol_l>:
+ 8043310:	00820174 	movhi	r2,2053
+ 8043314:	300f883a 	mov	r7,r6
+ 8043318:	280d883a 	mov	r6,r5
+ 804331c:	200b883a 	mov	r5,r4
+ 8043320:	1132af17 	ldw	r4,-13636(r2)
+ 8043324:	80430e81 	jmpi	80430e8 <_strtol_l.isra.0>
+
+08043328 <strtol>:
+ 8043328:	00820174 	movhi	r2,2053
+ 804332c:	300f883a 	mov	r7,r6
+ 8043330:	280d883a 	mov	r6,r5
+ 8043334:	200b883a 	mov	r5,r4
+ 8043338:	1132af17 	ldw	r4,-13636(r2)
+ 804333c:	80430e81 	jmpi	80430e8 <_strtol_l.isra.0>
+
+08043340 <___svfprintf_internal_r>:
+ 8043340:	deffbd04 	addi	sp,sp,-268
+ 8043344:	dfc04215 	stw	ra,264(sp)
+ 8043348:	dd403e15 	stw	r21,248(sp)
+ 804334c:	dcc03c15 	stw	r19,240(sp)
+ 8043350:	d9000515 	stw	r4,20(sp)
+ 8043354:	2827883a 	mov	r19,r5
+ 8043358:	302b883a 	mov	r21,r6
+ 804335c:	d9c00615 	stw	r7,24(sp)
+ 8043360:	df004115 	stw	fp,260(sp)
+ 8043364:	ddc04015 	stw	r23,256(sp)
+ 8043368:	dd803f15 	stw	r22,252(sp)
+ 804336c:	dd003d15 	stw	r20,244(sp)
+ 8043370:	dc803b15 	stw	r18,236(sp)
+ 8043374:	dc403a15 	stw	r17,232(sp)
+ 8043378:	dc003915 	stw	r16,228(sp)
+ 804337c:	8007bf00 	call	8007bf0 <_localeconv_r>
+ 8043380:	10800017 	ldw	r2,0(r2)
+ 8043384:	1009883a 	mov	r4,r2
+ 8043388:	d8800d15 	stw	r2,52(sp)
+ 804338c:	8002dac0 	call	8002dac <strlen>
+ 8043390:	d8800b15 	stw	r2,44(sp)
+ 8043394:	9880030b 	ldhu	r2,12(r19)
+ 8043398:	1080200c 	andi	r2,r2,128
+ 804339c:	10000226 	beq	r2,zero,80433a8 <___svfprintf_internal_r+0x68>
+ 80433a0:	98800417 	ldw	r2,16(r19)
+ 80433a4:	10059a26 	beq	r2,zero,8044a10 <___svfprintf_internal_r+0x16d0>
+ 80433a8:	ddc02904 	addi	r23,sp,164
+ 80433ac:	ddc01c15 	stw	r23,112(sp)
+ 80433b0:	d8001e15 	stw	zero,120(sp)
+ 80433b4:	d8001d15 	stw	zero,116(sp)
+ 80433b8:	d8000815 	stw	zero,32(sp)
+ 80433bc:	d8000915 	stw	zero,36(sp)
+ 80433c0:	d8000a15 	stw	zero,40(sp)
+ 80433c4:	b811883a 	mov	r8,r23
+ 80433c8:	d8000c15 	stw	zero,48(sp)
+ 80433cc:	d8001115 	stw	zero,68(sp)
+ 80433d0:	d8000415 	stw	zero,16(sp)
+ 80433d4:	a82d883a 	mov	r22,r21
+ 80433d8:	b0800007 	ldb	r2,0(r22)
+ 80433dc:	10009126 	beq	r2,zero,8043624 <___svfprintf_internal_r+0x2e4>
+ 80433e0:	10800960 	cmpeqi	r2,r2,37
+ 80433e4:	1004f61e 	bne	r2,zero,80447c0 <___svfprintf_internal_r+0x1480>
+ 80433e8:	b021883a 	mov	r16,r22
+ 80433ec:	00000206 	br	80433f8 <___svfprintf_internal_r+0xb8>
+ 80433f0:	18008226 	beq	r3,zero,80435fc <___svfprintf_internal_r+0x2bc>
+ 80433f4:	9021883a 	mov	r16,r18
+ 80433f8:	80800047 	ldb	r2,1(r16)
+ 80433fc:	84800044 	addi	r18,r16,1
+ 8043400:	10c00958 	cmpnei	r3,r2,37
+ 8043404:	103ffa1e 	bne	r2,zero,80433f0 <___svfprintf_internal_r+0xb0>
+ 8043408:	95a3c83a 	sub	r17,r18,r22
+ 804340c:	88008526 	beq	r17,zero,8043624 <___svfprintf_internal_r+0x2e4>
+ 8043410:	d8c01e17 	ldw	r3,120(sp)
+ 8043414:	d8801d17 	ldw	r2,116(sp)
+ 8043418:	45800015 	stw	r22,0(r8)
+ 804341c:	1c47883a 	add	r3,r3,r17
+ 8043420:	10800044 	addi	r2,r2,1
+ 8043424:	d8801d15 	stw	r2,116(sp)
+ 8043428:	44400115 	stw	r17,4(r8)
+ 804342c:	d8c01e15 	stw	r3,120(sp)
+ 8043430:	10800208 	cmpgei	r2,r2,8
+ 8043434:	1000741e 	bne	r2,zero,8043608 <___svfprintf_internal_r+0x2c8>
+ 8043438:	42000204 	addi	r8,r8,8
+ 804343c:	d8c00417 	ldw	r3,16(sp)
+ 8043440:	80800047 	ldb	r2,1(r16)
+ 8043444:	1c47883a 	add	r3,r3,r17
+ 8043448:	d8c00415 	stw	r3,16(sp)
+ 804344c:	10007526 	beq	r2,zero,8043624 <___svfprintf_internal_r+0x2e4>
+ 8043450:	92800047 	ldb	r10,1(r18)
+ 8043454:	95800044 	addi	r22,r18,1
+ 8043458:	d8001545 	stb	zero,85(sp)
+ 804345c:	0009883a 	mov	r4,zero
+ 8043460:	000b883a 	mov	r5,zero
+ 8043464:	02ffffc4 	movi	r11,-1
+ 8043468:	0023883a 	mov	r17,zero
+ 804346c:	0019883a 	mov	r12,zero
+ 8043470:	b5800044 	addi	r22,r22,1
+ 8043474:	5039883a 	mov	fp,r10
+ 8043478:	e0bff804 	addi	r2,fp,-32
+ 804347c:	10c01668 	cmpgeui	r3,r2,89
+ 8043480:	18008a1e 	bne	r3,zero,80436ac <___svfprintf_internal_r+0x36c>
+ 8043484:	100490ba 	slli	r2,r2,2
+ 8043488:	00c20134 	movhi	r3,2052
+ 804348c:	10c7883a 	add	r3,r2,r3
+ 8043490:	188d2617 	ldw	r2,13464(r3)
+ 8043494:	1000683a 	jmp	r2
+ 8043498:	0804377c 	xorhi	zero,at,4317
+ 804349c:	080436ac 	andhi	zero,at,4314
+ 80434a0:	080436ac 	andhi	zero,at,4314
+ 80434a4:	08043770 	cmpltui	zero,at,4317
+ 80434a8:	080436ac 	andhi	zero,at,4314
+ 80434ac:	080436ac 	andhi	zero,at,4314
+ 80434b0:	080436ac 	andhi	zero,at,4314
+ 80434b4:	080436ac 	andhi	zero,at,4314
+ 80434b8:	080436ac 	andhi	zero,at,4314
+ 80434bc:	080436ac 	andhi	zero,at,4314
+ 80434c0:	08043748 	cmpgei	zero,at,4317
+ 80434c4:	08043738 	rdprs	zero,at,4316
+ 80434c8:	080436ac 	andhi	zero,at,4314
+ 80434cc:	08043720 	cmpeqi	zero,at,4316
+ 80434d0:	080436dc 	xori	zero,at,4315
+ 80434d4:	080436ac 	andhi	zero,at,4314
+ 80434d8:	080436d0 	cmplti	zero,at,4315
+ 80434dc:	0804367c 	xorhi	zero,at,4313
+ 80434e0:	0804367c 	xorhi	zero,at,4313
+ 80434e4:	0804367c 	xorhi	zero,at,4313
+ 80434e8:	0804367c 	xorhi	zero,at,4313
+ 80434ec:	0804367c 	xorhi	zero,at,4313
+ 80434f0:	0804367c 	xorhi	zero,at,4313
+ 80434f4:	0804367c 	xorhi	zero,at,4313
+ 80434f8:	0804367c 	xorhi	zero,at,4313
+ 80434fc:	0804367c 	xorhi	zero,at,4313
+ 8043500:	080436ac 	andhi	zero,at,4314
+ 8043504:	080436ac 	andhi	zero,at,4314
+ 8043508:	080436ac 	andhi	zero,at,4314
+ 804350c:	080436ac 	andhi	zero,at,4314
+ 8043510:	080436ac 	andhi	zero,at,4314
+ 8043514:	080436ac 	andhi	zero,at,4314
+ 8043518:	080436ac 	andhi	zero,at,4314
+ 804351c:	080436ac 	andhi	zero,at,4314
+ 8043520:	080436ac 	andhi	zero,at,4314
+ 8043524:	080436ac 	andhi	zero,at,4314
+ 8043528:	08043d30 	cmpltui	zero,at,4340
+ 804352c:	08043c50 	cmplti	zero,at,4337
+ 8043530:	080436ac 	andhi	zero,at,4314
+ 8043534:	08043c50 	cmplti	zero,at,4337
+ 8043538:	080436ac 	andhi	zero,at,4314
+ 804353c:	080436ac 	andhi	zero,at,4314
+ 8043540:	080436ac 	andhi	zero,at,4314
+ 8043544:	080436ac 	andhi	zero,at,4314
+ 8043548:	08043e84 	addi	zero,at,4346
+ 804354c:	080436ac 	andhi	zero,at,4314
+ 8043550:	080436ac 	andhi	zero,at,4314
+ 8043554:	08043c1c 	xori	zero,at,4336
+ 8043558:	080436ac 	andhi	zero,at,4314
+ 804355c:	080436ac 	andhi	zero,at,4314
+ 8043560:	080436ac 	andhi	zero,at,4314
+ 8043564:	080436ac 	andhi	zero,at,4314
+ 8043568:	080436ac 	andhi	zero,at,4314
+ 804356c:	08043e50 	cmplti	zero,at,4345
+ 8043570:	080436ac 	andhi	zero,at,4314
+ 8043574:	080436ac 	andhi	zero,at,4314
+ 8043578:	08043e08 	cmpgei	zero,at,4344
+ 804357c:	080436ac 	andhi	zero,at,4314
+ 8043580:	080436ac 	andhi	zero,at,4314
+ 8043584:	080436ac 	andhi	zero,at,4314
+ 8043588:	080436ac 	andhi	zero,at,4314
+ 804358c:	080436ac 	andhi	zero,at,4314
+ 8043590:	080436ac 	andhi	zero,at,4314
+ 8043594:	080436ac 	andhi	zero,at,4314
+ 8043598:	080436ac 	andhi	zero,at,4314
+ 804359c:	080436ac 	andhi	zero,at,4314
+ 80435a0:	080436ac 	andhi	zero,at,4314
+ 80435a4:	08043904 	addi	zero,at,4324
+ 80435a8:	08043890 	cmplti	zero,at,4322
+ 80435ac:	08043c50 	cmplti	zero,at,4337
+ 80435b0:	08043c50 	cmplti	zero,at,4337
+ 80435b4:	08043c50 	cmplti	zero,at,4337
+ 80435b8:	08043b88 	cmpgei	zero,at,4334
+ 80435bc:	08043890 	cmplti	zero,at,4322
+ 80435c0:	080436ac 	andhi	zero,at,4314
+ 80435c4:	080436ac 	andhi	zero,at,4314
+ 80435c8:	08043b74 	orhi	zero,at,4333
+ 80435cc:	080436ac 	andhi	zero,at,4314
+ 80435d0:	08043b34 	orhi	zero,at,4332
+ 80435d4:	08043af4 	orhi	zero,at,4331
+ 80435d8:	08043ba0 	cmpeqi	zero,at,4334
+ 80435dc:	08043b94 	ori	zero,at,4334
+ 80435e0:	080436ac 	andhi	zero,at,4314
+ 80435e4:	08043830 	cmpltui	zero,at,4320
+ 80435e8:	080436ac 	andhi	zero,at,4314
+ 80435ec:	080437f0 	cmpltui	zero,at,4319
+ 80435f0:	080436ac 	andhi	zero,at,4314
+ 80435f4:	080436ac 	andhi	zero,at,4314
+ 80435f8:	080437a8 	cmpgeui	zero,at,4318
+ 80435fc:	95a3c83a 	sub	r17,r18,r22
+ 8043600:	883f9326 	beq	r17,zero,8043450 <___svfprintf_internal_r+0x110>
+ 8043604:	003f8206 	br	8043410 <___svfprintf_internal_r+0xd0>
+ 8043608:	d9000517 	ldw	r4,20(sp)
+ 804360c:	d9801c04 	addi	r6,sp,112
+ 8043610:	980b883a 	mov	r5,r19
+ 8043614:	80456900 	call	8045690 <__ssprint_r>
+ 8043618:	1000081e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 804361c:	b811883a 	mov	r8,r23
+ 8043620:	003f8606 	br	804343c <___svfprintf_internal_r+0xfc>
+ 8043624:	d8801e17 	ldw	r2,120(sp)
+ 8043628:	10000426 	beq	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 804362c:	d9000517 	ldw	r4,20(sp)
+ 8043630:	d9801c04 	addi	r6,sp,112
+ 8043634:	980b883a 	mov	r5,r19
+ 8043638:	80456900 	call	8045690 <__ssprint_r>
+ 804363c:	9880030b 	ldhu	r2,12(r19)
+ 8043640:	1080100c 	andi	r2,r2,64
+ 8043644:	10072d1e 	bne	r2,zero,80452fc <___svfprintf_internal_r+0x1fbc>
+ 8043648:	d8800417 	ldw	r2,16(sp)
+ 804364c:	dfc04217 	ldw	ra,264(sp)
+ 8043650:	df004117 	ldw	fp,260(sp)
+ 8043654:	ddc04017 	ldw	r23,256(sp)
+ 8043658:	dd803f17 	ldw	r22,252(sp)
+ 804365c:	dd403e17 	ldw	r21,248(sp)
+ 8043660:	dd003d17 	ldw	r20,244(sp)
+ 8043664:	dcc03c17 	ldw	r19,240(sp)
+ 8043668:	dc803b17 	ldw	r18,236(sp)
+ 804366c:	dc403a17 	ldw	r17,232(sp)
+ 8043670:	dc003917 	ldw	r16,228(sp)
+ 8043674:	dec04304 	addi	sp,sp,268
+ 8043678:	f800283a 	ret
+ 804367c:	0023883a 	mov	r17,zero
+ 8043680:	e0bff404 	addi	r2,fp,-48
+ 8043684:	b5800044 	addi	r22,r22,1
+ 8043688:	8c4002a4 	muli	r17,r17,10
+ 804368c:	b73fffc7 	ldb	fp,-1(r22)
+ 8043690:	1463883a 	add	r17,r2,r17
+ 8043694:	e0bff404 	addi	r2,fp,-48
+ 8043698:	10c002b0 	cmpltui	r3,r2,10
+ 804369c:	183ff91e 	bne	r3,zero,8043684 <___svfprintf_internal_r+0x344>
+ 80436a0:	e0bff804 	addi	r2,fp,-32
+ 80436a4:	10c01668 	cmpgeui	r3,r2,89
+ 80436a8:	183f7626 	beq	r3,zero,8043484 <___svfprintf_internal_r+0x144>
+ 80436ac:	21003fcc 	andi	r4,r4,255
+ 80436b0:	20068c1e 	bne	r4,zero,80450e4 <___svfprintf_internal_r+0x1da4>
+ 80436b4:	e03fdb26 	beq	fp,zero,8043624 <___svfprintf_internal_r+0x2e4>
+ 80436b8:	df001f05 	stb	fp,124(sp)
+ 80436bc:	d8001545 	stb	zero,85(sp)
+ 80436c0:	05000044 	movi	r20,1
+ 80436c4:	05400044 	movi	r21,1
+ 80436c8:	dc001f04 	addi	r16,sp,124
+ 80436cc:	00009606 	br	8043928 <___svfprintf_internal_r+0x5e8>
+ 80436d0:	63002014 	ori	r12,r12,128
+ 80436d4:	b2800007 	ldb	r10,0(r22)
+ 80436d8:	003f6506 	br	8043470 <___svfprintf_internal_r+0x130>
+ 80436dc:	b7000007 	ldb	fp,0(r22)
+ 80436e0:	b0c00044 	addi	r3,r22,1
+ 80436e4:	e0800aa0 	cmpeqi	r2,fp,42
+ 80436e8:	1007491e 	bne	r2,zero,8045410 <___svfprintf_internal_r+0x20d0>
+ 80436ec:	e0bff404 	addi	r2,fp,-48
+ 80436f0:	118002b0 	cmpltui	r6,r2,10
+ 80436f4:	182d883a 	mov	r22,r3
+ 80436f8:	0017883a 	mov	r11,zero
+ 80436fc:	303f5e26 	beq	r6,zero,8043478 <___svfprintf_internal_r+0x138>
+ 8043700:	b5800044 	addi	r22,r22,1
+ 8043704:	5ac002a4 	muli	r11,r11,10
+ 8043708:	b73fffc7 	ldb	fp,-1(r22)
+ 804370c:	5897883a 	add	r11,r11,r2
+ 8043710:	e0bff404 	addi	r2,fp,-48
+ 8043714:	10c002b0 	cmpltui	r3,r2,10
+ 8043718:	183ff91e 	bne	r3,zero,8043700 <___svfprintf_internal_r+0x3c0>
+ 804371c:	003f5606 	br	8043478 <___svfprintf_internal_r+0x138>
+ 8043720:	b7000003 	ldbu	fp,0(r22)
+ 8043724:	e2803fcc 	andi	r10,fp,255
+ 8043728:	5280201c 	xori	r10,r10,128
+ 804372c:	63000114 	ori	r12,r12,4
+ 8043730:	52bfe004 	addi	r10,r10,-128
+ 8043734:	003f4e06 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043738:	01000044 	movi	r4,1
+ 804373c:	01400ac4 	movi	r5,43
+ 8043740:	b2800007 	ldb	r10,0(r22)
+ 8043744:	003f4a06 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043748:	d8800617 	ldw	r2,24(sp)
+ 804374c:	b7000003 	ldbu	fp,0(r22)
+ 8043750:	14400017 	ldw	r17,0(r2)
+ 8043754:	10800104 	addi	r2,r2,4
+ 8043758:	88049016 	blt	r17,zero,804499c <___svfprintf_internal_r+0x165c>
+ 804375c:	d8800615 	stw	r2,24(sp)
+ 8043760:	e2803fcc 	andi	r10,fp,255
+ 8043764:	5280201c 	xori	r10,r10,128
+ 8043768:	52bfe004 	addi	r10,r10,-128
+ 804376c:	003f4006 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043770:	63000054 	ori	r12,r12,1
+ 8043774:	b2800007 	ldb	r10,0(r22)
+ 8043778:	003f3d06 	br	8043470 <___svfprintf_internal_r+0x130>
+ 804377c:	28803fcc 	andi	r2,r5,255
+ 8043780:	1080201c 	xori	r2,r2,128
+ 8043784:	10bfe004 	addi	r2,r2,-128
+ 8043788:	b7000003 	ldbu	fp,0(r22)
+ 804378c:	103ff41e 	bne	r2,zero,8043760 <___svfprintf_internal_r+0x420>
+ 8043790:	e2803fcc 	andi	r10,fp,255
+ 8043794:	5280201c 	xori	r10,r10,128
+ 8043798:	01000044 	movi	r4,1
+ 804379c:	01400804 	movi	r5,32
+ 80437a0:	52bfe004 	addi	r10,r10,-128
+ 80437a4:	003f3206 	br	8043470 <___svfprintf_internal_r+0x130>
+ 80437a8:	21003fcc 	andi	r4,r4,255
+ 80437ac:	2006b01e 	bne	r4,zero,8045270 <___svfprintf_internal_r+0x1f30>
+ 80437b0:	00820134 	movhi	r2,2052
+ 80437b4:	109d2004 	addi	r2,r2,29824
+ 80437b8:	d8800c15 	stw	r2,48(sp)
+ 80437bc:	6080080c 	andi	r2,r12,32
+ 80437c0:	10019826 	beq	r2,zero,8043e24 <___svfprintf_internal_r+0xae4>
+ 80437c4:	d8800617 	ldw	r2,24(sp)
+ 80437c8:	15000017 	ldw	r20,0(r2)
+ 80437cc:	15400117 	ldw	r21,4(r2)
+ 80437d0:	10800204 	addi	r2,r2,8
+ 80437d4:	d8800615 	stw	r2,24(sp)
+ 80437d8:	6080004c 	andi	r2,r12,1
+ 80437dc:	10000226 	beq	r2,zero,80437e8 <___svfprintf_internal_r+0x4a8>
+ 80437e0:	a544b03a 	or	r2,r20,r21
+ 80437e4:	1004671e 	bne	r2,zero,8044984 <___svfprintf_internal_r+0x1644>
+ 80437e8:	00800084 	movi	r2,2
+ 80437ec:	0000fb06 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 80437f0:	21003fcc 	andi	r4,r4,255
+ 80437f4:	20069a1e 	bne	r4,zero,8045260 <___svfprintf_internal_r+0x1f20>
+ 80437f8:	6080080c 	andi	r2,r12,32
+ 80437fc:	1001a41e 	bne	r2,zero,8043e90 <___svfprintf_internal_r+0xb50>
+ 8043800:	d8800617 	ldw	r2,24(sp)
+ 8043804:	60c0040c 	andi	r3,r12,16
+ 8043808:	15000017 	ldw	r20,0(r2)
+ 804380c:	10800104 	addi	r2,r2,4
+ 8043810:	1801961e 	bne	r3,zero,8043e6c <___svfprintf_internal_r+0xb2c>
+ 8043814:	60c0100c 	andi	r3,r12,64
+ 8043818:	1805ab26 	beq	r3,zero,8044ec8 <___svfprintf_internal_r+0x1b88>
+ 804381c:	d8800615 	stw	r2,24(sp)
+ 8043820:	a53fffcc 	andi	r20,r20,65535
+ 8043824:	002b883a 	mov	r21,zero
+ 8043828:	00800044 	movi	r2,1
+ 804382c:	0000eb06 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043830:	d8800617 	ldw	r2,24(sp)
+ 8043834:	d8001545 	stb	zero,85(sp)
+ 8043838:	14000017 	ldw	r16,0(r2)
+ 804383c:	14800104 	addi	r18,r2,4
+ 8043840:	80051226 	beq	r16,zero,8044c8c <___svfprintf_internal_r+0x194c>
+ 8043844:	da000e15 	stw	r8,56(sp)
+ 8043848:	db000715 	stw	r12,28(sp)
+ 804384c:	58bfffe0 	cmpeqi	r2,r11,-1
+ 8043850:	1004671e 	bne	r2,zero,80449f0 <___svfprintf_internal_r+0x16b0>
+ 8043854:	580d883a 	mov	r6,r11
+ 8043858:	000b883a 	mov	r5,zero
+ 804385c:	8009883a 	mov	r4,r16
+ 8043860:	dac00615 	stw	r11,24(sp)
+ 8043864:	80085d00 	call	80085d0 <memchr>
+ 8043868:	dac00617 	ldw	r11,24(sp)
+ 804386c:	db000717 	ldw	r12,28(sp)
+ 8043870:	da000e17 	ldw	r8,56(sp)
+ 8043874:	10066826 	beq	r2,zero,8045218 <___svfprintf_internal_r+0x1ed8>
+ 8043878:	142bc83a 	sub	r21,r2,r16
+ 804387c:	a829883a 	mov	r20,r21
+ 8043880:	a800010e 	bge	r21,zero,8043888 <___svfprintf_internal_r+0x548>
+ 8043884:	0029883a 	mov	r20,zero
+ 8043888:	dc800615 	stw	r18,24(sp)
+ 804388c:	00002606 	br	8043928 <___svfprintf_internal_r+0x5e8>
+ 8043890:	21003fcc 	andi	r4,r4,255
+ 8043894:	20067c1e 	bne	r4,zero,8045288 <___svfprintf_internal_r+0x1f48>
+ 8043898:	6080080c 	andi	r2,r12,32
+ 804389c:	1001831e 	bne	r2,zero,8043eac <___svfprintf_internal_r+0xb6c>
+ 80438a0:	d8800617 	ldw	r2,24(sp)
+ 80438a4:	60c0040c 	andi	r3,r12,16
+ 80438a8:	10800104 	addi	r2,r2,4
+ 80438ac:	1801271e 	bne	r3,zero,8043d4c <___svfprintf_internal_r+0xa0c>
+ 80438b0:	60c0100c 	andi	r3,r12,64
+ 80438b4:	18012526 	beq	r3,zero,8043d4c <___svfprintf_internal_r+0xa0c>
+ 80438b8:	d8c00617 	ldw	r3,24(sp)
+ 80438bc:	d8800615 	stw	r2,24(sp)
+ 80438c0:	1d00000f 	ldh	r20,0(r3)
+ 80438c4:	a02bd7fa 	srai	r21,r20,31
+ 80438c8:	a805883a 	mov	r2,r21
+ 80438cc:	10012516 	blt	r2,zero,8043d64 <___svfprintf_internal_r+0xa24>
+ 80438d0:	58bfffd8 	cmpnei	r2,r11,-1
+ 80438d4:	db401543 	ldbu	r13,85(sp)
+ 80438d8:	10018226 	beq	r2,zero,8043ee4 <___svfprintf_internal_r+0xba4>
+ 80438dc:	00ffdfc4 	movi	r3,-129
+ 80438e0:	a544b03a 	or	r2,r20,r21
+ 80438e4:	60d8703a 	and	r12,r12,r3
+ 80438e8:	10017e1e 	bne	r2,zero,8043ee4 <___svfprintf_internal_r+0xba4>
+ 80438ec:	5801801e 	bne	r11,zero,8043ef0 <___svfprintf_internal_r+0xbb0>
+ 80438f0:	6025883a 	mov	r18,r12
+ 80438f4:	0017883a 	mov	r11,zero
+ 80438f8:	002b883a 	mov	r21,zero
+ 80438fc:	b821883a 	mov	r16,r23
+ 8043900:	00018006 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 8043904:	d8c00617 	ldw	r3,24(sp)
+ 8043908:	d8001545 	stb	zero,85(sp)
+ 804390c:	05000044 	movi	r20,1
+ 8043910:	18800017 	ldw	r2,0(r3)
+ 8043914:	18c00104 	addi	r3,r3,4
+ 8043918:	d8c00615 	stw	r3,24(sp)
+ 804391c:	d8801f05 	stb	r2,124(sp)
+ 8043920:	05400044 	movi	r21,1
+ 8043924:	dc001f04 	addi	r16,sp,124
+ 8043928:	6025883a 	mov	r18,r12
+ 804392c:	0017883a 	mov	r11,zero
+ 8043930:	d8000715 	stw	zero,28(sp)
+ 8043934:	9380008c 	andi	r14,r18,2
+ 8043938:	70000126 	beq	r14,zero,8043940 <___svfprintf_internal_r+0x600>
+ 804393c:	a5000084 	addi	r20,r20,2
+ 8043940:	9340210c 	andi	r13,r18,132
+ 8043944:	d8c01e17 	ldw	r3,120(sp)
+ 8043948:	6800021e 	bne	r13,zero,8043954 <___svfprintf_internal_r+0x614>
+ 804394c:	8d0fc83a 	sub	r7,r17,r20
+ 8043950:	01c2a616 	blt	zero,r7,80443ec <___svfprintf_internal_r+0x10ac>
+ 8043954:	d8801547 	ldb	r2,85(sp)
+ 8043958:	10000c26 	beq	r2,zero,804398c <___svfprintf_internal_r+0x64c>
+ 804395c:	d8801d17 	ldw	r2,116(sp)
+ 8043960:	d9001544 	addi	r4,sp,85
+ 8043964:	18c00044 	addi	r3,r3,1
+ 8043968:	10800044 	addi	r2,r2,1
+ 804396c:	41000015 	stw	r4,0(r8)
+ 8043970:	01000044 	movi	r4,1
+ 8043974:	d8801d15 	stw	r2,116(sp)
+ 8043978:	41000115 	stw	r4,4(r8)
+ 804397c:	d8c01e15 	stw	r3,120(sp)
+ 8043980:	10800208 	cmpgei	r2,r2,8
+ 8043984:	1002d31e 	bne	r2,zero,80444d4 <___svfprintf_internal_r+0x1194>
+ 8043988:	42000204 	addi	r8,r8,8
+ 804398c:	70000c26 	beq	r14,zero,80439c0 <___svfprintf_internal_r+0x680>
+ 8043990:	d8801d17 	ldw	r2,116(sp)
+ 8043994:	d9001584 	addi	r4,sp,86
+ 8043998:	18c00084 	addi	r3,r3,2
+ 804399c:	10800044 	addi	r2,r2,1
+ 80439a0:	41000015 	stw	r4,0(r8)
+ 80439a4:	01000084 	movi	r4,2
+ 80439a8:	d8801d15 	stw	r2,116(sp)
+ 80439ac:	41000115 	stw	r4,4(r8)
+ 80439b0:	d8c01e15 	stw	r3,120(sp)
+ 80439b4:	10800208 	cmpgei	r2,r2,8
+ 80439b8:	1002d41e 	bne	r2,zero,804450c <___svfprintf_internal_r+0x11cc>
+ 80439bc:	42000204 	addi	r8,r8,8
+ 80439c0:	6b402018 	cmpnei	r13,r13,128
+ 80439c4:	6801ca26 	beq	r13,zero,80440f0 <___svfprintf_internal_r+0xdb0>
+ 80439c8:	5d4fc83a 	sub	r7,r11,r21
+ 80439cc:	01c20116 	blt	zero,r7,80441d4 <___svfprintf_internal_r+0xe94>
+ 80439d0:	9080400c 	andi	r2,r18,256
+ 80439d4:	1001791e 	bne	r2,zero,8043fbc <___svfprintf_internal_r+0xc7c>
+ 80439d8:	d8801d17 	ldw	r2,116(sp)
+ 80439dc:	1d47883a 	add	r3,r3,r21
+ 80439e0:	44000015 	stw	r16,0(r8)
+ 80439e4:	10800044 	addi	r2,r2,1
+ 80439e8:	d8801d15 	stw	r2,116(sp)
+ 80439ec:	45400115 	stw	r21,4(r8)
+ 80439f0:	d8c01e15 	stw	r3,120(sp)
+ 80439f4:	10800208 	cmpgei	r2,r2,8
+ 80439f8:	1002721e 	bne	r2,zero,80443c4 <___svfprintf_internal_r+0x1084>
+ 80439fc:	42000204 	addi	r8,r8,8
+ 8043a00:	9480010c 	andi	r18,r18,4
+ 8043a04:	90000226 	beq	r18,zero,8043a10 <___svfprintf_internal_r+0x6d0>
+ 8043a08:	8d21c83a 	sub	r16,r17,r20
+ 8043a0c:	04000916 	blt	zero,r16,8043a34 <___svfprintf_internal_r+0x6f4>
+ 8043a10:	8d00010e 	bge	r17,r20,8043a18 <___svfprintf_internal_r+0x6d8>
+ 8043a14:	a023883a 	mov	r17,r20
+ 8043a18:	d8800417 	ldw	r2,16(sp)
+ 8043a1c:	1445883a 	add	r2,r2,r17
+ 8043a20:	d8800415 	stw	r2,16(sp)
+ 8043a24:	18021f1e 	bne	r3,zero,80442a4 <___svfprintf_internal_r+0xf64>
+ 8043a28:	d8001d15 	stw	zero,116(sp)
+ 8043a2c:	b811883a 	mov	r8,r23
+ 8043a30:	003e6906 	br	80433d8 <___svfprintf_internal_r+0x98>
+ 8043a34:	03020174 	movhi	r12,2053
+ 8043a38:	81000450 	cmplti	r4,r16,17
+ 8043a3c:	632e3844 	addi	r12,r12,-18207
+ 8043a40:	d8801d17 	ldw	r2,116(sp)
+ 8043a44:	20001c1e 	bne	r4,zero,8043ab8 <___svfprintf_internal_r+0x778>
+ 8043a48:	04800404 	movi	r18,16
+ 8043a4c:	dd400517 	ldw	r21,20(sp)
+ 8043a50:	6039883a 	mov	fp,r12
+ 8043a54:	00000406 	br	8043a68 <___svfprintf_internal_r+0x728>
+ 8043a58:	843ffc04 	addi	r16,r16,-16
+ 8043a5c:	81000448 	cmpgei	r4,r16,17
+ 8043a60:	42000204 	addi	r8,r8,8
+ 8043a64:	20001326 	beq	r4,zero,8043ab4 <___svfprintf_internal_r+0x774>
+ 8043a68:	10800044 	addi	r2,r2,1
+ 8043a6c:	18c00404 	addi	r3,r3,16
+ 8043a70:	47000015 	stw	fp,0(r8)
+ 8043a74:	44800115 	stw	r18,4(r8)
+ 8043a78:	d8c01e15 	stw	r3,120(sp)
+ 8043a7c:	d8801d15 	stw	r2,116(sp)
+ 8043a80:	11000208 	cmpgei	r4,r2,8
+ 8043a84:	203ff426 	beq	r4,zero,8043a58 <___svfprintf_internal_r+0x718>
+ 8043a88:	d9801c04 	addi	r6,sp,112
+ 8043a8c:	980b883a 	mov	r5,r19
+ 8043a90:	a809883a 	mov	r4,r21
+ 8043a94:	80456900 	call	8045690 <__ssprint_r>
+ 8043a98:	103ee81e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8043a9c:	843ffc04 	addi	r16,r16,-16
+ 8043aa0:	81000448 	cmpgei	r4,r16,17
+ 8043aa4:	d8c01e17 	ldw	r3,120(sp)
+ 8043aa8:	d8801d17 	ldw	r2,116(sp)
+ 8043aac:	b811883a 	mov	r8,r23
+ 8043ab0:	203fed1e 	bne	r4,zero,8043a68 <___svfprintf_internal_r+0x728>
+ 8043ab4:	e019883a 	mov	r12,fp
+ 8043ab8:	10800044 	addi	r2,r2,1
+ 8043abc:	1c07883a 	add	r3,r3,r16
+ 8043ac0:	d8801d15 	stw	r2,116(sp)
+ 8043ac4:	43000015 	stw	r12,0(r8)
+ 8043ac8:	44000115 	stw	r16,4(r8)
+ 8043acc:	d8c01e15 	stw	r3,120(sp)
+ 8043ad0:	10800210 	cmplti	r2,r2,8
+ 8043ad4:	103fce1e 	bne	r2,zero,8043a10 <___svfprintf_internal_r+0x6d0>
+ 8043ad8:	d9000517 	ldw	r4,20(sp)
+ 8043adc:	d9801c04 	addi	r6,sp,112
+ 8043ae0:	980b883a 	mov	r5,r19
+ 8043ae4:	80456900 	call	8045690 <__ssprint_r>
+ 8043ae8:	103ed41e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8043aec:	d8c01e17 	ldw	r3,120(sp)
+ 8043af0:	003fc706 	br	8043a10 <___svfprintf_internal_r+0x6d0>
+ 8043af4:	21003fcc 	andi	r4,r4,255
+ 8043af8:	2005e11e 	bne	r4,zero,8045280 <___svfprintf_internal_r+0x1f40>
+ 8043afc:	6080080c 	andi	r2,r12,32
+ 8043b00:	1000f11e 	bne	r2,zero,8043ec8 <___svfprintf_internal_r+0xb88>
+ 8043b04:	d8800617 	ldw	r2,24(sp)
+ 8043b08:	60c0040c 	andi	r3,r12,16
+ 8043b0c:	15000017 	ldw	r20,0(r2)
+ 8043b10:	10800104 	addi	r2,r2,4
+ 8043b14:	1800481e 	bne	r3,zero,8043c38 <___svfprintf_internal_r+0x8f8>
+ 8043b18:	60c0100c 	andi	r3,r12,64
+ 8043b1c:	18053326 	beq	r3,zero,8044fec <___svfprintf_internal_r+0x1cac>
+ 8043b20:	d8800615 	stw	r2,24(sp)
+ 8043b24:	a53fffcc 	andi	r20,r20,65535
+ 8043b28:	002b883a 	mov	r21,zero
+ 8043b2c:	0005883a 	mov	r2,zero
+ 8043b30:	00002a06 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043b34:	21003fcc 	andi	r4,r4,255
+ 8043b38:	2005d71e 	bne	r4,zero,8045298 <___svfprintf_internal_r+0x1f58>
+ 8043b3c:	d9000617 	ldw	r4,24(sp)
+ 8043b40:	6080080c 	andi	r2,r12,32
+ 8043b44:	20c00104 	addi	r3,r4,4
+ 8043b48:	1003871e 	bne	r2,zero,8044968 <___svfprintf_internal_r+0x1628>
+ 8043b4c:	6080040c 	andi	r2,r12,16
+ 8043b50:	1003dc1e 	bne	r2,zero,8044ac4 <___svfprintf_internal_r+0x1784>
+ 8043b54:	6300100c 	andi	r12,r12,64
+ 8043b58:	6003da26 	beq	r12,zero,8044ac4 <___svfprintf_internal_r+0x1784>
+ 8043b5c:	d8800617 	ldw	r2,24(sp)
+ 8043b60:	d8c00615 	stw	r3,24(sp)
+ 8043b64:	d8c00417 	ldw	r3,16(sp)
+ 8043b68:	10800017 	ldw	r2,0(r2)
+ 8043b6c:	10c0000d 	sth	r3,0(r2)
+ 8043b70:	003e1906 	br	80433d8 <___svfprintf_internal_r+0x98>
+ 8043b74:	b2800007 	ldb	r10,0(r22)
+ 8043b78:	50801b18 	cmpnei	r2,r10,108
+ 8043b7c:	10043426 	beq	r2,zero,8044c50 <___svfprintf_internal_r+0x1910>
+ 8043b80:	63000414 	ori	r12,r12,16
+ 8043b84:	003e3a06 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043b88:	63001014 	ori	r12,r12,64
+ 8043b8c:	b2800007 	ldb	r10,0(r22)
+ 8043b90:	003e3706 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043b94:	63000814 	ori	r12,r12,32
+ 8043b98:	b2800007 	ldb	r10,0(r22)
+ 8043b9c:	003e3406 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043ba0:	d8c00617 	ldw	r3,24(sp)
+ 8043ba4:	00800c04 	movi	r2,48
+ 8043ba8:	d8801585 	stb	r2,86(sp)
+ 8043bac:	00801e04 	movi	r2,120
+ 8043bb0:	01020134 	movhi	r4,2052
+ 8043bb4:	d88015c5 	stb	r2,87(sp)
+ 8043bb8:	1d000017 	ldw	r20,0(r3)
+ 8043bbc:	18800104 	addi	r2,r3,4
+ 8043bc0:	d8800615 	stw	r2,24(sp)
+ 8043bc4:	209d2004 	addi	r2,r4,29824
+ 8043bc8:	d8800c15 	stw	r2,48(sp)
+ 8043bcc:	002b883a 	mov	r21,zero
+ 8043bd0:	63000094 	ori	r12,r12,2
+ 8043bd4:	00800084 	movi	r2,2
+ 8043bd8:	07001e04 	movi	fp,120
+ 8043bdc:	d8001545 	stb	zero,85(sp)
+ 8043be0:	58ffffe0 	cmpeqi	r3,r11,-1
+ 8043be4:	001b883a 	mov	r13,zero
+ 8043be8:	1800681e 	bne	r3,zero,8043d8c <___svfprintf_internal_r+0xa4c>
+ 8043bec:	04bfdfc4 	movi	r18,-129
+ 8043bf0:	a546b03a 	or	r3,r20,r21
+ 8043bf4:	64a4703a 	and	r18,r12,r18
+ 8043bf8:	1801fa1e 	bne	r3,zero,80443e4 <___svfprintf_internal_r+0x10a4>
+ 8043bfc:	5804101e 	bne	r11,zero,8044c40 <___svfprintf_internal_r+0x1900>
+ 8043c00:	103f3c1e 	bne	r2,zero,80438f4 <___svfprintf_internal_r+0x5b4>
+ 8043c04:	6540004c 	andi	r21,r12,1
+ 8043c08:	a8030126 	beq	r21,zero,8044810 <___svfprintf_internal_r+0x14d0>
+ 8043c0c:	00800c04 	movi	r2,48
+ 8043c10:	d88028c5 	stb	r2,163(sp)
+ 8043c14:	dc0028c4 	addi	r16,sp,163
+ 8043c18:	0000ba06 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 8043c1c:	21003fcc 	andi	r4,r4,255
+ 8043c20:	2005951e 	bne	r4,zero,8045278 <___svfprintf_internal_r+0x1f38>
+ 8043c24:	6080080c 	andi	r2,r12,32
+ 8043c28:	63000414 	ori	r12,r12,16
+ 8043c2c:	1000a61e 	bne	r2,zero,8043ec8 <___svfprintf_internal_r+0xb88>
+ 8043c30:	d8800617 	ldw	r2,24(sp)
+ 8043c34:	10800104 	addi	r2,r2,4
+ 8043c38:	d8c00617 	ldw	r3,24(sp)
+ 8043c3c:	002b883a 	mov	r21,zero
+ 8043c40:	d8800615 	stw	r2,24(sp)
+ 8043c44:	1d000017 	ldw	r20,0(r3)
+ 8043c48:	0005883a 	mov	r2,zero
+ 8043c4c:	003fe306 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043c50:	21003fcc 	andi	r4,r4,255
+ 8043c54:	20058e1e 	bne	r4,zero,8045290 <___svfprintf_internal_r+0x1f50>
+ 8043c58:	d8c00617 	ldw	r3,24(sp)
+ 8043c5c:	00a00034 	movhi	r2,32768
+ 8043c60:	10bfffc4 	addi	r2,r2,-1
+ 8043c64:	1d000117 	ldw	r20,4(r3)
+ 8043c68:	1c800017 	ldw	r18,0(r3)
+ 8043c6c:	01dffc34 	movhi	r7,32752
+ 8043c70:	a0a0703a 	and	r16,r20,r2
+ 8043c74:	01bfffc4 	movi	r6,-1
+ 8043c78:	18800204 	addi	r2,r3,8
+ 8043c7c:	39ffffc4 	addi	r7,r7,-1
+ 8043c80:	9009883a 	mov	r4,r18
+ 8043c84:	800b883a 	mov	r5,r16
+ 8043c88:	da000f15 	stw	r8,60(sp)
+ 8043c8c:	dac00e15 	stw	r11,56(sp)
+ 8043c90:	db000715 	stw	r12,28(sp)
+ 8043c94:	dd000a15 	stw	r20,40(sp)
+ 8043c98:	dc800915 	stw	r18,36(sp)
+ 8043c9c:	d8800615 	stw	r2,24(sp)
+ 8043ca0:	800f5580 	call	800f558 <__unorddf2>
+ 8043ca4:	db000717 	ldw	r12,28(sp)
+ 8043ca8:	dac00e17 	ldw	r11,56(sp)
+ 8043cac:	da000f17 	ldw	r8,60(sp)
+ 8043cb0:	1002d91e 	bne	r2,zero,8044818 <___svfprintf_internal_r+0x14d8>
+ 8043cb4:	01dffc34 	movhi	r7,32752
+ 8043cb8:	01bfffc4 	movi	r6,-1
+ 8043cbc:	39ffffc4 	addi	r7,r7,-1
+ 8043cc0:	9009883a 	mov	r4,r18
+ 8043cc4:	800b883a 	mov	r5,r16
+ 8043cc8:	800e4700 	call	800e470 <__ledf2>
+ 8043ccc:	db000717 	ldw	r12,28(sp)
+ 8043cd0:	dac00e17 	ldw	r11,56(sp)
+ 8043cd4:	da000f17 	ldw	r8,60(sp)
+ 8043cd8:	0082cf0e 	bge	zero,r2,8044818 <___svfprintf_internal_r+0x14d8>
+ 8043cdc:	000d883a 	mov	r6,zero
+ 8043ce0:	000f883a 	mov	r7,zero
+ 8043ce4:	9009883a 	mov	r4,r18
+ 8043ce8:	a00b883a 	mov	r5,r20
+ 8043cec:	da000e15 	stw	r8,56(sp)
+ 8043cf0:	800e4700 	call	800e470 <__ledf2>
+ 8043cf4:	db000717 	ldw	r12,28(sp)
+ 8043cf8:	da000e17 	ldw	r8,56(sp)
+ 8043cfc:	1004db16 	blt	r2,zero,804506c <___svfprintf_internal_r+0x1d2c>
+ 8043d00:	db401543 	ldbu	r13,85(sp)
+ 8043d04:	e0801210 	cmplti	r2,fp,72
+ 8043d08:	1004b51e 	bne	r2,zero,8044fe0 <___svfprintf_internal_r+0x1ca0>
+ 8043d0c:	04020134 	movhi	r16,2052
+ 8043d10:	841d1804 	addi	r16,r16,29792
+ 8043d14:	04bfdfc4 	movi	r18,-129
+ 8043d18:	64a4703a 	and	r18,r12,r18
+ 8043d1c:	050000c4 	movi	r20,3
+ 8043d20:	054000c4 	movi	r21,3
+ 8043d24:	0017883a 	mov	r11,zero
+ 8043d28:	d8000715 	stw	zero,28(sp)
+ 8043d2c:	00007906 	br	8043f14 <___svfprintf_internal_r+0xbd4>
+ 8043d30:	21003fcc 	andi	r4,r4,255
+ 8043d34:	20054c1e 	bne	r4,zero,8045268 <___svfprintf_internal_r+0x1f28>
+ 8043d38:	6080080c 	andi	r2,r12,32
+ 8043d3c:	63000414 	ori	r12,r12,16
+ 8043d40:	10005a1e 	bne	r2,zero,8043eac <___svfprintf_internal_r+0xb6c>
+ 8043d44:	d8800617 	ldw	r2,24(sp)
+ 8043d48:	10800104 	addi	r2,r2,4
+ 8043d4c:	d8c00617 	ldw	r3,24(sp)
+ 8043d50:	1d000017 	ldw	r20,0(r3)
+ 8043d54:	d8800615 	stw	r2,24(sp)
+ 8043d58:	a02bd7fa 	srai	r21,r20,31
+ 8043d5c:	a805883a 	mov	r2,r21
+ 8043d60:	103edb0e 	bge	r2,zero,80438d0 <___svfprintf_internal_r+0x590>
+ 8043d64:	0529c83a 	sub	r20,zero,r20
+ 8043d68:	a004c03a 	cmpne	r2,r20,zero
+ 8043d6c:	056bc83a 	sub	r21,zero,r21
+ 8043d70:	a8abc83a 	sub	r21,r21,r2
+ 8043d74:	00800b44 	movi	r2,45
+ 8043d78:	d8801545 	stb	r2,85(sp)
+ 8043d7c:	58ffffe0 	cmpeqi	r3,r11,-1
+ 8043d80:	03400b44 	movi	r13,45
+ 8043d84:	00800044 	movi	r2,1
+ 8043d88:	183f9826 	beq	r3,zero,8043bec <___svfprintf_internal_r+0x8ac>
+ 8043d8c:	10c00060 	cmpeqi	r3,r2,1
+ 8043d90:	1800541e 	bne	r3,zero,8043ee4 <___svfprintf_internal_r+0xba4>
+ 8043d94:	108000a0 	cmpeqi	r2,r2,2
+ 8043d98:	1001e81e 	bne	r2,zero,804453c <___svfprintf_internal_r+0x11fc>
+ 8043d9c:	b807883a 	mov	r3,r23
+ 8043da0:	00000106 	br	8043da8 <___svfprintf_internal_r+0xa68>
+ 8043da4:	8007883a 	mov	r3,r16
+ 8043da8:	a008d0fa 	srli	r4,r20,3
+ 8043dac:	a80a977a 	slli	r5,r21,29
+ 8043db0:	a82ad0fa 	srli	r21,r21,3
+ 8043db4:	a50001cc 	andi	r20,r20,7
+ 8043db8:	a0800c04 	addi	r2,r20,48
+ 8043dbc:	2928b03a 	or	r20,r5,r4
+ 8043dc0:	18bfffc5 	stb	r2,-1(r3)
+ 8043dc4:	a548b03a 	or	r4,r20,r21
+ 8043dc8:	1c3fffc4 	addi	r16,r3,-1
+ 8043dcc:	203ff51e 	bne	r4,zero,8043da4 <___svfprintf_internal_r+0xa64>
+ 8043dd0:	6100004c 	andi	r4,r12,1
+ 8043dd4:	20007626 	beq	r4,zero,8043fb0 <___svfprintf_internal_r+0xc70>
+ 8043dd8:	10803fcc 	andi	r2,r2,255
+ 8043ddc:	1080201c 	xori	r2,r2,128
+ 8043de0:	10bfe004 	addi	r2,r2,-128
+ 8043de4:	10800c18 	cmpnei	r2,r2,48
+ 8043de8:	10007126 	beq	r2,zero,8043fb0 <___svfprintf_internal_r+0xc70>
+ 8043dec:	18ffff84 	addi	r3,r3,-2
+ 8043df0:	00800c04 	movi	r2,48
+ 8043df4:	80bfffc5 	stb	r2,-1(r16)
+ 8043df8:	b8ebc83a 	sub	r21,r23,r3
+ 8043dfc:	6025883a 	mov	r18,r12
+ 8043e00:	1821883a 	mov	r16,r3
+ 8043e04:	00003f06 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 8043e08:	21003fcc 	andi	r4,r4,255
+ 8043e0c:	2005121e 	bne	r4,zero,8045258 <___svfprintf_internal_r+0x1f18>
+ 8043e10:	00820134 	movhi	r2,2052
+ 8043e14:	109d1b04 	addi	r2,r2,29804
+ 8043e18:	d8800c15 	stw	r2,48(sp)
+ 8043e1c:	6080080c 	andi	r2,r12,32
+ 8043e20:	103e681e 	bne	r2,zero,80437c4 <___svfprintf_internal_r+0x484>
+ 8043e24:	d8c00617 	ldw	r3,24(sp)
+ 8043e28:	6080040c 	andi	r2,r12,16
+ 8043e2c:	1d000017 	ldw	r20,0(r3)
+ 8043e30:	18c00104 	addi	r3,r3,4
+ 8043e34:	d8c00615 	stw	r3,24(sp)
+ 8043e38:	10025f1e 	bne	r2,zero,80447b8 <___svfprintf_internal_r+0x1478>
+ 8043e3c:	6080100c 	andi	r2,r12,64
+ 8043e40:	10025d26 	beq	r2,zero,80447b8 <___svfprintf_internal_r+0x1478>
+ 8043e44:	a53fffcc 	andi	r20,r20,65535
+ 8043e48:	002b883a 	mov	r21,zero
+ 8043e4c:	003e6206 	br	80437d8 <___svfprintf_internal_r+0x498>
+ 8043e50:	21003fcc 	andi	r4,r4,255
+ 8043e54:	2005121e 	bne	r4,zero,80452a0 <___svfprintf_internal_r+0x1f60>
+ 8043e58:	6080080c 	andi	r2,r12,32
+ 8043e5c:	63000414 	ori	r12,r12,16
+ 8043e60:	10000b1e 	bne	r2,zero,8043e90 <___svfprintf_internal_r+0xb50>
+ 8043e64:	d8800617 	ldw	r2,24(sp)
+ 8043e68:	10800104 	addi	r2,r2,4
+ 8043e6c:	d8c00617 	ldw	r3,24(sp)
+ 8043e70:	002b883a 	mov	r21,zero
+ 8043e74:	d8800615 	stw	r2,24(sp)
+ 8043e78:	1d000017 	ldw	r20,0(r3)
+ 8043e7c:	00800044 	movi	r2,1
+ 8043e80:	003f5606 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043e84:	63000214 	ori	r12,r12,8
+ 8043e88:	b2800007 	ldb	r10,0(r22)
+ 8043e8c:	003d7806 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8043e90:	d8c00617 	ldw	r3,24(sp)
+ 8043e94:	00800044 	movi	r2,1
+ 8043e98:	1d000017 	ldw	r20,0(r3)
+ 8043e9c:	1d400117 	ldw	r21,4(r3)
+ 8043ea0:	18c00204 	addi	r3,r3,8
+ 8043ea4:	d8c00615 	stw	r3,24(sp)
+ 8043ea8:	003f4c06 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043eac:	d8c00617 	ldw	r3,24(sp)
+ 8043eb0:	18800117 	ldw	r2,4(r3)
+ 8043eb4:	1d000017 	ldw	r20,0(r3)
+ 8043eb8:	18c00204 	addi	r3,r3,8
+ 8043ebc:	d8c00615 	stw	r3,24(sp)
+ 8043ec0:	102b883a 	mov	r21,r2
+ 8043ec4:	003e8106 	br	80438cc <___svfprintf_internal_r+0x58c>
+ 8043ec8:	d8c00617 	ldw	r3,24(sp)
+ 8043ecc:	0005883a 	mov	r2,zero
+ 8043ed0:	1d000017 	ldw	r20,0(r3)
+ 8043ed4:	1d400117 	ldw	r21,4(r3)
+ 8043ed8:	18c00204 	addi	r3,r3,8
+ 8043edc:	d8c00615 	stw	r3,24(sp)
+ 8043ee0:	003f3e06 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8043ee4:	a800111e 	bne	r21,zero,8043f2c <___svfprintf_internal_r+0xbec>
+ 8043ee8:	a08002a8 	cmpgeui	r2,r20,10
+ 8043eec:	10000f1e 	bne	r2,zero,8043f2c <___svfprintf_internal_r+0xbec>
+ 8043ef0:	a5000c04 	addi	r20,r20,48
+ 8043ef4:	dd0028c5 	stb	r20,163(sp)
+ 8043ef8:	6025883a 	mov	r18,r12
+ 8043efc:	05400044 	movi	r21,1
+ 8043f00:	dc0028c4 	addi	r16,sp,163
+ 8043f04:	5829883a 	mov	r20,r11
+ 8043f08:	5d40010e 	bge	r11,r21,8043f10 <___svfprintf_internal_r+0xbd0>
+ 8043f0c:	a829883a 	mov	r20,r21
+ 8043f10:	d8000715 	stw	zero,28(sp)
+ 8043f14:	6b403fcc 	andi	r13,r13,255
+ 8043f18:	6b40201c 	xori	r13,r13,128
+ 8043f1c:	6b7fe004 	addi	r13,r13,-128
+ 8043f20:	683e8426 	beq	r13,zero,8043934 <___svfprintf_internal_r+0x5f4>
+ 8043f24:	a5000044 	addi	r20,r20,1
+ 8043f28:	003e8206 	br	8043934 <___svfprintf_internal_r+0x5f4>
+ 8043f2c:	dc400e15 	stw	r17,56(sp)
+ 8043f30:	b821883a 	mov	r16,r23
+ 8043f34:	a823883a 	mov	r17,r21
+ 8043f38:	db000715 	stw	r12,28(sp)
+ 8043f3c:	982b883a 	mov	r21,r19
+ 8043f40:	dac00f15 	stw	r11,60(sp)
+ 8043f44:	4025883a 	mov	r18,r8
+ 8043f48:	6827883a 	mov	r19,r13
+ 8043f4c:	00000206 	br	8043f58 <___svfprintf_internal_r+0xc18>
+ 8043f50:	1029883a 	mov	r20,r2
+ 8043f54:	1823883a 	mov	r17,r3
+ 8043f58:	a009883a 	mov	r4,r20
+ 8043f5c:	880b883a 	mov	r5,r17
+ 8043f60:	01800284 	movi	r6,10
+ 8043f64:	000f883a 	mov	r7,zero
+ 8043f68:	800c9c00 	call	800c9c0 <__umoddi3>
+ 8043f6c:	10800c04 	addi	r2,r2,48
+ 8043f70:	843fffc4 	addi	r16,r16,-1
+ 8043f74:	a009883a 	mov	r4,r20
+ 8043f78:	880b883a 	mov	r5,r17
+ 8043f7c:	80800005 	stb	r2,0(r16)
+ 8043f80:	01800284 	movi	r6,10
+ 8043f84:	000f883a 	mov	r7,zero
+ 8043f88:	800c4280 	call	800c428 <__udivdi3>
+ 8043f8c:	883ff01e 	bne	r17,zero,8043f50 <___svfprintf_internal_r+0xc10>
+ 8043f90:	a50002a8 	cmpgeui	r20,r20,10
+ 8043f94:	a03fee1e 	bne	r20,zero,8043f50 <___svfprintf_internal_r+0xc10>
+ 8043f98:	db000717 	ldw	r12,28(sp)
+ 8043f9c:	dc400e17 	ldw	r17,56(sp)
+ 8043fa0:	dac00f17 	ldw	r11,60(sp)
+ 8043fa4:	981b883a 	mov	r13,r19
+ 8043fa8:	9011883a 	mov	r8,r18
+ 8043fac:	a827883a 	mov	r19,r21
+ 8043fb0:	bc2bc83a 	sub	r21,r23,r16
+ 8043fb4:	6025883a 	mov	r18,r12
+ 8043fb8:	003fd206 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 8043fbc:	e2801990 	cmplti	r10,fp,102
+ 8043fc0:	5000be1e 	bne	r10,zero,80442bc <___svfprintf_internal_r+0xf7c>
+ 8043fc4:	d9000917 	ldw	r4,36(sp)
+ 8043fc8:	d9400a17 	ldw	r5,40(sp)
+ 8043fcc:	000d883a 	mov	r6,zero
+ 8043fd0:	000f883a 	mov	r7,zero
+ 8043fd4:	da000f15 	stw	r8,60(sp)
+ 8043fd8:	d8c00e15 	stw	r3,56(sp)
+ 8043fdc:	800e3000 	call	800e300 <__eqdf2>
+ 8043fe0:	d8c00e17 	ldw	r3,56(sp)
+ 8043fe4:	da000f17 	ldw	r8,60(sp)
+ 8043fe8:	1001641e 	bne	r2,zero,804457c <___svfprintf_internal_r+0x123c>
+ 8043fec:	d8801d17 	ldw	r2,116(sp)
+ 8043ff0:	01020134 	movhi	r4,2052
+ 8043ff4:	211d2704 	addi	r4,r4,29852
+ 8043ff8:	10800044 	addi	r2,r2,1
+ 8043ffc:	18c00044 	addi	r3,r3,1
+ 8044000:	41000015 	stw	r4,0(r8)
+ 8044004:	01000044 	movi	r4,1
+ 8044008:	d8801d15 	stw	r2,116(sp)
+ 804400c:	41000115 	stw	r4,4(r8)
+ 8044010:	d8c01e15 	stw	r3,120(sp)
+ 8044014:	10800208 	cmpgei	r2,r2,8
+ 8044018:	1002f81e 	bne	r2,zero,8044bfc <___svfprintf_internal_r+0x18bc>
+ 804401c:	42000204 	addi	r8,r8,8
+ 8044020:	d8801617 	ldw	r2,88(sp)
+ 8044024:	d8c00817 	ldw	r3,32(sp)
+ 8044028:	10c00216 	blt	r2,r3,8044034 <___svfprintf_internal_r+0xcf4>
+ 804402c:	9080004c 	andi	r2,r18,1
+ 8044030:	10026826 	beq	r2,zero,80449d4 <___svfprintf_internal_r+0x1694>
+ 8044034:	d8800d17 	ldw	r2,52(sp)
+ 8044038:	d8c01e17 	ldw	r3,120(sp)
+ 804403c:	d9000b17 	ldw	r4,44(sp)
+ 8044040:	40800015 	stw	r2,0(r8)
+ 8044044:	d8801d17 	ldw	r2,116(sp)
+ 8044048:	20c7883a 	add	r3,r4,r3
+ 804404c:	41000115 	stw	r4,4(r8)
+ 8044050:	10800044 	addi	r2,r2,1
+ 8044054:	d8801d15 	stw	r2,116(sp)
+ 8044058:	d8c01e15 	stw	r3,120(sp)
+ 804405c:	10800208 	cmpgei	r2,r2,8
+ 8044060:	1003021e 	bne	r2,zero,8044c6c <___svfprintf_internal_r+0x192c>
+ 8044064:	42000204 	addi	r8,r8,8
+ 8044068:	d8800817 	ldw	r2,32(sp)
+ 804406c:	143fffc4 	addi	r16,r2,-1
+ 8044070:	043e630e 	bge	zero,r16,8043a00 <___svfprintf_internal_r+0x6c0>
+ 8044074:	03020174 	movhi	r12,2053
+ 8044078:	81000450 	cmplti	r4,r16,17
+ 804407c:	632e3444 	addi	r12,r12,-18223
+ 8044080:	d8801d17 	ldw	r2,116(sp)
+ 8044084:	2003381e 	bne	r4,zero,8044d68 <___svfprintf_internal_r+0x1a28>
+ 8044088:	dc400715 	stw	r17,28(sp)
+ 804408c:	05400404 	movi	r21,16
+ 8044090:	df000517 	ldw	fp,20(sp)
+ 8044094:	6023883a 	mov	r17,r12
+ 8044098:	00000406 	br	80440ac <___svfprintf_internal_r+0xd6c>
+ 804409c:	42000204 	addi	r8,r8,8
+ 80440a0:	843ffc04 	addi	r16,r16,-16
+ 80440a4:	81000448 	cmpgei	r4,r16,17
+ 80440a8:	20032d26 	beq	r4,zero,8044d60 <___svfprintf_internal_r+0x1a20>
+ 80440ac:	10800044 	addi	r2,r2,1
+ 80440b0:	18c00404 	addi	r3,r3,16
+ 80440b4:	44400015 	stw	r17,0(r8)
+ 80440b8:	45400115 	stw	r21,4(r8)
+ 80440bc:	d8c01e15 	stw	r3,120(sp)
+ 80440c0:	d8801d15 	stw	r2,116(sp)
+ 80440c4:	11000208 	cmpgei	r4,r2,8
+ 80440c8:	203ff426 	beq	r4,zero,804409c <___svfprintf_internal_r+0xd5c>
+ 80440cc:	d9801c04 	addi	r6,sp,112
+ 80440d0:	980b883a 	mov	r5,r19
+ 80440d4:	e009883a 	mov	r4,fp
+ 80440d8:	80456900 	call	8045690 <__ssprint_r>
+ 80440dc:	103d571e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80440e0:	d8c01e17 	ldw	r3,120(sp)
+ 80440e4:	d8801d17 	ldw	r2,116(sp)
+ 80440e8:	b811883a 	mov	r8,r23
+ 80440ec:	003fec06 	br	80440a0 <___svfprintf_internal_r+0xd60>
+ 80440f0:	8d0fc83a 	sub	r7,r17,r20
+ 80440f4:	01fe340e 	bge	zero,r7,80439c8 <___svfprintf_internal_r+0x688>
+ 80440f8:	03020174 	movhi	r12,2053
+ 80440fc:	39000450 	cmplti	r4,r7,17
+ 8044100:	632e3444 	addi	r12,r12,-18223
+ 8044104:	d8801d17 	ldw	r2,116(sp)
+ 8044108:	2000271e 	bne	r4,zero,80441a8 <___svfprintf_internal_r+0xe68>
+ 804410c:	dc800e15 	stw	r18,56(sp)
+ 8044110:	dc000f15 	stw	r16,60(sp)
+ 8044114:	dc401015 	stw	r17,64(sp)
+ 8044118:	03400404 	movi	r13,16
+ 804411c:	3821883a 	mov	r16,r7
+ 8044120:	dac01215 	stw	r11,72(sp)
+ 8044124:	dc400517 	ldw	r17,20(sp)
+ 8044128:	6025883a 	mov	r18,r12
+ 804412c:	00000406 	br	8044140 <___svfprintf_internal_r+0xe00>
+ 8044130:	843ffc04 	addi	r16,r16,-16
+ 8044134:	81000448 	cmpgei	r4,r16,17
+ 8044138:	42000204 	addi	r8,r8,8
+ 804413c:	20001426 	beq	r4,zero,8044190 <___svfprintf_internal_r+0xe50>
+ 8044140:	10800044 	addi	r2,r2,1
+ 8044144:	18c00404 	addi	r3,r3,16
+ 8044148:	44800015 	stw	r18,0(r8)
+ 804414c:	43400115 	stw	r13,4(r8)
+ 8044150:	d8c01e15 	stw	r3,120(sp)
+ 8044154:	d8801d15 	stw	r2,116(sp)
+ 8044158:	11000208 	cmpgei	r4,r2,8
+ 804415c:	203ff426 	beq	r4,zero,8044130 <___svfprintf_internal_r+0xdf0>
+ 8044160:	d9801c04 	addi	r6,sp,112
+ 8044164:	980b883a 	mov	r5,r19
+ 8044168:	8809883a 	mov	r4,r17
+ 804416c:	80456900 	call	8045690 <__ssprint_r>
+ 8044170:	103d321e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044174:	843ffc04 	addi	r16,r16,-16
+ 8044178:	81000448 	cmpgei	r4,r16,17
+ 804417c:	d8c01e17 	ldw	r3,120(sp)
+ 8044180:	d8801d17 	ldw	r2,116(sp)
+ 8044184:	b811883a 	mov	r8,r23
+ 8044188:	03400404 	movi	r13,16
+ 804418c:	203fec1e 	bne	r4,zero,8044140 <___svfprintf_internal_r+0xe00>
+ 8044190:	800f883a 	mov	r7,r16
+ 8044194:	9019883a 	mov	r12,r18
+ 8044198:	dc000f17 	ldw	r16,60(sp)
+ 804419c:	dc401017 	ldw	r17,64(sp)
+ 80441a0:	dac01217 	ldw	r11,72(sp)
+ 80441a4:	dc800e17 	ldw	r18,56(sp)
+ 80441a8:	10800044 	addi	r2,r2,1
+ 80441ac:	19c7883a 	add	r3,r3,r7
+ 80441b0:	d8801d15 	stw	r2,116(sp)
+ 80441b4:	43000015 	stw	r12,0(r8)
+ 80441b8:	41c00115 	stw	r7,4(r8)
+ 80441bc:	d8c01e15 	stw	r3,120(sp)
+ 80441c0:	10800208 	cmpgei	r2,r2,8
+ 80441c4:	1002941e 	bne	r2,zero,8044c18 <___svfprintf_internal_r+0x18d8>
+ 80441c8:	5d4fc83a 	sub	r7,r11,r21
+ 80441cc:	42000204 	addi	r8,r8,8
+ 80441d0:	01fdff0e 	bge	zero,r7,80439d0 <___svfprintf_internal_r+0x690>
+ 80441d4:	03020174 	movhi	r12,2053
+ 80441d8:	39000450 	cmplti	r4,r7,17
+ 80441dc:	632e3444 	addi	r12,r12,-18223
+ 80441e0:	d8801d17 	ldw	r2,116(sp)
+ 80441e4:	2000251e 	bne	r4,zero,804427c <___svfprintf_internal_r+0xf3c>
+ 80441e8:	dc800e15 	stw	r18,56(sp)
+ 80441ec:	dc000f15 	stw	r16,60(sp)
+ 80441f0:	dc401015 	stw	r17,64(sp)
+ 80441f4:	02c00404 	movi	r11,16
+ 80441f8:	3821883a 	mov	r16,r7
+ 80441fc:	dc400517 	ldw	r17,20(sp)
+ 8044200:	6025883a 	mov	r18,r12
+ 8044204:	00000406 	br	8044218 <___svfprintf_internal_r+0xed8>
+ 8044208:	843ffc04 	addi	r16,r16,-16
+ 804420c:	81000448 	cmpgei	r4,r16,17
+ 8044210:	42000204 	addi	r8,r8,8
+ 8044214:	20001426 	beq	r4,zero,8044268 <___svfprintf_internal_r+0xf28>
+ 8044218:	10800044 	addi	r2,r2,1
+ 804421c:	18c00404 	addi	r3,r3,16
+ 8044220:	44800015 	stw	r18,0(r8)
+ 8044224:	42c00115 	stw	r11,4(r8)
+ 8044228:	d8c01e15 	stw	r3,120(sp)
+ 804422c:	d8801d15 	stw	r2,116(sp)
+ 8044230:	11000208 	cmpgei	r4,r2,8
+ 8044234:	203ff426 	beq	r4,zero,8044208 <___svfprintf_internal_r+0xec8>
+ 8044238:	d9801c04 	addi	r6,sp,112
+ 804423c:	980b883a 	mov	r5,r19
+ 8044240:	8809883a 	mov	r4,r17
+ 8044244:	80456900 	call	8045690 <__ssprint_r>
+ 8044248:	103cfc1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 804424c:	843ffc04 	addi	r16,r16,-16
+ 8044250:	81000448 	cmpgei	r4,r16,17
+ 8044254:	d8c01e17 	ldw	r3,120(sp)
+ 8044258:	d8801d17 	ldw	r2,116(sp)
+ 804425c:	b811883a 	mov	r8,r23
+ 8044260:	02c00404 	movi	r11,16
+ 8044264:	203fec1e 	bne	r4,zero,8044218 <___svfprintf_internal_r+0xed8>
+ 8044268:	800f883a 	mov	r7,r16
+ 804426c:	9019883a 	mov	r12,r18
+ 8044270:	dc401017 	ldw	r17,64(sp)
+ 8044274:	dc000f17 	ldw	r16,60(sp)
+ 8044278:	dc800e17 	ldw	r18,56(sp)
+ 804427c:	10800044 	addi	r2,r2,1
+ 8044280:	19c7883a 	add	r3,r3,r7
+ 8044284:	d8801d15 	stw	r2,116(sp)
+ 8044288:	43000015 	stw	r12,0(r8)
+ 804428c:	41c00115 	stw	r7,4(r8)
+ 8044290:	d8c01e15 	stw	r3,120(sp)
+ 8044294:	10800208 	cmpgei	r2,r2,8
+ 8044298:	10013f1e 	bne	r2,zero,8044798 <___svfprintf_internal_r+0x1458>
+ 804429c:	42000204 	addi	r8,r8,8
+ 80442a0:	003dcb06 	br	80439d0 <___svfprintf_internal_r+0x690>
+ 80442a4:	d9000517 	ldw	r4,20(sp)
+ 80442a8:	d9801c04 	addi	r6,sp,112
+ 80442ac:	980b883a 	mov	r5,r19
+ 80442b0:	80456900 	call	8045690 <__ssprint_r>
+ 80442b4:	103ddc26 	beq	r2,zero,8043a28 <___svfprintf_internal_r+0x6e8>
+ 80442b8:	003ce006 	br	804363c <___svfprintf_internal_r+0x2fc>
+ 80442bc:	d8800817 	ldw	r2,32(sp)
+ 80442c0:	df001d17 	ldw	fp,116(sp)
+ 80442c4:	18c00044 	addi	r3,r3,1
+ 80442c8:	10800088 	cmpgei	r2,r2,2
+ 80442cc:	e5400044 	addi	r21,fp,1
+ 80442d0:	42800204 	addi	r10,r8,8
+ 80442d4:	10010226 	beq	r2,zero,80446e0 <___svfprintf_internal_r+0x13a0>
+ 80442d8:	00800044 	movi	r2,1
+ 80442dc:	40800115 	stw	r2,4(r8)
+ 80442e0:	44000015 	stw	r16,0(r8)
+ 80442e4:	d8c01e15 	stw	r3,120(sp)
+ 80442e8:	dd401d15 	stw	r21,116(sp)
+ 80442ec:	a8800210 	cmplti	r2,r21,8
+ 80442f0:	10013e26 	beq	r2,zero,80447ec <___svfprintf_internal_r+0x14ac>
+ 80442f4:	d8800b17 	ldw	r2,44(sp)
+ 80442f8:	d9000d17 	ldw	r4,52(sp)
+ 80442fc:	ad400044 	addi	r21,r21,1
+ 8044300:	1887883a 	add	r3,r3,r2
+ 8044304:	50800115 	stw	r2,4(r10)
+ 8044308:	51000015 	stw	r4,0(r10)
+ 804430c:	d8c01e15 	stw	r3,120(sp)
+ 8044310:	dd401d15 	stw	r21,116(sp)
+ 8044314:	a8800208 	cmpgei	r2,r21,8
+ 8044318:	10012b1e 	bne	r2,zero,80447c8 <___svfprintf_internal_r+0x1488>
+ 804431c:	52800204 	addi	r10,r10,8
+ 8044320:	d8800817 	ldw	r2,32(sp)
+ 8044324:	d9000917 	ldw	r4,36(sp)
+ 8044328:	d9400a17 	ldw	r5,40(sp)
+ 804432c:	52000204 	addi	r8,r10,8
+ 8044330:	12ffffc4 	addi	r11,r2,-1
+ 8044334:	af000044 	addi	fp,r21,1
+ 8044338:	000d883a 	mov	r6,zero
+ 804433c:	000f883a 	mov	r7,zero
+ 8044340:	d8c01215 	stw	r3,72(sp)
+ 8044344:	da800f15 	stw	r10,60(sp)
+ 8044348:	da000e15 	stw	r8,56(sp)
+ 804434c:	dac00715 	stw	r11,28(sp)
+ 8044350:	df001015 	stw	fp,64(sp)
+ 8044354:	800e3000 	call	800e300 <__eqdf2>
+ 8044358:	dac00717 	ldw	r11,28(sp)
+ 804435c:	da000e17 	ldw	r8,56(sp)
+ 8044360:	da800f17 	ldw	r10,60(sp)
+ 8044364:	db401017 	ldw	r13,64(sp)
+ 8044368:	d8c01217 	ldw	r3,72(sp)
+ 804436c:	1000e826 	beq	r2,zero,8044710 <___svfprintf_internal_r+0x13d0>
+ 8044370:	84000044 	addi	r16,r16,1
+ 8044374:	1ac7883a 	add	r3,r3,r11
+ 8044378:	df001d15 	stw	fp,116(sp)
+ 804437c:	54000015 	stw	r16,0(r10)
+ 8044380:	52c00115 	stw	r11,4(r10)
+ 8044384:	d8c01e15 	stw	r3,120(sp)
+ 8044388:	e7000208 	cmpgei	fp,fp,8
+ 804438c:	e001da1e 	bne	fp,zero,8044af8 <___svfprintf_internal_r+0x17b8>
+ 8044390:	50800404 	addi	r2,r10,16
+ 8044394:	af000084 	addi	fp,r21,2
+ 8044398:	4015883a 	mov	r10,r8
+ 804439c:	1011883a 	mov	r8,r2
+ 80443a0:	d9001117 	ldw	r4,68(sp)
+ 80443a4:	d8801844 	addi	r2,sp,97
+ 80443a8:	df001d15 	stw	fp,116(sp)
+ 80443ac:	20c7883a 	add	r3,r4,r3
+ 80443b0:	50800015 	stw	r2,0(r10)
+ 80443b4:	51000115 	stw	r4,4(r10)
+ 80443b8:	d8c01e15 	stw	r3,120(sp)
+ 80443bc:	e7000210 	cmplti	fp,fp,8
+ 80443c0:	e03d8f1e 	bne	fp,zero,8043a00 <___svfprintf_internal_r+0x6c0>
+ 80443c4:	d9000517 	ldw	r4,20(sp)
+ 80443c8:	d9801c04 	addi	r6,sp,112
+ 80443cc:	980b883a 	mov	r5,r19
+ 80443d0:	80456900 	call	8045690 <__ssprint_r>
+ 80443d4:	103c991e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80443d8:	d8c01e17 	ldw	r3,120(sp)
+ 80443dc:	b811883a 	mov	r8,r23
+ 80443e0:	003d8706 	br	8043a00 <___svfprintf_internal_r+0x6c0>
+ 80443e4:	9019883a 	mov	r12,r18
+ 80443e8:	003e6806 	br	8043d8c <___svfprintf_internal_r+0xa4c>
+ 80443ec:	03020174 	movhi	r12,2053
+ 80443f0:	39000450 	cmplti	r4,r7,17
+ 80443f4:	632e3844 	addi	r12,r12,-18207
+ 80443f8:	d8801d17 	ldw	r2,116(sp)
+ 80443fc:	20002b1e 	bne	r4,zero,80444ac <___svfprintf_internal_r+0x116c>
+ 8044400:	dc801015 	stw	r18,64(sp)
+ 8044404:	dc001215 	stw	r16,72(sp)
+ 8044408:	dc401315 	stw	r17,76(sp)
+ 804440c:	03c00404 	movi	r15,16
+ 8044410:	db800e15 	stw	r14,56(sp)
+ 8044414:	db400f15 	stw	r13,60(sp)
+ 8044418:	dac01415 	stw	r11,80(sp)
+ 804441c:	3821883a 	mov	r16,r7
+ 8044420:	dc400517 	ldw	r17,20(sp)
+ 8044424:	6025883a 	mov	r18,r12
+ 8044428:	00000406 	br	804443c <___svfprintf_internal_r+0x10fc>
+ 804442c:	843ffc04 	addi	r16,r16,-16
+ 8044430:	81000448 	cmpgei	r4,r16,17
+ 8044434:	42000204 	addi	r8,r8,8
+ 8044438:	20001426 	beq	r4,zero,804448c <___svfprintf_internal_r+0x114c>
+ 804443c:	10800044 	addi	r2,r2,1
+ 8044440:	18c00404 	addi	r3,r3,16
+ 8044444:	44800015 	stw	r18,0(r8)
+ 8044448:	43c00115 	stw	r15,4(r8)
+ 804444c:	d8c01e15 	stw	r3,120(sp)
+ 8044450:	d8801d15 	stw	r2,116(sp)
+ 8044454:	11000208 	cmpgei	r4,r2,8
+ 8044458:	203ff426 	beq	r4,zero,804442c <___svfprintf_internal_r+0x10ec>
+ 804445c:	d9801c04 	addi	r6,sp,112
+ 8044460:	980b883a 	mov	r5,r19
+ 8044464:	8809883a 	mov	r4,r17
+ 8044468:	80456900 	call	8045690 <__ssprint_r>
+ 804446c:	103c731e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044470:	843ffc04 	addi	r16,r16,-16
+ 8044474:	81000448 	cmpgei	r4,r16,17
+ 8044478:	d8c01e17 	ldw	r3,120(sp)
+ 804447c:	d8801d17 	ldw	r2,116(sp)
+ 8044480:	b811883a 	mov	r8,r23
+ 8044484:	03c00404 	movi	r15,16
+ 8044488:	203fec1e 	bne	r4,zero,804443c <___svfprintf_internal_r+0x10fc>
+ 804448c:	800f883a 	mov	r7,r16
+ 8044490:	9019883a 	mov	r12,r18
+ 8044494:	db800e17 	ldw	r14,56(sp)
+ 8044498:	db400f17 	ldw	r13,60(sp)
+ 804449c:	dc401317 	ldw	r17,76(sp)
+ 80444a0:	dac01417 	ldw	r11,80(sp)
+ 80444a4:	dc001217 	ldw	r16,72(sp)
+ 80444a8:	dc801017 	ldw	r18,64(sp)
+ 80444ac:	10800044 	addi	r2,r2,1
+ 80444b0:	19c7883a 	add	r3,r3,r7
+ 80444b4:	d8801d15 	stw	r2,116(sp)
+ 80444b8:	43000015 	stw	r12,0(r8)
+ 80444bc:	41c00115 	stw	r7,4(r8)
+ 80444c0:	d8c01e15 	stw	r3,120(sp)
+ 80444c4:	10800208 	cmpgei	r2,r2,8
+ 80444c8:	1001be1e 	bne	r2,zero,8044bc4 <___svfprintf_internal_r+0x1884>
+ 80444cc:	42000204 	addi	r8,r8,8
+ 80444d0:	003d2006 	br	8043954 <___svfprintf_internal_r+0x614>
+ 80444d4:	d9000517 	ldw	r4,20(sp)
+ 80444d8:	d9801c04 	addi	r6,sp,112
+ 80444dc:	980b883a 	mov	r5,r19
+ 80444e0:	dac01015 	stw	r11,64(sp)
+ 80444e4:	db400f15 	stw	r13,60(sp)
+ 80444e8:	db800e15 	stw	r14,56(sp)
+ 80444ec:	80456900 	call	8045690 <__ssprint_r>
+ 80444f0:	103c521e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80444f4:	d8c01e17 	ldw	r3,120(sp)
+ 80444f8:	b811883a 	mov	r8,r23
+ 80444fc:	dac01017 	ldw	r11,64(sp)
+ 8044500:	db400f17 	ldw	r13,60(sp)
+ 8044504:	db800e17 	ldw	r14,56(sp)
+ 8044508:	003d2006 	br	804398c <___svfprintf_internal_r+0x64c>
+ 804450c:	d9000517 	ldw	r4,20(sp)
+ 8044510:	d9801c04 	addi	r6,sp,112
+ 8044514:	980b883a 	mov	r5,r19
+ 8044518:	dac00f15 	stw	r11,60(sp)
+ 804451c:	db400e15 	stw	r13,56(sp)
+ 8044520:	80456900 	call	8045690 <__ssprint_r>
+ 8044524:	103c451e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044528:	d8c01e17 	ldw	r3,120(sp)
+ 804452c:	b811883a 	mov	r8,r23
+ 8044530:	dac00f17 	ldw	r11,60(sp)
+ 8044534:	db400e17 	ldw	r13,56(sp)
+ 8044538:	003d2106 	br	80439c0 <___svfprintf_internal_r+0x680>
+ 804453c:	d9000c17 	ldw	r4,48(sp)
+ 8044540:	b821883a 	mov	r16,r23
+ 8044544:	a08003cc 	andi	r2,r20,15
+ 8044548:	a806973a 	slli	r3,r21,28
+ 804454c:	2085883a 	add	r2,r4,r2
+ 8044550:	a028d13a 	srli	r20,r20,4
+ 8044554:	10800003 	ldbu	r2,0(r2)
+ 8044558:	a82ad13a 	srli	r21,r21,4
+ 804455c:	843fffc4 	addi	r16,r16,-1
+ 8044560:	1d28b03a 	or	r20,r3,r20
+ 8044564:	80800005 	stb	r2,0(r16)
+ 8044568:	a544b03a 	or	r2,r20,r21
+ 804456c:	103ff51e 	bne	r2,zero,8044544 <___svfprintf_internal_r+0x1204>
+ 8044570:	bc2bc83a 	sub	r21,r23,r16
+ 8044574:	6025883a 	mov	r18,r12
+ 8044578:	003e6206 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 804457c:	d9001617 	ldw	r4,88(sp)
+ 8044580:	0101680e 	bge	zero,r4,8044b24 <___svfprintf_internal_r+0x17e4>
+ 8044584:	d8800817 	ldw	r2,32(sp)
+ 8044588:	d9000717 	ldw	r4,28(sp)
+ 804458c:	1039883a 	mov	fp,r2
+ 8044590:	20810516 	blt	r4,r2,80449a8 <___svfprintf_internal_r+0x1668>
+ 8044594:	07000a0e 	bge	zero,fp,80445c0 <___svfprintf_internal_r+0x1280>
+ 8044598:	d8801d17 	ldw	r2,116(sp)
+ 804459c:	1f07883a 	add	r3,r3,fp
+ 80445a0:	44000015 	stw	r16,0(r8)
+ 80445a4:	10800044 	addi	r2,r2,1
+ 80445a8:	d8801d15 	stw	r2,116(sp)
+ 80445ac:	47000115 	stw	fp,4(r8)
+ 80445b0:	d8c01e15 	stw	r3,120(sp)
+ 80445b4:	10800208 	cmpgei	r2,r2,8
+ 80445b8:	1003011e 	bne	r2,zero,80451c0 <___svfprintf_internal_r+0x1e80>
+ 80445bc:	42000204 	addi	r8,r8,8
+ 80445c0:	e0010616 	blt	fp,zero,80449dc <___svfprintf_internal_r+0x169c>
+ 80445c4:	d8800717 	ldw	r2,28(sp)
+ 80445c8:	1739c83a 	sub	fp,r2,fp
+ 80445cc:	07011916 	blt	zero,fp,8044a34 <___svfprintf_internal_r+0x16f4>
+ 80445d0:	d9001617 	ldw	r4,88(sp)
+ 80445d4:	d8800817 	ldw	r2,32(sp)
+ 80445d8:	2080f60e 	bge	r4,r2,80449b4 <___svfprintf_internal_r+0x1674>
+ 80445dc:	d8800d17 	ldw	r2,52(sp)
+ 80445e0:	d9400b17 	ldw	r5,44(sp)
+ 80445e4:	40800015 	stw	r2,0(r8)
+ 80445e8:	d8801d17 	ldw	r2,116(sp)
+ 80445ec:	1947883a 	add	r3,r3,r5
+ 80445f0:	41400115 	stw	r5,4(r8)
+ 80445f4:	10800044 	addi	r2,r2,1
+ 80445f8:	d8801d15 	stw	r2,116(sp)
+ 80445fc:	d8c01e15 	stw	r3,120(sp)
+ 8044600:	10800208 	cmpgei	r2,r2,8
+ 8044604:	1002a61e 	bne	r2,zero,80450a0 <___svfprintf_internal_r+0x1d60>
+ 8044608:	42000204 	addi	r8,r8,8
+ 804460c:	d8800817 	ldw	r2,32(sp)
+ 8044610:	d9400717 	ldw	r5,28(sp)
+ 8044614:	1105c83a 	sub	r2,r2,r4
+ 8044618:	2901300e 	bge	r5,r4,8044adc <___svfprintf_internal_r+0x179c>
+ 804461c:	1039883a 	mov	fp,r2
+ 8044620:	07000c0e 	bge	zero,fp,8044654 <___svfprintf_internal_r+0x1314>
+ 8044624:	d9000717 	ldw	r4,28(sp)
+ 8044628:	1f07883a 	add	r3,r3,fp
+ 804462c:	47000115 	stw	fp,4(r8)
+ 8044630:	8121883a 	add	r16,r16,r4
+ 8044634:	d9001d17 	ldw	r4,116(sp)
+ 8044638:	44000015 	stw	r16,0(r8)
+ 804463c:	d8c01e15 	stw	r3,120(sp)
+ 8044640:	21000044 	addi	r4,r4,1
+ 8044644:	d9001d15 	stw	r4,116(sp)
+ 8044648:	21000208 	cmpgei	r4,r4,8
+ 804464c:	2002e71e 	bne	r4,zero,80451ec <___svfprintf_internal_r+0x1eac>
+ 8044650:	42000204 	addi	r8,r8,8
+ 8044654:	e000010e 	bge	fp,zero,804465c <___svfprintf_internal_r+0x131c>
+ 8044658:	0039883a 	mov	fp,zero
+ 804465c:	1739c83a 	sub	fp,r2,fp
+ 8044660:	073ce70e 	bge	zero,fp,8043a00 <___svfprintf_internal_r+0x6c0>
+ 8044664:	03020174 	movhi	r12,2053
+ 8044668:	e1000450 	cmplti	r4,fp,17
+ 804466c:	632e3444 	addi	r12,r12,-18223
+ 8044670:	d8801d17 	ldw	r2,116(sp)
+ 8044674:	2002741e 	bne	r4,zero,8045048 <___svfprintf_internal_r+0x1d08>
+ 8044678:	dc400715 	stw	r17,28(sp)
+ 804467c:	05400404 	movi	r21,16
+ 8044680:	dc000517 	ldw	r16,20(sp)
+ 8044684:	6023883a 	mov	r17,r12
+ 8044688:	00000406 	br	804469c <___svfprintf_internal_r+0x135c>
+ 804468c:	42000204 	addi	r8,r8,8
+ 8044690:	e73ffc04 	addi	fp,fp,-16
+ 8044694:	e1000448 	cmpgei	r4,fp,17
+ 8044698:	20026926 	beq	r4,zero,8045040 <___svfprintf_internal_r+0x1d00>
+ 804469c:	10800044 	addi	r2,r2,1
+ 80446a0:	18c00404 	addi	r3,r3,16
+ 80446a4:	44400015 	stw	r17,0(r8)
+ 80446a8:	45400115 	stw	r21,4(r8)
+ 80446ac:	d8c01e15 	stw	r3,120(sp)
+ 80446b0:	d8801d15 	stw	r2,116(sp)
+ 80446b4:	11000208 	cmpgei	r4,r2,8
+ 80446b8:	203ff426 	beq	r4,zero,804468c <___svfprintf_internal_r+0x134c>
+ 80446bc:	d9801c04 	addi	r6,sp,112
+ 80446c0:	980b883a 	mov	r5,r19
+ 80446c4:	8009883a 	mov	r4,r16
+ 80446c8:	80456900 	call	8045690 <__ssprint_r>
+ 80446cc:	103bdb1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80446d0:	d8c01e17 	ldw	r3,120(sp)
+ 80446d4:	d8801d17 	ldw	r2,116(sp)
+ 80446d8:	b811883a 	mov	r8,r23
+ 80446dc:	003fec06 	br	8044690 <___svfprintf_internal_r+0x1350>
+ 80446e0:	9080004c 	andi	r2,r18,1
+ 80446e4:	103efc1e 	bne	r2,zero,80442d8 <___svfprintf_internal_r+0xf98>
+ 80446e8:	00800044 	movi	r2,1
+ 80446ec:	dd401d15 	stw	r21,116(sp)
+ 80446f0:	44000015 	stw	r16,0(r8)
+ 80446f4:	40800115 	stw	r2,4(r8)
+ 80446f8:	d8c01e15 	stw	r3,120(sp)
+ 80446fc:	ad400208 	cmpgei	r21,r21,8
+ 8044700:	a800fd1e 	bne	r21,zero,8044af8 <___svfprintf_internal_r+0x17b8>
+ 8044704:	e7000084 	addi	fp,fp,2
+ 8044708:	42000404 	addi	r8,r8,16
+ 804470c:	003f2406 	br	80443a0 <___svfprintf_internal_r+0x1060>
+ 8044710:	02ff230e 	bge	zero,r11,80443a0 <___svfprintf_internal_r+0x1060>
+ 8044714:	58800450 	cmplti	r2,r11,17
+ 8044718:	03020174 	movhi	r12,2053
+ 804471c:	10032f1e 	bne	r2,zero,80453dc <___svfprintf_internal_r+0x209c>
+ 8044720:	632e3444 	addi	r12,r12,-18223
+ 8044724:	dc800715 	stw	r18,28(sp)
+ 8044728:	dc400e15 	stw	r17,56(sp)
+ 804472c:	04000404 	movi	r16,16
+ 8044730:	5823883a 	mov	r17,r11
+ 8044734:	df000517 	ldw	fp,20(sp)
+ 8044738:	6025883a 	mov	r18,r12
+ 804473c:	682b883a 	mov	r21,r13
+ 8044740:	00000506 	br	8044758 <___svfprintf_internal_r+0x1418>
+ 8044744:	52800204 	addi	r10,r10,8
+ 8044748:	8c7ffc04 	addi	r17,r17,-16
+ 804474c:	88800448 	cmpgei	r2,r17,17
+ 8044750:	10018e26 	beq	r2,zero,8044d8c <___svfprintf_internal_r+0x1a4c>
+ 8044754:	ad400044 	addi	r21,r21,1
+ 8044758:	18c00404 	addi	r3,r3,16
+ 804475c:	54800015 	stw	r18,0(r10)
+ 8044760:	54000115 	stw	r16,4(r10)
+ 8044764:	d8c01e15 	stw	r3,120(sp)
+ 8044768:	dd401d15 	stw	r21,116(sp)
+ 804476c:	a8800208 	cmpgei	r2,r21,8
+ 8044770:	103ff426 	beq	r2,zero,8044744 <___svfprintf_internal_r+0x1404>
+ 8044774:	d9801c04 	addi	r6,sp,112
+ 8044778:	980b883a 	mov	r5,r19
+ 804477c:	e009883a 	mov	r4,fp
+ 8044780:	80456900 	call	8045690 <__ssprint_r>
+ 8044784:	103bad1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044788:	dd401d17 	ldw	r21,116(sp)
+ 804478c:	d8c01e17 	ldw	r3,120(sp)
+ 8044790:	b815883a 	mov	r10,r23
+ 8044794:	003fec06 	br	8044748 <___svfprintf_internal_r+0x1408>
+ 8044798:	d9000517 	ldw	r4,20(sp)
+ 804479c:	d9801c04 	addi	r6,sp,112
+ 80447a0:	980b883a 	mov	r5,r19
+ 80447a4:	80456900 	call	8045690 <__ssprint_r>
+ 80447a8:	103ba41e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80447ac:	d8c01e17 	ldw	r3,120(sp)
+ 80447b0:	b811883a 	mov	r8,r23
+ 80447b4:	003c8606 	br	80439d0 <___svfprintf_internal_r+0x690>
+ 80447b8:	002b883a 	mov	r21,zero
+ 80447bc:	003c0606 	br	80437d8 <___svfprintf_internal_r+0x498>
+ 80447c0:	b025883a 	mov	r18,r22
+ 80447c4:	003b2206 	br	8043450 <___svfprintf_internal_r+0x110>
+ 80447c8:	d9000517 	ldw	r4,20(sp)
+ 80447cc:	d9801c04 	addi	r6,sp,112
+ 80447d0:	980b883a 	mov	r5,r19
+ 80447d4:	80456900 	call	8045690 <__ssprint_r>
+ 80447d8:	103b981e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80447dc:	d8c01e17 	ldw	r3,120(sp)
+ 80447e0:	dd401d17 	ldw	r21,116(sp)
+ 80447e4:	b815883a 	mov	r10,r23
+ 80447e8:	003ecd06 	br	8044320 <___svfprintf_internal_r+0xfe0>
+ 80447ec:	d9000517 	ldw	r4,20(sp)
+ 80447f0:	d9801c04 	addi	r6,sp,112
+ 80447f4:	980b883a 	mov	r5,r19
+ 80447f8:	80456900 	call	8045690 <__ssprint_r>
+ 80447fc:	103b8f1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044800:	d8c01e17 	ldw	r3,120(sp)
+ 8044804:	dd401d17 	ldw	r21,116(sp)
+ 8044808:	b815883a 	mov	r10,r23
+ 804480c:	003eb906 	br	80442f4 <___svfprintf_internal_r+0xfb4>
+ 8044810:	b821883a 	mov	r16,r23
+ 8044814:	003dbb06 	br	8043f04 <___svfprintf_internal_r+0xbc4>
+ 8044818:	d9000917 	ldw	r4,36(sp)
+ 804481c:	d9400a17 	ldw	r5,40(sp)
+ 8044820:	da000f15 	stw	r8,60(sp)
+ 8044824:	200d883a 	mov	r6,r4
+ 8044828:	280f883a 	mov	r7,r5
+ 804482c:	dac00e15 	stw	r11,56(sp)
+ 8044830:	db000715 	stw	r12,28(sp)
+ 8044834:	800f5580 	call	800f558 <__unorddf2>
+ 8044838:	db000717 	ldw	r12,28(sp)
+ 804483c:	dac00e17 	ldw	r11,56(sp)
+ 8044840:	da000f17 	ldw	r8,60(sp)
+ 8044844:	1002d91e 	bne	r2,zero,80453ac <___svfprintf_internal_r+0x206c>
+ 8044848:	00fff7c4 	movi	r3,-33
+ 804484c:	e0c6703a 	and	r3,fp,r3
+ 8044850:	58bfffe0 	cmpeqi	r2,r11,-1
+ 8044854:	d8c00715 	stw	r3,28(sp)
+ 8044858:	1002621e 	bne	r2,zero,80451e4 <___svfprintf_internal_r+0x1ea4>
+ 804485c:	188011d8 	cmpnei	r2,r3,71
+ 8044860:	1000a226 	beq	r2,zero,8044aec <___svfprintf_internal_r+0x17ac>
+ 8044864:	d8800a17 	ldw	r2,40(sp)
+ 8044868:	64804014 	ori	r18,r12,256
+ 804486c:	10021516 	blt	r2,zero,80450c4 <___svfprintf_internal_r+0x1d84>
+ 8044870:	dd000a17 	ldw	r20,40(sp)
+ 8044874:	d8000e05 	stb	zero,56(sp)
+ 8044878:	e08019a0 	cmpeqi	r2,fp,102
+ 804487c:	d8800f15 	stw	r2,60(sp)
+ 8044880:	1001531e 	bne	r2,zero,8044dd0 <___svfprintf_internal_r+0x1a90>
+ 8044884:	e08011a0 	cmpeqi	r2,fp,70
+ 8044888:	1001511e 	bne	r2,zero,8044dd0 <___svfprintf_internal_r+0x1a90>
+ 804488c:	d8800717 	ldw	r2,28(sp)
+ 8044890:	da001215 	stw	r8,72(sp)
+ 8044894:	db001015 	stw	r12,64(sp)
+ 8044898:	10801158 	cmpnei	r2,r2,69
+ 804489c:	10022b26 	beq	r2,zero,804514c <___svfprintf_internal_r+0x1e0c>
+ 80448a0:	d8801a04 	addi	r2,sp,104
+ 80448a4:	d8800315 	stw	r2,12(sp)
+ 80448a8:	d9400917 	ldw	r5,36(sp)
+ 80448ac:	d8801704 	addi	r2,sp,92
+ 80448b0:	d9000517 	ldw	r4,20(sp)
+ 80448b4:	d8800215 	stw	r2,8(sp)
+ 80448b8:	d8801604 	addi	r2,sp,88
+ 80448bc:	dac00015 	stw	r11,0(sp)
+ 80448c0:	d8800115 	stw	r2,4(sp)
+ 80448c4:	01c00084 	movi	r7,2
+ 80448c8:	a00d883a 	mov	r6,r20
+ 80448cc:	dac00815 	stw	r11,32(sp)
+ 80448d0:	80053ec0 	call	80053ec <_dtoa_r>
+ 80448d4:	dac00817 	ldw	r11,32(sp)
+ 80448d8:	1021883a 	mov	r16,r2
+ 80448dc:	e08019d8 	cmpnei	r2,fp,103
+ 80448e0:	db001017 	ldw	r12,64(sp)
+ 80448e4:	da001217 	ldw	r8,72(sp)
+ 80448e8:	582b883a 	mov	r21,r11
+ 80448ec:	1002291e 	bne	r2,zero,8045194 <___svfprintf_internal_r+0x1e54>
+ 80448f0:	6080004c 	andi	r2,r12,1
+ 80448f4:	1002291e 	bne	r2,zero,804519c <___svfprintf_internal_r+0x1e5c>
+ 80448f8:	d8c01617 	ldw	r3,88(sp)
+ 80448fc:	d8800717 	ldw	r2,28(sp)
+ 8044900:	d8c00715 	stw	r3,28(sp)
+ 8044904:	d8c01a17 	ldw	r3,104(sp)
+ 8044908:	108011e0 	cmpeqi	r2,r2,71
+ 804490c:	1c07c83a 	sub	r3,r3,r16
+ 8044910:	d8c00815 	stw	r3,32(sp)
+ 8044914:	10017126 	beq	r2,zero,8044edc <___svfprintf_internal_r+0x1b9c>
+ 8044918:	d8c00717 	ldw	r3,28(sp)
+ 804491c:	18bfff50 	cmplti	r2,r3,-3
+ 8044920:	10016d1e 	bne	r2,zero,8044ed8 <___svfprintf_internal_r+0x1b98>
+ 8044924:	58c16c16 	blt	r11,r3,8044ed8 <___svfprintf_internal_r+0x1b98>
+ 8044928:	d8800717 	ldw	r2,28(sp)
+ 804492c:	d8c00817 	ldw	r3,32(sp)
+ 8044930:	10c23d16 	blt	r2,r3,8045228 <___svfprintf_internal_r+0x1ee8>
+ 8044934:	6300004c 	andi	r12,r12,1
+ 8044938:	6002731e 	bne	r12,zero,8045308 <___svfprintf_internal_r+0x1fc8>
+ 804493c:	1029883a 	mov	r20,r2
+ 8044940:	1000010e 	bge	r2,zero,8044948 <___svfprintf_internal_r+0x1608>
+ 8044944:	0029883a 	mov	r20,zero
+ 8044948:	dd400717 	ldw	r21,28(sp)
+ 804494c:	070019c4 	movi	fp,103
+ 8044950:	d8800e07 	ldb	r2,56(sp)
+ 8044954:	10021726 	beq	r2,zero,80451b4 <___svfprintf_internal_r+0x1e74>
+ 8044958:	00800b44 	movi	r2,45
+ 804495c:	d8801545 	stb	r2,85(sp)
+ 8044960:	0017883a 	mov	r11,zero
+ 8044964:	003d6f06 	br	8043f24 <___svfprintf_internal_r+0xbe4>
+ 8044968:	d9400417 	ldw	r5,16(sp)
+ 804496c:	20800017 	ldw	r2,0(r4)
+ 8044970:	d8c00615 	stw	r3,24(sp)
+ 8044974:	2809d7fa 	srai	r4,r5,31
+ 8044978:	11400015 	stw	r5,0(r2)
+ 804497c:	11000115 	stw	r4,4(r2)
+ 8044980:	003a9506 	br	80433d8 <___svfprintf_internal_r+0x98>
+ 8044984:	00800c04 	movi	r2,48
+ 8044988:	d8801585 	stb	r2,86(sp)
+ 804498c:	df0015c5 	stb	fp,87(sp)
+ 8044990:	63000094 	ori	r12,r12,2
+ 8044994:	00800084 	movi	r2,2
+ 8044998:	003c9006 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 804499c:	0463c83a 	sub	r17,zero,r17
+ 80449a0:	d8800615 	stw	r2,24(sp)
+ 80449a4:	003b5f06 	br	8043724 <___svfprintf_internal_r+0x3e4>
+ 80449a8:	2039883a 	mov	fp,r4
+ 80449ac:	073efa16 	blt	zero,fp,8044598 <___svfprintf_internal_r+0x1258>
+ 80449b0:	003f0306 	br	80445c0 <___svfprintf_internal_r+0x1280>
+ 80449b4:	9080004c 	andi	r2,r18,1
+ 80449b8:	103f081e 	bne	r2,zero,80445dc <___svfprintf_internal_r+0x129c>
+ 80449bc:	d8800817 	ldw	r2,32(sp)
+ 80449c0:	d9400717 	ldw	r5,28(sp)
+ 80449c4:	1105c83a 	sub	r2,r2,r4
+ 80449c8:	2900440e 	bge	r5,r4,8044adc <___svfprintf_internal_r+0x179c>
+ 80449cc:	1039883a 	mov	fp,r2
+ 80449d0:	003f2006 	br	8044654 <___svfprintf_internal_r+0x1314>
+ 80449d4:	d8c01e17 	ldw	r3,120(sp)
+ 80449d8:	003c0906 	br	8043a00 <___svfprintf_internal_r+0x6c0>
+ 80449dc:	d8800717 	ldw	r2,28(sp)
+ 80449e0:	0039883a 	mov	fp,zero
+ 80449e4:	1739c83a 	sub	fp,r2,fp
+ 80449e8:	073ef90e 	bge	zero,fp,80445d0 <___svfprintf_internal_r+0x1290>
+ 80449ec:	00001106 	br	8044a34 <___svfprintf_internal_r+0x16f4>
+ 80449f0:	8009883a 	mov	r4,r16
+ 80449f4:	8002dac0 	call	8002dac <strlen>
+ 80449f8:	102b883a 	mov	r21,r2
+ 80449fc:	1029883a 	mov	r20,r2
+ 8044a00:	dc800615 	stw	r18,24(sp)
+ 8044a04:	db000717 	ldw	r12,28(sp)
+ 8044a08:	da000e17 	ldw	r8,56(sp)
+ 8044a0c:	003bc606 	br	8043928 <___svfprintf_internal_r+0x5e8>
+ 8044a10:	d9000517 	ldw	r4,20(sp)
+ 8044a14:	01401004 	movi	r5,64
+ 8044a18:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8044a1c:	98800015 	stw	r2,0(r19)
+ 8044a20:	98800415 	stw	r2,16(r19)
+ 8044a24:	10028626 	beq	r2,zero,8045440 <___svfprintf_internal_r+0x2100>
+ 8044a28:	00801004 	movi	r2,64
+ 8044a2c:	98800515 	stw	r2,20(r19)
+ 8044a30:	003a5d06 	br	80433a8 <___svfprintf_internal_r+0x68>
+ 8044a34:	03020174 	movhi	r12,2053
+ 8044a38:	e1000450 	cmplti	r4,fp,17
+ 8044a3c:	632e3444 	addi	r12,r12,-18223
+ 8044a40:	d8801d17 	ldw	r2,116(sp)
+ 8044a44:	2001741e 	bne	r4,zero,8045018 <___svfprintf_internal_r+0x1cd8>
+ 8044a48:	b009883a 	mov	r4,r22
+ 8044a4c:	dc800e15 	stw	r18,56(sp)
+ 8044a50:	dc000f15 	stw	r16,60(sp)
+ 8044a54:	882d883a 	mov	r22,r17
+ 8044a58:	05400404 	movi	r21,16
+ 8044a5c:	e023883a 	mov	r17,fp
+ 8044a60:	dc000517 	ldw	r16,20(sp)
+ 8044a64:	6025883a 	mov	r18,r12
+ 8044a68:	2039883a 	mov	fp,r4
+ 8044a6c:	00000406 	br	8044a80 <___svfprintf_internal_r+0x1740>
+ 8044a70:	42000204 	addi	r8,r8,8
+ 8044a74:	8c7ffc04 	addi	r17,r17,-16
+ 8044a78:	89000448 	cmpgei	r4,r17,17
+ 8044a7c:	20015f26 	beq	r4,zero,8044ffc <___svfprintf_internal_r+0x1cbc>
+ 8044a80:	10800044 	addi	r2,r2,1
+ 8044a84:	18c00404 	addi	r3,r3,16
+ 8044a88:	44800015 	stw	r18,0(r8)
+ 8044a8c:	45400115 	stw	r21,4(r8)
+ 8044a90:	d8c01e15 	stw	r3,120(sp)
+ 8044a94:	d8801d15 	stw	r2,116(sp)
+ 8044a98:	11000208 	cmpgei	r4,r2,8
+ 8044a9c:	203ff426 	beq	r4,zero,8044a70 <___svfprintf_internal_r+0x1730>
+ 8044aa0:	d9801c04 	addi	r6,sp,112
+ 8044aa4:	980b883a 	mov	r5,r19
+ 8044aa8:	8009883a 	mov	r4,r16
+ 8044aac:	80456900 	call	8045690 <__ssprint_r>
+ 8044ab0:	103ae21e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044ab4:	d8c01e17 	ldw	r3,120(sp)
+ 8044ab8:	d8801d17 	ldw	r2,116(sp)
+ 8044abc:	b811883a 	mov	r8,r23
+ 8044ac0:	003fec06 	br	8044a74 <___svfprintf_internal_r+0x1734>
+ 8044ac4:	d8800617 	ldw	r2,24(sp)
+ 8044ac8:	10800017 	ldw	r2,0(r2)
+ 8044acc:	d8c00615 	stw	r3,24(sp)
+ 8044ad0:	d8c00417 	ldw	r3,16(sp)
+ 8044ad4:	10c00015 	stw	r3,0(r2)
+ 8044ad8:	003a3f06 	br	80433d8 <___svfprintf_internal_r+0x98>
+ 8044adc:	d9000817 	ldw	r4,32(sp)
+ 8044ae0:	d9400717 	ldw	r5,28(sp)
+ 8044ae4:	2179c83a 	sub	fp,r4,r5
+ 8044ae8:	003ecd06 	br	8044620 <___svfprintf_internal_r+0x12e0>
+ 8044aec:	583f5d1e 	bne	r11,zero,8044864 <___svfprintf_internal_r+0x1524>
+ 8044af0:	02c00044 	movi	r11,1
+ 8044af4:	003f5b06 	br	8044864 <___svfprintf_internal_r+0x1524>
+ 8044af8:	d9000517 	ldw	r4,20(sp)
+ 8044afc:	d9801c04 	addi	r6,sp,112
+ 8044b00:	980b883a 	mov	r5,r19
+ 8044b04:	80456900 	call	8045690 <__ssprint_r>
+ 8044b08:	103acc1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044b0c:	df001d17 	ldw	fp,116(sp)
+ 8044b10:	d8c01e17 	ldw	r3,120(sp)
+ 8044b14:	da002b04 	addi	r8,sp,172
+ 8044b18:	e7000044 	addi	fp,fp,1
+ 8044b1c:	b815883a 	mov	r10,r23
+ 8044b20:	003e1f06 	br	80443a0 <___svfprintf_internal_r+0x1060>
+ 8044b24:	d8801d17 	ldw	r2,116(sp)
+ 8044b28:	01420134 	movhi	r5,2052
+ 8044b2c:	295d2704 	addi	r5,r5,29852
+ 8044b30:	10800044 	addi	r2,r2,1
+ 8044b34:	18c00044 	addi	r3,r3,1
+ 8044b38:	41400015 	stw	r5,0(r8)
+ 8044b3c:	01400044 	movi	r5,1
+ 8044b40:	d8801d15 	stw	r2,116(sp)
+ 8044b44:	41400115 	stw	r5,4(r8)
+ 8044b48:	d8c01e15 	stw	r3,120(sp)
+ 8044b4c:	10800208 	cmpgei	r2,r2,8
+ 8044b50:	10014a1e 	bne	r2,zero,804507c <___svfprintf_internal_r+0x1d3c>
+ 8044b54:	42000204 	addi	r8,r8,8
+ 8044b58:	2000541e 	bne	r4,zero,8044cac <___svfprintf_internal_r+0x196c>
+ 8044b5c:	d9000817 	ldw	r4,32(sp)
+ 8044b60:	9080004c 	andi	r2,r18,1
+ 8044b64:	1104b03a 	or	r2,r2,r4
+ 8044b68:	103ba526 	beq	r2,zero,8043a00 <___svfprintf_internal_r+0x6c0>
+ 8044b6c:	d8800d17 	ldw	r2,52(sp)
+ 8044b70:	d9000b17 	ldw	r4,44(sp)
+ 8044b74:	40800015 	stw	r2,0(r8)
+ 8044b78:	d8801d17 	ldw	r2,116(sp)
+ 8044b7c:	20c7883a 	add	r3,r4,r3
+ 8044b80:	41000115 	stw	r4,4(r8)
+ 8044b84:	10800044 	addi	r2,r2,1
+ 8044b88:	d8c01e15 	stw	r3,120(sp)
+ 8044b8c:	d8801d15 	stw	r2,116(sp)
+ 8044b90:	11000208 	cmpgei	r4,r2,8
+ 8044b94:	2001551e 	bne	r4,zero,80450ec <___svfprintf_internal_r+0x1dac>
+ 8044b98:	42000204 	addi	r8,r8,8
+ 8044b9c:	d9000817 	ldw	r4,32(sp)
+ 8044ba0:	10800044 	addi	r2,r2,1
+ 8044ba4:	d8801d15 	stw	r2,116(sp)
+ 8044ba8:	20c7883a 	add	r3,r4,r3
+ 8044bac:	44000015 	stw	r16,0(r8)
+ 8044bb0:	41000115 	stw	r4,4(r8)
+ 8044bb4:	d8c01e15 	stw	r3,120(sp)
+ 8044bb8:	10800208 	cmpgei	r2,r2,8
+ 8044bbc:	103b8f26 	beq	r2,zero,80439fc <___svfprintf_internal_r+0x6bc>
+ 8044bc0:	003e0006 	br	80443c4 <___svfprintf_internal_r+0x1084>
+ 8044bc4:	d9000517 	ldw	r4,20(sp)
+ 8044bc8:	d9801c04 	addi	r6,sp,112
+ 8044bcc:	980b883a 	mov	r5,r19
+ 8044bd0:	dac01015 	stw	r11,64(sp)
+ 8044bd4:	db400f15 	stw	r13,60(sp)
+ 8044bd8:	db800e15 	stw	r14,56(sp)
+ 8044bdc:	80456900 	call	8045690 <__ssprint_r>
+ 8044be0:	103a961e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044be4:	d8c01e17 	ldw	r3,120(sp)
+ 8044be8:	b811883a 	mov	r8,r23
+ 8044bec:	dac01017 	ldw	r11,64(sp)
+ 8044bf0:	db400f17 	ldw	r13,60(sp)
+ 8044bf4:	db800e17 	ldw	r14,56(sp)
+ 8044bf8:	003b5606 	br	8043954 <___svfprintf_internal_r+0x614>
+ 8044bfc:	d9000517 	ldw	r4,20(sp)
+ 8044c00:	d9801c04 	addi	r6,sp,112
+ 8044c04:	980b883a 	mov	r5,r19
+ 8044c08:	80456900 	call	8045690 <__ssprint_r>
+ 8044c0c:	103a8b1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044c10:	b811883a 	mov	r8,r23
+ 8044c14:	003d0206 	br	8044020 <___svfprintf_internal_r+0xce0>
+ 8044c18:	d9000517 	ldw	r4,20(sp)
+ 8044c1c:	d9801c04 	addi	r6,sp,112
+ 8044c20:	980b883a 	mov	r5,r19
+ 8044c24:	dac00e15 	stw	r11,56(sp)
+ 8044c28:	80456900 	call	8045690 <__ssprint_r>
+ 8044c2c:	103a831e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044c30:	d8c01e17 	ldw	r3,120(sp)
+ 8044c34:	b811883a 	mov	r8,r23
+ 8044c38:	dac00e17 	ldw	r11,56(sp)
+ 8044c3c:	003b6206 	br	80439c8 <___svfprintf_internal_r+0x688>
+ 8044c40:	10c00060 	cmpeqi	r3,r2,1
+ 8044c44:	9019883a 	mov	r12,r18
+ 8044c48:	183c5226 	beq	r3,zero,8043d94 <___svfprintf_internal_r+0xa54>
+ 8044c4c:	003ca806 	br	8043ef0 <___svfprintf_internal_r+0xbb0>
+ 8044c50:	b7000043 	ldbu	fp,1(r22)
+ 8044c54:	63000814 	ori	r12,r12,32
+ 8044c58:	b5800044 	addi	r22,r22,1
+ 8044c5c:	e2803fcc 	andi	r10,fp,255
+ 8044c60:	5280201c 	xori	r10,r10,128
+ 8044c64:	52bfe004 	addi	r10,r10,-128
+ 8044c68:	003a0106 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8044c6c:	d9000517 	ldw	r4,20(sp)
+ 8044c70:	d9801c04 	addi	r6,sp,112
+ 8044c74:	980b883a 	mov	r5,r19
+ 8044c78:	80456900 	call	8045690 <__ssprint_r>
+ 8044c7c:	103a6f1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044c80:	d8c01e17 	ldw	r3,120(sp)
+ 8044c84:	b811883a 	mov	r8,r23
+ 8044c88:	003cf706 	br	8044068 <___svfprintf_internal_r+0xd28>
+ 8044c8c:	588001f0 	cmpltui	r2,r11,7
+ 8044c90:	582b883a 	mov	r21,r11
+ 8044c94:	10011126 	beq	r2,zero,80450dc <___svfprintf_internal_r+0x1d9c>
+ 8044c98:	04020134 	movhi	r16,2052
+ 8044c9c:	a829883a 	mov	r20,r21
+ 8044ca0:	dc800615 	stw	r18,24(sp)
+ 8044ca4:	841d2504 	addi	r16,r16,29844
+ 8044ca8:	003b1f06 	br	8043928 <___svfprintf_internal_r+0x5e8>
+ 8044cac:	d8800d17 	ldw	r2,52(sp)
+ 8044cb0:	d9400b17 	ldw	r5,44(sp)
+ 8044cb4:	40800015 	stw	r2,0(r8)
+ 8044cb8:	d8801d17 	ldw	r2,116(sp)
+ 8044cbc:	28c7883a 	add	r3,r5,r3
+ 8044cc0:	41400115 	stw	r5,4(r8)
+ 8044cc4:	10800044 	addi	r2,r2,1
+ 8044cc8:	d8c01e15 	stw	r3,120(sp)
+ 8044ccc:	d8801d15 	stw	r2,116(sp)
+ 8044cd0:	11400208 	cmpgei	r5,r2,8
+ 8044cd4:	2801051e 	bne	r5,zero,80450ec <___svfprintf_internal_r+0x1dac>
+ 8044cd8:	42000204 	addi	r8,r8,8
+ 8044cdc:	203faf0e 	bge	r4,zero,8044b9c <___svfprintf_internal_r+0x185c>
+ 8044ce0:	03020174 	movhi	r12,2053
+ 8044ce4:	217ffc08 	cmpgei	r5,r4,-16
+ 8044ce8:	632e3444 	addi	r12,r12,-18223
+ 8044cec:	012bc83a 	sub	r21,zero,r4
+ 8044cf0:	2801711e 	bne	r5,zero,80452b8 <___svfprintf_internal_r+0x1f78>
+ 8044cf4:	dc000715 	stw	r16,28(sp)
+ 8044cf8:	07000404 	movi	fp,16
+ 8044cfc:	a821883a 	mov	r16,r21
+ 8044d00:	882b883a 	mov	r21,r17
+ 8044d04:	6023883a 	mov	r17,r12
+ 8044d08:	00000406 	br	8044d1c <___svfprintf_internal_r+0x19dc>
+ 8044d0c:	42000204 	addi	r8,r8,8
+ 8044d10:	843ffc04 	addi	r16,r16,-16
+ 8044d14:	81000448 	cmpgei	r4,r16,17
+ 8044d18:	20016326 	beq	r4,zero,80452a8 <___svfprintf_internal_r+0x1f68>
+ 8044d1c:	10800044 	addi	r2,r2,1
+ 8044d20:	18c00404 	addi	r3,r3,16
+ 8044d24:	44400015 	stw	r17,0(r8)
+ 8044d28:	47000115 	stw	fp,4(r8)
+ 8044d2c:	d8c01e15 	stw	r3,120(sp)
+ 8044d30:	d8801d15 	stw	r2,116(sp)
+ 8044d34:	11000208 	cmpgei	r4,r2,8
+ 8044d38:	203ff426 	beq	r4,zero,8044d0c <___svfprintf_internal_r+0x19cc>
+ 8044d3c:	d9000517 	ldw	r4,20(sp)
+ 8044d40:	d9801c04 	addi	r6,sp,112
+ 8044d44:	980b883a 	mov	r5,r19
+ 8044d48:	80456900 	call	8045690 <__ssprint_r>
+ 8044d4c:	103a3b1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8044d50:	d8c01e17 	ldw	r3,120(sp)
+ 8044d54:	d8801d17 	ldw	r2,116(sp)
+ 8044d58:	b811883a 	mov	r8,r23
+ 8044d5c:	003fec06 	br	8044d10 <___svfprintf_internal_r+0x19d0>
+ 8044d60:	8819883a 	mov	r12,r17
+ 8044d64:	dc400717 	ldw	r17,28(sp)
+ 8044d68:	10800044 	addi	r2,r2,1
+ 8044d6c:	1c07883a 	add	r3,r3,r16
+ 8044d70:	d8801d15 	stw	r2,116(sp)
+ 8044d74:	43000015 	stw	r12,0(r8)
+ 8044d78:	44000115 	stw	r16,4(r8)
+ 8044d7c:	d8c01e15 	stw	r3,120(sp)
+ 8044d80:	10800208 	cmpgei	r2,r2,8
+ 8044d84:	103b1d26 	beq	r2,zero,80439fc <___svfprintf_internal_r+0x6bc>
+ 8044d88:	003d8e06 	br	80443c4 <___svfprintf_internal_r+0x1084>
+ 8044d8c:	8817883a 	mov	r11,r17
+ 8044d90:	9019883a 	mov	r12,r18
+ 8044d94:	dc400e17 	ldw	r17,56(sp)
+ 8044d98:	dc800717 	ldw	r18,28(sp)
+ 8044d9c:	af000044 	addi	fp,r21,1
+ 8044da0:	50800204 	addi	r2,r10,8
+ 8044da4:	1ac7883a 	add	r3,r3,r11
+ 8044da8:	53000015 	stw	r12,0(r10)
+ 8044dac:	52c00115 	stw	r11,4(r10)
+ 8044db0:	d8c01e15 	stw	r3,120(sp)
+ 8044db4:	df001d15 	stw	fp,116(sp)
+ 8044db8:	e1000208 	cmpgei	r4,fp,8
+ 8044dbc:	203f4e1e 	bne	r4,zero,8044af8 <___svfprintf_internal_r+0x17b8>
+ 8044dc0:	e7000044 	addi	fp,fp,1
+ 8044dc4:	12000204 	addi	r8,r2,8
+ 8044dc8:	1015883a 	mov	r10,r2
+ 8044dcc:	003d7406 	br	80443a0 <___svfprintf_internal_r+0x1060>
+ 8044dd0:	d8801a04 	addi	r2,sp,104
+ 8044dd4:	d8800315 	stw	r2,12(sp)
+ 8044dd8:	d9400917 	ldw	r5,36(sp)
+ 8044ddc:	d8801704 	addi	r2,sp,92
+ 8044de0:	d9000517 	ldw	r4,20(sp)
+ 8044de4:	d8800215 	stw	r2,8(sp)
+ 8044de8:	d8801604 	addi	r2,sp,88
+ 8044dec:	dac00015 	stw	r11,0(sp)
+ 8044df0:	d8800115 	stw	r2,4(sp)
+ 8044df4:	01c000c4 	movi	r7,3
+ 8044df8:	a00d883a 	mov	r6,r20
+ 8044dfc:	da001215 	stw	r8,72(sp)
+ 8044e00:	db001015 	stw	r12,64(sp)
+ 8044e04:	dac00815 	stw	r11,32(sp)
+ 8044e08:	80053ec0 	call	80053ec <_dtoa_r>
+ 8044e0c:	dac00817 	ldw	r11,32(sp)
+ 8044e10:	1021883a 	mov	r16,r2
+ 8044e14:	db001017 	ldw	r12,64(sp)
+ 8044e18:	12eb883a 	add	r21,r2,r11
+ 8044e1c:	80800007 	ldb	r2,0(r16)
+ 8044e20:	da001217 	ldw	r8,72(sp)
+ 8044e24:	10800c20 	cmpeqi	r2,r2,48
+ 8044e28:	10013e1e 	bne	r2,zero,8045324 <___svfprintf_internal_r+0x1fe4>
+ 8044e2c:	d8801617 	ldw	r2,88(sp)
+ 8044e30:	a8ab883a 	add	r21,r21,r2
+ 8044e34:	d9000917 	ldw	r4,36(sp)
+ 8044e38:	000d883a 	mov	r6,zero
+ 8044e3c:	000f883a 	mov	r7,zero
+ 8044e40:	a00b883a 	mov	r5,r20
+ 8044e44:	da001215 	stw	r8,72(sp)
+ 8044e48:	dac01015 	stw	r11,64(sp)
+ 8044e4c:	db000815 	stw	r12,32(sp)
+ 8044e50:	800e3000 	call	800e300 <__eqdf2>
+ 8044e54:	db000817 	ldw	r12,32(sp)
+ 8044e58:	dac01017 	ldw	r11,64(sp)
+ 8044e5c:	da001217 	ldw	r8,72(sp)
+ 8044e60:	10009c26 	beq	r2,zero,80450d4 <___svfprintf_internal_r+0x1d94>
+ 8044e64:	d8801a17 	ldw	r2,104(sp)
+ 8044e68:	01000c04 	movi	r4,48
+ 8044e6c:	1540052e 	bgeu	r2,r21,8044e84 <___svfprintf_internal_r+0x1b44>
+ 8044e70:	10c00044 	addi	r3,r2,1
+ 8044e74:	d8c01a15 	stw	r3,104(sp)
+ 8044e78:	11000005 	stb	r4,0(r2)
+ 8044e7c:	d8801a17 	ldw	r2,104(sp)
+ 8044e80:	157ffb36 	bltu	r2,r21,8044e70 <___svfprintf_internal_r+0x1b30>
+ 8044e84:	1405c83a 	sub	r2,r2,r16
+ 8044e88:	d8c00717 	ldw	r3,28(sp)
+ 8044e8c:	d8800815 	stw	r2,32(sp)
+ 8044e90:	d8801617 	ldw	r2,88(sp)
+ 8044e94:	18c011d8 	cmpnei	r3,r3,71
+ 8044e98:	d8800715 	stw	r2,28(sp)
+ 8044e9c:	183e9e26 	beq	r3,zero,8044918 <___svfprintf_internal_r+0x15d8>
+ 8044ea0:	d8800f17 	ldw	r2,60(sp)
+ 8044ea4:	10000d26 	beq	r2,zero,8044edc <___svfprintf_internal_r+0x1b9c>
+ 8044ea8:	d8c00717 	ldw	r3,28(sp)
+ 8044eac:	6080004c 	andi	r2,r12,1
+ 8044eb0:	12c4b03a 	or	r2,r2,r11
+ 8044eb4:	00c0bb0e 	bge	zero,r3,80451a4 <___svfprintf_internal_r+0x1e64>
+ 8044eb8:	1001381e 	bne	r2,zero,804539c <___svfprintf_internal_r+0x205c>
+ 8044ebc:	dd400717 	ldw	r21,28(sp)
+ 8044ec0:	a829883a 	mov	r20,r21
+ 8044ec4:	003ea206 	br	8044950 <___svfprintf_internal_r+0x1610>
+ 8044ec8:	d8800615 	stw	r2,24(sp)
+ 8044ecc:	002b883a 	mov	r21,zero
+ 8044ed0:	00800044 	movi	r2,1
+ 8044ed4:	003b4106 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8044ed8:	e73fff84 	addi	fp,fp,-2
+ 8044edc:	d8800717 	ldw	r2,28(sp)
+ 8044ee0:	df001845 	stb	fp,97(sp)
+ 8044ee4:	157fffc4 	addi	r21,r2,-1
+ 8044ee8:	dd401615 	stw	r21,88(sp)
+ 8044eec:	a8009216 	blt	r21,zero,8045138 <___svfprintf_internal_r+0x1df8>
+ 8044ef0:	00800ac4 	movi	r2,43
+ 8044ef4:	d8801885 	stb	r2,98(sp)
+ 8044ef8:	a8800290 	cmplti	r2,r21,10
+ 8044efc:	1001191e 	bne	r2,zero,8045364 <___svfprintf_internal_r+0x2024>
+ 8044f00:	dc000715 	stw	r16,28(sp)
+ 8044f04:	dd001bc4 	addi	r20,sp,111
+ 8044f08:	a821883a 	mov	r16,r21
+ 8044f0c:	db000f15 	stw	r12,60(sp)
+ 8044f10:	982b883a 	mov	r21,r19
+ 8044f14:	4027883a 	mov	r19,r8
+ 8044f18:	00000206 	br	8044f24 <___svfprintf_internal_r+0x1be4>
+ 8044f1c:	2029883a 	mov	r20,r4
+ 8044f20:	1021883a 	mov	r16,r2
+ 8044f24:	8009883a 	mov	r4,r16
+ 8044f28:	01400284 	movi	r5,10
+ 8044f2c:	800cf800 	call	800cf80 <__modsi3>
+ 8044f30:	10800c04 	addi	r2,r2,48
+ 8044f34:	8009883a 	mov	r4,r16
+ 8044f38:	a0bfffc5 	stb	r2,-1(r20)
+ 8044f3c:	01400284 	movi	r5,10
+ 8044f40:	800cf000 	call	800cf00 <__divsi3>
+ 8044f44:	80c01908 	cmpgei	r3,r16,100
+ 8044f48:	a13fffc4 	addi	r4,r20,-1
+ 8044f4c:	183ff31e 	bne	r3,zero,8044f1c <___svfprintf_internal_r+0x1bdc>
+ 8044f50:	10800c04 	addi	r2,r2,48
+ 8044f54:	20bfffc5 	stb	r2,-1(r4)
+ 8044f58:	a0ffff84 	addi	r3,r20,-2
+ 8044f5c:	d9001bc4 	addi	r4,sp,111
+ 8044f60:	9811883a 	mov	r8,r19
+ 8044f64:	dc000717 	ldw	r16,28(sp)
+ 8044f68:	db000f17 	ldw	r12,60(sp)
+ 8044f6c:	a827883a 	mov	r19,r21
+ 8044f70:	1901242e 	bgeu	r3,r4,8045404 <___svfprintf_internal_r+0x20c4>
+ 8044f74:	d90018c4 	addi	r4,sp,99
+ 8044f78:	00000106 	br	8044f80 <___svfprintf_internal_r+0x1c40>
+ 8044f7c:	18800003 	ldbu	r2,0(r3)
+ 8044f80:	21000044 	addi	r4,r4,1
+ 8044f84:	20bfffc5 	stb	r2,-1(r4)
+ 8044f88:	18c00044 	addi	r3,r3,1
+ 8044f8c:	d8801bc4 	addi	r2,sp,111
+ 8044f90:	18bffa1e 	bne	r3,r2,8044f7c <___svfprintf_internal_r+0x1c3c>
+ 8044f94:	d8801c44 	addi	r2,sp,113
+ 8044f98:	d8c018c4 	addi	r3,sp,99
+ 8044f9c:	1505c83a 	sub	r2,r2,r20
+ 8044fa0:	1885883a 	add	r2,r3,r2
+ 8044fa4:	d8c01844 	addi	r3,sp,97
+ 8044fa8:	10c5c83a 	sub	r2,r2,r3
+ 8044fac:	d8801115 	stw	r2,68(sp)
+ 8044fb0:	d8c00817 	ldw	r3,32(sp)
+ 8044fb4:	d9001117 	ldw	r4,68(sp)
+ 8044fb8:	18800088 	cmpgei	r2,r3,2
+ 8044fbc:	192b883a 	add	r21,r3,r4
+ 8044fc0:	1000ef26 	beq	r2,zero,8045380 <___svfprintf_internal_r+0x2040>
+ 8044fc4:	d8800b17 	ldw	r2,44(sp)
+ 8044fc8:	a8ab883a 	add	r21,r21,r2
+ 8044fcc:	a829883a 	mov	r20,r21
+ 8044fd0:	a800010e 	bge	r21,zero,8044fd8 <___svfprintf_internal_r+0x1c98>
+ 8044fd4:	0029883a 	mov	r20,zero
+ 8044fd8:	d8000715 	stw	zero,28(sp)
+ 8044fdc:	003e5c06 	br	8044950 <___svfprintf_internal_r+0x1610>
+ 8044fe0:	04020134 	movhi	r16,2052
+ 8044fe4:	841d1704 	addi	r16,r16,29788
+ 8044fe8:	003b4a06 	br	8043d14 <___svfprintf_internal_r+0x9d4>
+ 8044fec:	d8800615 	stw	r2,24(sp)
+ 8044ff0:	002b883a 	mov	r21,zero
+ 8044ff4:	0005883a 	mov	r2,zero
+ 8044ff8:	003af806 	br	8043bdc <___svfprintf_internal_r+0x89c>
+ 8044ffc:	9019883a 	mov	r12,r18
+ 8045000:	dc000f17 	ldw	r16,60(sp)
+ 8045004:	dc800e17 	ldw	r18,56(sp)
+ 8045008:	e009883a 	mov	r4,fp
+ 804500c:	8839883a 	mov	fp,r17
+ 8045010:	b023883a 	mov	r17,r22
+ 8045014:	202d883a 	mov	r22,r4
+ 8045018:	10800044 	addi	r2,r2,1
+ 804501c:	1f07883a 	add	r3,r3,fp
+ 8045020:	d8801d15 	stw	r2,116(sp)
+ 8045024:	43000015 	stw	r12,0(r8)
+ 8045028:	47000115 	stw	fp,4(r8)
+ 804502c:	d8c01e15 	stw	r3,120(sp)
+ 8045030:	10800208 	cmpgei	r2,r2,8
+ 8045034:	1000381e 	bne	r2,zero,8045118 <___svfprintf_internal_r+0x1dd8>
+ 8045038:	42000204 	addi	r8,r8,8
+ 804503c:	003d6406 	br	80445d0 <___svfprintf_internal_r+0x1290>
+ 8045040:	8819883a 	mov	r12,r17
+ 8045044:	dc400717 	ldw	r17,28(sp)
+ 8045048:	10800044 	addi	r2,r2,1
+ 804504c:	1f07883a 	add	r3,r3,fp
+ 8045050:	d8801d15 	stw	r2,116(sp)
+ 8045054:	43000015 	stw	r12,0(r8)
+ 8045058:	47000115 	stw	fp,4(r8)
+ 804505c:	d8c01e15 	stw	r3,120(sp)
+ 8045060:	10800208 	cmpgei	r2,r2,8
+ 8045064:	103a6526 	beq	r2,zero,80439fc <___svfprintf_internal_r+0x6bc>
+ 8045068:	003cd606 	br	80443c4 <___svfprintf_internal_r+0x1084>
+ 804506c:	00800b44 	movi	r2,45
+ 8045070:	d8801545 	stb	r2,85(sp)
+ 8045074:	03400b44 	movi	r13,45
+ 8045078:	003b2206 	br	8043d04 <___svfprintf_internal_r+0x9c4>
+ 804507c:	d9000517 	ldw	r4,20(sp)
+ 8045080:	d9801c04 	addi	r6,sp,112
+ 8045084:	980b883a 	mov	r5,r19
+ 8045088:	80456900 	call	8045690 <__ssprint_r>
+ 804508c:	10396b1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8045090:	d9001617 	ldw	r4,88(sp)
+ 8045094:	d8c01e17 	ldw	r3,120(sp)
+ 8045098:	b811883a 	mov	r8,r23
+ 804509c:	003eae06 	br	8044b58 <___svfprintf_internal_r+0x1818>
+ 80450a0:	d9000517 	ldw	r4,20(sp)
+ 80450a4:	d9801c04 	addi	r6,sp,112
+ 80450a8:	980b883a 	mov	r5,r19
+ 80450ac:	80456900 	call	8045690 <__ssprint_r>
+ 80450b0:	1039621e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80450b4:	d9001617 	ldw	r4,88(sp)
+ 80450b8:	d8c01e17 	ldw	r3,120(sp)
+ 80450bc:	b811883a 	mov	r8,r23
+ 80450c0:	003d5206 	br	804460c <___svfprintf_internal_r+0x12cc>
+ 80450c4:	1520003c 	xorhi	r20,r2,32768
+ 80450c8:	00800b44 	movi	r2,45
+ 80450cc:	d8800e05 	stb	r2,56(sp)
+ 80450d0:	003de906 	br	8044878 <___svfprintf_internal_r+0x1538>
+ 80450d4:	a805883a 	mov	r2,r21
+ 80450d8:	003f6a06 	br	8044e84 <___svfprintf_internal_r+0x1b44>
+ 80450dc:	05400184 	movi	r21,6
+ 80450e0:	003eed06 	br	8044c98 <___svfprintf_internal_r+0x1958>
+ 80450e4:	d9401545 	stb	r5,85(sp)
+ 80450e8:	00397206 	br	80436b4 <___svfprintf_internal_r+0x374>
+ 80450ec:	d9000517 	ldw	r4,20(sp)
+ 80450f0:	d9801c04 	addi	r6,sp,112
+ 80450f4:	980b883a 	mov	r5,r19
+ 80450f8:	80456900 	call	8045690 <__ssprint_r>
+ 80450fc:	10394f1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8045100:	d9001617 	ldw	r4,88(sp)
+ 8045104:	d8c01e17 	ldw	r3,120(sp)
+ 8045108:	d8801d17 	ldw	r2,116(sp)
+ 804510c:	b811883a 	mov	r8,r23
+ 8045110:	203ea20e 	bge	r4,zero,8044b9c <___svfprintf_internal_r+0x185c>
+ 8045114:	003ef206 	br	8044ce0 <___svfprintf_internal_r+0x19a0>
+ 8045118:	d9000517 	ldw	r4,20(sp)
+ 804511c:	d9801c04 	addi	r6,sp,112
+ 8045120:	980b883a 	mov	r5,r19
+ 8045124:	80456900 	call	8045690 <__ssprint_r>
+ 8045128:	1039441e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 804512c:	d8c01e17 	ldw	r3,120(sp)
+ 8045130:	b811883a 	mov	r8,r23
+ 8045134:	003d2606 	br	80445d0 <___svfprintf_internal_r+0x1290>
+ 8045138:	00c00044 	movi	r3,1
+ 804513c:	18abc83a 	sub	r21,r3,r2
+ 8045140:	00800b44 	movi	r2,45
+ 8045144:	d8801885 	stb	r2,98(sp)
+ 8045148:	003f6b06 	br	8044ef8 <___svfprintf_internal_r+0x1bb8>
+ 804514c:	d8801a04 	addi	r2,sp,104
+ 8045150:	d8800315 	stw	r2,12(sp)
+ 8045154:	d9400917 	ldw	r5,36(sp)
+ 8045158:	d8801704 	addi	r2,sp,92
+ 804515c:	d9000517 	ldw	r4,20(sp)
+ 8045160:	5d400044 	addi	r21,r11,1
+ 8045164:	d8800215 	stw	r2,8(sp)
+ 8045168:	d8801604 	addi	r2,sp,88
+ 804516c:	d8800115 	stw	r2,4(sp)
+ 8045170:	dd400015 	stw	r21,0(sp)
+ 8045174:	01c00084 	movi	r7,2
+ 8045178:	a00d883a 	mov	r6,r20
+ 804517c:	dac00815 	stw	r11,32(sp)
+ 8045180:	80053ec0 	call	80053ec <_dtoa_r>
+ 8045184:	dac00817 	ldw	r11,32(sp)
+ 8045188:	db001017 	ldw	r12,64(sp)
+ 804518c:	da001217 	ldw	r8,72(sp)
+ 8045190:	1021883a 	mov	r16,r2
+ 8045194:	e08011d8 	cmpnei	r2,fp,71
+ 8045198:	103dd526 	beq	r2,zero,80448f0 <___svfprintf_internal_r+0x15b0>
+ 804519c:	856b883a 	add	r21,r16,r21
+ 80451a0:	003f2406 	br	8044e34 <___svfprintf_internal_r+0x1af4>
+ 80451a4:	1000891e 	bne	r2,zero,80453cc <___svfprintf_internal_r+0x208c>
+ 80451a8:	05000044 	movi	r20,1
+ 80451ac:	05400044 	movi	r21,1
+ 80451b0:	003de706 	br	8044950 <___svfprintf_internal_r+0x1610>
+ 80451b4:	db401543 	ldbu	r13,85(sp)
+ 80451b8:	0017883a 	mov	r11,zero
+ 80451bc:	003b5506 	br	8043f14 <___svfprintf_internal_r+0xbd4>
+ 80451c0:	d9000517 	ldw	r4,20(sp)
+ 80451c4:	d9801c04 	addi	r6,sp,112
+ 80451c8:	980b883a 	mov	r5,r19
+ 80451cc:	80456900 	call	8045690 <__ssprint_r>
+ 80451d0:	10391a1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80451d4:	d8c01e17 	ldw	r3,120(sp)
+ 80451d8:	b811883a 	mov	r8,r23
+ 80451dc:	e03cf90e 	bge	fp,zero,80445c4 <___svfprintf_internal_r+0x1284>
+ 80451e0:	003dfe06 	br	80449dc <___svfprintf_internal_r+0x169c>
+ 80451e4:	02c00184 	movi	r11,6
+ 80451e8:	003d9e06 	br	8044864 <___svfprintf_internal_r+0x1524>
+ 80451ec:	d9000517 	ldw	r4,20(sp)
+ 80451f0:	d9801c04 	addi	r6,sp,112
+ 80451f4:	980b883a 	mov	r5,r19
+ 80451f8:	80456900 	call	8045690 <__ssprint_r>
+ 80451fc:	10390f1e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 8045200:	d8801617 	ldw	r2,88(sp)
+ 8045204:	d9000817 	ldw	r4,32(sp)
+ 8045208:	d8c01e17 	ldw	r3,120(sp)
+ 804520c:	b811883a 	mov	r8,r23
+ 8045210:	2085c83a 	sub	r2,r4,r2
+ 8045214:	003d0f06 	br	8044654 <___svfprintf_internal_r+0x1314>
+ 8045218:	5829883a 	mov	r20,r11
+ 804521c:	dc800615 	stw	r18,24(sp)
+ 8045220:	582b883a 	mov	r21,r11
+ 8045224:	0039c006 	br	8043928 <___svfprintf_internal_r+0x5e8>
+ 8045228:	d8800817 	ldw	r2,32(sp)
+ 804522c:	d8c00b17 	ldw	r3,44(sp)
+ 8045230:	10eb883a 	add	r21,r2,r3
+ 8045234:	d8800717 	ldw	r2,28(sp)
+ 8045238:	00800316 	blt	zero,r2,8045248 <___svfprintf_internal_r+0x1f08>
+ 804523c:	d8800717 	ldw	r2,28(sp)
+ 8045240:	a8b9c83a 	sub	fp,r21,r2
+ 8045244:	e5400044 	addi	r21,fp,1
+ 8045248:	a829883a 	mov	r20,r21
+ 804524c:	a8003316 	blt	r21,zero,804531c <___svfprintf_internal_r+0x1fdc>
+ 8045250:	070019c4 	movi	fp,103
+ 8045254:	003dbe06 	br	8044950 <___svfprintf_internal_r+0x1610>
+ 8045258:	d9401545 	stb	r5,85(sp)
+ 804525c:	003aec06 	br	8043e10 <___svfprintf_internal_r+0xad0>
+ 8045260:	d9401545 	stb	r5,85(sp)
+ 8045264:	00396406 	br	80437f8 <___svfprintf_internal_r+0x4b8>
+ 8045268:	d9401545 	stb	r5,85(sp)
+ 804526c:	003ab206 	br	8043d38 <___svfprintf_internal_r+0x9f8>
+ 8045270:	d9401545 	stb	r5,85(sp)
+ 8045274:	00394e06 	br	80437b0 <___svfprintf_internal_r+0x470>
+ 8045278:	d9401545 	stb	r5,85(sp)
+ 804527c:	003a6906 	br	8043c24 <___svfprintf_internal_r+0x8e4>
+ 8045280:	d9401545 	stb	r5,85(sp)
+ 8045284:	003a1d06 	br	8043afc <___svfprintf_internal_r+0x7bc>
+ 8045288:	d9401545 	stb	r5,85(sp)
+ 804528c:	00398206 	br	8043898 <___svfprintf_internal_r+0x558>
+ 8045290:	d9401545 	stb	r5,85(sp)
+ 8045294:	003a7006 	br	8043c58 <___svfprintf_internal_r+0x918>
+ 8045298:	d9401545 	stb	r5,85(sp)
+ 804529c:	003a2706 	br	8043b3c <___svfprintf_internal_r+0x7fc>
+ 80452a0:	d9401545 	stb	r5,85(sp)
+ 80452a4:	003aec06 	br	8043e58 <___svfprintf_internal_r+0xb18>
+ 80452a8:	8819883a 	mov	r12,r17
+ 80452ac:	a823883a 	mov	r17,r21
+ 80452b0:	802b883a 	mov	r21,r16
+ 80452b4:	dc000717 	ldw	r16,28(sp)
+ 80452b8:	10800044 	addi	r2,r2,1
+ 80452bc:	1d47883a 	add	r3,r3,r21
+ 80452c0:	43000015 	stw	r12,0(r8)
+ 80452c4:	45400115 	stw	r21,4(r8)
+ 80452c8:	d8c01e15 	stw	r3,120(sp)
+ 80452cc:	d8801d15 	stw	r2,116(sp)
+ 80452d0:	11000208 	cmpgei	r4,r2,8
+ 80452d4:	203e3026 	beq	r4,zero,8044b98 <___svfprintf_internal_r+0x1858>
+ 80452d8:	d9000517 	ldw	r4,20(sp)
+ 80452dc:	d9801c04 	addi	r6,sp,112
+ 80452e0:	980b883a 	mov	r5,r19
+ 80452e4:	80456900 	call	8045690 <__ssprint_r>
+ 80452e8:	1038d41e 	bne	r2,zero,804363c <___svfprintf_internal_r+0x2fc>
+ 80452ec:	d8c01e17 	ldw	r3,120(sp)
+ 80452f0:	d8801d17 	ldw	r2,116(sp)
+ 80452f4:	b811883a 	mov	r8,r23
+ 80452f8:	003e2806 	br	8044b9c <___svfprintf_internal_r+0x185c>
+ 80452fc:	00bfffc4 	movi	r2,-1
+ 8045300:	d8800415 	stw	r2,16(sp)
+ 8045304:	0038d006 	br	8043648 <___svfprintf_internal_r+0x308>
+ 8045308:	d8800717 	ldw	r2,28(sp)
+ 804530c:	d8c00b17 	ldw	r3,44(sp)
+ 8045310:	10eb883a 	add	r21,r2,r3
+ 8045314:	a829883a 	mov	r20,r21
+ 8045318:	a83fcd0e 	bge	r21,zero,8045250 <___svfprintf_internal_r+0x1f10>
+ 804531c:	0029883a 	mov	r20,zero
+ 8045320:	003fcb06 	br	8045250 <___svfprintf_internal_r+0x1f10>
+ 8045324:	d9000917 	ldw	r4,36(sp)
+ 8045328:	000d883a 	mov	r6,zero
+ 804532c:	000f883a 	mov	r7,zero
+ 8045330:	a00b883a 	mov	r5,r20
+ 8045334:	da001215 	stw	r8,72(sp)
+ 8045338:	dac01015 	stw	r11,64(sp)
+ 804533c:	db000815 	stw	r12,32(sp)
+ 8045340:	800e3000 	call	800e300 <__eqdf2>
+ 8045344:	db000817 	ldw	r12,32(sp)
+ 8045348:	dac01017 	ldw	r11,64(sp)
+ 804534c:	da001217 	ldw	r8,72(sp)
+ 8045350:	103eb626 	beq	r2,zero,8044e2c <___svfprintf_internal_r+0x1aec>
+ 8045354:	00800044 	movi	r2,1
+ 8045358:	12c5c83a 	sub	r2,r2,r11
+ 804535c:	d8801615 	stw	r2,88(sp)
+ 8045360:	003eb306 	br	8044e30 <___svfprintf_internal_r+0x1af0>
+ 8045364:	00800c04 	movi	r2,48
+ 8045368:	a8c00c04 	addi	r3,r21,48
+ 804536c:	d88018c5 	stb	r2,99(sp)
+ 8045370:	00800104 	movi	r2,4
+ 8045374:	d8c01905 	stb	r3,100(sp)
+ 8045378:	d8801115 	stw	r2,68(sp)
+ 804537c:	003f0c06 	br	8044fb0 <___svfprintf_internal_r+0x1c70>
+ 8045380:	6080004c 	andi	r2,r12,1
+ 8045384:	d8800715 	stw	r2,28(sp)
+ 8045388:	103f0e1e 	bne	r2,zero,8044fc4 <___svfprintf_internal_r+0x1c84>
+ 804538c:	a829883a 	mov	r20,r21
+ 8045390:	a83d6f0e 	bge	r21,zero,8044950 <___svfprintf_internal_r+0x1610>
+ 8045394:	0029883a 	mov	r20,zero
+ 8045398:	003d6d06 	br	8044950 <___svfprintf_internal_r+0x1610>
+ 804539c:	d8800b17 	ldw	r2,44(sp)
+ 80453a0:	1885883a 	add	r2,r3,r2
+ 80453a4:	12eb883a 	add	r21,r2,r11
+ 80453a8:	003ff806 	br	804538c <___svfprintf_internal_r+0x204c>
+ 80453ac:	d8800a17 	ldw	r2,40(sp)
+ 80453b0:	10001016 	blt	r2,zero,80453f4 <___svfprintf_internal_r+0x20b4>
+ 80453b4:	db401543 	ldbu	r13,85(sp)
+ 80453b8:	e0801210 	cmplti	r2,fp,72
+ 80453bc:	10000a1e 	bne	r2,zero,80453e8 <___svfprintf_internal_r+0x20a8>
+ 80453c0:	04020134 	movhi	r16,2052
+ 80453c4:	841d1a04 	addi	r16,r16,29800
+ 80453c8:	003a5206 	br	8043d14 <___svfprintf_internal_r+0x9d4>
+ 80453cc:	d8800b17 	ldw	r2,44(sp)
+ 80453d0:	10800044 	addi	r2,r2,1
+ 80453d4:	12eb883a 	add	r21,r2,r11
+ 80453d8:	003fec06 	br	804538c <___svfprintf_internal_r+0x204c>
+ 80453dc:	4005883a 	mov	r2,r8
+ 80453e0:	632e3444 	addi	r12,r12,-18223
+ 80453e4:	003e6f06 	br	8044da4 <___svfprintf_internal_r+0x1a64>
+ 80453e8:	04020134 	movhi	r16,2052
+ 80453ec:	841d1904 	addi	r16,r16,29796
+ 80453f0:	003a4806 	br	8043d14 <___svfprintf_internal_r+0x9d4>
+ 80453f4:	00800b44 	movi	r2,45
+ 80453f8:	d8801545 	stb	r2,85(sp)
+ 80453fc:	03400b44 	movi	r13,45
+ 8045400:	003fed06 	br	80453b8 <___svfprintf_internal_r+0x2078>
+ 8045404:	00800084 	movi	r2,2
+ 8045408:	d8801115 	stw	r2,68(sp)
+ 804540c:	003ee806 	br	8044fb0 <___svfprintf_internal_r+0x1c70>
+ 8045410:	d8800617 	ldw	r2,24(sp)
+ 8045414:	12c00017 	ldw	r11,0(r2)
+ 8045418:	10800104 	addi	r2,r2,4
+ 804541c:	5800010e 	bge	r11,zero,8045424 <___svfprintf_internal_r+0x20e4>
+ 8045420:	02ffffc4 	movi	r11,-1
+ 8045424:	b7000043 	ldbu	fp,1(r22)
+ 8045428:	d8800615 	stw	r2,24(sp)
+ 804542c:	182d883a 	mov	r22,r3
+ 8045430:	e2803fcc 	andi	r10,fp,255
+ 8045434:	5280201c 	xori	r10,r10,128
+ 8045438:	52bfe004 	addi	r10,r10,-128
+ 804543c:	00380c06 	br	8043470 <___svfprintf_internal_r+0x130>
+ 8045440:	d8c00517 	ldw	r3,20(sp)
+ 8045444:	00800304 	movi	r2,12
+ 8045448:	18800015 	stw	r2,0(r3)
+ 804544c:	00bfffc4 	movi	r2,-1
+ 8045450:	d8800415 	stw	r2,16(sp)
+ 8045454:	00387c06 	br	8043648 <___svfprintf_internal_r+0x308>
+
+08045458 <vprintf>:
+ 8045458:	00820174 	movhi	r2,2053
+ 804545c:	10b2af17 	ldw	r2,-13636(r2)
+ 8045460:	280f883a 	mov	r7,r5
+ 8045464:	200d883a 	mov	r6,r4
+ 8045468:	11400217 	ldw	r5,8(r2)
+ 804546c:	1009883a 	mov	r4,r2
+ 8045470:	80469701 	jmpi	8046970 <_vfprintf_r>
+
+08045474 <_vprintf_r>:
+ 8045474:	300f883a 	mov	r7,r6
+ 8045478:	280d883a 	mov	r6,r5
+ 804547c:	21400217 	ldw	r5,8(r4)
+ 8045480:	80469701 	jmpi	8046970 <_vfprintf_r>
+
+08045484 <_vsprintf_r>:
+ 8045484:	deffe504 	addi	sp,sp,-108
+ 8045488:	00a00034 	movhi	r2,32768
+ 804548c:	00fffff4 	movhi	r3,65535
+ 8045490:	2811883a 	mov	r8,r5
+ 8045494:	10bfffc4 	addi	r2,r2,-1
+ 8045498:	18c08204 	addi	r3,r3,520
+ 804549c:	d80b883a 	mov	r5,sp
+ 80454a0:	dfc01a15 	stw	ra,104(sp)
+ 80454a4:	d8c00315 	stw	r3,12(sp)
+ 80454a8:	da000015 	stw	r8,0(sp)
+ 80454ac:	da000415 	stw	r8,16(sp)
+ 80454b0:	d8800515 	stw	r2,20(sp)
+ 80454b4:	d8800215 	stw	r2,8(sp)
+ 80454b8:	80433400 	call	8043340 <___svfprintf_internal_r>
+ 80454bc:	d8c00017 	ldw	r3,0(sp)
+ 80454c0:	18000005 	stb	zero,0(r3)
+ 80454c4:	dfc01a17 	ldw	ra,104(sp)
+ 80454c8:	dec01b04 	addi	sp,sp,108
+ 80454cc:	f800283a 	ret
+
+080454d0 <vsprintf>:
+ 80454d0:	00820174 	movhi	r2,2053
+ 80454d4:	300f883a 	mov	r7,r6
+ 80454d8:	280d883a 	mov	r6,r5
+ 80454dc:	200b883a 	mov	r5,r4
+ 80454e0:	1132af17 	ldw	r4,-13636(r2)
+ 80454e4:	80454841 	jmpi	8045484 <_vsprintf_r>
+
+080454e8 <__register_exitproc>:
+ 80454e8:	00820174 	movhi	r2,2053
+ 80454ec:	10f2ae17 	ldw	r3,-13640(r2)
+ 80454f0:	18805217 	ldw	r2,328(r3)
+ 80454f4:	10001726 	beq	r2,zero,8045554 <__register_exitproc+0x6c>
+ 80454f8:	10c00117 	ldw	r3,4(r2)
+ 80454fc:	1a000808 	cmpgei	r8,r3,32
+ 8045500:	40001b1e 	bne	r8,zero,8045570 <__register_exitproc+0x88>
+ 8045504:	20000b26 	beq	r4,zero,8045534 <__register_exitproc+0x4c>
+ 8045508:	181090ba 	slli	r8,r3,2
+ 804550c:	02400044 	movi	r9,1
+ 8045510:	48d2983a 	sll	r9,r9,r3
+ 8045514:	1211883a 	add	r8,r2,r8
+ 8045518:	41802215 	stw	r6,136(r8)
+ 804551c:	11806217 	ldw	r6,392(r2)
+ 8045520:	21000098 	cmpnei	r4,r4,2
+ 8045524:	324cb03a 	or	r6,r6,r9
+ 8045528:	11806215 	stw	r6,392(r2)
+ 804552c:	41c04215 	stw	r7,264(r8)
+ 8045530:	20000b26 	beq	r4,zero,8045560 <__register_exitproc+0x78>
+ 8045534:	19000084 	addi	r4,r3,2
+ 8045538:	200890ba 	slli	r4,r4,2
+ 804553c:	18c00044 	addi	r3,r3,1
+ 8045540:	10c00115 	stw	r3,4(r2)
+ 8045544:	1105883a 	add	r2,r2,r4
+ 8045548:	11400015 	stw	r5,0(r2)
+ 804554c:	0005883a 	mov	r2,zero
+ 8045550:	f800283a 	ret
+ 8045554:	18805304 	addi	r2,r3,332
+ 8045558:	18805215 	stw	r2,328(r3)
+ 804555c:	003fe606 	br	80454f8 <__register_exitproc+0x10>
+ 8045560:	11006317 	ldw	r4,396(r2)
+ 8045564:	2252b03a 	or	r9,r4,r9
+ 8045568:	12406315 	stw	r9,396(r2)
+ 804556c:	003ff106 	br	8045534 <__register_exitproc+0x4c>
+ 8045570:	00bfffc4 	movi	r2,-1
+ 8045574:	f800283a 	ret
+
+08045578 <__call_exitprocs>:
+ 8045578:	defff704 	addi	sp,sp,-36
+ 804557c:	00820174 	movhi	r2,2053
+ 8045580:	ddc00715 	stw	r23,28(sp)
+ 8045584:	15f2ae17 	ldw	r23,-13640(r2)
+ 8045588:	dd400515 	stw	r21,20(sp)
+ 804558c:	dd000415 	stw	r20,16(sp)
+ 8045590:	dcc00315 	stw	r19,12(sp)
+ 8045594:	dfc00815 	stw	ra,32(sp)
+ 8045598:	dd800615 	stw	r22,24(sp)
+ 804559c:	dc800215 	stw	r18,8(sp)
+ 80455a0:	dc400115 	stw	r17,4(sp)
+ 80455a4:	dc000015 	stw	r16,0(sp)
+ 80455a8:	2029883a 	mov	r20,r4
+ 80455ac:	282b883a 	mov	r21,r5
+ 80455b0:	04c00044 	movi	r19,1
+ 80455b4:	bc805217 	ldw	r18,328(r23)
+ 80455b8:	90000d26 	beq	r18,zero,80455f0 <__call_exitprocs+0x78>
+ 80455bc:	94000117 	ldw	r16,4(r18)
+ 80455c0:	847fffc4 	addi	r17,r16,-1
+ 80455c4:	88000a16 	blt	r17,zero,80455f0 <__call_exitprocs+0x78>
+ 80455c8:	84000044 	addi	r16,r16,1
+ 80455cc:	802090ba 	slli	r16,r16,2
+ 80455d0:	9421883a 	add	r16,r18,r16
+ 80455d4:	a8001126 	beq	r21,zero,804561c <__call_exitprocs+0xa4>
+ 80455d8:	80804017 	ldw	r2,256(r16)
+ 80455dc:	15400f26 	beq	r2,r21,804561c <__call_exitprocs+0xa4>
+ 80455e0:	8c7fffc4 	addi	r17,r17,-1
+ 80455e4:	88bfffd8 	cmpnei	r2,r17,-1
+ 80455e8:	843fff04 	addi	r16,r16,-4
+ 80455ec:	103ff91e 	bne	r2,zero,80455d4 <__call_exitprocs+0x5c>
+ 80455f0:	dfc00817 	ldw	ra,32(sp)
+ 80455f4:	ddc00717 	ldw	r23,28(sp)
+ 80455f8:	dd800617 	ldw	r22,24(sp)
+ 80455fc:	dd400517 	ldw	r21,20(sp)
+ 8045600:	dd000417 	ldw	r20,16(sp)
+ 8045604:	dcc00317 	ldw	r19,12(sp)
+ 8045608:	dc800217 	ldw	r18,8(sp)
+ 804560c:	dc400117 	ldw	r17,4(sp)
+ 8045610:	dc000017 	ldw	r16,0(sp)
+ 8045614:	dec00904 	addi	sp,sp,36
+ 8045618:	f800283a 	ret
+ 804561c:	90800117 	ldw	r2,4(r18)
+ 8045620:	81800017 	ldw	r6,0(r16)
+ 8045624:	10bfffc4 	addi	r2,r2,-1
+ 8045628:	14401526 	beq	r2,r17,8045680 <__call_exitprocs+0x108>
+ 804562c:	80000015 	stw	zero,0(r16)
+ 8045630:	303feb26 	beq	r6,zero,80455e0 <__call_exitprocs+0x68>
+ 8045634:	9c46983a 	sll	r3,r19,r17
+ 8045638:	90806217 	ldw	r2,392(r18)
+ 804563c:	95800117 	ldw	r22,4(r18)
+ 8045640:	1884703a 	and	r2,r3,r2
+ 8045644:	1000061e 	bne	r2,zero,8045660 <__call_exitprocs+0xe8>
+ 8045648:	303ee83a 	callr	r6
+ 804564c:	90800117 	ldw	r2,4(r18)
+ 8045650:	15bfd81e 	bne	r2,r22,80455b4 <__call_exitprocs+0x3c>
+ 8045654:	b8805217 	ldw	r2,328(r23)
+ 8045658:	14bfe126 	beq	r2,r18,80455e0 <__call_exitprocs+0x68>
+ 804565c:	003fd506 	br	80455b4 <__call_exitprocs+0x3c>
+ 8045660:	90806317 	ldw	r2,396(r18)
+ 8045664:	81002017 	ldw	r4,128(r16)
+ 8045668:	1886703a 	and	r3,r3,r2
+ 804566c:	1800061e 	bne	r3,zero,8045688 <__call_exitprocs+0x110>
+ 8045670:	200b883a 	mov	r5,r4
+ 8045674:	a009883a 	mov	r4,r20
+ 8045678:	303ee83a 	callr	r6
+ 804567c:	003ff306 	br	804564c <__call_exitprocs+0xd4>
+ 8045680:	94400115 	stw	r17,4(r18)
+ 8045684:	003fea06 	br	8045630 <__call_exitprocs+0xb8>
+ 8045688:	303ee83a 	callr	r6
+ 804568c:	003fef06 	br	804564c <__call_exitprocs+0xd4>
+
+08045690 <__ssprint_r>:
+ 8045690:	30800217 	ldw	r2,8(r6)
+ 8045694:	defff604 	addi	sp,sp,-40
+ 8045698:	dcc00315 	stw	r19,12(sp)
+ 804569c:	dfc00915 	stw	ra,36(sp)
+ 80456a0:	df000815 	stw	fp,32(sp)
+ 80456a4:	ddc00715 	stw	r23,28(sp)
+ 80456a8:	dd800615 	stw	r22,24(sp)
+ 80456ac:	dd400515 	stw	r21,20(sp)
+ 80456b0:	dd000415 	stw	r20,16(sp)
+ 80456b4:	dc800215 	stw	r18,8(sp)
+ 80456b8:	dc400115 	stw	r17,4(sp)
+ 80456bc:	dc000015 	stw	r16,0(sp)
+ 80456c0:	3027883a 	mov	r19,r6
+ 80456c4:	10005426 	beq	r2,zero,8045818 <__ssprint_r+0x188>
+ 80456c8:	2029883a 	mov	r20,r4
+ 80456cc:	2821883a 	mov	r16,r5
+ 80456d0:	35800017 	ldw	r22,0(r6)
+ 80456d4:	29000017 	ldw	r4,0(r5)
+ 80456d8:	2c400217 	ldw	r17,8(r5)
+ 80456dc:	057edfc4 	movi	r21,-1153
+ 80456e0:	00003406 	br	80457b4 <__ssprint_r+0x124>
+ 80456e4:	8080030b 	ldhu	r2,12(r16)
+ 80456e8:	10c1200c 	andi	r3,r2,1152
+ 80456ec:	18002426 	beq	r3,zero,8045780 <__ssprint_r+0xf0>
+ 80456f0:	81800517 	ldw	r6,20(r16)
+ 80456f4:	81400417 	ldw	r5,16(r16)
+ 80456f8:	90c00044 	addi	r3,r18,1
+ 80456fc:	318000e4 	muli	r6,r6,3
+ 8045700:	216fc83a 	sub	r23,r4,r5
+ 8045704:	1dc7883a 	add	r3,r3,r23
+ 8045708:	3022d7fa 	srli	r17,r6,31
+ 804570c:	89a3883a 	add	r17,r17,r6
+ 8045710:	8823d07a 	srai	r17,r17,1
+ 8045714:	880d883a 	mov	r6,r17
+ 8045718:	88c0022e 	bgeu	r17,r3,8045724 <__ssprint_r+0x94>
+ 804571c:	1823883a 	mov	r17,r3
+ 8045720:	180d883a 	mov	r6,r3
+ 8045724:	1081000c 	andi	r2,r2,1024
+ 8045728:	10002b26 	beq	r2,zero,80457d8 <__ssprint_r+0x148>
+ 804572c:	300b883a 	mov	r5,r6
+ 8045730:	a009883a 	mov	r4,r20
+ 8045734:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8045738:	10002e26 	beq	r2,zero,80457f4 <__ssprint_r+0x164>
+ 804573c:	81400417 	ldw	r5,16(r16)
+ 8045740:	b80d883a 	mov	r6,r23
+ 8045744:	1009883a 	mov	r4,r2
+ 8045748:	80086b80 	call	80086b8 <memcpy>
+ 804574c:	1007883a 	mov	r3,r2
+ 8045750:	8080030b 	ldhu	r2,12(r16)
+ 8045754:	1544703a 	and	r2,r2,r21
+ 8045758:	10802014 	ori	r2,r2,128
+ 804575c:	8080030d 	sth	r2,12(r16)
+ 8045760:	8dc5c83a 	sub	r2,r17,r23
+ 8045764:	1dc9883a 	add	r4,r3,r23
+ 8045768:	84400515 	stw	r17,20(r16)
+ 804576c:	80c00415 	stw	r3,16(r16)
+ 8045770:	81000015 	stw	r4,0(r16)
+ 8045774:	9023883a 	mov	r17,r18
+ 8045778:	80800215 	stw	r2,8(r16)
+ 804577c:	902f883a 	mov	r23,r18
+ 8045780:	b80d883a 	mov	r6,r23
+ 8045784:	e00b883a 	mov	r5,fp
+ 8045788:	80087b80 	call	80087b8 <memmove>
+ 804578c:	80c00217 	ldw	r3,8(r16)
+ 8045790:	81000017 	ldw	r4,0(r16)
+ 8045794:	98800217 	ldw	r2,8(r19)
+ 8045798:	1c63c83a 	sub	r17,r3,r17
+ 804579c:	25c9883a 	add	r4,r4,r23
+ 80457a0:	84400215 	stw	r17,8(r16)
+ 80457a4:	81000015 	stw	r4,0(r16)
+ 80457a8:	14a5c83a 	sub	r18,r2,r18
+ 80457ac:	9c800215 	stw	r18,8(r19)
+ 80457b0:	90001926 	beq	r18,zero,8045818 <__ssprint_r+0x188>
+ 80457b4:	b4800117 	ldw	r18,4(r22)
+ 80457b8:	b7000017 	ldw	fp,0(r22)
+ 80457bc:	882f883a 	mov	r23,r17
+ 80457c0:	b5800204 	addi	r22,r22,8
+ 80457c4:	903ffb26 	beq	r18,zero,80457b4 <__ssprint_r+0x124>
+ 80457c8:	947fc62e 	bgeu	r18,r17,80456e4 <__ssprint_r+0x54>
+ 80457cc:	9023883a 	mov	r17,r18
+ 80457d0:	902f883a 	mov	r23,r18
+ 80457d4:	003fea06 	br	8045780 <__ssprint_r+0xf0>
+ 80457d8:	a009883a 	mov	r4,r20
+ 80457dc:	8009abc0 	call	8009abc <_realloc_r>
+ 80457e0:	1007883a 	mov	r3,r2
+ 80457e4:	103fde1e 	bne	r2,zero,8045760 <__ssprint_r+0xd0>
+ 80457e8:	81400417 	ldw	r5,16(r16)
+ 80457ec:	a009883a 	mov	r4,r20
+ 80457f0:	80071c40 	call	80071c4 <_free_r>
+ 80457f4:	80c0030b 	ldhu	r3,12(r16)
+ 80457f8:	00800304 	movi	r2,12
+ 80457fc:	a0800015 	stw	r2,0(r20)
+ 8045800:	18c01014 	ori	r3,r3,64
+ 8045804:	80c0030d 	sth	r3,12(r16)
+ 8045808:	00bfffc4 	movi	r2,-1
+ 804580c:	98000215 	stw	zero,8(r19)
+ 8045810:	98000115 	stw	zero,4(r19)
+ 8045814:	00000206 	br	8045820 <__ssprint_r+0x190>
+ 8045818:	98000115 	stw	zero,4(r19)
+ 804581c:	0005883a 	mov	r2,zero
+ 8045820:	dfc00917 	ldw	ra,36(sp)
+ 8045824:	df000817 	ldw	fp,32(sp)
+ 8045828:	ddc00717 	ldw	r23,28(sp)
+ 804582c:	dd800617 	ldw	r22,24(sp)
+ 8045830:	dd400517 	ldw	r21,20(sp)
+ 8045834:	dd000417 	ldw	r20,16(sp)
+ 8045838:	dcc00317 	ldw	r19,12(sp)
+ 804583c:	dc800217 	ldw	r18,8(sp)
+ 8045840:	dc400117 	ldw	r17,4(sp)
+ 8045844:	dc000017 	ldw	r16,0(sp)
+ 8045848:	dec00a04 	addi	sp,sp,40
+ 804584c:	f800283a 	ret
+
+08045850 <___svfiprintf_internal_r>:
+ 8045850:	2880030b 	ldhu	r2,12(r5)
+ 8045854:	deffd004 	addi	sp,sp,-192
+ 8045858:	df002e15 	stw	fp,184(sp)
+ 804585c:	dd802c15 	stw	r22,176(sp)
+ 8045860:	dd002a15 	stw	r20,168(sp)
+ 8045864:	dfc02f15 	stw	ra,188(sp)
+ 8045868:	ddc02d15 	stw	r23,180(sp)
+ 804586c:	dd402b15 	stw	r21,172(sp)
+ 8045870:	dcc02915 	stw	r19,164(sp)
+ 8045874:	dc802815 	stw	r18,160(sp)
+ 8045878:	dc402715 	stw	r17,156(sp)
+ 804587c:	dc002615 	stw	r16,152(sp)
+ 8045880:	1080200c 	andi	r2,r2,128
+ 8045884:	d9c00315 	stw	r7,12(sp)
+ 8045888:	2829883a 	mov	r20,r5
+ 804588c:	202d883a 	mov	r22,r4
+ 8045890:	3039883a 	mov	fp,r6
+ 8045894:	10000226 	beq	r2,zero,80458a0 <___svfiprintf_internal_r+0x50>
+ 8045898:	28800417 	ldw	r2,16(r5)
+ 804589c:	10039b26 	beq	r2,zero,804670c <___svfiprintf_internal_r+0xebc>
+ 80458a0:	dc801604 	addi	r18,sp,88
+ 80458a4:	dc800915 	stw	r18,36(sp)
+ 80458a8:	d8000b15 	stw	zero,44(sp)
+ 80458ac:	d8000a15 	stw	zero,40(sp)
+ 80458b0:	9011883a 	mov	r8,r18
+ 80458b4:	d8000415 	stw	zero,16(sp)
+ 80458b8:	d8000015 	stw	zero,0(sp)
+ 80458bc:	e0800007 	ldb	r2,0(fp)
+ 80458c0:	10009026 	beq	r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4>
+ 80458c4:	10800960 	cmpeqi	r2,r2,37
+ 80458c8:	1003751e 	bne	r2,zero,80466a0 <___svfiprintf_internal_r+0xe50>
+ 80458cc:	e021883a 	mov	r16,fp
+ 80458d0:	00000206 	br	80458dc <___svfiprintf_internal_r+0x8c>
+ 80458d4:	18008126 	beq	r3,zero,8045adc <___svfiprintf_internal_r+0x28c>
+ 80458d8:	8821883a 	mov	r16,r17
+ 80458dc:	80800047 	ldb	r2,1(r16)
+ 80458e0:	84400044 	addi	r17,r16,1
+ 80458e4:	10c00958 	cmpnei	r3,r2,37
+ 80458e8:	103ffa1e 	bne	r2,zero,80458d4 <___svfiprintf_internal_r+0x84>
+ 80458ec:	8f27c83a 	sub	r19,r17,fp
+ 80458f0:	98008426 	beq	r19,zero,8045b04 <___svfiprintf_internal_r+0x2b4>
+ 80458f4:	d8c00b17 	ldw	r3,44(sp)
+ 80458f8:	d8800a17 	ldw	r2,40(sp)
+ 80458fc:	47000015 	stw	fp,0(r8)
+ 8045900:	1cc7883a 	add	r3,r3,r19
+ 8045904:	10800044 	addi	r2,r2,1
+ 8045908:	d8800a15 	stw	r2,40(sp)
+ 804590c:	44c00115 	stw	r19,4(r8)
+ 8045910:	d8c00b15 	stw	r3,44(sp)
+ 8045914:	10800208 	cmpgei	r2,r2,8
+ 8045918:	1000731e 	bne	r2,zero,8045ae8 <___svfiprintf_internal_r+0x298>
+ 804591c:	42000204 	addi	r8,r8,8
+ 8045920:	d8c00017 	ldw	r3,0(sp)
+ 8045924:	80800047 	ldb	r2,1(r16)
+ 8045928:	1cc7883a 	add	r3,r3,r19
+ 804592c:	d8c00015 	stw	r3,0(sp)
+ 8045930:	10007426 	beq	r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4>
+ 8045934:	88800047 	ldb	r2,1(r17)
+ 8045938:	8f000044 	addi	fp,r17,1
+ 804593c:	d8000845 	stb	zero,33(sp)
+ 8045940:	000b883a 	mov	r5,zero
+ 8045944:	000d883a 	mov	r6,zero
+ 8045948:	027fffc4 	movi	r9,-1
+ 804594c:	0021883a 	mov	r16,zero
+ 8045950:	0019883a 	mov	r12,zero
+ 8045954:	e7000044 	addi	fp,fp,1
+ 8045958:	10fff804 	addi	r3,r2,-32
+ 804595c:	19001668 	cmpgeui	r4,r3,89
+ 8045960:	20008a1e 	bne	r4,zero,8045b8c <___svfiprintf_internal_r+0x33c>
+ 8045964:	180690ba 	slli	r3,r3,2
+ 8045968:	01020134 	movhi	r4,2052
+ 804596c:	1909883a 	add	r4,r3,r4
+ 8045970:	20d65e17 	ldw	r3,22904(r4)
+ 8045974:	1800683a 	jmp	r3
+ 8045978:	08045c5c 	xori	zero,at,4465
+ 804597c:	08045b8c 	andi	zero,at,4462
+ 8045980:	08045b8c 	andi	zero,at,4462
+ 8045984:	08045c50 	cmplti	zero,at,4465
+ 8045988:	08045b8c 	andi	zero,at,4462
+ 804598c:	08045b8c 	andi	zero,at,4462
+ 8045990:	08045b8c 	andi	zero,at,4462
+ 8045994:	08045b8c 	andi	zero,at,4462
+ 8045998:	08045b8c 	andi	zero,at,4462
+ 804599c:	08045b8c 	andi	zero,at,4462
+ 80459a0:	08045c28 	cmpgeui	zero,at,4464
+ 80459a4:	08045c18 	cmpnei	zero,at,4464
+ 80459a8:	08045b8c 	andi	zero,at,4462
+ 80459ac:	08045c00 	call	8045c0 <OSCtxSw_SWITCH_PC+0x804580>
+ 80459b0:	08045bbc 	xorhi	zero,at,4462
+ 80459b4:	08045b8c 	andi	zero,at,4462
+ 80459b8:	08045bb0 	cmpltui	zero,at,4462
+ 80459bc:	08045b5c 	xori	zero,at,4461
+ 80459c0:	08045b5c 	xori	zero,at,4461
+ 80459c4:	08045b5c 	xori	zero,at,4461
+ 80459c8:	08045b5c 	xori	zero,at,4461
+ 80459cc:	08045b5c 	xori	zero,at,4461
+ 80459d0:	08045b5c 	xori	zero,at,4461
+ 80459d4:	08045b5c 	xori	zero,at,4461
+ 80459d8:	08045b5c 	xori	zero,at,4461
+ 80459dc:	08045b5c 	xori	zero,at,4461
+ 80459e0:	08045b8c 	andi	zero,at,4462
+ 80459e4:	08045b8c 	andi	zero,at,4462
+ 80459e8:	08045b8c 	andi	zero,at,4462
+ 80459ec:	08045b8c 	andi	zero,at,4462
+ 80459f0:	08045b8c 	andi	zero,at,4462
+ 80459f4:	08045b8c 	andi	zero,at,4462
+ 80459f8:	08045b8c 	andi	zero,at,4462
+ 80459fc:	08045b8c 	andi	zero,at,4462
+ 8045a00:	08045b8c 	andi	zero,at,4462
+ 8045a04:	08045b8c 	andi	zero,at,4462
+ 8045a08:	080461c8 	cmpgei	zero,at,4487
+ 8045a0c:	08045b8c 	andi	zero,at,4462
+ 8045a10:	08045b8c 	andi	zero,at,4462
+ 8045a14:	08045b8c 	andi	zero,at,4462
+ 8045a18:	08045b8c 	andi	zero,at,4462
+ 8045a1c:	08045b8c 	andi	zero,at,4462
+ 8045a20:	08045b8c 	andi	zero,at,4462
+ 8045a24:	08045b8c 	andi	zero,at,4462
+ 8045a28:	08045b8c 	andi	zero,at,4462
+ 8045a2c:	08045b8c 	andi	zero,at,4462
+ 8045a30:	08045b8c 	andi	zero,at,4462
+ 8045a34:	08046194 	ori	zero,at,4486
+ 8045a38:	08045b8c 	andi	zero,at,4462
+ 8045a3c:	08045b8c 	andi	zero,at,4462
+ 8045a40:	08045b8c 	andi	zero,at,4462
+ 8045a44:	08045b8c 	andi	zero,at,4462
+ 8045a48:	08045b8c 	andi	zero,at,4462
+ 8045a4c:	08046160 	cmpeqi	zero,at,4485
+ 8045a50:	08045b8c 	andi	zero,at,4462
+ 8045a54:	08045b8c 	andi	zero,at,4462
+ 8045a58:	08046118 	cmpnei	zero,at,4484
+ 8045a5c:	08045b8c 	andi	zero,at,4462
+ 8045a60:	08045b8c 	andi	zero,at,4462
+ 8045a64:	08045b8c 	andi	zero,at,4462
+ 8045a68:	08045b8c 	andi	zero,at,4462
+ 8045a6c:	08045b8c 	andi	zero,at,4462
+ 8045a70:	08045b8c 	andi	zero,at,4462
+ 8045a74:	08045b8c 	andi	zero,at,4462
+ 8045a78:	08045b8c 	andi	zero,at,4462
+ 8045a7c:	08045b8c 	andi	zero,at,4462
+ 8045a80:	08045b8c 	andi	zero,at,4462
+ 8045a84:	080460e8 	cmpgeui	zero,at,4483
+ 8045a88:	08046074 	orhi	zero,at,4481
+ 8045a8c:	08045b8c 	andi	zero,at,4462
+ 8045a90:	08045b8c 	andi	zero,at,4462
+ 8045a94:	08045b8c 	andi	zero,at,4462
+ 8045a98:	08046068 	cmpgeui	zero,at,4481
+ 8045a9c:	08046074 	orhi	zero,at,4481
+ 8045aa0:	08045b8c 	andi	zero,at,4462
+ 8045aa4:	08045b8c 	andi	zero,at,4462
+ 8045aa8:	08046054 	ori	zero,at,4481
+ 8045aac:	08045b8c 	andi	zero,at,4462
+ 8045ab0:	08046014 	ori	zero,at,4480
+ 8045ab4:	08045fd4 	ori	zero,at,4479
+ 8045ab8:	08045d7c 	xorhi	zero,at,4469
+ 8045abc:	08045d70 	cmpltui	zero,at,4469
+ 8045ac0:	08045b8c 	andi	zero,at,4462
+ 8045ac4:	08045d10 	cmplti	zero,at,4468
+ 8045ac8:	08045b8c 	andi	zero,at,4462
+ 8045acc:	08045cd0 	cmplti	zero,at,4467
+ 8045ad0:	08045b8c 	andi	zero,at,4462
+ 8045ad4:	08045b8c 	andi	zero,at,4462
+ 8045ad8:	08045c88 	cmpgei	zero,at,4466
+ 8045adc:	8f27c83a 	sub	r19,r17,fp
+ 8045ae0:	983f9426 	beq	r19,zero,8045934 <___svfiprintf_internal_r+0xe4>
+ 8045ae4:	003f8306 	br	80458f4 <___svfiprintf_internal_r+0xa4>
+ 8045ae8:	d9800904 	addi	r6,sp,36
+ 8045aec:	a00b883a 	mov	r5,r20
+ 8045af0:	b009883a 	mov	r4,r22
+ 8045af4:	80456900 	call	8045690 <__ssprint_r>
+ 8045af8:	1000081e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8045afc:	9011883a 	mov	r8,r18
+ 8045b00:	003f8706 	br	8045920 <___svfiprintf_internal_r+0xd0>
+ 8045b04:	d8800b17 	ldw	r2,44(sp)
+ 8045b08:	10000426 	beq	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8045b0c:	d9800904 	addi	r6,sp,36
+ 8045b10:	a00b883a 	mov	r5,r20
+ 8045b14:	b009883a 	mov	r4,r22
+ 8045b18:	80456900 	call	8045690 <__ssprint_r>
+ 8045b1c:	a080030b 	ldhu	r2,12(r20)
+ 8045b20:	1080100c 	andi	r2,r2,64
+ 8045b24:	10037e1e 	bne	r2,zero,8046920 <___svfiprintf_internal_r+0x10d0>
+ 8045b28:	d8800017 	ldw	r2,0(sp)
+ 8045b2c:	dfc02f17 	ldw	ra,188(sp)
+ 8045b30:	df002e17 	ldw	fp,184(sp)
+ 8045b34:	ddc02d17 	ldw	r23,180(sp)
+ 8045b38:	dd802c17 	ldw	r22,176(sp)
+ 8045b3c:	dd402b17 	ldw	r21,172(sp)
+ 8045b40:	dd002a17 	ldw	r20,168(sp)
+ 8045b44:	dcc02917 	ldw	r19,164(sp)
+ 8045b48:	dc802817 	ldw	r18,160(sp)
+ 8045b4c:	dc402717 	ldw	r17,156(sp)
+ 8045b50:	dc002617 	ldw	r16,152(sp)
+ 8045b54:	dec03004 	addi	sp,sp,192
+ 8045b58:	f800283a 	ret
+ 8045b5c:	0021883a 	mov	r16,zero
+ 8045b60:	10fff404 	addi	r3,r2,-48
+ 8045b64:	e7000044 	addi	fp,fp,1
+ 8045b68:	840002a4 	muli	r16,r16,10
+ 8045b6c:	e0bfffc7 	ldb	r2,-1(fp)
+ 8045b70:	1c21883a 	add	r16,r3,r16
+ 8045b74:	10fff404 	addi	r3,r2,-48
+ 8045b78:	190002b0 	cmpltui	r4,r3,10
+ 8045b7c:	203ff91e 	bne	r4,zero,8045b64 <___svfiprintf_internal_r+0x314>
+ 8045b80:	10fff804 	addi	r3,r2,-32
+ 8045b84:	19001668 	cmpgeui	r4,r3,89
+ 8045b88:	203f7626 	beq	r4,zero,8045964 <___svfiprintf_internal_r+0x114>
+ 8045b8c:	29403fcc 	andi	r5,r5,255
+ 8045b90:	2803471e 	bne	r5,zero,80468b0 <___svfiprintf_internal_r+0x1060>
+ 8045b94:	103fdb26 	beq	r2,zero,8045b04 <___svfiprintf_internal_r+0x2b4>
+ 8045b98:	d8800c05 	stb	r2,48(sp)
+ 8045b9c:	d8000845 	stb	zero,33(sp)
+ 8045ba0:	04c00044 	movi	r19,1
+ 8045ba4:	05400044 	movi	r21,1
+ 8045ba8:	ddc00c04 	addi	r23,sp,48
+ 8045bac:	00015706 	br	804610c <___svfiprintf_internal_r+0x8bc>
+ 8045bb0:	63002014 	ori	r12,r12,128
+ 8045bb4:	e0800007 	ldb	r2,0(fp)
+ 8045bb8:	003f6606 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045bbc:	e0800007 	ldb	r2,0(fp)
+ 8045bc0:	e1000044 	addi	r4,fp,1
+ 8045bc4:	10c00aa0 	cmpeqi	r3,r2,42
+ 8045bc8:	1803581e 	bne	r3,zero,804692c <___svfiprintf_internal_r+0x10dc>
+ 8045bcc:	10fff404 	addi	r3,r2,-48
+ 8045bd0:	19c002b0 	cmpltui	r7,r3,10
+ 8045bd4:	2039883a 	mov	fp,r4
+ 8045bd8:	0013883a 	mov	r9,zero
+ 8045bdc:	383f5e26 	beq	r7,zero,8045958 <___svfiprintf_internal_r+0x108>
+ 8045be0:	e7000044 	addi	fp,fp,1
+ 8045be4:	4a4002a4 	muli	r9,r9,10
+ 8045be8:	e0bfffc7 	ldb	r2,-1(fp)
+ 8045bec:	48d3883a 	add	r9,r9,r3
+ 8045bf0:	10fff404 	addi	r3,r2,-48
+ 8045bf4:	190002b0 	cmpltui	r4,r3,10
+ 8045bf8:	203ff91e 	bne	r4,zero,8045be0 <___svfiprintf_internal_r+0x390>
+ 8045bfc:	003f5606 	br	8045958 <___svfiprintf_internal_r+0x108>
+ 8045c00:	e0800003 	ldbu	r2,0(fp)
+ 8045c04:	10803fcc 	andi	r2,r2,255
+ 8045c08:	1080201c 	xori	r2,r2,128
+ 8045c0c:	63000114 	ori	r12,r12,4
+ 8045c10:	10bfe004 	addi	r2,r2,-128
+ 8045c14:	003f4f06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045c18:	01400044 	movi	r5,1
+ 8045c1c:	01800ac4 	movi	r6,43
+ 8045c20:	e0800007 	ldb	r2,0(fp)
+ 8045c24:	003f4b06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045c28:	d8800317 	ldw	r2,12(sp)
+ 8045c2c:	14000017 	ldw	r16,0(r2)
+ 8045c30:	15c00104 	addi	r23,r2,4
+ 8045c34:	e0800003 	ldbu	r2,0(fp)
+ 8045c38:	8002ee16 	blt	r16,zero,80467f4 <___svfiprintf_internal_r+0xfa4>
+ 8045c3c:	ddc00315 	stw	r23,12(sp)
+ 8045c40:	10803fcc 	andi	r2,r2,255
+ 8045c44:	1080201c 	xori	r2,r2,128
+ 8045c48:	10bfe004 	addi	r2,r2,-128
+ 8045c4c:	003f4106 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045c50:	63000054 	ori	r12,r12,1
+ 8045c54:	e0800007 	ldb	r2,0(fp)
+ 8045c58:	003f3e06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045c5c:	30c03fcc 	andi	r3,r6,255
+ 8045c60:	18c0201c 	xori	r3,r3,128
+ 8045c64:	18ffe004 	addi	r3,r3,-128
+ 8045c68:	e0800003 	ldbu	r2,0(fp)
+ 8045c6c:	183ff41e 	bne	r3,zero,8045c40 <___svfiprintf_internal_r+0x3f0>
+ 8045c70:	10803fcc 	andi	r2,r2,255
+ 8045c74:	1080201c 	xori	r2,r2,128
+ 8045c78:	01400044 	movi	r5,1
+ 8045c7c:	01800804 	movi	r6,32
+ 8045c80:	10bfe004 	addi	r2,r2,-128
+ 8045c84:	003f3306 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045c88:	29403fcc 	andi	r5,r5,255
+ 8045c8c:	28030e1e 	bne	r5,zero,80468c8 <___svfiprintf_internal_r+0x1078>
+ 8045c90:	00c20134 	movhi	r3,2052
+ 8045c94:	18dd2004 	addi	r3,r3,29824
+ 8045c98:	d8c00415 	stw	r3,16(sp)
+ 8045c9c:	60c0080c 	andi	r3,r12,32
+ 8045ca0:	18012426 	beq	r3,zero,8046134 <___svfiprintf_internal_r+0x8e4>
+ 8045ca4:	d8c00317 	ldw	r3,12(sp)
+ 8045ca8:	1cc00017 	ldw	r19,0(r3)
+ 8045cac:	1d400117 	ldw	r21,4(r3)
+ 8045cb0:	18c00204 	addi	r3,r3,8
+ 8045cb4:	d8c00315 	stw	r3,12(sp)
+ 8045cb8:	60c0004c 	andi	r3,r12,1
+ 8045cbc:	18000226 	beq	r3,zero,8045cc8 <___svfiprintf_internal_r+0x478>
+ 8045cc0:	9d46b03a 	or	r3,r19,r21
+ 8045cc4:	1802811e 	bne	r3,zero,80466cc <___svfiprintf_internal_r+0xe7c>
+ 8045cc8:	00800084 	movi	r2,2
+ 8045ccc:	00003906 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 8045cd0:	29403fcc 	andi	r5,r5,255
+ 8045cd4:	2803081e 	bne	r5,zero,80468f8 <___svfiprintf_internal_r+0x10a8>
+ 8045cd8:	6080080c 	andi	r2,r12,32
+ 8045cdc:	10017e1e 	bne	r2,zero,80462d8 <___svfiprintf_internal_r+0xa88>
+ 8045ce0:	d8800317 	ldw	r2,12(sp)
+ 8045ce4:	60c0040c 	andi	r3,r12,16
+ 8045ce8:	14c00017 	ldw	r19,0(r2)
+ 8045cec:	10800104 	addi	r2,r2,4
+ 8045cf0:	1801221e 	bne	r3,zero,804617c <___svfiprintf_internal_r+0x92c>
+ 8045cf4:	60c0100c 	andi	r3,r12,64
+ 8045cf8:	1802e626 	beq	r3,zero,8046894 <___svfiprintf_internal_r+0x1044>
+ 8045cfc:	d8800315 	stw	r2,12(sp)
+ 8045d00:	9cffffcc 	andi	r19,r19,65535
+ 8045d04:	002b883a 	mov	r21,zero
+ 8045d08:	00800044 	movi	r2,1
+ 8045d0c:	00002906 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 8045d10:	d8800317 	ldw	r2,12(sp)
+ 8045d14:	d8000845 	stb	zero,33(sp)
+ 8045d18:	15c00017 	ldw	r23,0(r2)
+ 8045d1c:	14400104 	addi	r17,r2,4
+ 8045d20:	b802cf26 	beq	r23,zero,8046860 <___svfiprintf_internal_r+0x1010>
+ 8045d24:	48bfffe0 	cmpeqi	r2,r9,-1
+ 8045d28:	10026e1e 	bne	r2,zero,80466e4 <___svfiprintf_internal_r+0xe94>
+ 8045d2c:	480d883a 	mov	r6,r9
+ 8045d30:	000b883a 	mov	r5,zero
+ 8045d34:	b809883a 	mov	r4,r23
+ 8045d38:	da000315 	stw	r8,12(sp)
+ 8045d3c:	db000215 	stw	r12,8(sp)
+ 8045d40:	da400115 	stw	r9,4(sp)
+ 8045d44:	80085d00 	call	80085d0 <memchr>
+ 8045d48:	da400117 	ldw	r9,4(sp)
+ 8045d4c:	db000217 	ldw	r12,8(sp)
+ 8045d50:	da000317 	ldw	r8,12(sp)
+ 8045d54:	1002d826 	beq	r2,zero,80468b8 <___svfiprintf_internal_r+0x1068>
+ 8045d58:	15ebc83a 	sub	r21,r2,r23
+ 8045d5c:	a827883a 	mov	r19,r21
+ 8045d60:	a800010e 	bge	r21,zero,8045d68 <___svfiprintf_internal_r+0x518>
+ 8045d64:	0027883a 	mov	r19,zero
+ 8045d68:	dc400315 	stw	r17,12(sp)
+ 8045d6c:	0000e706 	br	804610c <___svfiprintf_internal_r+0x8bc>
+ 8045d70:	63000814 	ori	r12,r12,32
+ 8045d74:	e0800007 	ldb	r2,0(fp)
+ 8045d78:	003ef606 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8045d7c:	d8c00317 	ldw	r3,12(sp)
+ 8045d80:	00800c04 	movi	r2,48
+ 8045d84:	d8800885 	stb	r2,34(sp)
+ 8045d88:	00801e04 	movi	r2,120
+ 8045d8c:	01020134 	movhi	r4,2052
+ 8045d90:	d88008c5 	stb	r2,35(sp)
+ 8045d94:	1cc00017 	ldw	r19,0(r3)
+ 8045d98:	18800104 	addi	r2,r3,4
+ 8045d9c:	d8800315 	stw	r2,12(sp)
+ 8045da0:	209d2004 	addi	r2,r4,29824
+ 8045da4:	d8800415 	stw	r2,16(sp)
+ 8045da8:	002b883a 	mov	r21,zero
+ 8045dac:	63000094 	ori	r12,r12,2
+ 8045db0:	00800084 	movi	r2,2
+ 8045db4:	d8000845 	stb	zero,33(sp)
+ 8045db8:	48ffffe0 	cmpeqi	r3,r9,-1
+ 8045dbc:	001b883a 	mov	r13,zero
+ 8045dc0:	1801181e 	bne	r3,zero,8046224 <___svfiprintf_internal_r+0x9d4>
+ 8045dc4:	047fdfc4 	movi	r17,-129
+ 8045dc8:	9d46b03a 	or	r3,r19,r21
+ 8045dcc:	6462703a 	and	r17,r12,r17
+ 8045dd0:	1801d21e 	bne	r3,zero,804651c <___svfiprintf_internal_r+0xccc>
+ 8045dd4:	48028a1e 	bne	r9,zero,8046800 <___svfiprintf_internal_r+0xfb0>
+ 8045dd8:	1000bf1e 	bne	r2,zero,80460d8 <___svfiprintf_internal_r+0x888>
+ 8045ddc:	6540004c 	andi	r21,r12,1
+ 8045de0:	a8023126 	beq	r21,zero,80466a8 <___svfiprintf_internal_r+0xe58>
+ 8045de4:	00800c04 	movi	r2,48
+ 8045de8:	d88015c5 	stb	r2,87(sp)
+ 8045dec:	ddc015c4 	addi	r23,sp,87
+ 8045df0:	4827883a 	mov	r19,r9
+ 8045df4:	4d40010e 	bge	r9,r21,8045dfc <___svfiprintf_internal_r+0x5ac>
+ 8045df8:	a827883a 	mov	r19,r21
+ 8045dfc:	6b403fcc 	andi	r13,r13,255
+ 8045e00:	6b40201c 	xori	r13,r13,128
+ 8045e04:	6b7fe004 	addi	r13,r13,-128
+ 8045e08:	68000126 	beq	r13,zero,8045e10 <___svfiprintf_internal_r+0x5c0>
+ 8045e0c:	9cc00044 	addi	r19,r19,1
+ 8045e10:	8b40008c 	andi	r13,r17,2
+ 8045e14:	68000126 	beq	r13,zero,8045e1c <___svfiprintf_internal_r+0x5cc>
+ 8045e18:	9cc00084 	addi	r19,r19,2
+ 8045e1c:	8b00210c 	andi	r12,r17,132
+ 8045e20:	d8800b17 	ldw	r2,44(sp)
+ 8045e24:	d9000a17 	ldw	r4,40(sp)
+ 8045e28:	6000021e 	bne	r12,zero,8045e34 <___svfiprintf_internal_r+0x5e4>
+ 8045e2c:	84c7c83a 	sub	r3,r16,r19
+ 8045e30:	00c1bc16 	blt	zero,r3,8046524 <___svfiprintf_internal_r+0xcd4>
+ 8045e34:	d9800847 	ldb	r6,33(sp)
+ 8045e38:	21400044 	addi	r5,r4,1
+ 8045e3c:	40c00204 	addi	r3,r8,8
+ 8045e40:	30000f26 	beq	r6,zero,8045e80 <___svfiprintf_internal_r+0x630>
+ 8045e44:	d9800844 	addi	r6,sp,33
+ 8045e48:	10800044 	addi	r2,r2,1
+ 8045e4c:	41800015 	stw	r6,0(r8)
+ 8045e50:	01800044 	movi	r6,1
+ 8045e54:	41800115 	stw	r6,4(r8)
+ 8045e58:	d8800b15 	stw	r2,44(sp)
+ 8045e5c:	d9400a15 	stw	r5,40(sp)
+ 8045e60:	29800208 	cmpgei	r6,r5,8
+ 8045e64:	3001e11e 	bne	r6,zero,80465ec <___svfiprintf_internal_r+0xd9c>
+ 8045e68:	21c00084 	addi	r7,r4,2
+ 8045e6c:	41800404 	addi	r6,r8,16
+ 8045e70:	2809883a 	mov	r4,r5
+ 8045e74:	1811883a 	mov	r8,r3
+ 8045e78:	380b883a 	mov	r5,r7
+ 8045e7c:	3007883a 	mov	r3,r6
+ 8045e80:	68000d26 	beq	r13,zero,8045eb8 <___svfiprintf_internal_r+0x668>
+ 8045e84:	d9000884 	addi	r4,sp,34
+ 8045e88:	10800084 	addi	r2,r2,2
+ 8045e8c:	41000015 	stw	r4,0(r8)
+ 8045e90:	01000084 	movi	r4,2
+ 8045e94:	41000115 	stw	r4,4(r8)
+ 8045e98:	d8800b15 	stw	r2,44(sp)
+ 8045e9c:	d9400a15 	stw	r5,40(sp)
+ 8045ea0:	29000208 	cmpgei	r4,r5,8
+ 8045ea4:	2001e21e 	bne	r4,zero,8046630 <___svfiprintf_internal_r+0xde0>
+ 8045ea8:	2809883a 	mov	r4,r5
+ 8045eac:	1811883a 	mov	r8,r3
+ 8045eb0:	29400044 	addi	r5,r5,1
+ 8045eb4:	18c00204 	addi	r3,r3,8
+ 8045eb8:	63002018 	cmpnei	r12,r12,128
+ 8045ebc:	60011626 	beq	r12,zero,8046318 <___svfiprintf_internal_r+0xac8>
+ 8045ec0:	4d53c83a 	sub	r9,r9,r21
+ 8045ec4:	02414816 	blt	zero,r9,80463e8 <___svfiprintf_internal_r+0xb98>
+ 8045ec8:	a885883a 	add	r2,r21,r2
+ 8045ecc:	45c00015 	stw	r23,0(r8)
+ 8045ed0:	45400115 	stw	r21,4(r8)
+ 8045ed4:	d8800b15 	stw	r2,44(sp)
+ 8045ed8:	d9400a15 	stw	r5,40(sp)
+ 8045edc:	29000210 	cmplti	r4,r5,8
+ 8045ee0:	20017026 	beq	r4,zero,80464a4 <___svfiprintf_internal_r+0xc54>
+ 8045ee4:	8c40010c 	andi	r17,r17,4
+ 8045ee8:	88000226 	beq	r17,zero,8045ef4 <___svfiprintf_internal_r+0x6a4>
+ 8045eec:	84e3c83a 	sub	r17,r16,r19
+ 8045ef0:	04400916 	blt	zero,r17,8045f18 <___svfiprintf_internal_r+0x6c8>
+ 8045ef4:	84c0010e 	bge	r16,r19,8045efc <___svfiprintf_internal_r+0x6ac>
+ 8045ef8:	9821883a 	mov	r16,r19
+ 8045efc:	d8c00017 	ldw	r3,0(sp)
+ 8045f00:	1c07883a 	add	r3,r3,r16
+ 8045f04:	d8c00015 	stw	r3,0(sp)
+ 8045f08:	10017e1e 	bne	r2,zero,8046504 <___svfiprintf_internal_r+0xcb4>
+ 8045f0c:	d8000a15 	stw	zero,40(sp)
+ 8045f10:	9011883a 	mov	r8,r18
+ 8045f14:	003e6906 	br	80458bc <___svfiprintf_internal_r+0x6c>
+ 8045f18:	01c20174 	movhi	r7,2053
+ 8045f1c:	89400450 	cmplti	r5,r17,17
+ 8045f20:	39ee4044 	addi	r7,r7,-18175
+ 8045f24:	d9000a17 	ldw	r4,40(sp)
+ 8045f28:	05400404 	movi	r21,16
+ 8045f2c:	28000526 	beq	r5,zero,8045f44 <___svfiprintf_internal_r+0x6f4>
+ 8045f30:	00001906 	br	8045f98 <___svfiprintf_internal_r+0x748>
+ 8045f34:	8c7ffc04 	addi	r17,r17,-16
+ 8045f38:	89400448 	cmpgei	r5,r17,17
+ 8045f3c:	18c00204 	addi	r3,r3,8
+ 8045f40:	28001526 	beq	r5,zero,8045f98 <___svfiprintf_internal_r+0x748>
+ 8045f44:	21000044 	addi	r4,r4,1
+ 8045f48:	10800404 	addi	r2,r2,16
+ 8045f4c:	19c00015 	stw	r7,0(r3)
+ 8045f50:	1d400115 	stw	r21,4(r3)
+ 8045f54:	d8800b15 	stw	r2,44(sp)
+ 8045f58:	d9000a15 	stw	r4,40(sp)
+ 8045f5c:	21400208 	cmpgei	r5,r4,8
+ 8045f60:	283ff426 	beq	r5,zero,8045f34 <___svfiprintf_internal_r+0x6e4>
+ 8045f64:	d9800904 	addi	r6,sp,36
+ 8045f68:	a00b883a 	mov	r5,r20
+ 8045f6c:	b009883a 	mov	r4,r22
+ 8045f70:	d9c00115 	stw	r7,4(sp)
+ 8045f74:	80456900 	call	8045690 <__ssprint_r>
+ 8045f78:	103ee81e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8045f7c:	8c7ffc04 	addi	r17,r17,-16
+ 8045f80:	89400448 	cmpgei	r5,r17,17
+ 8045f84:	d8800b17 	ldw	r2,44(sp)
+ 8045f88:	d9000a17 	ldw	r4,40(sp)
+ 8045f8c:	9007883a 	mov	r3,r18
+ 8045f90:	d9c00117 	ldw	r7,4(sp)
+ 8045f94:	283feb1e 	bne	r5,zero,8045f44 <___svfiprintf_internal_r+0x6f4>
+ 8045f98:	21000044 	addi	r4,r4,1
+ 8045f9c:	1445883a 	add	r2,r2,r17
+ 8045fa0:	d9000a15 	stw	r4,40(sp)
+ 8045fa4:	19c00015 	stw	r7,0(r3)
+ 8045fa8:	1c400115 	stw	r17,4(r3)
+ 8045fac:	d8800b15 	stw	r2,44(sp)
+ 8045fb0:	21000210 	cmplti	r4,r4,8
+ 8045fb4:	203fcf1e 	bne	r4,zero,8045ef4 <___svfiprintf_internal_r+0x6a4>
+ 8045fb8:	d9800904 	addi	r6,sp,36
+ 8045fbc:	a00b883a 	mov	r5,r20
+ 8045fc0:	b009883a 	mov	r4,r22
+ 8045fc4:	80456900 	call	8045690 <__ssprint_r>
+ 8045fc8:	103ed41e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8045fcc:	d8800b17 	ldw	r2,44(sp)
+ 8045fd0:	003fc806 	br	8045ef4 <___svfiprintf_internal_r+0x6a4>
+ 8045fd4:	29403fcc 	andi	r5,r5,255
+ 8045fd8:	28024b1e 	bne	r5,zero,8046908 <___svfiprintf_internal_r+0x10b8>
+ 8045fdc:	6080080c 	andi	r2,r12,32
+ 8045fe0:	1000af1e 	bne	r2,zero,80462a0 <___svfiprintf_internal_r+0xa50>
+ 8045fe4:	d8800317 	ldw	r2,12(sp)
+ 8045fe8:	60c0040c 	andi	r3,r12,16
+ 8045fec:	14c00017 	ldw	r19,0(r2)
+ 8045ff0:	10800104 	addi	r2,r2,4
+ 8045ff4:	18006e1e 	bne	r3,zero,80461b0 <___svfiprintf_internal_r+0x960>
+ 8045ff8:	60c0100c 	andi	r3,r12,64
+ 8045ffc:	18022126 	beq	r3,zero,8046884 <___svfiprintf_internal_r+0x1034>
+ 8046000:	d8800315 	stw	r2,12(sp)
+ 8046004:	9cffffcc 	andi	r19,r19,65535
+ 8046008:	002b883a 	mov	r21,zero
+ 804600c:	0005883a 	mov	r2,zero
+ 8046010:	003f6806 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 8046014:	29403fcc 	andi	r5,r5,255
+ 8046018:	2802391e 	bne	r5,zero,8046900 <___svfiprintf_internal_r+0x10b0>
+ 804601c:	d9000317 	ldw	r4,12(sp)
+ 8046020:	6080080c 	andi	r2,r12,32
+ 8046024:	20c00104 	addi	r3,r4,4
+ 8046028:	1001a11e 	bne	r2,zero,80466b0 <___svfiprintf_internal_r+0xe60>
+ 804602c:	6080040c 	andi	r2,r12,16
+ 8046030:	1001be1e 	bne	r2,zero,804672c <___svfiprintf_internal_r+0xedc>
+ 8046034:	6300100c 	andi	r12,r12,64
+ 8046038:	6001bc26 	beq	r12,zero,804672c <___svfiprintf_internal_r+0xedc>
+ 804603c:	d8800317 	ldw	r2,12(sp)
+ 8046040:	d8c00315 	stw	r3,12(sp)
+ 8046044:	d8c00017 	ldw	r3,0(sp)
+ 8046048:	10800017 	ldw	r2,0(r2)
+ 804604c:	10c0000d 	sth	r3,0(r2)
+ 8046050:	003e1a06 	br	80458bc <___svfiprintf_internal_r+0x6c>
+ 8046054:	e0800007 	ldb	r2,0(fp)
+ 8046058:	10c01b18 	cmpnei	r3,r2,108
+ 804605c:	1801ec26 	beq	r3,zero,8046810 <___svfiprintf_internal_r+0xfc0>
+ 8046060:	63000414 	ori	r12,r12,16
+ 8046064:	003e3b06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8046068:	63001014 	ori	r12,r12,64
+ 804606c:	e0800007 	ldb	r2,0(fp)
+ 8046070:	003e3806 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 8046074:	29403fcc 	andi	r5,r5,255
+ 8046078:	28021d1e 	bne	r5,zero,80468f0 <___svfiprintf_internal_r+0x10a0>
+ 804607c:	6080080c 	andi	r2,r12,32
+ 8046080:	10008e1e 	bne	r2,zero,80462bc <___svfiprintf_internal_r+0xa6c>
+ 8046084:	d8800317 	ldw	r2,12(sp)
+ 8046088:	60c0040c 	andi	r3,r12,16
+ 804608c:	10800104 	addi	r2,r2,4
+ 8046090:	1800541e 	bne	r3,zero,80461e4 <___svfiprintf_internal_r+0x994>
+ 8046094:	60c0100c 	andi	r3,r12,64
+ 8046098:	18005226 	beq	r3,zero,80461e4 <___svfiprintf_internal_r+0x994>
+ 804609c:	d8c00317 	ldw	r3,12(sp)
+ 80460a0:	d8800315 	stw	r2,12(sp)
+ 80460a4:	1cc0000f 	ldh	r19,0(r3)
+ 80460a8:	982bd7fa 	srai	r21,r19,31
+ 80460ac:	a805883a 	mov	r2,r21
+ 80460b0:	10005216 	blt	r2,zero,80461fc <___svfiprintf_internal_r+0x9ac>
+ 80460b4:	48bfffd8 	cmpnei	r2,r9,-1
+ 80460b8:	db400843 	ldbu	r13,33(sp)
+ 80460bc:	10008d26 	beq	r2,zero,80462f4 <___svfiprintf_internal_r+0xaa4>
+ 80460c0:	00ffdfc4 	movi	r3,-129
+ 80460c4:	9d44b03a 	or	r2,r19,r21
+ 80460c8:	60d8703a 	and	r12,r12,r3
+ 80460cc:	1000891e 	bne	r2,zero,80462f4 <___svfiprintf_internal_r+0xaa4>
+ 80460d0:	48008b1e 	bne	r9,zero,8046300 <___svfiprintf_internal_r+0xab0>
+ 80460d4:	6023883a 	mov	r17,r12
+ 80460d8:	0013883a 	mov	r9,zero
+ 80460dc:	002b883a 	mov	r21,zero
+ 80460e0:	902f883a 	mov	r23,r18
+ 80460e4:	003f4206 	br	8045df0 <___svfiprintf_internal_r+0x5a0>
+ 80460e8:	d8c00317 	ldw	r3,12(sp)
+ 80460ec:	d8000845 	stb	zero,33(sp)
+ 80460f0:	04c00044 	movi	r19,1
+ 80460f4:	18800017 	ldw	r2,0(r3)
+ 80460f8:	18c00104 	addi	r3,r3,4
+ 80460fc:	d8c00315 	stw	r3,12(sp)
+ 8046100:	d8800c05 	stb	r2,48(sp)
+ 8046104:	05400044 	movi	r21,1
+ 8046108:	ddc00c04 	addi	r23,sp,48
+ 804610c:	6023883a 	mov	r17,r12
+ 8046110:	0013883a 	mov	r9,zero
+ 8046114:	003f3e06 	br	8045e10 <___svfiprintf_internal_r+0x5c0>
+ 8046118:	29403fcc 	andi	r5,r5,255
+ 804611c:	2801ec1e 	bne	r5,zero,80468d0 <___svfiprintf_internal_r+0x1080>
+ 8046120:	00c20134 	movhi	r3,2052
+ 8046124:	18dd1b04 	addi	r3,r3,29804
+ 8046128:	d8c00415 	stw	r3,16(sp)
+ 804612c:	60c0080c 	andi	r3,r12,32
+ 8046130:	183edc1e 	bne	r3,zero,8045ca4 <___svfiprintf_internal_r+0x454>
+ 8046134:	d9000317 	ldw	r4,12(sp)
+ 8046138:	60c0040c 	andi	r3,r12,16
+ 804613c:	24c00017 	ldw	r19,0(r4)
+ 8046140:	21000104 	addi	r4,r4,4
+ 8046144:	d9000315 	stw	r4,12(sp)
+ 8046148:	1801481e 	bne	r3,zero,804666c <___svfiprintf_internal_r+0xe1c>
+ 804614c:	60c0100c 	andi	r3,r12,64
+ 8046150:	18014626 	beq	r3,zero,804666c <___svfiprintf_internal_r+0xe1c>
+ 8046154:	9cffffcc 	andi	r19,r19,65535
+ 8046158:	002b883a 	mov	r21,zero
+ 804615c:	003ed606 	br	8045cb8 <___svfiprintf_internal_r+0x468>
+ 8046160:	29403fcc 	andi	r5,r5,255
+ 8046164:	2801dc1e 	bne	r5,zero,80468d8 <___svfiprintf_internal_r+0x1088>
+ 8046168:	6080080c 	andi	r2,r12,32
+ 804616c:	63000414 	ori	r12,r12,16
+ 8046170:	1000591e 	bne	r2,zero,80462d8 <___svfiprintf_internal_r+0xa88>
+ 8046174:	d8800317 	ldw	r2,12(sp)
+ 8046178:	10800104 	addi	r2,r2,4
+ 804617c:	d8c00317 	ldw	r3,12(sp)
+ 8046180:	002b883a 	mov	r21,zero
+ 8046184:	d8800315 	stw	r2,12(sp)
+ 8046188:	1cc00017 	ldw	r19,0(r3)
+ 804618c:	00800044 	movi	r2,1
+ 8046190:	003f0806 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 8046194:	29403fcc 	andi	r5,r5,255
+ 8046198:	2801d11e 	bne	r5,zero,80468e0 <___svfiprintf_internal_r+0x1090>
+ 804619c:	6080080c 	andi	r2,r12,32
+ 80461a0:	63000414 	ori	r12,r12,16
+ 80461a4:	10003e1e 	bne	r2,zero,80462a0 <___svfiprintf_internal_r+0xa50>
+ 80461a8:	d8800317 	ldw	r2,12(sp)
+ 80461ac:	10800104 	addi	r2,r2,4
+ 80461b0:	d8c00317 	ldw	r3,12(sp)
+ 80461b4:	002b883a 	mov	r21,zero
+ 80461b8:	d8800315 	stw	r2,12(sp)
+ 80461bc:	1cc00017 	ldw	r19,0(r3)
+ 80461c0:	0005883a 	mov	r2,zero
+ 80461c4:	003efb06 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 80461c8:	29403fcc 	andi	r5,r5,255
+ 80461cc:	2801c61e 	bne	r5,zero,80468e8 <___svfiprintf_internal_r+0x1098>
+ 80461d0:	6080080c 	andi	r2,r12,32
+ 80461d4:	63000414 	ori	r12,r12,16
+ 80461d8:	1000381e 	bne	r2,zero,80462bc <___svfiprintf_internal_r+0xa6c>
+ 80461dc:	d8800317 	ldw	r2,12(sp)
+ 80461e0:	10800104 	addi	r2,r2,4
+ 80461e4:	d8c00317 	ldw	r3,12(sp)
+ 80461e8:	1cc00017 	ldw	r19,0(r3)
+ 80461ec:	d8800315 	stw	r2,12(sp)
+ 80461f0:	982bd7fa 	srai	r21,r19,31
+ 80461f4:	a805883a 	mov	r2,r21
+ 80461f8:	103fae0e 	bge	r2,zero,80460b4 <___svfiprintf_internal_r+0x864>
+ 80461fc:	04e7c83a 	sub	r19,zero,r19
+ 8046200:	9804c03a 	cmpne	r2,r19,zero
+ 8046204:	056bc83a 	sub	r21,zero,r21
+ 8046208:	a8abc83a 	sub	r21,r21,r2
+ 804620c:	00800b44 	movi	r2,45
+ 8046210:	d8800845 	stb	r2,33(sp)
+ 8046214:	48ffffe0 	cmpeqi	r3,r9,-1
+ 8046218:	03400b44 	movi	r13,45
+ 804621c:	00800044 	movi	r2,1
+ 8046220:	183ee826 	beq	r3,zero,8045dc4 <___svfiprintf_internal_r+0x574>
+ 8046224:	10c00060 	cmpeqi	r3,r2,1
+ 8046228:	1800321e 	bne	r3,zero,80462f4 <___svfiprintf_internal_r+0xaa4>
+ 804622c:	108000a0 	cmpeqi	r2,r2,2
+ 8046230:	1000a41e 	bne	r2,zero,80464c4 <___svfiprintf_internal_r+0xc74>
+ 8046234:	9007883a 	mov	r3,r18
+ 8046238:	00000106 	br	8046240 <___svfiprintf_internal_r+0x9f0>
+ 804623c:	b807883a 	mov	r3,r23
+ 8046240:	9808d0fa 	srli	r4,r19,3
+ 8046244:	a80a977a 	slli	r5,r21,29
+ 8046248:	a82ad0fa 	srli	r21,r21,3
+ 804624c:	9cc001cc 	andi	r19,r19,7
+ 8046250:	98800c04 	addi	r2,r19,48
+ 8046254:	2926b03a 	or	r19,r5,r4
+ 8046258:	18bfffc5 	stb	r2,-1(r3)
+ 804625c:	9d48b03a 	or	r4,r19,r21
+ 8046260:	1dffffc4 	addi	r23,r3,-1
+ 8046264:	203ff51e 	bne	r4,zero,804623c <___svfiprintf_internal_r+0x9ec>
+ 8046268:	6100004c 	andi	r4,r12,1
+ 804626c:	2000a226 	beq	r4,zero,80464f8 <___svfiprintf_internal_r+0xca8>
+ 8046270:	10803fcc 	andi	r2,r2,255
+ 8046274:	1080201c 	xori	r2,r2,128
+ 8046278:	10bfe004 	addi	r2,r2,-128
+ 804627c:	10800c18 	cmpnei	r2,r2,48
+ 8046280:	10009d26 	beq	r2,zero,80464f8 <___svfiprintf_internal_r+0xca8>
+ 8046284:	18ffff84 	addi	r3,r3,-2
+ 8046288:	00800c04 	movi	r2,48
+ 804628c:	b8bfffc5 	stb	r2,-1(r23)
+ 8046290:	90ebc83a 	sub	r21,r18,r3
+ 8046294:	6023883a 	mov	r17,r12
+ 8046298:	182f883a 	mov	r23,r3
+ 804629c:	003ed406 	br	8045df0 <___svfiprintf_internal_r+0x5a0>
+ 80462a0:	d8c00317 	ldw	r3,12(sp)
+ 80462a4:	0005883a 	mov	r2,zero
+ 80462a8:	1cc00017 	ldw	r19,0(r3)
+ 80462ac:	1d400117 	ldw	r21,4(r3)
+ 80462b0:	18c00204 	addi	r3,r3,8
+ 80462b4:	d8c00315 	stw	r3,12(sp)
+ 80462b8:	003ebe06 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 80462bc:	d8c00317 	ldw	r3,12(sp)
+ 80462c0:	18800117 	ldw	r2,4(r3)
+ 80462c4:	1cc00017 	ldw	r19,0(r3)
+ 80462c8:	18c00204 	addi	r3,r3,8
+ 80462cc:	d8c00315 	stw	r3,12(sp)
+ 80462d0:	102b883a 	mov	r21,r2
+ 80462d4:	003f7606 	br	80460b0 <___svfiprintf_internal_r+0x860>
+ 80462d8:	d8c00317 	ldw	r3,12(sp)
+ 80462dc:	00800044 	movi	r2,1
+ 80462e0:	1cc00017 	ldw	r19,0(r3)
+ 80462e4:	1d400117 	ldw	r21,4(r3)
+ 80462e8:	18c00204 	addi	r3,r3,8
+ 80462ec:	d8c00315 	stw	r3,12(sp)
+ 80462f0:	003eb006 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 80462f4:	a801131e 	bne	r21,zero,8046744 <___svfiprintf_internal_r+0xef4>
+ 80462f8:	988002a8 	cmpgeui	r2,r19,10
+ 80462fc:	1001111e 	bne	r2,zero,8046744 <___svfiprintf_internal_r+0xef4>
+ 8046300:	9cc00c04 	addi	r19,r19,48
+ 8046304:	dcc015c5 	stb	r19,87(sp)
+ 8046308:	6023883a 	mov	r17,r12
+ 804630c:	05400044 	movi	r21,1
+ 8046310:	ddc015c4 	addi	r23,sp,87
+ 8046314:	003eb606 	br	8045df0 <___svfiprintf_internal_r+0x5a0>
+ 8046318:	84d9c83a 	sub	r12,r16,r19
+ 804631c:	033ee80e 	bge	zero,r12,8045ec0 <___svfiprintf_internal_r+0x670>
+ 8046320:	61800450 	cmplti	r6,r12,17
+ 8046324:	01c20174 	movhi	r7,2053
+ 8046328:	3001791e 	bne	r6,zero,8046910 <___svfiprintf_internal_r+0x10c0>
+ 804632c:	39ee3c44 	addi	r7,r7,-18191
+ 8046330:	03400404 	movi	r13,16
+ 8046334:	00000406 	br	8046348 <___svfiprintf_internal_r+0xaf8>
+ 8046338:	633ffc04 	addi	r12,r12,-16
+ 804633c:	60c00448 	cmpgei	r3,r12,17
+ 8046340:	42000204 	addi	r8,r8,8
+ 8046344:	18001a26 	beq	r3,zero,80463b0 <___svfiprintf_internal_r+0xb60>
+ 8046348:	21000044 	addi	r4,r4,1
+ 804634c:	10800404 	addi	r2,r2,16
+ 8046350:	41c00015 	stw	r7,0(r8)
+ 8046354:	43400115 	stw	r13,4(r8)
+ 8046358:	d8800b15 	stw	r2,44(sp)
+ 804635c:	d9000a15 	stw	r4,40(sp)
+ 8046360:	20c00208 	cmpgei	r3,r4,8
+ 8046364:	183ff426 	beq	r3,zero,8046338 <___svfiprintf_internal_r+0xae8>
+ 8046368:	d9800904 	addi	r6,sp,36
+ 804636c:	a00b883a 	mov	r5,r20
+ 8046370:	b009883a 	mov	r4,r22
+ 8046374:	d9c00515 	stw	r7,20(sp)
+ 8046378:	db000215 	stw	r12,8(sp)
+ 804637c:	da400115 	stw	r9,4(sp)
+ 8046380:	80456900 	call	8045690 <__ssprint_r>
+ 8046384:	103de51e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8046388:	db000217 	ldw	r12,8(sp)
+ 804638c:	d8800b17 	ldw	r2,44(sp)
+ 8046390:	d9000a17 	ldw	r4,40(sp)
+ 8046394:	633ffc04 	addi	r12,r12,-16
+ 8046398:	60c00448 	cmpgei	r3,r12,17
+ 804639c:	9011883a 	mov	r8,r18
+ 80463a0:	d9c00517 	ldw	r7,20(sp)
+ 80463a4:	03400404 	movi	r13,16
+ 80463a8:	da400117 	ldw	r9,4(sp)
+ 80463ac:	183fe61e 	bne	r3,zero,8046348 <___svfiprintf_internal_r+0xaf8>
+ 80463b0:	21000044 	addi	r4,r4,1
+ 80463b4:	41800204 	addi	r6,r8,8
+ 80463b8:	1305883a 	add	r2,r2,r12
+ 80463bc:	41c00015 	stw	r7,0(r8)
+ 80463c0:	43000115 	stw	r12,4(r8)
+ 80463c4:	d8800b15 	stw	r2,44(sp)
+ 80463c8:	d9000a15 	stw	r4,40(sp)
+ 80463cc:	20c00208 	cmpgei	r3,r4,8
+ 80463d0:	1801161e 	bne	r3,zero,804682c <___svfiprintf_internal_r+0xfdc>
+ 80463d4:	4d53c83a 	sub	r9,r9,r21
+ 80463d8:	21400044 	addi	r5,r4,1
+ 80463dc:	30c00204 	addi	r3,r6,8
+ 80463e0:	3011883a 	mov	r8,r6
+ 80463e4:	027eb80e 	bge	zero,r9,8045ec8 <___svfiprintf_internal_r+0x678>
+ 80463e8:	49800450 	cmplti	r6,r9,17
+ 80463ec:	01c20174 	movhi	r7,2053
+ 80463f0:	30012c1e 	bne	r6,zero,80468a4 <___svfiprintf_internal_r+0x1054>
+ 80463f4:	39ee3c44 	addi	r7,r7,-18191
+ 80463f8:	03000404 	movi	r12,16
+ 80463fc:	00000406 	br	8046410 <___svfiprintf_internal_r+0xbc0>
+ 8046400:	4a7ffc04 	addi	r9,r9,-16
+ 8046404:	48c00448 	cmpgei	r3,r9,17
+ 8046408:	42000204 	addi	r8,r8,8
+ 804640c:	18001826 	beq	r3,zero,8046470 <___svfiprintf_internal_r+0xc20>
+ 8046410:	21000044 	addi	r4,r4,1
+ 8046414:	10800404 	addi	r2,r2,16
+ 8046418:	41c00015 	stw	r7,0(r8)
+ 804641c:	43000115 	stw	r12,4(r8)
+ 8046420:	d8800b15 	stw	r2,44(sp)
+ 8046424:	d9000a15 	stw	r4,40(sp)
+ 8046428:	20c00208 	cmpgei	r3,r4,8
+ 804642c:	183ff426 	beq	r3,zero,8046400 <___svfiprintf_internal_r+0xbb0>
+ 8046430:	d9800904 	addi	r6,sp,36
+ 8046434:	a00b883a 	mov	r5,r20
+ 8046438:	b009883a 	mov	r4,r22
+ 804643c:	d9c00215 	stw	r7,8(sp)
+ 8046440:	da400115 	stw	r9,4(sp)
+ 8046444:	80456900 	call	8045690 <__ssprint_r>
+ 8046448:	103db41e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 804644c:	da400117 	ldw	r9,4(sp)
+ 8046450:	d8800b17 	ldw	r2,44(sp)
+ 8046454:	d9000a17 	ldw	r4,40(sp)
+ 8046458:	4a7ffc04 	addi	r9,r9,-16
+ 804645c:	48c00448 	cmpgei	r3,r9,17
+ 8046460:	9011883a 	mov	r8,r18
+ 8046464:	d9c00217 	ldw	r7,8(sp)
+ 8046468:	03000404 	movi	r12,16
+ 804646c:	183fe81e 	bne	r3,zero,8046410 <___svfiprintf_internal_r+0xbc0>
+ 8046470:	21400044 	addi	r5,r4,1
+ 8046474:	41000204 	addi	r4,r8,8
+ 8046478:	1245883a 	add	r2,r2,r9
+ 804647c:	41c00015 	stw	r7,0(r8)
+ 8046480:	42400115 	stw	r9,4(r8)
+ 8046484:	d8800b15 	stw	r2,44(sp)
+ 8046488:	d9400a15 	stw	r5,40(sp)
+ 804648c:	28c00208 	cmpgei	r3,r5,8
+ 8046490:	1800781e 	bne	r3,zero,8046674 <___svfiprintf_internal_r+0xe24>
+ 8046494:	29400044 	addi	r5,r5,1
+ 8046498:	20c00204 	addi	r3,r4,8
+ 804649c:	2011883a 	mov	r8,r4
+ 80464a0:	003e8906 	br	8045ec8 <___svfiprintf_internal_r+0x678>
+ 80464a4:	d9800904 	addi	r6,sp,36
+ 80464a8:	a00b883a 	mov	r5,r20
+ 80464ac:	b009883a 	mov	r4,r22
+ 80464b0:	80456900 	call	8045690 <__ssprint_r>
+ 80464b4:	103d991e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 80464b8:	d8800b17 	ldw	r2,44(sp)
+ 80464bc:	9007883a 	mov	r3,r18
+ 80464c0:	003e8806 	br	8045ee4 <___svfiprintf_internal_r+0x694>
+ 80464c4:	902f883a 	mov	r23,r18
+ 80464c8:	d9000417 	ldw	r4,16(sp)
+ 80464cc:	988003cc 	andi	r2,r19,15
+ 80464d0:	a806973a 	slli	r3,r21,28
+ 80464d4:	2085883a 	add	r2,r4,r2
+ 80464d8:	9826d13a 	srli	r19,r19,4
+ 80464dc:	10800003 	ldbu	r2,0(r2)
+ 80464e0:	a82ad13a 	srli	r21,r21,4
+ 80464e4:	bdffffc4 	addi	r23,r23,-1
+ 80464e8:	1ce6b03a 	or	r19,r3,r19
+ 80464ec:	b8800005 	stb	r2,0(r23)
+ 80464f0:	9d44b03a 	or	r2,r19,r21
+ 80464f4:	103ff41e 	bne	r2,zero,80464c8 <___svfiprintf_internal_r+0xc78>
+ 80464f8:	95ebc83a 	sub	r21,r18,r23
+ 80464fc:	6023883a 	mov	r17,r12
+ 8046500:	003e3b06 	br	8045df0 <___svfiprintf_internal_r+0x5a0>
+ 8046504:	d9800904 	addi	r6,sp,36
+ 8046508:	a00b883a 	mov	r5,r20
+ 804650c:	b009883a 	mov	r4,r22
+ 8046510:	80456900 	call	8045690 <__ssprint_r>
+ 8046514:	103e7d26 	beq	r2,zero,8045f0c <___svfiprintf_internal_r+0x6bc>
+ 8046518:	003d8006 	br	8045b1c <___svfiprintf_internal_r+0x2cc>
+ 804651c:	8819883a 	mov	r12,r17
+ 8046520:	003f4006 	br	8046224 <___svfiprintf_internal_r+0x9d4>
+ 8046524:	01c20174 	movhi	r7,2053
+ 8046528:	19400450 	cmplti	r5,r3,17
+ 804652c:	39ee4044 	addi	r7,r7,-18175
+ 8046530:	03800404 	movi	r14,16
+ 8046534:	28000526 	beq	r5,zero,804654c <___svfiprintf_internal_r+0xcfc>
+ 8046538:	00002206 	br	80465c4 <___svfiprintf_internal_r+0xd74>
+ 804653c:	18fffc04 	addi	r3,r3,-16
+ 8046540:	19400448 	cmpgei	r5,r3,17
+ 8046544:	42000204 	addi	r8,r8,8
+ 8046548:	28001e26 	beq	r5,zero,80465c4 <___svfiprintf_internal_r+0xd74>
+ 804654c:	21000044 	addi	r4,r4,1
+ 8046550:	10800404 	addi	r2,r2,16
+ 8046554:	41c00015 	stw	r7,0(r8)
+ 8046558:	43800115 	stw	r14,4(r8)
+ 804655c:	d8800b15 	stw	r2,44(sp)
+ 8046560:	d9000a15 	stw	r4,40(sp)
+ 8046564:	21400208 	cmpgei	r5,r4,8
+ 8046568:	283ff426 	beq	r5,zero,804653c <___svfiprintf_internal_r+0xcec>
+ 804656c:	d9800904 	addi	r6,sp,36
+ 8046570:	a00b883a 	mov	r5,r20
+ 8046574:	b009883a 	mov	r4,r22
+ 8046578:	d9c00715 	stw	r7,28(sp)
+ 804657c:	d8c00615 	stw	r3,24(sp)
+ 8046580:	da400515 	stw	r9,20(sp)
+ 8046584:	db000215 	stw	r12,8(sp)
+ 8046588:	db400115 	stw	r13,4(sp)
+ 804658c:	80456900 	call	8045690 <__ssprint_r>
+ 8046590:	103d621e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8046594:	d8c00617 	ldw	r3,24(sp)
+ 8046598:	d8800b17 	ldw	r2,44(sp)
+ 804659c:	d9000a17 	ldw	r4,40(sp)
+ 80465a0:	18fffc04 	addi	r3,r3,-16
+ 80465a4:	19400448 	cmpgei	r5,r3,17
+ 80465a8:	9011883a 	mov	r8,r18
+ 80465ac:	d9c00717 	ldw	r7,28(sp)
+ 80465b0:	03800404 	movi	r14,16
+ 80465b4:	da400517 	ldw	r9,20(sp)
+ 80465b8:	db000217 	ldw	r12,8(sp)
+ 80465bc:	db400117 	ldw	r13,4(sp)
+ 80465c0:	283fe21e 	bne	r5,zero,804654c <___svfiprintf_internal_r+0xcfc>
+ 80465c4:	21000044 	addi	r4,r4,1
+ 80465c8:	10c5883a 	add	r2,r2,r3
+ 80465cc:	40c00115 	stw	r3,4(r8)
+ 80465d0:	41c00015 	stw	r7,0(r8)
+ 80465d4:	d8800b15 	stw	r2,44(sp)
+ 80465d8:	d9000a15 	stw	r4,40(sp)
+ 80465dc:	20c00208 	cmpgei	r3,r4,8
+ 80465e0:	1800751e 	bne	r3,zero,80467b8 <___svfiprintf_internal_r+0xf68>
+ 80465e4:	42000204 	addi	r8,r8,8
+ 80465e8:	003e1206 	br	8045e34 <___svfiprintf_internal_r+0x5e4>
+ 80465ec:	d9800904 	addi	r6,sp,36
+ 80465f0:	a00b883a 	mov	r5,r20
+ 80465f4:	b009883a 	mov	r4,r22
+ 80465f8:	da400515 	stw	r9,20(sp)
+ 80465fc:	db000215 	stw	r12,8(sp)
+ 8046600:	db400115 	stw	r13,4(sp)
+ 8046604:	80456900 	call	8045690 <__ssprint_r>
+ 8046608:	103d441e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 804660c:	d9000a17 	ldw	r4,40(sp)
+ 8046610:	d8800b17 	ldw	r2,44(sp)
+ 8046614:	d8c01804 	addi	r3,sp,96
+ 8046618:	21400044 	addi	r5,r4,1
+ 804661c:	9011883a 	mov	r8,r18
+ 8046620:	da400517 	ldw	r9,20(sp)
+ 8046624:	db000217 	ldw	r12,8(sp)
+ 8046628:	db400117 	ldw	r13,4(sp)
+ 804662c:	003e1406 	br	8045e80 <___svfiprintf_internal_r+0x630>
+ 8046630:	d9800904 	addi	r6,sp,36
+ 8046634:	a00b883a 	mov	r5,r20
+ 8046638:	b009883a 	mov	r4,r22
+ 804663c:	da400215 	stw	r9,8(sp)
+ 8046640:	db000115 	stw	r12,4(sp)
+ 8046644:	80456900 	call	8045690 <__ssprint_r>
+ 8046648:	103d341e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 804664c:	d9000a17 	ldw	r4,40(sp)
+ 8046650:	d8800b17 	ldw	r2,44(sp)
+ 8046654:	d8c01804 	addi	r3,sp,96
+ 8046658:	21400044 	addi	r5,r4,1
+ 804665c:	9011883a 	mov	r8,r18
+ 8046660:	da400217 	ldw	r9,8(sp)
+ 8046664:	db000117 	ldw	r12,4(sp)
+ 8046668:	003e1306 	br	8045eb8 <___svfiprintf_internal_r+0x668>
+ 804666c:	002b883a 	mov	r21,zero
+ 8046670:	003d9106 	br	8045cb8 <___svfiprintf_internal_r+0x468>
+ 8046674:	d9800904 	addi	r6,sp,36
+ 8046678:	a00b883a 	mov	r5,r20
+ 804667c:	b009883a 	mov	r4,r22
+ 8046680:	80456900 	call	8045690 <__ssprint_r>
+ 8046684:	103d251e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8046688:	d9000a17 	ldw	r4,40(sp)
+ 804668c:	d8800b17 	ldw	r2,44(sp)
+ 8046690:	d8c01804 	addi	r3,sp,96
+ 8046694:	21400044 	addi	r5,r4,1
+ 8046698:	9011883a 	mov	r8,r18
+ 804669c:	003e0a06 	br	8045ec8 <___svfiprintf_internal_r+0x678>
+ 80466a0:	e023883a 	mov	r17,fp
+ 80466a4:	003ca306 	br	8045934 <___svfiprintf_internal_r+0xe4>
+ 80466a8:	902f883a 	mov	r23,r18
+ 80466ac:	003dd006 	br	8045df0 <___svfiprintf_internal_r+0x5a0>
+ 80466b0:	d9400017 	ldw	r5,0(sp)
+ 80466b4:	20800017 	ldw	r2,0(r4)
+ 80466b8:	d8c00315 	stw	r3,12(sp)
+ 80466bc:	2809d7fa 	srai	r4,r5,31
+ 80466c0:	11400015 	stw	r5,0(r2)
+ 80466c4:	11000115 	stw	r4,4(r2)
+ 80466c8:	003c7c06 	br	80458bc <___svfiprintf_internal_r+0x6c>
+ 80466cc:	00c00c04 	movi	r3,48
+ 80466d0:	d88008c5 	stb	r2,35(sp)
+ 80466d4:	d8c00885 	stb	r3,34(sp)
+ 80466d8:	63000094 	ori	r12,r12,2
+ 80466dc:	00800084 	movi	r2,2
+ 80466e0:	003db406 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 80466e4:	b809883a 	mov	r4,r23
+ 80466e8:	da000215 	stw	r8,8(sp)
+ 80466ec:	db000115 	stw	r12,4(sp)
+ 80466f0:	8002dac0 	call	8002dac <strlen>
+ 80466f4:	102b883a 	mov	r21,r2
+ 80466f8:	1027883a 	mov	r19,r2
+ 80466fc:	dc400315 	stw	r17,12(sp)
+ 8046700:	db000117 	ldw	r12,4(sp)
+ 8046704:	da000217 	ldw	r8,8(sp)
+ 8046708:	003e8006 	br	804610c <___svfiprintf_internal_r+0x8bc>
+ 804670c:	01401004 	movi	r5,64
+ 8046710:	8007ddc0 	call	8007ddc <_malloc_r>
+ 8046714:	a0800015 	stw	r2,0(r20)
+ 8046718:	a0800415 	stw	r2,16(r20)
+ 804671c:	10008f26 	beq	r2,zero,804695c <___svfiprintf_internal_r+0x110c>
+ 8046720:	00801004 	movi	r2,64
+ 8046724:	a0800515 	stw	r2,20(r20)
+ 8046728:	003c5d06 	br	80458a0 <___svfiprintf_internal_r+0x50>
+ 804672c:	d8800317 	ldw	r2,12(sp)
+ 8046730:	10800017 	ldw	r2,0(r2)
+ 8046734:	d8c00315 	stw	r3,12(sp)
+ 8046738:	d8c00017 	ldw	r3,0(sp)
+ 804673c:	10c00015 	stw	r3,0(r2)
+ 8046740:	003c5e06 	br	80458bc <___svfiprintf_internal_r+0x6c>
+ 8046744:	902f883a 	mov	r23,r18
+ 8046748:	00000206 	br	8046754 <___svfiprintf_internal_r+0xf04>
+ 804674c:	1027883a 	mov	r19,r2
+ 8046750:	182b883a 	mov	r21,r3
+ 8046754:	9809883a 	mov	r4,r19
+ 8046758:	a80b883a 	mov	r5,r21
+ 804675c:	01800284 	movi	r6,10
+ 8046760:	000f883a 	mov	r7,zero
+ 8046764:	db400615 	stw	r13,24(sp)
+ 8046768:	da000515 	stw	r8,20(sp)
+ 804676c:	da400215 	stw	r9,8(sp)
+ 8046770:	db000115 	stw	r12,4(sp)
+ 8046774:	800c9c00 	call	800c9c0 <__umoddi3>
+ 8046778:	10800c04 	addi	r2,r2,48
+ 804677c:	bdffffc4 	addi	r23,r23,-1
+ 8046780:	9809883a 	mov	r4,r19
+ 8046784:	a80b883a 	mov	r5,r21
+ 8046788:	b8800005 	stb	r2,0(r23)
+ 804678c:	01800284 	movi	r6,10
+ 8046790:	000f883a 	mov	r7,zero
+ 8046794:	800c4280 	call	800c428 <__udivdi3>
+ 8046798:	db000117 	ldw	r12,4(sp)
+ 804679c:	da400217 	ldw	r9,8(sp)
+ 80467a0:	da000517 	ldw	r8,20(sp)
+ 80467a4:	db400617 	ldw	r13,24(sp)
+ 80467a8:	a83fe81e 	bne	r21,zero,804674c <___svfiprintf_internal_r+0xefc>
+ 80467ac:	9cc002a8 	cmpgeui	r19,r19,10
+ 80467b0:	983fe61e 	bne	r19,zero,804674c <___svfiprintf_internal_r+0xefc>
+ 80467b4:	003f5006 	br	80464f8 <___svfiprintf_internal_r+0xca8>
+ 80467b8:	d9800904 	addi	r6,sp,36
+ 80467bc:	a00b883a 	mov	r5,r20
+ 80467c0:	b009883a 	mov	r4,r22
+ 80467c4:	da400515 	stw	r9,20(sp)
+ 80467c8:	db000215 	stw	r12,8(sp)
+ 80467cc:	db400115 	stw	r13,4(sp)
+ 80467d0:	80456900 	call	8045690 <__ssprint_r>
+ 80467d4:	103cd11e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 80467d8:	d8800b17 	ldw	r2,44(sp)
+ 80467dc:	d9000a17 	ldw	r4,40(sp)
+ 80467e0:	9011883a 	mov	r8,r18
+ 80467e4:	da400517 	ldw	r9,20(sp)
+ 80467e8:	db000217 	ldw	r12,8(sp)
+ 80467ec:	db400117 	ldw	r13,4(sp)
+ 80467f0:	003d9006 	br	8045e34 <___svfiprintf_internal_r+0x5e4>
+ 80467f4:	0421c83a 	sub	r16,zero,r16
+ 80467f8:	ddc00315 	stw	r23,12(sp)
+ 80467fc:	003d0106 	br	8045c04 <___svfiprintf_internal_r+0x3b4>
+ 8046800:	10c00060 	cmpeqi	r3,r2,1
+ 8046804:	8819883a 	mov	r12,r17
+ 8046808:	183e8826 	beq	r3,zero,804622c <___svfiprintf_internal_r+0x9dc>
+ 804680c:	003ebc06 	br	8046300 <___svfiprintf_internal_r+0xab0>
+ 8046810:	e0800043 	ldbu	r2,1(fp)
+ 8046814:	63000814 	ori	r12,r12,32
+ 8046818:	e7000044 	addi	fp,fp,1
+ 804681c:	10803fcc 	andi	r2,r2,255
+ 8046820:	1080201c 	xori	r2,r2,128
+ 8046824:	10bfe004 	addi	r2,r2,-128
+ 8046828:	003c4a06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 804682c:	d9800904 	addi	r6,sp,36
+ 8046830:	a00b883a 	mov	r5,r20
+ 8046834:	b009883a 	mov	r4,r22
+ 8046838:	da400115 	stw	r9,4(sp)
+ 804683c:	80456900 	call	8045690 <__ssprint_r>
+ 8046840:	103cb61e 	bne	r2,zero,8045b1c <___svfiprintf_internal_r+0x2cc>
+ 8046844:	d9000a17 	ldw	r4,40(sp)
+ 8046848:	d8800b17 	ldw	r2,44(sp)
+ 804684c:	d8c01804 	addi	r3,sp,96
+ 8046850:	21400044 	addi	r5,r4,1
+ 8046854:	9011883a 	mov	r8,r18
+ 8046858:	da400117 	ldw	r9,4(sp)
+ 804685c:	003d9806 	br	8045ec0 <___svfiprintf_internal_r+0x670>
+ 8046860:	488001f0 	cmpltui	r2,r9,7
+ 8046864:	482b883a 	mov	r21,r9
+ 8046868:	1000011e 	bne	r2,zero,8046870 <___svfiprintf_internal_r+0x1020>
+ 804686c:	05400184 	movi	r21,6
+ 8046870:	05c20134 	movhi	r23,2052
+ 8046874:	a827883a 	mov	r19,r21
+ 8046878:	dc400315 	stw	r17,12(sp)
+ 804687c:	bddd2504 	addi	r23,r23,29844
+ 8046880:	003e2206 	br	804610c <___svfiprintf_internal_r+0x8bc>
+ 8046884:	d8800315 	stw	r2,12(sp)
+ 8046888:	002b883a 	mov	r21,zero
+ 804688c:	0005883a 	mov	r2,zero
+ 8046890:	003d4806 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 8046894:	d8800315 	stw	r2,12(sp)
+ 8046898:	002b883a 	mov	r21,zero
+ 804689c:	00800044 	movi	r2,1
+ 80468a0:	003d4406 	br	8045db4 <___svfiprintf_internal_r+0x564>
+ 80468a4:	1809883a 	mov	r4,r3
+ 80468a8:	39ee3c44 	addi	r7,r7,-18191
+ 80468ac:	003ef206 	br	8046478 <___svfiprintf_internal_r+0xc28>
+ 80468b0:	d9800845 	stb	r6,33(sp)
+ 80468b4:	003cb706 	br	8045b94 <___svfiprintf_internal_r+0x344>
+ 80468b8:	4827883a 	mov	r19,r9
+ 80468bc:	dc400315 	stw	r17,12(sp)
+ 80468c0:	482b883a 	mov	r21,r9
+ 80468c4:	003e1106 	br	804610c <___svfiprintf_internal_r+0x8bc>
+ 80468c8:	d9800845 	stb	r6,33(sp)
+ 80468cc:	003cf006 	br	8045c90 <___svfiprintf_internal_r+0x440>
+ 80468d0:	d9800845 	stb	r6,33(sp)
+ 80468d4:	003e1206 	br	8046120 <___svfiprintf_internal_r+0x8d0>
+ 80468d8:	d9800845 	stb	r6,33(sp)
+ 80468dc:	003e2206 	br	8046168 <___svfiprintf_internal_r+0x918>
+ 80468e0:	d9800845 	stb	r6,33(sp)
+ 80468e4:	003e2d06 	br	804619c <___svfiprintf_internal_r+0x94c>
+ 80468e8:	d9800845 	stb	r6,33(sp)
+ 80468ec:	003e3806 	br	80461d0 <___svfiprintf_internal_r+0x980>
+ 80468f0:	d9800845 	stb	r6,33(sp)
+ 80468f4:	003de106 	br	804607c <___svfiprintf_internal_r+0x82c>
+ 80468f8:	d9800845 	stb	r6,33(sp)
+ 80468fc:	003cf606 	br	8045cd8 <___svfiprintf_internal_r+0x488>
+ 8046900:	d9800845 	stb	r6,33(sp)
+ 8046904:	003dc506 	br	804601c <___svfiprintf_internal_r+0x7cc>
+ 8046908:	d9800845 	stb	r6,33(sp)
+ 804690c:	003db306 	br	8045fdc <___svfiprintf_internal_r+0x78c>
+ 8046910:	180d883a 	mov	r6,r3
+ 8046914:	2809883a 	mov	r4,r5
+ 8046918:	39ee3c44 	addi	r7,r7,-18191
+ 804691c:	003ea606 	br	80463b8 <___svfiprintf_internal_r+0xb68>
+ 8046920:	00bfffc4 	movi	r2,-1
+ 8046924:	d8800015 	stw	r2,0(sp)
+ 8046928:	003c7f06 	br	8045b28 <___svfiprintf_internal_r+0x2d8>
+ 804692c:	d8800317 	ldw	r2,12(sp)
+ 8046930:	12400017 	ldw	r9,0(r2)
+ 8046934:	15c00104 	addi	r23,r2,4
+ 8046938:	4800010e 	bge	r9,zero,8046940 <___svfiprintf_internal_r+0x10f0>
+ 804693c:	027fffc4 	movi	r9,-1
+ 8046940:	e0800043 	ldbu	r2,1(fp)
+ 8046944:	ddc00315 	stw	r23,12(sp)
+ 8046948:	2039883a 	mov	fp,r4
+ 804694c:	10803fcc 	andi	r2,r2,255
+ 8046950:	1080201c 	xori	r2,r2,128
+ 8046954:	10bfe004 	addi	r2,r2,-128
+ 8046958:	003bfe06 	br	8045954 <___svfiprintf_internal_r+0x104>
+ 804695c:	00800304 	movi	r2,12
+ 8046960:	b0800015 	stw	r2,0(r22)
+ 8046964:	00bfffc4 	movi	r2,-1
+ 8046968:	d8800015 	stw	r2,0(sp)
+ 804696c:	003c6e06 	br	8045b28 <___svfiprintf_internal_r+0x2d8>
+
+08046970 <_vfprintf_r>:
+ 8046970:	8002e441 	jmpi	8002e44 <___vfprintf_internal_r>
+
+08046974 <_exit>:
+ *
+ * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h
+ */
+
+void ALT_EXIT (int exit_code)
+{
+ 8046974:	defffd04 	addi	sp,sp,-12
+ 8046978:	df000215 	stw	fp,8(sp)
+ 804697c:	df000204 	addi	fp,sp,8
+ 8046980:	e13ffe15 	stw	r4,-8(fp)
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n");
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code);
+  /* Stop all other threads */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n");
+  ALT_OS_STOP();
+ 8046984:	d0204b45 	stb	zero,-32467(gp)
+ 8046988:	e0bffe17 	ldw	r2,-8(fp)
+ 804698c:	e0bfff15 	stw	r2,-4(fp)
+/*
+ * Routine called on exit.
+ */
+static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code)
+{
+  register int r2 asm ("r2") = exit_code;
+ 8046990:	e0bfff17 	ldw	r2,-4(fp)
+  __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */
+
+  __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA );
+
+#else /* !DEBUG_STUB */
+  if (r2) {
+ 8046994:	10000226 	beq	r2,zero,80469a0 <_exit+0x2c>
+    ALT_SIM_FAIL();
+ 8046998:	002af070 	cmpltui	zero,zero,43969
+ 804699c:	00000106 	br	80469a4 <_exit+0x30>
+  } else {
+    ALT_SIM_PASS();
+ 80469a0:	002af0b0 	cmpltui	zero,zero,43970
+  ALT_SIM_HALT(exit_code);
+
+  /* spin forever, since there's no where to go back to */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n");
+  while (1);
+ 80469a4:	003fff06 	br	80469a4 <_exit+0x30>
diff --git a/FPGA_nios/hit_pat/inc/control.h b/FPGA_nios/hit_pat/inc/control.h
new file mode 100644
index 0000000..12a69f3
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/control.h
@@ -0,0 +1,39 @@
+/*
+ * control.h
+ *
+ *  Created on: Aug 14, 2017
+ *      Author: mdziewiecki
+ */
+
+#ifndef CONTROL_H_
+#define CONTROL_H_
+
+//**************************
+
+#include "dev_commands.h"
+
+//**************************
+
+#define CONTROL_TASK_PRIORITY		10
+#define CONTROL_STACK_SIZE			(6144+8192)
+
+#define CONTROL_MAX_DATA_LENGTH		16		//maximum command data length in WORDS (16-bit)
+#define CONTROL_TIMEOUT				1000	//timeout to get command data in unknown time units
+
+#define CONTROL_PORT				4000
+#define DATA_PORT					4001
+
+#define CONTROL_SWAP_BYTES 			1		//playing around endianness in PC communication
+
+typedef struct
+{
+	unsigned short marker;	//must be 0x5555
+	unsigned short command;
+	unsigned short length;
+} command_header;
+
+	//Initialize control task
+void control_init();
+
+
+#endif /* CONTROL_H_ */
diff --git a/FPGA_nios/hit_pat/inc/dev_commands.h b/FPGA_nios/hit_pat/inc/dev_commands.h
new file mode 100644
index 0000000..378fef7
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/dev_commands.h
@@ -0,0 +1,136 @@
+#ifndef DEV_COMMANDS_H
+#define DEV_COMMANDS_H
+
+//This file is derived from v.1 version and it's great if it's kept compatible
+//All sizes are in HALF-WORDS (16-bit)!
+
+#define COMMAND_PING				0x0001
+    //L: 0
+    //D: []
+    //Return the same
+
+#define COMMAND_DEBUG_LED_OFF		0x0010
+    //L: 0
+    //D: [];
+    //Turn off LED 0
+
+#define COMMAND_DEBUG_LED_ON		0x0011
+    //L: 0
+    //D: [];
+    //Turn on LED 0
+
+// ***DEVICE CONTROL***
+
+#define COMMAND_LEDS_DISABLE		0x0110
+    //L: 0
+    //D: [];
+    //Disable LED4 blinking. Other LEDs must be explicitly switched off
+
+#define COMMAND_LEDS_ENABLE			0x0111
+    //L: 0
+    //D: [];
+    //Enable LED4 blinking
+
+// ***TRIGGER SETTING***
+
+#define COMMAND_TRIGGER_DISABLE		0x0210
+    //L: 0
+    //D: [];
+    //Disable trigger generation in master mode
+
+#define COMMAND_TRIGGER_ENABLE		0x0211
+    //L: 0
+    //D: [];
+    //Enable trigger generation in master mode
+
+#define COMMAND_TRIGGER_SET_SLAVE	0x0220
+    //L: 0
+    //D: [];
+    //Set trigger to slave mode
+
+#define COMMAND_TRIGGER_SET_MASTER	0x0221
+    //L: 0
+    //D: [];
+    //Set trigger to master mode
+
+#define COMMAND_TRIGGER_SET_PERIOD	0x0230
+    //L: 1											L: 0
+    //D: [Period_ticks]								D: []
+    //Set trigger period for master mode in timer ticks
+
+#define COMMAND_TRIGGER_SET_TINT	0x0240
+    //L: 1											L: 0
+    //D: [Tint_ticks]								D: []
+    //Set integration time in timer ticks
+
+#define COMMAND_SET_GAIN            0x0250
+    //L: 1                                          L:0
+    //D: [gain]                                     D: []
+
+#define COMMAND_TRIGGER_SET_MASTER_DELAY	0x0260
+    //L: 1											L: 0
+    //D: [Tdelay_ticks]								D: []
+    //Set trigger delay time in timer ticks for master mode.
+
+#define COMMAND_TRIGGER_SET_SLAVE_DELAY		0x0270
+    //L: 1											L: 0
+    //D: [Tdelay_ticks]								D: []
+    //Set trigger delay time in timer ticks for slave mode.
+
+
+// ***DAQ CONTROL***
+
+#define COMMAND_DAQ_DISABLE			0x0310
+    //L: 0
+    //D: [];
+    //Disable sending data
+
+#define COMMAND_DAQ_ENABLE			0x0311
+    //L: 0
+    //D: [];
+    //Enable sending data
+
+#define COMMAND_DAQ_RESET_COUNTERS	0x0321
+    //L: 0
+    //D: []
+    //Reset synchronization counters
+
+#define COMMAND_DAQ_FLUSH_DATA		0x0322
+    //L: 0
+    //D: []
+    //Send all remaining data over data socket
+
+#define COMMAND_DAQ_CONFIG_PEER		0x0331
+    //L: 5											L: 0
+    //D: [ip ip ip ip port]							D: []
+    //Set connection settings (peer IP and port) for data transfer
+    //Warning: IP is sent as 4 shorts with MSB=0!
+
+// ***SLOW CONTROL***
+
+#define COMMAND_SLOWCTRL_SNAPSHOT	0x0410
+	//L: 0											L: 10
+	//D:[]											D: [(Readout of 5 ADC channels as 32-bit integers)]
+	//Slow control snapshot - read all channels of ADC
+
+
+// ***DATA TRANSFER - SOCKET 1!!!!***
+
+#define COMMAND_DATA_TRANSFER		0x8000
+	//(no incoming packet)							L: 64*5*2 + 6
+	//(no incoming packet)							D: [Read out single frame]
+
+
+// *** SET_CLUSTER_THRESHOLD *** //
+#define COMMAND_SET_CLUSTER_THRESHOLD 0x4001
+	//L: 1
+#define COMMAND_SET_CLUSTER_SIZE 	  0x4002
+	//L: 1
+#define COMMAND_SET_CALIBRATION_FACTOR 0x4003
+	//L: 2* 16bit
+
+
+
+
+
+#endif // DEV_COMMANDS_H
diff --git a/FPGA_nios/hit_pat/inc/network_utilities.h b/FPGA_nios/hit_pat/inc/network_utilities.h
new file mode 100644
index 0000000..635bc05
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/network_utilities.h
@@ -0,0 +1,49 @@
+/******************************************************************************
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved. All use of this software and documentation is          *
+* subject to the License Agreement located at the end of this file below.     *
+******************************************************************************
+* Date - October 24, 2006                                                     *
+* Module - network_utilities.h                                                *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __NETWORK_UTILITIES_H__
+#define __NETWORK_UTILITIES_H__
+
+#include <errno.h>
+
+error_t get_board_mac_addr(unsigned char mac_addr[6]);
+
+#endif /*__NETWORK_UTILITIES_H__ */
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
diff --git a/FPGA_nios/hit_pat/inc/sensor.h b/FPGA_nios/hit_pat/inc/sensor.h
new file mode 100644
index 0000000..6338921
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/sensor.h
@@ -0,0 +1,67 @@
+/*
+ * sensor.h
+ *
+ *  Created on: Aug 19, 2019
+ *      Author: mdziewiecki
+ */
+
+#ifndef SENSOR_H_
+#define SENSOR_H_
+
+//SENSOR_INTERFACE_BASE	- this is the base address of the interface
+
+		//byte offsets for registers
+		#define SENSOR_REG_COMMAND				0		//8 bits
+		#define SENSOR_REG_STATUS				1		//8 bits
+		#define SENSOR_REG_SENSORCLK			2		//16 bits, 6 used	divider for producing sensor clock ('4' MHz)
+		#define SESNOR_REG_ADCCNV				3		//8 bits,  6 used	time of conversion pulse in ADC clocks, should be > 500 ns
+		#define SENSOR_REG_DELAY				4		//16 bits, 12 used	reset signal delay in 50 MHz clocks
+		#define SENSOR_REG_SHUTTER				6		//16 bits, 12 used	sensor reset ('shutter') time in sensor clocks
+		#define SENSOR_REG_SERSPEED				8		//8 bits 		synchro baudrate, 50 for 1 Mbps
+		#define SENSOR_REG_HEADER_ANYDATA		9		//8 bits		any data transmitted with SMA state (8 bits SMA + 8 bits anydata)
+		#define SENSOR_REG_HEADER_CMD			10		//16 bits 		command field of the command header transmitted in packet
+		#define SENSOR_REG_CLUSTER_THRESHOLD	12 //8 bits	 the threshold for cluster locate, range 0~255
+		#define SENSOR_REG_CLUSTER_SIZE			13 //8 bits  the size for clluster locate, range 0~255
+		#define SENSOR_REG_IN_ALGO_THRESHOLD	14 //8 bits	 the threshold inside Linear Regression, range 0~255
+		#define SENSOR_REG_RESERVED				15 //8 bits  not used
+
+		//CSR bitmasks
+		#define SENSOR_CSR_EN_BITMASK			0x01	//enable operation
+		#define SENSOR_CSR_GAIN_BITMASK			0x02	//gain selection
+		#define SENSOR_CSR_ADCK_BITMASK 		0x04	//ADC clock divider on/off
+		#define SENSOR_CSR_RESET_BITMASK		0x08	//Reset all logic
+
+		//Status bitmasks
+		#define SENSOR_STATUS_SEND				0x01	//Sending over Avalon-ST
+		#define SENSOR_STATUS_TRG_WAITING		0x02	//The trigger came and is being delayed now
+		#define SENSOR_STATUS_RESET_ACTIVE		0x04	//The RESET signal for the sensor is active now
+		#define SENSOR_STATUS_ADC_ACTIVE		0x08	//The ADC is converting data (signal high over all 64 channels) or just finished and waits for reset high
+		#define SESNOR_STATUS_ADC_FINISHED		0x10	//The ADC waits for reset high
+		#define SESNOR_STATUS_TX_ACTIVE			0x20	//Sync port is sending
+		#define SESNOR_STATUS_RX_ACTIVE			0x40	//Sync port is receiving
+
+
+	//Register access functions/macros
+void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state);
+#define sensor_command(base, val) 				IOWR_8DIRECT(base, SENSOR_REG_COMMAND, val)
+#define sensor_set_enable(base, val)			sensor_command_bit(base, SENSOR_CSR_EN_BITMASK, val);
+#define sensor_set_gain(base, val)				sensor_command_bit(base, SENSOR_CSR_GAIN_BITMASK, val);
+#define sensor_set_adck(base, val)				sensor_command_bit(base, SENSOR_CSR_ADCK_BITMASK, val);
+#define sensor_reset(base)						{ sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,1); sensor_command_bit(base,SENSOR_CSR_RESET_BITMASK,0); }
+#define sensor_set_sensorclk(base, val)			IOWR_8DIRECT(base, SENSOR_REG_SENSORCLK, val)
+#define sensor_set_adccnv(base, val)			IOWR_8DIRECT(base, SESNOR_REG_ADCCNV, val)
+#define sensor_set_delay(base, val)				IOWR_16DIRECT(base, SENSOR_REG_DELAY, val)
+#define sensor_set_shutter(base, val)			IOWR_16DIRECT(base, SENSOR_REG_SHUTTER, val)
+#define sensor_set_serspeed(base, val)			IOWR_8DIRECT(base, SENSOR_REG_SERSPEED, val)
+#define sensor_set_header_anydata(base, val)	IOWR_8DIRECT(base, SENSOR_REG_HEADER_ANYDATA, val)
+#define sensor_set_header_cmd(base, val)		IOWR_16DIRECT(base, SENSOR_REG_HEADER_CMD, val)
+#define sensor_set_cluster_threshold(base, val)	IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_THRESHOLD, val)
+#define sensor_set_cluster_size(base, val)		IOWR_8DIRECT(base, SENSOR_REG_CLUSTER_SIZE, val)
+#define sensor_set_in_algo_threshold(base, val)	IOWR_8DIRECT(base, SENSOR_REG_IN_ALGO_THRESHOLD, val)
+
+//write calibration factor: CALIBRATION_RAM_BASE
+#define calibration_ram_set_factor(base, channelID, val) IOWR_16DIRECT(base, channelID*2, val)
+
+void sensor_preconfigure(alt_u32 base);
+
+#endif /* SENSOR_H_ */
diff --git a/FPGA_nios/hit_pat/inc/socket_server.h b/FPGA_nios/hit_pat/inc/socket_server.h
new file mode 100644
index 0000000..5a9c8ed
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/socket_server.h
@@ -0,0 +1,144 @@
+/******************************************************************************
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved. All use of this software and documentation is          *
+* subject to the License Agreement located at the end of this file below.     *
+*******************************************************************************                                                                             *
+* Date - October 24, 2006                                                     *
+* Module - simple_socket_server.h                                             *
+* EXTENSIVELY REWRITTEN by M.D. 2019                                                                            *                                                                             *
+******************************************************************************/
+
+/*
+	SO THIS IS HOW IT WORKS:
+
+	User can use up to NR_CHANNELS sockets.
+	First, ethernet_init() must be called from any task.
+	It will start a special 'listener' thread which is responsible for serving connection requests.
+	Then:
+	For each 'channel' (a placeholder for one socket), user may call ethernet_listen() to start listening on a specified port.
+	After that, ethernet_read() and ethernet_write() can be used. These functions are non-blocking and return 0 if no client is connected.
+	User can explicitly close connection to a client by calling ethernet_close();
+	If another connection request comes when a client is already connected, the old client will be disconnected in favor of the new one.
+	It means, that only one client can be connected to one channel at a given time.
+	This weird behaviour is implemented to enable easy killing 'hanging' connections.
+	Channel re-configuration (i.e. repeated calls of ethernet_listen() for the same channel) is not allowed.
+	VERY IMPORTANT:
+	All the above functions (excluding ethernet_init()) must be called from a socket-compatible thread (created with TK_NEWTASK).
+	All ethernet_* calls are served directly in user's task. Ethernet_init() can be called from any thread after hardware configuration.
+ */
+
+ /* Validate supported Software components specified on system library properties page.
+  */
+#ifndef __SOCKET_SERVER_H__
+#define __SOCKET_SERVER_H__
+
+#if !defined (ALT_INICHE)
+  #error The Simple Socket Server example requires the 
+  #error NicheStack TCP/IP Stack Software Component. Please see the Nichestack
+  #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition,
+  #error including notes on migrating applications from lwIP to NicheStack.
+#endif
+
+#ifndef __ucosii__
+  #error This Simple Socket Server example requires 
+  #error the MicroC/OS-II Intellectual Property Software Component.
+#endif
+
+#if defined (ALT_LWIP)
+  #error The Simple Socket Server example requires the 
+  #error NicheStack TCP/IP Stack Software Component, and no longer works
+  #error with the lwIP networking stack.  Please see the Altera Nichstack
+  #error Tutorial for details on Nichestack TCP/IP Stack - Nios II Edition,
+  #error including notes on migrating applications from lwIP to NicheStack.
+#endif
+
+
+
+
+/*
+ *  Task Priorities:
+ *  MicroC/OS-II only allows one task (thread) per priority number.   
+ */
+#define SS_LISTENER_TASK_PRIORITY  	9	//Also, another priority just below this one will be reserved for mutex
+#define SS_LISTENER_STACK_SIZE		(6144+8192)
+
+#define NR_CHANNELS 1	//number of listening sockets - as in Wiznet
+						//Each socket listens on its own port and is able to open one "talking" connection at a time
+						//If a new connection request comes, the old one gets preempted. This allows us killing dead connections.
+
+
+/*
+ * If DHCP will not be used, select valid static _BASE_ IP addresses here:
+ *  The contents of DIPSW[3:0] will be added to the last byte of the IP.
+ *  DIPSW[4] is used to enable/disable DHCP.
+ */
+#define IPADDR0   10
+#define IPADDR1   0
+#define IPADDR2   7
+#define IPADDR3   16
+
+#define GWADDR0   10
+#define GWADDR1   0
+#define GWADDR2   7
+#define GWADDR3   1
+
+#define MSKADDR0  255
+#define MSKADDR1  255
+#define MSKADDR2  255
+#define MSKADDR3  0
+
+
+/* 
+ * Here we structure to manage sss communication for a single connection
+ */
+typedef struct SS_SOCKET
+{
+  enum { FREE, LISTENING, CONNECTED} state;
+  int 		fd_listen;
+  int       fd_conn;
+  int 		listenport;
+} SSConn;
+
+// *** User's interface ***
+
+int ethernet_init();
+/*REMARK: All the below functions can be used ONLY:
+	1: After ethernet_init();
+	2: From a task created by TK_NEWTASK. */
+int ethernet_listen(int channel, int port);						//Remark: Once we listen on a port, we can not change it
+int ethernet_write(int channel, int size, unsigned char* data);
+int ethernet_read(int channel, int size, unsigned char* data);	//Non-blocking. Returns the number of characters read.
+int ethernet_close(int channel);
+
+#endif /* __SOCKET_SERVER_H__ */
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
diff --git a/FPGA_nios/hit_pat/inc/udpgen.h b/FPGA_nios/hit_pat/inc/udpgen.h
new file mode 100644
index 0000000..bd69f56
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/udpgen.h
@@ -0,0 +1,54 @@
+/*
+ * udpgen.h
+ *
+ *  Created on: Aug 7, 2019
+ *      Author: mdziewiecki
+ */
+
+#ifndef UDPGEN_H_
+#define UDPGEN_H_
+
+//UDP_GENERATOR_0_BASE
+
+	//byte offsets for registers
+#define UDPGEN_REG_CSR		0	//16 bits 	8 bits command + 8 bits status
+#define UDPGEN_REG_SIZE		2	//16 bits	payload size in words
+#define UDPGEN_REG_SRCIP	4	//32 bits	source IP, last octet first
+#define UDPGEN_REG_DSTIP	8	//32 bits	destination IP. last octet first
+#define UDPGEN_REG_DSTPORT	12	//16 bits	destination port
+#define UDPGEN_REG_SRCPORT	14	//16 bits	source port
+#define UDPGEN_REG_DSTMAC	16	//2*32 bits	destination MAC, last octet first
+#define UDPGEN_REG_RES1		24	//32 bits	reserved
+#define UDPGEN_REG_RES2		28 	//32 bits	reserved
+
+	//csr bitmasks
+#define UDPGEN_CSR_EN_BITMASK	0x0001
+
+
+	//Register access macros
+void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state);
+#define udpgen_command(base, val) 		IOWR_8DIRECT(base, UDPGEN_REG_CSR, val)
+#define udpgen_set_size(base, val) 		IOWR_16DIRECT(base, UDPGEN_REG_SIZE, val)
+#define udpgen_set_srcip(base, val) 	IOWR_32DIRECT(base, UDPGEN_REG_SRCIP, val)
+#define udpgen_set_dstip(base, val) 	IOWR_32DIRECT(base, UDPGEN_REG_DSTIP, val)
+#define udpgen_set_srcip_a(base, val) 	{ for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_SRCIP+i, val[3-i]); }
+#define udpgen_set_dstip_a(base, val) 	{ for(int i = 0; i < 4; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTIP+i, val[3-i]); }
+#define udpgen_set_srcport(base, val) 	IOWR_16DIRECT(base, UDPGEN_REG_SRCPORT, val)
+#define udpgen_set_dstport(base, val) 	IOWR_16DIRECT(base, UDPGEN_REG_DSTPORT, val)
+#define udpgen_set_dstmac_a(base, val) 	{ for(int i = 0; i < 6; i++) IOWR_8DIRECT(base, UDPGEN_REG_DSTMAC+i, val[5-i]); }
+
+#define udpgen_status(base)				IORD_16DIRECT(base, UDPGEN_REG_CSR)
+#define udpgen_get_size(base, val) 		IORD_16DIRECT(base, UDPGEN_REG_SIZE)
+#define udpgen_get_srcip(base, val) 	IORD_32DIRECT(base, UDPGEN_REG_SRCIP)
+#define udpgen_get_dstip(base, val) 	IORD_32DIRECT(base, UDPGEN_REG_DSTIP)
+#define udpgen_get_srcport(base, val) 	IORD_16DIRECT(base, UDPGEN_REG_SRCPORT)
+#define udpgen_get_dstport(base, val) 	IORD_16DIRECT(base, UDPGEN_REG_DSTPORT)
+#define udpgen_get_dstmac(base, val) 	{ for(int i = 0; i < 6; i++) val[i] = IORD_8DIRECT(base, UDPGEN_REG_DSTMAC+i); }
+
+
+//******************************************************
+
+void udpgen_test(alt_u32 base);
+
+
+#endif /* UDPGEN_H_ */
diff --git a/FPGA_nios/hit_pat/inc/utils.h b/FPGA_nios/hit_pat/inc/utils.h
new file mode 100644
index 0000000..eafe646
--- /dev/null
+++ b/FPGA_nios/hit_pat/inc/utils.h
@@ -0,0 +1,34 @@
+/*
+ * utils.h
+ *
+ *  Created on: Jul 31, 2019
+ *      Author: mdziewiecki
+ *  Various utils for various purposes
+ *  Mainly wrappers on hardware
+ */
+
+
+
+#ifndef UTILS_H_
+#define UTILS_H_
+
+//Swap opdd/even bytes in a bunch of data to align endianness of shorts
+void swap_bytes(unsigned char* array, int size_bytes);
+void swap_quad(unsigned char* array, int size_bytes);
+
+void reload_fpga();					//trigger FPGA reload
+
+#define TRIGGER_MASTER	1
+#define TRIGGER_SLAVE	0
+void masterslave(alt_u8 master);			//set trigger system to master or slave operation
+void master_clock_period(alt_u32 period);	//set period of the master frame timer
+void master_clock_enable(alt_u8 en);		//enable/disable pulse generation
+
+void led_set(alt_u8 led_nr);
+void led_clear(alt_u8 led_nr);
+void led_toggle(alt_u8 led_nr);
+void led4_blink_enable(alt_u8 en);
+
+void set_delay(alt_u8 master, alt_u16 value);
+
+#endif /* UTILS_H_ */
diff --git a/FPGA_nios/hit_pat/mem_init/ext_flash.hex b/FPGA_nios/hit_pat/mem_init/ext_flash.hex
new file mode 100644
index 0000000..80559b1
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/ext_flash.hex
@@ -0,0 +1,19658 @@
+:100000003A7001007400C0043A48019804F8FF9C5B
+:100010001EFD3F983A2000003AE02E000620000026
+:10002000C4FF7F013AE02E00060B00003A8807303B
+:100030003AE02E00060800003A880930260400182D
+:1000400026FF7F193AE02E00060D000006F53F005E
+:100050003AE83E2006FF3F00040100BA3A880D004E
+:100060000401C00123008012440080103AB08C3299
+:100070003A160C30C4FFFF391EFA3F383A68004088
+:100080000401C0BD3A8807192300401244008010C3
+:1000900025004022440000211EFBFF203A6800B8E2
+:1000A000040140BB3AE00400040280103A68006892
+:1000B0008CCB0400000000087F454C460101010084
+:1000C00000000000000000000200710001000000BC
+:1000D00038030008340000002BE51F00000000007A
+:1000E00034002000020028002F001800010000004A
+:1000F0000000000000000008000000088CCB040095
+:100100009CE5050007000000001000000100000051
+:1001100000D00400000000140000001420000000C3
+:10012000200000000500000000100000000000009A
+:1001300000000000000000000000000000000000BF
+:1001400000000000000000000000000000000000AF
+:10015000000000000000000000000000000000009F
+:10016000000000000000000000000000000000008F
+:10017000000000000000000000000000000000007F
+:10018000000000000000000000000000000000006F
+:10019000000000000000000000000000000000005F
+:1001A000000000000000000000000000000000004F
+:1001B000000000000000000000000000000000003F
+:1001C000000000000000000000000000000000002F
+:1001D000000000000000000004EDFFDE1500C0DF9D
+:1001E000150240D8150380D81504C0D8150500D9CC
+:1001F000150640D9150780D91508C0D97A300B00EB
+:10020000150900DA150A40DA150B80DA150CC0DA88
+:10021000150D00DB150E40DB150F80DB1510C0DB64
+:10022000151140D904FFFFEB1512C0DB3A3109006C
+:100230004C0080282603001026020020C01F0080EA
+:1002400006070000151240DF17FFBFE804FF3FE973
+:10025000402C00801E02001004FFFFEB1512C0DBD3
+:10026000171140D9171240DF1700C0DF7A7001283C
+:10027000170240D8170380D81704C0D8170500D933
+:10028000170640D9170780D91708C0D9170900DA0F
+:10029000170A40DA170B80DA170CC0DA170D00DBEB
+:1002A000170E40DB170F80DB1710C0DB0413C0DE16
+:1002B0003A0880EF04F9FFDE1506C0DF150500DF00
+:1002C000040500DFC07C10803A31050015FCBFE05A
+:1002D00017FCBFE015FFBFE015FD3FE044008000C4
+:1002E00015FEBFE017FFFFE017FEBFE03A7084186D
+:1002F0002611001017FDBFE0FA900610B40182002D
+:100300003A88851817DCF81017FDBFE0FA9008103E
+:10031000B40182003A88852017DDB8103A880910A8
+:100320003AE83E183A8801003A31050015FBBFE073
+:1003300017FBBFE00607000017FEBFE03A888510F4
+:1003400015FEBFE017FDBFE04400801015FDBFE0C3
+:1003500006E43F0015FFBFE017FFBFE01EDE3F10C1
+:10036000808110803A8801003A8837E01701C0DFA9
+:10037000170000DF0402C0DE3A2800F804FBFFDEAD
+:100380001504C0DF150300DF040300DF15FD3FE1A6
+:10039000FA31050015FFBFE017FFBFE0BAD0041027
+:1003A000CC07801015FFBFE03A33050015FEBFE013
+:1003B00017A9A0D02607001017A9A0D017FFFFE0AB
+:1003C00017FEBFE117FD7FE13A8809183AE83E10B1
+:1003D000060200003AA03D003A8805003A8837E05E
+:1003E0001701C0DF170000DF0402C0DE3A2800F862
+:1003F000140082003300001004F8BF1016FDBF0087
+:100400003400C4061400C0DE7401820614AE92D615
+:100410003401820014E3B2107401C2001467F918A9
+:100420002603C010150000100401801036FDFF10D7
+:10043000C0B70F8006FF3F0004FEFFDE1501C0DFDE
+:10044000150000DF3A8839D884000001C0301780D9
+:100450003A8801003A8837E01701C0DF170000DF53
+:100460000402C0DE3A2800F804FBFFDE1504C0DFFA
+:10047000150300DF040300DF15FD3FE117FDBFE0BA
+:100480000B00C0108DFEFFE08B00C0100DFFFFE0E1
+:100490000B0180108DFFBFE084FEBFE084014001AE
+:1004A0003A880910807A028017FDBFE1840140017B
+:1004B0003A880900C02002803A8801003A8837E073
+:1004C0001701C0DF170000DF0402C0DE3A2800F881
+:1004D00004FCFFDE1503C0DF150200DF040200DFAD
+:1004E000445595008DFEBFE0040481000DFFBFE080
+:1004F0008DFF3FE084FEBFE0840140013A8809108F
+:10050000807A028084FEBFE03A880D1084014001A9
+:100510003A880900C02002803A8801003A8837E012
+:100520001701C0DF170000DF0402C0DE3A2800F820
+:1005300004FCFFDE150300DF040300DF15FE3FE1CE
+:1005400015FD7FE117FEBFE01700801017FDFFE0EB
+:10055000260280183A8805000611000015FF3FE0CA
+:10056000060B000017FEFFE017FFBFE03A88851872
+:1005700003018010CC3F8010260200104400800050
+:100580000607000017FFBFE04400801015FFBFE022
+:1005900017FFBFE0900180101EF23F103A8805005F
+:1005A0003A8837E0170000DF0401C0DE3A2800F87F
+:1005B00004F1FFDE150EC0DF150D00DF040D00DFB6
+:1005C00015F63FE115FA3FE015F93FE04455950077
+:1005D0008DF7BFE044CC80000DF8BFE08DF83FE020
+:1005E00015FF3FE00610000017FABFE03A92061030
+:1005F000C400000117FFBFE03AC885203A88851083
+:100600003A88091017F6BFE03A8805110B008010F0
+:10061000CC3F80103AB0841815FABFE017FFBFE056
+:100620004400801015FFBFE017FFBFE010018010ED
+:100630001EED3F1017F6BFE00B008010CCFFFF103F
+:1006400017F6BFE0840080100B008010CCFF3F1134
+:1006500017F6BFE0040180100B008010CCFF7F1163
+:1006600017F6BFE0840180100B008010CCFFBF1094
+:10067000150080D83A880F283A880D203A880B1840
+:1006800034010201046A1A2180C7028017FABFE010
+:100690003A880910C03B238015FEBFE015FD3FE0FE
+:1006A000062600003401020104731A21C0D9028019
+:1006B00017FA3FE117FDBFE04400C01015FDFFE051
+:1006C000CCFFBF103A880F10040280013A880B005B
+:1006D000C0F0278015FC3FE006090000C4020001BD
+:1006E000C030178017FABFE03A880910C03B23805A
+:1006F00015FEBFE017FCBFE04400801015FCBFE012
+:1007000017FCBFE0480180101E05001017FABFE07B
+:100710003A880B1017FE3FE18047008026EF3F101C
+:1007200017FDBFE0D00280101E040010340102014A
+:10073000047D1A21C0D902800605000017FABFE027
+:100740003A880B1017FE3FE18047008026D53F1006
+:1007500017FEBFE003018010CC3F401117FEBFE041
+:1007600043018010CC3F801117FEBFE08301801051
+:10077000CC3FC01117FEBFE0C3018010CC3F8010FA
+:1007800017FEFFE00302C018CC3FC01817FE3FE180
+:1007900043020021CC3F0021150200D91501C0D829
+:1007A000150080D834010201048A1A2180C7028012
+:1007B000B40182001770B710170A801015F9BFE056
+:1007C00004F9BFE0040140013A8809100084028066
+:1007D00004FABFE0040140013A8809100084028055
+:1007E000C429C00034108600AD30CF1017F9BFE027
+:1007F0003A880710341086003531CF1017FABFE061
+:100800003A880710341086003532CF1044E8C30010
+:1008100034108600AD33CF1017F6BFE0040280100D
+:100820000B008010CCFFFF10341086002D33CF104A
+:1008300015FB3FE00611000017FBBFE00404801029
+:100840003A8807103410860004308F103A888518D3
+:100850004401000117FBFFE03AC8C72017FE3FE143
+:100860003A88C7200301C018CC3FC0182500C0102B
+:1008700017FBBFE04400801015FBBFE017FBBFE093
+:10088000900180101EEC3F1084F7BFE0840140010E
+:100890003A880910807A028084F7BFE03A880D1008
+:1008A000840140013A880900C02002803A88010092
+:1008B0003A8837E01701C0DF170000DF0402C0DE0E
+:1008C0003A2800F804FDFFDE1502C0DF150100DF45
+:1008D000040100DF15FF3FE11735A0D08401C000FF
+:1008E0003AC885183A8809101735E0D00436A0D0E8
+:1008F0003A8885183A880D103A880B203A88090002
+:10090000403102803A8807101735A0D03A88851800
+:100910001535A0D01735A0D0A80180101E020010F8
+:100920003A8805000608000084014001043620D101
+:10093000807A028017FFBFE00436E0D01500C010B7
+:10094000153520D0440080003A8837E01701C0DF19
+:10095000170000DF0402C0DE3A2800F804FCFFDEC6
+:100960001503C0DF150200DF040200DF3A8805200E
+:1009700015FE7FE10DFFBFE00BFFBFE03A88851059
+:100980003A8807101738A0D03AC885183A88091055
+:100990001738E0D0740182000458B3103A888518E3
+:1009A0003A880D103A880B203A88090040310280BD
+:1009B0003A8807101738A0D03A8885181538A0D083
+:1009C0000BFFBFE03A8885103A8807101738A0D08F
+:1009D0002E02C0103A8805000606000017FEFFE050
+:1009E000740182000458B31015008018153820D007
+:1009F000440080003A8837E01701C0DF170000DFAD
+:100A00000402C0DE3A2800F804FBFFDE1504C0DF54
+:100A1000150300DF040300DF15FF3FE006070000B9
+:100A20000038008017FFBFE04400801015FFBFE0D2
+:100A300017FFBFE070FA801026AE011004FEBFE081
+:100A40003A880910C0800080CC3F801026F43F1007
+:100A500017FEBFE00B008010CCFFBF106055951053
+:100A600026A60110060700000038008017FFBFE02F
+:100A70004400801015FFBFE017FFBFE070FA801040
+:100A800026A0011017FEBFE00B018010CCFFBF10A5
+:100A900004FDFFE03A880B183A880910408A00806C
+:100AA000CC3F801026F03F1017FDFFE017FEBFE09F
+:100AB0000B018010CCFFBF103A8885103A880B10CC
+:100AC0003A880918807A028017FEBFE08B008010F8
+:100AD000CCFFBF102094C0101EB500184894C01061
+:100AE0001E2000182084C0101E6900184884C01001
+:100AF0001E0E00186004C0101E4A00188804C010A2
+:100B00001E0500186000C0101E360018200480105A
+:100B10001E3B0010067C01002044C0101E4A001835
+:100B2000604480101E510010067701006088C010DC
+:100B30001E7200188888C0101E0500186084C0103E
+:100B40001E5C0018208880101E630010066E0100D5
+:100B5000208CC0101E720018209080101E82001081
+:100B600006690100A0C8C0101EFF0018C8C8C01048
+:100B70001E0E001820C4C0101EC8001848C4C010A3
+:100B80001E0500182098C0101E9E0018209C801082
+:100B90001EAF0010065C010060C4C0101ED000181B
+:100BA00060C880101EDF0010065701006000D010E2
+:100BB0001E0001188800D0101E05001860CCC0105F
+:100BC0001EF00018200481101EF50010064E0100D2
+:100BD000A000D0101E090118E00090101E1901108D
+:100BE000064901003401020104951A21C0D902808E
+:100BF00017FEBFE03A880910003B00800642010062
+:100C00003401020104991A21C0D902803A880900EE
+:100C1000C0AB028017FEBFE03A880910003B00809D
+:100C20000639010034010201049F1A21C0D9028053
+:100C30003A88090000A7028017FEBFE03A88091031
+:100C4000003B0080063001003401020104A51A2196
+:100C5000C0D902803A880900C0B7028017FEBFE001
+:100C60003A880910003B0080062701003401020188
+:100C700004AB1A21C0D9028044000001C0B7028031
+:100C800017FEBFE03A880910003B0080061E0100F5
+:100C90003401020104B01A21C0D902803A88090047
+:100CA00040A1028017FEBFE03A880910003B008097
+:100CB000061501003401020104B61A21C0D90280D0
+:100CC0004400000140A1028017FEBFE03A880910ED
+:100CD000003B0080060C01003401020104BC1A2113
+:100CE000C0D902803A8809004094028017FEBFE014
+:100CF0003A880910003B008006030100340102011C
+:100D000004C31A21C0D9028044000001409402802B
+:100D100017FEBFE03A880910003B008006FA000089
+:100D200017FDBFE00B008010CCFFBF103A880B10FE
+:100D30003401020104CA1A2180C7028017FDBFE0F6
+:100D40000B008010CCFFBF103A880910C09C0280B5
+:100D500017FEBFE00D01001017FEBFE03A88091032
+:100D6000003B008006E8000017FDBFE00B0080108C
+:100D7000CCFFBF103A880B103401020104D21A21B3
+:100D800080C7028017FDBFE00B008010CCFFFF1072
+:100D900034108600AD55CF1017FEBFE00D010010D6
+:100DA00017FEBFE03A880910003B008006D600001D
+:100DB00017FDBFE00B008010CCFFBF103A880B106E
+:100DC0003401020104DA1A2180C7028017FDBFE056
+:100DD0000B008010CC3F80103A880D108400400139
+:100DE0003410060104540F2100B8018017FEBFE043
+:100DF0000D01001017FEBFE03A880910003B00808B
+:100E000006C1000017FDBFE00B008010CCFFBF1033
+:100E10003A880B103401020104E01A2180C70280D5
+:100E200017FDBFE00B008010CCFFBF103A880B10FD
+:100E30004400000180BC028017FEBFE00D010010DD
+:100E400017FEBFE03A880910003B008006AE0000A4
+:100E500017FDBFE00B008010CCFFBF103A880B10CD
+:100E60003401020104EA1A2180C7028017FDBFE0A5
+:100E70000B008010CCFFBF103A880B103A88090095
+:100E800080BC028017FEBFE00D01001017FEBFE01E
+:100E90003A880910003B0080069B000034010201E3
+:100EA00004F41A21C0D902803A880D0044004001A0
+:100EB0003410060104540F2100B801803A880D0057
+:100EC000440040013410060104300F2140550280D7
+:100ED00017FEBFE03A880910003B0080068A000038
+:100EE0003401020104F91A21C0D9028044008001B2
+:100EF000440040013410060104300F2140550280A7
+:100F000044008001440040013410060104540F21C4
+:100F100000B8018017FEBFE03A880910003B00804E
+:100F2000067900003401020104FE1A21C0D90280B2
+:100F300044008001040240013410060104540F21D2
+:100F400000B801803A880D00040240013410060107
+:100F500004540F2100B8018017FEBFE03A88091041
+:100F6000003B0080066800003401020104051B21DB
+:100F7000C0D9028017FEBFE03A880910003B00800C
+:100F80000661000034010201040B1B21C0D902805C
+:100F900017FDBFE03A880910804F0080065A000014
+:100FA0003401020104111B21C0D90280804100805C
+:100FB0000655000017FDBFE00B008010CCFFBF10EE
+:100FC0003A880B103401020104181B2180C70280EB
+:100FD00017FDBFE00B008010CCFFFF10341086001F
+:100FE0002557CF1017FEBFE00D01001017FEBFE020
+:100FF0003A880910003B00800643000017FDBFE05F
+:101000000B008010CCFFBF103A880B103401020196
+:1010100004211B2180C7028017FDBFE00B00801058
+:10102000CCFFFF10341086006557CF1017FEBFE0CD
+:101030000D01001017FEBFE03A880910003B008048
+:101040000631000017FEBFE00B018010CCFFBF107F
+:10105000B00080101E1A001017FDBFE00B008010BA
+:10106000CCFFBF103A8885103A88071034108600EC
+:1010700004008D103A88851817FDFFE08400C01821
+:101080000B00C018CCFFFF182D00C01017FDBFE0EB
+:101090000B008010CCFFFF1017FDBFE08400801014
+:1010A0000B008010CCFFBF103A880D103A880B1847
+:1010B0003401020104291B2180C7028006070000B9
+:1010C00017FEBFE00B018010CCFFBF103A880B1059
+:1010D0003401020104361B2180C7028017FEBFE0E5
+:1010E0000D01001017FEBFE03A880910003B008098
+:1010F000060500003A880100060300003A88010056
+:10110000060100003A8801003A8837E01701C0DF85
+:10111000170000DF0402C0DE3A2800F804FCFFDEFE
+:101120001503C0DF150200DF040200DF15FE3FE1FA
+:101130003401020104451B21C0D9028004E84301A7
+:101140003A880900000D02803410060104540F2172
+:1011500080C0018034010201044D1B21C0D90280EE
+:1011600015FF3FE0060B000017FFBFE03A8885102F
+:101170003A8807103410860004008D103A888518CC
+:101180000400C8002D00C01017FFBFE0440080100D
+:1011900015FFBFE017FFBFE0305080101EF23F1078
+:1011A0000095008006FE3F0004FEFFDE1501C0DF53
+:1011B000150000DF3A8839D87401020104482E2155
+:1011C000400729803A8801003A8837E01701C0DFDC
+:1011D000170000DF0402C0DE3A2800F804FCFFDE3E
+:1011E0001503C0DF150200DF040200DF15FE3FE13A
+:1011F000C03D298040812780060200008400000154
+:10120000C0301780176FA0D026FC3F1034010201B8
+:10121000045E1B21C0D9028000050280000F0180FE
+:10122000C43F0001007F1680C5FFBFE006FF3F00FE
+:1012300004F5FFDE150AC0DF150900DF040900DF31
+:1012400015FE3FE115FD7FE115FCBFE13A8809007D
+:1012500040731780150400D8150300D804008E00D1
+:10126000150280D874018200048BB310150180D858
+:1012700044018000150080D84401C001B4018201FE
+:10128000048BAB313A880B0034000201044904217D
+:10129000C0641680C5FFBFE000A7108006FF3F00B6
+:1012A00004FBFFDE1504C0DF150300DF040300DFCD
+:1012B00015FE3FE115FD7FE115FF3FE017FD3FE122
+:1012C000408B018015FFBFE017FFBFE02603001031
+:1012D00017FD3FE10078018015FFBFE017FFBFE079
+:1012E0003A8837E01701C0DF170000DF0402C0DED4
+:1012F0003A2800F804F8FFDE1507C0DF150600DF06
+:10130000040600DF15FE3FE115FD7FE115FCBFE19E
+:1013100015FBFFE13410860037508F103A308400FF
+:1013200015FFBFE017FF7FE13401020104651B21B7
+:1013300080C70280170280E01500001017FFBFE091
+:101340003AD10410CC038010040480103A960610A1
+:10135000F4018000840280103AB0861817FDBFE0C7
+:101360001500C01017FBFFE0F441800084028010DC
+:101370001500801817FCFFE034408000C4FFBF1048
+:101380001500801834010201046B1B21C0D90280B2
+:1013900017FDBFE0170080103AD6061017FDBFE01A
+:1013A000170080103AD204100CC0BF103AB0861853
+:1013B00017FDBFE0170080103A920410EC3F801038
+:1013C0003AB0861817FDBFE0170080103A96041057
+:1013D0003AB084183AD6081017FDBFE01700801005
+:1013E0003AD6061017FDBFE0170080103AD204105D
+:1013F0000CC0BF103AB0861817FDBFE01700801070
+:101400003A920410EC3F80103AB0861817FDBFE006
+:10141000170080103A9604103AB084183AD4041099
+:10142000CC3F401117FDBFE0170080103AD60610E0
+:1014300017FDBFE0170080103AD204100CC0BF1097
+:101440003AB0861817FDBFE0170080103A920410DA
+:10145000EC3F80103AB0861817FDBFE017008010EF
+:101460003A9604103AB084183AD20410CC3F801156
+:1014700017FDBFE0170080103AD6061017FDBFE039
+:10148000170080103AD204100CC0BF103AB0861872
+:1014900017FDBFE0170080103A920410EC3F801057
+:1014A0003AB0861817FDBFE0170080103A96041076
+:1014B0003AB08418CC3F8010150080D83A880F309D
+:1014C0003A880D283A880B2034010201046F1B2151
+:1014D00080C70280440080003A8837E01701C0DFEF
+:1014E000170000DF0402C0DE3A2800F804F9FFDE2E
+:1014F0001506C0DF150500DF040500DF15FF3FE01E
+:1015000015FE3FE0065600003401020104781B215D
+:10151000C0D902803401020104881B21C0D9028095
+:101520003401020104981B2180C7028015FE3FE0B0
+:10153000061D000080C302803A88071017FEBFE036
+:101540003A8885E0C5FBFF1017FEBFE03A8885E0CA
+:10155000C3FBBF10CC3F80101C20801004E0BF10E4
+:101560003A88091080CB028017FEBFE03A8885E0F8
+:10157000C3FBBF10CC3F80101C20801004E0BF10C4
+:10158000180280101E05001017FEBFE016030010A1
+:1015900017FEBFE0C4FFBF1015FEBFE017FEBFE09F
+:1015A0004400801015FEBFE017FEBFE0500280101F
+:1015B0001EE03F108402000180CB028015FE3FE058
+:1015C0000624000017FEBFE03A8885E0C3FBBF1089
+:1015D000CC3F80101C20801004E0BF104400C010DD
+:1015E0003401820084759C103A88851803008010AD
+:1015F000CC3F80100C018010260E001017FFBFE0BA
+:10160000A402801015FFBFE017FEBFE03A8885E016
+:10161000C3FBBF10CC3FC0101C20C01804E0FF1853
+:1016200017FFBFE03A88851804F4BF1015FFBFE02C
+:101630000605000015FF3FE03401020104A61B214E
+:10164000C0D902800606000017FEBFE044008010EB
+:1016500015FEBFE017FEBFE0500280101ED93F10FC
+:1016600017FFBFE026A83F1017FFBFE03A8837E01A
+:101670001701C0DF170000DF0402C0DE3A2800F8BF
+:1016800004EFFFDE1510C0DF150F00DF040F00DFD1
+:10169000C4FFBF0015FFBFE015FE3FE034010201AB
+:1016A00004B51B21C0D902803401020104C51B21ED
+:1016B000C0D902803401020104D61B21C0D90280A6
+:1016C0004043018015FEBFE017FEBFE02654001026
+:1016D00084FFBF0005F1BFE08416800045F1BFE044
+:1016E00085F13FE0C5F13FE005F23FE0C401800035
+:1016F00045F2BFE044FBBF0085F2BFE0C4FFBF007E
+:10170000C5F2BFE017FEBFE03AD2041005F3BFE018
+:1017100017FEBFE045F3BFE0C4FFBF0085F3BFE0A5
+:10172000C4FFBF00C5F3BFE08402800005F4BFE042
+:1017300045F43FE0C401800085F4BFE0040480006C
+:10174000C5F4BFE0C4FFBF0005F5BFE0C4FFBF00A4
+:1017500045F5BFE0C4FFBF0085F5BFE0C4FFBF0093
+:10176000C5F5BFE0C4FFBF0005F6BFE0C4FFBF0082
+:1017700045F6BFE0C4FFBF0085F6BFE0C5F63FE019
+:101780008402800005F7BFE045F73FE0C401800018
+:1017900085F7BFE044008000C5F7BFE0C4FFBF008D
+:1017A00005F8BFE0C4FFBF0045F8BFE0C4FFBF00BD
+:1017B00085F8BFE0C4FFBF00C5F8BFE034010201F7
+:1017C00004DD1B21407E0F8015FDBFE017FDBFE04B
+:1017D00026130010173AA0D03A88071017FDBFE073
+:1017E00015FCBFE015FBFFE004F1BFE015FABFE018
+:1017F0000408800015F9BFE017FCBFE01705801052
+:1018000017F9FFE117FABFE117FB7FE117FC3FE192
+:101810003AE83E1017FD3FE1C0840F8015FF3FE01E
+:1018200017FFBFE03A8837E01701C0DF170000DF7D
+:101830000402C0DE3A2800F804F8FFDE1507C0DF16
+:10184000150600DF040600DF15FD3FE1C4FFBF0001
+:1018500015FFBFE015FE3FE03401020104E31B2148
+:10186000C0D902803401020104F31B21C0D90280D7
+:101870004043018015FEBFE017FEBFE02635001093
+:1018800017FDBFE00500001017FDBFE04400801009
+:10189000C401C0000500C01017FDBFE08400801027
+:1018A00044FBFF000500C01017FDBFE0C40080101E
+:1018B000C4FFFF000500C01017FEBFE03AD20610BB
+:1018C00017FDBFE0040180100500C01017FDBFE048
+:1018D0004401801017FEFFE00500C01017FDBFE0B7
+:1018E00003008010CC3F401117FDBFE04400801082
+:1018F00003008010CC3F801117FDBFE084008010F2
+:1019000003008010CC3FC01117FDBFE0C400801061
+:1019100003008010CC3F801017FDFFE00401C018C9
+:101920000300C018CC3FC01817FD3FE1440100215F
+:1019300003000021CC3F0021150200D91501C0D8B9
+:10194000150080D83401020104F71B2180C70280F2
+:1019500015FF3FE017FFBFE03A8837E01701C0DF0F
+:10196000170000DF0402C0DE3A2800F804F8FFDEAA
+:101970001507C0DF150600DF040600DF15FD3FE197
+:1019800015FF3FE0043A20D140A5018015FFBFE0DC
+:1019900017FFBFE01E040010173AE0D034008500A6
+:1019A0003A888518153BA0D017FFBFE01E0800102D
+:1019B000173BA0D03700801015FEBFE017FEBFE038
+:1019C000A0BF96101E020010805C018015FFBFE0D2
+:1019D00017FFBFE01E470010173BA0D00401801086
+:1019E00023008010CC3F80103A88071017FDBFE01D
+:1019F0000500C010173BA0D04401801023008010C8
+:101A0000CC3FC01017FDBFE0440080100500C0109F
+:101A1000173BA0D08401801023008010CC3FC01061
+:101A200017FDBFE0840080100500C010173BA0D058
+:101A3000C401801023008010CC3FC01017FDBFE010
+:101A4000C40080100500C010173BA0D00402801015
+:101A500023008010CC3FC01017FDBFE004018010B0
+:101A60000500C010173BA0D0440280102300801056
+:101A7000CC3FC01017FDBFE0440180100500C0102E
+:101A800017FDBFE003008010CC3F401117FDBFE001
+:101A90004400801003008010CC3F801117FDBFE090
+:101AA0008400801003008010CC3FC01117FDBFE000
+:101AB000C400801003008010CC3F801017FDFFE0B1
+:101AC0000401C0180300C018CC3FC01817FD3FE147
+:101AD0004401002103000021CC3F0021150200D960
+:101AE0001501C0D8150080D83401020104F71B216C
+:101AF00080C7028017FFBFE03A8837E01701C0DFD8
+:101B0000170000DF0402C0DE3A2800F804F3FFDE0D
+:101B1000150CC0DF150B00DF040B00DF15F53FE1EE
+:101B200015FC3FE03401020104DD1B21407E0F80E3
+:101B300015FBBFE017FBBFE01E020010C4FFBF0093
+:101B400015FCBFE017FCBFE01E0D001017FBBFE047
+:101B500015FABFE004F7BFE015F9BFE004F6BFE0F7
+:101B600015F8BFE017FABFE01707801017F8BFE1BC
+:101B700017F97FE117FA3FE13AE83E1015FCBFE0A4
+:101B800017FCBFE01E21001017F7BFE015FFBFE0F4
+:101B90004400800015FDBFE00610000017F7FFE0CD
+:101BA00017FDBFE03A9104103A888518170080109D
+:101BB00017FFFFE01700C0180E05801817F7FFE0A9
+:101BC00017FDBFE03A9104103A88851815FFBFE071
+:101BD00017FDBFE04400801015FDBFE017F6BFE021
+:101BE00017FDFFE016EDBF1817FFBFE01700C0108C
+:101BF00017FFBFE0170180103A88871817FFBFE072
+:101C0000170380103AC8851815FEBFE017FCBFE027
+:101C10001E03001017FEFFE017F5BFE01500C0100F
+:101C200017FCBFE03A8837E01701C0DF170000DF7C
+:101C30000402C0DE3A2800F804FBFFDE150400DFD2
+:101C4000040400DF15FE3FE13A8805283A88073092
+:101C500005FDBFE03A88051805FCBFE017FEBFE0B0
+:101C600023008010CC3F8010C5FFBFE003FCBFE025
+:101C700026050010C3FFFFE003FDBFE03AB0841863
+:101C8000C5FFBFE00606000003FDBFE03A30840058
+:101C90003A880710C3FFBFE03A708418C5FFBFE061
+:101CA00017FEBFE0C3FFFFE02500C0103A88010027
+:101CB0003A8837E0170000DF0401C0DE3A2800F858
+:101CC00004FDFFDE1502C0DF150100DF040100DFA7
+:101CD00015FF3FE13401020104061C21C0D9028036
+:101CE00017FFBFE03A8807002500C01017FFBFE0CC
+:101CF000840080103A880710840180002500801835
+:101D000017FFBFE0C40080103A880710C4078000A6
+:101D10002500801817FFBFE0040180103A880710E3
+:101D2000440080002D00801817FFBFE08401801060
+:101D30003A880710041980002D00801817FFBFE0B3
+:101D4000040280103A880710840C80002500801857
+:101D500017FFBFE0440280103A8807002500C0103A
+:101D600017FFBFE0840280103A8807100400A0002B
+:101D70002D00801817FFBFE04400C0002500C010F0
+:101D800017FFBFE0040380103A8807108402800028
+:101D90002500801817FFBFE0440380103A88071021
+:101DA000040180002500801817FFBFE08403801025
+:101DB0003A88071004018000250080183A88010045
+:101DC0003A8837E01701C0DF170000DF0402C0DEE9
+:101DD0003A2800F804FEFFDE150100DF040100DFF1
+:101DE00015FF3FE117FFBFE0C4FFFF001502C01061
+:101DF00017FFBFE04400C0001500C0103A88010082
+:101E00003A8837E0170000DF0401C0DE3A2800F806
+:101E100004FEFFDE150100DF040100DF15FF3FE1D6
+:101E200017FFBFE0C4FFFF001502C01017FFBFE09F
+:101E3000C4FFFF001501C01017FFBFE0C4FFFF0083
+:101E40001503C01017FFBFE0150000103A8801000D
+:101E50003A8837E0170000DF0401C0DE3A2800F8B6
+:101E600004F6FFDE1509C0DF150800DF040800DFF7
+:101E700015F83FE1173CA0D0C4F9FFE03A880D18EF
+:101E80003A880B003A880910C0CD13800404800002
+:101E900015FEBFE017F8BFE017028010E0FFBF108B
+:101EA0001E0900103401020104161C21C0D9028051
+:101EB00017F8BFE0170280103A88091000A62280A8
+:101EC00017F83FE1C0D1018017F8BFE0170180107B
+:101ED00004FE3FE104FAFFE03A880D203A880B182F
+:101EE0003A8809104021268015FFBFE017FFBFE0A8
+:101EF000160C001017F8BFE017FFFFE01502C01026
+:101F000017F8BFE08400C0001500C01017FB3FE1C8
+:101F1000C08F26803A880B103401020104211C2155
+:101F200080C70280173CA0D03A8809108023148013
+:101F30003A8801003A8837E01701C0DF170000DF58
+:101F40000402C0DE3A2800F804B3FFDE154CC0DFFF
+:101F5000154B00DF044B00DF15B63FE115FF3FE0F6
+:101F6000173CA0D0C4F8FFE03A880D183A880B005F
+:101F70003A880910C0CD138015F93FE015FA3FE00B
+:101F8000B400800004A8A11015FBBFE015FE3FE0DF
+:101F9000060D00003A880D00440040018400000155
+:101FA00000A72B803A88091017FEBFE03A9106106F
+:101FB000740182003A8885181561331117FEBFE05D
+:101FC0004400801015FEBFE017FEBFE00EF1BF0019
+:101FD000173CA0D03A8809108023148015B73FE041
+:101FE00015FD3FE00620000017FDBFE03A91061006
+:101FF000740182003A8885181763B3101617001011
+:1020000017FDBFE03A910610740182003A888518E6
+:102010001761B31004B7FFE03A880B183A8809102B
+:1020200080B1308017FDBFE03A9106107401820044
+:102030003A8885181761F31017FFBFE0160780185C
+:1020400017FDBFE03A910610740182003A888518A6
+:102050001761B3104400801015FFBFE017FDBFE00B
+:102060004400801015FDBFE017FDBFE00EDEBF008D
+:1020700017FFBFE01E030010C4020001C03017802C
+:1020800006D63F0004B7FFE004F9BFE0150080D892
+:102090003A880F003A880D003A880B1817FF3FE185
+:1020A00040A7268015FC3FE00614000017FCBFE0A7
+:1020B0003A910610740182003A8885181761B310AE
+:1020C00004B7FFE03A880B183A880910C0B830808E
+:1020D0002607001017FCBFE03A9106107401820039
+:1020E0000460B3103A8885183A88091080DA0180B4
+:1020F00017FCBFE04400801015FCBFE017FCBFE0F8
+:102100000EEABF0006B53F0004FCFFDE1503C0DF8A
+:10211000150200DF040200DFC4FEBFE03A880B10A6
+:1021200004020001C0891380153CA0D015FF3FE0D8
+:10213000060A000017FFBFE03A9106107401820002
+:102140000460B3103A8885183A88091080D5018058
+:1021500017FFBFE04400801015FFBFE017FFBFE08E
+:102160000EF4BF0074010201044E2E2140072980A5
+:102170003A8805003A8837E01701C0DF170000DF12
+:102180000402C0DE3A2800F804F7FFDE1508C0DFBD
+:10219000150700DF040700DF15FA3FE115F97FE1BD
+:1021A000173CA0D0C4FBFFE03A880D183A880B001A
+:1021B0003A880910C0CD1380840080000DFCBFE078
+:1021C00017F9BFE03AD20510CC3F80103A880710CB
+:1021D00017F9BFE03A9204103AB084188DFCBFE0C2
+:1021E00015FD3FE017FABFE03A9106107401820036
+:1021F0003A8885181761B31004FCFFE004048001DD
+:102200003A880B183A88091000AF2B800E05001091
+:10221000173CA0D03A88091080231480C4FFBF0067
+:102220000623000017FABFE03A91061074018200FD
+:102230003A8885181761B310440040013A880910A4
+:1022400000C52B800E050010173CA0D03A8809105D
+:102250008023148084FFBF000615000017FABFE03A
+:102260003A910610740182000460B3103A88851810
+:102270003A880910C0D1018017FABFE03A910810DE
+:1022800017F9FFE0740182003A8885201563F31086
+:1022900017F97FE134010201042F1C2180C702805D
+:1022A000173CA0D03A880910802314803A88050092
+:1022B0003A8837E01701C0DF170000DF0402C0DEF4
+:1022C0003A2800F804F9FFDE1506C0DF150500DF27
+:1022D000040500DF15FD3FE115FC7FE115FBBFE1C3
+:1022E000173CA0D0C4FEFFE03A880D183A880B00D6
+:1022F0003A880910C0CD138017FDBFE03A9106104F
+:10230000740182003A8885181762B310D8FFBF1095
+:102310001E050010173CA0D03A88091080231480B5
+:102320003A8805000624000017FDBFE03A91061028
+:10233000740182003A8885181762B3103A880F003A
+:1023400017FCBFE117FB7FE13A880910C0B92C8068
+:1023500015FFBFE017FFBFE0D8FFBF101E1200102F
+:1023600034010201043D1C21C0D9028017FDBFE0E9
+:102370003A910610740182003A8885181762B310EA
+:102380003A88091000A6228017FDBFE03A91061096
+:10239000740182000460B3103A8885183A880910E5
+:1023A000C0D1018015FF3FE0173CA0D03A8809104A
+:1023B0008023148017FFBFE03A8837E01701C0DFA1
+:1023C000170000DF0402C0DE3A2800F804B3FFDE85
+:1023D000154CC0DF154B00DF044B00DF15B83FE1A3
+:1023E00015B77FE115B6BFE1173CA0D0C4B9FFE037
+:1023F0003A880D183A880B003A880910C0CD13802E
+:1024000017B8BFE03A910610740182003A88851827
+:102410001762B310D8FFBF101E050010173CA0D0E4
+:102420003A880910802314803A880500065000007D
+:1024300015BD3FE017B8BFE03A9106107401820065
+:102440003A8885181762B31004BDFFE03A880B186C
+:102450003A88091080B1308017B8BFE03A91061071
+:10246000740182003A8885181762B3104400801006
+:1024700015FEBFE015BA3FE015BB3FE015BC3FE0DD
+:1024800004BDFFE004BABFE0150080D83A880F0011
+:102490003A880D003A880B1817FE3FE140A72680C6
+:1024A000262F001017B8BFE03A9106107401820081
+:1024B0003A8885181762B31004BDFFE03A880B18FC
+:1024C0003A880910C0B830802625001017B8BFE040
+:1024D0003A910610740182003A8885181762B31089
+:1024E0003A880F0017B7BFE117B67FE13A880910A5
+:1024F00040792C8015FFBFE017FFBFE0D8FFBF1069
+:102500001E12001034010201044A1C21C0D90280AD
+:1025100017B8BFE03A910610740182003A88851816
+:102520001762B3103A88091000A6228017B8BFE0DE
+:102530003A910610740182000460B3103A8885183D
+:102540003A880910C0D1018015FF3FE0173CA0D0A8
+:102550003A8809108023148017FFBFE006040000AA
+:10256000173CA0D03A880910802314803A880500CF
+:102570003A8837E01701C0DF170000DF0402C0DE31
+:102580003A2800F804FCFFDE1503C0DF150200DF67
+:10259000040200DF15FE3FE1173CA0D0C4FFFFE0BE
+:1025A0003A880D183A880B003A880910C0CD13807C
+:1025B00017FEBFE03A910610740182003A88851830
+:1025C0001762B3103A88091000A6228017FEBFE0F8
+:1025D0003A910610740182000460B3103A8885189D
+:1025E0003A880910C0D10180173CA0D03A88091060
+:1025F000802314803A8805003A8837E01701C0DF4D
+:10260000170000DF0402C0DE3A2800F804FBFFDEFA
+:10261000150400DF040400DF15FE3FE13A880528B9
+:102620003A88073005FDBFE03A88051805FCBFE091
+:1026300017FEBFE023008010CC3F8010C5FFBFE035
+:1026400003FCBFE026050010C3FFFFE003FDBFE071
+:102650003AB08418C5FFBFE00606000003FDBFE0E6
+:102660003A3084003A880710C3FFBFE03A708418FC
+:10267000C5FFBFE017FEBFE0C3FFFFE02500C010AD
+:102680003A8801003A8837E0170000DF0401C0DE15
+:102690003A2800F804F6FFDE1509C0DF150800DF50
+:1026A000040800DF15F83FE13401020104601C2139
+:1026B000C0D902800406800085FBBFE084F5BF001E
+:1026C000C5FBBFE0C4F1BF0005FCBFE044018000D2
+:1026D00045FCBFE084EABF0085FCBFE0C418800071
+:1026E000C5FCBFE08402800085FABFE0C5FA3FE088
+:1026F000C401800005FBBFE04404800045FBBFE04F
+:102700008402800085F9BFE0C5F93FE0C401800084
+:1027100005FABFE04400800045FABFE04400C00075
+:10272000341086002530CF100404C0003410860019
+:10273000AD30CF1015FF3FE00610000017FFBFE0DF
+:10274000040180103A8807103410860004308F107E
+:102750003A888518C400000117FFFFE03AC8C72077
+:102760003A88C7E083FAFF18CC3FC0182500C01094
+:1027700017FFBFE04400801015FFBFE017FFBFE068
+:10278000100180101EED3F1015FE3FE00610000006
+:1027900017FEBFE0040280103A880710341086004C
+:1027A00004308F103A888518C400000117FEFFE03E
+:1027B0003AC8C7203A88C7E083F9FF18CC3FC01851
+:1027C0002500C01017FEBFE04400801015FEBFE0DA
+:1027D00017FEBFE0100180101EED3F100400C40082
+:1027E00034108600AD33CF104400C400341086008E
+:1027F0002D33CF1015FD3FE00610000017FDBFE0A0
+:10280000040480103A8807103410860004308F10BA
+:102810003A8885184401000117FDFFE03AC8C72037
+:102820003A88C7E083FBFF18CC3FC0182500C010D2
+:1028300017FDBFE04400801015FDBFE017FDBFE0AD
+:10284000900180101EED3F103A8801003A8837E071
+:102850001701C0DF170000DF0402C0DE3A2800F8CD
+:1028600004FBFFDE150400DF040400DF15FD3FE17B
+:1028700015FC7FE115FF3FE00617000017FFBFE0E2
+:1028800017FDFFE03A88851803008010C5FEBFE001
+:1028900017FFBFE04400801017FDFFE03A8887185B
+:1028A00017FFBFE017FD3FE13A8885200300C018FD
+:1028B0000500C01017FFBFE04400801017FDFFE0C7
+:1028C0003A888518C3FEFFE00500C01017FFBFE07F
+:1028D0008400801015FFBFE017FFFFE017FCBFE08A
+:1028E00016E6BF183A8801003A8837E0170000DF83
+:1028F0000401C0DE3A2800F804FAFFDE150500DF07
+:10290000040500DF15FC3FE115FB7FE115FF3FE00B
+:102910000622000017FFBFE017FCFFE03A88851889
+:102920000300C01005FDFFE04300C01045FDFFE0BF
+:102930008300C01085FDFFE0C3008010C5FDBFE02F
+:1029400015FE3FE0060F0000C400C00017FEBFE008
+:102950003AC8871817FF3FE117FEBFE03A88852085
+:102960003A88091017FCBFE03A8805113A88C7E099
+:1029700003FDFF180500C01017FEBFE044008010E3
+:1029800015FEBFE017FEBFE0100180101EEE3F10E5
+:1029900017FFBFE00401801015FFBFE017FFFFE045
+:1029A00017FBBFE016DBBF183A8801003A8837E012
+:1029B000170000DF0401C0DE3A2800F804FEFFDE45
+:1029C0001501C0DF150000DF3A8839D83401020153
+:1029D00004691C21C0D902803401020104711C2148
+:1029E000C0D902803A8801003A8837E01701C0DF79
+:1029F000170000DF0402C0DE3A2800F804FDFFDE05
+:102A00001502C0DF150100DF040100DF3A88052050
+:102A100005FFBFE003FFBFE0260400100420C00054
+:102A2000341086003514CF10060300000420C000C7
+:102A3000341086003515CF1003FFBFE0853DA0D0D0
+:102A4000833DA0D0CC3F0011833DA0D0CC3F80106F
+:102A50003A888710043EA0D03A8885180B00801071
+:102A6000CCFFBF103A880B1080BC02803A8801006E
+:102A70003A8837E01701C0DF170000DF0402C0DE2C
+:102A80003A2800F804FEFFDE150100DF040100DF34
+:102A900015FF3FE117FFBFE0CCFFFF1034108600A9
+:102AA0003502CF1017FFBFE03AD40410CCFFFF105F
+:102AB000341086003503CF103A8801003A8837E099
+:102AC000170000DF0401C0DE3A2800F804FDFFDE35
+:102AD000150200DF040200DF3A88052005FEBFE092
+:102AE0008DFF3FE003FEBFE0260400108BFFBFE038
+:102AF000940180108DFFBFE0060300008BFFBFE054
+:102B0000140280108DFFBFE08BFFFFE034108600C1
+:102B10003501CF103A8801003A8837E0170000DF0E
+:102B20000401C0DE3A2800F804FEFFDE150100DFD4
+:102B3000040100DF3A88052005FFBFE003FFBFE086
+:102B4000700180102606001003FFBFE04400C000A3
+:102B50003A988618341086003514CF10060100000C
+:102B60003A8801003A8837E0170000DF0401C0DE30
+:102B70003A2800F804FEFFDE150100DF040100DF43
+:102B80003A88052005FFBFE003FFBFE07001801019
+:102B90002606001003FFBFE04400C0003A988618E4
+:102BA000341086003515CF10060100003A88010068
+:102BB0003A8837E0170000DF0401C0DE3A2800F849
+:102BC00004FDFFDE150200DF040200DF3A88052065
+:102BD00005FEBFE003FEBFE070018010261000106C
+:102BE0003410860037108F1015FFBFE003FEBFE0E2
+:102BF0004400C0003A9884183A88071017FFBFE0D5
+:102C00003AF0C41015FFBFE003FEBFE04400C0006F
+:102C10003A988618341086003510CF10060100004F
+:102C20003A8801003A8837E0170000DF0401C0DE6F
+:102C30003A2800F804FEFFDE150100DF040100DF82
+:102C40003A88052005FFBFE003FFBFE0260400101F
+:102C50000408C000341086003515CF1006030000AC
+:102C60000408C000341086003514CF103A880100E3
+:102C70003A8837E0170000DF0401C0DE3A2800F888
+:102C800004FDFFDE150200DF040200DF3A880520A4
+:102C90003A88072805FFBFE03A8805180DFEBFE017
+:102CA00003FFBFE03A888710043EA0D03A88851819
+:102CB0000BFEFFE00D00C010833DA0D003FFFFE03E
+:102CC000CC3F80101E0380180BFEFFE034108600FE
+:102CD0002D55CF103A8801003A8837E0170000DF01
+:102CE0000401C0DE3A2800F817014021C1AD078079
+:102CF0007401820017AF321117014021C1AD078066
+:102D000004FDFFDE3A8805281500C0DF150180D9D3
+:102D10001502C0D9170240210401C0D93A880D100C
+:102D200040E402801700C0DF0403C0DE3A2800F848
+:102D300004FCFFDE1500C0DF150140D9150280D963
+:102D40001503C0D97401820017AFB2103A880B2066
+:102D5000040180D91702001140FA04801700C0DF77
+:102D60000404C0DE3A2800F817028021019109808E
+:102D70007401820017AFB2103A880B20170280113D
+:102D80003A8809100191098004F5FFDE150800DC7E
+:102D90003A8821203A880928150940DC150AC0DF45
+:102DA0003A882328C0DA028044000011150580D833
+:102DB000440080003401C200150780D8040480D884
+:102DC0000416DD18150180D884008000150440DC4D
+:102DD0001506C0D8150300D9150280D81702408106
+:102DE00026020080170E8080261300100B03802817
+:102DF0000C00C8101E0600181719C028C4FF3701A0
+:102E0000140088103A7006190D0380281519C0287F
+:102E1000040180D93A880980004C07801E0B0010FD
+:102E200084028000170AC0DF170940DC170800DCA5
+:102E3000040BC0DE3A2800F83A880980150040D912
+:102E400000060780170040D906E83F00C4FFBF0016
+:102E500006F43F00740182003A880B2017AF32114C
+:102E600001CD0280CC0080202620001007008020A9
+:102E7000262000103A880520060200000700C01036
+:102E80002618001844008010CC00C0101EFB3F180C
+:102E900017004011F4BFFF01C4BFFF393A88C729AA
+:102EA0007420A0013A304A013A7046190420A0313A
+:102EB0003A7086191E09001804018010170040118D
+:102EC0003A88C7293A304A013A7046193A70861949
+:102ED00026F93F1806010000440080100700C010CA
+:102EE0001EFD3F183AC805113A2800F83A88052017
+:102EF00006E73F003A8805003A2800F804BDFFDEE7
+:102F00001542C0DF153D00DD153CC0DC153900DC85
+:102F1000150500D93A8821203A8827283A8829308F
+:102F20001506C0D9154100DF1540C0DD153F80DD15
+:102F3000153E40DD153B80DC153A40DC00BF0780C4
+:102F4000170080103A880910150D80D8C0DA028069
+:102F5000150B80D826020080170E808026DA02101A
+:102F60000B0380980C00C8101E0600181719C09893
+:102F7000C4FF3701140088103A7006190D038098B9
+:102F80001519C0980C02C010269A00181704C09892
+:102F9000269800188C06801098028010269D00103C
+:102FA0000429C0DD151CC0DD151E00D8151D00D874
+:102FB000150800D8150900D8150A00D83A8811B8A4
+:102FC000150C00D8151100D8150400D83A882DA08A
+:102FD000070080B026A20010600980101E2E051088
+:102FE0003A8821B006020000269300183A88219002
+:102FF00047008080440080845809C0101EFA3F10AA
+:103000003AC8A39526960088171EC0D8171D80D8E9
+:10301000150080453A88471C44008010151D80D853
+:1030200015014044151EC0D8080280101E850010EE
+:10303000040200421704C0D8470080803A88471C29
+:103040001504C0D826860010470080924400809561
+:10305000451500D83A8809003A880B00C4FFFF02E2
+:103060003A8823003A881900440080B53A883950DC
+:1030700004F8BFE06816C0101E9B0018BA90041038
+:103080003400C2003A88C71017F68B183A6800104F
+:10309000003300083032000830320008F4320008F3
+:1030A0003032000830320008303200083032000878
+:1030B0003032000830320008CC320008BC32000840
+:1030C00030320008A43200086032000830320008B4
+:1030D00054320008003200080032000800320008B4
+:1030E00000320008003200080032000800320008F8
+:1030F0000032000800320008303200083032000888
+:103100003032000830320008303200083032000817
+:103110003032000830320008303200083032000807
+:1031200014380008343700083032000834370008FB
+:1031300030320008303200083032000830320008E7
+:10314000283700083032000830320008F436000812
+:1031500030320008303200083032000830320008C7
+:1031600030320008343900083032000830320008AC
+:10317000EC380008303200083032000830320008E5
+:103180003032000830320008303200083032000897
+:103190003032000830320008303200088434000831
+:1031A000103400083437000834370008343700087A
+:1031B000043A0008103400083032000830320008A9
+:1031C000F039000830320008B436000874360008C0
+:1031D000743900086839000830320008B433000838
+:1031E00030320008743300083032000830320008F2
+:1031F0002C330008170500D93A880B98C0070580C2
+:103200001E4C07100B0380988C06801098028010CB
+:103210001E633F108F03809816613F101706C0D9B8
+:10322000170500D93A880DA03A880B98C0FB048096
+:10323000150480D8061300003AC8A39526823F885B
+:1032400006713F00170500D9041C80D93A880B98F5
+:10325000803F0A801E0800103A8811B806753F00AA
+:10326000171E80D826040010170500D9041C80D929
+:103270003A880B98803F0A800B0380980C108010CE
+:103280001E2C0710170480D81742C0DF174100DF3B
+:103290001740C0DD173F80DD173E40DD173D00DDE4
+:1032A000173CC0DC173B80DC173A40DC173900DCE8
+:1032B0000443C0DE3A2800F83A88230004F4BFE053
+:1032C000440080B5A402408CC7FF3FB73A8863141E
+:1032D00004F4BFE0B002C0101EF93F1804F8BFE0CC
+:1032E0006816C01026653F18CC3F00211E6D0620D1
+:1032F00026DB3FE0051F00DF451500D844004005F0
+:1033000044000005041F00DC069500001420006343
+:10331000070080B206543F00070000B74400C0B069
+:10332000A00A80E01E41071004F4BFE0B002801143
+:103330003A882D183A881700264D3F30440080B552
+:10334000A402C05AC7FF3FB73A88975804F4BFE0B9
+:10335000B002C0101EF93F1806453F00030000B739
+:10336000CC3F80E21C2080521401006304E0BF5275
+:10337000063D3F0044000001C40A4001070080B23E
+:1033800006393F00170680D8030000B71700401425
+:103390000401801016D70488150680D8CC3F80E23F
+:1033A0001C20805204E0BF52062F3F0054000063EF
+:1033B000070080B2062C3F00CC3F80281C208010E4
+:1033C00004E0BF10030000B71EF43F10CC3F80E2C2
+:1033D0001C208052440000010408400104E0BF5258
+:1033E00006213F00CC3F00211EB30620340182009D
+:1033F00004209D10150C80D80C08806026700110E8
+:10340000170680D817004015170100150402801018
+:10341000150680D84C008060260200103AB004AD3A
+:103420001EA7041084008000068F0100CC3F0021FD
+:103430001E9F06200C0880601EB40110170680D85D
+:103440000C04C06017004015040180101E6E0118A6
+:103450000C10C060269F0518150680D8CCFF7FADE4
+:103460003A88290044008000067F0100170680D8B2
+:10347000451500D8170000140401801426C70480E5
+:10348000150E00DA150700DBE0FFBF581E690510B6
+:103490003A880D583A880B003A8809801506C0DA38
+:1034A000005D08801706C0DA170700DB170E00DA88
+:1034B000266706103AC829143A882BA016F705A0EB
+:1034C000150680DC06260000CC3F00211E76062073
+:1034D0000C0880601E7F0110170680D80C04C060A5
+:1034E000040180101E0001180C10C06026FE001898
+:1034F0001706C0D8150680D80F00401DFAD729A896
+:103500003A8805A016FE0010D8FFBF58431540DBCF
+:1035100026850110C4DFFF003AB004AD3A70D860D0
+:103520001E8101101E8301583A8825603A881700D1
+:103530003A8829003A8821B8068301001706C0D8C6
+:10354000451500D844004005170080180401C01834
+:103550001506C0D8051F80D844000005041F00DCF4
+:103560003A8825603A881700150700D88C008093A8
+:1035700026010070840040AD0C214093171EC0D876
+:103580001E0200683AC84F8D16CEC201471580D87A
+:10359000260C0010171D80D8441500D94400C0180F
+:1035A000440080101500004144000001151D80D822
+:1035B00015010041151EC0D8080280101EFB021024
+:1035C00004020042260C0070171D80D8841500D913
+:1035D0008400C018440080101500004184000001E0
+:1035E000151D80D815010041151EC0D80802801095
+:1035F0001EFC0210040200421820406B26CF016816
+:103600003AC80F5D1606C2010C4080901E7C011066
+:10361000171D80D83A88071D15000044440080100B
+:10362000151D80D815010045151EC0D80802801050
+:103630001E570210040200420C01809426020090E2
+:103640003AC8618D160900040E01408D3A8823A8FE
+:10365000170480D83A884514150480D81E2402180F
+:10366000151D00D83A8811B806593E0034010203EE
+:1036700050040081842B1D63171D80D81E1C002060
+:1036800004048004170500DD3A8839600604000050
+:1036900004FC3F84480400810402004226130020F9
+:1036A000440080100404C018150000471501804430
+:1036B000151EC0D8151D80D80802001126F43F2021
+:1036C000041C80D93A880B983A8809A0803F0A8068
+:1036D0001EE93E1004FC3F8448040081171EC0D838
+:1036E000171D80D83A8811B81EED3F203A8819E09E
+:1036F000440080103A88071C151D80D8150000432F
+:1037000015010044151EC0D8100280101ECE3F10B7
+:10371000170500D9041C80D93A880B98803F0A808D
+:103720001ED53E10171EC0D806C73F00CC3F002153
+:103730001ED905200C0880601EED0010170680D8E9
+:103740000C04C06017004015040180101E1E0018F4
+:103750000C10C06026DB0418150680D8CCFF7FADA6
+:103760003A8829003A88050006BF0000CC3F0021B6
+:103770001ECB0520170600D90C0880600401C0206C
+:103780001ED503100C0480601E3004100C10006362
+:10379000262E0460170680D81506C0D81704C0D896
+:1037A000170080100D00C01006093E00CC3F00211C
+:1037B0001EC305200C088060140400631ECC00109A
+:1037C000170680D8040180101706C0D83A8829004F
+:1037D000150680D81700401D3A88050006A2000093
+:1037E00014020063070080B2061F3E00CC3F002198
+:1037F0001EB705201706C0D83400A000C4FFBF10B4
+:103800001701001D1700801C34FCDF013A70A0A0D6
+:10381000C4FFBF0104028018C4FFFF393A88099031
+:103820003A880B80150F00DA150EC0DA150700DB99
+:10383000150A00DD150980DC150680D880550F803B
+:10384000170700DB170EC0DA170F00DA1E16031079
+:1038500034FCDF01C4FFBF01C4FFFF393A8809907F
+:103860003A880B8000470E80170700DB170EC0DA7E
+:10387000170F00DA0E0C83003A880D003A880F000B
+:103880003A8809903A880BA0150E00DA00470E809E
+:10389000170700DB170E00DA16E20410431540DBB1
+:1038A000101280E01ECB04103401020404181D84A1
+:1038B000C4DFBF043A70A464C4004005C40000051E
+:1038C0003A881700150700D806A30000CC3F002156
+:1038D0001E7D05200C088060140400631E7D00100E
+:1038E000170680D8040180101706C0D81700401DA5
+:1038F000150680D8FAD729A83A8805A00E023F10ED
+:103900003AC86B053AC004A83AC829053AC8A9A024
+:10391000440B8000451580D8E0FFFF58440B40035E
+:1039200044008000265400186000C0101E7E00185D
+:10393000A00080101E3702103A8807B80601000068
+:103940003A880780FAD008A87A970AA0FAD028A067
+:10395000CC0140AD040C80A83AB02A29C5FFBF189D
+:103960003AB008ADC4FF3F1C1EF53F204C0000617B
+:1039700026A00020CC3F80101C20801004E0BF1047
+:10398000180C8010269B001084FFFF18040C800088
+:10399000C5FFBF803AC8E9B83A8825603A8821183F
+:1039A00006690000CC3F00211E3905203401820049
+:1039B000041B9D10150C80D80C0880601E903E10D2
+:1039C0001706C0D80C0480601700401D0401C01801
+:1039D0001506C0D81EAE02100C10806026AC021076
+:1039E000CCFF7FAD3A882900068A3E00CC3F0021FB
+:1039F0001E3905200C088060140400631E4300106B
+:103A0000170680D8040180101706C0D83A8829000C
+:103A1000150680D81700401D4400800006120000E3
+:103A200014080063070080B2068F3D001706C0D857
+:103A3000040C8000851580D8041E8000340102012A
+:103A4000C51580D81700401D04018018150680D8C0
+:103A500004209D20150C80D83A882900940000632A
+:103A600084008000041E0007451500D8E0FFFF58C1
+:103A70003A881B001EAC3F18C4DFBF043AB006AD45
+:103A80003A70A4641E8D01181EB903581EA73E107B
+:103A90004C000065268202A0040C8000C52880D856
+:103AA000C42800DC06280000070080B2181B8050E4
+:103AB0002629031014040063066B3D0014100063F4
+:103AC000070080B206683D00170500D90006078090
+:103AD00006233D001706C0D8170180181700401DA7
+:103AE0000402C0181506C0D83A88291006853E0081
+:103AF0001706C0D83A8805001700401D1701001DA1
+:103B00000402C0181506C0D806D73F001706C0D853
+:103B1000440080001700401D1701001D0402C0185A
+:103B20001506C0D806D03F001E1100A0A80280A82C
+:103B30001E0F0010040C40ADC52840DD3A882560FA
+:103B400044000005C42800DC3A882B580E01005DB3
+:103B50003A882BA0150700D8CC3F406B1C20406B47
+:103B600004E07F6B26813E68440040AD067F3E0046
+:103B7000150E40DC3A8821B83A8823A0150700DBEF
+:103B80003A882998150FC0DA3A8825403A8827687C
+:103B9000060200003A882B103A8823183A8809A8B0
+:103BA0003A880B88840280013A880F00009C0C80C0
+:103BB000040C8010C4FF3F843A8809A83A880B8817
+:103BC00005008080840280013A880F0080420C80CA
+:103BD0001EF03F88A80240AD1EEE3FA8170700DB8D
+:103BE000170E40DC170FC0DA3A881B983A881190FC
+:103BF0003A8827A03AC829BC3A88256006D23F00F7
+:103C0000901980E21EEA0050170900D9170A40D91E
+:103C10003A880D003A880F00150F00DA150EC0D84B
+:103C200000300E80170EC0D8170F00DA1E89011061
+:103C3000171D80D83401020104271D214400801083
+:103C40004400C0181500004144000001151D80D833
+:103C500015010041151EC0D8080280101E33031044
+:103C600004020042171680D81708C0D81604C010E6
+:103C70004C0080901E020010171EC0D8066E3E0039
+:103C8000170D80D8171EC0D8170B00D9150080401B
+:103C9000171D80D83A88C7201501004144008010C4
+:103CA000151D80D8151EC0D8080280101EB1021044
+:103CB00004020042170880D8C4FF3F140E5E3E0481
+:103CC000340102035004008184271D63171D80D82E
+:103CD0001E730320150740DC04040005170500DFF0
+:103CE0003A882360060400000402004204FC3F847A
+:103CF0004804008126680320440080100404C01892
+:103D00001500404415010045151EC0D8151D80D86A
+:103D10000802001126F43F20041C80D93A880B9831
+:103D20003A8809E0803F0A801E533D10171EC0D814
+:103D3000171D80D83A8811B806EC3F003AC84F8D5D
+:103D40000E2FFE01340102035004003984271D6345
+:103D5000171D80D81E270020150E00DC150F80DCF3
+:103D6000151040DC040440033A8821381512C0DAEB
+:103D7000170540DC3A8825600604000004FC3F84F7
+:103D800048040081040200422614002044008010F0
+:103D90000404C0181500804415014043151EC0D806
+:103DA000151D80D80802001126F43F20041C80D97C
+:103DB0003A880B983A880988803F0A801E2E3D1069
+:103DC00004FC3F8448040081171EC0D8171D80D80A
+:103DD0003A8811B8040440031EEC3F203A880F8053
+:103DE0003A881990170E00DC171040DC1712C0DA61
+:103DF000170F80DC440080103A88C719151D80D841
+:103E0000150000431501C041151EC0D808028010DE
+:103E10001ECD02103AC80F5D040200420EFAFD01E9
+:103E2000340102035004003984271D63171D80D814
+:103E30001E250020150E00DC150F80DC151040DC5F
+:103E40000404C0023A882138170540DC3A8825600E
+:103E50000604000004FC3F84480400810402004280
+:103E600026140020440080100404C018150080446B
+:103E70001501C042151EC0D8151D80D808020011BA
+:103E800026F43F20041C80D93A880B983A88098888
+:103E9000803F0A801EF83C1004FC3F8448040081E7
+:103EA000171EC0D8171D80D83A8811B80404C00264
+:103EB0001EEC3F203A880F803A881990171040DC9A
+:103EC000170E00DC170F80DC440080103A88C719F9
+:103ED000151D80D8150000431501C041151EC0D81E
+:103EE000080280101E6201100402004206C63D0056
+:103EF000170500D9041C80D93A880B98803F0A80A6
+:103F000026D73D1006DC3C00170500D9041C80D9DB
+:103F10003A880B98803F0A801ED73C10171600D9AC
+:103F2000171EC0D83A8811B81E950220170800D96C
+:103F30004C0080903AB0041126BF3D10170D80D878
+:103F4000170B00D915008040171D80D83A88C7206C
+:103F50001501004144008010151EC0D8151D80D8E1
+:103F6000080200111E64032004020042170800D951
+:103F700044008010151D80D83A88C72015000044E1
+:103F800015010041151EC0D80802801026A93D1059
+:103F9000170500D9041C80D93A880B98803F0A8005
+:103FA0001EB53C10171EC0D83A8811B806A23D00B5
+:103FB000170880D8171D00DF4400C0188800801043
+:103FC000440000E50402804226FB0010440080000B
+:103FD0001501804015000044151EC0D8151D00DDD8
+:103FE000100280A0262C0210170B80D8170D00D9C4
+:103FF000440000A53A88871815018050150000512B
+:10400000151EC0D8151D00DD080280A01E19021063
+:1040100004028052170880D8170900D9170A40D91E
+:1040200004020052C4FFFF12440000A73A880D00AA
+:104030003A880F001512C0D8150F80DA150E00DA75
+:104040001507C0DA151000DF00300E801707C0DA40
+:10405000170E00DA170F80DA171040DB1712C0D8DE
+:1040600026E10010440000843A88C71A151D00DFBD
+:10407000150000541501C052151EC0D8080200E7F3
+:104080001EAA01E004048050840000A73A8815406D
+:104090003A881110171100D9441880D8151D00DF77
+:1040A0003A88C7201500805015010051151EC0D850
+:1040B000100200E71E603DE006B53F003A88199007
+:1040C00006193E003401020350040039842B1D639D
+:1040D000171D80D81E2B0020151000DC151280DC67
+:1040E000151340DC0404C003150E80DB150F40DB04
+:1040F0001514C0DA3A882138170540DC3A88256063
+:104100000604000004FC3F844804008104020042CD
+:1041100026140020440080100404C01815008044B8
+:104120001501C043151EC0D8151D80D80802001106
+:1041300026F43F20041C80D93A880B983A880988D5
+:10414000803F0A801E4C3C1004FC3F8448040081E0
+:10415000171EC0D8171D80D83A8811B80404C003B0
+:104160001EEC3F203A880F803A881990170E80DBAA
+:10417000170F40DB171340DC1714C0DA171000DCF0
+:10418000171280DC440080103A88C719151D80D8AA
+:10419000150000431501C041151EC0D8080280104B
+:1041A0001ED401100402004206F83C00170500D995
+:1041B000041C80D93A880B981510C0DA150F40DB23
+:1041C000150E80DB803F0A801E2B3C10171EC0D8C6
+:1041D0003A8811B81710C0DA170F40DB170E80DBD2
+:1041E00006F83C00170500D9041C80D93A880B98C2
+:1041F000150FC0DA150E40DB803F0A801E1E3C10F2
+:10420000171EC0D83A8811B8170FC0DA170E40DB56
+:1042100006F93C00170C00D93A8821B8CC0380A8D5
+:104220003A9706A03A8885203AD12AA80300801040
+:104230003AD128A0C4FF3F843AB06A1D05008080AF
+:104240003AB004AD1EF53F103AC829BC3A88256043
+:10425000063D3E00171600D90E980101170780D8B9
+:10426000170800D93A883910162581200E0A000750
+:10427000171D80D83A88071F15000044440080109D
+:10428000151D80D815010047151EC0D808028010E2
+:104290001ED9021004020042163E01E0170780D822
+:1042A0003AC8391716450107171600D9170880D8DC
+:1042B0000E168120170D80D8170B40D915008040AD
+:1042C000171D80D83A8847191501404144008010D5
+:1042D000151D80D8151EC0D8080280101E6002105F
+:1042E00004020042170880D8170740D93AC80511C0
+:1042F0000E5C01293A8839100E0C0007170700D907
+:104300003A88071F150100473A882181171D00D9F7
+:1043100015000044151EC0D844000021151D00D909
+:10432000080200211EBF0220040200420E0100E02C
+:104330003A8839003AC839170EBF3C0734010203E6
+:10434000500400E184271D63171D80D81E3B022006
+:10435000150740DC04040005170500DC3A882360DB
+:10436000060400000402004204FC3FE7480400E1A8
+:1043700026300220440080100404C0181500404478
+:1043800015010045151EC0D8151D80D80802001162
+:1043900026F43F20041C80D93A880B983A8809807B
+:1043A000803F0A801EB43B10171EC0D8171D80D84E
+:1043B0003A8811B806EC3F004C0080901E033F1075
+:1043C00044008000151D00DD1500004415018040EB
+:1043D000151EC0D8080200A51ED400A0840000E766
+:1043E00004040042062B3F000E2AFF0250048058AE
+:1043F000340102031EF8021084271D63150780DCB8
+:10440000150E40DC040400043A882358170500DF29
+:104410003A8825603A88296806050000040280521F
+:1044200004FC7F8C48048088268A0110440000A583
+:104430000404C0181500805415010054151EC0D87E
+:10444000151D00DD080280A026F43F10041C80D951
+:104450003A880B983A8809E0803F0A801E863B1014
+:10446000171D00DD171EC0D83A8815B806EC3F00AE
+:10447000170500D9041C80D93A880B98803F0A8020
+:104480001E7D3B10171EC0D83A8811B8065E3C004E
+:104490003A88290006DF3B003A8825B006EA3A0050
+:1044A0003A8821B806A83D00170900D9170A40D953
+:1044B000150F00DA3A880D203A880F28150EC0DA59
+:1044C000150700DB80550F80170700DB170EC0DAD9
+:1044D000170F00DA1EAF0210C4F7FF003A70C6E0F3
+:1044E000E0FFBF581507C0D81E4C0210D811801825
+:1044F00026FE0110170A80D81440806416E10110CE
+:10450000170A40DD050E00D8A01980E0150F80D8ED
+:104510001E740110A01180E01E720110170780D8D0
+:10452000151200DA151000DB581180102605021054
+:10453000041A80D8150380D8170940D9041780D8E9
+:10454000170500D9150280D8041680D81500C0DAE6
+:10455000150180D88400C0013A880DA81508C0DA7A
+:10456000C03E05801708C0DA3A882110D81980E0CB
+:10457000171000DB171200DA3A8829581E030210C0
+:104580004C0080601E0302101716C0D8170780D891
+:104590001507C0D8171AC0D8E01180103AC8071CF8
+:1045A0001508C0D8260500101707C0D850FFBF183F
+:1045B0001E0100100E05C25884FF3FE7170780D880
+:1045C000451800DFC4FF3F15151600DD167902A05F
+:1045D000C40A8000851880D8900280A01E5802105E
+:1045E000150700DCC41B40DD3A8821A0150F00DB55
+:1045F0003A8829983A882740060200003A882B20FA
+:104600003A8821103A8809808402400100F80C8021
+:10461000040C80103A880980C5FFBFA884024001BD
+:1046200000F00C800819C080C4FF3FA91EF33F189A
+:10463000040C8010C5FFBF2084FFFFA8C41B00D955
+:104640003A881198170700DC170F00DB3A8827A07B
+:104650002E730219C41800D9060100000300801847
+:1046600044000021C5FFBF204400C018C41B80D8EF
+:104670001EFABF18441C80D8C418C0D83AC84515C3
+:104680003A8885184418C0D83AC8C510151180D882
+:104690001708C0D8171100D9880080183A8829193E
+:1046A00026490210170B80D83A88A9A03A882BA077
+:1046B0000E0100A03A882B00150700D8063F010024
+:1046C000040C8000851580D8C51500DF94000063B8
+:1046D0008400800006E43C00170440D917008020C5
+:1046E0001506C0D8FAD70928150040111501001188
+:1046F00006373A003AC86304150680D806183B000E
+:104700003A88392016DA3E0706E33E004C008090D6
+:104710001EE83E10170880D8170740D93AC805117F
+:104720000E5000293A88391006003F00170500D9BD
+:10473000041C80D93A880B98803F0A801ECE3A101C
+:10474000171D00DF171EC0D8042B00DA440000E755
+:104750003A8815B8064F3E00430000B714080063BE
+:10476000440080B5CC3F80E21C20805204E0BF5260
+:10477000063D3A00170500D9041C80D93A880B98E9
+:10478000803F0A801EBC3A10171EC0D83A8811B864
+:1047900006483D003A88390006C03E00F0018058C6
+:1047A0003A882958263B0110340102043A882BA08C
+:1047B000150680DC04251D8406693B0034010203D4
+:1047C000500400E184271D63171D80D81E0B0120B3
+:1047D0003A8809B0150E00DC150F80DC3A882D8868
+:1047E000040400053A8823E0170500DC3A882560B8
+:1047F0003A883920060400000402004204FC7F8C41
+:104800004804008926F60020440080100404C018E3
+:104810001500804415010045151EC0D8151D80D80F
+:104820000802001126F43F20041C80D93A880B9816
+:104830003A880980803F0A801E8F3A10171EC0D820
+:10484000171D80D83A8811B806EC3F00170680D8AB
+:10485000170080101506C0D81704C0D81500C01066
+:1048600006DB3900170800D9170740D93AC8792163
+:1048700006A13E00170500D9041C80D93A880B9880
+:10488000803F0A801E7C3A10171EC0D8171D00DD1D
+:104890003A8815B806DF3D00170500D9041C80D9F9
+:1048A0003A880B98803F0A801E733A10171EC0D8B2
+:1048B000171D00DD3A8815B806CB3D00171D80D8BE
+:1048C0003401420104275D29440080104400C018CF
+:1048D0001500404144004001151D80D8150140419C
+:1048E000151EC0D8080280101E873D100402004229
+:1048F000068D3D00170500D9041C80D93A880B9815
+:104900001510C0DA150F40DB150E80DB803F0A80E2
+:104910001E593A10171EC0D83A8811B81710C0DABD
+:10492000170F40DB170E80DB06183B00170500D978
+:10493000041C80D93A880B98803F0A801E4E3A109A
+:104940003A8811B806C73C00170500D9041C80D965
+:104950003A880B98150EC0DA803F0A801E463A103E
+:10496000171EC0D83A8811B8170EC0DA06243B00CB
+:104970006000C0103A88199026ED3B18066D3C0087
+:10498000170D80D8170B40D915008040171D80D80F
+:104990003A88C7281501404144008010151EC0D830
+:1049A000151D80D8080240111ED3002804020042C1
+:1049B0000E6E3D203401020308FC7F2184271D6315
+:1049C0003AC829011E4A0128150700DC0404000723
+:1049D0003A8821A03A8829883A8823600604000092
+:1049E0000402004204FC3F8448040081263C01206C
+:1049F000440080100404C01815004044150100470D
+:104A0000151EC0D8151D80D80802001126F43F20BD
+:104A1000170500D9041C80D93A880B98803F0A807A
+:104A20001E153A10171EC0D8171D80D83A8811B825
+:104A300006EC3F003A880980C0DA02803A882910E3
+:104A40003A882B10150680DC170700DB170E00DAFA
+:104A500006C33A003A8817883A881990170E40DC46
+:104A6000170780DC440000A7040280503A88C71A68
+:104A7000150000531501C052151EC0D8151D00DFCA
+:104A8000080200E11E293F20440000E70402001252
+:104A90003A881510067F3D003A881988170740DCD0
+:104AA000440080103A88071C151D80D8150000436B
+:104AB00015010044151EC0D80802801026DD3A10EA
+:104AC00006333D00150680D83A8829003A8805004B
+:104AD00006E53B00150680D83A882900440080008E
+:104AE00006E13B00041A80D8150380D8170940D985
+:104AF000041780D8170500D9150280D8041680D86D
+:104B00001500C0DA150180D8C400C0013A880DA88C
+:104B1000151200DA151000DB1508C0DAC03E05805A
+:104B20001708C0DA3A882110171000DB3A88E9121A
+:104B300007008080171200DA200C80101E5B001026
+:104B4000171680D83A88A9A0170900D93A880D000D
+:104B50003A880F003A880BA8151200DA1510C0DA4F
+:104B6000150800DB00300E80170800DB1710C0DAD4
+:104B7000171200DA1E8900103A8805A03AC80514F9
+:104B80001707C0D8150880D8171680D8D811C018B4
+:104B9000150780D826843E18170F80D826873E1028
+:104BA0001707C0D84C0080603AB0C4120E0DC10087
+:104BB0001EF10010170700DD3A882BA0070E80D8E1
+:104BC000267F0010440B8000451580D83A881700D6
+:104BD00006E53B003401020404171D8406343B0043
+:104BE0003A881990170E00DC170F80DC3A8809E02C
+:104BF0003A8839883A8823B03A882D2044008010BA
+:104C00003A88071F151D80D815000043150100477D
+:104C1000151EC0D8080280101E4200100402004277
+:104C200006A13D00440B8000451580D8440B40038D
+:104C3000061B3B003A881988170740DC44008010A7
+:104C40003A88071F151D80D815000043150100473D
+:104C5000151EC0D80802801026763A1006CC3C00FB
+:104C6000170500D9041C80D93A880B98803F0A8028
+:104C70001E813910171600D9171EC0D83A8811B8EE
+:104C800006983D003C006015440B8000050E80D85E
+:104C9000061D3E008401000506C33E003A882B0035
+:104CA00006073A00451540D906913900170900D981
+:104CB0003A880D003A880F003A880BA8151200DADE
+:104CC0001510C0DA150800DB00300E80170800DB75
+:104CD0001710C0DA171200DA26993F10440080003E
+:104CE0003AC8C512151680D806963F001E013E58D8
+:104CF0004400C00206FF3D00170500D9041C80D9FE
+:104D00003A880B98803F0A801E5B3910171600D92D
+:104D1000171EC0D8171D80D83A8811B80E933C20B2
+:104D200006243F00170500D9041C80D93A880B9847
+:104D3000803F0A801E503910171EC0D83A8811B81B
+:104D400006593D00041A80D8150380D8170940D9A8
+:104D5000041780D8170500D94400005D150280D8DB
+:104D6000041680D8150180D8150000DD8400C0012C
+:104D70003A880DA81508C0DAC03E05801708C0DAC9
+:104D8000171000DB171200DA3A882110D81180E0E2
+:104D900026FB3D103A882985066B3F00171A80D8FC
+:104DA000040C00012E753F154400C010151AC0D820
+:104DB00005000011171A80D836FB3F15066F3F001B
+:104DC000431540DB3A88170006633B00170780D87D
+:104DD0001708C0D81622C0104C0000631E5F006088
+:104DE0003A882B100E0100103A882B00170700DDBF
+:104DF000C419000706713F00170500D9041C80D9AB
+:104E00003A880B98803F0A801E1B3910171EC0D8A5
+:104E10003A8811B80E213DE0065E3E008401C002D2
+:104E200006B43D00170500D9041C80D93A880B98B8
+:104E3000803F0A801E103910171680D8170800D935
+:104E4000171EC0D83A8811B83AC8852006373D00E9
+:104E50003A882B58150680DC3A88295806C0390054
+:104E6000170880D8170BC0D83A88E910170780D8E0
+:104E700016038000170780D83AC8B9A0440000E59F
+:104E80003A882BA0163A00A0C4190007064B3F0031
+:104E9000451540D906C53A00451540D906253A00C2
+:104EA000451540D906333A00451540D906883900E2
+:104EB000451540D9065F3900451540D9064B3900E4
+:104EC000451540D9063B3A00451540D906813A00C0
+:104ED000451540D906473A00451540D906C53A0060
+:104EE0003A8819883A8823A03A882980170700DC75
+:104EF000440080103A88071D150000431501004545
+:104F0000151EC0D8151D80D80802001126163C2099
+:104F1000170500D9041C80D93A880B98803F0A8075
+:104F20001ED53810171EC0D8171D80D83A8811B862
+:104F3000060E3C00C4FFBF00150480D806D138001F
+:104F4000040C8000040CC0A0C51880D804018000A7
+:104F50000519C0D8151180D806CD3D00170780D897
+:104F6000170BC0D83A88E9103A882BA00EC63FA08C
+:104F70003A882B0006C43F00170B80D83A88851862
+:104F80003A88E9123A882BA00E0C3FA03A882B00F1
+:104F9000060A3F00170A80D8161D0010431540DB93
+:104FA000101280E01E17001034010204041A1D8440
+:104FB000063F3A004400C0003AC8A918440B8000DC
+:104FC000851880D806843D004C008060150780D885
+:104FD0001EB43D1006EB3F003A88054084271D6350
+:104FE00006A23E001E0300104400400544000005D8
+:104FF00006F23E00170B80D8440080103A88E91270
+:1050000006E03F003401020404191D8406283A001A
+:10501000440B8000451580D8440B400306E03F0058
+:1050200084008000151180D806993D00170680D8AD
+:105030001700C012040180100E010058C4FFFF02C7
+:10504000430000B7150680D83A882D18CC3F80E27F
+:105050001C20805204E0BF52060338007401820015
+:105060003A880F303A880D283A880B2017AF321152
+:1050700041E402800B0380281719002B8B03C02A00
+:105080001707802A1709402A04E2FEDE041A00DA14
+:105090000400C100151A01DC4CFFBF103A8821281A
+:1050A0003A880BD8151C81DC151B41DC151DC1DFAE
+:1050B0003A8825200D0380D8151900DB8D03C0DA4E
+:1050C000150780DA150940DA150000DA150400DA50
+:1050D0001502C0D81505C0D8150600D840E40280D6
+:1050E0003A8823100E0D00100B0380D80C1080108E
+:1050F000260300100B038080141080100D038080A5
+:105100003A880588171DC1DF171C81DC171B41DC9D
+:10511000171A01DC041EC1DE3A2800F83A880BD8C1
+:105120003A880990C0CD068026EF3F10C4FF7F0467
+:1051300006ED3F007401820017AFB21004FDFFDEE0
+:10514000150140DC150000DC1502C0DF3A88232081
+:105150003A88212826020010170EC01026200018B9
+:105160000B0380800C02C0103A8809102622001818
+:105170001704C080262800184C0000111E0B0020C8
+:105180008C0080101E2D0010170580801502808075
+:10519000260B00183A8805001702C0DF170140DC13
+:1051A000170000DC0403C0DE3A2800F817058080F1
+:1051B000150200803AC88500150680801EF53F184C
+:1051C0000B03C0803A8805000C20001926F23F200E
+:1051D0001410C0180D03C080C4FFBF0006EE3F00CE
+:1051E0003A880910000607800B0380800C02C0106B
+:1051F0003A8809101EDE3F180C048020261F00107C
+:105200000C0180201E0F00101704C08014028020A3
+:105210000D0380801ED83F180CA0001120800021B3
+:105220001ED53F203A880B803A88098800CA07803B
+:105230000B0380801704C08006CF3F003A8805002A
+:1052400006D23F00170C40812606002804108080FB
+:10525000260380283A880988401C07800B030081B8
+:10526000150C00801704C080C4F6BF003A70081106
+:10527000150100801500C08006E43F004402800054
+:1052800015008088141080200D038080C4FFBF00AB
+:1052900006C13F0004F5FFDE150380DC1704802003
+:1052A0001704802C150AC0DF150900DF1508C0DDC2
+:1052B000150780DD150640DD150500DD1504C0DC91
+:1052C000150240DC150100DC16748014C4FFBF9485
+:1052D000BA902E900405402C040540253A88E98DAB
+:1052E000170000A73A88EFAD1700C0B8440000E7E8
+:1052F0003A882D283A8821203A880BE03A88091804
+:105300001500C0D880FF0C801700C0D83A8827103D
+:10531000362C001F3A8811883A880BA83A88130067
+:105320003A8807000401004217FFFF411700802957
+:1053300004014029CCFFBF383A38C5143AD40838A4
+:10534000CCFFBF323A8845123AD41210CCFFFF117D
+:105350003A38C9243AC8C7193A888F1A3AD406305D
+:105360003A8849223AD40538CCFFBF213AC8871978
+:105370003A8887183A940C18CCFFFF393AD4122097
+:105380003AB0CE3115FFFF293AD407182EE53FA2D7
+:10539000170080B81E0B001004FFBFB82E0880A8AD
+:1053A00017FFFFB826030018060500001700C010FD
+:1053B0001E03001804FFBF10C4FFBF9436FBBFA834
+:1053C000150480843A880BB03A88098080250980CA
+:1053D000162500104400C09C3A880DA83A880700A2
+:1053E0000401408C17FF3F891700403104018031D0
+:1053F000CCFFBF203AC88718CCFFBF283A88851851
+:105400003AD408203AD406283AD40F10CCFF7F11A2
+:105410003AC807193A88C7193A9404183AD40718B1
+:105420003AB0441115FFBF302EED7FA4BA9006901C
+:105430003A88C7A8170080181E0B001004FFBF1879
+:105440002E0880A817FFFF18260300180605000085
+:105450001700C0101E03001804FFBF10C4FFBF9444
+:1054600036FBBFA8150480843A880598170AC0DF68
+:10547000170900DF1708C0DD170780DD170640DDBC
+:10548000170500DD1704C0DC170380DC170240DCC1
+:10549000170100DC040BC0DE3A2800F83A8805004A
+:1054A00006F23F001710802004E2FFDE151C00DF2B
+:1054B0001517C0DC151540DC151400DC151DC0DF08
+:1054C000151BC0DD151A80DD151940DD151800DD2E
+:1054D000151680DC150140D91502C0D93A8839204B
+:1054E0003A882730172000DC3A882330260800103D
+:1054F000171180214400C0003A880B103A98861991
+:10550000150180111502C01080A70880151000E059
+:1055100016810198150000802CFC9F9834FCDF0058
+:105520002686C110170100D93A880D003A880F006D
+:105530003A880B8800300E801E190010171FC0D843
+:105540004400800015008018172180D826240310FD
+:10555000172100D93401820044279D103401C20074
+:105560001500802004279D18150380D8170380D8C4
+:10557000171DC0DF171C00DF171BC0DD171A80DDE9
+:10558000171940DD171800DD1717C0DC171680DC6F
+:10559000171540DC171400DC041EC0DE3A2800F8A2
+:1055A000170180DC041280D83AD52098150080D8E5
+:1055B0000413C0D93A880B903A880D883A8809E0DC
+:1055C000C05C09803A882B101E700180171280DCA5
+:1055D000171300DC3A882194840C81805008C01095
+:1055E0001E0F0318041000013AC885203A98A698A7
+:1055F000170180D8840401813AD808113AB008997B
+:10560000406F0F803A88091034847F014400800085
+:105610003A884B19C4FF3F84150A80D83A880D0098
+:1056200034FECF01C0BE0E80F4DB9801F4F4CF014C
+:1056300044D89031C4E9E1393A8809103A880B1806
+:1056400000560E8074D8A201F4F1CF01C42CB231FF
+:10565000048AE2393A880B183A880910800B0D80C9
+:105660003A8809803A8829103A882718C0620F8042
+:10567000F4279401F4F4CF01C47E9E31C404D139DF
+:105680003A8809103A880B1800560E803A880D1097
+:105690003A880F183A8809A03A880B98800B0D8039
+:1056A0003A8809103A880B183A8829103A8827183E
+:1056B000C05A0F803A880D003A880F003A8809A036
+:1056C0003A880B983A882D1000470E8016BA0210BF
+:1056D0003AC82194E80580B0C4FF3F851EAE021091
+:1056E000FA9006B034018200044B9D103A88C51030
+:1056F000170080111701C011170100D93A880B88D3
+:1057000000470E800E6F0210150900D8C4FFBFB508
+:1057100016A402A0150500D80E6D02B0170580D89A
+:105720001702C0D8150480DD3AC88515150580D844
+:105730003AC88505150880D8A80280183A882D0037
+:105740001E690210900180181EBA021004FFBF18D3
+:10575000150280D83A8821001702C0D8E0008018CE
+:105760001E9D031008018018267A02101702C0D867
+:10577000200180182669021044008000150780D897
+:10578000171E80D80E678300150B80D8150680D8A9
+:105790003A880D10151100E010068030170680DCE5
+:1057A0001EEB04104400C000040180003A888510FC
+:1057B000040500113A880B184400C0182EFB3F3135
+:1057C000151140E13A8809E0409D0880150380D812
+:1057D000151080E0E80380941EFE009026FD0080F6
+:1057E000170400D90EC60301CC038020FA900610DE
+:1057F0003AD12F2034018200044B9D103A88C51005
+:105800000C04C0B817008012170140121E62031862
+:10581000170180D83A88278884000004150C80D8A6
+:105820003401820404419D94260F00B83A88055043
+:105830003A8807484C0080B93A8809107AD02FB8C6
+:105840003A880B1826040030170080911701C09188
+:105850004400008400560E80040280941EF53FB878
+:105860003A8815103A881318170C00D93A880B9803
+:105870003A880D503A880F4880A50D803A88251047
+:105880003A882718170980D8260600103A880D0094
+:1058900034FCCF013A8809903A880B9800470E8073
+:1058A000162604103A880980C0620F803A880D904D
+:1058B0003A880F983A8809103A880B1800560E80DB
+:1058C0003A880D003407D0013A8809103A880B183D
+:1058D000800B0D80150C80D83430BF003A888518B5
+:1058E000150D80D8170680D8266D0310170480D8B0
+:1058F000150F80D8170680D8150E80D83A880B98D7
+:105900003A880990C05A0F803A8809103A882F10B7
+:10591000C0620F803A880D103A880F183A880990B3
+:105920003A880B98C0BE0E803A882510170E80D892
+:105930003A882118040C40BAC4FFBF10FA90061030
+:1059400034018200044B9D103A88C5101700801165
+:105950001703C0D81701C011170780D83A8811481B
+:10596000151000DA4400C01D26A203103A88090071
+:1059700034F84F01151140DA80A50D80170C80D93D
+:10598000170DC0D93A8809103A880B18C0BE0E808E
+:105990003A882718171140DA1703C0D83A880D90B3
+:1059A0003A880F800500401A3A8809103A880B9807
+:1059B000150C80D800380E80171000DA16488000C9
+:1059C0003A880D903A880F803A88090034FC4F01DC
+:1059D000150D00DAC0BE0E80170C00D93A880D10E4
+:1059E0003A880F183A880B9800380E80170D00DAA5
+:1059F000164E8400170EC0D8600080181E75001067
+:105A0000170380D8150D80DD150E00DD3A88C5100E
+:105A1000170C00DD3A882D10150C40DC060800003C
+:105A2000C0BE0E803A880DA03A880F983A880910B7
+:105A30003A880B1800470E8016230410266280BD9A
+:105A40003A8809A03A880B983A880D003409D001A9
+:105A500000560E803A880D003409D0013A8809902A
+:105A60003A880B803A8829103A88271800560E8009
+:105A70003A880B183A8809103A8821183A88251074
+:105A8000C05A0F803A8809103A882310C0620F80EC
+:105A90003A8809903A880B803A880D103A880F1896
+:105AA000C0BE0E804400C0BD040C408C3A880DA0DE
+:105AB0003A880F983A8809103A880B18C5FF7FBCBE
+:105AC0003A8825103A88211800470E803A880D90B0
+:105AD0003A880F803A88090034FC4F010ED03F10FD
+:105AE000170F80D844008010150480D83A880BA87E
+:105AF0003A8809E080A70880171F80D81704C0D80B
+:105B0000050000B81500C010172180D826973E1058
+:105B10001500C01506953E0034006004C4FF7F8C5C
+:105B20003A70629C440080003A8827881500808083
+:105B300034FCDF002CFC9F981E7AFE103404800099
+:105B4000171FC0D8C4FFBF103A70A698C4C38900FD
+:105B500015008018170180D83AB0AA981E1400A822
+:105B6000172180D826F60310340182003A880710E6
+:105B70000431DD18340182001503C0D804339D10B0
+:105B80001721C0D81500801806783E003404400163
+:105B9000C4FF7F293A704A893A88099034FC4F291A
+:105BA00044003F84171280DC150A00D8069B3E0093
+:105BB000172180D81E4602103401820004309D1047
+:105BC000150380D806693E00170D80DD170E00DD35
+:105BD000170C40DC171380D8169F0010170400D94B
+:105BE000C803C0201E9C0018FA90062034018200D1
+:105BF000044B9D103A88C51017000014170180143B
+:105C0000171E80D80E140010170680D816128000B8
+:105C10001EB802103A8809803A880B903A880D0025
+:105C20003405D00100560E80170180D93A880F88BC
+:105C30003A8809103A880B1800380E803A882500F7
+:105C40003A88210016FD0110171E80D81703C0DD09
+:105C50003A30A20006FF01001701C0DC3A880D802F
+:105C60003A880F903A880B883A88099880A50D8069
+:105C70003A880B183A880910C05A0F803A880910E0
+:105C80003A882D10C0620F803A880D803A880F90B4
+:105C90003A8809103A880B1800560E803A880B880B
+:105CA0003A880D103A880F183A880998C0BE0E80BD
+:105CB000170340DC3A8809101704C0D9040C80B0DF
+:105CC00005008088170680D84400C0391504C0D963
+:105CD000600080113A880B183A8805204400C08D76
+:105CE0001E3900303409D00100560E803A880D006C
+:105CF0003A880F003A8809103A880B183A8827101A
+:105D00003A88291800300E8026783F101706C0D830
+:105D10003A880588150140DD8400408C3A88ED10F2
+:105D2000060A000000560E803A880D003A880F00DF
+:105D30003A8809103A880B183A8827103A882918A7
+:105D40004400408C00300E80269D02103A880D8061
+:105D50003A880F903A8809983A880BA080A50D8060
+:105D60003A880B183A880910C05A0F803A880910EF
+:105D70003A882B10C0620F803A880D803A880F90C5
+:105D80003A8809103A880B1800560E803A880D1090
+:105D90003A880F183A8809983A880BA0C0BE0E803E
+:105DA000040C40AAC5FF7F8A3A880D003409D0014F
+:105DB0003A8809103A880B183A882F881ED97FB480
+:105DC0003A882DA8170140DD3A880D103A880F183F
+:105DD0003A8809103A880B18800B0D803A880D809C
+:105DE0003A880F903A8809103A880B183A88271099
+:105DF0003A88231800380E80160880003A880D80F3
+:105E00003A880F903A8809983A880B8800300E80BB
+:105E10001E363F104C0080B526343FB0C3FF3FBA5A
+:105E2000170300D906030000260EC320C3FF3F1A44
+:105E30003A882F18CC3F80401C20801004E0BF100F
+:105E4000600E8010C4FFFFB81EF73F1044000042F0
+:105E50000500001A06253F001707C0D826E40018E1
+:105E60001702C0D88800C01826EC0118170680D881
+:105E7000C4FFBF14170880D80EC58114170880D836
+:105E8000150880DC3AC885903A88ADB03A8825007C
+:105E9000170680D8164C02101705C0D83A88A9A05A
+:105EA0003A8885183A882718150580D8440040019B
+:105EB0003A8809E040DD08803A8821100E08C004C5
+:105EC0000E0700053A88059816A9C1A41705C0D881
+:105ED0003AC8A7983AC8A9A03AC887181505C0D8E3
+:105EE000170880D826140010170780D826720110D2
+:105EF0000E0E80043A880B803A880D903A8809E0AB
+:105F000040FF08803A880DA83A880B103A8809E0CB
+:105F10003A88211080E008803A882F103A880BA830
+:105F20003A8809E080A708803A882BB8170880D8FB
+:105F30003AC88D141E610130440040013A8809E0DE
+:105F400040DD08803A88251016BC8005170280D8ED
+:105F500088008010266501103A88230044008000E4
+:105F60001EBF00B03A880515CC07801026AA001085
+:105F70000408C0003AC88718500100191EF6022014
+:105F80000407C0003AC885181705C0D83A88A798F2
+:105F90003A88A9A03A8887181505C0D8170580D86F
+:105FA000169780000E0500053A880B903A880DA0E0
+:105FB0003A8809E0C01109803A882510170980D86D
+:105FC0001E2B0110170680D80E0D8100170480D8F3
+:105FD00044008010150480D8170780D81EB2001026
+:105FE0001703C0DD440040041706C0DC06030000B0
+:105FF000C0A908803A882B104400408C3A880B9046
+:106000003A8809A8C01D0580040C80104400C0BD5A
+:10601000C5FFBFB83A880F00840280013A880BA8F8
+:106020003A8809E016F2FF8C3A8811103A88290064
+:106030003A880BA8440080013A8809E0150100DA8B
+:10604000C01109803A880B903A8809103A882B10C1
+:1060500080250980C3FFFFB80E618100170340D976
+:106060000603000026770129C3FFFF203A882F206E
+:10607000CC3F80181C20801004E0BF10600E801000
+:10608000C4FF3FB91EF73F104400C0180500C020F0
+:106090003A880B903A8809E080A7088026933E80D2
+:1060A000260400A0260300A43A880BA03A8809E041
+:1060B00080A708803A880B803A8809E080A708808A
+:1060C000068A3E00150900D8163600A0150500D82E
+:1060D0001702C0D8150480DD150800D8A802801862
+:1060E0003A88A9A526973D1044008000150780D85E
+:1060F000C4FFBF00C4FFBF0444000004150200D861
+:10610000150680D8151E00D8170680D8151100E096
+:106110003A880B00150B80D806AA3D006001801854
+:106120004400C0001507C0D8260D0010171E80D8E7
+:106130001704C0D83A88C510150B80D844008010C9
+:10614000150680D83A880D101692BD0044008001D3
+:1061500006903D00A0008018150700D81E883D104D
+:10616000151100E03A880B003A8809E0409D08804C
+:10617000150380D8151080E0C4FFBF00150B80D830
+:1061800044008000150780D8C4FFBF00151E00D84A
+:10619000150680D8068F3E0044008000150980D87F
+:1061A0000E5C3DA0440080043AC80594150580D8D3
+:1061B0003A88290006583D003A8809B0C0620F802D
+:1061C0003A880DA03A880F983A8809103A880B1837
+:1061D00000300E80263E3D10C4FFBFB5063C3D009A
+:1061E0003401820004279D10150380D806DF3C008F
+:1061F000170880DC1705C0DC3A882100062F3F0015
+:106200003A880BA83A880D103A8809E0C011098035
+:106210003A882B1006633F0004078000065A3F00AF
+:10622000040800013AC88920170180D83A9808115B
+:1062300006F33C004400000406473D003A880DB0D8
+:106240003A880B103A8809E040FF08803A88251008
+:10625000170280D8900080101E2F01103A8823006A
+:106260001704809004018010BA9004103A88859039
+:106270001700001100CC08800408C0003AC8851837
+:1062800006383F003A880B803A880F00840280016C
+:106290003A8809E0C0A908803A882110170B80D8F5
+:1062A0000E1B8200150680D816B3C0041E34018868
+:1062B0003A882780170340DC1706C0D8170180D81A
+:1062C000C4FFFF8D3A88C7B81506C0D81702C0D8DA
+:1062D0004C008010150880D83AB0C410150780D83B
+:1062E000062C00003A880BB83A8809A8150500DA90
+:1062F000802509803A880BB83A8809E0150180D8D2
+:1063000080A70880170180D8170500DA1E02001048
+:106310001707C0D826F201184400C08D160501A049
+:106320001702C0D83AB0E8A01708C0D83AB0281D64
+:10633000260001A016288100170680D80500008AD3
+:10634000262941143A880BA83A880F00840280015C
+:106350003A8809E0C0A908803A882B103A880F00D3
+:10636000840280013A880B803A8809E02620C084A4
+:10637000C0A908803A880B983A880F0084028001EF
+:106380003A8809E03A882110C0A908803A88271085
+:106390003A8823B83A880B903A8809A8C01D05802E
+:1063A0003A880B803A8809A83A882D108025098000
+:1063B0003A880D983A880B903A8809E03A88291073
+:1063C000002B09803A882F1017038010040C00B2AC
+:1063D00026C43F103A880BB83A8809E0150100DA64
+:1063E00080A7088044008000170100DA06CA3F0039
+:1063F000C0A908803A8821103A88271006E43F0097
+:10640000170280D8D00080101E4B0010170680D8CD
+:106410001E0D3E103A880B903A8809E03A880F002A
+:1064200044018001C0A908803A880B103A8809A865
+:106430003A882510802509800E03BE001703C0D8B6
+:10644000440C800005008018170480D84400C01D4B
+:10645000440040143A880B903A8809E080A70880ED
+:1064600044008088150480D81E123F80069F3D009E
+:106470003A880B903A8809A8802509800ED13E10F1
+:106480003A880BA83A880F00840280013A8809E014
+:10649000C0A908803A882B10170480D8C4FF3F1584
+:1064A000170780D81E773F10170B80D80E918100F8
+:1064B000150680D806CA3E00170880D93A880BA86E
+:1064C0003A8809E040FF08803A882B10069A3E007F
+:1064D000340182003A8807100430DD18340182004C
+:1064E0001503C0D8C4309D1006A53D00170180D803
+:1064F0001E993E1034048000C4FFBF103A70848897
+:106500001E953E102CFC5F8C26933E88170580D884
+:10651000440000A54400400444008010150580D8C4
+:10652000068E3E004400800044008004150680D89A
+:10653000151E80D806F43E00170480D84400801051
+:10654000150480D8170780D81E573F103A880B9043
+:106550003A8809A8C01D0580040C0012170380D8D2
+:106560003A8829004400C0150500001206B03E001C
+:106570003A8805A006553E003A880B803A880D9867
+:106580003A8809E0C01109803A88211006473F0087
+:106590003AC8A514063E3E003401820004419D1015
+:1065A000170880111709C011170100D93A880B8804
+:1065B000150E40DA150D80DA80A50D80150C80D8F7
+:1065C0003A882718CC03C0BDC4000004170D80DA38
+:1065D000170E40DA06923C00150700D806D33E009D
+:1065E0001E030010170100DA4C0000421E9B3E40C3
+:1065F0003A8805180602000083FFBFB83A882F18B2
+:10660000CC3F80101C20801004E0BF10180C8010BC
+:10661000C4FFFFB826F83F10069D3E00170AC0D8F9
+:1066200026BC00181705C0D8C40C81103A88A9A050
+:106630003A8885183A882718170880DC150580D80D
+:10664000061A3E001703C0D8440C800005008018CD
+:10665000170480D844008010150480D8068C3E00B2
+:106660003A880980C0620F803A880D903A880F9866
+:106670003A8809103A880B1800560E803A880D00A7
+:106680003407D0013A8809103A880B18800B0D8026
+:10669000150C80D83430BF003A888518150D80D885
+:1066A0003A8809903A880B983A880D003405D00151
+:1066B000C0BE0E80170CC0DD170DC0DC3A88091073
+:1066C0003A880DB83A880F983A880B183A882510FE
+:1066D0003A88211800380E8016EE80003C00E099C0
+:1066E0003A880DB83A8809903A880B8000470E80A6
+:1066F0000E383D103A8825003A88210006523D00A8
+:10670000170480D81EAD0010170180DC3A88278856
+:1067100084000004065B3C00170180D81ECF3E10A9
+:1067200034048000C4FFBF103A70848826753F107F
+:1067300006CA3E000E0E80003A880BA84400800175
+:106740003A8809E0150100DAC01109803A880B90F7
+:106750003A8809103A882B1080250980170100DA41
+:106760000ED58000600E00421EC30040440C00B2F3
+:106770003A8829800500008A3A88219806443E001C
+:10678000170140813A8809E0409D08801704808104
+:10679000040340810403001184008031BA900C305E
+:1067A0003A882310806B0880440080013A880B8867
+:1067B0003A8809E0C01109803A88271006BD3E00DA
+:1067C000170140DD06C93C00170580D81706C0D860
+:1067D0003AC8E71006B53D00580E804026A60010C6
+:1067E0004400004206E23F003A8829803A88219816
+:1067F000060F3E00170C00D9170D40D9151040DACE
+:1068000000560E80170E00D9150DC0D8171040DAAB
+:106810001703C0D8150C80D8580080200500401AF6
+:106820003A8807193A880918261D00103A88078007
+:106830003A880590150E40DC3A8821203A880D00F0
+:106840003409D0013A8809103A880B1800560E8096
+:106850003A880B183A8809103A8825183A88231084
+:10686000C05A0F803A8809103A882710C0620F80FA
+:106870003A880D103A880F183A8809883A880B90A0
+:106880004400C0BD040CC09CC0BE0E80C5FFFFBC50
+:106890001EEA3FBC170E40DC3A8825103A882118C2
+:1068A000170C00D9170D40D93A880D0034F8CF01E4
+:1068B000800B0D803A880D103A880F183A8809909D
+:1068C0003A880B8000380E8016758000170C80D92E
+:1068D000170DC0D93A88090034F84F01C0BE0E80A8
+:1068E0003A880D103A880F183A8809903A880B8038
+:1068F00000470E800EB73C10060100003A882F18A2
+:10690000C7FFBFB8C4FFFFB8200C80101EFB3F10AC
+:1069100006733C001712C0D8170500D9840D8000FB
+:106920003AC8C5103A88A9A03A8885203A88272015
+:10693000170880DC150580D8065C3D00170680D856
+:1069400026473F10170BC0DD0EA2FC053A880B98B6
+:106950003A880D003409D0013A88099000560E801B
+:10696000440000813A8825103A882718C0620F80B9
+:106970003A880D903A880F983A8809103A880B188F
+:1069800000560E803A880D003407D0013A8809106D
+:106990003A880B18800B0D80150C80D8170480D80E
+:1069A000150EC0DDC4FFBF10150F80D83430BF00F6
+:1069B0003A888518150D80D806D03B00170480D87A
+:1069C000170100D93A880B883AC8AF00CC0380B8C9
+:1069D000FA90061034018200044B9D103A88C510CD
+:1069E000170080111701C0113AD12FB800560E8040
+:1069F0003A8825103A882718264A00B8340102023E
+:106A00008400000404411D42150C40DC3A880F004C
+:106A10003A8823803A8821404C0080B93A8809108E
+:106A20007AD02FB83A880B18260500301701C0819C
+:106A3000170080814400408C00560E804400C00145
+:106A4000040200841EF43FB8CC3FC0393A88218844
+:106A5000170C40DC268B3B383A8825103A882718DB
+:106A600006883B00170480D8440C000244008010C4
+:106A7000150480D806F63C00440E80003A88298030
+:106A8000050080883A882198440EC000170340D939
+:106A900006773D003A8825003A88210006673E00C7
+:106AA000170F80D8C3FF3FBA170300D944008010E6
+:106AB000150480D806DF3C001E2D3F104C0080409E
+:106AC0001E283F10062A3F00170F80D83A881188E9
+:106AD000170300D944008010150480D806D53C0067
+:106AE000600E80404400C08D1EE33F10161F3F051E
+:106AF000061F3F00170280D8C800801026933E1062
+:106B0000170B80D8150400DD150680D8063F3E001F
+:106B1000170280D8C80080101EF93F10170B80D8CC
+:106B200006E03D008400000406563B00170F80D8A5
+:106B3000170300D944008010150480D806BD3C001E
+:106B40003401820004319D10150380D806873A0075
+:106B50003A880B00061B3B002001C0181E0F3D1891
+:106B6000040FC0003AC8851806073D000B038028B3
+:106B700004FBFFDE1503C0DC150000DC1504C0DFDC
+:106B8000150280DC150140DC0C02C0103A88212877
+:106B90003A8827201E3F00181701C02814008210D1
+:106BA0000D0380280E55C000170A008226310040D0
+:106BB0001700409C0C000411150000983A8807103B
+:106BC000170740811E5200204400C0013A880D0082
+:106BD0003A8809983AE83E40D8FFFF102658001836
+:106BE0000B03C080170A0082170740810C01C018F0
+:106BF0002606001817010081170CC0803AC805113D
+:106C000026020018170FC0803AC8C5103A880F0036
+:106C10003A880D103A8809983AE83E40D8FFFF10AC
+:106C20001E3D0018170000990B03C080264E00205F
+:106C3000600740211E020028A0050021262C00200C
+:106C400017048080CCFFFD180D03C0801501008063
+:106C500015008080170C40811500409C26050028F7
+:106C600004108080260280283A880998401C0780FA
+:106C7000150C00803A8805001704C0DF1703C0DC3C
+:106C8000170280DC170140DC170000DC0405C0DEC1
+:106C90003A2800F81704802C26F63F901700402C65
+:106CA000CC0080101500802C3AC8A38C1E16001052
+:106CB00017058028150280801603400406ED3F006A
+:106CC0003A88A5900EEB7F04170980801707408152
+:106CD0003A880F883A880D903A8809983AE83E1029
+:106CE0003AC8A38816F6BF000B03C080C4FFBF00DC
+:106CF0001410C0180D03C08006DF3F00170FC02816
+:106D000016A9FF0006DB3F003A88050006E93F00B0
+:106D10001714808006B53F000B03C0801704008164
+:106D200015010080CCFF7D190D0340811500008105
+:106D30000C00C41826C73F181514808006C53F00F4
+:106D40001700C09826A63F18600700191E0E0020E5
+:106D50009805C018260C00180B03C0801410C0182A
+:106D60000D03C08006C43F0017040081CCFF7D19CD
+:106D70000D03408115010080150000810C00C4182E
+:106D800026B43F1806EC3F001500409C3A880500E9
+:106D900006B93F0004FDFFDE150100DC1502C0DF6F
+:106DA0003A88212026020020170E80202607001096
+:106DB0000F0380281E0A00103A8805001702C0DF62
+:106DC000170100DC0403C0DE3A2800F8150040D9A2
+:106DD00000060780170040D90F03802826F63F10D1
+:106DE0003A8809801702C0DF170100DC0403C0DE07
+:106DF00041AB06803A880B202603002074018200F4
+:106E000017AF3211C1CD06807401820017AE321166
+:106E10003400420104375B2981A207803A880500CB
+:106E20003A2800F87400420104B96E2981A2078053
+:106E30003400C20017018020045BDB18150FC0204E
+:106E400004BB4021C400C00015B9C02015BA4021C0
+:106E500015B8002005170010451700108517001001
+:106E6000C5170010051800104518001085180010EF
+:106E7000C51800100401C0001503C0107400020200
+:106E80001702C0207400C201740082017400420124
+:106E9000047128420488E83904A8A83104BF68298D
+:106EA00074004002151900101500001015010010A3
+:106EB000150200101504001015050010150600102D
+:106EC00015078010150800121509C011150A801148
+:106ED000150B40118402404A1503401A1519001879
+:106EE00015000018150100181502001815040018E7
+:106EF000051700184517001885170018C517001842
+:106F0000051800184518001885180018C51800182D
+:106F100017038020B400400215050018150600185C
+:106F20001507C0181508001A1509C019150A801987
+:106F3000150B40198404404A151900101500001063
+:106F40001501001015020010150340121504001061
+:106F50001505001015060010051700104517001044
+:106F600085170010C51700100518001045180010EF
+:106F700085180010C518001015078010150800129C
+:106F80001509C011150A8011150B4011440080002D
+:106F9000150E80203A2800F83A8805003A2800F8B3
+:106FA00004FCFFDE150140DCC4FF7F2C241A408C5A
+:106FB000150280DC3A882528041D4089150000DC74
+:106FC0001503C0DFC0DD07803A88211026070010B6
+:106FD00004030011150000101501801415020011A2
+:106FE000041A80893A880B00408E08803A88058010
+:106FF0001703C0DF170280DC170140DC170000DC3C
+:107000000404C0DE3A2800F804FDFFDE74018200AB
+:10701000150000DC17AE3214150140DC1502C0DF8C
+:10702000170E80803A882320262B001004B8008495
+:107030001701C08017028080C4FFFF180E050018DA
+:1070400006210000C4FFFF18D8FF3F19041A801062
+:10705000261D00200F0300111EFA3F20F4FFFF0041
+:107060004400C0181519001015000010150100107B
+:10707000150200101503C0101504001015050010AE
+:107080001506001005170010451700108517001091
+:10709000C5170010051800104518001085180010BD
+:1070A000C5180010150C0010150D0010151100105A
+:1070B000151200101702C0DF170140DC170000DCBA
+:1070C0000403C0DE3A2800F817008080260500106F
+:1070D0003A88211006D63F003A88098080D706807A
+:1070E00006D23F00040140013A88098880EE0680FC
+:1070F000150080801EF63F100403C0001500C088F4
+:1071000006EC3F007401820017AE32117400420198
+:1071100004B96E2981A20780170E80202601001075
+:107120003A2800F881D706803A2800F83A2800F873
+:107130003A2800F83A2800F87401820017AF32119B
+:107140003400420104595B29419807807401820090
+:1071500017AF32113400420104B85B29419807800F
+:1071600004FBFFDE1503C0DC7401C204150280DCE1
+:10717000150140DC150000DC1504C0DF3A88212829
+:1071800004A9EF9C3A882520C0E00F801702809860
+:107190001701401404FFBF003A70A2883AC8218C3E
+:1071A000C4FB03843AD32080C4FF3F843A932080F9
+:1071B00008008480260600103A880B003A8809905F
+:1071C000C0160A801702C0983A88471C260AC010C9
+:1071D0003A880990C0F20F803A8805001704C0DF92
+:1071E0001703C0DC170280DC170140DC170000DC4D
+:1071F0000405C0DE3A2800F83AC80B043A88099022
+:10720000C0160A80D8FFBF10260D0010740182003E
+:107210001764B3101702C0983AC8238C5400408CEE
+:107220003AC821141501401C740182003A88099063
+:1072300015643314C0F20F804400800006E73F005D
+:107240003A880B003A880990C0160A801702009904
+:107250003AC80711100440191EDD3F28740142018D
+:1072600017B072295400C0181501C0203AC8451142
+:10727000740142011564B32806D53F00264F00284B
+:1072800004FDFFDE150140DC150000DC3A882320F8
+:107290003A8821281502C0DFC0E00F8017FFFF8168
+:1072A00084FFBF0004FEFF803A70843874018201BD
+:1072B0003A88891804A9AF3117014021170200321A
+:1072C00004FF7F023A704A2A2664004115014021DA
+:1072D0004C00C0393A8851211E28003817FEBF8261
+:1072E000170100427401C2013AC8871A1702401AF6
+:1072F00004ABEF393A8885124C000042264CC04955
+:107300001703801A1503804A150240522671004067
+:1073100054004011150140191500802028800011EB
+:107320001E2C0020FAD008101701C0314400802024
+:10733000BAD00B20FA900410440000013A9848217A
+:107340003A888530170040113AB0C82104FEFF1179
+:107350001503C01915024019150100311500C010A0
+:107360001503C0283A8809881702C0DF170140DCDE
+:10737000170000DC0403C0DEC1F20F801701C0411A
+:107380004C00C0391E0E00387401C2013A88451104
+:1073900004ABEF3917024021540040123A8891188B
+:1073A0002652C02917030021150300291502402188
+:1073B0001501401A1500804006D83F003A2800F811
+:1073C0005400401115FF7F81150080202880001196
+:1073D00026D43F207AD20810680140211E340028AC
+:1073E000BAD10810440EC021FA900E38040E402184
+:1073F0003A88CF311700003904FEFF3926420039A0
+:1074000004FFBF01170140213A708A292E02401162
+:10741000170200211EFB3F391703C0211503C019B5
+:10742000150200191502C0381503C02006CD3F0013
+:107430001E4D004017038021170200213A8885283D
+:107440005400401115038021150200311501401927
+:107450003A8887181500801806C23F004C00C039D2
+:107460003A8845111E07003817FEFF813AC8C71930
+:1074700017030019170240193A88C511150300298E
+:1074800015024021740102015400401117B132214C
+:10749000150140191502C03036B23F117401820047
+:1074A00017EF72113A880988800A078006AD3F00FD
+:1074B0006805402126090028681540211E1900286A
+:1074C0003AD30810C41BC021841B4021FA900E3807
+:1074D00006C73F003A88451106AE3F000417C02199
+:1074E000C4164021FA900E3806C13F001505C03081
+:1074F0001504C0301503C0191502C0191501401A32
+:107500001500804006973F00BAD00B284400800049
+:10751000170100323A984A113AB00A2A150140314F
+:1075200006BE3F00685540211E050028FAD308100A
+:10753000041EC021C41D4021FA900E3806AC3F0045
+:10754000685501211E050020BAD40810441FC0212F
+:10755000041F4021FA900E3806A53F0004FEC0012A
+:10756000841F400106A23F0054004011150140193C
+:1075700015008020067B3F001702803026C90010CE
+:107580000B03802804F3FFDE150700DD150300DC84
+:10759000150CC0DF150B00DF150AC0DD150980DDF5
+:1075A000150840DD1506C0DC150580DC150440DC3F
+:1075B000150000D90C02C0103A8821283A882930D9
+:1075C000262400181704C028262200188C00C0109A
+:1075D000170040A4262700181709C08017078080CD
+:1075E000340060053A8827003A88250004007FAD02
+:1075F0003A880D983A880B10170000D92611009090
+:107600003A880F902E0180AC3A880FA83AE83E18CD
+:107610000E9F80001702C0A03A88A7983AC8A5908C
+:107620003AC88518150280A02663001017078080CD
+:107630001709C0803A880D983A880B10170000D9B6
+:107640001EEF3F901700C08C1701808C0402408C05
+:1076500006E73F00170000D93A880B80C007058075
+:107660001EF400100B038080170040A48C00C01093
+:107670001ED93F184C00C0101702808417000087E5
+:107680001E8A00183400E00084FFFF183400200137
+:107690001501C0D8C4FFFF203A882D003A882F007A
+:1076A0001502C0D8264000B80C800011269000209A
+:1076B0003A882B9036B480BC0C200111262500207E
+:1076C0001705808117044081440000B9E40080312F
+:1076D0003AC867E13A88C924FAD724303A88A59194
+:1076E0007AD025903A880D902E0200913A88252074
+:1076F0003A880D200C00811026BC0010170000D91C
+:107700003A880B30C0DD078026C500101704408181
+:107710003A880D983A880910806B08803A880F10D3
+:107720000B038080C4DFFE003A70C4101420801068
+:107730000D0380803AC8C5943A88F93C15058084C9
+:107740001504C081150000873A8825B8150280808D
+:107750003A882BB83A880DA83A880BB03A8809E0E5
+:10776000807B088017028080170080813A8827B8C4
+:107770003AC8A5143A884D351502808415008081D9
+:107780003A882F00170280A03A88EDB43AC8E7146F
+:107790001502C0A4260800980B038080170280847D
+:1077A000170000871EC03FB81700808D1701C08DDD
+:1077B0000402408C06BB3F003A880500170CC0DF6E
+:1077C000170B00DF170AC0DD170980DD170840DD41
+:1077D000170700DD1706C0DC170580DC170440DC46
+:1077E000170300DC040DC0DE3A2800F8166EC0B1A5
+:1077F0001709808017074081170000D93A880DB813
+:107800003AE83E103A8825100E2180003AC8ABAC09
+:10781000266000A8440080001702C0A03A88AFBCD0
+:107820003AC8A79C3AC8A51C150280A426E23F903E
+:107830001702808417000087262100982624001054
+:107840003A8805A83A882D982E01C0143A882D1040
+:10785000170480801705C0812EE43F173A88A53CA5
+:107860000EE2BF953A880BB83A8809E03A880D9045
+:10787000807B088017008080170000D93A880B8031
+:107880003A88851415008080C0CD068026DF3F1021
+:107890000B038080141080100D038080C4FFBF0094
+:1078A00006C63F003A8805003A2800F83A882700C3
+:1078B0003A882B003A8805003A882F001EDF3F984F
+:1078C0001701C08C1700C08D0402408C26FC3F9825
+:1078D0003A880D98840240013A8809B8005D088012
+:1078E000263F0010440080103AC8EB1506D43F0034
+:1078F00017048080361100171705C084360FC0BCEE
+:10790000170180D82E34C015170200D93A880B9879
+:1079100000F00C803A38CF14170740811709808097
+:10792000170000D93A880DB03AE83E100ED8BF00D3
+:107930003A8827103AC8EFBC06923F003A88279051
+:107940002E0180BC3A8827B83A8809E03A880D9819
+:107950003A880BB0807B0880170280801700008176
+:107960003AC8C5143A88C9241502808015000081E0
+:107970001EF03F10170000D93A880B80C0CD06805A
+:1079800026EC3F1006C23F003A8825B83A882BB84B
+:1079900006703F00170000D93A880B80C0CD0680E2
+:1079A000269D3F1006BA3F003A880DB03A880BB8C2
+:1079B0003A8809E0807B08801702C0801700808029
+:1079C0003A8825B03AC8871D3A88AD151502C0809F
+:1079D00015008085068D3F003A8809B806CB3F0028
+:1079E000440080983A882B1006963F00170000D973
+:1079F000C0AB09803A880F101E4E3F10170040DCC4
+:107A0000170440813A880988401C07800B03808056
+:107A10000403C0001500C088CCDFBF10069D3F00E6
+:107A20001700C0D804038000150080180B03808065
+:107A300006983F00C4FFBF0006603F0004FAFFDE67
+:107A4000150280DC1505C0DF150400DD1503C0DC60
+:107A5000150140DC150000DC04B88024261E0090CF
+:107A60003A8827283A882900170140941702009481
+:107A7000C4FF7F8C160D00880B038080C4FF7F8CB1
+:107A8000B00080101E0600108F0380803A880980A5
+:107A9000E0FFBF101E0200103AE83E983AB0A8A0DE
+:107AA000D8FFBF88041A00841EF33F10170080948B
+:107AB0001EED3F903A8805A01705C0DF170400DDD2
+:107AC0001703C0DC170280DC170140DC170000DC64
+:107AD0000406C0DE3A2800F83A88290006F53F007F
+:107AE00004F9FFDE150280DC1506C0DF150540DD58
+:107AF000150400DD1503C0DC150140DC150000DCB9
+:107B000004B88024262100903A8829283A88272022
+:107B10003A882B001701409417020094C4FF7F8C11
+:107B2000160E00880B038080C4FF7F8CB00080108D
+:107B30001E0700108F0380803A880B803A880998CE
+:107B4000E0FFBF101E0200103AE83EA03AB0AAA81B
+:107B5000D8FFBF88041A00841EF23F1017008094DB
+:107B60001EEC3F903A8805A81706C0DF170540DDD8
+:107B7000170400DD1703C0DC170280DC170140DCAE
+:107B8000170000DC0407C0DE3A2800F83A882B0012
+:107B900006F43F0004FDFFDE150100DC1502C0DF26
+:107BA0003A88212026020020170E8020260C001083
+:107BB00017018028C4FFBF1015018028160F001080
+:107BC000170080284400C0101500C0280300801052
+:107BD0001702C0DF170100DC0403C0DE3A2800F8FA
+:107BE000150040D900060780170040D917018028EA
+:107BF000C4FFBF10150180280EF13F103A8809809C
+:107C00001702C0DF170100DC0403C0DE810E0A800A
+:107C100004FDFFDE74018200150140DC17AF721411
+:107C2000150000DC1502C0DF3A88212026020088FA
+:107C3000170E8088260D001017018080C4FFBF102A
+:107C400015018080160F0010170080804400C010BE
+:107C50001500C080030080101702C0DF170140DC50
+:107C6000170000DC0403C0DE3A2800F83A880988CF
+:107C70000006078017018080C4FFBF1015018080B7
+:107C80000EF13F103A880B803A8809881702C0DF4E
+:107C9000170140DC170000DC0403C0DE810E0A80FF
+:107CA000043C80203A2800F87401820004E7B010F8
+:107CB0003A2800F87401820004E7B0103A2800F86E
+:107CC00004EAFFDE151200DC3A8821288F034029E0
+:107CD000151480DC151340DC1515C0DF3A882330FD
+:107CE0003A882538161000283A880DD8C0DD0B8058
+:107CF000160D00101701C0D8040082000C00FC18FB
+:107D00002000C8181500C0900400C1001500C088EC
+:107D10001715C0DF171480DC171340DC171200DCC6
+:107D20000416C0DE3A2800F80B038080150000908E
+:107D30000C2080102604001004108000150080889C
+:107D40003A88050006F23F00040081001500808893
+:107D50003A88050006EE3F000B03C02804FAFFDE58
+:107D6000150200DC1505C0DF150480DC150340DCBE
+:107D70008C00C0183A882128260B0018C410C0288F
+:107D80001500C0281504C0284400C0001505C028EF
+:107D90001705C0DF170480DC170340DC170200DC86
+:107DA0000406C0DE3A2800F80401C0D93A880DD88C
+:107DB0003A88232080C007803A882510170180D890
+:107DC0001E130010170040D93A880988C0DD0780CB
+:107DD000261C001034000201045B1B210B03C08031
+:107DE000150F00891500808015048080170080D849
+:107DF000170140D91420C0180D03C08015058080DC
+:107E00001E1C00283AB0C6900D03C08006E03F005B
+:107E10008F0340813A880988C0E30B8026E93F1030
+:107E20000B038080C410C0801500C08054008010F7
+:107E30000D038080440080001504C08015058080FB
+:107E400006E03F000B0380800C80C0101ED03F185E
+:107E50000CFFBF1094008010C410C0800D03808000
+:107E6000440080001500C0801504C0801505808086
+:107E700006C73F008F0340813A880988C0E30B8022
+:107E80000B03C08026DF3F100CFFFF185400C01802
+:107E900006DC3F0004F6FFDE150140DCC402402C86
+:107EA000150280DC1509C0DF150800DF1507C0DDED
+:107EB000150680DD150540DD150400DD1503C0DC69
+:107EC000150000DCE80580883A8825201E1B00107C
+:107ED000680440291E950028C0E00F800404400477
+:107EE00004068000840080017401C20404A9EF9C90
+:107EF0003A8885981701001404FEFF10269EC08062
+:107F0000170180801703008104FFFF003A70C4103E
+:107F1000170240813A8885801701C0101503002997
+:107F2000150240215400C0181501C0103A8809906C
+:107F3000C0F20F8004028080067F000004FEBF00B4
+:107F40003A70A2881679008836784089C0E00F80A0
+:107F5000287E8088263301107AD204882682001079
+:107F60006801C0101E150118BAD10488440E801192
+:107F7000FA900A30040E00127401C20404A9EF9CA6
+:107F80003A884B991701002C04FE7F292611002CFA
+:107F90001701808004FFFF003A70C4103AC84714EC
+:107FA000080400191EE800200EE9001804FFFF0174
+:107FB00006060000170180803A70C4113AC84714C1
+:107FC000080400191EE000200EE1001817030084C9
+:107FD0001EF83F2C1704009C7401020204AB2F42D0
+:107FE000266C00821701C08004FFBF003A7084181D
+:107FF0003AC8471410040019261501201505009AE7
+:108000001504009A0E0A01182880C0101ED200180C
+:10801000FAD00410170140994400C010BAD00910DA
+:10802000FA900618440080003A9804113A88C798DC
+:10803000170000193AB0441104FE7F19150340815E
+:1080400015020081150180981500001C15030024FD
+:10805000BAD00730440000013A98C82036520011C7
+:108060003A7086201E0A001804FFFF003A88092192
+:108070003A70CC303A708620040180311E0400181A
+:108080003A8809213A7086200401803126FC3F1885
+:1080900004FF7F02FA9014303A8817303A88959A94
+:1080A0003A880F501703003C26CD003C1701808012
+:1080B0003A7044123AC84714080440191E080028B0
+:1080C0000ECC00181703008426C5003C17018080E1
+:1080D0003A7044123AC84714100440191EF83F2859
+:1080E00017030081170240815400808915018081A7
+:1080F00015030029150240213A8863841505409C28
+:108100001504409C54000019150100893A888580A7
+:108110001503008A1502008A1500C0103A880990DC
+:10812000C0F20F8004028080060300000403800078
+:10813000150080903A8805001709C0DF170800DF96
+:108140001707C0DD170680DD170540DD170400DDC9
+:108150001703C0DC170280DC170140DC170000DCCD
+:10816000040AC0DE3A2800F80480400104108001AF
+:10817000C40F000206803F00170300148400803102
+:108180001E5F3F141704009C7401020204AB2F42CF
+:108190001E943F82BAD00730440000011701809836
+:1081A0003A98C8202EAE3F111702009C04FFBF0072
+:1081B000170100853A70ACA0360340B43AC845B404
+:1081C0000804C0101E5600187401820017B0B210C7
+:1081D0007401C20017EF321DD8FFBF103A88AB857B
+:1081E0003A88298D26C80010C40304A50400BC00E9
+:1081F0003A70A8A03A880BA03A880990C0160A8065
+:108200003A882F10D8FFBF10269A0010369840BD2C
+:10821000740182001764B3107401C2003A8885A00B
+:108220001564B3183A88071026DDC0AD74018200CA
+:1082300017B0B210D8FFBF1026E000103AC86BBDCF
+:108240003A88C7A8740182001564F310CC0100BFFE
+:1082500026B600E03AC82FBF0402C0BD0402840065
+:108260003AC805173A8829BD3AC80515CCFF431509
+:108270003A880BA83A880990C0160A80E0FFFF10E0
+:108280001EE400183AC8C5153A88691574018200C1
+:108290001764B3101502C09D540000A53A8885A844
+:1082A0007401C2001564B318150100BD26C6C08450
+:1082B0002804C0B026C600181701008104FE7F0103
+:1082C00004FDFFB03A7046194C0000213AB0C820B6
+:1082D00015010081440140013A88C98015014021FF
+:1082E000150240212804C0181ECF0018170100BD38
+:1082F0003A8821B87401C20017EEF2182E028018D5
+:108300007401C20015EEB2187401C20017EDF21824
+:108310002E5A80187401C20015EDB21806570000DD
+:108320005400C0881501C0803A88638454008010CE
+:108330001502409C150180883A880990C0F20F8090
+:1083400004028080067C3F003A880D4006213F00F1
+:108350001703008106EE3E007AD20610680100196C
+:10836000263E0020680500191E7A002004174019D7
+:10837000FA900A28C41600193A884B991700C028A9
+:1083800004FE7F292662C02804FFFF01170100199F
+:108390003A70C8212E0200111702C0181EFBFF28D8
+:1083A0001703401917018098150340811502C080FA
+:1083B0001502002C1503001C06253F006805C0109F
+:1083C000263800186815C0101E6900183AD30488B2
+:1083D000C41B8011841B0012FA900A3006E63E008E
+:1083E0004400C05ACC0080580402C0391E2D3F10F2
+:1083F000063300003A8885801701C01017030081FA
+:10840000170240815400C0181501C010150300293F
+:10841000150240213A880990C0F20F800402808042
+:1084200006453F00FAD00C880402808806AE3E0064
+:108430003A8885801701C0103A8809905400C01806
+:108440001501C010C0F20F8004028080063A3F0080
+:10845000540000891501008106273F00BAD106109B
+:10846000440E4019040E0019FA900A2806C23F0073
+:108470002646C0841702009C1701008504FFBF0038
+:108480003A70A8A03AC845A4360240A40804C01017
+:108490001EA33F183A880990C0F20F803A88050061
+:1084A00006253F0004178011C4160012FA900A3006
+:1084B00006B13E0017028050C4FFBF311E7080120B
+:1084C000CC00803004FEBF521EFA3F101701C09846
+:1084D0003A3004013A70C410150180983A88092195
+:1084E00036313F1126303F203A7086201E04001896
+:1084F0003A8809213A7086200401C05A26FC3F18A8
+:108500003A880D5806E33E00040400A506393F00F2
+:10851000BAD00920440080001701C0993A9804118C
+:108520003AB0C41115018098069F3F003A8805BDF6
+:108530003AC88500CCFF43153A880BA83A880990C1
+:10854000C0160A80E0FFFF10264E3F183A882B0025
+:10855000064E3F00681500191E2000203AD3061071
+:10856000C41B4019841B0019FA900A2806823F0098
+:108570006855C0101E200018FAD30488041E80110C
+:10858000C41D0012FA900A30067B3E00740182007E
+:108590001764F3103A88C7A01564F31006233F0050
+:1085A000CCFF03A91E213F201702009C3A8829B561
+:1085B000540000A515010085064E3F00740182009D
+:1085C00015B0F21506213F003A8821B806493F0050
+:1085D00044008000150180B806AE3F0068550019C0
+:1085E0001E190020FAD30610041E4019C41D0019DC
+:1085F000FA900A2806603F00685581101E19001085
+:10860000BAD40488441F8011041F0012FA900A3063
+:1086100006593E0004FE3FE73A8829A73AC8E9A573
+:108620003A882B0006193F00040240813A880990DD
+:10863000401C07801702009C740182001764B3106D
+:1086400017010085062B3F006855C1181E09001848
+:10865000BAD40610441F4019041F0019FA900A28C2
+:1086600006453F0004FE4001C41F8001841F000234
+:1086700006413E0004FE4001841F0001063E3F000B
+:108680001701809806953F00CC0080203A880F287B
+:1086900026350010C4FFBF30261900300300C0206B
+:1086A000CC3F80291E06C03006170000C4FFBF1053
+:1086B000E0FFFF101E1200180300C02026128019D0
+:1086C00044000021CC00C0201EF83F182801C01033
+:1086D0001E0F0018260A00100300C020CC3F4029BE
+:1086E000260940193A888520CC3F4039060200000F
+:1086F0000300C02026044019440000211EFC3F1145
+:108700003A8805003A2800F83A8805203A2800F807
+:108710003A920C28CC3F402AF4BFBF02CCFFBF31B5
+:108720003AB046323A94121874202002C4BFBF52A5
+:108730003AB0D248042020421700C0203AF0C64880
+:108740003A888D1A3A30C6003A70C6303A70061A26
+:108750001EE13F1804FFBF102801C01004010021D2
+:108760001EF53F1806DB3F003A88053006D73F006C
+:108770003004C0303A8805201E2D00183AB0062972
+:10878000CC00C0181E35001804FCFF323AD1165830
+:108790003A8807203A880F284400C05A3A91165860
+:1087A0003A88C9221700003A1701803A1702403A66
+:1087B0000404C0391500001A17FF3F3A1501801A4A
+:1087C0001502401A0404C01815FF3F1A1EF5FF20B9
+:1087D0000C0300313A88CB2ACC0300322622002039
+:1087E0003A8809283A8813180401002117FFBF228C
+:1087F0003AC80F410401404A3A88CF2915FFBF4AC1
+:108800002801C0391EF83F3804FF3F41BAD0082084
+:10881000CC008031C4FFFF3144000021BA90082011
+:108820003A8807193A880B291E0400303A2800F8C4
+:108830003A880720C4FFFF3126FC3F304400C0398E
+:108840003A88CF1944004029C3FFBF294400C0180B
+:10885000C5FFBF191EFBFF193A2800F8C4FFFF31FE
+:108860003A88072006F53F003A880D4006F13F00A0
+:108870003A8805202E0A00293A8889292E080011F5
+:108880003A888711263E0030C4FF3F210300402173
+:10889000C4FFFF18050040191EFBFF103A2800F81E
+:1088A0003004C030260B00183A880710C4FFFF318F
+:1088B000263700304400C0393A88CF294400402987
+:1088C000C3FFBF294400C018C5FFBF191EFBFF2905
+:1088D0003A2800F83AB08628CC00C0181E290018A3
+:1088E00004FC7F323AD112483A880F283A880710A0
+:1088F0004400404A3A9112483A8851121700003910
+:108900000404C0180404C03915FC3F1917FD3F3991
+:1089100015FD3F1917FE3F3915FE3F1917FF3F3967
+:1089200015FF3F191EF5FF400C0300313A884B2A12
+:10893000CC030032261700203A8813283A880F18F3
+:108940000401404A0401C03917FFBF4A3AC8C9416F
+:108950003A88091915FFBF3A280100211EF83F2067
+:1089600004FF3F41BAD00820CC00803144000021F0
+:10897000BA9008203A8807193A880B2906CB3F009D
+:108980003A2800F8C4FFFF313A88071006C93F00B3
+:108990003A2800F83A880D4006C43F00CC00C020B9
+:1089A0003A88052026360018C4FFFF3126330030F0
+:1089B0003A8811283A88072006030000C4FFFF39CF
+:1089C000E0FFBF391E2D00304400C018C5FF3F1A1C
+:1089D000CC0080191EF93F30300100391E220020E2
+:1089E000CC3F00293A920C203004003A3AB00831CA
+:1089F0003A940C203AB00C311E0E004004FC3F3A71
+:108A00003AD11040440000423A9110403A88111A7D
+:108A10001500801915018019150280190404C01869
+:108A200015FFBF191EFAFF400C030039CC03C039F3
+:108A3000260D00203A880918040100213AC811398E
+:108A40003A88111A15FFBF21280100421EFA3F4043
+:108A500004FF3F39BAD00820CC00C03944000021BF
+:108A6000BA9008203A880719260400383A88CF19A6
+:108A70004400C018C5FF7F191EFDFF383A2800F8D2
+:108A80003A8807203A880F3006D33F00171380201A
+:108A900004FCFFDE150140DC150000DC1503C0DF1F
+:108AA000150280DC3A8821203A882328260E0010FF
+:108AB000BA9006883A88C71017008018261100104F
+:108AC00017000011150000191504001015030010FF
+:108AD0001703C0DF170280DC170140DC170000DC41
+:108AE0000404C0DE3A2800F8440880010401400173
+:108AF000C0A20B80151380801EED3F103A88050040
+:108B000006F33F00440080043A9864944400400116
+:108B10003A88098044018091BA900C30C0A20B8041
+:108B200026F63F10150140141502801406E63F009A
+:108B3000260700281701C02817138020BA900618AE
+:108B40003A88C5101700C0101500C0281500401144
+:108B50003A2800F804FAFFDE150380DC150240DC39
+:108B6000150100DC3A8823281704002C3A882520B8
+:108B70001505C0DF040500291504C0DC3A880B0088
+:108B8000170080200401002144004029CCFFFF1081
+:108B90003A3887193AD404103A88CF193A388511EF
+:108BA0003AD41038CCFFFF383A880F123A94043880
+:108BB0003AD40E383A88C71015FFFF2016F03F2C24
+:108BC00026080038170280880E0E808044018080BD
+:108BD000BA900410440000843A8885881500C011BA
+:108BE0001504008C3A8805881705C0DF1704C0DC1F
+:108BF000170380DC170240DC170100DC0406C0DE2E
+:108C00003A2800F8170140893A8809901500C0D920
+:108C100044004029409D088017048089040340894E
+:108C20000403001184008031BA900C303A88271078
+:108C3000806B08801700C0D9260900881701C088FA
+:108C400017138090BA9006183A88C5101700C01004
+:108C50001500C088150040143A88239806DB3F00B1
+:108C60003A88239806D93F0004F9FFDE150280DC1C
+:108C7000150000DC3A8825203A88212804020039B2
+:108C8000440240011503C0DC150140DC1506C0DFBD
+:108C90003A882338150540DD150400DD3A88273071
+:108CA00000F00C809002C0881E3100184400C00003
+:108CB0003A880B003A88C7184400402916FDBF18AF
+:108CC0003A880990409D08801707C0D81505C01044
+:108CD0004400C0001504C0109002C0981E21001866
+:108CE000440240853A88E9843A8821A844000084F7
+:108CF000C7FFFF81840280013A880B1004F4FF391A
+:108D00003A880990C0A908801EF83FA404FE3F9C41
+:108D10003A8821AC0E0A409C3AC8E38C3A886384B6
+:108D200044000084C7FFFF81840280013A880B1051
+:108D300004F4FF393A880990C0A908801EF83F8CD6
+:108D40001706C0DF170540DD170400DD1703C0DC80
+:108D5000170280DC170140DC170000DC0407C0DECE
+:108D60003A2800F8840200844402C00406E93F0067
+:108D70003A880B0006D23F00ECFFBF201E13001004
+:108D80003A940820040480002CC0FF201E02001822
+:108D90003A920820040280102C00FC201E020018C9
+:108DA0003A910820040180102C00F0201E020018C7
+:108DB000BA90082084008010160300202C00102197
+:108DC00044008010260300203A2800F83A88050065
+:108DD00006ED3F00040880003A2800F81700C02084
+:108DE000CC018018260800104C0080181E1F0010AF
+:108DF0008C008018262100107AD0061844008000CC
+:108E00001500C0203A2800F8CCFFBF181E1500102E
+:108E10003AD4061804048000CC3F40191E020028F2
+:108E20003AD2061804028010CC0340191E02002812
+:108E30003AD1061804018010CC0040191E02002807
+:108E4000BAD00618840080104C0040191E03002878
+:108E50007AD0061844008010260600181500C0209D
+:108E60003A2800F83A88050006EB3F003A880500EA
+:108E70003A2800F8040880003A2800F8BAD006180A
+:108E8000840080001500C0203A2800F804FEFFDEB0
+:108E9000150000DC3A882128440040011501C0DF9C
+:108EA000409D0880440000011505001415040011C0
+:108EB0001701C0DF170000DC0402C0DE3A2800F80A
+:108EC00004FAFFDE150400DD1503C0DC17040035CD
+:108ED0001704C02C150280DC150140DC1505C0DF2D
+:108EE000150000DC3A8823283A8825301605009DB5
+:108EF0003A8807A03A8825283A8829983A88233062
+:108F00003A882718170280903A88E1A41701409107
+:108F10000E01001444004029409D0880BA90128040
+:108F2000040580123A8807503A8853522E03405263
+:108F3000150000180401C01836FD7F1ABA90169863
+:108F4000BA9010A004054089040580913A88D72A78
+:108F50003A8811323606C02A064100003AD41C7005
+:108F60001E22007004014029040180522E3CC02AB8
+:108F70001700802BCCFFFF7326F83F783A881B50F0
+:108F80003A881D303A883F00170000711700006BC7
+:108F90000401406BCCFFFF213A38CF3B3AD4062086
+:108FA000CCFF3F613A880F393A88CF3F3A38C71B28
+:108FB0003AD418603AD40838CCFFFF393A88071BF6
+:108FC0003A8807193A940818040180733AD43E1875
+:108FD0003AB0CE2115FFFF6936EB3F721500C06F26
+:108FE0001700802B3AD41C7026DE3F701700C0504B
+:108FF0003A881B503A8819303A880F183A881F006F
+:109000000B0000613AD40E38CCFFFF183A388923A0
+:109010000401406B040100633A88C9213A88C923DE
+:109020003A941E201700C0693AD408203AB0C67896
+:1090300015FFFF688BFFFF60CCFFFF3B3A38871BB3
+:109040003A88C71B3A8807193AD41E1836EC3F6293
+:109050001500C068040140290401805236C4FF2A6B
+:109060000E09000417FFFF4804FF7F4A260300187B
+:10907000060500001700C0481E030018C4FF3F8407
+:1090800004FF7F4A1EFB3F80150400141705C0DF54
+:10909000170400DD1703C0DC170280DC170140DC79
+:1090A000170000DC0406C0DE3A2800F804FBFFDEEF
+:1090B0001503C0DC150000DC1504C0DF150280DCE0
+:1090C000150140DCCC0080303A8821303A882720D6
+:1090D0001E2D00103A882528BAD02180261900803C
+:1090E0001712409C1E060088062F00007AD02180AF
+:1090F0002614008017008088261A00103A88231052
+:109100004C00808026F93F103A880D883A880B90F1
+:109110003A88099880E0088026190090170100918C
+:109120001713C0987AD02180BA9008203A8807197E
+:1091300017000019150000911500801C3A882510B1
+:109140001EEC3F803A8805901704C0DF1703C0DC8F
+:10915000170280DC170140DC170000DC0405C0DECC
+:109160003A2800F83A880D883A880B883A88099896
+:1091700080E00880150080881500001006DF3F00A1
+:109180003A88251006D93F00BA9004103401C20075
+:109190003A880F003A88C71017339D19C0A9088074
+:1091A0003A88251006CC3F00440040013A880998CF
+:1091B000409D08803A882310449C800015058088D3
+:1091C00044008000150480881512409C150000881A
+:1091D00006CB3F0004F9FFDE1503C0DC150140DCBF
+:1091E0001704C02C7AD1233017028028150540DDE2
+:1091F0003A88E78C150400DD150280DC150000DCE0
+:109200001506C0DF4400009C3A8825283A882B3098
+:109210003A882920170140290E0300143A88851046
+:109220004400402916FD3F143A8809A0409D08805B
+:10923000040500110E0940044401408CBA902288B4
+:109240003A8807203A884B140401C01815FF3F18CC
+:109250001EFDFF2804FB7F8C3A88492417040092E6
+:109260000405C090CC0780A9BA9010403A88111A22
+:1092700026210030040840023AC893493A880F007A
+:1092800017004019040100210401C0183A988A29E6
+:109290003AB0CA2915FF7F2117FF7F193AD84E2A05
+:1092A00036F73F1A1500C021260100383A8827807A
+:1092B0001504C01426070090170100911713C0A0D1
+:1092C000BA9008203A880719170000191500009174
+:1092D0001500801C1706C0DF170540DD170400DDF0
+:1092E0001703C0DC170280DC170140DC170000DC2C
+:1092F0000407C0DE3A2800F80401C01817FF7F19E0
+:109300000401002115FF7F2136FB3F1A06E83F00CC
+:10931000170480201704C0283AC8C5101E0E00107C
+:10932000BA900C1804050021040540293A888721C9
+:109330003A888B29060100002E08C02004FFFF1880
+:1093400004FF7F291700C0191700802926FABF39AA
+:109350002E038039C4FFBF003A2800F83A2800F8ED
+:10936000440080003A2800F804FAFFDE150280DC91
+:109370001704C0301704802C150400DD1503C0DC71
+:10938000150140DC150000DC1505C0DF3AC8E5908A
+:109390003A8827283A8829300405002C04054034EF
+:1093A0001E130090BA9006183A88C5803A88C7887C
+:1093B000060100002E55808004FFBF1004FFFF1837
+:1093C0001700C0111700401926FA7F392E0A4039BC
+:1093D0003A8807803A8805983A8821883A8827A0F1
+:1093E0003A8823183A8829104400800406020000B5
+:1093F00016F73F903A88250017014099409D088054
+:109400001704409A1704C0A204058012BA901048AD
+:10941000BA901658150380143A8811823A88D78A70
+:109420003A880700060100003A88153817000081C5
+:10943000170080890401C051CCFF7F213A88CB28D6
+:10944000CCFFFF303AC8CB283AD40C303AD40620AF
+:109450003AD40928CCFF7F293AC887193A880719D6
+:109460003A9408180401408C040100843AB04A215F
+:1094700015FF7F393AD4071836EBFF8A2E15008284
+:109480003A8815383A880D8017000031040180525F
+:1094900004018031CCFF7F213A88CB283AD41728A9
+:1094A0003AD40620CCFF3F293A88C71A3A940A18C2
+:1094B0003AD407183AB00A2915FF7F5136F23F32E5
+:1094C000C4FFBF423AC81554BAD01450BA901450D1
+:1094D0003A88953A1E04002804FFBF521700C05076
+:1094E000C4FF7F4A26FC3F18150440121705C0DF51
+:1094F000170400DD1703C0DC170280DC170140DC15
+:10950000170000DC0406C0DE3A2800F83A880B0099
+:10951000409D08804400C0001504C01015050010CF
+:1095200006F23F002CFC5F293430FF003A88C72840
+:109530000E02C0003A8805003A2800F83AC8C70071
+:109540003AD50718080580181E040010340240019F
+:109550003AD8C7283A8805003A2800F804FB3F1992
+:10956000C80780203A8807001E0300103400A000BE
+:109570003AD804113A2800F8440080003A2800F84C
+:1095800004FAFFDE150000DC17040024150280DC5D
+:1095900004058024BA902080150140DC150400DD0C
+:1095A0003A88219417FF7F841503C0DC3A88292864
+:1095B0003A8809881505C0DF00CC0880040800013E
+:1095C0003AC887201500C0A0C802C01004FFFF845D
+:1095D000261F001844FDFF102E0EC09417FEBF80FA
+:1095E000261200183AC8C9203AD80C113A98E288D5
+:1095F0003A98C41004FE7F813AB0868934FCCF18B3
+:109600002E0B409117FD7F813AD808293AB00411FA
+:1096100006070000260400183A98C6883A88050014
+:1096200034FCCF18060200003A88050034FCCF88CD
+:109630001705C0DF170400DD1703C0DC170280DC4C
+:10964000170140DC170000DC0406C0DE3A2800F8F1
+:10965000C40240013AC889283AD8068934FCCF1898
+:109660003605C0943A880B00440580103A988488E7
+:109670003AB0441106EE3F0017FE7F813AD80A291E
+:1096800006F93F0004F8FFDE150340DC3A8823307A
+:10969000150600DD150200DC3A8829283AD5208815
+:1096A000440040011505C0DC150480DC1507C0DF4F
+:1096B0003A882538409D088034048001C4FFBF31BA
+:1096C000CCFF01843A8827103A70A28926010080D5
+:1096D0003404408C150140DC262800A03A8809D8C3
+:1096E000150000DD40D208801701C0D81E170010F9
+:1096F000170000D91506C098150500991E1D001801
+:10970000440040041504409C26250080440DC00000
+:1097100044F33E843A88A1803AC885181708C0D817
+:1097200015000094150080183A8805981707C0DFC7
+:10973000170600DD1705C0DC170480DC170340DCCA
+:10974000170200DC0408C0DE3A2800F80408000113
+:109750003AC889203A980819170040D93AD886188B
+:109760003AB04821150500991501C0D81506C098D2
+:1097700026E33F188400400406E23F00040100D9BC
+:1097800040D208804400C0001504C0981701C0D81A
+:1097900004088010440040041505C0981EDB3F807B
+:1097A000BA90068884F3BE107A9122883A88C798C6
+:1097B000170400191500809000CC08803AC8A388CF
+:1097C000170880D81500401406D73F0004F9FFDEC3
+:1097D000150340DC3A8823283A880BD81506C0DFE9
+:1097E0001505C0DC150480DC3A882720150200DC52
+:1097F000804C0980040140D93A8809883A882510AC
+:109800003A882118804C0980170440891704009970
+:10981000170180D93AC84921170040D97A91082008
+:109820003AC88B293A8849210E0E00013A95082042
+:109830003A8821243A880D103A880F183A880990FE
+:109840003A880B8080A50D801706C0DF1705C0DCA5
+:10985000170480DC170340DC170200DC0407C0DEBD
+:109860003A2800F834FC7F013A3849213A88C72069
+:1098700006F03F0004FEFFDE150000DC1501C0DF2E
+:10988000080680203A882120260D00103A8805001D
+:1098900034FCCF00C4FF3F843A880D003409D00166
+:1098A0003A8809103A880B1800560E801EF93F803E
+:1098B0001701C0DF170000DC0402C0DE3A2800F800
+:1098C000FA90202034018200044B9D103A88211424
+:1098D000170080801701C0801701C0DF170000DC6F
+:1098E0000402C0DE3A2800F8C4FFFF297AD10F38FD
+:1098F00017044031040580304400C039BA900A286A
+:10990000BA900E383A884B113A88CF212E0C40116C
+:109910003A8807200401801017FF3F120401C01885
+:1099200015FF3F1A36FB7F113AC88529C4FABF10CC
+:10993000BAD0041044008010BA9004103A888920EC
+:109940002E03C0210401002115FF3F2036FDFF2119
+:109950003A2800F8170480207AD10D280405002148
+:109960000E0C8011BA9006103A88C7202E14C02021
+:1099700017FFBF1804FFFF181E0400102E0FC02091
+:1099800004FFFF181700401926FC3F284400800000
+:109990003A2800F8BA9006303A88C7200EF3BF3054
+:1099A000CC07402926F13F28170080193AD84431C6
+:1099B0003A984A111EF57F3106EC3F003A2800F82C
+:1099C0003A8805003A2800F804FCFFDE150200DCA6
+:1099D0001503C0DF3A88212026020020170E8020C0
+:1099E000260E001017028030C4FFBF101502803011
+:1099F000161300101700803005004011170080304A
+:109A00004400C0101500C030030080101703C0DFF1
+:109A1000170200DC0404C0DE3A2800F8150180D9E2
+:109A2000150040D900060780170180D9170040D9DA
+:109A300017028030C4FFBF10150280300EED3F10BA
+:109A40001706C030160EC0101700803005004011F8
+:109A50001700C03003008018A00280101E070010FD
+:109A60004400801815008030030080181703C0DF01
+:109A7000170200DC0404C0DE3A2800F8840240012A
+:109A80003A8809801703C0DF170200DC0404C0DE37
+:109A900041810B8004FCFFDE74018200150100DCB3
+:109AA00017AF3214150240DC1503C0DF3A882320BB
+:109AB00026020080170E8080260F001017028028D3
+:109AC000C4FFBF101502802816130010170080284D
+:109AD00005004014170080284400C0101500C0285D
+:109AE000030080101703C0DF170240DC170100DC01
+:109AF0000404C0DE3A2800F83A880980150040D9ED
+:109B000000060780170040D917028028C4FFBF1045
+:109B1000150280280EED3F101706C028160AC01047
+:109B200017008028050040141700C0280300801883
+:109B3000A00280101E0C0010440080181500802820
+:109B40000300801806E73F003A880D283A880B8802
+:109B50003A8809801703C0DF170240DC170100DCD8
+:109B60000404C0DE41810B803A880D288402400144
+:109B700006F73F0004F5FFDE1504C0DC150AC0DF60
+:109B8000150900DF1508C0DD150780DD150640DD6D
+:109B9000150500DD150380DC150240DC150100DC35
+:109BA0003A882730268B00283A882D283A882B209F
+:109BB000C402009CC0E00F80F00580801E5200109F
+:109BC00004FE7F013A7060813A8807801651008058
+:109BD0003650C08417FFBFB004FF7F0104FEBFB43E
+:109BE0003A7062113A8869940E39C088740102078C
+:109BF00004A92FE7170200E2170100A1268E0045F5
+:109C000084FFBF013A708C213A888DA11701803101
+:109C10004C0080311E4F00303A7048213A880B8941
+:109C20000ECBC0284C0080101E4C001017FEFFB158
+:109C300004FFBF003AC8CF91170140393A708A2813
+:109C4000260400A03A886F893A882FB926CB0045B0
+:109C50000E93C0B8264100383A886F89163FC0B8C5
+:109C60001702C0381703803804FFBF896809003124
+:109C7000150380181502C0103A88E93D0402C03867
+:109C80001EF8002030058030170000B11EEB0010D8
+:109C900015020039170100B128078030150300397B
+:109CA0001E040110170200B104048038040280B5BC
+:109CB00015000011170100B13A8823B83A882538F9
+:109CC00015010011170200B13A882D181502001174
+:109CD000170180913AC8058C3004C0104C008031C7
+:109CE000264900183AB08C8915018091170180A08F
+:109CF00054008010150180A03A8809A8C0F20F8096
+:109D00003A8827B006060000040400040404C000DA
+:109D10002EB0FF8404038000150080A83A88270035
+:109D20003A880598170AC0DF170900DF1708C0DD59
+:109D3000170780DD170640DD170500DD1704C0DCBE
+:109D4000170380DC170240DC170100DC040BC0DEC7
+:109D50003A2800F84C008010267800103A880B98BA
+:109D60003A8809A8C0DD07803A8827102616001017
+:109D700017FFBFB084FF3F0104FEFF983A70041143
+:109D80003A8885902667C01004FFBF896809803033
+:109D90001E76001030058030170000B12637001005
+:109DA0003A8805983A8807B0150000111701001984
+:109DB000150100111702C0181502C0103A880BB027
+:109DC0003A8809A8401C07803A8809A8C0F20F8089
+:109DD00006D33F003A880B30170AC0DF170900DFAF
+:109DE0001708C0DD170780DD170640DD170500DD09
+:109DF0001704C0DC170380DC170240DC170100DC0D
+:109E0000040BC0DEC1DD07803AB00C34150180912F
+:109E10003A880B945400801015018028170180A007
+:109E2000040240293A8809A854008010150180A036
+:109E3000401C078006B03F003A7048213A880B89E1
+:109E4000040480811677BF293A8825943AC8052CE6
+:109E5000150280E4540080101501809017FFBFB0F8
+:109E60003A8809A83A8827B04C0080103AB02014EC
+:109E700015FF3FB4C0F20F8006A93F0015000099FE
+:109E80001701C0B0280780301501C0981E6100106E
+:109E90000402C0B004028098170200B106C23F005D
+:109EA000170380A01702C0A004FFBF896809003112
+:109EB000150380181502C0101702C0381703803828
+:109EC0000402003A3A88E93D150380181502C010D3
+:109ED0001E6F0020300580301700C0B01E6A0010D1
+:109EE0001502C0381701C0B0280780301503C038EC
+:109EF0001E7A00101702C0B004048038040280B536
+:109F00001500C0101701C0B03A8823B83A88253828
+:109F10001501C0101702C0B03A882D401502C010BC
+:109F2000066B3F0017FFBF9804FFFF003A70C41094
+:109F30003A88A3883A88699406653F0017FEFFB106
+:109F40003AC8CF91170100393A704A2106413F00C3
+:109F5000170380A01702C0A03A8823283A88699185
+:109F6000150380181502C01006593F003A880BB03F
+:109F70003A880998807B088006903F00040480801E
+:109F80001634BFB8170380381702C03804FFBF89E2
+:109F900068090031150380181502C0100402C03C86
+:109FA0001E5A0020300580301700C0B01E5500102A
+:109FB0001502C0381701C0B0280780301503C0381B
+:109FC0001E6600101702C0B004048038040280B579
+:109FD0001500C0101701C0B01501C0101702C0B0A5
+:109FE0001502C0103A88073C3AC805BC1502C0E00B
+:109FF0005400801015018018170180383A8809A88C
+:10A000004C0080103AB020141501003CC0F20F80C3
+:10A0100006433F00170280B0200980311502809866
+:10A02000170380B0150380981E0600300404C0B0EA
+:10A0300004048098170400B1065B3F003A880518B5
+:10A04000061B3F00170400B10406C0B00406809848
+:10A0500015040099170500B115050099170600B100
+:10A0600006513F003A880BB03A8809181500C0D94C
+:10A07000807B08801700C0D93A882D103A8823B811
+:10A080003A88253806123F003A880540069C3F0072
+:10A090003A880BB03A8809401500C0D9807B088007
+:10A0A0001700C0D93A882D103A8823B83A88253845
+:10A0B00006073F00170280B0200980311504803860
+:10A0C000170380B015058038170400B11E15003045
+:10A0D00004068038040480B506F53E00170280B0FF
+:10A0E0002009803115048038170380B015058038A9
+:10A0F0001704C0B01E12003004068038040480B576
+:10A10000067F3F003A88059806B13F003A880BB0B9
+:10A110003A8809981500C0D9807B08801700C0D9FB
+:10A1200006B03F00040680B51506003917FF3FB1A1
+:10A130000408803815070039170000B106DC3E001E
+:10A14000040680B51506C03817FFFFB00408803834
+:10A150001507C0381700C0B006693F00170280B06D
+:10A160002009803115048038170380B01505803828
+:10A170001704C0B01E03003004068038040480B504
+:10A1800006933F00040680B51506C03817FFFFB0E0
+:10A19000040880381507C0381700C0B0068C3F008F
+:10A1A00004FDFFDE150140DC150000DC1502C0DFF8
+:10A1B0003A8823203A88212826020020170E802082
+:10A1C000261000103A880B803A88098880050C8098
+:10A1D0001E0E00101700C080170180804400001977
+:10A1E000C4FFBF1015018080150000810300801896
+:10A1F0001702C0DF170140DC170000DC0403C0DEDB
+:10A200003A2800F80006078006EE3F00C4FFBF00B2
+:10A2100006F73F00740182003A880B2017AF321115
+:10A22000810E0A8004FEFFDE150000DC740182004E
+:10A230003A8821203A8809281501C0DF15F032102C
+:10A2400080C30F80D8FFFF10260400181701C0DF5D
+:10A25000170000DC0402C0DE3A2800F87401C200D6
+:10A2600017F0F21826F93F181500C0801701C0DF5B
+:10A27000170000DC0402C0DE3A2800F804FEFFDE0E
+:10A28000150000DC3A8821288F0340291501C0DF22
+:10A2900080FD0B80160700101714C0803A888718BD
+:10A2A0001514C0801701C0DF170000DC0402C0DEF7
+:10A2B0003A2800F80B03C080CCFFFB180D03C080C8
+:10A2C0001701C0DF170000DC0402C0DE3A2800F8E6
+:10A2D0003A8805003A2800F80B03802804FBFFDECB
+:10A2E0001503C0DC150280DC150140DC150000DC24
+:10A2F0001504C0DF0C40C0103A8821283A8823207A
+:10A300003A8825303A8827388F0340291E0C0018D8
+:10A31000CCFFBB103A880F983A880D903A8809888C
+:10A320000D0380801704C0DF1703C0DC170280DC38
+:10A33000170140DC170000DC0405C0DE01970B802C
+:10A340008400C0013A880D0040F20B800B0380802E
+:10A350008F03408106EE3F0004FEFFDE150000DCA7
+:10A360003A8821288F0340291501C0DF40F20B8075
+:10A37000D8FFFF10260800180B03C080151480803A
+:10A380001400C4180D03C0801701C0DF170000DCE3
+:10A390000402C0DE3A2800F80B03C080CCFFFB1893
+:10A3A0000D03C0801701C0DF170000DC0402C0DE0F
+:10A3B0003A2800F88F034029419D0B801719802807
+:10A3C00004F6FFDE150400DD1509C0DF150800DF07
+:10A3D0001507C0DD150680DD150540DD1503C0DC61
+:10A3E000150280DC150140DC150000DC0C00881033
+:10A3F0003A882930262C0010170280303A8823280A
+:10A400003A8827201700403504FFFF052624001056
+:10A41000170180AD170000ACBAD024B0261B009005
+:10A420003A883900060200000401008426160097CD
+:10A43000170040813A880D883A880998C0D30B806C
+:10A44000E0FFBF10440000E726F73F10C4FFBF0045
+:10A45000150200A0150100A01709C0DF170800DFD2
+:10A460001707C0DD170680DD170540DD170400DD86
+:10A470001703C0DC170280DC170140DC170000DC8A
+:10A48000040AC0DE3A2800F8170280A03A70ECB542
+:10A490003AC88515150280A0040240AD1EDC3F10AD
+:10A4A0003A88050006EA3F00004C078006E83F00B6
+:10A4B0001702C0302601001841300A801501003013
+:10A4C0003A8805003A2800F804D0FFDE152E00DF98
+:10A4D0001529C0DC152880DC152FC0DF152DC0DD47
+:10A4E000152C80DD152B40DD152A00DD152740DCFD
+:10A4F000152600DC1503C0D93A8827203A8825287C
+:10A500003A88393026020020170E802026B6021025
+:10A510000B0380900C00C8101E0600181719C0907D
+:10A52000C4FF3701140088103A7006190D0380909B
+:10A530001519C0900C02C010269400181704C09082
+:10A54000269200188C068010980280102697001022
+:10A55000041640DC150940DC150B00D8150A00D89C
+:10A560003A881188150400D8150000D8070080E04B
+:10A5700026A20010600980101EE703103A8821E02F
+:10A5800006020000269200183A8821A04700808029
+:10A59000440000855809C0101EFA3F103AC82BA786
+:10A5A000269600A8170BC0D8170A80D815000047B8
+:10A5B0003A88C7A844008010150A80D81501404584
+:10A5C000150BC0D8080280101E840010040200423F
+:10A5D0001700C0D8470080803A88471D1500C0D8B2
+:10A5E00026860010470080A0440000A7450800D838
+:10A5F0003A880B003A880D00C4FF7F023A88210098
+:10A600003A881900440000E704F8FF1068160019A2
+:10A610001E9C0020BA900618740002013A8809199D
+:10A62000175CE9203A6800189CA80008CCA700082D
+:10A63000CCA7000890A80008CCA70008CCA7000869
+:10A64000CCA70008CCA70008CCA70008CCA700081E
+:10A6500068A8000858A80008CCA7000840A800086F
+:10A66000FCA70008CCA70008F0A700089CA70008DA
+:10A670009CA700089CA700089CA700089CA70008AE
+:10A680009CA700089CA700089CA700089CA700089E
+:10A69000CCA70008CCA70008CCA70008CCA70008CE
+:10A6A000CCA70008CCA70008CCA70008CCA70008BE
+:10A6B000CCA70008CCA7000858AE0008CCA700081B
+:10A6C000CCA70008CCA70008CCA70008CCA700089E
+:10A6D000CCA70008CCA70008CCA70008CCA700088E
+:10A6E000CCA70008F0AD0008CCA70008CCA7000854
+:10A6F000CCA70008CCA70008CCA7000824AE00080F
+:10A70000CCA70008CCA70008F4A90008CCA7000833
+:10A71000CCA70008CCA70008CCA70008CCA700084D
+:10A72000CCA70008CCA70008CCA70008CCA700083D
+:10A73000CCA7000890AB00081CAB0008CCA7000811
+:10A74000CCA70008CCA7000824A900081CAB00086F
+:10A75000CCA70008CCA7000810A90008CCA70008C7
+:10A76000DCAA0008B4A900083CA9000830A9000828
+:10A77000CCA700087CAA0008CCA700083CAA0008C7
+:10A78000CCA70008CCA70008C8A800083A880B90FE
+:10A790003A880998C00705801E0704100B038090B3
+:10A7A0008C068010980280101E693F108F038090E5
+:10A7B00016673F101703C0D93A880DE03A880B900E
+:10A7C0003A88099840750B80150080D8061400005F
+:10A7D0003AC82BA726833FA806723F00262B0318F2
+:10A7E000040980D93A880B903A88099840300A8049
+:10A7F0001E0800103A88118806753F00170B80D894
+:10A8000026040010040980D93A880B903A880998E8
+:10A8100040300A800B0380900C1080101EE603105D
+:10A82000170080D8172FC0DF172E00DF172DC0DDCF
+:10A83000172C80DD172B40DD172A00DD1729C0DC1F
+:10A84000172880DC172740DC172600DC0430C0DE28
+:10A850003A2800F83A88210004F4FF10440000E789
+:10A86000A4020084C7FFBFE03A88211C04F4FF1053
+:10A87000B00200191EF93F2004F8FF1068160019F5
+:10A8800026643F20CC3F40291EA9032826DB3F1029
+:10A89000050C80D8450800D84400400544008005D8
+:10A8A000040CC0DD06F1000014200063070080E006
+:10A8B00006543F00070080E0440000E1A00AC010F9
+:10A8C0001EC0031804F4FF10B002C0193A883920E2
+:10A8D0003A881300264C3F38440000E7A402404A5F
+:10A8E000C7FFBFE03A88D34804F4FF10B002001954
+:10A8F0001EF93F2006443F00030080E0CC3F80105B
+:10A900001C2080101401006304E0BF10063D3F00CE
+:10A9100044004001C40A8001070080E006393F007E
+:10A92000170380D8170000140401C015030080E04D
+:10A93000161403801503C0DDCC3F80101C2080104E
+:10A9400004E0BF10062F3F0054000063070080E0C2
+:10A95000062C3F00CC3FC0301C20C01804E0FF187C
+:10A96000030080E01EF43F18CC3F80101C208010B4
+:10A97000440040010408800104E0BF1006213F00AC
+:10A98000CC3F40291E7403283401C2000420DD1886
+:10A990001504C0D80C08C060264B00181703C0D897
+:10A9A0001700401D1701801D0402C0181503C0D8F0
+:10A9B0004C00C060260200183AB086AD1EDF0218B7
+:10A9C0008400800006190000070080E0181BC010FA
+:10A9D0002630031814040063060A3F0014100063B5
+:10A9E000070080E006073F0014080063070080E0CE
+:10A9F00006043F001703C0D8040C8000850880D8E7
+:10AA0000041E800034010201C50880D81700401DD3
+:10AA100004018018150380D804209D20150480D8D7
+:10AA20003A882D009400006384008000450800D817
+:10AA3000E0FFFF483A881B001E4C0118C4DF3F05A9
+:10AA40003AB086AD3A7028651E4102181E0D0348C3
+:10AA50001E7900104C00806526B102B0040C800005
+:10AA6000C51580D8C415C0DD067E0100CC3F402945
+:10AA70001E4603280C0880601E6B0110170380D847
+:10AA80000C04C06017004015040180101E0D011851
+:10AA90000C10C06026130318150380D8CCFF7FADBF
+:10AAA0003A882D003A88050006E03F00CC3F402957
+:10AAB0001E2503283401C200041BDD181504C0D86C
+:10AAC0000C08C0601EB53F18170300D90C04C06005
+:10AAD0001700402504010021150300D91E6E02183D
+:10AAE0000C10C060266C0218CCFF7FAD3A882D0098
+:10AAF00006AF3F00CC3F40291E1503280C0880609C
+:10AB00001E3B0110170380D80C04C06017004015CD
+:10AB1000040180101EF800180C10C06026ED021809
+:10AB2000150380D8CCFF7FAD3A882D00440080000B
+:10AB300006BE3F00170380D8450800D81700C0158F
+:10AB40000401001526DA02B8E0FFBF481E9002108B
+:10AB50003A880D483A880B003A8809B8150300DA9C
+:10AB6000150200DB150140DA005D0880170140DAAC
+:10AB7000170200DB170300DA26EF02103AC8ED15C2
+:10AB80003A882BB00E0100B03A882B00150300DD87
+:10AB900006360000CC3F40291EFA0228170300D9D0
+:10ABA0000C0880600401C0201E6A02100C04806042
+:10ABB0001E8902100C10006326870260170380D8DC
+:10ABC0001503C0D81700C0D8170080100D00C010A2
+:10ABD00006663E00CC3F40291EE802280C08806033
+:10ABE0001E0A0110170380D80C04C06004018010F5
+:10ABF0001ECE00180C10C06026CC00181703C0D859
+:10AC0000150380D80F00401DFAD72DA83A8805B04B
+:10AC100016CC0010D8FFBF48430840DB26090110BE
+:10AC2000C4DFFF003AB084AD3A70D8601E05011051
+:10AC30001E0701483A8829603A8813003A882D0097
+:10AC40003A882F88060701001703C0D8450800D8A6
+:10AC500044004005170080180401C0181503C0D82F
+:10AC6000050C80D844008005040CC0DD3A882960BA
+:10AC70003A8813008C0040A326010068840040AD90
+:10AC8000170A00D90C2100A3170B80D8440080219B
+:10AC90003A880B301E0200603AC8478516AEC100E4
+:10ACA000470880D90402C040260D0030440800D96E
+:10ACB00044008010150000414400000115010041CE
+:10ACC000150B80D8150A40D9080200291E830120DF
+:10ACD0003A8809283A881118440040290402C0180B
+:10ACE00026180068840800D98400801015000041EF
+:10ACF0008400000115010041150B80D8150A40D9C8
+:10AD000008020029268D012026ED0110040980D9B2
+:10AD10003A880B903A880998150240DA150100DB51
+:10AD200040300A801EBB3E10170A00D9170B80D88E
+:10AD3000170240DA170100DB0418C0D84400402194
+:10AD40003A8811881820006326E300603AC8934DC2
+:10AD5000162241023A8885B0150A40D91500C0452F
+:10AD600015018045150B80D8100240291E080028C7
+:10AD700026140010040980D93A880B903A88099863
+:10AD800040300A801EA33E10170B80D83A880788EF
+:10AD90000C0100A5260200A03AC86985160F00051F
+:10ADA0000E0140853A8821A81700C0D83A88071CB0
+:10ADB0001500C0D81E3F0110150A00D83A88118826
+:10ADC00006EA3D00150A00D80C0100A5269D01A049
+:10ADD0003AC869850E9B01053A880788500400A18E
+:10ADE0003401C201170A40D91E6C02200481DD39EA
+:10ADF0000404800506060000840080290402C018AF
+:10AE00003A880B2004FC3FA5480400A12617002027
+:10AE100044000029040480101500C0191501801D8C
+:10AE2000150B80D8150A00D90802802126F23F3080
+:10AE3000040980D93A880B903A88099826A2001014
+:10AE40001501C0D940300A801E723E10170A40D941
+:10AE500004FC3FA5480400A1170B80D83A88078856
+:10AE6000440080291701C0D91EE93F203A88051502
+:10AE7000150A80D91500C0191501001D150B80D8C1
+:10AE8000100280311EC63F30266E0110040980D9A1
+:10AE90003A880B903A88099840300A801E5D3E102F
+:10AEA000170B80D806BE3F00CC3F40291E2C02283D
+:10AEB0000C088060140400631E5B0010170380D828
+:10AEC000040180101703C0D83A882D00150380D8DC
+:10AED0001700401D3A88050006D43E00CC3F4029AB
+:10AEE0001E2102280C088060140400631E4000101C
+:10AEF000170380D8040180101703C0D83A882D00AA
+:10AF0000150380D81700401D4400800006C73E008E
+:10AF1000CC3F40291E1F02280C08806014040063E7
+:10AF20001E3A0010170380D8040180101703C0D800
+:10AF30001700401D150380D8FAD72DA83A8805B010
+:10AF40000E343F103AC86B053AC004A83AC8AD05A4
+:10AF50003AC8ADB0440B8000450880D8E0FFFF48F8
+:10AF6000440B40034400800026B43E186000C0102B
+:10AF70001E340018A00080101E4300103A88078875
+:10AF8000060100003A8807B8FAD008A87A970AB0F4
+:10AF9000FAD02CB0CC0140AD040C80A83AB02A29DC
+:10AFA000C5FFBF183AB088ADC4FFFF1D1EF53F2096
+:10AFB0004C00006126410020CC3F80101C208010F6
+:10AFC00004E0BF10180C8010263C001084FFFF180E
+:10AFD000040C8000C5FFBFB83AC8ED883A882960E4
+:10AFE0003A882F18061F00000006078006483D001B
+:10AFF0001703C0D8440080001700401D1701801DB2
+:10B000000402C0181503C0D806883E001703C0D834
+:10B01000170180181700401D0402C0181503C0D87E
+:10B020003A882D1006FA3E001703C0D83A8805006A
+:10B030001700401D1701801D0402C0181503C0D859
+:10B04000067A3E001E6A01B0A80280A81E680110A0
+:10B05000040C40ADC51540DD3A88296044008005E8
+:10B06000C415C0DD3A882B480E01804D3A882BB0BC
+:10B07000CC3F406B1C20406B04E07F6B26FD3E689C
+:10B08000440040AD06FB3E003A882F88170400D9E3
+:10B09000CC0380A83A9706B03A8885203AD12AA8EE
+:10B0A000030080103AD12CB0C4FFFFBD3AB06A1D36
+:10B0B000050080B83AB084AD1EF43F103AC8ED8D5B
+:10B0C0003A88296006E73F00440080013A880B0077
+:10B0D0003A880788064B3F003AC859850E1B3F0344
+:10B0E000500480613401C2011EAF0130047DDD399E
+:10B0F000040440030606000084008021040200428C
+:10B100003A88091804FC3F634804C060261C0018F4
+:10B110004400C020040480101500C04115014043C4
+:10B12000150B80D8150AC0D80802401926F23F280E
+:10B13000040980D93A880B903A8809982663001050
+:10B140001505C0D9150200DB150140DA40300A8030
+:10B150001EB03D10170200DB170A00D9170B80D86C
+:10B1600004FC3F634804C0603A8811884400802191
+:10B170001705C0D904044003170140DA1EE43F1844
+:10B18000040240433A8805131500C04115010043ED
+:10B19000150B80D8150A80D90802C03026E20018A5
+:10B1A00026570110040980D93A880B903A880998EB
+:10B1B000150140DA40300A801E963D10170140DA32
+:10B1C000170A00D9170B80D83AC8934D0418C0D875
+:10B1D000440040213A8811880EDE7E0250048049E6
+:10B1E0003401C2011E430130047DDD390404000333
+:10B1F0000606000084004021040200423A88091833
+:10B2000004FC7F4A4804C048261A00184400C020A5
+:10B21000040480101500C04115010043150B80D8AF
+:10B22000150AC0D80802401926F23F28040980D91F
+:10B230003A880B903A880998261A00101502C0D94E
+:10B24000150140DA40300A801E723D10170140DAC5
+:10B25000170A00D9170B80D804FC7F4A4804C0485D
+:10B260003A881188440040211702C0D90404000321
+:10B270001EE63F18040200413A8845121500C041FD
+:10B2800015014042150B80D8150A40D90802C02884
+:10B290001E720018440040290402C0203A88112080
+:10B2A00006AC3E00440040013A8809003A88118803
+:10B2B00006D33F00040980D93A880B903A88099850
+:10B2C00040300A8026BC3E1006523D0044008001FA
+:10B2D0003A8809003A881188068A3F0026700010D3
+:10B2E000040980D93A880B903A880998150540DA04
+:10B2F000150200DB150140DB40300A801E453D1081
+:10B30000170A00D9170B80D80418C0D84400402170
+:10B310003A881188170540DA170200DB170140DB75
+:10B32000066F3E00840880D8151680D884008000FF
+:10B33000151780D80418C0D8440040013A88111865
+:10B340003A880928440040210402C040067D3E009E
+:10B350003A8819A006053F00500440193401C20183
+:10B360001E0301280481DD39040480030607000060
+:10B370008400C023040200423A88093004FCFF180C
+:10B38000480440192620002844008021040480102D
+:10B390001500C04115018043150B80D8150A80D9CE
+:10B3A0000802403126F23F28040980D93A880B90E0
+:10B3B0003A880998261F00101507C0D91506C0D86D
+:10B3C000150540DA150200DB150140DB40300A802C
+:10B3D0001E103D101706C0D8170A00D9170B80D8C9
+:10B3E00004FCFF18480440193A8811884400C0231F
+:10B3F0001707C0D904048003170540DA170200DBE1
+:10B40000170140DB1EE03F283A88C5101501C040F7
+:10B410001500C041150B80D8150AC0DB0802C078A2
+:10B420001E2C001804020042440040793A88097832
+:10B43000061B3E003A8809004400C0033A88118880
+:10B4400006CE3F000E0140853A8821A8170080D81B
+:10B450003A880514150080D806573E002681001052
+:10B46000040980D93A880B903A88099840300A80BC
+:10B470001EE83C10170A40D9170B80D80418C0D812
+:10B48000440040293A88118806323E00150A00D847
+:10B490003A881188064E3C003A882D0006443D004B
+:10B4A00026330068840880D8151680D88400800070
+:10B4B000151780D8041800DA4400000106A13F00E7
+:10B4C0000418C0D8440040013A8809003A8811881D
+:10B4D000061C3E0026380010040980D93A880B90DB
+:10B4E0003A880998150540DA150200DB150140DBA2
+:10B4F00040300A801EC73C10170A00D9170B80D8AD
+:10B500003A88118844004021170540DA170200DB11
+:10B51000170140DB06E23D003A8829E006313C0095
+:10B520003A882F8806CF3E00440040310402C068AC
+:10B530003A8809303A88116806043E00040CC000BD
+:10B54000C50880D88508C0D89400006384008000B6
+:10B5500006363D00170040D9170080201503C0D8DB
+:10B56000FAD70928150040111501001106FF3B000C
+:10B570003A8809000418C0D8440040013A8811886C
+:10B5800006F03D003AC821041503C0DD06DB3C008F
+:10B590003A8809B8150200DA150100DBC0DA02802A
+:10B5A0003A882D103A882B10150300DD170100DBB7
+:10B5B000170200DA06AD3D004708C0D81E55001836
+:10B5C0001E583F683A8809000418C0D8440040015A
+:10B5D0003A88118806DD3D00170380D817008010D7
+:10B5E0001503C0D81700C0D81500C01006DF3B00F7
+:10B5F0003A882F88060200003A882B103A882D18C6
+:10B600003A8809A83A880BB0840280013A880F0072
+:10B61000150640DB150500DA150240DA150100DBDE
+:10B62000009C0C80040C8010C4FFFFBD3A8809A860
+:10B630003A880BB0050080B8840280013A880F0078
+:10B6400080420C80170100DB170240DA170500DA90
+:10B65000170640DB1EE83FB0A80240AD1EE63FA83B
+:10B6600006963E004400C000150AC0D83A8805B0CE
+:10B670001516C0DD151780DD150B80DD0418C0D848
+:10B6800006C33D006000C0103A8819A026393E1854
+:10B69000066F3E00430080E014080063440000E7AA
+:10B6A000CC3F80101C20801004E0BF1006D53B006A
+:10B6B000F00180483A882D481E0100108401800561
+:10B6C0003401C2053A882BB0150300DD0425DDBD29
+:10B6D00006663D00150380D83A882D00440080009E
+:10B6E00006D23C00150380D83A882D003A88050020
+:10B6F00006CE3C003A880918047DDD3906DE3E009E
+:10B700000418C0D8440040013A8809003A881188DA
+:10B71000068E3D00440880D8151680D8440080006D
+:10B72000151780D80418C0D84400400106683D00B1
+:10B73000450880D906553C003A882B48150300DDA2
+:10B740003A882D4806493D00450880D906D93C0075
+:10B75000450880D906E93C00450880D9068A3C00A6
+:10B76000450880D906D23D00450880D906DD3D0058
+:10B770003A881F300481DD3906233F00450880D90F
+:10B7800006163D00450880D906043D00450880D9CD
+:10B7900006B83C00450880D906DF3D0044008029FA
+:10B7A0000481DD3906B13D003A881B183A880D281E
+:10B7B000047DDD3906733E00C4FFBF00150080D84C
+:10B7C00006173C00170380D8170040120401C0156B
+:10B7D0000E010048C4FF7F02430080E01503C0DD76
+:10B7E0003A883920CC3F80101C20801004E0BF1024
+:10B7F00006843B00740182003A880F303A880D2895
+:10B800003A880B2017AF321101410A800B038028C0
+:10B810001719002B8B03C02A1707802A1709402A03
+:10B8200004E2FEDE041A00DA0400C100151A01DC8D
+:10B830004CFFBF103A8821283A880BD8151C81DCB0
+:10B84000151B41DC151DC1DF3A8825200D0380D86A
+:10B85000151900DB8D03C0DA150780DA150940DA07
+:10B86000150000DA150400DA1502C0D81505C0D895
+:10B87000150600D800410A803A8823100E0D0010EA
+:10B880000B0380D80C108010260300100B0380805F
+:10B89000141080100D0380803A880588171DC1DFC1
+:10B8A000171C81DC171B41DC171A01DC041EC1DEEA
+:10B8B0003A2800F83A880BD83A880990C0CD06801B
+:10B8C00026EF3F10C4FF7F0406ED3F0004FBFFDEC0
+:10B8D000150280DC150140DC150000DC1504C0DF1A
+:10B8E0001503C0DC3A8823203A8825283A8821307D
+:10B8F00026020020170E8020263E001017068080AA
+:10B900000B03C080150280800C028018261F0010D7
+:10B9100017048080261D00100C000819CC3FC0942D
+:10B92000262300201700C080170500813AC885181B
+:10B930000E290011440080101702008144004019B4
+:10B9400015004081C4FF3F21150200810500801CC5
+:10B950001705C080262980180B0380804C008010BA
+:10B960002602001098028098262400103A88059834
+:10B970001704C0DF1703C0DC170280DC170140DCAE
+:10B98000170000DC0405C0DE3A2800F83A880B8076
+:10B990003A880988C00705801E1C00100B03C08070
+:10B9A00017048080CC3FC0940C0008191EDD3F2096
+:10B9B000171900811400C818C4FF77013A70482194
+:10B9C0000D03C0801700C080151900811705008184
+:10B9D0003AC8851816D73F113A880B803A880988EB
+:10B9E000C0CD06801E0900101700C08044008000F2
+:10B9F00006D13F000006078006C03F003A880B8052
+:10BA00003A880988C0CD068026D83F10C4FFFF04BD
+:10BA100006D63F00740182003A880D283A880B2030
+:10BA200017AF321141810B8004FEFFDE3A880528F2
+:10BA3000150000DC3A880B303A8821203A880D380E
+:10BA40003A880910740182001501C0DF15F0321028
+:10BA5000C0C32280D8FFFF10260400181701C0DFE2
+:10BA6000170000DC0402C0DE3A2800F87401C200AE
+:10BA700017F0F21826F93F181500C0801701C0DF33
+:10BA8000170000DC0402C0DE3A2800F804FEFFDEE6
+:10BA9000150000DC740182003A8821203A880928C8
+:10BAA0001501C0DF15F0321000A62280D8FFFF106C
+:10BAB000260400181701C0DF170000DC0402C0DEF6
+:10BAC0003A2800F87401C20017F0F21826F93F185E
+:10BAD0001500C0801701C0DF170000DC0402C0DEC3
+:10BAE0003A2800F83A388B2904FFFFDE1500C0DF42
+:10BAF000C0DD07803A880710260C001017FFBF1121
+:10BB000004FFBF003A708C3004FFBF3168098030F9
+:10BB10001E14001030058030260800103A880518E1
+:10BB20001500001015010010150200103A880518C4
+:10BB30001700C0DF0401C0DE3A2800F81500001825
+:10BB40001501001828078030260E00101502001875
+:10BB500015030018200980311E0C003004048018E1
+:10BB600006EF3F003A8809183A880B00408E08809B
+:10BB70003A8807103A8805181700C0DF0401C0DEB4
+:10BB80003A2800F80402801806E53F001504001862
+:10BB9000040680181505001806E13F0004FCFFDECE
+:10BBA0001503C0DF150280DC150140DC150000DC48
+:10BBB000260700283A8823203A88212826020020D8
+:10BBC000170E8020262700100F0380801E0800100B
+:10BBD0003A8825003A8805901703C0DF170280DCF9
+:10BBE000170140DC170000DC0404C0DE3A2800F82E
+:10BBF0003A880B803A88098840AB06803A8825103D
+:10BC0000170B808026040010170740813A880988A6
+:10BC10003AE83E10161700100B0380800C208010AD
+:10BC20001E180010170C4081260500280410808083
+:10BC3000260280283A880988401C0780150C00805D
+:10BC400017114081260300283A880988401C078084
+:10BC500015110080000707800D0300804007078052
+:10BC600006DC3F00000607800F03808026D83F10C7
+:10BC700006DF3F000B038080C4FFBF040C20801050
+:10BC800026E83F10170440813A880988401C078045
+:10BC900006E43F00740182003A880B2017AF32118E
+:10BCA00041AE0B8004F9FFDE1504C0DC150380DC17
+:10BCB000150100DC1506C0DF150500DD150240DCAE
+:10BCC0003A8825203A8827283A88213040F00B808E
+:10BCD000580080101E070010C4FFBF98E83F801076
+:10BCE0001E0400103A880B98C500C0DC4400000513
+:10BCF000060A00000417C0813A880D98C40040D994
+:10BD00003A880990C02F0C803A882910D8FFBF10BC
+:10BD100026340010262900A0C30040D93A88230009
+:10BD2000060A00001700808005004011170080807F
+:10BD300044008010150080804400408CC40080D8EE
+:10BD40003A8845142E1D008D030040111702808093
+:10BD5000C4FFBF10150280800EF23F101706C0808E
+:10BD60001610C01017008080050040111700808059
+:10BD70000300C01044008010A002C01826ED3F1838
+:10BD80003A880D80840240013A88099040810B80F6
+:10BD9000E0FFBF10CC3F801026E73F10C4FF3F05F7
+:10BDA00006070000CC3F40293A880D803A88099068
+:10BDB00040810B80E0FFBF1006F63F003A882998CB
+:10BDC0003A8805A01706C0DF170500DD1704C0DCA0
+:10BDD000170380DC170240DC170100DC0407C0DE1B
+:10BDE0003A2800F80B038080141080100D03808027
+:10BDF00006F33F000B0380300C00C8101E0500182E
+:10BE00001719C030140088100D03803014008818F2
+:10BE100015198030C1BE0B8004FCFFDE7401820066
+:10BE2000150100DC17AF3214150240DC1503C0DF2A
+:10BE30003A88232026020080170E808026100010EA
+:10BE40000B0380280C00C8101E0500181719C02805
+:10BE5000140088100D0380281400881815198028F4
+:10BE60003A880D283A8809803A880B881703C0DF82
+:10BE7000170240DC170100DC0404C0DEC1BE0B80E9
+:10BE80003A880980150040D900060780170040D97C
+:10BE900006EB3F0004FEFFDE3A880528150000DCB3
+:10BEA0003A880B303A8821203A88091074018200C0
+:10BEB0001501C0DF15F03210C08D0F80D8FFFF10C4
+:10BEC000260400181701C0DF170000DC0402C0DEE2
+:10BED0003A2800F87401C20017F0F21826F93F184A
+:10BEE0001500C0801701C0DF170000DC0402C0DEAF
+:10BEF0003A2800F804FEFFDE150000DC7401820021
+:10BF00003A8821203A8809281501C0DF15F032103F
+:10BF1000809C0F80D8FFFF10260400181701C0DF97
+:10BF2000170000DC0402C0DE3A2800F87401C200E9
+:10BF300017F0F21826F93F181500C0801701C0DF6E
+:10BF4000170000DC0402C0DE3A2800F82618003092
+:10BF50003401420104FEFFDE04865D293A8809307F
+:10BF6000150000DC1501C0DF3A88213040220C802A
+:10BF70001E0600103401820004859D101701C0DFE9
+:10BF8000170000DC0402C0DE3A2800F83401420148
+:10BF900004855D293A88098040220C8026F53F10EF
+:10BFA0000300808026F33F103A88050006F33F0027
+:10BFB0003401820004859D103A2800F87401820043
+:10BFC00007F5B0103A2800F8740182003A880D286D
+:10BFD0003A880B2017AF321141E90B8004FEFFDED7
+:10BFE0003A880528150000DC3A880B303A88212071
+:10BFF0003A880D383A880910740182001501C0DFB3
+:10C0000015F0321080AA0F80D8FFFF102604001808
+:10C010001701C0DF170000DC0402C0DE3A2800F878
+:10C020007401C20017F0F21826F93F181500C080FD
+:10C030001701C0DF170000DC0402C0DE3A2800F858
+:10C040007401820017E4B0103A68001004FFFFDEAC
+:10C050002608002826090030260B0038030080300F
+:10C0600015008028030080303AC004100401C0DEAF
+:10C070003A2800F83A880BD81EF73F303A88050076
+:10C080000401C0DE3A2800F884FFBF0006F73F0035
+:10C0900004FEFFDE3A880528150000DC3A880B30E4
+:10C0A0003A8821203A880D383A88091074018200B4
+:10C0B0001501C0DF15F03210C0BC2280D8FFFF1080
+:10C0C000260400181701C0DF170000DC0402C0DEE0
+:10C0D0003A2800F87401C20017F0F21826F93F1848
+:10C0E0001500C0801701C0DF170000DC0402C0DEAD
+:10C0F0003A2800F80B0380204C0280105802801070
+:10C10000260200103A8805003A2800F8C1D30680BC
+:10C1100004FCFFDE150140DC150000DC1503C0DF68
+:10C12000150280DC3A8823203A8821282602002044
+:10C13000170E8020263A00100B03C0800C0008194F
+:10C140003A8805181E070020171900811400881866
+:10C15000C4FFF7003A70C8200D0380803A880710AA
+:10C1600015190081150100800C0800111E4D0020DA
+:10C170000C0100111E1C00200C040011265100208F
+:10C180000C0280101E3700101401C0180D03C0806F
+:10C1900017048080263C00100B038084CC00809024
+:10C1A0001E21001017048081170880801705C081A8
+:10C1B00017074081150080813A8809883AE83E10C7
+:10C1C0003A880710150180803A8805000E37C000B4
+:10C1D0001703C0DF170280DC170140DC170000DC0A
+:10C1E0000404C0DE3A2800F8170C408126E83F28F6
+:10C1F00004108080260280283A880988401C078025
+:10C20000170F8080150C00801501808026E03F10FC
+:10C21000170EC0803A8805001500C08006EC3F006C
+:10C220000006078006C43F007401820017AE321179
+:10C2300074004201440080000D038080040F7029C7
+:10C24000409807804C0280900D0380845802801033
+:10C250001ED43F103A880B803A88098840AB06808C
+:10C2600006D03F003A880B803A880988C0CD068006
+:10C270001E0C00100B03C080150200801506008004
+:10C28000CCFDFF1806C03F003A880B803A88098829
+:10C2900000CA078006C03F001410801015010080FE
+:10C2A0000D038080C4FFBF0006C93F000B038080E0
+:10C2B0001EF93F18140880100D038080C4FFBF00D2
+:10C2C00006C33F0044028000150080881410C01887
+:10C2D0000D03C080C4FFBF0006BD3F003AB044213B
+:10C2E000CC0080101E170010170080201700C028F7
+:10C2F0001E14C010F4BF7F02C4BF7F4A3A884712A1
+:10C30000742020023A3084003A70841804202042BD
+:10C310003A70041226020010062400001E230010AA
+:10C32000040100211700C0200401402917008029C2
+:10C330003A88451A3A30CE003A70C4113A70041265
+:10C3400026F6BF1903008020CC3FC0101C20C01867
+:10C3500004E0FF18260D001807008029CC3F80104C
+:10C3600026038019060A0000070080291E0B801191
+:10C37000440000210300C02044004029CC3F801825
+:10C380001C20801004E0BF101EF73F103A88050003
+:10C390000300C0283AC8C5103A2800F8CC3F8018DE
+:10C3A0000300C0283AC8C5103A2800F83A880500AA
+:10C3B0003A2800F804FAFFDE150440DC150300DC1F
+:10C3C000740182001505C0DF3A8821203A8823389D
+:10C3D00017E3B010260800283AE83E10D8FFFF10F7
+:10C3E000260A00181705C0DF170440DC170300DC1D
+:10C3F0000406C0DE3A2800F83A880D00840040D9CF
+:10C400003AE83E10D8FFFF101EF63F188422800045
+:10C410001500008815008080C4FFBF0006F13F00B2
+:10C4200004FAFFDE74018200150440DC150300DC11
+:10C430001505C0DF17AF3214740182003A8823302B
+:10C4400017E3B0103A880F30260B00203A880D28E9
+:10C450003A880B203A8809803AE83E10D8FFFF104E
+:10C46000260B00181705C0DF170440DC170300DC9B
+:10C470000406C0DE3A2800F83A880D00840040D94E
+:10C480003A8809803AE83E10D8FFFF101EF53F18A1
+:10C49000842280001500008815008080C4FFBF0042
+:10C4A00006F03F007401820017E3B0103A680010F4
+:10C4B000260900283040803026030010050080291E
+:10C4C000440080003A2800F8842280001500802073
+:10C4D000C4FFBF003A2800F83A8805003A2800F85F
+:10C4E00004F5FFDE150640DD150100DC150AC0DF8E
+:10C4F000150900DF1508C0DD150780DD150500DD15
+:10C500001504C0DC150380DC150240DC3A882B20C2
+:10C510003A8821281E8200383A8827383A88233002
+:10C520003A8825202E3D8029D4FFBF003A882D2847
+:10C530002EA5801134408000363881303AD606303E
+:10C540000406C004340182003A88851803899D10CE
+:10C550003A88E714040880003AC8C514260500107C
+:10C560003A98A0803AD8E6AC3A98A2303A98A4A873
+:10C570003AB02C9C3AD42A883A8809B0CCFF3F8D37
+:10C580003A880BA8C0050D803A880BA83A8809B0F4
+:10C590003A88271080FF0C803A8821103A94269818
+:10C5A0003AD404903A3807A43AB084982E05C010C3
+:10C5B0003A884514C4FF3F81360140143628C11023
+:10C5C0003A8821203AC8E7103A880BA83A88099897
+:10C5D000C0050D803A882D103A880BA83A88099832
+:10C5E00080FF0C803A942CB03A38A9A0CCFFBF94BD
+:10C5F0003AB0A4B42E0500953A88A58CC4FFFF106C
+:10C6000036014094361401953A8805183A940C8006
+:10C610003A8807003AB08430065500001E04003006
+:10C620003A880B004400000180FF0C803A882310F8
+:10C63000D4FFBF002E5F40143440800036F4808861
+:10C640003AD606880406C004340182003A88851868
+:10C6500003899D103A88E714040880003AC8C5147D
+:10C660001E5E00103AD428883AC86184CCFF7F8DC2
+:10C670004400C0003A8809803A880BA01500C0D851
+:10C68000C0050D803A8809803A880BA03A882710A7
+:10C6900080FF0C803A8821103A9426983AD404906E
+:10C6A0003A3849851700C0D83AB084982E05001151
+:10C6B0003A884514C4FF7F813601401436EB0011DF
+:10C6C0003A8821283AC827113A880BA03A88099855
+:10C6D0001500C0D8C0050D803A882D103A880BA0EF
+:10C6E0003A88099880FF0C803A942CB03A386B1540
+:10C6F000CCFFBF943AB0A4B41700C0D82E05409523
+:10C700003A88A58CC4FF3F113601409436D040953D
+:10C710003A8805203A940C803AB084300614000020
+:10C720003611C029D4FFBF002E1DC0113440800037
+:10C7300036AC80383AD6063804060001340182004F
+:10C740003A8885180389DD10040880053A8807199E
+:10C750003AC8EDB01E5300B036A5003C3A4085A95A
+:10C760003A880700060200003A8807003A88050068
+:10C77000170AC0DF170900DF1708C0DD170780DDC3
+:10C78000170640DD170500DD1704C0DC170380DC49
+:10C79000170240DC170100DC040BC0DE3A2800F869
+:10C7A000304080381E9500103AD20638040200014D
+:10C7B00006E23F00304080881E9B00103AD2068877
+:10C7C0000402C00406A03F00304080301E8E0010DE
+:10C7D0003AD206300402C004065A3F003A98A288B2
+:10C7E0003AD8EC843A98A0803AD428883A8809B09C
+:10C7F0003AD8E6AC3A880BA03A98A4A8C0050D80B8
+:10C800003A8809B03A880BA03AB0269C3A882110A1
+:10C8100080FF0C803A882F10CCFF7F8D3A942080C7
+:10C820003AD404983A38EDAD3AB084802E0680159B
+:10C830003A884514C4FFFFB8368340142E82801511
+:10C8400084FFFFBD3A8845143AC8AD153A880BA05D
+:10C850003A8809B0C0050D803A8821103A8809B09D
+:10C860003A880BA080FF0C803A9420803A3889A83F
+:10C87000CCFFFF9C3AB0E0842E0600813A886184A8
+:10C88000C4FFFF10366C40842E6B008184FFBF1004
+:10C890003A8861843A9406B83AC821813AB0861839
+:10C8A00006743F003AD8F8303A988E3D3AD8EE8078
+:10C8B0003AD8C6A83AB0F8E13AD424E03A98A0852C
+:10C8C0003A8809B83A880B903AB0221C3A98A835B1
+:10C8D000C0050D803A8809B83A880B903A8827102D
+:10C8E00080FF0C803A882110CCFFFFE03A94269814
+:10C8F0003AD404883A38091C3AB084982E060011BC
+:10C900003A880517C4FF7F81364D00172E4C001161
+:10C9100084FF3F843A8805173AC827113A880B905C
+:10C920003A8809981500C0D8C0050D803A88099842
+:10C930003A880B903A882F1080FF0C801700C0D8DF
+:10C940003A942EB8CCFF7F8C3A3889183AB062BC42
+:10C950002E0600893A88238FC4FFFF103634008FDB
+:10C960002E33008984FFBF103A88238F3A942080A9
+:10C97000CCFF7FA13AD40CA03AB08480CCFFFF104A
+:10C980003AD428103A3851193A3887193A384BA115
+:10C990003AD40E403AC823893A8847193A88C738AA
+:10C9A0003A38A9A12E024019740000013A8829A141
+:10C9B0003AD40C183A8829353608008D2602008DA5
+:10C9C0003A880700066A3F003A9406183A988CADF8
+:10C9D000CCFF3F423A88071A2EF9FF30C4FFBF1040
+:10C9E00006F73F003AD406380404000106533F001E
+:10C9F0003A88070044008000065D3F003A88073807
+:10CA00003A880900064D3F003A88073006CD3E00BF
+:10CA10003AD406880404C004060B3F003AD406301A
+:10CA20000404C00406C73E003A88078806063F0093
+:10CA30003A88051806CD3F003A88051806953F004C
+:10CA40003A88212806B43F003A882F18067E3F0016
+:10CA500084FFBF10062F3F0084FFBF1006EB3E008F
+:10CA600084FF3F843A88451406D63E0084FF3F8405
+:10CA70003A88451406133F0004F4FFDE150340DC3A
+:10CA8000150200DC150BC0DF150A00DF1509C0DD3B
+:10CA9000150880DD150740DD150600DD1505C0DC35
+:10CAA000150480DC3A8823283A8821201E7000383B
+:10CAB0003A882B383A8827303A8829202E3980291D
+:10CAC000D4FFBF003A882F2836978011304080303D
+:10CAD0001E2301103AD206300402400534018200C0
+:10CAE0003A88851803899D103A886B1504088000E0
+:10CAF0003AC86515260500903A98A28C3AD86A85FE
+:10CB00003A98A6343A98A8843AB06EAC3AD42C98A5
+:10CB10003A8809B8CCFF3F9C3A880BB0C0050D801D
+:10CB20003A880BB03A8809B83A882B1080FF0C80FD
+:10CB30003A942AA83AD406A03A3885803AB0C6A8D2
+:10CB40002E0380183A88C71C3601C01C361881187D
+:10CB50003AC8AB183A880BB03A8809A8C0050D80CE
+:10CB60003A8823103A880BB03A8809A880FF0C80D5
+:10CB70003A9422883A388580CCFFFFA03AB0C68824
+:10CB80002E0480183A88C71C3602C01C2E0180185B
+:10CB90003A88C71C3AC885183AD884143A880700DE
+:10CBA000063600001E0400303A880B0044000001E5
+:10CBB00080FF0C803A882710D4FFBF002E55C01488
+:10CBC0003440800036EE80983AD606980406400538
+:10CBD000340182003A88851803899D103A886B15C4
+:10CBE000040880003AC865151EAB00903AD42C9812
+:10CBF0003AC8E38CCCFF7F9D3A880BB03A8809880D
+:10CC0000C0050D803A880BB03A8809883A8821100F
+:10CC100080FF0C803A9420803AD406A03A3845151B
+:10CC20003AB0C6802E0480183A88C71C3602C01C51
+:10CC30002E0180183A88C71C3AC8A1183A880BB050
+:10CC40003A880980C0050D803A8823103A880BB0D5
+:10CC50003A88098080FF0C803A9422883A3845153A
+:10CC6000CCFF3FA53AB0068D2ECABF1806C53F00BF
+:10CC70003A8805202E0DC0293A880728170BC0DFF7
+:10CC8000170A00DF1709C0DD170880DD170740DD30
+:10CC9000170600DD1705C0DC170480DC170340DC35
+:10CCA000170200DC040CC0DE3A2800F8D4FF3F0174
+:10CCB0003A8807282E12C0213440000136AD0039D1
+:10CCC0003AD6103804064001340102013A8809417D
+:10CCD00003891D250408C0043A8869A13AC8279D24
+:10CCE0001E1600983601403C36E4BF813AC8858163
+:10CCF0003AC8CF893A8087803AC8C73806DF3F00F4
+:10CD0000304000391E9800203AD210380402400109
+:10CD100006ED3F00304080981E9C00103AD20698E5
+:10CD20000402400506AA3F00344080003699803056
+:10CD30003AD606300406400506683F003AD8043566
+:10CD40003A98CE3C3AD8388D3A98E28C3AB0EE1107
+:10CD50003AD42CB83AD804853A8809E03A880BB01E
+:10CD60003A98E4343AB06214C0050D803A8809E07C
+:10CD70003A880BB03A882B1080FF0C803A880D104F
+:10CD8000CCFFFFB83A942AA83AD404883A388919D3
+:10CD90003A98E0843AB084A82E0600113A88C51566
+:10CDA000C4FF7F313680C0152E7F001184FFBF3154
+:10CDB0003A88C5153AC82B113A880BB03A8809A8A9
+:10CDC000150180D91500C0D8C0050D803A880BB078
+:10CDD0003A8809A83A88391080FF0C801700C0D81B
+:10CDE0003A9438E0CCFF7F8C3A3887183AB062E446
+:10CDF000170180D92E06C0883A88E38DC4FF3F1101
+:10CE00003667C08D2E66C08884FFBF103A88E38DD8
+:10CE10003A940A303AD41090CCFFBF913AB08828A7
+:10CE2000CCFFFF213AD408203A880B303A388D39AC
+:10CE30003A384B213A380F3A3AD404303AC8C788C6
+:10CE40003A884F393A88C5113A3809222E024011E2
+:10CE5000740040013A8849213AD40A103A940410E7
+:10CE6000CCFFBF313A8809293A8885113636001936
+:10CE7000263400193AC885803A80A1803AC807193B
+:10CE80003AC8071C3A98201D3AD8C4143AD8C61C90
+:10CE90003AB0848006793F003A98A69C3AD8688DCB
+:10CEA0003AD86A853AD42C983A8809A03A98A28C44
+:10CEB0003A880BB0C0050D803A8809A03A880BB0BB
+:10CEC0003AB06EAC3A88231080FF0C80CCFF7F9D77
+:10CED0003A9422883AD406B83A3885A83A98A88471
+:10CEE0003AB0C6882E0480183A88C71C3602C01C87
+:10CEF0002E0180183A88C71C3AC8A3183A880988B6
+:10CF00003A880BB0C0050D803A8821103A8809880C
+:10CF10003A880BB080FF0C803A9422803A3885A87A
+:10CF2000CCFFFFBD3AB0E28D2E0480883A88E38CB6
+:10CF30003602C08C2E0180883A88E38C3AC8A388D8
+:10CF4000062D3F002ECBBF803AC8A5143A80851429
+:10CF50003A88C5153AC889203A88059006C53F0029
+:10CF60003A88073006DD3E003A8811383A880B00CF
+:10CF700006553F003AD410380404400106523F00E1
+:10CF80003AD406980404400506113F003A880798F1
+:10CF9000060F3F003AD406300404400506CF3E0099
+:10CFA0003A880520069A3F003A880D2806813F00FE
+:10CFB0003A88C71C06E63E00161A00203A880F0081
+:10CFC0000E0200283AC84B015C00C0393A880D2097
+:10CFD0004400C0002E090029040880004400C0005D
+:10CFE00006010000261200103A884B29C4FFBF102A
+:10CFF0003A88C71836FB3F29260D00183A880500E5
+:10D00000360240313AC84D313AB0C4107AD00618D1
+:10D010007AD00A281EFA3F18260100383AC885003F
+:10D020003A2800F83AC809014400C00106E43F006C
+:10D030003A88050006F83F00161A00203A880F00CB
+:10D040003A8805200E0100283AC84B014400C00070
+:10D050002E090029040880014400C00006010000D8
+:10D06000260D00303A884B29C4FFBF313A88C718D3
+:10D0700036FB3F29260800187AD0061836014011E1
+:10D080003AC845117AD00A281EFB3F1826010038FD
+:10D090003AC885003A2800F83A88052026FD3F382E
+:10D0A00006FB3F003AC809014400C00106E43F0006
+:10D0B0003A880D202E150029161400280408800037
+:10D0C0004400C00006020000260E001016050028CD
+:10D0D0003A884B29C4FFBF103A88C71836FA3F294F
+:10D0E000260800183A880500360240313AC84D310A
+:10D0F0003AB0C4107AD006187AD00A281EFA3F181F
+:10D100003A2800F83A8805003A2800F84400C000A0
+:10D1100006F43F003A8805202E1300291612002835
+:10D12000040880014400C00006020000260C003004
+:10D13000160500283A884B29C4FFBF313A88C71822
+:10D1400036FA3F29260600187AD006183601401113
+:10D150003AC845117AD00A281EFB3F183A2800F831
+:10D160003A8805203A2800F84400C00006F63F003F
+:10D170003404000204FBFFDEC4FF3F423A70122A6F
+:10D180003A70063A3AD50438150000DC3AD5202822
+:10D190007AD716207AD71430FAD70A28FA9012488C
+:10D1A000FA900618FAD70E38150140DCCCFF01843E
+:10D1B000CCFF81101504C0DF1503C0DC150280DC34
+:10D1C0003AB0525A3AB0C6503A882328FA901820FA
+:10D1D000FA9016303AC89580266AC0290E59800206
+:10D1E000267C0010D8FF8180260701103420C0184B
+:10D1F000480E80501EED0010080880501E5401108B
+:10D20000040800013AC889223A9826193AD8845A63
+:10D210003A9808593AD8861A3AB0A6983AC01620D1
+:10D220003AB0E69A3AC8D3483AC8E7643A80C96443
+:10D230003AC809492C20802026870010342040025B
+:10D24000C4FF7F4A3A70642226CF00903A88099042
+:10D2500000790F8004FEFF10040800013AC8C920BD
+:10D260003AD80A993A98C8903A98E6983AB0082974
+:10D2700016BE001C3AC8211C4400408108088028C2
+:10D280001E1B0110040880003AC845113AD846997F
+:10D290003A98A6983A9884203AD848213AC02698D5
+:10D2A0003AB0C4103AB0E6143A882100CC01809814
+:10D2B00026070010CC038098200180101E04001067
+:10D2C000040140993A80E72C3A88C9243A882728F3
+:10D2D0002C2080202662001044000084E0FF818022
+:10D2E000CCFF01841E73001034E07F01C4FF7F294E
+:10D2F0003A704A217A9704287A920A28FAD0269816
+:10D300003AD308283AB0C4143A9520803404C000B7
+:10D31000CC3F408CFA972288C4FFFF183A70C62091
+:10D320003AB0061C3AB0461C1704C0DF1703C0DC35
+:10D33000170280DC170140DC170000DC0405C0DEAA
+:10D340003A2800F81E2B0050440080808CFF81108A
+:10D350001EA100103AB00A4B3AB0C41A1E5C0180FC
+:10D36000262801281E6701107A9726483400C80035
+:10D37000C4FFFF183A70C4203AB08498FAD012481B
+:10D38000063D00000E4F800226240010D8FF818049
+:10D39000269D00103420C018480E80501E3B0010FF
+:10D3A000080880502603011004F8FF54200800519B
+:10D3B0003AD8C41C1E040020041000013AC895226B
+:10D3C0003A98861A3AB0D6583AC026583AB0A69833
+:10D3D000063000003AB0C41A26770010C4FFBF50D0
+:10D3E00026190110D8FF8152262001503A881510C5
+:10D3F000067F3F003AC809141EA600803AB00A4BC7
+:10D4000026F70028C4FF7F21267F0128D8FF0121AD
+:10D4100026A301203A88092806A100003AB0C41AC0
+:10D4200026650010C4FFBF5026040010D8FF8152AB
+:10D43000264301503A88151006D73F003A88E76224
+:10D440003A88D3483A80099B3A8809492C208020A1
+:10D450001EB4001044000004CC0180981E953F10BB
+:10D46000FAD026987A970420FAD012203AB08498FD
+:10D47000E0FFC1801E35001834040001C4FF3F21C5
+:10D480003A700849CCFF0184069F3F003AB0C81AA1
+:10D490003AC026203A88279B3A80099B3A8849223D
+:10D4A0002C20802026EC3F1044000084E0FF818087
+:10D4B000269D0010C4FF01043A8809003A8805003F
+:10D4C00006913F001E570050440080808CFF4111A0
+:10D4D0001EED00283AB0044B26A800802602011059
+:10D4E0003AB0D61A7A970A48FAD01248265F0158FD
+:10D4F00034000802C4FF3F423A7004222C02004963
+:10D500003AB04A1126080020FAD008182C028020D0
+:10D510001E0500107A9706183A7004323A882338AC
+:10D520003AB0CA103A8813207AD70428FA900848EB
+:10D530003400C800C4FFFF183AB008117A970420DD
+:10D54000FAD012203A70CA283AB044113AB086484C
+:10D55000266B01183404C00034020049C4FFFF18D0
+:10D560003A70C820C4FF010406673F0034E07F0121
+:10D57000C4FF7F29CC0180983AC8E1803A704821E5
+:10D580001E4C3F1006B63F003A88099800790F807C
+:10D590000406C01008080019262F3F2004FE3F1182
+:10D5A0003A9808993A88270006313F003AB0C81ADD
+:10D5B0003AC02620061C3F007A9726483400C8004F
+:10D5C000C4FFFF183A70C4203AB0C414FAD012480D
+:10D5D0003A88215006A63F003AC8E7623AC8E548B3
+:10D5E0003A80C9643AC825912C2080901EB2001060
+:10D5F0003AB0849C1E143F103A8813003A882100E8
+:10D600003A882300069C3F007A9726483400C800D9
+:10D61000C4FFFF183A70C4203AB0C414FAD01248BC
+:10D6200006CA3F003AC809141E5E00803AB00A4B91
+:10D6300026130128C4FF7F21262C0128D8FF0121B1
+:10D6400026A900203A880928480E40211EB9002842
+:10D65000080840211E1A0128040840013AC80B2975
+:10D660003A9866493AD80C613A984A613AD81249D0
+:10D670003AB0A6993AC00A283AB066993A88471A49
+:10D680003A88E79A3A80C99A3A88C9203A8821109C
+:10D6900006833F00D8FF4111266300283420404A0A
+:10D6A000480E40211E6E0028080840211EAB0028AD
+:10D6B000040840013AC80B293A9866493AD80C61E7
+:10D6C0003A984A613AD812493AB0A6993AC00A281B
+:10D6D0003AB066993AC8471A3AC8E75C3A80C95CDA
+:10D6E0003AC809193A8823383A88211006D13E00F1
+:10D6F00044F83F84200880283AD820241E040010D3
+:10D70000041080003AC84B113A9848213AB0269943
+:10D710003AC026983AB0269C3A8809003A882100F7
+:10D72000064D3F008400000434E0BF00C4FFBF107A
+:10D730003A708A207AD00498FA9706284C00C09C48
+:10D740003AB0E6147AD008283AB0E61C06D73E0074
+:10D7500004F8FF54200880503AD8E61C1E0400103C
+:10D76000041080003AC895123A98861A3AB0D658F2
+:10D770003AC008583AB0E62406AB3E0026A900108D
+:10D780003AB0C41A1EAE00107A97064834008800DA
+:10D79000C4FFBF103A7084203AB0C410FAD01248C7
+:10D7A00006353F00D8FF4111264F00283420404A5B
+:10D7B00006A53F00040800013AC889223A982619B4
+:10D7C0003AD8845A3A9808593AD8861A3AB0A6985C
+:10D7D0003AC016203AB0E69A3A88D348062D3F0060
+:10D7E000340048017A972618C4FF7F293A704431E3
+:10D7F0003AB0C414FAD012183A8823383A88212053
+:10D80000061B3F00267D0010340088007A97081818
+:10D81000C4FFBF103A7084303AB00411FAD0121825
+:10D820003A88233806143F007A970A183400080112
+:10D83000C4FF3F213A7004313AB08428FAD012185C
+:10D840003A88233806413F003AC8E7623AC8D348CD
+:10D850003A80C9643AC809494400000406753E008C
+:10D860003AB0124B3AC02648069B3F007A972648AA
+:10D870003400C800C4FFFF183A70C4203AB084983E
+:10D88000FAD0124806313F00E0FF01111E093F2087
+:10D890003A88D7623A80095B3A88D3483A880B497C
+:10D8A000FA9726287AD016587AD008283A88211074
+:10D8B0003AB0E69A06E83E003AC8275B3AC8531ADF
+:10D8C0003A80C95C3AC825493A882338065E3E004A
+:10D8D0001E2D00281ED43F10C4FFBF003A8823002D
+:10D8E0003A881340061B3F00340088007A970818D6
+:10D8F000C4FFBF103A7084303AB00411FAD0121845
+:10D9000006123F003AC8E7623AC8CB483A80C96479
+:10D910003AC809292C208020263600103AC8275BF7
+:10D920003AC8531A3A80C95C3AC809493A88233838
+:10D93000065E3E003AB0124B3AC0264806503F0001
+:10D940007A97064834008800C4FFBF103A708420DC
+:10D950003AB0C410FAD0124806FC3E0004F87F2109
+:10D96000200880213AD84A491E0400300410800162
+:10D970003AC809313A9812493AB058623AC026601A
+:10D980003AB0669906543F007A970A48FAD012488E
+:10D990002636001034000802C4FF3F423A700422C9
+:10D9A0002C0200493AB04A1126080020FAD0081883
+:10D9B0002C0280201E0500107A9706183A70043257
+:10D9C0003A8823383AB0CA103A881320FA900848A7
+:10D9D0007AD704283400C800C4FFFF183AB00811F1
+:10D9E0007A970C203A70C428FAD012203AB08430CA
+:10D9F00006D63E003AB004991E973E103A881300AE
+:10DA00003A882300069C3E003AC8275B3AC8531A5E
+:10DA10003A80C95C3AC809493A882338440000046E
+:10DA200006043E007A970A1834000801C4FF3F211B
+:10DA30003A7004313AB08428FAD01218068E3E00AB
+:10DA40003A88E7623A88D3483A80099B3A8809497C
+:10DA50002C20802026803E1034E0BF00C4FFBF1081
+:10DA60003A70882044000004067B3E0034008800A1
+:10DA7000C4FFBF103A7084203AB0441106B33E0090
+:10DA80007A970E1834004801C4FF7F293A70443158
+:10DA90003AB08438FAD012183A88212006743E0031
+:10DAA000340088007A970818C4FFBF103A70843099
+:10DAB0003AB00411FAD012183A88233806A33E006F
+:10DAC00004F87F21200880213AD84A491E040030FA
+:10DAD000041080013AC809313A9812493AB05862A4
+:10DAE0003AC026603AB0669906E53E003A88E76299
+:10DAF0003A88D3483A80C99A3A88094906533E0081
+:10DB00003A880500C4FF01043A88090006FE3D007A
+:10DB100004F1FFDE3AD50428150900DDFAD72828DC
+:10DB2000150500DC34040004150CC0DD150780DC8D
+:10DB3000C4FF3F84150EC0DF150D00DF150B80DD1F
+:10DB4000150A40DD1508C0DC150640DCCCFF81104D
+:10DB50003A8825203A70202C3A882FA02689001078
+:10DB6000E0FFC1101E9F0018FA900A807AD70820A3
+:10DB7000FA90249044007F153AB048213420802543
+:10DB80003A8823003A8821003AD506383404000147
+:10DB9000C4FF3F21CCFFC1183A702639FAD70E389E
+:10DBA00026630018E0FF81181E200010FA900898E4
+:10DBB0007AD70A30FA9010304400FF183AB008299A
+:10DBC0003AC8EBA83420C0243A880700280480898A
+:10DBD0003AF0F8A11EAD0030BA902288740082009D
+:10DBE0003A88858817CDB6103A680010D4DD000851
+:10DBF00068DC00080CDC000890DB00080CDC000886
+:10DC000090DD00080CDC000890DB000868DC0008F0
+:10DC100068DC000890DD000890DB0008A0DB00084D
+:10DC2000A0DB0008A0DB0008A8DD00083AB090994E
+:10DC300044007EAD1E8000409400408C3A8827004E
+:10DC40008400C00006E13F003A882F383A882D98BA
+:10DC50003A8825403A882118A00080801E7C011057
+:10DC6000E00080801ECA0110600080801E14001039
+:10DC7000C4FF00AC3A8839B80E580104CC0180903A
+:10DC80001E920110FAD00A902C4080B02604001099
+:10DC900034C0BF00C4FFBF103A70ACB0040001AC88
+:10DCA000C8FF81801E1E00107A9724B07A9208B0B7
+:10DCB000CCFF81803AB064913AD30820060400007A
+:10DCC0003A8839B83A8805003A8809003A88250028
+:10DCD0003A9504103404C000FA9738E0C4FFFF18E6
+:10DCE0003A70C6203AB086183AB0061F3A880590B6
+:10DCF000170EC0DF170D00DF170CC0DD170B80DD1E
+:10DD0000170A40DD170900DD1708C0DC170780DCA3
+:10DD1000170640DC170500DC040FC0DE3A2800F8C7
+:10DD2000C4FF81003A8809003A88250006E83F00D0
+:10DD30003AB09099263C0040261801983A880998F4
+:10DD4000150180D91500C0D900790F801700C0D9FE
+:10DD5000170180D944FD7F114407C00004FE3F1223
+:10DD60003AC847193A98089A3AD8C6303A981032C1
+:10DD70003AB026193A884515C4FC40153A88070080
+:10DD800006923F003AB02C243A882320262100B086
+:10DD90001501C0D9150080D926F500803A88098080
+:10DDA00000790F80170080D91701C0D93A882B104D
+:10DDB00044FD3F114407800504FEBFAC3AC82DB1B5
+:10DDC0003A988A843AD8888D3A98A48C3AB06C21D3
+:10DDD0004403BF003AC86B153A8823003A882100F3
+:10DDE00006693F003AB02C241E0500B03A88250091
+:10DDF00004024004C4FF41058400000406623F00A1
+:10DE00003A882D8004034004C4FF4105C400000487
+:10DE1000065D3F003A882500040140043A882B0043
+:10DE20004400000406583F005400408C3A88270004
+:10DE30004400C00006653F00D400408C3A88113091
+:10DE4000C400C00006613F00340400013A88390074
+:10DE5000C4FF3F21C4FFBF04C4FF8100069C3F00F4
+:10DE60002C0280B026A100102C0280981E9F00106A
+:10DE70003404800034020099C4FFBF103A70882037
+:10DE80003A8839383A88254006F33F0036B2809DFB
+:10DE900026B0809DC4FF7FAD3A8807B03A88210044
+:10DEA0003AD60C403A9226983A9204403A88091899
+:10DEB0003AB0E2343AD428881501C0D8150080D889
+:10DEC0003A880BA080FF0C801701C0D83A880BA0BD
+:10DED0003A882D103A880918C0050D803A9406102A
+:10DEE000CCFFFF8D3AD404903A38A7BD3AB0C410A5
+:10DEF0002E04C0143A884514C4FFFFB02EE140142C
+:10DF00003A882D183AC8E7143A880BA03A8809983D
+:10DF100080FF0C803A880BA03A880998150180D8B8
+:10DF2000C0050D801701C0D83A940410CCFFBF94EF
+:10DF30003A38CBB83AB084902E0440113A88451450
+:10DF4000C4FF3F192ECB40143A8807203A9408B0FA
+:10DF5000170080D93AC845113AB0EC20CCFFFFB089
+:10DF60003AD40E30CCFF3F323AD426B03A38E540AE
+:10DF70003A38C9383A38139A3AD406903A8849223E
+:10DF80003A8807193A38C9992E02401A740040019C
+:10DF90003A8849213AD426183A940618CCFFBF94FF
+:10DFA0003A8827993A88A51C365FC014265DC014AC
+:10DFB0003AC8A5843AC8C5143A80A784150200DA85
+:10DFC0001501C0D93AC8E714C4FF00AC26B6C08C0E
+:10DFD0003A8809983A880BA080FF0C803A88099803
+:10DFE0003A880BA0150380D8C0050D801703C0D850
+:10DFF0003A9408103AD404903A38E7B81701C0D9D7
+:10E000003AB00411170200DA2E06C0143A884514FB
+:10E01000C4FF3F1936AB40142EAAC01484FFFF186A
+:10E020003A8845143AC8E7143A880BA03A88099808
+:10E03000150400DA1503C0D81502C0D980FF0C8082
+:10E040003A880BA03A880998150180D8C0050D8040
+:10E05000170140DA3A940410CCFFBF943A386FBAF3
+:10E060003AB084901702C0D91703C0D8170400DA59
+:10E070002E06C0153A884514C4FF3F49368F401418
+:10E080002E8EC01584FF7F4A3A8845143A940A18A8
+:10E090003AC8C5153AB0642A3AD41290CCFF3F91E1
+:10E0A0003A380B223A3809393A38114A3AD4062814
+:10E0B0003A384F3A3A8809223A8807192E02001A4C
+:10E0C000740000013A880F393AD408183A940618B7
+:10E0D000CCFF7F293A88CF213A884719360AC011E8
+:10E0E0002608C0115400809406E33E0034048000EA
+:10E0F000340200B1C4FFBF103A7088203A8839A0BA
+:10E1000006553F0026DC3E183A888588C4FF3F91BB
+:10E1100036604014367DC01126A3C0113A882520F0
+:10E1200006F03F002EA2BF841700C0D83A88E180D5
+:10E130003A80C7803A88471C3A88C510C4FFFFB0B0
+:10E140002E488088366AC014266880983A882D1830
+:10E1500006973F00364F3F92FA970AB07AD0049064
+:10E16000FA9720907AD006B03AB0A428064C3F0027
+:10E1700000790F804405001148074021040840152C
+:10E18000170080D91701C0D9260A3F2804FE3F1185
+:10E190003A982C913A882500060D3F003A880930BC
+:10E1A0001501C0D9150080D900790F8044054011B0
+:10E1B0004807C0283A880910170080D90408801041
+:10E1C0001701C0D926E43E1804FE3F213A982631B3
+:10E1D0003A88110006E73E00C4FFBF044400000176
+:10E1E0003AC80924480E80201EB63E100808802038
+:10E1F0001E4E0010840781A83A9886B03AD80A913A
+:10E200003A9884903AD808B13AB064193AC00410E8
+:10E210003AB0A490CC01809026070010CC038090E7
+:10E22000200180101E040010040180903A80A51483
+:10E230003A8889243A8825102C2080202650001006
+:10E24000440080003A8809003A88250006A03E0074
+:10E250003A8839B8C4FF81003A8809003A88250015
+:10E26000069B3E001EB9BF88170000D936B73F8114
+:10E2700006B43F002E347F1184FFFF183A884514FE
+:10E2800006323F002E1EFF1484FFBFB53A884514A6
+:10E29000061C3F003A8825201E92FF11170080D8E7
+:10E2A0001E90FF1006743E000ECB3F043A880B0010
+:10E2B000440080043A88ADB406733E003A881320C7
+:10E2C00006723F003A88072006563F00CC03809034
+:10E2D00018018010266B3E1004014091C4FEBF005F
+:10E2E0003A80A514FAD00A2806F23F002E97BF8480
+:10E2F0001700C0D884FFBFB53A88E1803A80C78054
+:10E300003A88471C3A88C51006293F00170040D9B3
+:10E3100084FFBF943A8849293A804B213A884D2C92
+:10E320003A888511150000D906DB3F0044F8BF008C
+:10E330003AC82114200800213AD820B41E03002036
+:10E34000840F81A83A9888B03AB024913AC02490BA
+:10E350003AB02494CC0140911E0500283A88090067
+:10E36000FAD024903A8805003AB0649106583E00ED
+:10E37000CC038090180180103A8809001EAA3F1033
+:10E380007A9204207A970A203AD3081006F43F00C4
+:10E3900034048000340200B1C4FFBF103A708820FA
+:10E3A0003A8839B806AC3E00170040D936D7FF2866
+:10E3B0003A88252006B93F003AD510283AD50638C4
+:10E3C00034048000CCFF0142C4FFBF10D8FF81425B
+:10E3D0003A709228CCFFC1183A708438FAD70A28CC
+:10E3E000FAD70E3826060050E0FF811A1E020050B0
+:10E3F0001E01C04026088048440080003A2800F8EA
+:10E400003AB014491EFC3F50D8FFC1181EFA3F18FD
+:10E410003AB084111EF83F101EF7BF212604C02910
+:10E420001EF53F403AB004493AC004103A2800F8BB
+:10E430003A8805003A2800F83AD510283AD512381B
+:10E4400034048000CCFF0142C4FFBF10D8FF8142DA
+:10E450003A7096283A708638FAD70A28CCFF414A93
+:10E46000FAD70438260B0050D8FFC149260D0038D2
+:10E470001E1900403AB014593A000F501E130048BC
+:10E480003AB098191E1100601E0A00503A88050023
+:10E490003A2800F83AB00E591E1E0038E0FFC14974
+:10E4A000260D00383AB08E191E1A00382605004095
+:10E4B000260D80284400800026060028C4FFBF00E7
+:10E4C0003A2800F83AB00E593A000F3826F83F388B
+:10E4D00026FA3F103A2800F81EF53F483AB08E1948
+:10E4E0001EF33F3806F33F001607004A16F87F4236
+:10E4F00036F0FF1A2609C0582EE4FF5826EF3F28B1
+:10E500003A8805283A2800F81EEC3F1044008000A5
+:10E510003A2800F884FFBF003A2800F836E53F317A
+:10E520002EDABF2106F53F003AD510283AD5123829
+:10E5300034048000CCFF0142C4FFBF10D8FF8142E9
+:10E540003A7096283A708638FAD70A28CCFF414AA2
+:10E55000FAD70438260B0050D8FFC149260D0038E1
+:10E560001E1B00403AB014593A000F501E0E0048CE
+:10E570003AB098191E0C00601E0D00503A88050034
+:10E580003A2800F83AB00E591E0D0038E0FFC14994
+:10E59000260F00383AB08E191E0900381E030040BD
+:10E5A0003AB00E593A000F381E070038260C802862
+:10E5B0004400800026050028C4FFBF003A2800F868
+:10E5C000840080003A2800F826FB3F103A2800F823
+:10E5D0001EF63F483AB08E191EF43F3806F43F004D
+:10E5E0000E03004A1EF43F10440080003A2800F851
+:10E5F00016F57F4236EEFF1A2604C0582EDFFF586C
+:10E6000026ED3F283A8805283A2800F836E83F31B9
+:10E610002EDABF2106FA3F003AD5062804F5FFDEC0
+:10E62000150200DC34040004150600DD150480DC4E
+:10E63000C4FF3F84150AC0DF1509C0DD150880DD61
+:10E64000150740DD1505C0DC150340DCCCFFC11803
+:10E650003A8825203A70202CFAD72828265C001802
+:10E66000E0FF81181E710010FA9004807AD72020F4
+:10E67000FA9022204400FF1C3AB0A080342000848D
+:10E680003A882D003A882F003AD506383404000124
+:10E69000C4FF3F21CCFFC1183A702439FAD72A3879
+:10E6A00026690018E0FF81181E210010FA900890DA
+:10E6B0007AD70A30FA9010304400FF183AB008298F
+:10E6C0003A88E798342080243A880700280400B16B
+:10E6D0003AF04CA5440040991E980020BA9008B02A
+:10E6E000740082003A888520178EB9103A680010AD
+:10E6F00084E8000898E6000898E6000894E6000818
+:10E70000A4E60008A4E6000840E8000894E6000833
+:10E71000A4E6000840E80008A4E6000894E6000823
+:10E7200038E8000838E8000838E8000858E8000829
+:10E730003AB09034C4FFC19C1E690040940080B57B
+:10E740003A8825008400C00006E03F003A880DA802
+:10E750003A8821903A8823403A882F18A00080B840
+:10E760001E4D0010E00080B81E490110600080B806
+:10E7700026D800103A8807003A8821003A882300FA
+:10E78000CC3F8030340400013A950618C4FF3F2185
+:10E79000FA9704103A7020813AB0C6803AB08618D1
+:10E7A0003A880588170AC0DF1709C0DD170880DD21
+:10E7B000170740DD170600DD1705C0DC170480DCF5
+:10E7C000170340DC170200DC040BC0DE3A2800F817
+:10E7D0003AB02281263D00881501C0D9150080D9A4
+:10E7E00026E800803A88098000790F80170080D9D8
+:10E7F0001701C0D93A88071044FD7F114407000172
+:10E8000004FE7F1C3AC849213A9860843AD808919E
+:10E810003A9862943AB020244403FF043AC8E79837
+:10E820003A882D003A882F0006973F003AB022819F
+:10E830001E2100883A88210004028005C4FFC1041B
+:10E840008400C00506903F003AB090342616004080
+:10E8500026C000903A880990150080D900790F8071
+:10E86000170080D93A88071044FD3F114407400142
+:10E8700004FE3F1A3AC80B293AD84A313A9808920E
+:10E880003A9810323AB024293AC8C7984403FF1C7A
+:10E890003A880700068D3F00C4FFC1003A88210076
+:10E8A0003A88230006B63F00540080B53A88250018
+:10E8B0004400C00006853F003A88232004038005F9
+:10E8C000C4FFC104C400C005066F3F003A882100A0
+:10E8D000040180053A8827004400C005066A3F000D
+:10E8E000D40080B53A881130C400C00006773F00DC
+:10E8F0003A880DA006993F00340400043A880D00C0
+:10E90000C4FF3F84C4FF7F04C4FFC100069C3F00D6
+:10E910002C028080268900102C0280901E87001017
+:10E920003404800034020094C4FFBF103A70A08009
+:10E930003A880DA83A88234006F33F003AD4188855
+:10E940003AD42840CCFFFF42CCFF7F8C3A38475C5A
+:10E950003A38C9623A3845A43AD410183A381D6595
+:10E960003A8805113A8891402E02004174008000D7
+:10E970003A889D703AD41E90CCFFBF943A3849949F
+:10E980003A388F643A38637C3AD41A203A94144067
+:10E990003A88E389CCFF7F1A3A885B6C3AD4064008
+:10E9A0003A8853523A38C5632E02C0697400C001D8
+:10E9B0003A88C5113AD42A80CCFF3F823A382D5A82
+:10E9C0003A380FA23A38D7AA3A9414683AD418B011
+:10E9D0003AD42268CCFF3F213A88CF3A3A88155181
+:10E9E0003A88CF613A889B883A88871A3A3869A56D
+:10E9F0002E02C03A740080003A88A9A03A381792D3
+:10EA00003A38A5AC3A38117A3AD420583AD4083872
+:10EA10003A940E383A889144CCFFBFB53A881182B7
+:10EA20003A8829253A888F3D3A38597D2E0280440C
+:10EA3000740080003A8899603A940440CCFFFF5AF1
+:10EA40003A88871B3A88C5123A80951A3A88451346
+:10EA50003A88C7193A889D123A80CF193A880975C1
+:10EA60003AD410403A88D7213A8045133A80A172AF
+:10EA70003AB020143A8009253A80CF593AB0CE21D5
+:10EA80003A8821823A88E1817A9222183A88218351
+:10EA90007A922080FAD50858FAD506183AB0628AD8
+:10EAA0007A9204583AB020813AC022883AB0E2887B
+:10EAB0002C40C0803AB0A288265A00187AD0048828
+:10EAC000FA9706804C00408C7AD020803AB06214CD
+:10EAD0003AB0E288C4FFC0280E35C000CC0180885F
+:10EAE00026070010CC038088200180101E0400102F
+:10EAF000040180883A8063143A8861843A8823103C
+:10EB00002C4080802604001034C0BF00C4FFBF101A
+:10EB10003A70A0800400C128C8FF81181E5E3F1013
+:10EB20007A970480FAD022887A922080CCFFC1188C
+:10EB30003AB062143AD3208006113F0034048000BA
+:10EB400034020084C4FFBF103A70A0803A880DA040
+:10EB5000066D3F003A880930150080D900790F8092
+:10EB600044050011480740210408C010170080D94F
+:10EB7000263E3F2804FEBF103A98A4303A88110080
+:10EB800006413F0000790F804405401148070029E5
+:10EB90000408C010170080D91701C0D926173F20DC
+:10EBA00004FEBF103A98A0903A882300061A3F004E
+:10EBB000440080003AC8C510480E00111EED3E20EA
+:10EBC000080800111E190020840741293A9846813F
+:10EBD0003AD888883A984A893AD8A0803AB0041935
+:10EBE0003AC022283AB04414CC01C01026070018BD
+:10EBF000CC03C0102001C0181E0400180401C0106E
+:10EC00003A8085183A88A1803A8805182C20C0805F
+:10EC1000261B00184400C0003A8821003A882300CF
+:10EC200006D73E003A880B9806AA3F0044F83F01F9
+:10EC30003AC8C720200880103AD8C6801E030010AA
+:10EC4000840F81283A9884803AB0A2883AC02288FA
+:10EC50003AB0C488CC0140141E0500883A882100CF
+:10EC6000FAD004103A8807003AB0621406C43E0095
+:10EC7000CC03C0101801C0183A8821001EDF3F18CD
+:10EC80007A9206807A9722803AD3201806F43F00C1
+:10EC90003404800034020084C4FFBF103A70A080A6
+:10ECA00006193F00340480003AD51238C4FFBF1063
+:10ECB00004FBFFDE3A7090283A708438FAD70628B1
+:10ECC0001503C0DC150140DC3AD50A28FA90104043
+:10ECD0007AD72620FA9004107AD72230CCFF814AC6
+:10ECE000150280DC150000DC1504C0DFE0FF415296
+:10ECF0003A882518CCFF012CCC3FC0183AB0189A9E
+:10ED0000FA901A20FAD70E383AB09688FA901C304A
+:10ED10001E7100485C00C0393AC89182265AC01959
+:10ED20000E72000226810050D8FF81802616011045
+:10ED30003420C05A480E80401EFE00100808804053
+:10ED40001E5E0110040880003AC805123A98A258C5
+:10ED50003AD806723A989C703AD8045A3AB0E28887
+:10ED60003AC01C703AB0A28B3AC899603AC8636C3A
+:10ED70003A80496C3AC809612C208020269F0010F7
+:10ED80003420C004C4FFFF9C3A70E62426E00098BB
+:10ED90003A88099800790F8004FE3F1204080001A8
+:10EDA0003AC809223AD806893A98089A3A98228AA3
+:10EDB0003AB0081916CF00443AC8114444008040C4
+:10EDC0000808C0101E2501180408C0003AC887189A
+:10EDD0003AD88A883A98E2883A98C6203AD8882061
+:10EDE0003AC022883AB046193AB0621C3A882100EB
+:10EDF000CC01808826070010CC0380882001801079
+:10EE00001E0400100401C0883A80631C3A8849241B
+:10EE10003A8823182C208020267A00104400008293
+:10EE2000E0FF8140CCFF01421E8C001034E0BF00A7
+:10EE3000C4FFBF103A7084207A920810FAD022885A
+:10EE40007A970C103AD308203AB044343A951040DF
+:10EE50003404C000CC3F8094FA972490C4FFFF187C
+:10EE60003A70C6203AB0061A3AB0861C1704C0DFC2
+:10EE70001703C0DC170280DC170140DC170000DC40
+:10EE80000405C0DE3A2800F80E320002264C00507D
+:10EE9000D8FF818026BC00103420C05A480E804024
+:10EEA0001E640010080880402617011004F87F44F3
+:10EEB000200880403AD8465C1E04001004108000F0
+:10EEC0003AC805123A9884583AB09C703AC02270F9
+:10EED0003AB0E288065900003AB08A5B44003E82AC
+:10EEE0001E1A00285C00C039261AC0191E290040CD
+:10EEF000440080808CFF81101E9100103AB0466360
+:10EF00003AB0845B1E550180261B01181E64011057
+:10EF1000340088007A972260C4FFBF103A708820BE
+:10EF20003AB04424FAD02660063D00003AB0845B33
+:10EF3000268E0010C4FFBF40261F0110D8FF0142DB
+:10EF4000262D01403A881110067A3F00CC3FC03987
+:10EF50001EE6FF191E9300404400C0808CFF8118FC
+:10EF60001E2C01103AB044631EF900802673011074
+:10EF70003AB0845B1E7801107A9704603400C800B0
+:10EF8000C4FFFF183A70C6203AB0C410FAD0266009
+:10EF9000062300003AC811543A8825381E9900808B
+:10EFA0003AB0446326E30010C4FFBF40265D011061
+:10EFB000D8FF014226F900403A881110069400005B
+:10EFC0003AB0845B26020110C4FFBF402604001043
+:10EFD000D8FF0142264101403A88111006AF3F0098
+:10EFE0003A88A36B3A88C9623A805B8B3A88492396
+:10EFF0002C2080201EA6001044000004CC01808834
+:10F000001E7D3F10FAD022887A970420FAD026205D
+:10F010003A8811803AB08488E0FFC1401E2D001864
+:10F0200034040001C4FF3F213A700899CCFF01422B
+:10F0300006863F003AB0A25B3AC022883A88638BCA
+:10F040003A80498B3A8809232C20802026EB3F10F8
+:10F0500044000084E0FF8180268E0010C4FF01027E
+:10F060003A8809003A88050006783F007A971060D0
+:10F07000FAD0266026BB001034004801C4FF7F2967
+:10F080003A7046212C0280983AB0061A26080010E1
+:10F09000FAD008582C0280201E0500107A970458D8
+:10F0A0003A7046313A8825383AB086183A8827208F
+:10F0B0007AD70418FA90089834004801C4FF7F29D1
+:10F0C0003AB008117A970420FAD026203A704619EF
+:10F0D0003AB0C4103AB0C614264901183404C0002E
+:10F0E00034020099C4FFFF183A70C820C4FF01021F
+:10F0F00006563F0034E0BF00C4FFBF103A708820BE
+:10F10000CC0180883AC821821E3B3F1006BD3F00DB
+:10F110003A88098800790F80040600120808C04068
+:10F12000261E3F1804FE3F113A9808893A882300AA
+:10F1300006203F003AB0A25B3AC02288060B3F008F
+:10F140003AC8A36B3AC8E7623A80496C3AC8279933
+:10F150002C2080981EBB00103AB0C48C1E0B3F10B0
+:10F160003A8827003A88250006AD3F003400880021
+:10F170007A972260C4FFBF103A7088203AB04424C6
+:10F18000FAD0266006A43F00340088007A972260F7
+:10F19000C4FFBF103A7088203AB04424FAD02660E9
+:10F1A00006CC3F003AC81154264F0080D8FF81504A
+:10F1B00026B4001034200063480E80401EC40010A6
+:10F1C000080880401EF90010040880003AC80512A3
+:10F1D0003A98A2603AD8066A3A9884683AD8106297
+:10F1E0003AB0E2883AC004103AB0A2883A88175A76
+:10F1F0003A88A38B3A80858B3A88C9123A88215085
+:10F2000006913F00D8FF815026640010342000632F
+:10F21000480E80401E750010080880401EB6001081
+:10F22000040880003AC805123A98A2603AD8066AE3
+:10F230003A9884683AD810623AB0E2883AC004102A
+:10F240003AB0A2883AC8175A3AC863743A804574EB
+:10F250003AC889583A88215006C73E0044F83F42D0
+:10F260002008C0103AD810221E0400180410C00054
+:10F270003AC885183A9888203AB022893AC022883C
+:10F280003AB0228A3A8809003A882100065B3F009A
+:10F290008400000434E0BF00C4FFBF103A70842033
+:10F2A0007AD00688FA970A104C00408C3AB0621C5B
+:10F2B0007AD008103AB0622C06CD3E0004F87F44A4
+:10F2C000200880403AD8465C1E04001004108000DC
+:10F2D0003AC805123A9884583AB09C703AC02270E5
+:10F2E0003AB0E28806A13E003AB0446326A5001079
+:10F2F000C4FFBF4026BD0010D8FF01422661004078
+:10F300003A88111006AC3F00040880003AC8051284
+:10F310003A98A2583AD806723A989C703AD8045A49
+:10F320003AB0E2883AC01C703AB0A28B3A88996031
+:10F3300006423F007A9708583400C800C4FFFF18FF
+:10F340003A70CC303AB08421FAD0265806323F00C9
+:10F35000264C00103AB09C5B7A971060FAD0266079
+:10F360001E453F7034008800C4FFBF103A708420EF
+:10F370003AB0041206573F0026793F107A97045896
+:10F380003400C800C4FFFF183A70C6303AB0C41049
+:10F39000FAD026583A88253806213F007A97045833
+:10F3A0003400C800C4FFFF183A70C6303AB0C41029
+:10F3B000FAD0265806473F003AC8A36B3AC8C9623C
+:10F3C0003A805B6C3AC8492344000004066A3E0058
+:10F3D0007A9704603400C800C4FFFF183A70C82050
+:10F3E0003AB00411FAD02660060B3F003AB06663CB
+:10F3F0003AC0229806943F007A9704603400C8000F
+:10F40000C4FFFF183A70C8203AB00411FAD0266041
+:10F4100006303F00E0FF81181E103F103A889D6BB8
+:10F420003A88C9623A8045733A888520FA97221053
+:10F430007AD01C707AD008103A8821183AB0A28B82
+:10F4400006EE3E003AC863733AC8095B3A806774B7
+:10F450003AC8E7243A882538064C3E001E033F1878
+:10F46000265D0010340088007A970658C4FFBF104C
+:10F470003A7084303AB0C410FAD026583A88253809
+:10F4800006143F00340088007A970658C4FFBF1066
+:10F490003A7084303AB0C410FAD02658060D3F00B6
+:10F4A0003AC8A36B3AC8C5623A80496C3AC8091198
+:10F4B0002C208020263A00103AC863733AC8095BB2
+:10F4C0003A805D743AC889233A88253806483E0058
+:10F4D0003AB062633AC0228806453F007A970460DA
+:10F4E0003400C800C4FFFF183A70C6203AB0C410F8
+:10F4F000FAD0266006F73E0004F8BF402008C0405E
+:10F500003AD884601E0400180410C0043AC8119A46
+:10F510003A9826623AB0DA6C3AC022683AB0A288C9
+:10F5200006493F003AC863733AC8095B3A805D7484
+:10F530003AC8892344000004060F3E0034008800C6
+:10F540007A970658C4FFBF103A7084303AB0C4109E
+:10F55000FAD0265806B23E003A88A36B3A88C962B0
+:10F560003A805B8B3A8849232C20802026A33E10CA
+:10F5700034E0BF00C4FFBF103A708820440000048C
+:10F58000069E3E00340088007A970658C4FFBF10DC
+:10F590003A7084303AB0C410FAD02658069E3E0025
+:10F5A0003AB0048926EE3E1006943E0004F8BF40AF
+:10F5B0002008C0403AD884601E0400180410C0041B
+:10F5C0003AC8119A3A9826623AB0DA6C3AC0226880
+:10F5D0003AB0A28806063F003404C004C4FFFF9C72
+:10F5E0003A882500C4FFBF0006BC3E003A88A36BE2
+:10F5F0003A88C9623A809D8B3A888923067C3E000E
+:10F600003A880500C4FF01023A880900060F3E004F
+:10F610003AD506283AD5103834048000CCFFC118FA
+:10F62000C4FFBF10D8FFC1183A708A283A708E38CC
+:10F63000CCFF014226040018D8FF014226060040F4
+:10F640003A8805003A2800F83AB04A2126FA3F28BD
+:10F65000440080003A2800F83AB08E393AC00438A5
+:10F660003A2800F83AD50C283404C000C4FFFF182B
+:10F67000CCFF8131D0FFC0313A70C628FAD70A28B2
+:10F680001E060038900781301E0600103400A000CE
+:10F69000C4FFBF103A8885283A2800F83A88050048
+:10F6A0003A2800F8C40C81003AC88F110808803845
+:10F6B0003404C0181E07001044FBBE303A98861868
+:10F6C0003AD8C4213AB0841826F53F283AC88500B4
+:10F6D0003A2800F8C40481003AC885113AD8841841
+:10F6E00006F93F0004FDFFDE1502C0DF150140DC16
+:10F6F000150000DC261300203A882120FAD72220AA
+:10F70000162100203A88098000790F8084070101C2
+:10F710003AC88920C802C010CCFF01211E1C001865
+:10F72000C40280013AC88D303AD88A813404C000BE
+:10F7300044058010C4FFFF183A9884803A70CA28A4
+:10F74000060400003A8823003A8809003A880B0032
+:10F750003A8805003A950820CC3F408C340480015B
+:10F76000C4FFBF31FA9706883A708A293AB00A294D
+:10F770003AB0C6281702C0DF170140DC170000DCD2
+:10F780000403C0DE3A2800F83AC8210106DD3F0034
+:10F7900044FDBF103A988A8034048000C4FFBF1033
+:10F7A0003A708A283A88050006EA3F0004FEFFDE28
+:10F7B000150000DC1501C0DF3A882120260F00204B
+:10F7C00000790F80840701013AC88920C802C0105F
+:10F7D000CCFF01211E150018C402C0003AC88718CA
+:10F7E0003AD8C6803404400144058010C4FF7F2904
+:10F7F0003A98A0803A704419060200003A8809003D
+:10F800003A8805003A9508203404C000C4FFFF1868
+:10F810003A70C6103AB006193A8805801701C0DF61
+:10F82000170000DC0402C0DE3A2800F844FDBF10D7
+:10F830003A9884803404C000C4FFFF183A70C410A2
+:10F840003A88210006EF3F00D4FFBF00360B0011BD
+:10F85000304080201E0700103AD2082004064001E4
+:10F860003401C2003A88C72003899D183AC8852808
+:10F870003A2800F80408400106F93F0034408000AF
+:10F88000360380203AD608200402400106F43F00E7
+:10F890003AD408200404400106F13F0004FCFFDED6
+:10F8A0001503C0DF150200DF040200DF15FE3FE193
+:10F8B000040460D117FE3FE14040378015FFBFE0F0
+:10F8C00017FFBFE02609001017FFBFE017038010E5
+:10F8D0002606001017FFBFE01703801017FE7FE118
+:10F8E00017FF3FE13AE83E100601000017FFBFE0B6
+:10F8F0003A8837E01701C0DF170000DF0402C0DEDE
+:10F900003A2800F804FDFFDE1502C0DF150100DF14
+:10F91000040100DF15FF3FE117FFBFE026080010DC
+:10F9200017FFBFE0170480102605001017FFBFE087
+:10F930001704801017FF3FE13AE83E103A880100B3
+:10F940003A8801003A8837E01701C0DF170000DF6E
+:10F950000402C0DE3A2800F804FEFFDE1501C0DF15
+:10F96000150000DF3A8839D81727A0D026030010E9
+:10F970001727A0D03AE83E10060100000442A0D0AC
+:10F980003A8837E01701C0DF170000DF0402C0DE4D
+:10F990003A2800F804FBFFDE1504C0DF150300DF82
+:10F9A000040300DF15FE3FE115FD7FE117FEBFE018
+:10F9B0001606001017FEBFE02403C0107401820079
+:10F9C000041AB2103A888518060100003A8805002A
+:10F9D00015FFBFE017FFBFE02610001017FFBFE0C4
+:10F9E00017008010170880102607001017FFBFE0CF
+:10F9F000170080101708801017FD7FE117FF3FE107
+:10FA00003AE83E10060A000017FDBFE00400C800F7
+:10FA10001501C0103A88050006050000008A0F8015
+:10FA20003A8807104414800015008018C4FFBF00F6
+:10FA30003A8837E01701C0DF170000DF0402C0DE9C
+:10FA40003A2800F804FEFFDE1501C0DF150000DFD4
+:10FA50003A8839D81727A0D0260300101727A0D03E
+:10FA60003AE83E10060100000442A0D03A8837E090
+:10FA70001701C0DF170000DF0402C0DE3A2800F8DB
+:10FA800004EAFFDE1515C0DF151400DF041400DFE3
+:10FA900015EC3FE117ECBFE01606001017ECBFE0D5
+:10FAA0002403C01074018200041AB2103A88851829
+:10FAB000060100003A88050015FFBFE017FFBFE010
+:10FAC000260E001017FFBFE01700801017088010E7
+:10FAD0001E02001044008000060D000004EDBFE08F
+:10FAE0003A880B1017EC3FE1C08D0F8017EEBFE096
+:10FAF00020008810CC3F801006050000C0980F80C1
+:10FB00003A88071044148000150080183A880500D0
+:10FB10003A8837E01701C0DF170000DF0402C0DEBB
+:10FB20003A2800F804FEFFDE1501C0DF150000DFF3
+:10FB30003A8839D81727A0D0260300101727A0D05D
+:10FB40003AE83E10060100000442A0D03A8837E0AF
+:10FB50001701C0DF170000DF0402C0DE3A2800F8FA
+:10FB600004F9FFDE1506C0DF150500DF040500DF20
+:10FB700015FD3FE115FC7FE115FBBFE115FF3FE0FF
+:10FB800017FDBFE01606001017FDBFE02403C010EC
+:10FB900074018200041AB2103A8885180601000028
+:10FBA0003A88050015FEBFE017FEBFE026100010E2
+:10FBB00017FEBFE0170080101707801026090010FD
+:10FBC00017FEBFE0170080101707801017FBBFE17A
+:10FBD00017FC7FE117FE3FE13AE83E1015FFBFE05A
+:10FBE0000605000084DEBF0015FFBFE0060200002E
+:10FBF000C4EBBF0015FFBFE017FFBFE00E0700100A
+:10FC0000C0A60F803A88071017FFBFE03AC88500EA
+:10FC100015008018C4FFBF0015FFBFE017FFBFE04D
+:10FC20003A8837E01701C0DF170000DF0402C0DEAA
+:10FC30003A2800F804FBFFDE1504C0DF150300DFDF
+:10FC4000040300DF3A880900807C1780C0771080A9
+:10FC500044000001407715801548A0D04400000101
+:10FC600040771580154AA0D0048BA0D015FEBFE0C8
+:10FC7000440080008DFDBFE08BFDBFE03A88091095
+:10FC8000407715803A88071017FEBFE01500C010B6
+:10FC9000008017803401820104C99D313401420182
+:10FCA00004C95D293401020104C91D21807D37800A
+:10FCB00040343780F400020104E91C2100A942808D
+:10FCC0001744A0D01745E0D0174620D13A880D2020
+:10FCD0003A880B183A8809108017018015FFBFE099
+:10FCE0004400000100A6228017FF3FE1C0AB428024
+:10FCF00004F9FFDE150600DF040600DF15FA3FE118
+:10FD00003A30050015FDBFE017FDFFE084FFBF009E
+:10FD10003A7084183A70011017FDBFE015FFBFE07C
+:10FD20001706A0D0C400C01004FFBF003A708418AA
+:10FD30001506A0D01706E0D017FABFE03A8887185A
+:10FD400034008400040080102E06C01017FFBFE0AE
+:10FD500015FCBFE017FCBFE03A700110C4FFBF0004
+:10FD6000060B00001706A0D015FEBFE01706E0D076
+:10FD700017FABFE03A8885181506A0D017FFBFE034
+:10FD800015FBBFE017FBBFE03A70011017FEBFE0A4
+:10FD90003A8837E0170000DF0401C0DE3A2800F897
+:10FDA00004DFFFDE1520C0DF151F00DF041F00DFAA
+:10FDB00015E13FE104E4BFE03A880B10C43F0001C5
+:10FDC0000022178045E2BFE043E2BFE0CC3F801055
+:10FDD0001E1E001083F0BFE0CC3F801015FFBFE077
+:10FDE0001748A0D084E2FFE03A880B183A8809103F
+:10FDF00040E81580C3E3BFE0CC3F80102607001029
+:10FE00001707A0D017FFFFE01E0480181747A0D0E7
+:10FE1000440080101547A0D0060A00001748A0D063
+:10FE200044E2FFE03A880D183A880B003A8809103E
+:10FE300000A61580440080001547A0D017FFBFE042
+:10FE40001507A0D03A880100060100003A88010099
+:10FE50003A8837E01701C0DF170000DF0402C0DE78
+:10FE60003A2800F804FDFFDE1502C0DF150100DFAF
+:10FE7000040100DF15FF3FE11747A0D0260B00105B
+:10FE80001747A0D0C4FFBF101547A0D01747A0D078
+:10FE90001E070010C4FFBF001507A0D01748A0D050
+:10FEA0003A88091040D81580060100003A88010000
+:10FEB0003A8837E01701C0DF170000DF0402C0DE18
+:10FEC0003A2800F804DBFFDE1524C0DF152300DF2D
+:10FED000042300DF15DD3FE115FF3FE0434BA0D0D9
+:10FEE000CC3F8010600080102636001004E0BFE098
+:10FEF0003A880B10C43F00010022178045DEBFE0A6
+:10FF000043DEBFE0CC3F80101E30001083ECBFE02A
+:10FF1000CC3F801015FEBFE0174AA0D084DEFFE082
+:10FF20003A880B183A88091040E815803A300500E5
+:10FF300015FDBFE017FDFFE084FFBF003A70841895
+:10FF40003A70011017FDBFE015FFBFE08BDEBFE088
+:10FF5000CCFFBF101E0B00101708A0D017FEFFE04B
+:10FF60001E0880181749A0D0440080101549A0D061
+:10FF700017FFBFE015FCBFE017FCBFE03A700110AF
+:10FF8000060E000017FFBFE015FBBFE017FBBFE048
+:10FF90003A700110174AA0D044DEFFE03A880D18ED
+:10FFA0003A880B003A88091000A6158044008000AA
+:10FFB0001549A0D017FEBFE01508A0D03A8801006F
+:10FFC000060300003A880100060100003A8801009B
+:10FFD0003A8837E01701C0DF170000DF0402C0DEF7
+:10FFE0003A2800F804F8FFDE1507C0DF150600DF29
+:10FFF000040600DF15FA3FE115FF3FE0434BA0D0B8
+:020000021000EC
+:10000000CC3F801060008010262300103A3005009D
+:1000100015FEBFE017FEFFE084FFBF003A708418B2
+:100020003A70011017FEBFE015FFBFE01749A0D0DE
+:100030001E05001017FFBFE015FDBFE017FDBFE074
+:100040003A700110061500001749A0D0C4FFBF1078
+:100050001549A0D01749A0D01E0A0010C4FFBF0048
+:100060001508A0D017FFBFE015FCBFE017FCBFE0EC
+:100070003A700110174AA0D03A88091040D815806C
+:100080000606000017FFBFE015FBBFE017FBBFE04F
+:100090003A700110060100003A8801003A8837E002
+:1000A0001701C0DF170000DF0402C0DE3A2800F8A5
+:1000B00004F7FFDE1508C0DF150700DF040700DFC7
+:1000C00015FB3FE115FA7FE115F9BFE115FF3FE0B0
+:1000D0000357A0D0CC3F80102605001017F9BFE0D1
+:1000E0004404C0000500C0103A8805000621000045
+:1000F00017FBBFE003008010CC3F8010C4FFBF108F
+:10010000280180102605001017F9BFE04400C00048
+:100110000500C0103A880500061600003A88010064
+:100120003A30050015FCBFE017FCFFE084FFBF007C
+:100130003A7084183A70011017FCBFE015FFBFE059
+:1001400017FBBFE0840380103A880B1017FA3FE1D9
+:10015000007A1180C5FEBFE017FFBFE015FDBFE0CC
+:1001600017FDBFE03A70011017F9BFE0050000105D
+:10017000C3FEBFE03A8837E01701C0DF170000DF99
+:100180000402C0DE3A2800F804F6FFDE1509C0DFDD
+:10019000150800DF040800DF15FA3FE115F97FE1DB
+:1001A00015F8BFE115FF3FE00357A0D0CC3F80100A
+:1001B0002604001017F8BFE08404C0000500C0103A
+:1001C000062C000017FABFE003008010CC3F80101F
+:1001D000C4FFBF10280180102604001017F8BFE0EC
+:1001E0004400C0000500C010062200003A8801004B
+:1001F0003A30050015FDBFE017FDFFE084FFBF00AA
+:100200003A7084183A70011017FDBFE015FFBFE087
+:1002100017F93FE140811180C5FEBFE0C3FEBFE09A
+:10022000300880101E08001017FFBFE015FCBFE06B
+:1002300017FCBFE03A70011017F8BFE0C402C0001D
+:100240000500C010060B000017FABFE08403801001
+:1002500017F97FE13A880910007A118017FFBFE093
+:1002600015FBBFE017FBBFE03A70011017F8BFE0C5
+:10027000050000103A8837E01701C0DF170000DFE3
+:100280000402C0DE3A2800F804EDFFDE1512C0DFDC
+:10029000151100DF041100DF15F23FE115F17FE1D8
+:1002A00015F0BFE13A8805380DEFBFE015FB3FE0E0
+:1002B00017F1BFE01500001017F2BFE015FFBFE017
+:1002C00017FFBFE01700801015FEBFE00619000001
+:1002D00017FEBFE003008010CC3F8010A000C010CC
+:1002E0001E090018E000C0101E09001860008010F0
+:1002F0001E090010170280E04400C0000500C01075
+:100300003A880500064601003A880100060300000D
+:100310003A880100060100003A88010017FFBFE09B
+:100320000401801015FFBFE017FFBFE01700801029
+:1003300015FEBFE017FEBFE01EE53F100357A0D03B
+:10034000CC3F801026050010170280E08400C0001A
+:100350000500C0103A88050006310100034BA0D00B
+:10036000CC3F801026050010170280E04403C00037
+:100370000500C0103A880500062901003A30050042
+:1003800015F9BFE017F9FFE084FFBF003A70841849
+:100390003A70011017F9BFE015FBBFE0C5FD3FE063
+:1003A0000DFD3FE0C5FC3FE017F2BFE015FFBFE0E9
+:1003B00017FFBFE01700801015FEBFE006810000A8
+:1003C00017FEBFE003008010CC3F8010A000C010DB
+:1003D0001E3C0018E000C0101E03001860008010D2
+:1003E0001E1E00100666000017FEBFE00B02801004
+:1003F000CCFFBF102615001017FEBFE00B028010C7
+:10040000C4FFBF103A88071017FEBFE00D02C010EE
+:1004100017F1BFE00401C01015F1FFE017FEFFE087
+:100420001500C01044008000C5FDBFE017F0BFE01C
+:100430000401C01015F0FFE0150000100BFDBFE037
+:10044000440080100DFDBFE006580000C3FCBFE073
+:1004500054008010C5FCBFE00654000017FEBFE04A
+:10046000170180102613001017F0BFE00401C01020
+:1004700015F0FFE017FEFFE01701C0181500C010CF
+:1004800017FEBFE01501001017F1BFE00401C01016
+:1004900015F1FFE017FEFFE01500C01044008000DA
+:1004A000C5FDBFE00BFDBFE0440080100DFDBFE0C7
+:1004B000063E0000C3FCBFE094008010C5FCBFE016
+:1004C000063A000017FEBFE01701801015FABFE0E2
+:1004D00017FABFE08B058010CCFFBF102624001058
+:1004E00017FABFE01704C0100401001917FABFE0A3
+:1004F0001504001117F0BFE00401001115F03FE1F1
+:100500001700C0181500C01017FABFE01704C0107C
+:1005100017FABFE0170280101E04801817FABFE018
+:100520001701C01017FABFE01504C01017FABFE09A
+:100530008B058010C4FFBF103A88071017FABFE080
+:100540008D05C01017F1BFE00401C01015F1FFE0E8
+:1005500017FEFFE01500C01044008000C5FDBFE09D
+:100560000BFDBFE0440080100DFDBFE0060F000052
+:10057000C3FCBFE014018010C5FCBFE0060B000007
+:1005800017FBBFE015F8BFE017F8BFE03A700110A5
+:1005900017F1BFE015000010170280E04400C00012
+:1005A0000500C0100BFDBFE0069D000017FFBFE077
+:1005B0000401801015FFBFE017FFBFE01700801097
+:1005C00015FEBFE017FEBFE01E7D3F10C3FDBFE07C
+:1005D000580080101E0A001017F1BFE0150000102F
+:1005E00017FBBFE015F7BFE017F7BFE03A70011047
+:1005F000170280E0050000100BFDBFE00688000038
+:100600001758A0D0030C8010C3FCFFE03AB0841848
+:100610003A8809101758A0D004E0FF003AB0C6206D
+:10062000050CC0101758A0D0450C00101758A0D0CA
+:100630000BEFFFE08D0BC01017F23FE180F610804A
+:1006400017FBBFE015F5BFE017F5BFE03A700110EA
+:10065000C06611803A30050015F6BFE017F6FFE0DE
+:1006600084FFBF003A7084183A70011017F6BFE09B
+:1006700015FBBFE01758A0D0430C8010CC3F801072
+:1006800026020010980080101E1800101758A0D0E5
+:100690001707801015FEBFE017FEBFE0260B001005
+:1006A00017F1BFE00401C01015F1FFE017FEFFE0F5
+:1006B0001500C01017F1BFE0150000100BFDBFE0E2
+:1006C000440080100DFDBFE0060D00001758A0D0BB
+:1006D0004400C000450CC0101758A0D017F27FE1AD
+:1006E0003A88091000161180060500001758A0D09E
+:1006F00017F27FE13A880910001611803A8801004C
+:100700001758A0D0430C8010CC3F80102603001057
+:10071000A00080101E230010062A000017FEBFE074
+:1007200003008010CC3F80100E108000D000C0105D
+:100730001E070018D80080101E0C001017F0BFE034
+:100740000401C01015F0FFE01500001006120000B3
+:100750001758E0D017F0BFE00401001115F03FE199
+:100760001709C0181500C010060B000017FBBFE0EA
+:1007700015F4BFE017F4BFE03A70011017F1BFE0C5
+:1007800015000010170280E04400C0000500C010F2
+:100790000BFDBFE006220000170280E005000010FC
+:1007A0000610000017F0BFE00401C01015F0FFE0D4
+:1007B00015000010170280E08403C0000500C0107F
+:1007C0000608000017F0BFE00401C01015F0FFE0BC
+:1007D00015000010170280E08402C0000500C01060
+:1007E0003A8801001758A0D0050C00101758A0D067
+:1007F000450C00101758A0D0150700101758A0D0AE
+:10080000150800101758A0D01509001017FBBFE0FD
+:1008100015F3BFE017F3BFE03A7001100BFDBFE026
+:100820003A8837E01701C0DF170000DF0402C0DE9E
+:100830003A2800F804FEFFDE1501C0DF150000DFD6
+:100840003A8839D880653880003A1180C03D1180DF
+:10085000C04C1180002C118080ED128080651380C7
+:10086000C062158080441180806738803A8801001A
+:100870003A8837E01701C0DF170000DF0402C0DE4E
+:100880003A2800F804FFFFDE150000DF3A8839D867
+:10089000434BA0D0CC3F8010580080101E070010A2
+:1008A0000357A0D0CC3F8010E03F80101E03001003
+:1008B0000357A0D0440080100557A0D03A8801000B
+:1008C0003A8837E0170000DF0401C0DE3A2800F85C
+:1008D00004FBFFDE1504C0DF150300DF040300DFA7
+:1008E00015FF3FE0434BA0D0CC3F80105800801054
+:1008F0001E2D00103A30050015FEBFE017FEFFE088
+:1009000084FFBF003A7084183A70011017FEBFE0F0
+:1009100015FFBFE00357A0D0CC3F80102603001086
+:100920000357A0D0C4FFBF100557A0D00357A0D0D5
+:10093000CC3F80101E180010034BA0D0CC3F80107D
+:100940001E15001040731180034DE0D0434DA0D020
+:10095000CC3FC018CC3F8010260F8018034DA0D08C
+:10096000CC3F8010BA900610B40182003A888518F6
+:10097000175DB5101553A0D01753A0D0170EC01097
+:100980004400C018150EC010174FA0D044008010AE
+:10099000154FA0D08038388017FFBFE015FDBFE0AD
+:1009A00017FDBFE03A7001103A8801003A8837E03D
+:1009B0001701C0DF170000DF0402C0DE3A2800F88C
+:1009C00004FCFFDE150300DF040300DF15FF3FE03A
+:1009D000434BA0D0CC3F8010580080101E16001052
+:1009E0003A30050015FEBFE017FEFFE084FFBF00B0
+:1009F0003A7084183A70011017FEBFE015FFBFE08F
+:100A00000357A0D0CC3F80101E070010034BA0D08E
+:100A1000CC3F8010E03F80101E030010034BA0D09D
+:100A200044008010054BA0D017FFBFE015FDBFE0CC
+:100A300017FDBFE03A7001103A8801003A8837E0AC
+:100A4000170000DF0401C0DE3A2800F804F8FFDEDA
+:100A50001507C0DF150600DF040600DF15FF3FE0C5
+:100A6000434BA0D0CC3F8010580080101E280010AF
+:100A70003A30050015FEBFE017FEFFE084FFBF001F
+:100A80003A7084183A70011017FEBFE015FFBFE0FE
+:100A9000034BA0D0CC3F801026190010034BA0D0F0
+:100AA000C4FFBF10054BA0D0034BA0D0CC3F80109B
+:100AB0001E0E00100357A0D0CC3F80101E06001061
+:100AC00017FFBFE015FDBFE017FDBFE03A70011052
+:100AD000C0661180060E000017FFBFE015FCBFE0E6
+:100AE00017FCBFE03A7001100609000017FFBFE0D5
+:100AF00015FBBFE017FBBFE03A70011006040000D1
+:100B000017FFBFE015FABFE017FABFE03A70011017
+:100B10003A8801003A8837E01701C0DF170000DF8C
+:100B20000402C0DE3A2800F804FEFFDE1501C0DF33
+:100B3000150000DF3A8839D8434BA0D0CC3F801055
+:100B40001E0D001040731180034DA0D0454DA0D064
+:100B5000034DA0D0CC3F8010BA900610B4018200A3
+:100B60003A888518175DB5101553A0D01753A0D03B
+:100B70001558A0D0404138803A8801003A8837E0C3
+:100B80001701C0DF170000DF0402C0DE3A2800F8BA
+:100B900004F8FFDE1507C0DF150600DF040600DFDE
+:100BA00015FE3FE0C06238803A30050015FCBFE01A
+:100BB00017FCFFE084FFBF003A7084183A70011000
+:100BC00017FCBFE015FEBFE01759A0D0440080100D
+:100BD0001559A0D017FEBFE015FDBFE017FDBFE01F
+:100BE0003A700110434BA0D0CC3F801058008010C9
+:100BF0001E510010174EA0D015FFBFE0064900009F
+:100C00003A30050015FBBFE017FBFFE084FFBF0093
+:100C10003A7084183A70011017FBBFE015FEBFE070
+:100C200017FFBFE08B0B8010CCFFBF1026360010E3
+:100C300017FFBFE08B0B8010C4FFBF103A8807106E
+:100C400017FFBFE08D0BC01017FFBFE08B0B8010AC
+:100C5000CCFFBF101E2C001017FFBFE0030C80104C
+:100C6000CC3F8010CC0D8010260B001017FFBFE08A
+:100C7000030CC01004F2BF003A7084183A880710C1
+:100C800017FFBFE0050CC01017FFBFE04400C00015
+:100C9000450CC0100602000017FFBFE0450C001015
+:100CA00017FFBFE0030C8010CC3F80100C028010B7
+:100CB0001E15001017FFBFE0830DC0100355A0D014
+:100CC0003AB084180555A0D017FFBFE0030D80107F
+:100CD000CC3FC0104455A0D03A88851803000011BD
+:100CE00017FFBFE0430D801017FFFFE0030DC01892
+:100CF000CC3FC0183AB084203A8809104455A0D09F
+:100D00003A8885180500001117FFBFE0170580100D
+:100D100015FFBFE017FEBFE015FABFE017FABFE00E
+:100D20003A70011017FFBFE0830C8010CC3F801099
+:100D3000180580101EB23F103A8801003A8837E04B
+:100D40001701C0DF170000DF0402C0DE3A2800F8F8
+:100D500004FFFFDE150000DF3A8839D884478000A1
+:100D60003A8837E0170000DF0401C0DE3A2800F8B7
+:100D700004FFFFDE150000DF3A8839D83A88010009
+:100D80003A8837E0170000DF0401C0DE3A2800F897
+:100D900004F8FFDE1507C0DF150600DF040600DFDC
+:100DA00015FD3FE115FC7FE13A8805303A880738A8
+:100DB00005FBBFE03A88051805FABFE017FDBFE064
+:100DC00083028010CC3FC010340182003A8885181D
+:100DD00003CD9D10C5FFBFE0C3FFBFE017FDFFE0DF
+:100DE0003A888518C3028010CC3FC01034018200BD
+:100DF0003A88851803CD9D1085FFBFE0C3FFBFE093
+:100E0000FA9004103A88071083FFBFE03A88C510B3
+:100E100045FFBFE043FFBFE0BA900610B401820077
+:100E20003A888518175DB51015FEBFE017FEBFE0C4
+:100E30008D0B001017FEBFE017FCFFE01509C01076
+:100E400017FEBFE0030C80103A88071003FBBFE0D9
+:100E50003A3084003A7084183A88071017FEBFE0D1
+:100E6000050CC01017FEBFE003FAFFE0450CC010F0
+:100E700017FEBFE0030C8010CC3F80100C028010E6
+:100E80001E11001017FEBFE0830DC0100355A0D047
+:100E90003AB084180555A0D0C3FFFFE04455A0D058
+:100EA0003A8885180300001117FEBFE0430D80103B
+:100EB000C3FFFFE03AB084203A8809104455A0D01F
+:100EC0003A8885180500001117FD7FE117FE3FE104
+:100ED000000B118017FEBFE01708801026080010D5
+:100EE00017FEBFE0170880103A880B1017FE3FE18D
+:100EF0000016118017FEBFE017FDFFE01507C010B8
+:100F000043FFBFE03A8837E01701C0DF170000DF7A
+:100F10000402C0DE3A2800F804FDFFDE150200DFFF
+:100F2000040200DF15FE3FE11758A0D017FEFFE0D6
+:100F30001507C0101758A0D0030D8010CC3F8010AB
+:100F400017FEFFE03A888518C30200111758A0D099
+:100F5000430DC0101758A0D0030D8010CC3F801057
+:100F60003AB0C6203A88091817FEFFE03A8885187B
+:100F7000C502001117FEBFE08302C0101758A0D0B1
+:100F8000830D80103AB084183A88071017FEBFE02E
+:100F90008502C0101758A0D0030D8010C5FFBFE018
+:100FA000C3FFFFE04455A0D03A88851803008010A5
+:100FB0003A8807101758A0D0430D80103A308400AB
+:100FC0003A708418C3FFFFE03A8809104455A0D056
+:100FD0003A88851805000011C3FFFFE04455A0D0F2
+:100FE0003A88851803008010CC3F80101E0700103F
+:100FF0001758A0D0830D80103A3084003A8807102B
+:101000000355A0D03A7084180555A0D03A88010045
+:101010003A8837E0170000DF0401C0DE3A2800F804
+:1010200004FBFFDE150400DF040400DF15FC3FE1D4
+:101030001758A0D0150700101758A0D017FCFFE0D4
+:101040001508C01017FCBFE015FFBFE017FFBFE099
+:101050001700801015FEBFE0061E00001758A0D034
+:10106000030D8010CC3F801017FEFFE03A888518F2
+:10107000C30200111758A0D0430DC0101758A0D0BC
+:10108000030D8010CC3F80103AB0C6203A88091872
+:1010900017FEFFE03A888518C502001117FEBFE071
+:1010A0008302C0101758A0D0830D80103AB0841866
+:1010B0003A88071017FEBFE08502C01017FFBFE097
+:1010C0000401801015FFBFE017FFBFE0170080107C
+:1010D00015FEBFE017FEBFE01EE03F101758A0D07E
+:1010E000030D8010C5FDBFE0C3FDFFE04455A0D057
+:1010F0003A888518030080103A8807101758A0D046
+:10110000430D80103A3084003A708418C3FDFFE02C
+:101110003A8809104455A0D03A8885180500001176
+:10112000C3FDFFE04455A0D03A8885180300801025
+:10113000CC3F80101E0700101758A0D0830D8010E0
+:101140003A3084003A8807100355A0D03A708418CA
+:101150000555A0D03A8801003A8837E0170000DF33
+:101160000401C0DE3A2800F804FCFFDE150300DFAE
+:10117000040300DF15FE3FE115FD7FE117FEBFE030
+:10118000030D8010C5FFBFE0C3FFBFE017FDFFE008
+:101190003A888518C30280103A88071017FEBFE00E
+:1011A000430D80103A3084003A7084183A88071052
+:1011B000C3FFBFE03A88091817FDFFE03A88851899
+:1011C000C5020011C3FFBFE017FDFFE03A88851894
+:1011D000C3028010CC3F80101E0A001017FDBFE034
+:1011E000830280103A88071017FEBFE0830D80103D
+:1011F0003A3084003A7084183A88071017FDBFE02F
+:101200008502C0103A8801003A8837E0170000DFF5
+:101210000401C0DE3A2800F804FAFFDE150500DFFD
+:10122000040500DF15FC3FE115FB7FE117FCBFE083
+:10123000030D8010C5FDBFE017FCBFE0830D8010DB
+:1012400085FDBFE017FCBFE0430D801045FDBFE00A
+:1012500017FBBFE015FFBFE017FFBFE017008010CE
+:1012600015FEBFE006230000C3FDBFE017FEFFE050
+:101270003A888518C30280103A88071043FDBFE002
+:101280003A3084003A7084183A880710C3FDBFE0F2
+:101290003A88091817FEFFE03A888518C502001140
+:1012A000C3FDBFE017FEFFE03A888518C302801037
+:1012B000CC3F80101E09001017FEBFE08302801093
+:1012C0003A88071083FDBFE03A3084003A708418F2
+:1012D0003A88071017FEBFE08502C01017FFBFE075
+:1012E0000401801015FFBFE017FFBFE0170080105A
+:1012F00015FEBFE017FEBFE01EDB3F103A8801007D
+:101300003A8837E0170000DF0401C0DE3A2800F811
+:1013100004FCFFDE150300DF040300DF15FD3FE1E1
+:1013200017FDBFE08502001017FDBFE0C40280106A
+:1013300015FFBFE0C5FE3FE00607000017FFBFE056
+:101340004400C01015FFFFE005000010C3FEBFE021
+:1013500044008010C5FEBFE0C3FEBFE0F000801077
+:101360001EF63F103A8801003A8837E0170000DF88
+:101370000401C0DE3A2800F804FBFFDE1504C0DFDC
+:10138000150300DF040300DF04D04201B4010201B1
+:1013900004EB3121005B1180B401820004EBB11039
+:1013A00015FEBFE0B401820004F7B11015FDBFE0E7
+:1013B0008DFF3FE00613000017FEBFE005000010A0
+:1013C00017FEBFE017FDFFE01501C01017FEBFE0DC
+:1013D000C40FC0008503C01017FEBFE0C503001096
+:1013E00017FEBFE0040C801015FEBFE017FDBFE044
+:1013F000040C801015FDBFE08BFFBFE0440080109F
+:101400008DFFBFE08BFFBFE0F00E80101EEA3F10A3
+:1014100017FEBFE00500001017FEBFE01501001029
+:1014200017FEBFE0C40FC0008503C01017FEBFE069
+:10143000C5030010B401820004EBB1101556A0D012
+:101440003A8801003A8837E01701C0DF170000DF53
+:101450000402C0DE3A2800F804FFFFDE150000DFBA
+:101460003A8839D8155920D0055720D0054B20D0BF
+:10147000055120D0454B20D0154F20D0154C20D001
+:101480003A8801003A8837E0170000DF0401C0DE27
+:101490003A2800F804FDFFDE150200DF040200DF39
+:1014A000055520D04455A0D015FEBFE0C5FF3FE054
+:1014B0000607000017FEBFE04400C01015FEFFE065
+:1014C00005000010C3FFBFE044008010C5FFBFE06F
+:1014D000C3FFBFE0F00080101EF63F10454D20D046
+:1014E000054D20D0155320D0155820D03A88010042
+:1014F0003A8837E0170000DF0401C0DE3A2800F820
+:1015000004F8FFDE1507C0DF150600DF040600DF64
+:10151000C4008000150480D8150300D80480800022
+:10152000150280D8B401820004EBAF10150180D8F9
+:10153000D4FFBF00150080D80405C001B4018201AA
+:1015400004EAB1313A880B0074000201041A062142
+:10155000C0641680C4FFBFE03A880D103401420118
+:10156000040D5E290405000140D616803A8801006A
+:101570003A8837E01701C0DF170000DF0402C0DE41
+:101580003A2800F804FBFFDE1504C0DF150300DF76
+:10159000040300DF04A24001B401020104BB3421B2
+:1015A000005B118004154001B4010201045D352186
+:1015B000005B1180B401820004BBB41015FEBFE0D3
+:1015C000B401820004D6B41015FDBFE0C5FF3FE0B2
+:1015D0000611000017FEBFE017FDFFE01505C01063
+:1015E00017FEBFE0C40FC0000513C01017FEBFE018
+:1015F0004513001017FEBFE0041B801015FEBFE06E
+:1016000017FDBFE0041B801015FDBFE0C3FFBFE066
+:1016100044008010C5FFBFE0C3FFBFE07001801031
+:101620001EEC3F1017FEBFE01505001017FEBFE0CF
+:10163000C40FC0000513C01017FEBFE04513001013
+:10164000154E20D0B401820004BBB4101550A0D0B8
+:101650003A8801003A8837E01701C0DF170000DF41
+:101660000402C0DE3A2800F804FDFFDE150200DFA8
+:10167000040200DF15FF3FE13A8805280DFEBFE0B8
+:101680000607000017FFBFE04400C01015FFFFE091
+:10169000050000100BFEBFE0C4FFBF100DFEBFE051
+:1016A0000BFEBFE01EF73F103A8801003A8837E092
+:1016B000170000DF0401C0DE3A2800F804FCFFDE5A
+:1016C000150300DF040300DF15FF3FE115FE7FE196
+:1016D0003A8805300DFDBFE0060B000017FEFFE065
+:1016E0004400801815FEBFE017FFBFE04400001162
+:1016F00015FF3FE10300C0180500C0100BFDBFE05F
+:10170000C4FFBF100DFDBFE00BFDBFE01EF33F1097
+:101710003A8801003A8837E0170000DF0401C0DE94
+:101720003A2800F804FBFFDE1504C0DF150300DFD4
+:10173000040300DF15FF3FE03A30050015FEBFE06F
+:1017400017FEFFE084FFBF003A7084183A70011062
+:1017500017FEBFE015FFBFE00357A0D0CC3F8010BD
+:101760001E180010034BA0D0CC3F80101E15001097
+:1017700040731180034DE0D0434DA0D0CC3FC01842
+:10178000CC3F8010260F8018034DA0D0CC3F801096
+:10179000BA900610B40182003A888518175DB5101A
+:1017A0001553A0D01753A0D0170EC0104400C01876
+:1017B000150EC010174FA0D044008010154FA0D0B8
+:1017C0008038388017FFBFE015FDBFE017FDBFE090
+:1017D0003A7001103A8801003A8837E01701C0DFFB
+:1017E000170000DF0402C0DE3A2800F804FEFFDE26
+:1017F000150100DF040100DF0355A0D0CC3FC0106D
+:10180000340182003A88851803CD9D10C5FFBFE0E2
+:10181000C3FFBFE0FA9004103A880910C3FFFFE04D
+:101820004455A0D03A88851803008010CC3FC010E2
+:10183000340182003A88851803CD9D103A888520AE
+:10184000054DA0D03A8801003A8837E0170000DF44
+:101850000401C0DE3A2800F804FCFFDE150300DFB7
+:10186000040300DF15FE3FE115FD7FE1C5FF3FE00A
+:10187000060B000017FDFFE04400801815FDBFE0D7
+:1018800017FEBFE04400001115FE3FE10300C01841
+:101890000500C010C3FFBFE044008010C5FFBFE0DB
+:1018A00017FDBFE003008010CC3F80101EF13F10F9
+:1018B00017FEBFE005000010C3FFBFE03A8837E025
+:1018C000170000DF0401C0DE3A2800F804FDFFDE47
+:1018D000150200DF040200DF15FE3FE1C5FF3FE017
+:1018E0000606000017FEBFE04400801015FEBFE0B2
+:1018F000C3FFBFE044008010C5FFBFE017FEBFE09C
+:1019000003008010CC3F80101EF63F10C3FFBFE0E5
+:101910003A8837E0170000DF0401C0DE3A2800F8FB
+:1019200004FAFFDE1505C0DF150400DF040400DF44
+:1019300015FC3FE115FF3FE03A30050015FDBFE023
+:1019400017FDFFE084FFBF003A7084183A70011061
+:1019500017FDBFE015FFBFE0174CA0D0440080107A
+:10196000154CA0D017FFBFE015FEBFE017FEBFE08B
+:101970003A7001108069388006EF3F0004F2FFDE04
+:10198000150DC0DF150C00DF040C00DF3A880720BE
+:1019900015F77FE115F6BFE13A880938170480E0B2
+:1019A00005F8FFE03A8807200DF5FFE00DF4BFE0F1
+:1019B00015FF3FE03A30050015FDBFE017FDFFE0E1
+:1019C00084FFBF003A7084183A70011017FDBFE021
+:1019D00015FFBFE01750A0D015FEBFE017FEBFE017
+:1019E0002691001017FEBFE0170580101550A0D0FB
+:1019F00017FFBFE015FBBFE017FBBFE03A70011017
+:101A000017FEBFE017F7FFE01500C01017FEBFE09C
+:101A100003F8FFE0850CC01017FEBFE0050C0010B6
+:101A200017FEBFE0450C001017FEBFE08D0B001045
+:101A300017FEBFE01703C0E01501C01017FEBFE09E
+:101A40001702C0E01503C01017FEBFE017F6FFE055
+:101A50001502C01017FEBFE00BF4FFE00D04C0102C
+:101A600017FEBFE00BF5FFE08D04C01017FEBFE0CE
+:101A7000C50D001003F8BFE0FAD004103A88071033
+:101A800017FEBFE0050DC01003F8BFE0CC018010C9
+:101A90003A88071017FEBFE0C50CC01017FEBFE064
+:101AA000030D8010CC3F80104400C0003A98841889
+:101AB0003A88071017FEBFE0850DC01017FEBFE083
+:101AC000C30C8010CC3F80104400C0003A988418AA
+:101AD0003A88071017FEBFE0450DC01017FEBFE0A3
+:101AE0001507001017FEBFE01508001017FEBFE035
+:101AF000150A001017FEBFE01509001017FEBFE021
+:101B0000150E001017FEBFE01510001017FEBFE005
+:101B1000150F001017FEBFE01511001017FEBFE0F3
+:101B20001512001017FEBFE0C40FC0000513C0104F
+:101B300017FEBFE04513001017FE3FE1806B3880B1
+:101B400017FE3FE1405A38803A30050015FCBFE0EF
+:101B500017FCFFE084FFBF003A7084183A70011050
+:101B600017FCBFE015FFBFE003F8BFE0BA90081014
+:101B700017FEFFE0B40182003A888520155DF5105C
+:101B8000174EE0D017FEBFE01505C01017FEBFE0EE
+:101B900015060010174EA0D026030010174EA0D037
+:101BA00017FEFFE01506C01017FEBFE0154EA0D0CF
+:101BB00017FEBFE0830DC0100355A0D03AB08418C3
+:101BC0000555A0D017FEBFE0030D8010CC3FC0101C
+:101BD0004455A0D03A8885180300001117FEBFE0D5
+:101BE000430D801017FEFFE0030DC018CC3FC01856
+:101BF0003AB084203A8809104455A0D03A88851814
+:101C0000050000110351A0D0440080100551A0D060
+:101C100017FFBFE015FABFE017FABFE03A700110F6
+:101C20003A8805000605000017FFBFE015F9BFE080
+:101C300017F9BFE03A700110841080003A8837E04D
+:101C40001701C0DF170000DF0402C0DE3A2800F8E9
+:101C500004F2FFDE150D00DF040D00DF15F63FE195
+:101C60003A8805283A88073015F3FFE10DF5BFE003
+:101C70003A88051805F4BFE015FE3FE017F6BFE00F
+:101C800003008010CC3F8010600180101E05001002
+:101C900017F3BFE04400C0000500C0103A880500FB
+:101CA000069F000003F4FFE004E0BF003A708418D0
+:101CB000C5FDBFE0C3FDBFE02606001003F4BFE092
+:101CC000CC1F801005F4BFE04400800045FFBFE05A
+:101CD0000601000045FF3FE017F3BFE005000010DC
+:101CE0003A30050015FCBFE017FCFFE084FFBF00A1
+:101CF0003A7084183A70011017FCBFE015FEBFE07F
+:101D000003F4BFE06000C0101E5F00188800C01020
+:101D10001E020018263F001006770000A000C01029
+:101D20001E030018E00080101E1E00100672000046
+:101D300017F6BFE00B0280100BF5FFE03A70841835
+:101D40008DFFBFE08BFFFFE00BF5BFE01E0D80189D
+:101D500043FFBFE0580080101E0D001017F6BFE0D3
+:101D60000B0280103A8807108BFFBFE03A308400E6
+:101D70003A7084183A88071017F6BFE00D02C010B9
+:101D80000603000017F3BFE0041CC0000500C010EC
+:101D900017FEBFE015FBBFE017FBBFE03A70011074
+:101DA000065E000017F6BFE00B0280100BF5FFE0A7
+:101DB0003A7084188DFFBFE08BFFBFE0260D001046
+:101DC00043FFBFE0580080101E0D001017F6BFE063
+:101DD0000B0280103A8807108BFFBFE03A30840076
+:101DE0003A7084183A88071017F6BFE00D02C01049
+:101DF0000603000017F3BFE0041CC0000500C0107C
+:101E000017FEBFE015FABFE017FABFE03A70011005
+:101E10000642000017F6BFE00B0280103A30840043
+:101E20003A8807100BF5BFE03A7084188DFFBFE0C9
+:101E30008BFFFFE00BF5BFE01E0B801843FFBFE0F8
+:101E4000580080101E0B001017F6BFE00B02801028
+:101E50008BFFFFE03AB084183A88071017F6BFE00E
+:101E60000D02C0100603000017F3BFE0041CC00001
+:101E70000500C01017FEBFE015F9BFE017F9BFE07D
+:101E80003A7001100625000017F6BFE00B02801023
+:101E90003A3084003A8807100BF5BFE03A70841896
+:101EA0008DFFBFE08BFFBFE0260B001043FFBFE0BC
+:101EB000580080101E0B001017F6BFE00B028010B8
+:101EC0008BFFFFE03AB084183A88071017F6BFE09E
+:101ED0000D02C0100603000017F3BFE0041CC00091
+:101EE0000500C01017FEBFE015F8BFE017F8BFE00F
+:101EF0003A7001100609000017FEBFE015F7BFE0B9
+:101F000017F7BFE03A7001108DFF3FE017F3BFE015
+:101F1000C41BC0000500C0103A8801008BFFBFE061
+:101F20003A8837E0170000DF0401C0DE3A2800F8E5
+:101F300004F8FFDE150700DF040700DF3A880520FC
+:101F400015F97FE10DFABFE015FF3FE00357A0D080
+:101F5000CC3F80102605001017F9BFE00404C00034
+:101F60000500C0103A880500062B00003A30050035
+:101F700015FDBFE017FDFFE084FFBF003A70841835
+:101F80003A70011017FDBFE015FFBFE0175AA0D04F
+:101F900015FEBFE017FEBFE026170010175AA0D0AD
+:101FA00017018010155AA0D017FEBFE04401C000F1
+:101FB0000500C01017FEBFE00BFAFFE00D02C010D5
+:101FC00017FEBFE01501001017FEBFE0C40FC000F0
+:101FD0008502C01017FEBFE0C502001017FFBFE06A
+:101FE00015FCBFE017FCBFE03A70011017F9BFE025
+:101FF000050000100607000017FFBFE015FBBFE05B
+:1020000017FBBFE03A70011017F9BFE0841CC00055
+:102010000500C01017FEBFE03A8837E0170000DF68
+:102020000401C0DE3A2800F804F2FFDE150DC0DF1F
+:10203000150C00DF040C00DF15F63FE13A88052897
+:1020400015F4BFE105F5BFE015FC3FE00357A0D054
+:10205000CC3F80102605001017F4BFE0C403C00079
+:102060000500C01017F6BFE00671000017F6BFE0CC
+:1020700003008010CC3F8010600180101E0500100E
+:1020800017F4BFE04400C0000500C01017F6BFE021
+:10209000066700003A30050015FBBFE017FBFFE0C4
+:1020A00084FFBF003A7084183A70011017FBBFE03C
+:1020B00015FCBFE017F6BFE01701801026030010E3
+:1020C00044008000C5FFBFE006010000C5FF3FE0FF
+:1020D00003F5BFE026030010600080101E230010EF
+:1020E00006480000C3FFBFE01E16001017F6BFE051
+:1020F000C40FC0008502C01017F6BFE0C502001073
+:1021000017F6BFE005000010175AE0D017F6BFE041
+:102110001501C01017F6BFE00D02001017F6BFE062
+:10212000155AA0D017FCBFE015FABFE017FABFE0C0
+:102130003A70011017F4BFE00500001015FD3FE0F4
+:10214000063A000017FCBFE015F9BFE017F9BFE041
+:102150003A70011017F4BFE04412C0000500C0102F
+:1021600017F6BFE015FDBFE00630000017F6BFE030
+:102170001701801015FEBFE0060600003A880B002C
+:1021800017FE3FE180FB128017FEBFE017008010B2
+:1021900015FEBFE017FEBFE01EF83F1017F6BFE0C8
+:1021A000C40FC0008502C01017F6BFE0C5020010C2
+:1021B00017F6BFE005000010175AE0D017F6BFE091
+:1021C0001501C01017F6BFE00D02001017F6BFE0B2
+:1021D000155AA0D017FCBFE015F8BFE017F8BFE014
+:1021E0003A700110C3FFBFE0580080101E010010BC
+:1021F000C066118017F4BFE00500001015FD3FE038
+:10220000060A000017FCBFE015F7BFE017F7BFE0B4
+:102210003A70011017F4BFE0C401C0000500C010FF
+:1022200017F6BFE015FDBFE03A88010017FDBFE0DB
+:102230003A8837E01701C0DF170000DF0402C0DE74
+:102240003A2800F804F6FFDE1509C0DF150800DFA4
+:10225000040800DF15FA3FE115F97FE115F8BFE149
+:1022600015FF3FE00357A0D0CC3F8010260500109B
+:1022700017F8BFE04404C0000500C0103A8805000C
+:10228000062300003A30050015FDBFE017FDFFE012
+:1022900084FFBF003A7084183A70011017FDBFE048
+:1022A00015FFBFE017FABFE003008010CC3F80109D
+:1022B000600180101E09001017FFBFE015FCBFE091
+:1022C00017FCBFE03A70011017F8BFE04400C000EF
+:1022D0000500C0103A880500060D000017FABFE09F
+:1022E000840280103A880B1017F93FE1007A1180C0
+:1022F000C5FEBFE017FFBFE015FBBFE017FBBFE067
+:102300003A70011017F8BFE005000010C3FEBFE0EF
+:102310003A8837E01701C0DF170000DF0402C0DE93
+:102320003A2800F804F5FFDE150AC0DF150900DFC2
+:10233000040900DF15F93FE115F87FE115F7BFE16A
+:1023400015FF3FE00357A0D0CC3F801026040010BB
+:1023500017F7BFE08404C0000500C010062F00007E
+:102360003A30050015FDBFE017FDFFE084FFBF0018
+:102370003A7084183A70011017FDBFE015FFBFE0F6
+:1023800017F9BFE003008010CC3F8010600180107F
+:102390001E08001017FFBFE015FCBFE017FCBFE0F0
+:1023A0003A70011017F7BFE04400C0000500C010EC
+:1023B000061A000017F83FE140811180C5FEBFE01A
+:1023C000C3FEBFE0300880101E08001017FFBFE0FA
+:1023D00015FBBFE017FBBFE03A70011017F7BFE035
+:1023E000C41CC0000500C010060C000017F9BFE0B7
+:1023F0008402801017F87FE13A880910007A118072
+:1024000017FFBFE015FABFE017FABFE03A700110FE
+:1024100017F7BFE0050000103A8801003A8837E05E
+:102420001701C0DF170000DF0402C0DE3A2800F801
+:1024300004E2FFDE151DC0DF151C00DF041C00DFF9
+:1024400015E83FE13A8805283A8809303A88073884
+:102450000DE7BFE03A88052005E6BFE03A88051899
+:102460000DE5BFE015FE3FE00357A0D0CC3F801044
+:1024700026050010170280E08400C0000500C0108F
+:102480003A880500064B0100034BA0D0CC3F8010DA
+:1024900026050010170280E04403C0000500C010AC
+:1024A0003A8805000643010017E8BFE003008010EA
+:1024B000CC3F8010600180101E050010170280E0E4
+:1024C0004400C0000500C0103A880500063901002C
+:1024D00003E6FFE004E0BF003A708418C5FDBFE0EA
+:1024E000C3FDBFE02606001003E6BFE0CC1F80104E
+:1024F00005E6BFE044008000C5FFBFE00601000024
+:10250000C5FF3FE03A30050015FBBFE017FBFFE0D9
+:1025100084FFBF003A7084183A70011017FBBFE0C7
+:1025200015FEBFE003E6BFE06000C0101E92001879
+:102530008800C0101E0200182661001006BB0000B3
+:10254000A000C0101E030018E00080101E2F001015
+:1025500006B6000017E8BFE00B0280100BE7FFE0B3
+:102560003A7084180DFDBFE00BFDFFE00BE7BFE004
+:102570001E178018C3FFBFE0580080101E0900100E
+:1025800017E8BFE00B0280103A8807100BFDBFE090
+:102590003A3084003A7084183A88071017E8BFE090
+:1025A0000D02C0101758A0D00BFDFFE00D0BC0109E
+:1025B00017FEBFE015FABFE017FABFE03A7001104E
+:1025C000170280E0050000100BFDBFE006F90000D7
+:1025D0000BE73FE103E67FE10BE5BFE004E9FFE045
+:1025E000150080D83A880F283A880D203A880B18B1
+:1025F00017E83FE140D7128017FEBFE015F9BFE0B2
+:1026000017F9BFE03A7001100692000017E8BFE02A
+:102610000B0280100BE7FFE03A7084180DFDBFE05D
+:102620000BFDBFE026170010C3FFBFE0580080106D
+:102630001E09001017E8BFE00B0280103A8807104F
+:102640000BFDBFE03A3084003A7084183A880710D6
+:1026500017E8BFE00D02C0101758A0D00BFDFFE037
+:102660000D0BC01017FEBFE015F8BFE017F8BFE074
+:102670003A700110170280E0050000100BFDBFE06A
+:1026800006CC00000BE73FE103E67FE10BE5BFE08E
+:1026900004E9FFE0150080D83A880F283A880D2019
+:1026A0003A880B1817E83FE140D7128017FEBFE0C9
+:1026B00015F7BFE017F7BFE03A700110066500009C
+:1026C00017E8BFE00B0280103A3084003A88071008
+:1026D0000BE7BFE03A7084180DFDBFE00BFDFFE093
+:1026E0000BE7BFE01E158018C3FFBFE05800801045
+:1026F0001E07001017E8BFE00B0280100BFDFFE083
+:102700003AB084183A88071017E8BFE00D02C010ED
+:102710001758A0D00BFDFFE00D0BC01017FEBFE057
+:1027200015F6BFE017F6BFE03A700110170280E01F
+:10273000050000100BFDBFE0069E00000BE73FE127
+:1027400003E67FE10BE5BFE004E9FFE0150080D878
+:102750003A880F283A880D203A880B1817E83FE18D
+:1027600040D7128017FEBFE015F5BFE017F5BFE0B8
+:102770003A7001100637000017E8BFE00B02801026
+:102780003A3084003A8807100BE7BFE03A708418AB
+:102790000DFDBFE00BFDBFE026150010C3FFBFE03D
+:1027A000580080101E07001017E8BFE00B028010D1
+:1027B0000BFDFFE03AB084183A88071017E8BFE035
+:1027C0000D02C0101758A0D00BFDFFE00D0BC0107C
+:1027D00017FEBFE015F4BFE017F4BFE03A70011038
+:1027E000170280E0050000100BFDBFE0067100003D
+:1027F0000BE73FE103E67FE10BE5BFE004E9FFE023
+:10280000150080D83A880F283A880D203A880B188E
+:1028100017E83FE140D7128017FEBFE015F3BFE095
+:1028200017F3BFE03A700110060A000017FEBFE080
+:1028300015F2BFE017F2BFE03A7001100DFD3FE066
+:10284000170280E0C41BC0000500C0100BFDBFE0F4
+:1028500006580000C06611803A30050015F1BFE04F
+:1028600017F1FFE084FFBF003A7084183A7001103E
+:1028700017F1BFE015FEBFE01758A0D0430C801041
+:10288000CC3F8010261C00101758A0D0430C80109D
+:10289000C5FCBFE01758A0D0450C001004E9BFE00C
+:1028A0003A880910C00A13801758A0D0050C0010F0
+:1028B00017FEBFE015F0BFE017F0BFE03A7001105F
+:1028C0000DFD3FE0C3FCBFE0980080101E04001027
+:1028D000170280E08403C0000500C0100604000059
+:1028E000170280E08402C0000500C0103A88010091
+:1028F0000BFDBFE0062F00001758A0D00B0B801077
+:102900000DFDBFE0C3FFBFE0580080101E21001086
+:1029100003E6BFE0161600109000C0101E0C001851
+:10292000080180101E12001017E8BFE00B02801093
+:102930003A8807100BFDBFE03A3084003A708418E3
+:102940003A88071017E8BFE00D02C0100612000019
+:1029500017E8BFE00B0280100BFDFFE03AB08418CF
+:102960003A88071017E8BFE00D02C010060A000001
+:1029700017FEBFE015EFBFE017EFBFE03A700110A0
+:10298000170280E0C41BC0000500C0103A88050093
+:10299000060800003A88010017FEBFE015EEBFE010
+:1029A00017EEBFE03A700110170280E0050000103A
+:1029B0000BFDBFE03A8837E01701C0DF170000DFEA
+:1029C0000402C0DE3A2800F804FBFFDE150400DF35
+:1029D000040400DF15FF3FE03A30050015FCBFE0BE
+:1029E00017FCFFE084FFBF003A7084183A700110B2
+:1029F00017FCBFE015FFBFE01758A0D00B0B8010ED
+:102A00008DFEBFE017FFBFE015FDBFE017FDBFE083
+:102A10003A7001108BFEBFE03A8837E0170000DF04
+:102A20000401C0DE3A2800F804EFFFDE1510C0DF15
+:102A3000150F00DF040F00DF15F43FE13A88052889
+:102A40003A88073015F1FFE10DF3BFE03A88051829
+:102A500005F2BFE015FD3FE017F4BFE00300801072
+:102A6000CC3F8010600180101E05001017F1BFE000
+:102A70004400C0000500C0103A88050006C00000F0
+:102A80003A30050015FABFE017FAFFE084FFBF00F7
+:102A90003A7084183A70011017FABFE015FDBFE0D4
+:102AA00003F2BFE026030010600080101E0B001030
+:102AB0000612000017F4BFE00B0280103A880710DE
+:102AC0000BF3BFE03A3084003A7084183A8807105C
+:102AD00017F4BFE00D02C0100611000017F4BFE0AC
+:102AE0000B0280100BF3FFE03AB084183A8807100D
+:102AF00017F4BFE00D02C0100609000017FDBFE08B
+:102B000015F9BFE017F9BFE03A70011017F1BFE007
+:102B1000441CC0000500C0103A880500069800005B
+:102B2000C5FE3FE017F4BFE01701801015FFBFE0BE
+:102B30000677000017FFBFE083048010CC3F8010B1
+:102B40006000C0101E4A00188800C0101E02001845
+:102B5000262F0010065B0000A000C0101E03001806
+:102B6000E00080101E1700100656000017F4BFE0AA
+:102B70000B02C01017FFBFE00B0480103A708418DE
+:102B80008DFCBFE017FFBFE00B0480108BFCFFE063
+:102B9000CCFFBF101E5480188BFCBFE03A880B108E
+:102BA00017FF3FE180FB128045FCBFE043FCBFE024
+:102BB000580080101E4C001044008000C5FEBFE08D
+:102BC0000649000017F4BFE00B02C01017FFBFE07A
+:102BD0000B0480103A7084188DFCBFE08BFCBFE0C2
+:102BE000264300108BFCBFE03A880B1017FF3FE133
+:102BF00080FB128045FCBFE043FCBFE05800801022
+:102C00001E3B001044008000C5FEBFE006380000F7
+:102C100017F4BFE00B0280103A3084003A880710A6
+:102C200017FFBFE00B0480103A7084188DFCBFE0E2
+:102C300017FFBFE00B0480108BFCFFE0CCFFBF1040
+:102C40001E2D80188BFCBFE03A880B1017FF3FE168
+:102C500080FB128045FCBFE043FCBFE058008010C1
+:102C60001E25001044008000C5FEBFE006220000C3
+:102C700017F4BFE00B0280103A3084003A88071046
+:102C800017FFBFE00B0480103A7084188DFCBFE082
+:102C90008BFCBFE0261A00108BFCBFE03A880B10BB
+:102CA00017FF3FE180FB128045FCBFE043FCBFE023
+:102CB000580080101E12001044008000C5FEBFE0C6
+:102CC000060F000017FDBFE015F8BFE017F8BFE0E2
+:102CD0003A70011017F1BFE0C41BC0000500C0101E
+:102CE0003A880500062600003A8801000605000023
+:102CF0003A880100060300003A880100060100003E
+:102D00003A88010017FFBFE01700801015FFBFE0F1
+:102D100017FFBFE01E873F1017FDBFE015F7BFE0AC
+:102D200017F7BFE03A700110C3FEBFE058008010F3
+:102D30001E010010C06611803A30050015F5BFE095
+:102D400017F5FFE084FFBF003A7084183A70011055
+:102D500017F5BFE015FDBFE017F4BFE00B028010D0
+:102D60008DFBBFE017FDBFE015F6BFE017F6BFE033
+:102D70003A70011017F1BFE0050000108BFBBFE0B7
+:102D80003A8837E01701C0DF170000DF0402C0DE19
+:102D90003A2800F804F9FFDE150600DF040600DF1C
+:102DA00015FB3FE115FA7FE115FF3FE017FBBFE0A0
+:102DB00003008010CC3F8010600180101E050010C1
+:102DC00017FABFE04400C0000500C0103A880500B3
+:102DD000061200003A30050015FCBFE017FCFFE0CA
+:102DE00084FFBF003A7084183A70011017FCBFE0EE
+:102DF00015FFBFE017FBBFE00B0280108DFEBFE0A8
+:102E000017FFBFE015FDBFE017FDBFE03A700110EE
+:102E100017FABFE0050000108BFEBFE03A8837E0EC
+:102E2000170000DF0401C0DE3A2800F804F8FFDED6
+:102E3000150700DF040700DF15FD3FE115FC7FE10A
+:102E40003A8807303A880938170180E00DFBFFE027
+:102E50003A88072005FAFFE00DF9BFE01758A0D027
+:102E6000030CC0101758A0D01408C018050CC010CF
+:102E70001758A0D0450C00101758A0D00BF9FFE050
+:102E80008D0BC0101758A0D017FCFFE0150AC0101A
+:102E900017FCBFE00BFBFFE00D04C01017FCBFE008
+:102EA00003FAFFE08504C0101758E0D017FCBFE01C
+:102EB0001502C01017FDBFE01701C01017FCBFE0DE
+:102EC0001500C01017FCBFE01501001017FCBFE093
+:102ED00017FDFFE01503C01017FDBFE017018010BC
+:102EE00015FFBFE017FFBFE02603001017FFBFE08C
+:102EF00017FCFFE01501C01017FDBFE017FCFFE055
+:102F00001501C0101758A0D0030D8010C5FEBFE0FA
+:102F1000C3FEFFE04455A0D03A8885180300801016
+:102F20003A8807101758A0D0430D80103A3084001B
+:102F30003A708418C3FEFFE03A8809104455A0D0C7
+:102F40003A88851805000011C3FEFFE04455A0D063
+:102F50003A88851803008010CC3F80101E070010AF
+:102F60001758A0D0830D80103A3084003A8807109B
+:102F70000355A0D03A7084180555A0D03A880100B6
+:102F80003A8837E0170000DF0401C0DE3A2800F875
+:102F900004FBFFDE1504C0DF150300DF040300DFC0
+:102FA00004DC4001B4010201048B2B21005B118081
+:102FB000B4018200048BAB1015FEBFE0B4018200A7
+:102FC0000496AB1015FDBFE08DFF3FE00613000037
+:102FD00017FEBFE00500001017FEBFE017FDFFE081
+:102FE0001501C01017FEBFE0C40FC0008502C0105D
+:102FF00017FEBFE0C502001017FEBFE0040B8010F3
+:1030000015FEBFE017FDBFE0040B801015FDBFE00B
+:103010008BFFBFE0440080108DFFBFE08BFFBFE05F
+:10302000F00480101EEA3F1017FEBFE005000010FC
+:1030300017FEBFE01501001017FEBFE0C40FC0006F
+:103040008502C01017FEBFE0C5020010B401820067
+:10305000048BAB10155AA0D03A8801003A8837E0AB
+:103060001701C0DF170000DF0402C0DE3A2800F8B5
+:1030700004FAFFDE1505C0DF150400DF040400DFDD
+:1030800015FD3FE13A8805280DFCBFE017FDBFE0C4
+:103090001702801015FEBFE017FEBFE08D0B001079
+:1030A00017FEBFE00BFCFFE00D0BC01017FEBFE0EA
+:1030B000030CC010C4F7BF003A7084183A88071098
+:1030C00017FEBFE0050CC01017FEBFE0450C001056
+:1030D00017FEBFE0030C8010CC3F80101E180010BC
+:1030E00017FEBFE0830DC0100355A0D03AB084187E
+:1030F0000555A0D017FEBFE0030D8010CC3FC010D7
+:103100004455A0D03A8885180300001117FEBFE08F
+:10311000430D801017FEFFE0030DC018CC3FC01810
+:103120003AB084203A8809104455A0D03A888518CE
+:103130000500001144008000C5FFBFE0060100004B
+:10314000C5FF3FE017FD3FE1C00A1380C3FFBFE0AA
+:103150003A8837E01701C0DF170000DF0402C0DE45
+:103160003A2800F804FAFFDE150500DF040500DF49
+:1031700015FB3FE117FBBFE01701801015FFBFE013
+:1031800017FBBFE01700801015FEBFE017FFBFE080
+:103190001E0B001017FBBFE01703801015FDBFE0EA
+:1031A00017FDBFE017FEFFE01501C01017FEBFE0DE
+:1031B000260B001017FEBFE01501001006080000E6
+:1031C00017FFBFE017FEFFE01500C01017FEBFE0BD
+:1031D0002603001017FEBFE017FFFFE01501C01027
+:1031E00017FBBFE01702801015FCBFE017FCBFE023
+:1031F000150A00103A8801003A8837E0170000DF0E
+:103200000401C0DE3A2800F804F4FFDE150B00DFED
+:10321000040B00DF15F83FE115F77FE115F6BFE17C
+:1032200015F5FFE115FC3FE03A30050015FABFE067
+:1032300017FAFFE084FFBF003A7084183A7001105B
+:1032400017FABFE015FCBFE01752A0D015FBBFE096
+:103250001752A0D0260300101752A0D017018010DB
+:103260001552A0D017FCBFE015F9BFE017F9BFE079
+:103270003A70011017FBBFE01E05001017F5BFE004
+:103280008416C0000500C0103A880500062C000016
+:1032900017F8BFE015FEBFE017F8FFE017F6BFE034
+:1032A0003A88851815FFBFE015FD3FE0060C0000C9
+:1032B00017FEBFE017FFFFE01500C01017FFBFE0CB
+:1032C00015FEBFE017FFFFE017F6BFE03A8885184C
+:1032D00015FFBFE017FDBFE04400801015FDBFE003
+:1032E00017F7BFE0C4FFBF1017FDFFE036F0BF18AF
+:1032F00017FEBFE01500001017FBBFE017F8FFE056
+:103300001500C01017FBBFE017F8FFE01501C01053
+:1033100017FBBFE017F7FFE01504C01017FBBFE075
+:1033200017F7FFE01503C01017FBBFE017F6FFE02B
+:103330001502C01017F5BFE00500001017FBBFE035
+:103340003A8837E0170000DF0401C0DE3A2800F8B1
+:1033500004F8FFDE150700DF040700DF15FA3FE180
+:1033600015F97FE115FF3FE03A30050015FDBFE09C
+:1033700017FDFFE084FFBF003A7084183A70011017
+:1033800017FDBFE015FFBFE017FABFE0170480107C
+:103390002614001017FABFE01701801015FEBFE0D9
+:1033A00017FEBFE01700C01017FABFE01501C010EC
+:1033B00017FABFE017048010C4FFFF1017FABFE030
+:1033C0001504C01017FFBFE015FCBFE017FCBFE0FD
+:1033D0003A70011017F9BFE00500001017FEBFE0BA
+:1033E0000608000017FFBFE015FBBFE017FBBFE0BA
+:1033F0003A70011017F9BFE04417C0000500C01073
+:103400003A8805003A8837E0170000DF0401C0DE83
+:103410003A2800F804F7FFDE1508C0DF150700DFC3
+:10342000040700DF15FB3FE115FA7FE115F9BFE165
+:1034300015FF3FE00357A0D0CC3F801026050010B9
+:1034400017F9BFE04404C0000500C0103A88050029
+:10345000061500003A30050015FCBFE017FCFFE040
+:1034600084FFBF003A7084183A70011017FCBFE067
+:1034700015FFBFE017FBBFE0040580103A880B1072
+:1034800017FA3FE1007A1180C5FEBFE017FFBFE0E9
+:1034900015FDBFE017FDBFE03A70011017F9BFE05E
+:1034A00005000010C3FEBFE03A8837E01701C0DF17
+:1034B000170000DF0402C0DE3A2800F804F6FFDE41
+:1034C0001509C0DF150800DF040800DF15FA3FE129
+:1034D00015F97FE115F8BFE115FF3FE00357A0D0D4
+:1034E000CC3F80102604001017F8BFE08404C00011
+:1034F0000500C010062100003A30050015FDBFE0B0
+:1035000017FDFFE084FFBF003A7084183A70011085
+:1035100017FDBFE015FFBFE017F93FE140811180C3
+:10352000C5FEBFE0C3FEBFE0300880101E080010DB
+:1035300017FFBFE015FCBFE017FCBFE03A700110B9
+:1035400017F8BFE0C418C0000500C010060B00004B
+:1035500017FABFE00405801017F97FE13A880910D7
+:10356000007A118017FFBFE015FBBFE017FBBFE03B
+:103570003A70011017F8BFE0050000103A8837E0F4
+:103580001701C0DF170000DF0402C0DE3A2800F890
+:1035900004F9FFDE150600DF040600DF15FB3FE13E
+:1035A00015FA7FE115FF3FE03A30050015FEBFE058
+:1035B00017FEFFE084FFBF003A7084183A700110D4
+:1035C00017FEBFE015FFBFE017FBBFE01704C010F8
+:1035D00017FBBFE0170380103606801817FFBFE007
+:1035E00015FDBFE017FDBFE03A70011084178000A1
+:1035F0000611000017FBBFE01701C01017FABFE06B
+:103600001500C01017FBBFE017FAFFE01501C0104E
+:1036100017FBBFE0170480104400C01017FBBFE089
+:103620001504C01017FFBFE015FCBFE017FCBFE09A
+:103630003A7001103A8805003A8837E0170000DF39
+:103640000401C0DE3A2800F804FAFFDE150500DFA9
+:10365000040500DF15FC3FE115FB7FE115FF3FE0AE
+:103660003A30050015FDBFE017FDFFE084FFBF0005
+:103670003A7084183A70011017FDBFE015FFBFE0E3
+:1036800017FCBFE01700C01017FBBFE01500C0100B
+:1036900017FCBFE01701C01017FBBFE01501C010F9
+:1036A00017FCBFE01702C01017FBBFE01502C010E7
+:1036B00017FCBFE01703C01017FBBFE01503C010D5
+:1036C00017FCBFE01704C01017FBBFE01504C010C3
+:1036D00017FFBFE015FEBFE017FEBFE03A70011014
+:1036E00017FBBFE01703C01017FBBFE017048010E3
+:1036F0003AC8871817FBBFE01505C0103A880500C7
+:103700003A8837E0170000DF0401C0DE3A2800F8ED
+:1037100004FCFFDE1503C0DF150200DF040200DF3A
+:10372000040C4301B401020104672C21005B1180E9
+:10373000B40182000467AC1015FFBFE08DFE3FE0CE
+:10374000061300008BFEBFE044008010240DC01063
+:10375000B40182000467AC103A88871817FFBFE0F5
+:103760001501C01017FFBFE0C40FC0000505C01051
+:1037700017FFBFE04505001017FFBFE0040D8010E4
+:1037800015FFBFE08BFEBFE0440080108DFEBFE060
+:103790008BFEBFE0F00E80101EEA3F1017FFBFE067
+:1037A0001501001017FFBFE0C40FC0000505C010D1
+:1037B00017FFBFE045050010B40182000467AC109C
+:1037C0001552A0D03A8801003A8837E01701C0DFCF
+:1037D000170000DF0402C0DE3A2800F804F7FFDE1D
+:1037E000150800DF040800DF15F93FE115F87FE157
+:1037F00015FF3FE017F9BFE003008010CC3F8010B9
+:10380000200180101E05001017F8BFE04400C00022
+:103810000500C0103A880500064A00000357A0D0F2
+:10382000CC3F80102605001017F8BFE08400C000D0
+:103830000500C0103A880500064200003A30050035
+:1038400015FDBFE017FDFFE084FFBF003A7084184C
+:103850003A70011017FDBFE015FFBFE017F9BFE098
+:103860000B028010CCFFBF103AD20410C5FEBFE09F
+:1038700017F9BFE00B028010CCFFBF10CC3F8010C7
+:10388000D83F80101E28001017F9BFE00B02C010AF
+:1038900004C0BF003A7084183A88071017F9BFE0D7
+:1038A0000D02C01017F9BFE00B02C0101758A0D0CE
+:1038B000830C8010CC3F80103AB084183A880710EF
+:1038C00017F9BFE00D02C0101758E0D017F9BFE09C
+:1038D0001501C0101758A0D0830C8010C3FEFFE064
+:1038E000CC3F80103608801817FFBFE015FCBFE002
+:1038F00017FCBFE03A70011017F8BFE0041EC000CB
+:103900000500C0100606000017FFBFE015FBBFE072
+:1039100017FBBFE03A70011017F8BFE00500001078
+:10392000440080000607000017FFBFE015FABFE063
+:1039300017FABFE03A70011017F8BFE00500001059
+:103940003A8805003A8837E0170000DF0401C0DE3E
+:103950003A2800F804F6FFDE1509C0DF150800DF7D
+:10396000040800DF3A88052015F87FE105F9BFE07B
+:1039700015FF3FE00357A0D0CC3F80102605001074
+:1039800017F8BFE00404C0000500C0103A88050025
+:10399000064B00003A30050015FDBFE017FDFFE0C3
+:1039A00084FFBF003A7084183A70011017FDBFE021
+:1039B00015FFBFE003F9BFE0BA900610B401820022
+:1039C0003A888518175DB5102609001017FFBFE06B
+:1039D00015FCBFE017FCBFE03A70011017F8BFE01C
+:1039E000040AC0000500C0103A8805000634000033
+:1039F00003F9BFE0BA9008104400C000B40182008F
+:103A00003A888520155DF5101756A0D015FEBFE049
+:103A100017FEBFE01E0E001003F9BFE0BA900610BB
+:103A2000B40182003A888518155D351017FFBFE094
+:103A300015FBBFE017FBBFE03A70011017F8BFE0BD
+:103A40000401C0000500C01017FEBFE0061C000006
+:103A50001756A0D0170180101556A0D017FFBFE051
+:103A600015FABFE017FABFE03A70011017FEBFE089
+:103A70000401C0000500C01003F9BFE03A92041031
+:103A8000D43F80103A88071017FEBFE00D02C01027
+:103A900017FEBFE01501001017FEBFE0C40FC00005
+:103AA0008503C01017FEBFE0C503001017FE3FE1FD
+:103AB0008025118017F8BFE00500001017FEBFE059
+:103AC0003A8837E01701C0DF170000DF0402C0DECC
+:103AD0003A2800F804F1FFDE150EC0DF150D00DFF7
+:103AE000040D00DF15F53FE13A88052815F3BFE125
+:103AF00005F4BFE015FD3FE017F5BFE003008010BF
+:103B0000CC3F8010200180101E05001017F3BFE08D
+:103B10004400C0000500C01017F5BFE00698000083
+:103B20000357A0D0CC3F80102605001017F3BFE04C
+:103B3000C403C0000500C01017F5BFE006900000E8
+:103B40003A30050015FABFE017FAFFE084FFBF0026
+:103B50003A7084183A70011017FABFE015FDBFE003
+:103B600017F5BFE083028010CC3F801026030010C1
+:103B700044008000C5FFBFE006010000C5FF3FE034
+:103B800003F4BFE026030010600080101E2D00101B
+:103B900006700000C3FFBFE01E20001017F5BFE055
+:103BA000C40FC0008503C01017F5BFE0C5030010A7
+:103BB00017F5BFE00B028010CCFFBF103AD2041003
+:103BC000C5FCBFE0C3FCBFE0BA900610B4018200A0
+:103BD0003A888518155D351017F5BFE0050000100F
+:103BE0001756E0D017F5BFE01501C01017F5BFE07C
+:103BF0000D02001017F5BFE01556A0D017FDBFE06D
+:103C000015F9BFE017F9BFE03A70011017F3BFE0F4
+:103C10000500001015FE3FE00658000017FDBFE04C
+:103C200015F8BFE017F8BFE03A70011017F3BFE0D6
+:103C30004412C0000500C01017F5BFE015FEBFE03C
+:103C4000064E000017F5BFE00B028010CCFFBF103E
+:103C50003AD20410C5FCBFE017F5BFE00B0280109C
+:103C600085FCBFE017F5BFE01701801015FBBFE032
+:103C700017FBBFE0260F001017FBBFE0830C80107E
+:103C8000C3FCFFE0CC3F80101E0A801883FCBFE01D
+:103C90003A880B1017FB3FE1C0571480060500005F
+:103CA0003A880F00040480013A880B0017F53FE1C1
+:103CB00080CD108017F5BFE083028010CC3F8010CC
+:103CC0001EF73F1017F5BFE0C40FC0008503C010FA
+:103CD00017F5BFE0C503001017F5BFE00B02801019
+:103CE000CCFFBF103AD20410C5FCBFE0C3FCBFE05C
+:103CF000BA900610B40182003A888518155D351017
+:103D000017F5BFE0050000101756E0D017F5BFE02B
+:103D10001501C01017F5BFE00D02001017F5BFE048
+:103D20001556A0D017FDBFE015F7BFE017F7BFE0AD
+:103D30003A700110C3FFBFE0580080101E01001050
+:103D4000C066118017F3BFE00500001015FE3FE0CC
+:103D5000060A000017FDBFE015F6BFE017F6BFE04A
+:103D60003A70011017F3BFE0C401C0000500C01095
+:103D700017F5BFE015FEBFE03A88010017FEBFE06F
+:103D80003A8837E01701C0DF170000DF0402C0DE09
+:103D90003A2800F804EFFFDE1510C0DF150F00DF32
+:103DA000040F00DF15F33FE13A88052815F1BFE164
+:103DB0000DF2BFE015FE3FE017F3BFE003008010F7
+:103DC000CC3F8010200180101E04001017F1BFE0CE
+:103DD0004400C0000500C010064001000357A0D0F9
+:103DE000CC3F80102604001017F1BFE08400C00013
+:103DF0000500C01006390100034BA0D0CC3F801055
+:103E00002604001017F1BFE04403C0000500C010F5
+:103E1000063201003A30050015F9BFE017F9FFE05E
+:103E200084FFBF003A7084183A70011017F9BFE0A0
+:103E300015FEBFE017F3BFE00B028010CCFFBF10F0
+:103E40003AD20410C5FDBFE017F3BFE00B028010AB
+:103E5000CC3F8010D83F80101E27001017F3BFE022
+:103E60000B02C01004C0BF003A7084183A880710D3
+:103E700017F3BFE00D02C01017F3BFE00B02C01034
+:103E80001758A0D0830C8010CC3F80103AB0841813
+:103E90003A88071017F3BFE00D02C0101758E0D0A2
+:103EA00017F3BFE01501C0101758A0D0830C801085
+:103EB000C3FDFFE0CC3F80103608801817FEBFE03E
+:103EC00015F8BFE017F8BFE03A70011017F1BFE036
+:103ED000041EC0000500C0100600010017FEBFE070
+:103EE00015F7BFE017F7BFE03A70011017F1BFE018
+:103EF0000500001006F9000017F3BFE00B02801068
+:103F000085FDBFE017F3BFE01701801015FCBFE08F
+:103F100017FCBFE0830C8010C3FDFFE0CC3F801096
+:103F20002EB380181758A0D0830CC01083FDBFE0BB
+:103F3000CC3FC0182EAE801817FCBFE0030D8010D8
+:103F4000C5FBBFE0C3FBFFE04455A0D03A8885180D
+:103F50000300C01017FCBFE0430D80103A708418B6
+:103F6000CC3F8010261E0010C3FBFFE04455A0D0BC
+:103F70003A888518030080103A88071017FCBFE0C4
+:103F8000430D80103A3084003A708418C3FBFFE080
+:103F90003A8809104455A0D03A88851805000011C8
+:103FA000C3FBFFE04455A0D03A8885180300801079
+:103FB000CC3F80101E07001017FCBFE0830D80105F
+:103FC0003A3084003A8807100355A0D03A7084181C
+:103FD0000555A0D044008000C5FFBFE006280000C2
+:103FE00017FCBFE01707801015FABFE017FABFE013
+:103FF0002622001017FCBFE0030D8010CC3F80107C
+:1040000017FAFFE03A888518C30280103A88071033
+:1040100017FCBFE0430D80103A3084003A708418DA
+:104020003A88071017FCBFE0030D8010CC3F8010CA
+:104030003A88091817FAFFE03A888718C50200196C
+:1040400017FAFFE03A888518C3028010CC3F801031
+:104050001E0A001017FABFE0830280103A8807108A
+:1040600017FCBFE0830D80103A3084003A7084184A
+:104070003A88071017FABFE08502C010C5FF3FE07D
+:1040800017FCBFE0C3FDFFE0850CC01017FCBFE0CC
+:10409000830C8010CC3F8010FAD004103A880710AF
+:1040A00017FCBFE0050DC01017FCBFE0830C8010AB
+:1040B000CC0180103A88071017FCBFE0C50CC01077
+:1040C00017FCBFE0030D8010CC3F80104400C000FF
+:1040D0003A9884183A88071017FCBFE0850DC01085
+:1040E00017FCBFE0C30C8010CC3F80104400C00020
+:1040F0003A9884183A88071017FCBFE0450DC010A5
+:10410000C3FFBFE0580080101E16001017FCBFE070
+:10411000830DC0100355A0D03AB084180555A0D027
+:1041200017FCBFE0030D8010CC3FC0104455A0D059
+:104130003A8885180300001117FCBFE0430D80107A
+:1041400017FCFFE0030DC018CC3FC0183AB0842024
+:104150003A8809104455A0D03A8885180500001106
+:10416000061D000017FCBFE01707801015FABFE01E
+:1041700017FABFE02618001017FABFE08302C0103C
+:1041800017FCBFE0830D80103AB084183A880710FE
+:1041900017FABFE08502C01017FCBFE0030D8010C6
+:1041A000CC3F801017FAFFE03A888518C30200114F
+:1041B00017FCBFE0430DC01017FCBFE0030D8010DB
+:1041C000CC3F80103AB0C6203A88091817FAFFE0B1
+:1041D0003A888518C5020011C3FDBFE0BA900810E7
+:1041E00017FCFFE0B40182003A888520155DF510C8
+:1041F0001758A0D0030CC0101758A0D01404C01832
+:10420000050CC0101758A0D0450C00101758A0D0AE
+:104210000BF2FFE08D0BC01017F33FE100E61080BA
+:1042200017FEBFE015F5BFE017F5BFE03A700110CB
+:10423000C06611803A30050015F6BFE017F6FFE0C2
+:1042400084FFBF003A7084183A70011017F6BFE07F
+:1042500015FEBFE01758A0D0430C8010CC3F801053
+:1042600026030010A00080101E04001006070000A6
+:1042700017F1BFE005000010060C000017F1BFE0C9
+:104280008403C0000500C010060800001758A0D025
+:1042900017F37FE13A880910000B118017F1BFE096
+:1042A0008402C0000500C0103A8801001758A0D051
+:1042B000050C00101758A0D0450C00101758A0D0BE
+:1042C000150700101758A0D01508001017FEBFE002
+:1042D00015F4BFE017F4BFE03A7001103A8837E0F8
+:1042E0001701C0DF170000DF0402C0DE3A2800F823
+:1042F00004F6FFDE1509C0DF150800DF040800DF43
+:1043000015F83FE115FF3FE00357A0D0CC3F8010E8
+:104310002602001044018000066E000017F8BFE07E
+:1043200003008010CC3F8010200180101E0200107E
+:1043300044008000066700003A30050015FDBFE02C
+:1043400017FDFFE084FFBF003A7084183A70011037
+:1043500017FDBFE015FFBFE017F8BFE00B028010AC
+:10436000CCFFBF103AD20410C5FEBFE017F8BFE083
+:104370000B02801085FEBFE017F8BFE01701C010E8
+:104380001758A0D02606801817FFBFE015FCBFE025
+:1043900017FCBFE03A70011004198000064D0000C0
+:1043A0001758A0D0830C8010C3FEFFE0CC3F8010D4
+:1043B0001E0580181758A0D083FEFFE03A880B181E
+:1043C0003A880910C0571480C3FEBFE0BA900810A5
+:1043D0004400C000B40182003A888520155DF510C4
+:1043E00017F8BFE083028010CC3F8010262C00100D
+:1043F0003A880F00040480013A880B0017F83FE167
+:1044000080CD108085FEBFE017F8BFE00B02C01022
+:1044100004C0BF003A7084183A88071017F8BFE04C
+:104420000D02C01017F8BFE00B02C01083FEBFE002
+:104430003AB084183A88071017F8BFE00D02C01090
+:1044400083FEBFE0BA900610B40182003A88851856
+:10445000175DF51017F8BFE01501C01083FEBFE02F
+:10446000C3FEFFE03607801817FFBFE015FBBFE073
+:1044700017FBBFE03A700110C0661180041E800077
+:104480000614000017FFBFE015FABFE017FABFE0FF
+:104490003A700110C06611803A880500060D0000D0
+:1044A00017F8BFE00B028010D43F80103A88071045
+:1044B00017F8BFE00D02C01017F8BFE0150100109B
+:1044C00017FFBFE015F9BFE017F9BFE03A70011020
+:1044D0003A8805003A8837E01701C0DF170000DF8F
+:1044E0000402C0DE3A2800F804F7FFDE150800DFFA
+:1044F000040800DF15F93FE115F87FE115FC3FE006
+:104500000357A0D0CC3F8010260200108401800009
+:104510000644000017F9BFE003008010CC3F801074
+:10452000200180101E02001044008000063D0000A3
+:104530003A30050015FBBFE017FBFFE084FFBF002A
+:104540003A7084183A70011017FBBFE015FCBFE009
+:1045500017F9BFE00B028010CCFFBF103AD2041055
+:104560003A88071017F8BFE08501C01017F9BFE0BF
+:104570000B0280103A88071017F8BFE04501C01001
+:1045800017F8BFE043018010CC3F8010D83F801067
+:104590001E04001017F8BFE04400C0000501C01061
+:1045A0000602000017F8BFE00501001017F9BFE090
+:1045B0008302C01017F8BFE0C500C01017F9BFE0B4
+:1045C000C402801015FEBFE017F8BFE015FDBFE084
+:1045D000C5FF3FE0060B000017FEFFE04400801817
+:1045E00015FEBFE017FDBFE04400001115FD3FE1DF
+:1045F0000300C0180500C010C3FFBFE044008010D6
+:10460000C5FFBFE0C3FFBFE0F00080101EF23F1007
+:1046100017FCBFE015FABFE017FABFE03A700110CF
+:104620003A8805003A8837E0170000DF0401C0DE51
+:104630003A2800F804FCFFDE150300DF040300DF66
+:1046400015FE3FE13A88052805FDBFE017FEBFE0F3
+:10465000030D8010C5FFBFE0C3FFFFE04455A0D0AD
+:104660003A888518030080103A88071017FEBFE0CB
+:10467000430D80103A3084003A708418C3FFFFE085
+:104680003A8809104455A0D03A88851805000011D1
+:10469000C3FFFFE04455A0D03A888518030080107E
+:1046A000CC3F80101E07001017FEBFE0830D801066
+:1046B0003A3084003A8807100355A0D03A70841825
+:1046C0000555A0D017FEBFE003FDFFE0850CC0102C
+:1046D00003FDBFE0FAD00410CC0180103A88071027
+:1046E00017FEBFE0050DC01003FDBFE0CC01801038
+:1046F0003A88071017FEBFE0C50CC01017FEBFE0D8
+:10470000030D8010CC3F80104400C0003A988418FC
+:104710003A88071017FEBFE0850DC01017FEBFE0F6
+:10472000C30C8010CC3F80104400C0003A9884181D
+:104730003A88071017FEBFE0450DC01017FEBFE016
+:10474000830DC0100355A0D03AB084180555A0D0F1
+:1047500017FEBFE0030D8010CC3FC0104455A0D021
+:104760003A8885180300001117FEBFE0430D801042
+:1047700017FEFFE0030DC018CC3FC0183AB08420EC
+:104780003A8809104455A0D03A88851805000011D0
+:1047900003FDBFE0BA90081017FEFFE0B4018200ED
+:1047A0003A888520155DF5103A8801003A8837E08F
+:1047B000170000DF0401C0DE3A2800F804F8FFDE2D
+:1047C000150700DF040700DF15FA3FE115F97FE167
+:1047D00015FE3FE017FABFE003008010CC3F8010C9
+:1047E000A00080101E05001017F9BFE04400C000B3
+:1047F0000500C0103A880500063100003A30050077
+:1048000015FCBFE017FCFFE084FFBF003A7084187E
+:104810003A70011017FCBFE015FEBFE017FABFE0C9
+:104820001701801015FDBFE017FDBFE08B0580105C
+:10483000CCFFBF102619001017FDBFE01704801031
+:104840000401001117FDFFE0150400191700801086
+:1048500015FFBFE017FDBFE08B058010C4FFBF1040
+:104860003A88071017FDBFE08D05C01017FDBFE0A7
+:104870001704C01017FDBFE0170280101E04801837
+:1048800017FDBFE01701C01017FDBFE01504C010F1
+:1048900017F9BFE0050000100604000017F9BFE09B
+:1048A000C407C0000500C01015FF3FE017FEBFE0C1
+:1048B00015FBBFE017FBBFE03A70011017FFBFE028
+:1048C0003A8837E0170000DF0401C0DE3A2800F81C
+:1048D00004F4FFDE150BC0DF150A00DF040A00DF59
+:1048E00015F73FE13A8805280DF6BFE015FE3FE0D9
+:1048F0000357A0D0CC3F8010260200103A88050054
+:10490000065700003A30050015FCBFE017FCFFE039
+:1049100084FFBF003A7084183A70011017FCBFE0A2
+:1049200015FEBFE01756A0D015FFBFE01756A0D068
+:10493000260300101756A0D0170180101556A0D0DE
+:1049400017FEBFE015FBBFE017FBBFE03A70011098
+:1049500017FFBFE0264100103A30050015FABFE00E
+:1049600017FAFFE084FFBF003A7084183A70011014
+:1049700017FABFE015FEBFE01754A0D015FDBFE049
+:1049800017FDBFE0262B00101754A0D01700801091
+:104990001554A0D017FEBFE015F9BFE017F9BFE02E
+:1049A0003A70011017FDBFE017F7FFE01501C010C6
+:1049B0000BF6BFE0BA90041017F7FFE03A888718AB
+:1049C00017FDBFE01502C01017FDBFE017F7FFE0AD
+:1049D0001503C01017FDBFE017F7FFE01504C01066
+:1049E00017FDBFE00BF6FFE00D05C01017FDBFE09F
+:1049F0008D05001017FFBFE08400C0000500C01047
+:104A000017FFBFE00D02001017FFBFE017FDFFE02A
+:104A10001501C01017FFBFE0C40FC0008503C01010
+:104A200017FFBFE0C503001017FF3FE1802511808D
+:104A3000060A00001756E0D017FFBFE01501C010AE
+:104A400017FFBFE01556A0D017FEBFE015F8BFE076
+:104A500017F8BFE03A70011015FF3FE017FFBFE005
+:104A60003A8837E01701C0DF170000DF0402C0DE1C
+:104A70003A2800F804F2FFDE150DC0DF150C00DF48
+:104A8000040C00DF15F63FE13A88052815F4BFE174
+:104A900005F5BFE015FD3FE017F6BFE0030080100D
+:104AA000CC3F8010A00080101E05001017F4BFE05E
+:104AB0004400C0000500C01017F6BFE0067D0000EE
+:104AC0000357A0D0CC3F80102605001017F4BFE09C
+:104AD000C403C0000500C01017F6BFE00675000053
+:104AE0003A30050015FBBFE017FBFFE084FFBF0075
+:104AF0003A7084183A70011017FBBFE015FDBFE053
+:104B000017F6BFE083028010CC3F80102603001010
+:104B100044008000C5FFBFE006010000C5FF3FE084
+:104B200003F5BFE026030010600080101E30001067
+:104B300006550000C3FFBFE01E1E001017F6BFE0C1
+:104B4000C40FC0008503C01017F6BFE0C5030010F6
+:104B500017F6BFE01701801015FCBFE01754E0D036
+:104B600017FCBFE01500C01017FCBFE01554A0D023
+:104B700017F6BFE0050000101756E0D017F6BFE0AB
+:104B80001501C01017F6BFE00D02001017F6BFE0C8
+:104B90001556A0D017FDBFE015FABFE017FABFE029
+:104BA0003A70011017F4BFE00500001015FE3FE059
+:104BB000063F000017FDBFE015F9BFE017F9BFE0A1
+:104BC0003A70011017F4BFE04412C0000500C01095
+:104BD00017F6BFE015FEBFE0063500003A880F006B
+:104BE000040180013A880B0017F63FE180CD108068
+:104BF00017F6BFE083028010CC3F80101EF73F10F5
+:104C000017F6BFE0C40FC0008503C01017F6BFE061
+:104C1000C503001017F6BFE01701801015FCBFE0B8
+:104C20001754E0D017FCBFE01500C01017FCBFE020
+:104C30001554A0D017F6BFE0050000101756E0D0BD
+:104C400017F6BFE01501C01017F6BFE00D02001007
+:104C500017F6BFE01556A0D017FDBFE015F8BFE06E
+:104C600017F8BFE03A700110C3FFBFE05800801092
+:104C70001E010010C066118017F4BFE0050000108F
+:104C800015FE3FE0060A000017FDBFE015F7BFE084
+:104C900017F7BFE03A70011017F4BFE0C401C0007D
+:104CA0000500C01017F6BFE015FEBFE03A8801000E
+:104CB00017FEBFE03A8837E01701C0DF170000DFBA
+:104CC0000402C0DE3A2800F804FAFFDE150500DF12
+:104CD000040500DF15FB3FE115FF3FE03A3005001A
+:104CE00015FCBFE017FCFFE084FFBF003A7084189A
+:104CF0003A70011017FCBFE015FFBFE017FBBFE0E3
+:104D00001701801015FEBFE017FEBFE01701C010AD
+:104D100017FEBFE01503C01017FEBFE01701C0105B
+:104D200017FEBFE01504C01017FEBFE08D05001090
+:104D300017FFBFE015FDBFE017FDBFE03A7001109F
+:104D40003A8805003A8837E0170000DF0401C0DE2A
+:104D50003A2800F804F3FFDE150CC0DF150B00DF66
+:104D6000040B00DF15F73FE13A88052815F5BFE190
+:104D70000DF6BFE015FE3FE017F7BFE0030080101F
+:104D8000CC3F8010A00080101E05001017F5BFE07A
+:104D90004400C0000500C0103A88050006800000ED
+:104DA0000357A0D0CC3F80102605001017F5BFE0B8
+:104DB0008400C0000500C0103A8805000678000095
+:104DC000034BA0D0CC3F80102605001017F5BFE0A4
+:104DD0004403C0000500C0103A88050006700000BA
+:104DE0003A30050015FCBFE017FCFFE084FFBF0070
+:104DF0003A7084183A70011017FCBFE015FEBFE04E
+:104E000017F7BFE01701801015FDBFE017FDBFE0E9
+:104E10008B058010CCFFBF10261E001017FDBFE0D1
+:104E2000170480100401001117FDFFE0150400199C
+:104E30001700801015FFBFE017FDBFE08B05801045
+:104E4000C4FFBF103A88071017FDBFE08D05C010E2
+:104E500017FDBFE01704C01017FDBFE01702801058
+:104E60001E04801817FDBFE01701C01017FDBFE03A
+:104E70001504C01017FEBFE015FBBFE017FBBFE035
+:104E80003A70011017F5BFE00500001017FFBFE0F2
+:104E9000064300001758A0D0030CC0101758A0D02C
+:104EA0001401C018050CC0101758A0D0450C0010F4
+:104EB0001758A0D00BF6FFE08D0BC01017F73FE19D
+:104EC00000E6108017FEBFE015F9BFE017F9BFE05C
+:104ED0003A700110C06611803A30050015FABFE043
+:104EE00017FAFFE084FFBF003A7084183A7001108F
+:104EF00017FABFE015FEBFE01758A0D0430C801092
+:104F0000CC3F801026030010A00080101E07001068
+:104F1000060B00001758A0D01709801015FFBFE03E
+:104F200017F5BFE005000010060E000015FF3FE07A
+:104F300017F5BFE08403C0000500C010060900009B
+:104F40001758A0D017F77FE13A880910000B11809D
+:104F500015FF3FE017F5BFE08402C0000500C01058
+:104F60003A8801001758A0D0050C00101758A0D09F
+:104F7000450C00101758A0D0150700101758A0D0E6
+:104F8000150800101758A0D01509001017FEBFE033
+:104F900015F8BFE017F8BFE03A70011017FFBFE047
+:104FA0003A8837E01701C0DF170000DF0402C0DED7
+:104FB0003A2800F804F6FFDE1509C0DF150800DF07
+:104FC000040800DF15FA3FE13A88052815F8BFE12B
+:104FD00005F9BFE015FE3FE017FABFE003008010BF
+:104FE000CC3F8010A00080101E05001017F8BFE015
+:104FF0004400C0000500C0103A88050006380000D3
+:105000003A30050015FDBFE017FDFFE084FFBF004B
+:105010003A7084183A70011017FDBFE015FEBFE02A
+:1050200017FABFE083028010CC3F801026250010C5
+:10503000C5FF3FE003F9BFE0580080101E0E0010CE
+:10504000060800008400C001040180013A880B00BA
+:1050500017FA3FE180CD1080C3FFBFE0440080100D
+:10506000C5FFBFE017FABFE083028010CC3F80107D
+:105070001EF43F10060900008400C00104018001F5
+:105080003A880B0017FA3FE180CD1080C3FFBFE0E4
+:1050900044008010C5FFBFE03A88010017FEBFE062
+:1050A00015FCBFE017FCBFE03A700110C06611802C
+:1050B00017F8BFE08403C0000500C010C3FFBFE0C5
+:1050C0000607000017FEBFE015FBBFE017FBBFE0BF
+:1050D0003A70011017F8BFE0050000103A8805008B
+:1050E0003A8837E01701C0DF170000DF0402C0DE96
+:1050F0003A2800F804F6FFDE1509C0DF150800DFC6
+:10510000040800DF15F93FE115F87FE115FF3FE0E6
+:1051100017F9BFE003008010CC3F8010A000801082
+:105120001E02001044008000064300003A300500D3
+:1051300015FDBFE017FDFFE084FFBF003A70841843
+:105140003A70011017FDBFE015FFBFE017F9BFE08F
+:1051500083028010CC3F8010260C00103A880F008C
+:105160000401800117F87FE117F93FE180CD10803D
+:1051700017FFBFE015FCBFE017FCBFE03A7001105D
+:10518000C06611803A880500062B000017F9BFE0C1
+:105190001701801015FEBFE017FEBFE08B05C010A1
+:1051A00017FEBFE00B058010CCFFFF18CCFFBF102F
+:1051B0003606801817FFBFE015FBBFE017FBBFE006
+:1051C0003A70011084078000061B000017FEBFE044
+:1051D000170380100401001117FEFFE015030019EA
+:1051E00017F8FFE01500C01017FEBFE08B05801018
+:1051F000440080103A88071017FEBFE08D05C010EC
+:1052000017FEBFE01703C01017FEBFE017028010A3
+:105210001E04801817FEBFE01701C01017FEBFE084
+:105220001503C01017FFBFE015FABFE017FABFE083
+:105230003A7001103A8805003A8837E01701C0DF5C
+:10524000170000DF0402C0DE3A2800F804F6FFDE93
+:105250001509C0DF150800DF040800DF15F93FE17C
+:1052600015F87FE115FF3FE017F9BFE0030080105C
+:10527000CC3F8010A00080101E020010440080006F
+:10528000064500003A30050015FDBFE017FDFFE0C0
+:1052900084FFBF003A7084183A70011017FDBFE018
+:1052A00015FFBFE017F9BFE083028010CC3F8010EC
+:1052B000260C00103A880F000401800117F87FE1E6
+:1052C00017F93FE180CD108017FFBFE015FCBFE06C
+:1052D00017FCBFE03A700110C06611803A880500E3
+:1052E000062D000017F9BFE01701801015FEBFE082
+:1052F00017FEBFE08B05C01017FEBFE00B05801046
+:10530000CCFFFF18CCFFBF103606801817FFBFE098
+:1053100015FBBFE017FBBFE03A7001108407800067
+:10532000061D000017FEBFE01704C01017FEBFE007
+:10533000170180101E04801817FEBFE01702C0106E
+:1053400017FEBFE01504C01017FEBFE01704801061
+:1053500004FFFF1017FEBFE01504C01017FEBFE0EA
+:105360001704801017F8FFE01500C01017FEBFE00B
+:105370008B058010440080103A88071017FEBFE0AC
+:105380008D05C01017FFBFE015FABFE017FABFE0A8
+:105390003A7001103A8805003A8837E01701C0DFFB
+:1053A000170000DF0402C0DE3A2800F804F5FFDE33
+:1053B000150AC0DF150900DF040900DF15F93FE118
+:1053C00015F87FE13A88053005F7BFE015FF3FE0AB
+:1053D00017F9BFE003008010CC3F8010A0008010C0
+:1053E0001E02001044008000066A00003A300500EA
+:1053F00015FDBFE017FDFFE084FFBF003A70841881
+:105400003A70011017FDBFE015FFBFE017F9BFE0CC
+:1054100083028010CC3F8010261D001003F7BFE0F0
+:105420004C008010260B0010060500003A880F0083
+:105430000401800117F87FE117F93FE180CD10806A
+:1054400017F9BFE083028010CC3F80101EF73F1099
+:10545000060500003A880F000401800117F87FE17B
+:1054600017F93FE180CD108017FFBFE015FCBFE0CA
+:1054700017FCBFE03A70011003F7BFE00C01801089
+:105480001E010010C06611803A8805000641000028
+:1054900017F9BFE01701801015FEBFE017FEBFE04F
+:1054A0008B05C01017FEBFE00B058010CCFFFF1866
+:1054B000CCFFBF103606801817FFBFE015FBBFE01A
+:1054C00017FBBFE03A70011084078000063100002E
+:1054D00003F7BFE08C0080102613001017FEBFE01A
+:1054E0001704C01017FEBFE0170180101E048018BB
+:1054F00017FEBFE01702C01017FEBFE01504C01072
+:1055000017FEBFE01704801004FFFF1017FEBFE076
+:105510001504C01017FEBFE01704801017F8FFE055
+:105520001500C0100610000017FEBFE01703801022
+:105530000401001117FEFFE01503001917F8FFE042
+:105540001500C01017FEBFE01703C01017FEBFE024
+:10555000170280101E04801817FEBFE01701C0104C
+:1055600017FEBFE01503C01017FEBFE08B058010CB
+:10557000440080103A88071017FEBFE08D05C01068
+:1055800017FFBFE015FABFE017FABFE03A7001104D
+:105590003A8805003A8837E01701C0DF170000DFBE
+:1055A0000402C0DE3A2800F804F6FFDE150900DF29
+:1055B000040900DF15F83FE115F77FE115FC3FE036
+:1055C00017F8BFE003008010CC3F8010A0008010CF
+:1055D0001E02001044008000063E00003A30050024
+:1055E00015FABFE017FAFFE084FFBF003A70841895
+:1055F0003A70011017FABFE015FCBFE017F8BFE0E2
+:105600008302C01017F7BFE0C502C01017F8BFE053
+:10561000C402801015FEBFE017F7BFE0040280103F
+:1056200015FDBFE0C5FF3FE0060B000017FEFFE0E1
+:105630004400801815FEBFE017FDBFE044000011D4
+:1056400015FD3FE10300C0180500C010C3FFBFE017
+:1056500044008010C5FFBFE0C3FFBFE0F000801032
+:105660001EF23F1017F8BFE01701801015FBBFE0D6
+:1056700017FBBFE08B058010CCFFBF102606001083
+:1056800017FBBFE0170480101700C01017F7BFE02A
+:105690001500C0100602000017F7BFE0150000104B
+:1056A00017FBBFE08B05C01017F7BFE00D01C0105E
+:1056B00017FBBFE00B05C01017F7BFE08D01C0104E
+:1056C00017FCBFE015F9BFE017F9BFE03A70011011
+:1056D0003A8805003A8837E0170000DF0401C0DE91
+:1056E0003A2800F804FBFFDE1504C0DF150300DFD5
+:1056F000040300DF04784001B401020104732F2188
+:10570000005B1180B40182000473AF1015FEBFE08E
+:10571000B40182000479AF1015FDBFE08DFF3FE0BA
+:10572000060C000017FEBFE017FDFFE01500C010DB
+:1057300017FEBFE00406801015FEBFE017FDBFE0B6
+:105740000406801015FDBFE08BFFBFE04400801011
+:105750008DFFBFE08BFFBFE0F00480101EF13F1013
+:1057600017FEBFE015000010B40182000473AF10F3
+:105770001554A0D03A8801003A8837E01701C0DFFD
+:10578000170000DF0402C0DE3A2800F804FAFFDE4A
+:10579000150500DF040500DF15FB3FE115FF3FE0C5
+:1057A00017FBBFE003008010CC3F8010E0008010AA
+:1057B0001E0200103A880500061800003A30050065
+:1057C00015FDBFE017FDFFE084FFBF003A708418AD
+:1057D0003A70011017FDBFE015FFBFE017FBBFE0F7
+:1057E0000B0280108DFEBFE08BFEBFE0260600108E
+:1057F00017FBBFE00B028010C4FFBF103A880710F0
+:1058000017FBBFE00D02C01017FFBFE015FCBFE0A3
+:1058100017FCBFE03A7001108BFEBFE03A8837E01A
+:10582000170000DF0401C0DE3A2800F804F9FFDEAB
+:105830001506C0DF150500DF040500DF3A880520E6
+:105840000DFBBFE015FF3FE00357A0D0CC3F801019
+:10585000260200103A880500062500003A300500AF
+:1058600015FDBFE017FDFFE084FFBF003A7084180C
+:105870003A70011017FDBFE015FFBFE01756A0D02A
+:1058800015FEBFE01756A0D0260300101756A0D073
+:10589000170180101556A0D017FFBFE015FCBFE020
+:1058A00017FCBFE03A70011017FEBFE0260F001092
+:1058B00017FEBFE0C400C0000500C01017FEBFE027
+:1058C0000BFBFFE00D02C01017FEBFE0150100103A
+:1058D00017FEBFE0C40FC0008503C01017FEBFE075
+:1058E000C503001017FE3FE18025118017FEBFE0C1
+:1058F0003A8837E01701C0DF170000DF0402C0DE7E
+:105900003A2800F804F3FFDE150CC0DF150B00DFAA
+:10591000040B00DF15F73FE13A88052815F5BFE1D4
+:1059200005F6BFE015FD3FE017F7BFE0030080106C
+:10593000CC3F8010E00080101E05001017F5BFE07E
+:105940004400C0000500C01017F7BFE0066D00005E
+:105950000357A0D0CC3F80102605001017F5BFE0FC
+:10596000C403C0000500C01017F7BFE006650000C3
+:105970003A30050015FCBFE017FCFFE084FFBF00D4
+:105980003A7084183A70011017FCBFE015FDBFE0B3
+:1059900017F7BFE083028010CC3F80102603001071
+:1059A00044008000C5FFBFE006010000C5FF3FE0E6
+:1059B00003F6BFE026030010600080101E280010D0
+:1059C00006450000C3FFBFE01E16001017F7BFE03A
+:1059D000C40FC0008503C01017F7BFE0C503001057
+:1059E00017F7BFE0050000101756E0D017F7BFE02B
+:1059F0001501C01017F7BFE00D02001017F7BFE048
+:105A00001556A0D017FDBFE015FBBFE017FBBFE0A8
+:105A10003A70011017F5BFE00500001015FE3FE0D9
+:105A20000637000017FDBFE015FABFE017FABFE028
+:105A30003A70011017F5BFE04412C0000500C01015
+:105A400017F7BFE015FEBFE0062D00003A880F00F3
+:105A5000440080013A880B0017F73FE180CD1080A9
+:105A600017F7BFE083028010CC3F80101EF73F1075
+:105A700017F7BFE0C40FC0008503C01017F7BFE0E1
+:105A8000C503001017F7BFE0050000101756E0D05F
+:105A900017F7BFE01501C01017F7BFE00D020010A7
+:105AA00017F7BFE01556A0D017FDBFE015F9BFE00E
+:105AB00017F9BFE03A700110C3FFBFE05800801033
+:105AC0001E010010C066118017F5BFE00500001030
+:105AD00015FE3FE0060A000017FDBFE015F8BFE025
+:105AE00017F8BFE03A70011017F5BFE0C401C0001D
+:105AF0000500C01017F7BFE015FEBFE03A880100AF
+:105B000017FEBFE03A8837E01701C0DF170000DF5B
+:105B10000402C0DE3A2800F804F5FFDE150AC0DFF3
+:105B2000150900DF040900DF15F93FE13A8805286F
+:105B300015F7BFE10DF8BFE015FF3FE017F9BFE033
+:105B400003008010CC3F8010E00080101E04001085
+:105B500017F7BFE04400C0000500C0100662000057
+:105B60000357A0D0CC3F80102604001017F7BFE0E9
+:105B70008400C0000500C010065B0000034BA0D0ED
+:105B8000CC3F80102604001017F7BFE04403C0008C
+:105B90000500C010065400003A30050015FEBFE0B5
+:105BA00017FEFFE084FFBF003A7084183A700110BE
+:105BB00017FEBFE015FFBFE017F9BFE00B02801032
+:105BC000CCFFBF10260D001017F9BFE00B028010AC
+:105BD000C4FFBF103A88071017F9BFE00D02C010CC
+:105BE00017FFBFE015FDBFE017FDBFE03A700110E1
+:105BF00017F7BFE005000010063B00001758A0D0C3
+:105C0000030CC0101758A0D05400C018050CC010C9
+:105C10001758A0D0450C00101758A0D00BF8FFE083
+:105C20008D0BC01017F93FE100E6108017FFBFE0B1
+:105C300015FBBFE017FBBFE03A700110C066118092
+:105C40003A30050015FCBFE017FCFFE084FFBF0001
+:105C50003A7084183A70011017FCBFE015FFBFE0DE
+:105C60001758A0D0430C8010CC3F801026030010A2
+:105C7000A00080101E0400100607000017F7BFE008
+:105C800005000010060C000017F7BFE08403C000F9
+:105C90000500C010060800001758A0D017F97FE1D2
+:105CA0003A880910000B118017F7BFE08402C0008A
+:105CB0000500C0103A8801001758A0D0050C00104C
+:105CC0001758A0D0450C00101758A0D01507001089
+:105CD0001758A0D01508001017FFBFE015FABFE055
+:105CE00017FABFE03A7001103A8837E01701C0DFB9
+:105CF000170000DF0402C0DE3A2800F804F6FFDED9
+:105D00001509C0DF150800DF040800DF15FA3FE1C0
+:105D10003A88052815F8BFE105F9BFE015FE3FE018
+:105D200017FABFE003008010CC3F8010E000801025
+:105D30001E05001017F8BFE04400C0000500C010A9
+:105D40003A880500063800003A30050015FDBFE02E
+:105D500017FDFFE084FFBF003A7084183A7001100D
+:105D600017FDBFE015FEBFE017FABFE08302801009
+:105D7000CC3F801026250010C5FF3FE003F9BFE0AF
+:105D8000580080101E0E0010060800008400C0019C
+:105D9000440080013A880B0017FA3FE180CD108063
+:105DA000C3FFBFE044008010C5FFBFE017FABFE0AB
+:105DB00083028010CC3F80101EF43F1006090000C3
+:105DC0008400C001440080013A880B0017FA3FE1CB
+:105DD00080CD1080C3FFBFE044008010C5FFBFE04E
+:105DE0003A88010017FEBFE015FCBFE017FCBFE0DA
+:105DF0003A700110C066118017F8BFE08403C0003C
+:105E00000500C010C3FFBFE00607000017FEBFE09B
+:105E100015FBBFE017FBBFE03A70011017F8BFE0B9
+:105E2000050000103A8805003A8837E01701C0DF06
+:105E3000170000DF0402C0DE3A2800F804F8FFDE95
+:105E40001507C0DF150600DF040600DF15FA3FE185
+:105E500015FF3FE017FABFE003008010CC3F801031
+:105E6000E00080101E02001044008000062E00009A
+:105E70003A30050015FEBFE017FEFFE084FFBF00CB
+:105E80003A7084183A70011017FEBFE015FFBFE0AA
+:105E900017FABFE083028010CC3F8010260C001060
+:105EA0003A880F00440080013A880B0017FA3FE15E
+:105EB00080CD108017FFBFE015FDBFE017FDBFE0EC
+:105EC0003A700110C06611803A880500061600007D
+:105ED00017FABFE00B028010CCFFFF10D4FFBF0009
+:105EE000260C801817FABFE00B02801044008010C7
+:105EF0003A88071017FABFE00D02C01017FFBFE085
+:105F000015FCBFE017FCBFE03A7001103A880500AD
+:105F10000605000017FFBFE015FBBFE017FBBFE061
+:105F20003A700110840C80003A8837E01701C0DF16
+:105F3000170000DF0402C0DE3A2800F804F7FFDE95
+:105F4000150800DF040800DF15F93FE115F87FE1CF
+:105F500015FC3FE017F9BFE003008010CC3F801034
+:105F6000E00080101E02001044008000062B00009C
+:105F70003A30050015FBBFE017FBFFE084FFBF00D0
+:105F80003A7084183A70011017FBBFE015FCBFE0AF
+:105F900017F9BFE08302C01017F8BFE04501C01039
+:105FA00017F9BFE0C402801015FFBFE017F8BFE08B
+:105FB0008400801015FEBFE0C5FD3FE0060B000029
+:105FC00017FFFFE04400801815FFBFE017FEBFE099
+:105FD0004400001115FE3FE10300C0180500C01089
+:105FE000C3FDBFE044008010C5FDBFE0C3FDBFE0BE
+:105FF000F00080101EF23F1017F9BFE00B02C01036
+:1060000017F8BFE00D00C01017FCBFE015FABFE0A5
+:1060100017FABFE03A7001103A8805003A8837E075
+:10602000170000DF0401C0DE3A2800F804F9FFDEA3
+:10603000150600DF040600DF15FC3FE13A8805285D
+:1060400015FABFE10DFBBFE015FF3FE017FCBFE015
+:1060500003008010CC3F8010E00080101E04001070
+:1060600017FABFE04400C0000500C0100621000080
+:106070003A30050015FEBFE017FEFFE084FFBF00C9
+:106080003A7084183A70011017FEBFE015FFBFE0A8
+:1060900017FABFE00500001017FCBFE00B028010EC
+:1060A000CCFFBF102604001017FCBFE00BFBFFE085
+:1060B0000D02C010060B000017FCBFE08302801029
+:1060C000CC3F80101E04001017FCBFE00BFBFFE06C
+:1060D0000D02C0100603000017FABFE04412C00012
+:1060E0000500C01017FFBFE015FDBFE017FDBFE0C2
+:1060F0003A7001103A8837E0170000DF0401C0DE73
+:106100003A2800F804F1FFDE150EC0DF150D00DFA0
+:10611000040D00DF3A8805203A88072805F4BFE01F
+:106120003A88051805F3BFE015FD3FE03A30050059
+:1061300015F9BFE017F9FFE084FFBF003A7084183B
+:106140003A70011017F9BFE015FDBFE003F3BFE09F
+:10615000BA900610B40182003A888518175DB51010
+:106160002606001017FDBFE015F8BFE017F8BFE0E6
+:106170003A700110040A800006FD000003F4BFE03D
+:10618000D83F80101E0300101758A0D0830C801039
+:1061900005F4BFE003F4BFE0BA900610B40182003A
+:1061A0003A888518175DB51015FCBFE017FCBFE0F5
+:1061B0001E06001017FDBFE015F7BFE017F7BFE0A0
+:1061C0003A700110440A800006E9000017FCBFE0A5
+:1061D000580080101E06001017FDBFE015F6BFE046
+:1061E00017F6BFE03A700110C410800006E000000E
+:1061F00003F3BFE0FAD00410C5FBBFE003F3BFE038
+:10620000CC01801085FBBFE0C3FBBFE04400C000B1
+:106210003A98841845FBBFE083FBBFE04400C00010
+:106220003A98841805FBBFE003F4BFE0BA9006106B
+:10623000B40182003A888518155D351003F3BFE07C
+:10624000BA90081017FCFFE0B40182003A8885205C
+:10625000155DF51017FCBFE0030D8010C5FABFE017
+:1062600017FCBFE0830D801085FABFE017FCBFE08C
+:10627000430D801045FABFE0C3FAFFE04455A0D0BB
+:106280003A8885180300801043FAFFE03A708418BA
+:10629000CC3F801026280010C3FAFFE04455A0D060
+:1062A0003A888518030080103A88071043FABFE047
+:1062B0003A3084003A708418C3FAFFE03A88091033
+:1062C0004455A0D03A88851805000011C3FAFFE0B4
+:1062D0004455A0D03A88851803008010CC3F801028
+:1062E0001E06001083FABFE03A3084003A88071097
+:1062F0000355A0D03A7084180555A0D00355A0D0FE
+:1063000043FBFFE03AB084180555A0D0C3FBFFE083
+:106310004455A0D03A88851803008010C3FBFFE0E5
+:1063200003FB3FE13AB084203A8809104455A0D0DD
+:106330003A8885180500001117FCBFE01707801088
+:1063400015FFBFE017FFBFE0262F0010C3FABFE024
+:1063500017FFFFE03A888518C30280103A880710BB
+:1063600043FABFE03A3084003A7084183A88071044
+:10637000C3FABFE03A88091817FFFFE03A8885188A
+:10638000C5020011C3FABFE017FFFFE03A88851885
+:10639000C3028010CC3F80101E09001017FFBFE021
+:1063A000830280103A88071083FABFE03A308400F5
+:1063B0003A7084183A88071017FFBFE08502C010B2
+:1063C00017FFBFE08302801043FBFFE03AB0841860
+:1063D0003A88071017FFBFE08502C010C3FBBFE07B
+:1063E00017FFFFE03A888518C302C010C3FBBFE067
+:1063F00003FB3FE13AB0C6203A88091817FFFFE0D7
+:106400003A888518C502001117FCBFE017088010F4
+:10641000263E001017FCBFE01708801015FEBFE0F5
+:1064200017FEBFE01700801015FFBFE00635000023
+:10643000C3FABFE017FFFFE03A888518C302801057
+:106440003A88071043FABFE03A3084003A70841863
+:106450003A880710C3FABFE03A88091817FFFFE02F
+:106460003A888518C5020011C3FABFE017FFFFE0A4
+:106470003A888518C3028010CC3F80101E09001096
+:1064800017FFBFE0830280103A88071083FABFE04D
+:106490003A3084003A7084183A88071017FFBFE03A
+:1064A0008502C01017FFBFE08302801043FBFFE0AE
+:1064B0003AB084183A88071017FFBFE08502C01071
+:1064C000C3FBBFE017FFFFE03A888518C302C01086
+:1064D000C3FBBFE003FB3FE13AB0C6203A8809188E
+:1064E00017FFFFE03A888518C502001117FEBFE0CC
+:1064F0000401801015FEBFE017FEBFE017008010FA
+:1065000015FFBFE017FFBFE01EC93F1017FCBFE03B
+:1065100003F3FFE0850CC01017FCBFE0C3FBFFE0F6
+:10652000050DC01017FCBFE083FBFFE0C50CC010D9
+:1065300017FCBFE043FBFFE0850DC01017FCBFE078
+:1065400003FBFFE0450DC01017FDBFE015F5BFE0F0
+:1065500017F5BFE03A700110434BA0D0CC3F80103C
+:10656000580080101E010010C06611803A88050096
+:106570003A8837E01701C0DF170000DF0402C0DEF1
+:106580003A2800F804EEFFDE1511C0DF151000DF19
+:10659000041000DF15F63FE115F57FE115F4BFE1CA
+:1065A0003A88053805F3BFE015FF3FE03A300500B3
+:1065B00015FCBFE017FCFFE084FFBF003A708418B1
+:1065C0003A70011017FCBFE015FFBFE00357A0D0E1
+:1065D000CC3F80102606001017FFBFE015FBBFE080
+:1065E00017FBBFE03A700110040F80000640000066
+:1065F00003F3BFE0BA900610B40182003A88851810
+:10660000175DB5101E35001003F3BFE0BA900810F7
+:106610004400C000B40182003A888520155DF51061
+:1066200017FFBFE015FABFE017FABFE03A7001109C
+:106630003A880F0017F4BFE117F57FE117F63FE145
+:106640008045388015FEBFE003F3BFE0150200D897
+:10665000150100D8150000D83A880F003A880D00BF
+:1066600017FE7FE13A880910408C1180C5FDBFE01C
+:10667000C3FDBFE01E060010434BA0D0CC3F8010EE
+:10668000580080101E130010C06611800611000013
+:106690003A30050015F8BFE017F8FFE084FFBF00AF
+:1066A0003A7084183A70011017F8BFE015FFBFE088
+:1066B00003F3BFE0BA900610B40182003A8885184F
+:1066C000155D351017FFBFE015F9BFE017F9BFE002
+:1066D0003A700110C3FDBFE00605000017FFBFE0E0
+:1066E00015F7BFE017F7BFE03A700110040A800009
+:1066F0003A8837E01701C0DF170000DF0402C0DE70
+:106700003A2800F804ECFFDE1513C0DF151200DF95
+:10671000041200DF15F63FE115F57FE115F4BFE146
+:106720003A8809381702C0E0170680E005F33FE118
+:106730000DF2FFE00DF1BFE015FF3FE03A3005003C
+:1067400015FCBFE017FCFFE084FFBF003A7084181F
+:106750003A70011017FCBFE015FFBFE00357A0D04F
+:10676000CC3F80102606001017FFBFE015FBBFE0EE
+:1067700017FBBFE03A700110040F800006450000CF
+:1067800003F3BFE0BA900610B40182003A8885187E
+:10679000175DB5101E3A001003F3BFE0BA90081061
+:1067A0004400C000B40182003A888520155DF510D0
+:1067B00017FFBFE015FABFE017FABFE03A7001100B
+:1067C0000BF1BFE03A880F1017F4BFE117F57FE136
+:1067D00017F63FE18045388015FEBFE003F3FFE088
+:1067E0000BF23FE10BF1BFE0150280D8170580E006
+:1067F000150180D8170480E0150080D83A880F2052
+:10680000170380E117FE7FE13A880918408C118058
+:10681000C5FDBFE0C3FDBFE01E060010434BA0D086
+:10682000CC3F8010580080101E130010C0661180ED
+:10683000061100003A30050015F8BFE017F8FFE038
+:1068400084FFBF003A7084183A70011017F8BFE057
+:1068500015FFBFE003F3BFE0BA900610B401820059
+:106860003A888518155D351017FFBFE015F9BFE0B0
+:1068700017F9BFE03A700110C3FDBFE00605000044
+:1068800017FFBFE015F7BFE017F7BFE03A70011040
+:10689000040A80003A8837E01701C0DF170000DFE4
+:1068A0000402C0DE3A2800F804F4FFDE150BC0DF56
+:1068B000150A00DF040A00DF3A88052005F6BFE06C
+:1068C00015FF3FE00357A0D0CC3F801026020010F8
+:1068D0000410800006B4000003F6BFE01805801025
+:1068E0001E020010840F800006AF00003A30050041
+:1068F00015FCBFE017FCFFE084FFBF003A7084186E
+:106900003A70011017FCBFE015FFBFE003F6BFE0CF
+:10691000D83F80101E0300101758A0D0830C8010A1
+:1069200005F6BFE003F6BFE0BA900610B40182009E
+:106930003A888518175DB51015FEBFE017FEBFE059
+:106940001E06001017FFBFE015FBBFE017FBBFE0FE
+:106950003A700110C41080000693000017FEBFE0DB
+:10696000580080101E06001017FFBFE015FABFE0A8
+:1069700017FABFE03A700110440F8000068A000049
+:1069800017FEBFE0030D8010CC3FC0104455A0D0CF
+:106990003A888518030080103A88071017FEBFE078
+:1069A000430D80103A3084003A7084183A880910F8
+:1069B00017FEBFE0030D8010CC3FC0104455A0D09F
+:1069C0003A8885180500001117FEBFE0030D8010FE
+:1069D000CC3FC0104455A0D03A88851803008010E1
+:1069E000CC3F80101E07001017FEBFE0830D801003
+:1069F0003A3084003A8807100355A0D03A708418C2
+:106A00000555A0D017FEBFE017078010260500101F
+:106A100017FEBFE0170780103A880B1017FE3FE102
+:106A2000000B118017FEBFE017088010260500102C
+:106A300017FEBFE0170880103A880B1017FE3FE1E1
+:106A40000016118017FEBFE0170A801015FDBFE089
+:106A500017FDBFE02602001017FD3FE1C00A1380BA
+:106A600017FEBFE08D0B001017FEBFE0050C0010F5
+:106A700017FEBFE0450C0010034BA0D0CC3F8010A8
+:106A8000E03F80101E030010034BA0D04400801094
+:106A9000054BA0D017FFBFE015F8BFE017F8BFE027
+:106AA0003A70011080CB10803A30050015F9BFE034
+:106AB00017F9FFE084FFBF003A7084183A700110A4
+:106AC00017F9BFE015FFBFE0034BA0D0CC3F80100B
+:106AD00026030010034BA0D0C4FFBF10054BA0D06D
+:106AE00017FE3FE1805C38800351A0D0C4FFBF1087
+:106AF0000551A0D003F6BFE0BA900610B4018200A1
+:106B00003A888518155D351017FEBFE0170680100E
+:106B10001E07001017FEBFE01705801015060010B5
+:106B200017FEBFE017058010154EA0D0060A000022
+:106B300017FEBFE01706801017FEFFE01705C0180C
+:106B40001505C01017FEBFE01705801017FEFFE007
+:106B50001706C0181506C0101750E0D017FEBFE08A
+:106B60001505C01017FEBFE01550A0D017FEBFE0FE
+:106B7000C40FC0000513C01017FEBFE0451300107E
+:106B800017FFBFE015F7BFE017F7BFE03A7001103D
+:106B9000434BA0D0CC3F8010580080101E01001045
+:106BA000C06611803A8805003A8837E01701C0DFD7
+:106BB000170000DF0402C0DE3A2800F804F5FFDE0B
+:106BC000150A00DF040A00DF3A88052005F6BFE059
+:106BD00015FF3FE003F6BFE0180580101E0200100D
+:106BE000840F8000063B000003F6BFE0D83F801012
+:106BF0001E1100103A30050015FBBFE017FBFFE047
+:106C000084FFBF003A7084183A70011017FBBFE090
+:106C100015FFBFE01758A0D0C30D8010C5FEBFE020
+:106C200017FFBFE015FCBFE017FCBFE03A70011092
+:106C3000C3FEBFE0062700003A30050015FABFE0AA
+:106C400017FAFFE084FFBF003A7084183A70011011
+:106C500017FABFE015FFBFE003F6BFE0BA900610D9
+:106C6000B40182003A888518175DB51015FDBFE0A4
+:106C700017FDBFE01E06001017FFBFE015F9BFE0CB
+:106C800017F9BFE03A700110C4108000061100002F
+:106C900017FDBFE0580080101E06001017FFBFE070
+:106CA00015F8BFE017F8BFE03A700110440F8000FC
+:106CB0000608000017FDBFE0C40FC000C50DC010DE
+:106CC00017FFBFE015F7BFE017F7BFE03A700110FC
+:106CD0003A8805003A8837E0170000DF0401C0DE7B
+:106CE0003A2800F804F4FFDE150BC0DF150A00DFB8
+:106CF000040A00DF3A88052015F77FE115F6BFE1A9
+:106D000005F8BFE015FF3FE00357A0D0CC3F80104F
+:106D10002605001017F6BFE04404C0000500C010AF
+:106D20003A880500063800003A30050015FCBFE03F
+:106D300017FCFFE084FFBF003A7084183A7001101E
+:106D400017FCBFE015FFBFE003F8BFE0D83F80109D
+:106D50001E0300101758A0D0830C801005F8BFE068
+:106D600003F8BFE0BA900610B40182003A88851893
+:106D7000175DB51015FEBFE017FEBFE01E0900103D
+:106D800017FFBFE015FBBFE017FBBFE03A70011033
+:106D900017F6BFE0C410C0000500C0103A88050017
+:106DA0000619000017FEBFE0580080101E090010F1
+:106DB00017FFBFE015FABFE017FABFE03A70011005
+:106DC00017F6BFE0C410C0000500C0103A880500E7
+:106DD000060D000017FEBFE0041380103A880B1068
+:106DE00017F73FE1007A1180C5FDBFE017FFBFE054
+:106DF00015F9BFE017F9BFE03A70011017F6BFE0D0
+:106E000005000010C3FDBFE03A8837E01701C0DF7E
+:106E1000170000DF0402C0DE3A2800F804F3FFDEAA
+:106E2000150CC0DF150B00DF040B00DF3A880520CE
+:106E300015F67FE115F5BFE105F7BFE015FF3FE06F
+:106E40000357A0D0CC3F80102604001017F5BFE0F8
+:106E50008404C0000500C010064200003A3005005E
+:106E600015FCBFE017FCFFE084FFBF003A708418F8
+:106E70003A70011017FCBFE015FFBFE003F7BFE059
+:106E8000D83F80101E0300101758A0D0830C80102C
+:106E900005F7BFE003F7BFE0BA900610B401820027
+:106EA0003A888518175DB51015FEBFE017FEBFE0E4
+:106EB0001E08001017FFBFE015FBBFE017FBBFE087
+:106EC0003A70011017F5BFE0C410C0000500C010F3
+:106ED0000624000017FEBFE0580080101E080010B6
+:106EE00017FFBFE015FABFE017FABFE03A700110D4
+:106EF00017F5BFE0C410C0000500C010061900005F
+:106F000017F63FE140811180C5FDBFE0C3FDBFE042
+:106F1000300880101E08001017FFBFE015F9BFE011
+:106F200017F9BFE03A70011017F5BFE04410C00038
+:106F30000500C010060B000017FEBFE00413801010
+:106F400017F67FE13A880910007A118017FFBFE039
+:106F500015F8BFE017F8BFE03A70011017F5BFE071
+:106F6000050000103A8837E01701C0DF170000DF86
+:106F70000402C0DE3A2800F804F4FFDE150BC0DF7F
+:106F8000150A00DF040A00DF3A88052005F6BFE095
+:106F900015FF3FE03A30050015FDBFE017FDFFE0AB
+:106FA00084FFBF003A7084183A70011017FDBFE0EB
+:106FB00015FFBFE003F6BFE0BA900610B4018200EF
+:106FC0003A888518175DB51015FEBFE017FEBFE0C3
+:106FD0001E06001017FFBFE015FCBFE017FCBFE066
+:106FE0003A70011084118000064C000017FEBFE0CB
+:106FF000580080101E06001017FFBFE015FBBFE011
+:1070000017FBBFE03A700110C41080000643000077
+:1070100017FEBFE0030C8010CC3F80100C028010E4
+:107020002639001017FEBFE0030CC010C4FDBF00DE
+:107030003A7084183A88071017FEBFE0050CC0109C
+:1070400017FEBFE0030C8010CC3F80101E280010FC
+:1070500017FEBFE08B0B8010CCFFBF101E1F00106F
+:1070600017FEBFE0830DC0100355A0D03AB08418BE
+:107070000555A0D017FEBFE0030D8010CC3FC01017
+:107080004455A0D03A8885180300001117FEBFE0D0
+:10709000430D801017FEFFE0030DC018CC3FC01851
+:1070A0003AB084203A8809104455A0D03A8885180F
+:1070B0000500001117FFBFE015FABFE017FABFE0A7
+:1070C0003A700110434BA0D0CC3F80105800801084
+:1070D0001E0B0010C06611800609000017FFBFE0FC
+:1070E00015F9BFE017F9BFE03A700110060400007F
+:1070F00017FFBFE015F8BFE017F8BFE03A700110C6
+:107100003A8805000605000017FFBFE015F7BFE04D
+:1071100017F7BFE03A700110041180003A8837E099
+:107120001701C0DF170000DF0402C0DE3A2800F8B4
+:1071300004F5FFDE150AC0DF150900DF040900DFD2
+:107140003A88052005F7BFE015FE3FE03A3005001C
+:1071500015FBBFE017FBFFE084FFBF003A70841807
+:107160003A70011017FBBFE015FEBFE003F7BFE068
+:10717000D83F80101E0600101758A0D0830C801036
+:1071800005F7BFE044008000C5FFBFE0060900002E
+:107190001758A0D0830C801003F7FFE0CC3F80107D
+:1071A0001E03801844008000C5FFBFE006010000F8
+:1071B000C5FF3FE003F7BFE0BA900610B4018200BC
+:1071C0003A888518175DB51015FDBFE017FDBFE0C3
+:1071D0001E06001017FEBFE015FABFE017FABFE069
+:1071E0003A700110041280000636000017FDBFE05F
+:1071F000580080101E06001017FEBFE015F9BFE012
+:1072000017F9BFE03A700110C4108000062D00008D
+:1072100017FDBFE0030D8010C5FCBFE0C3FCFFE01D
+:107220004455A0D03A888518030080103A8807108A
+:1072300017FDBFE0430D80103A3084003A70841887
+:10724000C3FCFFE03A8809104455A0D03A8885185D
+:1072500005000011C3FCFFE04455A0D03A88851812
+:1072600003008010CC3F80101E07001017FDBFE008
+:10727000830D80103A3084003A8807100355A0D05F
+:107280003A7084180555A0D017FDBFE0030C80109C
+:10729000140280103A88071017FDBFE0050CC010DB
+:1072A00017FEBFE015F8BFE017F8BFE03A70011015
+:1072B000C3FFBFE0580080101E010010C06611809F
+:1072C0003A8805003A8837E01701C0DF170000DF71
+:1072D0000402C0DE3A2800F804F6FFDE1509C0DF1C
+:1072E000150800DF040800DF3A88052015F87FE163
+:1072F00005F9BFE015FF3FE03A30050015FDBFE09E
+:1073000017FDFFE084FFBF003A7084183A70011047
+:1073100017FDBFE015FFBFE003F9BFE0D83F8010C5
+:107320001E0300101758A0D0830C801005F9BFE091
+:1073300003F9BFE0BA900610B40182003A888518BC
+:10734000175DB51015FEBFE017FEBFE01E0600106A
+:1073500017FFBFE015FCBFE017FCBFE03A7001105B
+:10736000440A80000612000017FEBFE0580080109B
+:107370001E06001017FFBFE015FBBFE017FBBFE0C4
+:107380003A700110C410800006090000041B80013F
+:1073900017FE7FE117F83FE14060118017FFBFE063
+:1073A00015FABFE017FABFE03A7001103A880500FD
+:1073B0003A8837E01701C0DF170000DF0402C0DEA3
+:1073C0003A2800F804F9FFDE1506C0DF150500DFD6
+:1073D000040500DF3A8805200DFBBFE015FF3FE004
+:1073E0000357A0D0CC3F80101E3100100BFBBFE034
+:1073F000263000103A30050015FDBFE017FDFFE014
+:1074000084FFBF003A7084183A70011017FDBFE086
+:1074100015FFBFE01758A0D0030D8010C5FEBFE0D8
+:10742000C3FEFFE04455A0D03A88851803008010C1
+:107430003A8807101758A0D0430D80103A308400C6
+:107440003A708418C3FEFFE03A8809104455A0D072
+:107450003A88851805000011C3FEFFE04455A0D00E
+:107460003A88851803008010CC3F80101E0700105A
+:107470001758A0D0830D80103A3084003A88071046
+:107480000355A0D03A7084180555A0D01758A0D045
+:107490000BFBFFE08D0BC01017FFBFE015FCBFE03A
+:1074A00017FCBFE03A700110C066118006010000B1
+:1074B0003A8801003A8837E01701C0DF170000DF83
+:1074C0000402C0DE3A2800F804F7FFDE1508C0DF2A
+:1074D000150700DF150600DC040700DF3A880520E9
+:1074E0003A8809303A88073805FCBFE03A88052811
+:1074F00005FBBFE03A88052005FABFE03A88051889
+:107500000DF9BFE00357A0D0CC3F80102602001039
+:10751000441580000625000003FCBFE02484C3104E
+:1075200003FBBFE0240F80103A88871803FABFE0FE
+:107530003A888518241900140BF9BFE0241980102B
+:10754000047D801004FA40013A88091080FF0C8005
+:107550003A88858015FDBFE017FDBFE03AD40410DE
+:107560008DFEBFE017FDBFE0CCFFBF1015FDBFE0F3
+:1075700017FDBFE0CCFFBF103A880910C03017805C
+:107580000607000014002001C030178014002001FD
+:10759000C03017808BFEBFE0C4FFBF108DFEBFE080
+:1075A0008BFEBFE01EF73F103A88050004FFFFE6A0
+:1075B0001702C0DF170100DF170000DC0403C0DE84
+:1075C0003A2800F804F5FFDE150AC0DF150900DFD0
+:1075D000040900DF3A88052005F7BFE015FF3FE00A
+:1075E00003F7BFE0300580101E020010840A8000FF
+:1075F000066200003A30050015FDBFE017FDFFE010
+:1076000084FFBF003A7084183A70011017FDBFE084
+:1076100015FFBFE003F7BFE0BA900610B401820087
+:107620003A888518175DB51015FEBFE017FEBFE05C
+:107630001E06001017FFBFE015FCBFE017FCBFE0FF
+:107640003A700110C4108000064C000017FEBFE025
+:10765000580080101E06001017FFBFE015FBBFE0AA
+:1076600017FBBFE03A700110C41080000643000011
+:1076700017FEBFE08B0B8010CCFFBF101E06001062
+:1076800017FFBFE015FABFE017FABFE03A7001102C
+:10769000041480000639000017FEBFE08D0B0010B7
+:1076A00017FEBFE0030C8010CC3F8010CC0D801083
+:1076B000260B001017FEBFE0030CC01004F2BF0041
+:1076C0003A7084183A88071017FEBFE0050CC01006
+:1076D00017FEBFE04400C000450CC01006020000C9
+:1076E00017FEBFE0450C001017FEBFE0030C801032
+:1076F000CC3F80100C0280101E1B001017FEBFE054
+:10770000830DC0100355A0D03AB084180555A0D001
+:1077100017FEBFE0030D8010CC3FC0104455A0D031
+:107720003A8885180300001117FEBFE0430D801052
+:1077300017FEFFE0030DC018CC3FC0183AB08420FC
+:107740003A8809104455A0D03A88851805000011E0
+:1077500017FFBFE015F9BFE017F9BFE03A7001105D
+:10776000C06611800604000017FFBFE015F8BFE0F7
+:1077700017F8BFE03A7001103A8805003A8837E000
+:107780001701C0DF170000DF0402C0DE3A2800F84E
+:1077900004FBFFDE150400DF040400DF15FF3FE0FB
+:1077A0003A30050015FCBFE017FCFFE084FFBF0086
+:1077B0003A7084183A70011017FCBFE015FFBFE063
+:1077C0001759A0D015FEBFE017FFBFE015FDBFE0C1
+:1077D00017FDBFE03A70011017FEBFE03A8837E0AE
+:1077E000170000DF0401C0DE3A2800F804FBFFDECA
+:1077F000150400DF040400DF15FC3FE115FF3FE046
+:107800003A30050015FDBFE017FDFFE084FFBF0023
+:107810003A7084183A70011017FDBFE015FFBFE001
+:1078200017FCBFE01559A0D017FFBFE015FEBFE061
+:1078300017FEBFE03A7001103A8801003A8837E03D
+:10784000170000DF0401C0DE3A2800F804FDFFDE67
+:107850001502C0DF150100DF040100DF15FF3FE165
+:10786000042460D117FF3FE1002A37803A8837E0CF
+:107870001701C0DF170000DF0402C0DE3A2800F85D
+:1078800004FDFFDE1502C0DF150100DF040100DF8B
+:1078900015FF3FE140363880440080003A70011007
+:1078A0003A8801003A8837E01701C0DF170000DF8F
+:1078B0000402C0DE3A2800F804FAFFDE1505C0DF36
+:1078C000150400DF040400DF0419C0013A880D002C
+:1078D0003A880B003410060104180F2140AA1780C3
+:1078E0003A880100040180013A880B00740102010A
+:1078F0000412312100B51C807401020104083121F9
+:107900004079178015FF3FE04400800015FEBFE07E
+:1079100017FEBFE0160280004400800015FEBFE0A5
+:1079200015FF3FE0064E000017FFBFE02407C01020
+:10793000B40182003A8885181572351017FFBFE030
+:107940002407C010B40182003A88851815733510D9
+:107950001709E0D017FFBFE024070011B40182002F
+:107960003A8885201574F51017FFBFE02407001131
+:10797000B400C2000436C418B40182003A888520DD
+:107980001575F51017FFBFE02407C010B401820081
+:107990000472B5103A888518040FE0D015FDFFE099
+:1079A00015FCBFE017FCBFE017FDFFE01501C0109C
+:1079B00017FDBFE01700C01017FCBFE01500C01096
+:1079C00017FDBFE01700801017FCFFE01501C01085
+:1079D00017FDBFE017FCFFE01500C010035CA0D04E
+:1079E000CC3F001117FFBFE02407C010B401820094
+:1079F0000472B5103A88871824030021B40182006C
+:107A00003A88852015B6F510035CA0D0CC3F8010D5
+:107A1000240300113410C6000400CC18B401820005
+:107A20003A88852015B7F510035CA0D0CC3F8010B4
+:107A300017FFFFE03A8809182403C010B401820040
+:107A40003A88851805B83511035CA0D04400801031
+:107A5000055CA0D017FFBFE04400801015FFBFE019
+:107A600017FFFFE017FEBFE016AFBF187401020159
+:107A7000043C312100D21D8074018200177BF1107B
+:107A800074018200177CB1103A880D103A880B18E7
+:107A90007401020104743121C0EE1F807401820060
+:107AA0001797F110740182001798B1103A880D10E1
+:107AB0003A880B187401020104903121C0EE1F8036
+:107AC0007401020104AC312100A820803A88010031
+:107AD0003A8837E01701C0DF170000DF0402C0DE7C
+:107AE0003A2800F804FAFFDE1505C0DF150400DFB0
+:107AF000040400DF15FC3FE13A88070017FCBFE0F3
+:107B00003500C01017FCBFE0040180103700801062
+:107B10003A30050015FDBFE017FDFFE084FFBF0010
+:107B20003A7084183A70011017FDBFE015FFBFE0EE
+:107B300080F5378017FFBFE015FEBFE017FEBFE0FE
+:107B40003A7001103A8801003A8837E01701C0DF27
+:107B5000170000DF0402C0DE3A2800F804F8FFDE58
+:107B60001507C0DF150600DF040600DF15FE3FE144
+:107B700015FD7FE115FCBFE115FBFFE117FBBFE041
+:107B800015FFBFE0178DA0D01E02001017FFBFE049
+:107B9000158DA0D017FEBFE004018010C401C00005
+:107BA0003500C010150000D817FEFFE174008201F7
+:107BB000048B9E3117FC7FE117FD3FE14049378080
+:107BC0003A8801003A8837E01701C0DF170000DF6C
+:107BD0000402C0DE3A2800F804FBFFDE150100DFD6
+:107BE000040100DF15FF3FE1150140E1150280E1CE
+:107BF0001503C0E13A8801003A8837E0170000DF3A
+:107C00000404C0DE3A2800F804FBFFDE150400DFA0
+:107C1000040400DF15FF3FE115FE7FE115FDBFE124
+:107C200015FCFFE117FEFFE017FFBFE01500C010D5
+:107C300017FDFFE017FFBFE01501C01017FCFFE0C4
+:107C400017FFBFE01502C0101701C0E017FFBFE02B
+:107C50001504C0103A8805003A8837E0170000DFA5
+:107C60000401C0DE3A2800F804FAFFDE1505C0DF83
+:107C7000150400DF040400DF15FD3FE115FC7FE182
+:107C8000C5FE3FE015FF3FE0060B000017FFFFE0D9
+:107C90004400801815FFBFE0F403800004909010AA
+:107CA0001E0580183401020104341E21C0D902804F
+:107CB00084FABF000619000017FDBFE0170180100D
+:107CC00017038010370080104C0080101EEF3F100B
+:107CD0000404400117FC3FE1001C378017FDBFE0A2
+:107CE0001701801017FC7FE13A88091000162080E8
+:107CF000C5FEBFE0C3FEBFE026070010C3FEBFE025
+:107D00003A880B1034010201043B1E2180C7028017
+:107D1000C4FFBF00060100003A8805003A8837E03A
+:107D20001701C0DF170000DF0402C0DE3A2800F8A8
+:107D300004F9FFDE1506C0DF150500DF040500DFCE
+:107D400015FE3FE115FD7FE117FEBFE01702C010F1
+:107D500044008000150180D844008000150080D8C0
+:107D60003A880F003A880D0017FD7FE13A8809181C
+:107D700040D31F80C5FFBFE0C3FFBFE02602001055
+:107D8000C4FFBF00060100003A8805003A8837E0CA
+:107D90001701C0DF170000DF0402C0DE3A2800F838
+:107DA00004F9FFDE1506C0DF150500DF040500DF5E
+:107DB00015FE3FE115FD7FE117FEBFE01701C01082
+:107DC00044008000150180D844008000150080D850
+:107DD0003A880F003A880D0017FD7FE13A880918AC
+:107DE00040D31F80C5FFBFE0C3FFBFE026020010E5
+:107DF000C4FFBF00060100003A8805003A8837E05A
+:107E00001701C0DF170000DF0402C0DE3A2800F8C7
+:107E100004FCFFDE150300DF040300DF15FD3FE176
+:107E200017FDBFE0040280103700801015FEBFE090
+:107E300017FDBFE0040280100402C8003500C01026
+:107E400015FF3FE00603000017FFBFE0440080106D
+:107E500015FFBFE017FDBFE004028010370080105F
+:107E60000C0088102603001017FFBFE010C4891013
+:107E70001EF53F1017FDBFE00402801017FEFFE063
+:107E80003500C0103A8805003A8837E0170000DF57
+:107E90000401C0DE3A2800F804FDFFDE150200DF11
+:107EA000040200DF15FE3FE117FEBFE00402801070
+:107EB0003700801015FFBFE017FFFFE0C4FDBF00D3
+:107EC0003A70841815FFBFE017FEBFE0040280106F
+:107ED00017FFFFE03500C0103A8805003A8837E008
+:107EE000170000DF0401C0DE3A2800F804FDFFDEC1
+:107EF000150200DF040200DF15FE3FE117FEBFE0C0
+:107F0000040280103700801015FFBFE017FFBFE0AC
+:107F10001402801015FFBFE017FEBFE004028010BE
+:107F200017FFFFE03500C0103A8805003A8837E0B7
+:107F3000170000DF0401C0DE3A2800F804FBFFDE72
+:107F40001504C0DF150300DF150200DC040300DFA9
+:107F500015FD3FE115FE3FE00625000017FEBFE0DE
+:107F6000BA900610B40182003A88851817AEB51091
+:107F70001714C01017FDBFE0171480101E198018C9
+:107F800017FEBFE0BA900610B40182003A88851847
+:107F900017AEB5100315C01017FDBFE00315801014
+:107FA000CC3FC018CC3F80101E0E801817FDBFE0DC
+:107FB000171480103A88071017FDBFE003158010D2
+:107FC000CC3F80103A880D103A880B18340102011A
+:107FD000044D1E2180C702803401020104611E216C
+:107FE000C0D9028017FEBFE04400801015FEBFE03C
+:107FF000035BA0D0CC3F801017FEFFE016D7BF1860
+:10800000035BA0D0CC3F00140419000180C942805A
+:108010003A880910BA900680B40182003A8885181F
+:1080200015AE3511035BA0D0CC3F8010BA9006107E
+:10803000B40182003A88851817AEB5101E080010EA
+:10804000035BA0D0CC3F80103A880B1034010201B2
+:1080500004791E2180C70280C4FFBF00061E0000F5
+:10806000035BA0D0CC3F8010BA900610B401820010
+:108070003A88851817AEF51017FDBFE03A88091049
+:10808000041980003A880D103A880B203A880918A4
+:10809000806B0880035BA0D0CC3F8010BA900610A4
+:1080A000B40182003A88851817AEB5103A880710D7
+:1080B00017FDBFE03A880B103A88091800F6428095
+:1080C000035BA0D044008010055BA0D0035BA0D070
+:1080D000CC3F8010C4FFBF1004FFFFE61702C0DFD3
+:1080E000170100DF170000DC0403C0DE3A2800F8A7
+:1080F00004F2FFDE150DC0DF150C00DF150B00DCF0
+:10810000040C00DF15F73FE115F67FE115F5BFE13F
+:1081100015F4FFE117F7BFE015F8BFE017F6BFE071
+:1081200015FBBFE017F5BFE015FCBFE017F4BFE09B
+:1081300015FEBFE0170280E015FDBFE017F8BFE0B5
+:1081400003038010CC3F80101E0300104400800009
+:1081500015F9BFE0060E000017F8BFE0030380101A
+:10816000CC3F80102605001017F8BFE003038010F5
+:10817000CC3F801015F9BFE0060500003401020174
+:1081800004881E21C0D90280C4FFBF00060302007C
+:1081900015FA3FE006FD0100835BA0D0CC3F8010C4
+:1081A0001C20801004E0BF10100180101E0C001075
+:1081B0003401020104941E21C0D90280835BA0D047
+:1081C000CC3F80101C20801004E0BF103A880D10B6
+:1081D000040140013401020104A41E2180C7028071
+:1081E00017F8BFE01E0800103401020104B31E217D
+:1081F000C0D902803401020104BD1E21C0D9028011
+:10820000C4FFBF0006E5010017F8BFE01700C0106B
+:1082100017FABFE0BA9204103A880910835BA0D025
+:10822000CC3F80101C20801004E0BF103A88071952
+:1082300024130011740182003A8885201554EE1031
+:1082400017F8BFE00B01C010835BA0D0CC3F8010BB
+:108250001C20801004E0BF10CCFFFF182413001175
+:10826000740182003A8885201555EE1017F8BFE09A
+:108270008B01C010835BA0D0CC3F80101C208010ED
+:1082800004E0BF10CCFFFF1824130011740182001A
+:108290003A8885201556EE10835BA0D0CC3F801025
+:1082A0001C20801004E0BF1017F8FFE00302C01884
+:1082B00024130011740182003A8885200557EE10BE
+:1082C000835BA0D0CC3F80101C20801004E0BF1046
+:1082D00017F8FFE04302C018241300117401820054
+:1082E0003A8885204557EE10835BA0D0CC3F8010A4
+:1082F0001C20801004E0BF1017F8FFE08302C018B4
+:1083000024130011740182003A8885208557EE10ED
+:10831000835BA0D0CC3F80101C20801004E0BF10F5
+:1083200017F8FFE0C302C018241300117401820083
+:108330003A888520C557EE10835BA0D0CC3F8010D3
+:108340001C20801004E0BF1017F8FFE00303C018E2
+:1083500024130011740182003A8885200558EE101C
+:10836000835BA0D0CC3F80101C20801004E0BF10A5
+:1083700017F8FFE04303C0182413001174018200B2
+:108380003A8885204558EE10835BA0D0CC3F801002
+:108390001C20801004E0BF1017F8FFE08303C01812
+:1083A00024130011740182003A8885208558EE104C
+:1083B000835BA0D0CC3F80101C20801004E0BF1055
+:1083C00017F8FFE0C303C0182413001174018200E2
+:1083D0003A888520C558EE10835BA0D0CC3F801032
+:1083E0001C20801004E0BF1017F8FFE00304C01841
+:1083F00024130011740182003A8885200559EE107B
+:1084000017FBBFE01E0D00103401020104CF1E2136
+:10841000C0D90280835BA0D0CC3F80101C2080108C
+:1084200004E0BF103A880B103401020104DA1E2167
+:1084300080C70280C4FFBF000658010017FBBFE0E1
+:10844000170080103A880910C0DA028044008010BA
+:10845000835BE0D0CC3F001C1C20008404E03F8400
+:108460003A88091080C942803A8809102413C080D4
+:10847000740182003A888518155A2E11835BA0D0AA
+:10848000CC3F80101C20801004E0BF102413C010CB
+:10849000740182003A888518175AAE101E0A00101F
+:1084A000835BA0D0CC3F80101C20801004E0BF1064
+:1084B0003A880B103401020104F21E2180C70280A9
+:1084C000C4FFBF0006350100835BA0D0CC3F801005
+:1084D0001C20801004E0BF102413C010740182001F
+:1084E0003A888518175AEE1017FBBFE01700801066
+:1084F0003A880B103A88091800F6428017FBBFE053
+:10850000170180103A880910C0DA028044008010F8
+:10851000835BE0D0CC3F001C1C20008404E03F843F
+:108520003A88091080C942803A8809102413C08013
+:10853000740182003A888518155B2E11835BA0D0E8
+:10854000CC3F80101C20801004E0BF102413C0100A
+:10855000740182003A888518175BAE101E0A00105D
+:10856000835BA0D0CC3F80101C20801004E0BF10A3
+:108570003A880B103401020104051F2180C70280D4
+:10858000C4FFBF0006050100835BA0D0CC3F801074
+:108590001C20801004E0BF102413C010740182005E
+:1085A0003A888518175BEE1017FBBFE017018010A3
+:1085B0003A880B103A88091800F64280835BA0D0F5
+:1085C000CC3F80101C20801004E0BF1017FBFFE0A0
+:1085D0000B02C01824130011740182003A88852010
+:1085E0000D5CEE1017FCBFE01E110010835BA0D0E5
+:1085F000CC3F80101C20801004E0BF102413C0105A
+:10860000740182003A888518855C2E10835BA0D0A7
+:10861000CC3F80101C20801004E0BF102413C01039
+:10862000740182003A888518155D2E10061400002A
+:10863000835BA0D0CC3F80101C20801004E0BF10D2
+:1086400017FCFFE00300C01824130011740182001E
+:108650003A888520855CEE10835BA0D0CC3F8010EB
+:108660001C20801004E0BF1017FCFFE01701C018A9
+:1086700024130011740182003A888520155DEE10E4
+:1086800017FEBFE01E390010835BA0D0CC3F8010E6
+:108690001C20801004E0BF102413C010740182005D
+:1086A0003A888518055E2E10835BA0D0CC3F8010E1
+:1086B0001C20801004E0BF102413C010740182003D
+:1086C0003A888518155F2E10835BA0D0CC3F8010B0
+:1086D0001C20801004E0BF102413C010740182001D
+:1086E0003A88851815602E10835BA0D0CC3F80108F
+:1086F0001C20801004E0BF102413C01074018200FD
+:108700003A88851815612E10835BA0D0CC3F80106D
+:108710001C20801004E0BF102413C01074018200DC
+:108720003A88851815622E10835BA0D0CC3F80104C
+:108730001C20801004E0BF102413C01074018200BC
+:108740003A88851815632E10835BA0D0CC3F80102B
+:108750001C20801004E0BF102413C010740182009C
+:108760003A88851815642E1006460000835BA0D059
+:10877000CC3F80101C20801004E0BF1017FEFFE0EB
+:108780000300C01824130011740182003A88852068
+:10879000055EEE10835BA0D0CC3F80101C208010C3
+:1087A00004E0BF1017FEFFE01701C01824130011EA
+:1087B000740182003A888520155FEE10835BA0D09B
+:1087C000CC3F80101C20801004E0BF1017FEFFE09B
+:1087D0001702C01824130011740182003A88852002
+:1087E0001560EE10835BA0D0CC3F80101C20801061
+:1087F00004E0BF1017FEFFE01703C0182413001198
+:10880000740182003A8885201561EE10835BA0D048
+:10881000CC3F80101C20801004E0BF1017FEFFE04A
+:108820001704C01824130011740182003A888520AF
+:108830001562EE10835BA0D0CC3F80101C2080100E
+:1088400004E0BF1017FEFFE01705C0182413001145
+:10885000740182003A8885201563EE10835BA0D0F6
+:10886000CC3F80101C20801004E0BF1017FEFFE0FA
+:108870001706C01824130011740182003A8885205D
+:108880001564EE1017FDBFE01E120010835BA0D030
+:10889000CC3F80101C20801004E0BF102413001176
+:1088A000C4FFFF00740182003A8885201565EE1030
+:1088B000835BA0D0CC3F80101C20801004E0BF1050
+:1088C0002413C010740182003A88851815662E1092
+:1088D00006140000835BA0D0CC3F80101C208010C9
+:1088E00004E0BF1017FDFFE01700C01824130011AB
+:1088F000740182003A8885201565EE10835BA0D054
+:10890000CC3F80101C20801004E0BF1017FDFFE05A
+:108910001701C01824130011740182003A888520C1
+:108920001566EE1017FBBFE00403801015FBBFE0D7
+:1089300017FCBFE02603001017FCBFE00402801004
+:1089400015FCBFE017FEBFE02603001017FEBFE0D6
+:108950000407801015FEBFE017FDBFE026030010DE
+:1089600017FDBFE00402801015FDBFE0835BA0D0BF
+:1089700044008010855BA0D0835BA0D0050AA0D006
+:1089800017FABFE04400801015FABFE017FAFFE0C5
+:1089900017F9BFE01600BE183A88050004FFFFE68D
+:1089A0001702C0DF170100DF170000DC0403C0DE80
+:1089B0003A2800F804F9FFDE1506C0DF150500DFD0
+:1089C000040500DF15FC3FE13A88052805FBBFE000
+:1089D00015FF3FE0063F000017FFBFE0BA9004100C
+:1089E00017FCFFE03A8885181700801015FDBFE0DE
+:1089F00017FDBFE01E0800103401020104B31E2160
+:108A0000C0D902803401020104181F21C0D902809C
+:108A1000C4FFBF000633000015FE3FE0062600003D
+:108A200017FDBFE01700C01017FEBFE024130011B0
+:108A3000740182003A8885201754AE101E1B8018DE
+:108A400017FEBFE02413C010740182003A88851815
+:108A5000C357AE10CC3F801026080010340102012D
+:108A6000042C1F21C0D9028034010201043D1F21C2
+:108A7000C0D90280C4FFBF00061A000017FEBFE085
+:108A8000241300114400C000740182003A8885203C
+:108A90004558EE1017FEBFE02413001103FBFFE062
+:108AA000740182003A8885208558EE1017FEBFE0D9
+:108AB0004400801015FEBFE0030AA0D0CC3F801018
+:108AC00017FEFFE016D6BF1817FFBFE04400801066
+:108AD00015FFBFE003FBBFE017FFFFE016BEBF18A6
+:108AE0003A8805003A8837E01701C0DF170000DF39
+:108AF0000402C0DE3A2800F804FCFFDE1503C0DFE4
+:108B0000150200DF040200DF15FE3FE117FE3FE122
+:108B1000C0C118801703801015FFBFE017FF3FE1A9
+:108B200000DB1B803A8837E01701C0DF170000DF49
+:108B30000402C0DE3A2800F804FBFFDE1504C0DFA3
+:108B4000150300DF040300DF15FE3FE115FD7FE1A3
+:108B500017FE3FE1C0C118801703801015FFBFE06A
+:108B600017FD7FE117FF3FE1C00C1C803A8837E01A
+:108B70001701C0DF170000DF0402C0DE3A2800F84A
+:108B800004FDFFDE150200DF040200DF15FE3FE1F9
+:108B900015FF3FE0060C000017FFBFE02413C010D4
+:108BA000740182000454AE103A88851817FEFFE065
+:108BB0001E02801817FFBFE00608000017FFBFE085
+:108BC0004400801015FFBFE0030AA0D0CC3F801006
+:108BD00017FFFFE016F0BF18C4FFBF003A8837E068
+:108BE000170000DF0401C0DE3A2800F804FDFFDEB4
+:108BF000150200DF040200DF15FE3FE115FF3FE034
+:108C0000060C000017FFBFE0BA900610B401820006
+:108C10003A88851817AAB51017FEFFE01E028018C3
+:108C200017FFBFE00608000017FFBFE044008010F8
+:108C300015FFBFE0435BA0D0CC3F801017FFFFE0E3
+:108C400016F0BF18C4FFBF003A8837E0170000DFF6
+:108C50000401C0DE3A2800F804FDFFDE150200DF43
+:108C6000040200DF15FE3FE115FF3FE0060E0000A5
+:108C700017FEBFE01703C01017FFBFE044008010CD
+:108C8000BA9004103A8885181700801017FEFFE08C
+:108C90001E02801817FFBFE0060A000017FFBFE0A2
+:108CA0004400801015FFBFE017FEBFE017038010DF
+:108CB00003008010CC3F801017FFFFE016ECBF18B8
+:108CC000C4FFBF003A8837E0170000DF0401C0DEB0
+:108CD0003A2800F804FAFFDE150500DF040500DF7E
+:108CE00015FB3FE115FD3FE015FC3FE015FF3FE0C0
+:108CF0000622000017FFBFE0BA900610B401820000
+:108D00003A88851817AAB51015FDBFE015FE3FE09B
+:108D10000612000017FDFFE017FEBFE044008010C0
+:108D2000BA9004103A8885181700801015FCBFE02F
+:108D300017FCBFE017028010170080103A88071058
+:108D400017FBBFE01E02C01017FCBFE006100000BA
+:108D500017FEBFE04400801015FEBFE017FDBFE026
+:108D600003008010CC3F801017FEFFE016E9BF180B
+:108D700017FFBFE04400801015FFBFE0435BA0D0A9
+:108D8000CC3F801017FFFFE016DABF183A880500C5
+:108D90003A8837E0170000DF0401C0DE3A2800F807
+:108DA00004FCFFDE150300DF040300DF15FE3FE1D6
+:108DB0003A88052805FDBFE017FEBFE004028010D9
+:108DC0003700801015FFBFE003FDBFE09800801062
+:108DD0001E09001017FFBFE01402801015FFBFE04E
+:108DE00017FFFFE03480BF00C4FFBF103A70841843
+:108DF00015FFBFE00619000003FDBFE0580080101A
+:108E00001E0A001017FFFFE0C4FDBF003A7084186F
+:108E100015FFBFE017FFFFE03480BF00C4FFBF10A5
+:108E20003A70841815FFBFE0060C000003FDBFE098
+:108E30001E08001017FFFFE0C4FDBF003A70841841
+:108E400015FFBFE017FFBFE03480801015FFBFE0C3
+:108E50000602000084FDBF000605000017FEBFE00B
+:108E60000402801017FFFFE03500C0103A880500AB
+:108E70003A8837E0170000DF0401C0DE3A2800F826
+:108E800004FCFFDE150300DF040300DF15FE3FE1F5
+:108E90003A88052805FDBFE017FEBFE004028010F8
+:108EA0003700801015FFBFE003FDBFE01E04001077
+:108EB00017FFBFE01400811015FFBFE0060A000095
+:108EC00003FDBFE0580080101E05001017FFFFE0F3
+:108ED000C4FFBE003A70841815FFBFE00602000010
+:108EE00084FDBF000605000017FEBFE004028010ED
+:108EF00017FFFFE03500C0103A8805003A8837E0D8
+:108F0000170000DF0401C0DE3A2800F804F4FFDE99
+:108F1000150BC0DF150A00DF040A00DF15F73FE17B
+:108F200044008000C5FEBFE04400800085FEBFE035
+:108F300083FEBFE04C00C010C3FEBFE0980080106D
+:108F40001E02001084008000060100003A8805001F
+:108F50003AB0C610C3FEBFE0580080101E020010D9
+:108F600004018000060100003A8805003AB0C610EE
+:108F7000C3FEBFE01E0200100402800006010000D4
+:108F80003A8805003AB0C610C3FEBFE0D800801092
+:108F90001E02001074008000060100003A880500DF
+:108FA0003AB0C41015FFBFE015FD3FE015FC3FE0EF
+:108FB00015FB3FE015FA3FE0C5F93FE085F93FE0DA
+:108FC000C35BA0D0CC3F80101E030010C0E01A800D
+:108FD00044008000C55BA0D017F73FE1C0C11880F6
+:108FE00015FCBFE017FCBFE01E48001044008000E5
+:108FF000C5FEBFE04400800085FEBFE083FEBFE009
+:109000004C00C010C3FEBFE0980080101E0200108C
+:1090100084008000060100003A8805003AB0C610BE
+:10902000C3FEBFE0580080101E0200100401800043
+:10903000060100003A8805003AB0C610C3FEBFE042
+:109040001E02001004028000060100003A8805009C
+:109050003AB0C610C3FEBFE0D80080101E02001058
+:1090600074008000060100003A8805003AB0C41080
+:109070003420801015FFBFE0C3FEBFE0A0008010C9
+:109080001E0E0010C3FEBFE0600080101E0800101E
+:10909000C3FEBFE01E03001034018200044C9F1089
+:1090A0000608000034018200044D9F1006050000F0
+:1090B00034018200044F9F10060200003401820038
+:1090C00004509F1083FEFFE05800C0181E030018D4
+:1090D0003401C2000452DF18060200003401C2004D
+:1090E0000454DF183A880D183A880B103401020135
+:1090F00004561F2180C7028034010201046E1F2123
+:10910000C0D9028017FFBFE00619020017FCBFE0BC
+:109110001701801015FDBFE017FCBFE0170380109A
+:1091200015FBBFE017FCBFE01702801015FABFE087
+:1091300017FC3FE100BA1880C5F9BFE017FB3FE11B
+:1091400040B3188085F9BFE017FBBFE0170180101E
+:109150001702801003038010CC3F80101E5A0010AD
+:1091600044008000C5FEBFE04400800085FEBFE0F3
+:1091700083FEBFE04C00C010C3FEBFE0980080102B
+:109180001E02001084008000060100003A880500DD
+:109190003AB0C610C3FEBFE0580080101E02001097
+:1091A00004018000060100003A8805003AB0C610AC
+:1091B000C3FEBFE01E020010040280000601000092
+:1091C0003A8805003AB0C610C3FEBFE0D800801050
+:1091D0001E02001074008000060100003A8805009D
+:1091E0003AB0C4103410801015FFBFE0F403000142
+:1091F00004901021C011388017FABFE017128010B8
+:10920000260D001087F9BFE0C7F9FFE03A880D1876
+:109210003A880B1034010201047F1F2180C70280AD
+:1092200017FABFE01712801017F73FE13AE83E1037
+:1092300015FFBFE00622000087F93FE1C3FEBFE053
+:10924000A00080101E0E0010C3FEBFE06000801062
+:109250001E080010C3FEBFE01E0300103401820090
+:10926000044C9F100608000034018200044D9F103A
+:109270000605000034018200044F9F100602000022
+:109280003401820004509F1083FEFFE05800C01894
+:109290001E0300183401C2000452DF180602000049
+:1092A0003401C2000454DF183A880F183A880D10B0
+:1092B0003A880B203401020104911F2180C70280EB
+:1092C00017FFBFE006AA010017FBBFE017018010DF
+:1092D000170280101700801015F8BFE017FDBFE0DF
+:1092E0001E49001044008000C5FEBFE0440080001D
+:1092F00085FEBFE083FEBFE04C00C010C3FEBFE0B0
+:10930000980080101E0200108400800006010000FA
+:109310003A8805003AB0C610C3FEBFE0580080107E
+:109320001E02001004018000060100003A880500BA
+:109330003AB0C610C3FEBFE01E0200100402800057
+:10934000060100003A8805003AB0C610C3FEBFE02F
+:10935000D80080101E02001074008000060100007A
+:109360003A8805003AB0C4103408801015FFBFE0F9
+:1093700087F93FE1C7F97FE1C3FEBFE0A00080109D
+:109380001E0E0010C3FEBFE0600080101E0800101B
+:10939000C3FEBFE01E03001034018200044C9F1086
+:1093A0000608000034018200044D9F1006050000ED
+:1093B00034018200044F9F10060200003401820035
+:1093C00004509F1083FEFFE05800C0181E030018D1
+:1093D0003401C2000452DF18060200003401C2004A
+:1093E0000454DF181500C0D83A880F103A880D28A9
+:1093F0003A880B203401020104A31F2180C7028098
+:1094000017FFBFE0065A010017FCBFE00300801001
+:10941000CC3F8010580080101E0700103A880B00C7
+:1094200017FD3FE1007F1B800471420117FD3FE102
+:1094300080F11A80060E000017FCBFE003008010C8
+:10944000CC3F8010980080101E0900103A880B0055
+:1094500017FD3FE1409B1B803A880B0017FD3FE161
+:1094600080C01B800471420117FD3FE180F11A802A
+:109470000471420117FD3FE1C00D1B80D8FFBF10F2
+:109480001E49001044008000C5FEBFE0440080007B
+:1094900085FEBFE083FEBFE04C00C010C3FEBFE00E
+:1094A000980080101E020010840080000601000059
+:1094B0003A8805003AB0C610C3FEBFE058008010DD
+:1094C0001E02001004018000060100003A88050019
+:1094D0003AB0C610C3FEBFE01E02001004028000B6
+:1094E000060100003A8805003AB0C610C3FEBFE08E
+:1094F000D80080101E0200107400800006010000D9
+:109500003A8805003AB0C4103402801015FFBFE05D
+:1095100087F93FE1C7F97FE1C3FEBFE0A0008010FB
+:109520001E0E0010C3FEBFE0600080101E08001079
+:10953000C3FEBFE01E03001034018200044C9F10E4
+:109540000608000034018200044D9F10060500004B
+:1095500034018200044F9F10060200003401820093
+:1095600004509F1083FEFFE05800C0181E0300182F
+:109570003401C2000452DF18060200003401C200A8
+:109580000454DF181500C0D83A880F103A880D2807
+:109590003A880B203401020104B41F2180C70280E5
+:1095A00017FFBFE006F2000017F8BFE004108010BC
+:1095B00017FDFFE00300C018CC3FC0183500C010F5
+:1095C000150000D84400C001840380013A880B00D4
+:1095D00017FD3FE1C096198017FDBFE01705801009
+:1095E0001E2B001087F9BFE0C7F9FFE03A880D187D
+:1095F0003A880B103401020104C81F2180C7028081
+:1096000044008000C5FEBFE04400800085FEBFE04E
+:1096100083FEBFE04C00C010C3FEBFE09800801086
+:109620001E02001084008000060100003A88050038
+:109630003AB0C610C3FEBFE0580080101E020010F2
+:1096400004018000060100003A8805003AB0C61007
+:10965000C3FEBFE01E0200100402800006010000ED
+:109660003A8805003AB0C610C3FEBFE0D8008010AB
+:109670001E02001074008000060100003A880500F8
+:109680003AB0C4103401801015FFBFE0069300000B
+:1096900017FDBFE017058010171880102625001051
+:1096A00017FDBFE0170580101718801017F83FE16D
+:1096B0003AE83E1015FFBFE017FFBFE08C008010B6
+:1096C0001E0C001017FFBFE00C0180101E070010D9
+:1096D00017FFBFE00C028010260200103A88050038
+:1096E00006050000C400800006030000440080005E
+:1096F0000601000084008000C5FEBFE017FFBFE048
+:109700004C00801085FEBFE017FFBFE06C008010AA
+:109710002672001087F9BFE0C7F9FFE03A880D18FC
+:109720003A880B103401020104D61F2180C7028041
+:10973000066A000017FDBFE0170580108315801032
+:10974000CC3F80101E2B001087F9BFE0C7F9FFE067
+:109750003A880D183A880B103401020104E31F21E6
+:1097600080C7028044008000C5FEBFE04400800046
+:1097700085FEBFE083FEBFE04C00C010C3FEBFE02B
+:10978000980080101E020010840080000601000076
+:109790003A8805003AB0C610C3FEBFE058008010FA
+:1097A0001E02001004018000060100003A88050036
+:1097B0003AB0C610C3FEBFE01E02001004028000D3
+:1097C000060100003A8805003AB0C610C3FEBFE0AB
+:1097D000D80080101E0200107400800006010000F6
+:1097E0003A8805003AB0C410B400801015FFBFE0FD
+:1097F000063A000017FDBFE01705801083158010A2
+:10980000CC3FC01017FDBFE017058010C3158010B6
+:10981000CC3F80108400C0013A880D103A880B18A4
+:1098200017FD3FE180A91980C5FEBFE017FDBFE02D
+:109830001705801083158010CC3FC01017FDBFE0C6
+:109840001705801003168010CC3F80104400C00123
+:109850003A880D103A880B1817FD3FE180A919804E
+:1098600085FEBFE083FEBFE04C00C010C3FEBFE03A
+:10987000980080101E020010840080000601000085
+:109880003A8805003AB0C610C3FEBFE05800801009
+:109890001E02001004018000060100003A88050045
+:1098A0003AB0C610C3FEBFE01E02001004028000E2
+:1098B000060100003A8805003AB0C610C3FEBFE0BA
+:1098C000D80080101E020010740080000601000005
+:1098D0003A8805003AB0C41015FFBFE087F93FE1B0
+:1098E000C7F97FE1C3FEBFE0A00080101E0E00108C
+:1098F000C3FEBFE0600080101E080010C3FEBFE082
+:109900001E03001034018200044C9F100608000062
+:1099100034018200044D9F100605000034018200CE
+:10992000044F9F10060200003401820004509F1073
+:1099300083FEFFE05800C0181E0300183401C20067
+:109940000452DF18060200003401C2000454DF187C
+:109950001500C0D83A880F103A880D283A880B2095
+:109960003401020104FA1F2180C7028017FFBFE003
+:109970003A8837E01701C0DF170000DF0402C0DEBD
+:109980003A2800F804FDFFDE150200DF040200DFC4
+:1099900015FE3FE117FEBFE0170680101703801089
+:1099A00017018010170280101700801015FFBFE00C
+:1099B00017FFBFE004108010370080103A8837E0AE
+:1099C000170000DF0401C0DE3A2800F804FCFFDEC7
+:1099D000150300DF040300DF15FE3FE13A88052888
+:1099E00005FDBFE017FEBFE01706801017038010CB
+:1099F00017018010170280101700801015FFBFE0BC
+:109A000017FFBFE00410801003FDFFE03500C01019
+:109A10003A8805003A8837E0170000DF0401C0DE0D
+:109A20003A2800F804F6FFDE150900DF040900DF1C
+:109A300015FB3FE13A8807283A880B303A88093805
+:109A4000170180E005FAFFE03A88072805F9FFE0F2
+:109A50003A88072005F8FFE00DF7BFE017FBBFE0ED
+:109A6000170680101703801017018010170280104E
+:109A70001700801015FDBFE08DFF3FE015FE3FE0B1
+:109A8000060900008BFFBFE03A8885108DFFBFE01C
+:109A90008BFFBFE0540080108DFFBFE017FEBFE0DA
+:109AA0004400801015FEBFE003F8BFE017FEFFE0A2
+:109AB00016F4BF188BFFFFE003F9BFE03A98841853
+:109AC0008DFFBFE017FDBFE004A0801003FAFFE0A8
+:109AD000BA9006183A88C510370080108DFCBFE098
+:109AE0008BFFBFE03A3084003A8807108BFCBFE060
+:109AF0003A7084188DFCBFE00BF7FFE003F9BFE07C
+:109B00003A9884183A8807108BFFBFE03A7084189F
+:109B10003A8807108BFCBFE03AB084188DFCBFE098
+:109B200017FDBFE004A0801003FAFFE0BA9006180A
+:109B30003A88C5108BFCFFE03500C0103A8805005C
+:109B40003A8837E0170000DF0401C0DE3A2800F849
+:109B500004F7FFDE150800DF040800DF15FB3FE116
+:109B60003A8805283A8809303A88073805FABFE06C
+:109B70003A88052005F9BFE03A88051805F8BFE0E6
+:109B800017FBBFE017068010170380101701801025
+:109B9000170280101700801015FDBFE015FF3FE091
+:109BA00015FE3FE00609000017FFBFE03A88851068
+:109BB00015FFBFE017FFBFE05400801015FFBFE0A6
+:109BC00017FEBFE04400801015FEBFE003F8BFE0C1
+:109BD00017FEFFE016F4BF1817FDBFE004A08010C9
+:109BE00003FAFFE0BA9006183A88C51037008010D3
+:109BF0008DFCBFE08BFCFFE003F9BFE03AD885188D
+:109C00008DFCBFE08BFCFFE017FFBFE03A708418CB
+:109C10003A8837E0170000DF0401C0DE3A2800F878
+:109C20000481FFDE157EC0DF157D00DF047D00DFCF
+:109C300004E7BFE00419C0003A880D183A880B0009
+:109C40003A880910408E0880B49C9D0044539810B7
+:109C500015E7BFE0341B880044199B1015E8BFE0EE
+:109C600074518C00040E8E1015E9BFE0740C800056
+:109C7000444C8C1015EABFE004EBBFE00410C000B8
+:109C80003A880D183A880B003A880910408E0880EF
+:109C9000C410940015FBBFE00403800005FCBFE086
+:109CA0008400800045FCBFE04404800085FCBFE0E8
+:109CB00084038000C5FCBFE04403800005FDBFE0D5
+:109CC0008402800045FDBFE0B4008200045FB11053
+:109CD00015FEBFE004CEBFE00419C0003A880D189D
+:109CE0003A880B003A880910408E0880B49C9D0089
+:109CF0004453981015CEBFE0341B880044199B10C4
+:109D000015CFBFE07418990044549D1015D0BFE0E2
+:109D1000345296000408941015D1BFE0344E9100DF
+:109D200004088E1015D2BFE0344D8D00444C8C10C9
+:109D300015D3BFE015D43FE015D53FE015D63FE081
+:109D400015D73FE015D83FE015D93FE015DA3FE0E1
+:109D500015DB3FE015DC3FE015DD3FE015DE3FE0C1
+:109D600015DF3FE015E03FE015E13FE0C41094004F
+:109D700015E2BFE04403800005E3BFE084008000FB
+:109D800045E3BFE04404800085E3BFE08403800036
+:109D9000C5E3BFE04403800005E4BFE08402800027
+:109DA00045E4BFE0B4008200045FB11015E5BFE0F8
+:109DB00004B5BFE00419C0003A880D183A880B00BA
+:109DC0003A880910408E0880345D9A0084539810B8
+:109DD00015B5BFE074189B00C49B9B1015B6BFE07F
+:109DE00034148E000408911015B7BFE0B44D8D00F7
+:109DF000C40C8E1015B8BFE015B93FE004BABFE03F
+:109E0000040FC0003A880D183A880B003A880910F0
+:109E1000408E088034028000C405801015C9BFE060
+:109E2000C401800005CABFE08402800045CABFE0CB
+:109E30004404800085CABFE0C4008000C5CABFE0FA
+:109E40004400800005CBBFE08400800045CBBFE02C
+:109E5000049CFFE0740182000406A01004190001B4
+:109E60003A880D203A880B103A880918806B0880D0
+:109E70000483FFE074018200041FA0100419000194
+:109E80003A880D203A880B103A880918806B0880B0
+:109E900004E7BFE03A88091040E8178004CEBFE02D
+:109EA0003A88091040E8178004B5BFE03A880910E5
+:109EB00040E81780049CBFE03A88091040E817800A
+:109EC0000483BFE03A88091040E81780035BA0D004
+:109ED000CC3F80103A8837E01701C0DF170000DF61
+:109EE0000402C0DE3A2800F804FDFFDE1502C0DFE0
+:109EF000150100DF040100DF035BA0D0CC3F801020
+:109F00003A880B10740102010438202180C70280B6
+:109F1000C5FF3FE0065D0000C7FFBFE03A880B10B9
+:109F2000740102010447202180C70280C7FFBFE0FF
+:109F3000BA900610B40182003A88851817AEB510A1
+:109F40003A880B1074010201044C202180C7028062
+:109F5000C7FFBFE0BA900610B40182003A888518A6
+:109F600017AEB510171480103A880B107401020157
+:109F70000452202180C70280C7FFBFE0BA900610BC
+:109F8000B40182003A88851817AEB5100315801009
+:109F9000CC3F80103A880B10740102010459202133
+:109FA00080C70280C7FFBFE0BA900610B4018200EC
+:109FB0003A88851817AEB51043158010CC3F801035
+:109FC0003A880B10740102010460202180C70280CE
+:109FD000C7FFBFE0BA900610B40182003A88851826
+:109FE00017AEB51083158010CC3F80103A880B1047
+:109FF000740102010467202180C70280C7FFBFE00F
+:10A00000BA900610B40182003A88851817AEB510D0
+:10A01000C3158010CC3F80103A880B1074010201E8
+:10A02000046E202180C70280C7FFBFE0BA900610EF
+:10A03000B40182003A88851817AEB5100316801057
+:10A04000CC3F80103A880B10740102010474202167
+:10A0500080C70280C7FFBFE0BA900610B40182003B
+:10A060003A88851817AEB51043168010CC3F801083
+:10A070003A880B1074010201047A202180C7028003
+:10A08000C3FFBFE044008010C5FFBFE0C7FFFFE093
+:10A09000035BA0D0CC3F8010169FBF18035BA0D0FD
+:10A0A000CC3F80103A8837E01701C0DF170000DF8F
+:10A0B0000402C0DE3A2800F804FAFFDE1505C0DF0E
+:10A0C000150400DF040400DF15FD3FE015FF3FE04D
+:10A0D00015FC3FE0455B20D0C5FE3FE00692010045
+:10A0E000C7FEBFE02413C010740182000454AE10F8
+:10A0F0003A88851815FCBFE017FCBFE017068010F2
+:10A100002686011017FCBFE0170780102683011078
+:10A11000435BA0D0CC3FC01017FCBFE017008010FD
+:10A120003A880D103A880B1874010201048020212E
+:10A1300080C702800405000180C9428015FDBFE090
+:10A1400017FDBFE01E080010435BA0D0CC3F80107D
+:10A150003A880B1074010201048C202180C7028010
+:10A16000C4FFBF000675010017FCBFE0C3038010E9
+:10A17000CC3F80102612001017FCBFE00304C01073
+:10A1800017FDBFE00500C01074010201049A2021F0
+:10A19000C0D9028017FDBFE003008010CC3F8010C3
+:10A1A0003A880B107401020104A5202180C70280A7
+:10A1B0007401020104B02021C0D90280061F0000F2
+:10A1C00017FCBFE043048010CC3F80102612001023
+:10A1D00017FCBFE08304C01017FDBFE00500C010EE
+:10A1E0007401020104BB2021C0D902807401020164
+:10A1F00004B02021C0D9028017FDBFE00300801009
+:10A20000CC3F80103A880B107401020104C5202154
+:10A2100080C702800609000017FDBFE04400C000AF
+:10A220000500C0107401020104BB2021C0D90280C6
+:10A230007401020104D02021C0D9028085FE3FE0D4
+:10A24000062101000404000180C9428015FFBFE01F
+:10A2500017FFBFE01E0A0010435BA0D0CC3F801068
+:10A2600087FEFFE03A880D183A880B10740102014E
+:10A2700004DA202180C70280C4FFBF00062F01003E
+:10A2800017FFBFE017FDFFE01503C01017FFBFE089
+:10A2900015010010C7FEFFE087FEBFE03A88851871
+:10A2A0002413C010740182000454AE103A88871839
+:10A2B00017FFBFE01502C01017FFBFE017028010A4
+:10A2C000170680102604001017FFBFE01702801049
+:10A2D000170780101E090010C7FEFFE087FEBFE0D1
+:10A2E0003A8885183A880B107401020104EC202189
+:10A2F00080C70280C4FFBF000610010017FFBFE047
+:10A300001702801043038010CC3F8010260D0010F0
+:10A3100017FFBFE01702801083038010CC3F80102E
+:10A320002604001017FFBFE08400C0000500C01025
+:10A330000606000017FFBFE04400C0000500C01083
+:10A340000602000017FFBFE00500001017FFBFE086
+:10A350001702801043048010CC3F80102666001046
+:10A3600017FFBFE017028010C3038010CC3F80109E
+:10A370001E61001087FEFFE017FFBFE0170280108C
+:10A38000170080103A880D103A880B1874010201EA
+:10A3900004FB202180C7028087FE3FE1C7FEFFE06B
+:10A3A00087FEBFE03A8885183A880D103A880B205E
+:10A3B000740102010407212180C7028017FFBFE05A
+:10A3C00003008010CC3F80106000C0101E0C0018ED
+:10A3D000A000C0101E020018261100100618000070
+:10A3E00087FEBFE0740182010416A1313A880B1088
+:10A3F00074010201041B212180C70280061800009D
+:10A4000087FEBFE0740182010426A1313A880B1057
+:10A4100074010201041B212180C702800610000084
+:10A4200087FEBFE074018201042CA1313A880B1031
+:10A4300074010201041B212180C70280060800006C
+:10A4400087FEBFE034018201044D9F313A880B1032
+:10A4500074010201041B212180C702803A88010097
+:10A4600017FFBFE017028010C3048010CC3F80109C
+:10A47000268B001087FEFFE017FFBFE01702801059
+:10A48000C3048010CC3F80102603001074018200AA
+:10A490000433A11006020000740182000434A110EC
+:10A4A0003A880D103A880B187401020104352121F5
+:10A4B00080C7028087FEFFE017FFBFE01702801011
+:10A4C00003058010CC3F8010260300107401820029
+:10A4D0000433A11006020000740182000434A110AC
+:10A4E0003A880D103A880B187401020104402121AA
+:10A4F00080C70280066A000087FEBFE01E4200108F
+:10A5000017FFBFE003008010CC3F80106000C01038
+:10A510001E0A0018A000C0101E020018260D001010
+:10A52000061200007401420104166129740102013F
+:10A53000044B212180C702800612000074014201F1
+:10A540000426612974010201044B212180C7028085
+:10A55000060C000074014201042C612974010201FF
+:10A56000044B212180C7028006060000340142010D
+:10A57000044D5F2974010201044B212180C7028030
+:10A580003A88010017FFBFE017028010C304801053
+:10A59000CC3F8010261C001017FFBFE01702801070
+:10A5A000C3048010CC3F8010260300107401820089
+:10A5B0000433A11006020000740182000434A110CB
+:10A5C0003A880B10740102010456212180C70280D1
+:10A5D00017FFBFE01702801003058010CC3F8010EA
+:10A5E00026030010740182000433A110060200004B
+:10A5F000740182000434A1103A880B107401020126
+:10A600000461212180C7028017FFBFE0170280107C
+:10A61000C3038010CC3F80102613001087FEFFE09C
+:10A6200017FFBFE017028010170080103A880D1046
+:10A630003A880B1874010201046C212180C7028042
+:10A6400087FE3FE1C7FEFFE087FEBFE03A8885183E
+:10A650003A880D103A880B207401020104782121F8
+:10A6600080C70280060E000017FFBFE017028010AF
+:10A67000170080103A880B10740102010487212111
+:10A6800080C70280C7FEFFE087FEBFE03A888518DA
+:10A690003A880B10740102010493212180C70280C3
+:10A6A00087FEBFE017FDFFE044008010BA90041061
+:10A6B0003A88851817FFFFE01500C01083FEBFE041
+:10A6C0004400801085FEBFE087FEFFE017FDBFE07D
+:10A6D00003008010CC3F801016DABE18435BA0D078
+:10A6E000CC3F8010BA90081017FDFFE0B401820043
+:10A6F0003A88852015AAF510435BA0D0440080104D
+:10A70000455BA0D017FDBFE00300C010C3FEBFE053
+:10A710003A888518C4FFBF10C5FEBFE0C3FEBFE086
+:10A7200044008010C5FEBFE0C7FEFFE0030AA0D0D2
+:10A73000CC3F8010166ABE183A8805003A8837E088
+:10A740001701C0DF170000DF0402C0DE3A2800F85E
+:10A7500004EDFFDE1512C0DF151100DF041100DF6C
+:10A7600015F03FE115FF3FE015FD3FE0C5FE3FE07E
+:10A7700015F93FE015F83FE015F73FE017F0BFE0AF
+:10A7800017018010170280101700801015F6BFE027
+:10A7900017F6BFE0041080103700801015F5BFE0F9
+:10A7A00017F03FE140B31880C5F4BFE0C5FC3FE0BF
+:10A7B00006C1000017F6BFE004108010C3FCFFE0E4
+:10A7C0003500C01017F6BFE004A2801037008010DB
+:10A7D00015F3BFE017F6BFE004A380103700801028
+:10A7E00015FFBFE017F3FFE017FFBFE026AF8018AB
+:10A7F0000407000180C9428015F9BFE017F9BFE0E6
+:10A800001E090010C7F4BFE0C7FEFFE03A880D182C
+:10A810003A880B107401020104A2212180C7028032
+:10A82000C4FFBF0006C8000017F9BFE0C3FCFFE08B
+:10A830000500C01017F3BFE0BA91061017FFBFE084
+:10A84000BAD20510CC0F80103AB0841815F2BFE0D0
+:10A8500017FFBFE03AD10510CC0F8010C5F1BFE063
+:10A8600017FFBFE0CC03801085F1BFE0C5FA3FE0E1
+:10A8700015FB3FE0062C000017FBBFE0BA90061066
+:10A88000B40182003A88851817AEB51017148010ED
+:10A8900017F2FFE01E21801817FBBFE0BA900610E8
+:10A8A000B40182003A88851817AEB51003158010E0
+:10A8B000C3F1FFE0CC3F80101E18801817FBBFE0EB
+:10A8C000BA900610B40182003A88851817AEF510C8
+:10A8D00017F9BFE01505C01017FBBFE0BA900610CE
+:10A8E000B40182003A88851817AEB5103A8809106D
+:10A8F000C3FCBFE0C7F4FFE03A880F183A880D1098
+:10A900003A880B207401020104B1212180C7028022
+:10A9100044008000C5FABFE00607000017FBBFE057
+:10A920004400801015FBBFE0035BA0D0CC3F80103B
+:10A9300017FBFFE016D0BF18C3FABFE01E0F0010D0
+:10A9400017F9BFE015050010C3FCBFE0C7F4FFE036
+:10A950003A880D183A880B107401020104C12121B4
+:10A9600080C702807401020104D22121C0D9028073
+:10A9700017FDBFE04400801015FDBFE017F2BFE0F7
+:10A980003A880B107401020104DF212180C7028084
+:10A99000C3F1BFE03A880B107401020104EA2121DF
+:10A9A00080C7028083F1BFE03A880B107401020176
+:10A9B00004F5212180C7028017F97FE117F03FE1FC
+:10A9C00040AA1A801E34001017F9BFE01706801045
+:10A9D00015F8BFE017F8BFE01702801015F7BFE0C9
+:10A9E000150000D84400C001840380013A880B00A0
+:10A9F00017F93FE1C09619804400400117F93FE183
+:10AA0000007F1B804400400117F93FE1409B1B8001
+:10AA10004400400117F93FE180C01B8004C4490194
+:10AA200017F93FE180F11A8017F9BFE01705801090
+:10AA3000260F001017F9BFE01705801017178010B8
+:10AA4000260B001017F9BFE0170580103A880B108D
+:10AA5000740102010400222180C7028017F9BFE0BF
+:10AA6000170580101717801017F63FE13AE83E10DF
+:10AA700017F7BFE0171280102607001074010201BB
+:10AA8000040E2221C0D9028017F7BFE017128010F0
+:10AA900017F63FE13AE83E108402000180CB0280C5
+:10AAA000C3FEBFE044008010C5FEBFE0C3FCBFE0B2
+:10AAB00044008010C5FCBFE017F0BFE00300801029
+:10AAC000C3FCFFE0CC3F8010363ABF1844190001A8
+:10AAD000C030178017F0BFE003008010CC3FC010DB
+:10AAE000C7FEBFE026138018C7FEBFE01E06001099
+:10AAF000C7F4BFE03A880B1074010201041C222144
+:10AB000080C70280060B0000C7F4FFE0C7FE3FE1EC
+:10AB100017F0BFE003008010CC3F80103A880F1080
+:10AB20003A880D203A880B1874010201042822216A
+:10AB300080C7028017F6BFE00410801017F5FFE011
+:10AB40003500C01017FDBFE03A8837E01701C0DFBD
+:10AB5000170000DF0402C0DE3A2800F804F6FFDE2A
+:10AB60001509C0DF150800DF040800DF15F93FE113
+:10AB700015F87FE115FD3FE015FC3FE015FB3FE0D8
+:10AB8000C5FA3FE017F93FE140B3188085FABFE00E
+:10AB900045FA3FE0C5FF3FE015FE3FE0062B000011
+:10ABA00017F9FFE017FEBFE044008010BA900410D0
+:10ABB0003A8885181700801015FBBFE017FBBFE02F
+:10ABC0001702801015FCBFE017FCBFE01711C01082
+:10ABD00017F8BFE003008010CC3F80101E188018CB
+:10ABE00017FB3FE100BA1880C5FABFE017FC3FE150
+:10ABF00080AC188045FABFE017FBBFE017F8FFE014
+:10AC00001501C01017F8BFE017FBFFE01506C010D4
+:10AC100087FABFE0C7FAFFE047FA3FE13A880F2022
+:10AC20003A880D183A880B1074010201044722215A
+:10AC300080C7028044008000C5FFBFE00608000016
+:10AC400017FEBFE04400801015FEBFE017F9BFE01B
+:10AC500003008010CC3F801017FEFFE016D0BF1815
+:10AC6000C3FFBFE01E3C001015FE3FE006350000AC
+:10AC700017F9FFE017FEBFE044008010BA900410FF
+:10AC80003A8885181700801015FBBFE017FBBFE05E
+:10AC90001702801015FCBFE017FCBFE017068010FC
+:10ACA0002624001017FCBFE0170780102621001093
+:10ACB00017FCBFE017118010D8FFBF101E1E001038
+:10ACC00017FB3FE100BA1880C5FABFE017FC3FE16F
+:10ACD00080AC188045FABFE017FBBFE017F8FFE033
+:10ACE0001501C01017F8BFE017FBFFE01506C010F4
+:10ACF00017F8BFE003008010CC3FC01017FCBFE086
+:10AD00001511C01087FABFE0C7FAFFE047FA3FE12C
+:10AD10003A880F203A880D183A880B107401020106
+:10AD20000457222180C7028044008000C5FFBFE095
+:10AD3000060900003A88010017FEBFE044008010B9
+:10AD400015FEBFE017F9BFE003008010CC3F801074
+:10AD500017FEFFE016C6BF18C3FFBFE01E090010B4
+:10AD600017F8BFE01506001087FABFE03A880B100D
+:10AD7000740102010468222180C70280C4FFBF0061
+:10AD800015FDBFE017FDBFE03A8837E01701C0DFCF
+:10AD9000170000DF0402C0DE3A2800F804F8FFDEE6
+:10ADA0001507C0DF150600DF040600DF15FA3FE1D6
+:10ADB00017FABFE01702801015FDBFE017FDBFE0D6
+:10ADC0001700801015FFBFE017FABFE017038010CF
+:10ADD00015FEBFE017FA3FE100BA1880C5FCBFE0DE
+:10ADE00017FE3FE140B3188085FCBFE017FDBFE0D0
+:10ADF000C3048010CC3F8010262C001087FCBFE0DD
+:10AE0000C7FCFFE03A880D183A880B107401020164
+:10AE10000499222180C7028017FFBFE004808010C0
+:10AE2000041480103700801015FBBFE017FDBFE051
+:10AE300003058010CC3F8010260E001087FCBFE079
+:10AE4000C7FCFFE03A880D183A880B107401020124
+:10AE500004A7222180C7028017FFBFE00480801072
+:10AE60000414801017FBFFE0D400C0183500C01098
+:10AE7000060E000087FCBFE0C7FCFFE03A880D1813
+:10AE80003A880B107401020104B3222180C70280AA
+:10AE900017FFBFE0048080100414801017FB3FE10F
+:10AEA00004FFFF003A70C6203500C0103A88050044
+:10AEB0003A8837E01701C0DF170000DF0402C0DE68
+:10AEC0003A2800F804FBFFDE1504C0DF150300DF9D
+:10AED000040300DFC5FF3FE085FF3FE015FE3FE0D4
+:10AEE00015FD3FE080B6198000E3198000001A804C
+:10AEF000C5FF3FE0062C0000C7FFBFE0BA90061078
+:10AF0000B40182003A88851817AAB51015FEBFE073
+:10AF100017FEBFE017018010170280100303801096
+:10AF2000CC3F80102603001017FE3FE180691A8095
+:10AF300006070000C7FFBFE087FFFFE03A880D1853
+:10AF40003A880B107401020104BF222180C70280DD
+:10AF500085FF3FE0060C000087FFBFE017FEFFE023
+:10AF600044008010BA9004103A88851817008010A9
+:10AF700015FDBFE017FD3FE140CE1A8083FFBFE023
+:10AF80004400801085FFBFE087FFFFE017FEBFE0B1
+:10AF900003008010CC3F801016EFBF18C3FFBFE046
+:10AFA00044008010C5FFBFE0C7FFFFE0435BA0D0B7
+:10AFB000CC3F801016D0BF183A8805003A8837E099
+:10AFC0001701C0DF170000DF0402C0DE3A2800F8D6
+:10AFD00004F7FFDE1508C0DF150700DF040700DFF8
+:10AFE00015FB3FE115FA7FE117FBBFE01706801064
+:10AFF00015FFBFE017FFBFE01703801015FEBFE08D
+:10B0000017FF3FE100BA1880C5FCBFE017FE3FE123
+:10B0100040B3188085FCBFE017FB3FE1C08C19806E
+:10B0200045FCBFE017FBBFE003008010CC3F801061
+:10B030003A880B1017FB3FE1409119804400C00192
+:10B04000C40080014400400117FB3FE180A9198042
+:10B050001E0D001087FCBFE0C7FCFFE03A880D180A
+:10B060003A880B107401020104D5222180C70280A6
+:10B0700043FCBFE03A880B1017FB3FE14091198079
+:10B0800084FFBF00063E000044008000150080D809
+:10B090004400C001040380013A880B0017FB3FE124
+:10B0A000C096198044008000150080D84400C0017B
+:10B0B000440280013A880B0017FB3FE1C0961980DB
+:10B0C00087FCBFE0C7FCFFE03A880D183A880B10F8
+:10B0D0007401020104E5222180C7028015FD3FE0D2
+:10B0E0000615000017FDBFE04400C01015FDFFE08D
+:10B0F0003A88071017FABFE02E0DC01087FCBFE09A
+:10B10000C7FCFFE03A880D183A880B107401020161
+:10B1100004F7222180C7028043FCBFE03A880B106D
+:10B1200017FB3FE140911980C4FFBF0006140000E7
+:10B1300004FA0001C01138804400C00144018001BC
+:10B140004400400117FB3FE180A9198026E53F102C
+:10B1500087FCBFE0C7FCFFE03A880D183A880B1067
+:10B16000740102010403232180C7028043FCBFE075
+:10B170003A880B1017FB3FE1409119803A8805008F
+:10B180003A8837E01701C0DF170000DF0402C0DE95
+:10B190003A2800F804F8FFDE1507C0DF150600DFC7
+:10B1A000040600DF15FB3FE115FA7FE115FF3FE0E4
+:10B1B00017FBBFE01706801015FEBFE017FEBFE0CB
+:10B1C0001703801015FDBFE017FE3FE100BA18809D
+:10B1D000C5FCBFE017FD3FE140B3188085FCBFE030
+:10B1E00017FB3FE1C08C198045FCBFE017FBBFE0B7
+:10B1F00003008010CC3F80103A880B1017FB3FE112
+:10B200004091198087FCBFE0C7FCFFE03A880D1829
+:10B210003A880B1074010201040F232180C70280B9
+:10B220000621000017FFBFE04400C01015FFFFE03B
+:10B230003A88071017FABFE02E19C01087FCBFE04C
+:10B24000C7FCFFE03A880D183A880B107401020120
+:10B25000041A232180C7028017FA7FE117FB3FE120
+:10B2600080F11A80D8FFBF101E0D001087FCBFE0D0
+:10B27000C7FCFFE03A880D183A880B1074010201F0
+:10B28000042E232180C7028043FCBFE03A880B10C4
+:10B2900017FB3FE140911980C4FFBF00061A000070
+:10B2A00004FA0001C01138804400C0018403800109
+:10B2B0003A880B0017FB3FE180A919801ED93F1087
+:10B2C0004400C001440180014400400117FB3FE1FC
+:10B2D00080A9198026D33F1087FCBFE0C7FCFFE0A0
+:10B2E0003A880D183A880B1074010201043B23219F
+:10B2F00080C7028043FCBFE03A880B1017FB3FE198
+:10B30000409119803A8805003A8837E01701C0DF7C
+:10B31000170000DF0402C0DE3A2800F804F9FFDE5F
+:10B320001506C0DF150500DF040500DF15FB3FE152
+:10B3300015FF3FE017FBBFE01706801015FDBFE0CB
+:10B3400017FDBFE01703801015FCBFE017FD3FE1BC
+:10B3500000BA188045FEBFE017FC3FE140B31880FB
+:10B3600085FEBFE017FB3FE1C08C1980C5FEBFE042
+:10B3700017FBBFE003008010CC3F80103A880B1011
+:10B3800017FB3FE1409119804400C001C4008001D7
+:10B390004400400117FB3FE180A919801E0D0010F9
+:10B3A00087FEBFE047FEFFE03A880D183A880B1091
+:10B3B0007401020104D5222180C70280C3FEBFE0D0
+:10B3C0003A880B1017FB3FE14091198084FFBF00C2
+:10B3D000063001000471420117FB3FE180F11A8041
+:10B3E0004400C001440180014400400117FB3FE1DB
+:10B3F00080A919801E020010C4FFBF0015FFBFE026
+:10B400004400C001C4038001C403400117FB3FE1B5
+:10B4100080A919803A88071017FBBFE04500C010CB
+:10B420004400C00184038001C403400117FB3FE1D5
+:10B4300080A919803A88071017FBBFE08500C0106B
+:10B440004400C00144038001C403400117FB3FE1F5
+:10B4500080A919803A88071017FBBFE0C500C0100B
+:10B460004400C00104038001C403400117FB3FE115
+:10B4700080A919803A88071017FBBFE00501C010AA
+:10B480004400C001C40380014400400117FB3FE1B8
+:10B4900080A919803A88071017FBBFE04501C0104A
+:10B4A0004400C001840380014400400117FB3FE1D8
+:10B4B00080A919803A88071017FBBFE08501C010EA
+:10B4C0004400C001440380014400400117FB3FE1F8
+:10B4D00080A919803A88071017FBBFE0C501C0108A
+:10B4E0004400C001840280014400400117FB3FE199
+:10B4F00080A919803A88071017FBBFE00502C01029
+:10B500004400C001440280014400400117FB3FE1B8
+:10B5100080A919803A88071017FBBFE04502C010C8
+:10B520004400C001040380014400400117FB3FE1D7
+:10B5300080A919803A88071017FBBFE08502C01068
+:10B540004400C001C40280014400400117FB3FE1F8
+:10B5500080A919803A88071017FBBFE0C502C01008
+:10B560004400C001C40280018402400117FB3FE196
+:10B5700080A919803A88071017FBBFE00503C010A7
+:10B580004400C001840280018402400117FB3FE1B6
+:10B5900080A919803A88071017FBBFE04503C01047
+:10B5A0004400C001440280014401400117FB3FE117
+:10B5B00080A919803A88071017FBBFE08503C010E7
+:10B5C0004400C001040280014401400117FB3FE137
+:10B5D00080A919803A88071017FBBFE0C503C01087
+:10B5E0004400C001C40180014401400117FB3FE158
+:10B5F00080A919803A88071017FBBFE00504C01026
+:10B600004400C001840180014401400117FB3FE177
+:10B6100080A919803A88071017FBBFE04504C010C5
+:10B620004400C001440180014401400117FB3FE197
+:10B6300080A919803A88071017FBBFE08504C01065
+:10B6400087FEBFE047FEFFE03A880D183A880B10EE
+:10B65000740102010446232180C7028017FBBFE06A
+:10B6600043008010CC3F80103A880B107401020117
+:10B670000451232180C7028017FBBFE083008010A4
+:10B68000CC3F80103A880B1074010201045B232127
+:10B6900080C7028017FBBFE0C3008010CC3F801042
+:10B6A0003A880B10740102010465232180C70280CF
+:10B6B00017FBBFE003018010CC3F80103A880B10CD
+:10B6C00074010201046F232180C7028017FBBFE0D1
+:10B6D00043018010CC3F80103A880B1074010201A6
+:10B6E0000479232180C7028017FBBFE0830180100B
+:10B6F000CC3F80103A880B1074010201048323218F
+:10B7000080C7028017FBBFE0C3018010CC3F8010D0
+:10B710003A880B1074010201048D232180C7028036
+:10B7200017FBBFE003028010CC3F80103A880B105B
+:10B73000740102010497232180C7028017FBBFE038
+:10B7400043028010CC3F80103A880B107401020134
+:10B7500004A1232180C7028017FBBFE08302801071
+:10B76000CC3F80103A880B107401020104AB2321F6
+:10B7700080C7028017FBBFE0C3028010CC3F80105F
+:10B780003A880B107401020104B5232180C702809E
+:10B790008402000180CB028087FEBFE047FEFFE00D
+:10B7A0003A880D183A880B107401020104BF232156
+:10B7B00080C7028017FBBFE003038010CC3F8010DE
+:10B7C0003A880B10740102010465232180C70280AE
+:10B7D00017FBBFE043038010CC3F80103A880B106A
+:10B7E00074010201046F232180C7028017FBBFE0B0
+:10B7F00083038010CC3F80103A880B107401020143
+:10B800000479232180C7028017FBBFE0C3038010A7
+:10B81000CC3F80103A880B107401020104CC232124
+:10B8200080C7028017FBBFE003048010CC3F80106C
+:10B830003A880B107401020104D6232180C70280CC
+:10B8400017FBBFE043048010CC3F80103A880B10F8
+:10B850007401020104E0232180C7028017FBBFE0CE
+:10B8600083048010CC3F80103A880B1074010201D1
+:10B8700004EA232180C702808402000180CB028079
+:10B88000C3FEBFE03A880B1017FB3FE140911980DF
+:10B8900017FFBFE03A8837E01701C0DF170000DF6D
+:10B8A0000402C0DE3A2800F804F6FFDE1509C0DF06
+:10B8B000150800DF040800DF15FA3FE13A88052883
+:10B8C00005F9BFE017FABFE01706801015FCBFE0CE
+:10B8D00017FCBFE01703801015FEBFE017FC3FE127
+:10B8E00000BA1880C5FDBFE017FE3FE140B31880E5
+:10B8F000C5FFBFE017FA3FE1C08C1980C5FBBFE070
+:10B9000017FABFE003008010CC3F80103A880B107C
+:10B9100017FA3FE14091198003F9BFE0262D00108E
+:10B920004400C00144038001C403400117FA3FE111
+:10B9300080A9198085FBBFE083FBBFE0150080D89C
+:10B940004400C001440280014402400117FA3FE173
+:10B95000C0961980C7FFBFE0C7FDFFE083FB3FE152
+:10B960003A880F203A880D183A880B1074010201AA
+:10B9700004F4232180C702804400C0010403800135
+:10B98000C403400117FA3FE180A9198085FBBFE09D
+:10B9900083FBBFE0150080D84400C0010402800191
+:10B9A0004402400117FA3FE1C0961980C7FFBFE08B
+:10B9B000C7FDFFE083FB3FE13A880F203A880D186E
+:10B9C0003A880B10740102010407242180C7028009
+:10B9D000061C0000150000D84400C001440280018C
+:10B9E0004402400117FA3FE1C0961980C7FFBFE04B
+:10B9F000C7FDFFE03A880F003A880D183A880B100F
+:10BA00007401020104F4232180C70280150000D8CC
+:10BA10004400C001040280014402400117FA3FE1E2
+:10BA2000C0961980C7FFBFE0C7FDFFE03A880F004E
+:10BA30003A880D183A880B1074010201041A242167
+:10BA400080C70280C3FBBFE03A880B1017FA3FE1C2
+:10BA5000409119803A8805003A8837E01701C0DF25
+:10BA6000170000DF0402C0DE3A2800F804F8FFDE09
+:10BA70001507C0DF150600DF040600DF15FC3FE1F7
+:10BA80003A88052805FBBFE017FCBFE017068010C9
+:10BA900015FDBFE017FDBFE01703801015FEBFE0E6
+:10BAA00017FD3FE100BA188045FFBFE017FE3FE1F8
+:10BAB00040B3188005FFBFE017FC3FE1C08C198040
+:10BAC00085FFBFE017FCBFE003008010CC3F801073
+:10BAD0003A880B1017FC3FE14091198003FBBFE04F
+:10BAE000264300104400C001C4038001440040010B
+:10BAF00017FC3FE180A91980C5FFBFE0C3FFBFE08D
+:10BB0000150080D84400C0014402800104014001B6
+:10BB100017FC3FE1C096198007FFBFE047FFFFE039
+:10BB2000C3FF3FE13A880F203A880D183A880B107E
+:10BB300074010201042C242180C702804400C0014A
+:10BB4000840380014400400117FC3FE180A9198073
+:10BB5000C5FFBFE0C3FFBFE0150080D84400C001AF
+:10BB6000040280010401400117FC3FE1C0961980E6
+:10BB700007FFBFE047FFFFE0C3FF3FE13A880F2028
+:10BB80003A880D183A880B1074010201043C2421F4
+:10BB900080C702804400C00144038001440040018A
+:10BBA00017FC3FE180A91980C5FFBFE0C3FFBFE0DC
+:10BBB000150080D84400C001C40180010401400187
+:10BBC00017FC3FE1C096198007FFBFE047FFFFE089
+:10BBD000C3FF3FE13A880F203A880D183A880B10CE
+:10BBE00074010201044F242180C70280062A00004C
+:10BBF000150000D84400C001440280010401400146
+:10BC000017FC3FE1C096198007FFBFE047FFFFE048
+:10BC10003A880F003A880D183A880B107401020117
+:10BC2000042C242180C70280150000D84400C001E4
+:10BC3000040280010401400117FC3FE1C096198015
+:10BC400007FFBFE047FFFFE03A880F003A880D1872
+:10BC50003A880B1074010201043C242180C7028041
+:10BC6000150000D84400C001C40180010401400156
+:10BC700017FC3FE1C096198007FFBFE047FFFFE0D8
+:10BC80003A880F003A880D183A880B1074010201A7
+:10BC9000044F242180C7028083FFBFE03A880B1045
+:10BCA00017FC3FE1409119803A8805003A8837E057
+:10BCB0001701C0DF170000DF0402C0DE3A2800F8D9
+:10BCC00004F5FFDE150AC0DF150900DF040900DFF7
+:10BCD00015F93FE13A88052805F8BFE017F9BFE0FC
+:10BCE0001706801015FFBFE017FFBFE01703801095
+:10BCF00015FEBFE017FF3FE100BA188015FDBFE059
+:10BD000017FE3FE140B3188015FCBFE017F93FE193
+:10BD1000C08C198015FBBFE017F9BFE0030080104D
+:10BD2000CC3F80103A880B1017F93FE14091198001
+:10BD300003F8BFE0262900104400C001040380017D
+:10BD40004400400117F93FE180A91980C5FABFE01E
+:10BD5000C3FABFE0150080D84400C001840180010F
+:10BD60000401400117F93FE1C0961980C3FABFE012
+:10BD70003A880F1017FDBFE117FC7FE17401020143
+:10BD80000462242180C702804400C001C4028001F3
+:10BD90004400400117F93FE180A91980C5FABFE0CE
+:10BDA000C3FABFE0150080D84400C00144018001FF
+:10BDB0000401400117F93FE1C0961980C3FABFE0C2
+:10BDC0003A880F1017FDBFE117FC7FE174010201F3
+:10BDD0000475242180C7028006180000150000D8D1
+:10BDE0004400C001840180010401400117F93FE1D2
+:10BDF000C09619803A880F0017FDBFE117FC7FE15C
+:10BE0000740102010462242180C70280150000D859
+:10BE10004400C001440180010401400117F93FE1E1
+:10BE2000C09619803A880F0017FDBFE117FC7FE12B
+:10BE3000740102010475242180C7028017FBBFE052
+:10BE4000CC3F80103A880B1017F93FE140911980E0
+:10BE50003A8805003A8837E01701C0DF170000DF95
+:10BE60000402C0DE3A2800F804F5FFDE150AC0DF40
+:10BE7000150900DF040900DF15F73FE144008000E9
+:10BE8000C5FFBFE044008000C5FDBFE04400800066
+:10BE900085FDBFE044008000C5FBBFE015FA3FE030
+:10BEA00015F93FE017F73FE140B31880C5F8BFE050
+:10BEB00015FE3FE0061A000017F7FFE017FEBFE08F
+:10BEC00044008010BA9004103A888518170080103A
+:10BED00015FABFE017FABFE01701801015F9BFE0AF
+:10BEE00017F9BFE0260900104400400117F93FE1AF
+:10BEF000007F1B804400400117F93FE1409B1B80FD
+:10BF00004400400117F93FE180C01B80840200011A
+:10BF100080CB028017FEBFE04400801015FEBFE01A
+:10BF200017F7BFE003008010CC3F801017FEFFE042
+:10BF300016E1BF1815FE3FE00655000017F7FFE0B9
+:10BF400017FEBFE044008010BA9004103A888518AC
+:10BF50001700801015FABFE017FABFE01701801034
+:10BF600015F9BFE017F9BFE02643001017F93FE1CC
+:10BF700040261B801E420010C5FB3FE017FABFE0C1
+:10BF800003008010CC3F8010580080101E0200106B
+:10BF9000C5FF3FE00607000017FABFE0030080106E
+:10BFA000CC3F8010980080101E020010C5FD3FE0BD
+:10BFB00085FD3FE017F9BFE0C300C01017F9BFE0EF
+:10BFC000030380103A7084183A880710C3FFBFE05B
+:10BFD0003A70C410C5FFBFE017F9BFE08301C0107D
+:10BFE00017F9BFE0C30380103A7084183A8809102B
+:10BFF00017F9BFE0C301C01017F9BFE003048010B8
+:10C000003A7084183AB084203A88091017F9BFE0D2
+:10C010004301C01017F9BFE0830380103A70841801
+:10C020003AB084203A880710C3FDBFE03A70C410CC
+:10C03000C5FDBFE017F9BFE08302C01017F9BFE0EC
+:10C04000430480103A7084183A88091017F9BFE049
+:10C05000C302C01017F9BFE0830480103A7084183F
+:10C060003AB084203A88071083FDBFE03A70C410CC
+:10C0700085FDBFE0060300003A88010006010000CC
+:10C080003A88010017FEBFE04400801015FEBFE0B3
+:10C0900017F7BFE003008010CC3F801017FEFFE0D1
+:10C0A00016A6BF18C3FBBFE0580080101E08001082
+:10C0B000C4FFBF0015FCBFE0C7F8BFE03A880B1013
+:10C0C000740102010488242180C702800627000031
+:10C0D000C3FFBFE0260900108400800015FCBFE00C
+:10C0E000C7F8BFE004FA80013A880B10740102011E
+:10C0F000049A242180C70280061C0000C3FDBFE013
+:10C10000260900104400800015FCBFE0C7F8BFE01E
+:10C11000041980013A880B1074010201049A242149
+:10C1200080C702800611000083FDBFE026080010D2
+:10C1300015FC3FE0C7F8BFE0840280013A880B108D
+:10C1400074010201049A242180C7028006070000BE
+:10C15000C4FFBF0015FCBFE0C7F8BFE03A880B1072
+:10C160007401020104A7242180C7028017FCBFE0EC
+:10C170003A8837E01701C0DF170000DF0402C0DE95
+:10C180003A2800F804F0FFDE150FC0DF150E00DFBF
+:10C19000150D40DC150C00DC040E00DF15F43FE14A
+:10C1A00015F37FE115FB3FE015FA3FE015F93FE09D
+:10C1B000C5F83FE017F43FE140B3188085F8BFE0D1
+:10C1C00017F4BFE0170180101702801017008010CD
+:10C1D00015F7BFE017F7BFE004108010370080109C
+:10C1E00015F6BFE017F3BFE01603001017F3BFE02A
+:10C1F000D00080101E0C001087F8BFE017F3BFE1DD
+:10C200003A880B107401020104B4242180C7028013
+:10C2100017F7BFE00410801017F6FFE03500C010DC
+:10C22000C4FFBF0006FC000015FC3FE006DA00007A
+:10C2300017F4FFE017FCBFE044008010BA90041030
+:10C240003A8885181700801015FABFE017FA3FE109
+:10C2500000BA1880C5F8BFE017FABFE017018010D8
+:10C2600015FBBFE017FBBFE026C7001017FABFE0C1
+:10C270001702801015F9BFE017FBBFE00300801024
+:10C28000CC3F80103A880B1017FB3FE1409119809A
+:10C2900017FBBFE0C3008010CC3F80101E0C0010C5
+:10C2A00017FBBFE003018010CC3F80101E08001078
+:10C2B00017FBBFE043008010CC3F80101E0400102D
+:10C2C00017FBBFE083008010CC3F801026020010D7
+:10C2D00044008000060100003A880500C5F5BFE073
+:10C2E000C3F5BFE01E10001017F3BFE098008010E8
+:10C2F0001E0D001087F8BFE0C7F8FFE03A880D1860
+:10C300003A880B107401020104C8242180C70280FE
+:10C3100017F7BFE00410801017F6FFE03500C010DB
+:10C32000C4FFBF0006BC00004400C001C40080017F
+:10C330004400400117FB3FE180A919801E14001042
+:10C34000C3F5BFE02609001017F3BFE07AD005104F
+:10C35000CCFFBF10150080D84400C00184018001CB
+:10C360003A880B0017FB3FE1C096198017F3BFE036
+:10C37000CCFFBF10150080D84400C00144038001E9
+:10C380003A880B0017FB3FE1C0961980067F00003A
+:10C3900017F3BFE0980080101E0A0010440040010F
+:10C3A00017FB3FE1007F1B804400400117FB3FE18A
+:10C3B000409B1B804400400117FB3FE180C01B8075
+:10C3C0000622000017F3BFE0580080101E0A00107C
+:10C3D0003A880B0017FB3FE1007F1B8044004001BF
+:10C3E00017FB3FE1409B1B804400400117FB3FE1EE
+:10C3F00080C01B800615000017F3BFE01E0A001066
+:10C400003A880B0017FB3FE1007F1B803A880B0046
+:10C4100017FB3FE1409B1B804400400117FB3FE1BD
+:10C4200080C01B80060900003A880B0017FB3FE123
+:10C43000007F1B803A880B0017FB3FE1409B1B806D
+:10C440003A880B0017FB3FE180C01B804400C0010D
+:10C45000440180014400400117FB3FE180A919809D
+:10C46000580080101E3A0010C3F5BFE0260F0010E0
+:10C4700017FBBFE01705801083158010CC3FC0105C
+:10C4800017FBBFE017058010C3158010CC3F80104C
+:10C490008400C0013A880D103A880B1817FB3FE161
+:10C4A00080A91980C5FDBFE0060E000017FBBFE0A4
+:10C4B0001705801083158010CC3FC01017FBBFE01C
+:10C4C00017058010C3158010CC3F80104400C001B8
+:10C4D0003A880D103A880B1817FB3FE180A91980A4
+:10C4E000C5FDBFE0C3FDBFE017F3FFE026038018E2
+:10C4F0000471420117FB3FE180F11A8017FBBFE096
+:10C500001705801083158010CC3FC01017FBBFE0CB
+:10C510001705801003168010CC3F80104400C00126
+:10C520003A880D103A880B1817FB3FE180A9198053
+:10C5300085F5BFE017F9BFE0170080103A880710B3
+:10C5400083F5BFE03A880B103A88091880DC188020
+:10C5500087F83FE4C7F87FE40404C0013A880D007F
+:10C560004400400117FB3FE180A919803A880F1071
+:10C570003A880D883A880B807401020104DF242177
+:10C5800080C70280060100003A88010017FCBFE066
+:10C590004400801015FCBFE017F4BFE003008010DA
+:10C5A000CC3F801017FCFFE01621BF1887F8FFE092
+:10C5B00017F3BFE0A00080101E07001017F3BFE0C4
+:10C5C000580080101E0200100419800006030000AD
+:10C5D000840280000601000004FA80003A880D10F1
+:10C5E0003A880B187401020104EB242180C70280F1
+:10C5F00017F3BFE0CC3F80103A880B1017F73FE1EC
+:10C6000080CE188017F7BFE00410801017F6FFE007
+:10C610003500C01017F3BFE004FEFFE61703C0DFCC
+:10C62000170200DF170140DC170000DC0404C0DE45
+:10C630003A2800F804FCFFDE1503C0DF150200DF16
+:10C64000040200DF15FE3FE117FEBFE004A18010E9
+:10C65000370080100C0880101E16001074010201B3
+:10C6600004FC2421C0D9028017FEBFE004A0801082
+:10C6700004108010041EC0003500C01074010201B7
+:10C6800004052521C0D9028017FEBFE004A0801058
+:10C69000370080108DFFBFE017FEBFE004A08010C0
+:10C6A0008BFF3FE10400E0003AB0C620CCFFFF184A
+:10C6B0003500C0103A8805003A8837E01701C0DF1E
+:10C6C000170000DF0402C0DE3A2800F804FCFFDE99
+:10C6D0001503C0DF150200DF040200DF15FE3FE195
+:10C6E00017FEBFE004BB8010370080108DFFBFE055
+:10C6F0008BFFFFE004FCBF003A7084188DFFBFE0A1
+:10C7000074010201040A2521C0D9028017FEBFE08E
+:10C7100004BB80108BFFFFE0D403C018CCFFFF18D0
+:10C720003500C0107401020104162521C0D9028011
+:10C7300017FEBFE004B48010370080108DFFBFE00B
+:10C740008BFFFFE044DFBF003A7084188DFFBFE02D
+:10C7500017FEBFE004B480108BFFFFE03500C0106F
+:10C760007401020104052521C0D9028017FEBFE033
+:10C7700004A08010370080108DFFBFE017FEBFE0DF
+:10C7800004A080108BFF3FE10400E0003AB0C62017
+:10C79000CCFFFF183500C010440080003A8837E015
+:10C7A0001701C0DF170000DF0402C0DE3A2800F8DE
+:10C7B00004FCFFDE1503C0DF150200DF040200DF0A
+:10C7C00015FE3FE117FEBFE004BB8010370080106C
+:10C7D0008DFFBFE08BFFFFE004FCBF003A708418C0
+:10C7E0008DFFBFE07401020104202521C0D9028021
+:10C7F00017FEBFE004BB80108BFFFFE01401C018E0
+:10C80000CCFFFF183500C010740102010416252169
+:10C81000C0D9028017FEBFE004B48010370080103A
+:10C820008DFFBFE08BFFFFE044DFBF003A7084184C
+:10C830008DFFBFE017FEBFE004B480108BFFFFE068
+:10C840003500C0107401020104052521C0D9028001
+:10C8500017FEBFE004A08010370080108DFFBFE0FE
+:10C8600017FEBFE004A080108BFF3FE10400E00052
+:10C870003AB0C620CCFFFF183500C010440080003D
+:10C880003A8837E01701C0DF170000DF0402C0DE7E
+:10C890003A2800F804FCFFDE1503C0DF150200DFB4
+:10C8A000040200DF15FE3FE117FEBFE004BB80106D
+:10C8B000370080108DFFBFE08BFFFFE004FCBF005E
+:10C8C0003A7084188DFFBFE0740102010435252100
+:10C8D000C0D9028017FEBFE004BB80108BFFFFE0D1
+:10C8E000D402C018CCFFFF183500C010740102013B
+:10C8F00004442521C0D9028017FEBFE004B4801093
+:10C90000370080108DFFBFE08BFFFFE044DFBF00EA
+:10C910003A7084188DFFBFE08BFFBFE09420801039
+:10C920008DFFBFE017FEBFE004B480108BFFFFE077
+:10C930003500C0107401020104052521C0D9028010
+:10C9400017FEBFE004A08010370080108DFFBFE00D
+:10C9500017FEBFE004A080108BFF3FE10400E00061
+:10C960003AB0C620CCFFFF183500C010440080004C
+:10C970003A8837E01701C0DF170000DF0402C0DE8D
+:10C980003A2800F804FCFFDE150300DF040300DF93
+:10C9900015FD3FE115FF3FE017FDBFE004B080103B
+:10C9A0003700801015FEBFE017FEBFE08C0080103E
+:10C9B0002604001017FFBFE01402801015FFBFE02F
+:10C9C0000603000017FFBFE01401801015FFBFE051
+:10C9D00017FEBFE00C0180102603001017FFBFE018
+:10C9E0005400801015FFBFE017FFBFE03A8837E022
+:10C9F000170000DF0401C0DE3A2800F804FDFFDE66
+:10CA0000150200DF040200DF15FE3FE117FEBFE064
+:10CA100004B48010370080108DFFBFE08BFFBFE0B3
+:10CA2000CCFF8F108DFFBFE08BFFBFE01440801064
+:10CA30008DFFBFE017FEBFE004B480108BFFFFE066
+:10CA40003500C0103A8805003A8837E0170000DF4B
+:10CA50000401C0DE3A2800F804FCFFDE150300DF05
+:10CA6000040300DF15FD3FE115FF3FE017FDBFE0C8
+:10CA700004B880103700801015FEBFE017FEBFE03D
+:10CA8000CC0080101E03001017FFBFE014028010BE
+:10CA900015FFBFE017FEBFE0CC00801058008010EB
+:10CAA0001E03001017FFBFE01401801015FFBFE048
+:10CAB00017FEBFE0CC008010980080101E0300100D
+:10CAC00017FFBFE09400801015FFBFE017FEBFE026
+:10CAD0000C0280102603001017FFBFE054008010E6
+:10CAE00015FFBFE017FFBFE03A8837E0170000DF0F
+:10CAF0000401C0DE3A2800F804FAFFDE1505C0DFA5
+:10CB0000150400DF040400DF15FE3FE115FD7FE1A1
+:10CB100015FCBFE117FEBFE01700801015FFBFE056
+:10CB200017FFBFE0040AC01017FEBFE01702801015
+:10CB30003A880F1017FCBFE117FD7FE13A8809180A
+:10CB4000000B1D803A8837E01701C0DF170000DFB7
+:10CB50000402C0DE3A2800F804FAFFDE1505C0DF43
+:10CB6000150400DF040400DF15FE3FE115FD7FE141
+:10CB700015FCBFE117FEBFE01700801015FFBFE0F6
+:10CB800017FFBFE0040AC01017FEBFE017028010B5
+:10CB90003A880F1017FCBFE117FD7FE13A880918AA
+:10CBA00040351D803A8837E01701C0DF170000DFED
+:10CBB0000402C0DE3A2800F804FCFFDE1503C0DFE3
+:10CBC000150200DF040200DF15FE3FE117FEBFE0A3
+:10CBD0001700801015FFBFE017FFBFE0040AC01068
+:10CBE00017FEBFE0170280103A880B103A88091828
+:10CBF00000021D803A8837E01701C0DF170000DF10
+:10CC00000402C0DE3A2800F804F2FFDE150DC0DF92
+:10CC1000150C00DF040C00DF15F73FE115F67FE18E
+:10CC200015F5BFE117F7BFE01700801015FFBFE053
+:10CC300017F7BFE00407801015FDBFE08DFC3FE053
+:10CC40008BFCBFE044F8FFE03A880B183A880910E3
+:10CC500080E711803A88071017FDBFE01500C0106B
+:10CC600043F8BFE0CC3F80101E24001017F7BFE050
+:10CC70000408801015FBBFE0440080008DFABFE07F
+:10CC80008BFABFE03A880910407715803A88071080
+:10CC900017FBBFE01500C01017FBBFE017008010A6
+:10CCA000260200103A88050006010000C4FFBF00FC
+:10CCB0001E12001017F7BFE00409801015F9BFE03D
+:10CCC000440080008DF8BFE08BF8BFE03A8809107F
+:10CCD000407715803A88071017F9BFE01500C0109B
+:10CCE00017F9BFE017008010260200103A880500EF
+:10CCF00006010000C4FFBF002602001044008000AF
+:10CD0000060100003A88050015FEBFE017FEBFE0EF
+:10CD10001E0F001017F7BFE00420C3001501C0105C
+:10CD200017FFBFE00403801017F7FFE01701C018DA
+:10CD30003500C010150000D817F7FFE1B4008201DC
+:10CD4000042CB33117F57FE117F63FE140493780F6
+:10CD50003A8801003A8837E01701C0DF170000DF8A
+:10CD60000402C0DE3A2800F804FAFFDE1505C0DF31
+:10CD7000150400DF040400DF15FC3FE117FCBFE0F1
+:10CD800015FFBFE017FFBFE01700801015FEBFE0E2
+:10CD900017FEBFE0040280103700801015FDBFE0D1
+:10CDA00017FEBFE0040280103A8807003500C0106B
+:10CDB00017FEBFE0040280103700801017FDBFE0AF
+:10CDC0000C2080102603001017FD7FE117FF3FE1C4
+:10CDD000C0D41C8017FDBFE00C108110260300108A
+:10CDE00017FD7FE117FF3FE100E81C803A88010052
+:10CDF0003A8837E01701C0DF170000DF0402C0DE09
+:10CE00003A2800F804F9FFDE1506C0DF150500DF3B
+:10CE1000040500DF15FC3FE115FB7FE117FBBFE0D8
+:10CE2000CC0080101E3E001017FCBFE01703C0109E
+:10CE300017FCBFE0170280101E12801817FCBFE01D
+:10CE40001707801015FEBFE0440080008DFDBFE095
+:10CE50004400800045FDBFE0434BA0D0CC3F801094
+:10CE6000260800108BFDBFE043FDFFE004FD3FE11D
+:10CE70003A880F203A880D183A880B1017FE3FE1C8
+:10CE80000097128017FCBFE0170380104400801049
+:10CE9000CC0F801015FFBFE017FCBFE0170080101B
+:10CEA0003700C01017FCBFE0170380103A8809183C
+:10CEB00017FCFFE03A888518050A001117FCBFE04F
+:10CEC00017FFFFE01503C01017FCBFE01703801029
+:10CED00044008010CC0F801015FFBFE017FCBFE0AE
+:10CEE0001702801017FFFFE01E0E801817FCBFE02E
+:10CEF0001701C010C4DFBF003A70861817FCBFE0EE
+:10CF00001501C01017FCBFE017008010040380104B
+:10CF100017FCFFE01701C0183500C0100601000023
+:10CF20003A8801003A8837E01701C0DF170000DFB8
+:10CF30000402C0DE3A2800F804FAFFDE1505C0DF5F
+:10CF4000150400DF040400DF15FD3FE115FC7FE15F
+:10CF500017FDBFE01704C01017FDBFE017058010D4
+:10CF60002646801817FDBFE0170680108C00801041
+:10CF70002603001017FCBFE00C00821026310010C1
+:10CF800017FDBFE01704C01017FDBFE017058010A4
+:10CF900044008010CC0F80101E12801817FDBFE0D7
+:10CFA0001707801015FFBFE0840080008DFEBFE0F2
+:10CFB0004400800045FEBFE0434BA0D0CC3F801032
+:10CFC000260800108BFEBFE043FEFFE004FE3FE1B9
+:10CFD0003A880F203A880D183A880B1017FF3FE166
+:10CFE0000097128017FDBFE0170080100401801029
+:10CFF00017FDFFE01704C01817FD3FE13A88C7206E
+:10D00000031AC018CC3FC0183500C01017FDBFE090
+:10D01000170480104400801017FDFFE015048018ED
+:10D02000CC0FC01017FDBFE01504C01017FDBFE006
+:10D03000170180101410C01017FDBFE01501C010BB
+:10D04000060E000017FDBFE01700801004028010DC
+:10D050003700801015FCBFE017FCBFE00C00821009
+:10D060001E06001017FDBFE01701C010C4EFBF007F
+:10D070003A70861817FDBFE01501C01017FDBFE01C
+:10D080001704C01017FDBFE0170580101E0680189A
+:10D0900017FDBFE01701C010C4EFBE003A7086183C
+:10D0A00017FDBFE01501C01017FDBFE0170080108D
+:10D0B0000403801017FDFFE01701C0183500C010F1
+:10D0C0003A8801003A8837E01701C0DF170000DF17
+:10D0D0000402C0DE3A2800F804FDFFDE150200DF7E
+:10D0E000040200DF15FF3FE115FE7FE106050000A9
+:10D0F00017FEBFE00C0090102602001044FDBF0098
+:10D100000606000017FFBFE01704C01017FFBFE0BE
+:10D11000170580101EF6BF183A8805003A8837E0D8
+:10D12000170000DF0401C0DE3A2800F804FEFFDE2D
+:10D130001501C0DF150000DF3A8839D81727A0D0C5
+:10D14000260300101727A0D03AE83E100601000081
+:10D150000442A0D03A8837E01701C0DF170000DF93
+:10D160000402C0DE3A2800F804EBFFDE1514C0DF2D
+:10D17000151300DF041300DF15F13FE115F07FE127
+:10D1800015EFBFE115EEFFE1C5FF3FE015FE3FE003
+:10D1900017EEBFE00C0090103A000510CC3F801055
+:10D1A00015FDBFE017F1BFE01708801015FBBFE0C9
+:10D1B0008DFA3FE08BFABFE084F2FFE03A880D1869
+:10D1C0003A880B1017FB3FE100A6158006130000FC
+:10D1D00017FEBFE04400801015FEBFE017F1BFE06E
+:10D1E0001702801017F1FFE03A888518030A001132
+:10D1F00017F0BFE04400C01015F0FFE03A880720A8
+:10D200000500C01017F1BFE0170280104400801025
+:10D21000CC0FC01017F1BFE01502C01017FEFFE0E1
+:10D2200017EFBFE00E05801817F1BFE01702C0101E
+:10D2300017F1BFE0170380101EE5BF1817FEBFE00F
+:10D240001E3A001017F1BFE01702C01017F1BFE03F
+:10D25000170380101E35801817FDBFE01E07001051
+:10D2600040071D803A880710C4028000150080180E
+:10D2700044008000C5FFBFE0063000003A300500E2
+:10D2800015F5BFE017F5FFE084FFBF003A70841882
+:10D290003A70011017F5BFE015FCBFE017F1BFE0D1
+:10D2A000170180101420C01017F1BFE01501C01045
+:10D2B00017F1BFE0170080100403801017F1FFE0A2
+:10D2C0001701C0183500C01017FCBFE015F6BFE00D
+:10D2D00017F6BFE03A70011017F1BFE01707801092
+:10D2E00015F9BFE0440080008DF8BFE0C4E0BF0046
+:10D2F00045F8BFE08DF73FE0434BA0D0CC3F801016
+:10D30000260A00108BF8FFE043F83FE18BF77FE13E
+:10D31000C4F2BFE0150080D83A880F283A880D2063
+:10D320003A880B1817F93FE18037128017FEBFE0EB
+:10D330001E02001017EFBFE01EB83F1017F1BFE04C
+:10D34000170880103A88091040D815803A30050037
+:10D3500015F3BFE017F3FFE084FFBF003A708418B5
+:10D360003A70011017F3BFE015FCBFE017F1BFE002
+:10D37000170180101420C01017F1BFE01501C01074
+:10D3800017F1BFE0170080100403801017F1FFE0D1
+:10D390001701C0183500C01017FCBFE015F4BFE03E
+:10D3A00017F4BFE03A700110C3FFBFE0260200107F
+:10D3B00044FDBF000601000017FEBFE03A8837E0D9
+:10D3C0001701C0DF170000DF0402C0DE3A2800F8B2
+:10D3D00004FEFFDE1501C0DF150000DF3A8839D8F2
+:10D3E0001727A0D0260300101727A0D03AE83E1038
+:10D3F000060100000442A0D03A8837E01701C0DFE0
+:10D40000170000DF0402C0DE3A2800F804EBFFDE5C
+:10D410001514C0DF151300DF041300DF15F13FE121
+:10D4200015F07FE115EFBFE115EEFFE117EFBFE06B
+:10D4300015FFBFE017EEBFE00C00901015FEBFE037
+:10D4400017F1BFE01709801015FBBFE08DFA3FE030
+:10D450008BFABFE084F2FFE03A880D183A880B108F
+:10D4600017FB3FE100A615800650000017F1BFE052
+:10D470001705801044008010CC0F801015FDBFE010
+:10D4800017F1BFE01704801017FDFFE01E3780186A
+:10D4900017FEBFE02605001080311D803A88071076
+:10D4A000C402800015008018064200003A300500D2
+:10D4B00015F8BFE017F8FFE084FFBF003A7084184A
+:10D4C0003A70011017F8BFE015FCBFE017F1BFE09C
+:10D4D000170180101410C11017F1BFE01501C01022
+:10D4E00017F1BFE0170080100403801017F1FFE070
+:10D4F0001701C0183500C01017FCBFE015F9BFE0D8
+:10D5000017F9BFE03A70011017F1BFE0170780105C
+:10D5100015F7BFE0840080008DF6BFE0C4E0BF00D7
+:10D5200045F6BFE08DF53FE0434BA0D0CC3F8010E7
+:10D53000260A00108BF6FFE043F63FE18BF57FE112
+:10D54000C4F2BFE0150080D83A880F283A880D2031
+:10D550003A880B1817F73FE18037128017F1BFE0C8
+:10D560001704801017FDFFE026E7BF1817FFBFE084
+:10D57000C4FFBF1015FFBFE017F0BFE04400C010AC
+:10D5800015F0FFE00300C01017F1BFE01705801091
+:10D590003A88091817F1FFE03A888518051A001132
+:10D5A00017F1BFE017FDFFE01505C01017FFBFE042
+:10D5B0001EAE3F1017F1BFE0170980103A8809101E
+:10D5C00040D815803A30050015F3BFE017F3FFE0AF
+:10D5D00084FFBF003A7084183A70011017F3BFE05F
+:10D5E00015FCBFE017F1BFE0170180101410C11047
+:10D5F00017F1BFE01501C01017F1BFE01700801050
+:10D600000403801017F1FFE01701C0183500C010A7
+:10D6100017FCBFE015F4BFE017F4BFE03A7001104B
+:10D6200017EFFFE017FFBFE03AC885183A8837E0E8
+:10D630001701C0DF170000DF0402C0DE3A2800F83F
+:10D6400004FDFFDE1502C0DF150100DF040100DF6D
+:10D6500015FF3FE1040460D117FF3FE1002A378046
+:10D660003A8837E01701C0DF170000DF0402C0DE90
+:10D670003A2800F804F8FFDE1507C0DF150600DFC2
+:10D68000040600DF15FB3FE115FA7FE115FF3FE0DF
+:10D6900015FE3FE015FD3FE015FC3FE017FBBFE046
+:10D6A0001E02001084FABF000631000017FBBFE025
+:10D6B00015FEBFE017FABFE03A92041015FFBFE075
+:10D6C00017FFBFE0D400801015FFBFE017FEBFE0DA
+:10D6D00017308010040380103A88071017FFBFE04E
+:10D6E0003500801817FE3FE100011E8015FCBFE0E9
+:10D6F00017FCBFE02602001017FCBFE0061C00006C
+:10D7000017FEBFE0173080103700801015FCBFE017
+:10D7100017FCBFE0BAD00510CC01801017FDFFE068
+:10D720003AB0841815FDBFE017FCBFE0FAD0051031
+:10D730000C02801017FDFFE03AB0841815FDBFE021
+:10D7400017FCBFE07AD005100C04801017FDFFE035
+:10D750003AB0841815FDBFE017FDFFE017FABFE0EF
+:10D760002602801884F4BF00060100003A880500F4
+:10D770003A8837E01701C0DF170000DF0402C0DE7F
+:10D780003A2800F804FBFFDE150400DF040400DF84
+:10D7900015FE3FE115FD7FE115FCBFE115FF3FE000
+:10D7A00017FEBFE02604001017FDBFE026020010A0
+:10D7B00017FCBFE01E02001084FABF000610000034
+:10D7C00017FEBFE015FFBFE017FFBFE0170CC0104A
+:10D7D00017FCBFE01500C01017FFBFE0170C80104A
+:10D7E0001E020010C4FEBF000605000017FFBFE0C8
+:10D7F000040DC01017FDBFE01500C0103A880500E9
+:10D800003A8837E0170000DF0401C0DE3A2800F84C
+:10D8100004F8FFDE1507C0DF150600DF040600DF91
+:10D8200015FB3FE115FA7FE115FF3FE015FE3FE0F4
+:10D8300015FD3FE015FC3FE017FBBFE01E020010A6
+:10D8400084FABF000636000017FBBFE015FDBFE0FD
+:10D8500017FABFE0160A001017FDBFE0173180105D
+:10D8600017FAFFE02E06801817FDBFE0173480106E
+:10D87000C4FFFF1017FABFE03A70841826020010A8
+:10D8800084FABF000626000017FAFFE017FDBFE08C
+:10D89000173480103A880B103A88091880FF0C80E2
+:10D8A00015FCBFE017FCBFE03A9206103440800040
+:10D8B00004C0BF103A70841815FEBFE017FEBFE029
+:10D8C0009400801015FEBFE017FDBFE017308010F8
+:10D8D000040380103A88071017FEBFE03500801857
+:10D8E00017FDBFE01730801004048010370080104F
+:10D8F0004C008010580080101E08001017FDBFE07B
+:10D9000017308010040480103A880710440080000B
+:10D9100035008018C4FEBF000601000017FFBFE0FD
+:10D920003A8837E01701C0DF170000DF0402C0DECD
+:10D930003A2800F804F3FFDE150CC0DF150B00DFFA
+:10D94000040B00DF15F83FE115F77FE115F6BFE1A5
+:10D9500015F5FFE115FF3FE0170280E015FEBFE07F
+:10D9600017F6BFE015FDBFE017F8BFE015FABFE0FE
+:10D9700017F7BFE0161E001017F6BFE0161C0010C8
+:10D9800017F8BFE0261A001017F5BFE026180010A0
+:10D9900017FABFE01731801017F6FFE02E14801839
+:10D9A00017FABFE01731801017F7FFE02E1080182C
+:10D9B00017FABFE01734801017F63FE117F7FFE0C2
+:10D9C0003AC8C7203AC8C710170280E03608801846
+:10D9D000170280E01606001017FABFE01734801017
+:10D9E000C4FFFF1017F7BFE03A708418264D0010EF
+:10D9F00084FABF00064E0000C4FFBF0015F9BFE067
+:10DA000015FC3FE00401800015FBBFE017FDBFE0FF
+:10DA1000CC0080102615001017FDBFE0CC00801050
+:10DA200015FCBFE017FBFFE017FCBFE03AC8851804
+:10DA300015FBBFE017FBBFE017FEFFE02E028018CA
+:10DA400017FEBFE015FBBFE017FDFFE017FCBFE0CE
+:10DA50003AC8851815FDBFE017FDBFE0CC00801067
+:10DA60002607001084FABF000631000017FBBFE054
+:10DA700017FEFFE02E02801817FEBFE015FBBFE087
+:10DA800004F9FFE017FCBFE03A88891817F5FFE0BA
+:10DA900017FFBFE03A88851817FBBFE13A880B10E3
+:10DAA000806B088017FFFFE017FBBFE03A888518FE
+:10DAB00015FFBFE017FEFFE017FBBFE03AC885186F
+:10DAC00015FEBFE017FABFE0172EC01017FDBFE02C
+:10DAD0003A88851817F9FFE03500C01017FABFE043
+:10DAE0001730801004048010370080108C008010E4
+:10DAF000980080101E08001017FABFE01730801041
+:10DB0000040480103A8807108400800035008018D3
+:10DB1000C4FEBF000606000017FDBFE00401801030
+:10DB200015FDBFE017FEBFE01EB33F103A880500A9
+:10DB30003A8837E01701C0DF170000DF0402C0DEBB
+:10DB40003A2800F804F0FFDE150FC0DF150E00DFE5
+:10DB5000040E00DF15F63FE115F57FE115F4BFE196
+:10DB600015F3FFE115FF3FE015F93FE017F5BFE0C2
+:10DB700015FEBFE017F3BFE015FDBFE015FC3FE069
+:10DB800015FB3FE017F6BFE02602001017F4BFE0D8
+:10DB90001E02001084FABF00065F000017F6BFE007
+:10DBA00015F9BFE017F5BFE017F3FFE03A880D184D
+:10DBB0003A880B1017F93FE140F71D8015FFBFE0D1
+:10DBC00017FFBFE02602001017FFBFE0065200005B
+:10DBD00017F5FFE017F9BFE0173480103A880B10F3
+:10DBE0003A88091880FF0C8015FBBFE0064300004F
+:10DBF00015F83FE015FA3FE015F73FE017FDBFE0ED
+:10DC00002643001017F9BFE0173480103AC885008A
+:10DC100017FEFFE03A70841815F8BFE017F8FFE030
+:10DC200017FEBFE02604801817FEFFE017F8BFE0DC
+:10DC30003AC8851815FABFE017F8BFE03A880B100C
+:10DC400017F63FE180751D8015FFBFE017FFBFE0AD
+:10DC50002602001017FFBFE0062F000017F9BFE0F3
+:10DC60001734C01017FABFE03AC8871817FDBFE095
+:10DC70002E0180183A88051815F7BFE017F83FE124
+:10DC800017FE7FE117F4FFE017FCBFE03A88871822
+:10DC900017F7BFE0150080D83A880F183A880D288A
+:10DCA0003A880B2017F63FE1C0871D8015FFBFE0C3
+:10DCB00017FFBFE02602001017FFBFE006160000A6
+:10DCC00017FDFFE017F7BFE03AC8851815FDBFE064
+:10DCD00017FCFFE017F7BFE03A88851815FCBFE096
+:10DCE00017FEFFE017F7BFE03A88851815FEBFE082
+:10DCF00017FBBFE04400801015FBBFE017F9BFE041
+:10DD00001733801017FBFFE036B9BF18060100007B
+:10DD10003A88010017FFBFE03A8837E01701C0DFFB
+:10DD2000170000DF0402C0DE3A2800F804F8FFDE26
+:10DD30001507C0DF150600DF040600DF15FD3FE113
+:10DD400015FC7FE115FBBFE115FAFFE115FF3FE090
+:10DD500015FE3FE017FDBFE02602001017FBBFE0F5
+:10DD60001E02001084FABF000616000017FDBFE077
+:10DD700015FEBFE017FCBFE017FAFFE03A880D1868
+:10DD80003A880B1017FE3FE140F71D8015FFBFE0FA
+:10DD900017FFBFE01E0A001017FEBFE0172EC010CD
+:10DDA00017FCBFE03A8885183A88071017FABFE0D9
+:10DDB0003A880D103A880B1817FB3FE1806B0880FA
+:10DDC00017FFBFE03A8837E01701C0DF170000DF18
+:10DDD0000402C0DE3A2800F804FAFFDE1505C0DFB1
+:10DDE000150400DF040400DF15FC3FE115FF3FE0F0
+:10DDF00015FD3FE015FE3FE017FCBFE01E020010DE
+:10DE000084FABF000684000017FCBFE017308010C2
+:10DE10001E02001044FBBF00067F000017FCBFE09D
+:10DE2000173280101E35001017FCBFE0173080102D
+:10DE3000040280103700801015FFBFE017FFBFE01D
+:10DE4000CC3F801015FFBFE017FFBFE0C4FABF1042
+:10DE50006803C0101E270018BA900610B400820094
+:10DE60003A888518176DB7103A680010E8DD010888
+:10DE7000F4DD010800DE01080CDE010818DE0108EF
+:10DE80003CDE01083CDE01083CDE01083CDE010806
+:10DE90003CDE01083CDE010824DE010830DE01081A
+:10DEA0000408800015FEBFE006300000041080006A
+:10DEB00015FEBFE0062D00000420800015FEBFE027
+:10DEC000062A00000440800015FEBFE0062700007F
+:10DED0000480800015FEBFE00624000004008100DD
+:10DEE00015FEBFE0062100000400820015FEBFE021
+:10DEF000061E000044FBBF000647000017FCBFE001
+:10DF000017308010040180103700801015FFBFE02B
+:10DF100017FFBFE0CC3F801015FFBFE017FFBFE049
+:10DF2000A00580101E09001017FFBFE0200680101A
+:10DF30001E09001017FFBFE0180580101E09001011
+:10DF40000408800015FEBFE00608000004208000E1
+:10DF500015FEBFE0060500000440800015FEBFE08E
+:10DF60000602000044FBBF00062B000017FCBFE0C8
+:10DF70001734801017FEFFE03A38851815FDBFE012
+:10DF800017FCBFE01731801017FDFFE01E0480185A
+:10DF900017FCBFE01733801017FEFFE0260480183F
+:10DFA00017FCBFE0150C001044FBBF00061A000070
+:10DFB00017FCBFE017FFFFE01536C01017FCBFE0ED
+:10DFC00017FEFFE01533C01017FCBFE04400C0008F
+:10DFD000150CC01017FCBFE0150D001017FDFFE079
+:10DFE00017FCBFE0150EC01017FEFFE017FCBFE0E6
+:10DFF000150FC01017FCBFE0173480103A880710C7
+:10E0000017FCBFE01510C01017FCBFE03A880910DC
+:10E0100080581D803A8805003A8837E01701C0DF34
+:10E02000170000DF0402C0DE3A2800F804F9FFDE22
+:10E03000150600DF040600DF15FC3FE115FB7FE15C
+:10E0400015FABFE115FF3FE015FE3FE015FD3FE08B
+:10E0500017FCBFE01E02001084FABF000616000085
+:10E0600017FCBFE015FFBFE017FFBFE0172E8010C1
+:10E0700017FBFFE03A88851815FEBFE017FEFFE0AA
+:10E0800017FABFE03A88851815FDBFE017FFBFE01B
+:10E09000172F801017FEFFE02E04801817FFBFE037
+:10E0A000172F801017FDFFE03602801884FABF009A
+:10E0B000060100003A8805003A8837E0170000DFC3
+:10E0C0000401C0DE3A2800F804FBFFDE1504C0DFBF
+:10E0D000150300DF040300DF15FD3FE1F4028000BB
+:10E0E0000498AB1015FEBFE08DFF3FE017FDBFE0C9
+:10E0F0001E0C001084FABF0006110000440000014D
+:10E10000C0F536808BFFFFE017FEBFE036028018B7
+:10E1100084F0BF00060A00008BFFBFE044008010BF
+:10E120008DFFBFE017FDBFE0173080103700801073
+:10E130004C008010600080101EF03F103A880500EF
+:10E140003A8837E01701C0DF170000DF0402C0DEA5
+:10E150003A2800F804FEFFDE1501C0DF150000DFDD
+:10E160003A8839D81727A0D0260300101727A0D047
+:10E170003AE83E10060100000442A0D03A8837E099
+:10E180001701C0DF170000DF0402C0DE3A2800F8E4
+:10E1900004FCFFDE150300DF040300DF15FF3FE191
+:10E1A00015FE7FE115FDBFE117FFBFE037008010CE
+:10E1B0000C0180102602001004F9BF0006150000B3
+:10E1C00017FDBFE0170080103A88071017FEBFE068
+:10E1D0003500C01017FEBFE00401801017FDFFE0FE
+:10E1E0001701C0183500C01017FEBFE004028010F0
+:10E1F00017FDFFE01702C0183500C01017FEBFE082
+:10E200000403801017FDFFE01703C0183500C0108D
+:10E210003A8805003A8837E0170000DF0401C0DEC5
+:10E220003A2800F804FCFFDE150300DF040300DFDA
+:10E2300015FF3FE115FE7FE115FDBFE117FFBFE0D0
+:10E24000370080100C0180102602001004F9BF0076
+:10E25000063B000017FDBFE0170080103A8807104A
+:10E2600017FEBFE03500C01017FEBFE004018010AC
+:10E2700017FDFFE01701C0183500C01017FEBFE002
+:10E280000402801017FDFFE01702C0183500C0100F
+:10E2900017FEBFE00403801017FDFFE00B03C0185A
+:10E2A000CCFFFF182D00C01017FEBFE084038010C4
+:10E2B00017FDFFE08303C018CC3FC0182500C01035
+:10E2C00017FEBFE0C403801017FDFFE0C303C018B2
+:10E2D000CC3FC0182500C01017FEBFE0040480101A
+:10E2E00017FDFFE00B04C018CCFFFF182D00C01075
+:10E2F00017FEBFE08404801017FDFFE08B04C018F8
+:10E30000CCFFFF182D00C01017FEBFE004058010E1
+:10E310003A8807003500C01017FEBFE004068010E1
+:10E320003A8807003500C01017FEBFE004078010D0
+:10E3300017FDFFE01707C0183500C0103A88050028
+:10E340003A8837E0170000DF0401C0DE3A2800F801
+:10E3500004F8FFDE1507C0DF150600DF040600DF46
+:10E3600015FA3FE117FABFE015FFBFE017FFBFE066
+:10E3700083178010CC3F80102611001017FFBFE0DC
+:10E3800017068010370080103A880710C4FDBF00C0
+:10E390003A70841815FEBFE017FFBFE01706801023
+:10E3A00017FEFFE03500C01017FFBFE01706801012
+:10E3B000040480104400C0003500C01006110000A5
+:10E3C00017FFBFE017038010040180103700801092
+:10E3D0003A880710C4FBBF003A70841815FEBFE0EE
+:10E3E00017FFBFE0170380100401801017FEFFE045
+:10E3F0003500C01017FFBFE0170380100480C00075
+:10E400003500C01017FFBFE0170B80102612001058
+:10E410003A30050015FBBFE017FBFFE084FFBF00AB
+:10E420003A7084183A70011017FBBFE015FDBFE089
+:10E4300017FFBFE0170B801017FFFFE0170CC01885
+:10E440003A8809183AE83E1017FDBFE015FCBFE016
+:10E4500017FCBFE03A70011017FFBFE08317801070
+:10E46000CC3F8010260A001017FFBFE0170680106F
+:10E47000370080101402801015FEBFE017FFBFE0C8
+:10E480001706801017FEFFE03500C010060C0000D4
+:10E4900017FFBFE0170380100401801037008010C1
+:10E4A0001404801015FEBFE017FFBFE017038010B3
+:10E4B0000401801017FEFFE03500C0103A8801000B
+:10E4C0003A8837E01701C0DF170000DF0402C0DE22
+:10E4D0003A2800F804FBFFDE150400DF040400DF27
+:10E4E00015FF3FE115FE7FE115FDBFE115FCFFE1E2
+:10E4F00017FFBFE01712C010170180E03604801824
+:10E5000017FFBFE003178010CC3F801026020010D9
+:10E5100084FABF00060E000017FEBFE017FDFFE003
+:10E520001500C01017FEBFE017FCFFE01501C0107A
+:10E5300017FEBFE01701C0E01502C010170280E00F
+:10E540003400E01017FEBFE01503C0103A88050044
+:10E550003A8837E0170000DF0401C0DE3A2800F8EF
+:10E5600004F6FFDE150900DF040900DF15FF3FE1B7
+:10E5700015FE7FE115FDBFE115FCFFE1170380E10A
+:10E58000170440E1170500E11706C0E0170780E017
+:10E590000DFBBFE105FA7FE105F93FE10DF8FFE072
+:10E5A0000DF7BFE017FFBFE01712C010170180E0A2
+:10E5B0003619801817FF3FE1171380201714C02069
+:10E5C0000BF83FE1CCFF3F213A8815203A8817002D
+:10E5D0003611C01A1E01C058360F801217FF3FE1D6
+:10E5E000171380201714C0200BF73FE1CCFF3F2109
+:10E5F0003A8811203A8813003607401A1E01C04895
+:10E600003605001217FFBFE003178010CC3F8010C3
+:10E61000600080101E02001084FABF000621000076
+:10E6200017FEBFE017FDFFE01500C01017FEBFE0AA
+:10E6300017FCFFE01501C01017FEBFE01701C0E096
+:10E640001502C01017FEBFE00BFBFFE00D03C0106A
+:10E6500017FEBFE003FAFFE08503C01017FEBFE01E
+:10E6600003F9FFE0C503C01017FEBFE00BF8FFE0A1
+:10E670000D04C01017FEBFE00BF7FFE08D04C010C3
+:10E6800017FEBFE01505001017FEBFE015060010CD
+:10E69000170280E03400E01017FEBFE01507C0103D
+:10E6A0003A8805003A8837E0170000DF0401C0DE31
+:10E6B0003A2800F804EDFFDE1512C0DF151100DF67
+:10E6C000041100DF15F13FE115F07FE115EFBFE127
+:10E6D00015FE3FE015FD3FE08DFF3FE017F1BFE085
+:10E6E000170380100402801037008010CCFFBF1089
+:10E6F00015FCBFE017F1BFE0170380100402801083
+:10E70000370080103AD40410CCFFBF1015FBBFE0D7
+:10E7100017F1BFE01709801017FBFFE02E048018E7
+:10E7200017F1BFE01709801017FCFFE036028018D0
+:10E7300004F9BF0006A9000017F1BFE01718801008
+:10E7400015F8BFE08DF73FE08BF7BFE0C4F2FFE0C4
+:10E750003A880D183A880B1017F83FE100A615808B
+:10E760000408800015FEBFE03A30050015F9BFE04F
+:10E7700017F9FFE084FFBF003A7084183A70011067
+:10E7800017F9BFE015FDBFE017F1BFE017038010D8
+:10E790000401801017FEFFE03500C01017F1BFE044
+:10E7A0001703801017F1FFE01703C0183700C018D7
+:10E7B0003500C01017FDBFE015FABFE017FABFE043
+:10E7C0003A70011017F0BFE0261E001017EFBFE0EF
+:10E7D0001E1C00100611000044000001C0F5368028
+:10E7E0008BFFBFE030E284101E09001074010201AB
+:10E7F000044E2521C0A9378017F1BFE017188010FB
+:10E800003A88091040D8158084F0BF0006730000D4
+:10E810008BFFBFE0440080108DFFBFE017F1BFE029
+:10E820001703C01017F1BFE01704801017F0BFE105
+:10E830003A880B103A880918800D1E801EE63F109A
+:10E840000627000017F0BFE01E1F001017EFBFE003
+:10E85000261D00108DFF3FE006110000440000015E
+:10E86000C0F536808BFFBFE030E284101E09001037
+:10E870007401020104642521C0A9378017F1BFE0AB
+:10E88000171880103A88091040D8158084F0BF000E
+:10E89000065200008BFFBFE0440080108DFFBFE0F8
+:10E8A00017F1BFE01703C01017F1BFE01704801085
+:10E8B00017EFBFE13A880B103A880918C0161E807E
+:10E8C0001EE63F100606000017F1BFE01718801083
+:10E8D0003A88091040D81580C4FFBF00063F0000E9
+:10E8E00017F1BFE0170B8010261C001017F1BFE0D6
+:10E8F000170DC01017FEBFE03AB084181405801041
+:10E9000015FEBFE017FEFFE0C4F7BF003A708418A1
+:10E9100015FEBFE03A30050015F5BFE017F5FFE042
+:10E9200084FFBF003A7084183A70011017F5BFE0F9
+:10E9300015FDBFE017F1BFE0170380100401801040
+:10E9400017FEFFE03500C01017FDBFE015F6BFE071
+:10E9500017F6BFE03A700110061B000017F1BFE088
+:10E96000170DC01017FEBFE03AB0841814018010D4
+:10E9700015FEBFE017FEFFE0C4F3BF003A70841835
+:10E9800015FEBFE03A30050015F3BFE017F3FFE0D6
+:10E9900084FFBF003A7084183A70011017F3BFE08B
+:10E9A00015FDBFE017F1BFE01703801004018010D0
+:10E9B00017FEFFE03500C01017FDBFE015F4BFE003
+:10E9C00017F4BFE03A70011017F1BFE0171880107C
+:10E9D0003A88091040D815803A8805003A8837E00F
+:10E9E0001701C0DF170000DF0402C0DE3A2800F87C
+:10E9F00004EDFFDE1512C0DF151100DF041100DF8A
+:10EA000015F13FE115F07FE115EFBFE115FB3FE0A8
+:10EA100015FA3FE015FF3FE08DFE3FE017F1BFE044
+:10EA2000170380100402801037008010CCFFBF1045
+:10EA300015FDBFE017F1BFE017038010040280103E
+:10EA4000370080103AD40410CCFFBF1015FCBFE093
+:10EA50000478800015F9BFE0061A000044000001A8
+:10EA6000C0F536808BFEBFE030E284101E0500103A
+:10EA700074010201047A2521C0A9378084F0BF0007
+:10EA800006D800008BFEBFE0440080108DFEBFE082
+:10EA900017F1BFE0170380100402801037008010C8
+:10EAA000CCFFBF1015FDBFE017F1BFE017038010CA
+:10EAB00004028010370080103AD40410CCFFBF103D
+:10EAC00015FCBFE017F1BFE01709801017FCFFE04D
+:10EAD0002EE2BF1817F1BFE01709801017FDFFE005
+:10EAE0002EDEBF1817F1BFE01718801015F7BFE032
+:10EAF0008DF63FE08BF6BFE0C4F2FFE03A880D18D8
+:10EB00003A880B1017F73FE100A615803A30050050
+:10EB100015F8BFE017F8FFE084FFBF003A708418D3
+:10EB20003A70011017F8BFE015FABFE017F1BFE027
+:10EB300017038010040180100408C0003500C010C5
+:10EB400017F1BFE01703801017F1FFE01703C0189B
+:10EB50003700C0183500C01017F0BFE0261F0010A6
+:10EB600017EFBFE01E1D00108DFE3FE006110000F4
+:10EB700044000001C0F536808BFEBFE030E2841017
+:10EB80001E09001074010201048E2521C0A93780DE
+:10EB900017F1BFE0171880103A88091040D8158087
+:10EBA00084F0BF00068F00008BFEBFE044008010A1
+:10EBB0008DFEBFE017F1BFE01703C01017F1BFE0F3
+:10EBC0001704801017F0BFE13A880B103A88091833
+:10EBD000800D1E801EE63F100627000017F0BFE0E4
+:10EBE0001E1F001017EFBFE0261D00108DFE3FE036
+:10EBF0000611000044000001C0F536808BFEBFE026
+:10EC000030E284101E09001074010201049F2521C6
+:10EC1000C0A9378017F1BFE0171880103A88091093
+:10EC200040D8158084F0BF00066E00008BFEBFE068
+:10EC3000440080108DFEBFE017F1BFE01703C01045
+:10EC400017F1BFE01704801017EFBFE13A880B10EF
+:10EC50003A880918C0161E801EE63F1006060000FE
+:10EC600017F1BFE0171880103A88091040D81580B6
+:10EC7000C4FFBF00065B000017F1BFE01703801060
+:10EC80000401801017F1FFE0170D0019C4F2FF0016
+:10EC90003A70C6201401C0183500C01017FABFE042
+:10ECA00015F5BFE017F5BFE03A7001108DFE3FE0AB
+:10ECB00017F1BFE0170380103700801015FFBFE089
+:10ECC0000615000044000001C0F536808BFEBFE051
+:10ECD00030E284101E0900107401020104B02521E5
+:10ECE000C0A9378017F1BFE0171880103A880910C3
+:10ECF00040D8158084F0BF00063A00008BFEBFE0CC
+:10ED0000440080108DFEBFE017F1BFE017038010B4
+:10ED10003700801015FFBFE017FFFFE017F9BFE0D5
+:10ED20003A7084181E03001017FFBFE04C008010DB
+:10ED30001EE43F1017FFFFE017F9BFE03A70841898
+:10ED40002606001017F1BFE0171880103A88091046
+:10ED500040D8158017F9BFE00622000017F1BFE088
+:10ED600017038010040180103700801014088010F1
+:10ED700015FBBFE03A30050015F3BFE017F3FFE0E5
+:10ED800084FFBF003A7084183A70011017F3BFE097
+:10ED900015FABFE017F1BFE01703801004018010DF
+:10EDA00017FBFFE03500C01017F1BFE0170380101C
+:10EDB00017F1FFE01703C0183700C0183500C01066
+:10EDC00017FABFE015F4BFE017F4BFE03A70011086
+:10EDD00017F1BFE0171880103A88091040D8158045
+:10EDE0003A8805003A8837E01701C0DF170000DFD6
+:10EDF0000402C0DE3A2800F804F8FFDE1507C0DF81
+:10EE0000150600DF040600DF15FF3FE115FE7FE178
+:10EE100015FDBFE115FCFFE1170280E0150180D868
+:10EE200017FCBFE0150080D817FDFFE13A880D0000
+:10EE300017FE7FE117FF3FE1C0411E803A8837E0AF
+:10EE40001701C0DF170000DF0402C0DE3A2800F817
+:10EE500004F8FFDE1507C0DF150600DF040600DF3B
+:10EE600015FF3FE115FE7FE115FDBFE115FCFFE158
+:10EE7000170280E0150180D817FCBFE0150080D88C
+:10EE80003A880F0017FDBFE117FE7FE117FF3FE152
+:10EE9000C0411E803A8837E01701C0DF170000DF4D
+:10EEA0000402C0DE3A2800F804F8FFDE1507C0DFD0
+:10EEB000150600DF040600DF15FF3FE115FE7FE1C8
+:10EEC00015FDBFE115FCFFE1170380E0150180D8B7
+:10EED000170280E0150080D817FCFFE117FDBFE1A5
+:10EEE00017FE7FE117FF3FE1C0411E803A8837E0FF
+:10EEF0001701C0DF170000DF0402C0DE3A2800F867
+:10EF000004F0FFDE150FC0DF150E00DF040E00DF7A
+:10EF100015FF3FE115FE7FE115FDBFE115FCFFE1A7
+:10EF2000170300E11704C0E0170580E00DFB3FE187
+:10EF300005FAFFE00DF9BFE00BFBBFE003FAFFE0CD
+:10EF40000BF93FE1150600D9150500D81504C0D806
+:10EF5000150300D8150280D8170280E0150180D86B
+:10EF600017FCBFE0150080D817FDFFE13A880D00BF
+:10EF700017FE7FE117FF3FE1804A1E803A8837E0A5
+:10EF80001701C0DF170000DF0402C0DE3A2800F8D6
+:10EF900004F0FFDE150FC0DF150E00DF040E00DFEA
+:10EFA00015FF3FE115FE7FE115FDBFE115FCFFE117
+:10EFB000170300E11704C0E0170580E00DFB3FE1F7
+:10EFC00005FAFFE00DF9BFE00BFBBFE003FAFFE03D
+:10EFD0000BF93FE1150600D8150500D9150400D836
+:10EFE0001503C0D8150280D8170280E0150180D81B
+:10EFF00017FCBFE0150080D83A880F0017FDBFE16D
+:10F0000017FE7FE117FF3FE1804A1E803A8837E014
+:10F010001701C0DF170000DF0402C0DE3A2800F845
+:10F0200004EEFFDE1511C0DF151000DF041000DF55
+:10F0300015FF3FE115FE7FE115FDBFE115FCFFE186
+:10F04000170480E1170540E1170600E11707C0E04B
+:10F05000170880E00DFBBFE105FA7FE105F93FE10C
+:10F060000DF8FFE00DF7BFE00BFBBFE003FAFFE098
+:10F0700003F93FE10BF87FE10BF7BFE1150680D9FB
+:10F08000150540D9150400D91503C0D8150280D83C
+:10F09000170380E0150180D8170280E0150080D8A2
+:10F0A00017FCFFE117FDBFE117FE7FE117FF3FE10E
+:10F0B000804A1E803A8837E01701C0DF170000DF62
+:10F0C0000402C0DE3A2800F804FBFFDE150400DF6E
+:10F0D000040400DF15FF3FE115FE7FE115FDBFE1F0
+:10F0E00015FCFFE117FFBFE01712C010170180E009
+:10F0F0003604801817FFBFE003178010CC3F801044
+:10F100002602001084FABF000614000017FEBFE0BC
+:10F1100017FDFFE01500C01017FEBFE017FCFFE071
+:10F120001501C01017FEBFE01701C0E01502C010A6
+:10F1300017FEFFE017FEBFE01503C0101702C0E086
+:10F1400034009000C4FFBF103A7084183400E010FF
+:10F1500017FEBFE01507C0103A8805003A8837E06F
+:10F16000170000DF0401C0DE3A2800F804F4FFDED7
+:10F17000150B00DF040B00DF15FD3FE115FC7FE1FF
+:10F1800015FBBFE115FAFFE1170580E1170640E125
+:10F19000170700E11708C0E0170980E00DF9BFE18B
+:10F1A00005F87FE105F73FE10DF6FFE00DF5BFE063
+:10F1B00017FDBFE01712C010170380E03619801842
+:10F1C00017FD3FE1171380201714C0200BF63FE115
+:10F1D000CCFF3F213A8815203A8817003611C01A13
+:10F1E0001E01C058360F801217FD3FE11713802013
+:10F1F0001714C0200BF53FE1CCFF3F213A881120C6
+:10F200003A8813003607401A1E01C048360500121E
+:10F2100017FDBFE003178010CC3F80106000801006
+:10F220001E02001084FABF000631000017FCBFE088
+:10F2300017FBFFE01509C01017FCBFE017FAFFE04D
+:10F240001500C01017FCBFE01701C0E0150AC01080
+:10F2500017FCBFE01702C0E01501C01017FCBFE0AB
+:10F260001703C0E01502C01017FCBFE00BF9FFE068
+:10F270000D07C01017FCBFE003F8FFE08507C010C2
+:10F2800017FCBFE003F7FFE0C507C01017FCBFE0A5
+:10F290000BF6FFE00D08C01017FCBFE00BF5FFE018
+:10F2A0008D08C01017FCBFE03A8819103A881B007F
+:10F2B00015FE3FE315FF7FE317FEFFE017FCBFE0FD
+:10F2C0001503C01017FFFFE017FCBFE0150BC010BF
+:10F2D0001704C0E034009000C4FFBF103A708418D7
+:10F2E0003400E01017FCBFE0150FC0103A8805008D
+:10F2F0003A8837E0170000DF0401C0DE3A2800F842
+:10F3000004F8FFDE1507C0DF150600DF040600DF86
+:10F3100015FF3FE115FE7FE115FDBFE115FCFFE1A3
+:10F32000170380E0150180D8170280E0150080D80F
+:10F3300017FCFFE117FDBFE117FE7FE117FF3FE17B
+:10F3400000011F803A8837E01701C0DF170000DF97
+:10F350000402C0DE3A2800F804F8FFDE1507C0DF1B
+:10F36000150600DF040600DF15FF3FE115FE7FE113
+:10F3700015FDBFE115FCFFE1170280E0150180D803
+:10F3800017FCBFE0150080D817FDFFE13A880D009B
+:10F3900017FE7FE117FF3FE100011F803A8837E049
+:10F3A0001701C0DF170000DF0402C0DE3A2800F8B2
+:10F3B00004F8FFDE1507C0DF150600DF040600DFD6
+:10F3C00015FF3FE115FE7FE115FDBFE115FCFFE1F3
+:10F3D000170280E0150180D817FCBFE0150080D827
+:10F3E0003A880F0017FDBFE117FE7FE117FF3FE1ED
+:10F3F00000011F803A8837E01701C0DF170000DFE7
+:10F400000402C0DE3A2800F804EEFFDE1511C0DF6A
+:10F41000151000DF041000DF15FF3FE115FE7FE14E
+:10F4200015FDBFE115FCFFE1170400E11705C0E081
+:10F43000170680E00DFB3FE105FAFFE00DF9BFE0A4
+:10F440000BFBBFE003FAFFE00BF93FE1150800D921
+:10F45000150700D81506C0D8150500D8150480D8A2
+:10F46000170380E0150380D8170280E0150280D8CA
+:10F4700017FCBFE0150180D817FDBFE0150080D84C
+:10F480003A880F003A880D0017FE7FE117FF3FE131
+:10F49000400B1F803A8837E01701C0DF170000DFFC
+:10F4A0000402C0DE3A2800F804EEFFDE1511C0DFCA
+:10F4B000151000DF041000DF15FF3FE115FE7FE1AE
+:10F4C00015FDBFE115FCFFE1170400E11705C0E0E1
+:10F4D000170680E00DFB3FE105FAFFE00DF9BFE004
+:10F4E0000BFBBFE003FAFFE00BF93FE1150800D882
+:10F4F000150700D9150600D81505C0D8150480D801
+:10F50000170380E0150380D8170280E0150280D829
+:10F51000150100D8150000D817FCFFE117FDBFE169
+:10F5200017FE7FE117FF3FE1400B1F803A8837E06D
+:10F530001701C0DF170000DF0402C0DE3A2800F820
+:10F5400004ECFFDE1513C0DF151200DF041200DF2C
+:10F5500015FF3FE115FE7FE115FDBFE115FCFFE161
+:10F56000170680E1170740E1170800E11709C0E01E
+:10F57000170A80E00DFBBFE105FA7FE105F93FE1E5
+:10F580000DF8FFE00DF7BFE00BFBBFE003FAFFE073
+:10F5900003F93FE10BF87FE10BF7BFE1150880D9D4
+:10F5A000150740D9150600D91505C0D8150480D80F
+:10F5B000170580E0150380D8170480E0150280D875
+:10F5C000170380E0150180D8170280E0150080D86D
+:10F5D00017FCFFE117FDBFE117FE7FE117FF3FE1D9
+:10F5E000400B1F803A8837E01701C0DF170000DFAB
+:10F5F0000402C0DE3A2800F804FCFFDE150300DF39
+:10F60000040300DF15FE3FE115FD7FE117FDBFE0BC
+:10F610001E02001084FABF00062F000017FDBFE095
+:10F620001703C01017FDBFE02602801884FABF0040
+:10F630000629000017FEBFE0170080101E0500100D
+:10F6400017FEBFE017FDFFE01500C0103A88050067
+:10F650000621000017FEBFE01700801017FDFFE035
+:10F660001E02801884FABF00061B000017FEBFE0D0
+:10F670001700801015FFBFE00609000017FFBFE06C
+:10F680001703C01017FDBFE01E02801884FABF00E8
+:10F690000611000017FFBFE01703801015FFBFE041
+:10F6A00017FFBFE01703801017FEFFE01700C01818
+:10F6B0001EF2FF1017FDFFE017FFBFE01503C0109B
+:10F6C00017FEBFE0170080103A88071017FDBFE053
+:10F6D0001503C0103A8805003A8837E0170000DFAC
+:10F6E0000401C0DE3A2800F804F8FFDE150700DF49
+:10F6F000040700DF15FA3FE115F97FE117F93FE153
+:10F700001E02002084FABF000659000017F93FE1ED
+:10F710003A8815203A88170015FBBFE215FCFFE276
+:10F7200017F93FE11703402117FB3FE11E040029B1
+:10F7300017F93FE1170B402117FC3FE12602002992
+:10F7400084FABF00064A000017FA3FE117000021C3
+:10F750001E05002017FABFE017F9FFE01500C010E2
+:10F760003A8805000642000017FA3FE11700002121
+:10F7700017F97FE11E02002984FABF00063C000051
+:10F7800017FA3FE11700002115FF3FE117FA3FE1AB
+:10F79000170000213A8811203A88130015FD3FE236
+:10F7A00015FE7FE20618000017F93FE13A880D20A8
+:10F7B0003A880F0015FBBFE115FCFFE117FF3FE1A1
+:10F7C0001703402117FB3FE11E06002917FF3FE109
+:10F7D000170B402117FC3FE11E02002984FABF00ED
+:10F7E0000623000017FF3FE11703002115FB3FE14F
+:10F7F00017FF3FE1170B002115FC3FE117FB3FE12D
+:10F8000017FC7FE115FF3FE117FF3FE117034021A0
+:10F8100017FD3FE11EE43F2917FF3FE1170B402191
+:10F8200017FE3FE11EE03F2917F93FE13A88052026
+:10F830003A88070015FBBFE015FCFFE017FBFFE06F
+:10F8400017FFBFE01503C01017FCFFE017FFBFE074
+:10F85000150BC01017FDFFE017F9BFE01503C0102E
+:10F8600017FEFFE017F9BFE0150BC0103A8805003E
+:10F870003A8837E0170000DF0401C0DE3A2800F8BC
+:10F8800004F8FFDE1507C0DF150600DF040600DF01
+:10F8900015FC3FE13A8805283A88073005FBBFE0B0
+:10F8A0003A88051805FABFE015FD3FE015FE3FE078
+:10F8B00017FCBFE01E02001084FABF00062F0000F4
+:10F8C00017FCBFE015FFBFE0060D000017FFBFE00B
+:10F8D0001707801015FDBFE017FDBFE03400D01002
+:10F8E00017FFBFE01507C01017FFBFE01703801018
+:10F8F00015FFBFE017FEBFE04400801015FEBFE01B
+:10F9000017FFBFE01703C01017FCBFE01EEFBF18C2
+:10F9100017FFBFE01707801015FDBFE003FBBFE036
+:10F920002607001017FDFFE03400B000C4FFBF1031
+:10F930003A70861817FFBFE01507C01006040000D4
+:10F9400017FDBFE03400D01017FFBFE01507C0104F
+:10F9500017FEBFE04400801015FEBFE003FABFE0D1
+:10F960002605001017FEBFE07A9104103A880B10AC
+:10F9700017FC3FE1001C37803A8805003A8837E0E1
+:10F980001701C0DF170000DF0402C0DE3A2800F8CC
+:10F9900004F4FFDE150BC0DF150A00DF040A00DFE8
+:10F9A00015F83FE13A8809283A880B3005F73FE11E
+:10F9B0003A88092805F63FE115FD3FE015FE3FE0D6
+:10F9C00017F83FE11E02002084FABF00063E000047
+:10F9D00017F83FE115FF3FE117F83FE13A880520AE
+:10F9E0003A88070015FBBFE015FCFFE00613000096
+:10F9F00017FFBFE0170F801015FDBFE017FDBFE038
+:10FA00003400D01017FFBFE0150FC01017FFBFE084
+:10FA10001703801015F9BFE017FFBFE0170B801028
+:10FA200015FABFE017F9BFE017FAFFE015FFBFE0D6
+:10FA300017FEBFE04400801015FEBFE017FFBFE0D7
+:10FA40001703C01017FBBFE01EE9BF1817FFBFE088
+:10FA5000170BC01017FCBFE01EE5BF1817FFBFE073
+:10FA6000170F801015FDBFE003F7BFE02607001059
+:10FA700017FDFFE03400B000C4FFBF103A708618D5
+:10FA800017FFBFE0150FC0100604000017FDBFE010
+:10FA90003400D01017FFBFE0150FC01017FEBFE0F5
+:10FAA0004400801015FEBFE003F6BFE026050010FD
+:10FAB00017FEBFE0BA9104103A880B1017F83FE127
+:10FAC000001C37803A8805003A8837E01701C0DF0C
+:10FAD000170000DF0402C0DE3A2800F804EBFFDE66
+:10FAE0001514C0DF151300DF041300DF15F13FE12B
+:10FAF00015EF7FE115F0BFE13A880738170280E083
+:10FB000005EEFFE005EDBFE015FF3FE015FE3FE02D
+:10FB100015FD3FE017EFBFE015F3BFE017F0BFE0C2
+:10FB200015F4BFE017F1BFE01718801015FCBFE017
+:10FB30008DFB3FE08BFBBFE0C4F2FFE03A880D187D
+:10FB40003A880B1017FC3FE100A6158017F1BFE0C3
+:10FB5000170680103700801015FFBFE017FFBFE0C9
+:10FB60004C0080102606001017F1BFE01718801017
+:10FB70003A88091040D8158004FCBF0006960000A2
+:10FB80000408800015FEBFE03A30050015F9BFE01B
+:10FB900017F9FFE084FFBF003A7084183A70011033
+:10FBA00017F9BFE015FDBFE017F1BFE017038010A4
+:10FBB0000401801017FEFFE03500C01017F1BFE010
+:10FBC0001703801017F1FFE01703C0183700C018A3
+:10FBD0003500C01017FDBFE015FABFE017FABFE00F
+:10FBE0003A70011017F1BFE0170B801026230010A8
+:10FBF00017F1BFE0170DC01017FEBFE03AB0841830
+:10FC00001405801015FEBFE017FEFFE0C4F7BF002B
+:10FC10003A70841815FEBFE017FFBFE01402801091
+:10FC200015FFBFE03A30050015F7BFE017F7FFE01A
+:10FC300084FFBF003A7084183A70011017F7BFE0D4
+:10FC400015FDBFE017F1BFE017038010040180101D
+:10FC500017FEFFE03500C01017F1BFE01706801057
+:10FC600017FFFFE03500C01017FDBFE015F8BFE03B
+:10FC700017F8BFE03A7001100623000017F1BFE04B
+:10FC8000170DC01017FEBFE03AB0841814018010A1
+:10FC900015FEBFE017FEFFE0C4F3BF003A70841802
+:10FCA00015FEBFE017FFFFE0C4FDBF003A708418E7
+:10FCB00015FFBFE03A30050015F5BFE017F5FFE08E
+:10FCC00084FFBF003A7084183A70011017F5BFE046
+:10FCD00015FDBFE017F1BFE017038010040180108D
+:10FCE00017FEFFE03500C01017F1BFE017068010C7
+:10FCF00017FFFFE03500C01017FDBFE015F6BFE0AD
+:10FD000017F6BFE03A70011017F1BFE01706801038
+:10FD10000401801017F3FFE03500C01017F1BFE0B9
+:10FD2000170680100402801017F4FFE03500C010A1
+:10FD300003EEBFE02604001017FFBFE0140480109C
+:10FD400015FFBFE00604000017FFFFE0C4FBBF0083
+:10FD50003A70841815FFBFE003EDBFE0260E0010D7
+:10FD600017FFBFE09400801015FFBFE017F1BFE060
+:10FD70001706801004038010370080101E0A001040
+:10FD800017F1BFE01706801004038010C43FC000C5
+:10FD90003500C0100604000017FFFFE044FFBF005D
+:10FDA0003A70841815FFBFE017FFBFE054008010C1
+:10FDB00015FFBFE017F1BFE01706801017FFFFE047
+:10FDC0003500C01017F1BFE0171880103A880910ED
+:10FDD00040D815803A8805003A8837E01701C0DF1F
+:10FDE000170000DF0402C0DE3A2800F804F5FFDE49
+:10FDF000150AC0DF150900DF150840DC150700DC17
+:10FE0000040900DF15FD3FE115FC7FE13A88093068
+:10FE10003A880B381702C0E0170380E005FB3FE18A
+:10FE20003A88092805FA3FE105F9FFE005F8BFE047
+:10FE300003F9BFE003F8FFE03A880D183A880B1089
+:10FE400017FC3FE1807C1F802602001084FABF006F
+:10FE5000060B000017FCBFE03A8821103A88230007
+:10FE600003FBFFE003FABFE0150080D83A880F18C3
+:10FE70003A880B803A880D8817FD3FE140A21F8029
+:10FE800004FEFFE61703C0DF170200DF170140DCA6
+:10FE9000170000DC0404C0DE3A2800F804F5FFDE99
+:10FEA000150AC0DF150900DF150840DC150700DC66
+:10FEB000040900DF15FD3FE115FC7FE13A880930B8
+:10FEC0003A880B381702C0E0170380E005FB3FE1DA
+:10FED0003A88092805FA3FE105F9FFE005F8BFE097
+:10FEE00003F9BFE003F8FFE03A880D183A880B10D9
+:10FEF00017FC3FE1808D1F802602001084FABF00AE
+:10FF0000060B000017FCBFE03A8821103A88230056
+:10FF100003FBFFE003FABFE0150080D83A880F1812
+:10FF20003A880B803A880D8817FD3FE140A21F8078
+:10FF300004FEFFE61703C0DF170200DF170140DCF5
+:10FF4000170000DC0404C0DE3A2800F804FCFFDEE1
+:10FF50001503C0DF150200DF040200DF15FE3FE1DC
+:10FF600015FF3FE0040B60D117FE3FE140403780B2
+:10FF700015FFBFE017FFBFE01E040010C0091E8080
+:10FF80003A880710C40480001500801817FFBFE0EE
+:10FF90003A8837E01701C0DF170000DF0402C0DE37
+:10FFA0003A2800F804F6FFDE1509C0DF150800DF67
+:10FFB000040800DF15FB3FE115FA7FE115F9BFE109
+:10FFC00017FBBFE083178010CC3F8010260A00107B
+:10FFD00017FBBFE0170680100401C0003500C010F9
+:10FFE0003A88010017FBBFE0170680103700801029
+:10FFF0000C0180101EFB3F1017FBBFE017038010A1
+:020000022000DC
+:10000000040180108400C0003500C0103A8801004F
+:1000100017FBBFE017038010370080100C10801012
+:100020001EFB3F1017FBBFE0170380100401801078
+:10003000370080103A880710C4FBBF003A7084185C
+:1000400015FFBFE017FFBFE01408801015FFBFE0E9
+:1000500017FBBFE0170380100401801017FFFFE0BB
+:100060003500C01017FBBFE01703801017FBFFE03F
+:100070001703C0183700C0183500C01017FBBFE0C9
+:1000800083178010CC3F80102608001017FBBFE0BC
+:10009000170680100404801017FBFFE01706C01835
+:1000A0000404C0183700C0183500C010040B60D11C
+:1000B00017FB3FE1002A378017FBBFE004188010D0
+:1000C00015FDBFE0440080008DFCBFE08BFCBFE06D
+:1000D0003A880910407715803A88071017FDBFE06D
+:1000E0001500C01017FDBFE0170080102602001099
+:1000F0003A88050006010000C4FFBF0015FEBFE0FE
+:1001000017FEBFE01E080010150000D817FBFFE126
+:10011000B400820104A6B83117F97FE117FA3FE174
+:1001200040493780060400007401020104C2252101
+:10013000C0A937803A8801003A8837E01701C0DF4C
+:10014000170000DF0402C0DE3A2800F804FBFFDEDF
+:10015000150400DF040400DF15FF3FE115FE7FE119
+:1001600015FDBFE115FCFFE117FFBFE017FEFFE043
+:10017000150BC01017FFBFE017FCFFE0150CC010F7
+:1001800017FFBFE017FDFFE0150DC0103A88010012
+:100190003A8837E0170000DF0401C0DE3A2800F893
+:1001A00004FCFFDE1503C0DF150200DF040200DFE0
+:1001B00015FF3FE115FE7FE13A880D0017FE7FE154
+:1001C00017FF3FE1C05F1E803A8837E01701C0DFAC
+:1001D000170000DF0402C0DE3A2800F804FCFFDE4E
+:1001E0001503C0DF150200DF040200DF15FF3FE149
+:1001F00015FE7FE117FEBFE13A880B0017FF3FE1D4
+:10020000C05F1E803A8837E01701C0DF170000DFAB
+:100210000402C0DE3A2800F804FCFFDE1503C0DF4C
+:10022000150200DF040200DF15FF3FE115FE7FE14C
+:100230003A880D0017FE7FE117FF3FE180931E8093
+:100240003A8837E01701C0DF170000DF0402C0DE84
+:100250003A2800F804FCFFDE1503C0DF150200DFBA
+:10026000040200DF15FF3FE115FE7FE117FEBFE14D
+:100270003A880B0017FF3FE180931E803A8837E0F1
+:100280001701C0DF170000DF0402C0DE3A2800F8C3
+:1002900004FDFFDE1502C0DF150100DF040100DFF1
+:1002A00015FF3FE1040460D117FF3FE1002A3780CA
+:1002B0003A8837E01701C0DF170000DF0402C0DE14
+:1002C0003A2800F804F7FFDE1508C0DF150700DF45
+:1002D000040700DF15FC3FE115FB7FE115FABFE1E4
+:1002E00015F9FFE115FF3FE017FCBFE015FEBFE089
+:1002F00017FEBFE0170B801017FBFFE00E068018FB
+:1003000017FBFFE017F9BFE03A88851817FEFFE0FA
+:10031000170BC0180E02801884FCBF0006170000DF
+:1003200017FEBFE0170AC01017FBBFE03A88851818
+:1003300017F9FFE03A880D183A880B1017FA3FE1D9
+:10034000806B088017FEBFE0172F8010260A001070
+:1003500017FEBFE0172F8010370080100C018010AF
+:1003600015FDBFE017FDBFE0200180101E02001048
+:10037000C4FEBF0015FFBFE017FFBFE03A8837E0BB
+:100380001701C0DF170000DF0402C0DE3A2800F8C2
+:1003900004FAFFDE150500DF040500DF15FD3FE16F
+:1003A00015FC7FE115FBBFE115FF3FE017FDBFE046
+:1003B00015FEBFE017FBBFE02604001017FEBFE0EC
+:1003C000170CC01017FBBFE01500C01017FEBFE0F0
+:1003D000170C80101E03001004FDBF0015FFBFE0C6
+:1003E000060D000017FEBFE0170C801050028010B1
+:1003F0001E03001084FCBF0015FFBFE006060000CE
+:1004000017FCBFE02604001017FEBFE0040DC0106B
+:1004100017FCBFE01500C01017FFBFE03A8837E0B7
+:10042000170000DF0401C0DE3A2800F804F9FFDEFF
+:100430001506C0DF150500DF040500DF15FC3FE1F0
+:1004400015FB7FE115FF3FE017FCBFE015FEBFE0A5
+:1004500017FEBFE0170B801017FBFFE01602801895
+:1004600084FCBF000646000017FEBFE0172F801077
+:100470002603001017FEBFE0172E80102602001082
+:1004800044FBBF00063E000017FEBFE0173F801090
+:10049000C4FFFF1017FBBFE03A708418260200105B
+:1004A00084FABF000636000017FE3FE100F220800C
+:1004B00015FFBFE017FFBFE02602001017FFBFE0E7
+:1004C000062F000017FEBFE0172F80100401C01098
+:1004D00017FEBFE0172F8010040180103700801036
+:1004E0002C003C1134208000C4FFBF103AB084209F
+:1004F0003500801817FBBFE00E010010C40080100B
+:10050000BAD0051015FDBFE017FEBFE0172F801011
+:100510000401801017FEFFE0172FC0180401C01857
+:100520003700C0182C003C1917FDFFE0341CC01820
+:100530003AB0C6203500C01017FE3FE100F220801F
+:1005400015FFBFE017FE3FE100FB208015FFBFE075
+:1005500017FEBFE0172F80100401C01017FEBFE088
+:10056000172F801004018010370000113400840020
+:10057000C4FFBF103AB084203500801817FFBFE0D9
+:100580003A8837E01701C0DF170000DF0402C0DE41
+:100590003A2800F804F2FFDE150DC0DF150C00DF6D
+:1005A000040C00DF15F73FE115F67FE115F5BFE11B
+:1005B00015F4FFE115FF3FE017F7BFE015FBBFE0C3
+:1005C00015FE3FE017F5BFE015FDBFE017FBBFE0EC
+:1005D000170B801017F6FFE00E0A801817FBBFE01C
+:1005E000170B801017F5FFE00E06801817FBBFE011
+:1005F000170BC01017F5BFE03AC88718170280E044
+:100600000E02801884FCBF000693000017FBBFE0B9
+:10061000172F80102603001017FBBFE0172E801045
+:100620002602001044FBBF00068B000017FB3FE1D1
+:1006300000F2208015FFBFE017FFBFE02602001088
+:1006400017FFBFE00684000017FBBFE0172F8010E4
+:100650000401C01017FBBFE0172F801004018010A9
+:10066000370080102C003C1134208000C4FFBF10E4
+:100670003AB084203500801806650000C4FFBF0032
+:1006800015F8BFE017FDBFE0CC0080101E1E001063
+:1006900017FDBFE00401C01004FFBF003A708418CA
+:1006A00015FCBFE017FCFFE017FDBFE03AC8871854
+:1006B000170280E00E0180183A88051815FABFE08D
+:1006C00017FEBFE017F4FFE03A88871817FA3FE1FA
+:1006D00004F8BFE03A880D203A880B183A880910D0
+:1006E000806B088017FEFFE017FABFE03A88851894
+:1006F00015FEBFE01702C0E017FABFE03AC8851840
+:10070000150280E00630000017FDBFE0CC0080102D
+:1007100015F9BFE017FDFFE017F9BFE03AC88518EB
+:1007200015FDBFE017FDBFE00401C01004FFBF00CE
+:100730003A70841815FCBFE017FCFFE017FDBFE01E
+:100740003AC889181702C0E017F9BFE03A8887183D
+:100750003A8805200E0180183A88051815FABFE07E
+:1007600004F8FFE017F9BFE03A8885183A880F10BF
+:1007700017FEBFE017F4FFE03A88891817FAFFE088
+:1007800017F9BFE03AC885183A880D103A880B204F
+:100790003A880938806B088017FAFFE017F9BFE044
+:1007A0003AC8851817FEFFE03A88851815FEBFE0A5
+:1007B00017FAFFE017F9BFE03AC885181702C0E042
+:1007C0003AC88518150280E017FBBFE0170AC01071
+:1007D00017FDBFE03A88851817F8FFE03500C01014
+:1007E00017FB3FE100F2208015FFBFE017FFBFE0DD
+:1007F0001E0A001017FB3FE14004218015FFBFE0F7
+:1008000017FFBFE01E07001017FCBFE015FDBFE09B
+:10081000170280E01E993F10060300003A8801008D
+:10082000060100003A88010017FBBFE0172F801077
+:100830000401C01017FBBFE0172F801004018010C7
+:100840003700001134008400C4FFBF103AB0842088
+:100850003500801817FFBFE03A8837E01701C0DF86
+:10086000170000DF0402C0DE3A2800F804F1FFDEC2
+:10087000150EC0DF150D00DF040D00DF15F73FE199
+:1008800015F67FE115F5BFE115F4FFE115FF3FE037
+:1008900017F4BFE015FBBFE017F6BFE015FABFE0A5
+:1008A00017F7BFE015F9BFE017F9BFE0170B80108D
+:1008B00017F6FFE00E06801817F9BFE0170BC010FF
+:1008C00017F6BFE03AC8871817F4BFE00E02801889
+:1008D00084FCBF000693000015FE3FE00682000086
+:1008E00017F9FFE017FEBFE03A9104103A88851827
+:1008F000170D801017F6FFE01678801817F9FFE043
+:1009000017FEBFE03A9104103A888518170DC01001
+:1009100017F93FE117FEBFE03A9104103A888520AD
+:10092000170E80103A88851817F6FFE00E6B8018B6
+:1009300017F9FFE017FEBFE03A9104103A888518D6
+:10094000170D801015FCBFE015FD3FE0065C0000B0
+:1009500017F6FFE017FCBFE0164D801817F9FFE00F
+:1009600017FEBFE0040180103A9104103A88851800
+:100970001700C01017FCBFE03A88851817F6FFE093
+:100980000E43801817F9FFE017FEBFE00401801046
+:100990003A9104103A8885181700C01017FCBFE080
+:1009A0003A88871817F6BFE03AC8851815F8BFE0EF
+:1009B00017F8FFE017F4BFE00E0180183A88051819
+:1009C00015F8BFE017F9BFE0170AC01017F6BFE02F
+:1009D0003A88851817F8FFE03A880D183A880B1006
+:1009E00017F53FE180CB42802613001017F9BFE0D6
+:1009F0001708801017F9FFE017FC7FE13A88091803
+:100A00003AE83E1015FFBFE017FFBFE01E0A0010D6
+:100A100017F9BFE01709801017F93FE117F8FFE059
+:100A20001500C0D817F5FFE117F6BFE117FC7FE10D
+:100A30003AE83E1015FFBFE017F4FFE017F8BFE0FB
+:100A4000262E801817FFBFE01E2C001017F4FFE0C1
+:100A500017F8BFE03AC8851815F4BFE017F9FFE0B2
+:100A600017FEBFE0040180103A9104103A888518FF
+:100A70001700801017FCFFE03A88851815F6BFE0D4
+:100A800017F8BFE017F5FFE03A88851815F5BFE0C5
+:100A900017F9FFE017FEBFE0040180103A9104103F
+:100AA0003A8885181700801017FCFFE03A888518EF
+:100AB00015FCBFE017FDBFE04400801015FDBFE04E
+:100AC00017F9FFE017FEBFE03A9104103A88851845
+:100AD000170F801017FDFFE0169DBF1817FEBFE02F
+:100AE0004400801015FEBFE017F9BFE0170C80101E
+:100AF00017FEFFE0167ABF18060100003A880100D1
+:100B000017F9BFE0170AC01017FABFE03A88851836
+:100B100017FBFFE03A880B183A880910001C378051
+:100B200017FFBFE03A8837E01701C0DF170000DF8A
+:100B30000402C0DE3A2800F804F5FFDE150AC0DF23
+:100B4000150900DF150800DC040900DF15F73FE197
+:100B500015FD3FE015FC3FE015FB3FE015FA3FE0D7
+:100B600015F93FE015FE3FE017F7BFE0040D8010D8
+:100B700015F8BFE017F7BFE0172F801026190010F7
+:100B800017F7BFE0172F8010370080100C08801077
+:100B900015FDBFE017F7BFE0172F8010370080105A
+:100BA0000C10801015FCBFE017F7BFE0172F801066
+:100BB000370080100C20801015FBBFE017F7BFE056
+:100BC000172F8010370080100C40801015FABFE0FE
+:100BD00017F7BFE0172F8010370080100C808010AF
+:100BE00015F9BFE017F7BFE01730801058008010EC
+:100BF0001E2C001017FDBFE0200880101E290010D9
+:100C000017FEBFE03A91041017F8FFE03A88851804
+:100C100017F7FFE01731C0181500C01017F7BFE035
+:100C20001732C01017F7BFE0173180103AC8871885
+:100C300017FEBFE03A91041017F83FE13A8885208B
+:100C40004400C0181501C01017F7FFE017FEBFE001
+:100C50003A9104103A888518170E001117F7BFE073
+:100C6000173F401117FEBFE03A91041017F8FFE05C
+:100C70003A88A11800F00C801502808017FEBFE0B2
+:100C80003A91041017F8FFE03A88851817F7FFE04B
+:100C9000173FC0181503C01017FEBFE044008010B6
+:100CA00015FEBFE017F7BFE0173380105800801023
+:100CB0001E2C001017FCBFE0201080101E29001011
+:100CC00017FEBFE03A91041017F8FFE03A88851844
+:100CD00017F7FFE01734C0181500C01017F7BFE072
+:100CE0001735C01017F7BFE0173480103AC88718BF
+:100CF00017FEBFE03A91041017F83FE13A888520CB
+:100D00004400C0181501C01017F7FFE017FEBFE040
+:100D10003A9104103A888518170E001117F7BFE0B2
+:100D2000173F401117FEBFE03A91041017F8FFE09B
+:100D30003A88A11800F00C801502808017FEBFE0F1
+:100D40003A91041017F8FFE03A88851817F7FFE08A
+:100D5000173FC0181503C01017FEBFE044008010F5
+:100D600015FEBFE017F7BFE017368010580080105F
+:100D70001E2C001017FBBFE0202080101E29001041
+:100D800017FEBFE03A91041017F8FFE03A88851883
+:100D900017F7FFE01737C0181500C01017F7BFE0AE
+:100DA0001738C01017F7BFE0173780103AC88718F8
+:100DB00017FEBFE03A91041017F83FE13A8885200A
+:100DC0004400C0181501C01017F7FFE017FEBFE080
+:100DD0003A9104103A888518170E001117F7BFE0F2
+:100DE000173F401117FEBFE03A91041017F8FFE0DB
+:100DF0003A88A11800F00C801502808017FEBFE031
+:100E00003A91041017F8FFE03A88851817F7FFE0C9
+:100E1000173FC0181503C01017FEBFE04400801034
+:100E200015FEBFE017F7BFE017398010580080109B
+:100E30001E2C001017FABFE0204080101E29001061
+:100E400017FEBFE03A91041017F8FFE03A888518C2
+:100E500017F7FFE0173AC0181500C01017F7BFE0EA
+:100E6000173BC01017F7BFE0173A80103AC8871831
+:100E700017FEBFE03A91041017F83FE13A88852049
+:100E80004400C0181501C01017F7FFE017FEBFE0BF
+:100E90003A9104103A888518170E001117F7BFE031
+:100EA000173F401117FEBFE03A91041017F8FFE01A
+:100EB0003A88A11800F00C801502808017FEBFE070
+:100EC0003A91041017F8FFE03A88851817F7FFE009
+:100ED000173FC0181503C01017FEBFE04400801074
+:100EE00015FEBFE017F7BFE0173C801058008010D8
+:100EF0001E2C001017F9BFE0208080101E29001062
+:100F000017FEBFE03A91041017F8FFE03A88851801
+:100F100017F7FFE0173DC0181500C01017F7BFE026
+:100F2000173EC01017F7BFE0173D80103AC887186A
+:100F300017FEBFE03A91041017F83FE13A88852088
+:100F40004400C0181501C01017F7FFE017FEBFE0FE
+:100F50003A9104103A888518170E001117F7BFE070
+:100F6000173F401117FEBFE03A91041017F8FFE059
+:100F70003A88A11800F00C801502808017FEBFE0AF
+:100F80003A91041017F8FFE03A88851817F7FFE048
+:100F9000173FC0181503C01017FEBFE044008010B3
+:100FA00015FEBFE017F7BFE017FEFFE0150CC010FD
+:100FB00017F7BFE03A880910801D20803A880100A9
+:100FC00004FFFFE61702C0DF170100DF170000DC97
+:100FD0000403C0DE3A2800F804FAFFDE1505C0DF7E
+:100FE000150400DF040400DF15FC3FE115FF3FE0BE
+:100FF000F40280000498AB1015FDBFE0F4028000FD
+:101000000498AB1015FEBFE0060C00004400000180
+:10101000C0F5368017FDBFE02608001017FEBFE0C0
+:10102000C4FFBF1015FEBFE017FEBFE01E03001097
+:1010300004E3BF0015FFBFE00605000017FCBFE09A
+:10104000172F801037008010CC0080101EEF3F104B
+:1010500017FFBFE03A8837E01701C0DF170000DF55
+:101060000402C0DE3A2800F804FAFFDE1505C0DFEE
+:10107000150400DF040400DF15FC3FE115FF3FE02D
+:10108000F40280000498AB1015FDBFE0F40280006C
+:101090000498AB1015FEBFE0060C000044000001F0
+:1010A000C0F5368017FDBFE02608001017FEBFE030
+:1010B000C4FFBF1015FEBFE017FEBFE01E03001007
+:1010C00004E3BF0015FFBFE00606000017FCBFE009
+:1010D000172F8010370080100C0480101804801027
+:1010E0001EEE3F1017FFBFE03A8837E01701C0DF60
+:1010F000170000DF0402C0DE3A2800F804FAFFDE21
+:101100001505C0DF150400DF040400DF15FC3FE116
+:1011100015FF3FE0F40280000498AB1015FDBFE01E
+:10112000F40280000498AB1015FEBFE0060C00002E
+:1011300044000001C0F5368017FDBFE0260800100E
+:1011400017FEBFE0C4FFBF1015FEBFE017FEBFE0F3
+:101150001E03001004E3BF0015FFBFE006060000F9
+:1011600017FCBFE0172F8010370080100C02801092
+:10117000180280101EEE3F1017FFBFE03A8837E0DC
+:101180001701C0DF170000DF0402C0DE3A2800F8B4
+:1011900004FAFFDE1505C0DF150400DF040400DFDC
+:1011A00015FC3FE115FE3FE015FD3FE017FCBFE0F9
+:1011B000170580103A880B107401020104CA25211A
+:1011C00080C7028015FF3FE00610000017FFBFE058
+:1011D0002403C010B40182003A88851817B6B510F0
+:1011E00017FCFFE01E06801817FFBFE02403C010A5
+:1011F000B401820004B6B5103A88851815FEBFE028
+:1012000017FFBFE04400801015FFBFE0035CA0D0D3
+:10121000CC3F801017FFFFE016ECBF1817FEBFE0B1
+:101220001E02001044F7BF000626000015FF3FE035
+:101230000611000017FFBFE02413C01074018200E4
+:101240003A8885181754EE1017FEBFE0170180107A
+:101250001E06801817FFBFE02413C010740182001F
+:101260000454AE103A88851815FDBFE017FFBFE0A3
+:101270004400801015FFBFE0030AA0D0CC3F8010CF
+:1012800017FFFFE016EBBF1817FDBFE01E020010AE
+:1012900044F7BF00060B000017FCBFE01705001164
+:1012A00017FEBFE003028010CC3F80102413801093
+:1012B00017FDFFE03A8885183A880B10002221803C
+:1012C0003A8805003A8837E01701C0DF170000DFD1
+:1012D0000402C0DE3A2800F804FBFFDE1504C0DF7C
+:1012E000150300DF040300DF15FE3FE115FD7FE17C
+:1012F00017FE7FE17401020104D0252180C702801E
+:1013000017FEBFE02429C010B40182003A88851876
+:1013100015CD351017FEBFE02429001117FDFFE0A1
+:10132000B40182003A88852015EAF51017FEBFE067
+:10133000BA900610B40182003A8885181770B71069
+:1013400015FFBFE017FFBFE0172780108400C00023
+:101350001506C01017FFBFE0172780108400C000DB
+:101360001507C01017FFBFE017278010177DE0D0CA
+:101370001508C01017FFBFE01727C01017FEBFE009
+:101380002429801004060011B401820004C2B510A3
+:101390003A8885201505801817FFBFE01727C01071
+:1013A0007401820004D5A5101501801817FFBFE055
+:1013B0000404C0001508C01017FFBFE08401C0007E
+:1013C0001511C01017FFBFE0172780108401C0005F
+:1013D0001502C01017FFBFE0847AC1001509C010C4
+:1013E00017FFFFE0B4008200043185101502801859
+:1013F00017FFBFE01504001017FFFFE0B4008200E4
+:10140000041288101503801817FFFFE0B400820053
+:1014100004618A101505801817FFFFE0B4008200F0
+:1014200004518A101507801817FFBFE0172A801093
+:101430001402C01017FFBFE0152AC01017FEBFE04E
+:10144000BA900610B40182003A8885181770B71058
+:101450001727C01017FEBFE02429801004060011D2
+:10146000B401820004C2B5103A88852015058018A1
+:1014700017FEBFE0242980100406C010B4018200CA
+:1014800004C2B5103A8885183A880B1017FF3FE15F
+:10149000801E018017FEBFE02429001117FEFFE027
+:1014A000B40182003A88852015C2F51017FEBFE00E
+:1014B0002429001117FFFFE0B40182003A8885203B
+:1014C00015CAF51017FEBFE02429C010B401820030
+:1014D00004C2B5103A88871817FFBFE01528C0105E
+:1014E00017FEBFE04400801015FEBFE017FEBFE00E
+:1014F0003A8837E01701C0DF170000DF0402C0DEC2
+:101500003A2800F804FEFFDE150100DF040100DFC9
+:1015100015FF3FE117FFBFE0170680100401C00070
+:101520003500C0103A88010017FFBFE01706801091
+:10153000370080100C0180101EFB3F1017FFBFE02A
+:1015400017038010040180108400C0003500C01013
+:101550003A88010017FFBFE01703801037008010A2
+:101560000C1080101EFB3F103A8801003A8837E0CB
+:10157000170000DF0401C0DE3A2800F804F1FFDEA6
+:10158000150EC0DF150D00DF040D00DF15F43FE17F
+:1015900015FD3FE017F4BFE02429C010B40182001C
+:1015A0003A88851817EAB51015FABFE017F47FE1FD
+:1015B0007401020104DB252180C7028017FABFE015
+:1015C00083088010CC3F8010580080101E1B001034
+:1015D00017FABFE0170980103A88091017F4BFE026
+:1015E0002429C010B40182003A88851815D335111A
+:1015F00017FABFE017098010045080103A880910CC
+:1016000017F4BFE02429C010B40182003A8885187D
+:1016100015D4351117FABFE01709801004A0801007
+:101620003A88091017F4BFE02429C010B4018200E1
+:101630003A88851815D03511065100000450000174
+:10164000400A38803A88091017F4BFE02429C010F6
+:10165000B40182003A88851815D33511060B0000B5
+:1016600017F4BFE02429C010B40182003A8885181D
+:1016700017D3B5100408C01017F4BFE024290011D7
+:10168000B40182003A88852015D3F51017F4BFE025
+:101690002429C010B40182003A88851817D3B510E8
+:1016A000CC0780101EEE3F1004500001400A388025
+:1016B0003A88091017F4BFE02429C010B401820051
+:1016C0003A88851815D43511060B000017F4BFE0D1
+:1016D0002429C010B40182003A88851817D4B510A7
+:1016E0000408C01017F4BFE024290011B4018200DF
+:1016F0003A88852015D4F51017F4BFE02429C010CE
+:10170000B40182003A88851817D4B510CC07801030
+:101710001EEE3F1004180001400A38803A88091074
+:1017200017F4BFE02429C010B40182003A8885185C
+:1017300015D03511060B000017F4BFE02429C010A6
+:10174000B40182003A88851817D0B5100408C0107B
+:1017500017F4BFE024290011B40182003A888520E3
+:1017600015D0F51017F4BFE02429C010B401820091
+:101770003A88851817D0B510CC0780101EEE3F10A0
+:1017800017FABFE0170680103A88091040E91F8059
+:1017900015F9BFE017F9BFE01E0500107401020142
+:1017A00004E02521C0D9028084FABF0006070200A8
+:1017B00017FABFE0170780103A88091040E91F8028
+:1017C00015F8BFE017F8BFE01E0500107401020114
+:1017D00004EC2521C0D9028084FABF0006FB010079
+:1017E00017F4BFE0242980100401C010B401820066
+:1017F00004C2B5103A88871817FABFE017008010A6
+:1018000017F93FE117F87FE1150000D83A880F2853
+:101810003A880D203A880B103A88091800B51780CD
+:1018200017F4BFE02429C010B40182003A8885185B
+:1018300017C3B5103A88091040E5188015F7BFE0C6
+:1018400017F7BFE07AD00510CC01801015F6BFE085
+:1018500017F7BFE04C00801015F5BFE017F4BFE0AC
+:101860002429C010B40182003A88851817C3B51026
+:1018700004028010C400C8003500C01015FE3FE00F
+:101880000605000017FEBFE04400C01015FEFFE093
+:1018900050C48910260A001017F4BFE02429C01094
+:1018A000B40182003A88851817C3B510040280106D
+:1018B000370080100C0088101EF23F100601000057
+:1018C0003A88010017FEBFE010C489101E03001003
+:1018D0007401020104F82521C0D9028017F4BFE089
+:1018E0002429C010B40182003A88851817C3B510A6
+:1018F000040280103700801015FFBFE017FFBFE023
+:10190000CC0080102605001017FF7FE17401020152
+:101910000401262180C702800605000017FFBFE1F1
+:1019200017FE7FE1740102010415262180C70280A1
+:1019300017FABFE0030A8010CC3F801058008010D7
+:101940001E2C001015FC3FE015FB3FE015FC3FE0AE
+:101950000624000015FB3FE00616000017FCBFE060
+:10196000BA900610B40182003A88851817AAF510BB
+:1019700017FBBFE044008010BA9004103A88851825
+:10198000170080101702801017FAFFE01E0680185B
+:1019900017F4BFE02429001117FBFFE0B401820017
+:1019A0003A88852015CEF51017FBBFE04400801063
+:1019B00015FBBFE017FCBFE0BA900610B40182002F
+:1019C0003A88851817AAB51003008010CC3F801004
+:1019D00017FBFFE016E1BF1817FCBFE044008010C2
+:1019E00015FCBFE0435BA0D0CC3F801017FCFFE0AC
+:1019F00016D8BF1817FABFE0030A8010CC3F80103A
+:101A0000580080101E0F001017FABFE0170E80104C
+:101A10003A88071017FABFE01710801035008018B9
+:101A200017FABFE0170E8010040280103A880710E2
+:101A300017FABFE01710801004DDBF1035008018C2
+:101A4000064C000017F4BFE02429C010B401820046
+:101A50003A88851817C3B51004058010847BC1002F
+:101A60003500C01017F4BFE02429C010B401820073
+:101A70003A88851817C3B510040B80100402C00003
+:101A80003500C01017F4BFE02429C010B401820053
+:101A90003A88851817C3B510040C80100402C000E2
+:101AA0003500C01017F4BFE02429C010B401820033
+:101AB0003A88851817C3B510040D80100402C000C1
+:101AC0003500C01017F4BFE02429C010B401820013
+:101AD0003A88851817C3B510040E8010C400C000E2
+:101AE0003500C01017F4BFE02429C010B4018200F3
+:101AF0003A88851817C3B5100409801017FAFFE05B
+:101B00001701C01804FCFF183500C01017F4BFE01F
+:101B10002429C010B40182003A88851817C3B51073
+:101B2000040A80103A8807003500C01017F4BFE09F
+:101B30002429C010B40182003A88851817C3B51053
+:101B40000407801017FAFFE01702C01804FCFF1802
+:101B50003500C01017F4BFE02429C010B401820082
+:101B60003A88851817C3B510040880103A88070012
+:101B70003500C01017F4BFE02429C010B401820062
+:101B80003A88851817C3B510043A80103401C00094
+:101B90003500C01017F4BFE02429C010B401820042
+:101BA0003A88851817C3B510043A801037008010A2
+:101BB0002C0180102618001017F4BFE02429001112
+:101BC0004400C000B40182003A88852015CBF5108E
+:101BD00017F4BFE02429C010B40182003A888518A8
+:101BE00017C3B510043B80103480C0003500C0100E
+:101BF00017F4BFE02429C010B40182003A88851888
+:101C000017C3B510043B8010370080102C80801063
+:101C100026190010060B000017F4BFE02429C0109D
+:101C2000B40182003A88851815CB35108400400134
+:101C300074010201041D262180C7028044FDBF00FB
+:101C400006E2000017F4BFE0242900114400C000A0
+:101C5000B40182003A88852015CCF510340081004B
+:101C6000C480801015FFBFE017F6BFE05800801059
+:101C70001E150010060B000017F4BFE02429C01049
+:101C8000B40182003A88851815CC351084004001D3
+:101C9000740102010435262180C7028044FDBF0083
+:101CA00006CA000017FFBFE01402801015FFBFE056
+:101CB00017FFFFE03480BF00C4FFBF103A708418E4
+:101CC00015FFBFE00621000017F6BFE09800801066
+:101CD0001E0A001017FFFFE0C4FDBF003A70841811
+:101CE00015FFBFE017FFFFE03480BF00C4FFBF1047
+:101CF0003A70841815FFBFE00614000017F6BFE025
+:101D0000180180101E08001017FFFFE0C4FDBF007F
+:101D10003A70841815FFBFE017FFBFE034808010D1
+:101D200015FFBFE00609000017FFFFE0C4FDBF007C
+:101D30003A70841815FFBFE017FFFFE03480BF0042
+:101D4000C4FFBF103A70841815FFBFE017F5BFE05D
+:101D50001E04001017FFBFE01400811015FFBFE044
+:101D60000604000017FFFFE0C4FFBE003A708418AD
+:101D700015FFBFE017F4BFE02429C010B4018200B2
+:101D80003A88851817C3B5100402801017FFFFE0CA
+:101D90003500C01017F4BFE02429C010B401820040
+:101DA0003A88851817C3B5100402801037008010D8
+:101DB0003A880B1074010201044D262180C702806D
+:101DC00017F4BFE02429C010B40182003A888518B6
+:101DD00017C3B5100403C01017F4BFE02429001185
+:101DE000B40182003A88852003C8B510CC3F0011A9
+:101DF00017F4BFE024294011B40182003A888528F5
+:101E000043C8B510CC3F80103A9204103AB08820F5
+:101E100017F4BFE024294011B40182003A888528D4
+:101E200083C8B510CC3F80103A9404103AB0882093
+:101E300017F4BFE024294011B40182003A888528B4
+:101E4000C3C8B510CC3F80103A9604103AB0842035
+:101E50003500801817F4BFE02429C010B4018200B7
+:101E60003A88851817C3B5100404C01017F4BFE0F2
+:101E700024290011B40182003A88852003C9B510D5
+:101E8000CC3F001117F4BFE024294011B4018200B7
+:101E90003A88852843C9B510CC3F80103A92041087
+:101EA0003AB08420CCFFBF103500801817F4BFE093
+:101EB000BA900610B40182003A8885181770B710DE
+:101EC000172780104400C0001506C01017F4BFE0AB
+:101ED000BA900610B40182003A8885181770B710BE
+:101EE000172780104400C0001507C01017F4BFE08A
+:101EF0002429C010B40182003A88851817C535110D
+:101F000017F4BFE02429C010B401820004C2B51048
+:101F10003A8885183A880F103A880D00B4004201BB
+:101F2000048448294009208017F4BFE02429C01008
+:101F3000B40182003A88851817C4351117F4BFE040
+:101F40002429C010B401820004C2B5103A88851853
+:101F50003A880F103A880D00B400420104EA48297B
+:101F60004009208017F4BFE02429C010B40182008A
+:101F700004C2B5103A8885183A880910804022803A
+:101F800015FDBFE017FDBFE01E0A001017F4BFE00B
+:101F90002429C010B401820004C2B5103A88851803
+:101FA0003A880D003A880B003A88091080F22180A7
+:101FB00015FDBFE017FDBFE026030010740102010C
+:101FC00004592621C0D9028017FDBFE03A8837E0C6
+:101FD0001701C0DF170000DF0402C0DE3A2800F856
+:101FE00004F7FFDE1508C0DF150700DF040700DF78
+:101FF00015FC3FE115FB7FE115FABFE115FF3FE05E
+:1020000017FCBFE0150D001015FE3FE00633000081
+:1020100004C0800015FFBFE017FEBFE016040010EB
+:1020200017FFBFE01400901015FFBFE0060300008B
+:1020300017FFBFE03440801015FFBFE017FCBFE082
+:102040001702001117FCBFE0170EC01017FEBFE00B
+:102050007A9104103A88871817FB7FE117FFBFE0D9
+:10206000150080D817FAFFE13A880D283A880B1836
+:10207000802F1F8015FDBFE017FDBFE02602001076
+:10208000C4FFBF000619000017FEBFE01E020010CB
+:1020900017FCBFE0150D001017FCBFE0040D001188
+:1020A00017FCBFE0170EC01017FEBFE07A910410B6
+:1020B0003A8885183A880B1000541F8015FDBFE040
+:1020C00017FDBFE026020010C4FFBF000607000096
+:1020D00017FEBFE04400801015FEBFE017FEBFE012
+:1020E000900080101ECA3F103A8805003A8837E0F9
+:1020F0001701C0DF170000DF0402C0DE3A2800F835
+:1021000004F1FFDE150EC0DF150D00DF040D00DF4A
+:1021100015F53FE115F47FE115F3BFE117F3BFE0DB
+:1021200015FFBFE017F5BFE01728801015FEBFE0D0
+:102130003A30050015F9BFE017F9FFE084FFBF0052
+:102140003A7084183A70011017F9BFE015FDBFE02E
+:1021500017FEBFE00401801015FCBFE017FEBFE0D2
+:10216000170B80102609001074010201045E26215D
+:10217000C0D9028017FDBFE015F8BFE017F8BFE037
+:102180003A70011084FABF00064A000017FEBFE053
+:102190004400C000150BC0100401400117F43FE1DA
+:1021A00080E8378015FBBFE017FEBFE0170E8010F8
+:1021B00017FBFFE01500C01017FEBFE0170E8010E0
+:1021C00017FFFFE01502C01017FEBFE0170E8010CA
+:1021D0001707C01034009000C4FFBF103A70861873
+:1021E00017FEBFE0170E80103400E0181507C0106E
+:1021F00017FF7FE117FB3FE1001C378017FEBFE0B0
+:10220000170E80103A880B1017FC3FE180CE178024
+:1022100015FABFE017FABFE00E12001017FFBFE17A
+:1022200017FA7FE1740102010465262180C702804C
+:1022300017F5BFE0172780101712C0104400C01810
+:102240001512C01017FEBFE0150B001017FDBFE000
+:1022500015F7BFE017F7BFE03A70011084FABF002E
+:102260000614000017F5BFE017278010170F0011A4
+:1022700017F5BFE01727801017F3FFE03A88C72053
+:10228000150FC01017F5BFE0172780101710C010EA
+:102290004400C0181510C01017FEBFE0150B001049
+:1022A00017FDBFE015F6BFE017F6BFE03A7001106A
+:1022B0003A8805003A8837E01701C0DF170000DFD1
+:1022C0000402C0DE3A2800F804F8FFDE1507C0DF7C
+:1022D000150600DF040600DF15FA3FE117FABFE03C
+:1022E00015FEBFE0B401820017ADB61015FDBFE0CA
+:1022F00017FEBFE0170380101706801017FEFFE0DF
+:102300001703C0181706C0183700C0181402C018E9
+:102310003500C01017FEBFE01703801017038010B0
+:102320003700801015FCBFE017FCBFE00C208010C8
+:102330001E42001017FE3FE1807F228017FEBFE0A3
+:102340001713801017FEFFE044048010BA900410A9
+:102350003A88851817008010043880100407801010
+:102360003700801015FBBFE017FBBFE02C0090107A
+:102370001E2A001017FEBFE01714801015FFBFE0E3
+:102380000605000017FE3FE1807F228017FFBFE0B7
+:102390004400801015FFBFE017FFBFE0300280103F
+:1023A0001EF83F1017FEBFE01703801017068010BD
+:1023B000040480104400C0003500C01017FEBFE0C8
+:1023C00015140010B401820017D5B5101E040010BA
+:1023D0004400C000B401820015D5F51006020000CB
+:1023E000B401820015D5351017FEBFE004010011BD
+:1023F000B401820017D5B51017FEFFE0C4038010AA
+:10240000BA9004103A888518170080103A880B108B
+:1024100080C7178017FE3FE1006C2280B401820064
+:1024200017ADB61017FDFFE00E0780181780A0D07B
+:102430003A88091040D81580060300007401020193
+:1024400004722621C0D902803A8801003A8837E018
+:102450001701C0DF170000DF0402C0DE3A2800F8D1
+:1024600004FBFFDE1504C0DF150300DF040300DFFB
+:1024700015FD3FE117FDBFE015FFBFE017FFBFE00F
+:1024800017028010170380103700801015FEBFE080
+:1024900017FEBFE00C20801026030010740102011B
+:1024A00004752621C0D902803A8801003A8837E0B5
+:1024B0001701C0DF170000DF0402C0DE3A2800F871
+:1024C00004F6FFDE1509C0DF150800DF040800DF91
+:1024D00015F93FE115FB3FE0D4FFBF0015FCBFE05D
+:1024E00017F9BFE0170380101712C01017FCBFE0E8
+:1024F0002E04801817F9BFE0170380101712801000
+:1025000015FCBFE015FD3FE0067F000017F9FFE076
+:1025100017FDBFE0C4038010BA9004103A888518F4
+:102520001500001015FE3FE00671000015FF3FE0AA
+:1025300017FEBFE0080280101E320010047E010169
+:10254000404328803A880B1017F9FFE017FDBFE0E1
+:102550006402001117FEBFE03A88852084058010D0
+:10256000BA9004103A8885181500401117F9FFE059
+:1025700017FDBFE06402001117FEBFE03A88852016
+:1025800084058010BA9004103A88851817008010CE
+:102590001E0B00107401020104782621C0D90280AC
+:1025A00017F9BFE01708801017278010170CC0100C
+:1025B0004400C018150CC010C4FABF000669000022
+:1025C00017F9FFE017FDBFE06402001117FEBFE03E
+:1025D0003A88852084058010BA9004103A888518BE
+:1025E0001700801017018010040140013A8809107B
+:1025F00080E8378015FFBFE0047E410117FF3FE10F
+:10260000001C3780F43F80000400941015FBBFE0ED
+:1026100017F9BFE01703001117F9FFE017FDBFE03E
+:1026200044048010BA9004103A8885181700C0102E
+:1026300017FEBFE07A9104103A88871817FF7FE1F0
+:1026400017FCBFE117FBBFE0150080D83A880F30B8
+:102650003A880D283A880B18002A1F8015FABFE027
+:1026600017FABFE026020010C4FFBF00063D0000BD
+:1026700017FEBFE01E06001017F9FFE017FDBFE0D0
+:10268000C4038010BA9004103A8885181500001011
+:1026900017FDBFE0C4038010BA90041017F9FFE0E3
+:1026A0003A88891817F9FFE017FDBFE0440480104D
+:1026B000BA9004103A8885181700C01017FEBFE0C2
+:1026C0007A9104103A8885183A880B1000541F80BC
+:1026D00015FABFE017FABFE026020010C4FFBF00E2
+:1026E0000620000017FEBFE04400801015FEBFE08A
+:1026F00017FEBFE0500280101E8C3F1017FDBFE098
+:102700004400801015FDBFE017FDBFE09000801071
+:102710001E7E3F1017FE7FE174010201048926210D
+:1027200080C7028017F9BFE01514001017F9BFE049
+:102730001513001017F9BFE00401001117F9BFE0ED
+:102740001713801017F9FFE0C4038010BA9004102B
+:102750003A888518170080103A880B1080C71780B8
+:102760003A8805003A8837E01701C0DF170000DF1C
+:102770000402C0DE3A2800F804F9FFDE1506C0DFC7
+:10278000150500DF040500DF15FB3FE115FF3FE005
+:10279000063E0000047E01014043288015FEBFE094
+:1027A00017FEBFE01E05001074010201049A2621E5
+:1027B000C0D90280440080000638000017FBBFE04B
+:1027C000171380103A000510CC3F801017FBFFE074
+:1027D00044048010BA9004103A8885181700C0107D
+:1027E00017FFBFE07A9104103A88851815FDBFE005
+:1027F00017FBBFE0171380103A000510CC3F801084
+:1028000017FBFFE06402001117FFBFE03A88852044
+:1028100084058010BA9004103A88851817FEFFE0EE
+:102820001500C01017FBBFE0171380103A00051009
+:10283000CC3F801017FBFFE06402001117FFBFE0E0
+:102840003A88852084058010BA9004103A8885184B
+:102850001700801017018010040140013A88091008
+:1028600080E8378015FCBFE0047E410117FC3FE1A2
+:10287000001C378017FCFFE017FDBFE01501C010FA
+:1028800017FFBFE04400801015FFBFE017FFBFE057
+:10289000100280101EBF3F103A8805003A8837E0CA
+:1028A0001701C0DF170000DF0402C0DE3A2800F87D
+:1028B00004FAFFDE1505C0DF150400DF040400DFA5
+:1028C00015FC3FE117FCBFE01713801017FCFFE079
+:1028D00044048010BA9004103A8885181700C0107C
+:1028E00017FCBFE0171480107A9104103A888518FD
+:1028F000040480103700801084FFBF1015FFBFE074
+:1029000017FCBFE017088010172780101709001167
+:1029100017FFFFE017FCBFE0170880101727801093
+:102920003A88C7201509C01017FCBFE01713001123
+:1029300017FCBFE01714801017FCFFE064020021B1
+:102940003A88852084058010BA9004103A8885184A
+:102950001700801015FEBFE017FEBFE017018010C2
+:102960000404C01017FEBFE01503C01017FFBFE03E
+:1029700084FCBF103A88071017FEBFE01504C01092
+:10298000177DA0D03A88071017FEBFE01505C010CC
+:1029900017FCBFE01708C01017FEBFE01506C010F7
+:1029A00017FEBFE0170180108400801015FDBFE006
+:1029B00017FDBFE00B03C01017FEBFE00D08C010ED
+:1029C00017FE7FE1B401020104AB36210099288093
+:1029D00017FCBFE0171480104400C01017FCBFE0C4
+:1029E0001514C0103A8801003A8837E01701C0DF9B
+:1029F000170000DF0402C0DE3A2800F804FCFFDE06
+:102A00001503C0DF150200DF040200DF15FF3FE100
+:102A100015FE7FE17401420104A0662917FF3FE122
+:102A2000003927803A8805003A8837E01701C0DF6F
+:102A3000170000DF0402C0DE3A2800F804FCFFDEC5
+:102A40001503C0DF150200DF040200DF15FE3FE1C1
+:102A500017FEBFE0BA900610B40182003A888518CC
+:102A60001770B710172780108400C0001506C0101B
+:102A700017FEBFE02429C010B40182003A888518EF
+:102A800017C5B5103A880F003A880D003A880B0038
+:102A90003A8809104009208017FEBFE02429C010A1
+:102AA000B40182003A88851817C3B510040280105B
+:102AB0003700801015FFBFE017FEBFE02429C010CB
+:102AC000B40182003A88851817C3B510040280103B
+:102AD00017FF3FE144FFFF003A70C6203500C010E9
+:102AE00017FEBFE0BA900610B40182003A8885183C
+:102AF0001770B710172780108400C0001507C0108A
+:102B00003A8805003A8837E01701C0DF170000DF78
+:102B10000402C0DE3A2800F804FDFFDE1502C0DF23
+:102B2000150100DF040100DF15FF3FE117FFBFE0E3
+:102B3000080480101E03001017FF3FE1000F3780CC
+:102B40000602000017FF3FE100E72C803A8837E0DB
+:102B50001701C0DF170000DF0402C0DE3A2800F8CA
+:102B600004F5FFDE150AC0DF150900DF040900DFE8
+:102B700015F83FE1170FA0D015FFBFE0040FA0D05C
+:102B800015FEBFE00636000017FFBFE017FFFFE0AD
+:102B90001504C01017FFBFE017F8FFE01505C010BF
+:102BA00017FFBFE017058010BA900610B40182002D
+:102BB0003A8885181770F71017FFBFE01506C01088
+:102BC00017FFBFE01703801017FF3FE13AE83E1000
+:102BD00017FFBFE01706801015FDBFE004FA7FE184
+:102BE00004FB3FE104FCFFE004F9BFE0150080D8DE
+:102BF0003A880F283A880D203A880B1817FF3FE1D2
+:102C0000C02301802610001017FCFFE017FDBFE075
+:102C1000150AC01017FBFFE017FDBFE0150CC01030
+:102C200017FAFFE017FDBFE0150DC01017FDFFE01C
+:102C300034018200048EA210152B801817FDBFE00E
+:102C40008400C000052FC01017F8BFE044008010BA
+:102C500015F8BFE017FFBFE01700801015FFBFE0B9
+:102C600017FFFFE017FEBFE01EC7BF1817F8BFE051
+:102C70003A8837E01701C0DF170000DF0402C0DE2A
+:102C80003A2800F804F9FFDE1506C0DF150500DF5D
+:102C9000040500DF15FF3FE115FE7FE115FDBFE1F3
+:102CA00017FFBFE0080480101E05001017FDBFE1EC
+:102CB00017FE7FE117FF3FE140D337800608000091
+:102CC00017FDBFE0150100D8150000D83A880F00A5
+:102CD0003A880D1017FE7FE117FF3FE10093268031
+:102CE0003A8837E01701C0DF170000DF0402C0DEBA
+:102CF0003A2800F804FBFFDE1504C0DF150300DFEF
+:102D0000040300DF15FF3FE115FE7FE115FDBFE184
+:102D100017FFBFE0080480101E05001017FDBFE17B
+:102D200017FE7FE117FF3FE1C0263880060600004E
+:102D300017FDBFE03A880F003A880D1017FE7FE1BB
+:102D400017FF3FE1C0B92C803A8837E01701C0DF98
+:102D5000170000DF0402C0DE3A2800F804FEFFDEA0
+:102D60001501C0DF150000DF3A8839D8048201015F
+:102D7000801C2480260500107401020104AC262169
+:102D8000C0D9028044008000060100003A88050096
+:102D90003A8837E01701C0DF170000DF0402C0DE09
+:102DA0003A2800F804F9FFDE1506C0DF150500DF3C
+:102DB000040500DF15FC3FE115FB7FE117FCBFE0D8
+:102DC000170680101727801015FEBFE0177DE0D092
+:102DD00017FBBFE01506C01017FCBFE017038010FB
+:102DE00004FCFF1017FCBFE01503C01017FCBFE088
+:102DF000170480100404C01017FCBFE01504C010B5
+:102E000017FCBFE0170380108400801015FDBFE0A1
+:102E100017FCBFE01701801017FDFFE02E0380189C
+:102E20007401020104B826218017278017FBBFE038
+:102E300004018010840180013A880B1017FD3FE1E6
+:102E4000807B088017FDBFE08401C01017FEBFE043
+:102E500017058010840180013A880B103A88091800
+:102E6000807B088017FBBFE00B078010CCFFBF10F2
+:102E7000CC008010A00080101E04001017FDBFE0E1
+:102E8000040380100402C0000500C01017FDBFE05D
+:102E9000440380100500001017FCBFE017068010E7
+:102EA000170480102607001017FCBFE017068010DB
+:102EB0001704801017FC3FE13AE83E1015FFBFE011
+:102EC0000612000017FCBFE01706801017038010E1
+:102ED00017FCFFE01706001917FCFFE01703401965
+:102EE00017FCFFE01704C0183A880D183AE83E10A6
+:102EF00015FFBFE08400000180F3288017FC3FE14C
+:102F0000807428808400000140FF288017FFBFE004
+:102F10003A8837E01701C0DF170000DF0402C0DE87
+:102F20003A2800F804FBFFDE1504C0DF150300DFBC
+:102F3000040300DF15FD3FE117FDBFE0170480101B
+:102F400015FFBFE017FDBFE015040010840000016D
+:102F500080F328800609000017FFBFE017008010EB
+:102F600015FEBFE017FFBFE01500001017FF3FE19F
+:102F70008074288017FEBFE015FFBFE017FFBFE099
+:102F80001EF53F1017FDBFE0150000108400000182
+:102F900040FF28803A8801003A8837E01701C0DFF7
+:102FA000170000DF0402C0DE3A2800F804FCFFDE50
+:102FB0001503C0DF150200DF040200DF15FE3FE14C
+:102FC00017FEBFE01704801015FFBFE006090000E0
+:102FD00017FFBFE01700C01017FEBFE01504C010B8
+:102FE00017FFBFE01500001017FE7FE117FF3FE15C
+:102FF000C0CE228017FEBFE01704801015FFBFE08F
+:1030000017FFBFE01EF23F103A8801003A8837E010
+:103010001701C0DF170000DF0402C0DE3A2800F805
+:1030200004F4FFDE150BC0DF150A00DF040A00DF21
+:1030300015F73FE115F67FE117F7BFE0170680109F
+:1030400015FFBFE017F7BFE01706801017278010A5
+:1030500015FEBFE017F6BFE0E0FFBF101E1900101D
+:1030600017FFBFE0170C80103A30860017F6BFE05C
+:103070003A70861817FFBFE0170C80103A308400B2
+:103080002610801817F6BFE03AD6061017F6BFE0F4
+:103090003AD204100CC0BF103AB0861817F6BFE041
+:1030A0003A920410EC3F80103AB0861817F6BFE051
+:1030B0003A9604103AB084182C00FC103400B80082
+:1030C0001E39801817F7BFE0170680103A880B10DA
+:1030D00017F63FE18052238015FCBFE017FCBFE0EC
+:1030E0000401801084018001C43F40013A88091026
+:1030F000408E088017F7BFE017068010172B80104E
+:103100002625001017F6BFE03AD6061017F6BFE0E6
+:103110003AD204100CC0BF103AB0861817F6BFE0C0
+:103120003A920410EC3F80103AB0861817F6BFE0D0
+:103130003A9604103AB084182C00FC103400B80001
+:103140001E15801817F6BFE015F8BFE017FCBFE0AA
+:103150004400C0000501C01017FCBFE0450100108D
+:1031600017FCBFE08417C0008501C01043F8BFE022
+:10317000CC1F80103A88071017FCBFE0C501C010B3
+:1031800083F8FFE017FCBFE00502C010C3F8FFE0C2
+:1031900017FCBFE04502C01017FC7FE117F73FE1C5
+:1031A000C0CE228006AE000017F7BFE01707C010A0
+:1031B00017F7BFE017068010170A80101E0D801841
+:1031C00017F7BFE017078010CC3F8010E01F80107A
+:1031D0001E0800108400000180F3288017F73FE1EB
+:1031E000807428808400000140FF2880C4F7BF005D
+:1031F000069B00008400000180F32880040C00017D
+:103200004043288015FDBFE017FDBFE01E060010FB
+:1032100017F73FE1807428808400000140FF288078
+:1032200084FABF00068E00008400000140FF288061
+:1032300017FDBFE01701C01017FDBFE01503C01058
+:1032400017FDBFE0040CC0001504C01017F7BFE065
+:103250001706C01017FDBFE01506C01017F7BFE036
+:10326000170680103A880B1017F63FE18052238032
+:1032700015FCBFE017FCBFE017F7FFE01504C01016
+:1032800017FDBFE0170180108400801015FBBFE020
+:1032900017FDBFE0170180100404801015FABFE08D
+:1032A00017FABFE00440C0000D00C01017FABFE0DD
+:1032B0000402C0008D00C01017FABFE08401C000F6
+:1032C0000501C01017FABFE00401C0004501C0109D
+:1032D00017FABFE00440C0008D01C01017FABFE02C
+:1032E00017F6FFE01507C01017F7BFE017068010AC
+:1032F000170AC01017FABFE01504C01017FABFE094
+:103300000402C01017FEBFE0170580108401800181
+:103310003A880B103A880918807B08808401800164
+:10332000C43F400117FB3FE1408E088017FBBFE020
+:103330008401C01017FEBFE01705801084018001D2
+:103340003A880B103A880918807B088017FBBFE089
+:10335000040380100402C0000500C01017FBBFE08A
+:10336000440380108401C0000500C01017FABFE0BC
+:1033700015F9BFE017F9BFE00402C01017FABFE06B
+:1033800004028010840180013A880B103A880918E1
+:10339000807B088017F9BFE08403C01017FABFE0F4
+:1033A00004048010040180013A880B103A8809183F
+:1033B000807B088017F9BFE08404C01017FABFE0D3
+:1033C00004058010840180013A880B103A8809189E
+:1033D000807B088017F9BFE00406C01017FABFE031
+:1033E00004078010040180013A880B103A880918FC
+:1033F000807B088017FFBFE01704801026050010AF
+:1034000017FFBFE01704801017FD3FE13AE83E10B8
+:10341000060F000017FFBFE01703801017FDFFE045
+:103420001706001917FDFFE01701C018040C8001F2
+:103430003A880B183AE83E108400000180F3288097
+:1034400017FD3FE1807428808400000140FF288040
+:103450001761A0D0440080101561A0D04400800006
+:103460003A8837E01701C0DF170000DF0402C0DE32
+:103470003A2800F804F8FFDE1507C0DF150600DF64
+:10348000040600DF15FA3FE115FE3FE015FD3FE0C1
+:1034900015FC3FE0177DA0D015FBBFE0B401820012
+:1034A0000466B61015FFBFE0063B000017FFBFE043
+:1034B00017048010260B001017FFBFE017058010BF
+:1034C00017FBFFE03AC88518701980101E1700100E
+:1034D00017FF3FE1C0E6228017FFBFE01500001094
+:1034E0000612000017FFBFE017008010260F001023
+:1034F00017FFBFE01705801017FBFFE03AC88518DB
+:103500003A8807101711A0D01608801817FFBFE0DF
+:103510001706801017FBFFE03AC8851810198010B5
+:103520001E02001017FFBFE01500001017FFBFE0DC
+:103530001700801017FAFFE01E03801817FFBFE086
+:1035400015FEBFE00611000017FFBFE01700801056
+:10355000260A001017FDBFE02605001017FFBFE088
+:103560001706C01017FDBFE0170680102E07801841
+:1035700017FFBFE015FDBFE00604000017FCBFE029
+:103580001E02001017FFBFE015FCBFE017FFBFE0F1
+:103590000408801015FFBFE017FFFFE0B4018200B0
+:1035A00004A6B61036C1BF1817FEBFE01E060010F5
+:1035B00017FCBFE02602001017FCBFE00603000066
+:1035C00017FDBFE00601000017FEBFE03A8837E0B4
+:1035D0001701C0DF170000DF0402C0DE3A2800F840
+:1035E00004FAFFDE1505C0DF150400DF040400DF68
+:1035F00015FD3FE115FC7FE1177DA0D015FFBFE071
+:1036000017FD3FE1C03B238015FEBFE017FEBFE082
+:10361000170480102606001017FEBFE01700801068
+:1036200017FDFFE02602801817FE3FE1C0E622806A
+:1036300017FEBFE017FDFFE01500C01017FEBFE04A
+:1036400017FCFFE01503C01017FEBFE00D070010C8
+:1036500017FEBFE004018010840180013A880B004E
+:103660003A880910408E088017FEBFE017FFFFE080
+:103670001506C01017FEBFE01706C01017FEBFE00A
+:103680001505C010175DA0D01E0700103A880D0068
+:1036900004C44901B400020104310F2140C738803D
+:1036A000155DA0D006070000175DA0D01702C0105E
+:1036B000175DA0D03A88091017FFBFE03A88851837
+:1036C0001503802017FEBFE03A8837E01701C0DFFE
+:1036D000170000DF0402C0DE3A2800F804F7FFDE1E
+:1036E0001508C0DF150700DF040700DF15F93FE10B
+:1036F0008400000180F32880040C000140432880EE
+:1037000015FFBFE08400000140FF288017FFBFE0E5
+:103710001E02001040CD2880069B000017F9BFE074
+:103720001706C01017FFBFE01506C01017F9BFE05D
+:103730001703801084FCBF1015FEBFE017FFBFE029
+:10374000170180108400801015FDBFE017FDBFE059
+:10375000040380100402C0000500C01017FDBFE084
+:10376000440380108401C0000500C01017F9BFE0B9
+:103770001703801015FCBFE017FFBFE01701801092
+:103780000404801015FBBFE017FFBFE0040CC0006D
+:103790001504C01017FBBFE00440C0000D00C010AE
+:1037A00017FBBFE00402C0008D00C01017FBBFE094
+:1037B0008401C0000501C01017FBBFE00401C00078
+:1037C0004501C01017FBBFE00480C0008D01C01090
+:1037D00017FCBFE01704C01017FBBFE01507C010AF
+:1037E00017FCBFE01707C01017FBBFE01504C0109F
+:1037F00017FBBFE00405C01017FCBFE004028010F7
+:10380000840180013A880B103A880918807B08806F
+:1038100017FBBFE00402C01017FFBFE017068010BF
+:103820001727801017058010840180013A880B103B
+:103830003A880918807B088017FEBFE08401801059
+:10384000840180013A880B1017FD3FE1807B0880DE
+:1038500017FDBFE08401C01017FFBFE017068010FE
+:103860001727801017058010840180013A880B10FB
+:103870003A880918807B088017FBBFE015FABFE083
+:1038800017FABFE00402C01017FBBFE0040280106B
+:10389000840180013A880B103A880918807B0880DF
+:1038A00017FABFE08403C01017FBBFE004048010C8
+:1038B000040180013A880B103A880918807B08803F
+:1038C00017FABFE08404C01017FBBFE004058010A6
+:1038D000840180013A880B103A880918807B08809F
+:1038E00017FABFE00406C01017FBBFE00407801002
+:1038F000040180013A880B103A880918807B0880FF
+:1039000017FFBFE01706801017048010260A00106A
+:1039100017FFBFE01701C01017FFBFE01503C0106D
+:1039200017FFBFE0170680101704801017FF3FE154
+:103930003AE83E100611000017FFBFE0170680109E
+:103940001703801017F9FFE01706001917FFFFE0B3
+:103950001701401917FFFFE01704C0183A880D1827
+:103960003AE83E108400000180F3288017FF3FE111
+:10397000807428808400000140FF28801763A0D055
+:10398000440080101563A0D03A8837E01701C0DFEB
+:10399000170000DF0402C0DE3A2800F804F9FFDE59
+:1039A0001506C0DF150500DF040500DF15FB3FE14C
+:1039B00017FBBFE01703801084FCBF1015FEBFE0AB
+:1039C00017FBBFE01703801015FDBFE017FDBFE038
+:1039D00015FCBFE017FDBFE00407C01017FCBFE0F7
+:1039E00004068010040180013A880B103A880918F7
+:1039F000807B088017FDBFE00405C01017FCBFE006
+:103A000084048010840180013A880B103A880918D8
+:103A1000807B088017FDBFE00404C01017FCBFE0E6
+:103A200084038010040180013A880B103A88091839
+:103A3000807B088017FDBFE00402C01017FCBFE0C8
+:103A400004028010840180013A880B103A8809181A
+:103A5000807B088017FDBFE01707C01017FBBFE091
+:103A600017068010170A8010261C801817FDBFE06B
+:103A7000170780103AD6061017FDBFE01707801011
+:103A80003AD204100CC0BF103AB0861817FDBFE040
+:103A9000170780103A920410EC3F80103AB0861855
+:103AA00017FDBFE0170780103A9604103AB084184B
+:103AB0002C00FC103400B800260880188400000197
+:103AC00080F3288017FB3FE1807428808400000188
+:103AD00040FF2880840080000644000017FDBFE0FE
+:103AE0008B018010CCFFBF10184080101E0D0010FD
+:103AF0001760A0D0440080101560A0D017FB3FE1F4
+:103B00004062238017FDBFE01704C01017FBBFE021
+:103B1000170680103A880B103A88091880522380C3
+:103B2000060300001762A0D0440080101562A0D0E8
+:103B3000B40182000466B61015FFBFE00620000045
+:103B400017FFBFE01700C01017FDBFE0170480107B
+:103B50001E18801817FFBFE00401C01017FDBFE05A
+:103B600004028010840180013A880B103A880918F9
+:103B7000807B0880177DE0D017FFBFE01506C010DE
+:103B800017FFBFE0170480102602001017FF3FE167
+:103B900040EF22808400000180F3288017FB3FE182
+:103BA000807428808400000140FF28803A88050046
+:103BB000060E000017FFBFE00408801015FFBFE0ED
+:103BC00017FFFFE0B401820004A6B61036DCBF1870
+:103BD0008400000180F3288017FB3FE18074288077
+:103BE0008400000140FF2880840080003A8837E08C
+:103BF0001701C0DF170000DF0402C0DE3A2800F81A
+:103C000004F8FFDE1507C0DF150600DF040600DF3D
+:103C100015FB3FE115FA7FE1177DA0D015FCBFE051
+:103C200017FABFE01E0800108400000180F328800E
+:103C300017FB3FE1807428808400000140FF28804A
+:103C400084FABF0006480000175FA0D017FCFFE011
+:103C50003AC88518701980101E010010155E20D01A
+:103C6000175EA0D026070010175EA0D017008010A6
+:103C700017FAFFE01E038018175EA0D015FFBFE003
+:103C80000603000017FA3FE1C03B238015FFBFE0A9
+:103C900017FFBFE01700801017FAFFE01E2D8018F5
+:103CA00017FFBFE01704801026210010B401820026
+:103CB0001798B710880080101E09001084000001BA
+:103CC00080F3288017FB3FE1807428808400000186
+:103CD00040FF288084FABF0015FEBFE006210000E7
+:103CE00017FFBFE01704801015FDBFE006030000BA
+:103CF00017FDBFE01700801015FDBFE017FDBFE006
+:103D0000170080101EFA3F1017FDBFE017FBFFE001
+:103D10001500C01017FBBFE017008010260100102F
+:103D200040CD28804400800015FEBFE0060D000055
+:103D300017FFBFE0155EA0D017FCBFE0155FA0D055
+:103D400017FF7FE117FB3FE1C0CE228015FEBFE0E9
+:103D50000604000017FA7FE117FB3FE180F622809E
+:103D600015FEBFE017FEBFE03A8837E01701C0DF5D
+:103D7000170000DF0402C0DE3A2800F804FAFFDE74
+:103D80001505C0DF150400DF040400DF15FC3FE16A
+:103D900015FE3FE0177DA0D015FDBFE0B401820005
+:103DA0000466B61015FFBFE00627000017FFBFE04E
+:103DB000170080102621001017FFBFE017048010A5
+:103DC000260B001017FFBFE01705801017FDFFE05E
+:103DD0003AC88518701980101E05001017FF3FE1C2
+:103DE000C0E6228017FFBFE0150000100613000098
+:103DF00017FFBFE01705801017FDFFE03AC88518D0
+:103E00003A8807101711A0D01609801817FFBFE0D5
+:103E10001706801017FDFFE03AC8851810198010AA
+:103E20001E03001017FFBFE015000010060300007E
+:103E300017FEBFE04400801015FEBFE017FFBFE093
+:103E40000408801015FFBFE017FFFFE0B4018200F7
+:103E500004A6B61036D5BF1817FEBFE01E0400102A
+:103E6000175DA0D03A88091000DA3880155D20D09F
+:103E70003A8801003A8837E01701C0DF170000DFF9
+:103E80000402C0DE3A2800F804F7FFDE1508C0DFA0
+:103E9000150700DF040700DF15FA3FE115F97FE1A0
+:103EA00017FABFE01727801015FFBFE0840000015C
+:103EB00080F32880040C00014043288015FEBFE0F9
+:103EC00017FEBFE01E0400108400000140FF2880A0
+:103ED00084FABF00069500008400000140FF28809E
+:103EE00017FEBFE01701C01017FEBFE01503C0109A
+:103EF00017FEBFE0040CC0001504C01017FEBFE0A1
+:103F000017FAFFE01506C01017FEBFE0170180107A
+:103F10008400801015FDBFE017FEBFE01701801080
+:103F20000404801015FCBFE017FCBFE00440C00093
+:103F30000D00C01017FCBFE00402C0008D00C010CF
+:103F400017FCBFE08401C0000501C01017FCBFE0F2
+:103F50000401C0004501C01017F9BFE01E040010A5
+:103F600017FCBFE00440C0008D01C0100603000034
+:103F700017FCBFE00480C0008D01C01017FABFE03D
+:103F8000170AC01017FCBFE01507C01017FABFE0F2
+:103F9000170AC01017FCBFE01504C01017FCBFE0E3
+:103FA0000402C01017FFBFE01705801084018001D4
+:103FB0003A880B103A880918807B088084018001B8
+:103FC000C43F400117FD3FE1408E088017FDBFE070
+:103FD0008401C01017FFBFE0170580108401800125
+:103FE0003A880B103A880918807B088017FDBFE0DB
+:103FF000040380100402C0000500C01017FDBFE0DC
+:10400000440380108401C0000500C01017FCBFE00D
+:1040100015FBBFE017FBBFE00402C01017FCBFE0B8
+:1040200004028010840180013A880B103A88091834
+:10403000807B088017FBBFE08403C01017FCBFE043
+:1040400004048010040180013A880B103A88091892
+:10405000807B088017F9BFE01E09001017FBBFE046
+:104060008404C01017FCBFE00405801084018001A7
+:104070003A880B103A880918807B088006080000EF
+:1040800017FBBFE08404C01017FCBFE004028010DF
+:10409000840180013A880B103A880918807B0880D7
+:1040A00017FBBFE00406C01017FCBFE00407801038
+:1040B000040180013A880B103A880918807B088037
+:1040C00017FABFE0170480102605001017FABFE0AA
+:1040D0001704801017FE3FE13AE83E10060F00007B
+:1040E00017FABFE01703801017FEFFE0170600194C
+:1040F00017FEFFE01701C018040C80013A880B1866
+:104100003AE83E108400000180F3288017FE3FE16A
+:10411000807428808400000140FF28801761A0D0AF
+:10412000440080101561A0D0440080003A8837E038
+:104130001701C0DF170000DF0402C0DE3A2800F8D4
+:1041400004FCFFDE1503C0DF150200DF040200DF00
+:1041500015FE3FE1B401820017A6B61015FFBFE0BF
+:104160000609000017FEBFE0C4FFFF1015FEFFE0C8
+:104170001E02001017FFBFE00607000017FFBFE098
+:104180001700801015FFBFE017FFBFE01EF53F10BE
+:1041900040CD28803A8805003A8837E01701C0DF13
+:1041A000170000DF0402C0DE3A2800F804FDFFDE3D
+:1041B000150200DF040200DF15FF3FE115FE7FE17D
+:1041C00017FEBFE0CC008010260E001017FEBFE0E7
+:1041D0000B008010CCFFFF10D4FFBF002602801818
+:1041E0003A8805000622000017FEBFE08400801018
+:1041F00017008010E0FFBF101E1000103A88050065
+:10420000061B000017FEBFE017008010E0FFBF1084
+:104210001E0200103A8805000615000017FEBFE0D8
+:10422000040180100B008010CCFFFF10D4FFBF00F2
+:10423000260280183A880500060D000017FFBFE02F
+:104240001727801017028010E00580101E0500104F
+:1042500017FFBFE017278010170280101807801083
+:104260001E0200103A88050006010000440080008C
+:104270003A8837E0170000DF0401C0DE3A2800F872
+:1042800004FBFFDE1504C0DF150300DF040300DFBD
+:104290003A8805200DFDBFE0B401820017A6B610D4
+:1042A00015FFBFE00611000017FFBFE017068010E2
+:1042B000260B001017FFBFE0170680100BFDFFE074
+:1042C00017FF7FE13A8809183AE83E1015FEBFE073
+:1042D00017FEBFE02602001017FEBFE00606000032
+:1042E00017FFBFE01700801015FFBFE017FFBFE00A
+:1042F0001EED3F103A8805003A8837E01701C0DF0D
+:10430000170000DF0402C0DE3A2800F804FAFFDEDE
+:104310001505C0DF150400DF040400DF15FC3FE1D4
+:10432000B40182001771B81015FFBFE0061300003A
+:1043300017FFBFE0170180102605001017FFBFE030
+:1043400017018010170A801015FEBFE0060100005B
+:1043500015FE3FE017FFBFE01700801015FDBFE01E
+:1043600017FEFFE017FCBFE01E02801817FF3FE1B9
+:10437000C06F2D8017FDBFE015FFBFE017FFBFE046
+:104380001EEB3F103A8801003A8837E01701C0DF82
+:10439000170000DF0402C0DE3A2800F804FCFFDE4C
+:1043A0001503C0DF150200DF040200DF15FF3FE048
+:1043B000063C000017FFBFE0BA900610B40182006F
+:1043C0003A8885181770B7101727801017028010C9
+:1043D000980180101E1C001017FFBFE0BA90061055
+:1043E000B40182003A8885181770B7101709801039
+:1043F0001E07001017FFBFE0BA900610B40182003C
+:104400003A8885181770B710847AC1001509C01052
+:1044100017FFBFE0BA900610B40182003A888518F1
+:104420001770B710170880101E07001017FFBFE0A5
+:10443000BA900610B40182003A8885181770B71038
+:104440000404C0001508C01017FFBFE0BA900610A2
+:10445000B40182003A8885181770B71017088010C9
+:104460001764E0D00E01C0103A8805181564A0D07A
+:1044700017FFBFE0BA900610B40182003A88851891
+:104480001770B710170980101765E0D00E01C01023
+:104490003A8805181565A0D017FFBFE044008010CA
+:1044A00015FFBFE01767A0D03A88071017FFBFE0DD
+:1044B00016C0FF10B401820015AC3610B4018200A2
+:1044C00017ACF610B401820015ABF610B4018200EF
+:1044D00015AD3610B401820017ADF610B40182009C
+:1044E00015AFF610B401820017AFF610B4018200C8
+:1044F00015AEF6108400000180F32880801A288011
+:1045000015FEBFE08400000140FF288017FEBFE0D9
+:104510002602001017FEBFE006CF0000B400020123
+:1045200004391221401E258015FF3FE006C500001A
+:1045300017FFBFE0BA900610B40182003A888518D0
+:104540001770B710170280102677001017FFBFE012
+:10455000BA900610B40182003A8885181770B71017
+:104560001702801017FF3FE13AE83E1015FEBFE04A
+:1045700017FEBFE0260E001017FFBFE117FE7FE118
+:104580007401020104BD262180C7028017FFBFE02D
+:10459000BA900610B40182003A8885181770B710D7
+:1045A000172780108400C0001507C01006A2000065
+:1045B00017FFBFE0BA900610B40182003A88851850
+:1045C0001770B710172780101702801098018010FD
+:1045D0001E0D001017FFBFE0BA900610B401820054
+:1045E0003A8885181770B710172AC01017FFBFE058
+:1045F000BA900810B40182003A8885201770B7106D
+:104600005400C018152AC01017FFBFE0BA9006105A
+:10461000B40182003A8885181770B71017278010E8
+:104620004400C0001506C01017FFBFE0BA90061086
+:10463000B40182003A8885181770B7100301801002
+:10464000CC3F80101C20801004E0BF101E360010EC
+:1046500017FFBFE0BA900610B40182003A888518AF
+:104660001770B7101727801017028010980180105C
+:104670001E0F001017FFBFE0BA900610B4018200B1
+:104680003A8885181770B7104419C0000501C0108A
+:1046900017FFBFE0BA900610B40182003A8885186F
+:1046A0001770B710041DC0004501C010060E0000B1
+:1046B00017FFBFE0BA900610B40182003A8885184F
+:1046C0001770B710441AC0000501C01017FFBFE0F3
+:1046D000BA900610B40182003A8885181770B71096
+:1046E0008419C0004501C01017FFBFE0440C8010C2
+:1046F0003A88091017FFBFE0BA900610B401820093
+:104700003A8885181770B7103A8807208501C010BD
+:1047100017FFBFE0BA900610B40182003A888518EE
+:104720001770B710C501001017FF3FE1407B2480D0
+:1047300017FFBFE0BA900610B40182003A888518CE
+:104740001770B710170A8010263B001017FFBFE044
+:10475000BA900610B40182003A8885181770B71015
+:10476000170A001117FFBFE0BA900610B4018200CB
+:104770003A8885181770B710170C80103A308600E9
+:1047800017FFBFE0BA900A10B40182003A8885286A
+:104790001770B7103AB0C620150EC01017FFBFE053
+:1047A000BA900610B40182003A8885181770B710C5
+:1047B000170A001117FFBFE0BA900610B40182007B
+:1047C0003A8885181770B710170CC01017FFBFE094
+:1047D000BA900A10B40182003A8885281770B71081
+:1047E0003A70C620150FC01017FFBFE0BA90061030
+:1047F000B40182003A8885181770B710170A0011A3
+:1048000017FFBFE0BA900610B40182003A888518FD
+:104810001770B710170C80103A30860017FFBFE0F2
+:10482000BA900A10B40182003A8885281770B71030
+:104830003AB0C6201510C01017FFBFE0440080102A
+:1048400015FFBFE01767A0D03A88071017FFBFE039
+:104850001637FF103A8805003A8837E01701C0DFA5
+:10486000170000DF0402C0DE3A2800F804FCFFDE77
+:104870001503C0DF150200DF040200DF15FE3FE173
+:1048800017FEBFE0BA900610B40182003A8885187E
+:104890001770B710170C80101E3A001017FEBFE0FB
+:1048A000BA900610B40182003A8885181770B710C4
+:1048B000170A80100C2080101E03001034C0BF00A7
+:1048C00015FFBFE0061B000017FEBFE0BA90061000
+:1048D000B40182003A8885181770B710170A801043
+:1048E0000C308010182080101E030010F4FFBF0051
+:1048F00015FFBFE0060F000017FEBFE0BA900610DC
+:10490000B40182003A8885181770B710170A801012
+:104910000C388010183080101E03001004C0BF0037
+:1049200015FFBFE00603000040CD288004C0BF0093
+:1049300015FFBFE017FFBFE03AD6061017FFBFE034
+:104940003AD204100CC0BF103AB0861817FFBFE06F
+:104950003A920410EC3F80103AB0881817FFBFE07D
+:104960003A96061017FEBFE0BA900A10B401820012
+:104970003A8885281770B7103AB0C620150CC010B9
+:10498000060100003A8801003A8837E01701C0DFCD
+:10499000170000DF0402C0DE3A2800F804FCFFDE46
+:1049A0001503C0DF150200DF040200DF15FE3FE043
+:1049B0001766A0D00C0180102603001074010201BC
+:1049C00004C42621C0D90280B401820017A6B61003
+:1049D00015FFBFE00621000017FFBFE0170580109C
+:1049E000260F001017FFBFE0172780101701801057
+:1049F0003A880B107401020104C9262180C7028085
+:104A000017FFBFE01705C01017FEBFE044000011FC
+:104A100015FE3FE13A8809103AE83E18060C0000FE
+:104A20001766A0D00C0180102606001017FFBFE00B
+:104A3000040180103A880B107401020104D0262171
+:104A400080C7028017FEBFE04400801015FEBFE063
+:104A500017FFBFE01700801015FFBFE017FFBFE092
+:104A60001EDD3F103A8801003A8837E01701C0DFA9
+:104A7000170000DF0402C0DE3A2800F804F9FFDE68
+:104A80001506C0DF150500DF040500DF15FF3FE058
+:104A900006D9000017FFBFE04400C01015FFFFE07B
+:104AA000B401C20017DDF7180E02801840CE27802F
+:104AB00015FF3FE04400000180F32880B4010201AB
+:104AC00004AB3621808D288015FEBFE04400000134
+:104AD00040FF288017FEBFE01E0300107401020192
+:104AE00004D726218017278017FEBFE01706801005
+:104AF00015FDBFE017FDBFE01727801015FCBFE0D4
+:104B000017FEBFE017018010840080103A880B1058
+:104B100017FD3FE1400F24802606001017FCBFE080
+:104B2000170B80104400C01017FCBFE0150BC0101D
+:104B30000605000017FCBFE0170A80104400C010F3
+:104B400017FCBFE0150AC01017FCBFE01706801065
+:104B5000980080101E0C00108400000180F3288053
+:104B600017FE3FE1807428808400000140FF288008
+:104B700017FCBFE0170C80104400C01017FCBFE00A
+:104B8000150CC010069C000017FEBFE01701801036
+:104B900004FFBF1003008010CC3F80101C20801049
+:104BA00004E0BF10581380101E0B001017FEBFE06A
+:104BB0001701C01017FEBFE0170280103A88851851
+:104BC00003008010CC3F80101C20801004E0BF1038
+:104BD000601380101E04001040CD28807401020173
+:104BE00004DD26218017278017FDBFE0172A8010DB
+:104BF0000C0280101E49001017FDBFE0172780101F
+:104C000017028010980180101E36001017FEBFE0BA
+:104C1000170180108400801015FBBFE017FBBFE078
+:104C20000403801003008010CC3F80101C208010F3
+:104C300004E0BF103A9204103A88071017FBBFE057
+:104C40004403801003008010CC3F80101C20801093
+:104C500004E0BF10CC3F80103A888518CCFFBF100D
+:104C60003AD204103A88071017FBBFE00403801003
+:104C700003008010CC3F80101C20801004E0BF1087
+:104C80003A9204103A88091017FBBFE044038010E1
+:104C900003008010CC3F80101C20801004E0BF1067
+:104CA000CC3F80103A888520CCFFBF103A92041088
+:104CB0003AB084183A88071017FEBFE00D08C010FC
+:104CC00017FEBFE01701801017FEFFE01706C0189F
+:104CD0001708C0183A88C71017FEBFE01503C010A8
+:104CE000060F000017FDBFE0172780101702801085
+:104CF0003A880B107401020104E3262180C7028068
+:104D00008400000180F3288017FE3FE18074288032
+:104D10008400000140FF2880063700003A88010027
+:104D200017FEBFE00B088010CCFFBF102002C010A0
+:104D30001E030018208281101E080010060E0000BD
+:104D40003A88090080F3288017FE3FE180663B80A7
+:104D50003A88090040FF2880062600003A880900AA
+:104D600080F3288017FE3FE1408E23803A880900B7
+:104D700040FF2880061F00001766A0D00C0081109D
+:104D80002610001017FEBFE00B088010CCFFBF10EC
+:104D90003AD20410CCFFBF10CC3FC01017FEBFE0CA
+:104DA0000B088010CCFFBF103A920410CCFFBF104C
+:104DB0003AB084183A880B107401020104EB2621E2
+:104DC00080C7028017FDBFE017278010170EC010A4
+:104DD0004400C018150EC0108400000180F3288024
+:104DE00017FE3FE1807428808400000140FF288086
+:104DF0003A8801003A880100B401820017ADB6106C
+:104E00001E243F103A8801003A8837E01701C0DFBE
+:104E1000170000DF0402C0DE3A2800F804FDFFDEC0
+:104E2000150200DF040200DF15FF3FE115FE7FE100
+:104E3000177DA0D00E0C0010177DE0D017FFBFE04B
+:104E400036038018177DE0D017FEBFE02E068018CD
+:104E5000177DA0D017FFFFE0360A8018177DA0D07D
+:104E600017FEFFE03607801817FFFFE017FEBFE0D0
+:104E70002E02801817FFBFE00608000017FEBFE0F3
+:104E80000606000017FFFFE017FEBFE0360280189D
+:104E900017FFBFE00601000017FEBFE03A8837E0C9
+:104EA000170000DF0401C0DE3A2800F804FBFFDE33
+:104EB0001504C0DF150300DF040300DF15FE3FE12A
+:104EC00015FD7FE117FEBFE0170680101727801041
+:104ED00015FFBFE017FFBFE0170680109800801095
+:104EE0001E0800108400000180F3288017FE3FE1B7
+:104EF000807428808400000140FF2880C4F7BF0030
+:104F00000648000017FEBFE0170680101708801043
+:104F10002608001017FFBFE017028010E005801080
+:104F20001E04001017FFBFE0170280101807801042
+:104F30001E29001017FFBFE0171080104400C0109A
+:104F400017FFBFE01510C01017FFBFE0170FC0100C
+:104F500017FEBFE0170480103A88871817FFBFE0DC
+:104F6000150FC01017FEBFE0170680101704801041
+:104F70002606001017FEBFE01706801017048010E9
+:104F800017FE3FE13AE83E100611000017FEBFE0B1
+:104F9000170680101703801017FEFFE01706001990
+:104FA00017FEFFE01703401917FEFFE01704C018B3
+:104FB0003A880D183AE83E108400000180F32880FA
+:104FC00017FE3FE1807428808400000140FF2880A4
+:104FD0003A8805000613000017FEBFE01706801090
+:104FE000170A80101E0C001017FEBFE01707801074
+:104FF000E0FFBF101E0800108400000180F328802D
+:1050000017FE3FE1807428808400000140FF288063
+:1050100084F8BF000603000017FD7FE117FE3FE1A3
+:1050200080B423803A8837E01701C0DF170000DF23
+:105030000402C0DE3A2800F804FCFFDE1503C0DFDE
+:10504000150200DF040200DF15FF3FE0062200002A
+:1050500017FFBFE02430C010B401820004B0B610C6
+:105060003A88871817FFBFE0BA900810B401820091
+:105070003A8885201570F71017FFBFE0BA90061028
+:10508000B40182003A8885181770F71017FFBFE047
+:10509000BA900810B40182003A8885201770B710C2
+:1050A0000412C0181527C01017FFBFE0BA900610F1
+:1050B000B40182003A8885181770B7103A880B102F
+:1050C000B401020104A636210099288017FFBFE031
+:1050D0004400801015FFBFE017FFBFE010018010F3
+:1050E0001EDB3F101767A0D03A88091080563C801D
+:1050F0001567A0D01767A0D01E03001074018200AE
+:1051000004FCA610066000001767A0D015FFBFE0E2
+:105110000611000017FFBFE0BA900610B40182002C
+:105120003A8885181770B7103A880B10B40102013D
+:1051300004A6362100A4288017FFBFE0BA9006100D
+:10514000B40182003A8885181570371017FFBFE048
+:105150004400801015FFBFE017FFBFE01001801072
+:105160001EEC3F1000DE2880F4000201048623219B
+:10517000401E2580402E248015FEBFE017FEBFE0B4
+:1051800026030010740182000406A710063E0000EA
+:1051900040CA228015FEBFE017FEBFE026040010C3
+:1051A000C024258074018200040DA710063600007B
+:1051B00000073A8015FEBFE017FEBFE0260400108E
+:1051C000C0242580740182000414A710062E00005C
+:1051D000C037258015FEBFE017FEBFE02603001094
+:1051E000C02425801712A0D00627000015FF3FE03D
+:1051F0000617000017FFBFE0BA900610B401820046
+:105200003A8885181770B710172B8010260D0010DC
+:1052100017FFBFE0BA900610B40182003A888518E3
+:105220001770B710040180013A880B10046B20D16D
+:10523000C02A3C801E030010C02425801712A0D075
+:105240000611000017FFBFE04400801015FFBFE00B
+:105250001767A0D03A88071017FFBFE016E5FF10C8
+:10526000C037368015FEBFE017FEBFE026040010F1
+:10527000C024258074018200041AA71006020000D1
+:1052800000613C803A8805003A8837E01701C0DFAA
+:10529000170000DF0402C0DE3A2800F804FDFFDE3C
+:1052A0001502C0DF150100DF040100DF15FF3FE13B
+:1052B0001768A0D0900380101E0300107401020133
+:1052C00004212721801727801768A0D04400801070
+:1052D0001568A0D01768A0D0BA90081017FFFFE09B
+:1052E000740182003A888520156EF3103A88010017
+:1052F0003A8837E01701C0DF170000DF0402C0DE84
+:105300003A2800F804FDFFDE1502C0DF150100DFBA
+:10531000040100DF1768A0D015FFBFE0061D0000E4
+:1053200017FFBFE0BA900610740182003A88851812
+:10533000176EB3103A880B10740102010424272160
+:1053400080C7028017FFBFE0BA9006107401820088
+:105350003A888518176EB310260B001017FFBFE0B0
+:10536000BA900610740182003A888518176EB3103F
+:105370003AE83E1017FFBFE0BA90061074018200B1
+:105380003A888518156E331017FFBFE0C4FFBF10B1
+:1053900015FFBFE017FFBFE01EE13F103A88010094
+:1053A0003A8837E01701C0DF170000DF0402C0DED3
+:1053B0003A2800F804FBFFDE1504C0DF150300DF08
+:1053C000040300DF15FD3FE1B401820017A6B6100B
+:1053D00015FEBFE015FF3FE0060B000017FEFFE0E3
+:1053E00017FDBFE01E02801817FFBFE0060C00008B
+:1053F00017FEBFE01700801015FEBFE017FFBFE0EB
+:105400004400801015FFBFE017FEBFE01EF33F1001
+:1054100074010201042B2721801727803A88050098
+:105420003A8837E01701C0DF170000DF0402C0DE52
+:105430003A2800F804FEFFDE150100DF040100DF5A
+:105440003440800004388010156BA0D03480800078
+:1054500004388010156CA0D0B401820017A6B610D5
+:1054600015FFBFE00610000017FFBFE0032F8010FC
+:10547000CC3F8010580080101E04001017FFBFE0C2
+:105480004400C000052DC0100604000017FFBFE057
+:10549000052D001017FFBFE0152E001017FFBFE00D
+:1054A0001700801015FFBFE017FFBFE01EEE3F1092
+:1054B000177DA0D004058010156AA0D0156920D0F2
+:1054C0003A8805003A8837E0170000DF0401C0DEA3
+:1054D0003A2800F804FBFFDE1504C0DF150300DFE7
+:1054E000040300DF15FD3FE1B40182001774B7101B
+:1054F0004400C010B40182001574F71017FD3FE19D
+:1055000040B8258015FFBFE017FFBFE01E18001050
+:1055100017FDBFE017068010032F8010C5FEBFE007
+:10552000C3FEBFE06000C0101E030018A000801082
+:105530001E0400100606000017FD3FE1C0DF3D809D
+:105540000613000017FD3FE140063E8006100000F4
+:10555000B40182001781B7104400C010B40182006A
+:105560001581F710C4FFBF0015FFBFE00601000062
+:105570003A8801008400000180F3288017FD3FE194
+:10558000807428808400000140FF288017FFBFE05E
+:105590003A8837E01701C0DF170000DF0402C0DEE1
+:1055A0003A2800F804FCFFDE1503C0DF150200DF17
+:1055B000040200DF3A88090080F328801769A0D030
+:1055C0001E0300103A88090040FF2880064C0000A6
+:1055D000B401820017A6B61015FEBFE00640000019
+:1055E00017FEBFE0172C801015FFBFE00637000044
+:1055F00017FFBFE0170080102630001017FFBFE034
+:1056000017038010262E001017FFBFE0170380102D
+:10561000C4FFFF1017FFBFE01503C01017FFBFE066
+:10562000170380101E26001017FEBFE0032D801008
+:10563000CC3F80102604001017FF7FE18404000196
+:10564000C06525800603000017FF7FE18405000187
+:10565000C065258017FEBFE0032F8010CC3F80106F
+:10566000980080101E11001017FFBFE04400C0001A
+:105670000504C01017FEBFE0032D8010CC3F801042
+:10568000260A001017FEBFE0172EC0101410A70046
+:105690003A888718177DA0D02E04801817FEBFE027
+:1056A000052D001017FEBFE0152E00101769A0D0C1
+:1056B000C4FFBF101569A0D0060100003A880100A0
+:1056C00017FFBFE01705801015FFBFE017FFBFE011
+:1056D0001EC73F1017FEBFE01700801015FEBFE089
+:1056E00017FEBFE01EBE3F10177DA0D0040580103E
+:1056F000156AA0D03A88090040FF28803A88010046
+:105700003A8837E01701C0DF170000DF0402C0DE6F
+:105710003A2800F804DEFFDE1521C0DF152000DF87
+:10572000042000DF3A88052015E07FE105E1BFE0B5
+:105730000405800085E2BFE0C5E23FE01764A0D029
+:1057400004078010C5FDBFE003E1BFE0E005801065
+:105750001E03001003E1BFE0980580101E03001037
+:10576000C3FDBFE004018010C5FDBFE0840000015F
+:1057700080F32880C3FDBFE03A88091040432880A9
+:1057800015FCBFE08400000140FF288017FCBFE04B
+:105790001E060010B40182001780B7104400C0102C
+:1057A000B40182001580F7100674000017FCBFE0FA
+:1057B0001703801015FBBFE017E0BFE01701801052
+:1057C000170AC01017FBBFE01503C01003E1BFE0CC
+:1057D000D80580101E040010176CE0D017FBBFE046
+:1057E0001504C0100604000017E0BFE01700C01049
+:1057F00017FBBFE01504C01017FBBFE01704C01073
+:1058000017FCBFE01507C01017FCBFE0170380109E
+:105810000405801015FFBFE003E1BFE0E005801044
+:105820001E03001003E1BFE0980580101E06001063
+:1058300017FFBFE00401801015FFBFE084E2BFE066
+:1058400015FEBFE00603000084E2BFE044008010C4
+:1058500015FEBFE017FFBFE015FABFE017FABFE083
+:1058600003E1FFE00500C01017FABFE0450000109B
+:1058700017E0BFE01700C01017FABFE01501C01015
+:1058800017FABFE08D0000100401400117FA3FE154
+:10589000C0D726803A3084003A88071017FABFE054
+:1058A0008D00C01004E3BFE015F9BFE004168001CD
+:1058B0003A880B0017F93FE1408E088017E0BFE0FF
+:1058C0001701C01017F9BFE01500C01017F9BFE0AD
+:1058D0004400C0000501C01017F9BFE045010010E9
+:1058E00017FCBFE017FFFFE01503C01017FCBFE077
+:1058F0000402C0001504C01017FCBFE017F9FFE058
+:10590000150BC01017FEBFE117FC7FE184000001FA
+:1059100080BF3A8003E1BFE0D80580101E0600106A
+:10592000B4018200178BB7104400C010B40182008C
+:10593000158BF7100611000003E1BFE098058010F9
+:105940001E060010B4018200178CB7104400C0106E
+:10595000B4018200158CF7100608000003E1BFE0D7
+:10596000980480101E050010B4018200178AB71039
+:105970004400C010B4018200158AF7103A8837E05D
+:105980001701C0DF170000DF0402C0DE3A2800F86C
+:1059900004FCFFDE1503C0DF150200DF040200DF98
+:1059A00015FE3FE117FEBFE01701801015FFBFE0B5
+:1059B00017FEBFE01700C010176BA0D01E038018A1
+:1059C00017FEBFE0150300100677000017FFBFE0C9
+:1059D000032D8010CC3F80102634001017FE7FE18D
+:1059E00084040001C0652580B40182001751F910BC
+:1059F000B40182001770B710170A80103AD6081049
+:105A0000B40182001770B710170A80103AD2041040
+:105A10000CC0BF103AB08820B40182001770B710D4
+:105A2000170A80103A920410EC3F80103AB0882098
+:105A3000B40182001770B710170A80103A9604104C
+:105A40003AB084203A88871817FEBFE0170080100C
+:105A50003AD6081017FEBFE0170080103AD20410A3
+:105A60000CC0BF103AB0882017FEBFE017008010AE
+:105A70003A920410EC3F80103AB0882017FEBFE045
+:105A8000170080103A9604103AB084203A8885189E
+:105A9000840C40013A880910C0050D804400C010F4
+:105AA00017FEBFE01503C0100633000017FE7FE1AC
+:105AB00084050001C0652580B40182001751F910EA
+:105AC000B40182001770B710170A80103AD6081078
+:105AD000B40182001770B710170A80103AD2041070
+:105AE0000CC0BF103AB08820B40182001770B71004
+:105AF000170A80103A920410EC3F80103AB08820C8
+:105B0000B40182001770B710170A80103A9604107B
+:105B10003AB084203A88871817FEBFE0170080103B
+:105B20003AD6081017FEBFE0170080103AD20410D2
+:105B30000CC0BF103AB0882017FEBFE017008010DD
+:105B40003A920410EC3F80103AB0882017FEBFE074
+:105B5000170080103A9604103AB084203A888518CD
+:105B6000840C40013A880910C0050D804400C01023
+:105B700017FEBFE01503C01017FFBFE0032F801012
+:105B8000CC3F8010980080101E03001017FEBFE06D
+:105B90004400C0000504C0101769A0D04400801064
+:105BA0001569A0D03A8801003A8837E01701C0DFB4
+:105BB000170000DF0402C0DE3A2800F804FCFFDE14
+:105BC0001503C0DF150200DF040200DF15FE3FE110
+:105BD00017FEBFE01701801015FFBFE017FFBFE001
+:105BE000032F8010CC3F8010980080101E0D0010F5
+:105BF00017FFBFE0032D8010CC3F80101E0900105E
+:105C000017FEBFE003048010CC3F801058008010C6
+:105C10001E04001017FE7FE1C4050001C065258049
+:105C20003A8801003A8801003A8837E01701C0DF5E
+:105C3000170000DF0402C0DE3A2800F804F6FFDE99
+:105C40001509C0DF150800DF040800DF15F83FE183
+:105C500017F8BFE01703801015FFBFE017F8BFE08B
+:105C60001704C01017FFBFE003008010CC3F801066
+:105C7000BA9004100C0F80103AC8851815FEBFE0CA
+:105C800017FEBFE0200280101E070010B401820042
+:105C9000177EB7104400C010B4018200157EF710C3
+:105CA00004F8BF000697000017FFBFE00300801054
+:105CB000CC3F8010BA9004100C0F801017FFFFE04B
+:105CC0003A88851815FDBFE017FDBFE08B008010F6
+:105CD0008DFCBFE017FDBFE08D00001017FEBFE098
+:105CE0007AD005103A880B1017FD3FE1C0D7268007
+:105CF0003A3084000DFCBFE00BFCFFE08BFCBFE002
+:105D0000260A801817FDBFE08BFCFFE08D00C01055
+:105D1000B4018200177FB7104400C010B4018200A4
+:105D2000157FF71004F8BF000676000017FDBFE0EE
+:105D300003008010C5FBBFE017FDBFE01701801016
+:105D40003AD6061017FDBFE0170180103AD20410B2
+:105D50000CC0BF103AB0861817FDBFE017018010C5
+:105D60003A920410EC3F80103AB0861817FDBFE05D
+:105D7000170180103A9604103AB0841815FABFE063
+:105D800017FDBFE043008010C5F9BFE0C3FBBFE0D3
+:105D9000580480101E2C0010C3F9BFE02604001028
+:105DA000C3F9BFE0260D001017FABFE01E0B00106C
+:105DB00017FFBFE01704C010176BA0D0260780188C
+:105DC000B40182001782B7104400C010B4018200F1
+:105DD0001582F71004F8BF00064A0000C3F9BFE0BF
+:105DE0002619001017FABFE02617001017F8BFE0B9
+:105DF00017068010032F8010CC3F801058008010B1
+:105E00001E02001004F8BF00063E000017FABFE0B3
+:105E10002C00FC103400B8001E04801817FDBFE0F1
+:105E20001701C010176BA0D01E078018B4018200A4
+:105E30001785B7104400C010B40182001585F71013
+:105E400004F8BF00062F0000C3FBBFE0A0048010D1
+:105E50001E030010C3FBBFE0980580101E10001049
+:105E600017FDBFE01701C01017FFBFE01704801037
+:105E70001E04801817FABFE02C00FC103400B80094
+:105E800026078018B40182001783B7104400C010A1
+:105E9000B40182001583F71004F8BF000619000052
+:105EA000C3FBBFE0E00580101E0A0010C3FBBFE08B
+:105EB000A00580101E070010C3FBBFE0580480102F
+:105EC0001E0F001017FDBFE043008010CC3F801074
+:105ED000260B001017FF3FE140573E80CC3F80105B
+:105EE0001E070010B40182001788B7104400C010CC
+:105EF000B40182001588F71004F8BF000601000005
+:105F00003A8805003A8837E01701C0DF170000DF44
+:105F10000402C0DE3A2800F804FAFFDE1505C0DFEF
+:105F2000150400DF040400DF15FE3FE1B401820028
+:105F300017A6B61015FFBFE0063B000017FFBFE035
+:105F40000401C01017FFBFE0032F8010CC3F0011E9
+:105F500017FFBFE0032F8010CC3F80105800801047
+:105F60001E03001074018200042EA7100602000018
+:105F700074018200042FA710150080D83A880F20E2
+:105F80003A880D18740142010430672917FE3FE179
+:105F90000039278017FFBFE0032F8010CC3F80100F
+:105FA000980080101E19001017FFBFE0032D80100D
+:105FB000CC3F401117FFBFE0032D8010CC3F801075
+:105FC000580080101E030010740182000435A710D1
+:105FD00006020000740182000437A71017FFFFE0DB
+:105FE000172EC018177D20D1150100D91500C0D873
+:105FF0003A880F103A880D28740142010439672944
+:1060000017FE3FE1003927800604000074014201B9
+:106010000444672917FE3FE10039278017FFBFE0DE
+:106020001700801015FFBFE017FFBFE01EC33F1031
+:10603000B40182001774B7101769E0D03A880F18BE
+:106040003A880D10740142010445672917FE3FE1AB
+:1060500000392780B40182001775B7103A880D10F7
+:10606000740142010452672917FE3FE1003927807D
+:10607000B40182001776B7103A880D1074014201FE
+:106080000463672917FE3FE100392780B4018200CD
+:106090001777B7103A880D1074014201046F672911
+:1060A00017FE3FE100392780B40182001778B7104E
+:1060B0003A880D10740142010482672917FE3FE1FE
+:1060C00000392780B40182001779F710B4018200EB
+:1060D000177AB7103A880F103A880D1874014201E8
+:1060E0000493672917FE3FE100392780B40182003D
+:1060F000177BB7103A880D1074014201046F6729AD
+:1061000017FE3FE100392780B4018200177CB710E9
+:106110003A880D107401420104A6672917FE3FE179
+:1061200000392780B4018200177DB7103A880D101E
+:106130007401420104B7672917FE3FE10039278047
+:10614000B4018200178BF710B4018200178CB710CE
+:106150003A880F103A880D187401420104C3672968
+:1061600017FE3FE100392780B4018200178AB7107B
+:106170003A880D107401420104D6672917FE3FE1E9
+:1061800000392780B4018200177EB7103A880D10BD
+:106190007401420104E2672917FE3FE100392780BC
+:1061A000B4018200177FB7103A880D1074014201C4
+:1061B00004EE672917FE3FE100392780B401820011
+:1061C0001780F710B40182001781B7103A880F10BA
+:1061D0003A880D187401420104FA672917FE3FE15D
+:1061E00000392780B40182001782F710B4018200C1
+:1061F0001783B7103A880F103A880D1874014201BE
+:10620000040E682917FE3FE100392780B40182009F
+:106210001785B7103A880D1074014201041E6829D1
+:1062200017FE3FE100392780B40182001786B710BE
+:106230003A880D1074014201042B682917FE3FE1D2
+:1062400000392780B40182001787B7103A880D10F3
+:1062500074014201043E682917FE3FE1003927809E
+:10626000B40182001788B7103A880D1074014201FA
+:10627000044F682917FE3FE100392780B4018200EE
+:106280001784B7103A880D1074014201046168291F
+:1062900017FE3FE100392780B40182001789B7104B
+:1062A0003A880D10740142010471682917FE3FE11C
+:1062B000003927803A8805003A8837E01701C0DFA7
+:1062C000170000DF0402C0DE3A2800F804F4FFDE05
+:1062D000150BC0DF150A00DF040A00DF15F83FE1E7
+:1062E00015F77FE115F6BFE117F8BFE004FCBF101A
+:1062F000BA90041015FEBFE0B40182000471B8101A
+:1063000015FFBFE00606000017FFFFE017FEBFE025
+:106310002606801817FFBFE01700801015FFBFE0AA
+:1063200017FFBFE01EF83F10060100003A88010089
+:1063300017FFFFE017FEBFE02603801840CD28803E
+:10634000C4FFBF000624000017F7BFE026070010B7
+:1063500017F6BFE01E05001017FEBFE08403C00063
+:106360001506C010C4FFBF00061B000004F9BFE003
+:1063700017F6BFE13A880B1017F83FE140D22B80A7
+:1063800015FDBFE017FDBFE0E0FFBF101E110010BC
+:1063900017F7BFE0260F001017F6BFE017008010B8
+:1063A000700480101E03001017F6BFE00404C00044
+:1063B0001500C01017F6BFE0170080103A880710CC
+:1063C00004F9BFE03A880D183A880B1017F73FE13F
+:1063D000806B088017FDBFE03A8837E01701C0DF07
+:1063E000170000DF0402C0DE3A2800F804F3FFDEE5
+:1063F000150CC0DF150B00DF040B00DF15F73FE1C4
+:1064000015F67FE115F5BFE117F7BFE004FCBF10FB
+:10641000BA90041015FEBFE0B40182000471B810F8
+:1064200015FFBFE00606000017FFFFE017FEBFE004
+:106430002606801817FFBFE01700801015FFBFE089
+:1064400017FFBFE01EF83F10060100003A88010068
+:1064500017FFFFE017FEBFE02603801840CD28801D
+:10646000C4FFBF000624000017F5BFE01E050010A2
+:1064700017FEBFE08403C0001506C010C4FFBF00B4
+:10648000061D000017F5BFE01700801015F8BFE0EB
+:1064900004F8FFE004F9BFE03A880D183A880B10C1
+:1064A00017F73FE1401E2C8015FDBFE017FDBFE050
+:1064B000E0FFBF101E0F001017F8BFE0700480103F
+:1064C0001E0200100404800015F8BFE017F8BFE0BA
+:1064D0003A88071004F9BFE03A880D183A880B1083
+:1064E00017F63FE1806B088017F8FFE017F5BFE073
+:1064F0001500C01017FDBFE03A8837E01701C0DF74
+:10650000170000DF0402C0DE3A2800F804F3FFDEC3
+:10651000150CC0DF150B00DF040B00DF15F73FE1A2
+:1065200015F67FE115F5BFE117F7BFE004FCBF10DA
+:10653000BA90041015FEBFE0B40182000471B810D7
+:1065400015FFBFE00606000017FFFFE017FEBFE0E3
+:106550002606801817FFBFE01700801015FFBFE068
+:1065600017FFBFE01EF83F10060100003A88010047
+:1065700017FFFFE017FEBFE02603801840CD2880FC
+:10658000C4FFBF000624000017F5BFE01E05001081
+:1065900017FEBFE08403C0001506C010C4FFBF0093
+:1065A000061D000017F5BFE01700801015F8BFE0CA
+:1065B00004F8FFE004F9BFE03A880D183A880B10A0
+:1065C00017F73FE180222C8015FDBFE017FDBFE0EB
+:1065D000E0FFBF101E0F001017F8BFE0700480101E
+:1065E0001E0200100404800015F8BFE017F8BFE099
+:1065F0003A88071004F9BFE03A880D183A880B1062
+:1066000017F63FE1806B088017F8FFE017F5BFE051
+:106610001500C01017FDBFE03A8837E01701C0DF52
+:10662000170000DF0402C0DE3A2800F804FDFFDE98
+:10663000150200DF040200DF15FF3FE115FE7FE1D8
+:1066400017FEBFE0202080101E49001017FEBFE09B
+:10665000482080101E25001017FEBFE008038010A0
+:106660001E14001017FEBFE0880280101E480010A4
+:1066700017FEBFE0200180101E41001017FEBFE092
+:10668000480180101E04001017FEBFE0E0008010DB
+:106690001E4300100644000017FEBFE020028010D9
+:1066A0001E37001017FEBFE0600280101E3600107B
+:1066B000063D000017FEBFE0200480101E300010D1
+:1066C00017FEBFE0480480101E04001017FEBFE054
+:1066D000880380101E340010062F000017FEBFE054
+:1066E000200880101E260010062F000017FEBFE0B5
+:1066F000C80184101E0E001017FEBFE04801841070
+:106700001E1D001017FEBFE0204080101E1C001050
+:1067100017FEBFE0104080101E23001017FEBFE0E0
+:10672000C4FFBB10A80080101E1F0010061400003C
+:1067300017FEBFE0880584101E07001017FEBFE09B
+:10674000080584101E08001017FEBFE048028410E0
+:106750001E150010060A000017FEBFE0A0058410F9
+:106760001E070010061000003A880500060F000002
+:1067700004028000060D000084008000060B00006B
+:1067800004018000060900000401800006070000E3
+:10679000440080000605000004028000060300009B
+:1067A00004018000060100003A8805003A8837E0BD
+:1067B000170000DF0401C0DE3A2800F804F5FFDE10
+:1067C000150AC0DF150900DF040900DF15FB3FE1F2
+:1067D00015FA7FE115F9BFE115F8FFE117FBBFE0FE
+:1067E00004FCBF10BA90041015FEBFE0B401820093
+:1067F0000471B81015FFBFE00606000017FFFFE0A8
+:1068000017FEBFE02606801817FFBFE017008010B4
+:1068100015FFBFE017FFBFE01EF83F1006010000A4
+:106820003A88010017FFFFE017FEBFE0260380183B
+:1068300040CD2880C4FFBF00061D000017F97FE18E
+:1068400017FA3FE14057268015FDBFE0170280E0B0
+:1068500026040010170280E01700C01017FDBFE0EB
+:106860000E05801817FEBFE08403C0001506C01097
+:10687000C4FFBF00060E000017FDBFE0150080D862
+:1068800017F8FFE117F9BFE117FA7FE117FB3FE1C6
+:10689000C0602C8015FCBFE017FCBFE01E03001099
+:1068A000170280E017FDFFE01500C01017FCBFE0E5
+:1068B0003A8837E01701C0DF170000DF0402C0DEAE
+:1068C0003A2800F804F5FFDE1508C0DF150700DFE1
+:1068D000040700DF15FB3FE115FA7FE1150280E1B7
+:1068E0001503C0E117FBBFE004FCBF10BA90041011
+:1068F00015FEBFE0B40182000471B81015FFBFE0BF
+:106900000606000017FFFFE017FEBFE0260680180E
+:1069100017FFBFE01700801015FFBFE017FFBFE0B3
+:106920001EF83F10060100003A88010017FFFFE043
+:1069300017FEBFE02603801840CD2880C4FFBF00AB
+:1069400006170000040280E015FDBFE017FABFE063
+:10695000980584101E0E001017FDBFE00401C01042
+:1069600015FDFFE01700801015FCBFE004FCFFE000
+:1069700004018000150080D83A880F18840584012E
+:10698000C4FF7F0117FB3FE1C0442C8006040000D8
+:1069900017FEBFE08405C0001506C010C4FFBF008D
+:1069A0003A8837E01701C0DF170000DF0404C0DEBB
+:1069B0003A2800F804FDFFDE1502C0DF150100DFF4
+:1069C000040100DF15FF3FE117FFBFE03A8809101F
+:1069D000C0FB26803A8837E01701C0DF170000DFD0
+:1069E0000402C0DE3A2800F804F0FFDE150FC0DF15
+:1069F000150E00DF040E00DF15F73FE115F67FE10D
+:106A000015F5BFE115F4FFE115F83FE017F7BFE01A
+:106A100004FCBF10BA90041015FEBFE0B401820060
+:106A20000471B81015FFBFE00606000017FFFFE075
+:106A300017FEBFE02606801817FFBFE01700801082
+:106A400015FFBFE017FFBFE01EF83F100601000072
+:106A50003A88010017FFFFE017FEBFE02603801809
+:106A600040CD2880C4FFBF00062B0000170280E045
+:106A7000260A0010170380E01E05001017FEBFE075
+:106A80008403C0001506C010C4FFBF00062200002A
+:106A9000170380E01700801015F8BFE004F8BFE08E
+:106AA000150180D804F9BFE0150080D817F4FFE184
+:106AB00017F5BFE117F67FE117F73FE100872C805C
+:106AC00015FDBFE017FDBFE0E0FFBF101E11001075
+:106AD000170280E0260F001017F8BFE07004801046
+:106AE0001E0200100404800015F8BFE017F8BFE094
+:106AF0003A88071004F9BFE03A880D183A880B105D
+:106B0000170200E1806B088017F8FFE0170380E0B0
+:106B10001500C01017FDBFE03A8837E01701C0DF4D
+:106B2000170000DF0402C0DE3A2800F804F8FFDE98
+:106B30001507C0DF150600DF040600DF15FD3FE185
+:106B400015FC7FE115FBBFE115FAFFE1170280E0BC
+:106B5000264C00100419800015FEBFE017FEBFE0B0
+:106B600010FA80101E0E0010170280E0170280102D
+:106B7000840C8010041940013A88091000F00C8040
+:106B80003A88071017FEBFE03A38851804C4490157
+:106B90003A88091000F00C8015FFBFE006310000B4
+:106BA00017FEBFE0101980101E0E0010170280E0C3
+:106BB00017028010047D801004FA40013A88091001
+:106BC00000F00C803A88071017FEBFE03A388518AD
+:106BD00004FA40013A88091000F00C8015FFBFE06C
+:106BE0000620000017FEBFE0900280101E0E00106D
+:106BF000170280E01702801004E2841004C44901E7
+:106C00003A88091000F00C803A88071017FEBFE0A0
+:106C10003A388518041940013A88091000F00C80B0
+:106C200015FFBFE0060F0000170280E01702C0103A
+:106C300014D4B0003A888518B400400104A8612932
+:106C40003A88091000F00C803A88071017FEBFE060
+:106C50003A388518840240013A88091000F00C8007
+:106C600015FFBFE0170200E1170080201701C020C8
+:106C70002419C01017FFBFE03A88851815FFBFE040
+:106C800006020000C4FFBF0015FFBFE017FFFFE1D1
+:106C900017FABFE117FB7FE117FC3FE1803F30802F
+:106CA0003A8837E01701C0DF170000DF0402C0DEBA
+:106CB0003A2800F804F7FFDE1508C0DF150700DFEB
+:106CC000040700DF15FD3FE115FC7FE115FBBFE187
+:106CD00015FAFFE117FDBFE004FCBF10BA900410E5
+:106CE00015FEBFE0B40182000471B81015FFBFE0CB
+:106CF0000606000017FFFFE017FEBFE0260680181B
+:106D000017FFBFE01700801015FFBFE017FFBFE0BF
+:106D10001EF83F10060100003A88010017FFFFE04F
+:106D200017FEBFE02603801840CD2880C4FFBF00B7
+:106D30000612000017FB7FE117FC3FE14057268059
+:106D40003A880710170280E00E05C01017FEBFE05A
+:106D50008403C0001506C010C4FFBF000607000072
+:106D6000170280E0150080D817FAFFE117FBBFE19A
+:106D700017FC7FE117FD3FE1C0442C803A8837E0E3
+:106D80001701C0DF170000DF0402C0DE3A2800F858
+:106D900004FAFFDE150500DF040500DF15FC3FE106
+:106DA00015FB7FE117FCBFE015FFBFE015FE3FE0DC
+:106DB00017FBBFE015FDBFE00608000017FFBFE0AE
+:106DC0008400C01015FFFFE00B008010CCFFBF1047
+:106DD00017FEFFE03A88851815FEBFE017FDBFE0FB
+:106DE000C4FFBF1015FDBFE017FDBFE00EF33F105D
+:106DF00017FEBFE0CCFFFF1017FEBFE03AD404102F
+:106E00003A88851815FEBFE017FEBFE0CCFFFF10E3
+:106E100017FEBFE03AD404103A88851815FEBFE08B
+:106E200017FEBFE03A8837E0170000DF0401C0DE3C
+:106E30003A2800F804FCFFDE1503C0DF150200DF6E
+:106E4000040200DF15FF3FE115FE7FE11713A0D01C
+:106E5000A00080101E04001017FE7FE117FF3FE125
+:106E600080CD26800603000017FE7FE117FF3FE17B
+:106E700000B428803A8837E01701C0DF170000DF30
+:106E80000402C0DE3A2800F804FEFFDE1501C0DF70
+:106E9000150000DF3A8839D840CD28803A880500AF
+:106EA0003A8837E01701C0DF170000DF0402C0DEB8
+:106EB0003A2800F804FEFFDE150100DF040100DFC0
+:106EC00015FF3FE10603000017FFBFE044008010FC
+:106ED00015FFBFE017FFBFE003008010CC3F80101C
+:106EE0001C20801004E0BF10480880101EF63F10E0
+:106EF0000603000017FFBFE04400801015FFBFE04D
+:106F000017FFBFE003008010CC3F80101C208010D2
+:106F100004E0BF10200880101EF63F1017FFBFE0EE
+:106F20003A8837E0170000DF0401C0DE3A2800F895
+:106F300004F8FFDE1507C0DF150600DF040600DFDA
+:106F400015FC3FE115FB7FE115FABFE117FBBFE040
+:106F500015FFBFE0063F000015FE3FE0060D0000F4
+:106F600017FFFFE017FEBFE03A8885180300801086
+:106F7000CC3F80103A880D107401420104816829C9
+:106F800017FC3FE10039278017FEBFE04400801066
+:106F900015FEBFE017FEBFE0280480101E0300109E
+:106FA00017FEFFE017FABFE036EDBF1815FE3FE011
+:106FB0000616000017FFFFE017FEBFE03A888518AD
+:106FC00003008010C5FDBFE0C7FDBFE010088010C2
+:106FD0001E050010C7FDBFE0E01F80101E0200105C
+:106FE000C7FDBFE006010000840B80003A880D1049
+:106FF000740142010483682917FC3FE100392780AE
+:1070000017FEBFE04400801015FEBFE017FEBFE092
+:10701000280480101E03001017FEFFE017FABFE0DF
+:1070200036E4BF18740142010484682917FC3FE16B
+:107030000039278017FAFFE017FEBFE03AC885182D
+:1070400015FABFE017FFFFE017FEBFE03A8885188A
+:1070500015FFBFE017FABFE01EBF3F103A880100DE
+:107060003A8837E01701C0DF170000DF0402C0DEF6
+:107070003A2800F804FAFFDE1505C0DF150400DF2A
+:10708000040400DF15FE3FE117FEBFE015FFBFE07F
+:1070900003FFBFE0CC3F001143FFBFE0CC3F4011F6
+:1070A00083FFBFE0CC3F8010C3FFFFE0CC3FC018A0
+:1070B0001501C0D8150080D83A880F283A880D20CD
+:1070C0007401420104856829B401020184913721C9
+:1070D00080D94280B40182008491B7103A8837E0A9
+:1070E0001701C0DF170000DF0402C0DE3A2800F8F5
+:1070F00004F8FFDE1507C0DF150600DF040600DF19
+:1071000015FC3FE117FCBFE0041940013A88091063
+:1071100080FF0C8015FCBFE017FCBFE0040F4001AE
+:107120003A880910C0050D8015FFBFE017FCBFE0CD
+:10713000040F40013A88091080FF0C8015FCBFE065
+:1071400017FCBFE0040F40013A880910C0050D800C
+:1071500015FEBFE017FCBFE0040F40013A8809109C
+:1071600080FF0C8015FCBFE017FCBFE00406400167
+:107170003A880910C0050D8015FDBFE017FCBFE07F
+:10718000040640013A88091080FF0C8015FCBFE01E
+:1071900017FCBFE0260C001017FFBFE0150180D8D8
+:1071A00017FEBFE0150080D817FDFFE117FCBFE117
+:1071B000740142010488682974010201047D3321AD
+:1071C00080D942800613000017FDBFE0260A001098
+:1071D00017FFBFE0150080D817FEFFE117FDBFE1E4
+:1071E00074014201048E682974010201047D332177
+:1071F00080D942800607000017FFFFE117FEBFE1BC
+:10720000740142010493682974010201047D332151
+:1072100080D9428074018200047DB3103A8837E03F
+:107220001701C0DF170000DF0402C0DE3A2800F8B3
+:1072300004FDFFDE1502C0DF150100DF040100DFE1
+:1072400015FF3FE117FF7FE1740102010498282137
+:1072500080C7028040CD288044000001805E3C80D1
+:107260003A8801003A8837E01701C0DF170000DFD5
+:107270000402C0DE3A2800F804FBFFDE150400DF3C
+:10728000040400DF15FD3FE13A88052805FCBFE056
+:10729000B4018200048DB71015FEBFE015FF3FE07A
+:1072A000063F000017FDBFE003008010CC3F8010B8
+:1072B0003AD10410040C80103A88071017FEBFE082
+:1072C0000500C01017FEBFE003008010CC3F801007
+:1072D0001C20801004E0BF10900E80101E060010CD
+:1072E00017FEBFE003008010C40180103A88071029
+:1072F00017FEBFE00500C01017FEBFE0440080107D
+:1073000015FEBFE017FDBFE003008010CC03801026
+:10731000040C80103A88071017FEBFE00500C0106B
+:1073200017FEBFE003008010CC3F80101C208010AF
+:1073300004E0BF10900E80101E06001017FEBFE084
+:1073400003008010C40180103A88071017FEBFE0C8
+:107350000500C01017FEBFE04400801015FEBFE01E
+:1073600007FCBFE02608001017FFBFE048018010AF
+:107370001E05001017FEBFE04400C01015FEFFE020
+:1073800003FCFFE00500C01017FDBFE044008010C3
+:1073900015FDBFE017FFBFE04400801015FFBFE000
+:1073A00017FFBFE0900180101EBE3F1017FEBFE028
+:1073B00005000010B4018200048DB7103A8837E050
+:1073C000170000DF0401C0DE3A2800F804FDFFDEEC
+:1073D000150200DF040200DF15FE3FE117FEBFE0EB
+:1073E00015FFBFE0060D000017FFBFE0030080108F
+:1073F000CC3F80101C20801004E0BF1018178010B4
+:107400001E03001017FFBFE0C40BC0000500C01032
+:1074100017FFBFE04400801015FFBFE017FFBFE07B
+:1074200003008010CC3F80101C20801004E0BF10AF
+:107430001EED3F1017FEBFE03A8837E0170000DF6F
+:107440000401C0DE3A2800F804F3FFDE150AC0DFAD
+:10745000150900DF150840DC150700DC040900DF12
+:1074600015F83FE115F77FE1150280E11503C0E152
+:1074700015FC3FE00427800015FDBFE017F8BFE0D2
+:1074800015FBBFE017FBBFE01E090010040280E0FF
+:1074900015F9BFE017F9BFE03A880B1017F73FE185
+:1074A0008045458015FABFE017FABFE0063B0000B3
+:1074B00017FBBFE0170180101E020010C4FFBF00C1
+:1074C0000636000017F73FE1C0DA028015FABFE088
+:1074D00017FABFE0102780101E04001017FDFFE010
+:1074E00017FABFE03A88851815FDBFE017FDBFE029
+:1074F0003A880910C082298015FCBFE017FCBFE064
+:107500001E02001084FFBF0006240000040280E079
+:1075100015F9BFE017F9BFE03A880D1017F77FE1C2
+:1075200017FC3FE1004D458015FABFE017FC3FE135
+:10753000C0DA02803A88071017FDBFE00E08C010BD
+:1075400074010201049B28218017278017FDBFE0EA
+:10755000C4FFBF1017FCFFE03A8885180500001033
+:1075600017FBBFE01701001417FBBFE01702401420
+:1075700017FC3FE1C0DA02803A880D1017FC7FE16A
+:107580003A8809883AE83E8015FABFE017FC3FE1E7
+:107590000086298040CE278017FABFE004FEFFE670
+:1075A0001703C0DF170200DF170140DC170000DC03
+:1075B0000406C0DE3A2800F804FBFFDE1504C0DF35
+:1075C000150300DF040300DF15FF3FE115FE7FE137
+:1075D00015FDBFE117FE7FE17401020104A228211D
+:1075E00080C7028017FDBFE03A8837E01701C0DF8F
+:1075F000170000DF0402C0DE3A2800F804FAFFDEBC
+:107600001505C0DF150400DF040400DF15FD3FE1B0
+:1076100015FC7FE117FDBFE015FFBFE017FCBFE0E1
+:10762000040540013A88091000F80C801E23001060
+:1076300017FFBFE02621001017FFBFE017038010DF
+:10764000261E00107401420104A3682917FF3FE1C0
+:107650000039278017FFBFE01703801017FFFFE0F6
+:107660001702C0183A8809183AE83E1015FEBFE024
+:1076700017FEBFE01E01001040CE278017FEBFE0BE
+:1076800026F43F1017FEBFE0D8FFBF101E02001007
+:1076900044008000060A0000740142010484682945
+:1076A00017FF3FE10039278017FEBFE0D8068010A2
+:1076B0001E02001044008000060100003A88050008
+:1076C0003A8837E01701C0DF170000DF0402C0DE90
+:1076D0003A2800F804F7FFDE1508C0DF150700DFC1
+:1076E000040700DF15FB3FE115FA7FE115F9BFE163
+:1076F00017FBBFE015FEBFE015FD3FE017F9BFE047
+:107700001500001017FBBFE01E0200103A880500AC
+:107710000669000017FB3FE1C0DA028015FCBFE0FC
+:1077200017FCBFE0160280003A88050006620000E0
+:1077300017FABFE0BA9004103A880910C082298075
+:1077400015FDBFE017FDBFE01E0500103A880500DB
+:107750000659000017FEBFE04400801015FEBFE090
+:1077600017FEBFE003008010CC3F80101C2080106B
+:1077700004E0BF10200880101EF63F10062E000007
+:1077800017F9BFE017008010BA90041017FDFFE052
+:107790003A88851817FEFFE01500C01017F9BFE002
+:1077A000170080104400C01017F9BFE01500C0108A
+:1077B0000603000017FEBFE04400801015FEBFE086
+:1077C00017FEBFE003008010CC3F80101C2080100B
+:1077D00004E0BF10200880101E0A001017FEBFE052
+:1077E00003008010CC3F80101C20801004E0BF10EC
+:1077F0001EF03F100603000017FEBFE0440080109B
+:1078000015FEBFE017FEBFE003008010CC3F8010E4
+:107810001C20801004E0BF10180880101E06001005
+:1078200017FEBFE003008010CC3F80101C208010AA
+:1078300004E0BF101EF03F1017FEBFE003008010F1
+:10784000CC3F80101C20801004E0BF1026040010E4
+:1078500017F9BFE01700C01017FABFE016C8BF182D
+:1078600015FF3FE00610000017FFBFE017FBFFE029
+:107870003A88851803008010CC3F80101C208010AF
+:1078800004E0BF10180880101E04001017FFBFE0AE
+:1078900017FBFFE03A8885180500001017FFBFE0CE
+:1078A0004400801015FFBFE017FFFFE017FCBFE0AA
+:1078B00016EDBF1817FDBFE03A8837E01701C0DFAB
+:1078C000170000DF0402C0DE3A2800F804FCFFDEE7
+:1078D0001503C0DF150200DF040200DF156F20D0A2
+:1078E000C0A5388015FEBFE015FF3FE0061A000076
+:1078F00017FFBFE02406C0107401820004ECB11031
+:107900003A8885183A8809104007298015FEBFE09B
+:1079100017FEBFE0260D00107401020104B52821F6
+:10792000C0D9028017FFBFE0240680100401C010F8
+:107930007401820004ECB1103A8885183A88091065
+:1079400080172780C4FFBF000613000017FFBFE0A9
+:107950004400801015FFBFE01714A0D017FFFFE010
+:1079600016E3BF1880E3388015FEBFE017FEBFE0C6
+:10797000260800107401020104B52821C0D9028034
+:107980007401020104BA282180172780C4FFBF00B8
+:10799000060100003A8805003A8837E01701C0DF89
+:1079A000170000DF0402C0DE3A2800F804FCFFDE06
+:1079B0001503C0DF150200DF040200DF15FE3FE102
+:1079C000C06D388044008000156FA0D01780A0D013
+:1079D000C4FFFFE03A880D18041940013A880910E5
+:1079E00000A61580C3FFBFE0CC3F80102605001025
+:1079F000C3FFBFE0CC3F8010A00280101E0100102A
+:107A000040CD2880176DA0D044008010156DA0D007
+:107A1000B401820017ADB61026EC3F10409C2480C4
+:107A200006EA3F0004FDFFDE1502C0DF150100DF9E
+:107A3000040100DF15FF3FE10602000084000001A1
+:107A4000C0301780176FA0D026FC3F1084000001C3
+:107A5000C0301780176EA0D044008010156EA0D0E3
+:107A600000AB388006F93F0004FEFFDE1501C0DFE1
+:107A7000150000DF3A8839D884000001C030178033
+:107A80003A8801003A8837E01701C0DF170000DFAD
+:107A90000402C0DE3A2800F804FCFFDE1503C0DF54
+:107AA000150200DF040200DF15FE3FE117FEBFE014
+:107AB00003008010CC3F80103A88091000EC16803B
+:107AC000C5FFBFE0C3FFBFE0260A0010C3FFBFE051
+:107AD000201180101E0700107401020104BC28212F
+:107AE000C0D9028040CD28807401020104C9282138
+:107AF000801727803A8801003A8837E01701C0DFF5
+:107B0000170000DF0402C0DE3A2800F804FBFFDEA5
+:107B10001504C0DF150300DF040300DF15FD3FE19E
+:107B200015FF3FE0063D000017FFBFE02403C01033
+:107B3000B40182003A8885181720B8101E3400104E
+:107B400017FFBFE02403001117FDFFE0B40182001E
+:107B50003A8885201520F810177DE0D017FFBFE088
+:107B600024030011B40182003A888520151FF81003
+:107B7000177CE0D017FFBFE00E02801817FFBFE0B0
+:107B8000157CA0D01778A0D0440080101578A0D024
+:107B90003A88090040FF288017FFBFE02403C01087
+:107BA000B40182003A8885181721B810C4FEFFE09E
+:107BB0003A880D18041940013A88091000A615806A
+:107BC000C3FEBFE0CC3F8010980280101E0D001055
+:107BD0001771A0D0440080101571A0D017FFBFE02E
+:107BE0002403C010B40182003A888518151F38108C
+:107BF00017FFBFE02403C010B40182003A88851843
+:107C0000152038103A88090080F32880060D0000FE
+:107C100017FFBFE04400801015FFBFE017FFBFE073
+:107C2000100580101EC03F1017FFBFE0157CA0D0CC
+:107C30003A88090040FF288040CE27803A88090012
+:107C400080F328803A8837E01701C0DF170000DF93
+:107C50000402C0DE3A2800F804FCFFDE1503C0DF92
+:107C6000150200DF040200DF15FE3FE18090108066
+:107C700015FF3FE00624000017FFBFE02403C010FB
+:107C8000B40182003A888518171FB810261B00100F
+:107C900017FFBFE02403C010B40182003A888518A2
+:107CA0001720B81017FEFFE01E14801817FFBFE062
+:107CB0002403C010B40182003A8885181721B81037
+:107CC0003A88091040D8158017FFBFE02403C01080
+:107CD000B40182003A888518151F381017FFBFE0DD
+:107CE0002403C010B40182003A888518152038108A
+:107CF0001779A0D0440080101579A0D017FFBFE0FD
+:107D00004400801015FFBFE017FFBFE01005801092
+:107D10001ED93F10409910803A8801003A8837E018
+:107D20001701C0DF170000DF0402C0DE3A2800F8A8
+:107D300004E2FFDE151DC0DF151C00DF041C00DFA0
+:107D400004E4BFE03A880B10C43F00010022178012
+:107D5000C5FFBFE0C3FFBFE01E04001083F0BFE01B
+:107D600085FFBFE083FFBFE006070000740102014A
+:107D700004CD282180C702807401020104DA282181
+:107D8000801727803A8805003A8837E01701C0DF5E
+:107D9000170000DF0402C0DE3A2800F804FEFFDE10
+:107DA0001501C0DF150000DF3A8839D84400000112
+:107DB000C03017803A8801003A8837E01701C0DFE9
+:107DC000170000DF0402C0DE3A2800F804EFFFDEEF
+:107DD0001510C0DF150F00DF040F00DF15F23FE1C3
+:107DE0007401420104DE682917F23FE1003927805F
+:107DF000174FA0D03A880D107401420104E468299D
+:107E000017F23FE1003927807401420104EC682930
+:107E100017F23FE10039278015FF3FE006500000D0
+:107E200017FFBFE0BA900610B40182003A888518A7
+:107E3000175DB51015FDBFE017FDBFE0264400102B
+:107E400017FDBFE0580080102641001017FDBFE06D
+:107E5000830C8010CC3F801084F33FE1C4F3FFE03B
+:107E60003A880D203A880B183A880910C0C216804B
+:107E700017FDBFE0830C8010CC3F001117FDBFE061
+:107E8000030C8010CC3F8010C4F3FFE0150080D8B5
+:107E90003A880F203A880D187401420104FC6829C1
+:107EA00017F23FE10039278017FDBFE0170280106D
+:107EB0002622001017FDBFE017038010261F0010B8
+:107EC00017FDBFE0170280100401801015FEBFE00F
+:107ED0000603000017FEBFE00401801015FEBFE09E
+:107EE00017FEBFE01700801026FA3F1017FDBFE015
+:107EF0001703801017FDFFE01702C01817FE3FE1BF
+:107F00003AC8C720BAD007183AC8C510BA900410AA
+:107F100015FCBFE017FDBFE017038010BA900410F6
+:107F200017FCFFE13A880D1074014201040469292D
+:107F300017F23FE100392780060600007401420174
+:107F40000408692917F23FE1003927800601000083
+:107F50003A88010017FFBFE04400801015FFBFE022
+:107F600017FFBFE0500580101EAD3F101778A0D05E
+:107F70001779E0D03A880F183A880D107401420141
+:107F8000040C692917F23FE100392780177CA0D043
+:107F90001771E0D03A880F183A880D107401420129
+:107FA0000418692917F23FE1003927803A88050053
+:107FB0003A8837E01701C0DF170000DF0402C0DE97
+:107FC0003A2800F804F5FFDE150AC0DF150900DFC6
+:107FD000040900DF15FA3FE115F97FE115F8BFE16B
+:107FE0003A8805380DF7BFE08400000180F328804F
+:107FF00017F8BFE0040B80103A880910404328802E
+:1080000015FEBFE08400000140FF288017FEBFE09E
+:108010001E0800101766A0D00C80801026030010E8
+:1080200074010201042D2921C0D90280C4FABF00C5
+:108030000686000017FEBFE017018010040BC01079
+:1080400017FEBFE01503C01017FEBFE017F8FFE0F2
+:108050001504C01017FEBFE017FAFFE01507C010A7
+:1080600017FABFE0D8FFBF101E040010B401820051
+:108070001770F71017FEBFE01506C01017F9BFE024
+:108080002607001017FEBFE01703801017F8BFE1A6
+:1080900017F97FE13A880910806B08800617000005
+:1080A00017FEBFE0170380101715E0D03A880B18B1
+:1080B0003A88091000F642801715A0D03A880910B6
+:1080C000C0DA028015FFBFE00609000017FEBFE01E
+:1080D0001703C01017FFBFE03A88851817FFFFE0AD
+:1080E0000500C01017FFBFE04400801015FFBFE07F
+:1080F00017FFFFE017F8BFE036F4BF1817FEBFE028
+:108100001703801004FEFF1017FEBFE01503C01018
+:1081100017FEBFE0170480100402C01017FEBFE076
+:108120001504C01017FEBFE01703801015FDBFE057
+:1081300017FDBFE00402C0000500C01017FDBFE03E
+:108140004500001017FDBFE00D01001017FDBFE056
+:108150000BF7FFE08D01C01017FDBFE08D00001090
+:1081600017F8BFE04C0080102605001017FDBFE097
+:108170000402C01017F8BFE03A8885180500001007
+:1081800017F8BFE0440280107AD004103A880B1030
+:1081900017FD3FE1C0D726803A3084003A880710A7
+:1081A00017FDBFE08D00C01017FEBFE01703801061
+:1081B00004FBBF1015FCBFE017FA3FE180023B80D3
+:1081C0003A88071017FCBFE01503C01017FCBFE08A
+:1081D00017FAFFE01504C0103A88090080F32880E0
+:1081E00017FE7FE144000001809E3A8015FBBFE04E
+:1081F0003A88090040FF288017FBBFE00E080010F6
+:108200001766A0D00C028010260300107401020132
+:1082100004342921C0D9028017FBBFE0060B0000FF
+:10822000B40182001742B9104400C010B4018200AA
+:108230001542F910B40182001749B9104400C0106A
+:10824000B40182001549F9103A8805003A8837E0F0
+:108250001701C0DF170000DF0402C0DE3A2800F873
+:1082600004F8FFDE1507C0DF150600DF040600DF97
+:108270001718E0D01716A0D03A88851815FCBFE073
+:10828000C5FB3FE015FF3FE006780000040D00014C
+:10829000C082298015FABFE017FABFE026800010DF
+:1082A00017FFBFE0300F80101E050010740102019F
+:1082B000043C2921C0D90280C4FFBF00068600000B
+:1082C00017FFBFE0BA90081017FAFFE0B401820070
+:1082D0003A888520159FF71017FABFE015050010A2
+:1082E0001718A0D017FFFFE02E2F80181719A0D065
+:1082F000440180103A880910008A29803A880710C2
+:1083000017FABFE01501C01017FABFE0170180107F
+:108310002665001015FE3FE00609000017FABFE0D1
+:108320001701C01017FEBFE03A8885184413C0003B
+:108330000500C01017FEBFE04400801015FEBFE02E
+:1083400017FEBFE0100180101EF43F1017FABFE0C7
+:108350001701C0101719A0D0040180103A888518A1
+:108360004413C0000500C01017FABFE017018010C9
+:108370000401C01017FABFE01501C01017FABFE0E2
+:1083800017018010264A00101719E0D017FABFE035
+:108390001502C01017FA7FE1B401020104DB372196
+:1083A00000992880062E00001717A0D044018010E5
+:1083B0003A880910008A29803A88071017FABFE026
+:1083C0001501C01017FABFE017018010263A0010FF
+:1083D00015FD3FE00609000017FABFE01701C010C5
+:1083E00017FDBFE03A8885184413C0000500C0108F
+:1083F00017FDBFE04400801015FDBFE017FDBFE092
+:10840000100180101EF43F1017FABFE01701C010D2
+:108410001717A0D0040180103A8885184413C000B3
+:108420000500C01017FABFE0170180100401C0104A
+:1084300017FABFE01501C01017FABFE0170180104E
+:10844000261F00101717E0D017FABFE01502C01062
+:1084500017FA7FE1B40102010496372100992880C0
+:1084600017FFBFE04400801015FFBFE017FFFFE0DB
+:1084700017FCBFE03685BF181718A0D03A88071040
+:10848000B401820015DFF7101716A0D03A88071044
+:10849000B4018200159AF7103A880500060E000014
+:1084A0003A880100060700003A880100060500002E
+:1084B0003A880100060300003A8801000601000026
+:1084C0003A88010017FF7FE174010201044129216C
+:1084D00080C70280C4FFBF003A8837E01701C0DFC1
+:1084E000170000DF0402C0DE3A2800F804FCFFDEBB
+:1084F0001503C0DF150200DF040200DF15FE3FE1B7
+:108500001719E0D017FEBFE02E0280183A88050048
+:10851000062100001717E0D017FEBFE036038018D1
+:10852000B40182001798B7101E050010B4010201B3
+:1085300004DB3721808D288015FFBFE00604000092
+:10854000B401020104963721808D288015FFBFE019
+:1085500017FFBFE01E0200103A880500060E00005B
+:1085600017FFBFE0170180101764E0D03A88C710EA
+:1085700017FFBFE01503C01017FFBFE01504001080
+:1085800017FFBFE01506001017FFBFE04400C00052
+:108590001509C01017FFBFE03A8837E01701C0DFA8
+:1085A000170000DF0402C0DE3A2800F804FBFFDEFB
+:1085B0001504C0DF150300DF040300DF15FD3FE1F4
+:1085C00017FDBFE017008010260C001017FDBFE05C
+:1085D000170980102609001040E92880B4018200A4
+:1085E000179EB7104400C010B4018200159EF7100A
+:1085F00040EF2880C4FFBF00067C000017FDBFE0ED
+:108600001702C0101719A0D01E1D801840E928803D
+:10861000B401820017DBB71015FFBFE0061400009D
+:1086200017FFFFE017FDBFE01E0E801817FD7FE16A
+:1086300074010201044C292180C7028040EF288088
+:1086400040E92880B4018200179DB7104400C01093
+:10865000B4018200159DF71040EF2880C4FFBF00D1
+:108660000662000017FFBFE01700801015FFBFE093
+:1086700017FFBFE01EEA3F1040EF2880062A0000E7
+:1086800017FDBFE01702C0101717A0D01E1D8018DD
+:1086900040E92880B40182001796B71015FFBFE0AB
+:1086A0000614000017FFFFE017FDBFE01E0E801844
+:1086B00017FD7FE1740102010456292180C7028061
+:1086C00040EF288040E92880B4018200179DB71050
+:1086D0004400C010B4018200159DF71040EF2880BF
+:1086E000C4FFBF000641000017FFBFE01700801065
+:1086F00015FFBFE017FFBFE01EEA3F1040EF2880E4
+:108700000609000040E92880B4018200179BB710D9
+:108710004400C010B4018200159BF71040EF288080
+:10872000C4FFBF00063100000401800015FEBFE059
+:108730000617000017FDBFE01701C01017FEBFE0CD
+:108740003AC885003A88851803008010CC3F801015
+:108750001C20801004E0BF10601380101E09001060
+:1087600040E92880B4018200179CB7104400C01073
+:10877000B4018200159CF71040EF2880C4FFBF00B1
+:10878000061A000017FEBFE0C4FFBF1015FEBFE0D1
+:1087900017FEBFE016E7BF0017FDBFE01701C010CE
+:1087A00017FDBFE0170280103A888518030080107B
+:1087B000CC3F80101C20801004E0BF10601380109C
+:1087C0001E09001040E92880B4018200179CB710F0
+:1087D0004400C010B4018200159CF71040EF2880BF
+:1087E000C4FFBF00060100003A8805003A8837E060
+:1087F0001701C0DF170000DF0402C0DE3A2800F8CE
+:1088000004FCFFDE1503C0DF150200DF040200DFF9
+:1088100015FE3FE117FE3FE1404F288015FFBFE006
+:1088200017FFBFE01E19001017FEBFE017098010E8
+:10883000C4FF3F1117FEFFE015090019B0008010BA
+:108840002614001017FEBFE01702C0101719A0D0A1
+:108850001E05801817FE7FE1B401020104DB3721F9
+:1088600000992880060C000017FEBFE01702C01018
+:108870001717A0D01E08801817FE7FE1B40102016F
+:108880000496372100992880060300003A880100E9
+:10889000060100003A8801003A8837E01701C0DF7E
+:1088A000170000DF0402C0DE3A2800F804FFFFDEF4
+:1088B000150000DF3A8839D81719A0D03A8837E078
+:1088C000170000DF0401C0DE3A2800F804F9FFDEDB
+:1088D0001506C0DF150500DF040500DF15FB3FE1CD
+:1088E0008400000180F3288040E92880B4018200E0
+:1088F000179BB71015FCBFE0B4018200179CB7109E
+:1089000015FDBFE0B4018200179DB71015FEBFE052
+:10891000B4018200179EB71015FFBFE040EF28801A
+:108920008400000140FF288074014201046069292D
+:1089300017FB3FE10039278017FCBFE017FDFFE080
+:108940003A880F183A880D107401420104696929A8
+:1089500017FB3FE10039278017FEBFE017FFFFE05C
+:108960003A880F183A880D1074014201047669297B
+:1089700017FB3FE1003927803A8805003A8837E045
+:108980001701C0DF170000DF0402C0DE3A2800F83C
+:1089900004FCFFDE1503C0DF150200DF040200DF68
+:1089A00015FE3FE140E9288017FEBFE01700801068
+:1089B00015FFBFE017FFBFE01E03001040EF288047
+:1089C0003A880500061B000017FFBFE01700C01023
+:1089D00017FEBFE01500C01017FFBFE01500001024
+:1089E00017FEBFE0170080101E02001017FEBFE048
+:1089F0001501001017FEBFE017028010C4FFFF1022
+:108A000017FEBFE01502C01017FEBFE01702C0102E
+:108A100017FEBFE0170480100E04801817FEBFE099
+:108A20001702C01017FEBFE01504C01040EF2880E9
+:108A300017FFBFE03A8837E01701C0DF170000DFFB
+:108A40000402C0DE3A2800F804FCFFDE1503C0DF94
+:108A5000150200DF040200DF15FF3FE115FE7FE194
+:108A600040E9288017FEBFE01500001017FFBFE0A7
+:108A7000170080101E04001017FFBFE017FEFFE074
+:108A80001500C0100604000017FFBFE0170180109A
+:108A900017FEFFE01500C01017FFBFE017FEFFE054
+:108AA0001501C01017FFBFE0170280104400C0106E
+:108AB00017FFBFE01502C01017FFBFE017028010BC
+:108AC00017FFFFE01703C0180E04801817FFBFE060
+:108AD0001702C01017FFBFE01503C01040EF288039
+:108AE0003A8801003A8837E01701C0DF170000DF3D
+:108AF0000402C0DE3A2800F804FAFFDE1505C0DFE4
+:108B0000150400DF040400DF15FD3FE115FC7FE1E3
+:108B100040E9288017FDBFE01700801015FFBFE077
+:108B200015FE3FE0062B000017FFFFE017FCBFE03B
+:108B30001E23801817FEBFE02605001017FFBFE0B8
+:108B40001700C01017FEBFE01500C010060400009B
+:108B500017FFBFE01700C01017FDBFE01500C010E1
+:108B600017FDBFE01701801017FCFFE01E038018FF
+:108B700017FDBFE017FEFFE01501C01017FDBFE0B5
+:108B800017028010C4FFFF1017FDBFE01502C010D0
+:108B900017FDBFE01702C01017FDBFE017048010DB
+:108BA0000E04801817FDBFE01702C01017FDBFE0CC
+:108BB0001504C01040EF288017FCBFE00609000034
+:108BC00017FFBFE015FEBFE017FFBFE017008010E2
+:108BD00015FFBFE017FFBFE01ED33F1040EF288016
+:108BE0003A8805003A8837E01701C0DF170000DF38
+:108BF0000402C0DE3A2800F83A8805000E624001FF
+:108C00003A880D008C00C020260300180B0080203D
+:108C100084000021C4FF7F29F400C2020423E35A28
+:108C20004C00402A7AD00B28CC03802ABA901450EA
+:108C30003A880951BA9014503AC8975A3A6800587D
+:108C40000410002117F0FF213A8885383A80D111AD
+:108C50003A888D4117F1FF213A8885383A80D11141
+:108C60003A888D4117F2FF213A8885383A80D11130
+:108C70003A888D4117F3FF213A8885383A80D1111F
+:108C80003A888D4117F4FF213A8885383A80D1110E
+:108C90003A888D4117F5FF213A8885383A80D111FD
+:108CA0003A888D4117F6FF213A8885383A80D111EC
+:108CB0003A888D4117F7FF213A8885383A80D111DB
+:108CC0003A888D4117F8FF213A8885383A80D111CA
+:108CD0003A888D4117F9FF213A8885383A80D111B9
+:108CE0003A888D4117FAFF213A8885383A80D111A8
+:108CF0003A888D4117FBFF213A8885383A80D11197
+:108D00003A888D4117FCFF213A8885383A80D11185
+:108D10003A888D4117FDFF213A8885383A80D11174
+:108D20003A888D4117FEFF213A8885383A80D11163
+:108D30003A888D4117FFFF213A8885383A80D11152
+:108D40003A888D4104FC7F290EBD3F282604004847
+:108D50000B00C0213A8885383A80D1113A888D417C
+:108D60003AD40E10CCFFBF103A8885383A88853047
+:108D70003AD40E10CCFFBF103A8885383AD40E1082
+:108D8000CCFFBF103A8885383A2800F804FEFFDE91
+:108D90001501C0DF150000DF3A8839D874010201DF
+:108DA00004822921C0D902803A8801003A8837E03C
+:108DB0001701C0DF170000DF0402C0DE3A2800F808
+:108DC00004FDFFDE1502C0DF150100DF040100DF36
+:108DD0001775A0D01E0B0010040090010401400183
+:108DE0003A88090080ED38802604001074010201E1
+:108DF00004892921C0D9028040CD28804400800008
+:108E00001575A0D0171AA0D0D8FFBF101E080010EB
+:108E100080C3028015FFBFE017FFBFE00E02001005
+:108E20003A8805000603000017FFBFE0151AA0D01E
+:108E3000440080003A8837E01701C0DF170000DFE8
+:108E40000402C0DE3A2800F804FDFFDE1502C0DF90
+:108E5000150100DF040100DF171AA0D0E0FFBF10EA
+:108E60001E050010171AA0D015FFBFE0C4FFBF00F9
+:108E7000151AA0D00602000080C3028015FFBFE0D3
+:108E800017FFBFE03A8837E01701C0DF170000DFA7
+:108E90000402C0DE3A2800F804FFFFDE150000DF00
+:108EA0003A8839D8041980001577A0D0157620D0DB
+:108EB000157D20D0440080001572A0D03A880100B2
+:108EC0003A8837E0170000DF0401C0DE3A2800F8D6
+:108ED00004FFFFDE150000DF3A8839D83A88010028
+:108EE0003A8837E0170000DF0401C0DE3A2800F8B6
+:108EF00004FFFFDE150000DF3A8839D81772A0D0D2
+:108F0000260D00101776A0D0041980101576A0D079
+:108F10001776E0D01777A0D016078018177DA0D05D
+:108F200044008010157DA0D01776E0D01777A0D030
+:108F30003AC885181576A0D03A8801003A8837E0FB
+:108F4000170000DF0401C0DE3A2800F804FDFFDE50
+:108F5000150200DF040200DF3A30050015FEBFE015
+:108F600017FEFFE084FFBF003A7084183A700110CA
+:108F700017FEBFE015FFBFE01773A0D044008010BC
+:108F80001573A0D01773A0D0580080101E020010D7
+:108F900017FFBFE01574A0D03A8801003A8837E087
+:108FA000170000DF0401C0DE3A2800F804FEFFDEEF
+:108FB000150100DF040100DF1773A0D0C4FFBF104C
+:108FC0001573A0D01773A0D01E0400101774A0D082
+:108FD00015FFBFE017FFBFE03A7001103A880100AB
+:108FE0003A8837E0170000DF0401C0DE3A2800F8B5
+:108FF00004FBFFDE1504C0DF150300DF040300DF00
+:1090000015FD3FE1C5FE3FE015FF3FE017FDBFE066
+:109010001620001017FDBFE0080480101E1D001070
+:1090200017FDBFE0BA900610B40182003A88851897
+:10903000175BB810C4FEFFE03A880D183A880B00A1
+:109040003A88091000A61580C3FEBFE0CC3F80100F
+:10905000980280101E0A001017FFBFE04400801025
+:1090600015FFBFE017FFBFE050FA80101E0400108C
+:1090700074010201048D2921801727800606000053
+:10908000C3FEBFE0CC3F8010A00280101EE43F1062
+:109090000601000040CD28803A8837E01701C0DF84
+:1090A000170000DF0402C0DE3A2800F804FCFFDEEF
+:1090B0001503C0DF150200DF040200DF15FE3FE1EB
+:1090C000C5FF3FE017FEBFE01611001017FEBFE01E
+:1090D000080480101E0E001017FEBFE0BA900610A4
+:1090E000B40182003A888518175BB8103A880910D5
+:1090F00040D81580C5FFBFE0C3FFBFE026050010C4
+:1091000074010201049029218017278006010000C4
+:1091100040CD28803A8801003A8837E01701C0DF47
+:10912000170000DF0402C0DE3A2800F804EEFFDE7C
+:109130001511C0DF151000DF041000DF15F53FE149
+:1091400017F5BFE0170480103A880910C082298003
+:1091500015FFBFE017FFBFE01E03001074010201FE
+:10916000049329218017278017F5BFE0170200120A
+:1091700017F5BFE0170480103A88071004FFBF00FE
+:109180003A70841804FFBF1017FFFFE03A888B186D
+:1091900017F5BFE017038010CC3F801117F5BFE033
+:1091A00017038010CCFFBF1017F5FFE01704C0189D
+:1091B000BAD00618C4000001150400D9150300D860
+:1091C0001502C0D817FFFFE01501C0D8150080D8E0
+:1091D0003A880F303A880D283A880B003A880940BF
+:1091E000C0641680C5FEBFE0C3FEBFE0CC3F801068
+:1091F000180A80101E1C001017F5BFE0170380101E
+:10920000CC3F801084FE3FE184F6FFE03A880D20D9
+:109210003A880B183A880910C0C2168045FE3FE014
+:1092200017F5BFE01701C01017F5BFE017030011D5
+:1092300017F5BFE01703801084F67FE1150080D892
+:109240003A880F283A880D203A880B1874010201D9
+:109250000496292180C702807401020104AE2921ED
+:10926000C0D9028006200000C3FEBFE0CC3F8010C2
+:10927000980A80101E0E001017F5BFE01701C010ED
+:1092800017F5BFE0170380100405C0013A880D10E0
+:109290003A880B187401020104D6292180C7028084
+:1092A0007401020104F32921C0D90280060E0000D6
+:1092B000C3FEBFE0CC3F8010260B0010C3FEBFE012
+:1092C000CC3FC01017F5BFE0170180103A880D1091
+:1092D0003A880B187401020104122A2180C7028007
+:1092E000C4FFBF00061C000017F5BFE01703801085
+:1092F000CC3FC01017F5BFE017018010C4FE3FE15E
+:109300003A880D203A880B103A88091840D6168002
+:1093100017F5BFE017FFFFE01505C01017F5BFE018
+:109320001703C01017F5BFE0170080100500C0102C
+:1093300017F5BFE01701C01017F5BFE01703801045
+:109340003A880D103A880B187401020104202A2172
+:1093500080C702803A8805003A8837E01701C0DFED
+:10936000170000DF0402C0DE3A2800F804FBFFDE2D
+:109370001504C0DF150300DF040300DF15FD3FE126
+:10938000C5FE3FE015FF3FE017FDBFE0A8018010DC
+:109390001E1D001017FDBFE0BA900610B401820038
+:1093A0003A888518176BB810C4FEFFE03A880D188C
+:1093B0003A880B003A88091000A61580C3FEBFE06A
+:1093C000CC3F8010980280101E0A001017FFBFE0EB
+:1093D0004400801015FFBFE017FFBFE050FA801077
+:1093E0001E04001074010201048D292180172780BA
+:1093F00006060000C3FEBFE0CC3F8010A002801034
+:109400001EE43F100601000040CD28803A8837E076
+:109410001701C0DF170000DF0402C0DE3A2800F8A1
+:1094200004FCFFDE1503C0DF150200DF040200DFCD
+:1094300015FE3FE117FEBFE0A80180101E0E0010D0
+:1094400017FEBFE0BA900610B40182003A88851872
+:10945000176BB8103A88091040D81580C5FFBFE0D7
+:10946000C3FFBFE02605001074010201049029210A
+:10947000801727800601000040CD28803A8801002F
+:109480003A8837E01701C0DF170000DF0402C0DEB2
+:109490003A2800F804FDFFDE1502C0DF150100DFE9
+:1094A000040100DF4400000140771580157FA0D043
+:1094B000177FA0D01E0300107401020104282A2186
+:1094C000801727803A880900407715801580A0D042
+:1094D0001780A0D01E03001074010201042F2A215E
+:1094E0008017278015FF3FE00614000044000001AC
+:1094F000407715803A88091017FFBFE0BA90061030
+:10950000B40182003A888518155B381117FFBFE057
+:10951000BA900610B40182003A888518175BB8101B
+:109520001E0300107401020104362A2180172780CF
+:1095300017FFBFE04400801015FFBFE017FFBFE03A
+:10954000100480101EE93F1015FF3FE006140000D4
+:1095500044000001407715803A88091017FFBFE0EA
+:10956000BA900610B40182003A888518156B38113C
+:1095700017FFBFE0BA900610B40182003A88851840
+:10958000176BB8101E03001074010201043D2A215C
+:109590008017278017FFBFE04400801015FFBFE051
+:1095A00017FFBFE0900180101EE93F1015FF3FE05C
+:1095B000061E000017FFBFE02403C010B4018200A4
+:1095C0003A888518151F381017FFBFE02403C01014
+:1095D000B40182003A888518152038103A880900AD
+:1095E000407715803A88091017FFBFE02403C010A8
+:1095F000B40182003A8885181521381117FFBFE0A1
+:109600002403C010B40182003A8885181721B810CD
+:109610001E0300107401020104442A2180172780D0
+:1096200017FFBFE04400801015FFBFE017FFBFE049
+:10963000100580101EDF3F10157C20D03A880100F5
+:109640003A8837E01701C0DF170000DF0402C0DEF0
+:109650003A2800F804FFFFDE150000DF3A8839D809
+:10966000840780001518A0D0840780001516A0D0AC
+:10967000048081001519A0D0042080001517A0D007
+:10968000F40082000482A5101596A0D03A88050047
+:109690003A8837E0170000DF0401C0DE3A2800F8FE
+:1096A00004FFFFDE150000DF3A8839D83A8805004C
+:1096B0003A8837E0170000DF0401C0DE3A2800F8DE
+:1096C00004FDFFDE1502C0DF150100DF040100DF2D
+:1096D00015FF3FE117FF3FE180AA228015FFBFE0A1
+:1096E00017FFBFE03A8837E01701C0DF170000DF3F
+:1096F0000402C0DE3A2800F804F8FFDE1507C0DFD8
+:10970000150600DF040600DF15FB3FE115FA7FE1D7
+:1097100017FABFE0260300103401820004268B10E4
+:1097200006020000340182000429A01015FEBFE0EB
+:10973000177FA0D0C4FCFFE03A880D183A880B00D0
+:109740003A88091000A61580C3FCBFE0CC3F80100A
+:109750002616001015FF3FE00610000017FFBFE0BF
+:109760004400C01015FFFFE050FA80101E050010E5
+:1097700074010201044C2A21801727803A880500D1
+:10978000061B0000177FA0D0C4FCFFE03A880D182C
+:109790003A880B003A88091000A61580C3FCBFE088
+:1097A000CC3F8010A00280101EEC3F1017FEBFE0DF
+:1097B00017FB3FE13AE83E1015FDBFE0177FA0D050
+:1097C0003A88091040D81580C5FCBFE017FDBFE0FE
+:1097D0001E0200103A8805000605000017FBBFE1D5
+:1097E0003A880B0017FD3FE1408E088017FDBFE06F
+:1097F0003A8837E01701C0DF170000DF0402C0DE3F
+:109800003A2800F804F9FFDE1506C0DF150500DF71
+:10981000040500DF15FC3FE115FB7FE117FBBFE00E
+:109820002603001034018200042A8B100602000077
+:10983000340182000418A01015FEBFE0177FA0D0ED
+:10984000C4FDFFE03A880D183A880B003A880910E9
+:1098500000A61580C3FDBFE0CC3F80102615001088
+:1098600015FF3FE0060F000017FFBFE04400C010E7
+:1098700015FFFFE050FA80101E0400107401020171
+:10988000044E2A218017278006110000177FA0D0E0
+:10989000C4FDFFE03A880D183A880B003A88091099
+:1098A00000A61580C3FDBFE0CC3F8010A002801051
+:1098B0001EED3F1017FEBFE017FC3FE13AE83E10F7
+:1098C000177FA0D03A88091040D81580C5FDBFE0A9
+:1098D0003A8837E01701C0DF170000DF0402C0DE5E
+:1098E0003A2800F804FDFFDE1502C0DF150100DF95
+:1098F000040100DF15FF3FE14400400117FF3FE195
+:10990000006429803A8837E01701C0DF170000DFC4
+:109910000402C0DE3A2800F804FDFFDE1502C0DFB5
+:10992000150100DF040100DF15FF3FE117FFBFE075
+:10993000260300104400400117FF3FE1C074298056
+:109940003A8801003A8837E01701C0DF170000DFCE
+:109950000402C0DE3A2800F804FDFFDE1502C0DF75
+:10996000150100DF040100DF15FF3FE13A880B001D
+:1099700017FF3FE1006429803A8837E01701C0DF14
+:10998000170000DF0402C0DE3A2800F804FDFFDE05
+:109990001502C0DF150100DF040100DF15FF3FE104
+:1099A00017FFBFE0260300103A880B0017FF3FE1C6
+:1099B000C07429803A8801003A8837E01701C0DF77
+:1099C000170000DF0402C0DE3A2800F804FCFFDEC6
+:1099D0001503C0DF150200DF040200DF15FF3FE1C1
+:1099E00015FE7FE117FFBFE0A00080101E030010EE
+:1099F00040CD28803A8805000613000017FEBFE01E
+:109A0000580080101E0300107401820004F8B11089
+:109A1000060D000017FEBFE0980080101E03001026
+:109A20007401820004FEB1100607000017FEBFE0BB
+:109A3000D80080101E030010740182000404B210CC
+:109A4000060100003A8805003A8837E01701C0DFB8
+:109A5000170000DF0402C0DE3A2800F804FBFFDE36
+:109A60001504C0DF150300DF040300DF15FF3FE12D
+:109A700015FE7FE115FDBFE117FDBFE0D8008010A6
+:109A80001E04001017FD7FE117FF3FE14091298080
+:109A90000620000017FEBFE0A00180101E06001087
+:109AA00017FEBFE0600480101E09001017FEBFE023
+:109AB00026100010060C000017FDBFE058008010B3
+:109AC000260E001040CD28803A88050006110000BF
+:109AD00017FDBFE098008010260A001040CD2880B6
+:109AE0003A880500060B000040CD28803A88050022
+:109AF000060800003A880100060300003A880100C9
+:109B0000060100003A88010017FD7FE117FF3FE1E1
+:109B1000409129803A8837E01701C0DF170000DF45
+:109B20000402C0DE3A2800F804FAFFDE1505C0DFA3
+:109B3000150400DF040400DF15FD3FE115FC7FE1A3
+:109B400015FF3FE017FDBFE00E03800017FDBFE0EB
+:109B5000900380101E01001040CD288017FCBFE04C
+:109B6000260D00108400000180F3288017FCBFE060
+:109B7000040E80103A8809104043288015FFBFE08A
+:109B80008400000140FF288017FFBFE01E02001084
+:109B90003A88050006410000B4010201048A382118
+:109BA000808D288015FEBFE017FEBFE01E0A001062
+:109BB00017FFBFE0260600108400000180F3288014
+:109BC00017FF3FE1807428808400000140FF288057
+:109BD0003A8805000631000017FEBFE017FDFFE0E0
+:109BE0001508C01017FCBFE01E07001017FEBFE0ED
+:109BF0001501001017FEBFE01504001017FEBFE0AE
+:109C0000150500100615000017FEBFE017FFFFE066
+:109C10001501C01017FFBFE017018010040EC0101F
+:109C200017FFBFE01503C01017FFBFE01703C010F8
+:109C300017FEBFE01503C01017FEBFE01703C010EA
+:109C400017FEBFE01504C01017FFBFE01702801019
+:109C500004F2FF1017FEBFE01505C01017FEBFE0AD
+:109C60001502001017FEBFE01507001017FEBFE039
+:109C70001707C01017FEBFE01506C0101783A0D04D
+:109C8000440080101583A0D017FE7FE1B4010201CB
+:109C9000048538210099288017FEBFE03A8837E014
+:109CA0001701C0DF170000DF0402C0DE3A2800F809
+:109CB00004FCFFDE1503C0DF150200DF040200DF35
+:109CC00015FE3FE1B40182001787B810160380002B
+:109CD0007401020104502A218017278017FEBFE07B
+:109CE000170880100E04800017FEBFE017088010D0
+:109CF000900380101E0A001017FEBFE017088010A6
+:109D00001E04001040CD288017FEBFE0170680100B
+:109D1000062300007401020104542A2180172780C1
+:109D200017FEBFE01706801015FFBFE017FE7FE1AA
+:109D3000B40102010485382100A428801E0300100C
+:109D40007401020104582A218017278017FEBFE002
+:109D50001508001017FEBFE017018010260800103C
+:109D60008400000180F3288017FEBFE017018010F7
+:109D70003A880910807428808400000140FF288000
+:109D80001784A0D0440080101584A0D017FE7FE176
+:109D9000B4010201048A38210099288017FFBFE02E
+:109DA0003A8837E01701C0DF170000DF0402C0DE89
+:109DB0003A2800F804FDFFDE1502C0DF150100DFC0
+:109DC000040100DF15FF3FE10603000017FF3FE13C
+:109DD00080BF298015FFBFE017FFBFE01EFB3F10CB
+:109DE0003A8801003A8837E01701C0DF170000DF2A
+:109DF0000402C0DE3A2800F804F7FFDE1508C0DFD1
+:109E0000150700DF040700DF15FB3FE115FA7FE1CE
+:109E100015F9BFE117F9BFE01E0200103A880500EE
+:109E200006A6000017FABFE01605001017F9BFE0FC
+:109E30000E18001017F9BFE0E0FFBF101E1500104C
+:109E400040CD28803A880500069C000017FBBFE043
+:109E50001E03001040CD28803A88050006970000B8
+:109E600017FBBFE0170280103A88071017FABFE00F
+:109E7000160BC01017FAFFE017FBBFE017028010A7
+:109E80003AC8851815FABFE017FBBFE01706801027
+:109E900015FBBFE017FABFE016ECBF00060100009B
+:109EA0003A88010015FD3FE017FDBFE015FEBFE059
+:109EB0000678000017FBBFE01E05001074010201C8
+:109EC000045C2A21801727803A880500067B000061
+:109ED00017FBBFE01702C01017FABFE03AC8851899
+:109EE0003A88071017F9BFE00E0180183A88051864
+:109EF00015FCBFE017FABFE0CC0080101E05001073
+:109F000017FBBFE017018010170980106000801058
+:109F10001E21001017FBBFE01708801017FC7FE11F
+:109F20003A88091000A7298015FFBFE017FFBFE09E
+:109F3000265C001017FFBFE01703001117FBBFE0FE
+:109F40001703C01017FABFE03A88851817FCFFE026
+:109F50003A880D183A880B10806B088017FCFFE0D8
+:109F600017FFBFE01502C010B401820017D2B8106D
+:109F70004400C010B401820015D2F810B401820070
+:109F800017D4F81017FCBFE03A888718B401820094
+:109F900015D4F810062D000017FBBFE0170880103D
+:109FA0003A880B003A88091000A7298015FFBFE006
+:109FB00017FFBFE0263D001017FBBFE01701801020
+:109FC0001709C0104400C0181509C01017FBBFE0E6
+:109FD0001701C01017FFBFE01501C01017FBBFE04D
+:109FE0001704C01017FFBFE01504C01017FBBFE037
+:109FF0001705C01017FFBFE01505C01017FBBFE025
+:10A000001703C01017FABFE03A88871817FFBFE0A0
+:10A010001503C01017FCFFE017FFBFE01502C010CA
+:10A02000B401820017D3B8104400C010B4018200FC
+:10A0300015D3F810B401820017D5F81017FCBFE053
+:10A040003A888718B401820015D5F81017F9FFE097
+:10A0500017FCBFE03AC8851815F9BFE015FA3FE0D4
+:10A0600017FDBFE02604001017FDBFE017FFFFE05B
+:10A070001506C0100602000017FFBFE015FEBFE086
+:10A0800017FFBFE015FDBFE017FBBFE0170680100C
+:10A0900015FBBFE017F9BFE01686BF0017FEBFE053
+:10A0A000060600003A880100060100003A88010017
+:10A0B00017FE3FE1C0CF29803A8805003A8837E093
+:10A0C0001701C0DF170000DF0402C0DE3A2800F8E5
+:10A0D00004FBFFDE150400DF040400DF15FD3FE193
+:10A0E00015FC7FE117FDBFE015FFBFE017FFBFE0E4
+:10A0F0002662001017FCBFE016220010061C0000AC
+:10A1000017FFBFE01702801017FCFFE0360B801826
+:10A1100017FCFFE017FFBFE0170280103AC8851850
+:10A1200015FCBFE017FFBFE01502001017FFBFE0EE
+:10A130001706801015FFBFE0060D000017FFBFE0F7
+:10A140001702C01017FCBFE03AC8871817FFBFE01E
+:10A150001502C01017FFBFE01703C01017FCBFE0C7
+:10A160003A88871817FFBFE01503C01006440000A7
+:10A1700017FFBFE02642001017FCBFE016E0BF004B
+:10A18000063F000017FCBFE03AC8850015FCBFE0A1
+:10A1900015FE3FE017FFBFE01702C01017FEBFE03B
+:10A1A0003A88851815FEBFE017FFBFE0170680103C
+:10A1B0002604001017FFBFE01706801015FFBFE050
+:10A1C00006F43F003A88010017FFBFE01702C010F5
+:10A1D00017FCBFE03607801817FFBFE01702C0105A
+:10A1E00017FCBFE03AC8871817FFBFE01502C01080
+:10A1F0000623000017FEFFE017FCBFE03AC88518F1
+:10A2000015FEBFE017FDBFE015FFBFE00610000020
+:10A2100017FFBFE01702C01017FEBFE0360480181A
+:10A2200017FEFFE017FFBFE01502C010060A00008E
+:10A2300017FEFFE017FFBFE0170280103AC885182D
+:10A2400015FEBFE017FFBFE01706801015FFBFE047
+:10A2500017FFBFE01EEE3F100602000017FFBFE031
+:10A260001502001017FFBFE01706801015FFBFE0B2
+:10A2700017FFBFE01EF93F10060100003A880100F9
+:10A280003A8837E0170000DF0401C0DE3A2800F802
+:10A2900004FDFFDE150200DF040200DF15FE3FE1D2
+:10A2A00015FF3FE00608000017FEBFE01702C010D0
+:10A2B00017FFBFE03A88851815FFBFE017FEBFE023
+:10A2C0001706801015FEBFE017FEBFE01EF63F1018
+:10A2D00017FFBFE03A8837E0170000DF0401C0DE57
+:10A2E0003A2800F804FBFFDE1504C0DF150300DF89
+:10A2F000040300DF15FD3FE1B40182001785B810AB
+:10A3000015FFBFE00612000017FFBFE015FEBFE01B
+:10A3100017FEBFE01704801017FDFFE03609801814
+:10A3200017FEBFE01704C01017FEBFE0170580102E
+:10A330003A88851817FDFFE02E02801817FFBFE04E
+:10A340000609000017FFBFE01700801015FFBFE0EF
+:10A3500017FFBFE01EEC3F107401020104602A21C8
+:10A36000801727803A8805003A8837E01701C0DF58
+:10A37000170000DF0402C0DE3A2800F804FDFFDE0B
+:10A38000150200DF040200DF15FE3FE117FEBFE00B
+:10A3900015FFBFE017FFBFE017018010260E001069
+:10A3A00017FFBFE01701801017FFFFE01700C0186C
+:10A3B0001500C01017FFBFE017008010260700101F
+:10A3C00017FFBFE01700801017FFFFE01701C0184C
+:10A3D0001501C010060100003A8801003A8837E0F4
+:10A3E000170000DF0401C0DE3A2800F804FBFFDE9E
+:10A3F000150400DF040400DF15FD3FE115FC7FE1DB
+:10A4000017FDBFE015FFBFE017FCBFE015FEBFE082
+:10A4100017FEBFE01700C01017FFBFE01500C01007
+:10A4200017FFBFE017FEFFE01501C01017FEBFE0E9
+:10A4300017FFFFE01500C01017FFBFE017008010E6
+:10A440002604001017FFBFE01700801017FFFFE081
+:10A450001501C0103A8801003A8837E0170000DF84
+:10A460000401C0DE3A2800F804FBFFDE1504C0DF5B
+:10A47000150300DF040300DF1716E0D01718A0D083
+:10A480003A8885183A888510C400801015FEBFE010
+:10A49000040580013A880B00B401020104713821DF
+:10A4A000408E0880040580013A880B00B401020147
+:10A4B00004853821408E0880040580013A880B000D
+:10A4C000B4010201048A3821408E088015FF3FE064
+:10A4D0000615000004090001C082298015FDBFE0B7
+:10A4E00017FDBFE01E0300107401020104622A215F
+:10A4F0008017278017FDBFE01508001017FDBFE08B
+:10A500001502001017FDBFE01503001017FD7FE1D5
+:10A51000B4010201048A38210099288017FFBFE0A6
+:10A520004400801015FFBFE017FEBFE017FFFFE0FB
+:10A5300016E8BF1817FEFFE0B4018200158EF81070
+:10A54000809F34803A8805003A8837E01701C0DFE1
+:10A55000170000DF0402C0DE3A2800F804F9FFDE2D
+:10A560001506C0DF150500DF040500DF15FB3FE120
+:10A5700017FBBFE01703801015FFBFE017FFBFE018
+:10A580008B008010CCFFBF103AD204103A8807101D
+:10A5900017FFBFE08B008010CCFFBF103A92041071
+:10A5A0003AB084188DFEBFE017FFBFE003008010B3
+:10A5B000CC3F8010BA9004100C0F801017FFFFE002
+:10A5C0003A88851815FDBFE017FF3FE1000C408079
+:10A5D0003A88071017FDBFE00B048010CCFFFF186E
+:10A5E000CCFFBF1026128018B40182001783B81068
+:10A5F0004400C010B40182001583F810B401820039
+:10A6000017C0B8104400C010B401820015C0F81083
+:10A610008400000180F3288017FB3FE180742880CC
+:10A620008400000140FF288004F8BF0006330000CA
+:10A630003A880B004400000100A7298015FCBFE008
+:10A6400017FCBFE01E0800108400000180F3288082
+:10A6500017FB3FE1807428808400000140FF2880C0
+:10A6600084FABF000625000017FFBFE0030080103A
+:10A67000CC3F8010BA9004100C0F80103A8807105D
+:10A680008BFEBFE03AC8C5108DFEBFE017FFBFE0EC
+:10A690008BFEFFE08D00C01017FCBFE017FBFFE052
+:10A6A0001501C01017FBBFE01703C01017FCBFE077
+:10A6B0001503C01017FBBFE01704C01017FCBFE064
+:10A6C0001502C01017FBBFE01701C01017FCBFE058
+:10A6D0001504C01017FBBFE01702C01017FCBFE045
+:10A6E0001505C01017FBBFE0170680103A880B1045
+:10A6F00017FC3FE1000531803A8805003A8837E0D1
+:10A700001701C0DF170000DF0402C0DE3A2800F89E
+:10A7100004F4FFDE150BC0DF150A00DF040A00DFBA
+:10A7200015F73FE115F67FE117F7BFE01706801038
+:10A730002602011017F7BFE015FFBFE017F7BFE0D3
+:10A740001706801015FEBFE00633000017FFBFE0BC
+:10A750001701801015FBBFE017FBBFE01701C01009
+:10A7600017FBBFE0170280103A88851817FFFFE03B
+:10A770001703001917FFFFE01702401917FEFFE04B
+:10A780001702C0183A88C7283A88C7202E2980188F
+:10A7900017FFBFE01703C01017FFBFE017028010BC
+:10A7A0003A88871817FEBFE01703001117FEBFE0B5
+:10A7B000170280103A880D103A880B203A88091841
+:10A7C000806B088017FFBFE01702C01017FEBFE0C4
+:10A7D000170280103A88871817FFBFE01502C010D3
+:10A7E00017FEBFE01706C01017FFBFE01506C01028
+:10A7F00017FE3FE180BF298017FFBFE017068010DA
+:10A8000015FEBFE0B401820017D7B8104400C01095
+:10A81000B401820015D7F81017FEBFE026570010CC
+:10A8200017FEBFE017028010B00280101EC73F1055
+:10A83000065200003A8801000650000017FEBFE0F3
+:10A840001703C01017FEBFE017018010170180101A
+:10A850003AC8851815FABFE01764A0D017FAFFE0D0
+:10A860000E0980181764A0D017FABFE13A880B10C0
+:10A870007401020104642A2180C70280740102016C
+:10A88000046A2A218017278017FFBFE01702801073
+:10A890001764E0D017FA3FE13AC8C7202E39C0103C
+:10A8A00017FFBFE017028010CC0080101E3500108B
+:10A8B00017FEBFE01703C01017FEBFE0170180109E
+:10A8C000170180103AC88518180E80101E2D001030
+:10A8D00017FEBFE01703C01017FFBFE0170280107C
+:10A8E0003AC885003A88871817FFBFE017030011A0
+:10A8F00017FFBFE0170280103A880D103A880B202E
+:10A900003A880918806B088017FEBFE01703C01053
+:10A9100017FFBFE0170280103AC885003A888718F1
+:10A9200017FEBFE01503C01017FEBFE01702C010EE
+:10A9300017FFBFE0170280103A88871817FEBFE0A4
+:10A940001502C01017FF3FE180BF298017FEBFE04E
+:10A9500015FFBFE017FFBFE015F7BFE017FEBFE030
+:10A960001706801015FEBFE0B401820017D6B8109C
+:10A970004400C010B401820015D6F81017FEBFE0E5
+:10A980001EAE3F1017FEBFE0266C001015FC3FE026
+:10A9900017FFBFE015FDBFE00608000017FDBFE090
+:10A9A0001702C01017FCBFE03A88851815FCBFE0FD
+:10A9B00017FDBFE01706801015FDBFE017FDBFE0D3
+:10A9C0001EF63F108400000180F3288017FCBFE0D2
+:10A9D000040E80103A8809104043288015FBBFE020
+:10A9E0008400000140FF288017FBBFE01E0200101A
+:10A9F000441A800006A3000017FBBFE01701801077
+:10AA00001764E0D03A88C71017FBBFE01503C010E9
+:10AA100017FFBFE015FDBFE00627000017FBBFE0F2
+:10AA20001703C01017FDBFE01703001117FDBFE0AB
+:10AA3000170280103A880D103A880B203A880918BE
+:10AA4000806B088017FBBFE01703C01017FDBFE045
+:10AA5000170280103A88871817FBBFE01503C01053
+:10AA600017FBBFE01704C01017FDBFE017028010EE
+:10AA70003A88871817FBBFE01504C01017FDBFE028
+:10AA800015FEBFE017FDBFE01706801015FDBFE003
+:10AA900017FEFFE017F7BFE02602801817FE3FE120
+:10AAA00080BF2980B401820017D8B8104400C010BC
+:10AAB000B401820015D8F81017FDBFE01ED73F1073
+:10AAC00017FBBFE01703C01017FCBFE03AC88500B2
+:10AAD0003A88871817FBBFE01503C01084000001F7
+:10AAE00080F3288017F7BFE0170180103A8809101B
+:10AAF000807428808400000140FF288017F7BFE0A1
+:10AB000017FBFFE01501C01017FBBFE01704C010D2
+:10AB100017F7BFE01502C01017F7BFE015060010C9
+:10AB200017FBBFE01703C01017F7BFE01503C010F5
+:10AB300017FCFFE017F7BFE01502C01017F7BFE0E2
+:10AB40001703C01017F7BFE017018010170180101E
+:10AB5000176420D13A8805112E0380187401020170
+:10AB6000046F2A218017278017F7BFE01701801094
+:10AB700015FBBFE017F6BFE02603001017FBBFE090
+:10AB800017F6FFE0150CC01017F7BFE01703801091
+:10AB900015F9BFE017F9BFE01704C01017FBBFE0BD
+:10ABA0001507C01017F9BFE04411C0000500C01020
+:10ABB00017F9BFE08B008010CCFFBF103AD2041011
+:10ABC0003A88071017F9BFE08B008010CCFFBF1048
+:10ABD0003A9204103AB084183A88071017F9BFE087
+:10ABE0008D00C01017F9BFE003008010CC3F80102B
+:10ABF000BA9004100C0F801017F9FFE03A888518FE
+:10AC000015F8BFE017F93FE1000C40803A880710C3
+:10AC100017F8BFE00D04C01017F9BFE00405C0101D
+:10AC200017FBBFE01503C01017F7BFE01702801035
+:10AC300004FBFF1017FBBFE01504C01017FB7FE1FA
+:10AC400084010001809E3A8015FABFE017F7BFE04B
+:10AC50001501001017F73FE1C0CF298017FABFE0B8
+:10AC60000E07001017FABFE098FABF101E0200107E
+:10AC70003A8805000603000017FABFE0060100004D
+:10AC80003A8805003A8837E01701C0DF170000DF77
+:10AC90000402C0DE3A2800F804FEFFDE150100DFE2
+:10ACA000040100DF15FF3FE117FFBFE0D8FFBF1031
+:10ACB0001E02001044008000060100003A880500D2
+:10ACC0003A8837E0170000DF0401C0DE3A2800F8B8
+:10ACD00004FBFFDE1504C0DF150300DF040300DF03
+:10ACE00015FE3FE115FD7FE117FEBFE00300801078
+:10ACF000CC3F8010BA9004100C0F801015FFBFE0FD
+:10AD000017FFBFE0480580102627001017FFBFE09F
+:10AD100004FBBF1015FFBFE017FEBFE08B008010E3
+:10AD200017FFFFE03AC8C5103A88071017FEBFE0CA
+:10AD30008D00C01017FEBFE0030080103A88071096
+:10AD400004FCBF003A708418540180103A88071040
+:10AD500017FEBFE00500C01017FFBFE017FEFFE0C1
+:10AD60003A8885180405800117FE7FE13A880910AA
+:10AD7000807B088017FDBFE01702C01017FFBFE0FF
+:10AD80003AC8871817FDBFE01502C01017FDBFE0D5
+:10AD90001703C01017FFBFE03A88871817FDBFE000
+:10ADA0001503C010060100003A8801003A8837E018
+:10ADB0001701C0DF170000DF0402C0DE3A2800F8E8
+:10ADC00004F3FFDE150CC0DF150B00DF040B00DF02
+:10ADD00015F83FE115F77FE117F7BFE01706801080
+:10ADE0003AD6061017F7BFE0170680103AD20410C3
+:10ADF0000CC0BF103AB0861817F7BFE017068010D6
+:10AE00003A920410EC3F80103AB0861817F7BFE072
+:10AE1000170680103A9604103AB0841815FEBFE069
+:10AE200017F7BFE0170580103AD6061017F7BFE0F6
+:10AE3000170580103AD204100CC0BF103AB0861823
+:10AE400017F7BFE0170580103A920410EC3F80100E
+:10AE50003AB0861817F7BFE0170580103A9604102D
+:10AE60003AB0841815FDBFE017F7BFE00407801063
+:10AE70000B008010CCFFBF103AD204103A880710A4
+:10AE800017F7BFE0040780100B008010CCFFBF1045
+:10AE90003A9204103AB084188DFCBFE017F7BFE077
+:10AEA000840780100B008010CCFFBF103AD2041032
+:10AEB0003A88071017F7BFE0840780100B00801056
+:10AEC000CCFFBF103A9204103AB084180DFCBFE0DA
+:10AED00017F7BFE043008010CC3F80101C2080108B
+:10AEE00004E0BF1018018010266E001017F7BFE0B5
+:10AEF00043048010CC3F8010980180101E22001067
+:10AF00000BFC3FE18BFCBFE04400C0001501C0D842
+:10AF1000150080D817FDFFE13A880D2017FE7FE16C
+:10AF2000B40102010499382100B6408015FBBFE04E
+:10AF300017FBBFE0265D001017FBBFE0170880106D
+:10AF400015FABFE017FABFE0265A001017FBBFE062
+:10AF50001709801015F9BFE017F9BFE026060010A9
+:10AF600017F9BFE0170280108800801026530010E8
+:10AF700017F93FE1800E358017FABFE0C41BC0000F
+:10AF80001506C0100654000017F7BFE043048010F8
+:10AF9000CC3F8010580480101E4A0010179EA0D08D
+:10AFA00015FFBFE00621000017FFBFE00B02801075
+:10AFB0000BFCFFE0CCFFBF102604801817FFBFE09A
+:10AFC0000B028010CCFFBF101E15001017FFBFE052
+:10AFD0001704C01017FEBFE03AD6081017FEBFE0F6
+:10AFE0003AD204100CC0BF103AB0882017FEBFE060
+:10AFF0003A920410EC3F80103AB0882017FEBFE070
+:10B000003A9604103AB084201E05801817FFBFE05E
+:10B010008B0180108BFCFFE0CCFFBF102606801850
+:10B0200017FFBFE01700801015FFBFE017FFBFE05C
+:10B030001EDD3F10060100003A88010017FFBFE047
+:10B040002622001017FFBFE01706801015FABFE098
+:10B0500017FABFE083098010CC3F80101C208010BD
+:10B0600004E0BF10A0008010261A001017FABFE0FD
+:10B07000C41BC0001506C01017FABFE0040A8010F8
+:10B080003A880B1017FA3FE1C0942F8017FABFE0FF
+:10B09000041280103A880B1017FA3FE1C0942F80F9
+:10B0A000060D00003A880100060B00003A880100F6
+:10B0B000060900003A880100060700003A880100EE
+:10B0C000060500003A880100060300003A880100E6
+:10B0D000060100003A8801008400000180F3288006
+:10B0E00017F83FE1807428808400000140FF288029
+:10B0F0003A8801003A8837E01701C0DF170000DF07
+:10B100000402C0DE3A2800F804FEFFDE1501C0DFAD
+:10B11000150000DF3A8839D81782A0D01E1200101F
+:10B120001782A0D0440080101582A0D03A88090070
+:10B1300080F32880177DE0D01781A0D036048018D6
+:10B1400080303580177DA0D0840C80101581A0D070
+:10B150003A88090040FF28801782A0D0C4FFBF10A2
+:10B160001582A0D0060100003A8801003A8837E035
+:10B170001701C0DF170000DF0402C0DE3A2800F824
+:10B1800004FDFFDE150200DF040200DF15FE3FE1D3
+:10B19000179BA0D015FFBFE00609000017FFBFE016
+:10B1A0001704801017FEFFE01E02801817FFBFE093
+:10B1B0000606000017FFBFE01700801015FFBFE074
+:10B1C00017FFBFE01EF53F103A8805003A8837E0C8
+:10B1D000170000DF0401C0DE3A2800F804F5FFDEA6
+:10B1E000150AC0DF150900DF040900DF15F83FE18B
+:10B1F00015F77FE117F7BFE015FFBFE03A880900B8
+:10B2000080F3288017FFBFE0170AC01017F8BFE0CF
+:10B21000170480103A88871817FFBFE0170B8010BB
+:10B22000360480183A88090040FF2880441A8000BC
+:10B23000065600003A880B004400000100A7298050
+:10B2400015FEBFE017FEBFE01E0400103A8809009B
+:10B2500040FF2880441A8000064C000017FEBFE023
+:10B2600017F8FFE01501C01017F8BFE01701C01074
+:10B2700017FEBFE01504C01017F8BFE01702C0109A
+:10B2800017FEBFE01505C01017F8BFE01703C01088
+:10B2900017FEBFE01503C01017F8BFE01704C01079
+:10B2A00017FEBFE01502C01017FFBFE017048010A3
+:10B2B0000C0088101E13001017F8BFE01703801051
+:10B2C00003008010CC3F8010BA9004100C0F801047
+:10B2D00015FDBFE017FEBFE01703C01017FDBFE06C
+:10B2E0003A88871817FEBFE01503C01017FEBFE0AD
+:10B2F0001702C01017FDBFE03AC8871817FEBFE05D
+:10B300001502C01017F8BFE01707801015FABFE04C
+:10B310008DF93FE0840080000DF9BFE017FFBFE02A
+:10B32000040A801004F9FFE017FEBFE13A880B1809
+:10B330003A88091040C72F801E08001017FEBFE092
+:10B340001501001017FE3FE180BF29803A880900EF
+:10B3500040FF2880441A8000060C000017FFBFE061
+:10B36000040A80103A88091000BA278017FFBFE04E
+:10B37000040A80103A880B1017FF3FE1C0942F8019
+:10B380003A88090040FF28803A8805003A8837E06B
+:10B390001701C0DF170000DF0402C0DE3A2800F802
+:10B3A00004EFFFDE1510C0DF150F00DF150E00DC07
+:10B3B000040F00DF15F43FE115F37FE115F2BFE163
+:10B3C00017F4BFE01707801015FABFE017FABFE0C7
+:10B3D000680480101EB9011017FABFE0BA90061079
+:10B3E000F40082003A88851817CEAC103A68001035
+:10B3F0007CB3020804B4020840B4020804BA02088C
+:10B4000040B4020804BA0208F8B9020804BA0208F3
+:10B41000F8B90208C8B5020804BA020804BA02085A
+:10B4200004BA020804BA020804BA020864B902089D
+:10B4300064B9020817F4BFE0170480100C008810EC
+:10B440003A88091000AE3C803A88071017F4BFE034
+:10B450001513C01017F4BFE01713C01017F4BFE0A6
+:10B46000150BC01017F2BFE0C5F9BFE03A8809001C
+:10B4700040FF2880C3F9FFE017F4BFE0150080D833
+:10B48000F400C2010449EC393A880D003A880B00F7
+:10B490003A880918C0633C8015F8BFE03A88090073
+:10B4A00080F3288017F8BFE01E020010840580009A
+:10B4B000068301003A8805000681010017F43FE188
+:10B4C000800C2B8015F8BFE017F8BFE01E020010BB
+:10B4D00084058000067A01003A88090040FF288030
+:10B4E00017F83FE140713C803A88090080F32880DA
+:10B4F0003A8805000672010017F2BFE01E02001034
+:10B5000084058000066E010017F2BFE0170380106B
+:10B5100015F7BFE017F7BFE01E020010840580009A
+:10B520000667010017F2BFE01702801020048010A8
+:10B530001E020010840580000661010017F43FE13F
+:10B54000800C2B8015F8BFE017F8BFE01E0200103A
+:10B5500084058000065A010017FABFE098008010A9
+:10B560001E1F001017F7BFE0170180101E02001009
+:10B5700015FC3FE00616000017F7BFE0170180102A
+:10B5800015FCBFE0B401820017A6B61015FBBFE0A2
+:10B590000607000017FBBFE0170A801017FCFFE04A
+:10B5A0002606801817FBBFE01700801015FBBFE0D0
+:10B5B00017FBBFE01EF73F10060100003A880100AC
+:10B5C00017FBBFE01E020010441F8000063C010074
+:10B5D00017F8BFE017FCFFE01501C01006260000B9
+:10B5E00017F7BFE0170180101E02001015FD3FE0A5
+:10B5F0000603000017F7BFE01701801015FDBFE03C
+:10B6000017F8BFE017FDFFE01502C01017FDBFE0FF
+:10B61000260E001017F4BFE08B08C010C4FCBF005A
+:10B620003A7084183A88071017F4BFE08D08C010EC
+:10B6300017F4BFE08B088010940080103A88071040
+:10B6400017F4BFE08D08C0100607000017F4BFE034
+:10B650008B08C01044FFBF003A7084183A88071066
+:10B6600017F4BFE08D08C01017F4BFE0040A801083
+:10B670003A880910C00230803A880500061001009F
+:10B6800017F3BFE01E02001084058000060C0100C5
+:10B6900017F43FE1800C2B8015F8BFE017F8BFE0EE
+:10B6A0001E04001017F33FE180BF2980C41B8000F7
+:10B6B0000603010017F2BFE01E0B001017F4BFE0F5
+:10B6C0008B088010CCFFBF108C0080101E02001071
+:10B6D0000420800006FA000017F8BFE0170280106F
+:10B6E00015FDBFE00614000017F4BFE08B088010C2
+:10B6F000CCFFBF108C00801026020010C41F8000F9
+:10B7000006EF000017F2BFE017028010200480103F
+:10B710001E03001040CD28808405800006E800004C
+:10B7200017F2BFE01703801015F7BFE017F7BFE06F
+:10B730001701801015FDBFE017F3BFE017020014DA
+:10B7400017F4BFE0170480100C0088103A88091025
+:10B7500000AE3C802E03001440CD2880841E800063
+:10B7600006D7000017F3BFE0170280103A880710D1
+:10B7700017F4BFE0170480100C0088103A880B10F3
+:10B780003A880918409E3C8015F6BFE017F6BFE0E6
+:10B790001E04001017F33FE180BF2980441A800087
+:10B7A00006C7000017F6BFE01703C01017F3BFE08D
+:10B7B0001703001117F3BFE0170280103A880D102D
+:10B7C0003A880B203A880918806B088017F3BFE08D
+:10B7D0001702C01017F6BFE01504C01017F33FE1C1
+:10B7E00080BF298017F6BFE017FDFFE01507C010E6
+:10B7F00017FDBFE0D8FFBF101E47001017F8BFE0CD
+:10B8000017018010260F0010B401820017A6B61091
+:10B8100015FBBFE00608000017FBBFE0170AC010C9
+:10B8200017F8BFE017018010261C801817FBBFE037
+:10B830001700801015FBBFE017FBBFE01EF63F109E
+:10B8400006190000B401820017A6B61015FBBFE070
+:10B85000060F000017FBBFE0172A80104C00801075
+:10B860002608001017FBBFE01727801026050010E0
+:10B8700017FBBFE0172780101706801058008010B4
+:10B880002608001017FBBFE01700801015FBBFE073
+:10B8900017FBBFE01EEF3F10060300003A880100CF
+:10B8A000060100003A88010017FBBFE01E170010D8
+:10B8B000B401820017A6B61015FBBFE0060B00000E
+:10B8C00017FBBFE0172780102605001017FBBFE00D
+:10B8D00017278010170680105800801026060010C9
+:10B8E00017FBBFE01700801015FBBFE017FBBFE0A0
+:10B8F0001EF33F10060100003A88010017FBBFE06D
+:10B900001E020010441F8000066D000017F6BFE005
+:10B9100017FBFFE01506C01017F4BFE017038010F7
+:10B920002604001017F4BFE01703C01017F6BFE09D
+:10B93000150BC01017F4BFE0170480100C0088101E
+:10B94000260800103A88090040FF288017F63FE1DA
+:10B95000C0F63A8015FEBFE03A88090080F32880DF
+:10B960000628000017F6BFE01703801004FBBF1085
+:10B9700015F5BFE017F8BFE017018010260500108D
+:10B9800017F8BFE01701C01017F5BFE01503C0108E
+:10B99000060E000017FDBFE0D8FFBF101E06001006
+:10B9A00017F6BFE017068010170AC01017F5BFE0A2
+:10B9B0001503C0100605000017FD3FE180023B8023
+:10B9C0003A88071017F5BFE01503C01017F5BFE060
+:10B9D00017FDFFE01504C0103A88090040FF2880D9
+:10B9E00017F8BFE003058010CC3F801017F67FE109
+:10B9F0003A880910809E3A8015FEBFE03A88090017
+:10BA000080F3288017FEBFE00E02001017FEBFE093
+:10BA1000062B00003A8805000629000017F2BFE057
+:10BA20001E020010840580000625000017F2BFE00A
+:10BA30001703801015F7BFE017F7BFE01E020010D4
+:10BA400084058000061E000017F43FE1800C2B8067
+:10BA500015F8BFE017F8BFE01E0200108405800053
+:10BA60000617000017F7BFE08D00001017F2BFE0C7
+:10BA70000404C0001502C01017FABFE0D8038010FC
+:10BA80001E05001017F8BFE01701C01017F7BFE040
+:10BA90001501C0100604000017F8BFE01702C0101F
+:10BAA00017F7BFE01501C0103A8805000604000032
+:10BAB00040CD28803A88050006010000C4178000A8
+:10BAC00004FFFFE61702C0DF170100DF170000DCEC
+:10BAD0000403C0DE3A2800F804FCFFDE1503C0DFD3
+:10BAE000150200DF040200DF15FF3FE115FE7FE1D4
+:10BAF00017FFBFE017058010980080101E0400108B
+:10BB000017FEBFE0280480101E01001040CD2880E1
+:10BB10003A8801003A8837E01701C0DF170000DFDC
+:10BB20000402C0DE3A2800F804FAFFDE1505C0DF83
+:10BB3000150400DF040400DF15FE3FE115FD7FE181
+:10BB400015FCBFE13A88090080F3288017FCBFE1AB
+:10BB500017FD7FE117FE3FE100052D8015FFBFE0D7
+:10BB600017FFBFE01E0400103A88090040FF28803C
+:10BB7000C4FFBF000607000017FFBFE01506001056
+:10BB80003A88090040FF288017FFBFE0BAD00410B0
+:10BB9000040480103A8837E01701C0DF170000DF87
+:10BBA0000402C0DE3A2800F804F2FFDE150DC0DF03
+:10BBB000150C00DF040C00DF15F63FE115F57FE101
+:10BBC00015F4BFE117F6BFE004FCBF10BA900410F3
+:10BBD00015FDBFE0B40182000471B81015FEBFE08E
+:10BBE0000606000017FEFFE017FDBFE026068018DE
+:10BBF00017FEBFE01700801015FEBFE017FEBFE084
+:10BC00001EF83F10060100003A88010017FEFFE011
+:10BC100017FDBFE02603801840CD2880C4FFBF0079
+:10BC20000634000017F47FE117FD3FE100A22B80EE
+:10BC300017FDBFE01506001017F5BFE01E0D001040
+:10BC400004F7BFE0040480013A880B003A88091029
+:10BC5000408E08800404800015F4BFE017FDBFE0AB
+:10BC6000170580100DF7BFE004F7BFE015FFBFE038
+:10BC70000602000017F5BFE015FFBFE04402800197
+:10BC800017F47FE117FF3FE100F32C8015FCBFE0C4
+:10BC900017FCBFE01E05001017FDBFE00403C00045
+:10BCA0001506C010C4FFBF00061200003A88090044
+:10BCB00080F3288017FC7FE117FD3FE1801F2D8076
+:10BCC00015FBBFE017FC3FE1C0CF29803A8809008F
+:10BCD00040FF288017FBBFE02605001017FDBFE0DE
+:10BCE00017FBFFE01506C010C4FFBF0006010000EF
+:10BCF0003A8805003A8837E01701C0DF170000DFF7
+:10BD00000402C0DE3A2800F804F9FFDE1506C0DFA1
+:10BD1000150500DF040500DF15FC3FE115FB7FE1A1
+:10BD200017FCBFE004FCBF10BA90041015FEBFE082
+:10BD3000B40182000471B81015FFBFE006060000D0
+:10BD400017FFFFE017FEBFE02606801817FFBFE0D1
+:10BD50001700801015FFBFE017FFBFE01EF83F106F
+:10BD6000060100003A88010017FFFFE017FEBFE060
+:10BD70002603801840CD2880C4FFBF0006120000B3
+:10BD800017FEBFE0150600103A88090080F32880EE
+:10BD900017FB7FE117FE3FE140252D8015FDBFE039
+:10BDA0003A88090040FF288017FDBFE026050010F3
+:10BDB00017FEBFE017FDFFE01506C010C4FFBF006F
+:10BDC000060100003A8805003A8837E01701C0DF15
+:10BDD000170000DF0402C0DE3A2800F804F7FFDE97
+:10BDE0001508C0DF150700DF040700DF15FB3FE182
+:10BDF00015FA7FE115F9BFE117FBBFE004FCBF10A6
+:10BE0000BA90041015FEBFE0B40182000471B810AE
+:10BE100015FFBFE00606000017FFFFE017FEBFE0BA
+:10BE20002606801817FFBFE01700801015FFBFE03F
+:10BE300017FFBFE01EF83F10060100003A8801001E
+:10BE400017FFFFE017FEBFE02603801840CD2880D3
+:10BE5000C4FFBF000670000017F9BFE01700801094
+:10BE60003A880B1017FE3FE100A22B8017FEBFE0BF
+:10BE70001506001017FEBFE0170480108C0080101C
+:10BE80001E05001017FEBFE08405C0001506C01097
+:10BE9000C4FFBF000660000017FEBFE08B088010E3
+:10BEA000CCFFBF100C408010260B001017FEBFE027
+:10BEB000431E8010CC3F80101C20801004E0BF1077
+:10BEC0001E05001017FEBFE0C402C0001506C0101A
+:10BED000C4FFBF00065000003A88090080F32880A4
+:10BEE0000610000017FEBFE08B088010CCFFBF10CB
+:10BEF0000C0880102607001017FEBFE0441CC0008D
+:10BF00001506C0103A88090040FF2880C4FFBF0012
+:10BF10000641000017FEBFE0040980103A880910AE
+:10BF200040A5278017FEBFE0431E8010CC3F801045
+:10BF30001C20801004E0BF101E03001017FEBFE09D
+:10BF40001706801026E73F1017FEBFE01706801087
+:10BF5000260400103A88090040FF2880C4FFBF0073
+:10BF6000062D0000040440014402000100A72980BE
+:10BF700015FDBFE017FDBFE01E0700103A8809005D
+:10BF800040FF288017FEBFE00403C0001506C01064
+:10BF9000C4FFBF000620000017FEBFE0171D801081
+:10BFA00015FCBFE04400400117FC3FE1C06E2F804C
+:10BFB0001E0300107401020104742A2180172780D7
+:10BFC00017FCBFE015FEBFE017FD7FE117FE3FE164
+:10BFD000C0742D8017FABFE02608001017FDBFE0DF
+:10BFE0001703C01017F9BFE0170080103A880D1032
+:10BFF0003A880B1817FA3FE1806B088017FD3FE184
+:10C00000C0CF29803A88090040FF288017FEBFE092
+:10C01000BAD00410040480103A8837E01701C0DF5A
+:10C02000170000DF0402C0DE3A2800F804F8FFDE43
+:10C030001507C0DF150600DF040600DF15FC3FE131
+:10C0400015FB7FE115FABFE117FCBFE004FCBF1050
+:10C05000BA90041015FEBFE0B40182000471B8105C
+:10C0600015FFBFE00606000017FFFFE017FEBFE068
+:10C070002606801817FFBFE01700801015FFBFE0ED
+:10C0800017FFBFE01EF83F10060100003A880100CC
+:10C0900017FFFFE017FEBFE02603801840CD288081
+:10C0A000C4FFBF000678000017FA7FE117FE3FE1EA
+:10C0B00000A22B8017FEBFE08B088010CCFFBF10C2
+:10C0C0000C4080102624001017FEBFE08B08801063
+:10C0D000CCFFBF100C0180102605001017FEBFE03A
+:10C0E000C41DC0001506C010C4FFBF0006660000D6
+:10C0F00017FEBFE08B088010CCFFBF108C008010B3
+:10C100002604001017FEBFE0150600103A8805004F
+:10C11000065D000017FEBFE08B088010CCFFBF104B
+:10C120000C008810260C001017FEBFE08B08C01012
+:10C13000C4FFB7003A7084183A88071017FEBFE0B2
+:10C140008D08C01017FEBFE01706801026020010F1
+:10C15000C4FFBF00064C000017FEBFE0150600102C
+:10C160004402800117FA7FE117FB3FE100F32C80C6
+:10C1700015FDBFE017FDBFE01E05001017FEBFE074
+:10C180000403C0001506C010C4FFBF00063E000037
+:10C190003A88090080F3288017FD7FE117FE3FE110
+:10C1A000407E2D803A88071017FEBFE01506C010AC
+:10C1B00017FEBFE0170680101E1B001017FEBFE021
+:10C1C0008B088010CCFFBF100C408010260D001093
+:10C1D00017FEBFE08B088010CCFFBF100C01801051
+:10C1E0002608001017FEBFE0C41DC0001506C010D1
+:10C1F0000610000017FEBFE0040980103A880910FD
+:10C2000040A5278017FEBFE08B088010CCFFBF1031
+:10C210000C0180102606001017FEBFE017068010E4
+:10C2200026F43F10060200003A88010006010000D3
+:10C230003A88010017FEBFE017068010E01D80104D
+:10C240001E07001017FEBFE08B08C010C4FEB70029
+:10C250003A7084183A88071017FEBFE08D08C010A6
+:10C2600017FD3FE1C0CF29803A88090040FF2880B0
+:10C2700017FEBFE01706801026020010C4FFBF00A3
+:10C28000060100003A8805003A8837E01701C0DF50
+:10C29000170000DF0402C0DE3A2800F804FBFFDECE
+:10C2A0001504C0DF150300DF040300DF15FF3FE1C5
+:10C2B00015FE7FE115FDBFE10404C00117FDBFE1DC
+:10C2C00017FE7FE117FF3FE1C0262C803A8837E058
+:10C2D0001701C0DF170000DF0402C0DE3A2800F8B3
+:10C2E00004FBFFDE1504C0DF150300DF040300DFDD
+:10C2F00015FF3FE115FE7FE115FDBFE1C403C0015D
+:10C3000017FDBFE117FE7FE117FF3FE1C0262C803C
+:10C310003A8837E01701C0DF170000DF0402C0DEF3
+:10C320003A2800F804F6FFDE1509C0DF150800DF23
+:10C33000040800DF15FB3FE115FA7FE115F9BFE1C5
+:10C3400015F8FFE117FBBFE004FCBF10BA90041022
+:10C3500015FEBFE0B40182000471B81015FFBFE004
+:10C360000606000017FFFFE017FEBFE02606801854
+:10C3700017FFBFE01700801015FFBFE017FFBFE0F9
+:10C380001EF83F10060100003A88010017FFFFE089
+:10C3900017FEBFE02603801840CD2880C4FFBF00F1
+:10C3A0000653000017FEBFE01506001017F8BFE0A7
+:10C3B000180480101E0A001017FEBFE08B088010C2
+:10C3C000CCFFBF108C0080101E05001017FEBFE0D0
+:10C3D0000420C0001506C010C4FFBF0006440000C2
+:10C3E0003A88090080F328800404400144020001D7
+:10C3F00000A7298015FDBFE017FDBFE01E07001054
+:10C4000017FEBFE00403C0001506C0103A880900FB
+:10C4100040FF2880C4FFBF000635000017FEBFE0C4
+:10C4200017F8FFE01507C01017FEBFE017028010D5
+:10C430001703801017FDBFE13A880B0017FE3FE19C
+:10C440003AE83E1015FCBFE017FCBFE01E190010D3
+:10C4500017FEBFE017058010980080101E1700100F
+:10C4600017F9BFE017008010280480101E07001085
+:10C4700040CD288017FD3FE1C0CF29803A880900D0
+:10C4800040FF2880840580000619000017FDBFE0EA
+:10C4900017038010040480013A880B1017FA3FE15B
+:10C4A000806B088017F9BFE00404C0001500C010BD
+:10C4B000060300003A880100060100003A880100E6
+:10C4C00017FD3FE1C0CF29803A88090040FF28804E
+:10C4D00017FCBFE02605001017FEBFE017FCFFE0C9
+:10C4E0001506C010C4FFBF00060100003A88050011
+:10C4F0003A8837E01701C0DF170000DF0402C0DE12
+:10C500003A2800F804F7FFDE1508C0DF150700DF42
+:10C51000040700DF15FC3FE115FB7FE115FABFE1E1
+:10C5200015F9FFE117FCBFE004FCBF10BA9004103E
+:10C5300015FEBFE0B40182000471B81015FFBFE022
+:10C540000606000017FFFFE017FEBFE02606801872
+:10C5500017FFBFE01700801015FFBFE017FFBFE017
+:10C560001EF83F10060100003A88010017FFFFE0A7
+:10C5700017FEBFE02603801840CD2880C4FFBF000F
+:10C58000064B00003A88090080F3288017FEBFE0C0
+:10C590001506001017FBBFE0600080101E0E001093
+:10C5A00017F9BFE117FA7FE117FE3FE100782E800F
+:10C5B00015FDBFE017FDBFE0263A001017FEBFE0F3
+:10C5C00017FDFFE01506C0103A88090040FF2880DB
+:10C5D000C4FFBF000636000017FEBFE0171F801023
+:10C5E0001E0F001004010001C08229803A88071044
+:10C5F00017FEBFE0151FC01017FEBFE0171F801009
+:10C600001E07001017FEBFE00403C0001506C0108F
+:10C610003A88090040FF2880C4FFBF0006240000BC
+:10C6200017FABFE0180180101E06001017F9BFE0CE
+:10C630001700C01017FEBFE0171F80104500C01084
+:10C640000618000017FABFE0D80080101E06001080
+:10C6500017F9BFE01700C01017FEBFE0171F8010CA
+:10C660000500C010060F000017FABFE09803801005
+:10C670001E08001017F9BFE0170080103A88071055
+:10C6800017FEBFE0171F8010CC3FC0181501C01067
+:10C69000060400003A88090040FF2880C4FFBF005C
+:10C6A000060300003A88090040FF28803A88050008
+:10C6B0003A8837E01701C0DF170000DF0402C0DE50
+:10C6C0003A2800F804F7FFDE1508C0DF150700DF81
+:10C6D000040700DF15FC3FE115FB7FE115FABFE120
+:10C6E00015F9FFE117FCBFE004FCBF10BA9004107D
+:10C6F00015FEBFE0B40182000471B81015FFBFE061
+:10C700000606000017FFFFE017FEBFE026068018B0
+:10C7100017FFBFE01700801015FFBFE017FFBFE055
+:10C720001EF83F10060100003A88010017FFFFE0E5
+:10C7300017FEBFE02603801840CD2880C4FFBF004D
+:10C74000063D00003A88090080F3288017FBBFE00F
+:10C75000600080101E0E001017F9BFE117FA7FE18C
+:10C7600017FE3FE1C0C02E8015FDBFE017FDBFE002
+:10C77000262C001017FEBFE017FDFFE01506C010C5
+:10C780003A88090040FF2880C4FFBF00062A000045
+:10C7900017FABFE0180180101E0E001017FEBFE050
+:10C7A000171F80101E04001017F9BFE00410C0000E
+:10C7B0001500C010061B000017FEBFE0171F8010F9
+:10C7C00043008010CC3FC01017F9BFE01500C01027
+:10C7D0000614000017FABFE0D80080101E0D0010EC
+:10C7E00017FEBFE0171F80101E03001017F9BFE0EF
+:10C7F00015000010060B000017FEBFE0171F801089
+:10C8000003008010CC3FC01017F9BFE01500C01026
+:10C81000060400003A88090040FF2880C4FFBF00DA
+:10C820000605000017FEBFE0150600103A88090053
+:10C8300040FF28803A8805003A8837E01701C0DFBA
+:10C84000170000DF0402C0DE3A2800F804F6FFDE1D
+:10C850001509C0DF150800DF040800DF15FC3FE103
+:10C8600015FB7FE115FABFE115F9FFE117FABFE00B
+:10C8700015FFBFE017FCBFE004FCBF10BA90041026
+:10C8800015FEBFE017FEBFE08B088010CCFFBF1085
+:10C890008C038010A00080101E05001017FEBFE062
+:10C8A0000408C0001506C010C4FFBF000619000030
+:10C8B00017FEBFE0150600103A88090080F32880B3
+:10C8C00004FAFFE017F9BFE0150080D83A880F1886
+:10C8D00017FBBFE13A880B0017FE3FE140E92D80CE
+:10C8E00015FDBFE03A88090040FF288017FDBFE032
+:10C8F0002605001017FEBFE017FDFFE01506C0106B
+:10C90000C4FFBF000603000017FABFE017FFFFE0F7
+:10C910003AC885183A8837E01701C0DF170000DFF2
+:10C920000402C0DE3A2800F804F4FFDE150BC0DF75
+:10C93000150A00DF040A00DF15FA3FE115F97FE16F
+:10C9400015F8BFE115F7FFE115FB3FE017F8BFE071
+:10C9500015FEBFE017FABFE004FCBF10BA90041048
+:10C9600015FDBFE0B40182000471B81015FFBFE0EF
+:10C970000606000017FFFFE017FDBFE0260680183F
+:10C9800017FFBFE01700801015FFBFE017FFBFE0E3
+:10C990001EF83F10060100003A88010017FFFFE073
+:10C9A00017FDBFE02603801840CD2880C4FFBF00DC
+:10C9B0000627000017FDBFE0150600103A880900A1
+:10C9C00080F3288004F83FE104FBFFE017F7BFE0A5
+:10C9D000150080D83A880F2017F9BFE13A880B1864
+:10C9E00017FD3FE140E92D8015FCBFE017FBBFE0DC
+:10C9F000260B001017FBBFE01703C010170380E0E1
+:10CA0000170080103A880D103A880B18170200E1C1
+:10CA1000806B088017FBBFE03A880910C0CF2980DF
+:10CA20003A88090040FF288017FCBFE02605001067
+:10CA300017FDBFE017FCFFE01506C010C4FFBF00E4
+:10CA40000603000017F8BFE017FEFFE03AC885189C
+:10CA50003A8837E01701C0DF170000DF0402C0DEAC
+:10CA60003A2800F804F4FFDE150BC0DF150A00DFDA
+:10CA7000040A00DF15FA3FE115F97FE115F8BFE17F
+:10CA800015F7FFE117FABFE004FCBF10BA900410DD
+:10CA900015FDBFE0B40182000471B81015FEBFE0BF
+:10CAA0000606000017FEFFE017FDBFE0260680180F
+:10CAB00017FEBFE01700801015FEBFE017FEBFE0B5
+:10CAC0001EF83F10060100003A88010017FEFFE043
+:10CAD00017FDBFE02603801840CD2880C4FFBF00AB
+:10CAE0000657000017FDBFE01506001017FDBFE058
+:10CAF00083098010CC3F80101C20801004E0BF1000
+:10CB0000A000C0101E0A0018E000C0101E0B001884
+:10CB1000580080101E10001017F7FFE117F8BFE152
+:10CB200017F97FE117FA3FE1C0B92C8006440000F5
+:10CB300040D93D8015FBBFE0060D000017FDBFE0AA
+:10CB4000170480100C0088103A88091000AE3C8051
+:10CB500015FBBFE00606000040CD288017FDBFE0B2
+:10CB60008403C0001506C010C4FFBF0006340000D7
+:10CB700017FBFFE017F8BFE00E05801817FDBFE0B8
+:10CB8000841EC0001506C010C4FFBF00062C0000A4
+:10CB9000170280E0260C001044028001170340E1D8
+:10CBA000170200E100F32C8015FFBFE017FFBFE084
+:10CBB0001E06001017FDBFE00403C0001506C010DC
+:10CBC000C4FFBF00061E000015FF3FE017F8BFE0DE
+:10CBD00015FBBFE03A88090080F3288004FBFFE0E2
+:10CBE00017F7BFE0150080D83A880F1817F9BFE192
+:10CBF00017FF7FE117FD3FE140932D8015FCBFE05B
+:10CC000017FFBFE02602001017FF3FE1C0CF2980C9
+:10CC10003A88090040FF288017FCBFE02605001075
+:10CC200017FDBFE017FCFFE01506C010C4FFBF00F2
+:10CC30000603000017FBBFE017F8FFE03AC88518AD
+:10CC40003A8837E01701C0DF170000DF0402C0DEBA
+:10CC50003A2800F804F1FFDE150EC0DF150D00DFE5
+:10CC6000040D00DF15F83FE115F77FE115F6BFE190
+:10CC700015F5FFE115FF3FE017F8BFE004FCBF101A
+:10CC8000BA90041015FDBFE017FDBFE08B088010BF
+:10CC9000CCFFBF108C038010A00080101E05001078
+:10CCA00017FDBFE00408C0001506C010C4FFBF0098
+:10CCB0000663000017FDBFE01506001017FDBFE07A
+:10CCC00083098010CC3F80101C20801004E0BF102E
+:10CCD000600080101E080010150100D8150000D853
+:10CCE00017F5FFE117F6BFE117F77FE117F83FE10E
+:10CCF000C09A2C8006520000046D810015FEBFE032
+:10CD000017FDBFE0170180102648001017FDBFE097
+:10CD1000170180101709801015FCBFE017FCBFE059
+:10CD20000B0A8010CCFFBF102640001017FCBFE09C
+:10CD30000B0A8010CCFFBF1015FEBFE0063B0000C1
+:10CD400017F6BFE017FEFFE00E03801817FEBFE0E6
+:10CD500015F9BFE00602000017F6BFE015F9BFE0C5
+:10CD600017F9BFE015FBBFE03A88090080F328807F
+:10CD700004F9FFE017F5BFE0150080D83A880F18D6
+:10CD800017F7BFE13A880B0017FD3FE140932D8074
+:10CD900015FABFE03A88090040FF288017FABFE083
+:10CDA0002610001017FABFE0601A80101E03001052
+:10CDB00017FABFE0D80280101E05001017FFBFE071
+:10CDC0002603001017FDBFE015060010061B00002B
+:10CDD00017FDBFE017FAFFE01506C010C4FFBF0043
+:10CDE0000617000017F9BFE01E13001017F9BFE087
+:10CDF00017FBFFE03AC8851815FBBFE017FBBFE043
+:10CE000017F7FFE03A88851815F7BFE017F6FFE03F
+:10CE100017FBBFE03AC8851815F6BFE017FFFFE023
+:10CE200017FBBFE03A88851815FFBFE017F6BFE093
+:10CE30001EC33F10060100003A88010017FFBFE043
+:10CE40003A8837E01701C0DF170000DF0402C0DEB8
+:10CE50003A2800F804F9FFDE1506C0DF150500DFEB
+:10CE6000040500DF15FC3FE115FB7FE117FCBFE087
+:10CE700004FCBF10BA90041015FEBFE0B40182009C
+:10CE80000471B81015FFBFE00606000017FFFFE0B1
+:10CE900017FEBFE02606801817FFBFE017008010BE
+:10CEA00015FFBFE017FFBFE01EF83F1006010000AE
+:10CEB0003A88010017FFFFE017FEBFE02603801845
+:10CEC00040CD2880C4FFBF000612000017FEBFE05F
+:10CED000150600103A88090080F3288017FB7FE1CF
+:10CEE00017FE3FE1C05E2E8015FDBFE03A880900C5
+:10CEF00040FF288017FDBFE02605001017FEBFE0A9
+:10CF000017FDFFE01506C010C4FFBF0006010000BA
+:10CF10003A8805003A8837E01701C0DF170000DFC4
+:10CF20000402C0DE3A2800F804FAFFDE1505C0DF6F
+:10CF3000150400DF040400DF15FC3FE117FCBFE02F
+:10CF400004FCBF10BA90041015FEBFE0B4018200CB
+:10CF50000471B81015FFBFE00606000017FFFFE0E0
+:10CF600017FEBFE02606801817FFBFE017008010ED
+:10CF700015FFBFE017FFBFE01EF83F1006010000DD
+:10CF80003A88010017FFFFE017FEBFE02603801874
+:10CF900040CD2880C4FFBF00060E000017FEBFE092
+:10CFA000150600103A88090080F3288017FE3FE13B
+:10CFB00040432D8015FDBFE03A88090040FF2880DE
+:10CFC00017FDBFE026020010C4FFBF0006010000ED
+:10CFD0003A8805003A8837E01701C0DF170000DF04
+:10CFE0000402C0DE3A2800F804FAFFDE1505C0DFAF
+:10CFF000150400DF040400DF15FE3FE115FD7FE1AD
+:10D0000015FCBFE13A88090080F3288017FD7FE115
+:10D0100017FC3FE100A7298015FFBFE03A8809000F
+:10D0200040FF288017FFBFE01E0200103A8805006D
+:10D03000060B000017FDFFE017FFBFE01502C01050
+:10D0400017FFBFE01703801017FDFFE03A880D18A7
+:10D0500017FE7FE13A880910806B088017FFBFE058
+:10D060003A8837E01701C0DF170000DF0402C0DE96
+:10D070003A2800F804FAFFDE1505C0DF150400DFCA
+:10D08000040400DF15FC3FE117FCBFE004FCBF1007
+:10D09000BA90041015FDBFE0041B800015FEBFE030
+:10D0A0003A88090080F32880B40182000471B81026
+:10D0B00015FFBFE0060A000017FFFFE017FDBFE005
+:10D0C0001E04801817FDBFE01706801015FEBFE094
+:10D0D0000605000017FFBFE01700801015FFBFE036
+:10D0E00017FFBFE01EF43F103A88090040FF288078
+:10D0F00017FEBFE03A8837E01701C0DF170000DFF6
+:10D100000402C0DE3A2800F804F7FFDE1508C0DF8D
+:10D11000150700DF040700DF15FB3FE115FA7FE18B
+:10D1200015F9BFE117F9BFE02606001017FABFE1B5
+:10D1300017F97FE117FB3FE1409A298015FFBFE017
+:10D140000604000017FA7FE117FB3FE140912980B8
+:10D1500015FFBFE017FFBFE01E0200103A88050070
+:10D16000064E000017FFBFE00B008010CCFFBF1081
+:10D170001C00A0100400A01017FAFFE0260280187F
+:10D180003A8805000645000004210001C08229807C
+:10D1900015FEBFE017FEBFE01E0200103A88050032
+:10D1A000063E000017FEBFE01500001017FE7FE1ED
+:10D1B000B401020104713821009928800B1CA0D011
+:10D1C000CCFFFF1017FEBFE01504C01017FEBFE034
+:10D1D00017FBFFE01505C01017FEBFE08D0800101B
+:10D1E00017FABFE03A88071017FEBFE08509C010A4
+:10D1F00017FEBFE017FFFFE01502C01017FEBFE0EB
+:10D200001503001017FEBFE01507001017FFBFE061
+:10D210001703801017F9FFE03A880D183A880B00C1
+:10D2200017FE3FE13AE83E1015FDBFE017FDBFE0F5
+:10D230001E0A0010039AA0D0CC3F801026160010C2
+:10D240001798A0D017FE3FE13AE83E1015FCBFE06A
+:10D2500017FCBFE0260C0010060100003A88010010
+:10D2600017FEBFE08B088010540080103A8807102A
+:10D2700017FEBFE08D08C01017FE3FE140322D8041
+:10D280003A8805000605000080C727803A88071005
+:10D2900017FEBFE00520C01017FEBFE03A8837E058
+:10D2A0001701C0DF170000DF0402C0DE3A2800F8D3
+:10D2B00004FBFFDE1504C0DF150300DF040300DFFD
+:10D2C00015FE3FE115FD7FE117FEBFE08400C000C1
+:10D2D0001507C01017FEBFE017028010170380105B
+:10D2E00017FDBFE13A880B0017FE3FE13AE83E1018
+:10D2F00015FFBFE017FFBFE03A8837E01701C0DF36
+:10D30000170000DF0402C0DE3A2800F804FBFFDE4D
+:10D310001504C0DF150300DF040300DF15FE3FE145
+:10D3200015FD7FE117FEBFE0C400C0001507C01067
+:10D3300017FEBFE017028010170380103A880D0017
+:10D340003A880B0017FE3FE13AE83E1015FFBFE0B8
+:10D3500017FFBFE02602001017FFBFE0061A00000B
+:10D3600017FEBFE0171D80101E0B001017FEBFE058
+:10D3700017FEFFE0151DC01017FEBFE017FEFFE00F
+:10D38000151CC01017FEBFE0170480109400C010D9
+:10D3900017FEBFE01504C01017FDBFE00E0100101E
+:10D3A00015FD3FE017FDBFE0880180101E02001050
+:10D3B00017FDBFE0060100004401800017FEFFE0FA
+:10D3C000851E80183A8805003A8837E01701C0DFCB
+:10D3D000170000DF0402C0DE3A2800F804FDFFDE7B
+:10D3E0001502C0DF150100DF040100DF15FF3FE17A
+:10D3F00017FFBFE0170180101E36001017FFBFE0B7
+:10D400008B088010CCFFBF104C008010263100101C
+:10D4100017FFBFE0171B8010260D00103A880B0085
+:10D4200017FF3FE1C06E2F801E070010440040012F
+:10D4300017FF3FE1C06E2F801E0300107401020130
+:10D4400004762A218017278017FFBFE0151B0010E4
+:10D4500017FFBFE0041280103A88091000AB2F803C
+:10D4600017FF3FE140682E8017FFBFE017038010D1
+:10D470002604001017FFBFE0170380103A88091038
+:10D4800040E73E8017FFBFE0171F80102604001002
+:10D4900017FFBFE0171F80103A8809100086298007
+:10D4A00017FF7FE1B40102010471382100A4288034
+:10D4B000039AA0D0CC3F8010260300101799A0D06B
+:10D4C00017FF3FE13AE83E1017FF3FE10086298051
+:10D4D000060100003A8801003A8837E01701C0DFF2
+:10D4E000170000DF0402C0DE3A2800F804F9FFDE6E
+:10D4F0001506C0DF150500DF040500DF15FB3FE161
+:10D5000015FF3FE0B40182001771B81015FEBFE0AF
+:10D510000606000017FBFFE017FEBFE02606801896
+:10D5200017FEBFE01700801015FEBFE017FEBFE03A
+:10D530001EF83F10060100003A88010017FEBFE008
+:10D540001E020010840580000695000017FBBFE056
+:10D55000170480108C0080102612001006040000B2
+:10D5600017FBBFE0171C80103A880910C06F2D8090
+:10D5700017FBBFE0171C801017FBFFE01EF8BF1859
+:10D580000604000017FBBFE0171D80103A88091041
+:10D59000C06F2D8017FBBFE0171D801017FBFFE049
+:10D5A0001EF8BF1817FBBFE083098010CC3F801026
+:10D5B0001C20801004E0BF10600080101E0C0010C2
+:10D5C00017FBBFE04400C0001507C01017FBBFE009
+:10D5D00017028010170380103A880D003A880B005C
+:10D5E00017FB3FE13AE83E1015FFBFE0065D000083
+:10D5F00017FBBFE0170180102657001017FBBFE094
+:10D600008B088010CCFFBF108C008010263A0010D1
+:10D6100017FBBFE08B088010CCFFBF100C028010FE
+:10D620001E05001017FB3FE1C0892D8015FFBFE0EC
+:10D6300017FFBFE01E32001017FBBFE01704801079
+:10D640000C2080102621001017FBBFE08B088010F3
+:10D65000CCFFBF100C0280102605001017FBBFE0A6
+:10D660008B088010CCFFBF100C4080101E260010CD
+:10D6700017FBBFE00B088010CCFFBF101C00A010F0
+:10D680000400A0102419C010177DA0D03A88851876
+:10D6900015FDBFE00604000017FBBFE00409801081
+:10D6A0003A88091040A5278017FBBFE08B0880103F
+:10D6B000CCFFBF108C00801026140010177DE0D026
+:10D6C00017FDBFE036F4BF180610000017FBBFE0DF
+:10D6D000171280102608001017FBBFE08B0880107F
+:10D6E000540080103A88071017FBBFE08D08C01067
+:10D6F0003A880500062A00003A8801000603000067
+:10D700003A880100060100003A88010017FBBFE0DB
+:10D71000170180102612001017FBBFE04400C00064
+:10D720001507C01017FBBFE0170280101703801009
+:10D730003A880D003A880B0017FB3FE13AE83E10AB
+:10D7400015FCBFE017FFBFE01E05001017FCBFE08F
+:10D7500015FFBFE0060300003A8801000601000043
+:10D760003A88010017FBBFE08B088010CCFFBF1088
+:10D770004C0080102601001040CD288017FBBFE030
+:10D780008B088010540080103A88071017FBBFE008
+:10D790008D08C01017FB3FE140322D8017FFBFE01E
+:10D7A0003A8837E01701C0DF170000DF0402C0DE4F
+:10D7B0003A2800F804FDFFDE1502C0DF150100DF86
+:10D7C000040100DF15FF3FE117FFBFE08402C00046
+:10D7D0001507C01017FFBFE0170280101703801055
+:10D7E0003A880D003A880B0017FF3FE13AE83E10F7
+:10D7F0003A8837E01701C0DF170000DF0402C0DEFF
+:10D800003A2800F804FBFFDE1504C0DF150300DF33
+:10D81000040300DF15FE3FE115FD7FE117FEBFE0C9
+:10D820008B088010CCFFBF104C0080101E0300102E
+:10D830007401020104782A218017278017FEBFE0B7
+:10D840008B08C01084FFBF003A7084183A88071014
+:10D8500017FEBFE08D08C01017FEBFE04401C000F6
+:10D860001507C01017FEBFE01702801017038010C5
+:10D8700017FDBFE13A880B0017FE3FE13AE83E1082
+:10D8800015FFBFE017FFBFE03A8837E01701C0DFA0
+:10D89000170000DF0402C0DE3A2800F804FBFFDEB8
+:10D8A0001504C0DF150300DF040300DF15FE3FE1B0
+:10D8B00015FD7FE117FEBFE0170480108C0080107B
+:10D8C00026020010C4178000061D000017FEBFE0EE
+:10D8D0008B088010CCFFBF108C018010260C00102C
+:10D8E00017FEBFE0170280100B018010CCFFBF10A5
+:10D8F0000C0180101E03001017FE3FE1C0892D802F
+:10D9000026030010C41F800015FFBFE0060B0000B7
+:10D9100017FEBFE00401C0001507C01017FEBFE0EE
+:10D92000170280101703801017FDBFE13A880B0023
+:10D9300017FE3FE13AE83E1015FFBFE017FFBFE0DA
+:10D940003A8837E01701C0DF170000DF0402C0DEAD
+:10D950003A2800F804FCFFDE1503C0DF150200DFE3
+:10D96000040200DF15FE3FE117FEBFE08B088010C8
+:10D97000CCFFBF108C0080101E030010042080001C
+:10D9800015FFBFE00613000017FEBFE08B088010F4
+:10D99000CCFFBF100C02801026030010041E800074
+:10D9A00015FFBFE0060B000017FEBFE08401C000BA
+:10D9B0001507C01017FEBFE0170280101703801074
+:10D9C0003A880D003A880B0017FE3FE13AE83E1016
+:10D9D00015FFBFE017FFBFE03A8837E01701C0DF4F
+:10D9E000170000DF0402C0DE3A2800F804F2FFDE70
+:10D9F000150DC0DF150C00DF040C00DF15F73FE14B
+:10DA000015F67FE115F5BFE115F4FFE115FF3FE0E5
+:10DA100015FB3FE04400800015FABFE017F4BFE0BB
+:10DA20001700801015FCBFE017FCBFE00E020010CD
+:10DA3000840580000640010017F7BFE01702801040
+:10DA40000B018010CCFFBF104C0080102607001087
+:10DA500017F7BFE0171380103A88071017FCBFE0D4
+:10DA60000E028018841E800006330100170280E039
+:10DA70000C018010260C001017F7BFE0170480106F
+:10DA80000C0480101E08001017F7BFE0170280106A
+:10DA90000B018010CCFFBF104C008010260200103C
+:10DAA00044008000060100003A88050015F9BFE037
+:10DAB0000604000017F7BFE0041980103A88091027
+:10DAC00040A5278017F7BFE00B198010CCFFBF10CF
+:10DAD0004C0080101EF73F1017F7BFE00B198010A5
+:10DAE000540080103A88071017F7BFE00D19C010D6
+:10DAF00017F7BFE0170680102606001017F7BFE0E3
+:10DB00001706801015FBBFE017F7BFE015060010E1
+:10DB100006F9000017F7BFE08B088010CCFFBF109C
+:10DB20000C048010260300100408800015FBBFE0E1
+:10DB300006F1000017F7BFE08B088010CCFFBF1084
+:10DB40008C0080101E0E001017F7BFE01702801027
+:10DB50000B018010CCFFBF100C01801026030010B9
+:10DB60000420800015FBBFE006E3000017F6BFE0CD
+:10DB70001E030010441E800015FBBFE006DE0000FF
+:10DB8000170280E04C008010260300100400810082
+:10DB900015FDBFE00647000017F7BFE01713801020
+:10DBA0003A88071017F7BFE0171280103AC8851897
+:10DBB0001606001017F7BFE01713C01017F7BFE0E5
+:10DBC000171280103AC88518060100003A8805002F
+:10DBD00015FDBFE017F7BFE0170280100B018010A2
+:10DBE000CCFFBF104C0080102603001017FDFFE093
+:10DBF00017FCBFE01612801817FCBFE0105E811002
+:10DC00001E2C001017FDBFE0085E81101E290010B9
+:10DC100017F7BFE017128010305E81101E2500102C
+:10DC200017F7BFE08B088010CCFFBF100C408010AE
+:10DC30001E200010170280E00C0880101E1D00102E
+:10DC400017F7BFE08B088010CCFFBF100C4080108E
+:10DC50001E030010170280E00C088010260500103B
+:10DC600017FABFE0269D0010C402800015FBBFE03C
+:10DC7000069A000017F7BFE00B19C01084FFBF0021
+:10DC80003A7084183A88071017F7BFE00D19C010D2
+:10DC900017F7BFE0041980103A88091000BA2780EE
+:10DCA00017F7BFE0041280103A880910008E2F8009
+:10DCB000067F3F0017FDBFE0165E800017F7BFE04C
+:10DCC0008B088010CCFFBF100C4080101E0300108A
+:10DCD000170280E00C0880102605001017FABFE03C
+:10DCE00026800010C402800015FBBFE0067D000006
+:10DCF00017F7BFE00B19C01084FFBF003A708418FB
+:10DD00003A88071017F7BFE00D19C01017F7BFE0EA
+:10DD1000041980103A88091000BA278017F7BFE06D
+:10DD2000041280103A880910008E2F8006603F0090
+:10DD300017FCBFE015F8BFE017F7BFE083098010BC
+:10DD4000CC3F80101C20801004E0BF1058008010D1
+:10DD50001E17001017F87FE18400000100A729803A
+:10DD600015FEBFE017FEBFE01E030010441A80003E
+:10DD700015FBBFE00660000017FEBFE01703801030
+:10DD800017F8FFE03A880D1817F57FE13A88091077
+:10DD9000806B088017F7BFE00B19801014208010EB
+:10DDA0003A88071017F7BFE00D19C01006070000EA
+:10DDB0003A880B008400000100A7298015FEBFE00F
+:10DDC00017FEBFE017F5FFE01503C01017F4BFE022
+:10DDD0001700C01017F8BFE03AC8871817F4BFE063
+:10DDE0001500C01017FCFFE017F8BFE03AC885180F
+:10DDF00015FCBFE017F8BFE017F5FFE03A8885187B
+:10DE000015F5BFE017F8FFE017FEBFE01502C010E0
+:10DE100017FFBFE01E02001017FEBFE015FFBFE0B6
+:10DE200017FBBFE01E31001017F4BFE01700801091
+:10DE30000E03800017FDBFE016BDBF000601000005
+:10DE40003A88010017F9BFE02605001017F7BFE078
+:10DE5000170480101404C01017F7BFE01504C01099
+:10DE6000170280E04C00801026020010840380001E
+:10DE7000060100004402800017F7FFE01507801834
+:10DE800017F7BFE0170280101703801017F6BFE1E5
+:10DE900017FF7FE117F73FE13AE83E1015FBBFE0BF
+:10DEA00017F9BFE02606001017F7BFE01704C010EF
+:10DEB000C4FBBF003A70861817F7BFE01504C01006
+:10DEC00015FF3FE015FA3FE017FCBFE02609001000
+:10DED00017FBBFE026063F10060600003A88010047
+:10DEE000060500003A880100060300003A88010098
+:10DEF000060100003A88010017F7BFE00B19C010B7
+:10DF000084FFBF003A7084183A88071017F7BFE003
+:10DF10000D19C01017F7BFE0041980103A880910D6
+:10DF200000BA278017FFBFE02602001017FF3FE16D
+:10DF3000C0CF298017FBBFE03A8837E01701C0DF68
+:10DF4000170000DF0402C0DE3A2800F804F2FFDE0A
+:10DF5000150DC0DF150C00DF040C00DF15F73FE1E5
+:10DF600015F67FE115F5BFE115F4FFE115FD3FE082
+:10DF700017F7BFE01702801015F9BFE017F6BFE0F2
+:10DF80002602001017F6BFE015000010170280E00F
+:10DF90004C008010264100103A880B00440000011C
+:10DFA00000A7298015FFBFE017FFBFE01E02001089
+:10DFB000441A800006B60100170280E08C00801031
+:10DFC00015F8BFE017F7BFE04403C0001507C01005
+:10DFD00017F9BFE01703801017F8FFE03A880D1813
+:10DFE00017FF7FE117F73FE13AE83E1015FDBFE06C
+:10DFF00017FDBFE01E23001017F4BFE017008010CC
+:10E0000015FEBFE017FFBFE0170280103A88071027
+:10E0100017FEBFE00E03801817FFBFE01702801045
+:10E0200015FEBFE017FFBFE01703801017FEFFE0EB
+:10E030003A880D183A880B1017F53FE1806B08807D
+:10E0400017FEBFE017F5FFE03A88851815F5BFE029
+:10E0500017F4BFE017FEFFE01500C01017FF3FE107
+:10E0600080BF298015FFBFE017F4BFE017008010C4
+:10E070002604001017FDBFE01E02001017FFBFE0CE
+:10E080001EDD3F1017FFBFE02602001017FF3FE123
+:10E09000C0CF298017FDBFE0067D01003A8801004E
+:10E0A0000604000017F7BFE0041180103A88091039
+:10E0B00040A5278017F7BFE00B118010CCFFBF10E1
+:10E0C0004C0080101EF73F1017F7BFE00B118010B7
+:10E0D000540080103A88071017F7BFE00D11C010E8
+:10E0E00017F7BFE0170A80101E3A001017F7BFE0BD
+:10E0F000170680102606001017F7BFE017068010DD
+:10E1000015FDBFE017F7BFE015060010065401002B
+:10E1100017F7BFE08B088010CCFFBF100C088010F1
+:10E120001E4A011017F7BFE08B088010CCFFBF100C
+:10E130008C0080101E09001017F7BFE01702801036
+:10E140000B018010CCFFBF100C01801026030010C3
+:10E150000420800015FDBFE00641010017F4BFE078
+:10E1600017008010263B011017F7BFE08B088010C6
+:10E17000CCFFBF100C4080101E030010170280E07F
+:10E180000C08801026030010C402800015FDBFE0BB
+:10E190000633010017F7BFE00B11C01084FFBF006A
+:10E1A0003A7084183A88071017F7BFE00D11C010B5
+:10E1B00017F7BFE0041180103A88091000BA2780D1
+:10E1C00017F7BFE0040A80103A880910008E2F80EC
+:10E1D00006B33F0017F7BFE01710801015FFBFE030
+:10E1E00017FFBFE01E03001074010201047B2A2107
+:10E1F0008017278017FFBFE01707801015FBBFE0CF
+:10E2000017F9BFE00B018010CCFFBF108C0080100D
+:10E210002642001017FFBFE0170880106002801030
+:10E220001E09001017FFBFE0170880103A880B1076
+:10E2300074010201047E2A2180C702807401020158
+:10E2400004842A2180172780170280E08C00801028
+:10E25000260F001017F6BFE02609001017FFBFE0D9
+:10E26000170280103A880D103A880B0017FF3FE123
+:10E2700000D429803A88071017F6BFE01500C010B7
+:10E2800017FFBFE01706801015FFBFE00623000050
+:10E2900017F7BFE0170AC01017FFBFE01702801082
+:10E2A0003AC8871817F7BFE0150AC01017F6BFE085
+:10E2B000260D001017F6BFE017FFFFE01500C01095
+:10E2C00017FFBFE01706801015FFBFE017F6BFE08D
+:10E2D000170080101506001017F7BFE017FFFFE0CA
+:10E2E0001510C0100608000017FF3FE180BF29800D
+:10E2F0003A88071017F7BFE01510C01017F7BFE0F6
+:10E300001710801015FFBFE017FFBFE026030010B5
+:10E3100017FFBFE017FBFFE01507C01015FA3FE03D
+:10E3200015FC3FE0069E000017FFBFE017088010B5
+:10E33000600080101E07001017FFBFE01708801054
+:10E34000E00080101E0300107401020104872A21DE
+:10E350008017278017F4BFE01700801015FEBFE07C
+:10E3600017F7BFE08B08C010C4EFBF003A708418E5
+:10E370003A88071017F7BFE08D08C01017F7BFE005
+:10E38000171A8010260C001017F7BFE0171AC010DC
+:10E3900017FCBFE03AC885183A88071017FEBFE09F
+:10E3A0000E05801817F7BFE0171AC01017FCBFE062
+:10E3B0003AC8851815FEBFE017FFBFE01702C0106E
+:10E3C00017FABFE03AC885183A88071017FEBFE071
+:10E3D0000E05801817FFBFE01702C01017FABFE044
+:10E3E0003AC8851815FEBFE017FFBFE01703C0103D
+:10E3F00017FABFE03A88851817FEFFE03A880D1833
+:10E400003A880B1017F53FE1806B088017FEBFE0DC
+:10E4100017F5FFE03A88851815F5BFE017F4BFE05F
+:10E420001700C01017FEBFE03AC8871817F4BFE006
+:10E430001500C01017FFBFE01702C01017FABFE0A9
+:10E440003AC885183A88071017FEBFE01E20C01092
+:10E45000170280E08C0080102605001017FFBFE037
+:10E460001706801015FFBFE015FA3FE006320000E6
+:10E4700017FFBFE01707801015FBBFE017F7BFE0DD
+:10E48000170AC01017FFBFE0170280103AC887189C
+:10E4900017F7BFE0150AC01017FF3FE180BF2980C2
+:10E4A0003A88071017F7BFE01510C01017F7BFE044
+:10E4B0001710801015FFBFE017FFBFE0261E0010E9
+:10E4C00017FFBFE017FBFFE01507C010061A00009A
+:10E4D000170280E08C0080102605001017FAFFE07C
+:10E4E00017FEBFE03A88851815FABFE00612000053
+:10E4F00017FFBFE01703C01017FEBFE03A88871868
+:10E5000017FFBFE01503C01017FFBFE01702C010D0
+:10E5100017FEBFE03AC8871817FFBFE01502C0100A
+:10E5200017F7BFE0170AC01017FEBFE03AC88718F8
+:10E5300017F7BFE0150AC01017F7BFE0171A8010D1
+:10E5400026170010170280E08C0080101E100010AB
+:10E5500017F7BFE0171AC01017FEBFE03AC88718B8
+:10E5600017F7BFE0151AC01017F7BFE0171A801091
+:10E570001E0B001017F7BFE08B08801014108010DE
+:10E580003A88071017F7BFE08D08C010060B00008F
+:10E5900017FCFFE017FEBFE03A88851815FCBFE0C6
+:10E5A00017FFBFE02605001017F4BFE0170080102A
+:10E5B0000E02800017FDBFE0265B3F10170280E0CF
+:10E5C0008C0080101E25001017FFBFE01E040010F5
+:10E5D00017F7BFE017FBFFE01510C0100609000099
+:10E5E00017F9BFE00B018010CCFFBF104C0080106A
+:10E5F0002604001017F7BFE0040A80103A880910BB
+:10E600008036308017F9BFE00B018010CCFFBF10BF
+:10E610000C0280102611001017F7BFE017018010C0
+:10E62000260E001017F7BFE00402C0001507C01047
+:10E6300017F9BFE0170380103A880D003A880B00E5
+:10E6400017F73FE13AE83E10060500003A8801005E
+:10E65000060300003A880100060100003A88010024
+:10E6600017F7BFE00B11C01084FFBF003A70841889
+:10E670003A88071017F7BFE00D11C01017F7BFE079
+:10E68000041180103A88091000BA278017FDBFE0F6
+:10E690003A8837E01701C0DF170000DF0402C0DE50
+:10E6A0003A2800F804FCFFDE1503C0DF150200DF86
+:10E6B000040200DF15FF3FE115FE7FE117FEBFE01A
+:10E6C0004400801015FEBFE017FEBFE04C00801034
+:10E6D0002602001017FF3FE140682E8017FEBFE0C2
+:10E6E0008C008010260F001017FFBFE0041280106E
+:10E6F0003A880910C002308017FFBFE0C401C00093
+:10E700001507C01017FFBFE0170280101703801015
+:10E710003A880D003A880B0017FF3FE13AE83E10B7
+:10E72000060100003A8805003A8837E01701C0DF8B
+:10E73000170000DF0402C0DE3A2800F804FBFFDE09
+:10E740001504C0DF150300DF040300DF15FD3FE102
+:10E7500017FDBFE0040A801015FFBFE006040000AB
+:10E7600017FFBFE0040780103A88091040A52780F2
+:10E7700017FFBFE00B078010CCFFBF104C008010CC
+:10E780001EF73F1017FFBFE00B07801054008010EA
+:10E790003A88071017FFBFE00D07C01017FD3FE1D3
+:10E7A000C0842F8017FFBFE00B07C01084FFBF009D
+:10E7B0003A7084183A88071017FFBFE00D07C010A1
+:10E7C00017FFBFE0040780103A88091000BA2780BD
+:10E7D00017FF3FE100AB2F80040880013A880B004F
+:10E7E00017FF3FE1408E088017FDBFE0170680103D
+:10E7F00015FEBFE017FDBFE0841BC0001506C0106A
+:10E8000017FDBFE0040A80103A880B1017FD3FE1A6
+:10E81000C0942F8017FDBFE017FEFFE01506C01063
+:10E820003A8801003A8837E01701C0DF170000DF9F
+:10E830000402C0DE3A2800F804F6FFDE1509C0DF46
+:10E84000150800DF040800DF15FA3FE115F97FE144
+:10E8500015F8BFE115FF3FE017F9BFE020808010F9
+:10E860001E52001017F9BFE0488080101E210010D2
+:10E8700017F9BFE0880380101E0D001017F9BFE0E4
+:10E88000480280101E97001017F9BFE02001801089
+:10E890001E46001017F9BFE0200280101E43001032
+:10E8A00017F9BFE0A00080101E94001006FB0000C6
+:10E8B00017F9BFE0200880101E3C001017F9BFE0D8
+:10E8C000480880101E04001017F9BFE020048010D3
+:10E8D0001E36001006F1000017F9BFE0202080105E
+:10E8E0001E2D001017F9BFE0204080101E2F0010D1
+:10E8F00006EA000017F9BFE0200584101E5300103F
+:10E9000017F9BFE0480584101E0F001017F9BFE08B
+:10E91000A00184101E48001017F9BFE0C801841040
+:10E920001E05001017F9BFE0C4FFBB10A80080103F
+:10E930001EDA0010062F000017F9BFE02004841033
+:10E940001EAF001006D5000017F9BFE0E0008810E8
+:10E950001EAB001017F9BFE0080188101E07001059
+:10E9600017F9BFE0600584101E3F001017F9BFE0E3
+:10E97000A00584101E44001006C8000017F9BFE06F
+:10E98000200188101E72001017F9BFE020009010BF
+:10E990001E06001006C1000017F8BFE01701801026
+:10E9A0003A88071017FABFE00D08C01017F8BFE04B
+:10E9B000170080102607001017FABFE01704C010D8
+:10E9C00017F9BFE03AB0861817FABFE01504C01077
+:10E9D00006B6000017FABFE01704801017F9FFE031
+:10E9E0003A30C6003A70C61017FABFE01504C010DE
+:10E9F00006AE000017F9BFE0580084101E03001097
+:10EA000017FABFE0041280100602000017FABFE0F8
+:10EA1000040A801017F8FFE01700C0183A880B1896
+:10EA20003A88091000A62F801E9F0010441A80000B
+:10EA300015FFBFE0069D000017F8BFE00B00C010F7
+:10EA400017FABFE08D11C0100698000017FABFE05A
+:10EA50008B088010144080103A88071017FABFE026
+:10EA60008D08C0100691000017FABFE08B08C01097
+:10EA7000C4BFBF003A7084183A88071017FABFE085
+:10EA80008D08C0100689000017F8BFE01E030010B3
+:10EA900084FDBF0015FFBFE00684000017F8BFE04B
+:10EAA000170080102607001017FABFE08B088010AF
+:10EAB000144080103A88071017FABFE08D08C01084
+:10EAC000067A000017FABFE08B08C010C4BFBF0071
+:10EAD0003A7084183A88071017FABFE08D08C01002
+:10EAE0000672000017F8BFE117FA7FE117F93FE15E
+:10EAF000407C3E8015FFBFE0066C000017F8BFE0C9
+:10EB00001E03001084FDBF0015FFBFE00667000074
+:10EB100017F8BFE0170080102606001017FABFE0B4
+:10EB2000170480101400C81017FABFE01504C010B5
+:10EB3000065E000017FABFE01704C010C4FFB7005C
+:10EB40003A70861817FABFE01504C0100657000087
+:10EB500017FABFE083098010CC3F80101C20801082
+:10EB600004E0BF10600080101E03001084058000C8
+:10EB700015FFBFE0064D000017FABFE01701801037
+:10EB800015FEBFE017FEBFE01709801015FDBFE0BE
+:10EB900017FDBFE01E0300100420800015FFBFE03A
+:10EBA0000642000017F8BFE01E03001084FDBF00FE
+:10EBB00015FFBFE0063D000017F8BFE0170080100A
+:10EBC0002607001017FDBFE00B0B8010140180100A
+:10EBD0003A88071017FDBFE00D0BC0100633000088
+:10EBE00017FDBFE00B0BC010C4FEBF003A708418C5
+:10EBF0003A88071017FDBFE00D0BC010062B000070
+:10EC000017FABFE083098010CC3F80101C208010D1
+:10EC100004E0BF10600080101E0300108405800017
+:10EC200015FFBFE00621000017FABFE017018010B2
+:10EC300015FCBFE017FCBFE01709801015FBBFE013
+:10EC400017FBBFE01E0300100420800015FFBFE08B
+:10EC50000616000017FBBFE0170280102603001005
+:10EC60008405800015FFBFE00610000017F8BFE024
+:10EC7000170080103A88071017FBBFE00D0AC0107C
+:10EC800017FBBFE00B0B8010140081103A880710AF
+:10EC900017FBBFE00D0BC01006040000441B8000F2
+:10ECA00015FFBFE0060100003A88010017FFBFE032
+:10ECB0003A8837E01701C0DF170000DF0402C0DE2A
+:10ECC0003A2800F804F5FFDE150AC0DF150900DF59
+:10ECD000040900DF15F93FE115F87FE115F7BFE101
+:10ECE00015FF3FE017F7BFE01E02001084FDBF00D4
+:10ECF0000637010017F8BFE0E00084101E8E0010F8
+:10ED000017F8BFE0080184101E2E001017F8BFE0AE
+:10ED1000200480101E80001017F8BFE04804801007
+:10ED20001E11001017F8BFE0200280101E7A00109C
+:10ED300017F8BFE0480280101E07001017F8BFE068
+:10ED4000A00080101EEE001017F8BFE02001801018
+:10ED50001E710010061B010017F8BFE008038010A9
+:10ED60001E18011006E0000017F8BFE020408010D8
+:10ED70001E69001017F8BFE0484080101E07001001
+:10ED800017F8BFE0200880101E63001017F8BFE0DE
+:10ED9000202080101E510010060A010017F8BFE065
+:10EDA000600084101E70001017F8BFE08800841007
+:10EDB0001E73001017F8BFE0208080101E56001050
+:10EDC0000600010017F8BFE0200484101E8D00101B
+:10EDD00017F8BFE0480484101E17001017F8BFE0B2
+:10EDE000A00184101EA7001017F8BFE0C80184100E
+:10EDF0001E07001017F8BFE0200184101E540010F9
+:10EE000017F8BFE0600184101E99001006ED0000A5
+:10EE100017F8BFE0200284101E6B001017F8BFE047
+:10EE2000100284101E70001017F8BFE060028410FA
+:10EE30001E99001006E3000017F8BFE0E0048410FC
+:10EE40001E14001017F8BFE0080584101E070010FC
+:10EE500017F8BFE0600484101E4F001017F8BFE0E1
+:10EE6000A00484101E52001006D6000017F8BFE060
+:10EE7000E00088101E63001017F8BFE02001881022
+:10EE80001EAA001017F8BFE0A00584101E8A00100B
+:10EE900006CC000017F9BFE08B088010CCFFBF1034
+:10EEA0008C0080102607001017F9BFE017018010B2
+:10EEB000170A8010170AC01017F7BFE01500C0101E
+:10EEC00006C20000B40182001770B710170AC01004
+:10EED00017F7BFE01500C01006BC000017F7BFE031
+:10EEE00015FEBFE017F9BFE0170480100C20C0101A
+:10EEF00017FEBFE01500C01017F9BFE00B08801027
+:10EF0000CCFFFF101C00E0180400E01817FEBFE063
+:10EF10001501C01006AD000017F9BFE01704C010BE
+:10EF200017F8BFE03A7084183A88071017F7BFE067
+:10EF30001500C01006A5000017F9BFE017168010D5
+:10EF40003A88071017F7BFE01500C010069F0000B1
+:10EF500017F9BFE0170E80103A88071017F7BFE0C7
+:10EF60001500C0100699000017F9BFE017138010B4
+:10EF70003A88071017F7BFE01500C010069300008D
+:10EF800017F9BFE0170B80103A88071017F7BFE09A
+:10EF90001500C010068D000017F9BFE0170A801099
+:10EFA0003A88071017F7BFE01500C0100687000069
+:10EFB00017F9BFE0171280103A88071017F7BFE063
+:10EFC0001500C0100681000017F9BFE0830980100A
+:10EFD000CC3FC0101C20C01804E0FF1817F7BFE09A
+:10EFE0001500C0100679000017F9BFE01706C01021
+:10EFF00017F7BFE01500C01017F9BFE015060010A5
+:10F000000672000017F9BFE083098010CC3F801022
+:10F010001C20801004E0BF10600080101E03001050
+:10F020008405800015FFBFE00668000017F9BFE007
+:10F030001701801015FDBFE017FDBFE01709801014
+:10F0400015FCBFE017FCBFE01E0300100420800089
+:10F0500015FFBFE0065D000017FCBFE00B0A801043
+:10F06000CCFFFF1017F7BFE01500C01006570000D7
+:10F0700017F9BFE08B19C01017F7BFE00D00C010E3
+:10F080000652000017F9BFE08B11C01017F7BFE060
+:10F090000D00C010064D000017F9BFE0C309801035
+:10F0A000CC3FC0101C20C01804E0FF1817F7BFE0C9
+:10F0B0001500C0100645000017F9BFE08B0880104E
+:10F0C000CCFFBF100C4080102604001017F7BFE0E3
+:10F0D0004400C0001500C010063C000017F7BFE058
+:10F0E000150000100639000017F7BFE117F97FE19E
+:10F0F00017F83FE140D63E8015FFBFE00633000021
+:10F1000017F9BFE0170480100C00881026040010C7
+:10F1100017F7BFE04400C0001500C010062B000028
+:10F1200017F7BFE0150000100628000017F9BFE030
+:10F1300083098010CC3F80101C20801004E0BF1099
+:10F14000600080101E0300108405800015FFBFE0E2
+:10F15000061E000017F9BFE01701801015FBBFE085
+:10F1600017FBBFE01709801015FABFE017FABFE0E0
+:10F170001E0300100420800015FFBFE006130000EE
+:10F1800017F7BFE01E03001084FDBF0015FFBFE0AE
+:10F19000060E000017FABFE00B0B8010CCFFBF106B
+:10F1A0000C0180102604001017F7BFE04400C000D7
+:10F1B0001500C0100605000017F7BFE0150000108D
+:10F1C00006020000441B80000601000017FFBFE09C
+:10F1D0003A8837E01701C0DF170000DF0402C0DE05
+:10F1E0003A2800F804FDFFDE1502C0DF150100DF3C
+:10F1F000040100DF15FF3FE117FFBFE04436C00008
+:10F200001506C01017FFBFE0040A80103A880B10E3
+:10F2100017FF3FE1C0942F803A8801003A8837E019
+:10F220001701C0DF170000DF0402C0DE3A2800F833
+:10F2300004FDFFDE1502C0DF150100DF040100DF61
+:10F2400015FF3FE117FFBFE08B08C01044FDBF0072
+:10F250003A7084183A88071017FFBFE08D08C01075
+:10F2600017FFBFE08B088010140180103A88071048
+:10F2700017FFBFE08D08C01017FFBFE00409801022
+:10F280003A88091000BA27803A8801003A8837E0A6
+:10F290001701C0DF170000DF0402C0DE3A2800F8C3
+:10F2A00004FCFFDE1503C0DF150200DF040200DFEF
+:10F2B00015FE3FE117FEBFE0171B801015FFBFE0F2
+:10F2C00017FFBFE0261400103A880B0017FE3FE13D
+:10F2D000C06E2F801E03001074010201048A2A21CF
+:10F2E000801727804400800117FE7FE117FF3FE170
+:10F2F00000642F8017FFBFE0040A80103A880B10CB
+:10F3000017FF3FE1C0942F8017FFBFE00409801072
+:10F310003A88091000BA278017FEBFE08B08C0109A
+:10F32000C4FCBF003A7084183A88071017FEBFE08B
+:10F330008D08C01017FEBFE08B088010940080106D
+:10F340003A88071017FEBFE08D08C01017FEBFE017
+:10F350001506001017FEBFE0040980103A88091056
+:10F3600000BA278017FEBFE0040A80103A880B100D
+:10F3700017FE3FE1C0942F8017FEBFE004128010FB
+:10F380003A880B1017FE3FE1C0942F803A880100A5
+:10F390003A8837E01701C0DF170000DF0402C0DE43
+:10F3A0003A2800F804FDFFDE1502C0DF150100DF7A
+:10F3B000040100DF15FF3FE117FFBFE08B08C0101D
+:10F3C000C4FEBF003A7084183A88071017FFBFE0E8
+:10F3D0008D08C01017FFBFE08B088010140E80103E
+:10F3E0003A88071017FFBFE08D08C01017FFBFE075
+:10F3F000040980103A88091000BA278017FFBFE07F
+:10F40000041280103A880B1017FF3FE1C0942F8040
+:10F4100017FFBFE0040A80103A880B1017FF3FE186
+:10F42000C0942F803A8801003A8837E01701C0DF86
+:10F43000170000DF0402C0DE3A2800F804FDFFDEFA
+:10F440001502C0DF150100DF040100DF15FF3FE1F9
+:10F4500017FFBFE08B088010CCFFBF100C0180109D
+:10F460002606001017FFBFE08B08801014008810DC
+:10F470003A88071017FFBFE08D08C01017FFBFE0E4
+:10F480008B08C01044FCBF003A7084183A880710FB
+:10F4900017FFBFE08D08C01017FFBFE08B0880107A
+:10F4A000140C80103A88071017FFBFE08D08C010B9
+:10F4B00017FFBFE0040980103A88091000BA2780BE
+:10F4C00017FFBFE0041280103A880B1017FF3FE1CE
+:10F4D000C0942F8017FFBFE0040A80103A880B10F9
+:10F4E00017FF3FE1C0942F803A8801003A8837E047
+:10F4F0001701C0DF170000DF0402C0DE3A2800F861
+:10F5000004FBFFDE1504C0DF150300DF040300DF8A
+:10F5100015FD3FE117FDBFE0431E8010CC3FC0103A
+:10F520001C20C01804E0FF1817FDBFE0031E801068
+:10F53000CC3F80101C20801004E0BF103A88871850
+:10F5400017FDBFE0831E8010CC3F80101C20801070
+:10F5500004E0BF10E4008010FAD708103A88852034
+:10F560007AD00510165BC01004210001C0822980EA
+:10F5700015FFBFE017FFBFE02658001017FFBFE0E0
+:10F580001500001017FF7FE1B4010201047138215A
+:10F590000099288017FDBFE08309C01017FFBFE066
+:10F5A0008509C01017FDBFE01704C01044FFBF005D
+:10F5B0003A70861817FFBFE01504C01017FDBFE0B2
+:10F5C0000B08C01017FFBFE00D08C01017FDBFE00B
+:10F5D0008B088010540080103A88071017FFBFE096
+:10F5E0008D08C01017FDBFE01702C01017FFBFE065
+:10F5F0001502C01017FDBFE00B09C01017FFBFE0D8
+:10F600000D09C0101721E0D017FFBFE0150BC01087
+:10F610001720E0D017FFBFE01513C0103A880D0087
+:10F6200017FF7FE117FD3FE100642F8017FFBFE068
+:10F630001507001017FDBFE01705C01017FFBFE04A
+:10F640001505C01017FFBFE01702801017038010C8
+:10F650003A880D003A880B0017FF3FE13AE83E1068
+:10F660001E0F0010039AA0D0CC3F8010260A001075
+:10F670001798A0D017FF3FE13AE83E1015FEBFE013
+:10F6800017FEBFE01E08001017FDBFE00320C010EA
+:10F6900017FFBFE00520C01017FFBFE006110000F4
+:10F6A0003A880100060100003A8801003A880B0000
+:10F6B00017FF3FE1C06E2F8017FF7FE1B401020109
+:10F6C0000471382100A4288017FF3FE100862980BB
+:10F6D000060300003A880100060100003A88010094
+:10F6E0003A8805003A8837E01701C0DF170000DFCD
+:10F6F0000402C0DE3A2800F804FCFFDE150300DF38
+:10F70000040300DF15FF3FE115FE7FE115FDBFE1BA
+:10F7100017FEBFE017FFFFE0151BC01017FDBFE08D
+:10F720001E0E001017FFBFE0031E80104400801063
+:10F730003A88071017FFBFE0051EC01017FFBFE093
+:10F74000171CC01017FEBFE0151CC01017FFBFE04C
+:10F7500017FEFFE0151CC010060D000017FFBFE0EC
+:10F76000431E8010440080103A88071017FFBFE046
+:10F77000451EC01017FFBFE0171DC01017FEBFE0E9
+:10F78000151DC01017FFBFE017FEFFE0151DC010CC
+:10F790003A8801003A8837E0170000DF0401C0DE34
+:10F7A0003A2800F804FAFFDE150500DF040500DF43
+:10F7B00015FC3FE115FB7FE117FCBFE0171B801034
+:10F7C00015FEBFE017FEBFE015FFBFE017FBBFE06F
+:10F7D0002603001017FFBFE0171D8010060200006F
+:10F7E00017FFBFE0171C801015FDBFE017FDFFE0FD
+:10F7F00017FCBFE02608801817FDFFE017FEBFE0EA
+:10F800001E0280183A8805000624000017FDBFE09C
+:10F8100015FFBFE006ED3F003A88010017FBBFE08F
+:10F820001E0B001017FDBFE0171CC01017FFBFE034
+:10F83000151CC01017FEBFE0031E8010C4FFBF10D0
+:10F840003A88071017FEBFE0051EC010060A000028
+:10F8500017FDBFE0171DC01017FFBFE0151DC0103A
+:10F8600017FEBFE0431E8010C4FFBF103A88071088
+:10F8700017FEBFE0451EC01017FDBFE0151D0010AC
+:10F8800017FDBFE0171DC01017FDBFE0151CC0100D
+:10F8900017FDBFE0151B0010440080003A8837E0D8
+:10F8A000170000DF0401C0DE3A2800F804FDFFDE87
+:10F8B0001502C0DF150100DF040100DF15FF3FE185
+:10F8C00017FFBFE08B088010140480103A880710DF
+:10F8D00017FFBFE08D08C01017FFBFE004128010B3
+:10F8E0003A880B1017FF3FE1C0942F803A8801003F
+:10F8F0003A8837E01701C0DF170000DF0402C0DEDE
+:10F900003A2800F804FDFFDE1502C0DF150100DF14
+:10F91000040100DF15FF3FE117FFBFE08B088010F7
+:10F92000140880103A88071017FFBFE08D08C01038
+:10F9300017FFBFE0040A80103A880B1017FF3FE161
+:10F94000C0942F803A8801003A8837E01701C0DF61
+:10F95000170000DF0402C0DE3A2800F804FEFFDED4
+:10F96000150100DF040100DF15FF3FE117FFBFE0D5
+:10F970000B078010140280103A88071017FFBFE0B1
+:10F980000D07C0103A8801003A8837E0170000DF01
+:10F990000401C0DE3A2800F804FDFFDE1502C0DFD6
+:10F9A000150100DF040100DF15FF3FE117FFBFE095
+:10F9B0000B078010140180103A88071017FFBFE072
+:10F9C0000D07C01017FFBFE03A88091040A5278037
+:10F9D00017FFBFE00B07C010C4FEBF003A708418C9
+:10F9E0003A88071017FFBFE00D07C0103A880100E2
+:10F9F0003A8837E01701C0DF170000DF0402C0DEDD
+:10FA00003A2800F804FCFFDE1503C0DF150200DF12
+:10FA1000040200DF15FF3FE115FE7FE117FEBFE0A6
+:10FA20000B078010CCFFBF100C028010260A0010BC
+:10FA30000D8520D0048520D100BA278017FEBFE0B5
+:10FA40000B07C010C4FDBF003A7084183A88071035
+:10FA500017FEBFE00D07C01017FEBFE00B078010B8
+:10FA6000CCFFBF100C0180102603001017FEBFE072
+:10FA70003A88091000BA27803A8801003A8837E0AE
+:10FA80001701C0DF170000DF0402C0DE3A2800F8CB
+:10FA900004FBFFDE1504C0DF150300DF040300DFF5
+:10FAA00015FF3FE115FE7FE115FDBFE117FFBFE048
+:10FAB0000412801017FE7FE13A88091000A62F80FB
+:10FAC000260E001017FFBFE0040A801017FD7FE12B
+:10FAD0003A88091000A62F80260200103A880500F7
+:10FAE000060800003A88010017FFBFE004128010EA
+:10FAF0003A88091000AB2F80060100003A88010007
+:10FB0000441A80003A8837E01701C0DF170000DF91
+:10FB10000402C0DE3A2800F804FDFFDE150200DF13
+:10FB2000040200DF15FF3FE115FE7FE117FFBFE094
+:10FB300017FEFFE01501C01017FEBFE03A888510E0
+:10FB40007000D0101E0100180400900017FFFFE0A5
+:10FB500015038018440080003A8837E0170000DF62
+:10FB60000401C0DE3A2800F804FDFFDE1502C0DF04
+:10FB7000150100DF040100DF15FF3FE117FF3FE142
+:10FB8000C002308017FFBFE01503001017FFBFE071
+:10FB90001703C01017FFBFE01501C0103A8801001D
+:10FBA0003A8837E01701C0DF170000DF0402C0DE2B
+:10FBB0003A2800F804FBFFDE1504C0DF150300DF60
+:10FBC000040300DF15FE3FE115FD7FE117FDBFE0F7
+:10FBD000261A001040E9288017FEBFE017068010A3
+:10FBE00015FFBFE017FFBFE0260E00100603000060
+:10FBF00017FFBFE01707801015FFBFE017FFBFE03A
+:10FC0000170780101EFA3F100603000017FFBFE021
+:10FC10001706801015FFBFE017FFBFE01706801022
+:10FC20001EFA3F1017FFBFE117FD7FE117FE3FE10E
+:10FC300000E52F8040EF2880060100003A8801008F
+:10FC40003A8837E01701C0DF170000DF0402C0DE8A
+:10FC50003A2800F804FBFFDE1504C0DF150300DFBF
+:10FC6000040300DF15FE3FE115FD7FE117FDBFE056
+:10FC70002628001040E9288017FEBFE017068010F4
+:10FC800015FFBFE017FFBFE02607001006030000C6
+:10FC900017FFBFE01707801015FFBFE017FFBFE099
+:10FCA000170780101EFA3F1017FEBFE01700C010A4
+:10FCB00017FDBFE0170280103A88871817FEBFE0D3
+:10FCC0001500C01017FFBFE02604001017FFBFE0AB
+:10FCD00017FDFFE01507C0100603000017FEBFE088
+:10FCE00017FDFFE01506C01017FDBFE017068010D6
+:10FCF00015FFBFE017FDBFE01506001017FDBFE1BF
+:10FD000017FF7FE117FE3FE100E52F8040EF2880DD
+:10FD1000060100003A8801003A8837E01701C0DF89
+:10FD2000170000DF0402C0DE3A2800F804F8FFDE06
+:10FD30001507C0DF150600DF040600DF15FC3FE1F4
+:10FD400015FB7FE115FABFE10404800015FDBFE05B
+:10FD500040E9288017FABFE015FFBFE00608000061
+:10FD600017FFBFE01702C01017FDBFE03A888518E3
+:10FD700015FDBFE017FFBFE01706801015FFBFE0BD
+:10FD800017FFBFE01EF63F1017FCBFE01701801001
+:10FD90003A88071017FCBFE0170080103AC8851892
+:10FDA0001607001017FCBFE01701C01017FCBFE0DA
+:10FDB000170080103AC885183A880710060100001D
+:10FDC0003A88070017FDBFE00E03801840EF288037
+:10FDD0003A8805000647000004044001440200017F
+:10FDE00000A7298015FFBFE017FFBFE01E0300102A
+:10FDF00040EF28803A880500063E000017FFBFE06C
+:10FE00001703801017FBFFE00B0000190D00001115
+:10FE10008B0000198D0000110B0100190D0100115C
+:10FE20008B0100198D0100110B0200190D02001148
+:10FE30008B0200198D0200110B0300190D03001134
+:10FE40008B03C0188D03C01017FFBFE00404C0006F
+:10FE50001502C01017FCBFE01700C01017FFBFE06D
+:10FE6000170280103A88871817FCBFE01500C010F1
+:10FE700017FCBFE01706801015FEBFE017FEBFE0BD
+:10FE8000260B00100603000017FEBFE017078010C6
+:10FE900015FEBFE017FEBFE0170780101EFA3F10E7
+:10FEA00017FEBFE017FFFFE01507C01006030000B4
+:10FEB00017FCBFE017FFFFE01506C01017FFBFE0FB
+:10FEC000170680102603001017FFBFE017068010EA
+:10FED00015FFBFE017FABFE02604001017FFBFE1CF
+:10FEE00017FA7FE117FC3FE100E52F8040EF288003
+:10FEF000440080003A8837E01701C0DF170000DFB8
+:10FF00000402C0DE3A2800F804FBFFDE1504C0DF5F
+:10FF1000150300DF040300DF15FF3FE115FE7FE15D
+:10FF200015FDBFE10667000017FEBFE01702801055
+:10FF30001E04001017FE3FE180BF298015FEBFE0C0
+:10FF40000660000017FEBFE01708801060008010F8
+:10FF50001E11001017FEBFE017088010A0008010CF
+:10FF60001E0D001017FEBFE0170880106002801001
+:10FF70001E09001017FEBFE0170880103A880B100A
+:10FF800074010201048E2A2180C7028074010201DB
+:10FF900004932A218017278017FDBFE02632001026
+:10FFA00017FFBFE00B078010CCFFBF100C208010A4
+:10FFB000262D001017FDBFE01702C01017FEBFE08E
+:10FFC000170280103A88871817FDBFE017058010C8
+:10FFD00017FD3FE11703402117FD3FE11704002102
+:10FFE0003AC809293AC805112E1F801817FDBFE02D
+:10FFF0001703C01017FDBFE0170280103A8887185A
+:020000023000CC
+:1000000017FEBFE01703001117FEBFE017028010B4
+:100010003A880D103A880B203A880918806B0880BE
+:1000200017FFBFE01700C01017FEBFE017028010D7
+:100030003A88871817FFBFE01500C01017FDBFE012
+:100040001702C01017FEBFE0170280103A88871809
+:1000500017FDBFE01502C01017FE3FE180BF2980E9
+:1000600015FEBFE00617000017FFBFE01700C01025
+:1000700017FEBFE0170280103A88871817FFBFE00D
+:100080001500C01017FDBFE02604001017FDBFE0EB
+:1000900017FEFFE01506C0100603000017FFBFE0C3
+:1000A00017FEFFE01506C01017FEBFE015FDBFE00C
+:1000B00017FEBFE01706801015FEBFE017FDBFE07A
+:1000C0001506001017FEBFE01E973F103A8801008A
+:1000D0003A8837E01701C0DF170000DF0402C0DEF6
+:1000E0003A2800F804FDFFDE1502C0DF150100DF2D
+:1000F000040100DF15FF3FE140E9288017FFBFE062
+:100100000B078010CCFFBF104C0080102609001098
+:100110007401020104962A21801727800605000039
+:1001200017FFBFE0170080103A880B1017FF3FE160
+:10013000000B308017FFBFE0170280101EF83F1041
+:1001400017FFBFE0170080101EF53F1040EF28801A
+:100150003A8801003A8837E01701C0DF170000DF56
+:100160000402C0DE3A2800F804F9FFDE1506C0DFFD
+:10017000150500DF040500DF15FC3FE115FB7FE1FD
+:1001800040E9288017FCBFE01706801015FFBFE08C
+:1001900017FFBFE02604001017FFBFE0170780100D
+:1001A00015FEBFE00637000015FE3FE006350000F3
+:1001B00017FFBFE01E0B001017FEBFE01E0300106C
+:1001C0007401020104982A218017278017FEBFE0DE
+:1001D00015FFBFE017FFBFE01707801015FEBFE057
+:1001E0000628000017FFBFE01702801017FBFFE092
+:1001F0002E13801817FFBFE01702C01017FBBFE0D7
+:100200003AC8871817FFBFE01502C01017FFBFE0FC
+:100210001703C01017FBBFE03A88871817FFBFE02D
+:100220001503C01017FCBFE01700C01017FBBFE09C
+:100230003AC8871817FCBFE01500C010061300006D
+:1002400017FBFFE017FFBFE0170280103AC88518C0
+:1002500015FBBFE017FCBFE01700C01017FFBFE0A1
+:10026000170280103AC8871817FCBFE01500C010AD
+:1002700017FF3FE180BF298015FDBFE017FDBFE0FC
+:1002800015FFBFE017FBBFE016C9BF00060C00005A
+:1002900017FCBFE01700C01017FFBFE01702801067
+:1002A0003AC8871817FCBFE01500C01017FF3FE1E0
+:1002B00080BF298015FDBFE017FDBFE015FFBFE03F
+:1002C00017FFBFE02603001017FFBFE017028010E2
+:1002D00026EF3F1017FFBFE02607001017FCBFE016
+:1002E00017FFFFE01506C01017FFBFE017FEFFE085
+:1002F0001507C0100603000017FCBFE017FEFFE063
+:100300001506C01040EF28803A8801003A8837E08F
+:100310001701C0DF170000DF0402C0DE3A2800F832
+:1003200004F9FFDE1506C0DF150500DF040500DF58
+:1003300015FC3FE115FB7FE140E9288017FB3FE119
+:10034000801D2A8015FDBFE017FDBFE00E0780006D
+:1003500017FCBFE01706C01017FDBFE03AC88500C4
+:100360003A880B103A88091880012A8017FCBFE0F0
+:100370001706801015FFBFE015FE3FE017FCBFE039
+:1003800017068010170280101E08001017FCBFE02F
+:10039000150600100605000017FFBFE015FEBFE0C0
+:1003A00017FFBFE01706801015FFBFE017FFBFE083
+:1003B0002603001017FFBFE0170280101EF63F1043
+:1003C00017FFBFE02609001017FFBFE017028010DB
+:1003D0001E06001017FEBFE02602001017FEBFE049
+:1003E0001506001017FF3FE1C0CF298017FCBFE0C2
+:1003F0001700C01017FDBFE03AC8871817FCBFE010
+:100400001500C01040EF28803A8801003A8837E094
+:100410001701C0DF170000DF0402C0DE3A2800F831
+:1004200004FBFFDE1504C0DF150300DF040300DF5B
+:1004300015FD3FE140E9288017FDBFE01706801059
+:1004400015FFBFE017FFBFE02612001017FFBFE047
+:100450001707C01017FDBFE01506C01017FDBFE05D
+:100460001700C01017FFBFE0170280103AC88718A6
+:1004700017FDBFE01500C01017FF3FE180BF2980C6
+:1004800015FEBFE017FEBFE015FFBFE017FFBFE09E
+:100490001EF23F1040EF28803A8801003A8837E08A
+:1004A0001701C0DF170000DF0402C0DE3A2800F8A1
+:1004B0000472FEDE158DC1DF158C01DF048C01DFB7
+:1004C00015773EE115767EE11575BEE11574FEE106
+:1004D00015FF3FE0043BBFE004C380013A880B00F6
+:1004E0003A880910408E08800478BEE004C3800179
+:1004F0003A880B003A880910408E08801777BEE0D2
+:10050000260500100478BEE00441800117777EE1E3
+:100510003A880910806B08801776BEE02606001026
+:100520000478BEE0044180100441800117767EE12A
+:100530003A880910806B08801775BEE02606001007
+:100540000478BEE0048280100441800117757EE1CA
+:100550003A880910806B0880177DE0D01774BEE0E0
+:100560003A88851815FEBFE01778BEE01E0C001013
+:1005700017B9BEE01E0A001017FABEE01E080010F0
+:100580001774BEE00E1F80001774BEE04400801098
+:10059000CCFFBF103A880910C03017800619000040
+:1005A0003A88090080F32880060A00001774BEE02C
+:1005B000E0FFBF101E030010177DE0D017FEBFE064
+:1005C0002E0D8018440080000D85A0D0048520D118
+:1005D00040A52780043BFFE00478BEE03A880B1872
+:1005E0003A880910805C308015FFBFE017FFBFE03C
+:1005F00026EE3F10060100003A8801003A88090003
+:1006000040FF288017FFBFE0161700101777BEE0E5
+:1006100026050010043BBFE0044180013A880B101E
+:1006200017773EE1806B08801776BEE02606001043
+:10063000043BBFE004418010044180013A880B1064
+:1006400017763EE1806B08801775BEE02606001025
+:10065000043BBFE004828010044180013A880B1003
+:1006600017753EE1806B088017FFBFE03A8837E0DE
+:100670001701C0DF170000DF0402C0DE3A2800F8CF
+:1006800004F6FFDE1509C0DF150800DF040800DFEF
+:1006900015F93FE115F87FE115FD3FE015FC3FE05E
+:1006A00015FF3FE0063D000017FFBFE0600080102F
+:1006B0001E08001017FFBFE0A00080101E080010E9
+:1006C00017FFBFE01E0800104400800015FDBFE0CA
+:1006D000060500008400800015FDBFE00602000052
+:1006E00015FD3FE03A88010017FFBFE0244180106C
+:1006F00017F9FFE03A88851815FBBFE017FFBFE048
+:100700002441801017F8FFE03A88851815FABFE0F9
+:1007100015FE3FE00619000017FBFFE017FEBFE0E3
+:1007200044008010BA9004103A8885181700801091
+:1007300017FD7FE13A88091080703080260C001088
+:1007400017FBFFE017FEBFE044008010BA900410D2
+:100750003A8885181700801017FA7FE13A88091047
+:1007600080B1308017FCBFE04400801015FCBFE072
+:1007700017FEBFE04400801015FEBFE017FBBFE08E
+:10078000170080103A88071017FEBFE016E2FF102E
+:1007900017FFBFE04400801015FFBFE017FFBFE068
+:1007A000D00080101EC03F1017FCBFE03A8837E031
+:1007B0001701C0DF170000DF0402C0DE3A2800F88E
+:1007C00004FAFFDE1505C0DF150400DF040400DFB6
+:1007D00015FD3FE115FC7FE115FF3FE017FDBFE090
+:1007E00004FCBF10BA90041015FEBFE017FCBFE078
+:1007F000600080101E06001017FCBFE0A0008010F3
+:100800001E21001017FCBFE0264300100660000008
+:1008100017FEBFE0170A8010260300104400800076
+:1008200015FFBFE0065A000017FEBFE08B088010DE
+:10083000CCFFBF100C08801026030010440080007D
+:1008400015FFBFE00652000017FEBFE0431E8010F8
+:10085000CC3F80101C20801004E0BF102603001045
+:100860004400800015FFBFE00649000017FEBFE00E
+:100870000B118010140280103A88071017FEBFE099
+:100880000D11C0100642000017FEBFE017138010C4
+:100890003A88071017FEBFE0171280103AC8851873
+:1008A0001618001017FEBFE01713C01017FEBFE0A8
+:1008B000171280102613801817FEBFE08B088010D7
+:1008C000CCFFBF108C0080101E0B001017FEBFE085
+:1008D000170280100B018010CCFFBF100C0180109C
+:1008E0002605001017FEBFE08B088010CCFFBF105C
+:1008F0000C048010260300104400800015FFBFE0A8
+:100900000623000017FEBFE0041280103A88091089
+:10091000408A2F80061E000017FEBFE0171A8010C5
+:100920001E05001017FEBFE08B088010CCFFBF1023
+:100930000C108010260300104400800015FFBFE05B
+:100940000613000017FEBFE017068010260B0010EC
+:1009500017FEBFE017068010E01D80101E07001074
+:1009600017FEBFE017068010E00280101E03001083
+:100970004400800015FFBFE00605000017FEBFE041
+:10098000040A80103A880910408A2F803A880100B2
+:1009900017FFBFE03A8837E01701C0DF170000DF1C
+:1009A0000402C0DE3A2800F804F8FFDE1507C0DFB5
+:1009B000150600DF040600DF15FD3FE115FC7FE1B1
+:1009C00015FBBFE115FAFFE117FDBFE0170080102E
+:1009D00015FFBFE0061C000017FFBFE01703C010A3
+:1009E00017FCBFE0170080101E03801817FFBFE040
+:1009F000170880101E04001017FFBFE017008010BA
+:100A000015FFBFE00610000017FBBFE02604001032
+:100A100017FFBFE01708801017FBFFE01506C01096
+:100A200017FFBFE015FEBFE017FFBFE01700801003
+:100A300015FFBFE017FABFE02603001017FABFE06A
+:100A400017FE3FE13AE83E1017FFFFE017FDBFE059
+:100A50001EE1BF183A8801003A8837E01701C0DF6D
+:100A6000170000DF0402C0DE3A2800F804FDFFDEB4
+:100A70001502C0DF150100DF040100DF15FF3FE1B3
+:100A800017FFBFE017088010040980103A8809108A
+:100A900000BA278017FFBFE01708C01017FFBFE09C
+:100AA00017088010040A80103A880B103A88091839
+:100AB000C0942F8017FFBFE01708C01017FFBFE0DA
+:100AC00017088010041280103A880B103A88091811
+:100AD000C0942F803A8801003A8837E01701C0DFC0
+:100AE000170000DF0402C0DE3A2800F804FBFFDE36
+:100AF0001504C0DF150300DF040300DF15FE3FE12E
+:100B000015FD7FE115FF3FE00627000017FDFFE020
+:100B100017FFBFE044008010BA9004103A8885188F
+:100B20001700801017FEFFE01E1C80180610000042
+:100B300017FFBFE04400801017FDFFE04400801065
+:100B4000BA9004103A8885181700C01017FD3FE1CD
+:100B500017FFBFE044008010BA9004103A88852047
+:100B60001500C01017FFBFE04400801015FFBFE064
+:100B700017FFBFE04400C01017FDBFE01700801052
+:100B800036EBBF1817FDBFE017008010C4FFFF1041
+:100B900017FDBFE01500C0100608000017FFBFE0FA
+:100BA0004400801015FFBFE017FDBFE01700801064
+:100BB00017FFFFE036D5BF1840CD28803A8837E0D0
+:100BC0001701C0DF170000DF0402C0DE3A2800F87A
+:100BD00004FCFFDE1503C0DF150200DF040200DFA6
+:100BE00015FF3FE115FE7FE117FEBFE01700801003
+:100BF000281080101E0C001017FEBFE01700801098
+:100C00004400001117FEFFE01500001917FEFFE079
+:100C100044008010BA9004103A88851817FFFFE04E
+:100C20001500C0100601000040CD28803A88010060
+:100C30003A8837E01701C0DF170000DF0402C0DE8A
+:100C40003A2800F804FCFFDE150300DF040300DF90
+:100C500015FE3FE115FD7FE115FF3FE0060D0000A9
+:100C600017FDFFE017FFBFE044008010BA900410AA
+:100C70003A8885181700801017FEFFE01E028018C2
+:100C8000440080000608000017FFBFE04400801009
+:100C900015FFBFE017FDBFE01700801017FFFFE052
+:100CA00036EFBF183A8805003A8837E0170000DFB2
+:100CB0000401C0DE3A2800F804FCFFDE1503C0DFA3
+:100CC000150200DF040200DF15FF3FE115FE7FE1A2
+:100CD00017FEBFE01700801017FFFFE02E078018F7
+:100CE00017FEFFE017FFBFE044008010BA90041029
+:100CF0003A888518170080100602000040CD288031
+:100D0000C4FFBF003A8837E01701C0DF170000DFDB
+:100D10000402C0DE3A2800F804F5FFDE150AC0DF41
+:100D2000150900DF040900DF15F93FE115F87FE13F
+:100D300015F7BFE117F9BFE0170D801017088010F5
+:100D400015FEBFE017F8BFE0269C001017F9BFE0C2
+:100D50001700801015FFBFE00609000017FFBFE075
+:100D60001706C01017F8BFE0170680103AC885189C
+:100D70001607800017FFBFE01700801015FFBFE0C7
+:100D800017FFFFE017F9BFE01EF4BF1806010000CF
+:100D90003A88010017FFBFE01701801017F9FFE044
+:100DA000263B801817FFBFE01701801015FFBFE03A
+:100DB00017FFBFE01706C01017FFBFE08B028010BF
+:100DC000CCFFBF103A88871817F8BFE017068010CD
+:100DD0003AC8851815FDBFE017FDBFE00E29800059
+:100DE00017F8BFE08B028010CCFFBF1017FDFFE0AB
+:100DF00016148018B401820017C3B8104400C01044
+:100E0000B401820015C3F810B401820017C4F810B1
+:100E100017F8BFE08B028010CCFFBF103A8887180C
+:100E2000B401820015C4F810C42580001587A0D035
+:100E30003A88010017F73FE1C0CF29803A880500C2
+:100E400006AC000017FD7FE117F73FE180012A8023
+:100E500017F8BFE08B02801017FDFFE03AC8C510FD
+:100E60003A88071017F8BFE08D02C01017F8BFE0EE
+:100E70001706C01017FDBFE03A88871817F8BFE0C3
+:100E80001506C01017FFBFE01700801015FFBFE068
+:100E9000B401820017C7B8104400C010B40182002A
+:100EA00015C7F810B401820017C8F81017F8BFE092
+:100EB0008B028010CCFFBF103A888718B4018200E3
+:100EC00015C8F8100632000017F8BFE01706C0106A
+:100ED00017F8BFE08B028010CCFFBF103A8887184C
+:100EE00017FFBFE0170680103AC8851815FCBFE051
+:100EF00017FCBFE00E2A800017FFBFE08B028010B6
+:100F0000CCFFBF1017FCFFE00E13801817FFBFE0E7
+:100F10001706C01017FCBFE03A88871817FFBFE01C
+:100F20001506C01017FFBFE08B02801017FCFFE012
+:100F30003AC8C5103A88071017FFBFE08D02C010ED
+:100F400017FF3FE1C0222A8017FC7FE13A88091091
+:100F500080012A800613000017FFBFE017008010F1
+:100F600015FFBFE017FFBFE0170180103A88091096
+:100F7000C0222A8015FBBFE017FFBFE017018010D9
+:100F80003A880910402C2A8017FB3FE1C0CF298006
+:100F900017FFFFE017F9BFE01ECBBF1806010000E6
+:100FA0003A88010017FFBFE0170180103A880B1044
+:100FB00017F83FE140332A80060100003A8801001B
+:100FC00017F9BFE017028010C80080101E02001041
+:100FD0003A8805000647000017F9BFE017008010A7
+:100FE00015F8BFE017F8FFE017F9BFE026058018F5
+:100FF00017F8BFE01706C01017F9BFE017168010EA
+:10100000260280183A880500063A000017F9BFE06A
+:1010100017028010D80080101E06001017F8BFE0DD
+:101020008B028010CCFFBF10260200103A8805000A
+:101030000630000017F9BFE01716C01017F8BFE020
+:101040008B028010CCFFBF103A88871817F9BFE0D9
+:101050001516C01017F8BFE043088010CC3F801071
+:101060004C00801015FABFE017F83FE1402C2A80B1
+:1010700017F83FE1C0222A8015FBBFE017F8BFE058
+:101080001700801015F8BFE017FEBFE08B08801036
+:10109000CCFFBF100C0880102603001017FB3FE1A7
+:1010A000C0CF29800605000017FEBFE0040A8010AB
+:1010B00017FB7FE13A880910C0AF2F8017F8FFE0D7
+:1010C00017F9BFE02605801817F8BFE01706C01013
+:1010D00017F9BFE01716801026D6BF1817FEBFE01D
+:1010E000040A80103A880B1017FE3FE1C0942F804D
+:1010F00017FABFE03A8837E01701C0DF170000DFBA
+:101100000402C0DE3A2800F804DFFFDE1520C0DF4D
+:10111000151F00DF041F00DF15E43FE115E37FE149
+:1011200015FD3FE015FC3FE015FA3FE015F73FE005
+:1011300015F63FE015F53FE0B401820017BDB81089
+:101140004400C010B401820015BDF810B401820043
+:10115000177FB8104400C010B4018200157FF8104A
+:1011600017E4BFE01703801015FFBFE017FFBFE0D3
+:1011700003008010CC3F8010B01180101E060010BC
+:1011800017E47FE117FF3FE180C12A8017E4BFE049
+:101190001703801015FFBFE017E4BFE017028010AF
+:1011A000280A80101E060010B401820017C2B81071
+:1011B0004400C010B401820015C2F81006520800A5
+:1011C00017FFBFE08B008010CCFFBF1015F1BFE010
+:1011D00017E4BFE01703801015F0BFE017E4BFE08D
+:1011E000170180101701801017F0FFE02E03801800
+:1011F00074010201049A2A218017278017F0BFE0AA
+:1012000003088010CC3F80103AD10410CC3F8010EE
+:10121000BA90041015EFBFE017EFBFE03005801063
+:101220001E03001017EFBFE017F1FFE00E0D80184E
+:10123000B401820017C1B8104400C010B40182008C
+:1012400015C1F810B40182001783B8104400C01013
+:10125000B40182001583F810845780001587A0D050
+:101260000614080017F1FFE017EFBFE03AC8851831
+:1012700015F1BFE017F1BFE03A88071017F0BFE0A3
+:101280008D02C01017EFBFE0700580101E330010F4
+:1012900017EFBFE004FBBF1015EEBFE017EE7FE1D4
+:1012A0004400000100A7298015FDBFE017FDBFE045
+:1012B0001E030010845A80001587A0D006FD070089
+:1012C00017EEFFE017FDBFE01502C01017E4BFE006
+:1012D000170180100B088010CCFFFF109461B7003D
+:1012E0001E05801817E4BFE0170380100405801066
+:1012F00015F4BFE00604000017E4BFE017038010F8
+:10130000040A801015F4BFE017FDBFE0170380103A
+:1013100017EEFFE03A880D1817F47FE13A880910BC
+:10132000806B088017E4BFE01703C01017FDBFE013
+:10133000170280103A88871817E4BFE01503C01021
+:1013400017E4BFE01702C01017FDBFE017028010BE
+:101350003AC8871817E4BFE01502C01017F0BFE0C5
+:1013600043088010CC3F801015FBBFE017F0BFE0B2
+:10137000170680103AD6061017F0BFE01706801047
+:101380003AD204100CC0BF103AB0861817F0BFE074
+:10139000170680103A920410EC3F80103AB086187D
+:1013A00017F0BFE0170680103A9604103AB086187E
+:1013B00017F0BFE01506C01017F0BFE01707801048
+:1013C0003AD6061017F0BFE0170780103AD2041083
+:1013D0000CC0BF103AB0861817F0BFE01707801096
+:1013E0003A920410EC3F80103AB0861817F0BFE034
+:1013F000170780103A9604103AB0861817F0BFE02D
+:101400001507C01017F0BFE08B098010CCFFBF108C
+:101410003AD204103A88071017F0BFE08B09801009
+:10142000CCFFBF103A9204103AB084183A880710E3
+:1014300017F0BFE08D09C01017E4BFE0170180105E
+:101440000B088010CCFFBF10180280101E22001065
+:1014500017E4BFE017038010040AC01017E4BFE0D0
+:101460001503C01017E4BFE01702801004F6FF1048
+:1014700017E4BFE01502C01017F0BFE0170300111A
+:1014800017F0BFE00B058010CCFF7F1117F0BFE015
+:101490001704801117F0BFE08B058010CCFFBF1040
+:1014A0004400C0001501C0D8150080D83A880F301C
+:1014B0003A880D283A880B20B4010201049938219A
+:1014C00000B6408015FEBFE03A88010017FEBFE07D
+:1014D0001E0600100602000040CD2880068A070084
+:1014E000046B80001587A0D00633070017FEBFE00D
+:1014F0001709801015FCBFE017FCBFE01E030010A9
+:10150000C46B80001587A0D0062B070017FCBFE036
+:10151000170280101E030010446C80001587A0D0B5
+:101520000664070017FEBFE01708801015FABFE039
+:1015300017F0BFE08B088010CCFFBF103AD2041028
+:10154000CCFFBF10CC3FC01017F0BFE08B0880105D
+:10155000CCFFBF103A920410CCFFBF103AB08418F1
+:1015600015EDBFE017FABFE0170480108C00801063
+:10157000262C001017FA3FE180442F8015FABFE0B7
+:1015800017FABFE01E030010447380001587A0D037
+:101590000648070017F6BFE04400801015F6BFE0CC
+:1015A00017FABFE01701801015FEBFE017FEBFE07D
+:1015B00017E3FFE0150AC01017FABFE01705801007
+:1015C000980080101E0D001017FEBFE017F0FFE01E
+:1015D0001704C0181504C01017E3BFE01709C010A6
+:1015E00017E3BFE017088010040A80103AC8871874
+:1015F00017FEBFE01506C0103A88010017F0BFE0E3
+:101600008B05C01017FEBFE08D07C01017FEBFE0AE
+:101610001709801015FCBFE017FCBFE04400C000B4
+:101620001502C01017FCBFE0151D0010171EE0D0FA
+:1016300017FCBFE01505C01017FDBFE0260900101C
+:1016400017FCBFE017028010600080101E0500101C
+:1016500017F0BFE117FD7FE117FC3FE14026338023
+:1016600015FD3FE017F0BFE01707C01017FCBFE003
+:10167000170E80103AC8851815ECBFE017FABFE0C6
+:10168000170B80103A88071017FABFE0170A80106E
+:101690003AC885181606001017FABFE0170BC010DD
+:1016A00017FABFE0170A80103AC885180601000033
+:1016B0003A88050015F3BFE017F3BFE00E010010F4
+:1016C00015F33FE017FCBFE01719C01017FCBFE08F
+:1016D000171680103AC8851817F3FFE02E01C010C6
+:1016E0003A88051817FCFFE01515801817FCBFE0B5
+:1016F00017028010180180101EF4001017FBBFE0C5
+:10170000CC0D8010180480101EF0001017F0BFE000
+:101710001706C01017FCBFE0171680101EEB8018CC
+:1017200017EDBFE026E9001017FCBFE0171480108A
+:1017300017EDFFE01EE5801817FCBFE0170FC01083
+:1017400017FCBFE0171A80101EE0801817F0BFE0EA
+:101750008B028010CCFFBF101E5B001017F0BFE0A3
+:101760001707C01017FCBFE0170E80103AC8851885
+:101770000ED6800017F0BFE01707C01017FCBFE0BF
+:10178000171A80103AC8851816D0800017FCBFE0E1
+:10179000171BC01017FCBFE01714801036CB801841
+:1017A000B401820017D9B8104400C010B4018200FF
+:1017B00015D9F81017FCBFE0171E8010260800107E
+:1017C00017F0BFE01707C01017FCBFE0171F80100D
+:1017D0003AC885180E02800017FC3FE18051338023
+:1017E000B401820017CFB8104400C010B4018200C9
+:1017F00015CFF810B401820017D0F81017ECBFE035
+:101800003A888718B401820015D0F81017FABFE0A3
+:101810000412801017EC7FE13A880910000B308029
+:1018200017F0BFE01707C01017FCBFE0150EC0107F
+:1018300017E43FE1C0CF298017FCBFE0170EC010AE
+:1018400017FCBFE0171A80101E03801817FCBFE0BA
+:10185000150300100607000017FCBFE017048010F6
+:101860001E04001017FCBFE01708C01017FCBFE0F3
+:101870001503C01017FABFE00B198010CCFFBF1082
+:101880000C0380102605001017FABFE00412801028
+:101890003A880B1017FA3FE1C0942F8017FABFE087
+:1018A0001712801017FCFFE0170F001917FCFFE05C
+:1018B000170EC0183AC8C7202E8A861817FC3FE1B9
+:1018C000408933800687060017F0BFE01707C01075
+:1018D00017FCBFE0170E80101E7C801817FCBFE0BD
+:1018E0001700801017FCFFE01E78801817F0BFE08B
+:1018F0008B028010CCFFFF1017FABFE0170B80108F
+:101900003A88091017FABFE0170A80103AC88520F4
+:101910001606001017FABFE0170B001117FABFE008
+:10192000170A80103AC88520060100003A88050091
+:101930003666C01017FCBFE0171580101E0A001095
+:10194000B401820017CCB8104400C010B40182006A
+:1019500015CCF81017E43FE1C0CF298017FC3FE118
+:101960004089338006680600B401820017DAB81097
+:101970004400C010B401820015DAF81017FCBFE073
+:101980001716C01017F0BFE08B028010CCFFBF10FD
+:101990003A88871817FCBFE01516C010B401820002
+:1019A00017BEB8104400C010B401820015BEF81074
+:1019B000B401820017BFF81017F0BFE08B0280104F
+:1019C000CCFFBF103A888718B401820015BFF81009
+:1019D00017FABFE0040A801017E47FE13A88091083
+:1019E000C0AF2F8017FABFE0040A80103A880B10AE
+:1019F00017FA3FE1C0942F8017FBBFE00C02801064
+:101A00002607001017FCBFE00B0B8010540080105D
+:101A10003A88071017FCBFE00D0BC0100606000047
+:101A200017FCBFE00B0B8010940080103A88071061
+:101A300017FCBFE00D0BC01017FCBFE01715C0105E
+:101A400017FCBFE01716001117FCBFE01719801034
+:101A50003AC885203A88851815EBBFE017FCBFE02F
+:101A60000B0A8010CCFFBF103A8885103A88071007
+:101A700017EBBFE00E05C01017FCBFE00B0B80108A
+:101A8000CCFFBF104C0080102618061017FCBFE0DA
+:101A90000B0B8010540080103A88071017FCBFE031
+:101AA0000D0BC01017FCBFE00B0BC01044FFBF00B4
+:101AB0003A7084183A88071017FCBFE00D0BC0106D
+:101AC00017FC3FE1408933800608060017FCBFE0A1
+:101AD000170280106000C0101E030018A0008010C4
+:101AE0001EA800100676010017FBBFE00C01801055
+:101AF00026030010C4BE80001587A0D006ED0500A7
+:101B000017FBBFE00C0480102603001044BF8000C8
+:101B10001587A0D006A8050017FBBFE08C00801039
+:101B20001E030010C4BF80001587A0D006E1050089
+:101B300017F0BFE0170480103A88091000BE2A8011
+:101B40002603001044C080001587A0D006D90500E8
+:101B5000040440014402000100A7298015EABFE007
+:101B600017EABFE01E03001004C180001587A0D053
+:101B700006D0050017FEBFE017088010170580107B
+:101B8000980080101E2C001017EABFE00404C0006B
+:101B90001502C01017EABFE01703801015E9BFE077
+:101BA00017E9BFE08400C0000D00C01017E9BFE0D6
+:101BB00017F0FFE01703C0181501C01017F0BFE0C1
+:101BC0000B05C01017E9BFE08D00C01017FEBFE085
+:101BD0001704801015E5BFE017FEBFE01704801062
+:101BE0001E04001017FEBFE017F0FFE01704C01836
+:101BF0001504C01017EA7FE117FE3FE1C081408065
+:101C00002608001017FEBFE017E5FFE01504C0101E
+:101C100017EA3FE180BF298084C680001587A0D0E5
+:101C200006A4050017FEBFE017E3FFE0150AC01089
+:101C300017EA3FE180BF298017FC3FE100A4348010
+:101C40003A88071017FCBFE0150CC01017FCBFE066
+:101C5000170C80101E070010441A400117FC3FE1CA
+:101C6000C004358015F63FE0C4D180001587A0D0B0
+:101C70000690050017FDBFE02605001017F0BFE134
+:101C800017FD7FE117FC3FE14026338015FD3FE063
+:101C900017F5BFE02604001017F5FFE017FCBFE0C2
+:101CA0001513C01006030000178AE0D017FCBFE030
+:101CB0001513C010178AE0D0D49FBE003A8885184B
+:101CC000158AA0D017F0BFE01706C01017FCBFE0C0
+:101CD0001518C01017FCBFE01713C01017FCBFE0A9
+:101CE0001510C01017FCBFE01710C01017FCBFE0A4
+:101CF000151AC01017FCBFE0171AC01017FCBFE080
+:101D0000150FC01017FCBFE0170FC01017FCBFE085
+:101D1000150EC01017FCBFE0171880104400C0104B
+:101D200017FCBFE01516C01017FCBFE01716C01057
+:101D300017FCBFE01519C01017FCBFE00B0B80109B
+:101D4000540080103A88071017FCBFE00D0BC0103C
+:101D500017FCBFE0C400C0001502C01017FCBFE0B4
+:101D60008425C0001505C01015F63FE0B4018200BF
+:101D700017A5B8104400C010B401820015A5F810D2
+:101D8000068E000017FEBFE017E3FFE0150AC01043
+:101D900017FBBFE00C048010260F001017F0BFE007
+:101DA0001707C01017FCBFE0171380103AC885183A
+:101DB0000E06800017F0BFE01707C01017FCBFE049
+:101DC000171A80103AC885180E03800004DC8000C2
+:101DD0001587A0D006F8040017FBBFE00C018010A7
+:101DE0002609001017FBBFE00C048010260300102A
+:101DF000C41B400117FC3FE1C004358084DD800036
+:101E00001587A0D0062B050017FBBFE08C008010C3
+:101E10001E03001044DE80001587A0D006250500B3
+:101E200017FBBFE00C048010260E001017F0BFE077
+:101E30001707C01017FCBFE0150EC01017FCBFE05D
+:101E4000170FC01017FCBFE0170E80103AC8851896
+:101E50000E04001017FCBFE0170EC01017FCBFE007
+:101E6000150FC01017FCBFE01503001017F0BFE0FE
+:101E70001706C01017FCBFE01518C01017FCBFE014
+:101E8000171880104400C01017FCBFE01516C010D2
+:101E900017FCBFE01716C01017FCBFE01519C010E3
+:101EA00017FEBFE01704C01017F0BFE01704801042
+:101EB0002617801817E4BFE017018010170680105E
+:101EC0002613001017E4BFE01701801017068010DA
+:101ED000170AC01017F0BFE0170480101E0C8018FE
+:101EE00017FEBFE017F0FFE01704C0181504C0107C
+:101EF00017FCBFE0170C80102605001017FCBFE090
+:101F0000170C801017F0FFE01704C0181503C0105D
+:101F100017FCBFE00B0B8010540080103A880710AC
+:101F200017FCBFE00D0BC01017FBBFE00C048010C6
+:101F3000261F001017FCBFE0170EC01017FCBFE0F3
+:101F4000171380103AC885180E198000B40182005A
+:101F500017A6B8104400C010B401820015A6F810EE
+:101F600017FCBFE00401C0001502C01017FA3FE1E2
+:101F7000801E2F8017FA3FE1C07933803A8807101E
+:101F800017FCBFE00D0AC01017E4BFE13A880B0050
+:101F900017FC3FE100C6308017FCBFE0171E801021
+:101FA0002606001017FC3FE1805133800603000035
+:101FB00017FCBFE0C400C0001502C01017F0BFE05E
+:101FC000170680104400C01017F0BFE01506C010BF
+:101FD00017F0BFE08B028010CCFFBF1017FCFFE0B2
+:101FE0001715C0182E2C801817F0BFE08B02801038
+:101FF000CCFFFF1017FCBFE017158010CCFFBF10FF
+:102000003AC8851815F9BFE017E4BFE01702801041
+:102010002606001017F9BFE03AC885003A880B1071
+:1020200017E43FE180012A800607000017E4BFE0C3
+:102030001706C01017F9BFE03AC885003A880B10A0
+:102040003A88091880012A8017FCBFE01715801014
+:102050003A88071017F0BFE08D02C01017FBFFE0B1
+:1020600084FFBF003A70841815FBBFE0B401820002
+:1020700017C9B8104400C010B401820015C9F81087
+:10208000B401820017CAF81017F9BFE03A88871820
+:10209000B401820015CAF81017F0BFE017068010CF
+:1020A000C4FFFF1017FCBFE01511C01017F0BFE010
+:1020B0001706C01017FCBFE01517C01006CB0200B2
+:1020C00017FCBFE01716C01017F0BFE0170680100E
+:1020D0003AC8851815F9BFE017F9BFE00E898000EE
+:1020E00017FBBFE08C008010261C001017FBFFE0E0
+:1020F00044FFBF003A70841815FBBFE017F0BFE043
+:10210000170680104400C01017F0BFE01506C0107D
+:1021100017F0BFE08B098010CCFFBF10B00080101B
+:102120001E07001017F0BFE08B098010C4FFBF101E
+:102130003A88071017F0BFE08D09C01006040000B0
+:1021400017FBFFE0C4F7BF003A70841815FBBFE02F
+:1021500017F9BFE0C4FFBF1015F9BFE017F0BFE0EB
+:102160008B028010CCFFFF1017F9BFE01608801813
+:1021700017F0BFE08B028010CCFFBF1017F9FFE013
+:102180001E31801817FBBFE04C0080101E2E00107F
+:10219000B401820017C3B8104400C010B40182001B
+:1021A00015C3F810B401820017C4F81017F0BFE08F
+:1021B0008B028010CCFFBF103A888718B4018200D0
+:1021C00015C4F81017FBBFE04C0080102606001065
+:1021D00017F0BFE08B028010CCFFBF1044008010CE
+:1021E00017F9FFE02609801817FBBFE00C018010EB
+:1021F00026DD031017F0BFE01706C01017FCBFE084
+:1022000017168010C4FFBF101ED7831817F0BFE049
+:102210008B028010CCFFBF1015F9BFE017FBFFE069
+:1022200084FFBF003A70841815FBBFE017FCBFE0C5
+:102230000B0B8010540080103A88071017FCBFE089
+:102240000D0BC010060B0000B401820017C5B810BA
+:102250004400C010B401820015C5F810B40182001A
+:1022600017C6F81017F9BFE03A888718B401820042
+:1022700015C6F81017F97FE117E43FE180012A80C5
+:1022800017F0BFE01706C01017F9BFE03A888718AB
+:1022900017F0BFE01506C01017F0BFE08B028010EA
+:1022A00017F9FFE03AC8C5103A88071017F0BFE0E9
+:1022B0008D02C01017F0BFE08B09801017F9FFE006
+:1022C000CCFFBF10CCFFFF182E08801817F0BFE01E
+:1022D0008B09801017F9FFE03AC8C5103A8807103B
+:1022E00017F0BFE08D09C0100606000017FBFFE0E5
+:1022F000C4F7BF003A70841815FBBFE017F0BFE0C9
+:102300008D09001017FABFE08B088010CCFFBF10BA
+:102310004C0080102613001017FCBFE0170280103D
+:10232000900180101E0F001017F0BFE08B0280108C
+:10233000CCFFBF10260B001017FC3FE1800E35804C
+:1023400015FCBFE0B401820017CBB8104400C010E8
+:10235000B401820015CBF810440481001587A0D089
+:102360000695030017F0BFE01706C01017F0BFE096
+:102370008B028010CCFFBF101C00A0100400A01026
+:102380003A88871817FCBFE01716001117FCBFE04A
+:10239000171580103A8885203AC8851815F9BFE0CE
+:1023A00017F9BFE00E618000B401820017C9B810B0
+:1023B0004400C010B401820015C9F81017F0BFE046
+:1023C0008B028010CCFFBF1017F9FFE01636801883
+:1023D000B401820017CAF81017F0BFE08B0280101A
+:1023E000CCFFBF103A888718B401820015CAF810D4
+:1023F00017FBBFE08C0080102617001017FCBFE011
+:1024000017028010980280101E13001017F0BFE012
+:102410001706C01017FCBFE0171680103AC88518C1
+:102420000E0D800017FCBFE01716C010B40080002E
+:10243000C43FBD103A88851815F5BFE017F5BFE019
+:102440002CC0BF102601001015F53FE017FC3FE13E
+:10245000800E358006F83B0017FCBFE01715801092
+:102460001E43031017F0BFE01706C01017FCBFE0B3
+:10247000171680101E3E831817FCBFE00B0B801050
+:10248000540080103A88071017FCBFE00D0BC010F5
+:10249000B401820017CCB8104400C010B40182000F
+:1024A00015CCF81006060000B401820017CAF81017
+:1024B00017F9BFE03A888718B401820015CAF810EE
+:1024C00017E4BFE0170280102606001017F9BFE0DE
+:1024D0003AC885003A880B1017E43FE180012A8052
+:1024E0000607000017E4BFE01706C01017F9BFE0A9
+:1024F0003AC885003A880B103A88091880012A806A
+:1025000017F0BFE08B02801017F9FFE03AC8C51042
+:102510003A88071017F0BFE08D02C01017FBFFE0EC
+:1025200084FDBF003A70841815FBBFE017FBBFE0C5
+:102530000C018010262F001017FCBFE0170280103E
+:1025400044FFBF102802C0101E2A0018BA900610BF
+:10255000F40082003A888518172A89103A6800101A
+:10256000C8240308D8240308EC240308EC24030837
+:102570002825030828250308EC2403082825030838
+:1025800017FABFE0C41BC0001506C0100608000003
+:10259000B4018200177DB8104400C010B40182005D
+:1025A000157DF81017FABFE0041AC0001506C01018
+:1025B00017FCBFE015020010B401820017A7B81085
+:1025C0004400C010B401820015A7F81017FC3FE1C9
+:1025D000800E3580042281001587A0D006350300C7
+:1025E00017FC3FE1800E3580842381001587A0D041
+:1025F0000630030017FBBFE08C0080102607001098
+:10260000041A400117FC3FE1C004358015FCBFE00F
+:10261000042B81001587A0D006E7020017FBBFE05E
+:102620000C0480101E030010042D81001587A0D01B
+:102630000620030017FCBFE017028010E000C01066
+:102640001E050018D000C0101E680118C8028010B6
+:102650001E660110062C000017FCBFE0170EC0100C
+:1026600017F0BFE0170780103AC8851816068000DB
+:1026700017F0BFE01707C01017FCBFE0171A801053
+:102680003AC885180E088000B4018200177DB81082
+:102690004400C010B4018200157DF810843181001F
+:1026A0001587A0D006C40200B401820017A6B81096
+:1026B0004400C010B401820015A6F81017FCBFE05A
+:1026C0000401C0001502C01017FA3FE1801E2F80E0
+:1026D00017FA3FE1C07933803A88071017FCBFE052
+:1026E0000D0AC01017E4BFE13A880B0017FC3FE168
+:1026F00000C6308017F0BFE017068010C4FFFF103F
+:1027000017FCBFE01511C01017F0BFE01707C0108D
+:1027100017FCBFE0170E80103AC8851816618000BC
+:1027200017F0BFE08B028010CCFFBF101E580010C6
+:1027300017FCBFE01714801017EDFFE01E5480183F
+:10274000B401820017CDB8104400C010B40182005B
+:1027500015CDF81017FCBFE01703801026050010F8
+:1027600017F0BFE01707C01017FCBFE0170E80106E
+:102770002603801817FCBFE015090010064700006B
+:1027800017FCBFE0170980104400C01017FCBFE021
+:102790001509C01017FCBFE01709C010831CA0D09A
+:1027A000CC3F80101C20801004E0BF101E3B80181E
+:1027B00017FCBFE0170F801015E8BFE017FCBFE063
+:1027C0001714001117FCBFE0171BC0103A88052032
+:1027D0002E0180183A8805187AD0061017FCBFE041
+:1027E0000B0A8010CCFFBF103A880B103A880918EA
+:1027F00080FF0C808DF2BFE08BF2BFE0A80080105C
+:102800001E020010840080008DF2BFE017FCBFE0C4
+:102810000B0A80108BF2FFE03A388518CCFFFF10CE
+:1028200017FCBFE0151CC01017FCBFE0150300101B
+:1028300017FCBFE0151E001017F0BFE01707C0100F
+:1028400017FCBFE0150FC01017FCBFE00B0A80108B
+:10285000CCFFFF1017FCBFE0151BC01017FC3FE1B9
+:102860004089338017FCBFE0170F801017E8FFE0A6
+:102870003AC885180E03800017FCBFE017E8FFE098
+:10288000150FC010444581001587A0D006890200AD
+:1028900017FCBFE01509001006D400003A880100BB
+:1028A00006D2000017FCBFE01509001017F0BFE0CA
+:1028B0001707C01017FCBFE0171A80103AC8851818
+:1028C0000E068000B401820017CEB8104400C0107C
+:1028D000B401820015CEF8100626020017F0BFE002
+:1028E0001707C01017FCBFE0170E80103AC88518F4
+:1028F00015ECBFE0B401820017CFB8104400C0103F
+:10290000B401820015CFF810B401820017D0F8107E
+:1029100017ECBFE03A888718B401820015D0F81090
+:1029200017FCBFE0171E80102608001017F0BFE04C
+:102930001707C01017FCBFE0171F80103AC8851892
+:102940000E02800017FC3FE18051338017F0BFE09A
+:102950001707C01017FCBFE0171A80101E0580185B
+:1029600017FCBFE0150300104400800015F7BFE01E
+:102970000607000017FCBFE0170480101E040010BB
+:1029800017FCBFE01708C01017FCBFE01503C0100C
+:1029900017FCBFE0171B801015E7BFE017FCBFE076
+:1029A0000B0A80100DF2BFE017FCBFE0171CC0102F
+:1029B00017E7BFE02E0A80180BF2FFE00BF2BFE032
+:1029C0003A38851817E77FE13A88091080FF0C80B4
+:1029D0002804C0101E010018040480000DF2BFE09E
+:1029E0000BF2FFE017E7BFE03A8885187000D810B7
+:1029F0001E0100180400980017FCFFE0151B80184A
+:102A000017FABFE0171280103A88071017ECBFE0E2
+:102A10000E12801817FCBFE01714C01017FABFE0A1
+:102A200017128010CCFFBF103AC8871817FCBFE000
+:102A30001514C01017FABFE00412C01017FABFE057
+:102A4000171280103A880B103A880918000B308052
+:102A50004400800015F8BFE0060D000017FABFE043
+:102A60000412801017EC7FE13A880910000B3080C7
+:102A700017FCBFE01714C01017ECBFE0CCFFBF106D
+:102A80003AC8871817FCBFE01514C01015F83FE0CE
+:102A900017FABFE00B198010CCFFBF100C03801099
+:102AA0002605001017FABFE0041280103A880B10B8
+:102AB00017FA3FE1C0942F8017F0BFE01707C0104E
+:102AC00017FCBFE0150EC01017FCBFE0170FC010B9
+:102AD00017FCBFE0170E80103AC885180E040010CE
+:102AE00017FCBFE0170EC01017FCBFE0150FC01099
+:102AF00017FCBFE017028010E001C0101E1A00187A
+:102B00000802C0101E030018A00180101E0600104D
+:102B1000063600002002C0101E220018A0028010FD
+:102B20001E2700100631000017F8BFE0262A00100B
+:102B300017FABFE08B088010CCFFBF100C08801084
+:102B40002605001017FA3FE140382F801789E0D0A2
+:102B500017FCBFE01506C01017FCBFE04402C00020
+:102B60001502C010061C000017F8BFE0261C00105C
+:102B700017FCBFE08402C0001502C01017FC3FE143
+:102B800040563580171BA0D03A8885103A88071028
+:102B900017FCBFE01506C01017FA3FE140382F8040
+:102BA000060F000017F8BFE0260F001017FC3FE1EA
+:102BB000800E3580446681001587A0D006BD0100D7
+:102BC000171BA0D03A8885103A88071017FCBFE081
+:102BD0001506C010066701003A88010006030000D0
+:102BE0003A880100060100003A88010017FBBFE0A7
+:102BF0000C0480102642001017FCBFE01711C01013
+:102C000017F0BFE0170680103AC885181614001098
+:102C100017FCBFE01711C01017F0BFE017068010B7
+:102C20001E37801817FCBFE01712C01017F0BFE066
+:102C3000170780103AC885181609001017FCBFE066
+:102C40001712C01017F0BFE0170780101E2C801855
+:102C500017FCBFE01714C01017EDBFE02E28801836
+:102C600017F0BFE08B028010CCFFBF101E0E0010CB
+:102C700017FCBFE01712C01017F0BFE01707801055
+:102C80001E09801817FCBFE01714C01017EDBFE035
+:102C90002E058018B401820017D1B8104400C0106E
+:102CA000B401820015D1F81017FCBFE017EDFFE06A
+:102CB0001514C01017F0BFE01706C01017FCBFE0D6
+:102CC0001511C01017F0BFE01707C01017FCBFE0C8
+:102CD0001512C01017FCBFE01714801017FCFFE09E
+:102CE0001723C0182E04801817FCBFE01714C0105B
+:102CF00017FCBFE01523C0104400800015F7BFE0AB
+:102D000017FBBFE00C0880102656001017F0BFE03C
+:102D10008B098010CCFFBF102652001017FCBFE0BB
+:102D200017028010880280101E4E001017F0BFE0BE
+:102D30008B098010CCFFFF1017FABFE0170A801034
+:102D40003A888518700090101E07001017F0BFE039
+:102D50008D09001017FBFFE0C4F7BF003A7084181C
+:102D600015FBBFE0064D000017F0BFE01706C010CE
+:102D700017F0BFE08B098010CCFFBF103A8887188E
+:102D800017FCBFE0171780103AC885180E25800081
+:102D900017F0BFE01706C01017F0BFE08B098010D6
+:102DA000CCFFBF103A88871817FCBFE01517C0107A
+:102DB00017FABFE0170AC01017FCBFE01717001181
+:102DC00017FCBFE0171680103AC885203A8885188E
+:102DD000C4FFFF1017FABFE0151AC01017FABFE0C2
+:102DE000171A80101E06001017FABFE08B0880101B
+:102DF000141080103A88071017FABFE08D08C01031
+:102E000017FA3FE1C0122F8017FCBFE00324C01067
+:102E100004FFBF003A7084183A88071017FCBFE01F
+:102E20000524C01017F0BFE08B09001117F0BFE0B8
+:102E30008B02C010CCFFBF20CCFFFF1836148018C7
+:102E400017FABFE0170480100C4080101E1000100D
+:102E500017E4BFE117F07FE117FA3FE1C03E33808E
+:102E6000060B000017FCBFE01716C01017FCBFE0F0
+:102E7000171780103AC885180E07800017FCBFE0AE
+:102E80001716C01017FCBFE01517C010060300008E
+:102E90003A880100060100003A88010017F0BFE0FF
+:102EA0008B028010CCFFBF101E03001017FBBFE089
+:102EB0004C008010265A001017FCBFE0170280104B
+:102EC000880280101E56001017F0BFE01706C010D1
+:102ED00017FCBFE0171680101E33801817FCBFE0E8
+:102EE0001700801017FCFFE01E2F801817FCBFE0B2
+:102EF00017028010180180101E2B001017FCBFE075
+:102F00000B0B8010540080103A88071017FCBFE0AC
+:102F10000D0BC01017FCBFE01716C01017F0BFE074
+:102F20008B028010CCFFBF103A88871817FCBFE0D7
+:102F30001516C01017F0BFE043088010CC3F80107A
+:102F40004C00801015FBBFE0B401820017BEB81022
+:102F50004400C010B401820015BEF810B401820014
+:102F600017BFF81017F0BFE08B028010CCFFBF1026
+:102F70003A888718B401820015BFF81017FABFE02D
+:102F8000040A801017E47FE13A880910C0AF2F804F
+:102F900017FABFE0040A80103A880B1017FA3FE1D5
+:102FA000C0942F80060B000017E4BFE117F07FE10B
+:102FB00017FC3FE100C6308015FBBFE017FCBFE007
+:102FC0000B0B8010540080103A88071017FCBFE0EC
+:102FD0000D0BC01017FABFE0170BC01017FCBFE0B5
+:102FE0001716001117FCBFE0171980103AC885208A
+:102FF0003A88851815E6BFE017FCBFE0172280105D
+:103000003A88071017E6BFE00E0B801817E6BFE0FE
+:10301000CCFFFF1017FCBFE01522C0100606000011
+:1030200017E43FE1C0CF298017FBFFE084FFBF001A
+:103030003A70841815FBBFE017FBBFE04C0080100E
+:10304000263E001017FCBFE0170280108802801097
+:103050001E0D001017FA3FE1C0842F8017FCBFE05F
+:103060000B0B8010540080103A88071017FCBFE04B
+:103070000D0BC01017FCBFE0171680104400C010E5
+:1030800017FCBFE01516C01017FCBFE01702801038
+:1030900044FFBF102802C0101E290018BA90061065
+:1030A000F40082003A88851817FE8B103A680010E9
+:1030B0001830030818300308883003082830030844
+:1030C0008830030888300308383003086C30030860
+:1030D00017FCBFE04401C0001502C0100618000034
+:1030E00017FCBFE0C401C0001502C01006140000A8
+:1030F00017FCBFE08402C0001502C01017FC3FE1BE
+:1031000040563580171BA0D03A8885103A880710A2
+:1031100017FCBFE01506C01017FA3FE140382F80BA
+:1031200006070000171BA0D03A8885103A880710C0
+:1031300017FCBFE01506C010060100003A88010028
+:1031400017F7BFE01E05001017FCBFE00B0B801047
+:10315000CCFFBF104C0080102666001017FC3FE12A
+:1031600040893380066300003A88010006010000B0
+:103170003A88010017FBBFE00C0180102603001005
+:1031800004A981001587A0D0064A000017E43FE19A
+:10319000C0CF298017FCBFE00B0B801054008010BB
+:1031A0003A88071017FCBFE00D0BC01017FC3FE179
+:1031B0004089338006540000B40182001783B810A0
+:1031C0004400C010B40182001583F81017FDBFE061
+:1031D0002603001017FD3FE180BF298015FD3FE069
+:1031E00017FBBFE00C0180102603001004AD810026
+:1031F0001587A0D0062F000017F0BFE0170480103D
+:103200003A88091000BE2A802603001044AF8100CE
+:103210001587A0D00627000017FBBFE00C04801024
+:10322000260C001017F0BFE01707C01017E4BFE02E
+:10323000150180D804018000150080D83A880F1845
+:103240003A880D0017F07FE117FC3FE180B434802D
+:103250000613000017FBBFE08C008010260500104D
+:1032600017F0BFE0170680104400C01017F0BFE051
+:103270001506C01017F0BFE01706C01017E4BFE036
+:10328000150180D804058000150080D83A880F0009
+:103290003A880D1817F07FE117FC3FE180B43480C5
+:1032A00017F6BFE02615001017FA3FE1C06F2D801A
+:1032B0000612000017FDBFE02602001017FD3FE1D7
+:1032C00080BF298017E43FE1C0CF298017F6BFE017
+:1032D000260C001017FA3FE1C06F2D803A880100DC
+:1032E000060800003A880100060700003A8801003D
+:1032F000060500003A880100060300003A88010034
+:10330000060100003A8801003A8837E01701C0DF63
+:10331000170000DF0402C0DE3A2800F804F5FFDEE3
+:10332000150AC0DF150900DF040900DF15F93FE1C8
+:1033300015F87FE115F7BFE117F9BFE0170D801011
+:103340001708801015FCBFE017F8BFE017038010C6
+:1033500015FFBFE017F8BFE01702801015FDBFE0B2
+:103360000642000017FFBFE003008010CC3F801032
+:1033700015FBBFE017FBBFE0263F001017FBBFE0C7
+:10338000580080101E0300104400800015FEBFE0AE
+:103390000607000017FFBFE0440080100300801004
+:1033A000CC3F801015FEBFE017FEBFE00E3480005A
+:1033B00017FBBFE0980080101E1F001017FEBFE033
+:1033C00020018010261E001017F7BFE04308801070
+:1033D000CC3F80108C008010261B001017FFBFE030
+:1033E0008B0080108DFABFE08BFABFE03AD2041058
+:1033F0003A8807108BFABFE03A9204103AB084186A
+:103400008DFABFE017FC3FE1C07933803A8807109E
+:103410008BFABFE0CCFFFF182E03801817FC3FE1AA
+:10342000C0793380060100008BFABFE017F9FFE096
+:103430000D0A8018060500003A8801000603000006
+:103440003A880100060100003A88010017FDFFE0FC
+:1034500017FEBFE03AC8851815FDBFE017FEBFE0B4
+:1034600017FFFFE03A88851815FFBFE017FDBFE0A2
+:1034700016BCBF00060300003A88010006010000E8
+:103480003A88010017F83FE180BF29803A8801009F
+:103490003A8837E01701C0DF170000DF0402C0DE02
+:1034A0003A2800F804F8FFDE1507C0DF150600DF34
+:1034B000040600DF15FC3FE115FB7FE115FABFE1D3
+:1034C00017FBBFE08B098010CCFFBF10C4FFBF10FB
+:1034D00015FFBFE00632000017FABFE017028010A8
+:1034E00017FFFFE02E24801817FABFE01703C01063
+:1034F00017FFBFE03A88851815FEBFE017FCBFE054
+:10350000170180101709801015FDBFE017FEBFE0FE
+:103510000300C01017FDBFE04524C01017FDBFE039
+:1035200003248010540080103A88071017FDBFE074
+:103530000524C01017FEBFE04400001117FABFE0D9
+:103540001702C01017FFBFE03AC88518C4FFBF10AC
+:103550003A880D103A880B2017FE3FE1806B0880F7
+:1035600017FABFE017028010C4FFFF1017FABFE080
+:103570001502C0100611000017FFFFE017FABFE0A8
+:10358000170280103AC8851815FFBFE017FABFE090
+:103590001706801015FABFE017FABFE026030010E7
+:1035A00017FFBFE00ECC3F10060100003A88010073
+:1035B00074010201049D2A21801727803A8837E090
+:1035C0001701C0DF170000DF0402C0DE3A2800F850
+:1035D00004FBFFDE1504C0DF150300DF040300DF7A
+:1035E00015FD3FE117FDBFE0171E80101E02001001
+:1035F00040CD288006800000B401820017ABB810CF
+:103600004400C010B401820015ABF810177DE0D063
+:1036100017FDBFE0171E80103AC88518840C4001C2
+:103620003A88091080FF0C8015FEBFE017FDBFE04F
+:10363000172080102644001017FEBFE01E13001054
+:1036400017FDBFE017208010900080101E050010AD
+:1036500017FDBFE017208010C4FFFF1017FDBFE06B
+:103660001520C01017FDBFE01721801090008010BA
+:103670001E42001017FDBFE017218010C4FFFF108D
+:1036800017FDBFE01521C010063C000017FEBFE08B
+:10369000C4FFBF10BA90061017FDBFE017208010BE
+:1036A000FAD005103AC8851815FFBFE017FDBFE036
+:1036B0001720C01017FFBFE03A88871817FDBFE03A
+:1036C0001520C01017FDBFE01720801016038000E2
+:1036D00017FDBFE04400C0001520C01017FFBFE079
+:1036E0000E03001017FFBFE03AC8850015FFBFE0CA
+:1036F00017FDBFE0172180107AD00510CCFFBF1056
+:103700001C00A0100400A01017FFFFE03AC88518A5
+:1037100015FFBFE017FDBFE01721C01017FFBFE086
+:103720003A88871817FDBFE01521C01017FDBFE0CC
+:10373000172180101611800017FDBFE04400C00063
+:103740001521C010060D000017FEBFE01602800014
+:103750004400800015FEBFE017FEBFE0FA9006109F
+:1037600017FDBFE01520C01017FEBFE03A88851096
+:103770003A88071017FDBFE01521C01017FDBFE004
+:10378000151E001017FDBFE01507001017FDBFE064
+:1037900017208010BAD0071017FDBFE01721801046
+:1037A0003A8885187AD00510CCFFFF101C00E0186D
+:1037B0000400E01817FDBFE01508C01017FDBFE0BA
+:1037C00017088010880080101E04001017FDBFE04D
+:1037D0008400C0001508C0100607000017FDBFE0F8
+:1037E00017088010502080101E03001017FDBFE046
+:1037F0000420C0001508C0103A8837E01701C0DF68
+:10380000170000DF0402C0DE3A2800F804FDFFDEE6
+:10381000150200DF040200DF15FE3FE117FEBFE0E6
+:1038200017018010170A801015FFBFE017FFBFE0D7
+:103830001709C01017FFBFE017088010040A801096
+:103840003AC885183A8837E0170000DF0401C0DE67
+:103850003A2800F804FAFFDE1505C0DF150400DF82
+:10386000040400DF15FC3FE117FCBFE02607001051
+:1038700017FCBFE0170180102604001017FCBFE002
+:1038800017018010170A80101E06001017FCBFE0F9
+:1038900017058010980080101E020010046D810032
+:1038A0000625000017FC3FE14075338015FFBFE09F
+:1038B00017FFBFE0506D81101E020010046D8100E3
+:1038C00015FFBFE017FCBFE01701801015FEBFE039
+:1038D00017FEBFE01709801015FDBFE017FDBFE020
+:1038E0000B0B8010CCFFBF100C00811026040010C1
+:1038F00017FDBFE00B0A8010CCFFBF10060E0000C2
+:1039000017FDBFE00B0A8010CCFFBF102609001086
+:1039100017FDBFE00B0A8010CCFFFF1017FFBFE0C0
+:103920000E04801817FDBFE00B0A8010CCFFBF10FB
+:1039300015FFBFE017FFBFE03A8837E01701C0DF8F
+:10394000170000DF0402C0DE3A2800F804E8FFDEBA
+:103950001517C0DF151600DF041600DF15EA3FE17A
+:1039600017EABFE0170D80101708801015F7BFE0A9
+:1039700015FB3FE017EABFE0171AC01017EABFE0D7
+:10398000170E80103A008518CC3F801015F6BFE066
+:1039900015FA3FE017EABFE0170FC01017EABFE0C3
+:1039A000170E80103AC8851815F5BFE017EABFE07A
+:1039B0001714801015FEBFE017EABFE0171B801038
+:1039C0003A88071017FEBFE00E06801817EABFE01E
+:1039D000171B80103A88071004FFBF003A70841844
+:1039E00015FEBFE017EABFE0830A8010CC3F8010CD
+:1039F0001C20801004E0BF102609001017FEBFE055
+:103A00001E0300104400800015FEBFE00604000005
+:103A100017EABFE01504001017EABFE01507001011
+:103A200017F7BFE01712801017FEFFE02E01801875
+:103A30003A8805183A88071017F5BFE03AC8851884
+:103A400015FFBFE017EABFE01702C0107401820043
+:103A50003A888518030AB210CC3F801015FDBFE0EC
+:103A600017FDBFE08C0080102609001017FBFFE057
+:103A70000488A0D03A88851817F7FFE117FDBFE149
+:103A80003A880B1017EA3FE1C092348015FBBFE083
+:103A900017FFBFE00E09001015FF3FE017FEBFE063
+:103AA0001E06001017EABFE01503001017EABFE07A
+:103AB000170EC01017EABFE0150FC01017EABFE0DD
+:103AC0000B0A8010CCFFFF1017FFBFE00E06801816
+:103AD00017EABFE00B0A8010CCFFBF1015FFBFE054
+:103AE0004400800015FABFE017EABFE0170FC010CE
+:103AF00017FFBFE03A88871817EABFE0170E0011DA
+:103B000017F7BFE0171280103A8885203AC8851849
+:103B10000E04001017FDFFE084FFBF003A70841808
+:103B200015FDBFE017F7BFE0170B80103A880710AC
+:103B300017F7BFE0170A80103AC88518160600105C
+:103B400017F7BFE0170BC01017F7BFE0170A801078
+:103B50003AC88518060100003A88050015FEBFE046
+:103B600017FDBFE04C008010260D001017F7BFE0D6
+:103B7000171280101E0A001017EABFE00B0B80100E
+:103B8000CCFFBF100C0480102666001017EABFE0BF
+:103B9000170FC01017EABFE0170E801026618018BB
+:103BA00017EABFE00B0B8010CCFFBF104C00801059
+:103BB0001E5E001017FDBFE08C0180101E5D00101E
+:103BC00017EABFE01710C01017EABFE0170E801009
+:103BD0003AC885181659800017FFBFE02624001048
+:103BE00017EABFE00B0A8010CCFFBF1017FFFFE001
+:103BF0002654801817F6BFE01E05001017EABFE034
+:103C00000B0B8010CCFFBF100C018010260600109B
+:103C100017FFFFE017F5BFE03A88851817F7FFE0B8
+:103C20001712C0180E49C01017EABFE0830A8010AF
+:103C3000CC3F80101C20801004E0BF101E450010F7
+:103C400017EABFE0172380107AD004103A880710D3
+:103C500017FFBFE00E41C01017EABFE0170FC010FA
+:103C600017EABFE0171A80103AC88518163D0010F1
+:103C700017FEBFE00E1C800017EABFE01719C01046
+:103C800017EABFE0171680103AC885183A8807105F
+:103C900017FEBFE03AC8C51015F4BFE017F7BFE044
+:103CA000170A80101E07001017EABFE00B0A8010E9
+:103CB000CCFFBF103A8885103A88071017F4BFE090
+:103CC0000E2AC01017F4BFE02419C01017F7BFE088
+:103CD000170B80103A880B103A88091880FF0C8067
+:103CE000F00880102623001017F7BFE0171280108D
+:103CF000260A001017EABFE0170380101E07001005
+:103D000017EABFE0170480101E04001017EABFE096
+:103D10001507001017EA3FE1008334803A88050058
+:103D200006EC02003A880100061300003A88010000
+:103D3000061100003A880100060F00003A880100D1
+:103D4000060D00003A880100060B00003A880100C9
+:103D5000060900003A880100060700003A880100C1
+:103D6000060500003A880100060300003A880100B9
+:103D7000060100003A88010040E9288017F5BFE0FD
+:103D800015F8BFE017F7BFE01718801015F9BFE06E
+:103D900017FFBFE026550010060A000017F8FFE0E5
+:103DA00017F9BFE0170280103AC8851815F8BFE070
+:103DB00017F8BFE01606001017F9BFE017068010CD
+:103DC00015F9BFE017F9BFE01EF43F10060100002F
+:103DD0003A88010017F9BFE01E01001040CD28808D
+:103DE00017F9BFE01702C01017F8BFE03A8885182E
+:103DF00015F8BFE017F9BFE017068010260B00107A
+:103E000017F9BFE0170280103A88071017FFBFE0CC
+:103E10000E06801817FDFFE084FFBF003A7084187B
+:103E200015FDBFE04400800015FABFE017FDBFE0BC
+:103E30004C0080102608001017F7BFE01712801002
+:103E400017FFFFE02E04801817FDFFE084FFBF007E
+:103E50003A70841815FDBFE017F9BFE01702801013
+:103E60003A88071017FFBFE00E0180183A8805183E
+:103E700015FFBFE017F8BFE01E07001017F9BFE0FD
+:103E80001703C01017F9BFE0170480103AC885184F
+:103E9000CC0080102615001017F9BFE01702C010E3
+:103EA00017F8BFE03AC885183A88071017FFBFE037
+:103EB0000E0180183A88051815FFBFE01717A0D02B
+:103EC00004F2BF103A88071017FFBFE00E078018F2
+:103ED000B401820017DDB710880080101E030010A7
+:103EE0001717A0D004F2BF1015FFBFE017FFBFE007
+:103EF0002635001017F8BFE01E33001017F9BFE099
+:103F00001701801017098010580080101E2E001015
+:103F100017F9BFE01703C01017F9BFE017048010AE
+:103F20003AC88518CC0080101E27001017FBBFE090
+:103F30001E2500103A880B008400000100A729808C
+:103F400015FCBFE017FCBFE01E03001040EF288007
+:103F5000441A8000065F020017F9BFE01701C01085
+:103F600017FCBFE01501C01017FCBFE0170180105F
+:103F70001709C0104400C0181509C01017F9BFE098
+:103F80001704C01017FCBFE01504C01017F9BFE0FC
+:103F90001705C01017FCBFE01505C01017FFBFE0E4
+:103FA000040A80103A88071017FCBFE01502C01001
+:103FB00017F9BFE01703801004F6FF1017FCBFE0ED
+:103FC0001503C010062700001764A0D0040A801053
+:103FD0003A880B10C400000100A7298015FCBFE03F
+:103FE00017FCBFE01E03001040EF2880441A800039
+:103FF0000638020017FCBFE0040AC0001502C0101A
+:1040000017FCBFE0170380101764E0D03A88C71090
+:1040100017FCBFE01503C01017FFBFE0261100100A
+:1040200017F7BFE01718801017FFBFE117F57FE102
+:104030003A88091000D429803A88071017FCBFE09D
+:104040001506C01017FCBFE0170680101E050010F3
+:1040500017FC3FE1C0CF298040EF2880441A800040
+:10406000061C020040EF288017FFBFE0262D00103D
+:1040700017EABFE0830A8010CC3F80101C2080101C
+:1040800004E0BF102609001017FFBFE058008010A1
+:104090001E060010B401820017B9B8104400C01009
+:1040A000B401820015B9F8100643000017EABFE01A
+:1040B000170FC01017EABFE0171A80103AC885180A
+:1040C0000E0C0010B401820017B6B8104400C010E6
+:1040D000B401820015B6F810B401820017B7F810C9
+:1040E00017FFBFE03A888718B401820015B7F810AF
+:1040F00006310000B401820017B4B8104400C010AB
+:10410000B401820015B4F810B401820017B5F8109C
+:1041100017FFBFE03A888718B401820015B5F81080
+:104120000625000017EABFE00B0B8010CCFFBF1084
+:104130004C00801026060010B401820017B8B81099
+:104140004400C010B401820015B8F810061A00002F
+:1041500017FDBFE0CC01801026060010B4018200DC
+:1041600017BCB8104400C010B401820015BCF81090
+:104170000611000017EABFE01710C01017EABFE0F1
+:10418000170E80103AC885180E068000B401820010
+:1041900017BAB8104400C010B401820015BAF81064
+:1041A00006050000B401820017BBB8104400C0101F
+:1041B000B401820015BBF81017FCBFE01703801094
+:1041C00015F3BFE017FCBFE0170180101701801046
+:1041D00017F3FFE02E0380187401020104A22A21C4
+:1041E0008017278017FCBFE015F2BFE017EABFE099
+:1041F000170C80101E0300107401020104AA2A216A
+:104200008017278017EABFE0170C8010040A80018E
+:104210003A880B1017F33FE1806B088017FDBFE071
+:104220004C008010260F001017EABFE00B0B801027
+:10423000CCFFBF100C048010260A001017EABFE064
+:10424000170FC01017EABFE0171A80101E0580185C
+:1042500017EABFE0170F8010C4FFFF1017EABFE096
+:10426000150FC01017EABFE0170F80103AD60610DE
+:1042700017EABFE0170F80103AD204100CC0BF102D
+:104280003AB0861817EABFE0170F80103A92041070
+:10429000EC3F80103AB0861817EABFE0170F801085
+:1042A0003A9604103AB0861817F3BFE01506C0100E
+:1042B00017EABFE0171680103AD6061017EABFE0DB
+:1042C000171680103AD204100CC0BF103AB08618EE
+:1042D00017EABFE0171680103A920410EC3F8010E6
+:1042E0003AB0861817EABFE0171680103A96041005
+:1042F0003AB0861817F3BFE01507C01017FDBFE0EE
+:104300008C0080102623001017F7BFE017018010E3
+:1043100015F1BFE017F7BFE0170580109800801077
+:104320001E1A001017FDBFE00C0480101E1B0010A9
+:1043300017F3BFE01704801004EBFFE03A880B1876
+:104340003A88091000373B8015F0BFE017F0BFE056
+:104350002609001017F0BFE01709C01017F0BFE0E2
+:1043600017088010040A80103AC8871817F1BFE0B8
+:104370001506C0100609000017F1BFE00491C00047
+:104380001506C0103A8801000604000040CD2880C0
+:10439000060300003A880100060100003A88010087
+:1043A00017FBBFE0262B00100440400184000001F1
+:1043B00000A7298015EFBFE017EFBFE01E04001033
+:1043C00017FC3FE1C0CF2980441A8000064101005C
+:1043D00017F2BFE01706C01017EFBFE01506C010B8
+:1043E00017F2BFE017EFFFE01506C0100606000049
+:1043F00017FBBFE04400C01015FBFFE00488E0D0CD
+:104400003A88C5100500001017FBBFE0CC008010F3
+:104410001EF73F1017EFBFE01703801017FBBFE137
+:10442000048860D13A880910806B088017EFBFE0DC
+:1044300017FBFFE01502C01017FBBFE0040580105A
+:10444000BAD004103A9104103A88071017F3BFE06D
+:104450000508C01017FDBFE03A88071017F3BFE04A
+:104460004508C01017F7BFE0170B8010BAD0041032
+:104470003A88071017FEBFE00E06C01017EABFE02B
+:104480000B0A8010CCFFBF1017FEFFE00E01801852
+:1044900015FE3FE017EABFE01719C01017EABFE0AA
+:1044A000171680103AC885183A88071017FEBFE023
+:1044B0000E06C01017EABFE01719C01017EABFE0D8
+:1044C000171680103AC8851815FEBFE0B4018200A7
+:1044D00017DDB7101E02001015FE3FE0060E0000AB
+:1044E000B401820017DDB710C4FFBF101719E0D068
+:1044F0003A38C71017FEBFE00E078018B4018200DB
+:1045000017DDB710C4FFBF103A8807101719A0D0E5
+:104510003A38851815FEBFE017FEBFE0CCFFBF108C
+:104520003AD204103A88071017FEBFE0CCFFBF1044
+:104530003A9204103AB084183A88071017F3BFE093
+:104540008D08C01017EABFE01710C01017EABFE0CF
+:10455000170F80103AC885180E1C800017EABFE0BC
+:10456000171080103A88071017EABFE0170F801065
+:104570003AC88518CCFFBF103AD204103A88071009
+:1045800017EABFE0171080103A88091017EABFE059
+:10459000170F80103AC88520CCFFBF103A92041044
+:1045A0003AB084183A88071017F3BFE08D09C0109D
+:1045B00017F3BFE043088010140880103A880710F2
+:1045C00017F3BFE04508C0100604000017EABFE07B
+:1045D000170EC01017EABFE01510C01017FFBFE09C
+:1045E000260C001017F5FFE017FFBFE03A8885188A
+:1045F00017F7FFE01712C0181E06C01017F3BFE030
+:1046000043088010140280103A88071017F3BFE0A7
+:104610004508C01017EABFE0830A8010CC3F801025
+:104620001C20801004E0BF102603001017EABFE032
+:10463000170480101E4B001017EABFE0170F801000
+:1046400015EEBFE017FDBFE08C00801026050010BE
+:1046500017EABFE0170F80104400C01017EABFE050
+:10466000150FC01017FDBFE04C008010260B001086
+:1046700017EABFE0170F80104400C01017EABFE030
+:10468000150FC01017EABFE00B0B80101404801048
+:104690003A88071017EABFE00D0BC01017EABFE019
+:1046A000170FC01017FFBFE03A88871817EABFE05E
+:1046B000150FC01017EABFE0170FC01017EABFE0D0
+:1046C000171A80103AC885180E12800017EABFE04A
+:1046D000170FC01017EABFE0151AC01017EABFE0A5
+:1046E000171E80101E0B0010177DE0D017EABFE0E8
+:1046F000151EC01017EABFE017EEFFE0151FC0102F
+:10470000B401820017AAB8104400C010B40182009E
+:1047100015AAF81017EABFE0170380101E2000103A
+:1047200017EABFE0170FC01017EABFE0170E80109E
+:10473000261B801817EABFE01708C01017EABFE071
+:104740001503C01017EABFE01704801026140010EC
+:1047500017EABFE01504001017EABFE015070010C4
+:10476000060F000017EABFE0170FC01017FFBFE0E9
+:104770003A88871817EABFE0171A80103AC88518D8
+:104780000E08800017EABFE0170FC01017FFBFE048
+:104790003A88871817EABFE0151AC0100601000012
+:1047A0003A88010015ED3FE017FCBFE017038010C9
+:1047B00015ECBFE017FBBFE03A88071017FFBFE01A
+:1047C0003A888518040A80103A88071017ECBFE071
+:1047D0008D00C01017F7BFE0171F80103A880B102C
+:1047E00017FC3FE180652A8015EDBFE017EDBFE0C3
+:1047F0002613001017EDBFE0581A80101E0E00108F
+:1048000017FCBFE0170880101E03001017FCBFE064
+:104810001706801015FCBFE017FC3FE1C0CF2980D0
+:1048200017EABFE0170D80103A880910001D358087
+:1048300017EDBFE00627000017EDBFE006250000DA
+:10484000B40182001780B8104400C010B401820087
+:104850001580F810B401820017B3B8104400C010DE
+:10486000B401820015B3F81017FEBFE00E0E8000F1
+:1048700017EABFE01716C01017FEBFE03A88871886
+:1048800017EABFE0171980103AC885180E06800095
+:1048900017EABFE01716C01017FEBFE03A88871866
+:1048A00017EABFE01519C01017EABFE00B0BC010E4
+:1048B00004EFBF003A7084183A88071017EABFE087
+:1048C0000D0BC01017FABFE02601001006303C00A7
+:1048D0003A8805003A8837E01701C0DF170000DF8B
+:1048E0000402C0DE3A2800F804FCFFDE1503C0DF36
+:1048F000150200DF040200DF15FE3FE117FEBFE0F6
+:1049000017208010BAD0071017FEBFE017218010C3
+:104910003A8885187AD0051015FFBFE017FEBFE072
+:1049200017038010260300107401020104AD2A2130
+:104930008017278017FFBFE03A88091017FEBFE0F5
+:104940001707C010740182003A888518C30CB21092
+:10495000CC3F80103A388520CCFFFF101C00E018B7
+:104960000400E01817FEBFE01504C01017FEBFE0FA
+:1049700017048010880280101E04001017FEBFE08C
+:104980008402C0001504C0100607000017FEBFE037
+:1049900017048010501E80101E03001017FEBFE089
+:1049A000041EC0001504C01017FEBFE017078010DA
+:1049B000080380101E05001017FEBFE017078010C7
+:1049C0004400C01017FEBFE01507C0103A88010070
+:1049D0003A8837E01701C0DF170000DF0402C0DEAD
+:1049E0003A2800F804F8FFDE1507C0DF150600DFDF
+:1049F000040600DF15FD3FE115FC7FE115FBBFE17B
+:104A000015FAFFE117FDBFE00B0B8010CCFFBF10C4
+:104A10000C028010260200103A880500061F0000D4
+:104A200017FBBFE08C008010261A001017FA3FE138
+:104A3000C07933808DFEBFE017FCBFE08400C0006A
+:104A40000500C01017FCBFE0440080100401C00046
+:104A50000500C0108BFEBFE03AD204103A88071060
+:104A600017FCBFE0840080100500C01017FCBFE0F9
+:104A7000C40080108BFEFFE00500C0100401800020
+:104A800015FFBFE017FCBFE00401801015FCBFE07C
+:104A90000601000015FF3FE017FFBFE03A8837E04E
+:104AA0001701C0DF170000DF0402C0DE3A2800F85B
+:104AB00004FFFFDE150000DF3A8839D8440080008B
+:104AC000158AA0D0B40182000499B810B401C200C4
+:104AD000159AB818B4018200179AF810B401820030
+:104AE0001599F8103A8801003A8837E0170000DF7E
+:104AF0000401C0DE3A2800F804FBFFDE1504C0DF25
+:104B0000150300DF040300DF15FD3FE117FDBFE0E3
+:104B1000170D801015FEBFE017FDBFE0170C8010C9
+:104B200015FFBFE017FFBFE01E070010040A0001D9
+:104B3000C082298015FFBFE017FFBFE01E020010F2
+:104B40003A8805000629000017FFBFE01501001094
+:104B500017FFBFE01701C01017FFBFE01500C0101E
+:104B600017FFBFE00400C5008D02C01017FFBFE0B3
+:104B700017FEFFE01704C0181503C01017FFBFE0B1
+:104B800017FEFFE01703C0181504C01017FEBFE0A2
+:104B90008B07C01017FFBFE00D05C01017FEBFE068
+:104BA0000B07C01017FFBFE08D05C01017FFBFE057
+:104BB0001506001017FFBFE01507001017FFBFE034
+:104BC0000414C0000508C01017FFBFE0450800101E
+:104BD00017FFBFE08D08001017FFBFE00D090010A0
+:104BE00017FFBFE08D09001017FFBFE03A8837E0DC
+:104BF0001701C0DF170000DF0402C0DE3A2800F80A
+:104C000004F2FFDE150DC0DF150C00DF040C00DF21
+:104C100015F73FE115F67FE115F5BFE115F4FFE16A
+:104C200015FD3FE017F7BFE02617001017F7BFE0AC
+:104C3000170D801017088010170B80103A88071086
+:104C400017F7BFE0170D801017088010170A8010A3
+:104C50003AC88518160A001017F7BFE0170D801024
+:104C600017088010170BC01017F7BFE0170D801042
+:104C700017088010170A80103AC88518060100002E
+:104C80003A88050015FDBFE0170280E01E260010DF
+:104C900004104001C400000100A7298015FCBFE0FA
+:104CA00017FCBFE026CE00104400800015FFBFE0D7
+:104CB00017FFBFE0040A80103A88071017FCBFE016
+:104CC0001502C01017FCBFE01703801015FBBFE0F2
+:104CD00017FCBFE0170180101701801017FBFFE0E1
+:104CE0002E0380187401020104B22A218017278044
+:104CF000040A800117F67FE117FB3FE1806B088013
+:104D000017FBBFE015F6BFE004048000150280E049
+:104D100017F7BFE0170D80101708801017058010D7
+:104D200015FEBFE006390000170380E015FCBFE068
+:104D300017FCBFE0170180100B088010CCFFBF10DC
+:104D4000180280101E0300108400800015FEBFE0D2
+:104D500006020000C400800015FEBFE017FCBFE0A3
+:104D6000170680103A880910C0CF298017FCBFE0D1
+:104D70001506001015FF3FE017FCBFE0040AC00055
+:104D80001502C01017F6BFE08B0580108DFABFE04A
+:104D900017F6BFE00B05C01017F6BFE08D05C01079
+:104DA00017F6BFE08BFAFFE00D05C01017FCBFE05F
+:104DB000170180100B088010CCFFBF101802801064
+:104DC0001E0A001017F6BFE01704801015F9BFE0A7
+:104DD00017F6BFE01703C01017F6BFE01504C010A8
+:104DE00017F6BFE017F9FFE01503C010170280E0C7
+:104DF0000C01801026050010B40182001784B81041
+:104E00004400C010B40182001584F81017F4BFE00C
+:104E10003AD6061017F4BFE03AD204100CC0BF1007
+:104E20003AB0861817F4BFE03A920410EC3F8010B5
+:104E30003AB0861817F4BFE03A9604103AB08618D4
+:104E400017F6BFE01506C01017F5BFE03AD60610FA
+:104E500017F5BFE03AD204100CC0BF103AB0861864
+:104E600017F5BFE03A920410EC3F80103AB0861874
+:104E700017F5BFE03A9604103AB0861817F6BFE06F
+:104E80001507C01017F6BFE00414C0000508C010D5
+:104E9000170280E03A88071017F6BFE04508C010F7
+:104EA00017FDBFE0CCFFBF103AD204103A880710BC
+:104EB00017FDBFE0CCFFBF103A9204103AB084183F
+:104EC0003A88071017F6BFE08D08C01017F6BFE04C
+:104ED0008D09001017FEBFE0980080101E3C0010E6
+:104EE00017F6BFE015F8BFE017FFBFE0040A801017
+:104EF0003A88071017F8BFE08D00C01017FCBFE01C
+:104F000017018010170180101764E0D03A88C5108F
+:104F100017F8FFE03604801817FCBFE017F8FFE031
+:104F20001503C0100612000017FCBFE01701801027
+:104F30001701C0101764A0D03A88091017FCBFE011
+:104F4000170180103A8807191503C0101703C01005
+:104F500017FCBFE01503C01017FCBFE0170380105B
+:104F6000040A800117F87FE13A880910807B0880E5
+:104F700017F7BFE01E03001017FC3FE1C0CF2980E8
+:104F80000615000017F7BFE0170D8010260C001063
+:104F900017F7BFE0170D80101708801026080010C3
+:104FA00017F7BFE0170D801017088010171F80102B
+:104FB0003A880B1017FC3FE180652A800606000046
+:104FC0003A880B0017FC3FE180652A80060200004A
+:104FD00040CD28803A8801003A880100060100008F
+:104FE0003A8801003A8837E01701C0DF170000DF78
+:104FF0000402C0DE3A2800F804FBFFDE1504C0DF1F
+:10500000150300DF040300DF15FD3FE10425000167
+:10501000C082298015FFBFE017FFBFE01E0200100D
+:105020003A8805000632000017FFBFE017FFFFE0D7
+:105030001501C01017FFBFE01701C01017FFBFE038
+:105040001500C01017FFBFE0046DC1000D0AC010AD
+:1050500017FFBFE00D0B001017FFBFE017FDFFE0CB
+:10506000150DC01017FFBFE01520001017FFBFE09F
+:105070000406C0001521C010040380008DFEBFE0AF
+:105080008FFEFFE017FFBFE01508C01017FFBFE05D
+:1050900017088010880080101E04001017FFBFE062
+:1050A0008400C0001508C0100607000017FFBFE00D
+:1050B00017088010502080101E03001017FFBFE05B
+:1050C0000420C0001508C01017FFBFE004DAC200BA
+:1050D000151BC01017FFBFE0D4FFFF00151CC01048
+:1050E00017FDBFE017FFFFE01509C01017FFBFE075
+:1050F0003A8837E01701C0DF170000DF0402C0DE86
+:105100003A2800F804FBFFDE1504C0DF150300DFBA
+:10511000040300DF15FE3FE115FD7FE117FEBFE050
+:10512000170D80101708801015FFBFE017FEBFE0B5
+:1051300017028010D00080101E0A001017FEBFE07A
+:105140001502001017FE3FE140893380B401820050
+:1051500017A7B8104400C010B401820015A7F810BA
+:1051600006050000B401820017A8B8104400C01062
+:10517000B401820015A8F81017FFBFE017FDFFE08B
+:105180001506C01017FE3FE1800E35803A8837E0E3
+:105190001701C0DF170000DF0402C0DE3A2800F864
+:1051A00004F9FFDE1506C0DF150500DF040500DF8A
+:1051B00015FB3FE117FBBFE0170D801015FEBFE0A8
+:1051C00017FEBFE01708801015FDBFE017FBBFE01A
+:1051D0001700801015FFBFE0060E000017FFBFE0AC
+:1051E0001700801015FFBFE017FFBFE01701801008
+:1051F0003A880910C0222A8015FCBFE017FFBFE0E3
+:10520000170180103A880910402C2A8017FC3FE1D2
+:10521000C0CF298017FFFFE017FBBFE01EEFBF18CC
+:1052200017FBBFE0170C80102604001017FBBFE02F
+:10523000170C80103A8809100086298017FB3FE17F
+:105240000086298017FEBFE01509001017FD3FE119
+:1052500040382F8017FE3FE1405B4080B401820060
+:1052600017A9B8104400C010B401820015A9F810A5
+:105270003A8805003A8837E01701C0DF170000DFE1
+:105280000402C0DE3A2800F804FDFFDE150200DF4C
+:10529000040200DF15FE3FE117FEBFE01709801092
+:1052A00015FFBFE017FFBFE02605001017FFBFE0A6
+:1052B0000B0A8010CCFFFF1017FFBFE0151BC010BA
+:1052C0003A8801003A8837E0170000DF0401C0DEA9
+:1052D0003A2800F804FCFFDE150300DF040300DFBA
+:1052E00015FE3FE115FD7FE117FEBFE0C400801011
+:1052F00015FEBFE015FF3FE0060B000017FEBFE004
+:10530000C4FFFF1015FEFFE017FDFFE00500C01011
+:1053100017FDBFE03AD2041015FDBFE017FFBFE054
+:105320004400801015FFBFE017FFBFE010018010A0
+:105330001EF23F1017FEBFE0440180103A8837E0AC
+:10534000170000DF0401C0DE3A2800F804FCFFDE8D
+:10535000150300DF040300DF15FD3FE115FE3FE00C
+:1053600015FF3FE0060E000017FEBFE03A92041062
+:1053700015FEBFE017FDBFE04400C01015FDFFE0C3
+:1053800003008010CC3F801017FEFFE03A8885189C
+:1053900015FEBFE017FFBFE04400801015FFBFE01F
+:1053A00017FFBFE0100180101EEF3F1017FEBFE097
+:1053B0003A8837E0170000DF0401C0DE3A2800F821
+:1053C00004F7FFDE1508C0DF150700DF040700DF64
+:1053D000171FA0D0FA9004101589A0D0B401820044
+:1053E0001771B81015FEBFE0067C000017FEBFE085
+:1053F0001700801015FDBFE017FEBFE08309801085
+:10540000CC3F80101C20801004E0BF10580080109A
+:105410001E42001017FEBFE01701801015FCBFE010
+:1054200017FCBFE02666001017FCBFE017008010D5
+:1054300015FBBFE017FEBFE01701801017098010B1
+:1054400015FABFE017FABFE0265F001015FF3FE036
+:10545000062A000017FAFFE017FFBFE0C400801023
+:10546000BA9004103A888518170080102620001082
+:1054700017FAFFE017FFBFE0C4008010BA900410D5
+:105480003A88851817008010C4FFFF1017FA3FE113
+:1054900017FFBFE0C4008010BA9004103A8885203E
+:1054A0001500C01017FAFFE017FFBFE0C40080101E
+:1054B000BA9004103A888518170080101E0C00104E
+:1054C00017FEBFE0C404C0001507C01017FFBFE0FF
+:1054D0003A880D103A880B0017FE3FE140A1358055
+:1054E00017FBBFE01701801017FCFFE01E38801883
+:1054F00017FFBFE04400801015FFBFE017FFBFE0BB
+:10550000100180101ED33F1017FABFE0171D801046
+:105510004400C01017FABFE0151DC01017FEBFE011
+:10552000040A801015F9BFE017F9BFE00B078010DF
+:10553000CCFFBF100C028010260A00100D8520D071
+:10554000048520D100BA278017F9BFE00B07C010EF
+:10555000C4FDBF003A7084183A88071017F9BFE0FD
+:105560000D07C01017FEBFE00412801015F9BFE050
+:1055700017F9BFE00B078010CCFFBF100C028010A2
+:10558000260A00100D8520D0048520D100BA27807E
+:1055900017F9BFE00B07C010C4FDBF003A708418B4
+:1055A0003A88071017F9BFE00D07C01017FEBFE0DB
+:1055B000040980103A88091000BA27800605000007
+:1055C0003A880100060300003A8801000601000045
+:1055D0003A88010017FDBFE015FEBFE017FEBFE0EF
+:1055E0001E823F10178AE0D0D49FBE003A888518EB
+:1055F000158AA0D0178AA0D02CC0BF102601001099
+:10560000158A20D03A8801003A8837E01701C0DFB8
+:10561000170000DF0402C0DE3A2800F804FDFFDEB8
+:10562000150200DF040200DF15FE3FE115FF3FE039
+:105630000609000017FEFFE017FFBFE0C40080105E
+:10564000BA9004103A8885181500001017FFBFE0C3
+:105650004400801015FFBFE017FFBFE0100180106D
+:105660001EF43F103A8801003A8837E0170000DF47
+:105670000401C0DE3A2800F804F8FFDE1507C0DF99
+:10568000150600DF040600DF15FD3FE115FC7FE194
+:1056900017FCBFE0600080101EAF001017FCBFE0D9
+:1056A000880080101E03001017FCBFE0261A0010AF
+:1056B0000600010017FCBFE0A00080101EB500101E
+:1056C00017FCBFE0D80080101EFA001017FDBFE0E5
+:1056D00017028010A00280101E0B001017FDBFE003
+:1056E000171D80101789E0D016078018171FA0D04B
+:1056F000CCFFFF101C00E0180400E01817FDBFE00D
+:105700001506C01006EB000017FD3FE1800E358046
+:1057100015FDBFE006E70000B40182001781B81054
+:105720004400C010B40182001581F81017FDBFE0DD
+:10573000170780104400C01017FDBFE01507C01008
+:1057400017FDBFE017078010500380101E0D0010DA
+:1057500017FDBFE00403C0001507C010B4018200AC
+:1057600017ADB8104400C010B401820015ADF81098
+:10577000041D400117FD3FE1C004358015FDBFE069
+:1057800006CC0000B401820017AEB8104400C0106F
+:10579000B401820015AEF81017FDBFE0172080108D
+:1057A000BAD0071017FDBFE0172180103A8885187E
+:1057B0007AD0051015FEBFE017FDBFE01707C01037
+:1057C000740182003A888518C30CB210CC3F801057
+:1057D00017FEFFE03A38851815FEBFE017FEBFE060
+:1057E000CCFFFF101C00E0180400E01817FDBFE01C
+:1057F0001508C01017FDBFE0170880108800801042
+:105800001E04001017FDBFE08400C0001508C01082
+:105810000607000017FDBFE0170880105020801019
+:105820001E03001017FDBFE00420C0001508C010C3
+:1058300017FDBFE01708C01017FDBFE01503C0102B
+:1058400017FDBFE017078010100180101E0F001019
+:1058500017FDBFE00B0B8010CCFFBF100C40801079
+:105860001E0A001017FDBFE01721C01017FDBFE092
+:1058700017208010BAD005103A88871817FDBFE0AE
+:105880001521C01017FDBFE01520001017FDBFE067
+:10589000170EC01017FDBFE0150FC01017FDBFE0B9
+:1058A000151E001017FDBFE0170D8010170880109F
+:1058B000170480100C0090101E24001017FDBFE08C
+:1058C0001714001117FDBFE0171BC0103A88052000
+:1058D0002E0180183A88051815FFBFE017FFBFE0BA
+:1058E0007AD0061017FDBFE00B0A8010CCFFBF1066
+:1058F0003A880B103A88091880FF0C8015FFBFE02A
+:1059000017FFBFE0A80080101E0200108400800076
+:1059100015FFBFE017FDBFE00B0A8010CCFFFF10A2
+:1059200017FDBFE0151BC01017FFBFE0CCFFFF1035
+:1059300017FDBFE00B0A8010CCFFBF103A38851866
+:105940003A88071017FDBFE0151CC01017FD3FE196
+:105950004089338006570000B401820017AFB810A9
+:105960004400C010B401820015AFF81017FD3FE1EC
+:105970000083348017FDBFE04400C000850AC010DA
+:1059800017FD3FE14089338017FDBFE0850A001015
+:1059900006480000B401820017B0B8104400C010DF
+:1059A000B401820015B0F81017FDBFE01702801097
+:1059B000080180102632001017FDBFE0170D80107F
+:1059C00017088010170480100C0280102625001084
+:1059D00017FDBFE017028010880180101E21001003
+:1059E00017FDBFE0171DC010171E20D11789A0D0CA
+:1059F0003A8885200E248018B401820017B1B810AF
+:105A00004400C010B401820015B1F81017FDBFE0CA
+:105A1000170CC01017FDBFE017168010C4FF3F1110
+:105A200017FDBFE0170E8010C4FFBF10150100D88E
+:105A3000150000D83A880F103A880D203A880B18C4
+:105A400017FD3FE180B43480171FA0D0CCFFFF10BA
+:105A50001C00E0180400E01817FDBFE01505C01099
+:105A600006140000171EA0D0CCFFFF101C00E01889
+:105A70000400E01817FDBFE01505C010060D00007A
+:105A80003A880100060100003A880100B401820052
+:105A900017B2B8104400C010B401820015B2F8105B
+:105AA000041D400117FD3FE1C004358015FDBFE036
+:105AB0003A88010017FDBFE03A8837E01701C0DFE0
+:105AC000170000DF0402C0DE3A2800F804F6FFDE0B
+:105AD0001509C0DF150800DF040800DF15FA3FE1F3
+:105AE00015F97FE115F8BFE115FE3FE017FABFE0B9
+:105AF0001707801015FDBFE017FABFE017018010EF
+:105B000015FCBFE017FCBFE01E04001017FDBFE04E
+:105B100026020010840580000695010017FCBFE0F6
+:105B20002604001017FCBFE01709801015FFBFE026
+:105B30000607000017FDBFE01E02001015FF3FE042
+:105B40000603000040CD28808405800006880100FF
+:105B500017FDBFE0280580101E6F011017FDBFE084
+:105B6000BA900610F40082003A88851817AF961094
+:105B70003A6800100C5B03086C5B0308945B030835
+:105B8000CC5B0308045C03084C5D0308405D03081C
+:105B9000F45D0308205E03082C5E0308885E03089A
+:105BA00060600308985E0308A45E03085C5F030856
+:105BB0002C6003083C600308345D03086060030840
+:105BC0004C60030817FCBFE026030010C41F8000D0
+:105BD00015FEBFE00665010017FA3FE1C00C3680F4
+:105BE00015FEBFE017FEBFE01E4F011017FABFE021
+:105BF000170480100C208010264D011017FABFE00A
+:105C00000B088010CCFFBF101C00A0100400A010D7
+:105C10001E47011017FABFE0041EC0000D08C01097
+:105C20000643010017FFBFE01702801090008010AC
+:105C30001E03001017FF3FE1401E3680064B010097
+:105C400017FF3FE1800E35800648010017FCBFE0DA
+:105C50001708801017058010980080101E0500108E
+:105C600017F87FE117FC3FE1C060408015FEBFE000
+:105C7000063E010040CD28808405800015FEBFE06F
+:105C8000063A010017FCBFE08B078010CCFFBF1065
+:105C90001E0400103A880B0017FC3FE1C0604080F2
+:105CA00015FEBFE017FEBFE01E23011017FFBFE087
+:105CB0004400C0001502C010061F010017FCBFE021
+:105CC0008B078010CCFFBF101E0600103A880B0017
+:105CD00017FC3FE1C060408015FEBFE017FEBFE04B
+:105CE0001E17011017F87FE117FC3FE1C0814080CB
+:105CF00015FEBFE017FEBFE01E13011017FF3FE1C6
+:105D000000A434803A88071017FFBFE0150CC010BC
+:105D100017FFBFE0170C80101E05001017FC3FE1B5
+:105D2000C09F4080441A800015FEBFE0060F0100AE
+:105D300017FA3FE180172F80B401820017A4B81032
+:105D40004400C010B401820015A4F81017FFBFE092
+:105D50008400C0001502C01017FFBFE08425C000FA
+:105D60001505C010178AE0D017FFBFE01513C0104B
+:105D7000178AE0D0D49FBE003A888518158AA0D033
+:105D800017FFBFE01713C01017FFBFE01510C010BA
+:105D900017FFBFE01710C01017FFBFE0151AC010A3
+:105DA00017FFBFE0171AC01017FFBFE0150FC01094
+:105DB00017FFBFE0170FC01017FFBFE0150EC01090
+:105DC00017FF3FE14089338015FEBFE017FEBFE0BB
+:105DD0001EDF0010B4018200177AB8104400C01012
+:105DE000B4018200157AF81006D90000C4178000AB
+:105DF00015FEBFE006DD000017FF3FE1401E3680C4
+:105E000006DA000017F8BFE01703801015FBBFE0AB
+:105E100017FABFE017058010980080101E0E0010C2
+:105E200017F8BFE00404C0001502C01017FBBFE064
+:105E30008400C0000D00C01017FCBFE00B07C010AD
+:105E400017FBBFE08D00C01017FBBFE017FCFFE0A1
+:105E50001703C0181501C01017FABFE0170580100E
+:105E6000A00080101E0B001017FABFE0170580106D
+:105E7000E00080101E07001017FABFE01705801021
+:105E80003A880B107401020104BB2A2180C70280EA
+:105E900040CD2880B4018200177BB8104400C010A8
+:105EA000B4018200157BF81006B0000017FA3FE13C
+:105EB000407F2F8017FF3FE1002B368015FFBFE0AA
+:105EC00017FFBFE026A4001017FF3FE14089338091
+:105ED00015FEBFE006A0000017FF3FE140893380B8
+:105EE00006A2000017FABFE0170180101E03001081
+:105EF0000408800015FEBFE0069C000017FABFE012
+:105F00000412801017F97FE13A880910C0AF2F8082
+:105F100017FF3FE14089338015FEBFE017FEBFE069
+:105F2000581A80101E8E001017FABFE0041280105D
+:105F300017F97FE13A880910802630800688000032
+:105F4000441C400117FF3FE1C00435800687000074
+:105F500040CD28803A8805000685000017FABFE08A
+:105F6000171A80101E05001017FABFE08B0880106A
+:105F7000CCFFBF100C1080102609001017FABFE0EC
+:105F8000170480100C4080101E05001017FFBFE0A2
+:105F900003248010CC3F80108C008010260300105A
+:105FA0008405800015FEBFE00670000017FFBFE00B
+:105FB00003248010CC3F80104C0080101E03001082
+:105FC000C402800015FEBFE00668000017F9BFE0BC
+:105FD0004400C0001502C01017F9BFE0170380107D
+:105FE00017FFFFE04324C0180500C01017F8BFE0FA
+:105FF0008C0080101E5C001017FFBFE0032480108F
+:10600000DC0080103A88071017FFBFE00524C0109D
+:106010000655000017FABFE0170180101E0300109C
+:106020000408800015FEBFE00650000017FABFE02C
+:10603000171380103A88071017FABFE01712801064
+:106040003AC885181605001017FABFE01713C010DC
+:1060500017FABFE0171280101E05801817F93FE1EC
+:10606000C0CF2980441A800015FEBFE0063F000023
+:1060700017FABFE00412801017F97FE13A8809107F
+:10608000C0AF2F8017FFBFE0170EC01017FABFE098
+:10609000171280103A88871817FFBFE01510C0103C
+:1060A00017FFBFE04400C000850AC01017FF3FE1A2
+:1060B0004089338015FEBFE017FEBFE0581A8010FC
+:1060C0001E05001017FABFE00412801017F97FE1D7
+:1060D0003A8809108026308017FFBFE0850A00103B
+:1060E0000622000017F87FE117FC3FE180A5408001
+:1060F000061E000017F87FE117FC3FE1C0AD4080AD
+:10610000061A000017F8BFE03A880B1017FF3FE1AE
+:10611000005C3580061500007401020104C32A21C9
+:1061200080172780061100003A880100060F000042
+:106130003A880100060D00003A880100060B0000B5
+:106140003A880100060900003A88010006070000AD
+:106150003A880100060500003A88010006030000A5
+:106160003A880100060100003A88010017FEBFE0EE
+:106170003A8837E01701C0DF170000DF0402C0DEF5
+:106180003A2800F804F9FFDE1506C0DF150500DF28
+:10619000040500DF15FB3FE117FBBFE0171380107C
+:1061A0002603001017FBBFE0170B80101E0B00101A
+:1061B0001720A0D01721E0D03A880D183A880B108C
+:1061C00017FB3FE1809D2F8015FFBFE017FFBFE069
+:1061D0002602001017FFBFE0062B0000B4014201A9
+:1061E0000499782917FB3FE1C052408015FFBFE0BA
+:1061F00017FFBFE02602001017FFBFE006220000D5
+:1062000017FBBFE01701801015FEBFE017FE3FE14E
+:1062100000F4348015FDBFE017FDBFE01E1700102D
+:1062200017FBBFE08B088010CCFFBF104C00801024
+:1062300015FCBFE017FBBFE08B08C01084FFBF0058
+:106240003A7084183A88071017FBBFE08D08C01019
+:1062500017FE3FE1405B408017FBBFE08B088010DA
+:1062600017FCFFE03AB0C4103A88071017FBBFE0F4
+:106270008D08C010441A80000603000017FDBFE01F
+:10628000150200103A8805003A8837E01701C0DF90
+:10629000170000DF0402C0DE3A2800F804FCFFDE2D
+:1062A0001503C0DF150200DF040200DF15FE3FE129
+:1062B00017FEBFE0170D80101708801015FFBFE014
+:1062C00017FEBFE017028010080180101E040010A6
+:1062D00017FE3FE1800E358015FEBFE0061C000072
+:1062E00017FFBFE0170480100C208010260B001051
+:1062F00017FFBFE00B088010CCFFBF101C00A010E0
+:106300000400A0101E0500103A880B0017FE3FE1A4
+:10631000C004358015FEBFE0060D000017FF3FE109
+:10632000C02E2F8017FFBFE0040A80103A880910A2
+:10633000C002308017FE3FE1002B368015FEBFE023
+:1063400017FEBFE02602001017FE3FE140893380B0
+:1063500017FEBFE03A8837E01701C0DF170000DF03
+:106360000402C0DE3A2800F804FDFFDE1502C0DF9B
+:10637000150100DF040100DF15FF3FE117FFBFE05B
+:1063800017028010A801C0101E190018BA9006103C
+:10639000F40082003A88851817BA98103A680010FD
+:1063A000006303080063030800630308186303081D
+:1063B000186303082863030817FFBFE015020010E5
+:1063C00017FF3FE1800E358015FFBFE00608000093
+:1063D00017FFBFE08401C0001502C01006040000D2
+:1063E00017FFBFE00402C0001502C0103A88010088
+:1063F00017FFBFE02609001017FFBFE0170280104B
+:10640000500280101E05001017FFBFE0170D80100E
+:10641000170880103A88091040382F8017FFBFE016
+:106420003A8837E01701C0DF170000DF0402C0DE42
+:106430003A2800F804FDFFDE1502C0DF150100DF79
+:10644000040100DF003B2A8015FFBFE017FFBFE01B
+:106450002602001017FFBFE0060100003A88050081
+:106460003A8837E01701C0DF170000DF0402C0DE02
+:106470003A2800F804FDFFDE150200DF040200DF09
+:1064800015FE3FE1179EA0D015FFBFE006090000F2
+:1064900017FFBFE01706801017FEFFE01E028018EE
+:1064A00017FFBFE00606000017FFBFE017008010CF
+:1064B00015FFBFE017FFBFE01EF53F103A8805004B
+:1064C0003A8837E0170000DF0401C0DE3A2800F800
+:1064D00004F5FFDE150AC0DF150900DF040900DF3F
+:1064E00015F83FE115F77FE117F7BFE015FFBFE0B3
+:1064F0003A88090080F3288017FFBFE0170AC01010
+:1065000017F8BFE0170480103A88871817FFBFE01C
+:10651000170B8010360480183A88090040FF288045
+:10652000441A8000064D00003A880B004400000128
+:1065300000A7298015FEBFE017FEBFE01E04001073
+:106540003A88090040FF2880441A80000643000072
+:1065500017FEBFE017F8FFE01501C01017F8BFE005
+:106560001703C01017FEBFE01503C01017F8BFE0F7
+:106570001704C01017FEBFE01502C01017F8BFE0E7
+:106580001701C01017FEBFE01504C01017F8BFE0D8
+:106590001702C01017FEBFE01505C01017F8BFE0C6
+:1065A0001707801015FABFE017F8BFE01703801037
+:1065B00004FEBF1015FDBFE017FDBFE00B0080100B
+:1065C000CCFFBF103AD204103A88071017FDBFE085
+:1065D0000B008010CCFFBF103A9204103AB0841820
+:1065E0008DF9BFE0840080000DF9BFE017FFBFE028
+:1065F000040A801004F9FFE017FEBFE13A880B1887
+:106600003A88091040C72F801E08001017FEBFE00F
+:106610001501001017FE3FE180BF29803A8809006C
+:1066200040FF2880441A8000060C000017FFBFE0DE
+:10663000040A80103A88091000BA278017FFBFE0CB
+:10664000040A80103A880B1017FF3FE1C0942F8096
+:106650003A88090040FF28803A8805003A8837E0E8
+:106660001701C0DF170000DF0402C0DE3A2800F87F
+:1066700004F8FFDE1507C0DF150600DF040600DFA3
+:1066800015FD3FE115FC7FE115FBBFE115FF3FE084
+:1066900017FDBFE01707801015FEBFE017FEBFE033
+:1066A000680480101E7A001017FEBFE0BA90061032
+:1066B000F40082003A888518178299103A68001011
+:1066C0004C660308D06603080C670308D867030804
+:1066D0000C670308D8670308CC670308D86703086A
+:1066E000CC6703084C670308D8670308D86703081A
+:1066F000D8670308D8670308D86703088C670308BE
+:106700008C67030840D93D803A88071017FDBFE029
+:106710001513C01017FDBFE01713C01017FDBFE021
+:10672000150BC01017FDBFE01705801098008010F2
+:106730001E0F00103A88090040FF288080C23D806B
+:10674000CCFFFF1017FDBFE0150080D8F400C20198
+:106750000406D9393A880D183A880B003A8809009E
+:106760004025408015FFBFE03A88090080F328806B
+:1067700017FFBFE01E0200108405800006450000E0
+:106780003A8805000643000017FD3FE1C03B368014
+:1067900015FFBFE017FFBFE01E0200108405800058
+:1067A000063C00003A88090040FF288017FF3FE1BF
+:1067B000404540803A88090080F328803A880500E7
+:1067C0000634000017FBBFE01E02001084058000A5
+:1067D0000630000017FDBFE01705801098008010FC
+:1067E0001E05001017FEBFE117FB7FE117FD3FE11B
+:1067F000007F36800627000040CD28808405800079
+:106800000624000017FCBFE01E0200108405800073
+:106810000620000017FDBFE01705801098008010CB
+:106820001E05001017FBBFE117FC7FE117FD3FE1DC
+:1068300000AC36800617000040CD2880840580001B
+:106840000614000017FBBFE01E0200108405800044
+:106850000610000017FDBFE017058010980080109B
+:106860001E05001017FEBFE117FB7FE117FD3FE19A
+:1068700040E336800607000040CD28808405800074
+:106880000604000040CD28803A880500060100007B
+:10689000C41780003A8837E01701C0DF170000DF17
+:1068A0000402C0DE3A2800F804F3FFDE150CC0DF56
+:1068B000150B00DF040B00DF15F73FE115F67FE154
+:1068C00015F5BFE117F6BFE01703801015FABFE01A
+:1068D00017FABFE01E0200108405800006A1000028
+:1068E00017F6BFE017028010200480101E0200106F
+:1068F00084058000069B000017F73FE1C03B36800F
+:1069000015F9BFE017F9BFE01E02001084058000F2
+:106910000694000017F5BFE0980080101E5200108A
+:1069200017FABFE08B008010CCFFBF101E0B0010C9
+:1069300017F9BFE08B018010CCFFBF1026040010B8
+:1069400017F9BFE08B0180108DFEBFE0060E00003E
+:1069500080C23D808DFEBFE0060B000017FABFE04D
+:106960008B008010CCFFBF103AD204103A88071079
+:1069700017FABFE08B008010CCFFBF103A920410D2
+:106980003AB084188DFEBFE017FABFE017018010FF
+:106990001E02001015FC3FE00616000017FABFE0CB
+:1069A0001701801015FCBFE0B401820017A6B610D5
+:1069B00015FBBFE00607000017FBBFE0170A8010B9
+:1069C00017FCFFE02606801817FBBFE017008010B9
+:1069D00015FBBFE017FBBFE01EF73F1006010000EC
+:1069E0003A88010017FBBFE01E020010441F800020
+:1069F000065C000017F7BFE0170480100C01801040
+:106A00001E120010179EA0D015FFBFE0060D00005B
+:106A100017FFBFE08B0180108BFEFFE0CCFFBF10A3
+:106A20001E05801817FFFFE017F9BFE02602801847
+:106A3000041C8000064B000017FFBFE01700801009
+:106A400015FFBFE017FFBFE01EF13F1017F9BFE0D1
+:106A50008BFEFFE08D01C01017F9BFE017FCFFE0CF
+:106A60001503C010063E000017FABFE08B0080102F
+:106A7000CCFFBF103AD204103A88071017FABFE0D3
+:106A80008B008010CCFFBF103A9204103AB08418EB
+:106A90008DF8BFE017FABFE0170180101E0200104A
+:106AA00015FD3FE00603000017FABFE01701801054
+:106AB00015FDBFE017FD3FE180023B8015FCBFE004
+:106AC00017FCBFE01E020010841C80000625000099
+:106AD00017F9BFE08B0180108DFEBFE08BFEBFE099
+:106AE0001E02001080C23D808DFEBFE017F9BFE09E
+:106AF00017FCFFE01503C01017F9BFE08BFEFFE0A5
+:106B00008D01C01017F9BFE017FDFFE01504C0109C
+:106B100017F9BFE08BF8FFE00D02C01017F7BFE0D8
+:106B20008B08C010C4FCBF003A7084183A88071064
+:106B300017F7BFE08D08C01017F7BFE08B08801073
+:106B4000940080103A88071017F7BFE08D08C01036
+:106B500017F7BFE0040A80103A880910C00230809D
+:106B60003A8805003A8837E01701C0DF170000DFD8
+:106B70000402C0DE3A2800F804F3FFDE150CC0DF83
+:106B8000150B00DF150A00DC040B00DF15F73FE1F1
+:106B900015F67FE115F5BFE117F73FE1C03B368001
+:106BA00015FBBFE017FBBFE01E04001017F63FE126
+:106BB00080BF2980C41B800006C6000017F5BFE017
+:106BC0001E0E001017F7BFE08B088010CCFFBF101F
+:106BD0008C0080102607001017FBBFE00B0280100E
+:106BE0008DFEBFE017FBBFE01704801015FDBFE06E
+:106BF000062800008405800006B6000017F5BFE0F7
+:106C000017028010200480101E03001040CD288041
+:106C10008405800006AF000017F5BFE01703801061
+:106C200015FABFE017FABFE01701801015FDBFE0AD
+:106C300017FABFE08B008010CCFFBF10260C0010AD
+:106C400017FABFE08B008010CCFFBF103AD20410BF
+:106C50003A88071017FABFE08B008010CCFFBF10F6
+:106C60003A9204103AB084188DFEBFE00609000085
+:106C700017FBBFE00B028010CCFFBF101E020010FC
+:106C8000840580000693000017FBBFE00B02801014
+:106C90008DFEBFE017F6BFE01702001440D93D801B
+:106CA0002E03001440CD2880841E80000689000039
+:106CB00017F6BFE0170280103A880B003A880910D7
+:106CC00080CD3D8015F9BFE017F9BFE01E0400102C
+:106CD00017F63FE180BF2980441A8000067D00003E
+:106CE00017F9BFE01703C01017F6BFE01703001134
+:106CF00017F6BFE0170280103A880D103A880B2073
+:106D00003A880918806B088017F6BFE01702C01098
+:106D100017F9BFE01504C01017F63FE180BF2980C6
+:106D200017F9BFE017FDFFE01507C01017FDBFE022
+:106D3000D8FFBF101E47001017FBBFE017038010DD
+:106D4000260F0010B401820017A6B61015FCBFE094
+:106D50000608000017FCBFE0170AC01017FBBFE0D1
+:106D600017038010261C801817FCBFE01700801046
+:106D700015FCBFE017FCBFE01EF63F10061900002F
+:106D8000B401820017A6B61015FCBFE0060F000084
+:106D900017FCBFE0172A80104C0080102608001056
+:106DA00017FCBFE0172780102605001017FCBFE076
+:106DB0001727801017068010580080102608001032
+:106DC00017FCBFE01700801015FCBFE017FCBFE008
+:106DD0001EEF3F10060300003A8801000601000084
+:106DE0003A88010017FCBFE01E170010B4018200B2
+:106DF00017A6B61015FCBFE0060B000017FCBFE09D
+:106E0000172780102605001017FCBFE017278010F9
+:106E100017068010580080102606001017FCBFE0EF
+:106E20001700801015FCBFE017FCBFE01EF33F10F9
+:106E3000060100003A88010017FCBFE01E020010A6
+:106E4000441F80000623000017F9BFE017FCFFE095
+:106E50001506C01017F7BFE01703801026040010B6
+:106E600017F7BFE01703C01017F9BFE0150BC010EC
+:106E700017F7BFE0171F80102604001017F7BFE0B8
+:106E8000171FC01017F9BFE0150CC0103A88090091
+:106E900040FF28808BFEFFE017FBBFE08B018010D6
+:106EA000CCFFBF1017F9BFE13A880B103A880918D8
+:106EB000008A3D8015F8BFE03A88090080F32880F9
+:106EC00017F8BFE00E02001017F8BFE0060100003F
+:106ED0003A88050004FFFFE61702C0DF170100DF54
+:106EE000170000DC0403C0DE3A2800F804F9FFDED6
+:106EF0001506C0DF150500DF040500DF15FD3FE1C5
+:106F000015FC7FE115FBBFE117FCBFE01703801004
+:106F100015FFBFE017FFBFE01E02001084058000D0
+:106F20000637000017FD3FE1C03B368015FEBFE08D
+:106F300017FEBFE01E02001084058000063000002E
+:106F400017FCBFE00404C0001502C01017FBBFE02F
+:106F5000D80380101E15001017FFBFE08400C0008A
+:106F60000D00C01017FEBFE08B018010CCFFBF10DA
+:106F70003AD204103A88071017FEBFE08B01801048
+:106F8000CCFFBF103A9204103AB084183A88071028
+:106F900017FFBFE08D00C01017FEBFE01703C01041
+:106FA00017FFBFE01501C0100614000017FFBFE077
+:106FB0008400C0000D00C01017FEBFE00B0280105F
+:106FC000CCFFBF103AD204103A88071017FEBFE07A
+:106FD0000B028010CCFFBF103A9204103AB0841814
+:106FE0003A88071017FFBFE08D00C01017FEBFE002
+:106FF0001704C01017FFBFE01501C0103A88050044
+:107000003A8837E01701C0DF170000DF0402C0DE56
+:107010003A2800F804FAFFDE1505C0DF150400DF8A
+:10702000040400DF15FC3FE1C400800015FEBFE052
+:1070300017FEFFE0F4038000049090103A388518A2
+:107040003A880B10F4BE000104203C2180FF0C8024
+:107050003A880B1034002001C4FF3F2180FF0C80D0
+:107060003A880B1017FC3FE180FF0C8015FDBFE054
+:1070700017FDBFE0262A001015FF3FE006170000AD
+:107080003400A000C4FFBF10C4FFBF101EFE3F109D
+:1070900017FEFFE0F4038000049090103A38851842
+:1070A0003A880B10F4BE000104203C2180FF0C80C4
+:1070B0003A880B1034002001C4FF3F2180FF0C8070
+:1070C0003A88071017FCBFE03AC8C51015FCBFE0AE
+:1070D00017FFBFE04400801015FFBFE017FFFFE07F
+:1070E00017FDBFE016E6BF1817FEFFE0F4038000AF
+:1070F000049090103A3885183A880B10F4BE0001BD
+:1071000004203C2180FF0C803A88071017FCBFE068
+:107110003A388518C4FFBF101EFE3F10060D000050
+:1071200017FEFFE0F4038000049090103A388518B1
+:107130003A880B10F4BE000104203C2180FF0C8033
+:107140003A88071017FCBFE03A388518C4FFBF1013
+:1071500016FEBF003A8805003A8837E01701C0DF05
+:10716000170000DF0402C0DE3A2800F804FEFFDE4C
+:107170001501C0DF150000DF3A8839D81727A0D0E5
+:10718000260300101727A0D03AE83E1006010000A1
+:107190000442A0D03A8837E01701C0DF170000DFB3
+:1071A0000402C0DE3A2800F804FBFFDE1504C0DF4D
+:1071B000150300DF040300DF15FD3FE117FDBFE00D
+:1071C0001606001017FDBFE02403C01074018200F2
+:1071D000041AB2103A888518060100003A880500A2
+:1071E00015FFBFE017FFBFE02619001017FFBFE033
+:1071F00017008010170480102606001017FFBFE04C
+:10720000170080101704801017FF3FE13AE83E1086
+:10721000060100003A88050015FEBFE017FD3FE1BA
+:1072200000E3378017FEBFE00E070010400B3780E9
+:107230003A88071017FEBFE03AC88500150080188D
+:10724000C4FFBF00060700003A88050006050000DD
+:10725000400B37803A8807104414800015008018CE
+:10726000C4FFBF003A8837E01701C0DF170000DF16
+:107270000402C0DE3A2800F804FBFFDE150400DF3C
+:10728000040400DF15FD3FE115FC7FE117FDFFE081
+:1072900017FCBFE03A88851815FEBFE017FDBFE078
+:1072A00015FFBFE00605000017FFBFE01B00001040
+:1072B00017FFBFE00408801015FFBFE017FFFFE0D5
+:1072C00017FEBFE036F8BF1817FDBFE0CC078010EF
+:1072D0002602001017FFBFE01B0000103A880100D3
+:1072E0003A8837E0170000DF0401C0DE3A2800F8D2
+:1072F00004FCFFDE150300DF040300DF15FF3FE1A0
+:1073000015FE7FE115FDBFE117FDBFE03A8837E0CC
+:10731000170000DF0401C0DE3A2800F804FEFFDE9B
+:107320001501C0DF150000DF3A8839D81727A0D033
+:10733000260300101727A0D03AE83E1006010000EF
+:107340000442A0D03A8837E01701C0DF170000DF01
+:107350000402C0DE3A2800F804FAFFDE1505C0DF9B
+:10736000150400DF040400DF15FD3FE115FC7FE19B
+:1073700017FDBFE02603001017FDBFE017028010C5
+:107380001E060010402637803A88071084058000CA
+:107390001500801884FABF000613000017FDBFE037
+:1073A00017FCFFE015FFFFE015FEBFE017FEBFE092
+:1073B00017FFFFE01501C01017FFBFE01700C01056
+:1073C00017FEBFE01500C01017FFBFE017008010C8
+:1073D00017FEFFE01501C01017FFBFE017FEFFE02A
+:1073E0001500C0103A8805003A8837E01701C0DF61
+:1073F000170000DF0402C0DE3A2800F804FDFFDEBB
+:107400001502C0DF150100DF040100DF3401820036
+:1074100004699A1015FFBFE00606000017FFBFE0E1
+:10742000170080103AE83E1017FFBFE004FFBF10BE
+:1074300015FFBFE017FFFFE034018200046A9A10D5
+:107440002EF6BF183A8801003A8837E01701C0DFEE
+:10745000170000DF0402C0DE3A2800F804FDFFDE5A
+:107460001502C0DF150100DF040100DF34018200D6
+:1074700004699A1015FFBFE00606000017FFBFE081
+:10748000170080103AE83E1017FFBFE004FFBF105E
+:1074900015FFBFE017FFFFE034018200046A9A1075
+:1074A0002EF6BF183A8801003A8837E01701C0DF8E
+:1074B000170000DF0402C0DE3A2800F804FAFFDEFD
+:1074C0001505C0DF150400DF040400DF15FD3FE1F2
+:1074D00015FC7FE117FCBFE01700801015FFBFE02F
+:1074E00017FD3FE1C0DA02804400801015FEBFE0C6
+:1074F000060D000017FFBFE01702801017FEFFE027
+:107500003A880D1817FD7FE13A88091080CB428038
+:107510001E02001017FFBFE00607000017FFBFE0C4
+:107520001700801015FFBFE017FFFFE017FCBFE05A
+:107530001EF0BF183A8805003A8837E01701C0DF0F
+:10754000170000DF0402C0DE3A2800F804F9FFDE6D
+:107550001506C0DF150500DF040500DF15FF3FE15C
+:1075600015FE7FE115FDBFE115FCFFE1170280E08C
+:10757000150080D817FCFFE117FDBFE117FE7FE182
+:1075800017FF3FE1406437803A8837E01701C0DFDA
+:10759000170000DF0402C0DE3A2800F804F9FFDE1D
+:1075A000150600DF040600DF15FB3FE115FA7FE159
+:1075B00017FABFE015FFBFE03A30050015FEBFE047
+:1075C00017FEFFE084FFBF003A7084183A70011084
+:1075D00017FEBFE015FDBFE04400C00017FFBFE08D
+:1075E0003A9884183A880710178CA0D03AB08418BB
+:1075F000158CA0D0178CA0D0FA70011017FDBFE039
+:1076000015FCBFE017FCBFE03A7001103A88050096
+:107610003A8801003A8837E0170000DF0401C0DE35
+:107620003A2800F804F9FFDE150600DF040600DF43
+:1076300015FB3FE115FA7FE117FABFE015FFBFE048
+:107640003A30050015FEBFE017FEFFE084FFBF00E3
+:107650003A7084183A70011017FEBFE015FDBFE0C4
+:107660004400C00017FFBFE03A9884183A30840005
+:107670003A880710178CA0D03A708418158CA0D0C7
+:10768000178CA0D0FA70011017FDBFE015FCBFE009
+:1076900017FCBFE03A7001103A8805003A880100F3
+:1076A0003A8837E0170000DF0401C0DE3A2800F80E
+:1076B00004FCFFDE150300DF040300DF15FE3FE1DD
+:1076C00015FD7FE1FA30050015FFBFE04400C00062
+:1076D00017FDBFE03A9884183A88071017FFBFE0FB
+:1076E0003A7084183AC00410CC3F80103A8837E0D2
+:1076F000170000DF0401C0DE3A2800F804F5FFDEC1
+:10770000150AC0DF150900DF040900DF15FA3FE1A3
+:1077100015F97FE115F8BFE115F7FFE184FABF0025
+:1077200015FFBFE017F9BFE015FEBFE017FEBFE091
+:10773000080880101E2400103A30050015FCBFE038
+:1077400017FCFFE084FFBF003A7084183A70011004
+:1077500017FCBFE015FDBFE017FEBFE0FA90081070
+:1077600017F8FFE0B40182003A88852015DCF81094
+:1077700017FEBFE0FA90081017F7FFE0B40182008F
+:107780003A88852015DDF81017F8BFE026050010AF
+:1077900017FEBFE03A880B1017FA3FE1404E3780E2
+:1077A0000604000017FEBFE03A880B1017FA3FE10D
+:1077B000C056378015FFBFE017FDBFE015FBBFE0E7
+:1077C00017FBBFE03A70011017FFBFE03A8837E0BF
+:1077D0001701C0DF170000DF0402C0DE3A2800F8FE
+:1077E00004F9FFDE1506C0DF150500DF040500DF24
+:1077F00015FE3FE115FD7FE115FCBFE115FBFFE143
+:1078000017FBBFE117FC7FE117FD3FE18094378054
+:1078100015FFBFE017FFBFE01617001017FFBFE00E
+:107820002403C010740182003A888518171AF210D8
+:1078300017FEBFE01500C01017FFBFE02403C01003
+:10784000740182003A888518171BF21017FEBFE0FA
+:107850001501C01017FFBFE02403C010740182009F
+:107860003A888518171CF21017FEBFE01502C010E9
+:1078700017FF3FE100E337803A8801003A8837E09C
+:107880001701C0DF170000DF0402C0DE3A2800F84D
+:1078900004FBFFDE1504C0DF150300DF040300DF77
+:1078A00015FF3FE115FE7FE115FDBFE1C47FC0017B
+:1078B0004400800117FF7FE174010201041D3221A1
+:1078C00080723780C47FC0013A880D0017FE7FE1C7
+:1078D00074010201041A322180723780C47FC00112
+:1078E0004400800117FD7FE1740102010420322170
+:1078F000807237803A8801003A8837E01701C0DF8C
+:10790000170000DF0402C0DE3A2800F804FEFFDEA4
+:107910001501C0DF150000DF3A8839D81727A0D03D
+:10792000260300101727A0D03AE83E1006010000F9
+:107930000442A0D03A8837E01701C0DF170000DF0B
+:107940000402C0DE3A2800F804FDFFDE150200DF65
+:10795000040200DF15FE3FE117FEBFE017028010B2
+:107960003400D01017FEBFE01502C01015FF3FE035
+:10797000061A000017FFBFE02403C0107401820044
+:107980003A888518171AF21017FEBFE0170080100A
+:107990001E0F801817FFBFE02403C010740182007F
+:1079A0003A888518171CB2100E09001017FFBFE0A7
+:1079B0002403C01074018200041AB2103A8885189A
+:1079C00017FEFFE026028018C4FCBF000608000076
+:1079D00017FFBFE04400801015FFBFE01726A0D0BE
+:1079E0003A88071017FFBFE02EE2BF183A8805005B
+:1079F0003A8837E0170000DF0401C0DE3A2800F8BB
+:107A000004F6FFDE1509C0DF150800DF040800DFFB
+:107A100015FA3FE115F97FE115F8BFE1C4FFBF009A
+:107A200015FEBFE044FBBF0015FDBFE015FC3FE0C5
+:107A3000042460D117FA3FE14040378015FFBFE0D2
+:107A400017FFBFE01E05001017FA3FE1808142805A
+:107A500015FFBFE04400800015FCBFE017FFBFE04A
+:107A60002629001017FF3FE10092428015FEBFE07B
+:107A700017FEBFE00E03001017FEBFE015FDBFE0CC
+:107A80000623000017FEBFE02403C010740182002B
+:107A9000041AB2103A88851815FBBFE017F9FFE009
+:107AA00034009000C4FFBF103A70861817FBBFE087
+:107AB0001502C01017FCBFE01E05001017FB3FE1C8
+:107AC0000089378015FDBFE017FDBFE016100010DC
+:107AD00017FFBFE0170380102608001017FFBFE054
+:107AE0001703801017F8FFE117F9BFE117FA7FE1DC
+:107AF00017FB3FE13AE83E10060100003A88050016
+:107B000015FDBFE00602000044FBBF0015FDBFE00D
+:107B100017FDBFE00E09001017FE3FE100E33780BC
+:107B2000408537803A88071017FDBFE03AC88500C6
+:107B300015008018C4FFBF000601000017FEBFE05B
+:107B40003A8837E01701C0DF170000DF0402C0DE0B
+:107B50003A2800F804F2FFDE150AC0DF150900DF3D
+:107B6000040900DF15F73FE1150240E1150380E14C
+:107B70001504C0E1040280E015F8BFE017F7BFE08C
+:107B800015FFBFE0066F0000C7FEBFE06009801070
+:107B90001E040010C7FEBFE03A88091080CC378071
+:107BA0000668000017FFBFE04400C01015FFFFE0AB
+:107BB00003008010C5FEBFE0C7FEBFE026690010CD
+:107BC000C7FEBFE0580980101E040010C7FEBFE0CA
+:107BD0003A88091080CC3780065A0000C7FEBFE003
+:107BE000D81880101E08001017F8BFE00401C0105C
+:107BF00015F8FFE01700801015FBBFE017FB3FE111
+:107C000080CC3780064F0000C7FEBFE0181E8010F2
+:107C10001E34001017F8BFE00401C01015F8FFE093
+:107C20001700801015FABFE017FABFE01E0300101E
+:107C3000040C000180CC378006420000040780005D
+:107C400015FDBFE00603000017FDBFE004FFBF10F5
+:107C500015FDBFE0C403C00017FDBFE03A988418CB
+:107C60003A88071017FABFE03A70841826F63F10DA
+:107C700006190000C403C00017FDBFE03A9884183D
+:107C80003A88071017FABFE03A70861817FDBFE070
+:107C90003AD8841815F9BFE017F9BFE0A8028010A0
+:107CA0001E04001017F9BFE0040C8010C5FEBFE0F1
+:107CB0000603000017F9BFE0C4158010C5FEBFE041
+:107CC000C7FEBFE03A88091080CC378017FDBFE0BF
+:107CD00004FFBF1015FDBFE017FDBFE00EE53F102C
+:107CE00006180000C7FEBFE0D81C80101E1500104B
+:107CF00017F8BFE00401C01015F8FFE0170080106E
+:107D000015FCBFE00609000017FCBFE04400C010EE
+:107D100015FCFFE003008010CC3F80101C20801079
+:107D200004E0BF103A88091080CC378017FCBFE010
+:107D300003008010CC3F80101C20801004E0BF1096
+:107D40001EF13F1017FFBFE04400C01015FFFFE019
+:107D500003008010C5FEBFE0C7FEBFE01E8A3F10D3
+:107D6000060100003A8801003A8801003A8837E0AD
+:107D70001701C0DF170000DF0405C0DE3A2800F855
+:107D800004FDFFDE1502C0DF150100DF040100DF86
+:107D900015FF3FE117FF3FE180CB02803A8837E0D3
+:107DA0001701C0DF170000DF0402C0DE3A2800F828
+:107DB00004FEFFDE1501C0DF150000DF3A8839D868
+:107DC0001727A0D0260300101727A0D03AE83E10AE
+:107DD000060100000442A0D03A8837E01701C0DF56
+:107DE000170000DF0402C0DE3A2800F804F9FFDEC5
+:107DF0001506C0DF150500DF040500DF15FD3FE1B6
+:107E000015FC7FE115FBBFE117FDBFE01606001072
+:107E100017FDBFE02403C01074018200041AB210E1
+:107E20003A888518060100003A88050015FFBFE072
+:107E300017FFBFE02622001017FFBFE017028010D7
+:107E4000CC008010600080101E18001017FFBFE0EB
+:107E500017008010170580102614001017FFBFE0D0
+:107E6000170080101705801017FBFFE03A880D18E7
+:107E700017FC7FE117FF3FE13AE83E1015FEBFE037
+:107E800017FEBFE00E07001080CF37803A8807103A
+:107E900017FEBFE03AC8850015008018C4FFBF0078
+:107EA000060C000017FEBFE0060A000080CF3780F6
+:107EB0003A8807104403800015008018060400006B
+:107EC00080CF37803A88071044148000150080184E
+:107ED000C4FFBF003A8837E01701C0DF170000DF9A
+:107EE0000402C0DE3A2800F804FEFFDE150100DFC0
+:107EF000040100DF15FF3FE117FFBFE0D000801055
+:107F00001E0A001017FFBFE02403C0107401820096
+:107F10003A888518151C321017FFBFE02403C010E3
+:107F2000740182003A888518151A32103A880100C7
+:107F30003A8837E0170000DF0401C0DE3A2800F875
+:107F400004FDFFDE150200DF040200DF15FF3FE144
+:107F500015FE7FE117FFFFE03400A000C4FFBF1053
+:107F60003A7084183A8837E0170000DF0401C0DE59
+:107F70003A2800F804FAFFDE150500DF040500DFEB
+:107F800015FB3FE13A30050015FCBFE017FCFFE0B0
+:107F900084FFBF003A7084183A70011017FCBFE0EC
+:107FA00015FFBFE017FBBFE015FDBFE017FDBFE009
+:107FB0001700801017FDFFE01701C0181501C01051
+:107FC00017FDBFE01701801017FDFFE01700C01874
+:107FD0001500C01017FDBFE017FDFFE01501C01030
+:107FE00017FDBFE017FDFFE01500C01017FFBFE051
+:107FF00015FEBFE017FEBFE03A7001103A8801009D
+:108000003A8837E0170000DF0401C0DE3A2800F8A4
+:1080100004FBFFDE1504C0DF150300DF040300DFEF
+:108020001729A0D015FFBFE0178EA0D04400801004
+:10803000158EA0D0062E000017FFBFE0170080109D
+:1080400015FEBFE017FFBFE003048010CC3F801097
+:1080500026040010178EA0D01E02001017FFBFE0EC
+:108060000504001017FFBFE017028010178EE0D044
+:10807000361D801817FFBFE003048010CC3F80102E
+:108080001E19001017FFBFE01703801017FFFFE055
+:108090001705C0183A8809183AE83E1015FDBFE0E8
+:1080A00017FDBFE01E03001017FF3FE1C0EB378054
+:1080B000060D000017FFBFE01702C01017FDBFE05C
+:1080C0003A88871817FFBFE01502C01017FFBFE0FE
+:1080D0001702C010178EA0D02E03801817FFBFE024
+:1080E0004400C0000504C01017FEBFE015FFBFE04C
+:1080F00017FFFFE00429A0D01ECFBF1880AD10806D
+:108100003A8801003A8837E01701C0DF170000DF26
+:108110000402C0DE3A2800F804FDFFDE1502C0DFCD
+:10812000150100DF040100DF15FF3FE117FFFFE04D
+:108130003400A000C4FFBF103A7084183A880910B8
+:1081400080CA42803A8801003A8837E01701C0DFD0
+:10815000170000DF0402C0DE3A2800F804FAFFDE50
+:108160001505C0DF150400DF040400DF15FC3FE146
+:1081700017FCBFE0C40780107AD1041015FFBFE0E0
+:1081800017FFBFE07A91041015FEBFE017FE7FE1F4
+:108190000408000100AF428015FDBFE017FDBFE0FD
+:1081A0001E0200103A8805000605000017FE7FE158
+:1081B00017FD3FE1001C378017FDBFE03400A01021
+:1081C0003A8837E01701C0DF170000DF0402C0DE85
+:1081D0003A2800F804FAFFDE1505C0DF150400DFB9
+:1081E000150300DC040400DF15FC3FE1434BA0D085
+:1081F000CC3F80101E03001017FC3FE1C0F5368015
+:1082000006330000178DA0D015FDBFE017FCBFE0BE
+:10821000F4034001049050293A88091080FF0C8033
+:108220003A88071017FDBFE03A38A11817FCBFE0E5
+:10823000F4034001049050293A880910C0050D80CC
+:108240003A88071017FDBFE03A388518F40340015B
+:10825000049050293A88091080FF0C803A88858064
+:1082600015FEBFE006070000D4FF3F01C0301780B5
+:1082700017FEFFE0F4FFBF00440080103A88851825
+:1082800015FEBFE017FEBFE0D4FFFF0036F6BF18B3
+:1082900017FEBFE0CCFFBF103A880910C03017802E
+:1082A00017FD7FE1F40300010490102180FF0C8092
+:1082B0003A88071017FCBFE03A880B183A88091073
+:1082C000C0050D803A880910C0F536803A8805004F
+:1082D00004FFFFE61702C0DF170100DF170000DC14
+:1082E0000403C0DE3A2800F804FEFFDE1501C0DFFB
+:1082F000150000DF3A8839D81727A0D026030010D0
+:108300001727A0D03AE83E10060100000442A0D092
+:108310003A8837E01701C0DF170000DF0402C0DE33
+:108320003A2800F804F9FFDE1506C0DF150500DF66
+:10833000040500DF15FD3FE115FC7FE115FBBFE102
+:1083400017FDBFE01606001017FDBFE02403C010A4
+:1083500074018200041AB2103A88851806010000E0
+:108360003A88050015FFBFE017FFBFE02621001087
+:1083700017FFBFE017028010CC00801026180010F5
+:1083800017FFBFE01700801017068010261400109A
+:1083900017FFBFE0170080101706801017FBFFE0E3
+:1083A0003A880D1817FC7FE117FF3FE13AE83E10CD
+:1083B00015FEBFE017FEBFE00E0700100023388057
+:1083C0003A88071017FEBFE03AC8850015008018EC
+:1083D000C4FFBF00060C000017FEBFE0060A000045
+:1083E000002338803A880710440380001500801865
+:1083F00006040000002338803A88071044148000E7
+:1084000015008018C4FFBF003A8837E01701C0DFAD
+:10841000170000DF0402C0DE3A2800F804FFFFDE88
+:10842000150000DF3A8839D8FA7001003A88010057
+:108430003A8837E0170000DF0401C0DE3A2800F870
+:1084400004F5FFDE1701E0D0175820D11500C0DF7A
+:10845000150100DF1502C0DD150380DD150440DDC8
+:10846000150500DD1506C0DC150780DC150840DCAD
+:10847000150900DC150AC0D81500C026C05E38807A
+:10848000175320D1074D60D1155820D1454D60D1EB
+:108490001700C026170AC0D81700C0DF170100DF79
+:1084A0001702C0DD170380DD170440DD170500DD6E
+:1084B0001706C0DC170780DC170840DC170900DC52
+:1084C0001501E0D0040BC0DE3A2800F83A30250050
+:1084D00084FF7F043A7064943A700190C05E3880E3
+:1084E00044008004454BA0D406E53F000400C006CC
+:1084F0003A300500540080103A700110170180D8FE
+:10850000170000D90402C0DE3AE83E103A880100A4
+:1085100004F7FFDE1508C0DF150700DF040700DFE2
+:1085200015FC3FE115FB7FE115FABFE13A880538FC
+:108530000DF9BFE017FAFFE004FFBF003A7084189E
+:1085400004F7BE1015FFBFE0040981013A880B0053
+:1085500017FF3FE1408E088017FFBFE004BBC0104B
+:1085600017FFBFE01501C01017FFBFE004D5C01012
+:1085700017FFBFE01502C01017FFBFE004EFC010E7
+:1085800017FFBFE01503C01017FFBFE04400C00095
+:108590001529C010152A001017FFBFE084C3CC00B6
+:1085A0000D2BC01017FFBFE044F3EA008D2BC01065
+:1085B00017FFBFE0048DC4000D2CC01017FFBFE0F3
+:1085C000449BF9008D2CC01017FFBFE004BBF700DF
+:1085D0000D2DC01017FFBFE04401C0008D2DC0104D
+:1085E00017FFBFE0C402C0000D2EC01017FFBFE090
+:1085F00015FEBFE017FEBFE004F3BF1015FDBFE09E
+:1086000017FDBFE0040C801017FCFFE01500C01040
+:1086100017FDBFE0040B801017FBFFE01500C01032
+:1086200017FDBFE0040A801017FFFFE01500C0101F
+:1086300034018200040DA1100401C01017FDBFE039
+:108640001500C01017FDBFE03A8837E01701C0DF02
+:10865000170000DF0402C0DE3A2800F804FEFFDE47
+:10866000150100DF040100DF15FF3FE13A8801003A
+:108670003A8837E0170000DF0401C0DE3A2800F82E
+:1086800004FEFFDE150100DF040100DF15FF3FE1FE
+:108690003A8801003A8837E0170000DF0401C0DEA5
+:1086A0003A2800F804FFFFDE150000DF3A8839D8C9
+:1086B0003A8801003A8837E0170000DF0401C0DE85
+:1086C0003A2800F804FFFFDE150000DF3A8839D8A9
+:1086D0003A8801003A8837E0170000DF0401C0DE65
+:1086E0003A2800F804FEFFDE1501C0DF150000DFA8
+:1086F0003A8839D880E328803A8801003A8837E000
+:108700001701C0DF170000DF0402C0DE3A2800F8BE
+:1087100004FFFFDE150000DF3A8839D83A880100EF
+:108720003A8837E0170000DF0401C0DE3A2800F87D
+:1087300004FFFFDE150000DF3A8839D83A880100CF
+:108740003A8837E0170000DF0401C0DE3A2800F85D
+:1087500004FFFFDE150000DF3A8839D83A880100AF
+:108760003A8837E0170000DF0401C0DE3A2800F83D
+:1087700004FEFFDE150100DF040100DF15FF3FE10D
+:108780003A8801003A8837E0170000DF0401C0DEB4
+:108790003A2800F804FBFFDE1504C0DF150300DFF4
+:1087A000150200DC040300DF15FE3FE0172BA0D00C
+:1087B0003A880910C0D902807401020104D42A2128
+:1087C000C0D90280C059298015FDBFE017FDBFE068
+:1087D0002602001017FD3FE18017278000F8248053
+:1087E00015FDBFE017FDBFE02607001017FD7FE174
+:1087F0007401020104E62A2180C70280740102018B
+:1088000004EC2A218017278080593F8080EF3E802A
+:10881000156620D0B401820017A6B610040100141A
+:10882000B401820017A6B610170A80103A88091002
+:10883000C0FB26803A880D103A880B807401020133
+:1088400004ED2A2180C70280805E298015FDBFE0EB
+:1088500017FDBFE02602001017FD3FE180172780BB
+:108860003A88010004FFFFE61702C0DF170100DFAE
+:10887000170000DC0403C0DE3A2800F804FBFFDE2A
+:108880001504C0DF150300DF150200DC040300DF60
+:1088900015FE3FE115FD7FE117FDBFE003008010ED
+:1088A000CC3F80101C20801004E0BF10BA9006104E
+:1088B000740182003A888518174A321417FEBFE007
+:1088C000170780103A880910C0FB26803A880D10DF
+:1088D0003A880B807401020104FD2A2180C70280BE
+:1088E000172CA0D03A88091080C702803A8801006E
+:1088F00004FFFFE61702C0DF170100DF170000DCEE
+:108900000403C0DE3A2800F804F9FFDE1506C0DFD4
+:10891000150500DF150400DC040500DF15FC3FE150
+:1089200015FE3FE0B401820017A6B61015FDBFE0AA
+:108930000625000017FDBFE00401001417FDBFE08D
+:10894000170A80103A880910C0FB2680150080D8CD
+:108950003A880F8017FEBFE17401420104066B29BB
+:1089600017FC3FE10039278017FDBFE0170C80108E
+:108970003A880910C0FB26803A880D107401420124
+:10898000040D6B2917FC3FE10039278017FDBFE07C
+:10899000170D80103A880910C0FB26803A880D1008
+:1089A0007401420104106B2917FC3FE10039278054
+:1089B00017FDBFE01700801015FDBFE017FEBFE0F8
+:1089C0004400801015FEBFE017FDBFE01ED93F1028
+:1089D000177DA0D03A880D107401420104136B2951
+:1089E00017FC3FE100392780172DE0D0172DA0D0CC
+:1089F000A40280103A880F103A880D1874014201C1
+:108A000004196B2917FC3FE100392780178FA0D08C
+:108A10003A880910C0FB26803A880D107401420183
+:108A200004256B2917FC3FE100392780172EA0D0C1
+:108A30003A880D1074014201042C6B2917FC3FE1A8
+:108A40000039278017FC3FE1C0E538803A880500EF
+:108A500004FFFFE61702C0DF170100DF170000DC8C
+:108A60000403C0DE3A2800F804FEFFDE1501C0DF73
+:108A7000150000DF3A8839D8177DA0D004194001CD
+:108A80003A88091080FF0C80241980103A8837E05A
+:108A90001701C0DF170000DF0402C0DE3A2800F82B
+:108AA00004FEFFDE1501C0DF150000DF3A8839D86B
+:108AB0001790A0D01E0800101790A0D0440080107E
+:108AC0001590A0D0409C24801790A0D0C4FFBF1068
+:108AD0001590A0D0060100003A8801003A8837E0DE
+:108AE0001701C0DF170000DF0402C0DE3A2800F8DB
+:108AF00004FEFFDE150100DF040100DF15FF3FE18A
+:108B00003A8805003A8837E0170000DF0401C0DE2C
+:108B10003A2800F804FDFFDE1502C0DF150100DF72
+:108B2000040100DF15FF3FE04069428015FFBFE010
+:108B300017FFBFE0260600107401020104342B2148
+:108B4000C0D9028074010201043A2B2180172780CA
+:108B50003A8805003A8837E01701C0DF170000DFC8
+:108B60000402C0DE3A2800F804FEFFDE1501C0DF73
+:108B7000150000DF3A8839D800052B8080B2388094
+:108B8000176AE0D0177DA0D02E018018C04E258036
+:108B90001791E0D0177DA0D036048018177DA0D0A3
+:108BA00004FAC0101791A0D02E078018177DA0D00E
+:108BB000041980101591A0D01792A0D026020010A1
+:108BC0001792A0D03AE83E103A8801003A8837E080
+:108BD0001701C0DF170000DF0402C0DE3A2800F8EA
+:108BE00004FCFFDE1503C0DF150200DF040200DF16
+:108BF00015FE3FE01793A0D00E46800015FF3FE022
+:108C0000063F000017FFBFE02405C010B40182003A
+:108C10003A888518171CB9102636001017FFBFE0D8
+:108C20002405C010B40182003A888518171FF91076
+:108C3000177DA0D02E29801817FFBFE02405C01093
+:108C4000B40182003A8885181720B9101E2300103D
+:108C500017FFBFE02405C010B40182003A888518D0
+:108C6000171EF910177DA0D03A88871817FFBFE0AC
+:108C700024050011B40182003A888520151FF910DF
+:108C800017FFBFE0240500114400C000B4018200BA
+:108C90003A8885201520F91017FFBFE02405C01081
+:108CA000B40182003A888518171CF91017FFBFE03D
+:108CB00024050011B40182003A888520171DB910DF
+:108CC0003A8809103AE83E1817FFBFE02405C010A3
+:108CD000B40182003A8885181520391017FEBFE0CC
+:108CE0004400801015FEBFE01793A0D017FEFFE0F0
+:108CF0000E07801817FFBFE04400801015FFBFE08B
+:108D000017FFBFE0500180101EBE3F10060100009B
+:108D10003A8801003A8801003A8837E01701C0DF3D
+:108D2000170000DF0402C0DE3A2800F804FAFFDE74
+:108D30001505C0DF150400DF040400DF15FE3FE168
+:108D400015FD7FE115FCBFE115FF3FE0063900008E
+:108D500017FFBFE02405C010B40182003A888518CF
+:108D6000171CB9101E30001017FFBFE024050011BA
+:108D700017FEFFE0B40182003A888520151CF91027
+:108D800017FFBFE02405001117FCFFE0B4018200CB
+:108D90003A888520151DF91017FDBFE084024001B7
+:108DA0003A88091000F00C803A88091017FFBFE0DC
+:108DB0002405C010B40182003A888518151E3911A7
+:108DC00017FFBFE02405C010B40182003A8885185F
+:108DD000171EF910177DA0D03A88871817FFBFE03B
+:108DE00024050011B40182003A888520151FF9106E
+:108DF00017FFBFE02405C010B40182003A8885182F
+:108E0000152039101793A0D0440080101593A0D0DE
+:108E100017FFBFE02405C010B4018200041CB91084
+:108E20003A8885180607000017FFBFE0440080104D
+:108E300015FFBFE017FFBFE0500180101EC43F10B8
+:108E40003A8805003A8837E01701C0DF170000DFD5
+:108E50000402C0DE3A2800F804FCFFDE1503C0DF80
+:108E6000150200DF040200DF15FE3FE115FF3FE0C1
+:108E70000615000017FFBFE02405C010B4018200F2
+:108E8000041CB9103A8885183A88071017FEBFE00D
+:108E90001E0AC01017FFBFE02405C010B4018200F5
+:108EA0003A888518151C39101793A0D0C4FFBF103D
+:108EB0001593A0D03A8805000608000017FFBFE010
+:108EC0004400801015FFBFE017FFBFE05001801085
+:108ED0001EE83F1040CD288084FDBF003A8837E06F
+:108EE0001701C0DF170000DF0402C0DE3A2800F8D7
+:108EF00004FEFFDE150100DF040100DF15FF3FE087
+:108F000017FFBFE03A8837E0170000DF0401C0DE3A
+:108F10003A2800F804FDFFDE1502C0DF150100DF6E
+:108F2000040100DF15FF3FE174014201043E6B299B
+:108F300017FF3FE100392780176DA0D03A880D1048
+:108F40007401420104426B2917FF3FE10039278079
+:108F5000176EA0D03A880D107401420104466B29A7
+:108F600017FF3FE10039278074014201044A6B2951
+:108F700017FF3FE1003927803A8801003A8837E03F
+:108F80001701C0DF170000DF0402C0DE3A2800F836
+:108F900004F8FFDE1505C0DF150400DF040400DF60
+:108FA00015FD3FE115FC7FE1150280E11503C0E1ED
+:108FB00017FDBFE0080480101E0C0010040280E0C2
+:108FC00015FEBFE017FEBFE00401C01015FEFFE074
+:108FD0001700801015FFBFE017FFBFE117FC7FE10E
+:108FE00017FD3FE1406F4280060C0000040280E064
+:108FF00015FEBFE017FEBFE00401C01015FEFFE044
+:109000001700801015FFBFE017FCBFE017FFBFE19E
+:109010003A880B1017FD3FE1C08026803A8837E080
+:109020001701C0DF170000DF0404C0DE3A2800F893
+:1090300004EFFFDE1510C0DF150F00DF150E40DC5A
+:10904000150D00DC040F00DF15F33FE1C5FD3FE027
+:10905000B40182001735B9104400C010B401820079
+:109060001535F91017F3BFE01703801015FCBFE0AA
+:1090700017F3BFE01704C01017FCBFE00300801017
+:10908000CC3F8010BA9004100C0F80103AC885189D
+:1090900015FBBFE017F3BFE01707801015FABFE01C
+:1090A0001766A0D00C008110261500101766A0D0FE
+:1090B0000C8080102612001017FABFE0CC3F001180
+:1090C00017FABFE03AD20410CC3F401117FABFE0C4
+:1090D0003AD40410CC3F801017FAFFE03AD60618B5
+:1090E0001501C0D8150080D83A880F283A880D207D
+:1090F00017FB7FE174010201044B2B2180C7028022
+:1091000017FCBFE003008010CC3F8010BA90041021
+:109110000C0F801017FCFFE03A88851815F9BFE0A6
+:1091200017F9BFE08B0080108DF8BFE017F9BFE0A2
+:109130008D00001017FBBFE04C00801026090010C6
+:1091400017F9FFE017FBBFE03A888518030080108D
+:10915000C5FDBFE017F9FFE017FBBFE03A888518AF
+:109160000500001017FBBFE0440080107AD0041007
+:109170003A880B1017F93FE1C0D726803A308400B7
+:109180000DF8BFE017FBBFE04C0080102605001073
+:1091900017F9FFE017FBBFE03A888518C3FDFFE031
+:1091A0000500C0100BF8FFE08BF8BFE02622801806
+:1091B00017F9BFE08BF8FFE08D00C0101766A0D054
+:1091C0000C008110260F00101766A0D00C808010B4
+:1091D000260C00108BF8BFE00BF8FFE03A880D1862
+:1091E0003A880B107401020104532B2180C70280BE
+:1091F0001766A0D08C0080102602001017F33FE104
+:10920000C00C3B80B40182001736B9104400C01076
+:10921000B40182001536F9108400000180F3288023
+:1092200017F33FE1807428808400000140FF28800C
+:1092300004F8BF00062E020017F9BFE08BF8FFE02C
+:109240008D00C01017F9BFE003008010CC3F8010E4
+:109250001C20801004E0BF102804C0101E0A021851
+:10926000BA900610340182003A888518176FA4104E
+:109270003A68001054940308D0990308D099030861
+:109280007494030868950308FC950308D0990308B3
+:10929000D0990308FC910308D0990308D0990308DA
+:1092A000289703082898030884980308D09903088E
+:1092B0009C990308B4018200173CB9104400C01007
+:1092C000B4018200153CF9101766A0D00C00811083
+:1092D000261400101766A0D00C80801026110010F4
+:1092E00017FABFE0CC3FC01017FABFE03AD2041023
+:1092F000CC3F001117FABFE03AD40410CC3F401124
+:1093000017FABFE03AD60410150080D83A880F2823
+:109310003A880D203A880B1874010201045E2B2153
+:1093200080C7028017F9BFE00500001017F9BFE001
+:109330008D00001017FBBFE04C00801026090010C4
+:1093400017F9FFE017FBBFE03A888518030080108B
+:10935000C5FDBFE017F9FFE017FBBFE03A888518AD
+:109360000500001017FBBFE0440080107AD0041005
+:109370003A880B1017F93FE1C0D726803A308400B5
+:109380003A88071017F9BFE08D00C01017FBBFE047
+:109390004C0080102605001017F9FFE017FBBFE016
+:1093A0003A888518C3FDFFE00500C01017FCBFE038
+:1093B00017048010E0FFBF101E1F001017FCBFE055
+:1093C000170480103AD6061017FCBFE0170480106F
+:1093D0003AD204100CC0BF103AB0861817FCBFE098
+:1093E000170480103A920410EC3F80103AB08618AF
+:1093F00017FCBFE0170480103A9604103AB08418A6
+:109400002C00FC103400B800260B801817FCBFE0BD
+:109410001704C01017F3BFE017068010170A0011D9
+:1094200017F3BFE017068010170C80103A30840045
+:109430003AB084201E06801817F3BFE0170680108C
+:10944000170AC01017FCBFE01503C0100604000087
+:1094500017FCBFE01704C01017FCBFE01503C010D5
+:1094600017FCBFE017FAFFE01504C010B40182003A
+:10947000174AB9104400C010B4018200154AF9100F
+:10948000B40182001742B9104400C010B401820038
+:109490001542F91017F3BFE017FAFFE01507C010E7
+:1094A00017F3BFE01703C01017FCBFE003008010E4
+:1094B000CC3F8010BA9004100C0F80103A888718A7
+:1094C00017F3BFE01503C01017F3BFE017FBFFE071
+:1094D0001504C01017F37FE144000001809E3A801C
+:1094E00015F7BFE017F7BFE00E0600101766A0D013
+:1094F0000C008110260300107401020104672B2167
+:10950000C0D902803A88050006790100B4018200C2
+:10951000173DB9104400C010B4018200153DF91088
+:1095200017F33FE1007D3C8006710100B401820029
+:109530001737B9104400C010B40182001537F91074
+:1095400017F9BFE015F6BFE01766A0D00C00811038
+:10955000262F001074010201046C2B2180C70280A9
+:1095600017F6BFE043008010CC3F00111C20002103
+:1095700004E03F2117F6BFE017068010CC3F4011F2
+:1095800017F6BFE0170680103AD20410CC3F8011C6
+:1095900017F6BFE0170680103AD40410CC3F8010B5
+:1095A00017F6FFE01706C0183AD606181501C0D8FE
+:1095B000150080D83A880F303A880D283A880B2059
+:1095C0007401020104752B2180C7028017FABFE0E5
+:1095D000CC3FC01017FABFE03AD20410CC3F0011C4
+:1095E00017FABFE03AD40410CC3F401117FABFE09D
+:1095F0003AD60410150080D83A880F283A880D20F2
+:109600003A880B1874010201047A2B2180C702806A
+:1096100017F67FE117F33FE1C0013A8006330100FE
+:10962000B4018200173AB9104400C010B40182009E
+:10963000153AF9101766A0D00C00811026160010FC
+:1096400017FABFE0CC3FC01017FABFE03AD20410BF
+:10965000CC3F001117FABFE03AD40410CC3F4011C0
+:1096600017FABFE03AD60410150080D83A880F28C0
+:109670003A880D203A880B1874010201047F2B21CF
+:1096800080C702801766A0D08C00801026020010D0
+:1096900017F33FE1C00C3B808400000180F3288079
+:1096A00017F33FE1807428808400000140FF288088
+:1096B000060E0100B4018200173BB9104400C0102F
+:1096C000B4018200153BF91017F9BFE015F5BFE0B2
+:1096D0001766A0D00C008110262A001017F5BFE0F5
+:1096E00017068010CC3FC01017F5BFE0170680109A
+:1096F0003AD20410CC3F001117F5BFE017068010D6
+:109700003AD40410CC3F401117F5BFE01706801083
+:109710003AD60410150080D83A880F283A880D20D0
+:109720003A880B187401020104892B2180C702803A
+:1097300017F5BFE017018010CC3FC01017F5BFE050
+:10974000170180103AD20410CC3F001117F5BFE08A
+:10975000170180103AD40410CC3F401117F5BFE038
+:10976000170180103AD60410150080D83A880F28C7
+:109770003A880D203A880B187401020104932B21BA
+:1097800080C7028017F5BFE01706001417F5BFE089
+:109790001701401417F3BFE0170680103A8809102C
+:1097A000C02F25803A88071004018000150080D85A
+:1097B0003A880F183A880D88C4FF7F013A880980DB
+:1097C000C0C73C808400000180F3288017F33FE18C
+:1097D000807428808400000140FF288006C30000B8
+:1097E000B40182001738B9104400C010B4018200DF
+:1097F0001538F9101766A0D00C0081102631001022
+:1098000017F9BFE015F4BFE017F3BFE017078010AA
+:10981000CC3FC01017F3BFE0170780103AD20410F6
+:10982000CC3F001117F3BFE0170780103AD40410A3
+:10983000CC3F401117F3BFE0170780103AD6041051
+:10984000150080D83A880F283A880D203A880B18DE
+:109850007401020104972B2180C7028017F4BFE036
+:1098600017068010CC3FC01017F4BFE01706801019
+:109870003AD20410CC3F001117F4BFE01706801055
+:109880003AD40410CC3F401117F4BFE01706801003
+:109890003AD60410150080D83A880F283A880D204F
+:1098A0003A880B187401020104A02B2180C70280A2
+:1098B0001766A0D08C0080102602001017F33FE13D
+:1098C000C00C3B808400000180F3288017F33FE147
+:1098D000807428808400000140FF288006830000F7
+:1098E000B40182001739B9104400C010B4018200DD
+:1098F0001539F9101766A0D00C008110260300104E
+:109900007401020104A52B21C0D902801766A0D0E2
+:109910008C0080102602001017F33FE1C00C3B8042
+:109920008400000180F3288017F33FE180742880D1
+:109930008400000140FF2880066C0000B401820012
+:10994000173EB9104400C010B4018200153EF91052
+:109950001766A0D00C0081102603001074010201CC
+:1099600004AD2B21C0D9028017F9BFE08403C000E9
+:109970000500C01017F9BFE08D00001084024001FF
+:1099800017F93FE1C0D726803A3084003A880710A3
+:1099900017F9BFE08D00C01017FCBFE01704C0101E
+:1099A00017FCBFE01503C01017FCBFE017FAFFE07B
+:1099B0001504C010B40182001742B9104400C01051
+:1099C000B40182001542F910B4018200174CB9109D
+:1099D0004400C010B4018200154CF91017F3BFE029
+:1099E0001703C01017FCBFE003008010CC3F8010AD
+:1099F000BA9004100C0F80103A88871817F3BFE054
+:109A00001503C01017F3BFE00405C0001504C01013
+:109A100017F3BFE017FAFFE01507C01017F37FE157
+:109A200044000001809E3A8015F7BFE017F7BFE0C1
+:109A30000E0600101766A0D00C008110260300103F
+:109A40007401020104B42B21C0D902803A880500B8
+:109A5000062700001766A0D00C0081102603001016
+:109A60007401020104BD2B21C0D9028084000001D1
+:109A700080F3288017F33FE1807428808400000180
+:109A800040FF2880061900001766A0D00C00811046
+:109A9000260E001017F9BFE003008010CC3F8010A5
+:109AA0001C20801004E0BF103A880B1074010201E2
+:109AB00004C32B2180C702801766A0D08C008010C1
+:109AC0002602001017F33FE1C00C3B808400000128
+:109AD00080F3288017F33FE1807428808400000120
+:109AE00040FF288084008000060100008400800080
+:109AF00004FEFFE61703C0DF170200DF170140DC9A
+:109B0000170000DC0404C0DE3A2800F804F4FFDE8D
+:109B1000150BC0DF150A00DF040A00DF15FB3FE16B
+:109B200015FA7FE115F9BFE115F8FFE11766A0D03E
+:109B30000C0480102618001017F8BFE0CC3F8010EE
+:109B4000BA900610740182003A88851817503211B5
+:109B500017FBBFE0CC3F401117FBBFE03AD2041027
+:109B6000CC3F801117FBBFE03AD40410CC3F8010EB
+:109B700017FBFFE03AD606181501C0D8150080D8AB
+:109B80003A880F303A880D283A880B207401020178
+:109B900004DD2B2180C702808400000180F328802F
+:109BA000048500014043288015FFBFE084000001C8
+:109BB00040FF288017FFBFE01E0C00101766A0D0E2
+:109BC0000C808010260300107401020104EA2B218E
+:109BD000C0D90280B40182001743B9104400C010FC
+:109BE000B40182001543F9100679000017FFBFE0A9
+:109BF0001703801015FEBFE017FEBFE017FAFFE065
+:109C00001503C01017FEBFE017FBFFE01504C010DE
+:109C100017FFBFE0170380100405C01017FFBFE057
+:109C20001503C01017FFBFE01704801004FBFF10DE
+:109C300017FFBFE01504C01017FFBFE01702C0E018
+:109C40001506C01017FFBFE01703801015FDBFE019
+:109C500017F8BFE00CC0BF102606001017F8BFE0D1
+:109C60003AD204103A88071017FDBFE00500C01073
+:109C70000603000017FDBFE0C400C0000500C010CF
+:109C800017F8BFE03A88071017FDBFE04500C01085
+:109C900017FDBFE08D01001017FDBFE08B01C01064
+:109CA00017FDBFE00D01C01017F8BFE0CC3F8010DA
+:109CB000180180101E120010170280E01709C01052
+:109CC000170280E0170880103AC885183AD20510AC
+:109CD000CC3F80103A880910170280E01709C010A5
+:109CE000170280E0170880103AC885183A920410CD
+:109CF0003AB084203A88071017FDBFE08D01C010EC
+:109D000017FDBFE0040280100407800117F97FE10E
+:109D10003A880910806B088017FDBFE08D000010A5
+:109D20008404400117FD3FE1C0D726803A3084000B
+:109D30003A88071017FDBFE08D00C01017FFBFE085
+:109D40000409C0001504C01017FFBFE017FBFFE0B7
+:109D50001507C01017FF7FE144000001809E3A8084
+:109D600015FCBFE017FCBFE00E0C0010B401820030
+:109D70001743B9104400C010B40182001543F91014
+:109D80001766A0D00C868010261000107401020106
+:109D900004F02B21C0D90280060C0000B40182001F
+:109DA0001742B9104400C010B40182001542F910E6
+:109DB000B40182001744B9104400C010B4018200FD
+:109DC0001544F9103A880100060100003A880100A4
+:109DD0003A8837E01701C0DF170000DF0402C0DE59
+:109DE0003A2800F804F5FFDE150AC0DF150900DF88
+:109DF000040900DF15FA3FE13A88052805F9BFE0BC
+:109E00001766A0D00C0480102630001007F97FE1FF
+:109E100017FABFE0170380103AD20410CC3FC010ED
+:109E200017FABFE0170380103A920410CCFFBF105E
+:109E30003AB08418CC3F801117FABFE017038010A6
+:109E40003AD20410CC3FC01017FABFE017038010BD
+:109E50003A920410CCFFBF103AB084183AD20410E2
+:109E6000CC3FC01117FABFE0170380103AD204109C
+:109E7000CC3FC01017FABFE0170380103A920410CD
+:109E8000CCFFBF103AB084183AD40410CC3F8010F5
+:109E900017FAFFE01703C0183AD20618CC3F001992
+:109EA00017FAFFE01703C0183A920618CCFFFF1804
+:109EB0003AB0C6203AD606181501C0D8150080D889
+:109EC0007401020104F92B2180C7028017FABFE058
+:109ED00003008010CC3F8010BA9004100C0F80104B
+:109EE00004048010C5FFBFE08400000180F32880D7
+:109EF000C3FFBFE01764E0D03A88C51004058010A6
+:109F00003A8809104043288015FEBFE08400000114
+:109F100040FF288017FEBFE01E0C00101766A0D07F
+:109F20000C808010260300107401020104EA2B212A
+:109F3000C0D90280B40182001743B9104400C01098
+:109F4000B40182001543F910065D000017FEBFE062
+:109F50001703801015FDBFE017FABFE01704C0100B
+:109F600017FDBFE01503C01017FABFE01703C010BC
+:109F700017FDBFE01504C01017FEBFE017038010E7
+:109F80000405C01017FEBFE01503C01017FEBFE0A8
+:109F90001703801015FCBFE017FCBFE0C402C0002F
+:109FA0000500C01017FCBFE003F9FFE04500C0103A
+:109FB00017FCBFE08D01001017FCBFE08B01C01043
+:109FC00017FCBFE00D01C01017FCBFE00402C01079
+:109FD00017FABFE003008010CC3F8010BA90041045
+:109FE0000C0F8010040280103A880D1017FA7FE1E0
+:109FF0003A880918806B088017FCBFE08D000010BC
+:10A00000C3FFBFE07AD00410CC3F80103A880B1019
+:10A0100017FC3FE1C0D726803A3084003A88071009
+:10A0200017FCBFE08D00C010C3FFFFE017FEBFE0CC
+:10A030001504C01017FDBFE01704C01017FEBFE0E5
+:10A040001507C01017FE7FE144000001809E3A8092
+:10A0500015FBBFE017FBBFE00E0C0010B40182003F
+:10A060001743B9104400C010B40182001543F91021
+:10A070001766A0D00C868010261000107401020113
+:10A0800004092C21C0D90280060C0000B401820012
+:10A090001742B9104400C010B40182001542F910F3
+:10A0A000B40182001745B9104400C010B401820009
+:10A0B0001545F9103A880100060100003A880100B0
+:10A0C0003A8837E01701C0DF170000DF0402C0DE66
+:10A0D0003A2800F804FCFFDE1503C0DF150200DF9C
+:10A0E000040200DF15FF3FE115FE7FE11794A0D0C9
+:10A0F000260400101794A0D017FE7FE117FF3FE160
+:10A100003AE83E1017FE7FE117FF3FE180D02A803A
+:10A110003A8801003A8837E01701C0DF170000DFF6
+:10A120000402C0DE3A2800F804FEFFDE1501C0DF9D
+:10A13000150000DF3A8839D804020001801C248011
+:10A14000260500107401020104112C21C0D90280DF
+:10A150004400800006250000041480013A880B00AA
+:10A16000B4010201044F3921408E08808400C000F0
+:10A17000B4018200154FF9100410C000B401820030
+:10A180001550F9101730A0D0240F80103A8809100C
+:10A19000C08229801595A0D01795A0D01E0500106B
+:10A1A00074010201041E2C21C0D9028004FBBF00EF
+:10A1B000060E00001795E0D01730A0D0240F8010B5
+:10A1C0003A880D103A880B003A880918408E0880AA
+:10A1D0004400C000B4018200154FF910041EC000F5
+:10A1E000B4018200155BF9103A8805003A8837E01F
+:10A1F0001701C0DF170000DF0402C0DE3A2800F8B4
+:10A2000004F8FFDE1507C0DF150600DF040600DFD7
+:10A2100015FD3FE115FC7FE13A8805303A880738A3
+:10A2200005FBBFE03A8805180DFABFE017FDBFE057
+:10A230001703801004FBFF1017FDBFE01503C010CB
+:10A2400017FDBFE0170480100405C01017FDBFE024
+:10A250001504C01017FDBFE01703801015FFBFE005
+:10A2600017FFBFE04411C0000500C01017FFBFE09A
+:10A270000BFAFFE08D01C01017FCBFE0CCFFBF1050
+:10A280003AD204103A88071017FCBFE0CCFFBF1089
+:10A290003A9204103AB084183A88071017FFBFE0CA
+:10A2A0000D01C01017FDBFE017048010CCFFBF10D8
+:10A2B0003AD204103A88071017FDBFE01704801047
+:10A2C000CCFFBF103A9204103AB084183A880710B5
+:10A2D00017FFBFE08D00C01017FFBFE003FBFFE0DA
+:10A2E0004502C01017FDBFE0170C801015FEBFE03F
+:10A2F00017FEBFE02611001017FEBFE043008010DC
+:10A30000CC3F80102605001017FEBFE04300C010B0
+:10A3100017FFBFE00502C0100603000017FFBFE0F3
+:10A320000410C0000502C01017FEBFE00300C010FB
+:10A3300017FFBFE04500C0100605000017FFBFE093
+:10A340000410C0000502C01017FFBFE04500001058
+:10A3500017FFBFE08D0200108402400117FF3FE1AC
+:10A36000C0D726803A3084003A88071017FFBFE034
+:10A370008D02C0103A8801003A8837E01701C0DF2B
+:10A38000170000DF0402C0DE3A2800F804F1FFDE07
+:10A39000150EC0DF150D00DF040D00DF15F63FE1DF
+:10A3A00017F6BFE0170780103AD6061017F6BFE081
+:10A3B000170780103AD204100CC0BF103AB08618AC
+:10A3C00017F6BFE0170780103A920410EC3F801098
+:10A3D0003AB0861817F6BFE0170780103A960410B7
+:10A3E0003AB084182C00FC103400B8001EA280186B
+:10A3F00017F6BFE0170B80102614001017F6BFE009
+:10A40000170B8010170080102606001017F6BFE00B
+:10A41000170B80101700C01017F6BFE01506C0100C
+:10A420000621000017F6BFE01707801004F7FFE0D1
+:10A430003A880B183A88091000373B803A88071091
+:10A4400017F6BFE01506C0100617000015FF3FE025
+:10A450000612000017FFBFE0BA900610B401820098
+:10A460003A8885181770B710172B8010260800102F
+:10A4700017FFBFE0BA900610B40182003A88851831
+:10A480001770F71017F6BFE01506C010060600009B
+:10A4900017FFBFE04400801015FFBFE01767A0D092
+:10A4A00017FFFFE036EBBF1817F6BFE01706801066
+:10A4B0002604001017F6BFE017068010172B801037
+:10A4C0001E2A00101766A0D00C848010261A0010D7
+:10A4D00017F6BFE01704401117F6BFE0170780100A
+:10A4E000CC3F801117F6BFE0170780103AD2041056
+:10A4F000CC3F801017F6FFE01707C0183AD40618B3
+:10A50000CC3FC01817F63FE1170700213AD60820C4
+:10A51000150200D91501C0D8150080D83A880F302F
+:10A520003A880D2817F67FE17401020104282C21D6
+:10A5300080C7028040CD2880B4018200175AB9102C
+:10A540004400C010B4018200155AF91084000001C3
+:10A5500080F3288017F63FE1807428808400000192
+:10A5600040FF2880C4F7BF000648010017F6BFE08F
+:10A570001707C01017F6BFE0170680103A880B10B7
+:10A580003A88091840503C8015FDBFE017FDBFE038
+:10A59000261B001017F6BFE0170B801026050010D1
+:10A5A00017F6BFE0170B801043018010CC3F8010DE
+:10A5B0002613001017F6BFE00402C0000D08C010FB
+:10A5C00017F63FE1C0533B8015FCBFE017FCBFE02E
+:10A5D000260B00104400000180F3288017FC7FE167
+:10A5E000B401020104AB3621009928804400000127
+:10A5F00040FF28801780A0D03A88091040D81580E5
+:10A6000017F6BFE01703801015FBBFE017FBBFE094
+:10A6100003028010CC3F8010260B001017F6BFE01D
+:10A6200017078010CC3F8010E01F80101E0600101E
+:10A6300017F6BFE01707C01017F6BFE01706801027
+:10A64000170A80101E0880188400000180F32880FB
+:10A6500017F63FE1807428808400000140FF2880C5
+:10A660003A8805000609010017F6BFE017078010B9
+:10A6700015F7BFE0063F000017F6BFE01707801090
+:10A68000D8FFBF101E04001017F6BFE01707801098
+:10A6900015F7BFE00637000017F6BFE01707801078
+:10A6A00004F7FFE03A880B183A88091000373B801E
+:10A6B0003A88071017F6BFE01506C01017F6BFE07E
+:10A6C000170680101E2A00101766A0D00C84801078
+:10A6D000261A001017F6BFE01704401117F6BFE066
+:10A6E00017078010CC3F801117F6BFE017078010C6
+:10A6F0003AD20410CC3F801017F6FFE01707C018BD
+:10A700003AD40618CC3FC01817F63FE117070021CE
+:10A710003AD60820150200D91501C0D8150080D8F6
+:10A720003A880F303A880D2817F67FE1740102014C
+:10A7300004282C2180C7028040CD2880B4018200EB
+:10A74000175AB9104400C010B4018200155AF9100C
+:10A750008400000180F3288017F63FE18074288090
+:10A760008400000140FF2880C4F7BF0006C7000036
+:10A770003A8801001766A0D00C80801026290010AE
+:10A7800017F6BFE01704001117F6BFE01707801097
+:10A79000CC3F401117F6BFE0170780103AD20410E3
+:10A7A000CC3F801117F6BFE0170780103AD4041091
+:10A7B000CC3F801017F6FFE01707C0183AD60618EE
+:10A7C0001501C0D8150080D83A880F303A880D2876
+:10A7D0003A880B207401020104382C2180C70280C2
+:10A7E00017F7BFE0CC3FC01017F7BFE03AD2041014
+:10A7F000CC3F001117F7BFE03AD40410CC3F401112
+:10A8000017F7BFE03AD60410150080D83A880F2811
+:10A810003A880D203A880B187401020104412C215A
+:10A8200080C7028017F6BFE017068010170AC01015
+:10A8300017F6BFE0170780101E27801817F6BFE035
+:10A8400017078010CC3F8010E01F80101E220010E0
+:10A8500017F6BFE017068010172A80100C02801030
+:10A860001E09001040CD28808400000180F328805C
+:10A8700017F63FE1807428808400000140FF2880A3
+:10A8800044FDBF000681000017F6BFE00402C000CF
+:10A890000D08C0103A88090040FF288044000001DC
+:10A8A00080F3288017F67FE1B401020104AB362162
+:10A8B000009928804400000140FF28803A88090060
+:10A8C00080F328801780A0D03A88091040D81580DE
+:10A8D0003A880500066D000017F6BFE0170A8010E1
+:10A8E0000C0480103A000510C5FABFE0407F2880B4
+:10A8F00015F9BFE0C3FABFE01E09001017F6BFE06C
+:10A9000017068010170980103A88071017F9BFE062
+:10A910002E0180183A88051815FEBFE006040000D5
+:10A9200017F6BFE0170680101709801015FEBFE06C
+:10A9300017F6BFE01704801017F6FFE01706C018DF
+:10A940001708C0183A88C51017FEFFE02E098018B6
+:10A9500040CD28808400000180F3288017F63FE175
+:10A96000807428808400000140FF288044FDBF00DF
+:10A9700006460000C3FABFE01E400010840000013C
+:10A9800080F3288017F6BFE01704801017F6FFE069
+:10A990001706C0181708C0183A88C5103A88091059
+:10A9A0004043288015F8BFE08400000140FF288064
+:10A9B00017F8BFE01E0800108400000180F3288013
+:10A9C00017F63FE1807428808400000140FF288052
+:10A9D000C4FABF00062D000017F8BFE01701801071
+:10A9E00017F6FFE01706C0181708C0183A88C710F6
+:10A9F00017F8BFE01503C01017F8BFE01703C01029
+:10AA000017F6BFE01703001117F6BFE01704801018
+:10AA10003A880D103A880B203A880918806B088014
+:10AA200017F6BFE01704C01017F8BFE01504C010F8
+:10AA300017F6BFE01706C01017F8BFE01506C010E4
+:10AA400017F6BFE01707C01017F8BFE01507C010D2
+:10AA50008400000180F3288017F63FE1807428808D
+:10AA60008400000140FF288017F7BFE03A880B10F0
+:10AA700017F83FE140DF24800604000017F7BFE02D
+:10AA80003A880B1017F63FE140DF24803A8837E020
+:10AA90001701C0DF170000DF0402C0DE3A2800F80B
+:10AAA00004F9FFDE1506C0DF150500DF040500DF31
+:10AAB0003A88052015FB7FE105FCBFE0B401820068
+:10AAC0001758B9104400C010B40182001558F9108D
+:10AAD00017FBBFE01703801004FBFF1017FBBFE05C
+:10AAE0001503C01017FBBFE0170480100405C01049
+:10AAF00017FBBFE01504C01017FBBFE01703801061
+:10AB000015FEBFE017FEBFE04411C0000500C010F5
+:10AB100017FEBFE08D010010172FA0D0CCFFBF1093
+:10AB20003AD204103A880710172FA0D0CCFFBF10DC
+:10AB30003A9204103AB084183A88071017FEBFE022
+:10AB40000D01C010172FA0D044008010152FA0D0E9
+:10AB500017FBBFE017048010CCFFBF103AD20410DF
+:10AB60003A88071017FBBFE017048010CCFFBF1016
+:10AB70003A9204103AB084183A88071017FEBFE0E2
+:10AB80008D00C01017FEBFE003FCFFE04502C010BF
+:10AB900017FEBFE08D02001004108000C5FFBFE06B
+:10ABA00017FBBFE0170780103AD6061017FBBFE06F
+:10ABB000170780103AD204100CC0BF103AB08618A4
+:10ABC00017FBBFE0170780103A920410EC3F80108B
+:10ABD0003AB0861817FBBFE0170780103A960410AA
+:10ABE0003AB084182C00FC103400B8001E078018FE
+:10ABF00017FBBFE0170B80102604001017FBBFE007
+:10AC0000170B801003018010C5FFBFE017FBBFE0EA
+:10AC1000170C801015FDBFE017FDBFE026110010D6
+:10AC200017FDBFE043008010CC3F801026050010C8
+:10AC300017FDBFE04300C01017FEBFE00502C010C3
+:10AC40000603000017FEBFE0C3FFFFE00502C010CF
+:10AC500017FDBFE00300C01017FEBFE04500C010A5
+:10AC60000605000017FEBFE0C3FFFFE00502C010AD
+:10AC700017FEBFE0450000108402400117FE3FE1CF
+:10AC8000C0D726803A3084003A88071017FEBFE00C
+:10AC90008D02C01017FB3FE1402D3A803A8837E023
+:10ACA0001701C0DF170000DF0402C0DE3A2800F8F9
+:10ACB00004F6FFDE1509C0DF150800DF040800DF19
+:10ACC0003A88052015F97FE115F8BFE105FABFE0E4
+:10ACD0000405800085FFBFE0B40182001758B91059
+:10ACE0004400C010B40182001558F91017F8BFE0F5
+:10ACF00015FEBFE0060D000017FEBFE00300801048
+:10AD0000CC3F8010180580101E04001083FFBFE0A8
+:10AD10000401801085FFBFE0060100003A880100B1
+:10AD200017FEBFE04400801015FEBFE017FEBFE035
+:10AD300003008010CC3F80101EEF3F1083FFBFE068
+:10AD4000CC0080102607001083FFBFE0CC008010ED
+:10AD50003A880710040180003AC8C510C5FDBFE05D
+:10AD600006010000C5FD3FE017F9BFE01703C01062
+:10AD700083FF3FE1C3FDBFE03A8885203AC88500E4
+:10AD80003A88871817F9BFE01503C01017F9BFE01C
+:10AD90001704801083FF3FE1C3FDFFE03A88C7201E
+:10ADA0003A88C71017F9BFE01504C01017F9BFE0C3
+:10ADB0001703801015FCBFE083FFFFE0C3FDBFE079
+:10ADC0003A888518BAD00510141080103A880710F8
+:10ADD00017FCBFE00500C01017FCBFE08D0100109C
+:10ADE000172FA0D0CCFFBF103AD204103A8807101A
+:10ADF000172FA0D0CCFFBF103A9204103AB084189D
+:10AE00003A88071017FCBFE00D01C010172FA0D023
+:10AE100044008010152FA0D017F9BFE01704801050
+:10AE2000CCFFBF103AD204103A88071017F9BFE0E0
+:10AE300017048010CCFFBF103A9204103AB0841867
+:10AE40003A88071017FCBFE08D00C01017FCBFE068
+:10AE500003FAFFE04502C01017FCBFE08D020010AE
+:10AE600004108000C5FFBFE017F9BFE0170780108E
+:10AE70003AD6061017F9BFE0170780103AD204102F
+:10AE80000CC0BF103AB0861817F9BFE01707801042
+:10AE90003A920410EC3F80103AB0861817F9BFE0E0
+:10AEA000170780103A9604103AB084182C00FC1052
+:10AEB0003400B8001E07801817F9BFE0170B801088
+:10AEC0002604001017F9BFE0170B80100301801053
+:10AED000C5FFBFE017F9BFE0170C801015FBBFE0FE
+:10AEE00017FBBFE02611001017FBBFE043008010E6
+:10AEF000CC3F80102605001017FBBFE04300C010B8
+:10AF000017FCBFE00502C0100603000017FCBFE0FD
+:10AF1000C3FFFFE00502C01017FBBFE00300C01035
+:10AF200017FCBFE04500C0100605000017FCBFE09D
+:10AF3000C3FFFFE00502C01017FCBFE04500001092
+:10AF400017F9BFE0170380100405801015FEBFE05D
+:10AF50000610000017F8BFE003008010CC3F8010FF
+:10AF6000180580101E07001017FEBFE00425C10061
+:10AF70001500C01017FEBFE00401801015FEBFE0F1
+:10AF8000060100003A88010017F8BFE04400801075
+:10AF900015F8BFE017F8BFE003008010CC3F801029
+:10AFA0001EEC3F1085FD3FE00607000083FDBFE07B
+:10AFB00017FEFFE03A8885180500001083FDBFE00A
+:10AFC0004400801085FDBFE083FDFFE0C3FDBFE0CE
+:10AFD00036F6BF1883FFFFE0C3FDBFE03A8885184F
+:10AFE000FAD706103A8885187AD005103A880B10DF
+:10AFF00017FC3FE1C0D726803A3084003A8807101A
+:10B0000017FCBFE08D02C01017F93FE1402D3A80D8
+:10B010003A8837E01701C0DF170000DF0402C0DE06
+:10B020003A2800F804FCFFDE1503C0DF150200DF3C
+:10B03000040200DF15FE3FE1B40182001758B91089
+:10B040004400C010B40182001558F91017FEBFE08B
+:10B050001703801015FFBFE017FFBFE00B01801042
+:10B06000CCFFBF101E0E0010172FA0D0CCFFBF10BA
+:10B070003AD204103A880710172FA0D0CCFFBF1087
+:10B080003A9204103AB084183A88071017FFBFE0CC
+:10B090000D01C010172FA0D044008010152FA0D094
+:10B0A00017FFBFE08D0200108402400117FF3FE14F
+:10B0B000C0D726803A3084003A88071017FFBFE0D7
+:10B0C0008D02C01017FE3FE1402D3A803A8837E0EC
+:10B0D0001701C0DF170000DF0402C0DE3A2800F8C5
+:10B0E00004FAFFDE1505C0DF150400DF040400DFED
+:10B0F00015FD3FE104FEBFE03A880B1017FD3FE16C
+:10B1000000373B8015FFBFE017FFBFE01E160010A1
+:10B110001766A0D00C0580102611001017FDBFE0A7
+:10B12000CC3FC01017FDBFE03AD20410CC3F001155
+:10B1300017FDBFE03AD40410CC3F401117FDBFE02B
+:10B140003AD60410150080D83A880F283A880D2086
+:10B150003A880B187401020104462C2180C7028032
+:10B160003A8805000602000017FFBFE0170A8010AA
+:10B170003A8837E01701C0DF170000DF0402C0DEA5
+:10B180003A2800F804F7FFDE1508C0DF150700DFD6
+:10B19000040700DF15FC3FE117FCBFE01703801038
+:10B1A00015FFBFE017FFBFE08B0280108DFEBFE0F0
+:10B1B00017FFBFE08D02001017FFBFE003008010F3
+:10B1C000CC3F8010BA9004107AD005108C07801004
+:10B1D0003A880B1017FF3FE1C0D726803A30840031
+:10B1E0000DFEBFE08BFEFFE00BFEBFE026018018E6
+:10B1F00040CD288074014201044F6C293A8809002F
+:10B200000039278017FFBFE015FDBFE017FDBFE045
+:10B2100003008010CC3F401117FDBFE044008010B8
+:10B2200003008010CC3F801117FFBFE08B0080101F
+:10B23000CCFFBF103AD20410CCFFBF10CC3FC010DF
+:10B2400017FFBFE08B008010CCFFBF103A920410B4
+:10B25000CCFFBF103AB0841817FFFFE00B01C018F5
+:10B26000CCFFFF183AD20618CCFFFF18CC3F0019CC
+:10B2700017FFFFE00B01C018CCFFFF183A92061829
+:10B28000CCFFFF183AB0C6201501C0D8150080D8F1
+:10B290003A880F303A880D287401420104546C2911
+:10B2A0003A8809000039278017FDBFE0840180102B
+:10B2B0000B008010CCFFBF103AD20410CCFFBF109F
+:10B2C000CC3FC01017FDBFE0840180100B00801040
+:10B2D000CCFFBF103A920410CCFFBF103AB08C18CC
+:10B2E00017FFBFE003028010CC3FC01117FFBFE083
+:10B2F00043028010CC3FC0108BFEBFE03AD2041056
+:10B30000CCFFBF10CC3F00118BFEBFE03A9204107F
+:10B31000CCFFBF103AB088208BFE7FE10BFEBFE070
+:10B320001E038028740182000460AC100602000035
+:10B33000740182000461AC10150280D8150100D997
+:10B340001500C0D87401420104626C293A880900D2
+:10B350000039278017FFBFE017038010CC3F001192
+:10B3600017FFBFE0170380103AD20410CC3F401102
+:10B3700017FFBFE0170380103AD40410CC3F8010B1
+:10B3800017FFFFE01703C0183AD606181501C0D8FA
+:10B39000150080D83A880F283A880D2074014201A0
+:10B3A00004726C293A8809000039278017FFBFE032
+:10B3B00017048010CC3F001117FFBFE01704801066
+:10B3C0003AD20410CC3F401117FFBFE017048010A1
+:10B3D0003AD40410CC3F801017FFFFE01704C018C8
+:10B3E0003AD606181501C0D8150080D83A880F281B
+:10B3F0003A880D207401420104776C293A880900CB
+:10B400000039278017FFBFE08BFEFFE08D02C010E0
+:10B410003A8801003A8837E01701C0DF170000DFE3
+:10B420000402C0DE3A2800F804F8FFDE1507C0DF8A
+:10B43000150600DF040600DF15FC3FE115FB7FE188
+:10B4400017FCBFE01E0200103A88050006640000E9
+:10B450001795A0D01E0200103A8805000660000073
+:10B46000179CA0D0260E0010179CA0D017008010AB
+:10B4700017FCFFE01E0A8018179CA0D01706C0100A
+:10B4800017FBBFE01500C010179CA0D0177DE0D0BF
+:10B490001509C010179CA0D0170E80100650000090
+:10B4A00017FC3FE180B23C8015FDBFE017FDBFE017
+:10B4B0002609001017FDBFE0159CA0D017FDBFE0C6
+:10B4C0001706C01017FBBFE01500C01017FDBFE046
+:10B4D000170E801006420000B401820017A6B610B5
+:10B4E00015FEBFE015FF3FE00624000017FEBFE099
+:10B4F000170C8010261B001017FEBFE0170A8010E3
+:10B500002618001017FEBFE0170AC01017FCBFE096
+:10B510003AF0861817FEBFE0170C80103A708418B6
+:10B520001E10001044008000150080D817FFFFE1B6
+:10B5300017FCBFE1C4FF7F0117FC3FE1C0C73C809F
+:10B54000159CA0D0179CA0D01E01001040CD2880D3
+:10B5500017FBBFE017FCFFE01500C01017FEBFE0AF
+:10B56000061F000017FEBFE01700801015FEBFE0A9
+:10B5700017FFBFE04400801015FFBFE017FEBFE0DB
+:10B580001EDA3F10B401820017A6B61015FEBFE008
+:10B59000060C000017FEBFE0170D801026060010F5
+:10B5A00017FEBFE0170DC01017FBBFE01500C0105D
+:10B5B00017FEBFE0060A000017FEBFE0170080106C
+:10B5C00015FEBFE017FEBFE01EF23F1017FBBFE005
+:10B5D00017FCFFE01500C010B401820017A6B610DA
+:10B5E0003A8837E01701C0DF170000DF0402C0DE31
+:10B5F0003A2800F804FBFFDE1504C0DF150300DF66
+:10B60000040300DF15FD3FE117FDBFE017048010C4
+:10B6100017FDFFE01703001917FDFFE01701C01821
+:10B620003AC8C7203A88C51015FFBFE08400000162
+:10B6300080F3288017FFBFE03A8809104043288034
+:10B6400015FEBFE08400000140FF288017FEBFE028
+:10B650001E06001017FF7FE174010201047C2C21FB
+:10B6600080C702803A8805000628000017FEBFE068
+:10B670001701C01017FDBFE01701801017FF3FE151
+:10B680003A880D203A880B103A880918806B088098
+:10B6900017FEBFE01701801017FDFFE01703001928
+:10B6A00017FDFFE01701C0183AC8C7203A88C71035
+:10B6B00017FEBFE01503C01017FDBFE01704C01050
+:10B6C00017FEBFE01504C01017FDBFE01706C0103D
+:10B6D00017FEBFE01506C01017FDBFE01707C0102A
+:10B6E00017FEBFE01507C01017FDBFE00B08C01024
+:10B6F00017FEBFE00D08C01017FDBFE01705C01012
+:10B7000017FEBFE01505C01017FEBFE03A8837E00E
+:10B710001701C0DF170000DF0402C0DE3A2800F87E
+:10B7200004F4FFDE150BC0DF150A00DF150900DC8D
+:10B73000040A00DF15F63FE1C4FFBF0015FDBFE0BE
+:10B740001766A0D00C008110260E00101766A0D03E
+:10B750000C808010260B001017F6BFE017040014B1
+:10B7600017F6BFE0170680103A880910C02F258011
+:10B770003A880D103A880B807401020104882C214C
+:10B7800080C70280B40182001751B9104400C01074
+:10B79000B40182001551F91017F6BFE017038010AD
+:10B7A00015FCBFE017F6BFE01704801017FCFFE0A0
+:10B7B0008B00C018CCFFFF183AD20618CCFFFF1838
+:10B7C000CC3F001917FCFFE08B00C018CCFFFF181E
+:10B7D0003A920618CCFFFF183AB0C6202E1DC010B2
+:10B7E0001766A0D00C008110260C00101766A0D0A0
+:10B7F0000C808010260900107401020104912C2194
+:10B80000C0D902801766A0D08C00801026030010DB
+:10B8100017F6BFE03A880910C00C3B80B4018200E3
+:10B820001752B9104400C010B40182001552F9102B
+:10B830008400000180F3288017F6BFE03A880910E1
+:10B84000807428808400000140FF288004F8BF0035
+:10B850000682000017FCBFE08B008010CCFFBF10F9
+:10B860003AD20410CCFFBF10CC3FC01017FCBFE091
+:10B870008B008010CCFFBF103A920410CCFFBF1099
+:10B880003AB0841815FBBFE017F6BFE017FBFFE0E6
+:10B890001504C01017FCBFE003008010CC3F8010DF
+:10B8A0003AD10410CC3F8010200180101E1D0010E2
+:10B8B0001766A0D00C008110260C00101766A0D0CF
+:10B8C0000C808010260900107401020104962C21BE
+:10B8D000C0D902801766A0D08C008010260300100B
+:10B8E00017F6BFE03A880910C00C3B80B401820013
+:10B8F0001752B9104400C010B40182001552F9105B
+:10B900008400000180F3288017F6BFE03A88091010
+:10B91000807428808400000140FF288004F8BF0064
+:10B92000064E000017FCBFE08B0280108DFABFE0CE
+:10B9300017FCBFE08D02001017FCBFE00300801071
+:10B94000CC3F8010BA9004100C0F801015F9BFE0A6
+:10B9500017F9BFE07AD004103A880B1017FC3FE1CA
+:10B96000C0D726803A3084008DF8BFE08BFAFFE024
+:10B970008BF8BFE02620801817FCBFE08BFAFFE0B1
+:10B980008D02C0101766A0D00C008110260C00108C
+:10B990001766A0D00C8080102609001074010201E7
+:10B9A000049D2C21C0D902801766A0D08C00801085
+:10B9B0002603001017F6BFE03A880910C00C3B8040
+:10B9C000B40182001752B9104400C010B4018200C3
+:10B9D0001552F9108400000180F3288017F6BFE0AB
+:10B9E0003A880910807428808400000140FF288074
+:10B9F00004F8BF000619000017FCBFE08BFAFFE057
+:10BA00008D02C010440080000DF8BFE004F6BFE0D6
+:10BA100015F7BFE0C5FE3FE0060B0000C3FEBFE028
+:10BA2000BA90041017F7FFE03A88851817008010C5
+:10BA30003A880910C09B3B8015FDBFE0C3FEBFE004
+:10BA400044008010C5FEBFE0C3FEFFE00BF8BFE07E
+:10BA5000CCFFFF1836F1BF1817FDBFE004FFFFE66B
+:10BA60001702C0DF170100DF170000DC0403C0DE8F
+:10BA70003A2800F804F6FFDE1509C0DF150800DFDC
+:10BA8000040800DF15F93FE117F9BFE01703801044
+:10BA900015FFBFE017F9BFE01706801015FEBFE0E5
+:10BAA00017FFBFE0170480103AD6061017FFBFE05B
+:10BAB000170480103AD204100CC0BF103AB0861898
+:10BAC00017FFBFE0170480103A920410EC3F80107B
+:10BAD0003AB0861817FFBFE0170480103A9604109A
+:10BAE0003AB084182C00FC103400B8001E158018E1
+:10BAF00017FFBFE01704801017FE7FE13A88091096
+:10BB000040503C8015FDBFE017FDBFE01EDC00107B
+:10BB1000B4018200175AB9104400C010B401820069
+:10BB2000155AF9108400000180F3288017F93FE1CD
+:10BB3000807428808400000140FF288084008000F9
+:10BB4000061A010017FFBFE01704C01017FEBFE080
+:10BB5000170A801026CC801817FFBFE0170480104A
+:10BB6000E0FFBF101EC8001017FFBFE01704C01091
+:10BB700017FEBFE0170E801026C3801817FFBFE026
+:10BB80001704C01017FEBFE0170F801026BE8018E4
+:10BB900017FFBFE01704C01017FEBFE0171080109A
+:10BBA00026B9801817FEBFE0170AC01017FEBFE0C5
+:10BBB000170C80103A3084003A70841826B20010B6
+:10BBC0001766A0D00C008110261800101766A0D0B0
+:10BBD0000C8080102615001017FFBFE0170480109E
+:10BBE000CC3FC01017FFBFE0170480103AD20410FA
+:10BBF000CC3F001117FFBFE0170480103AD40410A7
+:10BC0000CC3F401117FFBFE0170480103AD6041054
+:10BC1000150080D83A880F283A880D203A880B18EA
+:10BC20007401020104A22C2180C70280B4018200A9
+:10BC3000174FB910980080101E0D0010B40182003B
+:10BC40001759B9104400C010B40182001559F910F9
+:10BC50008400000180F3288017F93FE18074288078
+:10BC60008400000140FF2880C4F7BF0006CF000019
+:10BC7000B40182001754B9104400C010B40182000E
+:10BC80001554F91017FFBFE003028010CC3F80105D
+:10BC9000A80080101E1A0010B40182001759B910B4
+:10BCA0004400C010B40182001559F91017FFBFE01D
+:10BCB0001703C01017F9BFE017068010170A00110C
+:10BCC00017F9BFE017068010150080D804C0C20124
+:10BCD00017FFBFE13A880B203A88091840A5398040
+:10BCE0008400000180F3288017F93FE180742880E8
+:10BCF0008400000140FF2880C4F7BF0006AB0000AD
+:10BD000017FFBFE01704C01017F9BFE01507C010F8
+:10BD100017F9BFE01707801004FAFFE03A880B1804
+:10BD20003A88091000373B8015FCBFE017FCBFE0E4
+:10BD30001E0D0010B4018200175AB9104400C01043
+:10BD4000B4018200155AF9108400000180F32880A4
+:10BD500017F93FE1807428808400000140FF2880AB
+:10BD6000C4F7BF000691000017FFBFE01704C01022
+:10BD700017FCBFE0170A80102645801817FFBFE0A8
+:10BD80001704C01017FCBFE0170E80102642801861
+:10BD900017FFBFE01704C01017F9BFE017068010A7
+:10BDA000170E8010263C801817F9BFE017FCFFE043
+:10BDB0001506C01017F9BFE01704801017F9FFE04F
+:10BDC0001706C0181708C0183A88C51017FCFFE0FE
+:10BDD0001709C0182E16801840CD288017FFBFE025
+:10BDE0001703C01017F9BFE017068010170A0011DB
+:10BDF00017F9BFE017068010150080D80401C001B4
+:10BE000017FFBFE13A880B203A88091840A539800E
+:10BE10008400000180F3288017F93FE180742880B6
+:10BE20008400000140FF288044FDBF00065F000041
+:10BE300017FFBFE003028010C4FFBF103A8807104D
+:10BE400017FFBFE00502C01017FFBFE08D02001012
+:10BE50008402400117FF3FE1C0D726803A308400BA
+:10BE60003A88071017FFBFE08D02C01017FABFE035
+:10BE70003A880B1017F93FE140DF2480064B0000A1
+:10BE80003A880100060500003A8801000603000018
+:10BE90003A880100060100003A88010017FFBFE060
+:10BEA0008B018010CCFFBF103AD204103A880710E3
+:10BEB00017FFBFE08B018010CCFFBF103A92041037
+:10BEC0003AB084188DFBBFE08BFBBFE00C008810FC
+:10BED0001E0500108BFBFFE0F4FFBF00C4FF8710BE
+:10BEE0003A708418262F00101766A0D00C0081101D
+:10BEF000261A00101766A0D00C808010261700109C
+:10BF000017FFBFE017038010CC3FC01017FFBFE042
+:10BF1000170380103AD20410CC3F001117FFBFE086
+:10BF2000170380103AD40410CC3F401117FFBFE034
+:10BF3000170380103AD60410150080D83A880F28CD
+:10BF40003A880D203A880B187401020104AE2C21A6
+:10BF500080C7028017F93FE1C00C3B80B40182002A
+:10BF6000175CB9104400C010B4018200155CF910D0
+:10BF7000B4018200175EB9104400C010B401820001
+:10BF8000155EF9108400000180F3288017F93FE165
+:10BF9000807428808400000140FF28808400800095
+:10BFA0000602000017F93FE180F03B803A8837E055
+:10BFB0001701C0DF170000DF0402C0DE3A2800F8D6
+:10BFC00004F9FFDE1506C0DF150500DF040500DFFC
+:10BFD00015FD3FE117FDBFE01703801015FEBFE020
+:10BFE00017FEBFE003008010CC3F8010601180106E
+:10BFF0001E13001017FEBFE003008010CC3F80101E
+:10C00000701180101E05001017FEBFE003008010A5
+:10C01000CC3F8010301280101E09001017FEBFE0C8
+:10C0200003008010CC3F80103A880B10740102018D
+:10C0300004B72C2180C7028044FDBF0006C4000065
+:10C0400017FEBFE01703C01017FDBFE01507C010B3
+:10C050001766A0D00C008110262100101766A0D012
+:10C060000C808010261E001017FEBFE043028010D7
+:10C07000CC3F001117FEBFE017038010CC3F4011EA
+:10C0800017FEBFE0170380103AD20410CC3F801196
+:10C0900017FEBFE0170380103AD40410CC3F801085
+:10C0A00017FEFFE01703C0183AD606181501C0D8CE
+:10C0B000150080D83A880F303A880D283A880B202E
+:10C0C0007401020104BE2C2180C702801766A0D033
+:10C0D0008C0080102602001017FD3FE1C00C3B8051
+:10C0E00017FEBFE043028010CC3F8010A000C010BC
+:10C0F0001E1B0018C800C0101E030018600080102E
+:10C100001E0E001006280000A001C0101E1D001801
+:10C11000580480101E240010B40182001757B91073
+:10C120004400C010B40182001557F91017FD3FE11B
+:10C1300040133D8015FFBFE006240000B4018200DB
+:10C140001757B9104400C010B40182001557F910F8
+:10C1500017FD3FE180F7388015FFBFE0061B0000A8
+:10C16000B40182001757B9104400C010B401820016
+:10C170001557F91017FD3FE1C041258015FFBFE0BD
+:10C1800006120000B40182001757B9104400C01015
+:10C19000B40182001557F91017FD3FE1404A2A808B
+:10C1A00015FFBFE006090000B40182001757B9105F
+:10C1B0004400C010B40182001557F91017FD3FE18B
+:10C1C000007D3C8015FFBFE03A88010017FFBFE00B
+:10C1D000A0FDBF101E02001017FFBFE0065C0000AC
+:10C1E00017FEBFE017048010E0FFBF101E4C0010C8
+:10C1F00017FEBFE0170480103AD6061017FEBFE006
+:10C20000170480103AD204100CC0BF103AB0861840
+:10C2100017FEBFE0170480103A920410EC3F801024
+:10C220003AB0861817FEBFE0170480103A96041043
+:10C230003AB084182C00FC103400B800263880185E
+:10C2400017FEBFE01704C01017FDBFE017068010EF
+:10C25000170E80102632801817FEBFE01704C0109A
+:10C2600017FDBFE017068010170F8010262C8018CE
+:10C2700017FEBFE01704C01017FDBFE017068010BF
+:10C28000171080102626801817FDBFE017068010B3
+:10C29000170AC01017FDBFE0170680101710801096
+:10C2A000261F80181766A0D00C008110260F0010E2
+:10C2B0001766A0D00C808010260C001017FEBFE07F
+:10C2C00043028010CC3F80103A880B1074010201A9
+:10C2D00004C82C2180C702801766A0D08C00801073
+:10C2E0002602001017FD3FE1C00C3B8017FEBFE0A7
+:10C2F0001703C01017FDBFE017068010170A0011C2
+:10C3000017FDBFE017068010150080D88400C0011B
+:10C3100017FEBFE13A880B203A88091840A53980FA
+:10C32000B40182001755B9104400C010B401820056
+:10C330001555F9108400000180F3288017FD3FE1B6
+:10C34000807428808400000140FF288084008000E1
+:10C350003A8837E01701C0DF170000DF0402C0DEB3
+:10C360003A2800F804F9FFDE1506C0DF150500DFE6
+:10C37000040500DF15FD3FE115FC7FE115FBBFE182
+:10C3800015FF3FE017FDBFE02603001017FDBFE0DB
+:10C39000170080101E0200103A880500063F0000BA
+:10C3A00040E9288017FBBFE0A00180101E060010A6
+:10C3B00017FDBFE01700801017FC7FE13A880910D5
+:10C3C00040503C8015FFBFE017FFBFE0260600107D
+:10C3D00017FFBFE0170280104400C01017FFBFE036
+:10C3E0001502C010062B000004060001C08229803F
+:10C3F00015FFBFE017FFBFE01E03001040EF2880CD
+:10C400003A8805000625000017FBBFE0A001801058
+:10C410001E04001017FDBFE01700C01017FFBFE09B
+:10C420001500C01017FFBFE017FCFFE01501C0109A
+:10C4300017FFBFE04400C0001502C01017FCBFE0AA
+:10C44000172CC01017FFBFE01505C01017FCBFE088
+:10C4500017FFFFE0152CC01017FCBFE0172B801052
+:10C460002606001017FCBFE0172B801017FF3FE1D6
+:10C470003AE83E1015FEBFE00601000015FE3FE061
+:10C4800017FFBFE0170080102602001017FF3FE1E2
+:10C49000808D258040EF288017FFBFE03A8837E085
+:10C4A0001701C0DF170000DF0402C0DE3A2800F8E1
+:10C4B00004FAFFDE1505C0DF150400DF040400DF09
+:10C4C00015FC3FE117FCBFE01701801015FDBFE030
+:10C4D00040E9288017FCBFE017028010C4FFFF105E
+:10C4E00017FCBFE01502C01017FCBFE01702801058
+:10C4F0001E2B001017FDBFE0172C801015FFBFE0AA
+:10C500000614000017FFFFE017FCBFE01E058018AF
+:10C5100017FFBFE01705C01017FDBFE0152CC010B6
+:10C52000060E000017FFBFE01705801017FCFFE0A4
+:10C530001E05801817FCBFE01705C01017FFBFE0ED
+:10C540001505C0100605000017FFBFE01705801095
+:10C5500015FFBFE017FFBFE01EEA3F1017FDBFE069
+:10C56000172B80102606001017FDBFE0172B801038
+:10C5700017FC3FE13AE83E1015FEBFE0060100005F
+:10C5800015FE3FE017FCBFE01700801026020010E8
+:10C5900017FC3FE140B0258017FC3FE10086298071
+:10C5A00040EF28803A8801003A8837E01701C0DF61
+:10C5B000170000DF0402C0DE3A2800F804FCFFDEAA
+:10C5C000150300DF040300DF15FE3FE115FD7FE1E9
+:10C5D00017FDBFE0172C801015FFBFE00609000013
+:10C5E00017FFBFE01700801017FEFFE01E02801843
+:10C5F00017FFBFE00606000017FFBFE01705801019
+:10C6000015FFBFE017FFBFE01EF53F103A88050099
+:10C610003A8837E0170000DF0401C0DE3A2800F84E
+:10C6200004FDFFDE1502C0DF150100DF040100DF9D
+:10C6300015FF3FE11796A0D0260400101796A0D052
+:10C6400017FF3FE13AE83E1015FFBFE017FFBFE0DC
+:10C650001567A0D017FFBFE0580080101E03001020
+:10C660007401820004D0AC10060200007401820044
+:10C6700004D1AC103A880D1017FF7FE1740102015C
+:10C6800004D22C2180C7028017FFBFE03A8837E030
+:10C690001701C0DF170000DF0402C0DE3A2800F8EF
+:10C6A00004FDFFDE1502C0DF150100DF040100DF1D
+:10C6B00015FF3FE1440080001597A0D0C0242580DD
+:10C6C00017FF3FE1C0AB428004FFFFDE150000DF33
+:10C6D0003A8839D8059A20D0159820D0159920D0BD
+:10C6E0003A8801003A8837E0170000DF0401C0DE15
+:10C6F0003A2800F804F9FFDE1506C0DF150500DF53
+:10C70000040500DF3A88052015FD7FE115FCBFE137
+:10C7100015FBFFE105FEBFE03A88090080F32880A1
+:10C7200004060001C082298015FFBFE017FFBFE0AB
+:10C730001E0A00101766A0D00C01801026030010FE
+:10C740007401020104DD2C21C0D902803A8809005D
+:10C7500040FF288017FFBFE00617000017FFBFE06B
+:10C7600017FDFFE01501C01017FFBFE017FCFFE049
+:10C770001502C01017FFBFE003FEFFE00505C01063
+:10C7800017FFBFE017FBFFE01503C01017FFBFE066
+:10C790001702C0E01504C010179BE0D017FFBFE0E0
+:10C7A0001500C01017FFBFE0159BA0D03A88090004
+:10C7B00040FF288017FFBFE03A8837E01701C0DF4D
+:10C7C000170000DF0402C0DE3A2800F804FBFFDE99
+:10C7D0001504C0DF150300DF040300DF15FD3FE192
+:10C7E0003A88090080F3288015FF3FE0179BA0D00E
+:10C7F00015FEBFE00608000017FEFFE017FDBFE0D2
+:10C800002608801817FEBFE015FFBFE017FEBFE047
+:10C810001700801015FEBFE017FEBFE01EF63F10A8
+:10C82000060100003A88010017FEBFE01E04001058
+:10C8300040CD28803A88090040FF2880060D00007E
+:10C8400017FFBFE02604001017FEBFE0170080109E
+:10C8500015FFBFE00603000017FEBFE017008010C1
+:10C86000159BA0D017FE3FE1008629803A88090079
+:10C8700040FF28803A8837E01701C0DF170000DF4B
+:10C880000402C0DE3A2800F804F6FFDE1509C0DF16
+:10C89000150800DF040800DF15F83FE115FE3FE052
+:10C8A00015FC3FE017F8BFE01703801015FBBFE051
+:10C8B000179BA0D015FFBFE0064C000017FFBFE09C
+:10C8C0001700801015FABFE017FFBFE003058010C6
+:10C8D000CC3F80102607001017FFBFE00305C010F3
+:10C8E00017FBBFE043028010CC3FC018CC3F801044
+:10C8F0001E37801817FFBFE01701801026050010B3
+:10C9000017FFBFE01701C01017FBBFE0170480102E
+:10C910001E31801817FFBFE0170280102605001097
+:10C9200017FFBFE01702C01017FBBFE0170380100E
+:10C930001E2B801817FFBFE0170380102629001058
+:10C9400017FEBFE0261F001017FEBFE01703801080
+:10C95000261C001017F83FE1C0533B8015F9BFE0DB
+:10C9600017F9BFE0261700103A88090040FF288019
+:10C9700017FEBFE01703801017FEFFE01704C01872
+:10C980003A880B1817F93FE13AE83E1015FDBFE071
+:10C990003A88090080F3288017FDBFE026070010C1
+:10C9A0008400000180F3288017F93FE1807428801B
+:10C9B0008400000140FF288006020000440080003F
+:10C9C00015FCBFE017FFBFE015FEBFE00605000045
+:10C9D0003A880100060300003A88010006010000C1
+:10C9E0003A88010017FABFE015FFBFE017FFBFE06C
+:10C9F0001EB23F1017FEBFE02614001017FEBFE066
+:10CA000017038010261100103A88090040FF288083
+:10CA100017FEBFE01703801017FEFFE01704C018D1
+:10CA20003A880B1817F83FE13AE83E1015FDBFE0D1
+:10CA30003A88090080F3288017FDBFE01E0A001025
+:10CA40004400800015FCBFE00607000084FDBF0025
+:10CA500015FDBFE0B40182001755B9104400C010A5
+:10CA6000B40182001555F91017FCBFE01E05001037
+:10CA7000B40182001757B910C4FFFF10B40182003F
+:10CA80001557F91017FDBFE03A8837E01701C0DFEE
+:10CA9000170000DF0402C0DE3A2800F804FAFFDEC7
+:10CAA0001505C0DF150400DF040400DF15FD3FE1BC
+:10CAB00015FC7FE117FDBFE04400C01084FFBF00FC
+:10CAC0003A70841815FFBFE017FCBFE01E0300108A
+:10CAD00017FFBFE00405801015FFBFE084000001D0
+:10CAE00080F328801764E0D017FFBFE03A888518EC
+:10CAF0003A8809104043288015FEBFE084000001F9
+:10CB000040FF288017FEBFE0260C001017FCBFE096
+:10CB10001E0A001017FEBFE0170380100405C010A6
+:10CB200017FEBFE01503C01017FEBFE0170480100A
+:10CB300004FBFF1017FEBFE01504C01017FEBFE096
+:10CB40003A8837E01701C0DF170000DF0402C0DEBB
+:10CB50003A2800F804FDFFDE1502C0DF150100DFF2
+:10CB6000040100DF15FF3FE18400000180F328800D
+:10CB700017FF3FE1807428808400000140FF288077
+:10CB80003A8801003A8837E01701C0DF170000DF5C
+:10CB90000402C0DE3A2800F804FDFFDE150200DFC3
+:10CBA000040200DF15FE3FE11719A0D01764E0D0A2
+:10CBB0003AC8C51015FFBFE017FEBFE01E03001006
+:10CBC00017FFBFE004FBBF1015FFBFE017FFBFE07A
+:10CBD0003A8837E0170000DF0401C0DE3A2800F889
+:10CBE00004F8FFDE150700DF040700DF15F93FE159
+:10CBF000C5FD3FE015FE3FE01795A0D015FFBFE053
+:10CC0000063A000017FFBFE0170680102633001019
+:10CC100017FFBFE0170A801015FBBFE017FFBFE04A
+:10CC20001700C01017F9BFE03AF0861817FBBFE0F5
+:10CC30003A7084181E2A001085FD3FE03400A000E1
+:10CC400015FCBFE00618000017FBBFE03AD606103F
+:10CC500017FBBFE03AD204100CC0BF103AB08618E0
+:10CC600017FBBFE03A920410EC3F80103AB08618F0
+:10CC700017FBBFE03A9604103AB0841817FCFFE0A7
+:10CC80003A70841815FABFE017FABFE026030010C7
+:10CC900083FDBFE04400801085FDBFE017FCBFE0CE
+:10CCA0007AD0041015FCBFE017FCBFE01EE63F1071
+:10CCB00083FDBFE0C3FDFFE02E09801883FDBFE0C8
+:10CCC000C5FDBFE017FFBFE015FEBFE0C3FDBFE03D
+:10CCD00018088010260C0010060100003A88010098
+:10CCE00017FFBFE0040F801015FFBFE01795E0D0DD
+:10CCF0001730A0D0240F80103A88851817FFFFE066
+:10CD000036C0BF18060100003A88010017FEBFE0D8
+:10CD100026030010177DE0D017FEBFE01509C010F4
+:10CD200017FEBFE03A8837E0170000DF0401C0DEDD
+:10CD30003A2800F804F7FFDE1508C0DF150700DF0A
+:10CD4000040700DF15FC3FE115FB7FE115FABFE1A9
+:10CD500015F9FFE115FE3FE017F93FE18008248057
+:10CD600015FDBFE017FDBFE01E0200103A88050068
+:10CD700006D400001795A0D01E0200103A880500C6
+:10CD800006D0000017FCBFE02602001017FBBFE032
+:10CD90001E22001040CD288017FCBFE03AD60610B6
+:10CDA00017FCBFE03AD204100CC0BF103AB086188E
+:10CDB00017FCBFE03A920410EC3F80103AB086189E
+:10CDC00017FCBFE03A9604103AB0881817FBBFE092
+:10CDD0003AD6061017FBBFE03AD204100CC0BF10C1
+:10CDE0003AB0861817FBBFE03A920410EC3F80106F
+:10CDF0003AB0861817FBBFE03A9604103AB0841890
+:10CE00003A880D103A880B207401020104E62C21A7
+:10CE100080C702803A88050006AA00001795A0D0B6
+:10CE200015FFBFE00664000017FFBFE01700801089
+:10CE300017FCFFE01E15801817FFBFE017FAFFE090
+:10CE40001506C010177DE0D017FFBFE01509C01010
+:10CE500017F9BFE04400C01017FFBFE01501C01074
+:10CE600017FFBFE01702C0E01508C01017FFBFE0B2
+:10CE700017FBFFE0150AC01017FFBFE017FDFFE02A
+:10CE8000150EC01017FFBFE0068E000017FEBFE0B2
+:10CE90002603001017FEBFE017088010264300107D
+:10CEA00017FFBFE0170680101E05001017FFBFE038
+:10CEB00015FEBFE017FEBFE015080010063B00009E
+:10CEC0001702C0E0740182003A88851803563211B7
+:10CED00017FFBFE01708C010740182003A88851858
+:10CEE0000356B210CC3FC020CC3F8010362F8018A4
+:10CEF00017FEBFE01E03001017FFBFE015FEBFE0E6
+:10CF0000062A000017FFBFE01708C0107401820056
+:10CF10003A8885180356321117FEBFE01708C01073
+:10CF2000740182003A8885180356B210CC3FC020A5
+:10CF3000CC3F80102E03801817FFBFE015FEBFE026
+:10CF4000061A000017FFBFE01708C0107401820026
+:10CF50003A8885180356321117FEBFE01708C01033
+:10CF6000740182003A8885180356B210CC3FC02065
+:10CF7000CC3F80101E0D801817FFBFE01709C010AE
+:10CF800017FEBFE0170980103A880B103A8809187D
+:10CF900040D624803A88071017FFBFE01709801099
+:10CFA0001E02801817FFBFE015FEBFE017FFBFE0AD
+:10CFB000040F801015FFBFE01795E0D01730A0D008
+:10CFC000240F80103A88851817FFFFE03696BF18A7
+:10CFD00017FEBFE02628001017FEBFE015FFBFE0D8
+:10CFE00017FFBFE017FDFFE0150EC01017FFBFE0F1
+:10CFF00017FCFFE01500C01017FD3FE1C02F258092
+:10D000004400C01017FFBFE01501C010B40182003A
+:10D010001750B9103A88071017FFBFE01502C0106B
+:10D0200017FFBFE0C4FFFF001503C01017FFBFE0EC
+:10D03000C4FFFF001504C01017FFBFE0C4FFFF00CE
+:10D040001505C01017FFBFE017FAFFE01506C01066
+:10D0500017FFBFE01702C0E01508C01017FCFFE083
+:10D0600017FABFE03AF0861817FBBFE03A70841851
+:10D070001E070010060200003A8805000611000095
+:10D0800017FFBFE0C400C0001507C0100603000072
+:10D0900017FFBFE00401C0001507C010177DE0D0E6
+:10D0A00017FFBFE01509C01017FFBFE017FBFFE037
+:10D0B000150AC01017FFBFE0C4FFFF00150BC0101A
+:10D0C00017FFBFE03A8837E01701C0DF170000DF25
+:10D0D0000402C0DE3A2800F804F8FFDE1507C0DFBE
+:10D0E000150600DF040600DF15FC3FE115FB7FE1BC
+:10D0F00015FABFE115FE3FE017FABFE0D8FFBF10F9
+:10D100001E02001015FD3FE00603000017FA3FE184
+:10D110008008248015FDBFE01795A0D01E020010E6
+:10D120003A880500062C00001795A0D015FFBFE037
+:10D130000622000017FFBFE0170680102619001016
+:10D1400017FDBFE02604001017FFBFE0170E801088
+:10D1500017FDFFE01E15801817FFBFE01700C01075
+:10D1600017FCBFE03AF0861817FBBFE03A7084184E
+:10D170001E070010040F80013A880B0017FF3FE1E3
+:10D18000408E088017FEBFE04400801015FEBFE00F
+:10D19000179CA0D017FFFFE01E058018159C20D01B
+:10D1A000060300003A880100060100003A880100E9
+:10D1B00017FFBFE0040F801015FFBFE01795E0D008
+:10D1C0001730A0D0240F80103A88851817FFFFE091
+:10D1D00036D8BF1817FEBFE03A8837E01701C0DF26
+:10D1E000170000DF0402C0DE3A2800F804ECFFDE7E
+:10D1F0001513C0DF151200DF041200DF15F23FE146
+:10D2000017F2BFE01703801015FBBFE017FBBFE06C
+:10D2100003008010CC3F8010BA9004100C0F8010D7
+:10D2200017FBFFE03A88851815FABFE017FABFE050
+:10D230000B018010CCFFBF103AD20410CCFFBF10FE
+:10D24000CC3FC01017FABFE00B018010CCFFBF101D
+:10D250003A920410CCFFBF103AB0841815F9BFE021
+:10D2600017F2BFE01704C01017F9BFE02E23801893
+:10D270001766A0D00C008110261700101766A0D0EA
+:10D280000C4080102614001017F2BFE017040011A4
+:10D2900017FABFE00B018010CCFFBF103AD2041088
+:10D2A000CCFFBF10CC3FC01017FABFE00B018010BD
+:10D2B000CCFFBF103A920410CCFFBF103AB08418D4
+:10D2C000040280103A880D103A880B207401020184
+:10D2D00004F42C2180C70280B40182001765B910C4
+:10D2E0004400C010B40182001565F91017F23FE147
+:10D2F00080DB3D8004F8BF000692010017FABFE012
+:10D300008B0180108DF8BFE08BF8BFE0265600102F
+:10D3100017F9BFE04C0080102604001017FAFFE058
+:10D3200017F9BFE03A8885180500001017F2BFE032
+:10D330001707801015F3BFE017FBBFE0170480103C
+:10D3400015F4BFE005F53FE04404800045F5BFE07B
+:10D3500017FABFE00B0180108DF5BFE004F3BFE0CA
+:10D36000840140013A880910C0D726803A88071006
+:10D3700017FABFE08D01C01017F9BFE0440080101C
+:10D380007AD004103A880B1017FA3FE1C0D72680F4
+:10D390003A3084008DFEBFE08BFEBFE01E0200101D
+:10D3A000C4FFBF008DFEBFE017FABFE08BF8FFE0BF
+:10D3B0008D01C0108BFEFFE08BF8BFE0262A80189D
+:10D3C0001766A0D00C008110261E00101766A0D092
+:10D3D0000C408010261B00108BF87FE18BFEBFE114
+:10D3E00017F2BFE017078010CC3FC01117F2BFE063
+:10D3F000170780103AD20410CC3F801017F2FFE0DC
+:10D400001707C0183AD40618CC3FC01817F23FE1EE
+:10D41000170700213AD60820150200D91501C0D8F7
+:10D42000150080D87401020104FE2C2180C70280FF
+:10D430001766A0D08C0080102602001017F23FE182
+:10D44000C00C3B80B40182001765B9104400C010C5
+:10D45000B40182001565F91017F23FE180DB3D80D1
+:10D4600004F8BF000637010017FA3FE140B33D80E2
+:10D4700017FBBFE003008010CC3F8010BA9004106F
+:10D480000C0F80100402801015FDBFE017F2BFE002
+:10D490001704C01017FDBFE03AC8871817F2BFE0A5
+:10D4A0001504C01017F2BFE01703C01017FDBFE04E
+:10D4B0003A88871817F2BFE01503C0101766A0D08E
+:10D4C0000C008110261F00101766A0D00C408010A1
+:10D4D000261C001017F2BFE017078010CC3F801108
+:10D4E00017F2BFE0170780103AD20410CC3FC011EA
+:10D4F00017F2BFE0170780103AD40410CC3F801019
+:10D5000017F2FFE01707C0183AD6061817FA3FE1DE
+:10D510000B000021CCFF3F2117FA7FE18B0040294F
+:10D52000CCFF7F29150340D9150200D91501C0D8B9
+:10D53000150080D817F97FE174010201040C2D2138
+:10D5400080C70280179EA0D015FFBFE006AA00008A
+:10D5500017FFBFE08B018010CCFFBF102607001023
+:10D5600017FFBFE08B01C01017FABFE08B008010DF
+:10D57000CCFFFF18CCFFBF101E95801817FFBFE02F
+:10D580000B028010CCFFBF102607001017FFBFE072
+:10D590000B02C01017FABFE00B008010CCFFFF1881
+:10D5A000CCFFBF101E8C801817FFBFE0170480103F
+:10D5B0002605001017FFBFE01704C01017F2BFE0E8
+:10D5C000170780101E86801817FBBFE01704801015
+:10D5D0003AD6061017FBBFE0170480103AD20410A9
+:10D5E0000CC0BF103AB0861817FBBFE017048010BC
+:10D5F0003A920410EC3F80103AB0861817FBBFE057
+:10D60000170480103A9604103AB084182C00FC10CD
+:10D610003400B8001E2D801817FFBFE017068010D9
+:10D6200015F7BFE017FFBFE01705C010F400820038
+:10D63000040699101E25801817F7BFE01703801005
+:10D640002622001017F7BFE01703801015F6BFE081
+:10D650008DFC3FE0061700008BFCBFE017F6FFE0F3
+:10D6600084008010BA9004103A8885181700801042
+:10D670001701C01017F2BFE0170680101E0A8018AD
+:10D680008BFCBFE017F6FFE084008010BA90041016
+:10D690003A888518170080101700C01017FBBFE0EC
+:10D6A00017048010260B80188BFCBFE0440080100C
+:10D6B0008DFCBFE017F6BFE08B0180108BFCFFE014
+:10D6C000CCFFBF1036E4BF18064800003A880100BE
+:10D6D000060100003A88010017FBBFE01704801024
+:10D6E0003AD6061017FBBFE0170480103AD2041098
+:10D6F0000CC0BF103AB0861817FBBFE017048010AB
+:10D700003A920410EC3F80103AB0861817FBBFE045
+:10D71000170480103A9604103AB084182C00FC10BC
+:10D720003400B8002608801817FFBFE017038010E8
+:10D730002605001017FFBFE01703C01017FBBFE05E
+:10D74000170480101E288018B40182001763B910D6
+:10D750004400C010B40182001563F91017FFBFE048
+:10D7600017058010260D00103A88090040FF288018
+:10D7700017FFBFE01705801017FFFFE01706C0185E
+:10D780003A880B1817F23FE13AE83E1015FDBFE06A
+:10D790003A88090080F328800602000044FDBF009B
+:10D7A00015FDBFE017FDBFE026070010B4018200A1
+:10D7B0001765B9104400C010B40182001565F91056
+:10D7C00017F23FE180DB3D8017FDBFE0065D000002
+:10D7D0003A880100060500003A88010006030000AF
+:10D7E0003A880100060100003A88010017FFBFE0F7
+:10D7F0001700801015FFBFE017FFBFE01E543F1059
+:10D8000017FBBFE017048010E0FFBF101E120010CE
+:10D8100017FBBFE01704C01017F2BFE01706801017
+:10D82000170E8010260C801817FBBFE01704C010DD
+:10D8300017F2BFE017068010170F80102606801819
+:10D8400017FBBFE01704C01017F2BFE017068010E7
+:10D85000171080101E1280181766A0D00C008110BF
+:10D86000260600101766A0D00C408010260300107A
+:10D870007401020104162D21C0D90280B401820076
+:10D880001765B9104400C010B40182001565F91085
+:10D8900017F23FE180DB3D80840080000629000014
+:10D8A0001766A0D00C008110260F00101766A0D0BC
+:10D8B0000C408010260C001017FABFE08B0080107F
+:10D8C000CCFFBF103A880B1074010201041D2D21FA
+:10D8D00080C702801766A0D08C008010260200103E
+:10D8E00017F23FE1C00C3B8017FA3FE140B33D80A7
+:10D8F00017F2BFE01707C01017F2BFE0170680103D
+:10D90000170A001117F2BFE017068010150080D823
+:10D91000C400C00117FBBFE13A880B203A88091800
+:10D9200040A53980B40182001764B9104400C010CA
+:10D93000B40182001564F91017F23FE180DB3D80ED
+:10D94000840080003A8837E01701C0DF170000DF4D
+:10D950000402C0DE3A2800F804EFFFDE1510C0DF35
+:10D96000150F00DF040F00DF3A8805203A880728EA
+:10D9700015F5BFE10DF7BFE03A8805180DF6BFE0D9
+:10D980001766A0D00C418010261A001017F5BFE0D2
+:10D99000170400120BF6BFE117F5BFE01707801060
+:10D9A000CC3FC01117F5BFE0170780103AD2041022
+:10D9B000CC3F801017F5FFE01707C0183AD40618BF
+:10D9C000CC3FC01817F53FE1170700213AD60820D1
+:10D9D0000BF77FE1150340D9150200D91501C0D816
+:10D9E000150080D83A880B407401020104242D21CF
+:10D9F00080C702803A88090080F3288017F5BFE0CD
+:10DA00001703801004FEFF1017F5BFE01503C010C8
+:10DA100017F5BFE01703801015FEBFE017F5BFE054
+:10DA2000170480100402801015FDBFE017FDFFE011
+:10DA300017F5BFE01504C01017FDBFE04C008010C3
+:10DA40002604001017FDBFE017FEFFE03A88851896
+:10DA50000500001017FDBFE03A88071017FEBFE071
+:10DA60000D01C01017FEBFE00BF6FFE00D00C01067
+:10DA700017FEBFE00BF7FFE08D00C01017FE3FE17F
+:10DA800040B33D8017F5BFE017078010D8FFBF10E7
+:10DA90001E0F001017F5BFE0170680101E070010BC
+:10DAA00040CD288017F53FE180DB3D803A880900B2
+:10DAB00040FF288084F7BF000647000017F5BFE04D
+:10DAC00017068010170A801015FFBFE0060500003A
+:10DAD00017F5BFE0170780103A88091080023B80D5
+:10DAE00015FFBFE017FFBFE015F8BFE017F5BFE077
+:10DAF0001707801015F9BFE005FA3FE044048000E5
+:10DB000045FABFE017FEBFE00B0180108DFABFE0C1
+:10DB100004F8BFE0840140013A880910C0D726808C
+:10DB20003A88071017FEBFE08D01C01017FDBFE057
+:10DB3000440080107AD005103A880B1017FE3FE1A0
+:10DB4000C0D726803A3084003A88071017FEBFE01D
+:10DB50008D01C01017FEBFE08B018010CCFFBF10FD
+:10DB60001E03001017FEBFE0C4FFFF008D01C010B0
+:10DB700017F5BFE01703801004FBBF1015FCBFE0D2
+:10DB800017FCBFE017FFFFE01503C01017F5BFE05B
+:10DB90001707C01017FCBFE01504C010B4018200C5
+:10DBA0001766B9104400C010B40182001566F91060
+:10DBB00017FDFFE017F5BFE01504C01017F57FE172
+:10DBC00044040001809E3A8015FBBFE03A880900BA
+:10DBD00040FF288017FBBFE03A8837E01701C0DF1D
+:10DBE000170000DF0402C0DE3A2800F804FEFFDE62
+:10DBF000150100DF040100DF15FF3FE117FFBFE063
+:10DC00000B008010CCFFBF103AD204103A880710E6
+:10DC100017FFBFE00B008010CCFFBF103A9204103A
+:10DC20003AB084183A88071017FFBFE00D00C01003
+:10DC300017FFBFE08B008010CCFFBF103AD204105A
+:10DC40003A88071017FFBFE08B008010CCFFBF1091
+:10DC50003A9204103AB084183A88071017FFBFE0D0
+:10DC60008D00C01017FFBFE00B018010CCFFBF106C
+:10DC70003AD204103A88071017FFBFE00B0180105A
+:10DC8000CCFFBF103A9204103AB084183A880710BB
+:10DC900017FFBFE00D01C01017FFBFE08B01801020
+:10DCA000CCFFBF103AD204103A88071017FFBFE02C
+:10DCB0008B018010CCFFBF103A9204103AB0841848
+:10DCC0003A88071017FFBFE08D01C0103A880100A5
+:10DCD0003A8837E0170000DF0401C0DE3A2800F878
+:10DCE00004FEFFDE150100DF040100DF0B9DA0D064
+:10DCF000CCFFBF10282C81101E0A0010177DA0D069
+:10DD0000CCFF9F100D9DA0D00B9DA0D0CCFFBF10CD
+:10DD1000282C81101E0300100B9DA0D0042C811014
+:10DD20000D9DA0D0179EA0D015FFBFE0060F0000EC
+:10DD300017FFBFE08B01C0100B9DA0D0CCFFFF18D8
+:10DD4000CCFFBF101E0680180B9DA0D04400801091
+:10DD50000D9DA0D0179EA0D015FFBFE03A8801000E
+:10DD600017FFBFE01700801015FFBFE017FFBFE0EF
+:10DD70001EEF3F100B9DA0D04400C0100D9DE0D0C1
+:10DD80003A8837E0170000DF0401C0DE3A2800F8C7
+:10DD900004FAFFDE1505C0DF150400DF040400DF10
+:10DDA00015FD3FE115FC7FE117FDBFE04402801047
+:10DDB0003A88071084FFBF003A70841815FFBFE04F
+:10DDC0008400000180F3288017FFBFE00409C01021
+:10DDD00017FCBFE03A8885183A880910404328802C
+:10DDE00015FEBFE08400000140FF288017FEBFE061
+:10DDF0002610001017FCBFE0BAD0051004078010F1
+:10DE000015FFBFE017FEBFE01703C01017FFBFE00C
+:10DE10003A88871817FEBFE01503C01017FEBFE051
+:10DE20001704C01017FFBFE03AC8871817FEBFE0FD
+:10DE30001504C01017FEBFE03A8837E01701C0DFB5
+:10DE4000170000DF0402C0DE3A2800F804FFFFDEFE
+:10DE5000150000DF3A8839D81719A0D004F7BF1091
+:10DE60003A8837E0170000DF0401C0DE3A2800F8E6
+:10DE700004FDFFDE1502C0DF150100DF040100DF35
+:10DE800015FF3FE18400000180F3288017FF3FE188
+:10DE9000807428808400000140FF28803A880100B7
+:10DEA0003A8837E01701C0DF170000DF0402C0DE48
+:10DEB0003A2800F804F8FFDE1507C0DF150600DF7A
+:10DEC000040600DF15FA3FE117FABFE017068010DD
+:10DED00015FDBFE017FABFE01703801015FCBFE087
+:10DEE00017FCBFE003008010CC3F8010BA900410F4
+:10DEF0000C0F801017FCFFE03A88851815FBBFE077
+:10DF000017FBBFE003008010CC3F80106004C010FE
+:10DF10001E030018A00480101E500010066B0000A5
+:10DF2000B40182001775B7104400C010B40182001C
+:10DF30001575F71017FDBFE0172C801015FFBFE017
+:10DF40000642000017FFBFE017008010263B0010BC
+:10DF500017FFBFE01700C010176BA0D0263880183D
+:10DF600017FFBFE0170380101E350010B4018200B8
+:10DF70001751F910B40182001770B710170A8010FA
+:10DF80003AD60810B40182001770B710170A801033
+:10DF90003AD204100CC0BF103AB08820B4018200FD
+:10DFA0001770B710170A80103A920410EC3F8010D7
+:10DFB0003AB08820B40182001770B710170A801099
+:10DFC0003A9604103AB084203A88871817FFBFE0C9
+:10DFD000170080103AD6081017FFBFE01700801016
+:10DFE0003AD204100CC0BF103AB0882017FFBFE02F
+:10DFF000170080103A920410EC3F80103AB088204D
+:10E0000017FFBFE0170080103A9604103AB0842042
+:10E010003A888518840C40013A880910C0050D80A3
+:10E020004400C01017FFBFE01503C0101769A0D04F
+:10E03000440080101569A0D0060100003A88010054
+:10E0400017FFBFE01705801015FFBFE017FFBFE007
+:10E050001EBC3F1015FE3FE006240000B401820004
+:10E060001776B7104400C010B40182001576F7107F
+:10E0700017FBBFE01701801017FD7FE13A880910F8
+:10E0800040503C8015FFBFE017FFBFE0260D001099
+:10E0900017FFBFE017038010260A001017FFBFE02C
+:10E0A000150300101769A0D0C4FFBF101569A0D0D8
+:10E0B000B40182001777B7104400C010B401820089
+:10E0C0001577F71015FE3FE006080000B401820046
+:10E0D0001784B7104400C010B40182001584F710F3
+:10E0E000C4FFBF0015FEBFE03A88010084000001B4
+:10E0F00080F3288017FA3FE18074288084000001B3
+:10E1000040FF288017FEBFE03A8837E01701C0DFE4
+:10E11000170000DF0402C0DE3A2800F804F9FFDE31
+:10E120001506C0DF150500DF040500DF15FB3FE124
+:10E1300017FBBFE01703801015FEBFE017FEBFE01E
+:10E1400003008010CC3F8010BA9004100C0F801098
+:10E1500017FEFFE03A88851815FDBFE017FDBFE008
+:10E1600003008010C5FCBFE0C3FCBFE0A004C010EA
+:10E170001E0E0018C804C0101E0300186004801092
+:10E180001E06001006140000A005C0101E0700188F
+:10E19000E00580101E090010060F000017FB3FE18C
+:10E1A00040283E8015FFBFE00613000017FB3FE14B
+:10E1B00000173E8015FFBFE0060F0000B40182008B
+:10E1C000177DB7104400C010B4018200157DF71010
+:10E1D00015FF3FE006080000B40182001789B71060
+:10E1E0004400C010B40182001589F710C4FFBF00BD
+:10E1F00015FFBFE03A8801008400000180F3288009
+:10E2000017FB3FE1807428808400000140FF2880D4
+:10E2100017FFBFE03A8837E01701C0DF170000DFC3
+:10E220000402C0DE3A2800F804F9FFDE1506C0DF5C
+:10E23000150500DF040500DF15FB3FE117FBBFE01C
+:10E240001706801015FFBFE017FBBFE01703801013
+:10E2500015FEBFE017FEBFE003008010CC3F80102A
+:10E26000BA9004100C0F801017FEFFE03A88851852
+:10E2700015FDBFE017FDBFE01701801017FF7FE11C
+:10E280003A88091040503C8015FCBFE017FCBFE005
+:10E29000261F001017FCBFE0170380102616001081
+:10E2A00017FFBFE0032D8010CC3F80102605001023
+:10E2B00017FDBFE003008010CC3F8010A005801048
+:10E2C0001E18001017FCBFE0150300101769A0D03E
+:10E2D000C4FFBF101569A0D017FCBFE005040010F3
+:10E2E000B4018200177BB7104400C010B401820053
+:10E2F000157BF710060B0000B4018200177CB710E5
+:10E300004400C010B4018200157CF710060500001F
+:10E31000B40182001787B7104400C010B401820016
+:10E320001587F7103A8805003A8837E01701C0DFF3
+:10E33000170000DF0402C0DE3A2800F804F8FFDE10
+:10E340001507C0DF150600DF040600DF15FA3FE100
+:10E3500017FABFE01706801015FDBFE017FABFE0FF
+:10E360001703801015FCBFE017FCBFE0030080100E
+:10E37000CC3F8010BA9004100C0F801017FCFFE007
+:10E380003A88851815FBBFE017FBBFE043008010FB
+:10E39000CC3F80101E10001017FDBFE04400C000ED
+:10E3A000052DC010177DE0D017FDBFE0152EC01061
+:10E3B000B40182001778B7104400C010B401820085
+:10E3C0001578F710840C80008DFFBFE044008000BA
+:10E3D00045FFBFE00618000017FBBFE017018010E3
+:10E3E0001E080010B40182001779B7104400C01055
+:10E3F000B40182001579F7104400800045FFBFE0AA
+:10E4000006060000B4018200177AB7104400C0105D
+:10E41000B4018200157AF71045FF3FE017FBBFE01B
+:10E4200043008010CC3F8010FAD706103A88851838
+:10E430007AD005108DFFBFE043FFBFE02617001024
+:10E4400017FDBFE0172C801015FEBFE0061000007E
+:10E4500017FEBFE0170080102609001017FEBFE06E
+:10E460001700C010176BA0D0260680188BFFBFE0E6
+:10E470003A880B1017FE3FE140443E800601000041
+:10E480003A88010017FEBFE01705801015FEBFE0B7
+:10E4900017FEBFE01EEE3F100612000017FBBFE0A4
+:10E4A0001701801017FD7FE13A88091040503C8029
+:10E4B00015FEBFE017FEBFE0260500108BFFBFE092
+:10E4C0003A880B1017FE3FE140443E8006050000ED
+:10E4D000B40182001786B7104400C010B401820056
+:10E4E0001586F7103A8805003A8837E01701C0DF33
+:10E4F000170000DF0402C0DE3A2800F804FCFFDE4B
+:10E500001503C0DF150200DF040200DF15FF3FE145
+:10E510003A8805280DFEBFE017FFBFE01703801003
+:10E520000BFEFFE03603801817FFBFE017038010D3
+:10E530001E38001017FFBFE0170380101E030010E5
+:10E540001769A0D0440080101569A0D0B4018200E2
+:10E550001751F910B40182001770B710170A801014
+:10E560003AD60810B40182001770B710170A80104D
+:10E570003AD204100CC0BF103AB08820B401820017
+:10E580001770B710170A80103A920410EC3F8010F1
+:10E590003AB08820B40182001770B710170A8010B3
+:10E5A0003A9604103AB084203A88871817FFBFE0E3
+:10E5B000170080103AD6081017FFBFE01700801030
+:10E5C0003AD204100CC0BF103AB0882017FFBFE049
+:10E5D000170080103A920410EC3F80103AB0882067
+:10E5E00017FFBFE0170080103A9604103AB084205D
+:10E5F0003A8885180BFEFFE03A880B183A88091014
+:10E60000C0050D804400C01017FFBFE01503C01007
+:10E610003A8801003A8801003A8837E01701C0DFE4
+:10E62000170000DF0402C0DE3A2800F804FBFFDE1A
+:10E63000150400DF040400DF15FC3FE117FCBFE018
+:10E6400003008010BA9004100C0F801004FBBF1060
+:10E65000C5FEBFE0C3FEBFE0263E001017FCBFE0D2
+:10E660000405801015FFBFE00638000017FFBFE06B
+:10E6700003008010CC07801045FEBFE043FEBFE0E2
+:10E680006000C0101E0700182005C0101E080018EA
+:10E690001E2000104400800085FEBFE03A8805007F
+:10E6A000062D00004400800085FEBFE0061F00002C
+:10E6B00017FFBFE015FDBFE017FDBFE0170080109A
+:10E6C0003AD6061017FDBFE0170080103AD20410AA
+:10E6D0000CC0BF103AB0861817FDBFE017008010BD
+:10E6E0003A920410EC3F80103AB0861817FDBFE054
+:10E6F000170080103A9604103AB086183401A5002D
+:10E700001E02801844008000061300003A880500AD
+:10E710000611000017FFBFE04400801003008010C6
+:10E720008400801085FEBFE03A88010083FEBFE0D0
+:10E7300017FFFFE03A88851815FFBFE0C3FEFFE032
+:10E7400083FEBFE03AC88518C5FEBFE0C3FEBFE048
+:10E750001EC63F103A8805003A8837E0170000DFF0
+:10E760000401C0DE3A2800F804FCFFDE150300DFD8
+:10E77000040300DF15FE3FE115FD7FE18DFF3FE063
+:10E780008BFFBFE0BA900610B40182003A8885186A
+:10E790001770F71017FDBFE01500C01017FEBFE09F
+:10E7A0001E2800108DFF3FE0061200008BFFBFE027
+:10E7B000BA900610B40182003A8885181770B71015
+:10E7C000172B8010260800108BFFBFE0BA900610B0
+:10E7D000B40182003A8885181770F71017FDBFE062
+:10E7E0001500C010062000008BFFBFE04400801021
+:10E7F0008DFFBFE08BFFFFE01767A0D036EBBF189F
+:10E80000061900008BFFBFE0440080108DFFBFE0C1
+:10E810008BFFFFE01767A0D03603801817FDBFE01D
+:10E8200015000010061000008BFFBFE0BA90061024
+:10E83000B40182003A8885181770F71017FDBFE001
+:10E840001500C01017FDBFE017008010260600104D
+:10E8500017FDBFE017008010170A801017FEFFE0B9
+:10E860001EE8BF18060000003A8801003A8837E029
+:10E87000170000DF0401C0DE3A2800F804F3FFDED1
+:10E88000150CC0DF150B00DF150A00DC040B00DFE0
+:10E8900015F73FE115F67FE115F5BFE115FE3FE005
+:10E8A00015F83FE017F6BFE01703801015FCBFE036
+:10E8B00017F6BFE00403801015FBBFE017FCBFE0B4
+:10E8C0001E14001004160001C082298015FCBFE050
+:10E8D00017FCBFE01E020010441A80000649010028
+:10E8E00017FBBFE017FCFFE01500C01017FCBFE0EE
+:10E8F0001500001017FCBFE04400C0000501C01067
+:10E9000017FCBFE04400C0004501C01017FCBFE089
+:10E910008D01001017F7BFE0C4FDBF106801C010E3
+:10E920001E1C0118BA900610340182003A8885181E
+:10E930001720BA103A68001094E80308FCE80308AE
+:10E9400010E9030844E9030808EB030817F5BFE0E2
+:10E950001700801015FABFE017FABFE01E03001081
+:10E9600017FCBFE015000010060E010004F8BFE020
+:10E970003A880B1017FA3FE1006B3E8017F8BFE0B2
+:10E980002603001017F8BFE0172B80101E0300109D
+:10E99000441F800015FEBFE00602010017FABFE029
+:10E9A00026FF001017F8FFE017FCBFE01500C010AD
+:10E9B00006FB000017F5BFE00300C01017FCBFE026
+:10E9C0000501C01006F7000017F5BFE00300801036
+:10E9D000CC3F8010B00080101E0300108405800022
+:10E9E00015FEBFE006EF000017F5BFE00300C01002
+:10E9F00017FCBFE04501C01006EA000017F5BFE0B4
+:10EA000015F9BFE017F9BFE0170080103AD60610DD
+:10EA100017F9BFE0170080103AD204100CC0BF10E5
+:10EA20003AB0861817F9BFE0170080103A92041028
+:10EA3000EC3F80103AB0861817F9BFE0170080103D
+:10EA40003A9604103AB084182C00FC103400B80038
+:10EA5000260380188405800015FEBFE006D1000063
+:10EA600017F9BFE01701801004F8FFE03A880B188F
+:10EA70003A880910006B3E8017F8BFE026030010AB
+:10EA800017F8BFE0172B80101E030010441F8000F2
+:10EA900015FEBFE006C300008DFD3FE00616000036
+:10EAA0008BFDBFE017FCFFE084008010BA900410DB
+:10EAB0003A888518170080101701C01017F8BFE0BA
+:10EAC0001E0A80188BFDBFE017FCFFE08400801059
+:10EAD000BA9004103A888518170080101700C010EB
+:10EAE00017F9BFE017008010260980188BFDBFE0E2
+:10EAF000440080108DFDBFE017FCBFE08B0180104B
+:10EB00008BFDFFE0CCFFBF1036E5BF18060100000B
+:10EB10003A88010017FCBFE08B0180108BFDFFE0FD
+:10EB2000CCFFBF102E038018041C800015FEBFE030
+:10EB3000069C00008BFDBFE0180580101E0300102E
+:10EB40004420800015FEBFE00696000017F9BFE0E4
+:10EB500017F8FFE08BFD3FE4040180013A880B18B1
+:10EB60003A880910C02A3C803A88091017FCFFE057
+:10EB700084008080BA9004103A888518150000112E
+:10EB800017FCFFE084008080BA9004103A88851852
+:10EB9000170080101E030010441A800015FEBFE00D
+:10EBA0000680000017FCBFE08B018010440080103D
+:10EBB0003A88071017FCBFE08D01C01006790000ED
+:10EBC00017F5BFE015F9BFE017F9BFE01700801097
+:10EBD0003AD6061017F9BFE0170080103AD2041099
+:10EBE0000CC0BF103AB0861817F9BFE017008010AC
+:10EBF0003A920410EC3F80103AB0861817F9BFE043
+:10EC0000170080103A9604103AB084182C00FC10BB
+:10EC10003400B800260380188405800015FEBFE08C
+:10EC20000660000017F9BFE01701801004F8FFE04C
+:10EC30003A880B183A880910006B3E8017F8BFE03D
+:10EC40001E030010441F800015FEBFE006550000A3
+:10EC50008DFD3FE00618000017F8BFE02609001000
+:10EC60008BFDBFE017FCFFE084008010BA90041019
+:10EC70003A888518170080101701C01017F8BFE0F8
+:10EC80001E0A80188BFDBFE017FCFFE08400801097
+:10EC9000BA9004103A888518170080101700C01029
+:10ECA00017F9BFE017008010260980188BFDBFE020
+:10ECB000440080108DFDBFE017FCBFE08B01801089
+:10ECC0008BFDFFE0CCFFBF1036E3BF18060100004C
+:10ECD0003A88010017FCBFE08B0180108BFDFFE03C
+:10ECE000CCFFBF101E038018441F800015FEBFE03C
+:10ECF000062C00008BFDBFE017FCFFE084008010B5
+:10ED0000BA9004103A888518170080103A880910C4
+:10ED1000803F3C808BFDBFE0440080108DFDBFE054
+:10ED2000061000008BFDFFE08BFDBFE0C4FFBF10AD
+:10ED300017FC3FE18400C018BA9006183A88C72033
+:10ED40001700C01817FC3FE184008010BA9004102F
+:10ED50003A8885201500C0108BFDBFE0440080106C
+:10ED60008DFDBFE017FCBFE08B0180108BFDFFE045
+:10ED7000CCFFBF1036EBBF1817FCBFE08B01801033
+:10ED8000C4FFBF103A88071017FCBFE08D01C01008
+:10ED900006040000C417800015FEBFE00601000055
+:10EDA0003A88010017FCBFE0170080101E14001005
+:10EDB00017FCBFE003018010CC3F8010580080108A
+:10EDC0001E0F001017FCBFE043018010CC3F8010E5
+:10EDD000580080101E0A001017FCBFE08B01801045
+:10EDE000CCFFBF101E06001017FBBFE017008010FD
+:10EDF0003A8809100086298017FBBFE01500001033
+:10EE000017FEBFE004FFFFE61702C0DF170100DFB7
+:10EE1000170000DC0403C0DE3A2800F804F8FFDE27
+:10EE2000150700DF040700DF15FB3FE115FA7FE15E
+:10EE300015F9BFE117FABFE01703801015FFBFE017
+:10EE400017FBBFE0A00280101E17001017FBBFE0E9
+:10EE5000E00280101E22001017FBBFE05802801055
+:10EE60001E2D001017F9BFE015FEBFE017FFBFE031
+:10EE70002603001017FFBFE0170080101E030010CC
+:10EE800017FEBFE0150000100605000017FFBFE0E9
+:10EE900017008010170AC01017FEBFE01500C01041
+:10EEA0003A880500061D000017F9BFE015FDBFE018
+:10EEB00017FFBFE01E04001017FDBFE04400C000B4
+:10EEC0000500C0100604000017FFBFE00301C010DA
+:10EED00017FDBFE00500C0103A880500060F0000CE
+:10EEE00017F9BFE015FCBFE017FFBFE01E040010DC
+:10EEF00017FCBFE04400C0000500C010060400007D
+:10EF000017FFBFE04301C01017FCBFE00500C010B1
+:10EF10003A88050006010000C41780003A8837E0EF
+:10EF2000170000DF0401C0DE3A2800F804FCFFDE11
+:10EF30001503C0DF150200DF040200DF15FE3FE10C
+:10EF400017FEBFE0261400108DFF3FE0060B000007
+:10EF50008BFFBFE017FEFFE084008010BA90041022
+:10EF60003A888518170080103A880910803F3C8045
+:10EF70008BFFBFE0440080108DFFBFE017FEBFE0B5
+:10EF80008B0180108BFFFFE0CCFFBF1036F0BF1865
+:10EF900017FE3FE1008629803A8801003A8837E071
+:10EFA0001701C0DF170000DF0402C0DE3A2800F8B6
+:10EFB00004FEFFDE1501C0DF150000DF3A8839D8F6
+:10EFC00074010201042E2D21C0D902803A8801006B
+:10EFD0003A8837E01701C0DF170000DF0402C0DE07
+:10EFE0003A2800F804DEFEDE1521C1DF152001DF1E
+:10EFF000042001DF15E23EE184E8FEE074018200B6
+:10F0000004DAAD10840700013A880D203A880B100D
+:10F010003A880918806B08803A880D008400400106
+:10F020008400000100A72B8015FEBFE017FEBFE0A3
+:10F03000D8FFBF101E09001017FE3FE1C0FB2C8057
+:10F040003A880D107401420104336D2917E23EE144
+:10F050000039278044000001C0AB4280440080009A
+:10F0600015E7BEE004E7FEE004018000150080D84B
+:10F070003A880F1804018001C4FF7F0117FE3FE1A9
+:10F08000C0442C8015FDBFE017FDBFE0D8FFBF10C6
+:10F090001E07001017FE3FE1C0FB2C803A880D10C0
+:10F0A00074014201043A6D2917E23EE100392780DC
+:10F0B000840080000DF8BFE015F93FE04403A00094
+:10F0C0008DF8BFE004F8BFE0040480013A880B101B
+:10F0D00017FE3FE100AF2B8015FDBFE017FDBFE03D
+:10F0E000D8FFBF101E06001017FE3FE1C0FB2C80AA
+:10F0F0003A880B107401020104462D2180C702805A
+:10F1000074018201044DAD317401420104506D2936
+:10F1100017E23EE10039278074010201044D2D21E0
+:10F1200080C33F8015E5BEE0B401820017BAB61077
+:10F1300015E6BEE004E5FEE004028000150080D87C
+:10F140003A880F18040380013A880B0017FE3FE14C
+:10F15000C0442C8015FDBFE017FDBFE0D8FFBF10F5
+:10F160001E07001017FE3FE1C0FB2C803A880D10EF
+:10F170007401420104586D2917E23EE100392780ED
+:10F1800040CE2780740182010465AD3174014201D3
+:10F1900004506D2917E23EE1003927807401020115
+:10F1A00004652D2180C33F8015E5BEE0B4018200D7
+:10F1B00017BAB61015E6BEE004E5FEE004028000D2
+:10F1C000150080D83A880F18040380013A880B0094
+:10F1D00017FE3FE1C0442C8015FDBFE017FDBFE0E6
+:10F1E000D8FFBF101E07001017FE3FE1C0FB2C80A8
+:10F1F0003A880D107401420104586D2917E23EE16E
+:10F200000039278040CE2780740182010468AD3127
+:10F210007401420104506D2917E23EE10039278054
+:10F220007401020104682D2180C33F8015E5BEE012
+:10F23000B401820017BAB61015E6BEE004E5FEE0A0
+:10F2400004028000150080D83A880F18040380015A
+:10F250003A880B0017FE3FE1C0442C8015FDBFE04B
+:10F2600017FDBFE0D8FFBF101E07001017FE3FE1DB
+:10F27000C0FB2C803A880D107401420104586D299E
+:10F2800017E23EE10039278040CE278084008000CD
+:10F29000C5E4BEE0C4E4FEE044008000150080D870
+:10F2A0003A880F18840280013A880B0017FE3FE16C
+:10F2B000C0442C8015FDBFE017FDBFE0D8FFBF1094
+:10F2C0001E07001017FE3FE1C0FB2C803A880D108E
+:10F2D00074014201046B6D2917E23EE10039278079
+:10F2E00044008000C5E4BEE0C4E4FEE044008000C9
+:10F2F000150080D83A880F18C40280013A880B00A4
+:10F3000017FE3FE1C0442C8015FDBFE017FDBFE0B4
+:10F31000D8FFBF101E07001017FE3FE1C0FB2C8076
+:10F320003A880D107401420104786D2917E23EE11C
+:10F3300000392780840080000DF4BFE074010201D1
+:10F3400004652D2180C33F8015F5BFE04403A00074
+:10F350008DF4BFE0740182010465AD317401420196
+:10F3600004856D2917E23EE10039278015FF3FE053
+:10F37000068600001731A0D04400C0101531E0D03F
+:10F3800084E8FEE00404C0183A880D1074014201BC
+:10F3900004946D293A88091880D9428084E8FEE0F7
+:10F3A00004048000150180D804F4BFE0150080D863
+:10F3B0003A880F00840780013A880B1817FE3FE156
+:10F3C000C09A2C8015FDBFE017FDBFE00E080010AD
+:10F3D00017FE3FE1C0FB2C803A880D1074014201FA
+:10F3E00004956D2917E23EE100392780066B000085
+:10F3F0004400800015E7BEE004E7FEE00401800061
+:10F40000150080D83A880F1884058401C4FF7F0155
+:10F4100017FE3FE1C0442C8015FDBFE017FDBFE0A3
+:10F42000D8FFBF101E07001017FE3FE1C0FB2C8065
+:10F430003A880D1074014201049D6D2917E23EE1E6
+:10F4400000392780177DA0D0047D801015FCBFE017
+:10F45000063400000404800015E3BEE040CE27809F
+:10F4600004F0FEE004E3BEE0150180D804F0BFE044
+:10F47000150080D83A880F00040081013A880B18E3
+:10F4800017FE3FE100872C8015FDBFE017FDBFE0B0
+:10F490000E0C001017FE3FE1C0FB2C80E002801034
+:10F4A0001E08001017FE3FE1C0FB2C803A880D10AB
+:10F4B0007401420104A96D2917E23EE10039278059
+:10F4C0000636000017FDBFE00E16800017F1BFE002
+:10F4D0003A880910C0FB26803A8809108BF0BFE0FB
+:10F4E000CCFFBF103AD20410CCFFBF10CC3FC010ED
+:10F4F0008BF0BFE0CCFFBF103A920410CCFFBF10DE
+:10F500003AB0861804F0BEE0150080D83A880F188B
+:10F510003A880D207401420104B16D2917E23EE1E1
+:10F5200000392780177DE0D017FCBFE036C9BF182F
+:10F53000C5E43EE0C4E4FEE044008000150080D84D
+:10F540003A880F1884058401C4FF7F0117FE3FE14C
+:10F55000C0442C8015FDBFE017FDBFE0D8FFBF10F1
+:10F560001E07001017FE3FE1C0FB2C803A880D10EB
+:10F570007401420104B86D2917E23EE10039278089
+:10F5800017FFBFE04400801015FFBFE017FFBFE08A
+:10F59000D00080101E773F103A88010074010201EC
+:10F5A000044D2D2180C33F8015E5BEE0B4018200EB
+:10F5B00017BAB61015E6BEE004E5FEE004028000CE
+:10F5C000150080D83A880F18440380013A880B0050
+:10F5D00017FE3FE1C0442C8015FDBFE017FDBFE0E2
+:10F5E000D8FFBF101E07001017FE3FE1C0FB2C80A4
+:10F5F0003A880D107401420104C46D2917E23EE1FE
+:10F600000039278017FE3FE100E72C8015FDBFE0A1
+:10F6100017FDBFE0D8FFBF101E07001017FE3FE127
+:10F62000C0FB2C803A880D107401420104D16D2971
+:10F6300017E23EE1003927803A8805003A8837E032
+:10F640001701C0DF170000DF0402C0DE3A2800F80F
+:10F6500004FFFFDE150000DF3A8839D817A1E0D09B
+:10F66000740182001559F210740182000459B2101D
+:10F6700015A1A0D017A3E0D0740182001562F2108A
+:10F68000740182000483B21015A3A0D03A8805004B
+:10F690003A8837E0170000DF0401C0DE3A2800F89E
+:10F6A00004FDFFDE150200DF040200DF15FF3FE16D
+:10F6B00015FE7FE13A8805003A8837E0170000DF41
+:10F6C0000401C0DE3A2800F804FEFFDE150100DF69
+:10F6D000040100DF15FF3FE13A8801003A8837E076
+:10F6E000170000DF0401C0DE3A2800F804F7FFDE4F
+:10F6F0001508C0DF150700DF040700DF15FC3FE138
+:10F7000015FB7FE115FABFE115F9FFE13408800030
+:10F7100015FEBFE017F9BFE02607001017F9BFE09C
+:10F72000170180102604001017F9BFE017018010A0
+:10F730001707801015FEBFE017F9BFE01702C010D1
+:10F7400017F9BFE017018010170680103AC8851816
+:10F7500015FDBFE017FAFFE017FBBFE03A38851848
+:10F7600015FFBFE017FDFFE017FFBFE03A888518DF
+:10F7700017FEFFE02E04801817FEFFE017FDBFE024
+:10F780003AC8851815FFBFE017FDFFE017FEBFE080
+:10F790002E05801817FFBFE0ECFFBF101E020010FF
+:10F7A00017FFBFE01E0200103A8805000620000087
+:10F7B00017F9BFE0170180108B058010CCFFBF1038
+:10F7C0001C00A0100400A0101610001017F9BFE0D4
+:10F7D0001701801003018010CC3F80101C20801086
+:10F7E00004E0BF10581B80101E08001017F9BFE07E
+:10F7F0001702C010340880003A88851817FFBFE14F
+:10F800003A880B1017FC3FE1806B088017F9BFE0C6
+:10F810001702C01017FFBFE03A88871817F9BFE03A
+:10F820001502C01017FB7FE117FF3FE180FF0C803E
+:10F830003A8837E01701C0DF170000DF0402C0DE9E
+:10F840003A2800F804FBFFDE150400DF040400DFA3
+:10F8500015FF3FE115FE7FE115FDBFE115FCFFE15E
+:10F8600017FCBFE01701801003018010CC3F80100F
+:10F870001C20801004E0BF10581B80101E020010D6
+:10F880003A8805000609000017FCBFE01702C01007
+:10F8900017FD3FE117FEBFE03A3885203A88871808
+:10F8A00017FCBFE01502C01017FDBFE03A8837E033
+:10F8B000170000DF0401C0DE3A2800F804FCFFDE78
+:10F8C000150300DF040300DF15FF3FE115FE7FE1B4
+:10F8D00015FDBFE13A8805003A8837E0170000DFE0
+:10F8E0000401C0DE3A2800F804FEFFDE150100DF47
+:10F8F000040100DF15FF3FE1340880003A8837E05B
+:10F90000170000DF0401C0DE3A2800F804FCFFDE27
+:10F91000150300DF040300DF15FD3FE115FF3FE0A5
+:10F9200017FDBFE01702C01017FDBFE017018010E0
+:10F93000170680103AC8851815FEBFE017FDBFE016
+:10F94000170180101707801017FEFFE0360280189D
+:10F95000C4FFBF00061A000017FDBFE017018010AA
+:10F960008B058010CCFFBF101C00A0100400A0105D
+:10F97000160D001017FDBFE0170180100301801065
+:10F98000CC3F80101C20801004E0BF10581B80105A
+:10F990001E05001017FDBFE0170280100300801045
+:10F9A000CC3F801015FFBFE017FDBFE017028010AD
+:10F9B0004400C01017FDBFE01502C01017FFBFE0E4
+:10F9C0003A8837E0170000DF0401C0DE3A2800F86B
+:10F9D00004FEFFDE150100DF040100DF15FF3FE13B
+:10F9E0003A8805003A8837E0170000DF0401C0DEDE
+:10F9F0003A2800F804F6FFDE1509C0DF150800DF1D
+:10FA0000040800DF15FA3FE115F97FE115F8BFE1C1
+:10FA100015FE3FE07401820004E2AD1015FDBFE069
+:10FA200017F8BFE015FFBFE00625000017FFBFE095
+:10FA300003008010CC3F80101C20801004E0BF1019
+:10FA4000880E80101E0E001017FFBFE0030080100C
+:10FA5000CC3F80101C20801004E0BF10900B801061
+:10FA60001E07001017FFBFE003008010CC3F80107E
+:10FA70001C20801004E0BF10D80B80101E03001063
+:10FA80007401820004EBAD100694000017FFBFE084
+:10FA900003008010CC3F80101C20801004E0BF10B9
+:10FAA000980B80101E03001017FEBFE0440080106A
+:10FAB00015FEBFE017FFBFE04400801015FFBFE058
+:10FAC00017FFBFE003008010CC3F80101C20801087
+:10FAD00004E0BF101ED53F1017FEBFE00E038000EC
+:10FAE00017FEBFE0100180101E0300107401820099
+:10FAF00004F6AD100679000017F8BFE015FFBFE06F
+:10FB000017FF3FE140AA428015FCBFE017FCBFE0B1
+:10FB1000104080101E02001017FDBFE0066F0000AD
+:10FB200017FCBFE005FBBFE00603000017FFBFE0C6
+:10FB30004400801015FFBFE017FFBFE003008010F6
+:10FB4000CC3F80101C20801004E0BF10980B801068
+:10FB50001EF63F1017FFBFE04400801015FFBFE006
+:10FB600017FEBFE0600080101E03001017FEBFE00C
+:10FB7000980080101E02001045FB3FE006180000B0
+:10FB800017FF3FE140AA428015FCBFE006030000DA
+:10FB900017FFBFE04400801015FFBFE017FFBFE074
+:10FBA00003008010CC3F80101C20801004E0BF10A8
+:10FBB000980B80101EF63F1017FFBFE04400801026
+:10FBC00015FFBFE017FCBFE0104080101E020010C0
+:10FBD00017FDBFE00641000017FCBFE045FBBFE09A
+:10FBE00017FEBFE0580080101E02001085FB3FE0AA
+:10FBF0000618000017FF3FE140AA428015FCBFE055
+:10FC00000603000017FFBFE04400801015FFBFE0AF
+:10FC100017FFBFE003008010CC3F80101C20801035
+:10FC200004E0BF10980B80101EF63F1017FFBFE0D6
+:10FC30004400801015FFBFE017FCBFE010408010AB
+:10FC40001E02001017FDBFE00624000017FCBFE0F5
+:10FC500085FBBFE017FF3FE140AA428015FCBFE0F3
+:10FC600017FCBFE0104080101E02001017FDBFE01F
+:10FC7000061A000017FCBFE0C5FBBFE003FBBFE0B6
+:10FC8000CC3F80101C20801004E0BF101604001030
+:10FC900017F9BFE00402C0001500C010060B0000F9
+:10FCA00003FBBFE0CC3F8010283080101E04001002
+:10FCB00017F9BFE00404C0001500C01006030000DF
+:10FCC00017F9BFE00406C0001500C01017FBFFE0E5
+:10FCD00017FABFE01500C0103A8805003A8837E0EF
+:10FCE0001701C0DF170000DF0402C0DE3A2800F869
+:10FCF00004FBFFDE1504C0DF150300DF040300DF93
+:10FD000015FD3FE117FD7FE17401020104833321FA
+:10FD100000F6428004FEFFE004FFBFE074018201B0
+:10FD20000483B3313A880B183A880910C0933F8096
+:10FD30001E02001017FFBFE0060100003A88050010
+:10FD40003A8837E01701C0DF170000DF0402C0DE89
+:10FD50003A2800F804FEFFDE150100DF040100DF91
+:10FD600015FF3FE117FFBFE0CC03801015FFBFE098
+:10FD700017FFBFE0880280101E03001017FFBFE0CE
+:10FD8000040C80100602000017FFBFE0C40D8010B5
+:10FD90003A8837E0170000DF0401C0DE3A2800F897
+:10FDA00004F8FFDE1507C0DF150600DF040600DFDC
+:10FDB00015FC3FE115FB7FE115FABFE117FCBFE041
+:10FDC000980080101E15001004FDFFE004FEBFE047
+:10FDD00017FBBFE13A880B183A880910C0933F809F
+:10FDE00015FFBFE017FFBFE01E07001004FEBFE0D5
+:10FDF000040180013A880B1017FA3FE1806B0880FC
+:10FE00003A88050006060000740182000400AE1066
+:10FE10001533A0D044008000060100003A88050098
+:10FE20003A8837E01701C0DF170000DF0402C0DEA8
+:10FE30003A2800F804F8FFDE1507C0DF150600DFDA
+:10FE4000040600DF15FD3FE115FC7FE115FBBFE176
+:10FE500015FAFFE117FDBFE0980080101E1000109A
+:10FE600017FCBFE01700801015FFBFE017FF3FE150
+:10FE7000C0FB268015FEBFE017FE3FE1C0DA02801E
+:10FE80003A88071017FABFE02E05801817FE7FE1A9
+:10FE900017FB3FE100F6428017FBBFE006010000C0
+:10FEA0003A8805003A8837E01701C0DF170000DF05
+:10FEB0000402C0DE3A2800F804FCFFDE1503C0DFB0
+:10FEC000150200DF040200DF15FE3FE117FEBFE070
+:10FED0000B008010CCFFBF10980080101E07001090
+:10FEE00017FEBFE015FFBFE017FFBFE0170180104E
+:10FEF0003A880910C0FB2680060100003A880500F8
+:10FF00003A8837E01701C0DF170000DF0402C0DEC7
+:10FF10003A2800F804FBFFDE1504C0DF150300DFFC
+:10FF2000040300DF15FE3FE115FD7FE117FDBFE093
+:10FF30008400C0000D00C01017FEBFE04400801018
+:10FF400003008010CC3F80101C20801004E0BF1004
+:10FF5000A00B80101E10001017FEBFE08400801060
+:10FF600003008010CC3F80101C20801004E0BF10E4
+:10FF7000A00B80101E08001017FEBFE0C400801008
+:10FF800003008010CC3F80101C20801004E0BF10C4
+:10FF9000980B80101E0A001017FDBFE015FFBFE090
+:10FFA00017FE3FE180C33F803A88071017FFBFE08C
+:10FFB0001501C01017FFBFE08400C0000D00C01085
+:10FFC0003A8805003A8837E01701C0DF170000DFE4
+:10FFD0000402C0DE3A2800F804FCFFDE150300DF4F
+:10FFE000040300DF15FE3FE115FD7FE117FEBFE0D2
+:10FFF0000B008010CCFFBF10980080101E0C00106A
+:020000024000BC
+:1000000017FEBFE015FFBFE017FDBFE03AD20510B5
+:10001000CC3F80103A88071017FDBFE03A920410D9
+:100020003AB084183A88071017FFBFE08D00C0105F
+:100030003A8801003A8837E0170000DF0401C0DE8B
+:100040003A2800F804F9FFDE150600DF040600DF99
+:1000500015FA3FE117FABFE015FFBFE004FBBFE070
+:1000600015FCBFE015FE3FE08DFD3FE015FB3FE0D6
+:100070000631000017FFBFE003008010CC3F801066
+:100080001C20801004E0BF10980B80101E0E001082
+:1000900017FEBFE017FCFFE03A8885188BFDFFE0F4
+:1000A0000500C0108DFD3FE017FEBFE0440080104A
+:1000B00015FEBFE017FEBFE0100180101E1B0010F0
+:1000C00017FBBFE00628000017FFBFE00300801009
+:1000D000CC3F80101C20801004E0BF10100C80105A
+:1000E0001E12001017FFBFE003008010CC3F8010ED
+:1000F0001C20801004E0BF10880E80101E0B001022
+:100100008BFDBFE0A40280103A88071017FFBFE004
+:1001100003008010CC3F80101C20801004E0BF1032
+:100120003A88851804F4BF108DFDBFE017FFBFE0CB
+:100130004400801015FFBFE017FFBFE003008010F0
+:10014000CC3F80101C20801004E0BF101EC93F105F
+:1001500017FEBFE017FCFFE03A8885188BFDFFE033
+:100160000500C01017FBBFE03A8837E0170000DF3A
+:100170000401C0DE3A2800F804F7FFDE1508C0DFEE
+:10018000150700DF040700DF15F93FE115FE3FE02A
+:10019000C5FD3FE017F9BFE003008010CC3F8010A1
+:1001A000BA9004100C0F80108DFCBFE017F9BFE06F
+:1001B0008B008010CCFFBF103AD204103A88071091
+:1001C00017F9BFE08B008010CCFFBF103A920410EB
+:1001D0003AB084183A8807108BFCBFE03AC88518FB
+:1001E0008DFFBFE017F9BFE003008010CC3F801007
+:1001F000BA9004100C0F801017F9FFE03A888518A8
+:1002000015FBBFE017FBBFE00B0480108DFABFE0C9
+:100210008BFFBFE0840180103AD20510CC3F8010E4
+:100220003A8807108BFFBFE0840180103A920410D7
+:100230003AB084183A88071017FBBFE00D04C010CD
+:100240008BFFBFE04C008010260E00108BFCFFE0FF
+:100250008BFFBFE03A88851817F9FFE03A888518C8
+:1002600015FEBFE017FEBFE003008010C5FDBFE034
+:1002700017FEBFE0050000108BFFBFE044008010B8
+:100280008DFFBFE017FBBFE004FEFF108BFFBFE058
+:10029000040280107AD005103A880B103A880918A9
+:1002A000C0D726803A3084000DFDBFE00BFDFFE093
+:1002B0008BFABFE0260780188BFAFFE0D4FFBF005F
+:1002C0001E0480180BFDBFE01E020010C4FFBF001B
+:1002D0000DFDBFE017FBBFE08BFAFFE00D04C0107F
+:1002E000C7FDBFE02603001017FEBFE0C3FDFFE01F
+:1002F0000500C0100BFDBFE03A8837E01701C0DFF2
+:10030000170000DF0402C0DE3A2800F804F4FFDE24
+:10031000150BC0DF150A00DF040A00DF15FD3FE101
+:100320003A8805283A88073015FAFFE10DFCBFE04E
+:100330003A8805180DFBBFE01766A0D00C018010AD
+:100340002615001017FDBFE0CC3F001217FDBFE0DF
+:100350003AD20410CC3F801117FDBFE03AD404100C
+:10036000CC3FC01117FDBFE03AD604100BFBFFE0F5
+:100370000BFC3FE1170240E1150340D9150200D9FB
+:100380001501C0D8150080D83A880B4074010201CD
+:1003900004072E2180C702803A88090080F3288054
+:1003A00015FE3FE0179EA0D015FFBFE0062000001D
+:1003B00017FFBFE015FEBFE017FFBFE08B01801005
+:1003C0000BFBFFE0CCFFBF101E16801817FFBFE02D
+:1003D0000B0280100BFCFFE0CCFFBF101E11801839
+:1003E00017FFBFE0170380101E0E001017FFBFE0BD
+:1003F0001704801017FDFFE01E0A80181766A0D0B2
+:100400000C058010260300107401020104162E2131
+:10041000C0D902803A88090040FF28803A88050048
+:100420000635000017FFBFE01700801015FFBFE082
+:1004300017FFBFE01EDE3F1004080001C0822980C4
+:1004400015FFBFE017FFBFE01E0A00101766A0D01F
+:100450000C0180102603001074010201041E2E21DD
+:10046000C0D902803A88090040FF28803A880500F8
+:100470000621000017FEBFE02604001017FEBFE0B3
+:1004800017FFFFE01500C0100602000017FFBFE0D5
+:10049000159EA0D017FFBFE01500001017FFBFE0AA
+:1004A0000BFBFFE08D01C01017FFBFE00BFCFFE06E
+:1004B0000D02C01017FFBFE01503001017FFBFE0CB
+:1004C00017FDFFE01504C01017FFBFE017FAFFE0AB
+:1004D0001505C01017FFBFE01702C0E01506C010D9
+:1004E00017FFBFE04400C0000D01C0103A880900AA
+:1004F00040FF288017FFBFE03A8837E01701C0DFD0
+:10050000170000DF0402C0DE3A2800F804FBFFDE1B
+:100510001504C0DF150300DF040300DF15FD3FE114
+:1005200017FDBFE026020010179EA0D01E0200108B
+:1005300040CD2880062600003A88090080F32880F4
+:1005400015FE3FE0179EA0D015FFBFE00608000093
+:1005500017FFFFE017FDBFE02608801817FFBFE078
+:1005600015FEBFE017FFBFE01700801015FFBFE0CA
+:1005700017FFBFE01EF63F10060100003A88010099
+:1005800017FFBFE01E04001040CD28803A88090004
+:1005900040FF2880060E000017FEBFE02605001071
+:1005A00017FDBFE01700C01017FEBFE01500C01018
+:1005B0000603000017FDBFE017008010159EA0D0B5
+:1005C00017FD3FE1008629803A88090040FF288016
+:1005D0003A8837E01701C0DF170000DF0402C0DEF1
+:1005E0003A2800F804FBFFDE1504C0DF150300DF26
+:1005F000040300DF15FE3FE115FD7FE1040B000160
+:10060000C082298015FFBFE017FFBFE01E02001067
+:10061000040380000610000017FFBFE017FDFFE095
+:100620001502C01017FFBFE017FEFFE01508C0104D
+:1006300017FFBFE00480C0001506C01017FD7FE162
+:1006400017FF3FE140332A8017FEBFE017FFFFE0AE
+:100650001501C0103A8805003A8837E01701C0DF5D
+:10066000170000DF0402C0DE3A2800F804FCFFDEB9
+:100670001503C0DF150200DF040200DF15FE3FE1B5
+:1006800017FEBFE01708801015FFBFE017FFBFE09F
+:100690001501001017FF3FE140322D8017FE3FE1AA
+:1006A000402C2A8017FE3FE1008629803A8801000D
+:1006B0003A8837E01701C0DF170000DF0402C0DE10
+:1006C0003A2800F804F5FFDE150AC0DF150900DF3F
+:1006D000040900DF15FA3FE115F97FE117FABFE0E1
+:1006E0001708801015FDBFE017FABFE01702801051
+:1006F00015FCBFE08DFF3FE017FABFE08B078010CD
+:10070000CCFFBF101E03001017FABFE017048010C3
+:1007100026020010840580000669000017F9BFE07A
+:100720002639001017F9BFE01703801015FBBFE052
+:1007300017FBBFE017018010260A001017FBBFE06F
+:10074000170180103A88091080023B803A88071010
+:1007500017FBBFE01701801026028018441F80009D
+:100760000657000017FBBFE08B0080108DFFBFE035
+:100770008BFFBFE0261F001015FE3FE017FDBFE016
+:10078000170480100C0180101E0C001017FDBFE034
+:10079000170280100B018010CCFFBF100C018010DD
+:1007A0002604001017FDBFE0170480108C00801095
+:1007B0001E0200104400800015FEBFE017FBBFE0E2
+:1007C000170100118BFFBFE017FEFFE01501C0D835
+:1007D000150080D83A880F203A880D003A880B001F
+:1007E00017FC3FE100B6408026020010041C800088
+:1007F0000633000017FABFE017FBFFE01701C0182F
+:100800001504C010060100003A8801008BFFBFE00C
+:100810001E27001017FCBFE08B0780104400C0109B
+:100820003A88091817FCFFE08D070019CCFFBF10AC
+:10083000300081101E05001017FCBFE08B078010F0
+:10084000CCFFBF1070E284101E03001017FCBFE045
+:100850000400C1008D07C01017FCBFE08B0780109B
+:10086000CCFFBF103AD204103A88071017FCBFE043
+:100870008B078010CCFFBF103A9204103AB0841856
+:100880008DFFBFE017FABFE01704C0108BFFBFE079
+:10089000150100D8150080D83A880F183A880D0045
+:1008A0003A880B0017FC3FE100B640801ED93F108C
+:1008B00017FABFE08BFFFFE08D07C0103A880500F4
+:1008C0003A8837E01701C0DF170000DF0402C0DEFE
+:1008D0003A2800F804F6FFDE1509C0DF150800DF2E
+:1008E000040800DF15FB3FE115FA7FE117FABFE0CE
+:1008F0001703801015FEBFE017FABFE01702801043
+:10090000280480101E020010840580000664000088
+:1009100017FEBFE00B008010CCFFBF101C00A01022
+:100920000400A010A00080101E020010841A800095
+:10093000065B000017FEBFE08B008010CCFFBF10ED
+:100940001E020010441F80000655000017FEBFE085
+:10095000170180101E0D001017FBBFE026090010C4
+:1009600017FBBFE0170A80102606001017FBBFE038
+:10097000170A8010170AC01017FEBFE01501C0103B
+:1009800006080000441F80000645000017FEBFE077
+:1009900017018010D8FFBF101E020010441F8000F6
+:1009A000063F000017FBBFE0170480101E0F001069
+:1009B00017FEBFE01701801004FCFFE03A880B1817
+:1009C0003A88091000373B8015FDBFE017FDBFE0F6
+:1009D0001E020010441F80000631000017FDBFE01A
+:1009E000170A801015FFBFE00603000017FBBFE0E9
+:1009F0001704801015FFBFE017FBBFE01702C010FF
+:100A000017FEBFE01701001117FEBFE08B0080103A
+:100A1000CCFF7F1117FBBFE08B078010CCFFBF100E
+:100A2000150100D8150080D817FFFFE13A880D287E
+:100A30003A880B203A88091800B640802602001038
+:100A4000041C80000616000017FBBFE0170480108E
+:100A50001E0A001017FBBFE08B078010CCFFBF10F1
+:100A60001E0300103A880B0017FB3FE1C060408076
+:100A700017FBBFE017FFFFE01504C01017FBBFE036
+:100A800017FEFFE01701C0181503C01017FEBFE0E6
+:100A90008B00C01017FBBFE00D07C0103A8805009F
+:100AA0003A8837E01701C0DF170000DF0402C0DE1C
+:100AB0003A2800F804FDFFDE1502C0DF150100DF53
+:100AC000040100DF15FF3FE117FFBFE01503001031
+:100AD00017FFBFE00D07001017FFBFE017088010D9
+:100AE0008B088010CCFFBF104C0080102602001035
+:100AF00017FF3FE1405B40803A8801003A8837E0C9
+:100B00001701C0DF170000DF0402C0DE3A2800F83A
+:100B100004FBFFDE1504C0DF150300DF040300DF64
+:100B200015FE3FE115FD7FE117FDBFE00404C000A5
+:100B30001502C01017FDBFE01703801015FFBFE0BE
+:100B4000040480013A880B0017FF3FE1408E0880C3
+:100B500017FFBFE08400C0000D00C01017FEBFE00B
+:100B60008B07C01017FFBFE08D00C01017FFBFE05C
+:100B700017FEFFE01704C0181501C0103A880100E5
+:100B80003A8837E01701C0DF170000DF0402C0DE3B
+:100B90003A2800F804FBFFDE1504C0DF150300DF70
+:100BA000040300DF15FE3FE115FD7FE117FDBFE007
+:100BB0000404C0001502C01017FDBFE01703801029
+:100BC00015FFBFE0040480013A880B0017FF3FE1E6
+:100BD000408E088017FFBFE08400C0000D00C010E9
+:100BE00017FEBFE00B07C01017FFBFE08D00C0105D
+:100BF00017FFBFE017FEFFE01703C0181501C01074
+:100C00003A8801003A8837E01701C0DF170000DF9B
+:100C10000402C0DE3A2800F804F5FFDE150A00DF02
+:100C2000040A00DF15FA3FE115F97FE13A88073041
+:100C300015F7FFE1170180E00DF8FFE00DF6BFE0CA
+:100C400015FE3FE00BF8BFE08DFBBFE00BF6BFE009
+:100C50000DFBBFE0C400800015FDBFE017FABFE048
+:100C60001700801015FFBFE0064F000017FFBFE020
+:100C70008B0780100BFBFFE0CCFFBF101E408018DD
+:100C800017FFBFE01708801017058010A000801024
+:100C9000263D001015FC3FE017FFBFE01704801051
+:100CA000260B001017F7BFE01E04001017FCBFE072
+:100CB0004400801015FCBFE0060A000017FFBFE0EB
+:100CC0001704801017F7FFE026068018063300008F
+:100CD00017F7BFE02603001017FCBFE044008010A8
+:100CE00015FCBFE017FFBFE01703801026100010AF
+:100CF00017F9BFE01E04001017FCBFE0440080108D
+:100D000015FCBFE0060F000017FFBFE017038010BF
+:100D100017F9FFE01E1E801817FFBFE00B078010B9
+:100D20008BFBFFE0CCFFBF102606801806180000E2
+:100D300017F9BFE02603001017FCBFE04400801045
+:100D400015FCBFE017FCBFE026030010170280E08F
+:100D50004C0080102610001017FCFFE017FDBFE0CC
+:100D60000E0E801817FFBFE015FEBFE017FCBFE0B6
+:100D700015FDBFE017FDBFE0260F001006070000BD
+:100D80003A880100060500003A88010006030000C9
+:100D90003A880100060100003A88010017FFBFE011
+:100DA0001700801015FFBFE017FFFFE017FABFE044
+:100DB0001EAEBF18060100003A88010017FEBFE012
+:100DC0001E02001017FEBFE00624000017FABFE065
+:100DD0001700801017FEFFE01E048018179FA0D098
+:100DE00044008010159FA0D0061B000017A0A0D0C3
+:100DF0004400801015A0A0D017FEBFE0170080109F
+:100E000017FEFFE01701C0181501C01017FEBFE064
+:100E10001701801017FEFFE01700C0181500C01062
+:100E200017FABFE01700C01017FEBFE01500C01092
+:100E300017FABFE017FEFFE01500C01017FEBFE075
+:100E400017FAFFE01501C01017FEBFE01700801071
+:100E500017FEFFE01501C01017FEBFE03A8837E02B
+:100E6000170000DF0401C0DE3A2800F804FEFFDEB0
+:100E7000150100DF040100DF15FF3FE117FFBFE0B0
+:100E800015A4A0D03A8801003A8837E0170000DFA7
+:100E90000401C0DE3A2800F804FFFFDE150000DF81
+:100EA0003A8839D817A4A0D03A8837E0170000DF75
+:100EB0000401C0DE3A2800F804FDFFDE1502C0DFA1
+:100EC000150100DF040100DF17A6A0D0F03F80105D
+:100ED0001E0200103A880500060E000004050001FD
+:100EE000C082298015FFBFE017FFBFE02608001071
+:100EF00017A2E0D017FFBFE01500C01017FFBFE03A
+:100F000015A2A0D017A6A0D04400801015A6A0D08E
+:100F100017FFBFE03A8837E01701C0DF170000DF96
+:100F20000402C0DE3A2800F804F9FFDE1506C0DF2F
+:100F3000150500DF040500DF15FB3FE117A7E0D032
+:100F400017FBBFE03A888518D4FFFF002E028018F7
+:100F50003A880500062100000401800015FFBFE06B
+:100F60000401800015FEBFE017FFBFE017FEFFE0A1
+:100F70002E10801817FEBFE0980080101E08001089
+:100F8000F4FFBF0015FDBFE03A88010017FBFFE04A
+:100F900017FDBFE03A708418260600100603000013
+:100FA00040CD28803A880500060C00003A880500EC
+:100FB000060A000017FB3FE1C082298015FCBFE054
+:100FC00017FCBFE02604001017A7E0D017FBBFE016
+:100FD0003A88851815A7A0D017FCBFE03A8837E0FB
+:100FE0001701C0DF170000DF0402C0DE3A2800F856
+:100FF00004FCFFDE1503C0DF150200DF040200DF82
+:1010000015FF3FE115FE7FE117FFBFE0260200104C
+:1010100017FF3FE10086298017A7E0D017FEBFE049
+:101020003AC8851815A7A0D03A8801003A8837E059
+:101030001701C0DF170000DF0402C0DE3A2800F805
+:1010400004F9FFDE1506C0DF150500DF040500DF2B
+:1010500015FC3FE115FB7FE13A88090040DB408049
+:10106000C40F400117FC3FE1C0DF4280260300109F
+:1010700040CD28803A88050006BA000017FC3FE101
+:101080008020428015FEBFE017FEBFE0264A001018
+:1010900017FBBFE003008010CC3F80101C208010A5
+:1010A00004E0BF10D81D80101E09001017FEBFE01D
+:1010B0008B058010CCFFBF100C0880101E040010A0
+:1010C00084F93F0140DB40803A88050006A5000016
+:1010D00000E0408015FDBFE017FDBFE01E040010DA
+:1010E00004FB3F0140DB40803A880500069D00007C
+:1010F00017FDBFE017FEFFE01501C01017FEBFE0AF
+:101100001706C01017FDBFE01502C01017FBBFE0A7
+:1011100003008010CC3F80101C20801004E0BF1022
+:10112000581880101E0A001017FEBFE01706801026
+:101130002607001017FEBFE01706C01017FEBFE01D
+:10114000170880103A88871817FDBFE01502C010F5
+:1011500017FBBFE003008010CC3F80101C208010E4
+:1011600004E0BF10D81D80101E11001017FEBFE054
+:101170001507001017FEBFE01508001017FEBFE0AE
+:101180008B058010148080103A88071017FEBFE08E
+:101190008D05C01017FEBFE08B05C01084FFBF0097
+:1011A0003A7084183A88071017FEBFE08D05C0100A
+:1011B00017FDBFE0066B000017FBBFE003008010C7
+:1011C000CC3F80101C20801004E0BF10A01C8010B9
+:1011D0001E12001017A1A0D015FFBFE0060D0000E1
+:1011E00017FFBFE01701801017FB7FE117FC3FE1FD
+:1011F0003AE83E1015FDBFE017FDBFE026020010E3
+:1012000017FDBFE00657000017FFBFE01700801072
+:1012100015FFBFE017FFBFE01EF13F1017FBBFE057
+:1012200003008010CC3F80101C20801004E0BF1011
+:10123000A01C80101E48001017A8A0D0F03F8010FE
+:101240001E04001004FB3F0140DB40803A8805008B
+:101250000644000017FC3FE1C0DA028070048010F1
+:101260001E04001084FD3F0140DB40803A880500E9
+:10127000063C0000040B0001C082298015FEBFE07F
+:1012800017FEBFE01E04001004FB3F0140DB40805E
+:101290003A8805000633000000E0408015FDBFE0FD
+:1012A00017FDBFE01E06001017FE3FE100862980F3
+:1012B00004FB3F0140DB40803A880500062900001E
+:1012C00017A3E0D017FEBFE01500C01017FEBFE067
+:1012D00015A3A0D017A8A0D04400801015A8A0D0B6
+:1012E00017FCBFE003008010CC3F80101C20801052
+:1012F00004E0BF10E00B80101E07001017FCBFE0D9
+:1013000003008010CC3F80101C20801004E0BF1030
+:10131000181780101E03001017FCBFE04400801057
+:1013200015FCBFE017FEBFE00401801017FC7FE151
+:101330003A88091000F6428017FEBFE004D8C000CA
+:101340008D05C01017FDBFE017FEFFE01501C010AE
+:1013500017FDBFE006030000C4F93F0140DB4080F9
+:101360003A8805003A8837E01701C0DF170000DF30
+:101370000402C0DE3A2800F804FBFFDE1504C0DFDB
+:10138000150300DF040300DF15FE3FE115FD7FE1DB
+:1013900044010001402B298017FD7FE117FE3FE14A
+:1013A00080F8408015FFBFE04401000180362980AD
+:1013B00017FFBFE03A8837E01701C0DF170000DFF2
+:1013C0000402C0DE3A2800F804F8FFDE1507C0DF8B
+:1013D000150600DF040600DF15FA3FE115FE3FE0C9
+:1013E00017A2A0D015FFBFE00608000017FAFFE023
+:1013F00017FFBFE02608801817FFBFE015FEBFE00B
+:1014000017FFBFE01700801015FFBFE017FFBFE018
+:101410001EF63F10060100003A88010017FAFFE0AF
+:1014200017FFBFE01E51801817FABFE017018010A8
+:1014300015FDBFE017FDBFE02638001017FDBFE027
+:10144000170A80102608001017FDBFE0170A801049
+:1014500015FCBFE017FCBFE01702801017FA3FE150
+:101460003AE83E100630000017FDBFE08B05801003
+:10147000CCFFBF100C208010262A001017FDBFE003
+:101480001709C01017FDBFE0170880103AC885186B
+:10149000304080101E23001017FDBFE0170680109B
+:1014A0002620001017FDBFE0170880103A880910A9
+:1014B00000E7408015FBBFE017FBBFE026190010D6
+:1014C00017FDBFE01706C01017FDBFE0170880101A
+:1014D0003A880D103A880B1817FB3FE1806B0880A3
+:1014E00017FDBFE01706C01017FDBFE017098010F9
+:1014F0003A880B103A88091880F3408017FDBFE046
+:1015000017FBFFE01506C01017FDBFE01708C0105D
+:1015100017FDBFE01509C010060200003A8801005F
+:10152000060100003A88010017FEBFE02605001002
+:1015300017FFBFE01700C01017FEBFE01500C01076
+:101540000603000017FFBFE01700801015A2A0D00F
+:1015500017FF3FE10086298017A6A0D0C4FFBF1067
+:1015600015A6A0D03A880100060100003A880100C3
+:101570003A8837E01701C0DF170000DF0402C0DE41
+:101580003A2800F804FDFFDE1502C0DF150100DF78
+:10159000040100DF15FF3FE144010001402B2980D9
+:1015A00017FF3FE10031418044010001803629806E
+:1015B0003A8801003A8837E01701C0DF170000DFE2
+:1015C0000402C0DE3A2800F804FDFFDE1502C0DF89
+:1015D000150100DF040100DF15FF3FE144010001B8
+:1015E000402B29807401020104282E21C0D90280D9
+:1015F00044010001803629803A8805003A8837E0A6
+:101600001701C0DF170000DF0402C0DE3A2800F82F
+:1016100004F9FFDE1506C0DF150500DF040500DF55
+:1016200015FD3FE115FC7FE115FBBFE1C4FFBF00E5
+:1016300015FFBFE017FDBFE015FEBFE0060B000081
+:1016400017FEBFE04400C01015FEFFE017FFFFE0EB
+:101650000500C01003008010CC3F80101C208010BB
+:1016600004E0BF1098028010260C001017FCBFE0A9
+:10167000C4FFBF1015FCBFE017FCBFE00E088000E0
+:1016800017FB3FE1001C428015FFBFE017FFBFE0E2
+:10169000D8FFBF101EEA3F10060100003A88010083
+:1016A00017FEBFE00500001017FFBFE0D8FFBF1016
+:1016B0001E03001017FEFFE017FDBFE02602801892
+:1016C00017FDBFE0060100003A8805003A8837E0C0
+:1016D0001701C0DF170000DF0402C0DE3A2800F85F
+:1016E00004FCFFDE1503C0DF150200DF040200DF8B
+:1016F00015FE3FE115FF3FE017FE3FE1001C428071
+:1017000015FFBFE017FFBFE0D8FFBF101E0200109B
+:1017100044008000060100003A8805003A8837E05E
+:101720001701C0DF170000DF0402C0DE3A2800F80E
+:1017300004FDFFDE150200DF040200DF15FE3FE1BD
+:1017400017A2A0D015FFBFE00609000017FFBFE0F9
+:101750001701801017FEFFE01E02801817FFBFE080
+:101760001501001017FFBFE01700801015FFBFE044
+:1017700017FFBFE01EF53F103A8801003A8837E0B6
+:10178000170000DF0401C0DE3A2800F804F6FFDE8F
+:101790001509C0DF150800DF040800DF15F83FE178
+:1017A00015FF3FE017F83FE1C0DA028044008010E7
+:1017B0003A88091080C9428015FCBFE017F87FE124
+:1017C00017FC3FE100F6428044010001402B2980D4
+:1017D00017FC3FE18020428015FBBFE017FBBFE014
+:1017E0001E060010440100018036298017FC3FE1ED
+:1017F00080CA4280C4FFBF00065F000017FBBFE045
+:101800001700801015FABFE015FD3FE017A3A0D028
+:1018100015FEBFE00608000017FEFFE017FBBFE063
+:101820002608801817FEBFE015FDBFE017FEBFE0D9
+:101830001700801015FEBFE017FEBFE01EF63F1038
+:10184000060100003A88010017FEBFE01E070010E5
+:1018500040CD2880440100018036298017FC3FE1FB
+:1018600080CA4280C4FFBF000643000017FBBFE0F0
+:10187000170A80102609001017FBBFE0170A801016
+:1018800015F9BFE017F9BFE01708801017FC3FE11A
+:101890003AE83E1015FFBFE00626000017FBBFE048
+:1018A0008B058010CCFFBF100C0880101E060010A6
+:1018B000440100018036298017FC3FE180CA428044
+:1018C000C4FFBF00062C000017FBBFE08B05801093
+:1018D000CCFFBF100C208010260A001017FBBFE0C1
+:1018E000170680102607001017FBBFE01706C01070
+:1018F00017FBBFE0170980103A880B103A880918C7
+:1019000080F3408017FBBFE08B058010CCFFBF1039
+:101910000C1080102605001017A8A0D0C4FFBF101F
+:1019200015A8A0D017FB3FE10086298015FF3FE0F6
+:101930003A88010017FDBFE02604001017FDBFE044
+:1019400017FAFFE01500C0100602000017FABFE00A
+:1019500015A3A0D017FB3FE18067418044008000C1
+:1019600015A5A0D0440100018036298017FC3FE175
+:1019700080CA428017FFBFE03A8837E01701C0DF16
+:10198000170000DF0402C0DE3A2800F804F6FFDE8C
+:101990001509C0DF150800DF040800DF15FB3FE173
+:1019A00015FA7FE115F9BFE115F8FFE144010001E7
+:1019B000402B298017F83FE100544280264D00104B
+:1019C00017F8BFE0170180101E0400104401000149
+:1019D000803629803A8805000649000017F8BFE0E4
+:1019E00017018010170A80102610001017F8BFE0AA
+:1019F00017018010170A801015FEBFE017FEBFE028
+:101A00001703801017F8FFE117F9BFE117FA7FE11C
+:101A100017FB3FE13AE83E1015FDBFE0440100012D
+:101A20008036298017FDBFE00635000017F8BFE0BB
+:101A300017018010170680101E04001044010001D9
+:101A4000803629803A880500062D000017F9FFE04E
+:101A500017FABFE03A38851815FFBFE017F8BFE066
+:101A60001702C01017F8BFE017018010170680108A
+:101A70003AC8851815FCBFE017FCFFE017FFBFE070
+:101A80003A88851817F8FFE01701C0181708C01822
+:101A90002E06801817F8BFE0170180101708C01035
+:101AA00017FCBFE03AC8851815FFBFE017F8BFE084
+:101AB0001702801017FFBFE13A880B1017FB3FE1B8
+:101AC000806B088017F8BFE01702C01017FFBFE057
+:101AD0003A88871817F8BFE01502C01044010001CA
+:101AE0008036298017FA7FE117FF3FE180FF0C80E5
+:101AF0000603000044010001803629803A88050071
+:101B00003A8837E01701C0DF170000DF0402C0DEAB
+:101B10003A2800F804F2FFDE150DC0DF150C00DFD7
+:101B2000040C00DF15F73FE115F67FE115F5BFE185
+:101B300015F4FFE117F43FE1005442801E0200104B
+:101B40004402800006D9000017F4BFE0170180109E
+:101B5000170A8010260E001017F4BFE0170180103E
+:101B6000170A801015FFBFE017FFBFE017048010B1
+:101B700017F4FFE117F5BFE117F67FE117F73FE133
+:101B80003AE83E1015FEBFE017FEBFE006C70000B2
+:101B900017F4BFE0170180101E0200103A880500FC
+:101BA00006C2000017F4BFE01701801015FDBFE06A
+:101BB00017FDBFE08B058010CCFFBF100C08801014
+:101BC0001E05001017F4BFE084F9FF001504C010D3
+:101BD0003A88050006B5000017F6FFE017F5BFE0EC
+:101BE0003A38851815FCBFE017FCBFE01E02001054
+:101BF0003A88050006AD000017FDBFE0170680100B
+:101C00001E3D001017FCBFE0C4FFFF100400B80029
+:101C10003A7084180400881015FBBFE017FB3FE101
+:101C200000E740803A88071017FDBFE01506C01096
+:101C300017FDBFE0170680101E05001017F4BFE067
+:101C400004FBFF001504C0103A8805000697000049
+:101C500017FDBFE017FBFFE01509C01017FDBFE03F
+:101C600017FCFFE01507C01017FDBFE017FCFFE0F1
+:101C70001508C01017FDBFE01706C01017FCBFE025
+:101C80003A88871817F4BFE01502C01017FDBFE0AF
+:101C90008B05C01084FFBF003A7084183A88071083
+:101CA00017FDBFE08D05C01017FDBFE08B0580104C
+:101CB000148080103A88071017FDBFE08D05C01012
+:101CC00017FDBFE08B058010142080103A880710A4
+:101CD00017FDBFE08D05C01017FDBFE0170680108F
+:101CE00017FCBFE117F77FE13A880910806B088085
+:101CF00017F5BFE0066D000017F4BFE01702C01033
+:101D000017FDBFE0170680103AC8851815FABFE026
+:101D100017FAFFE017FCBFE03A88851817FDFFE0CF
+:101D20001709C0182E38801817FAFFE017FCBFE01B
+:101D30003A888518C4FFFF100400B8003A70841870
+:101D40000400881015F9BFE017F93FE100E7408073
+:101D500015F8BFE017F8BFE01E05001017F4BFE04C
+:101D600004FBFF001504C0103A880500064F000070
+:101D700017FDBFE01706C01017FDBFE01708801061
+:101D80003A880D103A880B1817F83FE1806B0880ED
+:101D900017FDBFE08B058010CCFFBF100C2080101A
+:101DA0002607001017FDBFE01706C01017FDBFE0A3
+:101DB000170980103A880B103A88091880F3408080
+:101DC00017FDBFE017F8FFE01506C01017FDBFE0D4
+:101DD00017F9FFE01509C01017FDBFE08B05801053
+:101DE000142080103A88071017FDBFE08D05C01041
+:101DF00017FDBFE01706C01017FABFE03A88871832
+:101E000017F4BFE01502C01017F4BFE017028010EE
+:101E100017FCBFE117F77FE13A880910806B088053
+:101E200017F4BFE01702C01017FCBFE03A8887180C
+:101E300017F4BFE01502C01017FAFFE017FCBFE06F
+:101E40003A88851817FDFFE01708C0182E0580187E
+:101E500017FAFFE017FCBFE03A88871817FDBFE0CC
+:101E60001508C01017FDBFE01708C01017FDBFE030
+:101E70001507C01017FDBFE08B05C01084FFBF0021
+:101E80003A7084183A88071017FDBFE08D05C0101E
+:101E900017FDBFE08B058010148080103A88071072
+:101EA00017FDBFE08D05C01017F5BFE03A8837E099
+:101EB0001701C0DF170000DF0402C0DE3A2800F877
+:101EC00004F9FFDE1506C0DF150500DF040500DF9D
+:101ED00015FE3FE115FD7FE115FCBFE115FBFFE1BC
+:101EE00044010001402B298017FBFFE117FCBFE1F3
+:101EF00017FD7FE117FE3FE1C0A5418015FFBFE060
+:101F0000440100018036298017FFBFE03A8837E09E
+:101F10001701C0DF170000DF0402C0DE3A2800F816
+:101F200004F9FFDE1506C0DF150500DF040500DF3C
+:101F300015FD3FE115FC7FE115FBBFE14401000108
+:101F4000402B298017FD3FE10054428026410010BC
+:101F500017FDBFE0170180101E04001044010001AE
+:101F600080362980C4FFBF00063D000017FDBFE09A
+:101F700017018010170A8010260F001017FDBFE010
+:101F800017018010170A801015FFBFE017FFBFE090
+:101F90001705801017FBBFE117FC7FE117FD3FE13C
+:101FA0003AE83E1015FEBFE044010001803629806A
+:101FB00017FEBFE0062A000017FBBFE0600080109C
+:101FC0001E0D001017FBBFE0A00080101E110010B6
+:101FD00017FBBFE01E1B001017FDBFE017018010AC
+:101FE0001706C01017FCBFE03A88871817FDBFE03E
+:101FF0001502C0100613000017FDBFE01702C01045
+:1020000017FCBFE03A88871817FDBFE01502C01023
+:10201000060C000017FDBFE0170180101706C01066
+:1020200017FDBFE0170180101708001117FCBFE073
+:102030003A8885203A88871817FDBFE01502C0103E
+:102040003A88010044010001803629803A88050061
+:10205000060300004401000180362980C4FFBF0050
+:102060003A8837E01701C0DF170000DF0402C0DE46
+:102070003A2800F804FBFFDE1504C0DF150300DF7B
+:10208000040300DF15FD3FE144010001402B2980DE
+:1020900017FD3FE1005442802631001017FDBFE0DC
+:1020A000170180101E0400104401000180362980B1
+:1020B000C4FFBF00062D000017FDBFE01701801010
+:1020C000170A8010260D001017FDBFE017018010C1
+:1020D000170A801015FFBFE017FFBFE0170680103A
+:1020E00017FD3FE13AE83E1015FEBFE04401000154
+:1020F0008036298017FEBFE0061C000017FDBFE0F8
+:102100001702C01017FDBFE017018010170600115D
+:1021100017FDBFE017018010170880103A8885204E
+:102120001E068018440100018036298017FDBFE09B
+:102130001701801017088010060C000044010001F0
+:102140008036298017FDBFE01702C01017FDBFE0E1
+:1021500017018010170680103AC885180603000082
+:102160004401000180362980440280003A8837E02B
+:102170001701C0DF170000DF0402C0DE3A2800F8B4
+:1021800004FBFFDE1504C0DF150300DF040300DFDE
+:1021900015FD3FE117FD3FE100544280262F00105E
+:1021A00017FDBFE0170180101E020010C4FFBF0022
+:1021B000062C000017FDBFE017018010170A8010E1
+:1021C0002609001017FDBFE017018010170A8010C4
+:1021D00015FEBFE017FEBFE01707801017FD3FE1B7
+:1021E0003AE83E10061F000017FDBFE017018010FF
+:1021F000170680101E020010C4FFBF000619000061
+:1022000017FDBFE01702C01017FDBFE017018010D7
+:102210001706001117FDBFE0170180101708801086
+:102220003A88852036038018C4FFBF0015FFBFE041
+:102230000608000017FDBFE01702801044000011DF
+:1022400017FDFFE01502001903008010CC3F80103D
+:1022500015FFBFE017FFBFE00602000040CD288059
+:10226000C4FFBF003A8837E01701C0DF170000DF66
+:102270000402C0DE3A2800F804FCFFDE1503C0DFCC
+:10228000150200DF040200DF15FE3FE144010001FA
+:10229000402B298017FE3FE1800C428015FFBFE0F4
+:1022A000440100018036298017FFBFE03A8837E0FB
+:1022B0001701C0DF170000DF0402C0DE3A2800F873
+:1022C00004FBFFDE1504C0DF150300DF040300DF9D
+:1022D00015FD3FE117FDBFE003008010CC3F8010EB
+:1022E0001C20801004E0BF10E00B80101E070010BF
+:1022F00017FDBFE003008010CC3F80101C20801031
+:1023000004E0BF10181780101E19001017FD3FE1E0
+:102310004037428015FEBFE017FEBFE01E120010DE
+:1023200017FDBFE003008010CC3F80101C20801000
+:1023300004E0BF10E00B80101E07001017FDBFE087
+:1023400003008010CC3F80101C20801004E0BF10E0
+:10235000181780101E06001017FDBFE04400801003
+:1023600015FDBFE00602000017FEBFE015FDBFE04F
+:10237000C40F400117FD3FE1C0DF4280260300107B
+:1023800040CD28803A8805000611000017A3A0D090
+:1023900015FFBFE0060B000017FFBFE0040180102F
+:1023A0003A880B1017FD3FE140220C801E020010FE
+:1023B00017FFBFE00606000017FFBFE01700801000
+:1023C00015FFBFE017FFBFE01EF33F103A8805007E
+:1023D0003A8837E01701C0DF170000DF0402C0DED3
+:1023E0003A2800F804FCFFDE1503C0DF150200DF09
+:1023F000040200DF15FE3FE144010001402B29806B
+:1024000017FE3FE18020428015FFBFE0440100013C
+:102410008036298017FFBFE03A8837E01701C0DF18
+:10242000170000DF0402C0DE3A2800F804F9FFDEDE
+:102430001506C0DF150500DF040500DF15FB3FE1D1
+:1024400017FB3FE14031278015FEBFE01734A0D0D5
+:1024500015FFBFE0063A000017FFBFE04400801000
+:1024600015FFBFE017FFBFE003008010CC3F8010D6
+:102470001C20801004E0BF10E00B80101EF63F10FF
+:1024800017FFBFE003008010CC3F80101C2080109D
+:1024900004E0BF1026370010C40B400117FF3FE1D6
+:1024A000C0DF428015FCBFE017FCBFE0260500102E
+:1024B00017FCFFE017FFBFE03AC8851815FDBFE025
+:1024C0000607000017FF3FE1C0DA028015FDBFE0FC
+:1024D0000603000017FEBFE04400801015FEBFE0B9
+:1024E00017FEBFE003008010CC3F80101C2080103E
+:1024F00004E0BF10E00B80101EF63F1017FDBFE098
+:102500003A880D1017FF7FE117FE3FE1C0FE4280C1
+:102510001E09001017FDBFE017FFFFE03A8885187D
+:1025200015FFBFE017FDBFE017FEFFE03A888518F2
+:1025300015FEBFE0060200003A88050006290000EB
+:1025400017FFBFE003008010CC3F80101C208010DC
+:1025500004E0BF102608001017FEBFE00300801043
+:10256000CC3F80101C20801004E0BF101EBD3F1027
+:10257000060100003A88010017FFBFE00300801049
+:10258000CC3F80101C20801004E0BF101E140010EF
+:102590000603000017FEBFE04400801015FEBFE0F8
+:1025A00017FEBFE003008010CC3F80101C2080107D
+:1025B00004E0BF10201780101EF63F1017FEBFE08A
+:1025C00003008010CC3F80101C20801004E0BF105E
+:1025D000E00B80101EEF3F1017FEBFE00601000069
+:1025E0003A8805003A8837E01701C0DF170000DF9E
+:1025F0000402C0DE3A2800F804FDFFDE150200DF09
+:10260000040200DF15FE3FE117A2A0D015FFBFE0D6
+:102610000608000017FFFFE017FEBFE01E0280184B
+:10262000440080000606000017FFBFE0170080107E
+:1026300015FFBFE017FFBFE01EF63F103A88050008
+:102640003A8837E0170000DF0401C0DE3A2800F8BE
+:1026500004FCFFDE1503C0DF150200DF040200DF0B
+:1026600015FE3FE144010001402B298017FE3FE1A8
+:102670000054428015FFBFE04401000180362980EC
+:1026800017FFBFE03A8837E01701C0DF170000DF0F
+:102690000402C0DE3A2800F804FDFFDE1502C0DFA8
+:1026A000150100DF040100DF15FF3FE144010001D7
+:1026B000402B298017FF3FE100544280260500107F
+:1026C000440100018036298017FFBFE01704801005
+:1026D000060300004401000180362980C4FFBF00CA
+:1026E0003A8837E01701C0DF170000DF0402C0DEC0
+:1026F0003A2800F804FDFFDE1502C0DF150100DFF7
+:10270000040100DF15FF3FE144010001402B298057
+:1027100017FF3FE1005442802605001044010001EC
+:102720008036298017FFBFE0150400100602000064
+:1027300044010001803629803A8837E01701C0DF64
+:10274000170000DF0402C0DE3A2800F804FEFFDEB6
+:10275000150100DF040100DF15FF3FE017FFBFE0B8
+:102760003A8837E0170000DF0401C0DE3A2800F89D
+:1027700004FEFFDE1501C0DF150000DF3A8839D8FE
+:102780001727A0D0260300101727A0D03AE83E1044
+:10279000060100000442A0D03A8837E01701C0DFEC
+:1027A000170000DF0402C0DE3A2800F804F7FFDE5D
+:1027B0001506C0DF150500DF040500DF15FC3FE14D
+:1027C00015FB7FE1150280E11503C0E117FCBFE0B6
+:1027D0001606001017FCBFE02403C010740182002D
+:1027E000041AB2103A888518060100003A880500DC
+:1027F00015FFBFE017FFBFE0262B001017FBBFE05F
+:10280000E00080101E04001017FBBFE020018010C4
+:102810001E070010061E000017FFBFE01702C010C1
+:1028200034009000C4FFBF103A70841806230000E3
+:10283000040280E015FDBFE017FDBFE00401C010F9
+:1028400015FDFFE01700801015FEBFE017FFBFE089
+:102850001702C010C4FDAF003A70861817FFBFE022
+:102860001502C01017FFBFE0170280103A8807104A
+:1028700017FEBFE00C0290103AB084183A88071097
+:1028800017FFBFE01502C0103A880500060B0000D4
+:10289000806B42803A8807108405800015008018FC
+:1028A000C4FFBF0006050000806B42803A88071015
+:1028B0004414800015008018C4FFBF003A8837E038
+:1028C0001701C0DF170000DF0404C0DE3A2800F85B
+:1028D00004FBFFDE1504C0DF150300DF040300DF87
+:1028E00015FD3FE11722A0D015FFBFE00631000023
+:1028F00017FFBFE0170280103A880910C0DA028083
+:1029000015FEBFE017FFBFE01702C01017FEBFE0C3
+:10291000C4FFBF103A88851803008010CC3F801098
+:102920001C20801004E0BF10D80B80101E03001084
+:1029300017FEBFE0C4FFBF1015FEBFE017FEBFE0EB
+:1029400017FDFFE03A88851803008010CC3F801007
+:102950001C20801004E0BF10E00B80101E08001047
+:1029600017FEBFE017FDFFE03A88851803008010CE
+:10297000CC3F80101C20801004E0BF101E0A001005
+:1029800017FFBFE01702801017FEFFE03A880D180E
+:1029900017FD7FE13A88091080CB42801E020010AB
+:1029A00017FFBFE00607000017FFBFE01700801009
+:1029B00015FFBFE017FFFFE00422A0D01ECCBF1818
+:1029C0003A8805003A8837E01701C0DF170000DFBA
+:1029D0000402C0DE3A2800F804F9FFDE1506C0DF65
+:1029E000150500DF040500DF15FB3FE104FABF0019
+:1029F00015FEBFE0178BA0D015FDBFE08DFC3FE0BA
+:102A00008BFCBFE044FCFFE03A880D183A880B10BD
+:102A100017FD3FE100A6158015FF3FE006170000F7
+:102A200017FFBFE02403C010740182003A888518A4
+:102A3000171AB2101E0E001017FFBFE0240300117A
+:102A400017FBFFE0740182003A888520151AF21006
+:102A50001726E0D017FFBFE00E02801817FFBFE077
+:102A60001526A0D017FFBFE015FEBFE00607000047
+:102A700017FFBFE04400801015FFBFE017FFBFE065
+:102A8000100480101EE63F103A880100178BA0D07A
+:102A90003A88091040D8158017FEBFE03A8837E021
+:102AA0001701C0DF170000DF0402C0DE3A2800F87B
+:102AB00004FEFFDE150100DF040100DF15FF3FE12A
+:102AC00017FFBFE084FEBF102804C0101E190018B5
+:102AD000BA900610340182003A888518178B8A1044
+:102AE0003A6800106C2A04086C2A04087C2A04083E
+:102AF0007C2A04087C2A04086C2A0408742A040826
+:102B00007C2A04086C2A04086C2A04087C2A04081D
+:102B10006C2A0408742A04087C2A04087C2A040805
+:102B20006C2A040844008000060300003A8805006F
+:102B3000060100003A8805003A8837E0170000DFF8
+:102B40000401C0DE3A2800F83A880B203A880F00CA
+:102B50003A880D003A880900814E45808402800140
+:102B60003A880B00813243808402C0013A880D000C
+:102B7000C130438004FEFFDE3A880B00150000DC04
+:102B80001501C0DF3A8821208057458074018200FA
+:102B900017AE3211170F8020260100103AE83E10C0
+:102BA0003A88098040974680740182003A880D284F
+:102BB0003A880B2017AF321141B04280680280285A
+:102BC0002652001004FAFFDE150140DCC402403436
+:102BD0001503C0DC1505C0DF150400DD150280DC1F
+:102BE000150000DCF00580883A8827201E39001087
+:102BF00004FEBF003A70A2881638008836378089F4
+:102C0000280480283A8821281E01001004040004AA
+:102C1000040440813A884B2C3A880998C0DD07802B
+:102C20003A882510263000103A880998C0E00F80B5
+:102C30003A880B803A88099004FE3F95C0050D80C4
+:102C4000261B0010C4FF7F813AC805043A884B91C7
+:102C50003A708A2804FE7F293AC8072D0804801894
+:102C6000262C00103A88292817FFBF9004FF3F0147
+:102C70003A880B903A7004113AC8C51054000011FC
+:102C8000150100A13A8885A0170180113A8809989A
+:102C9000540080311501801117FFBF904C00801047
+:102CA0003AB0C41015FFBF90401C0780040280A4F6
+:102CB000170180A004FFFF003A70C4103AC8451401
+:102CC0001004C010261700183A880998C0F20F8027
+:102CD00006050000040440042EC9BF8904038000D7
+:102CE000150080983A8825003A8805901705C0DFBE
+:102CF000170400DD1703C0DC170280DC170140DC7D
+:102D0000170000DC0406C0DE3A2800F83A880B30D1
+:102D1000C1DD07803A880B2C3AC8072D3A8829284C
+:102D200006D13F003A884BA454008010150180283A
+:102D3000170180A0040240293A8809984C008010AD
+:102D40003AB06214150140A4401C078006DE3F0023
+:102D5000740182003A880B2017AF3211C1DD078061
+:102D6000740182003A880B2017AF3211411C078092
+:102D7000300180301E0B00103AB04421CC0080108E
+:102D80001E1A00101700C020170080281E17801878
+:102D900004FFBF31280180300401002104014029D3
+:102DA0001EF83F10C4FFFF30260E003003008029BC
+:102DB000030080201E0F8030440080184400C02093
+:102DC0003A88892006050000030080180300802946
+:102DD0004400C018CC3F80101E06801144004029DA
+:102DE0001EF93F193A8805003A2800F8C4FFFF3061
+:102DF00006EE3F003AC885113A2800F804E4FFDEE9
+:102E00003A881128151AC0DF151BC0D93400A0005C
+:102E1000F4FFFF00C4FFBF100482C018041BC0D918
+:102E20003A880BD81503C0D8150000DA150400DA6B
+:102E3000150580D8150280D8003443801700C0D80B
+:102E400005000018171AC0DF041CC0DE3A2800F87D
+:102E500004E3FFDE3A881120151AC0DF151B80D964
+:102E6000151CC0D97401820017AF3211F4FFFF00A6
+:102E70003400A000C4FFBF100482C0183A880D2897
+:102E8000041BC0D93A880BD81503C0D8150000DA46
+:102E9000150400DA150580D8150280D80034438067
+:102EA0001700C0D805000018171AC0DF041DC0DEC7
+:102EB0003A2800F8CC3F402A3A881128CC008020DC
+:102EC00026370048260B0010030080202632001011
+:102ED000264F80483A8807480603000003008020F8
+:102EE000262D0010264AC01044000021CC0080206E
+:102EF0001EFA3F10CC3F40293A9204281700C02008
+:102F0000F4BFFF013AB08A283A941628C4BFFF39AB
+:102F10003A88C5193AB056593AF0CA583A88CD2974
+:102F20003A30C6003A304A013A70C4103A704A3119
+:102F30007420A0023AB044110420A0523A708412C6
+:102F40001E0C0010040100211700C0203AF0CA1A1C
+:102F50003A88C5193A88CD293A30C6003A304A0134
+:102F60003A70C4103A704A313AB044113A7084123F
+:102F700026F43F10030080202607001026248048F6
+:102F8000CC3F00420601000026210012440000212F
+:102F9000030080201EFC3F103A8805003A2800F804
+:102FA000260500100300802026190010440000218F
+:102FB000CC0080201EFB3F101700C020F4BFBF01D3
+:102FC000C4BFBF313A888519742060013A30C60009
+:102FD0003A70C410042060293A7044111E07001092
+:102FE000040100211700C0203A8885193A30C60034
+:102FF0003A70C4103A70441126F93F100300802043
+:103000002603001044000021030080201EFD3F1015
+:103010003A8805203A2800F83AB00629CC00C018B2
+:103020003A8805201E1D00181700C029F4BFBF02F2
+:10303000C4BFBF523A88873A3A30C8017420600250
+:103040003A7006190420604A3A70461A3A880D1000
+:103050001E090018040180310401402915FFFF31C9
+:103060001700C0293A88873A3A30D0013A70061AD8
+:103070003A70461A26F73F1844004029C3FFFF283C
+:1030800044008031C5FFFF30CC3FC0181C20C01861
+:1030900004E0FF181EF83F183A2800F83A880D207F
+:1030A00006F53F00263700303AB04421CC008010AE
+:1030B0001E1F0010300180301E1D001017008020E0
+:1030C0001700C0281E31C01004FFBF31262D00306C
+:1030D000F4BFBF02C4BFBF523A8887127420600297
+:1030E0003A3084003A7084180420604A3A704412DE
+:1030F000260B0010062300001700C0201700C0296F
+:103100003A88851A3A30D0003A7004123A70441264
+:103110001E1EC01904FFBF31261A00301E190010F0
+:1031200030018030040100210401402926F23F10C3
+:10313000070080200700C028C4FFBF311E0DC0104B
+:1031400026100030260F0010440080203A888D2180
+:1031500006030000260B8011440080102609001889
+:10316000440040290700C0100700C0293A88091010
+:1031700026F8FF19030080200300C0283AC8C510B4
+:103180003A2800F83A8805003A2800F80700C028D5
+:1031900007008020C4FFBF3126EABF1806F53F00B4
+:1031A00004F5FFDE150640DD150500DD1504C0DC65
+:1031B000150000D9150AC0DF150900DF1508C0DDAC
+:1031C000150780DD150380DC150240DC150100DCED
+:1031D0003A8827283A8829303A882B383A880928AB
+:1031E000060100003A88098044000024C3FFFF80E4
+:1031F000340182003A888518C3759C100C02801037
+:103200001EF83F10580B801826520010E00A801854
+:103210001E2500103A8823183A883900262600A86F
+:10322000200480A81E4F00103A882DA83400E00525
+:103230001E0100E0C4FFFFBD3A880BB03A8809B810
+:10324000C0050D803A880BB03A8809B83A88251035
+:1032500080FF0C803A880F103A880B003A880500EE
+:1032600004F4FF88A802001926040020C4EFFF8898
+:10327000A806C0181E18001844F2FF880E1B401D37
+:10328000E0FF3F291E05002036118038260F8038C8
+:103290003A3889B0440040013A8805194400008456
+:1032A000C3FF7F8406EE3F00030040843A88390064
+:1032B000840000241EDA3FA8200C80881E360010EF
+:1032C000840280058402400506D83F000EF0FF907E
+:1032D000C4FF7F0106F13F00C4E7FF88A806C018BD
+:1032E0001E02001844EAFF8816E57F1DD8FFFF285C
+:1032F00026110018260100E03AC88500260200A029
+:103300001E2E00281500C0A4170AC0DF170900DF11
+:103310001708C0DD170780DD170640DD170500DD43
+:103320001704C0DC170380DC170240DC170100DC47
+:10333000040BC0DE3A2800F81700C0D884088000CB
+:1033400015008018261B00A0C4FFFF843A8805B82A
+:1033500006EC3F0003004084440000078400002482
+:1033600006AE3F00180C80881E0400100300808009
+:10337000CC378010201680101E0200100404800537
+:1033800006AA3F00430040840404800584000084B2
+:103390000404400506A53F0003008080CC37801060
+:1033A000201680101EF73F1004028005040240051D
+:1033B000069E3F003A8805B806D33F003A882F1092
+:1033C00006E13F00810E4380740182003A880F308D
+:1033D0003A880D283A880B2017AF3211810E4380AE
+:1033E000740182003A880F303A880D283A880B2001
+:1033F00017AF3211810E438004BDFFDE1542C0DFDE
+:10340000153E40DD153CC0DC150500D93A8827285B
+:103410003A882B301506C0D9154100DF1540C0DDB4
+:10342000153F80DD153D00DD153B80DC153A40DCA5
+:10343000153900DC00BF0780170080103A8809109A
+:10344000150D80D8C0DA0280150B80D80B03809848
+:103450000C2080102602001017048098269A051070
+:103460000429C0DD151CC0DD151E00D8151D00D8AF
+:10347000150800D8150900D8150A00D83A8811B8DF
+:10348000150C00D8151100D8150400D83A882DA8BD
+:10349000070080B026910010600980101EF604100D
+:1034A0003A8821B006020000268200183A8821904E
+:1034B00047008080440080845809C0101EFA3F10E5
+:1034C0003AC8A39526850088171EC0D8171D80D836
+:1034D000150080453A88471C44008010151D80D88F
+:1034E00015014044151EC0D8080280101E7400103B
+:1034F000040200421704C0D8470080803A88471C65
+:103500001504C0D8267500104700809244008095AD
+:10351000451500D83A8809003A880B00C4FFFF021D
+:103520003A8823003A881900440080B53A88395017
+:1035300004F8BFE06816C0101E8A0018BA90041084
+:103540003401C2003A88C71017268D183A68001057
+:103550007C370408AC360408AC360408703704081D
+:10356000AC360408AC360408AC360408AC360408A3
+:10357000AC360408AC360408483704083837040869
+:10358000AC36040820370408DC360408AC360408DE
+:10359000D03604087C3604087C3604087C360408DF
+:1035A0007C3604087C3604087C3604087C36040823
+:1035B0007C3604087C360408AC360408AC360408B3
+:1035C000AC360408AC360408AC360408AC36040843
+:1035D000AC360408AC360408AC360408AC36040833
+:1035E000303D0408503C0408AC360408503C040844
+:1035F000AC360408AC360408AC360408AC36040813
+:10360000843E0408AC360408AC3604081C3C0408AC
+:10361000AC360408AC360408AC360408AC360408F2
+:10362000AC360408503E0408AC360408AC36040836
+:10363000083E0408AC360408AC360408AC3604086E
+:10364000AC360408AC360408AC360408AC360408C2
+:10365000AC360408AC360408AC3604080439040857
+:1036600090380408503C0408503C0408503C0408BE
+:10367000883B040890380408AC360408AC360408CB
+:10368000743B0408AC360408343B0408F43A0408DC
+:10369000A03B0408943B0408AC3604083038040806
+:1036A000AC360408F0370408AC360408AC3604081D
+:1036B000A83704083AC8A39526933F8806823F009E
+:1036C000170500D9041C80D93A880B9800694580F9
+:1036D0001E0800103A8811B806863F00171E80D8D1
+:1036E00026040010170500D9041C80D93A880B98CD
+:1036F000006945800B0380980C1080101E2D071068
+:10370000170480D81742C0DF174100DF1740C0DD23
+:10371000173F80DD173E40DD173D00DD173CC0DC64
+:10372000173B80DC173A40DC173900DC0443C0DE6D
+:103730003A2800F83A88230004F4BFE0440080B53A
+:10374000A402408CC7FF3FB73A88631404F4BFE07B
+:10375000B002C0101EF93F1804F8BFE06816C01090
+:1037600026763F18CC3F00211E8C062026DB3FE04A
+:10377000051F00DF451500D8440000054400400542
+:10378000041F00DC0696000014200063070080B2CE
+:1037900006653F00070000B74400C0B0A00A80E003
+:1037A0001E49071004F4BFE0B00280113A882D18BA
+:1037B0003A881700265E3F30440080B5A402C05A04
+:1037C000C7FF3FB73A88975804F4BFE0B002C01073
+:1037D0001EF93F1806563F00030000B7CC3F80E2B9
+:1037E0001C2080521401006304E0BF52064E3F00CB
+:1037F00044000001C40A4001070080B2064A3F00AD
+:10380000170680D8030000B7170040140401801089
+:1038100016900488150680D8CC3F80E21C20805288
+:1038200004E0BF5206403F0054000063070080B22E
+:10383000063D3F00CC3F80281C20801004E0BF10D4
+:10384000030000B71EF43F10CC3F80E21C208052E2
+:10385000440000010408400104E0BF5206323F006A
+:10386000CC3F00211EB006203401820004209D10B0
+:10387000150C80D80C08806026980110170680D897
+:10388000170000151701401504028010150680D896
+:103890004C008060260200103AB044A51E67041058
+:1038A0008400800006FB0000CC3F00211E9A062009
+:1038B0000C0880601EA40110170680D80C04C0609C
+:1038C00017000015040180101E9601180C10C0602E
+:1038D00026AB0518150680D8CCFF3FA53A882B00EB
+:1038E0004400800006EB0000170680D8451500D87C
+:1038F000170000140401801426120580150E00DA4A
+:10390000150700DBE0FFBF581E6704103A880D580A
+:103910003A880B003A8809801506C0DA005D0880F5
+:103920001706C0DA170700DB170E00DA2668061044
+:103930003AC82B143A8829A80E0100A83A88290011
+:10394000150680DC06260000CC3F00211E7C0620E8
+:103950000C0880601E830110170680D80C04C0601C
+:10396000040180101E2701180C10C06026250118C4
+:103970001706C0D8150680D80F00001DFAD72BA057
+:103980003A8805A816250110D8FFBF58431540DB1B
+:1039900026820110C4DFFF003AB044A53A70D86017
+:1039A0001E7E01101E8001583A8825603A88170053
+:1039B0003A882B003A8821B8068001001706C0D843
+:1039C000451500D844000005170080180401C018F0
+:1039D0001506C0D8051F80D844004005041F00DC30
+:1039E0003A8825603A881700150700D88C00809324
+:1039F00026010070840000A50C214093171EC0D83A
+:103A00001E0200683AC80F8D16A6C201471580D85D
+:103A1000260C0010171D80D8441500D94400C0188A
+:103A2000440080101500004144000001151D80D89D
+:103A300015010041151EC0D8080280101ED30210C7
+:103A400004020042260C0070171D80D8841500D98E
+:103A50008400C0184400801015000041840000015B
+:103A6000151D80D815010041151EC0D80802801010
+:103A70001ED40210040200421820406B26CA0168BE
+:103A80003AC84F5D1601C2010C4080901E790110AA
+:103A9000171D80D83A88471D150000444400801047
+:103AA000151D80D815014045151EC0D8080280108C
+:103AB0001E720210040200420C0180942602009043
+:103AC0003AC8218D160900040E01008D3A8823A002
+:103AD000170480D83A884514150480D81E1F021890
+:103AE000151D00D83A8811B806693E00740102031A
+:103AF0005004008144382E63171D80D81E1C0020FE
+:103B000004048004170540DD3A883960060400008B
+:103B100004FC3F8448040081040200422613002074
+:103B2000440080100404C0181500004715018044AB
+:103B3000151EC0D8151D80D80802001126F43F209C
+:103B4000041C80D93A880B983A8809A800694580F6
+:103B50001EE83E1004FC3F8448040081171EC0D8B4
+:103B6000171D80D83A8811B81EED3F203A8819E019
+:103B7000440080103A88071C151D80D815000043AA
+:103B800015010044151EC0D8100280101ECE3F1033
+:103B9000170500D9041C80D93A880B980069458024
+:103BA0001ED43E10171EC0D806C73F00CC3F0021D0
+:103BB0001EE105200C0880601EF10010170680D859
+:103BC0000C04C06017000015040180101E48001886
+:103BD0000C10C06026330518150680D8CCFF3FA511
+:103BE0003A882B003A880500062A0000CC3F0021C5
+:103BF0001ED70520170600D90C0880600401C020DC
+:103C00001E8703100C0480601EDC03100C10006380
+:103C100026DA0360170680D81506C0D81704C0D866
+:103C2000170080100D00C01006193E00070080B27A
+:103C3000181B80502634041014040063063A3E001A
+:103C400014100063070080B206373E0014080063BA
+:103C5000070080B206343E001706C0D8040C80006E
+:103C6000851580D8041E800034010201C51580D856
+:103C70001700001D04018018150680D804209D201F
+:103C8000150C80D83A882B009400006384008000D3
+:103C9000041E0007451500D8E0FFFF583A881B00B6
+:103CA0001E680018C4DFBF043AB046A53A70A46489
+:103CB0001EFA01181E1004581E3C3F104C004065AF
+:103CC000260103A8040C8000C52880D8C42800DC85
+:103CD00006BA0000CC3F00211E9505200C0880602C
+:103CE000140400631EA60010170680D8040180107B
+:103CF0001706C0D83A882B00150680D81700001D7B
+:103D00003A88050006E33F00CC3F00211E8E0520C7
+:103D10001706C0D83400A000C4FFBF101701001D53
+:103D20001700801C34FCDF013A70A0A0C4FFBF0163
+:103D300004028018C4FFFF393A8809903A880B8042
+:103D4000150F00DA150EC0DA150700DB150A00DDC5
+:103D5000150980DC150680D880550F80170700DB19
+:103D6000170EC0DA170F00DA1ED9021034FCDF017B
+:103D7000C4FFBF01C4FFFF393A8809903A880B801D
+:103D800000470E80170700DB170EC0DA170F00DAA6
+:103D90000ECF82003A880D003A880F003A880990C9
+:103DA0003A880BA0150E00DA00470E80170700DBDB
+:103DB000170E00DA16DB0410431540DB101280E00A
+:103DC0001EB504103401020404181D84C4DFBF04AE
+:103DD0003A70A464C4000005C40040053A88170086
+:103DE000150700D806790000CC3F00211E4C0520A5
+:103DF0000C088060140400631E5A0010170680D857
+:103E0000040180101706C0D81700001D150680D8C1
+:103E1000FAD72BA03A8805A80EDB3E103AC8290530
+:103E20003AC004A03AC86B053AC8ABA8440B80005E
+:103E3000451580D8E0FFFF58440B40034400800044
+:103E400026983F186000C0101E540018A000801073
+:103E50001EE801103A8807B8060100003A8807807A
+:103E6000FAD008A07A970AA8FAD02AA8CC0100A50F
+:103E7000040C80A03AB02829C5FFBF183AB048A565
+:103E8000C4FF3F1C1EF53F204C0000612676002039
+:103E9000CC3F80101C20801004E0BF10180C801054
+:103EA0002671001084FFFF18040C8000C5FFBF803E
+:103EB0003AC8EBB83A8825603A882118063F0000D6
+:103EC000CC3F00211E12052034018200041B9D10EE
+:103ED000150C80D80C0880601E683E101706C0D8EC
+:103EE0000C0480601700001D0401C0181506C0D81E
+:103EF0001E5F02100C108060265D0210CCFF3FA5F3
+:103F00003A882B0006623E00CC3F00211E1205209D
+:103F10000C088060140400631E0B0010170680D884
+:103F2000040180101706C0D83A882B00150680D8E7
+:103F30001700001D4400800006563F001402006375
+:103F4000070080B206783D001706C0D84400800004
+:103F50001700001D1701401D0402C0181506C0D827
+:103F6000064C3F001706C0D8170180181700001D27
+:103F70000402C0181506C0D83A882B1006813E00EE
+:103F80001706C0D83A8805001700001D1701401D0C
+:103F90000402C0181506C0D8063E3F001E1100A836
+:103FA000A80280A01E0F0010040C00A5C52800DD8B
+:103FB0003A88256044004005C42800DC3A88295826
+:103FC0000E01405D3A8829A8150700D8CC3F406B08
+:103FD0001C20406B04E07F6B26843E68440000A5F3
+:103FE00006823E00150E40DC3A8821B83A8823A8A4
+:103FF000150700DB3A882B98150FC0DA3A88254060
+:104000003A882768060200003A8829103A8823185F
+:104010003A8809A03A880B88840280013A880F0008
+:10402000009C0C80040C8010C4FF3F843A8809A0D7
+:104030003A880B8805008080840280013A880F004E
+:1040400080420C801EF03F88A80200A51EEE3FA013
+:10405000170700DB170E40DC170FC0DA3A881B98F1
+:104060003A8811903A8827A83AC82BBC3A8825602C
+:1040700006D23F00901980E21EBE0050170900D9F9
+:10408000170A40D93A880D003A880F00150F00DA58
+:10409000150EC0D800300E80170EC0D8170F00DAEA
+:1040A0001E640110171D80D83401020104271D2150
+:1040B000440080104400C018150000414400000175
+:1040C000151D80D815010041151EC0D808028010AA
+:1040D0001EF8021004020042171680D81708C0D834
+:1040E0001602C0104C00809026680210170D80D870
+:1040F000171EC0D8170B00D915008040171D80D897
+:104100003A88C7201501004144008010151D80D851
+:10411000151EC0D8080280101E02031004020042BF
+:10412000170880D8C4FF3F140E633E0474010203D5
+:104130005004008144342E63171D80D81E3803209C
+:10414000150740DC04044005170500DF3A882360AA
+:10415000060400000402004204FC3F84480400817D
+:10416000262D0320440080100404C018150040448C
+:1041700015014045151EC0D8151D80D80802001134
+:1041800026F43F20041C80D93A880B983A8809E02D
+:10419000006945801E573D10171EC0D8171D80D8D6
+:1041A0003A8811B806EC3F003AC80F8D0E34FE0174
+:1041B000740102035004003944342E63171D80D863
+:1041C0001E270020150E80DC150F00DC151040DCCA
+:1041D000040440033A8821381512C0DA170540DC80
+:1041E0003A8825600604000004FC3F8448040081EE
+:1041F0000402004226140020440080100404C01869
+:104200001500804415014043151EC0D8151D80D8E7
+:104210000802001126F43F20041C80D93A880B982C
+:104220003A880988006945801E323D1004FC3F84AD
+:1042300048040081171EC0D8171D80D83A8811B8CD
+:10424000040440031EEC3F203A880F803A881990FE
+:10425000170F00DC171040DC1712C0DA170E80DCD5
+:10426000440080103A88C719151D80D815000043F6
+:104270001501C041151EC0D8080280101E940210FE
+:104280003AC84F5D040200420EFFFD0174010203B3
+:104290005004003944342E63171D80D81E25002099
+:1042A000150E80DC150F00DC151040DC0404C00284
+:1042B0003A882138170540DC3A882560060400005A
+:1042C00004FC3F84480400810402004226140020BC
+:1042D000440080100404C018150080441501C04239
+:1042E000151EC0D8151D80D80802001126F43F20E5
+:1042F000041C80D93A880B983A880988006945805F
+:104300001EFC3C1004FC3F8448040081171EC0D8EA
+:10431000171D80D83A8811B80404C0021EEC3F2053
+:104320003A880F803A881990171040DC170F00DC8C
+:10433000170E80DC440080103A88C719151D80D8FC
+:10434000150000431501C041151EC0D80802801099
+:104350001E3F01100402004206CB3D00170500D9A4
+:10436000041C80D93A880B980069458026DC3D10F2
+:1043700006E03C00170880D8171D00DF4400C01875
+:1043800088008010440040E50402804226020110AB
+:10439000440080001501804015000044151EC0D85F
+:1043A000151D40DD100280A8263E0110170B80D895
+:1043B000170D00D9440040AD3A8887181501805088
+:1043C00015000051151EC0D8151D40DD080280A83B
+:1043D0001E2B011004028052170880D8170900D93B
+:1043E000170A40D904020052C4FFFF12440000AF74
+:1043F0003A880D003A880F001512C0D8150F80DAE0
+:10440000150E00DA1507C0DA151000DF00300E8037
+:104410001707C0DA170E00DA170F80DA171040DB23
+:104420001712C0D826E80010440000843A88C71A42
+:10443000151D00DF150000541501C052151EC0D80F
+:10444000080200E71EDA01E004048050840000AF97
+:104450003A8815403A881110171100D9441880D8AD
+:10446000151D00DF3A88C720150080501501005146
+:10447000151EC0D8100200E71E8F3DE0170500D9B9
+:10448000041C80D93A880B98006945801E993C101D
+:10449000171EC0D83A8811B806873D003A8819908F
+:1044A00006683E00740102035004003944382E634C
+:1044B000171D80D81E2B0020151080DC151200DC83
+:1044C000151340DC0404C003150E80DB150F40DB20
+:1044D0001514C0DA3A882138170540DC3A8825607F
+:1044E0000604000004FC3F844804008104020042EA
+:1044F00026140020440080100404C01815008044D5
+:104500001501C043151EC0D8151D80D80802001122
+:1045100026F43F20041C80D93A880B983A880988F1
+:10452000006945801E733C1004FC3F8448040081F0
+:10453000171EC0D8171D80D83A8811B80404C003CC
+:104540001EEC3F203A880F803A881990170E80DBC6
+:10455000170F40DB171340DC1714C0DA171200DC0A
+:10456000171080DC440080103A88C719151D80D8C8
+:10457000150000431501C041151EC0D80802801067
+:104580001EBE01100402004206203D00170500D99E
+:10459000041C80D93A880B981510C0DA150F40DB3F
+:1045A000150E80DB006945801E523C10171EC0D8D6
+:1045B0003A8811B81710C0DA170F40DB170E80DBEE
+:1045C00006203D00170500D9041C80D93A880B98B5
+:1045D000150FC0DA150E40DB006945801E453C1002
+:1045E000171EC0D83A8811B8170FC0DA170E40DB73
+:1045F00006213D00170C00D93A8821B8CC0380A0D1
+:104600003A9706A83A8885203AD128A0030080105E
+:104610003AD12AA8C4FF3F843AB0281D0500808003
+:104620003AB044A51EF53F103AC82BBC3A88256025
+:1046300006623E00171600D90E680101170880D8DF
+:10464000170700D93A883910160581200E0A00078D
+:10465000171D80D83A88071F1500004444008010B9
+:10466000151D80D815010047151EC0D808028010FE
+:104670001E01031004020042160601E0170780D84D
+:104680003AC8391716190107171600D9170880D824
+:104690000EF68020170D80D8170B40D915008040EA
+:1046A000171D80D83A8847191501404144008010F1
+:1046B000151D80D8151EC0D8080280101EA6021035
+:1046C00004020042170880D8170740D93AC80511DC
+:1046D0000E3001293A8839100E0C0007170700D94F
+:1046E0003A88071F150100473A882181171D00D914
+:1046F00015000044151EC0D844000021151D00D926
+:10470000080200211EE70220040200420E0100E020
+:104710003A8839003AC839170EE73C07740102039A
+:10472000500400E144342E63171D80D81E7402200B
+:10473000150740DC04044005170500DC3A882360B7
+:10474000060400000402004204FC3FE7480400E1C4
+:1047500026690220440080100404C018150040445B
+:1047600015014045151EC0D8151D80D8080200113E
+:1047700026F43F20041C80D93A880B983A88098097
+:10478000006945801EDB3B10171EC0D8171D80D85E
+:104790003A8811B806EC3F004C0080901EFC3E1099
+:1047A00044008000151D40DD1500004415018040C7
+:1047B000151EC0D8080240AD1EFD00A8840000E709
+:1047C0000404004206243F000E23FF0250048058D8
+:1047D000740102031E2F031044342E63150780DC7E
+:1047E000150E40DC040400043A882358170500DF46
+:1047F0003A8825603A882B6806050000040280523A
+:1048000004FC7F8C48048088268E0110440040AD53
+:104810000404C0181500805415010054151EC0D89A
+:10482000151D40DD080280A826F43F10041C80D925
+:104830003A880B983A8809E0006945801EAD3B1024
+:10484000171D40DD171EC0D83A8815B806EC3F008A
+:10485000170500D9041C80D93A880B980069458057
+:104860001EA43B10171EC0D83A8811B806863C001B
+:104870003A882B0006063C003A8825B006223B0009
+:10488000170500D9041C80D93A880B980069458027
+:104890001E983B10171EC0D8171D40DD3A8815B86A
+:1048A00006CD3E00170500D9041C80D93A880B9824
+:1048B000006945801E8F3B10171EC0D8171D40DDB4
+:1048C0003A8815B806B93E003A8821B806BB3D00C3
+:1048D000170900D9170A40D9150F00DA3A880D20B8
+:1048E0003A880F28150EC0DA150700DB80550F80B7
+:1048F000170700DB170EC0DA170F00DA1ED90210F7
+:10490000C4F7FF003A70C6E0E0FFBF581507C0D8F3
+:104910001E620210D811801826A20010170A80D833
+:104920001440806416150210170A00DD050E00D829
+:10493000A01980E0150F80D81E530110A01180E04F
+:104940001E510110170780D8151200DA151000DB70
+:1049500058118010262B0210041A80D8150380D815
+:10496000170940D9041780D8170500D9150280D837
+:10497000041680D81500C0DA150180D88400C00163
+:104980003A880DA01508C0DAC03E05801708C0DAC5
+:104990003A882110D81980E0171000DB171200DACE
+:1049A0003A882B581E2902104C0080601E290210E4
+:1049B0001716C0D8170780D81507C0D8171AC0D83F
+:1049C000E01180103AC8071C1508C0D826710110E4
+:1049D0001707C0D850FFBF181E6D0110166CC158C4
+:1049E000170780D81708C0D8163DC2104C000063C6
+:1049F0001E7302603A8829100E0100103A882900BF
+:104A0000170740DDC4190007070E80D826170210CB
+:104A1000440B8000451580D83A881700066F3D008A
+:104A2000170440D9170080201506C0D8FAD70928E6
+:104A3000150040111501001106953A00040C800084
+:104A4000851580D8C51500DF9400006384008000C0
+:104A500006903C003AC86304150680D8065F3B0008
+:104A60003A88392016FA3E0706033F004C00809032
+:104A70001E083F10170880D8170740D93AC80511FB
+:104A80000E4400293A88391006203F00171EC0D86E
+:104A900006093C00170780D83A8839003AC8391708
+:104AA0000EF93E07061100003A880980C0DA02803C
+:104AB0003A882B103A882910150680DC170700DB8E
+:104AC000170E00DA06C63B00170500D90410400196
+:104AD000C0DD078015008098150480982686021096
+:104AE0000410800015058098065D3A0074010203E9
+:104AF000500400E144342E63171D80D81E74012039
+:104B00003A8809B0150E80DC150F00DC3A882D8834
+:104B1000040440053A8823E0170500DC3A88256044
+:104B20003A883920060400000402004204FC7F8C0D
+:104B300048040089265F0120440080100404C01846
+:104B40001500804415014045151EC0D8151D80D89C
+:104B50000802001126F43F20041C80D93A880B98E3
+:104B60003A880980006945801EE23A10171EC0D8B5
+:104B7000171D80D83A8811B806EC3F00170680D878
+:104B8000170080101506C0D81704C0D81500C01033
+:104B9000063F3A00170800D9170740D93AC87921CB
+:104BA00006CD3E001E5D3F584400C002065B3F003C
+:104BB000170500D9041C80D93A880B9800694580F4
+:104BC0001ECC3A10171D00DF171EC0D8042B00DAC8
+:104BD000440000E73A8815B8061F3E00171D80D82C
+:104BE0003401420104275D29440080104400C018AC
+:104BF0001500404144004001151D80D81501404179
+:104C0000151EC0D8080280101E4A0110040200427E
+:104C10001E540020170800D94C0080903AB00411AF
+:104C200026A53B10170D80D8170B00D91500804022
+:104C3000171D80D83A88C720150100414400801014
+:104C4000151EC0D8151D80D8080200111E55012060
+:104C500004020042170800D944008010151D80D8B6
+:104C60003A88C7201500004415010041151EC0D820
+:104C700008028010268F3B1006003E00170500D961
+:104C8000041C80D93A880B981510C0DA150F40DB48
+:104C9000150E80DB006945801E963A10171EC0D89D
+:104CA0003A8811B81710C0DA170F40DB170E80DBF7
+:104CB00006563B00170500D9041C80D93A880B988A
+:104CC000006945801E8B3A103A8811B806023D00F3
+:104CD000170500D9041C80D93A880B98150EC0DA44
+:104CE000006945801E833A10171EC0D83A8811B853
+:104CF000170EC0DA06623B006000C0103A881990B7
+:104D000026523C1806A83C00430000B71408006374
+:104D1000440080B5CC3F80E21C20805204E0BF52AA
+:104D200006013A00170500D9041C80D93A880B986F
+:104D3000006945801E6F3A10171EC0D83A8811B816
+:104D400006F73C00F00180583A882B5826110110D4
+:104D5000340102043A8829A8150680DC04251D8444
+:104D6000061F3B00170D80D8170B40D91500804057
+:104D7000171D80D83A88C72815014041440080108B
+:104D8000151EC0D8151D80D8080240111E05012827
+:104D9000040200420EAF3F207401020308FC7F2191
+:104DA00044342E633AC82B011E710128150700DC1C
+:104DB000040400073A8821A83A882B883A8823609F
+:104DC000060400000402004204FC3F844804008101
+:104DD00026630120440080100404C01815004044DC
+:104DE00015010047151EC0D8151D80D808020011F6
+:104DF00026F43F20170500D9041C80D93A880B9867
+:104E0000006945801E3B3A10171EC0D8171D80D878
+:104E10003A8811B806EC3F003A881988170740DC39
+:104E2000440080103A88071C151D80D815000043E7
+:104E300015010044151EC0D808028010261D3B1025
+:104E4000068E3D003A8817883A881990170E40DC84
+:104E5000170780DC440000AF040280503A88C71A6C
+:104E6000150000531501C052151EC0D8151D00DFD6
+:104E7000080200E11E4E3F20440000E70402001239
+:104E80003A88151006743D00041A80D8150380D89E
+:104E9000170940D9041780D8170500D9150280D802
+:104EA000041680D81500C0DA150180D8C400C001EE
+:104EB0003A880DA0151200DA151000DB1508C0DACB
+:104EC000C03E05801708C0DA3A882110171000DBB1
+:104ED0003A88EB1207008080171200DA200C80104D
+:104EE0001E3E0110171680D83A88ABA8170900D9C2
+:104EF0003A880D003A880F003A880BA0151200DAA4
+:104F00001510C0DA150800DB00300E80170800DB32
+:104F10001710C0DA171200DA269C0010171A80D872
+:104F2000040C00012E0540154400C010151AC0D80D
+:104F300005000011171A80D836FB7F153AC80514F2
+:104F40001707C0D8150880D8171680D8D811C018F0
+:104F5000150780D8269E3E18170F80D8260D001002
+:104F60001707C0D84C0080603AB0C4120EBBC00016
+:104F70001E380110170740DD3A8829A806A23E0016
+:104F8000150680D83A882B004400800006413B007B
+:104F900084FF3FE7170780D8451800DFC4FF7F155F
+:104FA000151640DD169200A8C40A8000851880D826
+:104FB000900280A81E190110150700DCC41B00DD3B
+:104FC0003A8821A8150F00DB3A882B983A882740A9
+:104FD000060200003A8829203A8821103A88098080
+:104FE0008402400100F80C80040C80103A8809808B
+:104FF000C5FFBFA08402400100F00C800819C080EA
+:10500000C4FF3FA11EF33F18040C8010C5FFBF2052
+:1050100084FFFFA0C41B00D93A881198170700DC51
+:10502000170F00DB3A8827A82E240119C41800D9CD
+:10503000060100000300801844000021C5FFBF20C6
+:105040004400C018C41B80D81EFABF18441C80D866
+:10505000C418C0D83AC805153A8885184418C0D86D
+:105060003AC8C510151180D81708C0D8171100D933
+:10507000880080183A882B1926EF0010170B80D86B
+:105080003A88ABA83A8829A80E0100A83A882900D6
+:10509000150700D8065C3E003401020404171D8485
+:1050A000064A3B00150680D83A882B003A8805004E
+:1050B00006F83A003A881990170F00DC170E80DCCA
+:1050C0003A8809E03A8839883A8823B03A882D200E
+:1050D000440080103A88071F151D80D81500004332
+:1050E00015010047151EC0D8080280101E38001098
+:1050F0000402004206643D003A881988170740DC24
+:10510000440080103A88071F151D80D81500004301
+:1051100015010047151EC0D80802801026653A10F8
+:1051200006D63C00440B8000451580D8440B400354
+:1051300006223B00170500D9041C80D93A880B9839
+:10514000006945801E6B3910171600D9171EC0D88C
+:105150003A8811B806AE3E00170500D9041C80D964
+:105160003A880B98006945801E623910171600D9DD
+:10517000171EC0D83A8811B806523D003C002015D1
+:10518000440B8000050E80D806E93D003A8805A84A
+:10519000066A3F008401400506ED3E00451540D9F2
+:1051A00006723900170500D9041C80D93A880B987B
+:1051B000006945801E4F3910171600D9171EC0D838
+:1051C000171D80D83A8811B80EA23E2006F23E0084
+:1051D000170500D9041C80D93A880B9800694580CE
+:1051E0001E443910171EC0D83A8811B806263D0053
+:1051F0004400C0003AC8AB18440B8000851880D822
+:10520000066B3F00041A80D8150380D8170940D9CF
+:10521000041780D8170500D94400405D150280D8D6
+:10522000041680D8150180D8150040DD8400C00127
+:105230003A880DA01508C0DAC03E05801708C0DA0C
+:10524000171000DB171200DA3A882110D81180E01D
+:1052500026D53D103A886B8506243F001E89001034
+:10526000440000054400400506E73D00431540DBCF
+:105270003A88170006553B00170500D9041C80D951
+:105280003A880B98006945801E1A3910171EC0D83D
+:105290003A8811B80EF93CE006FE3D008401C002D8
+:1052A000069E3D00170500D9041C80D93A880B984A
+:1052B000006945801E0F3910171680D8170800D9CD
+:1052C000171EC0D83A8811B83AC88520060F3D008D
+:1052D0003A882958150680DC3A882B5806C03900D0
+:1052E000170880D8170BC0D83A88EB10170780D85A
+:1052F00016038000170780D83AC8B9A8440040E5D3
+:105300003A8829A8163300A8C419000706BE3D0034
+:10531000451540D906EC3A00451540D906643900D8
+:10532000451540D906B23A00451540D9064E390018
+:10533000451540D906693A00451540D9061D3A0081
+:10534000451540D906823900451540D906703A0006
+:10535000451540D906273A00451540D906EC3A00D4
+:105360003A8819883A8823A83A882B80170700DCE6
+:10537000440080103A88471D150000431501404540
+:10538000151EC0D8151D80D80802001126303E20F9
+:10539000170500D9041C80D93A880B98006945800C
+:1053A0001ED43810171EC0D8171D80D83A8811B8DF
+:1053B00006283E00C4FFBF00150480D806D0380080
+:1053C000170780D8170BC0D83A88EB103A8829A85D
+:1053D0000ECD3FA83A88290006CB3F00170900D917
+:1053E0003A880D003A880F003A880BA0151200DAAF
+:1053F0001510C0DA150800DB00300E80170800DB3E
+:105400001710C0DA171200DA26B63E1044008000EA
+:105410003AC8C512151680D806B33E00040C8000A9
+:10542000040CC0A8C51880D8040180000519C0D894
+:10543000151180D8060C3F004C008060150780D8FD
+:105440001E0E3F103A8829A80E6F3DA83A88290001
+:10545000066D3D00170B80D83A8885183A88EB1204
+:1054600006F83F00170A80D816100010431540DBDD
+:10547000101280E01E0A001034010204041A1D8478
+:1054800006523A00170B80D8440080103A88EB127D
+:1054900006EC3F003A88054044342E63066F3E0018
+:1054A0003401020404191D8406483A00440B8000AC
+:1054B000451580D8440B400306ED3F008400800072
+:1054C000151180D806E83E00170680D81700C012D4
+:1054D000040180100E010058C4FFFF02430000B712
+:1054E000150680D83A882D18CC3F80E21C208052C7
+:1054F00004E0BF52060C38001705C0D80403800032
+:1055000015008018C4FFBF00150480D8067C380041
+:105510007401820017AFB2103A880F283A880D2024
+:10552000170240113A880910019746803A880F30D7
+:105530003A880D28170240210197468004E5FFDED6
+:105540003400A000F4FFFF003A881128C4FFBF1008
+:105550000482C0183A880BD8151AC0DF1503C0D8CA
+:10556000150000DA150400DA150580D8150280D878
+:10557000003443801700C0D805000018171AC0DF98
+:10558000041BC0DE3A2800F8740182003A880F300C
+:105590003A880D283A880B2017AF321141484580D0
+:1055A0007401820017AEF2101752801826170010EF
+:1055B0001701C0100808001A1E1B0040260B00200F
+:1055C000BA901018440040023A98D2483A88111212
+:1055D0001522804117628011980000213AB04C32A8
+:1055E000156280111542C041260B0020840000196D
+:1055F000BA9008204400C0181501C0103A8805115F
+:10560000150040113A8805003A2800F80453801824
+:105610001552801806E63F00176300113AB0522277
+:105620001563401206F13F00C4FFBF003A2800F89E
+:1056300004F7FFDE740182001507C0DD17AEF21516
+:10564000150540DD150400DD1503C0DC1508C0DFBD
+:10565000150680DD150280DC150140DC150000DC3C
+:105660003A8829203A882B284400C004175280BC6D
+:10567000260D009017010094C4FF7F84160A00884D
+:1056800044000084BA9020803A882194261100A812
+:1056900017408080260F4015C4FF7F8CD8FFBF883D
+:1056A00004FF3F841EF93F101708C0DF1707C0DD55
+:1056B000170680DD170540DD170400DD1703C0DC89
+:1056C000170280DC170140DC170000DC0409C0DE93
+:1056D0003A2800F81701809017008081C4FFBF109E
+:1056E000261540141500008026EB3F303A98469C62
+:1056F00017628090170180953A7084181E0600107A
+:105700003AE83E30170180901ED8BF15175280B876
+:1057100026E1BF1406D53F00176380901720008153
+:105720003A7086181E0600183A880B203A8809A09D
+:105730003AE83E3006F33F001501409406EA3F0088
+:105740003AE83E3006EF3F001702803004F6FFDEF5
+:105750001503C0DC1509C0DF150800DF1507C0DD23
+:10576000150680DD150540DD150400DD150280DC21
+:10577000150140DC150000DC3A8827302654001063
+:105780003A8829203A8821281700803517000029F7
+:105790001702402CC4DF7E05063400000B03808016
+:1057A0000C20C110262400181705808117044081A1
+:1057B0004400C090E40080313AC86F213A88C71D88
+:1057C000FAD722303A88A3897AD023883A880D887C
+:1057D0002E02C0883A8823183A880D180C008110D0
+:1057E000262B00103A880B303A8809A0C0DD0780CC
+:1057F000262E0010170440813A880DB83A88091007
+:10580000806B08803A8807100B0380803A7044153B
+:10581000142080100D0380803AC8C58D3A88C91DB8
+:10582000150540841504C080150000813A88239036
+:10583000150280803A882F903A880DB83A880BE09C
+:10584000807B08801702C0801700008117028098B3
+:105850003AC8631C3A88C9251502408415000081A6
+:105860003AC8A5141502809C26190090170180B42F
+:10587000170000B73A882F88040280B526FB3F90B6
+:105880002EC67F943A8823903A882F9006EA3F00EC
+:105890003A8809A0C0AB09803A8807101EDE3F1085
+:1058A000170440813A8809A0401C07800B03C08080
+:1058B00004038000150080A01410C0180D03C080E0
+:1058C000C4FFBF00150200981501009806020000F1
+:1058D000150100983A8805001709C0DF170800DF96
+:1058E0001707C0DD170680DD170540DD170400DD52
+:1058F0001703C0DC170280DC170140DC170000DC56
+:10590000040AC0DE3A2800F80B03802804D0FFDE2A
+:10591000152E00DF152C80DD152A00DD152FC0DFC8
+:10592000152DC0DD152B40DD1529C0DC152880DCC8
+:10593000152740DC152600DC0C2080101503C0D98B
+:105940003A8829283A882D203A88393026020010D2
+:1059500017048028269B0310041680DC150980DCC0
+:10596000150B00D8150A00D83A881190150400D8F4
+:10597000150000D8070080E0269000106009801014
+:105980001E7503103A8821E00602000026810018E7
+:105990003A88218847008080440040845809C0101C
+:1059A0001EFA3F103AC8278F26840098170BC0D8DC
+:1059B000170A80D8150000473A88C71C4400801099
+:1059C000150A80D81501C044150BC0D808028010F4
+:1059D0001E730010040200421700C0D847008080E8
+:1059E0003A88C71C1500C0D826740010470080886C
+:1059F0004400008F450800D83A880B003A880D0013
+:105A0000C4FF7F023A8821003A881900440000E769
+:105A100004F8FF10681600191E8A0020BA900618B4
+:105A2000340102013A880919175ED6203A68001835
+:105A30005C5C04088C5B04088C5B0408505C040804
+:105A40008C5B04088C5B04088C5B04088C5B04088A
+:105A50008C5B04088C5B0408285C0408185C040850
+:105A60008C5B0408005C0408BC5B04088C5B0408C5
+:105A7000B05B04085C5B04085C5B04085C5B0408C6
+:105A80005C5B04085C5B04085C5B04085C5B04080A
+:105A90005C5B04085C5B04088C5B04088C5B04089A
+:105AA0008C5B04088C5B04088C5B04088C5B04082A
+:105AB0008C5B04088C5B04088C5B04088C5B04081A
+:105AC000C86104088C5B04088C5B04088C5B0408C8
+:105AD0008C5B04088C5B04088C5B04088C5B0408FA
+:105AE0008C5B04088C5B04088C5B040894610408DC
+:105AF0008C5B04088C5B04088C5B04088C5B0408DA
+:105B00008C5B0408606104088C5B04088C5B0408EF
+:105B1000186104088C5B04088C5B04088C5B040827
+:105B20008C5B04088C5B04088C5B04088C5B0408A9
+:105B30008C5B04088C5B04088C5B0408E860040838
+:105B4000746004088C5B04088C5B04088C5B04089C
+:105B500068600408746004088C5B04088C5B0408AB
+:105B6000546004088C5B040814600408D45F0408C3
+:105B70007C5D0408705D04088C5B0408105D0408FB
+:105B80008C5B0408D05C04088C5B04088C5B040804
+:105B9000885C04083AC8278F26943F9806833F0004
+:105BA000040980D93A880BA03A8809B00069458079
+:105BB0001E0800103A88119006873F00170B80D806
+:105BC00026040010040980D93A880BA03A8809B04D
+:105BD000006945800B0380A00C1080101E7E03100E
+:105BE000170080D8172FC0DF172E00DF172DC0DD5C
+:105BF000172C80DD172B40DD172A00DD1729C0DCAC
+:105C0000172880DC172740DC172600DC0430C0DEB4
+:105C10003A2800F83A88210004F4FF10440000E715
+:105C2000A4020084C7FFBFE03A88211C04F4FF10DF
+:105C3000B00200191EF93F2004F8FF106816001981
+:105C400026763F20CC3F40291E47032826DB3F1005
+:105C5000050C80D8450800D84400C0044400400525
+:105C6000040CC0DD0657010014200063070080E02B
+:105C700006663F00070080E0440000E1A00AC01073
+:105C80001E58031804F4FF10B002C0193A883920D6
+:105C90003A881300265E3F38440000E7A402404AD9
+:105CA000C7FFBFE03A88D34804F4FF10B0020019E0
+:105CB0001EF93F2006563F00030080E0CC3F8010D5
+:105CC0001C2080101401006304E0BF10064F3F0049
+:105CD00044004001C40A8001070080E0064B3F00F9
+:105CE000170380D8170000140401C015030080E0DA
+:105CF00016EE02801503C0DDCC3F80101C20801002
+:105D000004E0BF1006413F0054000063070080E03C
+:105D1000063E3F00CC3FC0301C20C01804E0FF18F6
+:105D2000030080E01EF43F18CC3F80101C20801040
+:105D3000440040010408800104E0BF1006333F0026
+:105D4000CC3F40291E0E03283401C2000420DD1878
+:105D50001504C0D80C08C060262401181703C0D849
+:105D60001700C01C1701401D0402C0181503C0D83D
+:105D70004C00C060260200183AB0469D1E810218F1
+:105D80008400800006390000CC3F40291E0803280B
+:105D90000C0880601E7E0110170380D80C04C060C0
+:105DA0001700C014040180101E2201180C10C060DE
+:105DB00026E60218150380D8CCFFFF9C3A882B00FA
+:105DC0004400800006290000170380D8450800D849
+:105DD0001700C0150401401426CF02B8E0FFBF48E9
+:105DE0001E6E02103A880D483A880B003A8809B8AE
+:105DF000150300DA150200DB150140DA005D0880AA
+:105E0000170140DA170200DB170300DA26D8021068
+:105E10003AC8EB153A8827A80E0100A83A8827004F
+:105E2000150340DC06E7000014080063070080E06B
+:105E300006F63E001703C0D8040C8000850880D801
+:105E4000041E800034010201C50880D81700C01C60
+:105E500004018018150380D804209D20150480D8E3
+:105E60003A882B009400006384008000450800D825
+:105E7000E0FFFF483A881B001E180118C4DF7F04AA
+:105E80003AB0469D3A7062641ED201181E8A0248DA
+:105E90001EBF00104C004065263102A8040C800093
+:105EA000C51580D8C415C0DD3A8827480E01404D7D
+:105EB0003A8827A8CC3F406B1C20406B04E07F6BE6
+:105EC000260100684400C09C8C00408B26010068BD
+:105ED0008400C09C0C21008B170B80D8170A00D9B6
+:105EE0001E0200603AC8C78416BCC100470880D9AA
+:105EF000440040210402C040260F0030440880D9ED
+:105F0000440080101500804144008001150180414B
+:105F1000150B80D8150A40D9080280291EE10130EE
+:105F20008400C021040480413A8809283A88111865
+:105F30003A880B383A880730260D0068840800D963
+:105F4000840080101500004184000001150100410B
+:105F5000150B80D8150A40D9080200291EE201203D
+:105F60003A8809283A881118440040290402C018C8
+:105F700018200063261601603AC8534D16484102A6
+:105F80003A8885A81500C04515014045150B80D8F5
+:105F9000150A40D910020029267001200C01408CFE
+:105FA000260200883AC8E384160940040E01C08422
+:105FB0003A8821981700C0D83A88071C1500C0D825
+:105FC0001E7E0110150A00D83A88119006693E001D
+:105FD0007401C201500440894440EE39170A00D9C7
+:105FE00004044005260500280619000004FC7F8CE7
+:105FF000480440890402C0182615002844000021E6
+:10600000040480101500C0191501401D150B80D81F
+:10601000150A00D90802402126F43F28040980D936
+:106020003A880BA03A8809B01501C0D900694580AB
+:106030001EE83E1004FC7F8C48044089170B80D872
+:10604000170A00D93A8807901701C0D91EEB3F28DC
+:10605000440000213A884514150A00D91500C019DA
+:106060001501401C150B80D8100200211ECF3F20C7
+:10607000040980D93A880BA03A8809B000694580A4
+:106080001ED43E10170B80D806C83F00CC3F4029D5
+:106090001E4B02280C0880601EAF0010170380D82A
+:1060A0000C04C0601700C014040180101E6E00189C
+:1060B0000C10C06026210218150380D8CCFFFF9C6D
+:1060C0003A882B003A88050006683F00CC3F4029FB
+:1060D0001E390228170300D90C0880600401C02073
+:1060E0001EA101100C0480601EBE01100C10006384
+:1060F00026BC0160170380D81503C0D81700C0D88C
+:10610000170080100D00C010061A3E00070080E046
+:10611000181BC01026EC011814040063063B3E0057
+:1061200014100063070080E006383E00CC3F402991
+:106130001E1D02280C0880601E8E0010170380D8D8
+:106140000C04C060040180101E5400180C10C060C4
+:10615000265200181703C0D8150380D80F00C01CA2
+:10616000FAD72B983A8805A816520010D8FFBF48D6
+:10617000430840DB268D0010C4DFFF003AB0449D89
+:106180003A70D8601E8900101E8B00483A88236040
+:106190003A8813003A882B003A882F9006423F0035
+:1061A0001703C0D8450800D84400C0041700801861
+:1061B0000401C0181503C0D8050C80D84400400560
+:1061C000040CC0DD3A8823603A881300063E3F0085
+:1061D000CC3F40291EEC01283401C200041BDD180D
+:1061E0001504C0D80C08C0601EDC3E18170300D987
+:1061F0000C04C0601700C02404010021150300D95D
+:106200001E4801180C10C06026460118CCFFFF9CE8
+:106210003A882B0006D63E00CC3F40291EDC0128E0
+:106220000C088060140400631E590010170380D806
+:10623000040180101703C0D83A882B00150380D8BA
+:106240001700C01C4400800006083F00CC3F4029D6
+:106250001ED101280C088060140400631E3E00104B
+:10626000170380D8040180101703C0D83A882B0088
+:10627000150380D81700C01C3A88050006FB3E00B5
+:10628000CC3F40291EC601280C088060140400631E
+:106290001E380010170380D8040180101703C0D8DF
+:1062A0001700C01C150380D8FAD72B983A8805A888
+:1062B0000EAE3F103AC8E7043AC004983AC86B05DE
+:1062C0003AC8ABA8440B8000450880D8E0FFFF48DF
+:1062D000440B40034400800026E83E186000C010D4
+:1062E0001E320018A00080101EA400103A880790EB
+:1062F000060100003A8807B8FAD008987A970AA8E9
+:10630000FAD02AA8CC01C09C040C80983AB0262967
+:10631000C5FFBF183AB0489DC4FFFF1D1EF53F20C2
+:106320004C00006126A20020CC3F80101C20801071
+:1063300004E0BF10180C8010269D001084FFFF1889
+:10634000040C8000C5FFBFB83AC8EB903A882360C0
+:106350003A882F1806D43E001703C0D83A880500A3
+:106360001700C01C1701401D0402C0181503C0D837
+:1063700006BE3E001703C0D8170180181700C01CC6
+:106380000402C0181503C0D83A882B1006763F00C7
+:106390001703C0D8440080001700C01C1701401D1F
+:1063A0000402C0181503C0D806B03E001E1301A891
+:1063B000A80280981E110110040CC09CC515C0DCF9
+:1063C0003A88236044004005C415C0DD06B63E008F
+:1063D0003AC8D9840EE83E03500480617401C201BA
+:1063E0001E790130443CEE390404400306040000E9
+:1063F00004FC3F634804C06004020042261A0018EF
+:1064000044000021040480101500C04115014043E0
+:10641000150B80D8150A00D90802C02026F43F18B1
+:10642000040980D93A880BA03A8809B01505C0D96B
+:10643000150200DB150140DA006945801EE53D10BC
+:10644000170200DB170B80D8170A00D904FC3F6342
+:106450004804C0603A8811901705C0D9040440036D
+:10646000170140DA1EE63F18440000210402804173
+:106470003A8805131500C04115010043150B80D85B
+:10648000150A00D90802C0201E1601183AC8534D3B
+:10649000440040210402C0303A8811300EB87E0218
+:1064A000500480497401C2011E2C0130443CEE3975
+:1064B000040400030604000004FC7F4A4804C048AA
+:1064C0000402004226180018440000210404801031
+:1064D0001500C04115010043150B80D8150A00D9DD
+:1064E0000802C02026F43F18040980D93A880BA07E
+:1064F0003A8809B01502C0D9150140DA0069458013
+:106500001EB43D10170140DA170B80D8170A00D9C6
+:1065100004FC7F4A4804C0483A8811901702C0D949
+:10652000040400031EE83F18440040210402004117
+:106530003A8845121500C04115014042150B80D81C
+:10654000150A40D90802C0281E78001844004029C6
+:106550000402C0203A88112006893E00040980D92F
+:106560003A880BA03A8809B0006945801E993D1011
+:10657000170B80D83A88079006883E003A882F90FB
+:10658000170400D9CC0380983A9706A83A8885204A
+:106590003AD12698030080103AD12AA8C4FFFFBD43
+:1065A0003AB0E61C050080B83AB0449D1EF43F1096
+:1065B0003AC8EB953A882360063B3E00040980D92F
+:1065C0003A880BA03A8809B000694580267D3E10C4
+:1065D00006803D003A88198806403F007401C201D8
+:1065E000500440194440EE39040480032605002875
+:1065F0000622000004FCFF1848044019040200426F
+:10660000261E002844000021040480101500C0410B
+:1066100015018043150B80D8150A00D908024021C6
+:1066200026F43F28040980D93A880BA03A8809B09B
+:106630001507C0D91506C0D8150540DA150200DBCC
+:10664000150140DB006945801E623D101706C0D869
+:10665000170B80D8170A00D904FCFF18480440190A
+:106660003A8811901707C0D904048003170540DA4F
+:10667000170200DB170140DB1EE23F284400002127
+:106680003A88C5101501C0401500C041150B80D8CF
+:10669000150A00D90802C0201E7500180402004225
+:1066A00006123E00040980D93A880BA03A8809B046
+:1066B000150540DA150200DB150140DB0069458055
+:1066C0001E443D10170A00D9170B80D80418C0D8F3
+:1066D000440040213A881190170540DA170200DB88
+:1066E000170140DB06143E00040980D93A880BA04C
+:1066F0003A8809B0150240DA150100DB00694580CF
+:106700001E343D10170A00D9170B80D80418C0D8C2
+:10671000440040213A881190170240DA170100DB4B
+:1067200006133E003A882B0006913D00040980D9EB
+:106730003A880BA03A8809B0006945801E253D10B3
+:10674000170A00D9170B80D80418C0D8440040217C
+:106750003A881190060A3E003A8823E006A33C00DE
+:106760003A882F9006D03D00170040D917008020AE
+:106770001503C0D8FAD709281500401115010011DA
+:10678000067C3C00040CC000C50880D88508C0D831
+:10679000940000638400800006B43D003A8809B884
+:1067A000150200DA150100DBC0DA02803A882B10EE
+:1067B0003A882710150340DC170100DB170200DAC6
+:1067C00006803E0004104001C0DD0780150080A057
+:1067D000150480A0268F001004108000150580A0ED
+:1067E000065D3C00170380D8170080101503C0D841
+:1067F0001700C0D81500C010065E3C003A882F90E4
+:10680000060200003A8827103A882B183A8809981F
+:106810003A880BA8840280013A880F00150640DBF5
+:10682000150500DA150240DA150100DB009C0C802A
+:10683000040C8010C4FFFFBD3A8809983A880BA861
+:10684000050080B8840280013A880F0080420C80E5
+:10685000170100DB170240DA170500DA170640DBE4
+:106860001EE83FA8A802C09C1EE63F9806503F00C5
+:10687000040980D93A880BA03A8809B0150540DA96
+:10688000150200DB150140DB006945801ED13C107C
+:10689000170B80D8170A00D93A881190170540DAEB
+:1068A000170200DB170140DB06903D003AC82104C7
+:1068B0001503C0DD06013D006000C0103A8819884C
+:1068C00026883E1806BC3E00430080E014080063A2
+:1068D000440000E7CC3F80101C20801004E0BF1073
+:1068E000064A3C00040980D93A880BA03A8809B0CE
+:1068F000150140DA006945801EB63C10170A00D920
+:10690000170B80D80418C0D8440040213A88119051
+:10691000170140DA06983D00F00180483A882B487C
+:106920001E010010840140053401C2053A8827A8E1
+:10693000150340DC0425DDBD06223E00150380D88A
+:106940003A882B003A88050006483D00150380D898
+:106950003A882B004400800006443D003A8809181C
+:10696000443CEE3906F23E00450880D906B73C00AB
+:106970003A882748150340DC3A882B4806113E0028
+:10698000450880D906F03C00450880D906123E0033
+:10699000450880D906223E00450880D9062D3E00D4
+:1069A000450880D906383E00450880D906E13D00FB
+:1069B000450880D906F63C00450880D906C53D004B
+:1069C000450880D906B33D003A880D183A88092851
+:1069D000443CEE3906A63E00C4FFBF00150080D837
+:1069E000067F3C00170380D8170040120401C01531
+:1069F0000E010048C4FF7F02430080E01503C0DDA4
+:106A00003A883920CC3F80101C20801004E0BF1051
+:106A100006FE3B0004038000150080B0C4FFBF00E9
+:106A2000150080D8066E3C0041E4028004FDFFDEC4
+:106A3000150200DF040200DF15FE3FE1454B20D0C8
+:106A400017FEBFE015FFBFE017FFBFE026020010F2
+:106A500070F02A0006010000B0F02A0006FF3F0097
+:106A60005175657279696E672041525020666F7268
+:106A70002025642E25642E25642E2564202E2E2E9E
+:106A80000A00000041525020656E74727920636FD5
+:106A9000756C64206E6F7420626520666F756E641D
+:106AA0002C2070696E67696E67210000436F756CFA
+:106AB00064206E6F74207265736F6C7665204D4133
+:106AC00043212054686520726573756C742062657B
+:106AD0006C6F772069732072616E646F6D210000A6
+:106AE00050656572204D414320697320253032780E
+:106AF0002025303278202530327820253032782019
+:106B00002530327820253032780A0000434F4D4D31
+:106B1000414E445F50494E4700000000434F4D4DE9
+:106B2000414E445F44454255475F4C45445F4F46A4
+:106B300046000000434F4D4D414E445F4445425591
+:106B4000475F4C45445F4F4E00000000434F4D4DA2
+:106B5000414E445F4C4544535F44495341424C4588
+:106B600000000000434F4D4D414E445F4C4544539F
+:106B70005F454E41424C4500434F4D4D414E445FB1
+:106B8000545249474745525F44495341424C45009E
+:106B9000434F4D4D414E445F545249474745525F24
+:106BA000454E41424C450000434F4D4D414E445FE0
+:106BB000545249474745525F5345545F534C4156E1
+:106BC00045000000434F4D4D414E445F54524947EC
+:106BD0004745525F5345545F4D4153544552000061
+:106BE000434F4D4D414E445F545249474745525FD4
+:106BF0005345545F504552494F443A2025640A009A
+:106C0000434F4D4D414E445F545249474745525FB3
+:106C10005345545F54494E543A2025640A000000FD
+:106C2000434F4D4D414E445F5345545F4741494E9C
+:106C30003A2025640A000000434F4D4D414E445F09
+:106C4000545249474745525F5345545F4D41535451
+:106C500045525F44454C41593A2025640A000000E2
+:106C6000434F4D4D414E445F545249474745525F53
+:106C70005345545F534C4156455F44454C41593A46
+:106C80002025640A00000000434F4D4D414E445FF3
+:106C90004441515F44495341424C4500434F4D4D9F
+:106CA000414E445F4441515F454E41424C450000D6
+:106CB000434F4D4D414E445F4441515F5245534512
+:106CC000545F434F554E544552530000434F4D4D72
+:106CD000414E445F4441515F464C5553485F4441E7
+:106CE00054410000434F4D4D414E445F4441515F7C
+:106CF000434F4E4649475F5045455200434F4D4D27
+:106D0000414E445F534C4F574354524C5F534E4196
+:106D10005053484F54000000434F4D4D414E445F87
+:106D20005345545F434C55535445525F5448524564
+:106D300053484F4C443A2025640A0000434F4D4DC0
+:106D4000414E445F5345545F434C55535445525F45
+:106D500053495A453A2025640A000000434F4D4DDF
+:106D6000414E445F5345545F43414C494252415464
+:106D7000494F4E5F464143544F52204368616E6E07
+:106D8000656C49502564203A2025640A0000000003
+:106D9000434F4D4D414E445F5345545F43414C4931
+:106DA00042524154494F4E5F464143544F52206C2A
+:106DB000656E6774683A2025640A0000436F6E743C
+:106DC000726F6C2074687265616400003A3A3A2010
+:106DD000436F6E74726F6C207461736B2073746197
+:106DE00072746564203A3A3A20000000496E697472
+:106DF000696174652043616C6962726174696F6E68
+:106E000020466163746F72203120746F20333230FA
+:106E10002066726F6D206368616E6E656C312074E0
+:106E20006F206368616E6E656C3332302000000045
+:106E30000A536F636B6574205365727665722073B5
+:106E400074617274696E672075700000496E7075A8
+:106E5000742073746174653A2030782530386C780A
+:106E60000A000000444843502064697361626C6505
+:106E7000642E00005374617469632049502041649A
+:106E800064726573732069732025642E25642E2532
+:106E9000642E25640A000000506C656173652065EE
+:106EA0006E74657220796F757220392D6469676917
+:106EB000742073657269616C206E756D6265722EE7
+:106EC0002054686973206973207072696E746564F8
+:106ED000206F6E20612000006C6162656C20756E11
+:106EE00064657220796F7572204E696F73206465D6
+:106EF000762E20626F6172642E2054686520666968
+:106F0000727374203320646967697473206F66201C
+:106F100074686520000000006C6162656C2061721D
+:106F2000652041534A20616E642074686520736552
+:106F30007269616C206E756D62657220666F6C6C33
+:106F40006F777320746869732E0A202D2D3E000020
+:106F500053657269616C206E756D626572206F6E2B
+:106F60006C7920636F6E7461696E73206465636908
+:106F70006D616C2064696769747320616E64206957
+:106F800073206E6F6E2D7A65726F000043616E27FD
+:106F900074207265616420746865204D41432061EE
+:106FA0006464726573732066726F6D20796F757299
+:106FB00020626F6172642028746869732070726F38
+:106FC0006261626C79206D65616E730074686174D2
+:106FD00020796F757220666C617368207761732009
+:106FE000657261736564292E2057652077696C6C22
+:106FF0002061737369676E20796F752061204D4140
+:1070000043206164647265737320616E64000000E4
+:10701000737461746963206E6574776F726B20732B
+:10702000657474696E67730A000000002F646576EA
+:107030002F6578745F666C6173685F61766C5F6DF5
+:10704000656D00000A43616E2774207265616420DB
+:10705000746865204D4143206164647265737320D8
+:1070600066726F6D20796F757220626F6172642E27
+:107070002057652077696C6C2061737369676E2097
+:10708000796F750061204D414320616464726573BE
+:10709000732E0A00596F75722045746865726E65AB
+:1070A00074204D4143206164647265737320697379
+:1070B00020253032783A253032783A253032783A05
+:1070C000253032783A253032783A253032780A0045
+:1070D000202A2A2A20507265636F6E66696775726E
+:1070E000696E672073656E736F72206D6F64756C67
+:1070F000652E2E2E20000000736F636B6574207365
+:107100006572766572206C697374656E65720000D5
+:107110005B73735F68616E646C655F616363657008
+:10712000745D20636C6F73696E67206F6C6420639D
+:107130006F6E6E656374696F6E0000005B73735FE2
+:1071400068616E646C655F6163636570745D206126
+:107150006363657074656420636F6E6E65637469E4
+:107160006F6E20726571756573742066726F6D2025
+:1071700025730A005B7373735F7461736B5D2053D7
+:10718000696D706C6520536F636B65742053657215
+:10719000766572206C697374656E696E67206F6EB8
+:1071A00020706F72742025640A0000005B657468AB
+:1071B00065726E65745F77726974655D20636C6F6C
+:1071C00073696E6720636F6E6E656374696F6E209E
+:1071D00064756520746F206572726F720000000024
+:1071E0005B65746865726E65745F726561645D206D
+:1071F000636C6F73696E6720636F6E6E656374692D
+:107200006F6E2064756520746F206572726F7200F6
+:107210002F6465762F6D7367646D615F74785F634B
+:10722000737200002F6465762F6D7367646D615F04
+:1072300072785F6373720000202A2A2A20536574D3
+:1072400074696E67207570205544502067656E65BF
+:107250007261746F722E2E2E2000000024242424CC
+:10726000205245434F4E4649475552494E472046C6
+:107270005047412121212024242424002A2A2A2085
+:1072800044495341424C454421202A2A2A000020E7
+:1072900020202020202020202828282828202020C6
+:1072A0002020202020202020202020202020208876
+:1072B00010101010101010101010101010101004DA
+:1072C000040404040404040404101010101010102A
+:1072D000414141414141010101010101010101011E
+:1072E0000101010101010101010110101010101034
+:1072F00042424242424202020202020202020202EE
+:107300000202020202020202020210101010200009
+:10731000000000000000000000000000000000006D
+:10732000000000000000000000000000000000005D
+:10733000000000000000000000000000000000004D
+:10734000000000000000000000000000000000003D
+:10735000000000000000000000000000000000002D
+:10736000000000000000000000000000000000001D
+:10737000000000000000000000000000000000000D
+:1073800000000000000000000000000000000000FD
+:1073900000000000000000000000000000000000ED
+:1073A00000000000000000000000000000000000DD
+:1073B00000000000000000000000000000000000CD
+:1073C00000000000000000000000000000000000BD
+:1073D00000000000000000000000000000000000AD
+:1073E000000000000000000000000000000000009D
+:1073F000000000000000000000000000000000008D
+:10740000000000000000000000000000000000205C
+:107410002020202020202020282828282820202044
+:1074200020202020202020202020202020202088F4
+:107430001010101010101010101010101010100458
+:1074400004040404040404040410101010101010A8
+:10745000414141414141010101010101010101019C
+:1074600001010101010101010101101010101010B2
+:10747000424242424242020202020202020202026C
+:107480000202020202020202020210101010200088
+:1074900000000000000000000000000000000000EC
+:1074A00000000000000000000000000000000000DC
+:1074B00000000000000000000000000000000000CC
+:1074C00000000000000000000000000000000000BC
+:1074D00000000000000000000000000000000000AC
+:1074E000000000000000000000000000000000009C
+:1074F000000000000000000000000000000000008C
+:10750000000000000000000000000000000000007B
+:107510000A000000494E4600696E66004E414E006A
+:107520006E616E003031323334353637383941428E
+:10753000434445460000000030313233343536379D
+:10754000383961626364656600000000286E756CFE
+:107550006C29000030003030303030303030303086
+:1075600030303030303020202020202020202020BB
+:1075700020202020202000004E614E00496E6669C8
+:107580006E69747900000000050000001900000019
+:107590007D000000BC89D897B2D29C3C33A7A8D507
+:1075A00023F649393DA7F444FD0FA5329D978CCFB2
+:1075B00008BA5B25436FAC642806C80A0080E03730
+:1075C00079C34143176E05B5B5B89346F5F93FE960
+:1075D000034F384D321D30F94877825A3CBF737FD4
+:1075E000DD4F1575000000000000F03F00000000B6
+:1075F000000024400000000000005940000000008E
+:1076000000408F40000000000088C34000000000E0
+:10761000006AF8400000000080842E410000000055
+:10762000D01263410000000084D7974100000000A1
+:1076300065CDCD41000000205FA00242000000E8BF
+:1076400076483742000000A2941A6D42000040E5DF
+:107650009C30A2420000901EC4BCD64200003426DA
+:10766000F56B0C430080E03779C3414300A0D88517
+:107670005734764300C84E676DC1AB43003D9160FF
+:10768000E458E143408CB5781DAF154450EFE2D685
+:10769000E41A4B4492D54D06CFF08044F64AE1C738
+:1076A000022DB544B49DD9794378EA443030303066
+:1076B000303030303030303030303030202020200A
+:1076C00020202020202020202020202043000000F7
+:1076D000504F5349580000002E00000000010202E4
+:1076E000030303030404040404040404050505055A
+:1076F0000505050505050505050505050606060636
+:107700000606060606060606060606060606060619
+:107710000606060606060606060606060707070705
+:1077200007070707070707070707070707070707E9
+:1077300007070707070707070707070707070707D9
+:1077400007070707070707070707070707070707C9
+:1077500007070707070707070707070708080808B5
+:107760000808080808080808080808080808080899
+:107770000808080808080808080808080808080889
+:107780000808080808080808080808080808080879
+:107790000808080808080808080808080808080869
+:1077A0000808080808080808080808080808080859
+:1077B0000808080808080808080808080808080849
+:1077C0000808080808080808080808080808080839
+:1077D0000808080808080808080808082F646576DB
+:1077E0002F64656275675F75617274000000010047
+:1077F000020001000300010002000100040001007A
+:107800000200010003000100020001000500010068
+:107810000200010003000100020001000400010059
+:107820000200010003000100020001000600010047
+:107830000200010003000100020001000400010039
+:107840000200010003000100020001000500010028
+:107850000200010003000100020001000400010019
+:107860000200010003000100020001000700010006
+:1078700002000100030001000200010004000100F9
+:1078800002000100030001000200010005000100E8
+:1078900002000100030001000200010004000100D9
+:1078A00002000100030001000200010006000100C7
+:1078B00002000100030001000200010004000100B9
+:1078C00002000100030001000200010005000100A8
+:1078D0000200010003000100020001000400010099
+:1078E00002000100030001000200010075432F4F58
+:1078F000532D49492049646C650000002F6465766A
+:107900002F64656275675F75617274002F646576B8
+:107910002F6574685F747365000000002F646576DE
+:107920002F6578745F666C6173685F61766C5F6DFC
+:10793000656D00002F6465762F6D7367646D615F00
+:1079400072785F6373720000416C69676E656420D2
+:107950004163636573736573000000002F6465768F
+:107960002F6D7367646D615F74785F63737200007D
+:107970002F6465762F6F6E636869705F666C6173E4
+:10798000685F6461746100005741524E494E472060
+:107990003A205458204D5347444D412054696D6559
+:1079A0006F7574005741524E494E47203A616C74CE
+:1079B0005F6D7367646D615F7374616E646172643F
+:1079C0005F64657363726970746F725F73796E63FD
+:1079D0005F7472616E73666572204572726F722099
+:1079E000636F646520307825780A00005741524E55
+:1079F000494E47203A20504859204F554920307869
+:107A0000253036782C20504859204D6F64656C2005
+:107A10004E756D6265722030782530327820616C49
+:107A2000726561647920657869737420696E20508D
+:107A300048592070726F66696C650A00496E206350
+:107A4000617365206F662073616D65205048592011
+:107A50004F554920616E6420504859204D6F646530
+:107A60006C204E756D62657220696E2070726F6653
+:107A7000696C652C20666972737420616464656446
+:107A8000205048592073657474696E672077696C5B
+:107A90006C20626520757365640000004552524F8A
+:107AA000522020203A20556E61626C6520746F2050
+:107AB000616C6C6F63617465206D656D6F727920A8
+:107AC000666F7220707068795F70726F66696C653E
+:107AD0005B25645D0A0000004552524F5220202071
+:107AE0003A20496E76616C6964206E756D626572CC
+:107AF000206F66206368616E6E656C2073706563CD
+:107B000069666965642100004552524F5220202069
+:107B10003A204E756D626572206F66205453452081
+:107B200053797374656D206164646564206578635E
+:107B3000656564207468652073697A65206F6620C6
+:107B400061727261792100004552524F522020200B
+:107B50003A2053697A65206F6620617272617920DC
+:107B60003D2025642C204E756D626572206F662065
+:107B70005453452053797374656D203D2025640A64
+:107B8000000000004552524F522020203A204D4123
+:107B9000432073797374656D2073747275637475A3
+:107BA0007265203D3D204E554C4C00004552524FD1
+:107BB000522020203A20506C6561736520706173FB
+:107BC0007320696E20636F727265637420706F69D1
+:107BD0006E74657220746F20616C745F7473655F7E
+:107BE00073797374656D5F6164645F737973282959
+:107BF000000000004552524F522020203A204D53A1
+:107C000047444D412073797374656D2073747275A8
+:107C10006374757265203D3D204E554C4C0000004C
+:107C20004552524F522020203A20506C65617365B6
+:107C3000207061737320696E20636F727265637464
+:107C400020706F696E74657220746F20616C745F50
+:107C50007473655F73797374656D5F6164645F737A
+:107C60007973282920666F72207473655F6D616374
+:107C70005F6465766963655B25645D0A00000000EA
+:107C80004552524F522020203A20556E61626C6559
+:107C900020746F20616C6C6F63617465206D656D1D
+:107CA0006F727920666F72207473655F6D61635FB8
+:107CB0006465766963655B25645D2E7473655F6DCD
+:107CC0007367646D615F74780A0000004552524F1B
+:107CD000522020203A20556E61626C6520746F201E
+:107CE000616C6C6F63617465206D656D6F72792076
+:107CF000666F72207473655F6D61635F646576693A
+:107D000063655B25645D2E7473655F6D7367646D79
+:107D1000615F72780A0000004552524F52202020C5
+:107D20003A20506C65617365207061737320696ED1
+:107D300020636F727265637420706F696E74657210
+:107D400020746F20616C745F7473655F7379735F07
+:107D5000656E61626C655F6D64696F5F73686172A7
+:107D6000696E6728290000004552524F522020209A
+:107D70003A204D44494F2073686172696E672073E1
+:107D80007570706F727465642062792064656661D5
+:107D9000756C7420666F72204D756C74692D636804
+:107DA000616E6E656C204D41430000004552524F9C
+:107DB000522020203A20446F206E6F7420696E6339
+:107DC0006C756465204D756C74692D6368616E6EA9
+:107DD000656C204D414320696E20746865204D41DB
+:107DE00043204C697374000031300000556E6B6E97
+:107DF0006F776E00313030003130303000000000DD
+:107E000046756C6C0000000048616C660000000064
+:107E10004552524F522020203A205B6765745048EB
+:107E20005953706565645D20706D6163206E6F7479
+:107E300020666F756E642066726F6D206C69737456
+:107E4000206F6620706D61635F696E666F5B5D2198
+:107E5000205370656564203D202573204D6270734A
+:107E60002C204475706C6578203D2025730A000035
+:107E70004552524F522020203A205B67657450488B
+:107E80005953706565645D20506C6561736520644D
+:107E90006566696E65207473655F6D61635F6465B7
+:107EA000766963655B5D20636F72726563746C797C
+:107EB000000000005741524E494E47203A2050489A
+:107EC000595B25642E25645D202D204D44494F20AB
+:107ED0006E6F7420656E61626C6564212052756EF0
+:107EE0006E696E67207573657220636F6E66696771
+:107EF00075726174696F6E2E2E2E0A005741524EB4
+:107F0000494E47203A204D41432047726F75705BC0
+:107F100025645D202D204D44494F206E6F742065EF
+:107F20006E61626C656421205370656564203D203C
+:107F300025732C204475706C6578203D2025730ACC
+:107F4000000000004552524F522020203A20504855
+:107F5000595B25642E25645D202D204E6F205048EE
+:107F60005920636F6E6E656374656421205370657C
+:107F70006564203D2025732C204475706C65782045
+:107F80003D2025730A0000005741524E494E4720BC
+:107F90003A205048595B25642E25645D202D2041F0
+:107FA00075746F2D4E65676F74696174696F6E20AB
+:107FB0006E6F7420636F6D706C65746564212053FF
+:107FC00070656564203D2025732C204475706C65B8
+:107FD00078203D2025730A005741524E494E4720D4
+:107FE0003A205048595B25642E25645D202D205091
+:107FF0004859206E6F7420666F756E6420696E201C
+:108000005048592070726F66696C650A0000000064
+:108010005741524E494E47203A205048595B2564FB
+:108020002E25645D202D20496E76616C6964207375
+:108030007065656420726561642066726F6D2050A2
+:1080400048590A005741524E494E47203A2050485D
+:10805000595B25642E25645D202D205048592053FE
+:108060007065636966696320537461747573207207
+:108070006567697374657220696E666F726D61748D
+:10808000696F6E206E6F742070726F7669646564BC
+:1080900020696E2070726F66696C650A00000000CE
+:1080A000494E464F202020203A205048595B2564F5
+:1080B0002E25645D202D205370656564203D2025AC
+:1080C000732C204475706C6578203D2025730A0060
+:1080D0004E6174696F6E616C2044503833383438A7
+:1080E000430000000000000000000000000000004D
+:1080F0000000000000000000000000000000000080
+:10810000000000000000000000000000000000006F
+:10811000000000000000000000000000000000005F
+:108120001700080009000000000000000000000027
+:10813000CCC80108496E74656C205045463730370D
+:1081400031000000000000000000000000000000FE
+:10815000000000000000000000000000000000001F
+:10816000000000000000000000000000000000000F
+:1081700000000000000000000000000000000000FF
+:1081800000000000695935000001000000000000F7
+:1081900044C90108A0C901084C697374206F6620A6
+:1081A0005048592070726F66696C657320737570E2
+:1081B000706F727465642028546F74616C207072E3
+:1081C0006F66696C6573203D202564292E2E2E0A6A
+:1081D0000000000050726F66696C65204E6F2E259E
+:1081E00032642020203A0A00504859204E616D65C3
+:1081F00020202020202020203A2025730A00000083
+:10820000504859204F554920202020202020202050
+:108210003A203078253036780A000000504859203E
+:108220004D6F64656C204E756D2E20203A2030789D
+:10823000253032780A000000504859205265762EC9
+:10824000204E756D2E2020203A203078253032784F
+:108250000A00000053746174757320526567697376
+:10826000746572203A203078253032780A00000098
+:1082700053706565642042697420202020202020EE
+:108280003A2025640A0000004475706C657820422D
+:1082900069742020202020203A2025640A00000054
+:1082A0004C696E6B20426974202020202020202001
+:1082B0003A2025640A0A0000494E464F202020201B
+:1082C0003A20545345204D414320256420666F7564
+:1082D0006E64206174206164647265737320307809
+:1082E000253038780A0000004552524F5220202095
+:1082F0003A20556E61626C6520746F20616C6C6F02
+:1083000063617465206D656D6F727920666F722090
+:108310004D41432047726F75705B25645D0A000014
+:10832000494E464F202020203A204D756C7469201C
+:108330004368616E6E656C20202020202020202064
+:108340002020203D2059657300000000494E464F13
+:10835000202020203A204E756D626572206F6620C5
+:108360006368616E6E656C20202020202020203DF7
+:108370002025640A00000000494E464F202020209E
+:108380003A204D44494F2053686172656420202093
+:1083900020202020202020202020203D20596573EF
+:1083A00000000000494E464F202020203A204D7505
+:1083B0006C7469204368616E6E656C2020202020FB
+:1083C000202020202020203D204E6F00494E464F87
+:1083D000202020203A204E756D626572206F662045
+:1083E0004D4143205368617265204D44494F203D03
+:1083F0002025640A00000000494E464F202020201E
+:108400003A204D44494F2053686172656420202012
+:1084100020202020202020202020203D204E6F00E2
+:108420004552524F522020203A20556E61626C65B1
+:1084300020746F20616C6C6F63617465206D656D75
+:108440006F727920666F72204D41432047726F75BD
+:10845000705B25645D2D3E706D61635F696E666F54
+:108460005B25645D0A0000004552524F52202020D7
+:108470003A207473655F6D61635F646576696365F7
+:108480005B25645D20646F6573206E6F7420646586
+:1084900066696E656420636F72726563746C7921BE
+:1084A0000A000000494E464F202020203A204D412E
+:1084B0004320253264204164647265737320202058
+:1084C00020202020202020203D20307825303878A2
+:1084D0000A000000494E464F202020203A204D41FE
+:1084E000432025326420446576696365202020207E
+:1084F00020202020202020203D207473655F6D61A6
+:10850000635F6465766963655B25645D0A000000EE
+:1085100031303030204D62707320536D616C6C20AF
+:108520004D414300494E464F202020203A204D41E6
+:10853000432025326420547970652020202020209B
+:1085400020202020202020203D2025730A0000002C
+:1085500031302F313030204D62707320536D616C9B
+:108560006C204D414300000031302F3130302F312D
+:108570003030302045746865726E6574204D41431B
+:1085800000000000596573004E6F0000494E464FD1
+:10859000202020203A205043532025326420456E6D
+:1085A00061626C65202020202020202020202020B7
+:1085B0003D2025730A000000494E464F2020202010
+:1085C0003A20504353202532642053474D494920D7
+:1085D000456E61626C652020202020203D2025739F
+:1085E0000A000000494E464F202020203A204D41ED
+:1085F0004320547970652020202020202020202036
+:10860000202020202020203D2025730A000000008B
+:10861000494E464F202020203A2050435320456E9B
+:1086200061626C6520202020202020202020202036
+:108630002020203D2025730A00000000494E464FAF
+:10864000202020203A205043532053474D494920B1
+:10865000456E61626C652020202020202020203D76
+:108660002025730A00000000494E464F202020209C
+:108670003A204368616E6E656C2025326420416447
+:108680006472657373202020202020203D203078E4
+:10869000253038780A000000494E464F202020201F
+:1086A0003A204368616E6E656C2025326420446513
+:1086B0007669636520202020202020203D207473CF
+:1086C000655F6D61635F6465766963655B25645DA5
+:1086D0000A000000494E464F202020203A204D41FC
+:1086E0004320416464726573732020202020202081
+:1086F000202020202020203D203078253038780A86
+:1087000000000000494E464F202020203A204D41D5
+:1087100043204465766963652020202020202020A6
+:10872000202020202020203D207473655F6D616330
+:108730005F6465766963655B25645D0A000000001F
+:108740004552524F522020203A20556E61626C658E
+:1087500020746F20616C6C6F63617465206D656D52
+:108760006F727920666F72207068795F696E666FCC
+:108770005B25642E25645D0A00000000494E464FCB
+:10878000202020203A2050485920257320666F75FC
+:108790006E6420617420504859206164647265736E
+:1087A0007320307825303278206F66204D41432089
+:1087B00047726F75705B25645D0A00005741524E29
+:1087C000494E47203A20556E6B6E6F776E205048A9
+:1087D0005920666F756E642061742050485920617D
+:1087E00064647265737320307825303278206F6648
+:1087F000204D41432047726F75705B25645D0A0010
+:108800005741524E494E47203A20506C656173657E
+:10881000206164642050485920696E666F726D61F2
+:1088200074696F6E20746F205048592070726F66A3
+:10883000696C6500494E464F202020203A20504860
+:1088400059204F5549202020202020202020202062
+:1088500020203D20203078253036780A00000000A6
+:10886000494E464F202020203A20504859204D6F35
+:1088700064656C204E756D626572202020203D205D
+:10888000203078253032780A00000000494E464FEB
+:10889000202020203A20504859205265766973697B
+:1088A0006F6E204E756D626572203D2020307825F8
+:1088B0003031780A00000000494E464F2020202029
+:1088C0003A204170706C79696E67206164646974E4
+:1088D000696F6E616C2050485920636F6E666967DE
+:1088E00075726174696F6E206F662025730A0000CF
+:1088F000494E464F202020203A204170706C796903
+:108900006E67206164646974696F6E616C20757351
+:1089100065722050485920636F6E66696775726191
+:1089200074696F6E000000004552524F52202020A3
+:108930003A204D41432047726F75705B25645D207E
+:108940002D204E6F2050485920636F6E6E65637402
+:108950006564210A000000005741524E494E4720ED
+:108960003A204D41432047726F75705B25645D204E
+:108970002D204E756D626572206F6620504859201B
+:10898000636F6E6E6563746564206973206E6F74C7
+:1089900020657175616C20746F20746865206E7538
+:1089A0006D626572206F66206368616E6E656C2C07
+:1089B000204E756D626572206F6620504859203ACE
+:1089C0002025642C204368616E6E656C203A20255A
+:1089D000640A0000494E464F202020203A2050488B
+:1089E000595B25642E25645D202D204578706C69C7
+:1089F0006369746C79206D617070656420746F2098
+:108A00007473655F6D61635F6465766963655B253B
+:108A1000645D0A00494E464F202020203A205048ED
+:108A2000595B25642E25645D202D204175746F6D82
+:108A300061746963616C6C79206D6170706564202C
+:108A4000746F207473655F6D61635F6465766963DD
+:108A5000655B25645D0A00005741524E494E472030
+:108A60003A205048595B25642E585D202D204D61D9
+:108A70007070696E67206F662050485920746F20AF
+:108A80004D4143206661696C656421204D616B65D1
+:108A900020737572652074686520504859206164A0
+:108AA000647265737320697320646566696E6564BA
+:108AB00020636F72726563746C7920696E207473C1
+:108AC000655F6D61635F6465766963655B5D207397
+:108AD00074727563747572652C20616E64206E7596
+:108AE0006D626572206F66205048597320636F6E07
+:108AF0006E6563746564206973206571756976615C
+:108B00006C656E7420746F206E756D626572206F77
+:108B100066206368616E6E656C0A0000494E464FC0
+:108B2000202020203A205043535B25642E25645D8D
+:108B3000202D20436F6E6669677572696E672050DD
+:108B40004353206F7065726174696E67206D6F6446
+:108B5000650A0000494E464F202020203A2050430D
+:108B6000535B25642E25645D202D205043532053F4
+:108B7000474D4949206D6F646520656E61626C6583
+:108B8000640A0000494E464F202020203A205043DE
+:108B9000535B25642E25645D202D205043532053C4
+:108BA000474D4949206D6F64652064697361626C4B
+:108BB00065640A005741524E494E47203A204D41C4
+:108BC000432047726F7570735B25645D2D3E706D39
+:108BD00061635F696E666F5B25645D204D44494F3C
+:108BE000206973206E6F7420757365642C20756E18
+:108BF00061626C6520746F2072756E205048592038
+:108C0000646574656374696F6E0A00005741524E63
+:108C1000494E47203A205048595B25642E25645D13
+:108C2000202D20504859206E6F742063617061625E
+:108C30006C6520666F72204175746F2D4E65676F8D
+:108C400074696174696F6E0A00000000494E464FF6
+:108C5000202020203A205048595B25642E25645D51
+:108C6000202D2052657374617274204175746F2DCC
+:108C70004E65676F74696174696F6E2C20636865F7
+:108C8000636B696E6720504859206C696E6B2E2E9D
+:108C90002E0A00005741524E494E47203A20504874
+:108CA000595B25642E25645D202D204175746F2D40
+:108CB0004E65676F74696174696F6E204641494CF7
+:108CC00045440A00494E464F202020203A20504873
+:108CD000595B25642E25645D202D204175746F2D10
+:108CE0004E65676F74696174696F6E2050415353AC
+:108CF00045440A00494E464F202020203A20504843
+:108D0000595B25642E25645D202D20436865636BC7
+:108D1000696E67206C696E6B2E2E2E0A00000000B3
+:108D2000494E464F202020203A205048595B256468
+:108D30002E25645D202D204C696E6B206E6F742093
+:108D40007965742065737461626C69736865642CFD
+:108D50002072657374617274206175746F2D6E6515
+:108D6000676F74696174696F6E2E2E2E0A000000A1
+:108D70005741524E494E47203A205048595B25648E
+:108D80002E25645D202D204C696E6B20636F756C01
+:108D900064206E6F742065737461626C69736865BA
+:108DA000640A0000494E464F202020203A205048B7
+:108DB000595B25642E25645D202D204C696E6B2047
+:108DC00065737461626C69736865640A0000000011
+:108DD000494E464F202020203A205048595B2564B8
+:108DE0002E25645D202D204361706162696C697479
+:108DF00079206F6620504859203A0A00494E464F64
+:108E0000202020203A203130303020426173652DFF
+:108E1000582046756C6C204475706C6578203D2038
+:108E200025640A00494E464F202020203A20313048
+:108E3000303020426173652D582048616C662044B3
+:108E400075706C6578203D2025640A00494E464FB8
+:108E5000202020203A203130303020426173652DAF
+:108E6000542046756C6C204475706C6578203D20EC
+:108E700025640A00494E464F202020203A203130F8
+:108E8000303020426173652D542048616C66204467
+:108E900075706C6578203D2025640A00494E464F68
+:108EA000202020203A2031303020426173652D543B
+:108EB00034202020202020202020202020203D2081
+:108EC00025640A00494E464F202020203A203130A8
+:108ED0003020426173652D582046756C6C204475B6
+:108EE000706C657820203D2025640A00494E464F6D
+:108EF000202020203A2031303020426173652D58E7
+:108F00002048616C66204475706C657820203D2097
+:108F100025640A00494E464F202020203A20313057
+:108F20003020426173652D54322046756C6C2044AC
+:108F300075706C6578203D2025640A00494E464FC7
+:108F4000202020203A2031303020426173652D549A
+:108F5000322048616C66204475706C6578203D2035
+:108F600025640A00494E464F202020203A20313007
+:108F700020426173652D542046756C6C20447570D9
+:108F80006C65782020203D2025640A00494E464F1C
+:108F9000202020203A20313020426173652D54205A
+:108FA00048616C66204475706C65782020203D20F7
+:108FB00025640A00494E464F202020203A20504880
+:108FC000595B25642E25645D202D204C696E6B2035
+:108FD000506172746E6572204361706162696C6980
+:108FE0007479203A0A000000494E464F2020202084
+:108FF0003A2031303020426173652D545820467537
+:109000006C6C204475706C6578203D2025640A00E6
+:10901000494E464F202020203A20313030204261F6
+:1090200073652D54582048616C66204475706C65DA
+:1090300078203D2025640A00494E464F20202020FC
+:109040003A20313020426173652D54582046756CAA
+:109050006C204475706C657820203D2025640A00E2
+:10906000494E464F202020203A2031302042617363
+:10907000652D54582048616C66204475706C657885
+:1090800020203D2025640A00494E464F2020202004
+:109090003A205048595B25642E25645D202D2041DF
+:1090A00064766572746973656D656E74206F662091
+:1090B0003130303020426173652D542046756C6C20
+:1090C000204475706C65782073657420746F20255A
+:1090D000640A0000494E464F202020203A20504884
+:1090E000595B25642E25645D202D204164766572D0
+:1090F000746973656D656E74206F66203130303031
+:1091000020426173652D542048616C66204475705F
+:109110006C65782073657420746F2025640A0000E4
+:10912000494E464F202020203A205048595B256464
+:109130002E25645D202D2041647665727469736507
+:109140006D656E74203130303020426173652D546E
+:109150002068616C66204475706C65782073657456
+:1091600020746F2025640A00494E464F202020209D
+:109170003A205048595B25642E25645D202D2041FE
+:1091800064766572746973656D656E74206F6620B0
+:1091900031303020426173652D5434207365742062
+:1091A000746F2025640A0000494E464F202020207D
+:1091B0003A205048595B25642E25645D202D2041BE
+:1091C00064766572746973656D656E74206F662070
+:1091D00031303020426173652D54582046756C6CD7
+:1091E000204475706C65782073657420746F202539
+:1091F000640A0000494E464F202020203A20504863
+:10920000595B25642E25645D202D204164766572AE
+:10921000746973656D656E74206F6620313030201F
+:10922000426173652D54582048616C662044757006
+:109230006C65782073657420746F2025640A0000C3
+:10924000494E464F202020203A205048595B256443
+:109250002E25645D202D20416476657274697365E6
+:109260006D656E74206F6620313020426173652D0C
+:1092700054582046756C6C204475706C657820736A
+:10928000657420746F2025640A000000494E464F23
+:10929000202020203A205048595B25642E25645D0B
+:1092A000202D204164766572746973656D656E74F6
+:1092B000206F6620313020426173652D545820485C
+:1092C000616C66204475706C6578207365742074D9
+:1092D0006F2025640A0000004552524F5220202082
+:1092E0003A204D41432047726F75705B25645D20C5
+:1092F0002D204E6F6E65206F662074686520504883
+:109300005973204175746F2D4E65676F7469617470
+:10931000696F6E20636F6D706C65746564210A00FF
+:10932000494E464F202020203A204D41432047728D
+:109330006F75705B25645D202D20436F6D6D6F6EC2
+:10934000205370656564203A202564204D62707357
+:109350000A0000004552524F522020203A204D4131
+:10936000432047726F75705B25645D202D204E6F22
+:1093700020636F6D6D6F6E2073706565642061741E
+:1093800020616C6C210A00004552524F522020206F
+:109390003A204D41432047726F75705B25645D2014
+:1093A0002D20496E76616C696420636F6D6D6F6E00
+:1093B00020737065656420737065636966696564B0
+:1093C0002120636F6D6D6F6E207370656564203D45
+:1093D0002025640A000000004552524F52202020F0
+:1093E0003A205048595B25642E25645D202D20507D
+:1093F000485920646F6573206E6F742073757070A8
+:109400006F72742031303030204D6270732C2070B8
+:109410006C65617365207370656369667920766138
+:109420006C696420636F6D6D6F6E20737065656429
+:109430000A000000494E464F202020203A20504884
+:10944000595B25642E25645D202D205048592053FA
+:109450005441545553203D203078253034780A0A41
+:1094600000000000494E464F202020203A204D4168
+:10947000432047726F75705B25645D202D20416C21
+:109480006C20504859732073657420746F20636F8B
+:109490006D6D6F6E207370656564203A20256420C1
+:1094A0004D6270730A0000004D415256454C4C20ED
+:1094B0003A20456E61626C696E67206175746F2039
+:1094C00063726F73736F7665720000004D41525680
+:1094D000454C4C203A205048592072657365740001
+:1094E0004D415256454C4C203A204D6F64652063E7
+:1094F00068616E67656420746F20474D4949207428
+:109500006F20636F70706572206D6F64650000007E
+:109510004D415256454C4C203A2044697361626C6F
+:10952000652052474D49492054696D696E67204353
+:109530006F6E74726F6C00004D415256454C4C205A
+:109540003A204D6F6465206368616E6765642074BE
+:109550006F2053474D494920776974686F757420AF
+:10956000636C6F636B20776974682053474D49497A
+:10957000204175746F2D4E656720746F20636F7086
+:10958000706572206D6F6465000000004D41525699
+:10959000454C4C203A204D6F6465206368616E67CE
+:1095A000656420746F2052474D49492F4D6F64699F
+:1095B00066696564204D494920746F20436F70705F
+:1095C0006572206D6F6465004D415256454C4C20CC
+:1095D0003A20456E61626C652052474D49492054DE
+:1095E000696D696E6720436F6E74726F6C00000066
+:1095F00074696D65206F75742061667465722035BD
+:10960000206D736563207768696C65207761697484
+:10961000696E672066726565204649464F2062750F
+:109620006666657220666F722073746F72696E670A
+:10963000207374616E64617264206465736372691F
+:1096400070746F720A00000074696D65206F757424
+:109650002061667465722035206D736563207768BC
+:10966000696C652077616974696E672066726565EB
+:10967000204649464F2062756666657220666F72A5
+:109680002073746F72696E6720657874656E6465A7
+:10969000642064657363726970746F720A000000FD
+:1096A00074696D65206F757420616674657220350C
+:1096B000206D736563207768696C652077616974D4
+:1096C000696E672066726565204649464F2062755F
+:1096D0006666657220666F722073746F72696E675A
+:1096E0002064657363726970746F720A0000000011
+:1096F00074696D65206F75742061667465722035BC
+:10970000206D736563207768696C65207772697472
+:10971000696E67207374616E64617264206465733E
+:1097200063726970746F7220746F204649464F0AE5
+:109730000000000074696D65206F757420616674A7
+:1097400065722035206D736563207768696C6520CC
+:1097500077726974696E6720657874656E64656494
+:109760002064657363726970746F7220746F204631
+:1097700049464F0A0000000074696D65206F7574DA
+:109780002061667465722035206D7365632077688B
+:10979000696C652077616974696E6720666F7220F5
+:1097A000616E792070656E64696E67207472616E97
+:1097B0007366657220636F6D706C6574650A000076
+:1097C0006661696C656420746F206372656174659D
+:1097D0002073656D6170686F7265730A0000000028
+:1097E000616C746572615F6574685F7473655F69ED
+:1097F0006E69742025640A00707265705F74736509
+:109800005F6D61632025640A00000000416C74658F
+:10981000726120545345204D414320657468657240
+:109820006E6574007473655F6D61635F696E697402
+:109830002025640A000000005B616C746572615F42
+:109840006574685F7473655F696E69745D204572E5
+:10985000726F72206F70656E696E67205458204D6C
+:109860005347444D410000005B616C746572615F59
+:109870006574685F7473655F696E69745D204572B5
+:10988000726F72206F70656E696E67205258204D3E
+:109890005347444D410000005453454D414320532C
+:1098A0005720726573657420626974206E657665F1
+:1098B0007220636C65617265642100005741524EED
+:1098C0003A2052582F5458206E6F74206469736187
+:1098D000626C65642061667465722072657365747C
+:1098E0002E2E2E206D697373696E672050485920A3
+:1098F000636C6F636B3F20434D445F434F4E46495B
+:10990000473D3078253038780A0000004F4B2C2036
+:10991000783D25642C20434D445F434F4E464947D4
+:109920003D3078253038780A000000005B7473659C
+:109930005F6D61635F696E69745D204572726F72FD
+:109940003A20496E636F6D70617469626C652025A1
+:10995000642076616C756520776974682054585F5F
+:10996000434D445F53544154207265676973746575
+:10997000722072657475726E2054785368696674CB
+:1099800031362076616C75652E200A005B74736534
+:109990005F6D61635F696E69745D204572726F729D
+:1099A0003A20496E636F6D70617469626C65202541
+:1099B000642076616C756520776974682052585F01
+:1099C000434D445F53544154207265676973746515
+:1099D000722072657475726E20527853686966746D
+:1099E00031362076616C75652E200A000A4D4143A0
+:1099F00020706F73742D696E697469616C697A6126
+:109A000074696F6E3A20434D445F434F4E46494759
+:109A10003D3078253038780A000000005453455F07
+:109A20004D41435F494E4954206572726F72000088
+:109A30007261775F73656E642043414C4C454420EE
+:109A4000414741494E212121000000007261775FAA
+:109A500073656E642829204D5347444D41206E6F35
+:109A60007420617661696C61626C652C207265742A
+:109A70003D25642C206C656E3D25640A00000000C5
+:109A80005258204552524F52000000005458205363
+:109A9000544F5050454400005B7473655F6D7367AD
+:109AA000646D615F726561645F696E69745D2046B3
+:109AB0006174616C206572726F723A204E6F20661D
+:109AC000726565207061636B65742062756666659A
+:109AD000727320666F722052580000005B747365C9
+:109AE0005F6D7367646D615F726561645F696E6904
+:109AF000745D2052582064657363726970746F726C
+:109B000020636861696E2064657363202825642082
+:109B100064657074682920637265617465640A0005
+:109B20004E6F206672656520627566666572732089
+:109B3000666F7220727800007473655F6D61635F99
+:109B4000737461747328292C207374617473207783
+:109B5000696C6C206265206164646564206C61746A
+:109B60006572210A000000004152503A20756E6172
+:109B7000626C6520746F207265676973746572200A
+:109B8000747970652077697468204D414320447270
+:109B9000697665720000000065745F73656E643AF3
+:109BA0002070726570656E6400000000696E6974F3
+:109BB000206572726F72202564206F6E206E65744E
+:109BC0005B25645D0A0000006E6574636C6F7365ED
+:109BD00028292063616C6C65640000006E65746305
+:109BE0006C6F73653A20636C6F73696E672069668A
+:109BF0006163652025730A006E65742025733A2021
+:109C00006E6F20636C6F736520726F7574696E651B
+:109C1000210A0000706B7464656D75783A20676F77
+:109C200074206E756C6C20706B740000706B7464C3
+:109C3000656D75783A20636F727275707420706B01
+:109C400074000000706B7464656D75783A20626111
+:109C500064204966616365207479706520256C64B1
+:109C60000A000000706B7464656D75783A2062615B
+:109C70006420706B742074797065203078253034DE
+:109C8000780A0000756E61626C6520746F20696EE1
+:109C9000697469616C697A65204950204D756C74EE
+:109CA0006963617374000000756E61626C65207495
+:109CB0006F2066696E6420616E7920776F726B69C0
+:109CC0006E6720696E74657266616365730000007B
+:109CD000756E61626C6520746F20696E697469616C
+:109CE0006C697A65206E657400000000756E6162B3
+:109CF0006C6520746F20696E697469616C697A653E
+:109D00002061727000000000756E61626C652074E5
+:109D10006F20696E697469616C697A6520495000C9
+:109D2000756E61626C6520746F20696E697469611B
+:109D30006C697A65205443500000000065786974AE
+:109D40005F686F6F6B00000069705F657869743AD7
+:109D50002063616C6C696E672066756E6320257088
+:109D60000A000000626164206E65742070747200E5
+:109D7000763100007632000025733A206D6F6465FD
+:109D80003A202575205B25735D2000007072657395
+:109D9000656E7400616273656E74000076312072C6
+:109DA00074723A202575205B25735D207631206C16
+:109DB0006173742071756572793A202578205B6E25
+:109DC0006F772025785D0A000A0000005B5278203A
+:109DD0005D2049474D50206D657373616765732041
+:109DE000726376643A20256C752C2074696D6572F7
+:109DF000732072756E6E696E673A20256C750A0065
+:109E00005B5278205D2049474D50763120486F7372
+:109E100074204D656D626572736869702051756557
+:109E200072696573207263766420286279207631C6
+:109E30002D6D6F6465206C696E6B73293A20256CFB
+:109E4000750A00005B5278205D2049474D507631FD
+:109E500020486F7374204D656D6265727368697018
+:109E6000205265706F72747320726376643A202595
+:109E70006C750A005B5278205D2049474D502048A0
+:109E80006F7374204D656D626572736869702052DE
+:109E900065706F727473207263766420636175738A
+:109EA000696E672074696D65722063616E63656CAD
+:109EB0006C6174696F6E3A20256C750A00000000B1
+:109EC0005B5278205D2049474D50763120486F73B2
+:109ED00074204D656D626572736869702051756597
+:109EE0007269657320726376642028627920763205
+:109EF0002D6D6F6465206C696E6B73293A20256C3B
+:109F0000750A00005B5278205D2049474D5076323B
+:109F10002047656E6572616C205175657269657365
+:109F200020726376643A20256C752C2047726F7519
+:109F3000702D537065636966696320517565726938
+:109F4000657320726376643A20256C750A00000000
+:109F50005B5278205D2049474D5020486F73742034
+:109F60004D656D62657273686970205265706F72BD
+:109F7000747320726376642077697468206E6F2032
+:109F80006C6F63616C2074696D65723A20256C7525
+:109F90000A0000005B5278205D2049474D50763220
+:109FA000204C656176652047726F7570206D657312
+:109FB000736167657320726376643A20256C750A55
+:109FC000000000005B5478205D2049474D507632F8
+:109FD000204C656176652047726F7570206D6573E2
+:109FE00073616765732073656E743A20256C752CF8
+:109FF000204D656D62657273686970205265706F7F
+:10A000007274732073656E743A20256C750A0000B3
+:10A010005B5478205D2049474D50763120486F735E
+:10A0200074204D656D626572736869702052657049
+:10A030006F7274732073656E743A20256C750A0014
+:10A040005B4572725D2049474D50207061636B65BE
+:10A050007473207263766420776974682062616427
+:10A06000206C656E6774683A20256C750A000000E4
+:10A070005B4572725D2049474D50207061636B658E
+:10A0800074732072637664207769746820626164F7
+:10A0900020636865636B73756D3A20256C750A00E3
+:10A0A0005B4572725D205061636B657420627566FA
+:10A0B00066657220616C6C6F636174696F6E206697
+:10A0C00061696C757265733A20256C752C2042614C
+:10A0D000642049474D50204F706572204D6F646574
+:10A0E00020636F6E6669673A20256C750A00000070
+:10A0F0005B4572725D204261642049474D5020519A
+:10A1000075657269657320726376643A20256C7593
+:10A110002C204261642049474D50205265706F7277
+:10A12000747320726376643A20256C750A0000000F
+:10A130005B4572725D204261642049474D50763222
+:10A140002047726F75702D5370656369666963206F
+:10A150005175657269657320726376643A20256C67
+:10A16000750A00005B4572725D2049474D5076329A
+:10A170002047726F75702D5370656369666963203F
+:10A1800051756572696573207263766420776974AE
+:10A190006820756E6B6E6F776E2047726F757020DA
+:10A1A000416464726573733A20256C750A0000007F
+:10A1B0005B4572725D2049474D50204D656D62656B
+:10A1C0007273686970205265706F72747320726365
+:10A1D0007664207769746820756E6B6E6F776E2079
+:10A1E00047726F757020416464726573733A2025FD
+:10A1F0006C750A005B4572725D204E756D6265720A
+:10A20000206F662049474D507632206D657373612B
+:10A21000676573207263766420776974686F7574FC
+:10A2200020526F7574657220416C657274206F7076
+:10A2300074696F6E3A20256C750A00005B45727276
+:10A240005D2049474D50207061636B657473206FCA
+:10A250006620756E6B6E6F776E20747970652072F4
+:10A260006376642062792076312D6D6F6465206C91
+:10A27000696E6B733A20256C750A00005B4572723B
+:10A280005D2049474D50207061636B657473206F8A
+:10A290006620756E6B6E6F776E20747970652072B4
+:10A2A0006376642062792076322D6D6F6465206C50
+:10A2B000696E6B733A20256C750A00002530327880
+:10A2C00020000000256300000A00000025752E25EF
+:10A2D000752E25752E257500256C642064617973B3
+:10A2E0002C202564683A25646D3A256473000000CB
+:10A2F000256420686F7572732C2025646D3A25647F
+:10A30000730000002564206D696E757465732C20E0
+:10A310002564207365632E0070616E69633A2025A1
+:10A32000730A00006E735F7072696E74663A4275EC
+:10A3300066666572206F766572666C6F77000000E6
+:10A34000257300002E2E2E2E707265737320616EA1
+:10A3500079206B657920666F72206D6F7265202899
+:10A3600045534320746F20627265616B292E2E2E37
+:10A370002E000000496E6574206D61696E0000005A
+:10A38000636C6F636B207469636B00007461736B43
+:10A3900020637265617465206572726F72000000DF
+:10A3A0006E65746D61696E004368726F6E4F532005
+:10A3B0004150492063616C6C206661696C757265FF
+:10A3C0002C20746F20526573756D65205375737002
+:10A3D000656E646564205461736B2100544B5F4F5C
+:10A3E000535461736B526573756D65004368726F8A
+:10A3F0006E4F53204150492063616C6C2066616947
+:10A400006C7572652C20756E61626C6520746F20AE
+:10A410006964656E74696679207461736B210000EC
+:10A42000544B5F4F535461736B51756572790000E3
+:10A430004368726F6E4F532052544F5320737461B0
+:10A4400074733A0A00000000436F6E7465787420DC
+:10A4500073776974636865733B2044656C61793A0E
+:10A460002020256C750A0000202020202020206E4E
+:10A47000616D6520202020207072696F2E2073741A
+:10A480006174652020202077616B6575707320737F
+:10A490007461636B2D73697A6520737461636B2DCE
+:10A4A000757365200A00000025313573202532645C
+:10A4B000202020203078253034782C202020202D9A
+:10A4C0002D2D2020200000002536642C2020202067
+:10A4D00020202536640A00004E6F20737461636B80
+:10A4E00020646174610A00007463705F736C656559
+:10A4F000705F636F756E74203D20256C752C207421
+:10A5000063705F77616B6575705F636F756E7420E4
+:10A510003D20256C750A0000676C6F62616C5F54AA
+:10A52000435077616B6575705F736574496E6478CD
+:10A53000203D2025642C207463705F736C6565700A
+:10A540005F74696D656F7574203D20256C750A0018
+:10A5500050696E672066726F6D204E6574506F7221
+:10A560007420495020737461636B000069636D70DF
+:10A570003A2063616E277420616C6C6F6320706198
+:10A58000636B65740000000069636D703A2063615D
+:10A590006E27742073656E64206563686F20726532
+:10A5A0007175657374000000706B5F696E69743A51
+:10A5B0002062616420646566696E65004E65746939
+:10A5C0006E69743A2063616C6C6F63206661696CBC
+:10A5D00065642067657474696E6720627566666578
+:10A5E000722025640A000000706B5F667265653A30
+:10A5F0002062756666657220257020616C726561E7
+:10A60000647920696E2062696766726565710A0007
+:10A61000706B5F667265653A20627566666572206A
+:10A62000257020616C726561647920696E206C69A7
+:10A630006C66726565710A00526567756C6172209F
+:10A64000627566666572206572726F7220737461DE
+:10A65000746973746963733A0A000000426164208C
+:10A66000627566666572206C656E67746820256C1D
+:10A67000752C2047756172642062616E6420766972
+:10A680006F6C6174696F6E7320256C750A00000031
+:10A690004D756C7469706C652066726565732025F4
+:10A6A0006C752C20496E636F6E73697374656E747C
+:10A6B000206C6F636174696F6E20256C750A0000F1
+:10A6C0006474726170202D206E65656473206272FF
+:10A6D00065616B706F696E7400000000465F5345E2
+:10A6E00054464C206661696C65642E006C6F636B28
+:10A6F000204E455400000000756E6C6F636B204E59
+:10A7000045540000737461636B20616C6C6F63006F
+:10A710005072696F726974792072657175657374AE
+:10A72000656420666F72207461736B20222573222A
+:10A7300020285072696F3A25642920636F6E666C19
+:10A7400069637473207769746820616C72656164F1
+:10A75000792072756E6E696E67207461736B20224A
+:10A7600025732220285072696F3A202564290A0037
+:10A77000596F75206D6179207769736820746F2037
+:10A78000636865636B20796F7572207461736B20E9
+:10A790007072696F726974792073657474696E6719
+:10A7A0007320696E20223C62737020706174683E71
+:10A7B0005C696E696368655C7372635C685C6E6932
+:10A7C0006F73325C6970706F72742E6822206167DB
+:10A7D00061696E737420746865207072696F726944
+:10A7E00074792073657474696E677320696E20795B
+:10A7F0006F7572206170706C69636174696F6E202F
+:10A80000616E64207265636F6D70696C652E0A00FD
+:10A810005072696F726974792072657175657374AD
+:10A82000656420666F72207461736B202225732229
+:10A8300020285072696F3A25642920657863656520
+:10A84000647320617661696C61626C652070726905
+:10A850006F72697479206C6576656C7320696E20FF
+:10A860007468652073797374656D20284F535F4C4D
+:10A870004F574553545F5052494F203D202564297E
+:10A880000A0A0000506C65617365206D6F6469662B
+:10A890007920746865207461736B73207072696FBE
+:10A8A00072697479206C6576656C2C206F72206DEE
+:10A8B0006F646966792074686520224C6F776573D0
+:10A8C000742061737369676E61626C652070726970
+:10A8D0006F72697479222073657474696E67206978
+:10A8E0006E20746865204D6963726F432F4F532D3E
+:10A8F000494920636F6D706F6E656E7400000000D3
+:10A900005461736B20637265617465206572726F48
+:10A9100072202F284D6963726F432F4F532D494981
+:10A92000206572726F7220636F64653A25642F2907
+:10A93000206F6E2025730A00437265617465642080
+:10A9400022257322207461736B20285072696F3A3C
+:10A95000202564290A0000006D686561705F7365D9
+:10A960006D5F7074722063726561746520657272C8
+:10A970000000000072637664715F73656D5F7074D0
+:10A980007220637265617465206572720000000058
+:10A9900072657369645F73656D6170686F7265205D
+:10A9A0006372656174652065727200006170705F2A
+:10A9B00073656D6170686F7265206372656174653F
+:10A9C0002065727200000000676C6F6277616B65D2
+:10A9D0005F73656D6170686F726520637265617425
+:10A9E00065206572720000006E70616C6C6F6300B0
+:10A9F0006E706672656500006D667265653A2071FD
+:10AA00005F6C656E000000006D5F667265653A20E0
+:10AA100074797065000000006D5F667265653A20AC
+:10AA20006D697373696E67006D5F636F70793A204B
+:10AA3000626164206C656E0064746F6D00000000DC
+:10AA4000746370696E6974006E707463703A204D3F
+:10AA500061784C6E683A25642C20653A25640A00BA
+:10AA60007463705F6F75743A6D6275662D6E627592
+:10AA70006600000069705F6F75747075743A206FBE
+:10AA8000766572666C6F7700616363657074000051
+:10AA9000736F667265650000736F616363657074E0
+:10AAA00000000000736F72656376203100000000C3
+:10AAB000736F726563763A74797065202564206ED1
+:10AAC0006F74206E616D0000736F72656376203263
+:10AAD00000000000736F7265637620330000000091
+:10AAE000736F6973636F6E6E6563746564000000F5
+:10AAF0007362636F6D703A6261642074797065206F
+:10AB000025640A007362636F6D703A6261640000CD
+:10AB10007362666C75736800736264726F700000B4
+:10AB20007463705F696E7075740000007463705FA9
+:10AB300070756C6C6F75746F6662616E6400000096
+:10AB40007463705F6F75742D207061636B65742022
+:10AB500070747220756E646572666C6F770A00009F
+:10AB60007463705F6F757470757400007463705FE8
+:10AB70006F7574707574205245584D540000000074
+:10AB80007463705F726573706F6E642D20706163A3
+:10AB90006B65742070747220756E646572666C6F7C
+:10ABA000770A00002A2A2A205052555F4143434524
+:10ABB00050542062616420646F6D61696E203D2095
+:10ABC00025640A007463705F7573727265710000AA
+:10ABD0002F6465762F6E756C6C000000496E74658D
+:10ABE000724E6963686520506F727461626C652093
+:10ABF0005443502F49502C2076332E31200A000028
+:10AC0000494E45543E200000436F70797269676871
+:10AC10007420313939362D3230303820627920496C
+:10AC20006E7465724E6963686520546563686E6F03
+:10AC30006C6F676965732E20416C6C207269676860
+:10AC400074732072657365727665642E200000004F
+:10AC5000696E6574207374617274757020657272A8
+:10AC60006F723A2025730A00495000004950206154
+:10AC7000646472657373206F66202573203A202503
+:10AC8000730A00004E455400484F53540000000022
+:10AC900050524F5400000000504F5254000000002A
+:10ACA000465241470000000053524300676F742032
+:10ACB00049434D5020257320554E5245414348414C
+:10ACC000424C452066726F6D2025730A000000001B
+:10ACD00069666163652025642D25732049502061D4
+:10ACE0006464723A25732020000000007375626E60
+:10ACF00065743A2573202000676174657761793A3D
+:10AD000025730A0063757272656E74207469636BD3
+:10AD100020636F756E7420256C750A00636F6D6D0E
+:10AD20006F6E2064656C617920706172616D65740D
+:10AD300065723A2020256C75207469636B73202836
+:10AD4000256C75206D73292E0A000000636F6D6DF0
+:10AD50006F6E20686F737420706172616D657465C9
+:10AD6000723A2025730A0000636F6D6D6F6E206C60
+:10AD7000656E67746820706172616D657465723AA2
+:10AD80002025640A00000000564653204D6F64756C
+:10AD90006C652070726570206661696C6564000086
+:10ADA000707265705F6D6F64756C65730000000094
+:10ADB0005461736B2077616B657570733A000000A6
+:10ADC0006E65746D61696E3A20256C750A0000002D
+:10ADD0006E65747469636B3A20256C750A00000017
+:10ADE0000A00000049434D503A20705B25755D20F4
+:10ADF00066726F6D2025752E25752E25752E25758D
+:10AE00000A00000049434D503A20426164207873A3
+:10AE1000756D20253034782073686F756C642068F8
+:10AE2000617665206265656E20253034780A000001
+:10AE300049434D503A206563686F207265706C79A4
+:10AE400020746F2025752E25752E25752E25750AE3
+:10AE50000000000069636D703A207265706C7920A3
+:10AE60006661696C6564000049434D503A20676F24
+:10AE700074206465737420756E72656163686162C5
+:10AE80006C65207479706520000000002575206FC6
+:10AE90006E2025752E25752E25752E257520000012
+:10AEA00066726F6D2025752E25752E25752E2575DC
+:10AEB0000A00000049434D503A20736F7572636574
+:10AEC000207175656E63682066726F6D2025752E22
+:10AED00025752E25752E25750A00000049434D5015
+:10AEE0003A207263766420726564697265637420C7
+:10AEF000666F722025752E25752E25752E257520D9
+:10AF000000000000746F2025752E25752E25752EE6
+:10AF100025750A0049434D503A2074696D657820C3
+:10AF20006D73672066726F6D2025752E25752E2531
+:10AF3000752E25750A0000002061626F757420254A
+:10AF4000752E25752E25752E25750A0049434D5001
+:10AF50003A20676F7420706172616D2070726F6249
+:10AF60006C656D206D6573736167650049434D5075
+:10AF70003A20676F742074696D657374616D702019
+:10AF8000726571756573740069636D703A206361F1
+:10AF90006E27742073656E642074696D65737461C7
+:10AFA0006D70207265706C790000000069636D70CF
+:10AFB0003A20676F7420696E666F207265717565DF
+:10AFC0007374000069636D703A20756E68616E6419
+:10AFD0006C656420747970652025750A0000000096
+:10AFE0006E657400686F73740000000070726F7497
+:10AFF0006F636F6C00000000706F727400000000DF
+:10B00000667261676D656E746174696F6E206E65DE
+:10B010006564656400000000736F7572636520727B
+:10B020006F757465206661696C65640069636D7035
+:10B030003A2073656E64696E6720257320646573BA
+:10B040007420756E726561636861626C6520746FEF
+:10B050002025752E25752E25752E25750A000000D4
+:10B0600069636D703A2063616E277420616C6C6F48
+:10B070006320706B7400000049434D503A204361D7
+:10B080006E27742073656E64206465737420756E1A
+:10B09000726561636861626C6500000069636D7070
+:10B0A0003A2073656E64696E672049434D502054A1
+:10B0B000696D6520457863656564656420776974AA
+:10B0C0006820636F646520257520746F2025752EB8
+:10B0D00025752E25752E25750A00000049434D5013
+:10B0E0003A2043616E27742073656E642054696D45
+:10B0F00065204578636565646564000049505F4973
+:10B100004E49543A20756E61626C6520746F2072EE
+:10B1100065676973746572207479706520776974E6
+:10B1200068204D414320647269766572000000001A
+:10B1300049505F494E4954204552524F523A20637C
+:10B14000616E277420616C6C6F6320726F7574651B
+:10B15000207461626C65000069705F777269746564
+:10B160005F696E7465726E616C3A20706B743A251B
+:10B1700070206C656E257520746F2025752E2575E1
+:10B180002E25752E25752C2063616E277420726F15
+:10B190007574650A0000000069705F7772697465F4
+:10B1A0003A20706B745B25755D20746F2025752EB9
+:10B1B00025752E25752E25752C00000020726F75C3
+:10B1C00074652025752E25752E25752E25750A008A
+:10B1D00049503A20436F756C646E277420726F7506
+:10B1E000746520746F2025752E25752E25752E25E6
+:10B1F000750A00004950207061636B6574206865B2
+:10B20000616465723A0A00007665722F686C656E3B
+:10B210003A20253032782C20544F533A20253032B2
+:10B22000782C206C656E3A20253034782C206964A7
+:10B230003A20253034780A006F6B000062616400A8
+:10B24000666C6167732F6F6666733A2025303478B9
+:10B250002C2054544C20253032782C2070726F747E
+:10B260006F636F6C3A20253032782C20636B7375D6
+:10B270006D3A202530347820282573290A000000F3
+:10B280007372633A2025752E25752E25752E25752A
+:10B2900020200000646573743A2025752E25752ED4
+:10B2A00025752E25750A000069705F636F707970CF
+:10B2B0006B7428293A20756E61626C6520746F206A
+:10B2C0006F627461696E207061636B657420286CB5
+:10B2D000656E202564290A0069705F7263763A20E2
+:10B2E000676F74207061636B65742C206C656E3AB7
+:10B2F00025642C2069663A25640A000069705F7233
+:10B3000063763A2062616420706B74206C656E0015
+:10B3100069705F7263763A20626164207665727349
+:10B32000696F6E206E756D626572000069705F7284
+:10B3300063763A20626164207873756D00000000C6
+:10B3400069705F7263763A20676F7420706B742047
+:10B350006E6F7420666F72206D653B20666F722081
+:10B3600025752E25752E25752E25750A00000000E1
+:10B3700069705F7263763A20667261676D656E749C
+:10B380002066726F6D2025752E25752E25752E254C
+:10B39000750A000069705F64656D75783A206261B6
+:10B3A00064204950207479706520307825780A002F
+:10B3B00069705F64656D75783A20706B7420707287
+:10B3C0006F742025752066726F6D2025752E25758A
+:10B3D0002E25752E25750A0069705F64656D757878
+:10B3E0003A20756E68616E646C65642070726F746B
+:10B3F0002025750A00000000000000007300000016
+:10B400007072657070656420257520696E74657250
+:10B410006661636525732C20696E697469616C6966
+:10B420007A696E672E2E2E0A0000000049503A20DD
+:10B43000436F756C646E277420616C6C6F6361740C
+:10B44000652065702073746F726167652E0000005F
+:10B450006164645F726F7574653A2072656A6563D2
+:10B46000746564206E756C6C207061726D3B206435
+:10B470006573743A20256C782C206D61736B3A20CB
+:10B48000256C780A000000005544503A206261643F
+:10B49000206C656E20706B743A20726376643A207B
+:10B4A00025752C206864723A2025752E0A0000004C
+:10B4B00055445044454D55583A2062616420787394
+:10B4C000756D2025303478207269676874202530C6
+:10B4D00034782066726F6D2025752E25752E2575A2
+:10B4E0002E25750A000000005544503A20706B74F8
+:10B4F0005B25755D2066726F6D2025752E25752E76
+:10B5000025752E25753A256420746F2025640A0060
+:10B510005544503A2069676E6F72696E6720697092
+:10B520002062726F61646361737400005544503A25
+:10B5300020756E657870656374656420706F7274D1
+:10B5400020253034780A00005544503A20706B743E
+:10B55000205B25755D2025303478202D3E20257513
+:10B560002E25752E25752E25753A253034780A003E
+:10B570006D637465737420696E69742063616C6CAB
+:10B5800065640000745F736F636B657428292066BF
+:10B5900061696C65642C204572723A2025640A004A
+:10B5A000745F736574736F636B6F707428292053B5
+:10B5B0004F5F524555534541444452206661696C82
+:10B5C00065642C204572723A2025640A0000000050
+:10B5D000745F62696E642829206661696C65642CF9
+:10B5E000204572723A2025640A0000003233342E5E
+:10B5F000352E362E370000004A6F696E696E67205F
+:10B600006D756C7469636173742067726F75703ADD
+:10B610002025730A00000000745F736574736F6304
+:10B620006B6F707428292049505F4144445F4D4539
+:10B630004D42455253484950206661696C65642CFF
+:10B64000204572723A2025640A0000003233342EFD
+:10B65000312E322E330000003233342E342E352E6C
+:10B6600036000000745F736574736F636B6F707482
+:10B6700028292049505F4D554C5449434153545F4C
+:10B6800054544C206661696C65642C204572723A92
+:10B690002025640A00000000745F736574736F6393
+:10B6A0006B6F707428292049505F4D554C544943A5
+:10B6B0004153545F4C4F4F50206661696C65642C58
+:10B6C000204572723A2025640A0000004E6F7720F0
+:10B6D00073656E64696E6720746F2028616E6420E4
+:10B6E000726563656976696E672066726F6D292081
+:10B6F0006D756C7469636173742067726F75703AED
+:10B700002025730A0000000025640000745F736543
+:10B710006E64746F2829206661696C65642C20450D
+:10B7200072726F723A2025640A000000745F7365BC
+:10B7300074736F636B6F7074282920534F5F4E4F83
+:10B740004E424C4F434B20283129206661696C657D
+:10B75000642C204572723A2025640A00745F726579
+:10B76000637666726F6D2829206661696C65642C4A
+:10B77000204572726F723A2025640A0046726F6D1E
+:10B7800020686F73743A257320706F72743A256461
+:10B790002C2025730A000000745F736574736F6357
+:10B7A0006B6F7074282920534F5F4E4F4E424C4FA1
+:10B7B000434B20283029206661696C65642C204544
+:10B7C00072723A2025640A00745F736574736F6344
+:10B7D0006B6F707428292049505F44524F505F4D61
+:10B7E000454D42455253484950206661696C656435
+:10B7F0002C204572723A2025640A0000745F736F32
+:10B80000636B6574636C6F73652829206661696C6E
+:10B8100065642E20204572723A2025640A000000DB
+:10B820004D657373616765206E756D6265723A2050
+:10B830002020202020202020202020202000000068
+:10B8400065616368206E756D626572206D757374D5
+:10B85000206265206C657373207468616E203235D8
+:10B8600035000000616C6C206368617273206D7537
+:10B870007374206265206469676974732028302DB1
+:10B880003929206F7220646F747320282E290000DC
+:10B89000737472696E67206D75737420636F6E7454
+:10B8A00061696E2031202D203320646F747320284D
+:10B8B0002E290000000000004950763420616464A5
+:10B8C00072657373207061727365206661696C754F
+:10B8D000726500007564705F6F70656E3A20686F06
+:10B8E00073742025752E25752E25752E25752C2013
+:10B8F0006C736F636B2025752C2066736F636B20F0
+:10B9000025752C20666F6F20253034780A000000E2
+:10B910005544503A20436F6E6E656374696F6E20B4
+:10B92000616C7265616479206578697374732E0047
+:10B930005544503A20436F756C646E277420616CD7
+:10B940006C6F6361746520636F6E6E2073746F72C9
+:10B950006167652E000000007666666C7573682866
+:10B96000293A20546869732066756E6374696F6E36
+:10B97000206E6565647320746F20626520696D7048
+:10B980006C656D656E746564003030303030303019
+:10B990003030303030303030302020202020202017
+:10B9A0002020202020202020203030303030303027
+:10B9B00030303030303030303020202020202020F7
+:10B9C0002020202020202020200000000000000057
+:10B9D00000000000000000009CCB0408046D040877
+:10B9E000641000080A000000003800000000000099
+:10B9F000ACCB040840700408901E00080900000049
+:10BA0000003800000000000000304018000800006E
+:10BA1000000800000100000001000100010000001A
+:10BA2000587104086C710408FFFF01000000401801
+:10BA30000000000000000000000000000000000006
+:10BA4000000000000000000000000000FFFFFFFFFA
+:10BA5000DCC701080000000000000000000000003A
+:10BA600000000000000000000000000000000000D6
+:10BA700000000000000000000000000000000000C6
+:10BA800000000000000000000000000000000000B6
+:10BA900000000000000000000000000000000000A6
+:10BAA0000000000000000000000000000000000096
+:10BAB0000000000000000000000000000000000086
+:10BAC0000000000000000000000000000000000076
+:10BAD0000000000000000000000000000000000066
+:10BAE0000000000000000000000000000000000056
+:10BAF0000000000000000000000000000000000046
+:10BB00000000000000000000000000000000000035
+:10BB10000000000000000000000000000000000025
+:10BB20000000000000000000000000000000000015
+:10BB30000000000000000000000000006CBD0408D0
+:10BB4000D4BD04083CBE0408000000000000000052
+:10BB500000000000000000000000000000000000E5
+:10BB600000000000000000000000000000000000D5
+:10BB700000000000000000000000000000000000C5
+:10BB800000000000000000000000000000000000B5
+:10BB900000000000000000000000000000000000A5
+:10BBA0000000000000000000000000000000000095
+:10BBB0000000000000000000000000000000000085
+:10BBC0000000000000000000000000000000000075
+:10BBD0000000000000000000000000000100000064
+:10BBE000000000000E33CDAB34126DE6ECDE050034
+:10BBF0000B0000000000000000000000000000003A
+:10BC00000000000000000000000000000000000034
+:10BC10000000000000000000000000000000000024
+:10BC20000000000000000000000000000000000014
+:10BC30000000000000000000000000000000000004
+:10BC400000000000000000000000000000000000F4
+:10BC500000000000000000000000000000000000E4
+:10BC600000000000000000000000000000000000D4
+:10BC700000000000000000000000000000000000C4
+:10BC800000000000000000000000000000000000B4
+:10BC900000000000000000000000000000000000A4
+:10BCA0000000000000000000000000000000000094
+:10BCB0000000000000000000000000000000000084
+:10BCC0000000000000000000000000000000000074
+:10BCD0000000000000000000000000000000000064
+:10BCE0000000000000000000000000000000000054
+:10BCF0000000000000000000000000000000000044
+:10BD00000000000000000000000000000000000033
+:10BD10000000000000000000000000000000000023
+:10BD20000000000000000000000000000000000013
+:10BD30000000000000000000000000000000000003
+:10BD400000000000000000000000000000000000F3
+:10BD500000000000000000000000000000000000E3
+:10BD600000000000000000000000000000000000D3
+:10BD700000000000000000000000000000000000C3
+:10BD800000000000000000000000000000000000B3
+:10BD900000000000000000000000000000000000A3
+:10BDA0000000000000000000000000000000000093
+:10BDB0000000000000000000000000000000000083
+:10BDC0000000000000000000000000000000000073
+:10BDD0000000000000000000000000000000000063
+:10BDE0000000000000000000000000000000000053
+:10BDF0000000000000000000000000000000000043
+:10BE00000000000000000000000000000000000032
+:10BE10000000000000000000000000000000000022
+:10BE20000000000000000000000000000000000012
+:10BE30000000000000000000000000000000000002
+:10BE400000000000000000000000000000000000F2
+:10BE500000000000000000000000000000000000E2
+:10BE600000000000000000000000000000000000D2
+:10BE700000000000000000000000000000000000C2
+:10BE800000000000000000000000000000000000B2
+:10BE900000000000000000000000000000000000A2
+:10BEA0000000000000000000000000000000000092
+:10BEB0000000000000000000000000000000000082
+:10BEC0000000000000000000000000000000000072
+:10BED0000000000000000000000000000000000062
+:10BEE0000000000000000000000000000000000052
+:10BEF0000000000000000000000000000000000042
+:10BF00000000000000000000000000000000000031
+:10BF10000000000000000000000000000000000021
+:10BF20000000000000000000000000000000000011
+:10BF30000000000000000000000000000000000001
+:10BF400000000000000000000000000000000000F1
+:10BF500000000000000000000000000000000000E1
+:10BF600000000000A4BE0408A4BE0408ACBE04087F
+:10BF7000ACBE0408B4BE0408B4BE0408BCBE0408C9
+:10BF8000BCBE0408C4BE0408C4BE0408CCBE040879
+:10BF9000CCBE0408D4BE0408D4BE0408DCBE040829
+:10BFA000DCBE0408E4BE0408E4BE0408ECBE0408D9
+:10BFB000ECBE0408F4BE0408F4BE0408FCBE040889
+:10BFC000FCBE040804BF040804BF04080CBF040836
+:10BFD0000CBF040814BF040814BF04081CBF0408E5
+:10BFE0001CBF040824BF040824BF04082CBF040895
+:10BFF0002CBF040834BF040834BF04083CBF040845
+:10C000003CBF040844BF040844BF04084CBF0408F4
+:10C010004CBF040854BF040854BF04085CBF0408A4
+:10C020005CBF040864BF040864BF04086CBF040854
+:10C030006CBF040874BF040874BF04087CBF040804
+:10C040007CBF040884BF040884BF04088CBF0408B4
+:10C050008CBF040894BF040894BF04089CBF040864
+:10C060009CBF0408A4BF0408A4BF0408ACBF040814
+:10C07000ACBF0408B4BF0408B4BF0408BCBF0408C4
+:10C08000BCBF0408C4BF0408C4BF0408CCBF040874
+:10C09000CCBF0408D4BF0408D4BF0408DCBF040824
+:10C0A000DCBF0408E4BF0408E4BF0408ECBF0408D4
+:10C0B000ECBF0408F4BF0408F4BF0408FCBF040884
+:10C0C000FCBF040804C0040804C004080CC0040831
+:10C0D0000CC0040814C0040814C004081CC00408E0
+:10C0E0001CC0040824C0040824C004082CC0040890
+:10C0F0002CC0040834C0040834C004083CC0040840
+:10C100003CC0040844C0040844C004084CC00408EF
+:10C110004CC0040854C0040854C004085CC004089F
+:10C120005CC0040864C0040864C004086CC004084F
+:10C130006CC0040874C0040874C004087CC00408FF
+:10C140007CC0040884C0040884C004088CC00408AF
+:10C150008CC0040894C0040894C004089CC004085F
+:10C160009CC00408A4C00408A4C00408ACC004080F
+:10C17000ACC00408B4C00408B4C00408BCC00408BF
+:10C18000BCC00408C4C00408C4C00408CCC004086F
+:10C19000CCC00408D4C00408D4C00408DCC004081F
+:10C1A000DCC00408E4C00408E4C00408ECC00408CF
+:10C1B000ECC00408F4C00408F4C00408FCC004087F
+:10C1C000FCC0040804C1040804C104080CC104082C
+:10C1D0000CC1040814C1040814C104081CC10408DB
+:10C1E0001CC1040824C1040824C104082CC104088B
+:10C1F0002CC1040834C1040834C104083CC104083B
+:10C200003CC1040844C1040844C104084CC10408EA
+:10C210004CC1040854C1040854C104085CC104089A
+:10C220005CC1040864C1040864C104086CC104084A
+:10C230006CC1040874C1040874C104087CC10408FA
+:10C240007CC1040884C1040884C104088CC10408AA
+:10C250008CC1040894C1040894C104089CC104085A
+:10C260009CC10408A4C10408A4C10408ACC104080A
+:10C27000ACC10408B4C10408B4C10408BCC10408BA
+:10C28000BCC10408C4C10408C4C10408CCC104086A
+:10C29000CCC10408D4C10408D4C10408DCC104081A
+:10C2A000DCC10408E4C10408E4C10408ECC10408CA
+:10C2B000ECC10408F4C10408F4C10408FCC104087A
+:10C2C000FCC1040804C2040804C204080CC2040827
+:10C2D0000CC2040814C2040814C204081CC20408D6
+:10C2E0001CC2040824C2040824C204082CC2040886
+:10C2F0002CC2040834C2040834C204083CC2040836
+:10C300003CC2040844C2040844C204084CC20408E5
+:10C310004CC2040854C2040854C204085CC2040895
+:10C320005CC2040864C2040864C204086CC2040845
+:10C330006CC2040874C2040874C204087CC20408F5
+:10C340007CC2040884C2040884C204088CC20408A5
+:10C350008CC2040894C2040894C204089CC2040855
+:10C360009CC2040843000000000000000000000020
+:10C3700000000000000000000000000000000000BD
+:10C38000000000004300000000000000000000006A
+:10C39000000000000000000000000000000000009D
+:10C3A000000000004300000000000000000000004A
+:10C3B000000000000000000000000000000000007D
+:10C3C000000000004300000000000000000000002A
+:10C3D000000000000000000000000000000000005D
+:10C3E000000000004300000000000000000000000A
+:10C3F000000000000000000000000000000000003D
+:10C4000000000000430000000000000000000000E9
+:10C41000000000000000000000000000000000001C
+:10C4200000000000430000000000000000000000C9
+:10C4300000000000000000000000000000000000FC
+:10C4400000000000F8C3000894BF000800000000CE
+:10C4500056730408207604087C7404087C7404086D
+:10C460007C7404087C7404087C7404087C740408DC
+:10C470007C7404087C7404087C7404087F7F7F7FCC
+:10C480007F7F7F7F7F7F7F7F7F7F00000100415321
+:10C4900043494900000000000000000000000000C7
+:10C4A00000000000000000000000000000004153F8
+:10C4B00043494900000000000000000000000000A7
+:10C4C000000000000000000000000000000000006C
+:10C4D000000000000000000000000000000000005C
+:10C4E000447804080000000000CB010840CA01089D
+:10C4F000A0CA0108000000000000000000000000C9
+:10C50000203C401800000000000000000000000077
+:10C51000000000000000000001000000000000001A
+:10C52000000000000000000000000000000000000B
+:10C5300000000000000000000000000000000000FB
+:10C5400000000000000000000000000000000000EB
+:10C5500000000000000000000000000000000000DB
+:10C5600000000000000000000000000000000000CB
+:10C5700000000000000000000000000000000000BB
+:10C5800000000000000000000000000000000000AB
+:10C59000000000000000000000000000000000009B
+:10C5A000000000000000000000000000000000008B
+:10C5B0006478040800000000000000008CDA010824
+:10C5C00074DC0108CCD6010858D701087CD80108D2
+:10C5D0000000001400000004000000000000000043
+:10C5E000000000000000000000000000000000004B
+:10C5F000000000000000000000000000000000003B
+:10C60000000000000000000000000000000000002A
+:10C61000000000000000000000000000000000001A
+:10C62000000000000000000000000000000000000A
+:10C6300000000000000000000000000000000000FA
+:10C6400000000000000000000000000000000000EA
+:10C65000000000000000000000000000BCD5010840
+:10C660000000001400000018203D401800000004E5
+:10C6700000000000000400000000010000010000B4
+:10C6800000000000000000000000000000000000AA
+:10C690007C780408E03C4018000000000000000026
+:10C6A000803C401800000000030000000000000073
+:10C6B000000000000000000000000000000000007A
+:10C6C0000000000020000000200000000200000028
+:10C6D0000008000001000000000000000000000051
+:10C6E0009078040800020100000000000000000033
+:10C6F000000000000000000000000000000000003A
+:10C70000A4780408003D401800000000000000006C
+:10C71000A03C4018000000000200000000000000E3
+:10C720000000000000000000000000000000000009
+:10C7300000000000200000002000000002000000B7
+:10C7400000080000010000000000000000000000E0
+:10C7500090780408000201000000000000000000C2
+:10C7600000000000000000000000000000000000C9
+:10C77000B87804080000000000000000B4070208B8
+:10C780000C020208D802020874030208DC04020842
+:10C79000000020180000160000000000000000004B
+:10C7A0000000000000000000000000000000000089
+:10C7B0000000000000000000000000000000000079
+:10C7C0000000000000000000000000000000000069
+:10C7D0000000000000000000000000000000000059
+:10C7E0000000000000000000000000000000000049
+:10C7F0000000000000000000000000000000000039
+:10C800000000000000000000000000000000000028
+:10C810000000000000000000000000000000000018
+:10C8200000000000603D4018010000000000000012
+:10C83000FF7F00000100000000800000FFFF0000FB
+:10C840000100000000000100FFFF060001000000E1
+:10C8500000000700FF7F0B000100000000800B00BC
+:10C86000FFFF15000020000078CC0408BCA20408DB
+:10C87000F478020802000000003000000000000010
+:10C8800079CC0408C8A204086C79020803000000EF
+:10C890000030000000000000010006000C00000055
+:10C8A00050100308145A0308F849030808530308F2
+:10C8B000020011000300000000000000B86503083A
+:10C8C00000000000000000000300FF000300000063
+:10C8D00000000000E8B202080000000000000000B4
+:10C8E000140002121010111111101001020408108E
+:10C8F000204040404040404048CB040848CB04081A
+:10C9000018AB040800000000000000000000000058
+:10C910003872030800000000000000000000000062
+:10C9200040C80408000000000000000040C80408DF
+:10C93000000000000000000040C8040800000000E3
+:10C9400000000000000000000000000000000000E7
+:10C9500000000000000000000000000000000000D7
+:10C9600000000000000000000000000000000000C7
+:10C9700000000000000000000000000000000000B7
+:10C9800000000000000000000000000000000000A7
+:10C990000000000000000000000000000000000097
+:10C9A0000000000000000000000000000000000087
+:10C9B0000000000000000000000000000000000077
+:10C9C0000000000000000000000000000000000067
+:10C9D0000000000000000000000000000000000057
+:10C9E000CCAB0408D0AB0408D8AB0408E0AB040817
+:10C9F000E8AB0408F0AB040828AF04082CAF040827
+:10CA000034AF040840AF040848AF040860AF04081E
+:10CA100000F0FFF0CAA08080B0000000000000001D
+:10CA2000E8F5030810F6030834F603088CF703084A
+:10CA300004F8030830F8030854F8030818F9030849
+:10CA4000000000006D656D324D0000000000000028
+:10CA50000000000000000080000000000000200036
+:10CA6000000020000000000064C9040888C9040810
+:10CA70006D656D314D0000000000000000000000F9
+:10CA80000000008000000000000010000000100006
+:10CA90000000000064C90408B4C904086D656D3560
+:10CAA00031324B0000000000000000000000008058
+:10CAB0000000000000000800000008000000000066
+:10CAC00064C90408E0C904086E756C6C00000000BD
+:10CAD00000000000000000000000208000000000B6
+:10CAE00000002000000020000000000064C90408CD
+:10CAF0002F00000000000000000000000000000007
+:10CB00000000000000000000000000000000000025
+:10CB10000000000000000000000000000000000015
+:10CB20000000000000000000000000000000000005
+:10CB300000000000000000000000000000000000F5
+:10CB400000000000000000000000000000000000E5
+:10CB500000000000000000000000000000000000D5
+:10CB600000000000000000000000000000000000C5
+:10CB700080BA040880BA0408FFFFFFFF000002002B
+:10CB8000C8CA0408C8CA04089CE50508FFFFFFFFDF
+:10CB9000FFFFFFFF5478040804000000E4CA040803
+:10CBA000E4CA0408ECCA0408ECCA0408F4CA04087D
+:10CBB000F4CA040860EA0000CC9B040802000000EC
+:10CBC0000200000098A404081E000000800000007D
+:10CBD0001E00000000060000FFFFFFFF3C000000F9
+:10CBE000001F03001E0000004038000096000000F7
+:10CBF000002000000020000040CB040840CB0408C7
+:10CC000040C8040840C80408FFFFFFFF0000000000
+:10CC1000FFFFFFFF5CCB04085CCB040824AB0408D7
+:10CC200048AB040864000000400000000100000060
+:10CC3000100000000100000004000000FCB7040820
+:0CCC400038CA0408000000003803000897
+:00000001FF
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.dat b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.dat
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym
new file mode 100644
index 0000000..d508ca2
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/hdl_sim/onchip_flash.sym
@@ -0,0 +1,1138 @@
+00000000 a OSTCBStkPtr_OFFSET
+00000014 a OSTCBNext_OFFSET
+00000032 a OSTCBPrio_OFFSET
+00000040 a OSCtxSw_SWITCH_PC
+08000000 A __alt_mem_ddr3_ram
+08000120 T alt_exception
+08000120 T alt_irq_entry
+080001fc T alt_irq_handler
+080002c4 T alt_instruction_exception_entry
+08000338 T _start
+0800037c t alt_after_alt_main
+08000380 T control_delay
+080003b0 T control_pong
+08000418 T control_process_snapshot
+08000478 T check_arp
+080004f8 T control_process_config_peer
+0800080c T control_get_header
+080008a4 T control_get_data
+08000950 T control_step
+08001064 T ControlTask
+080010f0 T control_init
+08001124 T InitialTask
+08001178 T main
+080011e8 T get_mac_addr
+0800123c T get_ip_addr
+08001434 T get_serial_number
+080015c8 T generate_and_store_mac_addr
+08001780 T generate_mac_addr
+080018b4 T get_board_mac_addr
+08001a54 T FindLastFlashSectorOffset
+08001b80 T sensor_command_bit
+08001c08 T sensor_preconfigure
+08001d1c T ss_reset_connection
+08001d58 T ss_initialize_connection
+08001da8 T ss_handle_accept
+08001e90 T SSListenerTask
+08002050 T ethernet_init
+080020d0 T ethernet_listen
+0800220c T ethernet_write
+08002314 T ethernet_read
+080024cc T ethernet_close
+08002554 T udpgen_command_bit
+080025dc T udpgen_test
+080027a8 T swap_bytes
+08002840 T swap_quad
+08002904 T reload_fpga
+08002944 T masterslave
+080029cc T master_clock_period
+08002a14 T master_clock_enable
+08002a70 T led_set
+08002abc T led_clear
+08002b08 T led_toggle
+08002b7c T led4_blink_enable
+08002bc8 T set_delay
+08002c30 T _getchar_r
+08002c38 T getchar
+08002c48 T _printf_r
+08002c78 T printf
+08002cb0 T _putchar_r
+08002cb8 T putchar
+08002cd0 T _puts_r
+08002d9c T puts
+08002dac T strlen
+08002e44 T ___vfprintf_internal_r
+08004fa4 T __vfprintf_internal
+08004fbc t __sbprintf
+0800507c T __swsetup_r
+080051dc t quorem
+080053ec T _dtoa_r
+08006ab4 T __sflush_r
+08006cdc T _fflush_r
+08006d3c T fflush
+08006d64 t __fp_lock
+08006d6c T _cleanup_r
+08006d78 t __sinit.part.0
+08006ee0 t __fp_unlock
+08006ee8 T __sfmoreglue
+08006f50 T __sfp
+0800704c T _cleanup
+08007060 T __sinit
+08007070 T __sfp_lock_acquire
+08007074 T __sfp_lock_release
+08007078 T __sinit_lock_acquire
+0800707c T __sinit_lock_release
+08007080 T __fp_lock_all
+08007094 T __fp_unlock_all
+080070a8 T _malloc_trim_r
+080071c4 T _free_r
+080074c0 T __sfvwrite_r
+08007984 T _fwalk
+08007a28 T _fwalk_reent
+08007adc T _getc_r
+08007b58 T getc
+08007be8 T __localeconv_l
+08007bf0 T _localeconv_r
+08007bfc T localeconv
+08007c08 T __swhatbuf_r
+08007ca0 T __smakebuf_r
+08007ddc T _malloc_r
+080085d0 T memchr
+080086b8 T memcpy
+080087b8 T memmove
+080088e4 T memset
+080089d4 T _Balloc
+08008a78 T _Bfree
+08008a9c T __multadd
+08008bb0 T __s2b
+08008cc0 T __hi0bits
+08008d24 T __lo0bits
+08008dd4 T __i2b
+08008e08 T __multiply
+08008ff4 T __pow5mult
+0800911c T __lshift
+08009258 T __mcmp
+080092b0 T __mdiff
+0800946c T __ulp
+080094c8 T __b2d
+080095cc T __d2b
+08009714 T __ratio
+080097bc T _mprec_log10
+08009830 T __copybits
+0800989c T __any_on
+08009910 T _putc_r
+080099dc T putc
+08009abc T _realloc_r
+0800a0e8 T __srget_r
+0800a15c T __srget
+0800a16c T _sbrk_r
+0800a1c4 T __sread
+0800a218 T __seofread
+0800a220 T __swrite
+0800a2a0 T __sseek
+0800a2fc T __sclose
+0800a304 t __sprint_r.part.0
+0800a3f8 T __sprint_r
+0800a410 T ___vfiprintf_internal_r
+0800b73c T __vfiprintf_internal
+0800b754 t __sbprintf
+0800b814 T __swbuf_r
+0800b95c T __swbuf
+0800b970 T _write_r
+0800b9d4 T _close_r
+0800ba2c T _calloc_r
+0800bae4 T _fclose_r
+0800bbdc T fclose
+0800bbec T __fputwc
+0800bd3c T _fputwc_r
+0800bd60 T fputwc
+0800bddc T _fstat_r
+0800be3c T _isatty_r
+0800be94 T _setlocale_r
+0800bf04 T __locale_mb_cur_max
+0800bf10 T setlocale
+0800bf24 T _lseek_r
+0800bf88 T _mbtowc_r
+0800bf94 T __ascii_mbtowc
+0800bfd8 T _read_r
+0800c03c t lflush
+0800c058 T __srefill_r
+0800c224 T strcmp
+0800c2fc T _wcrtomb_r
+0800c368 T wcrtomb
+0800c3ec T _wctomb_r
+0800c3f8 T __ascii_wctomb
+0800c428 T __udivdi3
+0800c9c0 T __umoddi3
+0800cf00 T __divsi3
+0800cf80 T __modsi3
+0800cff8 T __udivsi3
+0800d05c T __umodsi3
+0800d0b8 T __adddf3
+0800da58 T __divdf3
+0800e300 T __eqdf2
+0800e300 T __nedf2
+0800e380 T __gedf2
+0800e380 T __gtdf2
+0800e470 T __ledf2
+0800e470 T __ltdf2
+0800e560 T __muldf3
+0800ebec T __subdf3
+0800f558 T __unorddf2
+0800f5ac T __fixdfsi
+0800f62c T __floatsidf
+0800f6f4 T __floatunsidf
+0800f790 T __clzsi2
+0800f7e4 T alt_flash_open_dev
+0800f84c T alt_flash_close_dev
+0800f8a0 t alt_get_errno
+0800f8dc T fstat
+0800f98c t alt_get_errno
+0800f9c8 T isatty
+0800fa6c t alt_get_errno
+0800faa8 T lseek
+0800fb7c T alt_main
+0800fc38 T sbrk
+0800fce8 T __env_lock
+0800fdac T __env_unlock
+0800fe0c T __malloc_lock
+0800ff2c T __malloc_unlock
+0800fff8 T OSEventNameGet
+080100d0 T OSEventNameSet
+080101d0 T OSEventPendMulti
+0801077c T OSInit
+080107cc T OSIntEnter
+08010818 T OSIntExit
+08010908 T OSSchedLock
+08010994 T OSSchedUnlock
+08010a70 T OSStart
+08010ad8 T OSTimeTick
+08010c98 T OSVersion
+08010cb8 T OS_Dummy
+08010cd8 T OS_EventTaskRdy
+08010e60 T OS_EventTaskWait
+08010f68 T OS_EventTaskWaitMulti
+080110b0 T OS_EventTaskRemove
+08011160 T OS_EventTaskRemoveMulti
+08011258 T OS_EventWaitListInit
+080112c0 t OS_InitEventList
+080113a0 t OS_InitMisc
+080113dc t OS_InitRdyList
+08011448 t OS_InitTaskIdle
+080114cc t OS_InitTCBList
+080115b0 T OS_MemClr
+08011604 T OS_MemCopy
+0801166c T OS_Sched
+08011734 t OS_SchedNew
+080117a0 T OS_StrCopy
+08011814 T OS_StrLen
+08011868 T OS_TaskIdle
+080118c4 T OS_TCBInit
+08011b98 T OSFlagAccept
+08011e78 T OSFlagCreate
+08011f70 T OSFlagDel
+0801218c T OSFlagNameGet
+0801226c T OSFlagNameSet
+08012378 T OSFlagPend
+08012910 T OSFlagPendGetFlagsRdy
+08012970 T OSFlagPost
+08012cdc T OSFlagQuery
+08012d74 t OS_FlagBlock
+08012ed8 T OS_FlagInit
+08012fb8 t OS_FlagTaskRdy
+080130ac T OS_FlagUnlink
+08013150 T OSMemCreate
+08013298 T OSMemGet
+0801335c T OSMemNameGet
+08013404 T OSMemNameSet
+080134d8 T OSMemPut
+08013590 T OSMemQuery
+08013658 T OS_MemInit
+08013724 T OSMutexAccept
+0801389c T OSMutexCreate
+08013a1c T OSMutexDel
+08013cdc T OSMutexPend
+08014238 T OSMutexPost
+08014430 T OSMutexQuery
+0801457c t OSMutex_RdyAtPrio
+08014704 T OSQAccept
+08014818 T OSQCreate
+080149bc T OSQDel
+08014c10 T OSQFlush
+08014c9c T OSQPend
+08014efc T OSQPendAbort
+0801503c T OSQPost
+08015194 T OSQPostFront
+080152f4 T OSQPostOpt
+080154f0 T OSQQuery
+0801562c T OS_QInit
+080156d4 T OSSemAccept
+08015774 T OSSemCreate
+0801584c T OSSemDel
+08015a60 T OSSemPend
+08015c44 T OSSemPendAbort
+08015d84 T OSSemPost
+08015e84 T OSSemQuery
+08015f74 T OSSemSet
+0801604c T OSTaskChangePrio
+080164cc T OSTaskCreate
+0801664c T OSTaskCreateExt
+080167f0 T OSTaskDel
+08016b04 T OSTaskDelReq
+08016c2c T OSTaskNameGet
+08016d64 T OSTaskNameSet
+08016ec0 T OSTaskResume
+08017078 T OSTaskSuspend
+08017220 T OSTaskQuery
+0801730c T OSTimeDly
+08017410 T OSTimeDlyHMSM
+0801750c T OSTimeDlyResume
+080176d8 T OSTimeGet
+08017734 T OSTimeSet
+08017794 t alt_dev_reg
+080177c8 T alt_irq_init
+08017800 T alt_sys_init
+08017a2c t alt_avalon_timer_sc_irq
+08017aa4 T alt_avalon_timer_sc_init
+08017b20 T no_printf
+08017b50 T tse_mac_initTransInfo2
+08017bb0 T tse_mac_sTxWrite
+08017c78 T tse_mac_aRxRead
+08017ce8 T tse_mac_aTxWrite
+08017d58 T tse_mac_SwReset
+08017de0 T tse_mac_setMIImode
+08017e34 T tse_mac_setGMIImode
+08017e84 T alt_tse_phy_add_profile
+08018038 T alt_tse_system_add_sys
+080188fc T alt_tse_sys_enable_mdio_sharing
+08018a40 T alt_tse_mac_get_common_speed
+08018a80 T alt_tse_mac_set_common_speed
+08018ac8 T alt_tse_get_system_index
+08018b34 T alt_tse_get_mac_group_index
+08018ba0 T alt_tse_get_mac_info_index
+08018c1c T alt_tse_get_mac_info
+08018ce8 T alt_tse_mac_set_speed
+08018dc8 T alt_tse_mac_set_duplex
+08018e54 T getPHYSpeed
+080198cc T alt_tse_phy_rd_mdio_addr
+08019914 T alt_tse_phy_wr_mdio_addr
+0801996c T alt_tse_phy_wr_mdio_reg
+08019a98 T alt_tse_phy_rd_mdio_reg
+08019b68 T alt_tse_phy_add_profile_default
+08019e30 T alt_tse_phy_print_profile
+0801a000 T alt_tse_mac_group_init
+0801a698 T alt_tse_mac_get_phy
+0801aaa4 T alt_tse_mac_associate_phy
+0801ace4 T alt_tse_phy_cfg_pcs
+0801ae0c T alt_tse_phy_init
+0801af18 T alt_tse_phy_restart_an
+0801b0dc T alt_tse_phy_check_link
+0801b264 T alt_tse_phy_get_cap
+0801b7f0 T alt_tse_phy_set_adv_1000
+0801b9b4 T alt_tse_phy_set_adv_100
+0801bc08 T alt_tse_phy_set_adv_10
+0801bdb0 T alt_tse_phy_get_common_speed
+0801c0cc T alt_tse_phy_set_common_speed
+0801c57c T marvell_phy_cfg
+0801c614 T marvell_cfg_gmii
+0801c6f8 T marvell_cfg_sgmii
+0801c7dc T marvell_cfg_rgmii
+0801c8cc T DP83848C_link_status_read
+0801c944 T PEF7071_config
+0801c9a0 T PEF7071_link_status_read
+0801ca40 T altera_avalon_uart_read_fd
+0801caa0 T altera_avalon_uart_write_fd
+0801cb00 T altera_avalon_uart_close_fd
+0801cb50 T altera_avalon_uart_init
+0801ccb0 t altera_avalon_uart_irq
+0801cd4c t altera_avalon_uart_rxirq
+0801ce80 t altera_avalon_uart_txirq
+0801d020 T altera_avalon_uart_close
+0801d074 t alt_get_errno
+0801d0b0 T altera_avalon_uart_read
+0801d318 t alt_get_errno
+0801d354 T altera_avalon_uart_write
+0801d588 t alt_flash_device_register
+0801d5bc T alt_qspi_controller_lock
+0801d6cc T alt_qspi_controller_get_info
+0801d758 T alt_qspi_controller_erase_block
+0801d87c T alt_qspi_controller_write_block
+0801da8c T alt_qspi_controller_write
+0801dc74 T alt_qspi_controller_read
+0801dd20 T altera_qspi_controller_init
+0801df74 t alt_qspi_validate_read_write_arguments
+0801e010 t alt_qspi_poll_for_write_in_progress
+0801e09c t alt_get_errno
+0801e0d8 t alt_msgdma_write_standard_descriptor
+0801e16c t alt_msgdma_write_extended_descriptor
+0801e298 t alt_msgdma_irq
+0801e41c t alt_msgdma_construct_standard_descriptor
+0801e4a8 t alt_msgdma_construct_extended_descriptor
+0801e5fc t alt_msgdma_descriptor_async_transfer
+0801e938 t alt_msgdma_descriptor_sync_transfer
+0801ed40 T alt_msgdma_construct_standard_st_to_mm_descriptor
+0801ed98 T alt_msgdma_construct_standard_mm_to_st_descriptor
+0801edf0 T alt_msgdma_construct_standard_mm_to_mm_descriptor
+0801ee48 T alt_msgdma_construct_extended_st_to_mm_descriptor
+0801eed8 T alt_msgdma_construct_extended_mm_to_st_descriptor
+0801ef68 T alt_msgdma_construct_extended_mm_to_mm_descriptor
+0801f010 t alt_msgdma_construct_prefetcher_standard_descriptor
+0801f0b4 t alt_msgdma_construct_prefetcher_extended_descriptor
+0801f248 T alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
+0801f2a0 T alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
+0801f2f8 T alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
+0801f350 T alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
+0801f3f0 T alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
+0801f488 T alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
+0801f540 T alt_msgdma_prefetcher_add_standard_desc_to_list
+0801f630 T alt_msgdma_prefetcher_add_extended_desc_to_list
+0801f7c8 T alt_msgdma_prefetcher_set_std_list_own_by_hw_bits
+0801f8d8 T alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits
+0801fa24 T alt_msgdma_start_prefetcher_with_list_addr
+0801fd34 T alt_msgdma_start_prefetcher_with_std_desc_list
+0801fde4 T alt_msgdma_start_prefetcher_with_extd_desc_list
+0801fe94 T alt_msgdma_open
+0801feec T alt_msgdma_init
+08020094 T alt_msgdma_register_callback
+080200e8 T alt_msgdma_standard_descriptor_async_transfer
+08020124 T alt_msgdma_extended_descriptor_async_transfer
+08020160 T alt_msgdma_standard_descriptor_sync_transfer
+0802019c T alt_msgdma_extended_descriptor_sync_transfer
+080201d8 t alt_flash_device_register
+0802020c T alt_onchip_flash_read
+080202d8 T alt_onchip_flash_get_info
+08020374 T alt_onchip_flash_erase_block
+080204dc T alt_onchip_flash_write_block
+080207b4 T alt_onchip_flash_write
+08020a80 T altera_onchip_flash_init
+08020f20 T alt_onchip_flash_poll_for_status_to_go_idle
+08020fb0 T alt_onchip_flash_poll_for_status_erase_passed
+08021044 T alt_onchip_flash_poll_for_status_write_passed
+080210d8 T altera_eth_tse_init
+08021220 T prep_tse_mac
+0802144c T msgdma_reset
+080214c4 T tse_mac_init
+08021f28 T tse_msgdma_write_init
+08022048 T tse_mac_raw_send
+08022210 T tse_msgdmaRx_isr
+080223a8 T tse_msgdmaTx_isr
+08022408 T tse_msgdma_read_init
+080226c0 T allocate_rx_descriptor_chain
+080227f8 T tse_mac_rcv
+08022944 T tse_mac_stats
+08022984 T tse_mac_close
+08022a60 T close
+08022aa8 T iniche_devices_init
+08022bcc T read
+08022c3c T write
+08022ca4 T etainit
+08022cec T et_send
+08022e6c T arp_free_pending
+08022ef4 T arp_send_pending
+08022f68 T send_arp
+080233bc T find_oldest_arp
+08023528 T make_arp_entry
+08023624 T arpReply
+080238e4 T arprcv
+08023b48 T send_via_arp
+08023cc4 T cb_arpent_tmo
+08023dd0 T grat_arp
+08024088 T if_getbynum
+080240f4 T isbcast
+080241c8 T reg_type
+08024254 T if_killsocks
+080242e4 T Netinit
+080247b4 T fixup_subnet_mask
+080248e4 T netclose
+080249c4 T pktdemux
+08024d64 T c_older
+08024df4 T ip2mac
+08024f80 T ip_startup
+080251e4 T exit_hook
+0802524c T ip_exit
+080252fc T if_netnumber
+0802537c T igmp_init
+0802541c T igmp_input
+080254ec T igmp_fasttimo
+0802565c T igmp_send
+080258d8 T igmp_joingroup
+08025b04 T igmp_leavegroup
+08025b84 T igmp_validate
+08025e60 T igmp_print_stats
+08026214 T bsd_accept
+08026334 T bsd_getpeername
+08026454 T bsd_getsockname
+08026574 T bsd_i_sockoptlen
+08026704 T bsd_getsockopt
+0802680c T bsd_ioctl
+080268fc T bsd_inet_ntoa
+08026930 T bsd_recvfrom
+08026a74 T bsd_select
+08026bfc T bsd_setsockopt
+08026cd8 T ccksum
+08026d7c T cksum
+08026dd0 T do_trap
+08026dfc T nextarg
+08026e78 T hexdump
+08026fbc T print_ipad
+08027038 T print_uptime
+08027178 T panic
+080271c0 T print_eth
+08027314 T uslash
+08027390 T ns_printf
+08027500 T std_out
+08027544 T con_page
+0802761c T parse_args
+08027814 T netmain
+080278f4 T tk_netmain
+0802796c T tk_nettick
+080279b0 T TK_OSTimeDly
+080279e0 T TK_OSTaskResume
+08027a54 T tcp_sleep
+08027ba0 T tcp_wakeup
+08027c78 T TK_OSTaskQuery
+08027ce4 T tk_yield
+08027d14 T tk_stats
+08027f0c T icmpEcho
+080281a8 T pk_init
+08028434 T pk_alloc
+080284f4 T pk_validate
+08028748 T pk_free
+080287f4 T pk_get_max_intrsafe_buf_len
+08028814 T dump_buf_estats
+080288d8 T getq
+08028990 T putq
+08028a40 T qdel
+08028b40 T asm_cksum
+08028b60 t asm1
+08028b88 t loop
+08028c8c t loop0
+08028ca8 t fold
+08028cd0 t done
+08028cd4 T dtrap
+08028d08 T kbhit
+08028d90 T getch
+08028de0 T clock_init
+08028e18 T clock_c
+08028e38 T cticks_hook
+08028e94 T irq_Mask
+08028ef4 T irq_Unmask
+08028f38 T LOCK_NET_RESOURCE
+08028ff4 T UNLOCK_NET_RESOURCE
+08029074 T TK_NEWTASK
+080292b4 T wait_app_sem
+08029368 T post_app_sem
+080293dc T alt_iniche_init
+0802959c T pre_task_setup
+080295e8 T post_task_setup
+08029608 T prep_armintcp
+08029640 T npalloc_base
+0802974c T npfree_base
+0802982c T npalloc
+08029860 T npfree
+080298a0 T ncpalloc
+080298d4 T ncpfree
+08029914 T pffindtype
+080299a4 T pffindproto
+08029a70 T m_getnbuf
+08029bf8 T m_free
+08029cfc T m_freem
+08029d40 T m_copy
+0802a018 T m_adj
+0802a1d8 T mbuf_len
+0802a22c T dtom
+0802a2c4 T remque
+0802a334 T insque
+0802a3b0 T nptcp_init
+0802a4a4 T tcp_rcv
+0802a658 T ip_output
+0802abe0 T in_broadcast
+0802ac18 T np_stripoptions
+0802ad08 T so_icmpdu
+0802b050 T tcp_tick
+0802b0c8 T rawip_lookup
+0802b124 T rawip_soinput
+0802b2e8 T rawip_usrreq
+0802ba20 T DOMAIN_CHECK
+0802ba70 T t_socket
+0802baf0 T t_bind
+0802bc50 T t_listen
+0802bd24 T t_accept
+0802bf74 T t_connect
+0802c1e4 T t_getpeername
+0802c228 T t_getsockname
+0802c26c t t_getname
+0802c44c T t_setsockopt
+0802c60c T t_getsockopt
+0802c794 T t_recv
+0802c870 T t_recvfrom
+0802c9ac T t_sendto
+0802cb9c T t_send
+0802cd9c T t_shutdown
+0802ce70 T t_socketclose
+0802cf30 t sockargs
+0802cfbc T t_errno
+0802d050 T socreate
+0802d1f8 T sobind
+0802d254 T solisten
+0802d324 T sofree
+0802d434 T soclose
+0802d6fc T soabort
+0802d74c T soaccept
+0802d7e4 T soconnect
+0802d89c T sodisconnect
+0802d934 T sosend
+0802de94 T soreceive
+0802e5ec T soshutdown
+0802e684 T sorflush
+0802e780 T sosetopt
+0802ec0c T sogetopt
+0802f12c T sohasoutofband
+0802f178 T soisconnecting
+0802f1e8 T soisconnected
+0802f2ec T soisdisconnecting
+0802f384 T soisdisconnected
+0802f448 T sonewconn
+0802f640 T soqinsque
+0802f6ec T soqremque
+0802f7f4 T socantsendmore
+0802f84c T socantrcvmore
+0802f8a4 T sbselqueue
+0802f8e0 T sbwait
+0802f94c T sbwakeup
+0802f9d8 T soreserve
+0802fa60 T sbreserve
+0802fab0 T sbrelease
+0802fafc T sbappend
+0802fb9c T sbappendrecord
+0802fc74 T sbappendaddr
+0802fe50 T sbcompress
+0803002c T sbflush
+080300b0 T sbdrop
+08030268 T sbdropend
+08030368 T sbdroprecord
+080303f8 T t_select
+080305c8 T sock_selscan
+08030708 T sock_select
+080308f0 T in_pcbnotify
+080309b4 T tcp_notify
+08030a34 T ifd_clr
+08030b18 T ifd_set
+08030b8c T ifd_isset
+08030c00 T ifd_get
+08030c60 T tcp_reass
+08031050 T tcp_input
+08033264 T tcp_dooptions
+080333ec T tcp_pulloutofband
+08033518 T tcp_xmit_timer
+08033754 T ip4_tcpmss
+0803379c T tcp_mss
+08033894 T tcp_output
+08034830 T tcp_setpersist
+0803492c t bld_options
+080349f8 T tcp_init
+08034a40 T tcp_template
+08034b48 T tcp_respond
+08034f40 T tcp_newtcpcb
+0803504c T tcp_drop
+080350e8 T tcp_close
+080351d0 T tcp_quench
+0803521c T tcp_putseq
+08035294 T tcp_getseq
+08035308 T tcp_slowtimo
+08035564 T tcp_canceltimers
+080355c0 T tcp_timers
+08035a14 T tcp_usrreq
+080360cc T tcp_attach
+080361e4 T tcp_disconnect
+080362b0 T tcp_usrclosed
+0803637c T tcpinit
+080363bc T udp_lookup
+08036418 T udp_soinput
+080365b8 T udp_usrreq
+080367f0 T udp4_sockbind
+08036ac0 T udp4_socksend
+08036e34 T udp4_sockaddr
+08036f5c T alt_busy_sleep
+080370b4 t alt_get_errno
+080370f0 T alt_close
+080371c0 T alt_dcache_flush
+08037238 t alt_dev_null_write
+08037264 t alt_get_errno
+080372a0 T alt_dev_llist_insert
+08037344 T _do_ctors
+080373a4 T _do_dtors
+08037404 T alt_find_dev
+08037494 T alt_ic_isr_register
+080374e4 T alt_ic_irq_enable
+0803756c T alt_ic_irq_disable
+080375f8 T alt_ic_irq_enabled
+08037644 T alt_iic_isr_register
+08037728 t alt_open_fd
+080377d8 T alt_io_redirect
+08037854 t alt_get_errno
+08037890 t alt_file_locked
+08037948 T open
+08037a9c T alt_printf
+08037cc8 T alt_putchar
+08037cf8 t alt_get_errno
+08037d34 T alt_read
+08037e30 T alt_release_fd
+08037e88 T alt_remap_cached
+08037ebc T alt_alarm_stop
+08037f58 T alt_tick
+08038060 T alt_uncached_free
+080380a4 T alt_uncached_malloc
+0803811c T usleep
+08038230 t alt_get_errno
+0803826c T alt_write
+08038364 T altera_nios2_gen2_irq_init
+08038388 T OSCtxSw
+08038388 T OSIntCtxSw
+08038414 T OSStartHighRdy
+08038434 T OSStartTsk
+08038458 T OSTaskStkInit
+080385a4 T OSTaskCreateHook
+080385c8 T OSTaskDelHook
+080385ec T OSTaskSwHook
+0803860c T OSTaskStatHook
+0803862c T OSTimeTickHook
+08038658 T OSInitHookBegin
+08038678 T OSInitHookEnd
+08038698 T OSTaskIdleHook
+080386b8 T OSTCBInitHook
+080386dc T netmain_init
+080387c4 T icmp_port_du
+08038850 T station_state
+080389b0 T sysuptime
+080389e8 T packet_check
+08038a38 T mcastlist
+08038a5c T prep_modules
+08038ab0 T inet_timer
+08038b28 t check_interval_timers
+08038c74 T in_timerset
+08038da0 T in_timerkill
+08038e38 T create_apptasks
+08038e5c T task_stats
+08038ed8 T fcntl
+08038f78 T icmprcv
+08039a54 T icmp_destun
+08039d2c T icmp_timex
+0803a01c T icmp_du
+0803a070 T ip_init
+0803a148 T ip_bldhead
+0803a2d4 T ip_write_internal
+0803a9e8 T ip_write
+0803abf8 T ip_write2
+0803af6c T ip_raw_write
+0803b028 T ip_mymach
+0803b0cc T ip_dump
+0803b370 T iproute
+0803b53c T ip_copypkt
+0803b668 T ip_rcv
+0803b9bc T ip_rcv_phase2
+0803bf08 T ip_demux
+0803c2ac T in_addmulti
+0803c3f8 T in_delmulti
+0803c504 T lookup_mcast
+0803c568 T prep_ifaces
+0803c5e8 T netexit
+0803c610 T evtmap_setup
+0803c63c T ip_raw_open
+0803c714 T ip_raw_close
+0803c7d0 T ip_raw_input
+0803c9e4 T ip_raw_alloc
+0803ca9c T ip_raw_free
+0803cae0 T ip_raw_maxalloc
+0803cb28 T rt_lookup
+0803cc7c T add_route
+0803d020 T del_route
+0803d134 T udpdemux
+0803d8a0 T udp_send
+0803db34 T udpswap
+0803dc28 T udp_socket
+0803dcd8 T udp_alloc
+0803dd94 T udp_maxalloc
+0803ddb8 T udp_free
+0803ddfc T igmpv1_input
+0803e064 T igmpv2_input
+0803e170 T igmpv2_process_report
+0803e284 T igmpv2_process_query
+0803e444 T igmpv2_chk_set_timer
+0803e574 T igmpv2_chk4_rtr_alert_opt
+0803e6b0 T IPADDR_TO_NETP
+0803e7c4 T ip_setmoptions
+0803ed64 T ip_getmoptions
+0803ee74 T ip_freemoptions
+0803eef8 T u_mctest_init
+0803ef2c T u_mctest_run
+0803f598 T init_memdev
+0803f5e8 T md_fopen
+0803f610 T md_fclose
+0803f634 T md_fread
+0803f78c T md_fwrite
+0803f804 T md_fseek
+0803f830 T md_ftell
+0803f854 T md_fgetc
+0803f918 T md_unlink
+0803f93c T parse_ipad
+0803fc38 T inet_addr
+0803fc9c T hextoa
+0803fce8 T inet_pton
+0803fd7c T inet_ntop
+0803fe00 T print46_addr
+0803fe5c T inet46_addr
+0803ff20 T inet_setport
+0803ff8c T convert_ip
+080400c0 T tcp_cksum
+08040254 T udp_open
+08040454 T udp_close
+0804052c T in_pcballoc
+080405b4 T in_pcbdetach
+0804060c T in_pcbbind
+0804081c T in_pcbconnect
+080409fc T in_pcbdisconnect
+08040a58 T in_setsockaddr
+08040adc T in_setpeeraddr
+08040b60 T in_pcblookup
+08040db4 T set_vfopen_error
+08040de0 T get_vfopen_error
+08040e00 T vf_alloc_and_link_vop
+08040e70 T vf_alloc_buffer
+08040f38 T vf_free_buffer
+08040f88 T vfopen_locked
+080412c0 T vfopen
+08041310 T vfclose_locked
+080414cc T vfclose
+08041510 T vfflush
+08041558 T vfgets
+08041628 T vfeof
+08041678 T vunlink_flag_open_files
+080416d4 T vunlink
+080418d4 T vfread
+08041a5c T vfwrite_locked
+08041e08 T vfwrite
+08041e68 T vfseek
+08041fbc T vftell
+080420c8 T vgetc_locked
+080421c0 T vgetc
+08042208 T vfslookup_locked
+0804232c T vfslookup
+08042374 T strippath
+08042540 T isvfile_locked
+08042598 T isvfile
+080425e0 T vferror
+0804263c T vclearerr
+08042694 T prep_vfs
+080426b8 t alt_get_errno
+080426f4 T alt_fcntl
+08042818 T alt_find_file
+08042920 T alt_get_fd
+080429f8 T alt_exception_cause_generated_bad_addr
+08042a90 T atexit
+08042aa4 T atoi
+08042ab0 T _atoi_r
+08042abc T exit
+08042af0 T memalign
+08042b04 T _memalign_r
+08042c98 T malloc
+08042ca8 T free
+08042cb8 T memcmp
+08042d44 T _sprintf_r
+08042d98 T sprintf
+08042dfc T strchr
+08042f60 T strcpy
+08042fec T strncmp
+080430e8 t _strtol_l.isra.0
+0804330c T _strtol_r
+08043310 T strtol_l
+08043328 T strtol
+08043340 T ___svfprintf_internal_r
+08045458 T vprintf
+08045474 T _vprintf_r
+08045484 T _vsprintf_r
+080454d0 T vsprintf
+080454e8 T __register_exitproc
+08045578 T __call_exitprocs
+08045690 T __ssprint_r
+08045850 T ___svfiprintf_internal_r
+08046970 T _vfprintf_r
+08046974 T _exit
+080469a8 A __CTOR_END__
+080469a8 A __CTOR_LIST__
+080469a8 A __DTOR_END__
+080469a8 A __DTOR_LIST__
+080471d6 R _ctype_
+080472d7 R _ctype_b
+0804749e r zeroes.5227
+080474ae r blanks.5226
+080474d0 r p05.4024
+080474dc R __mprec_tinytens
+08047504 R __mprec_bigtens
+0804752c R __mprec_tens
+080475f4 r zeroes.5204
+08047604 r blanks.5203
+08047624 R __clz_tab
+08047734 R OSUnMapTbl
+0804b8d1 r zeroes.5208
+0804b8e1 r blanks.5207
+0804b8f1 r zeroes.5188
+0804b901 r blanks.5187
+0804b920 G controltask
+0804b938 G sslistenertask
+0804b950 G tse_mac_device
+0804ba80 g impure_data
+0804bea4 G __malloc_av_
+0804c2ac G __global_locale
+0804c420 g debug_uart
+0804c4f0 g ext_flash
+0804c5d0 g msgdma_rx
+0804c640 g msgdma_tx
+0804c6b0 g onchip_flash
+0804c7b0 G nettasks
+0804c7e0 G tcp_protosw
+0804c7f8 G udp_protosw
+0804c810 G rawip_protosw
+0804c828 G tcp_outflags
+0804c833 G tcp_backoff
+0804c840 G alt_dev_null
+0804c868 G alt_fd_list
+0804c928 G icmpdu_types
+0804c940 g dsts
+0804c958 G rtp_priority
+0804c964 G mdio
+0804c988 G mdlist
+0804ca38 G vfs_root_path
+0804cab8 G _global_impure_ptr
+0804cabc G _impure_ptr
+0804cac0 G __malloc_sbrk_base
+0804cac4 G __malloc_trim_threshold
+0804cac8 G alt_flash_dev_list
+0804cad0 g heap_end
+0804cad4 g lockid
+0804cad8 g lockid
+0804cadc G eth_tse_name
+0804cae0 G max_mac_system
+0804cae4 G alt_msgdma_list
+0804caec G altera_onchip_flash_list
+0804caf4 G alt_iniche_dev_list
+0804cafc G arp_ageout
+0804cb00 G ipmcfail_str
+0804cb04 g cksum_select
+0804cb08 G num_net_tasks
+0804cb0c G pingdata
+0804cb10 G lilbufs
+0804cb14 G lilbufsiz
+0804cb18 G bigbufs
+0804cb1c G bigbufsiz
+0804cb20 G kb_last
+0804cb24 G TCPTV_MSL
+0804cb28 G socket_defaults
+0804cb2a G tcprexmtthresh
+0804cb2c G tcp_ttl
+0804cb30 G tcp_keepidle
+0804cb34 G tcp_keepintvl
+0804cb38 G tcp_sendspace
+0804cb3c G tcp_recvspace
+0804cb40 G alt_fs_list
+0804cb48 G alt_dev_list
+0804cb50 G alt_max_fd
+0804cb54 G alt_errno
+0804cb58 G alt_priority_mask
+0804cb5c G alt_alarm_list
+0804cb64 G name
+0804cb68 G prompt
+0804cb6c G pingdelay
+0804cb70 G deflength
+0804cb74 g uid
+0804cb78 G ipRoutes
+0804cb7c g iCounter.5304
+0804cb80 G mdlist_size
+0804cb84 G pton_error
+0804cb88 G http_root_path
+0804cb8c A __bss_start
+0804cb8c A _edata
+0804cb8c b bytes_received.5850
+0804cb90 b header.5849
+0804cb98 b bytes_received.5856
+0804cb9c B to_controltask
+0804cba0 B last_flash_sector_offset
+0804cba4 B last_flash_sector
+0804cba8 b mutex
+0804cbac B to_sslistenertask
+0804cbae B mastermode
+0804cbb0 B delays
+0804cbb4 B __malloc_max_total_mem
+0804cbb8 B __malloc_max_sbrked_mem
+0804cbbc B __malloc_top_pad
+0804cbc0 B errno
+0804cbc4 B _PathLocale
+0804cbc8 B alt_argc
+0804cbcc B alt_argv
+0804cbd0 B alt_envp
+0804cbd4 b locks
+0804cbd8 B alt_envsem
+0804cbdc b locks
+0804cbe0 B alt_heapsem
+0804cbe4 B OSLockNesting
+0804cbe5 B OSRunning
+0804cbe8 B OSIdleCtr
+0804cbec B OSPrioHighRdy
+0804cbed B OSPrioCur
+0804cbf0 B OSTCBList
+0804cbf4 B OSCtxSwCtr
+0804cbf8 B OSTCBFreeList
+0804cbfc B OSTaskCtr
+0804cc00 B OSMemFreeList
+0804cc04 B OSTCBHighRdy
+0804cc08 B OSQFreeList
+0804cc0c B OSRdyGrp
+0804cc0d B OSRdyTbl
+0804cc10 B OSEventFreeList
+0804cc14 B OSIntNesting
+0804cc18 B OSTCBCur
+0804cc1c B OSTime
+0804cc20 B OSFlagFreeList
+0804cc24 B phy_profile_count
+0804cc25 B mac_group_count
+0804cc26 b tse_system_count.5331
+0804cc27 b is_init.5413
+0804cc28 B number_of_tse_mac
+0804cc2c b arp_timer
+0804cc30 B arpcache
+0804cc34 b cachetime
+0804cc38 B arpReqsIn
+0804cc3c B arpReqsOut
+0804cc40 B arpRepsIn
+0804cc44 B arpRepsOut
+0804cc48 B MaxLnh
+0804cc4c B MaxMtu
+0804cc50 B NDEBUG
+0804cc54 B ifNumber
+0804cc58 b nclosers
+0804cc5c B igmp_timers_are_running
+0804cc60 B igmp_cticks
+0804cc64 B igmp_all_hosts_group
+0804cc68 B igmp_all_rtrs_group
+0804cc6c B netmain_wakes
+0804cc70 B nettick_wakes
+0804cc74 B iniche_net_ready
+0804cc78 B to_netmain
+0804cc79 B to_nettick
+0804cc7c B tcp_sleep_timeout
+0804cc80 B cticks_initialized
+0804cc84 B irq_level
+0804cc88 b cpu_statusreg
+0804cc8c b kbd_init.4507
+0804cc90 B cticks_factor
+0804cc94 B OS_TPS
+0804cc98 B tcp_sleep_count
+0804cc9c B tcp_wakeup_count
+0804cca0 B netq_intmask
+0804cca4 B old_mode
+0804cca8 B global_TCPwakeup_setIndx
+0804ccac B cticks
+0804ccb0 B memtrapsize
+0804ccb4 B mheap_sem_ptr
+0804ccb8 B rcvdq_sem_ptr
+0804ccbc B nextslow
+0804ccc0 b in_tcptick
+0804ccc4 B mbstat
+0804cccc B select_wait
+0804ccd0 B tcpprintfs
+0804ccd4 B dropline
+0804ccd8 B tcp_optionbuf
+0804ccdc B tcp_maxidle
+0804cce0 B tcp_iss
+0804cce4 B alt_fd_list_lock
+0804cce8 B alt_irq_active
+0804ccec B _alt_tick_rate
+0804ccf0 B _alt_nticks
+0804ccf4 B activehost
+0804ccf8 b inside_pktdemux
+0804ccfc B nextppp
+0804cd00 B port_1s_callout
+0804cd04 b numtimers
+0804cd08 B icmpdu_hook
+0804cd0c B rt_mib
+0804cd10 B port_prep
+0804cd14 B net_system_exit
+0804cd18 B so_evtmap_create
+0804cd1c B so_evtmap_delete
+0804cd20 B so_evtmap
+0804cd24 B ipraw_eps
+0804cd28 B cachedRoute
+0804cd2c b usocket
+0804cd30 B firstudp
+0804cd34 B inpcb_cachehits
+0804cd38 B inpcb_cachemiss
+0804cd3c B vfsystems
+0804cd40 B vfiles
+0804cd44 B vfsfiles
+0804cd48 B vfopen_error
+0804cd4c B vfs_dir_stale
+0804cd50 B vfs_open_files
+0804cd54 B vfs_total_rw_space
+0804cd58 B vfs_total_dyna_files
+0804cd5c B alt_instruction_exception_handler
+0804cd60 b packet_data.5855
+0804cd80 b connections
+0804cd90 B __malloc_current_mallinfo
+0804cdb8 b closers
+0804cdf4 b tistring
+0804ce0c b nearBuf.4931
+0804ce2c B InitialTaskStk
+08054ab8 A _gp
+0805ae2c B OSFlagTbl
+0805b19c B OSMemTbl
+0805bdcc B OSQTbl
+0805bfac B OSTaskIdleStk
+0805c7ac B OSEventTbl
+0805d2ec B OSTCBTbl
+0805d574 B OSTCBPrioTbl
+0805d5c8 B eth_tse_if
+0805d6a8 B pmac_groups
+0805d6b8 B pphy_profiles
+0805d6d8 B tse_iniche_dev_driver_data
+0805d708 B tse
+0805d998 B arp_table
+0805da98 B netlist
+0805daac B rcvdq
+0805dac0 B netstatic
+0805ddc0 B nets
+0805ddd0 B igmpstats
+0805de34 B eth_prt_buf
+0805de46 B ipreturn
+0805de58 B lilfreeq
+0805de6c B memestats
+0805de7c B pktlog
+0805df6c B bigfreeq
+0805df80 B global_tcb_ext
+0805e07c B global_TCPwakeup_set
+0805e16c B resid_semaphore
+0805e1ac B app_semaphore
+0805e1c4 B soq
+0805e1d8 B tcpmib
+0805e214 B mbufq
+0805e228 B mfreeq
+0805e23c B tcp_saveti
+0805e264 B tcb
+0805e290 B tcpstat
+0805e370 B alt_irq
+0805e470 B intimers
+0805e4d4 B icmp_mib
+0805e53c B ip_mib
+0805e58c B udp_mib
+0805e59c A __alt_heap_start
+0805e59c A __alt_stack_base
+0805e59c A __bss_end
+0805e59c A _end
+0805e59c A end
+10000000 A __alt_data_end
+10000000 A __alt_heap_limit
+10000000 A __alt_stack_pointer
+14000000 A __alt_mem_ext_flash_avl_mem
+14000000 T __reset
+18200000 A __alt_mem_onchip_flash_data
+18400000 A __alt_mem_descriptor_memory
+18403400 A __alt_mem_calibration_ram
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.dat b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.dat
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.sym b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.sym
new file mode 100644
index 0000000..d508ca2
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_calibration_ram.sym
@@ -0,0 +1,1138 @@
+00000000 a OSTCBStkPtr_OFFSET
+00000014 a OSTCBNext_OFFSET
+00000032 a OSTCBPrio_OFFSET
+00000040 a OSCtxSw_SWITCH_PC
+08000000 A __alt_mem_ddr3_ram
+08000120 T alt_exception
+08000120 T alt_irq_entry
+080001fc T alt_irq_handler
+080002c4 T alt_instruction_exception_entry
+08000338 T _start
+0800037c t alt_after_alt_main
+08000380 T control_delay
+080003b0 T control_pong
+08000418 T control_process_snapshot
+08000478 T check_arp
+080004f8 T control_process_config_peer
+0800080c T control_get_header
+080008a4 T control_get_data
+08000950 T control_step
+08001064 T ControlTask
+080010f0 T control_init
+08001124 T InitialTask
+08001178 T main
+080011e8 T get_mac_addr
+0800123c T get_ip_addr
+08001434 T get_serial_number
+080015c8 T generate_and_store_mac_addr
+08001780 T generate_mac_addr
+080018b4 T get_board_mac_addr
+08001a54 T FindLastFlashSectorOffset
+08001b80 T sensor_command_bit
+08001c08 T sensor_preconfigure
+08001d1c T ss_reset_connection
+08001d58 T ss_initialize_connection
+08001da8 T ss_handle_accept
+08001e90 T SSListenerTask
+08002050 T ethernet_init
+080020d0 T ethernet_listen
+0800220c T ethernet_write
+08002314 T ethernet_read
+080024cc T ethernet_close
+08002554 T udpgen_command_bit
+080025dc T udpgen_test
+080027a8 T swap_bytes
+08002840 T swap_quad
+08002904 T reload_fpga
+08002944 T masterslave
+080029cc T master_clock_period
+08002a14 T master_clock_enable
+08002a70 T led_set
+08002abc T led_clear
+08002b08 T led_toggle
+08002b7c T led4_blink_enable
+08002bc8 T set_delay
+08002c30 T _getchar_r
+08002c38 T getchar
+08002c48 T _printf_r
+08002c78 T printf
+08002cb0 T _putchar_r
+08002cb8 T putchar
+08002cd0 T _puts_r
+08002d9c T puts
+08002dac T strlen
+08002e44 T ___vfprintf_internal_r
+08004fa4 T __vfprintf_internal
+08004fbc t __sbprintf
+0800507c T __swsetup_r
+080051dc t quorem
+080053ec T _dtoa_r
+08006ab4 T __sflush_r
+08006cdc T _fflush_r
+08006d3c T fflush
+08006d64 t __fp_lock
+08006d6c T _cleanup_r
+08006d78 t __sinit.part.0
+08006ee0 t __fp_unlock
+08006ee8 T __sfmoreglue
+08006f50 T __sfp
+0800704c T _cleanup
+08007060 T __sinit
+08007070 T __sfp_lock_acquire
+08007074 T __sfp_lock_release
+08007078 T __sinit_lock_acquire
+0800707c T __sinit_lock_release
+08007080 T __fp_lock_all
+08007094 T __fp_unlock_all
+080070a8 T _malloc_trim_r
+080071c4 T _free_r
+080074c0 T __sfvwrite_r
+08007984 T _fwalk
+08007a28 T _fwalk_reent
+08007adc T _getc_r
+08007b58 T getc
+08007be8 T __localeconv_l
+08007bf0 T _localeconv_r
+08007bfc T localeconv
+08007c08 T __swhatbuf_r
+08007ca0 T __smakebuf_r
+08007ddc T _malloc_r
+080085d0 T memchr
+080086b8 T memcpy
+080087b8 T memmove
+080088e4 T memset
+080089d4 T _Balloc
+08008a78 T _Bfree
+08008a9c T __multadd
+08008bb0 T __s2b
+08008cc0 T __hi0bits
+08008d24 T __lo0bits
+08008dd4 T __i2b
+08008e08 T __multiply
+08008ff4 T __pow5mult
+0800911c T __lshift
+08009258 T __mcmp
+080092b0 T __mdiff
+0800946c T __ulp
+080094c8 T __b2d
+080095cc T __d2b
+08009714 T __ratio
+080097bc T _mprec_log10
+08009830 T __copybits
+0800989c T __any_on
+08009910 T _putc_r
+080099dc T putc
+08009abc T _realloc_r
+0800a0e8 T __srget_r
+0800a15c T __srget
+0800a16c T _sbrk_r
+0800a1c4 T __sread
+0800a218 T __seofread
+0800a220 T __swrite
+0800a2a0 T __sseek
+0800a2fc T __sclose
+0800a304 t __sprint_r.part.0
+0800a3f8 T __sprint_r
+0800a410 T ___vfiprintf_internal_r
+0800b73c T __vfiprintf_internal
+0800b754 t __sbprintf
+0800b814 T __swbuf_r
+0800b95c T __swbuf
+0800b970 T _write_r
+0800b9d4 T _close_r
+0800ba2c T _calloc_r
+0800bae4 T _fclose_r
+0800bbdc T fclose
+0800bbec T __fputwc
+0800bd3c T _fputwc_r
+0800bd60 T fputwc
+0800bddc T _fstat_r
+0800be3c T _isatty_r
+0800be94 T _setlocale_r
+0800bf04 T __locale_mb_cur_max
+0800bf10 T setlocale
+0800bf24 T _lseek_r
+0800bf88 T _mbtowc_r
+0800bf94 T __ascii_mbtowc
+0800bfd8 T _read_r
+0800c03c t lflush
+0800c058 T __srefill_r
+0800c224 T strcmp
+0800c2fc T _wcrtomb_r
+0800c368 T wcrtomb
+0800c3ec T _wctomb_r
+0800c3f8 T __ascii_wctomb
+0800c428 T __udivdi3
+0800c9c0 T __umoddi3
+0800cf00 T __divsi3
+0800cf80 T __modsi3
+0800cff8 T __udivsi3
+0800d05c T __umodsi3
+0800d0b8 T __adddf3
+0800da58 T __divdf3
+0800e300 T __eqdf2
+0800e300 T __nedf2
+0800e380 T __gedf2
+0800e380 T __gtdf2
+0800e470 T __ledf2
+0800e470 T __ltdf2
+0800e560 T __muldf3
+0800ebec T __subdf3
+0800f558 T __unorddf2
+0800f5ac T __fixdfsi
+0800f62c T __floatsidf
+0800f6f4 T __floatunsidf
+0800f790 T __clzsi2
+0800f7e4 T alt_flash_open_dev
+0800f84c T alt_flash_close_dev
+0800f8a0 t alt_get_errno
+0800f8dc T fstat
+0800f98c t alt_get_errno
+0800f9c8 T isatty
+0800fa6c t alt_get_errno
+0800faa8 T lseek
+0800fb7c T alt_main
+0800fc38 T sbrk
+0800fce8 T __env_lock
+0800fdac T __env_unlock
+0800fe0c T __malloc_lock
+0800ff2c T __malloc_unlock
+0800fff8 T OSEventNameGet
+080100d0 T OSEventNameSet
+080101d0 T OSEventPendMulti
+0801077c T OSInit
+080107cc T OSIntEnter
+08010818 T OSIntExit
+08010908 T OSSchedLock
+08010994 T OSSchedUnlock
+08010a70 T OSStart
+08010ad8 T OSTimeTick
+08010c98 T OSVersion
+08010cb8 T OS_Dummy
+08010cd8 T OS_EventTaskRdy
+08010e60 T OS_EventTaskWait
+08010f68 T OS_EventTaskWaitMulti
+080110b0 T OS_EventTaskRemove
+08011160 T OS_EventTaskRemoveMulti
+08011258 T OS_EventWaitListInit
+080112c0 t OS_InitEventList
+080113a0 t OS_InitMisc
+080113dc t OS_InitRdyList
+08011448 t OS_InitTaskIdle
+080114cc t OS_InitTCBList
+080115b0 T OS_MemClr
+08011604 T OS_MemCopy
+0801166c T OS_Sched
+08011734 t OS_SchedNew
+080117a0 T OS_StrCopy
+08011814 T OS_StrLen
+08011868 T OS_TaskIdle
+080118c4 T OS_TCBInit
+08011b98 T OSFlagAccept
+08011e78 T OSFlagCreate
+08011f70 T OSFlagDel
+0801218c T OSFlagNameGet
+0801226c T OSFlagNameSet
+08012378 T OSFlagPend
+08012910 T OSFlagPendGetFlagsRdy
+08012970 T OSFlagPost
+08012cdc T OSFlagQuery
+08012d74 t OS_FlagBlock
+08012ed8 T OS_FlagInit
+08012fb8 t OS_FlagTaskRdy
+080130ac T OS_FlagUnlink
+08013150 T OSMemCreate
+08013298 T OSMemGet
+0801335c T OSMemNameGet
+08013404 T OSMemNameSet
+080134d8 T OSMemPut
+08013590 T OSMemQuery
+08013658 T OS_MemInit
+08013724 T OSMutexAccept
+0801389c T OSMutexCreate
+08013a1c T OSMutexDel
+08013cdc T OSMutexPend
+08014238 T OSMutexPost
+08014430 T OSMutexQuery
+0801457c t OSMutex_RdyAtPrio
+08014704 T OSQAccept
+08014818 T OSQCreate
+080149bc T OSQDel
+08014c10 T OSQFlush
+08014c9c T OSQPend
+08014efc T OSQPendAbort
+0801503c T OSQPost
+08015194 T OSQPostFront
+080152f4 T OSQPostOpt
+080154f0 T OSQQuery
+0801562c T OS_QInit
+080156d4 T OSSemAccept
+08015774 T OSSemCreate
+0801584c T OSSemDel
+08015a60 T OSSemPend
+08015c44 T OSSemPendAbort
+08015d84 T OSSemPost
+08015e84 T OSSemQuery
+08015f74 T OSSemSet
+0801604c T OSTaskChangePrio
+080164cc T OSTaskCreate
+0801664c T OSTaskCreateExt
+080167f0 T OSTaskDel
+08016b04 T OSTaskDelReq
+08016c2c T OSTaskNameGet
+08016d64 T OSTaskNameSet
+08016ec0 T OSTaskResume
+08017078 T OSTaskSuspend
+08017220 T OSTaskQuery
+0801730c T OSTimeDly
+08017410 T OSTimeDlyHMSM
+0801750c T OSTimeDlyResume
+080176d8 T OSTimeGet
+08017734 T OSTimeSet
+08017794 t alt_dev_reg
+080177c8 T alt_irq_init
+08017800 T alt_sys_init
+08017a2c t alt_avalon_timer_sc_irq
+08017aa4 T alt_avalon_timer_sc_init
+08017b20 T no_printf
+08017b50 T tse_mac_initTransInfo2
+08017bb0 T tse_mac_sTxWrite
+08017c78 T tse_mac_aRxRead
+08017ce8 T tse_mac_aTxWrite
+08017d58 T tse_mac_SwReset
+08017de0 T tse_mac_setMIImode
+08017e34 T tse_mac_setGMIImode
+08017e84 T alt_tse_phy_add_profile
+08018038 T alt_tse_system_add_sys
+080188fc T alt_tse_sys_enable_mdio_sharing
+08018a40 T alt_tse_mac_get_common_speed
+08018a80 T alt_tse_mac_set_common_speed
+08018ac8 T alt_tse_get_system_index
+08018b34 T alt_tse_get_mac_group_index
+08018ba0 T alt_tse_get_mac_info_index
+08018c1c T alt_tse_get_mac_info
+08018ce8 T alt_tse_mac_set_speed
+08018dc8 T alt_tse_mac_set_duplex
+08018e54 T getPHYSpeed
+080198cc T alt_tse_phy_rd_mdio_addr
+08019914 T alt_tse_phy_wr_mdio_addr
+0801996c T alt_tse_phy_wr_mdio_reg
+08019a98 T alt_tse_phy_rd_mdio_reg
+08019b68 T alt_tse_phy_add_profile_default
+08019e30 T alt_tse_phy_print_profile
+0801a000 T alt_tse_mac_group_init
+0801a698 T alt_tse_mac_get_phy
+0801aaa4 T alt_tse_mac_associate_phy
+0801ace4 T alt_tse_phy_cfg_pcs
+0801ae0c T alt_tse_phy_init
+0801af18 T alt_tse_phy_restart_an
+0801b0dc T alt_tse_phy_check_link
+0801b264 T alt_tse_phy_get_cap
+0801b7f0 T alt_tse_phy_set_adv_1000
+0801b9b4 T alt_tse_phy_set_adv_100
+0801bc08 T alt_tse_phy_set_adv_10
+0801bdb0 T alt_tse_phy_get_common_speed
+0801c0cc T alt_tse_phy_set_common_speed
+0801c57c T marvell_phy_cfg
+0801c614 T marvell_cfg_gmii
+0801c6f8 T marvell_cfg_sgmii
+0801c7dc T marvell_cfg_rgmii
+0801c8cc T DP83848C_link_status_read
+0801c944 T PEF7071_config
+0801c9a0 T PEF7071_link_status_read
+0801ca40 T altera_avalon_uart_read_fd
+0801caa0 T altera_avalon_uart_write_fd
+0801cb00 T altera_avalon_uart_close_fd
+0801cb50 T altera_avalon_uart_init
+0801ccb0 t altera_avalon_uart_irq
+0801cd4c t altera_avalon_uart_rxirq
+0801ce80 t altera_avalon_uart_txirq
+0801d020 T altera_avalon_uart_close
+0801d074 t alt_get_errno
+0801d0b0 T altera_avalon_uart_read
+0801d318 t alt_get_errno
+0801d354 T altera_avalon_uart_write
+0801d588 t alt_flash_device_register
+0801d5bc T alt_qspi_controller_lock
+0801d6cc T alt_qspi_controller_get_info
+0801d758 T alt_qspi_controller_erase_block
+0801d87c T alt_qspi_controller_write_block
+0801da8c T alt_qspi_controller_write
+0801dc74 T alt_qspi_controller_read
+0801dd20 T altera_qspi_controller_init
+0801df74 t alt_qspi_validate_read_write_arguments
+0801e010 t alt_qspi_poll_for_write_in_progress
+0801e09c t alt_get_errno
+0801e0d8 t alt_msgdma_write_standard_descriptor
+0801e16c t alt_msgdma_write_extended_descriptor
+0801e298 t alt_msgdma_irq
+0801e41c t alt_msgdma_construct_standard_descriptor
+0801e4a8 t alt_msgdma_construct_extended_descriptor
+0801e5fc t alt_msgdma_descriptor_async_transfer
+0801e938 t alt_msgdma_descriptor_sync_transfer
+0801ed40 T alt_msgdma_construct_standard_st_to_mm_descriptor
+0801ed98 T alt_msgdma_construct_standard_mm_to_st_descriptor
+0801edf0 T alt_msgdma_construct_standard_mm_to_mm_descriptor
+0801ee48 T alt_msgdma_construct_extended_st_to_mm_descriptor
+0801eed8 T alt_msgdma_construct_extended_mm_to_st_descriptor
+0801ef68 T alt_msgdma_construct_extended_mm_to_mm_descriptor
+0801f010 t alt_msgdma_construct_prefetcher_standard_descriptor
+0801f0b4 t alt_msgdma_construct_prefetcher_extended_descriptor
+0801f248 T alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
+0801f2a0 T alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
+0801f2f8 T alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
+0801f350 T alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
+0801f3f0 T alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
+0801f488 T alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
+0801f540 T alt_msgdma_prefetcher_add_standard_desc_to_list
+0801f630 T alt_msgdma_prefetcher_add_extended_desc_to_list
+0801f7c8 T alt_msgdma_prefetcher_set_std_list_own_by_hw_bits
+0801f8d8 T alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits
+0801fa24 T alt_msgdma_start_prefetcher_with_list_addr
+0801fd34 T alt_msgdma_start_prefetcher_with_std_desc_list
+0801fde4 T alt_msgdma_start_prefetcher_with_extd_desc_list
+0801fe94 T alt_msgdma_open
+0801feec T alt_msgdma_init
+08020094 T alt_msgdma_register_callback
+080200e8 T alt_msgdma_standard_descriptor_async_transfer
+08020124 T alt_msgdma_extended_descriptor_async_transfer
+08020160 T alt_msgdma_standard_descriptor_sync_transfer
+0802019c T alt_msgdma_extended_descriptor_sync_transfer
+080201d8 t alt_flash_device_register
+0802020c T alt_onchip_flash_read
+080202d8 T alt_onchip_flash_get_info
+08020374 T alt_onchip_flash_erase_block
+080204dc T alt_onchip_flash_write_block
+080207b4 T alt_onchip_flash_write
+08020a80 T altera_onchip_flash_init
+08020f20 T alt_onchip_flash_poll_for_status_to_go_idle
+08020fb0 T alt_onchip_flash_poll_for_status_erase_passed
+08021044 T alt_onchip_flash_poll_for_status_write_passed
+080210d8 T altera_eth_tse_init
+08021220 T prep_tse_mac
+0802144c T msgdma_reset
+080214c4 T tse_mac_init
+08021f28 T tse_msgdma_write_init
+08022048 T tse_mac_raw_send
+08022210 T tse_msgdmaRx_isr
+080223a8 T tse_msgdmaTx_isr
+08022408 T tse_msgdma_read_init
+080226c0 T allocate_rx_descriptor_chain
+080227f8 T tse_mac_rcv
+08022944 T tse_mac_stats
+08022984 T tse_mac_close
+08022a60 T close
+08022aa8 T iniche_devices_init
+08022bcc T read
+08022c3c T write
+08022ca4 T etainit
+08022cec T et_send
+08022e6c T arp_free_pending
+08022ef4 T arp_send_pending
+08022f68 T send_arp
+080233bc T find_oldest_arp
+08023528 T make_arp_entry
+08023624 T arpReply
+080238e4 T arprcv
+08023b48 T send_via_arp
+08023cc4 T cb_arpent_tmo
+08023dd0 T grat_arp
+08024088 T if_getbynum
+080240f4 T isbcast
+080241c8 T reg_type
+08024254 T if_killsocks
+080242e4 T Netinit
+080247b4 T fixup_subnet_mask
+080248e4 T netclose
+080249c4 T pktdemux
+08024d64 T c_older
+08024df4 T ip2mac
+08024f80 T ip_startup
+080251e4 T exit_hook
+0802524c T ip_exit
+080252fc T if_netnumber
+0802537c T igmp_init
+0802541c T igmp_input
+080254ec T igmp_fasttimo
+0802565c T igmp_send
+080258d8 T igmp_joingroup
+08025b04 T igmp_leavegroup
+08025b84 T igmp_validate
+08025e60 T igmp_print_stats
+08026214 T bsd_accept
+08026334 T bsd_getpeername
+08026454 T bsd_getsockname
+08026574 T bsd_i_sockoptlen
+08026704 T bsd_getsockopt
+0802680c T bsd_ioctl
+080268fc T bsd_inet_ntoa
+08026930 T bsd_recvfrom
+08026a74 T bsd_select
+08026bfc T bsd_setsockopt
+08026cd8 T ccksum
+08026d7c T cksum
+08026dd0 T do_trap
+08026dfc T nextarg
+08026e78 T hexdump
+08026fbc T print_ipad
+08027038 T print_uptime
+08027178 T panic
+080271c0 T print_eth
+08027314 T uslash
+08027390 T ns_printf
+08027500 T std_out
+08027544 T con_page
+0802761c T parse_args
+08027814 T netmain
+080278f4 T tk_netmain
+0802796c T tk_nettick
+080279b0 T TK_OSTimeDly
+080279e0 T TK_OSTaskResume
+08027a54 T tcp_sleep
+08027ba0 T tcp_wakeup
+08027c78 T TK_OSTaskQuery
+08027ce4 T tk_yield
+08027d14 T tk_stats
+08027f0c T icmpEcho
+080281a8 T pk_init
+08028434 T pk_alloc
+080284f4 T pk_validate
+08028748 T pk_free
+080287f4 T pk_get_max_intrsafe_buf_len
+08028814 T dump_buf_estats
+080288d8 T getq
+08028990 T putq
+08028a40 T qdel
+08028b40 T asm_cksum
+08028b60 t asm1
+08028b88 t loop
+08028c8c t loop0
+08028ca8 t fold
+08028cd0 t done
+08028cd4 T dtrap
+08028d08 T kbhit
+08028d90 T getch
+08028de0 T clock_init
+08028e18 T clock_c
+08028e38 T cticks_hook
+08028e94 T irq_Mask
+08028ef4 T irq_Unmask
+08028f38 T LOCK_NET_RESOURCE
+08028ff4 T UNLOCK_NET_RESOURCE
+08029074 T TK_NEWTASK
+080292b4 T wait_app_sem
+08029368 T post_app_sem
+080293dc T alt_iniche_init
+0802959c T pre_task_setup
+080295e8 T post_task_setup
+08029608 T prep_armintcp
+08029640 T npalloc_base
+0802974c T npfree_base
+0802982c T npalloc
+08029860 T npfree
+080298a0 T ncpalloc
+080298d4 T ncpfree
+08029914 T pffindtype
+080299a4 T pffindproto
+08029a70 T m_getnbuf
+08029bf8 T m_free
+08029cfc T m_freem
+08029d40 T m_copy
+0802a018 T m_adj
+0802a1d8 T mbuf_len
+0802a22c T dtom
+0802a2c4 T remque
+0802a334 T insque
+0802a3b0 T nptcp_init
+0802a4a4 T tcp_rcv
+0802a658 T ip_output
+0802abe0 T in_broadcast
+0802ac18 T np_stripoptions
+0802ad08 T so_icmpdu
+0802b050 T tcp_tick
+0802b0c8 T rawip_lookup
+0802b124 T rawip_soinput
+0802b2e8 T rawip_usrreq
+0802ba20 T DOMAIN_CHECK
+0802ba70 T t_socket
+0802baf0 T t_bind
+0802bc50 T t_listen
+0802bd24 T t_accept
+0802bf74 T t_connect
+0802c1e4 T t_getpeername
+0802c228 T t_getsockname
+0802c26c t t_getname
+0802c44c T t_setsockopt
+0802c60c T t_getsockopt
+0802c794 T t_recv
+0802c870 T t_recvfrom
+0802c9ac T t_sendto
+0802cb9c T t_send
+0802cd9c T t_shutdown
+0802ce70 T t_socketclose
+0802cf30 t sockargs
+0802cfbc T t_errno
+0802d050 T socreate
+0802d1f8 T sobind
+0802d254 T solisten
+0802d324 T sofree
+0802d434 T soclose
+0802d6fc T soabort
+0802d74c T soaccept
+0802d7e4 T soconnect
+0802d89c T sodisconnect
+0802d934 T sosend
+0802de94 T soreceive
+0802e5ec T soshutdown
+0802e684 T sorflush
+0802e780 T sosetopt
+0802ec0c T sogetopt
+0802f12c T sohasoutofband
+0802f178 T soisconnecting
+0802f1e8 T soisconnected
+0802f2ec T soisdisconnecting
+0802f384 T soisdisconnected
+0802f448 T sonewconn
+0802f640 T soqinsque
+0802f6ec T soqremque
+0802f7f4 T socantsendmore
+0802f84c T socantrcvmore
+0802f8a4 T sbselqueue
+0802f8e0 T sbwait
+0802f94c T sbwakeup
+0802f9d8 T soreserve
+0802fa60 T sbreserve
+0802fab0 T sbrelease
+0802fafc T sbappend
+0802fb9c T sbappendrecord
+0802fc74 T sbappendaddr
+0802fe50 T sbcompress
+0803002c T sbflush
+080300b0 T sbdrop
+08030268 T sbdropend
+08030368 T sbdroprecord
+080303f8 T t_select
+080305c8 T sock_selscan
+08030708 T sock_select
+080308f0 T in_pcbnotify
+080309b4 T tcp_notify
+08030a34 T ifd_clr
+08030b18 T ifd_set
+08030b8c T ifd_isset
+08030c00 T ifd_get
+08030c60 T tcp_reass
+08031050 T tcp_input
+08033264 T tcp_dooptions
+080333ec T tcp_pulloutofband
+08033518 T tcp_xmit_timer
+08033754 T ip4_tcpmss
+0803379c T tcp_mss
+08033894 T tcp_output
+08034830 T tcp_setpersist
+0803492c t bld_options
+080349f8 T tcp_init
+08034a40 T tcp_template
+08034b48 T tcp_respond
+08034f40 T tcp_newtcpcb
+0803504c T tcp_drop
+080350e8 T tcp_close
+080351d0 T tcp_quench
+0803521c T tcp_putseq
+08035294 T tcp_getseq
+08035308 T tcp_slowtimo
+08035564 T tcp_canceltimers
+080355c0 T tcp_timers
+08035a14 T tcp_usrreq
+080360cc T tcp_attach
+080361e4 T tcp_disconnect
+080362b0 T tcp_usrclosed
+0803637c T tcpinit
+080363bc T udp_lookup
+08036418 T udp_soinput
+080365b8 T udp_usrreq
+080367f0 T udp4_sockbind
+08036ac0 T udp4_socksend
+08036e34 T udp4_sockaddr
+08036f5c T alt_busy_sleep
+080370b4 t alt_get_errno
+080370f0 T alt_close
+080371c0 T alt_dcache_flush
+08037238 t alt_dev_null_write
+08037264 t alt_get_errno
+080372a0 T alt_dev_llist_insert
+08037344 T _do_ctors
+080373a4 T _do_dtors
+08037404 T alt_find_dev
+08037494 T alt_ic_isr_register
+080374e4 T alt_ic_irq_enable
+0803756c T alt_ic_irq_disable
+080375f8 T alt_ic_irq_enabled
+08037644 T alt_iic_isr_register
+08037728 t alt_open_fd
+080377d8 T alt_io_redirect
+08037854 t alt_get_errno
+08037890 t alt_file_locked
+08037948 T open
+08037a9c T alt_printf
+08037cc8 T alt_putchar
+08037cf8 t alt_get_errno
+08037d34 T alt_read
+08037e30 T alt_release_fd
+08037e88 T alt_remap_cached
+08037ebc T alt_alarm_stop
+08037f58 T alt_tick
+08038060 T alt_uncached_free
+080380a4 T alt_uncached_malloc
+0803811c T usleep
+08038230 t alt_get_errno
+0803826c T alt_write
+08038364 T altera_nios2_gen2_irq_init
+08038388 T OSCtxSw
+08038388 T OSIntCtxSw
+08038414 T OSStartHighRdy
+08038434 T OSStartTsk
+08038458 T OSTaskStkInit
+080385a4 T OSTaskCreateHook
+080385c8 T OSTaskDelHook
+080385ec T OSTaskSwHook
+0803860c T OSTaskStatHook
+0803862c T OSTimeTickHook
+08038658 T OSInitHookBegin
+08038678 T OSInitHookEnd
+08038698 T OSTaskIdleHook
+080386b8 T OSTCBInitHook
+080386dc T netmain_init
+080387c4 T icmp_port_du
+08038850 T station_state
+080389b0 T sysuptime
+080389e8 T packet_check
+08038a38 T mcastlist
+08038a5c T prep_modules
+08038ab0 T inet_timer
+08038b28 t check_interval_timers
+08038c74 T in_timerset
+08038da0 T in_timerkill
+08038e38 T create_apptasks
+08038e5c T task_stats
+08038ed8 T fcntl
+08038f78 T icmprcv
+08039a54 T icmp_destun
+08039d2c T icmp_timex
+0803a01c T icmp_du
+0803a070 T ip_init
+0803a148 T ip_bldhead
+0803a2d4 T ip_write_internal
+0803a9e8 T ip_write
+0803abf8 T ip_write2
+0803af6c T ip_raw_write
+0803b028 T ip_mymach
+0803b0cc T ip_dump
+0803b370 T iproute
+0803b53c T ip_copypkt
+0803b668 T ip_rcv
+0803b9bc T ip_rcv_phase2
+0803bf08 T ip_demux
+0803c2ac T in_addmulti
+0803c3f8 T in_delmulti
+0803c504 T lookup_mcast
+0803c568 T prep_ifaces
+0803c5e8 T netexit
+0803c610 T evtmap_setup
+0803c63c T ip_raw_open
+0803c714 T ip_raw_close
+0803c7d0 T ip_raw_input
+0803c9e4 T ip_raw_alloc
+0803ca9c T ip_raw_free
+0803cae0 T ip_raw_maxalloc
+0803cb28 T rt_lookup
+0803cc7c T add_route
+0803d020 T del_route
+0803d134 T udpdemux
+0803d8a0 T udp_send
+0803db34 T udpswap
+0803dc28 T udp_socket
+0803dcd8 T udp_alloc
+0803dd94 T udp_maxalloc
+0803ddb8 T udp_free
+0803ddfc T igmpv1_input
+0803e064 T igmpv2_input
+0803e170 T igmpv2_process_report
+0803e284 T igmpv2_process_query
+0803e444 T igmpv2_chk_set_timer
+0803e574 T igmpv2_chk4_rtr_alert_opt
+0803e6b0 T IPADDR_TO_NETP
+0803e7c4 T ip_setmoptions
+0803ed64 T ip_getmoptions
+0803ee74 T ip_freemoptions
+0803eef8 T u_mctest_init
+0803ef2c T u_mctest_run
+0803f598 T init_memdev
+0803f5e8 T md_fopen
+0803f610 T md_fclose
+0803f634 T md_fread
+0803f78c T md_fwrite
+0803f804 T md_fseek
+0803f830 T md_ftell
+0803f854 T md_fgetc
+0803f918 T md_unlink
+0803f93c T parse_ipad
+0803fc38 T inet_addr
+0803fc9c T hextoa
+0803fce8 T inet_pton
+0803fd7c T inet_ntop
+0803fe00 T print46_addr
+0803fe5c T inet46_addr
+0803ff20 T inet_setport
+0803ff8c T convert_ip
+080400c0 T tcp_cksum
+08040254 T udp_open
+08040454 T udp_close
+0804052c T in_pcballoc
+080405b4 T in_pcbdetach
+0804060c T in_pcbbind
+0804081c T in_pcbconnect
+080409fc T in_pcbdisconnect
+08040a58 T in_setsockaddr
+08040adc T in_setpeeraddr
+08040b60 T in_pcblookup
+08040db4 T set_vfopen_error
+08040de0 T get_vfopen_error
+08040e00 T vf_alloc_and_link_vop
+08040e70 T vf_alloc_buffer
+08040f38 T vf_free_buffer
+08040f88 T vfopen_locked
+080412c0 T vfopen
+08041310 T vfclose_locked
+080414cc T vfclose
+08041510 T vfflush
+08041558 T vfgets
+08041628 T vfeof
+08041678 T vunlink_flag_open_files
+080416d4 T vunlink
+080418d4 T vfread
+08041a5c T vfwrite_locked
+08041e08 T vfwrite
+08041e68 T vfseek
+08041fbc T vftell
+080420c8 T vgetc_locked
+080421c0 T vgetc
+08042208 T vfslookup_locked
+0804232c T vfslookup
+08042374 T strippath
+08042540 T isvfile_locked
+08042598 T isvfile
+080425e0 T vferror
+0804263c T vclearerr
+08042694 T prep_vfs
+080426b8 t alt_get_errno
+080426f4 T alt_fcntl
+08042818 T alt_find_file
+08042920 T alt_get_fd
+080429f8 T alt_exception_cause_generated_bad_addr
+08042a90 T atexit
+08042aa4 T atoi
+08042ab0 T _atoi_r
+08042abc T exit
+08042af0 T memalign
+08042b04 T _memalign_r
+08042c98 T malloc
+08042ca8 T free
+08042cb8 T memcmp
+08042d44 T _sprintf_r
+08042d98 T sprintf
+08042dfc T strchr
+08042f60 T strcpy
+08042fec T strncmp
+080430e8 t _strtol_l.isra.0
+0804330c T _strtol_r
+08043310 T strtol_l
+08043328 T strtol
+08043340 T ___svfprintf_internal_r
+08045458 T vprintf
+08045474 T _vprintf_r
+08045484 T _vsprintf_r
+080454d0 T vsprintf
+080454e8 T __register_exitproc
+08045578 T __call_exitprocs
+08045690 T __ssprint_r
+08045850 T ___svfiprintf_internal_r
+08046970 T _vfprintf_r
+08046974 T _exit
+080469a8 A __CTOR_END__
+080469a8 A __CTOR_LIST__
+080469a8 A __DTOR_END__
+080469a8 A __DTOR_LIST__
+080471d6 R _ctype_
+080472d7 R _ctype_b
+0804749e r zeroes.5227
+080474ae r blanks.5226
+080474d0 r p05.4024
+080474dc R __mprec_tinytens
+08047504 R __mprec_bigtens
+0804752c R __mprec_tens
+080475f4 r zeroes.5204
+08047604 r blanks.5203
+08047624 R __clz_tab
+08047734 R OSUnMapTbl
+0804b8d1 r zeroes.5208
+0804b8e1 r blanks.5207
+0804b8f1 r zeroes.5188
+0804b901 r blanks.5187
+0804b920 G controltask
+0804b938 G sslistenertask
+0804b950 G tse_mac_device
+0804ba80 g impure_data
+0804bea4 G __malloc_av_
+0804c2ac G __global_locale
+0804c420 g debug_uart
+0804c4f0 g ext_flash
+0804c5d0 g msgdma_rx
+0804c640 g msgdma_tx
+0804c6b0 g onchip_flash
+0804c7b0 G nettasks
+0804c7e0 G tcp_protosw
+0804c7f8 G udp_protosw
+0804c810 G rawip_protosw
+0804c828 G tcp_outflags
+0804c833 G tcp_backoff
+0804c840 G alt_dev_null
+0804c868 G alt_fd_list
+0804c928 G icmpdu_types
+0804c940 g dsts
+0804c958 G rtp_priority
+0804c964 G mdio
+0804c988 G mdlist
+0804ca38 G vfs_root_path
+0804cab8 G _global_impure_ptr
+0804cabc G _impure_ptr
+0804cac0 G __malloc_sbrk_base
+0804cac4 G __malloc_trim_threshold
+0804cac8 G alt_flash_dev_list
+0804cad0 g heap_end
+0804cad4 g lockid
+0804cad8 g lockid
+0804cadc G eth_tse_name
+0804cae0 G max_mac_system
+0804cae4 G alt_msgdma_list
+0804caec G altera_onchip_flash_list
+0804caf4 G alt_iniche_dev_list
+0804cafc G arp_ageout
+0804cb00 G ipmcfail_str
+0804cb04 g cksum_select
+0804cb08 G num_net_tasks
+0804cb0c G pingdata
+0804cb10 G lilbufs
+0804cb14 G lilbufsiz
+0804cb18 G bigbufs
+0804cb1c G bigbufsiz
+0804cb20 G kb_last
+0804cb24 G TCPTV_MSL
+0804cb28 G socket_defaults
+0804cb2a G tcprexmtthresh
+0804cb2c G tcp_ttl
+0804cb30 G tcp_keepidle
+0804cb34 G tcp_keepintvl
+0804cb38 G tcp_sendspace
+0804cb3c G tcp_recvspace
+0804cb40 G alt_fs_list
+0804cb48 G alt_dev_list
+0804cb50 G alt_max_fd
+0804cb54 G alt_errno
+0804cb58 G alt_priority_mask
+0804cb5c G alt_alarm_list
+0804cb64 G name
+0804cb68 G prompt
+0804cb6c G pingdelay
+0804cb70 G deflength
+0804cb74 g uid
+0804cb78 G ipRoutes
+0804cb7c g iCounter.5304
+0804cb80 G mdlist_size
+0804cb84 G pton_error
+0804cb88 G http_root_path
+0804cb8c A __bss_start
+0804cb8c A _edata
+0804cb8c b bytes_received.5850
+0804cb90 b header.5849
+0804cb98 b bytes_received.5856
+0804cb9c B to_controltask
+0804cba0 B last_flash_sector_offset
+0804cba4 B last_flash_sector
+0804cba8 b mutex
+0804cbac B to_sslistenertask
+0804cbae B mastermode
+0804cbb0 B delays
+0804cbb4 B __malloc_max_total_mem
+0804cbb8 B __malloc_max_sbrked_mem
+0804cbbc B __malloc_top_pad
+0804cbc0 B errno
+0804cbc4 B _PathLocale
+0804cbc8 B alt_argc
+0804cbcc B alt_argv
+0804cbd0 B alt_envp
+0804cbd4 b locks
+0804cbd8 B alt_envsem
+0804cbdc b locks
+0804cbe0 B alt_heapsem
+0804cbe4 B OSLockNesting
+0804cbe5 B OSRunning
+0804cbe8 B OSIdleCtr
+0804cbec B OSPrioHighRdy
+0804cbed B OSPrioCur
+0804cbf0 B OSTCBList
+0804cbf4 B OSCtxSwCtr
+0804cbf8 B OSTCBFreeList
+0804cbfc B OSTaskCtr
+0804cc00 B OSMemFreeList
+0804cc04 B OSTCBHighRdy
+0804cc08 B OSQFreeList
+0804cc0c B OSRdyGrp
+0804cc0d B OSRdyTbl
+0804cc10 B OSEventFreeList
+0804cc14 B OSIntNesting
+0804cc18 B OSTCBCur
+0804cc1c B OSTime
+0804cc20 B OSFlagFreeList
+0804cc24 B phy_profile_count
+0804cc25 B mac_group_count
+0804cc26 b tse_system_count.5331
+0804cc27 b is_init.5413
+0804cc28 B number_of_tse_mac
+0804cc2c b arp_timer
+0804cc30 B arpcache
+0804cc34 b cachetime
+0804cc38 B arpReqsIn
+0804cc3c B arpReqsOut
+0804cc40 B arpRepsIn
+0804cc44 B arpRepsOut
+0804cc48 B MaxLnh
+0804cc4c B MaxMtu
+0804cc50 B NDEBUG
+0804cc54 B ifNumber
+0804cc58 b nclosers
+0804cc5c B igmp_timers_are_running
+0804cc60 B igmp_cticks
+0804cc64 B igmp_all_hosts_group
+0804cc68 B igmp_all_rtrs_group
+0804cc6c B netmain_wakes
+0804cc70 B nettick_wakes
+0804cc74 B iniche_net_ready
+0804cc78 B to_netmain
+0804cc79 B to_nettick
+0804cc7c B tcp_sleep_timeout
+0804cc80 B cticks_initialized
+0804cc84 B irq_level
+0804cc88 b cpu_statusreg
+0804cc8c b kbd_init.4507
+0804cc90 B cticks_factor
+0804cc94 B OS_TPS
+0804cc98 B tcp_sleep_count
+0804cc9c B tcp_wakeup_count
+0804cca0 B netq_intmask
+0804cca4 B old_mode
+0804cca8 B global_TCPwakeup_setIndx
+0804ccac B cticks
+0804ccb0 B memtrapsize
+0804ccb4 B mheap_sem_ptr
+0804ccb8 B rcvdq_sem_ptr
+0804ccbc B nextslow
+0804ccc0 b in_tcptick
+0804ccc4 B mbstat
+0804cccc B select_wait
+0804ccd0 B tcpprintfs
+0804ccd4 B dropline
+0804ccd8 B tcp_optionbuf
+0804ccdc B tcp_maxidle
+0804cce0 B tcp_iss
+0804cce4 B alt_fd_list_lock
+0804cce8 B alt_irq_active
+0804ccec B _alt_tick_rate
+0804ccf0 B _alt_nticks
+0804ccf4 B activehost
+0804ccf8 b inside_pktdemux
+0804ccfc B nextppp
+0804cd00 B port_1s_callout
+0804cd04 b numtimers
+0804cd08 B icmpdu_hook
+0804cd0c B rt_mib
+0804cd10 B port_prep
+0804cd14 B net_system_exit
+0804cd18 B so_evtmap_create
+0804cd1c B so_evtmap_delete
+0804cd20 B so_evtmap
+0804cd24 B ipraw_eps
+0804cd28 B cachedRoute
+0804cd2c b usocket
+0804cd30 B firstudp
+0804cd34 B inpcb_cachehits
+0804cd38 B inpcb_cachemiss
+0804cd3c B vfsystems
+0804cd40 B vfiles
+0804cd44 B vfsfiles
+0804cd48 B vfopen_error
+0804cd4c B vfs_dir_stale
+0804cd50 B vfs_open_files
+0804cd54 B vfs_total_rw_space
+0804cd58 B vfs_total_dyna_files
+0804cd5c B alt_instruction_exception_handler
+0804cd60 b packet_data.5855
+0804cd80 b connections
+0804cd90 B __malloc_current_mallinfo
+0804cdb8 b closers
+0804cdf4 b tistring
+0804ce0c b nearBuf.4931
+0804ce2c B InitialTaskStk
+08054ab8 A _gp
+0805ae2c B OSFlagTbl
+0805b19c B OSMemTbl
+0805bdcc B OSQTbl
+0805bfac B OSTaskIdleStk
+0805c7ac B OSEventTbl
+0805d2ec B OSTCBTbl
+0805d574 B OSTCBPrioTbl
+0805d5c8 B eth_tse_if
+0805d6a8 B pmac_groups
+0805d6b8 B pphy_profiles
+0805d6d8 B tse_iniche_dev_driver_data
+0805d708 B tse
+0805d998 B arp_table
+0805da98 B netlist
+0805daac B rcvdq
+0805dac0 B netstatic
+0805ddc0 B nets
+0805ddd0 B igmpstats
+0805de34 B eth_prt_buf
+0805de46 B ipreturn
+0805de58 B lilfreeq
+0805de6c B memestats
+0805de7c B pktlog
+0805df6c B bigfreeq
+0805df80 B global_tcb_ext
+0805e07c B global_TCPwakeup_set
+0805e16c B resid_semaphore
+0805e1ac B app_semaphore
+0805e1c4 B soq
+0805e1d8 B tcpmib
+0805e214 B mbufq
+0805e228 B mfreeq
+0805e23c B tcp_saveti
+0805e264 B tcb
+0805e290 B tcpstat
+0805e370 B alt_irq
+0805e470 B intimers
+0805e4d4 B icmp_mib
+0805e53c B ip_mib
+0805e58c B udp_mib
+0805e59c A __alt_heap_start
+0805e59c A __alt_stack_base
+0805e59c A __bss_end
+0805e59c A _end
+0805e59c A end
+10000000 A __alt_data_end
+10000000 A __alt_heap_limit
+10000000 A __alt_stack_pointer
+14000000 A __alt_mem_ext_flash_avl_mem
+14000000 T __reset
+18200000 A __alt_mem_onchip_flash_data
+18400000 A __alt_mem_descriptor_memory
+18403400 A __alt_mem_calibration_ram
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.dat b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.dat
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.sym b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.sym
new file mode 100644
index 0000000..d508ca2
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/hdl_sim/q_sys_descriptor_memory.sym
@@ -0,0 +1,1138 @@
+00000000 a OSTCBStkPtr_OFFSET
+00000014 a OSTCBNext_OFFSET
+00000032 a OSTCBPrio_OFFSET
+00000040 a OSCtxSw_SWITCH_PC
+08000000 A __alt_mem_ddr3_ram
+08000120 T alt_exception
+08000120 T alt_irq_entry
+080001fc T alt_irq_handler
+080002c4 T alt_instruction_exception_entry
+08000338 T _start
+0800037c t alt_after_alt_main
+08000380 T control_delay
+080003b0 T control_pong
+08000418 T control_process_snapshot
+08000478 T check_arp
+080004f8 T control_process_config_peer
+0800080c T control_get_header
+080008a4 T control_get_data
+08000950 T control_step
+08001064 T ControlTask
+080010f0 T control_init
+08001124 T InitialTask
+08001178 T main
+080011e8 T get_mac_addr
+0800123c T get_ip_addr
+08001434 T get_serial_number
+080015c8 T generate_and_store_mac_addr
+08001780 T generate_mac_addr
+080018b4 T get_board_mac_addr
+08001a54 T FindLastFlashSectorOffset
+08001b80 T sensor_command_bit
+08001c08 T sensor_preconfigure
+08001d1c T ss_reset_connection
+08001d58 T ss_initialize_connection
+08001da8 T ss_handle_accept
+08001e90 T SSListenerTask
+08002050 T ethernet_init
+080020d0 T ethernet_listen
+0800220c T ethernet_write
+08002314 T ethernet_read
+080024cc T ethernet_close
+08002554 T udpgen_command_bit
+080025dc T udpgen_test
+080027a8 T swap_bytes
+08002840 T swap_quad
+08002904 T reload_fpga
+08002944 T masterslave
+080029cc T master_clock_period
+08002a14 T master_clock_enable
+08002a70 T led_set
+08002abc T led_clear
+08002b08 T led_toggle
+08002b7c T led4_blink_enable
+08002bc8 T set_delay
+08002c30 T _getchar_r
+08002c38 T getchar
+08002c48 T _printf_r
+08002c78 T printf
+08002cb0 T _putchar_r
+08002cb8 T putchar
+08002cd0 T _puts_r
+08002d9c T puts
+08002dac T strlen
+08002e44 T ___vfprintf_internal_r
+08004fa4 T __vfprintf_internal
+08004fbc t __sbprintf
+0800507c T __swsetup_r
+080051dc t quorem
+080053ec T _dtoa_r
+08006ab4 T __sflush_r
+08006cdc T _fflush_r
+08006d3c T fflush
+08006d64 t __fp_lock
+08006d6c T _cleanup_r
+08006d78 t __sinit.part.0
+08006ee0 t __fp_unlock
+08006ee8 T __sfmoreglue
+08006f50 T __sfp
+0800704c T _cleanup
+08007060 T __sinit
+08007070 T __sfp_lock_acquire
+08007074 T __sfp_lock_release
+08007078 T __sinit_lock_acquire
+0800707c T __sinit_lock_release
+08007080 T __fp_lock_all
+08007094 T __fp_unlock_all
+080070a8 T _malloc_trim_r
+080071c4 T _free_r
+080074c0 T __sfvwrite_r
+08007984 T _fwalk
+08007a28 T _fwalk_reent
+08007adc T _getc_r
+08007b58 T getc
+08007be8 T __localeconv_l
+08007bf0 T _localeconv_r
+08007bfc T localeconv
+08007c08 T __swhatbuf_r
+08007ca0 T __smakebuf_r
+08007ddc T _malloc_r
+080085d0 T memchr
+080086b8 T memcpy
+080087b8 T memmove
+080088e4 T memset
+080089d4 T _Balloc
+08008a78 T _Bfree
+08008a9c T __multadd
+08008bb0 T __s2b
+08008cc0 T __hi0bits
+08008d24 T __lo0bits
+08008dd4 T __i2b
+08008e08 T __multiply
+08008ff4 T __pow5mult
+0800911c T __lshift
+08009258 T __mcmp
+080092b0 T __mdiff
+0800946c T __ulp
+080094c8 T __b2d
+080095cc T __d2b
+08009714 T __ratio
+080097bc T _mprec_log10
+08009830 T __copybits
+0800989c T __any_on
+08009910 T _putc_r
+080099dc T putc
+08009abc T _realloc_r
+0800a0e8 T __srget_r
+0800a15c T __srget
+0800a16c T _sbrk_r
+0800a1c4 T __sread
+0800a218 T __seofread
+0800a220 T __swrite
+0800a2a0 T __sseek
+0800a2fc T __sclose
+0800a304 t __sprint_r.part.0
+0800a3f8 T __sprint_r
+0800a410 T ___vfiprintf_internal_r
+0800b73c T __vfiprintf_internal
+0800b754 t __sbprintf
+0800b814 T __swbuf_r
+0800b95c T __swbuf
+0800b970 T _write_r
+0800b9d4 T _close_r
+0800ba2c T _calloc_r
+0800bae4 T _fclose_r
+0800bbdc T fclose
+0800bbec T __fputwc
+0800bd3c T _fputwc_r
+0800bd60 T fputwc
+0800bddc T _fstat_r
+0800be3c T _isatty_r
+0800be94 T _setlocale_r
+0800bf04 T __locale_mb_cur_max
+0800bf10 T setlocale
+0800bf24 T _lseek_r
+0800bf88 T _mbtowc_r
+0800bf94 T __ascii_mbtowc
+0800bfd8 T _read_r
+0800c03c t lflush
+0800c058 T __srefill_r
+0800c224 T strcmp
+0800c2fc T _wcrtomb_r
+0800c368 T wcrtomb
+0800c3ec T _wctomb_r
+0800c3f8 T __ascii_wctomb
+0800c428 T __udivdi3
+0800c9c0 T __umoddi3
+0800cf00 T __divsi3
+0800cf80 T __modsi3
+0800cff8 T __udivsi3
+0800d05c T __umodsi3
+0800d0b8 T __adddf3
+0800da58 T __divdf3
+0800e300 T __eqdf2
+0800e300 T __nedf2
+0800e380 T __gedf2
+0800e380 T __gtdf2
+0800e470 T __ledf2
+0800e470 T __ltdf2
+0800e560 T __muldf3
+0800ebec T __subdf3
+0800f558 T __unorddf2
+0800f5ac T __fixdfsi
+0800f62c T __floatsidf
+0800f6f4 T __floatunsidf
+0800f790 T __clzsi2
+0800f7e4 T alt_flash_open_dev
+0800f84c T alt_flash_close_dev
+0800f8a0 t alt_get_errno
+0800f8dc T fstat
+0800f98c t alt_get_errno
+0800f9c8 T isatty
+0800fa6c t alt_get_errno
+0800faa8 T lseek
+0800fb7c T alt_main
+0800fc38 T sbrk
+0800fce8 T __env_lock
+0800fdac T __env_unlock
+0800fe0c T __malloc_lock
+0800ff2c T __malloc_unlock
+0800fff8 T OSEventNameGet
+080100d0 T OSEventNameSet
+080101d0 T OSEventPendMulti
+0801077c T OSInit
+080107cc T OSIntEnter
+08010818 T OSIntExit
+08010908 T OSSchedLock
+08010994 T OSSchedUnlock
+08010a70 T OSStart
+08010ad8 T OSTimeTick
+08010c98 T OSVersion
+08010cb8 T OS_Dummy
+08010cd8 T OS_EventTaskRdy
+08010e60 T OS_EventTaskWait
+08010f68 T OS_EventTaskWaitMulti
+080110b0 T OS_EventTaskRemove
+08011160 T OS_EventTaskRemoveMulti
+08011258 T OS_EventWaitListInit
+080112c0 t OS_InitEventList
+080113a0 t OS_InitMisc
+080113dc t OS_InitRdyList
+08011448 t OS_InitTaskIdle
+080114cc t OS_InitTCBList
+080115b0 T OS_MemClr
+08011604 T OS_MemCopy
+0801166c T OS_Sched
+08011734 t OS_SchedNew
+080117a0 T OS_StrCopy
+08011814 T OS_StrLen
+08011868 T OS_TaskIdle
+080118c4 T OS_TCBInit
+08011b98 T OSFlagAccept
+08011e78 T OSFlagCreate
+08011f70 T OSFlagDel
+0801218c T OSFlagNameGet
+0801226c T OSFlagNameSet
+08012378 T OSFlagPend
+08012910 T OSFlagPendGetFlagsRdy
+08012970 T OSFlagPost
+08012cdc T OSFlagQuery
+08012d74 t OS_FlagBlock
+08012ed8 T OS_FlagInit
+08012fb8 t OS_FlagTaskRdy
+080130ac T OS_FlagUnlink
+08013150 T OSMemCreate
+08013298 T OSMemGet
+0801335c T OSMemNameGet
+08013404 T OSMemNameSet
+080134d8 T OSMemPut
+08013590 T OSMemQuery
+08013658 T OS_MemInit
+08013724 T OSMutexAccept
+0801389c T OSMutexCreate
+08013a1c T OSMutexDel
+08013cdc T OSMutexPend
+08014238 T OSMutexPost
+08014430 T OSMutexQuery
+0801457c t OSMutex_RdyAtPrio
+08014704 T OSQAccept
+08014818 T OSQCreate
+080149bc T OSQDel
+08014c10 T OSQFlush
+08014c9c T OSQPend
+08014efc T OSQPendAbort
+0801503c T OSQPost
+08015194 T OSQPostFront
+080152f4 T OSQPostOpt
+080154f0 T OSQQuery
+0801562c T OS_QInit
+080156d4 T OSSemAccept
+08015774 T OSSemCreate
+0801584c T OSSemDel
+08015a60 T OSSemPend
+08015c44 T OSSemPendAbort
+08015d84 T OSSemPost
+08015e84 T OSSemQuery
+08015f74 T OSSemSet
+0801604c T OSTaskChangePrio
+080164cc T OSTaskCreate
+0801664c T OSTaskCreateExt
+080167f0 T OSTaskDel
+08016b04 T OSTaskDelReq
+08016c2c T OSTaskNameGet
+08016d64 T OSTaskNameSet
+08016ec0 T OSTaskResume
+08017078 T OSTaskSuspend
+08017220 T OSTaskQuery
+0801730c T OSTimeDly
+08017410 T OSTimeDlyHMSM
+0801750c T OSTimeDlyResume
+080176d8 T OSTimeGet
+08017734 T OSTimeSet
+08017794 t alt_dev_reg
+080177c8 T alt_irq_init
+08017800 T alt_sys_init
+08017a2c t alt_avalon_timer_sc_irq
+08017aa4 T alt_avalon_timer_sc_init
+08017b20 T no_printf
+08017b50 T tse_mac_initTransInfo2
+08017bb0 T tse_mac_sTxWrite
+08017c78 T tse_mac_aRxRead
+08017ce8 T tse_mac_aTxWrite
+08017d58 T tse_mac_SwReset
+08017de0 T tse_mac_setMIImode
+08017e34 T tse_mac_setGMIImode
+08017e84 T alt_tse_phy_add_profile
+08018038 T alt_tse_system_add_sys
+080188fc T alt_tse_sys_enable_mdio_sharing
+08018a40 T alt_tse_mac_get_common_speed
+08018a80 T alt_tse_mac_set_common_speed
+08018ac8 T alt_tse_get_system_index
+08018b34 T alt_tse_get_mac_group_index
+08018ba0 T alt_tse_get_mac_info_index
+08018c1c T alt_tse_get_mac_info
+08018ce8 T alt_tse_mac_set_speed
+08018dc8 T alt_tse_mac_set_duplex
+08018e54 T getPHYSpeed
+080198cc T alt_tse_phy_rd_mdio_addr
+08019914 T alt_tse_phy_wr_mdio_addr
+0801996c T alt_tse_phy_wr_mdio_reg
+08019a98 T alt_tse_phy_rd_mdio_reg
+08019b68 T alt_tse_phy_add_profile_default
+08019e30 T alt_tse_phy_print_profile
+0801a000 T alt_tse_mac_group_init
+0801a698 T alt_tse_mac_get_phy
+0801aaa4 T alt_tse_mac_associate_phy
+0801ace4 T alt_tse_phy_cfg_pcs
+0801ae0c T alt_tse_phy_init
+0801af18 T alt_tse_phy_restart_an
+0801b0dc T alt_tse_phy_check_link
+0801b264 T alt_tse_phy_get_cap
+0801b7f0 T alt_tse_phy_set_adv_1000
+0801b9b4 T alt_tse_phy_set_adv_100
+0801bc08 T alt_tse_phy_set_adv_10
+0801bdb0 T alt_tse_phy_get_common_speed
+0801c0cc T alt_tse_phy_set_common_speed
+0801c57c T marvell_phy_cfg
+0801c614 T marvell_cfg_gmii
+0801c6f8 T marvell_cfg_sgmii
+0801c7dc T marvell_cfg_rgmii
+0801c8cc T DP83848C_link_status_read
+0801c944 T PEF7071_config
+0801c9a0 T PEF7071_link_status_read
+0801ca40 T altera_avalon_uart_read_fd
+0801caa0 T altera_avalon_uart_write_fd
+0801cb00 T altera_avalon_uart_close_fd
+0801cb50 T altera_avalon_uart_init
+0801ccb0 t altera_avalon_uart_irq
+0801cd4c t altera_avalon_uart_rxirq
+0801ce80 t altera_avalon_uart_txirq
+0801d020 T altera_avalon_uart_close
+0801d074 t alt_get_errno
+0801d0b0 T altera_avalon_uart_read
+0801d318 t alt_get_errno
+0801d354 T altera_avalon_uart_write
+0801d588 t alt_flash_device_register
+0801d5bc T alt_qspi_controller_lock
+0801d6cc T alt_qspi_controller_get_info
+0801d758 T alt_qspi_controller_erase_block
+0801d87c T alt_qspi_controller_write_block
+0801da8c T alt_qspi_controller_write
+0801dc74 T alt_qspi_controller_read
+0801dd20 T altera_qspi_controller_init
+0801df74 t alt_qspi_validate_read_write_arguments
+0801e010 t alt_qspi_poll_for_write_in_progress
+0801e09c t alt_get_errno
+0801e0d8 t alt_msgdma_write_standard_descriptor
+0801e16c t alt_msgdma_write_extended_descriptor
+0801e298 t alt_msgdma_irq
+0801e41c t alt_msgdma_construct_standard_descriptor
+0801e4a8 t alt_msgdma_construct_extended_descriptor
+0801e5fc t alt_msgdma_descriptor_async_transfer
+0801e938 t alt_msgdma_descriptor_sync_transfer
+0801ed40 T alt_msgdma_construct_standard_st_to_mm_descriptor
+0801ed98 T alt_msgdma_construct_standard_mm_to_st_descriptor
+0801edf0 T alt_msgdma_construct_standard_mm_to_mm_descriptor
+0801ee48 T alt_msgdma_construct_extended_st_to_mm_descriptor
+0801eed8 T alt_msgdma_construct_extended_mm_to_st_descriptor
+0801ef68 T alt_msgdma_construct_extended_mm_to_mm_descriptor
+0801f010 t alt_msgdma_construct_prefetcher_standard_descriptor
+0801f0b4 t alt_msgdma_construct_prefetcher_extended_descriptor
+0801f248 T alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
+0801f2a0 T alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
+0801f2f8 T alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
+0801f350 T alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
+0801f3f0 T alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
+0801f488 T alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
+0801f540 T alt_msgdma_prefetcher_add_standard_desc_to_list
+0801f630 T alt_msgdma_prefetcher_add_extended_desc_to_list
+0801f7c8 T alt_msgdma_prefetcher_set_std_list_own_by_hw_bits
+0801f8d8 T alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits
+0801fa24 T alt_msgdma_start_prefetcher_with_list_addr
+0801fd34 T alt_msgdma_start_prefetcher_with_std_desc_list
+0801fde4 T alt_msgdma_start_prefetcher_with_extd_desc_list
+0801fe94 T alt_msgdma_open
+0801feec T alt_msgdma_init
+08020094 T alt_msgdma_register_callback
+080200e8 T alt_msgdma_standard_descriptor_async_transfer
+08020124 T alt_msgdma_extended_descriptor_async_transfer
+08020160 T alt_msgdma_standard_descriptor_sync_transfer
+0802019c T alt_msgdma_extended_descriptor_sync_transfer
+080201d8 t alt_flash_device_register
+0802020c T alt_onchip_flash_read
+080202d8 T alt_onchip_flash_get_info
+08020374 T alt_onchip_flash_erase_block
+080204dc T alt_onchip_flash_write_block
+080207b4 T alt_onchip_flash_write
+08020a80 T altera_onchip_flash_init
+08020f20 T alt_onchip_flash_poll_for_status_to_go_idle
+08020fb0 T alt_onchip_flash_poll_for_status_erase_passed
+08021044 T alt_onchip_flash_poll_for_status_write_passed
+080210d8 T altera_eth_tse_init
+08021220 T prep_tse_mac
+0802144c T msgdma_reset
+080214c4 T tse_mac_init
+08021f28 T tse_msgdma_write_init
+08022048 T tse_mac_raw_send
+08022210 T tse_msgdmaRx_isr
+080223a8 T tse_msgdmaTx_isr
+08022408 T tse_msgdma_read_init
+080226c0 T allocate_rx_descriptor_chain
+080227f8 T tse_mac_rcv
+08022944 T tse_mac_stats
+08022984 T tse_mac_close
+08022a60 T close
+08022aa8 T iniche_devices_init
+08022bcc T read
+08022c3c T write
+08022ca4 T etainit
+08022cec T et_send
+08022e6c T arp_free_pending
+08022ef4 T arp_send_pending
+08022f68 T send_arp
+080233bc T find_oldest_arp
+08023528 T make_arp_entry
+08023624 T arpReply
+080238e4 T arprcv
+08023b48 T send_via_arp
+08023cc4 T cb_arpent_tmo
+08023dd0 T grat_arp
+08024088 T if_getbynum
+080240f4 T isbcast
+080241c8 T reg_type
+08024254 T if_killsocks
+080242e4 T Netinit
+080247b4 T fixup_subnet_mask
+080248e4 T netclose
+080249c4 T pktdemux
+08024d64 T c_older
+08024df4 T ip2mac
+08024f80 T ip_startup
+080251e4 T exit_hook
+0802524c T ip_exit
+080252fc T if_netnumber
+0802537c T igmp_init
+0802541c T igmp_input
+080254ec T igmp_fasttimo
+0802565c T igmp_send
+080258d8 T igmp_joingroup
+08025b04 T igmp_leavegroup
+08025b84 T igmp_validate
+08025e60 T igmp_print_stats
+08026214 T bsd_accept
+08026334 T bsd_getpeername
+08026454 T bsd_getsockname
+08026574 T bsd_i_sockoptlen
+08026704 T bsd_getsockopt
+0802680c T bsd_ioctl
+080268fc T bsd_inet_ntoa
+08026930 T bsd_recvfrom
+08026a74 T bsd_select
+08026bfc T bsd_setsockopt
+08026cd8 T ccksum
+08026d7c T cksum
+08026dd0 T do_trap
+08026dfc T nextarg
+08026e78 T hexdump
+08026fbc T print_ipad
+08027038 T print_uptime
+08027178 T panic
+080271c0 T print_eth
+08027314 T uslash
+08027390 T ns_printf
+08027500 T std_out
+08027544 T con_page
+0802761c T parse_args
+08027814 T netmain
+080278f4 T tk_netmain
+0802796c T tk_nettick
+080279b0 T TK_OSTimeDly
+080279e0 T TK_OSTaskResume
+08027a54 T tcp_sleep
+08027ba0 T tcp_wakeup
+08027c78 T TK_OSTaskQuery
+08027ce4 T tk_yield
+08027d14 T tk_stats
+08027f0c T icmpEcho
+080281a8 T pk_init
+08028434 T pk_alloc
+080284f4 T pk_validate
+08028748 T pk_free
+080287f4 T pk_get_max_intrsafe_buf_len
+08028814 T dump_buf_estats
+080288d8 T getq
+08028990 T putq
+08028a40 T qdel
+08028b40 T asm_cksum
+08028b60 t asm1
+08028b88 t loop
+08028c8c t loop0
+08028ca8 t fold
+08028cd0 t done
+08028cd4 T dtrap
+08028d08 T kbhit
+08028d90 T getch
+08028de0 T clock_init
+08028e18 T clock_c
+08028e38 T cticks_hook
+08028e94 T irq_Mask
+08028ef4 T irq_Unmask
+08028f38 T LOCK_NET_RESOURCE
+08028ff4 T UNLOCK_NET_RESOURCE
+08029074 T TK_NEWTASK
+080292b4 T wait_app_sem
+08029368 T post_app_sem
+080293dc T alt_iniche_init
+0802959c T pre_task_setup
+080295e8 T post_task_setup
+08029608 T prep_armintcp
+08029640 T npalloc_base
+0802974c T npfree_base
+0802982c T npalloc
+08029860 T npfree
+080298a0 T ncpalloc
+080298d4 T ncpfree
+08029914 T pffindtype
+080299a4 T pffindproto
+08029a70 T m_getnbuf
+08029bf8 T m_free
+08029cfc T m_freem
+08029d40 T m_copy
+0802a018 T m_adj
+0802a1d8 T mbuf_len
+0802a22c T dtom
+0802a2c4 T remque
+0802a334 T insque
+0802a3b0 T nptcp_init
+0802a4a4 T tcp_rcv
+0802a658 T ip_output
+0802abe0 T in_broadcast
+0802ac18 T np_stripoptions
+0802ad08 T so_icmpdu
+0802b050 T tcp_tick
+0802b0c8 T rawip_lookup
+0802b124 T rawip_soinput
+0802b2e8 T rawip_usrreq
+0802ba20 T DOMAIN_CHECK
+0802ba70 T t_socket
+0802baf0 T t_bind
+0802bc50 T t_listen
+0802bd24 T t_accept
+0802bf74 T t_connect
+0802c1e4 T t_getpeername
+0802c228 T t_getsockname
+0802c26c t t_getname
+0802c44c T t_setsockopt
+0802c60c T t_getsockopt
+0802c794 T t_recv
+0802c870 T t_recvfrom
+0802c9ac T t_sendto
+0802cb9c T t_send
+0802cd9c T t_shutdown
+0802ce70 T t_socketclose
+0802cf30 t sockargs
+0802cfbc T t_errno
+0802d050 T socreate
+0802d1f8 T sobind
+0802d254 T solisten
+0802d324 T sofree
+0802d434 T soclose
+0802d6fc T soabort
+0802d74c T soaccept
+0802d7e4 T soconnect
+0802d89c T sodisconnect
+0802d934 T sosend
+0802de94 T soreceive
+0802e5ec T soshutdown
+0802e684 T sorflush
+0802e780 T sosetopt
+0802ec0c T sogetopt
+0802f12c T sohasoutofband
+0802f178 T soisconnecting
+0802f1e8 T soisconnected
+0802f2ec T soisdisconnecting
+0802f384 T soisdisconnected
+0802f448 T sonewconn
+0802f640 T soqinsque
+0802f6ec T soqremque
+0802f7f4 T socantsendmore
+0802f84c T socantrcvmore
+0802f8a4 T sbselqueue
+0802f8e0 T sbwait
+0802f94c T sbwakeup
+0802f9d8 T soreserve
+0802fa60 T sbreserve
+0802fab0 T sbrelease
+0802fafc T sbappend
+0802fb9c T sbappendrecord
+0802fc74 T sbappendaddr
+0802fe50 T sbcompress
+0803002c T sbflush
+080300b0 T sbdrop
+08030268 T sbdropend
+08030368 T sbdroprecord
+080303f8 T t_select
+080305c8 T sock_selscan
+08030708 T sock_select
+080308f0 T in_pcbnotify
+080309b4 T tcp_notify
+08030a34 T ifd_clr
+08030b18 T ifd_set
+08030b8c T ifd_isset
+08030c00 T ifd_get
+08030c60 T tcp_reass
+08031050 T tcp_input
+08033264 T tcp_dooptions
+080333ec T tcp_pulloutofband
+08033518 T tcp_xmit_timer
+08033754 T ip4_tcpmss
+0803379c T tcp_mss
+08033894 T tcp_output
+08034830 T tcp_setpersist
+0803492c t bld_options
+080349f8 T tcp_init
+08034a40 T tcp_template
+08034b48 T tcp_respond
+08034f40 T tcp_newtcpcb
+0803504c T tcp_drop
+080350e8 T tcp_close
+080351d0 T tcp_quench
+0803521c T tcp_putseq
+08035294 T tcp_getseq
+08035308 T tcp_slowtimo
+08035564 T tcp_canceltimers
+080355c0 T tcp_timers
+08035a14 T tcp_usrreq
+080360cc T tcp_attach
+080361e4 T tcp_disconnect
+080362b0 T tcp_usrclosed
+0803637c T tcpinit
+080363bc T udp_lookup
+08036418 T udp_soinput
+080365b8 T udp_usrreq
+080367f0 T udp4_sockbind
+08036ac0 T udp4_socksend
+08036e34 T udp4_sockaddr
+08036f5c T alt_busy_sleep
+080370b4 t alt_get_errno
+080370f0 T alt_close
+080371c0 T alt_dcache_flush
+08037238 t alt_dev_null_write
+08037264 t alt_get_errno
+080372a0 T alt_dev_llist_insert
+08037344 T _do_ctors
+080373a4 T _do_dtors
+08037404 T alt_find_dev
+08037494 T alt_ic_isr_register
+080374e4 T alt_ic_irq_enable
+0803756c T alt_ic_irq_disable
+080375f8 T alt_ic_irq_enabled
+08037644 T alt_iic_isr_register
+08037728 t alt_open_fd
+080377d8 T alt_io_redirect
+08037854 t alt_get_errno
+08037890 t alt_file_locked
+08037948 T open
+08037a9c T alt_printf
+08037cc8 T alt_putchar
+08037cf8 t alt_get_errno
+08037d34 T alt_read
+08037e30 T alt_release_fd
+08037e88 T alt_remap_cached
+08037ebc T alt_alarm_stop
+08037f58 T alt_tick
+08038060 T alt_uncached_free
+080380a4 T alt_uncached_malloc
+0803811c T usleep
+08038230 t alt_get_errno
+0803826c T alt_write
+08038364 T altera_nios2_gen2_irq_init
+08038388 T OSCtxSw
+08038388 T OSIntCtxSw
+08038414 T OSStartHighRdy
+08038434 T OSStartTsk
+08038458 T OSTaskStkInit
+080385a4 T OSTaskCreateHook
+080385c8 T OSTaskDelHook
+080385ec T OSTaskSwHook
+0803860c T OSTaskStatHook
+0803862c T OSTimeTickHook
+08038658 T OSInitHookBegin
+08038678 T OSInitHookEnd
+08038698 T OSTaskIdleHook
+080386b8 T OSTCBInitHook
+080386dc T netmain_init
+080387c4 T icmp_port_du
+08038850 T station_state
+080389b0 T sysuptime
+080389e8 T packet_check
+08038a38 T mcastlist
+08038a5c T prep_modules
+08038ab0 T inet_timer
+08038b28 t check_interval_timers
+08038c74 T in_timerset
+08038da0 T in_timerkill
+08038e38 T create_apptasks
+08038e5c T task_stats
+08038ed8 T fcntl
+08038f78 T icmprcv
+08039a54 T icmp_destun
+08039d2c T icmp_timex
+0803a01c T icmp_du
+0803a070 T ip_init
+0803a148 T ip_bldhead
+0803a2d4 T ip_write_internal
+0803a9e8 T ip_write
+0803abf8 T ip_write2
+0803af6c T ip_raw_write
+0803b028 T ip_mymach
+0803b0cc T ip_dump
+0803b370 T iproute
+0803b53c T ip_copypkt
+0803b668 T ip_rcv
+0803b9bc T ip_rcv_phase2
+0803bf08 T ip_demux
+0803c2ac T in_addmulti
+0803c3f8 T in_delmulti
+0803c504 T lookup_mcast
+0803c568 T prep_ifaces
+0803c5e8 T netexit
+0803c610 T evtmap_setup
+0803c63c T ip_raw_open
+0803c714 T ip_raw_close
+0803c7d0 T ip_raw_input
+0803c9e4 T ip_raw_alloc
+0803ca9c T ip_raw_free
+0803cae0 T ip_raw_maxalloc
+0803cb28 T rt_lookup
+0803cc7c T add_route
+0803d020 T del_route
+0803d134 T udpdemux
+0803d8a0 T udp_send
+0803db34 T udpswap
+0803dc28 T udp_socket
+0803dcd8 T udp_alloc
+0803dd94 T udp_maxalloc
+0803ddb8 T udp_free
+0803ddfc T igmpv1_input
+0803e064 T igmpv2_input
+0803e170 T igmpv2_process_report
+0803e284 T igmpv2_process_query
+0803e444 T igmpv2_chk_set_timer
+0803e574 T igmpv2_chk4_rtr_alert_opt
+0803e6b0 T IPADDR_TO_NETP
+0803e7c4 T ip_setmoptions
+0803ed64 T ip_getmoptions
+0803ee74 T ip_freemoptions
+0803eef8 T u_mctest_init
+0803ef2c T u_mctest_run
+0803f598 T init_memdev
+0803f5e8 T md_fopen
+0803f610 T md_fclose
+0803f634 T md_fread
+0803f78c T md_fwrite
+0803f804 T md_fseek
+0803f830 T md_ftell
+0803f854 T md_fgetc
+0803f918 T md_unlink
+0803f93c T parse_ipad
+0803fc38 T inet_addr
+0803fc9c T hextoa
+0803fce8 T inet_pton
+0803fd7c T inet_ntop
+0803fe00 T print46_addr
+0803fe5c T inet46_addr
+0803ff20 T inet_setport
+0803ff8c T convert_ip
+080400c0 T tcp_cksum
+08040254 T udp_open
+08040454 T udp_close
+0804052c T in_pcballoc
+080405b4 T in_pcbdetach
+0804060c T in_pcbbind
+0804081c T in_pcbconnect
+080409fc T in_pcbdisconnect
+08040a58 T in_setsockaddr
+08040adc T in_setpeeraddr
+08040b60 T in_pcblookup
+08040db4 T set_vfopen_error
+08040de0 T get_vfopen_error
+08040e00 T vf_alloc_and_link_vop
+08040e70 T vf_alloc_buffer
+08040f38 T vf_free_buffer
+08040f88 T vfopen_locked
+080412c0 T vfopen
+08041310 T vfclose_locked
+080414cc T vfclose
+08041510 T vfflush
+08041558 T vfgets
+08041628 T vfeof
+08041678 T vunlink_flag_open_files
+080416d4 T vunlink
+080418d4 T vfread
+08041a5c T vfwrite_locked
+08041e08 T vfwrite
+08041e68 T vfseek
+08041fbc T vftell
+080420c8 T vgetc_locked
+080421c0 T vgetc
+08042208 T vfslookup_locked
+0804232c T vfslookup
+08042374 T strippath
+08042540 T isvfile_locked
+08042598 T isvfile
+080425e0 T vferror
+0804263c T vclearerr
+08042694 T prep_vfs
+080426b8 t alt_get_errno
+080426f4 T alt_fcntl
+08042818 T alt_find_file
+08042920 T alt_get_fd
+080429f8 T alt_exception_cause_generated_bad_addr
+08042a90 T atexit
+08042aa4 T atoi
+08042ab0 T _atoi_r
+08042abc T exit
+08042af0 T memalign
+08042b04 T _memalign_r
+08042c98 T malloc
+08042ca8 T free
+08042cb8 T memcmp
+08042d44 T _sprintf_r
+08042d98 T sprintf
+08042dfc T strchr
+08042f60 T strcpy
+08042fec T strncmp
+080430e8 t _strtol_l.isra.0
+0804330c T _strtol_r
+08043310 T strtol_l
+08043328 T strtol
+08043340 T ___svfprintf_internal_r
+08045458 T vprintf
+08045474 T _vprintf_r
+08045484 T _vsprintf_r
+080454d0 T vsprintf
+080454e8 T __register_exitproc
+08045578 T __call_exitprocs
+08045690 T __ssprint_r
+08045850 T ___svfiprintf_internal_r
+08046970 T _vfprintf_r
+08046974 T _exit
+080469a8 A __CTOR_END__
+080469a8 A __CTOR_LIST__
+080469a8 A __DTOR_END__
+080469a8 A __DTOR_LIST__
+080471d6 R _ctype_
+080472d7 R _ctype_b
+0804749e r zeroes.5227
+080474ae r blanks.5226
+080474d0 r p05.4024
+080474dc R __mprec_tinytens
+08047504 R __mprec_bigtens
+0804752c R __mprec_tens
+080475f4 r zeroes.5204
+08047604 r blanks.5203
+08047624 R __clz_tab
+08047734 R OSUnMapTbl
+0804b8d1 r zeroes.5208
+0804b8e1 r blanks.5207
+0804b8f1 r zeroes.5188
+0804b901 r blanks.5187
+0804b920 G controltask
+0804b938 G sslistenertask
+0804b950 G tse_mac_device
+0804ba80 g impure_data
+0804bea4 G __malloc_av_
+0804c2ac G __global_locale
+0804c420 g debug_uart
+0804c4f0 g ext_flash
+0804c5d0 g msgdma_rx
+0804c640 g msgdma_tx
+0804c6b0 g onchip_flash
+0804c7b0 G nettasks
+0804c7e0 G tcp_protosw
+0804c7f8 G udp_protosw
+0804c810 G rawip_protosw
+0804c828 G tcp_outflags
+0804c833 G tcp_backoff
+0804c840 G alt_dev_null
+0804c868 G alt_fd_list
+0804c928 G icmpdu_types
+0804c940 g dsts
+0804c958 G rtp_priority
+0804c964 G mdio
+0804c988 G mdlist
+0804ca38 G vfs_root_path
+0804cab8 G _global_impure_ptr
+0804cabc G _impure_ptr
+0804cac0 G __malloc_sbrk_base
+0804cac4 G __malloc_trim_threshold
+0804cac8 G alt_flash_dev_list
+0804cad0 g heap_end
+0804cad4 g lockid
+0804cad8 g lockid
+0804cadc G eth_tse_name
+0804cae0 G max_mac_system
+0804cae4 G alt_msgdma_list
+0804caec G altera_onchip_flash_list
+0804caf4 G alt_iniche_dev_list
+0804cafc G arp_ageout
+0804cb00 G ipmcfail_str
+0804cb04 g cksum_select
+0804cb08 G num_net_tasks
+0804cb0c G pingdata
+0804cb10 G lilbufs
+0804cb14 G lilbufsiz
+0804cb18 G bigbufs
+0804cb1c G bigbufsiz
+0804cb20 G kb_last
+0804cb24 G TCPTV_MSL
+0804cb28 G socket_defaults
+0804cb2a G tcprexmtthresh
+0804cb2c G tcp_ttl
+0804cb30 G tcp_keepidle
+0804cb34 G tcp_keepintvl
+0804cb38 G tcp_sendspace
+0804cb3c G tcp_recvspace
+0804cb40 G alt_fs_list
+0804cb48 G alt_dev_list
+0804cb50 G alt_max_fd
+0804cb54 G alt_errno
+0804cb58 G alt_priority_mask
+0804cb5c G alt_alarm_list
+0804cb64 G name
+0804cb68 G prompt
+0804cb6c G pingdelay
+0804cb70 G deflength
+0804cb74 g uid
+0804cb78 G ipRoutes
+0804cb7c g iCounter.5304
+0804cb80 G mdlist_size
+0804cb84 G pton_error
+0804cb88 G http_root_path
+0804cb8c A __bss_start
+0804cb8c A _edata
+0804cb8c b bytes_received.5850
+0804cb90 b header.5849
+0804cb98 b bytes_received.5856
+0804cb9c B to_controltask
+0804cba0 B last_flash_sector_offset
+0804cba4 B last_flash_sector
+0804cba8 b mutex
+0804cbac B to_sslistenertask
+0804cbae B mastermode
+0804cbb0 B delays
+0804cbb4 B __malloc_max_total_mem
+0804cbb8 B __malloc_max_sbrked_mem
+0804cbbc B __malloc_top_pad
+0804cbc0 B errno
+0804cbc4 B _PathLocale
+0804cbc8 B alt_argc
+0804cbcc B alt_argv
+0804cbd0 B alt_envp
+0804cbd4 b locks
+0804cbd8 B alt_envsem
+0804cbdc b locks
+0804cbe0 B alt_heapsem
+0804cbe4 B OSLockNesting
+0804cbe5 B OSRunning
+0804cbe8 B OSIdleCtr
+0804cbec B OSPrioHighRdy
+0804cbed B OSPrioCur
+0804cbf0 B OSTCBList
+0804cbf4 B OSCtxSwCtr
+0804cbf8 B OSTCBFreeList
+0804cbfc B OSTaskCtr
+0804cc00 B OSMemFreeList
+0804cc04 B OSTCBHighRdy
+0804cc08 B OSQFreeList
+0804cc0c B OSRdyGrp
+0804cc0d B OSRdyTbl
+0804cc10 B OSEventFreeList
+0804cc14 B OSIntNesting
+0804cc18 B OSTCBCur
+0804cc1c B OSTime
+0804cc20 B OSFlagFreeList
+0804cc24 B phy_profile_count
+0804cc25 B mac_group_count
+0804cc26 b tse_system_count.5331
+0804cc27 b is_init.5413
+0804cc28 B number_of_tse_mac
+0804cc2c b arp_timer
+0804cc30 B arpcache
+0804cc34 b cachetime
+0804cc38 B arpReqsIn
+0804cc3c B arpReqsOut
+0804cc40 B arpRepsIn
+0804cc44 B arpRepsOut
+0804cc48 B MaxLnh
+0804cc4c B MaxMtu
+0804cc50 B NDEBUG
+0804cc54 B ifNumber
+0804cc58 b nclosers
+0804cc5c B igmp_timers_are_running
+0804cc60 B igmp_cticks
+0804cc64 B igmp_all_hosts_group
+0804cc68 B igmp_all_rtrs_group
+0804cc6c B netmain_wakes
+0804cc70 B nettick_wakes
+0804cc74 B iniche_net_ready
+0804cc78 B to_netmain
+0804cc79 B to_nettick
+0804cc7c B tcp_sleep_timeout
+0804cc80 B cticks_initialized
+0804cc84 B irq_level
+0804cc88 b cpu_statusreg
+0804cc8c b kbd_init.4507
+0804cc90 B cticks_factor
+0804cc94 B OS_TPS
+0804cc98 B tcp_sleep_count
+0804cc9c B tcp_wakeup_count
+0804cca0 B netq_intmask
+0804cca4 B old_mode
+0804cca8 B global_TCPwakeup_setIndx
+0804ccac B cticks
+0804ccb0 B memtrapsize
+0804ccb4 B mheap_sem_ptr
+0804ccb8 B rcvdq_sem_ptr
+0804ccbc B nextslow
+0804ccc0 b in_tcptick
+0804ccc4 B mbstat
+0804cccc B select_wait
+0804ccd0 B tcpprintfs
+0804ccd4 B dropline
+0804ccd8 B tcp_optionbuf
+0804ccdc B tcp_maxidle
+0804cce0 B tcp_iss
+0804cce4 B alt_fd_list_lock
+0804cce8 B alt_irq_active
+0804ccec B _alt_tick_rate
+0804ccf0 B _alt_nticks
+0804ccf4 B activehost
+0804ccf8 b inside_pktdemux
+0804ccfc B nextppp
+0804cd00 B port_1s_callout
+0804cd04 b numtimers
+0804cd08 B icmpdu_hook
+0804cd0c B rt_mib
+0804cd10 B port_prep
+0804cd14 B net_system_exit
+0804cd18 B so_evtmap_create
+0804cd1c B so_evtmap_delete
+0804cd20 B so_evtmap
+0804cd24 B ipraw_eps
+0804cd28 B cachedRoute
+0804cd2c b usocket
+0804cd30 B firstudp
+0804cd34 B inpcb_cachehits
+0804cd38 B inpcb_cachemiss
+0804cd3c B vfsystems
+0804cd40 B vfiles
+0804cd44 B vfsfiles
+0804cd48 B vfopen_error
+0804cd4c B vfs_dir_stale
+0804cd50 B vfs_open_files
+0804cd54 B vfs_total_rw_space
+0804cd58 B vfs_total_dyna_files
+0804cd5c B alt_instruction_exception_handler
+0804cd60 b packet_data.5855
+0804cd80 b connections
+0804cd90 B __malloc_current_mallinfo
+0804cdb8 b closers
+0804cdf4 b tistring
+0804ce0c b nearBuf.4931
+0804ce2c B InitialTaskStk
+08054ab8 A _gp
+0805ae2c B OSFlagTbl
+0805b19c B OSMemTbl
+0805bdcc B OSQTbl
+0805bfac B OSTaskIdleStk
+0805c7ac B OSEventTbl
+0805d2ec B OSTCBTbl
+0805d574 B OSTCBPrioTbl
+0805d5c8 B eth_tse_if
+0805d6a8 B pmac_groups
+0805d6b8 B pphy_profiles
+0805d6d8 B tse_iniche_dev_driver_data
+0805d708 B tse
+0805d998 B arp_table
+0805da98 B netlist
+0805daac B rcvdq
+0805dac0 B netstatic
+0805ddc0 B nets
+0805ddd0 B igmpstats
+0805de34 B eth_prt_buf
+0805de46 B ipreturn
+0805de58 B lilfreeq
+0805de6c B memestats
+0805de7c B pktlog
+0805df6c B bigfreeq
+0805df80 B global_tcb_ext
+0805e07c B global_TCPwakeup_set
+0805e16c B resid_semaphore
+0805e1ac B app_semaphore
+0805e1c4 B soq
+0805e1d8 B tcpmib
+0805e214 B mbufq
+0805e228 B mfreeq
+0805e23c B tcp_saveti
+0805e264 B tcb
+0805e290 B tcpstat
+0805e370 B alt_irq
+0805e470 B intimers
+0805e4d4 B icmp_mib
+0805e53c B ip_mib
+0805e58c B udp_mib
+0805e59c A __alt_heap_start
+0805e59c A __alt_stack_base
+0805e59c A __bss_end
+0805e59c A _end
+0805e59c A end
+10000000 A __alt_data_end
+10000000 A __alt_heap_limit
+10000000 A __alt_stack_pointer
+14000000 A __alt_mem_ext_flash_avl_mem
+14000000 T __reset
+18200000 A __alt_mem_onchip_flash_data
+18400000 A __alt_mem_descriptor_memory
+18403400 A __alt_mem_calibration_ram
diff --git a/FPGA_nios/hit_pat/mem_init/meminit.qip b/FPGA_nios/hit_pat/mem_init/meminit.qip
new file mode 100644
index 0000000..7589c13
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/meminit.qip
@@ -0,0 +1 @@
+set_global_assignment -name SEARCH_PATH $::quartus(qip_path)
diff --git a/FPGA_nios/hit_pat/mem_init/meminit.spd b/FPGA_nios/hit_pat/mem_init/meminit.spd
new file mode 100644
index 0000000..b546ac5
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/meminit.spd
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+<file path="hdl_sim/q_sys_calibration_ram.dat" type="DAT" initParamName="INIT_FILE" memoryPath="calibration_ram" />
+<file path="hdl_sim/q_sys_descriptor_memory.dat" type="DAT" initParamName="INIT_FILE" memoryPath="descriptor_memory" />
+<file path="hdl_sim/onchip_flash.dat" type="DAT" initParamName="INIT_FILENAME" memoryPath="onchip_flash" />
+<file path="q_sys_calibration_ram.hex" type="HEX" initParamName="INIT_FILE" memoryPath="calibration_ram" />
+<file path="q_sys_descriptor_memory.hex" type="HEX" initParamName="INIT_FILE" memoryPath="descriptor_memory" />
+<file path="ext_flash.hex" type="HEX" memoryPath="ext_flash" />
+<file path="onchip_flash.hex" type="HEX" initParamName="INIT_FILENAME" memoryPath="onchip_flash" />
+</simPackage>
diff --git a/FPGA_nios/hit_pat/mem_init/onchip_flash.hex b/FPGA_nios/hit_pat/mem_init/onchip_flash.hex
new file mode 100644
index 0000000..1996e8f
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/onchip_flash.hex
@@ -0,0 +1 @@
+:00000001FF
diff --git a/FPGA_nios/hit_pat/mem_init/q_sys_calibration_ram.hex b/FPGA_nios/hit_pat/mem_init/q_sys_calibration_ram.hex
new file mode 100644
index 0000000..cdf6967
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/q_sys_calibration_ram.hex
@@ -0,0 +1,22 @@
+:020000020000FC
+:200000000000000000000000000000000000000000000000000000000000000000000000E0
+:200010000000000000000000000000000000000000000000000000000000000000000000D0
+:200020000000000000000000000000000000000000000000000000000000000000000000C0
+:200030000000000000000000000000000000000000000000000000000000000000000000B0
+:200040000000000000000000000000000000000000000000000000000000000000000000A0
+:20005000000000000000000000000000000000000000000000000000000000000000000090
+:20006000000000000000000000000000000000000000000000000000000000000000000080
+:20007000000000000000000000000000000000000000000000000000000000000000000070
+:20008000000000000000000000000000000000000000000000000000000000000000000060
+:20009000000000000000000000000000000000000000000000000000000000000000000050
+:2000A000000000000000000000000000000000000000000000000000000000000000000040
+:2000B000000000000000000000000000000000000000000000000000000000000000000030
+:2000C000000000000000000000000000000000000000000000000000000000000000000020
+:2000D000000000000000000000000000000000000000000000000000000000000000000010
+:2000E000000000000000000000000000000000000000000000000000000000000000000000
+:2000F0000000000000000000000000000000000000000000000000000000000000000000F0
+:200100000000000000000000000000000000000000000000000000000000000000000000DF
+:200110000000000000000000000000000000000000000000000000000000000000000000CF
+:200120000000000000000000000000000000000000000000000000000000000000000000BF
+:200130000000000000000000000000000000000000000000000000000000000000000000AF
+:00000001FF
diff --git a/FPGA_nios/hit_pat/mem_init/q_sys_descriptor_memory.hex b/FPGA_nios/hit_pat/mem_init/q_sys_descriptor_memory.hex
new file mode 100644
index 0000000..e35303d
--- /dev/null
+++ b/FPGA_nios/hit_pat/mem_init/q_sys_descriptor_memory.hex
@@ -0,0 +1,258 @@
+:020000020000FC
+:200000000000000000000000000000000000000000000000000000000000000000000000E0
+:200008000000000000000000000000000000000000000000000000000000000000000000D8
+:200010000000000000000000000000000000000000000000000000000000000000000000D0
+:200018000000000000000000000000000000000000000000000000000000000000000000C8
+:200020000000000000000000000000000000000000000000000000000000000000000000C0
+:200028000000000000000000000000000000000000000000000000000000000000000000B8
+:200030000000000000000000000000000000000000000000000000000000000000000000B0
+:200038000000000000000000000000000000000000000000000000000000000000000000A8
+:200040000000000000000000000000000000000000000000000000000000000000000000A0
+:20004800000000000000000000000000000000000000000000000000000000000000000098
+:20005000000000000000000000000000000000000000000000000000000000000000000090
+:20005800000000000000000000000000000000000000000000000000000000000000000088
+:20006000000000000000000000000000000000000000000000000000000000000000000080
+:20006800000000000000000000000000000000000000000000000000000000000000000078
+:20007000000000000000000000000000000000000000000000000000000000000000000070
+:20007800000000000000000000000000000000000000000000000000000000000000000068
+:20008000000000000000000000000000000000000000000000000000000000000000000060
+:20008800000000000000000000000000000000000000000000000000000000000000000058
+:20009000000000000000000000000000000000000000000000000000000000000000000050
+:20009800000000000000000000000000000000000000000000000000000000000000000048
+:2000A000000000000000000000000000000000000000000000000000000000000000000040
+:2000A800000000000000000000000000000000000000000000000000000000000000000038
+:2000B000000000000000000000000000000000000000000000000000000000000000000030
+:2000B800000000000000000000000000000000000000000000000000000000000000000028
+:2000C000000000000000000000000000000000000000000000000000000000000000000020
+:2000C800000000000000000000000000000000000000000000000000000000000000000018
+:2000D000000000000000000000000000000000000000000000000000000000000000000010
+:2000D800000000000000000000000000000000000000000000000000000000000000000008
+:2000E000000000000000000000000000000000000000000000000000000000000000000000
+:2000E8000000000000000000000000000000000000000000000000000000000000000000F8
+:2000F0000000000000000000000000000000000000000000000000000000000000000000F0
+:2000F8000000000000000000000000000000000000000000000000000000000000000000E8
+:200100000000000000000000000000000000000000000000000000000000000000000000DF
+:200108000000000000000000000000000000000000000000000000000000000000000000D7
+:200110000000000000000000000000000000000000000000000000000000000000000000CF
+:200118000000000000000000000000000000000000000000000000000000000000000000C7
+:200120000000000000000000000000000000000000000000000000000000000000000000BF
+:200128000000000000000000000000000000000000000000000000000000000000000000B7
+:200130000000000000000000000000000000000000000000000000000000000000000000AF
+:200138000000000000000000000000000000000000000000000000000000000000000000A7
+:2001400000000000000000000000000000000000000000000000000000000000000000009F
+:20014800000000000000000000000000000000000000000000000000000000000000000097
+:2001500000000000000000000000000000000000000000000000000000000000000000008F
+:20015800000000000000000000000000000000000000000000000000000000000000000087
+:2001600000000000000000000000000000000000000000000000000000000000000000007F
+:20016800000000000000000000000000000000000000000000000000000000000000000077
+:2001700000000000000000000000000000000000000000000000000000000000000000006F
+:20017800000000000000000000000000000000000000000000000000000000000000000067
+:2001800000000000000000000000000000000000000000000000000000000000000000005F
+:20018800000000000000000000000000000000000000000000000000000000000000000057
+:2001900000000000000000000000000000000000000000000000000000000000000000004F
+:20019800000000000000000000000000000000000000000000000000000000000000000047
+:2001A00000000000000000000000000000000000000000000000000000000000000000003F
+:2001A800000000000000000000000000000000000000000000000000000000000000000037
+:2001B00000000000000000000000000000000000000000000000000000000000000000002F
+:2001B800000000000000000000000000000000000000000000000000000000000000000027
+:2001C00000000000000000000000000000000000000000000000000000000000000000001F
+:2001C800000000000000000000000000000000000000000000000000000000000000000017
+:2001D00000000000000000000000000000000000000000000000000000000000000000000F
+:2001D800000000000000000000000000000000000000000000000000000000000000000007
+:2001E0000000000000000000000000000000000000000000000000000000000000000000FF
+:2001E8000000000000000000000000000000000000000000000000000000000000000000F7
+:2001F0000000000000000000000000000000000000000000000000000000000000000000EF
+:2001F8000000000000000000000000000000000000000000000000000000000000000000E7
+:200200000000000000000000000000000000000000000000000000000000000000000000DE
+:200208000000000000000000000000000000000000000000000000000000000000000000D6
+:200210000000000000000000000000000000000000000000000000000000000000000000CE
+:200218000000000000000000000000000000000000000000000000000000000000000000C6
+:200220000000000000000000000000000000000000000000000000000000000000000000BE
+:200228000000000000000000000000000000000000000000000000000000000000000000B6
+:200230000000000000000000000000000000000000000000000000000000000000000000AE
+:200238000000000000000000000000000000000000000000000000000000000000000000A6
+:2002400000000000000000000000000000000000000000000000000000000000000000009E
+:20024800000000000000000000000000000000000000000000000000000000000000000096
+:2002500000000000000000000000000000000000000000000000000000000000000000008E
+:20025800000000000000000000000000000000000000000000000000000000000000000086
+:2002600000000000000000000000000000000000000000000000000000000000000000007E
+:20026800000000000000000000000000000000000000000000000000000000000000000076
+:2002700000000000000000000000000000000000000000000000000000000000000000006E
+:20027800000000000000000000000000000000000000000000000000000000000000000066
+:2002800000000000000000000000000000000000000000000000000000000000000000005E
+:20028800000000000000000000000000000000000000000000000000000000000000000056
+:2002900000000000000000000000000000000000000000000000000000000000000000004E
+:20029800000000000000000000000000000000000000000000000000000000000000000046
+:2002A00000000000000000000000000000000000000000000000000000000000000000003E
+:2002A800000000000000000000000000000000000000000000000000000000000000000036
+:2002B00000000000000000000000000000000000000000000000000000000000000000002E
+:2002B800000000000000000000000000000000000000000000000000000000000000000026
+:2002C00000000000000000000000000000000000000000000000000000000000000000001E
+:2002C800000000000000000000000000000000000000000000000000000000000000000016
+:2002D00000000000000000000000000000000000000000000000000000000000000000000E
+:2002D800000000000000000000000000000000000000000000000000000000000000000006
+:2002E0000000000000000000000000000000000000000000000000000000000000000000FE
+:2002E8000000000000000000000000000000000000000000000000000000000000000000F6
+:2002F0000000000000000000000000000000000000000000000000000000000000000000EE
+:2002F8000000000000000000000000000000000000000000000000000000000000000000E6
+:200300000000000000000000000000000000000000000000000000000000000000000000DD
+:200308000000000000000000000000000000000000000000000000000000000000000000D5
+:200310000000000000000000000000000000000000000000000000000000000000000000CD
+:200318000000000000000000000000000000000000000000000000000000000000000000C5
+:200320000000000000000000000000000000000000000000000000000000000000000000BD
+:200328000000000000000000000000000000000000000000000000000000000000000000B5
+:200330000000000000000000000000000000000000000000000000000000000000000000AD
+:200338000000000000000000000000000000000000000000000000000000000000000000A5
+:2003400000000000000000000000000000000000000000000000000000000000000000009D
+:20034800000000000000000000000000000000000000000000000000000000000000000095
+:2003500000000000000000000000000000000000000000000000000000000000000000008D
+:20035800000000000000000000000000000000000000000000000000000000000000000085
+:2003600000000000000000000000000000000000000000000000000000000000000000007D
+:20036800000000000000000000000000000000000000000000000000000000000000000075
+:2003700000000000000000000000000000000000000000000000000000000000000000006D
+:20037800000000000000000000000000000000000000000000000000000000000000000065
+:2003800000000000000000000000000000000000000000000000000000000000000000005D
+:20038800000000000000000000000000000000000000000000000000000000000000000055
+:2003900000000000000000000000000000000000000000000000000000000000000000004D
+:20039800000000000000000000000000000000000000000000000000000000000000000045
+:2003A00000000000000000000000000000000000000000000000000000000000000000003D
+:2003A800000000000000000000000000000000000000000000000000000000000000000035
+:2003B00000000000000000000000000000000000000000000000000000000000000000002D
+:2003B800000000000000000000000000000000000000000000000000000000000000000025
+:2003C00000000000000000000000000000000000000000000000000000000000000000001D
+:2003C800000000000000000000000000000000000000000000000000000000000000000015
+:2003D00000000000000000000000000000000000000000000000000000000000000000000D
+:2003D800000000000000000000000000000000000000000000000000000000000000000005
+:2003E0000000000000000000000000000000000000000000000000000000000000000000FD
+:2003E8000000000000000000000000000000000000000000000000000000000000000000F5
+:2003F0000000000000000000000000000000000000000000000000000000000000000000ED
+:2003F8000000000000000000000000000000000000000000000000000000000000000000E5
+:200400000000000000000000000000000000000000000000000000000000000000000000DC
+:200408000000000000000000000000000000000000000000000000000000000000000000D4
+:200410000000000000000000000000000000000000000000000000000000000000000000CC
+:200418000000000000000000000000000000000000000000000000000000000000000000C4
+:200420000000000000000000000000000000000000000000000000000000000000000000BC
+:200428000000000000000000000000000000000000000000000000000000000000000000B4
+:200430000000000000000000000000000000000000000000000000000000000000000000AC
+:200438000000000000000000000000000000000000000000000000000000000000000000A4
+:2004400000000000000000000000000000000000000000000000000000000000000000009C
+:20044800000000000000000000000000000000000000000000000000000000000000000094
+:2004500000000000000000000000000000000000000000000000000000000000000000008C
+:20045800000000000000000000000000000000000000000000000000000000000000000084
+:2004600000000000000000000000000000000000000000000000000000000000000000007C
+:20046800000000000000000000000000000000000000000000000000000000000000000074
+:2004700000000000000000000000000000000000000000000000000000000000000000006C
+:20047800000000000000000000000000000000000000000000000000000000000000000064
+:2004800000000000000000000000000000000000000000000000000000000000000000005C
+:20048800000000000000000000000000000000000000000000000000000000000000000054
+:2004900000000000000000000000000000000000000000000000000000000000000000004C
+:20049800000000000000000000000000000000000000000000000000000000000000000044
+:2004A00000000000000000000000000000000000000000000000000000000000000000003C
+:2004A800000000000000000000000000000000000000000000000000000000000000000034
+:2004B00000000000000000000000000000000000000000000000000000000000000000002C
+:2004B800000000000000000000000000000000000000000000000000000000000000000024
+:2004C00000000000000000000000000000000000000000000000000000000000000000001C
+:2004C800000000000000000000000000000000000000000000000000000000000000000014
+:2004D00000000000000000000000000000000000000000000000000000000000000000000C
+:2004D800000000000000000000000000000000000000000000000000000000000000000004
+:2004E0000000000000000000000000000000000000000000000000000000000000000000FC
+:2004E8000000000000000000000000000000000000000000000000000000000000000000F4
+:2004F0000000000000000000000000000000000000000000000000000000000000000000EC
+:2004F8000000000000000000000000000000000000000000000000000000000000000000E4
+:200500000000000000000000000000000000000000000000000000000000000000000000DB
+:200508000000000000000000000000000000000000000000000000000000000000000000D3
+:200510000000000000000000000000000000000000000000000000000000000000000000CB
+:200518000000000000000000000000000000000000000000000000000000000000000000C3
+:200520000000000000000000000000000000000000000000000000000000000000000000BB
+:200528000000000000000000000000000000000000000000000000000000000000000000B3
+:200530000000000000000000000000000000000000000000000000000000000000000000AB
+:200538000000000000000000000000000000000000000000000000000000000000000000A3
+:2005400000000000000000000000000000000000000000000000000000000000000000009B
+:20054800000000000000000000000000000000000000000000000000000000000000000093
+:2005500000000000000000000000000000000000000000000000000000000000000000008B
+:20055800000000000000000000000000000000000000000000000000000000000000000083
+:2005600000000000000000000000000000000000000000000000000000000000000000007B
+:20056800000000000000000000000000000000000000000000000000000000000000000073
+:2005700000000000000000000000000000000000000000000000000000000000000000006B
+:20057800000000000000000000000000000000000000000000000000000000000000000063
+:2005800000000000000000000000000000000000000000000000000000000000000000005B
+:20058800000000000000000000000000000000000000000000000000000000000000000053
+:2005900000000000000000000000000000000000000000000000000000000000000000004B
+:20059800000000000000000000000000000000000000000000000000000000000000000043
+:2005A00000000000000000000000000000000000000000000000000000000000000000003B
+:2005A800000000000000000000000000000000000000000000000000000000000000000033
+:2005B00000000000000000000000000000000000000000000000000000000000000000002B
+:2005B800000000000000000000000000000000000000000000000000000000000000000023
+:2005C00000000000000000000000000000000000000000000000000000000000000000001B
+:2005C800000000000000000000000000000000000000000000000000000000000000000013
+:2005D00000000000000000000000000000000000000000000000000000000000000000000B
+:2005D800000000000000000000000000000000000000000000000000000000000000000003
+:2005E0000000000000000000000000000000000000000000000000000000000000000000FB
+:2005E8000000000000000000000000000000000000000000000000000000000000000000F3
+:2005F0000000000000000000000000000000000000000000000000000000000000000000EB
+:2005F8000000000000000000000000000000000000000000000000000000000000000000E3
+:200600000000000000000000000000000000000000000000000000000000000000000000DA
+:200608000000000000000000000000000000000000000000000000000000000000000000D2
+:200610000000000000000000000000000000000000000000000000000000000000000000CA
+:200618000000000000000000000000000000000000000000000000000000000000000000C2
+:200620000000000000000000000000000000000000000000000000000000000000000000BA
+:200628000000000000000000000000000000000000000000000000000000000000000000B2
+:200630000000000000000000000000000000000000000000000000000000000000000000AA
+:200638000000000000000000000000000000000000000000000000000000000000000000A2
+:2006400000000000000000000000000000000000000000000000000000000000000000009A
+:20064800000000000000000000000000000000000000000000000000000000000000000092
+:2006500000000000000000000000000000000000000000000000000000000000000000008A
+:20065800000000000000000000000000000000000000000000000000000000000000000082
+:2006600000000000000000000000000000000000000000000000000000000000000000007A
+:20066800000000000000000000000000000000000000000000000000000000000000000072
+:2006700000000000000000000000000000000000000000000000000000000000000000006A
+:20067800000000000000000000000000000000000000000000000000000000000000000062
+:2006800000000000000000000000000000000000000000000000000000000000000000005A
+:20068800000000000000000000000000000000000000000000000000000000000000000052
+:2006900000000000000000000000000000000000000000000000000000000000000000004A
+:20069800000000000000000000000000000000000000000000000000000000000000000042
+:2006A00000000000000000000000000000000000000000000000000000000000000000003A
+:2006A800000000000000000000000000000000000000000000000000000000000000000032
+:2006B00000000000000000000000000000000000000000000000000000000000000000002A
+:2006B800000000000000000000000000000000000000000000000000000000000000000022
+:2006C00000000000000000000000000000000000000000000000000000000000000000001A
+:2006C800000000000000000000000000000000000000000000000000000000000000000012
+:2006D00000000000000000000000000000000000000000000000000000000000000000000A
+:2006D800000000000000000000000000000000000000000000000000000000000000000002
+:2006E0000000000000000000000000000000000000000000000000000000000000000000FA
+:2006E8000000000000000000000000000000000000000000000000000000000000000000F2
+:2006F0000000000000000000000000000000000000000000000000000000000000000000EA
+:2006F8000000000000000000000000000000000000000000000000000000000000000000E2
+:200700000000000000000000000000000000000000000000000000000000000000000000D9
+:200708000000000000000000000000000000000000000000000000000000000000000000D1
+:200710000000000000000000000000000000000000000000000000000000000000000000C9
+:200718000000000000000000000000000000000000000000000000000000000000000000C1
+:200720000000000000000000000000000000000000000000000000000000000000000000B9
+:200728000000000000000000000000000000000000000000000000000000000000000000B1
+:200730000000000000000000000000000000000000000000000000000000000000000000A9
+:200738000000000000000000000000000000000000000000000000000000000000000000A1
+:20074000000000000000000000000000000000000000000000000000000000000000000099
+:20074800000000000000000000000000000000000000000000000000000000000000000091
+:20075000000000000000000000000000000000000000000000000000000000000000000089
+:20075800000000000000000000000000000000000000000000000000000000000000000081
+:20076000000000000000000000000000000000000000000000000000000000000000000079
+:20076800000000000000000000000000000000000000000000000000000000000000000071
+:20077000000000000000000000000000000000000000000000000000000000000000000069
+:20077800000000000000000000000000000000000000000000000000000000000000000061
+:20078000000000000000000000000000000000000000000000000000000000000000000059
+:20078800000000000000000000000000000000000000000000000000000000000000000051
+:20079000000000000000000000000000000000000000000000000000000000000000000049
+:20079800000000000000000000000000000000000000000000000000000000000000000041
+:2007A000000000000000000000000000000000000000000000000000000000000000000039
+:2007A800000000000000000000000000000000000000000000000000000000000000000031
+:2007B000000000000000000000000000000000000000000000000000000000000000000029
+:2007B800000000000000000000000000000000000000000000000000000000000000000021
+:2007C000000000000000000000000000000000000000000000000000000000000000000019
+:2007C800000000000000000000000000000000000000000000000000000000000000000011
+:2007D000000000000000000000000000000000000000000000000000000000000000000009
+:2007D800000000000000000000000000000000000000000000000000000000000000000001
+:2007E0000000000000000000000000000000000000000000000000000000000000000000F9
+:2007E8000000000000000000000000000000000000000000000000000000000000000000F1
+:2007F0000000000000000000000000000000000000000000000000000000000000000000E9
+:2007F8000000000000000000000000000000000000000000000000000000000000000000E1
+:00000001FF
diff --git a/FPGA_nios/hit_pat/obj/default/src/control.d b/FPGA_nios/hit_pat/obj/default/src/control.d
new file mode 100644
index 0000000..b2ac93f
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/control.d
@@ -0,0 +1,140 @@
+obj/default/src/control.o: src/control.c \
+ ../hit_pat_bsp/HAL/inc/includes.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_irq.h ../hit_pat_bsp/HAL/inc/nios2.h \
+ ../hit_pat_bsp/HAL/inc/alt_types.h ../hit_pat_bsp/system.h \
+ ../hit_pat_bsp/linker.h ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/profiler.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/nptcp.h ../hit_pat_bsp/iniche/src/h/mbuf.h \
+ ../hit_pat_bsp/iniche/src/h/socket.h \
+ ../hit_pat_bsp/iniche/src/h/sockvar.h \
+ ../hit_pat_bsp/iniche/src/h/sockcall.h \
+ ../hit_pat_bsp/iniche/src/h/bsdsock.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h inc/socket_server.h inc/control.h \
+ inc/dev_commands.h inc/sensor.h inc/udpgen.h inc/utils.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/nptcp.h:
+
+../hit_pat_bsp/iniche/src/h/mbuf.h:
+
+../hit_pat_bsp/iniche/src/h/socket.h:
+
+../hit_pat_bsp/iniche/src/h/sockvar.h:
+
+../hit_pat_bsp/iniche/src/h/sockcall.h:
+
+../hit_pat_bsp/iniche/src/h/bsdsock.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
+
+inc/socket_server.h:
+
+inc/control.h:
+
+inc/dev_commands.h:
+
+inc/sensor.h:
+
+inc/udpgen.h:
+
+inc/utils.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/main.d b/FPGA_nios/hit_pat/obj/default/src/main.d
new file mode 100644
index 0000000..1640688
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/main.d
@@ -0,0 +1,99 @@
+obj/default/src/main.o: src/main.c ../hit_pat_bsp/HAL/inc/includes.h \
+ ../hit_pat_bsp/HAL/inc/os_cpu.h ../hit_pat_bsp/HAL/inc/sys/alt_irq.h \
+ ../hit_pat_bsp/HAL/inc/nios2.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/system.h ../hit_pat_bsp/linker.h \
+ ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ inc/socket_server.h inc/control.h inc/dev_commands.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/q.h ../hit_pat_bsp/iniche/src/h/profiler.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+inc/socket_server.h:
+
+inc/control.h:
+
+inc/dev_commands.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/network_utilities.d b/FPGA_nios/hit_pat/obj/default/src/network_utilities.d
new file mode 100644
index 0000000..278e4c4
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/network_utilities.d
@@ -0,0 +1,121 @@
+obj/default/src/network_utilities.o: src/network_utilities.c \
+ ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_flash.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_flash_types.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_cache.h ../hit_pat_bsp/HAL/inc/includes.h \
+ ../hit_pat_bsp/HAL/inc/os_cpu.h ../hit_pat_bsp/HAL/inc/sys/alt_irq.h \
+ ../hit_pat_bsp/HAL/inc/nios2.h ../hit_pat_bsp/system.h \
+ ../hit_pat_bsp/linker.h ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/iniche/inc/alt_iniche_dev.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/profiler.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/nptcp.h ../hit_pat_bsp/iniche/src/h/mbuf.h \
+ ../hit_pat_bsp/iniche/src/h/socket.h \
+ ../hit_pat_bsp/iniche/src/h/sockvar.h \
+ ../hit_pat_bsp/iniche/src/h/sockcall.h \
+ ../hit_pat_bsp/iniche/src/h/bsdsock.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h inc/network_utilities.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h inc/socket_server.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_flash.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_flash_types.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_cache.h:
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/iniche/inc/alt_iniche_dev.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/nptcp.h:
+
+../hit_pat_bsp/iniche/src/h/mbuf.h:
+
+../hit_pat_bsp/iniche/src/h/socket.h:
+
+../hit_pat_bsp/iniche/src/h/sockvar.h:
+
+../hit_pat_bsp/iniche/src/h/sockcall.h:
+
+../hit_pat_bsp/iniche/src/h/bsdsock.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+inc/network_utilities.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h:
+
+inc/socket_server.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/sensor.d b/FPGA_nios/hit_pat/obj/default/src/sensor.d
new file mode 100644
index 0000000..44718a3
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/sensor.d
@@ -0,0 +1,140 @@
+obj/default/src/sensor.o: src/sensor.c ../hit_pat_bsp/HAL/inc/includes.h \
+ ../hit_pat_bsp/HAL/inc/os_cpu.h ../hit_pat_bsp/HAL/inc/sys/alt_irq.h \
+ ../hit_pat_bsp/HAL/inc/nios2.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/system.h ../hit_pat_bsp/linker.h \
+ ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_dev.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_sem.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_flag.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/q.h ../hit_pat_bsp/iniche/src/h/profiler.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h inc/utils.h inc/dev_commands.h \
+ inc/sensor.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_dev.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_sem.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_flag.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
+
+inc/utils.h:
+
+inc/dev_commands.h:
+
+inc/sensor.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/socket_server.d b/FPGA_nios/hit_pat/obj/default/src/socket_server.d
new file mode 100644
index 0000000..b55fd77
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/socket_server.d
@@ -0,0 +1,124 @@
+obj/default/src/socket_server.o: src/socket_server.c \
+ ../hit_pat_bsp/HAL/inc/includes.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_irq.h ../hit_pat_bsp/HAL/inc/nios2.h \
+ ../hit_pat_bsp/HAL/inc/alt_types.h ../hit_pat_bsp/system.h \
+ ../hit_pat_bsp/linker.h ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ inc/socket_server.h ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/profiler.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/nptcp.h ../hit_pat_bsp/iniche/src/h/mbuf.h \
+ ../hit_pat_bsp/iniche/src/h/socket.h \
+ ../hit_pat_bsp/iniche/src/h/sockvar.h \
+ ../hit_pat_bsp/iniche/src/h/sockcall.h \
+ ../hit_pat_bsp/iniche/src/h/bsdsock.h \
+ ../hit_pat_bsp/iniche/src/h/tcpport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+inc/socket_server.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/nptcp.h:
+
+../hit_pat_bsp/iniche/src/h/mbuf.h:
+
+../hit_pat_bsp/iniche/src/h/socket.h:
+
+../hit_pat_bsp/iniche/src/h/sockvar.h:
+
+../hit_pat_bsp/iniche/src/h/sockcall.h:
+
+../hit_pat_bsp/iniche/src/h/bsdsock.h:
+
+../hit_pat_bsp/iniche/src/h/tcpport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/tse_my_system.d b/FPGA_nios/hit_pat/obj/default/src/tse_my_system.d
new file mode 100644
index 0000000..321c605
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/tse_my_system.d
@@ -0,0 +1,99 @@
+obj/default/src/tse_my_system.o: src/tse_my_system.c \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h ../hit_pat_bsp/system.h \
+ ../hit_pat_bsp/linker.h ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/HAL/inc/includes.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_irq.h ../hit_pat_bsp/HAL/inc/nios2.h \
+ ../hit_pat_bsp/HAL/inc/alt_types.h ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_tse.h \
+ ../hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_dev.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_sem.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_flag.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_tse.h
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_tse.h:
+
+../hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_dev.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_sem.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_flag.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_tse.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/udpgen.d b/FPGA_nios/hit_pat/obj/default/src/udpgen.d
new file mode 100644
index 0000000..d926cde
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/udpgen.d
@@ -0,0 +1,137 @@
+obj/default/src/udpgen.o: src/udpgen.c ../hit_pat_bsp/HAL/inc/includes.h \
+ ../hit_pat_bsp/HAL/inc/os_cpu.h ../hit_pat_bsp/HAL/inc/sys/alt_irq.h \
+ ../hit_pat_bsp/HAL/inc/nios2.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/system.h ../hit_pat_bsp/linker.h \
+ ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_dev.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_sem.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h \
+ ../hit_pat_bsp/UCOSII/inc/os/alt_flag.h \
+ ../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/q.h ../hit_pat_bsp/iniche/src/h/profiler.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h inc/utils.h inc/udpgen.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_dev.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_sem.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h:
+
+../hit_pat_bsp/UCOSII/inc/os/alt_flag.h:
+
+../hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
+
+inc/utils.h:
+
+inc/udpgen.h:
diff --git a/FPGA_nios/hit_pat/obj/default/src/utils.d b/FPGA_nios/hit_pat/obj/default/src/utils.d
new file mode 100644
index 0000000..037f944
--- /dev/null
+++ b/FPGA_nios/hit_pat/obj/default/src/utils.d
@@ -0,0 +1,108 @@
+obj/default/src/utils.o: src/utils.c ../hit_pat_bsp/HAL/inc/includes.h \
+ ../hit_pat_bsp/HAL/inc/os_cpu.h ../hit_pat_bsp/HAL/inc/sys/alt_irq.h \
+ ../hit_pat_bsp/HAL/inc/nios2.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/system.h ../hit_pat_bsp/linker.h \
+ ../hit_pat_bsp/UCOSII/inc/os_cfg.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_alarm.h \
+ ../hit_pat_bsp/HAL/inc/sys/alt_llist.h \
+ ../hit_pat_bsp/HAL/inc/priv/alt_alarm.h \
+ ../hit_pat_bsp/UCOSII/inc/ucos_ii.h ../hit_pat_bsp/HAL/inc/os_cpu.h \
+ ../hit_pat_bsp/HAL/inc/io.h ../hit_pat_bsp/HAL/inc/alt_types.h \
+ ../hit_pat_bsp/iniche/src/h/nios2/ipport.h \
+ ../hit_pat_bsp/iniche/src/h/nptypes.h \
+ ../hit_pat_bsp/iniche/src/h/tk_crnos.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/nios2/osport.h ../hit_pat_bsp/iniche/src/h/q.h \
+ ../hit_pat_bsp/iniche/src/h/netbuf.h ../hit_pat_bsp/iniche/src/h/net.h \
+ ../hit_pat_bsp/iniche/src/h/q.h ../hit_pat_bsp/iniche/src/h/profiler.h \
+ ../hit_pat_bsp/iniche/src/h/arp.h ../hit_pat_bsp/iniche/src/h/ip.h \
+ ../hit_pat_bsp/iniche/src/h/icmp.h ../hit_pat_bsp/iniche/src/h/udp.h \
+ ../hit_pat_bsp/iniche/src/h/nvparms.h \
+ ../hit_pat_bsp/iniche/src/h/libport.h \
+ ../hit_pat_bsp/iniche/src/h/nvfsio.h ../hit_pat_bsp/iniche/src/h/menu.h \
+ ../hit_pat_bsp/iniche/src/h/in_utils.h \
+ ../hit_pat_bsp/iniche/src/h/app_ping.h \
+ ../hit_pat_bsp/iniche/src/h/task.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h \
+ ../hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h inc/utils.h \
+ inc/sensor.h
+
+../hit_pat_bsp/HAL/inc/includes.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_irq.h:
+
+../hit_pat_bsp/HAL/inc/nios2.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/system.h:
+
+../hit_pat_bsp/linker.h:
+
+../hit_pat_bsp/UCOSII/inc/os_cfg.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_alarm.h:
+
+../hit_pat_bsp/HAL/inc/sys/alt_llist.h:
+
+../hit_pat_bsp/HAL/inc/priv/alt_alarm.h:
+
+../hit_pat_bsp/UCOSII/inc/ucos_ii.h:
+
+../hit_pat_bsp/HAL/inc/os_cpu.h:
+
+../hit_pat_bsp/HAL/inc/io.h:
+
+../hit_pat_bsp/HAL/inc/alt_types.h:
+
+../hit_pat_bsp/iniche/src/h/nios2/ipport.h:
+
+../hit_pat_bsp/iniche/src/h/nptypes.h:
+
+../hit_pat_bsp/iniche/src/h/tk_crnos.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/nios2/osport.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/netbuf.h:
+
+../hit_pat_bsp/iniche/src/h/net.h:
+
+../hit_pat_bsp/iniche/src/h/q.h:
+
+../hit_pat_bsp/iniche/src/h/profiler.h:
+
+../hit_pat_bsp/iniche/src/h/arp.h:
+
+../hit_pat_bsp/iniche/src/h/ip.h:
+
+../hit_pat_bsp/iniche/src/h/icmp.h:
+
+../hit_pat_bsp/iniche/src/h/udp.h:
+
+../hit_pat_bsp/iniche/src/h/nvparms.h:
+
+../hit_pat_bsp/iniche/src/h/libport.h:
+
+../hit_pat_bsp/iniche/src/h/nvfsio.h:
+
+../hit_pat_bsp/iniche/src/h/menu.h:
+
+../hit_pat_bsp/iniche/src/h/in_utils.h:
+
+../hit_pat_bsp/iniche/src/h/app_ping.h:
+
+../hit_pat_bsp/iniche/src/h/task.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h:
+
+../hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h:
+
+inc/utils.h:
+
+inc/sensor.h:
diff --git a/FPGA_nios/hit_pat/onchip_flash.flash b/FPGA_nios/hit_pat/onchip_flash.flash
new file mode 100644
index 0000000..974c5a9
--- /dev/null
+++ b/FPGA_nios/hit_pat/onchip_flash.flash
@@ -0,0 +1,2 @@
+S00600002D454C3B
+S70500000000FA
\ No newline at end of file
diff --git a/FPGA_nios/hit_pat/readme.txt b/FPGA_nios/hit_pat/readme.txt
new file mode 100644
index 0000000..953ca77
--- /dev/null
+++ b/FPGA_nios/hit_pat/readme.txt
@@ -0,0 +1,101 @@
+Readme - Simple Socket Server Software Example
+
+DESCRIPTION:	
+A Simple Socket Server that controls development board LEDs. 
+
+This software application may be targeted for TSE design having RGMII interface 
+media between Ethernet MAC and Ethernet Phy. 
+
+RGMII (Reduced Gigabit Media Independent Interface) is intended to be an 
+alternative to GMII. The principle objective of RGMII is to reduce the number 
+of pins from 22 (GMII) down to 12 in a cost-effective manner. RGMII interface 
+require a 1.5 to 2ns delay (90 degree phase shift) on the transmitted clock 
+over the data bus. This timing requirement can be achieved through a PCB trace 
+delay, or optionally of introducing the delay on-chip at the physical layer 
+transceiver chip. This example software include a configuration file to enable 
+the on-chip delay method.
+
+Requirements:
+  -RTOS Type - MicroC/OS-II
+  -Software Component - NicheStack TCP/IP Stack - Nios II Edition
+  -Period System Timer - SYS_CLK_TIMER
+
+PERIPHERALS USED:
+This example exercises the following peripherals:
+- Ethernet MAC 
+- PIO, 8-bit output (named "led_pio" in SOPC Builder)
+- PIO, 16-bit output (named "seven_seg_pio" in SOPC Builder) (optional)
+- STDOUT device (UART or JTAG UART)
+
+SOFTWARE SOURCE FILES:
+This example includes the following software source files:
+
+- iniche_init.c: Contains main() and SSSInitialTask() to initialize NicheStack 
+and then create the other tasks once network has been properly initialized.
+Tasks which will use sockets, such as the SSSSimpleSocketServerTask() in this 
+example, must be created with TK_NEWTASK.  All other tasks can be created by directly
+calling the MicroC/OS-II API to create a task, i.e. OSTaskCreateExt().
+
+- simple_socket_server.c: Implementation of a simple_socket_server including all necessary sockets
+calls to handle a single socket connection & process received commands.
+
+- network_utilities.c: Contains MAC address and IP address routines to
+manage addressing. These are used by NicheStack during initialization, but are
+implementation-specific (you set your MAC address to whatever you want.. or read
+it from your own special non-volatile memory.
+
+- network_utilities.h: Contains prototype for function get_board_mac_addr().
+
+- led.c: Contains tasks to manage board LED commands and update LED displays.
+LEDManagementTask interprets commands, and toggles the row of 8 LEDS or signals the 
+LED7SegLightshowTask in response to commands received from the host running telnet.
+The LEDManagementTask reads data from a MicroC/OS-II SSSLEDCommandQ Queue which
+receives its data from the SSSSimpleSocketServerTask.  LED7SegLightshowTask controls the 
+7-segment display.    
+
+- simple_socket_server.h: Definitions for the entire example application.
+
+- alt_error_handler.h: Definitions for 3 error handlers, one each for MicroC-OS/II, Network, 
+and Simple Socket Server Application.
+
+- alt_error_handler.c: Implementation for 3 error handlers, one each for MicroC-OS/II, 
+Network, and Simple Socket Server Application.
+
+- tse_my_system.c: Allow customization of tse_mac_device[] structure through global array initialization.
+If using marvell phy, this can be set to RGMII mode in this file.  Other Phys will operate in one mode or 
+the other depending on thier implementation in driver file altera_avalon_tse.c.
+
+BOARD/HOST REQUIREMENTS:
+Must contain a supported phy, and use a quartus project that uses tse and msgdma.
+
+This example requires an Ethernet cable connected to the development board's 
+RJ-45 jack, and a JTAG connection with the development board. If the host 
+communication settings are changed from JTAG UART (default) to use a
+conventional UART, a serial cable between board DB-9 connector  and the host is
+required. 
+
+If DHCP is available (and enabled in the Software component configuration page, from
+the BSP properties configuration), NicheStack TCP/IP Stack will attempt 
+to obtain an IP address from a DHCP server. Otherwise, a static IP address (defined in 
+Simple_Socket_Server.h) will be assigned after a DHCP timeout.  
+
+ADDITIONAL INFORMATION:
+
+This is an example socket server using NicheStack TCP/IP Stack on MicroC/OS-II. The server
+implements simple commands to control board LEDs through a separate MicroC/OS-II
+task. It is in no way a complete implementation of a telnet server.
+
+A good introduction to sockets programming is the book "Unix Network Programming" by 
+Richard Stevens. Additionally, the text "Sockets in C", by Donahoo & Calvert, is a concise 
+& inexpensive text for getting started with sockets programming.
+
+This example will not run on the Instruction Set Simulator (ISS).
+
+Once the simple socket server example is running and has obtained an IP address (shown 
+in the terminal window of Nios II Software Build Tools for Eclipse), 
+you can connect to it over a network by typing the 
+following command in a command shell on a development host:
+
+  telnet <ip address> 30
+
+This command will try to connect to the Simple Socket Server using port 30.
diff --git a/FPGA_nios/hit_pat/src/control.c b/FPGA_nios/hit_pat/src/control.c
new file mode 100644
index 0000000..4611a64
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/control.c
@@ -0,0 +1,390 @@
+/*
+ * control.c
+ *
+ *  Created on: Aug 14, 2017
+ *      Author: mdziewiecki
+ */
+
+
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+
+/* MicroC/OS-II definitions */
+#include "includes.h"
+
+#include <system.h>
+#include <io.h>
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "tcpport.h"
+#include "libport.h"
+#include "osport.h"
+
+#include "socket_server.h"
+#include "control.h"
+#include "sensor.h"
+#include "udpgen.h"
+#include "utils.h"
+
+// ****************************
+
+extern   NET   nets[MAXNETS];    /* pointers to the static network structs */
+
+// ****************************
+
+void control_delay()
+{
+	TK_SLEEP(1);
+}
+
+
+// ****************************
+
+	//simple reply
+void control_pong(command_header* header)
+{
+	command_header tmp;
+	tmp = *header;
+	swap_bytes((char*)(void*)(&tmp), sizeof(tmp));
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(header));
+}
+
+void control_process_snapshot()
+{
+	command_header header = {.marker = 0x5555, .command = COMMAND_SLOWCTRL_SNAPSHOT,
+							 .length = 0};	//SLOWCTRL_ADC_CHANNEL_COUNT * sizeof(SLOWCTRL_ADC_DATA_TYPE) / sizeof(unsigned short)};
+	swap_bytes((char*)(void*)(&header), sizeof(header));
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(&header));
+	//ethernet_write(0, SLOWCTRL_ADC_CHANNEL_COUNT*sizeof(SLOWCTRL_ADC_DATA_TYPE), (unsigned char*)slowctrl_adc_buffer);
+}
+
+	//helper for the one below
+int check_arp(struct arptabent * arp_entry, ip_addr ip)
+{
+	if (arp_entry->t_pro_addr != ip)
+		return 0;	//bad IP
+
+	for (int i = 0; i < 6; i++)
+		if (arp_entry->t_phy_addr[i] != 0)
+			return 1;	//non-zero MAC
+
+	return 0;
+}
+
+void control_process_config_peer(unsigned short* data)
+{
+	ip_addr ip = 0;
+	ip_addr srcip = 0;
+	int i;
+	command_header header = {.marker = 0x5555, .command = COMMAND_DAQ_CONFIG_PEER, .length = 0};
+
+	for (i = 0; i < 4; i++)
+		ip = (ip << 8) | (unsigned char)(data[3-i] & 0x00FF);
+
+	//daq_configure_peer_addr(ip, data[4]);
+
+	printf("Querying ARP for %d.%d.%d.%d ...\n",data[0],data[1],data[2],data[3]);
+
+	struct arptabent * arp_entry = find_oldest_arp(ip);
+
+	int pingseq = 0;
+	while (!check_arp(arp_entry, ip))	//big loop for pinging 10 times
+	{
+		printf("ARP entry could not be found, pinging!\n");
+			//ping the peer to ARP it.
+		icmpEcho(ip, NULL, 8, pingseq++);
+
+		for (int i = 0; (i < 5) && (!check_arp(arp_entry, ip)); i++)	//small loop for waiting 5 times after each ping
+		{
+			TK_SLEEP(10);
+			arp_entry = find_oldest_arp(ip);
+		}
+
+		if (pingseq > 10)
+		{
+			printf("Could not resolve MAC! The result below is random!\n");
+			break;
+		}
+	}
+
+	printf("Peer MAC is %02x %02x %02x %02x %02x %02x\n",
+			arp_entry->t_phy_addr[0], arp_entry->t_phy_addr[1], arp_entry->t_phy_addr[2],
+			arp_entry->t_phy_addr[3], arp_entry->t_phy_addr[4], arp_entry->t_phy_addr[5]);
+
+	srcip = nets[0]->n_ipaddr;
+	swap_quad((unsigned char*)(void*)(&srcip), 4);	//UDP generator needs such a format
+	swap_quad((unsigned char*)(void*)(&ip), 4);
+
+	//set up udpgen with correct values
+	udpgen_set_size(UDP_GENERATOR_BASE, 167);	//sensor_interface.v:39
+	udpgen_set_srcip(UDP_GENERATOR_BASE, srcip);
+	udpgen_set_dstip(UDP_GENERATOR_BASE, ip);
+	udpgen_set_srcport(UDP_GENERATOR_BASE, DATA_PORT);
+	udpgen_set_dstport(UDP_GENERATOR_BASE, data[4]);
+	udpgen_set_dstmac_a(UDP_GENERATOR_BASE, arp_entry->t_phy_addr);
+
+	swap_bytes((unsigned char*)(void*)(&header), sizeof(header));
+	ethernet_write(0, sizeof(command_header), (unsigned char*)(&header));
+}
+
+
+
+// ****************************
+
+	//Receive command header. Return (without loosing data!) if number of received bytes is insufficient.
+unsigned char control_get_header(command_header** result)
+{
+	static command_header header;
+	static unsigned int bytes_received = 0;
+
+	bytes_received += ethernet_read(0, sizeof(command_header)-bytes_received, (unsigned char*)(&header) + bytes_received);
+
+	if (bytes_received < sizeof(command_header))
+		return 0;
+
+	swap_bytes((unsigned char*)(void*)(&header),sizeof(header));	//if the header is complete, swap bytes and return it
+	*result = &header;
+	bytes_received = 0;
+	return 1;
+}
+
+	//Receive command data. Return (without loosing data!) if number of received bytes is insufficient.
+	//Expected data length is given in words!
+unsigned char control_get_data(unsigned short expected_length, unsigned short** data)
+{
+	static unsigned short packet_data[CONTROL_MAX_DATA_LENGTH];
+	static unsigned int bytes_received = 0;
+
+	bytes_received += ethernet_read(0, 2*expected_length - bytes_received, (unsigned char*)(&packet_data) + bytes_received);
+
+		if (bytes_received < (2*expected_length))
+			return 0;
+
+		*data = packet_data;
+		bytes_received = 0;
+		return 1;
+}
+
+// ****************************
+
+void control_step()
+{
+	command_header* header;
+	unsigned short* data;
+	unsigned int loop_ctr = 0;
+
+
+	//get header - at this moment this is blocking!
+	while (!control_get_header(&header))
+	{
+		control_delay();
+
+		if (++loop_ctr > CONTROL_TIMEOUT)
+		{
+			return;
+		}
+	}
+
+		//check start marker
+	if (header->marker != 0x5555)
+		return;
+
+
+		//get packet data - at this moment this is blocking!
+	while (!control_get_data(header->length, &data))
+	{
+		control_delay();
+
+		if (++loop_ctr > CONTROL_TIMEOUT)
+		{
+			return;
+		}
+	}
+		//swap data bytes
+	swap_bytes((unsigned char*)(void*)data, header->length*2);
+
+	switch(header->command)
+	{
+	case COMMAND_PING:
+		printf("COMMAND_PING\n");
+		control_pong(header);
+		break;
+	case COMMAND_DEBUG_LED_OFF:
+		printf("COMMAND_DEBUG_LED_OFF\n");
+		led_clear(0);
+		control_pong(header);
+		break;
+	case COMMAND_DEBUG_LED_ON:
+		printf("COMMAND_DEBUG_LED_ON\n");
+		led_set(0);
+		control_pong(header);
+		break;
+
+	case COMMAND_LEDS_DISABLE:
+		printf("COMMAND_LEDS_DISABLE\n");
+		led4_blink_enable(0);
+		control_pong(header);
+		break;
+	case COMMAND_LEDS_ENABLE:
+		printf("COMMAND_LEDS_ENABLE\n");
+		led4_blink_enable(1);
+		control_pong(header);
+		break;
+
+	case COMMAND_TRIGGER_DISABLE:
+		printf("COMMAND_TRIGGER_DISABLE\n");
+		master_clock_enable(0);
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_ENABLE:
+		printf("COMMAND_TRIGGER_ENABLE\n");
+		master_clock_enable(1);
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_SLAVE:
+		printf("COMMAND_TRIGGER_SET_SLAVE\n");
+		masterslave(TRIGGER_SLAVE);
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_MASTER:
+		printf("COMMAND_TRIGGER_SET_MASTER\n");
+		masterslave(TRIGGER_MASTER);
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_PERIOD:
+		printf("COMMAND_TRIGGER_SET_PERIOD: %d\n", data[0]);
+		master_clock_period((alt_u32)data[0]);	//we set only 16 lsbs!
+		header->length = 0;
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_TINT:
+		printf("COMMAND_TRIGGER_SET_TINT: %d\n", data[0]);
+		sensor_set_shutter(SENSOR_INTERFACE_BASE, data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+	case COMMAND_SET_GAIN:
+		printf("COMMAND_SET_GAIN: %d\n", data[0]);
+		sensor_set_gain(SENSOR_INTERFACE_BASE, data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_MASTER_DELAY:
+		printf("COMMAND_TRIGGER_SET_MASTER_DELAY: %d\n", data[0]);
+		set_delay(TRIGGER_MASTER, data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+	case COMMAND_TRIGGER_SET_SLAVE_DELAY:
+		printf("COMMAND_TRIGGER_SET_SLAVE_DELAY: %d\n", data[0]);
+		set_delay(TRIGGER_SLAVE, data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+
+	case COMMAND_DAQ_DISABLE:
+		printf("COMMAND_DAQ_DISABLE\n");
+		sensor_set_enable(SENSOR_INTERFACE_BASE, 0);
+		udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,0);
+		control_pong(header);
+		break;
+	case COMMAND_DAQ_ENABLE:
+		printf("COMMAND_DAQ_ENABLE\n");
+		udpgen_command_bit(UDP_GENERATOR_BASE, UDPGEN_CSR_EN_BITMASK,1);
+		sensor_set_enable(SENSOR_INTERFACE_BASE, 1);
+		control_pong(header);
+		break;
+	case COMMAND_DAQ_RESET_COUNTERS:
+		printf("COMMAND_DAQ_RESET_COUNTERS\n");
+		sensor_reset(SENSOR_INTERFACE_BASE);
+		control_pong(header);
+		break;
+	case COMMAND_DAQ_FLUSH_DATA:
+		printf("COMMAND_DAQ_FLUSH_DATA\n");
+			//nothing
+		control_pong(header);
+		break;
+	case COMMAND_DAQ_CONFIG_PEER:
+		printf("COMMAND_DAQ_CONFIG_PEER\n");
+		control_process_config_peer(data);
+		break;
+
+	case COMMAND_SLOWCTRL_SNAPSHOT:
+		printf("COMMAND_SLOWCTRL_SNAPSHOT\n");
+		control_process_snapshot();
+		break;
+
+	case COMMAND_SET_CLUSTER_THRESHOLD:
+		printf("COMMAND_SET_CLUSTER_THRESHOLD: %d\n", data[0]);
+		sensor_set_cluster_threshold(SENSOR_INTERFACE_BASE,data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+
+	case COMMAND_SET_CLUSTER_SIZE:
+		printf("COMMAND_SET_CLUSTER_SIZE: %d\n", data[0]);
+		sensor_set_cluster_size(SENSOR_INTERFACE_BASE,data[0]);
+		header->length = 0;
+		control_pong(header);
+		break;
+
+	case COMMAND_SET_CALIBRATION_FACTOR: //data[i] is 16 bit unsigned short; calibration factor is 16 bit
+		if (header->length>=2){
+		calibration_ram_set_factor(CALIBRATION_RAM_BASE,data[0],data[1]); //i is channelID
+		printf("COMMAND_SET_CALIBRATION_FACTOR ChannelIP%d : %d\n", data[0],data[1]);
+		}else{
+			printf("COMMAND_SET_CALIBRATION_FACTOR length: %d\n", header->length);
+		}
+		header->length = 0;
+		control_pong(header);
+		break;
+
+
+	default:
+		break;
+	}
+
+}
+
+// ******************** The task *****************
+
+TK_OBJECT(to_controltask);
+TK_ENTRY(ControlTask);
+
+struct inet_taskinfo controltask =
+{
+      &to_controltask,
+      "Control thread",
+      ControlTask,
+	  CONTROL_TASK_PRIORITY,
+      CONTROL_STACK_SIZE,
+};
+
+
+void ControlTask(void* param)
+{
+	printf ("::: Control task started ::: \n");
+	ethernet_listen(0, CONTROL_PORT);
+
+	sensor_preconfigure(SENSOR_INTERFACE_BASE);
+
+	//initial calibration factor here
+	printf("Initiate Calibration Factor 1 to 320 from channel1 to channel320 \n");
+
+
+	for (alt_u32 i = 0; i < 320; i++) {
+		//pow(2,13)=8192. represent calibration factor 1; range[0.00012,8)
+		//default calibration factor is 1.
+		calibration_ram_set_factor(CALIBRATION_RAM_BASE,i,8192); //i is channelID
+	 }
+
+	while(1)
+		control_step();
+}
+
+void control_init()
+{
+	TK_NEWTASK(&controltask);
+}
diff --git a/FPGA_nios/hit_pat/src/main.c b/FPGA_nios/hit_pat/src/main.c
new file mode 100644
index 0000000..e41efc4
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/main.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved. All use of this software and documentation is          *
+* subject to the License Agreement located at the end of this file below.     *
+*******************************************************************************                                                                             *
+* Date - October 24, 2006                                                     *
+* Module - iniche_init.c                                                      *
+*                                                                             *                                                                             *
+******************************************************************************/
+
+/******************************************************************************
+ * NicheStack TCP/IP stack initialization and Operating System Start in main()
+ * for Simple Socket Server (SSS) example. 
+ * 
+ * This example demonstrates the use of MicroC/OS-II running on NIOS II.       
+ * In addition it is to serve as a good starting point for designs using       
+ * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition.                                                                                           
+ *      
+ * Please refer to the Altera NicheStack Tutorial documentation for details on 
+ * this software example, as well as details on how to configure the NicheStack
+ * TCP/IP networking stack and MicroC/OS-II Real-Time Operating System.  
+ */
+  
+
+#include <stdio.h>
+
+/* MicroC/OS-II definitions */
+#include "includes.h"
+
+/* Simple Socket Server definitions */
+#include "socket_server.h"
+#include "control.h"
+//#include "alt_error_handler.h"
+
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "libport.h"
+#include "osport.h"
+
+#define SS_INITIAL_TASK_PRIORITY    5
+/* Definition of task stack for the initial task which will initialize the NicheStack
+ * TCP/IP Stack and then initialize the rest of the Simple Socket Server example tasks. 
+ */
+OS_STK    InitialTaskStk[APP_STACK_SIZE];
+
+/* InitialTask will initialize the NicheStack
+ * TCP/IP Stack and then initialize the rest of the Simple Socket Server example 
+ * RTOS structures and tasks. 
+ */
+void InitialTask(void *task_data)
+{
+  INT8U error_code;
+  
+  /*
+   * Initialize Altera NicheStack TCP/IP Stack - Nios II Edition specific code.
+   * NicheStack is initialized from a task, so that RTOS will have started, and 
+   * I/O drivers are available.  Two tasks are created:
+   *    "Inet main"  task with priority 2
+   *    "clock tick" task with priority 3
+   */   
+
+  alt_iniche_init();
+  netmain(); 
+
+  /* Wait for the network stack to be ready before proceeding. 
+   * iniche_net_ready indicates that TCP/IP stack is ready, and IP address is obtained.
+   */
+  while (!iniche_net_ready){
+    TK_SLEEP(1);
+  }
+
+  /* Now that the stack is running, perform the application initialization steps */
+  
+  /* Application Specific Task Launching Code Block Begin */
+
+  printf("\nSocket Server starting up\n");
+
+  /* Create tasks */
+  ethernet_init();
+  control_init();
+  //TK_NEWTASK(&ssconntask);
+  
+  /* Application Specific Task Launching Code Block End */
+  
+  /*This task is deleted because there is no need for it to run again */
+  error_code = OSTaskDel(OS_PRIO_SELF);
+  //alt_uCOSIIErrorHandler(error_code, 0);
+  
+  while (1); /* Correct Program Flow should never get here */
+}
+
+/* Main creates a single task, SSSInitialTask, and starts task scheduler.
+ */
+
+int main (int argc, char* argv[], char* envp[])
+{
+  
+  INT8U error_code;
+
+  /* Clear the RTOS timer */
+  OSTimeSet(0);
+
+  /* SSSInitialTask will initialize the NicheStack
+   * TCP/IP Stack and then initialize the rest of the Simple Socket Server example
+   * RTOS structures and tasks.
+   */
+  error_code = OSTaskCreateExt(InitialTask,
+                             NULL,
+                             (void *)&InitialTaskStk[APP_STACK_SIZE],
+                             SS_INITIAL_TASK_PRIORITY,
+                             SS_INITIAL_TASK_PRIORITY,
+                             InitialTaskStk,
+							 APP_STACK_SIZE,
+                             NULL,
+                             0);
+  //alt_uCOSIIErrorHandler(error_code, 0);
+
+  /*
+   * As with all MicroC/OS-II designs, once the initial thread(s) and
+   * associated RTOS resources are declared, we start the RTOS. That's it!
+   */
+  OSStart();
+
+
+  
+  while(1); /* Correct Program Flow never gets here. */
+
+  return -1;
+}
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
diff --git a/FPGA_nios/hit_pat/src/network_utilities.c b/FPGA_nios/hit_pat/src/network_utilities.c
new file mode 100644
index 0000000..1b54881
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/network_utilities.c
@@ -0,0 +1,456 @@
+/******************************************************************************
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved. All use of this software and documentation is          *
+* subject to the License Agreement located at the end of this file below.     *
+******************************************************************************
+* Date - October 24, 2006                                                     *
+* Module - network_utilities.c                                                *
+*                                                                             *
+******************************************************************************/
+
+#include <alt_types.h>
+#include <ctype.h>
+#include <errno.h>
+#include <stdio.h>
+#include <sys/alt_flash.h>
+#include "includes.h"
+#include "io.h"
+#include <alt_iniche_dev.h>
+
+#include "ipport.h"
+#include "tcpport.h"
+#include "network_utilities.h"
+
+#include <altera_avalon_pio_regs.h>
+#include <socket_server.h>
+
+#define IP4_ADDR(ipaddr, a,b,c,d) ipaddr = \
+    htonl((((alt_u32)(a & 0xff) << 24) | ((alt_u32)(b & 0xff) << 16) | \
+          ((alt_u32)(c & 0xff) << 8) | (alt_u32)(d & 0xff)))
+
+error_t generate_mac_addr(unsigned char mac_addr[6]);
+
+/*
+* get_mac_addr
+*
+* Read the MAC address in a board specific way. Prompt user to enter serial 
+* number to generate MAC address if failed to read from flash.
+*
+*/
+int get_mac_addr(NET net, unsigned char mac_addr[6])
+{
+    error_t error = 0;
+    
+    error = get_board_mac_addr(mac_addr);
+    
+    if(error)
+    {
+        /* Failed read MAC address from flash, prompt user to enter serial 
+           number to generate MAC address. */
+        error = generate_mac_addr(mac_addr);
+    }
+    return error;
+}
+
+/*
+ * get_ip_addr()
+ *
+ * This routine is called by InterNiche to obtain an IP address for the
+ * specified network adapter. Like the MAC address, obtaining an IP address is
+ * very system-dependant and therefore this function is exported for the
+ * developer to control.
+ *
+ * In our system, we are either attempting DHCP auto-negotiation of IP address,
+ * or we are setting our own static IP, Gateway, and Subnet Mask addresses our
+ * self. This routine is where that happens.
+ */
+int get_ip_addr(alt_iniche_dev *p_dev,
+                ip_addr* ipaddr,
+                ip_addr* netmask,
+                ip_addr* gw,
+                int* use_dhcp)
+{
+
+	alt_u32 sw_state = ~(IORD_ALTERA_AVALON_PIO_DATA(BUTTON_PIO_BASE));
+
+    printf("Input state: 0x%08lx\n", sw_state);
+
+    /*if (sw_state & 0x100)
+    {
+        	*use_dhcp = 1;
+    		IP4_ADDR(*ipaddr, 0, 0, 0, 0);
+    		IP4_ADDR(*gw, 0, 0, 0, 0);
+    		IP4_ADDR(*netmask, 0, 0, 0, 0);
+    		printf("DHCP enabled.\n");
+    }
+    else
+    {*/
+    	*use_dhcp = 0;
+        IP4_ADDR(*ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3+((sw_state>>4)&0x0F));
+        IP4_ADDR(*gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3);
+        IP4_ADDR(*netmask, MSKADDR0, MSKADDR1, MSKADDR2, MSKADDR3);
+        printf("DHCP disabled.\n");
+        printf("Static IP Address is %d.%d.%d.%d\n",
+            ip4_addr1(*ipaddr),
+            ip4_addr2(*ipaddr),
+            ip4_addr3(*ipaddr),
+            ip4_addr4(*ipaddr));
+    //}
+
+
+    /* Non-standard API: return 1 for success */
+    return 1;
+}
+
+int FindLastFlashSectorOffset(
+    alt_u32                     *pLastFlashSectorOffset);
+
+alt_u32 last_flash_sector_offset;
+alt_u32 last_flash_sector;
+
+/*
+* get_serial_number
+*
+* Prompt user to enter 9-digit serial number. 
+*
+*/
+alt_u32 get_serial_number (void)
+{
+    alt_u32 ser_num = 0;
+    char serial_number[9];
+    int i = 0;
+    
+    while(!ser_num)
+    {
+        printf("Please enter your 9-digit serial number. This is printed on a \n");
+        printf("label under your Nios dev. board. The first 3 digits of the \n");
+        printf("label are ASJ and the serial number follows this.\n -->");
+        
+        for(i=0; i<9; i++)
+        {
+            serial_number[i] = getchar();
+            putchar(serial_number[i]);
+            
+            /* Handle backspaces.  How civilized. */
+            if ((serial_number[i] == 0x08) && (i >= 0)) 
+            {
+                i--;
+            }
+        }
+        printf("\n");
+                
+        for(i=0; i<9; i++)
+        {
+            if (isdigit(serial_number[i]))
+            {
+                ser_num *= 10;
+                ser_num += serial_number[i] - '0';
+            }
+            else
+            {
+                ser_num = 0;
+                printf("Serial number only contains decimal digits and is non-zero\n");
+                break;
+            }
+        }
+    }
+    
+    return ser_num;
+}
+
+/*
+ * generate_and_store_mac_addr()
+ * 
+ * This routine is called when, upon program initialization, we discover
+ * that there is no valid network settings (including MAC address) programmed
+ * into flash memory at the last flash sector.  If it is not safe to use the 
+ * contents of this last sector of flash, the user is prompted to
+ * enter the serial number at the console.  A MAC address is then
+ * generated using 0xFF followed by the last 2 bytes of the serial number 
+ * appended to Altera's Vendor ID, an assigned MAC address range with the first
+ * 3 bytes of 00:07:ED.  For example, if the Nios Development Board serial 
+ * number is 040800017, the corresponding ethernet number generated will be
+ * 00:07:ED:FF:8F:11.
+ * 
+ * It should be noted that this number, while unique, will likely differ from
+ * the also unique (but now lost forever) MAC address programmed into the 
+ * development board on the production line.
+ * 
+ * As we are erasing the entire flash sector, we'll re-program it with not
+ * only the MAC address, but static IP, subnet, gateway, and "Use DHCP" 
+ * sections. These fail-safe static settings are compatible with previous
+ * Nios Ethernet designs, and allow the "factory-safe" design to behave 
+ * as expected if the last flash sector is erased.
+ */
+error_t generate_and_store_mac_addr()
+{
+    error_t error = -1;
+    alt_u32 ser_num = 0;
+    char flash_content[32];
+    alt_flash_fd* flash_handle;
+    
+    printf("Can't read the MAC address from your board (this probably means\n");
+    printf("that your flash was erased). We will assign you a MAC address and\n");
+    printf("static network settings\n\n");
+    
+    ser_num = get_serial_number();
+  
+    if (ser_num)
+    {
+        /* This says the image is safe */
+        flash_content[0] = 0xfe;
+        flash_content[1] = 0x5a;
+        flash_content[2] = 0x0;
+        flash_content[3] = 0x0;
+        
+        /* This is the Altera Vendor ID */
+        flash_content[4] = 0x0;
+        flash_content[5] = 0x7;
+        flash_content[6] = 0xed;
+        
+        /* Reserverd Board identifier for erase boards */
+        flash_content[7] = 0xFF;
+        flash_content[8] = (ser_num & 0xff00) >> 8;
+        flash_content[9] = ser_num & 0xff;
+        
+        /* Then comes a 16-bit "flags" field */
+        flash_content[10] = 0xFF;
+        flash_content[11] = 0xFF;
+        
+        /* Then comes the static IP address */
+        flash_content[12] = IPADDR0;
+        flash_content[13] = IPADDR1;
+        flash_content[14] = IPADDR2;
+        flash_content[15] = IPADDR3;
+        
+        /* Then comes the static nameserver address */
+        flash_content[16] = 0xFF;
+        flash_content[17] = 0xFF;
+        flash_content[18] = 0xFF;
+        flash_content[19] = 0xFF;
+        
+        /* Then comes the static subnet mask */
+        flash_content[20] = MSKADDR0;
+        flash_content[21] = MSKADDR1;
+        flash_content[22] = MSKADDR2;
+        flash_content[23] = MSKADDR3;
+        
+        /* Then comes the static gateway address */
+        flash_content[24] = GWADDR0;
+        flash_content[25] = GWADDR1;
+        flash_content[26] = GWADDR2;
+        flash_content[27] = GWADDR3;
+        
+        /* And finally whether to use DHCP - set all bits to be safe */
+        flash_content[28] = 0xFF;
+        flash_content[29] = 0xFF;
+        flash_content[30] = 0xFF;
+        flash_content[31] = 0xFF;
+        
+        /* Write the MAC address to flash */
+        flash_handle = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME);
+        if (flash_handle)
+        {
+            alt_write_flash(flash_handle,
+                            last_flash_sector_offset,
+                            flash_content,
+                            32);
+            alt_flash_close_dev(flash_handle);
+            error = 0;
+        }
+    }
+
+    return error;    
+}
+
+/*
+ * generate_mac_addr()
+ * 
+ * This routine is called when failed to read MAC address from flash (i.e: no 
+ * flash on the board). The user is prompted to enter the serial number at the 
+ * console. A MAC address is then generated using 0xFF followed by the last 2 
+ * bytes of the serial number appended to Altera's Vendor ID, an assigned MAC 
+ * address range with the first 3 bytes of 00:07:ED.  For example, if the Nios 
+ * Development Board serial number is 040800017, the corresponding ethernet 
+ * number generated will be 00:07:ED:FF:8F:11.
+ * 
+ */
+error_t generate_mac_addr(unsigned char mac_addr[6])
+{
+    error_t error = -1;
+    alt_u32 ser_num = 0;
+    
+    printf("\nCan't read the MAC address from your board. We will assign you\n");
+    printf("a MAC address.\n\n");
+    
+    ser_num = get_serial_number();
+  
+    if (ser_num)
+    {
+        /* This is the Altera Vendor ID */
+        mac_addr[0] = 0x0;
+        mac_addr[1] = 0x7;
+        mac_addr[2] = 0xed;
+        
+        /* Reserverd Board identifier */
+        mac_addr[3] = 0xFF;
+        mac_addr[4] = (ser_num & 0xff00) >> 8;
+        mac_addr[5] = ser_num & 0xff;
+        
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+            mac_addr[0],
+            mac_addr[1],
+            mac_addr[2],
+            mac_addr[3],
+            mac_addr[4],
+            mac_addr[5]);
+        
+        error = 0;
+    }
+  
+    return error;    
+}
+
+/*
+* get_board_mac_addr
+*
+* Read the MAC address in a board specific way
+*
+*/
+error_t get_board_mac_addr(unsigned char mac_addr[6])
+{
+    error_t error = 0;
+    alt_u32 signature;
+    
+    /* Get the flash sector with the MAC address. */
+    error = FindLastFlashSectorOffset(&last_flash_sector_offset);
+    if (!error)
+        last_flash_sector = EXT_FLASH_AVL_MEM_BASE + last_flash_sector_offset;
+
+    /* This last_flash_sector region of flash is examined to see if 
+     * valid network settings are present, indicated by a signature of 0x00005afe at 
+     * the first address of the last flash sector.  This hex value is chosen as the 
+     * signature since it looks like the english word "SAFE", meaning that it is 
+     * safe to use these network address values.  
+    */
+    if (!error)
+    {
+        signature = IORD_32DIRECT(last_flash_sector, 0);
+        if (signature != 0x00005afe)
+        {
+          error = generate_and_store_mac_addr();
+        }
+    }
+  
+    if (!error)
+    {
+        mac_addr[0] = IORD_8DIRECT(last_flash_sector, 4);
+        mac_addr[1] = IORD_8DIRECT(last_flash_sector, 5);
+        mac_addr[2] = IORD_8DIRECT(last_flash_sector, 6);
+        mac_addr[3] = IORD_8DIRECT(last_flash_sector, 7);
+        mac_addr[4] = IORD_8DIRECT(last_flash_sector, 8);
+        mac_addr[5] = IORD_8DIRECT(last_flash_sector, 9);
+    
+        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 
+            mac_addr[0],
+            mac_addr[1],
+            mac_addr[2],
+            mac_addr[3],
+            mac_addr[4],
+            mac_addr[5]);
+    
+    }
+    
+    return error;
+}
+
+/*******************************************************************************
+ *
+ * Flash service functions.
+ *
+ ******************************************************************************/
+
+#include "sys/alt_flash.h"
+#include "sys/alt_flash_dev.h"
+
+/*
+ * FindLastFlashSectorOffset
+ *
+ *   <-- pLastFlashSectorOffset Offset of last sector in flash.
+ *
+ *   This function finds the offset to the last sector in flash and returns it
+ * in pLastFlashSectorOffset.
+ */
+
+int FindLastFlashSectorOffset(
+    alt_u32                     *pLastFlashSectorOffset)
+{
+    alt_flash_fd                *fd;
+    flash_region                *regions;
+    int                         numRegions;
+    flash_region                *pLastRegion;
+    int                         lastFlashSectorOffset;
+    int                         n;
+    int                         error = 0;
+
+    /* Open the flash device. */
+    fd = alt_flash_open_dev(EXT_FLASH_AVL_MEM_NAME);
+    if (fd <= 0)
+        error = -1;
+
+    /* Get the flash info. */
+    if (!error)
+        error = alt_get_flash_info(fd, &regions, &numRegions);
+
+    /* Find the last flash sector. */
+    if (!error)
+    {
+        pLastRegion = &(regions[0]);
+        for (n = 1; n < numRegions; n++)
+        {
+            if (regions[n].offset > pLastRegion->offset)
+                pLastRegion = &(regions[n]);
+        }
+        lastFlashSectorOffset =   pLastRegion->offset
+                                + pLastRegion->region_size
+                                - pLastRegion->block_size;
+    }
+
+    /* Return results. */
+    if (!error)
+        *pLastFlashSectorOffset = lastFlashSectorOffset;
+
+    return (error);
+}
+
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
diff --git a/FPGA_nios/hit_pat/src/sensor.c b/FPGA_nios/hit_pat/src/sensor.c
new file mode 100644
index 0000000..ca468d8
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/sensor.c
@@ -0,0 +1,53 @@
+/*
+ * sensor.c
+ *
+ *  Created on: Aug 19, 2019
+ *      Author: mdziewiecki
+ */
+
+#include <stdio.h>
+#include "includes.h"
+#include <system.h>
+#include <io.h>
+#include <altera_msgdma.h>
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "libport.h"
+#include "osport.h"
+
+#include "utils.h"
+#include "dev_commands.h"
+#include "sensor.h"
+
+
+void sensor_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state)
+{
+	alt_u8 tmp = IORD_8DIRECT(base, SENSOR_REG_COMMAND);
+	if (state)
+		tmp |= bitmask;
+	else
+		tmp &= ~bitmask;
+	IOWR_8DIRECT(base, SENSOR_REG_COMMAND, tmp);
+}
+
+
+void sensor_preconfigure(alt_u32 base)
+{
+	printf(" *** Preconfiguring sensor module... \n");
+
+	sensor_command(base, 0);				//disable
+	sensor_set_sensorclk(base, 6);			//sensor clock - 3.57 MHz
+	sensor_set_adccnv(base, 31);			//conversion delay - default
+	sensor_set_delay(base, 1);				//trigger delay - default
+	sensor_set_shutter(base, 100);			//integration time - dummy default
+	sensor_set_serspeed(base, 50);			//synchro serial port - 1 Mbps
+	sensor_set_header_anydata(base, 0x00);	//should be 0
+	sensor_set_header_cmd(base, COMMAND_DATA_TRANSFER);	//command header, must be this one
+	sensor_command(base, 1);			//enable, gain low, SCLK full
+
+	sensor_set_cluster_threshold(base, 10); //default cluster threshold 10
+	sensor_set_cluster_size(base, 4);		//default cluster size  4
+	sensor_set_in_algo_threshold(base, 4);  //default algo threshold  4
+
+}
diff --git a/FPGA_nios/hit_pat/src/socket_server.c b/FPGA_nios/hit_pat/src/socket_server.c
new file mode 100644
index 0000000..ba4f205
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/socket_server.c
@@ -0,0 +1,332 @@
+/******************************************************************************
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved. All use of this software and documentation is          *
+* subject to the License Agreement located at the end of this file below.     *
+*******************************************************************************
+* Date - October 24, 2006                                                     *
+* Module - simple_socket_server.c                                             *
+*                                                                             *
+******************************************************************************/
+ 
+/******************************************************************************
+ * Simple Socket Server (SSS) example. 
+ * 
+ * This example demonstrates the use of MicroC/OS-II running on NIOS II.       
+ * In addition it is to serve as a good starting point for designs using       
+ * MicroC/OS-II and Altera NicheStack TCP/IP Stack - NIOS II Edition.                                          
+ *                                                                             
+ * -Known Issues                                                             
+ *     None.   
+ *      
+ * Please refer to the Altera NicheStack Tutorial documentation for details on this 
+ * software example, as well as details on how to configure the NicheStack TCP/IP 
+ * networking stack and MicroC/OS-II Real-Time Operating System.  
+ */
+ 
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h> 
+
+/* MicroC/OS-II definitions */
+#include "includes.h"
+
+/* Simple Socket Server definitions */
+#include "socket_server.h"
+//#include "alt_error_handler.h"
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "tcpport.h"
+#include "libport.h"
+#include "osport.h"
+
+
+static OS_EVENT *mutex;
+
+static SSConn connections[NR_CHANNELS];
+
+TK_OBJECT(to_sslistenertask);
+TK_ENTRY(SSListenerTask);
+
+struct inet_taskinfo sslistenertask =
+{
+      &to_sslistenertask,
+      "socket server listener",
+      SSListenerTask,
+	  SS_LISTENER_TASK_PRIORITY,
+	  SS_LISTENER_STACK_SIZE,
+};
+
+// ********************************************************
+
+
+
+void ss_reset_connection(SSConn* conn)	//called e.g. after closing a socket
+{
+  conn->fd_conn = -1;
+  conn->state = LISTENING;
+  return;
+}
+
+void ss_initialize_connection(SSConn* conn)	//called only at initialization
+{
+  conn->fd_conn = -1;
+  conn->fd_listen = -1;
+  conn->listenport = -1;
+  conn->state = FREE;
+  return;
+}
+
+void ss_handle_accept(SSConn* conn)
+{
+	int                 socket;
+	int					len;
+	struct sockaddr_in  incoming_addr;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+
+	len = sizeof(incoming_addr);
+
+	  //Close old connection if needed
+	if ((conn)->fd_conn != -1)
+	{
+		printf("[ss_handle_accept] closing old connection\n");
+		close(conn->fd_conn);
+		ss_reset_connection(conn);
+	}
+
+	if((socket=accept(conn->fd_listen,(struct sockaddr*)&incoming_addr,&len))<0)
+	{
+		//alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,
+		//					 "[ss_handle_accept] accept failed");
+	}
+	else
+	{
+		(conn)->fd_conn = socket;
+		(conn)->state = CONNECTED;
+		printf("[ss_handle_accept] accepted connection request from %s\n",
+		   inet_ntoa(incoming_addr.sin_addr));
+	}
+  
+	OSMutexPost(mutex);
+	return;
+}
+
+/*
+ * Listener Task()
+ */
+void SSListenerTask(void* param)
+{
+
+  int max_socket = 0;
+  BSD_TIMEVAL_T timeout;
+
+  INT8U err;
+  OSMutexPend(mutex, 0, &err);	//wrap initialization in a mutex - just in case...
+
+  timeout.tv_sec = 0;
+  timeout.tv_usec = 100000;
+
+  fd_set readfds;	//set of descriptors
+  
+  for (int ch = 0; ch < NR_CHANNELS; ch++)
+	  if ((connections[ch].fd_listen = socket(AF_INET, SOCK_STREAM, 0)) < 0)
+	  {
+		  //printf("Errot initializing socket #%d!\n", ch);
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Socket creation failed");
+	  }
+
+  	  //Binding etc. is done by ethernet_listen()
+
+  OSMutexPost(mutex);
+
+  	  //Now run in loop to handle incoming requests on all listening ports
+  while(1)
+  {
+		FD_ZERO(&readfds);
+
+		for (int ch = 0; ch < NR_CHANNELS; ch++)
+			if (connections[ch].listenport >= 0)
+			{
+				FD_SET(connections[ch].fd_listen, &readfds);
+				if (connections[ch].fd_listen >= max_socket)
+					max_socket = connections[ch].fd_listen+1;
+			}
+
+		if (max_socket == 0)
+			TK_SLEEP(10);	//just sleep a bit if nothing to do
+		else
+		{
+			select(max_socket, &readfds, NULL, NULL, &timeout);	//we must timeout from time to time to find newly set-up channels
+
+			for (int ch = 0; ch < NR_CHANNELS; ch++)
+				if (FD_ISSET(connections[ch].fd_listen, &readfds))
+					ss_handle_accept(&(connections[ch]));
+		}
+  } /* while(1) */
+
+  //never come here
+}
+
+
+// ****************** User interface ********************
+
+int ethernet_init()
+{
+	  INT8U err;
+	  mutex = OSMutexCreate(SS_LISTENER_TASK_PRIORITY-1, &err);
+
+
+	  for (int ch = 0; ch < NR_CHANNELS; ch++)
+		  ss_initialize_connection(&(connections[ch]));
+
+	  TK_NEWTASK(&sslistenertask);
+	  return 0;
+}
+
+int ethernet_listen(int channel, int port)
+{
+	  struct sockaddr_in addr;
+
+		INT8U err;
+		OSMutexPend(mutex, 0, &err);
+
+	  addr.sin_family = AF_INET;
+	  addr.sin_port = htons(port);
+	  addr.sin_addr.s_addr = INADDR_ANY;
+
+	  if (bind(connections[channel].fd_listen,(struct sockaddr *)&addr,sizeof(addr)) < 0)
+	  {
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Bind failed");
+		  OSMutexPost(mutex);
+		  return -1;
+	  }
+
+	  if (listen(connections[channel].fd_listen,1) < 0)
+	  {
+		  //alt_NetworkErrorHandler(EXPANDED_DIAGNOSIS_CODE,"[sss_task] Listen failed");
+		  OSMutexPost(mutex);
+		  return -2;
+	  }
+
+	  ss_reset_connection(&(connections[channel]));
+	  connections[channel].listenport = port;
+	  printf("[sss_task] Simple Socket Server listening on port %d\n", port);
+
+	  OSMutexPost(mutex);
+	  return 0;
+}
+
+int ethernet_write(int channel, int size, unsigned char* data)
+{
+	int result;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+
+	if (connections[channel].fd_conn == -1)	//socket is closed or channel unconfigured
+	{
+		OSMutexPost(mutex);
+	    return 0;
+	}
+
+	result = (int)send(connections[channel].fd_conn, data, size, 0);
+	if (result == -1)
+	{
+		printf("[ethernet_write] closing connection due to error\n");
+		close(connections[channel].fd_conn);			//close connection on error
+		ss_reset_connection(&(connections[channel]));
+		result = 0;
+	}
+
+	OSMutexPost(mutex);
+	return result;
+}
+
+int ethernet_read(int channel, int size, unsigned char* data)
+{
+	fd_set readfds;	//set of descriptors
+	int max_socket;
+	BSD_TIMEVAL_T timeout;
+	int result;
+
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+
+	if (connections[channel].fd_conn == -1)	//socket is closed or channel unconfigured
+	{
+		OSMutexPost(mutex);
+	    return 0;
+	}
+
+		//prepare call parameters
+    FD_ZERO(&readfds);
+    FD_SET(connections[channel].fd_conn, &readfds);
+    max_socket = connections[channel].fd_conn+1;
+    timeout.tv_sec = 0;
+    timeout.tv_usec = 0;
+
+    	//check for data
+    if (select(max_socket, &readfds, NULL, NULL, &timeout))
+    	if (FD_ISSET(connections[channel].fd_conn, &readfds))
+    	{
+    		result =  (int)recv(connections[channel].fd_conn, data, size, 0);
+    		if (result == -1)
+    		{
+    			printf("[ethernet_read] closing connection due to error\n");
+    			close(connections[channel].fd_conn);			//close connection on error
+    			ss_reset_connection(&(connections[channel]));
+    			result = 0;
+    		}
+    		OSMutexPost(mutex);
+    		return result;
+    	}
+
+	OSMutexPost(mutex);
+    return 0;
+}
+
+int ethernet_close(int channel)
+{
+	INT8U err;
+	OSMutexPend(mutex, 0, &err);
+
+	close(connections[channel].fd_conn);
+	ss_reset_connection(&(connections[channel]));
+
+	OSMutexPost(mutex);
+	return 0;
+}
+
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
diff --git a/FPGA_nios/hit_pat/src/tse_my_system.c b/FPGA_nios/hit_pat/src/tse_my_system.c
new file mode 100644
index 0000000..a6cbb18
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/tse_my_system.c
@@ -0,0 +1,12 @@
+#ifdef ALT_INICHE
+    #include "ipport.h"
+#endif
+
+#include "system.h"
+#include "altera_avalon_tse.h"
+#include "altera_avalon_tse_system_info.h"
+
+alt_tse_system_info tse_mac_device[MAXNETS] = {
+		TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETH_TSE, 0, MSGDMA_TX, MSGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY)
+		
+};
diff --git a/FPGA_nios/hit_pat/src/udpgen.c b/FPGA_nios/hit_pat/src/udpgen.c
new file mode 100644
index 0000000..0f2bf44
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/udpgen.c
@@ -0,0 +1,51 @@
+/*
+ * udpgen.c
+ *
+ *  Created on: Aug 7, 2019
+ *      Author: mdziewiecki
+ */
+
+#include <stdio.h>
+#include "includes.h"
+#include <system.h>
+#include <io.h>
+#include <altera_msgdma.h>
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "libport.h"
+#include "osport.h"
+
+#include "utils.h"
+
+#include "udpgen.h"
+
+//*******************************************************************
+
+
+void udpgen_command_bit(alt_u32 base, alt_u8 bitmask, alt_u8 state)
+{
+	alt_u8 tmp = IORD_8DIRECT(base, UDPGEN_REG_CSR);
+	if (state)
+		tmp |= bitmask;
+	else
+		tmp &= ~bitmask;
+	IOWR_8DIRECT(base, UDPGEN_REG_CSR, tmp);
+}
+
+void udpgen_test(alt_u32 base)
+{
+	printf (" *** Setting up UDP generator... \n");
+
+	unsigned char dstmac[] = {0x18, 0xd6, 0xc7, 0x05, 0xaa, 0x63};
+	unsigned char srcip[] = {10,0,7,17};
+	unsigned char dstip[] = {10,0,7,1};
+
+	udpgen_command(UDP_GENERATOR_BASE, 0x01);
+	udpgen_set_size(UDP_GENERATOR_BASE, 16);
+	udpgen_set_srcip_a(UDP_GENERATOR_BASE, srcip);
+	udpgen_set_dstip_a(UDP_GENERATOR_BASE, dstip);
+	udpgen_set_srcport(UDP_GENERATOR_BASE, 4096);
+	udpgen_set_dstport(UDP_GENERATOR_BASE, 4097);
+	udpgen_set_dstmac_a(UDP_GENERATOR_BASE, dstmac);
+}
diff --git a/FPGA_nios/hit_pat/src/utils.c b/FPGA_nios/hit_pat/src/utils.c
new file mode 100644
index 0000000..926a6cc
--- /dev/null
+++ b/FPGA_nios/hit_pat/src/utils.c
@@ -0,0 +1,131 @@
+/*
+ * utils.c
+ *
+ *  Created on: Jul 31, 2019
+ *      Author: mdziewiecki
+ */
+
+
+#include <stdio.h>
+#include "includes.h"
+#include <system.h>
+#include <io.h>
+
+/* Nichestack definitions */
+#include "ipport.h"
+#include "libport.h"
+#include "osport.h"
+
+#include "altera_avalon_pio_regs.h"
+#include "altera_avalon_timer_regs.h"
+#include "utils.h"
+
+#include "sensor.h"
+
+alt_u16 delays[2];
+alt_u8 mastermode;
+
+//******************************************************
+
+//Swap odd/even bytes in a bunch of data to align endianness of shorts
+void swap_bytes(unsigned char* array, int size_bytes)
+{
+	for (int i = 0; i < size_bytes; i+= 2)
+	{
+		unsigned char tmp = array[i];
+		array[i] = array[i+1];
+		array[i+1] = tmp;
+	}
+}
+//The same, but four-byte-wise
+void swap_quad(unsigned char* array, int size_bytes)
+{
+	unsigned char buf[4];
+
+	for (int i = 0; i < size_bytes; i+= 4)
+	{
+		memcpy(buf, array+i, 4);
+		for (int j = 0; j < 4; j++)
+			array[i+j] = buf[3-j];
+	}
+}
+
+	//trigger FPGA reload
+void reload_fpga()
+{
+	printf("$$$$ RECONFIGURING FPGA!!! $$$$\n");
+	//TK_SLEEP(100);	//let it print the message before dying
+	//IOWR(DUAL_BOOT_BASE, 0, 0x1);
+	printf("*** DISABLED! ***\n");
+}
+
+void masterslave(alt_u8 master)
+{
+	if (master)
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 0x80);
+	else
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 0x80);
+	mastermode = master;
+	set_delay(mastermode, delays[mastermode]);	//update sensor delay setting
+}
+
+void master_clock_period(alt_u32 period)
+{
+		//set period
+	IOWR_ALTERA_AVALON_TIMER_PERIODL(FRAME_TIMER_BASE, (alt_u16)(period & 0xFFFF));
+	IOWR_ALTERA_AVALON_TIMER_PERIODH(FRAME_TIMER_BASE, (alt_u16)((period>>16) & 0xFFFF));
+		//start timer in continuous mode
+	//IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,
+	//									ALTERA_AVALON_TIMER_CONTROL_CONT_MSK);
+}
+
+void master_clock_enable(alt_u8 en)
+{
+	alt_u16 tmp = 0;	// = IORD_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE);
+
+	if (en)
+		tmp |= ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK;
+	else
+		tmp |= ALTERA_AVALON_TIMER_CONTROL_STOP_MSK;
+
+	IOWR_ALTERA_AVALON_TIMER_CONTROL(FRAME_TIMER_BASE,tmp);
+}
+
+void led_set(alt_u8 led_nr)
+{
+	if (led_nr > 4)
+		return;
+	IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<led_nr);
+}
+
+void led_clear(alt_u8 led_nr)
+{
+	if (led_nr > 4)
+		return;
+	IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1<<led_nr);
+}
+
+void led_toggle(alt_u8 led_nr)
+{
+	if (led_nr > 4)
+		return;
+	alt_u32 tmp = IORD_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE);
+	tmp ^= (1<<led_nr);
+	IOWR_ALTERA_AVALON_PIO_DATA(OUTPUT_PIO_BASE, 1<<led_nr);
+}
+
+void led4_blink_enable(alt_u8 en)
+{
+	if (en)
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(OUTPUT_PIO_BASE, 1<<5);
+	else
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(OUTPUT_PIO_BASE, 1<<5);
+}
+
+void set_delay(alt_u8 master, alt_u16 value)
+{
+	delays[master] = value;
+	if (master == mastermode)
+		sensor_set_delay(SENSOR_INTERFACE_BASE, value);	//update sensor setting only if right mode
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/.project b/FPGA_nios/hit_pat_bsp/.project
new file mode 100644
index 0000000..097dbcb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/.project
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>hit_pat_bsp</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIBspNature</nature>
+	</natures>
+</projectDescription>
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h b/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h
new file mode 100644
index 0000000..8eb438f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/alt_types.h
@@ -0,0 +1,54 @@
+#ifndef __ALT_TYPES_H__
+#define __ALT_TYPES_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/* 
+ * Don't declare these typedefs if this file is included by assembly source.
+ */
+#ifndef ALT_ASM_SRC
+typedef signed char  alt_8;
+typedef unsigned char  alt_u8;
+typedef signed short alt_16;
+typedef unsigned short alt_u16;
+typedef signed long alt_32;
+typedef unsigned long alt_u32;
+typedef long long alt_64;
+typedef unsigned long long alt_u64;
+#endif
+
+#define ALT_INLINE        __inline__
+#define ALT_ALWAYS_INLINE __attribute__ ((always_inline))
+#define ALT_WEAK          __attribute__((weak))
+
+#endif /* __ALT_TYPES_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h
new file mode 100644
index 0000000..048e02f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/altera_nios2_gen2_irq.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * Support for the Nios II internal interrupt controller.
+ */
+
+#ifndef __ALT_NIOS2_GEN2_IRQ_H__
+#define __ALT_NIOS2_GEN2_IRQ_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The macro ALTERA_NIOS2_GEN2_IRQ_INSTANCE is used by the alt_irq_init()
+ * function in the auto-generated file alt_sys_init.c to create an
+ * instance of this interrupt controller device driver state if this
+ * module contains an interrupt controller.
+ * Only one instance of a Nios II is allowed so this macro is just empty.
+ */
+
+#define ALTERA_NIOS2_GEN2_IRQ_INSTANCE(name, state)
+
+/*
+ * altera_nios2_gen2_irq_init() is called by the auto-generated function 
+ * alt_irq_init() once for the Nios II if it contains an interrupt controller.
+ * The altera_nios2_gen2_irq_init() routine is called using the 
+ * ALTERA_NIOS2_GEN2_IRQ_INIT macro given below.
+ *
+ * This function initializes the internal interrupt controller
+ * so is not called if the Nios II contains an external interrupt
+ * controller port (because the internal interrupt controller
+ * is removed if this port is present).
+ */
+
+extern void altera_nios2_gen2_irq_init( void );
+
+/*
+ * The macro ALTERA_NIOS2_GEN2_IRQ_INIT is used by the alt_irq_init() routine
+ * in the auto-generated file alt_sys_init.c to initialize an instance
+ * of the interrupt controller device driver state.
+ */
+
+#define ALTERA_NIOS2_GEN2_IRQ_INIT(name, state) altera_nios2_gen2_irq_init()
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_NIOS2_ULTRA_IRQ_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h b/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h
new file mode 100644
index 0000000..ac95016
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/includes.h
@@ -0,0 +1,65 @@
+#ifndef __INCLUDES_H__
+#define __INCLUDES_H__
+
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*
+*                        (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL
+*                                           All Rights Reserved
+*
+*                                           MASTER INCLUDE FILE
+*********************************************************************************************************
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include    "os_cpu.h"
+#include    "os_cfg.h"
+#include    "ucos_ii.h"
+
+#ifdef      ONT_GLOBALS
+#define     ONT_EXT
+#else
+#define     ONT_EXT  extern
+#endif
+
+/*
+*********************************************************************************************************
+*                                             DATA TYPES
+*********************************************************************************************************
+*/
+
+typedef struct {
+    char    TaskName[30];
+    INT16U  TaskCtr;
+    INT16U  TaskExecTime;
+    INT32U  TaskTotExecTime;
+} TASK_USER_DATA;
+
+/*
+*********************************************************************************************************
+*                                              VARIABLES
+*********************************************************************************************************
+*/
+
+ONT_EXT  TASK_USER_DATA  TaskUserData[10];
+
+/*
+*********************************************************************************************************
+*                                         FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+void   DispTaskStat(INT8U id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCLUDES_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/io.h b/FPGA_nios/hit_pat_bsp/HAL/inc/io.h
new file mode 100644
index 0000000..05efdd0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/io.h
@@ -0,0 +1,81 @@
+#ifndef __IO_H__
+#define __IO_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/* IO Header file for Nios II Toolchain */
+
+#include "alt_types.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#ifndef SYSTEM_BUS_WIDTH
+#define SYSTEM_BUS_WIDTH 32
+#endif
+
+/* Dynamic bus access functions */
+
+#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \
+  ((void *)(((alt_u8*)BASE) + (OFFSET)))
+
+#define IORD_32DIRECT(BASE, OFFSET) \
+  __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))
+#define IORD_16DIRECT(BASE, OFFSET) \
+  __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))
+#define IORD_8DIRECT(BASE, OFFSET) \
+  __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))
+
+#define IOWR_32DIRECT(BASE, OFFSET, DATA) \
+  __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))
+#define IOWR_16DIRECT(BASE, OFFSET, DATA) \
+  __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))
+#define IOWR_8DIRECT(BASE, OFFSET, DATA) \
+  __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))
+
+/* Native bus access functions */
+
+#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \
+  ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8))))
+
+#define IORD(BASE, REGNUM) \
+  __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)))
+#define IOWR(BASE, REGNUM, DATA) \
+  __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IO_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h b/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h
new file mode 100644
index 0000000..7d4a550
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/nios2.h
@@ -0,0 +1,300 @@
+#ifndef __NIOS2_H__
+#define __NIOS2_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This header provides processor specific macros for accessing the Nios2
+ * control registers.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * Number of available IRQs in internal interrupt controller.
+ */
+#define NIOS2_NIRQ 32
+
+/*
+ * Macros for accessing select Nios II general-purpose registers.
+ */
+
+/* ET (Exception Temporary) register */ 
+#define NIOS2_READ_ET(et) \
+    do { __asm ("mov %0, et" : "=r" (et) ); } while (0)
+
+#define NIOS2_WRITE_ET(et) \
+    do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0)
+
+/* SP (Stack Pointer) register */ 
+#define NIOS2_READ_SP(sp) \
+    do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0)
+
+/*
+ * Macros for useful processor instructions.
+ */
+#define NIOS2_BREAK() \
+    do { __asm volatile ("break"); } while (0)
+
+#define NIOS2_REPORT_STACK_OVERFLOW() \
+    do { __asm volatile("break 3"); } while (0)
+
+/*
+ * Macros for accessing Nios II control registers.
+ */
+#define NIOS2_READ_STATUS(dest) \
+    do { dest = __builtin_rdctl(0); } while (0)
+
+#define NIOS2_WRITE_STATUS(src) \
+    do { __builtin_wrctl(0, src); } while (0)
+
+#define NIOS2_READ_ESTATUS(dest) \
+    do { dest = __builtin_rdctl(1); } while (0)
+
+#define NIOS2_READ_BSTATUS(dest) \
+    do { dest = __builtin_rdctl(2); } while (0)
+
+#define NIOS2_READ_IENABLE(dest) \
+    do { dest = __builtin_rdctl(3); } while (0)
+
+#define NIOS2_WRITE_IENABLE(src) \
+    do { __builtin_wrctl(3, src); } while (0)
+
+#define NIOS2_READ_IPENDING(dest) \
+    do { dest = __builtin_rdctl(4); } while (0)
+
+#define NIOS2_READ_CPUID(dest) \
+    do { dest = __builtin_rdctl(5); } while (0)
+
+#define NIOS2_READ_EXCEPTION(dest) \
+    do { dest = __builtin_rdctl(7); } while (0)
+
+#define NIOS2_READ_PTEADDR(dest) \
+    do { dest = __builtin_rdctl(8); } while (0)
+
+#define NIOS2_WRITE_PTEADDR(src) \
+    do { __builtin_wrctl(8, src); } while (0)
+
+#define NIOS2_READ_TLBACC(dest) \
+    do { dest = __builtin_rdctl(9); } while (0)
+
+#define NIOS2_WRITE_TLBACC(src) \
+    do { __builtin_wrctl(9, src); } while (0)
+
+#define NIOS2_READ_TLBMISC(dest) \
+    do { dest = __builtin_rdctl(10); } while (0)
+
+#define NIOS2_WRITE_TLBMISC(src) \
+    do { __builtin_wrctl(10, src); } while (0)
+
+#define NIOS2_READ_ECCINJ(dest) \
+    do { dest = __builtin_rdctl(11); } while (0)
+
+#define NIOS2_WRITE_ECCINJ(src) \
+    do { __builtin_wrctl(11, src); } while (0)
+
+#define NIOS2_READ_BADADDR(dest) \
+    do { dest = __builtin_rdctl(12); } while (0)
+
+#define NIOS2_WRITE_CONFIG(src) \
+    do { __builtin_wrctl(13, src); } while (0)
+
+#define NIOS2_READ_CONFIG(dest) \
+    do { dest = __builtin_rdctl(13); } while (0)
+
+#define NIOS2_WRITE_MPUBASE(src) \
+    do { __builtin_wrctl(14, src); } while (0)
+
+#define NIOS2_READ_MPUBASE(dest) \
+    do { dest = __builtin_rdctl(14); } while (0)
+
+#define NIOS2_WRITE_MPUACC(src) \
+    do { __builtin_wrctl(15, src); } while (0)
+
+#define NIOS2_READ_MPUACC(dest) \
+    do { dest = __builtin_rdctl(15); } while (0)
+
+/*
+ * Nios II control registers that are always present
+ */
+#define NIOS2_STATUS   status
+#define NIOS2_ESTATUS  estatus
+#define NIOS2_BSTATUS  bstatus
+#define NIOS2_IENABLE  ienable
+#define NIOS2_IPENDING ipending
+#define NIOS2_CPUID cpuid
+
+/*
+ * Bit masks & offsets for Nios II control registers.
+ * The presence and size of a field is sometimes dependent on the Nios II
+ * configuration.  Bit masks for every possible field and the maximum size of
+ * that field are defined.
+ *
+ * All bit-masks are expressed relative to the position
+ * of the data with a register. To read data that is LSB-
+ * aligned, the register read data should be masked, then
+ * right-shifted by the designated "OFST" macro value. The
+ * opposite should be used for register writes when starting
+ * with LSB-aligned data.
+ */
+
+/* STATUS, ESTATUS, BSTATUS, and SSTATUS registers */
+#define NIOS2_STATUS_PIE_MSK  (0x00000001)
+#define NIOS2_STATUS_PIE_OFST (0)
+#define NIOS2_STATUS_U_MSK    (0x00000002)
+#define NIOS2_STATUS_U_OFST   (1)
+#define NIOS2_STATUS_EH_MSK   (0x00000004)
+#define NIOS2_STATUS_EH_OFST  (2)
+#define NIOS2_STATUS_IH_MSK     (0x00000008)
+#define NIOS2_STATUS_IH_OFST    (3)
+#define NIOS2_STATUS_IL_MSK     (0x000003f0)
+#define NIOS2_STATUS_IL_OFST    (4)
+#define NIOS2_STATUS_CRS_MSK    (0x0000fc00)
+#define NIOS2_STATUS_CRS_OFST   (10)
+#define NIOS2_STATUS_PRS_MSK    (0x003f0000)
+#define NIOS2_STATUS_PRS_OFST   (16)
+#define NIOS2_STATUS_NMI_MSK    (0x00400000)
+#define NIOS2_STATUS_NMI_OFST   (22)
+#define NIOS2_STATUS_RSIE_MSK   (0x00800000)
+#define NIOS2_STATUS_RSIE_OFST  (23)
+#define NIOS2_STATUS_SRS_MSK    (0x80000000)
+#define NIOS2_STATUS_SRS_OFST   (31)
+
+/* EXCEPTION register */
+#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c)
+#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2)
+#define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000)
+#define NIOS2_EXCEPTION_REG_ECCFTL_OFST (31)
+
+/* PTEADDR (Page Table Entry Address) register */
+#define NIOS2_PTEADDR_REG_VPN_OFST 2
+#define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc
+#define NIOS2_PTEADDR_REG_PTBASE_OFST 22
+#define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000
+
+/* TLBACC (TLB Access) register */
+#define NIOS2_TLBACC_REG_PFN_OFST 0
+#define NIOS2_TLBACC_REG_PFN_MASK 0xfffff
+#define NIOS2_TLBACC_REG_G_OFST 20
+#define NIOS2_TLBACC_REG_G_MASK 0x100000
+#define NIOS2_TLBACC_REG_X_OFST 21
+#define NIOS2_TLBACC_REG_X_MASK 0x200000
+#define NIOS2_TLBACC_REG_W_OFST 22
+#define NIOS2_TLBACC_REG_W_MASK 0x400000
+#define NIOS2_TLBACC_REG_R_OFST 23
+#define NIOS2_TLBACC_REG_R_MASK 0x800000
+#define NIOS2_TLBACC_REG_C_OFST 24
+#define NIOS2_TLBACC_REG_C_MASK 0x1000000
+#define NIOS2_TLBACC_REG_IG_OFST 25
+#define NIOS2_TLBACC_REG_IG_MASK 0xfe000000
+
+/* TLBMISC (TLB Miscellaneous) register */
+#define NIOS2_TLBMISC_REG_D_OFST 0
+#define NIOS2_TLBMISC_REG_D_MASK 0x1
+#define NIOS2_TLBMISC_REG_PERM_OFST 1
+#define NIOS2_TLBMISC_REG_PERM_MASK 0x2
+#define NIOS2_TLBMISC_REG_BAD_OFST 2
+#define NIOS2_TLBMISC_REG_BAD_MASK 0x4
+#define NIOS2_TLBMISC_REG_DBL_OFST 3
+#define NIOS2_TLBMISC_REG_DBL_MASK 0x8
+#define NIOS2_TLBMISC_REG_PID_OFST 4
+#define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0
+#define NIOS2_TLBMISC_REG_WE_OFST 18
+#define NIOS2_TLBMISC_REG_WE_MASK 0x40000
+#define NIOS2_TLBMISC_REG_RD_OFST 19
+#define NIOS2_TLBMISC_REG_RD_MASK 0x80000
+#define NIOS2_TLBMISC_REG_WAY_OFST 20
+#define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000
+#define NIOS2_TLBMISC_REG_EE_OFST 24
+#define NIOS2_TLBMISC_REG_EE_MASK 0x1000000
+
+/* ECCINJ (ECC Inject) register */
+#define NIOS2_ECCINJ_REG_RF_OFST 0
+#define NIOS2_ECCINJ_REG_RF_MASK 0x3
+#define NIOS2_ECCINJ_REG_ICTAG_OFST 2
+#define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc
+#define NIOS2_ECCINJ_REG_ICDAT_OFST 4
+#define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30
+#define NIOS2_ECCINJ_REG_DCTAG_OFST 6
+#define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0
+#define NIOS2_ECCINJ_REG_DCDAT_OFST 8
+#define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300
+#define NIOS2_ECCINJ_REG_TLB_OFST 10
+#define NIOS2_ECCINJ_REG_TLB_MASK 0xc00
+#define NIOS2_ECCINJ_REG_DTCM0_OFST 12
+#define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000
+#define NIOS2_ECCINJ_REG_DTCM1_OFST 14
+#define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000
+#define NIOS2_ECCINJ_REG_DTCM2_OFST 16
+#define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000
+#define NIOS2_ECCINJ_REG_DTCM3_OFST 18
+#define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000
+
+/* CONFIG register */
+#define NIOS2_CONFIG_REG_PE_MASK (0x00000001)
+#define NIOS2_CONFIG_REG_PE_OFST (0)
+#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002)
+#define NIOS2_CONFIG_REG_ANI_OFST (1)
+#define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004)
+#define NIOS2_CONFIG_REG_ECCEN_OFST (2)
+#define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008)
+#define NIOS2_CONFIG_REG_ECCEXC_OFST (3)
+
+/* MPUBASE (MPU Base Address) Register */
+#define NIOS2_MPUBASE_D_MASK         (0x00000001)
+#define NIOS2_MPUBASE_D_OFST         (0)
+#define NIOS2_MPUBASE_INDEX_MASK     (0x0000003e)
+#define NIOS2_MPUBASE_INDEX_OFST     (1)
+#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0)
+#define NIOS2_MPUBASE_BASE_ADDR_OFST (6)
+
+/* MPUACC (MPU Access) Register */
+#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0)
+#define NIOS2_MPUACC_LIMIT_OFST (6)
+#define NIOS2_MPUACC_MASK_MASK  (0xffffffc0)
+#define NIOS2_MPUACC_MASK_OFST  (6)
+#define NIOS2_MPUACC_C_MASK     (0x00000020)
+#define NIOS2_MPUACC_C_OFST     (5)
+#define NIOS2_MPUACC_PERM_MASK  (0x0000001c)
+#define NIOS2_MPUACC_PERM_OFST  (2)
+#define NIOS2_MPUACC_RD_MASK    (0x00000002)
+#define NIOS2_MPUACC_RD_OFST    (1)
+#define NIOS2_MPUACC_WR_MASK    (0x00000001)
+#define NIOS2_MPUACC_WR_OFST    (0)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __NIOS2_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h b/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h
new file mode 100644
index 0000000..d7591fe
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/os_cpu.h
@@ -0,0 +1,145 @@
+#ifndef __OS_CPU_H__
+#define __OS_CPU_H__
+
+/*
+*********************************************************************************************************
+*                                               uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                         (c) Copyright 1992-1999, Jean J. Labrosse, Weston, FL
+*                                          All Rights Reserved
+*
+*                                       80x86/80x88 Specific code
+*                                          LARGE MEMORY MODEL
+*
+*                                          Borland C/C++ V4.51
+*
+* File         : OS_CPU.H
+* By           : IS (modified from version by Jean J. Labrosse)
+*********************************************************************************************************
+*/
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-5 Altera Corporation, San Jose, California, USA.         *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include "sys/alt_irq.h"
+
+#ifdef  OS_CPU_GLOBALS
+#define OS_CPU_EXT
+#else
+#define OS_CPU_EXT  extern
+#endif
+
+/*****************************************************************************************
+/                                      REVISION HISTORY
+/
+*****************************************************************************************/
+
+/*****************************************************************************************
+/                                              DATA TYPES
+/                                         (Compiler Specific)
+*****************************************************************************************/
+
+/* This is the definition for Nios32.  */
+typedef unsigned char  BOOLEAN;
+typedef unsigned char  INT8U;                    /* Unsigned  8 bit quantity                           */
+typedef signed   char  INT8S;                    /* Signed    8 bit quantity                           */
+typedef unsigned short INT16U;                   /* Unsigned 16 bit quantity                           */
+typedef signed   short INT16S;                   /* Signed   16 bit quantity                           */
+typedef unsigned long  INT32U;                   /* Unsigned 32 bit quantity                           */
+typedef signed   long  INT32S;                   /* Signed   32 bit quantity                           */
+typedef float          FP32;                     /* Single precision floating point                    */
+typedef double         FP64;                     /* Double precision floating point                    */
+typedef unsigned int   OS_STK;                   /* Each stack entry is 32-bits                        */
+
+/****************************************************************************
+*                           Nios2 Miscellaneous defines
+****************************************************************************/
+
+#define  OS_STK_GROWTH        1        /* Stack grows from HIGH to LOW memory */
+#define  OS_TASK_SW           OSCtxSw  
+
+/******************************************************************************************
+ *                Disable and Enable Interrupts - 2 methods
+ *
+ * Method #1:  Disable/Enable interrupts using simple instructions.  After critical 
+ *             section, interrupts will be enabled even if they were disabled before 
+ *             entering the critical section.
+ *
+ * Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In 
+ *             other words, if interrupts were disabled before entering the critical 
+ *             section, they will be disabled when leaving the critical section.  
+ *
+ * Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
+ *             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
+ *             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
+ *             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
+ *             into the CPU's status register.
+ *
+ *****************************************************************************************/
+
+#define  OS_CRITICAL_METHOD    3    
+
+#if      OS_CRITICAL_METHOD == 1
+#error OS_CRITICAL_METHOD == 1 not supported, please use method 3 instead.
+#endif
+
+#if      OS_CRITICAL_METHOD == 2
+#error OS_CRITICAL_METHOD == 2 not supported, please use method 3 instead.
+#endif
+
+#if      OS_CRITICAL_METHOD == 3
+#define  OS_CPU_SR alt_irq_context  
+#define  OS_ENTER_CRITICAL() \
+         cpu_sr = alt_irq_disable_all ()
+#define  OS_EXIT_CRITICAL() \
+         alt_irq_enable_all (cpu_sr);
+#endif
+
+/* Prototypes */
+void OSStartHighRdy(void); 
+void OSCtxSw(void); 
+void OSIntCtxSw(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __OS_CPU_H__ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h
new file mode 100644
index 0000000..ae687bb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_alarm.h
@@ -0,0 +1,101 @@
+#ifndef __ALT_PRIV_ALARM_H__
+#define __ALT_PRIV_ALARM_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+
+/*
+ * This header provides the internal defenitions required by the public 
+ * interface alt_alarm.h. These variables and structures are not guaranteed to 
+ * exist in future implementations of the HAL.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * "alt_alarm_s" is a structure type used to maintain lists of alarm callback
+ * functions.
+ */
+
+struct alt_alarm_s
+{
+  alt_llist llist;       /* linked list */
+  alt_u32 time;          /* time in system ticks of the callback */
+  alt_u32 (*callback) (void* context); /* callback function. The return 
+                          * value is the period for the next callback; where 
+                          * zero indicates that the alarm should be removed 
+                          * from the list. 
+                          */
+  alt_u8 rollover;       /* set when desired alarm time + current time causes
+                            overflow, to prevent premature alarm */
+  void* context;         /* Argument for the callback */
+};
+
+/*
+ * "_alt_tick_rate" is a global variable used to store the system clock rate 
+ * in ticks per second. This is initialised to zero, which coresponds to there
+ * being no system clock available. 
+ *
+ * It is then set to it's final value by the system clock driver through a call
+ * to alt_sysclk_init(). 
+ */
+
+extern alt_u32 _alt_tick_rate;
+
+/*
+ * "_alt_nticks" is a global variable which records the elapsed number of 
+ * system clock ticks since the last call to settimeofday() or since reset if
+ * settimeofday() has not been called.
+ */
+
+extern volatile alt_u32 _alt_nticks;
+
+/* The list of registered alarms. */
+
+extern alt_llist alt_alarm_list;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_PRIV_ALARM_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h
new file mode 100644
index 0000000..a165e93
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_busy_sleep.h
@@ -0,0 +1,35 @@
+#ifndef __ALT_BUSY_SLEEP_H
+#define __ALT_BUSY_SLEEP_H
+
+/*
+ * Copyright (c) 2003 Altera Corporation, San Jose, California, USA.  
+ * All rights reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
+ * deal in the Software without restriction, including without limitation the 
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is 
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The function alt_busy_sleep provides a busy loop implementation of usleep.
+ * This is used to provide usleep for the standalone HAL, or when the timer is
+ * unavailable in uC/OS-II.
+ */ 
+
+extern unsigned int alt_busy_sleep (unsigned int us);
+
+#endif /* __ALT_BUSY_SLEEP_H */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h
new file mode 100644
index 0000000..0ab7a28
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_dev_llist.h
@@ -0,0 +1,77 @@
+#ifndef __ALT_DEV_LLIST_H__
+#define __ALT_DEV_LLIST_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_llist.h"
+#include "alt_types.h"
+
+/*
+ * This header provides the internal defenitions required to control file 
+ * access. These variables and functions are not guaranteed to exist in 
+ * future implementations of the HAL.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The alt_dev_llist is an internal structure used to form a common base 
+ * class for all device types. The use of this structure allows common code
+ * to be used to manipulate the various device lists.
+ */
+
+typedef struct {
+  alt_llist llist;
+  const char* name;
+} alt_dev_llist;
+
+/*
+ *
+ */
+
+extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_DEV_LLIST_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h
new file mode 100644
index 0000000..4502ea7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_exception_handler_registry.h
@@ -0,0 +1,39 @@
+#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__
+#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include "sys/alt_exceptions.h"
+
+/* Function pointer to exception callback routine */
+extern alt_exception_result (*alt_instruction_exception_handler)
+  (alt_exception_cause, alt_u32, alt_u32);
+
+#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h
new file mode 100644
index 0000000..94007a6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_file.h
@@ -0,0 +1,179 @@
+#ifndef __ALT_FILE_H__
+#define __ALT_FILE_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_dev.h"
+#include "sys/alt_llist.h"
+#include "os/alt_sem.h"
+
+#include "alt_types.h"
+
+/*
+ * This header provides the internal defenitions required to control file 
+ * access. These variables and functions are not guaranteed to exist in 
+ * future implementations of the HAL.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The function alt_find_dev() is used to search the device list "list" to
+ * locate a device named "name". If a match is found, then a pointer to the
+ * device is returned, otherwise NULL is returned. 
+ */
+ 
+extern alt_dev* alt_find_dev (const char* name, alt_llist* list);
+
+/*
+ * alt_find_file() is used to search the list of registered file systems to
+ * find the filesystem that the file named "name" belongs to. If a match is
+ * found, then a pointer to the filesystems alt_dev structure is returned,
+ * otherwise NULL is returned.
+ *
+ * Note that a match does not indicate that the file exists, only that a 
+ * filesystem exists that is registered for a partition that could contain
+ * the file. The filesystems open() function would need to be called in order
+ * to determine if the file exists.
+ */
+
+extern alt_dev* alt_find_file (const char* name);
+
+/*
+ * alt_get_fd() is used to allocate a file descriptor for the device or 
+ * filesystem "dev". A negative return value indicates an error, otherwise the
+ * return value is the index of the file descriptor within the file descriptor
+ * pool.
+ */
+
+extern int alt_get_fd (alt_dev* dev);
+
+/*
+ * alt_release_fd() is called to free the file descriptor with index "fd".
+ */
+
+extern void alt_release_fd (int fd);
+
+/*
+ * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as 
+ * being open for exclusive access. Subsequent calls to open() for the device 
+ * associated with "fd" will fail. A device is unlocked by either calling 
+ * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for 
+ * details).
+ */
+
+extern int alt_fd_lock (alt_fd* fd);
+
+/*
+ * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously 
+ * locked by a call to alt_fd_lock().
+ */
+
+extern int alt_fd_unlock (alt_fd* fd);
+
+/*
+ * "alt_fd_list" is the pool of file descriptors.
+ */
+
+extern alt_fd alt_fd_list[];
+
+/*
+ * flags used by alt_fd. 
+ *
+ * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive
+ * access, i.e. further calls to open() for the associated device should
+ * fail.
+ *
+ * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a
+ * filesystem. 
+ */
+
+#define ALT_FD_EXCL 0x80000000
+#define ALT_FD_DEV  0x40000000
+
+#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV)
+
+/*
+ * "alt_dev_list" is the head of the linked list of registered devices.
+ */
+
+extern alt_llist alt_dev_list;
+
+/*
+ * "alt_fs_list" is the head of the linked list of registered filesystems.
+ */
+
+extern alt_llist alt_fs_list;
+
+/*
+ * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool
+ * of file descriptors is thread safe.
+ */
+
+ALT_EXTERN_SEM(alt_fd_list_lock)
+
+/*
+ * "alt_max_fd" is a 'high water mark'. It indicates the highest file 
+ * descriptor allocated. Use of this can save searching the entire pool
+ * for active file descriptors, which helps avoid contention on access 
+ * to the file descriptor pool.
+ */
+ 
+extern alt_32 alt_max_fd;
+
+/*
+ * alt_io_redirect() is called at startup to redirect stdout, stdin, and 
+ * stderr to the devices named in the input arguments. By default these streams
+ * are directed at /dev/null, and are then redirected using this function once
+ * all of the devices have been registered within the system. 
+ */
+
+extern void alt_io_redirect(const char* stdout_dev, 
+                            const char* stdin_dev, 
+                            const char* stderr_dev);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_FILE_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h
new file mode 100644
index 0000000..6c53c86
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_iic_isr_register.h
@@ -0,0 +1,39 @@
+#ifndef __ALT_IIC_ISR_REGISTER_H_
+#define __ALT_IIC_ISR_REGISTER_H_
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include "alt_types.h"
+#include "sys/alt_irq.h"
+
+extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags);
+
+#endif /* __ALT_IIC_ISR_REGISTER_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h
new file mode 100644
index 0000000..5b4a787
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_irq_table.h
@@ -0,0 +1,59 @@
+#ifndef __ALT_IRQ_TABLE_H__
+#define __ALT_IRQ_TABLE_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009      Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * Definition of a table describing each interrupt handler. The index into 
+ * the array is the interrupt id associated with the handler. 
+ *
+ * When an interrupt occurs, the associated handler is called with
+ * the argument stored in the context member.
+ *
+ * The table is physically created in alt_irq_handler.c 
+ */
+extern struct ALT_IRQ_HANDLER
+{
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  void (*handler)(void*);
+#else
+  void (*handler)(void*, alt_u32);
+#endif
+  void *context;
+} alt_irq[ALT_NIRQ];
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h
new file mode 100644
index 0000000..0e19af2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_legacy_irq.h
@@ -0,0 +1,158 @@
+#ifndef __ALT_LEGACY_IRQ_H__
+#define __ALT_LEGACY_IRQ_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file provides prototypes and inline implementations of certain routines
+ * used by the legacy interrupt API. Do not include this in your driver or 
+ * application source files, use "sys/alt_irq.h" instead to access the proper
+ * public API.
+ */
+ 
+#include <errno.h>
+#include "system.h"
+
+#ifndef NIOS2_EIC_PRESENT
+
+#include "nios2.h"
+#include "alt_types.h"
+
+#include "sys/alt_irq.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_irq_register() can be used to register an interrupt handler. If the 
+ * function is succesful, then the requested interrupt will be enabled upon 
+ * return.
+ */
+extern int alt_irq_register (alt_u32 id, 
+                             void*   context, 
+                             alt_isr_func handler);
+
+/*
+ * alt_irq_disable() disables the individual interrupt indicated by "id".
+ */
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id)
+{
+  alt_irq_context  status;
+  extern volatile alt_u32 alt_irq_active;
+
+  status = alt_irq_disable_all ();
+
+  alt_irq_active &= ~(1 << id);
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+
+  alt_irq_enable_all(status);
+
+  return 0;
+}
+
+/*
+ * alt_irq_enable() enables the individual interrupt indicated by "id".
+ */
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id)
+{
+  alt_irq_context  status;
+  extern volatile alt_u32 alt_irq_active;
+
+  status = alt_irq_disable_all ();
+
+  alt_irq_active |= (1 << id);
+  NIOS2_WRITE_IENABLE (alt_irq_active);
+
+  alt_irq_enable_all(status);
+
+  return 0;
+}
+
+#ifndef ALT_EXCEPTION_STACK
+/*
+ * alt_irq_initerruptable() should only be called from within an ISR. It is used
+ * to allow higer priority interrupts to interrupt the current ISR. The input
+ * argument, "priority", is the priority, i.e. interrupt number of the current
+ * interrupt.
+ *
+ * If this function is called, then the ISR is required to make a call to
+ * alt_irq_non_interruptible() before returning. The input argument to
+ * alt_irq_non_interruptible() is the return value from alt_irq_interruptible().
+ *
+ * Care should be taken when using this pair of functions, since they increasing
+ * the system overhead associated with interrupt handling.
+ *
+ * If you are using an exception stack then nested interrupts won't work, so
+ * these functions are not available in that case.
+ */
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority)
+{
+  extern volatile alt_u32 alt_priority_mask;
+  extern volatile alt_u32 alt_irq_active;
+
+  alt_u32 old_priority;
+
+  old_priority      = alt_priority_mask;
+  alt_priority_mask = (1 << priority) - 1;
+
+  NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask);
+
+  NIOS2_WRITE_STATUS (1);
+
+  return old_priority; 
+}
+
+/*
+ * See Comments above for alt_irq_interruptible() for an explanation of the use of this
+ * function.
+ */
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask)
+{
+  extern volatile alt_u32 alt_priority_mask;
+  extern volatile alt_u32 alt_irq_active;
+
+  NIOS2_WRITE_STATUS (0);  
+
+  alt_priority_mask = mask;
+
+  NIOS2_WRITE_IENABLE (mask & alt_irq_active);  
+}
+#endif /* ALT_EXCEPTION_STACK */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NIOS2_EIC_PRESENT */
+
+#endif /* __ALT_LEGACY_IRQ_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h
new file mode 100644
index 0000000..06a036c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/alt_no_error.h
@@ -0,0 +1,77 @@
+#ifndef __ALT_NO_ERROR_H__
+#define __ALT_NO_ERROR_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It
+ * substitutes for functions that have a return code by creating a function 
+ * that always returns zero. 
+ *
+ * This may seem a little obscure, but what happens is that the compiler can 
+ * then optomise away the call to this function, and any code written which
+ * handles the error path (i.e. non zero return values). 
+ *
+ * This allows code to be written which correctly use the uC/OS-II semaphore
+ * and flag utilities, without the use of those utilities impacting on 
+ * excutables built for a single threaded HAL environment.
+ *
+ * This function is considered to be part of the internal implementation of
+ * the HAL, and should not be called directly by application code or device
+ * drivers. It is not guaranteed to be preserved in future versions of the
+ * HAL.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void)
+{
+  return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_NO_ERROR_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h
new file mode 100644
index 0000000..4bc058d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/priv/nios2_gmon_data.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#ifndef NIOS2_GMON_DATA_H
+#define NIOS2_GMON_DATA_H
+
+#define GMON_DATA_SIG  0
+#define GMON_DATA_WORDS 1
+#define GMON_DATA_PROFILE_DATA 2
+#define GMON_DATA_PROFILE_LOWPC 3
+#define GMON_DATA_PROFILE_HIGHPC 4
+#define GMON_DATA_PROFILE_BUCKET 5
+#define GMON_DATA_PROFILE_RATE 6
+#define GMON_DATA_MCOUNT_START 7
+#define GMON_DATA_MCOUNT_LIMIT 8
+
+#define GMON_DATA_SIZE 9
+
+extern unsigned int alt_gmon_data[GMON_DATA_SIZE];
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h
new file mode 100644
index 0000000..9093080
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_alarm.h
@@ -0,0 +1,126 @@
+#ifndef __ALT_ALARM_H__
+#define __ALT_ALARM_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_llist.h"
+#include "alt_types.h"
+
+#include "priv/alt_alarm.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * "alt_alarm" is a structure type used by applications to register an alarm
+ * callback function. An instance of this type must be passed as an input
+ * argument to alt_alarm_start(). The user is not responsible for initialising
+ * the contents of the instance. This is done by alt_alarm_start(). 
+ */
+
+typedef struct alt_alarm_s alt_alarm;
+
+/* 
+ * alt_alarm_start() can be called by an application/driver in order to register
+ * a function for periodic callback at the system clock frequency. Be aware that
+ * this callback is likely to occur in interrupt context. 
+ */
+
+extern int alt_alarm_start (alt_alarm* the_alarm, 
+                            alt_u32    nticks, 
+                            alt_u32    (*callback) (void* context),
+                            void*      context);
+
+/*
+ * alt_alarm_stop() is used to unregister a callback. Alternatively the callback 
+ * can return zero to unregister.
+ */
+
+extern void alt_alarm_stop (alt_alarm* the_alarm);
+
+/*
+ * Obtain the system clock rate in ticks/s. 
+ */
+
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void)
+{
+  return _alt_tick_rate;
+}
+
+/*
+ * alt_sysclk_init() is intended to be only used by the system clock driver
+ * in order to initialise the value of the clock frequency.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks)
+{
+  if (! _alt_tick_rate)
+  {
+    _alt_tick_rate = nticks;
+    return 0;
+  }
+  else
+  {
+    return -1;
+  }
+}
+
+/*
+ * alt_nticks() returns the elapsed number of system clock ticks since reset.
+ */
+
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void)
+{
+  return _alt_nticks;
+}
+
+/*
+ * alt_tick() should only be called by the system clock driver. This is used
+ * to notify the system that the system timer period has expired.
+ */
+
+extern void alt_tick (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_ALARM_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h
new file mode 100644
index 0000000..44d976c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_cache.h
@@ -0,0 +1,117 @@
+#ifndef __ALT_CACHE_H__
+#define __ALT_CACHE_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA.     *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <stdlib.h>
+
+#include "alt_types.h"
+
+/*
+ * alt_cache.h defines the processor specific functions for manipulating the
+ * cache.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_icache_flush() is called to flush the instruction cache for a memory
+ * region of length "len" bytes, starting at address "start".
+ */
+
+extern void alt_icache_flush (void* start, alt_u32 len);
+
+/*
+ * alt_dcache_flush() is called to flush the data cache for a memory
+ * region of length "len" bytes, starting at address "start".
+ * Any dirty lines in the data cache are written back to memory.
+ */
+
+extern void alt_dcache_flush (void* start, alt_u32 len);
+
+/*
+ * alt_dcache_flush() is called to flush the data cache for a memory
+ * region of length "len" bytes, starting at address "start".
+ * Any dirty lines in the data cache are NOT written back to memory.
+ */
+
+extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len);
+
+/*
+ * Flush the entire instruction cache.
+ */
+
+extern void alt_icache_flush_all (void);
+
+/*
+ * Flush the entire data cache.
+ */
+
+extern void alt_dcache_flush_all (void);
+
+/*
+ * Allocate a block of uncached memory.
+ */
+
+extern volatile void* alt_uncached_malloc (size_t size);
+
+/*
+ * Free a block of uncached memory.
+ */
+
+extern void alt_uncached_free (volatile void* ptr);
+
+/*
+ * Convert a pointer to a block of cached memory, into a block of
+ * uncached memory.
+ */
+
+extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len);
+
+/*
+ * Convert a pointer to a block of uncached memory, into a block of
+ * cached memory.
+ */
+
+extern void* alt_remap_cached (volatile void* ptr, alt_u32 len);
+
+/*
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __ALT_CACHE_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h
new file mode 100644
index 0000000..af509d8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_debug.h
@@ -0,0 +1,45 @@
+#ifndef __ALT_DEBUG_H__
+#define __ALT_DEBUG_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break 
+ * from within software. The break is generated if "condition" evaluates to
+ * false.
+ */
+
+#define ALT_DEBUG_ASSERT(condition) if (!condition) \
+{                                                   \
+  __asm__ volatile ("break");                       \
+}
+
+#endif /* __ALT_DEBUG_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h
new file mode 100644
index 0000000..d96327e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dev.h
@@ -0,0 +1,115 @@
+#ifndef __ALT_DEV_H__
+#define __ALT_DEV_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+#include "sys/alt_llist.h"
+#include "priv/alt_dev_llist.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected 
+ * interrupt line. It cannot evaluate to a valid interrupt number.
+ */
+
+#define ALT_IRQ_NOT_CONNECTED (-1)
+
+typedef struct alt_dev_s alt_dev;
+
+struct stat;
+
+/*
+ * The file descriptor structure definition.
+ */
+
+typedef struct alt_fd_s
+{
+  alt_dev* dev;
+  alt_u8*  priv;
+  int      fd_flags;
+} alt_fd;
+
+/* 
+ * The device structure definition. 
+ */
+ 
+struct alt_dev_s {
+  alt_llist    llist;     /* for internal use */
+  const char*  name; 
+  int (*open)  (alt_fd* fd, const char* name, int flags, int mode);
+  int (*close) (alt_fd* fd);
+  int (*read)  (alt_fd* fd, char* ptr, int len);
+  int (*write) (alt_fd* fd, const char* ptr, int len); 
+  int (*lseek) (alt_fd* fd, int ptr, int dir);
+  int (*fstat) (alt_fd* fd, struct stat* buf);
+  int (*ioctl) (alt_fd* fd, int req, void* arg);
+};
+
+/*
+ * Functions used to register device for access through the C standard 
+ * library.
+ *
+ * The only difference between alt_dev_reg() and alt_fs_reg() is the 
+ * interpretation that open() places on the device name. In the case of
+ * alt_dev_reg the device is assumed to be a particular character device,
+ * and so there must be an exact match in the name for open to succeed. 
+ * In the case of alt_fs_reg() the name of the device is treated as the
+ * mount point for a directory, and so any call to open() where the name 
+ * is the root of the device filename will succeed. 
+ */
+
+extern int alt_fs_reg  (alt_dev* dev); 
+
+static ALT_INLINE int alt_dev_reg (alt_dev* dev)
+{
+  extern alt_llist alt_dev_list;
+
+  return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list);
+}
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif /* __ALT_DEV_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h
new file mode 100644
index 0000000..88dcda0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma.h
@@ -0,0 +1,226 @@
+#ifndef __ALT_DMA_H__
+#define __ALT_DMA_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_dma_dev.h"
+#include "alt_types.h"
+
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * This header contains the application side interface for accessing DMA 
+ * resources. See alt_dma_dev.h for the dma device driver interface.
+ *
+ * The interface model treats a DMA transaction as being composed of two 
+ * halves (read and write). 
+ *
+ * The application can supply data for transmit using an "alt_dma_txchan"
+ * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to
+ * receive data.
+ */
+
+/*
+ * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for
+ * a DMA transmit device. The name is the name of the associated physical
+ * device (e.g. "/dev/dma_0").
+ *
+ * The return value will be NULL on failure, and non-NULL otherwise. 
+ */
+
+extern alt_dma_txchan alt_dma_txchan_open (const char* name);
+
+/*
+ * alt_dma_txchan_close() is provided so that an application can notify the 
+ * system that it has finished with a given DMA transmit channel. This is only
+ * provided for completness.
+ */
+
+static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma)
+{
+  return 0;
+}
+
+/*
+ * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel.
+ * The input arguments are:
+ *
+ * dma: the channel to use.
+ * from: a pointer to the start of the data to send.
+ * length: the length of the data to send in bytes.
+ * done: callback function that will be called once the data has been sent.
+ * handle: opaque value passed to "done".
+ *
+ * The return value will be negative if the request cannot be posted, and
+ * zero otherwise.
+ */
+
+static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, 
+             const void* from, 
+             alt_u32 length,
+             alt_txchan_done* done, 
+             void* handle)
+{
+  return dma ? dma->dma_send (dma, 
+        from, 
+        length,
+        done, 
+        handle) : -ENODEV;
+}
+
+/*
+ * alt_dma_txchan_space() returns the number of tranmit requests that can be 
+ * posted to the specified DMA transmit channel.
+ *
+ * A negative value indicates that the value could not be determined. 
+ */
+
+static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma)
+{
+  return dma ? dma->space (dma) : -ENODEV;
+}
+
+/*
+ * alt_dma_txchan_ioctl() can be used to perform device specific I/O 
+ * operations on the indicated DMA transmit channel. For example some drivers
+ * support options to control the width of the transfer operations. See
+ * alt_dma_dev.h for the list of generic requests.
+ *
+ * A negative return value indicates failure, otherwise the interpretation
+ * of the return value is request specific.  
+ */
+
+static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, 
+              int            req, 
+              void*          arg)
+{
+  return dma ? dma->ioctl (dma, req, arg) : -ENODEV;
+}
+
+/*
+ * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for
+ * a DMA receive channel. The name is the name of the associated physical
+ * device (e.g. "/dev/dma_0").
+ *
+ * The return value will be NULL on failure, and non-NULL otherwise. 
+ */
+
+extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev);
+
+/*
+ * alt_dma_rxchan_close() is provided so that an application can notify the 
+ * system that it has finished with a given DMA receive channel. This is only
+ * provided for completness.
+ */
+
+static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma)
+{
+  return 0;
+}
+
+/*
+ *
+ */
+
+/*
+ * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel.
+ * 
+ * The input arguments are:
+ *
+ * dma: the channel to use.
+ * data: a pointer to the location that data is to be received to.
+ * len: the maximum length of the data to receive. 
+ * done: callback function that will be called once the data has been 
+ *       received.
+ * handle: opaque value passed to "done".
+ *
+ * The return value will be negative if the request cannot be posted, and
+ * zero otherwise.
+ */
+
+static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan   dma, 
+                                              void*            data,
+                                              alt_u32          len,
+                                              alt_rxchan_done* done,  
+                                              void*            handle)
+{
+  return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV;
+}
+
+/*
+ * alt_dma_rxchan_ioctl() can be used to perform device specific I/O 
+ * operations on the indicated DMA receive channel. For example some drivers
+ * support options to control the width of the transfer operations. See
+ * alt_dma_dev.h for the list of generic requests.
+ *
+ * A negative return value indicates failure, otherwise the interpretation
+ * of the return value is request specific.  
+ */
+
+static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, 
+              int            req, 
+              void*          arg)
+{
+  return dma ? dma->ioctl (dma, req, arg) : -ENODEV;
+}
+
+/*
+ * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store
+ * receive requests.
+ */
+
+static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma)
+{
+  return dma->depth;
+}
+
+/*
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h
new file mode 100644
index 0000000..65063bd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_dma_dev.h
@@ -0,0 +1,200 @@
+#ifndef __ALT_DMA_DEV_H__
+#define __ALT_DMA_DEV_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "priv/alt_dev_llist.h"
+
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * This header contains the device driver interface for accessing DMA 
+ * resources. See alt_dma.h for the DMA application side interface.
+ *
+ * The interface model treats a DMA transaction as being composed of two 
+ * halves (read and write). 
+ *
+ * An "alt_dma_txchan_dev" is used to describe the device associated with a
+ * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the
+ * device associated with a DMA receive channel. 
+ */
+
+/*
+ * List of generic ioctl requests that may be supported by a DMA device.
+ *
+ * ALT_DMA_RX_ONLY_ON:    This causes a DMA channel to operate in a mode
+ *                        where only the receiver is under software control.
+ *                        The other side reads continously from a single
+ *                        location. The address to read is the argument to
+ *                        this request.
+ * ALT_DMA_RX_ONLY_OFF:   Return to the default mode where both the receive
+ *                        and transmit sides of the DMA can be under software
+ *                        control.
+ * ALT_DMA_TX_ONLY_ON:    This causes a DMA channel to operate in a mode
+ *                        where only the transmitter is under software control.
+ *                        The other side writes continously to a single
+ *                        location. The address to write to is the argument to
+ *                        this request.
+ * ALT_DMA_TX_ONLY_OFF:   Return to the default mode where both the receive
+ *                        and transmit sides of the DMA can be under software
+ *                        control.
+ * ALT_DMA_SET_MODE_8:    Transfer data in units of 8 bits.
+ * ALT_DMA_SET_MODE_16:   Transfer data in units of 16 bits.
+ * ALT_DMA_SET_MODE_32:   Transfer data in units of 32 bits.
+ * ALT_DMA_SET_MODE_64:   Transfer data in units of 64 bits.
+ * ALT_DMA_SET_MODE_128:  Transfer data in units of 128 bits.
+ * ALT_DMA_GET_MODE:      Get the current transfer mode.
+ *
+ * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF
+ * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should
+ * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, 
+ * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF.
+ */
+
+#define ALT_DMA_TX_STREAM_ON  (0x1)
+#define ALT_DMA_TX_STREAM_OFF (0x2)
+#define ALT_DMA_RX_STREAM_ON  (0x3)
+#define ALT_DMA_RX_STREAM_OFF (0x4)
+#define ALT_DMA_SET_MODE_8    (0x5)
+#define ALT_DMA_SET_MODE_16   (0x6)
+#define ALT_DMA_SET_MODE_32   (0x7)
+#define ALT_DMA_SET_MODE_64   (0x8)
+#define ALT_DMA_SET_MODE_128  (0x9)
+#define ALT_DMA_GET_MODE      (0xa)
+
+#define ALT_DMA_RX_ONLY_ON    ALT_DMA_TX_STREAM_ON
+#define ALT_DMA_RX_ONLY_OFF   ALT_DMA_TX_STREAM_OFF
+#define ALT_DMA_TX_ONLY_ON    ALT_DMA_RX_STREAM_ON
+#define ALT_DMA_TX_ONLY_OFF   ALT_DMA_RX_STREAM_OFF
+
+/*
+ *
+ */
+
+typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev;
+typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev;
+
+typedef alt_dma_txchan_dev* alt_dma_txchan;
+typedef alt_dma_rxchan_dev* alt_dma_rxchan;
+
+typedef void (alt_txchan_done)(void* handle);
+typedef void (alt_rxchan_done)(void* handle, void* data);
+
+/*
+ * devices that provide a DMA transmit channel are required to provide an
+ * instance of the "alt_dma_txchan_dev" structure. 
+ */
+
+struct alt_dma_txchan_dev_s {
+  alt_llist  llist;                  /* for internal use */
+  const char* name;                  /* name of the device instance 
+                                      * (e.g. "/dev/dma_0"). 
+                                      */
+  int (*space) (alt_dma_txchan dma); /* returns the maximum number of 
+                                      * transmit requests that can be posted
+              */
+  int (*dma_send) (alt_dma_txchan dma,   
+         const void* from, 
+         alt_u32 len,
+         alt_txchan_done* done, 
+         void* handle);        /* post a transmit request */
+  int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device
+              * specific I/O control.
+                                      */ 
+};
+
+/*
+ * devices that provide a DMA receive channel are required to provide an
+ * instance of the "alt_dma_rxchan_dev" structure. 
+ */
+
+struct alt_dma_rxchan_dev_s {
+  alt_llist list;                    /* for internal use */
+  const char* name;                  /* name of the device instance 
+                                      * (e.g. "/dev/dma_0"). 
+                                      */
+  alt_u32        depth;              /* maximum number of receive requests that
+                                      * can be posted.
+                                      */
+  int (*prepare) (alt_dma_rxchan   dma, 
+                  void*            data,
+                  alt_u32          len,
+                  alt_rxchan_done* done,  
+                  void*            handle); /* post a receive request */
+  int (*ioctl) (alt_dma_rxchan dma, int req, void* arg);  /* perform device
+              * specific I/O control.
+                                      */ 
+};
+
+/*
+ * Register a DMA transmit channel with the system.
+ */
+
+static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev)
+{
+  extern alt_llist alt_dma_txchan_list;
+
+  return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list);
+}
+
+/*
+ * Register a DMA receive channel with the system.
+ */
+
+static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev)
+{
+  extern alt_llist alt_dma_rxchan_list;
+
+  return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list);
+}
+
+/*
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_DEV_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h
new file mode 100644
index 0000000..ca7aea1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_driver.h
@@ -0,0 +1,168 @@
+#ifndef __ALT_DRIVER_H__
+#define __ALT_DRIVER_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/*
+ * Macros used to access a driver without HAL file descriptors.
+ */
+
+/*
+ * ALT_MODULE_CLASS
+ *
+ * This macro returns the module class name for the specified module instance.
+ * It uses information in the system.h file.
+ * Neither the instance name or class name are quoted (so that they can
+ * be used with other pre-processor macros).
+ *
+ * Example:
+ *   Assume the design has an instance of an altera_avalon_uart called uart1.
+ *   Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart.
+ */
+
+#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance
+
+
+/*
+ * ALT_DRIVER_FUNC_NAME
+ *
+ *   --> instance               Instance name.
+ *   --> func                   Function name.
+ *
+ * This macro returns the device driver function name of the specified
+ * module instance for the specified function name.
+ *
+ * Example:
+ *   Assume the design has an instance of an altera_avalon_uart called uart1.
+ *   Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns 
+ *   altera_avalon_uart_write.
+ */
+
+#define ALT_DRIVER_FUNC_NAME(instance, func) \
+  ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func)
+#define ALT_DRIVER_FUNC_NAME1(module_class, func) \
+  ALT_DRIVER_FUNC_NAME2(module_class, func)
+#define ALT_DRIVER_FUNC_NAME2(module_class, func) \
+  module_class ## _ ## func
+
+/*
+ * ALT_DRIVER_STATE_STRUCT
+ *
+ *   --> instance               Instance name.
+ *
+ * This macro returns the device driver state type name of the specified
+ * module instance.
+ *
+ * Example:
+ *   Assume the design has an instance of an altera_avalon_uart called uart1.
+ *   Calling ALT_DRIVER_STATE_STRUCT(uart1) returns:
+ *     struct altera_avalon_uart_state_s
+ *
+ * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't
+ * really a function but it does match the required naming convention.
+ */
+#define ALT_DRIVER_STATE_STRUCT(instance) \
+    struct ALT_DRIVER_FUNC_NAME(instance, state_s)
+
+/*
+ * ALT_DRIVER_STATE
+ *
+ *   --> instance               Instance name.
+ *
+ * This macro returns the device driver state name of the specified
+ * module instance.
+ *
+ * Example:
+ *   Assume the design has an instance of an altera_avalon_uart called uart1.
+ *   Calling ALT_DRIVER_STATE(uart1) returns uart1.
+ */
+#define ALT_DRIVER_STATE(instance) instance
+
+/*
+ * ALT_DRIVER_WRITE
+ *
+ *   --> instance               Instance name.
+ *   --> buffer                 Write buffer.
+ *   --> len                    Length of write buffer data.
+ *   --> flags                  Control flags (e.g. O_NONBLOCK)
+ *
+ * This macro calls the "write" function of the specified driver instance.
+ */
+
+#define ALT_DRIVER_WRITE_EXTERNS(instance)                                  \
+    extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance);    \
+    extern int ALT_DRIVER_FUNC_NAME(instance, write)                        \
+      (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int);
+
+#define ALT_DRIVER_WRITE(instance, buffer, len, flags)                      \
+    ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags)
+
+
+/*
+ * ALT_DRIVER_READ
+ *
+ *   --> instance               Instance name.
+ *   <-- buffer                 Read buffer.
+ *   --> len                    Length of read buffer.
+ *   --> flags                  Control flags (e.g. O_NONBLOCK)
+ *
+ * This macro calls the "read" function of the specified driver instance.
+ */
+
+#define ALT_DRIVER_READ_EXTERNS(instance)                                   \
+    extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance);    \
+    extern int ALT_DRIVER_FUNC_NAME(instance, read)                         \
+      (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int);
+
+#define ALT_DRIVER_READ(instance, buffer, len, flags)                       \
+    ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags)
+
+/*
+ * ALT_DRIVER_IOCTL
+ *
+ *   --> instance               Instance name.
+ *   --> req                    ioctl request (e.g. TIOCSTIMEOUT)
+ *   --> arg                    Optional argument (void*)
+ *
+ * This macro calls the "ioctl" function of the specified driver instance
+ */
+
+#define ALT_DRIVER_IOCTL_EXTERNS(instance)                                  \
+    extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance);    \
+    extern int ALT_DRIVER_FUNC_NAME(instance, ioctl)                        \
+      (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*);
+
+#define ALT_DRIVER_IOCTL(instance, req, arg)                                \
+    ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg)
+
+#endif /* __ALT_DRIVER_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h
new file mode 100644
index 0000000..23e3096
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_errno.h
@@ -0,0 +1,87 @@
+#ifndef __ALT_ERRNO_H__
+#define __ALT_ERRNO_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * errno is defined in <errno.h> so that it uses the thread local version 
+ * stored in the location pointed to by "_impure_ptr". This means that the 
+ * accesses to errno within the HAL library can cause the entirety of 
+ * of the structure pointed to by "_impure_ptr" to be added to the 
+ * users application. This can be undesirable in very small footprint systems.
+ *
+ * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below,
+ * to access errno, rather than accessing it directly. This macro will only 
+ * use the thread local version if some other code has already caused it to be 
+ * included into the system, otherwise it will use the global errno value.
+ *
+ * This causes a slight increases in code size where errno is accessed, but 
+ * can lead to significant overall benefits in very small systems. The 
+ * increase is inconsequential when compared to the size of the structure
+ * pointed to by _impure_ptr.
+ *
+ * Note that this macro accesses __errno() using an externally declared 
+ * function pointer (alt_errno). This is done so that the function call uses the
+ * subroutine call instruction via a register rather than an immediate address.
+ * This is important in the case that the code has been linked for a high
+ * address, but __errno() is not being used. In this case the weak linkage
+ * would have resulted in the instruction: "call 0" which would fail to link. 
+ */
+
+extern int* (*alt_errno) (void);
+
+/* Must define this so that values such as EBADFD are defined in errno.h. */
+#define __LINUX_ERRNO_EXTENSIONS__
+
+#include <errno.h>
+
+#include "alt_types.h"
+
+#undef errno
+
+extern int errno;
+
+static ALT_INLINE int* alt_get_errno(void)
+{
+  return ((alt_errno) ? alt_errno() : &errno);
+}
+
+#define ALT_ERRNO *alt_get_errno()
+
+#endif /* __ALT_ERRNO_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h
new file mode 100644
index 0000000..9c938b9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_exceptions.h
@@ -0,0 +1,166 @@
+#ifndef __ALT_EXCEPTIONS_H__
+#define __ALT_EXCEPTIONS_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include "alt_types.h"
+#include "system.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * This file defines instruction-generated exception handling and registry
+ * API, exception type enumeration, and handler return value enumeration for
+ * Nios II.
+ */
+
+/*
+ * The following enumeration describes the value in the CPU EXCEPTION
+ * register CAUSE bit field.
+ */
+enum alt_exception_cause_e {
+  /*
+   * This value is passed to an exception handler's cause argument if
+   * "extra exceptions" information (EXECPTION) register is not
+   * present in the processor hardware configuration.
+   */
+  NIOS2_EXCEPTION_CAUSE_NOT_PRESENT            = -1,
+
+  /*
+   * Real values
+   */
+  NIOS2_EXCEPTION_RESET                        = 0,
+  NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST       = 1,
+  NIOS2_EXCEPTION_INTERRUPT                    = 2,
+  NIOS2_EXCEPTION_TRAP_INST                    = 3,
+  NIOS2_EXCEPTION_UNIMPLEMENTED_INST           = 4,
+  NIOS2_EXCEPTION_ILLEGAL_INST                 = 5,
+  NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR         = 6,
+  NIOS2_EXCEPTION_MISALIGNED_TARGET_PC         = 7,
+  NIOS2_EXCEPTION_DIVISION_ERROR               = 8,
+  NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR    = 9,
+  NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST         = 10,
+  NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR    = 11,
+  NIOS2_EXCEPTION_TLB_MISS                     = 12,
+  NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION   = 13,
+  NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION      = 14,
+  NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION     = 15,
+  NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION    = 16,
+  NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION    = 17,
+  NIOS2_EXCEPTION_ECC_TLB_ERR                  = 18,
+  NIOS2_EXCEPTION_ECC_FETCH_ERR                = 19,
+  NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR        = 20,
+  NIOS2_EXCEPTION_ECC_DATA_ERR                 = 21,
+  NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
+};
+typedef enum alt_exception_cause_e alt_exception_cause;
+
+/*
+ * These define valid return values for a user-defined instruction-generated
+ * exception handler. The handler should return one of these to indicate
+ * whether to re-issue the instruction that triggered the exception, or to
+ * skip it.
+ */
+enum alt_exception_result_e {
+  NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0,
+  NIOS2_EXCEPTION_RETURN_SKIP_INST    = 1
+};
+typedef enum alt_exception_result_e alt_exception_result;
+
+/*
+ * alt_instruction_exception_register() can be used to register an exception
+ * handler for instruction-generated exceptions that are not handled by the
+ * built-in exception handler (i.e. for interrupts).
+ *
+ * The registry API is optionally enabled through the "Enable
+ * Instruction-related Exception API" HAL BSP setting, which will
+ * define the macro below.
+ */
+#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
+void alt_instruction_exception_register (
+  alt_exception_result (*exception_handler)(
+    alt_exception_cause cause,
+    alt_u32 exception_pc,
+    alt_u32 bad_addr) );
+#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
+
+/*
+ * alt_exception_cause_generated_bad_addr() indicates whether a particular
+ * exception cause value was from an exception-type that generated a valid
+ * address in the BADADDR register. The contents of BADADDR is passed to
+ * a user-registered exception handler in all cases, whether valid or not.
+ * This routine should be called to validate the bad_addr argument to
+ * your exception handler.
+ *
+ * Note that this routine will return false (0) for causes 
+ * NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR.
+ * You must read the TLBMISC.D field to determine if BADADDR
+ * is valid for these (valid if TLBMISC.D = 1).
+ */
+int alt_exception_cause_generated_bad_addr(alt_exception_cause cause);
+
+/*
+ * alt_ecc_fatal_exception_register() is called to register a handler to
+ * service likely fatal ECC error exceptions. Likely the handler will
+ * assume that correct execution of the running software is not possible
+ * and re-initialize the processor (e.g. jump to reset address).
+ * 
+ * Passing null (0x0) in the handler argument will disable a previously-
+ * registered handler.
+ *
+ * Note that if no handler is registered, just normal exception processing
+ * occurs on a likely fatal ECC exception and the exception processing
+ * code might trigger an infinite exception loop.
+ *
+ * Note that the handler isn't a C function: it must be written in 
+ * assembly-code because it doesn't support C language calling conventions
+ * and it can't return.
+ *
+ * The handler code must be carefully written to avoid triggering
+ * another fatal ECC exception and creating an infinite exception loop.
+ * The handler must avoid reading registers in case the fatal ECC
+ * error is a register file ECC error.
+ * If a data cache is present, the handler must avoid instructions that
+ * access the data cache in case the fatal ECC error is a data cache 
+ * related ECC error. This includes cacheable load, cacheable store, 
+ * non-cacheable store (because it looks in the data cache to update the
+ * data cache if it hits), and all data cache management instructions except
+ * for INITD.
+ */
+void alt_ecc_fatal_exception_register(alt_u32 handler);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_EXCEPTIONS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h
new file mode 100644
index 0000000..f1ab10d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash.h
@@ -0,0 +1,181 @@
+#ifndef __ALT_FLASH_H__
+#define __ALT_FLASH_H__
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* Alt_flash.h - User interface for flash code                                 *
+*                                                                             *
+* Use this interface to avoid being exposed to the internals of the device    *
+* driver architecture. If you chose to use the flash driver internal          *
+* structures we don't guarantee not to change them                            *
+*                                                                             *
+* Author PRR                                                                  *
+*                                                                             *
+******************************************************************************/
+
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include "alt_types.h"
+#include "alt_flash_types.h"
+#include "alt_flash_dev.h"
+#include "sys/alt_cache.h"
+
+alt_flash_fd* alt_flash_open_dev(const char* name);
+void alt_flash_close_dev(alt_flash_fd* fd );
+
+/*
+ *  alt_flash_lock
+ *
+ *  Locks the range of the memory sectors, which 
+ *  protected from write and erase.
+ *
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_lock_flash( 
+                                      alt_flash_fd* fd, alt_u32 sectors_to_lock)
+{
+  return fd->lock( fd, sectors_to_lock);
+}
+
+/*
+ *  alt_write_flash
+ *
+ *  Program a buffer into flash.
+ *
+ *  This routine erases all the affected erase blocks (if necessary)
+ *  and then programs the data. However it does not read the data out first
+ *  and preserve and none overwritten data, because this would require very 
+ *  large buffers on the target. If you need
+ *  that functionality use the functions below.
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_write_flash(
+                                                           alt_flash_fd* fd, 
+                                                           int offset, 
+                                                           const void* src_addr, 
+                                                           int length )
+{
+  return fd->write( fd, offset, src_addr, length );
+}
+
+/*
+ *  alt_read_flash
+ *
+ *  Read a block of flash for most flashes this is just memcpy
+ *  it's here for completeness in case we need it for some serial flash device
+ *
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_read_flash( 
+                                      alt_flash_fd* fd, int offset, 
+                                      void* dest_addr, int length )
+{
+  return fd->read( fd, offset, dest_addr, length );
+}
+
+/*
+ *  alt_get_flash_info
+ *
+ *  Return the information on the flash sectors.
+ * 
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( 
+                                      alt_flash_fd* fd, flash_region** info, 
+                                      int* number_of_regions)
+{
+  return fd->get_info( fd, info, number_of_regions);
+}
+
+/*
+ *  alt_erase_flash_block
+ *
+ *  Erase a particular erase block, pass in the offset to the start of 
+ *  the block and it's size
+ */
+static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( 
+                                      alt_flash_fd* fd, int offset, int length) 
+{
+  int ret_code;
+  ret_code = fd->erase_block( fd, offset );
+  
+/* remove dcache_flush call for FB330552  
+  if(!ret_code)
+      alt_dcache_flush((alt_u8*)fd->base_addr + offset, length);
+*/
+  return ret_code;
+}
+
+/*
+ *  alt_write_flash_block
+ *
+ *  Write a particular flash block, block_offset is the offset 
+ *  (from the base of flash) to start of the block
+ *  data_offset is the offset (from the base of flash)
+ *  where you wish to start programming
+ *  
+ *  NB this function DOES NOT check that you are only writing a single
+ *  block of data as that would slow down this function. 
+ *
+ *  Use alt_write_flash if you want that level of error checking.
+ */
+
+static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( 
+                                      alt_flash_fd* fd, int block_offset,
+                                      int data_offset,
+                                      const void *data, int length)
+{
+
+  int ret_code;
+  ret_code = fd->write_block( fd, block_offset, data_offset, data, length );
+
+/* remove dcache_flush call for FB330552  
+  if(!ret_code)
+      alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length);
+*/
+  return ret_code;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_FLASH_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h
new file mode 100644
index 0000000..6d06725
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_dev.h
@@ -0,0 +1,100 @@
+#ifndef __ALT_FLASH_DEV_H__
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* Alt_flash_dev.h - Generic Flash device interfaces                           *
+*                                                                             *
+* Author PRR                                                                  *
+*                                                                             *
+******************************************************************************/
+#define __ALT_FLASH_DEV_H__
+
+#include "alt_flash_types.h"
+#include "sys/alt_llist.h"
+#include "priv/alt_dev_llist.h"
+
+#include "alt_types.h"
+
+typedef struct alt_flash_dev alt_flash_dev; 
+typedef alt_flash_dev alt_flash_fd;
+
+static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd)
+{
+  extern alt_llist alt_flash_dev_list;
+
+  return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list);
+}
+
+typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, 
+                                         const char* name );
+typedef int (*alt_flash_close)(alt_flash_dev* flash_info);
+
+typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, 
+                                const void* src_addr, int length );
+
+typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, 
+                                          int* number_of_regions);
+typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, 
+                                      int data_offset, const void* data, 
+                                      int length);
+typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset);
+typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, 
+                              void* dest_addr, int length );
+typedef int (*alt_flash_lock)(alt_flash_dev* flash, alt_u32 sectors_to_lock);						  
+
+struct alt_flash_dev
+{
+  alt_llist                 llist;
+  const char*               name;
+  alt_flash_open            open;
+  alt_flash_close           close;
+  alt_flash_write           write;
+  alt_flash_read            read;
+  alt_flash_get_flash_info  get_info;
+  alt_flash_erase_block     erase_block;
+  alt_flash_write_block     write_block;
+  void*                     base_addr;
+  int                       length;
+  int                       number_of_regions;
+  flash_region              region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; 
+  alt_flash_lock            lock;
+};
+
+#endif /* __ALT_FLASH_DEV_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h
new file mode 100644
index 0000000..10f1f01
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_flash_types.h
@@ -0,0 +1,64 @@
+#ifndef __ALT_FLASH_TYPES_H__
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* Alt_flash_types.h - Some generic types and defines used by the flash code   *
+*                                                                             *
+* Author PRR                                                                  *
+*                                                                             *
+******************************************************************************/
+#define __ALT_FLASH_TYPES_H__
+
+#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS
+#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8
+#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */
+
+/*
+ * Description of a single Erase region
+ */
+typedef struct flash_region
+{
+  int   offset;
+  int   region_size;
+  int   number_of_blocks;
+  int   block_size;
+}flash_region;
+
+#endif /* __ALT_FLASH_TYPES_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h
new file mode 100644
index 0000000..94a556a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq.h
@@ -0,0 +1,245 @@
+#ifndef __ALT_IRQ_H__
+#define __ALT_IRQ_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * alt_irq.h is the Nios II specific implementation of the interrupt controller 
+ * interface.
+ *
+ * Nios II includes optional support for an external interrupt controller. 
+ * When an external controller is present, the "Enhanced" interrupt API
+ * must be used to manage individual interrupts. The enhanced API also
+ * supports the processor's internal interrupt controller. Certain API
+ * members are accessible from either the "legacy" or "enhanced" interrpt
+ * API. 
+ *
+ * Regardless of which API is in use, this file should be included by
+ * application code and device drivers that register ISRs or manage interrpts.
+ */
+#include <errno.h>
+
+#include "nios2.h"
+#include "alt_types.h"
+#include "system.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * Macros used by alt_irq_enabled
+ */
+#define ALT_IRQ_ENABLED  1
+#define ALT_IRQ_DISABLED 0  
+
+/* 
+ * Number of available interrupts in internal interrupt controller.
+ */
+#define ALT_NIRQ NIOS2_NIRQ
+
+/*
+ * Used by alt_irq_disable_all() and alt_irq_enable_all().
+ */
+typedef int alt_irq_context;
+
+/* ISR Prototype */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+typedef void (*alt_isr_func)(void* isr_context);
+#else
+typedef void (*alt_isr_func)(void* isr_context, alt_u32 id);
+#endif
+
+/*
+ * The following protypes and routines are supported by both
+ * the enhanced and legacy interrupt APIs
+ */
+ 
+/*
+ * alt_irq_enabled can be called to determine if the processor's global
+ * interrupt enable is asserted. The return value is zero if interrupts 
+ * are disabled, and non-zero otherwise.
+ *
+ * Whether the internal or external interrupt controller is present, 
+ * individual interrupts may still be disabled. Use the other API to query
+ * a specific interrupt. 
+ */
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void)
+{
+  int status;
+
+  NIOS2_READ_STATUS (status);
+
+  return status & NIOS2_STATUS_PIE_MSK; 
+}
+
+/*
+ * alt_irq_disable_all() 
+ *
+ * This routine inhibits all interrupts by negating the status register PIE 
+ * bit. It returns the previous contents of the CPU status register (IRQ 
+ * context) which can be used to restore the status register PIE bit to its 
+ * state before this routine was called.
+ */
+static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE 
+       alt_irq_disable_all (void)
+{
+  alt_irq_context context;
+
+  NIOS2_READ_STATUS (context);
+
+  NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK);
+  
+  return context;
+}
+
+/*
+ * alt_irq_enable_all() 
+ *
+ * Enable all interrupts that were previously disabled by alt_irq_disable_all()
+ *
+ * This routine accepts a context to restore the CPU status register PIE bit
+ * to the state prior to a call to alt_irq_disable_all().
+ 
+ * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), 
+ * this means that alt_irq_enable_all() does not necessarily re-enable
+ * interrupts.
+ *
+ * This routine will perform a read-modify-write sequence to restore only
+ * status.PIE if the processor is configured with options that add additional 
+ * writeable status register bits. These include the MMU, MPU, the enhanced 
+ * interrupt controller port, and shadow registers. Otherwise, as a performance
+ * enhancement, status is overwritten with the prior context. 
+ */
+static ALT_INLINE void ALT_ALWAYS_INLINE 
+       alt_irq_enable_all (alt_irq_context context)
+{
+#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \
+    (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT)
+  alt_irq_context status;
+  
+  NIOS2_READ_STATUS (status);
+  
+  status &= ~NIOS2_STATUS_PIE_MSK;
+  status |= (context & NIOS2_STATUS_PIE_MSK);
+  
+  NIOS2_WRITE_STATUS (status);
+#else
+  NIOS2_WRITE_STATUS (context);
+#endif
+}
+
+/*
+ * The function alt_irq_init() is defined within the auto-generated file
+ * alt_sys_init.c. This function calls the initilization macros for all
+ * interrupt controllers in the system at config time, before any other
+ * non-interrupt controller driver is initialized.
+ *
+ * The "base" parameter is ignored and only present for backwards-compatibility.
+ * It is recommended that NULL is passed in for the "base" parameter.
+ */
+extern void alt_irq_init (const void* base);
+
+/*
+ * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts.
+ */
+static ALT_INLINE void ALT_ALWAYS_INLINE 
+       alt_irq_cpu_enable_interrupts (void)
+{
+    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
+#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)
+    | NIOS2_STATUS_RSIE_MSK
+#endif      
+      );
+}
+
+
+/*
+ * Prototypes for the enhanced interrupt API.
+ */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+/*
+ * alt_ic_isr_register() can be used to register an interrupt handler. If the
+ * function is succesful, then the requested interrupt will be enabled upon 
+ * return.
+ */
+extern int alt_ic_isr_register(alt_u32 ic_id,
+                        alt_u32 irq,
+                        alt_isr_func isr,
+                        void *isr_context,
+                        void *flags);
+
+/* 
+ * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific 
+ * interrupt by using IRQ port and interrupt controller instance.
+ */
+int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq);
+int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq);        
+
+ /* 
+ * alt_ic_irq_enabled() indicates whether a specific interrupt, as
+ * specified by IRQ port and interrupt controller instance is enabled.
+ */        
+alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq);
+
+#else 
+/*
+ * Prototypes for the legacy interrupt API.
+ */
+#include "priv/alt_legacy_irq.h"
+#endif 
+
+
+/*
+ * alt_irq_pending() returns a bit list of the current pending interrupts.
+ * This is used by alt_irq_handler() to determine which registered interrupt
+ * handlers should be called.
+ *
+ * This routine is only available for the Nios II internal interrupt
+ * controller.
+ */
+#ifndef NIOS2_EIC_PRESENT
+static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void)
+{
+  alt_u32 active;
+
+  NIOS2_READ_IPENDING (active);
+
+  return active;
+}
+#endif 
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_IRQ_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h
new file mode 100644
index 0000000..549811c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_irq_entry.h
@@ -0,0 +1,39 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file pulls in the IRQ entry assembler and C code, which is only
+ * required if there are any interruptes in the system.
+ */
+
+__asm__( "\n\t.globl alt_irq_entry" );
+
+__asm__( "\n\t.globl alt_irq_handler" );
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h
new file mode 100644
index 0000000..1d1f16f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h
@@ -0,0 +1,77 @@
+#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__
+#define __ALT_LICENSE_REMINDER_UCOSII_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include <stdio.h>
+
+#define ALT_LICENSE_REMINDER_UCOSII_STRING                                     \
+    "============== Software License Reminder ===============\n"               \
+    "\n"                                                                       \
+    "uC/OS-II is provided in source form for FREE evaluation,\n"               \
+    "for educational use, or for peaceful research. If you\n"                  \
+    "plan on using uC/OS-II in a commercial product you need\n"                \
+    "to contact Micrium to properly license its use in your\n"                 \
+    "product. Micrium provides ALL the source code on the\n"                   \
+    "Altera distribution for your convenience and to help you\n"               \
+    "experience uC/OS-II. The fact that the source is provided\n"              \
+    "does NOT mean that you can use it without paying a\n"                     \
+    "licensing fee. Please help us continue to provide the\n"                  \
+    "Embedded community with the finest software available.\n"                 \
+    "Your honesty is greatly appreciated.\n"                                   \
+    "\n"                                                                       \
+    "Please contact:\n"                                                        \
+    "\n"                                                                       \
+    "M I C R I U M\n"                                                          \
+    "949 Crestview Circle\n"                                                   \
+    "Weston,  FL 33327-1848\n"                                                 \
+    "U.S.A.\n"                                                                 \
+    "\n"                                                                       \
+    "Phone : +1 954 217 2036\n"                                                \
+    "FAX   : +1 954 217 2037\n"                                                \
+    "WEB   : www.micrium.com\n"                                                \
+    "E-mail: Sales@Micrium.com\n"                                              \
+    "\n"                                                                       \
+    "========================================================\n"
+
+#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING)
+
+
+#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h
new file mode 100644
index 0000000..84cb051
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_llist.h
@@ -0,0 +1,123 @@
+#ifndef __ALT_LIST_H__
+#define __ALT_LIST_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+
+/*
+ * alt_llist.h defines structures and functions for use in manipulating linked
+ * lists. A list is considered to be constructed from a chain of objects of
+ * type alt_llist, with one object being defined to be the head element. 
+ *
+ * A list is considered to be empty if it only contains the head element.
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_llist is the structure used to represent an element within a linked
+ * list.
+ */
+
+typedef struct alt_llist_s alt_llist;
+
+struct alt_llist_s {
+  alt_llist* next;     /* Pointer to the next element in the list. */
+  alt_llist* previous; /* Pointer to the previous element in the list. */
+};
+
+/*
+ * ALT_LLIST_HEAD is a macro that can be used to create the head of a new 
+ * linked list. This is named "head". The head element is initialised to 
+ * represent an empty list.  
+ */
+
+#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head}
+
+/*
+ * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list
+ * entry. This is used to reserve space in structure initialisation for
+ * structures that inherit form alt_llist.
+ */
+
+#define ALT_LLIST_ENTRY {0, 0}
+
+/*
+ * alt_llist_insert() insert adds the linked list entry "entry" as the 
+ * first entry in the linked list "list". "list" is the list head element.  
+ */
+
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, 
+                alt_llist* entry)
+{
+  entry->previous = list;
+  entry->next     = list->next;
+
+  list->next->previous = entry;
+  list->next           = entry;
+}
+
+/*
+ * alt_llist_remove() is called to remove an element from a linked list. The
+ * input argument is the element to remove.
+ */
+     
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry)
+{
+  entry->next->previous = entry->previous;
+  entry->previous->next = entry->next;
+
+  /* 
+   * Set the entry to point to itself, so that any further calls to
+   * alt_llist_remove() are harmless.
+   */
+
+  entry->previous = entry;
+  entry->next     = entry;
+} 
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif /* __ALT_LLIST_H__ */ 
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h
new file mode 100644
index 0000000..e4c4c46
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_load.h
@@ -0,0 +1,78 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2005 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "alt_types.h"
+
+/*
+ * This macro is used to load code/data from its load address to its 
+ * execution address for a given section. The section name is the input
+ * argument. Note that a leading '.' is assumed in the name. For example
+ * to load the section .onchip_ram, use:
+ * 
+ * ALT_LOAD_SECTION_BY_NAME(onchip_ram);
+ * 
+ * This requires that the apropriate linker symbols have been generated
+ * for the section in question. This will be the case if you are using the
+ * default linker script.
+ */ 
+
+#define ALT_LOAD_SECTION_BY_NAME(name)                         \
+  {                                                            \
+    extern void _alt_partition_##name##_start;                 \
+    extern void _alt_partition_##name##_end;                   \
+    extern void _alt_partition_##name##_load_addr;             \
+                                                               \
+    alt_load_section(&_alt_partition_##name##_load_addr,       \
+                     &_alt_partition_##name##_start,           \
+                     &_alt_partition_##name##_end);            \
+  }
+
+/*
+ * Function used to load an individual section from flash to RAM.
+ *
+ * There is an implicit assumption here that the linker script will ensure
+ * that all sections are word aligned.
+ *
+ */
+
+static void ALT_INLINE alt_load_section (alt_u32* from, 
+                                         alt_u32* to, 
+                                         alt_u32* end)
+{
+  if (to != from)
+  {
+    while( to != end )
+    {
+      *to++ = *from++;
+    }
+  }
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h
new file mode 100644
index 0000000..1536d8f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_log_printf.h
@@ -0,0 +1,354 @@
+/*  alt_log_printf.h
+ *
+ *  ALT_LOG is designed to provide extra logging/debugging messages from HAL
+ *  through a different port than stdout.  It is enabled by the ALT_LOG_ENABLE
+ *  define, which needs to supplied at compile time.  When logging is turned off, 
+ *  code size is unaffected.  Thus, this should be transparent to the user
+ *  when it is not actively turned on, and should not affect projects in any way.
+ *
+ *  There are macros sprinkled within different components, such as the jtag uart 
+ *  and timer, in the HAL code.  They are always named ALT_LOG_<name>, and can be
+ *  safely ignored if ALT_LOG is turned off. 
+ *
+ *  To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and
+ *  ALT_LOG_PORT_BASE must be set in system.h.  This is done through editing 
+ *  <project>.ptf, by editing the alt_log_port_type & alt_log_port_base settings.
+ *  See the documentation html file for examples.
+ *
+ *  When it is turned on, it will output extra HAL messages to a port specified
+ *  in system.h.  This can be a UART or JTAG UART port.  By default it will 
+ *  output boot messages, detailing every step of the boot process.  
+ *
+ *  Extra logging is designed to be enabled by flags, which are defined in 
+ *  alt_log_printf.c.  The default value is that all flags are off, so only the
+ *  boot up logging messages show up.  ALT_LOG_FLAGS can be set to enable certain
+ *  groupings of flags, and that grouping is done in this file.  Each flag can 
+ *  also be overridden with a -D at compile time.
+ *
+ *  This header file includes the necessary prototypes for using the alt_log
+ *  functions.  It also contains all the macros that are used to remove the code
+ *  from alt log is turned off.  Also, the macros in other HAL files are defined 
+ *  here at the bottom.  These macros all call some C function that is in 
+ *  alt_log_printf.c.
+ *
+ *  The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly
+ *  (ALT_LOG_PUTS).  This was needed because the assembly printing occurs before
+ *  the device is initialized.  The assembly function corrupts register R4-R7, 
+ *  which are not used in the normal boot process.  For this reason, do not call
+ *  the assembly function in C.
+ *
+ *  author: gkwan 
+ */
+
+
+#ifndef __ALT_LOG_PRINTF_H__
+#define __ALT_LOG_PRINTF_H__
+
+#include <system.h>
+
+/* Global switch to turn on logging functions */
+#ifdef ALT_LOG_ENABLE
+
+    /* ALT_LOG_PORT_TYPE values as defined in system.h.  They are defined as
+     * numbers here first becasue the C preprocessor does not handle string
+     * comparisons.  */
+    #define ALTERA_AVALON_JTAG_UART 1
+    #define ALTERA_AVALON_UART 0
+
+    /* If this .h file is included by an assembly file, skip over include files
+     * that won't compile in assembly. */
+    #ifndef ALT_ASM_SRC
+        #include <stdarg.h>
+        #include "sys/alt_alarm.h"
+        #include "sys/alt_dev.h"
+        #ifdef __ALTERA_AVALON_JTAG_UART 
+            #include "altera_avalon_jtag_uart.h"
+        #endif
+    #endif /* ALT_ASM_SRC */
+
+    /* These are included for the port register offsets and masks, needed
+     * to write to the port.  Only include if the port type is set correctly,
+     * otherwise error.  If alt_log is turned on and the port to output to is
+     * incorrect or does not exist, then should exit. */
+    #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART 
+        #ifdef __ALTERA_AVALON_JTAG_UART
+            #include <altera_avalon_jtag_uart_regs.h>
+        #else
+            #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. 
+        #endif
+    #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART 
+        #ifdef __ALTERA_AVALON_UART
+            #include <altera_avalon_uart_regs.h>
+        #else
+            #error ALT_LOG: UART Port chosen, but no UART in system.
+        #endif
+    #else
+        #error ALT_LOG: alt_log_port_type declaration invalid!
+    #endif
+
+    /* ALT_LOG_ENABLE turns on the basic printing function */
+    #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0)
+ 
+    /* Assembly macro for printing in assembly, calls tx_log_str
+     * which is in alt_log_macro.S.
+     * If alt_log_boot_on_flag is 0, skips the printing */
+    #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \
+         addi r4, r4, %lo(alt_log_boot_on_flag) ; \
+         ldwio r5, 0(r4) ; \
+         beq r0, r5, 0f ; \
+         movhi r4, %hiadj(str) ; \
+         addi r4, r4, %lo(str) ; \
+	 call tx_log_str ; \
+       0:
+    
+    /* These defines are here to faciliate the use of one output function 
+     * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending
+     * on the port type, the status register, read mask, and output register 
+     * are set to the appropriate value for the port.  */
+    #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART 
+      #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL
+      #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK
+      #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA
+      #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4)
+      #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4)
+    #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART 
+      #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS
+      #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK
+      #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA
+      #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4)
+      #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4)
+    #endif /* ALT_LOG_PORT */
+
+    /* Grouping of flags via ALT_LOG_FLAGS.  Each specific flag can be set via 
+     * -D at compile time, or else they'll be set to a default value according
+     * to ALT_LOG_FLAGS.  ALT_LOG_FLAGS = 0 or not set is the default, where 
+     * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they
+     * increase in intrusiveness to the program, and will affect performance.
+     *
+     * Flag Level 1 - turns on system clock and JTAG UART startup status
+     *            2 - turns on write echo and JTAG_UART alarm (periodic report)
+     *            3 - turns on JTAG UART ISR logging - will slow performance
+     *                significantly. 
+     *           -1 - All logging output is off, but if ALT_LOG_ENABLE is 
+     *                defined all logging function is built and code size 
+     *                remains constant 
+     *
+     * Flag settings - 1 = on, 0 = off. */
+
+    /* This flag turns on "boot" messages for printing.  This includes messages
+     * during crt0.S, then alt_main, and finally alt_exit. */
+    #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING
+        #if ALT_LOG_FLAGS == 1
+            #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */
+            #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1
+        #endif
+    #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */
+
+    #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING
+        #if ALT_LOG_FLAGS == 1
+            #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */ 
+            #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0
+        #endif
+    #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */
+
+    #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING
+        #if ALT_LOG_FLAGS == 1
+            #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */
+            #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0
+        #endif
+    #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */
+
+    #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING
+        #ifndef __ALTERA_AVALON_JTAG_UART 
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 1
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0
+        #endif
+    #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */
+
+    #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING
+        #ifndef __ALTERA_AVALON_JTAG_UART 
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 1
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0
+        #endif
+    #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */
+
+    #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING
+        #ifndef __ALTERA_AVALON_JTAG_UART 
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 1
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 2
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0
+        #elif ALT_LOG_FLAGS == 3
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1
+        #elif ALT_LOG_FLAGS == -1 /* silent mode */
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0
+        #else /* default setting */
+            #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0
+        #endif
+    #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */
+
+#ifndef ALT_ASM_SRC
+    /* Function Prototypes */
+    void alt_log_txchar(int c,char *uartBase);
+    void alt_log_private_printf(const char *fmt,int base,va_list args);
+    void alt_log_repchar(char c,int r,int base);
+    int alt_log_printf_proc(const char *fmt, ... );
+    void alt_log_system_clock();
+    #ifdef __ALTERA_AVALON_JTAG_UART 
+        alt_u32 altera_avalon_jtag_uart_report_log(void * context);
+        void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base);
+        void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \
+             int base, const char* header);
+        void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev);
+    #endif
+    void alt_log_write(const void *ptr, size_t len);
+    
+    /* extern all global variables */
+    /* CASE:368514 - The boot message flag is linked into the sdata section
+     * because if it is zero, it would otherwise be placed in the bss section.
+     * alt_log examines this variable before the BSS is cleared in the boot-up
+     * process. 
+     */
+    extern volatile alt_u32 alt_log_boot_on_flag __attribute__ ((section (".sdata")));
+    extern volatile alt_u8 alt_log_write_on_flag;
+    extern volatile alt_u8 alt_log_sys_clk_on_flag;
+    extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag;
+    extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag;
+    extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag;
+    extern volatile int alt_log_sys_clk_count;
+    extern volatile int alt_system_clock_in_sec;
+    extern alt_alarm alt_log_jtag_uart_alarm_1;
+#endif  /* ALT_ASM_SRC */
+
+
+    /* Below are the MACRO defines used in various HAL files.  They check
+     * if their specific flag is turned on; if it is, then it executes its 
+     * code.
+     *
+     * To keep this file reasonable, most of these macros calls functions,
+     * which are defined in alt_log_printf.c.  Look there for implementation
+     * details. */
+  
+    /* Boot Messages Logging */
+    #define ALT_LOG_PRINT_BOOT(...) \
+       do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \
+          } while (0)
+
+    /* JTAG UART Logging */
+    /* number of ticks before alarm runs logging function */
+    #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR
+    	#define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10
+    #endif
+    #ifndef ALT_LOG_JTAG_UART_TICKS
+        #define ALT_LOG_JTAG_UART_TICKS \
+        	(alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR)
+    #endif
+  
+    /* if there's a JTAG UART defined, then enable these macros */
+    #ifdef __ALTERA_AVALON_JTAG_UART 
+
+        /* Macro in altera_avalon_jtag_uart.c, to register the alarm function.
+         * Also, the startup register info is also printed here, as this is
+         * called within the device driver initialization.  */
+        #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \
+            do { if (alt_log_jtag_uart_alarm_on_flag==1) { \
+                    alt_alarm_start(&alt_log_jtag_uart_alarm_1, \
+                    ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\
+                    dev);} \
+                 if (alt_log_jtag_uart_startup_info_on_flag==1) {\
+                    alt_log_jtag_uart_startup_info(dev, base);} \
+               } while (0)
+  
+        /* JTAG UART IRQ Logging (when buffer is empty) 
+         * Inserted in the ISR in altera_avalon_jtag_uart.c */
+        #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \
+            do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) 
+    /* else, define macros to nothing.  Or else the jtag_uart specific types
+     * will throw compiler errors */
+    #else
+        #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) 
+        #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) 
+    #endif
+
+    /* System clock logging
+     * How often (in seconds) the system clock logging prints.
+     * The default value is every 1 second */
+    #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER
+	#define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1
+    #endif
+    #ifndef ALT_LOG_SYS_CLK_INTERVAL
+	#define ALT_LOG_SYS_CLK_INTERVAL \
+	    (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER)
+    #endif
+
+    /* System clock logging - prints a message every interval (set above) 
+     * to show that the system clock is alive. 
+     * This macro is used in altera_avalon_timer_sc.c */
+    #define ALT_LOG_SYS_CLK_HEARTBEAT() \
+    	do { alt_log_system_clock(); } while (0)
+
+    /* alt_write_logging - echos a message every time write() is called,
+     * displays the first ALT_LOG_WRITE_ECHO_LEN characters.
+     * This macro is used in alt_write.c */
+    #ifndef ALT_LOG_WRITE_ECHO_LEN
+        #define ALT_LOG_WRITE_ECHO_LEN 15
+    #endif
+
+    #define ALT_LOG_WRITE_FUNCTION(ptr,len) \
+        do { alt_log_write(ptr,len); } while (0)
+
+#else /* ALT_LOG_ENABLE not defined */
+
+    /* logging is off, set all relevant macros to null */
+    #define ALT_LOG_PRINT_BOOT(...)
+    #define ALT_LOG_PRINTF(...)
+    #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) 
+    #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) 
+    #define ALT_LOG_SYS_CLK_HEARTBEAT()
+    #define ALT_LOG_PUTS(str) 
+    #define ALT_LOG_WRITE_FUNCTION(ptr,len) 
+
+#endif /* ALT_LOG_ENABLE */
+
+#endif /* __ALT_LOG_PRINTF_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h
new file mode 100644
index 0000000..a9372c5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_set_args.h
@@ -0,0 +1,71 @@
+#ifndef __ALT_SET_ARGS_H__
+#define __ALT_SET_ARGS_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The function alt_set_args() is provided in order to define the input 
+ * arguments to main(). If this function is not called before main() then the
+ * argument list passed to main() will be empty.
+ *
+ * It is expected that this function will only be used by the ihost/iclient
+ * utility.
+ */
+
+static inline void alt_set_args (int argc, char** argv, char** envp)
+{
+  extern int    alt_argc;
+  extern char** alt_argv;
+  extern char** alt_envp;
+
+  alt_argc = argc;
+  alt_argv = argv;
+  alt_envp = envp;
+}
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif /* __ALT_SET_ARGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h
new file mode 100644
index 0000000..b41da40
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sim.h
@@ -0,0 +1,91 @@
+#ifndef __ALT_SIM_H__
+#define __ALT_SIM_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2007      Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include "system.h"
+#include "alt_types.h"
+
+/* 
+ * Instructions that might mean something special to a simulator. 
+ * These have no special effect on real hardware (they are just nops).
+ */
+#define ALT_SIM_FAIL() \
+    do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0)
+
+#define ALT_SIM_PASS() \
+    do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0)
+
+#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \
+    do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0)
+
+/*
+ * Routine called on exit.
+ */
+static ALT_INLINE ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code)
+{
+  register int r2 asm ("r2") = exit_code;
+
+#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON))
+
+  register int r3 asm ("r3") = (1 << 2);
+
+#ifdef ALT_PROVIDE_GMON
+  extern unsigned int alt_gmon_data[];
+  register int r4 asm ("r4") = (int)alt_gmon_data;
+  r3 |= (1 << 4);
+#define ALT_GMON_DATA ,"r"(r4)
+#else
+#define ALT_GMON_DATA
+#endif /* ALT_PROVIDE_GMON */
+
+  if (r2) {
+    ALT_SIM_FAIL();
+  } else {
+    ALT_SIM_PASS();
+  }
+
+  __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */
+
+  __asm__ volatile ("break 2" : : "r"(r2), "r"(r3) ALT_GMON_DATA );
+
+#else /* !DEBUG_STUB */
+  if (r2) {
+    ALT_SIM_FAIL();
+  } else {
+    ALT_SIM_PASS();
+  }
+#endif /* DEBUG_STUB */
+}
+
+#define ALT_SIM_HALT(exit_code) \
+  alt_sim_halt(exit_code)
+
+#endif /* __ALT_SIM_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h
new file mode 100644
index 0000000..ebcad7a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stack.h
@@ -0,0 +1,126 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_STACK_H__
+#define __ALT_STACK_H__
+
+/*
+ * alt_stack.h is the nios2 specific implementation of functions used by the
+ * stack overflow code.
+ */
+
+#include "nios2.h"
+
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+extern char * alt_stack_limit_value;
+
+#ifdef ALT_EXCEPTION_STACK
+extern char __alt_exception_stack_pointer[];  /* set by the linker */
+#endif /* ALT_EXCEPTION_STACK */
+
+
+/*
+ * alt_stack_limit can be called to determine the current value of the stack
+ * limit register.
+ */
+
+static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void)
+{
+  char * limit;
+  NIOS2_READ_ET(limit);
+
+  return limit; 
+}
+
+/*
+ * alt_stack_pointer can be called to determine the current value of the stack
+ * pointer register.
+ */
+
+static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void)
+{
+  char * pointer;
+  NIOS2_READ_SP(pointer);
+
+  return pointer; 
+}
+
+
+#ifdef ALT_EXCEPTION_STACK
+
+/*
+ * alt_exception_stack_pointer returns the normal stack pointer from
+ * where it is stored on the exception stack (uppermost 4 bytes).  This
+ * is really only useful during exception processing, and is only
+ * available if a separate exception stack has been configured.
+ */
+
+static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void)
+{
+  return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32));
+}
+
+#endif /* ALT_EXCEPTION_STACK */
+
+
+/*
+ * alt_set_stack_limit can be called to update the current value of the stack
+ * limit register.
+ */
+
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit)
+{
+  alt_stack_limit_value = limit;
+  NIOS2_WRITE_ET(limit);
+}
+
+/*
+ * alt_report_stack_overflow reports that a stack overflow happened.
+ */
+
+static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void)
+{
+  NIOS2_REPORT_STACK_OVERFLOW();
+}
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_STACK_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h
new file mode 100644
index 0000000..a3d1f48
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_stdio.h
@@ -0,0 +1,66 @@
+#ifndef __ALT_STDIO_H__
+#define __ALT_STDIO_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * Definitions for ALT stdio routines.
+ */
+
+#include <stdarg.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int alt_getchar();
+int alt_putchar(int c);
+int alt_putstr(const char* str);
+void alt_printf(const char *fmt, ...);
+#ifdef ALT_SEMIHOSTING
+int alt_putcharbuf(int c);
+int alt_putstrbuf(const char* str);
+int alt_putbufflush();
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_STDIO_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h
new file mode 100644
index 0000000..3b18059
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_init.h
@@ -0,0 +1,62 @@
+#ifndef __ALT_SYS_INIT_H__
+#define __ALT_SYS_INIT_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The function alt_sys_init() is defined within the auto-generated file:
+ * alt_sys_init.c. This function calls the initilisation macros for all
+ * devices, file systems, and software components within the system.
+ *
+ * The list of initilisation macros to use is constructed using the PTF and
+ * STF files associated with the system.
+ */
+
+extern void alt_sys_init (void);
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif /* __ALT_SYS_INIT_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h
new file mode 100644
index 0000000..eea552d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_sys_wrappers.h
@@ -0,0 +1,100 @@
+#ifndef __ALT_SYS_WRAPPERS_H__
+#define __ALT_SYS_WRAPPERS_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file provides the prototypes for the HAL 'UNIX style functions. The
+ * names of these functions are defined in alt_syscall.h. THese are defined to
+ * be the standard names when running the standalone HAL, e.g. open(), close()
+ * etc., but the names may be redefined as a part of an operating system port
+ * in order to avoid name clashes.
+ */
+
+#include "os/alt_syscall.h"
+
+#include <unistd.h>
+#include <sys/times.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+extern int     ALT_CLOSE (int __fd);
+extern int     ALT_EXECVE (const char *__path, 
+                           char * const __argv[], 
+                           char * const __envp[]);
+extern void    ALT_EXIT (int __status);
+extern int     ALT_FSTAT (int file, struct stat *st);
+extern int     ALT_FCNTL (int file, int cmd, ...);
+extern pid_t   ALT_FORK (void);
+extern pid_t   ALT_GETPID (void);
+
+#if defined (__GNUC__) && __GNUC__ >= 4
+extern int     ALT_GETTIMEOFDAY (struct timeval  *ptimeval, 
+                                 void *ptimezone);
+#else
+extern int     ALT_GETTIMEOFDAY (struct timeval  *ptimeval, 
+                                 struct timezone *ptimezone);
+#endif
+
+extern int     ALT_IOCTL (int file, int req, void* arg);
+extern int     ALT_ISATTY (int file);
+extern int     ALT_KILL (int pid, int sig);
+extern int     ALT_LINK (const char *existing, const char *new);
+extern off_t   ALT_LSEEK (int file, off_t ptr, int dir);
+extern int     ALT_OPEN (const char* file, int flags, ...);
+extern int     ALT_READ (int file, void *ptr, size_t len);
+extern int     ALT_RENAME (char *existing, char *new);
+extern void*   ALT_SBRK (ptrdiff_t incr);
+extern int     ALT_SETTIMEOFDAY (const struct timeval  *t,
+                                 const struct timezone *tz);
+extern int     ALT_STAT (const char *file, struct stat *st);
+extern clock_t ALT_TIMES (struct tms *buf);
+extern int     ALT_UNLINK (const char *name);
+
+#if defined (__GNUC__) && __GNUC__ >= 4
+int ALT_USLEEP (useconds_t us);
+#else
+unsigned int   ALT_USLEEP (unsigned int us);
+#endif
+
+extern int     ALT_WAIT (int *status);
+extern int     ALT_WRITE (int file, const void *ptr, size_t len);
+
+
+extern char** ALT_ENVIRON;
+
+/*
+ *
+ */
+
+#endif /* __ALT_SYS_WRAPPERS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h
new file mode 100644
index 0000000..ec704ba
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_timestamp.h
@@ -0,0 +1,60 @@
+#ifndef __ALT_TIMESTAMP_H__
+#define __ALT_TIMESTAMP_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+#include "altera_avalon_timer.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+extern int alt_timestamp_start (void);
+
+extern alt_timestamp_type alt_timestamp (void);
+
+extern alt_u32 alt_timestamp_freq (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_TIMESTAMP_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h
new file mode 100644
index 0000000..01318bd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/alt_warning.h
@@ -0,0 +1,75 @@
+#ifndef __WARNING_H__
+#define __WARNING_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * alt_warning.h provides macro definitions that can be used to generate link 
+ * time warnings.
+ */ 
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The symbol "__alt_invalid" is used to force a link error. There should be 
+ * no corresponding implementation of this function.
+ */  
+
+extern void __alt_invalid (void);
+
+#define ALT_LINK_WARNING(symbol, msg)                                                      \
+  __asm__(".ifndef __evoke_link_warning_" #symbol                                          \
+          "\n\t .section .gnu.warning." #symbol                                            \
+          "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \
+          "\n .endif");
+
+/* A canned warning for sysdeps/stub functions.  */
+
+#define ALT_STUB_WARNING(name) \
+  ALT_LINK_WARNING (name, \
+    "warning: " #name " is not implemented and will always fail")
+
+#define ALT_OBSOLETE_FUNCTION_WARNING(name) \
+  ALT_LINK_WARNING (name, \
+    "warning: " #name " is a deprecated function")
+
+#define ALT_LINK_ERROR(msg) \
+  ALT_LINK_WARNING (__alt_invalid, msg); \
+  __alt_invalid()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WARNING_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h
new file mode 100644
index 0000000..453283b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/ioctl.h
@@ -0,0 +1,90 @@
+#ifndef __IOCTL_H__
+#define __IOCTL_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * The ioctl() system call be used to initiate a variety of control operations
+ * on a file descriptor. For the most part this simply translates to a call to
+ * the ioctl() function of the associated device driver (TIOCEXCL and
+ * TIOCNXCL are notable exceptions - see ioctl.c for details).
+ *
+ * The interpretation of the ioctl requests are therefore device specific.
+ *
+ * This function is equivalent to the standard Posix ioctl() call.
+ */
+
+extern int ioctl (int fd, int req, void* arg);
+
+/*
+ * list of ioctl calls handled by the system ioctl implementation.
+ */
+
+#define TIOCEXCL 0x740d /* exclusive use of the device */
+#define TIOCNXCL 0x740e /* allow multiple use of the device */
+
+/*
+ * ioctl calls which can be handled by device drivers.
+ */
+
+#define TIOCOUTQ 0x7472 /* get output queue size */
+#define TIOCMGET 0x741d /* get termios flags */
+#define TIOCMSET 0x741a /* set termios flags */
+
+/*
+ * ioctl calls specific to JTAG UART.
+ */
+
+#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */
+#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */
+
+/*
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __IOCTL_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h
new file mode 100644
index 0000000..d271387
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/inc/sys/termios.h
@@ -0,0 +1,181 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT.                       *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This is the termios.h file provided with newlib. The only modification has 
+ * been to the baud rate macro definitions, and an increase in the size of the
+ * termios structure to accomodate this.
+ */
+
+
+#ifndef _SYS_TERMIOS_H
+# define _SYS_TERMIOS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+# define _XCGETA (('x'<<8)|1)
+# define _XCSETA (('x'<<8)|2)
+# define _XCSETAW (('x'<<8)|3)
+# define _XCSETAF (('x'<<8)|4)
+# define _TCSBRK (('T'<<8)|5)
+# define _TCFLSH (('T'<<8)|7)
+# define _TCXONC (('T'<<8)|6)
+
+# define TCOOFF 0
+# define TCOON  1
+# define TCIOFF 2
+# define TCION  3
+
+# define TCIFLUSH 0
+# define TCOFLUSH 1
+# define TCIOFLUSH  2
+
+# define NCCS 13
+
+# define TCSAFLUSH  _XCSETAF
+# define TCSANOW  _XCSETA
+# define TCSADRAIN  _XCSETAW
+# define TCSADFLUSH _XCSETAF
+
+# define IGNBRK 000001
+# define BRKINT 000002
+# define IGNPAR 000004
+# define INPCK  000020
+# define ISTRIP 000040
+# define INLCR  000100
+# define IGNCR  000200
+# define ICRNL  000400
+# define IXON 002000
+# define IXOFF  010000
+
+# define OPOST  000001
+# define OCRNL  000004
+# define ONLCR  000010
+# define ONOCR  000020
+# define TAB3 014000
+
+# define CLOCAL 004000
+# define CREAD  000200
+# define CSIZE  000060
+# define CS5  0
+# define CS6  020
+# define CS7  040
+# define CS8  060
+# define CSTOPB 000100
+# define HUPCL  002000
+# define PARENB 000400
+# define PAODD  001000
+
+#define CCTS_OFLOW 010000
+#define CRTS_IFLOW 020000
+#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW)
+
+# define ECHO 0000010
+# define ECHOE  0000020
+# define ECHOK  0000040
+# define ECHONL 0000100
+# define ICANON 0000002
+# define IEXTEN 0000400 /* anybody know *what* this does?! */
+# define ISIG 0000001
+# define NOFLSH 0000200
+# define TOSTOP 0001000
+
+# define VEOF 4 /* also VMIN -- thanks, AT&T */
+# define VEOL 5 /* also VTIME -- thanks again */
+# define VERASE 2
+# define VINTR  0
+# define VKILL  3
+# define VMIN 4 /* also VEOF */
+# define VQUIT  1
+# define VSUSP  10
+# define VTIME  5 /* also VEOL */
+# define VSTART 11
+# define VSTOP  12
+
+# define B0 0
+# define B50  50
+# define B75  75
+# define B110 110
+# define B134 134
+# define B150 150
+# define B200 200
+# define B300 300
+# define B600 600
+# define B1200  1200
+# define B1800  1800
+# define B2400  2400
+# define B4800  4800
+# define B9600  9600
+# define B19200 19200
+# define B38400 38400
+# define B57600 57600
+# define B115200 115200
+
+typedef unsigned char cc_t;
+typedef unsigned short tcflag_t;
+typedef unsigned long speed_t;
+
+struct termios {
+  tcflag_t  c_iflag;
+  tcflag_t  c_oflag;
+  tcflag_t  c_cflag;
+  tcflag_t  c_lflag;
+  char      c_line;
+  cc_t      c_cc[NCCS];
+  speed_t   c_ispeed;
+  speed_t   c_ospeed;
+};
+
+# ifndef _NO_MACROS
+
+#  define cfgetospeed(tp) ((tp)->c_ospeed)
+#  define cfgetispeed(tp) ((tp)->c_ispeed)
+#  define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0)
+#  define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0)
+#  define tcdrain(fd)   _ioctl (fd, _TCSBRK, 1)
+# endif /* _NO_MACROS */
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif  /* _SYS_TERMIOS_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c
new file mode 100644
index 0000000..2bd672f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_alarm_start.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <errno.h>
+
+#include "sys/alt_alarm.h"
+#include "sys/alt_irq.h"
+
+/*
+ * alt_alarm_start is called to register an alarm with the system. The 
+ * "alarm" structure passed as an input argument does not need to be 
+ * initialised by the user. This is done within this function.
+ *
+ * The remaining input arguments are:
+ *
+ * nticks - The time to elapse until the alarm executes. This is specified in
+ *          system clock ticks.
+ * callback - The function to run when the indicated time has elapsed.
+ * context  - An opaque value, passed to the callback function. 
+*
+ * Care should be taken when defining the callback function since it is 
+ * likely to execute in interrupt context. In particular, this mean that 
+ * library calls like printf() should not be made, since they can result in 
+ * deadlock.
+ *
+ * The interval to be used for the next callback is the return
+ * value from the callback function. A return value of zero indicates that the
+ * alarm should be unregistered. 
+ * 
+ * alt_alarm_start() will fail if  the timer facility has not been enabled 
+ * (i.e. there is no system clock). Failure is indicated by a negative return 
+ * value.
+ */ 
+
+int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks,
+                     alt_u32 (*callback) (void* context),
+                     void* context)
+{
+  alt_irq_context irq_context;
+  alt_u32 current_nticks = 0;
+  
+  if (alt_ticks_per_second ())
+  {
+    if (alarm)
+    {
+      alarm->callback = callback;
+      alarm->context  = context;
+ 
+      irq_context = alt_irq_disable_all ();
+      
+      current_nticks = alt_nticks();
+      
+      alarm->time = nticks + current_nticks + 1; 
+      
+      /* 
+       * If the desired alarm time causes a roll-over, set the rollover
+       * flag. This will prevent the subsequent tick event from causing
+       * an alarm too early.
+       */
+      if(alarm->time < current_nticks)
+      {
+        alarm->rollover = 1;
+      }
+      else
+      {
+        alarm->rollover = 0;
+      }
+    
+      alt_llist_insert (&alt_alarm_list, &alarm->llist);
+      alt_irq_enable_all (irq_context);
+
+      return 0;
+    }
+    else
+    {
+      return -EINVAL;
+    }
+  }
+  else
+  {
+    return -ENOTSUP;
+  }
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c
new file mode 100644
index 0000000..1b910a5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_busy_sleep.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA.  
+ * All rights reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
+ * deal in the Software without restriction, including without limitation the 
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is 
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * ------------
+ *
+ * Altera does not recommend, suggest or require that this reference design 
+ * file be used in conjunction or combination with any other product.
+ *
+ * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy
+ *                    loop to perform the delay. This is used to implement
+ *                    usleep for both uC/OS-II and the standalone HAL.  
+ *
+ * Author PRR
+ *
+ * Calibrated delay with no timer required
+ * 
+ * The ASM instructions in the routine are equivalent to 
+ *
+ * for (i=0;i<us*(ALT_CPU_FREQ/3);i++);
+ * 
+ * and takes three cycles each time around the loop
+ *
+ */
+
+#include <limits.h>
+#include <string.h>
+
+#include "system.h"
+#include "alt_types.h"
+
+#include "priv/alt_busy_sleep.h"
+
+unsigned int alt_busy_sleep (unsigned int us)
+{
+/*
+ * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software
+ * is built targetting ModelSim RTL simulation, the delay will be
+ * skipped to speed up simulation.
+ */
+#ifndef ALT_SIM_OPTIMIZE
+  int i;
+  int big_loops;
+  alt_u32 cycles_per_loop;
+  
+  if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny"))
+  {
+    cycles_per_loop = 9;
+  }
+  else  
+  {
+    cycles_per_loop = 3;
+  }
+  
+
+  big_loops = us / (INT_MAX/
+  (ALT_CPU_FREQ/(cycles_per_loop * 1000000)));
+
+  if (big_loops)
+  {
+    for(i=0;i<big_loops;i++)
+    {
+      /*
+      * Do NOT Try to single step the asm statement below 
+      * (single step will never return)
+      * Step out of this function or set a breakpoint after the asm statements
+      */
+      __asm__ volatile (
+        "\n0:"
+        "\n\taddi %0,%0, -1"
+        "\n\tbne %0,zero,0b"
+        "\n1:"
+        "\n\t.pushsection .debug_alt_sim_info"
+        "\n\t.int 4, 0, 0b, 1b"
+        "\n\t.popsection"
+        :: "r" (INT_MAX));
+      us -= (INT_MAX/(ALT_CPU_FREQ/
+      (cycles_per_loop * 1000000)));
+    }
+
+    /*
+    * Do NOT Try to single step the asm statement below 
+    * (single step will never return)
+    * Step out of this function or set a breakpoint after the asm statements
+    */
+    __asm__ volatile (
+      "\n0:"
+      "\n\taddi %0,%0, -1"
+      "\n\tbne %0,zero,0b"
+      "\n1:"
+      "\n\t.pushsection .debug_alt_sim_info"
+      "\n\t.int 4, 0, 0b, 1b"
+      "\n\t.popsection"
+      :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
+  }
+  else
+  {
+    /*
+    * Do NOT Try to single step the asm statement below 
+    * (single step will never return)
+    * Step out of this function or set a breakpoint after the asm statements
+    */
+    __asm__ volatile (
+      "\n0:"
+      "\n\taddi %0,%0, -1"
+      "\n\tbgt %0,zero,0b"
+      "\n1:"
+      "\n\t.pushsection .debug_alt_sim_info"
+      "\n\t.int 4, 0, 0b, 1b"
+      "\n\t.popsection"
+      :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
+  }
+#endif /* #ifndef ALT_SIM_OPTIMIZE */
+  return 0;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_close.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_close.c
new file mode 100644
index 0000000..f5d8e32
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_close.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <unistd.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+int ALT_CLOSE (int fildes)
+{
+  /* Generate a link time warning, should this function ever be called. */
+  
+  ALT_STUB_WARNING(close);
+  
+  /* Indicate an error */
+  
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+/*
+ * close() is called by an application to release a file descriptor. If the
+ * associated file system/device has a close() callback function registered 
+ * then this called. The file descriptor is then marked as free.
+ *
+ * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h
+ */
+ 
+int ALT_CLOSE (int fildes)
+{
+  alt_fd* fd;
+  int     rval;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (fildes < 0) ? NULL : &alt_fd_list[fildes];
+
+  if (fd)
+  {
+    /*
+     * If the associated file system/device has a close function, call it so 
+     * that any necessary cleanup code can run.
+     */
+
+    rval = (fd->dev->close) ? fd->dev->close(fd) : 0;
+
+    /* Free the file descriptor structure and return. */
+
+    alt_release_fd (fildes);
+    if (rval < 0)
+    {
+      ALT_ERRNO = -rval;
+      return -1;
+    }
+    return 0;
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    return -1;
+  }
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c
new file mode 100644
index 0000000..4326634
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "nios2.h"
+#include "system.h"
+
+#include "alt_types.h"
+#include "sys/alt_cache.h" 
+
+#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i));
+
+/*
+ * alt_dcache_flush() is called to flush the data cache for a memory
+ * region of length "len" bytes, starting at address "start".
+ *
+ * Any dirty lines in the data cache are written back to memory.
+ */
+
+void alt_dcache_flush (void* start, alt_u32 len)
+{
+#if NIOS2_DCACHE_SIZE > 0
+
+  char* i;
+  char* end = ((char*) start) + len; 
+
+  for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE)
+  { 
+    ALT_FLUSH_DATA(i); 
+  }
+
+  /* 
+   * For an unaligned flush request, we've got one more line left.
+   * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a 
+   * multiple of 2 (which it always is).
+   */
+
+  if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1))
+  {
+    ALT_FLUSH_DATA(i);
+  }
+
+#endif /* NIOS2_DCACHE_SIZE > 0 */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c
new file mode 100644
index 0000000..80735b7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_all.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "nios2.h"
+#include "system.h"
+
+#include "alt_types.h"
+#include "sys/alt_cache.h" 
+
+/*
+ * alt_dcache_flush_all() is called to flush the entire data cache.
+ */
+
+void alt_dcache_flush_all (void)
+{
+#if NIOS2_DCACHE_SIZE > 0
+  char* i;
+  
+  for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE)
+  { 
+    __asm__ volatile ("flushd (%0)" :: "r" (i));
+  }
+#endif /* NIOS2_DCACHE_SIZE > 0 */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c
new file mode 100644
index 0000000..76b1618
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dcache_flush_no_writeback.c
@@ -0,0 +1,69 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "nios2.h"
+#include "system.h"
+
+#include "alt_types.h"
+#include "sys/alt_cache.h" 
+
+#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \
+  __asm__ volatile ("initda (%0)" :: "r" (i));
+
+/*
+ * alt_dcache_flush_no_writeback() is called to flush the data cache for a
+ * memory region of length "len" bytes, starting at address "start".
+ *
+ * Any dirty lines in the data cache are NOT written back to memory.
+ * Make sure you really want this behavior.  If you aren't 100% sure,
+ * use the alt_dcache_flush() routine instead.
+ */
+
+void alt_dcache_flush_no_writeback (void* start, alt_u32 len)
+{
+  char* i;
+  char* end = ((char*) start) + len; 
+
+  for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE)
+  { 
+    ALT_FLUSH_DATA_NO_WRITEBACK(i); 
+  }
+
+  /* 
+   * For an unaligned flush request, we've got one more line left.
+   * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a 
+   * multiple of 2 (which it always is).
+   */
+
+  if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1))
+  {
+    ALT_FLUSH_DATA_NO_WRITEBACK(i);
+  }
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c
new file mode 100644
index 0000000..92f3f2a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev.c
@@ -0,0 +1,149 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+#include "alt_types.h"
+
+#include "system.h"
+
+/*
+ * This file contains the data constructs used to control access to device and
+ * filesytems.
+ */
+
+/*
+ * "alt_fs_list" is the head of a linked list of registered filesystems. It is 
+ * initialised as an empty list. New entries can be added using the 
+ * alt_fs_reg() function.  
+ */
+
+ALT_LLIST_HEAD(alt_fs_list);
+
+
+/*
+ * "alt_dev_list" is the head of a linked list of registered devices. It is
+ * configured at startup to include a single device, "alt_dev_null". This
+ * device is discussed below.
+ */
+
+extern alt_dev alt_dev_null; /* forward declaration */
+
+alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist};
+
+/*
+ * alt_dev_null_write() is the implementation of the write() function used
+ * by the alt_dev_null device. It simple discards all data passed to it, and
+ * indicates that the data has been successfully transmitted.
+ */
+
+static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len)
+{
+  return len;
+}
+
+/*
+ * "alt_dev_null" is used to allow output to be redirected to nowhere. It is
+ * the only device registered before the call to alt_sys_init(). At startup 
+ * stin, stdout & stderr are all directed towards this device so that library 
+ * calls like printf() will be safe but inefectual.  
+ */
+
+alt_dev alt_dev_null = {
+   {
+     &alt_dev_list,
+     &alt_dev_list
+   },
+   "/dev/null",
+   NULL,               /* open */
+   NULL,               /* close */
+   NULL,               /* write */
+   alt_dev_null_write, /* write */
+   NULL,               /* lseek */   
+   NULL,               /* fstat */ 
+   NULL                /* ioctl */
+ };
+
+/*
+ * "alt_fd_list_lock" is a semaphore used to control access to the file
+ * descriptor list. This is used to ensure that access to the list is thread
+ * safe.  
+ */
+
+ALT_SEM(alt_fd_list_lock)
+
+/*
+ * "alt_max_fd" is used to make access to the file descriptor list more 
+ * efficent. It is set to be the value of the highest allocated file 
+ * descriptor. This saves having to search the entire pool of unallocated
+ * file descriptors when looking for a match.
+ */
+
+alt_32 alt_max_fd = -1;
+
+/*
+ * "alt_fd_list" is the file descriptor pool. The first three entries in the
+ * array are configured as standard in, standard out, and standard error. These
+ * are all initialised so that accesses are directed to the alt_dev_null 
+ * device. The remaining file descriptors are initialised as unallocated.
+ *
+ * The maximum number of file descriptors within the system is specified by the
+ * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is 
+ * auto-genereated using the projects PTF and STF files.
+ */
+
+alt_fd alt_fd_list[ALT_MAX_FD] = 
+  {
+    {
+      &alt_dev_null, /* standard in */
+      0,
+      0
+    },
+    {
+      &alt_dev_null, /* standard out */
+      0,
+      0
+    },
+    {
+      &alt_dev_null, /* standard error */
+      0,
+      0
+    }
+    /* all other elements are set to zero */
+  };
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c
new file mode 100644
index 0000000..5e8a952
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dev_llist_insert.c
@@ -0,0 +1,59 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "priv/alt_dev_llist.h"
+#include "sys/alt_errno.h"
+
+/*
+ *
+ */
+
+int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list)
+{
+  /*
+   * check that the device exists, and that it has a valid name.
+   */
+
+  if (!dev || !dev->name)
+  {
+    ALT_ERRNO = EINVAL;
+    return -EINVAL;
+  }
+  
+  /*
+   * register the device.
+   */
+  
+  alt_llist_insert(list, &dev->llist);
+
+  return 0;  
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c
new file mode 100644
index 0000000..5d461d9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_rxchan_open.c
@@ -0,0 +1,63 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_dma.h"
+#include "sys/alt_errno.h"
+#include "priv/alt_file.h"
+
+/*
+ * The list of registered DMA receive channels.
+ */
+
+ALT_LLIST_HEAD(alt_dma_rxchan_list);
+
+/*
+ * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for
+ * a DMA transmit device. The name is the name of the associated physical
+ * device (e.g. "/dev/dma_0").
+ *
+ * The return value will be NULL on failure, and non-NULL otherwise. 
+ */
+
+alt_dma_rxchan alt_dma_rxchan_open (const char* name)
+{
+  alt_dma_rxchan dev;
+
+  dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list);
+
+  if (!dev)
+  {
+    ALT_ERRNO = ENODEV;
+  }
+
+  return dev;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c
new file mode 100644
index 0000000..99f9181
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_dma_txchan_open.c
@@ -0,0 +1,63 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_dma.h"
+#include "sys/alt_errno.h"
+#include "priv/alt_file.h"
+
+/*
+ * The list of registered receive channels.
+ */
+
+ALT_LLIST_HEAD(alt_dma_txchan_list);
+
+/*
+ * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for
+ * a DMA transmit device. The name is the name of the associated physical
+ * device (e.g. "/dev/dma_0").
+ *
+ * The return value will be NULL on failure, and non-NULL otherwise. 
+ */
+
+alt_dma_txchan alt_dma_txchan_open (const char* name)
+{
+  alt_dma_txchan dev;
+
+  dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list);
+
+  if (!dev)
+  {
+    ALT_ERRNO = ENODEV;
+  }
+
+  return dev;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c
new file mode 100644
index 0000000..be1c134
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_ctors.c
@@ -0,0 +1,64 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+* To provide your own implementation of a HAL function, include the file in   *
+* your Nios II IDE application project. When building the executable, the     *
+* Nios II IDE finds your function first, and uses it in place of the HAL      *
+* version.                                                                    *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * 
+ */
+
+typedef void (*constructor) (void);
+extern constructor __CTOR_LIST__[];
+extern constructor __CTOR_END__[];
+
+/*
+ * Run the C++ static constructors.
+ */
+
+void _do_ctors(void)
+{
+  constructor* ctor;
+
+  for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--)
+        (*ctor) (); 
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c
new file mode 100644
index 0000000..b61166a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_do_dtors.c
@@ -0,0 +1,64 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+* To provide your own implementation of a HAL function, include the file in   *
+* your Nios II IDE application project. When building the executable, the     *
+* Nios II IDE finds your function first, and uses it in place of the HAL      *
+* version.                                                                    *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * 
+ */
+
+typedef void (*destructor) (void);
+extern destructor __DTOR_LIST__[];
+extern destructor __DTOR_END__[];
+
+/*
+ * Run the C++ static destructors.
+ */
+
+void _do_dtors(void)
+{
+  destructor* dtor;
+
+  for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--)
+        (*dtor) (); 
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S
new file mode 100644
index 0000000..43fedc0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_entry.S
@@ -0,0 +1,102 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2013 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This is the code called at the beginning of the exception handler
+ * to detect a likely fatal ECC error exception and then jump to
+ * user-provided code to handle it.
+ *
+ * This code is pulled in from a .globl in alt_ecc_fatal_exception.c.
+ * This scheme is used so that if a handler is never registered, then this
+ * code will not appear in the generated executable, thereby improving 
+ * code footprint.
+ *
+ * This code is located in its own section that the linker script
+ * explicitly mentions and ensures it gets linked at the beginning
+ * of the exception handler.
+ */
+
+        /*
+         * Pull in the exception handler register save code.
+         */
+        .globl alt_exception
+
+        .section .exceptions.entry.ecc_fatal, "xa"
+
+        /*
+         * This might be handling an unrecoverable ECC error exception
+         * in the register file and/or data cache.
+         * Must avoid reading registers or performing load/store instructions
+         * before this is determined because they could trigger another 
+         * unrecoverable ECC error exception and create an infinite loop.
+         *
+         * The EXCEPTION register is always present when ECC is present.
+         * Bit 31 of this register indicates that there was an unrecoverable 
+         * ECC error exception in the register file and/or data cache.
+         * Test this (using blt to check sign bit) to determine if this is
+         * what we are dealing with.  Otherwise, just do normal processing.
+         *
+         * Jump to an application-provided routine to handle this condition.
+         * Pass in the return address in the et register in case this code
+         * can clean up the ECC error and then return here (unlikely).
+         *
+         * Runtime stack checking can't be enabled when ECC is present
+         * because they both want to use the et register.
+         */
+        rdctl et, exception
+        bge et, r0, alt_exception_not_ecc_fatal /* Not ECCFTL if bit 31 is 0 */
+
+        /*
+         * Load ECC fatal handler pointer into et register.
+         * Using a ldwio is safe because it completely bypasses the data cache.
+         */
+        movhi et, %hi(alt_exception_ecc_fatal_handler)
+        ori   et, et, %lo(alt_exception_ecc_fatal_handler) 
+        ldwio et, 0(et)
+ 
+        /* 
+         * If ECC fatal handler pointer is not 0, assume a handler
+         * has been provided by the application.
+         */
+        beq et, r0, alt_exception_not_ecc_fatal
+        
+        /*
+         * The et register contains the address of the ECC fatal handler.
+         * Jump to this address to invoke the handler.
+         */
+        jmp et
+
+        /*
+         * An ECC fatal handler can jump to this label if it able
+         * to recover from the fatal error (rare) and wants to continue
+         * with normal exception processing.
+         */
+.globl alt_exception_not_ecc_fatal
+alt_exception_not_ecc_fatal:
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c
new file mode 100644
index 0000000..9d40ff5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ecc_fatal_exception.c
@@ -0,0 +1,75 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2013 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+#include "io.h"
+#include "sys/alt_exceptions.h"
+#include "sys/alt_cache.h"
+
+/*
+ * This file implements support for calling a user-registered handler
+ * when a likely fatal ECC error exception occurs.
+ */
+
+/* 
+ * Global variable containing address to jump to when likely fatal
+ * ECC error exception occurs.
+ */
+alt_u32 alt_exception_ecc_fatal_handler = 0x0;
+
+/*
+ * Pull in the exception entry assembly code. This will not be linked in 
+ * unless this object is linked into the executable (i.e. only if 
+ * alt_ecc_fatal_exception_register() is called).
+ */
+__asm__( "\n\t.globl alt_exception" );
+
+/*
+ * alt_ecc_fatal_exception_register() is called to register a handler to
+ * service likely fatal ECC error exceptions. 
+ * 
+ * Passing null (0x0) in the handler argument will disable a previously-
+ * registered handler.
+ *
+ * Note that if no handler is registered, just normal exception processing
+ * occurs on a likely fatal ECC exception and the exception processing
+ * code might trigger an infinite exception loop.
+ */
+void 
+alt_ecc_fatal_exception_register(alt_u32 handler)
+{
+    alt_exception_ecc_fatal_handler = handler;
+
+    /* 
+     * Flush this from the cache. Required because the exception handler uses ldwio
+     * to read this value to avoid trigger another data cache ECC error exception.
+     */
+    alt_dcache_flush(&alt_exception_ecc_fatal_handler, sizeof(alt_exception_ecc_fatal_handler));
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c
new file mode 100644
index 0000000..780635a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_environ.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "os/alt_syscall.h"
+
+/*
+ * These are the environment variables passed to the C code. By default there 
+ * are no variables registered. An application can manipulate this list using
+ * getenv() and setenv().
+ */
+
+char *__env[1] = { 0 };
+char **ALT_ENVIRON = __env;
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c
new file mode 100644
index 0000000..4c5ca3e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_errno.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/*
+ * This file defines the alt_errno global variable. See comments in 
+ * alt_errno.h for the use of this variable.
+ */
+
+
+#include "sys/alt_errno.h"
+#include "alt_types.h"
+
+extern int ALT_WEAK *__errno (void);
+
+int* (*alt_errno) (void) = __errno;
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S
new file mode 100644
index 0000000..3740a0d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_entry.S
@@ -0,0 +1,402 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+
+/*
+ * This is the exception entry point code, which saves all the caller saved
+ * registers and then handles the appropriate exception.  It should be pulled
+ * in using a .globl from all the exception handler routines.  This scheme is
+ * used so that if an interrupt is never registered, then this code will not
+ * appear in the generated executable, thereby improving code footprint.
+ *
+ * If an external interrpt controller (EIC) is present, it will supply an 
+ * interrupt vector address to the processor when an interrupt occurs. For 
+ * The Altera Vectored Interrupt Controller (VIC) driver will establish a 
+ * vector table and the processor will jump directly to the appropriate 
+ * table entry, funnel routine, and then user ISR. This will bypass this code 
+ * in entirety. This code might still be linked into a system with an EIC, 
+ * but would then be used only for non-interrupt exceptions.
+ */
+
+        /*
+         * Explicitly allow the use of r1 (the assembler temporary register)
+         * within this code. This register is normally reserved for the use of
+         * the assembler.
+         */
+        .set noat
+
+        /*
+         * The top and bottom of the exception stack.
+         */
+#ifdef ALT_EXCEPTION_STACK
+        .globl __alt_exception_stack_pointer
+
+#ifdef ALT_STACK_CHECK
+        .globl __alt_exception_stack_limit
+
+        /*
+         * Store the value of the stack limit after interrupt somewhere.
+         */
+        .globl  alt_exception_old_stack_limit
+#endif /* ALT_STACK_CHECK */
+#endif /* ALT_EXCEPTION_STACK */
+
+/* 
+ * The code at alt_exception is located at the Nios II exception
+ * handler address.
+ */
+        .section .exceptions.entry.label, "xa"
+        .globl alt_exception
+        .type alt_exception, @function
+alt_exception:
+
+        /*
+         * The code for detecting a likely fatal ECC exception is
+         * linked here before the normal exception handler code if required.
+         * This is handled by the linker script and putting that code
+         * in the .exceptions.entry.ecc_fatal section.
+         */
+
+        /*
+         * Now start the normal exception handler code.
+         */
+        .section .exceptions.entry, "xa"
+
+#ifdef ALT_EXCEPTION_STACK
+#ifdef ALT_STACK_CHECK
+        /* 
+         * When runtime stack checking is enabled, the et register
+         * contains the stack limit. Save this in memory before
+         * overwriting the et register.
+         */
+        stw   et, %gprel(alt_exception_old_stack_limit)(gp)
+#endif /* ALT_STACK_CHECK */
+
+        /* 
+         * Switch to the exception stack and save the current stack pointer
+         * in memory. Uses the et register as a scratch register.
+         */
+        movhi et, %hi(__alt_exception_stack_pointer - 80)
+        ori   et, et, %lo(__alt_exception_stack_pointer - 80) 
+        stw   sp, 76(et)
+        mov   sp, et
+
+#ifdef ALT_STACK_CHECK
+        /*
+         * Restore the stack limit from memory to the et register.
+         */
+        movhi et, %hi(__alt_exception_stack_limit)
+        ori   et, et, %lo(__alt_exception_stack_limit) 
+        stw   et, %gprel(alt_stack_limit_value)(gp)
+#endif /* ALT_STACK_CHECK */
+
+#else /* ALT_EXCEPTION_STACK disabled */
+        /* 
+         * Reserve space on normal stack for registers about to be pushed.
+         */
+        addi  sp, sp, -76
+
+#ifdef ALT_STACK_CHECK
+        /* Ensure stack didn't just overflow. */
+        bltu  sp, et, .Lstack_overflow
+#endif /* ALT_STACK_CHECK */
+
+#endif /* ALT_EXCEPTION_STACK */
+
+        /* 
+         * Process an exception.  For all exceptions we must preserve all
+         * caller saved registers on the stack (See the Nios II ABI
+         * documentation for details).
+         *
+         * Leave a gap in the stack frame at 4(sp) for the muldiv handler to
+         * store zero into.
+         */
+        stw   ra,  0(sp)
+        stw   r1,   8(sp)
+        stw   r2,  12(sp)
+        stw   r3,  16(sp)
+        stw   r4,  20(sp)
+        stw   r5,  24(sp)
+        stw   r6,  28(sp)
+        stw   r7,  32(sp)
+        rdctl r5, estatus   /* Read early to avoid usage stall */
+        stw   r8,  36(sp)
+        stw   r9,  40(sp)
+        stw   r10, 44(sp)
+        stw   r11, 48(sp)
+        stw   r12, 52(sp)
+        stw   r13, 56(sp)
+        stw   r14, 60(sp)
+        stw   r15, 64(sp)
+
+        /*
+         * ea-4 contains the address of the instruction being executed
+         * when the exception occured. For interrupt exceptions, we will
+         * will be re-issue the isntruction. Store it in 72(sp)
+         */
+        stw   r5,  68(sp)  /* estatus */
+        addi  r15, ea, -4  /* instruction that caused exception */
+        stw   r15,  72(sp)
+
+        /*
+         * The interrupt testing code (.exceptions.irqtest) will be
+         * linked here. If the Internal Interrupt Controller (IIC) is
+         * present (an EIC is not present), the presense of an interrupt
+         * is determined by examining CPU control registers or an interrupt
+         * custom instruction, if present. 
+         * 
+         * If the IIC is used and an interrupt is active, the code linked 
+         * here will call the HAL IRQ handler (alt_irq_handler()) which 
+         * successively calls registered interrupt handler(s) until no 
+         * interrupts remain pending. It then jumps to .exceptions.exit. If 
+         * there is no interrupt then it continues to .exception.notirq, below.
+         */
+
+        .section .exceptions.notirq, "xa"
+
+        /*
+         * Prepare to service unimplemtned instructions or traps,
+         * each of which is optionally inked into section .exceptions.soft,
+         * which will preceed .exceptions.unknown below.
+         *
+         * Unlike interrupts, we want to skip the exception-causing instructon
+         * upon completion, so we write ea (address of instruction *after*
+         * the one where the exception occured) into 72(sp). The actual
+         * instruction that caused the exception is written in r2, which these
+         * handlers will utilize.
+         */
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
+
+#ifdef NIOS2_CDX_PRESENT
+        mov.n r4, ea            /* EA contains PC+4 of instruction that caused the exception */
+        subi.n r4, r4, 4        /* Calculate PC */
+        ldhu.n r2, 0(r4)        /* Load least-significant 16 bits of instruction */
+        andi r5, r2, 0x7        /* Mask off all bits except the 3 most-significant bits of OP field */
+
+        /*
+         * These instructions compare the MSB 3 bits of OP to 0x1, 0x3, and 0x5
+         * which is where all the 16-bit instructions live.
+         */
+        subi.n r5, r5, 1
+        beqz.n r5, .Lunknown_16bit
+        subi.n r5, r5, 2
+        beqz.n r5, .Lunknown_16bit
+        subi.n r5, r5, 2
+        beqz.n r5, .Lunknown_16bit
+
+.Lunknown_32bit:
+        stw ea, 72(sp) /* EA is PC+4 so will skip over instruction causing exception */
+
+        /* Load most-significant 16 bits of instruction */
+        ldhu.n r3, 2(r4)
+        slli.n r3, r3, 16
+        or.n r2, r2, r3 /* 32-bit instruction value that caused exception */
+        br.n .Lunknown_inst_loaded
+
+.Lunknown_16bit:
+        addi.n r4, r4, 2 /* Need PC+2 to skip over instruction causing exception */
+        stw r4, 72(sp)
+
+#else /* CDX is not Enabled and all instructions are 32bits */
+        ldw r2, -4(ea) /* Instruction value that caused exception */
+#endif
+
+.Lunknown_inst_loaded:
+
+        /*
+         * Other exception handling code, if enabled, will be linked here.
+         * This includes unimplemted (multiply/divide) instruction support
+         * (a BSP generaton option), and a trap handler (that would typically
+         * be augmented with user-specific code). These are not linked in by
+         * default.
+         */
+
+        /*
+         * In the context of linker sections, "unknown" are all exceptions
+         * not handled by the built-in handlers above (interupt, and trap or
+         * unimplemented instruction decoding, if enabled).
+         *
+         * Advanced exception types can be serviced by registering a handler.
+         * To do so, enable the "Enable Instruction-related Exception API" HAL
+         * BSP setting. If this setting is disabled, this handler code will
+         * either break (if the debug core is present) or enter an infinite
+         * loop because we don't how how to handle the exception.
+         */
+        .section .exceptions.unknown
+#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
+        /*
+         * The C-based HAL routine alt_instruction_exception_entry() will
+         * attempt to service the exception by calling a user-registered
+         * exception handler using alt_instruction_exception_register().
+         * If no handler was registered it will either break (if the
+         * debugger is present) or go into an infinite loop since the
+         * handling behavior is undefined; in that case we will not return here.
+         */
+
+        /* Load exception-causing address as first argument (r4) */
+        addi   r4, ea, -4
+
+        /* Call the instruction-exception entry */
+        call   alt_instruction_exception_entry
+
+        /*
+         * If alt_instruction_exception_entry() returned, the exception was
+         * serviced by a user-registered routine. Its return code (now in r2)
+         * indicates whether to re-issue or skip the exception-causing
+         * instruction
+         *
+         * Return code was 0: Skip. The instruction after the exception is
+         * already stored in 72(sp).
+         */
+        bne   r2, r0, .Lexception_exit
+
+        /*
+         * Otherwise, modify 72(sp) to re-issue the instruction that caused the
+         * exception.
+         */
+        addi  r15, ea, -4  /* instruction that caused exception */
+        stw   r15,  72(sp)
+
+#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */
+
+        /*
+         * We got here because an instruction-related exception occured, but the
+         * handler API was not compiled in. We do not presume to know how to
+         * handle it. If the debugger is present, break, otherwise hang.
+         *
+         *  If you get here then one of the following could have happened:
+         *
+         *  - An instruction-generated exception occured, and the processor
+         *    does not have the extra exceptions feature enabled, or you
+         *    have not registered a handler using
+         *    alt_instruction_exception_register()
+         *
+         *  Some examples of instruction-generated exceptions and why they
+         *  might occur:
+         *
+         *  - Your program could have been compiled for a full-featured
+         *    Nios II core, but it is running on a smaller core, and
+         *    instruction emulation has been disabled by defining
+         *    ALT_NO_INSTRUCTION_EMULATION.
+         *
+         *    You can work around the problem by re-enabling instruction
+         *    emulation, or you can figure out why your program is being
+         *    compiled for a system other than the one that it is running on.
+         *
+         *  - Your program has executed a trap instruction, but has not
+         *    implemented a handler for this instruction.
+         *
+         *  - Your program has executed an illegal instruction (one which is
+         *    not defined in the instruction set).
+         *
+         *  - Your processor includes an MMU or MPU, and you have enabled it
+         *    before registering an exception handler to service exceptions it
+         *    generates.
+         *
+         * The problem could also be hardware related:
+         *  - If your hardware is broken and is generating spurious interrupts
+         *    (a peripheral which negates its interrupt output before its
+         *    interrupt handler has been executed will cause spurious
+         *    interrupts)
+         */
+alt_exception_unknown:
+#ifdef NIOS2_HAS_DEBUG_STUB
+       /*
+        *  Either tell the user now (if there is a debugger attached) or go into
+        *  the debug monitor which will loop until a debugger is attached.
+        */
+        break
+#else /* NIOS2_HAS_DEBUG_STUB disabled */
+       /*
+        *  If there is no debug stub, an infinite loop is more useful.
+        */
+        br   alt_exception_unknown
+#endif /* NIOS2_HAS_DEBUG_STUB */
+#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
+
+        .section .exceptions.exit.label
+.Lexception_exit:
+
+        .section .exceptions.exit, "xa"
+
+        /* 
+         * Restore the saved registers, so that all general purpose registers 
+         * have been restored to their state at the time the interrupt occured.
+         */
+
+        ldw   r5,  68(sp)
+        ldw   ea,  72(sp)  /* This becomes the PC once eret is executed */
+        ldw   ra,   0(sp)
+
+        wrctl estatus, r5
+
+        ldw   r1,   8(sp)
+        ldw   r2,  12(sp)
+        ldw   r3,  16(sp)
+        ldw   r4,  20(sp)
+        ldw   r5,  24(sp)
+        ldw   r6,  28(sp)
+        ldw   r7,  32(sp)
+
+#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
+        ldw   et, %gprel(alt_exception_old_stack_limit)(gp)
+#endif
+
+        ldw   r8,  36(sp)
+        ldw   r9,  40(sp)
+        ldw   r10, 44(sp)
+        ldw   r11, 48(sp)
+        ldw   r12, 52(sp)
+        ldw   r13, 56(sp)
+        ldw   r14, 60(sp)
+        ldw   r15, 64(sp)
+
+#ifdef ALT_EXCEPTION_STACK
+#ifdef ALT_STACK_CHECK
+        stw   et, %gprel(alt_stack_limit_value)(gp)
+        stw   zero, %gprel(alt_exception_old_stack_limit)(gp)
+#endif /* ALT_STACK_CHECK */
+        ldw   sp,  76(sp)
+#else /* ALT_EXCEPTION_STACK disabled */
+        addi  sp, sp, 76
+#endif /* ALT_EXCEPTION_STACK */
+
+        /*
+         * Return to the interrupted instruction.
+         */
+
+        eret
+
+#ifdef ALT_STACK_CHECK
+.Lstack_overflow:
+        break 3
+#endif /* ALT_STACK_CHECK */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S
new file mode 100644
index 0000000..6a794a3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_muldiv.S
@@ -0,0 +1,583 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+        /*
+         * This is the software multiply/divide handler for Nios2.
+         */ 
+
+        /*
+         * Provide a label which can be used to pull this file in.
+         */
+
+        .section .exceptions.start
+        .globl alt_exception_muldiv
+alt_exception_muldiv:
+
+        /*
+         * Pull in the entry/exit code.
+         */
+        .globl alt_exception
+
+
+        .section .exceptions.soft, "xa"
+
+
+        /* INSTRUCTION EMULATION
+        *  ---------------------
+        *
+        * Nios II processors generate exceptions for unimplemented instructions.
+        * The routines below emulate these instructions.  Depending on the
+        * processor core, the only instructions that might need to be emulated
+        * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
+        *
+        * The emulations match the instructions, except for the following
+        * limitations:
+        *
+        * 1) The emulation routines do not emulate the use of the exception
+        *    temporary register (et) as a source operand because the exception
+        *    handler already has modified it.
+        *
+        * 2) The routines do not emulate the use of the stack pointer (sp) or the
+        *    exception return address register (ea) as a destination because
+        *    modifying these registers crashes the exception handler or the
+        *    interrupted routine.
+        *
+        * 3) To save code size, the routines do not emulate the use of the
+        *    breakpoint registers (ba and bt) as operands.
+        *
+        * Detailed Design
+        * ---------------
+        *
+        * The emulation routines expect the contents of integer registers r0-r31
+        * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp).  The
+        * routines retrieve source operands from the stack and modify the
+        * destination register's value on the stack prior to the end of the
+        * exception handler.  Then all registers except the destination register
+        * are restored to their previous values.
+        *
+        * The instruction that causes the exception is found at address -4(ea).
+        * The instruction's OP and OPX fields identify the operation to be
+        * performed.
+        *
+        * One instruction, muli, is an I-type instruction that is identified by
+        * an OP field of 0x24.
+        *
+        * muli   AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
+        *           27    22                6      0    <-- LSB of field
+        *
+        * The remaining emulated instructions are R-type and have an OP field
+        * of 0x3a.  Their OPX fields identify them.
+        *
+        * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
+        *           27    22    17     11     6      0  <-- LSB of field
+        * 
+        * 
+        */
+
+
+        /*
+         * Split the instruction into its fields.  We need 4*A, 4*B, and 4*C as
+         * offsets to the stack pointer for access to the stored register values.
+         */
+                             /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP    */
+        roli  r3, r2, 7      /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB   */
+        roli  r4, r3, 3      /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB    */
+        roli  r6, r4, 2      /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II   */
+        srai  r4, r4, 16     /* r4 = (sign-extended) IMM16                  */
+        xori  r6, r6, 0x42   /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */
+        roli  r7, r6, 5      /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */
+        andi  r5, r2, 0x3f   /* r5 = 00000000000000000000000000,PPPPPP      */
+        xori  r3, r3, 0x40
+        andi  r3, r3, 0x7c   /* r3 = 0000000000000000000000000,aAAAA,00     */
+        andi  r6, r6, 0x7c   /* r6 = 0000000000000000000000000,bBBBB,00     */
+        andi  r7, r7, 0x7c   /* r7 = 0000000000000000000000000,cCCCC,00     */
+
+        /* Now either
+         *  r5 = OP
+         *  r3 = 4*(A^16)
+         *  r4 = IMM16 (sign extended)
+         *  r6 = 4*(B^16)
+         *  r7 = 4*(C^16)
+         * or
+         *  r5 = OP
+         */
+
+
+        /*
+         * Save everything on the stack to make it easy for the emulation routines
+         * to retrieve the source register operands.  The exception entry code has
+         * already saved some of this so we don't need to do it all again.
+         */
+
+        addi  sp, sp, -60
+        stw   zero, 64(sp)   /* Save zero on stack to avoid special case for r0. */
+                             /* Register at and r2-r15 have already been saved.  */
+
+        stw   r16,  0(sp)
+        stw   r17,  4(sp)
+        stw   r18,  8(sp)
+        stw   r19, 12(sp)
+        stw   r20, 16(sp)
+        stw   r21, 20(sp)
+        stw   r22, 24(sp)
+        stw   r23, 28(sp)
+                            /* et @ 32 - Has already been changed.*/
+                            /* bt @ 36 - Usually isn't an operand.   */
+        stw   gp,  40(sp)
+        stw   sp,  44(sp)
+        stw   fp,  48(sp)
+                            /* ea @ 52 - Don't bother to save - it's already been changed */
+                            /* ba @ 56 - Breakpoint register usually isn't an operand */
+                            /* ra @ 60 - Has already been saved */
+
+
+        /*
+         *  Prepare for either multiplication or division loop.
+         *  They both loop 32 times.
+         */
+        movi   r14, 32
+
+
+        /*
+         * Get the operands.
+         *
+         * It is necessary to check for muli because it uses an I-type instruction
+         * format, while the other instructions are have an R-type format.
+         */
+        add    r3, r3, sp     /* r3 = address of A-operand. */
+        ldw    r3, 0(r3)      /* r3 = A-operand. */
+        movi   r15, 0x24      /* muli opcode (I-type instruction format) */
+        beq    r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */
+
+        add    r6, r6, sp     /* r6 = address of B-operand.               */
+        ldw    r6, 0(r6)      /* r6 = B-operand.                          */
+                              /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------   */
+                              /* IMM16 not needed, align OPX portion      */
+                              /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
+        srli   r4, r4, 5      /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
+        andi   r4, r4, 0x3f   /* r4 = 00000000000000000000000000,-OPX--   */
+
+        /* Now
+         * r5 = OP
+         * r3 = src1
+         * r6 = src2
+         * r4 = OPX (no longer can be muli)
+         * r7 = 4*(C^16)
+         * r14 = loop counter
+         */
+
+        /* ILLEGAL-INSTRUCTION EXCEPTION
+         *  -----------------------------
+         *
+         *  This code is for Nios II cores that generate exceptions when attempting
+         *  to execute illegal instructions.  Nios II cores that support an
+         *  illegal-instruction exception are identified by the presence of the
+         *  macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h .
+         *
+         *  Remember that illegal instructions are different than unimplemented
+         *  instructions.  Illegal instructions are instruction encodings that
+         *  have not been defined by the Nios II ISA.  Unimplemented instructions
+         *  are legal instructions that must be emulated by some Nios II cores.
+         *
+         *  If we get here, all instructions except multiplies and divides
+         *  are illegal.
+         *
+         *  This code assumes that OP is not muli (because muli was tested above).
+         *  All other multiplies and divides are legal.  Anything else is illegal.
+         */
+
+        movi  r8, 0x3a                        /* OP for R-type mul* and div* */
+        bne   r5, r8, .Lnot_muldiv
+
+        /* r15 already is 0x24 */            /* OPX of divu */
+        beq   r4, r15, .Ldivide
+
+        movi  r15,0x27                        /* OPX of mul */
+        beq   r4, r15, .Lmultiply
+
+        movi  r15,0x07                        /* OPX of mulxuu */
+        beq   r4, r15, .Lmultiply
+
+        movi  r15,0x17                        /* OPX of mulxsu */
+        beq   r4, r15, .Lmultiply
+
+        movi  r15,0x1f                        /* OPX of mulxss */
+        beq   r4, r15, .Lmultiply
+
+        movi  r15,0x25                        /* OPX of div */
+        bne   r4, r15, .Lnot_muldiv
+
+
+        /* DIVISION
+         *
+         * Divide an unsigned dividend by an unsigned divisor using
+         * a shift-and-subtract algorithm.  The example below shows
+         * 43 div 7 = 6 for 8-bit integers.  This classic algorithm uses a
+         * single register to store both the dividend and the quotient,
+         * allowing both values to be shifted with a single instruction.
+         *
+         *                               remainder dividend:quotient
+         *                               --------- -----------------
+         *   initialize                   00000000     00101011:
+         *   shift                        00000000     0101011:_
+         *   remainder >= divisor? no     00000000     0101011:0
+         *   shift                        00000000     101011:0_
+         *   remainder >= divisor? no     00000000     101011:00
+         *   shift                        00000001     01011:00_
+         *   remainder >= divisor? no     00000001     01011:000
+         *   shift                        00000010     1011:000_
+         *   remainder >= divisor? no     00000010     1011:0000
+         *   shift                        00000101     011:0000_
+         *   remainder >= divisor? no     00000101     011:00000
+         *   shift                        00001010     11:00000_
+         *   remainder >= divisor? yes    00001010     11:000001
+         *       remainder -= divisor   - 00000111
+         *                              ----------
+         *                                00000011     11:000001
+         *   shift                        00000111     1:000001_
+         *   remainder >= divisor? yes    00000111     1:0000011
+         *       remainder -= divisor   - 00000111
+         *                              ----------
+         *                                00000000     1:0000011
+         *   shift                        00000001     :0000011_
+         *   remainder >= divisor? no     00000001     :00000110
+         *
+         * The quotient is 00000110.
+         */
+
+.Ldivide:
+        /*
+         *  Prepare for division by assuming the result
+         *  is unsigned, and storing its "sign" as 0.
+         */
+        movi   r17, 0
+
+
+        /* Which division opcode? */
+        xori   r15, r4, 0x25         /* OPX of div */
+        bne    r15, zero, .Lunsigned_division
+
+
+        /*
+         *  OPX is div.  Determine and store the sign of the quotient.
+         *  Then take the absolute value of both operands.
+         */
+        xor   r17, r3, r6      /* MSB contains sign of quotient */
+        bge   r3, zero, 0f
+        sub   r3, zero, r3     /* -r3 */
+0:
+        bge   r6, zero, 0f
+        sub   r6, zero, r6     /* -r6 */
+0:
+
+
+.Lunsigned_division:
+        /* Initialize the unsigned-division loop. */
+        movi  r13, 0          /* remainder = 0 */
+
+        /* Now
+        * r3 = dividend : quotient
+        * r4 = 0x25 for div, 0x24 for divu
+        * r6 = divisor
+        * r13 = remainder
+        * r14 = loop counter (already initialized to 32)
+        * r17 = MSB contains sign of quotient
+        */
+
+
+        /*
+        *   for (count = 32; count > 0; --count)
+        *   {
+        */
+.Ldivide_loop:
+
+        /*
+        *       Division:
+        *
+        *       (remainder:dividend:quotient) <<= 1;
+        */
+        slli  r13, r13, 1
+        cmplt r15, r3, zero        /* r15 = MSB of r3 */
+        or    r13, r13, r15
+        slli  r3, r3, 1
+
+
+        /*
+        *       if (remainder >= divisor)
+        *       {
+        *           set LSB of quotient
+        *           remainder -= divisor;
+        *       }
+        */
+        bltu  r13, r6, .Ldiv_skip
+        ori   r3, r3, 1
+        sub   r13, r13, r6
+.Ldiv_skip:
+
+        /*
+        *   }
+        */
+        subi  r14, r14, 1
+        bne   r14, zero, .Ldivide_loop
+
+        mov   r9, r3
+
+
+        /* Now
+        * r9 = quotient
+        * r4 = 0x25 for div, 0x24 for divu
+        * r7 = 4*(C^16)
+        * r17 = MSB contains sign of quotient
+        */
+
+    
+        /*
+        *  Conditionally negate signed quotient.  If quotient is unsigned,
+        *  the sign already is initialized to 0.
+        */
+        bge   r17, zero, .Lstore_result
+        sub   r9, zero, r9     /* -r9 */
+
+        br    .Lstore_result
+
+
+
+
+        /* MULTIPLICATION
+        *
+        * A "product" is the number that one gets by summing a "multiplicand"
+        * several times.  The "multiplier" specifies the number of copies of the
+        * multiplicand that are summed.
+        *
+        * Actual multiplication algorithms don't use repeated addition, however.
+        * Shift-and-add algorithms get the same answer as repeated addition, and
+        * they are faster.  To compute the lower half of a product (pppp below)
+        * one shifts the product left before adding in each of the partial products
+        * (a * mmmm) through (d * mmmm).
+        *
+        * To compute the upper half of a product (PPPP below), one adds in the
+        * partial products (d * mmmm) through (a * mmmm), each time following the
+        * add by a right shift of the product.
+        *
+        *     mmmm
+        *   * abcd
+        *   ------
+        *     ####  = d * mmmm
+        *    ####   = c * mmmm
+        *   ####    = b * mmmm
+        *  ####     = a * mmmm
+        * --------
+        * PPPPpppp
+        *
+        * The example above shows 4 partial products.  Computing actual Nios II
+        * products requires 32 partials.
+        *
+        * It is possible to compute the result of mulxsu from the result of mulxuu
+        * because the only difference between the results of these two opcodes is
+        * the value of the partial product associated with the sign bit of rA.
+        *
+        *   mulxsu = mulxuu - ((rA < 0) ? rB : 0);
+        *
+        * It is possible to compute the result of mulxss from the result of mulxsu
+        * because the only difference between the results of these two opcodes is
+        * the value of the partial product associated with the sign bit of rB.
+        *
+        *   mulxss = mulxsu - ((rB < 0) ? rA : 0);
+        *
+        */
+
+.Lmul_immed:
+        /* Opcode is muli.  Change it into mul for remainder of algorithm. */
+        mov   r7, r6         /* Field B is dest register, not field C. */
+        mov   r6, r4         /* Field IMM16 is src2, not field B. */
+        movi  r4, 0x27       /* OPX of mul is 0x27 */
+
+.Lmultiply:
+        /* Initialize the multiplication loop. */
+        movi  r9, 0          /* mul_product    = 0 */
+        movi  r10, 0         /* mulxuu_product = 0 */
+        mov   r11, r6        /* save original multiplier for mulxsu and mulxss */
+        mov   r12, r6        /* mulxuu_multiplier (will be shifted) */
+        movi  r16, 1         /* used to create "rori B,A,1" from "ror B,A,r16" */
+
+        /* Now
+        * r3 = multiplicand
+        * r6 = mul_multiplier
+        * r7 = 4 * dest_register (used later as offset to sp)
+        * r9 = mul_product
+        * r10 = mulxuu_product
+        * r11 = original multiplier
+        * r12 = mulxuu_multiplier
+        * r14 = loop counter (already initialized)
+        * r15 = temp
+        * r16 = 1
+        */
+
+
+        /*
+        *   for (count = 32; count > 0; --count)
+        *   {
+        */
+.Lmultiply_loop:
+
+        /*
+        *       mul_product <<= 1;
+        *       lsb = multiplier & 1;
+        */
+        slli   r9, r9, 1
+        andi   r15, r12, 1
+
+        /*
+        *       if (lsb == 1)
+        *       {
+        *           mulxuu_product += multiplicand;
+        *       }
+        */
+        beq   r15, zero, .Lmulx_skip
+        add   r10, r10, r3
+        cmpltu r15, r10, r3  /* Save the carry from the MSB of mulxuu_product. */
+        ror   r15, r15, r16  /* r15 = 0x80000000 on carry, or else 0x00000000 */
+.Lmulx_skip:
+
+        /*
+        *       if (MSB of mul_multiplier == 1)
+        *       {
+        *           mul_product += multiplicand;
+        *       }
+        */
+        bge   r6, zero, .Lmul_skip
+        add   r9, r9, r3
+.Lmul_skip:
+
+        /*
+        *       mulxuu_product >>= 1;           logical shift
+        *       mul_multiplier <<= 1;           done with MSB
+        *       mulx_multiplier >>= 1;          done with LSB
+        */
+        srli   r10, r10, 1
+        or     r10, r10, r15           /* OR in the saved carry bit. */
+        slli   r6, r6, 1
+        srli   r12, r12, 1
+
+
+        /*
+        *   }
+        */
+        subi   r14, r14, 1
+        bne    r14, zero, .Lmultiply_loop
+
+
+        /*
+        *  Multiply emulation loop done.
+        */
+
+        /* Now
+        * r3 = multiplicand
+        * r4 = OPX
+        * r7 = 4 * dest_register (used later as offset to sp)
+        * r9 = mul_product
+        * r10 = mulxuu_product
+        * r11 = original multiplier
+        * r15 = temp
+        */
+
+
+        /*
+        *  Select/compute the result based on OPX.
+        */
+
+
+        /* OPX == mul?  Then store. */
+        xori  r15, r4, 0x27
+        beq   r15, zero, .Lstore_result
+
+        /* It's one of the mulx.. opcodes.  Move over the result. */
+        mov   r9, r10
+
+        /* OPX == mulxuu?  Then store. */
+        xori  r15, r4, 0x07
+        beq   r15, zero, .Lstore_result
+
+        /* Compute mulxsu
+         *
+         * mulxsu = mulxuu - ((rA < 0) ? rB : 0);
+         */
+        bge   r3, zero, .Lmulxsu_skip
+        sub   r9, r9, r11
+.Lmulxsu_skip:
+
+        /* OPX == mulxsu?  Then store. */
+        xori  r15, r4, 0x17
+        beq   r15, zero, .Lstore_result
+
+        /* Compute mulxss
+         *
+         * mulxss = mulxsu - ((rB < 0) ? rA : 0);
+         */
+        bge   r11, zero, .Lmulxss_skip
+        sub   r9, r9, r3
+.Lmulxss_skip:
+        /* At this point, assume that OPX is mulxss, so store */
+
+
+.Lstore_result:
+        add   r7, r7, sp
+        stw   r9, 0(r7)
+
+        ldw   r16,  0(sp)
+        ldw   r17,  4(sp)
+        ldw   r18,  8(sp)
+        ldw   r19, 12(sp)
+        ldw   r20, 16(sp)
+        ldw   r21, 20(sp)
+        ldw   r22, 24(sp)
+        ldw   r23, 28(sp)
+
+                            /* bt @ 32 - Breakpoint register usually isn't an operand. */
+                            /* et @ 36 - Don't corrupt et. */
+                            /* gp @ 40 - Don't corrupt gp. */
+                            /* sp @ 44 - Don't corrupt sp. */
+        ldw   fp,  48(sp)
+                            /* ea @ 52 - Don't corrupt ea. */
+                            /* ba @ 56 - Breakpoint register usually isn't an operand. */
+
+        addi  sp, sp, 60
+
+        br    .Lexception_exit
+
+
+.Lnot_muldiv:
+
+        addi  sp, sp, 60
+
+
+        .section .exceptions.exit.label
+.Lexception_exit:
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S
new file mode 100644
index 0000000..730e893
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exception_trap.S
@@ -0,0 +1,95 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+        /*
+         * This is the trap exception handler for Nios2.
+         */ 
+
+        /*
+         * Provide a label which can be used to pull this file in.
+         */
+
+        .section .exceptions.start
+        .globl alt_exception_trap
+alt_exception_trap:
+
+        /*
+         * Pull in the entry/exit code.
+         */
+        .globl alt_exception
+
+        .section .exceptions.soft, "xa"
+
+.Ltrap_handler:
+
+        /*
+         * Did a trap instruction cause the exception?
+         *
+         * The instruction which the exception occurred on has been loaded
+         * into r2 by code in alt_exception_entry.S
+         *
+         */
+
+#ifdef ALT_CPU_CPU_ARCH_NIOS2_R2
+        movhi r3,0xb41d              /* upper half of trap opcode */
+        ori   r3,r3,0x0020           /* lower half of trap opcode */
+        beq   r2,r3,.Lis_trap
+#ifdef NIOS2_CDX_PRESENT
+        mov   r3,r2
+        andhi r3,r3,0xffff
+        ori   r3,r3,0xd009           /* trap.n opcode */
+        beq   r2,r3,.Lis_trap
+#endif
+        br   .Lnot_trap
+#else
+        movhi r3,0x003b              /* upper half of trap opcode */
+        ori   r3,r3,0x683a           /* lower half of trap opcode */
+        bne   r2,r3,.Lnot_trap
+#endif
+
+.Lis_trap:
+        /*
+         *  There is no trap handler defined here, and so executing a trap
+         *  instruction causes a software break.  If you provide a trap handler,
+         *  then you must replace the break instruction below with your handler.
+         *  Your handler must preserve ea and the usual callee saved registers.
+         */
+
+        break
+
+        br   .Lexception_exit
+
+.Lnot_trap:
+
+
+        .section .exceptions.exit.label
+.Lexception_exit:
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c
new file mode 100644
index 0000000..51bfcc4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_execve.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "os/alt_syscall.h"
+
+/*
+ * execve() is used by newlib to launch new processes. This is unsupported in
+ * the HAL environment. However a "do-nothing" implementation is still 
+ * provied for newlib compatability.
+ *
+ * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h
+ */
+ 
+int ALT_EXECVE (char *name, char ** argv, char** env)
+{
+  /* Generate a link time warning, should this function ever be called. */
+
+  ALT_STUB_WARNING(execve);
+
+  /* Indicate an error */
+
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c
new file mode 100644
index 0000000..46cbe18
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_exit.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_irq.h"
+#include "sys/alt_sim.h"
+#include "os/alt_hooks.h"
+#include "os/alt_syscall.h"
+
+#include "alt_types.h"
+#include "sys/alt_log_printf.h"
+/*
+ * _exit() is called by exit() in order to terminate the current process. 
+ * Typically this is called when main() completes. It should never return. 
+ * Since there is nowhere to go once this process completes, this 
+ * implementation simply blocks forever.
+ *
+ * Note that interrupts are not disabled so that execution outside of this
+ * thread is allowed to continue. 
+ *
+ * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h
+ */
+
+void ALT_EXIT (int exit_code)
+{
+  /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n");
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code);
+  /* Stop all other threads */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n");
+  ALT_OS_STOP();
+
+  /* Provide notification to the simulator that we've stopped */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n");
+  ALT_SIM_HALT(exit_code);
+
+  /* spin forever, since there's no where to go back to */
+
+  ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n");
+  while (1);
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c
new file mode 100644
index 0000000..382fa43
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fcntl.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <unistd.h>
+#include <fcntl.h>
+
+#include <stdio.h>
+#include <stdarg.h>
+
+#include "sys/alt_errno.h"
+#include "priv/alt_file.h"
+#include "alt_types.h"
+#include "os/alt_syscall.h"
+
+#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK))
+
+/*
+ * fcntl() is a limited implementation of the standard fcntl() system call.
+ * It can be used to change the state of the flags associated with an open
+ * file descriptor. Normally these flags are set during the call to
+ * open(). It is anticipated that the main use of this function will be to
+ * change the state of a device from blocking to non-blocking (where this is
+ * supported). 
+ *
+ * The input argument "fd" is the file descriptor to be manipulated. "cmd"
+ * is the command to execute. This can be either F_GETFL (return the 
+ * current value of the flags) or F_SETFL (set the value of the flags).
+ *
+ * If "cmd" is F_SETFL then the argument "arg" is the new value of flags,
+ * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK
+ * can be updated by a call to fcntl(). All other flags remain
+ * unchanged.
+ *
+ * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h
+ */
+ 
+int ALT_FCNTL (int file, int cmd, ...)
+{ 
+  alt_fd*  fd;
+  long     flags;
+  va_list  argp;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+    switch (cmd)
+    {
+    case F_GETFL:
+      return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK);
+    case F_SETFL:
+      va_start(argp, cmd);
+      flags = va_arg(argp, long);
+      fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK;
+      fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK);
+      va_end(argp);
+      return 0;
+    default:
+      ALT_ERRNO = EINVAL;
+      return -1;
+    }
+  }
+
+  ALT_ERRNO = EBADFD;
+  return -1;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c
new file mode 100644
index 0000000..162295a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_lock.c
@@ -0,0 +1,75 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <errno.h>
+
+#include "priv/alt_file.h"
+
+/*
+ * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive
+ * access to a device, i.e.:
+ *
+ * ioctl (fd, TIOCEXCL, NULL);
+ *
+ * If there are no other open file descriptors which reference the same
+ * device, then alt_fd_lock() will grant the lock. Further calls to open() 
+ * for this device will fail until the lock is released.
+ *
+ * This is done by calling close() for this file descriptor, or by calling:
+ *
+ * ioctl (fd, TIOCNXCL, NULL);
+ *
+ * The return value is zero for success, or negative in the case of failure.
+ */
+
+int alt_fd_lock (alt_fd* fd)
+{
+  int i;
+  int rc = 0;
+
+  ALT_SEM_PEND(alt_fd_list_lock, 0);
+
+  for (i = 0; i < alt_max_fd; i++)
+  {
+    if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev))
+    {
+      rc = -EACCES;
+      goto alt_fd_lock_exit;
+    }
+  }
+  fd->fd_flags |= ALT_FD_EXCL;
+
+ alt_fd_lock_exit:
+
+  ALT_SEM_POST(alt_fd_list_lock);
+  return rc;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c
new file mode 100644
index 0000000..5f50386
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fd_unlock.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <errno.h>
+
+#include "priv/alt_file.h"
+
+/*
+ * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a 
+ * consequence of a TIOCNXCL ioctl request, e.g:
+ *
+ * ioctl (fd, TIOCNXCL, NULL);
+ *
+ * It enables multiple file descriptors to exist for the same device. This
+ * is normally the case, but it may have been disabled by a previous call to
+ * alt_fd_lock().
+ *
+ * Return zero on sucess, and a negative value on failure.
+ *
+ * The current implementation always succeeds.
+ */
+
+int alt_fd_unlock (alt_fd* fd)
+{
+  fd->fd_flags &= ~ALT_FD_EXCL;
+  return 0;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c
new file mode 100644
index 0000000..964f63f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_dev.c
@@ -0,0 +1,88 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+#include "alt_types.h"
+
+/* 
+ * alt_find_dev() is used by open() in order to locate a previously registered 
+ * device with the name "name". The input argument "llist" is a pointer to the
+ * head of the device list to search.
+ *
+ * The return value is a pointer to the matching device, or NULL if there is
+ * no match. 
+ *
+ * "name" must be an exact match for the devices registered name for a match to
+ * be found.
+ */
+ 
+alt_dev* alt_find_dev(const char* name, alt_llist* llist)
+{
+  alt_dev* next = (alt_dev*) llist->next;
+  alt_32 len;
+
+  len  = strlen(name) + 1;
+
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+
+  while (next != (alt_dev*) llist)
+  {
+
+    /* 
+     * memcmp() is used here rather than strcmp() in order to reduce the size
+     * of the executable.
+     */
+
+    if (!memcmp (next->name, name, len))
+    {
+      /* match found */
+
+      return next;
+    }
+    next = (alt_dev*) next->llist.next;
+  }
+  
+  /* No match found */
+  
+  return NULL;
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c
new file mode 100644
index 0000000..ae30e93
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_find_file.c
@@ -0,0 +1,89 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+#include "alt_types.h"
+
+/* 
+ * alt_find_file() is used by open() in order to locate a previously registered 
+ * filesystem that owns that mount point that contains the file named "name". 
+ *
+ * The return value is a pointer to the matching filesystem, or NULL if there is
+ * no match. 
+ *
+ * A match is considered to have been found if the filesystem name followed by
+ * either '/' or '\0' is the prefix of the filename. For example the filename:
+ * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". 
+ */
+ 
+alt_dev* alt_find_file (const char* name)
+{
+  alt_dev* next = (alt_dev*) alt_fs_list.next;   
+
+  alt_32 len;
+ 
+  /*
+   * Check each list entry in turn, until a match is found, or we reach the
+   * end of the list (i.e. next winds up pointing back to the list head).
+   */ 
+ 
+  while (next != (alt_dev*) &alt_fs_list)
+  {
+    len = strlen(next->name);
+    
+    if (next->name[len-1] == '/')
+    {
+      len -= 1;
+    }
+
+    if (((name[len] == '/') || (name[len] == '\0')) && 
+        !memcmp (next->name, name, len))
+    {
+      /* match found */
+
+      return next;
+    }
+    next = (alt_dev*) next->llist.next;
+  }
+  
+  /* No match found */
+  
+  return NULL;     
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c
new file mode 100644
index 0000000..0acffc7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_flash_dev.c
@@ -0,0 +1,69 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* Alt_flash.c - Functions to register a flash device to the "generic" flash   *
+*               interface                                                     *
+*                                                                             *
+* Author PRR                                                                  *
+*                                                                             *
+******************************************************************************/
+
+#include <errno.h>
+#include "sys/alt_llist.h"
+#include "sys/alt_flash_dev.h"
+#include "priv/alt_file.h"
+
+ALT_LLIST_HEAD(alt_flash_dev_list);
+
+alt_flash_fd* alt_flash_open_dev(const char* name)
+{
+  alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list);
+
+  if ((dev) && dev->open)
+  {
+    return dev->open(dev, name);
+  }
+
+  return dev;
+}
+
+void alt_flash_close_dev(alt_flash_fd* fd)
+{
+  if (fd && fd->close)
+  {
+    fd->close(fd);
+  }
+  return;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c
new file mode 100644
index 0000000..b6edbb5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fork.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_warning.h"
+#include "sys/alt_errno.h"
+#include "os/alt_syscall.h"
+
+/*
+ * The fork() system call is used by newlib to create a duplicate copy of the
+ * curent process.  This is unsupported in the HAL environment. However a 
+ * "do-nothing" implementation is still provied for newlib compatability.
+ *
+ * ALT_FORK is mapped onto the fork() system call in alt_syscall.h
+ */
+ 
+int ALT_FORK (void)
+{
+  /* Generate a link time warning, should this function ever be called. */
+
+  ALT_STUB_WARNING(fork);
+
+ /* Indicate an error */
+
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
+
+ 
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c
new file mode 100644
index 0000000..e88a340
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fs_reg.c
@@ -0,0 +1,75 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <errno.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+/*
+ * The alt_fs_reg() function is used to register a file system. Once registered 
+ * a device can be accessed using the standard posix calls: open(), read(), 
+ * write() etc.
+ *
+ * System behaviour is undefined in the event that a file system is registered 
+ * with a name that conflicts with an existing device or file system.
+ *
+ * alt_fs_reg() is not thread safe in the sense that there should be no other 
+ * thread using the file system list at the time that alt_dev_reg() is called. In
+ * practice this means that alt_fs_reg() should only be called while operating
+ * in a single threaded mode. The expectation is that it will only be called
+ * by the file system initilisation functions invoked by alt_sys_init(), which in 
+ * turn should only be called by the single threaded C startup code.   
+ *
+ * A return value of zero indicates success. A negative return value indicates
+ * failure. 
+ */
+ 
+int alt_fs_reg (alt_dev* dev)
+{
+  /*
+   * check that the device has a name.
+   */
+
+  if (!dev->name)
+  {
+    return -ENODEV;
+  }
+  
+  /*
+   * register the file system.
+   */
+
+  alt_llist_insert(&alt_fs_list, &dev->llist);
+
+  return 0;
+} 
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c
new file mode 100644
index 0000000..3248764
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_fstat.c
@@ -0,0 +1,128 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <sys/stat.h>
+
+#include "sys/alt_dev.h"
+#include "sys/alt_warning.h"
+#include "sys/alt_errno.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+/*
+ * The fstat() system call is used to obtain information about the capabilities
+ * of an open file descriptor. By default file descriptors are marked as 
+ * being character devices. If a device or file system wishes to advertise 
+ * alternative capabilities then they can register an fstat() function within
+ * their associated alt_dev structure. This will be called to fill in the
+ * entries in the imput "st" structure.
+ *
+ * This function is provided for compatability with newlib. 
+ *
+ * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h
+ */
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#include "system.h"
+
+/*
+ * Provide minimal version that just describes all file descriptors 
+ * as character devices for provided stdio devices.
+ */
+int ALT_FSTAT (int file, struct stat *st)
+{
+    switch (file) {
+#ifdef ALT_STDIN_PRESENT
+    case 0: /* stdin file descriptor */
+#endif /* ALT_STDIN_PRESENT */
+#ifdef ALT_STDOUT_PRESENT
+    case 1: /* stdout file descriptor */
+#endif /* ALT_STDOUT_PRESENT */
+#ifdef ALT_STDERR_PRESENT
+    case 2: /* stderr file descriptor */
+#endif /* ALT_STDERR_PRESENT */
+        st->st_mode = _IFCHR;
+        return 0;
+    default:
+        return -1;
+    }
+
+#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT)
+    /* Generate a link time warning, should this function ever be called. */
+    ALT_STUB_WARNING(fstat);
+#endif
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_FSTAT (int file, struct stat *st)
+{
+  alt_fd*  fd;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+    /* Call the drivers fstat() function to fill out the "st" structure. */
+
+    if (fd->dev->fstat)
+    {
+      return fd->dev->fstat(fd, st);
+    }
+
+    /* 
+     * If no function is provided, mark the fd as belonging to a character 
+     * device.
+     */
+ 
+    else
+    {
+      st->st_mode = _IFCHR;
+      return 0;
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    return -1;
+  }
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c
new file mode 100644
index 0000000..f42944b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_get_fd.c
@@ -0,0 +1,105 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <stdio.h>
+#include <errno.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+#include "alt_types.h"
+
+#include "system.h"
+
+/*
+ * alt_get_fd() is called to allocate a new file descriptor from the file
+ * descriptor pool. If a file descriptor is succesfully allocated, it is 
+ * configured to refer to device "dev".
+ *
+ * The return value is the index of the file descriptor structure (i.e. 
+ * the offset of the file descriptor within the file descriptor array). A
+ * negative value indicates failure.
+ */
+
+int alt_get_fd (alt_dev* dev)
+{
+  alt_32 i;
+  int rc = -EMFILE;
+  
+  /* 
+   * Take the alt_fd_list_lock semaphore in order to avoid races when 
+   * accessing the file descriptor pool.
+   */
+  
+  ALT_SEM_PEND(alt_fd_list_lock, 0);
+  
+  /* 
+   * Search through the list of file descriptors, and allocate the first
+   * free descriptor that's found. 
+   *
+   * If a free descriptor is found, then the value of "alt_max_fd" is 
+   * updated accordingly. "alt_max_fd" is a 'highwater mark' which 
+   * indicates the highest file descriptor ever allocated. This is used to
+   * improve efficency when searching the file descriptor list, and 
+   * therefore reduce contention on the alt_fd_list_lock semaphore. 
+   */
+
+  for (i = 0; i < ALT_MAX_FD; i++)
+  {
+    if (!alt_fd_list[i].dev)
+    {
+      alt_fd_list[i].dev = dev;
+      if (i > alt_max_fd)
+      {
+        alt_max_fd = i;
+      }
+      rc = i;
+      goto alt_get_fd_exit;
+    }
+  }
+
+ alt_get_fd_exit:
+
+  /*
+   * Release the alt_fd_list_lock semaphore now that we are done with the
+   * file descriptor pool.
+   */
+
+  ALT_SEM_POST(alt_fd_list_lock);
+
+  return rc;
+}
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c
new file mode 100644
index 0000000..fe5cb32
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getchar.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stdio.h>
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+#include "system.h"
+#include "sys/alt_driver.h"
+#include "sys/alt_stdio.h"
+#include "priv/alt_file.h"
+#include "unistd.h"
+#endif
+#ifdef ALT_SEMIHOSTING
+#include "sys/alt_stdio.h"
+#include "unistd.h"
+#endif
+/*
+ * Uses the ALT_DRIVER_READ() macro to call directly to driver if available.
+ * Otherwise, uses newlib provided getchar() routine.
+ */
+int 
+alt_getchar(void)
+{
+#ifdef ALT_SEMIHOSTING
+    char c;
+    read(STDIN_FILENO,&c,1);
+    return c;
+#else
+#ifdef ALT_USE_DIRECT_DRIVERS
+    ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV);
+    char c;
+
+    if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) {
+        return -1;
+    }
+    return c;
+#else
+    return getchar();
+#endif
+#endif
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c
new file mode 100644
index 0000000..b63ec33
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_getpid.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "os/alt_syscall.h"
+
+/*
+ * The getpid() system call is used by newlib to obtain the current process 
+ * id. Since there is only ever a single process in the HAL environment,
+ * this just returns a constant. 
+ *
+ * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h
+ */
+ 
+int ALT_GETPID (void)
+{
+  return 0;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c
new file mode 100644
index 0000000..46b12c2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gettod.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <sys/time.h>
+#include <sys/times.h>
+#include <errno.h>
+
+#include "sys/alt_alarm.h"
+#include "alt_types.h"
+#include "os/alt_syscall.h"
+
+/*
+ * Macro defining the number of micoseconds in a second.
+ */
+
+#define ALT_US (1000000)
+
+/*
+ * "alt_timezone" and "alt_resettime" are the values of the the reset time and
+ * time zone set through the last call to settimeofday(). By default they are
+ * zero initialised.
+ */
+
+struct timezone alt_timezone = {0, 0};
+struct timeval  alt_resettime = {0, 0};
+
+/*
+ * gettimeofday() can be called to obtain a time structure which indicates the
+ * current "wall clock" time. This is calculated using the elapsed number of
+ * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set
+ * through the last call to settimeofday().  
+ *
+ * Warning: if this function is called concurrently with a call to 
+ * settimeofday(), the value returned by gettimeofday() will be unreliable. 
+ *
+ * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in 
+ * alt_syscall.h
+ */
+ 
+
+#if defined (__GNUC__) && (__GNUC__ >= 4)
+int ALT_GETTIMEOFDAY (struct timeval  *ptimeval, void *ptimezone_vptr)
+{
+  struct timezone *ptimezone = (struct timezone*)ptimezone_vptr;
+#else
+int ALT_GETTIMEOFDAY (struct timeval  *ptimeval, struct timezone *ptimezone)
+{
+#endif
+  
+  alt_u32 nticks = alt_nticks (); 
+  alt_u32 tick_rate = alt_ticks_per_second ();
+
+  /* 
+   * Check to see if the system clock is running. This is indicated by a 
+   * non-zero system clock rate. If the system clock is not running, an error
+   * is generated and the contents of "ptimeval" and "ptimezone" are not
+   * updated.
+   */
+
+  if (tick_rate)
+  {
+    ptimeval->tv_sec  = alt_resettime.tv_sec  + nticks/tick_rate;
+    ptimeval->tv_usec = alt_resettime.tv_usec +
+     (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US);
+      
+    while(ptimeval->tv_usec < 0) {
+      if (ptimeval->tv_sec <= 0)
+      {
+          ptimeval->tv_sec = 0;
+          ptimeval->tv_usec = 0;
+          break;
+      }
+      else
+      {
+          ptimeval->tv_sec--;
+          ptimeval->tv_usec += ALT_US;
+      }
+    }
+    
+    while(ptimeval->tv_usec >= ALT_US) {
+      ptimeval->tv_sec++;
+      ptimeval->tv_usec -= ALT_US;
+    }
+      
+    if (ptimezone)
+    { 
+      ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest;
+      ptimezone->tz_dsttime     = alt_timezone.tz_dsttime;
+    }
+
+    return 0;
+  }
+
+  return -ENOTSUP;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c
new file mode 100644
index 0000000..fa1cb1d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_gmon.c
@@ -0,0 +1,272 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <assert.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "priv/nios2_gmon_data.h"
+
+#include "sys/alt_irq.h"
+#include "sys/alt_alarm.h"
+
+
+/* Macros */
+
+/* How large should the bins be which we use to generate the histogram */
+#define PCSAMPLE_BYTES_PER_BUCKET 32
+
+#define NIOS2_READ_EA(dest)  __asm__ ("mov %0, ea" : "=r" (dest))
+
+/* The compiler inserts calls to mcount() at the start of
+ * every function call. The structure mcount_fn_arc records t
+ * he return address of the function called (in from_pc)
+ * and the return address of the mcount function
+ * (in self_pc). The number of times this arc is executed is
+ * recorded in the field count.
+ */
+struct mcount_fn_arc
+{
+  struct mcount_fn_arc * next;
+  void * from_pc;
+  unsigned int count;
+};
+
+/* We need to maintain a list of pointers to the heads of each adjacency
+ * list so that we can find them when writing out the gmon.out file. Since
+ * we don't know at the start of program execution how many functions will
+ * be called we use a list structure to do this.
+ */
+struct mcount_fn_entry
+{
+  struct mcount_fn_entry * next;
+  void * self_pc;
+  struct mcount_fn_arc * arc_head;
+};
+
+/* function prototypes */
+
+void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function));
+
+static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function));
+static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function));
+static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function));
+
+/* global variables */
+
+/* stext and etext are defined in the linker script */
+extern char stext[];
+extern char etext[];
+
+/* Is the PC sampling stuff enabled yet? */
+static int pcsample_need_init = 1;
+
+#define HASH_BUCKETS 64 /* Must be a power of 2 */
+
+/* This points to the list of adjacency list pointers. */
+struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS];
+
+/* pointer to the in-memory buffer containing the histogram */
+static unsigned short* s_pcsamples = 0;
+
+/* the address of the start and end of text section */
+static const unsigned int s_low_pc  = (unsigned int)stext;
+static const unsigned int s_high_pc = (unsigned int)etext;
+
+/* the alarm structure to register for pc sampling */
+static alt_alarm s_nios2_pcsample_alarm;
+
+unsigned int alt_gmon_data[GMON_DATA_SIZE] =
+{
+  0x6e6f6d67, /* "gmon" */
+  GMON_DATA_SIZE,
+  0,
+  (unsigned int)stext,
+  (unsigned int)etext,
+  PCSAMPLE_BYTES_PER_BUCKET,
+  0,
+  (unsigned int)__mcount_fn_head,
+  (unsigned int)(__mcount_fn_head + HASH_BUCKETS)
+};
+
+/* This holds the current slab of memory we're allocating out of */
+static char * mcount_slab_ptr = 0;
+static int    mcount_slab_size = 0;
+
+#define MCOUNT_SLAB_INCREMENT 1020
+
+
+/*
+ * We can't use malloc to allocate memory because that's too complicated, and
+ * can't be called at interrupt time.  Use the lower level allocator instead
+ * because that's interrupt safe (and because we never free anything).
+ *
+ * For speed, we allocate a block of data at once.
+ */
+static __inline__ void * mcount_allocate(unsigned int size)
+{
+  void * data;
+
+  if (size > mcount_slab_size)
+  {
+    mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT);
+    mcount_slab_size = MCOUNT_SLAB_INCREMENT;
+  }
+
+  data = mcount_slab_ptr;
+  mcount_slab_ptr += size;
+  mcount_slab_size -= size;
+
+  return data;
+}
+
+
+/*
+ * Add the arc with the values of frompc and topc given to the graph.
+ * This function might be called at interrupt time so must be able to
+ * cope with reentrancy.
+ *
+ * The fast case, where we have already allocated a function arc, has been
+ * handled by the assmebler code.
+ */
+void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head)
+{
+  alt_irq_context context;
+  struct mcount_fn_arc * arc_entry;
+
+  /* Keep trying to start up the PC sampler until it is running.
+   * (It can't start until the timer is going).
+   */
+  if (pcsample_need_init)
+  {
+    pcsample_need_init = 0;
+    pcsample_need_init = nios2_pcsample_init();
+  }
+
+  /*
+   * We must disable interrupts around the allocation and the list update to
+   * prevent corruption if the instrumented function is re-entrant.
+   *
+   * It's safe for the code above to be stepping through the chain and be
+   * interrupted by this code modifying it - there is an edge case which will
+   * leave two copies of the same arc on the list (both with count=1), but
+   * this is dealt with on the host.
+   */
+  context = alt_irq_disable_all();
+
+  if (fn_entry == NULL)
+  {
+    /* Add it to the list of functions we must output later. */
+    fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry));
+
+    fn_entry->self_pc = self_pc;
+    fn_entry->arc_head = NULL;
+
+    fn_entry->next = *fn_head;
+    *fn_head = fn_entry;
+  }
+
+  /* We will need a new list entry - if there was a list entry before
+   * then the assembler code would have handled it. */
+  arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc));
+
+  arc_entry->from_pc = from_pc;
+  arc_entry->count = 1;
+
+  arc_entry->next = fn_entry->arc_head;
+  fn_entry->arc_head = arc_entry;
+
+  alt_irq_enable_all(context);
+}
+
+
+/*
+ * nios2_pcsample_init starts profiling.
+ * It is called the first time mcount is called, and on subsequent calls to
+ * mcount until it returns zero. It initializes the pc histogram and turns on
+ * timer driven pc sampling.
+ */
+static int nios2_pcsample_init(void)
+{
+  unsigned int pcsamples_size; 
+
+  /* We sample the PC every tick */
+  unsigned int prof_rate = alt_ticks_per_second();
+  if (prof_rate == 0)
+    return 1;
+
+  /* allocate the histogram buffer s_pcsamples */
+  pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET;
+  s_pcsamples    = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short));
+
+  if (s_pcsamples != 0)
+  {
+    /* initialize the buffer to zero */
+    memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short));
+
+    alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples;
+    alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate;
+
+    /* Sample every tick (it's cheap) */
+    alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0);
+  }
+
+  return 0;
+}
+
+
+/*
+ * Sample the PC value and store it in the histogram
+ */
+static alt_u32 nios2_pcsample(void* context)
+{
+  unsigned int pc=0;
+  unsigned int bucket;
+
+  /* read the exception return address - this will be
+   * inaccurate if there are nested interrupts but we
+   * assume that this is rare and the inaccuracy will
+   * not be great */
+  NIOS2_READ_EA(pc);
+
+  /*
+   * If we're within the profilable range then increment the relevant
+   * bucket in the histogram
+   */
+  if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0)
+  {
+    bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET;
+    s_pcsamples[bucket]++;
+  }
+
+  /* Sample every tick */
+  return 1;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c
new file mode 100644
index 0000000..1662991
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush.c
@@ -0,0 +1,84 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "nios2.h"
+#include "system.h"
+
+#include "alt_types.h"
+#include "sys/alt_cache.h" 
+
+/*
+ * alt_icache_flush() is called to flush the instruction cache for a memory
+ * region of length "len" bytes, starting at address "start".
+ */
+
+void alt_icache_flush (void* start, alt_u32 len)
+{
+#if NIOS2_ICACHE_SIZE > 0
+
+  char* i;
+  char* end;
+
+  /*
+   * This is the most we would ever need to flush.
+   */
+ 
+  if (len > NIOS2_ICACHE_SIZE)
+  {
+    len = NIOS2_ICACHE_SIZE;
+  }
+
+  end = ((char*) start) + len;
+
+  for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE)
+  { 
+    __asm__ volatile ("flushi %0" :: "r" (i)); 
+  }
+
+  /* 
+   * For an unaligned flush request, we've got one more line left.
+   * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a 
+   * multiple of 2 (which it always is).
+   */
+
+  if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1))
+  {
+    __asm__ volatile ("flushi %0" :: "r" (i));
+  }
+
+  /* 
+   * Having flushed the cache, flush any stale instructions in the 
+   * pipeline 
+   */
+
+  __asm__ volatile ("flushp");
+
+#endif /* NIOS2_ICACHE_SIZE > 0 */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c
new file mode 100644
index 0000000..dc40ea8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_icache_flush_all.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "nios2.h"
+#include "system.h"
+
+#include "alt_types.h"
+#include "sys/alt_cache.h" 
+
+/*
+ * alt_icache_flush_all() is called to flush the entire instruction cache.
+ */
+
+void alt_icache_flush_all (void)
+{
+#if NIOS2_ICACHE_SIZE > 0
+  alt_icache_flush (0, NIOS2_ICACHE_SIZE);
+#endif
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c
new file mode 100644
index 0000000..4821f25
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include "system.h"
+
+/*
+ * This file implements the HAL Enhanced interrupt API for Nios II processors
+ * with an internal interrupt controller (IIC). For most routines, this serves 
+ * as a wrapper layer over the legacy interrupt API (which must be used with 
+ * the IIC only). 
+ *
+ * Use of the enhanced API is recommended so that application and device
+ * drivers are compatible with a Nios II system configured with an external 
+ * interrupt controller (EIC), or IIC. This will afford maximum portability. 
+ *
+ * If an EIC is present, the EIC device driver must provide these routines, 
+ * because their operation will be specific to that EIC type. 
+ */
+#ifndef NIOS2_EIC_PRESENT
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+
+#include "sys/alt_irq.h"
+#include "priv/alt_iic_isr_register.h"
+#include "priv/alt_legacy_irq.h"
+                            
+/** @Function Description:  This function registers an interrupt handler. 
+  * If the function is succesful, then the requested interrupt will be enabled upon 
+  * return. Registering a NULL handler will disable the interrupt.
+  * @API Type:              External
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+    return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags);
+}  
+
+/** @Function Description:  This function enables a single interrupt.
+  * @API Type:              External
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq)
+{
+    return alt_irq_enable(irq);
+}
+
+/** @Function Description:  This function disables a single interrupt.
+  * @API Type:              External
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq)
+{
+    return alt_irq_disable(irq);
+}
+
+/** @Function Description:  This function to determine if corresponding
+  *                         interrupt is enabled.
+  * @API Type:              External
+  * @param ic_id            Ignored.
+  * @param irq              IRQ number
+  * @return                 Zero if corresponding interrupt is disabled and
+  *                         non-zero otherwise.
+  */
+alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq)
+{
+    alt_u32 irq_enabled;
+
+    NIOS2_READ_IENABLE(irq_enabled);
+
+    return (irq_enabled & (1 << irq)) ? 1: 0;
+}
+
+#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */
+#endif /* NIOS2_EIC_PRESENT */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c
new file mode 100644
index 0000000..2e6bf5b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_iic_isr_register.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009      Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+#include <errno.h>
+#include "system.h"
+
+/*
+ * Provides an interrupt registry mechanism for the any CPUs internal interrupt
+ * controller (IIC) when the enhanced interrupt API is active.
+ */
+#ifndef ALT_CPU_EIC_PRESENT
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+
+#include "alt_types.h"
+#include "sys/alt_irq.h"
+#include "priv/alt_iic_isr_register.h"
+
+/*
+ * The header, alt_irq_entry.h, contains the exception entry point, and is
+ * provided by the processor component. It is included here, so that the code
+ * will be added to the executable only if alt_irq_register() is present, i.e.
+ * if no interrupts are registered - there's no need to provide any 
+ * interrupt handling.
+ */
+
+#include "sys/alt_irq_entry.h"
+
+/*
+ * The header, alt_irq_table.h contains a table describing which function
+ * handles each interrupt.
+ */
+
+#include "priv/alt_irq_table.h"
+
+/** @Function Description:  This function registers an interrupt handler. 
+  * If the function is succesful, then the requested interrupt will be enabled
+  * upon return. Registering a NULL handler will disable the interrupt.
+  *
+  * @API Type:              External
+  * @param ic_id            Interrupt controller ID
+  * @param irq              IRQ ID number
+  * @param isr              Pointer to interrupt service routine
+  * @param isr_context      Opaque pointer passed to ISR
+  * @param flags            
+  * @return                 0 if successful, else error (-1)
+  */
+int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, 
+  void *isr_context, void *flags)
+{
+  int rc = -EINVAL;  
+  int id = irq;             /* IRQ interpreted as the interrupt ID. */
+  alt_irq_context status;
+
+  if (id < ALT_NIRQ)
+  {
+    /* 
+     * interrupts are disabled while the handler tables are updated to ensure
+     * that an interrupt doesn't occur while the tables are in an inconsistant
+     * state.
+     */
+
+    status = alt_irq_disable_all();
+
+    alt_irq[id].handler = isr;
+    alt_irq[id].context = isr_context;
+
+    rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
+
+    alt_irq_enable_all(status);
+  }
+
+  return rc; 
+}
+
+#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */
+#endif /* ALT_CPU_EIC_PRESENT */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c
new file mode 100644
index 0000000..b993811
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_entry.c
@@ -0,0 +1,206 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+#include "sys/alt_exceptions.h"
+#include "nios2.h"
+#include "alt_types.h"
+#include "system.h"
+
+/*
+ * This file implements support for calling user-registered handlers for
+ * instruction-generated exceptions. This handler could also be reached
+ * in the event of a spurious interrupt.
+ *
+ * The handler code is optionally enabled through the "Enable
+ * Instruction-related Exception API" HAL BSP setting, which will
+ * define the macro below.
+ */
+#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
+
+/* Function pointer to exception callback routine */
+alt_exception_result (*alt_instruction_exception_handler)
+  (alt_exception_cause, alt_u32, alt_u32) = 0x0;
+
+/* Link entry routine to .exceptions section */
+int alt_instruction_exception_entry (alt_u32 exception_pc)
+  __attribute__ ((section (".exceptions")));
+
+/*
+ * This is the entry point for instruction-generated exceptions handling.
+ * This routine will be called by alt_exceptions_entry.S, after it determines
+ * that an exception could not be handled by handlers that preceed that
+ * of instruction-generated exceptions (such as interrupts).
+ *
+ * For this to function properly, you must register an exception handler
+ * using alt_instruction_exception_register(). This routine will call
+ * that handler if it has been registered. Absent a handler, it will
+ * break break or hang as discussed below.
+ */
+int 
+alt_instruction_exception_entry (alt_u32 exception_pc)
+{
+  alt_u32 cause, badaddr;
+
+/*
+ * If the processor hardware has the optional EXCEPTIONS & BADADDR registers,
+ * read them and pass their content to the user handler. These are always
+ * present if the MMU or MPU is enabled, and optionally for other advanced
+ * exception types via the "Extra exceptions information" setting in the
+ * processor (hardware) configuration.
+ *
+ * If these registers are not present, the cause field will be set to
+ * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should
+ * check the validity of the cause argument before proceeding.
+ */
+#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO
+  /* Get exception cause & "badaddr" */
+  NIOS2_READ_EXCEPTION(cause);
+  cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >>
+              NIOS2_EXCEPTION_REG_CAUSE_OFST );
+
+  NIOS2_READ_BADADDR(badaddr);
+#else
+  cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT;
+  badaddr = 0;
+#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
+
+  if(alt_instruction_exception_handler) {
+    /*
+     * Call handler. Its return value indicates whether the exception-causing
+     * instruction should be re-issued. The code that called us,
+     * alt_eceptions_entry.S, will look at this value and adjust the ea
+     * register as necessary
+     */
+    return alt_instruction_exception_handler(cause, exception_pc, badaddr);
+  }
+  /*
+   * We got here because an instruction-generated exception occured, but no
+   * handler is present. We do not presume to know how to handle it. If the
+   * debugger is present, break, otherwise hang.
+   *
+   * If you've reached here in the debugger, consider examining the
+   * EXCEPTIONS register cause bit-field, which was read into the 'cause'
+   * variable above, and compare it against the exceptions-type enumeration
+   * in alt_exceptions.h. This register is availabe if the MMU or MPU is
+   * present, or if the "Extra exceptions information" hardware option is
+   * selected.
+   *
+   *  If you get here then one of the following could have happened:
+   *
+   *  - An instruction-generated exception occured, and the processor
+   *    does not have the extra exceptions feature enabled, or you
+   *    have not registered a handler using
+   *    alt_instruction_exception_register()
+   *
+   *  Some examples of instruction-generated exceptions and why they
+   *  might occur:
+   *
+   *  - Your program could have been compiled for a full-featured
+   *    Nios II core, but it is running on a smaller core, and
+   *    instruction emulation has been disabled by defining
+   *    ALT_NO_INSTRUCTION_EMULATION.
+   *
+   *    You can work around the problem by re-enabling instruction
+   *    emulation, or you can figure out why your program is being
+   *    compiled for a system other than the one that it is running on.
+   *
+   *  - Your program has executed a trap instruction, but has not
+   *    implemented a handler for this instruction.
+   *
+   *  - Your program has executed an illegal instruction (one which is
+   *    not defined in the instruction set).
+   *
+   *  - Your processor includes an MMU or MPU, and you have enabled it
+   *    before registering an exception handler to service exceptions it
+   *    generates.
+   *
+   * The problem could also be hardware related:
+   *  - If your hardware is broken and is generating spurious interrupts
+   *    (a peripheral which negates its interrupt output before its
+   *    interrupt handler has been executed will cause spurious interrupts)
+   */
+  else {
+#ifdef NIOS2_HAS_DEBUG_STUB
+    NIOS2_BREAK();
+#else
+    while(1)
+      ;
+#endif /* NIOS2_HAS_DEBUG_STUB */
+  }
+
+  /* We should not get here. Remove compiler warning. */
+  return NIOS2_EXCEPTION_RETURN_REISSUE_INST;
+}
+
+#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
+
+/*
+ * This routine indicates whether a particular exception cause will have
+ * set a valid address into the BADADDR register, which is included
+ * in the arguments to a user-registered instruction-generated exception
+ * handler. Many exception types do not set valid contents in BADADDR;
+ * this is a convenience routine to easily test the validity of that
+ * argument in your handler.
+ *
+ * Note that this routine will return false (0) for causes 
+ * NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR.
+ * You must read the TLBMISC.D field to determine if BADADDR
+ * is valid for these (valid if TLBMISC.D = 1).
+ *
+ * Arguments:
+ * cause:  The 5-bit exception cause field of the EXCEPTIONS register,
+ *         shifted to the LSB position. You may pass the 'cause' argument
+ *         in a handler you registered directy to this routine.
+ *
+ * Return: 1: BADADDR (bad_addr argument to handler) is valid
+ *         0: BADADDR is not valid
+ */
+int 
+alt_exception_cause_generated_bad_addr(alt_exception_cause cause)
+{
+  switch (cause) {
+  case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR:
+  case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR:
+  case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC:
+  case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION:
+  case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION:
+  case NIOS2_EXCEPTION_ECC_DATA_ERR:
+    return 1;
+
+  case NIOS2_EXCEPTION_TLB_MISS:
+  case NIOS2_EXCEPTION_ECC_TLB_ERR:
+    return 0;
+
+  default:
+    return 0;
+  }
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c
new file mode 100644
index 0000000..395c644
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_instruction_exception_register.c
@@ -0,0 +1,82 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2008 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+#include "sys/alt_exceptions.h"
+#include "alt_types.h"
+#include "system.h"
+
+/*
+ * This file implements support for calling user-registered handlers for
+ * instruction-generated exceptions.
+ *
+ * The registry API is optionally enabled through the "Enable
+ * Instruction-related Exception API" HAL BSP setting, which will
+ * define the macro below.
+ */
+#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
+
+/*
+ * The header, alt_exception_handler_registry.h contains a struct describing
+ * the registered exception handler
+ */
+#include "priv/alt_exception_handler_registry.h"
+
+/*
+ * Pull in the exception entry assembly code. This will not be linked in 
+ * unless this object is linked into the executable (i.e. only if 
+ * alt_instruction_exception_register() is called).
+ */
+__asm__( "\n\t.globl alt_exception" );
+
+/*
+ * alt_instruction_exception_register() is called to register a handler to
+ * service instruction-generated exceptions that are not handled by the
+ * default exception handler code (interrupts, and optionally unimplemented
+ * instructions and traps). 
+ * 
+ * Passing null (0x0) in the handler argument will disable a previously-
+ * registered handler.
+ *
+ * Note that if no handler is registered, exceptions that are not processed
+ * using the built-in handler (interrupts, and optionally unimplemented
+ * instructions and traps) are treated as unknown exceptions, resulting
+ * in either a break or an infinite loop.
+ */
+void alt_instruction_exception_register (
+  alt_exception_result (*exception_handler)(
+    alt_exception_cause cause,
+    alt_u32 exception_pc,
+    alt_u32 bad_addr) )
+{
+  alt_instruction_exception_handler = exception_handler;
+}
+
+#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c
new file mode 100644
index 0000000..049ed62
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_io_redirect.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+
+/*
+ * alt_open_fd() is similar to open() in that it is used to obtain a file
+ * descriptor for the file named "name". The "flags" and "mode" arguments are
+ * identical to the "flags" and "mode" arguments of open().
+ *
+ * The distinction between the two functions is that the file descriptor 
+ * structure to use is passed in as an argument, rather than allocated from the
+ * list of free file descriptors.
+ *
+ * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr
+ * file descriptors to point to new devices.
+ *
+ * If the device can not be succesfully opened, then the input file descriptor
+ * remains unchanged.
+ */
+
+static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode)
+{
+  int old;
+
+  old = open (name, flags, mode);
+
+  if (old >= 0)
+  {
+    fd->dev      = alt_fd_list[old].dev;
+    fd->priv     = alt_fd_list[old].priv;
+    fd->fd_flags = alt_fd_list[old].fd_flags;
+
+    alt_release_fd (old);
+  }
+} 
+
+/*
+ * alt_io_redirect() is called once the device/filesystem lists have been 
+ * initialised, but before main(). Its function is to redirect standard in,
+ * standard out and standard error so that they point to the devices selected by
+ * the user (as defined in system.h).
+ *
+ * Prior to the call to this function, io is directed towards /dev/null. If
+ * i/o can not be redirected to the requested device, for example if the device 
+ * does not exist, then it remains directed at /dev/null. 
+ */
+ 
+void alt_io_redirect(const char* stdout_dev, 
+                     const char* stdin_dev, 
+                     const char* stderr_dev)
+{
+  /* Redirect the channels */
+
+  alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777);
+  alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777);
+  alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777);
+}  
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c
new file mode 100644
index 0000000..510b40d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_ioctl.c
@@ -0,0 +1,170 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+
+#include "sys/ioctl.h"
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+/*
+ * The ioctl() system call is provided so that application code can manipulate 
+ * the i/o capabilities of a device in device specific ways. This is identical
+ * to the standard posix ioctl() function.
+ *
+ * In general this implementation simply vectors ioctl requests to the 
+ * apropriate drivers ioctl function (as registered in the drivers alt_dev
+ * structure).
+ *
+ * However in the case of devices (as oposed to filesystem), the TIOCEXCL and
+ * TIOCNXCL requests are handled without reference to the driver. These 
+ * requests are used to lock/release a device for exclusive access.
+ *
+ * Handling these requests centrally eases the task of device driver 
+ * development. 
+ *
+ * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h 
+ */
+ 
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#include "system.h"
+#include "sys/alt_driver.h"
+
+/*
+ * Provide minimal version that calls ioctl routine of provided stdio devices.
+ */
+int ALT_IOCTL (int file, int req, void* arg)
+{
+#ifdef ALT_STDIN_PRESENT
+    ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV);
+#endif
+#ifdef ALT_STDOUT_PRESENT
+    ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV);
+#endif
+#ifdef ALT_STDERR_PRESENT
+    ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV);
+#endif
+
+#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT)
+    /* Generate a link time warning, should this function ever be called. */
+    ALT_STUB_WARNING(ioctl);
+#endif
+
+    switch (file) {
+#ifdef ALT_STDIN_PRESENT
+    case 0: /* stdin file descriptor */
+        return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg);
+#endif /* ALT_STDIN_PRESENT */
+#ifdef ALT_STDOUT_PRESENT
+    case 1: /* stdout file descriptor */
+        return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg);
+#endif /* ALT_STDOUT_PRESENT */
+#ifdef ALT_STDERR_PRESENT
+    case 2: /* stderr file descriptor */
+        return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg);
+#endif /* ALT_STDERR_PRESENT */
+    default:
+        ALT_ERRNO = EBADFD;
+        return -1;
+    }
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_IOCTL (int file, int req, void* arg)
+{
+  alt_fd* fd;
+  int     rc;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+
+    /*
+     * In the case of device drivers (not file systems) handle the TIOCEXCL
+     * and TIOCNXCL requests as special cases.
+     */
+
+    if (fd->fd_flags & ALT_FD_DEV)
+    {
+      if (req == TIOCEXCL)
+      {
+        rc = alt_fd_lock (fd);
+        goto ioctl_done;
+      }
+      else if (req == TIOCNXCL)
+      {
+        rc = alt_fd_unlock (fd);
+        goto ioctl_done;
+      }
+    }
+
+    /*
+     * If the driver provides an ioctl() function, call that to handle the
+     * request, otherwise set the return code to indicate that the request
+     * could not be processed.
+     */
+   
+    if (fd->dev->ioctl)
+    {
+      rc = fd->dev->ioctl(fd, req, arg);
+    }
+    else
+    {
+      rc = -ENOTTY;
+    }
+  }
+  else  
+  {
+    rc = -EBADFD;
+  }
+
+ioctl_done:
+
+  if (rc < 0)
+  {
+    ALT_ERRNO = -rc;
+  }
+  return rc;
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S
new file mode 100644
index 0000000..8ee89e1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_entry.S
@@ -0,0 +1,108 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+
+/*
+ * This is the interrupt exception entry point code, which saves all the
+ * registers and calls the interrupt handler.  It should be pulled in using
+ * a .globl from alt_irq_register.c.  This scheme is used so that if an
+ * interrupt is never registered, then this code will not appear in the
+ * generated executable, thereby improving code footprint.
+ */
+
+        /*
+         * Explicitly allow the use of r1 (the assembler temporary register)
+         * within this code. This register is normally reserved for the use of
+         * the compiler.
+         */
+        .set noat
+
+        /*
+         * Pull in the exception handler register save code.
+         */
+        .globl alt_exception
+
+        .globl alt_irq_entry
+        .section .exceptions.entry.label, "xa"
+alt_irq_entry:
+
+        /*
+         * Section .exceptions.entry is in alt_exception_entry.S
+         * This saves all the caller saved registers and reads estatus into r5
+         */
+
+        .section .exceptions.irqtest, "xa"
+
+#ifdef ALT_CI_INTERRUPT_VECTOR_N
+        /*
+         * Use the interrupt vector custom instruction if present to accelerate
+         * this code.
+         * If the interrupt vector custom instruction returns a negative
+         * value, there are no interrupts active (estatus.pie is 0
+         * or ipending is 0) so assume it is a software exception.
+         */
+        custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0
+        blt r4, r0, .Lnot_irq
+#else
+        /*
+         * Test to see if the exception was a software exception or caused 
+         * by an external interrupt, and vector accordingly.
+         */
+        rdctl r4, ipending
+        andi  r2, r5, 1
+        beq   r2, zero, .Lnot_irq
+        beq   r4, zero, .Lnot_irq
+#endif /* ALT_CI_INTERRUPT_VECTOR_N */
+
+        .section .exceptions.irqhandler, "xa"
+        /*
+         * Now that all necessary registers have been preserved, call 
+         * alt_irq_handler() to process the interrupts.
+         */
+
+        call alt_irq_handler
+
+        .section .exceptions.irqreturn, "xa"
+
+        br    .Lexception_exit
+
+        .section .exceptions.notirq.label, "xa"
+
+.Lnot_irq:
+
+        /*
+         * Section .exceptions.exit is in alt_exception_entry.S
+         * This restores all the caller saved registers
+         */
+
+        .section .exceptions.exit.label
+.Lexception_exit:
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c
new file mode 100644
index 0000000..bb52fc8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_handler.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009      Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <errno.h>
+#include "system.h"
+
+/*
+ * This interrupt handler only works with an internal interrupt controller
+ * (IIC). Processors with an external interrupt controller (EIC) use an 
+ * implementation provided by an EIC driver.
+ */
+#ifndef ALT_CPU_EIC_PRESENT
+
+#include "sys/alt_irq.h"
+#include "os/alt_hooks.h"
+
+#include "alt_types.h"
+
+/*
+ * A table describing each interrupt handler. The index into the array is the
+ * interrupt id associated with the handler. 
+ *
+ * When an interrupt occurs, the associated handler is called with
+ * the argument stored in the context member.
+ */
+struct ALT_IRQ_HANDLER
+{
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  void (*handler)(void*);
+#else
+  void (*handler)(void*, alt_u32);
+#endif
+  void *context;
+} alt_irq[ALT_NIRQ];
+
+/*
+ * alt_irq_handler() is called by the interrupt exception handler in order to 
+ * process any outstanding interrupts. 
+ *
+ * It is defined here since it is linked in using weak linkage. 
+ * This means that if there is never a call to alt_irq_register() (above) then
+ * this function will not get linked in to the executable. This is acceptable
+ * since if no handler is ever registered, then an interrupt can never occur.
+ *
+ * If Nios II interrupt vector custom instruction exists, use it to accelerate
+ * the dispatch of interrupt handlers.  The Nios II interrupt vector custom 
+ * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined.
+ */
+
+void alt_irq_handler (void) __attribute__ ((section (".exceptions")));
+void alt_irq_handler (void)
+{
+#ifdef ALT_CI_INTERRUPT_VECTOR
+  alt_32 offset;
+  char*  alt_irq_base = (char*)alt_irq;
+#else
+  alt_u32 active;
+  alt_u32 mask;
+  alt_u32 i;
+#endif /* ALT_CI_INTERRUPT_VECTOR */
+  
+  /*
+   * Notify the operating system that we are at interrupt level.
+   */ 
+  
+  ALT_OS_INT_ENTER();
+
+#ifdef ALT_CI_INTERRUPT_VECTOR
+  /*
+   * Call the interrupt vector custom instruction using the 
+   * ALT_CI_INTERRUPT_VECTOR macro.
+   * It returns the offset into the vector table of the lowest-valued pending
+   * interrupt (corresponds to highest priority) or a negative value if none.
+   * The custom instruction assumes that each table entry is eight bytes.
+   */
+  while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) {
+    struct ALT_IRQ_HANDLER* handler_entry = 
+      (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset);
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+    handler_entry->handler(handler_entry->context);
+#else
+    handler_entry->handler(handler_entry->context, offset >> 3);
+#endif
+  }
+#else /* ALT_CI_INTERRUPT_VECTOR */
+  /* 
+   * Obtain from the interrupt controller a bit list of pending interrupts,
+   * and then process the highest priority interrupt. This process loops, 
+   * loading the active interrupt list on each pass until alt_irq_pending() 
+   * return zero.
+   * 
+   * The maximum interrupt latency for the highest priority interrupt is
+   * reduced by finding out which interrupts are pending as late as possible.
+   * Consider the case where the high priority interupt is asserted during
+   * the interrupt entry sequence for a lower priority interrupt to see why
+   * this is the case.
+   */
+
+  active = alt_irq_pending ();
+
+  do
+  {
+    i = 0;
+    mask = 1;
+
+    /*
+     * Test each bit in turn looking for an active interrupt. Once one is 
+     * found, the interrupt handler asigned by a call to alt_irq_register() is
+     * called to clear the interrupt condition.
+     */
+
+    do
+    {
+      if (active & mask)
+      { 
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+        alt_irq[i].handler(alt_irq[i].context); 
+#else
+        alt_irq[i].handler(alt_irq[i].context, i); 
+#endif
+        break;
+      }
+      mask <<= 1;
+      i++;
+
+    } while (1);
+
+    active = alt_irq_pending ();
+    
+  } while (active);
+#endif /* ALT_CI_INTERRUPT_VECTOR */
+
+  /*
+   * Notify the operating system that interrupt processing is complete.
+   */ 
+
+  ALT_OS_INT_EXIT();
+}
+
+#endif /* ALT_CPU_EIC_PRESENT */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c
new file mode 100644
index 0000000..cf7261e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_register.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009      Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+#include <errno.h>
+#include "system.h"
+
+/*
+ * This interrupt registry mechanism works with the Nios II internal interrupt 
+ * controller (IIC) only. Systems with an external interrupt controller (EIC),
+ * or those with the IIC who are using the enhanced interrupt API will
+ * utilize the alt_ic_isr_register() routine to register an interrupt. 
+ */
+#ifndef NIOS2_EIC_PRESENT
+
+#include "sys/alt_irq.h"
+#include "priv/alt_legacy_irq.h"
+#include "os/alt_hooks.h"
+
+#include "alt_types.h"
+
+/*
+ * The header, alt_irq_entry.h, contains the exception entry point, and is
+ * provided by the processor component. It is included here, so that the code
+ * will be added to the executable only if alt_irq_register() is present, i.e.
+ * if no interrupts are registered - there's no need to provide any 
+ * interrupt handling.
+ */
+
+#include "sys/alt_irq_entry.h"
+
+/*
+ * The header, alt_irq_table.h contains a table describing which function
+ * handles each interrupt.
+ */
+
+#include "priv/alt_irq_table.h"
+
+/*
+ * alt_irq_handler() is called to register an interrupt handler. If the 
+ * function is succesful, then the requested interrupt will be enabled upon 
+ * return. Registering a NULL handler will disable the interrupt.
+ *
+ * The return value is 0 if the interrupt handler was registered and the 
+ * interrupt was enabled, otherwise it is negative.
+ */
+ 
+int alt_irq_register (alt_u32 id, 
+                      void* context, 
+                      alt_isr_func handler)
+{
+  int rc = -EINVAL;  
+  alt_irq_context status;
+
+  if (id < ALT_NIRQ)
+  {
+    /* 
+     * interrupts are disabled while the handler tables are updated to ensure
+     * that an interrupt doesn't occur while the tables are in an inconsistant
+     * state.
+     */
+
+    status = alt_irq_disable_all ();
+
+    alt_irq[id].handler = handler;
+    alt_irq[id].context = context;
+
+    rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id);
+
+    alt_irq_enable_all(status);
+  }
+  return rc; 
+}
+#endif /* NIOS2_EIC_PRESENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c
new file mode 100644
index 0000000..4f4d140
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_irq_vars.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+
+#include "system.h"
+
+/*
+ * These global variables are used to save the current list of enabled 
+ * interrupts. See alt_irq.h for further details.
+ */
+
+volatile alt_u32 alt_irq_active    = 0;
+
+#ifndef ALT_EXCEPTION_STACK
+
+volatile alt_u32 alt_priority_mask = (alt_u32) -1;
+
+#endif
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c
new file mode 100644
index 0000000..73677dd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_isatty.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stddef.h>
+#include <sys/stat.h>
+
+#include "sys/alt_dev.h"
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#include "system.h"
+
+/*
+ * Provide minimal version that just describes all file descriptors 
+ * as tty devices for provided stdio devices.
+ */
+int ALT_ISATTY (int file)
+{
+    switch (file) {
+#ifdef ALT_STDIN_PRESENT
+    case 0: /* stdin file descriptor */
+#endif /* ALT_STDIN_PRESENT */
+#ifdef ALT_STDOUT_PRESENT
+    case 1: /* stdout file descriptor */
+#endif /* ALT_STDOUT_PRESENT */
+#ifdef ALT_STDERR_PRESENT
+    case 2: /* stderr file descriptor */
+#endif /* ALT_STDERR_PRESENT */
+        return 1;
+    default:
+        return 0;
+    }
+
+#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT)
+    /* Generate a link time warning, should this function ever be called. */
+    ALT_STUB_WARNING(isatty);
+#endif
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+/*
+ * isatty() can be used to determine whether the input file descriptor "file" 
+ * refers to a terminal device or not. If it is a terminal device then the
+ * return value is one, otherwise it is zero.  
+ *
+ * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h
+ */
+ 
+int ALT_ISATTY (int file)
+{
+  alt_fd*     fd;
+  struct stat stat;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+    /*
+     * If a device driver does not provide an fstat() function, then it is 
+     * treated as a terminal device by default.
+     */
+
+    if (!fd->dev->fstat)
+    {
+      return 1;
+    }
+
+    /*
+     * If a driver does provide an implementation of the fstat() function, then
+     * this is called so that the device can identify itself.
+     */ 
+
+    else
+    {
+      fstat (file, &stat);
+      return (stat.st_mode == _IFCHR) ? 1 : 0;
+    }
+  }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+    return 0;
+  }
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c
new file mode 100644
index 0000000..58097d1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_kill.c
@@ -0,0 +1,121 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <signal.h>
+#include <unistd.h>
+
+#include "sys/alt_errno.h"
+#include "os/alt_syscall.h"
+
+
+/*
+ * kill() is used by newlib in order to send signals to processes. Since there
+ * is only a single process in the HAL, the only valid values for pid are 
+ * either the current process id, or the broadcast values, i.e. pid must be
+ * less than or equal to zero. 
+ *
+ * ALT_KILL is mapped onto the kill() system call in alt_syscall.h
+ */
+
+int ALT_KILL (int pid, int sig)
+{
+  int status = 0;
+
+  if (pid <= 0)
+  {
+    switch (sig)
+    {
+    case 0:
+
+      /* The null signal is used to check that a pid is valid. */
+
+      break;
+
+    case SIGABRT:
+    case SIGALRM:
+    case SIGFPE:
+    case SIGILL:
+    case SIGKILL:
+    case SIGPIPE:
+    case SIGQUIT:
+    case SIGSEGV:
+    case SIGTERM:
+    case SIGUSR1:
+    case SIGUSR2:
+    case SIGBUS:
+    case SIGPOLL:
+    case SIGPROF:
+    case SIGSYS:
+    case SIGTRAP:
+    case SIGVTALRM:
+    case SIGXCPU:
+    case SIGXFSZ:
+
+      /* 
+       * The Posix standard defines the default behaviour for all these signals 
+       * as being eqivalent to a call to _exit(). No mechanism is provided to 
+       * change this behaviour.
+       */
+
+      _exit(0);
+    case SIGCHLD:
+    case SIGURG:
+
+      /* 
+       * The Posix standard defines these signals to be ignored by default. No 
+       * mechanism is provided to change this behaviour.
+       */
+
+      break;
+    default:
+
+      /* Tried to send an unsupported signal */
+
+      status = EINVAL;
+    }
+  }
+
+  else if (pid > 0)
+  {
+    /* Attempted to signal a non-existant process */
+
+    status = ESRCH;
+  }
+
+  if (status)
+  {
+    ALT_ERRNO = status;
+    return -1;
+  }
+
+  return 0;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c
new file mode 100644
index 0000000..a57a5c4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_link.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_warning.h"
+#include "sys/alt_errno.h"
+#include "os/alt_syscall.h"
+
+/*
+ * link() is used by newlib to create a new link to an existing file. This is 
+ * unsupported in the HAL environment. However a "do-nothing" implementation 
+ * is still provied for newlib compatability. 
+ *
+ * ALT_LINK is mapped onto the link() system call in alt_syscall.h
+ */
+ 
+int ALT_LINK ( char *existing, char *new)
+{
+  /* Generate a link time warning, should this function ever be called. */
+
+  ALT_STUB_WARNING(link);
+
+  /* Indicate an error */
+
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c
new file mode 100644
index 0000000..38d9618
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_load.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_load.h"
+#include "sys/alt_cache.h"
+
+/*
+ * Linker defined symbols.
+   These used to be
+ *    extern alt_u32 __flash_rwdata_start;
+ *    extern alt_u32 __ram_rwdata_start;
+ *    extern alt_u32 __ram_rwdata_end;
+ * but that results in a fatal error when compiling -mgpopt=global
+ * because gcc assumes they are normal C variables in .sdata
+ * and therefore addressable from gp using a 16-bit offset,
+ * when in fact they are special values defined by linker.x
+ * and located nowhere near .sdata. 
+ * Specifying __attribute__((section(".data"))) will force these
+ * in .data. (CASE:258384.)
+ */
+
+extern alt_u32 __flash_rwdata_start __attribute__((section(".data")));
+extern alt_u32 __ram_rwdata_start __attribute__((section(".data")));
+extern alt_u32 __ram_rwdata_end __attribute__((section(".data")));
+extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
+extern alt_u32 __ram_rodata_start __attribute__((section(".data")));
+extern alt_u32 __ram_rodata_end __attribute__((section(".data")));
+extern alt_u32 __flash_exceptions_start __attribute__((section(".data")));  
+extern alt_u32 __ram_exceptions_start __attribute__((section(".data")));
+extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
+
+/*
+ * alt_load() is called when the code is executing from flash. In this case
+ * there is no bootloader, so this application is responsible for loading to
+ * RAM any sections that are required.
+ */  
+
+void alt_load (void)
+{
+  /* 
+   * Copy the .rwdata section. 
+   */
+
+  alt_load_section (&__flash_rwdata_start, 
+		               &__ram_rwdata_start,
+		               &__ram_rwdata_end);
+
+  /*
+   * Copy the exception handler.
+   */
+
+  alt_load_section (&__flash_exceptions_start, 
+		                &__ram_exceptions_start,
+		                &__ram_exceptions_end);
+
+  /*
+   * Copy the .rodata section.
+   */
+
+  alt_load_section (&__flash_rodata_start, 
+		                &__ram_rodata_start,
+		                &__ram_rodata_end);
+  
+  /*
+   * Now ensure that the caches are in synch.
+   */
+  
+  alt_dcache_flush_all();
+  alt_icache_flush_all();
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S
new file mode 100644
index 0000000..d6b0a90
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_macro.S
@@ -0,0 +1,60 @@
+/*  alt_log_macro.S
+ *
+ *  Implements the function tx_log_str, called by the assembly macro 
+ *  ALT_LOG_PUTS().  The macro will be empty when logging is turned off,
+ *  and this function will not be compiled.  When logging is on,
+ *  this function is used to print out the strings defined in the beginning
+ *  of alt_log_printf.c, using port information taken from system.h and 
+ *  alt_log_printf.h.  
+ *
+ *  This routine only handles strings, and sends a character into the defined
+ *  output device's output buffer when the device is ready. It's intended for 
+ *  debugging purposes, where messages can be set to print out at certain 
+ *  points in the boot code to indicate the progress of the program.
+ *
+ */
+
+#ifndef __ALT_LOG_MACROS__
+#define __ALT_LOG_MACROS__
+
+/* define this flag to skip assembly-incompatible parts
+ * of various include files. */
+#define ALT_ASM_SRC
+
+#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. 
+	
+	#include "system.h"
+	#include "sys/alt_log_printf.h"
+
+        .global tx_log_str
+tx_log_str:
+	/* load base uart / jtag uart address into r6 */
+	movhi r6, %hiadj(ALT_LOG_PORT_BASE)
+	addi r6, r6, %lo(ALT_LOG_PORT_BASE)
+tx_next_char:
+        /* if pointer points to null, return 
+         * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */
+	ldb r7, (r4)
+	beq r0, r7, end_tx
+
+	/* check device transmit ready  */
+wait_tx_ready_loop:
+        ldwio   r8, ALT_LOG_PRINT_REG_OFFSET(r6)
+        /*UART, ALT_LOG_PRINT_MSK == 0x40
+          JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */
+        andhi   r5, r8, %hi(ALT_LOG_PRINT_MSK)
+        andi    r8, r8, %lo(ALT_LOG_PRINT_MSK)
+        or      r5, r5, r8
+        beq     r5, r0, wait_tx_ready_loop	
+	/* write char */
+	stwio   r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6)		
+	/* advance string pointer */
+	addi r4, r4, 1
+	br tx_next_char
+end_tx:	
+        ret
+    
+#endif
+
+#endif /* __ALT_LOG_MACROS__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c
new file mode 100644
index 0000000..7464185
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_log_printf.c
@@ -0,0 +1,479 @@
+
+/* alt_log_printf.c
+ *
+ * This file implements the various C functions used for the 
+ * alt_log logging/debugging print functions.  The functions
+ * sit as is here - the job of hiding them from the compiler
+ * if logging is disabled is accomplished in the .h file. 
+ *
+ * All the global variables for alt_log are defined here.  
+ * These include the various flags that turn on additional 
+ * logging options; the strings for assembly printing; and
+ * other globals needed by different logging options. 
+ *
+ * There are 4 functions that handle the actual printing: 
+ * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART.
+ * alt_log_repchar: Calls alt_log_txchar 'n' times - used by
+ *            alt_log_private_printf for formatting.
+ * alt_log_private_printf:
+ *     Stripped down implementation of printf - no floats.
+ * alt_log_printf_proc:
+ *     Wrapper function for private_printf.
+ * 
+ * The rest of the functions are called by the macros which
+ * were called by code in the other components.  Each function
+ * is preceded by a comment, about which file it gets called
+ * in, and what its purpose is.
+ *
+ * author: gkwan
+ */
+
+/* skip all code if enable is off */
+#ifdef ALT_LOG_ENABLE
+
+#include <system.h>
+#include <stdarg.h>
+#include <string.h>
+#ifdef __ALTERA_AVALON_JTAG_UART
+   #include "altera_avalon_jtag_uart.h"
+   #include <altera_avalon_jtag_uart_regs.h>
+#endif
+#include "sys/alt_log_printf.h"
+
+/* strings for assembly puts */
+char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";;
+char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n";
+char alt_log_msg_stackpointer[] \
+    = "[crt0.S] Setting up stack and global pointers.\r\n";
+char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n";
+/* char array allocation for alt_write */
+char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2];
+
+/* global variables for all 'on' flags */
+
+/* 
+ * CASE:368514 - The boot message flag is linked into the sdata section
+ * because if it is zero, it would otherwise be placed in the bss section.
+ * alt_log examines this variable before the BSS is cleared in the boot-up
+ * process.
+ */
+volatile alt_u32 alt_log_boot_on_flag \
+  __attribute__ ((section (".sdata"))) = ALT_LOG_BOOT_ON_FLAG_SETTING;
+
+volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING;
+
+volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING;
+
+volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \
+  ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING;
+
+volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \
+  ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING;
+
+volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \
+  ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING;
+
+/* Global alarm object for recurrent JTAG UART status printing */
+alt_alarm alt_log_jtag_uart_alarm_1;
+
+/* Global ints for system clock printing and count */
+volatile int alt_log_sys_clk_count;
+volatile int alt_system_clock_in_sec;
+
+/* enum used by alt_log_private_printf */
+enum
+{
+  pfState_chars,
+  pfState_firstFmtChar,
+  pfState_otherFmtChar
+};
+
+
+
+
+/* Function to put one char onto the UART/JTAG UART txdata register. */
+void alt_log_txchar(int c,char *base)
+{
+  /* Wait until the device is ready for a character */
+  while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0)
+    ;
+  /* And pop the character into the register */
+  ALT_LOG_PRINT_TXDATA_WR(base,c);
+}
+
+
+/* Called by alt_log_private_printf to print out characters repeatedly */
+void alt_log_repchar(char c,int r,int base)
+{
+  while(r-- > 0)
+    alt_log_txchar(c,(char*) base);
+}
+
+
+/* Stripped down printf function */
+void alt_log_private_printf(const char *fmt,int base,va_list args)
+  {
+  const char *w;
+  char c;
+  int state;
+  int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */
+  int fmtLong = 0;
+  int fmtBeforeDecimal = 0;
+  int fmtAfterDecimal = 0;
+  int fmtBase = 0;
+  int fmtSigned = 0;
+  int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */
+
+  w = fmt;
+  state = pfState_chars;
+
+  while(0 != (c = *w++))
+    {
+    switch(state)
+      {
+      case pfState_chars:
+        if(c == '%')
+        {
+          fmtLeadingZero = 0;
+          fmtLong = 0;
+          fmtBase = 10;
+          fmtSigned = 1;
+          fmtCase = 0; /* Only %X sets this. */
+          fmtBeforeDecimal = -1;
+          fmtAfterDecimal = -1;
+          state = pfState_firstFmtChar;
+        }
+        else
+        {
+          alt_log_txchar(c,(char*)base);
+        }
+        break;
+
+      case pfState_firstFmtChar:
+        if(c == '0')
+        {
+          fmtLeadingZero = 1;
+          state = pfState_otherFmtChar;
+        }
+        else if(c == '%')
+        {
+          alt_log_txchar(c,(char*)base);
+          state = pfState_chars;
+        }
+        else
+        {
+          state = pfState_otherFmtChar;
+          goto otherFmtChar;
+        }
+        break;
+
+      case pfState_otherFmtChar:
+otherFmtChar:
+        if(c == '.')
+        {
+          fmtAfterDecimal = 0;
+        }
+        else if('0' <= c && c <= '9')
+        {
+          c -= '0';
+          if(fmtAfterDecimal < 0)     /* still before decimal */
+          {
+            if(fmtBeforeDecimal < 0)
+            {
+              fmtBeforeDecimal = 0;
+            }
+            else
+            {
+              fmtBeforeDecimal *= 10;
+            }
+            fmtBeforeDecimal += c;
+          }
+          else
+          {
+            fmtAfterDecimal = (fmtAfterDecimal * 10) + c;
+          }
+        }
+        else if(c == 'l')
+        {
+          fmtLong = 1;
+        }
+        else                  /* we're up to the letter which determines type */
+        {
+          switch(c)
+          {
+            case 'd':
+            case 'i':
+doIntegerPrint:
+                {
+                unsigned long v;
+                unsigned long p;  /* biggest power of fmtBase */
+                unsigned long vShrink;  /* used to count digits */
+                int sign;
+                int digitCount;
+
+                /* Get the value */
+                if(fmtLong)
+                {
+                  if (fmtSigned)
+                  {
+                    v = va_arg(args,long);
+                  }
+                  else
+                  {
+                    v = va_arg(args,unsigned long);
+                  }
+                }
+                else
+                {
+                  if (fmtSigned)
+                  {
+                    v = va_arg(args,int);
+                  }
+                  else
+                  {
+                    v = va_arg(args,unsigned int);
+                  }
+                }
+
+                /* Strip sign */
+                sign = 0;
+                  /* (assumes sign bit is #31) */
+                if( fmtSigned && (v & (0x80000000)) )
+                  {
+                  v = ~v + 1;
+                  sign = 1;
+                  }
+
+                /* Count digits, and get largest place value */
+                vShrink = v;
+                p = 1;
+                digitCount = 1;
+                while( (vShrink = vShrink / fmtBase) > 0 )
+                  {
+                  digitCount++;
+                  p *= fmtBase;
+                  }
+
+                /* Print leading characters & sign */
+                fmtBeforeDecimal -= digitCount;
+                if(fmtLeadingZero)
+                  {
+                  if(sign)
+                    {
+                    alt_log_txchar('-',(char*)base);
+                    fmtBeforeDecimal--;
+                    }
+                  alt_log_repchar('0',fmtBeforeDecimal,base);
+                  }
+                else
+                  {
+                    if(sign)
+                    {
+                      fmtBeforeDecimal--;
+                    }
+                    alt_log_repchar(' ',fmtBeforeDecimal,base);
+                    if(sign)
+                    {
+                      alt_log_txchar('-',(char*)base);
+                    }
+                  }
+
+                /* Print numbery parts */
+                while(p)
+                  {
+                  unsigned char d;
+
+                  d = v / p;
+                  d += '0';
+                  if(d > '9')
+                  {
+                    d += (fmtCase ? 'A' : 'a') - '0' - 10;
+                  }
+                  alt_log_txchar(d,(char*)base);
+
+                  v = v % p;
+                  p = p / fmtBase;
+                  }
+                }
+
+              state = pfState_chars;
+              break;
+
+            case 'u':
+              fmtSigned = 0;
+              goto doIntegerPrint;
+            case 'o':
+              fmtSigned = 0;
+              fmtBase = 8;
+              goto doIntegerPrint;
+            case 'x':
+              fmtSigned = 0;
+              fmtBase = 16;
+              goto doIntegerPrint;
+            case 'X':
+              fmtSigned = 0;
+              fmtBase = 16;
+              fmtCase = 1;
+              goto doIntegerPrint;
+
+            case 'c':
+              alt_log_repchar(' ',fmtBeforeDecimal-1,base);
+              alt_log_txchar(va_arg(args,int),(char*)base);
+              break;
+
+            case 's':
+                {
+                char *s;
+
+                s = va_arg(args,char *);
+                alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base);
+
+                while(*s)
+                  alt_log_txchar(*s++,(char*)base);
+                }
+              break;
+            } /* switch last letter of fmt */
+          state=pfState_chars;
+          }
+        break;
+      } /* switch */
+    } /* while chars left */
+  } /* printf */
+
+/* Main logging printf function */
+int alt_log_printf_proc(const char *fmt, ... )
+{
+    va_list args;
+
+    va_start (args, fmt);
+    alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args);
+    return (0);
+}
+
+/* Below are the functions called by different macros in various components. */
+
+/* If the system has a JTAG_UART, include JTAG_UART debugging functions */
+#ifdef __ALTERA_AVALON_JTAG_UART
+
+/* The alarm function in altera_avalon_jtag_uart.c.
+ * This function, when turned on, prints out the status
+ * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS.
+ * If the flag is off, the alarm should never be registered, and this
+ * function should never run */
+alt_u32 altera_avalon_jtag_uart_report_log(void * context)
+{
+    if (alt_log_jtag_uart_alarm_on_flag) {
+    altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context;
+        const char* header="JTAG Alarm:";
+        alt_log_jtag_uart_print_control_reg(dev, dev->base, header);
+        return ALT_LOG_JTAG_UART_TICKS;
+    }
+    else 
+    {  
+        /* If flag is not on, return 0 to disable future alarms.
+        * Should never be here, alarm should not be enabled at all. */
+        return 0;
+    }
+}
+
+void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header)
+{
+     unsigned int control, space, ac, wi, ri, we, re;
+     control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base);
+     space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >>
+             ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST;
+     we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >>
+         ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST;
+     re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >>
+         ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST;
+     ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >>
+         ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST;
+     wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >>
+         ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST;
+     ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >>
+         ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST;
+         
+#ifdef ALTERA_AVALON_JTAG_UART_SMALL
+    ALT_LOG_PRINTF(
+     "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n",
+         header,space,ac,wi,ri,we,re);
+#else
+    ALT_LOG_PRINTF(
+     "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n",
+         header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re);
+#endif   
+         
+     return;
+
+}
+
+/* In altera_avalon_jtag_uart.c
+ * Same output as the alarm function above, but this is called in the driver
+ * init function.  Hence, it gives the status of the JTAG UART control register
+ * right at the initialization of the driver */ 
+void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base)
+{
+     const char* header="JTAG Startup Info:";
+     alt_log_jtag_uart_print_control_reg(dev, base, header);
+     return;
+}
+
+/* In altera_avalon_jtag_uart.c
+ * When turned on, this function will print out the status of the jtag uart
+ * control register every time there is a jtag uart "almost-empty" interrupt. */
+void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) 
+{
+    if (alt_log_jtag_uart_isr_on_flag) {
+        const char* header="JTAG IRQ:";
+        alt_log_jtag_uart_print_control_reg(dev, base, header);
+    }
+    return;
+}
+
+#endif /* __ALTERA_AVALON_JTAG_UART */ 
+
+/* In alt_write.c
+ * When the alt_log_write_on_flag is turned on, this function gets called
+ * every time alt_write gets called.  The first 
+ * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command
+ * that eventually calls write()) gets echoed to the alt_log output. */
+void alt_log_write(const void *ptr, size_t len)
+{
+    if (alt_log_write_on_flag) {
+    int temp_cnt;
+        int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN;
+
+        if (length < 2) return;
+
+        strncpy (alt_log_write_buf,ptr,length);
+    alt_log_write_buf[length-1]='\n';
+    alt_log_write_buf[length]='\r';
+    alt_log_write_buf[length+1]='\0';
+
+    /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal
+         * connection of alt_log. It will get replaced by 'D'. */
+        for (temp_cnt=0;temp_cnt < length; temp_cnt++) {
+        if (alt_log_write_buf[temp_cnt]== 0x4) {
+            alt_log_write_buf[temp_cnt]='D';
+        }
+    }
+        ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf);
+    }
+}
+
+/* In altera_avalon_timer_sc
+ * This function prints out a system clock is alive message
+ * every ALT_LOG_SYS_CLK_INTERVAL (in ticks).  */
+void alt_log_system_clock()
+{
+    if (alt_log_sys_clk_on_flag) {
+    alt_log_sys_clk_count++;
+        if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) {
+            alt_log_sys_clk_count = 0;
+            ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++);
+        }
+    }
+}
+
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c
new file mode 100644
index 0000000..a56dbfb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_lseek.c
@@ -0,0 +1,117 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <unistd.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+off_t ALT_LSEEK (int file, off_t ptr, int dir)
+{
+  /* Generate a link time warning, should this function ever be called. */
+  
+  ALT_STUB_WARNING(lseek);
+  
+  /* Indicate an error */
+  
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+/*
+ * lseek() can be called to move the read/write pointer associated with the 
+ * file descriptor "file". This function simply vectors the call to the lseek()
+ * function provided by the driver associated with the file descriptor.
+ *
+ * If the driver does not provide an implementation of lseek() an error is
+ * indicated.
+ *
+ * lseek() corresponds to the standard lseek() function.
+ *
+ * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h
+ *
+ */
+
+off_t ALT_LSEEK (int file, off_t ptr, int dir)
+{
+  alt_fd* fd;
+  off_t   rc = 0; 
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd) 
+  {
+    /*
+     * If the device driver provides an implementation of the lseek() function,
+     * then call that to process the request.
+     */
+ 
+    if (fd->dev->lseek)
+    {
+      rc = fd->dev->lseek(fd, ptr, dir);
+    }
+    /*
+     * Otherwise return an error.
+     */
+
+    else
+    {
+      rc = -ENOTSUP;
+    }
+  }
+  else  
+  {
+    rc = -EBADFD;
+  }
+
+  if (rc < 0)
+  {
+    ALT_ERRNO = -rc;
+    rc = -1;
+  }
+
+  return rc;
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c
new file mode 100644
index 0000000..33e3463
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_main.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#include "sys/alt_dev.h"
+#include "sys/alt_sys_init.h"
+#include "sys/alt_irq.h"
+#include "sys/alt_dev.h"
+
+#include "os/alt_hooks.h"
+
+#include "priv/alt_file.h"
+#include "alt_types.h"
+
+#include "system.h"
+
+#include "sys/alt_log_printf.h"
+
+extern void _do_ctors(void);
+extern void _do_dtors(void);
+
+/*
+ * Standard arguments for main. By default, no arguments are passed to main.
+ * However a device driver may choose to configure these arguments by calling
+ * alt_set_args(). The expectation is that this facility will only be used by
+ * the iclient/ihost utility.
+ */
+
+int    alt_argc = 0;
+char** alt_argv = {NULL};
+char** alt_envp = {NULL};
+
+/*
+ * Prototype for the entry point to the users application.
+ */
+
+extern int main (int, char **, char **);
+
+/*
+ * alt_main is the C entry point for the HAL. It is called by the assembler
+ * startup code in the processor specific crt0.S. It is responsible for:
+ * completing the C runtime configuration; configuring all the
+ * devices/filesystems/components in the system; and call the entry point for
+ * the users application, i.e. main().
+ */
+
+void alt_main (void)
+{
+#ifndef ALT_NO_EXIT    
+  int result;
+#endif
+
+  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
+  /* Initialize the interrupt controller. */
+  alt_irq_init (NULL);
+
+  /* Initialize the operating system */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n");
+  ALT_OS_INIT();
+
+  /*
+   * Initialize the semaphore used to control access to the file descriptor
+   * list.
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
+  ALT_SEM_CREATE (&alt_fd_list_lock, 1);
+
+  /* Initialize the device drivers/software components. */
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
+  alt_sys_init();
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n");
+
+#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT))
+
+  /*
+   * Redirect stdio to the apropriate devices now that the devices have
+   * been initialized. This is only done if the user has requested these
+   * devices be present (not equal to /dev/null) and if direct drivers
+   * aren't being used.
+   */
+
+    ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n");
+    alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR);
+#endif
+
+#ifndef ALT_NO_C_PLUS_PLUS
+  /* 
+   * Call the C++ constructors 
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n");
+  _do_ctors ();
+#endif /* ALT_NO_C_PLUS_PLUS */
+
+#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT)
+  /*
+   * Set the C++ destructors to be called at system shutdown. This is only done
+   * if a clean exit has been requested (i.e. the exit() function has not been
+   * redefined as _exit()). This is in the interest of reducing code footprint,
+   * in that the atexit() overhead is removed when it's not needed.
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n");
+  atexit (_do_dtors);
+#endif
+
+  /*
+   * Finally, call main(). The return code is then passed to a subsequent
+   * call to exit() unless the application is never supposed to exit.
+   */
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");
+
+#ifdef ALT_NO_EXIT
+  main (alt_argc, alt_argv, alt_envp);
+#else
+  result = main (alt_argc, alt_argv, alt_envp);
+  close(STDOUT_FILENO);
+  exit (result);
+#endif
+
+  ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n");
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S
new file mode 100644
index 0000000..cf510da
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_mcount.S
@@ -0,0 +1,198 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*  mcount or _mcount is inserted by GCC before the function prologue of every 
+ *  function when a program is compiled for profiling. At the start of mcount,
+ *  we guarantee that:
+ *  ra = self_pc (an address in the function which called mcount)
+ *  r8 = from_pc (an address in the function which called mcount's caller)
+ *
+ *  Because this is always called at the start of a function we can corrupt
+ *  r2,r3 and r11-r15.  We must not corrupt r4-r7 (because they might contain
+ *  function arguments for the instrumented function) or r8 (which holds ra
+ *  for the instrumented function).
+ */
+
+        .global __mcount_fn_head
+
+        .global mcount
+
+        /* _mcount is used by gcc4 */
+        .global _mcount
+
+_mcount:        
+mcount:
+        /* Use a hash to speed up locating fn_entry.  We use bits 5 upwards to choose
+         * the bucket because bits 1:0 will always be 0, and because the distribution
+         * of values for bits 4:2 won't be even (aligning on cache line boundaries
+         * will skew it).  Higher bits should be fairly random.
+         */
+        /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */
+
+        srli    r2, ra, 3
+        movhi   r3, %hiadj(__mcount_fn_head)
+        addi    r3, r3, %lo(__mcount_fn_head)
+        andi    r2, r2, 0xFC
+        add     r11, r2, r3
+
+        /* The fast case is where we have already allocated a function arc, and so
+         * also a function pointer.
+         */
+
+        /* First find the function being called (using self_pc) */
+        mov     r10, r11
+0:
+        ldw     r10, 0(r10)
+        beq     r10, zero, .Lnew_arc
+        ldw     r2, 4(r10)
+        bne     r2, ra, 0b
+
+        /* Found a function entry for this PC. Now look for an arc with a matching
+         * from_pc value. There will always be at least one arc. */
+        ldw     r3, 8(r10)
+0:
+        ldw     r2, 4(r3)
+        beq     r2, r8, .Lfound_arc
+        ldw     r3, 0(r3)
+        bne     r3, zero, 0b
+
+.Lnew_arc:
+        addi    sp, sp, -24
+
+.LCFI0:
+        stw     ra, 0(sp)
+        stw     r4, 4(sp)
+        stw     r5, 8(sp)
+        stw     r6, 12(sp)
+        stw     r7, 16(sp)
+        stw     r8, 20(sp)
+
+.LCFI1:
+        /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */
+        mov     r4, ra
+        mov     r5, r8
+        mov     r6, r10
+        mov     r7, r11
+        call     __mcount_record
+        
+        /* restore registers from the stack */
+        ldw     ra, 0(sp)
+        ldw     r4, 4(sp)
+        ldw     r5, 8(sp)
+        ldw     r6, 12(sp)
+        ldw     r7, 16(sp)
+        ldw     r8, 20(sp)
+
+        addi    sp, sp, 24
+
+.LCFI2:
+        ret
+
+.Lfound_arc:
+        /* We've found the correct arc record.  Increment the count and return */
+        ldw     r2, 8(r3)
+        addi    r2, r2, 1
+        stw     r2, 8(r3)
+        ret
+
+.Lmcount_end:
+
+
+
+/*
+ * Dwarf2 debug information for the function.  This provides GDB with the
+ * information it needs to backtrace out of this function.
+ */
+
+        .section    .debug_frame,"",@progbits
+.LCIE:
+        .4byte   2f - 1f               /* Length */
+1:
+        .4byte   0xffffffff            /* CIE id */
+        .byte    0x1                   /* Version */
+        .string  ""                    /* Augmentation */
+        .uleb128 0x1                   /* Code alignment factor */
+        .sleb128 -4                    /* Data alignment factor */
+        .byte    0x1f                  /* Return address register */
+
+        .byte    0xc                   /* Define CFA */
+        .uleb128 0x1b                  /*   Register 27 (sp) */
+        .uleb128 0x0                   /*   Offset 0 */
+
+        .align   2                     /* Padding */
+2:
+
+.LFDE_mcount:
+        .4byte   2f - 1f               /* Length */
+1:
+        .4byte   .LCIE                 /* Pointer to CIE */
+        .4byte   mcount                /* Start of table entry */
+        .4byte   .Lmcount_end - mcount /* Size of table entry */
+
+        .byte    0x4                   /* Advance location */
+        .4byte   .LCFI0 - mcount       /*   to .LCFI0 */
+        .byte    0xe                   /* Define CFA offset */
+        .uleb128 24                    /*   to 24     */
+
+        .byte    0x4                   /* Advance location */
+        .4byte   .LCFI1 - .LCFI0       /*   to .LCFI1 */
+        .byte    0x9f                  /* Store ra    */
+        .uleb128 0x6                   /*   at CFA-24 */
+        .byte    0x84                  /* Store r4    */
+        .uleb128 0x5                   /*   at CFA-20 */
+        .byte    0x85                  /* Store r5    */
+        .uleb128 0x4                   /*   at CFA-16 */
+        .byte    0x86                  /* Store r6    */
+        .uleb128 0x3                   /*   at CFA-12 */
+        .byte    0x87                  /* Store r7    */
+        .uleb128 0x2                   /*   at CFA-8  */
+        .byte    0x88                  /* Store r8    */
+        .uleb128 0x1                   /*   at CFA-4  */
+
+        .byte    0x4                   /* Advance location */
+        .4byte   .LCFI2 - .LCFI1       /*   to .LCFI2 */
+        .byte    0xe                   /* Define CFA offset */
+        .uleb128 0                     /*   to 0      */
+        .byte    0x8                   /* Same value  */
+        .uleb128 31                    /*   for ra    */
+        .byte    0x8                   /* Same value  */
+        .uleb128 4                     /*   for r4    */
+        .byte    0x8                   /* Same value  */
+        .uleb128 5                     /*   for r5    */
+        .byte    0x8                   /* Same value  */
+        .uleb128 6                     /*   for r6    */
+        .byte    0x8                   /* Same value  */
+        .uleb128 7                     /*   for r7    */
+        .byte    0x8                   /* Same value  */
+        .uleb128 8                     /*   for r8    */
+
+        .align   2
+2:
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c
new file mode 100644
index 0000000..d7040bc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_open.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "alt_types.h"
+#include "os/alt_syscall.h"
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+int ALT_OPEN (const char* file, int flags, int mode)
+{
+  /* Generate a link time warning, should this function ever be called. */
+  
+  ALT_STUB_WARNING(open);
+  
+  /* Indicate an error */
+  
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+extern alt_llist alt_dev_list;
+
+/*
+ * alt_file_locked() is used by open() to ensure that a device has not been
+ * previously locked for exclusive access using ioctl(). This test is only
+ * performed for devices. Filesystems are required to handle the ioctl() call
+ * themselves, and report the error from the filesystems open() function. 
+ */ 
+
+static int alt_file_locked (alt_fd* fd)
+{
+  alt_u32 i;
+
+  /*
+   * Mark the file descriptor as belonging to a device.
+   */
+
+  fd->fd_flags |= ALT_FD_DEV;
+
+  /*
+   * Loop through all current file descriptors searching for one that's locked
+   * for exclusive access. If a match is found, generate an error.
+   */
+
+  for (i = 0; i <= alt_max_fd; i++)
+  {
+    if ((alt_fd_list[i].dev == fd->dev) &&
+        (alt_fd_list[i].fd_flags & ALT_FD_EXCL) &&
+        (&alt_fd_list[i] != fd))
+    {
+      return -EACCES;
+    }
+  }
+  
+  /* The device is not locked */
+ 
+  return 0;
+}
+
+/*
+ * open() is called in order to get a file descriptor that reference the file
+ * or device named "name". This descriptor can then be used to manipulate the
+ * file/device using the standard system calls, e.g. write(), read(), ioctl()
+ * etc.
+ *
+ * This is equivalent to the standard open() system call.
+ *
+ * ALT_OPEN is mapped onto the open() system call in alt_syscall.h
+ */
+ 
+int ALT_OPEN (const char* file, int flags, int mode)
+{ 
+  alt_dev* dev;
+  alt_fd*  fd;
+  int index  = -1;
+  int status = -ENODEV;
+  int isafs = 0;
+
+  /* 
+   * Check the device list, to see if a device with a matching name is 
+   * registered.
+   */
+  
+  if (!(dev = alt_find_dev (file, &alt_dev_list)))
+  {
+    /* No matching device, so try the filesystem list */
+
+    dev   = alt_find_file (file);
+    isafs = 1;
+  }
+
+  /* 
+   * If a matching device or filesystem is found, allocate a file descriptor. 
+   */
+
+  if (dev)
+  {
+    if ((index = alt_get_fd (dev)) < 0)
+    {
+      status = index;
+    }
+    else
+    {
+      fd = &alt_fd_list[index];
+      fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK);
+      
+      /* If this is a device, ensure it isn't already locked */
+
+      if (isafs || ((status = alt_file_locked (fd)) >= 0))
+      {
+        /* 
+         * If the device or filesystem provides an open() callback function,
+         * call it now to perform any device/filesystem specific operations.
+         */
+    
+        status = (dev->open) ? dev->open(fd, file, flags, mode): 0;
+      }
+    }
+  }
+  else
+  {
+    status = -ENODEV;
+  }
+
+  /* Allocation failed, so clean up and return an error */ 
+
+  if (status < 0)
+  {
+    alt_release_fd (index);  
+    ALT_ERRNO = -status;
+    return -1;
+  }
+  
+  /* return the reference upon success */
+
+  return index;
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c
new file mode 100644
index 0000000..f81b290
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_printf.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/*
+ * This file provides a very minimal printf implementation for use with very
+ * small applications.  Only the following format strings are supported:
+ *   %x
+ *   %s
+ *   %c
+ *   %%
+ */
+
+#include <stdarg.h>
+#include "sys/alt_stdio.h"
+#ifdef ALT_SEMIHOSTING
+#define alt_putchar(x) alt_putcharbuf(x)
+#endif
+/* 
+ * ALT printf function 
+ */
+void 
+alt_printf(const char* fmt, ... )
+{
+	va_list args;
+	va_start(args, fmt);
+    const char *w;
+    char c;
+
+    /* Process format string. */
+    w = fmt;
+    while ((c = *w++) != 0)
+    {
+        /* If not a format escape character, just print  */
+        /* character.  Otherwise, process format string. */
+        if (c != '%')
+        {
+            alt_putchar(c);
+        }
+        else
+        {
+            /* Get format character.  If none     */
+            /* available, processing is complete. */
+            if ((c = *w++) != 0)
+            {
+                if (c == '%')
+                {
+                    /* Process "%" escape sequence. */
+                    alt_putchar(c);
+                } 
+                else if (c == 'c')
+                {
+                    int v = va_arg(args, int);
+                    alt_putchar(v);
+                }
+                else if (c == 'x')
+                {
+                    /* Process hexadecimal number format. */
+                    unsigned long v = va_arg(args, unsigned long);
+                    unsigned long digit;
+                    int digit_shift;
+
+                    /* If the number value is zero, just print and continue. */
+                    if (v == 0)
+                    {
+                        alt_putchar('0');
+                        continue;
+                    }
+
+                    /* Find first non-zero digit. */
+                    digit_shift = 28;
+                    while (!(v & (0xF << digit_shift)))
+                        digit_shift -= 4;
+
+                    /* Print digits. */
+                    for (; digit_shift >= 0; digit_shift -= 4)
+                    {
+                        digit = (v & (0xF << digit_shift)) >> digit_shift;
+                        if (digit <= 9)
+                            c = '0' + digit;
+                        else
+                            c = 'a' + digit - 10;
+                        alt_putchar(c);
+                    }
+                }
+                else if (c == 's')
+                {
+                    /* Process string format. */
+                    char *s = va_arg(args, char *);
+
+                    while(*s)
+                      alt_putchar(*s++);
+                }
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+#ifdef ALT_SEMIHOSTING
+    alt_putbufflush();
+#endif
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c
new file mode 100644
index 0000000..a8049d7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putchar.c
@@ -0,0 +1,68 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stdio.h>
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+#include "system.h"
+#include "sys/alt_driver.h"
+#include "sys/alt_stdio.h"
+#endif
+#ifdef ALT_SEMIHOSTING
+#include "sys/alt_stdio.h"
+#include "unistd.h"
+#endif
+
+/*
+ * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available.
+ * Otherwise, uses newlib provided putchar() routine.
+ */
+int 
+alt_putchar(int c)
+{
+#ifdef ALT_SEMIHOSTING
+	char        c1 = (char)(c & 0xff);
+    return write(STDOUT_FILENO,&c1,1);
+#else
+#ifdef ALT_USE_DIRECT_DRIVERS
+    ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV);
+    char        c1 = (char)(c & 0xff);
+
+    if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) {
+        return -1;
+    }
+    return c;
+#else
+    return putchar(c);
+#endif
+#endif
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c
new file mode 100644
index 0000000..a0e4f2b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putcharbuf.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+
+#ifdef ALT_SEMIHOSTING
+#include "sys/alt_stdio.h"
+#include "unistd.h"
+
+#ifndef ALT_PUTBUF_SIZE
+#define ALT_PUTBUF_SIZE 64
+#endif
+
+// Buffer for the printed chars
+static char buf[ALT_PUTBUF_SIZE] ={0};
+// index into the buffer
+static unsigned int fill_index;
+
+/* 
+ * ALT putcharbuf funtion
+ * Used only for semihosting. 
+ * Not thread safe!
+ * This fucntion buffers up chars to be printed until either alt_putbufflush()
+ * is called or the buffer is full.
+ * It is called by alt_printf when semihosting is turned on
+ * Its purpose is to minimize the number of Break 1 issuesd by the semihosting
+ * libraries. 
+ */
+int 
+alt_putcharbuf(int c)
+{
+    buf[fill_index++] = (char)(c & 0xff);
+    if(fill_index >= ALT_PUTBUF_SIZE)
+        alt_putbufflush();
+    return c;
+}
+
+/*
+ * ALT putbufflush 
+ * used only for smehosting
+ * Not thread safe!
+ * Dumps all the chars in the buffer to STDOUT
+ */
+int 
+alt_putbufflush()
+{
+    int results;
+    results = write(STDOUT_FILENO,buf,fill_index);
+    fill_index = 0;
+    return results;
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c
new file mode 100644
index 0000000..add3402
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_putstr.c
@@ -0,0 +1,64 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <stdio.h>
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+#include <string.h>
+#include "system.h"
+#include "sys/alt_driver.h"
+#include "sys/alt_stdio.h"
+#endif
+#ifdef ALT_SEMIHOSTING
+#include <string.h>
+#include "sys/alt_stdio.h"
+#include "unistd.h"
+#endif
+
+/*
+ * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available.
+ * Otherwise, uses newlib provided fputs() routine.
+ */
+int 
+alt_putstr(const char* str)
+{
+#ifdef ALT_SEMIHOSTING
+    return write(STDOUT_FILENO,str,strlen(str));
+#else
+#ifdef ALT_USE_DIRECT_DRIVERS
+    ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV);
+    return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0);
+#else
+    return fputs(str, stdout);
+#endif
+#endif
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c
new file mode 100644
index 0000000..920ab13
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_read.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <unistd.h>
+#include <fcntl.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+/*
+ * The read() system call is used to read a block of data from a file or device.
+ * This function simply vectors the request to the device driver associated
+ * with the input file descriptor "file". 
+ *
+ * ALT_READ is mapped onto the read() system call in alt_syscall.h
+ */
+
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#include "system.h"
+#include "sys/alt_driver.h"
+
+/*
+ * Provide minimal version that just reads from the stdin device when provided.
+ */
+
+int ALT_READ (int file, void *ptr, size_t len)
+{
+#ifdef ALT_STDIN_PRESENT
+    ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV);
+#endif
+
+#if !defined(ALT_STDIN_PRESENT)
+    /* Generate a link time warning, should this function ever be called. */
+    ALT_STUB_WARNING(read);
+#endif
+
+    switch (file) {
+#ifdef ALT_STDIN_PRESENT
+    case 0: /* stdin file descriptor */
+        return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0);
+#endif /* ALT_STDIN_PRESENT */
+    default:
+        ALT_ERRNO = EBADFD;
+        return -1;
+    }
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_READ (int file, void *ptr, size_t len)
+{
+  alt_fd*  fd;
+  int      rval;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+    /*
+     * If the file has not been opened with read access, or if the driver does
+     * not provide an implementation of read(), generate an error. Otherwise
+     * call the drivers read() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && 
+        (fd->dev->read))
+      {
+        if ((rval = fd->dev->read(fd, ptr, len)) < 0)
+        {
+          ALT_ERRNO = -rval;
+          return -1;
+        }
+        return rval;
+      }
+      else
+      {
+        ALT_ERRNO = EACCES;
+      }
+    }
+  else
+  {
+    ALT_ERRNO = EBADFD;
+  }
+  return -1;
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c
new file mode 100644
index 0000000..c22a97f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_release_fd.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_dev.h"
+#include "priv/alt_file.h"
+
+/*
+ * alt_release_fd() is called to free an allocated file descriptor. This is 
+ * done by setting the device pointer in the file descriptor structure to zero.
+ * 
+ * File descriptors correcponding to standard in, standard out and standard 
+ * error cannont be released backed to the pool. They are always reserved.
+ */
+
+void alt_release_fd (int fd)
+{
+  if (fd > 2)
+  {
+    alt_fd_list[fd].fd_flags = 0;
+    alt_fd_list[fd].dev      = 0;
+  }
+}
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c
new file mode 100644
index 0000000..6d7c137
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_cached.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_warning.h"
+#include "sys/alt_cache.h"
+#include "system.h"
+
+/*
+ * Convert a pointer to a block of uncached memory into a block of cached memory.
+ * Return a pointer that should be used to access the cached memory.
+ */
+
+void* 
+alt_remap_cached(volatile void* ptr, alt_u32 len)
+{
+#if ALT_CPU_DCACHE_SIZE > 0
+#ifdef ALT_CPU_DCACHE_BYPASS_MASK
+  return (void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK);
+#else /* No address mask option enabled. */
+  /* Generate a link time error, should this function ever be called. */
+  ALT_LINK_ERROR("alt_remap_cached() is not available because CPU is not configured to use bit 31 of address to bypass data cache");
+  return NULL;
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Nothing needs to be done to the pointer. */
+  return (void*) ptr;
+#endif /* No data cache */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c
new file mode 100644
index 0000000..7b3a216
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_remap_uncached.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_warning.h"
+#include "sys/alt_cache.h"
+#include "system.h"
+
+/*
+ * Convert a pointer to a block of cached memory into a block of uncached memory.
+ * Return a pointer that should be used to access the uncached memory.
+ *
+ * This routine was created for Nios II Gen1 cores which allow mixing cacheable and
+ * uncachable data in the same data cache line. So, they could take any memory region
+ * and make it uncached. However, Nios II Gen2 cores don't support mixing cacheable
+ * and uncachable data in the same data cache line so require the memory region to
+ * be aligned to a cache line boundary and must be an integer number of cache line
+ * bytes in size. So, software on a Nios II Gen2 core shouldn't really be using this
+ * function so it fails with a link error.
+ */
+
+volatile void* 
+alt_remap_uncached(void* ptr, alt_u32 len)
+{
+  /* Generate a link time error, should this function ever be called. */
+  ALT_LINK_ERROR("alt_remap_uncached() is not available because Nios II Gen2 cores with data caches don't support mixing cacheable and uncacheable data on the same line.");
+  return NULL;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c
new file mode 100644
index 0000000..26db44d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_rename.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "os/alt_syscall.h"
+
+/*
+ * _rename() is used by newlib to rename an existing file. This is unsupported 
+ * in the HAL environment. However a "do-nothing" implementation is still 
+ * provied for newlib compatability.
+ *
+ * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h
+ */
+ 
+int ALT_RENAME (char *existing, char *new)
+{
+  /* Generate a link time warning, should this function ever be called. */
+
+  ALT_STUB_WARNING(_rename);
+
+  /* Indicate an error */
+
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c
new file mode 100644
index 0000000..7ab3367
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_sbrk.c
@@ -0,0 +1,136 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <sys/types.h>
+
+#include "os/alt_syscall.h"
+
+#include "sys/alt_irq.h"
+#include "sys/alt_stack.h"
+
+#include "system.h"
+
+/*
+ * sbrk() is called to dynamically extend the data segment for the application.
+ * Thie input argument "incr" is the size of the block to allocate.
+ *
+ * This simple implementation does not perform any bounds checking. Memory will
+ * be allocated, even if the request region colides with the stack or overflows
+ * the available physical memory. 
+ *
+ * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h
+ *
+ * This function is called by the profiling code to allocate memory so must be
+ * safe if called from an interrupt context.  It must also not be instrumented
+ * because that would lead to an infinate loop.
+ */
+
+extern char __alt_heap_start[]; /* set by linker */
+extern char __alt_heap_limit[]; /* set by linker */
+
+static char *heap_end = __alt_heap_start;
+
+#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK)
+char * alt_exception_old_stack_limit = NULL;
+#endif
+ 
+caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function ));
+
+caddr_t ALT_SBRK (int incr)
+{ 
+  alt_irq_context context;
+  char *prev_heap_end; 
+
+  context = alt_irq_disable_all();
+
+  /* Always return data aligned on a word boundary */
+  heap_end = (char *)(((unsigned int)heap_end + 3) & ~3);
+
+#ifdef ALT_MAX_HEAP_BYTES
+  /*  
+   * User specified a maximum heap size.  Return -1 if it would
+   * be exceeded by this sbrk call.
+   */
+  if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) {
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+  }
+#else
+  if ((heap_end + incr) > __alt_heap_limit) {
+    alt_irq_enable_all(context);
+    return (caddr_t)-1;
+  }
+#endif
+
+  prev_heap_end = heap_end; 
+  heap_end += incr; 
+
+#ifdef ALT_STACK_CHECK
+  /*
+   * If the stack and heap are contiguous then extending the heap reduces the
+   * space available for the stack.  If we are still using the default stack
+   * then adjust the stack limit to note this, while checking for stack
+   * pointer overflow. 
+   * If the stack limit isn't pointing at the top of the heap then the code
+   * is using a different stack so none of this needs to be done.
+   */
+
+  if (alt_stack_limit() == prev_heap_end)
+  {
+    if (alt_stack_pointer() <= heap_end)
+      alt_report_stack_overflow();
+
+    alt_set_stack_limit(heap_end);
+  }
+
+#ifdef ALT_EXCEPTION_STACK
+  /*
+   * If we are executing from the exception stack then compare against the
+   * stack we switched away from as well.  The exception stack is a fixed
+   * size so doesn't need to be checked.
+   */
+
+  if (alt_exception_old_stack_limit == prev_heap_end)
+  {
+    if (alt_exception_old_stack_limit <= heap_end)
+      alt_report_stack_overflow();
+
+    alt_exception_old_stack_limit = heap_end;
+  }
+#endif
+
+#endif
+
+  alt_irq_enable_all(context);
+
+  return (caddr_t) prev_heap_end; 
+} 
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c
new file mode 100644
index 0000000..13349b8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_settod.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <sys/time.h>
+#include <sys/times.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_alarm.h"
+#include "os/alt_syscall.h"
+
+/*
+ * "alt_timezone" and "alt_resettime" are the values of the the reset time and
+ * time zone set through the last call to settimeofday(). By default they are
+ * zero initialised.
+ */
+
+extern struct timezone alt_timezone;
+extern struct timeval  alt_resettime;
+
+/*
+ * Macro defining the number of micoseconds in a second.
+ */
+
+#define ALT_US (1000000)
+
+
+/*
+ * settimeofday() can be called to calibrate the system clock, so that 
+ * subsequent calls to gettimeofday() will return the elapsed "wall clock" 
+ * time.
+ *
+ * This is done by updating the global structures "alt_resettime" and 
+ * "alt_timezone" so that an immediate call to gettimeofday() would return
+ * the value specified by "t" and "tz". 
+ *
+ * Warning: if this function is called concurrently with a call to 
+ * gettimeofday(), the value returned by gettimeofday() will be unreliable.  
+ *
+ * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in 
+ * alt_syscall.h
+ */
+ 
+int ALT_SETTIMEOFDAY (const struct timeval  *t,
+                      const struct timezone *tz)
+{
+  alt_u32 nticks    = alt_nticks ();
+  alt_u32 tick_rate = alt_ticks_per_second ();
+
+  /* If there is a system clock available, update the current time */
+
+  if (tick_rate)
+  {
+    alt_resettime.tv_sec  = t->tv_sec - nticks/tick_rate;
+    alt_resettime.tv_usec = t->tv_usec - 
+      ((nticks*(ALT_US/tick_rate))%ALT_US);
+
+    alt_timezone.tz_minuteswest = tz->tz_minuteswest;
+    alt_timezone.tz_dsttime     = tz->tz_dsttime;
+    
+    return 0;
+  }
+  
+  /* There's no system clock available */
+
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S b/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S
new file mode 100644
index 0000000..0a9381e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_software_exception.S
@@ -0,0 +1,53 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+ /*
+  * This file provides the global symbol: software_exception. It is provided to
+  * support legacy code, and should not be used by new software.
+  *
+  * It is used by legacy code to invoke the software exception handler as
+  * defined by version 1.0 of the Nios II kit. It should only be used when you
+  * are providing your own interrupt entry point, i.e. you are not using
+  * alt_irq_entry.
+  */
+	
+#include "system.h"
+
+        /*
+         * Pull in the exception handler.
+         */
+
+        .globl alt_exception
+
+        .section .exceptions.entry.label, "xa"
+
+        .globl software_exception
+        .type software_exception, @function
+software_exception:
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c
new file mode 100644
index 0000000..c196d0c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_stat.c
@@ -0,0 +1,59 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+
+#include "os/alt_syscall.h"
+
+/*
+ * The stat() function is similar to the fstat() function in that it is used to
+ * obtain status information about a file. Instead of using an open file
+ * descriptor (like fstat()), stat() takes the name of a file as an input 
+ * argument. 
+ *
+ * ALT_STAT is mapped onto the stat() system call in alt_syscall.h
+ */
+ 
+int ALT_STAT (const char *file, struct stat *st)
+{
+  int fd;
+  int rc;
+
+  fd = open (file, 0);
+  rc = fstat (fd, st);
+  close (fd);
+
+  return rc;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c
new file mode 100644
index 0000000..23719b1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_tick.c
@@ -0,0 +1,149 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_irq.h"
+#include "sys/alt_alarm.h"
+#include "os/alt_hooks.h"
+#include "alt_types.h"
+
+/*
+ * "_alt_tick_rate" is used to store the value of the system clock frequency
+ * in ticks per second. It is initialised to zero, which corresponds to there
+ * being no system clock facility available. 
+ */
+
+alt_u32 _alt_tick_rate = 0;
+
+/*
+ * "_alt_nticks" is the number of system clock ticks that have elapsed since
+ * reset. 
+ */
+
+volatile alt_u32 _alt_nticks = 0;
+
+/*
+ * "alt_alarm_list" is the head of a linked list of registered alarms. This is
+ * initialised to be an empty list.
+ */
+
+ALT_LLIST_HEAD(alt_alarm_list);
+
+/*
+ * alt_alarm_stop() is called to remove an alarm from the list of registered 
+ * alarms. Alternatively an alarm can unregister itself by returning zero when 
+ * the alarm executes.
+ */
+
+void alt_alarm_stop (alt_alarm* alarm)
+{
+  alt_irq_context irq_context;
+
+  irq_context = alt_irq_disable_all();
+  alt_llist_remove (&alarm->llist);
+  alt_irq_enable_all (irq_context);
+}
+
+/*
+ * alt_tick() is periodically called by the system clock driver in order to
+ * process the registered list of alarms. Each alarm is registed with a
+ * callback interval, and a callback function, "callback". 
+ *
+ * The return value of the callback function indicates how many ticks are to
+ * elapse until the next callback. A return value of zero indicates that the
+ * alarm should be deactivated. 
+ * 
+ * alt_tick() is expected to run at interrupt level.
+ */
+
+void alt_tick (void)
+{
+  alt_alarm* next;
+  alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next;
+
+  alt_u32    next_callback;
+
+  /* update the tick counter */
+
+  _alt_nticks++;
+
+  /* process the registered callbacks */
+
+  while (alarm != (alt_alarm*) &alt_alarm_list)
+  {
+    next = (alt_alarm*) alarm->llist.next;
+
+    /* 
+     * Upon the tick-counter rolling over it is safe to clear the 
+     * roll-over flag; once the flag is cleared this (or subsequnt)
+     * tick events are enabled to generate an alarm event. 
+     */
+    if ((alarm->rollover) && (_alt_nticks == 0))
+    {
+      alarm->rollover = 0;
+    }
+    
+    /* if the alarm period has expired, make the callback */    
+    if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0))
+    {
+      next_callback = alarm->callback (alarm->context);
+
+      /* deactivate the alarm if the return value is zero */
+
+      if (next_callback == 0)
+      {
+        alt_alarm_stop (alarm);
+      }
+      else
+      {
+        alarm->time += next_callback;
+        
+        /* 
+         * If the desired alarm time causes a roll-over, set the rollover
+         * flag. This will prevent the subsequent tick event from causing
+         * an alarm too early.
+         */
+        if(alarm->time < _alt_nticks)
+        {
+          alarm->rollover = 1;
+        }
+      }
+    }
+    alarm = next;
+  }
+
+  /* 
+   * Update the operating system specific timer facilities.
+   */
+
+  ALT_OS_TIME_TICK();
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c
new file mode 100644
index 0000000..6543164
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_times.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <sys/times.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_alarm.h"
+#include "os/alt_syscall.h"
+
+/*
+ * The times() function is used by newlib to obtain elapsed time information.
+ * The return value is the elapsed time since reset in system clock ticks. Note
+ * that this is distinct from the strict Posix version of times(), which should
+ * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT.
+ *
+ * The input structure is filled in with time accounting information. This 
+ * implementation attributes all cpu time to the system.
+ *
+ * ALT_TIMES is mapped onto the times() system call in alt_syscall.h
+ */
+ 
+clock_t ALT_TIMES (struct tms *buf)
+{
+  clock_t ticks = alt_nticks(); 
+
+  /* If there is no system clock present, generate an error */
+
+  if (!alt_ticks_per_second())
+  {
+    ALT_ERRNO = ENOSYS;
+    return 0;
+  }
+
+  /* Otherwise return the elapsed time */
+
+  buf->tms_utime  = 0;
+  buf->tms_stime  = ticks;
+  buf->tms_cutime = 0;
+  buf->tms_cstime = 0;
+
+  return ticks;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c
new file mode 100644
index 0000000..0d725c0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_free.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "sys/alt_warning.h"
+#include "sys/alt_cache.h"
+#include "system.h"
+
+/*
+ * Free a block of uncached memory.
+ */
+
+void 
+alt_uncached_free(volatile void* ptr)
+{
+#if ALT_CPU_DCACHE_SIZE > 0
+#ifdef ALT_CPU_DCACHE_BYPASS_MASK
+  free((void*) (((alt_u32)ptr) & ~ALT_CPU_DCACHE_BYPASS_MASK));
+#else /* No address mask option enabled. */
+  /* Generate a link time error, should this function ever be called. */
+  ALT_LINK_ERROR("alt_uncached_free() is not available because CPU is not configured to use bit 31 of address to bypass data cache");
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Nothing needs to be done to the pointer. */
+  free((void*)ptr);
+#endif /* No data cache */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c
new file mode 100644
index 0000000..75af9b0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_uncached_malloc.c
@@ -0,0 +1,77 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA.      *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <malloc.h>
+#include "sys/alt_warning.h"
+#include "sys/alt_cache.h"
+#include "system.h"
+
+/*
+ * Allocate a block of uncached memory.
+ * Return pointer to the block of memory or NULL if can't allocate it.
+ */
+
+volatile void* 
+alt_uncached_malloc(size_t size)
+{
+#if ALT_CPU_DCACHE_SIZE > 0
+#ifdef ALT_CPU_DCACHE_BYPASS_MASK
+
+  void* ptr;
+
+  /* Round up size to an integer number of data cache lines. Required to guarantee that
+   * cacheable and non-cacheable data won't be mixed on the same cache line. */ 
+  const size_t num_lines = (size + ALT_CPU_DCACHE_LINE_SIZE - 1) / ALT_CPU_DCACHE_LINE_SIZE;
+  const size_t aligned_size = num_lines * ALT_CPU_DCACHE_LINE_SIZE;
+
+  /* Use memalign() Newlib routine to allocate starting on a data cache aligned address.
+   * Required to guarantee that cacheable and non-cacheable data won't be mixed on the
+   * same cache line. */ 
+  ptr = memalign(ALT_CPU_DCACHE_LINE_SIZE, aligned_size);
+
+  if (ptr == NULL) {
+    return NULL; /* Out of memory */
+  }
+
+  /* Ensure that the memory region isn't in the data cache. */
+  alt_dcache_flush(ptr, aligned_size);
+
+  return (volatile void*) (((alt_u32)ptr) | ALT_CPU_DCACHE_BYPASS_MASK);
+
+#else /* No address mask option enabled. */
+  /* Generate a link time error, should this function ever be called. */
+  ALT_LINK_ERROR("alt_uncached_malloc() is not available because CPU is not configured to use bit 31 of address to bypass data cache");
+  return NULL;
+#endif /* No address mask option enabled. */
+#else /* No data cache */
+  /* Just use regular malloc. */
+  return malloc(size);
+#endif /* No data cache */
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c
new file mode 100644
index 0000000..606f019
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_unlink.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "os/alt_syscall.h"
+
+/*
+ * unlink() is used by newlib to delete an existing link to a file. This is 
+ * unsupported in the HAL environment. However a "do-nothing" implementation 
+ * is still provied for newlib compatability.
+ *
+ * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h
+ */
+ 
+int ALT_UNLINK (char *name)
+{
+  /* Generate a link time warning, should this function ever be called. */
+  
+  ALT_STUB_WARNING(unlink);
+  
+  /* Indicate an error */
+  
+  ALT_ERRNO = ENOSYS;
+  return -1;
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c
new file mode 100644
index 0000000..86533cb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_usleep.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2003 Altera Corporation, San Jose, California, USA.  
+ * All rights reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
+ * deal in the Software without restriction, including without limitation the 
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is 
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * ------------
+ *
+ * Altera does not recommend, suggest or require that this reference design 
+ * file be used in conjunction or combination with any other product.
+ */
+
+#include <limits.h>
+#include <system.h>
+#include <unistd.h>
+
+#include "sys/alt_alarm.h"
+#include "priv/alt_busy_sleep.h"
+#include "os/alt_syscall.h"
+
+#include "includes.h"
+
+/*
+ * Macro defining the number of micoseconds in a second.
+ */
+
+#define ALT_US (1000000)
+
+/*
+ * This implementation of usleep overrides the default provided in the HAL/src
+ * directory of the altera_nios2 component. When possible, this
+ * implementation uses the uC/OS-II OSTimeDly function to block the current
+ * thread, rather than using a busy loop. This allows other threads to execute 
+ * while the current thread is sleeping.
+ *
+ * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h 
+ */
+
+#if defined (__GNUC__) && __GNUC__ >= 4
+int ALT_USLEEP (useconds_t us)
+#else
+unsigned int ALT_USLEEP (unsigned int us)
+#endif
+{
+  alt_u32 ticks;
+  alt_u32 tick_rate;
+
+  /* 
+   * If the O/S hasn't started yet, then we delay using a busy loop, rather than
+   * OSTimeDly (since this would fail). The use of a busy loop is acceptable,
+   * since the system is still running in a single-threaded mode.
+   */ 
+
+  if (OSRunning == OS_FALSE)
+  {
+    return alt_busy_sleep (us);
+  }
+
+  /* 
+   * Calculate the number of whole system clock ticks to delay.
+   */
+
+  tick_rate = alt_ticks_per_second ();
+  ticks     = (us/ALT_US)* tick_rate + ((us%ALT_US)*tick_rate)/ALT_US;
+
+  /*
+   * OSTimeDly can only delay for a maximum of 0xffff ticks, so if the requested
+   * delay is greater than that, we need to break it down into a number of
+   * seperate delays.
+   */
+
+  while (ticks > 0xffff)
+  {
+    OSTimeDly(0xffff);
+    ticks -= 0xffff;
+  }
+
+  OSTimeDly ((INT16U) (ticks));
+
+  /*
+   * Now delay by the remainder using a busy loop. This is here in order to
+   * provide very short delays of less than one clock tick.
+   */
+
+  alt_busy_sleep (us%(ALT_US/tick_rate));  
+
+  return 0;  
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c
new file mode 100644
index 0000000..dd768ad
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_wait.c
@@ -0,0 +1,52 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2004 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "sys/alt_errno.h"
+#include "os/alt_syscall.h"
+
+/*
+ * wait() is used by newlib to wait for all child processes to exit. Since the
+ * HAL does not support spawning child processes, this returns immediately as
+ * there can't be anythign to wait for.
+ *
+ * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h
+ */
+ 
+int ALT_WAIT (int *status)
+{
+  *status = 0;
+
+  ALT_ERRNO = ECHILD;
+
+  return -1;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c b/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c
new file mode 100644
index 0000000..d161cdf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/alt_write.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <unistd.h>
+#include <fcntl.h>
+
+#include "sys/alt_errno.h"
+#include "sys/alt_warning.h"
+#include "priv/alt_file.h"
+#include "os/alt_syscall.h"
+
+#include "sys/alt_log_printf.h"
+
+/*
+ * The write() system call is used to write a block of data to a file or 
+ * device. This function simply vectors the request to the device driver 
+ * associated with the input file descriptor "file". 
+ *
+ * ALT_WRITE is mapped onto the write() system call in alt_syscall.h
+ */
+ 
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#include "system.h"
+#include "sys/alt_driver.h"
+
+/*
+ * Provide minimal version that just writes to the stdout/stderr devices
+ * when provided.
+ */
+
+int ALT_WRITE (int file, const void *ptr, size_t len)
+{
+#ifdef ALT_STDOUT_PRESENT
+    ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV);
+#endif
+#ifdef ALT_STDERR_PRESENT
+    ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV);
+#endif
+
+#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT)
+    /* Generate a link time warning, should this function ever be called. */
+    ALT_STUB_WARNING(write);
+#endif
+
+    switch (file) {
+#ifdef ALT_STDOUT_PRESENT
+    case 1: /* stdout file descriptor */
+        return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0);
+#endif /* ALT_STDOUT_PRESENT */
+#ifdef ALT_STDERR_PRESENT
+    case 2: /* stderr file descriptor */
+        return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0);
+#endif /* ALT_STDERR_PRESENT */
+    default:
+        ALT_ERRNO = EBADFD;
+        return -1;
+    }
+}
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+int ALT_WRITE (int file, const void *ptr, size_t len)
+{
+  alt_fd*  fd;
+  int      rval;
+
+  /*
+   * A common error case is that when the file descriptor was created, the call
+   * to open() failed resulting in a negative file descriptor. This is trapped
+   * below so that we don't try and process an invalid file descriptor.
+   */
+
+  fd = (file < 0) ? NULL : &alt_fd_list[file];
+  
+  if (fd)
+  {
+    /*
+     * If the file has not been opened with write access, or if the driver does
+     * not provide an implementation of write(), generate an error. Otherwise
+     * call the drivers write() function to process the request.
+     */
+
+    if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write)
+    {
+      
+      /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
+      ALT_LOG_WRITE_FUNCTION(ptr,len);
+
+      if ((rval = fd->dev->write(fd, ptr, len)) < 0)
+      {
+        ALT_ERRNO = -rval;
+        return -1;
+      }
+      return rval;
+    }
+    else
+    {
+      ALT_ERRNO = EACCES;
+    }
+  }
+  else  
+  {
+    ALT_ERRNO = EBADFD;
+  }
+  return -1;
+}
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c b/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c
new file mode 100644
index 0000000..4dfd940
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/altera_nios2_gen2_irq.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2009 Altera Corporation, San Jose, California, USA.  
+ * All rights reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
+ * deal in the Software without restriction, including without limitation the 
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is 
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ * altera_nios2_gen2_irq.c - Support for Nios II internal interrupt controller.
+ *
+ */
+
+#include "sys/alt_irq.h"
+#include "altera_nios2_gen2_irq.h"
+
+/*
+ * To initialize the internal interrupt controller, just clear the IENABLE
+ * register so that all possible IRQs are disabled.
+ */
+void altera_nios2_gen2_irq_init(void) 
+{
+    NIOS2_WRITE_IENABLE(0);
+}
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S b/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S
new file mode 100644
index 0000000..f12623b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/crt0.S
@@ -0,0 +1,521 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+#include "nios2.h"
+
+/* Setup header files to work with assembler code. */
+#define ALT_ASM_SRC
+
+/* Debug logging facility */
+#include "sys/alt_log_printf.h"
+
+/*************************************************************************\
+|                                MACROS                                   |
+\*************************************************************************/
+
+/*
+ * The new build tools explicitly define macros when alt_load()
+ * must be called.  The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that
+ * those macros are controlling if alt_load() needs to be called.
+ */
+#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED
+
+/* Need to call alt_load() if any of these sections are being copied. */
+#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS)
+#define CALL_ALT_LOAD
+#endif
+
+#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
+
+/*
+ * The legacy build tools use the following macros to detect when alt_load()
+ * needs to be called.
+ */
+
+#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \
+  ((res##_BASE != rodata##_BASE) ||                 \
+   (res##_BASE != rwdata##_BASE) ||                 \
+   (res##_BASE != exc##_BASE))
+
+#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \
+    __ALT_LOAD_SECTIONS(res, text, rodata, exc)
+
+#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE,  \
+                                             ALT_RODATA_DEVICE, \
+                                             ALT_RWDATA_DEVICE, \
+                                             ALT_EXCEPTIONS_DEVICE)
+
+/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */
+#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS
+#define CALL_ALT_LOAD
+#endif
+
+#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */
+
+/*
+ * When the legacy build tools define a macro called ALT_NO_BOOTLOADER,
+ * it indicates that initialization code is allowed at the reset address.
+ * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for
+ * the same purpose.
+ */
+#ifdef ALT_NO_BOOTLOADER
+#define ALT_ALLOW_CODE_AT_RESET
+#endif
+
+/*************************************************************************\
+|                         EXTERNAL REFERENCES                             |
+\*************************************************************************/
+
+/*
+ * The entry point for user code is either "main" in hosted mode, or
+ * "alt_main" in standalone mode. These are explicitly referenced here,
+ * to ensure they are built into the executable. This allows the user
+ * to build them into libraries, rather than supplying them in object
+ * files at link time.
+ */
+    .globl main
+    .globl alt_main
+
+/*
+ * Create a reference to the software multiply/divide and trap handers,
+ * so that if they are provided, they will appear in the executable.
+ */
+#ifndef ALT_NO_INSTRUCTION_EMULATION
+    .globl alt_exception_muldiv
+#endif
+#ifdef ALT_TRAP_HANDLER
+    .globl alt_exception_trap
+#endif
+
+/*
+ * Linker defined symbols used to initialize bss.
+ */
+.globl __bss_start
+.globl __bss_end
+
+/*************************************************************************\
+|                         RESET SECTION (.entry)                          |
+\*************************************************************************/
+
+/*
+ * This is the reset entry point for Nios II.
+ *
+ * At reset, only the cache line which contain the reset vector is
+ * initialized by the hardware. The code within the first cache line
+ * initializes the remainder of the instruction cache.
+ */
+
+    .section .entry, "xa"
+    .align 5
+
+/*
+ * Explicitly allow the use of r1 (the assembler temporary register)
+ * within this code. This register is normally reserved for the use of
+ * the assembler.
+ */
+    .set noat
+
+/*
+ * Some tools want to know where the reset vector is.
+ * Code isn't always provided at the reset vector but at least the
+ * __reset label always contains the reset vector address because
+ * it is defined at the start of the .entry section.
+ */
+
+    .globl __reset
+    .type __reset, @function
+__reset:
+
+/*
+ * Initialize the instruction cache if present (i.e. size > 0) and
+ * reset code is allowed unless optimizing for RTL simulation.
+ * RTL simulations can ensure the instruction cache is already initialized
+ * so skipping this loop speeds up RTL simulation.
+ *
+ * When ECC is present, need to execute initi for each word address
+ * to ensure ECC parity bits in cache RAM get initialized.
+ */
+
+#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
+    /* Assume the instruction cache size is always a power of two. */
+#if NIOS2_ICACHE_SIZE > 0x8000
+    movhi r2, %hi(NIOS2_ICACHE_SIZE)
+#else
+    movui r2, NIOS2_ICACHE_SIZE
+#endif
+
+0:
+    initi r2
+    addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
+    bgt r2, zero, 0b
+1:
+
+    /*
+     * The following debug information tells the ISS not to run the loop above
+     * but to perform its actions using faster internal code.
+     */
+    .pushsection .debug_alt_sim_info
+    .int 1, 1, 0b, 1b
+    .popsection
+#endif /* Initialize Instruction Cache */
+
+/*
+ * Jump to the _start entry point in the .text section if reset code
+ * is allowed or if optimizing for RTL simulation.
+ */
+#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
+    /* Jump to the _start entry point in the .text section. */
+    movhi r1, %hi(_start)
+    ori r1, r1, %lo(_start)
+    jmp r1
+
+    .size __reset, . - __reset
+#endif /* Jump to _start */
+
+/*
+ * When not using exit, provide an _exit symbol to prevent unresolved
+ * references to _exit from the linker script.
+ */
+#ifdef ALT_NO_EXIT
+    .globl _exit
+_exit:
+#endif
+
+/*************************************************************************\
+|                          TEXT SECTION (.text)                           |
+\*************************************************************************/
+
+/*
+ * Start of the .text section, and also the code entry point when
+ * the code is executed by a bootloader rather than directly from reset.
+ */
+    .section .text
+    .align 2
+
+    .globl _start
+    .type _start, @function
+_start:
+
+#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)    
+    /*
+     * Ensure that the current register set is 0 upon
+     * entry to this code.  Switch register set to 0 by
+     * writing zero to SSTATUS register and executing an ERET instruction
+     * to set STATUS.CRS to 0.
+     */
+    
+    /* Get the current register set number (STATUS.CRS). */
+    rdctl r2, status
+    andi r2, r2, NIOS2_STATUS_CRS_MSK
+    
+    /* Skip switching register set if STATUS.CRS is 0.  */
+    beq r2, zero, 0f
+
+    /* Set SSTATUS to 0 to get to set SSTATUS.PRS to 0. */
+    .set nobreak
+    movui sstatus, 0
+    .set break
+
+    /* Switch to register set 0 and jump to label. */
+    movhi ea, %hi(0f)
+    ori ea, ea, %lo(0f)
+    eret
+
+0:
+#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */
+
+/*
+ * Initialize the data cache if present (i.e. size > 0).
+ * Skip initialization if optimizing for RTL simulation and ECC isn't present.
+ * RTL simulations can ensure the data cache tag RAM is already initialized
+ * (but not the data RAM for ECC) so skipping this speeds up RTL simulation.
+ *
+ * When ECC is present, need to execute initd for each word address
+ * to ensure ECC parity bits in data RAM get initialized.
+ * Otherwise, only need to execute initd for each line address.
+ */
+
+#if NIOS2_DCACHE_SIZE > 0 && (!defined(ALT_SIM_OPTIMIZE) || defined(NIOS2_ECC_PRESENT))
+
+    /* Assume the data cache size is always a power of two. */
+#if NIOS2_DCACHE_SIZE > 0x8000
+    movhi r2, %hi(NIOS2_DCACHE_SIZE)
+#else
+    movui r2, NIOS2_DCACHE_SIZE
+#endif
+
+0:
+    initd 0(r2)
+#ifdef NIOS2_ECC_PRESENT
+    addi r2, r2, -4
+#else
+    addi r2, r2, -NIOS2_DCACHE_LINE_SIZE
+#endif
+    bgt r2, zero, 0b
+1:
+
+    /*
+     * The following debug information tells the ISS not to run the loop above
+     * but to perform its actions using faster internal code.
+     */
+    .pushsection .debug_alt_sim_info
+    .int 2, 1, 0b, 1b
+    .popsection
+#endif /* Initialize Data Cache */
+
+    /* Log that caches have been initialized. */
+    ALT_LOG_PUTS(alt_log_msg_cache)
+
+    /* Log that the stack pointer is about to be setup. */
+    ALT_LOG_PUTS(alt_log_msg_stackpointer)
+
+    /*
+     * Now that the caches are initialized, set up the stack pointer and global pointer.
+     * The values provided by the linker are assumed to be correctly aligned.
+     */
+    movhi sp, %hi(__alt_stack_pointer)
+    ori sp, sp, %lo(__alt_stack_pointer)
+    movhi gp, %hi(_gp)
+    ori gp, gp, %lo(_gp)
+
+#ifdef NIOS2_ECC_PRESENT
+    /* 
+     * Initialize all general-purpose registers so that ECC can be enabled
+     * later without accidentally triggering a spurious ECC error.
+     */
+    movui r1, 0
+    movui r2, 0
+    movui r3, 0
+    movui r4, 0
+    movui r5, 0
+    movui r6, 0
+    movui r7, 0
+    movui r8, 0
+    movui r9, 0
+    movui r10, 0
+    movui r11, 0
+    movui r12, 0
+    movui r13, 0
+    movui r14, 0
+    movui r15, 0
+    movui r16, 0
+    movui r17, 0
+    movui r18, 0
+    movui r19, 0
+    movui r20, 0
+    movui r21, 0
+    movui r22, 0
+    movui r23, 0
+    /* Skip r24 (et) because only exception handler should write it. */
+    /* Skip r25 (bt) because only debugger should write it. */
+    /* Skip r26 (gp) because it is already been initialized. */
+    /* Skip r27 (sp) because it is already been initialized. */
+    movui r28, 0    /* fp */
+    movui r29, 0    /* ea */
+    .set nobreak
+    movui r30, 0    /* sstatus */
+    .set break
+    movui r31, 0    /* ra */
+
+#endif /* NIOS2_ECC_PRESENT */
+
+#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0)    
+    /* 
+     * Setup registers in shadow register sets
+     * from 1 to NIOS2_NUM_OF_SHADOW_REG_SETS.
+     */
+
+    movui r2, 0     /* Contains value written into STATUS */
+    movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS  /* counter */
+    movhi r4, 1     /* Constant to increment STATUS.PRS */
+    
+.Linitialize_shadow_registers:
+    /* Increment STATUS.PRS */
+    add r2, r2, r4
+    wrctl status, r2
+
+    /* Clear r0 in the shadow register set (not done by hardware) */
+    wrprs r0, r0
+
+    /* Write the GP in previous register set */
+    wrprs gp, gp
+
+    /* 
+     * Only write the SP in previous register set
+     * if using the separate exception stack. For normal case (single stack),
+     * funnel code would read the SP from previous register set with a RDPRS.
+     */
+#ifdef ALT_INTERRUPT_STACK
+    movhi et, %hiadj(__alt_interrupt_stack_pointer)
+    addi  et, et, %lo(__alt_interrupt_stack_pointer)
+    wrprs sp, et
+#endif /* ALT_INTERRUPT_STACK */
+
+#ifdef NIOS2_ECC_PRESENT
+    /* 
+     * Initialize all general-purpose registers so that ECC can be enabled
+     * later without accidentally triggering a spurious ECC error.
+     */
+    wrprs r1, r0
+    wrprs r2, r0
+    wrprs r3, r0
+    wrprs r4, r0
+    wrprs r5, r0
+    wrprs r6, r0
+    wrprs r7, r0
+    wrprs r8, r0
+    wrprs r9, r0
+    wrprs r10, r0
+    wrprs r11, r0
+    wrprs r12, r0
+    wrprs r13, r0
+    wrprs r14, r0
+    wrprs r15, r0
+    wrprs r16, r0
+    wrprs r17, r0
+    wrprs r18, r0
+    wrprs r19, r0
+    wrprs r20, r0
+    wrprs r21, r0
+    wrprs r22, r0
+    wrprs r23, r0
+    /* Skip r24 (et) because only exception handler should write it. */
+    /* Skip r25 (bt) because only debugger should write it. */
+    /* Skip r26 (gp) because it is already been initialized. */
+    /* Skip r27 (sp) because it was initialized above or will be by a rdprs if not above */
+    wrprs r28, r0    /* fp */
+    wrprs r29, r0    /* ea */
+    wrprs r30, r0    /* ba */
+    wrprs r31, r0    /* ra */
+#endif /* NIOS2_ECC_PRESENT */
+
+    /* Decrement shadow register set counter */
+    addi r3, r3, -1
+
+    /* Done if index is 0. */
+    bne r3, zero, .Linitialize_shadow_registers
+#endif /* (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) */
+
+/*
+ * Clear the BSS if not optimizing for RTL simulation.
+ *
+ * This uses the symbols: __bss_start and __bss_end, which are defined
+ * by the linker script. They mark the begining and the end of the bss
+ * region. The linker script guarantees that these values are word aligned.
+ */
+#ifndef ALT_SIM_OPTIMIZE
+    /* Log that the BSS is about to be cleared. */
+    ALT_LOG_PUTS(alt_log_msg_bss)
+
+    movhi r2, %hi(__bss_start)
+    ori r2, r2, %lo(__bss_start)
+
+    movhi r3, %hi(__bss_end)
+    ori r3, r3, %lo(__bss_end)
+
+    beq r2, r3, 1f
+
+0:
+    stw zero, (r2)
+    addi r2, r2, 4
+    bltu r2, r3, 0b
+
+1:
+
+    /*
+     * The following debug information tells the ISS not to run the loop above
+     * but to perform its actions using faster internal code.
+     */
+    .pushsection .debug_alt_sim_info
+    .int 3, 1, 0b, 1b
+    .popsection
+#endif /* ALT_SIM_OPTIMIZE */
+
+/*
+ * Turn off the use of r1 (the assembler temporary register)
+ * so that call instructions can be safely relaxed across a
+ * 256MB boundary if needed
+ */
+    .set at
+
+/*
+ * The alt_load() facility is normally used when there is no bootloader.
+ * It copies some sections into RAM so it acts like a mini-bootloader.
+ */
+#ifdef CALL_ALT_LOAD
+
+#ifdef ALT_STACK_CHECK
+    /*
+     * If the user has selected stack checking then we need to set up a safe
+     * value in the stack limit register so that the relocation functions
+     * don't think the stack has overflowed (the contents of the rwdata
+     * section aren't defined until alt_load() has been called).
+     */
+    mov   et, zero
+#endif
+
+    call alt_load
+
+#endif /* CALL_ALT_LOAD */
+
+#ifdef ALT_STACK_CHECK
+    /*
+     * Set up the stack limit (if required).  The linker has set up the
+     * copy of the variable which is in memory.
+     */
+
+    ldw   et, %gprel(alt_stack_limit_value)(gp)
+#endif
+
+    /* Log that alt_main is about to be called. */
+    ALT_LOG_PUTS(alt_log_msg_alt_main)
+
+    /* Call the C entry point. It should never return. */
+    call alt_main
+
+    /* Wait in infinite loop in case alt_main does return. */
+alt_after_alt_main:
+    br alt_after_alt_main
+
+    .size _start, . - _start
+
+/*
+ * Add information about the stack base if stack overflow checking is enabled.
+ */
+#ifdef ALT_STACK_CHECK
+    .globl  alt_stack_limit_value
+    .section .sdata,"aws",@progbits
+    .align  2
+    .type   alt_stack_limit_value, @object
+    .size   alt_stack_limit_value, 4
+alt_stack_limit_value:
+    .long   __alt_stack_limit
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S
new file mode 100644
index 0000000..ce05145
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_a.S
@@ -0,0 +1,270 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/*********************************************************************************************************
+ *                                               uC/OS-II
+ *                                         The Real-Time Kernel
+ * File         : os_cpu_a.S
+ * For          : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor
+ * Written by   : IS
+ *
+ *********************************************************************************************************/
+
+#include "os_cfg.h"
+
+        .text
+
+/*********************************************************************************************************
+ *                                PERFORM A CONTEXT SWITCH
+ *                                           void OSCtxSw(void)    - from task level
+ *                                           void OSIntCtxSw(void) - from interrupt level
+ *
+ * Note(s): 1) Upon entry, 
+ *             OSTCBCur     points to the OS_TCB of the task to suspend
+ *             OSTCBHighRdy points to the OS_TCB of the task to resume
+ *
+ *********************************************************************************************************/
+        .global OSIntCtxSw             
+        .global OSCtxSw
+
+OSIntCtxSw:
+OSCtxSw:	
+
+      /* 
+       * Save the remaining registers to the stack. 
+       */
+
+      addi sp, sp, -44
+
+#ifdef ALT_STACK_CHECK
+
+      bltu  sp, et, .Lstack_overflow
+
+#endif
+
+#if OS_THREAD_SAFE_NEWLIB
+      ldw r3, %gprel(_impure_ptr)(gp)   /* load the pointer */
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+      ldw r4, %gprel(OSTCBCur)(gp)
+
+      stw ra,  0(sp)
+      stw fp,  4(sp)
+      stw r23, 8(sp)
+      stw r22, 12(sp)
+      stw r21, 16(sp)
+      stw r20, 20(sp)
+      stw r19, 24(sp)
+      stw r18, 28(sp)
+      stw r17, 32(sp)
+      stw r16, 36(sp)
+
+#if OS_THREAD_SAFE_NEWLIB
+      /*
+       * store the current value of _impure_ptr so it can be restored
+       * later; _impure_ptr is asigned on a per task basis. It is used
+       * by Newlib to achieve reentrancy.	
+       */
+
+      stw r3, 40(sp)                  /* save the impure pointer */
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+      /* 
+       * Save the current tasks stack pointer into the current tasks OS_TCB.
+       * i.e. OSTCBCur->OSTCBStkPtr = sp;
+       */
+
+      stw sp, (r4)                  /* save the stack pointer (OSTCBStkPtr */
+                                    /* is the first element in the OS_TCB  */
+                                    /* structure.                          */
+
+      /*
+       * Call the user definable OSTaskSWHook()
+       */
+
+      call OSTaskSwHook
+
+0:
+
+9:
+
+      /*
+       * OSTCBCur = OSTCBHighRdy; 
+       * OSPrioCur = OSPrioHighRdy; 
+       */
+
+      ldw r4, %gprel(OSTCBHighRdy)(gp)
+      ldb r5, %gprel(OSPrioHighRdy)(gp)
+
+      stw r4, %gprel(OSTCBCur)(gp)     /* set the current task to be the new task */
+      stb r5, %gprel(OSPrioCur)(gp)    /* store the new task's priority as the current */
+                                       /* task's priority                              */ 
+
+      /*
+       * Set the stack pointer to point to the new task's stack
+       */
+
+      ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */
+      
+#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0)
+
+      ldw et, 8(r4)                  /* load the new stack limit */
+
+#endif
+
+#if OS_THREAD_SAFE_NEWLIB
+      /*
+       * restore the value of _impure_ptr ; _impure_ptr is asigned on a 
+       * per task basis. It is used by Newlib to achieve reentrancy.	
+       */
+
+      ldw r3, 40(sp)                  /* load the new impure pointer */
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+      /*
+       * Restore the saved registers for the new task.
+       */
+
+      ldw ra,  0(sp)
+      ldw fp,  4(sp)
+      ldw r23, 8(sp)
+      ldw r22, 12(sp)
+      ldw r21, 16(sp)
+      ldw r20, 20(sp)
+      ldw r19, 24(sp)
+      ldw r18, 28(sp)
+      ldw r17, 32(sp)
+      ldw r16, 36(sp)
+
+#if OS_THREAD_SAFE_NEWLIB
+
+      stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */
+
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0)
+
+      stw et, %gprel(alt_stack_limit_value)(gp)
+
+#endif
+
+      addi sp, sp, 44
+
+      /*
+       * resume execution of the new task.
+       */
+
+      ret
+
+#ifdef ALT_STACK_CHECK
+
+.Lstack_overflow:
+        break 3
+
+#endif
+
+.set OSCtxSw_SWITCH_PC,0b-OSCtxSw
+
+/*********************************************************************************************************
+ *                                        START THE HIGHEST PRIORITY TASK
+ *                                           void OSStartHighRdy(void)
+ *
+ * Note(s): 1) Upon entry, 
+ *             OSTCBCur     points to the OS_TCB of the task to suspend
+ *             OSTCBHighRdy points to the OS_TCB of the task to resume
+ *
+ *********************************************************************************************************/
+      .global OSStartHighRdy            
+
+OSStartHighRdy:
+
+      /*
+       * disable interrupts so that the scheduler doesn't run while
+       * we're initialising this task.
+       */  
+      rdctl r18, status
+      subi  r17, zero, 2   /* r17 = 0xfffffffe */
+      and   r18, r18, r17
+      wrctl status, r18
+
+      /*
+       * Call the user definable OSTaskSWHook()
+       */
+
+      call OSTaskSwHook
+
+      /* 
+       * set OSRunning = TRUE.
+       */
+
+      movi r18, 1                    /* set r18 to the value 'TRUE' */
+      stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */
+
+#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN == 0)
+
+      mov et, zero                   /* Don't check stack limits */
+      stw et, %gprel(alt_stack_limit_value)(gp)
+
+#endif
+
+      /*
+       * start execution of the new task.
+       */
+
+      br 9b
+
+/*********************************************************************************************************
+ *                                        CALL THE TASK INITILISATION FUNCTION
+ *                                           void OSStartTsk(void)
+ *********************************************************************************************************/
+
+      .global OSStartTsk           
+
+OSStartTsk:
+      /* This instruction is never executed.  Its here to make the
+       * backtrace work right 
+       */
+      movi sp, 0
+
+      /* Enable interrupts */
+      rdctl r2, status
+      ori   r2, r2, 0x1
+      wrctl status, r2
+
+      ldw r2, 4(sp)
+      ldw r4, 0(sp)
+
+      addi sp, sp, 8
+
+      callr r2
+
+      nop
diff --git a/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c
new file mode 100644
index 0000000..86648e0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/HAL/src/os_cpu_c.c
@@ -0,0 +1,243 @@
+/***********************************************************************************************
+ *                                               uC/OS-II
+ *                                         The Real-Time Kernel
+ * File         : os_cpu_c.c
+ * For          : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor
+ * Written by   : IS
+ * Based on     : Nios port done by JS
+ *
+ * Functions defined in this module:
+ *
+ ***********************************************************************************************/
+
+#include <reent.h>
+#include <string.h>
+
+#include <stddef.h>
+
+#define  OS_CPU_GLOBALS
+#include "includes.h"                   /* Standard includes for uC/OS-II */
+
+#include "system.h"
+
+/* This used to be
+ *    extern alt_u32 OSStartTsk;  
+ * but that results in a fatal error when compiling -mgpopt=global
+ * because gcc assumes they are normal C variables in .sdata
+ * and therefore addressable from gp using a 16-bit offset,
+ * when in fact they are special values defined by linker.x
+ * and located nowhere near .sdata. 
+ * Specifying __attribute__((section(".data"))) will force these
+ * in .data. (CASE:258384 or CASE:362640)
+ */
+extern alt_u32 OSStartTsk __attribute__((section(".data")));    /* The entry point for all tasks. */
+
+#if OS_TMR_EN > 0
+static  INT16U  OSTmrCtr;
+#endif
+
+#ifdef ALT_CPU_EIC_PRESENT
+#error Nios II does not support uC/OS-II if EIC is enabled.
+#endif
+
+/***********************************************************************************************
+ *                                        INITIALIZE A TASK'S STACK
+ *
+ * Description: This function is called by either OSTaskCreate() or OSTaskCreateExt() to
+ *              initialize the stack frame of the task being created.  This function is
+ *              highly processor specific.
+ *
+ * What it does: It builds up initial stack for a task.
+ *
+ * Arguments  : task          is a pointer to the task code
+ *
+ *              pdata         is a pointer to a user supplied data area that will be passed to the task
+ *                            when the task first executes.
+ *
+ *              ptos          is a pointer to the top of stack.  It is assumed that 'ptos' points to
+ *                            a 'free' entry on the task stack.  If OS_STK_GROWTH is set to 1 then
+ *                            'ptos' will contain the HIGHEST valid address of the stack.  Similarly, if
+ *                            OS_STK_GROWTH is set to 0, the 'ptos' will contains the LOWEST valid address
+ *                            of the stack.
+ *
+ *              opt           specifies options that can be used to alter the behavior of OSTaskStkInit().
+ *                            (see uCOS_II.H for OS_TASK_OPT_???).
+ *
+ * Returns    : Always returns the location of the new top-of-stack' once the processor registers have
+ *              been placed on the stack in the proper order.
+ *
+ ***********************************************************************************************/
+
+OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt)
+{
+   INT32U   *frame_pointer;
+   INT32U   *stk;
+
+#if OS_THREAD_SAFE_NEWLIB
+   struct _reent* local_impure_ptr;   
+
+   /* 
+    * create and initialise the impure pointer used for Newlib thread local storage.
+    * This is only done if the C library is being used in a thread safe mode. Otherwise
+    * a single reent structure is used for all threads, which saves memory.
+    */
+
+   local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent));
+
+   _REENT_INIT_PTR (local_impure_ptr);
+     
+   /* 
+    * create a stack frame at the top of the stack (leaving space for the 
+    * reentrant data structure).
+    */
+
+   frame_pointer = (INT32U*) local_impure_ptr;
+#else
+   frame_pointer =   (INT32U*) (((INT32U)(pstk)) & ~0x3);
+#endif /* OS_THREAD_SAFE_NEWLIB */
+   stk = frame_pointer - 13;
+
+   /* Now fill the stack frame. */
+
+   stk[12] = (INT32U)task;            /* task address (ra) */
+   stk[11] = (INT32U) pdata;          /* first register argument (r4) */
+
+#if OS_THREAD_SAFE_NEWLIB
+   stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */
+#endif /* OS_THREAD_SAFE_NEWLIB */
+   stk[0]  = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */  
+
+   /* The next three lines don't generate any code, they just put symbols into
+    * the debug information which will later be used to navigate the thread
+    * data structures
+    */
+   __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext)));
+   __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio)));
+   __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr)));
+  
+   return((OS_STK *)stk);
+}
+
+#if OS_CPU_HOOKS_EN
+/*
+*********************************************************************************************************
+*                                          TASK CREATION HOOK
+*
+* Description: This function is called when a task is created.
+*
+* Arguments  : ptcb   is a pointer to the task control block of the task being created.
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+void OSTaskCreateHook (OS_TCB *ptcb)
+{
+    ptcb = ptcb;                       /* Prevent compiler warning */
+}
+
+
+/*
+*********************************************************************************************************
+*                                           TASK DELETION HOOK
+*
+* Description: This function is called when a task is deleted.
+*
+* Arguments  : ptcb   is a pointer to the task control block of the task being deleted.
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+void OSTaskDelHook (OS_TCB *ptcb)
+{
+    ptcb = ptcb;                       /* Prevent compiler warning                                     */
+}
+
+/*
+*********************************************************************************************************
+*                                           TASK SWITCH HOOK
+*
+* Description: This function is called when a task switch is performed.  This allows you to perform other
+*              operations during a context switch.
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*              2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
+*                 will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                 task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+void OSTaskSwHook (void)
+{
+}
+
+/*
+*********************************************************************************************************
+*                                           STATISTIC TASK HOOK
+*
+* Description: This function is called every second by uC/OS-II's statistics task.  This allows your
+*              application to add functionality to the statistics task.
+*
+* Arguments  : none
+*********************************************************************************************************
+*/
+void OSTaskStatHook (void)
+{
+}
+
+/*
+*********************************************************************************************************
+*                                               TICK HOOK
+*
+* Description: This function is called every tick.
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+/*
+ * Iniche stack has no header declaration for its timer 'hook'.
+ * Do that here to avoid build warnings.
+ */
+#ifdef ALT_INICHE
+void cticks_hook(void);
+#endif
+
+void OSTimeTickHook (void)
+{
+#if OS_TMR_EN > 0
+    OSTmrCtr++;
+    if (OSTmrCtr >= (OS_TICKS_PER_SEC / OS_TMR_CFG_TICKS_PER_SEC)) {
+        OSTmrCtr = 0;
+        OSTmrSignal();
+    }
+#endif  
+    
+#ifdef ALT_INICHE
+    /* Service the Interniche timer */
+    cticks_hook();
+#endif
+}
+
+void OSInitHookBegin(void)
+{
+#if OS_TMR_EN > 0
+    OSTmrCtr = 0;
+#endif
+}
+
+void OSInitHookEnd(void)
+{
+}
+
+void OSTaskIdleHook(void)
+{
+}
+
+void OSTCBInitHook(OS_TCB *ptcb)
+{
+}
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf b/FPGA_nios/hit_pat_bsp/UCOSII/Micrium_45_Day_Evaluation_License.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..de49fdaf14e49ea950c6f65965e95a95704e1dd7
GIT binary patch
literal 96321
zcmc$`1yG$$w<by;kU(%J*oNTF#v!=7yE_EmNN~5{?i$?P-QC^Y-8~HCpYQy0&P>g{
zQ+00*wRgR}x_hl&EmW=j^s`=K837?`dKwm(u+*&Tp4q*77$ATSV5Rp14o00;l%JnZ
z*VfPg!0=WlrwIpRXld}b>0SO?`2HOZhE~Yb+|CdLpcOLLwKEhj)VDG)1iV#C7+M<J
znE-%HY|QVX)SDGJ7%nb27+X7#p{@lSjAKe_+)oAh1@wTi7M2#7D8!(caWfM+a1po`
zkw_W}dT2zk_6RUSW&s6j0olmh&p@(u&n*7P3c?`253&_UAF%|cZLCqT<3tTgu-2NL
z&PI~g@bBEs(p$z>jL+O=8^I!;eIPp}RG>X!GgVMG_Id(CgN=1QeSkd&gD?kMx2~$<
zL%$aSPXu?J4>3<fxyNW}ga<r4QA}}%bb!64$26!C(u2t)gzR13FKA$446t%4rx4dk
z4<ytwN{-TrjS{MQ1C^p}FR9dBZxam>*sg%S-?4^lM>h@6x0gw`LfMd8Ln3vsF!ny*
zHvn5n^nL6^{dsz=wkxn)rI^9UqLyiPZRHKjsr94CfZo(wPGIXI1KQ`4v?{}6C_@N6
zqr+-6$V7R8SR@+q{-Mz*!5d>^l6%2D!*uX0q2D&?=M%A1aW+6;Mq|&as7@AGm4qDg
ztZb}w7StB4WYZp+&&g4D4slw(9;a9W`1f76%I=A9VCA`nH4Bdc7N%%mnnxdGnqC4%
zbZEhXDqHR0-E8n0UA5%8H>r#%i<Xx)#6P5)k<;#<J*LBZ@N2t{$+fPW?dUpQMYBfP
z(erDuSQ<I!3Uv36ZdyOU?xqLa<A3^NkB5%*Ow<}k8zU$%lq&&{h^tZWM+t;X<n!mb
zPfxl>==zhr&=B`)@g8YBP6a%N;46<i9vB$~5&+u8fO7oI?MtsP#KTDNL}Ehf)0p=k
zH|2VXKmF)L9%1^z0>FA?+0o;qXEks}0GJ>T#32v%J_Jhp$J%zJdN71_2ykAqz>hXM
z^y}WJ5g!Bq7^t2#8JIENB|4<}Q1%%}j6TfPn08+J>x`_QXuO7WJ}!Tdqk~WLBtM54
z=0WuJ>qkVB3$O$5_v2LhsYGCJLqPH)$>79%Cg$f80Y~FG%8<*)DfB<gG}>3+C$sz7
z2nNSrmmzC{{D|iK=^Gt%ZiiYqk~w6Rjx_7%Fkg(0fpZ`$K8<%>d#p8tE8?lIbXWX3
zk_rsBS00ilA`<)WU^*o9P9eTXM<Qq>f}#lIY;aSa#R$A?{DvTr$h>}aR473~dKrnB
zFN64Kew)AJGL<r!vkGND$)x6UO)E~5{eZbak`yxgJu)%64`xTjj+GirBcz;>JdV3x
zwU2bo`iKVQlc^s<ABO26fkT2;1zv?!g*_F<=7-fAqMKWxQp`S!a})&E11i@ur>})^
zL3BZOf#e8t^ZB-EXI;yxt?^wdkg{8GUCo-*TG<+<9;+F774a+tq37y+=)&+`$Q8l;
zGj~`z0U1gNbg8chAB8S;X4JS4t9ZS*BQFv1O`ue_^>5F5e-+X10^g-^h+BzeMU04;
z$-RgOEC^0WQwdiHTL94mLIwz+@2V23e3m5X1Z$*ivKbUA6d%dXQI#mC$?PaJWF2z@
zl^GST6*P(y%2YBP1#Cnv3Xru1M1GZY%c|ulWZ5Yk_)k^?6&Hlq6xjHkszAY)kUPSt
zR6T*4{2Q`CWKU$qWcmueh0=!d4b%41LWin{tZ@7cxsc;>ra9GCCO*~VXhA`#V%1`4
zVxfaJXymw=*b@-@2iL$y-ADUJ4n=B3X~ot<k{RY1%EGdl-F&C~iy5)$#TlXL)dGfT
zx9O?rx`LktYg0U?38ubg+dqycSc@*~;4Q+2a86UA*aG&JXMLGQ7{4(po19MJjHk>_
z&R$LpP8LqGXWb|ym!4#%7Pjy|`QB#3EA~kWXH@a;WsmCn!*oSQj^-O&)92bT*}vEm
zH{LY*G%`5%I?FoyIiEP+T|+-oy%4?NKDIo{L$N~<KtV#4K-Ixr_)~SEc4_**_?Lx-
zgzAMbW7=bJ0+krx=|)*BnOe>Gm~B{8jV5(KBdGd=KuLxb3+Dw`<|-C(`XYL4V896O
zFywC2NC5RXx)eHJFjO$M1oBjLVwbsLnA#+@5A_%7CaQE*ER`O0i>kxAM-vOHRLd0;
zw?2P86cc%qDgCRWl0@pc+TPnmjZ2NShN3-(F*i$N%f7lL{hw25Kk)V1I$G!c`1oY`
z^k<IfPENGbPgKlaKn3^0=vx@2{^a9uVk>cA-@Tq)=uka&oqxc<$Q4f#4<5>L>b<(Z
z`nng|aM%FSIMU3qgsl^(Yq6C3srfU^#pekE!3`lzIJ(a_ufVu)k9W*iYgUV}48Cm6
z-1t`PmfWg)X{@Q+WjtULWk>$Rc1?MVWub27=iu0?mERh<N3}=9EAuP%2el8&p1Ym}
zJbmr4UT(bE8IZg)ya?VS-hv&R1lA%t{kIWKS8#h@_I~<#k9&@vWZrd#bjA6(;fFyZ
zd?|zWz|=*NMVx5!Y}6U>j)N>CY#|&XJQGM15dH0(g_ec#J2^|c&#^D2Pei{&Pq|ks
zXetn;+rCeKD{CuxGY{jDYPrGsdk0r0>&7GDmY`EG4b`klO6&bSau0C|u`u$)FZy59
zzs}e)Q=mq#Cp~j&#PjOSPian3(mq*zvWhwzq}`JyY9NUv<rH&}Tuu9)xS1vwd8yEj
zuJ9!-?=f#Sr&a2U<Wl-AIVVXACq#T?f{lU*QZDopu!i9Z7*I7_6;zcyloEfU!AuN;
z%w)*F5M0^R!?-Xu?b$6*sRc~hij$ANB4J^_6G;Q5(OKy<EL=(skzTr8wP|^&b!bkg
zXQ-Fg>e%J%4L&N47v>Z>D<757sByOTT8((s_|}-3d5~4pP|><J&=_e-M=DJu{jRui
zKT;1y3li*MVXimNUkY3#n`f;zJ<TnY#20rY#t<(NrxaVW+O=%Gj~!8t)plEqsx~Yi
z&NLrW8dlnvJz83>!zELu8KcEt!mDht{iH8E5Ejo7f7~pit1Md=TrOTIu7;(tplK*m
zQ*-EMFLommsx0YJVsw(bIM?LVRCatZKc$qXsH}EpS*CL~;@tK)3YFy_<d)#Z_JqeQ
z#B%E~^4QoQnpIGJ(B;12e&7`d;WiRBGD4k1ZCGMmlx=^h)7de!=IAlC(raF1l~)&!
z2OdBafaj5Xe{$2s8{iUN9#-vUe6MNosU|BM<xpdlZ6<b-_$2HIkL#;rbzNUh-j>VI
z*&Y5Ar;@G4j^hG!=da%==~BDtDO|DkhX)7SQ~E99&SxpVIBiR4o2|~x#}}^lT*p!m
z?vA;gR&SmwzKmjoX&Go9H*Q-O*tWZ8Y<+sdXNSUt;t0SAXr$%PJjF_5aor4hik(t!
zDNAcYw?3Kde~#QZlAW_!6{#m^8EAUgS9&bjtFyHnTUNEjaI4!+n`{YsO1i^#XMCy9
zJOprZ9dfdt>vZ^V=r320avQ#0yEpF>Jm~iLjtX3TTN3UgaU-SW*1C6m7M+bw%<JK%
zeARdw-d_0G=J*VxL*rojqjCK_RhF!s-!}g`d1`oOH-G)2j8$f&72hoDVY^O!WbxXR
z@Dqih;jH3}k~_hD{{i#*;xsQrI^7-O&iCr+Z_N2m!1z!2$@rhbPkvqi{d<6^;ACwG
zpcQnq6PCAo3q;?m^mYF>y$7BD=+e{wC*}Wr?8?Z(`acJ)Cz|5X+pI{fC><X8x>(LG
znJvz$wPjS+>y5VhY)HJ;o?me8pR%{*xN<6+mf)I@aEuCzhKR)zwcQ`0me<_xTH0QA
zwCk*fj()DKxj*foPi})+8<v87(l=&STA#OWPw;n>+uR<^+|DdtABSE7&e|x`U$4+}
zExy#1OIkL#J*=EaYrn3i_;~#J^Yygs;!jfAo~i2A+~L;4pQN+0FB)+#4sF9tPemSK
z^41M6kAEyY@R#$Rj-H#PxM)u*L+;?+leU)K+xjPbT%@Lul~R_j#M8i~ep6?<QQsS@
zxZd7{^Cu5qKJU?bG{5{A8uPd{%6xPJxmU^EgoU5X4dhthFO?bhg-z93)+OW-UuAZ=
z*%P$9qC;Coa?~ZPabJHITuXL?(lHlT_=+%e_2qfB1WFj$J!6nDr{u%8RoY-YMVLFu
zU)5l0_HY>Vfi3};%$BlV!^F>*L*GX-;n2@O;n1zj!evV1x$8#t#;}iD{`a+r_+Ss>
z=KW<ymnIe;uUl<8*|jGbtr}kKt19n`7+4XX^ll0~;iJ5YZYwtST=A%NldZ_5Z8x*}
zu&xg@O{}oFeZ9RAt9e-%1tKi8l3{)uREBjnLzE_k_6Gfl7Vid@XGh3XeI9^kvtal}
znou<6pPc4K5&TCjjBnfba-=5;@f<|W+Z-zD-oT5szVU*(YXP7uZ?y<gErV@HqXPFA
zZ5?TF8~r@<sXkPwLf7L{oj$m<ToZ1sc3yoqzn6DyTqf(z^zZt<k{`t#(9H-`wzI92
zG>WsyYR&RA7HwOkxh+g5YY&jc&bKEtM6lDmve!ISCzhWta)xc7laq+TcKx8&`(UQ#
z)M#bSYGFVoxw|rzg2H4AxgRsx1tcjlQuaDvHuPy|zoa3@cW2NE#mR2h2{NAU2AtE3
ziEE>PcbhwZ0zgS!4sF*dCjX$R2v(mMavT8W-&2jx*^mxZ3&D9<@|7{*dyajz=vL5b
zi{c@E2H!+4p#d-bNF?NpTZ6Px;N(gdLJ%a*iOFzZs?$-V1|cC=2(=vzk^_W8=oop?
zY*Rzx2Ryp_M?@2Oe~`h)gB`_KWV<gRI&tk)1?&CAcBRAY9b?<SNMcUZ%bSTPp|VC!
zpH?k$q?EmpdQB<Rq=Tbd=Z$S6>5Bu6l$qk7PR$;3=#DO_`9$3&N0s2^H#<^v(37(m
znyVn7h=^&xOhGg+66tLx<Yp<Q_8~KvS2AYgGRw6DbgSBD2ipM<$a}%%6`=8ZaMMu+
zH9o<-TpEQmM{_{R(J&5tmIVe6K|B32+vaT72gdDBv_b&}619ST;>K3|hJq%Ts0VqQ
zV+sN($*zARxvM%I&@~gY5xF#EK9ImYV@?Lz&ve)bpV6^jA<WJDfY{kpfV+e!;AYH@
zxMN)YnTW~VwYp@{IalcLh@#xAk(({_jjtk0-mLUv_?GIBoHUu3qq1eAh6EQFfEd>M
zkV;fjoT$|DVCRdn!(t=cq4pn+?OcGz+an!srj8C>S@M&9_L<^7hb{3P^YF>EdZ&G$
zzE5N+#wp2<&+UDEUlxp?iN4bkR^q4Y`bBjBB!=_^TmbwheJO^)d<zM#0;)<*7G45c
z?#yTnlO!LuwG@I%Gb6=w>!nPWhEdz}lFBQMf{<eqn)!puucqz3QRrmt7#ZCXSHVVH
z5<*elazO)o&F!IZK_vL?H3G`pS^WrPjUqj1vpl1#zuk?}pB^3{5n1jq>S*1r<9;Km
zF<nKIKt^6#9-z*;vQz$&pd%U6YBY?WiWFkOxTd<>+77$EVV#V)p1!#NxTQ-R>+F|G
z3Xi+yor6+S`{4At9a~bdc~eCe7k|PRdj76105PBXLaCZ#f3_ZyKXAYgp}d8;2kh}+
zvZz3LfjCVSHUNyF!3|C}pYe2QJ~ZwVNeYh+wjEcw5;lybMvWB}mhFouClA8B0Kl^c
zh8w&2XBunerYG5DTar11^faZWeE|0W*D?a+BCOCKUCL@&s___tc)0o^`6zSHg0fyP
zq~w^F9+94Rji@z{5!UNO7>Y;a(=gu+Z}{B87b(SvA~PsHno{JLES2Nb9sGVw<rx(`
z?QG}Pl$Y@9*BRi%(S(r)SS|pY&F|U#!f{$h@lswpZ{eOnpAiRs?FH?bKk=U!8|K)<
z&L_jkp|miTJeE}MzQQG4Y;iW(LDij^*_q7Gsmi<_WxUwRI?$OAToxV#D6ImB)SWkS
zBqGV@b5aTUuGw91hzdGL@;H0+M;3+{=`}=1=%viUdbNDn9+%pz#Orf#EMGleS7PMc
zu6{ai@i?BhYT3U&Sk<+y-Zp&r)$5q9&T7@SlmsK`8!Bx^62nK+oS;da&w9_A{|sHk
zD7gn=h>^ExVO@Ii;S})~+w#>H$3iq*9^UU3Q@?L{Jz9y0RXQYvpok*A`HA12It>n>
zCOvW_tY(8DEI6zdLrtUS)`hj07vUx!3x0*kY9Dr}IasGZY__Nu6#21(M~V^YQfXMw
zp$2ViH6x=|F^woE5Bf1E1;%`5Rk}tYp@f{xx<ii|YAg4VR{nsL&Fwg@cXQwv?}Mht
zc#Crtapm}_Nn+M9=+^oQlG^U|9-CkNEGI3h@rzJM?D18h$zm+3zLwA+7ILrKtyJ(w
z+E3qX8tEBEtA~zCa%aU4^_BEzVt>di*aWO{3?4nb$TlFIS0MHp$=uWECGCQsyZJg>
zP#d#<A91id7Sx3|67nxq`};$nqK*`=<wx@#p*C~3iC<sdbZb7$aYI2L#_e1>#r?wj
zu%45RXG3R)4a8uVB*_j!1b&#39V{t00X|Xhbf2abL_QY`|2ZWuMwBW^B{zX7s40(a
zM7Aw}wM?ejH#z!R@1v$1awNjw#R$>i!%{Kj<$4SI)364)oi}$}JE8m%JH|YQoJM_L
zx}piCi`+`m@4FKM#qXM<;Bpp_+-X3Ev-smiRjsrd%eOBW0(I@=-*C){Bfrq`W`sh{
z4uryP+mK~&+Jr{iQ@LQK41?_XgD*fSV%P&mBlKI3tnP5LO=-n0Z2`#O25XhO)EE?j
ztBJ^$9;u){p>|jCgZ*NoLcJd<;9Q&-BBe?zZb>7NAM}@V3QnM&ed2!>O>^F<Qa1R^
zcUK~~4*zTkbmaR~XU{m8J|5CD-70%!RzEFlA*LhziK=?lp3$8qdWrP;sIZwY(S72g
zDeE%)bHCIM`>@f7QgkL7IG5?wgkPdjki42}A3JS7<C*_i-t#vx#tXa@YH8wxYDhDF
z_s+%KcCX!QJtV-M`R)8+_Y9~JF47~bTsFDtF5*-)EH4#*$x1%Ztl_NOHR{`}onuze
zhDaI&MZvD5K()t7=FqM`L0b`jZDuO$B*(ZyXRSlugt^XA^6!2KVIQE{Lq{n=fwoR&
z=CNX>5hG3BAe*9j)l}e|lU?2@Q|N|2!-juJ7P)2{qT`dD(d^Myr?SnA!|bRwaYVTk
zLBEgIH!dr%nSQEsZK#R8S4QN*uxT7*)<kUF+vJBc?jr43`WjRG9QD1;TQ6*8j?ciR
zfn1mN8O?>m;K=d?)gpf^TlE6kB*x87Ofb2fg);P3<!-Q?zR0*R)8}m;&ms|hq<~^=
zRK^<`GQ2x~cM5Kiji1pAzo901xej+XiTARxbdl&^r3=mrEgvEq)(~n6V^r@zfp;3W
z`&3wE3^Noli1}RzvyWob8bbt2jV6rR-2|pVTuT)mg*YH`xAtJ7Sy_(HeuT=}^7H5*
z?$inv?EO$|Yx^UO*{7v(;mKUUcnPQA;$1Pb_~Cxe6ys8E2wG@X?t)1VLb9nl$39OH
zO5UOgzS8D#t_HcEP4pEw1gwtds@{o(>|BP8TI{Fn!#qfY5(E@O<8E5y9f*r?XF)-T
zd4&6VITNto+UA?r-5ZpJe$~NtP#eWb8mLx^7#)LF{Qa9dW_#;P<vPXTu~auYzOD+R
z#%xvmM_*Z0Z7LZaWCLXRTg|_3*2oaq30~)dylO5%&oQ{<j*7R|)eloMxPn5#$Iyb!
z6ui=8g)e$`M!Efqr=<fGy-23?Hr-Tr=P4rljM@_y`|+KtSwL}x>4o+T@_A<V?%rbh
zBW<HNfR>Pzb6*rNE64>G4cnMwA67I&dZ*25$RljW8UFQ2z{>DLj%2|~O`@eyyqg?@
z9PgNj_~*dIa*3h^Te_lHGIdwKIAyz(Z;?ggD>8EE&GX@6X+gMD&Q;_<3AnZ;BR+ZW
z{R@FFU_;-+D=n(?8?I)**Ha`T1d3|QoQPQlnNDT=*%$=Hr*FO%X$Ek7SgjWq#t_GC
zBIo?Nv6#~P2QPfR6$p`0<!p#1QNWW_#gIqV6!{(ZI94*k40+I=84T}caAeb;=>w!@
z5YC(_e*&k;MjYAR4DRyK@dEEM!M4r(ZB4RNm^0XK%8rn=3U%b>aE_7RpL2eOic#HS
zkL=@b$4kiwFYvQCt1Pu9lFgIU!GGpk`DTSzHZEy;5@~R*ip`YwsV9RycK;Jjf$=VW
z)N%&YZ<2(gFgNzwvftmnM|m_#Y7q{jK1g}A@;;SthzfkYFYG+cJhB(>OQ~PeAK4^f
z!cB~Y(N8d9Z>@>h3lL&ow;7D)PCK-Ga8K5V_=Ffk)RLml31`)~;#!7ofpq)BEg^Hb
zr2=(G_a;lARe_)~Tuio7zR>dMv;7zYl2B8KCnft@wVIYKuApD5H5%^E<pI%S!3#>2
z+3yN@iIhd*F%!I!x}TvW@Ryc*X3@VkCrk>37a$^Ji3!2+PTDX?<V<=Fc#^Fh=@+xs
zB`r)SF-fSOmIdSBau~$+&u5i;69H*io&;WTI%7DC24XjnIR>|?U5+M<0lDZdeleea
zZ_@3OI$n1Q092HIW&Bu@{H5o=oTuwIJoGtp8p;3*pNR^`dI-;6Ht>gQb8dm(uEGHk
z$pRHtVxaO`*(Uf>7U%w_StK;+dMcy?gL&SoxLI4fWSSfo>o3AM*4=HeF_dPbHRb^L
zI8(gwsGaj9r53gDy=&=DMzFR{0~(LJXTqjVxf_l4I!U3fjZc+~_QnlOYB|IRnCTuR
z{P%<oHK*$5iXxy_CrI(6ILFzq3H&)Nleb(?ab~>+`+65g&0wP6$-?nW8i`OEf_wmh
z5ve5vJ<KtK=2{a?ne&lyiOi<e`W9d1_r!R{4yK_)#&_(^Wb;T<9}-LF_z=_CiB+_?
zqx?(+iHcM6aICk2DPYQtGj=MnRjL95`+&cm4D5FSmrln!HZr8(xVtU*1w-|bw>7)y
z1s)wM>tKmL^TJ1H?Gyc7h;?C<0+7<+R_aU}s;(p-*!+Z;KI}lIEIx-wM;ZGpL|j@#
z<tCg1oj)A8YdiZhD@sj&O$gJhH;;#{#u01#^pOwYhjOi%t4jn@PAyGYn^G~EexI6t
z)D$MInpnFDHtu2{e@bE&Ef8+%MxSbA-=GW?L$%!LkZgfB1*zk8^eZKX!rsx^&c5e)
zgjWw94XzC)?vR!8R9+kb)X893(E2aV2;&$OJRUu}LoF9u+FJ5pl_+AIBvZ-|w?$OT
zSf=&K>F6(ZIK|*xwV~=U8TOcPF<+9F_s>U?ztt4=mwZnZ?Uw4wkj8a>Mk4OWVh1yH
z`&QtPP*H<f(>I0t*}hYaLpr4s5_LTnlcR9*ZaQ2<&&GMrZi7wm2H9kyOIzXirtw*I
zFVjCzO`mu!U~F7lAZh1XqS!K*vzk(6#8nlFi2mDsq&+^@G-gN>z5y6}>`zrZg^hr-
z14|5`^vB3+IS?^5n$`6ewU-RTP#<2YJ}KWW@TWjX@vWxaiSLV{2@$H>HgO6D%^r(8
z_U)zkD^8OWsvL3oK**-Yj1EDo>1l^k#i@|O01){Tip#<pUesaALfJ!lo3jM6%Wg~P
zXo%|C=rEAI3;MCFlucFnOjxI87AF_gKB~~^@q<r^`IklgD;}F4jz(-Ieh2kxCOkZ>
zEkQV)+dD?6<gEm0Q1zXda-y~#jHI0H1>uybZSa^(ut4%Lk%E-bp3tV;GtYh}$^4#q
zp6}Ls-iM~-u}>vgp+l%}MAT_vBGfqk`nTPQ;T9{f0&K+zIKmj%uiwN^wzA@K*vDmQ
zpZvTHx-{H?&MNll#QoLhQGasi@mih)zjGNR3(pX^1(tF_(@)y4q1l=4W_K%3dx775
z=ig-r4F+($HkUwkEl1Clts>m*n<186jEZFt!dVb19tyRZ4VeNJB$|b9ig!x~o0{qR
zfOe5G(<n#j7j3sk+5=dpZLWHCISvS740mRz@fDwoLtk#<nXyJ!6<l-m{39G)3^L<b
zxum`gFqukkeOg<CK1oJaj}9+OpXn2NhVpnEcDQKK;923(krEf`f97s6rnUNC;%D^#
zamV}j{+8d$($3J*&KB?&8<Tqn&Lj;DOm+FJ90BTdZ*UniJ&=a(?;n7L?VqCNdp{Xn
z(3|EP$o6(W{4UEG+FIFz^bKtR-@nrez1jWyWCAe#?LaHU3Sj+P;^G3(%A4pKm|7aY
z^>~+LbnV_QkuCqbq#~{N!%+WS`@N0d%G?ShZ>_6u_->A0o*wW%0Xe{X+rRO?w<ckE
zI>0+PDEHR#_IY#YU!b6juJJn__@8jV|C2jxCML#ri19yPUY}@+R^hPy#Q{z92%*}1
zhSYwfet^PUZ?|{dvPt@EsgdxC@1?L31#DA@D{R^^PF~-<Jt~#Uk!!HJ+2~6@-r3Wp
z!Qb2q=hpo5e4)3Z)7+LY<bv`CpKD}itBn@_Pp#JRTj92CWG6n|>h<BE@BYbyW~#ho
z%W%=(dP1A#)$#5}h!azEi+kh4qp77w@`WMZaBb@rxB49r&N9(bdnt0wFn%e|>uhST
zyKGAucXRQ!w)(CveHX01didbzx|{y>JDfYtT8ED%0v+B5XQwteU2Idfr_E)$r5#)_
zBdyg>z830_?rU|TGTA$y)pm99P}H6U>TWi6((zy2ACCI8Uk}%hbGxc+jZ``{9UW;-
z26I+go3)`ho|>_tYQ&9C?u|G(YQ6}U+dmUV-^S5#<O+_NUnK~vuuCNSS$wSxkVr@A
zXtp^>aR7~viRK93Rl;sHck&+(BcbJc(+iT+20B<F9~dpB+=FQFr%tT!J>fh)oHX(+
z4wZ*~;TmcA_^i?`ynNrNI`61Ez9+p$!UHaW@~x9XBT?G8wE=g^P@aqjIJmhADbFz)
z1E0vbT1`Xg83Di6Ws^}3ik!?9J=WRI*tBqWhrVB)h5JRia&~ojMCU>pxV`i8)x_$1
z9AjMCm6KC|i;=l}Hn#Z)875_3S2~|>1(R3x@&Jm+8VAe_djr)fD+Mx!^ZgQ-0$fT;
z?kAP81+bNRN7i;tGE_+W+XG*ly$&av)fX(5jJS)Fn7SSXcAZQ*ZEz|Lu2QMUz9)yE
z@4Zc3U1Y&9-ezyGm>c#pMdZ!*sAEjjdLB81>wwrfi)itz!XS_iGgie=aFtJ;;Dz8&
zPl<RcTV>1u`fR2Ol0t%Iokpr!D@6kp*>@}a?1!Mo)K6_8WOIJ45(-E+yZ(#pFXn`P
zmL}IK^2Are+mJCltFt}^!x5jp3_&^6Ee+_yKpABu>3!ug(LwK?qfc}X53h4jNts(8
z65-pfKq3AlS)tVI^HHnXb=IcjjF2|05M{J2D<auHQI!-;F6;5iQXHXtuJ$}mmqy?&
z&~Gm;goqHp&Wh#$Bh^DFYeXe)0(FZzPsvkfe!M5*z;!R1DC13xNS2A{pDPK@Ett~?
z-nO$PcAZY1?-Re_6HmX<dSofoBb0q9TZ5Fvqi&9FBDaSE9gBX^AJzXPT4+QOBsYZ^
zV{1&SH#<x{%Q$SsQwBe5A7crJ>pvNtfTO4@@190U$S@_*LAaNu$(T$}ODSkeOU?kV
z(GQ3vQo4{xG}zEI&k4O0VQ`T3Sj?0+TPaLgnaT`zoQ=L4G_<~6{QwWlq`#`uRq&uu
zE)8sLm!AsM**StWhj+i*H|AxPSX{h8p;_cg7lb7$ZkNVNOi3RvIV8aJ%}k?_CQ;wr
zSpS%;2+>0bn;4!TPw$;jaJGKJN9ca8foB)!2U)U@L*vG_%-Z<zn+_V^rvnqA%7p5W
z(=3QNUT$HR1xe&0T!dkNmxW1U&p~U?iGqBa<&-Uy=|Oc#k})C?*=0%)dvPOtk#IcQ
zpqa714TsqvL^2Dm&^b%=WloqYz3$?v>7v5*XXYZ6&wX)-a>cQh#-64(p8Exv6{zHc
zK5g{~ef@vr4ZrDlq)~Q#`<cjo&~Xk;n(Bod<aP(0%9aOqo-Lj0{z!4phmS>e7=9DK
zvBg|`6e&q+SEXxHo&qJyhs$T!XHuRjv~GyxqH%xO^oOd>bOVf!e5w2a$x%Z<!gXee
zxPj-ZOu>|oWh&I6dcXv2(zeMjdcJBo1hfjYov?*Vr5t1Aj0Bi^SeWzJZUXioFjEmC
z#7n4IUHYV6BAjwaFmykNpe2tNiC>GHf7B$@bq8w&q`HSfJ~-o36}EF`X~*&-L$Tnf
zfp?8jd58ZN9Pg(|98MYO*YOPK3&Vqd9g%3DPr<2zRgsAl;r7hf6%FyR#U!D{`I+Pe
zp#xv#rYailnrJ|$eyAHn=ew?9eQ4@j*|~0EVRvk_S`hm2n2Py49~~T5`Hp|OIab%*
zP25qRupq!?y;gUTS+tB$+mZcaQQ9dw-h>znges}6X<Ji&JuEDo9gSeseOH7c=XZ+X
zSbfkTEq$CWp+7%}2=E~8N_Y6Wn%rtg<1@tTo>>O-sG5{JswU@g^KA<AqXQ-30gEPj
zS}r7p`v_E4@?mnJ-2S10_J%}jz}L0(k;VqfpPxl(KTi56t+B8{v1q$_Mk!JlQ5ud$
z9mmaDFtKGVjPrc~ZDA69us09hn*bXB(#BRS*wl9imiz?vFG?njbbQW!&ZeC9bukKK
zMl}sTA4jiBMjj7i#SF0i($nGoHI42ROaRyi=G!tc%|bhhz=HI;bU!vze_Mxdac|Qw
zDJTW9vGpcKxr03diPur{rb&~aBxc$huW7Y4KSF==0c!19PI~bPBgYN9f8BEERp&9|
zZoGkNf~(WQuRD<jur3TvfupR2jGmFnT-!9YC*@Lz3}Zad^c%|)3Ow<xohlC>sWha1
z>(Q1~;fs-P6${!3>G-@1($pD#&DL}s!^zL)*EDQ-a5ng$z@aa(SF6<6!~xf&s}2MA
z8V1#m34Mxa9<e>-eK~)yxpoGtXIufJ!ZQc9QAy^Fic81>mB_UdG+Vq{MT{lci%eJ&
z?*Y@s0L`SkX1kW;4VC$`#JNz*XlhVh_Z$sHu=xJR%AtMl<OH2Y`F0sSy-a73mqc6%
z+7|H~w`A$+M>}efGB*{1V$M-pLyO@UTZ7>FrO=>kX#^!S>M)7}u<D)C&3Zadx&9pD
zv#=4g-6ktXYk2P~m@{532nNU!##+&*&1&(4;`oR!i~SeQ_bmK|!@PJI$RZNwwv^|@
zmj#$wX;*H=fXjIb3kCaFzPV;-3KvzIF9TkPjYd*|orW^4@D2>?1a)MNmAp|p^yNM-
zD>Wz%?0I@EbhPN|25VVz^@EeRrizI=*-V>ih7r>RIQ=U~6j*`;`C_#}N+8`H83G8f
z$7*K5-(wnTCCDDF>^@y{vf~N5T0dlK>nN}1qa}SuPGY1_QPfE;%7c8_3^Nr5y9%}=
zoki!V&+F(^RJLG|OVgV70hwH0vaH@f8QUYzt7b&$u+>>xHNy<R;N!&2`AiE!rDN>#
zR5;TMj3VL6mr_-%kL;W-zBLNICKESidz0+y04BWzMX^~p>2?ELvMi(Kc}C=8BgTl>
zukJlZ{CYiu#^wub#b+i4y3kxgUj<~?6z61ck*O+b9b&I%LQ2vks*m^aXEcQ2_3@#=
zuy1VD)~k~YQ<&OzzYEW(ipqnCt1&Ga1!MS@<7v;x<iLf~O=6G}ebow}L~o9@U-96<
zrvxt2AiJ*fhQ!O@e+&?Y<Xxx!SZjctW*#mw3A5PodN>@2SdB$P;?T!U5Yez<&??%s
zRGk-Q`pqU<_erS5Kb`V(@LVdiJ6@2@l-SAgEq@MMK}LDTaLpeX<&huxZd%Qo!m~Gd
zGk2}<+;uVl7qmhP&r&a&9&qu5O`1E~A3)_|I|T9j@~eaLDTD;=U)+k|#k^u=l~M|T
zaOabG{iR~YXu}R($k9zYlVFGnjdtWYzJa?P${JQQsKrAYiUEiaX2BZl@H;XTN<@nh
zX6+x+Qk1{1vgu}ENZVPj)@e=KRTPM1{lf_F`3zvcv<9Mg@_n4>&}NGKsS?QH6v^v3
zkD<Vn5;9kVxE%V_r>j5f6BAN{ya7+`RaOFYAU+O21WFPunJ?8iHVg0eYcu1*@Wyq7
zX=UL0i1n9IWvIw;!3i-;>*S_b&z8w%8}VwYI4D-BUXsuJ5LK@c4*NE(Rv~~CbgZDc
zl%?a>=ZFQT5Ou6o`75j#JyB1=jPX$3pY_8r!JIkB18vKX9fp#dYFWYb+D)9(J?M0%
zUs1}q+((dcZ^#q_>X+km%evB>-}Q8s8(XZ?cjIZr%=6Ke*qLaL<lHZxhX4Eu<O^|{
zZ^8`Lg!&<hgO6Tu(q#;kHED>J!%jpfo$Zqqp-npiQi71ZqR~#DKW1289Y7ISFHKi|
zKXpLzn-Y)ssAdcjSTwJx>@&8gjkYOt<&gZDT3lgP_4RU|-d0m^r4|e|R08npD-ea(
zw7fk($j|$xj`tNqc0WDcP3Ur_x4^tB#bqB~ie_5<FhPe}Nhp3;oG$o;;-M11FS)}a
zo!|m!Z;b`Mzwx8ON2rX#Uwg*DYWsY$DjIE6u5DS%I8Wk_IioKdk|1s{Ywxf|e3J!}
zi34+!P0M4HLbJuE&C)*GTspZAHvLAQ`ZvZfuW}R#ib)>^zPc+}0FeUt>+IljYK4AU
z=zBWSkP1~XhP|Hu5y}<4ty1L3#tY3=tZjv*ECB8k&uCoZuW1#UV)+_}E9jKu?h?q7
zCu;|T1%8XJjPvg9VR}|086{vOPVG*YH!W2cS(T_N$Cbg%PBgGEb5^S_LFVJB!iPX}
zTF?Y{!l?l-o#=SxV<t^lWUpk04Mopc72D(GV;02E4C%2+LbF$*B&=l(QCtG~TxKrw
zTs)86&i&4h1O1@2p-HvXde%Z1zKNpcMX(Uohx&{`r;ptLaJz&WvW$#a+DqIWx1Z(o
zzJGut*lfWyLTGmzGYi%Dqq`N}%#_{j;cy_FBu#=${(5rqgMUtcfK#dGmOQ5sT_Mp?
z2=y6b0TXY^vc~{vRvDMh)*uAh4S3lknj3?p7%um0tzZ<ly_Pe~&HN&XHXAiP*z~1|
z{^omex5@l~qoKEZWlAaQi{t|#vs^F}up&1#vGmrBO+yVBn?M`KzXq$&>Gn(V_B7Fy
z#=33x<4<a2o1bFwQ_BMbnbJaJteU|@{u^|^yhXb3ZEpgZ1FmPBZke;>+&;2|7<-qT
zGj6KGZSL~6KF}B{nD!p_q<5HeDl~#7SrE;rII;7pG@k+*Jb>j4X8z9%l5=jNw)F@>
z4gIc2CDqUYc-7D7i^Tk~Y0S90cHy@tN3=g@%U0Pt+$eSWjXB7YZnX!#$$+1(nQZg|
z(#%YsmA>^XEW9?WS#yqStwM=Io8bqQ4Lxkp=~DOI?TeL5K`rVdyun_A)CKnW4T(FF
zv?+XOnl|W|=0g)24XF^zM29nsF~6-ZLP&7?ef73Lv`Sd<GcZyqT+r+X2_FkxKiU2a
zLp$)6m%&O;(5+VLq~b$Uno?#!{&gM*%OcIw76IUUv7lS|7=-_wwvYYj5Is3E5`&o3
zP43sMUYFk08)KpV)fJ1W<t%I?sGLGX+EsMS(rZ{!yba#Gs5c9)J50{vbLMt4<_9&S
z5N=+Uvkwmp>Nivm^75s?0{Nj->+kXP_!))5o3wx)iKz1?$3=Z>bV`XC!xPNqi+W~T
z7fR>G$Rr;TA$}wn0vbvQlcBI;x&xA$<#jH8bnj3&TR!;ycDlAu#gHPWg6M^zl`4Q=
zyv&lD3N;wRyv#tmsafmTFXmlVA88fT8&##yJ4aIlv>oATUeXgh`%k!a3UDV8qB%Ov
zf%h4Dj80-KRrv^JSR+qb*`ggy4x(;Skrl^G#C*M=FWVh=_$zDAMZ~s;_S7#+bKZhF
zfgfMGKHS7*;*L2-Ak6nnPiDxr4i@z%4c4cii=W0EPIf^N)YjQ=mXvXmO}2OFg^hTO
zuP$t`vx4z*NEr3lp1yJPPYkuT7gtabJ$MT+J%%1L)Nfc(Z%A`B@ZfXDPING*vdzVX
z#>|jslwIV%di_wPAf5N$5Jbs#{-WGdTxZwG*{Z^qs-Yf9czBOBnL8<3yFg6_VoN%U
zH6{vHF$=xlNDHOg4`LW<yu*hzSN7qLwWbRSdAa2_QmD*7(|n2UQxuVskzC}Q1S=YI
zyhj@kQ{>}bCa7f5C{~LvcN~J`6X%~cIEPP479(1)*5O1w;d5ExMHO%eYJ>S@ze(+U
zq4~p~2+O4!Kqlo=t{`lArng_84*QwJj43<Iu4O>CmM24u<)t(@&a|W|X;X|@qu`T$
zbZ4TU@&5gU@&+V}R+9tBv*W=CLM)7E>CrKAfZbfkchdqE&e5)|HRw;0Q6sV5D0F5{
z=v_IYY}eiZkyuLfG2O#YD;mf(nT@;77E=gl0Bd$KKxGr#WsOjEy2GT7L`6rbGX&Bk
z_K?G9xv<B1;)cd9ME+Z~uM)J)g+vUnO~y@-_&Pa5<l?ElG$%)D?7&@DcevT-=(->m
zh4pSSCwe5Ck>py@F4_T_J;1_3OYWzz5rVXiywhlFrQ~$|g_OKu<wt+oUFXjgv1J`Y
z8D*8Ld<0E6_jy8@a|ducwQ;rW6KlMgLNzkpfzr2DGd6au;WWAZ-N`^-8p-BPY|-jL
zyi6FL8bY~SssknOg?#WA@f*pSJ-v2;UWQjWU$ZF^N6GWo!zKF@O!I}YJLi??mfF-c
zv+P`>uham0IY1P#lpcK`A-SB&Q4KRo7+O3ML19cGR*3kAT+tQuI{3j=2<il&!X4#l
z0eAkD@s)7(_jqJ1Zgj>H(D~L>DHOH1ESa<{TTw#TV1G>5X6L6tzq+$R(XYrLr^kzl
z`2~t_VH#GsInb_OgOqgAv>am&7QMsg@%?b%^^F!@ON-hfOMdHY*N%XDUfp6dy?IHd
z1BZD&CyDDxs%$6suO_Oj33#dV(E?ai^l`21t-&m3B%6ts8)3Aau^}%nR-nO<_;EDx
zO-KY@i?Zw)NFDp<^!VI}vK--S;v_fGSasI-$`8>q<sX%v$htnoc#*^+&#J}tX2~nw
zem#-%))XfYE$k|Z%_n<pSsf)9jL?<a)mW3YR>@n;nAk+DL~TWuY@@WF3_|1g<AB$i
zIV{KwV3K|GIjcf{<Zw}7e942e9t)e+z^z&WaY2L(Pd>v0op4k(W1*9Z(PVTMOoYuk
zqa3@_82(n{|JuKR7I31}*D8jj5+E5!s?lA|BoiT0A9|az0-}hke~b%Bq=m@DFDZ8&
zV;PpC96K(_`l?=j--+N#(<WjE#*X#}4YDRz&7VxnYFXT3S2}!Qp9^m_#Nf3s;JFQ4
z6^w{Pg6|LbsL(Q^cT^>EM*KFk5sgQMx8BEJ$dSM2ir^^3mUgPPdM_KU7Ny)r!)rqy
zpxe7f6#8t7D&Wo4ZH{+-lTy00!c2NhUGU}9qfU1DP5qF+m4=UM8dR7B&z~OR$}=Y@
z3ZEeqyFBiol6j>lw8u=Gm$KSZsB-m(Z*;ZQ=IXCcQLqfHM{*wmCucM#NFB0G7;vkM
zE1D$a2}V;0k>exGe5{1wPeSLOX$?5Fpr9J8w<~F->=M}lBOgPL_rndx?ksG6L-mqZ
zWd5LR+~E%@(r>Vsc4o8I;gJ2-A!Syg(sY<h#!7}DVlD82E=>$%b#Ha?QUKE{812Zv
zbARP7`O}j-12G~!8U#U{eW@Lcj6v|fM!)|Hee^%j@4s12@1XJjx9Imjm^ZD^KREb1
zZvB55{eFkx|KDeD(bN4;==X>^NAxl?@~Ec$tCu3z6Jx3RXRC;v?pmTxQZ)+$kwqHt
zqXTT`YuujvjE&r23|X41-^S&t_`P4AACI7JPnyDw9(KZaEE-y$>YvY>F^j5ggSFD^
z{&=(=?mXP>oP;0g#qDX|jX6JT#cy%ruf?9d)_klfafePGWNFd<bFmve%l=x`H>2qd
zTAkB=+WHY@##(w&pBt>IczGJyJhtDse9^#VMI$YG5IP(FV6W7-l@)sVWAf&3v&Y2n
z<q;~51>}UXZEK%;xv01hal1EDk^c>gxwf{5!i7Yy>T?T)mw#i+5BbIU#*_w?qTix7
z4|YyKk|UhLQMH72l?PcL!DHgW{i7}#PlCyLo>_4S#e$;B-odA%yIBpTnqIgS4i`8-
zVRwnLY{GizoZ8l9OOZVyE8)x{V@DZ7@@OlPv4V*Zfr*R(f40XdW_tQ5&O(FIqObJ<
zsH1l#O_{$7)F}!^@>nF-aX@A-8ZA|8wYm020nRm={V&hYQ<obLwA#(+Xq7QuUEm){
zp*VuYHh8EZYem(l6PgRPsaMkE^%Myd0}K@^gxJ)=e^+L2HeyK#mWx9cd<{K$qROd3
zD}vR-_8bHAje?<h%N|i{@e{Z5p+U*xO|zdaSTsUCVsm_9_QL=z%ikW<j_BlMOHAJ|
z`ONQS%mr|YN2336n@70(Zpttax0+5Y5yJ0-Ek{p|eZt5rUO+!FLPd8WedFv?neEzr
zxDIfXaO3zu?ptrSXP)?6n_$?BX_o1%mMdIyDUhe9awBp%lF%t-%*!HP&>syTlF(TC
zaS%5I4PNzaYakzDPDZ6c+N3&T@(?co1-h*l!LKd_9}@!lps_op#~q#KBM{Y9@}lyH
zXWuIuur5v`t*Ws0>yZwhLYY{je;=`~^EC~=g?%%1K(Nb!z#~8{lDcS9$F?0sipkbG
zF|5!*BH?=E9#qyU6@gsj!-Ky?ZbUr9MM){$^*iIY4leaX@G>-~H{-hQBN&ZN#*79X
zWU6Q?0E6}6Db>6?i(R!I<1<e0M~G~5r_GvIT^{6G%lhugDA_|Xu*XV(m_q<JF`HaW
z8rF?|^3^K~*frJ*CbI}KTGD1t<_N*!qY>!?<`AcBRDKJTu_zXYWt8IZP{N6nH!QNx
z6bA@&C9s=NibfqS77cPrwCJJZLf~mezNa7Ohh>U5<b?n{`Uxq!e2r3G8TXf}3h3(K
z!Z=tNnARUh4>ou_ep_gVRx=zbnkb1bkt_bswLBO|xU#dQUik~E=KGv-u3+w;I8m4`
zR}TFyNkQ``z{$>p;ndXa#<+clG5%;&!00^Zs2GQM6ctge5DPF`Kii;MdZ!Ozr*Ca2
zyi9-;q*+0e74V|YVuI*-X)zGQ2*2ZE;yUx_3bhfV|M|S`VhAh0bkJ8dkE@L6-esX6
z8M`c3!~(U~gem8#syMUQrDa26F&%seI!UJeWxues88dHo`X;AY{*0VZ)sj!2<4e5G
z??}koUUafwTNdg^iDw;*V=+Ie?o{0J^>{h4Ln<6`B!wXYwd@;$)^LAeY_|kRWg?KM
z+=P^r_Al2;>J8Y?wNtxx7c%LTxRgi6Jk+4nm$O}G(dKGvI%3(S1fnac(my4P2A>U&
zXH%0XShLE2Mwf$=EHgef817suN1@R<kw|LL97RRa6(&pz9Xk%9+DIsD!Q>@3GLFQF
zf%;tfs8cOAKc@v3>)}6t+SB?ft4|y;c#;gDk!n0p-N2uP7`*vWmReEIYNi>940Kqy
zEymN2uWCOm&>--(7^e1d-z=w@Pkgn#s~LS>JL67`+a@vg!KCn1#e<`FP9m-AAe6Vt
zLng@QXrMk01ZHlQN%|*8-HOV5M`58#&g+OZNR3FmF(so^No#yiF8cBPoA&rCyv%+J
z&a&U59cpQHV4qA6^*p_DOMXfk8YeYcccXZ{Zcz8dxK6y?RBQY+>L9vr{yd!8gTIn=
z_bGZ9EW|b?dkDK9kmQHrPO<r|s&?A2S9Ux{u1ehFGU8JVX@4DgG&JMj&!+8m0dYiC
z=F={CdeG*a6&!A`s!YQ<_|fNEOX)hE$`*7wDy;D4CxQ&$h*N9c7(%Y?8brMG`w9JK
zTEwZ-+9waIab9Z`m>aP?fryX8I!Kq<leRcNPOYq3w)OoomFuS%D@%qrlDH;m?VY#c
zsAs$U5wN`N9X8EBLi>181i@yc-c*aCV?U)pG8Bn*iRyLfjweftJ>kWSgg7295_tJS
z<5+Y_0On#@XK@+oK43ok-Ws$e#dNig;1EVVaw1y5s7LkOOI+pq;2~%k&sd5L3(J?y
zs;vGRi6?G`zx0IUK2WNCZOoDxr<aub`D&lu$XVePNXu86`4(2=4&m`V!wwq1C3S{9
z0qPFsVNzha;{v6z23JuWJZL0WeHhD=A@(}U5746Q*<H=IpQ)NfD1t=2<Djtad;``Q
zCA)a5Z@ao!=K33DGs&Rv2#>#p_|6YyQkF(zi4+-w6uiMIs>I#Fq*@K)8*q0zShHB8
zP~sLG?atu&>@a)kTlgGy=FaHsg7tn0*xrvCkyzfupTZm~^jV^R%OXAE>w;dEYfQ2B
z?<}Csp;^xh0Q7=ca~2%bs<M0x2!opTwIccx|FkpJ@hzHx&3P|RP&t%C0<&!{+B88{
zZPbwcBYrr&S`{E@Z9RJ?7a0i)<`11l>T<0-@=@b;DM^~$!_}pX)|B8#v)K1tRTsXb
z?Zd{#)hbe`(6JXIZIFXvYxBHB1$AOWsNNuS0O}%A;L%FR*s;EtV$@WhnTXpEhU_vy
z5FAV^n^N`j1XX~1A8O~>8ME+fflMXn#q8mN^L2!Tr~LL&Z59!yTf<76n8$SJ&kvj)
z8Kfq|mNQKJ?QzYs)4Y3iH@|s;Q)T1CO7S{jgNQ<6Ig8iZqm}ube#fEF{BpQoWa4HS
z_K(iaA0a3Ow;QIw$9IEyN^(t+aR(F=${MEAKJg-}zeWXhx_{#UUMdJ_=!%(qIGdLZ
z@{fIHME)`=y+S`^dS|?l&eDF}!kx`sJiwxsf;SzoHP-sftwJ-lGL=;}#u;NDcwLBF
zU+V-agY%wJo@#UUhTG^+m4er(;s+bgkz{_AmRM*ZOKsa=d*;VNH&zLt4+>sAE_UfD
zmjf1GTBbT3RYXo3FO4ZYB|3-@R;|w5LJ@uGzF;F>Og3EN#5bU#Pd1j4jE)V%?vVOr
z5sp=2_j6V>07WE3(P#xqEuA;QVeHn7!76cQY!?B=R_KA)fG5cP!L5RR2H`auq0v?6
z=V`i!y1QnncanJ?zm$CIH(AMga<g3F2TShgtF@<JWzYZXFq!Q?g^2$qiTsPf@&99(
zOwR;(`}{-j_`e(||CdFuf1|X#r-adpn;O^x)c-PR<N)-4NhbjM_a&19{AI@cn|NaT
z-(%;0GSGnkC(IN2|2hBc=@tJYJQx^u@!PH1ds^Fn&5i@UQ+ECx+w<D$zf*LWSy<lP
z<`)%^H?#x%_2DmLhhNuP#L(2(#16nj_a5cb3K;%Nfg1R>32*Y-TOEvT0St_P%WuDx
z`2Ny@sF|2p0MraX769;#7zCiFV`Bb0?RU=4TTY!J5Ww<xE#3{hRY~buyyfNz$w(`y
zDNrhyS{T|&8UB>Bve31p;<GY0c(*NTr)zGi&ueLHZuqA8Rv~X^Xrc7Bw10(vE$6$b
zcmF`9)^=8)w@&{fqv!p|{CnE(FRu7YK>FX0`mfm<=)QUVX8UbNfq$t*f9E1-`SvP{
zcZL$JsKMJ3n%X&0i~M!WUeE4tuHm~=|MJdC(bDwqdoO_hL52Fa$N$C8za#t~JNmwH
zPPT7LB5G-5^-hD5Gc-1R+j=Je8SmRmISk1Gw9+60L(sdwWdHd4Rw-|9ZEbF7@qPs8
z{zZv;v!q}pEGi(WYyIz;z0d2vtnS})^!JR&|1;q?)%Q;CQv<$h{HHn6D!;MC)LB?q
z0c?zn0N~q`@$LEkWny9mure?JSQy`q3lrU6`Tevpyw$ybS>Bf9U4HM&%*^t)oq?6@
zZ{0ur{^|2BzuSJ7|Mq>8|Iv9L=k2G|-!b0x-^co^_g4Qt&U^d2{Li@Ww*J<=+5205
zm*2lE%mB^zBk(^SufIF{?``{kNF06p@A$8LG0m8fuw*(^p*trS+Pq+-dp#XOK@p-v
z5!Gv9$tSRnDX0Y>wj%^rTYJ~`Ocl|EK0Pho&9@RYZT(@rt`ci)sNh^s)qKpfz2)N4
zFq>J>dg3jq&M&pv3*4AlO%g3Z#`kbuHFn{EkC(Mz9{9QDl)fV0GQHwho33y<V?TS-
zrPzYQ!7=>ue2p(1Zu)3pm8PhsSXdQrSUEOwoztKi>pMTk`sZfv^m;4;e{6uF<5Ot%
zVnx+mfoX}Ef01I5<YBs)1^l0a=|T9F*KZPG{Z~0JGpqt8_>s9r+8>B@DoBjlLrlQq
z_=dgMD%#gs6|u_QNn0UfV(Q@&`V!5$@dDL#c$akv_?IEXH#wlpHb3+i+rf0;BDF$R
zO`cOH`uj)9@OJfEYr<tk{Wr$GsZA6u$hB?Twr$(CZQHhO+vaZDwr$(p_ssL1hxre+
z@>Q~uRCckU3Ii-`F%ca|F;5vFF><09$}+>`kr0a)@nS>|P;m}7B?A%`WDHC)N=^X-
z^#J5)BYH0=yoyH<Yhte>;XBrCbAN?N5>T;`bVy=k4?|J~KygeDW(*Tu%78`o5!%=m
z)x+a&&mC8F+A57L+L<0biR(xTBdBp&5rpWsqT9_7r@mw1s&MH?)7u~L*8_jXDCKbD
z2k=cakk|i;x&H%p|JT`IVrAp}|J{Vw-H;wQBbf|3E4)k2@^9O3F7k7wiq>$F#oB3F
zX{J-{KE^})U&HH3Ha0MXYz7PnL6C2WG+_vJ3G0mm5ya8RLO`0YLy~Ne8z#Yh!`ZUy
z5aXj9;1=I~syj)h1Rt+^XCHrOANgnLysGx9>gwt}FRR`wTd@p6<591KXp-3Nw;K*?
zYx;gbR(WC;3$)p*^?L3@HM9QW7LL@*toA`s*fcfRlfepdw*P$2Qnk15dSOnw3cfd2
zZ>-h#Rv;0yoFGZ;b$UN12cjOVn1%jZy=ZK;eLp^VZ|Ay!PW(cm<ZE_Xl|N^@`1?=`
zv3JGCb=nObj!xEeK2H3F&f6%2bl&#wKL>29>HGl;y9)T{$c7Cn*u`QY#H@vs^9}E*
zb1XwxtMN=&x(A7>C+?xd2${`&LJjo?dB=m6JSd^41~+CKXFUfqXFH8^E3gd?h$Swi
zA=L*{!$8Dg&xs>>9}=xZ@QEfIfCyupATrr7&kD?V^l{^$+1%S{<7gkMk7O!a>pcrz
z9G|h6%8F+^*f()^aJvw3Bk&@2@V$v%<*w@)zYMM_)x=z)@fN5{LRu2tpYV30l_+d2
zPivH75>FaXoTr=$dD9Y2vr(KUBpZ3t(vn3fS4qglXLm|oi!@Y%P^%)vx)&@!SlNkF
z;zxQKHE<42HBwL=F<99dGbT!m72BZ|b{4S^2RXJ)eV1O_VjDxX#b<LBXcs&(;UJ{G
zRHEnf?P8-@M}Rs{iPoUXp{64TCxDb8T3h1wN5+tp-9W`1c3`8J?qp0g2qUt|DTXFD
zpaN276Q*|5V1TG5@Ff{lI)H6Yfk8(+V()RsgHaTMpnj_952Q>xm_n#5BnCJRq$kN{
zhd*@m`uZ9d(k-lPEG+FT?VJus+&qC5Brm^bTIzBpNRnkCUrF#xtS-5f33pHPSJl{8
zD+i4I;o^GiU1+LRq-Vdov9N*BQOnT&=wF*H^O+HK{uW%bCpTF7og9F<KMRdKj*5F-
z1H*1zu%b_jZj9VUMn`S12*Fl_l346S*-%9J)qfs*>jc>EgzQjIb%V4coB~tM@dobr
zh`E)Dq5&ohq+)s__CzIz5pB}4r@}d>D<QUubGA%d5pcu{(KJDzjTJX?c4oOnz>g|m
z!Bo!q0AS<V*b}caQfQX8kqbJtrqd_If!+-OiUSY~fYhrW0y&6B)kok*;)h{JJlwwt
z0LTx^4|QyIAqk!*=kGV9Od}4vk<p|$n6(rQa`*88?!&1YP@wGYzq)mlW?53Rc^kk0
z``h9!ZIEZ5YdSPk)oVP8=e1c~M|wglM{8SzRO##7VnkQlFqA08;A%`w0G1lmPjk6v
z>P++jNxlVpzJcM&X*@bl8sDp@t0&s;x!=`eCagwXWoq3sI|iB*w@o)papU%`JU5?O
z+(SGEym@|w9#`J8Ezt-0;Ei$@lFw0UMkRfqn8B_`VB|b}1{Cgn(cON`8H|}pKVjK+
zBXgn1&aEI^lXYS>bWHJ%gx?{y5&3fb=x0hkDlkloV99!LC*s#APLj!NinxbvX|jbX
zSGR(o?!iG7SlnBf<STMWIdZ(cFkIu^;^W{TbL-mJ)U{13Y#}Ik=gGR|Ah2Ln@9!13
z`T@x@%bcX0k2tiN@8cCZ;1#ayZ7j@G9WSf5^m$qjF57$WS9(|DI??D55Tu<vAEwhb
zUeJFC-!pkRzIW359NyzlZI@1Kui!$l&iGpX;Bln_9f~&k@7n;~oH?qsY%#U7XROix
z*_uc>Rl$7t<3vZ8hNfIik?gsv*c6Ru=v1GAW>ss}_t8+i<89qQ8AEdd=rW>+b25?*
zhvJ0${t5t0#78(v9R}V-F-jdyq+|dK#FEy+c4OULpRQO)v-d5GW64mAjTo!-2G!8-
zr;Z1x^SO6jlw71lvc~SCt6)z)03uSfvr!^*<?o0z8J9X`o+3t`R;}I8=O;WA#3a&;
z$9&hfKBXbl)haU~JZ3VdE+`(fh)v|?7Doa7p(ZO6bc0J^0UBDX)KfrIY_IWnGP;-@
zK_koxS>`5qu?a`~yiC^e*7op*mU)s@6Qj+3kk~Y#Ygd<1Mr~wKHpc%=p{u>RzRhNt
z?SDJHT~hmPZjy-z*-)9<bVV`3y%!r2ZvgI`$zfk^j3vh0dEk{A$i>gtVM*l5Frs-6
z>sjYpvbSvDNAO|dMq=$U_gI^mtejGiOAKNsinBoB4Q-M6%!W8hv5+PENIjDzKcrBQ
zCyUKmz}B{}*RYXH>D7k|>(IuF7CdZnl)uhUIA5la$=!tNYjdMWy(E}e698WBtB}G=
z>V$|mr0yLv%o#>{CmSP>JHW69>8sRIvMwy;Ds^QknWz>ZX9@GO)KkxYThzK?dX;gy
zNIJ0|Kcvc+G-Plk8AVkNpd>#=@m*J+<d&ei$ULRJGR;K4u!PS_lzACdK7PsRxa2wH
zxirlxIPJE&kjFJM5ZOQ|E06xos*t5aSjHeF()IHTq3;NhFRO*Iu$3p^LLEY1(Zty-
z%ZMF0K~i}|EEkHt#%58jTzT8;u>4(a+MxH2CP$YTvDR+Ty*@N9o643gvjQ`#>%T$l
zHkR7R#p`y}@!mqtjhRb8s`<m6Q>*vG<<3qkk6^;Mb&0NE*)u-jEk~9`<6-Q&z_GW7
zC=oGq=kpPtDI388RH@%eM&?RtYTL6$pQL2q8t!`0Rl4n`rK|%sXl3VQA(fLSlX33l
zFc=DVHyZ{M_6}Hu-mvFhT~|za@vi!zu50rTTqJeqi2a0r#y{tuvp<6a8IsRM^9-$p
z2@6mV3L(IU>cRD38m-I^ARvG03f0jbA1LMNP4?yZGtX6h1bdSGaSyjg(8@^PEaNRY
zbC9L0zvNsR!oA>Ja4rm?5pr$}y@r@Q$1_C7k&YiCh8kLEXmd`A3N9@^Nu71~zAX6x
z--n#e?{KPPpo&4tlTv{s${+K8HwGzhZT5ICt2FW<HFL)3P$JJPV?#SmXBxFR;B4WF
z))B@Lzk1*#+rn4NL+)$63p1nNDee@Rv`L(LtWszpX_AmmlgU_sW(>Ekz3P>eslDW1
znsazh>a|t>@Hb+fVV`B6X`XJ$J!5NUer)@E>2m@D5n*BJ?Rrm$&K3I=82ZN$eP--m
zor=x=d}OTEo!Du&`yOw9A$Lv{t_aIbb<0veeYy(v!8<AahSkF6mfIBUp4=P6CW2aA
zzUfj_1=c%~711XCqZ6xVO8gfu`Mh?f$8SHP8X3q9u68$W-c{Au7O_=5oD%(5Cm_$7
zHS@G<R6?d`6J-4mmk^!svl8u%POr<@@O|oCwPr_~9e7|$T>XH%CL`_Qu3mdJWLX44
za)o}#{aQtt&(US2yERj)lykf{3E`rTp)l6@XZv0Ez%)#ZSZRUgr|^@r{%v?luerJ$
z{v%hv1^vy8h3;&`nC(mTrgHJI4Nb~@E}1i6d%rdG%8`E*El`}ZXN64KC~AYMDlGpr
z(>m9Y2ic9_CFoOq=kDu2@l$F+E2WgYtYbsjhPLuq_Ia8|7TpPUGE<r@Eq|Ox<HR{J
z>Yh%bU!arXB-QzJpfLrp^-{xgV#rDcSi+?oDny4*eQiAo3qO`sc&Wjp4&3$Z$*M%<
zC0%MHTc^QPg6;H?^{Mo;{F#R@_0o}d9Sws49u8P%pZ6k6xu8UWAj(Tfk|8ok!xQLm
z57}IMUwTnO{rkfrW|@<>vZSoP$50x$EXuv)<AqN_9VXX{?7mqnk1^=nEx#_@-1q7^
z340bdi#$7v>)H;Bs(X(tM%fqaFPyrtq#_FF+I?t6y{M&xp+sd|9xBI9L91fOxlcn;
z5C@LR6B43GlS84Di*s&MA@mDTY{Ssut2dgEqFgZDp$xdu|K4pUY%Dyvqhh8sDk2;p
zp@KY*ouHm1`^my&JwE}1EL&a)^N%Y!?qGzzPvz%xT;k<kn*L}+yieoj;wb(wOBnv>
zx;S3dpX*h-`=k@|D!smglkQ>R@AFK^&&|~{ojb*5v<T<Cl14j`QSVjfrFt%2rSJDJ
z+T&pS$z#HK3SQO!`+jI8pZAkumhYQE4KBCl3NNRT_j&C!VhCb$$UQwpL-Tbc?XVr~
zwDS@@)*6jYPwcsz_Dl{FNg&jgqrMGPddjH_ndWR5ZMVdslmK7hv76{vM^sZu$#tf6
zW^#0UrZd|*pC*2}SK+l~WFCqv>;WRL@^c=lSJTEUE58OD+a?qRIBWP2qE{&wPd{)_
zC<BuJVv4exb7;$h&no&cO!vEPJNR4OW^S{0$XP0`9W!aP%!_T~xOsYv`oXOm9e-G?
z8^$yQCK+=e=+Y&eJHlvwAX}8#IIPNi_*1CD7o^?yh$t3M4w+OHFsUM^ZvMp`RDhEd
zr==Davadd1H9mBKxfn}kz}`XT?l4*<vbB*XdDb+Awr%EHwT<^Xwi7$0>!aM3ezVv9
zi|<Y#weX}s9uYB$S8~$WNAKUUU(+|3ZsDPfq<XQw{)0>#00}S+m4LO@y8V_@qyF7q
z!xp-7w0uvOh2e|5eZ`Qpv{A=SuH2gMd*}c*7W<9=Z=&fPA9riD2LVzXcTBn}cfQxt
zBj$%mV}gdyNSQ1<--{r}N$mvVd9A*FYe9>V;M~a9ui*)CIjDC$OX#{)bN{IaoJk!p
z>Aex_dk@3xW}|oJMy8{I36zNpS~G1K*7&bWkOfNxX6ZC`17XfGi(=Nye3M-ku64E&
zS!Wgy^nu8uNs^!>YbTYYKyj82#RQ3G`?=Znr6hLS1sdo~p>+~Ixb+|!QQKFqd6R6d
zun1O=Dj-y(nd*7gl%|n(3{h2me|%JjB?ln@IKq)q&OtX`e)vI$3`mAC#iUdBP;RK^
z=;6A(<Cx++%9K(1PUeW?D&`oTH9=g_r~ul9ldz&y>ZVpg5W)VXwF7ouq&bxL^{Aj-
zy>C4O#^xAq3qHzgsGe~zwbok}7;f<Q?!Mp>-x%Mo!90u`Yytoo3?NC|S_vlmZNRjm
z(7a2TS<?Y?ht~=`y}tj7yuZt*yFJ@142SJcs1MK8z1gDSYwFzZYueq;J4Bu5iEGVt
z#@E%IzFH<DHHo}tB(nTX?8kU-4wT!B%6htIO+|Wz=(OiB%8>IoiBr&oLN!5*Gu?n;
zdspI6B}6wbX_j89px~*V>?0!MBCa94xI+n{b1wW@?%J9lvcglXDC_?9X|&P94Usm;
z3pn^hR+><v6GL9I>iEf)^N7DMcl;B-AVvC;tL2v@-V;A3q}qu*4xIa}+$t(pld>?+
znnKz&`3+2y^lOrD{*T)iA$Rz7kS{8z{N`SJ_BCOp1{G82;TtmjzH5eX!?$o28%UW+
zxr5jFa{_}};k<oF^JJzypesVCMEg8<WIAY#Y!MCO3Ahb5^2AF@7H2`E!k<Jm-9xf$
ztn9|4r*^nTp{(gYL0>@qV)(wB)U>#tnyv}&CE0iJIh`Kw)s#n+Sp#&SMjB`6E%vsr
zMFXrDOdQG?Lp!}C_3ocx(%O&88A$2nk*^w`%8UD3R+Cz$v)}P;V+>(Jm;6f}3vLT@
z3!~=Zc?iC`u!eyvQ{Oe_jAR?qY%62ip|lq{?4dY=axCV}xUC^X8wP@13M@?H+OfMW
z;IbI2H#cvHAkcZ5=se`SWV}^mDCDbn48UOkgjpA$MF_SEm=K~%JZ@b=JszT)Sr;R#
z7<fVh|JdG=x)pGip?HFd&Q8$y@5gi>v2)9KdXC<2tMr$uIX~kn!<x_K&Bk<e6l3cj
z@>RLSy8(Ymy1!XGCiS(>rO{%8sTIblJV#>m|6Z4@@AeHXF&d_gpSFMi5H*I3sQrRI
zjEi^I&raaS?#J&(U~~+6XZk2TyIn(Fv#pc<X&+4kU9aFasm@97=wD`k+&kXI<n_Ry
z@1*v&{epeY-SQ8nufb2h+v<m*ZdkJu+pHx*4BdYlEewhpDh&p+UHjCLpxOYLR`5dt
z28)TKS|wt07W;$&8ZBTv2=UYVh=7<>G^XqEcAYU@TB6wOjRJdgg`CpmWm$BRItnR#
z6M>w`e5nymlq0aUA)|Mt^!+~_plg6(8TU>=H)yalMvcouJa)01DYApV6uuM;$%&{a
z5}{gY1_NtdHe?tLS{>Xe0`0(eoXaez<wa}SB^{}G9oVqJlOQYSG{oshPMv<x_2dm|
z5`^rJqf4r_f@sH{h$jglG>aSHv`Ot(ty#_WB+*tF4Gn1ueGJ1iJZT^63D5N71SGh?
zP(--6P+?<1D>W6CQz=>KneO>msDv1Rzz`mW_JRySXeOk)<AkSV1V9v0oMjb~EGjLx
zA}7JJQg9IG^3G%gebBahgjV>&GdWyfTLp~F@xK}^U0c8Ac3J@b$=uWvv1u~RLsBcL
z_X?jEj|z68gQFIt#44?Ykd39Y`S6pz7Bk`4_gW>Xf1Z7;dGv?v+DDB)>S4^Z>*^M2
zRsOL|`uN)8Jg)|dPGw7q?bebnaz368ZnHUZ&4mH}Y$)KLLmMfCxu;ot%xFYR&q>by
zCjO92EqJa>=@oo(2%9iT^Q#4Ja@78H7jjF%vNq_NLo3bMaqS0lS$I?YJ0Ci~T_5d8
z{4;$k&)MCj6U*jVCz+@j8!n0l!5?<d221Mqjy~Hq_ACd!x^LKc<Nl4i0sp}Mt$wPz
z!h+vE;Ew8B`eWu_Hf8+)>vD6i`!OFme`UZurmPBVdE<5zF4!<;r~JbzrK?>&;ll3Q
zd^aMtw#ZrJXn)8Wonz-)es3MMXZx)m^|!{cZGmMw9EE!t?_^*0rbRQ0T+3moXV*7m
zV>pF-!g*3X&7OhJ#Aog^`_0@iViunc{;yDmtyxf9Or_v%JIqL&f60Nq3ME=b0kk;)
zK58I!;AS8^C_I=RT-F}kAOD+T94xp>nF1VhVR-$WtFcaFP1n34JMHRZi3sAx9ia(i
z;wU=Jj$kL977UU}Y^!*9fT%+E>mNp|wJQ43O9=cIkx3gXFze2lfDdJbC;)O7AWMvk
zXV-%-u`*NDDBuxQ@c>5FqEtlhFW3$_le^3Lbi!jTR0Wbb)i6DL%>#`hVAp^foe=OK
z;y@nS=xh!eOR0l~WAgG!*$wD{Yx6whAxK~@Z_P!>+<I^$K`_-+CDG#iCZ4Po=xTqt
zai+*-n&lM7Q5^>apES<Ygj*YFTu23RTrCqxZCD(KkjhO#SbGuno`*+8(0+Khfw6$D
zmOEQ{whMM@1rjoyh1KDwFLHM_lRbKQtCfv`ncquUAT4nRWx?w6a#(R@Chm@O*xtI^
zP%vQm$`yq8A#A!Vwua%(Qlf0gBW(M2m*=mke$UM!Ep2B8_c?NE)@Ltg?9ZA!ewLQE
z{fiwcO6`8l?uPqO8zyv?Hq->f2IP}qc1^$BJs~7}CA#D7#%`2*mwU3kuS5J=N*mv-
zPrB#M3-BrUwRT*)kH5*^b;Iq8q2|l`r1S>twVNk<mwInr&%#ICQ9GY>?MDuNHZ2-x
zCTO#X*$is&vAD-Se~>jE<OvU%QA8Ymvv$qz5G0%ar*A6>x-WL(B2gqX2%`uF#lioy
z2v^oZ2gTbo^~t*lFwMo(G%&$6Axk`WYtJ$jvQ8^-*XNRePz9kkd*v~xhMA?|A=pXC
zdE^KUD}fx$;>8vxtl<j;QV@-24K54_Pz<_Dv?Ge^modj})X1X%`l3$lh$2tgItBJE
z1UZXdJKG<D*R-96nzF|Z>g_SL(OFHk=h|DHC8{~h4d=(EQe*j@*I@T#OZ}#t^M3s9
z23N&9roZ4dynnAJ?hSYD@jO1I=XN^321yq95SX~5oD{KeRWsK2c0R674AvdIp5B*@
zDBiy;wsC%OX;PCmB$+}Kv?bsJO?)YAW#acwRRp9~812ym25P1L5xpVe8ADb4GA@#2
zi>A$COr<qhyeX#T2;9{|@G#W5=Cd&aU{_&1tDgV)+Fun5V(}~$ZDV---AeP7Wx2M1
zLIA|Fv}58%;m?k_l?=;g_O{Z@{gwe4?4ikotHauMdpjfi6=g5Zl=C_L)m|0~Wo_lA
za>U^Q!ODnDEC4@MFovEYxZk$SZEexu&M3EXc32X|#EKK8ov-II@*DW!n)&J`IC2gB
zgZAPW>~<rOBoK3jgcRVO=%37RBE6J}_y@mrTqiP9G9)HfQ_f|`iYXPb41ZN$NSi4Y
zCCQMJhM(lDEr1<g#KrC>jma4`2G8<T)4{SCD5RmxQEAteuAV$2;Ww(~EDw7$9(ylL
zyN6kCRK2sihiPwAv$F^(SA>g>2`5$sh{_2fqZ1(Nn)XNZ25CJR{YmCfp8k^r>fKmR
zT=Q9G3X{8UvuCe*FS>72X0PNdqmc1lP5Gp@<zT92%$S#<LI8X72S%nNrzc>t7kU;k
zcc^8vHH<2q$W+R?3oFSpD+-1od2iE+bKbhs<G9!+Tn~f!ieX}{#Bg01<sOZcRs@2;
zJ8gH6d=u7oXQ~tClg91>kQ%j?5#S|7&QBvXv+mvE`6JekhfLA|*T}^ydL?C^gwprP
zd;II4@A91=QuPS8RA<;gLE4e@xTv>OW-jA;d7sQ`@^@Y(Ug~OP%Ty*);A%(0-CW4(
z>NeThv*;Yo0deU#+_OH=3x>c>DPNGZC&*o}LBwaNhn>J?uipIFe|DzlLfk|8Aj)zQ
z>TFT7tl`&h<#uzu7GF<}BW^NFW-QpbraAL{!))7fm2InX9oZw!1;vIl_JOMlSb0Sv
zVBRY6o(sAlP)`o=QwuP>7>L4#LIj19w}v=)g6Nfx3c-K;UAkg1M~>snx7pf9F;v^@
zW9Z$;1z^2L4^Pq%1X{Jar;%pp#W(6=>8(jK^F&*K@lgl9p`T23Xy)kaY3%9mXz}Ts
zP1`kzauZTCi#$zLIy8fi9qP<-tk?Fl9+XG26o?%G5SW1YyuDifJ7nN;U!xgx!kTOb
z*fCP$g}ierr;mi>j}^th?mH4Ww13UOnSj&BN(dNsu0k^}eyG%uKYfhhBItY`dOD9d
z5ij>#O2c1^@Pl&A(n<y)5%-S(ktl%!IDz9^Yv_akdOY~>fnyIBpYyHS*q~qmM=Rl*
zf~6eRvg<4nQ6mt06YFSx9wS^$?9Ssq|Mu~{=Qg}3S;3>ILReRHRcJWKsZds;m=^Wp
zu?t?988)Z;V@BGLilKDLQv+wgGw}+L02llhDX-Hl{1_0?ggifb%D<Zhg`%(SKOasY
zO0jr<Dv8YNaVCV;U?_@pDoMA&aM3s$S9~-?qiNl4o|Df!oi6pk%*pPpv{$%MTS$MQ
zgeUzhy{yH~i{J0%E`EM<vEh?f@C|#_KG&_XG!>GRuidk>*)H>f)ztv-*Sot4TG{-@
zQrCmc+VCZwd=f7)VxjA`nCt{p&iNm!hOIzsMzH22M$H<r=Ak$kv+yA^?1A(Oph3NL
zC$<n-vut4O`RI3I6A?8rg&Q*)mMvV7E`w?MCbaYQ5cSG|qQb5Id$5Imj6oivNk}M8
z{&!%)p`~XY*V|0F$(nzHZMiqgsY32sfk8$9Tj6J(UUj+;`(joy<T{aQA=QZ+{wwBu
z%DA<kYDe1loNiCzZ@rqlk<#`|fcp@>1)R9R8#G6Nt^3CfBUnwV1z4;5t)E1_6kC%s
z$9c?6Y{YQlHHyMA0W4<yhQL!+%_)XyP1*ST-?)af2Cmo*h9G_J+q8}J&BKud_(S6W
z+`oV;linimM<1a(12GKsxI_F5#psxD6BJ?m3PV+%{XP&Vbq-SR1A>~$^T!HGLj#zm
z9=DbU*Ygz)S{%YSXQ=xt#v$C*dTG~?X$^X54n}IASj8bKD=^%^*VGn<1!t>4X~NuD
z!pcebD->9_n6>jeXz7yWOcyF-xsxTznFzf#K_v5(F9C_4r-^<LXckKl?j1l>sM!pd
z6-74lDpau-;4E3Pq$bFArgeJ!uX4nCzk@&Rs@3p3ZQa%46L2+oO5|qfw-tC*d66vG
zXDZd;IPkiEldN~TTdHeSGO1-NP_NYJ_#dEQFV_8AnY=RSMv5324|9l6*pA}`xjZ>&
ze!)@B;(-)MvXEwT>rc}#-9NHIV+AbO;RY+j4P7>uqzAre)|`?^fh16pY+h`j>}B}l
zvCA0j|JZ~N^wxZT#d){2$|a)+HQA&Y%X4DTJjjXJMTy3*!6I>yjb&=4beIkRk=b;W
z*-tcocrvPtoI`h`1B@!Fedr#cc9YUy*z#+qe{@Nmc$nKkus|qd>BtW;R^3u6ESu49
zK1NH;<}J)gQ3<bKJ9uE!lV?n=n`zv8haLR%`_Z36eZc5a)k0*j){;mt!$__olSBf!
zNN<vtBDA=(s#Cvpy=fOfB^w(f9paxR2^x^w=dMg-bdpw3gcQ(pfezRbeZ<-A3qSWK
z`FCHgqtmw^9%+^9^a(wPV&nB)P6qQ}e=b^%w`wdyl+jhhcX{5!>1$!OV9)rzPYz>J
z@%;egheql3RLPO@Rb9EbC;8%{JZ_p<ddKBF&enK)>5v4Np=X?)!_&jnMd+w(AnhY<
zsJ3x1BfHTYS3Rt{Yb#iJaAn<Xj@h!<Ht(qU0`nmLSdIZ!k0`jVMaj+CBXj7F(S3su
zu^R<J(C!d>T6=9|r5w?smxc)KIdGb|aRm4O;-n$BoH!6iBaJwYLDI|~O`|D91?H88
zD&14Ij(je2JLaHc*2hB=ZB>6NKi{r2z0ywaS5vNl0~zk9KQZ<o!gegCPfBb!xoM}&
z^yMkWJr>6?giF0T#Bzm}30dA?GFS^D6x9=$WN@oQptGqH0Pvcs0~Qu`K(}Xg6e{Y^
z0+ii932uzGOy=f7d-0GnW|r54b$C&Uf3tV7nid~Hxlv<)zx7w}<*q3A`IpyNaQ<}{
z_d>U$ZkDU^Yv}K_TP}=Zo`g|iWY738C@tj}=KU!3G3S~c8<;hCfyZrcCDs`)S{|j?
z$IR6EEq8jD+JE7+vKu##SltmOCO8|O_`_joLdps{-^VYTS`Li5ua&}U*iG(bdavGh
zpIF>_9Q-VUFV(DyNh7a~x=K97oVqaNHXjeGHR^Y-_z2$wr;R<uzilr6E-!}=qoW{f
z*-3eJImH$ARA0L>OIP4iz>t}xU)o(MF>g4bFKl<I=r`zG4jw-;x;JdI4q~ZjXb!sf
zG^TmqylNyGswy;WAhK0$4%pT7wOd?H4SRTn!BIiMYBdaIl=^M&;oE>8$nONixoz(v
z;IJ`zXs{d*MXnohvZ}MEo=YSIz%imeDUVc6FaL%JP=RVu8t5T_ieVVWR<SG7398Fr
zKAAR7r>uyGRT9r37q-dOPNZH%Y=zcu>A5$=;Z|^KjxFEhZB>clBaV$+$Q{O`iy3Z=
zEj3Qgi{}nrC~C>##0~r0;wW=TDjZWd4xjs>)>Dy962PGB7|d7Yi|aDnvFyi3#AIlI
zAqwy?b3wLU@T+69GK5Eb0+EsO`V@OXD;j^t(taA&pe-ob*)1T&-pgoZgL$F!TRB>I
zQ4aY)y5m&8fwcGWL}Sm&TV8x_!k@w0YB}8?=ks<J-7Q|VU3WZ8DvMJ!Z-Sq)yTcuq
zQnQh4y7_)M!#^ZWZP43Q*IV9dxStUji_@tZKwZL0^QBkR>#I>s!&DCWuBBeW+xC9E
z)KQDw?)Kgk8uOOI|Lr4XW1-Jn!ge0|?JGh-#G#DC0Ol$b+aYOpPR7P}FxrdYAc++B
zLjsvgN8-Tp69+1=d{5^gfg<^x$`9t|EJTgM+t`r!EtZYQFB*6FWa14aa!4grOUf7c
z42QvQGBiQ5jk>j-^BwaYnnmB*y$QZSzEQR>)QZm}etYyPxGgY98LjIgh)aG%7KO_T
z@&1M+x?cM<9OuBh%Z5la)z=adCNX?1b}EmG8@_@XSi*yUBus<UYId@Dx;{S5ZY6~$
z|K;$cw+L{9H3ES>nu0$NG_Uos-*-Q?X0==SX&<qW`N|2VA!VBQ8im??x*Z0SJY_s}
zBwMlsi;OhUNHrGFtVw|))KjLTK#xxt5Cjy;f2E~}I;==|i*_sVkTV^!mL_RoQNX6b
zrN)pl+at-wR8ps7SB$i-p_E@QhSZsT&Xyh|Xk9;(Y^8BU9*e|=wwp0ons27Dp)0nH
zCZa@X$Z0ga5*?aKkcFO5h{(agCR<>^J0?4L0XPUZhmFLX@-F0%XC=uMw=$I>Jt;Z)
ziC3I7SGVzUup>{=5A(;h%{X%YoBKW=uexdvTPYpoyb$@CZIm5zpV9t$Y0uamd3qP%
z(xs4y9v$8NN-q|DX(iA6s<Qy5RgS)4`$k<Y!kbeT{|QS7O~jIp4UTPR=R<t2d@B#!
z1NlX1xNf|C_APT@_6}e3Xnx^)<-5x5C0{46$vM7xs*DAW_0}j(ZPm&YE1KUieJ?su
z99pA|_l)g7l7YT{^=BHBLDEGq74-f2tBa=G28#Kcz&Juuq9G?|48JA=e}p7B{f=5Y
zGY2jU_{-=*sHvYg2-?A$W)x&LKa_ovm0>3VmkpP-&)Q{k?6%~tQ4>BgJTVQWq}rME
zF)eM<-KfS<!Bd)^d<pWO_wUMo311Q0j%cwsstZA}nop&yl3E~G>nx`hrn|(ab5kOB
zO5}(a7v~-WZlVf729yT=x_*<uSZaPCqQ>Cnrp#U(lsL!4so;;TGYMRXJG5|YijN5!
z9pvijCjpM26sg;xG+}z}#8&g3yn+6G*u!2_=G(6Nn2cGKFtgfi;6>i*u6h9!cD=3@
z|23@fJ=2X{xdOv3A)Zq~kKvx7dmt4Qt+wlP*58J`x&q8T)}0S4^60~IV~!ZGJ01;F
z^6@nAbRhW6`BC})>7bO8tHqIZ#2Q3Ko!a^R_$|e;cFGc+|K~`6gaWLULc$i6qkkXy
zo9N75t?hx5O0;n9qIdt;4FKXwc?U9%=^7L}2#G}T0o1rG9R&5ofwWHybT>R|(SOID
z$w3!olgJP0E!8~<e@~<D*c%+FE3ku)#211&xVJk@gGWHjy~^1qBaR_yHs!c7kPeFV
z=SyXWaQF@}9UM6_S1qI!GmuG$z-e5_oXR|~0I6zm$RVRBA)+9t92j$Srk7v#6=Tk#
zQXvFOs-FYHCI>bJQD?zU7KxlPQ@qQT^&#<kR!k82&_N4#ndG->`dKm<^4I)nm5nlf
z#E+so@DIGsZnFI#?BD9@rM2Se*c$mzn#<-%d^x)c{^-b6)(FkHkj~RDW9Iddra|bs
zA-?qa#aSZEI8<0`#39^(ZkmZIUV{917!m-?FMIL@F<Dr!l1zeWG|JIQ$-Di*z4$|h
z1=JcrB%%j1R!LsDmMYs5+QOj5KOrFm>4Cug8$mV-NTRf1K*xHIE(-+x{#J@{pC1jQ
zEm09|0<tIo{zHb<lM#)xcR$QMhUXdtDXs@{{)bOsS6p&kF>k3XcG_kq--32t{?)wl
z-9uJ(cUowZ{*14|-5bca@Vgv$6zuOC=-Yv<#9MMZ(3s_e_Q?GApW-$)FDUJt9The?
z^9;bpwD1Xw<8PfX=6kq?>?@IQ0%+HquZAa6a^%3BWTf0Idk$%!1XF1#7ll2Cp!cvf
zGHWFxU8YE42kM~k>|>F^3m1)<W#sD@1o4J&4u9VN+!XPf(0y%g6e*YgL)`zP?}^F@
z0bmz}juUv(-VMi|OG6NN*MxQkZ;?P~(Be=sjSLbgv2-^cnE$BG@%DpmKWNYM_JVE^
z%aGlIfV2d(-u-Q5-39@3Mn<k9uO%BuUBDgG+yTsAJU(kqA>>k;3%@<Z8%`nfjv>Ng
zUmG=!9Yq62iGmAUT3dYw!E@$)`Xe3j8<bagyt3feC38UJ4uRc}@&lia_zYyfFvz~q
zT7=gAI4N9`;5}}8d!y?nR%9y8u!QW|kt#El$Go|!FfT#aW--5Bf_7cO;Z*OsW4Hp5
z4_@96a&aTmdaG=8CD@eN?@g~AFTu*nO~d#Knm8tps+W&_<H&L5xbvQ{w{Ovyqo5th
z2u^8F_lb?ZS4zsX5oF=`2O|M=zH>A;?Ax>dOJV6%h5>maVb(+b6UyR-c1uMt32OD=
zaf%*$Vsr*!GwY}jwM)F#7)x<V?BzCaPXmu4kDfMoP)MYV!pu>;xIm93L0~W(1Rj(e
zAP9k~MIJcO;z85wZq~9?*=jB}j|gL?@?rQy{4FSIcm@rAU^vF=Ts@F1O|}ekHfPBX
zWTy3I(p0$$Ai0q;aZFQhlHkTBR@7h_@8CGcc!rq_ZWWIrkJ>J9uJ=|quy<l`cl{mh
zr~UZCdHck#@t*!$`G<a)^Yxys3*)M7bucQLVM(zdYmSp*;m1OtG%HmUth)&fJ6iTY
z%zmR1(7Tmj^Ee;e{*bPqwT|y}>SO&9g}GIZzt!Tg)ST_b?y7NJS_y8Z3pQ%dm;=A8
z!vdeO#!mM}Mj~u<t1I0Fr~5YJz1LN>9Xyo&VZ5-}h;9EArSJ2OEpN)x4uF~xxaI>|
zK@g*KF6-3$a8~@v7AeA`V`QD3Kkx=N2R19^p9tG}N-^k0X_jP4Gs3}nK~UdIN({<Q
zB~qL-1}oOADX~9Hum17&fe*BDl15ZxETa7U1cziX0<*5Zf%(OHF)f`T2+0DPonZC}
ze^p0VG#8`xU+FXo=D)X!Frhf+krMVATywIXNFubMgz;V#MCm{eMSZ57L}92D*5vb5
zGhc01Qj(cNBi*CGIvKh}_lfmyX>a00OH?yHIaT}~-xq%p9rc?%f8ORoucbCN&Rn@R
zJ7aK2m&fQY{iNV&U*oY%`fc~S+7Rt}jyL>wM;$RX68>N_CpI?_Z<TBl%D{8TjrKj6
z@t0z#NK_KO4oP}jz+(NLvU>X$E1fb;{XHz*dehxdRKx{ZE55=ukuLH+D-1$0Ati1i
z*DegO>^XejMd8zniCbkgou;Z)!7IpWLsF6$RuaWul*r-9awHE1N1}lgBr79RBmF}N
z6b>sI1Tl&n_-}mnbc-0r&9}EWiJ#c%E@Rx}Suy>U65WD!+T7n1=7k@C<n@8epZDy7
z9WaIH%TMTFSv25ZHm@PxB|FyX*Vz4wDp>X?o>T9j;Z#UtZf3E04>J^CeKMP6;awmq
z>+mIHJZypcu-t6fg0c-`sj((k<}|&R*2^DPSa@0|&1teVQeEY>oreGFq9E&b3cPUu
zb<Q3}j$`xpl9V%!$2;Fv$Z>3q{?RF**T_;@7PFtjMpn{d4$)@TW8h2Tvd4kMmy0op
zNBt!>wS<<DuN;oP|2w`tu3OHl;k1>&RL+#qCEJV1att20mZlsSAc~IR2>Vu=<`h>m
z;z)}c>u-zTJS7RGhyx>TtVkI9kkO^dmwK|ynFSBp72raKFk8I9nms>Rq@0DYQU*AA
zYSc(^<d`8{*C+1y$gmn7MI0^E>R6Uz<iN+cgJ4k54`2p$DMt8EZ6J?(hy6v**h2~f
z;i~BJsfvIesf`RyN6tmgptzUE;%AWZONGouUSb!8&u}G820{e_rB`7{oybH}1U&^&
zO!W~UC;Ogw6JZ6{QOZ-GhzzsjS<JRt*ZNWSmw(D(T#A_`K~Q?prapUNXdmW^0>;nj
z<e<@qNh>1N`!ZTl$KBZGkW)8seB<Q>Ef35u?^U=NecMyUcMOktu2ldn(FIZC3TW~O
zoa`#kzPQTZz;G%Z25^)WNy_}Gq0DRC$Qd#~S_guFJiZ@5aXVwlOf4pVA!q?}B6pUd
zEI$Qv3hor{B<@7!RGz&M@sWUGEYwQZ#!c5G7qG$%Rha1}oWT|a4Jv>H5k!XwqC<$_
zA-ELRPLyKZWGQEzxsY{E&dS5pFIpP*ERE#U9cK+$0t;u%ofH{dU>MS5QsS~rXy!13
zA4wdd)B==q%A|qgK6FfB7;8o!{!3^uCVEO*!vLoZUff;gJspdU&&+4esAt|YFnq;&
z)q0EaUV6j0lXZNCojfTRQ(zsf4*dyut?tV#?*ZRt=#_pr&~2~tvRYBK*Wou;-wJM;
zsA4(%$#InvKbrnLy<RRY7>dzlb$KlN`t$Ow^z1pHhUQs-NXGMS`DbO{WNh}eRPM($
z4_EDZ>%DT}G3|kQzwPyG4^ntn?dabSgY^)$81|W4n)}l3QBSR_?qA|k@+)#wDW**v
zTk804vO=%I{8Gt?SJTOy={?S;KD)l%`8ZVH;z_5oQ%3LmCAOjFQWTMpNK^`ul?g!;
z6*J~KT7!tV=0ZbE@tk`gP~MyTJ(ue<t89ugMR34dld}}y1rn;bd-xlKmElh=II8uH
zh<x`JRZcw|!d#h3#2<5I@4gnMFuw1^`jG6Y^I@OL_RK_=Rz+5)oKAmXr^o06yKa6*
zUDtOcMW+moIS2uYgo9e6L@NKG>15|vcK`NdWj0>R{<71>V<+Zcp3g4b`?O?wHQ7yW
z6EDN046Qr5tcdconmOj+HMM~m%7Yy1F<q8q0J~Eng8jgVXO!eTjFJegk9zAx<IZQ-
zN<;PI7cg0RwsTj9i&%>zS$V<`Co7WMnsrx|-Wtfo#D5t58~B<0B2%eXi(i3X!@hjA
z0MH88ZZ$^QWrg36-;m#eeN(sy+BNx~cHY&idX2xO`mahNd(~R@>ZR-@**&$+FUIOl
z8~No3=tpsK8T6>IB`MOh>EfROT{N?!gw@aoO<iOe`Lmelo-i(DtG5`ZWKz#S&qGgU
zk84=&ZcpLBx_MIYM$aVdu6FX9#~ti0exJS{!%N1S<VWSQ<DE3+8w-9J7s+!w4{zPL
z%sLRHzVlQGEqJv&Jf(|f1U$IZ(%5gZ7t@36ODuD`ozG)YbYGjPoxSkXBJ0eAleU=d
zUUSo@g+FJ89CKtp)$7?Y?S1uE>7nai?_b-0U0HDaUaDJ%dw*+>aoiAZC>1%|AXM5=
z>C4=vkEEfngLH=Oj{y$GkCbE1K^J&qjNrk_l3)`PCWDtPBQ=2{3}_93f)g3WXnj-Y
zPe&=J6Ti5UdI?Ed>tacg$F1ilB*`)ita7_oE|1f6<ZfE^P6r{<`>?+zgC{0190|uK
zDzM|WG4jCfCz|`TYSkmtUyXmDKDbhcL0Ks^g-T`&&GgO`&P>i!L#3fHDT>U%3eMiA
z5~Cs|JKcnZPGl%~|3z$Yar_@xWWGy`4IX534%D`7Q9oBxJ->4x118;3KJh;GxXp<a
z|Nbe%PV?l<zgE63IzihF`_(e^8g0-_HAPoPwpkE1m2#P$mioT$@xHq+Jvptd8<_MS
zpJkk<-Q^Fj-Q-ubh=MqC*=m0k6#fj6{}Pf1N$sN_+Qpk*;y=V!dCps+sj)M-1K7J1
z1Gb(9JaOh(GH#D;n|cO)M2$dvqFVp84IMRX0mhTkFTh6~i~e`)aRo?8TH|uV4}M3b
z81;Z=1cn!T;Y<jW^9*U*1PJpO3Bh@+?9(!Hv1#LE62EG%|0yONwd|$l{rlk3z1m(?
zd{y4wN+aMeqTCQQesEogq3y)Q23oaq!=c{;nST)b*6_BSXOu^>l^;GPPLynb<f7PV
zhP?Q3uxRThF3J30Mg(zrH-}rgH6?PvbNrP6yctH3_}j##Q1+!q)7HVm?*)4WHncYn
zwH<HZrUPuQAh?>Vie9x(^##Eefd=B$_SJED)<--yH+F}f>7ZhMwgW%@$ZagO^lVGB
zeTmv^cxRe-7W`6w%>KU;TEMK(00b5gU^C>#Z_%ZI3tx<Xk<h8xOqPV9%9L2Q!|vr-
z$s)rQUp$4k;92?>W>B6wF(abljHf8LH#`=FH{BD4XtISG8Zf1gmW(UgyF_e#08Nn|
z^uay?Fl3^dGHj?*M#_Y@B4BZ46Z66&<<ZlmBihmQs2fJtdcPO1>6;tUoA$PU$a8c@
z@b~bo&5aj6UFm0APhQ=W$Mu!$|9nsM&mM}td%u@H@K0bpuichAdQ6F54_NR<zZxIR
z#;6bTMcf)adOXVCLoD8#j?m+p;a;8J{l1CJ{K2{&l)}$lIfmU<azUi?-S0(vcL<CY
z2+>B|guNN*M?JvVoRJkOIw@0+g#?k!d6zwlk}pV#(%n<J|5IWI7XJHb`XQVC1eKXB
zI1-O;AM1@gqL{lD!>vfp^rLyuA6E1-d%j-Jj4H}SS0~%WD)?fbXJaYBahRp0cs>~?
zjD0$CE|(YvCoB93>`wExZpn#X`mWG@Tcrutm4}1Am<^}1P>jA0*aO}2cZ#C+zk-7I
zNBsd&d>IW=GtVTCOeS$mBH)!t=oR;sZA7}h{wC#2`j%-d0s$OGef&T@9E4@3^o42$
zwQaMFv8UvT%SX#k%R~R0c;F64O;+y{co@a|<5&WuOD-MV3=!O39JJbOmo%3POp}Du
zHQOSNz9JrJ<d=<<g#L`m*+{Oa-et74xY`aso1<pbDY0Q|D$L9bG{Kw8Yci!`F8v%G
zk_wP4jq#IjdFp-fg@Z?+&X=0;v%px}Wn4*+Gj5mM2UUJ3JGFJ~#ki+68wG2+DkC)M
zNX)DJ(YrAv(cgNSX3w=}>@)toWEiC})Fz{va%v*|H{3YeIMle+I`{A~j*jzo{{|r+
z7SEM;u!rPF?SYwxN^{WAHEO&3klp{VnZvG5b?6bpUNYm^7+_<zFz5-)WJAL*L4*YN
zeOX=a7T>eU`|#?e?O4NHbSprqf}kW+n8Ff73-GGOb32?7r~<M;ruDNBa6VT$tfB;V
zL8j#sr2ZU9$(Sj#S~e`iG=bGO60qt7beo0e?sXs*ct#&9+B1)S7ZKb##y#LcA6XGl
zg9axPhgk5mKJtL5Qw*kDS+ZyD+x4s$xuHEsx{lgwsrFr;hREYVV?MHq=<{CTtU<69
zJm$E9k2@b^=Qeg!gvX$*oxP+tDU}j!ke@T1JBjI3Xmmk39fXk|E`ODW&dZkOu(V`c
zK9^G&^CQMl+;dcaQ!%e|FrB%-Zdrt&*l4jDj|&4n3M;sdYAYz3DRP-?`1v1a&VwbR
zr$~6Zj|$SIok^ycWs$2<$uyPijnAL)yE5;I<U;lDbRK!Z_Hz`Lpi?(is(JmG&8oAK
zdGq&c`5WWCNtB4{rd{f=*L}h7Lr#IMRGG&-AM_bRUZ&=n0IkY3bJi>9(c7;5=WRMK
zNg^1PY04>K)OF4sKAUF2{$Pd&)pSha5c09%>;%lCnYL9qg}&K}Ob)w8*M@IrUM|(>
zX5p;EmWU^V%o`xWZDQ1j!kmbg^q(Sc*By>?Lr8uKceY-FG9`%pvS?C_Vx64qR8*GU
z>$4}zm#LaP1sV)k)>AuU!<LzBQN@s&xw+EMZuH*QgvhQJ{HgZBXtgJ>SJ+GJ8^$N8
zoZqD*(SPp`P;$Y#GzuRcPWEjlY(55!tbbT=CTlw+st|?p6AZ_a3!=1^BcPHiul0uS
zj!eq8;>hv=SB7$KJLR864B02khc@C<9_Ix-%8w&zaJqU)n%oP+Ix(fP6aMBqea3Q2
z?vXOQJ<Z=9?YqGd!qfnqeUGH-W}wX%M*Oj+J4&X%fg`HujE7E?#`CI0)XOw`Caw{k
z^^)4dr_UMhYbw01^~wt3uv-veBqK#q!x%nfe3Cocu)#Fg?Y4{+`%Mg2%&;!|7C7)<
zRU@zQXW&YrCt?(1%E%jTbSP{jqR*S6B$9qe8rb@*JO7ajmmdO#;Ve&e1)aU-2icQ2
ziXhl2j1|BDEGsPWH2w-kO<$#kjg=5ZGGLieqZTh-eY?WA+0X$+>|{wBb)z<HVwxEe
zuOwV>G%`NkdyBt$s^WWWF5$0p5&&ZiRPj#vMB=0PakBMo8&PZ`A-_@vguCETK81so
zU<HrrWJ>~iGW`a~;^+#7IS?J~a%ttl8N7wK#YPQTCJ<gMA;Zj_Y|r`e(^MPJztYvN
z=g$>?kMq{GG~O2%wl)BnK~v_dvNxSpn~VOKRGYgVXLjG;KzwL*8{=V|+Z{LMe9S)Y
zyJmI0w;qK?i+Ytky{8SI!8s?VrR%{`Xg;seE-$mUwhNP+uen?^@fd4GfOj9@y!zD!
zx8O0;H?Pm@Y$k7}G8Q{X8ryZ-j=T+gul@&vOUg0jO2j9}dR=rnK<KL@>#LIpUR;q^
zC*lbhBSD;j)nYqiz$SYKxSP^nM`NNQHp+(3DL1!7UxJ?1-XT9;rm`D2abO2;le6Fp
zFU$`jw^Z~D(u)FI6>fK6MZCaMpE$7j`hwv}*f_7<#6egvyTze6r#J}MVW$*gVj3mm
zUZo#;6}JFhkTB7X>8YaW@xFcO)~XT3I#Svk@Btd)2i-IU;zAgW=L5z0aw?Lh*Xay2
z1XenviTIjpz%y2@km{h;gdjF|><^zM!1DXtI|NvtPCK&qxi6a0p-c))7WwYA>rm5$
zI98T7(5JzH8~@MrHUGx9x^Vj6__e;D;6nAq%GFKHo^-p}Xt;V6Exnx1xJo;}*C=uS
zpPk@zey*EKdb{q6nX}j0e@ol<nVM@athKlKAElSp3j&X$nd!H-JvEOv5B1PI&}!BA
zlpbkVO(GnL(%Mdd$_$6eJ{JbFModRLrx{`6G$vyl;oJ;^S}QC{%9%_`sX!#LGYKv-
zl+_jhxI~O?p6y{ui;JG~fw&;aaSFL;g)kL4+**KJ`~=mNHkxF)<0Z(ME={_l!k^WE
z=9CQXE$Apq05te4W%+TzuPou(62COttyBejrCZ$p#eY~k)TAOH!;W%;k`I(7T#^oK
z+^Tns*tcMF=I&mY3yi{p6A7jmGe*Fsom!>j3_Cic^@5qmB#QF-v2=_>NDg9Z2PD1S
zV4*$%l^6t4=Hx-flQ1+{Lc$x?j!mB7OA_5zS}7!p8GZ*?8sNwH8T<LR$nH9fFS7hI
zl+qRcVaeZazs!~HUSfk;lPy<;EE>}9X<0z5I87V>xtLthLa(Zp!S4K>_<R5U()0T)
zMfdezaq+3sgC_4`c-MPb&BP=vdx0iyJXJHpc=t<D7o@KoCL+~QA0tUBnmD<(It?Zu
z#`-Cb$8ehW?R5}hy=*b@<PT5q%GhZQ2<w@o({!u0Fs-`x8ze8C*dg;-3|2vA`-O`t
zY+ylsW;zM-E0cXJY?9pwM;|MzgVy+)HFEsMb+yGk8%zFEzl(9uD!6k&664z3kz`No
z&2Ra8DUBjODDnVWz__=9uwKTg(7Jq)|0EJ{Uh-X!Pu-5%Fvv7D26P{;!MN?N@i(@3
zrG2vEy0R^;l!d(!oEYKbW3%>K!aLPA2G2%g0acFX|Le~IjW+v8Qa1BZz0Kk)ZM|Kz
z?sdrU`EO#_Q@&=x!mZmXs6S@mrwN%WMdQE!S#nMI-<K|h!Q10$(-J%}w2(U5VqCms
zBCYVX$Oz!?eye8(Jbym<!|GtiW%0#3$zWHR^2eVJ*tZ#iU!LX(Imh^m;=-^5J)!{%
zHD{F1tGt`W><QCR=mXiFVW$_t=;Y6i&I46ghv?(CSO%~m21s^w&bI@dAhpa0ZUBGK
zIKh9PV*ABT-p8Oi_`^L`&d<WWKs_yY-U;S~HUa$5hUi1w(hBXcz<mOH@O^(ybin9~
zJiUC_fVwq7fsFYwTs8-^fFm#g+i(XZG;4lAx?!yT1sUpuCZNM)_X7wWphAfL#wa}3
zLqx6-k^pN<?S?9NF@D<#QecZwoQX<&h=*M23H?9f?m4=WaBmQG*g?lhC+VbP+qP}n
zwr$(#*fw@-Cmq|iZB6=o=X^8Y%(-*t&OdjpU3^u0?OIi9SH17=DVd6qE&VnHL28wV
zXx<8yo4kr(&J`w`9w^)P!@CK8uH}0!bxnF}4F23L41Wi0<3<cZ+PB@45Dyc+bT-?|
z_IF5FOFq+F@lJ3Fl~TWFyc0neylD6Pa8t6eJ-!2u;n3lDO8refLGE50<RS)>WA`Dm
zux=Q7hRp>%)GL=ZI80gC+fX=6x!C6<IERwx=W@98sj4vVv6B8|rzL-DM(J6-5CYS;
z4^}R{kXIFC#vzZ5S-o#R+dJ6DKtL><mVDbcgt3_M+g#${9ELBoO8bcC=%!<Sg0FYY
z>U}@C*Us&OyHLJ_yo-dT<Q)B}R^0bZF;p_2wkMg%KIE%$E5nptuyV~kA}r<{$-M{^
zX2f<O@4`Oc@~<dhmci~Gb7fxz(A+|LQBw>v#*b=(eP9=^s(Ua#m{j|^zF9mi>cW0v
zRBY=6Fuhs)O>|~8&-aGb7+G^DcSJwPQXsPoaCf<2{;EBAjTw4%WXYby5q&U$Lr{+-
z7qI4YTmzhB&r?vt`^uKvSAbL55wcaIyr9>uM<t*~^HavE3$D-A+=BEhz}@DY`l}NA
zb9v}jv)5wB6hK!{FW$-r6&CS%Lql{dlhPSGjD`BE2lUWU+J|_^NSgT*n%S!{R`5f3
za1)A}f>9D&Um7{ahB=gXqJ|UtRla4RZPvqWBwT{`1%8bi(#Lqhl}#2S&253(GD$;|
zjJZuV;A?oOlN*v)32>4umpO<j-Adqs05_VI$m&)T@;P4spa@O84=BNrY0jpI3fi_1
z!gWV^7>$2jxY>tfg-_xXPY1rzg|9Wb(XqSBo3zqz<=&KKZmhV&Cg3od#{}-K6XK;4
z<Rva=^L*;i7=XIf00iILupM?NikwfAE9^^;T!^YDGE{@%jvm;E#OcDs8FE*Ps#VmK
z30^2AD^aEWC9%@ck@$y<J7Q~m9=I~gYKoeYCoXpX_!@buzthWR{%*NwLOxxr39Pa>
z^Bh0(?Z|^=jYHC+%2)Z6^nkDgM<*tgme@aY{I1gqr3vfq;~p^J?#RZOpzDq$MdT&8
zYel5q1!@lY@r^|J>Wy>wK9e?l-1ZQzyI0?ry7*DlG>iLp(A0x{_{g<eWl=sMV{LS_
z-`Ea4`zGusf%}W==)>nOYY|9$(nRyOiw#MWW-pLxwpa_W-yFmTt1vQVpcrhM)eEQ3
z+z?aviP=Xk)POf1m*1+#m!F$tpE}EA*#!Z&<&07Cz1F5}uvdHwcA#&o6_a6}BxZ=`
z7MOPp*cUS;<|#Y=cjC$>WL8}YJ}<x6Kb;)g!DjDy$D?Y}M#&lp#rr%+odL^d8LGLk
zfT2vs#rPZCf%Sb`Cz7{W+uGm_j_7f209e){gW1Kd%C}=`4G0-E36C{NIzT$N1yy0b
zj7OF7hUBpYMIqsNsi8Gk_1;U4v>4LBANF^(^n2`u6ECxR5)@J|{ex99=11A+nxCxQ
zdrY4iyDJZ2ou99&X_9igr<{^zrX*O;D^M6Ocgq$spL@;h#M{1Og6X5uFYR{N43ed`
z@B<sp-Ji^@x5}U6spcu#Uckx?SO6`V1~oI<<<WqbXyW{JCcYMRo&ut6Odp@9&^4UH
zR7_Hpb@3tg=<@H6I#>gj=Fru%Dz^!*ue%<N!8dI5E6z1W;dkPG+`IIx5sR}8YOqd*
zS(v#4PYrn+hks(OBY$Cym^Zt`a!V!fuCxz{-1>x2e6qCUpuDT%I1IkV>LW9@fS)j0
z##Fz%lk+v6tle@(eQ-^1OKbR~w<RQDrsRBLB@~nht6&sXEM_;v$?q|H{hpg<gFn?&
znT3EfQI)!`uDoSsvd({mKZ#fO=yg6)+O1n9CN*MWr&%9-ee<!UBBlkTO=NCaF(jR0
z1TRjfQIw$8MnyZ-RV+!ey}*g5zo36UtjM$3`gsP-Pe}D5s_9t;rqe9Jf1ZDkx@<^Z
zV%oePbCz8gaGL*m#Od;&n9pYRvE10*Wv}+g*kn?XJiEMRs>s*$;PCnr9Cq^}hQi+*
z)5y<})6@z@mK){%71MCRen@ciyIWXeu#ne)%am4~lRnJu>kGg7%ca5n8}gtDo0_(!
z=<Fd~ZTimj&F40I^sQqarqwK+L+-EjXhyGNPVGkCh=v5h?uo9x7^aVo=m}j->js_f
z0TqFmRkERHM=OQd;6bASx3|dA{9D$vF$L;&3yA$6E9#ZghwsPn4)>d?)7xRoms3s^
znU0^<g#@^ZB%}MEWZ;pbP2N+<!}HIk?1{;K3xL>#u|RgH<|F>*Iu!BQ9A}I<!`uP<
zclYF~IePMtm)vzE@?8KoDnC2?pHZ@y^k_nL;=<)AZ|pmvi*o_AX_GrXn+Vg<Ai!md
zEC<95cL!EWKAL$lZ)!IKDcW2X3;e~5<6&y6<eYFT`blBfPi@w+)Vr`<g7oi&K~p|m
z-VG2hSz@mQyCjp@(%WvxyBSq6fRLTgJIR-``TL0=fHTw{=#(|0mp6Q7J@bm2Bi!tE
zEAww|c95Gre{PjZte#2vcW5;N`c5{}i2}8I*<W|F(-}iLG<%@5_A{R_&8;coq0hF5
zjO?>QC>~zy6T_B=Q!~$MW)$-hCIU6$wzRNYEm!Guer-XF^MiG^@-|-&A%AvwcP24+
zVRM}qrliYAteD@;%;>i&@0n+ICVxNX<o=j5N<?}!Eyrfx6+%X#&y=rbez7~5%cAp{
z5d|E^HDq!o+m$7MOkhvD|Lp1%)H#;f3DWHd*$IranC?&bRGzG1$xg%&zn7ZXkvc7G
zS#7e~Y%#Izm}~QLwSB!h$xLsup%CTLXcGU<VzUNt2m#o>N8k6gEmTv8!ijvoF!i0f
zNZdj!+Gt2#q}IDnK2SJ|Yc$!cwJWQ)dD%|Vwus=b|HdeU8Bsqe_$=?RiHRv|zxAdz
zAx;PsBi1AUo)9Arq)kBhWsN6FpD-5KPb((sPb@kr84vXnGBqXDw}is4s$95odA`A4
z`AS`-)yRI(9BA5dwX&lm$C^S(hqtiO#r0MBbwS*?Ymxz&|2LJ_rjPUEt)8^^<oTnA
zchljc=7b;H?AGPU@m$&4x>astlxYY1+;XMTeM3l4LD7V+>M6!#F~MAU5`;#Zztsn|
zl_b6?KSEiMfLDhVupw3))yIbK!s0si(L8={^a-(*Q4Q4;798blub(gK(%hG?2M@5&
z3RAA+La;uCeSicljC|nj$2o(Zw1BpT4s1{tHG{Oearv(1O*M0B18;frXg$Y|_1Tg=
z!JPcY7IP!3(w2M)+jt)wSmjU+br&4;)psg+;x_;{De*ok$bVtgF}lmKqHVE@XsJWH
z{Pf88K|OZ?{o2I^ypca@1NTiiM+@09qB}I{W8;C>MX=5O7(_&(L}qnwv+TZSDb&_N
z1QOjx^%UyP8d@0tO6XMim~!$YiTW7ytG@tj!()RGK)0!}kYQ<ot%~MG*F{4m+tz@v
zpaG(f3!Qv?b3Iy{4*}o@y>n=`qPCrTQB|q#ZEM~8x$EYXUD#P79=46d{P?XmPFoei
zCki>{;?R{U0b>sWj|gdrP&l6jvh+NcYF!KO(=}IiC0q7~9*BnkLJ)vvCcxGL-V${J
zT*@S;{BV+zK7F9XC9t)X-=1(VuY}j)J|tJV<W+MnGphP+LbRZ`poDaa%SOW1poU}$
z`)>04eH9H-1HNn(X2fI*cv@F+F-2&opJmU%4)TfqSGNqh@Ff2o*zFNmyb`JkcuP1(
zy?D_WZPxw3Ch8PNV~36_AJsuZPw--}DGRS^oWUkEQ>=~@UdXpbX`f5?CCas>4kZ|j
zR*PI^$qegll&*|B|C`To=-gPIUvLfJ@AzOV0#;t>TaG^Z*5BH;QayXFK`a^uYt=pn
zHB03@fM5c`?3zh48;Q`5QO0-i%XBI80v}AKwfF+{`5U+9(^VgFb7dl%YHD~_QOx0;
zzg}iy&CEgs^k#zVi~BlR=zvA(O|zmB)zm-+hk&Yz_V7jCr~IZaD?7s#Bt95ODK13P
zU>8XL@Q=cud3A5g9b5VZtLK#1Y6%Gtn)tT#%qr~J1hKzHE*99_#ROoZwZ0ytCo~S4
z6B*0Tx{ad`hIV<;Q?l6dA34S`F|9_x84Ujc^)>#A2if77hK+Zui9BXORb|<+vb-l>
ziN*XL)@f0(jmz39x*YMI4Sc0xUP{TSJe^UNvDrLb9ndO1uC$sruejLyol(ZYE1<Ym
zuH0g(tmB@doXfPls#3LOMN6xVpF*T-h5Zb1J|#?dMX?yl&!D1=E6P80aaL9?sI0u*
z-N;En!cSRkU6I07*}qhx+=YozNk#YEa_U5dWp0tl9d`q^v0=U;2{v};+TA?;fRB8I
zagwRTG)k!|iK38n(cE+s_rAQO+{Ua#TW-EUX};3YV@mbH&$#L)DJzf^U8#0P>6~h6
zjk?+*NaUdm^!GP0=A!imCG2G|H|jSfMy17hXa@2V^K=YZD&Hhnsl!%njrAk4uQ99h
zQN4Icuui%(Yhl<<@lY@G?ns(}<qhA3!3gs@Tc;hg(VB)DklHbX4zK%f$9}(|K~Fbo
zZ%~A`#Y)JDh~hBi-)$3-aeQ^XD=Z-|TpKPtdOCkY_(b$UJf7M&8Tp+}^x5Q<obj|+
zJ35*0X~Hcd9l5b@^5=IpnT~gn=X2^!cJ;yUYzmzx&F2aiY95WwH_PXn`u$Jm$>jaD
zx6_Mvf1mk|Y*xDPd9!-Xm~H8+crNAPTRGJWKExI{ofq#bfeJ;;5wzGFJa?V&4~&s#
zc||4r_f^VEF&Zf?n#B(7mSAG#KN7FT?Ibj2g?Z$Kf9MPO)hbXZq>WnS^C>$D0*ku7
z!kr1LN>nG3^hwBtH?%{1bQVl72DA@VmT0kyBNbzIZKn(VxP$;5+j<OZdK%gU&j9nJ
zb$5EB=o8k*T1VjN8IXXrN2Yy9mHJ5Di-#Y6-xIoFx^Wl`3z_I+ubz^$2iJ2XE6qiv
zk3u(vo=8((l9MUgGW@h~HN|O(_Y|ZUac0MK*ujejr7G4}e&bpeQ0eC(Tpht=6n)5h
zRG15UHzBGF#~~>f^?G9)#%)G>M_m@04TYA3ZWxU56G&MThKtpSXH^rxrac2jtKD@R
z$|kTFv2cX#pymd>txaF!$Ht9`71$%}$c!cpZjPZuGO<V#B$@W?B=|rfWBw)e;r%9Z
zP0$bWBGP@2Y^*}Qn~g~F%$s{H-8({92c*K{mdGiwk(=s>SdD9Dh-c^(wI=y+?Rlgs
zbm40SaU|u4BNM?xy&)Cs<&Me5XOlxfxoSIS%kE8(3i*o4KMQ=r`iyoXa6{LuG(+5J
z2B6fIAf-d(SO~XveZ3rh+-kwudO?&bUIt)fd<J3XU*1@MVA_7bJ)=0>e9m}c6g1V)
zH}-9@)^mM$#Y240+>(n*Dvt2{eIQ5D0q2FIudzgBiRqKvmA^+(yfbi(gG4Y<AYB*0
z3EQSkWE0Cmr=2t>;WJ{rP1m<MVB_B@q^j4*mrXM4eZ$5yWytO)U4)^<`@6d?{Rq<Q
z_qd_*!kET0cc0dE<#pS@s`geYkh?YRCT>&w;jrEf_H&A-cyYc7qI>eRyE{uq$VVvF
z!QxHBoA+4jYf{G__{3_MpTRhhoy_ha+Gw5!29=Ng8W1gro!Eo-0yn7pj1dzc#rt>W
zw(24rN8^sM9|T^J++x{<G}8ok0`B2ou`cS`mb}hzUsaq_u(lamqS~IVKkDKu+Y8^w
zMtqD9jw14lcS`L%Jo!9nKV;v|pNj2KjB$5HYg{UNB+o+b1NLx6nznCEhAH;YLfdw4
z*u|s`U_Jz+LW?MJ<lq`+*Z@EaS`z8UsO-F#g)y@@vo6PCFFyz@K}LIw3?i22EvZ&}
zxb<|dQLOi=y+J=weKLJYEtyzt&zU?oZC70B%^HvQtFbv9EE6NYiCp4%(RM=CnhNeo
z^=4><a<xD+oT-nUpW20eBDaHcw<2QuK*rU_9PQygL%IFz<dNJUz7+KuxW^OTdEA5f
zSr{3<=}5aRe#DJKpx|eEJq<L-Y_~4xGR1KO+KgQQKP$4exp;JX2kV~EDZ>*Y75IZ5
zO#?XMWZCJ=qIsc~xiNEnB&+A1{FTTfy<@0z4>hYti95vO$=#a+XG`t_=9A^)JCTeX
znbIHOeWHCPRc)gZ<_ZSD&kIIQeb=!o(7s6+5?H(4jzN*AzCrkS`FK>4c@id~^|(73
zF^Gf>vGDW*+^qH~?~CTk*ma3&h43ZZsCvDncaVsy?E2TEjcXkS1{mG|=elUvTY<Ax
z7WkXTCzoY7ev~Fbnj!KBdbg~0OILwZ{U_h{{-T7*8tjds_cQRu1f!V&&s6*J8+zr;
z%BfpA=M17+ube0J{MzV>B9+)pvc*`1t53Z?AW!v?=;@BLp)+&A8@U@+4pHZLE<)bl
zylu`mUN=O~9<A9HcWV9X%=Uqv{L&eV%4F;c6MrI8E$eH+2mskt;a&X)gFJ&3KEF4_
zHx6|0AF6X30HK^>8$%_Z{?r9!^ks%|i#0dn`0)7VJ`(yV0Xz!!bOGEXuh0B-!fbwY
zH0-xugZuG%yZE|vsbLNoTkIFZ=Fu&#KyU8mqf%BwM7zoHP40&Fex!lYbn1CVoZ&yl
zf_g%yj%Vw>Q%?BgneO2XLv<p_e||fig=s~|=;uO}13cLX<3NPK7NnreDz|<sE|Ch|
zQM;C!dK0S<ns{1yk`{>Qk=8DxI7Yd_SFV<Hz4jKkIV#Ta{C0a~B`<VISUc@Z@9#yF
zFi`|2I9nV%9?aJ_8*BnYgRV`dEoR+a;f0X@g#FCr3>($hgN75wgS#+F=K)RYqdAoa
z?V*Zhu^l1`o*C`+2z#b2L0f-9cRP?!f?3195%hcq_7JNwVrHIeG4g$n)Odn%?3Q_$
z#ZLxyBJ7m+oltqmW(r+>WrR{cAiJ}`43Hv(D^pSbXpo8JCw&>ask<L4(E)u#e=>N~
z5XTeR0s|Ex#)Z|J^+u^ienImzy0=J()@H$WaI|}LC}3F-mugtL?e#~r$JDAl1^gM0
z{YRS~MqU{d$E&?N7eF)w%VZcuT?93%3aF_=b@T*QCiIfYz$B%&h;$J{S>Up%CZR*z
zeRteZB|g1tM23QE;$~iIqHbnig^EH=z1?uS7d)Ec5N(`-vS#(*U~(iq(_(yNVNQ*~
z#89dWU%^vJ=Z)6ZJ<W~ZT)d8K#8j3wzo6To^3H6UQ%7;6URmi!c<X%3x6kHpI*I}c
z`$3Fy<0K=1?_`-dXHN{`CjK*S(edhl@?oVQ@U)>aAssu72EA5eC5A6;ppr`cPC@PA
z&rJ?xy4=KsFvNJm^6^66T(MhTQaT3&CpXIyY+;e2Dg_8x5V#>J(T@Se#Jt%GE&)e%
zvLtZkaRvJR&=HuzyxB@?nLFrm4O4{uuZ#YJ>3f-R3<m{ATVV~ZIK@gurJO!hOwlS4
zRB5b!-e9<CJW4)z5YwKtRf(?QR+Zj&v-@QdfX3>(MSA|)CcdHJ65b+Krt|K|*sT(6
zw(7L!s;ea`&XwUeCOIthW~qn^wRukLbgG$T)GJ;c=C&CYS*U53p05~!7zMQ&8fp1=
z%As?CM7?E!UcludfG1|tX+w*a1_#{$cmW14Tycy><I~w<j>jRH*kf#~oYLhqEUMAE
z#;0|LVB!S7;L2KxjFlf~`q1BlDStu@!4($9{2)#lLIXLpts@)}DlOX1Fe#lHR*&)x
zHMhcGG;8cF(vJfRAK}%Y8@@8jJ^Eoa6bhC<@}m=2BFq%+JwJFEwVe5ijSozf=Y6ji
z^;0#%u5sT1KOA3rA_(KkWK^z=%e+1eL9DDhg?~t1O-E6+#x3Q%@j;c*&=#jO#O9rf
zNXXX5xe<MfBjhVwUy|u(*@2)IL8ThI9qO`1-WUljfeD?0@^{HkwXv29ZVLS8pU+-%
zWO51{EnSYIb7EN&@uZnAXj6V*oki2?_2yFb2S2Z(o*Rpf{nbHqJmFZB!==ki57aCx
z`s<qe@ktl62vCy_pyZ60KO*T%RzngbL&cZ*8~&6Gs3eJM$k)|>{*msxp3VC`HsOM)
zz@V<*RnvLq{{ns@g}x=LI%2>iW%2EsJaxB{J~#$?3BWuFv=jK#w!Le<OsxX+)vhR&
zVQTj}6Ki_=$&aHxFUh5$J5*ZT-_)qUb6DI)hiR{%iKWVH!v;^Vt)o=UBvI+<k4CV)
zpT$Ns;!a|vBp_T^ZdwqWMFr9^GnLS5!J7o{9jScyo0<(~kzix$M5Ejc^B9s<a$pW8
z*>IRvr<JOh?$_`21CWYj^$vCNMrV#pi|WVbi^;`LNPmr3E-a*Q`{Wv%P*E7$OdLyW
z1ic#MC9YJol~y5%uae72W}H!K-uEYPDUdN__+D)GSD&~!rH;a^7OD~cF$8UVGytXs
zuG>gFOd+*ov!<IZvVtYfiKGrTtisIi)(t^h3bkJ(F|5`s6>j>MMC#TNS__%l9K#*c
z_lzn-q5w^TV|q~o{KZo=QGkl=2rdOuC0!HAbUEj=CcCg^9k0`VUKMbLFLpO~x0x^E
zib*VfH!d!mtfADD73do15-2O4DG|%8zoSaBKJXyERa3VD>RoNObM_mti(=7nIFvSB
z9DBF*b(AfU5Q)}_H|;iE%v|Eo*{xyK;iQvjAh%cWE`sx3X7jV+H1B<>8j`@>%}s6Z
z&W<3SF@@tVmqOCO3=mpymnT-F5$)PHx9C}#Jn3grv0_EQO|^dVNbKNb{|pIR2KDz(
zf>H=tq<sNHux`;%AL&M5^x?<jAQfmnPaR64aXsL7vOM4y;Ec2F9n6Qk3oytRg<3HM
z@Yl_g<DYe#c3vO7UoDO}&b1NWy5vmCJfHT9EB@Nm8S0VPr@<51y2iQ9MyQ{=y;f}<
zn1*+Y@q44|Od11!f$}D>!}ST@^k+!GeND<rj=iPe+B~o=yt=$fClX81i6O}U)Al61
zo@);Ayo-<hOj5h2n7c{RY81YU@EL1En84?Rq&PcwC(xdb0vt%xS8G^rFva8t-#4b$
zEEE)-c$Qq6&{Y+Hxc82HIdm<#AM)({t54~JaWhv&P6Y0TN3@Ox3~ks01(BdGg>9T}
zNBkfr9CEuWV91B0@SQtZ<qWrq(;F=nUf1^Im9&GVQ+|?1;Ftks)&xCml9n->FJck_
z5a<IvR-8k&Gb9S{lMVyooL}L)uZ)GgM)SSpIr{z0=4t#Ya39xGWZGSVl1<9gxt`lD
zp0G_#@~TeYO-dd@SN5YMB`!DMEqx}jN7Xp_=*q_Z2CVs_s9!Z_H%cD{?%KOkz+J!X
zj`t2+5%Kd4v(AB&8LzJvHh(kF9P*gUm%vv62;5MrCO51C)HZf;Xl4fM7~&aYxkX(@
zBL{m&iT3NxRW6<#PvE3Yrz|^jU!fL_Cg_KvKkh(k7A{94uY$G56q?PhUEWka<&^~2
znP*^C(cDk>iCdl2Su(F=k*AjJ7(}UfG7{EY7FuWsDYX_qRh2$tSnp*iZm(f^!x$3I
zN)@;8r%C>b2)&aCJ&h=Z<olj3tA27==!f$~EGk<ld<_HwI4QaT#4y&^%zEJ03_*n6
zg+9{Z&HyNvs0?V$+!ck`&n@ik2w!BN0Lyz|^p!&afB0iuUq1uH6Vw7}U-&8bB~WzW
zjBkW-eeDSL{ijd|1m_Tfz(XyrVtk=!yfGlx&=6H|48;73by4Sz$x~K_nCpX$*H(X+
z`<O=?VG<ms&p<*P0z?nO2ysS`bnIp9edx2Z&m^m44w4P2Qo|O{2$P1<oMaf2DP2cj
z;~phwvYQR3SX27p+K8uM?0?xpcaP|;iDE%y<e?r~z1bdL&nOhW)jT#oCjQ3Zc79tb
zHF&e#zV1~BT00&mx1&@O5pcxp2q7n@$}<8)lb^bV+U!2s3hfKE!_?+H$$QAZDm=d_
znwWc$Hx-zdTGBenm@_&N-iwyung620rpuzuV#YX$;x>q>-DEXgGhhsVJWM8Hi~3`x
z0`7q+y&k{_ty_R|oI|NbXbg6YsD_j1gfoM!=JLh16H&}O=YiGuFKXnRim*c>IObUk
zvFpqM??8n41T|t81ON?s?`Om@@GPc|Qnsj5_fZ`lYq}FY3Q|WLMDNuhsz7m&H*i9K
z(OOh7d53ajucS|3)$y;g5Ur=@cqq(tK(WiUs;0x6#Za=vEsVzhIQEp&w>eoLI<7K1
z<FnNaab($I^-aJpF!GJ9DE0T}3Y{Bq9ymbJ?K5e+<E)4qwntj75M&lGuB9mASZJBC
z<6VYjh1(LGQ{+u884y{LUZ*m3IT=M(8}Z+*DqIo@BIg+41|o10bs3dMoS|1+Au*eo
zoX;1P8J35i;W~V&Od#Sb2AOzJS)$hDkP|my$-5UeAtz8M-s$J2>tnP_!I}y{p4WSb
z%(CG_l`w1_)=WST`5eDvNcEN}YBO@rmaI-PYh{=>|Hz+zt5&{ssW4W7ZcE$Cdj?4I
zBp!b=QLlOq(7cUt7?0Uc!x?A7DY#7dg<F?7>oC?eLHAkx>(+topx9yT@gQaKAVp<A
zMdbie`B{*_nE0bOHq~3Jh#_N^@m3}6S!?{wVf+nw{4LbjdU}iqWBB;8ra0|bfc`yM
z5{;{As)CwvQqz>XdkfP&GfO%io?f_`z&I;!ReWAAi;^L^(!+!xJ=a5PxX#fA^sB3Q
z6WTK2x<~bixbd+gBm`<w;WS>tFv(HlId3sBeS-BXJAHt)Mj70!+`6&Q14)MgaUIQl
zwAygz6bCB)tES=P?56;`EtvB0=K=@zH;)&@5j4wV8!_zF2v60=WWSe|K*tvtvcmf5
zNDbCp@b@a~0Q)<#_2if{j#etP<%F;^y7eM_55Y?W8&FTx%VxCYru*oGVdvv#E&omF
zc$#NU-Wx;gg$^}dooWy85bSl0K*|CSG`!W4-<|%HCBL&!v=(Ra!jFou`iYtDPqCP<
zktGd+J)`y{?$ql<?X`0~f+Wbnk$<PU55m~ZLfc*B?>max+nqE%<5J99xeX_iaJnRI
z=!qy-9QF-4hGl)yayGe2c5BjcPtIzV;GwHIt!g8bx({h8wGTD+1yD-d1<EH37Dy8o
z%9p~d6PHl7N-5~%loklsOX9gXF4mv?yn0tSrtJ_`>2iciFRA*#!&$CBA=yyAH@Kvg
z?l=)i8T80jiV3(=B@3TWyvJG<yFZWqb#KBf%UVB|y>d{>Gqzd=cZj2Cu%UK>fD+*h
zD0^im47uFTO|Rlk;u#}#zdTkg<<_k)-~5A#%Kio#YJ*JQeWbjq>?E?`+yI}8aJ`Wm
zY{f92^;TVuc@valX8t#1TW{?B5%Q60^^4VGS*MWv?$_{rIZQM$Omp@Eq4`22x%ufF
zWqwfHKVTpjlmeRUQ%)Os0lgxum5Tk^aw;@#S$ZTz@4niH?F9m2O@s}^Ohicrlc@=e
z9Aq43$}@(uf(ZkO#%a3ZUtLXw6ZG|o*G_9kcAE0fcLvlFqHbWVgoO&iDK*gJy5z|>
z*9J?%wv8#+!xn4O25*j#JjQM1+ws&btHaVxsx7ed?$W6M#OyP|=IRYcXi*D#Y5pA6
z0Sy_#Bnz==MK_WNBFpE^E>`B)MRwD>3zXOB7CgCtt%bIFL2b9wbt)>ulY_dky0F5Z
z5)|ubVx9)2LtGau%k<|D-_05F9~T*!MY6M&k(@&LJ&h%#9IIUC8nT^gVX+^*8|4hC
z#$U}yPHz}PomY;nftTsUgvFPIV-c%|c?TEb<@tgi8g{?D!?bmQ!a}G#c6P#0TC)?v
z=`=980atu)lFC@YA8*oPceeaFu<pD$3Wm50j)>_frVNf^b&`C{iN7JFvE2L(hvOjp
zb2&o<tJz~FWO6>){60+lu#4_Ez2&s|S3ToNi1undr<Ojy^Z4C-#z-?ZdOEn&y9yrH
zyMqAf+)a#UrcQq-OJSaDa6X*TPcE)3klFj-wk~7XinLW)Tba7u3QdiJbgZ3V<Bw+*
z9poCDbXU^2P(P}^UnHxZKkS^+#5xVJsST{s^jfy*DpMNHYx^MH-GgXR7;4e{{mipl
ze8u+)wpUl!<TS+J-+A0N#5O1;OQGtlI7_}MP0o^Mb4oTc*@$=I#k(VmH@69su1OXd
z2l69#{Lu;qt)QMW({FG@r+D!7PpTens(4TqmC;0XRE%&I*>RU9QigCQ1m5!(9EoRU
zDzD%fb{GU7SYha!FOm_k-ZFb|Ol;>ZP8%1WMDIiR0bccD!cWIhw3+bwrVb*>vxh+5
zwoG2)isX>@(wmxW^NiLlv<)2(p2r(Rw?8}}tavid1gzUQz!}|SKBzckT=MRDi7~D*
zt}?z4OK}Dy(bsXk1VJRw&+&AyfhDNWu#-Ao54Jk0AMJ4f<rOLvzZp`<^2t^_N<_qC
zbWf!7x^k?@v%}WaNwi)l!|bzoQ`qbnJzTI?(d>5~Z=_0HxXsn`PdN0vtE+$Om3+BP
z|L0)Izc;8rK7fEImm%-}ef|H{*!`D5#r6+6>t6=de+p6m*9O&>6-32A%lu_fF*1J{
zRE)I$lR@?6*8T;#{%ITi3!xGf=2QN!2-V*l{}28Y>;EY~^<PEZ|B;{i_wD_!@)Yym
zgZ;mkr~ZRX`=3>&|3Vo3ZQ;K&HUIC&`2Pbs^&gVj*SGlpicb9}_ViE0=`Td}7nJ%J
z?DQ9n`X9Id?q~grME!F=!#{zjzsrB1QD5o*LZtqpQh%qvSk&Kgf6M#>vij%x-+lim
z{{=_=WBIlHci&$K>n~3Ax81*W{;S@<X@94`b^cBJJN>KN-#mZI{Ad1uqE&yl8EO9m
zzWTfV_Za?``B%Ar)%iE=?{TwzfmQ!2V)b8<wEsO~#l-OM5vzP!guqKTXdDxG0)H!A
zVSdr)B>N>CD`y;E-vpsFAp2oF8=gU>Of9Mq!TrYcmsTl~^uC8FmjrR|r(CvHvCOv4
z`wQkZuid#3tyXO+`O1~5RKdZn1N9j5xWL<?AuIbu0UvBdHDVrtE9U1AceRGT5ihwf
z(u#fa9_`-VREx)HmVgrba`$Pwim%*AsdORp&`{^}TEokUJj_JL==1b){5qSe3p-x{
z<2#uolfbF9!8)tXBU&-)K0Rj=`Qvu!T<`t)Cx?ANLb1bb@dImIF!E?297O({obhEM
z@gGkavwTYWKQPl&MsTU}s7sWk8wl%iodo7&Dxu;BOa(=2ynha;_AvLU#VME{LT@^b
zk!EE5n{*En+mVQDq{TM;k=ns6lKh)u>$m2?Bzw}Q9iX+_a=~nfOS?6OJw_<fd&-6U
zS<qDWwD`=gP${F0ebj!zZZMrz^jN4-z-kLjVzdVnGr2N!sst<|=>#+(VD9Z3P3`?q
z!KFtsf;cwUrgoxKOT5ywt<N<nqQA<h&Ha|eAO=2}jJ7nzaB8_k5O*i(2|B4xpD&X9
z&U6%~r4S!FbF&a8hz6sjhVT<a9jUekRWLaTfSblJu?g^O`+AshxmdmUqY6rFccqj6
z`=S30NUD}*L|luN=qTsyQmDZNTS{8nqaN{q8M=uadZeCy>tX+|5W1}0NfO+4w%C7r
z6Zpr~_rG6m{`V&vBP|^p+y7#wMS4Pc{u)SfQF@frnPr%DaG6}rZ<%)xV<0dy>;YVR
zL4NoAV_X9SA&O8-*sbet5C=5atxtr97fb0}2Zc9OW%Z2Fhm=?$Fuc9BE~Oez8R6ms
zH>yV@%^foSjnGSJo<Z2~@%5d1d0k1%OA_a@<K=VHLkS232#glaG-rdc{dSO|%ejxB
zWS;}b^SpZ;r^Pyb%5BpI=;_6LZo!Gcyg6FqTyXU<_xx$RX~P@suzYFyfdQy{>*@is
z3V9-*YwK9SRHNg*wN3aVdVLJ&D$1cm?)}NB$$M|Kh2;~~*F+M?)Mm40*V)PVV2~E*
z(-RozxD!*vx>YH05gT}G?fj_do5&zHJ^h{T<1WzK0}Rl^Brx<hU|NWApmnP6!SL(V
zR_u~Jhb5OF-)iQ*Cv;ny%WiUsgZd3586c4UGVlgIF9w2T@C|9|w(zSEyL=eG(<0M4
zJIy`@Wm5dTAyOW#zeP*SwB*A^4}%-=r>_rT7`!s)2gkSk=n?`yWm;2^%ksOq*Vdoy
z5Q?)X?y_6_F85Nm=CQ?+Pg&7vz>cVx4hk;}4dL4D%ALwTNz>{&WuBagU5c<D&ZX$W
z)$~YZ?`pCD>c2?S#*KrGX0ZRDfRjhoA1iWZ4x>d#<Z8D=TkErguoOasH_<iKHWk`f
z;E+Z4*&T2{bl$nXy4v}?ZgzL&!lB3nc_XrGC|;U8)OgG=8kPdx34_Q3sNxkt5o0GH
zfN-Fe@@s2;K?m-NEgxD)5UrOg#_u<OyC>+NN)pyEV>_lOSjPWttRS}hD=yYo5MNKc
z&Vk#;;9^oli`ty4Oq0{R3G>Igbwi$d`oz~u%3ZltsI`6{5vlE_Er9ZzB3)teH+h26
z>p8)2DW(z{Y_heR*b1_lf!2fUX#jUu<O0SAb^|xmy92A2(vhulx$CmQAB#q<88XE`
z1t6J9KSgI{(`JU<z29jCsMMQ|O>OE}g#2D~MGzNG^Ye94=C;x2P_^oh327%Y=dH9Y
zV2d)7F}f*Q=pGLWRE?rQ)*sVD2FQ6`z^3UTPyLX|!X`qFYyo_qL)Ur;MHTU&N+cmf
zaKlWM^~y7znG@vkKhW>{SI~ol;F=~i$iH5Z$eXyR3;-vLDAFtAd2m_d1ZpMO)Bnt$
z?ACdCU#+@G=lUtBotc?RZXN1jg42>$Gm}|>8uHzOIslmTE~vG2tQ`3nc5!@c%-ckz
zfGdu)+`txZzP^%ym=I~%@@-{V>8gD3AV3X#<Tbv<;ZE!Yw<Z7~iGdNk>j&2n>QAw}
zg$Vo)<-AayL{c?M({q;X$#9pQ@QdCkV*8Yl-&>UOAY@urt<13BkCHM5Db5*{F>YF&
zurG&(p07uM%ahbDSz3fNTZKlfO{ONdU=g+6{H=SG638gS<7i*H!9^N!#E#t49MuVU
z{HZHw?4mukSlWj=czk(wzRsBuhKWy<Eqm`Um;6KTC&;eFk5M4ZX%32_VSI}Y3m>q~
zqvyEn83J4I#a7H>sEC~4&MOS$IjJicZTOU6NrED%Sv+I|cA68@V(JStGCMifX>v7z
zWIf5#Y+-(eqDuBe?Y5JtZl!eii0vOC1VukoY&PyV5e|!dp{U|oO0%-EdW6zHu%C{l
zbwR9KZ>f$eyW7Xj%-n09c_W-pv}pGvm*N%iQ&5m3XY^dkalzin?`}$n>q`#m#K~c%
zOur~F#hjFBaf?5Cx0l+4Lq{6`In|H|=HqCN5{{I%pf)QPj?0@3yiLTtlK>}K5&x=N
zz7aXtoPhxC7rpO@M?F1!hDQb8ULU6Qy6ro^y-w`Wn)L8%_7%Z7zqDhs^!3NOl_a*c
zdWt4<S(}t1hgpz|`7va-8x4)N>2$spY4K=jwCsn!XSZG?;Ajcsc$!c4$h7l(+=qNV
zBz$@u_O2*AwllukKzwZP5C{x&%Zs9#91ZdMuQ19Wb&#ze7c4l$_R&L9nPb?LMYTLS
zeMe<yid>z3U|SCglD|&?eV@SPo>)$KMW*AEwoJT&Q*3dC!8wZLk@$qTn*PjP-2*d_
zv!X}-vqDK3Lb#0{1Gfbx>ng<&)d@{c#boxv$rz|cFfeDaQW~AN5Pup~F#&5w@M|0j
zbsm3p2MVXP%uek49$}aoJUHb>>@d6HJ8}Cy%Qly{-;rO!ZajHNy3#k65_6>WbDZcM
z0oncad{?xpjBbz22}Pt+uvWARRM#K?|Lm|i^!Kko(Nvj(&b1HfSmim|ex-N?z~<(V
zsY?Q63d>*5p_P7%B$pfW9I7KHE7TsP+2a4$mAA#iJU}f^77VrMCTf)c3Jc7OJ*<U7
z?a>b_gLO@?1`WXl^dUCmbizp0@Nrd>WQ6lvIKnj(YtFH%W7$u46SXKRrrKxP(N*Q{
zJ-Q&@^QFx$(&TzO6>*2VD;ti-sr@d3?W303<@nsad%cQD69(`@gPlj`tmA;i6W|8<
z^9IOgJ70DT>n_GMe<R+lgHK&S?t@B2q->N8Kqd*X3hu|RUkwXd*nV)2OTAAu_(9n^
zVmROzNud#zhb8LRHmzL7zo{GJPC&MLX5+wdp*F*l2J1`{@*TorrLw#%{dmaOyVgf-
z3K8@D<LO60Ok^Jks`EEp{R4?zP_1&Zhd<Wjeum4yKnjA+PWfT!B%_^t_@e>rsDjx6
zkYxt%C;H{tf=NwbMpW@|$d9=~QNIeE9BHhu8URix*3<b<C57LAQxOhPF>Vu}(&vRP
zl&?Q6DmP7NL<vFS09u`Z6`$*?whUChKhc*n*|!QyFSdq(55le^al=}DYBp`%wuV{f
zo;Te?as$%wU&%b9tRY&012p^m?rz45vQX3AU%YlP%smuhd<r$La>?h{V(u_>MDEFh
zCWuC-A?D|eP8Uv}QhME+jo%;c+ZJa}S!hSu_XHPuAB@I@eH2JhVlx&SW@pAwJ{SN=
zq!kZ5<*H)RV#PI`8S#wrour6g0>+Hj(aq5b>cUu+Mwed_M=~2}ML1j%X=NFmDh|_3
zkrNG}#`lqh-uWZ84Q{=ot0HU509%J9y-3l0ctabPN8&qJZwU;!eGoPnr4PY}Ds8T2
zv(DfICS{wt91)<sR2c#xk#`6X+K`I!1uJ)8%1jSrr!$+cXkXzDHrThL;gq9XgPXd%
z@X5;z0bRE<yP`PXYWb!rZ1oY!GSZ+%VNc%kt=3a*A<B-D8|PE6>XNLYCDBWh&rKyq
z10!Hp+!-5bk+s9gU-oP7OFx26dr#3EQZKwa(!?Bmr6^Zx5Pebvl~E`u4e0AflbunF
zvT2WQpNT{`)fKlx-9-yyVM~u5E+n-h9#Pu1MIUpm%P^bVURkIktF^I?agK@yUrAob
zrfBXJ-iH}+Ts%hK1=7D^&K(d;7rTtYHlKS-wcX@7kECe|CZ#$EPrK~L$548Mrv7+S
zA^3bPt_?HW7M=poKE<g1bkWcRXdu@bYDRv`9p5mP0K=<gED;gXA}_J91w@ZUQCsT%
zc0@&~c3ZaBcV^!+;_qEs+zKS<LnTb4XJ&6e`sT@G>CxKS)+(N<on8CjPJ40NXp1B4
zU9u^d5@Y1mFP@8)iNjbA^U7B~9jc)ahV*OcU~FA;#Wv=!NJOO)J<7e3f6=Jks|s8$
zTNk>3S<zZeN-k@oupX<t9Myrbt*E??x!AEHO-uIl?$&Y%M{+q=BY(oCp5&{qc!$M&
z*?q_3*u_$gJHd6cOgP)OEdc_zj=HtH@v2tl7>r%Jq4|<Z0eGV}6Rz|&kZV`n9(ULC
z-Q^Pfm>8fy3Y9UbS&z8)Q?TFD@RRkv=21(XY0*k+$hx<X9(ZplxIhfR{YbTJOZ18D
zPY8f_n|{Tln#x;U0eSqP<T6UKWld}XmL!qlJqcXPKZX%Ta))&C^8$G7&N*86jaqu1
zv7~9vqq4-6^lbdeNP2{o#In4~U~2xYx%QB46I;|rhbv}=;xM@7Qn}VR%Td|c#KHWV
z)==Dvc^MXMISNsVLl%=)L*Of=Y%YFUg%I6+$srVy!^h`I=DSSDIGR@4<CJp00hJf?
z79Ii_x&}&9jUZJ>%BsqW%1$&VT6W9Aqf*JQ&#!^6ln+iDG9IO(Ru)khJK{NOzbE(p
zO!fdF&{c6xs0;uK$#+a1AC(F1cncf>7)WMGC>(+bOCd{t%H0R$wFqpInnoS@HmDSC
zND$TfWHiraUrFzl2wJXxC6(tqF68_^flDCbNeXDm1tV1xs?`*x`S8+D7N6`%=lw-^
zMYB?dizpUJLX1SrWrxQXMWV~!3qh2XkBawpnVOy!iOU#<z|SgM;#|{OSyl&n#wsB}
z+1}j?j9M2#t#fyc3fC?AvI8I<*JWCGF=hk>y%W1!KqPHub*Q42idiTcLXhWGM!*T6
zY|$(J8n=Z15xfoZp(z;lTL~4+z*xmaMg@N0Dx+IY5+G%jpAueJ1|l;215Elimp*K7
z;}VDi6Qp}{9W;ee1Oq8vp^ZSfb`ede9c?QVSlKkRhVR3}gU2ONGe#u7Wz^Jd(MTHd
z0^;p#H@g3f2**?cei$bQS=>%@<w|9q3Cj~c`NRpTgpx9q5{|mR>dJd^nJ>4I3&w8{
za&X0)l07K6>`#`^ECyT2WJEl2mL--L*a&^PNZglnk&x-fF-F$Y>FvCMKuH81HcNB;
z`?TQwpN|B?kVNRHeOcl^m-DRqDQfkupVovi>m<1QXc1%Q=FfZ1$spJv_&nwWsb0%n
z7mYM{5GUUD-Ub^Q1mnpGk%I(YFFWn|rpTVo;*X9oTWa&sxU;nCT?HmjUag%-vtO3-
zq6b{8LN7aNE2&n~FDVb1B@OXaOdlsdj%L5FRWwu|evjaRIQ0^DE@}0oct{AXmpG0H
zg>aNVJye5ZnY1`(Y^DHLz$4jBu9dSjh(E_wlB|nSC=lN^Cn<H#JJIXL^~{m7IGpZM
z-*&{(_~?a*WE``=-E)?8ap{%bGW=puFh7IW&#8fBshP}3c$aoiPE2*mv)LGohL`c6
z?i(iqy4SLO>0N-I5S@?;jL}}LwD}#Ui@dl6TK>3QHde``Uz(6+v2d^j-QK3HX7BAz
zH1m|+cT<}X)r`3@_|#v??F)ax`lZ*q*l`49{>l7U1$8lcg!V|H@u#_odF{&Kf|yA3
z>FamRngv*Tv;nb^!)S$boPjJ)(Aq*r*D#EfhHvUvqOBeIRum1mO+;<{VlP~uOb4Tm
z5Et5Fqdu@_#{+}0>s*>zFM_T$AJ!Ju0?hbkU@wt$F9v-FVIqu#>_RrxQ;E{)v)MQE
zM#}?Z<|^pWSIN~{k7>R3(x|VAtu!jFkSF&+b{TD!sEWDIE|1AdZ&B?ERlSj{r?|*w
zEB=YFdF1ak&!stQWiUF5@vy>5-D34|n3mMcT?Ox9u~ibB!z29BT5^qdcg~JwjWKnU
zPVnbXpggQ}<}bKqSSH>~+7C-n2u-TR@KK>=a=S)a(P6dWF$FM5h*mxNpwF<Y)htcw
zmlrdL(FU^`uDE13qlfLP02M0Lb*)I{S$<bF&+RiP55+i7qL*4h@<es|RjAJlF%Gu~
zra0OWIgRu8n9a|v9ZQc9i!M)F9w);1n6P+JLTsRyE?FD3JgM7d{-BzmyilT+fC{UO
zb<DmRj+iF>T-RWNnrwoU^smqD;I)}H&vjFn&v7V2tAgTlWmbQP2VZE$FMKrUIEg@d
z`cA>YV3`SB-|)$iuNnL}AXM<%Ed+3O955fbcE4`s<rJOU#Sy?8ZQ25g%F0x1i_6ZV
zJ>lMj%zyDaxS9LQo7*u{6ha58x(}>N-7RfvARoK-Hryi;V^`zWKnJWh)7T4~JPFH`
zp5`X@A>`-*B*q~m{b4(b^-Vl6joz}hO(6{b-Y|k0WLzfRO-?h@tpDCmn5ApPRLR1%
zz`Z@`bSKYZ$jJO5_j7>WuNoZUoJZxm2WXWZ^fuL>B``|D<j6l9CcvEJaYQsi$j5U3
zq(VEDfP~2QDF(sWZAdO{<eazWQzbwRsWjT9)>s))CPED%KrY_aMk~Jd>NgwMA@s9L
z?1k;trmR~ddv36D^z;b)0yq$?d0!Y!^y^7u4=3_pKZqLRG9>;SNf~57P8IlxVORi@
z)N?XPAe;G<+@K?AgGh8mcfT1dxNd>gv{P_6U3Zy`g3&;n6hH$x9%=c|ltX_)c$$C2
z<6NY#Bfq6eVu41=v$My}BUx(|pA=0JTC@_>?5mh)N{W91M)nEsYYC*crZsLuxYrTp
zuj2I;oH<yjdVI!i;0)xqHj?D`*UL4%TD_c8?G?QkfbGTIql(p0n~C$`U?@`Lkb>AN
zhU;O~w9I($$p!*{-DqQvla9^>2`ehd<Jx5@_v|CDulVHbn4qW&{y5~ZDitNZ9P0G0
zzcE^AYv@L^dKC%U0(S*9_1Zczm$O=P#ri2Tlddij?;KBN7MnvWtyftoc(s%m4Ju&v
zcBEv7pzeamVzS*Gi0?ao{)e(qPsVDL1p%sQEkw>?zIAgi?8xLX-*C=mBUnx<WLqj^
zXDX@RvQY`Uz(r!Lyy7#%b{@3~DXYxYWX2#nr$do;cD%Gi@kwwu0THi@Cz9$kEG0_0
z#<p^JSx}ZOXKwqJThFTOhT_sYUh^XSVyH!h#z5r)&mU29PJ8j94s5mSS%m5}KhW3*
zlynyfG%{#<eeg}dqtWDP)~1{3q{y0IHi!gh)?$4b<bWrhBdK5zP#|#v+Xc35j~!aS
zG)dpSBPvIx|K>(SP#f9m6V6Ez!VkeK<glkPwllZ*qUkD!sqJzQ0BamZfZW`8<a`f$
z^7bxpNn6L%obDtJR&Zn{0qf{SzuJ764!e}6B#}(Tu{3!@hGZ>tuZGsT?LI|y;>`3Y
zR_W5y&RfyLq~m7tt&!wr`ukxagAa?V8?o0rY+)sfEQ?47j#kzi<c?hV;l#AXu|PL0
z|J}43Qp!QQH9W$(XtHk<3NwF*WmX<s4s`gDCT{MJnTvdC7Ix_JmcDIXCS54PUzEB;
z$@<sUp3GIh`i5$Y2G=O|U=*LPp(wxl5J!L$ke(5hE*6C$%$+*zZ27?cJe^g*@hy!t
z`SlAZ1Srae4+3C^JV;~zByz`^OcSQGEI<jngeM3ES3~?zUsRn&EXDXihRTIO>>-AP
zY%9`x#Af${iwa5f4Ny|!W|uH-90(pNiP8AP7&rD(>W*b+<5_(q9d@Z;XPtEV2Lau_
zi$DDbQz(#Y&B=VgJY*+@-t-@OkzP>OTTyl`;&F@B+kK$?t8~pp_of%-QH?js0=M9O
zw&^pqp0h%1y@ybEvB!{);Fm_vv3rM;-w!%sXr-S5Z5aY*2rT|t)-<174@9rv$qal8
z?l?lXlM|WXFgw5$ZBK=B^xjg2SPju#Ss3{btq<ff&7FfjQl_>;PXfL0rJn^8;b`D2
zF2O;*Tz&HS&Hb0wARPb!$eJ_y7QX4zo~9Ff<xCB(Hm=vW@D$FhZl3hmoQcd-M-{0Q
z&t}`}vd%TNfy<{fpnjdecd|n%h%#rIwTt!h^~1srwDk)+IMf!XXmb14=0!I39hjj9
zybH=9+s!&RNnM&`3ifi22<CNW-F!c(x>DvBf7lgK6aS6EbNNU?fxRjp<3vXiCq+qu
zZzNLrHjKeS;+O(U81*IR*!_8o6=~=c(c9PnICuA&52_W%MBvywVF;*m0%POI{zKI}
zi)2-$IR_;Q^_oL(`ltYhW?frE+D4GU&VyuKOQ=CqnMOxUoqJJnB{{6GOh9mjo}oV5
zzQc6M4Xm6wJs$^4HA4n=U>Ii{A|Y5619MyW34O^$WGN!envs5lUQ0-_Np;9hR#}3K
zVrwj8)mx2L9?YBB5w6~E1Jzx(ue&mxto0Dw2FZz-tqb01>Q}R?HeK7)j~hNASHCZL
zA4oP&)=@5}FTs7&Jm81U$6`QeLi=2JYQBE~HWlnh7Y1Y2h{GVv&~-~G9sz=eLXrn!
zl<+E|rtmm6O#EJT@F}DlL2?;=mA6N<h6W%|8%S7;w3z-Z=#|fDrm$o__1Wg7K1f>r
z!oPVBw;irp^y=ACf#~J*QXSczoIeDwew4jEfLS9A81D3id$vA%6kkv3y|0rIZ7-(m
zj?q1whmK_Qmz5D;=D4I_=RBrl6?Ki*j;bz=wkRwFRn>UZo+0~@ZGp?9XtyRrhr0Dj
z!ln+5LyQBSv8KQK{z4NPVb{f~l~$G7HFX*m2Q4>LsuWVptjnscQzpbBc_ClO?SD*1
z@*0^94RW_kTRT>Ty+;T8g{YgTthmxkti)cy--Qd|hp*9(8`6khR091&0vD2Bk{4X~
z4E<50zY9{hmIT<3n9x#$(>I)%byF_zw=1F9Y(k%B#B7sn{LnbYuXiK_dsbSvOLKdV
z=B*Es&y(!Vm#Zd-&d#2yKRwQvj{D+G%1v+gIyU8sGjnYuKA$mYJUkn#5;(6n_FX8L
zsbZ6F7AD7qXmDIOwggN%oGufF!uF`ZZ045Qp9z!*X9;?Slu|GuLScAQ!NBIj68#ev
za<#T>q1pcpQb4W0pYRY>Zu<EDq?3TLN=UjI#DTaFc50!mP{fG^P;%+K4FM%LNF;bR
zo27|&4$EHwElr$+V{j5-3#aFW;;we0vw&)$X?$vMBn0))5P}C03%ZQOOC-@tT=?h?
z2~JW;EKa2ihkYTRA;*x1W7acFA#ZdoS`z?GA-In}`fI3bL4Ay`io_I&=t)pOUB|Lz
z<pQ=RS7`b2P~jfaJ?4i@<AsBTsRFAP#tRfEc-uYNdh>d2o%RKmUCu(a&@C(zHV9ud
zeWU$Aft@N`&?r>}Y83Yr7SvNL=~LIJ*Qz%P!|L7Yez0Ht7JHI?vE7p7Tq$v(GwfRI
z38lOXgW=HP2s+JT%6iCKi)3Lo8=)-`V2O$(T<7!*dB?p6y>!Go;ibIqWCj@0-Q~-;
zJh808EXpr3f^(YIKRq*6$8kCIhe!Z6*jUIVBIQ8(K-m3B&BUb=NiL%T&4gBIHlf0H
zbC!rVGz7bjJtJ_mjwF0+v~F+$H;7pHM1y_n=rGUH*#>8x9Hv_$UL)=*gODSu>8pGo
z;vWR@9C?bku!wi+hl|Ene&Ot&{$b}DB<g<63LQCn)EmfIW-sKKz8eagmTWmRyyd2)
zm%aCcAHZe(-~4ML@$bF%6%x+-5qx#=NOjH4Fa7vmF!Hw|PX2$8<abfe&y)L558>pJ
z;1CF37Gy%UWkR;)7UGw&pO0vROsIgIB%w0gkc^fqsT_=&Fl&yIYeaK|HRN!F8n@<J
z^g7p~?Wl5Ix8u`u<a#-XBzB>Iw8m+0Ymi1u3Y3xJ*ek?xSGqvT5z3md-Nr#8ZJN;S
z4>Rp4>C}szh+h|)blafWEj`*)c4FnIkTv?nR2f|qU(%5hh#?mUu@;E32u<5gnwr*L
z?&*e6(i|ntQPLdEwODly2e<JKRC%AUj9jj#`~R0-2lPS@V%I_sX4m$FJvrVp(PKK)
zGu3mZht?Q4&@<FCf}8XnsB&^9>@X;GE)!0zY!fnJX=N;$2`3FoT}kB^mcy0BP)&6K
z@|38Db~q$Kk>mV?01pY!E{q8Kg_i}BK*HQP5RK;}xq;kJZX{<K&rRg0Lpca?Qf?}D
zCTGeGbsKcL{{K&>-Tt7NV-kU6(5wU@%lX;R{MZwAI3rGN=nne6f+^JC1jMIJtUZyY
z9Zr&H<iKot9+`IhFY%@(ohIR?OJSw%u6cwS_HX~x!YfAtE}Kx)XD|2YodO+MT<rMR
zN>6p^Z0}_;w~Q#Yr(lCl^P@A@-@RnRHTt(^|9&ItV=$?fu7r!faBZQyW;RGdMlPXe
z1AUpHa9F$A0AT)LUJZ&yE}Z_RU4}Nm`D}_cZO_=-O-0su8N948C~t>1%eNMG%8$b*
z3qO&6CBF&ZL1tNof{!UKEz(_bS8*AlkHwUnEYgf@F8X}51~O=C0qFHr<%&`%);ia8
z-VE*rJLH|p?Zt<{Uitpw6X5aUH^I}z1D%IDf9m^@Jk|NHzF*2`I;VYa%Wo@ZJKqI=
z_Wf5eu^g`OEiG(@gT4)gkNNIWUX*`Od_{hx_#62*MVmbm;G=D7B;b#><s*S~w2g`c
zxM)m@1iaB$G!jTfV?J4K1JDg*1wciXaSGk##e%yi`-%m*01N2eeSSspQ9Q>1P%Ng>
zTyYD6cuFDPrmE2c(L>Rx=$Yu*C=-23?}VL@!k4g0cGZr^oc*be>;BcS*EmhFU#h=b
z#}y=7g;^Z-G{Pu`%wcycakiSVvz5!sq$0P1pCtbcXTXu1pg=)#i#2Ghq^c}Cs<Py)
z0#2^_5U)7qtNM!WDl|AhUIr0huLpDy$_1KNycFP+AaMu|D-@H+(7b@Qjtr-HjzmTc
z0mbMJ=S}`)5?s?Q3rUh3vhRPHBS$Ztxfn<c6lc>o4bE*_wHA)U^Y9!TFKmo^gNcE{
z%v5n>%scZ((;e^cXyw7tJ2t07sl<D~Hj&NuAG);Tq4yp}Xr~XocNW=v3uvRZe_-`b
zf;j5XLnM31N=&vjN{~xb#@0FNl4%}$POxc4m9xZn^O#3B6CHnc93RbFWo*z%htQb&
zkE6{l<7}(Tc!i`T$tr$nzBSS9(cMux+O{2O%Mb$@oj@$yOXCYLZHx;PYOf$Be!4Eb
zR&OGrX1X0R>o`H+6t<HsYi?DE9gmVVzRuBAtD2RC3yq4dbaylBbp`_F07Ky)MKCJb
z#=7w1y{iZDnLHnlS&2=zQrL7`iA~2(X4rJOm8XPTP8i)lJT}jc8&C?6yoJ+7Ag^i8
zm5DeUijTx6;s@dv;$}5I5T|s!ierq@*;yuKPp?ttibferkW$Yp{xUN1u9a=pOxTG`
zdrDcThNFu`MRZM|N2vnPCbBN4Fu_B<N@M1?sDcaKUaQczh@w@o#${cr$|R=R)mxsB
z;eZT><Pmv7J|JI^&GKYy@^6|>Bu$&fI)z};^cYD-MHB!%nsg~)$?%6Eb8Ue6lYrqm
zPUz?+Scl6^47E!zGD2(qX_8Ne)9H-xgX@0}^}|g2f(7mEeG5LRbS#`*v?w1S;rp}=
zy3LQ`9ewTX3udD;>V_&Z!v4PX@Vd`uRT7eiU@2mZE9rwEO0{9hp5#oh6_cm@P3SHf
zFrGkqZ^F*AL(!2a;vm>JgoG{{YRvtd_=ZsB$Hy^f33Xs#j$K3b+NoyB=PAqwoiY3x
zZ)?w$K@4*>pLL^|3cA*r)|%Hc>)1_!O+of1^A7Vk7>^ze{6IaUo&~=#^WAV6+#s(H
zZjBAeL%|*LSnwg|qpk_Zg#0x88g(#s1bz?xko}?Z7I!ZAwt5lD47Jj^(fM%XVRbxq
zA;vmX`1c4kt7wVLot*?BfP>ma!~%z+<53DkrKlPmh~np(m}grrM6J;qL$BMR{fAxz
zoYCXGI_a+BLho@_(L-9IKaGfRjkr&w#DYY8TSH(3On^gR3Y-NzZlJ)oZu5WIPYw9t
zen0d#pr|`9U}cgRl_@ehV`dh$Ejmek1{lesqy5wMvC)~)`ngd;A~mfxJv~ao;pd!9
ztrgaWZV25LqCXdcpguZ?kPk-D1V<ye0!R#T&>2W_HGuT(xT|VLwi;sLmT<Ir>abL8
zriBg;!qLD9yPc0lY2HiHIuYhZ03!GS<~Bl|SQwk$3Q%fFWr`#vw~%&sS2w*f@#?3)
z{3e7)_xxQ)c0t%-iN!A8cG*>5*?aw!-DP;qv44Qf>#suFzW!t(>Ddtpue|;%Uwdy+
zerFR~Qzwutrs1#V`!w50RtOXEIZ`Afm69W{nItzqr!3Nf#gP_Jj^JpP1B-Bkq`XB4
zN{(F05sg5Jmc7bz2qeoOi8DUeq_(Gar|49gl|>q1<kL8JY+9O``X8|<Y)hpN1LGLJ
zToRqTo!`w<Ji36)pgSd&&_ReLzQ;ck7e@r=+F^T$E5z3kiL_@vz_{r8$QGVHUB3iv
z1NwHAQth2or(LIX`=?B--VV36!$>A9r${E&1F=*}U6>4~76ZZ3?r^ITG|A)GtVtpi
z2Wc9xvQOB`KxE39e54(=14ld(iKuW~olq&DO6nnX3aOk~9m+iY@ek)>jv;9@vg@bE
zrt6Moc0HJ9*v3Wy&VQQp$_feK$U<6daIPb_&}k#-sb=I_db(QD)5>4+T|%1O^P%SI
z+je#@FUMmWJx))q=(1jM`K-3IO%cr2m_L#dpoc#Av!5->rn;86GuO_pSe**Q<8d#^
zOuFH~WkJKfjnDnN$!xv_^iWR_M5#DGpM^-FDGLqkrZmWywKZ@J#XEW%aH)Q#tEbCP
z2TWV#t;$ya)&OI+nr)zcs@HV8<#y}swjK77@JM8&FjCyhJz&{m-DA7YzDIk;^h`-|
zT1(clwGt|Y%ApDZa8%BuhSf+WlPg^gFQ;mzqEZYOBgN=t<;yC|t;^fjSvFWVN*gj8
zv`_>_s6Z)F33RQK*D34#gPqrut|?zrxu$D#w~e+~GA>IX6SJtj3o^ytG3S_TZ~Tkw
z7Yk1mpD9eGzt{evHr0Ef*L@||69C((z(M#jq~LA{;j_rht<tTPCp&_H(Dq0m9DX*0
zTgu9l?siS<6K!r$v}t0y&6MOx!NlMU!r<u+I+k|x)OVmBZYx6=Ny20U#&oIRc)>xv
z?trS}pyPE1?PySYPDH*F)+8im_<+d%JbWSlyZl_9&g;u6dj4g!L4&-SFXpH6ru^T-
zrJxFzLfJ5O^}04X);~RVaT?R0nK2~(hTn|j`L^-^Y(^e{45afHr=c``ahlZXP#Q&b
zBQ-u=WL@c`CCisU#-1#}xC^b=BH9#kVhLEptd^46OVDo1v?rXg65t9<2_hp%d~A}D
z&Z8NGst(5Li#F-}4VD|NH%T{WrurZb_h@(!2*$voMYdN>MSHb`7LpVn&|Q^EhoW>)
zR7W`M?&zUId<WBDe}8nigLcOn?C&Or-F(Y~(aarjTr#VU81`4-+yk#KOtma4W??Z$
zDNGrDyHqlsoS%e1e>>r<f9IN;AJi^?>$?xH`rY3zC`bOmuY}k{!oTU*@UG8v_oimQ
z_PNz(|8{t1kIx?!%(u*Hdk$Q?`>M-Jt9IRZ>tk0v`8sc|g$wW>Kl_=X`!;vpm<|8K
z?T@Vc>_1nONCDg9H2~0en;!uhwQzovGe>-UIf6WMByTT($f%8hoGsH#$9LMWXTyn&
zuFXjTPy|ER80^yHk);*5cp~fr0FgQz>~u05GI!Hc(p2p<_DB#@JB1y|r=%D0zYoRv
zPXaqR2jEa(D8t0jmAFhZgPyn)Ac3OfHeNMGi`Ymz+Wr->wl-TX+j83xdrquvYv{=3
z535gjo=DP*>BZu5<$n5p(fp(d7IM3z6U+p=pWDwrB|YUhl;b5vVyUg|TQw@k*^Y*}
z&$hv%VYWeYdL$O!AATWBg&pyP4{8Gvl#1;cr-R{GK?=Y?173Y(Uk>IP)Vq_gU28x|
zx27}DX?IAUwcBAFhfIzP4V6jR+iR4yno-6(NU3{+(ei{1;y}w*+lXz-cE-lol<c!K
zgE}um!Hm#IKT@cRgzWX9;*I(_!<P5;&5ZTcW*pUep%uALq}<+Q!jnvR(?O7O$FZZK
znc|AT#TZF(J?x7&*z<_Ng~JZ?4INU0edqXa#=)35o<LYmXbo!Wtl^hzq}X4gY8bu7
zDkVHTq+|>i!O>8X<;r+GB@cW$n7DlH%xjtS70Tq~remWY-PBtS`${V#kz`&Eo~KvO
zJU!l)jmOiAuctOI@7w#`I~M19!j<T)E?37*uUxSlV~M$Q=A-muAWP4DAiKwt(Xhit
zWigeq0X`{nrgS30*cqG)R;v{XzN$2H2K`OV%LF?Kl5=nBiwS25lJpU>mPukGXRPHU
zZvts@@ts+i1$QK1!g5C%rY*+Rv)NoUn$KNI8bg2eTAgH#k-RY+%OD>LA!L%c8mv{k
zDbyi55-BymHUCk5B>z_8t@NJ~e@ct^fJs+{9QRTnQjX^HnQdJmMTrDrQr;vaL&<Ei
znq2SuhVL8lH<Fws(H-wjtpTfHKf8ik7GIj`PxogYWXGj($6qBLOh1?z&p#<Wh7V3W
zC!I{3OuvwSDe+SJmx*7d&*US(Y(n_X<l_@;icd3{if@s$$T48Pn%y8@o!M*ICp{?d
zRrbanOgxwz&-?c95BT;ZX)8Yn@09Lzn0TH;-!_pDAWMaz<a2~2H5Lu4Ad?LPyI>33
zBT6`oV9*0cxO57E(_OkQC*mr{ay%Q)q}`cJ8p%c?RpfX#$MLd9Ry=Vb;TD8MEFLe)
zid&YIOfse*aKj_*Lf_#zcpj)A49_2lK)VBPNx%lr>w?`bNeJ+$fWnOsWYHlAiObKy
zkAVc>;M2N2t)rVoqGeIvw|_){4S4wI6!=IchI8LMdY~|%zyk_=UU^x0U7?lF#tSmC
zLMK#v0!rwkW9_tv<-~JP0!iS3H|e4-6t*Uzo*Yk7s1H4Vl;4#qaL>X3`niBEs0i(j
zr!S<bG^SJN)bs%syW|4{891JSI2T9F=$S*Asmz%Sn;FVo%2$}i5hukzJ#!9qg`@IC
z|FlAaP=3^acFX7d)6zw}OgDXteu<>G<K%``8m&>EHagoq=6U&c9IlvKl~#+U{XY}%
z{`X`&ob6*I`ykGXNy)J!b{!#Ve&GlzT{tB+ggr->3O6n;O!}$`TzJUVVNdna05%+N
z)vZY5=rm<>grjDVC295%J75xN%vefBa=qa~a^W04lGH~s_Harcdnw7Uxea49jN$Q>
zRybaXI!^tdET_DE@aXcen>+J8cd81b8#A*%%lu~ckBQk|g?jqv#}cM+Fp{15J^b4}
zeLfqVNYFkh=Jw3|0lwFzy24Z<Vg2a)?@%jdPSDhf5+*it|2?~seipHt6sS^b=k=$V
z1%%&p3hlVS&T||;a4A5gGcMAdx>S<%uC~UisjVojdMQe)(rL|UvN8VF;5Cb^$oYh=
zYmi}6#N7r+{vCjb)x4(RaWT^*)$T)K+bPu1N~a1RikqDTopbLW!xpboz==vE_$3Gn
zdePmH9@j<sT9<0DE(YJ!Z}k9)pQ-4mG-FEvsMyfWSn%E88z3=U$zV3{Qh@hNGgU*w
zUGOJ`1=v4Ol~zbwq`eN)16jBrTU)RyyCwTE$H%g_aXTG5v-fddXW!!fo3|DhY$^?w
zhs!2?0W5HII^%SynXvLen+vm}7)V9eq{3h^<<!!&DKB+Fd?yr(?@5tuogEQj0w=VN
z3kL;Sct@pNL<LoK06RLyqYyg?45xrOI@F5;zDCNBF-i^7bnLmuz8>EtUk`1QaEOd_
zt7@UbTDe3yDJF}F3frl|f)%Ywe3uG4Ecr_Tv6e%>4o1n?wIh&ax=5^-VQu*a`=7^#
zZ5E&6C%vp<GkV!(;FnI6Jgp9uB?vOr@)wo7^PKo*gK%MoX>$k(1^vlo`_?>k&FF(8
z-&)y~?(|hx&8kXw%H@$_VL1WIyzSPt+b+NA8hul-5T~nSuk5^T_`aV{e`&YJo|}E^
z+EO@?fL=?-Hv0O(qHNne`>pM<-c48Dc=De{uauq0&TgAKNBsiHeuwE}^CUl2B9dRy
z@mLQE65lB#zEfxq__>sb+fz|Hc8218b}a6lc)z`a<x=*j$*Gy)PBR=fLvx~l2v0k!
z+!=;9gkd<L`r(j&#83I17En7?uTR(O1yrH}XL{GL%%4WW_Vd%y&$SQd)OAMfDbCdH
z4LkE@s=b3XE~7YCnc*$wPnaolqMcnFhTFooBY2l^S|Gl|Kj?le{C0b()6dxmOh`F#
zkxG?1n{s{1C{N)`q&i-tQ>W@R=@c2E(9CDZ@L45GIh}dkQq86<RoOi#ZcctldMs`h
zSRpNBhDsx)@e*S%HK3~RK`QbS>rZT_;-?b-5_={7%j_GbH)3zZ-^yB?wQN26@!YQL
zKDdwCM~{2P{o{f0;NIN6ycP3bf#yXfC}dx1`%#Pw(q6YS=nW~EK=uj#3E@lX=VG6W
zTb!CTon4t-Q`%a(D|1)&0oyaNgQYj=H-ch@>j;DAQHLIZ1w=L*P@4qL=Nr(kJKE*2
z@_ZodkNBbFSJ9ipJC*0XcxRi_8IM^lCVPq$<}myr$QRl>0KhNR|4BuWv188dE#MbR
z{nQDe^X2I4(ceYsXoGg^mJvG~vX9s&>@?yHUAmI;EBOcqx$OQF93m40(0H~0D)lT>
zK_^rXuWGq5Fv}#-wi%pPG#7>S!D<0@NRx9ARWa*4cM*>=CH~uU^XMmHf<inNi(4&j
ztJTsXqk{$;t&e?(kD_XG{(!v7TgyNjB<debXCkWPVAzNw8iY)S3j$RN2LYQl2ce<*
z_u>I0gmu2hzAL@!crT4uCmbV`bCa&@hx@7h^nS~e)(Ovqe<Cmue4_2~*#4Y|sHp}=
ziN|k~ZYjhH@rSctihn6<t`B0W>PV|fl}{^Gs0&pJEde9N$xr<HLN$+?vSi__q7-)4
zY${&it~XF6g;I?hiDEIM5K(d5Rn5vS<62JRT6QP;2`BmqXEm!j@i`X|K}3hytF&ZA
zzhlK0xS%_&=y$B>7_`U^vi#+6mJk0yV|)wl^eHOu_j~gltRl3V8|)iLhuc|a7*!^R
zotD2K*9NU7B%07_U&~>M3?3rYtz?*ZYCff=CZfqZuUWc5jconwPoBSH-Eh?7vqq!A
zr><YJ@w(Z6%jLfGiLU;VLvo7r!P%ES_pz0^o^&R^?1r!IdLk_N;j%{_y{fw8+KJxk
z#?deO>^2!$zR%2^gWJLPfdwoe{-+?&84IoRdT)i-Yn81$+|M86DgJ)(V|U|Tg@h0Q
zp`nw2A#esKJj{y%Kv2*Z=JN{|exI!K1s!ws%K<PQGOq>^7$(2dyBTh#HitHcZ-KW^
zw}fs9bA@Ovx+eNX^W%YM%ufec3WmbQ6d%UK9;_S#5j;^xv_VbjE*@$?_t|PrJBWY*
za1fY4gG%duj%P?bi|~1##02;@pEsg~Nwyq51B9jU*6@L_Df}#z2Hv^z#>n30$OCls
zBkHy~$tc$@BH=y>!bprP6?}n7i@l7#w{}kIBlCG&BpLy9O9d^hU2hQXI@5<_L;8{Q
zBa#wW4;-h$VTp^#4ff)(;mH4(UqkCea)DnZbj3)PUF<JnhqxnT*qF=o6?@X+irlpB
zg+OvmVdi@{koY%S)8&<HQZlce{r<XmZ})o_TM<H&Xmbr;120EkAcMZZ3G@Y2@bBac
z1SB9KBcwvTZ6kFPbtm<Z`h@yT^`t7owg!AuFWI(rt*5RDQ|SHE(Kc^)z;RidfWJsg
zjkNM)|1;>2s9=nuIq)4gOf{%edco@>pTI{xfscFwUmMR0Bv>PmR)M^0;i>3#^=8(N
zhTXX2l@dOHN7J9HSF1*tZ480)z%c-5r(`F-TZy8B=tWKr(<bs3Y4R2|<1ONs=%eR_
zWMg=wOp;-msRWqdo4yde{k=Cz8xo#is=q|tIJ{An#LiFO@a0e54DV!TClWpC?es0X
z)hq%I?fTC5zq2;tap&*AV?^7~d(^NbBX)KezsZvzk3{Qpy_G`#4*B-L?ZJD}Bl*t<
z*`4x<__OI>2Ywy=Rh&^$Qa+umCaS3g>0*9!>Z7TV{CM8-B7pv2Cb%m2FUqe2=4aCI
z$MIkKeii>^>eci+aVDt8LTS#1gY#`L5@4e-dnDkA#z08TwujQS*qRs>i?N>ewAbsQ
z5F>R0zvM6ab%Y4a{uP9QUtX(#Jk;}t^3?wPRQ^n!&SxR{K#+V2NInp3v)hcJI))>R
zd>`9WIn-s|c_ez>4P;;x`ARd!x5BZ+ckBIFJ(6_ptpF+TWFW)^kBwY?8lh)rwUs0i
zjAwj7Igw6geAxXNM5~n2UV@20tkgo6_udOutlOze;kIZbw!qXDRu_P%8Uc{_KY?~H
zNyHk1B%uW1p-`;BzI|*s6yiMX4fgkw!yX)>JT~m1E_r%d>ZScJex7;a(dlg(uvE+P
zVnYnS7EJb+XP!fH;tn7=fxkcgPZPg>sbg$m<?7JQk1xM(U1@;&#Oxj85hN!)k=yBE
zTw67H_tR%=%LL&o<C`8|<-*p_F?WuhrXK?;_4Yh(56=U?lX2q#M-H^8XrWpI|EABM
zuN9mh8u8a53w(g%`L-xJ&*CP-hukj4(N01)PKF{a6l7FVQSo(7Yaje~8eHbJ(-O)1
z(|PAwVUxT?p%olAv{c%#xLoI{xD~fQ#<vMkhw6;Ws-pUP`Kr+C#7QZ={*~McezCAb
zUZSk<f0X+&_XPjf{wD+b+r9~&;l9p)Rr#v_nZS3sWBhU9xO_r+*8f~!s_hr@yTZHj
zd;Z*h9=4IF_)wXYT8B}FGe)^=nNg-vMj4A4rNco=T~~r-d)qw#i2yZXzDK>+e7|E~
z8{f;7g|b`?yvR&NU-h#O3VY=}3f=8oE>kWU4>Js?&0&U(xd-$t?^je=QHs3aMrJAC
z_mjbfJjXI-lZlK?G=>=Z6^q<}A>FxEfRYdw_6x^_p9^MT7azd<OVXLb0q!LCGmhqV
z@yZ>3Jj_`IJi1@Iv&`fBRzjql?5yD8gjfOm6zWVH@P*@28ys&l-Ud1fm&fg{aumBy
z6iL%Y$1c{fO895wH}Eu4P5()KOrE|piIg;r$9(K*dPU65$)o-^7YK26;1n$5kEo9Z
zaW?ufLG@Z|90E-zP|3$FIFaBi!chWF1{7RXPDMZpEkr>9fjb23@P6QA{1&w}c5!kT
z$(xbEg)z?mbHE}VuSlF3i2lKY!Bocci&uP{rL7FLvO5->eJ(S5(wmMrI_bv}Ni|lS
zWhiS;$i~|(iG;}!Ui$uTX>(UW;yJ8Wmmz~}H$MtI@H_MKUVL-!8hI~nk%4T}=TBm>
zki=r4h*S8QndNVj>_xGa+9Kiv7?N1tnESV5B-h;hJkm@KEi7<h*M;j+mN|<PLbT3H
zA%RO1bVx7G3%sUWBzwh8l6G;DIRI=k8eqf$OvVg5tz;C@h!m5Gk&GgWKJSN;3Tq^H
z7w4axnD9;cF8F94alkJv<5KUfE+|9aq;*@@fDh`v0pE~s#5dtPfDUBEOqgBS1~XwM
z6>FuPqg!Gb0l>IbY+l9~qF-51o)F=H2#3TGaY8&GUJ%XVq<3CAiIEyu>-!+iT8E>=
zCr|Q6j(UKZ<%oE&O{e>%`D`vFinIc%pHRxnW^1*)-xiVmX$N$eAAN7(hMo{f3ZeBc
zEhA}o5PW?0+whCvCEx?M5+suvqy~Mbyfp6{QqCwe4*_d3*->YB+^LHeQ?K0<@r-+D
zPXl%3mWX|;ow6(Pm%nB(ul|`jAy-a=O&JdmH~|3=olcPe+=8P-pqZ=Eb;&2u8gPrd
zjgQ|n%CoE`;dFQOuIjqtrhT*D&bI9va9Mdb-&^WfdfV2U4&zz<E}LCS|C&As7JwCC
z(D3`~pK^K!9#1~eMT4BQh1$`+V=V>RnLKm#!>Xy)y=Key?mLnrTlSgunLq8jPu^E~
z=<-i5*|+L}HJ|r=UVdUt!*tSo)OS?=QTa!!rna2fa(2swEdjskDM=M~S7eL%8{EpS
zS^#+IuIS1DP!>5IlHFz%EdtNGTyCBlPe5k^53Y5(srAG;>=tXd)Gba+ZGYlm;)MjA
zXuzkAZPLc0Fp3V<t@v2y{^-Hz3z+p9=a3Se5=F=A^2AEGQb(;T@#JGGvpCGQa=;DU
z*hlT!&cWS?5$g_g8Lq-Su?Q||&>gy{tP~0g98ks;N_n38CuB`{x*znRT>`@@SHY{Y
zS$qF?=^{d&VYIG-e!8efq$1p2+*jORq>C~h5oV07Emo>|dVC#Rho8-gbQo2Bd{lCi
z%D)jMTZh@6U`1NCE)hw?G>KRF{N;UVxF$W4o=Trdo6<IXWV)5Ok;a}wC$<ggJJc=3
zE&7%N=$)IlkbsCqEN`*x`@&MVl!RQCcBo!x_l|g9_R?PLej#}tUJ(yvGe$sqaXPN+
zi5jeR6zKt)8lWMdC7Pm}T>{<o)zhu)J6t(|pOOCP<}J^{yFe5Qhf#N-y^9SG_PCGD
zkjk_+c23ep-z6K`7#^>rjY{VbeyfjRkGe68Y32<)sHrARk72ib9ToU^bTHyHN3m0b
zst;;o7pHMIgj*7?Cs4~+YxctC<b@>7qBVcT-K#eCE{RuyA)gG*$wX&IsiWLMGYgYz
zlKDh?azkQW5C#{7gJ4yqUj<jdnhGv6*MeXm*B=B|YwJ|FSY8^0>r)$paKpw>ZvY)0
zSO8XctW@Eum6a}?TBKqwY3d8YD+^Zz!P?AKDp=xM6eI&uv{t0Nxtc$#oTjxC9|jH-
z*2(ZlG8ju2@_5FBisZ!eUR*frY{ttEbM6NFuAUf1qKX7|D+kwbu*Sgx2P1ftGIY`$
zqj#;$f`GE9!M=WMSW#9oeWb>)S7q(Q&rd)nc|CsV^ww+Z%|C)eTd{H@$=Qv_T`bo0
z0g!1ceB|FHUn!pY0{tUrLBnUzoU;xx^S97;W!>h}2R=RYea%KQX4<aZ*>mdai<f01
z(PD7qXP4Etf9%WeeeeEN7Dt8MTGp!2vvS+w^1$lrmy~AzR4Ddtd;aLROXVm39bTFF
z+~9+!bTh;I{DPTTJ~DpXovgYYDr=(6ymjR2(HlOyv9n8-6IbvzL^>j|YpFdu?tW_H
z6=Qer-+aaU_m(y#it)>LFE4w&CI(P*H_R@D`^@`*1!Ulbd0tja+C>8Pt_aT8ym%B_
z3%)h>m~SPT@;FlNGV)Q4Tvh=$TO*CRS#k=hoNr}S{c9`F>Q$X5=~aNqkSK$gCQ*iT
z#vAyV1Parq@u(c>mD8;$^0ZbWs)qXS!0|8pA)`PI>vyfYV$~+C^)6i-&?dBJY|n%a
zXpD+B#x+_(EoU^^j{}4YQ{nVt1wRt%>-~JY5>PWD>%~(~SS8e{u;`cV`(2Q@@cY`0
zv`&3lh0bd}pI;Q4S*ipQ;3q}vcqB4`r>uZO>H+nFN~<ct_l>zf>Q)lbm~7YnF^W57
zLeiQ!QJAM)DdEX0`Y&ooyQk}9ay<i+9AZufj*|S+>9Ii^b*nmvDm%62)KbROb-}RB
z9!do5ksu7)0$9snE7p!s$Y>pP@LsQ!VH#Y=aUH-6D+L<tg~?&bn7yLrpKgvP{EIZv
zdGl3xOMj6qn%4UIwD!Kf@s|#4+0+sB2OQT$<-GTUoY8$`ce~a%tG<8ZJLj&5#X7C*
z#>B?YP>(#WMVon}0o39CCt_SZCVif)iAg~&CrvpJjARSglaO;sR1cnb1?0jGBg|eX
z;28T9SvgvhuIPK5O9Z&jy3e-Hu_w8w{EFoj->*`?D)IJwQb<_h;+SxU<&91@*qgU+
z?lR?T=9*M<^dxKPYPs0E!m>tM<5(JAkzAc#Rn~hqC>s(3y?3y?ExV=Nj@{nfzR$D!
zrTva?$j>FiHnUx_JM7tr6mdkd86o2<^a@h%dVX`)K(DC@DdXtAclN*@{2)6Du#iud
zWx)jU_!+|aP^g;E_f}is{6fLVST|;YG1mB*?oG<Fg1$hiT&@TfQ7j>X$+AkaTq&0-
z3Fkg<0b#HT0;*myv`ZNX!*C(7J+?bW#rDNuOiASP)l%*cnM|rQfZq773apsTY(in#
zcqQSkR1%^$l`57*cc~;ILM`*6uartCmYzaV7HF}|R)ScwvOIsqdONc85%f(8dHg{T
zS#vlr1Iy=Byw{Y2xm-9L62t~va%{U7dh-aB*p8?QRPZH4siG@~l(WhO#e^F$|5Bc#
zx<Cm5?VBbm`4mDPM?eXdo}<2pkV7xke<XUEbe;9-i_>`eCT(>3V!auOu4^rVg-4M|
zWQxbShSh@%v2Uh)?Xm4L0?)VtWoLC)K|U{?tK+wRj=XwjwO**B7Kv<1_nb#HmXrEy
zeS2(D->y@qaB+$|#iD{kt#~ruu{s$@ISNL}P+`m5g-M}m!Bgw;RUh_!qxzdiQ0c+b
zCGbH<&8i0^GQsZ=w1G?A<+Ihy7<#cXT6N)CFQ%WU%%tu3Y8Q^%s|nSPN#3iIc08c?
zEGjzj%uiOd!%AAP&pfH(#ev!!_`FvqErb|OI*r0%(8PeXDxnwPK#NazRwc<^ML@Hf
z)jd_05heE;g%guu5BA7k&|RKt7w4&_i|%R$Ee_6G<;lgo)r{^yi>KO&7xc?M{Of4J
zryq7yKh&*%@b{N~dibFoWWF6iPL@r1N^;QvYrQTEI{=f71nGQ%jPeNQh1MvK4~6Jk
zPWo;#K($F@S(n%AGx9=F&zmAi#&{d|)7{vd1>nI<G-mNGT(!I{3A;Mt9qV_UTerMA
zJCH*i!~>sOoXgGrA|6O?p8C6$S6znqZqO%pN^Ljae1qQ;N+f8xZR{Jfjh!8IJnpvn
zeDzbOwm9Sz6_1<Up*!c^AMQq4w-%05n<yV*7wZV0P$~0xXj|8AGg2Q49HMDJNpJuT
z!3lT(o`DQ(!16ILZd$h)Q@EKrp1rhyV@jC#AjXQgJm)_=4Dj6G#<NG)Qs$ZWDBt7g
z*B+Q%YFdh|Dr61MXD|AmjtZ78-EFUo^d9P^q+S@}<Fud%kdd&yDxNh+V;k^kT~gSr
zsw$S8JszieLc9m(n|MDf@&fJ*+bkAQw`2a>MN*JOSP*OCR*{y(HR3_>WzmGxKdrmf
z-l5)+-tk^jZ*ic#y@#S;55(u&@vIFh7zY!;3?8md8Y%0Dr%n^dS}jcDxibi9CG#y#
z8?DIX;}jD-*1tKyB2hy`t&ivI0$^0O!HGwQRg2<iaHh#&r4`C4VJhn?wZheoOSR?%
z8VHQF3M@UX{*Po4ms6*{=Cm%&?AY;jj%{=KoqkI@KYZ1d?O|@?7y2uyU<|fddk};U
zxhWCSkIlUEnM%6z0qWq)*tUoq@J5#H+}^7V-nhvl6(jaF2QJf!m-m+PcMixmtu`-3
zU#bKEbr<nczd__;dz65zD9MM6>gkFSz0R?%i;D!PXqy}fIHPS!Bmko^J`!+5V@?Np
zt(>foxlt7|PFgYHQ<XM;gd6A1a`YUYaAANO;^?j16nBQBo3l9)*D;63l;U$yWmXU2
zpXRPpN224=vr)Q8hBDANU4bIQz|cn_F#rTzFn0N1s&tKbkMTM%>2^rOx$B@Jl;Loq
zF2zo82x`7dx9Ri0GzJU7W9qJ%=Zfo+vQ>y=i$!Wl$J(S~6;!R5NF+McyXoPZqKZ={
z_4gkmb)-KkLJ=p;Hv<7!Ax++6+G~Y&u*9m{Y26OnMd)E6#Xy=jGteYjtiU8%O?WIy
z0|s>`%eh&W<7gAhh#ZJmq4hcVWrQ*;aKCOfLx$%VhBKQ)(exZ#fpnOIH|iFix6^Px
zeGpSY_+PpVYv_CW0gfymu%ETlc1C9*tJt1}k0K=}UJN9=^-(;8?joM6;tdHqWooF)
zF><J8#`+vhe77gBnVM6T+3og@A{fI%GsgnQL=#6@5svdAo5%`Qs|nv0p5F+ErAk_-
z;nIVim?P$hR$vJgkUn|*>oeb{?)doEXXEhVqq9%K8^`HSz5fXHm6@$LQnGUHP5K0S
zdlHC)Uz5>0*KukCGLvSr2NzbWzX9#KllOz9o}~2TQ1U?XY|@l;;AY!aupR6M`@jLD
z&Pw807;Zgny?^>j{Jj0sAIv?z8pdPswm8L5kVYSbO#}m>KsZ1%uB1I-Ng|x1P)yY1
zxE@3p|Mk#qLp866YH_Gu4+9)pIVI2aKoQXDQt#1DmiG301BcBj8GK?kTRjc-t;u1l
z_0pW;uClY6U|ENoA`0Iv8S&b#rYzzdmX(j(zIo`&_k8KWf4=_v_uhJHNp-aA_He!!
zuV#7|SC*Hlr{08Xu3otR2eSvy&mRB$Z@%|mvu_^${B>jBfz>y^bXzfc+1lAJV~=NG
z?%&y6NUy8()$=0>uqTsr<A@^ew5b#o<ck55#YtH>jQ(&!No{`SsIKsgl@&RJ_XMHH
zR9UA@c2&h@%=`$)mr*&6O9auz^*2$ai?0+`@`I*L{5N<e$!J{Gk`~jhv_BJQPp3M%
zn5w^AT*fSBS6P+^)-jvdP28ZcN!;Y$R9x5bQDz%EY`NKgbKsWJ4$}^12fIVK%kl~F
z6aKpb|ChZt0gt1&7KN*-yJuf|M$+t>>6y_i(ny+-wOEp6Yh*2!Y}t}!c@ZFxEXkH^
z*^(vM#w@YIW)K7%LI_)o6T)I3LAJ4x4FQt?2?1^(Ap~-BgUK~pz{EEf2m~~Gr>bYP
z7|6@J-}nFDd*8?Oba!=ibuFh(ojRxL)Tv8d7fRcsSMt}X##~oNuZ~?)aHH~8?RV0?
zW4qOHi}R-NccVAO?o-{bzF&L4<38sB*ZrCIMh`0ws~*uzI3AAuBKE23Q|;%OpGr%6
zqdl?Sf@{=#sk7fb;MtnT_b7W*y=rcmy3tb~UKZusoNJ>iV_dVcS#^#U8YR+jTCK|x
z&2eRW3Y2A9b;=wNGA}51#?&reYmy=BG^><atW}kT%!IB_t%Qzq@@e{;-pRoUoUF^G
zQmZvCz&*EHg%sF{(j4i|v~V=r88+)6mXJH>43!m>I?E=e1`j*68j#`!;^{G!QqpO)
zJ|~2BI$SQdTBD)sWiy;E@Nh*lRVp7{eH)7w0N+91xMBtHSdeB8g~MfKW<<0ajY_3d
zFW9HJy8!C!P`tQ+GF#>B77ymdied$$1$zs)rh*F!Itm8a!^wg(1*(E~RBx+Ww9X?A
z?QtR@2mVJ~OO3L=sN;0^mM@qfn+|*FZWfeTK4lkA*~G~YKV*{$lW(P#g{M~RQXNgk
z7z;_pSazr`oi#u4uj*(TDyWvGQml|SxsZRTolO>Ewt_649tL_`>82Mc1{V)yc;(r|
zHVo2fJYDT#4WW#vwCWsFuoMgC494owicGP3sr9@V7(ID@f=*E+XDpKYS)_$RvQfn^
zY;r+;l$RDScBe-YSA`SLC0@u%Y{}E5*Dk;x+lotbvG$Fyl;O~)+3jiBM9eBJ%ELS+
zxtW&WLZLAbEb?FR*`r+7=ilcye8U=q?kMK-e`8Wf_6(gnFPNq`s}$gsUATMFL*Bb2
zW(}(h0ZIv$PQ4)*h0Q1n%bFXD)o!}1C(1=VHydwt-(|eZeAEa$zsij*R(vUUamIy~
zZ*gOm?{hah9^@Y7)H=?<lgxUqjT53O(Uj#x6IeJxoXK@LN2S|@u#3YJ<n<$_$he51
z`>i^1gZ@rE(NA#Ec$BWcK^WtC;)4&Fu*XzsA|^*Xh=b}1$%c(KkB!*a<g%?H(A|}^
zK{Lc?_s4V<;fLFReot=uu>HfgDo>|Y&QN^`s*srBROpleM^GEI1Qbqn9@1sNMP(QA
zu*Ry-J4+#vY5qIo21#;>qKlApR~F|In3W?Jm#&{sel%-+%gpkYq`C!F!XX*y=A^|V
z-Y?PdHglG&b_4tx|B}bE=&c{@`NO3<PTz9HuXcGhB+fjVc<9*JQC#`c@7$1McBVVD
z!sbNbua91nc=`2-#NYOAyD$C7eg8QA`E$7S(RxdoGbU?baQ(nNXW&;@jYZ8W-p1d_
z->JXTaDboSm3LaP-nw01P|}Rn8JjaWCvP>R8PDfijIZ-A8kI@v6vmv@!WoG{&@B`2
z#R6^?Is_ubbcz}y9x>tzi~~kuj1dh$7sN?+k*y3T>699MEQ(bbZfc4yD?U#U9@e<E
zyuoP9;`nrq<2fzijaX-}>S-!`vw($|UZ)T*Fk)j26OHjvvIrRvPZq^<Ih=nd6fM75
zk7N3{eo)Wp9Z_qgwaLm^b@|$2L@=>itUr*&?G+zxTmIoGiU5EJAGV(o;h=jI4OOs9
zDv!yrWnfnJT>6v^@Zx<Wew4g1AsG!tfNx<EvSI4QxEkbPE(RC29f}?t#yEY-vXmJo
zrv7-;QpShVsq@vN>1F(&nL76#HJ9<W4C;L6Xa+cq%z4l_SG=Sa0-TS4WRj6VbOJM>
zr&ACk@B+YpYR+DN$^mQSWi-S;-<yHGln0p4ou~c$Rnn1oxw9h8$%hpjn!F9K=v!tL
zwb-6`JB!P)`{yl91U`S+pDS$yzDYz#7>AbaLLSmOYxK&DJ#OO8L@u`rWqPpNMVRh@
zmCj7Usi6z-RmA1yj4GEU6L|*lC?*)IjD)UUqAD3Ly!b*i%7%hYpZ?%|9F>3KrF))w
zN`#Yg22K?qf?m|P)t+XrBEy&_I!q4egKU`!I>~b=P|W6fV(W_7J(ADvhq7gFDJXk8
z+_JZoc^}GPxA^zOv?9Gx3z3%@mm2HD26vOU&A3)voxaY!$+%JMb?*>I`8|d);~sI3
z`5O1tp4*MLi?^C?cONqz6MyPB=6=rjEAf|^zjFV(@m29X<2&Lz?oW-Mh@WPD>dsXg
zmpO?Cm_z^)g8tW~HfWq`i_7Y?sEE?30ztr;aiQBNQq@M6&m^Xs22Gewh#6>yY9j7*
zLfoFryAhHBH-V4Dbt=)wWmqgKm0IPRfSyrpgm1{*hPY{h#11#Pv3r8N4}^zWlsjYK
z4EIX3s|2Cb?wD*pZKG=%Qo~AgQ0YU;H&oE!BWBE^osAy}mwxG_y?osxUiwspvI72q
z_}kiNMmL6_e|yAj%*<39J$OQSI<D*YctCVeTGLZTD=afcD^j-IO!6L1a|SDLA(lrn
z*z~5Ba0e#;`#j%*^@-K1?S+f*fB5mMW$mjb-(6W2-ul-2_?cIlLY}BH5HQ+e-{H^u
z?3Sxn3V{Hh@6Ejc>q*w+A8GFd!np7d@Trwt?+gY%Y~qzRCmnZHl+O<bn8B=|$&2#&
zpuLm?iCv{ovBgIWMcF9q=hG~!xXXm~c6G2EUx;>k1+#|^78#5n<)oL1Rq;r?imReX
zc7w-Xv;$pey2v*exhU^8->v?8@IB%I?*ZQd|2=sJqL2C?4Llk=UV60hm*UgTr=?$(
zov8Yq`FGN%+A~!yb5xYfJ}D~_&W}bHiZOFcTHq}S#Ue|P-i)fGs#w*FRs1t~cqH$V
z=#`OcqI`9vP1ok-)PB3)vZ%6ZnWH+SFsJ9^to$DD-QK(NQzN!M-cc3LHU;yE33>B*
zXMlpj=}<US6co;2X^=9OjHyiCC=l9{BzsxD6vcU7DJlZu`ph5^=9w!MqSC2wNDxaX
zFAQvDWx2CVz`Roc;nism`e>}t`OeZjpD6lpUOL8kKnBdrmWvckrzXR^Cd9J~_LY^E
z0*gZ&cDq6$sCp}LWdzYpawHtX=iv@Kh{y2>d=j6*8sG{35jWOItE6s;ljb4cejo8o
zke?roSKXXq6+djBY~OaOeFpVYyPkc?=;^=25YE1W>}rIL0JT$HX@Cs1WDh^Qt$N+j
zD9-jp7jf-vOgFR7+Z`E*c2x095qSvcIprIT8$x}hB*z9UqhHjQ5jJY7EA!j5W%+RW
z>n&x$n1%YEfX>4gwoo&aCl6W5(&-SXmYI|x@}3W6c`9?6PcoO4QvG8i+guH9W_e^)
zl5Y|Dwg_%#cQ7*}m#h@jRDN8SkGv+{5uRVp1q1RpC7_2*$#V`TYuJD_UmT~zsa8B+
zR#OOZSTU=aLp!HxH^tKnj^t3OHAf01SA+e#wx2V3yxf)HR4Zd|B~Im;OBxfN!oZ@z
zdK^!DwB?pAGTgi%_Tqo#r0I<L_4tjltdetD$X^pH9=-r*0M@DlX;!Og2|h1zQ+X&u
z%HaY5L3FG;7vF^U+}TCfA?3RQOA^oGf|77XhL~Z(;AOO~=%X})T8+IMXoeP@lt&l&
zsgsA(oQnk7(j(xotFXZ3s28KSzC*uX|110~c@@7(PU^J|gtZs}1Huu3=O^%Y;tq}g
zFGF}vFT|G=3xCE6xGDaOsiH8x_2_<(=IlD*IC%$g<n6c)@gh&RPTS85{A1)Tq)QGr
z(BZ>VY|P<9s+JlNPe&@JrJU5}a3jKq;tJsk1ut*N$1Lws-JGKu4dV4k!K`dT!jxM`
z+Sdf`zz?hfa0;P+Bfn2n4C3!5uH6=EEzA@ega3G(f7+Sfp+y|JWa=GmOz1^+6hwvi
zM~rVg4ppr#^c3cV1`03ojcP}AbnV1tfzjYt;Q`y-j(Y=#bq_lp2|gNnTJyB__j(Hm
zx>%tn4t2<)w>kp)fMFTF4qvXn(r^G77NByx3@yVA;S2D&q4Nqip-s4tYz%G+^%h=?
zFA43)y`+%ppNuL;RhOAAGvAPYgXI?fX4Ormo6Wad?g{=l^y9(_{;29*?O$~78r}`P
zJ1<+QSBJ_`87`eC)Tofo5#rfJw6f73g^)*YY5L46H8vtOj<YicZV_*Yi>NqWOsJ*t
z{lzDX`C|WL@PfmOP!2Z6H8E@4x)*p$d(m<H0e*LSKnNs<_H7@ZKJ}qICX}Q!OqQ4z
ziMo9z3$Mxucm@A@<WXj>$GPb_>ruWrwjTR<X+3t+0icK_Z#{~d;4*7ZI;Ju})lQ*K
zosT$lD8#2JqzUDl5BDpCw7d!B8;APSl4C*1b{L#d4N_XB75l+2P$C<+WUVqSxjThC
ziGR%x+Mhr0qhIzvFkaU9hl5Y{ui1qQE{yNkuwk^gpk!6^x3=_O7F<FexMKgBE1ozs
z)VOc+)hjk^yWzQAox|rGe5L==roNp!nu>a(iMQ+S?)c{I7p<)?+XOA@3`iUbz#a=a
z#4sm4ZtJk^x1F>BF2-$S2f7LoLsc5?!&OiR`;iX-P2DPR`=LpGf{eHiS-=P3zr_vM
zXe4Ta1+_{?ICLEU9fCK+%?5)pZYqu$cN_N__ZxYm-Flp4;Zw=Fq1wWyPl@t?E@SYg
zcQ2w89AN8w7z;|qvK;DH>!!8D(qxl~lzc5B(=)_p@KSGD#d!(RQEJhEgcw-N|KbOq
z?HMYiiyBF0!A0bcH|0of50pL!A^u^YCxv(~D}80Wc%y5l>-N|I+k>%3V<(GMYwUxH
zLFI1MZuO{QRC$By2DLiN<IME>0v>0?>sPTcbCuU%@Ti@#9cVB0QF;mSD4a@{=p@(=
z{BmX?x;v6jjp&iQ3G&;xH#au|66M{Q&Uaj{OqKdUl}hnorE<5DP(#Q~N)F<BE8fiF
z+L8ZYZp4!pg-`n(4@$s+zwYFmtD1`kp#gBkNMy>|BGbzjnLI7}0$EI1JBxW{u@U#I
zeMKja;XO!RxDb)oCs0A_G{{+#A5#sV3XyT5?*j)4w*+HFfgDv#R!}ZO7Ox^nF)Na+
z9gwPx`S}rrBBEAD9FEKg2HEHIk$#LbBZwJyjpQ(u{0PZRXU~~#R*{)0mHfyI>p9z`
zgqO{enB>I{UZxPphD_%dCRO)ml(VUb4lev4&KU_6DFOk5!Q8Ss@roEOeQUTkwx}w+
z{j>LCv4~`KWVOcl3}Yyxa9+4aAd~O-^G6clE|))?s5&QPm7<F-O*|N|it#RP+c(|e
zK;rkCn=_1bth$=p$gKjI%YyRIo$^ROMh4zy4LChvpUR{S$9+ewrnvSf$XkeuTCENv
z+e?V5$K}M0&hq_0Fn(?{cnqT;22ejWU;a=!PPgYrC-BH&FP(9tyNfJ8JxOb2vOT%6
zNab=m74_liSt5GMqK?{%eA=+q1pR=m@~L_AOob-4L?mNc<)?6#UPa)`y>Z>TMvYpp
z&oyT+TsptH|4MRhPaFhVZLTGI;qubOo30WzXXke>@aql6g}JfXk=5Nl4hGB5TjVkr
z#08Op`k~c*Kc1ROK?rlG4%*dS2w*`65edR1hs#F5zR*7WNv;R~4dCcNoeYYZYCH6!
zf~ZbMNA>Y^&IN!I%8gc!b(HF?;+(^x-RXJ^=O8co4PJ;CjHpiL%(g2@pwK};=V3ic
zXTV76W6qzekU2kPT=;{H0f$y+(3%~l@FGu6dG+SD1zb;bVR5k7V>Bw&6?yYq!ELQO
zI;s7un#58baSx$P6d}SadD{_W%`KQ=p|=bLR=ShA#0JVRG7G`Ul@iQOupzY&6da#0
z)nS8hTvi>9i^@!e(QWnzY>MnQvsP)4R~gG&bj~ObpJ3~o<t4@^oH<kp$eBZDL!C^^
z-(hsP*N7a>W82?Jwor2(iRX>x{V2RYkB>QG-pZWPNRt?M#Jx>9^^tYPW=EU5*?UgT
z1(5-9y<@$1Am<Wsn`5_on|F8QO2@Y%cNlMW+~L02drQu~$bFW391pmD964rr9CGl7
z$orAcA~{mta9}umL)!P!zL$O?Pq``$`&5Q(w=$H}Aa>e}ZV%^oWMf(^e<0JQR4NQk
zC-Qg<bW%2oJa{iA9UxIZgt_F7qVEL@#Ej+)@<hh3*}e!&V=|*UH)X?@u7&_=K$X9o
zjI>j`qw)-G1ziy|ImC81NUkTbWrfqMS=OM0!f9{`So{(WrBhSBDIF!cuz%Z7X@o95
zjI=o)&Q!{($Pf1`4K_a;%CRZU*%K<uto3<kDJUliQPQ3-V*B9D=aM!^<?fr?Y%5%v
zn3q<XnQlAx>V_*{!s$OR>j;(?UmohN9Nd4`@PhNWhd$e|Zk{U;5Vd73c&xwaZ_mAp
z1Cr#*nvCL~EL&6Y_>;#@6hiBPK3DiY^jNj{_zWICvV=|AqQJz|$IPHzpop3XGgD^~
zL%$-{4-}<QbBAec6A$cT80ljO?4#JqIt(8R=yO!j4Q?{w%!M-wXFk%&mTy2{|1+wf
zTJ8%`R#yH(lJC-hU>arPM=!{G-_VPUu_xqRW&a~`f~vd6w+$}YzvRUwCztSPOZK_q
zCC%U@W{*?r_4zzbm)BS1aprq{wI1gpW^+{I^{089POl%j+dQwo*yCL2^#c_ASy|3S
z3m0m&8j_!v=W;n!<}@FP`|#^NEcs%-K@d1!^qur6K<Jd>4sl7xk`qffX$f9Z8}Jo3
z7j+boqJ4FAY8hxNolve2>3WJehHT}noLKLd62q7Z1f4cGQmNK)iz?V&*qOOe&M7Zw
z&!Qb(T;C75(<~wylBaT}hAXIQzI7h_+33nyQ_$0M&@;=9ykGD+`xAUO*}>+gW2A=l
zZSutR<YTc_LHpzwdsT4Oly)rQv60{7D|+RrY^zw+{rPui=C$$n6J0Y;+~!%qfC^IF
z>jm5kqaw1L(e6W8Y_WTQA<Z5iHeVTh+W&MO*N}B@9<h0>`5Ur0HC6|LfhA}i9v}l*
z7vqb`uxD7>;kz&}hWALf<UN2N2s{#eEN?0+Lm^#(ugkh3bX(Tl_($ZPtcUWR$a^*R
z*Sx7by%~5+2Qh~oF-JjpetB#|R$o+;qarRB&Y-J5eJBuiB9+H!@cJzjll*a#8_3G?
z5u8p4&U%nYM46L)H)GMPG`qlNH7h%m9Nlt)D3S9)SJ4FicHB5GoSEq&MuP!*C6$>C
zPOg&&Cu^IEk@q1lY4Yy(67LbQ1jkDTOI|GDN{UpB1yeCNs92Ly`79Z%MP)G04Au-Y
z_7!&?!*(>Yq%p~a4YBDmx>hbKua%1?*UBX^@$_jCdV=<$XoOnlw>!ks(|d}U%N)=p
z%KN|X5rs>iDu~(WYP!4vx8D=U^G6GDfg3LQzT86O&x%R&sMWBf?(>XQBsNqYm^yh#
zN6jprIh0-&rXv~YWkj@7=b0m7SxltX!jkKJ=+=M{=b@}zenR<fT-~3WYjj~108#n*
zp?=rA3FQZHbFvoVB4M3TWG%!fYh=*%cJe$6Q_b*tv25-CpDevo(!mQnZ)Ohwp*L}J
zqPS4fyG2*9v6wBwV~aKM2d}<x!(9(xTgTYI=L^$Z>YqJ*=jG*H<RXG`V#nO2c$EjX
zUpf&?Tzu6!9k~hLciHYc(}2oqr%nn70n_v4RYS*6Z0f|}oM=&ujbLZ7d%V@+Dheyg
z6^)8rMn2#Vgy#9@g=+n^p}RxM>`+;VG{;7?7aMO2JrVjOsHiZ=nlv7d)9&@<FijdD
zZ8oppZnFV~l0aCm&dHvb`mfZUWN)SRBzr5lCmDG*E~?e4xUNhUuPl~SF%?m<jR?}|
zLJ3CBRcv#6>U&gHwP87}sVo*_crdm<HXb_}<6|C)p{peCRlv|y@|n%M)9^qVPLnrs
zGO!(<*dF9*_UMN{OrdOh`;6)^;H<o|U}kYHm8~n1yFLK9T()x8!TBmc$DlW?G5NfH
zFHsl+p+J^F%0r?lsLRg7T8&o><e{(@E)ixFoPC|cw%S6}u0GZ7Il?;;$M(Sn(ZWXb
z0k*nVFHhMOCh6*oMi1+cLu?o9*@`~Q6kQUtxR>zB!sbZE%G1yP>8+SlyS$JrEo#lO
zXExr@d*yGI111TfK%m;QZSoJ#zwv|HE^GUUm@i!s2oz@xO&)A|erV~)kylAzx0Fkz
zgZimAgbRVI)gdSP4Wo?(-!tE*JfJxs@;mV^<sN*slCM_j!-&fWE7Z0M4;SSKUCtqK
zF)q#tTtg;XPz4p68P6n{rV3FlsfkhTQ4@88D>*$%XGfQd0Cwt_(QTQBom7X#5ljmj
zbf!Gy#I`(~t^}7w0GFuI=V3d6i&>SChpc=?-mLKpN(OLyyYnE@L+|x)KjIV_6Uz4v
z^()lV3M^PcCJ}k*b$*EzU}<6sEM}7!3X;=Ug)dKBlz1=kPU7-EKJoXXTd%o(%i$+J
zy=JShIWdrUIq_Vg7hjJnaP{*C8}{6ncr5Yo;j3{DuEOU%a5c0xFGvd>Xl;4;LdMgC
zK^$_&=Lfn=)Vx|V9_4O{9FIH`d5!yR<X!$<&1d{)8ug$ssMrm1`KU0exB=vHl~SY5
zAxf`KH-Uq3y~?S~^f;|vp8^DN>XR)v6$WO#-0g7&z5YmUSfkSM0<=6oGyrQJ@&{2^
zq*kmzIuFosZi`hFii96T)P_|oJ5KkP%igO{c$BzFiJwqnC7u4sM+VlGlB=TSy{dff
zOxB1pnP(;={h9mnJG;)J`;6hB%j70c$xAjrXrC6iXN0{-QsSOW-R0f8pz%55y6o(r
zAOuw^YY;>2{f&y<)}SnQvw`6w{Xvp$wK3XjowL+=?j*N~?drwMIQqYu^GKub@m+sk
z-J}l$aHzKC@4#i`0+(?-$z?#3=l)CYchvT50^$0-Wdn)grlo<znpsRmQjIS0$^~s<
zDi4~W<@|)|A(HvD_8-<56&{kD4YFXjsHeuU3?5=p8i<n3QZhxQ<eZPrEPAm;r7b&P
z!K|;g$<vI5#qu;`Zj{~QmrMSl|2BW-IpgJyTaVcub&PvIRSE~}4>}$bjw+5Rh5Lnj
z6$g~}XWVNMZddL#?ls?L+3OYhGP<oJ{4UL?S2)MA*4pgtQS>Q=bCqqXb2aB1+A@T=
zw;8o^YlT$`LGl*yr5Sao!5{<_*~+jgoDsGN&}h6dZwEEJlpG9pA%j=aSR9rd3ujU4
zX%U?UYF0|+G0+*F%J$^s&h*?)IufuG88bwu(V&9B9;@5wnV8xWH(8VlNu^W*uL0sn
zhM-W;PNLXirK4gX#u^NWC>83@tl0W?%o4ZkwVbi=mUm(qaS*P?GtOiPQbtF{V8&<$
zpD{t+J1TjTvojyIx7$B#Kh+KhlVpUaZL9sWRmAd@jc~Wm{20H`F0Uqzt2H)rnK5o=
zyLTNG%T%f~s!RUr(X=v6Sl-NQ)&xi!a2d`=EK1RhIfI_zGXP0R36ngpAuHvi)(nSc
zO<$x`Z$ibwPwE53*@;jf!G}b9!y=M%erY~#!|`Z&t)LSc1A1>k&u8D@zkN=+$1el|
z>in#En?8S&GmYeB7HgqrPV&CH081^%i)$EtZ__%pnOBM56@MoRJH#F7d&FDPZq0bs
z`E2IPqRM76r)Ro3Wd`2kxY|v^Duu_1ygsGJsrUM=Ub`o3FzAUrY_TAftD?ya%|J9u
z=9oEd7R(b<e>%!+@;CUC_8H=SEcx-Ef4~2vpYwaa%zTD&j;V7-auoY~Um!V2y9^Pz
z|6mHu;%QS^N@jLB+<<0*^q|}5T7w-KaLF`z)?jCvea$Qz4DH)Mc;4nbsP|5&2=u}p
z#_j2KOm@~2WSvk>9_mMS5TW6Q<;CCfa33A-qdiLDTpmy2%^9Ln;SE8rLc1Dj<fd><
zmW3JL2;&%D_~e66Cbs|k?lte=d5M2JbIx#JzIT}Grv^C25|95j@#f<%uXo`(Y{hn5
zlL<9;CFduPL659Q4tZ?*kqP@R?SI#CbeAq_U7y|aVnvv)jK~4mePZgD@l0^oZE$gv
z!sYKetkhX`MB}>Bu(3psCUEOvCFd}}{ZKlGCb(i?%{06L9C3@oVKr&C@ISY1K_+av
z(&@U%OD*C+Up@ITTjeBQP~~I={6Q3(o~*}1&LhYWSF(YtLdOe?m*GOwlLSi6%guTq
z@e&Iu&5x9&l_l2Cw-o2)mODx~KhD}^w^x>z7p(3|{5uX`lp8N!P!PI4@fuLssW+$o
z0wk^xh49}Q_AVPUWAhCdlXz3{4FsDr2@a9Gw9>Q-({3TJlPRK1^ZCpomB4*oDuMer
zx+jP~o$d+ZH=9kE5TDtXZZ`XT6ZnU5W9UJwQL8a=I#gyg$M*8jnOB)ik{A=?A}7+3
zFS@i<Os$or4u<C9KDJe>2xy*-rEI)E`(!rBPD^L%jb3lehfnyhPad5R+31A4Fqe*7
z*u$MOoar`Z=sShs-~sNpn4+^x!%m;xBWqP4=vd3x_8>~StO2zTRj-SO)n>an8&{$-
za}!!>z5tzL9zdJS7nyIz2k@i#i1|7E4{ZJ`!F0^K4Q+$!V=@z&x{t25p)<jUE&56`
zC2Q6)9Cy(f-ggcqZ%%eQYA?eo8=Ly2YPe>L8N{m$CSs+@Yi9`E+K}BoIRdg*e8#v`
ziX<XtP6~RyG~!evVpfNAY89i5YGQM`SX*;W>%Ggi7ATeEym;Ewjm!=E&o*_!2GN~(
zkXuMM8o{qp%RyP6U*-%p#S&q<|Hy)c3o;i7jh`zyL&|>8XV>sGpZ|1vzmbP(bJNuF
zJ~+awfN$001BP!C7aJZo5TFIS(ROmNVMlCN@kJ$1XpZYuTM#z$wfUy*k`l6-^pH_<
zO?)r8HGWwCu;F;&@#^2{e?L!e)&l(}3L?zA7VVk04?T$Y8(x~H(jvNuMbLTFZha04
z;Ha8z<$WD`rsy^Fw<4ojYuCnbF)55MjyKodgYP1D$B&Yun(@Uipg*D)@yp~D?mhG#
zK7&8foYDPFZ?hCyii+mNidyll=qCNm^S)b@Quy^ojXrmUyS63+WyFXfhPaT;Vt3jU
zHdS`e8CnoZ>SnMDom<?-`tImtg)?5J&?}t^Hx>4LQMQ{-Mb$!Qg~0Pp!AQAOzlZIp
zv!JNlxd0>NGw9Qyd#FN)Hi6byQF<&^gs{G-N~n#Ysv^Ezj|p9(uT&Za4Nn+|A*ke)
zN{hw*psixTf^ayru)G`?!v{k)t5u;8LPStie1|v0Vo`onz=Hx7CP-;q7uPrI$*3NW
z>w$M9pT={eM%J+ySs!9#9gETDakHl9W}a@=vAFlu)INqQfN}3+gBf!y|4^$BlXQ^*
zGeZZBPfV?p6K9Ueq_#&{dlX<rr(%<9=4S1dp5!l*V;gfG<aKb{&^Fp|)zQMds_5dp
zYNo-#mTZ?$y$y|&E-zRU%i^Mej%vJf$WVr;nuZ~@l?0l#l|)i0n9bxm<A#_4<js&m
zl~cYDNU^MA0o9zL<T<uKz@dJdDrwH7P~L=nj*f+F@f`neNAXN0^O3x0jQRm@qfnA=
z{NcqvSvz@gd0|>{B9{&1<xf67YanlNel*u(OW%&O7ddn0dGOzI>w6n5N649k@!~c`
zAP}<If<^e(iDh&6Zl6sa%!_v?I@9{Gcy8Ej^;5f-m38Sr$I$hO2cWAyh_t}%?3OKn
zc>_<HHkLeNe9A|3dS_aOsMZ~|=@fCKOrPLZ#69k~P0Ph)A+^LQmK(hu@2Hpa{?cjB
zqMaX5W;#_PvXzsQ)MzW+hB##q08<f0t=H+?Hmw3Fla_B~BWJVbr?{`Ms(~HUdK{eR
zpKV@)I~Zq{<?`eI_{SFwZD7=zSV}Gtu19HT87rs%X4AbUa+U5H6VcqFHlbT^8ni==
z`aXlNS%DR!>8<C>iXLpGXHxEFbDxKC8icpWJCbEU)skWn%?A#Y01N6S<dX08?7aie
z`}pF0E4+@SmnH@RjT^p=$6m%Icxr1-&HIU)pMK?`v3qZ$l2AV6Y7NWPQkJW%Y(7U-
zFL00@6J#q5h@DykS&}zh;S{48>wfgbY|%`q({L(NX&?<)fVV<QfT9_|m{0O=>AB&K
z#IOH;@tw=P_GOm{-8suP+?d$;yTq>&cx#~cJ-qqp-;Iym!}4ST*<1&Cn$LYYYu+p3
zU^KzbuJQnqNwyLu4<_mKbWOd5UW0V^ZZ=6q=NKaLR)Hm<d=E};63Etsd70H6Z$8`K
zB;P{k&GJ*5pya1GhJ1M!Z{|qE87q)4Vv~mtYOIbxm?cDwaM0~gf~Xi;tht2Q;ejR=
zwCi-T@gDBaN7Xt#GZ?`A`JjfH(u$mpB)1ZrjGQ=eV#cCya;ubQ#HXI2%Mzf@Q*^=^
zKV~fRlo7K+#PI))`n#IF+P%8ljklR@H{a&Dv+S@&Q)Vx7Tp(Uxy1>&f4wwc!w-fby
z?$aJJs{W?o8SWY5yX0NtY13cLs!CI(t<qB}RhHEmhcw%bswl}3rGONSmX+dCQJEpG
z#w}v2#QVjyc&+g*@gq@aFx7j0rv91cKQ)3?Z4o`09#1V<Y*c7X#x%V{muYkxJc?D^
zYJQc_CbpVd(-d}NW~SS-ilp=nqa`+GB>;<@CR7YCx<rR{7pnos6!wr#2T3RQIAj}B
zd-Lf)Bz?|L?V+BZ+Cx1*zpQlD&M$064gmT>dvf;|wqO!Kwpuh|Vlt<tiFS{}ZO_kk
zheAFLQM)yCzrv8eBowVGc9+zkDAJ~hVwU7dmoSk$Mp2Amk`CM|HAm=4!+eMsHKJ(K
z%ts(=;P>N=Hr?}DtwsR?pxtiMXk)rj9XX@JFX~R}$e`{7-QCD)z0-zm4iE5t-mH9-
z6^){NF@Kzyyc3%9@o4^DXd4}+WfS<q!(O_54An*-qFm%@@$?FDh%TR_JAOdtHfv;_
zicof1WJ=Wlam0!W)`J;Rd(lw`f&jLpU1hl=lT~-=yQh>&)}IY+qnjTMB^R=w)B<mj
zZhCLlR(is~wZfSh2gC~-nd%{MiduRzQO$IEQ_DBqtYy$Cl$DpeXt5}9A%L4sqn0<Z
z(<lNC3l|DAwLyDmdU<nXrb{!)D^ioPHC@)sI<=HOFit7qoW1`|)4NM`DsK>9-?F9Z
zz4zApVp;Y@iRz#;oOs)wzdVs&=g-g@4U!`x$Am@U`p>t$Tw~Vh(ld!9k^BX(C4PUg
zH)_yiW#No8Ya!m4c(JY2hO@FvTB~;@xA@K_P7|~Cw0`Oxj>_g<EYC_+|A@!tHg}(U
zx3F8WJM%jJTbasYQtVyLt(Mk$H@kKSyIgz7m}AU!7k8hU%G5^W$3_t_Gs9w4rRxdD
z(Z!i2$(t^5yySH_U7XU!3*dX_VM+3)9mk&{8<!Rbl7jz?$e+Dl#G~VQ5pv=sM@HF%
z(ggk}t^v6{?(gsuzhwe{dQ>F)z1T}5iL0f!xL*Xm-*+5;H>sp{s+}TQJ4GqFRP*#H
zlti!7bi4P{*i^<03naHWWL5@JTi{V^cSF);_%d>tq)4h5w#!?+XgBi%=5F_(FqkP&
z^-<?RPMT18kMwh#S8tn8ArRR0UIJc+`n~+jHs7?~m0l&!w9^!`I^Luq89K6pxm_y~
zy=_>1`;}|2SUJ4wqJezBBNSb>eEY$D*KT<X^FrhOM??Frp4fbJG&FzJJXb{Y79HGu
z@$bs>l*9-e$I7Ww+<ihXvVvSHuTd(zIP{wEd*5pzzL(!6T&lWAy;FCgeplK~=~~t0
zX&SZahHSDxC4_9=kWJv+0UjxZ<G2giaQxv=GaHnx297W=5Fmj7a#J-zgMcUSbq`yu
zNN=Nc<iN&9<lz?1Jb`=SW|SSz9?j<B*&W$b_T;niaU2J1GCmU5JfR^PdzdaQeP>#e
z@D!_`Nx6QghDMayMoQ}ESW~(v)w|+3&McKl7Zd}opg-u*d)K2(BVACc0+*z9ug6Xk
zTzu-l`s8-m$<cVGP6#!n3`{8hexx7Re1s>IuRh$5^aeLuSYi<7)RdL>?ek|eTxg{M
zC+WvYJC!M|pZ?2EzLfp_-8VeH;o@iR-Ff4mp83J!q|m&0*YdWj+Nv(d|As3-w&Sda
zdj8{)L)RV{d*HJ_Cw6^v6FGL-iq1DK+`sR)JJ;k=o`BAE+%IfKMffgOXRR8(E}z&#
zjxZ5zqMb-3@sf^`3sr-*LHmU{du@B|<F;|THZQtEyGP5}O7b1eC4(i`@jvEImhd|6
zD(#69u3kmuqyP4qnLJd)R+=4VE6wm>gt%q#>Vn&H>6W94a4u&E`_woBf(hjol7fkX
z2_`<1soA{OOpN9xGoh8d+dO6F%{=8A%pi83VjP8ef_xI!YATw8*ckNCT`i{0$oxc5
zWUNX<aranqSfPDr`Q*ouXhb%aPX(M)NY=}VR!r~alpH-Pk|Ih`6$pp2LpdQ%p$ldO
zj9$|MEO|teGNQ>tdOuu5$*=&aLyA1C4H)v06`!0k%aJRe*<YlKn6^3Nnu3B{LVURv
zt3xK(R;w?!h|5(l{ghnJXJ8oNo4t6At;U|UehqkMi7x1n7qBq`Jv|DbP{^y<DD6%)
z@A>?@Ada-|dOR_?XWPyHJ-Y0=Do<4l(c4#KrVpRICb9GRTi0wj^xfx{?iwgfOLKC<
z=0xlMmD^wV@n3(IIPu+J0AIbK(i;pG1-2wQ7nOhh)4w17(a-zV+OjkJREH&J>J82W
z^xBWj41X5Xn(+l`7o?MJ>!9^Y-2=uG0l{p;u|PaP94dL*G?Pu3T5K-SVkely(&Oob
z8I0pJN9<v}I@3k>mZ13HO0kR75%<#ibotckm@2NiL3O9<A(ili>UGtWic^uK`GLR0
z)7h*kQ{qxN0<Vi$Jed`kAO(lLCx1xUfK%<_$I~NB$!Sh%8m&TJGoKng6&+5E&Y^QH
zz*>z{YhQraY-Vylg!XODhtt!s-aesx??}I1&11x*NKBGrHA%hiv*s|9Dr+*;O-hf?
zGvfrd>K~1q-*5NkN`)b7mNUxaL^@>&(%xj>t&e}Jy`sSG$vL-VaVxhkWv`$!QK!rW
zett1(B@qVwP4}RCs@|{SkR7>1dxopozS_0JqQoK!zk~i#b#l$ewfwr~dou2^ytsy!
znx&Oe%LO*xizF-&sfq7JJ!E6%9>niLW9YLg?x3n_@#4b8sHvr3aTP(lmUrYdRTUDx
z8rn3sIIb2K;YGcO+4Nid$YNt%5G_`^9_1E8`c7`ik;ZS9xa+JF+{$=~vM#@<MANd7
zFD)ooy+&J?Q|b7z<fJRmIHzMxS*fvMw1G6-msU<Se&W7nAMdlTUNeDTJM6vVeA@(`
zf913~C9rQFGaYc+E+*eZl^;%0t3GduZ&p^G7C&mAY=4uHZkd8pUDs##hz5D<iv=~y
z<}VatOX}<DYwJ11g7S)TqR0)Z0~tXnU<zaf!vTG;W?{n!S~kBS6Dgv6CQ{{TN3g|{
zHi5SvMz%}`+#kU%r`;h2s9!u28A1@EzPx$_FD-4%L_$oNi8K-A2uk-_*;jU#d^h`z
za6f`|*~Sq(ZNX-SWX$^I<jAV%^jBI+G45c#l1=57G)|~Ahx!*)PbmKsH}*U8OVFZ4
zs3hMh1l`sN<vS1eyNyBPg!1)6{XsOXs?OH_$;0)SODUs+3`w&5KAx_J<qIX0R!ET7
zmj!aK85Pds%^A$Z0ma+Y9``Z=&sWm549Q4jeo`3SUge5N4KLhycjC84-%gCY{Tv>A
z87uLDk@9mA!Nf}+Bzph+34Y?UU*qLJx$E<58kd`II#jb{>rd|(KDW9}^!{ww@@>rv
zmgJU?UMH0{aE~XpoxCth%DoZSA9?`$ZvQAz^vPR^tDnTs<0n2yJopCw{wG+4pT+or
z#3RQZN!<FQ`l`}%4{zGN>D#z>+p5~yt!YgoPw!n<*|hGF^X}|kyn<@|CZ6I}F-xLR
zbT?}+3-55=k$)gM5&dQK-KgRs!*=VK;YurSv%5kF^G2^KM`t^l6VKAh#zhM%UFFSr
z*qG<Z8_nbLm@4r85Dxu(j@8k_MtiJawh}NMH31%@eTcGwr%%B@wbe{g_m^tLKVm~!
zIVl^YbhPoG*&r3Z!hg7@Qlr&tEEY>n#q#-!H}An+YnN*@I=#he%3ip%q^AGM#8WwC
z?F(H7gGyBqiPaCS?fXeqPF~Lfzd^53EsDhIwy*B~G35*pQoOaH;dbZX1;&bxRCX1j
zzaRc*=FjN;rSG5OJ{y_5PCQ?=5+3O&F=heas`Msm(OMCGHuC9j#PgH>GruK@GVCJY
z5PpHuc!X-<B#JU*;=Y9%z^$VvDMRV-+{mM;&)~TRPCYa#ANW^*e;v6W>G@$a3il?6
zM-SmX<uXw>#QSajKhYvMv*EoDzB9o$3&DRYxEGSLsV=xX;k#A*9q1~!7s9gy=Thaj
zkW*NLmO}j55T^*I5&R(!=n^>3K%6=7u9}|k-IFw55XKMR_~EXFvmVm)!re^$xf*n(
z@QbN8!A<jhJ$%y&XFkmnoa^CSNxy-7=P1udoiyGgjBb`sE(f4=6d~1RP<%K|k0X>m
z4sCiVLXKY{<o+{4UT|mCAQbu`LOG=f<)tGO-H%YghX@tN5Ssr!LKWXYsPZDn?g*TJ
zM5yk3sD^tGYWM>}%jY4~6o&I8Lal#7Xl)}x=M}*T@tqIu3vNWH<3-4B7D5~H5!wjh
zHUTp9KaW7HMQ8}p8)-pkdow~iFG1+SeQ-X7(5?#sYykFeK-%BzMd<R|5W3<OgsyrS
zp=%&7*8=-_T{%M6-;dCZke~0=!wKo%G=$Kt7KCntH1D_yp?%LFw0|)|cY*(p_A_i+
zLXMyc^ed!ftEb}#LMe*)_mF@nT9p%k65=QriGx9tV|eLiPt;A2f&47#=FmE_H|geQ
zg#n(Nypwb*kdI5nqeMHV!>CY<izVG^bd?ZKy7hXS@JtHtvEKZr>9%1^doSrGNSR)l
zbaN;-J(zU!v%&~Sm)??eE08HY)s~cK!E_iEvYFpZy49#UeIV)9E3QjF1TkZtgS2$c
zMa)ehBsy0xw}Sbf&)f`>&P~j%V(yEWTMZd?bH1cohN0}1VJN$07|L#bRu~zEvRj6s
z?3Q6DyJZ;4ZW)HMTd&V?jxo1pR{pg#Z{dfTTQ|$!K;7Y|m|LWI3%|_VY2Y@8|IFO!
zv%+VvGRkhtEPp%u_Cw}&vb5wlGiQbI%yMVZ@Y#g9bC_FX?mXspQ@3hX{#CQm(#`VM
zrOI*uNoXF5p#oG4u2uvL8Qhnn0kjp)5wr^pGM{RA8Ui=Hc7lH&3y}|Rs!%^15^4dz
zjqv>l8fH&DaPNW8JK);QLh9kDho|-6+k<w3PZNuME2NuBrx9Y`1#xeOcqE8-0OIUJ
zUEuBl_aM9*nodWW&V39Of-5-vG#}-%Jaj?~gAi7NbUPs(8b=q}oD91Zo_fKTzTFOa
z9G)%{g+m`JNB>vmX9I(U1iWw`l&GKib}~rJEu$RIK(eF~OJzH}?PBGnPa7cao$&1t
z^Vtrex*6mo@K4o81LTQ9r;mNNmBDra`@V;T=s{Z`O$zC5c9oJjN`;k}|1kJa_zh0i
z;7mE_`w_@RAAC6sP-q3$7WR#VRwT>P0%5l>NT$lw$#O|?qMPM`mSQt2?}q;oKAj!1
z{C}GdifJ1GYW*y2356k!K32|wY3OF7H4LJ|)1@wfw8{WeW@4A)o{6~`t%8_Z|9@^F
z8g_o&O8#GIC11pYnOdr0n6MMVZUuPIdfWg<U$RVjaIRu;ZH2gc;42xch8Qepth9F4
zu<#?v)Eim(yIFoIqzeFt3!ygK7_=mYxw{y2<kE~x*U$zQ;|Oc9^m&lMZVS8}fkTGH
zdiHG!nzd*(q*pbo?5Q_{tZj8eDqSqbJ_ezkEUhkvM_-n%{M^UztDj+#oGL9Fg)4nO
zn8YNBL8UvHR$nrPu4G(t=_v+EUnuzigXS(q2l}Ah&#v>Y%GcH}#Qm>BX*Ncs>UoIa
z&<M+U*E9}&dFkcUznHHDvtU3=B9~=^rI(^HLktUdG3X5d{I{}}*ZGwtl_A|Z2dZ)l
z8c1H{Qps-GmIsq9n&x)LH0H|j(2$gF{PQ}ZeSV5&(wy|OJkGR<x$Q5P!MBsSyOXu~
z#rA!6n+-EMM{`>aa(0xx$!BS7X05n~)lDb((Q<Bt5UF?3WSkeAMKiKlPCDV+L6(}_
z`^e=^<>vo{D*uaAP;#9WM`J1uDRUYpH-VoF?Nr_OupXp8Nj+z9^q*1o6mESrb*DAg
zJdOXuv-(aMuVhT=Nv5@tVdU0iE6HVL9!gSOnHQjxp_9R1uICgsZe`yOCi`bOg#n0F
zrm|b7F{KmD^lqs*|39pYX$W<)vQxPAv3^~Ka5wYW&UlBdEU&ZsiatishZ$}r^Z3<u
z%ld&i{TtMF_AD6D8kTd|H>W-P%keSl+{eC4h5m9Hm3tPAO2Pi@ulpI-)OS|7Q~8?V
zJ!V?X_UZPWs>57HwFg)#8>XLoW?=}WK5`8WLu|Rzy@Z_W^(-%P$l>Xbb7_fOhtXt>
z53^R%Kb?nEyPk_n|2kA>Qb?6@c7HJ!r)MCslfiMz|F9lYG@bHBTa%EP+m8+)nO~ZL
z%O(iXHLC|0`6u*Prr+JH1gU<jd=3@wgct`H#rbk>Q|5+JeZ>rXQvJ~kjAql6xnB)4
zS|Qif`eeDkyyxuviW(i7F8y$l#~NYnx1Z&JzMtJM|4%U>)xXsPw?yAIp*nb43tUqR
z^JxG-38-ibyjcTJHQ-wVJ|PIPD)~OdYHBU(hw35RYSzceakRj71w6Mg8drxT_Dr9a
zLHHFA7yY&ttz&7_LTsy8$QBm&a`0`0du=it{h}ItR>L!OFJV+rPHzQ#CG*Y=$v#oe
zX)E|k(<Pjns|J>0Drd{#sRiP%Prj{!xEok}H2*aHI_6$6ozJ>tPOBJ<Xv{Ru>LlOU
z!hBc5y&1x-V(C}0GRwJL!OBnv@8z=8vK-Kq^OI$j!%_IGNxq?VMDy2(8fTTNiou|s
z<z@zc)o^cyoYVN1z}r^VLo~scHLRqo81!nBFr%eyWKT1tl547(m4-r<!k`A+%i&xy
z4Z9Y0mGjavE4I0?Tg%?hgp$iwmAqCn$ThJixi+fVQ!A@0`ZhONmo2OuXQ#TBVPY){
zRmDoYY8pf881~A!PhqE=M$@dE$m!9#ot>8yR!je+jmWX2-mgy9^cUemp<cycLi4q1
zI_0m58QSInX<n?LSZeL<k(Li^9T?d)*dtXB3=Iwpb&m86Y|WRd`unApzKy*j!%|Dn
zaL>?=p6+}}udnY}Kh(2RY8vd>+DgA^?A$f5eMIUX*x1)4bqx&e8lvAwH2PSf6r{KL
zxl&7K|6s3F-?_DGpldVuE*<FID%EfA9;PX^_Vx`+{j=lQFfb%7?pxpA*VWlCB~yej
z1CXdRJg|MJs|RiyMs{`%^+?;dcJ~ZPBeWb1tx{uOSI^ero(0lyPmk2IWqnU~cTcy}
zFZ)W}J;Pl?eS@@sERF7-k<PyU;r!OVEj`213P`18U`yv#npUSYGSu1Kv!!!rvox^b
ztKpRLEI&JrmY$8<`#XoE@bbQ{p#hrR>@__@!!+rV{IVDe4xw4#=2gpEr(<Vetr_av
z*|&A0)U;s(<Xy^>R*iIS?eEzInHcH=sO3s)`npD-2#uXX-91}Jq=K@-d2IvRr7fMi
zr0r1D5en1|1MsGESQ_jZ+R`^N0+3k0i-D?kbz>ES0DTx78tC5MH6rzGm3H>_b@k5r
z7VdppyZX0NAdU=3-F?G@P*GCn)^7N!4+3;SC`dkEl2VBeZ0+AAh5NE)=+BO8Ybx}Y
zW=XCrTIQji;gKOI9e`?9^6>d|TnktZ!hMj+NY55p7ejrJYWKj-t^EU?vlE3(cgk4>
zB!Th{KvHnsJ~9Z%*4?v%0vE#c_Vf>)RU*Bf*7=5k{{8`06G<G(mDYC-Lv{wXPUBn(
zyTZLABZKA9XwTOCoqe18279{uI`apHHb&`F6hdB*#LnzosdI3!zYp*Q(x%aTd2{-*
zX7HP2h(;RXw-l0_1|ZwC^gTOz`k{$1h|X<r6k2ndoL=8d;XlmK5nu&C>4C2{4s}A|
zyK|)tL(qHx?YnwAhc-f)DHylzqLl`pO9Shn*=(gi>10iwhWtM(1<g?B@bExaUnfO@
z?t!lDTL9>ta?9-N2grnJjB`pWtxC4}-)6HMb@xDoeR4f~X*g+T-$*a@o`q4lNsOYo
zPrdH%15}jLrg06)R1Z?vPV1YNFjv|#(A~Fz-g_882Dd|jhI?~qlYpq#Zyy2AVd|O0
z5-4F53O?KeWE5hcb)AILmu8iHK$Dc)MH1316FYkcw)~SaQcT}Iv=uUwY@-7}8(Cg9
z^>mG-5NrmI0l&NZSlcR>QM_~gz>c0-q#MW(Z51p(v>gr3U`q1UaBnA+YJJa~#@RWm
zphGnIVW3zeeNaWvKIOLj&j3K%TYasxs;RDZZB<LH)UZlwZfRQ6P*YnYg{oG;b0}9@
z+t6Cyw7OM-5G_?JTHB<iI;m<!o3yN9MNO_$yRNyVcGW7WsYPm7-rU$w3w{kNsvB3=
zG^|)6Er#z_G(iv104)(BZEcchg2|{FYFE+7me;ma*TZAg;)ceC*0x-!uAy}Wjk69S
zt&*CnT3Q>bfp)e?&8u6Qn^x6A@--0ciiQ<+Es#p>^4b-x`H(93NwsU>L0VN`)!4|A
zs#*=XZ(;eXZfb68X;@O<D%CeN*3^RM;#$aA)#AolIVmVqbz@b-@?5E=YI)U?TJ}{F
z#L~ioC3Cm7zLt4GdR6eRZf$5<L5oq{w4${I9&@3TEv?g^u5DOVn=4hdG_0ZkscUJ1
z=qWhiizXHce7B-jj)j6+no}bXgg&ocRXdZHn%b&Hh-(%7cy{1?J@6j`OqQW?#a1RW
ztVg@B9wdWJ@cb^5YEti0W4+z-7%q1kcaZxj_XM2BxZ~V|UytE_J%;;#?HH~+EA{m_
z?*E(PxN_}%J(m0RSnk(jxnGavo=wfa9?zXSo|}Ts*JHY0kLi9rru%>0m@c%<8L6w2
z^%JS*H<%RGGe;`xnIm^G$%}XM1^hC83BM4oWe~a(s2}CHWt!EC$MFw1#As+0gdbwM
zMl=p2Tn}d>qSoeI+)Z>3@ToW8JO$@FiKSDY3!9NYv1#fgmxd7faq>hcfNn;2qAYX<
z7oeY^6Tqw812H$Fo1o0UMh_ta$c)b+9{B+t_n`o$`kr;jiUo8ldJUZiId~JD1ny%Q
z`V%%oJhedaEU0YiUAQhoS5F;-P#UPCpP=KoAFqNw5?U<D#SuvPhN%<Cio#PbOuY(E
z-$!ratf_+l-S4BfkO}D2ZuD(rhF;}YQ=dalvw*(di!Z_NA}{Jd*YZXD*wki_V~(KT
z;bq`jj&=#Js*eC%zm4v~R(xXW^{Kbf<2(j9??#uQt0BjS&<T>yRSWwO)gN2P;M;>P
zMz7&CT)@SrLQ{*UZUx_a(cegfJi{p=9}%ec3(&XF4*(jkpi}50ti{Fn`}hGkUcw&;
zuR`9IK|NfAMj_|-z_$;gW4Hhp5G%0)w5-5mt%i3upt~Xc!{|l447cGE_(|?=A(p6|
zN}tM@dV6XL<p5Q^73$(iNaI5sgD{W+=i^2ICq{&Mli!3AcB4Dci|8fD$DaW1AE8fh
z4jgZgZ;;(nYp3p;dXwoudr&D_iOyj?=T7uPsMVjLr_g`l&xjgA{+fSUxJWoNbtAww
z2<?6u;PFbp#BOvg)Y2g|0mmy)N)wi#6s33tZowPz4ftj}fnUR~5e4y*ZR9W9IQJa)
zN4`W5rph5E3vxrcerOH7Py^opXx|9sy$?N&p2ZnBi1VOCufX>olLe#(j=RXO$)C6@
zxf}S;g{u-L6YnKHn;Jt(z_KL(hwbQofWlv~1@e%MH{oIYpOEvt<YCUhiJYG+=Bl_>
zu8q5zyNUZH_iy|V{{a67p+V>r9#D2BwkBShS~hhB(=k^-zG#nEgysYOYyfQ9%;Xg+
zQ(l6;iN?_NfG;<q{pbNG_Y>$@^gHw)=zXXGguRgGK1h8FVBMAYdN^*y58@~B)A(8Z
z2L6~H#0N*1l#ohNP3p)-awQx$kr&A;<Q>k%b#c47Q8@N-N4eK{#Pj@=Fb|G;;acHd
z#dFHAvR=7f_5A0jCvzs-CjXQ`2}k1G#LbB(6K_wgnc4;U51>4tESI1?kjq;E2k(aC
ze!#?|=o$1p`aR3*-!Q=fV7v|c0UL6m)++H5+yKXNyb_MpaID4Wz|o1<<6by+<57GW
zz8qhHzlFccj$5E?cjE*2C>)RA<8b^AzmDI+f5CqvfW(9YYz~kRiIOrXX*F3wnn(*A
z8_571gJg*8fEv1&945!eD_j~E;PSXmZX0(i_Y>}C+{@gjJmGWsC||*^;WzS^^S|a_
z;$P)I6Ffq#&@1c{ex`6LiWI9An-sSw9#Xuc_*|(_HY?XFFHyd%oKgjVTKxjbePqts
znW*B|cvwj1FC?!+yRdPC!XCUDAf_O#Tt9a`_ZwjYKEp})4|t60<2Fy-#nq8dxB<L|
zJb`_jM=0kupzF{Set^6|J|u7R8Mu|ai^Kf4@grn_t0oGz?BKV227kHm4npMjsGMAi
zPmrg%%el*^eu~P4efV`@A9)E${7I6AUWZn_hkOq{`Zv-?u0`wkBH=UC2XH?iTnO-9
zM6Sj;+{^qv^d{#g|BcV!n}KS)fS2-F<a|<w9{`FwiQVWl-i8M8cTpTaivI&oAdK(h
z?!}En2ema$^msl-=mpM;U*<H>TT?U-k__BT&XCpIV~Q8KVvK=G{03cwIUEDrN&OPg
zS8PBxkr2={%Dwy+&qFr!J)rj=CLW^{TX<Et7Vzu`TrTuzG1N|;1D^awpfqnno4g9m
zL&pIJuSPL)3%X=#6n8Uy<{m(g3A_nKu@<PM74o(l`U?y30WG`$QvC$z|F3}RFT)?8
zomhgFbpnNX`sO;m7AR8((BEs}=tk}EbO*XoaYXnnYQk28cqy?Du>6nceCTuj6Vi8}
z3dr9%=m&f*<Ki07Hu&O>L_LbLl`qd>f-Z$TFM@X7%+~|uy?JUAl&}x_s7B}$pGAFB
z-$T_<cP&$wPhE>HnEJugdC-@xnz|3@?~bWMs08g1+Q=Fq!WRLJeHK3j{n5YUYk_Xp
zqdx#W3Sb-h3miXz{4Ww7MPvN$fp%6-T{rbRlmYPY0fg2=FM104_zwVX_1p<mm{>s$
zPStTBy$G+Pl~eald9VicPW1!jeGJ{L6oB@OBDZii;O@2j1`=bVaTXi}-}8h!x!-gD
z#Sfyde_#K;{(b%X`uFwk>)-!-KMNdI;J0kR#W+ER%?6Gm2P6~9-$#MBDFWVOK1gn5
zz`ra2K4&3tF^hrksRM4J5%{boHY&9WWXZL_^_>R?-4OnK;IZWOZ5!FBC!KSmV+Gql
z_M_6@PT+^W0UX&V$U2t+hqMQdF_31j2f6=d;EcWp{L_Ar5$^(S?Lpvj4ufPdfsUca
zK^A(F$&F8gr11;j;C_Xk177TT^lu=4{s#RPWRE|fe+S;|Pv~{vu1*4f_EvoDl_SGL
z+Xe@=Zt35=sjqkAhMx89t6Q5^#48sqtXNQ9R!WT{6wWJ%Mf3A=BRSdOP%x0?_jx6c
zJJaQK*lkuzdYYN;ORT3>KvhbGz;gtn+**HKhcq7S80Ulj`uaTj?C%7R&RHHE;}Uq)
z%?&dyb+BO4+>mhyx#6skaXDmsIwTgQ3RIDoE7kg?@fT|R(gZ$d<vMVGtH$3Zjh|-j
z<;=a8x%J@odf@}9*4A4ijpGifcD!y!?^ta|4McZPtEu)^_h|BR(Ls$CoLX>=Tm6Fv
zv2_t<4q~k>KS+>D51ATw_-ks%?fx2?gK;iU+u1$dymDP_jnnIG%gY_d)m{Ge<H)~w
z+!$d&P&G?tTv0u)WXVW<v^3~i>0s`OvFj#8w7w&v>-Kkdp0{qC>ujTGm?DsF&A9cV
zQ?{8$h}>MgZqMwuPHwE$)+f=&v9UeU`2LmaX212)Yg-${F-`(?9b<Kn@O1#fWve7e
zi(J{ZZX90;2}-mav`lj8di=H2r(=^euJ$kX_l|AqfQoU9jiZ)b-a`&Y{Mgh<<fxU#
zTG#o#<CRW-TW5{yU^*IW*>%_+m+W)j<mDa|O)^*y8jMMYPCwhxGyRUaSa9lE)-nxO
zOmpOK0CX6ax+KWSIzN=DlwNvD(O6e01cP52hOfrEp+5S?)zuwiVmbJW^!srkAo``T
zj}X+q|MdHFeL9mqih%eLqE3n>(})J|Q||FdWIQK_B8ajYY83Lgh&>nQ<?fgu<NiTW
zf*XJjH3Mur+sdN=e6N>Q@3j+gv>qPDM^~<spCz>3c?iX$k+yNtLEoH6y~$Wj-;Ac-
zOn=_t2Rwe5EuYUAR|Tj4M$wX1+gm=4E&t?okNkewD*v*T=d6=z$2yX*UDi71Nq%2C
z{VwUk@(Td?I3EB=HTVJbTFzNVJ>V|{>io5R9re)EAdll|)$2GXX_H;V$+4&af6tqa
znLe!3(YW}4g5iJngi-|v%zUs^H!gP6%hxuI*ZVJiG%<CCe#LGxpC!vQULKkIykO4r
zob2hwILI&`B+FXQ85`5gc~=L-YHX~|FV&58jCD>-jjs1gqJQidw~kvkHdxz{s{V<o
z<JUUJ>#l2qLiFPDyj(whGd9+J5OIOlb>ng8LChTUtFLVvZ;G_}$Ja;vUjMotNaSES
z(s^4us=-Cj;)8yC^~!^BeD$hx)*TZOlCExDcZgt8-LbgsU>3YvcT7Sk&U^{=rJnRb
zq7NYELt8pTR4lynSRA2I_LgTJ?73?KBj%?{`C-&GL1aHsPAJF{qB|6JP4M!Ycq%jx
zek$2-R1O_ZhE~BFk-j;Opw~d`rTjaHm_0$w{CIhML3|OZBmfcWbqIWpL)Zlv9bSYh
zvGX9r*}}Xh@aVw>apy4>Q%f@BD1@Ybqtkwna~f<`M3A0b@YORVSbfgA!;28a&#n++
zG5t|`37MGP5*T@*t$@+eF6h8Ez@0YX4nMSN|I&kGMTFfkyN@mP*LFh)dO{CT47u`3
z-EB0KpJE5C;javYX9c2kk3~KvE=WD$<P$u=e{6i?+{fPO$2xjKhZ@M28wlVt!%gq_
zCg*s6TVy&&=lJM)X$+9KoMLi0`*;aGJD_1N86WNHq-`7;eU~3RmV$@0ZoSjn1`*PJ
zWsG+7U7he5ADm8Ud~0M*lz{xW6_O?aTAcCGW~rl1>VU?ASFVGGDvb+pmo`9O@9(4y
zq**RcGteryb&joqZxK{Pn{!+V6l+6gkDoU0aayr5^kv$#bR4Z(H;$ZRWB##m3|S1+
zL12hJIIajb&>Q>*BmT}F%7$#9Tu6`HLqc{LbZBhOTEDjqf{*}%B>)aEYCXMljZr42
zy(0pUFpZhVq_Q!<>~?6Be6VXx2Q*+wl<Fi_)tydw0w6Tdr#6U44yX>$fbc#02gkQW
z4z?=;Gd}D;5Rn6`Sgfqi8*fepQL;ZcwnfH?wG>{`!edI0W$H|UCj=S*ym7!PC;eI)
zC#^|JDSzKUKXs-mO#TdfSkq+P>Hli&YJ;0N&hYN7zHD)paDW($SxaYuL2~Sf5)-&a
zcd|qZa$^?=SR@nKI1ULRW2dsxX=*S`N+(Q8?I|>$P3(M_W?~qhPe8>-izl77lT4@3
z>Ay@GoQD4BM~aiQ=_HfZeRd@X%<!i(mHj-=?)$#`slC&k?AgP)Cq$oYzxI&7*SaaS
z@t$f-Yy&=K%yP1sT~>~f8p7G%*@w77=Ile;Rl^JHZ+W(Y$ISWc66s`rCL`=m<Rai8
zepviS#ehDfX94Hz6nj6POh%0YG<=IxyMB4}lyKOK7Ds=^-dB#2WrV|U(Oyt3J@47^
zcqwt)>S7|lq9J<GENAbL%Yee(V;4z%u~fePmgtPB!a&&`;-i#sGRpoyEI=U!dnaGF
zG&*vQ{RaNG*;}}P7scMP)wxkr_-po4Qi<W6WG70V6Zwj{QDSD<L7Xe6z!!jNU<PoI
zUiK3*2n+!efP?tJ9B2gEgoTZ>arARc?7IVQ1bTrXz=4^41NMgnv)9>95=7bWv%_RQ
z^eJ{o>TA$N&{tqz0(}{Ip(CaI3sB*IzGQz6`32BtOZp7#)zGKqUne>HQ7Qiz%gJ*6
zB^_m1dkOcOOW>~sngE8>VWbXY>JE!tg}{_O!FI`(CZSR2BSpn@?Y0A&e2;eLZ(bN3
z#gy*G)bGa3?Z(XQCJwj;uEY!!V;a~1Vg?X1fS3WyN)yYXy{y<r3G4@I0fu?cV%~+_
z0#5-Kr2V_#VPI6`*tal`%h9U?Y^Pn%vB-AhZ#SZ`GwcCOwZR_9FRY0UeVHpO7Yh+u
zQBt3X?UCM|eAygf?a42yDJr5KHY->+`3|6vdEh$WD?kEpux`7qk)LLFkw-klsNjRj
zARBZHIvq_3T6vB|NxO$&NmjB3qI<|mp3!OZ{!w#3+b*u@z<!_)7zP{|Z3gyQb{~+z
zykyX+`(P(vf}9_?fb=xfiJT8{KE(N8^}*_cm4Jn(9q0u5N?zAh&y_MFenxnJW$;$O
zD)uy*2G58TumL$0ITbk-Q5Tdi&_h4C7H9{Uv`qte|G-y#O(lOP;FA6s8FR&Fh_cET
zMr7I4a%zc(w$S0_)X-yQ)ChtqD=YU8wNA92YdzoU$h7vh4z{vp@rV>V+!U1>3<*79
zFI*ID_L*yy3G^%j9sw=_jBs!x5CeJvhcW@?IJ-3hF`x~|08W%RCXQJ!FZqOhMEXQZ
z_?7GY3}ZNIuUXk<ejVqr3@`#P)O{5GqcXafnvix2JT2{QrT9^4=in=4m@FgC9otIG
zff$eh`T!?6&$i;cyH(T==0G1X0XWz;{A^`gm1FohsvKnzL%nrACkqzf)LuE)<2U`v
z9K5M2eO>aik`G9ZNv<<0HmIL&P=CHb{oV$384^l8G2u8YIbe8A^|-0Fnd)*=MQt~e
z08y3sl3jx7UnSoqIbzHUsGkMYPXg*k0rkaz`e;D?YCx1*jKe}z=1KMnrcX=WAbF|b
z<?64vx|OTVTs2kt5=HAIE_sRMYQgm5<GzHCl%1g;lLTs_w!WO>6I}|OwRIEnA6vf@
z@^4#z3G%tEAL3`}XH<S#&`<5UOWd4K|3TL~ME;YKeni)kap(+m2lNQhX$bn7t?v`@
zucG|($iG5@9ufaCX_w_j=z3{?u~hEIc4RwReZh`=8?8Q1BC^$I?8qfp5806ekRRHS
zU63I=Bs#d$)>m+IF5N-u6cO7^LW<}~YpKPrq2^uCJBx*rc0`m)hz1I@#nx_xEEByv
zOEuCio8z`72U$ZjS;b<a$xc_3kkkt5lbu&dP^!n)_MsNn@z5pyFa3-dIQb{_*)Q=A
z&SHF9ko_ZFZ;$ieof6Y!^Yf7c4V~n_)z0u=))nX$n@>dw9yrcL3JN{JCo#zuVikIl
zPegX`W194iY4GB$9?={43)(jRTnKra?~9xj-5`%(#9QD_NABRQ`Z!+~Dp0r$9gP{~
ze2w-^eml&o3v_*coZnhk5M60P9pfkY3beRXLsyRTRd?Urd|FvW+%#uI-2LwD?k(<b
zxYxQ@x*OcJ?i%-E_dHLf$M31|%<+_aJRX<F;ZZ!qGp{f^ZG^>tH_UVS<v%$%1UqEf
zuLu@f|B2fc>QQj?SU0hhlG+rfR%ME$Hpi{zaH`;*-Ds^2rz}tVJsp#j{veH<r96py
zv&|h?qQbPlT6_<5ics3P|6sMyf&B;5X_~U8x=Ct#t@Y_9jHDd*vra8uMHW03tBO_L
zG57X$i5pO7iLcq!wd%S(UaM;2*3+p?9rmg>-l&PEt*A`T&LW+%?i61nol+iEdXtG$
zN}rH)$F+S0R8;TUFCm~HEknZ~jnoiBhcJY63Pab>-5t^nEeJ@1bW4LY14wrYA}XB<
zh)8^c|L=d!(R1#1?_KNOz4q*R_p_hpeSS~uJuKF5-eJ9H{%Y-7P%}M1yj^a}P;x>S
zvn2)5&AuZ;c5mwKeY+G>-Rf=&GafQ_%=Rbqa9~A&0Bj=8%+SLc&7%S5aoU@(nRl%_
z$&3&0;}qzoA1)1T5bV52`LRI&T{I))Bgdv=AR?lBF-mtwDdJV3-=$&`fX$OxS?Wy|
zf%32?%N0*i2U#dW?YX*W)V&)CW3l5Ky0ne9)%H$(|E&2^M!#T{-O>S?3Zf?8h8N#E
z^)IrWY&Ophu)^0ZHw`P9O;@TJZJFCzoz@Nj2b>(BC#^3sM3~xQv%^+k?u-pp5aA$;
z8b%L8eXOd+Ssw4uAxs$<M}8%JDP^-}PXMGog~*{0qAwRi|E6-LUr@QhOUYMWbj8(4
z{oC^<sz@2;1N=`omjPab<`xdQwyLK#Slyec0-22))-H+|VddTS+~GJ_rOw(>T=t4p
zWny;dv&GxHjH$F6Eqa+@Pqe@0_04{;2QTN4BoBvoU$wB=><x5NE+oI1i#|+sS5(!L
zwR*_Wv?ON|>7p+?9L95+4w9>$qui-Hq;{*famZ`DXavbA!Nbi?Ye8}ab7Zy^PE>Br
zv60?lv~Hh2KU$eGJs;oR^eEJ!orydl43P2yjHYZp+YD7;TA-x5kB1@mjQDY?^ZR9&
zsR_AfsiEwVDe^y$6__l%+|(|g+Xt!KXLv+|Is={4X>5v#wn7z1A&2e5#*Dy&5oE;U
z_;I!1m!>MmBlzE6rL5EW?i$!V#q*PEf9W;k*S%YBpjm}eWiuZ$4E48GYb&3g-CWwG
z@QiI8iZJYTESz56T-k*MI#o8kv-4hVS2-xUV?K;#7U$Yx+k5EA*xV%Aou0G?%f3T8
zor<^F!$EDC;Qr|%ZC$S;<ozA%E(H_fHHJ=<8=7;J^E=K7%w3VeIw5asYB1*#DtuY!
zHh>&CAx4P&A4S@evl!O%=rSwyl_l@mo|k1zvXxNlLme-iOI6<494&W=bQuSaqcX$a
zlvIf7h+<AdlW;ZfEAG8s;bNgYC|;*y)vCz4wii@-gNQ6rt6;7j2e)6dF!5#3FS2*<
zJOj$>)#dA|Y^9J=xi&d|HSS;i$cu{&bF^@CcZHcc{2Dr$+2UgJf`Ht>Un5abTx>2`
z8+&({E09ap-qaliftfp5z<@}x63o%c-5Mx_9E*$NV*fpfccusm3Q9Lh_kWz4NAS0)
zAG?{u9NmEe{M@%QN<V>U!rXzs+-v+2m^#bDY^<!^f&ARRG$63Q3^;iBZvEauvT_6R
z^86Y*Il4<pIe7#1IrzDGfE>KsU?7Nxj~fW$<^dc2t$_>%#sdTiAYuG+A&az9F?E0;
z!&8&d&{cgTZEA00=8F6>4K~*kcjVaov7?ne45^M3Xu883o&p7bjkSE7Z;g=Vx1d~Y
zoZX#Vkvg}jK&JFp_CWl<1uJFh2D{b&Pp<w7%)->s{Z_*bsL#uNi|`k08AoKwZ5*wD
zTu&^J*|Kr>;gJ7@#>3407l>OZe_?XccC`6bA0DB<1N<k>KhXX1@Xsp$Pv~w7<Ku=5
z{)wZd6Hru?O9N(QgDkiYkmWHlR2VCeOV!l^=6VZ~<!_Kkp{9qkvpvk=w#3}x;<uQQ
zGif==J%K2jI{!1A+Y5gr@>ieyDv;*iQ6f!mm2TttRqx*d<I(}@bL;bS3jld|z(B*>
zy!~q>ex>7|vHs5;&BMe0-{$}9X~P6%+g@&h@bBUX_7^e<dkvtluwYULg)Az`m;F__
zFZ*<j&d<^ZC6dRa%q&-#v$LCL=9d=luEXCta!Xld(NSGNDDn`i!h>JYVrE_JrVFu1
zfW#vL-^g4_3^()G5dvHT^1M`I{Y~C?T$n>G4DlnEa^c`HQTrl-K$kTd3+<5ZgR6x|
z>>OK3f@m>^i|KDumx-bq!D{TG{-DD4ZV*fCYlHZNl%(=!U;DKmM~q$SRG2Jp)5_o^
z@B(3Uq$bO67f<F_va+KVbe}Vjue%F^-<#uzGdPMF<x{$4{>OXu*G=+&nlwQW|7}%%
ze-h04-SeKAoxN`7UHooBgoZxC6%%a&G$o9Yd?yLGYl=&rX*z0QnRMU64FJ4L*1$q7
z<6x*?Ii=SCei}q>@a*U6XnSL016!k~mqP;_`^T!^cqT!~h5yawkL=<bCZElK!<Nl#
zzr&Vc0~&q0a02ptW8Lt{)x~+wD~wJfjA3f2!FFoY>KjBv%=hpbrBDY)tot5Mye#tf
z<bKS=RSl}p87a#8NDSFziHRQ;16WL3&}gBCt6A+<FBv!U{LzPGo0=Zgxb0O66kO&K
zEYAOEM1Ho$e@Nhj7}XKHBVO`dZp+sD+KnOg;4DAT-ic-6XGYKR^RTp-^I{di*0%1#
zg@!AhYzEsH(W5>Em&%sv_gA@tFO~D<M_zn?uc@n_0Tw$oh0?S4B#b^(mWO^CQGR3b
zK_Jk-;ZuhYD^|r1Txr*fmDy4(<Qo40C#MDD+B5-ISs*Lz4*EyNe&0?7zKMHt-c$@N
zI(1xbjF5w^y3hB13Qr;zzwH<knoCB{n!B`}T}@ww?$^Jj*@7gj?|eNTPm$1pUK<GY
zB#)<UC;njkL4hIka%Se)gMrW3!<o}V8)MmGc6qQda#-9uA%KI3`9V5PWu2As8(o}*
zHxv0oQx{XkyOrf}MY?CgW%Hvd*?i(nKoQ18o;>f76O2M1JAq`*lC(5iW#w9?;zAW6
zx8u+KW3BHx6-IM(b@^PB^p?`1Wx|QSX~uWF%KUb0{K8GV^vTZUXEwW`%h=gsz3O54
zI)=j6_m$abye=-2B0O4(KQqFzlTwY7UkWox*eUGy7m$*usDYRs05mEJ9@RXvt$wXU
zaj_WcMC$m?@F<ZiwFsaudX%~{&JxI4=(Y7CKHezl+H=X^!E`N(hR7PP3>ER$cQK(k
z{+GwyCr!j>pCn$srfL=&mub<F_JO_*2@gQqbs+S~*DwfMnTl#pcx_j#&-7`!jPl26
zvG(`W0!0P=T<LobB*kXMFH|VLykLKh@FEh1C5vg>lj1YEzY;VYQ`mC1uZX>uWh%tt
z#q3_Bo61L*SJ$`w<h@hlm)6&mM8b0JMcE*p8)zw(oNMx{3k@m#+@SP{r|Ox$40$hP
ze=xu+W`da9hgkf|(sEuVPuS#hR|@A%%NXgoNm&if+FXZ?J@~SXocbk;QV@M!-IuQ?
z_{73;BctwS3_Pr2iB?m|fA3EU{8`3dYsxONj=%m-dlQcI2oZ0e5(vvS{4O@F>>_=S
zWJXliQ*;ud_KRs8MS?PYtz65*t-flyS0;9()Fn8(8Yoo3-#z^=K0-r1vyN=SIZAey
zWgY;yhHh3riLPvJ0e0Q%o%5}vM`T9Q$xfq<Fmo@yqY;Wdm00rFHfroH$}fL~rz_!C
zwBJgFFj!p1I*?j~2Zs6@k=)=5>BZ@agD_s!q+xS)9{5B%E~8hE(*}|5T=~w~c9^aN
z>6QndX`9=HHsG{sp5)b|D~u}tfDnSv+IC_sXJV}%`#0{gh((tWX3_3w`b_w1=OjBd
z^yB&lI@FZ-$e7}90q7jIXA0sNHa<#^@=>=a>I-{7xV}nx9uz88cMNGbnI*5(xNjS=
z7QM2vn7OMJ-|owqY(B;vYj`>ndY>#!VjsfKrYDd?6QnjS$n!>()oKQwH?W$OMq24t
zekLluKFO;AT`paotZ2$JICk<o<D;%rl-rv2iDFXe+w%YBsMUTr0X=1!V|?uuYPO?Z
z*^s!9!AD79?$;xi6=xW|ML6>8srAo6HlI@(b*sGHFrQ<*GgAhml}@h7pztxRJ7QzK
zO$v;9<sY!yH&x!>kVLy_+*>KuDKV7WkqHym)$Rkg8`(0d#teBjWU#s|%dY#JtQNAL
zZ7)W8G(Pmr>h(3&u#?_Y-cJn9HdXshIN@eL>mW4k(G%|0!ZHcwD~mWwHO^W5<YyUq
zFkJk7#_CiN_GMQ(yWnExLT;|Bde`sNa9)7zu-&(4C3-}&BKTTMWc#yEx$jb~=7hou
z!_NE0xRVoT!OnHl;LT4e>iDsyh(y8fgkp{#?rk1^*c>a~|LihKn}W(u{0e79%HJzO
z){(DMe0t@=-cQ1-DB0@po=_q2<cssy(8Rc%EYewys|){<#XGX=EaNHx{T<ff*VSW)
zV_x-Axq>m2l^7D=N?*j-ax9eBat!qJPC#C^v#Ney$@aa|v#_^`CaPZHwIy}a*4T|+
zkRDl0Ak|$5{PRb)Z?n4R)M{8KX!cJcWGTjYiAcT?xb$awgs73x#k7#{S~0T4m@FJo
zBqq$$ZhehtBo}j#eNE3@wtJ?gTCbBHAZFOUdSC)HI8OhhM{}xt98pYh9bC&WGfgZ+
z7pN02L9hevSv{x;A;ema0Xyl`)Qv9?#<-Jxw6=TAYm!^w7*x|HW^WSpQ9c)kqwQ)-
zU?$c@hYXjnfMYEdA{|mgi0v&BYjP*xyk|PbIh9oC*vBtV`$d(t6~h8NVP&#P@^1D=
zNeI?m%Jw{(7+qYlNf8l0PcmxxLc+fH{)F@k4iGI%<lns@;n0;W95*N2#@((Nb%q+=
zXZ_s{A=qPwHl_u`%PUsr`MP)%O$z2-CXs|+%{cRbMX?d9oal=Xfv5#MMZspAgG3r7
z>$X=(^9vtwJ=Bfax;yZk?xN#_u?as+T=hvw5%JtB*;>EUF;Qlt4`>(Lr*m?WGcM$s
znwzG+$83<|_|43DIXS18`8nMg`J^+7bZ=RSZ7)3Lj+9}yJj0rR-p`ZVU4voLJn(Cr
z!Bh!_^u<ZS6OR~M96ZmT!UchRi2Ik_ND7#+n)x9v#>cf#om>$OQ|Aw2EAo5EYg+UZ
zvt<<2__L#9IYJNjs~Rz<9>j$`6W8lZT%CR6Qt`tVMf2GfhQ9p%Si+L^bvE@%me}fK
zmf46A1uFn;djGM`d5o-Y0ipe;{l~_VKiuyK`>DQ~xUu9oQP8?TcQCT=$98J=V!kGH
zrN1r={BrN6N1vl{edPP6?+;xh4OnRitJeV?1UtLyxy>Y89-5*|fec23H<1zp7fEf9
zm#5;FcAp;5MM%&DZZ1@Iskx4^45zSUC0S54-QUFR^h?@bG1tM{q^49Lr{{5BwjWlk
zxmKp3zFyF%9O`w`UUUVyS2-R(-iaMJ5cXVtBBV<{2gfxlSYXgQfp=9OURHXOxUVzq
z&lNh(G<>SVE#$aBtj}LG&mVi4J@C5p49JKiX4LkI<CHrcZ723R=5(oA;5cIt_p%;#
zoY|ZDlGSD8Li2RP-zDVfh((K<KXk9R%#i&IUhQwX{fM58iIXtZEQ^acHK<D5S!x^m
zGEmze_vc48mxg9pgUA4v_U4ZayA4a%xGn|F_xxmM4RME+^-7np5Yy{4F2&7??=!p?
z?UgOUzD*UmEx@Vv`tNg5@tX~Oh)cBJN4%eXZx)??5O(!UouiTYYl$dV7_&^Chno6X
zW^(i+Zmg*RD@bAa>1DjWoYfb2MP@vuENsKqP-DkpcXQjWPrwDOGh8)AyRZXSd55V|
zZrO?ISgd4N;FIx5lL?38^z(G~CaDih9q_s<F%a;e>(E6^kMIL)N43t_gV2YZc+qXO
zN#CFU>`Q12QeUxJ#An<)CLA_(>GVbs`D}X3;`nOdc=%<ci64V$fW~skWwSRL?2Alc
zF#_LN`bzf_B1)f4s+xC_d3{Nzz!jC+r;2#QL%Ab!%<NA?!o|?Z=z2s!`tCdZxIomX
zS>1FU7ZG08^z!t|Y>R_kO+h=yn$yY~pXq+wT`@<UZ%ak|<vNuHwQpUZy;F>*9u53(
zQlWCvK%4GMA1m!FAukme;>1RCNI}&@sgacQ^X3;zE6dl#g+&a^P!0{Ha<`c#GD|2t
zU28+P)xDKX<Sn<i9J!v7KWW-2^F^90+>=-3#J#6(pFx$`M_5i2mR&2!o+dt8;zqVn
z*MMg(UuFC$LR@Y4h-^bduX;kbREhMBIt%M#oPw(6f;ny&T-|EU=`d=xVdmkgiKT38
z0aF4f;1$`(VAx0)PqCmc)|cdP4V>ZRR-aHn;>*fb{>nlRqs|uJ*tV*<ryA>%VD$p?
zbXI=LvN+hC*)#-W|60AAc`DwQ=((3)**kj=SGK^FMtskqyJofU(MwmivVytH*4;`o
zB_R_Px0$*0FL-zC>?yV-U%e~z!J|J*>{_Efd>fFD$f$Xpyb-{Vtffiygm?#v6N5|N
zcd4K-qsvL|`uypGk!yZOwof^njm^$aU-~I2!pnS;?XV5YigN5^Uo{CT%xKIuFkCl!
zJ;=DK>_4#??6`h}pxwcp)|;DpZiTl%86{+E$LcidI1R=5c*3-yCm>irbiE2tdRQ`5
z)9>(9*mo3dz|1wcTg{HZV0TWLXmsQmg=YOZQRT=`s~$gR0q2~CBDz*BmEHSD#NJ2x
zP%E-V={f{?PeH#aVAe!^XvfSkD8t67_D8M6^8KdDK6l>)@%UcqqY`b`&*_@+xot!%
z1&-k@S)WJ8Y&S{^Z6cP<>U?KxyG>?3_11c$vVE;FXf1i_evH=3;qYu_La|4>lz2VY
zgrgE#R#s7FGpeB<T^ttJVItqymzJbBTCZOF)r5?k`1D(gG`$mlZmFzcuICJj>fKkF
zWF`-ntm3EhT@$y+IHqP?Ilr*kv8r&|1HvYm8lEE}Sf5fl%5{BoF~JwoX`6koRdsp+
zuJYikf*#J5XDu*}GAEaGJXa`UdCX7B&c6_P`UPzC)X*q@m>yBctS#W&ARYS%@C_f^
zu5@Xr@o}k)>nJ0Qn|8~9X(MvYs2RaxRZ1mdDB~yxzhL=k^8wYVQDmak%)nde-mA*m
z$HlyJ`twsD{LP0O)<*+Wb}KmczDLRjVvUAnhoF3QFqli01^I>Lt%RTR_l3V)H|(xN
zehcG16KMMcuqm~H?vaa<cpUUb5U4mbu$1$ZJ<G#p(;&vSS^D6)zzXTCQl7#zJi~pG
z=U`+1qDR1jPM^j@t4PEZ8^<=Or2pOOlbXWB%AB{w3~#5^UKHCNke)vzY)uNp3|FY(
zrC&_nQ1Y^bzTuEB<w2OX&~|KVPz@z5PJyG+l$S&qeqv2$HTDW?X!g|6W)ICtnDq{(
zESE@b#WNiUi=)r`e$QhMIlmyLfzRT5nz~?}5p<~T-0xfpY7?Wb1;n?CK?u*-u3xiK
z<AmF|u=ho2z8SeMXHuKKty{4-J7lDM_5h}e7)zBQf>&~`=)%!SK`Jr&3k+HO<=8g&
zaq$J(6tf%JKe2X0m+n@0Wo&;rcU9yx#O!3m=HTW6{R}YT$NT77-dI|QD~><Lh!v(7
znjUv|JNoWX$-Kjik2F2)*{k_H#*t>>3$dbN1CJd%-xHrvUWCSgC~skm8B=O$9Gh4z
zC=Pn@wHrFl(yps6+|M-E`p!(6Fw2MKNhy@9Wjut<82;GLf@6#)0BW%?NYs^;qXn24
ztYKsefAz9~k5{BusajI<k~IsOcaZscN-I7Rvs#gqnQFo-J3X2(B~}5JkNPIG43i&l
zX&95oHb0=1#xI@!u9jG*n4&%|`ME7`TYWd&Nx(Me9=zZ=WpSw@H!tC*CvS?%(yizY
zn~5SKoZL=QVlKK@@;a_&u8A9a1xtE}MHWpQS#rcV_ATrh!2@PCi#aR7UsGO+^(<Ml
zo|Zac)GRssc9MJSluy;#PrP|!P&Y%RztJTSRj7rEPyHxPHTvUs<j+F*G;|D$&p(NC
z)i9nG_GWhyPqoO0z{z=+RoOjb9_*4Fk+E0i3fw8mKhWDtsRY*%i@Y$Lc}@nR9|w)+
ziMxM7mO=M*qIt-EykRk(a_6{nlUW_TNq}O7cu{tVxYI+2=<Jb$uf$U82J-eacQmF!
zKXoWMXbLb?HCy@(HOzW#?oc{-7Yo1LDL3ICwL0~^(mL*+0g!r^dfQvFb)+r5MU}hP
z@mR?NUHxp9>;=()?1C9cZe(V&k!I|!afJDN?%kmFFL+LpVtLCmIKsKhbLP#$B5bcJ
z$3p6;f}xv4(Y>?tW#ayzQ^^lA8gWXW2m1SB>dcy-34C0pFCA&B!Z6m}p?o)?xZjW$
z#=uvSgcULfYS$8)B2+8bW}|(dtmpea|HgOdoshB|V(``b4O`F2%_q@rL(0PoY+7aS
zhKo)eJBlmHT2Z$>%ybsD?0W0@+K7h>mIX?Rz((A*nDA@7Cz;jV8ZAMmTZculmg?ry
zn3O~!hJDkO@`I^|DqJszft(gDsPJ#llRCk8gb~0`cMrK*D%_C$LU+%iHWc9rPzMkK
zOaYrUTd>LA{0tdVxC&rd*B(Y_G1;A;B|`~E!I8kBg+B!t0XWzjYZgY#h~cs9;2PcW
zp5C6(b$h_BZnG|5o$hdcG=c(94y`b&O+sJ;hM|0Kbo=u|5E=kQ-I=-)bM@i;2!t5`
zt}6)Ds?!}@S7Zm&q>Y==!0U9iY6V{)3;=GrncZe!IF#M;O<H$;k_-lXo4u%(#mYq(
zUdmonBN!_~4%Yw_zj3Zf8_5p~@9r5hBZ5b>Gu718l8u{D!OZ~X&<C|F7V2H=4*=%6
zpX&zA6Nev0%7EeQfOK{q-Pd*U=7~cO!)18j41lKq03az`{;tr-IvKoxT^x3N4;~M_
zgd<nyx(r2pfcp2XO9O(;k97dFHQqT0KlWAFF&?}LdKr$$fnG)<XrY%Oh(qXQ973Nx
zaClvSebvGx3_;0mWOYmdH?H$eK~(ErCLy?V-}bC;vIq9B!vGSnV<I>y^ljI=4`963
z`z3;xJ+NnefIYBpJ(4}JYuyH*TI-#JAZDkrIwph5K}CDkO#%3|-U$eF_5&-IGz0<s
zr|$dVbsB(IonYU?F|&m5ck7%0uQ%u7a1q`6HRm+&WvG8D!hzip=7Ix1tZ7b1G(r90
zh{phd+U7)r0Q7y=x-Z~^$*~7uzP9-#f}g$0(uD;62<jh;(199sue$<LYX!U3H2|qK
zQMKpT@GEvsOBX_T0Q>nO{g40qU7G#;ivGv{*Zm)$8t8xgFLpaT)({;x|0yYv)sf>T
z;kh^^?t%VOqG}Q;WAsauImsAH(uFIKO``pWJ8)HlJ4@s_y68)f>$6xCJP6ssqot5+
zK5-XNNoq-CNrpjdlyGz-f_WySkq9GNIBF?+X`R^iF)G`SXn#m0#3&z-&jHCOU14H#
zU|5o@&mNTi%p{y)O`QlYNw?-uC!VCppM{i1Jte9H>Z#1g*Rwm?q3{!M#4f)Kc}Xxk
z;1HYJ+Uy`y^0Fkt8Z^t1@2Qe+Yul8tr3k?pbQ7NxwG9NQlT4;V+@d$sYIvh8HItzb
z-e^m;8ijmpTY)TV3U#5$ZHQ)c5kZ!0-f)xx>qaRAFaO<x*08}`PtW`(5aMVig2kx*
zfr08fvGi<l@x~Ywidv9<seCk^Y$?77mYkihQLgXOq?47CWjxX$<dAKxRM}*OWFp!o
ziexI<Cd_1r1!F<DLXy07QZHnn9xkd-s2VL!cagSpEmIgobQQXF2%$y5Gal3S!{?t}
z%NBML1xTKV&$i1IdPT3&`DW}~OPyHpTt{!kLxO-8Vl9_(3Qp?VO<EVYlNk`Xk^|iQ
z`FH0Olhx5ij29#=mq`kpKwn1jGy940Pv-L>fwCt&<UtB2M3Zm`SHkc&$avy0G~X&J
zQ0m0o^#|c3{=0MZ{Nm{BhrUT$_rCgPD#R0tDV*G$6;nDPAV;o+5xf<c-wToc>_eM!
zz}OnO<(MyhoNucpYE+NPCvQQtBIC|H`91moNCCVsdVBYK!`rNU|I{sTSzF2$ApekH
zMd`#L--(c#p*8y1ioANq6L<7kL)8=9{AyxDIoztkDSn6!v7wBIjz)4dVL-}G6|gmP
zizgo)lA5&1sP&vMAlzDF5&<Da;I!uk9QQn(NR8%<A#Dud1PV(SZK0hG;JA<ve_IcC
zd+Zl|ruJ=R=D;A|@K{QsB>vSQ!(To5fDT)8i-2DuvP8gW3;k5B#_{Xk!ySet+4>X~
z`F&(Z+E_Tuh)RBDR;5*cl$cr)ZjCc(`Ras;Vo^39mv8&@!ICs}OY~UL$Et!jg9n9w
zb>%DX5aN1aqg-EI5-zo6KiJzfsfp*_-R={vt~LyM0Ise!NwAs?>m(7++yKtmvz>Je
z(oow^7@HxsnQ-ij{hw!0#eL((r;A+4+GjWhS5@DzE(|wY&YI8g_FP~GiRpg!eiYv`
z+pJ8+%l$NXJli~5#;6y*?6~ba?^7*&Z2jPxXkEAG#_8-p8`YYWk1;7fb78852Z1?g
zjYTQIqc&t>OZXqHW4H96)1}_6#5;`~QJeDTb!V_3q)P|!U2f$iIB1A1w1^~U=>)}<
z56p^8eA;o`b#*`-J=5N=iVN}7(NFn6LUz>VkNg23CvCW$;w;nrMu>7%toE)UCFWe4
zsJ7$$;*qh=?4BzwU)$W%N*8|I3YW?<y=}dFKcAP$&VLP&oqtnSSQQacSjDJ)S|zMx
zs5F>iqExd{idvBwoOn0GK(u$Gp1QW(Ns$OVeO59m%;fbp;4RGdKoDAIo4H5swc0#9
z0Cj`sa5W0Ti&e_UsefKB2=sRdfVUrPE|ij-=Cf1}vb+J5wUAU=SIrw3DvG+rWtX=P
zsz1%qXK};X4}aPE9s7&8X-Y)0)J8~!%~6X!U}?7!|H*04eFcDq5#6g{%E&2*W<h$R
zZz${cj6%EFVz*IWURWoq!LC3vR^i)`f}4UoXzq1+HRqv-v!s&2dutVg-8g-Gn#|^f
zY3s8``|h@474^aJVt+S53QjMP)WYaX`X7gz`Z%=j{KUtTG9J0PMY?gc2%S+~filfU
zM;op5X9k=b8(0LUvu#|ot*VCVUkkZ`WUR(Ucz3fF&(&UxzSCPVI2@^{>K-^DKmBrH
z<!0gL?IxHXnDTXyMWOX!#dS|&N!dWKJ2W}yBYsOrW7sjVsd?D$inObXzmk~e^}~nE
z>im;E=VWhTUs6lzf!T+sqs*^J$93k{pb+ijOU7K@Pd^+d-g{sBPEeJJgj#!w22of8
ze8yrn%cYV3eyHw<WQ%4i`Qg4}ihMj`h-6u_VPr_TQ>c@x+lU&k+$|;&V%e~G4wdS@
z|J;oE6=a`@NE!HsFqWBubbR>^Tim7tW^C-H11bq22@wfF7V;@c@mVuelxKtJ3jvH6
zmT1M~W0?TTVu@u*VF?#~@s2k-=IKM6L<XX<kMEzh_0$^VTv=CrxMn?J?i%RoH2KMF
ze}i(3=YPll?#~awo%sjo$se#*(N{56L#`awxJrKV4h5lI-@QaV4^U~l@)DvxYYP5=
z)`_|rwtx2=cg<ssKRF0DkmQ`?NO6sHae1%WV!Zx_>auQ6<>&As>?{Y3>v3nAp<@uL
zH;p&m>3GkXl4t4_^MpjiHQ@<<UDHxf0(HGa){1EmTiePt!;*N2cRYGL>R2i*Vw1kB
zw@Vtjxj;LDy+}KVy?i+Sd;uR_x+|dO1J3)<);4voyN!a}chkBI(*w>#c)b=ob6S=I
z<u+)3N^Tha{2sg<a){Q1+Jx3*q0$tD<<EQMQ2zsPZn6RXsXQSd6-3;Odg0r5foT>%
zU0W5pueV0AX1m6=rm$vb{aw4S?V)+$)z=v9vtgd4eJmcwTH{wP8CUT5A2&@B;P^{b
z{EwYCk=Nh3;1L|gfWYDKE{v`pk`m4|HKYsZdzfPwo~Qv`DkfMp)KO@J!26l#Cum}l
z0uvbSXv@Ksk_1~QOCew&$~h|S1h#hwzyzm;eBqA$9Wcr+D*hVg80H)*XD+!e4j-yr
z@N5^G31bbKE*>A+a4@C`Yt5Y!tes%JTuj~j>}Z*i{51sUL^UXB_#^0JXl22?AuU~0
zYxhmS+&F3XMo`#7uuX)yaapibu!_($gQtUeavuniIHSA>A?iZe>tZl@$c<Wq`YFUk
z62uK)LBkF~TYF$~KLP(UYKtUZ0<HyWx+G=--fPrSN$iCC3>*~w#UwQ-L<ButrY{D9
z3%ZKCel<~W5Zd28bcuWZ=m_;l{D|g=^9b(<d_=l7-jx$9ffj@kh<}OajdRX%M7gHC
zcJ~PLNcf22$Zk!0O{a@1#2BR-MFJ}j^X>i12j2I*3B7;yi#Na<^ZeeC`I=l8eh4j!
zD!MAFDw-<FZHL68#iQV(<D=rE;iG&<j|`z(6JIl0qgiuYBOt)SL?v#<X(m1wcgEsI
z@yBnbKIe3%bbjQFb40ynxwhQZ6dc;6+!fm;5JDNe8{&jwj8%nRg;9lCg;|AGb*BT<
zpQIVBnX37|Ac_ID0a{;hHOkKrcnCZ=pr^CMc>Pi_Gbs8Sm&-NdSZCjlRKXjf&Hq72
zj^>Od{~nddE4Ysu=<@$`_&0!`L{`S@dy1I>(RExdXN+SVeT%7rNa2k{0RBztjra95
z`Z?DP>*^b5)D3EAdh+alBnu!pIRDBSQZu!JxdCr^M88NJe{nUWO_78eC#yfW8N9r|
zSw8k~w?;B)Sgvnak&0Z>NNSS1jgun;$vpzHK!ka?K?2<TARZ7mABYFc!Oh3a&CUEz
z&3~~}g!y<mxmvjWV=84Qi~s#BYOYQe9_C286A}Q5EQ%9~H;N64I|>j*0|ka+ieiC0
zx+2fiP$0;wx9_gV>yAi`zvNGUy}Kc0PDm*bMG%D(g$McKM!rDE5eP-#7g!{##TI7n
z{ts+gHttB0(SHa1ugn#1SC}O(HaC!$4|)8@1_bl-^MZl5S8g{D7%YIy|Lq2J{HGoW
zNw)e^#?SYsj7NYES*PFhkSP{I5{Q12{dM-&@gIH#dH9e_s^9eZ_;|tp0Sgk@@3wsW
zVDR6ve_-Yj<o**2w*VOYZ&(C`ZW%ql`33Rv^CS6IzsUr_JOaq>`c3xN*<Z)M;}8T3
z34s651Mwm$Eq}_ue4sxugTR9Pe_{p+2q4L4zxxFV@PPl!6$mWwZ<zV`K%hTk<KyS%
z{WlpOKa!{PyAM7-Zk|8m6$Eo5JLPvhK`^pm{!PYrOT4??{?S8%{6c(x`Vivh0sZL%
zDHHe?TX$DeB+Jef7aPeG)3ou0A)6P-rQzg+r1srDB{Y!CuUj73uNz<EFUF9mtNUM_
RE`+S204_Eoql~KTe*wID9n=5-

literal 0
HcmV?d00001

diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h
new file mode 100644
index 0000000..50758c1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_flag.h
@@ -0,0 +1,87 @@
+#ifndef __ALT_FLAG_H__
+#define __ALT_FLAG_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This header provides macro definitions that can be used to create and use
+ * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based 
+ * environment, and a single threaded HAL based environment.
+ *
+ * The motivation for these macros is to allow code to be developed which is
+ * thread safe under uC/OS-II, but incurs no additional overhead when used in a
+ * single threaded HAL environment. 
+ *
+ * In the case of a single threaded HAL environment, they compile to 
+ * "do nothing" directives, which ensures they do not contribute to the final
+ * executable. The definitions used in that case are provided with the HAL. 
+ *
+ * The following macros are available:
+ *
+ * ALT_FLAG_GRP        - Create a flag group instance.
+ * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance.
+ * ALT_STATIC_FLAG_GRP - Create a static flag group instance.
+ * ALT_FLAG_CREATE     - Initialise a flag group.
+ * ALT_FLAG_PEND       - Pend on a flag group.
+ * ALT_FLAG_POST       - Set a flag condition.
+ 
+ *
+ * Input arguments and return codes are all consistant with the equivalent
+ * uC/OS-II function.
+ *
+ * It's important to be careful in the use of the macros: ALT_FLAG_GRP, 
+ * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the 
+ * semi-colon is included in the macro definition; so, for example, you should 
+ * use:
+ *
+ * ALT_FLAG_GRP(mygroup)
+ *
+ * not:
+ *
+ * ALT_FLAG_GRP(mygroup);
+ *
+ * The inclusion of the semi-colon has been necessary to ensure the macros can
+ * compile with no warnings when used in a single threaded HAL environment.
+ *
+ */ 
+
+#include "priv/alt_flag_ucosii.h"
+
+#define ALT_FLAG_GRP(group) OS_FLAG_GRP* group;
+#define ALT_EXTERN_FLAG_GRP(group) extern OS_FLAG_GRP* group;
+#define ALT_STATIC_FLAG_GRP(group) OS_FLAG_GRP* group;
+
+#define ALT_FLAG_CREATE(pgroup, flags) alt_flag_create (pgroup, flags)     
+#define ALT_FLAG_PEND(group, flags, wait_type, timeout) \
+                      alt_flag_pend(group, flags, wait_type, timeout)
+#define ALT_FLAG_POST(group, flags, opt) alt_flag_post (group, flags, opt)
+
+#endif /* __ALT_FLAG_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h
new file mode 100644
index 0000000..9c647a2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_hooks.h
@@ -0,0 +1,69 @@
+#ifndef __ALT_HOOKS_H__
+#define __ALT_HOOKS_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file is included by the Altera Vectored Interrpt Controller's 
+ * interrpt funnel assembly code. Only those macros relevant to the funnel 
+ * should be seen by the assembler. The funnel code defines the ALT_ASM_SRC 
+ * macro. 
+ */
+#ifndef ALT_ASM_SRC
+
+#include "includes.h"
+
+/*
+ * Semaphores used to protect the heap and environment
+ */
+extern OS_EVENT *alt_envsem;
+extern OS_EVENT *alt_heapsem;
+
+/*
+ * This header provides definitions for the operating system hooks used by the
+ * HAL.
+ */
+
+#define ALT_OS_TIME_TICK OSTimeTick
+#define ALT_OS_INIT()    OSInit();                     \
+                         alt_envsem  = OSSemCreate(1); \
+                         alt_heapsem = OSSemCreate(1)
+#define ALT_OS_STOP()    OSRunning = OS_FALSE
+#define ALT_OS_INT_ENTER OSIntEnter
+#define ALT_OS_INT_EXIT  OSIntExit
+
+#endif /* ALT_ASM_SRC */
+
+/* These macros are used by the VIC funnel assembly code */
+#define ALT_OS_INT_ENTER_ASM    call OSIntEnter
+#define ALT_OS_INT_EXIT_ASM     call OSIntExit
+
+#endif /* __ALT_HOOKS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h
new file mode 100644
index 0000000..a554b8c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os/alt_sem.h
@@ -0,0 +1,85 @@
+#ifndef __ALT_SEM_H__
+#define __ALT_SEM_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This header provides macro definitions that can be used to create and use
+ * semaphores. These macros can be used in both a uC/OS-II based environment,
+ * and a single threaded HAL based environment.
+ *
+ * The motivation for these macros is to allow code to be developed which is
+ * thread safe under uC/OS-II, but incurs no additional overhead when used in a
+ * single threaded HAL environment.  
+ *
+ * In the case of a single threaded HAL environment, they compile to 
+ * "do nothing" directives, which ensures they do not contribute to the final
+ * executable. The macro definitions used in that case are supplied with the
+ * HAL.
+ *
+ * The following macros are available:
+ *
+ * ALT_SEM        - Create a semaphore instance.
+ * ALT_EXTERN_SEM - Create a reference to an external semaphore instance.
+ * ALT_STATIC_SEM - Create a static semaphore instance.
+ * ALT_SEM_CREATE - Initialise a semaphore.
+ * ALT_SEM_PEND   - Pend on a semaphore.
+ * ALT_SEM_POST   - Increment a semaphore.
+ *
+ * Input arguments and return codes are all consistant with the equivalent
+ * uC/OS-II function.
+ *
+ * It's important to be careful in the use of the macros: ALT_SEM, 
+ * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is
+ * included in the macro definition; so, for example, you should use:
+ *
+ * ALT_SEM(mysem)
+ *
+ * not:
+ *
+ * ALT_SEM(mysem);
+ *
+ * The inclusion of the semi-colon has been necessary to ensure the macros can
+ * compile with no warnings when used in a single threaded HAL environment.
+ *
+ */ 
+
+#include "priv/alt_sem_ucosii.h"
+
+#define ALT_SEM(sem) OS_EVENT* sem;
+#define ALT_EXTERN_SEM(sem) extern OS_EVENT* sem;
+#define ALT_STATIC_SEM(sem) static OS_EVENT* sem;
+
+#define ALT_SEM_CREATE(sem, value) alt_sem_create (sem, value)
+#define ALT_SEM_PEND(sem, timeout) alt_sem_pend (sem, timeout)
+#define ALT_SEM_POST(sem) OSSemPost (sem)
+
+#endif /* __ALT_SEM_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h
new file mode 100644
index 0000000..8feb1af
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/os_cfg.h
@@ -0,0 +1,65 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                  uC/OS-II Configuration File for V2.8x
+*
+*                               (c) Copyright 2005-2007, Micrium, Weston, FL
+*                                          All Rights Reserved
+*
+*
+* File    : OS_CFG.H
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micrim to properly license
+* its use in your product. We provide ALL the source code for your convenience and to help you experience
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef OS_CFG_H
+#define OS_CFG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#ifndef __ASSEMBLER__ 
+#include "sys/alt_alarm.h"
+#endif /* __ASSEMBLER__ */
+
+
+/*
+ * The following uC/OS configuration options have not been defined as
+ * configuration options in Nios II IDE or BSP tools; therefore they are
+ * defined here rather than in the generated system.h content. As long
+ * as they appear here, you may change their values in this file to change
+ * the setting
+ */
+                                       /* ---------------------- MISCELLANEOUS ----------------------- */
+#define OS_APP_HOOKS_EN           1    /* Application-defined hooks are called from the uC/OS-II hooks */
+#define OS_EVENT_MULTI_EN         1    /* Include code for OSEventPendMulti()                          */
+
+                                       /* -------------------- MESSAGE MAILBOXES --------------------- */
+#define OS_MBOX_PEND_ABORT_EN     1    /*     Include code for OSMboxPendAbort()                       */
+
+                                       /* ---------------------- MESSAGE QUEUES ---------------------- */
+#define OS_Q_PEND_ABORT_EN        1    /*     Include code for OSQPendAbort()                          */
+
+                                       /* ------------------------ SEMAPHORES ------------------------ */
+#define OS_SEM_PEND_ABORT_EN      1    /*    Include code for OSSemPendAbort()                         */
+
+                                                                                                                     
+#include "system.h"
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __OS_CFG_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h
new file mode 100644
index 0000000..e65a73f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_flag_ucosii.h
@@ -0,0 +1,109 @@
+#ifndef __ALT_FLAG_UCOSII_H__
+#define __ALT_FLAG_UCOSII_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file provides the uC/OS-II specific functions used to implement the 
+ * macros in alt_flag.h. These functions are simply wrappers for the uc/OS-II
+ * flags API.
+ *
+ * These functions are considered to be part of the internal implementation of
+ * the HAL, and should not be called directly by application code or device
+ * drivers. They are not guaranteed to be preserved in future versions of the
+ * HAL.
+ */
+
+#include "includes.h"
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_flag_create() is a wrapper for OSFlagCreate(), with the error code 
+ * converted into the functions return value.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, 
+               OS_FLAGS flags)
+{
+  INT8U err;
+  *pgroup = OSFlagCreate (flags, &err);
+  return err;
+}
+
+/*
+ * alt_flag_pend() is a wrapper for OSFlagPend(), with the error code 
+ * converted into the functions return value.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_pend (OS_FLAG_GRP* group, 
+                   OS_FLAGS flags, 
+                   INT8U wait_type, 
+                   INT16U timeout)
+{
+  INT8U err;
+  if (OSRunning)
+  {
+    OSFlagPend (group, flags, wait_type, timeout, &err);
+    return err;
+  }
+  return OS_ERR_PEND_ISR;
+}
+
+
+/*
+ * alt_flag_post() is a wrapper for OSFlagPost(), with the error code 
+ * converted into the functions return value.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_post (OS_FLAG_GRP* group, 
+                   OS_FLAGS     flags, 
+                   INT8U        opt)
+{
+  INT8U err;
+
+  if (OSRunning)
+  {
+    OSFlagPost (group, flags, opt, &err);
+    return err;
+  }
+  return OS_ERR_PEND_ISR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_FLAG_UCOSII_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h
new file mode 100644
index 0000000..7c383bb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/priv/alt_sem_ucosii.h
@@ -0,0 +1,82 @@
+#ifndef __ALT_SEM_UCOSII_H__
+#define __ALT_SEM_UCOSII_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * This file provides the uC/OS-II specific functions used to implement the 
+ * macros in alt_sem.h. These functions are simply wrappers for the uc/OS-II
+ * semaphore API.
+ *
+ * These functions are considered to be part of the internal implementation of
+ * the HAL, and should not be called directly by application code or device
+ * drivers. They are not guaranteed to be preserved in future versions of the
+ * HAL. 
+ */
+
+#include "includes.h"
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * alt_sem_create() is a wrapper for OSSemCreate(). The return value is 0 if 
+ * the semaphore has been successfully created, or non-zero otherwise.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, 
+              INT16U value)
+{
+  *sem = OSSemCreate (value);
+  return *sem ? 0 : -1;
+} 
+
+/*
+ * alt_sem_pend() is a wrapper for OSSemPend(), with the error code 
+ * converted into the functions return value.
+ */
+
+static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, 
+                  INT16U timeout)
+{
+  INT8U err;
+  OSSemPend (sem, timeout, &err);
+  return err;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_SEM_UCOSII_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h b/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h
new file mode 100644
index 0000000..62d1ca3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/inc/ucos_ii.h
@@ -0,0 +1,1930 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : uCOS_II.H
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micrim to properly license
+* its use in your product. We provide ALL the source code for your convenience and to help you experience
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef   OS_uCOS_II_H
+#define   OS_uCOS_II_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+*********************************************************************************************************
+*                                          uC/OS-II VERSION NUMBER
+*********************************************************************************************************
+*/
+
+#define  OS_VERSION                 286u                /* Version of uC/OS-II (Vx.yy mult. by 100)    */
+
+/*
+*********************************************************************************************************
+*                                           INCLUDE HEADER FILES
+*********************************************************************************************************
+*/
+
+// #include <app_cfg.h>
+#include <os_cfg.h>
+#include <os_cpu.h>
+
+/*
+*********************************************************************************************************
+*                                             MISCELLANEOUS
+*********************************************************************************************************
+*/
+
+#ifdef   OS_GLOBALS
+#define  OS_EXT
+#else
+#define  OS_EXT  extern
+#endif
+
+#ifndef  OS_FALSE
+#define  OS_FALSE                     0u
+#endif
+
+#ifndef  OS_TRUE
+#define  OS_TRUE                      1u
+#endif
+
+#define  OS_ASCII_NUL          (INT8U)0
+
+#define  OS_PRIO_SELF              0xFFu                /* Indicate SELF priority                      */
+
+#if OS_TASK_STAT_EN > 0
+#define  OS_N_SYS_TASKS               2u                /* Number of system tasks                      */
+#else
+#define  OS_N_SYS_TASKS               1u
+#endif
+
+#define  OS_TASK_STAT_PRIO  (OS_LOWEST_PRIO - 1)        /* Statistic task priority                     */
+#define  OS_TASK_IDLE_PRIO  (OS_LOWEST_PRIO)            /* IDLE      task priority                     */
+
+#if OS_LOWEST_PRIO <= 63
+#define  OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 8 + 1)   /* Size of event table                         */
+#define  OS_RDY_TBL_SIZE   ((OS_LOWEST_PRIO) / 8 + 1)   /* Size of ready table                         */
+#else
+#define  OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 16 + 1)  /* Size of event table                         */
+#define  OS_RDY_TBL_SIZE   ((OS_LOWEST_PRIO) / 16 + 1)  /* Size of ready table                         */
+#endif
+
+#define  OS_TASK_IDLE_ID          65535u                /* ID numbers for Idle, Stat and Timer tasks   */
+#define  OS_TASK_STAT_ID          65534u
+#define  OS_TASK_TMR_ID           65533u
+
+#define  OS_EVENT_EN           (((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) || (OS_SEM_EN > 0) || (OS_MUTEX_EN > 0))
+
+#define  OS_TCB_RESERVED        ((OS_TCB *)1)
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                              TASK STATUS (Bit definition for OSTCBStat)
+*********************************************************************************************************
+*/
+#define  OS_STAT_RDY               0x00u    /* Ready to run                                            */
+#define  OS_STAT_SEM               0x01u    /* Pending on semaphore                                    */
+#define  OS_STAT_MBOX              0x02u    /* Pending on mailbox                                      */
+#define  OS_STAT_Q                 0x04u    /* Pending on queue                                        */
+#define  OS_STAT_SUSPEND           0x08u    /* Task is suspended                                       */
+#define  OS_STAT_MUTEX             0x10u    /* Pending on mutual exclusion semaphore                   */
+#define  OS_STAT_FLAG              0x20u    /* Pending on event flag group                             */
+#define  OS_STAT_MULTI             0x80u    /* Pending on multiple events                              */
+
+#define  OS_STAT_PEND_ANY         (OS_STAT_SEM | OS_STAT_MBOX | OS_STAT_Q | OS_STAT_MUTEX | OS_STAT_FLAG)
+
+/*
+*********************************************************************************************************
+*                           TASK PEND STATUS (Status codes for OSTCBStatPend)
+*********************************************************************************************************
+*/
+#define  OS_STAT_PEND_OK              0u    /* Pending status OK, not pending, or pending complete     */
+#define  OS_STAT_PEND_TO              1u    /* Pending timed out                                       */
+#define  OS_STAT_PEND_ABORT           2u    /* Pending aborted                                         */
+
+/*
+*********************************************************************************************************
+*                                        OS_EVENT types
+*********************************************************************************************************
+*/
+#define  OS_EVENT_TYPE_UNUSED         0u
+#define  OS_EVENT_TYPE_MBOX           1u
+#define  OS_EVENT_TYPE_Q              2u
+#define  OS_EVENT_TYPE_SEM            3u
+#define  OS_EVENT_TYPE_MUTEX          4u
+#define  OS_EVENT_TYPE_FLAG           5u
+
+#define  OS_TMR_TYPE                100u    /* Used to identify Timers ...                             */
+                                            /* ... (Must be different value than OS_EVENT_TYPE_xxx)    */
+
+/*
+*********************************************************************************************************
+*                                         EVENT FLAGS
+*********************************************************************************************************
+*/
+#define  OS_FLAG_WAIT_CLR_ALL         0u    /* Wait for ALL    the bits specified to be CLR (i.e. 0)   */
+#define  OS_FLAG_WAIT_CLR_AND         0u
+
+#define  OS_FLAG_WAIT_CLR_ANY         1u    /* Wait for ANY of the bits specified to be CLR (i.e. 0)   */
+#define  OS_FLAG_WAIT_CLR_OR          1u
+
+#define  OS_FLAG_WAIT_SET_ALL         2u    /* Wait for ALL    the bits specified to be SET (i.e. 1)   */
+#define  OS_FLAG_WAIT_SET_AND         2u
+
+#define  OS_FLAG_WAIT_SET_ANY         3u    /* Wait for ANY of the bits specified to be SET (i.e. 1)   */
+#define  OS_FLAG_WAIT_SET_OR          3u
+
+
+#define  OS_FLAG_CONSUME           0x80u    /* Consume the flags if condition(s) satisfied             */
+
+
+#define  OS_FLAG_CLR                  0u
+#define  OS_FLAG_SET                  1u
+
+/*
+*********************************************************************************************************
+*                                   Values for OSTickStepState
+*
+* Note(s): This feature is used by uC/OS-View.
+*********************************************************************************************************
+*/
+
+#if OS_TICK_STEP_EN > 0
+#define  OS_TICK_STEP_DIS             0u    /* Stepping is disabled, tick runs as mormal               */
+#define  OS_TICK_STEP_WAIT            1u    /* Waiting for uC/OS-View to set OSTickStepState to _ONCE  */
+#define  OS_TICK_STEP_ONCE            2u    /* Process tick once and wait for next cmd from uC/OS-View */
+#endif
+
+/*
+*********************************************************************************************************
+*       Possible values for 'opt' argument of OSSemDel(), OSMboxDel(), OSQDel() and OSMutexDel()
+*********************************************************************************************************
+*/
+#define  OS_DEL_NO_PEND               0u
+#define  OS_DEL_ALWAYS                1u
+
+/*
+*********************************************************************************************************
+*                                        OS???Pend() OPTIONS
+*
+* These #defines are used to establish the options for OS???PendAbort().
+*********************************************************************************************************
+*/
+#define  OS_PEND_OPT_NONE             0u    /* NO option selected                                      */
+#define  OS_PEND_OPT_BROADCAST        1u    /* Broadcast action to ALL tasks waiting                   */
+
+/*
+*********************************************************************************************************
+*                                     OS???PostOpt() OPTIONS
+*
+* These #defines are used to establish the options for OSMboxPostOpt() and OSQPostOpt().
+*********************************************************************************************************
+*/
+#define  OS_POST_OPT_NONE          0x00u    /* NO option selected                                      */
+#define  OS_POST_OPT_BROADCAST     0x01u    /* Broadcast message to ALL tasks waiting                  */
+#define  OS_POST_OPT_FRONT         0x02u    /* Post to highest priority task waiting                   */
+#define  OS_POST_OPT_NO_SCHED      0x04u    /* Do not call the scheduler if this option is selected    */
+
+/*
+*********************************************************************************************************
+*                                 TASK OPTIONS (see OSTaskCreateExt())
+*********************************************************************************************************
+*/
+#define  OS_TASK_OPT_NONE        0x0000u    /* NO option selected                                      */
+#define  OS_TASK_OPT_STK_CHK     0x0001u    /* Enable stack checking for the task                      */
+#define  OS_TASK_OPT_STK_CLR     0x0002u    /* Clear the stack when the task is create                 */
+#define  OS_TASK_OPT_SAVE_FP     0x0004u    /* Save the contents of any floating-point registers       */
+
+/*
+*********************************************************************************************************
+*                            TIMER OPTIONS (see OSTmrStart() and OSTmrStop())
+*********************************************************************************************************
+*/
+#define  OS_TMR_OPT_NONE              0u    /* No option selected                                      */
+
+#define  OS_TMR_OPT_ONE_SHOT          1u    /* Timer will not automatically restart when it expires    */
+#define  OS_TMR_OPT_PERIODIC          2u    /* Timer will     automatically restart when it expires    */
+
+#define  OS_TMR_OPT_CALLBACK          3u    /* OSTmrStop() option to call 'callback' w/ timer arg.     */
+#define  OS_TMR_OPT_CALLBACK_ARG      4u    /* OSTmrStop() option to call 'callback' w/ new   arg.     */
+
+/*
+*********************************************************************************************************
+*                                            TIMER STATES
+*********************************************************************************************************
+*/
+#define  OS_TMR_STATE_UNUSED          0u
+#define  OS_TMR_STATE_STOPPED         1u
+#define  OS_TMR_STATE_COMPLETED       2u
+#define  OS_TMR_STATE_RUNNING         3u
+
+/*
+*********************************************************************************************************
+*                                             ERROR CODES
+*********************************************************************************************************
+*/
+#define OS_ERR_NONE                   0u
+
+#define OS_ERR_EVENT_TYPE             1u
+#define OS_ERR_PEND_ISR               2u
+#define OS_ERR_POST_NULL_PTR          3u
+#define OS_ERR_PEVENT_NULL            4u
+#define OS_ERR_POST_ISR               5u
+#define OS_ERR_QUERY_ISR              6u
+#define OS_ERR_INVALID_OPT            7u
+#define OS_ERR_PDATA_NULL             9u
+
+#define OS_ERR_TIMEOUT               10u
+#define OS_ERR_EVENT_NAME_TOO_LONG   11u
+#define OS_ERR_PNAME_NULL            12u
+#define OS_ERR_PEND_LOCKED           13u
+#define OS_ERR_PEND_ABORT            14u
+#define OS_ERR_DEL_ISR               15u
+#define OS_ERR_CREATE_ISR            16u
+#define OS_ERR_NAME_GET_ISR          17u
+#define OS_ERR_NAME_SET_ISR          18u
+
+#define OS_ERR_MBOX_FULL             20u
+
+#define OS_ERR_Q_FULL                30u
+#define OS_ERR_Q_EMPTY               31u
+
+#define OS_ERR_PRIO_EXIST            40u
+#define OS_ERR_PRIO                  41u
+#define OS_ERR_PRIO_INVALID          42u
+
+#define OS_ERR_SEM_OVF               50u
+
+#define OS_ERR_TASK_CREATE_ISR       60u
+#define OS_ERR_TASK_DEL              61u
+#define OS_ERR_TASK_DEL_IDLE         62u
+#define OS_ERR_TASK_DEL_REQ          63u
+#define OS_ERR_TASK_DEL_ISR          64u
+#define OS_ERR_TASK_NAME_TOO_LONG    65u
+#define OS_ERR_TASK_NO_MORE_TCB      66u
+#define OS_ERR_TASK_NOT_EXIST        67u
+#define OS_ERR_TASK_NOT_SUSPENDED    68u
+#define OS_ERR_TASK_OPT              69u
+#define OS_ERR_TASK_RESUME_PRIO      70u
+#define OS_ERR_TASK_SUSPEND_IDLE     71u
+#define OS_ERR_TASK_SUSPEND_PRIO     72u
+#define OS_ERR_TASK_WAITING          73u
+
+#define OS_ERR_TIME_NOT_DLY          80u
+#define OS_ERR_TIME_INVALID_MINUTES  81u
+#define OS_ERR_TIME_INVALID_SECONDS  82u
+#define OS_ERR_TIME_INVALID_MS       83u
+#define OS_ERR_TIME_ZERO_DLY         84u
+#define OS_ERR_TIME_DLY_ISR          85u
+
+#define OS_ERR_MEM_INVALID_PART      90u
+#define OS_ERR_MEM_INVALID_BLKS      91u
+#define OS_ERR_MEM_INVALID_SIZE      92u
+#define OS_ERR_MEM_NO_FREE_BLKS      93u
+#define OS_ERR_MEM_FULL              94u
+#define OS_ERR_MEM_INVALID_PBLK      95u
+#define OS_ERR_MEM_INVALID_PMEM      96u
+#define OS_ERR_MEM_INVALID_PDATA     97u
+#define OS_ERR_MEM_INVALID_ADDR      98u
+#define OS_ERR_MEM_NAME_TOO_LONG     99u
+
+#define OS_ERR_NOT_MUTEX_OWNER      100u
+
+#define OS_ERR_FLAG_INVALID_PGRP    110u
+#define OS_ERR_FLAG_WAIT_TYPE       111u
+#define OS_ERR_FLAG_NOT_RDY         112u
+#define OS_ERR_FLAG_INVALID_OPT     113u
+#define OS_ERR_FLAG_GRP_DEPLETED    114u
+#define OS_ERR_FLAG_NAME_TOO_LONG   115u
+
+#define OS_ERR_PIP_LOWER            120u
+
+#define OS_ERR_TMR_INVALID_DLY      130u
+#define OS_ERR_TMR_INVALID_PERIOD   131u
+#define OS_ERR_TMR_INVALID_OPT      132u
+#define OS_ERR_TMR_INVALID_NAME     133u
+#define OS_ERR_TMR_NON_AVAIL        134u
+#define OS_ERR_TMR_INACTIVE         135u
+#define OS_ERR_TMR_INVALID_DEST     136u
+#define OS_ERR_TMR_INVALID_TYPE     137u
+#define OS_ERR_TMR_INVALID          138u
+#define OS_ERR_TMR_ISR              139u
+#define OS_ERR_TMR_NAME_TOO_LONG    140u
+#define OS_ERR_TMR_INVALID_STATE    141u
+#define OS_ERR_TMR_STOPPED          142u
+#define OS_ERR_TMR_NO_CALLBACK      143u
+
+/*
+*********************************************************************************************************
+*                                    OLD ERROR CODE NAMES (< V2.84)
+*********************************************************************************************************
+*/
+#define OS_NO_ERR                    OS_ERR_NONE
+#define OS_TIMEOUT                   OS_ERR_TIMEOUT
+#define OS_TASK_NOT_EXIST            OS_ERR_TASK_NOT_EXIST
+#define OS_MBOX_FULL                 OS_ERR_MBOX_FULL
+#define OS_Q_FULL                    OS_ERR_Q_FULL
+#define OS_Q_EMPTY                   OS_ERR_Q_EMPTY
+#define OS_PRIO_EXIST                OS_ERR_PRIO_EXIST
+#define OS_PRIO_ERR                  OS_ERR_PRIO
+#define OS_PRIO_INVALID              OS_ERR_PRIO_INVALID
+#define OS_SEM_OVF                   OS_ERR_SEM_OVF
+#define OS_TASK_DEL_ERR              OS_ERR_TASK_DEL
+#define OS_TASK_DEL_IDLE             OS_ERR_TASK_DEL_IDLE
+#define OS_TASK_DEL_REQ              OS_ERR_TASK_DEL_REQ
+#define OS_TASK_DEL_ISR              OS_ERR_TASK_DEL_ISR
+#define OS_NO_MORE_TCB               OS_ERR_TASK_NO_MORE_TCB
+#define OS_TIME_NOT_DLY              OS_ERR_TIME_NOT_DLY
+#define OS_TIME_INVALID_MINUTES      OS_ERR_TIME_INVALID_MINUTES
+#define OS_TIME_INVALID_SECONDS      OS_ERR_TIME_INVALID_SECONDS
+#define OS_TIME_INVALID_MS           OS_ERR_TIME_INVALID_MS
+#define OS_TIME_ZERO_DLY             OS_ERR_TIME_ZERO_DLY
+#define OS_TASK_SUSPEND_PRIO         OS_ERR_TASK_SUSPEND_PRIO
+#define OS_TASK_SUSPEND_IDLE         OS_ERR_TASK_SUSPEND_IDLE
+#define OS_TASK_RESUME_PRIO          OS_ERR_TASK_RESUME_PRIO
+#define OS_TASK_NOT_SUSPENDED        OS_ERR_TASK_NOT_SUSPENDED
+#define OS_MEM_INVALID_PART          OS_ERR_MEM_INVALID_PART
+#define OS_MEM_INVALID_BLKS          OS_ERR_MEM_INVALID_BLKS
+#define OS_MEM_INVALID_SIZE          OS_ERR_MEM_INVALID_SIZE
+#define OS_MEM_NO_FREE_BLKS          OS_ERR_MEM_NO_FREE_BLKS
+#define OS_MEM_FULL                  OS_ERR_MEM_FULL
+#define OS_MEM_INVALID_PBLK          OS_ERR_MEM_INVALID_PBLK
+#define OS_MEM_INVALID_PMEM          OS_ERR_MEM_INVALID_PMEM
+#define OS_MEM_INVALID_PDATA         OS_ERR_MEM_INVALID_PDATA
+#define OS_MEM_INVALID_ADDR          OS_ERR_MEM_INVALID_ADDR
+#define OS_MEM_NAME_TOO_LONG         OS_ERR_MEM_NAME_TOO_LONG
+#define OS_TASK_OPT_ERR              OS_ERR_TASK_OPT
+#define OS_FLAG_INVALID_PGRP         OS_ERR_FLAG_INVALID_PGRP
+#define OS_FLAG_ERR_WAIT_TYPE        OS_ERR_FLAG_WAIT_TYPE
+#define OS_FLAG_ERR_NOT_RDY          OS_ERR_FLAG_NOT_RDY
+#define OS_FLAG_INVALID_OPT          OS_ERR_FLAG_INVALID_OPT
+#define OS_FLAG_GRP_DEPLETED         OS_ERR_FLAG_GRP_DEPLETED
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          EVENT CONTROL BLOCK
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0)
+typedef struct os_event {
+    INT8U    OSEventType;                    /* Type of event control block (see OS_EVENT_TYPE_xxxx)    */
+    void    *OSEventPtr;                     /* Pointer to message or queue structure                   */
+    INT16U   OSEventCnt;                     /* Semaphore Count (not used if other EVENT type)          */
+#if OS_LOWEST_PRIO <= 63
+    INT8U    OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+    INT8U    OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+#else
+    INT16U   OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+    INT16U   OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+#endif
+
+#if OS_EVENT_NAME_SIZE > 1
+    INT8U    OSEventName[OS_EVENT_NAME_SIZE];
+#endif
+} OS_EVENT;
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       EVENT FLAGS CONTROL BLOCK
+*********************************************************************************************************
+*/
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+
+#if OS_FLAGS_NBITS == 8                     /* Determine the size of OS_FLAGS (8, 16 or 32 bits)       */
+typedef  INT8U    OS_FLAGS;
+#endif
+
+#if OS_FLAGS_NBITS == 16
+typedef  INT16U   OS_FLAGS;
+#endif
+
+#if OS_FLAGS_NBITS == 32
+typedef  INT32U   OS_FLAGS;
+#endif
+
+
+typedef struct os_flag_grp {                /* Event Flag Group                                        */
+    INT8U         OSFlagType;               /* Should be set to OS_EVENT_TYPE_FLAG                     */
+    void         *OSFlagWaitList;           /* Pointer to first NODE of task waiting on event flag     */
+    OS_FLAGS      OSFlagFlags;              /* 8, 16 or 32 bit flags                                   */
+#if OS_FLAG_NAME_SIZE > 1
+    INT8U         OSFlagName[OS_FLAG_NAME_SIZE];
+#endif
+} OS_FLAG_GRP;
+
+
+
+typedef struct os_flag_node {               /* Event Flag Wait List Node                               */
+    void         *OSFlagNodeNext;           /* Pointer to next     NODE in wait list                   */
+    void         *OSFlagNodePrev;           /* Pointer to previous NODE in wait list                   */
+    void         *OSFlagNodeTCB;            /* Pointer to TCB of waiting task                          */
+    void         *OSFlagNodeFlagGrp;        /* Pointer to Event Flag Group                             */
+    OS_FLAGS      OSFlagNodeFlags;          /* Event flag to wait on                                   */
+    INT8U         OSFlagNodeWaitType;       /* Type of wait:                                           */
+                                            /*      OS_FLAG_WAIT_AND                                   */
+                                            /*      OS_FLAG_WAIT_ALL                                   */
+                                            /*      OS_FLAG_WAIT_OR                                    */
+                                            /*      OS_FLAG_WAIT_ANY                                   */
+} OS_FLAG_NODE;
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          MESSAGE MAILBOX DATA
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_EN > 0
+typedef struct os_mbox_data {
+    void   *OSMsg;                         /* Pointer to message in mailbox                            */
+#if OS_LOWEST_PRIO <= 63
+    INT8U   OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur                 */
+    INT8U   OSEventGrp;                    /* Group corresponding to tasks waiting for event to occur  */
+#else
+    INT16U  OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur                 */
+    INT16U  OSEventGrp;                    /* Group corresponding to tasks waiting for event to occur  */
+#endif
+} OS_MBOX_DATA;
+#endif
+
+/*
+*********************************************************************************************************
+*                                     MEMORY PARTITION DATA STRUCTURES
+*********************************************************************************************************
+*/
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+typedef struct os_mem {                   /* MEMORY CONTROL BLOCK                                      */
+    void   *OSMemAddr;                    /* Pointer to beginning of memory partition                  */
+    void   *OSMemFreeList;                /* Pointer to list of free memory blocks                     */
+    INT32U  OSMemBlkSize;                 /* Size (in bytes) of each block of memory                   */
+    INT32U  OSMemNBlks;                   /* Total number of blocks in this partition                  */
+    INT32U  OSMemNFree;                   /* Number of memory blocks remaining in this partition       */
+#if OS_MEM_NAME_SIZE > 1
+    INT8U   OSMemName[OS_MEM_NAME_SIZE];  /* Memory partition name                                     */
+#endif
+} OS_MEM;
+
+
+typedef struct os_mem_data {
+    void   *OSAddr;                    /* Pointer to the beginning address of the memory partition     */
+    void   *OSFreeList;                /* Pointer to the beginning of the free list of memory blocks   */
+    INT32U  OSBlkSize;                 /* Size (in bytes) of each memory block                         */
+    INT32U  OSNBlks;                   /* Total number of blocks in the partition                      */
+    INT32U  OSNFree;                   /* Number of memory blocks free                                 */
+    INT32U  OSNUsed;                   /* Number of memory blocks used                                 */
+} OS_MEM_DATA;
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                    MUTUAL EXCLUSION SEMAPHORE DATA
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_EN > 0
+typedef struct os_mutex_data {
+#if OS_LOWEST_PRIO <= 63
+    INT8U   OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+    INT8U   OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+#else
+    INT16U  OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+    INT16U  OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+#endif
+    BOOLEAN OSValue;                        /* Mutex value (OS_FALSE = used, OS_TRUE = available)      */
+    INT8U   OSOwnerPrio;                    /* Mutex owner's task priority or 0xFF if no owner         */
+    INT8U   OSMutexPIP;                     /* Priority Inheritance Priority or 0xFF if no owner       */
+} OS_MUTEX_DATA;
+#endif
+
+/*
+*********************************************************************************************************
+*                                          MESSAGE QUEUE DATA
+*********************************************************************************************************
+*/
+
+#if OS_Q_EN > 0
+typedef struct os_q {                   /* QUEUE CONTROL BLOCK                                         */
+    struct os_q   *OSQPtr;              /* Link to next queue control block in list of free blocks     */
+    void         **OSQStart;            /* Pointer to start of queue data                              */
+    void         **OSQEnd;              /* Pointer to end   of queue data                              */
+    void         **OSQIn;               /* Pointer to where next message will be inserted  in   the Q  */
+    void         **OSQOut;              /* Pointer to where next message will be extracted from the Q  */
+    INT16U         OSQSize;             /* Size of queue (maximum number of entries)                   */
+    INT16U         OSQEntries;          /* Current number of entries in the queue                      */
+} OS_Q;
+
+
+typedef struct os_q_data {
+    void          *OSMsg;               /* Pointer to next message to be extracted from queue          */
+    INT16U         OSNMsgs;             /* Number of messages in message queue                         */
+    INT16U         OSQSize;             /* Size of message queue                                       */
+#if OS_LOWEST_PRIO <= 63
+    INT8U          OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur         */
+    INT8U          OSEventGrp;          /* Group corresponding to tasks waiting for event to occur     */
+#else
+    INT16U         OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur         */
+    INT16U         OSEventGrp;          /* Group corresponding to tasks waiting for event to occur     */
+#endif
+} OS_Q_DATA;
+#endif
+
+/*
+*********************************************************************************************************
+*                                           SEMAPHORE DATA
+*********************************************************************************************************
+*/
+
+#if OS_SEM_EN > 0
+typedef struct os_sem_data {
+    INT16U  OSCnt;                          /* Semaphore count                                         */
+#if OS_LOWEST_PRIO <= 63
+    INT8U   OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+    INT8U   OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+#else
+    INT16U  OSEventTbl[OS_EVENT_TBL_SIZE];  /* List of tasks waiting for event to occur                */
+    INT16U  OSEventGrp;                     /* Group corresponding to tasks waiting for event to occur */
+#endif
+} OS_SEM_DATA;
+#endif
+
+/*
+*********************************************************************************************************
+*                                            TASK STACK DATA
+*********************************************************************************************************
+*/
+
+#if OS_TASK_CREATE_EXT_EN > 0
+typedef struct os_stk_data {
+    INT32U  OSFree;                    /* Number of free bytes on the stack                            */
+    INT32U  OSUsed;                    /* Number of bytes used on the stack                            */
+} OS_STK_DATA;
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          TASK CONTROL BLOCK
+*********************************************************************************************************
+*/
+
+typedef struct os_tcb {
+    OS_STK          *OSTCBStkPtr;           /* Pointer to current top of stack                         */
+
+#if OS_TASK_CREATE_EXT_EN > 0
+    void            *OSTCBExtPtr;           /* Pointer to user definable data for TCB extension        */
+    OS_STK          *OSTCBStkBottom;        /* Pointer to bottom of stack                              */
+    INT32U           OSTCBStkSize;          /* Size of task stack (in number of stack elements)        */
+    INT16U           OSTCBOpt;              /* Task options as passed by OSTaskCreateExt()             */
+    INT16U           OSTCBId;               /* Task ID (0..65535)                                      */
+#endif
+
+    struct os_tcb   *OSTCBNext;             /* Pointer to next     TCB in the TCB list                 */
+    struct os_tcb   *OSTCBPrev;             /* Pointer to previous TCB in the TCB list                 */
+
+#if (OS_EVENT_EN) || (OS_FLAG_EN > 0)
+    OS_EVENT        *OSTCBEventPtr;         /* Pointer to          event control block                 */
+#endif
+
+#if (OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)
+    OS_EVENT       **OSTCBEventMultiPtr;    /* Pointer to multiple event control blocks                */
+#endif
+
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0)
+    void            *OSTCBMsg;              /* Message received from OSMboxPost() or OSQPost()         */
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+#if OS_TASK_DEL_EN > 0
+    OS_FLAG_NODE    *OSTCBFlagNode;         /* Pointer to event flag node                              */
+#endif
+    OS_FLAGS         OSTCBFlagsRdy;         /* Event flags that made task ready to run                 */
+#endif
+
+    INT16U           OSTCBDly;              /* Nbr ticks to delay task or, timeout waiting for event   */
+    INT8U            OSTCBStat;             /* Task      status                                        */
+    INT8U            OSTCBStatPend;         /* Task PEND status                                        */
+    INT8U            OSTCBPrio;             /* Task priority (0 == highest)                            */
+
+    INT8U            OSTCBX;                /* Bit position in group  corresponding to task priority   */
+    INT8U            OSTCBY;                /* Index into ready table corresponding to task priority   */
+#if OS_LOWEST_PRIO <= 63
+    INT8U            OSTCBBitX;             /* Bit mask to access bit position in ready table          */
+    INT8U            OSTCBBitY;             /* Bit mask to access bit position in ready group          */
+#else
+    INT16U           OSTCBBitX;             /* Bit mask to access bit position in ready table          */
+    INT16U           OSTCBBitY;             /* Bit mask to access bit position in ready group          */
+#endif
+
+#if OS_TASK_DEL_EN > 0
+    INT8U            OSTCBDelReq;           /* Indicates whether a task needs to delete itself         */
+#endif
+
+#if OS_TASK_PROFILE_EN > 0
+    INT32U           OSTCBCtxSwCtr;         /* Number of time the task was switched in                 */
+    INT32U           OSTCBCyclesTot;        /* Total number of clock cycles the task has been running  */
+    INT32U           OSTCBCyclesStart;      /* Snapshot of cycle counter at start of task resumption   */
+    OS_STK          *OSTCBStkBase;          /* Pointer to the beginning of the task stack              */
+    INT32U           OSTCBStkUsed;          /* Number of bytes used from the stack                     */
+#endif
+
+#if OS_TASK_NAME_SIZE > 1
+    INT8U            OSTCBTaskName[OS_TASK_NAME_SIZE];
+#endif
+} OS_TCB;
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                   TIMER DATA TYPES
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+typedef  void (*OS_TMR_CALLBACK)(void *ptmr, void *parg);
+
+
+
+typedef  struct  os_tmr {
+    INT8U            OSTmrType;                       /* Should be set to OS_TMR_TYPE                                  */
+    OS_TMR_CALLBACK  OSTmrCallback;                   /* Function to call when timer expires                           */
+    void            *OSTmrCallbackArg;                /* Argument to pass to function when timer expires               */
+    void            *OSTmrNext;                       /* Double link list pointers                                     */
+    void            *OSTmrPrev;
+    INT32U           OSTmrMatch;                      /* Timer expires when OSTmrTime == OSTmrMatch                    */
+    INT32U           OSTmrDly;                        /* Delay time before periodic update starts                      */
+    INT32U           OSTmrPeriod;                     /* Period to repeat timer                                        */
+#if OS_TMR_CFG_NAME_SIZE > 0
+    INT8U            OSTmrName[OS_TMR_CFG_NAME_SIZE]; /* Name to give the timer                                        */
+#endif
+    INT8U            OSTmrOpt;                        /* Options (see OS_TMR_OPT_xxx)                                  */
+    INT8U            OSTmrState;                      /* Indicates the state of the timer:                             */
+                                                      /*     OS_TMR_STATE_UNUSED                                       */
+                                                      /*     OS_TMR_STATE_RUNNING                                      */
+                                                      /*     OS_TMR_STATE_STOPPED                                      */
+} OS_TMR;
+
+
+
+typedef  struct  os_tmr_wheel {
+    OS_TMR          *OSTmrFirst;                      /* Pointer to first timer in linked list                         */
+    INT16U           OSTmrEntries;
+} OS_TMR_WHEEL;
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+OS_EXT  INT32U            OSCtxSwCtr;               /* Counter of number of context switches           */
+
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0)
+OS_EXT  OS_EVENT         *OSEventFreeList;          /* Pointer to list of free EVENT control blocks    */
+OS_EXT  OS_EVENT          OSEventTbl[OS_MAX_EVENTS];/* Table of EVENT control blocks                   */
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+OS_EXT  OS_FLAG_GRP       OSFlagTbl[OS_MAX_FLAGS];  /* Table containing event flag groups              */
+OS_EXT  OS_FLAG_GRP      *OSFlagFreeList;           /* Pointer to free list of event flag groups       */
+#endif
+
+#if OS_TASK_STAT_EN > 0
+OS_EXT  INT8U             OSCPUUsage;               /* Percentage of CPU used                          */
+OS_EXT  INT32U            OSIdleCtrMax;             /* Max. value that idle ctr can take in 1 sec.     */
+OS_EXT  INT32U            OSIdleCtrRun;             /* Val. reached by idle ctr at run time in 1 sec.  */
+OS_EXT  BOOLEAN           OSStatRdy;                /* Flag indicating that the statistic task is rdy  */
+OS_EXT  OS_STK            OSTaskStatStk[OS_TASK_STAT_STK_SIZE];      /* Statistics task stack          */
+#endif
+
+OS_EXT  INT8U             OSIntNesting;             /* Interrupt nesting level                         */
+
+OS_EXT  INT8U             OSLockNesting;            /* Multitasking lock nesting level                 */
+
+OS_EXT  INT8U             OSPrioCur;                /* Priority of current task                        */
+OS_EXT  INT8U             OSPrioHighRdy;            /* Priority of highest priority task               */
+
+#if OS_LOWEST_PRIO <= 63
+OS_EXT  INT8U             OSRdyGrp;                        /* Ready list group                         */
+OS_EXT  INT8U             OSRdyTbl[OS_RDY_TBL_SIZE];       /* Table of tasks which are ready to run    */
+#else
+OS_EXT  INT16U            OSRdyGrp;                        /* Ready list group                         */
+OS_EXT  INT16U            OSRdyTbl[OS_RDY_TBL_SIZE];       /* Table of tasks which are ready to run    */
+#endif
+
+OS_EXT  BOOLEAN           OSRunning;                       /* Flag indicating that kernel is running   */
+
+OS_EXT  INT8U             OSTaskCtr;                       /* Number of tasks created                  */
+
+OS_EXT  volatile  INT32U  OSIdleCtr;                                 /* Idle counter                   */
+
+OS_EXT  OS_STK            OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE];      /* Idle task stack                */
+
+
+OS_EXT  OS_TCB           *OSTCBCur;                        /* Pointer to currently running TCB         */
+OS_EXT  OS_TCB           *OSTCBFreeList;                   /* Pointer to list of free TCBs             */
+OS_EXT  OS_TCB           *OSTCBHighRdy;                    /* Pointer to highest priority TCB R-to-R   */
+OS_EXT  OS_TCB           *OSTCBList;                       /* Pointer to doubly linked list of TCBs    */
+OS_EXT  OS_TCB           *OSTCBPrioTbl[OS_LOWEST_PRIO + 1];/* Table of pointers to created TCBs        */
+OS_EXT  OS_TCB            OSTCBTbl[OS_MAX_TASKS + OS_N_SYS_TASKS];   /* Table of TCBs                  */
+
+#if OS_TICK_STEP_EN > 0
+OS_EXT  INT8U             OSTickStepState;          /* Indicates the state of the tick step feature    */
+#endif
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+OS_EXT  OS_MEM           *OSMemFreeList;            /* Pointer to free list of memory partitions       */
+OS_EXT  OS_MEM            OSMemTbl[OS_MAX_MEM_PART];/* Storage for memory partition manager            */
+#endif
+
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+OS_EXT  OS_Q             *OSQFreeList;              /* Pointer to list of free QUEUE control blocks    */
+OS_EXT  OS_Q              OSQTbl[OS_MAX_QS];        /* Table of QUEUE control blocks                   */
+#endif
+
+#if OS_TIME_GET_SET_EN > 0
+OS_EXT  volatile  INT32U  OSTime;                   /* Current value of system time (in ticks)         */
+#endif
+
+#if OS_TMR_EN > 0
+OS_EXT  INT16U            OSTmrFree;                /* Number of free entries in the timer pool        */
+OS_EXT  INT16U            OSTmrUsed;                /* Number of timers used                           */
+OS_EXT  INT32U            OSTmrTime;                /* Current timer time                              */
+
+OS_EXT  OS_EVENT         *OSTmrSem;                 /* Sem. used to gain exclusive access to timers    */
+OS_EXT  OS_EVENT         *OSTmrSemSignal;           /* Sem. used to signal the update of timers        */
+
+OS_EXT  OS_TMR            OSTmrTbl[OS_TMR_CFG_MAX]; /* Table containing pool of timers                 */
+OS_EXT  OS_TMR           *OSTmrFreeList;            /* Pointer to free list of timers                  */
+OS_EXT  OS_STK            OSTmrTaskStk[OS_TASK_TMR_STK_SIZE];
+
+OS_EXT  OS_TMR_WHEEL      OSTmrWheelTbl[OS_TMR_CFG_WHEEL_SIZE];
+#endif
+
+extern  INT8U   const     OSUnMapTbl[256];          /* Priority->Index    lookup table                 */
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          FUNCTION PROTOTYPES
+*                                     (Target Independent Functions)
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            MISCELLANEOUS
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN)
+
+#if (OS_EVENT_NAME_SIZE > 1)
+INT8U         OSEventNameGet          (OS_EVENT        *pevent,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+
+void          OSEventNameSet          (OS_EVENT        *pevent,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+#endif
+
+#if (OS_EVENT_MULTI_EN > 0)
+INT16U        OSEventPendMulti        (OS_EVENT       **pevents_pend,
+                                       OS_EVENT       **pevents_rdy,
+                                       void           **pmsgs_rdy,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+#endif
+
+#endif
+
+/*
+*********************************************************************************************************
+*                                         EVENT FLAGS MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+
+#if OS_FLAG_ACCEPT_EN > 0
+OS_FLAGS      OSFlagAccept            (OS_FLAG_GRP     *pgrp,
+                                       OS_FLAGS         flags,
+                                       INT8U            wait_type,
+                                       INT8U           *perr);
+#endif
+
+OS_FLAG_GRP  *OSFlagCreate            (OS_FLAGS         flags,
+                                      INT8U            *perr);
+
+#if OS_FLAG_DEL_EN > 0
+OS_FLAG_GRP  *OSFlagDel               (OS_FLAG_GRP     *pgrp,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_FLAG_NAME_SIZE > 1)
+INT8U         OSFlagNameGet           (OS_FLAG_GRP     *pgrp,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+
+void          OSFlagNameSet           (OS_FLAG_GRP     *pgrp,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+#endif
+
+OS_FLAGS      OSFlagPend              (OS_FLAG_GRP     *pgrp,
+                                       OS_FLAGS         flags,
+                                       INT8U            wait_type,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+
+OS_FLAGS      OSFlagPendGetFlagsRdy   (void);
+OS_FLAGS      OSFlagPost              (OS_FLAG_GRP     *pgrp,
+                                       OS_FLAGS         flags,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+
+#if OS_FLAG_QUERY_EN > 0
+OS_FLAGS      OSFlagQuery             (OS_FLAG_GRP     *pgrp,
+                                       INT8U           *perr);
+#endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                        MESSAGE MAILBOX MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_EN > 0
+
+#if OS_MBOX_ACCEPT_EN > 0
+void         *OSMboxAccept            (OS_EVENT        *pevent);
+#endif
+
+OS_EVENT     *OSMboxCreate            (void            *pmsg);
+
+#if OS_MBOX_DEL_EN > 0
+OS_EVENT     *OSMboxDel               (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+void         *OSMboxPend              (OS_EVENT        *pevent,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+
+#if OS_MBOX_PEND_ABORT_EN > 0
+INT8U         OSMboxPendAbort         (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+#if OS_MBOX_POST_EN > 0
+INT8U         OSMboxPost              (OS_EVENT        *pevent,
+                                       void            *pmsg);
+#endif
+
+#if OS_MBOX_POST_OPT_EN > 0
+INT8U         OSMboxPostOpt           (OS_EVENT        *pevent,
+                                       void            *pmsg,
+                                       INT8U            opt);
+#endif
+
+#if OS_MBOX_QUERY_EN > 0
+INT8U         OSMboxQuery             (OS_EVENT        *pevent,
+                                       OS_MBOX_DATA    *p_mbox_data);
+#endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                           MEMORY MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+
+OS_MEM       *OSMemCreate             (void            *addr,
+                                       INT32U           nblks,
+                                       INT32U           blksize,
+                                       INT8U           *perr);
+
+void         *OSMemGet                (OS_MEM          *pmem,
+                                       INT8U           *perr);
+#if OS_MEM_NAME_SIZE > 1
+INT8U         OSMemNameGet            (OS_MEM          *pmem,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+
+void          OSMemNameSet            (OS_MEM          *pmem,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+#endif
+INT8U         OSMemPut                (OS_MEM          *pmem,
+                                       void            *pblk);
+
+#if OS_MEM_QUERY_EN > 0
+INT8U         OSMemQuery              (OS_MEM          *pmem,
+                                       OS_MEM_DATA     *p_mem_data);
+#endif
+
+#endif
+
+/*
+*********************************************************************************************************
+*                                MUTUAL EXCLUSION SEMAPHORE MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_EN > 0
+
+#if OS_MUTEX_ACCEPT_EN > 0
+BOOLEAN       OSMutexAccept           (OS_EVENT        *pevent,
+                                       INT8U           *perr);
+#endif
+
+OS_EVENT     *OSMutexCreate           (INT8U            prio,
+                                       INT8U           *perr);
+
+#if OS_MUTEX_DEL_EN > 0
+OS_EVENT     *OSMutexDel              (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+void          OSMutexPend             (OS_EVENT        *pevent,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+
+INT8U         OSMutexPost             (OS_EVENT        *pevent);
+
+#if OS_MUTEX_QUERY_EN > 0
+INT8U         OSMutexQuery            (OS_EVENT        *pevent,
+                                       OS_MUTEX_DATA   *p_mutex_data);
+#endif
+
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         MESSAGE QUEUE MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+
+#if OS_Q_ACCEPT_EN > 0
+void         *OSQAccept               (OS_EVENT        *pevent,
+                                       INT8U           *perr);
+#endif
+
+OS_EVENT     *OSQCreate               (void           **start,
+                                       INT16U           size);
+
+#if OS_Q_DEL_EN > 0
+OS_EVENT     *OSQDel                  (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+#if OS_Q_FLUSH_EN > 0
+INT8U         OSQFlush                (OS_EVENT        *pevent);
+#endif
+
+void         *OSQPend                 (OS_EVENT        *pevent,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+
+#if OS_Q_PEND_ABORT_EN > 0
+INT8U         OSQPendAbort            (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+#if OS_Q_POST_EN > 0
+INT8U         OSQPost                 (OS_EVENT        *pevent,
+                                       void            *pmsg);
+#endif
+
+#if OS_Q_POST_FRONT_EN > 0
+INT8U         OSQPostFront            (OS_EVENT        *pevent,
+                                       void            *pmsg);
+#endif
+
+#if OS_Q_POST_OPT_EN > 0
+INT8U         OSQPostOpt              (OS_EVENT        *pevent,
+                                       void            *pmsg,
+                                       INT8U            opt);
+#endif
+
+#if OS_Q_QUERY_EN > 0
+INT8U         OSQQuery                (OS_EVENT        *pevent,
+                                       OS_Q_DATA       *p_q_data);
+#endif
+
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          SEMAPHORE MANAGEMENT
+*********************************************************************************************************
+*/
+#if OS_SEM_EN > 0
+
+#if OS_SEM_ACCEPT_EN > 0
+INT16U        OSSemAccept             (OS_EVENT        *pevent);
+#endif
+
+OS_EVENT     *OSSemCreate             (INT16U           cnt);
+
+#if OS_SEM_DEL_EN > 0
+OS_EVENT     *OSSemDel                (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+void          OSSemPend               (OS_EVENT        *pevent,
+                                       INT16U           timeout,
+                                       INT8U           *perr);
+
+#if OS_SEM_PEND_ABORT_EN > 0
+INT8U         OSSemPendAbort          (OS_EVENT        *pevent,
+                                       INT8U            opt,
+                                       INT8U           *perr);
+#endif
+
+INT8U         OSSemPost               (OS_EVENT        *pevent);
+
+#if OS_SEM_QUERY_EN > 0
+INT8U         OSSemQuery              (OS_EVENT        *pevent,
+                                       OS_SEM_DATA     *p_sem_data);
+#endif
+
+#if OS_SEM_SET_EN > 0
+void          OSSemSet                (OS_EVENT        *pevent,
+                                       INT16U           cnt,
+                                       INT8U           *perr);
+#endif
+
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            TASK MANAGEMENT
+*********************************************************************************************************
+*/
+#if OS_TASK_CHANGE_PRIO_EN > 0
+INT8U         OSTaskChangePrio        (INT8U            oldprio,
+                                       INT8U            newprio);
+#endif
+
+#if OS_TASK_CREATE_EN > 0
+INT8U         OSTaskCreate            (void           (*task)(void *p_arg),
+                                       void            *p_arg,
+                                       OS_STK          *ptos,
+                                       INT8U            prio);
+#endif
+
+#if OS_TASK_CREATE_EXT_EN > 0
+INT8U         OSTaskCreateExt         (void           (*task)(void *p_arg),
+                                       void            *p_arg,
+                                       OS_STK          *ptos,
+                                       INT8U            prio,
+                                       INT16U           id,
+                                       OS_STK          *pbos,
+                                       INT32U           stk_size,
+                                       void            *pext,
+                                       INT16U           opt);
+#endif
+
+#if OS_TASK_DEL_EN > 0
+INT8U         OSTaskDel               (INT8U            prio);
+INT8U         OSTaskDelReq            (INT8U            prio);
+#endif
+
+#if OS_TASK_NAME_SIZE > 1
+INT8U         OSTaskNameGet           (INT8U            prio,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+
+void          OSTaskNameSet           (INT8U            prio,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+#endif
+
+#if OS_TASK_SUSPEND_EN > 0
+INT8U         OSTaskResume            (INT8U            prio);
+INT8U         OSTaskSuspend           (INT8U            prio);
+#endif
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+INT8U         OSTaskStkChk            (INT8U            prio,
+                                       OS_STK_DATA     *p_stk_data);
+#endif
+
+#if OS_TASK_QUERY_EN > 0
+INT8U         OSTaskQuery             (INT8U            prio,
+                                       OS_TCB          *p_task_data);
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            TIME MANAGEMENT
+*********************************************************************************************************
+*/
+
+void          OSTimeDly               (INT16U           ticks);
+
+#if OS_TIME_DLY_HMSM_EN > 0
+INT8U         OSTimeDlyHMSM           (INT8U            hours,
+                                       INT8U            minutes,
+                                       INT8U            seconds,
+                                       INT16U           milli);
+#endif
+
+#if OS_TIME_DLY_RESUME_EN > 0
+INT8U         OSTimeDlyResume         (INT8U            prio);
+#endif
+
+#if OS_TIME_GET_SET_EN > 0
+INT32U        OSTimeGet               (void);
+void          OSTimeSet               (INT32U           ticks);
+#endif
+
+void          OSTimeTick              (void);
+
+/*
+*********************************************************************************************************
+*                                            TIMER MANAGEMENT
+*********************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+OS_TMR      *OSTmrCreate              (INT32U           dly,
+                                       INT32U           period,
+                                       INT8U            opt,
+                                       OS_TMR_CALLBACK  callback,
+                                       void            *callback_arg,
+                                       INT8U           *pname,
+                                       INT8U           *perr);
+
+BOOLEAN      OSTmrDel                 (OS_TMR          *ptmr,
+                                       INT8U           *perr);
+
+#if OS_TMR_CFG_NAME_SIZE > 0
+INT8U        OSTmrNameGet             (OS_TMR          *ptmr,
+                                       INT8U           *pdest,
+                                       INT8U           *perr);
+#endif
+INT32U       OSTmrRemainGet           (OS_TMR          *ptmr,
+                                       INT8U           *perr);
+
+INT8U        OSTmrStateGet            (OS_TMR          *ptmr,
+                                       INT8U           *perr);
+
+BOOLEAN      OSTmrStart               (OS_TMR          *ptmr,
+                                       INT8U           *perr);
+
+BOOLEAN      OSTmrStop                (OS_TMR          *ptmr,
+                                       INT8U            opt,
+                                       void            *callback_arg,
+                                       INT8U           *perr);
+
+INT8U        OSTmrSignal              (void);
+#endif
+
+/*
+*********************************************************************************************************
+*                                             MISCELLANEOUS
+*********************************************************************************************************
+*/
+
+void          OSInit                  (void);
+
+void          OSIntEnter              (void);
+void          OSIntExit               (void);
+
+#if OS_SCHED_LOCK_EN > 0
+void          OSSchedLock             (void);
+void          OSSchedUnlock           (void);
+#endif
+
+void          OSStart                 (void);
+
+void          OSStatInit              (void);
+
+INT16U        OSVersion               (void);
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      INTERNAL FUNCTION PROTOTYPES
+*                            (Your application MUST NOT call these functions)
+*********************************************************************************************************
+*/
+
+#if OS_TASK_DEL_EN > 0
+void          OS_Dummy                (void);
+#endif
+
+#if (OS_EVENT_EN)
+INT8U         OS_EventTaskRdy         (OS_EVENT        *pevent,
+                                       void            *pmsg,
+                                       INT8U            msk,
+                                       INT8U            pend_stat);
+
+void          OS_EventTaskWait        (OS_EVENT        *pevent);
+
+void          OS_EventTaskRemove      (OS_TCB          *ptcb,
+                                       OS_EVENT        *pevent);
+
+#if (OS_EVENT_MULTI_EN > 0)
+void          OS_EventTaskWaitMulti   (OS_EVENT       **pevents_wait);
+
+void          OS_EventTaskRemoveMulti (OS_TCB          *ptcb,
+                                       OS_EVENT       **pevents_multi);
+#endif
+
+void          OS_EventWaitListInit    (OS_EVENT        *pevent);
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+void          OS_FlagInit             (void);
+void          OS_FlagUnlink           (OS_FLAG_NODE    *pnode);
+#endif
+
+void          OS_MemClr               (INT8U           *pdest,
+                                       INT16U           size);
+
+void          OS_MemCopy              (INT8U           *pdest,
+                                       INT8U           *psrc,
+                                       INT16U           size);
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+void          OS_MemInit              (void);
+#endif
+
+#if OS_Q_EN > 0
+void          OS_QInit                (void);
+#endif
+
+void          OS_Sched                (void);
+
+#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1)
+INT8U         OS_StrCopy              (INT8U           *pdest,
+                                       INT8U           *psrc);
+
+INT8U         OS_StrLen               (INT8U           *psrc);
+#endif
+
+void          OS_TaskIdle             (void            *p_arg);
+
+#if OS_TASK_STAT_EN > 0
+void          OS_TaskStat             (void            *p_arg);
+#endif
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+void          OS_TaskStkClr           (OS_STK          *pbos,
+                                       INT32U           size,
+                                       INT16U           opt);
+#endif
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+void          OS_TaskStatStkChk       (void);
+#endif
+
+INT8U         OS_TCBInit              (INT8U            prio,
+                                       OS_STK          *ptos,
+                                       OS_STK          *pbos,
+                                       INT16U           id,
+                                       INT32U           stk_size,
+                                       void            *pext,
+                                       INT16U           opt);
+
+#if OS_TMR_EN > 0
+void          OSTmr_Init              (void);
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          FUNCTION PROTOTYPES
+*                                      (Target Specific Functions)
+*********************************************************************************************************
+*/
+
+#if OS_DEBUG_EN > 0
+void          OSDebugInit             (void);
+#endif
+
+void          OSInitHookBegin         (void);
+void          OSInitHookEnd           (void);
+
+void          OSTaskCreateHook        (OS_TCB          *ptcb);
+void          OSTaskDelHook           (OS_TCB          *ptcb);
+
+void          OSTaskIdleHook          (void);
+
+void          OSTaskStatHook          (void);
+OS_STK       *OSTaskStkInit           (void           (*task)(void *p_arg),
+                                       void            *p_arg,
+                                       OS_STK          *ptos,
+                                       INT16U           opt);
+
+#if OS_TASK_SW_HOOK_EN > 0
+void          OSTaskSwHook            (void);
+#endif
+
+void          OSTCBInitHook           (OS_TCB          *ptcb);
+
+#if OS_TIME_TICK_HOOK_EN > 0
+void          OSTimeTickHook          (void);
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          FUNCTION PROTOTYPES
+*                                   (Application Specific Functions)
+*********************************************************************************************************
+*/
+
+#if OS_APP_HOOKS_EN > 0
+void          App_TaskCreateHook      (OS_TCB          *ptcb);
+void          App_TaskDelHook         (OS_TCB          *ptcb);
+void          App_TaskIdleHook        (void);
+
+void          App_TaskStatHook        (void);
+
+#if OS_TASK_SW_HOOK_EN > 0
+void          App_TaskSwHook          (void);
+#endif
+
+void          App_TCBInitHook         (OS_TCB          *ptcb);
+
+#if OS_TIME_TICK_HOOK_EN > 0
+void          App_TimeTickHook        (void);
+#endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                          FUNCTION PROTOTYPES
+*
+* IMPORTANT: These prototypes MUST be placed in OS_CPU.H
+*********************************************************************************************************
+*/
+
+#if 0
+void          OSStartHighRdy          (void);
+void          OSIntCtxSw              (void);
+void          OSCtxSw                 (void);
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   LOOK FOR MISSING #define CONSTANTS
+*
+* This section is used to generate ERROR messages at compile time if certain #define constants are
+* MISSING in OS_CFG.H.  This allows you to quickly determine the source of the error.
+*
+* You SHOULD NOT change this section UNLESS you would like to add more comments as to the source of the
+* compile time error.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            EVENT FLAGS
+*********************************************************************************************************
+*/
+
+#ifndef OS_FLAG_EN
+#error  "OS_CFG.H, Missing OS_FLAG_EN: Enable (1) or Disable (0) code generation for Event Flags"
+#else
+    #ifndef OS_MAX_FLAGS
+    #error  "OS_CFG.H, Missing OS_MAX_FLAGS: Max. number of Event Flag Groups in your application"
+    #else
+        #if     OS_MAX_FLAGS > 65500u
+        #error  "OS_CFG.H, OS_MAX_FLAGS must be <= 65500"
+        #endif
+    #endif
+
+    #ifndef OS_FLAGS_NBITS
+    #error  "OS_CFG.H, Missing OS_FLAGS_NBITS: Determine #bits used for event flags, MUST be either 8, 16 or 32"
+    #endif
+
+    #ifndef OS_FLAG_WAIT_CLR_EN
+    #error  "OS_CFG.H, Missing OS_FLAG_WAIT_CLR_EN: Include code for Wait on Clear EVENT FLAGS"
+    #endif
+
+    #ifndef OS_FLAG_ACCEPT_EN
+    #error  "OS_CFG.H, Missing OS_FLAG_ACCEPT_EN: Include code for OSFlagAccept()"
+    #endif
+
+    #ifndef OS_FLAG_DEL_EN
+    #error  "OS_CFG.H, Missing OS_FLAG_DEL_EN: Include code for OSFlagDel()"
+    #endif
+
+    #ifndef OS_FLAG_NAME_SIZE
+    #error  "OS_CFG.H, Missing OS_FLAG_NAME_SIZE: Determines the size of flag group names"
+    #endif
+
+    #ifndef OS_FLAG_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_FLAG_QUERY_EN: Include code for OSFlagQuery()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                           MESSAGE MAILBOXES
+*********************************************************************************************************
+*/
+
+#ifndef OS_MBOX_EN
+#error  "OS_CFG.H, Missing OS_MBOX_EN: Enable (1) or Disable (0) code generation for MAILBOXES"
+#else
+    #ifndef OS_MBOX_ACCEPT_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_ACCEPT_EN: Include code for OSMboxAccept()"
+    #endif
+
+    #ifndef OS_MBOX_DEL_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_DEL_EN: Include code for OSMboxDel()"
+    #endif
+
+    #ifndef OS_MBOX_PEND_ABORT_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_PEND_ABORT_EN: Include code for OSMboxPendAbort()"
+    #endif
+
+    #ifndef OS_MBOX_POST_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_POST_EN: Include code for OSMboxPost()"
+    #endif
+
+    #ifndef OS_MBOX_POST_OPT_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_POST_OPT_EN: Include code for OSMboxPostOpt()"
+    #endif
+
+    #ifndef OS_MBOX_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_MBOX_QUERY_EN: Include code for OSMboxQuery()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                           MEMORY MANAGEMENT
+*********************************************************************************************************
+*/
+
+#ifndef OS_MEM_EN
+#error  "OS_CFG.H, Missing OS_MEM_EN: Enable (1) or Disable (0) code generation for MEMORY MANAGER"
+#else
+    #ifndef OS_MAX_MEM_PART
+    #error  "OS_CFG.H, Missing OS_MAX_MEM_PART: Max. number of memory partitions"
+    #else
+        #if     OS_MAX_MEM_PART > 65500u
+        #error  "OS_CFG.H, OS_MAX_MEM_PART must be <= 65500"
+        #endif
+    #endif
+
+    #ifndef OS_MEM_NAME_SIZE
+    #error  "OS_CFG.H, Missing OS_MEM_NAME_SIZE: Determines the size of memory partition names"
+    #endif
+
+    #ifndef OS_MEM_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_MEM_QUERY_EN: Include code for OSMemQuery()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                       MUTUAL EXCLUSION SEMAPHORES
+*********************************************************************************************************
+*/
+
+#ifndef OS_MUTEX_EN
+#error  "OS_CFG.H, Missing OS_MUTEX_EN: Enable (1) or Disable (0) code generation for MUTEX"
+#else
+    #ifndef OS_MUTEX_ACCEPT_EN
+    #error  "OS_CFG.H, Missing OS_MUTEX_ACCEPT_EN: Include code for OSMutexAccept()"
+    #endif
+
+    #ifndef OS_MUTEX_DEL_EN
+    #error  "OS_CFG.H, Missing OS_MUTEX_DEL_EN: Include code for OSMutexDel()"
+    #endif
+
+    #ifndef OS_MUTEX_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_MUTEX_QUERY_EN: Include code for OSMutexQuery()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                              MESSAGE QUEUES
+*********************************************************************************************************
+*/
+
+#ifndef OS_Q_EN
+#error  "OS_CFG.H, Missing OS_Q_EN: Enable (1) or Disable (0) code generation for QUEUES"
+#else
+    #ifndef OS_MAX_QS
+    #error  "OS_CFG.H, Missing OS_MAX_QS: Max. number of queue control blocks"
+    #else
+        #if     OS_MAX_QS > 65500u
+        #error  "OS_CFG.H, OS_MAX_QS must be <= 65500"
+        #endif
+    #endif
+
+    #ifndef OS_Q_ACCEPT_EN
+    #error  "OS_CFG.H, Missing OS_Q_ACCEPT_EN: Include code for OSQAccept()"
+    #endif
+
+    #ifndef OS_Q_DEL_EN
+    #error  "OS_CFG.H, Missing OS_Q_DEL_EN: Include code for OSQDel()"
+    #endif
+
+    #ifndef OS_Q_FLUSH_EN
+    #error  "OS_CFG.H, Missing OS_Q_FLUSH_EN: Include code for OSQFlush()"
+    #endif
+
+    #ifndef OS_Q_PEND_ABORT_EN
+    #error  "OS_CFG.H, Missing OS_Q_PEND_ABORT_EN: Include code for OSQPendAbort()"
+    #endif
+
+    #ifndef OS_Q_POST_EN
+    #error  "OS_CFG.H, Missing OS_Q_POST_EN: Include code for OSQPost()"
+    #endif
+
+    #ifndef OS_Q_POST_FRONT_EN
+    #error  "OS_CFG.H, Missing OS_Q_POST_FRONT_EN: Include code for OSQPostFront()"
+    #endif
+
+    #ifndef OS_Q_POST_OPT_EN
+    #error  "OS_CFG.H, Missing OS_Q_POST_OPT_EN: Include code for OSQPostOpt()"
+    #endif
+
+    #ifndef OS_Q_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_Q_QUERY_EN: Include code for OSQQuery()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                              SEMAPHORES
+*********************************************************************************************************
+*/
+
+#ifndef OS_SEM_EN
+#error  "OS_CFG.H, Missing OS_SEM_EN: Enable (1) or Disable (0) code generation for SEMAPHORES"
+#else
+    #ifndef OS_SEM_ACCEPT_EN
+    #error  "OS_CFG.H, Missing OS_SEM_ACCEPT_EN: Include code for OSSemAccept()"
+    #endif
+
+    #ifndef OS_SEM_DEL_EN
+    #error  "OS_CFG.H, Missing OS_SEM_DEL_EN: Include code for OSSemDel()"
+    #endif
+
+    #ifndef OS_SEM_PEND_ABORT_EN
+    #error  "OS_CFG.H, Missing OS_SEM_PEND_ABORT_EN: Include code for OSSemPendAbort()"
+    #endif
+
+    #ifndef OS_SEM_QUERY_EN
+    #error  "OS_CFG.H, Missing OS_SEM_QUERY_EN: Include code for OSSemQuery()"
+    #endif
+
+    #ifndef OS_SEM_SET_EN
+    #error  "OS_CFG.H, Missing OS_SEM_SET_EN: Include code for OSSemSet()"
+    #endif
+#endif
+
+/*
+*********************************************************************************************************
+*                                             TASK MANAGEMENT
+*********************************************************************************************************
+*/
+
+#ifndef OS_MAX_TASKS
+#error  "OS_CFG.H, Missing OS_MAX_TASKS: Max. number of tasks in your application"
+#else
+    #if     OS_MAX_TASKS < 2
+    #error  "OS_CFG.H,         OS_MAX_TASKS must be >= 2"
+    #endif
+
+    #if     OS_MAX_TASKS >  ((OS_LOWEST_PRIO - OS_N_SYS_TASKS) + 1)
+    #error  "OS_CFG.H,         OS_MAX_TASKS must be <= OS_LOWEST_PRIO - OS_N_SYS_TASKS + 1"
+    #endif
+
+#endif
+
+#if     OS_LOWEST_PRIO >  254
+#error  "OS_CFG.H,         OS_LOWEST_PRIO must be <= 254 in V2.8x and higher"
+#endif
+
+#ifndef OS_TASK_IDLE_STK_SIZE
+#error  "OS_CFG.H, Missing OS_TASK_IDLE_STK_SIZE: Idle task stack size"
+#endif
+
+#ifndef OS_TASK_STAT_EN
+#error  "OS_CFG.H, Missing OS_TASK_STAT_EN: Enable (1) or Disable(0) the statistics task"
+#endif
+
+#ifndef OS_TASK_STAT_STK_SIZE
+#error  "OS_CFG.H, Missing OS_TASK_STAT_STK_SIZE: Statistics task stack size"
+#endif
+
+#ifndef OS_TASK_STAT_STK_CHK_EN
+#error  "OS_CFG.H, Missing OS_TASK_STAT_STK_CHK_EN: Check task stacks from statistics task"
+#endif
+
+#ifndef OS_TASK_CHANGE_PRIO_EN
+#error  "OS_CFG.H, Missing OS_TASK_CHANGE_PRIO_EN: Include code for OSTaskChangePrio()"
+#endif
+
+#ifndef OS_TASK_CREATE_EN
+#error  "OS_CFG.H, Missing OS_TASK_CREATE_EN: Include code for OSTaskCreate()"
+#endif
+
+#ifndef OS_TASK_CREATE_EXT_EN
+#error  "OS_CFG.H, Missing OS_TASK_CREATE_EXT_EN: Include code for OSTaskCreateExt()"
+#endif
+
+#ifndef OS_TASK_DEL_EN
+#error  "OS_CFG.H, Missing OS_TASK_DEL_EN: Include code for OSTaskDel()"
+#endif
+
+#ifndef OS_TASK_NAME_SIZE
+#error  "OS_CFG.H, Missing OS_TASK_NAME_SIZE: Determine the size of task names"
+#endif
+
+#ifndef OS_TASK_SUSPEND_EN
+#error  "OS_CFG.H, Missing OS_TASK_SUSPEND_EN: Include code for OSTaskSuspend() and OSTaskResume()"
+#endif
+
+#ifndef OS_TASK_QUERY_EN
+#error  "OS_CFG.H, Missing OS_TASK_QUERY_EN: Include code for OSTaskQuery()"
+#endif
+
+/*
+*********************************************************************************************************
+*                                             TIME MANAGEMENT
+*********************************************************************************************************
+*/
+
+#ifndef OS_TICKS_PER_SEC
+#error  "OS_CFG.H, Missing OS_TICKS_PER_SEC: Sets the number of ticks in one second"
+#endif
+
+#ifndef OS_TIME_DLY_HMSM_EN
+#error  "OS_CFG.H, Missing OS_TIME_DLY_HMSM_EN: Include code for OSTimeDlyHMSM()"
+#endif
+
+#ifndef OS_TIME_DLY_RESUME_EN
+#error  "OS_CFG.H, Missing OS_TIME_DLY_RESUME_EN: Include code for OSTimeDlyResume()"
+#endif
+
+#ifndef OS_TIME_GET_SET_EN
+#error  "OS_CFG.H, Missing OS_TIME_GET_SET_EN: Include code for OSTimeGet() and OSTimeSet()"
+#endif
+
+/*
+*********************************************************************************************************
+*                                             TIMER MANAGEMENT
+*********************************************************************************************************
+*/
+
+#ifndef OS_TMR_EN
+#error  "OS_CFG.H, Missing OS_TMR_EN: When (1) enables code generation for Timer Management"
+#elif   OS_TMR_EN > 0
+    #if     OS_SEM_EN == 0
+    #error  "OS_CFG.H, Semaphore management is required (set OS_SEM_EN to 1) when enabling Timer Management."
+    #error  "          Timer management require TWO semaphores."
+    #endif
+
+    #ifndef OS_TMR_CFG_MAX
+    #error  "OS_CFG.H, Missing OS_TMR_CFG_MAX: Determines the total number of timers in an application (2 .. 65500)"
+    #else
+        #if OS_TMR_CFG_MAX < 2
+        #error  "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500"
+        #endif
+
+        #if OS_TMR_CFG_MAX > 65500
+        #error  "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500"
+        #endif
+    #endif
+
+    #ifndef OS_TMR_CFG_WHEEL_SIZE
+    #error  "OS_CFG.H, Missing OS_TMR_CFG_WHEEL_SIZE: Sets the size of the timer wheel (1 .. 1023)"
+    #else
+        #if OS_TMR_CFG_WHEEL_SIZE < 2
+        #error  "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024"
+        #endif
+
+        #if OS_TMR_CFG_WHEEL_SIZE > 1024
+        #error  "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024"
+        #endif
+    #endif
+
+    #ifndef OS_TMR_CFG_NAME_SIZE
+    #error  "OS_CFG.H, Missing OS_TMR_CFG_NAME_SIZE: Determines the number of characters used for Timer names"
+    #endif
+
+    #ifndef OS_TMR_CFG_TICKS_PER_SEC
+    #error  "OS_CFG.H, Missing OS_TMR_CFG_TICKS_PER_SEC: Determines the rate at which tiem timer management task will run (Hz)"
+    #endif
+
+    #ifndef OS_TASK_TMR_STK_SIZE
+    #error  "OS_CFG.H, Missing OS_TASK_TMR_STK_SIZE: Determines the size of the Timer Task's stack"
+    #endif
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                            MISCELLANEOUS
+*********************************************************************************************************
+*/
+
+#ifndef OS_ARG_CHK_EN
+#error  "OS_CFG.H, Missing OS_ARG_CHK_EN: Enable (1) or Disable (0) argument checking"
+#endif
+
+
+#ifndef OS_CPU_HOOKS_EN
+#error  "OS_CFG.H, Missing OS_CPU_HOOKS_EN: uC/OS-II hooks are found in the processor port files when 1"
+#endif
+
+
+#ifndef OS_APP_HOOKS_EN
+#error  "OS_CFG.H, Missing OS_APP_HOOKS_EN: Application-defined hooks are called from the uC/OS-II hooks"
+#endif
+
+
+#ifndef OS_DEBUG_EN
+#error  "OS_CFG.H, Missing OS_DEBUG_EN: Allows you to include variables for debugging or not"
+#endif
+
+
+#ifndef OS_LOWEST_PRIO
+#error  "OS_CFG.H, Missing OS_LOWEST_PRIO: Defines the lowest priority that can be assigned"
+#endif
+
+
+#ifndef OS_MAX_EVENTS
+#error  "OS_CFG.H, Missing OS_MAX_EVENTS: Max. number of event control blocks in your application"
+#else
+    #if     OS_MAX_EVENTS > 65500u
+    #error  "OS_CFG.H, OS_MAX_EVENTS must be <= 65500"
+    #endif
+#endif
+
+
+#ifndef OS_SCHED_LOCK_EN
+#error  "OS_CFG.H, Missing OS_SCHED_LOCK_EN: Include code for OSSchedLock() and OSSchedUnlock()"
+#endif
+
+
+#ifndef OS_EVENT_MULTI_EN
+#error  "OS_CFG.H, Missing OS_EVENT_MULTI_EN: Include code for OSEventPendMulti()"
+#endif
+
+
+#ifndef OS_TASK_PROFILE_EN
+#error  "OS_CFG.H, Missing OS_TASK_PROFILE_EN: Include data structure for run-time task profiling"
+#endif
+
+
+#ifndef OS_TASK_SW_HOOK_EN
+#error  "OS_CFG.H, Missing OS_TASK_SW_HOOK_EN: Allows you to include the code for OSTaskSwHook() or not"
+#endif
+
+
+#ifndef OS_TICK_STEP_EN
+#error  "OS_CFG.H, Missing OS_TICK_STEP_EN: Allows to 'step' one tick at a time with uC/OS-View"
+#endif
+
+
+#ifndef OS_TIME_TICK_HOOK_EN
+#error  "OS_CFG.H, Missing OS_TIME_TICK_HOOK_EN: Allows you to include the code for OSTimeTickHook() or not"
+#endif
+
+/*
+*********************************************************************************************************
+*                                         SAFETY CRITICAL USE
+*********************************************************************************************************
+*/
+
+#ifdef SAFETY_CRITICAL_RELEASE
+
+#if    OS_ARG_CHK_EN < 1
+#error "OS_CFG.H, OS_ARG_CHK_EN must be enabled for safety-critical release code"
+#endif
+
+#if    OS_APP_HOOKS_EN > 0
+#error "OS_CFG.H, OS_APP_HOOKS_EN must be disabled for safety-critical release code"
+#endif
+
+#if    OS_DEBUG_EN > 0
+#error "OS_CFG.H, OS_DEBUG_EN must be disabled for safety-critical release code"
+#endif
+
+#ifdef CANTATA
+#error "OS_CFG.H, CANTATA must be disabled for safety-critical release code"
+#endif
+
+#ifdef OS_SCHED_LOCK_EN
+#error "OS_CFG.H, OS_SCHED_LOCK_EN must be disabled for safety-critical release code"
+#endif
+
+#ifdef VSC_VALIDATION_MODE
+#error "OS_CFG.H, VSC_VALIDATION_MODE must be disabled for safety-critical release code"
+#endif
+
+#if    OS_TASK_STAT_EN > 0
+#error "OS_CFG.H, OS_TASK_STAT_EN must be disabled for safety-critical release code"
+#endif
+
+#if    OS_TICK_STEP_EN > 0
+#error "OS_CFG.H, OS_TICK_STEP_EN must be disabled for safety-critical release code"
+#endif
+
+#if    OS_FLAG_EN > 0
+    #if    OS_FLAG_DEL_EN > 0
+    #error "OS_CFG.H, OS_FLAG_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_MBOX_EN > 0
+    #if    OS_MBOX_DEL_EN > 0
+    #error "OS_CFG.H, OS_MBOX_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_MUTEX_EN > 0
+    #if    OS_MUTEX_DEL_EN > 0
+    #error "OS_CFG.H, OS_MUTEX_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_Q_EN > 0
+    #if    OS_Q_DEL_EN > 0
+    #error "OS_CFG.H, OS_Q_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_SEM_EN > 0
+    #if    OS_SEM_DEL_EN > 0
+    #error "OS_CFG.H, OS_SEM_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_TASK_EN > 0
+    #if    OS_TASK_DEL_EN > 0
+    #error "OS_CFG.H, OS_TASK_DEL_EN must be disabled for safety-critical release code"
+    #endif
+#endif
+
+#if    OS_CRITICAL_METHOD != 3
+#error "OS_CPU.H, OS_CRITICAL_METHOD must be type 3 for safety-critical release code"
+#endif
+
+#endif  /* ------------------------ SAFETY_CRITICAL_RELEASE ------------------------ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt b/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt
new file mode 100644
index 0000000..3872d99
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/license-ucosii.txt
@@ -0,0 +1,20 @@
+MicroC/OS-II Licensing Terms
+============================
+
+Micrium's uC/OS-II is a real-time operating system (RTOS) available in source code.  
+This is not open-source software. 
+
+This RTOS can be used free of charge for non-commercial purposes and academic projects only, 
+any other use of the code is subject to the terms of an end-user license agreement 
+for more information please see the license file included in the BSP project or contact Micrium.
+
+Anyone planning to use a Micrium RTOS in a commercial product must purchase a commercial license 
+from the owner of the software, Silicon Laboratories Inc.  
+
+Licensing information is available at:
+
+Phone: +1 954-217-2036
+Email: sales@micrium.com
+URL: www.micrium.com
+
+Do not use this code if you do not agree to these conditions.
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c
new file mode 100644
index 0000000..03ed46d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_env_lock.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * These are the env lock/unlock stubs required by newlib. These are 
+ * used to make accesses to environment variables thread safe. Note that 
+ * this implementation requires that environment variables are never manipulated 
+ * by an interrupt service routine.
+ */
+
+
+#include <reent.h>
+
+#include "includes.h"
+#include "system.h"
+
+/* semaphore to protect the environment */
+
+OS_EVENT *alt_envsem;
+
+#if OS_THREAD_SAFE_NEWLIB
+/* id of the task that is currently manipulating the environment */
+
+static int lockid = -1;
+
+/* number of times __env_lock has recursed */
+
+static int locks;
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+/*
+ *
+ */
+
+void __env_lock ( struct _reent *_r )
+{
+#if OS_THREAD_SAFE_NEWLIB
+  OS_TCB tcb;
+  OS_SEM_DATA semdata;
+  INT8U err;
+  int id;
+
+  /* use our priority as a task id */
+
+  err = OSTaskQuery( OS_PRIO_SELF, &tcb );
+  if (err != OS_NO_ERR)
+    return;
+
+  id = tcb.OSTCBPrio;
+   
+  /* see if we own the environment already */
+
+  OSSemQuery( alt_envsem, &semdata );
+  if( semdata.OSEventGrp && id == lockid ) 
+  {
+    /* we do; just count the recursion */
+
+    locks++;
+  }
+  else 
+  {
+    /* wait on the other task to yield, then claim ownership */
+
+    OSSemPend( alt_envsem, 0, &err );
+    locks  = 1;
+    lockid = id;
+  }
+
+#endif /* OS_THREAD_SAFE_NEWLIB */
+  return;
+}
+
+/*
+ *
+ */
+
+void __env_unlock ( struct _reent *_r )
+{
+#if OS_THREAD_SAFE_NEWLIB
+  if (locks == 0)
+    return;
+
+   /* 
+    * release the environment once the number of locks == the number 
+    * of unlocks 
+    */
+
+  if( (--locks) == 0 ) 
+  {
+    lockid = -1;
+    OSSemPost( alt_envsem );
+  }
+#endif /* OS_THREAD_SAFE_NEWLIB */
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c
new file mode 100644
index 0000000..0f050ca
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/alt_malloc_lock.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+
+/*
+ * These are the malloc lock/unlock stubs required by newlib. These are 
+ * used to make accesses to the heap thread safe. Note that 
+ * this implementation requires that the heap is never manipulated 
+ * by an interrupt service routine.
+ */
+
+#include <reent.h>
+
+#include "includes.h"
+
+/* semaphore to protect the heap */
+
+OS_EVENT *alt_heapsem;
+
+
+#if OS_THREAD_SAFE_NEWLIB
+/* id of the task that is currently manipulating the heap */
+
+static int lockid = -1;
+
+/* number of times __malloc_lock has recursed */
+
+static int locks;
+#endif /* OS_THREAD_SAFE_NEWLIB */
+
+/*
+ *
+ */
+
+void __malloc_lock ( struct _reent *_r )
+{
+#if OS_THREAD_SAFE_NEWLIB
+  OS_TCB tcb;
+  OS_SEM_DATA semdata;
+  INT8U err;
+  int id;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif  
+  
+  if (OSRunning != OS_TRUE)
+      return;
+
+  /* use our priority as a task id */
+
+  err = OSTaskQuery( OS_PRIO_SELF, &tcb );
+  if (err != OS_NO_ERR)
+    return;
+
+  id = tcb.OSTCBPrio;
+   
+  /* see if we own the heap already */
+
+  OSSemQuery( alt_heapsem, &semdata );
+  
+  OS_ENTER_CRITICAL();
+
+  if( !semdata.OSCnt && id == lockid ) 
+  {
+    /* we do; just count the recursion */
+    locks++;
+    OS_EXIT_CRITICAL();
+  }
+  else 
+  {
+    /* wait on the other task to yield the heap, then claim ownership of it */
+    OS_EXIT_CRITICAL();
+
+    OSSemPend( alt_heapsem, 0, &err );
+    locks  = 1;
+    lockid = id;
+  }
+
+#endif /* OS_THREAD_SAFE_NEWLIB */
+  return;
+}
+
+/*
+ *
+ */
+
+void __malloc_unlock ( struct _reent *_r )
+{
+#if OS_THREAD_SAFE_NEWLIB
+
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif 
+
+  if (OSRunning != OS_TRUE)
+      return;
+
+  OS_ENTER_CRITICAL();
+  if (locks == 0)
+  {
+      OS_EXIT_CRITICAL();
+      return;
+  }
+
+  /* release the heap once the number of locks == the number of unlocks */
+  if( (--locks) == 0 ) 
+  {
+    lockid = -1;
+    OS_EXIT_CRITICAL();
+    OSSemPost( alt_heapsem );
+  }
+  else
+  {
+      OS_EXIT_CRITICAL();
+  }
+  
+#endif /* OS_THREAD_SAFE_NEWLIB */
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c
new file mode 100644
index 0000000..8c88045
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_core.c
@@ -0,0 +1,2018 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                             CORE FUNCTIONS
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_CORE.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micri�m to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#define  OS_GLOBALS
+#include <ucos_ii.h>
+#endif
+
+/*
+*********************************************************************************************************
+*                                       PRIORITY RESOLUTION TABLE
+*
+* Note: Index into table is bit pattern to resolve highest priority
+*       Indexed value corresponds to highest priority bit position (i.e. 0..7)
+*********************************************************************************************************
+*/
+
+INT8U  const  OSUnMapTbl[256] = {
+    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x00 to 0x0F                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x10 to 0x1F                             */
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x20 to 0x2F                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x30 to 0x3F                             */
+    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x40 to 0x4F                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x50 to 0x5F                             */
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x60 to 0x6F                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x70 to 0x7F                             */
+    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x80 to 0x8F                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0x90 to 0x9F                             */
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0xA0 to 0xAF                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0xB0 to 0xBF                             */
+    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0xC0 to 0xCF                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0xD0 to 0xDF                             */
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,       /* 0xE0 to 0xEF                             */
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0        /* 0xF0 to 0xFF                             */
+};
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                       FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+static  void  OS_InitEventList(void);
+
+static  void  OS_InitMisc(void);
+
+static  void  OS_InitRdyList(void);
+
+static  void  OS_InitTaskIdle(void);
+
+#if OS_TASK_STAT_EN > 0
+static  void  OS_InitTaskStat(void);
+#endif
+
+static  void  OS_InitTCBList(void);
+
+static  void  OS_SchedNew(void);
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                         GET THE NAME OF A SEMAPHORE, MUTEX, MAILBOX or QUEUE
+*
+* Description: This function is used to obtain the name assigned to a semaphore, mutex, mailbox or queue.
+*
+* Arguments  : pevent    is a pointer to the event group.  'pevent' can point either to a semaphore,
+*                        a mutex, a mailbox or a queue.  Where this function is concerned, the actual
+*                        type is irrelevant.
+*
+*              pname     is a pointer to an ASCII string that will receive the name of the semaphore,
+*                        mutex, mailbox or queue.  The string must be able to hold at least
+*                        OS_EVENT_NAME_SIZE characters.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the name was copied to 'pname'
+*                        OS_ERR_EVENT_TYPE          if 'pevent' is not pointing to the proper event
+*                                                   control block type.
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_PEVENT_NULL         if you passed a NULL pointer for 'pevent'
+*                        OS_ERR_NAME_GET_ISR        if you are trying to call this function from an ISR
+*
+* Returns    : The length of the string or 0 if the 'pevent' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1)
+INT8U  OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return (0);
+    }
+    if (pevent == (OS_EVENT *)0) {               /* Is 'pevent' a NULL pointer?                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr  = OS_ERR_NAME_GET_ISR;
+        return (0);
+    }
+    switch (pevent->OSEventType) {
+        case OS_EVENT_TYPE_SEM:
+        case OS_EVENT_TYPE_MUTEX:
+        case OS_EVENT_TYPE_MBOX:
+        case OS_EVENT_TYPE_Q:
+             break;
+
+        default:
+             *perr = OS_ERR_EVENT_TYPE;
+             return (0);
+    }
+    OS_ENTER_CRITICAL();
+    len   = OS_StrCopy(pname, pevent->OSEventName);   /* Copy name from OS_EVENT                       */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (len);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                         ASSIGN A NAME TO A SEMAPHORE, MUTEX, MAILBOX or QUEUE
+*
+* Description: This function assigns a name to a semaphore, mutex, mailbox or queue.
+*
+* Arguments  : pevent    is a pointer to the event group.  'pevent' can point either to a semaphore,
+*                        a mutex, a mailbox or a queue.  Where this function is concerned, it doesn't
+*                        matter the actual type.
+*
+*              pname     is a pointer to an ASCII string that will be used as the name of the semaphore,
+*                        mutex, mailbox or queue.  The string must be able to hold at least
+*                        OS_EVENT_NAME_SIZE characters.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the requested task is resumed
+*                        OS_ERR_EVENT_TYPE          if 'pevent' is not pointing to the proper event
+*                                                   control block type.
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_PEVENT_NULL         if you passed a NULL pointer for 'pevent'
+*                        OS_ERR_NAME_SET_ISR        if you called this function from an ISR
+*
+* Returns    : None
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1)
+void  OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return;
+    }
+    if (pevent == (OS_EVENT *)0) {               /* Is 'pevent' a NULL pointer?                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_SET_ISR;
+        return;
+    }
+    switch (pevent->OSEventType) {
+        case OS_EVENT_TYPE_SEM:
+        case OS_EVENT_TYPE_MUTEX:
+        case OS_EVENT_TYPE_MBOX:
+        case OS_EVENT_TYPE_Q:
+             break;
+
+        default:
+             *perr = OS_ERR_EVENT_TYPE;
+             return;
+    }
+    OS_ENTER_CRITICAL();
+    len = OS_StrLen(pname);                           /* Can we fit the string in the storage area?    */
+    if (len > (OS_EVENT_NAME_SIZE - 1)) {             /* No                                            */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_NAME_TOO_LONG;
+        return;
+    }
+    (void)OS_StrCopy(pevent->OSEventName, pname);     /* Yes, copy name to the event control block     */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      PEND ON MULTIPLE EVENTS
+*
+* Description: This function waits for multiple events.  If multiple events are ready at the start of the
+*              pend call, then all available events are returned as ready.  If the task must pend on the
+*              multiple events, then only the first posted or aborted event is returned as ready.
+*
+* Arguments  : pevents_pend  is a pointer to a NULL-terminated array of event control blocks to wait for.
+*
+*              pevents_rdy   is a pointer to an array to return which event control blocks are available
+*                            or ready.  The size of the array MUST be greater than or equal to the size
+*                            of the 'pevents_pend' array, including terminating NULL.
+*
+*              pmsgs_rdy     is a pointer to an array to return messages from any available message-type
+*                            events.  The size of the array MUST be greater than or equal to the size of
+*                            the 'pevents_pend' array, excluding the terminating NULL.  Since NULL
+*                            messages are valid messages, this array cannot be NULL-terminated.  Instead,
+*                            every available message-type event returns its messages in the 'pmsgs_rdy'
+*                            array at the same index as the event is returned in the 'pevents_rdy' array.
+*                            All other 'pmsgs_rdy' array indices are filled with NULL messages.
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for the resources up to the amount of time specified by this argument.
+*                            If you specify 0, however, your task will wait forever for the specified
+*                            events or, until the resources becomes available (or the events occur).
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task owns the resources
+*                                                or, the events you are waiting for occurred; check the
+*                                                'pevents_rdy' array for which events are available.
+*                            OS_ERR_PEND_ABORT   The wait on the events was aborted; check the
+*                                                'pevents_rdy' array for which events were aborted.
+*                            OS_ERR_TIMEOUT      The events were not received within the specified
+*                                                'timeout'.
+*                            OS_ERR_PEVENT_NULL  If 'pevents_pend', 'pevents_rdy', or 'pmsgs_rdy' is a 
+*                                                NULL pointer.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to an array of semaphores, 
+*                                                mailboxes, and/or queues.
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEND_LOCKED  If you called this function when the scheduler is locked.
+*
+* Returns    : >  0          the number of events returned as ready or aborted.
+*              == 0          if no events are returned as ready because of timeout or upon error.
+*
+* Notes      : 1) a. Validate 'pevents_pend' array as valid OS_EVENTs : 
+*
+*                        semaphores, mailboxes, queues
+*
+*                 b. Return ALL available events and messages, if any
+*
+*                 c. Add    current task priority as pending to   each events's wait list
+*                      Performed in OS_EventTaskWaitMulti()
+*
+*                 d. Wait on any of multiple events
+*
+*                 e. Remove current task priority as pending from each events's wait list
+*                      Performed in OS_EventTaskRdy(), if events posted or aborted
+*
+*                 f. Return any event posted or aborted, if any
+*                      else
+*                    Return timeout
+*
+*              2) 'pevents_rdy' initialized to NULL PRIOR to all other validation or function handling in 
+*                 case of any error(s).
+*********************************************************************************************************
+*/
+/*$PAGE*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+INT16U  OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr)
+{
+    OS_EVENT  **pevents;
+    OS_EVENT   *pevent;
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0))
+    OS_Q       *pq;
+#endif
+    BOOLEAN     events_rdy;
+    INT16U      events_rdy_nbr;
+    INT8U       events_stat;
+#if (OS_CRITICAL_METHOD == 3)                           /* Allocate storage for CPU status register    */
+    OS_CPU_SR   cpu_sr = 0;
+#endif
+
+
+
+#if (OS_ARG_CHK_EN > 0)
+    if (perr == (INT8U *)0) {                           /* Validate 'perr'                             */
+        return (0);
+    }
+    if (pevents_pend == (OS_EVENT **)0) {               /* Validate 'pevents_pend'                     */
+       *perr =  OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+    if (pevents_rdy  == (OS_EVENT **)0) {               /* Validate 'pevents_rdy'                      */
+       *perr =  OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+    if (pmsgs_rdy == (void **)0) {                      /* Validate 'pmsgs_rdy'                        */
+       *perr =  OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+
+   *pevents_rdy = (OS_EVENT *)0;                        /* Init array to NULL in case of errors        */
+
+    pevents     =  pevents_pend;
+    pevent      = *pevents;
+    while  (pevent != (OS_EVENT *)0) {
+        switch (pevent->OSEventType) {                  /* Validate event block types                  */
+#if (OS_SEM_EN  > 0)
+            case OS_EVENT_TYPE_SEM:
+                 break;
+#endif
+#if (OS_MBOX_EN > 0)
+            case OS_EVENT_TYPE_MBOX:
+                 break;
+#endif
+#if ((OS_Q_EN   > 0) && (OS_MAX_QS > 0))
+            case OS_EVENT_TYPE_Q:
+                 break;
+#endif
+
+            case OS_EVENT_TYPE_MUTEX:                                            
+            case OS_EVENT_TYPE_FLAG:
+            default:           
+                *perr = OS_ERR_EVENT_TYPE;
+                 return (0);
+        }
+        pevents++;
+        pevent = *pevents;
+    }
+
+    if (OSIntNesting  > 0) {                            /* See if called from ISR ...                  */
+       *perr =  OS_ERR_PEND_ISR;                        /* ... can't PEND from an ISR                  */
+        return (0);
+    }
+    if (OSLockNesting > 0) {                            /* See if called with scheduler locked ...     */
+       *perr =  OS_ERR_PEND_LOCKED;                     /* ... can't PEND when locked                  */
+        return (0);
+    }
+
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+    events_rdy     =  OS_FALSE;
+    events_rdy_nbr =  0;
+    events_stat    =  OS_STAT_RDY;
+    pevents        =  pevents_pend;
+    pevent         = *pevents;
+    while (pevent != (OS_EVENT *)0) {                   /* See if any events already available         */
+        switch (pevent->OSEventType) {
+#if (OS_SEM_EN > 0)
+            case OS_EVENT_TYPE_SEM:
+                 if (pevent->OSEventCnt > 0) {          /* If semaphore count > 0, resource available; */
+                     pevent->OSEventCnt--;              /* ... decrement semaphore,                ... */
+                    *pevents_rdy++ =  pevent;           /* ... and return available semaphore event    */
+                      events_rdy   =  OS_TRUE;
+                    *pmsgs_rdy++   = (void *)0;         /* NO message returned  for semaphores         */
+                      events_rdy_nbr++;
+
+                 } else {
+                      events_stat |=  OS_STAT_SEM;      /* Configure multi-pend for semaphore events   */
+                 }
+                 break;
+#endif
+
+#if (OS_MBOX_EN > 0)
+            case OS_EVENT_TYPE_MBOX:
+                 if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty;                   ... */
+                                                        /* ... return available message,           ... */
+                    *pmsgs_rdy++         = (void *)pevent->OSEventPtr;
+                     pevent->OSEventPtr  = (void *)0;
+                    *pevents_rdy++       =  pevent;     /* ... and return available mailbox event      */
+                      events_rdy         =  OS_TRUE;
+                      events_rdy_nbr++;
+
+                 } else {
+                      events_stat |= OS_STAT_MBOX;      /* Configure multi-pend for mailbox events     */
+                 }
+                 break;
+#endif
+
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0))
+            case OS_EVENT_TYPE_Q:
+                 pq = (OS_Q *)pevent->OSEventPtr;
+                 if (pq->OSQEntries > 0) {              /* If queue NOT empty;                     ... */
+                                                        /* ... return available message,           ... */
+                    *pmsgs_rdy++ = (void *)*pq->OSQOut++;
+                     if (pq->OSQOut == pq->OSQEnd) {    /* If OUT ptr at queue end, ...                */
+                         pq->OSQOut  = pq->OSQStart;    /* ... wrap   to queue start                   */
+                     }
+                     pq->OSQEntries--;                  /* Update number of queue entries              */
+                    *pevents_rdy++ = pevent;            /* ... and return available queue event        */
+                      events_rdy   = OS_TRUE;
+                      events_rdy_nbr++;
+
+                 } else {
+                      events_stat |= OS_STAT_Q;         /* Configure multi-pend for queue events       */
+                 }
+                 break;
+#endif
+
+            case OS_EVENT_TYPE_MUTEX:                                            
+            case OS_EVENT_TYPE_FLAG:
+            default:           
+                 OS_EXIT_CRITICAL();
+                *pevents_rdy = (OS_EVENT *)0;           /* NULL terminate return event array           */
+                *perr        =  OS_ERR_EVENT_TYPE;
+                 return (events_rdy_nbr);
+        }
+        pevents++;
+        pevent = *pevents;
+    }
+
+    if ( events_rdy == OS_TRUE) {                       /* Return any events already available         */
+       *pevents_rdy = (OS_EVENT *)0;                    /* NULL terminate return event array           */
+        OS_EXIT_CRITICAL();
+       *perr        =  OS_ERR_NONE;
+        return (events_rdy_nbr);
+    }
+/*$PAGE*/
+                                                        /* Otherwise, must wait until any event occurs */
+    OSTCBCur->OSTCBStat     |= events_stat  |           /* Resource not available, ...                 */
+                               OS_STAT_MULTI;           /* ... pend on multiple events                 */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;                 /* Store pend timeout in TCB                   */
+    OS_EventTaskWaitMulti(pevents_pend);                /* Suspend task until events or timeout occurs */
+
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                         /* Find next highest priority task ready       */
+    OS_ENTER_CRITICAL();
+
+    switch (OSTCBCur->OSTCBStatPend) {                  /* Handle event posted, aborted, or timed-out  */
+        case OS_STAT_PEND_OK:
+        case OS_STAT_PEND_ABORT:
+             pevent = OSTCBCur->OSTCBEventPtr;
+             if (pevent != (OS_EVENT *)0) {             /* If task event ptr != NULL, ...              */
+                *pevents_rdy++ =  pevent;               /* ... return available event ...              */
+                *pevents_rdy   = (OS_EVENT *)0;         /* ... & NULL terminate return event array     */
+                  events_rdy_nbr++;
+
+             } else {                                   /* Else NO event available, handle as timeout  */
+                 OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO;
+                 OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend);
+             }
+			 break;
+
+        case OS_STAT_PEND_TO:
+        default:                                        /* ... remove task from events' wait lists     */
+             OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend);
+             break;
+    }
+
+    switch (OSTCBCur->OSTCBStatPend) {
+        case OS_STAT_PEND_OK:
+             switch (pevent->OSEventType) {             /* Return event's message                      */
+#if (OS_SEM_EN > 0)
+                 case OS_EVENT_TYPE_SEM:
+                     *pmsgs_rdy++ = (void *)0;          /* NO message returned for semaphores          */
+                      break;
+#endif
+
+#if ((OS_MBOX_EN > 0) ||                 \
+    ((OS_Q_EN    > 0) && (OS_MAX_QS > 0)))
+                 case OS_EVENT_TYPE_MBOX:
+                 case OS_EVENT_TYPE_Q:
+                     *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg;     /* Return received message         */
+                      break;
+#endif
+
+                 case OS_EVENT_TYPE_MUTEX:                                       
+                 case OS_EVENT_TYPE_FLAG:
+                 default:           
+                      OS_EXIT_CRITICAL();
+                     *pevents_rdy = (OS_EVENT *)0;      /* NULL terminate return event array           */
+                     *perr        =  OS_ERR_EVENT_TYPE;
+                      return (events_rdy_nbr);
+             }
+            *perr = OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+            *pmsgs_rdy++ = (void *)0;                   /* NO message returned for abort               */
+            *perr        =  OS_ERR_PEND_ABORT;          /* Indicate that event  aborted                */
+             break;
+                                                        
+        case OS_STAT_PEND_TO:                                                
+        default:        
+            *pmsgs_rdy++ = (void *)0;                   /* NO message returned for timeout             */
+            *perr        =  OS_ERR_TIMEOUT;             /* Indicate that events timed out              */
+             break;
+    }
+
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;        /* Set   task  status to ready                 */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;    /* Clear pend  status                          */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;      /* Clear event pointers                        */
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+    OSTCBCur->OSTCBMsg           = (void      *)0;      /* Clear task  message                         */
+    OS_EXIT_CRITICAL();
+
+    return (events_rdy_nbr);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*
+* Description: This function is used to initialize the internals of uC/OS-II and MUST be called prior to
+*              creating any uC/OS-II object and, prior to calling OSStart().
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSInit (void)
+{
+    OSInitHookBegin();                                           /* Call port specific initialization code   */
+
+    OS_InitMisc();                                               /* Initialize miscellaneous variables       */
+
+    OS_InitRdyList();                                            /* Initialize the Ready List                */
+
+    OS_InitTCBList();                                            /* Initialize the free list of OS_TCBs      */
+
+    OS_InitEventList();                                          /* Initialize the free list of OS_EVENTs    */
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    OS_FlagInit();                                               /* Initialize the event flag structures     */
+#endif
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+    OS_MemInit();                                                /* Initialize the memory manager            */
+#endif
+
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+    OS_QInit();                                                  /* Initialize the message queue structures  */
+#endif
+
+    OS_InitTaskIdle();                                           /* Create the Idle Task                     */
+#if OS_TASK_STAT_EN > 0
+    OS_InitTaskStat();                                           /* Create the Statistic Task                */
+#endif
+
+#if OS_TMR_EN > 0
+    OSTmr_Init();                                                /* Initialize the Timer Manager             */
+#endif
+
+    OSInitHookEnd();                                             /* Call port specific init. code            */
+
+#if OS_DEBUG_EN > 0
+    OSDebugInit();
+#endif
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                              ENTER ISR
+*
+* Description: This function is used to notify uC/OS-II that you are about to service an interrupt
+*              service routine (ISR).  This allows uC/OS-II to keep track of interrupt nesting and thus
+*              only perform rescheduling at the last nested ISR.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) This function should be called ith interrupts already disabled
+*              2) Your ISR can directly increment OSIntNesting without calling this function because
+*                 OSIntNesting has been declared 'global'.
+*              3) You MUST still call OSIntExit() even though you increment OSIntNesting directly.
+*              4) You MUST invoke OSIntEnter() and OSIntExit() in pair.  In other words, for every call
+*                 to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the
+*                 end of the ISR.
+*              5) You are allowed to nest interrupts up to 255 levels deep.
+*********************************************************************************************************
+*/
+
+void  OSIntEnter (void)
+{
+    if (OSRunning == OS_TRUE) {
+        if (OSIntNesting < 255u) {
+            OSIntNesting++;                      /* Increment ISR nesting level                        */
+        }
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                               EXIT ISR
+*
+* Description: This function is used to notify uC/OS-II that you have completed serviving an ISR.  When
+*              the last nested ISR has completed, uC/OS-II will call the scheduler to determine whether
+*              a new, high-priority task, is ready to run.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) You MUST invoke OSIntEnter() and OSIntExit() in pair.  In other words, for every call
+*                 to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the
+*                 end of the ISR.
+*              2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock())
+*********************************************************************************************************
+*/
+
+void  OSIntExit (void)
+{
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {
+        OS_ENTER_CRITICAL();
+        if (OSIntNesting > 0) {                            /* Prevent OSIntNesting from wrapping       */
+            OSIntNesting--;
+        }
+        if (OSIntNesting == 0) {                           /* Reschedule only if all ISRs complete ... */
+            if (OSLockNesting == 0) {                      /* ... and not locked.                      */
+                OS_SchedNew();
+                if (OSPrioHighRdy != OSPrioCur) {          /* No Ctx Sw if current task is highest rdy */
+                    OSTCBHighRdy  = OSTCBPrioTbl[OSPrioHighRdy];
+#if OS_TASK_PROFILE_EN > 0
+                    OSTCBHighRdy->OSTCBCtxSwCtr++;         /* Inc. # of context switches to this task  */
+#endif
+                    OSCtxSwCtr++;                          /* Keep track of the number of ctx switches */
+                    OSIntCtxSw();                          /* Perform interrupt level ctx switch       */
+                }
+            }
+        }
+        OS_EXIT_CRITICAL();
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          PREVENT SCHEDULING
+*
+* Description: This function is used to prevent rescheduling to take place.  This allows your application
+*              to prevent context switches until you are ready to permit context switching.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair.  In other words, for every
+*                 call to OSSchedLock() you MUST have a call to OSSchedUnlock().
+*********************************************************************************************************
+*/
+
+#if OS_SCHED_LOCK_EN > 0
+void  OSSchedLock (void)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {                  /* Make sure multitasking is running                  */
+        OS_ENTER_CRITICAL();
+        if (OSIntNesting == 0) {                 /* Can't call from an ISR                             */
+            if (OSLockNesting < 255u) {          /* Prevent OSLockNesting from wrapping back to 0      */
+                OSLockNesting++;                 /* Increment lock nesting level                       */
+            }
+        }
+        OS_EXIT_CRITICAL();
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          ENABLE SCHEDULING
+*
+* Description: This function is used to re-allow rescheduling.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair.  In other words, for every
+*                 call to OSSchedLock() you MUST have a call to OSSchedUnlock().
+*********************************************************************************************************
+*/
+
+#if OS_SCHED_LOCK_EN > 0
+void  OSSchedUnlock (void)
+{
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSRunning == OS_TRUE) {                            /* Make sure multitasking is running        */
+        OS_ENTER_CRITICAL();
+        if (OSLockNesting > 0) {                           /* Do not decrement if already 0            */
+            OSLockNesting--;                               /* Decrement lock nesting level             */
+            if (OSLockNesting == 0) {                      /* See if scheduler is enabled and ...      */
+                if (OSIntNesting == 0) {                   /* ... not in an ISR                        */
+                    OS_EXIT_CRITICAL();
+                    OS_Sched();                            /* See if a HPT is ready                    */
+                } else {
+                    OS_EXIT_CRITICAL();
+                }
+            } else {
+                OS_EXIT_CRITICAL();
+            }
+        } else {
+            OS_EXIT_CRITICAL();
+        }
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          START MULTITASKING
+*
+* Description: This function is used to start the multitasking process which lets uC/OS-II manages the
+*              task that you have created.  Before you can call OSStart(), you MUST have called OSInit()
+*              and you MUST have created at least one task.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Note       : OSStartHighRdy() MUST:
+*                 a) Call OSTaskSwHook() then,
+*                 b) Set OSRunning to OS_TRUE.
+*                 c) Load the context of the task pointed to by OSTCBHighRdy.
+*                 d_ Execute the task.
+*********************************************************************************************************
+*/
+
+void  OSStart (void)
+{
+    if (OSRunning == OS_FALSE) {
+        OS_SchedNew();                               /* Find highest priority's task priority number   */
+        OSPrioCur     = OSPrioHighRdy;
+        OSTCBHighRdy  = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run    */
+        OSTCBCur      = OSTCBHighRdy;
+        OSStartHighRdy();                            /* Execute target specific code to start task     */
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        STATISTICS INITIALIZATION
+*
+* Description: This function is called by your application to establish CPU usage by first determining
+*              how high a 32-bit counter would count to in 1 second if no other tasks were to execute
+*              during that time.  CPU usage is then determined by a low priority task which keeps track
+*              of this 32-bit counter every second but this time, with other tasks running.  CPU usage is
+*              determined by:
+*
+*                                             OSIdleCtr
+*                 CPU Usage (%) = 100 * (1 - ------------)
+*                                            OSIdleCtrMax
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if OS_TASK_STAT_EN > 0
+void  OSStatInit (void)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    OSTimeDly(2);                                /* Synchronize with clock tick                        */
+    OS_ENTER_CRITICAL();
+    OSIdleCtr    = 0L;                           /* Clear idle counter                                 */
+    OS_EXIT_CRITICAL();
+    OSTimeDly(OS_TICKS_PER_SEC / 10);            /* Determine MAX. idle counter value for 1/10 second  */
+    OS_ENTER_CRITICAL();
+    OSIdleCtrMax = OSIdleCtr;                    /* Store maximum idle counter count in 1/10 second    */
+    OSStatRdy    = OS_TRUE;
+    OS_EXIT_CRITICAL();
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         PROCESS SYSTEM TICK
+*
+* Description: This function is used to signal to uC/OS-II the occurrence of a 'system tick' (also known
+*              as a 'clock tick').  This function should be called by the ticker ISR but, can also be
+*              called by a high priority task.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSTimeTick (void)
+{
+    OS_TCB    *ptcb;
+#if OS_TICK_STEP_EN > 0
+    BOOLEAN    step;
+#endif
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_TIME_TICK_HOOK_EN > 0
+    OSTimeTickHook();                                      /* Call user definable hook                     */
+#endif
+#if OS_TIME_GET_SET_EN > 0
+    OS_ENTER_CRITICAL();                                   /* Update the 32-bit tick counter               */
+    OSTime++;
+    OS_EXIT_CRITICAL();
+#endif
+    if (OSRunning == OS_TRUE) {
+#if OS_TICK_STEP_EN > 0
+        switch (OSTickStepState) {                         /* Determine whether we need to process a tick  */
+            case OS_TICK_STEP_DIS:                         /* Yes, stepping is disabled                    */
+                 step = OS_TRUE;
+                 break;
+
+            case OS_TICK_STEP_WAIT:                        /* No,  waiting for uC/OS-View to set ...       */
+                 step = OS_FALSE;                          /*      .. OSTickStepState to OS_TICK_STEP_ONCE */
+                 break;
+
+            case OS_TICK_STEP_ONCE:                        /* Yes, process tick once and wait for next ... */
+                 step            = OS_TRUE;                /*      ... step command from uC/OS-View        */
+                 OSTickStepState = OS_TICK_STEP_WAIT;
+                 break;
+
+            default:                                       /* Invalid case, correct situation              */
+                 step            = OS_TRUE;
+                 OSTickStepState = OS_TICK_STEP_DIS;
+                 break;
+        }
+        if (step == OS_FALSE) {                            /* Return if waiting for step command           */
+            return;
+        }
+#endif
+        ptcb = OSTCBList;                                  /* Point at first TCB in TCB list               */
+        while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) {     /* Go through all TCBs in TCB list              */
+            OS_ENTER_CRITICAL();
+            if (ptcb->OSTCBDly != 0) {                     /* No, Delayed or waiting for event with TO     */
+                if (--ptcb->OSTCBDly == 0) {               /* Decrement nbr of ticks to end of delay       */
+                                                           /* Check for timeout                            */
+                    if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) {
+                        ptcb->OSTCBStat  &= ~(INT8U)OS_STAT_PEND_ANY;          /* Yes, Clear status flag   */
+                        ptcb->OSTCBStatPend = OS_STAT_PEND_TO;                 /* Indicate PEND timeout    */
+                    } else {
+                        ptcb->OSTCBStatPend = OS_STAT_PEND_OK;
+                    }
+
+                    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) {  /* Is task suspended?       */
+                        OSRdyGrp               |= ptcb->OSTCBBitY;             /* No,  Make ready          */
+                        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+                    }
+                }
+            }
+            ptcb = ptcb->OSTCBNext;                        /* Point at next TCB in TCB list                */
+            OS_EXIT_CRITICAL();
+        }
+    }
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             GET VERSION
+*
+* Description: This function is used to return the version number of uC/OS-II.  The returned value
+*              corresponds to uC/OS-II's version number multiplied by 100.  In other words, version 2.00
+*              would be returned as 200.
+*
+* Arguments  : none
+*
+* Returns    : the version number of uC/OS-II multiplied by 100.
+*********************************************************************************************************
+*/
+
+INT16U  OSVersion (void)
+{
+    return (OS_VERSION);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            DUMMY FUNCTION
+*
+* Description: This function doesn't do anything.  It is called by OSTaskDel().
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if OS_TASK_DEL_EN > 0
+void  OS_Dummy (void)
+{
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                             MAKE TASK READY TO RUN BASED ON EVENT OCCURING
+*
+* Description: This function is called by other uC/OS-II services and is used to ready a task that was
+*              waiting for an event to occur.
+*
+* Arguments  : pevent      is a pointer to the event control block corresponding to the event.
+*
+*              pmsg        is a pointer to a message.  This pointer is used by message oriented services
+*                          such as MAILBOXEs and QUEUEs.  The pointer is not used when called by other
+*                          service functions.
+*
+*              msk         is a mask that is used to clear the status byte of the TCB.  For example,
+*                          OSSemPost() will pass OS_STAT_SEM, OSMboxPost() will pass OS_STAT_MBOX etc.
+*
+*              pend_stat   is used to indicate the readied task's pending status:
+*
+*                          OS_STAT_PEND_OK      Task ready due to a post (or delete), not a timeout or
+*                                               an abort.
+*                          OS_STAT_PEND_ABORT   Task ready due to an abort.
+*
+* Returns    : none
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+INT8U  OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat)
+{
+    OS_TCB  *ptcb;
+    INT8U    y;
+    INT8U    x;
+    INT8U    prio;
+#if OS_LOWEST_PRIO > 63
+    INT16U  *ptbl;
+#endif
+
+
+#if OS_LOWEST_PRIO <= 63
+    y    = OSUnMapTbl[pevent->OSEventGrp];              /* Find HPT waiting for message                */
+    x    = OSUnMapTbl[pevent->OSEventTbl[y]];
+    prio = (INT8U)((y << 3) + x);                       /* Find priority of task getting the msg       */
+#else
+    if ((pevent->OSEventGrp & 0xFF) != 0) {             /* Find HPT waiting for message                */
+        y = OSUnMapTbl[ pevent->OSEventGrp & 0xFF];
+    } else {
+        y = OSUnMapTbl[(pevent->OSEventGrp >> 8) & 0xFF] + 8;
+    }
+    ptbl = &pevent->OSEventTbl[y];
+    if ((*ptbl & 0xFF) != 0) {
+        x = OSUnMapTbl[*ptbl & 0xFF];
+    } else {
+        x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8;
+    }
+    prio = (INT8U)((y << 4) + x);                       /* Find priority of task getting the msg       */
+#endif
+
+    ptcb                  =  OSTCBPrioTbl[prio];        /* Point to this task's OS_TCB                 */
+    ptcb->OSTCBDly        =  0;                         /* Prevent OSTimeTick() from readying task     */
+#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0)
+    ptcb->OSTCBMsg        =  pmsg;                      /* Send message directly to waiting task       */
+#else
+    pmsg                  =  pmsg;                      /* Prevent compiler warning if not used        */
+#endif
+    ptcb->OSTCBStat      &= ~msk;                       /* Clear bit associated with event type        */
+    ptcb->OSTCBStatPend   =  pend_stat;                 /* Set pend status of post or abort            */
+                                                        /* See if task is ready (could be susp'd)      */
+    if ((ptcb->OSTCBStat &   OS_STAT_SUSPEND) == OS_STAT_RDY) {
+        OSRdyGrp         |=  ptcb->OSTCBBitY;           /* Put task in the ready to run list           */
+        OSRdyTbl[y]      |=  ptcb->OSTCBBitX;
+    }
+
+    OS_EventTaskRemove(ptcb, pevent);                   /* Remove this task from event   wait list     */
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {   /* Remove this task from events' wait lists    */
+        OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr);
+        ptcb->OSTCBEventPtr       = (OS_EVENT  *)pevent;/* Return event as first multi-pend event ready*/
+    }
+#endif
+
+    return (prio);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   MAKE TASK WAIT FOR EVENT TO OCCUR
+*
+* Description: This function is called by other uC/OS-II services to suspend a task because an event has
+*              not occurred.
+*
+* Arguments  : pevent   is a pointer to the event control block for which the task will be waiting for.
+*
+* Returns    : none
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventTaskWait (OS_EVENT *pevent)
+{
+    INT8U  y;
+
+
+    OSTCBCur->OSTCBEventPtr               = pevent;                 /* Store ptr to ECB in TCB         */
+
+    pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX;    /* Put task in waiting list        */
+    pevent->OSEventGrp                   |= OSTCBCur->OSTCBBitY;
+
+    y             =  OSTCBCur->OSTCBY;            /* Task no longer ready                              */
+    OSRdyTbl[y]  &= ~OSTCBCur->OSTCBBitX;
+    if (OSRdyTbl[y] == 0) {
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;         /* Clear event grp bit if this was only task pending */
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                          MAKE TASK WAIT FOR ANY OF MULTIPLE EVENTS TO OCCUR
+*
+* Description: This function is called by other uC/OS-II services to suspend a task because any one of
+*              multiple events has not occurred.
+*
+* Arguments  : pevents_wait     is a pointer to an array of event control blocks, NULL-terminated, for 
+*                               which the task will be waiting for.
+*
+* Returns    : none.
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+void  OS_EventTaskWaitMulti (OS_EVENT **pevents_wait)
+{
+    OS_EVENT **pevents;
+    OS_EVENT  *pevent;
+    INT8U      y;
+
+
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait;       /* Store ptr to ECBs in TCB        */
+
+    pevents =  pevents_wait;
+    pevent  = *pevents;
+    while (pevent != (OS_EVENT *)0) {                               /* Put task in waiting lists       */
+        pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX;
+        pevent->OSEventGrp                   |= OSTCBCur->OSTCBBitY;
+        pevents++;
+        pevent = *pevents;
+    }
+
+    y             =  OSTCBCur->OSTCBY;            /* Task no longer ready                              */
+    OSRdyTbl[y]  &= ~OSTCBCur->OSTCBBitX;
+    if (OSRdyTbl[y] == 0) {
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;         /* Clear event grp bit if this was only task pending */
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   REMOVE TASK FROM EVENT WAIT LIST
+*
+* Description: Remove a task from an event's wait list.
+*
+* Arguments  : ptcb     is a pointer to the task to remove.
+*
+*              pevent   is a pointer to the event control block.
+*
+* Returns    : none
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventTaskRemove (OS_TCB   *ptcb,
+                          OS_EVENT *pevent)
+{
+    INT8U  y;
+
+
+    y                       =  ptcb->OSTCBY;
+    pevent->OSEventTbl[y]  &= ~ptcb->OSTCBBitX;         /* Remove task from wait list                  */
+    if (pevent->OSEventTbl[y] == 0) {
+        pevent->OSEventGrp &= ~ptcb->OSTCBBitY;
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                             REMOVE TASK FROM MULTIPLE EVENTS WAIT LISTS
+*
+* Description: Remove a task from multiple events' wait lists.
+*
+* Arguments  : ptcb             is a pointer to the task to remove.
+*
+*              pevents_multi    is a pointer to the array of event control blocks, NULL-terminated.
+*
+* Returns    : none
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0))
+void  OS_EventTaskRemoveMulti (OS_TCB    *ptcb,
+                               OS_EVENT **pevents_multi)
+{
+    OS_EVENT **pevents;
+    OS_EVENT  *pevent;
+    INT8U      y;
+#if (OS_LOWEST_PRIO <= 63)
+    INT8U      bity;
+    INT8U      bitx;
+#else
+    INT16U     bity;
+    INT16U     bitx;
+#endif
+
+
+    y       =  ptcb->OSTCBY;
+    bity    =  ptcb->OSTCBBitY;
+    bitx    =  ptcb->OSTCBBitX;
+    pevents =  pevents_multi;
+    pevent  = *pevents;
+    while (pevent != (OS_EVENT *)0) {                   /* Remove task from all events' wait lists     */
+        pevent->OSEventTbl[y]  &= ~bitx;
+        if (pevent->OSEventTbl[y] == 0) {
+            pevent->OSEventGrp &= ~bity;
+        }
+        pevents++;
+        pevent = *pevents;
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                 INITIALIZE EVENT CONTROL BLOCK'S WAIT LIST
+*
+* Description: This function is called by other uC/OS-II services to initialize the event wait list.
+*
+* Arguments  : pevent    is a pointer to the event control block allocated to the event.
+*
+* Returns    : none
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+#if (OS_EVENT_EN)
+void  OS_EventWaitListInit (OS_EVENT *pevent)
+{
+#if OS_LOWEST_PRIO <= 63
+    INT8U  *ptbl;
+#else
+    INT16U *ptbl;
+#endif
+    INT8U   i;
+
+
+    pevent->OSEventGrp = 0;                      /* No task waiting on event                           */
+    ptbl               = &pevent->OSEventTbl[0];
+
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+        *ptbl++ = 0;
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                           INITIALIZE THE FREE LIST OF EVENT CONTROL BLOCKS
+*
+* Description: This function is called by OSInit() to initialize the free list of event control blocks.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitEventList (void)
+{
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0)
+#if (OS_MAX_EVENTS > 1)
+    INT16U     i;
+    OS_EVENT  *pevent1;
+    OS_EVENT  *pevent2;
+
+
+    OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table                   */
+    pevent1 = &OSEventTbl[0];
+    pevent2 = &OSEventTbl[1];
+    for (i = 0; i < (OS_MAX_EVENTS - 1); i++) {             /* Init. list of free EVENT control blocks */
+        pevent1->OSEventType    = OS_EVENT_TYPE_UNUSED;
+        pevent1->OSEventPtr     = pevent2;
+#if OS_EVENT_NAME_SIZE > 1
+        pevent1->OSEventName[0] = '?';                      /* Unknown name                            */
+        pevent1->OSEventName[1] = OS_ASCII_NUL;
+#endif
+        pevent1++;
+        pevent2++;
+    }
+    pevent1->OSEventType            = OS_EVENT_TYPE_UNUSED;
+    pevent1->OSEventPtr             = (OS_EVENT *)0;
+#if OS_EVENT_NAME_SIZE > 1
+    pevent1->OSEventName[0]         = '?';
+    pevent1->OSEventName[1]         = OS_ASCII_NUL;
+#endif
+    OSEventFreeList                 = &OSEventTbl[0];
+#else
+    OSEventFreeList                 = &OSEventTbl[0];       /* Only have ONE event control block       */
+    OSEventFreeList->OSEventType    = OS_EVENT_TYPE_UNUSED;
+    OSEventFreeList->OSEventPtr     = (OS_EVENT *)0;
+#if OS_EVENT_NAME_SIZE > 1
+    OSEventFreeList->OSEventName[0] = '?';                  /* Unknown name                            */
+    OSEventFreeList->OSEventName[1] = OS_ASCII_NUL;
+#endif
+#endif
+#endif
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                                    INITIALIZE MISCELLANEOUS VARIABLES
+*
+* Description: This function is called by OSInit() to initialize miscellaneous variables.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitMisc (void)
+{
+#if OS_TIME_GET_SET_EN > 0
+    OSTime        = 0L;                                    /* Clear the 32-bit system clock            */
+#endif
+
+    OSIntNesting  = 0;                                     /* Clear the interrupt nesting counter      */
+    OSLockNesting = 0;                                     /* Clear the scheduling lock counter        */
+
+    OSTaskCtr     = 0;                                     /* Clear the number of tasks                */
+
+    OSRunning     = OS_FALSE;                              /* Indicate that multitasking not started   */
+
+    OSCtxSwCtr    = 0;                                     /* Clear the context switch counter         */
+    OSIdleCtr     = 0L;                                    /* Clear the 32-bit idle counter            */
+
+#if OS_TASK_STAT_EN > 0
+    OSIdleCtrRun  = 0L;
+    OSIdleCtrMax  = 0L;
+    OSStatRdy     = OS_FALSE;                              /* Statistic task is not ready              */
+#endif
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                                       INITIALIZE THE READY LIST
+*
+* Description: This function is called by OSInit() to initialize the Ready List.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitRdyList (void)
+{
+    INT8U    i;
+#if OS_LOWEST_PRIO <= 63
+    INT8U   *prdytbl;
+#else
+    INT16U  *prdytbl;
+#endif
+
+
+    OSRdyGrp      = 0;                                     /* Clear the ready list                     */
+    prdytbl       = &OSRdyTbl[0];
+    for (i = 0; i < OS_RDY_TBL_SIZE; i++) {
+        *prdytbl++ = 0;
+    }
+
+    OSPrioCur     = 0;
+    OSPrioHighRdy = 0;
+
+    OSTCBHighRdy  = (OS_TCB *)0;
+    OSTCBCur      = (OS_TCB *)0;
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                                         CREATING THE IDLE TASK
+*
+* Description: This function creates the Idle Task.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitTaskIdle (void)
+{
+#if OS_TASK_NAME_SIZE > 7
+    INT8U  err;
+#endif
+
+
+#if OS_TASK_CREATE_EXT_EN > 0
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreateExt(OS_TaskIdle,
+                          (void *)0,                                 /* No arguments passed to OS_TaskIdle() */
+                          &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Top-Of-Stack                     */
+                          OS_TASK_IDLE_PRIO,                         /* Lowest priority level                */
+                          OS_TASK_IDLE_ID,
+                          &OSTaskIdleStk[0],                         /* Set Bottom-Of-Stack                  */
+                          OS_TASK_IDLE_STK_SIZE,
+                          (void *)0,                                 /* No TCB extension                     */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack  */
+    #else
+    (void)OSTaskCreateExt(OS_TaskIdle,
+                          (void *)0,                                 /* No arguments passed to OS_TaskIdle() */
+                          &OSTaskIdleStk[0],                         /* Set Top-Of-Stack                     */
+                          OS_TASK_IDLE_PRIO,                         /* Lowest priority level                */
+                          OS_TASK_IDLE_ID,
+                          &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Bottom-Of-Stack                  */
+                          OS_TASK_IDLE_STK_SIZE,
+                          (void *)0,                                 /* No TCB extension                     */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack  */
+    #endif
+#else
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreate(OS_TaskIdle,
+                       (void *)0,
+                       &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1],
+                       OS_TASK_IDLE_PRIO);
+    #else
+    (void)OSTaskCreate(OS_TaskIdle,
+                       (void *)0,
+                       &OSTaskIdleStk[0],
+                       OS_TASK_IDLE_PRIO);
+    #endif
+#endif
+
+#if OS_TASK_NAME_SIZE > 14
+    OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err);
+#else
+#if OS_TASK_NAME_SIZE > 7
+    OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err);
+#endif
+#endif
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                                      CREATING THE STATISTIC TASK
+*
+* Description: This function creates the Statistic Task.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if OS_TASK_STAT_EN > 0
+static  void  OS_InitTaskStat (void)
+{
+#if OS_TASK_NAME_SIZE > 7
+    INT8U  err;
+#endif
+
+
+#if OS_TASK_CREATE_EXT_EN > 0
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreateExt(OS_TaskStat,
+                          (void *)0,                                   /* No args passed to OS_TaskStat()*/
+                          &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1],   /* Set Top-Of-Stack               */
+                          OS_TASK_STAT_PRIO,                           /* One higher than the idle task  */
+                          OS_TASK_STAT_ID,
+                          &OSTaskStatStk[0],                           /* Set Bottom-Of-Stack            */
+                          OS_TASK_STAT_STK_SIZE,
+                          (void *)0,                                   /* No TCB extension               */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);  /* Enable stack checking + clear  */
+    #else
+    (void)OSTaskCreateExt(OS_TaskStat,
+                          (void *)0,                                   /* No args passed to OS_TaskStat()*/
+                          &OSTaskStatStk[0],                           /* Set Top-Of-Stack               */
+                          OS_TASK_STAT_PRIO,                           /* One higher than the idle task  */
+                          OS_TASK_STAT_ID,
+                          &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1],   /* Set Bottom-Of-Stack            */
+                          OS_TASK_STAT_STK_SIZE,
+                          (void *)0,                                   /* No TCB extension               */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);  /* Enable stack checking + clear  */
+    #endif
+#else
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreate(OS_TaskStat,
+                       (void *)0,                                      /* No args passed to OS_TaskStat()*/
+                       &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1],      /* Set Top-Of-Stack               */
+                       OS_TASK_STAT_PRIO);                             /* One higher than the idle task  */
+    #else
+    (void)OSTaskCreate(OS_TaskStat,
+                       (void *)0,                                      /* No args passed to OS_TaskStat()*/
+                       &OSTaskStatStk[0],                              /* Set Top-Of-Stack               */
+                       OS_TASK_STAT_PRIO);                             /* One higher than the idle task  */
+    #endif
+#endif
+
+#if OS_TASK_NAME_SIZE > 14
+    OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err);
+#else
+#if OS_TASK_NAME_SIZE > 7
+    OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err);
+#endif
+#endif
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             INITIALIZATION
+*                            INITIALIZE THE FREE LIST OF TASK CONTROL BLOCKS
+*
+* Description: This function is called by OSInit() to initialize the free list of OS_TCBs.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OS_InitTCBList (void)
+{
+    INT8U    i;
+    OS_TCB  *ptcb1;
+    OS_TCB  *ptcb2;
+
+
+    OS_MemClr((INT8U *)&OSTCBTbl[0],     sizeof(OSTCBTbl));      /* Clear all the TCBs                 */
+    OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl));  /* Clear the priority table           */
+    ptcb1 = &OSTCBTbl[0];
+    ptcb2 = &OSTCBTbl[1];
+    for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) {  /* Init. list of free TCBs            */
+        ptcb1->OSTCBNext = ptcb2;
+#if OS_TASK_NAME_SIZE > 1
+        ptcb1->OSTCBTaskName[0] = '?';                           /* Unknown name                       */
+        ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL;
+#endif
+        ptcb1++;
+        ptcb2++;
+    }
+    ptcb1->OSTCBNext = (OS_TCB *)0;                              /* Last OS_TCB                        */
+#if OS_TASK_NAME_SIZE > 1
+    ptcb1->OSTCBTaskName[0] = '?';                               /* Unknown name                       */
+    ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL;
+#endif
+    OSTCBList               = (OS_TCB *)0;                       /* TCB lists initializations          */
+    OSTCBFreeList           = &OSTCBTbl[0];
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        CLEAR A SECTION OF MEMORY
+*
+* Description: This function is called by other uC/OS-II services to clear a contiguous block of RAM.
+*
+* Arguments  : pdest    is the start of the RAM to clear (i.e. write 0x00 to)
+*
+*              size     is the number of bytes to clear.
+*
+* Returns    : none
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.
+*              2) Note that we can only clear up to 64K bytes of RAM.  This is not an issue because none
+*                 of the uses of this function gets close to this limit.
+*              3) The clear is done one byte at a time since this will work on any processor irrespective
+*                 of the alignment of the destination.
+*********************************************************************************************************
+*/
+
+void  OS_MemClr (INT8U *pdest, INT16U size)
+{
+    while (size > 0) {
+        *pdest++ = (INT8U)0;
+        size--;
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        COPY A BLOCK OF MEMORY
+*
+* Description: This function is called by other uC/OS-II services to copy a block of memory from one
+*              location to another.
+*
+* Arguments  : pdest    is a pointer to the 'destination' memory block
+*
+*              psrc     is a pointer to the 'source'      memory block
+*
+*              size     is the number of bytes to copy.
+*
+* Returns    : none
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.  There is
+*                 no provision to handle overlapping memory copy.  However, that's not a problem since this
+*                 is not a situation that will happen.
+*              2) Note that we can only copy up to 64K bytes of RAM
+*              3) The copy is done one byte at a time since this will work on any processor irrespective
+*                 of the alignment of the source and destination.
+*********************************************************************************************************
+*/
+
+void  OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size)
+{
+    while (size > 0) {
+        *pdest++ = *psrc++;
+        size--;
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                              SCHEDULER
+*
+* Description: This function is called by other uC/OS-II services to determine whether a new, high
+*              priority task has been made ready to run.  This function is invoked by TASK level code
+*              and is not used to reschedule tasks from ISRs (see OSIntExit() for ISR rescheduling).
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.
+*              2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock())
+*********************************************************************************************************
+*/
+
+void  OS_Sched (void)
+{
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    if (OSIntNesting == 0) {                           /* Schedule only if all ISRs done and ...       */
+        if (OSLockNesting == 0) {                      /* ... scheduler is not locked                  */
+            OS_SchedNew();
+            if (OSPrioHighRdy != OSPrioCur) {          /* No Ctx Sw if current task is highest rdy     */
+                OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy];
+#if OS_TASK_PROFILE_EN > 0
+                OSTCBHighRdy->OSTCBCtxSwCtr++;         /* Inc. # of context switches to this task      */
+#endif
+                OSCtxSwCtr++;                          /* Increment context switch counter             */
+                OS_TASK_SW();                          /* Perform a context switch                     */
+            }
+        }
+    }
+    OS_EXIT_CRITICAL();
+}
+
+
+/*
+*********************************************************************************************************
+*                              FIND HIGHEST PRIORITY TASK READY TO RUN
+*
+* Description: This function is called by other uC/OS-II services to determine the highest priority task
+*              that is ready to run.  The global variable 'OSPrioHighRdy' is changed accordingly.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.
+*              2) Interrupts are assumed to be disabled when this function is called.
+*********************************************************************************************************
+*/
+
+static  void  OS_SchedNew (void)
+{
+#if OS_LOWEST_PRIO <= 63                         /* See if we support up to 64 tasks                   */
+    INT8U   y;
+
+
+    y             = OSUnMapTbl[OSRdyGrp];
+    OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]);
+#else                                            /* We support up to 256 tasks                         */
+    INT8U   y;
+    INT16U *ptbl;
+
+
+    if ((OSRdyGrp & 0xFF) != 0) {
+        y = OSUnMapTbl[OSRdyGrp & 0xFF];
+    } else {
+        y = OSUnMapTbl[(OSRdyGrp >> 8) & 0xFF] + 8;
+    }
+    ptbl = &OSRdyTbl[y];
+    if ((*ptbl & 0xFF) != 0) {
+        OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]);
+    } else {
+        OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8);
+    }
+#endif
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        COPY AN ASCII STRING
+*
+* Description: This function is called by other uC/OS-II services to copy an ASCII string from a 'source'
+*              string to a 'destination' string.
+*
+* Arguments  : pdest    is a pointer to the string that will be receiving the copy.  Note that there MUST
+*                       be sufficient space in the destination storage area to receive this string.
+*
+*              psrc     is a pointer to the source string.  The source string MUST NOT be greater than
+*                       254 characters.
+*
+* Returns    : The size of the string (excluding the NUL terminating character)
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1)
+INT8U  OS_StrCopy (INT8U *pdest, INT8U *psrc)
+{
+    INT8U  len;
+
+
+    len = 0;
+    while (*psrc != OS_ASCII_NUL) {
+        *pdest++ = *psrc++;
+        len++;
+    }
+    *pdest = OS_ASCII_NUL;
+    return (len);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                DETERMINE THE LENGTH OF AN ASCII STRING
+*
+* Description: This function is called by other uC/OS-II services to determine the size of an ASCII string
+*              (excluding the NUL character).
+*
+* Arguments  : psrc     is a pointer to the string for which we need to know the size.
+*
+* Returns    : The size of the string (excluding the NUL terminating character)
+*
+* Notes      : 1) This function is INTERNAL to uC/OS-II and your application should not call it.
+*              2) The string to check must be less than 255 characters long.
+*********************************************************************************************************
+*/
+
+#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1)
+INT8U  OS_StrLen (INT8U *psrc)
+{
+    INT8U  len;
+
+
+    len = 0;
+    while (*psrc != OS_ASCII_NUL) {
+        psrc++;
+        len++;
+    }
+    return (len);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                              IDLE TASK
+*
+* Description: This task is internal to uC/OS-II and executes whenever no other higher priority tasks
+*              executes because they are ALL waiting for event(s) to occur.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Note(s)    : 1) OSTaskIdleHook() is called after the critical section to ensure that interrupts will be
+*                 enabled for at least a few instructions.  On some processors (ex. Philips XA), enabling
+*                 and then disabling interrupts didn't allow the processor enough time to have interrupts
+*                 enabled before they were disabled again.  uC/OS-II would thus never recognize
+*                 interrupts.
+*              2) This hook has been added to allow you to do such things as STOP the CPU to conserve
+*                 power.
+*********************************************************************************************************
+*/
+
+void  OS_TaskIdle (void *p_arg)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    (void)p_arg;                                 /* Prevent compiler warning for not using 'p_arg'     */
+    for (;;) {
+        OS_ENTER_CRITICAL();
+        OSIdleCtr++;
+        OS_EXIT_CRITICAL();
+        OSTaskIdleHook();                        /* Call user definable HOOK                           */
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            STATISTICS TASK
+*
+* Description: This task is internal to uC/OS-II and is used to compute some statistics about the
+*              multitasking environment.  Specifically, OS_TaskStat() computes the CPU usage.
+*              CPU usage is determined by:
+*
+*                                          OSIdleCtr
+*                 OSCPUUsage = 100 * (1 - ------------)     (units are in %)
+*                                         OSIdleCtrMax
+*
+* Arguments  : parg     this pointer is not used at this time.
+*
+* Returns    : none
+*
+* Notes      : 1) This task runs at a priority level higher than the idle task.  In fact, it runs at the
+*                 next higher priority, OS_TASK_IDLE_PRIO-1.
+*              2) You can disable this task by setting the configuration #define OS_TASK_STAT_EN to 0.
+*              3) You MUST have at least a delay of 2/10 seconds to allow for the system to establish the
+*                 maximum value for the idle counter.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_STAT_EN > 0
+void  OS_TaskStat (void *p_arg)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    (void)p_arg;                                 /* Prevent compiler warning for not using 'p_arg'     */
+    while (OSStatRdy == OS_FALSE) {
+        OSTimeDly(2 * OS_TICKS_PER_SEC / 10);    /* Wait until statistic task is ready                 */
+    }
+    OSIdleCtrMax /= 100L;
+    if (OSIdleCtrMax == 0L) {
+        OSCPUUsage = 0;
+        (void)OSTaskSuspend(OS_PRIO_SELF);
+    }
+    for (;;) {
+        OS_ENTER_CRITICAL();
+        OSIdleCtrRun = OSIdleCtr;                /* Obtain the of the idle counter for the past second */
+        OSIdleCtr    = 0L;                       /* Reset the idle counter for the next second         */
+        OS_EXIT_CRITICAL();
+        OSCPUUsage   = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax);
+        OSTaskStatHook();                        /* Invoke user definable hook                         */
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+        OS_TaskStatStkChk();                     /* Check the stacks for each task                     */
+#endif
+        OSTimeDly(OS_TICKS_PER_SEC / 10);        /* Accumulate OSIdleCtr for the next 1/10 second      */
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      CHECK ALL TASK STACKS
+*
+* Description: This function is called by OS_TaskStat() to check the stacks of each active task.
+*
+* Arguments  : none
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+void  OS_TaskStatStkChk (void)
+{
+    OS_TCB      *ptcb;
+    OS_STK_DATA  stk_data;
+    INT8U        err;
+    INT8U        prio;
+
+
+    for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) {
+        err = OSTaskStkChk(prio, &stk_data);
+        if (err == OS_ERR_NONE) {
+            ptcb = OSTCBPrioTbl[prio];
+            if (ptcb != (OS_TCB *)0) {                               /* Make sure task 'ptcb' is ...   */
+                if (ptcb != OS_TCB_RESERVED) {                       /* ... still valid.               */
+#if OS_TASK_PROFILE_EN > 0
+                    #if OS_STK_GROWTH == 1
+                    ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize;
+                    #else
+                    ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize;
+                    #endif
+                    ptcb->OSTCBStkUsed = stk_data.OSUsed;            /* Store the number of bytes used */
+#endif
+                }
+            }
+        }
+    }
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            INITIALIZE TCB
+*
+* Description: This function is internal to uC/OS-II and is used to initialize a Task Control Block when
+*              a task is created (see OSTaskCreate() and OSTaskCreateExt()).
+*
+* Arguments  : prio          is the priority of the task being created
+*
+*              ptos          is a pointer to the task's top-of-stack assuming that the CPU registers
+*                            have been placed on the stack.  Note that the top-of-stack corresponds to a
+*                            'high' memory location is OS_STK_GROWTH is set to 1 and a 'low' memory
+*                            location if OS_STK_GROWTH is set to 0.  Note that stack growth is CPU
+*                            specific.
+*
+*              pbos          is a pointer to the bottom of stack.  A NULL pointer is passed if called by
+*                            'OSTaskCreate()'.
+*
+*              id            is the task's ID (0..65535)
+*
+*              stk_size      is the size of the stack (in 'stack units').  If the stack units are INT8Us
+*                            then, 'stk_size' contains the number of bytes for the stack.  If the stack
+*                            units are INT32Us then, the stack contains '4 * stk_size' bytes.  The stack
+*                            units are established by the #define constant OS_STK which is CPU
+*                            specific.  'stk_size' is 0 if called by 'OSTaskCreate()'.
+*
+*              pext          is a pointer to a user supplied memory area that is used to extend the task
+*                            control block.  This allows you to store the contents of floating-point
+*                            registers, MMU registers or anything else you could find useful during a
+*                            context switch.  You can even assign a name to each task and store this name
+*                            in this TCB extension.  A NULL pointer is passed if called by OSTaskCreate().
+*
+*              opt           options as passed to 'OSTaskCreateExt()' or,
+*                            0 if called from 'OSTaskCreate()'.
+*
+* Returns    : OS_ERR_NONE         if the call was successful
+*              OS_ERR_TASK_NO_MORE_TCB  if there are no more free TCBs to be allocated and thus, the task cannot
+*                                  be created.
+*
+* Note       : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+INT8U  OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt)
+{
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    ptcb = OSTCBFreeList;                                  /* Get a free TCB from the free TCB list    */
+    if (ptcb != (OS_TCB *)0) {
+        OSTCBFreeList            = ptcb->OSTCBNext;        /* Update pointer to free TCB list          */
+        OS_EXIT_CRITICAL();
+        ptcb->OSTCBStkPtr        = ptos;                   /* Load Stack pointer in TCB                */
+        ptcb->OSTCBPrio          = prio;                   /* Load task priority into TCB              */
+        ptcb->OSTCBStat          = OS_STAT_RDY;            /* Task is ready to run                     */
+        ptcb->OSTCBStatPend      = OS_STAT_PEND_OK;        /* Clear pend status                        */
+        ptcb->OSTCBDly           = 0;                      /* Task is not delayed                      */
+
+#if OS_TASK_CREATE_EXT_EN > 0
+        ptcb->OSTCBExtPtr        = pext;                   /* Store pointer to TCB extension           */
+        ptcb->OSTCBStkSize       = stk_size;               /* Store stack size                         */
+        ptcb->OSTCBStkBottom     = pbos;                   /* Store pointer to bottom of stack         */
+        ptcb->OSTCBOpt           = opt;                    /* Store task options                       */
+        ptcb->OSTCBId            = id;                     /* Store task ID                            */
+#else
+        pext                     = pext;                   /* Prevent compiler warning if not used     */
+        stk_size                 = stk_size;
+        pbos                     = pbos;
+        opt                      = opt;
+        id                       = id;
+#endif
+
+#if OS_TASK_DEL_EN > 0
+        ptcb->OSTCBDelReq        = OS_ERR_NONE;
+#endif
+
+#if OS_LOWEST_PRIO <= 63
+        ptcb->OSTCBY             = (INT8U)(prio >> 3);          /* Pre-compute X, Y, BitX and BitY     */
+        ptcb->OSTCBX             = (INT8U)(prio & 0x07);
+        ptcb->OSTCBBitY          = (INT8U)(1 << ptcb->OSTCBY);
+        ptcb->OSTCBBitX          = (INT8U)(1 << ptcb->OSTCBX);
+#else
+        ptcb->OSTCBY             = (INT8U)((prio >> 4) & 0xFF); /* Pre-compute X, Y, BitX and BitY     */
+        ptcb->OSTCBX             = (INT8U) (prio & 0x0F);
+        ptcb->OSTCBBitY          = (INT16U)(1 << ptcb->OSTCBY);
+        ptcb->OSTCBBitX          = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+
+#if (OS_EVENT_EN)
+        ptcb->OSTCBEventPtr      = (OS_EVENT  *)0;         /* Task is not pending on an  event         */
+#if (OS_EVENT_MULTI_EN > 0)
+        ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0;         /* Task is not pending on any events        */
+#endif
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0)
+        ptcb->OSTCBFlagNode  = (OS_FLAG_NODE *)0;          /* Task is not pending on an event flag     */
+#endif
+
+#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0))
+        ptcb->OSTCBMsg       = (void *)0;                  /* No message received                      */
+#endif
+
+#if OS_TASK_PROFILE_EN > 0
+        ptcb->OSTCBCtxSwCtr    = 0L;                       /* Initialize profiling variables           */
+        ptcb->OSTCBCyclesStart = 0L;
+        ptcb->OSTCBCyclesTot   = 0L;
+        ptcb->OSTCBStkBase     = (OS_STK *)0;
+        ptcb->OSTCBStkUsed     = 0L;
+#endif
+
+#if OS_TASK_NAME_SIZE > 1
+        ptcb->OSTCBTaskName[0] = '?';                      /* Unknown name at task creation            */
+        ptcb->OSTCBTaskName[1] = OS_ASCII_NUL;
+#endif
+
+        OSTCBInitHook(ptcb);
+
+        OSTaskCreateHook(ptcb);                            /* Call user defined hook                   */
+
+        OS_ENTER_CRITICAL();
+        OSTCBPrioTbl[prio] = ptcb;
+        ptcb->OSTCBNext    = OSTCBList;                    /* Link into TCB chain                      */
+        ptcb->OSTCBPrev    = (OS_TCB *)0;
+        if (OSTCBList != (OS_TCB *)0) {
+            OSTCBList->OSTCBPrev = ptcb;
+        }
+        OSTCBList               = ptcb;
+        OSRdyGrp               |= ptcb->OSTCBBitY;         /* Make task ready to run                   */
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+        OSTaskCtr++;                                       /* Increment the #tasks counter             */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NONE);
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_TASK_NO_MORE_TCB);
+}
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c
new file mode 100644
index 0000000..fb84a6d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_dbg.c
@@ -0,0 +1,312 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                           DEBUGGER CONSTANTS
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_DBG.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#include <ucos_ii.h>
+
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*********************************************************************************************************
+*/
+
+INT16U  const  OSDebugEn           = OS_DEBUG_EN;               /* Debug constants are defined below   */
+
+#if OS_DEBUG_EN > 0
+
+INT32U  const  OSEndiannessTest    = 0x12345678L;               /* Variable to test CPU endianness     */
+
+INT16U  const  OSEventEn           = OS_EVENT_EN;
+INT16U  const  OSEventMax          = OS_MAX_EVENTS;             /* Number of event control blocks      */
+INT16U  const  OSEventNameSize     = OS_EVENT_NAME_SIZE;        /* Size (in bytes) of event names      */
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0)
+INT16U  const  OSEventSize         = sizeof(OS_EVENT);          /* Size in Bytes of OS_EVENT           */
+INT16U  const  OSEventTblSize      = sizeof(OSEventTbl);        /* Size of OSEventTbl[] in bytes       */
+#else
+INT16U  const  OSEventSize         = 0;
+INT16U  const  OSEventTblSize      = 0;
+#endif
+INT16U  const  OSEventMultiEn      = OS_EVENT_MULTI_EN;
+
+
+INT16U  const  OSFlagEn            = OS_FLAG_EN;
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+INT16U  const  OSFlagGrpSize       = sizeof(OS_FLAG_GRP);       /* Size in Bytes of OS_FLAG_GRP        */
+INT16U  const  OSFlagNodeSize      = sizeof(OS_FLAG_NODE);      /* Size in Bytes of OS_FLAG_NODE       */
+INT16U  const  OSFlagWidth         = sizeof(OS_FLAGS);          /* Width (in bytes) of OS_FLAGS        */
+#else
+INT16U  const  OSFlagGrpSize       = 0;
+INT16U  const  OSFlagNodeSize      = 0;
+INT16U  const  OSFlagWidth         = 0;
+#endif
+INT16U  const  OSFlagMax           = OS_MAX_FLAGS;
+INT16U  const  OSFlagNameSize      = OS_FLAG_NAME_SIZE;         /* Size (in bytes) of flag names       */
+
+INT16U  const  OSLowestPrio        = OS_LOWEST_PRIO;
+
+INT16U  const  OSMboxEn            = OS_MBOX_EN;
+
+INT16U  const  OSMemEn             = OS_MEM_EN;
+INT16U  const  OSMemMax            = OS_MAX_MEM_PART;           /* Number of memory partitions         */
+INT16U  const  OSMemNameSize       = OS_MEM_NAME_SIZE;          /* Size (in bytes) of partition names  */
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+INT16U  const  OSMemSize           = sizeof(OS_MEM);            /* Mem. Partition header sine (bytes)  */
+INT16U  const  OSMemTblSize        = sizeof(OSMemTbl);
+#else
+INT16U  const  OSMemSize           = 0;
+INT16U  const  OSMemTblSize        = 0;
+#endif
+INT16U  const  OSMutexEn           = OS_MUTEX_EN;
+
+INT16U  const  OSPtrSize           = sizeof(void *);            /* Size in Bytes of a pointer          */
+
+INT16U  const  OSQEn               = OS_Q_EN;
+INT16U  const  OSQMax              = OS_MAX_QS;                 /* Number of queues                    */
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+INT16U  const  OSQSize             = sizeof(OS_Q);              /* Size in bytes of OS_Q structure     */
+#else
+INT16U  const  OSQSize             = 0;
+#endif
+
+INT16U  const  OSRdyTblSize        = OS_RDY_TBL_SIZE;           /* Number of bytes in the ready table  */
+
+INT16U  const  OSSemEn             = OS_SEM_EN;
+
+INT16U  const  OSStkWidth          = sizeof(OS_STK);            /* Size in Bytes of a stack entry      */
+
+INT16U  const  OSTaskCreateEn      = OS_TASK_CREATE_EN;
+INT16U  const  OSTaskCreateExtEn   = OS_TASK_CREATE_EXT_EN;
+INT16U  const  OSTaskDelEn         = OS_TASK_DEL_EN;
+INT16U  const  OSTaskIdleStkSize   = OS_TASK_IDLE_STK_SIZE;
+INT16U  const  OSTaskProfileEn     = OS_TASK_PROFILE_EN;
+INT16U  const  OSTaskMax           = OS_MAX_TASKS + OS_N_SYS_TASKS; /* Total max. number of tasks      */
+INT16U  const  OSTaskNameSize      = OS_TASK_NAME_SIZE;             /* Size (in bytes) of task names   */
+INT16U  const  OSTaskStatEn        = OS_TASK_STAT_EN;
+INT16U  const  OSTaskStatStkSize   = OS_TASK_STAT_STK_SIZE;
+INT16U  const  OSTaskStatStkChkEn  = OS_TASK_STAT_STK_CHK_EN;
+INT16U  const  OSTaskSwHookEn      = OS_TASK_SW_HOOK_EN;
+
+INT16U  const  OSTCBPrioTblMax     = OS_LOWEST_PRIO + 1;        /* Number of entries in OSTCBPrioTbl[] */
+INT16U  const  OSTCBSize           = sizeof(OS_TCB);            /* Size in Bytes of OS_TCB             */
+INT16U  const  OSTicksPerSec       = OS_TICKS_PER_SEC;
+INT16U  const  OSTimeTickHookEn    = OS_TIME_TICK_HOOK_EN;
+INT16U  const  OSVersionNbr        = OS_VERSION;
+
+INT16U  const  OSTmrEn             = OS_TMR_EN;
+INT16U  const  OSTmrCfgMax         = OS_TMR_CFG_MAX;
+INT16U  const  OSTmrCfgNameSize    = OS_TMR_CFG_NAME_SIZE;
+INT16U  const  OSTmrCfgWheelSize   = OS_TMR_CFG_WHEEL_SIZE;
+INT16U  const  OSTmrCfgTicksPerSec = OS_TMR_CFG_TICKS_PER_SEC;
+
+#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0)
+INT16U  const  OSTmrSize           = sizeof(OS_TMR);
+INT16U  const  OSTmrTblSize        = sizeof(OSTmrTbl);
+INT16U  const  OSTmrWheelSize      = sizeof(OS_TMR_WHEEL);
+INT16U  const  OSTmrWheelTblSize   = sizeof(OSTmrWheelTbl);
+#else
+INT16U  const  OSTmrSize           = 0;
+INT16U  const  OSTmrTblSize        = 0;
+INT16U  const  OSTmrWheelSize      = 0;
+INT16U  const  OSTmrWheelTblSize   = 0;
+#endif
+
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*                            TOTAL DATA SPACE (i.e. RAM) USED BY uC/OS-II
+*********************************************************************************************************
+*/
+#if OS_DEBUG_EN > 0
+
+INT16U  const  OSDataSize = sizeof(OSCtxSwCtr)
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0)
+                          + sizeof(OSEventFreeList)
+                          + sizeof(OSEventTbl)
+#endif
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+                          + sizeof(OSFlagTbl)
+                          + sizeof(OSFlagFreeList)
+#endif
+#if OS_TASK_STAT_EN > 0
+                          + sizeof(OSCPUUsage)
+                          + sizeof(OSIdleCtrMax)
+                          + sizeof(OSIdleCtrRun)
+                          + sizeof(OSStatRdy)
+                          + sizeof(OSTaskStatStk)
+#endif
+#if OS_TICK_STEP_EN > 0
+                          + sizeof(OSTickStepState)
+#endif
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+                          + sizeof(OSMemFreeList)
+                          + sizeof(OSMemTbl)
+#endif
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+                          + sizeof(OSQFreeList)
+                          + sizeof(OSQTbl)
+#endif
+#if OS_TIME_GET_SET_EN > 0   
+                          + sizeof(OSTime)
+#endif
+#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0)
+                          + sizeof(OSTmrFree)
+                          + sizeof(OSTmrUsed)
+                          + sizeof(OSTmrTime)
+                          + sizeof(OSTmrSem)
+                          + sizeof(OSTmrSemSignal)
+                          + sizeof(OSTmrTbl)
+                          + sizeof(OSTmrFreeList)
+                          + sizeof(OSTmrTaskStk)
+                          + sizeof(OSTmrWheelTbl)
+#endif
+                          + sizeof(OSIntNesting)
+                          + sizeof(OSLockNesting)
+                          + sizeof(OSPrioCur)
+                          + sizeof(OSPrioHighRdy)
+                          + sizeof(OSRdyGrp)
+                          + sizeof(OSRdyTbl)
+                          + sizeof(OSRunning)
+                          + sizeof(OSTaskCtr)
+                          + sizeof(OSIdleCtr)
+                          + sizeof(OSTaskIdleStk)
+                          + sizeof(OSTCBCur)
+                          + sizeof(OSTCBFreeList)
+                          + sizeof(OSTCBHighRdy)
+                          + sizeof(OSTCBList)
+                          + sizeof(OSTCBPrioTbl)
+                          + sizeof(OSTCBTbl);
+
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        OS DEBUG INITIALIZATION
+*
+* Description: This function is used to make sure that debug variables that are unused in the application
+*              are not optimized away.  This function might not be necessary for all compilers.  In this
+*              case, you should simply DELETE the code in this function while still leaving the declaration
+*              of the function itself.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Note(s)    : (1) This code doesn't do anything, it simply prevents the compiler from optimizing out
+*                  the 'const' variables which are declared in this file.
+*              (2) You may decide to 'compile out' the code (by using #if 0/#endif) INSIDE the function 
+*                  if your compiler DOES NOT optimize out the 'const' variables above.
+*********************************************************************************************************
+*/
+
+#if OS_DEBUG_EN > 0
+void  OSDebugInit (void)
+{
+    void  *ptemp;
+
+    
+    ptemp = (void *)&OSDebugEn;
+
+    ptemp = (void *)&OSEndiannessTest;
+
+    ptemp = (void *)&OSEventMax;
+    ptemp = (void *)&OSEventNameSize;
+    ptemp = (void *)&OSEventEn;
+    ptemp = (void *)&OSEventSize;
+    ptemp = (void *)&OSEventTblSize;
+    ptemp = (void *)&OSEventMultiEn;
+
+    ptemp = (void *)&OSFlagEn;
+    ptemp = (void *)&OSFlagGrpSize;
+    ptemp = (void *)&OSFlagNodeSize;
+    ptemp = (void *)&OSFlagWidth;
+    ptemp = (void *)&OSFlagMax;
+    ptemp = (void *)&OSFlagNameSize;
+
+    ptemp = (void *)&OSLowestPrio;
+
+    ptemp = (void *)&OSMboxEn;
+
+    ptemp = (void *)&OSMemEn;
+    ptemp = (void *)&OSMemMax;
+    ptemp = (void *)&OSMemNameSize;
+    ptemp = (void *)&OSMemSize;
+    ptemp = (void *)&OSMemTblSize;
+
+    ptemp = (void *)&OSMutexEn;
+
+    ptemp = (void *)&OSPtrSize;
+
+    ptemp = (void *)&OSQEn;
+    ptemp = (void *)&OSQMax;
+    ptemp = (void *)&OSQSize;
+
+    ptemp = (void *)&OSRdyTblSize;
+
+    ptemp = (void *)&OSSemEn;
+
+    ptemp = (void *)&OSStkWidth;
+
+    ptemp = (void *)&OSTaskCreateEn;
+    ptemp = (void *)&OSTaskCreateExtEn;
+    ptemp = (void *)&OSTaskDelEn;
+    ptemp = (void *)&OSTaskIdleStkSize;
+    ptemp = (void *)&OSTaskProfileEn;
+    ptemp = (void *)&OSTaskMax;
+    ptemp = (void *)&OSTaskNameSize;
+    ptemp = (void *)&OSTaskStatEn;
+    ptemp = (void *)&OSTaskStatStkSize;
+    ptemp = (void *)&OSTaskStatStkChkEn;
+    ptemp = (void *)&OSTaskSwHookEn;
+
+    ptemp = (void *)&OSTCBPrioTblMax;
+    ptemp = (void *)&OSTCBSize;
+
+    ptemp = (void *)&OSTicksPerSec;
+    ptemp = (void *)&OSTimeTickHookEn;
+
+#if OS_TMR_EN > 0
+    ptemp = (void *)&OSTmrTbl[0];
+    ptemp = (void *)&OSTmrWheelTbl[0];
+    
+    ptemp = (void *)&OSTmrEn;
+    ptemp = (void *)&OSTmrCfgMax;
+    ptemp = (void *)&OSTmrCfgNameSize;
+    ptemp = (void *)&OSTmrCfgWheelSize;
+    ptemp = (void *)&OSTmrCfgTicksPerSec;
+    ptemp = (void *)&OSTmrSize;
+    ptemp = (void *)&OSTmrTblSize;
+
+    ptemp = (void *)&OSTmrWheelSize;
+    ptemp = (void *)&OSTmrWheelTblSize;
+#endif
+
+    ptemp = (void *)&OSVersionNbr;
+
+    ptemp = (void *)&OSDataSize;
+
+    ptemp = ptemp;                             /* Prevent compiler warning for 'ptemp' not being used! */
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c
new file mode 100644
index 0000000..b77ef1d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_flag.c
@@ -0,0 +1,1174 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                         EVENT FLAG  MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_FLAG.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+/*
+*********************************************************************************************************
+*                                            LOCAL PROTOTYPES
+*********************************************************************************************************
+*/
+
+static  void     OS_FlagBlock(OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout);
+static  BOOLEAN  OS_FlagTaskRdy(OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy);
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                              CHECK THE STATUS OF FLAGS IN AN EVENT FLAG GROUP
+*
+* Description: This function is called to check the status of a combination of bits to be set or cleared
+*              in an event flag group.  Your application can check for ANY bit to be set/cleared or ALL
+*              bits to be set/cleared.
+*
+*              This call does not block if the desired flags are not present.
+*
+* Arguments  : pgrp          is a pointer to the desired event flag group.
+*
+*              flags         Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check.
+*                            The bits you want are specified by setting the corresponding bits in
+*                            'flags'.  e.g. if your application wants to wait for bits 0 and 1 then
+*                            'flags' would contain 0x03.
+*
+*              wait_type     specifies whether you want ALL bits to be set/cleared or ANY of the bits
+*                            to be set/cleared.
+*                            You can specify the following argument:
+*
+*                            OS_FLAG_WAIT_CLR_ALL   You will check ALL bits in 'flags' to be clear (0)
+*                            OS_FLAG_WAIT_CLR_ANY   You will check ANY bit  in 'flags' to be clear (0)
+*                            OS_FLAG_WAIT_SET_ALL   You will check ALL bits in 'flags' to be set   (1)
+*                            OS_FLAG_WAIT_SET_ANY   You will check ANY bit  in 'flags' to be set   (1)
+*
+*                            NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by
+*                                  the call.  Example, to wait for any flag in a group AND then clear
+*                                  the flags that are present, set 'wait_type' to:
+*
+*                                  OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME
+*
+*              perr          is a pointer to an error code and can be:
+*                            OS_ERR_NONE               No error
+*                            OS_ERR_EVENT_TYPE         You are not pointing to an event flag group
+*                            OS_ERR_FLAG_WAIT_TYPE     You didn't specify a proper 'wait_type' argument.
+*                            OS_ERR_FLAG_INVALID_PGRP  You passed a NULL pointer instead of the event flag
+*                                                      group handle.
+*                            OS_ERR_FLAG_NOT_RDY       The desired flags you are waiting for are not
+*                                                      available.
+*
+* Returns    : The flags in the event flag group that made the task ready or, 0 if a timeout or an error
+*              occurred.
+*
+* Called from: Task or ISR
+*
+* Note(s)    : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions.  The
+*                 function NOW returns the flags that were ready INSTEAD of the current state of the
+*                 event flags.
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_ACCEPT_EN > 0
+OS_FLAGS  OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr)
+{
+    OS_FLAGS      flags_rdy;
+    INT8U         result;
+    BOOLEAN       consume;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return ((OS_FLAGS)0);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((OS_FLAGS)0);
+    }
+    result = (INT8U)(wait_type & OS_FLAG_CONSUME);
+    if (result != (INT8U)0) {                              /* See if we need to consume the flags      */
+        wait_type &= ~OS_FLAG_CONSUME;
+        consume    = OS_TRUE;
+    } else {
+        consume    = OS_FALSE;
+    }
+/*$PAGE*/
+    *perr = OS_ERR_NONE;                                   /* Assume NO error until proven otherwise.  */
+    OS_ENTER_CRITICAL();
+    switch (wait_type) {
+        case OS_FLAG_WAIT_SET_ALL:                         /* See if all required flags are set        */
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);     /* Extract only the bits we want   */
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we wanted      */
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+             }
+             OS_EXIT_CRITICAL();
+             break;
+
+        case OS_FLAG_WAIT_SET_ANY:
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);     /* Extract only the bits we want   */
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag set                      */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we got         */
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+             }
+             OS_EXIT_CRITICAL();
+             break;
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+        case OS_FLAG_WAIT_CLR_ALL:                         /* See if all required flags are cleared    */
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags);  /* Extract only the bits we want     */
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we wanted        */
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+             }
+             OS_EXIT_CRITICAL();
+             break;
+
+        case OS_FLAG_WAIT_CLR_ANY:
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want      */
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag cleared                  */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we got           */
+                 }
+             } else {
+                 *perr = OS_ERR_FLAG_NOT_RDY;
+             }
+             OS_EXIT_CRITICAL();
+             break;
+#endif
+
+        default:
+             OS_EXIT_CRITICAL();
+             flags_rdy = (OS_FLAGS)0;
+             *perr     = OS_ERR_FLAG_WAIT_TYPE;
+             break;
+    }
+    return (flags_rdy);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                           CREATE AN EVENT FLAG
+*
+* Description: This function is called to create an event flag group.
+*
+* Arguments  : flags         Contains the initial value to store in the event flag group.
+*
+*              perr          is a pointer to an error code which will be returned to your application:
+*                               OS_ERR_NONE               if the call was successful.
+*                               OS_ERR_CREATE_ISR         if you attempted to create an Event Flag from an
+*                                                         ISR.
+*                               OS_ERR_FLAG_GRP_DEPLETED  if there are no more event flag groups
+*
+* Returns    : A pointer to an event flag group or a NULL pointer if no more groups are available.
+*
+* Called from: Task ONLY
+*********************************************************************************************************
+*/
+
+OS_FLAG_GRP  *OSFlagCreate (OS_FLAGS flags, INT8U *perr)
+{
+    OS_FLAG_GRP *pgrp;
+#if OS_CRITICAL_METHOD == 3                         /* Allocate storage for CPU status register        */
+    OS_CPU_SR    cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                       /* Validate 'perr'                                 */
+        return ((OS_FLAG_GRP *)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                         /* See if called from ISR ...                      */
+        *perr = OS_ERR_CREATE_ISR;                  /* ... can't CREATE from an ISR                    */
+        return ((OS_FLAG_GRP *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pgrp = OSFlagFreeList;                          /* Get next free event flag                        */
+    if (pgrp != (OS_FLAG_GRP *)0) {                 /* See if we have event flag groups available      */
+                                                    /* Adjust free list                                */
+        OSFlagFreeList       = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList;
+        pgrp->OSFlagType     = OS_EVENT_TYPE_FLAG;  /* Set to event flag group type                    */
+        pgrp->OSFlagFlags    = flags;               /* Set to desired initial value                    */
+        pgrp->OSFlagWaitList = (void *)0;           /* Clear list of tasks waiting on flags            */
+#if OS_FLAG_NAME_SIZE > 1
+        pgrp->OSFlagName[0]  = '?';
+        pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+        OS_EXIT_CRITICAL();
+        *perr                = OS_ERR_NONE;
+    } else {
+        OS_EXIT_CRITICAL();
+        *perr                = OS_ERR_FLAG_GRP_DEPLETED;
+    }
+    return (pgrp);                                  /* Return pointer to event flag group              */
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                     DELETE AN EVENT FLAG GROUP
+*
+* Description: This function deletes an event flag group and readies all tasks pending on the event flag
+*              group.
+*
+* Arguments  : pgrp          is a pointer to the desired event flag group.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Deletes the event flag group ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the event flag group even if tasks are
+*                                                    waiting.  In this case, all the tasks pending will be
+*                                                    readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE               The call was successful and the event flag group was
+*                                                      deleted
+*                            OS_ERR_DEL_ISR            If you attempted to delete the event flag group from
+*                                                      an ISR
+*                            OS_ERR_FLAG_INVALID_PGRP  If 'pgrp' is a NULL pointer.
+*                            OS_ERR_EVENT_TYPE         If you didn't pass a pointer to an event flag group
+*                            OS_ERR_INVALID_OPT        An invalid option was specified
+*                            OS_ERR_TASK_WAITING       One or more tasks were waiting on the event flag
+*                                                      group.
+*
+* Returns    : pgrp          upon error
+*              (OS_EVENT *)0 if the event flag group was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the event flag group MUST check the return code of OSFlagAccept() and OSFlagPend().
+*              2) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the event flag group.
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_DEL_EN > 0
+OS_FLAG_GRP  *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr)
+{
+    BOOLEAN       tasks_waiting;
+    OS_FLAG_NODE *pnode;
+    OS_FLAG_GRP  *pgrp_return;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (pgrp);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return (pgrp);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        return (pgrp);
+    }
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event group type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (pgrp);
+    }
+    OS_ENTER_CRITICAL();
+    if (pgrp->OSFlagWaitList != (void *)0) {               /* See if any tasks waiting on event flags  */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete group if no task waiting          */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_FLAG_NAME_SIZE > 1
+                 pgrp->OSFlagName[0]  = '?';               /* Unknown name                             */
+                 pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+                 pgrp->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+                 pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list           */
+                 pgrp->OSFlagFlags    = (OS_FLAGS)0;
+                 OSFlagFreeList       = pgrp;
+                 OS_EXIT_CRITICAL();
+                 *perr                = OS_ERR_NONE;
+                 pgrp_return          = (OS_FLAG_GRP *)0;  /* Event Flag Group has been deleted        */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                = OS_ERR_TASK_WAITING;
+                 pgrp_return          = pgrp;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the event flag group       */
+             pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+             while (pnode != (OS_FLAG_NODE *)0) {          /* Ready ALL tasks waiting for flags        */
+                 (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0);
+                 pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext;
+             }
+#if OS_FLAG_NAME_SIZE > 1
+             pgrp->OSFlagName[0]  = '?';                   /* Unknown name                             */
+             pgrp->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+             pgrp->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+             pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list                */
+             pgrp->OSFlagFlags    = (OS_FLAGS)0;
+             OSFlagFreeList       = pgrp;
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr = OS_ERR_NONE;
+             pgrp_return          = (OS_FLAG_GRP *)0;      /* Event Flag Group has been deleted        */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                = OS_ERR_INVALID_OPT;
+             pgrp_return          = pgrp;
+             break;
+    }
+    return (pgrp_return);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                 GET THE NAME OF AN EVENT FLAG GROUP
+*
+* Description: This function is used to obtain the name assigned to an event flag group
+*
+* Arguments  : pgrp      is a pointer to the event flag group.
+*
+*              pname     is a pointer to an ASCII string that will receive the name of the event flag
+*                        group.  The string must be able to hold at least OS_FLAG_NAME_SIZE characters.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the requested task is resumed
+*                        OS_ERR_EVENT_TYPE          if 'pevent' is not pointing to an event flag group
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_FLAG_INVALID_PGRP   if you passed a NULL pointer for 'pgrp'
+*                        OS_ERR_NAME_GET_ISR        if you called this function from an ISR
+*
+* Returns    : The length of the string or 0 if the 'pgrp' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_NAME_SIZE > 1
+INT8U  OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return (0);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {              /* Is 'pgrp' a NULL pointer?                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return (0);
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_GET_ISR;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0);
+    }
+    len   = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP                         */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (len);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                 ASSIGN A NAME TO AN EVENT FLAG GROUP
+*
+* Description: This function assigns a name to an event flag group.
+*
+* Arguments  : pgrp      is a pointer to the event flag group.
+*
+*              pname     is a pointer to an ASCII string that will be used as the name of the event flag
+*                        group.  The string must be able to hold at least OS_FLAG_NAME_SIZE characters.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the requested task is resumed
+*                        OS_ERR_EVENT_TYPE          if 'pevent' is not pointing to an event flag group
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_FLAG_INVALID_PGRP   if you passed a NULL pointer for 'pgrp'
+*                        OS_ERR_NAME_SET_ISR        if you called this function from an ISR
+*
+* Returns    : None
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_NAME_SIZE > 1
+void  OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return;
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {              /* Is 'pgrp' a NULL pointer?                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return;
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_SET_ISR;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_EVENT_TYPE;
+        return;
+    }
+    len = OS_StrLen(pname);                      /* Can we fit the string in the storage area?         */
+    if (len > (OS_FLAG_NAME_SIZE - 1)) {         /* No                                                 */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_FLAG_NAME_TOO_LONG;
+        return;
+    }
+    (void)OS_StrCopy(pgrp->OSFlagName, pname);   /* Yes, copy name from OS_FLAG_GRP                    */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return;
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        WAIT ON AN EVENT FLAG GROUP
+*
+* Description: This function is called to wait for a combination of bits to be set in an event flag
+*              group.  Your application can wait for ANY bit to be set or ALL bits to be set.
+*
+* Arguments  : pgrp          is a pointer to the desired event flag group.
+*
+*              flags         Is a bit pattern indicating which bit(s) (i.e. flags) you wish to wait for.
+*                            The bits you want are specified by setting the corresponding bits in
+*                            'flags'.  e.g. if your application wants to wait for bits 0 and 1 then
+*                            'flags' would contain 0x03.
+*
+*              wait_type     specifies whether you want ALL bits to be set or ANY of the bits to be set.
+*                            You can specify the following argument:
+*
+*                            OS_FLAG_WAIT_CLR_ALL   You will wait for ALL bits in 'mask' to be clear (0)
+*                            OS_FLAG_WAIT_SET_ALL   You will wait for ALL bits in 'mask' to be set   (1)
+*                            OS_FLAG_WAIT_CLR_ANY   You will wait for ANY bit  in 'mask' to be clear (0)
+*                            OS_FLAG_WAIT_SET_ANY   You will wait for ANY bit  in 'mask' to be set   (1)
+*
+*                            NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by
+*                                  the call.  Example, to wait for any flag in a group AND then clear
+*                                  the flags that are present, set 'wait_type' to:
+*
+*                                  OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME
+*
+*              timeout       is an optional timeout (in clock ticks) that your task will wait for the
+*                            desired bit combination.  If you specify 0, however, your task will wait
+*                            forever at the specified event flag group or, until a message arrives.
+*
+*              perr          is a pointer to an error code and can be:
+*                            OS_ERR_NONE               The desired bits have been set within the specified
+*                                                      'timeout'.
+*                            OS_ERR_PEND_ISR           If you tried to PEND from an ISR
+*                            OS_ERR_FLAG_INVALID_PGRP  If 'pgrp' is a NULL pointer.
+*                            OS_ERR_EVENT_TYPE         You are not pointing to an event flag group
+*                            OS_ERR_TIMEOUT            The bit(s) have not been set in the specified
+*                                                      'timeout'.
+*                            OS_ERR_PEND_ABORT         The wait on the flag was aborted.
+*                            OS_ERR_FLAG_WAIT_TYPE     You didn't specify a proper 'wait_type' argument.
+*
+* Returns    : The flags in the event flag group that made the task ready or, 0 if a timeout or an error
+*              occurred.
+*
+* Called from: Task ONLY
+*
+* Note(s)    : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions.  The
+*                 function NOW returns the flags that were ready INSTEAD of the current state of the
+*                 event flags.
+*********************************************************************************************************
+*/
+
+OS_FLAGS  OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr)
+{
+    OS_FLAG_NODE  node;
+    OS_FLAGS      flags_rdy;
+    INT8U         result;
+    INT8U         pend_stat;
+    BOOLEAN       consume;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return ((OS_FLAGS)0);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {                        /* Validate 'pgrp'                          */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_PEND_ISR;                           /* ... can't PEND from an ISR               */
+        return ((OS_FLAGS)0);
+    }
+    if (OSLockNesting > 0) {                               /* See if called with scheduler locked ...  */
+        *perr = OS_ERR_PEND_LOCKED;                        /* ... can't PEND when locked               */
+        return ((OS_FLAGS)0);
+    }
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((OS_FLAGS)0);
+    }
+    result = (INT8U)(wait_type & OS_FLAG_CONSUME);
+    if (result != (INT8U)0) {                             /* See if we need to consume the flags      */
+        wait_type &= ~(INT8U)OS_FLAG_CONSUME;
+        consume    = OS_TRUE;
+    } else {
+        consume    = OS_FALSE;
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+    switch (wait_type) {
+        case OS_FLAG_WAIT_SET_ALL:                         /* See if all required flags are set        */
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);   /* Extract only the bits we want     */
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we wanted      */
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+                 return (flags_rdy);
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+
+        case OS_FLAG_WAIT_SET_ANY:
+             flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags);    /* Extract only the bits we want    */
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag set                      */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags &= ~flags_rdy;      /* Clear ONLY the flags that we got         */
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+                 return (flags_rdy);
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+        case OS_FLAG_WAIT_CLR_ALL:                         /* See if all required flags are cleared    */
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags);  /* Extract only the bits we want     */
+             if (flags_rdy == flags) {                     /* Must match ALL the bits that we want     */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we wanted        */
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+                 return (flags_rdy);
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+
+        case OS_FLAG_WAIT_CLR_ANY:
+             flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want      */
+             if (flags_rdy != (OS_FLAGS)0) {               /* See if any flag cleared                  */
+                 if (consume == OS_TRUE) {                 /* See if we need to consume the flags      */
+                     pgrp->OSFlagFlags |= flags_rdy;       /* Set ONLY the flags that we got           */
+                 }
+                 OSTCBCur->OSTCBFlagsRdy = flags_rdy;      /* Save flags that were ready               */
+                 OS_EXIT_CRITICAL();                       /* Yes, condition met, return to caller     */
+                 *perr                   = OS_ERR_NONE;
+                 return (flags_rdy);
+             } else {                                      /* Block task until events occur or timeout */
+                 OS_FlagBlock(pgrp, &node, flags, wait_type, timeout);
+                 OS_EXIT_CRITICAL();
+             }
+             break;
+#endif
+
+        default:
+             OS_EXIT_CRITICAL();
+             flags_rdy = (OS_FLAGS)0;
+             *perr      = OS_ERR_FLAG_WAIT_TYPE;
+             return (flags_rdy);
+    }
+/*$PAGE*/
+    OS_Sched();                                            /* Find next HPT ready to run               */
+    OS_ENTER_CRITICAL();
+    if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) {      /* Have we timed-out or aborted?            */
+        pend_stat                = OSTCBCur->OSTCBStatPend;
+        OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+        OS_FlagUnlink(&node);
+        OSTCBCur->OSTCBStat      = OS_STAT_RDY;            /* Yes, make task ready-to-run              */
+        OS_EXIT_CRITICAL();
+        flags_rdy                = (OS_FLAGS)0;
+        switch (pend_stat) {
+            case OS_STAT_PEND_ABORT:
+                 *perr = OS_ERR_PEND_ABORT;                 /* Indicate that we aborted   waiting       */
+                 break;
+
+            case OS_STAT_PEND_TO:
+            default:
+                 *perr = OS_ERR_TIMEOUT;                    /* Indicate that we timed-out waiting       */
+                 break;
+        }
+        return (flags_rdy);
+    }
+    flags_rdy = OSTCBCur->OSTCBFlagsRdy;
+    if (consume == OS_TRUE) {                              /* See if we need to consume the flags      */
+        switch (wait_type) {
+            case OS_FLAG_WAIT_SET_ALL:
+            case OS_FLAG_WAIT_SET_ANY:                     /* Clear ONLY the flags we got              */
+                 pgrp->OSFlagFlags &= ~flags_rdy;
+                 break;
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+            case OS_FLAG_WAIT_CLR_ALL:
+            case OS_FLAG_WAIT_CLR_ANY:                     /* Set   ONLY the flags we got              */
+                 pgrp->OSFlagFlags |=  flags_rdy;
+                 break;
+#endif
+            default:
+                 OS_EXIT_CRITICAL();
+                 *perr = OS_ERR_FLAG_WAIT_TYPE;
+                 return ((OS_FLAGS)0);
+        }
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;                                   /* Event(s) must have occurred              */
+    return (flags_rdy);
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                               GET FLAGS WHO CAUSED TASK TO BECOME READY
+*
+* Description: This function is called to obtain the flags that caused the task to become ready to run.
+*              In other words, this function allows you to tell "Who done it!".
+*
+* Arguments  : None
+*
+* Returns    : The flags that caused the task to be ready.
+*
+* Called from: Task ONLY
+*********************************************************************************************************
+*/
+
+OS_FLAGS  OSFlagPendGetFlagsRdy (void)
+{
+    OS_FLAGS      flags;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    flags = OSTCBCur->OSTCBFlagsRdy;
+    OS_EXIT_CRITICAL();
+    return (flags);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         POST EVENT FLAG BIT(S)
+*
+* Description: This function is called to set or clear some bits in an event flag group.  The bits to
+*              set or clear are specified by a 'bit mask'.
+*
+* Arguments  : pgrp          is a pointer to the desired event flag group.
+*
+*              flags         If 'opt' (see below) is OS_FLAG_SET, each bit that is set in 'flags' will
+*                            set the corresponding bit in the event flag group.  e.g. to set bits 0, 4
+*                            and 5 you would set 'flags' to:
+*
+*                                0x31     (note, bit 0 is least significant bit)
+*
+*                            If 'opt' (see below) is OS_FLAG_CLR, each bit that is set in 'flags' will
+*                            CLEAR the corresponding bit in the event flag group.  e.g. to clear bits 0,
+*                            4 and 5 you would specify 'flags' as:
+*
+*                                0x31     (note, bit 0 is least significant bit)
+*
+*              opt           indicates whether the flags will be:
+*                                set     (OS_FLAG_SET) or
+*                                cleared (OS_FLAG_CLR)
+*
+*              perr          is a pointer to an error code and can be:
+*                            OS_ERR_NONE                The call was successfull
+*                            OS_ERR_FLAG_INVALID_PGRP   You passed a NULL pointer
+*                            OS_ERR_EVENT_TYPE          You are not pointing to an event flag group
+*                            OS_ERR_FLAG_INVALID_OPT    You specified an invalid option
+*
+* Returns    : the new value of the event flags bits that are still set.
+*
+* Called From: Task or ISR
+*
+* WARNING(s) : 1) The execution time of this function depends on the number of tasks waiting on the event
+*                 flag group.
+*              2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on
+*                 the event flag group.
+*********************************************************************************************************
+*/
+OS_FLAGS  OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr)
+{
+    OS_FLAG_NODE *pnode;
+    BOOLEAN       sched;
+    OS_FLAGS      flags_cur;
+    OS_FLAGS      flags_rdy;
+    BOOLEAN       rdy;
+#if OS_CRITICAL_METHOD == 3                          /* Allocate storage for CPU status register       */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                        /* Validate 'perr'                                */
+        return ((OS_FLAGS)0);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {                  /* Validate 'pgrp'                                */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) {    /* Make sure we are pointing to an event flag grp */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((OS_FLAGS)0);
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+    switch (opt) {
+        case OS_FLAG_CLR:
+             pgrp->OSFlagFlags &= ~flags;            /* Clear the flags specified in the group         */
+             break;
+
+        case OS_FLAG_SET:
+             pgrp->OSFlagFlags |=  flags;            /* Set   the flags specified in the group         */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();                     /* INVALID option                                 */
+             *perr = OS_ERR_FLAG_INVALID_OPT;
+             return ((OS_FLAGS)0);
+    }
+    sched = OS_FALSE;                                /* Indicate that we don't need rescheduling       */
+    pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+    while (pnode != (OS_FLAG_NODE *)0) {             /* Go through all tasks waiting on event flag(s)  */
+        switch (pnode->OSFlagNodeWaitType) {
+            case OS_FLAG_WAIT_SET_ALL:               /* See if all req. flags are set for current node */
+                 flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+                 if (flags_rdy == pnode->OSFlagNodeFlags) {
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+                     if (rdy == OS_TRUE) {
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+                     }
+                 }
+                 break;
+
+            case OS_FLAG_WAIT_SET_ANY:               /* See if any flag set                            */
+                 flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+                 if (flags_rdy != (OS_FLAGS)0) {
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+                     if (rdy == OS_TRUE) {
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+                     }
+                 }
+                 break;
+
+#if OS_FLAG_WAIT_CLR_EN > 0
+            case OS_FLAG_WAIT_CLR_ALL:               /* See if all req. flags are set for current node */
+                 flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+                 if (flags_rdy == pnode->OSFlagNodeFlags) {
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+                     if (rdy == OS_TRUE) {
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+                     }
+                 }
+                 break;
+
+            case OS_FLAG_WAIT_CLR_ANY:               /* See if any flag set                            */
+                 flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags);
+                 if (flags_rdy != (OS_FLAGS)0) {
+                     rdy = OS_FlagTaskRdy(pnode, flags_rdy);  /* Make task RTR, event(s) Rx'd          */
+                     if (rdy == OS_TRUE) {
+                         sched = OS_TRUE;                     /* When done we will reschedule          */
+                     }
+                 }
+                 break;
+#endif
+            default:
+                 OS_EXIT_CRITICAL();
+                 *perr = OS_ERR_FLAG_WAIT_TYPE;
+                 return ((OS_FLAGS)0);
+        }
+        pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */
+    }
+    OS_EXIT_CRITICAL();
+    if (sched == OS_TRUE) {
+        OS_Sched();
+    }
+    OS_ENTER_CRITICAL();
+    flags_cur = pgrp->OSFlagFlags;
+    OS_EXIT_CRITICAL();
+    *perr     = OS_ERR_NONE;
+    return (flags_cur);
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                           QUERY EVENT FLAG
+*
+* Description: This function is used to check the value of the event flag group.
+*
+* Arguments  : pgrp         is a pointer to the desired event flag group.
+*
+*              perr          is a pointer to an error code returned to the called:
+*                            OS_ERR_NONE                The call was successfull
+*                            OS_ERR_FLAG_INVALID_PGRP   You passed a NULL pointer
+*                            OS_ERR_EVENT_TYPE          You are not pointing to an event flag group
+*
+* Returns    : The current value of the event flag group.
+*
+* Called From: Task or ISR
+*********************************************************************************************************
+*/
+
+#if OS_FLAG_QUERY_EN > 0
+OS_FLAGS  OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr)
+{
+    OS_FLAGS   flags;
+#if OS_CRITICAL_METHOD == 3                       /* Allocate storage for CPU status register          */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                     /* Validate 'perr'                                   */
+        return ((OS_FLAGS)0);
+    }
+    if (pgrp == (OS_FLAG_GRP *)0) {               /* Validate 'pgrp'                                   */
+        *perr = OS_ERR_FLAG_INVALID_PGRP;
+        return ((OS_FLAGS)0);
+    }
+#endif
+    if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type                         */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((OS_FLAGS)0);
+    }
+    OS_ENTER_CRITICAL();
+    flags = pgrp->OSFlagFlags;
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (flags);                               /* Return the current value of the event flags       */
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                         SUSPEND TASK UNTIL EVENT FLAG(s) RECEIVED OR TIMEOUT OCCURS
+*
+* Description: This function is internal to uC/OS-II and is used to put a task to sleep until the desired
+*              event flag bit(s) are set.
+*
+* Arguments  : pgrp          is a pointer to the desired event flag group.
+*
+*              pnode         is a pointer to a structure which contains data about the task waiting for
+*                            event flag bit(s) to be set.
+*
+*              flags         Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check.
+*                            The bits you want are specified by setting the corresponding bits in
+*                            'flags'.  e.g. if your application wants to wait for bits 0 and 1 then
+*                            'flags' would contain 0x03.
+*
+*              wait_type     specifies whether you want ALL bits to be set/cleared or ANY of the bits
+*                            to be set/cleared.
+*                            You can specify the following argument:
+*
+*                            OS_FLAG_WAIT_CLR_ALL   You will check ALL bits in 'mask' to be clear (0)
+*                            OS_FLAG_WAIT_CLR_ANY   You will check ANY bit  in 'mask' to be clear (0)
+*                            OS_FLAG_WAIT_SET_ALL   You will check ALL bits in 'mask' to be set   (1)
+*                            OS_FLAG_WAIT_SET_ANY   You will check ANY bit  in 'mask' to be set   (1)
+*
+*              timeout       is the desired amount of time that the task will wait for the event flag
+*                            bit(s) to be set.
+*
+* Returns    : none
+*
+* Called by  : OSFlagPend()  OS_FLAG.C
+*
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+static  void  OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout)
+{
+    OS_FLAG_NODE  *pnode_next;
+    INT8U          y;
+
+
+    OSTCBCur->OSTCBStat      |= OS_STAT_FLAG;
+    OSTCBCur->OSTCBStatPend   = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly        = timeout;              /* Store timeout in task's TCB                   */
+#if OS_TASK_DEL_EN > 0
+    OSTCBCur->OSTCBFlagNode   = pnode;                /* TCB to link to node                           */
+#endif
+    pnode->OSFlagNodeFlags    = flags;                /* Save the flags that we need to wait for       */
+    pnode->OSFlagNodeWaitType = wait_type;            /* Save the type of wait we are doing            */
+    pnode->OSFlagNodeTCB      = (void *)OSTCBCur;     /* Link to task's TCB                            */
+    pnode->OSFlagNodeNext     = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */
+    pnode->OSFlagNodePrev     = (void *)0;
+    pnode->OSFlagNodeFlagGrp  = (void *)pgrp;         /* Link to Event Flag Group                      */
+    pnode_next                = (OS_FLAG_NODE *)pgrp->OSFlagWaitList;
+    if (pnode_next != (void *)0) {                    /* Is this the first NODE to insert?             */
+        pnode_next->OSFlagNodePrev = pnode;           /* No, link in doubly linked list                */
+    }
+    pgrp->OSFlagWaitList = (void *)pnode;
+
+    y            =  OSTCBCur->OSTCBY;                 /* Suspend current task until flag(s) received   */
+    OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX;
+    if (OSRdyTbl[y] == 0x00) {
+        OSRdyGrp &= ~OSTCBCur->OSTCBBitY;
+    }
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                    INITIALIZE THE EVENT FLAG MODULE
+*
+* Description: This function is called by uC/OS-II to initialize the event flag module.  Your application
+*              MUST NOT call this function.  In other words, this function is internal to uC/OS-II.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* WARNING    : You MUST NOT call this function from your code.  This is an INTERNAL function to uC/OS-II.
+*********************************************************************************************************
+*/
+
+void  OS_FlagInit (void)
+{
+#if OS_MAX_FLAGS == 1
+    OSFlagFreeList                 = (OS_FLAG_GRP *)&OSFlagTbl[0];  /* Only ONE event flag group!      */
+    OSFlagFreeList->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+    OSFlagFreeList->OSFlagWaitList = (void *)0;
+    OSFlagFreeList->OSFlagFlags    = (OS_FLAGS)0;
+#if OS_FLAG_NAME_SIZE > 1
+    OSFlagFreeList->OSFlagName[0]  = '?';
+    OSFlagFreeList->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+#endif
+
+#if OS_MAX_FLAGS >= 2
+    INT16U       i;
+    OS_FLAG_GRP *pgrp1;
+    OS_FLAG_GRP *pgrp2;
+
+
+    OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl));           /* Clear the flag group table      */
+    pgrp1 = &OSFlagTbl[0];
+    pgrp2 = &OSFlagTbl[1];
+    for (i = 0; i < (OS_MAX_FLAGS - 1); i++) {                      /* Init. list of free EVENT FLAGS  */
+        pgrp1->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+        pgrp1->OSFlagWaitList = (void *)pgrp2;
+#if OS_FLAG_NAME_SIZE > 1
+        pgrp1->OSFlagName[0]  = '?';                                /* Unknown name                    */
+        pgrp1->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+        pgrp1++;
+        pgrp2++;
+    }
+    pgrp1->OSFlagType     = OS_EVENT_TYPE_UNUSED;
+    pgrp1->OSFlagWaitList = (void *)0;
+#if OS_FLAG_NAME_SIZE > 1
+    pgrp1->OSFlagName[0]  = '?';                                    /* Unknown name                    */
+    pgrp1->OSFlagName[1]  = OS_ASCII_NUL;
+#endif
+    OSFlagFreeList        = &OSFlagTbl[0];
+#endif
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                              MAKE TASK READY-TO-RUN, EVENT(s) OCCURRED
+*
+* Description: This function is internal to uC/OS-II and is used to make a task ready-to-run because the
+*              desired event flag bits have been set.
+*
+* Arguments  : pnode         is a pointer to a structure which contains data about the task waiting for
+*                            event flag bit(s) to be set.
+*
+*              flags_rdy     contains the bit pattern of the event flags that cause the task to become
+*                            ready-to-run.
+*
+* Returns    : OS_TRUE       If the task has been placed in the ready list and thus needs scheduling
+*              OS_FALSE      The task is still not ready to run and thus scheduling is not necessary
+*
+* Called by  : OSFlagsPost() OS_FLAG.C
+*
+* Note(s)    : 1) This function assumes that interrupts are disabled.
+*              2) This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+static  BOOLEAN  OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy)
+{
+    OS_TCB   *ptcb;
+    BOOLEAN   sched;
+
+
+    ptcb                 = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task             */
+    ptcb->OSTCBDly       = 0;
+    ptcb->OSTCBFlagsRdy  = flags_rdy;
+    ptcb->OSTCBStat     &= ~(INT8U)OS_STAT_FLAG;
+    ptcb->OSTCBStatPend  = OS_STAT_PEND_OK;
+    if (ptcb->OSTCBStat == OS_STAT_RDY) {                  /* Task now ready?                          */
+        OSRdyGrp               |= ptcb->OSTCBBitY;         /* Put task into ready list                 */
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+        sched                   = OS_TRUE;
+    } else {
+        sched                   = OS_FALSE;
+    }
+    OS_FlagUnlink(pnode);
+    return (sched);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                  UNLINK EVENT FLAG NODE FROM WAITING LIST
+*
+* Description: This function is internal to uC/OS-II and is used to unlink an event flag node from a
+*              list of tasks waiting for the event flag.
+*
+* Arguments  : pnode         is a pointer to a structure which contains data about the task waiting for
+*                            event flag bit(s) to be set.
+*
+* Returns    : none
+*
+* Called by  : OS_FlagTaskRdy() OS_FLAG.C
+*              OSFlagPend()     OS_FLAG.C
+*              OSTaskDel()      OS_TASK.C
+*
+* Note(s)    : 1) This function assumes that interrupts are disabled.
+*              2) This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_FlagUnlink (OS_FLAG_NODE *pnode)
+{
+#if OS_TASK_DEL_EN > 0
+    OS_TCB       *ptcb;
+#endif
+    OS_FLAG_GRP  *pgrp;
+    OS_FLAG_NODE *pnode_prev;
+    OS_FLAG_NODE *pnode_next;
+
+
+    pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev;
+    pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext;
+    if (pnode_prev == (OS_FLAG_NODE *)0) {                      /* Is it first node in wait list?      */
+        pgrp                 = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp;
+        pgrp->OSFlagWaitList = (void *)pnode_next;              /*      Update list for new 1st node   */
+        if (pnode_next != (OS_FLAG_NODE *)0) {
+            pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0;     /*      Link new 1st node PREV to NULL */
+        }
+    } else {                                                    /* No,  A node somewhere in the list   */
+        pnode_prev->OSFlagNodeNext = pnode_next;                /*      Link around the node to unlink */
+        if (pnode_next != (OS_FLAG_NODE *)0) {                  /*      Was this the LAST node?        */
+            pnode_next->OSFlagNodePrev = pnode_prev;            /*      No, Link around current node   */
+        }
+    }
+#if OS_TASK_DEL_EN > 0
+    ptcb                = (OS_TCB *)pnode->OSFlagNodeTCB;
+    ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0;
+#endif
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c
new file mode 100644
index 0000000..0ee0c51
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mbox.c
@@ -0,0 +1,629 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                       MESSAGE MAILBOX MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_MBOX.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if OS_MBOX_EN > 0
+/*
+*********************************************************************************************************
+*                                     ACCEPT MESSAGE FROM MAILBOX
+*
+* Description: This function checks the mailbox to see if a message is available.  Unlike OSMboxPend(),
+*              OSMboxAccept() does not suspend the calling task if a message is not available.
+*
+* Arguments  : pevent        is a pointer to the event control block
+*
+* Returns    : != (void *)0  is the message in the mailbox if one is available.  The mailbox is cleared
+*                            so the next time OSMboxAccept() is called, the mailbox will be empty.
+*              == (void *)0  if the mailbox is empty or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass the proper event pointer.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_ACCEPT_EN > 0
+void  *OSMboxAccept (OS_EVENT *pevent)
+{
+    void      *pmsg;
+#if OS_CRITICAL_METHOD == 3                               /* Allocate storage for CPU status register  */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                        /* Validate 'pevent'                         */
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {      /* Validate event block type                 */
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pmsg               = pevent->OSEventPtr;
+    pevent->OSEventPtr = (void *)0;                       /* Clear the mailbox                         */
+    OS_EXIT_CRITICAL();
+    return (pmsg);                                        /* Return the message received (or NULL)     */
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        CREATE A MESSAGE MAILBOX
+*
+* Description: This function creates a message mailbox if free event control blocks are available.
+*
+* Arguments  : pmsg          is a pointer to a message that you wish to deposit in the mailbox.  If
+*                            you set this value to the NULL pointer (i.e. (void *)0) then the mailbox
+*                            will be considered empty.
+*
+* Returns    : != (OS_EVENT *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                                created mailbox
+*              == (OS_EVENT *)0  if no event control blocks were available
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSMboxCreate (void *pmsg)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                      /* See if called from ISR ...                         */
+        return ((OS_EVENT *)0);                  /* ... can't CREATE from an ISR                       */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                    /* Get next free event control block                  */
+    if (OSEventFreeList != (OS_EVENT *)0) {      /* See if pool of free ECB pool was empty             */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {
+        pevent->OSEventType    = OS_EVENT_TYPE_MBOX;
+        pevent->OSEventCnt     = 0;
+        pevent->OSEventPtr     = pmsg;           /* Deposit message in event control block             */
+#if OS_EVENT_NAME_SIZE > 1
+        pevent->OSEventName[0] = '?';
+        pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+        OS_EventWaitListInit(pevent);
+    }
+    return (pevent);                             /* Return pointer to event control block              */
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         DELETE A MAIBOX
+*
+* Description: This function deletes a mailbox and readies all tasks pending on the mailbox.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            mailbox.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete the mailbox ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the mailbox even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE             The call was successful and the mailbox was deleted
+*                            OS_ERR_DEL_ISR          If you attempted to delete the mailbox from an ISR
+*                            OS_ERR_INVALID_OPT      An invalid option was specified
+*                            OS_ERR_TASK_WAITING     One or more tasks were waiting on the mailbox
+*                            OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a mailbox
+*                            OS_ERR_PEVENT_NULL      If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the mailbox was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the mailbox MUST check the return code of OSMboxPend().
+*              2) OSMboxAccept() callers will not know that the intended mailbox has been deleted!
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the mailbox.
+*              4) Because ALL tasks pending on the mailbox will be readied, you MUST be careful in
+*                 applications where the mailbox is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the mailbox.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_DEL_EN > 0
+OS_EVENT  *OSMboxDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (pevent);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (pevent);
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on mailbox      */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete mailbox only if no task waiting   */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+                 pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr  = OSEventFreeList;    /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt  = 0;
+                 OSEventFreeList     = pevent;             /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_NONE;
+                 pevent_return       = (OS_EVENT *)0;      /* Mailbox has been deleted                 */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_TASK_WAITING;
+                 pevent_return       = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the mailbox                */
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for mailbox      */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_OK);
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr         = OS_ERR_NONE;
+             pevent_return = (OS_EVENT *)0;                /* Mailbox has been deleted                 */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr         = OS_ERR_INVALID_OPT;
+             pevent_return = pevent;
+             break;
+    }
+    return (pevent_return);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      PEND ON MAILBOX FOR A MESSAGE
+*
+* Description: This function waits for a message to be sent to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for a message to arrive at the mailbox up to the amount of time
+*                            specified by this argument.  If you specify 0, however, your task will wait
+*                            forever at the specified mailbox or, until a message arrives.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_TIMEOUT      A message was not received within the specified 'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the mailbox was aborted.
+*                            OS_ERR_EVENT_TYPE   Invalid event type
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_PEND_LOCKED  If you called this function when the scheduler is locked
+*
+* Returns    : != (void *)0  is a pointer to the message received
+*              == (void *)0  if no message was received or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass the proper pointer to the event control block.
+*********************************************************************************************************
+*/
+/*$PAGE*/
+void  *OSMboxPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+    void      *pmsg;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return ((void *)0);
+    }
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((void *)0);
+    }
+    if (OSIntNesting > 0) {                           /* See if called from ISR ...                    */
+        *perr = OS_ERR_PEND_ISR;                      /* ... can't PEND from an ISR                    */
+        return ((void *)0);
+    }
+    if (OSLockNesting > 0) {                          /* See if called with scheduler locked ...       */
+        *perr = OS_ERR_PEND_LOCKED;                   /* ... can't PEND when locked                    */
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pmsg = pevent->OSEventPtr;
+    if (pmsg != (void *)0) {                          /* See if there is already a message             */
+        pevent->OSEventPtr = (void *)0;               /* Clear the mailbox                             */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        return (pmsg);                                /* Return the message received (or NULL)         */
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_MBOX;          /* Message not available, task will pend         */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Load timeout in TCB                           */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready to run  */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             pmsg =  OSTCBCur->OSTCBMsg;
+            *perr =  OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             pmsg = (void *)0;
+            *perr =  OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             pmsg = (void *)0;
+            *perr =  OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+#endif
+    OSTCBCur->OSTCBMsg           = (void      *)0;    /* Clear  received message                       */
+    OS_EXIT_CRITICAL();
+    return (pmsg);                                    /* Return received message                       */
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      ABORT WAITING ON A MESSAGE MAILBOX
+*
+* Description: This function aborts & readies any tasks currently waiting on a mailbox.  This function 
+*              should be used to fault-abort the wait on the mailbox, rather than to normally signal
+*              the mailbox via OSMboxPost() or OSMboxPostOpt().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     mailbox
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     mailbox
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the mailbox.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the mailbox was readied
+*                                                and informed of the aborted wait; check return value 
+*                                                for the number of tasks whose wait on the mailbox 
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a mailbox.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the mailbox, or upon error.
+*              >  0          if one or more tasks waiting on the mailbox are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_PEND_ABORT_EN > 0
+INT8U  OSMboxPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (0);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any task waiting on mailbox?      */
+        nbr_tasks = 0;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:                    /* Do we need to abort ALL waiting tasks?   */
+                 while (pevent->OSEventGrp != 0) {         /* Yes, ready ALL tasks waiting on mailbox  */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+             
+            case OS_PEND_OPT_NONE:
+            default:                                       /* No,  ready HPT       waiting on mailbox  */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                        /* Find HPT ready to run                    */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0);                                            /* No tasks waiting on mailbox              */
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                       POST MESSAGE TO A MAILBOX
+*
+* Description: This function sends a message to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              pmsg          is a pointer to the message to send.  You MUST NOT send a NULL pointer.
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_MBOX_FULL     If the mailbox already contains a message.  You can can only send one
+*                                   message at a time and thus, the message MUST be consumed before you
+*                                   are allowed to send another one.
+*              OS_ERR_EVENT_TYPE    If you are attempting to post to a non mailbox.
+*              OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer
+*              OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer
+*
+* Note(s)    : 1) HPT means Highest Priority Task
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_POST_EN > 0
+INT8U  OSMboxPost (OS_EVENT *pevent, void *pmsg)
+{
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pmsg == (void *)0) {                          /* Make sure we are not posting a NULL pointer   */
+        return (OS_ERR_POST_NULL_PTR);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                    /* See if any task pending on mailbox            */
+                                                      /* Ready HPT waiting on event                    */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find highest priority task ready to run       */
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventPtr != (void *)0) {            /* Make sure mailbox doesn't already have a msg  */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_MBOX_FULL);
+    }
+    pevent->OSEventPtr = pmsg;                        /* Place message in mailbox                      */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                       POST MESSAGE TO A MAILBOX
+*
+* Description: This function sends a message to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              pmsg          is a pointer to the message to send.  You MUST NOT send a NULL pointer.
+*
+*              opt           determines the type of POST performed:
+*                            OS_POST_OPT_NONE         POST to a single waiting task
+*                                                     (Identical to OSMboxPost())
+*                            OS_POST_OPT_BROADCAST    POST to ALL tasks that are waiting on the mailbox
+*
+*                            OS_POST_OPT_NO_SCHED     Indicates that the scheduler will NOT be invoked
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_MBOX_FULL     If the mailbox already contains a message.  You can can only send one
+*                                   message at a time and thus, the message MUST be consumed before you
+*                                   are allowed to send another one.
+*              OS_ERR_EVENT_TYPE    If you are attempting to post to a non mailbox.
+*              OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer
+*              OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer
+*
+* Note(s)    : 1) HPT means Highest Priority Task
+*
+* Warning    : Interrupts can be disabled for a long time if you do a 'broadcast'.  In fact, the
+*              interrupt disable time is proportional to the number of tasks waiting on the mailbox.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_POST_OPT_EN > 0
+INT8U  OSMboxPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt)
+{
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pmsg == (void *)0) {                          /* Make sure we are not posting a NULL pointer   */
+        return (OS_ERR_POST_NULL_PTR);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                    /* See if any task pending on mailbox            */
+        if ((opt & OS_POST_OPT_BROADCAST) != 0x00) {  /* Do we need to post msg to ALL waiting tasks ? */
+            while (pevent->OSEventGrp != 0) {         /* Yes, Post to ALL tasks waiting on mailbox     */
+                (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+            }
+        } else {                                      /* No,  Post to HPT waiting on mbox              */
+            (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+        }
+        OS_EXIT_CRITICAL();
+        if ((opt & OS_POST_OPT_NO_SCHED) == 0) {	  /* See if scheduler needs to be invoked          */
+            OS_Sched();                               /* Find HPT ready to run                         */
+        }
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventPtr != (void *)0) {            /* Make sure mailbox doesn't already have a msg  */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_MBOX_FULL);
+    }
+    pevent->OSEventPtr = pmsg;                        /* Place message in mailbox                      */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        QUERY A MESSAGE MAILBOX
+*
+* Description: This function obtains information about a message mailbox.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              p_mbox_data   is a pointer to a structure that will contain information about the message
+*                            mailbox.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non mailbox.
+*              OS_ERR_PEVENT_NULL  If 'pevent'      is a NULL pointer
+*              OS_ERR_PDATA_NULL   If 'p_mbox_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_QUERY_EN > 0
+INT8U  OSMboxQuery (OS_EVENT *pevent, OS_MBOX_DATA *p_mbox_data)
+{
+    INT8U      i;
+#if OS_LOWEST_PRIO <= 63
+    INT8U     *psrc;
+    INT8U     *pdest;
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_mbox_data == (OS_MBOX_DATA *)0) {                /* Validate 'p_mbox_data'                   */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_mbox_data->OSEventGrp = pevent->OSEventGrp;          /* Copy message mailbox wait list           */
+    psrc                    = &pevent->OSEventTbl[0];
+    pdest                   = &p_mbox_data->OSEventTbl[0];
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    p_mbox_data->OSMsg = pevent->OSEventPtr;               /* Get message from mailbox                 */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_MBOX_QUERY_EN                         */
+#endif                                                     /* OS_MBOX_EN                               */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c
new file mode 100644
index 0000000..72c8b84
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mem.c
@@ -0,0 +1,434 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                            MEMORY MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_MEM.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0)
+/*
+*********************************************************************************************************
+*                                        CREATE A MEMORY PARTITION
+*
+* Description : Create a fixed-sized memory partition that will be managed by uC/OS-II.
+*
+* Arguments   : addr     is the starting address of the memory partition
+*
+*               nblks    is the number of memory blocks to create from the partition.
+*
+*               blksize  is the size (in bytes) of each block in the memory partition.
+*
+*               perr     is a pointer to a variable containing an error message which will be set by
+*                        this function to either:
+*
+*                        OS_ERR_NONE              if the memory partition has been created correctly.
+*                        OS_ERR_MEM_INVALID_ADDR  if you are specifying an invalid address for the memory
+*                                                 storage of the partition or, the block does not align
+*                                                 on a pointer boundary
+*                        OS_ERR_MEM_INVALID_PART  no free partitions available
+*                        OS_ERR_MEM_INVALID_BLKS  user specified an invalid number of blocks (must be >= 2)
+*                        OS_ERR_MEM_INVALID_SIZE  user specified an invalid block size
+*                                                   - must be greater than the size of a pointer
+*                                                   - must be able to hold an integral number of pointers
+* Returns    : != (OS_MEM *)0  is the partition was created
+*              == (OS_MEM *)0  if the partition was not created because of invalid arguments or, no
+*                              free partition is available.
+*********************************************************************************************************
+*/
+
+OS_MEM  *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr)
+{
+    OS_MEM    *pmem;
+    INT8U     *pblk;
+    void     **plink;
+    INT32U     i;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0              
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return ((OS_MEM *)0);
+    }
+    if (addr == (void *)0) {                          /* Must pass a valid address for the memory part.*/
+        *perr = OS_ERR_MEM_INVALID_ADDR;
+        return ((OS_MEM *)0);
+    }
+    if (((INT32U)addr & (sizeof(void *) - 1)) != 0){  /* Must be pointer size aligned                  */
+        *perr = OS_ERR_MEM_INVALID_ADDR;
+        return ((OS_MEM *)0);
+    }
+    if (nblks < 2) {                                  /* Must have at least 2 blocks per partition     */
+        *perr = OS_ERR_MEM_INVALID_BLKS;
+        return ((OS_MEM *)0);
+    }
+    if (blksize < sizeof(void *)) {                   /* Must contain space for at least a pointer     */
+        *perr = OS_ERR_MEM_INVALID_SIZE;
+        return ((OS_MEM *)0);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    pmem = OSMemFreeList;                             /* Get next free memory partition                */
+    if (OSMemFreeList != (OS_MEM *)0) {               /* See if pool of free partitions was empty      */
+        OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList;
+    }
+    OS_EXIT_CRITICAL();
+    if (pmem == (OS_MEM *)0) {                        /* See if we have a memory partition             */
+        *perr = OS_ERR_MEM_INVALID_PART;
+        return ((OS_MEM *)0);
+    }
+    plink = (void **)addr;                            /* Create linked list of free memory blocks      */
+    pblk  = (INT8U *)((INT32U)addr + blksize);
+    for (i = 0; i < (nblks - 1); i++) {
+       *plink = (void *)pblk;                         /* Save pointer to NEXT block in CURRENT block   */
+        plink = (void **)pblk;                        /* Position to  NEXT      block                  */
+        pblk  = (INT8U *)((INT32U)pblk + blksize);    /* Point to the FOLLOWING block                  */
+    }
+    *plink              = (void *)0;                  /* Last memory block points to NULL              */
+    pmem->OSMemAddr     = addr;                       /* Store start address of memory partition       */
+    pmem->OSMemFreeList = addr;                       /* Initialize pointer to pool of free blocks     */
+    pmem->OSMemNFree    = nblks;                      /* Store number of free blocks in MCB            */
+    pmem->OSMemNBlks    = nblks;
+    pmem->OSMemBlkSize  = blksize;                    /* Store block size of each memory blocks        */
+    *perr               = OS_ERR_NONE;
+    return (pmem);
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          GET A MEMORY BLOCK
+*
+* Description : Get a memory block from a partition
+*
+* Arguments   : pmem    is a pointer to the memory partition control block
+*
+*               perr    is a pointer to a variable containing an error message which will be set by this
+*                       function to either:
+*
+*                       OS_ERR_NONE             if the memory partition has been created correctly.
+*                       OS_ERR_MEM_NO_FREE_BLKS if there are no more free memory blocks to allocate to caller
+*                       OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem'
+*
+* Returns     : A pointer to a memory block if no error is detected
+*               A pointer to NULL if an error is detected
+*********************************************************************************************************
+*/
+
+void  *OSMemGet (OS_MEM *pmem, INT8U *perr)
+{
+    void      *pblk;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return ((void *)0);
+    }
+    if (pmem == (OS_MEM *)0) {                        /* Must point to a valid memory partition        */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return ((void *)0);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (pmem->OSMemNFree > 0) {                       /* See if there are any free memory blocks       */
+        pblk                = pmem->OSMemFreeList;    /* Yes, point to next free memory block          */
+        pmem->OSMemFreeList = *(void **)pblk;         /*      Adjust pointer to new free list          */
+        pmem->OSMemNFree--;                           /*      One less memory block in this partition  */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;                          /*      No error                                 */
+        return (pblk);                                /*      Return memory block to caller            */
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_MEM_NO_FREE_BLKS;                  /* No,  Notify caller of empty memory partition  */
+    return ((void *)0);                               /*      Return NULL pointer to caller            */
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   GET THE NAME OF A MEMORY PARTITION
+*
+* Description: This function is used to obtain the name assigned to a memory partition.
+*
+* Arguments  : pmem      is a pointer to the memory partition
+*
+*              pname     is a pointer to an ASCII string that will receive the name of the memory partition.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the name was copied to 'pname'
+*                        OS_ERR_MEM_INVALID_PMEM    if you passed a NULL pointer for 'pmem'
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_NAME_GET_ISR        You called this function from an ISR
+*
+* Returns    : The length of the string or 0 if 'pmem' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_SIZE > 1
+INT8U  OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return (0);
+    }
+    if (pmem == (OS_MEM *)0) {                   /* Is 'pmem' a NULL pointer?                          */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return (0);
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_GET_ISR;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    len   = OS_StrCopy(pname, pmem->OSMemName);  /* Copy name from OS_MEM                              */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (len);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                 ASSIGN A NAME TO A MEMORY PARTITION
+*
+* Description: This function assigns a name to a memory partition.
+*
+* Arguments  : pmem      is a pointer to the memory partition
+*
+*              pname     is a pointer to an ASCII string that contains the name of the memory partition.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the name was copied to 'pname'
+*                        OS_ERR_MEM_INVALID_PMEM    if you passed a NULL pointer for 'pmem'
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_MEM_NAME_TOO_LONG   if the name doesn't fit in the storage area
+*                        OS_ERR_NAME_SET_ISR        if you called this function from an ISR
+*
+* Returns    : None
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_SIZE > 1
+void  OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return;
+    }
+    if (pmem == (OS_MEM *)0) {                   /* Is 'pmem' a NULL pointer?                          */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return;
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_SET_ISR;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    len = OS_StrLen(pname);                      /* Can we fit the string in the storage area?         */
+    if (len > (OS_MEM_NAME_SIZE - 1)) {          /* No                                                 */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_MEM_NAME_TOO_LONG;
+        return;
+    }
+    (void)OS_StrCopy(pmem->OSMemName, pname);    /* Yes, copy name to the memory partition header      */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         RELEASE A MEMORY BLOCK
+*
+* Description : Returns a memory block to a partition
+*
+* Arguments   : pmem    is a pointer to the memory partition control block
+*
+*               pblk    is a pointer to the memory block being released.
+*
+* Returns     : OS_ERR_NONE              if the memory block was inserted into the partition
+*               OS_ERR_MEM_FULL          if you are returning a memory block to an already FULL memory
+*                                        partition (You freed more blocks than you allocated!)
+*               OS_ERR_MEM_INVALID_PMEM  if you passed a NULL pointer for 'pmem'
+*               OS_ERR_MEM_INVALID_PBLK  if you passed a NULL pointer for the block to release.
+*********************************************************************************************************
+*/
+
+INT8U  OSMemPut (OS_MEM *pmem, void *pblk)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pmem == (OS_MEM *)0) {                   /* Must point to a valid memory partition             */
+        return (OS_ERR_MEM_INVALID_PMEM);
+    }
+    if (pblk == (void *)0) {                     /* Must release a valid block                         */
+        return (OS_ERR_MEM_INVALID_PBLK);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (pmem->OSMemNFree >= pmem->OSMemNBlks) {  /* Make sure all blocks not already returned          */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_MEM_FULL);
+    }
+    *(void **)pblk      = pmem->OSMemFreeList;   /* Insert released block into free block list         */
+    pmem->OSMemFreeList = pblk;
+    pmem->OSMemNFree++;                          /* One more memory block in this partition            */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);                        /* Notify caller that memory block was released       */
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          QUERY MEMORY PARTITION
+*
+* Description : This function is used to determine the number of free memory blocks and the number of
+*               used memory blocks from a memory partition.
+*
+* Arguments   : pmem        is a pointer to the memory partition control block
+*
+*               p_mem_data  is a pointer to a structure that will contain information about the memory
+*                           partition.
+*
+* Returns     : OS_ERR_NONE               if no errors were found.
+*               OS_ERR_MEM_INVALID_PMEM   if you passed a NULL pointer for 'pmem'
+*               OS_ERR_MEM_INVALID_PDATA  if you passed a NULL pointer to the data recipient.
+*********************************************************************************************************
+*/
+
+#if OS_MEM_QUERY_EN > 0
+INT8U  OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pmem == (OS_MEM *)0) {                   /* Must point to a valid memory partition             */
+        return (OS_ERR_MEM_INVALID_PMEM);
+    }
+    if (p_mem_data == (OS_MEM_DATA *)0) {        /* Must release a valid storage area for the data     */
+        return (OS_ERR_MEM_INVALID_PDATA);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    p_mem_data->OSAddr     = pmem->OSMemAddr;
+    p_mem_data->OSFreeList = pmem->OSMemFreeList;
+    p_mem_data->OSBlkSize  = pmem->OSMemBlkSize;
+    p_mem_data->OSNBlks    = pmem->OSMemNBlks;
+    p_mem_data->OSNFree    = pmem->OSMemNFree;
+    OS_EXIT_CRITICAL();
+    p_mem_data->OSNUsed    = p_mem_data->OSNBlks - p_mem_data->OSNFree;
+    return (OS_ERR_NONE);
+}
+#endif                                           /* OS_MEM_QUERY_EN                                    */
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                    INITIALIZE MEMORY PARTITION MANAGER
+*
+* Description : This function is called by uC/OS-II to initialize the memory partition manager.  Your
+*               application MUST NOT call this function.
+*
+* Arguments   : none
+*
+* Returns     : none
+*
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_MemInit (void)
+{
+#if OS_MAX_MEM_PART == 1
+    OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl));   /* Clear the memory partition table          */
+    OSMemFreeList               = (OS_MEM *)&OSMemTbl[0]; /* Point to beginning of free list           */
+#if OS_MEM_NAME_SIZE > 1
+    OSMemFreeList->OSMemName[0] = '?';                    /* Unknown name                              */
+    OSMemFreeList->OSMemName[1] = OS_ASCII_NUL;
+#endif
+#endif
+
+#if OS_MAX_MEM_PART >= 2
+    OS_MEM  *pmem;
+    INT16U   i;
+
+
+    OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl));   /* Clear the memory partition table          */
+    pmem = &OSMemTbl[0];                                  /* Point to memory control block (MCB)       */
+    for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) {         /* Init. list of free memory partitions      */
+        pmem->OSMemFreeList = (void *)&OSMemTbl[i+1];     /* Chain list of free partitions             */
+#if OS_MEM_NAME_SIZE > 1
+        pmem->OSMemName[0]  = '?';                        /* Unknown name                              */
+        pmem->OSMemName[1]  = OS_ASCII_NUL;
+#endif
+        pmem++;
+    }
+    pmem->OSMemFreeList = (void *)0;                      /* Initialize last node                      */
+#if OS_MEM_NAME_SIZE > 1
+    pmem->OSMemName[0]  = '?';                            /* Unknown name                              */
+    pmem->OSMemName[1]  = OS_ASCII_NUL;
+#endif
+
+    OSMemFreeList       = &OSMemTbl[0];                   /* Point to beginning of free list           */
+#endif
+}
+#endif                                                    /* OS_MEM_EN                                 */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c
new file mode 100644
index 0000000..c33d589
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_mutex.c
@@ -0,0 +1,715 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                  MUTUAL EXCLUSION SEMAPHORE MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_MUTEX.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+
+#if OS_MUTEX_EN > 0
+/*
+*********************************************************************************************************
+*                                            LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+#define  OS_MUTEX_KEEP_LOWER_8   ((INT16U)0x00FFu)
+#define  OS_MUTEX_KEEP_UPPER_8   ((INT16U)0xFF00u)
+
+#define  OS_MUTEX_AVAILABLE      ((INT16U)0x00FFu)
+
+/*
+*********************************************************************************************************
+*                                            LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+static  void  OSMutex_RdyAtPrio(OS_TCB *ptcb, INT8U prio);
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   ACCEPT MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This  function checks the mutual exclusion semaphore to see if a resource is available.
+*              Unlike OSMutexPend(), OSMutexAccept() does not suspend the calling task if the resource is
+*              not available or the event did not occur.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+*              perr       is a pointer to an error code which will be returned to your application:
+*                            OS_ERR_NONE         if the call was successful.
+*                            OS_ERR_EVENT_TYPE   if 'pevent' is not a pointer to a mutex
+*                            OS_ERR_PEVENT_NULL  'pevent' is a NULL pointer
+*                            OS_ERR_PEND_ISR     if you called this function from an ISR
+*                            OS_ERR_PIP_LOWER    If the priority of the task that owns the Mutex is
+*                                                HIGHER (i.e. a lower number) than the PIP.  This error
+*                                                indicates that you did not set the PIP higher (lower
+*                                                number) than ALL the tasks that compete for the Mutex.
+*                                                Unfortunately, this is something that could not be
+*                                                detected when the Mutex is created because we don't know
+*                                                what tasks will be using the Mutex.
+*
+* Returns    : == OS_TRUE    if the resource is available, the mutual exclusion semaphore is acquired
+*              == OS_FALSE   a) if the resource is not available
+*                            b) you didn't pass a pointer to a mutual exclusion semaphore
+*                            c) you called this function from an ISR
+*
+* Warning(s) : This function CANNOT be called from an ISR because mutual exclusion semaphores are
+*              intended to be used by tasks only.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_ACCEPT_EN > 0
+BOOLEAN  OSMutexAccept (OS_EVENT *pevent, INT8U *perr)
+{
+    INT8U      pip;                                    /* Priority Inheritance Priority (PIP)          */
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                          /* Validate 'perr'                              */
+        return (OS_FALSE);
+    }
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (OS_FALSE);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {  /* Validate event block type                    */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (OS_FALSE);
+    }
+    if (OSIntNesting > 0) {                            /* Make sure it's not called from an ISR        */
+        *perr = OS_ERR_PEND_ISR;
+        return (OS_FALSE);
+    }
+    OS_ENTER_CRITICAL();                               /* Get value (0 or 1) of Mutex                  */
+    pip = (INT8U)(pevent->OSEventCnt >> 8);            /* Get PIP from mutex                           */
+    if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;   /*      Mask off LSByte (Acquire Mutex)         */
+        pevent->OSEventCnt |= OSTCBCur->OSTCBPrio;     /*      Save current task priority in LSByte    */
+        pevent->OSEventPtr  = (void *)OSTCBCur;        /*      Link TCB of task owning Mutex           */
+        if (OSTCBCur->OSTCBPrio <= pip) {              /*      PIP 'must' have a SMALLER prio ...      */
+            OS_EXIT_CRITICAL();                        /*      ... than current task!                  */
+            *perr = OS_ERR_PIP_LOWER;
+        } else {
+            OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+        }
+        return (OS_TRUE);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (OS_FALSE);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                  CREATE A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function creates a mutual exclusion semaphore.
+*
+* Arguments  : prio          is the priority to use when accessing the mutual exclusion semaphore.  In
+*                            other words, when the semaphore is acquired and a higher priority task
+*                            attempts to obtain the semaphore then the priority of the task owning the
+*                            semaphore is raised to this priority.  It is assumed that you will specify
+*                            a priority that is LOWER in value than ANY of the tasks competing for the
+*                            mutex.
+*
+*              perr          is a pointer to an error code which will be returned to your application:
+*                               OS_ERR_NONE         if the call was successful.
+*                               OS_ERR_CREATE_ISR   if you attempted to create a MUTEX from an ISR
+*                               OS_ERR_PRIO_EXIST   if a task at the priority inheritance priority
+*                                                   already exist.
+*                               OS_ERR_PEVENT_NULL  No more event control blocks available.
+*                               OS_ERR_PRIO_INVALID if the priority you specify is higher that the
+*                                                   maximum allowed (i.e. > OS_LOWEST_PRIO)
+*
+* Returns    : != (void *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                            created mutex.
+*              == (void *)0  if an error is detected.
+*
+* Note(s)    : 1) The LEAST significant 8 bits of '.OSEventCnt' are used to hold the priority number
+*                 of the task owning the mutex or 0xFF if no task owns the mutex.
+*
+*              2) The MOST  significant 8 bits of '.OSEventCnt' are used to hold the priority number
+*                 to use to reduce priority inversion.
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSMutexCreate (INT8U prio, INT8U *perr)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return ((OS_EVENT *)0);
+    }
+    if (prio >= OS_LOWEST_PRIO) {                          /* Validate PIP                             */
+        *perr = OS_ERR_PRIO_INVALID;
+        return ((OS_EVENT *)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_CREATE_ISR;                         /* ... can't CREATE mutex from an ISR       */
+        return ((OS_EVENT *)0);
+    }
+    OS_ENTER_CRITICAL();
+    if (OSTCBPrioTbl[prio] != (OS_TCB *)0) {               /* Mutex priority must not already exist    */
+        OS_EXIT_CRITICAL();                                /* Task already exist at priority ...       */
+        *perr = OS_ERR_PRIO_EXIST;                         /* ... inheritance priority                 */
+        return ((OS_EVENT *)0);
+    }
+    OSTCBPrioTbl[prio] = OS_TCB_RESERVED;                  /* Reserve the table entry                  */
+    pevent             = OSEventFreeList;                  /* Get next free event control block        */
+    if (pevent == (OS_EVENT *)0) {                         /* See if an ECB was available              */
+        OSTCBPrioTbl[prio] = (OS_TCB *)0;                  /* No, Release the table entry              */
+        OS_EXIT_CRITICAL();
+        *perr              = OS_ERR_PEVENT_NULL;           /* No more event control blocks             */
+        return (pevent);
+    }
+    OSEventFreeList        = (OS_EVENT *)OSEventFreeList->OSEventPtr;   /* Adjust the free list        */
+    OS_EXIT_CRITICAL();
+    pevent->OSEventType    = OS_EVENT_TYPE_MUTEX;
+    pevent->OSEventCnt     = (INT16U)((INT16U)prio << 8) | OS_MUTEX_AVAILABLE; /* Resource is avail.   */
+    pevent->OSEventPtr     = (void *)0;                                 /* No task owning the mutex    */
+#if OS_EVENT_NAME_SIZE > 1
+    pevent->OSEventName[0] = '?';
+    pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+    OS_EventWaitListInit(pevent);
+    *perr                  = OS_ERR_NONE;
+    return (pevent);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          DELETE A MUTEX
+*
+* Description: This function deletes a mutual exclusion semaphore and readies all tasks pending on the it.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mutex.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete mutex ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the mutex even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE             The call was successful and the mutex was deleted
+*                            OS_ERR_DEL_ISR          If you attempted to delete the MUTEX from an ISR
+*                            OS_ERR_INVALID_OPT      An invalid option was specified
+*                            OS_ERR_TASK_WAITING     One or more tasks were waiting on the mutex
+*                            OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a mutex
+*                            OS_ERR_PEVENT_NULL      If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the mutex was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the mutex MUST check the return code of OSMutexPend().
+*
+*              2) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the mutex.
+*
+*              3) Because ALL tasks pending on the mutex will be readied, you MUST be careful because the
+*                 resource(s) will no longer be guarded by the mutex.
+*
+*              4) IMPORTANT: In the 'OS_DEL_ALWAYS' case, we assume that the owner of the Mutex (if there
+*                            is one) is ready-to-run and is thus NOT pending on another kernel object or
+*                            has delayed itself.  In other words, if a task owns the mutex being deleted,
+*                            that task will be made ready-to-run at its original priority.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_DEL_EN
+OS_EVENT  *OSMutexDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+    INT8U      pip;                                        /* Priority inheritance priority            */
+    INT8U      prio;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (pevent);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (pevent);
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                             /* ... can't DELETE from an ISR             */
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on mutex        */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* DELETE MUTEX ONLY IF NO TASK WAITING --- */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+                 pip                 = (INT8U)(pevent->OSEventCnt >> 8);
+                 OSTCBPrioTbl[pip]   = (OS_TCB *)0;        /* Free up the PIP                          */
+                 pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr  = OSEventFreeList;    /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt  = 0;
+                 OSEventFreeList     = pevent;
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_NONE;
+                 pevent_return       = (OS_EVENT *)0;      /* Mutex has been deleted                   */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_TASK_WAITING;
+                 pevent_return       = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* ALWAYS DELETE THE MUTEX ---------------- */
+             pip  = (INT8U)(pevent->OSEventCnt >> 8);                     /* Get PIP of mutex          */
+             prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* Get owner's original prio */
+             ptcb = (OS_TCB *)pevent->OSEventPtr;
+             if (ptcb != (OS_TCB *)0) {                    /* See if any task owns the mutex           */
+                 if (ptcb->OSTCBPrio == pip) {             /* See if original prio was changed         */
+                     OSMutex_RdyAtPrio(ptcb, prio);        /* Yes, Restore the task's original prio    */
+                 }
+             }
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for mutex        */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK);
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+             pip                 = (INT8U)(pevent->OSEventCnt >> 8);
+             OSTCBPrioTbl[pip]   = (OS_TCB *)0;            /* Free up the PIP                          */
+             pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr  = OSEventFreeList;        /* Return Event Control Block to free list  */
+             pevent->OSEventCnt  = 0;
+             OSEventFreeList     = pevent;                 /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr         = OS_ERR_NONE;
+             pevent_return = (OS_EVENT *)0;                /* Mutex has been deleted                   */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr         = OS_ERR_INVALID_OPT;
+             pevent_return = pevent;
+             break;
+    }
+    return (pevent_return);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                  PEND ON MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function waits for a mutual exclusion semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            mutex.
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for the resource up to the amount of time specified by this argument.
+*                            If you specify 0, however, your task will wait forever at the specified
+*                            mutex or, until the resource becomes available.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*                               OS_ERR_NONE        The call was successful and your task owns the mutex
+*                               OS_ERR_TIMEOUT     The mutex was not available within the specified 'timeout'.
+*                               OS_ERR_PEND_ABORT  The wait on the mutex was aborted.
+*                               OS_ERR_EVENT_TYPE  If you didn't pass a pointer to a mutex
+*                               OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer
+*                               OS_ERR_PEND_ISR    If you called this function from an ISR and the result
+*                                                  would lead to a suspension.
+*                               OS_ERR_PIP_LOWER   If the priority of the task that owns the Mutex is
+*                                                  HIGHER (i.e. a lower number) than the PIP.  This error
+*                                                  indicates that you did not set the PIP higher (lower
+*                                                  number) than ALL the tasks that compete for the Mutex.
+*                                                  Unfortunately, this is something that could not be
+*                                                  detected when the Mutex is created because we don't know
+*                                                  what tasks will be using the Mutex.
+*                               OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked
+*
+* Returns    : none
+*
+* Note(s)    : 1) The task that owns the Mutex MUST NOT pend on any other event while it owns the mutex.
+*
+*              2) You MUST NOT change the priority of the task that owns the mutex
+*********************************************************************************************************
+*/
+
+void  OSMutexPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+    INT8U      pip;                                        /* Priority Inheritance Priority (PIP)      */
+    INT8U      mprio;                                      /* Mutex owner priority                     */
+    BOOLEAN    rdy;                                        /* Flag indicating task was ready           */
+    OS_TCB    *ptcb;
+    OS_EVENT  *pevent2;
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return;
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return;
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_PEND_ISR;                           /* ... can't PEND from an ISR               */
+        return;
+    }
+    if (OSLockNesting > 0) {                               /* See if called with scheduler locked ...  */
+        *perr = OS_ERR_PEND_LOCKED;                        /* ... can't PEND when locked               */
+        return;
+    }
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+    pip = (INT8U)(pevent->OSEventCnt >> 8);                /* Get PIP from mutex                       */
+                                                           /* Is Mutex available?                      */
+    if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;       /* Yes, Acquire the resource                */
+        pevent->OSEventCnt |= OSTCBCur->OSTCBPrio;         /*      Save priority of owning task        */
+        pevent->OSEventPtr  = (void *)OSTCBCur;            /*      Point to owning task's OS_TCB       */
+        if (OSTCBCur->OSTCBPrio <= pip) {                  /*      PIP 'must' have a SMALLER prio ...  */
+            OS_EXIT_CRITICAL();                            /*      ... than current task!              */
+            *perr = OS_ERR_PIP_LOWER;
+        } else {
+            OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+        }
+        return;
+    }
+    mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* No, Get priority of mutex owner   */
+    ptcb  = (OS_TCB *)(pevent->OSEventPtr);                       /*     Point to TCB of mutex owner   */
+    if (ptcb->OSTCBPrio > pip) {                                  /*     Need to promote prio of owner?*/
+        if (mprio > OSTCBCur->OSTCBPrio) {
+            y = ptcb->OSTCBY;
+            if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0) {           /*     See if mutex owner is ready   */
+                OSRdyTbl[y] &= ~ptcb->OSTCBBitX;                  /*     Yes, Remove owner from Rdy ...*/
+                if (OSRdyTbl[y] == 0) {                           /*          ... list at current prio */
+                    OSRdyGrp &= ~ptcb->OSTCBBitY;
+                }
+                rdy = OS_TRUE;
+            } else {
+                pevent2 = ptcb->OSTCBEventPtr;
+                if (pevent2 != (OS_EVENT *)0) {                   /* Remove from event wait list       */
+                    if ((pevent2->OSEventTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX) == 0) {
+                        pevent2->OSEventGrp &= ~ptcb->OSTCBBitY;
+                    }
+                }
+                rdy = OS_FALSE;                            /* No                                       */
+            }
+            ptcb->OSTCBPrio = pip;                         /* Change owner task prio to PIP            */
+#if OS_LOWEST_PRIO <= 63
+            ptcb->OSTCBY    = (INT8U)( ptcb->OSTCBPrio >> 3);
+            ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x07);
+            ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY);
+            ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX);
+#else
+            ptcb->OSTCBY    = (INT8U)((ptcb->OSTCBPrio >> 4) & 0xFF);
+            ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x0F);
+            ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY);
+            ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+            if (rdy == OS_TRUE) {                          /* If task was ready at owner's priority ...*/
+                OSRdyGrp               |= ptcb->OSTCBBitY; /* ... make it ready at new priority.       */
+                OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+            } else {
+                pevent2 = ptcb->OSTCBEventPtr;
+                if (pevent2 != (OS_EVENT *)0) {            /* Add to event wait list                   */
+                    pevent2->OSEventGrp               |= ptcb->OSTCBBitY;
+                    pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+                }
+            }
+            OSTCBPrioTbl[pip] = ptcb;
+        }
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_MUTEX;         /* Mutex not available, pend current task        */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Store timeout in current task's TCB           */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted getting mutex        */
+             break;
+             
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get mutex within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+#endif
+    OS_EXIT_CRITICAL();
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                  POST TO A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function signals a mutual exclusion semaphore
+*
+* Arguments  : pevent              is a pointer to the event control block associated with the desired
+*                                  mutex.
+*
+* Returns    : OS_ERR_NONE             The call was successful and the mutex was signaled.
+*              OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a mutex
+*              OS_ERR_PEVENT_NULL      'pevent' is a NULL pointer
+*              OS_ERR_POST_ISR         Attempted to post from an ISR (not valid for MUTEXes)
+*              OS_ERR_NOT_MUTEX_OWNER  The task that did the post is NOT the owner of the MUTEX.
+*              OS_ERR_PIP_LOWER        If the priority of the new task that owns the Mutex is
+*                                      HIGHER (i.e. a lower number) than the PIP.  This error
+*                                      indicates that you did not set the PIP higher (lower
+*                                      number) than ALL the tasks that compete for the Mutex.
+*                                      Unfortunately, this is something that could not be
+*                                      detected when the Mutex is created because we don't know
+*                                      what tasks will be using the Mutex.
+*********************************************************************************************************
+*/
+
+INT8U  OSMutexPost (OS_EVENT *pevent)
+{
+    INT8U      pip;                                   /* Priority inheritance priority                 */
+    INT8U      prio;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                           /* See if called from ISR ...                    */
+        return (OS_ERR_POST_ISR);                     /* ... can't POST mutex from an ISR              */
+    }
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    pip  = (INT8U)(pevent->OSEventCnt >> 8);          /* Get priority inheritance priority of mutex    */
+    prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* Get owner's original priority      */
+    if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) {   /* See if posting task owns the MUTEX            */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NOT_MUTEX_OWNER);
+    }
+    if (OSTCBCur->OSTCBPrio == pip) {                 /* Did we have to raise current task's priority? */
+        OSMutex_RdyAtPrio(OSTCBCur, prio);            /* Restore the task's original priority          */
+    }
+    OSTCBPrioTbl[pip] = OS_TCB_RESERVED;              /* Reserve table entry                           */
+    if (pevent->OSEventGrp != 0) {                    /* Any task waiting for the mutex?               */
+                                                      /* Yes, Make HPT waiting for mutex ready         */
+        prio                = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK);
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;  /*      Save priority of mutex's new owner       */
+        pevent->OSEventCnt |= prio;
+        pevent->OSEventPtr  = OSTCBPrioTbl[prio];     /*      Link to new mutex owner's OS_TCB         */
+        if (prio <= pip) {                            /*      PIP 'must' have a SMALLER prio ...       */
+            OS_EXIT_CRITICAL();                       /*      ... than current task!                   */
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+            return (OS_ERR_PIP_LOWER);
+        } else {
+            OS_EXIT_CRITICAL();
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+            return (OS_ERR_NONE);
+        }
+    }
+    pevent->OSEventCnt |= OS_MUTEX_AVAILABLE;         /* No,  Mutex is now available                   */
+    pevent->OSEventPtr  = (void *)0;
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                     QUERY A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function obtains information about a mutex
+*
+* Arguments  : pevent          is a pointer to the event control block associated with the desired mutex
+*
+*              p_mutex_data    is a pointer to a structure that will contain information about the mutex
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_QUERY_ISR     If you called this function from an ISR
+*              OS_ERR_PEVENT_NULL   If 'pevent'       is a NULL pointer
+*              OS_ERR_PDATA_NULL    If 'p_mutex_data' is a NULL pointer
+*              OS_ERR_EVENT_TYPE    If you are attempting to obtain data from a non mutex.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_QUERY_EN > 0
+INT8U  OSMutexQuery (OS_EVENT *pevent, OS_MUTEX_DATA *p_mutex_data)
+{
+    INT8U      i;
+#if OS_LOWEST_PRIO <= 63
+    INT8U     *psrc;
+    INT8U     *pdest;
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        return (OS_ERR_QUERY_ISR);                         /* ... can't QUERY mutex from an ISR        */
+    }
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_mutex_data == (OS_MUTEX_DATA *)0) {              /* Validate 'p_mutex_data'                  */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_mutex_data->OSMutexPIP  = (INT8U)(pevent->OSEventCnt >> 8);
+    p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);
+    if (p_mutex_data->OSOwnerPrio == 0xFF) {
+        p_mutex_data->OSValue = OS_TRUE;
+    } else {
+        p_mutex_data->OSValue = OS_FALSE;
+    }
+    p_mutex_data->OSEventGrp  = pevent->OSEventGrp;        /* Copy wait list                           */
+    psrc                      = &pevent->OSEventTbl[0];
+    pdest                     = &p_mutex_data->OSEventTbl[0];
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_MUTEX_QUERY_EN                        */
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                RESTORE A TASK BACK TO ITS ORIGINAL PRIORITY
+*
+* Description: This function makes a task ready at the specified priority
+*
+* Arguments  : ptcb            is a pointer to OS_TCB of the task to make ready
+*
+*              prio            is the desired priority
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OSMutex_RdyAtPrio (OS_TCB *ptcb, INT8U prio)
+{
+    INT8U   y;
+
+
+    y            =  ptcb->OSTCBY;                          /* Remove owner from ready list at 'pip'    */
+    OSRdyTbl[y] &= ~ptcb->OSTCBBitX;
+    if (OSRdyTbl[y] == 0) {
+        OSRdyGrp &= ~ptcb->OSTCBBitY;
+    }
+    ptcb->OSTCBPrio         = prio;
+#if OS_LOWEST_PRIO <= 63
+    ptcb->OSTCBY            = (INT8U)((prio >> (INT8U)3) & (INT8U)0x07);
+    ptcb->OSTCBX            = (INT8U) (prio & (INT8U)0x07);
+    ptcb->OSTCBBitY         = (INT8U)(1 << ptcb->OSTCBY);
+    ptcb->OSTCBBitX         = (INT8U)(1 << ptcb->OSTCBX);
+#else
+    ptcb->OSTCBY            = (INT8U)((prio >> (INT8U)4) & (INT8U)0x0F);
+    ptcb->OSTCBX            = (INT8U) (prio & (INT8U)0x0F);
+    ptcb->OSTCBBitY         = (INT16U)(1 << ptcb->OSTCBY);
+    ptcb->OSTCBBitX         = (INT16U)(1 << ptcb->OSTCBX);
+#endif
+    OSRdyGrp               |= ptcb->OSTCBBitY;             /* Make task ready at original priority     */
+    OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+    OSTCBPrioTbl[prio]      = ptcb;
+}
+
+
+#endif                                                     /* OS_MUTEX_EN                              */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c
new file mode 100644
index 0000000..4d3c8a7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_q.c
@@ -0,0 +1,868 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                        MESSAGE QUEUE MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_Q.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if (OS_Q_EN > 0) && (OS_MAX_QS > 0)
+/*
+*********************************************************************************************************
+*                                      ACCEPT MESSAGE FROM QUEUE
+*
+* Description: This function checks the queue to see if a message is available.  Unlike OSQPend(),
+*              OSQAccept() does not suspend the calling task if a message is not available.
+*
+* Arguments  : pevent        is a pointer to the event control block
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_EVENT_TYPE   You didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_Q_EMPTY      The queue did not contain any messages
+*
+* Returns    : != (void *)0  is the message in the queue if one is available.  The message is removed
+*                            from the so the next time OSQAccept() is called, the queue will contain
+*                            one less entry.
+*              == (void *)0  if you received a NULL pointer message
+*                            if the queue is empty or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you passed an invalid event type
+*
+* Note(s)    : As of V2.60, you can now pass NULL pointers through queues.  Because of this, the argument
+*              'perr' has been added to the API to tell you about the outcome of the call.
+*********************************************************************************************************
+*/
+
+#if OS_Q_ACCEPT_EN > 0
+void  *OSQAccept (OS_EVENT *pevent, INT8U *perr)
+{
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return ((void *)0);
+    }
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+    if (pq->OSQEntries > 0) {                    /* See if any messages in the queue                   */
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+            pq->OSQOut = pq->OSQStart;
+        }
+        *perr = OS_ERR_NONE;
+    } else {
+        *perr = OS_ERR_Q_EMPTY;
+        pmsg  = (void *)0;                       /* Queue is empty                                     */
+    }
+    OS_EXIT_CRITICAL();
+    return (pmsg);                               /* Return message received (or NULL)                  */
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        CREATE A MESSAGE QUEUE
+*
+* Description: This function creates a message queue if free event control blocks are available.
+*
+* Arguments  : start         is a pointer to the base address of the message queue storage area.  The
+*                            storage area MUST be declared as an array of pointers to 'void' as follows
+*
+*                            void *MessageStorage[size]
+*
+*              size          is the number of elements in the storage area
+*
+* Returns    : != (OS_EVENT *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                                created queue
+*              == (OS_EVENT *)0  if no event control blocks were available or an error was detected
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSQCreate (void **start, INT16U size)
+{
+    OS_EVENT  *pevent;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                      /* See if called from ISR ...                         */
+        return ((OS_EVENT *)0);                  /* ... can't CREATE from an ISR                       */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                    /* Get next free event control block                  */
+    if (OSEventFreeList != (OS_EVENT *)0) {      /* See if pool of free ECB pool was empty             */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {               /* See if we have an event control block              */
+        OS_ENTER_CRITICAL();
+        pq = OSQFreeList;                        /* Get a free queue control block                     */
+        if (pq != (OS_Q *)0) {                   /* Were we able to get a queue control block ?        */
+            OSQFreeList            = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/
+            OS_EXIT_CRITICAL();
+            pq->OSQStart           = start;               /*      Initialize the queue                 */
+            pq->OSQEnd             = &start[size];
+            pq->OSQIn              = start;
+            pq->OSQOut             = start;
+            pq->OSQSize            = size;
+            pq->OSQEntries         = 0;
+            pevent->OSEventType    = OS_EVENT_TYPE_Q;
+            pevent->OSEventCnt     = 0;
+            pevent->OSEventPtr     = pq;
+#if OS_EVENT_NAME_SIZE > 1
+            pevent->OSEventName[0] = '?';                  /* Unknown name                             */
+            pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+            OS_EventWaitListInit(pevent);                 /*      Initalize the wait list              */
+        } else {
+            pevent->OSEventPtr = (void *)OSEventFreeList; /* No,  Return event control block on error  */
+            OSEventFreeList    = pevent;
+            OS_EXIT_CRITICAL();
+            pevent = (OS_EVENT *)0;
+        }
+    }
+    return (pevent);
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        DELETE A MESSAGE QUEUE
+*
+* Description: This function deletes a message queue and readies all tasks pending on the queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            queue.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete the queue ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the queue even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE             The call was successful and the queue was deleted
+*                            OS_ERR_DEL_ISR          If you tried to delete the queue from an ISR
+*                            OS_ERR_INVALID_OPT      An invalid option was specified
+*                            OS_ERR_TASK_WAITING     One or more tasks were waiting on the queue
+*                            OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL      If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the queue was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the queue MUST check the return code of OSQPend().
+*              2) OSQAccept() callers will not know that the intended queue has been deleted unless
+*                 they check 'pevent' to see that it's a NULL pointer.
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the queue.
+*              4) Because ALL tasks pending on the queue will be readied, you MUST be careful in
+*                 applications where the queue is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the queue.
+*              5) If the storage for the message queue was allocated dynamically (i.e. using a malloc()
+*                 type call) then your application MUST release the memory storage by call the counterpart
+*                 call of the dynamic allocation scheme used.  If the queue storage was created statically
+*                 then, the storage can be reused.
+*********************************************************************************************************
+*/
+
+#if OS_Q_DEL_EN > 0
+OS_EVENT  *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (pevent);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (pevent);
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on queue        */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete queue only if no task waiting     */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+                 pq                     = (OS_Q *)pevent->OSEventPtr;  /* Return OS_Q to free list     */
+                 pq->OSQPtr             = OSQFreeList;
+                 OSQFreeList            = pq;
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt     = 0;
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+                 pevent_return          = (OS_EVENT *)0;   /* Queue has been deleted                   */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the queue                  */
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for queue        */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK);
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+             pq                     = (OS_Q *)pevent->OSEventPtr;   /* Return OS_Q to free list        */
+             pq->OSQPtr             = OSQFreeList;
+             OSQFreeList            = pq;
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr                  = OS_ERR_NONE;
+             pevent_return          = (OS_EVENT *)0;       /* Queue has been deleted                   */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+             pevent_return          = pevent;
+             break;
+    }
+    return (pevent_return);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             FLUSH QUEUE
+*
+* Description : This function is used to flush the contents of the message queue.
+*
+* Arguments   : none
+*
+* Returns     : OS_ERR_NONE         upon success
+*               OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a queue
+*               OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*
+* WARNING     : You should use this function with great care because, when to flush the queue, you LOOSE
+*               the references to what the queue entries are pointing to and thus, you could cause
+*               'memory leaks'.  In other words, the data you are pointing to that's being referenced
+*               by the queue entries should, most likely, need to be de-allocated (i.e. freed).
+*********************************************************************************************************
+*/
+
+#if OS_Q_FLUSH_EN > 0
+INT8U  OSQFlush (OS_EVENT *pevent)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    pq             = (OS_Q *)pevent->OSEventPtr;      /* Point to queue storage structure              */
+    pq->OSQIn      = pq->OSQStart;
+    pq->OSQOut     = pq->OSQStart;
+    pq->OSQEntries = 0;
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                     PEND ON A QUEUE FOR A MESSAGE
+*
+* Description: This function waits for a message to be sent to a queue
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for a message to arrive at the queue up to the amount of time
+*                            specified by this argument.  If you specify 0, however, your task will wait
+*                            forever at the specified queue or, until a message arrives.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_TIMEOUT      A message was not received within the specified 'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the queue was aborted.
+*                            OS_ERR_EVENT_TYPE   You didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEND_LOCKED  If you called this function with the scheduler is locked
+*
+* Returns    : != (void *)0  is a pointer to the message received
+*              == (void *)0  if you received a NULL pointer message or,
+*                            if no message was received or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass a pointer to a queue.
+*
+* Note(s)    : As of V2.60, this function allows you to receive NULL pointer messages.
+*********************************************************************************************************
+*/
+
+void  *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                    /* Validate 'perr'                                    */
+        return ((void *)0);
+    }
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((void *)0);
+    }
+    if (OSIntNesting > 0) {                      /* See if called from ISR ...                         */
+        *perr = OS_ERR_PEND_ISR;                 /* ... can't PEND from an ISR                         */
+        return ((void *)0);
+    }
+    if (OSLockNesting > 0) {                     /* See if called with scheduler locked ...            */
+        *perr = OS_ERR_PEND_LOCKED;              /* ... can't PEND when locked                         */
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+    if (pq->OSQEntries > 0) {                    /* See if any messages in the queue                   */
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+            pq->OSQOut = pq->OSQStart;
+        }
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        return (pmsg);                           /* Return message received                            */
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_Q;        /* Task will have to pend for a message to be posted  */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;          /* Load timeout into TCB                              */
+    OS_EventTaskWait(pevent);                    /* Suspend task until event or timeout occurs         */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                  /* Find next highest priority task ready to run       */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:                         /* Extract message from TCB (Put there by QPost) */
+             pmsg =  OSTCBCur->OSTCBMsg;
+            *perr =  OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             pmsg = (void *)0;
+            *perr =  OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             pmsg = (void *)0;
+            *perr =  OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+#endif
+    OSTCBCur->OSTCBMsg           = (void      *)0;    /* Clear  received message                       */
+    OS_EXIT_CRITICAL();
+    return (pmsg);                                    /* Return received message                       */
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      ABORT WAITING ON A MESSAGE QUEUE
+*
+* Description: This function aborts & readies any tasks currently waiting on a queue.  This function 
+*              should be used to fault-abort the wait on the queue, rather than to normally signal
+*              the queue via OSQPost(), OSQPostFront() or OSQPostOpt().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     queue
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     queue
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the queue.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the queue was readied
+*                                                and informed of the aborted wait; check return value 
+*                                                for the number of tasks whose wait on the queue 
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a queue.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the queue, or upon error.
+*              >  0          if one or more tasks waiting on the queue are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_Q_PEND_ABORT_EN > 0
+INT8U  OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (0);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any task waiting on queue?        */
+        nbr_tasks = 0;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:                    /* Do we need to abort ALL waiting tasks?   */
+                 while (pevent->OSEventGrp != 0) {         /* Yes, ready ALL tasks waiting on queue    */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+               
+            case OS_PEND_OPT_NONE:
+            default:                                       /* No,  ready HPT       waiting on queue    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                        /* Find HPT ready to run                    */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0);                                            /* No tasks waiting on queue                */
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        POST MESSAGE TO A QUEUE
+*
+* Description: This function sends a message to a queue
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Note(s)    : As of V2.60, this function allows you to send NULL pointer messages.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_EN > 0
+INT8U  OSQPost (OS_EVENT *pevent, void *pmsg)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                     /* See if any task pending on queue             */
+                                                       /* Ready highest priority task waiting on event */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                    /* Find highest priority task ready to run      */
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                   /* Point to queue control block                 */
+    if (pq->OSQEntries >= pq->OSQSize) {               /* Make sure queue is not full                  */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+    }
+    *pq->OSQIn++ = pmsg;                               /* Insert message into queue                    */
+    pq->OSQEntries++;                                  /* Update the nbr of entries in the queue       */
+    if (pq->OSQIn == pq->OSQEnd) {                     /* Wrap IN ptr if we are at end of queue        */
+        pq->OSQIn = pq->OSQStart;
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                   POST MESSAGE TO THE FRONT OF A QUEUE
+*
+* Description: This function sends a message to a queue but unlike OSQPost(), the message is posted at
+*              the front instead of the end of the queue.  Using OSQPostFront() allows you to send
+*              'priority' messages.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Note(s)    : As of V2.60, this function allows you to send NULL pointer messages.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_FRONT_EN > 0
+INT8U  OSQPostFront (OS_EVENT *pevent, void *pmsg)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                    /* See if any task pending on queue              */
+                                                      /* Ready highest priority task waiting on event  */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find highest priority task ready to run       */
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+    }
+    if (pq->OSQOut == pq->OSQStart) {                 /* Wrap OUT ptr if we are at the 1st queue entry */
+        pq->OSQOut = pq->OSQEnd;
+    }
+    pq->OSQOut--;
+    *pq->OSQOut = pmsg;                               /* Insert message into queue                     */
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        POST MESSAGE TO A QUEUE
+*
+* Description: This function sends a message to a queue.  This call has been added to reduce code size
+*              since it can replace both OSQPost() and OSQPostFront().  Also, this function adds the
+*              capability to broadcast a message to ALL tasks waiting on the message queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+*              opt           determines the type of POST performed:
+*                            OS_POST_OPT_NONE         POST to a single waiting task
+*                                                     (Identical to OSQPost())
+*                            OS_POST_OPT_BROADCAST    POST to ALL tasks that are waiting on the queue
+*                            OS_POST_OPT_FRONT        POST as LIFO (Simulates OSQPostFront())
+*                            OS_POST_OPT_NO_SCHED     Indicates that the scheduler will NOT be invoked
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Warning    : Interrupts can be disabled for a long time if you do a 'broadcast'.  In fact, the
+*              interrupt disable time is proportional to the number of tasks waiting on the queue.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_OPT_EN > 0
+INT8U  OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0x00) {                 /* See if any task pending on queue              */
+        if ((opt & OS_POST_OPT_BROADCAST) != 0x00) {  /* Do we need to post msg to ALL waiting tasks ? */
+            while (pevent->OSEventGrp != 0) {         /* Yes, Post to ALL tasks waiting on queue       */
+                (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+            }
+        } else {                                      /* No,  Post to HPT waiting on queue             */
+            (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        }
+        OS_EXIT_CRITICAL();
+        if ((opt & OS_POST_OPT_NO_SCHED) == 0) {	  /* See if scheduler needs to be invoked          */
+            OS_Sched();                               /* Find highest priority task ready to run       */
+        }
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_Q_FULL);
+    }
+    if ((opt & OS_POST_OPT_FRONT) != 0x00) {          /* Do we post to the FRONT of the queue?         */
+        if (pq->OSQOut == pq->OSQStart) {             /* Yes, Post as LIFO, Wrap OUT pointer if we ... */
+            pq->OSQOut = pq->OSQEnd;                  /*      ... are at the 1st queue entry           */
+        }
+        pq->OSQOut--;
+        *pq->OSQOut = pmsg;                           /*      Insert message into queue                */
+    } else {                                          /* No,  Post as FIFO                             */
+        *pq->OSQIn++ = pmsg;                          /*      Insert message into queue                */
+        if (pq->OSQIn == pq->OSQEnd) {                /*      Wrap IN ptr if we are at end of queue    */
+            pq->OSQIn = pq->OSQStart;
+        }
+    }
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        QUERY A MESSAGE QUEUE
+*
+* Description: This function obtains information about a message queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              p_q_data      is a pointer to a structure that will contain information about the message
+*                            queue.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non queue.
+*              OS_ERR_PEVENT_NULL  If 'pevent'   is a NULL pointer
+*              OS_ERR_PDATA_NULL   If 'p_q_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_Q_QUERY_EN > 0
+INT8U  OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data)
+{
+    OS_Q      *pq;
+    INT8U      i;
+#if OS_LOWEST_PRIO <= 63
+    INT8U     *psrc;
+    INT8U     *pdest;
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_q_data == (OS_Q_DATA *)0) {                  /* Validate 'p_q_data'                          */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_q_data->OSEventGrp = pevent->OSEventGrp;         /* Copy message queue wait list                 */
+    psrc                 = &pevent->OSEventTbl[0];
+    pdest                = &p_q_data->OSEventTbl[0];
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;
+    if (pq->OSQEntries > 0) {
+        p_q_data->OSMsg = *pq->OSQOut;                 /* Get next message to return if available      */
+    } else {
+        p_q_data->OSMsg = (void *)0;
+    }
+    p_q_data->OSNMsgs = pq->OSQEntries;
+    p_q_data->OSQSize = pq->OSQSize;
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                 /* OS_Q_QUERY_EN                                */
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      QUEUE MODULE INITIALIZATION
+*
+* Description : This function is called by uC/OS-II to initialize the message queue module.  Your
+*               application MUST NOT call this function.
+*
+* Arguments   :  none
+*
+* Returns     : none
+*
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_QInit (void)
+{
+#if OS_MAX_QS == 1
+    OSQFreeList         = &OSQTbl[0];                /* Only ONE queue!                                */
+    OSQFreeList->OSQPtr = (OS_Q *)0;
+#endif
+
+#if OS_MAX_QS >= 2
+    INT16U  i;
+    OS_Q   *pq1;
+    OS_Q   *pq2;
+
+
+
+    OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl));  /* Clear the queue table                          */
+    pq1 = &OSQTbl[0];
+    pq2 = &OSQTbl[1];
+    for (i = 0; i < (OS_MAX_QS - 1); i++) {          /* Init. list of free QUEUE control blocks        */
+        pq1->OSQPtr = pq2;
+        pq1++;
+        pq2++;
+    }
+    pq1->OSQPtr = (OS_Q *)0;
+    OSQFreeList = &OSQTbl[0];
+#endif
+}
+#endif                                               /* OS_Q_EN                                        */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c
new file mode 100644
index 0000000..b8e159b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_sem.c
@@ -0,0 +1,609 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                          SEMAPHORE MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_SEM.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if OS_SEM_EN > 0
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                           ACCEPT SEMAPHORE
+*
+* Description: This function checks the semaphore to see if a resource is available or, if an event
+*              occurred.  Unlike OSSemPend(), OSSemAccept() does not suspend the calling task if the
+*              resource is not available or the event did not occur.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+* Returns    : >  0       if the resource is available or the event did not occur the semaphore is
+*                         decremented to obtain the resource.
+*              == 0       if the resource is not available or the event did not occur or,
+*                         if 'pevent' is a NULL pointer or,
+*                         if you didn't pass a pointer to a semaphore
+*********************************************************************************************************
+*/
+
+#if OS_SEM_ACCEPT_EN > 0
+INT16U  OSSemAccept (OS_EVENT *pevent)
+{
+    INT16U     cnt;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    cnt = pevent->OSEventCnt;
+    if (cnt > 0) {                                    /* See if resource is available                  */
+        pevent->OSEventCnt--;                         /* Yes, decrement semaphore and notify caller    */
+    }
+    OS_EXIT_CRITICAL();
+    return (cnt);                                     /* Return semaphore count                        */
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                           CREATE A SEMAPHORE
+*
+* Description: This function creates a semaphore.
+*
+* Arguments  : cnt           is the initial value for the semaphore.  If the value is 0, no resource is
+*                            available (or no event has occurred).  You initialize the semaphore to a
+*                            non-zero value to specify how many resources are available (e.g. if you have
+*                            10 resources, you would initialize the semaphore to 10).
+*
+* Returns    : != (void *)0  is a pointer to the event control block (OS_EVENT) associated with the
+*                            created semaphore
+*              == (void *)0  if no event control blocks were available
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSSemCreate (INT16U cnt)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        return ((OS_EVENT *)0);                            /* ... can't CREATE from an ISR             */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                              /* Get next free event control block        */
+    if (OSEventFreeList != (OS_EVENT *)0) {                /* See if pool of free ECB pool was empty   */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {                         /* Get an event control block               */
+        pevent->OSEventType    = OS_EVENT_TYPE_SEM;
+        pevent->OSEventCnt     = cnt;                      /* Set semaphore value                      */
+        pevent->OSEventPtr     = (void *)0;                /* Unlink from ECB free list                */
+#if OS_EVENT_NAME_SIZE > 1
+        pevent->OSEventName[0] = '?';                      /* Unknown name                             */
+        pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+        OS_EventWaitListInit(pevent);                      /* Initialize to 'nobody waiting' on sem.   */
+    }
+    return (pevent);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         DELETE A SEMAPHORE
+*
+* Description: This function deletes a semaphore and readies all tasks pending on the semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete semaphore ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the semaphore even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE             The call was successful and the semaphore was deleted
+*                            OS_ERR_DEL_ISR          If you attempted to delete the semaphore from an ISR
+*                            OS_ERR_INVALID_OPT      An invalid option was specified
+*                            OS_ERR_TASK_WAITING     One or more tasks were waiting on the semaphore
+*                            OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a semaphore
+*                            OS_ERR_PEVENT_NULL      If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the semaphore was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the semaphore MUST check the return code of OSSemPend().
+*              2) OSSemAccept() callers will not know that the intended semaphore has been deleted unless
+*                 they check 'pevent' to see that it's a NULL pointer.
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the semaphore.
+*              4) Because ALL tasks pending on the semaphore will be readied, you MUST be careful in
+*                 applications where the semaphore is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the semaphore.
+*********************************************************************************************************
+*/
+
+#if OS_SEM_DEL_EN > 0
+OS_EVENT  *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                              /* Validate 'perr'                          */
+        return (pevent);
+    }
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (pevent);
+    }
+    if (OSIntNesting > 0) {                                /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                             /* ... can't DELETE from an ISR             */
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                         /* See if any tasks waiting on semaphore    */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete semaphore only if no task waiting */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_SIZE > 1
+                 pevent->OSEventName[0] = '?';             /* Unknown name                             */
+                 pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt     = 0;
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+                 pevent_return          = (OS_EVENT *)0;   /* Semaphore has been deleted               */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the semaphore              */
+             while (pevent->OSEventGrp != 0) {             /* Ready ALL tasks waiting for semaphore    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK);
+             }
+#if OS_EVENT_NAME_SIZE > 1
+             pevent->OSEventName[0] = '?';                 /* Unknown name                             */
+             pevent->OSEventName[1] = OS_ASCII_NUL;
+#endif
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr                  = OS_ERR_NONE;
+             pevent_return          = (OS_EVENT *)0;       /* Semaphore has been deleted               */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+             pevent_return          = pevent;
+             break;
+    }
+    return (pevent_return);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                           PEND ON SEMAPHORE
+*
+* Description: This function waits for a semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for the resource up to the amount of time specified by this argument.
+*                            If you specify 0, however, your task will wait forever at the specified
+*                            semaphore or, until the resource becomes available (or the event occurs).
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task owns the resource
+*                                                or, the event you are waiting for occurred.
+*                            OS_ERR_TIMEOUT      The semaphore was not received within the specified
+*                                                'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the semaphore was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*                            OS_ERR_PEND_LOCKED  If you called this function when the scheduler is locked
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+/*$PAGE*/
+void  OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr)
+{
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return;
+    }
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return;
+    }
+    if (OSIntNesting > 0) {                           /* See if called from ISR ...                    */
+        *perr = OS_ERR_PEND_ISR;                      /* ... can't PEND from an ISR                    */
+        return;
+    }
+    if (OSLockNesting > 0) {                          /* See if called with scheduler locked ...       */
+        *perr = OS_ERR_PEND_LOCKED;                   /* ... can't PEND when locked                    */
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventCnt > 0) {                     /* If sem. is positive, resource available ...   */
+        pevent->OSEventCnt--;                         /* ... decrement semaphore only if positive.     */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        return;
+    }
+                                                      /* Otherwise, must wait until event occurs       */
+    OSTCBCur->OSTCBStat     |= OS_STAT_SEM;           /* Resource not available, pend on semaphore     */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Store pend timeout in TCB                     */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:        
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+#endif
+    OS_EXIT_CRITICAL();
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                      ABORT WAITING ON A SEMAPHORE
+*
+* Description: This function aborts & readies any tasks currently waiting on a semaphore.  This function 
+*              should be used to fault-abort the wait on the semaphore, rather than to normally signal
+*              the semaphore via OSSemPost().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     semaphore
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     semaphore
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the semaphore.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the semaphore was readied
+*                                                and informed of the aborted wait; check return value 
+*                                                for the number of tasks whose wait on the semaphore 
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the semaphore, or upon error.
+*              >  0          if one or more tasks waiting on the semaphore are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_SEM_PEND_ABORT_EN > 0
+INT8U  OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return (0);
+    }
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                    /* See if any task waiting on semaphore?         */
+        nbr_tasks = 0;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:               /* Do we need to abort ALL waiting tasks?        */
+                 while (pevent->OSEventGrp != 0) {    /* Yes, ready ALL tasks waiting on semaphore     */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+                 
+            case OS_PEND_OPT_NONE:
+            default:                                  /* No,  ready HPT       waiting on semaphore     */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0);                                       /* No tasks waiting on semaphore                 */
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         POST TO A SEMAPHORE
+*
+* Description: This function signals a semaphore
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the semaphore was signaled.
+*              OS_ERR_SEM_OVF      If the semaphore count exceeded its limit.  In other words, you have
+*                                  signalled the semaphore more often than you waited on it with either
+*                                  OSSemAccept() or OSSemPend().
+*              OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore
+*              OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+INT8U  OSSemPost (OS_EVENT *pevent)
+{
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0) {                    /* See if any task waiting for semaphore         */
+                                                      /* Ready HPT waiting on event                    */
+        (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventCnt < 65535u) {                /* Make sure semaphore will not overflow         */
+        pevent->OSEventCnt++;                         /* Increment semaphore count to register event   */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_NONE);
+    }
+    OS_EXIT_CRITICAL();                               /* Semaphore value has reached its maximum       */
+    return (OS_ERR_SEM_OVF);
+}
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                          QUERY A SEMAPHORE
+*
+* Description: This function obtains information about a semaphore
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore
+*
+*              p_sem_data    is a pointer to a structure that will contain information about the
+*                            semaphore.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non semaphore.
+*              OS_ERR_PEVENT_NULL  If 'pevent'     is a NULL pointer.
+*              OS_ERR_PDATA_NULL   If 'p_sem_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_SEM_QUERY_EN > 0
+INT8U  OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data)
+{
+#if OS_LOWEST_PRIO <= 63
+    INT8U     *psrc;
+    INT8U     *pdest;
+#else
+    INT16U    *psrc;
+    INT16U    *pdest;
+#endif
+    INT8U      i;
+#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_sem_data == (OS_SEM_DATA *)0) {                  /* Validate 'p_sem_data'                    */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_sem_data->OSEventGrp = pevent->OSEventGrp;           /* Copy message mailbox wait list           */
+    psrc                   = &pevent->OSEventTbl[0];
+    pdest                  = &p_sem_data->OSEventTbl[0];
+    for (i = 0; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    p_sem_data->OSCnt = pevent->OSEventCnt;                /* Get semaphore count                      */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_SEM_QUERY_EN                          */
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                              SET SEMAPHORE
+*
+* Description: This function sets the semaphore count to the value specified as an argument.  Typically,
+*              this value would be 0.
+*
+*              You would typically use this function when a semaphore is used as a signaling mechanism
+*              and, you want to reset the count value.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+*              cnt        is the new value for the semaphore count.  You would pass 0 to reset the
+*                         semaphore count.
+*
+*              perr       is a pointer to an error code returned by the function as follows:
+*
+*                            OS_ERR_NONE          The call was successful and the semaphore value was set.
+*                            OS_ERR_EVENT_TYPE    If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer.
+*                            OS_ERR_TASK_WAITING  If tasks are waiting on the semaphore.
+*********************************************************************************************************
+*/
+
+#if OS_SEM_SET_EN > 0
+void  OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr)
+{
+#if OS_CRITICAL_METHOD == 3                           /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                         /* Validate 'perr'                               */
+        return;
+    }
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    *perr = OS_ERR_NONE;
+    if (pevent->OSEventCnt > 0) {                     /* See if semaphore already has a count          */
+        pevent->OSEventCnt = cnt;                     /* Yes, set it to the new value specified.       */
+    } else {                                          /* No                                            */
+        if (pevent->OSEventGrp == 0) {                /*      See if task(s) waiting?                  */
+            pevent->OSEventCnt = cnt;                 /*      No, OK to set the value                  */
+        } else {
+            *perr              = OS_ERR_TASK_WAITING;
+        }
+    }
+    OS_EXIT_CRITICAL();
+}
+#endif
+
+#endif                                                /* OS_SEM_EN                                     */
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c
new file mode 100644
index 0000000..72bac53
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_task.c
@@ -0,0 +1,1095 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                            TASK MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_TASK.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        CHANGE PRIORITY OF A TASK
+*
+* Description: This function allows you to change the priority of a task dynamically.  Note that the new
+*              priority MUST be available.
+*
+* Arguments  : oldp     is the old priority
+*
+*              newp     is the new priority
+*
+* Returns    : OS_ERR_NONE            is the call was successful
+*              OS_ERR_PRIO_INVALID    if the priority you specify is higher that the maximum allowed
+*                                     (i.e. >= OS_LOWEST_PRIO)
+*              OS_ERR_PRIO_EXIST      if the new priority already exist.
+*              OS_ERR_PRIO            there is no task with the specified OLD priority (i.e. the OLD task does
+*                                     not exist.
+*              OS_ERR_TASK_NOT_EXIST  if the task is assigned to a Mutex PIP.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_CHANGE_PRIO_EN > 0
+INT8U  OSTaskChangePrio (INT8U oldprio, INT8U newprio)
+{
+#if (OS_EVENT_EN)
+    OS_EVENT  *pevent;
+#if (OS_EVENT_MULTI_EN > 0)
+    OS_EVENT **pevents;
+#endif
+#endif
+    OS_TCB    *ptcb;
+    INT8U      y_new;
+    INT8U      x_new;
+    INT8U      y_old;
+#if OS_LOWEST_PRIO <= 63
+    INT8U      bity_new;
+    INT8U      bitx_new;
+    INT8U      bity_old;
+    INT8U      bitx_old;
+#else
+    INT16U     bity_new;
+    INT16U     bitx_new;
+    INT16U     bity_old;
+    INT16U     bitx_old;
+#endif
+#if OS_CRITICAL_METHOD == 3
+    OS_CPU_SR  cpu_sr = 0;                                  /* Storage for CPU status register         */
+#endif
+
+
+/*$PAGE*/
+#if OS_ARG_CHK_EN > 0
+    if (oldprio >= OS_LOWEST_PRIO) {
+        if (oldprio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+    if (newprio >= OS_LOWEST_PRIO) {
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) {             /* New priority must not already exist     */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_PRIO_EXIST);
+    }
+    if (oldprio == OS_PRIO_SELF) {                          /* See if changing self                    */
+        oldprio = OSTCBCur->OSTCBPrio;                      /* Yes, get priority                       */
+    }
+    ptcb = OSTCBPrioTbl[oldprio];
+    if (ptcb == (OS_TCB *)0) {                              /* Does task to change exist?              */
+        OS_EXIT_CRITICAL();                                 /* No, can't change its priority!          */
+        return (OS_ERR_PRIO);
+    }
+    if (ptcb == OS_TCB_RESERVED) {                          /* Is task assigned to Mutex               */
+        OS_EXIT_CRITICAL();                                 /* No, can't change its priority!          */
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+#if OS_LOWEST_PRIO <= 63
+    y_new                 = (INT8U)(newprio >> 3);          /* Yes, compute new TCB fields             */
+    x_new                 = (INT8U)(newprio & 0x07);
+    bity_new              = (INT8U)(1 << y_new);
+    bitx_new              = (INT8U)(1 << x_new);
+#else
+    y_new                 = (INT8U)((newprio >> 4) & 0x0F);
+    x_new                 = (INT8U)( newprio & 0x0F);
+    bity_new              = (INT16U)(1 << y_new);
+    bitx_new              = (INT16U)(1 << x_new);
+#endif
+
+    OSTCBPrioTbl[oldprio] = (OS_TCB *)0;                    /* Remove TCB from old priority            */
+    OSTCBPrioTbl[newprio] =  ptcb;                          /* Place pointer to TCB @ new priority     */
+    y_old                 =  ptcb->OSTCBY;
+    bity_old              =  ptcb->OSTCBBitY;
+    bitx_old              =  ptcb->OSTCBBitX;
+    if ((OSRdyTbl[y_old] &   bitx_old) != 0) {              /* If task is ready make it not            */
+         OSRdyTbl[y_old] &= ~bitx_old;
+         if (OSRdyTbl[y_old] == 0) {
+             OSRdyGrp &= ~bity_old;
+         }
+         OSRdyGrp        |= bity_new;                       /* Make new priority ready to run          */
+         OSRdyTbl[y_new] |= bitx_new;
+    }
+
+#if (OS_EVENT_EN)
+    pevent = ptcb->OSTCBEventPtr;
+    if (pevent != (OS_EVENT *)0) {
+        pevent->OSEventTbl[y_old] &= ~bitx_old;             /* Remove old task prio from wait list     */
+        if (pevent->OSEventTbl[y_old] == 0) {
+            pevent->OSEventGrp    &= ~bity_old;
+        }
+        pevent->OSEventGrp        |= bity_new;              /* Add    new task prio to   wait list     */
+        pevent->OSEventTbl[y_new] |= bitx_new;
+    }
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {
+        pevents =  ptcb->OSTCBEventMultiPtr;
+        pevent  = *pevents;
+        while (pevent != (OS_EVENT *)0) {
+            pevent->OSEventTbl[y_old] &= ~bitx_old;         /* Remove old task prio from wait lists    */
+            if (pevent->OSEventTbl[y_old] == 0) {
+                pevent->OSEventGrp    &= ~bity_old;
+            }
+            pevent->OSEventGrp        |= bity_new;          /* Add    new task prio to   wait lists    */
+            pevent->OSEventTbl[y_new] |= bitx_new;
+            pevents++;
+            pevent                     = *pevents;
+        }
+    }
+#endif
+#endif
+
+    ptcb->OSTCBPrio = newprio;                              /* Set new task priority                   */
+    ptcb->OSTCBY    = y_new;
+    ptcb->OSTCBX    = x_new;
+    ptcb->OSTCBBitY = bity_new;
+    ptcb->OSTCBBitX = bitx_new;
+    OS_EXIT_CRITICAL();
+    if (OSRunning == OS_TRUE) {
+        OS_Sched();                                         /* Find new highest priority task          */
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            CREATE A TASK
+*
+* Description: This function is used to have uC/OS-II manage the execution of a task.  Tasks can either
+*              be created prior to the start of multitasking or by a running task.  A task cannot be
+*              created by an ISR.
+*
+* Arguments  : task     is a pointer to the task's code
+*
+*              p_arg    is a pointer to an optional data area which can be used to pass parameters to
+*                       the task when the task first executes.  Where the task is concerned it thinks
+*                       it was invoked and passed the argument 'p_arg' as follows:
+*
+*                           void Task (void *p_arg)
+*                           {
+*                               for (;;) {
+*                                   Task code;
+*                               }
+*                           }
+*
+*              ptos     is a pointer to the task's top of stack.  If the configuration constant
+*                       OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high
+*                       memory to low memory).  'pstk' will thus point to the highest (valid) memory
+*                       location of the stack.  If OS_STK_GROWTH is set to 0, 'pstk' will point to the
+*                       lowest memory location of the stack and the stack will grow with increasing
+*                       memory locations.
+*
+*              prio     is the task's priority.  A unique priority MUST be assigned to each task and the
+*                       lower the number, the higher the priority.
+*
+* Returns    : OS_ERR_NONE             if the function was successful.
+*              OS_PRIO_EXIT            if the task priority already exist
+*                                      (each task MUST have a unique priority).
+*              OS_ERR_PRIO_INVALID     if the priority you specify is higher that the maximum allowed
+*                                      (i.e. >= OS_LOWEST_PRIO)
+*              OS_ERR_TASK_CREATE_ISR  if you tried to create a task from an ISR.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_CREATE_EN > 0
+INT8U  OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio)
+{
+    OS_STK    *psp;
+    INT8U      err;
+#if OS_CRITICAL_METHOD == 3                  /* Allocate storage for CPU status register               */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {             /* Make sure priority is within allowable range           */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (OSIntNesting > 0) {                  /* Make sure we don't create the task from within an ISR  */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_CREATE_ISR);
+    }
+    if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority  */
+        OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ...  */
+                                             /* ... the same thing until task is created.              */
+        OS_EXIT_CRITICAL();
+        psp = OSTaskStkInit(task, p_arg, ptos, 0);              /* Initialize the task's stack         */
+        err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0);
+        if (err == OS_ERR_NONE) {
+            if (OSRunning == OS_TRUE) {      /* Find highest priority task if multitasking has started */
+                OS_Sched();
+            }
+        } else {
+            OS_ENTER_CRITICAL();
+            OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others                 */
+            OS_EXIT_CRITICAL();
+        }
+        return (err);
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_PRIO_EXIST);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                     CREATE A TASK (Extended Version)
+*
+* Description: This function is used to have uC/OS-II manage the execution of a task.  Tasks can either
+*              be created prior to the start of multitasking or by a running task.  A task cannot be
+*              created by an ISR.  This function is similar to OSTaskCreate() except that it allows
+*              additional information about a task to be specified.
+*
+* Arguments  : task      is a pointer to the task's code
+*
+*              p_arg     is a pointer to an optional data area which can be used to pass parameters to
+*                        the task when the task first executes.  Where the task is concerned it thinks
+*                        it was invoked and passed the argument 'p_arg' as follows:
+*
+*                            void Task (void *p_arg)
+*                            {
+*                                for (;;) {
+*                                    Task code;
+*                                }
+*                            }
+*
+*              ptos      is a pointer to the task's top of stack.  If the configuration constant
+*                        OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high
+*                        memory to low memory).  'ptos' will thus point to the highest (valid) memory
+*                        location of the stack.  If OS_STK_GROWTH is set to 0, 'ptos' will point to the
+*                        lowest memory location of the stack and the stack will grow with increasing
+*                        memory locations.  'ptos' MUST point to a valid 'free' data item.
+*
+*              prio      is the task's priority.  A unique priority MUST be assigned to each task and the
+*                        lower the number, the higher the priority.
+*
+*              id        is the task's ID (0..65535)
+*
+*              pbos      is a pointer to the task's bottom of stack.  If the configuration constant
+*                        OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high
+*                        memory to low memory).  'pbos' will thus point to the LOWEST (valid) memory
+*                        location of the stack.  If OS_STK_GROWTH is set to 0, 'pbos' will point to the
+*                        HIGHEST memory location of the stack and the stack will grow with increasing
+*                        memory locations.  'pbos' MUST point to a valid 'free' data item.
+*
+*              stk_size  is the size of the stack in number of elements.  If OS_STK is set to INT8U,
+*                        'stk_size' corresponds to the number of bytes available.  If OS_STK is set to
+*                        INT16U, 'stk_size' contains the number of 16-bit entries available.  Finally, if
+*                        OS_STK is set to INT32U, 'stk_size' contains the number of 32-bit entries
+*                        available on the stack.
+*
+*              pext      is a pointer to a user supplied memory location which is used as a TCB extension.
+*                        For example, this user memory can hold the contents of floating-point registers
+*                        during a context switch, the time each task takes to execute, the number of times
+*                        the task has been switched-in, etc.
+*
+*              opt       contains additional information (or options) about the behavior of the task.  The
+*                        LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application
+*                        specific.  See OS_TASK_OPT_??? in uCOS-II.H.  Current choices are:
+*
+*                        OS_TASK_OPT_STK_CHK      Stack checking to be allowed for the task
+*                        OS_TASK_OPT_STK_CLR      Clear the stack when the task is created
+*                        OS_TASK_OPT_SAVE_FP      If the CPU has floating-point registers, save them
+*                                                 during a context switch.
+*
+* Returns    : OS_ERR_NONE             if the function was successful.
+*              OS_PRIO_EXIT            if the task priority already exist
+*                                      (each task MUST have a unique priority).
+*              OS_ERR_PRIO_INVALID     if the priority you specify is higher that the maximum allowed
+*                                      (i.e. > OS_LOWEST_PRIO)
+*              OS_ERR_TASK_CREATE_ISR  if you tried to create a task from an ISR.
+*********************************************************************************************************
+*/
+/*$PAGE*/
+#if OS_TASK_CREATE_EXT_EN > 0
+INT8U  OSTaskCreateExt (void   (*task)(void *p_arg),
+                        void    *p_arg,
+                        OS_STK  *ptos,
+                        INT8U    prio,
+                        INT16U   id,
+                        OS_STK  *pbos,
+                        INT32U   stk_size,
+                        void    *pext,
+                        INT16U   opt)
+{
+    OS_STK    *psp;
+    INT8U      err;
+#if OS_CRITICAL_METHOD == 3                  /* Allocate storage for CPU status register               */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {             /* Make sure priority is within allowable range           */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (OSIntNesting > 0) {                  /* Make sure we don't create the task from within an ISR  */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_CREATE_ISR);
+    }
+    if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority  */
+        OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ...  */
+                                             /* ... the same thing until task is created.              */
+        OS_EXIT_CRITICAL();
+
+#if (OS_TASK_STAT_STK_CHK_EN > 0)
+        OS_TaskStkClr(pbos, stk_size, opt);                    /* Clear the task stack (if needed)     */
+#endif
+
+        psp = OSTaskStkInit(task, p_arg, ptos, opt);           /* Initialize the task's stack          */
+        err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt);
+        if (err == OS_ERR_NONE) {
+            if (OSRunning == OS_TRUE) {                        /* Find HPT if multitasking has started */
+                OS_Sched();
+            }
+        } else {
+            OS_ENTER_CRITICAL();
+            OSTCBPrioTbl[prio] = (OS_TCB *)0;                  /* Make this priority avail. to others  */
+            OS_EXIT_CRITICAL();
+        }
+        return (err);
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_PRIO_EXIST);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            DELETE A TASK
+*
+* Description: This function allows you to delete a task.  The calling task can delete itself by
+*              its own priority number.  The deleted task is returned to the dormant state and can be
+*              re-activated by creating the deleted task again.
+*
+* Arguments  : prio    is the priority of the task to delete.  Note that you can explicitely delete
+*                      the current task without knowing its priority level by setting 'prio' to
+*                      OS_PRIO_SELF.
+*
+* Returns    : OS_ERR_NONE             if the call is successful
+*              OS_ERR_TASK_DEL_IDLE    if you attempted to delete uC/OS-II's idle task
+*              OS_ERR_PRIO_INVALID     if the priority you specify is higher that the maximum allowed
+*                                      (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF.
+*              OS_ERR_TASK_DEL         if the task is assigned to a Mutex PIP.   
+*              OS_ERR_TASK_NOT_EXIST   if the task you want to delete does not exist.
+*              OS_ERR_TASK_DEL_ISR     if you tried to delete a task from an ISR
+*
+* Notes      : 1) To reduce interrupt latency, OSTaskDel() 'disables' the task:
+*                    a) by making it not ready
+*                    b) by removing it from any wait lists
+*                    c) by preventing OSTimeTick() from making the task ready to run.
+*                 The task can then be 'unlinked' from the miscellaneous structures in uC/OS-II.
+*              2) The function OS_Dummy() is called after OS_EXIT_CRITICAL() because, on most processors,
+*                 the next instruction following the enable interrupt instruction is ignored.
+*              3) An ISR cannot delete a task.
+*              4) The lock nesting counter is incremented because, for a brief instant, if the current
+*                 task is being deleted, the current task would not be able to be rescheduled because it
+*                 is removed from the ready list.  Incrementing the nesting counter prevents another task
+*                 from being schedule.  This means that an ISR would return to the current task which is
+*                 being deleted.  The rest of the deletion would thus be able to be completed.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_DEL_EN > 0
+INT8U  OSTaskDel (INT8U prio)
+{
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    OS_FLAG_NODE *pnode;
+#endif
+    OS_TCB       *ptcb;
+#if OS_CRITICAL_METHOD == 3                             /* Allocate storage for CPU status register    */
+    OS_CPU_SR     cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                             /* See if trying to delete from ISR            */
+        return (OS_ERR_TASK_DEL_ISR);
+    }
+    if (prio == OS_TASK_IDLE_PRIO) {                    /* Not allowed to delete idle task             */
+        return (OS_ERR_TASK_DEL_IDLE);
+    }
+#if OS_ARG_CHK_EN > 0
+    if (prio >= OS_LOWEST_PRIO) {                       /* Task priority valid ?                       */
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+#endif
+
+/*$PAGE*/
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                         /* See if requesting to delete self            */
+        prio = OSTCBCur->OSTCBPrio;                     /* Set priority to delete to current           */
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                          /* Task to delete must exist                   */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+    if (ptcb == OS_TCB_RESERVED) {                      /* Must not be assigned to Mutex               */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_DEL);
+    }
+
+    OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX;
+    if (OSRdyTbl[ptcb->OSTCBY] == 0) {                  /* Make task not ready                         */
+        OSRdyGrp           &= ~ptcb->OSTCBBitY;
+    }
+    
+#if (OS_EVENT_EN)
+    if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) {
+        OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr);  /* Remove this task from any event   wait list */
+    }
+#if (OS_EVENT_MULTI_EN > 0)
+    if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) {   /* Remove this task from any events' wait lists*/
+        OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr);
+    }
+#endif
+#endif
+
+#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0)
+    pnode = ptcb->OSTCBFlagNode;
+    if (pnode != (OS_FLAG_NODE *)0) {                   /* If task is waiting on event flag            */
+        OS_FlagUnlink(pnode);                           /* Remove from wait list                       */
+    }
+#endif
+
+    ptcb->OSTCBDly      = 0;                            /* Prevent OSTimeTick() from updating          */
+    ptcb->OSTCBStat     = OS_STAT_RDY;                  /* Prevent task from being resumed             */
+    ptcb->OSTCBStatPend = OS_STAT_PEND_OK;
+    if (OSLockNesting < 255u) {                         /* Make sure we don't context switch           */
+        OSLockNesting++;
+    }
+    OS_EXIT_CRITICAL();                                 /* Enabling INT. ignores next instruc.         */
+    OS_Dummy();                                         /* ... Dummy ensures that INTs will be         */
+    OS_ENTER_CRITICAL();                                /* ... disabled HERE!                          */
+    if (OSLockNesting > 0) {                            /* Remove context switch lock                  */
+        OSLockNesting--;
+    }
+    OSTaskDelHook(ptcb);                                /* Call user defined hook                      */
+    OSTaskCtr--;                                        /* One less task being managed                 */
+    OSTCBPrioTbl[prio] = (OS_TCB *)0;                   /* Clear old priority entry                    */
+    if (ptcb->OSTCBPrev == (OS_TCB *)0) {               /* Remove from TCB chain                       */
+        ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0;
+        OSTCBList                  = ptcb->OSTCBNext;
+    } else {
+        ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext;
+        ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev;
+    }
+    ptcb->OSTCBNext   = OSTCBFreeList;                  /* Return TCB to free TCB list                 */
+    OSTCBFreeList     = ptcb;
+#if OS_TASK_NAME_SIZE > 1
+    ptcb->OSTCBTaskName[0] = '?';                       /* Unknown name                                */
+    ptcb->OSTCBTaskName[1] = OS_ASCII_NUL;
+#endif
+    OS_EXIT_CRITICAL();
+    if (OSRunning == OS_TRUE) {
+        OS_Sched();                                     /* Find new highest priority task              */
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                    REQUEST THAT A TASK DELETE ITSELF
+*
+* Description: This function is used to:
+*                   a) notify a task to delete itself.
+*                   b) to see if a task requested that the current task delete itself.
+*              This function is a little tricky to understand.  Basically, you have a task that needs
+*              to be deleted however, this task has resources that it has allocated (memory buffers,
+*              semaphores, mailboxes, queues etc.).  The task cannot be deleted otherwise these
+*              resources would not be freed.  The requesting task calls OSTaskDelReq() to indicate that
+*              the task needs to be deleted.  Deleting of the task is however, deferred to the task to
+*              be deleted.  For example, suppose that task #10 needs to be deleted.  The requesting task
+*              example, task #5, would call OSTaskDelReq(10).  When task #10 gets to execute, it calls
+*              this function by specifying OS_PRIO_SELF and monitors the returned value.  If the return
+*              value is OS_ERR_TASK_DEL_REQ, another task requested a task delete.  Task #10 would look like
+*              this:
+*
+*                   void Task(void *p_arg)
+*                   {
+*                       .
+*                       .
+*                       while (1) {
+*                           OSTimeDly(1);
+*                           if (OSTaskDelReq(OS_PRIO_SELF) == OS_ERR_TASK_DEL_REQ) {
+*                               Release any owned resources;
+*                               De-allocate any dynamic memory;
+*                               OSTaskDel(OS_PRIO_SELF);
+*                           }
+*                       }
+*                   }
+*
+* Arguments  : prio    is the priority of the task to request the delete from
+*
+* Returns    : OS_ERR_NONE            if the task exist and the request has been registered
+*              OS_ERR_TASK_NOT_EXIST  if the task has been deleted.  This allows the caller to know whether
+*                                     the request has been executed.
+*              OS_ERR_TASK_DEL        if the task is assigned to a Mutex.
+*              OS_ERR_TASK_DEL_IDLE   if you requested to delete uC/OS-II's idle task
+*              OS_ERR_PRIO_INVALID    if the priority you specify is higher that the maximum allowed
+*                                     (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF.
+*              OS_ERR_TASK_DEL_REQ    if a task (possibly another task) requested that the running task be
+*                                     deleted.
+*********************************************************************************************************
+*/
+/*$PAGE*/
+#if OS_TASK_DEL_EN > 0
+INT8U  OSTaskDelReq (INT8U prio)
+{
+    INT8U      stat;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (prio == OS_TASK_IDLE_PRIO) {                            /* Not allowed to delete idle task     */
+        return (OS_ERR_TASK_DEL_IDLE);
+    }
+#if OS_ARG_CHK_EN > 0
+    if (prio >= OS_LOWEST_PRIO) {                               /* Task priority valid ?               */
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+#endif
+    if (prio == OS_PRIO_SELF) {                                 /* See if a task is requesting to ...  */
+        OS_ENTER_CRITICAL();                                    /* ... this task to delete itself      */
+        stat = OSTCBCur->OSTCBDelReq;                           /* Return request status to caller     */
+        OS_EXIT_CRITICAL();
+        return (stat);
+    }
+    OS_ENTER_CRITICAL();
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                                  /* Task to delete must exist           */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                         /* Task must already be deleted        */
+    }
+    if (ptcb == OS_TCB_RESERVED) {                              /* Must NOT be assigned to a Mutex     */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_DEL);
+    }
+    ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ;                    /* Set flag indicating task to be DEL. */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        GET THE NAME OF A TASK
+*
+* Description: This function is called to obtain the name of a task.
+*
+* Arguments  : prio      is the priority of the task that you want to obtain the name from.
+*
+*              pname     is a pointer to an ASCII string that will receive the name of the task.  The
+*                        string must be able to hold at least OS_TASK_NAME_SIZE characters.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the requested task is resumed
+*                        OS_ERR_TASK_NOT_EXIST      if the task has not been created or is assigned to a Mutex
+*                        OS_ERR_PRIO_INVALID        if you specified an invalid priority:
+*                                                   A higher value than the idle task or not OS_PRIO_SELF.
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_NAME_GET_ISR        You called this function from an ISR
+*                        
+*
+* Returns    : The length of the string or 0 if the task does not exist.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_NAME_SIZE > 1
+INT8U  OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr)
+{
+    OS_TCB    *ptcb;
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3                              /* Allocate storage for CPU status register   */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                            /* Validate 'perr'                            */
+        return (0);
+    }
+    if (prio > OS_LOWEST_PRIO) {                         /* Task priority valid ?                      */
+        if (prio != OS_PRIO_SELF) {
+            *perr = OS_ERR_PRIO_INVALID;                 /* No                                         */
+            return (0);
+        }
+    }
+    if (pname == (INT8U *)0) {                           /* Is 'pname' a NULL pointer?                 */
+        *perr = OS_ERR_PNAME_NULL;                       /* Yes                                        */
+        return (0);
+    }
+#endif
+    if (OSIntNesting > 0) {                              /* See if trying to call from an ISR          */
+        *perr = OS_ERR_NAME_GET_ISR;
+        return (0);
+    }
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                          /* See if caller desires it's own name        */
+        prio = OSTCBCur->OSTCBPrio;
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                           /* Does task exist?                           */
+        OS_EXIT_CRITICAL();                              /* No                                         */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+        return (0);
+    }
+    if (ptcb == OS_TCB_RESERVED) {                       /* Task assigned to a Mutex?                  */
+        OS_EXIT_CRITICAL();                              /* Yes                                        */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+        return (0);
+    }
+    len   = OS_StrCopy(pname, ptcb->OSTCBTaskName);      /* Yes, copy name from TCB                    */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (len);
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        ASSIGN A NAME TO A TASK
+*
+* Description: This function is used to set the name of a task.
+*
+* Arguments  : prio      is the priority of the task that you want the assign a name to.
+*
+*              pname     is a pointer to an ASCII string that contains the name of the task.  The ASCII
+*                        string must be NUL terminated.
+*
+*              perr       is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the requested task is resumed
+*                        OS_ERR_TASK_NOT_EXIST      if the task has not been created or is assigned to a Mutex
+*                        OS_ERR_TASK_NAME_TOO_LONG  if the name you are giving to the task exceeds the
+*                                                   storage capacity of a task name as specified by
+*                                                   OS_TASK_NAME_SIZE.
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_PRIO_INVALID        if you specified an invalid priority:
+*                                                   A higher value than the idle task or not OS_PRIO_SELF.
+*                        OS_ERR_NAME_SET_ISR        if you called this function from an ISR
+*
+* Returns    : None
+*********************************************************************************************************
+*/
+#if OS_TASK_NAME_SIZE > 1
+void  OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr)
+{
+    INT8U      len;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                          /* Allocate storage for CPU status register       */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                        /* Validate 'perr'                                */
+        return;
+    }
+    if (prio > OS_LOWEST_PRIO) {                     /* Task priority valid ?                          */
+        if (prio != OS_PRIO_SELF) {
+            *perr = OS_ERR_PRIO_INVALID;             /* No                                             */
+            return;
+        }
+    }
+    if (pname == (INT8U *)0) {                       /* Is 'pname' a NULL pointer?                     */
+        *perr = OS_ERR_PNAME_NULL;                   /* Yes                                            */
+        return;
+    }
+#endif
+    if (OSIntNesting > 0) {                          /* See if trying to call from an ISR              */
+        *perr = OS_ERR_NAME_SET_ISR;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                      /* See if caller desires to set it's own name     */
+        prio = OSTCBCur->OSTCBPrio;
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                       /* Does task exist?                               */
+        OS_EXIT_CRITICAL();                          /* No                                             */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+        return;
+    }
+    if (ptcb == OS_TCB_RESERVED) {                   /* Task assigned to a Mutex?                      */
+        OS_EXIT_CRITICAL();                          /* Yes                                            */
+        *perr = OS_ERR_TASK_NOT_EXIST;
+        return;
+    }
+    len = OS_StrLen(pname);                          /* Yes, Can we fit the string in the TCB?         */
+    if (len > (OS_TASK_NAME_SIZE - 1)) {             /*      No                                        */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_TASK_NAME_TOO_LONG;
+        return;
+    }
+    (void)OS_StrCopy(ptcb->OSTCBTaskName, pname);    /*      Yes, copy to TCB                          */
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+}
+#endif
+
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        RESUME A SUSPENDED TASK
+*
+* Description: This function is called to resume a previously suspended task.  This is the only call that
+*              will remove an explicit task suspension.
+*
+* Arguments  : prio     is the priority of the task to resume.
+*
+* Returns    : OS_ERR_NONE                if the requested task is resumed
+*              OS_ERR_PRIO_INVALID        if the priority you specify is higher that the maximum allowed
+*                                         (i.e. >= OS_LOWEST_PRIO)
+*              OS_ERR_TASK_RESUME_PRIO    if the task to resume does not exist
+*              OS_ERR_TASK_NOT_EXIST      if the task is assigned to a Mutex PIP
+*              OS_ERR_TASK_NOT_SUSPENDED  if the task to resume has not been suspended
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SUSPEND_EN > 0
+INT8U  OSTaskResume (INT8U prio)
+{
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                   /* Storage for CPU status register       */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio >= OS_LOWEST_PRIO) {                             /* Make sure task priority is valid      */
+        return (OS_ERR_PRIO_INVALID);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                                /* Task to suspend must exist            */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_RESUME_PRIO);
+    }
+    if (ptcb == OS_TCB_RESERVED) {                            /* See if assigned to Mutex              */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended                */
+        ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND;           /* Remove suspension                     */
+        if (ptcb->OSTCBStat == OS_STAT_RDY) {                 /* See if task is now ready              */
+            if (ptcb->OSTCBDly == 0) {
+                OSRdyGrp               |= ptcb->OSTCBBitY;    /* Yes, Make task ready to run           */
+                OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+                OS_EXIT_CRITICAL();
+                if (OSRunning == OS_TRUE) {
+                    OS_Sched();                               /* Find new highest priority task        */
+                }
+            } else {
+                OS_EXIT_CRITICAL();
+            }
+        } else {                                              /* Must be pending on event              */
+            OS_EXIT_CRITICAL();
+        }
+        return (OS_ERR_NONE);
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_TASK_NOT_SUSPENDED);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                             STACK CHECKING
+*
+* Description: This function is called to check the amount of free memory left on the specified task's
+*              stack.
+*
+* Arguments  : prio          is the task priority
+*
+*              p_stk_data    is a pointer to a data structure of type OS_STK_DATA.
+*
+* Returns    : OS_ERR_NONE            upon success
+*              OS_ERR_PRIO_INVALID    if the priority you specify is higher that the maximum allowed
+*                                     (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF.
+*              OS_ERR_TASK_NOT_EXIST  if the desired task has not been created or is assigned to a Mutex PIP
+*              OS_ERR_TASK_OPT        if you did NOT specified OS_TASK_OPT_STK_CHK when the task was created
+*              OS_ERR_PDATA_NULL      if 'p_stk_data' is a NULL pointer
+*********************************************************************************************************
+*/
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+INT8U  OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data)
+{
+    OS_TCB    *ptcb;
+    OS_STK    *pchk;
+    INT32U     nfree;
+    INT32U     size;
+#if OS_CRITICAL_METHOD == 3                            /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {                       /* Make sure task priority is valid             */
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+    if (p_stk_data == (OS_STK_DATA *)0) {              /* Validate 'p_stk_data'                        */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    p_stk_data->OSFree = 0;                            /* Assume failure, set to 0 size                */
+    p_stk_data->OSUsed = 0;
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                        /* See if check for SELF                        */
+        prio = OSTCBCur->OSTCBPrio;
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                         /* Make sure task exist                         */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+    if (ptcb == OS_TCB_RESERVED) {
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+    if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set       */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_OPT);
+    }
+    nfree = 0;
+    size  = ptcb->OSTCBStkSize;
+    pchk  = ptcb->OSTCBStkBottom;
+    OS_EXIT_CRITICAL();
+#if OS_STK_GROWTH == 1
+    while (*pchk++ == (OS_STK)0) {                    /* Compute the number of zero entries on the stk */
+        nfree++;
+    }
+#else
+    while (*pchk-- == (OS_STK)0) {
+        nfree++;
+    }
+#endif
+    p_stk_data->OSFree = nfree * sizeof(OS_STK);          /* Compute number of free bytes on the stack */
+    p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            SUSPEND A TASK
+*
+* Description: This function is called to suspend a task.  The task can be the calling task if the
+*              priority passed to OSTaskSuspend() is the priority of the calling task or OS_PRIO_SELF.
+*
+* Arguments  : prio     is the priority of the task to suspend.  If you specify OS_PRIO_SELF, the
+*                       calling task will suspend itself and rescheduling will occur.
+*
+* Returns    : OS_ERR_NONE               if the requested task is suspended
+*              OS_ERR_TASK_SUSPEND_IDLE  if you attempted to suspend the idle task which is not allowed.
+*              OS_ERR_PRIO_INVALID       if the priority you specify is higher that the maximum allowed
+*                                        (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF.
+*              OS_ERR_TASK_SUSPEND_PRIO  if the task to suspend does not exist
+*              OS_ERR_TASK_NOT_EXITS     if the task is assigned to a Mutex PIP
+*
+* Note       : You should use this function with great care.  If you suspend a task that is waiting for
+*              an event (i.e. a message, a semaphore, a queue ...) you will prevent this task from
+*              running when the event arrives.
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SUSPEND_EN > 0
+INT8U  OSTaskSuspend (INT8U prio)
+{
+    BOOLEAN    self;
+    OS_TCB    *ptcb;
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio == OS_TASK_IDLE_PRIO) {                            /* Not allowed to suspend idle task    */
+        return (OS_ERR_TASK_SUSPEND_IDLE);
+    }
+    if (prio >= OS_LOWEST_PRIO) {                               /* Task priority valid ?               */
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                                 /* See if suspend SELF                 */
+        prio = OSTCBCur->OSTCBPrio;
+        self = OS_TRUE;
+    } else if (prio == OSTCBCur->OSTCBPrio) {                   /* See if suspending self              */
+        self = OS_TRUE;
+    } else {
+        self = OS_FALSE;                                        /* No suspending another task          */
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                                  /* Task to suspend must exist          */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_SUSPEND_PRIO);
+    }
+    if (ptcb == OS_TCB_RESERVED) {                              /* See if assigned to Mutex            */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+    y            = ptcb->OSTCBY;
+    OSRdyTbl[y] &= ~ptcb->OSTCBBitX;                            /* Make task not ready                 */
+    if (OSRdyTbl[y] == 0) {
+        OSRdyGrp &= ~ptcb->OSTCBBitY;
+    }
+    ptcb->OSTCBStat |= OS_STAT_SUSPEND;                         /* Status of task is 'SUSPENDED'       */
+    OS_EXIT_CRITICAL();
+    if (self == OS_TRUE) {                                      /* Context switch only if SELF         */
+        OS_Sched();                                             /* Find new highest priority task      */
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                            QUERY A TASK
+*
+* Description: This function is called to obtain a copy of the desired task's TCB.
+*
+* Arguments  : prio         is the priority of the task to obtain information from.
+*
+*              p_task_data  is a pointer to where the desired task's OS_TCB will be stored.
+*
+* Returns    : OS_ERR_NONE            if the requested task is suspended
+*              OS_ERR_PRIO_INVALID    if the priority you specify is higher that the maximum allowed
+*                                     (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF.
+*              OS_ERR_PRIO            if the desired task has not been created
+*              OS_ERR_TASK_NOT_EXIST  if the task is assigned to a Mutex PIP
+*              OS_ERR_PDATA_NULL      if 'p_task_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_TASK_QUERY_EN > 0
+INT8U  OSTaskQuery (INT8U prio, OS_TCB *p_task_data)
+{
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0
+    if (prio > OS_LOWEST_PRIO) {                 /* Task priority valid ?                              */
+        if (prio != OS_PRIO_SELF) {
+            return (OS_ERR_PRIO_INVALID);
+        }
+    }
+    if (p_task_data == (OS_TCB *)0) {            /* Validate 'p_task_data'                             */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    if (prio == OS_PRIO_SELF) {                  /* See if suspend SELF                                */
+        prio = OSTCBCur->OSTCBPrio;
+    }
+    ptcb = OSTCBPrioTbl[prio];
+    if (ptcb == (OS_TCB *)0) {                   /* Task to query must exist                           */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_PRIO);
+    }
+    if (ptcb == OS_TCB_RESERVED) {               /* Task to query must not be assigned to a Mutex      */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);
+    }
+                                                 /* Copy TCB into user storage area                    */
+    OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB));
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                        CLEAR TASK STACK
+*
+* Description: This function is used to clear the stack of a task (i.e. write all zeros)
+*
+* Arguments  : pbos     is a pointer to the task's bottom of stack.  If the configuration constant
+*                       OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high
+*                       memory to low memory).  'pbos' will thus point to the lowest (valid) memory
+*                       location of the stack.  If OS_STK_GROWTH is set to 0, 'pbos' will point to the
+*                       highest memory location of the stack and the stack will grow with increasing
+*                       memory locations.  'pbos' MUST point to a valid 'free' data item.
+*
+*              size     is the number of 'stack elements' to clear.
+*
+*              opt      contains additional information (or options) about the behavior of the task.  The
+*                       LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application
+*                       specific.  See OS_TASK_OPT_??? in uCOS-II.H.
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0)
+void  OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt)
+{
+    if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) {       /* See if stack checking has been enabled       */
+        if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) {   /* See if stack needs to be cleared             */
+#if OS_STK_GROWTH == 1
+            while (size > 0) {                         /* Stack grows from HIGH to LOW memory          */
+                size--;
+                *pbos++ = (OS_STK)0;                   /* Clear from bottom of stack and up!           */
+            }
+#else
+            while (size > 0) {                         /* Stack grows from LOW to HIGH memory          */
+                size--;
+                *pbos-- = (OS_STK)0;                   /* Clear from bottom of stack and down          */
+            }
+#endif
+        }
+    }
+}
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c
new file mode 100644
index 0000000..540384e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_time.c
@@ -0,0 +1,268 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                             TIME MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+* File    : OS_TIME.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+/*
+*********************************************************************************************************
+*                                DELAY TASK 'n' TICKS   (n from 0 to 65535)
+*
+* Description: This function is called to delay execution of the currently running task until the
+*              specified number of system ticks expires.  This, of course, directly equates to delaying
+*              the current task for some time to expire.  No delay will result If the specified delay is
+*              0.  If the specified delay is greater than 0 then, a context switch will result.
+*
+* Arguments  : ticks     is the time delay that the task will be suspended in number of clock 'ticks'.
+*                        Note that by specifying 0, the task will not be delayed.
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSTimeDly (INT16U ticks)
+{
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        return;
+    }
+    if (ticks > 0) {                             /* 0 means no delay!                                  */
+        OS_ENTER_CRITICAL();
+        y            =  OSTCBCur->OSTCBY;        /* Delay current task                                 */
+        OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX;
+        if (OSRdyTbl[y] == 0) {
+            OSRdyGrp &= ~OSTCBCur->OSTCBBitY;
+        }
+        OSTCBCur->OSTCBDly = ticks;              /* Load ticks in TCB                                  */
+        OS_EXIT_CRITICAL();
+        OS_Sched();                              /* Find next task to run!                             */
+    }
+}
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                     DELAY TASK FOR SPECIFIED TIME
+*
+* Description: This function is called to delay execution of the currently running task until some time
+*              expires.  This call allows you to specify the delay time in HOURS, MINUTES, SECONDS and
+*              MILLISECONDS instead of ticks.
+*
+* Arguments  : hours     specifies the number of hours that the task will be delayed (max. is 255)
+*              minutes   specifies the number of minutes (max. 59)
+*              seconds   specifies the number of seconds (max. 59)
+*              milli     specifies the number of milliseconds (max. 999)
+*
+* Returns    : OS_ERR_NONE
+*              OS_ERR_TIME_INVALID_MINUTES
+*              OS_ERR_TIME_INVALID_SECONDS
+*              OS_ERR_TIME_INVALID_MS
+*              OS_ERR_TIME_ZERO_DLY
+*              OS_ERR_TIME_DLY_ISR
+*
+* Note(s)    : The resolution on the milliseconds depends on the tick rate.  For example, you can't do
+*              a 10 mS delay if the ticker interrupts every 100 mS.  In this case, the delay would be
+*              set to 0.  The actual delay is rounded to the nearest tick.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_HMSM_EN > 0
+INT8U  OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms)
+{
+    INT32U ticks;
+    INT16U loops;
+
+
+    if (OSIntNesting > 0) {                      /* See if trying to call from an ISR                  */
+        return (OS_ERR_TIME_DLY_ISR);
+    }
+#if OS_ARG_CHK_EN > 0
+    if (hours == 0) {
+        if (minutes == 0) {
+            if (seconds == 0) {
+                if (ms == 0) {
+                    return (OS_ERR_TIME_ZERO_DLY);
+                }
+            }
+        }
+    }
+    if (minutes > 59) {
+        return (OS_ERR_TIME_INVALID_MINUTES);    /* Validate arguments to be within range              */
+    }
+    if (seconds > 59) {
+        return (OS_ERR_TIME_INVALID_SECONDS);
+    }
+    if (ms > 999) {
+        return (OS_ERR_TIME_INVALID_MS);
+    }
+#endif
+                                                 /* Compute the total number of clock ticks required.. */
+                                                 /* .. (rounded to the nearest tick)                   */
+    ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC
+          + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L;
+    loops = (INT16U)(ticks >> 16);               /* Compute the integral number of 65536 tick delays   */
+    ticks = ticks & 0xFFFFL;                     /* Obtain  the fractional number of ticks             */
+    OSTimeDly((INT16U)ticks);
+    while (loops > 0) {
+        OSTimeDly((INT16U)32768u);
+        OSTimeDly((INT16U)32768u);
+        loops--;
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         RESUME A DELAYED TASK
+*
+* Description: This function is used resume a task that has been delayed through a call to either
+*              OSTimeDly() or OSTimeDlyHMSM().  Note that you can call this function to resume a
+*              task that is waiting for an event with timeout.  This would make the task look
+*              like a timeout occurred.
+*
+*              Also, you cannot resume a task that has called OSTimeDlyHMSM() with a combined time that
+*              exceeds 65535 clock ticks.  In other words, if the clock tick runs at 100 Hz then, you will
+*              not be able to resume a delayed task that called OSTimeDlyHMSM(0, 10, 55, 350) or higher:
+*
+*                  (10 Minutes * 60 + 55 Seconds + 0.35) * 100 ticks/second.
+*
+* Arguments  : prio                      specifies the priority of the task to resume
+*
+* Returns    : OS_ERR_NONE               Task has been resumed
+*              OS_ERR_PRIO_INVALID       if the priority you specify is higher that the maximum allowed
+*                                        (i.e. >= OS_LOWEST_PRIO)
+*              OS_ERR_TIME_NOT_DLY       Task is not waiting for time to expire
+*              OS_ERR_TASK_NOT_EXIST     The desired task has not been created or has been assigned to a Mutex.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_RESUME_EN > 0
+INT8U  OSTimeDlyResume (INT8U prio)
+{
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3                                    /* Storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    if (prio >= OS_LOWEST_PRIO) {
+        return (OS_ERR_PRIO_INVALID);
+    }
+    OS_ENTER_CRITICAL();
+    ptcb = OSTCBPrioTbl[prio];                                 /* Make sure that task exist            */
+    if (ptcb == (OS_TCB *)0) {
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+    }
+    if (ptcb == OS_TCB_RESERVED) {
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+    }
+    if (ptcb->OSTCBDly == 0) {                                 /* See if task is delayed               */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TIME_NOT_DLY);                          /* Indicate that task was not delayed   */
+    }
+
+    ptcb->OSTCBDly = 0;                                        /* Clear the time delay                 */
+    if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) {
+        ptcb->OSTCBStat     &= ~OS_STAT_PEND_ANY;              /* Yes, Clear status flag               */
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_TO;               /* Indicate PEND timeout                */
+    } else {
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_OK;
+    }
+    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) {  /* Is task suspended?                   */
+        OSRdyGrp               |= ptcb->OSTCBBitY;             /* No,  Make ready                      */
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                            /* See if this is new highest priority  */
+    } else {
+        OS_EXIT_CRITICAL();                                    /* Task may be suspended                */
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+/*$PAGE*/
+/*
+*********************************************************************************************************
+*                                         GET CURRENT SYSTEM TIME
+*
+* Description: This function is used by your application to obtain the current value of the 32-bit
+*              counter which keeps track of the number of clock ticks.
+*
+* Arguments  : none
+*
+* Returns    : The current value of OSTime
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0
+INT32U  OSTimeGet (void)
+{
+    INT32U     ticks;
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    ticks = OSTime;
+    OS_EXIT_CRITICAL();
+    return (ticks);
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                            SET SYSTEM CLOCK
+*
+* Description: This function sets the 32-bit counter which keeps track of the number of clock ticks.
+*
+* Arguments  : ticks      specifies the new value that OSTime needs to take.
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0
+void  OSTimeSet (INT32U ticks)
+{
+#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    OSTime = ticks;
+    OS_EXIT_CRITICAL();
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c
new file mode 100644
index 0000000..c80811f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/UCOSII/src/os_tmr.c
@@ -0,0 +1,1116 @@
+/*
+************************************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                            TIMER MANAGEMENT
+*
+*                              (c) Copyright 1992-2007, Micrium, Weston, FL
+*                                           All Rights Reserved
+*
+*
+* File    : OS_TMR.C
+* By      : Jean J. Labrosse
+* Version : V2.86
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.  
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micriµm to properly license 
+* its use in your product. We provide ALL the source code for your convenience and to help you experience 
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a 
+* licensing fee.
+************************************************************************************************************************
+*/
+
+#include <ucos_ii.h>
+
+/*
+************************************************************************************************************************
+*                                                        NOTES
+*
+* 1) Your application MUST define the following #define constants:
+*
+*    OS_TASK_TMR_PRIO          The priority of the Timer management task
+*    OS_TASK_TMR_STK_SIZE      The size     of the Timer management task's stack
+*
+* 2) You must call OSTmrSignal() to notify the Timer management task that it's time to update the timers.
+************************************************************************************************************************
+*/
+
+/*
+************************************************************************************************************************
+*                                                     CONSTANTS
+************************************************************************************************************************
+*/
+
+#define  OS_TMR_LINK_DLY       0
+#define  OS_TMR_LINK_PERIODIC  1
+
+/*
+************************************************************************************************************************
+*                                                  LOCAL PROTOTYPES
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  OS_TMR  *OSTmr_Alloc         (void);
+static  void     OSTmr_Free          (OS_TMR *ptmr);
+static  void     OSTmr_InitTask      (void);
+static  void     OSTmr_Link          (OS_TMR *ptmr, INT8U type);
+static  void     OSTmr_Unlink        (OS_TMR *ptmr);
+static  void     OSTmr_Lock          (void);
+static  void     OSTmr_Unlock        (void);
+static  void     OSTmr_Task          (void   *p_arg);
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                   CREATE A TIMER
+*
+* Description: This function is called by your application code to create a timer.
+*
+* Arguments  : dly           Initial delay.
+*                            If the timer is configured for ONE-SHOT mode, this is the timeout used
+*                            If the timer is configured for PERIODIC mode, this is the first timeout to wait for
+*                               before the timer starts entering periodic mode
+*
+*              period        The 'period' being repeated for the timer.
+*                               If you specified 'OS_TMR_OPT_PERIODIC' as an option, when the timer expires, it will
+*                               automatically restart with the same period.
+*
+*              opt           Specifies either:
+*                               OS_TMR_OPT_ONE_SHOT       The timer counts down only once
+*                               OS_TMR_OPT_PERIODIC       The timer counts down and then reloads itself
+*
+*              callback      Is a pointer to a callback function that will be called when the timer expires.  The
+*                               callback function must be declared as follows:
+*
+*                               void MyCallback (OS_TMR *ptmr, void *p_arg);
+*
+*              callback_arg  Is an argument (a pointer) that is passed to the callback function when it is called.
+*
+*              pname         Is a pointer to an ASCII string that is used to name the timer.  Names are useful for
+*                               debugging.  The length of the ASCII string for the name can be as big as:
+*
+*                               OS_TMR_CFG_NAME_SIZE and should be found in OS_CFG.H
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID_DLY     you specified an invalid delay
+*                               OS_ERR_TMR_INVALID_PERIOD  you specified an invalid period
+*                               OS_ERR_TMR_INVALID_OPT     you specified an invalid option
+*                               OS_ERR_TMR_ISR             if the call was made from an ISR
+*                               OS_ERR_TMR_NON_AVAIL       if there are no free timers from the timer pool
+*                               OS_ERR_TMR_NAME_TOO_LONG   if the timer name is too long to fit
+*
+* Returns    : A pointer to an OS_TMR data structure.  
+*              This is the 'handle' that your application will use to reference the timer created.
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+OS_TMR  *OSTmrCreate (INT32U           dly,
+                      INT32U           period,
+                      INT8U            opt,
+                      OS_TMR_CALLBACK  callback,
+                      void            *callback_arg,
+                      INT8U           *pname,
+                      INT8U           *perr)
+{
+    OS_TMR   *ptmr;
+#if OS_TMR_CFG_NAME_SIZE > 0
+    INT8U     len;
+#endif
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                               /* Validate arguments                                     */
+        return ((OS_TMR *)0);
+    }
+    switch (opt) {
+        case OS_TMR_OPT_PERIODIC:
+             if (period == 0) {
+                 *perr = OS_ERR_TMR_INVALID_PERIOD;
+                 return ((OS_TMR *)0);
+             }
+             break;
+
+        case OS_TMR_OPT_ONE_SHOT:
+             if (dly == 0) {
+                 *perr = OS_ERR_TMR_INVALID_DLY;
+                 return ((OS_TMR *)0);
+             }
+             break;
+
+        default:
+             *perr = OS_ERR_TMR_INVALID_OPT;
+             return ((OS_TMR *)0);
+    }
+#endif
+    if (OSIntNesting > 0) {                                 /* See if trying to call from an ISR                      */
+        *perr  = OS_ERR_TMR_ISR;
+        return ((OS_TMR *)0);
+    }
+    OSTmr_Lock();
+    ptmr = OSTmr_Alloc();                                   /* Obtain a timer from the free pool                      */
+    if (ptmr == (OS_TMR *)0) {
+        OSTmr_Unlock();
+        *perr = OS_ERR_TMR_NON_AVAIL;
+        return ((OS_TMR *)0);
+    }
+    ptmr->OSTmrState       = OS_TMR_STATE_STOPPED;          /* Indicate that timer is not running yet                 */
+    ptmr->OSTmrDly         = dly;
+    ptmr->OSTmrPeriod      = period;
+    ptmr->OSTmrOpt         = opt;
+    ptmr->OSTmrCallback    = callback;
+    ptmr->OSTmrCallbackArg = callback_arg;
+#if OS_TMR_CFG_NAME_SIZE > 0
+    if (pname !=(INT8U *)0) {
+        len = OS_StrLen(pname);                             /* Copy timer name                                        */
+        if (len < OS_TMR_CFG_NAME_SIZE) {
+            (void)OS_StrCopy(ptmr->OSTmrName, pname);
+        } else {
+#if OS_TMR_CFG_NAME_SIZE > 1
+            ptmr->OSTmrName[0] = '#';                       /* Invalid size specified                                 */
+            ptmr->OSTmrName[1] = OS_ASCII_NUL;
+#endif
+            *perr              = OS_ERR_TMR_NAME_TOO_LONG;
+            OSTmr_Unlock();
+            return (ptmr);
+        }
+    }
+#endif
+    OSTmr_Unlock();
+    *perr = OS_ERR_NONE;
+    return (ptmr);
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                   DELETE A TIMER
+*
+* Description: This function is called by your application code to delete a timer.
+*
+* Arguments  : ptmr          Is a pointer to the timer to stop and delete.
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID        'ptmr'  is a NULL pointer
+*                               OS_ERR_TMR_INVALID_TYPE   'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_TMR_ISR            if the function was called from an ISR
+*                               OS_ERR_TMR_INACTIVE       if the timer was not created
+*                               OS_ERR_TMR_INVALID_STATE  the timer is in an invalid state
+*
+* Returns    : OS_TRUE       If the call was successful
+*              OS_FALSE      If not
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+BOOLEAN  OSTmrDel (OS_TMR  *ptmr,
+                   INT8U   *perr)
+{
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                               /* Validate arguments                                     */
+        return (OS_FALSE);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (OS_FALSE);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {                   /* Validate timer structure                               */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (OS_FALSE);
+    }
+    if (OSIntNesting > 0) {                                 /* See if trying to call from an ISR                      */
+        *perr  = OS_ERR_TMR_ISR;
+        return (OS_FALSE);
+    }
+    OSTmr_Lock();
+    switch (ptmr->OSTmrState) {
+        case OS_TMR_STATE_RUNNING:
+             OSTmr_Unlink(ptmr);                            /* Remove from current wheel spoke                        */
+             OSTmr_Free(ptmr);                              /* Return timer to free list of timers                    */
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_STOPPED:                          /* Timer has not started or ...                           */
+        case OS_TMR_STATE_COMPLETED:                        /* ... timer has completed the ONE-SHOT time              */
+             OSTmr_Free(ptmr);                              /* Return timer to free list of timers                    */
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_UNUSED:                           /* Already deleted                                        */
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INACTIVE;
+             return (OS_FALSE);
+
+        default:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             return (OS_FALSE);
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                             GET THE NAME OF A TIMER
+*
+* Description: This function is called to obtain the name of a timer.
+*
+* Arguments  : ptmr          Is a pointer to the timer to obtain the name for
+*
+*              pdest         Is a pointer to where the name of the timer will be placed.  It is the caller's responsibility
+*                            to ensure that he has sufficient storage in the destination, i.e. at least OS_TMR_CFG_NAME_SIZE
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE               The call was successful
+*                               OS_ERR_TMR_INVALID_DEST   'pdest' is a NULL pointer
+*                               OS_ERR_TMR_INVALID        'ptmr'  is a NULL pointer
+*                               OS_ERR_TMR_INVALID_TYPE   'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_NAME_GET_ISR       if the call was made from an ISR
+*                               OS_ERR_TMR_INACTIVE       'ptmr'  points to a timer that is not active
+*                               OS_ERR_TMR_INVALID_STATE  the timer is in an invalid state
+*
+* Returns    : The length of the string or 0 if the timer does not exist.
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0 && OS_TMR_CFG_NAME_SIZE > 0
+INT8U  OSTmrNameGet (OS_TMR  *ptmr,
+                     INT8U   *pdest,
+                     INT8U   *perr)
+{
+    INT8U  len;
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {
+        return (0);
+    }
+    if (pdest == (INT8U *)0) {
+        *perr = OS_ERR_TMR_INVALID_DEST;
+        return (0);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (0);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {              /* Validate timer structure                                    */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (0);
+    }
+    if (OSIntNesting > 0) {                            /* See if trying to call from an ISR                           */
+        *perr = OS_ERR_NAME_GET_ISR;
+        return (0);
+    }
+    OSTmr_Lock();
+    switch (ptmr->OSTmrState) {
+        case OS_TMR_STATE_RUNNING:
+        case OS_TMR_STATE_STOPPED:
+        case OS_TMR_STATE_COMPLETED:
+             len   = OS_StrCopy(pdest, ptmr->OSTmrName);
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (len);
+
+        case OS_TMR_STATE_UNUSED:                      /* Timer is not allocated                                      */
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INACTIVE;
+             return (0);
+
+        default:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             return (0);
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                    GET HOW MUCH TIME IS LEFT BEFORE A TIMER EXPIRES
+*
+* Description: This function is called to get the number of ticks before a timer times out.
+*
+* Arguments  : ptmr          Is a pointer to the timer to obtain the remaining time from.
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID        'ptmr' is a NULL pointer
+*                               OS_ERR_TMR_INVALID_TYPE   'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_TMR_ISR            if the call was made from an ISR
+*                               OS_ERR_TMR_INACTIVE       'ptmr' points to a timer that is not active
+*                               OS_ERR_TMR_INVALID_STATE  the timer is in an invalid state
+*
+* Returns    : The time remaining for the timer to expire.  The time represents 'timer' increments.  In other words, if
+*              OSTmr_Task() is signaled every 1/10 of a second then the returned value represents the number of 1/10 of
+*              a second remaining before the timer expires.
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+INT32U  OSTmrRemainGet (OS_TMR  *ptmr,
+                        INT8U   *perr)
+{
+    INT32U  remain;
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {
+        return (0);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (0);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {              /* Validate timer structure                                    */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (0);
+    }
+    if (OSIntNesting > 0) {                            /* See if trying to call from an ISR                           */
+        *perr = OS_ERR_TMR_ISR;
+        return (0);
+    }
+    OSTmr_Lock();
+    switch (ptmr->OSTmrState) {
+        case OS_TMR_STATE_RUNNING:
+             remain = ptmr->OSTmrMatch - OSTmrTime;    /* Determine how much time is left to timeout                  */
+             OSTmr_Unlock();
+             *perr  = OS_ERR_NONE;
+             return (remain);
+
+        case OS_TMR_STATE_STOPPED:                     /* It's assumed that the timer has not started yet             */
+             switch (ptmr->OSTmrOpt) {
+                 case OS_TMR_OPT_PERIODIC:
+                      if (ptmr->OSTmrDly == 0) {
+                          remain = ptmr->OSTmrPeriod;
+                      } else {
+                          remain = ptmr->OSTmrDly;
+                      }
+                      OSTmr_Unlock();
+                      *perr  = OS_ERR_NONE;
+                      break;
+
+                 case OS_TMR_OPT_ONE_SHOT:
+                 default:
+                      remain = ptmr->OSTmrDly;
+                      OSTmr_Unlock();
+                      *perr  = OS_ERR_NONE;
+                      break;
+             }
+             return (remain);
+
+        case OS_TMR_STATE_COMPLETED:                   /* Only ONE-SHOT that timed out can be in this state           */
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (0);
+
+        case OS_TMR_STATE_UNUSED:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INACTIVE;
+             return (0);
+
+        default:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             return (0);
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                    FIND OUT WHAT STATE A TIMER IS IN
+*
+* Description: This function is called to determine what state the timer is in:
+*
+*                  OS_TMR_STATE_UNUSED     the timer has not been created
+*                  OS_TMR_STATE_STOPPED    the timer has been created but has not been started or has been stopped
+*                  OS_TMR_COMPLETED        the timer is in ONE-SHOT mode and has completed it's timeout
+*                  OS_TMR_RUNNING          the timer is currently running
+*
+* Arguments  : ptmr          Is a pointer to the desired timer
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID        'ptmr' is a NULL pointer
+*                               OS_ERR_TMR_INVALID_TYPE   'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_TMR_ISR            if the call was made from an ISR
+*                               OS_ERR_TMR_INACTIVE       'ptmr' points to a timer that is not active
+*                               OS_ERR_TMR_INVALID_STATE  if the timer is not in a valid state
+*
+* Returns    : The current state of the timer (see description).
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+INT8U  OSTmrStateGet (OS_TMR  *ptmr,
+                      INT8U   *perr)
+{
+    INT8U  state;
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {
+        return (0);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (0);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {              /* Validate timer structure                                    */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (0);
+    }
+    if (OSIntNesting > 0) {                            /* See if trying to call from an ISR                           */
+        *perr = OS_ERR_TMR_ISR;
+        return (0);
+    }
+    OSTmr_Lock();
+    state = ptmr->OSTmrState;
+    switch (state) {
+        case OS_TMR_STATE_UNUSED:   
+        case OS_TMR_STATE_STOPPED:  
+        case OS_TMR_STATE_COMPLETED:
+        case OS_TMR_STATE_RUNNING:  
+             *perr = OS_ERR_NONE;
+             break;
+             
+        default:
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             break;
+    }
+    OSTmr_Unlock();
+    return (state);
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                   START A TIMER
+*
+* Description: This function is called by your application code to start a timer.
+*
+* Arguments  : ptmr          Is a pointer to an OS_TMR
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID
+*                               OS_ERR_TMR_INVALID_TYPE    'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_TMR_ISR             if the call was made from an ISR
+*                               OS_ERR_TMR_INACTIVE        if the timer was not created
+*                               OS_ERR_TMR_INVALID_STATE   the timer is in an invalid state
+*
+* Returns    : OS_TRUE    if the timer was started
+*              OS_FALSE   if an error was detected
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+BOOLEAN  OSTmrStart (OS_TMR   *ptmr,
+                     INT8U    *perr)
+{
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                               /* Validate arguments                                     */
+        return (OS_FALSE);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (OS_FALSE);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {                   /* Validate timer structure                               */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (OS_FALSE);
+    }
+    if (OSIntNesting > 0) {                                 /* See if trying to call from an ISR                      */
+        *perr  = OS_ERR_TMR_ISR;
+        return (OS_FALSE);
+    }
+    OSTmr_Lock();
+    switch (ptmr->OSTmrState) {
+        case OS_TMR_STATE_RUNNING:                          /* Restart the timer                                      */
+             OSTmr_Unlink(ptmr);                            /* ... Stop the timer                                     */
+             OSTmr_Link(ptmr, OS_TMR_LINK_DLY);             /* ... Link timer to timer wheel                          */
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_STOPPED:                          /* Start the timer                                        */
+        case OS_TMR_STATE_COMPLETED:
+             OSTmr_Link(ptmr, OS_TMR_LINK_DLY);             /* ... Link timer to timer wheel                          */
+             OSTmr_Unlock();
+             *perr = OS_ERR_NONE;
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_UNUSED:                           /* Timer not created                                      */
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INACTIVE;
+             return (OS_FALSE);
+
+        default:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             return (OS_FALSE);
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                   STOP A TIMER
+*
+* Description: This function is called by your application code to stop a timer.
+*
+* Arguments  : ptmr          Is a pointer to the timer to stop.
+*
+*              opt           Allows you to specify an option to this functions which can be:
+*
+*                               OS_TMR_OPT_NONE          Do nothing special but stop the timer
+*                               OS_TMR_OPT_CALLBACK      Execute the callback function, pass it the callback argument
+*                                                        specified when the timer was created.
+*                               OS_TMR_OPT_CALLBACK_ARG  Execute the callback function, pass it the callback argument
+*                                                        specified in THIS function call
+*
+*              callback_arg  Is a pointer to a 'new' callback argument that can be passed to the callback function
+*                               instead of the timer's callback argument.  In other words, use 'callback_arg' passed in
+*                               THIS function INSTEAD of ptmr->OSTmrCallbackArg
+*
+*              perr          Is a pointer to an error code.  '*perr' will contain one of the following:
+*                               OS_ERR_NONE
+*                               OS_ERR_TMR_INVALID         'ptmr' is a NULL pointer
+*                               OS_ERR_TMR_INVALID_TYPE    'ptmr'  is not pointing to an OS_TMR
+*                               OS_ERR_TMR_ISR             if the function was called from an ISR
+*                               OS_ERR_TMR_INACTIVE        if the timer was not created
+*                               OS_ERR_TMR_INVALID_OPT     if you specified an invalid option for 'opt'
+*                               OS_ERR_TMR_STOPPED         if the timer was already stopped
+*                               OS_ERR_TMR_INVALID_STATE   the timer is in an invalid state
+*                               OS_ERR_TMR_NO_CALLBACK     if the timer does not have a callback function defined
+*
+* Returns    : OS_TRUE       If we stopped the timer (if the timer is already stopped, we also return OS_TRUE)
+*              OS_FALSE      If not
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+BOOLEAN  OSTmrStop (OS_TMR  *ptmr,
+                    INT8U    opt,
+                    void    *callback_arg,
+                    INT8U   *perr)
+{
+    OS_TMR_CALLBACK  pfnct;
+
+
+#if OS_ARG_CHK_EN > 0
+    if (perr == (INT8U *)0) {                                     /* Validate arguments                               */
+        return (OS_FALSE);
+    }
+    if (ptmr == (OS_TMR *)0) {
+        *perr = OS_ERR_TMR_INVALID;
+        return (OS_FALSE);
+    }
+#endif
+    if (ptmr->OSTmrType != OS_TMR_TYPE) {                         /* Validate timer structure                         */
+        *perr = OS_ERR_TMR_INVALID_TYPE;
+        return (OS_FALSE);
+    }
+    if (OSIntNesting > 0) {                                       /* See if trying to call from an ISR                */
+        *perr  = OS_ERR_TMR_ISR;
+        return (OS_FALSE);
+    }
+    OSTmr_Lock();
+    switch (ptmr->OSTmrState) {
+        case OS_TMR_STATE_RUNNING:
+             OSTmr_Unlink(ptmr);                                  /* Remove from current wheel spoke                  */
+             *perr = OS_ERR_NONE;
+             switch (opt) {
+                 case OS_TMR_OPT_CALLBACK:
+                      pfnct = ptmr->OSTmrCallback;                /* Execute callback function if available ...       */
+                      if (pfnct != (OS_TMR_CALLBACK)0) {
+                          (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg);  /* Use callback arg when timer was created */
+                      } else {
+                          *perr = OS_ERR_TMR_NO_CALLBACK;
+                      }
+                      break;
+
+                 case OS_TMR_OPT_CALLBACK_ARG:
+                      pfnct = ptmr->OSTmrCallback;                /* Execute callback function if available ...       */
+                      if (pfnct != (OS_TMR_CALLBACK)0) {
+                          (*pfnct)((void *)ptmr, callback_arg);   /* ... using the 'callback_arg' provided in call    */
+                      } else {
+                          *perr = OS_ERR_TMR_NO_CALLBACK;
+                      }
+                      break;
+
+                 case OS_TMR_OPT_NONE:
+                      break;
+
+                 default:
+                     *perr = OS_ERR_TMR_INVALID_OPT;
+                     break;
+             }
+             OSTmr_Unlock();
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_COMPLETED:                              /* Timer has already completed the ONE-SHOT or ...  */
+        case OS_TMR_STATE_STOPPED:                                /* ... timer has not started yet.                   */
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_STOPPED;
+             return (OS_TRUE);
+
+        case OS_TMR_STATE_UNUSED:                                 /* Timer was not created                            */
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INACTIVE;
+             return (OS_FALSE);
+
+        default:
+             OSTmr_Unlock();
+             *perr = OS_ERR_TMR_INVALID_STATE;
+             return (OS_FALSE);
+    }
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                      SIGNAL THAT IT'S TIME TO UPDATE THE TIMERS
+*
+* Description: This function is typically called by the ISR that occurs at the timer tick rate and is used to signal to
+*              OSTmr_Task() that it's time to update the timers.
+*
+* Arguments  : none
+*
+* Returns    : OS_ERR_NONE         The call was successful and the timer task was signaled.
+*              OS_ERR_SEM_OVF      If OSTmrSignal() was called more often than OSTmr_Task() can handle the timers.  
+*                                  This would indicate that your system is heavily loaded.
+*              OS_ERR_EVENT_TYPE   Unlikely you would get this error because the semaphore used for signaling is created 
+*                                  by uC/OS-II.
+*              OS_ERR_PEVENT_NULL  Again, unlikely you would ever get this error because the semaphore used for signaling 
+*                                  is created by uC/OS-II.
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+INT8U  OSTmrSignal (void)
+{
+    INT8U  err;
+
+
+    err = OSSemPost(OSTmrSemSignal);
+    return (err);
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                               ALLOCATE AND FREE A TIMER
+*
+* Description: This function is called to allocate a timer.
+*
+* Arguments  : none
+*
+* Returns    : a pointer to a timer if one is available
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  OS_TMR  *OSTmr_Alloc (void)
+{
+    OS_TMR *ptmr;
+
+
+    if (OSTmrFreeList == (OS_TMR *)0) {
+        return ((OS_TMR *)0);
+    }
+    ptmr            = (OS_TMR *)OSTmrFreeList;
+    OSTmrFreeList   = (OS_TMR *)ptmr->OSTmrNext;
+    ptmr->OSTmrNext = (OS_TCB *)0;
+    ptmr->OSTmrPrev = (OS_TCB *)0;
+    OSTmrUsed++;
+    OSTmrFree--;
+    return (ptmr);
+}
+#endif
+
+
+/*
+************************************************************************************************************************
+*                                             RETURN A TIMER TO THE FREE LIST
+*
+* Description: This function is called to return a timer object to the free list of timers.
+*
+* Arguments  : ptmr     is a pointer to the timer to free
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Free (OS_TMR *ptmr)
+{
+    ptmr->OSTmrState       = OS_TMR_STATE_UNUSED;      /* Clear timer object fields                                   */
+    ptmr->OSTmrOpt         = OS_TMR_OPT_NONE;
+    ptmr->OSTmrPeriod      = 0;
+    ptmr->OSTmrMatch       = 0;
+    ptmr->OSTmrCallback    = (OS_TMR_CALLBACK)0;
+    ptmr->OSTmrCallbackArg = (void *)0;
+#if OS_TMR_CFG_NAME_SIZE > 1
+    ptmr->OSTmrName[0]     = '?';                      /* Unknown name                                                */
+    ptmr->OSTmrName[1]     = OS_ASCII_NUL;
+#endif
+
+    ptmr->OSTmrPrev        = (OS_TCB *)0;              /* Chain timer to free list                                    */
+    ptmr->OSTmrNext        = OSTmrFreeList;
+    OSTmrFreeList          = ptmr;
+
+    OSTmrUsed--;                                       /* Update timer object statistics                              */
+    OSTmrFree++;
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                    INITIALIZATION
+*                                          INITIALIZE THE FREE LIST OF TIMERS
+*
+* Description: This function is called by OSInit() to initialize the free list of OS_TMRs.
+*
+* Arguments  : none
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+void  OSTmr_Init (void)
+{
+#if OS_EVENT_NAME_SIZE > 10
+    INT8U    err;
+#endif
+    INT16U   i;
+    OS_TMR  *ptmr1;
+    OS_TMR  *ptmr2;
+
+
+    OS_MemClr((INT8U *)&OSTmrTbl[0],      sizeof(OSTmrTbl));            /* Clear all the TMRs                         */
+    OS_MemClr((INT8U *)&OSTmrWheelTbl[0], sizeof(OSTmrWheelTbl));       /* Clear the timer wheel                      */
+
+    ptmr1 = &OSTmrTbl[0];
+    ptmr2 = &OSTmrTbl[1];
+    for (i = 0; i < (OS_TMR_CFG_MAX - 1); i++) {                        /* Init. list of free TMRs                    */
+        ptmr1->OSTmrType    = OS_TMR_TYPE;
+        ptmr1->OSTmrState   = OS_TMR_STATE_UNUSED;                      /* Indicate that timer is inactive            */
+        ptmr1->OSTmrNext    = (void *)ptmr2;                            /* Link to next timer                         */
+#if OS_TMR_CFG_NAME_SIZE > 1
+        ptmr1->OSTmrName[0] = '?';                                      /* Unknown name                               */
+        ptmr1->OSTmrName[1] = OS_ASCII_NUL;
+#endif
+        ptmr1++;
+        ptmr2++;
+    }
+    ptmr1->OSTmrType    = OS_TMR_TYPE;
+    ptmr1->OSTmrState   = OS_TMR_STATE_UNUSED;                          /* Indicate that timer is inactive            */
+    ptmr1->OSTmrNext    = (void *)0;                                    /* Last OS_TMR                                */
+#if OS_TMR_CFG_NAME_SIZE > 1
+    ptmr1->OSTmrName[0] = '?';                                          /* Unknown name                               */
+    ptmr1->OSTmrName[1] = OS_ASCII_NUL;
+#endif
+    OSTmrTime           = 0;
+    OSTmrUsed           = 0;
+    OSTmrFree           = OS_TMR_CFG_MAX;
+    OSTmrFreeList       = &OSTmrTbl[0];
+    OSTmrSem            = OSSemCreate(1);
+    OSTmrSemSignal      = OSSemCreate(0);
+
+#if OS_EVENT_NAME_SIZE > 18
+    OSEventNameSet(OSTmrSem,       (INT8U *)"uC/OS-II TmrLock",   &err);/* Assign names to semaphores                 */
+#else
+#if OS_EVENT_NAME_SIZE > 10
+    OSEventNameSet(OSTmrSem,       (INT8U *)"OS-TmrLock",         &err);
+#endif
+#endif
+
+#if OS_EVENT_NAME_SIZE > 18
+    OSEventNameSet(OSTmrSemSignal, (INT8U *)"uC/OS-II TmrSignal", &err);
+#else
+#if OS_EVENT_NAME_SIZE > 10
+    OSEventNameSet(OSTmrSemSignal, (INT8U *)"OS-TmrSig",          &err);
+#endif
+#endif
+
+    OSTmr_InitTask();
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                          INITIALIZE THE TIMER MANAGEMENT TASK
+*
+* Description: This function is called by OSTmrInit() to create the timer management task.
+*
+* Arguments  : none
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_InitTask (void)
+{
+#if OS_TASK_NAME_SIZE > 6
+    INT8U  err;
+#endif
+
+
+#if OS_TASK_CREATE_EXT_EN > 0
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreateExt(OSTmr_Task,
+                          (void *)0,                                       /* No arguments passed to OSTmrTask()      */
+                          &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1],         /* Set Top-Of-Stack                        */
+                          OS_TASK_TMR_PRIO,
+                          OS_TASK_TMR_ID,
+                          &OSTmrTaskStk[0],                                /* Set Bottom-Of-Stack                     */
+                          OS_TASK_TMR_STK_SIZE,
+                          (void *)0,                                       /* No TCB extension                        */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);      /* Enable stack checking + clear stack     */
+    #else
+    (void)OSTaskCreateExt(OSTmr_Task,
+                          (void *)0,                                       /* No arguments passed to OSTmrTask()      */
+                          &OSTmrTaskStk[0],                                /* Set Top-Of-Stack                        */
+                          OS_TASK_TMR_PRIO,
+                          OS_TASK_TMR_ID,
+                          &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1],         /* Set Bottom-Of-Stack                     */
+                          OS_TASK_TMR_STK_SIZE,
+                          (void *)0,                                       /* No TCB extension                        */
+                          OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);      /* Enable stack checking + clear stack     */
+    #endif
+#else
+    #if OS_STK_GROWTH == 1
+    (void)OSTaskCreate(OSTmr_Task,
+                       (void *)0,
+                       &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1],
+                       OS_TASK_TMR_PRIO);
+    #else
+    (void)OSTaskCreate(OSTmr_Task,
+                       (void *)0,
+                       &OSTmrTaskStk[0],
+                       OS_TASK_TMR_PRIO);
+    #endif
+#endif
+
+#if OS_TASK_NAME_SIZE > 12
+    OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"uC/OS-II Tmr", &err);
+#else
+#if OS_TASK_NAME_SIZE > 6
+    OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"OS-Tmr", &err);
+#endif
+#endif
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                         INSERT A TIMER INTO THE TIMER WHEEL
+*
+* Description: This function is called to insert the timer into the timer wheel.  The timer is always inserted at the
+*              beginning of the list.
+*
+* Arguments  : ptmr          Is a pointer to the timer to insert.
+*
+*              type          Is either:
+*                               OS_TMR_LINK_PERIODIC    Means to re-insert the timer after a period expired
+*                               OS_TMR_LINK_DLY         Means to insert    the timer the first time
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Link (OS_TMR *ptmr, INT8U type)
+{
+    OS_TMR       *ptmr1;
+    OS_TMR_WHEEL *pspoke;
+    INT16U        spoke;
+
+
+    ptmr->OSTmrState = OS_TMR_STATE_RUNNING;
+    if (type == OS_TMR_LINK_PERIODIC) {                            /* Determine when timer will expire                */
+        ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime;
+    } else {
+        if (ptmr->OSTmrDly == 0) {
+            ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime;
+        } else {
+            ptmr->OSTmrMatch = ptmr->OSTmrDly    + OSTmrTime;
+        }
+    }
+    spoke  = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE);
+    pspoke = &OSTmrWheelTbl[spoke];
+
+    if (pspoke->OSTmrFirst == (OS_TMR *)0) {                       /* Link into timer wheel                           */
+        pspoke->OSTmrFirst   = ptmr;
+        ptmr->OSTmrNext      = (OS_TMR *)0;
+        pspoke->OSTmrEntries = 1;
+    } else {
+        ptmr1                = pspoke->OSTmrFirst;                 /* Point to first timer in the spoke               */
+        pspoke->OSTmrFirst   = ptmr;
+        ptmr->OSTmrNext      = (void *)ptmr1;
+        ptmr1->OSTmrPrev     = (void *)ptmr;
+        pspoke->OSTmrEntries++;
+    }
+    ptmr->OSTmrPrev = (void *)0;                                   /* Timer always inserted as first node in list     */
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                         REMOVE A TIMER FROM THE TIMER WHEEL
+*
+* Description: This function is called to remove the timer from the timer wheel.
+*
+* Arguments  : ptmr          Is a pointer to the timer to remove.
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Unlink (OS_TMR *ptmr)
+{
+    OS_TMR        *ptmr1;
+    OS_TMR        *ptmr2;
+    OS_TMR_WHEEL  *pspoke;
+    INT16U         spoke;
+
+
+    spoke  = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE);
+    pspoke = &OSTmrWheelTbl[spoke];
+
+    if (pspoke->OSTmrFirst == ptmr) {                       /* See if timer to remove is at the beginning of list     */
+        ptmr1              = (OS_TMR *)ptmr->OSTmrNext;
+        pspoke->OSTmrFirst = (OS_TMR *)ptmr1;
+        if (ptmr1 != (OS_TMR *)0) {
+            ptmr1->OSTmrPrev = (void *)0;
+        }
+    } else {
+        ptmr1            = (OS_TMR *)ptmr->OSTmrPrev;       /* Remove timer from somewhere in the list                */
+        ptmr2            = (OS_TMR *)ptmr->OSTmrNext;
+        ptmr1->OSTmrNext = ptmr2;
+        if (ptmr2 != (OS_TMR *)0) {
+            ptmr2->OSTmrPrev = (void *)ptmr1;
+        }
+    }
+    ptmr->OSTmrState = OS_TMR_STATE_STOPPED;
+    ptmr->OSTmrNext  = (void *)0;
+    ptmr->OSTmrPrev  = (void *)0;
+    pspoke->OSTmrEntries--;
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                       TIMER MANAGER DATA STRUCTURE LOCKING MECHANISM
+*
+* Description: These functions are used to gain exclusive access to timer management data structures.
+*
+* Arguments  : none
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Lock (void)
+{
+    INT8U  err;
+
+
+    OSSemPend(OSTmrSem, 0, &err);
+    (void)err;
+}
+#endif
+
+
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Unlock (void)
+{
+    (void)OSSemPost(OSTmrSem);
+}
+#endif
+
+/*$PAGE*/
+/*
+************************************************************************************************************************
+*                                                 TIMER MANAGEMENT TASK
+*
+* Description: This task is created by OSTmrInit().
+*
+* Arguments  : none
+*
+* Returns    : none
+************************************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0
+static  void  OSTmr_Task (void *p_arg)
+{
+    INT8U            err;
+    OS_TMR          *ptmr;
+    OS_TMR          *ptmr_next;
+    OS_TMR_CALLBACK  pfnct;
+    OS_TMR_WHEEL    *pspoke;
+    INT16U           spoke;
+
+
+    (void)p_arg;                                                 /* Not using 'p_arg', prevent compiler warning       */
+    for (;;) {
+        OSSemPend(OSTmrSemSignal, 0, &err);                      /* Wait for signal indicating time to update timers  */
+        OSTmr_Lock();
+        OSTmrTime++;                                             /* Increment the current time                        */
+        spoke  = (INT16U)(OSTmrTime % OS_TMR_CFG_WHEEL_SIZE);    /* Position on current timer wheel entry             */
+        pspoke = &OSTmrWheelTbl[spoke];
+        ptmr   = pspoke->OSTmrFirst;
+        while (ptmr != (OS_TMR *)0) {
+            ptmr_next = (OS_TMR *)ptmr->OSTmrNext;               /* Point to next timer to update because current ... */
+                                                                 /* ... timer could get unlinked from the wheel.      */
+            if (OSTmrTime == ptmr->OSTmrMatch) {                 /* Process each timer that expires                   */
+                pfnct = ptmr->OSTmrCallback;                     /* Execute callback function if available            */
+                if (pfnct != (OS_TMR_CALLBACK)0) {
+                    (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg);
+                }
+                OSTmr_Unlink(ptmr);                              /* Remove from current wheel spoke                   */
+                if (ptmr->OSTmrOpt == OS_TMR_OPT_PERIODIC) {
+                    OSTmr_Link(ptmr, OS_TMR_LINK_PERIODIC);      /* Recalculate new position of timer in wheel        */
+                } else {
+                    ptmr->OSTmrState = OS_TMR_STATE_COMPLETED;   /* Indicate that the timer has completed             */
+                }
+            }
+            ptmr = ptmr_next;
+        }
+        OSTmr_Unlock();
+    }
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/alt_sys_init.c b/FPGA_nios/hit_pat_bsp/alt_sys_init.c
new file mode 100644
index 0000000..dcedff4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/alt_sys_init.c
@@ -0,0 +1,115 @@
+/*
+ * alt_sys_init.c - HAL initialization source
+ *
+ * Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys'
+ * SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+ *
+ * Generated: Thu Jun 08 10:06:13 CEST 2023
+ */
+
+/*
+ * DO NOT MODIFY THIS FILE
+ *
+ * Changing this file will have subtle consequences
+ * which will almost certainly lead to a nonfunctioning
+ * system. If you do modify this file, be aware that your
+ * changes will be overwritten and lost when this file
+ * is generated again.
+ *
+ * DO NOT MODIFY THIS FILE
+ */
+
+/*
+ * License Agreement
+ *
+ * Copyright (c) 2008
+ * Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#include "system.h"
+#include "sys/alt_irq.h"
+#include "sys/alt_sys_init.h"
+
+#include <stddef.h>
+
+/*
+ * Device headers
+ */
+
+#include "altera_nios2_gen2_irq.h"
+#include "altera_avalon_sysid_qsys.h"
+#include "altera_avalon_timer.h"
+#include "altera_avalon_uart.h"
+#include "altera_eth_tse.h"
+#include "altera_generic_quad_spi_controller.h"
+#include "altera_msgdma.h"
+#include "altera_onchip_flash.h"
+
+/*
+ * Allocate the device storage
+ */
+
+ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( CPU, cpu);
+ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid);
+ALTERA_AVALON_TIMER_INSTANCE ( FRAME_TIMER, frame_timer);
+ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer);
+ALTERA_AVALON_UART_INSTANCE ( DEBUG_UART, debug_uart);
+ALTERA_ETH_TSE_INSTANCE ( ETH_TSE, eth_tse);
+ALTERA_GENERIC_QUAD_SPI_CONTROLLER_AVL_MEM_AVL_CSR_INSTANCE ( EXT_FLASH, EXT_FLASH_AVL_MEM, EXT_FLASH_AVL_CSR, ext_flash);
+ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE ( MSGDMA_RX, MSGDMA_RX_CSR, MSGDMA_RX_PREFETCHER_CSR, msgdma_rx);
+ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE ( MSGDMA_TX, MSGDMA_TX_CSR, MSGDMA_TX_PREFETCHER_CSR, msgdma_tx);
+ALTERA_ONCHIP_FLASH_DATA_CSR_INSTANCE ( ONCHIP_FLASH, ONCHIP_FLASH_DATA, ONCHIP_FLASH_CSR, onchip_flash);
+
+/*
+ * Initialize the interrupt controller devices
+ * and then enable interrupts in the CPU.
+ * Called before alt_sys_init().
+ * The "base" parameter is ignored and only
+ * present for backwards-compatibility.
+ */
+
+void alt_irq_init ( const void* base )
+{
+    ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu);
+    alt_irq_cpu_enable_interrupts();
+}
+
+/*
+ * Initialize the non-interrupt controller devices.
+ * Called after alt_irq_init().
+ */
+
+void alt_sys_init( void )
+{
+    ALTERA_AVALON_TIMER_INIT ( FRAME_TIMER, frame_timer);
+    ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
+    ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid);
+    ALTERA_AVALON_UART_INIT ( DEBUG_UART, debug_uart);
+    ALTERA_ETH_TSE_INIT ( ETH_TSE, eth_tse);
+    ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT ( EXT_FLASH, ext_flash);
+    ALTERA_MSGDMA_INIT ( MSGDMA_RX, msgdma_rx);
+    ALTERA_MSGDMA_INIT ( MSGDMA_TX, msgdma_tx);
+    ALTERA_ONCHIP_FLASH_INIT ( ONCHIP_FLASH, onchip_flash);
+}
diff --git a/FPGA_nios/hit_pat_bsp/create-this-bsp b/FPGA_nios/hit_pat_bsp/create-this-bsp
new file mode 100644
index 0000000..acc3e00
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/create-this-bsp
@@ -0,0 +1,52 @@
+#!/bin/bash
+#
+# This script creates the ucosii_net_zipfs Board Support Package (BSP).
+
+BSP_TYPE=ucosii
+BSP_DIR=.
+SOPC_DIR=../../
+SOPC_FILE=../../q_sys.sopcinfo
+NIOS2_BSP_ARGS="--set hal.make.bsp_cflags_defined_symbols -DTSE_MY_SYSTEM --cmd enable_sw_package altera_iniche"
+CPU_NAME=
+
+if [ -n "$CPU_NAME" ]; then
+  NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME"
+fi
+
+# Don't run make if create-this-app script is called with --no-make arg
+SKIP_MAKE=
+while [ $# -gt 0 ]
+do
+  case "$1" in
+		--no-make)
+        	SKIP_MAKE=1
+        	;;
+		*)
+			NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1"
+			;;
+  esac
+  shift
+done
+
+
+# Run nios2-bsp utility to create a ucosii BSP in this directory
+# for the system with a .sopc file in $SOPC_FILE.
+# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist.
+
+if [ -z "$SOPC_FILE" ]; then
+	echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path."
+	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS"
+else
+	cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS"
+fi
+
+
+echo "create-this-bsp: Running \"$cmd\""
+$cmd || {
+    echo "$cmd failed"
+    exit 1
+}
+if [ -z "$SKIP_MAKE" ]; then
+	echo "create-this-bsp: Running make"
+	make
+fi
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h
new file mode 100644
index 0000000..a829ddd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_pio_regs.h
@@ -0,0 +1,67 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_PIO_REGS_H__
+#define __ALTERA_AVALON_PIO_REGS_H__
+
+#include <io.h>
+
+#define IOADDR_ALTERA_AVALON_PIO_DATA(base)           __IO_CALC_ADDRESS_NATIVE(base, 0)
+#define IORD_ALTERA_AVALON_PIO_DATA(base)             IORD(base, 0) 
+#define IOWR_ALTERA_AVALON_PIO_DATA(base, data)       IOWR(base, 0, data)
+
+#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base)      __IO_CALC_ADDRESS_NATIVE(base, 1)
+#define IORD_ALTERA_AVALON_PIO_DIRECTION(base)        IORD(base, 1) 
+#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data)  IOWR(base, 1, data)
+
+#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base)       __IO_CALC_ADDRESS_NATIVE(base, 2)
+#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base)         IORD(base, 2) 
+#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data)   IOWR(base, 2, data)
+
+#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base)       __IO_CALC_ADDRESS_NATIVE(base, 3)
+#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base)         IORD(base, 3) 
+#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data)   IOWR(base, 3, data)
+
+
+#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base)       __IO_CALC_ADDRESS_NATIVE(base, 4)
+#define IORD_ALTERA_AVALON_PIO_SET_BITS(base)         IORD(base, 4) 
+#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data)   IOWR(base, 4, data)
+    
+#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base)       __IO_CALC_ADDRESS_NATIVE(base, 5)
+#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base)         IORD(base, 5) 
+#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data)   IOWR(base, 5, data)
+     
+
+ 
+/* Defintions for direction-register operation with bi-directional PIOs */
+#define ALTERA_AVALON_PIO_DIRECTION_INPUT  0
+#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1
+
+#endif /* __ALTERA_AVALON_PIO_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h
new file mode 100644
index 0000000..f62bc22
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys.h
@@ -0,0 +1,60 @@
+#ifndef __ALT_AVALON_SYSID_QSYS_H__
+#define __ALT_AVALON_SYSID_QSYS_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * ALTERA_AVALON_SYSID_QSYS_INSTANCE is the macro used by alt_sys_init() to
+ * allocate any per device memory that may be required. In this case no
+ * allocation is necessary.
+ */
+
+#define ALTERA_AVALON_SYSID_QSYS_INSTANCE(name, dev) extern int alt_no_storage
+#define ALTERA_AVALON_SYSID_QSYS_INIT(name, dev) while (0)
+
+#ifdef SYSID_BASE
+alt_32 alt_avalon_sysid_qsys_test(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_AVALON_SYSID_QSYS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h
new file mode 100644
index 0000000..9801855
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_SYSID_QSYS_REGS_H__
+#define __ALTERA_AVALON_SYSID_QSYS_REGS_H__
+
+#include <io.h>
+
+#define IOADDR_ALTERA_AVALON_SYSID_QSYS_ID(base)         __IO_CALC_ADDRESS_NATIVE(base, 0)
+#define IORD_ALTERA_AVALON_SYSID_QSYS_ID(base)           IORD(base, 0)
+
+#define IOADDR_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base)  __IO_CALC_ADDRESS_NATIVE(base, 1)
+#define IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base)    IORD(base, 1)
+
+#endif /* __ALTERA_AVALON_SYSID_QSYS_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h
new file mode 100644
index 0000000..a928483
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer.h
@@ -0,0 +1,193 @@
+#ifndef __ALT_AVALON_TIMER_H__
+#define __ALT_AVALON_TIMER_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <string.h>
+
+#include "alt_types.h"
+#include "sys/alt_dev.h"
+#include "sys/alt_warning.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+#define __ALT_COUNTER_SIZE(name) name##_COUNTER_SIZE
+#define _ALT_COUNTER_SIZE(name) __ALT_COUNTER_SIZE(name)
+
+#define ALT_SYS_CLK_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_SYS_CLK)
+#define ALT_TIMESTAMP_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_TIMESTAMP_CLK)
+
+#if (ALT_SYS_CLK_COUNTER_SIZE == 64)
+#define alt_sysclk_type alt_u64
+#else
+#define alt_sysclk_type alt_u32
+#endif
+
+#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
+#define alt_timestamp_type alt_u64
+#else
+#define alt_timestamp_type alt_u32
+#endif
+
+/*
+ * The function alt_avalon_timer_sc_init() is the initialisation function for 
+ * the system clock. It registers the timers interrupt handler, and then calls 
+ * the system clock regestration function, alt_sysclk_init().
+ */
+
+extern void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, 
+                                      alt_u32 irq, alt_u32 freq);
+
+/*
+ * Variables used to store the timestamp parameters, when the device is to be
+ * accessed using the high resolution timestamp driver.
+ */
+
+extern void*   altera_avalon_timer_ts_base;
+extern alt_u32 altera_avalon_timer_ts_freq;
+
+/*
+ * ALTERA_AVALON_TIMER_INSTANCE is the macro used by alt_sys_init() to 
+ * allocate any per device memory that may be required. In this case no 
+ * allocation is necessary.
+ */ 
+
+#define ALTERA_AVALON_TIMER_INSTANCE(name, dev) extern int alt_no_storage
+
+/*
+ * Macro used to calculate the timer interrupt frequency. Although this is 
+ * somewhat fearsome, when compiled with -O2 it will be resolved at compile 
+ * time to a constant value.
+ */
+
+#define ALTERA_AVALON_TIMER_FREQ(freq, period, units) \
+  strcmp (units, "us") ?                              \
+    (strcmp (units, "ms") ?                           \
+      (strcmp (units, "s") ?                          \
+        ((freq + (period - 1))/period)                \
+      : 1)                                            \
+    : (1000 + (period - 1))/period)                   \
+  : ((1000000 + (period - 1))/period)         
+
+/*
+ * Construct macros which contain the base address of the system clock and the
+ * timestamp device. These are used below to determine which driver to use for
+ * a given timer.
+ */
+
+#define __ALT_CLK_BASE(name) name##_BASE
+#define _ALT_CLK_BASE(name) __ALT_CLK_BASE(name)
+
+#define ALT_SYS_CLK_BASE _ALT_CLK_BASE(ALT_SYS_CLK)
+#define ALT_TIMESTAMP_CLK_BASE _ALT_CLK_BASE(ALT_TIMESTAMP_CLK)
+
+/*
+ * If there is no system clock, then the above macro will result in 
+ * ALT_SYS_CLK_BASE being set to none_BASE. We therefore need to provide an
+ * invalid value for this, so that no timer is wrongly identified as the system
+ * clock.
+ */
+
+#define none_BASE 0xffffffff
+
+/*
+ * ALTERA_AVALON_TIMER_INIT is the macro used by alt_sys_init() to provide
+ * the run time initialisation of the device. In this case this translates to
+ * a call to alt_avalon_timer_sc_init() if the device is the system clock, i.e.
+ * if it has the name "sysclk".
+ *
+ * If the device is not the system clock, then it is used to provide the
+ * timestamp facility. 
+ *
+ * To ensure as much as possible is evaluated at compile time, rather than 
+ * compare the name of the device to "/dev/sysclk" using strcmp(), the base
+ * address of the device is compared to SYSCLK_BASE to determine whether it's
+ * the system clock. Since the base address of a device must be unique, these
+ * two aproaches are equivalent.
+ *
+ * This macro performs a sanity check to ensure that the interrupt has been
+ * connected for this device. If not, then an apropriate error message is 
+ * generated at build time.
+ */
+
+
+#define ALTERA_AVALON_TIMER_INIT(name, dev)                                   \
+  if (name##_BASE == ALT_SYS_CLK_BASE)                                        \
+  {                                                                           \
+    if (name##_IRQ == ALT_IRQ_NOT_CONNECTED)                                  \
+    {                                                                         \
+      ALT_LINK_ERROR ("Error: Interrupt not connected for " #dev ". "         \
+                      "The system clock driver requires an interrupt to be "  \
+                      "connected. Please select an IRQ for this device in "   \
+                      "SOPC builder.");                                       \
+    }                                                                         \
+    else                                                                      \
+    {                                                                         \
+      alt_avalon_timer_sc_init((void*) name##_BASE,                           \
+                               name##_IRQ_INTERRUPT_CONTROLLER_ID,            \
+                               name##_IRQ,                                    \
+                               ALTERA_AVALON_TIMER_FREQ(name##_FREQ,          \
+                                                        name##_PERIOD,        \
+                                                        name##_PERIOD_UNITS));\
+    }                                                                         \
+  }                                                                           \
+  else if (name##_BASE == ALT_TIMESTAMP_CLK_BASE)                             \
+  {                                                                           \
+    if (name##_SNAPSHOT)                                                      \
+    {                                                                         \
+      altera_avalon_timer_ts_base = (void*) name##_BASE;                      \
+      altera_avalon_timer_ts_freq = name##_FREQ;                              \
+    }                                                                         \
+    else                                                                      \
+    {                                                                         \
+       ALT_LINK_ERROR ("Error: Snapshot register not available for "          \
+                       #dev ". "                                              \
+                      "The timestamp driver requires the snapshot register "  \
+                      "to be readable. Please enable this register for this " \
+                      "device in SOPC builder.");                             \
+    }                                                                         \
+  }
+
+/*
+ *
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_AVALON_TIMER_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h
new file mode 100644
index 0000000..d9420d5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_timer_regs.h
@@ -0,0 +1,202 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_TIMER_REGS_H__
+#define __ALTERA_AVALON_TIMER_REGS_H__
+
+#include <io.h>
+
+/* STATUS register */
+#define ALTERA_AVALON_TIMER_STATUS_REG              0
+#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG)
+#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \
+  IORD(base, ALTERA_AVALON_TIMER_STATUS_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data)
+#define ALTERA_AVALON_TIMER_STATUS_TO_MSK           (0x1)
+#define ALTERA_AVALON_TIMER_STATUS_TO_OFST          (0)
+#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK          (0x2)
+#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST         (1)
+
+/* CONTROL register */
+#define ALTERA_AVALON_TIMER_CONTROL_REG             1
+#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG)
+#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \
+  IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data)
+#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK         (0x1)
+#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST        (0)
+#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK        (0x2)
+#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST       (1)
+#define ALTERA_AVALON_TIMER_CONTROL_START_MSK       (0x4)
+#define ALTERA_AVALON_TIMER_CONTROL_START_OFST      (2)
+#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK        (0x8)
+#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST       (3)
+
+/* Period and SnapShot Register for COUNTER_SIZE = 32 */
+/*----------------------------------------------------*/
+/* PERIODL register */
+#define ALTERA_AVALON_TIMER_PERIODL_REG             2
+#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data)
+#define ALTERA_AVALON_TIMER_PERIODL_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIODL_OFST            (0)
+
+/* PERIODH register */
+#define ALTERA_AVALON_TIMER_PERIODH_REG             3
+#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data)
+#define ALTERA_AVALON_TIMER_PERIODH_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIODH_OFST            (0)
+
+/* SNAPL register */
+#define ALTERA_AVALON_TIMER_SNAPL_REG               4
+#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data)
+#define ALTERA_AVALON_TIMER_SNAPL_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAPL_OFST              (0)
+
+/* SNAPH register */
+#define ALTERA_AVALON_TIMER_SNAPH_REG               5
+#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data)
+#define ALTERA_AVALON_TIMER_SNAPH_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAPH_OFST              (0)
+
+/* Period and SnapShot Register for COUNTER_SIZE = 64 */
+/*----------------------------------------------------*/
+/* PERIOD_0 register */
+#define ALTERA_AVALON_TIMER_PERIOD_0_REG             2
+#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data)
+#define ALTERA_AVALON_TIMER_PERIOD_0_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIOD_0_OFST            (0)
+
+/* PERIOD_1 register */
+#define ALTERA_AVALON_TIMER_PERIOD_1_REG             3
+#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data)
+#define ALTERA_AVALON_TIMER_PERIOD_1_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIOD_1_OFST            (0)
+
+/* PERIOD_2 register */
+#define ALTERA_AVALON_TIMER_PERIOD_2_REG             4
+#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data)
+#define ALTERA_AVALON_TIMER_PERIOD_2_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIOD_2_OFST            (0)
+
+/* PERIOD_3 register */
+#define ALTERA_AVALON_TIMER_PERIOD_3_REG             5
+#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
+#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \
+  IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data)
+#define ALTERA_AVALON_TIMER_PERIOD_3_MSK             (0xFFFF)
+#define ALTERA_AVALON_TIMER_PERIOD_3_OFST            (0)
+
+/* SNAP_0 register */
+#define ALTERA_AVALON_TIMER_SNAP_0_REG               6
+#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data)
+#define ALTERA_AVALON_TIMER_SNAP_0_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAP_0_OFST              (0)
+
+/* SNAP_1 register */
+#define ALTERA_AVALON_TIMER_SNAP_1_REG               7
+#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data)
+#define ALTERA_AVALON_TIMER_SNAP_1_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAP_1_OFST              (0)
+
+/* SNAP_2 register */
+#define ALTERA_AVALON_TIMER_SNAP_2_REG               8
+#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data)
+#define ALTERA_AVALON_TIMER_SNAP_2_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAP_2_OFST              (0)
+
+/* SNAP_3 register */
+#define ALTERA_AVALON_TIMER_SNAP_3_REG               9
+#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \
+  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
+#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \
+  IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG) 
+#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \
+  IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data)
+#define ALTERA_AVALON_TIMER_SNAP_3_MSK               (0xFFFF)
+#define ALTERA_AVALON_TIMER_SNAP_3_OFST              (0)
+
+#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h
new file mode 100644
index 0000000..53ab7da
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse.h
@@ -0,0 +1,1023 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_TSE_H__
+#define __ALTERA_AVALON_TSE_H__
+
+#include "altera_eth_tse_regs.h"
+#include "system.h"     /* check if SGDMA is used */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+
+/* TSE DEBUG Message Level */
+/* Level 6 : Info
+ * Level 5 : Debug Info
+ * Level 4 : Warning
+ * Level 3 : Critical Warning
+ * Level 2 : Error
+ * Level 1 : Critical Error, eg: malloc() failed
+ */
+ 
+#ifndef TSE_DEBUG_LEVEL
+    #define TSE_DEBUG_LEVEL 6
+#endif
+
+/* definition without InterNiche */
+#ifndef ALT_INICHE
+#define SUCCESS            0  /* whatever the call was, it worked. */
+#define ENP_RESOURCE     -22  /* ran out of other queue-able resource */
+#define ENP_PARAM        -10  /* bad parameter */
+
+#define MAXNETS            8  /* max ifaces to support at one time */
+
+#ifdef ALT_DEBUG
+#define tse_dprintf(level, fmt, rest...)        \
+    if(level <= TSE_DEBUG_LEVEL) {              \
+        printf (fmt, ## rest);                  \
+    }                                           \
+    else {                                      \
+        no_printf (fmt, ## rest);               \
+    }
+#else
+#define tse_dprintf(level, fmt, rest...) no_printf (fmt, ## rest)
+#endif /* ALT_DEBUG */
+    
+#else /* ALT_INICHE */
+#include "ipport.h"
+
+#define tse_dprintf(level, fmt, rest...)        \
+    if(level <= TSE_DEBUG_LEVEL) {              \
+        dprintf (fmt, ## rest);                 \
+    }                                           \
+    else {                                      \
+        no_printf (fmt, ## rest);               \
+    }
+#endif /* ALT_INICHE */
+
+
+void no_printf (char *fmt, ...);
+
+
+
+/* MSGDMA dependent */
+#ifdef __ALTERA_MSGDMA
+#include "altera_msgdma.h"
+
+/* Device addressing struct for all hardware TSE MAC depends on */
+typedef struct tse_mac_trans_info_struct {
+  np_tse_mac    *base;
+  alt_msgdma_dev *tx_msgdma;
+  alt_msgdma_dev *rx_msgdma;
+  alt_u32       *rx_msgdma_desc_ram;
+  alt_u32       cfgflags;  // flags or'ed during initialization of COMMAND_CONFIG
+} tse_mac_trans_info;
+
+
+/** @Function Description - Perform initialization steps on transaction info structure to prepare it for .
+  *                        use by the library functions with two MSGDMAs and extra initialization Flags
+  * @API Type:          Internal
+  * @param mi           Main Device Structure.
+  * @param mac_base     Base Address of the Control interface for the TSE MAC
+  * @param tx_msgdma     MSGDMA device handle for TSE transmit data path 
+  * @param rx_msgdma     MSGDMA device handle for TSE receive data path
+  * @param cfgflags     initialization flags for the device
+  * @return SUCCESS 
+  */
+
+alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi,
+                                        alt_u32 mac_base,
+                                        alt_32 tx_msgdma,
+                                        alt_32 rx_msgdma,
+                                        alt_32 cfgflags);
+
+/** @Function Description - Synchronous MSGDMA copy from buffer memory into transmit FIFO. Waits until 
+  *                         MSGDMA has completed.  Raw function without any error checks.
+  * @API Type:              Internal
+  * @param mi               Main Device Structure.
+  * @param txDesc           Pointer to the transmit MSGDMA descriptor
+  * @return actual bytes transferred if ok else ENP_RESOURCE if error
+  */
+alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi,  
+                       alt_msgdma_standard_descriptor *txDesc);
+                       
+                       
+                       
+/** @Function Description - Asynchronous MSGDMA copy from buffer memory into rxFIFO.
+  *                         Raw function without any transfer error checks.
+  *
+  * @API Type:    Internal
+  * @param mi     Main Device Structure.
+  * @param rxDesc Pointer to the receive MSGDMA descriptor
+  * @return SUCCESS if ok  else -1 if error
+ */                       
+alt_32 tse_mac_aTxWrite( tse_mac_trans_info *mi,  
+                       alt_msgdma_prefetcher_standard_descriptor *txDesc);                       
+
+
+
+/** @Function Description - Asynchronous MSGDMA copy from rxFIFO into given buffer memory area.
+  *                         Raw function without any error checks.
+  *
+  * @API Type:    Internal
+  * @param mi     Main Device Structure.
+  * @param rxDesc Pointer to the receive MSGDMA descriptor
+  * @return SUCCESS if ok  else ENP_RESOURCE if error
+  *
+  * Note:  At the point of this function call return, 
+  *        the MSGDMA asynchronous operation may not have been
+  *        completed yet, so the function does not return
+  *        the actual bytes transferred for current descriptor
+  */
+alt_32 tse_mac_aRxRead(tse_mac_trans_info *mi, alt_msgdma_prefetcher_standard_descriptor *rxDesc);
+
+#endif /* __ALTERA_MSGDMA */
+
+
+
+
+
+
+/*** Debug Definition *********/
+/* change ENABLE_PHY_LOOPBACK to 1 to enable PHY loopback for debug purpose */ 
+#ifndef ENABLE_PHY_LOOPBACK
+    #define ENABLE_PHY_LOOPBACK     0
+#endif
+
+#ifndef pnull
+#define pnull ((void *)0)
+#endif
+
+/* Constant definition for tse_system_info.h */
+#define TSE_EXT_DESC_MEM                        1
+#define TSE_INT_DESC_MEM                        0
+
+#define TSE_USE_SHARED_FIFO                     1
+#define TSE_NO_SHARED_FIFO                      0
+
+#define TSE_ENABLE_MDIO_SHARING                 1
+
+/* Multi-channel Shared FIFO Depth Settings */
+#ifndef ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT
+    #define ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT        2040
+#endif
+
+#ifndef ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT
+    #define ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT        2040
+#endif
+
+
+/* PHY Status definition */
+#define TSE_PHY_AUTO_ADDRESS        -1
+#define TSE_PHY_MAP_SUCCESS         0
+#define TSE_PHY_MAP_ERROR           -1
+
+#define TSE_PHY_AN_NOT_COMPLETE     -1
+#define TSE_PHY_AN_NOT_CAPABLE      -2
+#define TSE_PHY_AN_COMPLETE         0
+#define TSE_PHY_SPEED_INVALID       3
+#define TSE_PHY_SPEED_1000          2
+#define TSE_PHY_SPEED_100           1
+#define TSE_PHY_SPEED_10            0
+#define TSE_PHY_SPEED_NO_COMMON     -1
+#define TSE_PHY_DUPLEX_FULL         1
+#define TSE_PHY_DUPLEX_HALF         0
+
+/* getPHYSpeed return error */
+enum {
+    ALT_TSE_E_NO_PMAC_FOUND             = (1 << 23),
+    ALT_TSE_E_NO_MDIO                   = (1 << 22),
+    ALT_TSE_E_NO_PHY                    = (1 << 21),
+    ALT_TSE_E_NO_COMMON_SPEED           = (1 << 20),
+    ALT_TSE_E_AN_NOT_COMPLETE           = (1 << 19),
+    ALT_TSE_E_NO_PHY_PROFILE            = (1 << 18),
+    ALT_TSE_E_PROFILE_INCORRECT_DEFINED = (1 << 17),
+    ALT_TSE_E_INVALID_SPEED             = (1 << 16)
+};
+
+/* Maximum number of PHY that can be registered into PHY profile */
+#define TSE_MAX_PHY_PROFILE     8   
+
+/* Maximum MAC in system */
+#define TSE_MAX_MAC_IN_SYSTEM   MAXNETS
+#define TSE_MAX_CHANNEL         MAXNETS
+
+
+/* System Constant Definition Used in the TSE Driver Code */
+
+
+#define ALTERA_TSE_SW_RESET_TIME_OUT_CNT         10000
+#define ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT      1000000 
+
+//These values reflect useable chain size plus 1 for ending descriptor
+#define ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE     9   
+#define ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE     2   /* currently only a value of 2 is supported */
+
+#define ALTERA_TSE_MAC_MAX_FRAME_LENGTH         1518
+
+
+#define ALTERA_TSE_FULL_MAC                     0
+#define ALTERA_TSE_MACLITE_10_100               1
+#define ALTERA_TSE_MACLITE_1000                 2
+
+#define ALTERA_TSE_NO_INDEX_FOUND               -1
+#define ALTERA_TSE_SYSTEM_DEF_ERROR             -1
+#define ALTERA_TSE_MALLOC_FAILED                -1
+
+#define ALTERA_TSE_DUPLEX_MODE_DEFAULT          TSE_PHY_DUPLEX_FULL
+#define ALTERA_TSE_MAC_SPEED_DEFAULT            TSE_PHY_SPEED_100
+/* added as bsp public makefile settings
+#define ALTERA_AUTONEG_TIMEOUT_THRESHOLD        2500
+#define ALTERA_CHECKLINK_TIMEOUT_THRESHOLD      10000
+#define ALTERA_NOMDIO_TIMEOUT_THRESHOLD         1000000
+#define ALTERA_DISGIGA_TIMEOUT_THRESHOLD        5000000
+*/
+
+#define ALTERA_TSE_PCS_IF_MODE                  0x14        /* 0x14th register of ALTERA PCS */
+
+/* PHY ID, backward compatible */
+#define NTL848PHY_ID    0x20005c90  /* National 83848, 10/100 */
+#define MTIPPCS_ID      0x00010000  /* MTIP 1000 Base-X PCS */
+#define TDKPHY_ID       0x0300e540  /* TDK 78Q2120 10/100 */
+#define NTLPHY_ID       0x20005c7a  /* National DP83865 */
+#define MVLPHY_ID       0x0141      /* Marvell 88E1111 */
+
+
+
+/* PHY ID */
+/* Marvell PHY on PHYWORKX board */
+enum {
+    MV88E1111_OUI       = 0x005043,
+    MV88E1111_MODEL     = 0x0c,
+    MV88E1111_REV       = 0x2
+};
+
+/* Marvell Quad PHY on PHYWORKX board */
+enum {
+    MV88E1145_OUI       = 0x005043,
+    MV88E1145_MODEL     = 0x0d,
+    MV88E1145_REV       = 0x2
+};
+
+/* National PHY on PHYWORKX board */
+enum {
+    DP83865_OUI       = 0x080017,
+    DP83865_MODEL     = 0x07,
+    DP83865_REV       = 0xa
+};
+
+/* National 10/100 PHY on PHYWORKX board */
+enum {
+    DP83848C_OUI       = 0x080017,
+    DP83848C_MODEL     = 0x09,
+    DP83848C_REV       = 0x0
+};
+
+/* Intel PEF7071 Phy on C10 Devkit */
+enum {
+    PEF7071_OUI       = ((0xd565 << 6) | ((0xa401 >> 10) & 0x3f)),
+    PEF7071_MODEL     = ((0xa401 >> 4) & 0x3f),
+    PEF7071_REV       = (0xa401 & 0x0f)
+};
+
+
+
+/* PHY register definition */
+enum {
+    TSE_PHY_MDIO_CONTROL    = 0,
+    TSE_PHY_MDIO_STATUS     = 1,
+    TSE_PHY_MDIO_PHY_ID1    = 2,
+    TSE_PHY_MDIO_PHY_ID2    = 3,
+    TSE_PHY_MDIO_ADV        = 4,
+    TSE_PHY_MDIO_REMADV     = 5,
+    
+    TSE_PHY_MDIO_AN_EXT             = 6,
+    TSE_PHY_MDIO_1000BASE_T_CTRL    = 9,
+    TSE_PHY_MDIO_1000BASE_T_STATUS  = 10,
+    TSE_PHY_MDIO_EXT_STATUS         = 15    
+};
+
+/* MDIO CONTROL bit number */
+enum {
+    TSE_PHY_MDIO_CONTROL_RESET      = 15,
+    TSE_PHY_MDIO_CONTROL_LOOPBACK   = 14,
+    TSE_PHY_MDIO_CONTROL_SPEED_LSB  = 13,
+    TSE_PHY_MDIO_CONTROL_AN_ENA     = 12,
+    TSE_PHY_MDIO_CONTROL_POWER_DOWN = 11,
+    TSE_PHY_MDIO_CONTROL_ISOLATE    = 10,
+    TSE_PHY_MDIO_CONTROL_RESTART_AN = 9,
+    TSE_PHY_MDIO_CONTROL_DUPLEX     = 8,
+    TSE_PHY_MDIO_CONTROL_SPEED_MSB  = 6
+};
+
+/* MDIO STATUS bit number */
+enum {
+    TSE_PHY_MDIO_STATUS_100BASE_T4      = 15,
+    TSE_PHY_MDIO_STATUS_100BASE_X_FULL  = 14,
+    TSE_PHY_MDIO_STATUS_100BASE_X_HALF  = 13,
+    TSE_PHY_MDIO_STATUS_10BASE_T_FULL   = 12,
+    TSE_PHY_MDIO_STATUS_10BASE_T_HALF   = 11,
+    TSE_PHY_MDIO_STATUS_100BASE_T2_FULL = 10,
+    TSE_PHY_MDIO_STATUS_100BASE_T2_HALF = 9,
+    TSE_PHY_MDIO_STATUS_EXT_STATUS      = 8,
+    TSE_PHY_MDIO_STATUS_AN_COMPLETE     = 5,
+    TSE_PHY_MDIO_STATUS_AN_ABILITY      = 3,
+    TSE_PHY_MDIO_STATUS_LINK_STATUS     = 2
+};
+
+/* AN Advertisement bit number */
+/* and also */
+/* Link Partner Ability bit number */
+enum {
+    TSE_PHY_MDIO_ADV_100BASE_T4       = 9,
+    TSE_PHY_MDIO_ADV_100BASE_TX_FULL  = 8,
+    TSE_PHY_MDIO_ADV_100BASE_TX_HALF  = 7,
+    TSE_PHY_MDIO_ADV_10BASE_TX_FULL   = 6,
+    TSE_PHY_MDIO_ADV_10BASE_TX_HALF   = 5
+};
+
+/* AN Expansion bit number */
+enum {
+    TSE_PHY_MDIO_LP_AN_ABLE     = 0
+};
+
+/* 1000BASE-T Control bit number */
+enum {
+    TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV   = 9,
+    TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV   = 8
+};
+
+/* 1000BASE-T Status bit number */
+enum {
+    TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV   = 11,
+    TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV   = 10
+};
+
+/* Extended Status bit number */
+enum {
+    TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL = 15,
+    TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF = 14,
+    TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL = 13,
+    TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF = 12
+};
+
+
+
+
+
+/* 
+ * macros to access MSGDMA prefetcher standard Descriptors used in the TSE driver 
+ * - use the macros to assure cache coherancy 
+ */
+#define IORD_ALTERA_TSE_MSGDMA_DESC_READ_ADDR(base)                      (IORD(base, 0x0) & 0xFFFFFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_READ_ADDR(base, data)                IOWR(base, 0x0, data)
+#define IORD_ALTERA_TSE_MSGDMA_DESC_WRITE_ADDR(base)                     (IORD(base, 0x1) & 0xFFFFFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_WRITE_ADDR(base, data)               IOWR(base, 0x1, data)
+#define IORD_ALTERA_TSE_MSGDMA_DESC_NEXT(base)                           (IORD(base, 0x3) & 0xFFFFFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_NEXT(base, data)                     IOWR(base, 0x3, data)
+
+#define IORD_ALTERA_TSE_MSGDMA_DESC_BYTES_TO_TRANSFER(base)              (IORD(base, 0x2) & 0xFFFFFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_BYTES_TO_TRANSFER(base, data)        IOWR(base, 0x2,  data))
+
+#define IORD_ALTERA_TSE_MSGDMA_DESC_ACTUAL_BYTES_TRANSFERRED(base)       (IORD(base, 0x4) & 0xFFFFFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_ACTUAL_BYTES_TRANSFERRED(base, data) IOWR(base, 0x4,  data))
+#define IORD_ALTERA_TSE_MSGDMA_DESC_STATUS(base)                         (((IORD(base, 0x5)) >> 16) & 0xFFFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_STATUS(base, data)                   IOWR(base, 0x5, (data & 0xffff))
+#define IORD_ALTERA_TSE_MSGDMA_DESC_CONTROL(base)                        (((IORD(base, 0x7) >> 24) & 0xFF)
+#define IOWR_ALTERA_TSE_MSGDMA_DESC_CONTROL(base, data)                  IOWR(base, 0x7, data)
+
+/* TSE System Component Structure */
+typedef struct alt_tse_system_mac_struct {
+    alt_u32        tse_mac_base;                     /* Base address of TSE MAC                               */
+    alt_u16        tse_tx_depth;                     /* TX Receive FIFO depth                                 */
+    alt_u16        tse_rx_depth;                     /* RX Receive FIFO depth                                 */
+    alt_u8        tse_use_mdio;                     /* is MDIO enabled                                       */
+    alt_u8        tse_en_maclite;                   /* is Small MAC                                          */
+    alt_u8        tse_maclite_gige;                 /* is Small MAC 1000 Mbps                                */
+    alt_u8        tse_multichannel_mac;             /* MAC group together for MDIO block sharing             */
+    alt_u8        tse_num_of_channel;               /* Number of channel for Multi-channel MAC               */
+    alt_u8        tse_mdio_shared;                  /* is MDIO block shared                                  */
+    alt_u8        tse_number_of_mac_mdio_shared;    /* Number of MAC sharing the MDIO block                  */
+    alt_u8        tse_pcs_ena;                      /* is MAC+PCS combination                                */
+    alt_u8        tse_pcs_sgmii;                    /* is SGMII mode of PCS enabled                          */
+} alt_tse_system_mac;
+
+typedef struct alt_tse_system_msgdma_struct {
+    char *        tse_msgdma_tx;                      /* MSGDMA TX name                                         */
+    char *        tse_msgdma_rx;                      /* MSGDMA RX name                                         */
+    alt_u16        tse_msgdma_rx_irq;                  /* MSGDMA RX IRQ                                          */
+} alt_tse_system_msgdma;
+
+typedef struct alt_tse_system_desc_mem_struct {
+    alt_u8        ext_desc_mem;                     /* is dedicated memory used for descriptor               */
+    alt_u32        desc_mem_base;                      /* Base address of Descriptor Memory if ext_desc_mem = 1 */
+} alt_tse_system_desc_mem;
+
+typedef struct alt_tse_system_shared_fifo_struct {
+    alt_u8        use_shared_fifo;                  /* is Shared FIFO used in the system                     */
+    
+    alt_u32        tse_shared_fifo_tx_ctrl_base;     /* Base address of TX Shared FIFO Ctrl                   */
+    alt_u32        tse_shared_fifo_tx_stat_base;     /* Base address of TX Shared FIFO Fill Level             */
+    alt_u32        tse_shared_fifo_tx_depth;         /* Depth of TX Shared FIFO                               */
+    
+    alt_u32        tse_shared_fifo_rx_ctrl_base;     /* Base address of RX Shared FIFO Ctrl                   */
+    alt_u32        tse_shared_fifo_rx_stat_base;     /* Base address of RX Shared FIFO Fill Level             */
+    alt_u32        tse_shared_fifo_rx_depth;         /* Depth of RX Shared FIFO                               */
+    
+} alt_tse_system_shared_fifo;
+
+typedef struct alt_tse_system_phy_struct {
+    alt_32        tse_phy_mdio_address;              /* PHY's MDIO address                                    */
+    alt_32        (*tse_phy_cfg)(np_tse_mac *pmac); /* Function pointer to execute additional initialization */
+} alt_tse_system_phy;
+
+/* System Parameters for TSE System */
+typedef struct alt_tse_system_info_struct {
+    alt_u32        tse_mac_base;                     /* Base address of TSE MAC                               */
+    alt_u32        tse_tx_depth;                     /* TX Receive FIFO depth                                 */
+    alt_u32        tse_rx_depth;                     /* RX Receive FIFO depth                                 */
+    alt_u8        tse_use_mdio;                     /* is MDIO enabled                                       */
+    alt_u8        tse_en_maclite;                   /* is Small MAC                                          */
+    alt_u8        tse_maclite_gige;                 /* is Small MAC 1000 Mbps                                */
+    alt_u8        tse_multichannel_mac;             /* MAC group together for MDIO block sharing             */
+    alt_u8        tse_num_of_channel;               /* Number of channel for Multi-channel MAC               */
+    alt_u8        tse_mdio_shared;                  /* is MDIO block shared                                  */
+    alt_u8        tse_number_of_mac_mdio_shared;    /* Number of MAC sharing the MDIO block                  */
+    alt_u8        tse_pcs_ena;                      /* is MAC+PCS combination                                */
+    alt_u8        tse_pcs_sgmii;                    /* is SGMII mode of PCS enabled                          */
+        
+    char *        tse_msgdma_tx;                     /* MSGDMA TX name                                         */
+    char *        tse_msgdma_rx;                     /* MSGDMA RX name                                         */
+    alt_u16        tse_msgdma_rx_irq;                 /* MSGDMA TX IRQ                                          */
+    
+    alt_u8        ext_desc_mem;                     /* is dedicated memory used for descriptor               */
+    alt_u32        desc_mem_base;                    /* Base address of Descriptor Memory if ext_desc_mem = 1 */
+    
+    alt_u8        use_shared_fifo;                  /* is Shared FIFO used in the system                     */
+    alt_u32        tse_shared_fifo_tx_ctrl_base;     /* Base address of TX Shared FIFO Ctrl                   */
+    alt_u32        tse_shared_fifo_tx_stat_base;     /* Base address of TX Shared FIFO Fill Level             */
+    alt_u32        tse_shared_fifo_tx_depth;         /* Depth of TX Shared FIFO                               */
+    
+    alt_u32        tse_shared_fifo_rx_ctrl_base;     /* Base address of RX Shared FIFO Ctrl                   */
+    alt_u32        tse_shared_fifo_rx_stat_base;     /* Base address of RX Shared FIFO Fill Level             */
+    alt_u32        tse_shared_fifo_rx_depth;         /* Depth of RX Shared FIFO                               */
+    
+    alt_32        tse_phy_mdio_address;             /* PHY's MDIO address                                    */
+    alt_32        (*tse_phy_cfg)(np_tse_mac *pmac); /* Function pointer to execute additional initialization */
+    
+} alt_tse_system_info;
+
+
+ 
+
+/* PHY structure for PHY detection */
+typedef struct alt_tse_phy_profile_struct{
+
+    /* PHY name */
+    char name[80];
+
+    /* PHY OUI (Organizationally Unique Identififier) */
+    alt_u32 oui;
+    
+    /* PHY model number */
+    alt_u8 model_number;
+    
+    /* PHY revision number */
+    alt_u8 revision_number;
+    
+    /* Location of PHY Specific Status Register */
+    alt_u8 status_reg_location;
+    
+    /* Location of Speed Status bit in PHY Specific Status Register */
+    alt_u8 speed_lsb_location;
+    
+    /* Location of Duplex Status bit in PHY Specific Status Register */
+    alt_u8 duplex_bit_location;
+    
+    /* Location of Link Status bit in PHY Specific Status Register */
+    alt_u8 link_bit_location;
+    
+    /* Function pointer to execute additional initialization */
+    /* Profile specific */
+    alt_32 (*phy_cfg)(np_tse_mac *pmac);
+    
+    /** Function pointer to read the link status from the PHY specific status register 
+      * Use this function pointer if the PHY is using different format to store link information in PHY specific status register
+      * The above _location variable will not be used if this function pointer is not NULL
+      * Table below show the format of the return value required by TSE driver PHY detection
+      * ----------------------------------------------------------------------------------
+      * |  BIT  | Value: Description                                                     |
+      * ----------------------------------------------------------------------------------
+      * | 31-17 | Reserved                                                               |
+      * |   16  | 1: Error:Invalid speed read from PHY                                   |
+      * | 15- 4 | Reserved                                                               |
+      * |    3  | 1: 10 Mbps link                                                        |
+      * |    2  | 1: 100 Mbps link                                                       |
+      * |    1  | 1: 1000 Mbps link                                                      |
+      * |    0  | 1: Full Duplex                    0: Half Duplex                       |
+      * ----------------------------------------------------------------------------------
+      */
+    alt_u32 (*link_status_read)(np_tse_mac *pmac);
+    
+} alt_tse_phy_profile;
+
+
+/* TSE Multi-Channel PHY detection */
+typedef struct alt_tse_phy_link_cap_struct {
+    /* connected PHY capabilities */
+    alt_u8 cap_1000_base_x_full;
+    alt_u8 cap_1000_base_x_half;
+    alt_u8 cap_1000_base_t_full;
+    alt_u8 cap_1000_base_t_half;
+    
+    alt_u8 cap_100_base_t4;
+    alt_u8 cap_100_base_x_full;
+    alt_u8 cap_100_base_x_half;
+    alt_u8 cap_100_base_t2_full;
+    alt_u8 cap_100_base_t2_half;
+    alt_u8 cap_10_base_t_full;
+    alt_u8 cap_10_base_t_half;
+    
+    /* link partner capabilities */
+    alt_u8 lp_1000_base_t_full;
+    alt_u8 lp_1000_base_t_half;
+    
+    alt_u8 lp_100_base_t4;
+    alt_u8 lp_100_base_tx_full;
+    alt_u8 lp_100_base_tx_half;
+    alt_u8 lp_10_base_tx_full;
+    alt_u8 lp_10_base_tx_half;    
+} alt_tse_phy_link_cap;
+
+
+struct alt_tse_phy_info_struct;
+struct alt_tse_mac_info_struct;
+struct alt_tse_mac_group_struct;
+
+struct alt_tse_phy_info_struct {
+    alt_u8 mdio_address;                       /* Actual PHY MDIO address detected                           */
+    alt_tse_phy_link_cap link_capability;       /* structure to store link capability of PHY and link partner */
+    alt_tse_phy_profile *pphy_profile;          /* Pointer to type of PHY profile                             */
+    struct alt_tse_mac_info_struct *pmac_info;  /* Pointer to MAC info structure which connected to this PHY  */
+    
+};
+
+struct alt_tse_mac_info_struct {
+    alt_u8 mac_type;                               /* ALTERA_TSE_FULL_MAC, ALTERA_TSE_MACLITE_10_100, or ALTERA_TSE_MACLITE_1000 */
+    struct alt_tse_phy_info_struct *pphy_info;      /* Pointer to PHY info structure which connected to this MAC */
+    alt_tse_system_info *psys_info;                      /* Pointer to alt_tse_system_info structure in alt_tse_system_info.h */
+    struct alt_tse_mac_group_struct *pmac_group;    /* Pointer to the MAC group this MAC belongs to, all multi-channel MAC form a group */
+    
+};
+
+struct alt_tse_mac_group_struct {
+    alt_u8 channel;                                            /* Number of channel the MAC group has */
+    struct alt_tse_mac_info_struct *pmac_info[TSE_MAX_CHANNEL]; /* Pointer to hold MACs in the same group */
+};
+
+typedef struct alt_tse_phy_info_struct alt_tse_phy_info;
+typedef struct alt_tse_mac_info_struct alt_tse_mac_info;
+typedef struct alt_tse_mac_group_struct alt_tse_mac_group;
+
+
+
+/*******************************
+ *
+ * Public API for TSE Driver 
+ *
+ *******************************/
+
+/* @Function Description: Perform a software Reset. Reset operation will ocur with some latency.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+ * @return SUCCESS if ok, else if error return ENP_RESOURCE, ENP_LOGIC
+*/
+alt_32 tse_mac_SwReset( np_tse_mac *pmac);
+
+
+
+
+/* @Function Description: Perform switching of the TSE MAC into MII (10/100) mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+ * @return SUCCESS
+*/
+alt_32 tse_mac_setMIImode(np_tse_mac *pmac);
+
+
+
+
+/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+ * @return SUCCESS
+*/
+alt_32 tse_mac_setGMIImode(np_tse_mac *pmac);
+
+
+/* @Function Description - Add additional PHYs which are not supported by default into PHY profile for PHY detection and auto negotiation
+ * 
+ * @API TYPE - Public
+ * @param  phy  pointer to alt_tse_phy_profile structure describing PHY registers
+ * @return      index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ * PHY which are currently supported by default :  Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C
+ */
+alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy);
+
+
+/* @Function Description - Add TSE System to tse_mac_device[] array to customize TSE System
+ * 
+ * @API TYPE - Public
+ * @param        psys_mac  pointer to alt_tse_system_mac structure describing MAC of the system
+ * @param        psys_msgdma  pointer to alt_tse_system_msgdma structure describing SGDMA of the system
+ * @param        psys_mem  pointer to alt_tse_system_desc_mem structure describing Descriptor Memory of the system
+ * @param        psys_phy  pointer to alt_tse_system_phy structure describing PHY of the system
+ * @return      SUCCESS on success
+ *                 ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ *                 ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL
+ */
+alt_32 alt_tse_system_add_sys(
+    alt_tse_system_mac                    *psys_mac,
+    alt_tse_system_msgdma                *psys_msgdma,
+    alt_tse_system_desc_mem                *psys_mem,
+    alt_tse_system_shared_fifo            *psys_shared_fifo,
+    alt_tse_system_phy                     *psys_phy );
+
+
+/* @Function Description - Enable MDIO sharing for multiple single channel MAC
+ * 
+ * @API TYPE - Public
+ * @param        psys_mac_list  pointer to array of alt_tse_system_mac structure sharing MDIO block
+ * @param        number_of_mac  number of MAC sharing MDIO block
+ * @return      SUCCESS on success
+ *                 ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL
+ * Multi-channel MAC not supported
+ */
+alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac);
+
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Public
+ * @param pmac          Pointer to the TSE MAC Control Interface Base address
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac);
+
+/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group
+ * @API Type:               Public
+ * @param pmac              Pointer to the TSE MAC Control Interface Base address
+ *        common_speed      common speed supported by all PHYs
+ * @return                  common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed);
+
+/********************************
+ *
+ * Internal API for TSE Driver 
+ *
+ *******************************/
+
+/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[]
+ * @API Type:        Internal
+ * @param psys_info  Pointer to the alt_tse_system_info structure
+ * @return           Index of TSE system structure in tse_mac_device[]
+ */
+alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info);
+
+
+/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_group structure
+ * @return            Index of alt_tse_mac_group structure in pmac_groups[]
+ */
+alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group);
+
+
+/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_info structure
+ * @return            Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info);
+
+/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac        Pointer to the TSE MAC Control Interface Base address
+ * @return            Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac);
+
+/* @Function Description: Perform switching of the TSE MAC speed.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Internal
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps
+ */
+alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed);
+
+
+/* @Function Description: Perform switching of the TSE MAC duplex mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Internal
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param duplex 1 = Full Duplex, 0 = Half Duplex
+ */
+alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex);
+
+
+/** @Function Description -  Determine link speed our PHY negotiated with our link partner.
+  *                          This is fully vendor specific depending on the PHY you are using.
+  * 
+  * @API TYPE - Internal
+  * @param  tse.mi.base MAC register map.
+  * @return 
+  * ----------------------------------------------------------------------------------
+  * |  BIT  | Value: Description                                                     |
+  * ----------------------------------------------------------------------------------
+  * | 31-23 | Reserved                                                               |
+  * |   23  | 1: Argument *pmac not found from the list of MAC detected during init  |
+  * |   22  | 1: No MDIO used by the MAC                                             |
+  * |   21  | 1: No PHY detected                                                     |
+  * |   20  | 1: No common speed found for Multi-port MAC                            |
+  * |   19  | 1: PHY auto-negotiation not completed                                  |
+  * |   18  | 1: No PHY profile match the detected PHY                               |
+  * |   17  | 1: PHY Profile not defined correctly                                   |
+  * |   16  | 1: Invalid speed read from PHY                                         |
+  * |  4-15 | Reserved                                                               |
+  * |    3  | 1: 10 Mbps link                                                        |
+  * |    2  | 1: 100 Mbps link                                                       |
+  * |    1  | 1: 1000 Mbps link                                                      |
+  * |    0  | 1: Full Duplex                    0: Half Duplex                       |
+  * ----------------------------------------------------------------------------------
+  * 
+  * If the link speed cannot be determined, it is fall back to 100 Mbps (customizable by changing ALTERA_TSE_MAC_SPEED_DEFAULT)
+  *                                         Full duplex (customizable by changing ALTERA_TSE_DUPLEX_MODE_DEFAULT)
+  */
+alt_32 getPHYSpeed(np_tse_mac *pmac);
+
+/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy);
+
+/* @Function Description: Write MDIO address to the MDIO address1 register of first MAC within MAC group
+ * @API Type:           Internal
+ * @param pmac          Pointer to the alt_tse_phy_info structure
+ * @param mdio_address  MDIO address to be written
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address);
+
+/** @Function Description -  Write value of data with bit_length number of bits to mdio register based on register location reg_num
+  *                          and start from bit location lsb_num.
+  * 
+  * @API TYPE - Internal
+  * @param  pphy             pointer to alt_tse_phy_info structure
+  * @param  reg_num          location of mdio register to be written.
+  * @param  lsb_num          least significant bit location of mdio register to be written.
+  * @param  bit_length       number of bits to be written to the register.
+  * @param  data             data to be written to the register at specific bit location of register.
+  * @return SUCCESS 
+  */
+alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data);
+
+
+
+/** @Function Description -  Read bit_length number of bits from mdio register based on register location reg_num
+  *                          and start from bit location lsb_num.
+  * 
+  * @API TYPE - Internal
+  * @param  pphy             pointer to alt_tse_phy_info structure
+  * @param  reg_num          location of mdio register to be read.
+  * @param  lsb_num          least significant bit location of mdio register to be read.
+  * @param  bit_length       number of bits to be read from the register.
+  * @return data read from mdio register 
+  */
+alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length);
+
+
+/* @Function Description: Add supported PHY to profile
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ * 
+ * User might add their own PHY by calling alt_tse_phy_add_profile()
+ */
+alt_32 alt_tse_phy_add_profile_default();
+
+
+
+/* @Function Description: Display PHYs available in profile
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ */
+alt_32 alt_tse_phy_print_profile();
+
+
+/* @Function Description: Store information of all the MAC available in the system
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      return SUCCESS
+ *              return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error
+ */
+alt_32 alt_tse_mac_group_init();
+
+/* @Function Description: Store information of all the PHYs connected to MAC to phy_list
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @return            Number of PHY not in profile
+ */
+alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group);
+
+
+/* @Function Description: Associate the PHYs connected to the structure in alt_tse_system_info.h
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @param pphy        Pointer to the TSE PHY info structure which hold information of PHY
+ * @return            return TSE_PHY_MAP_ERROR if mapping error
+ *                    return TSE_PHY_MAP_SUCCESS otherwise
+ */
+alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy);
+
+/* @Function Description: Configure operating mode of Altera PCS if available
+ * @API Type:           Internal
+ * @param pmac_info     pointer to MAC info variable
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info);
+
+/* @Function Description: Detect and initialize all the PHYs connected
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      SUCCESS
+ */
+alt_32 alt_tse_phy_init();
+
+
+
+/* @Function Description: Restart Auto-Negotiation for the PHY
+ * @API Type:                   Internal
+ * @param pphy                  Pointer to the alt_tse_phy_info structure
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *                              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold);
+
+
+/* @Function Description: Check link status of PHY and start Auto-Negotiation if it has not yet done
+ * @API Type:                   Internal
+ * @param pphy                  Pointer to the alt_tse_phy_info structure
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ */
+alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold);
+
+
+/* @Function Description: Get link capability of PHY and link partner
+ * @API Type:   Internal
+ * @param pmac  Pointer to the alt_tse_phy_info structure
+ * @return      return TSE_PHY_AN_COMPLETE if success
+ *              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy);
+
+
+/* @Function Description: Set the advertisement of PHY for 1000 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable);
+
+
+/* @Function Description: Set the advertisement of PHY for 100 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable);
+
+
+/* @Function Description: Set the advertisement of PHY for 10 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable);
+
+
+
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Internal
+ * @param pmac_group    Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group);
+
+
+
+/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group
+ * @API Type:               Internal
+ * @param pmac_group        Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ *        common_speed      common speed supported by all PHYs
+ * @return      common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed);
+
+
+
+/* @Function Description: Additional configuration for Marvell PHY
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address of MAC group
+ */
+alt_32 marvell_phy_cfg(np_tse_mac *pmac);
+
+/* @Function Description: Additional configuration for PEF7071 PHY
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address of MAC group
+ */
+alt_32 PEF7071_config(np_tse_mac *pmac);
+
+/* @Function Description: Change operating mode of Marvell PHY to GMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_gmii(np_tse_mac *pmac);
+
+/* @Function Description: Change operating mode of Marvell PHY to SGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_sgmii(np_tse_mac *pmac);
+
+/* @Function Description: Change operating mode of Marvell PHY to RGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_rgmii(np_tse_mac *pmac);
+
+/* @Function Description: Read link status from PHY specific status register of DP83848C
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 DP83848C_link_status_read(np_tse_mac *pmac);
+
+/* @Function Description: Read link status from PHY specific status register of PEF7071
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 PEF7071_link_status_read(np_tse_mac *pmac);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALTERA_AVALON_TSE_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h
new file mode 100644
index 0000000..a505a71
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_tse_system_info.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_TSE_SYSTEM_INFO_H__
+#define __ALTERA_AVALON_TSE_SYSTEM_INFO_H__
+
+#include "altera_avalon_tse.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/* Define whole TSE system (dedicated descriptor memory, no shared fifo) */
+#define TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    tse_name##_MDIO_SHARED,               \
+    tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_EXT_DESC_MEM,                     \
+	desc_mem_name##_BASE,                 \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (program memory as descriptor memory, no shared fifo) */
+#define TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    tse_name##_MDIO_SHARED,               \
+    tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_INT_DESC_MEM,                     \
+	TSE_INT_DESC_MEM,                     \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (dedicated descriptor memory, use shared fifo) */
+#define TSE_SYSTEM_EXT_MEM_WITH_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, shared_fifo_tx_name, shared_fifo_rx_name) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    tse_name##_MDIO_SHARED,               \
+    tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_EXT_DESC_MEM,                     \
+	desc_mem_name##_BASE,                 \
+	TSE_USE_SHARED_FIFO,                  \
+	shared_fifo_tx_name##_CONTROL_BASE,      \
+    shared_fifo_tx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT,   \
+	shared_fifo_rx_name##_CONTROL_BASE,      \
+    shared_fifo_rx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT,   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (program memory as descriptor memory, use shared fifo) */
+#define TSE_SYSTEM_INT_MEM_WITH_SHARED_FIFO(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, shared_fifo_tx_name, shared_fifo_rx_name) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    tse_name##_MDIO_SHARED,               \
+    tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_INT_DESC_MEM,                     \
+	TSE_INT_DESC_MEM,                     \
+	TSE_USE_SHARED_FIFO,                  \
+	shared_fifo_tx_name##_CONTROL_BASE,      \
+    shared_fifo_tx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT,   \
+	shared_fifo_rx_name##_CONTROL_BASE,      \
+    shared_fifo_rx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT,   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+
+
+/* Define whole TSE system (dedicated descriptor memory, no shared fifo, enable MDIO sharing on first MAC) */
+/* MDIO sharing not supported for Multi-channel MAC */
+#define TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, number_of_mac_mdio_sharing) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    TSE_ENABLE_MDIO_SHARING,              \
+    number_of_mac_mdio_sharing,           \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_EXT_DESC_MEM,                     \
+	desc_mem_name##_BASE,                 \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (program memory as descriptor memory, no shared fifo, enable MDIO sharing on first MAC) */
+/* MDIO sharing not supported for Multi-channel MAC */
+#define TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, number_of_mac_mdio_sharing) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    TSE_ENABLE_MDIO_SHARING,              \
+    number_of_mac_mdio_sharing,           \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_INT_DESC_MEM,                     \
+	TSE_INT_DESC_MEM,                     \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	TSE_NO_SHARED_FIFO,                   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (dedicated descriptor memory, use shared fifo, enable MDIO sharing on first MAC) */
+/* MDIO sharing not supported for Multi-channel MAC */
+#define TSE_SYSTEM_EXT_MEM_WITH_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, desc_mem_name, shared_fifo_tx_name, shared_fifo_rx_name, number_of_mac_mdio_sharing) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    TSE_ENABLE_MDIO_SHARING,              \
+    number_of_mac_mdio_sharing,           \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_EXT_DESC_MEM,                     \
+	desc_mem_name##_BASE,                 \
+	TSE_USE_SHARED_FIFO,                  \
+	shared_fifo_tx_name##_CONTROL_BASE,      \
+    shared_fifo_tx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT,   \
+	shared_fifo_rx_name##_CONTROL_BASE,      \
+    shared_fifo_rx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT,   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+
+/* Define whole TSE system (program memory as descriptor memory, use shared fifo, enable MDIO sharing on first MAC) */
+/* MDIO sharing not supported for Multi-channel MAC */
+#define TSE_SYSTEM_INT_MEM_WITH_SHARED_FIFO_ENABLE_MDIO_SHARING(tse_name, offset, msgdma_tx_name, msgdma_rx_name, phy_addres, phy_cfg_fp, shared_fifo_tx_name, shared_fifo_rx_name, number_of_mac_mdio_sharing) {  \
+    tse_name##_BASE + offset,             \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    TSE_ENABLE_MDIO_SHARING,              \
+    number_of_mac_mdio_sharing,           \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII,                 \
+    msgdma_tx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_NAME,            \
+    msgdma_rx_name##_CSR_IRQ,             \
+    TSE_INT_DESC_MEM,                     \
+	TSE_INT_DESC_MEM,                     \
+	TSE_USE_SHARED_FIFO,                  \
+	shared_fifo_tx_name##_CONTROL_BASE,      \
+    shared_fifo_tx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT,   \
+	shared_fifo_rx_name##_CONTROL_BASE,      \
+    shared_fifo_rx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT,   \
+	phy_addres,                           \
+    phy_cfg_fp                            \
+},
+	
+	
+	
+	
+/* Macro to define single component used by alt_tse_system_add_sys() */	
+/* Define MAC of TSE system */
+#define TSE_SYSTEM_MAC(tse_name)	      \
+	tse_name##_BASE,       			      \
+    tse_name##_TRANSMIT_FIFO_DEPTH,       \
+    tse_name##_RECEIVE_FIFO_DEPTH,        \
+    tse_name##_USE_MDIO,                  \
+    tse_name##_ENABLE_MACLITE,            \
+    tse_name##_MACLITE_GIGE,              \
+    tse_name##_IS_MULTICHANNEL_MAC,       \
+    tse_name##_NUMBER_OF_CHANNEL,         \
+    tse_name##_MDIO_SHARED,               \
+    tse_name##_NUMBER_OF_MAC_MDIO_SHARED, \
+    tse_name##_PCS,                       \
+    tse_name##_PCS_SGMII
+
+/* Define MSGDMA of TSE system */
+#define TSE_SYSTEM_MSGDMA(msgdma_tx_name, msgdma_rx_name)	\
+	msgdma_tx_name##_CSR_NAME,           \
+    msgdma_rx_name##_CSR_NAME,           \
+    msgdma_rx_name##_CSR_IRQ
+
+/* Define descriptor memory of TSE system (dedicated descriptor memory) */
+#define TSE_SYSTEM_DESC_MEM(desc_mem_name)	\
+    TSE_EXT_DESC_MEM,               \
+	desc_mem_name##_BASE
+
+/* Define descriptor memory of TSE system (program memory as descriptor memory) */
+#define TSE_SYSTEM_NO_DESC_MEM()	\
+    TSE_INT_DESC_MEM,               \
+    TSE_INT_DESC_MEM
+
+/* Define shared fifo of TSE system (use shared fifo) */
+#define TSE_SYSTEM_SHARED_FIFO(shared_fifo_tx_name, shared_fifo_rx_name)	\
+    TSE_USE_SHARED_FIFO,               \
+    shared_fifo_tx_name##_CONTROL_BASE,      \
+    shared_fifo_tx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_TX_DEPTH_DEFAULT,   \
+	shared_fifo_rx_name##_CONTROL_BASE,      \
+    shared_fifo_rx_name##_FILL_LEVEL_BASE,   \
+	ALTERA_TSE_SHARED_FIFO_RX_DEPTH_DEFAULT
+
+/* Define shared fifo of TSE system (no shared fifo) */
+#define TSE_SYSTEM_NO_SHARED_FIFO()	  \
+	TSE_NO_SHARED_FIFO,               \
+	TSE_NO_SHARED_FIFO,               \
+	TSE_NO_SHARED_FIFO,               \
+	TSE_NO_SHARED_FIFO,               \
+    TSE_NO_SHARED_FIFO,               \
+	TSE_NO_SHARED_FIFO,               \
+	TSE_NO_SHARED_FIFO
+	
+/* Define PHY of TSE system */
+#define TSE_SYSTEM_PHY(phy_addres, phy_cfg_fp)	\
+	phy_addres,           			\
+    phy_cfg_fp
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALTERA_AVALON_TSE_SYSTEM_INFO_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h
new file mode 100644
index 0000000..e560202
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart.h
@@ -0,0 +1,319 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_AVALON_UART_H__
+#define __ALT_AVALON_UART_H__
+
+#include <stddef.h>
+#include <sys/termios.h>
+
+#include "sys/alt_warning.h"
+
+#include "os/alt_sem.h"
+#include "os/alt_flag.h"
+#include "alt_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
+
+/*
+ ***********************************************************************
+ *********************** SMALL DRIVER **********************************
+ ***********************************************************************
+ */
+
+/*
+ * State structure definition. Each instance of the driver uses one
+ * of these structures to hold its associated state.
+ */
+
+typedef struct altera_avalon_uart_state_s
+{
+    unsigned int        base;
+} altera_avalon_uart_state;
+
+/*
+ * The macro ALTERA_AVALON_UART_STATE_INSTANCE is used by the 
+ * auto-generated file alt_sys_init.c to create an instance of this 
+ * device driver state.
+ */
+
+#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state)   \
+  altera_avalon_uart_state state =                  \
+    {                                               \
+      name##_BASE                                   \
+    }
+
+/*
+ * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file
+ * alt_sys_init.c to initialize an instance of the device driver state.
+ */
+
+#define ALTERA_AVALON_UART_STATE_INIT(name, state)
+
+#else /* fast driver */
+
+/*
+ **********************************************************************
+ *********************** FAST DRIVER **********************************
+ **********************************************************************
+ */
+
+/*
+ * ALT_AVALON_UART_READ_RDY and ALT_AVALON_UART_WRITE_RDY are the bitmasks 
+ * that define uC/OS-II event flags that are releated to this device.
+ *
+ * ALT_AVALON_UART_READY_RDY indicates that there is read data in the buffer 
+ * ready to be processed. ALT_UART_WRITE_RDY indicates that the transmitter is
+ * ready for more data.
+ */
+
+#define ALT_UART_READ_RDY  0x1
+#define ALT_UART_WRITE_RDY 0x2
+
+/*
+ * ALT_AVALON_UART_BUF_LEN is the length of the circular buffers used to hold
+ * pending transmit and receive data. This value must be a power of two.
+ */
+
+#define ALT_AVALON_UART_BUF_LEN (64)
+
+/*
+ * ALT_AVALON_UART_BUF_MSK is used as an internal convenience for detecting 
+ * the end of the arrays used to implement the transmit and receive buffers.
+ */
+
+#define ALT_AVALON_UART_BUF_MSK (ALT_AVALON_UART_BUF_LEN - 1)
+
+/*
+ * This is somewhat of an ugly hack, but we need some mechanism for
+ * representing the non-standard 9 bit mode provided by this UART. In this
+ * case we abscond with the 5 bit mode setting. The value CS5 is defined in
+ * termios.h.
+ */
+
+#define CS9 CS5
+
+/*
+ * The value ALT_AVALON_UART_FB is a value set in the devices flag field to
+ * indicate that the device has a fixed baud rate; i.e. if this flag is set
+ * software can not control the baud rate of the device.
+ */
+
+#define ALT_AVALON_UART_FB 0x1
+
+/*
+ * The value ALT_AVALON_UART_FC is a value set in the device flag field to
+ * indicate the the device is using flow control, i.e. the driver must 
+ * throttle on transmit if the nCTS pin is low.
+ */
+
+#define ALT_AVALON_UART_FC 0x2
+
+/*
+ * The altera_avalon_uart_state structure is used to hold device specific data.
+ * This includes the transmit and receive buffers.
+ *
+ * An instance of this structure is created in the auto-generated 
+ * alt_sys_init.c file for each UART listed in the systems PTF file. This is
+ * done using the ALTERA_AVALON_UART_STATE_INSTANCE macro given below.
+ */
+
+typedef struct altera_avalon_uart_state_s
+{
+  void*            base;            /* The base address of the device */
+  alt_u32          ctrl;            /* Shadow value of the control register */
+  volatile alt_u32 rx_start;        /* Start of the pending receive data */
+  volatile alt_u32 rx_end;          /* End of the pending receive data */
+  volatile alt_u32 tx_start;        /* Start of the pending transmit data */
+  volatile alt_u32 tx_end;          /* End of the pending transmit data */
+#ifdef ALTERA_AVALON_UART_USE_IOCTL
+  struct termios termios;           /* Current device configuration */
+  alt_u32          freq;            /* Current baud rate */
+#endif
+  alt_u32          flags;           /* Configuation flags */
+  ALT_FLAG_GRP     (events)         /* Event flags used for 
+                                     * foreground/background in mult-threaded
+                                     * mode */
+  ALT_SEM          (read_lock)      /* Semaphore used to control access to the 
+                                     * read buffer in multi-threaded mode */
+  ALT_SEM          (write_lock)     /* Semaphore used to control access to the
+                                     * write buffer in multi-threaded mode */
+  volatile alt_u8  rx_buf[ALT_AVALON_UART_BUF_LEN]; /* The receive buffer */
+  volatile alt_u8  tx_buf[ALT_AVALON_UART_BUF_LEN]; /* The transmit buffer */
+} altera_avalon_uart_state;
+
+/*
+ * Conditionally define the data structures used to process ioctl requests.
+ * The following macros are defined for use in creating a device instance:
+ *
+ * ALTERA_AVALON_UART_TERMIOS - Initialise the termios structure used to
+ *                              describe the UART configuration.
+ * ALTERA_AVALON_UART_FREQ    - Initialise the 'freq' field of the device
+ *                              structure, if the field exists.
+ * ALTERA_AVALON_UART_IOCTL   - Initialise the 'ioctl' field of the device
+ *                              callback structure, if ioctls are enabled.
+ */
+
+#ifdef ALTERA_AVALON_UART_USE_IOCTL
+
+#define ALTERA_AVALON_UART_TERMIOS(stop_bits,               \
+                                   parity,                  \
+                                   odd_parity,              \
+                                   data_bits,               \
+                                   ctsrts,                  \
+                                   baud)                    \
+{                                                           \
+  0,                                                        \
+  0,                                                        \
+  ((stop_bits == 2) ? CSTOPB: 0)      |                     \
+    ((parity) ? PARENB: 0)            |                     \
+    ((odd_parity) ? PAODD: 0)         |                     \
+    ((data_bits == 7) ? CS7: (data_bits == 9) ? CS9: CS8) | \
+    ((ctsrts) ? CRTSCTS : 0),                               \
+  0,                                                        \
+  0,                                                        \
+  {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},                  \
+  baud,                                                     \
+  baud                                                      \
+},
+#define ALTERA_AVALON_UART_FREQ(name) name##_FREQ,
+
+#else /* !ALTERA_AVALON_UART_USE_IOCTL */
+
+#define ALTERA_AVALON_UART_TERMIOS(stop_bits,  \
+                                   parity,     \
+                                   odd_parity, \
+                                   data_bits,  \
+                                   ctsrts,     \
+                                   baud)
+#define ALTERA_AVALON_UART_FREQ(name)
+
+#endif /* ALTERA_AVALON_UART_USE_IOCTL */
+
+/*
+ * The macro ALTERA_AVALON_UART_INSTANCE is used by the auto-generated file
+ * alt_sys_init.c to create an instance of this device driver state.
+ */
+
+#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \
+  altera_avalon_uart_state state =                     \
+   {                                                   \
+     (void*) name##_BASE,                              \
+     0,                                                \
+     0,                                                \
+     0,                                                \
+     0,                                                \
+     0,                                                \
+     ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS,      \
+                               (name##_PARITY == 'N'), \
+                               (name##_PARITY == 'O'), \
+                               name##_DATA_BITS,       \
+                               name##_USE_CTS_RTS,     \
+                               name##_BAUD)            \
+     ALTERA_AVALON_UART_FREQ(name)                     \
+     (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) |    \
+       (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0)   \
+   }
+
+/*
+ * altera_avalon_uart_init() is called by the auto-generated function 
+ * alt_sys_init() for each UART in the system. This is done using the 
+ * ALTERA_AVALON_UART_INIT macro given below.
+ *
+ * This function is responsible for performing all the run time initilisation
+ * for a device instance, i.e. registering the interrupt handler, and 
+ * regestering the device with the system.
+ */
+extern void altera_avalon_uart_init(altera_avalon_uart_state* sp,
+                                    alt_u32 irq_controller_id, alt_u32 irq);
+
+/*
+ * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file
+ * alt_sys_init.c to initialize an instance of the device driver state.
+ *
+ * This macro performs a sanity check to ensure that the interrupt has been
+ * connected for this device. If not, then an apropriate error message is 
+ * generated at build time.
+ */
+
+#define ALTERA_AVALON_UART_STATE_INIT(name, state)                         \
+  if (name##_IRQ == ALT_IRQ_NOT_CONNECTED)                                 \
+  {                                                                        \
+    ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". "       \
+                    "You have selected the interrupt driven version of "   \
+                    "the ALTERA Avalon UART driver, but the interrupt is " \
+                    "not connected for this device. You can select a "     \
+                    "polled mode driver by checking the 'small driver' "   \
+                    "option in the HAL configuration window, or by "       \
+                    "using the -DALTERA_AVALON_UART_SMALL preprocessor "   \
+                    "flag.");                                              \
+  }                                                                        \
+  else                                                                     \
+  {                                                                        \
+    altera_avalon_uart_init(&state, name##_IRQ_INTERRUPT_CONTROLLER_ID,    \
+      name##_IRQ);                                                         \
+  }
+
+#endif /* small driver */
+
+/*
+ * Include in case non-direct version of driver required.
+ */
+#include "altera_avalon_uart_fd.h"
+
+/*
+ * Map alt_sys_init macros to direct or non-direct versions.
+ */
+#ifdef ALT_USE_DIRECT_DRIVERS
+
+#define ALTERA_AVALON_UART_INSTANCE(name, state) \
+   ALTERA_AVALON_UART_STATE_INSTANCE(name, state)
+#define ALTERA_AVALON_UART_INIT(name, state) \
+   ALTERA_AVALON_UART_STATE_INIT(name, state)
+
+#else /* !ALT_USE_DIRECT_DRIVERS */
+
+#define ALTERA_AVALON_UART_INSTANCE(name, dev) \
+   ALTERA_AVALON_UART_DEV_INSTANCE(name, dev)
+#define ALTERA_AVALON_UART_INIT(name, dev) \
+   ALTERA_AVALON_UART_DEV_INIT(name, dev)
+
+#endif /* ALT_USE_DIRECT_DRIVERS */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_AVALON_UART_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h
new file mode 100644
index 0000000..c5ccd0c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_fd.h
@@ -0,0 +1,143 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_AVALON_UART_FD_H__
+#define __ALT_AVALON_UART_FD_H__
+
+#include "sys/alt_dev.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * Externally referenced routines
+ */
+extern int altera_avalon_uart_read_fd (alt_fd* fd, char* ptr, int len);
+extern int altera_avalon_uart_write_fd (alt_fd* fd, const char* ptr,
+  int len);
+
+/*
+ * Device structure definition. This is needed by alt_sys_init in order to 
+ * reserve memory for the device instance.
+ */
+typedef struct altera_avalon_uart_dev_s
+{
+  alt_dev        dev;
+  altera_avalon_uart_state state;
+} altera_avalon_uart_dev;
+
+#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
+
+/*
+ * Macros used by alt_sys_init when the ALT file descriptor facility is used.
+ */
+
+#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d)    \
+  static altera_avalon_uart_dev d =                 \
+    {                                               \
+      {                                             \
+        ALT_LLIST_ENTRY,                            \
+        name##_NAME,                                \
+        NULL, /* open */                            \
+        NULL, /* close */                           \
+        altera_avalon_uart_read_fd,                 \
+        altera_avalon_uart_write_fd,                \
+        NULL, /* lseek */                           \
+        NULL, /* fstat */                           \
+        NULL, /* ioctl */                           \
+      },                                            \
+      {                                             \
+        name##_BASE,                                \
+      }                                             \
+    }
+
+#define ALTERA_AVALON_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev)
+
+#else /* use fast version of the driver */
+
+extern int altera_avalon_uart_ioctl_fd (alt_fd* fd, int req, void* arg);
+extern int altera_avalon_uart_close_fd(alt_fd* fd);
+
+#ifdef ALTERA_AVALON_UART_USE_IOCTL
+#define ALTERA_AVALON_UART_IOCTL_FD altera_avalon_uart_ioctl_fd
+#else
+#define ALTERA_AVALON_UART_IOCTL_FD NULL
+#endif
+
+#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d)       \
+  static altera_avalon_uart_dev d =                    \
+   {                                                   \
+     {                                                 \
+       ALT_LLIST_ENTRY,                                \
+       name##_NAME,                                    \
+       NULL, /* open */                                \
+       altera_avalon_uart_close_fd,                    \
+       altera_avalon_uart_read_fd,                     \
+       altera_avalon_uart_write_fd,                    \
+       NULL, /* lseek */                               \
+       NULL, /* fstat */                               \
+       ALTERA_AVALON_UART_IOCTL_FD,                    \
+     },                                                \
+     {                                                 \
+       (void*) name##_BASE,                            \
+       0,                                              \
+       0,                                              \
+       0,                                              \
+       0,                                              \
+       0,                                              \
+       ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS,    \
+                               (name##_PARITY == 'N'), \
+                               (name##_PARITY == 'O'), \
+                               name##_DATA_BITS,       \
+                               name##_USE_CTS_RTS,     \
+                               name##_BAUD)            \
+       ALTERA_AVALON_UART_FREQ(name)                   \
+       (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) |  \
+         (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \
+     }                                                 \
+   }
+
+#define ALTERA_AVALON_UART_DEV_INIT(name, d)           \
+  {                                                    \
+    ALTERA_AVALON_UART_STATE_INIT(name, d.state);      \
+                                                       \
+    /* make the device available to the system */      \
+    alt_dev_reg(&d.dev);                               \
+  }
+
+#endif /* fast driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_AVALON_UART_FD_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h
new file mode 100644
index 0000000..3c4c31e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_avalon_uart_regs.h
@@ -0,0 +1,137 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_AVALON_UART_REGS_H__
+#define __ALTERA_AVALON_UART_REGS_H__
+
+#include <io.h>
+
+#define ALTERA_AVALON_UART_RXDATA_REG                 0
+#define IOADDR_ALTERA_AVALON_UART_RXDATA(base)        \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_RXDATA_REG)
+#define IORD_ALTERA_AVALON_UART_RXDATA(base)          \
+        IORD(base, ALTERA_AVALON_UART_RXDATA_REG) 
+#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data)    \
+        IOWR(base, ALTERA_AVALON_UART_RXDATA_REG, data)
+
+#define ALTERA_AVALON_UART_TXDATA_REG                 1
+#define IOADDR_ALTERA_AVALON_UART_TXDATA(base)        \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_TXDATA_REG)
+#define IORD_ALTERA_AVALON_UART_TXDATA(base)          \
+        IORD(base, ALTERA_AVALON_UART_TXDATA_REG)
+#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data)    \
+        IOWR(base, ALTERA_AVALON_UART_TXDATA_REG, data)
+
+#define ALTERA_AVALON_UART_STATUS_REG                 2
+#define IOADDR_ALTERA_AVALON_UART_STATUS(base)        \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_STATUS_REG)
+#define IORD_ALTERA_AVALON_UART_STATUS(base)          \
+        IORD(base, ALTERA_AVALON_UART_STATUS_REG) 
+#define IOWR_ALTERA_AVALON_UART_STATUS(base, data)    \
+        IOWR(base, ALTERA_AVALON_UART_STATUS_REG, data)
+
+#define ALTERA_AVALON_UART_STATUS_PE_MSK              (0x1)
+#define ALTERA_AVALON_UART_STATUS_PE_OFST             (0)
+#define ALTERA_AVALON_UART_STATUS_FE_MSK              (0x2)
+#define ALTERA_AVALON_UART_STATUS_FE_OFST             (1)
+#define ALTERA_AVALON_UART_STATUS_BRK_MSK             (0x4)
+#define ALTERA_AVALON_UART_STATUS_BRK_OFST            (2)
+#define ALTERA_AVALON_UART_STATUS_ROE_MSK             (0x8)
+#define ALTERA_AVALON_UART_STATUS_ROE_OFST            (3)
+#define ALTERA_AVALON_UART_STATUS_TOE_MSK             (0x10)
+#define ALTERA_AVALON_UART_STATUS_TOE_OFST            (4)
+#define ALTERA_AVALON_UART_STATUS_TMT_MSK             (0x20)
+#define ALTERA_AVALON_UART_STATUS_TMT_OFST            (5)
+#define ALTERA_AVALON_UART_STATUS_TRDY_MSK            (0x40)
+#define ALTERA_AVALON_UART_STATUS_TRDY_OFST           (6)
+#define ALTERA_AVALON_UART_STATUS_RRDY_MSK            (0x80)
+#define ALTERA_AVALON_UART_STATUS_RRDY_OFST           (7)
+#define ALTERA_AVALON_UART_STATUS_E_MSK               (0x100)
+#define ALTERA_AVALON_UART_STATUS_E_OFST              (8)
+#define ALTERA_AVALON_UART_STATUS_DCTS_MSK            (0x400)
+#define ALTERA_AVALON_UART_STATUS_DCTS_OFST           (10)
+#define ALTERA_AVALON_UART_STATUS_CTS_MSK             (0x800)
+#define ALTERA_AVALON_UART_STATUS_CTS_OFST            (11)
+#define ALTERA_AVALON_UART_STATUS_EOP_MSK             (0x1000)
+#define ALTERA_AVALON_UART_STATUS_EOP_OFST            (12)
+
+#define ALTERA_AVALON_UART_CONTROL_REG                3
+#define IOADDR_ALTERA_AVALON_UART_CONTROL(base)       \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_CONTROL_REG)
+#define IORD_ALTERA_AVALON_UART_CONTROL(base)         \
+        IORD(base, ALTERA_AVALON_UART_CONTROL_REG)
+#define IOWR_ALTERA_AVALON_UART_CONTROL(base, data)   \
+        IOWR(base, ALTERA_AVALON_UART_CONTROL_REG, data)
+
+#define ALTERA_AVALON_UART_CONTROL_PE_MSK             (0x1)
+#define ALTERA_AVALON_UART_CONTROL_PE_OFST            (0)
+#define ALTERA_AVALON_UART_CONTROL_FE_MSK             (0x2)
+#define ALTERA_AVALON_UART_CONTROL_FE_OFST            (1)
+#define ALTERA_AVALON_UART_CONTROL_BRK_MSK            (0x4)
+#define ALTERA_AVALON_UART_CONTROL_BRK_OFST           (2)
+#define ALTERA_AVALON_UART_CONTROL_ROE_MSK            (0x8)
+#define ALTERA_AVALON_UART_CONTROL_ROE_OFST           (3)
+#define ALTERA_AVALON_UART_CONTROL_TOE_MSK            (0x10)
+#define ALTERA_AVALON_UART_CONTROL_TOE_OFST           (4)
+#define ALTERA_AVALON_UART_CONTROL_TMT_MSK            (0x20)
+#define ALTERA_AVALON_UART_CONTROL_TMT_OFST           (5)
+#define ALTERA_AVALON_UART_CONTROL_TRDY_MSK           (0x40)
+#define ALTERA_AVALON_UART_CONTROL_TRDY_OFST          (6)
+#define ALTERA_AVALON_UART_CONTROL_RRDY_MSK           (0x80)
+#define ALTERA_AVALON_UART_CONTROL_RRDY_OFST          (7)
+#define ALTERA_AVALON_UART_CONTROL_E_MSK              (0x100)
+#define ALTERA_AVALON_UART_CONTROL_E_OFST             (8)
+#define ALTERA_AVALON_UART_CONTROL_DCTS_MSK           (0x400)
+#define ALTERA_AVALON_UART_CONTROL_DCTS_OFST          (10)
+#define ALTERA_AVALON_UART_CONTROL_RTS_MSK            (0x800)
+#define ALTERA_AVALON_UART_CONTROL_RTS_OFST           (11)
+#define ALTERA_AVALON_UART_CONTROL_EOP_MSK            (0x1000)
+#define ALTERA_AVALON_UART_CONTROL_EOP_OFST           (12)
+
+#define ALTERA_AVALON_UART_DIVISOR_REG                4
+#define IOADDR_ALTERA_AVALON_UART_DIVISOR(base)       \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_DIVISOR_REG)
+#define IORD_ALTERA_AVALON_UART_DIVISOR(base)         \
+        IORD(base, ALTERA_AVALON_UART_DIVISOR_REG) 
+#define IOWR_ALTERA_AVALON_UART_DIVISOR(base, data)   \
+        IOWR(base, ALTERA_AVALON_UART_DIVISOR_REG, data)
+
+#define ALTERA_AVALON_UART_EOP_REG                    5
+#define IOADDR_ALTERA_AVALON_UART_EOP(base)           \
+        __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_EOP_REG)
+#define IORD_ALTERA_AVALON_UART_EOP(base)             \
+        IORD(base, ALTERA_AVALON_UART_EOP_REG)
+#define IOWR_ALTERA_AVALON_UART_EOP(base, data)       \
+        IOWR(base, ALTERA_AVALON_UART_EOP_REG, data)
+
+#define ALTERA_AVALON_UART_EOP_MSK                    (0xFF)
+#define ALTERA_AVALON_UART_EOP_OFST                   (0)
+
+#endif /* __ALTERA_AVALON_UART_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h
new file mode 100644
index 0000000..d796843
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse.h
@@ -0,0 +1,45 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_ETH_TSE_H__
+#define __ALTERA_ETH_TSE_H__
+
+#if defined(ALT_INICHE)
+
+#include "iniche/altera_eth_tse_iniche.h"
+
+#else
+
+#define ALTERA_ETH_TSE_INSTANCE(name, dev) extern int alt_no_storage
+#define ALTERA_ETH_TSE_INIT(name, dev) while(0)     
+
+#endif
+
+#endif /* __ALTERA_ETH_TSE_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h
new file mode 100644
index 0000000..7a2da9d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_eth_tse_regs.h
@@ -0,0 +1,735 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_ETH_TSE_REGS_H__
+#define __ALTERA_ETH_TSE_REGS_H__
+
+
+#include "alt_types.h"
+#include "io.h"
+
+/* MAC Registers */
+
+/* Revision register (read-only) */
+#define IOADDR_ALTERA_TSEMAC_REV(base) __IO_CALC_ADDRESS_NATIVE(base,0x0)
+#define IORD_ALTERA_TSEMAC_REV(base)   IORD_32DIRECT(base, 0)
+
+/* Scratch register */
+#define IOADDR_ALTERA_TSEMAC_SCRATCH(base)    __IO_CALC_ADDRESS_NATIVE(base,0x4)
+#define IORD_ALTERA_TSEMAC_SCRATCH(base)      IORD_32DIRECT(base, 0x4)
+#define IOWR_ALTERA_TSEMAC_SCRATCH(base,data) IOWR_32DIRECT(base, 0x4, data)
+
+/* Command register */
+#define IOADDR_ALTERA_TSEMAC_CMD_CONFIG(base)    __IO_CALC_ADDRESS_NATIVE(base,0x8)
+#define IORD_ALTERA_TSEMAC_CMD_CONFIG(base)      IORD_32DIRECT(base, 0x8)
+#define IOWR_ALTERA_TSEMAC_CMD_CONFIG(base,data) IOWR_32DIRECT(base, 0x8, data)
+
+/* Command register bit definitions */
+#define ALTERA_TSEMAC_CMD_TX_ENA_OFST          (0)   
+#define ALTERA_TSEMAC_CMD_TX_ENA_MSK           (0x1)
+#define ALTERA_TSEMAC_CMD_RX_ENA_OFST          (1)   
+#define ALTERA_TSEMAC_CMD_RX_ENA_MSK           (0x2)
+#define ALTERA_TSEMAC_CMD_XON_GEN_OFST        (2) 
+#define ALTERA_TSEMAC_CMD_XON_GEN_MSK         (0x4)
+#define ALTERA_TSEMAC_CMD_ETH_SPEED_OFST       (3)
+#define ALTERA_TSEMAC_CMD_ETH_SPEED_MSK        (0x8)
+#define ALTERA_TSEMAC_CMD_PROMIS_EN_OFST       (4)
+#define ALTERA_TSEMAC_CMD_PROMIS_EN_MSK        (0x10)
+#define ALTERA_TSEMAC_CMD_PAD_EN_OFST          (5)
+#define ALTERA_TSEMAC_CMD_PAD_EN_MSK           (0x20)
+#define ALTERA_TSEMAC_CMD_CRC_FWD_OFST         (6)  
+#define ALTERA_TSEMAC_CMD_CRC_FWD_MSK          (0x40)
+#define ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST       (7)
+#define ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK        (0x80)
+#define ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST    (8)
+#define ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK     (0x100)
+#define ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST     (9)
+#define ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK      (0x200)
+#define ALTERA_TSEMAC_CMD_HD_ENA_OFST          (10)
+#define ALTERA_TSEMAC_CMD_HD_ENA_MSK           (0x400)
+#define ALTERA_TSEMAC_CMD_EXCESS_COL_OFST      (11)
+#define ALTERA_TSEMAC_CMD_EXCESS_COL_MSK       (0x800)
+#define ALTERA_TSEMAC_CMD_LATE_COL_OFST        (12)
+#define ALTERA_TSEMAC_CMD_LATE_COL_MSK         (0x1000)
+#define ALTERA_TSEMAC_CMD_SW_RESET_OFST        (13)
+#define ALTERA_TSEMAC_CMD_SW_RESET_MSK         (0x2000)
+#define ALTERA_TSEMAC_CMD_MHASH_SEL_OFST       (14)
+#define ALTERA_TSEMAC_CMD_MHASH_SEL_MSK        (0x4000)
+#define ALTERA_TSEMAC_CMD_LOOPBACK_OFST        (15)
+#define ALTERA_TSEMAC_CMD_LOOPBACK_MSK         (0x8000)
+/* Bits (18:16) = address select */
+#define ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST     (16)   
+#define ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK      (0x70000)  
+#define ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST       (19)
+#define ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK        (0x80000)
+#define ALTERA_TSEMAC_CMD_SLEEP_OFST           (20)
+#define ALTERA_TSEMAC_CMD_SLEEP_MSK            (0x100000)
+#define ALTERA_TSEMAC_CMD_WAKEUP_OFST          (21)
+#define ALTERA_TSEMAC_CMD_WAKEUP_MSK           (0x200000)
+#define ALTERA_TSEMAC_CMD_XOFF_GEN_OFST        (22)
+#define ALTERA_TSEMAC_CMD_XOFF_GEN_MSK         (0x400000)
+#define ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST    (23)
+#define ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK     (0x800000)
+#define ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST (24)
+#define ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK  (0x1000000)
+#define ALTERA_TSEMAC_CMD_ENA_10_OFST          (25)
+#define ALTERA_TSEMAC_CMD_ENA_10_MSK           (0x2000000)
+#define ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST     (26)
+#define ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK      (0x4000000)
+/* Bits (30..27) reserved */
+#define ALTERA_TSEMAC_CMD_CNT_RESET_OFST       (31)
+#define ALTERA_TSEMAC_CMD_CNT_RESET_MSK        (0x80000000)
+
+/* Low word (bits 31:0) of MAC address */
+#define IOADDR_ALTERA_TSEMAC_MAC_0(base)    __IO_CALC_ADDRESS_NATIVE(base,0xC)
+#define IORD_ALTERA_TSEMAC_MAC_0(base)      IORD_32DIRECT(base, 0xC)
+#define IOWR_ALTERA_TSEMAC_MAC_0(base,data) IOWR_32DIRECT(base, 0xC, data)
+
+/* High half-word (bits 47:32) of MAC address. Upper 16 bits reserved */
+#define IOADDR_ALTERA_TSEMAC_MAC_1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x10)
+#define IORD_ALTERA_TSEMAC_MAC_1(base)      IORD_32DIRECT(base, 0x10)
+#define IOWR_ALTERA_TSEMAC_MAC_1(base,data) IOWR_32DIRECT(base, 0x10, data)
+
+/* Maximum frame length (bits 13:0), (bits 31:14 are reserved) */
+#define IOADDR_ALTERA_TSEMAC_FRM_LENGTH(base)    __IO_CALC_ADDRESS_NATIVE(base,0x14)
+#define IORD_ALTERA_TSEMAC_FRM_LENGTH(base)      IORD_32DIRECT(base, 0x14)
+#define IOWR_ALTERA_TSEMAC_FRM_LENGTH(base,data) IOWR_32DIRECT(base, 0x14, data)
+
+/* Receive pause quanta. Bits 31:16 reserved */
+#define IOADDR_ALTERA_TSEMAC_PAUSE_QUANT(base)    __IO_CALC_ADDRESS_NATIVE(base,0x18)
+#define IORD_ALTERA_TSEMAC_PAUSE_QUANT(base)      IORD_32DIRECT(base, 0x18)
+#define IOWR_ALTERA_TSEMAC_PAUSE_QUANT(base,data) IOWR_32DIRECT(base, 0x18, data)
+
+/* Sets RX FIFO section empty threshold */
+#define IOADDR_ALTERA_TSEMAC_RX_SECTION_EMPTY(base)    __IO_CALC_ADDRESS_NATIVE(base,0x1C)
+#define IORD_ALTERA_TSEMAC_RX_SECTION_EMPTY(base)      IORD_32DIRECT(base, 0x1C)
+#define IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(base,data) IOWR_32DIRECT(base, 0x1C, data)
+
+/* Set RX FIFO section full threshold */
+#define IOADDR_ALTERA_TSEMAC_RX_SECTION_FULL(base)    __IO_CALC_ADDRESS_NATIVE(base,0x20)
+#define IORD_ALTERA_TSEMAC_RX_SECTION_FULL(base)      IORD_32DIRECT(base, 0x20)
+#define IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(base,data) IOWR_32DIRECT(base, 0x20, data)
+
+/* Set TX FIFO section empty threshold */
+#define IOADDR_ALTERA_TSEMAC_TX_SECTION_EMPTY(base)    __IO_CALC_ADDRESS_NATIVE(base,0x24)
+#define IORD_ALTERA_TSEMAC_TX_SECTION_EMPTY(base)      IORD_32DIRECT(base, 0x24)
+#define IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(base,data) IOWR_32DIRECT(base, 0x24, data)
+
+/* Set TX FIFO section full threshold */
+#define IOADDR_ALTERA_TSEMAC_TX_SECTION_FULL(base)    __IO_CALC_ADDRESS_NATIVE(base,0x28)
+#define IORD_ALTERA_TSEMAC_TX_SECTION_FULL(base)      IORD_32DIRECT(base, 0x28)
+#define IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(base,data) IOWR_32DIRECT(base, 0x28, data)
+
+/* Set RX FIFO almost empty threshold */
+#define IOADDR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base)    __IO_CALC_ADDRESS_NATIVE(base,0x2c)
+#define IORD_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base)      IORD_32DIRECT(base, 0x2c)
+#define IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(base,data) IOWR_32DIRECT(base, 0x2c, data)
+
+/* Set RX FIFO almost full threshold */
+#define IOADDR_ALTERA_TSEMAC_RX_ALMOST_FULL(base)    __IO_CALC_ADDRESS_NATIVE(base,0x30)
+#define IORD_ALTERA_TSEMAC_RX_ALMOST_FULL(base)      IORD_32DIRECT(base, 0x30)
+#define IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(base,data) IOWR_32DIRECT(base, 0x30, data)
+
+/* Set TX FIFO almost empty threshold */
+#define IOADDR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base)    __IO_CALC_ADDRESS_NATIVE(base,0x34)
+#define IORD_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base)      IORD_32DIRECT(base, 0x34)
+#define IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(base,data) IOWR_32DIRECT(base, 0x34, data)
+
+/* Set TX FIFO almost full threshold */
+#define IOADDR_ALTERA_TSEMAC_TX_ALMOST_FULL(base)    __IO_CALC_ADDRESS_NATIVE(base,0x38)
+#define IORD_ALTERA_TSEMAC_TX_ALMOST_FULL(base)      IORD_32DIRECT(base, 0x38)
+#define IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(base,data) IOWR_32DIRECT(base, 0x38, data)
+
+/* MDIO Address of PHY 0. Bits 31:5 reserved */
+#define IOADDR_ALTERA_TSEMAC_MDIO_ADDR0(base)    __IO_CALC_ADDRESS_NATIVE(base,0x3c)
+#define IORD_ALTERA_TSEMAC_MDIO_ADDR0(base)      IORD_32DIRECT(base, 0x3c)
+#define IOWR_ALTERA_TSEMAC_MDIO_ADDR0(base,data) IOWR_32DIRECT(base, 0x3c, data)
+
+/* MDIO Address of PHY 1. Bits 31:5 reserved */
+#define IOADDR_ALTERA_TSEMAC_MDIO_ADDR1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x40)
+#define IORD_ALTERA_TSEMAC_MDIO_ADDR1(base)      IORD_32DIRECT(base, 0x40)
+#define IOWR_ALTERA_TSEMAC_MDIO_ADDR1(base,data) IOWR_32DIRECT(base, 0x40, data)
+
+/* -- Register offsets 0x44 to 0x54 reserved -- */
+
+/* Register read access status */
+#define IOADDR_ALTERA_TSEMAC_REG_STAT(base)    __IO_CALC_ADDRESS_NATIVE(base,0x58)
+#define IORD_ALTERA_TSEMAC_REG_STAT(base)      IORD_32DIRECT(base, 0x58)
+
+
+/* Inter-packet gap. Bits 31:5 reserved/ */
+#define IOADDR_ALTERA_TSEMAC_TX_IPG_LENGTH(base)     __IO_CALC_ADDRESS_NATIVE(base,0x5c)
+#define IORD_ALTERA_TSEMAC_TX_IPG_LENGTH(base)      IORD_32DIRECT(base, 0x5c)
+#define IOWR_ALTERA_TSEMAC_TX_IPG_LENGTH(base,data)      IOWR_32DIRECT(base, 0x5c, data)
+
+
+/* IEEE802.3, RMON, and MIB-II SNMP Statistic event counters */
+#define IOADDR_ALTERA_TSEMAC_A_MACID_1(base)     __IO_CALC_ADDRESS_NATIVE(base,0x60)
+#define IORD_ALTERA_TSEMAC_A_MACID_1(base)      IORD_32DIRECT(base, 0x60)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_MACID_2(base)     __IO_CALC_ADDRESS_NATIVE(base,0x64)
+#define IORD_ALTERA_TSEMAC_A_MACID_2(base)      IORD_32DIRECT(base, 0x64)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_FRAMES_TX_OK(base)     __IO_CALC_ADDRESS_NATIVE(base,0x68)
+#define IORD_ALTERA_TSEMAC_A_FRAMES_TX_OK(base)      IORD_32DIRECT(base, 0x68)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_FRAMES_RX_OK(base)     __IO_CALC_ADDRESS_NATIVE(base,0x6c)
+#define IORD_ALTERA_TSEMAC_A_FRAMES_RX_OK(base)      IORD_32DIRECT(base, 0x6c)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_FRAME_CHECK_SEQ_ERRS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x70)
+#define IORD_ALTERA_TSEMAC_A_FRAME_CHECK_SEQ_ERRS(base)      IORD_32DIRECT(base, 0x70)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_ALIGNMENT_ERRS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x74)
+#define IORD_ALTERA_TSEMAC_A_ALIGNMENT_ERRS(base)      IORD_32DIRECT(base, 0x74)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_OCTETS_TX_OK(base)     __IO_CALC_ADDRESS_NATIVE(base,0x78)
+#define IORD_ALTERA_TSEMAC_A_OCTETS_TX_OK(base)      IORD_32DIRECT(base, 0x78)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_OCTETS_RX_OK(base)     __IO_CALC_ADDRESS_NATIVE(base,0x7c)
+#define IORD_ALTERA_TSEMAC_A_OCTETS_RX_OK(base)      IORD_32DIRECT(base, 0x7c)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_TX_PAUSE_MAC_CTRL_FRAMES(base)     __IO_CALC_ADDRESS_NATIVE(base,0x80)
+#define IORD_ALTERA_TSEMAC_A_TX_PAUSE_MAC_CTRL_FRAMES(base)      IORD_32DIRECT(base, 0x80)
+
+
+#define IOADDR_ALTERA_TSEMAC_A_RX_PAUSE_MAC_CTRL_FRAMES(base)     __IO_CALC_ADDRESS_NATIVE(base,0x84)
+#define IORD_ALTERA_TSEMAC_A_RX_PAUSE_MAC_CTRL_FRAMES(base)      IORD_32DIRECT(base, 0x84)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_IN_ERRORS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x88)
+#define IORD_ALTERA_TSEMAC_IF_IN_ERRORS(base)      IORD_32DIRECT(base, 0x88)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_OUT_ERRORS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x8c)
+#define IORD_ALTERA_TSEMAC_IF_OUT_ERRORS(base)      IORD_32DIRECT(base, 0x8c)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_IN_UCAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x90)
+#define IORD_ALTERA_TSEMAC_IF_IN_UCAST_PKTS(base)      IORD_32DIRECT(base, 0x90)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_IN_MULTICAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x94)
+#define IORD_ALTERA_TSEMAC_IF_IN_MULTICAST_PKTS(base)      IORD_32DIRECT(base, 0x94)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_IN_BROADCAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x98)
+#define IORD_ALTERA_TSEMAC_IF_IN_BROADCAST_PKTS(base)      IORD_32DIRECT(base, 0x98)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_OUT_DISCARDS(base)     __IO_CALC_ADDRESS_NATIVE(base,0x9C)
+#define IORD_ALTERA_TSEMAC_IF_OUT_DISCARDS(base)      IORD_32DIRECT(base, 0x9C)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_OUT_UCAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xA0)
+#define IORD_ALTERA_TSEMAC_IF_OUT_UCAST_PKTS(base)      IORD_32DIRECT(base, 0xA0)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_OUT_MULTICAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xA4)
+#define IORD_ALTERA_TSEMAC_IF_OUT_MULTICAST_PKTS(base)      IORD_32DIRECT(base, 0xA4)
+
+
+#define IOADDR_ALTERA_TSEMAC_IF_OUT_BROADCAST_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xA8)
+#define IORD_ALTERA_TSEMAC_IF_OUT_BROADCAST_PKTS(base)      IORD_32DIRECT(base, 0xA8)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_DROP_EVENTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xAC)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_DROP_EVENTS(base)      IORD_32DIRECT(base, 0xAC)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xB0)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_OCTETS(base)      IORD_32DIRECT(base, 0xB0)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xB4)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS(base)      IORD_32DIRECT(base, 0xB4)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_UNDERSIZE_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xB8)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_UNDERSIZE_PKTS(base)      IORD_32DIRECT(base, 0xB8)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_OVERSIZE_PKTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xBC)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_OVERSIZE_PKTS(base)      IORD_32DIRECT(base, 0xBC)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_64_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xC0)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_64_OCTETS(base)      IORD_32DIRECT(base, 0xC0)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_65_TO_127_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xC4)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_65_TO_127_OCTETS(base)      IORD_32DIRECT(base, 0xC4)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_128_TO_255_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xC8)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_128_TO_255_OCTETS(base)      IORD_32DIRECT(base, 0xC8)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_256_TO_511_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xCC)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_256_TO_511_OCTETS(base)      IORD_32DIRECT(base, 0xCC)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_512_TO_1023_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xD0)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_512_TO_1023_OCTETS(base)      IORD_32DIRECT(base, 0xD0)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_1024_TO_1518_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xD4)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_1024_TO_1518_OCTETS(base)      IORD_32DIRECT(base, 0xD4)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_PKTS_1519_TO_X_OCTETS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xD8)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_PKTS_1519_TO_X_OCTETS(base)      IORD_32DIRECT(base, 0xD8)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_JABBERS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xDC)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_JABBERS(base)      IORD_32DIRECT(base, 0xDC)
+
+
+#define IOADDR_ALTERA_TSEMAC_ETHER_STATS_FRAGMENTS(base)     __IO_CALC_ADDRESS_NATIVE(base,0xE0)
+#define IORD_ALTERA_TSEMAC_ETHER_STATS_FRAGMENTS(base)      IORD_32DIRECT(base, 0xE0)
+
+
+
+/* Register offset 0xE4 reserved */
+
+#define IOADDR_ALTERA_TSEMAC_TX_CMD_STAT(base)     __IO_CALC_ADDRESS_NATIVE(base,0xE8)
+#define IORD_ALTERA_TSEMAC_TX_CMD_STAT(base)      IORD_32DIRECT(base, 0xE8)
+#define IOWR_ALTERA_TSEMAC_TX_CMD_STAT(base,data) IOWR_32DIRECT(base, 0xE8, data)
+
+
+#define IOADDR_ALTERA_TSEMAC_RX_CMD_STAT(base)     __IO_CALC_ADDRESS_NATIVE(base,0xEC)
+#define IORD_ALTERA_TSEMAC_RX_CMD_STAT(base)      IORD_32DIRECT(base, 0xEC)
+#define IOWR_ALTERA_TSEMAC_RX_CMD_STAT(base,data) IOWR_32DIRECT(base, 0xEC, data)
+
+
+#define ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST				(17)   
+#define ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK				(0x20000)
+#define ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST			(18)   
+#define ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK				(0x40000)
+
+#define ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST			(25)   
+#define ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK				(0x2000000)
+
+/* Register offset 0xF0 to 0xFC reserved */
+
+
+/*
+ * Share Multi Channel FIFO 
+ * 
+ * ## Threshold Register Access ## - Av-MM interface 1
+ */
+#define IOADDR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base)     __IO_CALC_ADDRESS_NATIVE(base,0x00)
+#define IORD_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base)   IORD_32DIRECT(base, 0x00)
+#define IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(base,data)   IOWR_32DIRECT(base, 0x00, data)
+
+
+#define IOADDR_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base)     __IO_CALC_ADDRESS_NATIVE(base,0x04)
+#define IORD_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base)   IORD_32DIRECT(base, 0x04)
+#define IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_EMPTY_THRESHOLD(base,data)   IOWR_32DIRECT(base, 0x04, data)
+
+#define IOADDR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base)     __IO_CALC_ADDRESS_NATIVE(base,0x08)
+#define IORD_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base)   IORD_32DIRECT(base, 0x08)
+#define IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(base,data)   IOWR_32DIRECT(base, 0x08, data)
+
+#define IOADDR_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base)     __IO_CALC_ADDRESS_NATIVE(base,0x10)
+#define IORD_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base)   IORD_32DIRECT(base, 0x10)
+#define IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_EMPTY_THRESHOLD(base,data)   IOWR_32DIRECT(base, 0x10, data)
+
+/*
+ * Share Multi Channel FIFO 
+ * 
+ * ## Fill Level Query Access ## - Av-MM interface 2
+ */
+#define IOADDR_ALTERA_MULTI_CHAN_FILL_LEVEL(base, channel)     __IO_CALC_ADDRESS_NATIVE(base,(channel * 0x04))
+#define IORD_ALTERA_MULTI_CHAN_FILL_LEVEL(base, channel)   IORD_32DIRECT(base, (channel * 0x04))
+ 
+/* 
+ * Hash table occupies registers 0x100:0x1FC. Explicit register definitions
+ * are not provided. If programatic access to the hash table is necessary,
+ * define a region of uncached memory using alt_remap_uncached, or use the 
+ * IORD/IOWR macros to access memory at the Ethernet MAC base address plus
+ * offsets in the range 0x100 to 0x1Fc.
+ * 
+ * The hash table's purpose is to provide multicast address resolution. When
+ * programming the table, only bit '0' is significant. If a '1' is written,
+ * all multicast addresses represented by the hash code (Address bits 0 to 5)
+ * are accepted by the controller. If a '0' is written, matching multicast
+ * addresses are rejected.
+ */
+#define IOADDR_ALTERA_TSEMAC_HASH_TABLE(base) \
+  __IO_CALC_ADDRESS_NATIVE(base,0x100)
+#define IORD_ALTERA_TSEMAC_HASH_TABLE(base, offset) \
+  IORD_32DIRECT(base, (0x100 + offset))
+#define IOWR_ALTERA_TSEMAC_HASH_TABLE(base, offset, data) \
+  IOWR_32DIRECT(base, (0x100 + offset), data)
+  
+ /* 
+  * PHY MDIO registers 
+  * 
+  * For all registers, bits 15:0 are relevant. Bits 31:16 should be written
+  * with 0 and ignored on read.
+  */
+
+/* Generic access macro for either MDIO port */
+#define IOADDR_ALTERA_TSEMAC_MDIO(base, mdio) \
+  __IO_CALC_ADDRESS_NATIVE(base, (0x200 + (mdio * 0x80)) )
+  
+#define IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num) \
+  IORD_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)) )
+
+#define IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data) \
+  IOWR_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)), data)
+
+
+
+/* Low word (bits 31:0) of supplemental MAC address 0*/
+#define IOADDR_ALTERA_TSEMAC_SMAC_0_0(base)    __IO_CALC_ADDRESS_NATIVE(base,0x300)
+#define IORD_ALTERA_TSEMAC_SMAC_0_0(base)      IORD_32DIRECT(base, 0x300)
+#define IOWR_ALTERA_TSEMAC_SMAC_0_0(base,data) IOWR_32DIRECT(base, 0x300, data)
+
+/* High half-word (bits 47:32) of supplemental MAC address 0. Upper 16 bits reserved */
+#define IOADDR_ALTERA_TSEMAC_SMAC_0_1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x304)
+#define IORD_ALTERA_TSEMAC_SMAC_0_1(base)      IORD_32DIRECT(base, 0x304)
+#define IOWR_ALTERA_TSEMAC_SMAC_0_1(base,data) IOWR_32DIRECT(base, 0x304, data)
+
+/* Low word (bits 31:0) of supplemental MAC address 1 */
+#define IOADDR_ALTERA_TSEMAC_SMAC_1_0(base)    __IO_CALC_ADDRESS_NATIVE(base,0x308)
+#define IORD_ALTERA_TSEMAC_SMAC_1_0(base)      IORD_32DIRECT(base, 0x308)
+#define IOWR_ALTERA_TSEMAC_SMAC_1_0(base,data) IOWR_32DIRECT(base, 0x308, data)
+
+/* High half-word (bits 47:32) of supplemental MAC address 1. Upper 16 bits reserved */
+#define IOADDR_ALTERA_TSEMAC_SMAC_1_1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x30C)
+#define IORD_ALTERA_TSEMAC_SMAC_1_1(base)      IORD_32DIRECT(base, 0x30C)
+#define IOWR_ALTERA_TSEMAC_SMAC_1_1(base,data) IOWR_32DIRECT(base, 0x30C, data)
+
+/* Low word (bits 31:0) of supplemental MAC address 2 */
+#define IOADDR_ALTERA_TSEMAC_SMAC_2_0(base)    __IO_CALC_ADDRESS_NATIVE(base,0x310)
+#define IORD_ALTERA_TSEMAC_SMAC_2_0(base)      IORD_32DIRECT(base, 0x310)
+#define IOWR_ALTERA_TSEMAC_SMAC_2_0(base,data) IOWR_32DIRECT(base, 0x310, data)
+
+/* High half-word (bits 47:32) of supplemental MAC address 2. Upper 16 bits reserved */
+#define IOADDR_ALTERA_TSEMAC_SMAC_2_1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x314)
+#define IORD_ALTERA_TSEMAC_SMAC_2_1(base)      IORD_32DIRECT(base, 0x314)
+#define IOWR_ALTERA_TSEMAC_SMAC_2_1(base,data) IOWR_32DIRECT(base, 0x314, data)
+
+/* Low word (bits 31:0) of supplemental MAC address 3 */
+#define IOADDR_ALTERA_TSEMAC_SMAC_3_0(base)    __IO_CALC_ADDRESS_NATIVE(base,0x318)
+#define IORD_ALTERA_TSEMAC_SMAC_3_0(base)      IORD_32DIRECT(base, 0x318)
+#define IOWR_ALTERA_TSEMAC_SMAC_3_0(base,data) IOWR_32DIRECT(base, 0x318, data)
+
+/* High half-word (bits 47:32) of supplemental MAC address 3. Upper 16 bits reserved */
+#define IOADDR_ALTERA_TSEMAC_SMAC_3_1(base)    __IO_CALC_ADDRESS_NATIVE(base,0x31C)
+#define IORD_ALTERA_TSEMAC_SMAC_3_1(base)      IORD_32DIRECT(base, 0x31C)
+#define IOWR_ALTERA_TSEMAC_SMAC_3_1(base,data) IOWR_32DIRECT(base, 0x31C, data)
+
+
+
+
+/* Enumeration of commonly-used PHY registers */
+#define ALTERA_TSEMAC_PHY_ADDR_CONTROL    0x0
+#define ALTERA_TSEMAC_PHY_ADDR_STATUS     0x1
+#define ALTERA_TSEMAC_PHY_ADDR_PHY_ID1    0x2
+#define ALTERA_TSEMAC_PHY_ADDR_PHY_ID2    0x3
+#define ALTERA_TSEMAC_PHY_ADDR_PHY_ADV    0x4
+#define ALTERA_TSEMAC_PHY_ADDR_PHY_REMADV 0x5
+
+
+/* (Original) Register bit definitions and Ethernet MAC device structure */
+// COMMAND_CONFIG Register Bits
+enum
+{
+  mmac_cc_TX_ENA_bit        = 0,
+  mmac_cc_RX_ENA_bit        = 1,
+  mmac_cc_XON_GEN_bit       = 2,
+  mmac_cc_ETH_SPEED_bit     = 3,
+  mmac_cc_PROMIS_EN_bit     = 4,
+  mmac_cc_PAD_EN_bit        = 5,
+  mmac_cc_CRC_FWD_bit       = 6,  
+  mmac_cc_PAUSE_FWD_bit     = 7,
+  mmac_cc_PAUSE_IGNORE_bit  = 8,
+  mmac_cc_TX_ADDR__INS_bit  = 9,
+  mmac_cc_HD_ENA_bit        = 10,
+  mmac_cc_EXCESS_COL_bit    = 11,
+  mmac_cc_LATE_COL_bit      = 12,
+  mmac_cc_SW_RESET_bit      = 13,
+  mmac_cc_MHASH_SEL_bit     = 14,
+  mmac_cc_LOOPBACK_bit      = 15,
+  mmac_cc_TX_ADDR_SEL_bit   = 16,   // bits 18:16 = address select
+  mmac_cc_MAGIC_ENA_bit     = 19,
+  mmac_cc_SLEEP_ENA_bit     = 20,
+  mmac_cc_WAKEUP_bit        = 21,
+  mmac_cc_XOFF_GEN_bit      = 22,
+  mmac_cc_CNTL_FRM_ENA_bit  = 23,
+  mmac_cc_NO_LENGTH_CHECK_bit  = 24,
+  mmac_cc_ENA_10_bit        = 25,
+  mmac_cc_RX_ERR_DISC_bit   = 26,
+  mmac_cc_CNT_RESET_bit     = 31,
+  
+  mmac_cc_TX_ENA_mask           = (1 << 0), // enable TX
+  mmac_cc_RX_ENA_mask           = (1 << 1), // enable RX
+  mmac_cc_XON_GEN_mask          = (1 << 2), // generate Pause frame with Quanta
+  mmac_cc_ETH_SPEED_mask        = (1 << 3), // Select Gigabit
+  mmac_cc_PROMIS_EN_mask        = (1 << 4), // enable Promiscuous mode
+  mmac_cc_PAD_EN_mask           = (1 << 5), // enable padding remove on RX
+  mmac_cc_CRC_FWD_mask          = (1 << 6), // forward CRC to application on RX (as opposed to stripping it off)
+  mmac_cc_PAUSE_FWD_mask        = (1 << 7), // forward Pause frames to application
+  mmac_cc_PAUSE_IGNORE_mask     = (1 << 8), // ignore Pause frames
+  mmac_cc_TX_ADDR_INS_mask      = (1 << 9), // MAC overwrites bytes 6 to 12 of frame with address on all transmitted frames
+  mmac_cc_HD_ENA_mask           = (1 << 10),// enable half-duplex operation
+  mmac_cc_EXCESS_COL_mask       = (1 << 11),// indicator
+  mmac_cc_LATE_COL_mask         = (1 << 12),// indicator
+  mmac_cc_SW_RESET_mask         = (1 << 13),// issue register and counter reset
+  mmac_cc_MHASH_SEL_mask        = (1 << 14),// select multicast hash method
+  mmac_cc_LOOPBACK_mask         = (1 << 15),// enable GMII loopback
+  mmac_cc_TX_ADDR_SEL_mask      = (1 << 16),// bits 18:16 = address select
+  mmac_cc_MAGIC_ENA_mask        = (1 << 19),// enable magic packet detect
+  mmac_cc_SLEEP_ENA_mask        = (1 << 20),// enter sleep mode
+  mmac_cc_WAKEUP_mask           = (1 << 21),
+  mmac_cc_XOFF_GEN_mask         = (1 << 22),
+  mmac_cc_CNTL_FRM_ENA_mask     = (1 << 23),
+  mmac_cc_NO_LENGTH_CHECK_mask  = (1 << 24), // disable payload length check
+  mmac_cc_ENA_10_mask           = (1 << 25),
+  mmac_cc_RX_ERR_DISCARD_mask   = (1 << 26),
+  mmac_cc_CNT_RESET_mask        = (1 << 31)
+};
+
+// TX_CMD_STAT Register bits
+enum{
+  mmac_tcs_OMIT_CRC_mask          = (1 << 17),
+  mmac_tcs_TX_SHIFT16_mask        = (1 << 18)
+};
+
+
+// RX_CMD_STAT Register bits
+enum{
+  mmac_rcs_RX_SHIFT16_mask          = (1 << 25)
+};
+
+
+
+// TxConf Register Bits
+enum{
+  mnet_txc_TYPE_AUTO_mask    = (1 << 0),
+  mnet_txc_H2N_IP_mask       = (1 << 1),
+  mnet_txc_H2N_PROT_mask     = (1 << 2),
+  mnet_txc_IPCHK_mask        = (1 << 3),
+  mnet_txc_PROTCHK_mask      = (1 << 4)
+};
+
+// RxConf and RxStat register bits
+enum{
+  mnet_rxc_PADREMOVE_mask    = (1 << 0),
+  mnet_rxc_IPERR_DISC_mask   = (1 << 1),
+  mnet_rxc_PROTERR_DISC_mask = (1 << 2),
+  mnet_rxc_TYPE_REMOVE_mask  = (1 << 3),
+  mnet_rxc_N2H_IP_mask       = (1 << 4),
+  mnet_rxc_N2H_PROT_mask     = (1 << 5),
+  
+  mnet_rxs_HDRLEN_mask       = 0x1f,    // 0..4 = header length of IP+Protocol in 32-bit words
+  mnet_rxs_IP_CHKERR_mask    = (1 << 5),
+  mnet_rxs_PROT_CHKERR_mask  = (1 << 6),
+  mnet_rxs_T_REMOVED_mask    = (1 << 7),
+  mnet_rxs_VLAN_mask         = (1 << 8),
+  mnet_rxs_IPv6_mask         = (1 << 17),
+  mnet_rxs_FRAGMENT_mask     = (1 << 18)       // IPv4 fragment
+  
+};
+
+enum {
+        PCS_CTL_speed1           = 1<<6,        // speed select
+        PCS_CTL_speed0           = 1<<13,       
+        PCS_CTL_fullduplex       = 1<<8,        // fullduplex mode select
+        PCS_CTL_an_restart       = 1<<9,        // Autonegotiation restart command
+        PCS_CTL_isolate          = 1<<10,       // isolate command
+        PCS_CTL_powerdown        = 1<<11,       // powerdown command
+        PCS_CTL_an_enable        = 1<<12,       // Autonegotiation enable
+        PCS_CTL_rx_slpbk         = 1<<14,       // Serial Loopback enable
+        PCS_CTL_sw_reset         = 1<<15        // perform soft reset
+        
+};
+
+/** PCS Status Register Bits. IEEE 801.2 Clause 22.2.4.2
+ */
+enum {
+        PCS_ST_has_extcap   = 1<<0,             // PHY has extended capabilities registers       
+        PCS_ST_rx_sync      = 1<<2,             // RX is in sync (8B/10B codes o.k.)
+        PCS_ST_an_ability   = 1<<3,             // PHY supports autonegotiation
+        PCS_ST_rem_fault    = 1<<4,             // Autonegotiation completed
+        PCS_ST_an_done      = 1<<5
+        
+};
+
+/** Autonegotiation Capabilities Register Bits. IEEE 802.3 Clause 37.2.1 */
+
+enum {
+        ANCAP_NEXTPAGE  = 1 << 15,
+        ANCAP_ACK       = 1 << 14,
+        ANCAP_RF2       = 1 << 13,
+        ANCAP_RF1       = 1 << 12,
+        ANCAP_PS2       = 1 << 8,
+        ANCAP_PS1       = 1 << 7,
+        ANCAP_HD        = 1 << 6,
+        ANCAP_FD        = 1 << 5
+        // all others are reserved
+};     
+
+// MDIO registers within MAC register Space
+// memory mapped access
+typedef volatile struct np_tse_mdio_struct
+{  
+  unsigned int CONTROL;
+  unsigned int STATUS;
+  unsigned int PHY_ID1;
+  unsigned int PHY_ID2;
+  unsigned int ADV;
+  unsigned int REMADV;
+
+  unsigned int reg6;
+  unsigned int reg7;
+  unsigned int reg8;
+  unsigned int reg9;
+  unsigned int rega;
+  unsigned int regb;
+  unsigned int regc;
+  unsigned int regd;
+  unsigned int rege;
+  unsigned int regf;
+  unsigned int reg10;
+  unsigned int reg11;
+  unsigned int reg12;
+  unsigned int reg13;
+  unsigned int reg14;
+  unsigned int reg15;
+  unsigned int reg16;
+  unsigned int reg17;
+  unsigned int reg18;
+  unsigned int reg19;
+  unsigned int reg1a;
+  unsigned int reg1b;
+  unsigned int reg1c;
+  unsigned int reg1d;
+  unsigned int reg1e;
+  unsigned int reg1f;
+
+} np_tse_mdio;
+
+typedef volatile struct np_tse_mac_struct
+{
+  unsigned int REV;
+  unsigned int SCRATCH;
+  unsigned int COMMAND_CONFIG;
+  unsigned int MAC_0;
+  unsigned int MAC_1;
+  unsigned int FRM_LENGTH;
+  unsigned int PAUSE_QUANT;
+  unsigned int RX_SECTION_EMPTY;
+  unsigned int RX_SECTION_FULL;
+  unsigned int TX_SECTION_EMPTY;
+  unsigned int TX_SECTION_FULL;
+  unsigned int RX_ALMOST_EMPTY;
+  unsigned int RX_ALMOST_FULL;
+  unsigned int TX_ALMOST_EMPTY;
+  unsigned int TX_ALMOST_FULL;
+  unsigned int MDIO_ADDR0;
+  unsigned int MDIO_ADDR1;
+    
+  unsigned int reservedx44[5];
+  unsigned int REG_STAT;
+  unsigned int TX_IPG_LENGTH;
+    
+  unsigned int aMACID_1;
+  unsigned int aMACID_2;
+  unsigned int aFramesTransmittedOK;
+  unsigned int aFramesReceivedOK;
+  unsigned int aFramesCheckSequenceErrors; 
+  unsigned int aAlignmentErrors;
+  unsigned int aOctetsTransmittedOK;
+  unsigned int aOctetsReceivedOK;
+  unsigned int aTxPAUSEMACCtrlFrames;
+  unsigned int aRxPAUSEMACCtrlFrames;
+  unsigned int ifInErrors;
+  unsigned int ifOutErrors;
+  unsigned int ifInUcastPkts;
+  unsigned int ifInMulticastPkts;
+  unsigned int ifInBroadcastPkts;
+  unsigned int ifOutDiscards;
+  unsigned int ifOutUcastPkts;
+  unsigned int ifOutMulticastPkts;
+  unsigned int ifOutBroadcastPkts;
+  unsigned int etherStatsDropEvent;
+  unsigned int etherStatsOctets;
+  unsigned int etherStatsPkts;
+  unsigned int etherStatsUndersizePkts;
+  unsigned int etherStatsOversizePkts;
+  unsigned int etherStatsPkts64Octets;
+  unsigned int etherStatsPkts65to127Octets;
+  unsigned int etherStatsPkts128to255Octets;
+  unsigned int etherStatsPkts256to511Octets;
+  unsigned int etherStatsPkts512to1023Octets;
+  unsigned int etherStatsPkts1024to1518Octets;
+  unsigned int etherStatsPkts1519toXOctets;
+  unsigned int etherStatsJabbers;
+  unsigned int etherStatsFragments;
+  
+  unsigned int reservedxE4;
+  unsigned int TX_CMD_STAT;
+  unsigned int RX_CMD_STAT;
+  
+  unsigned int msb_aOctetsTransmittedOK;
+  unsigned int msb_aOctetsReceivedOK;
+  unsigned int msb_etherStatsOctets;
+  unsigned int reservedxFC;  // current frame's IP payload sum result
+  
+  unsigned int hashtable[64];
+  
+  np_tse_mdio mdio0;
+  np_tse_mdio mdio1;
+  
+  unsigned int smac0_0;
+  unsigned int smac0_1;
+  unsigned int smac1_0;
+  unsigned int smac1_1;
+  unsigned int smac2_0;
+  unsigned int smac2_1;
+  unsigned int smac3_0;
+  unsigned int smac3_1;
+  
+  unsigned int reservedx320[56];
+
+} np_tse_mac;
+
+#endif /* __ALTERA_ETH_TSE_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h
new file mode 100644
index 0000000..387e138
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller.h
@@ -0,0 +1,126 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_QSPI_CONTROLLER_H__
+#define __ALT_QSPI_CONTROLLER_H__
+
+#include "alt_types.h"
+#include "sys/alt_flash_dev.h"
+#include "sys/alt_llist.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/**
+ *  Description of the QSPI controller
+ */
+typedef struct alt_qspi_controller_dev
+{
+    alt_flash_dev dev;
+
+    alt_u32 data_base; /** base address of data slave */
+    alt_u32 data_end; /** end address of data slave (not inclusive) */
+    alt_u32 csr_base; /** base address of CSR slave */
+    alt_u32 size_in_bytes; /** size of memory in bytes */
+    alt_u32 is_epcs; /** 1 if device is an EPCS device */
+    alt_u32 number_of_sectors; /** number of flash sectors */
+    alt_u32 sector_size; /** size of each flash sector */
+    alt_u32 page_size; /** page size */
+    alt_u32 silicon_id; /** ID of silicon used with EPCQ/QSPI IP */
+} alt_qspi_controller_dev;
+
+/**
+*   Macros used by alt_sys_init.c to create data storage for driver instance
+*/
+#define ALTERA_GENERIC_QUAD_SPI_CONTROLLER_AVL_MEM_AVL_CSR_INSTANCE(qspi_name, avl_mem, avl_csr, qspi_dev) \
+static alt_qspi_controller_dev qspi_dev =                                                       \
+{                                                                                               \
+  .dev = {                                                                                      \
+            .llist = ALT_LLIST_ENTRY,                                                           \
+            .name = avl_mem##_NAME,                                                             \
+            .write = alt_qspi_controller_write,                                                 \
+            .read = alt_qspi_controller_read,                                                   \
+            .get_info = alt_qspi_controller_get_info,                                           \
+            .erase_block = alt_qspi_controller_erase_block,                                     \
+            .write_block = alt_qspi_controller_write_block,                                     \
+            .base_addr = ((void*)(avl_mem##_BASE)),                                             \
+            .length = ((int)(avl_mem##_SPAN)),                                                  \
+            .lock = alt_qspi_controller_lock ,                                                  \
+         },                                                                                     \
+  .data_base = ((alt_u32)(avl_mem##_BASE)),   							\
+  .data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)),	                        \
+  .csr_base = ((alt_u32)(avl_csr##_BASE)),   							\
+  .size_in_bytes = ((alt_u32)(avl_mem##_SPAN)),         				        \
+  .is_epcs = ((alt_u32)(avl_mem##_IS_EPCS)),							\
+  .number_of_sectors = ((alt_u32)(avl_mem##_NUMBER_OF_SECTORS)),			        \
+  .sector_size = ((alt_u32)(avl_mem##_SECTOR_SIZE)),						\
+  .page_size = ((alt_u32)(avl_mem##_PAGE_SIZE))	,						\
+}
+
+/*
+    Public API
+
+    Refer to Using Flash Devices in the
+    Developing Programs Using the Hardware Abstraction Layer chapter
+    of the Nios II Software Developer's Handbook.
+
+*/
+int alt_qspi_controller_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
+
+int alt_qspi_controller_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
+
+int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset);
+
+int alt_qspi_controller_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
+
+int alt_qspi_controller_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
+
+int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
+
+
+/*
+ * Initialization function
+ */
+extern alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *dev);
+
+/*
+ * alt_sys_init.c will call this macro automatically initialize the driver instance
+ */
+#define ALTERA_GENERIC_QUAD_SPI_CONTROLLER_INIT(name, dev) 	\
+		altera_qspi_controller_init(&dev);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_QSPI_CONTROLLER_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h
new file mode 100644
index 0000000..722cdc1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_generic_quad_spi_controller_regs.h
@@ -0,0 +1,260 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_QSPI_CONTROLLER_REGS_H__
+#define __ALTERA_QSPI_CONTROLLER_REGS_H__
+
+#include <io.h>
+
+/*
+ * QSPI_RD_STATUS register offset
+ *
+ * The QSPI_RD_STATUS register contains information from the read status 
+ * register operation. A full description of the register can be found in the 
+ * data sheet,
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_STATUS_REG                       (0x0)
+
+/*
+ * QSPI_RD_STATUS register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_STATUS(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_STATUS_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_STATUS(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_STATUS_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_STATUS(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_STATUS_REG, data)
+
+/*
+ * QSPI_RD_STATUS register description macros
+ */
+
+/** Write in progress bit */
+#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK                  (0x00000001)
+#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_AVAILABLE             (0x00000000)
+#define ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY                  (0x00000001)
+/** When to time out a poll of the write in progress bit */
+/* 0.7 sec time out */
+#define ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE    		    700000 
+
+/*
+ * QSPI_RD_SID register offset
+ *
+ * The QSPI_RD_SID register contains the information from the read silicon ID 
+ * operation and can be used to determine what type of EPCS device we have.
+ * Only support in EPCS16 and EPCS64.
+ *
+ * This register is valid only if the device is an EPCS.
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_SID_REG                          (0x4)
+
+/*
+ * QSPI_RD_SID register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_SID(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_SID_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_SID(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_SID_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_SID(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_SID_REG, data)
+
+/*
+ * QSPI_RD_SID register description macros
+ * 
+ * Specific device values obtained from Table 14 of: 
+ * "Serial Configuration (EPCS) Devices Datasheet"
+ */
+#define ALTERA_QSPI_CONTROLLER_SID_MASK                         (0x000000FF)
+#define ALTERA_QSPI_CONTROLLER_SID_EPCS16                       (0x00000014)
+#define ALTERA_QSPI_CONTROLLER_SID_EPCS64                       (0x00000016)
+#define ALTERA_QSPI_CONTROLLER_SID_EPCS128                      (0x00000018)
+
+/*
+ * QSPI_RD_RDID register offset
+ *
+ * The QSPI_RD_RDID register contains the information from the read memory 
+ * capacity operation and can be used to determine what type of EPCQ/QSPI device 
+ * we have.
+ *
+ * This register is only valid if the device is an EPCQ/QSPI.
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_RDID_REG                         (0x8)
+
+/*
+ * QSPI_RD_RDID register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_RDID(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_RDID_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_RDID(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_RDID_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_RDID(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_RDID_REG, data)
+
+/*
+ * QSPI_RD_RDID register description macros
+ * 
+ * Specific device values obtained from Table 28 of: 
+ *  "Quad-Serial Configuration (EPCQ/QSPI? (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
+ *  Devices Datasheet"
+ */
+#define ALTERA_QSPI_CONTROLLER_RDID_MASK                         (0x000000FF)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI16                       (0x00000015)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI32                       (0x00000016)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI64                       (0x00000017)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI128                      (0x00000018)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI256                      (0x00000019)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI512                      (0x00000020)
+#define ALTERA_QSPI_CONTROLLER_RDID_QSPI1024                     (0x00000021)
+
+/*
+ * QSPI_MEM_OP register offset
+ *
+ * The QSPI_MEM_OP register is used to do memory protect and erase operations
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_REG                       (0xC)
+
+/*
+ * QSPI_MEM_OP register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_MEM_OP(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_MEM_OP(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_MEM_OP_REG, data)
+
+/*
+ * QSPI_MEM_OP register description macros
+ */
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_CMD_MASK                  (0x00000003)
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_BULK_ERASE_CMD            (0x00000001)
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
+
+/** see datasheet for sector values */
+#define ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
+
+/*
+ * QSPI_ISR register offset
+ *
+ * The QSPI_ISR register is used to determine whether an invalid write or erase 
+ * operation triggered an interrupt
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_ISR_REG                          (0x10)
+
+/*
+ * QSPI_ISR register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_ISR(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_ISR_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_ISR(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_ISR_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_ISR(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_ISR_REG, data)
+
+/*
+ * QSPI_ISR register description macros
+ */
+#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
+#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
+
+#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
+#define ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
+
+
+/*
+ * QSPI_IMR register offset
+ *
+ * The QSPI_IMR register is used to mask the invalid erase or the invalid write 
+ * interrupts.
+ *
+ */
+#define ALTERA_QSPI_CONTROLLER_IMR_REG                          (0x14)
+
+/*
+ * QSPI_IMR register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CONTROLLER_IMR(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CONTROLLER_IMR_REG)
+
+#define IORD_ALTERA_QSPI_CONTROLLER_IMR(base) \
+    IORD_32DIRECT(base, ALTERA_QSPI_CONTROLLER_IMR_REG)
+
+#define IOWR_ALTERA_QSPI_CONTROLLER_IMR(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CONTROLLER_IMR_REG, data)
+
+/*
+ * QSPI_IMR register description macros
+ */
+#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
+#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
+
+#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
+#define ALTERA_QSPI_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
+
+/*
+ * QSPI_CHIP_SELECT register offset
+ *
+ * The QSPI_CHIP_SELECT register is used to issue chip select 
+ */
+#define ALTERA_QSPI_CHIP_SELECT_REG                          (0x18)
+
+/*
+ * QSPI_CHIP_SELECT register access macros
+ */
+#define IOADDR_ALTERA_QSPI_CHIP_SELECT(base) \
+    __IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_QSPI_CHIP_SELECT_REG)
+
+#define IOWR_ALTERA_QSPI_CHIP_SELECT(base, data) \
+    IOWR_32DIRECT(base, ALTERA_QSPI_CHIP_SELECT_REG, data)
+
+/*
+ * QSPI_CHIP_SELECT register description macros
+ */
+#define ALTERA_QSPI_CHIP1_SELECT        (0x00000001)
+#define ALTERA_QSPI_CHIP2_SELECT        (0x00000002)
+#define ALTERA_QSPI_CHIP3_SELECT        (0x00000003)
+
+#endif /* __ALTERA_QSPI_CONTROLLER_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h
new file mode 100644
index 0000000..0ab231f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma.h
@@ -0,0 +1,512 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_MSGDMA_H__
+#define __ALTERA_MSGDMA_H__
+
+#include <stddef.h>
+#include <errno.h>
+
+#include "sys/alt_dev.h"
+#include "alt_types.h"
+#include "altera_msgdma_csr_regs.h"
+#include "altera_msgdma_descriptor_regs.h"
+#include "altera_msgdma_response_regs.h"
+#include "altera_msgdma_prefetcher_regs.h"
+#include "os/alt_sem.h"
+#include "os/alt_flag.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * Helper struct to have easy access to hi/low values from a 64 bit value.
+ * Useful when having to write prefetcher/descriptor 64 bit addresses.  
+ */
+typedef union {
+  alt_u64 u64;
+  alt_u32 u32[2];
+} msgdma_addr64;
+
+/*
+ * To ensure that a descriptor is created without spaces between the structure
+ * members, we call upon GCC's ability to pack to a byte-aligned boundary.  
+ * Additionally, msgdma requires the descriptors to be aligned to a 16 byte
+ * boundary.  
+ */
+#define alt_msgdma_standard_descriptor_packed \
+    __attribute__ ((packed, aligned(16)))
+#define alt_msgdma_extended_descriptor_packed \
+    __attribute__ ((packed, aligned(32)))
+#define alt_msgdma_prefetcher_standard_descriptor_packed \
+    __attribute__ ((packed, aligned(32)))
+#define alt_msgdma_prefetcher_extended_descriptor_packed \
+    __attribute__ ((packed, aligned(64)))
+#define alt_msgdma_response_packed __attribute__ ((packed, aligned(4)))
+
+/*
+ * The function alt_find_dev() is used to search the device list "list" to
+ * locate a device named "name". If a match is found, then a pointer to the
+ * device is returned, otherwise NULL is returned.
+ */
+extern alt_dev* alt_find_dev (const char* name, alt_llist* list);
+
+/* Callback routine type definition */
+typedef void (*alt_msgdma_callback)(void *context);
+
+/* use this structure if you haven't enabled the enhanced features */
+typedef struct {
+  alt_u32 *read_address;
+  alt_u32 *write_address;
+  alt_u32 transfer_length;
+  alt_u32 control;
+} alt_msgdma_standard_descriptor_packed alt_msgdma_standard_descriptor;
+
+/* use this structure if you have enabled the enhanced features (only the 
+ * elements enabled in hardware will be used) 
+ */
+typedef struct {
+  alt_u32 *read_address_low;
+  alt_u32 *write_address_low;
+  alt_u32 transfer_length;
+  alt_u16 sequence_number;
+  alt_u8  read_burst_count;
+  alt_u8  write_burst_count;
+  alt_u16 read_stride;
+  alt_u16 write_stride;
+  alt_u32 *read_address_high;
+  alt_u32 *write_address_high;
+  alt_u32 control;
+} alt_msgdma_extended_descriptor_packed alt_msgdma_extended_descriptor;
+
+
+/* Prefetcher Descriptors need to be different than standard dispatcher 
+ * descriptors use this structure if you haven't enabled the enhanced 
+ * features 
+ */
+typedef struct {
+  alt_u32 read_address;
+  alt_u32 write_address;
+  alt_u32 transfer_length;
+  alt_u32 next_desc_ptr;
+  alt_u32 bytes_transfered;
+  alt_u16 status;
+  alt_u16 _pad1_rsvd;
+  alt_u32 _pad2_rsvd;
+  alt_u32 control;
+} alt_msgdma_prefetcher_standard_descriptor_packed alt_msgdma_prefetcher_standard_descriptor;
+
+/* use this structure if you have enabled the enhanced features (only the elements 
+enabled in hardware will be used) */
+typedef struct {
+  alt_u32  read_address_low;
+  alt_u32  write_address_low;
+  alt_u32 transfer_length;
+  alt_u32  next_desc_ptr_low;
+  alt_u32 bytes_transfered;
+  alt_u16 status;
+  alt_u16 _pad1_rsvd;
+  alt_u32 _pad2_rsvd;
+  alt_u16 sequence_number;
+  alt_u8  read_burst_count;
+  alt_u8  write_burst_count;
+  alt_u16 read_stride;
+  alt_u16 write_stride;
+  alt_u32  read_address_high;
+  alt_u32  write_address_high;
+  alt_u32  next_desc_ptr_high;
+  alt_u32 _pad3_rsvd[3];
+  alt_u32 control;
+} alt_msgdma_prefetcher_extended_descriptor_packed alt_msgdma_prefetcher_extended_descriptor;
+
+
+/* msgdma device structure */
+typedef struct alt_msgdma_dev
+{
+    /* Device linked-list entry */
+    alt_llist                            llist;
+    /* Name of msgdma in Qsys system */
+    const char                           *name;
+    /* Base address of control and status register */
+    alt_u32                              *csr_base;
+    /* Base address of the descriptor slave port */
+    alt_u32                              *descriptor_base;
+    /* Base address of the response register */
+    alt_u32                              *response_base;
+    /* Base address of the prefetcher register */
+    alt_u32                              *prefetcher_base;
+    /* device IRQ controller ID */
+    alt_u32                                 irq_controller_ID;
+    /* device IRQ ID */
+    alt_u32                                 irq_ID;
+    /* FIFO size to store descriptor count,
+    { 8, 16, 32, 64,default:128, 256, 512, 1024 } */
+    alt_u32                              descriptor_fifo_depth;
+    /* FIFO size to store response count */
+    alt_u32                              response_fifo_depth;
+    /* Callback routine pointer */
+    alt_msgdma_callback                  callback;
+    /* Callback context pointer */
+    void                                 *callback_context;
+    /* user define control setting during interrupt registering*/
+    alt_u32                              control;
+    /* Enable burst transfer */
+    alt_u8                burst_enable;
+    /* Enable burst wrapping */
+    alt_u8                burst_wrapping_support;
+        /* Depth of the internal data path FIFO*/
+    alt_u32                data_fifo_depth;
+    /* Data path Width. This parameter affect both read
+           master and write master data width */
+    alt_u32                    data_width;
+    /* Maximum burst count*/
+    alt_u32                             max_burst_count;
+    /* Maximum transfer length*/
+    alt_u32                             max_byte;
+    /* Maximum stride count */
+    alt_u64                max_stride;
+    /* Enable dynamic burst programming*/
+    alt_u8                 programmable_burst_enable;
+    /* Enable stride addressing */
+    alt_u8                stride_enable;
+    /* Supported transaction type */
+    const char                          *transfer_type;    
+       /* Extended feature support enable "1"-enable  "0"-disable */ 
+    alt_u8                enhanced_features;
+      /* Enable response port "0"-memory-mapped, "1"-streaming, "2"-disable */    
+    alt_u8                response_port;
+    /* Prefetcher enabled "0"-disabled, "1"-enabled*/
+    alt_u8                prefetcher_enable;
+    /* Semaphore used to control access registers
+    in multi-threaded mode */
+    ALT_SEM                              (regs_lock)
+} __attribute__ ((aligned(0x10))) alt_msgdma_dev;
+
+
+
+/*******************************************************************************
+ *  Public API
+ ******************************************************************************/
+alt_msgdma_dev* alt_msgdma_open (const char* name);
+ 
+void alt_msgdma_register_callback(
+    alt_msgdma_dev *dev,
+    alt_msgdma_callback callback,
+    alt_u32 control,
+    void *context); 
+  
+int alt_msgdma_standard_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc);
+
+int alt_msgdma_extended_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc);
+
+int alt_msgdma_construct_standard_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address,
+    alt_u32 *write_address,
+    alt_u32 length,
+    alt_u32 control);
+
+int alt_msgdma_construct_standard_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control);
+    
+int alt_msgdma_construct_standard_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor, 
+    alt_u32 *read_address, 
+    alt_u32 length, 
+    alt_u32 control);
+
+int alt_msgdma_construct_extended_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number,
+    alt_u8 write_burst_count,
+    alt_u16 write_stride);
+
+int alt_msgdma_construct_extended_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor, 
+    alt_u32 *read_address, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride);
+
+int alt_msgdma_construct_extended_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor, 
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count,
+    alt_u8 write_burst_count, 
+    alt_u16 read_stride, 
+    alt_u16 write_stride);
+
+int alt_msgdma_standard_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc);
+
+int alt_msgdma_extended_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc);
+
+int alt_msgdma_standard_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc);
+
+/***************** MSGDMA PREFETCHER PUBLIC APIs ******************/
+int alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor,
+    alt_u32 read_address,
+    alt_u32 write_address,
+    alt_u32 length,
+    alt_u32 control);
+
+int alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 write_address, 
+    alt_u32 length, 
+    alt_u32 control);
+    
+int alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 read_address, 
+    alt_u32 length, 
+    alt_u32 control);
+
+int alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 write_address_high,
+    alt_u32 write_address_low, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number,
+    alt_u8 write_burst_count,
+    alt_u16 write_stride);
+
+int alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 read_address_high,
+    alt_u32 read_address_low, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride);
+
+int alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 read_address_high,
+    alt_u32 read_address_low,
+    alt_u32 write_address_high,
+    alt_u32 write_address_low, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count,
+    alt_u8 write_burst_count, 
+    alt_u16 read_stride, 
+    alt_u16 write_stride);
+
+int alt_msgdma_prefetcher_add_standard_desc_to_list (
+    alt_msgdma_prefetcher_standard_descriptor** list,
+    alt_msgdma_prefetcher_standard_descriptor* descriptor);
+
+int alt_msgdma_prefetcher_add_extended_desc_to_list (
+    alt_msgdma_prefetcher_extended_descriptor** list,
+    alt_msgdma_prefetcher_extended_descriptor* descriptor);
+
+int alt_msgdma_start_prefetcher_with_std_desc_list (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list);
+
+int alt_msgdma_start_prefetcher_with_extd_desc_list (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list);
+
+int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list);
+    
+int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list);   
+    
+void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq);
+
+/* HAL initialization macros */
+
+/*Depth of internal data path FIFO.STRIDE_ENABLE
+ * ALTERA_MSGDMA_INSTANCE is the macro used by alt_sys_init() to
+ * allocate any per device memory that may be required.
+ */
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_RESPONSE_INSTANCE(name, csr_if, desc_if, resp_if, dev) \
+static alt_msgdma_dev dev =                                                                       \
+{                                                                                                 \
+  ALT_LLIST_ENTRY,                                                                                \
+  name##_CSR_NAME,                                                                                \
+  ((alt_u32 *)(csr_if##_BASE)),                                                                   \
+  ((alt_u32 *)(desc_if##_BASE)),                                                                  \
+  ((alt_u32 *)(resp_if##_BASE)),                                                                  \
+  ((alt_u32 *)(0)),                                                                               \
+  ((alt_u32  )name##_CSR_IRQ_INTERRUPT_CONTROLLER_ID),                                            \
+  ((alt_u32  )name##_CSR_IRQ),                                                                    \
+  ((alt_u32  )desc_if##_DESCRIPTOR_FIFO_DEPTH),                                                   \
+  ((alt_u32  )resp_if##_DESCRIPTOR_FIFO_DEPTH * 2),                                               \
+  ((void *) 0x0),                                                                                 \
+  ((void *) 0x0),                                                                                 \
+  ((alt_u32) 0x0),                                                                                \
+  ((alt_u8) csr_if##_BURST_ENABLE),                                                               \
+  ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT),                                                     \
+  ((alt_u32) csr_if##_DATA_FIFO_DEPTH),                                                           \
+  ((alt_u32) csr_if##_DATA_WIDTH),                                                                \
+  ((alt_u32) csr_if##_MAX_BURST_COUNT),                                                           \
+  ((alt_u32) csr_if##_MAX_BYTE),                                                                  \
+  ((alt_u64) csr_if##_MAX_STRIDE),                                                                \
+  ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE),                                                  \
+  ((alt_u8) csr_if##_STRIDE_ENABLE),                                                              \
+  csr_if##_TRANSFER_TYPE,                                                                         \
+  ((alt_u8) csr_if##_ENHANCED_FEATURES),                                                          \
+  ((alt_u8) csr_if##_RESPONSE_PORT),                                                              \
+  ((alt_u8) csr_if##_PREFETCHER_ENABLE)                                                           \
+}; 
+
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_INSTANCE(name, csr_if, desc_if, dev) \
+static alt_msgdma_dev dev =                                                     \
+{                                                                               \
+  ALT_LLIST_ENTRY,                                                              \
+  name##_CSR_NAME,                                                              \
+  ((alt_u32 *)(csr_if##_BASE)),                                                 \
+  ((alt_u32 *)(desc_if##_BASE)),                                                \
+  ((alt_u32 *)(0)),                                                             \
+  ((alt_u32 *)(0)),                                                             \
+  ((alt_u32  )name##_CSR_IRQ_INTERRUPT_CONTROLLER_ID),                          \
+  ((alt_u32  )name##_CSR_IRQ),                                                  \
+  ((alt_u32  )desc_if##_DESCRIPTOR_FIFO_DEPTH),                                 \
+  ((alt_u32) 0x0),                                                              \
+  ((void *) 0x0),                                                               \
+  ((void *) 0x0),                                                               \
+  ((alt_u32) 0x0),                                                              \
+  ((alt_u8) csr_if##_BURST_ENABLE),                                             \
+  ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT),                                   \
+  ((alt_u32) csr_if##_DATA_FIFO_DEPTH),                                         \
+  ((alt_u32) csr_if##_DATA_WIDTH),                                              \
+  ((alt_u32) csr_if##_MAX_BURST_COUNT),                                         \
+  ((alt_u32) csr_if##_MAX_BYTE),                                                \
+  ((alt_u64) csr_if##_MAX_STRIDE),                                              \
+  ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE),                                \
+  ((alt_u8) csr_if##_STRIDE_ENABLE),                                            \
+  csr_if##_TRANSFER_TYPE,                                                       \
+  ((alt_u8) csr_if##_ENHANCED_FEATURES),                                        \
+  ((alt_u8) csr_if##_RESPONSE_PORT),                                            \
+  ((alt_u8) csr_if##_PREFETCHER_ENABLE)                                         \
+}; 
+
+/*
+ * New Interface for Prefetcher 15/6/2015.
+ */
+#define ALTERA_MSGDMA_CSR_PREFETCHER_CSR_INSTANCE(name, csr_if, pref_if, dev)   \
+static alt_msgdma_dev dev =                                                     \
+{                                                                               \
+  ALT_LLIST_ENTRY,                                                              \
+  name##_CSR_NAME,                                                              \
+  ((alt_u32 *)(csr_if##_BASE)),                                                 \
+  ((alt_u32 *)(0)),                                                             \
+  ((alt_u32 *)(0)),                                                             \
+  ((alt_u32 *)(pref_if##_BASE)),                                                \
+  ((alt_u32  )name##_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID),               \
+  ((alt_u32  )name##_PREFETCHER_CSR_IRQ),                                       \
+  ((alt_u32  )(0)),                                                             \
+  ((alt_u32) 0x0),                                                              \
+  ((void *) 0x0),                                                               \
+  ((void *) 0x0),                                                               \
+  ((alt_u32) 0x0),                                                              \
+  ((alt_u8) csr_if##_BURST_ENABLE),                                             \
+  ((alt_u8) csr_if##_BURST_WRAPPING_SUPPORT),                                   \
+  ((alt_u32) csr_if##_DATA_FIFO_DEPTH),                                         \
+  ((alt_u32) csr_if##_DATA_WIDTH),                                              \
+  ((alt_u32) csr_if##_MAX_BURST_COUNT),                                         \
+  ((alt_u32) csr_if##_MAX_BYTE),                                                \
+  ((alt_u64) csr_if##_MAX_STRIDE),                                              \
+  ((alt_u8) csr_if##_PROGRAMMABLE_BURST_ENABLE),                                \
+  ((alt_u8) csr_if##_STRIDE_ENABLE),                                            \
+  csr_if##_TRANSFER_TYPE,                                                       \
+  ((alt_u8) csr_if##_ENHANCED_FEATURES),                                        \
+  ((alt_u8) csr_if##_RESPONSE_PORT),                                            \
+  ((alt_u8) csr_if##_PREFETCHER_ENABLE)                                         \
+}; 
+
+
+/*
+ * The macro ALTERA_MSGDMA_INIT is called by the auto-generated function
+ * alt_sys_init() to initialize a given device instance.
+ */
+#define ALTERA_MSGDMA_INIT(name, dev)                                              \
+    alt_msgdma_init(&dev, dev.irq_controller_ID, dev.irq_ID);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALTERA_MSGDMA_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h
new file mode 100644
index 0000000..bd30d8b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_csr_regs.h
@@ -0,0 +1,175 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#ifndef ALTERA_MSGDMA_CSR_REGS_H_
+#define ALTERA_MSGDMA_CSR_REGS_H_
+
+#include "io.h"
+/*
+  Enhanced features off:
+
+  Bytes     Access Type     Description
+  -----     -----------     -----------
+  0-3       R/Clr           Status(1)
+  4-7       R/W             Control(2)
+  8-12      R               Descriptor Fill Level(write fill level[15:0], read 
+                            fill level[15:0])
+  13-15     R               Response Fill Level[15:0]
+  16-31     N/A             <Reserved>
+
+
+  Enhanced features on:
+
+  Bytes     Access Type     Description
+  -----     -----------     -----------
+  0-3       R/Clr           Status(1)
+  4-7       R/W             Control(2)
+  8-12      R               Descriptor Fill Level (write fill level[15:0], read 
+                            fill level[15:0])
+  13-15     R               Response Fill Level[15:0]
+  16-20     R               Sequence Number (write sequence number[15:0], read 
+                            sequence number[15:0])
+  21-31     N/A             <Reserved>
+
+  (1)  Writing a '1' to the interrupt bit of the status register clears the 
+       interrupt bit (when applicable), all other bits are unaffected by writes.
+  (2)  Writing to the software reset bit will clear the entire register 
+       (as well as all the registers for the entire msgdma).
+
+  Status Register:
+
+  Bits      Description
+  ----      -----------
+  0         Busy
+  1         Descriptor Buffer Empty
+  2         Descriptor Buffer Full
+  3         Response Buffer Empty
+  4         Response Buffer Full
+  5         Stop State
+  6         Reset State
+  7         Stopped on Error
+  8         Stopped on Early Termination
+  9         IRQ
+  10-31     <Reserved>
+
+  Control Register:
+
+  Bits      Description
+  ----      -----------
+  0         Stop (will also be set if a stop on error/early termination 
+            condition occurs)
+  1         Software Reset
+  2         Stop on Error
+  3         Stop on Early Termination
+  4         Global Interrupt Enable Mask
+  5         Stop dispatcher (stops the dispatcher from issuing more read/write 
+            commands)
+  6-31      <Reserved>
+*/
+
+
+
+#define ALTERA_MSGDMA_CSR_STATUS_REG                          0x0
+#define ALTERA_MSGDMA_CSR_CONTROL_REG                         0x4
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG           0x8
+#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG             0xC
+/* this register only exists when the enhanced features are enabled */
+#define ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG                 0x10
+
+
+/* masks for the status register bits */
+#define ALTERA_MSGDMA_CSR_BUSY_MASK                           1
+#define ALTERA_MSGDMA_CSR_BUSY_OFFSET                         0
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_MASK        (1 << 1)
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_EMPTY_OFFSET      1
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK         (1 << 2)
+#define ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_OFFSET       2
+#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_MASK          (1 << 3)
+#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_EMPTY_OFFSET        3
+#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_MASK           (1 << 4)
+#define ALTERA_MSGDMA_CSR_RESPONSE_BUFFER_FULL_OFFSET         4
+#define ALTERA_MSGDMA_CSR_STOP_STATE_MASK                     (1 << 5)
+#define ALTERA_MSGDMA_CSR_STOP_STATE_OFFSET                   5
+#define ALTERA_MSGDMA_CSR_RESET_STATE_MASK                    (1 << 6)
+#define ALTERA_MSGDMA_CSR_RESET_STATE_OFFSET                  6
+#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK               (1 << 7)
+#define ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_OFFSET             7
+#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK   (1 << 8)
+#define ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_OFFSET 8
+#define ALTERA_MSGDMA_CSR_IRQ_SET_MASK                        (1 << 9)
+#define ALTERA_MSGDMA_CSR_IRQ_SET_OFFSET                      9
+
+/* masks for the control register bits */
+#define ALTERA_MSGDMA_CSR_STOP_MASK                           1
+#define ALTERA_MSGDMA_CSR_STOP_OFFSET                         0
+#define ALTERA_MSGDMA_CSR_RESET_MASK                          (1 << 1)
+#define ALTERA_MSGDMA_CSR_RESET_OFFSET                        1
+#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK                  (1 << 2)
+#define ALTERA_MSGDMA_CSR_STOP_ON_ERROR_OFFSET                2
+#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_MASK      (1 << 3)
+#define ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_OFFSET    3
+#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK               (1 << 4)
+#define ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_OFFSET             4
+#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK               (1 << 5)
+#define ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_OFFSET             5
+
+/* masks for the FIFO fill levels and sequence number */
+#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK                0xFFFF
+#define ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET              0
+#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK               0xFFFF0000
+#define ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET             16
+#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_MASK            0xFFFF
+#define ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_OFFSET          0
+#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_MASK           0xFFFF
+#define ALTERA_MSGDMA_CSR_READ_SEQUENCE_NUMBER_OFFSET         0
+#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_MASK          0xFFFF0000
+#define ALTERA_MSGDMA_CSR_WRITE_SEQUENCE_NUMBER_OFFSET        16
+
+
+/* read/write macros for each 32 bit register of the CSR port */
+#define IOWR_ALTERA_MSGDMA_CSR_STATUS(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG, data)
+#define IOWR_ALTERA_MSGDMA_CSR_CONTROL(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG, data)
+#define IORD_ALTERA_MSGDMA_CSR_STATUS(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_STATUS_REG)
+#define IORD_ALTERA_MSGDMA_CSR_CONTROL(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_CONTROL_REG)
+#define IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL_REG)
+#define IORD_ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_RESPONSE_FILL_LEVEL_REG)
+#define IORD_ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_CSR_SEQUENCE_NUMBER_REG)
+
+
+
+#endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_CSR_REGS_H_*/
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h
new file mode 100644
index 0000000..21b1c31
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_descriptor_regs.h
@@ -0,0 +1,163 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#ifndef ALTERA_MSGDMA_DESCRIPTOR_REGS_H_
+#define ALTERA_MSGDMA_DESCRIPTOR_REGS_H_
+
+#include "io.h"
+
+/*
+  Descriptor formats:
+
+  Standard Format:
+  
+  Offset         |    3                 2                 1                   0
+  ------------------------------------------------------------------------------
+   0x0           |                      Read Address[31..0]
+   0x4           |                      Write Address[31..0]
+   0x8           |                      Length[31..0]
+   0xC           |                      Control[31..0]
+
+  Extended Format:
+  
+Offset|   3                  2                  1                  0
+ ------------------------------------------------------------------------------
+ 0x0  |                      Read Address[31..0]
+ 0x4  |                      Write Address[31..0]
+ 0x8  |                      Length[31..0]
+ 0xC  |Write Burst Count[7..0] | Read Burst Count[7..0] | Sequence Number[15..0]
+ 0x10 | Write Stride[15..0]           |            Read Stride[15..0]
+ 0x14 |                      Read Address[63..32]
+ 0x18 |                      Write Address[63..32]
+ 0x1C |                      Control[31..0]
+
+  Note:  The control register moves from offset 0xC to 0x1C depending on the 
+         format used
+
+*/
+
+
+
+
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG                      0x0
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG                     0x4
+#define ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG                            0x8
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG                  0xC
+#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG                   0xC
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG                        0xE
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG                       0xF
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG                       0x10
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG                      0x12
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG                 0x14
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG                0x18
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG                  0x1C
+
+
+/* masks and offsets for the sequence number and programmable burst counts */
+#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_MASK                  0xFFFF
+#define ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_OFFSET                0
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_MASK                 0x00FF0000
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_COUNT_OFFSET               16
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_MASK                0xFF000000
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_COUNT_OFFSET              24
+
+
+/* masks and offsets for the read and write strides */
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_MASK                      0xFFFF
+#define ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_OFFSET                    0
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_MASK                     0xFFFF0000
+#define ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_OFFSET                   16
+
+
+/* masks and offsets for the bits in the descriptor control field */
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_MASK         0xFF
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSMIT_CHANNEL_OFFSET       0
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK             (1 << 8)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_OFFSET           8
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK             (1 << 9)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_OFFSET           9
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_MASK               (1 << 10)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_READS_OFFSET             10
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_MASK              (1 << 11)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_PARK_WRITES_OFFSET            11
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK               (1 << 12)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_OFFSET             12
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK    (1 << 14)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_OFFSET  14
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_MASK    (1 << 15)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_OFFSET  15
+/* the read master will use this as the transmit error, the dispatcher will use 
+this to generate an interrupt if any of the error bits are asserted by the 
+write master */
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK                (0xFF << 16)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_OFFSET              16
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK        (1 << 24)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_OFFSET      24
+/* at a minimum you always have to write '1' to this bit as it commits the 
+descriptor to the dispatcher */
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK                       (1 << 31)
+#define ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_OFFSET                     31
+
+/* Each register is byte lane accessible so the some of the values that are
+ * less than 32 bits wide are written to according to the field width.
+ */
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_LENGTH_REG, data)
+/* this pushes the descriptor into the read/write FIFOs when standard descriptors 
+are used */
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(base, data)  \
+        IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(base, data)  \
+        IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_BURST_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(base, data)  \
+        IOWR_8DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(base, data)  \
+        IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(base, data)  \
+        IOWR_16DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH_REG, data)
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH_REG, data)
+/* this pushes the descriptor into the read/write FIFOs when the extended 
+descriptors are used */
+#define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED(base, data)  \
+        IOWR_32DIRECT(base, ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED_REG, data)
+
+
+
+#endif /*ALTERA_MSGDMA_ALTERA_MSGDMA_DESCRIPTOR_REGS_H_*/
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h
new file mode 100644
index 0000000..49d0815
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_prefetcher_regs.h
@@ -0,0 +1,292 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#ifndef ALT_MSGDMA_PREFETCHER_REGS_H_
+#define ALT_MSGDMA_PREFETCHER_REGS_H_
+
+#include "io.h"
+
+/*
+  MSGDMA Prefetcher core is an additional micro core to existing MSGDMA core which 
+  already consists of dispatcher, read master and write master micro core. Prefetcher
+  core provides functionality to fetch a series of descriptors from memory that 
+  describes the required data transfers before pass them to dispatcher core for data 
+  transfer execution.
+*/
+
+
+/*
+ * Component : MSGDMA PREFETCHER
+ *
+ */
+#define ALT_MSGDMA_PREFETCHER_CONTROL_OFST                          0x00
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST        0x04
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST       0x08
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST           0x0C
+#define ALT_MSGDMA_PREFETCHER_STATUS_OFST                         0x10
+
+/*
+ * New MSGDMA PREFETCHER Descriptor fields.  These are not prefetcher registers
+ * they are in the prefetcher descriptor structs
+ */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW  value. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK      (1 << 30)
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW value. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK      0xBFFFFFFF
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW field. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_BIT_OFFSET    30
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_GET(value) (((value) & 0x40000000) >> 30)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET(value) (((value) << 30) & 0x40000000)
+
+/*
+ * Register : control 
+ *
+ * The control register has two defined bits.
+ *
+ * DESC_POLL_EN and RUN .
+ *
+ * Detailed description available in their individual bitfields
+ *
+ * Register Layout
+ *
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [0]    | R/W    | 0x0   | RUN
+ *  [1]    | R/W    | 0x0   | DESC_POLL_EN
+ *  [2]    | R/W1S  | 0x0   | RESET_PREFETCHER
+ *  [3]    | R/W    | 0x0   | GLOBAL_INTR_EN_MASK
+ *  [4]    | R/W    | 0x0   | PARK_MODE
+ *  [31:5] | R      | 0x0   | RESERVED
+ *
+ */
+
+/* bits making up the "control" register */
+
+/* the RUN bit field in the control register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK         0x1
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_CLR_MASK         0xFFFFFFFE
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET           0
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET(value) (((value) << 0) & 0x00000001)
+
+/* the DESC_POLL_EN bit field in the control register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK         0x2
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK     0xFFFFFFFD
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_BIT_OFFSET           1
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_SET(value) (((value) << 1) & 0x00000002)
+
+/* the RESET_PREFETCHER bit field in the control register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_RESET register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK         0x4
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_CLR_MASK         0xFFFFFFFB
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_BIT_OFFSET           2
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET(value) (((value) << 2) & 0x00000004)
+
+/* the GLOBAL_INTR_EN_MASK bit field in the control register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_MASK register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK         0x8
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK         0xFFFFFFF7
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_BIT_OFFSET           3
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET(value) (((value) << 3) & 0x00000008)
+
+/* the PARK_MODE bit field in the control register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK         0x10
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK         0xFFFFFFEF
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_BIT_OFFSET           4
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Registers : Next Descriptor Pointer Low/High 
+ *
+ * The register has no bit fields, the 64 bits represent an address.
+ *
+ * Register Layout
+ *
+ *  Bits   | Access | Reset | Description
+ * :-------|:-------|:------|:------------
+ *  [31:0] | R/W    | 0x0   | NEXT_PTR_ADDR_LOW
+ *  [63:32]| R/W    | 0x0   | NEXT_PTR_ADDR_HIGH
+ *
+ */
+
+/* bits making up the "Next Descriptor Pointer " register */
+
+/* the NEXT_PTR_ADDR_LOW bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG register field value. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET_MASK         0xFFFFFFFF
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_CLR_MASK         0x0
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_BIT_OFFSET           0
+/* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_GET(value) (((value) & 0xFFFFFFFF) >> 0)
+/* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_SET(value) (((value) << 0) & 0xFFFFFFFF)
+
+/* the NEXT_PTR_ADDR_HIGH bit field in the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG register field value. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET_MASK         0xFFFFFFFF
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_CLR_MASK         0x0
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_BIT_OFFSET           0
+/* Extracts the ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_GET(value) (((value) & 0xFFFFFFFF) >> 0)
+/* Produces a ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_REG register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_SET(value) (((value) << 0) & 0xFFFFFFFF)
+
+
+/*
+ * Register : Descriptor Polling Frequency 
+ *
+ * The Descriptor Polling Frequency register has one defined bit field.
+ *
+ * POLL_FREQ
+ *
+ * Detailed description available in their individual bitfields
+ *
+ * Register Layout
+ *
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [15:0]  | R/W    | 0x0   | POLL_FREQ
+ *  [31:16] | R      | 0x0   | RESERVED
+ *
+ */
+
+/* bits making up the "DESC_POLL_FREQ" register */
+
+/* the POLL_FREQ bit field in the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field value. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET_MASK         0xFFFF
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_CLR_MASK         0xFFFF0000
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */
+#define ALT_MSGDMA_PREFETCHER_CTRL_RUN_BIT_OFFSET           0
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_GET(value) (((value) & 0x0000FFFF) >> 0)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_SET(value) (((value) << 0) & 0x0000FFFF)
+
+
+/*
+ * Register : Status 
+ *
+ * The Status register has one defined bit field.
+ *
+ * IRQ
+ *
+ * Detailed description available in their individual bitfields
+ *
+ * Register Layout
+ *
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [0]     | R/W1C  | 0x0   | IRQ
+ *  [31:1]  | R      | 0x0   | RESERVED
+ *
+ */
+
+/* bits making up the "STATUS" register */
+
+/* the IRQ bit field in the ALT_MSGDMA_PREFETCHER_STATUS register */
+/* The mask used to set the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */
+#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK         0x1
+/* The mask used to clear the ALT_MSGDMA_PREFETCHER_STATUS_IRQ register field value. */
+#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_CLR_MASK         0xFFFFFFFE
+/* The bit offset of the ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ register field. */
+#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_BIT_OFFSET       0
+/* Extracts the ALT_MSGDMA_PREFETCHER_CTRL_RUN field value from a register. */
+#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_MSGDMA_PREFETCHER_CTRL_RUN register field value suitable for setting the register. */
+#define ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET(value) (((value) << 0) & 0x00000001)
+
+
+
+/*****************************************************************/
+/***   READ/WRITE macros for the MSGDMA PREFETCHER registers   ***/
+/*****************************************************************/
+/* ALT_MSGDMA_PREFETCHER_CONTROL_REG */
+#define IORD_ALT_MSGDMA_PREFETCHER_CONTROL(base)  \
+        IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST)
+#define IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(base, data)  \
+        IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_CONTROL_OFST, data)
+/* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_REG */
+#define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base)  \
+        IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST)
+#define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base, data)  \
+        IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW_OFST, data)
+/* ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_REG */
+#define IORD_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base)  \
+        IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST)
+#define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base, data)  \
+        IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH_OFST, data)
+/* ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ_REG */
+#define IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base)  \
+        IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST)
+#define IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base, data)  \
+        IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLL_FREQ_OFST, data)
+/* ALT_MSGDMA_PREFETCHER_STATUS_REG */
+#define IORD_ALT_MSGDMA_PREFETCHER_STATUS(base)  \
+        IORD_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST)
+#define IOWR_ALT_MSGDMA_PREFETCHER_STATUS(base, data)  \
+        IOWR_32DIRECT(base, ALT_MSGDMA_PREFETCHER_STATUS_OFST, data)
+
+#endif /*ALT_MSGDMA_PREFETCHER_REGS_H_*/
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h
new file mode 100644
index 0000000..65424d6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_msgdma_response_regs.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#ifndef ALTERA_MSGDMA_RESPONSE_REGS_H_
+#define ALTERA_MSGDMA_RESPONSE_REGS_H_
+
+#include "io.h"
+
+/*
+  The response slave port only carries the actual bytes transferred,
+  error, and early termination bits.  Reading from the upper most byte
+  of the 2nd register pops the response FIFO.  For proper FIFO popping
+  always read the actual bytes transferred followed by the error and early
+  termination bits using 'little endian' accesses.  If a big endian
+  master accesses the response slave port make sure that address 0x7 is the
+  last byte lane access as it's the one that pops the reponse FIFO.
+  
+  If you use a pre-fetching descriptor master in front of the dispatcher
+  port then you do not need to access this response slave port. 
+*/
+
+
+
+#define ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG    0x0
+#define ALTERA_MSGDMA_RESPONSE_ERRORS_REG                      0x4
+
+/* bits making up the "errors" register */
+#define ALTERA_MSGDMA_RESPONSE_ERROR_MASK                      0xFF
+#define ALTERA_MSGDMA_RESPONSE_ERROR_OFFSET                    0
+#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_MASK          (1 << 8)
+#define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_OFFSET        8
+
+
+/* read macros for each 32 bit register */
+#define IORD_ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG)
+/* this read pops the response FIFO */
+#define IORD_ALTERA_MSGDMA_RESPONSE_ERRORS_REG(base)  \
+        IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ERRORS_REG)   
+
+
+#endif /*ALTERA_MSGDMA_RESPONSE_REGS_H_*/
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h
new file mode 100644
index 0000000..0d915fc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_ONCHIP_FLASH_H__
+#define __ALT_ONCHIP_FLASH_H__
+
+#include "alt_types.h"
+#include "sys/alt_flash_dev.h"
+#include "sys/alt_llist.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ *  Getting started:
+ *  Nios II Software Developer's Handbook (URL: http://www.altera.com/literature/lit-nio2.jsp)
+ *  -> Section II. Hardware Abstraction Layer
+ *     -> Chapter 6. Developing Programs Using the Hardware Abstraction Layer
+ *        -> Using Flash Devices
+ */
+
+/*
+ *  Description of the flash
+ */
+typedef struct alt_onchip_flash_dev
+{
+    /* Flash common declaration */
+    alt_flash_dev dev;
+
+    /* IP specific information */
+    int           is_read_only;
+    void          *csr_base;
+    int           sector1_enabled;
+    int           sector1_start_addr;
+    int           sector1_end_addr;
+    int           sector2_enabled;
+    int           sector2_start_addr;
+    int           sector2_end_addr;
+    int           sector3_enabled;
+    int           sector3_start_addr;
+    int           sector3_end_addr;
+    int           sector4_enabled;
+    int           sector4_start_addr;
+    int           sector4_end_addr;
+    int           sector5_enabled;
+    int           sector5_start_addr;
+    int           sector5_end_addr;
+    int           page_size;
+} alt_onchip_flash_dev;
+
+/*
+*   Macros used by alt_sys_init.c
+*
+*/
+#define ALTERA_ONCHIP_FLASH_DATA_CSR_INSTANCE(name, data, csr, dev) \
+static alt_onchip_flash_dev dev =   \
+{                                   \
+  {                                 \
+    ALT_LLIST_ENTRY,                \
+    data##_NAME,               \
+    NULL,                           \
+    NULL,                           \
+    alt_onchip_flash_write,         \
+    alt_onchip_flash_read,          \
+    alt_onchip_flash_get_info,      \
+    alt_onchip_flash_erase_block,   \
+    alt_onchip_flash_write_block,   \
+    ((void*)(data##_BASE)),    \
+    ((int)(data##_SPAN)),      \
+    0                               \
+  },                                \
+  data##_READ_ONLY_MODE,       \
+  ((void*)(csr##_BASE)),       \
+  data##_SECTOR1_ENABLED,      \
+  data##_SECTOR1_START_ADDR,   \
+  data##_SECTOR1_END_ADDR,     \
+  data##_SECTOR2_ENABLED,      \
+  data##_SECTOR2_START_ADDR,   \
+  data##_SECTOR2_END_ADDR,     \
+  data##_SECTOR3_ENABLED,      \
+  data##_SECTOR3_START_ADDR,   \
+  data##_SECTOR3_END_ADDR,     \
+  data##_SECTOR4_ENABLED,      \
+  data##_SECTOR4_START_ADDR,   \
+  data##_SECTOR4_END_ADDR,     \
+  data##_SECTOR5_ENABLED,      \
+  data##_SECTOR5_START_ADDR,   \
+  data##_SECTOR5_END_ADDR,     \
+  data##_BYTES_PER_PAGE        \
+}
+
+/*
+    Public API
+
+    Refer to Using Flash Devices in the
+    Developing Programs Using the Hardware Abstraction Layer chapter
+    of the Nios II Software Developer's Handbook.
+
+*/
+
+int alt_onchip_flash_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
+
+int alt_onchip_flash_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
+
+int alt_onchip_flash_erase_block(alt_flash_dev *flash_info, int block_offset);
+
+int alt_onchip_flash_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
+
+int alt_onchip_flash_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
+
+/*
+ * Initialization function
+ */
+extern void altera_onchip_flash_init(alt_onchip_flash_dev *dev);
+
+/*
+ * alt_sys_init.c will call this macro automatically
+ */
+#define ALTERA_ONCHIP_FLASH_INIT(name, dev) { altera_onchip_flash_init(&dev); }
+
+
+/*
+	Private API
+
+	Helper functions used by Public API functions.
+*/
+
+int alt_onchip_flash_poll_for_status_to_go_idle(alt_onchip_flash_dev *flash);
+
+int alt_onchip_flash_poll_for_status_erase_passed(alt_onchip_flash_dev* flash);
+
+int alt_onchip_flash_poll_for_status_write_passed(alt_onchip_flash_dev* flash);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_ONCHIP_FLASH_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h
new file mode 100644
index 0000000..6006e94
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/altera_onchip_flash_regs.h
@@ -0,0 +1,241 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_ONCHIP_FLASH_REGS_H__
+#define __ALTERA_ONCHIP_FLASH_REGS_H__
+
+#include <io.h>
+
+/*
+ * Status Register
+*/
+#define ALTERA_ONCHIP_FLASH_STATUS_REG                          0
+#define ALTERA_ONCHIP_FLASH_STATUS_MSK                          (0x00007FFF)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK                     (0x00000003)
+#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE                    (0x00000000)
+#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_ERASE                   (0x00000001)
+#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_WRITE                   (0x00000002)
+#define ALTERA_ONCHIP_FLASH_STATUS_BUSY_READ                    (0x00000003)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_READ_MSK                     (0x00000004)
+#define ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED                  (0x00000004)
+#define ALTERA_ONCHIP_FLASH_STATUS_READ_FAILED                  (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK                    (0x00000008)
+#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED                 (0x00000008)
+#define ALTERA_ONCHIP_FLASH_STATUS_WRITE_FAILED                 (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK                    (0x00000010)
+#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED                 (0x00000010)
+#define ALTERA_ONCHIP_FLASH_STATUS_ERASE_FAILED                 (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK                  (0x00000020)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE          (0x00000020)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK                  (0x00000040)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE          (0x00000040)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK                  (0x00000080)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE          (0x00000080)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK                  (0x00000100)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE          (0x00000100)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK                  (0x00000200)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE          (0x00000200)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READONLY_MSK         (0x00000400)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READONLY             (0x00000400)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_READWRITE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READONLY_MSK         (0x00000800)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READONLY             (0x00000800)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_READWRITE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READONLY_MSK         (0x00001000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READONLY             (0x00001000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_READWRITE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READONLY_MSK         (0x00002000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READONLY             (0x00002000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_READWRITE            (0x00000000)
+
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READONLY_MSK         (0x00004000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READONLY             (0x00004000)
+#define ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_READWRITE            (0x00000000)
+
+#define IOADDR_ALTERA_ONCHIP_FLASH_STATUS(base)                  \
+                 __IO_CALC_ADDRESS_NATIVE(base, ALTERA_ONCHIP_FLASH_STATUS_REG)
+
+#define   IORD_ALTERA_ONCHIP_FLASH_STATUS(base)                  \
+                                     IORD(base, ALTERA_ONCHIP_FLASH_STATUS_REG)
+
+#define   IOWR_ALTERA_ONCHIP_FLASH_STATUS(base, data)            \
+                                     IOWR(base, ALTERA_ONCHIP_FLASH_STATUS_REG, data)
+
+
+/*
+ * Control Register
+*/
+#define ALTERA_ONCHIP_FLASH_CONTROL_REG                         1
+#define ALTERA_ONCHIP_FLASH_CONTROL_MSK                         (0xCFFFFFFF)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK              (0x000FFFFF)
+#define ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET          (0x000FFFFF)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK            (0x00700000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR1        (0x00100000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR2        (0x00200000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR3        (0x00300000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR4        (0x00400000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_SECTOR5        (0x00500000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET        (0x00700000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_PROTECT_MSK   (0x00800000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_ENABLE        (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR1_WRITE_DISABLE       (0x00800000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_PROTECT_MSK   (0x01000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_ENABLE        (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR2_WRITE_DISABLE       (0x01000000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_PROTECT_MSK   (0x02000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_ENABLE        (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR3_WRITE_DISABLE       (0x02000000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_PROTECT_MSK   (0x04000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_ENABLE        (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR4_WRITE_DISABLE       (0x04000000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_PROTECT_MSK   (0x08000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_ENABLE        (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_SECTOR5_WRITE_DISABLE       (0x08000000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK (0x0F800000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE      (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_DISABLE     (0x0F800000)
+
+#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_MSK             (0xC0000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_IDLE            (0x00000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_PENDING         (0x40000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_BUSY            (0x80000000)
+#define ALTERA_ONCHIP_FLASH_CONTROL_ERASE_STATE_RSVD            (0xC0000000)
+
+#define IOADDR_ALTERA_ONCHIP_FLASH_CONTROL(base)                  \
+                  __IO_CALC_ADDRESS_NATIVE(base, ALTERA_ONCHIP_FLASH_CONTROL_REG)
+
+#define   IORD_ALTERA_ONCHIP_FLASH_CONTROL(base)                  \
+                                      IORD(base, ALTERA_ONCHIP_FLASH_CONTROL_REG)
+
+#define   IOWR_ALTERA_ONCHIP_FLASH_CONTROL(base, data)            \
+                                      IOWR(base, ALTERA_ONCHIP_FLASH_CONTROL_REG, data)
+
+
+/*
+ * Constant value
+*/
+#define ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE                     (32/8)
+/* 0.7 sec time out */
+#define ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE    700000
+
+/*
+ * Functional Macros
+*/
+
+/* Enable Write and Erase Operation */
+#define ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(base)              \
+    (                                                                           \
+        IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base),                                \
+            (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base))                           \
+            &                                                                   \
+                ~(                                                              \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK |   \
+                    ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK |                \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK                \
+                )                                                               \
+            )                                                                   \
+            |                                                                   \
+                (                                                               \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE |        \
+                    ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET |            \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET            \
+                )                                                               \
+        )                                                                       \
+    )
+
+/* Disable Write and Erase Operation */
+#define ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(base)             \
+    (                                                                           \
+        IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base),                                \
+            (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base))                           \
+            &                                                                   \
+                ~(                                                              \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK |   \
+                    ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK |                \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK                \
+                )                                                               \
+            )                                                                   \
+            |                                                                   \
+                (                                                               \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_DISABLE |       \
+                    ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_NOT_SET |            \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET            \
+                )                                                               \
+        )                                                                       \
+    )
+
+/* Page Erase Operation */
+#define ALTERA_ONCHIP_FLASH_PAGE_ERASE(base, page_erase_block_address)          \
+    (                                                                           \
+        IOWR_ALTERA_ONCHIP_FLASH_CONTROL((base),                                \
+            (IORD_ALTERA_ONCHIP_FLASH_CONTROL((base))                           \
+            &                                                                   \
+                ~(                                                              \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_PROTECT_MSK |   \
+                    ALTERA_ONCHIP_FLASH_CONTROL_PAGE_ERASE_MSK |                \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_MSK                \
+                )                                                               \
+            )                                                                   \
+            |                                                                   \
+                (                                                               \
+                    ALTERA_ONCHIP_FLASH_CONTROL_ALLSECTOR_WRITE_ENABLE  |       \
+                    (page_erase_block_address) |                                \
+                    ALTERA_ONCHIP_FLASH_CONTROL_SECTOR_ERASE_NOT_SET            \
+                )                                                               \
+        )                                                                       \
+    )
+
+#endif /* __ALTERA_ONCHIP_FLASH_REGS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h
new file mode 100644
index 0000000..9d0a23b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/altera_eth_tse_iniche.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALTERA_ETH_TSE_INICHE_H__
+#define __ALTERA_ETH_TSE_INICHE_H__
+
+#include "alt_iniche_dev.h"
+#include "altera_eth_tse_regs.h"
+#include "ins_tse_mac.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/* System Constant Definition Used in the TSE Driver Code */
+#define ALTERA_TSE_PKT_INIT_LEN                    1528
+                 
+#define ALTERA_TSE_ADMIN_STATUS_DOWN               2
+#define ALTERA_TSE_ADMIN_STATUS_UP                 1
+#define ALTERA_TSE_MAX_MTU_SIZE                    1514
+#define ALTERA_TSE_MIN_MTU_SIZE                    14
+#define ALTERA_TSE_HAL_ADDR_LEN                    6
+
+
+
+/*******************************
+ *
+ * Public API for TSE Driver 
+ *
+ *******************************/
+
+
+ /* @Function Description: TSE MAC Driver Open/Initialization routine
+ * @API TYPE: Public
+ * @Param p_dec        pointer to TSE device instance
+ * @Return SUCCESS
+ */
+
+error_t altera_eth_tse_init(
+    alt_iniche_dev              *p_dev);
+ 
+ 
+/* @Function Description -  Closing the TSE MAC Driver Interface
+ *                          
+ * 
+ * @API TYPE - Public
+ * @param  iface    index of the NET interface associated with the TSE MAC.
+ * @return SUCCESS
+ */
+int tse_mac_close(int iface);
+
+
+
+/* @Function Description -  TSE transmit API to send data to the MAC
+ *                          
+ * 
+ * @API TYPE - Public
+ * @param  net  - NET structure associated with the TSE MAC instance
+ * @param  data - pointer to the data payload
+ * @param  data_bytes - number of bytes of the data payload to be sent to the MAC
+ * @return SUCCESS if success, else SEND_DROPPED, ENP_RESOURCE if error 
+ * 
+ */
+int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes);
+
+/* @Function Description -  TSE transmit API to send data to the MAC
+ *                          
+ * 
+ * @API TYPE - Public
+ * @param  pke  - Packet containing data to send
+ * @return SUCCESS if success, else SEND_DROPPED, ENP_RESOURCE if error 
+ * 
+ */
+int tse_mac_pkt_send(PACKET pkt);
+
+
+/********************************
+ *
+ * Internal API for TSE Driver 
+ *
+ *******************************/
+
+/** @Function Description: TSE MAC Driver Open/Registration routine
+  * @API TYPE: Internal
+  * @Param index     index of the NET structure associated with TSE instance
+  * @Return next index of NET
+  */
+int prep_tse_mac(int index, alt_tse_system_info *psys_info);
+
+
+
+/* @Function Description: TSE MAC Initialization routine. This function opens the
+ *                          device handle, configure the callback function and interrupts ,
+ *                        for MSGDMA TX and MSGDMA RX block associated with the TSE MAC,
+ *                        Initialize the MAC Registers for the RX FIFO and TX FIFO
+ *                        threshold watermarks, initialize the tse device structure,
+ *                        set the MAC address of the device and enable the MAC   
+ * 
+ * @API TYPE: Internal
+ * @Param iface    index of the NET structure associated with TSE instance
+ * @Return SUCCESS if ok, else ENP_RESOURCE, ENP_PARAM, ENP_LOGIC if error
+ */
+int tse_mac_init(int iface);
+
+
+
+/* @Function Description -    TSE Driver MSGDMA RX ISR callback function
+ *                            
+ * 
+ * @API TYPE - callback
+ * @param  context    - context of the TSE MAC instance
+ * @param  intnum - temporary storage
+ * @return SUCCESS on success else ENP_LOGIC if error
+ */
+void tse_msgdmaRx_isr(void * context);
+
+/* @Function Description -    TSE Driver MSGDMA TX ISR callback function
+ *                            
+ * 
+ * @API TYPE - callback
+ * @param  context    - context of the TSE MAC instance
+ * @param  intnum - temporary storage
+ * @return SUCCESS on success else ENP_LOGIC if error
+ */
+void tse_msgdmaTx_isr(void * context);
+
+
+/* @Function Description -    Init and setup MSGDMA RX Descriptor chain
+ *                            
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success else ENP_NOBUFFER if error
+ */
+int tse_msgdma_read_init(ins_tse_info* tse_ptr);
+
+
+/* @Function Description -    Init and setup MSGDMA TX Descriptor chain
+ *                            
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success else ENP_NOBUFFER if error
+ */
+int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len);
+
+
+/* @Function Description -    TSE Driver MSGDMA RX ISR callback function
+ *                            
+ * 
+ * @API TYPE        - callback internal function
+ * @return SUCCESS on success else ENP_NORESOURCE, ENP_NOBUFFER if error
+ */
+void tse_mac_rcv(ins_tse_info* tse_ptr);
+
+/* @Function Description -    allocate rx descriptor chain memory
+ *                            
+ * 
+ * @API TYPE        - callback internal function
+ * @return SUCCESS on success else 1 if error
+ */
+int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr);
+
+
+int tse_mac_stats(void * pio, int iface);
+
+
+/**********************************
+ *
+ * TSE Driver Structure Definition
+ *
+ **********************************/
+
+typedef struct 
+{
+    alt_iniche_dev              dev;
+} altera_eth_tse_if;
+
+typedef struct
+{
+    alt_iniche_dev              *p_dev;
+    alt_u32                     hw_mac_base_addr;
+    alt_u8                      hw_channel_number;
+} alt_tse_iniche_dev_driver_data;
+
+#define ALTERA_ETH_TSE_INSTANCE(inst_name, dev_inst)                                                                 \
+altera_eth_tse_if dev_inst##_if[8];                                                                                  \
+char *dev_inst##_name = inst_name##_NAME;
+
+#define ALTERA_ETH_TSE_INIT(inst_name, dev_inst)                                                                     \
+{                                                                                                                           \
+     extern alt_u8 number_of_tse_mac;                                                                                       \
+     extern alt_tse_iniche_dev_driver_data tse_iniche_dev_driver_data[MAXNETS];                                             \
+                                                                                                                            \
+     int dev_inst##_loop_control = 0;                                                                                       \
+     int dev_inst##_number_of_channel = inst_name##_NUMBER_OF_CHANNEL;                                                      \
+     if(dev_inst##_number_of_channel < 1) {                                                                                 \
+        dev_inst##_number_of_channel = 1;                                                                                   \
+     }                                                                                                                      \
+                                                                                                                            \
+     for(dev_inst##_loop_control = 0; dev_inst##_loop_control < dev_inst##_number_of_channel; dev_inst##_loop_control++) {  \
+        dev_inst##_if[dev_inst##_loop_control].dev.llist.next     = 0;                                                      \
+        dev_inst##_if[dev_inst##_loop_control].dev.llist.previous = 0;                                                      \
+        dev_inst##_if[dev_inst##_loop_control].dev.name           = dev_inst##_name;                                        \
+        dev_inst##_if[dev_inst##_loop_control].dev.init_func      = altera_eth_tse_init;                             \
+                                                                                                                            \
+        alt_iniche_dev_reg(&(dev_inst##_if[dev_inst##_loop_control].dev));                                                  \
+        tse_iniche_dev_driver_data[number_of_tse_mac].p_dev = &(dev_inst##_if[dev_inst##_loop_control].dev);                \
+        tse_iniche_dev_driver_data[number_of_tse_mac].hw_mac_base_addr = inst_name##_BASE;                                  \
+        tse_iniche_dev_driver_data[number_of_tse_mac].hw_channel_number = dev_inst##_loop_control;                          \
+        number_of_tse_mac++;                                                                                                \
+     }                                                                                                                      \
+}
+     
+error_t altera_eth_tse_init(
+    alt_iniche_dev              *p_dev);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALTERA_ETH_TSE_INICHE_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h
new file mode 100644
index 0000000..4b6e01c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/inc/iniche/ins_tse_mac.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifndef _ins_tse_regs_h_
+#define _ins_tse_regs_h_
+
+#include "altera_msgdma.h"
+#include "altera_msgdma_descriptor_regs.h"
+#include "altera_msgdma_prefetcher_regs.h"
+#include "altera_msgdma_csr_regs.h"
+#include "altera_avalon_tse.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ALT_INICHE
+#include "ipport.h"
+#include "tcpport.h"
+#endif
+
+/* Base-Structure for all library functions */
+typedef struct{
+    /* index number */
+    int     index;
+    
+    tse_mac_trans_info mi; /* MAC base driver data. */
+
+    /* driver specific */
+    char     mac_addr[8];   /* use 8 to word align */
+    NET      netp;          /* pointer to Interniche NET struct */
+    int      txShift16OK;   /* TX supports Shift16 */
+    int      rxShift16OK;   /* RX supports Shift16 */
+/* Temporary variable to "protect" our transmit function - should be protected otherwise though */
+    int     sem;    
+/* Variable to store Channel number for Share Fifo System */
+    int     channel;
+    
+    // Location for the MSGDMA Descriptors
+    alt_msgdma_prefetcher_standard_descriptor *txdesc_list;        
+    alt_msgdma_prefetcher_standard_descriptor *txdesc;   
+    //The two lists are used to prepare one list while the other is executing    
+    alt_msgdma_prefetcher_standard_descriptor *rxdesc_list[2];    
+    alt_msgdma_prefetcher_standard_descriptor *rxdesc[2];
+    int     rx_chain;
+    int     rx_descriptor_index;
+    int     tx_descriptor_index;    
+    
+    // Pre-allocation of packet buffers for each RX descriptor
+    PACKET pkt_array_rx[2][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE];
+   
+    // Hardware location
+    void *tse;
+    
+} ins_tse_info;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ins_tse_regs_h_*/
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c
new file mode 100644
index 0000000..3dfca88
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_sysid_qsys.c
@@ -0,0 +1,82 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include "altera_avalon_sysid_qsys.h"
+#include "altera_avalon_sysid_qsys_regs.h"
+#include "alt_types.h"
+#include <io.h>
+
+/*
+*  This component is special: there's only one of it.
+*  Therefore we can dispense with a bunch of complexity
+*  normally associated with components, such as specialized
+*  structs containing parameter info, and instead use that
+*  info by name directly out of system.h.  A downside of this
+*  approach is that each time the system is regenerated, and
+*  system.h changes, this file must be recompiled.  Fortunately
+*  this file is, and is likely to remain, quite small.
+*/
+#include "system.h"
+
+#ifdef SYSID_BASE
+/*
+*  return values:
+*    0 if the hardware and software appear to be in sync
+*    1 if software appears to be older than hardware
+*   -1 if hardware appears to be older than software
+*/
+
+alt_32 alt_avalon_sysid_qsys_test(void)
+{
+  /* Read the hardware-tag, aka value0, from the hardware. */
+  alt_u32 hardware_id = IORD_ALTERA_AVALON_SYSID_QSYS_ID(SYSID_BASE);
+
+  /* Read the time-of-generation, aka value1, from the hardware register. */
+  alt_u32 hardware_timestamp = IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(SYSID_BASE);
+
+  /* Return 0 if the hardware and software appear to be in sync. */
+  if ((SYSID_TIMESTAMP == hardware_timestamp) && (SYSID_ID == hardware_id))
+  {
+    return 0;
+  }
+
+  /*
+  *  Return 1 if software appears to be older than hardware (that is,
+  *  the value returned by the hardware is larger than that recorded by
+  *  the generator function).
+  *  If the hardware time happens to match the generator program's value
+  *  (but the hardware tag, value0, doesn't match or 0 would have been
+  *  returned above), return an arbitrary value, let's say -1.
+  */
+  return ((alt_32)(hardware_timestamp - SYSID_TIMESTAMP)) > 0 ? 1 : -1;
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c
new file mode 100644
index 0000000..715723d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_sc.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <string.h>
+
+#include "sys/alt_alarm.h"
+#include "sys/alt_irq.h"
+
+#include "altera_avalon_timer.h"
+#include "altera_avalon_timer_regs.h"
+
+#include "alt_types.h"
+#include "sys/alt_log_printf.h"
+
+/* 
+ * alt_avalon_timer_sc_irq() is the interrupt handler used for the system 
+ * clock. This is called periodically when a timer interrupt occurs. The 
+ * function first clears the interrupt condition, and then calls the 
+ * alt_tick() function to notify the system that a timer tick has occurred.
+ *
+ * alt_tick() increments the system tick count, and updates any registered 
+ * alarms, see alt_tick.c for further details.
+ */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void alt_avalon_timer_sc_irq (void* base)
+#else
+static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
+#endif
+{
+  alt_irq_context cpu_sr;
+  
+  /* clear the interrupt */
+  IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
+  
+  /* 
+   * Dummy read to ensure IRQ is negated before the ISR returns.
+   * The control register is read because reading the status
+   * register has side-effects per the register map documentation.
+   */
+  IORD_ALTERA_AVALON_TIMER_CONTROL (base);
+
+  /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
+  ALT_LOG_SYS_CLK_HEARTBEAT();
+
+  /* 
+   * Notify the system of a clock tick. disable interrupts 
+   * during this time to safely support ISR preemption
+   */
+  cpu_sr = alt_irq_disable_all();
+  alt_tick ();
+  alt_irq_enable_all(cpu_sr);
+}
+
+/*
+ * alt_avalon_timer_sc_init() is called to initialise the timer that will be 
+ * used to provide the periodic system clock. This is called from the 
+ * auto-generated alt_sys_init() function.
+ */
+
+void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, 
+                                alt_u32 irq, alt_u32 freq)
+{
+  /* set the system clock frequency */
+  
+  alt_sysclk_init (freq);
+  
+  /* set to free running mode */
+  
+  IOWR_ALTERA_AVALON_TIMER_CONTROL (base, 
+            ALTERA_AVALON_TIMER_CONTROL_ITO_MSK  |
+            ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
+            ALTERA_AVALON_TIMER_CONTROL_START_MSK);
+
+  /* register the interrupt handler, and enable the interrupt */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+  alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, 
+                      base, NULL);
+#else
+  alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
+#endif  
+}
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c
new file mode 100644
index 0000000..c5df1b4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_ts.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <string.h>
+
+#include "system.h"
+#include "sys/alt_timestamp.h"
+
+#include "altera_avalon_timer.h"
+#include "altera_avalon_timer_regs.h"
+
+#include "alt_types.h"
+
+/*
+ * These functions are only available if a timestamp device has been selected
+ * for this system.
+ */
+
+#if (ALT_TIMESTAMP_CLK_BASE != none_BASE) 
+
+/*
+ * The function alt_timestamp_start() can be called at application level to
+ * initialise the timestamp facility. In this case the period register is
+ * set to full scale, i.e. 0xffffffff, and then started running. Note that
+ * the period register may not be writable, depending on the hardware 
+ * configuration, in which case this function does not reset the period.
+ *
+ * The timer is not run in continuous mode, so that the user can detect timer
+ * roll-over, i.e. alt_timestamp() returns 0.
+ *
+ * The return value of this function is 0 upon sucess and -1 if in timestamp
+ * device has not been registered. 
+ */
+
+int alt_timestamp_start(void)
+{
+  void* base = altera_avalon_timer_ts_base;
+
+  if (!altera_avalon_timer_ts_freq)
+  {
+    return -1;
+  }
+  else
+  {
+    if(ALT_TIMESTAMP_COUNTER_SIZE == 64) {
+        IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
+        IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF);
+        IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);;
+        IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF);
+        IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF);
+        IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
+    } else {
+        IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
+        IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF);
+        IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF);
+        IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); 
+    } 
+  }
+  return 0;
+}
+
+/*
+ * alt_timestamp() returns the current timestamp count. In the event that
+ * the timer has run full period, or there is no timestamp available, this
+ * function return -1.
+ *
+ * The returned timestamp counts up from the last time the period register
+ * was reset. 
+ */
+
+alt_timestamp_type alt_timestamp(void)
+{
+
+  void* base = altera_avalon_timer_ts_base;
+
+  if (!altera_avalon_timer_ts_freq)
+  {
+#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
+        return 0xFFFFFFFFFFFFFFFFULL;
+#else
+        return 0xFFFFFFFF;
+#endif
+  }
+  else
+  {
+#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
+        IOWR_ALTERA_AVALON_TIMER_SNAP_0 (base, 0);
+        alt_timestamp_type snap_0 = IORD_ALTERA_AVALON_TIMER_SNAP_0(base) & ALTERA_AVALON_TIMER_SNAP_0_MSK;
+        alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK;
+        alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK;
+        alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK;
+        
+        return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) ));
+#else
+        IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0);
+        alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK;
+        alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK;
+        
+        return (0xFFFFFFFF - ((upper << 16) | lower)); 
+#endif
+  }
+}
+
+/*
+ * Return the number of timestamp ticks per second. This will be 0 if no
+ * timestamp device has been registered.
+ */
+
+alt_u32 alt_timestamp_freq(void)
+{
+  return altera_avalon_timer_ts_freq;
+}
+
+#endif /* timestamp available */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c
new file mode 100644
index 0000000..57c431d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_timer_vars.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+#include <string.h>
+
+#include "altera_avalon_timer.h"
+#include "alt_types.h"
+
+/*
+ * Variables used to store the timestamp parameters. These are initialised
+ * from alt_sys_init() using the ALTERA_AVALON_TIMER_INIT macro
+ * defined in altera_avalon_timer.h.
+ */
+
+void* altera_avalon_timer_ts_base = (void*) 0;
+alt_u32 altera_avalon_timer_ts_freq = 0;
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c
new file mode 100644
index 0000000..9c2acc1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse.c
@@ -0,0 +1,2339 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "altera_avalon_tse.h"
+#include "sys/alt_cache.h" 
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+void no_printf (char *fmt, ...) {}
+
+#ifdef __ALTERA_MSGDMA
+
+
+/** @Function Description - Perform initialization steps on transaction info structure to prepare it for .
+  *                        use by the library functions with two MSGDMAs and extra initialization Flags
+  * @API Type:          Internal
+  * @param mi           Main Device Structure.
+  * @param mac_base     Base Address of the Control interface for the TSE MAC
+  * @param tx_msgdma     MSGDMA device handle for TSE transmit data path 
+  * @param rx_msgdma     MSGDMA device handle for TSE receive data path
+  * @param cfgflags     initialization flags for the device
+  * @return 0 
+  */
+
+alt_32 tse_mac_initTransInfo2( tse_mac_trans_info *mi,
+                                        alt_u32 mac_base,
+                                        alt_32 tx_msgdma,
+                                        alt_32 rx_msgdma,
+                                        alt_32 cfgflags) {
+                                              
+        mi->base     = (np_tse_mac*)mac_base;
+        mi->tx_msgdma = (alt_msgdma_dev *)tx_msgdma;
+        mi->rx_msgdma = (alt_msgdma_dev *)rx_msgdma;
+        mi->cfgflags = cfgflags;     
+        return SUCCESS;
+}
+
+/** @Function Description - Synchronous MSGDMA copy from buffer memory into transmit FIFO. Waits until 
+  *                         SGDMA has completed.  Raw function without any error checks.
+  * @API Type:              Internal
+  * @param mi               Main Device Structure.
+  * @param txDesc           Pointer to the transmit MSGDMA descriptor
+  * @return actual bytes transferred if ok, else error (-1)
+  */
+alt_32 tse_mac_sTxWrite( tse_mac_trans_info *mi, 
+                       alt_msgdma_standard_descriptor *txDesc)   
+{ 
+
+  alt_32 timeout;
+  alt_u8 result = 0;
+  
+  // Make sure DMA controller is not busy from a former command
+  // and TX is able to accept data
+  timeout = 0;
+  while ( (IORD_ALTERA_MSGDMA_CSR_STATUS(mi->tx_msgdma->csr_base) & 
+           ALTERA_MSGDMA_CSR_BUSY_MASK) ) {
+           if(timeout++ == ALTERA_TSE_MSGDMA_BUSY_TIME_OUT_CNT) {
+            tse_dprintf(4, "WARNING : TX MSGDMA Timeout\n");
+            return ENP_RESOURCE;  // avoid being stuck here
+           }
+  }
+  
+  // Start MSGDMA (blocking call)
+  alt_dcache_flush(txDesc,sizeof(alt_msgdma_standard_descriptor));
+  result = alt_msgdma_standard_descriptor_sync_transfer(
+                mi->tx_msgdma, 
+                txDesc);
+  
+  if (result != 0) {
+    tse_dprintf(4, "WARNING :alt_msgdma_standard_descriptor_sync_transfer Error code 0x%x\n",result);
+    return -1;
+  }
+
+  return 0;
+}
+
+
+/** @Function Description - Asynchronous MSGDMA copy from rxFIFO into given buffer memory area.
+  *                         Raw function without any error checks.
+  *
+  * @API Type:    Internal
+  * @param mi     Main Device Structure.
+  * @param rxDesc Pointer to the receive MSGDMA descriptor list
+  * @return 0 if ok, else error (-1)
+  *
+  * Note:  At the point of this function call return, 
+  *        the MSGDMA asynchronous operation may not have been
+  *        completed yet, so the function does not return
+  *        the actual bytes transferred for current descriptor
+  */
+alt_32 tse_mac_aRxRead( 
+  tse_mac_trans_info *mi,       
+  alt_msgdma_prefetcher_standard_descriptor *rxDesc)  
+{
+  alt_u8 result;
+           
+  result = alt_msgdma_start_prefetcher_with_std_desc_list(
+                mi->rx_msgdma, 
+                rxDesc,0,0,1,1);
+  
+  if (result != 0) { return -1; }
+ 
+  return SUCCESS;
+}
+
+/** @Function Description - Asynchronous MSGDMA transfer from buffer to txFIFO 
+  *               
+  *
+  * @API Type:    Internal
+  * @param mi     Main Device Structure.
+  * @param rxDesc Pointer to the transmit MSGDMA descriptor list
+  * @return 0 if ok, or (-1) if error
+  *
+  */
+alt_32 tse_mac_aTxWrite( 
+  tse_mac_trans_info *mi,       
+  alt_msgdma_prefetcher_standard_descriptor *txDesc)  
+{
+  alt_u8 result;
+  
+  result = alt_msgdma_start_prefetcher_with_std_desc_list(
+                mi->tx_msgdma, 
+                txDesc,0,0,1,1);
+
+  if (result != 0) { return -1; }
+ 
+  return SUCCESS;
+}
+
+
+#endif /* __ALTERA_MSGDMA */
+
+/* Definition of TSE system */
+extern alt_tse_system_info tse_mac_device[MAXNETS];
+
+/* PHY profile*/
+alt_tse_phy_profile *pphy_profiles[TSE_MAX_PHY_PROFILE];
+alt_u8 phy_profile_count = 0;
+
+/* MAC in TSE system */
+alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM];
+alt_u8 mac_group_count = 0;
+alt_u8 max_mac_system = MAXNETS;
+
+/*******************************
+ *
+ * Public API for TSE Driver 
+ *
+ *******************************/
+ 
+/* @Function Description: Perform a software Reset. Reset operation will ocur with some latency.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+*/
+alt_32 tse_mac_SwReset(np_tse_mac *pmac) 
+{
+    alt_32 timeout;
+    alt_32 cc;
+        
+    cc = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+    
+    // set reset and Gig-Speed bits to make sure we have an incoming clock on
+    // tx side. If there is a 10/100 PHY, we will still have a valid clock on
+    // tx_clk no matter what setting we have here, but on a Gig phy the
+    // MII clock may be missing.
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,(ALTERA_TSEMAC_CMD_SW_RESET_MSK | ALTERA_TSEMAC_CMD_ETH_SPEED_MSK));
+
+    
+    // wait for completion with fallback in case there is no PHY or it is
+    // not connected and hence might not provide any clocks at all.
+    timeout=0;
+    while( (IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac) & ALTERA_TSEMAC_CMD_SW_RESET_MSK) != 0 && timeout < ALTERA_TSE_SW_RESET_TIME_OUT_CNT) timeout++;
+   
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,cc); // Restore
+    return SUCCESS;
+}
+
+
+
+/* @Function Description: Perform switching of the TSE MAC into MII (10/100) mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+*/
+alt_32 tse_mac_setMIImode(np_tse_mac *pmac)
+{
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+  helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK; 
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar);
+  return SUCCESS;
+}
+
+
+/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Public
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address 
+ */
+alt_32 tse_mac_setGMIImode(np_tse_mac *pmac)
+{
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+  helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar);
+  return SUCCESS;
+}
+
+
+
+/* @Function Description - Add additional PHYs which are not supported by default into PHY profile for PHY detection and auto negotiation
+ * 
+ * @API TYPE - Public
+ * @param  phy  pointer to alt_tse_phy_profile structure describing PHY registers
+ * @return      index of PHY added in PHY profile on success, else return ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ * PHY which are currently supported by default :  Marvell 88E1111, Marvell Quad PHY 88E1145, National DP83865, and National DP83848C
+ */
+alt_32 alt_tse_phy_add_profile(alt_tse_phy_profile *phy)
+{
+    alt_32 i;
+    
+    /* search PHY profile for same ID */
+    for(i = 0; i < phy_profile_count; i++)
+    {
+        if(pphy_profiles[i]->oui == phy->oui && pphy_profiles[i]->model_number == phy->model_number)
+        {
+            tse_dprintf(4, "WARNING : PHY OUI 0x%06x, PHY Model Number 0x%02x already exist in PHY profile\n", (int) phy->oui, phy->model_number);
+            tse_dprintf(4, "In case of same PHY OUI and PHY Model Number in profile, first added PHY setting will be used\n");
+        }
+    }
+
+    /* Allocate memory space to store the profile */    
+    pphy_profiles[phy_profile_count] = (alt_tse_phy_profile *) malloc(sizeof(alt_tse_phy_profile));
+    if(!pphy_profiles[phy_profile_count]) {
+        tse_dprintf(1, "ERROR   : Unable to allocate memory for pphy_profile[%d]\n", phy_profile_count);
+        return ALTERA_TSE_MALLOC_FAILED;
+    }
+
+    /* Store PHY information */
+    *pphy_profiles[phy_profile_count] = *phy;
+    strcpy(pphy_profiles[phy_profile_count]->name, phy->name);
+    
+    phy_profile_count++;
+    
+    return phy_profile_count - 1;
+}
+
+/* @Function Description - Add TSE System to tse_mac_device[] array to customize TSE System
+ * 
+ * @API TYPE - Public
+ * @param        psys_mac  pointer to alt_tse_system_mac structure describing MAC of the system
+ * @param        psys_msgdma  pointer to alt_tse_system_msgdma structure describing MSGDMA of the system
+ * @param        psys_mem  pointer to alt_tse_system_desc_mem structure describing Descriptor Memory of the system
+ * @param        psys_phy  pointer to alt_tse_system_phy structure describing PHY of the system
+ * @return      SUCCESS on success
+ *                 ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ *                 ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL
+ */
+alt_32 alt_tse_system_add_sys(
+    alt_tse_system_mac                    *psys_mac,
+    alt_tse_system_msgdma                *psys_msgdma,
+    alt_tse_system_desc_mem                *psys_mem,
+    alt_tse_system_shared_fifo            *psys_shared_fifo,
+    alt_tse_system_phy                     *psys_phy ) {
+
+    int i;
+    int loop_end;
+    
+    alt_tse_system_mac                    *pmac    = psys_mac;
+    alt_tse_system_msgdma                *pmsgdma    = psys_msgdma;
+    alt_tse_system_desc_mem                *pmem    = psys_mem;
+    alt_tse_system_shared_fifo            *pfifo    = psys_shared_fifo;
+    alt_tse_system_phy                     *pphy    = psys_phy;
+    
+    static alt_8 tse_system_count = 0;
+    
+    /* Determine number of loop */
+    /* Run at least one for non-multi-channel MAC */
+    if(pmac->tse_num_of_channel == 0) {
+        loop_end = 1;
+    }
+    else if(pmac->tse_num_of_channel > 0) {
+        loop_end = pmac->tse_num_of_channel; 
+    }
+    else {
+        tse_dprintf(2, "ERROR   : Invalid number of channel specified!\n");
+        return ALTERA_TSE_SYSTEM_DEF_ERROR;
+    }
+
+    for(i = 0; i < loop_end; i++) {
+        
+        /* Make sure the boundary of array is not exceeded */
+        if(tse_system_count >= MAXNETS) {
+            tse_dprintf(2, "ERROR   : Number of TSE System added exceed the size of array!\n");
+            tse_dprintf(2, "ERROR   : Size of array = %d, Number of TSE System = %d\n", MAXNETS, tse_system_count);
+        }
+
+        /* Add MAC info to alt_tse_system_info structure */
+        if(pmac == 0) {
+            tse_dprintf(2, "ERROR   : MAC system structure == NULL\n");
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_system_add_sys()\n");
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+        }        
+        
+        tse_mac_device[tse_system_count].tse_mac_base                     = pmac->tse_mac_base + (i * 0x400);
+        tse_mac_device[tse_system_count].tse_tx_depth                     = pmac->tse_tx_depth;
+        tse_mac_device[tse_system_count].tse_rx_depth                     = pmac->tse_rx_depth;
+        tse_mac_device[tse_system_count].tse_use_mdio                     = pmac->tse_use_mdio;
+        tse_mac_device[tse_system_count].tse_en_maclite                 = pmac->tse_en_maclite;
+        tse_mac_device[tse_system_count].tse_maclite_gige                 = pmac->tse_maclite_gige;
+        tse_mac_device[tse_system_count].tse_multichannel_mac             = pmac->tse_multichannel_mac;
+        tse_mac_device[tse_system_count].tse_num_of_channel             = pmac->tse_num_of_channel;
+        tse_mac_device[tse_system_count].tse_mdio_shared                 = pmac->tse_mdio_shared;
+        tse_mac_device[tse_system_count].tse_number_of_mac_mdio_shared    = pmac->tse_number_of_mac_mdio_shared;
+        tse_mac_device[tse_system_count].tse_pcs_ena                     = pmac->tse_pcs_ena;
+        tse_mac_device[tse_system_count].tse_pcs_sgmii                     = pmac->tse_pcs_sgmii;
+        
+        /* Add MSGDMA info to alt_tse_system_info structure */
+        if(pmsgdma == 0) {
+            tse_dprintf(2, "ERROR   : MSGDMA system structure == NULL\n");
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_system_add_sys() for tse_mac_device[%d]\n", tse_system_count);
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+        }
+        
+        tse_mac_device[tse_system_count].tse_msgdma_tx = (char *) malloc(strlen(pmsgdma->tse_msgdma_tx) + 1);
+        if(!tse_mac_device[tse_system_count].tse_msgdma_tx) {
+            tse_dprintf(1, "ERROR   : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_tx\n", tse_system_count);
+            return ALTERA_TSE_MALLOC_FAILED;
+        }   
+        strcpy(tse_mac_device[tse_system_count].tse_msgdma_tx, pmsgdma->tse_msgdma_tx);
+        
+        tse_mac_device[tse_system_count].tse_msgdma_rx = (char *) malloc(strlen(pmsgdma->tse_msgdma_rx) + 1);
+        if(!tse_mac_device[tse_system_count].tse_msgdma_rx) {
+            tse_dprintf(1, "ERROR   : Unable to allocate memory for tse_mac_device[%d].tse_msgdma_rx\n", tse_system_count);
+            return ALTERA_TSE_MALLOC_FAILED;
+        }
+        strcpy(tse_mac_device[tse_system_count].tse_msgdma_rx, pmsgdma->tse_msgdma_rx);
+        
+        tse_mac_device[tse_system_count].tse_msgdma_rx_irq = pmsgdma->tse_msgdma_rx_irq;
+        
+        /* Add descriptor memory info to alt_tse_system_info structure */
+        if(pmem == 0) {
+            tse_mac_device[tse_system_count].ext_desc_mem    = TSE_INT_DESC_MEM;
+            tse_mac_device[tse_system_count].desc_mem_base    = TSE_INT_DESC_MEM;
+        }
+        else {
+            tse_mac_device[tse_system_count].ext_desc_mem    = pmem->ext_desc_mem;
+            tse_mac_device[tse_system_count].desc_mem_base    = pmem->desc_mem_base;
+        }
+        
+        /* Add shared fifo info to alt_tse_system_info structure */
+        if(pfifo == 0) {
+            tse_mac_device[tse_system_count].use_shared_fifo                = TSE_NO_SHARED_FIFO;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base    = TSE_NO_SHARED_FIFO;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base    = TSE_NO_SHARED_FIFO;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth       = TSE_NO_SHARED_FIFO;
+            
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base    = TSE_NO_SHARED_FIFO;
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base    = TSE_NO_SHARED_FIFO;
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth       = TSE_NO_SHARED_FIFO;
+        }
+        else {
+            tse_mac_device[tse_system_count].use_shared_fifo                = pfifo->use_shared_fifo;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_ctrl_base    = pfifo->tse_shared_fifo_tx_ctrl_base;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_stat_base    = pfifo->tse_shared_fifo_tx_stat_base;
+            tse_mac_device[tse_system_count].tse_shared_fifo_tx_depth       = pfifo->tse_shared_fifo_tx_depth;
+            
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_ctrl_base    = pfifo->tse_shared_fifo_rx_ctrl_base;
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_stat_base    = pfifo->tse_shared_fifo_rx_stat_base;
+            tse_mac_device[tse_system_count].tse_shared_fifo_rx_depth       = pfifo->tse_shared_fifo_rx_depth;
+        }
+        
+        /* Add PHY info to alt_tse_system_info structure */
+        if(pphy == 0) {
+            tse_mac_device[tse_system_count].tse_phy_mdio_address    = TSE_PHY_AUTO_ADDRESS;
+            tse_mac_device[tse_system_count].tse_phy_cfg             = 0;
+        }
+        else {
+            tse_mac_device[tse_system_count].tse_phy_mdio_address    = pphy->tse_phy_mdio_address;
+            tse_mac_device[tse_system_count].tse_phy_cfg             = pphy->tse_phy_cfg;
+        }
+        
+        /* Point to next structure */
+        pmsgdma++;
+        if(pmem) pmem++;
+        if(pfifo) pfifo++;
+        if(pphy) pphy++;
+        
+        tse_system_count++;
+        max_mac_system = tse_system_count;
+    }
+    
+    return SUCCESS;
+    
+}
+
+/* @Function Description - Enable MDIO sharing for multiple single channel MAC
+ * 
+ * @API TYPE - Public
+ * @param        psys_mac_list  pointer to array of alt_tse_system_mac structure sharing MDIO block
+ * @param        number_of_mac  number of MAC sharing MDIO block
+ * @return      SUCCESS on success
+ *                 ALTERA_TSE_SYSTEM_DEF_ERROR if definition of system incorrect or pointer == NULL
+ * Multi-channel MAC not supported
+ */
+alt_32 alt_tse_sys_enable_mdio_sharing(alt_tse_system_mac **psys_mac_list, alt_u8 number_of_mac) {
+    alt_32 i;
+    alt_32 j;
+    
+    alt_tse_system_mac *psys_mac;
+    
+    for(i = 0; i < number_of_mac; i++) {
+        psys_mac = psys_mac_list[i];
+        
+        if(psys_mac == 0) {
+            tse_dprintf(2, "ERROR   : MAC system structure == NULL\n");
+            tse_dprintf(2, "ERROR   : Please pass in correct pointer to alt_tse_sys_enable_mdio_sharing()\n");
+            return ALTERA_TSE_SYSTEM_DEF_ERROR;
+        }
+        
+        for(j = 0; j < max_mac_system; j++) {
+            
+            if(psys_mac->tse_mac_base == tse_mac_device[j].tse_mac_base) {
+                if(tse_mac_device[j].tse_multichannel_mac) {
+                    tse_dprintf(2, "ERROR   : MDIO sharing supported by default for Multi-channel MAC\n");
+                    tse_dprintf(2, "ERROR   : Do not include Multi-channel MAC in the MAC List\n");
+                    return ALTERA_TSE_SYSTEM_DEF_ERROR;
+                }
+                
+                tse_mac_device[j].tse_mdio_shared = 1;
+                tse_mac_device[j].tse_number_of_mac_mdio_shared = number_of_mac;
+            }
+        }    
+    }
+    
+    return SUCCESS;
+}
+
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Public
+ * @param pmac          Pointer to the TSE MAC Control Interface Base address
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_mac_get_common_speed(np_tse_mac *pmac) {
+    alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group;
+    return alt_tse_phy_get_common_speed(pmac_group);
+}
+
+/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group
+ * @API Type:               Public
+ * @param pmac              Pointer to the TSE MAC Control Interface Base address
+ *        common_speed      common speed supported by all PHYs
+ * @return                  common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_speed) {
+    alt_tse_mac_group *pmac_group = alt_tse_get_mac_info(pmac)->pmac_group;
+    return alt_tse_phy_set_common_speed(pmac_group, common_speed);
+}
+
+
+/********************************
+ *
+ * Internal API for TSE Driver 
+ *
+ *******************************/
+
+/* @Function Description: Get the index of alt_tse_system_info structure in tse_mac_device[]
+ * @API Type:        Internal
+ * @param psys_info  Pointer to the alt_tse_system_info structure
+ * @return           Index of alt_tse_system_info structure in tse_mac_device[]
+ */
+alt_32 alt_tse_get_system_index(alt_tse_system_info *psys_info) {
+    alt_32 i;
+    
+    for(i = 0; i < max_mac_system; i++) {
+        if(psys_info == &tse_mac_device[i]) {
+            return i;
+        }
+    }
+    return ALTERA_TSE_NO_INDEX_FOUND;
+}
+
+/* @Function Description: Get the index of alt_tse_mac_group structure in pmac_groups[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_group structure
+ * @return            Index of alt_tse_mac_group structure in pmac_groups[]
+ */
+alt_32 alt_tse_get_mac_group_index(alt_tse_mac_group *pmac_group) {
+    alt_32 i;
+    
+    for(i = 0; i < mac_group_count; i++) {
+        if(pmac_group == pmac_groups[i]) {
+            return i;
+        }
+    }
+    return ALTERA_TSE_NO_INDEX_FOUND;
+}
+
+
+/* @Function Description: Get the index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the alt_tse_mac_info structure
+ * @return            Index of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_32 alt_tse_get_mac_info_index(alt_tse_mac_info *pmac_info) {
+    alt_32 i;
+    
+    for(i = 0; i < pmac_info->pmac_group->channel; i++) {
+        if(pmac_info == pmac_info->pmac_group->pmac_info[i]) {
+            return i;
+        }
+    }
+    
+    return ALTERA_TSE_NO_INDEX_FOUND;
+}
+
+/* @Function Description: Get the pointer of alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ * @API Type:         Internal
+ * @param pmac        Pointer to the TSE MAC Control Interface Base address
+ * @return            Pointer to alt_tse_mac_info structure in pmac_groups[]->pmac_info[]
+ */
+alt_tse_mac_info *alt_tse_get_mac_info(np_tse_mac *pmac) {
+    alt_32 i;
+    alt_32 j;
+    alt_tse_mac_group *pmac_group = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    
+    for(i = 0; i < mac_group_count; i++) {
+        pmac_group = pmac_groups[i];
+        for(j = 0; j < pmac_group->channel; j++) {
+            pmac_info = pmac_group->pmac_info[j];
+            if(((np_tse_mac *) pmac_info->psys_info->tse_mac_base) == pmac) {
+                return pmac_info;
+            }
+        }        
+    }
+    
+    return 0;
+}
+    
+/* @Function Description: Perform switching of the TSE MAC speed.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Internal
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param speed 2 = 1000 Mbps, 1 = 100 Mbps, 0 = 10 Mbps
+ * @return ENP_PARAM if invalid speed specified, else return SUCCESS
+ */
+alt_32 alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed)
+{
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+  
+  /* 1000 Mbps */
+  if(speed == TSE_PHY_SPEED_1000) {
+    helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  /* 100 Mbps */
+  else if(speed == TSE_PHY_SPEED_100) {
+    helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    helpvar &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  /* 10 Mbps */
+  else if(speed == TSE_PHY_SPEED_10) {
+    helpvar &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    helpvar |= ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }  
+  else {
+    return ENP_PARAM;
+  }
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar);
+  return SUCCESS;
+}
+
+/* @Function Description: Perform switching of the TSE MAC duplex mode.
+ *                        COMMAND_CONFIG register is restored after reset.
+ * @API Type:   Internal
+ * @param pmac  Pointer to the TSE MAC Control Interface Base address
+ * @param duplex 1 = Full Duplex, 0 = Half Duplex
+ * @return ENP_PARAM if invalid duplex specified, else return SUCCESS
+ */
+alt_32 alt_tse_mac_set_duplex(np_tse_mac *pmac, alt_u8 duplex)
+{
+  alt_32 helpvar;
+  
+  helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
+  
+  /* Half Duplex */
+  if(duplex == TSE_PHY_DUPLEX_HALF) {
+    helpvar |= ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+  } 
+  /* Full Duplex */
+  else if(duplex == TSE_PHY_DUPLEX_FULL) {
+    helpvar &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+  }
+  else {
+    return ENP_PARAM;
+  }
+  
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac, helpvar);
+  return SUCCESS;
+
+}
+
+
+
+/** @Function Description -  Determine link speed our PHY negotiated with our link partner.
+  *                          This is fully vendor specific depending on the PHY you are using.
+  * 
+  * @API TYPE - Internal
+  * @param  tse.mi.base MAC register map.
+  * @return 
+  * ----------------------------------------------------------------------------------
+  * |  BIT  | Value: Description                                                     |
+  * ----------------------------------------------------------------------------------
+  * | 31-23 | Reserved                                                               |
+  * |   23  | 1: Argument *pmac not found from the list of MAC detected during init  |
+  * |   22  | 1: No MDIO used by the MAC                                             |
+  * |   21  | 1: No PHY detected                                                     |
+  * |   20  | 1: No common speed found for Multi-port MAC                            |
+  * |   19  | 1: PHY auto-negotiation not completed                                  |
+  * |   18  | 1: No PHY profile match the detected PHY                               |
+  * |   17  | 1: PHY Profile not defined correctly                                   |
+  * |   16  | 1: Invalid speed read from PHY                                         |
+  * |  4-15 | Reserved                                                               |
+  * |    3  | 1: 10 Mbps link                                                        |
+  * |    2  | 1: 100 Mbps link                                                       |
+  * |    1  | 1: 1000 Mbps link                                                      |
+  * |    0  | 1: Full Duplex                    0: Half Duplex                       |
+  * ----------------------------------------------------------------------------------
+  * 
+  * If the link speed cannot be determined, it is fall back to 100 Mbps (customizable by changing ALTERA_TSE_MAC_SPEED_DEFAULT)
+  *                                         Full duplex (customizable by changing ALTERA_TSE_DUPLEX_MODE_DEFAULT)
+  */
+
+#define ALT_TSE_SPEED_DUPLEX(speed, duplex) ((duplex & 0x01) |\
+      (((speed == TSE_PHY_SPEED_1000) ? 1 : 0) << 1) |   \
+    (((speed == TSE_PHY_SPEED_100) ? 1 : 0) << 2) |     \
+    (((speed == TSE_PHY_SPEED_10) ? 1 : 0) << 3) |      \
+    ((speed == TSE_PHY_SPEED_INVALID) ? ALT_TSE_E_INVALID_SPEED : 0))
+  
+alt_32 getPHYSpeed(np_tse_mac *pmac) {
+
+    alt_u8 speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+    alt_u8 duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;     /* 1 = full ; 0 = half*/
+    alt_32 result = ALT_TSE_SPEED_DUPLEX(speed, duplex);
+    
+    alt_tse_phy_info *pphy = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    alt_tse_mac_group *pmac_group = 0;
+    alt_tse_system_info *psys = 0;
+    
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+    alt_8 mac_group_index = 0;
+    
+    /* initialized PHYs only once */
+    static alt_u8 is_init = 0;
+    if(is_init == 0) {
+        alt_tse_phy_init();
+        is_init = 1;
+    }
+    
+    /* Look for pmac_group and pmac_info structure based on pmac or iface */
+    pmac_info = alt_tse_get_mac_info(pmac);
+    
+    if(pmac_info == 0) {
+        speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+        duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+        result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PMAC_FOUND;
+        tse_dprintf(2, "ERROR   : [getPHYSpeed] pmac not found from list of pmac_info[]! Speed = %s Mbps, Duplex = %s\n", speed == TSE_PHY_SPEED_1000 ? "1000" :
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+        tse_dprintf(2, "ERROR   : [getPHYSpeed] Please define tse_mac_device[] correctly\n");
+        return result;
+    }
+    
+    pphy = pmac_info->pphy_info;
+    pmac_group = pmac_info->pmac_group;
+    psys = pmac_info->psys_info;
+    
+    mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+         
+    /* MDIO is not used */
+    if (pmac_group->pmac_info[0]->psys_info->tse_use_mdio == 0)
+    {
+        speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+        duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+        result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_MDIO;
+        usleep(ALTERA_NOMDIO_TIMEOUT_THRESHOLD);
+        if(psys->tse_phy_cfg) {
+            tse_dprintf(4, "WARNING : PHY[%d.%d] - MDIO not enabled! Running user configuration...\n", mac_group_index, mac_info_index);
+            result = psys->tse_phy_cfg(pmac);
+        }
+        else {
+            tse_dprintf(4, "WARNING : MAC Group[%d] - MDIO not enabled! Speed = %s, Duplex = %s\n", mac_group_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+        }
+        return result;
+    }
+
+    /* Not running simulation */
+    #ifndef ALT_SIM_OPTIMIZE
+    
+        /* These variables declaration are here to avoid "warning: unused variable" message when compile for simulation */
+        np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    
+        /* if no PHY connected to the MAC */
+        if(pphy == 0) {
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY;
+            tse_dprintf(2, "ERROR   : PHY[%d.%d] - No PHY connected! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+            return result;
+        }
+
+        /* Small MAC */
+        if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) {
+            alt_tse_phy_set_adv_1000(pphy, 0);
+            alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+        }
+        else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) {
+            alt_tse_phy_set_adv_100(pphy, 0);
+            alt_tse_phy_set_adv_10(pphy, 0);
+            alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+        }
+        
+        /* check link connection for this PHY */
+        if(alt_tse_phy_check_link(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD) == TSE_PHY_AN_NOT_COMPLETE) {
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_AN_NOT_COMPLETE;
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - Auto-Negotiation not completed! Speed = %s, Duplex = %s\n", mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+                                                                             speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                             speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                             duplex == 1 ? "Full" : "Half");
+            return result;
+        }
+
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, pphy->mdio_address);
+
+        /* To enable PHY loopback */
+        #if ENABLE_PHY_LOOPBACK
+            tse_dprintf(5, "INFO    : PHY[%d.%d] - Putting PHY in loopback\n", mac_group_index, mac_info_index);
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 1);   // enable PHY loopback
+        #else
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0);   // disable PHY loopback
+        #endif
+       
+        /* if PHY not found in profile */
+        if(pphy->pphy_profile == 0) {
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not found in PHY profile\n", mac_group_index, mac_info_index);
+            speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+            duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+            result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_NO_PHY_PROFILE;
+        }
+        // retrieve duplex information from PHY
+        else
+        {
+            if(pphy->pphy_profile->link_status_read)
+            {
+                result = pphy->pphy_profile->link_status_read(pmac_group_base);
+                speed = (result & 0x02) ? TSE_PHY_SPEED_1000 :
+                        (result & 0x04) ? TSE_PHY_SPEED_100  :
+                        (result & 0x08) ? TSE_PHY_SPEED_10  : TSE_PHY_SPEED_INVALID;
+                duplex = (result & 0x01) ? TSE_PHY_DUPLEX_FULL : TSE_PHY_DUPLEX_HALF;
+                
+                if(result & ALT_TSE_E_INVALID_SPEED)
+                {
+                    tse_dprintf(3, "WARNING : PHY[%d.%d] - Invalid speed read from PHY\n", mac_group_index, mac_info_index);
+                }
+            }
+            else if(pphy->pphy_profile->status_reg_location == 0)
+            {
+                tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY Specific Status register information not provided in profile\n", mac_group_index, mac_info_index);
+                speed = ALTERA_TSE_MAC_SPEED_DEFAULT;
+                duplex = ALTERA_TSE_DUPLEX_MODE_DEFAULT;
+                result = ALT_TSE_SPEED_DUPLEX(speed, duplex) | ALT_TSE_E_PROFILE_INCORRECT_DEFINED;
+            }
+            else
+            {
+                /* extract connection speed and duplex information */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2);
+                duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1);
+                
+                result = ALT_TSE_SPEED_DUPLEX(speed, duplex);
+            }
+        }
+
+    #else
+        /* for simulation purpose, default to gigabit mode */
+        speed = 1;
+        duplex = 1;
+    #endif
+
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Speed = %s, Duplex = %s\n",  mac_group_index, mac_info_index, speed == TSE_PHY_SPEED_1000 ? "1000" :
+                                                                                 speed == TSE_PHY_SPEED_100 ? "100" :
+                                                                                 speed == TSE_PHY_SPEED_10 ? "10" : "Unknown",
+                                                                                 duplex == 1 ? "Full" : "Half");
+
+    return result;
+}
+
+
+/* @Function Description: Read MDIO address from the MDIO address1 register of first MAC within MAC group
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_rd_mdio_addr(alt_tse_phy_info *pphy) {
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    return IORD(&pmac_group_base->MDIO_ADDR1, 0);
+}
+
+
+/* @Function Description: Write MDIO address to the MDIO address1 register of first MAC within MAC group
+ * @API Type:           Internal
+ * @param pmac          Pointer to the alt_tse_phy_info structure
+ * @param mdio_address  MDIO address to be written
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_wr_mdio_addr(alt_tse_phy_info *pphy, alt_u8 mdio_address) {
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdio_address);
+    
+    return SUCCESS;
+}
+
+/** @Function Description -  Write value of data with bit_length number of bits to MDIO register based on register location reg_num
+  *                          and start from bit location lsb_num.
+  * 
+  * @API TYPE - Internal
+  * @param  pphy             pointer to alt_tse_phy_info structure
+  * @param  reg_num          location of MDIO register to be written.
+  * @param  lsb_num          least significant bit location of MDIO register to be written.
+  * @param  bit_length       number of bits to be written to the register.
+  * @param  data             data to be written to the register at specific bit location of register.
+  * @return SUCCESS 
+  */
+alt_32 alt_tse_phy_wr_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length, alt_u16 data)
+{
+    
+    alt_u16 temp_data;
+    alt_u16 bit_mask;
+    alt_32 i;
+    np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    
+    bit_mask = 0x00;
+    /* generate mask consist of bit_length number of 1
+     * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111
+     */
+    for(i = 0; i < bit_length; i++)
+    {
+        bit_mask <<= 1;
+        bit_mask |= 0x01;        
+    }
+    
+    /* shifting mask to left by bit_num */
+    bit_mask <<= lsb_num;
+
+    /* read register data */
+    temp_data = IORD(&pmac->mdio1, reg_num);
+    
+    /* clear bits to be written */
+    temp_data &= ~bit_mask;
+    
+    /* OR-ed together corresponding bits data */
+    temp_data |= ((data << lsb_num) & bit_mask);    
+    
+    /* write data to MDIO register */
+    IOWR(&pmac->mdio1, reg_num, temp_data);
+    
+    return SUCCESS;
+    
+}
+
+
+
+/* @Function Description -  Read bit_length number of bits from MDIO register based on register location reg_num
+ *                          and start from bit location lsb_num.
+ * 
+ * @API TYPE - Internal
+ * @param  pphy             pointer to alt_tse_phy_info structure
+ * @param  reg_num          location of MDIO register to be read.
+ * @param  lsb_num          least significant bit location of MDIO register to be read.
+ * @param  bit_length       number of bits to be read from the register.
+ * @return data read from MDIO register 
+ */
+
+alt_u32 alt_tse_phy_rd_mdio_reg(alt_tse_phy_info *pphy, alt_u8 reg_num, alt_u8 lsb_num, alt_u8 bit_length)
+{
+    alt_u16 temp_data;
+    alt_u32 bit_mask;
+    alt_32 i;
+    np_tse_mac *pmac = (np_tse_mac *) pphy->pmac_info->pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    
+    bit_mask = 0x00;
+    /* generate mask consist of bit_length number of 1
+     * eg: bit_length = 3, bit_mask = 0b0000 0000 0000 0111
+     */
+    for(i = 0; i < bit_length; i++)
+    {
+        bit_mask <<= 1;
+        bit_mask |= 0x01;        
+    }
+    
+    /* read register data */
+    temp_data = IORD(&pmac->mdio1, reg_num);
+    
+    /* shifting read data */
+    temp_data >>= lsb_num;
+    
+    return (temp_data & bit_mask);
+}
+
+
+
+/* @Function Description: Add supported PHY to profile
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ * 
+ * User might add their own PHY by calling alt_tse_phy_add_profile()
+ */
+alt_32 alt_tse_phy_add_profile_default() {
+    
+    /* supported PHY definition */
+        
+    /* ------------------------------ */
+    /* Marvell PHY on PHYWORKX board  */
+    /* ------------------------------ */
+    
+    alt_tse_phy_profile MV88E1111 = {"Marvell 88E1111",      /* Marvell 88E1111                                  */
+                            MV88E1111_OUI,          /* OUI                                                           */
+                            MV88E1111_MODEL,        /* Vender Model Number                                           */
+                            MV88E1111_REV,          /* Model Revision Number                                         */
+                            0x11,                   /* Location of Status Register                                   */
+                            14,                     /* Location of Speed Status                                      */
+                            13,                     /* Location of Duplex Status                                     */
+                            10,                     /* Location of Link Status                                       */
+                            &marvell_phy_cfg        /* Function pointer to configure Marvell PHY                     */
+                           };
+
+    
+    /* ---------------------------------- */
+    /* Marvell Quad PHY on PHYWORKX board */
+    /* ---------------------------------- */
+    
+    alt_tse_phy_profile MV88E1145 = {"Marvell Quad PHY 88E1145",      /* Marvell 88E1145                                  */
+                            MV88E1145_OUI,                   /* OUI                                                           */
+                            MV88E1145_MODEL,                 /* Vender Model Number                                           */
+                            MV88E1145_REV,                   /* Model Revision Number                                         */
+                            0x11,                            /* Location of Status Register                                   */
+                            14,                              /* Location of Speed Status                                      */
+                            13,                              /* Location of Duplex Status                                     */
+                            10,                              /* Location of Link Status                                       */
+                            &marvell_phy_cfg                 /* Function pointer to configure Marvell PHY                     */
+                           };
+                      
+    /* ------------------------------ */
+    /* National PHY on PHYWORKX board */
+    /* ------------------------------ */  
+    
+    alt_tse_phy_profile DP83865 = {"National DP83865",     /* National DP83865                                 */
+                          DP83865_OUI,            /* OUI                                              */
+                          DP83865_MODEL,          /* Vender Model Number                              */
+                          DP83865_REV,            /* Model Revision Number                            */
+                          0x11,                   /* Location of Status Register                      */
+                          3,                      /* Location of Speed Status                         */
+                          1,                      /* Location of Duplex Status                        */
+                          2                       /* Location of Link Status                          */
+                         };
+                      
+    /* -------------------------------------- */
+    /* National 10/100 PHY on PHYWORKX board  */
+    /* -------------------------------------- */ 
+                      
+    alt_tse_phy_profile DP83848C = {"National DP83848C",  /* National DP83848C                                          */
+                           DP83848C_OUI,                   /* OUI                                                        */
+                           DP83848C_MODEL,                 /* Vender Model Number                                        */
+                           DP83848C_REV,                   /* Model Revision Number                                      */
+                           0,                              /* Location of Status Register (ignored)                      */
+                           0,                              /* Location of Speed Status    (ignored)                      */
+                           0,                              /* Location of Duplex Status   (ignored)                      */
+                           0,                              /* Location of Link Status     (ignored)                      */
+                           0,                              /* No function pointer configure National DP83848C            */
+                           &DP83848C_link_status_read      /* Function pointer to read from PHY specific status register */           
+                          };
+
+    /* -------------------------------------- */
+    /* Intel PHY on C10LP EVA board  */
+    /* -------------------------------------- */ 
+                      
+    alt_tse_phy_profile PEF7071 = {"Intel PEF7071",       /* National DP83848C                                          */
+                           PEF7071_OUI,                   /* OUI                                                        */
+                           PEF7071_MODEL,                 /* Vender Model Number                                        */
+                           PEF7071_REV,                   /* Model Revision Number                                      */
+                           0,                             /* Location of Status Register                                */
+                           0,                             /* Location of Speed Status                                   */
+                           0,                             /* Location of Duplex Status                                  */
+                           0,                             /* Location of Link Status                                    */
+                           &PEF7071_config,               /* configure PEF7071                                          */
+                           &PEF7071_link_status_read      /* Function pointer to read from PHY specific status register */           
+                          };
+                      
+    /* add supported PHY to profile */                          
+    alt_tse_phy_add_profile(&MV88E1111);
+    alt_tse_phy_add_profile(&MV88E1145);
+    alt_tse_phy_add_profile(&DP83865);
+    alt_tse_phy_add_profile(&DP83848C);
+    alt_tse_phy_add_profile(&PEF7071);
+    
+    
+    return phy_profile_count;
+}
+
+/* @Function Description: Display PHYs available in profile
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      Number of PHY in profile
+ */
+alt_32 alt_tse_phy_print_profile() {
+   
+    alt_8 i;
+    /* display PHY in profile */
+    tse_dprintf(6, "List of PHY profiles supported (Total profiles = %d)...\n", phy_profile_count);
+    
+    for(i = 0; i < phy_profile_count; i++)
+    {
+        tse_dprintf(6, "Profile No.%2d   :\n", i);
+        tse_dprintf(6, "PHY Name        : %s\n", pphy_profiles[i]->name);
+   
+        tse_dprintf(6, "PHY OUI         : 0x%06x\n", (int)pphy_profiles[i]->oui);
+        tse_dprintf(6, "PHY Model Num.  : 0x%02x\n", pphy_profiles[i]->model_number);
+        tse_dprintf(6, "PHY Rev. Num.   : 0x%02x\n", pphy_profiles[i]->revision_number);
+        
+        tse_dprintf(6, "Status Register : 0x%02x\n", pphy_profiles[i]->status_reg_location); 
+        
+        tse_dprintf(6, "Speed Bit       : %d\n", pphy_profiles[i]->speed_lsb_location);
+        
+        tse_dprintf(6, "Duplex Bit      : %d\n", pphy_profiles[i]->duplex_bit_location);
+        
+        tse_dprintf(6, "Link Bit        : %d\n\n", pphy_profiles[i]->link_bit_location);
+ 
+    }
+    
+    return phy_profile_count;
+}
+
+
+
+/* @Function Description: Store information of all the MAC available in the system
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      return SUCCESS
+ *              return ALTERA_TSE_SYSTEM_DEF_ERROR if alt_tse_system_info structure definition error
+ */
+alt_32 alt_tse_mac_group_init() {
+    
+    alt_8 i;
+    alt_8 j;
+    
+    alt_tse_mac_group *pmac_group = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    alt_tse_system_info *psys = 0;
+
+    /* reset number of MAC group */
+    mac_group_count = 0;
+    
+    /* loop through every alt_tse_system_info structure */
+    for(i = 0; i < max_mac_system; i++) {
+        psys = &tse_mac_device[i];
+
+        if((psys->tse_msgdma_tx != 0) && (psys->tse_msgdma_rx != 0)) {        
+            tse_dprintf(5, "INFO    : TSE MAC %d found at address 0x%08x\n", mac_group_count, (int) psys->tse_mac_base);
+            
+            /* Allocate memory for the structure */
+            pmac_group = (alt_tse_mac_group *) malloc(sizeof(alt_tse_mac_group));
+            if(!pmac_group) {
+                tse_dprintf(1, "ERROR   : Unable to allocate memory for MAC Group[%d]\n", mac_group_count);
+                return ALTERA_TSE_MALLOC_FAILED;
+            }
+           
+            /* Non-multi-channel MAC considered as 1 channel */
+            if(psys->tse_multichannel_mac) {
+                pmac_group->channel = psys->tse_num_of_channel;
+                tse_dprintf(6, "INFO    : Multi Channel            = Yes\n");
+                tse_dprintf(6, "INFO    : Number of channel        = %d\n", pmac_group->channel);
+                tse_dprintf(6, "INFO    : MDIO Shared              = Yes\n");
+            }
+            else if(psys->tse_mdio_shared) {
+                pmac_group->channel = psys->tse_number_of_mac_mdio_shared;
+                tse_dprintf(6, "INFO    : Multi Channel            = No\n");
+                tse_dprintf(6, "INFO    : MDIO Shared              = Yes\n");
+                tse_dprintf(6, "INFO    : Number of MAC Share MDIO = %d\n", pmac_group->channel);
+            }
+            else {
+                pmac_group->channel = 1;
+                tse_dprintf(6, "INFO    : Multi Channel            = No\n");
+                tse_dprintf(6, "INFO    : MDIO Shared              = No\n");
+            }
+            
+            for(j = 0; j < pmac_group->channel; j++) {
+                /* Allocate memory for the structure */
+                pmac_info = (alt_tse_mac_info *) malloc(sizeof(alt_tse_mac_info));
+                if(!pmac_info) {
+                    tse_dprintf(1, "ERROR   : Unable to allocate memory for MAC Group[%d]->pmac_info[%d]\n", mac_group_count, j);
+                    return ALTERA_TSE_MALLOC_FAILED;
+                }
+                
+                pmac_info->pmac_group = pmac_group;
+                
+                pmac_info->pphy_info = 0;
+                
+                pmac_info->psys_info = &tse_mac_device[i + j];
+                
+                /* check to make sure the alt_tse_system_info defined correctly or has been defined */
+                if((pmac_info->psys_info->tse_msgdma_tx == 0) || (pmac_info->psys_info->tse_msgdma_rx == 0)){                    
+                    tse_dprintf(2, "ERROR   : tse_mac_device[%d] does not defined correctly!\n", i + j);
+                    return ALTERA_TSE_SYSTEM_DEF_ERROR;
+                }
+                
+                /* MAC type detection */
+                if(pmac_info->psys_info->tse_en_maclite) {
+                    if(pmac_info->psys_info->tse_maclite_gige) {
+                        pmac_info->mac_type = ALTERA_TSE_MACLITE_1000;
+                    }
+                    else {
+                        pmac_info->mac_type = ALTERA_TSE_MACLITE_10_100;
+                    }
+                }
+                else {
+                    pmac_info->mac_type = ALTERA_TSE_FULL_MAC;                    
+                }
+                
+                if((pmac_info->psys_info->tse_mdio_shared) && (!pmac_info->psys_info->tse_multichannel_mac)){
+                    tse_dprintf(6, "INFO    : MAC %2d Address           = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base);
+                    tse_dprintf(6, "INFO    : MAC %2d Device            = tse_mac_device[%d]\n", j, i + j);
+                    
+                    switch(pmac_info->mac_type) {
+                        case ALTERA_TSE_MACLITE_1000:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "1000 Mbps Small MAC");
+                            break;
+                        case ALTERA_TSE_MACLITE_10_100:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "10/100 Mbps Small MAC");
+                            break;
+                        case ALTERA_TSE_FULL_MAC:
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "10/100/1000 Ethernet MAC");
+                            break;
+                        default :
+                            tse_dprintf(6, "INFO    : MAC %2d Type              = %s\n", j, "Unknown");
+                            break;
+                    }
+                    
+                    if(pmac_info->psys_info->tse_pcs_ena) {
+                        tse_dprintf(6, "INFO    : PCS %2d Enable            = %s\n", j, pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No");
+                        tse_dprintf(6, "INFO    : PCS %2d SGMII Enable      = %s\n", j, pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No");                        
+                    }
+                }
+                else {
+                    /* display only once for all MAC, except shared MDIO MACs */
+                    if(j == 0) {
+                        switch(pmac_info->mac_type) {
+                            case ALTERA_TSE_MACLITE_1000:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "1000 Mbps Small MAC");
+                                break;
+                            case ALTERA_TSE_MACLITE_10_100:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "10/100 Mbps Small MAC");
+                                break;
+                            case ALTERA_TSE_FULL_MAC:
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "10/100/1000 Ethernet MAC");
+                                break;
+                            default :
+                                tse_dprintf(6, "INFO    : MAC Type                 = %s\n", "Unknown");
+                                    break;
+                }
+                        
+                        if(pmac_info->psys_info->tse_pcs_ena) {
+                            tse_dprintf(6, "INFO    : PCS Enable               = %s\n", pmac_info->psys_info->tse_pcs_ena ? "Yes" : "No");
+                            tse_dprintf(6, "INFO    : PCS SGMII Enable         = %s\n", pmac_info->psys_info->tse_pcs_sgmii ? "Yes" : "No");                            
+                        }
+                    }
+                    
+                    if(pmac_info->psys_info->tse_multichannel_mac) {
+                        tse_dprintf(6, "INFO    : Channel %2d Address       = 0x%08x\n", j, (int) pmac_info->psys_info->tse_mac_base);
+                        tse_dprintf(6, "INFO    : Channel %2d Device        = tse_mac_device[%d]\n", j, i + j);
+                    }                
+                    else {
+                        tse_dprintf(6, "INFO    : MAC Address              = 0x%08x\n", (int) pmac_info->psys_info->tse_mac_base);
+                        tse_dprintf(6, "INFO    : MAC Device               = tse_mac_device[%d]\n", i + j);
+                    }
+                }
+                
+                /* store the pointer in MAC group variable for the detected channel */
+                pmac_group->pmac_info[j] = pmac_info;
+            }
+            
+            /* store the pointer in global variable */
+            pmac_groups[mac_group_count] = pmac_group;
+            
+            mac_group_count++;
+
+            /* skip for subsequent Multi-channel MAC */
+            i += (pmac_group->channel - 1);
+                        
+        }
+    }
+    return SUCCESS;
+}
+
+
+/* @Function Description: Store information of all the PHYs connected to MAC to phy_list
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @return            Number of PHY not in profile, return ALTERA_TSE_MALLOC_FAILED if memory allocation failed
+ */
+alt_32 alt_tse_mac_get_phy(alt_tse_mac_group *pmac_group) {
+    
+    alt_32 phyid; 
+    alt_32 phyid2 = 0;
+    alt_u8 phyadd;
+    
+    alt_u32 oui;
+    alt_u8 model_number;
+    alt_u8 revision_number;
+
+    alt_32 i;
+
+    alt_u8 is_phy_in_profile;
+    alt_32 return_value = 0;
+    
+    alt_8 phy_info_count = 0;
+    
+    alt_tse_phy_info *pphy = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    alt_tse_system_info *psys = 0;
+    
+    np_tse_mac *pmac_group_base = (np_tse_mac *) pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+            
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0);
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* loop all valid PHY address to look for connected PHY */
+    for (phyadd = 0x00; phyadd < pmac_group->channel /*0x20*/; phyadd++)	//M.D. 2019-08-05: don't look at unused PHYs
+    {
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, phyadd);
+        phyid = IORD(&pmac_group_base->mdio1.PHY_ID1,0);     // read PHY ID
+        phyid2 = IORD(&pmac_group_base->mdio1.PHY_ID2,0);     // read PHY ID
+        
+        /* PHY found */
+        if (phyid != phyid2)
+        {
+            pphy = (alt_tse_phy_info *) malloc(sizeof(alt_tse_phy_info));
+            if(!pphy) {
+                tse_dprintf(1, "ERROR   : Unable to allocate memory for phy_info[%d.%d]\n", mac_group_index, phy_info_count);
+                return ALTERA_TSE_MALLOC_FAILED;
+            }
+            
+            /* store PHY address */
+            pphy->mdio_address = phyadd;
+
+            /* get oui, model number, and revision number from PHYID and PHYID2 */
+            oui = (phyid << 6) | ((phyid2 >> 10) & 0x3f);
+            model_number = (phyid2 >> 4) & 0x3f;
+            revision_number = phyid2 & 0x0f;
+            
+            /* map the PHY with PHY in profile */
+            is_phy_in_profile = 0;
+            for(i = 0; i < phy_profile_count; i++) {
+                
+                /* if PHY match with PHY in profile */
+                if((pphy_profiles[i]->oui == oui) && (pphy_profiles[i]->model_number == model_number))
+                {
+                    pphy->pphy_profile = pphy_profiles[i];
+                    
+                    /* PHY found, add it to phy_list */
+                    tse_dprintf(5, "INFO    : PHY %s found at PHY address 0x%02x of MAC Group[%d]\n", pphy_profiles[i]->name, phyadd, mac_group_index);
+                    is_phy_in_profile = 1;
+                    break;
+                }
+            }
+            /* PHY not found in PHY profile */
+            if(is_phy_in_profile == 0) {
+                pphy->pphy_profile = 0;
+                tse_dprintf(3, "WARNING : Unknown PHY found at PHY address 0x%02x of MAC Group[%d]\n", phyadd, mac_group_index);
+                tse_dprintf(3, "WARNING : Please add PHY information to PHY profile\n");
+                return_value++;
+            }
+            
+            tse_dprintf(6, "INFO    : PHY OUI             =  0x%06x\n", (int) oui);
+            tse_dprintf(6, "INFO    : PHY Model Number    =  0x%02x\n", model_number);
+            tse_dprintf(6, "INFO    : PHY Revision Number =  0x%01x\n", revision_number);
+            
+            /* map the detected PHY to connected MAC */
+            if(alt_tse_mac_associate_phy(pmac_group, pphy) == TSE_PHY_MAP_SUCCESS) {
+                
+                pmac_info = pphy->pmac_info;
+                psys = pmac_info->psys_info;
+                
+                /* Disable PHY loopback to allow Auto-Negotiation completed */
+                alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1, 0);   // disable PHY loopback
+                
+                /* Reset auto-negotiation advertisement */
+                alt_tse_phy_set_adv_1000(pphy, 1);
+                alt_tse_phy_set_adv_100(pphy, 1);
+                alt_tse_phy_set_adv_10(pphy, 1);
+                                
+                /* check link connection for this PHY */
+                alt_tse_phy_restart_an(pphy, ALTERA_CHECKLINK_TIMEOUT_THRESHOLD);
+                
+                /* Perform additional setting if there is any */
+                /* Profile specific */
+                if(pphy->pphy_profile) {
+                    if(pphy->pphy_profile->phy_cfg) {
+                        tse_dprintf(6, "INFO    : Applying additional PHY configuration of %s\n", pphy->pphy_profile->name);
+                        pphy->pphy_profile->phy_cfg(pmac_group_base);
+                    }
+                }
+                
+                /* Initialize PHY, call user's function pointer in alt_tse_system_info structure */
+                /* Individual PHY specific */
+                if(psys->tse_phy_cfg) {
+                    tse_dprintf(6, "INFO    : Applying additional user PHY configuration\n");
+                    psys->tse_phy_cfg(pmac_group_base);
+                }
+            }
+            
+            tse_dprintf(6, "\n");
+                
+            phy_info_count++;
+        }
+    }
+    
+    TK_SLEEP(100);	//Wait a little bit for PHY reset after specific configuration
+
+
+    /* check to verify the number of connected PHY match the number of channel */
+    if(pmac_group->channel != phy_info_count) {
+        if(phy_info_count == 0) {
+            tse_dprintf(2, "ERROR   : MAC Group[%d] - No PHY connected!\n", mac_group_index);
+        }
+        else {
+            tse_dprintf(3, "WARNING : MAC Group[%d] - Number of PHY connected is not equal to the number of channel, Number of PHY : %d, Channel : %d\n", mac_group_index, phy_info_count, pmac_group->channel);
+        }
+    }
+    
+    /* Restore previous MDIO address */
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+    
+    return return_value;
+}
+
+
+
+
+/* @Function Description: Associate the PHYs connected to the structure in alt_tse_system_info.h
+ * @API Type:         Internal
+ * @param pmac_group  Pointer to the TSE MAC grouping structure
+ * @param pphy        Pointer to the TSE PHY info structure which hold information of PHY
+ * @return            return TSE_PHY_MAP_ERROR if mapping error
+ *                    return TSE_PHY_MAP_SUCCESS otherwise
+ */
+alt_32 alt_tse_mac_associate_phy(alt_tse_mac_group *pmac_group, alt_tse_phy_info *pphy) {
+    
+    alt_32 i;
+    alt_32 return_value = TSE_PHY_MAP_SUCCESS;
+    
+    alt_u8 is_mapped;
+
+    alt_tse_system_info *psys = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    alt_8 sys_info_index = 0;
+    
+    is_mapped = 0;
+    
+    for(i = 0; i < pmac_group->channel; i++) {
+        pmac_info = pmac_group->pmac_info[i];
+        psys = pmac_info->psys_info;
+       
+        /* map according to the PHY address in alt_tse_system_info.h */
+        if(psys->tse_phy_mdio_address == pphy->mdio_address) {
+            mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+            sys_info_index = alt_tse_get_system_index(psys);
+            
+            pmac_info->pphy_info = pphy;
+            pphy->pmac_info = pmac_info;
+            tse_dprintf(5, "INFO    : PHY[%d.%d] - Explicitly mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index);
+            is_mapped = 1;
+            break;
+        }
+    }
+    
+    /* if not yet map, it will automatically mapped to the first TSE device encountered with tse_phy_mdio_address = TSE_PHY_AUTO_ADDRESS */
+    if(is_mapped == 0) {
+        for(i = 0; i < pmac_group->channel; i++) {
+            pmac_info = pmac_group->pmac_info[i];
+            psys = pmac_info->psys_info;
+            
+            /* alt_tse_system_info structure definition error */
+            if((psys->tse_msgdma_tx == 0) || (psys->tse_msgdma_rx == 0)){
+                continue;
+            }
+            
+            if(psys->tse_phy_mdio_address == TSE_PHY_AUTO_ADDRESS) {
+                mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+                sys_info_index = alt_tse_get_system_index(psys);
+                
+                pmac_info->pphy_info = pphy;
+                pphy->pmac_info = pmac_info;
+                psys->tse_phy_mdio_address = pphy->mdio_address;
+                tse_dprintf(5, "INFO    : PHY[%d.%d] - Automatically mapped to tse_mac_device[%d]\n", mac_group_index, mac_info_index, sys_info_index);
+                is_mapped = 1;
+                break;
+            }
+        }
+    }
+    
+    /* Still cannot find any matched MAC-PHY */
+    if(is_mapped == 0) {
+        pphy->pmac_info = 0;
+        tse_dprintf(2, "WARNING : PHY[%d.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel\n", mac_group_index);
+        return_value = TSE_PHY_MAP_ERROR;
+    }
+    
+    return return_value;
+}
+
+
+
+
+/* @Function Description: Configure operating mode of Altera PCS if available
+ * @API Type:           Internal
+ * @param pmac_info     pointer to MAC info variable
+ * @return              return SUCCESS
+ */
+alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) {
+    
+    alt_tse_system_info *psys = pmac_info->psys_info;
+    np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+
+    if(psys->tse_pcs_ena) {
+        tse_dprintf(5, "INFO    : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index);
+        
+        alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); 
+        
+        if(psys->tse_pcs_sgmii) {
+            tse_dprintf(5, "INFO    : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index);
+            IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03);
+            }
+        else {
+            tse_dprintf(5, "INFO    : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index);
+            IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03);
+        }
+    }
+    
+    return SUCCESS;
+}
+
+
+
+/* @Function Description: Detect and initialize all the PHYs connected
+ * @API Type:   Internal
+ * @param pmac  N/A
+ * @return      SUCCESS
+ */
+alt_32 alt_tse_phy_init() {
+    alt_8 i = 0;
+    alt_8 j = 0;
+    
+    alt_tse_mac_group *pmac_group = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    
+    /* add supported PHYs */
+    alt_tse_phy_add_profile_default();
+    
+    /* display PHY in profile */
+    alt_tse_phy_print_profile();
+    
+    alt_tse_mac_group_init();
+        
+    /* initialize for each TSE MAC */
+    /* run once only for multi-channel MAC */
+    for(i = 0; i < mac_group_count; i++) {
+        pmac_group = pmac_groups[i];
+        
+        if(pmac_group->pmac_info[0]->psys_info->tse_use_mdio) {
+            
+            /* get connected PHYs */
+            alt_tse_mac_get_phy(pmac_group);
+        }
+        else {
+            tse_dprintf(3, "WARNING : MAC Groups[%d]->pmac_info[%d] MDIO is not used, unable to run PHY detection\n", i, j);
+        }
+        
+        /* Configure PCS mode if MAC+PCS system is used */
+        for(j = 0; j < pmac_group->channel; j++) {
+            pmac_info = pmac_group->pmac_info[j];
+            
+            alt_tse_phy_cfg_pcs(pmac_info);
+        }
+    }
+                
+    return SUCCESS;
+}
+
+
+/* @Function Description: Restart Auto-Negotiation for the PHY
+ * @API Type:                   Internal
+ * @param pphy                  Pointer to the alt_tse_phy_info structure
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *                              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_restart_an(alt_tse_phy_info *pphy, alt_u32 timeout_threshold) {
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+    
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+    
+    if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+        tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index);
+        
+        /* Restore previous MDIO address */
+        alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+        
+        return TSE_PHY_AN_NOT_CAPABLE;
+    }
+    
+    /* enable Auto-Negotiation */    
+    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_AN_ENA, 1, 1);
+    
+    /* send PHY reset command */
+    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESTART_AN, 1, 1);
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Restart Auto-Negotiation, checking PHY link...\n", mac_group_index, mac_info_index);
+    
+    alt_32 timeout = 0;
+    while(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0 ){ 
+        if(timeout++ > timeout_threshold) {
+           tse_dprintf(4, "WARNING : PHY[%d.%d] - Auto-Negotiation FAILED\n", mac_group_index, mac_info_index);
+           
+           /* Restore previous MDIO address */
+           alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+           
+           return TSE_PHY_AN_NOT_COMPLETE;
+        }
+        usleep(1000);
+    }
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Auto-Negotiation PASSED\n", mac_group_index, mac_info_index);
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+    
+    return TSE_PHY_AN_COMPLETE;
+}
+
+
+/* @Function Description: Check link status of PHY and start Auto-Negotiation if it has not yet done
+ * @API Type:                   Internal
+ * @param pphy                  Pointer to the alt_tse_phy_info structure
+ *        timeout_threshold     timeout value of Auto-Negotiation
+ * @return                      return TSE_PHY_AN_COMPLETE if success
+ *                              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ */
+alt_32 alt_tse_phy_check_link(alt_tse_phy_info *pphy, alt_u32 timeout_threshold)
+{
+    alt_32 timeout=0;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); 
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+    
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+            
+    /* if Auto-Negotiation not complete yet, then restart Auto-Negotiation */
+    /* Issue a PHY reset here and wait for the link
+     * autonegotiation complete again... this takes several SECONDS(!)
+     * so be very careful not to do it frequently
+     * perform this when PHY is configured in loopback or has no link yet.
+     */
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Checking link...\n", mac_group_index, mac_info_index);
+    while( ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_LOOPBACK, 1)) != 0) ||
+        ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1)) == 0) )
+    {                 
+        if (timeout++ > timeout_threshold) 
+        {    
+          tse_dprintf(5, "INFO    : PHY[%d.%d] - Link not yet established, restart auto-negotiation...\n", mac_group_index, mac_info_index);
+          /* restart Auto-Negotiation */
+          /* if Auto-Negotiation still cannot complete, then go to next PHY */
+          if(alt_tse_phy_restart_an(pphy, timeout_threshold) == TSE_PHY_AN_NOT_COMPLETE)
+          {
+            tse_dprintf(3, "WARNING : PHY[%d.%d] - Link could not established\n", mac_group_index, mac_info_index);
+            
+            /* Restore previous MDIO address */
+            alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+    
+            return TSE_PHY_AN_NOT_COMPLETE;
+          } 
+        }   
+        usleep(1000);        
+    }
+    tse_dprintf(5, "INFO    : PHY[%d.%d] - Link established\n", mac_group_index, mac_info_index);
+            
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+    
+    return TSE_PHY_AN_COMPLETE; 
+}
+
+/* @Function Description: Get link capability of PHY and link partner
+ * @API Type:   Internal
+ * @param pmac  Pointer to the alt_tse_phy_info structure
+ * @return      return TSE_PHY_AN_COMPLETE if success
+ *              return TSE_PHY_AN_NOT_COMPLETE if auto-negotiation not completed
+ *              return TSE_PHY_AN_NOT_CAPABLE if the PHY not capable for AN
+ */
+alt_32 alt_tse_phy_get_cap(alt_tse_phy_info *pphy) {
+    alt_32 return_value = TSE_PHY_AN_COMPLETE;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);    
+        
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+            
+    if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+        tse_dprintf(3, "WARNING : PHY[%d.%d] - PHY not capable for Auto-Negotiation\n", mac_group_index, mac_info_index);
+        
+        /* Restore previous MDIO address */
+        alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+        
+        return TSE_PHY_AN_NOT_CAPABLE;
+    }
+    
+    /* check whether link has been established */
+    alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+    
+    if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 0) {
+        return_value = TSE_PHY_AN_NOT_COMPLETE;
+    }
+    
+    /* get PHY capabilities */
+    pphy->link_capability.cap_1000_base_x_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_FULL, 1);
+    pphy->link_capability.cap_1000_base_x_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_X_HALF, 1);
+    pphy->link_capability.cap_1000_base_t_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1);
+    pphy->link_capability.cap_1000_base_t_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1);
+    
+    pphy->link_capability.cap_100_base_t4      = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1);
+    pphy->link_capability.cap_100_base_x_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1);
+    pphy->link_capability.cap_100_base_x_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1);
+    pphy->link_capability.cap_100_base_t2_full = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_FULL, 1);
+    pphy->link_capability.cap_100_base_t2_half = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T2_HALF, 1);
+    pphy->link_capability.cap_10_base_t_full   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1);
+    pphy->link_capability.cap_10_base_t_half   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1);
+    
+    /* get link partner capability */
+    pphy->link_capability.lp_1000_base_t_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_FULL_ADV, 1);
+    pphy->link_capability.lp_1000_base_t_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_STATUS, TSE_PHY_MDIO_1000BASE_T_STATUS_LP_HALF_ADV, 1);
+    
+    pphy->link_capability.lp_100_base_t4       = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1);
+    pphy->link_capability.lp_100_base_tx_full  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1);
+    pphy->link_capability.lp_100_base_tx_half  = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1);
+    pphy->link_capability.lp_10_base_tx_full   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1);
+    pphy->link_capability.lp_10_base_tx_half   = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_REMADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1);
+    
+    tse_dprintf(6, "INFO    : PHY[%d.%d] - Capability of PHY :\n", mac_group_index, mac_info_index);
+    tse_dprintf(6, "INFO    : 1000 Base-X Full Duplex = %d\n", pphy->link_capability.cap_1000_base_x_full);
+    tse_dprintf(6, "INFO    : 1000 Base-X Half Duplex = %d\n", pphy->link_capability.cap_1000_base_x_half);
+    tse_dprintf(6, "INFO    : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.cap_1000_base_t_full);
+    tse_dprintf(6, "INFO    : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.cap_1000_base_t_half);
+    tse_dprintf(6, "INFO    : 100 Base-T4             = %d\n", pphy->link_capability.cap_100_base_t4);
+    tse_dprintf(6, "INFO    : 100 Base-X Full Duplex  = %d\n", pphy->link_capability.cap_100_base_x_full);
+    tse_dprintf(6, "INFO    : 100 Base-X Half Duplex  = %d\n", pphy->link_capability.cap_100_base_x_half);
+    tse_dprintf(6, "INFO    : 100 Base-T2 Full Duplex = %d\n", pphy->link_capability.cap_100_base_t2_full);
+    tse_dprintf(6, "INFO    : 100 Base-T2 Half Duplex = %d\n", pphy->link_capability.cap_100_base_t2_half);
+    tse_dprintf(6, "INFO    : 10 Base-T Full Duplex   = %d\n", pphy->link_capability.cap_10_base_t_full);
+    tse_dprintf(6, "INFO    : 10 Base-T Half Duplex   = %d\n", pphy->link_capability.cap_10_base_t_half);
+    tse_dprintf(6, "\n");
+    
+    tse_dprintf(6, "INFO    : PHY[%d.%d] - Link Partner Capability :\n", mac_group_index, mac_info_index);
+    tse_dprintf(6, "INFO    : 1000 Base-T Full Duplex = %d\n", pphy->link_capability.lp_1000_base_t_full);
+    tse_dprintf(6, "INFO    : 1000 Base-T Half Duplex = %d\n", pphy->link_capability.lp_1000_base_t_half);
+    tse_dprintf(6, "INFO    : 100 Base-T4             = %d\n", pphy->link_capability.lp_100_base_t4);
+    tse_dprintf(6, "INFO    : 100 Base-TX Full Duplex = %d\n", pphy->link_capability.lp_100_base_tx_full);
+    tse_dprintf(6, "INFO    : 100 Base-TX Half Duplex = %d\n", pphy->link_capability.lp_100_base_tx_half);
+    tse_dprintf(6, "INFO    : 10 Base-TX Full Duplex  = %d\n", pphy->link_capability.lp_10_base_tx_full);
+    tse_dprintf(6, "INFO    : 10 Base-TX Half Duplex  = %d\n", pphy->link_capability.lp_10_base_tx_half);
+    tse_dprintf(6, "\n");
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+    
+    return return_value;
+    
+}
+
+
+/* @Function Description: Set the advertisement of PHY for 1000 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_1000(alt_tse_phy_info *pphy, alt_u8 enable) {
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_FULL, 1); 
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+        
+        /* 1000 Mbps Half duplex not supported by TSE MAC */
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_EXT_STATUS, TSE_PHY_MDIO_EXT_STATUS_1000BASE_T_HALF, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_FULL_ADV, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 1000 Base-T Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+        
+        /* 1000 Mbps Half duplex not supported by TSE MAC */
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_1000BASE_T_CTRL, TSE_PHY_MDIO_1000BASE_T_CTRL_HALF_ADV, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement 1000 Base-T half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);    
+
+    return SUCCESS;
+}
+
+
+/* @Function Description: Set the advertisement of PHY for 100 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_100(alt_tse_phy_info *pphy, alt_u8 enable) {
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    alt_u8 mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_T4, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, cap);
+        
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_FULL, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+        
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_100BASE_X_HALF, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_T4, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-T4 set to %d\n", mac_group_index, mac_info_index, 0);
+        
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_FULL, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+        
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_100BASE_TX_HALF, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 100 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);  
+    
+    return SUCCESS;
+}
+
+
+/* @Function Description: Set the advertisement of PHY for 10 Mbps
+ * @API Type:    Internal
+ * @param pmac   Pointer to the alt_tse_phy_info structure
+ *        enable set Enable = 1 to advertise this speed if the PHY capable
+ *               set Enable = 0 to disable advertise of this speed
+ * @return       return SUCCESS
+ */
+alt_32 alt_tse_phy_set_adv_10(alt_tse_phy_info *pphy, alt_u8 enable) {
+    alt_u8 cap;
+    
+    /* pointer to MAC associated and MAC group */
+    alt_tse_mac_info *pmac_info = pphy->pmac_info;
+    alt_tse_mac_group *pmac_group = pmac_info->pmac_group;
+    
+    /* get index of the pointers in pointer array list */
+    int mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+    int mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* Record previous MDIO address, to be restored at the end of function */
+    int mdioadd_prev = alt_tse_phy_rd_mdio_addr(pphy); 
+       
+    /* write PHY address to MDIO to access the i-th PHY */
+    alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+    
+    /* if enable = 1, set advertisement based on PHY capability */
+    if(enable) {
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_FULL, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+    
+        cap = alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_10BASE_T_HALF, 1);
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, cap);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, cap);
+    }
+    /* else disable advertisement of this speed */
+    else {
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_FULL, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Full Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+    
+        alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_ADV, TSE_PHY_MDIO_ADV_10BASE_TX_HALF, 1, 0);
+        tse_dprintf(6, "INFO    : PHY[%d.%d] - Advertisement of 10 Base-TX Half Duplex set to %d\n", mac_group_index, mac_info_index, 0);
+    }
+    
+    /* Restore previous MDIO address */
+    alt_tse_phy_wr_mdio_addr(pphy, mdioadd_prev);
+    
+    return SUCCESS;
+}
+
+
+
+
+/* @Function Description: Get the common speed supported by all PHYs connected to the MAC within the same group
+ * @API Type:           Internal
+ * @param pmac_group    Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ * @return              common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if no common speed found
+ */
+alt_32 alt_tse_phy_get_common_speed(alt_tse_mac_group *pmac_group) {
+    
+    alt_32 i;
+    alt_u8 common_1000 = 1;
+    alt_u8 common_100 = 1;
+    alt_u8 common_10 = 1;
+    
+    alt_32 common_speed;
+    
+    alt_u8 none_an_complete = 1;
+    
+    alt_tse_mac_info *pmac_info = 0;
+    alt_tse_phy_info *pphy = 0;
+    
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+    
+    /* reset Auto-Negotiation advertisement */
+    for(i = 0; i < pmac_group->channel; i++) {
+        pmac_info = pmac_group->pmac_info[i];
+        pphy = pmac_info->pphy_info;
+        
+        /* run only if PHY connected */
+        if(pphy) {
+            alt_tse_phy_set_adv_1000(pphy, 1);
+            alt_tse_phy_set_adv_100(pphy, 1);
+            alt_tse_phy_set_adv_10(pphy, 1);
+        }
+        tse_dprintf(6, "\n");
+    }
+    
+    /* loop through every PHY connected */
+    for(i = 0; i < pmac_group->channel; i++) {
+
+        pmac_info = pmac_group->pmac_info[i];
+        pphy = pmac_info->pphy_info;
+        
+        /* if no PHY connected */
+        if(!pphy) {
+            continue;
+        }
+        
+        /* get PHY capability */
+        /* skip for PHY with Auto-Negotiation not completed */
+        if(alt_tse_phy_get_cap(pphy) != TSE_PHY_AN_COMPLETE) {
+            continue;
+        }
+        
+        none_an_complete = 0;
+        
+        /* Small MAC */
+        if(pmac_info->mac_type == ALTERA_TSE_MACLITE_10_100) {
+            common_1000 = 0;
+        }
+        else if(pmac_info->mac_type == ALTERA_TSE_MACLITE_1000) {
+            common_100 = 0;
+            common_10 = 0;            
+        }
+        
+        /* get common capabilities for all PHYs and link partners */
+        common_1000 &= ((pphy->link_capability.cap_1000_base_t_full & pphy->link_capability.lp_1000_base_t_full));
+                        //(pphy->link_capability.cap_1000_base_t_half & pphy->link_capability.lp_1000_base_t_half));
+        common_100 &= ((pphy->link_capability.cap_100_base_x_full & pphy->link_capability.lp_100_base_tx_full) |
+                        (pphy->link_capability.cap_100_base_x_half & pphy->link_capability.lp_100_base_tx_half) |
+                        (pphy->link_capability.cap_100_base_t4 & pphy->link_capability.lp_100_base_t4));
+        common_10 &= ((pphy->link_capability.cap_10_base_t_full & pphy->link_capability.lp_10_base_tx_full) |
+                        (pphy->link_capability.cap_10_base_t_half & pphy->link_capability.lp_10_base_tx_half));
+
+    }
+    
+    /* get common speed based on capabilities */
+    if(none_an_complete == 1) {
+        common_speed = TSE_PHY_SPEED_NO_COMMON;
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - None of the PHYs Auto-Negotiation completed!\n", mac_group_index);
+    }
+    else if(common_1000) {
+        common_speed = TSE_PHY_SPEED_1000;
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 1000);
+    }
+    else if(common_100) {
+        common_speed = TSE_PHY_SPEED_100;
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 100);
+    }
+    else if(common_10) {
+        common_speed = TSE_PHY_SPEED_10;
+        tse_dprintf(5, "INFO    : MAC Group[%d] - Common Speed : %d Mbps\n", mac_group_index, 10);
+    }
+    else {
+        common_speed = TSE_PHY_SPEED_NO_COMMON;
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - No common speed at all!\n", mac_group_index);    }
+
+    return common_speed;
+}
+
+
+/* @Function Description: Set the common speed to all PHYs connected to the MAC within the same group
+ * @API Type:               Internal
+ * @param pmac_group        Pointer to the TSE MAC Group structure which group all the MACs that should use the same speed
+ *        common_speed      common speed supported by all PHYs
+ * @return      common speed supported by all PHYs connected to the MAC, return TSE_PHY_SPEED_NO_COMMON if invalid common speed specified
+ */
+alt_32 alt_tse_phy_set_common_speed(alt_tse_mac_group *pmac_group, alt_32 common_speed) {
+    
+    alt_32 i;
+
+    alt_u8 speed;
+    alt_u8 duplex;
+    
+    alt_u8 gb_capable;
+    
+    alt_tse_phy_info *pphy = 0;
+    alt_tse_mac_info *pmac_info = 0;
+    alt_tse_system_info *psys = 0;
+    
+    /* get index of the pointers in pointer array list */
+    alt_8 mac_info_index = 0;
+    alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group);
+         
+    /* Record previous MDIO address, to be restored at the end of function */
+    np_tse_mac *pmac_group_base = (np_tse_mac *)pmac_group->pmac_info[0]->psys_info->tse_mac_base;
+    alt_32 mdioadd_prev = IORD(&pmac_group_base->MDIO_ADDR1, 0);
+    
+    if((common_speed < TSE_PHY_SPEED_10) || (common_speed > TSE_PHY_SPEED_1000)) {
+        tse_dprintf(2, "ERROR   : MAC Group[%d] - Invalid common speed specified! common speed = %d\n", mac_group_index, (int)common_speed);
+        /* Restore previous MDIO address */
+        IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+        return TSE_PHY_SPEED_NO_COMMON;
+    }
+    
+    /* loop through every PHY connected */
+    for(i = 0; i < pmac_group->channel; i++) {
+        pmac_info = pmac_group->pmac_info[i];
+        mac_info_index = alt_tse_get_mac_info_index(pmac_info);
+
+        pphy = pmac_info->pphy_info;
+        
+        /* if no PHY connected */
+        if(!pphy) {
+            continue;
+        }
+        
+        psys = pmac_info->psys_info; 
+            
+        /* write PHY address to MDIO to access the i-th PHY */
+        alt_tse_phy_wr_mdio_addr(pphy, pphy->mdio_address);
+
+        /* capability of PHY supports 1000 Mbps */
+        gb_capable = pphy->link_capability.cap_1000_base_t_full || pphy->link_capability.cap_1000_base_t_half || 
+                 pphy->link_capability.cap_1000_base_x_full || pphy->link_capability.cap_1000_base_x_half;
+        
+        /* if PHY does not supports 1000 Mbps, and common speed is 1000 Mbps */
+        if((!gb_capable) && (common_speed == TSE_PHY_SPEED_1000)) {
+            tse_dprintf(2, "ERROR   : PHY[%d.%d] - PHY does not support 1000 Mbps, please specify valid common speed\n", mac_group_index, mac_info_index);
+            /* Restore previous MDIO address */
+            IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+            return TSE_PHY_SPEED_NO_COMMON;
+        }
+        
+        /* if PHY is not Auto-Negotiation capable */
+        if(!alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_ABILITY, 1)) {
+            
+            /* if PHY supports 1000 Mbps, write msb of speed */
+            if(gb_capable) {
+                alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_MSB, 1, common_speed >> 1);
+            }
+            /* write lsb of speed */
+            alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_SPEED_LSB, 1, common_speed);
+            
+            /* continue to next PHY */
+            continue;
+        }
+        
+        /* set Auto-Negotiation advertisement based on common speed */
+        if(common_speed == TSE_PHY_SPEED_1000) {
+            alt_tse_phy_set_adv_1000(pphy, 1);
+            alt_tse_phy_set_adv_100(pphy, 1);
+            alt_tse_phy_set_adv_10(pphy, 1);
+        }
+        else if(common_speed == TSE_PHY_SPEED_100) {
+            alt_tse_phy_set_adv_1000(pphy, 0);
+            alt_tse_phy_set_adv_100(pphy, 1);
+            alt_tse_phy_set_adv_10(pphy, 1);
+        }    
+        else if(common_speed == TSE_PHY_SPEED_10) {
+            alt_tse_phy_set_adv_1000(pphy, 0);
+            alt_tse_phy_set_adv_100(pphy, 0);
+            alt_tse_phy_set_adv_10(pphy, 1);
+        }
+        else {
+            alt_tse_phy_set_adv_1000(pphy, 0);
+            alt_tse_phy_set_adv_100(pphy, 0);
+            alt_tse_phy_set_adv_10(pphy, 0);
+        }
+        
+        /* if PHY Auto-Negotiation is completed */
+        if(alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, TSE_PHY_MDIO_STATUS_AN_COMPLETE, 1) == 1) {
+            
+            /* read both msb and lsb of speed bits if PHY support 1000 Mbps */
+            if(gb_capable) {
+        
+                /* get speed information after Auto-Negotiation */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 2);
+            }
+            
+            /* read lsb of speed only if PHY support only 10/100 Mbps */
+            else {
+                /* get speed and link information after Auto-Negotiation */
+                speed = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->speed_lsb_location, 1);
+            }
+            
+            /* if current speed != common speed, then restart Auto-Negotiation */
+            if(speed != common_speed) {
+                alt_tse_phy_restart_an(pphy, ALTERA_AUTONEG_TIMEOUT_THRESHOLD);
+            }
+            
+            /* get speed information after Auto-Negotiation */
+            duplex = alt_tse_phy_rd_mdio_reg(pphy, pphy->pphy_profile->status_reg_location, pphy->pphy_profile->duplex_bit_location, 1);
+            
+            /* Set MAC duplex register */
+            alt_tse_mac_set_duplex((np_tse_mac *)psys->tse_mac_base, duplex);
+            
+        }
+        tse_dprintf(5, "INFO    : PHY[%d.%d] - PHY STATUS = 0x%04x\n\n", mac_group_index, mac_info_index, (int) alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_STATUS, 0, 16));        
+    }
+    tse_dprintf(5, "INFO    : MAC Group[%d] - All PHYs set to common speed : %d Mbps\n", mac_group_index, (common_speed == TSE_PHY_SPEED_1000) ? 1000 : ((common_speed == TSE_PHY_SPEED_100) ? 100 : 10));
+
+    /* Set MAC speed register */
+    alt_tse_mac_set_speed(pmac_group_base, common_speed);
+    
+    /* Restore previous MDIO address */
+    IOWR(&pmac_group_base->MDIO_ADDR1, 0, mdioadd_prev);
+        
+    return common_speed;
+}
+
+
+
+/* @Function Description: Additional configuration for Marvell PHY
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address of MAC group
+ */
+alt_32 marvell_phy_cfg(np_tse_mac *pmac) {
+    
+    alt_u16 dat;
+    
+    /* If there is no link yet, we enable auto crossover and reset the PHY */
+    if((IORD(&pmac->mdio1.STATUS, 0) & PCS_ST_an_done) == 0) {
+        tse_dprintf(5, "MARVELL : Enabling auto crossover\n");
+        IOWR(&pmac->mdio1.CONTROL, 16, 0x0078);
+        tse_dprintf(5, "MARVELL : PHY reset\n");
+        dat = IORD(&pmac->mdio1.CONTROL, 0); 
+        IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);        
+    }
+    
+    return 0;
+}
+
+
+/* @Function Description: Change operating mode of Marvell PHY to GMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_gmii(np_tse_mac *pmac) {
+    
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+    dat &= 0xfff0;
+
+    tse_dprintf(5, "MARVELL : Mode changed to GMII to copper mode\n");
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0xf);
+    
+    tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n");
+    dat = IORD(&pmac->mdio1.reg14, 0); 
+    dat &= ~0x82;
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+    
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+    
+    return 1;
+}
+
+/* @Function Description: Change operating mode of Marvell PHY to SGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_sgmii(np_tse_mac *pmac) {
+    
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+    dat &= 0xfff0;
+
+    tse_dprintf(5, "MARVELL : Mode changed to SGMII without clock with SGMII Auto-Neg to copper mode\n");
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0x4);
+    
+    tse_dprintf(5, "MARVELL : Disable RGMII Timing Control\n");
+    dat = IORD(&pmac->mdio1.reg14, 0); 
+    dat &= ~0x82;
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+    
+    return 1;
+}
+
+/* @Function Description: Change operating mode of Marvell PHY to RGMII
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) {
+    
+
+    alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
+    dat &= 0xfff0;
+    
+    tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n");
+    IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb);
+    
+    tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n");
+    dat = IORD(&pmac->mdio1.reg14, 0);
+    dat &= ~0x82;
+    dat |= 0x82;
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+    
+    tse_dprintf(5, "MARVELL : PHY reset\n");
+    dat = IORD(&pmac->mdio1.CONTROL, 0); 
+    IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
+    
+    return 1;
+    
+}
+
+/* @Function Description: Read link status from PHY specific status register of DP83848C
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 DP83848C_link_status_read(np_tse_mac *pmac) {
+    alt_u32 link_status = 0;
+    alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0);
+    
+    /* If speed == 10 Mbps */
+    if(reg_status & 0x2) {
+        link_status |= 0x8;
+    }
+    /* Else speed = 100 Mbps */
+    else {
+        link_status |= 0x4;
+    }
+    
+    /* If duplex == Full */
+    if(reg_status & 0x4) {
+        link_status |= 0x1;
+    }
+    
+    return link_status;
+}
+
+/* @Function Description: Additional configuration for PEF7071 Phy
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_32 PEF7071_config(np_tse_mac *pmac)
+{  
+    alt_u16 dat;
+        
+    dat = IORD(&pmac->mdio1.reg14, 0);
+    dat &= 0x3FFF;
+    dat |= 0x0100;
+    IOWR(&pmac->mdio1.reg14, 0, dat);
+    
+    return 0;
+    
+}
+
+/* @Function Description: Read link status from PHY specific status register of PEF7071
+ * @API Type:   Internal
+ * @param pmac  Pointer to the first TSE MAC Control Interface Base address within MAC group
+ */
+alt_u32 PEF7071_link_status_read(np_tse_mac *pmac)
+{
+    alt_u32 link_status = 0;
+    alt_u32 reg18 = IORD(&pmac->mdio1.reg18, 0);
+        
+    if ((reg18 & 0x3)==0) { link_status |= 0x8; }  /* If speed == 10 Mbps */
+    if ((reg18 & 0x3)==1) { link_status |= 0x4; }  /* Else speed = 100 Mbps */
+    if ((reg18 & 0x3)==2) { link_status |= 0x2; }  /* Else speed = 1000 Mbps */    
+        
+    /* If duplex == Full */
+    if(reg18 & 0x8) {
+        link_status |= 0x1;
+    }
+    
+    return link_status;
+}
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c
new file mode 100644
index 0000000..2fb6e8d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_tse_system_info.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#ifdef ALT_INICHE
+    #include "ipport.h"
+#endif
+
+#include "altera_avalon_tse.h"
+#include "altera_avalon_tse_system_info.h"
+#include "system.h"
+ 
+#ifdef TSE_MY_SYSTEM
+/* define TSE_MY_SYSTEM to customize tse_mac_device[] structure using global array initialization */
+	extern alt_tse_system_info tse_mac_device[MAXNETS];
+#else
+
+/* use tse_mac_device[] structure as defined in this file
+ * or
+ * customize tse_mac_device[] structure using API alt_tse_system_add_sys() and alt_tse_sys_enable_mdio_sharing() */
+alt_tse_system_info tse_mac_device[MAXNETS] = {
+              
+        /************************************************************************************/
+        #if ( defined(TSE_0_TSE_BASE) && defined(TSE_0_DMA_TX_CSR_NAME) && defined(TSE_0_DMA_RX_CSR_NAME) )
+			#ifdef DESCRIPTOR_MEMORY_BASE
+                TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_0_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, 0, DESCRIPTOR_MEMORY)
+			#else
+                TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(TSE_0_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, 0)
+			#endif
+        #endif
+        /************************************************************************************/		
+};
+
+#endif /* TSE_MY_SYSTEM */
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c
new file mode 100644
index 0000000..c07024a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_fd.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2007 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include "alt_types.h"
+#include "sys/alt_dev.h"
+#include "altera_avalon_uart.h"
+
+extern int altera_avalon_uart_read(altera_avalon_uart_state* sp,
+  char* buffer, int space, int flags);
+extern int altera_avalon_uart_write(altera_avalon_uart_state* sp,
+  const char* ptr, int count, int flags);
+extern int altera_avalon_uart_ioctl(altera_avalon_uart_state* sp,
+  int req, void* arg);
+extern int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags);
+
+/* ----------------------------------------------------------------------- */
+/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */
+/*
+ *
+ */
+
+int 
+altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space)
+{
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+
+    return altera_avalon_uart_read(&dev->state, buffer, space,
+      fd->fd_flags);
+}
+
+int 
+altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space)
+{
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+
+    return altera_avalon_uart_write(&dev->state, buffer, space,
+      fd->fd_flags);
+}
+
+#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
+
+/*
+ * Fast driver
+ */
+
+/*
+ * To reduce the code footprint of this driver, the ioctl() function is not
+ * included by default. If you wish to use the ioctl features provided 
+ * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL
+ * to CPPFLAGS in the Makefile (or through the Eclipse IDE).
+ */
+
+#ifdef ALTERA_AVALON_UART_USE_IOCTL
+
+int 
+altera_avalon_uart_ioctl_fd(alt_fd* fd, int req, void* arg)
+{
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev;
+
+    return altera_avalon_uart_ioctl(&dev->state, req, arg);
+}
+
+#endif /* ALTERA_AVALON_UART_USE_IOCTL */
+
+int 
+altera_avalon_uart_close_fd(alt_fd* fd)
+{
+    altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; 
+
+    return altera_avalon_uart_close(&dev->state, fd->fd_flags);
+}
+
+#endif /* fast driver */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c
new file mode 100644
index 0000000..92484d6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_init.c
@@ -0,0 +1,312 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2009 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <fcntl.h>
+
+#include "sys/alt_dev.h"
+#include "sys/alt_irq.h"
+#include "sys/ioctl.h"
+#include "sys/alt_errno.h"
+
+#include "altera_avalon_uart.h"
+#include "altera_avalon_uart_regs.h"
+
+#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
+
+/* ----------------------------------------------------------- */
+/* ------------------------- FAST DRIVER --------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * altera_avalon_uart_init() is called by the auto-generated function 
+ * alt_sys_init() in order to initialize a particular instance of this device.
+ * It is responsible for configuring the device and associated software 
+ * constructs.
+ */
+
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void altera_avalon_uart_irq(void* context);
+#else
+static void altera_avalon_uart_irq(void* context, alt_u32 id);
+#endif 
+
+static void altera_avalon_uart_rxirq(altera_avalon_uart_state* sp,
+  alt_u32 status);
+static void altera_avalon_uart_txirq(altera_avalon_uart_state* sp,
+  alt_u32 status);
+
+void 
+altera_avalon_uart_init(altera_avalon_uart_state* sp, 
+  alt_u32 irq_controller_id,  alt_u32 irq)
+{
+  void* base = sp->base;
+  int error;
+
+  /* 
+   * Initialise the read and write flags and the semaphores used to 
+   * protect access to the circular buffers when running in a multi-threaded
+   * environment.
+   */
+  error = ALT_FLAG_CREATE (&sp->events, 0)    || 
+          ALT_SEM_CREATE (&sp->read_lock, 1)  ||
+          ALT_SEM_CREATE (&sp->write_lock, 1);
+
+  if (!error)
+  {
+    /* enable interrupts at the device */
+    sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK  |
+                ALTERA_AVALON_UART_CONTROL_RRDY_MSK |
+                ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
+
+    IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); 
+  
+    /* register the interrupt handler */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+    alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, 
+      0x0);
+#else
+    alt_irq_register (irq, sp, altera_avalon_uart_irq);
+#endif  
+  }
+}
+
+/*
+ * altera_avalon_uart_irq() is the interrupt handler registered at 
+ * configuration time for processing UART interrupts. It vectors 
+ * interrupt requests to either altera_avalon_uart_rxirq() (for incoming 
+ * data), or altera_avalon_uart_txirq() (for outgoing data).
+ */
+#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
+static void altera_avalon_uart_irq(void* context)
+#else
+static void altera_avalon_uart_irq(void* context, alt_u32 id)
+#endif
+{
+  alt_u32 status;
+
+  altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context;
+  void* base               = sp->base;
+
+  /*
+   * Read the status register in order to determine the cause of the
+   * interrupt.
+   */
+
+  status = IORD_ALTERA_AVALON_UART_STATUS(base);
+
+  /* Clear any error flags set at the device */
+  IOWR_ALTERA_AVALON_UART_STATUS(base, 0);
+
+  /* Dummy read to ensure IRQ is negated before ISR returns */
+  IORD_ALTERA_AVALON_UART_STATUS(base);
+  
+  /* process a read irq */
+  if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK)
+  {
+    altera_avalon_uart_rxirq(sp, status);
+  }
+
+  /* process a write irq */
+  if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | 
+                  ALTERA_AVALON_UART_STATUS_DCTS_MSK))
+  {
+    altera_avalon_uart_txirq(sp, status);
+  }
+  
+
+}
+
+/*
+ * altera_avalon_uart_rxirq() is called by altera_avalon_uart_irq() to 
+ * process a receive interrupt. It transfers the incoming character into 
+ * the receive circular buffer, and sets the apropriate flags to indicate 
+ * that there is data ready to be processed.
+ */
+static void 
+altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status)
+{
+  alt_u32 next;
+  
+  /* If there was an error, discard the data */
+
+  if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | 
+                  ALTERA_AVALON_UART_STATUS_FE_MSK))
+  {
+    return;
+  }
+
+  /*
+   * In a multi-threaded environment, set the read event flag to indicate
+   * that there is data ready. This is only done if the circular buffer was
+   * previously empty.
+   */
+
+  if (sp->rx_end == sp->rx_start)
+  {
+    ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET);
+  }
+
+  /* Determine which slot to use next in the circular buffer */
+
+  next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+
+  /* Transfer data from the device to the circular buffer */
+
+  sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base);
+
+  sp->rx_end = next;
+
+  next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+
+  /*
+   * If the cicular buffer was full, disable interrupts. Interrupts will be
+   * re-enabled when data is removed from the buffer.
+   */
+
+  if (next == sp->rx_start)
+  {
+    sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+    IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); 
+  }   
+}
+
+/*
+ * altera_avalon_uart_txirq() is called by altera_avalon_uart_irq() to 
+ * process a transmit interrupt. It transfers data from the transmit 
+ * buffer to the device, and sets the apropriate flags to indicate that 
+ * there is data ready to be processed.
+ */
+static void 
+altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status)
+{
+  /* Transfer data if there is some ready to be transfered */
+
+  if (sp->tx_start != sp->tx_end)
+  {
+    /* 
+     * If the device is using flow control (i.e. RTS/CTS), then the
+     * transmitter is required to throttle if CTS is high.
+     */
+
+    if (!(sp->flags & ALT_AVALON_UART_FC) ||
+      (status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
+    { 
+
+      /*
+       * In a multi-threaded environment, set the write event flag to indicate
+       * that there is space in the circular buffer. This is only done if the
+       * buffer was previously empty.
+       */
+
+      if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))
+      { 
+        ALT_FLAG_POST (sp->events, 
+                       ALT_UART_WRITE_RDY,
+                       OS_FLAG_SET);
+      }
+
+      /* Write the data to the device */
+
+      IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]);
+
+      sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK;
+
+      /*
+       * In case the tranmit interrupt had previously been disabled by 
+       * detecting a low value on CTS, it is reenabled here.
+       */ 
+
+      sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+    }
+    else
+    {
+      /*
+       * CTS is low and we are using flow control, so disable the transmit
+       * interrupt while we wait for CTS to go high again. This will be 
+       * detected using the DCTS interrupt.
+       *
+       * There is a race condition here. "status" may indicate that 
+       * CTS is low, but it actually went high before DCTS was cleared on 
+       * the last write to the status register. To avoid this resulting in
+       * deadlock, it's necessary to re-check the status register here
+       * before throttling.
+       */
+ 
+      status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); 
+
+      if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK))
+      {
+        sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+      }
+    }
+  }
+
+  /*
+   * If the circular buffer is empty, disable the interrupt. This will be
+   * re-enabled when new data is placed in the buffer.
+   */
+
+  if (sp->tx_start == sp->tx_end)
+  {
+    sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+                    ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
+  }
+
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+}
+
+/*
+ * The close() routine is implemented to drain the UART transmit buffer
+ * when not in "small" mode. This routine will wait for transimt data to be
+ * emptied unless the driver flags have been set to non-blocking mode. 
+ * This routine should be called indirectly (i.e. though the C library 
+ * close() routine) so that the file descriptor associated with the relevant 
+ * stream (i.e. stdout) can be closed as well. This routine does not manage 
+ * file descriptors.
+ * 
+ * The close routine is not implemented for the small driver; instead it will
+ * map to null. This is because the small driver simply waits while characters
+ * are transmitted; there is no interrupt-serviced buffer to empty 
+ */
+int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags)
+{
+  /* 
+   * Wait for all transmit data to be emptied by the UART ISR.
+   */
+  while (sp->tx_start != sp->tx_end) {
+    if (flags & O_NONBLOCK) {
+      return -EWOULDBLOCK; 
+    }
+  }
+
+  return 0;
+}
+
+#endif /* fast driver */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c
new file mode 100644
index 0000000..4f281d5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_ioctl.c
@@ -0,0 +1,153 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <fcntl.h>
+#include <string.h>
+
+#include "sys/alt_irq.h"
+#include "sys/ioctl.h"
+#include "sys/alt_errno.h"
+
+#include "altera_avalon_uart_regs.h"
+#include "altera_avalon_uart.h"
+
+
+#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL)
+
+/* ----------------------------------------------------------- */
+/* ------------------------- FAST DRIVER --------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * To reduce the code footprint of this driver, the ioctl() function is not
+ * included by default. If you wish to use the ioctl features provided 
+ * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL
+ * to CPPFLAGS in the Makefile (or through the Eclipse IDE).
+ */
+
+#ifdef ALTERA_AVALON_UART_USE_IOCTL
+
+/*
+ * altera_avalon_uart_ioctl() is called by the system ioctl() function to handle
+ * ioctl requests for the UART. The only ioctl requests supported are TIOCMGET
+ * and TIOCMSET.
+ *
+ * TIOCMGET returns a termios structure that describes the current device
+ * configuration.
+ *
+ * TIOCMSET sets the device (if possible) to match the requested configuration.
+ * The requested configuration is described using a termios structure passed
+ * through the input argument "arg".
+ */
+
+static int altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp,
+  struct termios* term);
+static int altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp,
+  struct termios* term);
+
+int 
+altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, int req, void* arg)
+{
+  int rc = -ENOTTY;
+
+  switch (req)
+  {
+  case TIOCMGET:
+    rc = altera_avalon_uart_tiocmget(sp, (struct termios*) arg);
+    break;
+  case TIOCMSET:
+    rc = altera_avalon_uart_tiocmset(sp, (struct termios*) arg);
+    break;
+  default:
+    break;
+  }
+  return rc;
+}
+
+/*
+ * altera_avalon_uart_tiocmget() is used by altera_avalon_uart_ioctl() to fill
+ * in the input termios structure with the current device configuration. 
+ *
+ * See termios.h for further details on the contents of the termios structure.
+ */
+
+static int 
+altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp,
+  struct termios* term)
+{
+  memcpy (term, &sp->termios, sizeof (struct termios));
+  return 0;
+}
+
+/*
+ * altera_avalon_uart_tiocmset() is used by altera_avalon_uart_ioctl() to 
+ * configure the device according to the settings in the input termios 
+ * structure. In practice the only configuration that can be changed is the
+ * baud rate, and then only if the hardware is configured to have a writable
+ * baud register.
+ */
+
+static int 
+altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp,
+  struct termios* term)
+{
+  speed_t speed;
+
+  speed = sp->termios.c_ispeed;
+
+  /* Update the settings if the hardware supports it */
+
+  if (!(sp->flags & ALT_AVALON_UART_FB))
+  {
+    sp->termios.c_ispeed = sp->termios.c_ospeed = term->c_ispeed;
+  }
+  /* 
+   * If the request was for an unsupported setting, return an error.
+   */
+
+  if (memcmp(term, &sp->termios, sizeof (struct termios)))
+  {
+    sp->termios.c_ispeed = sp->termios.c_ospeed = speed;
+    return -EIO;
+  }
+
+  /*
+   * Otherwise, update the hardware.
+   */
+  
+  IOWR_ALTERA_AVALON_UART_DIVISOR(sp->base, 
+    ((sp->freq/sp->termios.c_ispeed) - 1));
+
+  return 0;
+}
+
+#endif /* ALTERA_AVALON_UART_USE_IOCTL */
+
+#endif /* fast driver */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c
new file mode 100644
index 0000000..5286ba3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_read.c
@@ -0,0 +1,240 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <fcntl.h>
+
+#include "sys/alt_irq.h"
+#include "sys/ioctl.h"
+#include "sys/alt_errno.h"
+
+#include "altera_avalon_uart.h"
+#include "altera_avalon_uart_regs.h"
+
+#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
+
+/* ----------------------------------------------------------- */
+/* ----------------------- SMALL DRIVER ---------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * altera_avalon_uart_read() is called by the system read() function in order to
+ * read a block of data from the UART. "len" is the maximum length of the data
+ * to read, and "ptr" indicates the destination address. "fd" is the file
+ * descriptor for the device to be read from.
+ *
+ * Permission checks are made before the call to altera_avalon_uart_read(), so
+ * we know that the file descriptor has been opened with the correct permissions
+ * for this operation.
+ *
+ * The return value is the number of bytes actually read.
+ *
+ * This implementation polls the device waiting for characters. At most it can
+ * only return one character, regardless of how many are requested. If the 
+ * device is being accessed in non-blocking mode then it is possible for this
+ * function to return without reading any characters. In this case errno is
+ * set to EWOULDBLOCK.
+ */
+
+int 
+altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len,
+  int flags)
+{
+  int block;
+  unsigned int status;
+
+  block = !(flags & O_NONBLOCK);
+
+  do
+  {
+    status = IORD_ALTERA_AVALON_UART_STATUS(sp->base);
+
+    /* clear any error flags */
+
+    IOWR_ALTERA_AVALON_UART_STATUS(sp->base, 0);
+
+    if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK)
+    {
+      ptr[0] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base);
+
+      if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK | 
+      ALTERA_AVALON_UART_STATUS_FE_MSK)))
+      {
+        return 1;
+      }
+    }
+  }
+  while (block);
+
+  ALT_ERRNO = EWOULDBLOCK;
+ 
+  return 0;
+}
+
+#else
+
+/* ----------------------------------------------------------- */
+/* ----------------------- FAST DRIVER ----------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * altera_avalon_uart_read() is called by the system read() function in order to
+ * read a block of data from the UART. "len" is the maximum length of the data
+ * to read, and "ptr" indicates the destination address. "sp" is the state
+ * pointer for the device to be read from.
+ *
+ * Permission checks are made before the call to altera_avalon_uart_read(), so
+ * we know that the file descriptor has been opened with the correct permissions
+ * for this operation.
+ *
+ * The return value is the number of bytes actually read.
+ *
+ * This function does not communicate with the device directly. Instead data is
+ * transfered from a circular buffer. The interrupt handler is then responsible
+ * for copying data from the device into this buffer.
+ */
+
+int 
+altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len,
+  int flags)
+{
+  alt_irq_context context;
+  int             block;
+  alt_u8          read_would_block = 0;
+  int             count = 0;
+
+  /* 
+   * Construct a flag to indicate whether the device is being accessed in
+   * blocking or non-blocking mode.
+   */
+
+  block = !(flags & O_NONBLOCK);
+
+  /*
+   * When running in a multi threaded environment, obtain the "read_lock"
+   * semaphore. This ensures that reading from the device is thread-safe.
+   */
+
+  ALT_SEM_PEND (sp->read_lock, 0);
+
+  /*
+   * Loop, copying data from the circular buffer to the destination address
+   * supplied in "ptr". This loop is terminated when the required number of
+   * bytes have been read. If the circular buffer is empty, and no data has
+   * been read, then the loop will block (when in blocking mode).
+   *
+   * If the circular buffer is empty, and some data has already been 
+   * transferred, or the device is being accessed in non-blocking mode, then
+   * the loop terminates without necessarily reading all the requested data.
+   */
+
+  do
+  {
+    /*
+     * Read the required amount of data, until the circular buffer runs
+     * empty
+     */
+
+    while ((count < len) && (sp->rx_start != sp->rx_end))
+    {
+      count++;
+      *ptr++ = sp->rx_buf[sp->rx_start];
+      
+      sp->rx_start = (sp->rx_start+1) & ALT_AVALON_UART_BUF_MSK;
+    }
+
+    /*
+     * If no data has been transferred, the circular buffer is empty, and
+     * this is not a non-blocking access, block waiting for data to arrive.
+     */
+
+    if (!count && (sp->rx_start == sp->rx_end))
+    {
+      if (!block)
+      {
+        /* Set errno to indicate the reason we're not returning any data */
+
+        ALT_ERRNO = EWOULDBLOCK;
+        read_would_block = 1;
+        break;
+      }
+      else
+      {
+       /* Block waiting for some data to arrive */
+
+       /* First, ensure read interrupts are enabled to avoid deadlock */
+
+       context = alt_irq_disable_all ();
+       sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+       IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+       alt_irq_enable_all (context);
+
+       /*
+        * When running in a multi-threaded mode, we pend on the read event 
+        * flag set in the interrupt service routine. This avoids wasting CPU
+        * cycles waiting in this thread, when we could be doing something more 
+        * profitable elsewhere.
+        */
+
+       ALT_FLAG_PEND (sp->events, 
+                      ALT_UART_READ_RDY,
+                      OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
+                      0);
+      }
+    }
+  }
+  while (!count && len);
+
+  /*
+   * Now that access to the circular buffer is complete, release the read
+   * semaphore so that other threads can access the buffer.
+   */
+
+  ALT_SEM_POST (sp->read_lock);
+
+  /*
+   * Ensure that interrupts are enabled, so that the circular buffer can
+   * re-fill.
+   */
+
+  context = alt_irq_disable_all ();
+  sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+  alt_irq_enable_all (context);
+
+  /* Return the number of bytes read */
+  if(read_would_block) {
+    return -EWOULDBLOCK;
+  }
+  else {
+    return count;
+  }
+}
+
+#endif /* fast driver */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c
new file mode 100644
index 0000000..0658e02
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_avalon_uart_write.c
@@ -0,0 +1,232 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <fcntl.h>
+
+#include "sys/alt_dev.h"
+#include "sys/alt_irq.h"
+#include "sys/ioctl.h"
+#include "sys/alt_errno.h"
+
+#include "altera_avalon_uart_regs.h"
+#include "altera_avalon_uart.h"
+
+#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL)
+
+/* ----------------------------------------------------------- */
+/* ------------------------ SMALL DRIVER --------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * altera_avalon_uart_write() is called by the system write() function in 
+ * order to write a block of data to the UART. 
+ * "len" is the length of the data to write,
+ * and "ptr" indicates the source address. "fd" is the file descriptor for the 
+ * device to be read from.
+ *
+ * Permission checks are made before the call to altera_avalon_uart_write(), so
+ * we know that the file descriptor has been opened with the correct permissions
+ * for this operation.
+ *
+ * The return value is the number of bytes actually written.
+ *
+ * This function will block on the devices transmit register, until all 
+ * characters have been transmitted. This is unless the device is being 
+ * accessed in non-blocking mode. In this case this function will return as 
+ * soon as the device reports that it is not ready to transmit.
+ *
+ * Since this is the small footprint version of the UART driver, the value of 
+ * CTS is ignored.
+ */
+
+int 
+altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len,
+  int flags)
+{
+  int block;
+  unsigned int status;
+  int count;
+
+  block = !(flags & O_NONBLOCK);
+  count = len;
+
+  do
+  {
+    status = IORD_ALTERA_AVALON_UART_STATUS(sp->base);
+   
+    if (status & ALTERA_AVALON_UART_STATUS_TRDY_MSK)
+    {
+      IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, *ptr++);
+      count--;
+    }
+  }
+  while (block && count);
+
+  if (count)
+  {
+    ALT_ERRNO = EWOULDBLOCK;
+  }
+
+  return (len - count);
+}
+
+#else /* Using the "fast" version of the driver */
+
+/* ----------------------------------------------------------- */
+/* ------------------------- FAST DRIVER --------------------- */
+/* ----------------------------------------------------------- */
+
+/*
+ * altera_avalon_uart_write() is called by the system write() function in order
+ * to write a block of data to the UART. "len" is the length of the data to 
+ * write, and "ptr" indicates the source address. "sp" is the state pointer
+ * for the device to be written to.
+ *
+ * Permission checks are made before the call to altera_avalon_uart_write(), so
+ * we know that the file descriptor has been opened with the correct permissions
+ * for this operation.
+ *
+ * The return value is the number of bytes actually written.
+ *
+ * This function does not communicate with the device directly. Instead data is
+ * transfered to a circular buffer. The interrupt handler is then responsible
+ * for copying data from this buffer into the device.
+ */
+
+int
+altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len,
+  int flags)
+{
+  alt_irq_context context;
+  int             no_block;
+  alt_u32         next;
+  int             count = len;
+
+  /* 
+   * Construct a flag to indicate whether the device is being accessed in
+   * blocking or non-blocking mode.
+   */
+
+  no_block = (flags & O_NONBLOCK);
+
+  /*
+   * When running in a multi threaded environment, obtain the "write_lock"
+   * semaphore. This ensures that writing to the device is thread-safe.
+   */
+
+  ALT_SEM_PEND (sp->write_lock, 0);
+
+  /*
+   * Loop transferring data from the input buffer to the transmit circular
+   * buffer. The loop is terminated once all the data has been transferred,
+   * or, (if in non-blocking mode) the buffer becomes full.
+   */
+
+  while (count)
+  {
+    /* Determine the next slot in the buffer to access */
+
+    next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK;
+
+    /* block waiting for space if necessary */
+
+    if (next == sp->tx_start)
+    {
+      if (no_block)
+      {
+        /* Set errno to indicate why this function returned early */
+ 
+        ALT_ERRNO = EWOULDBLOCK;
+        break;
+      }
+      else
+      {
+        /* Block waiting for space in the circular buffer */
+
+        /* First, ensure transmit interrupts are enabled to avoid deadlock */
+
+        context = alt_irq_disable_all ();
+        sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+                        ALTERA_AVALON_UART_CONTROL_DCTS_MSK);
+        IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+        alt_irq_enable_all (context);
+
+        /* wait for space to come free */
+
+        do
+        {
+          /*
+           * When running in a multi-threaded mode, we pend on the write event 
+           * flag set in the interrupt service routine. This avoids wasting CPU
+           * cycles waiting in this thread, when we could be doing something
+           * more profitable elsewhere.
+           */
+
+          ALT_FLAG_PEND (sp->events, 
+                         ALT_UART_WRITE_RDY,
+                         OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME,
+                         0);
+        }
+        while ((next == sp->tx_start));
+      }
+    }
+
+    count--;
+
+    /* Add the next character to the transmit buffer */
+
+    sp->tx_buf[sp->tx_end] = *ptr++;
+    sp->tx_end = next;
+  }
+
+  /*
+   * Now that access to the circular buffer is complete, release the write
+   * semaphore so that other threads can access the buffer.
+   */
+
+  ALT_SEM_POST (sp->write_lock);
+
+  /* 
+   * Ensure that interrupts are enabled, so that the circular buffer can 
+   * drain.
+   */
+
+  context = alt_irq_disable_all ();
+  sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK |
+                 ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
+  IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl);
+  alt_irq_enable_all (context);
+
+  /* return the number of bytes written */
+
+  return (len - count);
+}
+
+#endif /* fast driver */
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c
new file mode 100644
index 0000000..ef6b9e4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_generic_quad_spi_controller.c
@@ -0,0 +1,797 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2015 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <errno.h>
+#include <io.h>
+#include <string.h>
+#include <stddef.h>
+#include "sys/param.h"
+#include "alt_types.h"
+#include "altera_generic_quad_spi_controller_regs.h"
+#include "altera_generic_quad_spi_controller.h"
+#include "priv/alt_busy_sleep.h"
+#include "sys/alt_debug.h"
+#include "sys/alt_cache.h"
+
+
+ALT_INLINE alt_32 static alt_qspi_validate_read_write_arguments(alt_qspi_controller_dev *flash_info,alt_u32 offset, alt_u32 length);
+alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info);
+
+/*
+ *  Public API
+ *
+ *  Refer to “Using Flash Devices� in the
+ *  Developing Programs Using the Hardware Abstraction Layer chapter
+ *   of the Nios II Software Developer’s Handbook.
+ */
+
+
+ /**
+  * alt_qspi_controller_lock
+  *
+  *  Locks the range of the memory sectors, which 
+  *  protected from write and erase.
+  *
+  * Arguments:
+  * - *flash_info: Pointer to general flash device structure.
+  * - sectors_to_lock: Block protection bits in EPCQ/QSPI ==> Bit4 | Bit3 | Bit2 | Bit1 | Bit0
+  *                                                            TB  | BP3  | BP2  | BP1  | BP0
+  * For details of setting sectors protection, please refer to EPCQ/QSPI datasheet.
+  *  
+  * Returns:
+  * 0 -> success
+  * -EINVAL -> Invalid arguments
+  * -ETIME  -> Time out and skipping the looping after 0.7 sec.
+  * -ENOLCK -> Sectors lock failed.
+**/
+int alt_qspi_controller_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
+{
+    alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
+    alt_qspi_controller_dev* qspi_flash_info = NULL;
+    alt_u32 result = 0;
+    alt_32 status = 0;
+
+    /* return -EINVAL if flash_info is NULL */
+    if(NULL == flash_info || 0 > sectors_to_lock)
+    {
+    	return -EINVAL;
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+
+    /* sector value should occupy bits 17:8 */
+    mem_op_value = sectors_to_lock << 8;
+
+    /* sector protect commands 0b11 occupies lower 2 bits */
+    mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD;
+
+    /* write sector protect command to QSPI_MEM_OP register to protect sectors */
+    IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value);
+    
+    /* poll write in progress to make sure no operation is in progress */
+    status = alt_qspi_poll_for_write_in_progress(qspi_flash_info);
+    if(status != 0)
+    {
+    	return status;
+    }
+	
+	status = IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base);
+	result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */
+	result |= (status >> 3) & 0x08; /* extract out BP4 */
+    result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */
+
+	if(result != sectors_to_lock)
+	{
+		return -ENOLCK;
+	}
+
+    return 0;
+}
+
+/**
+ * alt_qspi_controller_get_info
+ *
+ * Pass the table of erase blocks to the user. This flash will return a single
+ * flash_region that gives the number and size of sectors for the device used.
+ *
+ * Arguments:
+ * - *fd: Pointer to general flash device structure.
+ * - **info: Pointer to flash region
+ * - *number_of_regions: Pointer to number of regions
+ *
+ * For details of setting sectors protection, please refer to EPCQ/QSPI datasheet.
+ *  
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ * -EIO -> Could be hardware problem.
+**/
+int alt_qspi_controller_get_info
+(
+    alt_flash_fd *fd, /** flash device descriptor */
+    flash_region **info, /** pointer to flash_region will be stored here */
+    int *number_of_regions /** number of regions will be stored here */
+)
+{
+	alt_flash_dev* flash = NULL;
+	
+	/* return -EINVAL if fd,info and number_of_regions are NULL */
+	if(NULL == fd || NULL == info || NULL == number_of_regions)
+    {
+    	return -EINVAL;
+    }
+
+    flash = (alt_flash_dev*)fd;
+
+    *number_of_regions = flash->number_of_regions;
+
+    if (!flash->number_of_regions)
+    {
+      return -EIO;
+    }
+    else
+    {
+      *info = &flash->region_info[0];
+    }
+
+    return 0;
+}
+
+/**
+  * alt_qspi_controller_erase_block
+  *
+  * This function erases a single flash sector.
+  *
+  * Arguments:
+  * - *flash_info: Pointer to QSPI flash device structure.
+  * - block_offset: byte-addressed offset, from start of flash, of the sector to be erased
+  *  
+  * Returns:
+  * 0 -> success
+  * -EINVAL -> Invalid arguments
+  * -EIO -> write failed, sector might be protected 
+**/
+int alt_qspi_controller_erase_block(alt_flash_dev *flash_info, int block_offset)
+{
+    alt_32 ret_code = 0;
+    alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
+    alt_qspi_controller_dev* qspi_flash_info = NULL;
+    alt_u32 sector_number = 0; 
+
+    /* return -EINVAL if flash_info is NULL */
+    if(NULL == flash_info)
+    {
+    	return -EINVAL;
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+
+    /* 
+     * Sanity checks that block_offset is within the flash memory span and that the 
+     * block offset is sector aligned.
+     *
+     */
+    if((block_offset < 0) 
+        || (block_offset >= qspi_flash_info->size_in_bytes)
+        || (block_offset & (qspi_flash_info->sector_size - 1)) != 0)
+    {
+    	return -EINVAL;
+    }
+
+    /* calculate current sector/block number */
+    sector_number = (block_offset/(qspi_flash_info->sector_size));
+
+    /* sector value should occupy bits 23:8 */
+    mem_op_value = (sector_number << 8) & ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK;
+
+    /* sector erase commands 0b10 occupies lower 2 bits */
+    mem_op_value |= ALTERA_QSPI_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD;
+
+    /* write sector erase command to QSPI_MEM_OP register to erase sector "sector_number" */
+    IOWR_ALTERA_QSPI_CONTROLLER_MEM_OP(qspi_flash_info->csr_base, mem_op_value);
+	
+    /* check whether erase triggered a illegal erase interrupt  */
+    if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) &
+            		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK) ==
+            				ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE)
+    {
+	    /* clear register */
+	    /* QSPI_ISR access is write one to clear (W1C) */
+    	IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base,
+    		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_ERASE_MASK );
+    	return -EIO; /* erase failed, sector might be protected */
+    }
+
+    return ret_code;
+}
+
+/**
+ * alt_qspi_controller_write_block
+ *
+ * This function writes one block/sector of data to flash. The length of the write can NOT 
+ * spill into the adjacent sector.
+ *
+ * It assumes that someone has already erased the appropriate sector(s).
+ *
+ * Arguments:
+ * - *flash_info: Pointer to QSPI flash device structure.
+ * - block_offset: byte-addressed offset, from the start of flash, of the sector to written to
+ * - data-offset: Byte offset (unaligned access) of write into flash memory. 
+ *                For best performance, word(32 bits - aligned access) offset of write is recommended.
+ * - *src_addr: source buffer
+ * - length: size of writing
+ *  
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ * -EIO -> write failed, sector might be protected 
+**/
+int alt_qspi_controller_write_block
+(
+    alt_flash_dev *flash_info, /** flash device info */
+    int block_offset, /** sector/block offset in byte addressing */
+    int data_offset, /** offset of write from base address */
+    const void *data, /** data to be written */
+    int length /** bytes of data to be written, >0 */
+)
+{
+    alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */
+    alt_u32 remaining_length = length; /** length left to write */
+    alt_u32 write_offset = data_offset; /** offset into flash to write too */
+
+    alt_qspi_controller_dev *qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+	
+    /* 
+     * Sanity checks that data offset is not larger then a sector, that block offset is 
+     * sector aligned and within the valid flash memory range and a write doesn't spill into 
+     * the adjacent flash sector.
+     */
+    if(block_offset < 0
+        || data_offset < 0
+        || NULL == flash_info
+        || NULL == data
+        || data_offset >= qspi_flash_info->size_in_bytes
+        || block_offset >= qspi_flash_info->size_in_bytes
+        || length > (qspi_flash_info->sector_size - (data_offset - block_offset))
+        || length < 0
+        || (block_offset & (qspi_flash_info->sector_size - 1)) != 0) 
+    {
+    	return -EINVAL;
+    }
+
+    /*
+     * Do writes one 32-bit word at a time.
+     * We need to make sure that we pad the first few bytes so they're word aligned if they are
+     * not already.
+     */
+    while (remaining_length > 0)
+    {
+    	alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
+    	alt_u32 padding = 0; /** bytes to pad the next word that is written */
+    	alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
+
+        /*
+         * we need to make sure the write is word aligned
+    	 * this should only be true at most 1 time
+    	 */
+        if (0 != (write_offset & (sizeof(alt_u32) - 1)))
+        {
+        	/*
+        	 * data is not word aligned
+        	 * calculate padding bytes need to add before start of a data offset
+        	 */
+            padding = write_offset & (sizeof(alt_u32) - 1);
+
+            /* update variables to account for padding being added */
+            bytes_to_copy -= padding;
+
+            if(bytes_to_copy > remaining_length)
+            {
+            	bytes_to_copy = remaining_length;
+            }
+
+            write_offset = write_offset - padding;
+            if(0 != (write_offset & (sizeof(alt_u32) - 1)))
+            {
+            	return -EINVAL;
+            }
+        }
+        else
+        {
+            if(bytes_to_copy > remaining_length)
+            {
+            	bytes_to_copy = remaining_length;
+            }
+        }
+
+        /* prepare the word to be written */
+        memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy);
+
+        /* update offset and length variables */
+        buffer_offset += bytes_to_copy;
+        remaining_length -= bytes_to_copy;
+
+        /* write to flash 32 bits at a time */
+        IOWR_32DIRECT(qspi_flash_info->data_base, write_offset, word_to_write);
+
+        /* check whether write triggered a illegal write interrupt */
+        if((IORD_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base) &
+        		ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) ==
+        				ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE)
+        {
+		    /* clear register */
+        	IOWR_ALTERA_QSPI_CONTROLLER_ISR(qspi_flash_info->csr_base,
+			ALTERA_QSPI_CONTROLLER_ISR_ILLEGAL_WRITE_MASK );
+        	return -EIO; /** write failed, sector might be protected */
+        }
+
+        /* update current offset */
+        write_offset = write_offset + sizeof(alt_u32);
+    }
+
+    return 0;
+}
+
+/**
+ * alt_qspi_controller_write
+ *
+ * Program the data into the flash at the selected address.
+ *
+ * The different between this function and alt_qspi_controller_write_block function
+ * is that this function (alt_qspi_controller_write) will automatically erase a block as needed
+ * Arguments:
+ * - *flash_info: Pointer to QSPI flash device structure.
+ * - offset: Byte offset (unaligned access) of write to flash memory. For best performance, 
+ *           word(32 bits - aligned access) offset of write is recommended.
+ * - *src_addr: source buffer
+ * - length: size of writing
+ *  
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ * -EIO -> write failed, sector might be protected 
+ *
+**/
+int alt_qspi_controller_write(
+    alt_flash_dev *flash_info, /** device info */
+    int offset, /** offset of write from base address */
+    const void *src_addr, /** source buffer */
+    int length /** size of writing */
+)
+{
+    alt_32 ret_code = 0;
+
+    alt_qspi_controller_dev *qspi_flash_info = NULL;
+
+    alt_u32 write_offset = offset; /** address of next byte to write */
+    alt_u32 remaining_length = length; /** length of write data left to be written */
+    alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */
+    alt_u32 i = 0;
+
+    /* return -EINVAL if flash_info and src_addr are NULL */
+	if(NULL == flash_info || NULL == src_addr)
+    {
+    	return -EINVAL;
+    }
+	
+	qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+	
+    /* make sure the write parameters are within the bounds of the flash */
+    ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length);
+
+	if(0 != ret_code)
+	{
+		return ret_code;
+	}
+
+    /*
+     * This loop erases and writes data one sector at a time. We check for write completion 
+     * before starting the next sector.
+     */
+    for(i = offset/qspi_flash_info->sector_size ; i < qspi_flash_info->number_of_sectors; i++)
+    {
+        alt_u32 block_offset = 0; /** block offset in byte addressing */
+    	alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */
+        alt_u32 length_to_write = 0; /** length to write to current sector */
+
+    	if(0 >= remaining_length)
+    	{
+    		break; /* out of data to write */
+    	}
+
+        /* calculate current sector/block offset in byte addressing */
+        block_offset = write_offset & ~(qspi_flash_info->sector_size - 1);
+           
+        /* calculate offset into sector/block if there is one */
+        if(block_offset != write_offset)
+        {
+            offset_within_current_sector = write_offset - block_offset;
+        }
+
+        /* erase sector */
+        ret_code = alt_qspi_controller_erase_block(flash_info, block_offset);
+
+        if(0 != ret_code)
+        {
+            return ret_code;
+        }
+
+        /* calculate the byte size of data to be written in a sector */
+        length_to_write = MIN(qspi_flash_info->sector_size - offset_within_current_sector, 
+                remaining_length);
+
+        /* write data to erased block */
+        ret_code = alt_qspi_controller_write_block(flash_info, block_offset, write_offset,
+            src_addr + buffer_offset, length_to_write);
+
+
+        if(0 != ret_code)
+        {
+            return ret_code;
+        }
+
+        /* update remaining length and buffer_offset pointer */
+        remaining_length -= length_to_write;
+        buffer_offset += length_to_write;
+        write_offset += length_to_write; 
+    }
+
+    return ret_code;
+}
+
+/**
+ * alt_qspi_controller_read
+ *
+ * There's no real need to use this function as opposed to using memcpy directly. It does
+ * do some sanity checks on the bounds of the read.
+ *
+ * Arguments:
+ * - *flash_info: Pointer to general flash device structure.
+ * - offset: offset read from flash memory.
+ * - *dest_addr: destination buffer
+ * - length: size of reading
+ *
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+**/
+int alt_qspi_controller_read
+(
+    alt_flash_dev *flash_info, /** device info */
+    int offset, /** offset of read from base address */
+    void *dest_addr, /** destination buffer */
+    int length /** size of read */
+)
+{
+    alt_32 ret_code = 0;
+	alt_qspi_controller_dev *qspi_flash_info = NULL;
+	
+	/* return -EINVAL if flash_info and dest_addr are NULL */
+	if(NULL == flash_info || NULL == dest_addr)
+    {
+    	return -EINVAL;
+    }
+	
+    qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+
+	/* validate arguments */
+	ret_code = alt_qspi_validate_read_write_arguments(qspi_flash_info, offset, length);
+
+	/* copy data from flash to destination address */
+	if(0 == ret_code)
+	{
+		memcpy(dest_addr, (alt_u8*)qspi_flash_info->data_base + offset, length);
+	}
+
+    return ret_code;
+}
+
+/**
+ * altera_qspi_controller_init
+ *
+ * alt_sys_init.c will call this function automatically through macro
+ *
+ * Information in system.h is checked against expected values that are determined by the silicon_id.
+ * If the information doesn't match then this system is configured incorrectly. Most likely the wrong
+ * type of EPCS or EPCQ/QSPI device was selected when instantiating the soft IP.
+ *
+ * Arguments:
+ * - *flash: Pointer to QSPI flash device structure.
+ *
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments.
+ * -ENODEV -> System is configured incorrectly.
+**/
+alt_32 altera_qspi_controller_init(alt_qspi_controller_dev *flash)
+{
+	alt_u32 silicon_id = 0;
+	alt_u32 size_in_bytes = 0;
+	alt_u32 number_of_sectors = 0;
+
+    /* return -EINVAL if flash is NULL */
+	if(NULL == flash)
+    {
+    	return -EINVAL;
+    }
+	
+	/* return -ENODEV if CSR slave is not attached */
+	if(NULL == (void *)flash->csr_base)
+	{
+		return -ENODEV;
+	}
+
+
+	/*
+	 * If flash is an EPCQ/QSPI device, we read the QSPI_RD_RDID register for the ID
+	 * If flash is an EPCS device, we read the QSPI_RD_SID register for the ID
+	 *
+	 * Whether or not the flash is a EPCQ, QSPI or EPCS is indicated in the system.h. The system.h gets
+	 * this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go
+	 * badly.
+	 *
+	 * In both cases, we can determine the number of sectors, which we can use
+	 * to calculate a size. We compare that size to the system.h value to make sure
+	 * the QSPI soft IP was configured correctly.
+	 */
+	if(0 == flash->is_epcs)
+	{
+		/* If we're an EPCQ or QSPI, we read QSPI_RD_RDID for the silicon ID */
+		silicon_id = IORD_ALTERA_QSPI_CONTROLLER_RDID(flash->csr_base);
+		silicon_id &= ALTERA_QSPI_CONTROLLER_RDID_MASK;
+
+		/* Determine which EPCQ/QSPI device so we can figure out the number of sectors */
+		/*EPCQ and QSPI share the same ID for the same capacity*/
+		switch(silicon_id)
+		{
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI16:
+			{
+				number_of_sectors = 32;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI32:
+			{
+				number_of_sectors = 64;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI64:
+			{
+				number_of_sectors = 128;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI128:
+			{
+				number_of_sectors = 256;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI256:
+			{
+				number_of_sectors = 512;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI512:
+			{
+				number_of_sectors = 1024;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_RDID_QSPI1024:
+			{
+				number_of_sectors = 2048;
+				break;
+			}
+			default:
+			{
+				return -ENODEV;
+			}
+		}
+	}
+	else {
+		/* If we're an EPCS, we read QSPI_RD_SID for the silicon ID */
+		silicon_id = IORD_ALTERA_QSPI_CONTROLLER_SID(flash->csr_base);
+		silicon_id &= ALTERA_QSPI_CONTROLLER_SID_MASK;
+
+		/* Determine which EPCS device so we can figure out various properties */
+		switch(silicon_id)
+		{
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS16:
+			{
+				number_of_sectors = 32;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS64:
+			{
+				number_of_sectors = 128;
+				break;
+			}
+			case ALTERA_QSPI_CONTROLLER_SID_EPCS128:
+			{
+				number_of_sectors = 256;
+				break;
+			}
+			default:
+			{
+				return -ENODEV;
+			}
+		}
+	}
+
+	/* Calculate size of flash based on number of sectors */
+	size_in_bytes = number_of_sectors * flash->sector_size;
+
+	/*
+	 * Make sure calculated size is the same size given in system.h
+	 * Also check number of sectors is the same number given in system.h
+	 * Otherwise the QSPI IP was not configured correctly
+	 */
+	if(	size_in_bytes != flash->size_in_bytes ||
+			number_of_sectors != flash->number_of_sectors)
+	{
+		flash->dev.number_of_regions = 0;
+		return -ENODEV;
+	}
+	else
+	{
+		flash->silicon_id = silicon_id;
+		flash->number_of_sectors = number_of_sectors;
+
+		/*
+		 * populate fields of region_info required to conform to HAL API
+		 * create 1 region that composed of "number_of_sectors" blocks
+		 */
+		flash->dev.number_of_regions = 1;
+		flash->dev.region_info[0].offset = 0;
+		flash->dev.region_info[0].region_size = size_in_bytes;
+		flash->dev.region_info[0].number_of_blocks = number_of_sectors;
+		flash->dev.region_info[0].block_size = flash->sector_size;
+	}
+
+
+    /*
+     * Register this device as a valid flash device type
+     *
+     * Only register the device if it's configured correctly.
+     */
+		alt_flash_device_register(&(flash->dev));
+
+
+    return 0;
+}
+
+
+/*
+ *	Private API
+ *
+ *	Helper functions used by Public API functions.
+ *  
+ * Arguments:
+ * - *flash_info: Pointer to QSPI flash device structure.
+ * - offset: Offset of read/write from base address.
+ * - length: Length of read/write in bytes.
+ *
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ */
+/**
+ * Used to check that arguments to a read or write are valid
+ */
+ALT_INLINE alt_32 static alt_qspi_validate_read_write_arguments
+(
+		alt_qspi_controller_dev *flash_info, /** device info */
+		alt_u32 offset, /** offset of read/write */
+		alt_u32 length /** length of read/write */
+)
+{
+    alt_qspi_controller_dev *qspi_flash_info = NULL;
+    alt_u32 start_address = 0;
+    alt_32 end_address = 0;
+	
+  /* return -EINVAL if flash_info is NULL */
+   if(NULL == flash_info)
+   {
+    	return -EINVAL;
+   }
+	
+  qspi_flash_info = (alt_qspi_controller_dev*)flash_info;
+
+  start_address = qspi_flash_info->data_base + offset; /** first address of read or write */
+  end_address = start_address + length; /** last address of read or write (not inclusive) */
+
+  /* make sure start and end address is less then the end address of the flash */
+  if(
+		  start_address >= qspi_flash_info->data_end ||
+		  end_address >= qspi_flash_info->data_end ||
+		  offset < 0 ||
+		  length < 0
+  )
+  {
+	  return -EINVAL;
+  }
+
+  return 0;
+}
+
+/*
+ * Private function that polls write in progress bit QSPI_RD_STATUS.
+ *
+ * Write in progress will be set if any of the following operations are in progress:
+ * 	-WRITE STATUS REGISTER
+ * 	-WRITE NONVOLATILE CONFIGURATION REGISTER
+ * 	-PROGRAM
+ * 	-ERASE
+ *
+ * Assumes QSPI was configured correctly.
+ *
+ * If ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE is set, the function will time out after
+ * a period of time determined by that value.
+ *
+ * Arguments:
+ * - *qspi_flash_info: Pointer to QSPI flash device structure.
+ *  
+ * Returns:
+ * 0 -> success
+ * -EINVAL -> Invalid arguments
+ * -ETIME  -> Time out and skipping the looping after 0.7 sec.
+ */
+alt_32 static alt_qspi_poll_for_write_in_progress(alt_qspi_controller_dev* qspi_flash_info)
+{  
+    /* we'll want to implement timeout if a timeout value is specified */
+#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0
+	alt_u32 timeout = ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE;
+	alt_u16 counter = 0;
+#endif
+
+    /* return -EINVAL if qspi_flash_info is NULL */
+	if(NULL == qspi_flash_info)
+    {
+    	return -EINVAL;
+    }
+
+	/* while Write in Progress bit is set, we wait */
+	while((IORD_ALTERA_QSPI_CONTROLLER_STATUS(qspi_flash_info->csr_base) &
+			ALTERA_QSPI_CONTROLLER_STATUS_WIP_MASK) ==
+			ALTERA_QSPI_CONTROLLER_STATUS_WIP_BUSY)
+	{
+        alt_busy_sleep(1); /* delay 1us */
+#if ALTERA_QSPI_CONTROLLER_1US_TIMEOUT_VALUE > 0
+		if(timeout <= counter )
+		{
+			return -ETIME;
+		}
+		
+		counter++;
+#endif
+
+	}
+
+	return 0;
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c
new file mode 100644
index 0000000..db8449c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_msgdma.c
@@ -0,0 +1,1806 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "altera_msgdma_descriptor_regs.h"
+#include "altera_msgdma_csr_regs.h"
+#include "altera_msgdma_response_regs.h"
+#include "io.h"
+#include "altera_msgdma.h"
+#include "priv/alt_busy_sleep.h"
+#include "sys/alt_errno.h"
+#include "sys/alt_irq.h"
+#include "sys/alt_stdio.h"
+#include "sys/alt_cache.h" 
+
+
+
+
+/*******************************************************************************
+ *  Private API
+ ******************************************************************************/
+static int alt_msgdma_write_standard_descriptor (
+    alt_u32 *csr_base,
+    alt_u32 *descriptor_base,
+    alt_msgdma_standard_descriptor *descriptor);
+static int alt_msgdma_write_extended_descriptor (
+    alt_u32 *csr_base, 
+    alt_u32 *descriptor_base,
+    alt_msgdma_extended_descriptor *descriptor);
+static void alt_msgdma_irq(void *context);
+static int alt_msgdma_construct_standard_descriptor(
+        alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address,
+    alt_u32 length, 
+    alt_u32 control);
+static int alt_msgdma_construct_extended_descriptor(
+        alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride);
+static int alt_msgdma_descriptor_async_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc);
+static int alt_msgdma_descriptor_sync_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc);
+/* The list of registered msgdma components */
+ALT_LLIST_HEAD(alt_msgdma_list);
+
+/* 
+ * Functions for writing descriptor structure to the dispatcher.  If you disable 
+ * some of the extended features in the hardware then you should pass in 0 for 
+ * that particular descriptor element. These disabled elements will not be 
+ * buffered by the dispatcher block.
+ * 
+ * This function is non-blocking and will return an error code if there is no 
+ * room to write another descriptor to the dispatcher. It is recommended to call
+ * 'read_descriptor_buffer_full' and make sure it returns '0' before calling 
+ * this function.
+ */
+static int alt_msgdma_write_standard_descriptor (
+    alt_u32 *csr_base, 
+    alt_u32 *descriptor_base,
+    alt_msgdma_standard_descriptor *descriptor)
+{
+    if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & 
+        ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK))
+    {
+      /*at least one descriptor buffer is full, returning so that this function 
+        is non-blocking*/
+        return -ENOSPC;
+    }
+
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(descriptor_base, 
+        (alt_u32)descriptor->read_address);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(descriptor_base, 
+    (    alt_u32)descriptor->write_address);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(descriptor_base, 
+        descriptor->transfer_length);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(descriptor_base, 
+        descriptor->control);
+        return 0;
+}
+
+/*
+ * This function is used for writing extended descriptors to the dispatcher.  
+   It handles only 32-bit descriptors.
+ */
+static int alt_msgdma_write_extended_descriptor (
+    alt_u32 *csr_base, 
+    alt_u32 *descriptor_base,
+    alt_msgdma_extended_descriptor *descriptor)
+{
+    if (0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(csr_base) & 
+        ALTERA_MSGDMA_CSR_DESCRIPTOR_BUFFER_FULL_MASK))
+    {
+      /*at least one descriptor buffer is full, returning so that this function 
+    is non-blocking*/
+        return -ENOSPC;
+    }
+
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(
+        descriptor_base, 
+        (alt_u32)descriptor->read_address_low);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(
+        descriptor_base, 
+        (alt_u32)descriptor->write_address_low);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(
+        descriptor_base, 
+        descriptor->transfer_length);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(
+        descriptor_base, 
+        descriptor->sequence_number);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(
+        descriptor_base, 
+        descriptor->read_burst_count);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(
+        descriptor_base, 
+        descriptor->write_burst_count);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(
+        descriptor_base, 
+        descriptor->read_stride);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(
+        descriptor_base, 
+        descriptor->write_stride);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(descriptor_base, 0);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS_HIGH(descriptor_base, 0);
+    IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ENHANCED(
+        descriptor_base, 
+        descriptor->control);
+    return 0;
+}
+
+/*
+ * alt_msgdma_irq()
+ *
+ * Interrupt handler for the Modular Scatter-Gather DMA controller.
+ */
+static void alt_msgdma_irq(void *context)
+{
+    alt_msgdma_dev *dev = (alt_msgdma_dev *) context;
+    alt_irq_context cpu_sr;
+    alt_u32 temporary_control;
+
+    
+    /* disable global interrupt*/
+    if (dev->prefetcher_enable)
+    {
+        temporary_control = 
+                IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)
+                & ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK;
+        
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base,
+                temporary_control);
+        
+        /* clear the IRQ status- W1C */
+        IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base,
+                ALT_MSGDMA_PREFETCHER_STATUS_IRQ_SET_MASK);
+    }
+    else
+    {
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+                & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+        
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+        /* clear the IRQ status */
+        IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base,
+                ALTERA_MSGDMA_CSR_IRQ_SET_MASK);
+    }
+
+    /* 
+    * Other interrupts are explicitly disabled if callbacks
+    * are registered because there is no guarantee that they are 
+    * pre-emption-safe. This allows the driver to support 
+    * interrupt pre-emption.
+    */
+    if(dev->callback) 
+    {
+        cpu_sr = alt_irq_disable_all();
+        dev->callback (dev->callback_context);
+        alt_irq_enable_all(cpu_sr);
+    }
+
+    /* enable global interrupt */
+    if (dev->prefetcher_enable)
+    {
+        temporary_control = 
+                IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)
+                | ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK;
+        
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base,
+                temporary_control);
+    }
+    else
+    {
+        temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) 
+                | (ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+        
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+    }
+
+    return;
+}
+/*
+ * Helper functions for constructing mm_to_st, st_to_mm, mm_to_mm standard 
+ * descriptors. Unnecessary elements are set to 0 for completeness and will be 
+ * ignored by the hardware.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+static int alt_msgdma_construct_standard_descriptor(
+        alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+    if(dev->max_byte < length ||
+       dev->enhanced_features != 0
+      )
+    {
+        return -EINVAL;
+    }
+    descriptor->read_address = read_address;
+    descriptor->write_address = write_address;
+    descriptor->transfer_length = length;
+    descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+    
+    return 0;
+}
+
+/*
+ * Helper functions for constructing mm_to_st, st_to_mm, mm_to_mm extended 
+ * descriptors. Unnecessary elements are set to 0 for completeness and will be 
+ * ignored by the hardware.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+static int alt_msgdma_construct_extended_descriptor(
+        alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+    if(dev->max_byte < length ||
+       dev->max_stride < read_stride ||
+       dev->max_stride < write_stride ||
+       dev->enhanced_features != 1 
+      )
+    {
+        return -EINVAL;
+    }
+    
+    descriptor->read_address_low = read_address;
+    descriptor->write_address_low = write_address;
+    descriptor->transfer_length = length;
+    descriptor->sequence_number = sequence_number;
+    descriptor->read_burst_count = read_burst_count;
+    descriptor->write_burst_count = write_burst_count;
+    descriptor->read_stride = read_stride;
+    descriptor->write_stride = write_stride;
+    descriptor->read_address_high = NULL;
+    descriptor->write_address_high = NULL;
+    descriptor->control = control | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+
+  return 0 ;
+
+}
+
+/*
+ * Helper functions for descriptor in async transfer.
+ * Arguments:# This driver supports HAL types
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - *standard_desc: Pointer to single standard descriptor.
+ * - *extended_desc: Pointer to single extended descriptor.
+ *
+ *note: Either one of both *standard_desc and *extended_desc must 
+ *      be assigned with NULL, another with proper pointer value.
+ *      Failing to do so can cause the function return with "-EPERM "
+ *
+ * If a callback routine has been previously registered with this
+ * particular msgdma controller, transfer will be set up to enable interrupt 
+ * generation. It is the responsibility of the application developer to check 
+ * source interruption, status completion and creating suitable interrupt 
+ * handling. Note: "stop on error" of CSR control register is always masking 
+ * within this function. The CSR control can be set by user through calling 
+ * "alt_register_callback" by passing user used defined control setting.
+ *
+ * Returns:
+ * 0 -> success
+ * -ENOSPC -> FIFO descriptor buffer is full
+ * -EPERM -> operation not permitted due to descriptor type conflict
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+static int alt_msgdma_descriptor_async_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc)
+{
+    alt_u32 control = 0;
+    alt_irq_context context = 0;
+    alt_u16 counter = 0;
+    alt_u32 fifo_read_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+    alt_u32 fifo_write_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET;
+
+    /* Return with error immediately if one of read/write buffer is full */
+    if((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+        (dev->descriptor_fifo_depth <= fifo_read_fill_level))
+    {
+        /*at least one write or read FIFO descriptor buffer is full,
+        returning so that this function is non-blocking*/
+        return -ENOSPC;
+    }
+    
+    /*
+    * When running in a multi threaded environment, obtain the "regs_lock"
+    * semaphore. This ensures that accessing registers is thread-safe.
+    */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+    
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* stop issuing more descriptors */
+    control = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+        dev->csr_base, 
+        IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+    alt_irq_enable_all(context);
+
+    if (NULL != standard_desc && NULL == extended_desc)
+    {
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+      write is succeed*/
+        while(0 != alt_msgdma_write_standard_descriptor (
+        dev->csr_base, dev->descriptor_base, standard_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+            {
+                alt_printf("time out after 5 msec while waiting" 
+                    " free FIFO buffer for storing standard descriptor\n");
+                
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+                
+                return -ETIME;
+            }
+            counter++; 
+        }
+    }
+    else if (NULL == standard_desc && NULL != extended_desc)
+    {
+        counter = 0; /* reset counter */
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+      write is succeed*/
+        while(0 != alt_msgdma_write_extended_descriptor (
+        dev->csr_base, 
+        dev->descriptor_base, 
+        extended_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+            {
+                alt_printf("time out after 5 msec while waiting free FIFO buffer" 
+                    " for storing extended descriptor\n");
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+                
+                return -ETIME;
+            }
+            counter++; 
+        }
+    }
+    else
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+        
+        /* operation not permitted due to descriptor type conflict */
+        return -EPERM; 
+    }
+
+    /*
+    * If a callback routine has been previously registered which will be
+    * called from the msgdma ISR. Set up controller to:
+    *  - Run
+    *  - Stop on an error with any particular descriptor
+    */
+    if(dev->callback)
+    {
+
+        control |= (dev->control |
+                    ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK |
+                    ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK );
+        control &=  (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+    /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all(); 
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+        alt_irq_enable_all(context);
+    }
+    /*
+    * No callback has been registered. Set up controller to:
+    *   - Run
+    *   - Stop on an error with any particular descriptor
+    *   - Disable interrupt generation
+    */
+    else
+    {
+        control |= (dev->control |
+                    ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK );
+        control &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) &
+                   (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+        /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all();
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+        alt_irq_enable_all(context);
+    }   
+
+    /*
+     * Now that access to the registers is complete, release the registers
+     * semaphore so that other threads can access the registers.
+     */
+    ALT_SEM_POST (dev->regs_lock);
+    
+    return 0;
+}
+
+/*
+ * Helper functions for descriptor in sync transfer.
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - *standard_desc: Pointer to single standard descriptor.
+ * - *extended_desc: Pointer to single extended descriptor.
+ *
+ * Note: Either one of both *standard_desc and *extended_desc must 
+ *      be assigned with NULL, another with proper pointer value.
+ *      Failing to do so can cause the function return with "-EPERM "
+ *
+ * "stop on error" of CSR control register is always being masked and interrupt 
+ * is always disabled within this function.
+ * The CSR control can be set by user through calling "alt_register_callback" 
+ * with passing user defined control setting.
+ *
+ * Returns:
+ * 0 -> success
+ * error -> errors or conditions causing msgdma stop issuing commands to masters. 
+ *          check the bit set in the error with CSR status register.
+ * -EPERM -> operation not permitted due to descriptor type conflict
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+static int alt_msgdma_descriptor_sync_transfer (
+    alt_msgdma_dev *dev, 
+    alt_msgdma_standard_descriptor *standard_desc, 
+    alt_msgdma_extended_descriptor *extended_desc)
+{
+    alt_u32 control=0;
+    alt_irq_context context=0;
+    alt_u32 csr_status = 0;
+    alt_u16 counter = 0;
+    alt_u32 fifo_read_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+    alt_u32 fifo_write_fill_level = (
+        IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+        ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET;
+    alt_u32 error = ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK | 
+                    ALTERA_MSGDMA_CSR_STOPPED_ON_EARLY_TERMINATION_MASK |
+                    ALTERA_MSGDMA_CSR_STOP_STATE_MASK |
+                    ALTERA_MSGDMA_CSR_RESET_STATE_MASK;
+    
+    /* Wait for available FIFO buffer to store new descriptor*/
+    while ((dev->descriptor_fifo_depth <= fifo_write_fill_level) || 
+        (dev->descriptor_fifo_depth <= fifo_read_fill_level))
+    { 
+        alt_busy_sleep(1); /* delay 1us */
+        if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+        {
+            alt_printf("time out after 5 msec while waiting free FIFO buffer"
+                " for storing descriptor\n");
+            return -ETIME;
+        }
+        counter++;  
+        fifo_read_fill_level = (
+            IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+            ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_MASK) >> 
+            ALTERA_MSGDMA_CSR_READ_FILL_LEVEL_OFFSET;
+        fifo_write_fill_level = (
+            IORD_ALTERA_MSGDMA_CSR_DESCRIPTOR_FILL_LEVEL(dev->csr_base) & 
+            ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_MASK) >> 
+            ALTERA_MSGDMA_CSR_WRITE_FILL_LEVEL_OFFSET;
+    }
+
+     /*
+     * When running in a multi threaded environment, obtain the "regs_lock"
+     * semaphore. This ensures that accessing registers is thread-safe.
+     */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+    
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base,
+        ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+        dev->csr_base, 
+        IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+
+    if (NULL != standard_desc && NULL == extended_desc)
+    {
+        counter = 0; /* reset counter */
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+          write is succeed*/
+        while(0 != alt_msgdma_write_standard_descriptor (
+            dev->csr_base, dev->descriptor_base, standard_desc))
+        {     
+            alt_busy_sleep(1); /* delay 1us */
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+            {
+                alt_printf("time out after 5 msec while writing standard" 
+                    " descriptor to FIFO\n");
+                
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+                
+                return -ETIME;
+            }
+            counter++;    
+        }
+    }
+    else if (NULL == standard_desc && NULL != extended_desc)
+    {
+        counter = 0; /* reset counter */
+        /*writing descriptor structure to the dispatcher, wait until descriptor 
+          write is succeed*/
+        while(0 != alt_msgdma_write_extended_descriptor (
+            dev->csr_base, dev->descriptor_base, extended_desc))
+        {
+            alt_busy_sleep(1); /* delay 1us */
+            if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+            {
+                alt_printf("time out after 5 msec while writing extended" 
+                    " descriptor to FIFO\n");
+                
+                /*
+                * Now that access to the registers is complete, release the 
+                * registers semaphore so that other threads can access the 
+                * registers.
+                */
+                ALT_SEM_POST (dev->regs_lock);
+                
+                return -ETIME;
+            }
+            counter++;
+        }
+    }
+    else
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+        
+        /* operation not permitted due to descriptor type conflict */
+        return -EPERM; 
+    }
+    
+    /*
+    * Set up msgdma controller to:
+    * - Disable interrupt generation
+    * - Run once a valid descriptor is written to controller
+    * - Stop on an error with any particular descriptor
+    */
+     IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base,
+        (dev->control |
+        ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK ) &
+        (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) &
+        (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK)) ;
+     
+    alt_irq_enable_all(context);
+     
+    counter = 0; /* reset counter */ 
+    
+    csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base);
+    
+    /* Wait for any pending transfers to complete or checking any errors or 
+    conditions causing descriptor to stop dispatching */
+    while (!(csr_status & error) && (csr_status & ALTERA_MSGDMA_CSR_BUSY_MASK))
+    {
+        alt_busy_sleep(1); /* delay 1us */
+        if(5000 <= counter) /* time_out if waiting longer than 5 msec */
+        {
+            alt_printf("time out after 5 msec while waiting for any pending" 
+                " transfer complete\n");
+            
+            /*
+            * Now that access to the registers is complete, release the registers
+            * semaphore so that other threads can access the registers.
+            */
+            ALT_SEM_POST (dev->regs_lock);
+            
+            return -ETIME;
+        }
+        counter++;
+        csr_status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base);
+    }
+    
+
+    /*Errors or conditions causing the dispatcher stopping issuing read/write 
+      commands to masters*/
+    if(0 != (csr_status & error))
+    {
+        /*
+        * Now that access to the registers is complete, release the registers
+        * semaphore so that other threads can access the registers.
+        */
+        ALT_SEM_POST (dev->regs_lock);
+        
+        return error;
+    }
+
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+    read or write masters  */
+    /* stop issuing more descriptors */
+    control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base) | 
+    ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();  
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, control);
+    /*
+    * Clear any (previous) status register information
+    * that might occlude our error checking later.
+    */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(
+        dev->csr_base, 
+        IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+        alt_irq_enable_all(context);
+
+    /*
+    * Now that access to the registers is complete, release the registers
+    * semaphore so that other threads can access the registers.
+    */
+    ALT_SEM_POST (dev->regs_lock);
+    
+    return 0;
+
+}
+
+/*
+ * Functions for constructing standard descriptors.  Unnecessary elements are
+ * set to 0 for completeness and will be ignored by the hardware.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+int alt_msgdma_construct_standard_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *write_address, alt_u32 length, alt_u32 control)
+{
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, NULL, 
+            write_address, length, control);
+}
+
+int alt_msgdma_construct_standard_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address,
+    alt_u32 length,
+    alt_u32 control)
+{
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, 
+            NULL, length, control);
+
+}
+
+int alt_msgdma_construct_standard_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+    return alt_msgdma_construct_standard_descriptor(dev, descriptor, read_address, 
+            write_address, length, control);
+}
+
+/*
+ * Functions for constructing extended descriptors.  If you disable some of the
+ * extended features in the hardware then you should pass in 0 for that 
+ * particular descriptor element. These disabled elements will not be buffered 
+ * by the dispatcher block.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+int alt_msgdma_construct_extended_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor,
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 write_burst_count, 
+    alt_u16 write_stride)
+{
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, 
+            NULL, write_address, length, control, sequence_number, 0, 
+            write_burst_count, 0, write_stride);
+}
+
+int alt_msgdma_construct_extended_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor,
+    alt_u32 *read_address,
+    alt_u32 length,
+    alt_u32 control,
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride)
+{
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, read_address, 
+            NULL, length, control, sequence_number, read_burst_count, 0, 
+            read_stride, 0);
+
+}
+
+int alt_msgdma_construct_extended_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *descriptor,
+    alt_u32 *read_address, 
+    alt_u32 *write_address, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+    return alt_msgdma_construct_extended_descriptor(dev, descriptor, 
+            read_address, write_address, length, control, sequence_number, 
+            read_burst_count, write_burst_count, read_stride, write_stride);
+
+}
+
+/********************** MSGDMA PREFETCHER PRIVATE APIs *************************/
+
+/*
+ * Base functions for constructing mm_to_st, st_to_mm, mm_to_mm standard 
+ * descriptors for the prefetcher. Unnecessary elements are set to 0 for 
+ * completeness and will be ignored by the hardware.
+ * The descriptor created will be suitable for park since this API will set next_ptr
+ * to itself as park_mode requires. Additionally OWN_BY_HW bit left as 0 (owned by sw) 
+ * until the prefetcher is started with this descriptor in the list. 
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+static int alt_msgdma_construct_prefetcher_standard_descriptor(
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor,
+    alt_u32 read_address, 
+    alt_u32 write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+    if(dev->max_byte < length ||
+       dev->enhanced_features != 0
+      )
+    {
+        return -EINVAL;
+    }
+    descriptor->read_address = read_address;
+    descriptor->write_address = write_address;
+    descriptor->transfer_length = length;
+    /* have descriptor point to itself for park_mode */
+    descriptor->next_desc_ptr = (alt_u32)descriptor;  
+    
+    /* clear control own_by_hw bit field (SW owns this descriptor)*/
+    descriptor->control = (control 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+    
+    return 0;
+}
+
+/*
+ * Base functions for constructing mm_to_st, st_to_mm, mm_to_mm extended 
+ * descriptors. Unnecessary elements are set to 0 for completeness and will be 
+ * ignored by the hardware. The descriptor created will be suitable for park 
+ * mode since this API will set next_ptr to itself as park_mode requires. 
+ * Additionally OWN_BY_HW bit left as 0 (owned by sw) until the prefetcher is 
+ * started with this descriptor in the list. 
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+static int alt_msgdma_construct_prefetcher_extended_descriptor(
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor,
+    alt_u32 read_address_high,
+    alt_u32 read_address_low,
+    alt_u32 write_address_high,
+    alt_u32 write_address_low, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u8 write_burst_count,
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+    msgdma_addr64 node_addr;
+    
+    if(dev->max_byte < length ||
+       dev->max_stride < read_stride ||
+       dev->max_stride < write_stride ||
+       dev->enhanced_features != 1 
+      )
+    {
+        return -EINVAL;
+    }
+    
+    descriptor->read_address_high = read_address_high;
+    descriptor->read_address_low = read_address_low;
+    descriptor->write_address_high = write_address_high;
+    descriptor->write_address_low = write_address_low;
+    descriptor->transfer_length = length;
+    descriptor->sequence_number = sequence_number;
+    descriptor->read_burst_count = read_burst_count;
+    descriptor->write_burst_count = write_burst_count;
+    descriptor->read_stride = read_stride;
+    descriptor->write_stride = write_stride;
+    /* have descriptor point to itself */
+    node_addr.u64 = (uintptr_t)descriptor;
+    descriptor->next_desc_ptr_low = node_addr.u32[0];  
+    descriptor->next_desc_ptr_high = node_addr.u32[1];
+    
+    /* clear control own_by_hw bit field (SW still owns this descriptor). */
+    descriptor->control = (control 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+
+  return 0 ;
+}
+
+
+/********************** MSGDMA PREFETCHER PUBLIC APIs ************************/
+
+/*
+ * Functions for constructing standard descriptors.  Unnecessary elements are
+ * set to 0 for completeness and will be ignored by the hardware.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+int alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor,
+    alt_u32 read_address,
+    alt_u32 write_address,
+    alt_u32 length,
+    alt_u32 control)
+{
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+            read_address, write_address, length, control);
+}
+
+int alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 write_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+            0, write_address, length, control);
+}
+    
+int alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *descriptor, 
+    alt_u32 read_address, 
+    alt_u32 length, 
+    alt_u32 control)
+{
+    return alt_msgdma_construct_prefetcher_standard_descriptor(dev, descriptor,
+            read_address, 0, length, control);
+}
+
+
+/*
+ * Functions for constructing extended descriptors.  If you disable some of the
+ * extended features in the hardware then you should pass in 0 for that 
+ * particular descriptor element. These disabled elements will not be buffered 
+ * by the dispatcher block.
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to argument which 
+ *                          has larger value than hardware setting value)
+ */
+int alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 write_address_high,
+    alt_u32 write_address_low, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number,
+    alt_u8 write_burst_count,
+    alt_u16 write_stride)
+{
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor, 
+            0, 0, write_address_high, write_address_low, length, control, 
+            sequence_number, 0, write_burst_count, 0, write_stride);
+}
+
+int alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 read_address_high,
+    alt_u32 read_address_low, 
+    alt_u32 length, 
+    alt_u32 control, 
+    alt_u16 sequence_number, 
+    alt_u8 read_burst_count, 
+    alt_u16 read_stride)
+{
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor,
+            read_address_high, read_address_low, 0, 0, length, control, 
+            sequence_number, read_burst_count, 0, read_stride, 0);
+}
+
+int alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *descriptor, 
+    alt_u32 read_address_high,
+    alt_u32 read_address_low,
+    alt_u32 write_address_high, 
+    alt_u32 write_address_low, 
+    alt_u32 length, 
+    alt_u32 control,
+    alt_u16 sequence_number,
+    alt_u8 read_burst_count,
+    alt_u8 write_burst_count, 
+    alt_u16 read_stride, 
+    alt_u16 write_stride)
+{
+    return alt_msgdma_construct_prefetcher_extended_descriptor(dev, descriptor,
+            read_address_high, read_address_low, write_address_high, 
+            write_address_low, length, control, sequence_number, 
+            read_burst_count, write_burst_count, read_stride, write_stride);
+
+}
+
+/* PREFETCHER linked list APIs */
+/*
+ * Function for adding standard descriptors to a standard descriptor list
+ * Returns:
+ * - status: return 0 (success)
+ *           return -EINVAL (invalid argument, could be due to descriptor 
+ *           already being in the list, descriptor pointer being NULL, or
+ *           descriptor.next_ptr not pointing back to itslef)
+ */
+int alt_msgdma_prefetcher_add_standard_desc_to_list (
+    alt_msgdma_prefetcher_standard_descriptor** list,
+    alt_msgdma_prefetcher_standard_descriptor* descriptor)
+{
+    alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr;
+    
+    if (descriptor == NULL)
+    {
+        return -EINVAL;  /* this descriptor cannot be NULL */
+    }
+    if (descriptor->next_desc_ptr != (alt_u32)descriptor)
+    {
+        return -EINVAL;  /* descriptor.next_ptr must point to itself */
+    }
+    if (*list == NULL)
+    {
+        *list = descriptor;  /* make this root-node if list is empty */
+        return 0;  /* successfully added */
+    }
+    if (*list == descriptor)
+    {
+        return -EINVAL;  /* this descriptor cannot already be root-node */
+    }
+    
+    /* get to last node in the list */
+    last_descr_ptr = *list; /* start at list root-node */
+    /* traverse list until you get the last node */
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)*list)  
+    {
+        if (last_descr_ptr->next_desc_ptr == (alt_u32)descriptor)
+        {
+            return -EINVAL;  /* descriptor cannot already be in the list */
+        }
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr);
+    }
+    /* add this descriptor to end of list */
+    last_descr_ptr->next_desc_ptr = (alt_u32)((uintptr_t)descriptor);
+    /* ensure new last pointer points the start of the list */
+    descriptor->next_desc_ptr = (alt_u32)((uintptr_t)*list);  
+    return 0; /* successfully added */
+}
+
+int alt_msgdma_prefetcher_add_extended_desc_to_list (
+    alt_msgdma_prefetcher_extended_descriptor** list,
+    alt_msgdma_prefetcher_extended_descriptor* descriptor)
+{
+    alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr;
+    msgdma_addr64 root_node_addr, next_node_addr;
+    
+    if (descriptor == NULL)
+    {
+        return -EINVAL;  /* this descriptor cannot be NULL */
+    }
+    
+    next_node_addr.u64 = (uintptr_t)descriptor;
+    if( (descriptor->next_desc_ptr_low != next_node_addr.u32[0]) ||
+        (descriptor->next_desc_ptr_high != next_node_addr.u32[1]))
+    {
+        return -EINVAL;  /* descriptor.next_ptr must point to itself */
+    }
+    
+    if (*list == NULL)
+    {
+        *list = descriptor;  /* make this the root-node if list is empty */
+        return 0;
+    }
+    if (*list == descriptor)
+    {
+        return -EINVAL;  /* this descriptor cannot already be root-node */
+    }
+    
+    /* get to last node in the list */
+    last_descr_ptr = *list; /* start at list root-node */
+    /* the last nodes next ptr should point to the root node*/
+    root_node_addr.u64 = (uintptr_t)*list;
+    
+    /* traverse list until you get the last node */
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+    {
+        /* first check if descriptor already in the list */
+        next_node_addr.u64 = (uintptr_t)descriptor;
+        if ((last_descr_ptr->next_desc_ptr_low == next_node_addr.u32[0])
+            && (last_descr_ptr->next_desc_ptr_high == next_node_addr.u32[1]))
+        {
+            return -EINVAL;  /* descriptor cannot already be in the list */
+        }
+        /* go to next node in list, using 64 bit address */
+        next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low;
+        next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high;
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64);
+    }
+    /* add this descriptor to end of list */
+    next_node_addr.u64 = (uintptr_t)descriptor;
+    last_descr_ptr->next_desc_ptr_low = next_node_addr.u32[0];
+    last_descr_ptr->next_desc_ptr_high = next_node_addr.u32[1];
+    /* ensure new last pointer points the beginning of the list */
+    descriptor->next_desc_ptr_low = root_node_addr.u32[0];
+    descriptor->next_desc_ptr_high = root_node_addr.u32[1];
+    return 0;
+}
+
+/*
+ * Function to set all the own-by-hw bits.  This is called right before starting 
+ * prefetcher since if the create descriptor APIs were used to create the descriptor
+ * list, then the set_by_hw bits are still set to SW owned. 
+ * Note the owned bits are automatically set when using the 
+ * alt_msgdma_start_prefetcher_with_std_desc_list function and in that case
+ * this function should not be used.
+ * This function includes options for setting the last descriptor in the
+ * chain to owned by software, and for flushing the descriptor list from dcache.
+ */ 
+int alt_msgdma_prefetcher_set_std_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)    
+{
+    alt_u32 descriptor_control_field = 0;
+    alt_msgdma_prefetcher_standard_descriptor *last_descr_ptr;
+    alt_u32 descriptor_count = 0;
+    
+    if (list == NULL)
+    {
+        return -EINVAL;  /* this list cannot be empty */
+    }
+
+    /* update all nodes in the list */
+    last_descr_ptr = list; /* start at list root-node */
+    /* traverse list to update all of the nodes */
+    while (last_descr_ptr->next_desc_ptr != (alt_u32)list)  
+    {
+        /* get current value */
+        descriptor_control_field = last_descr_ptr->control;
+        /* update own_by_hw bit only */
+        last_descr_ptr->control = descriptor_control_field 
+                | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;
+        /* go to next node in list */
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_standard_descriptor*)(last_descr_ptr->next_desc_ptr);
+            
+        descriptor_count++;
+    }
+    /* update the last node in the list, currently last_descr_ptr after while loop */
+    descriptor_control_field = last_descr_ptr->control;    /* get current value */
+    /* update own_by_hw bit only */
+    if (last_desc_owned_by_sw)
+    {
+        last_descr_ptr->control = descriptor_control_field 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK;
+    }
+    else {
+        last_descr_ptr->control = descriptor_control_field 
+            | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;        
+    }
+    
+    descriptor_count++;
+    
+    if (dcache_flush_desc_list)
+    {        
+        alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_standard_descriptor) * descriptor_count);
+    }
+    
+    return 0;
+}
+
+/*
+ * Function to set all the own-by-hw bits.  This is called right before starting 
+ * prefetcher since if the create descriptor APIs were used to create the descriptor
+ * list, then the set_by_hw bits are still set to SW owned. 
+ * Note the owned bits are automatically set when using the 
+ * alt_msgdma_start_prefetcher_with_extd_desc_list function and in that case
+ * this function should not be used.
+ * This function includes options for setting the last descriptor in the
+ * chain to owned by software, and for flushing the descriptor list from dcache.
+ */    
+int alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits (
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list) 
+{    
+    alt_u32 descriptor_control_field = 0;
+    msgdma_addr64 root_node_addr, next_node_addr;
+    alt_msgdma_prefetcher_extended_descriptor *last_descr_ptr;
+    alt_u32 descriptor_count = 0;
+    
+    if (list == NULL)
+    {
+        return -EINVAL;  /* this list cannot be empty */
+    }
+    
+    /* update all nodes in the list */
+    last_descr_ptr = list; /* start at list root-node */
+    /* the last nodes next ptr should point to the root node*/
+    root_node_addr.u64 = (uintptr_t)list;
+
+    /* traverse list until you get the last node */
+    while ((last_descr_ptr->next_desc_ptr_low != root_node_addr.u32[0]) 
+        || (last_descr_ptr->next_desc_ptr_high != root_node_addr.u32[1]))
+    {
+        /* start with current value */
+        descriptor_control_field = last_descr_ptr->control;
+        /* update own_by_hw bit only */
+        last_descr_ptr->control = descriptor_control_field 
+                | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;
+        /* go to next node in list, using 64 bit address */
+        next_node_addr.u32[0] = last_descr_ptr->next_desc_ptr_low;
+        next_node_addr.u32[1] = last_descr_ptr->next_desc_ptr_high;
+        last_descr_ptr = 
+            (alt_msgdma_prefetcher_extended_descriptor*)((uintptr_t)next_node_addr.u64);
+        descriptor_count++;            
+    }
+    /* update the last node in the list, currently last_descr_ptr after while loop */
+    descriptor_control_field = last_descr_ptr->control;    /* start with current value */
+    /* update own_by_hw bit only */
+    if (last_desc_owned_by_sw)
+    {
+        last_descr_ptr->control = descriptor_control_field 
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK;
+    }
+    else {
+        last_descr_ptr->control = descriptor_control_field 
+            | ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK;        
+    }
+    
+    descriptor_count++;
+    
+    if (dcache_flush_desc_list)
+    {        
+        alt_dcache_flush(list,sizeof(alt_msgdma_prefetcher_extended_descriptor) * descriptor_count);        
+    }
+    
+    return 0;
+}
+
+
+/*
+ * Functions to start the prefetcher.  Will return error if prefetcher already
+ * started.
+ * 
+ * Arguments:# This driver supports HAL types
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - *standard_desc: Pointer to single standard descriptor  OR  *extended_desc:
+ *      Pointer to single extended descriptor.
+ * -  park_mode_en:  setting for prefetcher park mode
+ * -  poll_en: setting for poll_en (IF poll frequency still 0 this API will 
+ *     also set that to a default non-zero value)
+ *
+ *note: Must call API specific to descriptor type. Either 
+ *     alt_msgdma_start_prefetcher_with_std_desc_list   OR
+ *     alt_msgdma_start_prefetcher_with_extd_desc_list  
+ *     where the list paratmeter is the root-node of your linked list. Then those
+ *      APIs will call the base function accordingly.
+ *
+ * If a callback routine has been previously registered with this
+ * particular msgdma controller, transfer will be set up to enable interrupt 
+ * generation. It is the responsibility of the application developer to check 
+ * source interruption, status completion and creating suitable interrupt 
+ * handling.
+ * Note: "stop on error" of CSR control register is always masking within this 
+ *     function. The CSR control can be set by user through calling 
+ *       "alt_register_callback" by passing user used defined control setting.
+ *
+ * Returns:
+ * 0 -> success
+ * -EBUSY -> prefetcher busy processing list already, it is up to user to stop
+ *  prefetcher/dispatcher correctly before calling this function.  
+ *  if already busy will always return error.
+ */
+
+/*
+ * Base function to start prefetcher.
+ */
+int alt_msgdma_start_prefetcher_with_list_addr (
+    alt_msgdma_dev *dev,
+    alt_u64  list_addr,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en)
+{
+    alt_u32 prefetcher_ctl = 0;
+    alt_u32 dispatcher_ctl = 0;
+    alt_irq_context context = 0;
+    
+    /* use helper struct to get easy access to hi/low address */
+    msgdma_addr64 root_node_addr;
+    root_node_addr.u64 = list_addr;  
+    
+    /*
+     * When running in a multi threaded environment, obtain the "regs_lock"
+     * semaphore. This ensures that accessing registers is thread-safe.
+     */
+    ALT_SEM_PEND (dev->regs_lock, 0);
+    
+    /* case where prefetcher already started, return busy error */ 
+    prefetcher_ctl = IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base);
+    if(ALT_MSGDMA_PREFETCHER_CTRL_RUN_GET(prefetcher_ctl)){
+        /* release the registers semaphore */
+        ALT_SEM_POST (dev->regs_lock);
+        return -EBUSY;
+    }
+        
+    /* Stop the msgdma dispatcher from issuing more descriptors to the
+       read or write masters  */
+    /* stop issuing more descriptors */
+    dispatcher_ctl = ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+    
+    /* making sure the read-modify-write below can't be pre-empted */
+    context = alt_irq_disable_all();
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+    /*
+     * Clear any (previous) status register information
+     * that might occlude our error checking later.
+     */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS( dev->csr_base, 
+            IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+    
+    alt_irq_enable_all(context);
+    
+    /*
+     * If a callback routine has been previously registered which will be
+     * called from the msgdma ISR. Set up dispatcher to:
+     *  - Run
+     *  - Stop on an error with any particular descriptor
+     */
+    if(dev->callback)
+    {
+        dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK 
+                | ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK );
+        dispatcher_ctl &=  (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK);
+        
+        prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK;
+        /* making sure the read-modify-write below can't be pre-empted */
+        context = alt_irq_disable_all(); 
+        IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+        alt_irq_enable_all(context);
+     }
+     /*
+      * No callback has been registered. Set up dispatcher to:
+      *   - Run
+      *   - Stop on an error with any particular descriptor
+      *   - Disable interrupt generation
+      */
+     else
+     {
+         dispatcher_ctl |= (dev->control | ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK);
+         dispatcher_ctl &= (~ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK) 
+                 & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_CLR_MASK;
+         /* making sure the read-modify-write below can't be pre-empted */
+         context = alt_irq_disable_all();
+         IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, dispatcher_ctl);
+         IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+         alt_irq_enable_all(context);
+     }   
+    
+     /* set next descriptor registers to point to the list root-node */
+     IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(dev->prefetcher_base,
+             root_node_addr.u32[0]);
+     IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(dev->prefetcher_base,
+             root_node_addr.u32[1]);
+        
+     /* set park-mode */
+     if (park_mode_en){
+         prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_SET_MASK;
+     }
+     else {
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_PARK_MODE_CLR_MASK;
+     }
+     
+     /* set poll-en */
+     if (poll_en){
+         prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_MASK; 
+         if(IORD_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(
+                 dev->prefetcher_base) == 0){
+             /* set poll frequency to some non-zero default value */
+             IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(
+                     dev->prefetcher_base, 0xFF);
+         }
+     }
+     else {
+         prefetcher_ctl &= ALT_MSGDMA_PREFETCHER_CTRL_DESC_POLL_EN_CLR_MASK; 
+     }
+     
+     /* set the prefetcher run bit */
+     prefetcher_ctl |= ALT_MSGDMA_PREFETCHER_CTRL_RUN_SET_MASK;
+     /* start the dma since run bit is set */
+     IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, prefetcher_ctl);
+     
+     /*
+      * Now that access to the registers is complete, release the registers
+      * semaphore so that other threads can access the registers.
+      */
+     ALT_SEM_POST (dev->regs_lock);
+     
+     return 0;
+}
+
+/*
+ * Public functions to start prefetcher.
+ * Note: The option last_desc_owned_by_sw has been added.
+ *       The last descriptor in a chain usually must be set to owned by sw.
+ *       In this case, the last descriptor does not actually transfer data.
+ *       When set, this option will set all descriptors in a chain to hw owned
+ *       and set the last to sw owned before starting the prefetcher.
+ * Note: The option dcache_flush_desc_list has been added.
+ *       When set this will call a function to flush the
+ *       descriptor list from dcache before starting the prefetcher.
+ *       If park_mode_en is not set, and poll_en is not set, it is recommended to
+ *       set both last_desc_owned_by_sw and dcache_flush_desc_list for proper
+ *       prefetcher operation.  
+ * Note: If options last_desc_owned_by_sw and dcache_flush_desc_list are not set
+ *       This function will behave exactly the same as in previous revisions.
+ * Note: It is not necessary to call any functions to set the owned by hw bits
+ *       before using these functions.
+ */
+int alt_msgdma_start_prefetcher_with_std_desc_list (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_standard_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)
+{    
+    if (alt_msgdma_prefetcher_set_std_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0)
+    {
+        return -EINVAL;
+    }
+
+    return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list,
+            park_mode_en, poll_en);
+}
+
+int alt_msgdma_start_prefetcher_with_extd_desc_list (
+    alt_msgdma_dev *dev,
+    alt_msgdma_prefetcher_extended_descriptor *list,
+    alt_u8 park_mode_en,
+    alt_u8 poll_en,
+    alt_u8 last_desc_owned_by_sw,
+    alt_u8 dcache_flush_desc_list)
+{
+    
+     if (alt_msgdma_prefetcher_set_extd_list_own_by_hw_bits(list,last_desc_owned_by_sw,dcache_flush_desc_list) != 0)
+    {
+        return -EINVAL;
+    }
+        
+    return alt_msgdma_start_prefetcher_with_list_addr (dev, (uintptr_t)list, 
+            park_mode_en, poll_en);
+}
+
+
+/*
+ * alt_msgdma_open - Retrieve a pointer to the msgdma
+ *
+ * Search the list of registered msgdma for one with the supplied name.
+ *
+ * The return value will be NULL on failure, and non-NULL otherwise.
+ *
+ * Arguments:
+ * - *name: Character pointer to name of msgdma peripheral as registered
+ *   with the HAL. For example, an msgdma controller named "msgdma_0"
+ *   in Qsys would be opened by asking for "/dev/msgdma_0_csr".
+ *
+ * Returns:
+ * - Pointer to msgdma device instance structure, or null if the device
+ *   could not be opened.
+ */
+alt_msgdma_dev* alt_msgdma_open (const char* name)
+{
+    alt_msgdma_dev* dev = NULL;
+
+    dev = (alt_msgdma_dev*) alt_find_dev (name, &alt_msgdma_list);
+
+    if (NULL == dev)
+    {
+        ALT_ERRNO = ENODEV;
+    }
+
+    return dev;
+}
+
+
+/*
+ * alt_msgdma_init()
+ *
+ * Initializes the Modular Scatter-Gather DMA controller. This routine is called
+ * from the ALTERA_MSGDMA_INIT macro and is called automatically
+ * by alt_sys_init.c
+ *
+ * This routine disables interrupts, descriptor processing,
+ * registers a specific instance of the device with the HAL,
+ * and installs an interrupt handler for the device.
+ */
+void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq)
+{
+    extern alt_llist alt_msgdma_list;
+    alt_u32 temporary_control;
+    int error;
+
+    if (dev->prefetcher_enable)
+    {
+        /* start prefetcher reset sequence */
+        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, 
+                ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
+        /* wait until hw clears the bit */
+        while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
+                IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)));
+        /*
+         * This reset is intended to be used along with reset dispatcher in 
+         * dispatcher core. Once the reset sequence in prefetcher core has 
+         * completed, software is expected to reset the dispatcher core, 
+         * and polls for dispatcher's reset sequence to be completed.
+         */
+    }    
+    
+    /* Reset the registers and FIFOs of the dispatcher and master modules */
+    /* set the reset bit, no need to read the control register first since 
+    this write is going to clear it out */
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK);
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+            & ALTERA_MSGDMA_CSR_RESET_STATE_MASK));
+    /*
+    * Disable interrupts, halt descriptor processing,
+    * and clear status register content
+    */
+
+    /* disable global interrupt */
+    temporary_control = IORD_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base)
+            & (~ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK);
+    /* stopping descriptor */
+    temporary_control |= ALTERA_MSGDMA_CSR_STOP_DESCRIPTORS_MASK;
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, temporary_control);
+
+    /* clear the CSR status register */
+    IOWR_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base, 
+            IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base));
+    
+    if (dev->prefetcher_enable)
+    {
+        /* clear all status bits that are set, since theyre W1C */
+        IOWR_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base, 
+                IORD_ALT_MSGDMA_PREFETCHER_STATUS(dev->prefetcher_base));
+    }
+
+    /* Register this instance of the msgdma controller with HAL */
+    alt_dev_llist_insert((alt_dev_llist*) dev, &alt_msgdma_list);
+
+    /*
+     * Creating semaphores used to protect access to the registers 
+     * when running in a multi-threaded environment.
+     */
+    error = ALT_SEM_CREATE (&dev->regs_lock, 1);
+            
+    if (!error)
+    {        
+        /* Install IRQ handler */
+        alt_ic_isr_register(ic_id, irq, alt_msgdma_irq, dev, 0x0);
+    }
+    else
+    {
+        alt_printf("failed to create semaphores\n");
+    }
+    
+    return;
+
+}
+
+
+/*
+ * alt_msgdma_register_callback
+ *
+ * Associate a user-specific routine with the msgdma interrupt handler.
+ * If a callback is registered, all non-blocking msgdma transfers will
+ * enable interrupts that will cause the callback to be executed.
+ * The callback runs as part of the interrupt service routine, and
+ * great care must be taken to follow the guidelines for acceptable
+ * interrupt service routine behaviour as described in the Nios II
+ * Software Developer's Handbook.However, user can change some of the CSR 
+ * control setting in blocking transfer by calling this function.
+ *
+ * Note: To disable callbacks after registering one, this routine
+ * may be called passing 0x0 to the callback argument.
+ *
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - callback: Pointer to callback routine to execute at interrupt level
+ * - control: For masking the source interruption and setting configuration in 
+ *            control register
+ */
+void alt_msgdma_register_callback(
+    alt_msgdma_dev *dev,
+    alt_msgdma_callback callback,
+    alt_u32 control,
+    void *context)
+{
+    dev->callback         = callback;
+    dev->callback_context = context;
+    dev->control          = control;
+
+    return ;
+}
+
+/*
+ * alt_msgdma_standard_descriptor_async_transfer
+ *
+ * Set up and commence a non-blocking transfer of one descriptors at a time.
+ *
+ * If the FIFO buffer for one of read/write is full at the time of this call, 
+ * the routine will immediately return -ENOSPC, the application can then decide 
+ * how to proceed without being blocked.
+ *
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) struct.
+ * - *desc: Pointer to single (ready to run) descriptor.
+ *
+ * Returns:
+ * 0 -> success
+ * -ENOSPC -> FIFO descriptor buffer is full
+ * -EPERM -> operation not permitted due to descriptor type conflict
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+int alt_msgdma_standard_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc)
+{
+   /*
+   * Error detection/handling should be performed at the application
+   * or callback level as appropriate.
+   */
+    return alt_msgdma_descriptor_async_transfer(dev, desc, NULL);
+
+}
+
+
+/*
+ * alt_msgdma_extended_descriptor_async_transfer
+ *
+ * Set up and commence a non-blocking transfer of one descriptors at a time.
+ *
+ * If the FIFO buffer for one of read/write is full at the time of this call, 
+ * the routine will immediately return -ENOSPC, the application can then
+ * decide how to proceed without being blocked.
+ *
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) struct.
+ * - *desc: Pointer to single (ready to run) descriptor.
+ *
+ * Returns:
+ * 0 -> success
+ * -ENOSPC -> FIFO descriptor buffer is full
+ * -EPERM -> operation not permitted due to descriptor type conflict
+ * -ETIME -> Time out and skipping the looping after 5 msec.
+ */
+int alt_msgdma_extended_descriptor_async_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc)
+{
+    /*
+    * Error detection/handling should be performed at the application
+    * or callback level as appropriate.
+    */
+    return alt_msgdma_descriptor_async_transfer(dev, NULL, desc);
+}
+
+
+/*
+ * alt_msgdma_standard_descriptor_sync_transfer
+ *
+ * This function will start commencing a blocking transfer of one standard 
+ * descriptor at a time. If the FIFO buffer for one of read/write is full at the 
+ * time of this call, the routine will wait until free FIFO buffer available for 
+ * continue processing.
+ *
+ * The function will return "-1" if errors or conditions causing the dispatcher 
+ * stop issuing the commands to both read and write masters before both read and 
+ * write command buffers are empty.
+ *
+ * Additional error information is available in the status bits of
+ * each descriptor that the msgdma processed; it is the responsibility
+ * of the user's application to search through the descriptor 
+ * to gather specific error information.
+ *
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - *desc: Pointer to single (ready to run) descriptor.
+ *
+ * Returns:
+ * - status: return 0 (success)
+ *           return error (errors or conditions causing msgdma stop issuing 
+ *               commands to masters)
+ *           Suggest suggest checking the bit set in the error with CSR status 
+ *               register.
+ *           return -EPERM (operation not permitted due to descriptor type 
+ *        conflict)
+ *           return -ETIME (Time out and skipping the looping after 5 msec)
+ */
+int alt_msgdma_standard_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_standard_descriptor *desc)
+{
+    return alt_msgdma_descriptor_sync_transfer(dev, desc, NULL);
+}
+
+/*
+ * alt_msgdma_extended_descriptor_sync_transfer
+ *
+ * This function will start commencing a blocking transfer of one extended 
+ * descriptor at a time. If the FIFO buffer for one of read/write is full at the 
+ * time of this call, the routine will wait until free FIFO buffer available for 
+ * continue processing.
+ *
+ * The function will return "-1" if errors or conditions causing the dispatcher 
+ * stop issuing the commands to both read and write masters before both read and 
+ * write command buffers are empty.
+ *
+ * Additional error information is available in the status bits of
+ * each descriptor that the msgdma processed; it is the responsibility
+ * of the user's application to search through the descriptor 
+ * to gather specific error information.
+ *
+ *
+ * Arguments:
+ * - *dev: Pointer to msgdma device (instance) structure.
+ * - *desc: Pointer to single (ready to run) descriptor.
+ *
+ * Returns:
+ * - status: return 0 (success)
+ *           return error (errors or conditions causing msgdma stop issuing 
+ *        commands to masters)
+ *           Suggest suggest checking the bit set in the error with CSR status 
+ *        register.
+ *           return -EPERM (operation not permitted due to descriptor type 
+ *        conflict)
+ *           return -ETIME (Time out and skipping the looping after 5 msec)
+ */
+int alt_msgdma_extended_descriptor_sync_transfer(
+    alt_msgdma_dev *dev,
+    alt_msgdma_extended_descriptor *desc)
+{
+    return alt_msgdma_descriptor_sync_transfer(dev, NULL, desc);
+}
+
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c b/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c
new file mode 100644
index 0000000..36482a4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/altera_onchip_flash.c
@@ -0,0 +1,590 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2014 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+#include <errno.h>
+#include <io.h>
+#include <string.h>
+#include "sys/param.h"
+#include "alt_types.h"
+#include "sys/alt_debug.h"
+#include "sys/alt_cache.h"
+#include "altera_onchip_flash.h"
+#include "altera_onchip_flash_regs.h"
+#include "priv/alt_busy_sleep.h"
+
+ALT_LLIST_HEAD(altera_onchip_flash_list);
+
+/*
+    Public API
+
+    Refer to "Using Flash Devices" in the
+    Developing Programs Using the Hardware Abstraction Layer chapter
+    of the Nios II Software Developer's Handbook.
+
+*/
+
+/**
+ * alt_onchip_flash_read
+ *
+ * reads data from flash.
+**/
+int alt_onchip_flash_read
+(
+    alt_flash_dev *flash_info,
+    int           offset,
+    void          *dest_addr,
+    int           length
+)
+{
+    int ret_code = 0;
+    alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if ((offset >= flash->dev.length) || ((offset+length) > flash->dev.length)) {
+        return -EFAULT;
+    }
+    
+    memcpy(dest_addr, (alt_u8*)flash->dev.base_addr+offset, length);
+
+    if (NULL != flash->csr_base) {
+        int read_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_READ_MSK;
+        if (read_status != ALTERA_ONCHIP_FLASH_STATUS_READ_PASSED) {
+            /* Read failed.  Return error.*/
+            ret_code = -EIO;
+        }
+    }
+    return ret_code;
+}
+
+/**
+ * alt_onchip_flash_get_info
+ *
+ * gets the details of the erase region.
+**/
+int alt_onchip_flash_get_info
+(
+    alt_flash_fd *fd,
+    flash_region **info,
+    int          *number_of_regions
+)
+{
+    int ret_code = 0;
+
+    alt_flash_dev* flash = (alt_flash_dev*)fd;
+
+    if (NULL != number_of_regions)
+    {
+        /* Pass the number of region to user */
+        *number_of_regions = flash->number_of_regions;
+    }
+
+    if (!flash->number_of_regions)
+    {
+        ret_code = -ENOMEM;
+    }
+    else if (flash->number_of_regions > ALT_MAX_NUMBER_OF_FLASH_REGIONS)
+    {
+        ret_code = -EFAULT;
+    }
+    else
+    {
+        if (NULL != info)
+        {
+            /* Pass the table of erase blocks to user */
+            *info = &flash->region_info[0];
+        }
+    }
+
+    return ret_code;
+}
+
+/**
+  This function erases an individual flash erase block.
+**/
+int alt_onchip_flash_erase_block
+(
+    alt_flash_dev *flash_info,
+    int           block_offset
+)
+{
+    int ret_code = 0;
+    alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info;
+    int page_address;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if (block_offset >= flash->dev.length) {
+        return -EFAULT;
+    }
+
+    /* Make sure IP support write and erase operation */
+    if ((flash->csr_base == NULL) || (flash->is_read_only)) {
+        return -ENODEV;
+    }
+
+    /* The block_offset must be page size aligned */
+    if ((block_offset & (flash->page_size - 1)) != 0)
+    {
+        /* The address is not aligned */
+        return -EINVAL;
+    }
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+    if (ret_code != 0)
+    {
+        return ret_code;
+    }
+
+    /* Enable write and erase operation */
+    ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+
+    /* Calculate Page erase address, it is 32bit word addressing*/
+    page_address = block_offset / 4;
+
+    /* Perform Page erase operation */
+    ALTERA_ONCHIP_FLASH_PAGE_ERASE(flash->csr_base, page_address);
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+
+    /* Wait until flash controller indicate erase passed */
+    ret_code = alt_onchip_flash_poll_for_status_erase_passed(flash);
+
+    /* Disable write and erase operation */
+    ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+
+    return ret_code;
+}
+
+/**
+ * alt_onchip_flash_write_block
+ *
+ * This function writes one block of data to flash.
+ * It assume that someone has kindly erased the appropriate sector(s).
+ *
+ * Note: "block_offset" is the base of the current erase block.
+ * "data_offset" is the absolute address (from the 0-base of this
+ * device's memory) of the beginning of the write-destination.
+ * This device has no need for "block_offset", but it's included for
+ * function type compatibility.
+**/
+int alt_onchip_flash_write_block
+(
+    alt_flash_dev *flash_info,
+    int           block_offset,
+    int           data_offset,
+    const void    *data,
+    int           length
+)
+{
+    int ret_code = 0;
+    alt_onchip_flash_dev *flash = (alt_onchip_flash_dev*)flash_info;
+    int buffer_offset = 0;
+    int length_of_current_write;
+    int current_data_offset = data_offset;
+    int next_data_offset;
+    alt_u32 chunk_of_data;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if (
+        (block_offset >= flash->dev.length) ||
+        (data_offset >= flash->dev.length) ||
+        (length > (flash->dev.length - data_offset))
+    ) {
+        return -EFAULT;
+    }
+
+    /* Make sure IP support support write and erase operation */
+    if ((flash->csr_base == NULL) || (flash->is_read_only != 0)) {
+        return -ENODEV;
+    }
+
+    /* Wait until flash controller idle */
+    ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+    if (ret_code != 0)
+    {
+        return ret_code;
+    }
+
+    /* Enable write and erase operation */
+    ALTERA_ONCHIP_FLASH_ENABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+
+    /* Check data length */
+    while (length)
+    {
+        /* Minimum write size to onchip flash is 32 bits of data */
+        chunk_of_data = 0xFFFFFFFF;
+
+        /* The start of data_offset must be 4 bytes (32 bits) aligned */
+        if ((current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1)) == 0)
+        {
+            /* The address is 4-byte aligned here */
+            next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+            length_of_current_write = MIN(length, next_data_offset - current_data_offset);
+            /* Prepare the 4 bytes chunk of data to be written */
+            memcpy(&chunk_of_data, &((alt_u8*)data)[buffer_offset], length_of_current_write);
+            buffer_offset += length_of_current_write;
+            length -= length_of_current_write;
+        } else {
+            /* Calculate how many padding bytes need to be added before the start of a data offset */
+            int padding = current_data_offset & (ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+
+            /* Calculate new 4-byte aligned data offset */
+            current_data_offset = current_data_offset - padding;
+            next_data_offset = (current_data_offset + ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE) & ~(ALTERA_ONCHIP_FLASH_DATA_ALIGN_SIZE - 1);
+            length_of_current_write = MIN(length + padding, next_data_offset - current_data_offset);
+            /* Prepare the 4 bytes chunk of data to be written */
+            memcpy((void *)(((int)&chunk_of_data) + (int)padding), &((alt_u8*)data)[buffer_offset], length_of_current_write - padding);
+            buffer_offset += length_of_current_write - padding;
+            length -= length_of_current_write - padding;
+        }
+
+        /* Writing to flash via IO 32 bits at a time */
+        IOWR_32DIRECT(flash->dev.base_addr, current_data_offset, chunk_of_data);
+
+        /* Wait until flash controller idle */
+        ret_code = alt_onchip_flash_poll_for_status_to_go_idle(flash);
+        if (ret_code != 0)
+        {
+            break;
+        }
+
+        /* Wait until flash controller indicate write passed */
+        ret_code = alt_onchip_flash_poll_for_status_write_passed(flash);
+        if (ret_code != 0)
+        {
+            break;
+        }
+
+        /* Prepare to write next 4 bytes */
+        current_data_offset = next_data_offset;
+    }
+
+    /* Disable write and erase operation */
+    ALTERA_ONCHIP_FLASH_DISABLE_WRITE_AND_ERASE_OPERATION(flash->csr_base);
+
+    return ret_code;
+}
+
+/**
+ * alt_onchip_flash_write
+ *
+ * Program the data into the flash at the selected address.
+ *
+ * The different between this function and alt_onchip_flash_write_block function
+ * is that this function (alt_onchip_flash_write) will automatically erase a block as needed
+ *
+**/
+int alt_onchip_flash_write(
+    alt_flash_dev *flash_info,
+    int           offset,
+    const void    *src_addr,
+    int           length
+)
+{
+    int         ret_code = 0;
+    int         i,j;
+    int         data_to_write;
+    int         current_offset;
+    int         full_length = length;
+    int         start_offset = offset;
+    alt_onchip_flash_dev* flash = (alt_onchip_flash_dev*)flash_info;
+
+    /* Make sure the input parameters is not outside of this device's range. */
+    if ((offset >= flash->dev.length) || (length > (flash->dev.length - offset)))
+    {
+        return -EFAULT;
+    }
+
+    /*
+    * First and foremost which sectors are affected?
+    */
+    for(i=0;i<flash->dev.number_of_regions;i++)
+    {
+        /* Is it in this erase block region?*/
+        if((offset >= flash->dev.region_info[i].offset) &&
+            (offset < (flash->dev.region_info[i].offset +
+            flash->dev.region_info[i].region_size)))
+        {
+            current_offset = flash->dev.region_info[i].offset;
+
+            for(j=0;j<flash->dev.region_info[i].number_of_blocks;j++)
+            {
+                if ((offset >= current_offset ) &&
+                    (offset < (current_offset +
+                    flash->dev.region_info[i].block_size)))
+                {
+                    /*
+                    * Check if the contents of the block are different
+                    * from the data we wish to put there
+                    */
+                    data_to_write = (current_offset + flash->dev.region_info[i].block_size - offset);
+                    data_to_write = MIN(data_to_write, length);
+                    if(memcmp(src_addr, (alt_u8*)flash->dev.base_addr+offset, data_to_write))
+                    {
+                        ret_code = (*flash->dev.erase_block)(&flash->dev, current_offset);
+
+                        if (!ret_code)
+                        {
+                            ret_code = (*flash->dev.write_block)(
+                                                                &flash->dev,
+                                                                current_offset,
+                                                                offset,
+                                                                src_addr,
+                                                                data_to_write);
+                        }
+                    }
+
+                    /* Was this the last block? */
+                    if ((length == data_to_write) || ret_code)
+                    {
+                        goto finished;
+                    }
+
+                    length -= data_to_write;
+                    offset = current_offset + flash->dev.region_info[i].block_size;
+                    src_addr = (alt_u8*)src_addr + data_to_write;
+                }
+                current_offset += flash->dev.region_info[i].block_size;
+            }
+        }
+    }
+
+finished:
+    alt_dcache_flush((alt_u8*)flash->dev.base_addr+start_offset, full_length);
+    return ret_code;
+}
+
+/**
+ * altera_onchip_flash_init
+ *
+ * alt_sys_init.c will call this function automatically through macro
+ *
+**/
+void altera_onchip_flash_init
+(
+    alt_onchip_flash_dev *flash
+)
+{
+    /* A region is a sector of the onchip flash */
+    int number_of_regions;
+    flash_region* region_info;
+    int sector1_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_AVAILABLE;
+    int sector2_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_AVAILABLE;
+    int sector3_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_AVAILABLE;
+    int sector4_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_AVAILABLE;
+    int sector5_status = ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_AVAILABLE;
+
+    /* Set up flash_region data structures. */
+    number_of_regions = 0;
+    region_info = &flash->dev.region_info[0];
+
+    if (flash->csr_base != NULL) {
+        sector1_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_MSK;
+        sector2_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_MSK;
+        sector3_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_MSK;
+        sector4_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_MSK;
+        sector5_status = IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) & ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_MSK;
+    }
+
+    if ((flash->sector1_enabled == 1) && (sector1_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR1_UNAVAILABLE)) {
+
+        region_info[number_of_regions].offset = flash->sector1_start_addr;
+        region_info[number_of_regions].region_size = flash->sector1_end_addr - flash->sector1_start_addr + 1;
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+        region_info[number_of_regions].block_size = flash->page_size;
+
+        number_of_regions++;
+    }
+
+    if ((flash->sector2_enabled == 1) && (sector2_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR2_UNAVAILABLE)) {
+
+        region_info[number_of_regions].offset = flash->sector2_start_addr;
+        region_info[number_of_regions].region_size = flash->sector2_end_addr - flash->sector2_start_addr + 1;
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+        region_info[number_of_regions].block_size = flash->page_size;
+
+        number_of_regions++;
+	}
+
+    if ((flash->sector3_enabled == 1) && (sector3_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR3_UNAVAILABLE)) {
+
+        region_info[number_of_regions].offset = flash->sector3_start_addr;
+        region_info[number_of_regions].region_size = flash->sector3_end_addr - flash->sector3_start_addr + 1;
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+        region_info[number_of_regions].block_size = flash->page_size;
+
+        number_of_regions++;
+	}
+
+	if ((flash->sector4_enabled == 1) && (sector4_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR4_UNAVAILABLE)) {
+
+        region_info[number_of_regions].offset = flash->sector4_start_addr;
+        region_info[number_of_regions].region_size = flash->sector4_end_addr - flash->sector4_start_addr + 1;
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+        region_info[number_of_regions].block_size = flash->page_size;
+
+        number_of_regions++;
+	}
+
+    if ((flash->sector5_enabled == 1) && (sector5_status != ALTERA_ONCHIP_FLASH_STATUS_SECTOR5_UNAVAILABLE)) {
+
+        region_info[number_of_regions].offset = flash->sector5_start_addr;
+        region_info[number_of_regions].region_size = flash->sector5_end_addr - flash->sector5_start_addr + 1;
+        region_info[number_of_regions].number_of_blocks = flash->dev.region_info[number_of_regions].region_size / flash->page_size;
+        region_info[number_of_regions].block_size = flash->page_size;
+
+        number_of_regions++;
+    }
+
+    /* Update number of regions. */
+    flash->dev.number_of_regions = number_of_regions;
+
+    /*
+    *  Register this device as a valid flash device type
+    */
+    alt_flash_device_register(&(flash->dev));
+}
+
+/*
+	Private API
+
+	Helper functions used by Public API functions.
+*/
+
+
+/**
+ * alt_onchip_flash_poll_for_status_to_go_idle
+ *
+ * This function return non zero value when polling timeout.
+**/
+int alt_onchip_flash_poll_for_status_to_go_idle
+(
+    alt_onchip_flash_dev *flash
+)
+{
+    int ret_code = 0;
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+
+    while (
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_BUSY_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_BUSY_IDLE
+    ) {
+	 
+	alt_busy_sleep(1); /* delay 1us */
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+            count_down--;
+            if (count_down == 0) {
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+                break;
+            }
+        }
+    }
+
+    return ret_code;
+}
+
+/**
+ * alt_onchip_flash_poll_for_status_erase_passed
+ *
+ * This function return non zero value when polling timeout.
+**/
+int alt_onchip_flash_poll_for_status_erase_passed
+(
+    alt_onchip_flash_dev *flash
+)
+{
+    int ret_code = 0;
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+
+    while (
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_ERASE_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_ERASE_PASSED
+    ) {
+
+	alt_busy_sleep(1); /* delay 1us */
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+            count_down--;
+            if (count_down == 0) {
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+                break;
+            }
+        }
+    }
+
+    return ret_code;
+}
+
+/**
+ * alt_onchip_flash_poll_for_status_write_passed
+ *
+ * This function return non zero value when polling timeout.
+**/
+int alt_onchip_flash_poll_for_status_write_passed
+(
+    alt_onchip_flash_dev *flash
+)
+{
+    int ret_code = 0;
+    int timeout = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+    int count_down = ALTERA_ONCHIP_FLASH_STATUS_BIT_POLLING_TIMEOUT_VALUE;
+
+    while (
+        (IORD_ALTERA_ONCHIP_FLASH_STATUS(flash->csr_base) &
+              ALTERA_ONCHIP_FLASH_STATUS_WRITE_MSK
+        ) !=  ALTERA_ONCHIP_FLASH_STATUS_WRITE_PASSED
+    ) {
+
+	alt_busy_sleep(1); /* delay 1us */
+
+        /* If timeout value is zero, it will never timeout. */
+        if (timeout != 0) {
+            count_down--;
+            if (count_down == 0) {
+                /* Timeout */
+                ret_code = -ETIMEDOUT;
+                break;
+            }
+        }
+    }
+
+    return ret_code;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c b/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c
new file mode 100644
index 0000000..92070f0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/drivers/src/iniche/ins_tse_mac.c
@@ -0,0 +1,911 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2016 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+#ifdef ALT_INICHE
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <io.h>
+#include <os_cpu.h>
+#include "ipport.h"
+
+#ifdef UCOS_II  
+#include <ucos_ii.h>
+#endif
+
+#include "in_utils.h"
+#include "netbuf.h"
+#include "net.h"
+#include "q.h"
+#include "ether.h"
+#include "system.h"
+#include "alt_types.h"
+
+#include "altera_avalon_timer_regs.h"
+#include "altera_msgdma_descriptor_regs.h"
+#include "altera_avalon_tse.h"
+
+#include "sys/alt_irq.h"
+#include "sys/alt_cache.h"
+
+#include "altera_eth_tse_regs.h"
+#include "iniche/altera_eth_tse_iniche.h"
+#include "iniche/ins_tse_mac.h"
+
+#include "socket.h"
+
+/* Task includes */
+#include "ipport.h"
+#include "tcpapp.h"
+
+#ifndef ALT_INICHE
+#include "osport.h"
+#endif
+
+#ifdef ALT_INICHE
+#include <errno.h>
+#include "alt_iniche_dev.h"
+#endif
+
+ins_tse_info tse[MAXNETS];
+extern alt_tse_system_info tse_mac_device[MAXNETS];
+
+alt_u8 number_of_tse_mac = 0;
+alt_tse_iniche_dev_driver_data tse_iniche_dev_driver_data[MAXNETS];
+extern alt_u8 max_mac_system;
+
+#ifdef ALT_INICHE
+
+
+/* @Function Description: TSE MAC Driver Open/Initialization routine
+ * @API TYPE: Public
+ * @Param p_dec     pointer to TSE device instance
+ * @Return ENP_HARDWARE on error, otherwise return SUCCESS
+ */
+
+error_t altera_eth_tse_init(
+    alt_iniche_dev              *p_dev)
+{
+    int i;
+    
+    alt_tse_iniche_dev_driver_data *p_driver_data = 0;
+    alt_tse_system_info *psys_info = 0;
+
+    dprintf("altera_eth_tse_init %d\n", p_dev->if_num);
+       
+    /* Get the pointer to the alt_tse_iniche_dev_driver_data structure from the global array */
+    for(i = 0; i < number_of_tse_mac; i++) {
+        if(tse_iniche_dev_driver_data[i].p_dev == p_dev) {
+            p_driver_data = &tse_iniche_dev_driver_data[i];
+        }
+    }
+    /* If pointer could not found */
+    if(p_driver_data == 0) {
+        return ENP_HARDWARE;
+    }
+    
+    /* Get the pointer to the alt_tse_system_info structure from the global array */
+    for(i = 0; i < max_mac_system; i++) {
+        if(tse_mac_device[i].tse_mac_base == p_driver_data->hw_mac_base_addr) {
+            psys_info = &tse_mac_device[i];
+        }
+    }
+    /* If pointer could not found */
+    if(psys_info == 0) {
+        return ENP_HARDWARE;
+    }
+    
+    prep_tse_mac(p_dev->if_num, psys_info + p_driver_data->hw_channel_number);
+    
+    return SUCCESS;
+}
+#endif /* ALT_INICHE */
+
+
+/* @Function Description: TSE MAC Driver Open/Registration routine
+ * @API TYPE: Internal
+ * @Param index     index of the NET structure associated with TSE instance
+ * @Param psys_info pointer to the TSE hardware info structure
+ * @Return next index of NET
+ */
+int prep_tse_mac(int index, alt_tse_system_info *psys_info)
+{
+    NET ifp;
+    dprintf("prep_tse_mac %d\n", index);
+    {
+        tse[index].sem = 0; /*Tx IDLE*/
+        tse[index].tse = (void *)psys_info;
+
+        ifp = nets[index];
+        ifp->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN; /* status = down */
+        ifp->n_mib->ifOperStatus =  ALTERA_TSE_ADMIN_STATUS_DOWN;   
+        ifp->n_mib->ifLastChange =  cticks * (100/TPS);
+        ifp->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr;
+        ifp->n_mib->ifDescr =       "Altera TSE MAC ethernet";
+        ifp->n_lnh =                ETHHDR_SIZE; /* ethernet header size. was:14 */
+        ifp->n_hal =                ALTERA_TSE_HAL_ADDR_LEN;  /* hardware address length */
+        ifp->n_mib->ifType =        ETHERNET;   /* device type */
+        ifp->n_mtu =                ALTERA_TSE_MAX_MTU_SIZE;  /* max frame size */
+    
+        /* install our hardware driver routines */
+        ifp->n_init =       tse_mac_init;
+        ifp->pkt_send =     NULL;
+        ifp->raw_send =     tse_mac_raw_send;
+        ifp->n_close =      tse_mac_close;
+        ifp->n_stats =      (void(*)(void *, int))tse_mac_stats; 
+    
+    #ifdef IP_V6
+        ifp->n_flags |= (NF_NBPROT | NF_IPV6);
+    #else
+        ifp->n_flags |= NF_NBPROT;
+    #endif
+    
+        nets[index]->n_mib->ifPhysAddress = (u_char*)tse[index].mac_addr;   /* ptr to MAC address */
+    
+    #ifdef ALT_INICHE
+        /* get the MAC address. */
+        get_mac_addr(ifp, (unsigned char *)tse[index].mac_addr);
+    #endif /* ALT_INICHE */
+    
+        /* set cross-pointers between iface and tse structs */
+        tse[index].index = index;
+        tse[index].netp = ifp;
+        ifp->n_local = (void*)(&tse[index]);
+    
+        index++;
+   }
+ 
+   return index;
+}
+
+//temporary code for msgdma hw workaround
+void msgdma_reset(alt_msgdma_dev * dev)
+{
+
+   /* start prefetcher reset sequence */
+   IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, 
+   ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
+   /* wait until hw clears the bit */
+   while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
+       IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)));
+   /*
+    * This reset is intended to be used along with reset dispatcher in 
+    * dispatcher core. Once the reset sequence in prefetcher core has 
+    * completed, software is expected to reset the dispatcher core, 
+    * and polls for dispatcher?s reset sequence to be completed.
+    */
+
+    /* Reset the registers and FIFOs of the dispatcher and master modules */
+    /* set the reset bit, no need to read the control register first since 
+    this write is going to clear it out */
+    IOWR_ALTERA_MSGDMA_CSR_CONTROL(dev->csr_base, ALTERA_MSGDMA_CSR_RESET_MASK);
+    while(0 != (IORD_ALTERA_MSGDMA_CSR_STATUS(dev->csr_base)
+                   & ALTERA_MSGDMA_CSR_RESET_STATE_MASK));
+
+}  
+
+/* @Function Description: TSE MAC Initialization routine. This function opens the
+ *                        device handle, configure the callback function and interrupts ,
+ *                        for MSGDMA TX and MSGDMA RX block associated with the TSE MAC,
+ *                        Initialize the MAC Registers for the RX FIFO and TX FIFO
+ *                        threshold watermarks, initialize the tse device structure,
+ *                        set the MAC address of the device and enable the MAC   
+ * 
+ * @API TYPE: Internal
+ * @Param iface index of the NET structure associated with TSE instance
+ * @Return 0 if ok, else -1 if error
+ */
+int tse_mac_init(int iface)
+{
+   int dat;
+   int speed, duplex, result, x;
+   int status = SUCCESS;
+   
+   alt_msgdma_dev *msgdma_tx_dev;
+   alt_msgdma_dev *msgdma_rx_dev;
+   alt_tse_system_info* tse_hw = (alt_tse_system_info *) tse[iface].tse;
+   
+   dprintf("tse_mac_init %d\n", iface);
+
+    if (tse_hw->ext_desc_mem == 1) {
+        tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *) tse_hw->desc_mem_base;
+        tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *) 
+               (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))));          
+        tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *) 
+               (tse_hw->desc_mem_base + ((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE+1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor))));          
+    }
+    else {
+        tse[iface].rxdesc[0] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+        while ((((alt_u32)tse[iface].rxdesc[0]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+        tse[iface].rxdesc[0]++;  //boundary
+          
+        tse[iface].rxdesc[1] = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+        while ((((alt_u32)tse[iface].rxdesc[1]) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0) 
+        tse[iface].rxdesc[1]++;  //boundary  
+    
+        tse[iface].txdesc = (alt_msgdma_prefetcher_standard_descriptor *)alt_uncached_malloc((1+ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE)*(sizeof(alt_msgdma_prefetcher_standard_descriptor)));
+        while ((((alt_u32)tse[iface].txdesc) % sizeof(alt_msgdma_prefetcher_standard_descriptor)) != 0)  
+          tse[iface].txdesc++;  //boundary
+    }
+   
+    /* Get the Rx and Tx MSGDMA addresses */
+    msgdma_tx_dev = alt_msgdma_open(tse_hw->tse_msgdma_tx); 
+    
+    if(!msgdma_tx_dev) {
+      dprintf("[altera_eth_tse_init] Error opening TX MSGDMA\n");
+      return ENP_RESOURCE;
+    }
+  
+    msgdma_rx_dev = alt_msgdma_open(tse_hw->tse_msgdma_rx);
+    if(!msgdma_rx_dev) {
+      dprintf("[altera_eth_tse_init] Error opening RX MSGDMA\n");
+      return ENP_RESOURCE;
+    }
+
+    /* Initialize mtip_mac_trans_info structure with values from <system.h>*/
+    tse_mac_initTransInfo2(&tse[iface].mi, (int)tse_hw->tse_mac_base,
+                                   (unsigned int)msgdma_tx_dev,            
+                                   (unsigned int)msgdma_rx_dev,
+                                   0);
+
+   /* reset the PHY if necessary */   
+   result = getPHYSpeed(tse[iface].mi.base);
+   speed = (result >> 1) & 0x07;
+   duplex = result & 0x01;
+   
+   /* reset the mac */ 
+   IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,
+                             mmac_cc_SW_RESET_mask | 
+                             mmac_cc_TX_ENA_mask | 
+                             mmac_cc_RX_ENA_mask);
+  
+   x=0;
+   while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) & 
+         ALTERA_TSEMAC_CMD_SW_RESET_MSK) {
+     if( x++ > 10000 ) {
+       break;
+     }
+   }
+   if(x >= 10000) {
+     dprintf("TSEMAC SW reset bit never cleared!\n");
+   }
+
+   dat = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base);
+   if( (dat & 0x03) != 0 ) {
+     dprintf("WARN: RX/TX not disabled after reset... missing PHY clock? CMD_CONFIG=0x%08x\n", dat);
+   } 
+   else {
+     dprintf("OK, x=%d, CMD_CONFIG=0x%08x\n", x, dat);
+   }
+  
+   /* Hack code to determine the Channel number <- Someone please fix this ugly code in the future */
+   extern alt_u8 mac_group_count;
+   extern alt_tse_mac_group *pmac_groups[TSE_MAX_MAC_IN_SYSTEM];
+      
+   if(tse_hw->use_shared_fifo == 1) {
+     int channel_loop = 0;
+     int mac_loop = 0;
+         
+     for (channel_loop = 0; channel_loop < mac_group_count; channel_loop ++) {
+       for (mac_loop = 0; mac_loop < pmac_groups[channel_loop]->channel; mac_loop ++) {
+         if (pmac_groups[channel_loop]->pmac_info[mac_loop]->psys_info == tse_hw) {
+           tse[iface].channel = mac_loop;
+         }
+       }
+     }
+   }
+   /* End of Hack code */
+  
+   if(tse_hw->use_shared_fifo == 1) {
+      IOWR_ALTERA_MULTI_CHAN_FIFO_SEC_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,tse_hw->tse_shared_fifo_rx_depth);
+      IOWR_ALTERA_MULTI_CHAN_FIFO_ALMOST_FULL_THRESHOLD(tse_hw->tse_shared_fifo_rx_ctrl_base,((tse_hw->tse_shared_fifo_rx_depth) - 140));
+   }
+   else {
+      /* Initialize MAC registers */
+      IOWR_ALTERA_TSEMAC_FRM_LENGTH(tse[iface].mi.base, ALTERA_TSE_MAC_MAX_FRAME_LENGTH); 
+      IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse[iface].mi.base, 8);
+      IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse[iface].mi.base, 8);
+      IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse[iface].mi.base, 8);
+      IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse[iface].mi.base,  3);
+      IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_tx_depth - 16); //1024/4;  
+      IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse[iface].mi.base,  0); //32/4; // start transmit when there are 48 bytes
+      IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse[iface].mi.base, tse_hw->tse_rx_depth - 16); //4000/4);
+      IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse[iface].mi.base,  0);
+   }
+  
+   /* Enable TX shift 16 for removing two bytes from the start of all transmitted frames */ 
+   if((ETHHDR_BIAS !=0) && (ETHHDR_BIAS !=2)) {
+     dprintf("[tse_mac_init] Error: Unsupported Ethernet Header Bias Value, %d\n",ETHHDR_BIAS);
+     return ENP_PARAM;
+   }
+ 
+   if(ETHHDR_BIAS == 0) {
+     alt_32 temp_reg;
+    
+     temp_reg = IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & (~ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK);
+     IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,temp_reg);
+ 
+     /* 
+      * check if the MAC supports the 16-bit shift option allowing us
+      * to send BIASed frames without copying. Used by the send function later. 
+      */
+     if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) & 
+        ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) {
+        tse[iface].txShift16OK = 1;
+        dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS);
+       return ENP_LOGIC;
+     } else {
+       tse[iface].txShift16OK = 0;
+     }
+   
+    /*Enable RX shift 16 for alignment of all received frames on 16-bit start address */   
+    temp_reg = IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & (~ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK);
+    IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,temp_reg);
+   
+    /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register  */ 
+    if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK)
+    {
+      tse[iface].rxShift16OK = 1;
+      dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS);
+      return ENP_LOGIC;
+    } 
+    else {
+      tse[iface].rxShift16OK = 0;
+    }
+  } /* if(ETHHDR_BIAS == 0) */
+ 
+  if(ETHHDR_BIAS == 2) {
+    IOWR_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK);
+ 
+    /*
+     * check if the MAC supports the 16-bit shift option allowing us
+     * to send BIASed frames without copying. Used by the send function later.
+     */
+    if(IORD_ALTERA_TSEMAC_TX_CMD_STAT(tse[iface].mi.base) &
+      ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK) {
+      tse[iface].txShift16OK = 1;
+    } 
+    else {
+      tse[iface].txShift16OK = 0;
+      dprintf("[tse_mac_init] Error: Incompatible %d value with TX_CMD_STAT register return TxShift16 value. \n",ETHHDR_BIAS);
+      return ENP_LOGIC;
+    }
+  
+    /* Enable RX shift 16 for alignment of all received frames on 16-bit start address */
+    IOWR_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base,ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK);
+ 
+    /* check if the MAC supports the 16-bit shift option at the RX CMD STATUS Register  */ 
+    if(IORD_ALTERA_TSEMAC_RX_CMD_STAT(tse[iface].mi.base) & ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK)
+    {
+      tse[iface].rxShift16OK = 1;
+    } 
+    else {
+      tse[iface].rxShift16OK = 0;
+      dprintf("[tse_mac_init] Error: Incompatible %d value with RX_CMD_STAT register return RxShift16 value. \n",ETHHDR_BIAS);
+      return ENP_LOGIC;
+    }
+  } /* if(ETHHDR_BIAS == 2) */
+  
+  /* enable MAC */
+  dat = ALTERA_TSEMAC_CMD_TX_ENA_MSK       |
+        ALTERA_TSEMAC_CMD_RX_ENA_MSK       |
+        mmac_cc_RX_ERR_DISCARD_mask        |
+#if ENABLE_PHY_LOOPBACK
+        ALTERA_TSEMAC_CMD_PROMIS_EN_MSK    |     // promiscuous mode
+        ALTERA_TSEMAC_CMD_LOOPBACK_MSK     |     // promiscuous mode
+#endif
+        ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK  |
+        ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK;  /* automatically discard frames with CRC errors */
+    
+  
+  /* 1000 Mbps */
+  if(speed == 0x01) {
+    dat |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  /* 100 Mbps */
+  else if(speed == 0x02) {
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  /* 10 Mbps */
+  else if(speed == 0x04) {
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    dat |= ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  /* default to 100 Mbps if returned invalid speed */
+  else {
+    dat &= ~ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
+    dat &= ~ALTERA_TSEMAC_CMD_ENA_10_MSK;
+  }
+  
+  /* Half Duplex */
+  if(duplex == TSE_PHY_DUPLEX_HALF) {
+    dat |= ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+  }
+  /* Full Duplex */
+  else {
+    dat &= ~ALTERA_TSEMAC_CMD_HD_ENA_MSK;
+  }
+          
+  IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base, dat);
+  dprintf("\nMAC post-initialization: CMD_CONFIG=0x%08x\n", 
+  IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base));
+  
+                          
+#ifdef ALT_INICHE
+   /* Set the MAC address */  
+   IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base,
+                           ((int)((unsigned char) tse[iface].mac_addr[0]) | 
+                            (int)((unsigned char) tse[iface].mac_addr[1] <<  8) |
+                            (int)((unsigned char) tse[iface].mac_addr[2] << 16) | 
+                            (int)((unsigned char) tse[iface].mac_addr[3] << 24)));
+  
+   IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, 
+                           (((int)((unsigned char) tse[iface].mac_addr[4]) | 
+                             (int)((unsigned char) tse[iface].mac_addr[5] <<  8)) & 0xFFFF));
+   
+#else /* not ALT_INICHE */
+
+   /* Set the MAC address */  
+   IOWR_ALTERA_TSEMAC_MAC_0(tse[iface].mi.base,
+                           ((int)(0x00)       | 
+                            (int)(0x07 <<  8) |
+                            (int)(0xAB << 16) | 
+                            (int)(0xF0 << 24)));
+
+   IOWR_ALTERA_TSEMAC_MAC_1(tse[iface].mi.base, 
+                           (((int)(0x0D)      | 
+                             (int)(0xBA <<  8)) & 0xFFFF));
+
+
+   /* Set the mac address in the tse struct */
+   tse[iface].mac_addr[0] = 0x00;
+   tse[iface].mac_addr[1] = 0x07;
+   tse[iface].mac_addr[2] = 0xAB;
+   tse[iface].mac_addr[3] = 0xF0;
+   tse[iface].mac_addr[4] = 0x0D;
+   tse[iface].mac_addr[5] = 0xBA;
+
+#endif /* not ALT_INICHE */
+
+   /* status = UP */ 
+   nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_UP;    
+   nets[iface]->n_mib->ifOperStatus =  ALTERA_TSE_ADMIN_STATUS_UP;
+   
+   /* Install MSGDMA (RX) interrupt handler */
+   alt_msgdma_register_callback(
+        tse[iface].mi.rx_msgdma,
+        (alt_msgdma_callback)&tse_msgdmaRx_isr,
+        0,
+        (void*)(&tse[iface]));
+        
+           /* Install MSGDMA (TX) interrupt handler */
+    alt_msgdma_register_callback(
+          tse[iface].mi.tx_msgdma,
+          (alt_msgdma_callback)&tse_msgdmaTx_isr,
+          0,
+          (void*)(&tse[iface]));
+    
+  status = tse_msgdma_read_init(&tse[iface]);
+  if (status == 0 ) status = tse_msgdma_write_init(&tse[iface],0,0);
+  
+  if (status!=0) dprintf("TSE_MAC_INIT error\n");
+  
+  return status;
+}
+
+/* @Function Description -  Init and setup MSGDMA TX Descriptor chain
+ *                          
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success 
+ */
+int tse_msgdma_write_init(ins_tse_info* tse_ptr,unsigned int * ActualData,unsigned int len)
+{     
+  alt_u32 control = 0;
+  int desc_index;
+  int rc;
+  
+  tse_ptr->txdesc_list = NULL;
+  
+  for(desc_index = 0; desc_index < (ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE); desc_index++)
+  { 
+        
+    /* trigger interrupt when transfer complete */
+    control =  ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_SOP_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MASK; 
+            
+    if (desc_index >= ( ALTERA_TSE_MSGDMA_TX_DESC_CHAIN_SIZE - 2)) control |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK;
+    else control  |= ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK;
+            
+    rc=alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor(
+            tse_ptr->mi.tx_msgdma,
+            (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->txdesc[desc_index],  
+            (int)ActualData,   
+            len,
+            control);
+    if (rc!=0) return -1;
+    
+    if (desc_index==0) tse_ptr->txdesc_list = NULL; 
+            
+    rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+               &tse_ptr->txdesc_list,
+               &tse_ptr->txdesc[desc_index] );        
+    if (rc!=0) return -1;
+
+  } 
+  
+  return 0;
+}
+
+/* @Function Description -  TSE transmit API to send data to the MAC
+ *                          
+ * 
+ * @API TYPE - Public
+ * @param  net  - NET structure associated with the TSE MAC instance
+ * @param  data - pointer to the data payload
+ * @param  data_bytes - number of bytes of the data payload to be sent to the MAC
+ * @return SUCCESS if success, else a negative value
+ */
+int tse_mac_raw_send(NET net, char * data, unsigned int data_bytes)
+{
+   unsigned int len = data_bytes;
+   int rc;
+
+   ins_tse_info* tse_ptr = (ins_tse_info*) net->n_local;
+   tse_mac_trans_info *mi;
+   unsigned int* ActualData;
+   int cpu_sr;
+   
+   OS_ENTER_CRITICAL();
+   mi = &tse_ptr->mi;
+   
+   if(tse_ptr->sem!=0) /* Tx is busy*/
+   {
+      dprintf("raw_send CALLED AGAIN!!!\n");
+      OS_EXIT_CRITICAL();
+      return ENP_RESOURCE;
+   }
+ 
+   tse_ptr->sem = 1;  
+   
+   // clear bit-31 before passing it to MSGDMA Driver
+   ActualData = (unsigned int*)alt_remap_cached ((volatile void*) data, 4);
+
+   #if (0)
+   rc= tse_msgdma_write_init(tse_ptr,ActualData,len);
+   if (rc<0) 
+   {
+     dprintf("tse_msgdma_write_init bad return\n");
+     OS_EXIT_CRITICAL();
+     return -1;
+   }
+   #else
+     tse_ptr->txdesc[0].read_address = (alt_u32)ActualData;
+     tse_ptr->txdesc[0].transfer_length = len;
+     tse_ptr->txdesc[0].control = (tse_ptr->txdesc[0].control
+            & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_CLR_MASK) 
+            | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_GO_MASK;
+   #endif  
+        
+   alt_dcache_flush(ActualData,len);   
+   rc = tse_mac_aTxWrite(mi,tse_ptr->txdesc);
+   if(rc < 0)   /* MSGDMA not available */
+   {
+      dprintf("raw_send() MSGDMA not available, ret=%d, len=%d\n",rc, len);
+      net->n_mib->ifOutDiscards++;
+      tse_ptr->sem = 0;
+
+      OS_EXIT_CRITICAL();
+      return SEND_DROPPED;   /* ENP_RESOURCE and SEND_DROPPED have the same value! */
+   }
+   else   /* = 0, success */
+   {
+      net->n_mib->ifOutOctets += data_bytes;
+      /* we dont know whether it was unicast or not, we count both in <ifOutUcastPkts> */
+      net->n_mib->ifOutUcastPkts++;
+      tse_ptr->sem = 0;
+
+      OS_EXIT_CRITICAL();
+      return SUCCESS;  /*success */
+   }
+}
+
+
+
+/* @Function Description -  TSE Driver MSGDMA RX ISR callback function
+ *                          
+ * 
+ * @API TYPE - callback
+ * @param  context  - context of the TSE MAC instance
+ * @param  intnum - temporary storage
+ */
+void tse_msgdmaRx_isr(void * context)
+{
+    ins_tse_info* tse_ptr = (ins_tse_info *) context; 
+    alt_u32 msgdma_status;
+    alt_u32 i,control;
+    
+    /* Capture current rcv queue length */
+    int initial_rcvdq_len = rcvdq.q_len;
+
+    /* reenable global interrupts so we don't miss one that occurs during the
+       processing of this ISR */
+    IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base,
+      			IORD_ALT_MSGDMA_PREFETCHER_CONTROL(tse_ptr->mi.rx_msgdma->prefetcher_base)
+	  			| ALT_MSGDMA_PREFETCHER_CTRL_GLOBAL_INTR_EN_SET_MASK);
+       
+    msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.rx_msgdma->csr_base);
+       
+    if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)==0)
+    {   
+       /* Handle received packet */
+        tse_mac_rcv(tse_ptr); 
+        
+        /* read the control field of the last descriptor in the chain */
+        control = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-2],0x1c);
+                          
+        //if the chain is completed then start a new chain
+        if ((control & ALT_MSGDMA_PREFETCHER_DESCRIPTOR_CTRL_OWN_BY_HW_SET_MASK)==0)            
+        {
+            /* process any unprocessed descriptors */      
+            for (i=(tse_ptr->rx_descriptor_index);i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+            {
+                tse_mac_rcv(tse_ptr); 
+            }
+            
+            /* cancel any pending ints */
+            /* the chain could have been completed and int generated during the processing of this ISR */
+            /* But we are handling that in this ISR, so cancel any pending interrupt */
+            IOWR_ALT_MSGDMA_PREFETCHER_STATUS(tse_ptr->mi.rx_msgdma->prefetcher_base,1);
+          
+            /* switch chains */
+            tse_ptr->rx_descriptor_index = 0;
+            if (tse->rx_chain == 0) tse->rx_chain=1; else tse->rx_chain=0; 
+                
+            /* start new chain */            
+            tse_mac_aRxRead(&tse_ptr->mi, tse_ptr->rxdesc_list[tse->rx_chain]);
+            
+            /* allocate storage for the non active chain */
+            allocate_rx_descriptor_chain(tse_ptr); 
+        }    
+        
+        /* Wake up Niche stack if there are new packets are on queue */
+        if ((rcvdq.q_len) > initial_rcvdq_len) {
+            SignalPktDemux();
+        }       
+    } /* if (no error) */
+    else {  dprintf("RX ERROR\n");  }
+    
+}
+
+/* @Function Description -  TSE Driver MSGDMA TX ISR callback function
+ *                          
+ * 
+ * @API TYPE - callback
+ * @param  context  - context of the TSE MAC instance
+ */
+void tse_msgdmaTx_isr(void * context)
+{
+  ins_tse_info* tse_ptr = (ins_tse_info *) context; 
+  int msgdma_status;
+
+  /* 
+   * The MSGDMA interrupt source was cleared in the MSGDMA ISR entry, 
+   * which called this routine. New interrupt sources will cause the 
+   * IRQ to fire again once this routine returns.
+   */        
+  
+  /* 
+   * Grab MSGDMA status to validate interrupt cause. 
+   * 
+   * IO read to peripheral that generated the IRQ is done after IO write
+   * to negate the interrupt request. This ensures at the IO write reaches 
+   * the peripheral (through any high-latency hardware in the system)
+   * before the ISR exits.
+   */   
+  msgdma_status = IORD_ALTERA_MSGDMA_CSR_STATUS(tse_ptr->mi.tx_msgdma->csr_base);
+  
+  if ((msgdma_status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK)!=0)
+      dprintf("TX STOPPED\n");
+   
+}
+
+
+/* @Function Description -  Init and setup MSGDMA Descriptor chain
+ *                          
+ * 
+ * @API TYPE - Internal
+ * @return SUCCESS on success 
+ */
+int tse_msgdma_read_init(ins_tse_info* tse_ptr)
+{     
+  alt_u32 *uncached_packet_payload;
+  alt_u32 control = 0;
+  int desc_index;
+  int chain_index;
+  int rc;
+  int max_transfer_size=0xffff;
+  
+  if  (tse_ptr->mi.rx_msgdma->max_byte < max_transfer_size) { max_transfer_size = tse_ptr->mi.rx_msgdma->max_byte; }
+   
+  for (chain_index=0;chain_index<2;chain_index++)
+  { 
+    tse_ptr->rxdesc_list[chain_index] = NULL;
+  
+    for(desc_index = 0; desc_index < ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE; desc_index++)
+    { 
+      uncached_packet_payload = NULL;
+      
+      if ((desc_index < (ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1))) {  
+        tse_ptr->pkt_array_rx[chain_index][desc_index] = pk_alloc(ALTERA_TSE_PKT_INIT_LEN);
+      
+        if (!tse_ptr->pkt_array_rx[chain_index][desc_index])   /* couldn't get a free buffer for rx */
+        {
+          dprintf("[tse_msgdma_read_init] Fatal error: No free packet buffers for RX\n");
+          tse_ptr->netp->n_mib->ifInDiscards++;
+        
+          return ENP_NOBUFFER;
+        }
+      
+        // ensure bit-31 of tse_ptr->pkt_array_rx[desc_index]->nb_buff is clear before passing
+        // to MSGDMA Driver
+        uncached_packet_payload = (alt_u32 *)alt_remap_cached ((volatile void*) tse_ptr->pkt_array_rx[chain_index][desc_index]->nb_buff, 4);
+        alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN);
+      }
+   
+      /* trigger interrupt when transfer complete */
+      control =  ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK |
+            ALTERA_MSGDMA_DESCRIPTOR_CONTROL_ERROR_IRQ_MASK | ALTERA_MSGDMA_DESCRIPTOR_CONTROL_END_ON_EOP_MASK; 
+            
+      rc=alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor(
+            tse_ptr->mi.rx_msgdma,
+            (alt_msgdma_prefetcher_standard_descriptor *) &tse_ptr->rxdesc[chain_index][desc_index],  
+            (alt_u32)uncached_packet_payload,   
+            max_transfer_size,
+            control);
+      if (rc!=0) return -1;
+      
+      if (desc_index==0) tse_ptr->rxdesc_list[chain_index] = NULL;  
+            
+      rc=alt_msgdma_prefetcher_add_standard_desc_to_list(
+               &tse_ptr->rxdesc_list[chain_index],
+               &tse_ptr->rxdesc[chain_index][desc_index] );        
+      if (rc!=0) return -1;
+    }
+
+  } 
+
+  dprintf("[tse_msgdma_read_init] RX descriptor chain desc (%d depth) created\n",  desc_index);
+   
+  tse_ptr->rx_descriptor_index=0;   //for processing completed rx descriptors
+  tse_ptr->rx_chain=0;
+  tse_mac_aRxRead( &tse_ptr->mi, tse_ptr->rxdesc_list[tse_ptr->rx_chain]);
+  
+  return SUCCESS;
+}
+
+/* allocate the storage for the non active rx descriptor chain 
+   update the write pointers in each descriptor to point
+   to the allocated storage. */
+int allocate_rx_descriptor_chain(ins_tse_info* tse_ptr)
+{
+    PACKET replacement_pkt;
+    alt_u32 *uncached_packet_payload;
+    alt_msgdma_prefetcher_standard_descriptor *rxDesc;
+    int i;
+    
+    for (i=0;i<(ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE-1);i++)
+    {
+        replacement_pkt = pk_alloc(ALTERA_TSE_PKT_INIT_LEN);
+        if (!replacement_pkt) { /* couldn't get a free buffer for rx */
+          dprintf("No free buffers for rx\n");
+          return 1;
+        }
+        else
+        {
+            rxDesc = &tse_ptr->rxdesc[!tse_ptr->rx_chain][i];
+            tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i] = replacement_pkt;
+            uncached_packet_payload = (alt_u32 *)alt_remap_cached(tse_ptr->pkt_array_rx[!tse_ptr->rx_chain][i]->nb_buff, 4);
+            alt_dcache_flush((void *) uncached_packet_payload, ALTERA_TSE_PKT_INIT_LEN);
+            rxDesc->write_address = (alt_u32)(uncached_packet_payload);
+        }
+    } 
+    
+    return 0;
+}
+
+/* @Function Description -  TSE Driver MSGDMA RX ISR callback function
+ *                          
+ * 
+ * @API TYPE        - callback internal function
+ * @return SUCCESS on success
+ */
+
+void tse_mac_rcv(ins_tse_info* tse_ptr)
+{     
+    struct ethhdr * eth;
+    int pklen;
+    PACKET rx_packet;
+        
+    /* Correct frame length to actual (this is different from TX side) */
+    pklen = IORD_32DIRECT(&tse_ptr->rxdesc[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index].bytes_transfered,0) - 2;  
+    
+    tse_ptr->netp->n_mib->ifInOctets += (u_long)pklen;
+    
+    rx_packet = tse_ptr->pkt_array_rx[tse_ptr->rx_chain][tse_ptr->rx_descriptor_index];   
+    rx_packet->nb_prot = rx_packet->nb_buff + ETHHDR_SIZE;
+    rx_packet->nb_plen = pklen - 14;
+    rx_packet->nb_tstamp = cticks;
+    rx_packet->net = tse_ptr->netp;
+    
+    // set packet type for demux routine
+    eth = (struct ethhdr *)(rx_packet->nb_buff + ETHHDR_BIAS);
+    rx_packet->type = eth->e_type;
+    
+    putq(&rcvdq, rx_packet);
+              
+    tse_ptr->rx_descriptor_index++; 
+} 
+
+int tse_mac_stats(void * pio, int iface)
+{
+    ns_printf(pio, "tse_mac_stats(), stats will be added later!\n");
+    return SUCCESS;
+}
+
+/* @Function Description -  Closing the TSE MAC Driver Interface
+ *                          
+ * 
+ * @API TYPE - Public
+ * @param  iface    index of the NET interface associated with the TSE MAC.
+ * @return SUCCESS
+ */
+int tse_mac_close(int iface)
+{
+    int state;
+     
+    /* status = down */
+    nets[iface]->n_mib->ifAdminStatus = ALTERA_TSE_ADMIN_STATUS_DOWN;    
+    
+    /* disable the interrupt in the OS*/
+    alt_msgdma_register_callback(tse[iface].mi.rx_msgdma, 0, 0, 0);
+     
+    /* Disable Receive path on the device*/
+    state = IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base);
+    IOWR_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base,state & ~ALTERA_TSEMAC_CMD_RX_ENA_MSK); 
+    
+    /* status = down */                                     
+    nets[iface]->n_mib->ifOperStatus = ALTERA_TSE_ADMIN_STATUS_DOWN;     
+    
+    return SUCCESS;
+}
+#endif /* ALT_INICHE */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h b/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h
new file mode 100644
index 0000000..07ac364
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/inc/alt_iniche_dev.h
@@ -0,0 +1,215 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+*                                                                             *
+* Source for the Altera InterNiche device services.                           *
+*                                                                             *
+* Author EPS                                                                  *
+*                                                                             *
+******************************************************************************/
+
+#ifndef __ALT_INICHE_DEV_H__
+#define __ALT_INICHE_DEV_H__
+
+/*******************************************************************************
+ *******************************************************************************
+ *
+ * InterNiche device services.
+ *
+ *******************************************************************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Imported services.
+ *
+ ******************************************************************************/
+
+#include <errno.h>
+
+#include "ipport.h"
+#include "tcpport.h"
+#include "sys/alt_llist.h"
+
+
+/*******************************************************************************
+ *
+ * Structure typedefs.
+ *
+ ******************************************************************************/
+
+typedef struct alt_iniche_dev_struct    alt_iniche_dev;
+
+
+/*******************************************************************************
+ *
+ * Typedefs.
+ *
+ ******************************************************************************/
+
+/*
+ * alt_iniche_dev_init_func
+ *
+ *   --> p_dev                  Device to initialize.
+ *
+ *   Functions of this type initialize the device specified by p_dev.
+ */
+
+typedef error_t (*alt_iniche_dev_init_func)(
+    alt_iniche_dev              *p_dev);
+
+
+/*******************************************************************************
+ *
+ * Structure defs.
+ *
+ ******************************************************************************/
+
+/*
+ * InterNiche network interface device structure
+ *
+ *   llist                      Linked list data record.
+ *   name                       Name of device.
+ *   init_func                  Device initialization function.
+ *   p_driver_data              Driver data.
+ *   if_num                     Device interface number.
+ *   p_net                      InterNiche network interface data record.
+ *
+ *   This structure contains fields used for InterNiche network interface
+ * device drivers.
+ *   All device data records are maintained in a list using the field llist.
+ *   The name of the device is maintained in name.
+ *   The function used to initialize the device is specified by init_func.
+ *   The device driver may maintain a pointer to its own data in p_driver_data.
+ *   Each device has an associated interface number maintained in if_num.
+ *   The InterNiche network interface data record is maintained in p_net.
+ */
+
+struct alt_iniche_dev_struct
+{
+    alt_llist                   llist;
+    char                        *name;
+    alt_iniche_dev_init_func    init_func;
+    void                        *p_driver_data;
+    int                         if_num;
+    NET                         p_net;
+};
+
+
+/*******************************************************************************
+ *
+ * Macros.
+ *
+ ******************************************************************************/
+
+/*
+ * alt_iniche_dev_reg
+ *
+ *   --> p_dev                  Device to register.
+ *
+ *   This macro registers the InterNiche device specified by p_dev with the
+ * InterNiche device services.
+ */
+
+extern alt_llist                alt_iniche_dev_list;
+
+#define alt_iniche_dev_reg(p_dev)                                              \
+    alt_llist_insert(&alt_iniche_dev_list, &((p_dev)->llist))
+
+
+/*******************************************************************************
+ *
+ * InterNiche device services prototypes.
+ *
+ ******************************************************************************/
+
+int iniche_devices_init(
+    int                         ifacesFound);
+
+
+/*******************************************************************************
+ *******************************************************************************
+ *
+ * External InterNiche device services.
+ *
+ *******************************************************************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * External InterNiche device services prototypes.
+ *
+ *   These functions are provided by the external system to the InterNiche
+ * device services.
+ *
+ ******************************************************************************/
+
+/*
+ * get_mac_addr
+ *
+ *   --> net                    Network interface for which to get MAC address.
+ *   <-- mac_addr               MAC address.
+ *
+ *   This function returns in mac_addr a MAC address to be used with the network
+ * interface specified by net.
+ */
+
+int get_mac_addr(
+    NET                         net,
+    unsigned char               mac_addr[6]);
+
+
+/*
+ * get_ip_addr
+ *
+ *   --> p_dev                  Device for which to get IP address.
+ *   <-- p_addr                 IP address for device.
+ *   <-- p_netmask              IP netmask for device.
+ *   <-- p_gw_addr              IP gateway address for device.
+ *   <-- p_use_dhcp             TRUE if DHCP should be used to obtain an IP
+ *                              address.
+ *
+ *   This function provides IP address information for the InterNiche network
+ * interface device specified by p_dev.  If a static IP address is to be used,
+ * the IP address, netmask, and default gateway address are returned in p_addr,
+ * p_netmask, and p_gw_addr, and FALSE is returned in p_use_dhcp.  If the DHCP
+ * protocol is to be used to obtain an IP address, TRUE is returned in
+ * p_use_dhcp.
+ */
+
+int get_ip_addr(
+    alt_iniche_dev              *p_dev,
+    ip_addr                     *p_addr,
+    ip_addr                     *p_netmask,
+    ip_addr                     *p_gw_addr,
+    int                         *p_use_dhcp);
+
+
+#endif /* __ALT_INICHE_DEV_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h b/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h
new file mode 100644
index 0000000..6189afb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/inc/os/alt_syscall.h
@@ -0,0 +1,77 @@
+#ifndef __ALT_SYSCALL_H__
+#define __ALT_SYSCALL_H__
+
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+******************************************************************************/
+
+/*
+ * The macros defined in this file are used to provide the function names used
+ * for the HAL 'UNIX style' interface, e.g. read(), write() etc. 
+ *
+ * Operating systems which are ported to the HAL can provide their own 
+ * version of this file, which will be used in preference. This allows
+ * the operating system to provide it's own implementation of the top level
+ * system calls, while retaining the HAL functions under a different name, 
+ * for example, alt_read(), alt_write() etc.
+ */
+
+#define ALT_NICHESTACK_ALT_SYSCALL_H
+
+#define ALT_CLOSE        alt_close
+#define ALT_ENVIRON      environ
+#define ALT_EXECVE       execve
+#define ALT_EXIT         _exit
+#define ALT_FCNTL        alt_fcntl
+#define ALT_FORK         fork
+#define ALT_FSTAT        fstat
+#define ALT_GETPID       getpid
+#define ALT_GETTIMEOFDAY gettimeofday
+#define ALT_IOCTL        ioctl
+#define ALT_ISATTY       isatty
+#define ALT_KILL         kill
+#define ALT_LINK         link
+#define ALT_LSEEK        lseek
+#define ALT_OPEN         open
+#define ALT_READ         alt_read
+#define ALT_RENAME       _rename
+#define ALT_SBRK         sbrk
+#define ALT_SETTIMEOFDAY settimeofday
+#define ALT_STAT         stat
+#define ALT_UNLINK       unlink
+#define ALT_USLEEP       usleep
+#define ALT_WAIT         wait
+#define ALT_WRITE        alt_write
+#define ALT_TIMES        times
+
+/*
+ *
+ */
+
+#endif /* __ALT_ALIAS_H__ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c
new file mode 100644
index 0000000..2f5aeb9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/allports.c
@@ -0,0 +1,947 @@
+/*
+ * FILENAME: allports.c
+ *
+ * Copyright 1998-2008 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Routines common to most targets. 
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: netmain_init(), icmp_port_du(), station_state(), 
+ * ROUTINES: ftpc_callback(), sysuptime(), packet_check(), 
+ * ROUTINES: mcastlist(), prep_modules(), 
+ *
+ * The functions in this file are generic functions 
+ * and hence used for all builds. In addition to the above functions,
+ * globals "name" and "prompt" are also initialized in this file.
+ *
+ * This file was previously .\misclib\cmnport.c
+ *
+ * PORTABLE: yes
+ * They are portable for all targets that InterNiche supports. In future
+ * if there is need for any of them  to be made target-specific, then
+ * #ifndef wrappers can be provided over here.
+ */
+
+#include "ipport.h"
+
+#ifdef DHCP_SERVER
+#include "dhcpport.h"
+#endif   /* DHCP_SERVER */
+
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+#ifdef IP_V6
+#include "ip6.h"
+#endif
+
+#ifdef INCLUDE_NVPARMS     /* system uses InterNiche NV system */
+#include "nvparms.h"
+#endif
+
+#ifdef USE_PPP
+#include "ppp_port.h"
+#endif   /* USE_PPP */
+
+#ifdef USE_MODEM
+#include "mdmport.h"
+#else
+#ifdef USE_PPP
+#include "../mppp/mppp.h" /* for pppcfg */
+#endif
+#endif   /* USE_MODEM */
+
+#ifdef PING_APP
+#include "app_ping.h"
+#endif
+#ifndef TIMEFOR1TICK
+#define TIMEFOR1TICK       (1000/TPS)
+#endif
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+#include "../ipmc/igmp_cmn.h"
+#endif /* IP multicast and (IGMPv1 or IGMPv2) */
+
+#include "menu.h"
+#ifdef INCLUDE_INICHE_LOG
+#include "iniche_log.h"
+#endif
+#ifdef OSPORT_H
+#include OSPORT_H
+#endif
+
+/* various network entry points */
+extern   char* ip_startup(void);
+extern   void  inet_timer(void);
+
+#ifdef WEBPORT
+extern   int   http_init(void);   /* start up the web server */
+extern   int   prep_http(void);
+#endif
+
+#ifdef TK_STDIN_DEVICE
+extern   void  kbdio(void);
+#endif
+
+#if defined(TFTP_CLIENT) || defined(TFTP_SERVER)
+extern   int   tftp_init(void);
+#endif
+
+#ifdef TELNET_SVR
+extern   int   tel_init(void);
+extern   void  tel_cleanup(void);
+extern   int   prep_telnet(void);
+#endif
+
+#ifdef DHCP_CLIENT
+extern   void  dhc_setup(void);
+#endif
+
+#ifdef DHCP_SERVER
+extern   int   dhcp_init(void);
+extern   int   prep_dhcpsrv(void);
+extern   void  dhcpsrv_cleanup(void);
+#endif
+
+#ifdef DNS_CLIENT
+#include "dns.h"
+#endif
+
+#ifdef TCP_ECHOTEST
+extern   int   tcp_echo_init(void);
+extern   void  tcp_echo_cleanup(void);
+extern   void  tcp_echo_recv(void);
+#endif
+
+#ifdef TCP_CIPHERTEST
+extern   int   tcp_cipher_init(void);
+extern   void  tcp_cipher_cleanup(void);
+extern   void  tcp_cipher_recv(void);
+#endif
+
+#ifdef FTP_CLIENT
+extern   int   fc_check(void);
+extern   void  (*fc_callback)(void *fc,int logstate, int cmdstate);
+extern   void  ftpc_callback(void *fc,int logstate, int cmdstate);
+extern   int   prep_ftpc(void);
+#endif
+
+#ifdef VFS_FILES
+extern   int   prep_vfs(void);
+#endif
+
+#ifdef SMTP_ALERTS
+extern   int   smtp_init(void);
+extern   int   prep_smtp(void);
+#endif
+
+#ifdef NATRT
+extern   int   prep_natrt(void);
+#endif
+
+#ifdef  IP_MULTICAST
+/* Add multicast test program call and a dummy definition of mcastlist */
+extern   void  u_mctest_init(void);
+extern   int   mcastlist(struct in_multi *);
+#endif   /* IP_MULTICAST */
+
+#ifdef TESTMENU   /* after menus.h */
+extern   struct menu_op testmenu[10];
+#endif   /* TESTMENU */
+
+#ifdef CSUM_DEMO
+extern   int   cksum_init(void);
+extern   void  csum_init(void);
+#endif
+
+#ifdef DNS_SERVER
+extern   int   dns_srvr_check(void);
+extern   int   dns_srvr_init(int );
+extern   void  dns_srvr_timer(void);
+#endif   /* DNS_SERVER */
+
+#ifdef UDPSTEST
+extern   int   udp_echo_init(void);
+extern   void  udp_echo_cleanup(void);
+#endif   /* UDPSTEST */
+
+#ifdef RIP_SUPPORT 
+extern   int   rip_init(void);
+extern   void  rip_cleanup(void);
+extern   int   prep_rip(void);
+#endif   /* RIP_SUPPORT */
+
+#ifdef INCLUDE_SNMP
+extern   int   snmp_init(void);
+extern   void  snmp_cleanup(void);
+extern   int   prep_snmp(void);
+#endif   /* INCLUDE_SNMP */
+
+#ifdef RAWIPTEST
+extern int raw_test_init(void);
+#endif   /* RAWIPTEST */
+
+#ifdef SUPERLOOP
+#define task_stats(x)     ;
+#else
+void task_stats(void * pio);
+#endif
+
+#ifdef FULL_ICMP
+void icmp_port_du(PACKET p, struct destun * pdp);
+#endif
+
+#ifdef FTP_SERVER
+extern   int   ftps_init(void);
+extern   void  ftps_cleanup(void);
+#endif
+
+#if defined(MEMDEV_SIZE) && defined(VFS_FILES)
+extern int   init_memdev(void);
+#endif
+
+#ifdef USE_AUTOIP
+extern   int   Upnp_init(void);
+#endif   /* USE_AUTOIP */
+
+#ifdef INICHE_SYSLOG 
+extern   int   syslog_init(void);
+extern   void  closelog(void);
+extern   int   prep_syslog(void);
+#endif   /* INICHE_SYSLOG */
+
+#ifdef INCLUDE_SSLAPP
+extern int sslapp_init(void);
+#endif   /* INCLUDE_SSLAPP */
+#ifdef SUPERLOOP
+int iniche_net_ready = FALSE;
+#endif
+
+#ifdef USE_SNTP_V4
+int sntpv4_init (void);
+int sntpv4_app (void);
+#endif
+
+/* The following global variables are used in most ports. They are used by code
+ * covered under a variety of ipport.h feature ifdefs. Experience has show that
+ * it's not practical to do a complete ifdef to omit these when they are not
+ * in use. It would require a huge multiple OR case, and many preprocessors
+ * don't handle ifdef logic that complex.
+ */
+
+char * name = "InterNiche Portable TCP/IP, v3.1 \n";
+char * prompt = "INET> ";     /* prompt for console */
+ip_addr activehost  =  0L;    /* common host parameter */
+u_long  pingdelay   =  TPS;   /* common delay parameter (1 second) */
+int     deflength   =  64;    /* common length parameter */
+
+/* PING_APP-related variables */
+#ifdef PING_APP
+extern ip_addr ping4_activehost; /* default ping host */
+extern u_long ping4_delay;       /* 1 second between pings */
+extern u_long ping4_deflength;   /* default ping packet data length */
+#endif /* PING_APP */
+
+#ifdef DNS_CLIENT_UPDT
+extern u_long dns_update_server;
+#endif   /* DNS_CLIENT_UPDT */
+
+
+#ifdef USE_COMPORT
+#include "comline.h"          /* include if not yet included */
+/* Struct contaning all configuration global params for Comport */
+struct ComPortCfg comportcfg;
+#endif   /* USE_COMPORT */
+
+/* static net structs, so we can patch in default IP address. */
+extern   struct net  netstatic[STATIC_NETS];
+
+
+/* FUNCTION: netmain_init()
+ * 
+ * Initialize all the modules that are being compiled in.
+ * This function is generic and is required for all builds
+ *
+ * Tasks do their own initialization. Hence for modules which have
+ * their own tasks, we don't do the initialization in netmain_init(). 
+ * That is done by putting then under "#ifdef SUPERLOOP"
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void 
+netmain_init(void)
+{
+   int   e = 0;
+   char *   msg;
+#ifdef IP_V6
+   ip6_addr host;
+#endif
+
+   printf("%s\n", name);
+   printf("Copyright 1996-2008 by InterNiche Technologies. All rights reserved. \n");
+#ifdef IN_MENUS
+   install_version("allports3.1");
+#endif
+#ifndef SUPERLOOP
+   /* call this to do pre-task setup including intialization of port_prep */
+   msg = pre_task_setup();
+   if (msg)
+      panic(msg);
+#endif
+
+#ifdef INCLUDE_NVPARMS     /* system uses InterNiche NV system */
+   e = get_nv_params();    /* get flash parameters into data structs */
+   if (e)
+   {
+      printf("fatal error (%d) reading NV parameters.\n", e);
+      panic("nv");
+   }
+
+   /* set static iface IP info up from stored parameters. These may 
+   be overwritten from command line parms or DHCP later. */
+   {
+      int   i;
+
+      for (i = 0; i < STATIC_NETS; i++)
+      {
+         netstatic[i].n_ipaddr = inet_nvparms.ifs[i].ipaddr;
+         netstatic[i].snmask = inet_nvparms.ifs[i].subnet;
+         netstatic[i].n_defgw = inet_nvparms.ifs[i].gateway;
+#ifdef IP_MULTICAST
+         /* Create a dummy entry for the Ethernet interface mcastlist */
+         /* If this entry is set to NULL, multicast is not supported  */
+         /* on this interface */
+         netstatic[i].n_mcastlist = mcastlist;
+#if defined (IGMP_V1) || defined (IGMP_V2)
+         if ((inet_nvparms.ifs[i].igmp_oper_mode != IGMP_MODE_V1) &&
+             (inet_nvparms.ifs[i].igmp_oper_mode != IGMP_MODE_V2))
+            netstatic[i].igmp_oper_mode = IGMP_MODE_DEFAULT;
+         else
+            netstatic[i].igmp_oper_mode = inet_nvparms.ifs[i].igmp_oper_mode;
+#endif /* IGMPv1 or IGMPv2 */
+#endif /* IP_MULTICAST */
+      }
+   }
+
+#ifdef DNS_CLIENT
+   /* set DNS client's server list from nvparms information */
+   MEMCPY(dns_servers, inet_nvparms.dns_servers, sizeof(dns_servers));
+
+#ifdef DNS_CLIENT_UPDT
+   MEMCPY(soa_mname, inet_nvparms.dns_zone_name, sizeof(soa_mname));
+   MEMCPY(&dns_update_server, &inet_nvparms.dns_update_server, sizeof(dns_update_server));
+#endif   /* DNS_CLIENT_UPDT */
+
+#endif   /* DNS_CLIENT */
+
+#ifdef USE_COMPORT
+   comportcfg.comport = comport_nvparms.comport;
+   comportcfg.LineProtocol = comport_nvparms.LineProtocol;
+#endif   /* USE_COMPORT */
+#endif   /* INCLUDE_NVPARMS */
+
+#ifndef INCLUDE_NVPARMS
+#ifdef USE_COMPORT
+   comportcfg.comport = 0x01;
+   comportcfg.LineProtocol = PPP;   /* Default to PPP */
+#endif   /* USE_COMPORT */
+#endif   /* INCLUDE_NVPARMS */
+
+#ifdef IP_V6
+         ip6_init();
+#endif
+
+#ifdef INCLUDE_INICHE_LOG
+   if(global_log_create())
+   {
+      printf("global_log_create() failed\n");
+   }
+   glog_with_type(LOG_TYPE_INFO, "INICHE LOG initialized", 1);
+#endif
+
+   msg = ip_startup();
+   if (msg)
+   {
+      printf("inet startup error: %s\n", msg);
+      panic("IP");
+   }
+
+#if defined(MEMDEV_SIZE) && defined(VFS_FILES)
+   init_memdev(); /* init the mem and null test devices */
+#endif
+
+#ifdef IP_MULTICAST
+#ifdef INCLUDE_TCP
+   /* call the IP multicast test program */
+   u_mctest_init();
+#endif
+#endif  
+
+   /* clear debugging flags. Port can optionally turn them
+    * back on in post_task_setup();
+    * NDEBUG = UPCTRACE | IPTRACE | TPTRACE ;  
+    */
+   NDEBUG = 0;    
+
+   /* print IP address of the first interface - for user's benefit */
+   printf("IP address of %s : %s\n" , ((NET)(netlist.q_head))->name,
+      print_ipad(((NET)(netlist.q_head))->n_ipaddr));
+ 
+#ifndef SUPERLOOP
+   /* call this per-target routine after basic tasks & net are up */
+   msg = post_task_setup();
+   if (msg)
+      panic(msg);
+#endif
+
+#ifdef PING_APP
+   ping_init();
+#endif   /* PING_APP */
+
+#ifdef RAWIPTEST
+   raw_test_init();
+#endif   /* RAWIPTEST */
+
+#if defined(TFTP_CLIENT) || defined(TFTP_SERVER)
+   tftp_init();
+#endif   /* TFTP */
+
+#ifdef TESTMENU
+   install_menu(testmenu);
+#endif   /* TESTMENU */
+#ifdef CSUM_DEMO
+   cksum_init();
+#endif
+
+#ifdef USE_AUTOIP
+   Upnp_init();      /* start Auto IP before DHCP client */
+#endif   /* USE_AUTOIP */
+
+#ifdef DHCP_CLIENT
+   dhc_setup();   /* kick off any DHCP clients */
+#endif   /* DHCP_CLIENT */
+
+#ifdef DHCP_SERVER
+#ifdef INCLUDE_NVPARMS
+   if(dhserve_nvparms.ServeDHCP)
+#endif
+   {
+      e = dhcp_init();
+      if(e)
+      {
+         dprintf("Error %d starting DHCP server.\n",e);
+      }
+      else
+      {
+         exit_hook(dhcpsrv_cleanup);
+         dprintf("Started DHCP server\n");
+      }
+   }
+#endif /* DHCP_SERVER */
+
+#ifdef IN_MENUS
+   printf(prompt);
+#endif
+
+#ifdef UDPSTEST
+   e=udp_echo_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(udp_echo_cleanup);
+   }
+   else
+      dprintf("Error %d starting UDP Echo server.\n",e);
+#endif
+
+#ifdef RIP_SUPPORT
+   e=rip_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(rip_cleanup);
+   }
+   else
+      dprintf("Error %d starting RIP server.\n",e);
+#endif
+
+#ifdef INICHE_SYSLOG
+   e =syslog_init();
+   if (e == SUCCESS)
+      exit_hook(closelog);
+   else
+      dprintf("Error %d initializing syslog client.\n",e);
+#endif
+
+#ifdef FTP_CLIENT
+   fc_callback=ftpc_callback;
+#endif
+
+#ifdef INCLUDE_SSLAPP
+   sslapp_init();
+#endif
+
+#ifdef USE_SNTP_V4
+   sntpv4_init ();
+#endif
+
+/* The following initializations take place when SUPERLOOP is enabled.
+ * Otherwise they would be done in the respective task.
+ */
+
+#ifdef SUPERLOOP
+
+#ifdef INCLUDE_SNMP
+   e = snmp_init();
+   if (e == SUCCESS)
+      exit_hook(snmp_cleanup);
+   else
+      dprintf("Error %d initializing SNMP agent.\n",e);
+#endif   /* INCLUDE_SNMP */
+
+#ifdef WEBPORT
+   e = http_init(); /* start up http server */
+   if (e)
+      dprintf("Error %d starting HTTP server.\n",e);
+#endif   /* WEBPORT */
+
+#ifdef FTP_SERVER
+   e = ftps_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(ftps_cleanup);
+   }
+   else
+      dprintf("Error %d starting FTP server.\n",e);
+#endif   /* FTP_SERVER */
+
+#ifdef TELNET_SVR
+   e=tel_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(tel_cleanup);
+   }
+   else
+      dprintf("Error %d starting TELNET server.\n",e);
+#endif
+
+#ifdef TCP_ECHOTEST
+   e=tcp_echo_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(tcp_echo_cleanup);
+   }
+   else
+      dprintf("Error %d starting TCP Echo server.\n",e);
+#endif
+#ifdef TCP_CIPHERTEST
+   e=tcp_cipher_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(tcp_cipher_cleanup);
+   }
+   else
+      dprintf("Error %d starting TCP cipher server.\n",e);
+#endif
+#ifdef USE_CRYPTOENG
+   e = ce_init();
+   if(e != 0)
+   {
+      dprintf("ce_init() failed\n");
+      panic("prep_modules");
+   }
+#endif
+
+#ifdef SMTP_ALERTS
+   smtp_init ();
+#endif
+
+#ifdef CSUM_DEMO
+   csum_init();
+#endif
+
+#ifdef USE_SNTP_V4
+   e = sntpv4_app ();
+   if(e != 0)
+   {
+      dprintf("Failed to start time sync via SNTPv4 client\n");
+      panic("prep_modules");
+   }
+#endif
+
+#endif   /* SUPERLOOP */
+
+#ifdef INCLUDE_SSLAPP
+   e = sslapp_init();
+   if(e != 0)
+   {
+      dprintf("sslapp_init() failed\n");
+      panic("prep_modules");
+   }
+#endif
+   USE_ARG(e);    /* Avoid compiler warnings */
+
+} /* end of netmain_init() */
+
+
+#ifdef FULL_ICMP
+char * icmpdu_types[] = {
+   "NET",
+   "HOST",
+   "PROT",
+   "PORT",
+   "FRAG",
+   "SRC",
+};
+
+/* FUNCTION: imcp_port_du()
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+void
+icmp_port_du(PACKET p, struct destun * pdp)
+{
+   dprintf("got ICMP %s UNREACHABLE from %s\n", 
+      icmpdu_types[(int)(pdp->dtype)], print_ipad(p->fhost) );
+   dprintf(prompt);
+}
+#endif   /* FULL_ICMP */
+
+
+
+/* FUNCTION: station_state()
+ *
+ * state() - printf some info about the current state of the user 
+ * settable station variables. 
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+station_state(void * pio)
+{
+   int i;
+   
+#ifndef NO_INET_STACK
+   NET ifp;
+
+   for (i = 0, ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next, i++)
+   {
+      ns_printf(pio, "iface %d-%s IP addr:%s  ", 
+       i, ifp->name, print_ipad(ifp->n_ipaddr) );
+      ns_printf(pio, "subnet:%s  ", print_ipad(ifp->snmask) );
+      ns_printf(pio, "gateway:%s\n", print_ipad(ifp->n_defgw) );
+   }
+#endif   /* NO_INET_STACK */
+
+   ns_printf(pio, "current tick count %lu\n", cticks);
+
+   ns_printf(pio, "common delay parameter:  %lu ticks (%lu ms).\n", pingdelay, (pingdelay * TIMEFOR1TICK));
+   ns_printf(pio, "common host parameter: %s\n", print_ipad(activehost));
+   ns_printf(pio, "common length parameter: %d\n", deflength);
+
+#ifdef PING_APP
+   ns_printf(pio, "ping delay:  %lu ticks (%lu ms).\n", ping4_delay, (ping4_delay * TIMEFOR1TICK));
+   ns_printf(pio, "ping host: %s\n", print_ipad(ping4_activehost));
+   ns_printf(pio, "ping length: %lu\n", ping4_deflength);
+#endif
+
+#ifdef USE_MODEM
+   ns_printf(pio, "current dialout number is %s\n", mdm_dial_string);
+#endif   /* USE_MODEM */
+
+#ifdef USE_PPP
+   ns_printf(pio, "current dial-in user name is %s\n", pppcfg.username);
+   ns_printf(pio, "current dial-in password is %s\n", pppcfg.password);
+#endif   /* USE_PPP */
+
+   task_stats(pio);
+
+   return 0;
+}
+
+#ifdef FTP_CLIENT
+/* If FC_USECALLBACK is enabled in ftpclnt.h, and if fc_callback 
+ * is defined, then FTP Client will call fc_callback when 
+ * its state changes. FC_USECALLBACK is enabled by default. 
+ */
+
+void ftpc_callback(void *fc,int logstate, int cmdstate)
+{
+   /*
+   dprintf("logstate=%d, cmdstate=%d\n",logstate,cmdstate);
+   */
+
+   USE_VOID(fc);
+   USE_ARG(logstate);
+   USE_ARG(cmdstate);
+}
+
+#endif 
+
+
+#ifndef NO_INET_STACK   /* these functions are pretty stack-centric */
+
+
+/* FUNCTION: sysuptime()
+ * 
+ * sysuptime() - return MIB-2 sys group compatable "sysUptime" value
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+unsigned long
+sysuptime()
+{
+   return ((cticks/TPS)*100);    /* 100ths of a sec since boot time */
+}
+
+
+/* FUNCTION: packet_check() - check for incoming packet 
+ * Process incoming packets.
+ *
+ * inside_pktdemux is nonzero while processing a received packet. 
+ * It is used for reentrancy protection. 
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+
+static int inside_pktdemux = 0; 
+
+void
+packet_check(void)
+{
+   if(inside_pktdemux != 0)   /* check re-entrancy flag */
+      return;           /* do not re-enter pktdemux(), packet will wait... */
+   inside_pktdemux++;   /* set re-entrany flag */
+   pktdemux();          /* process low level packet input */
+   inside_pktdemux--;   /* clear re-entrany flag */
+}
+
+#ifdef IP_MULTICAST
+/* This is a dummy routine that is replaced by the porting engineer with
+ * a routine by the same name in the Ethernet driver.  The purpose of this
+ * routine is to convert IP multicast addresses to their Ethernet multicast
+ * addresses and program the chip with the appropriate Ethernet multicast
+ * filters.  In the case of PPP, this dummy routine can be used.
+ */
+
+
+/* FUNCTION: mcastlist()
+ * 
+ * PARAM1: struct in_multi *multi_ptr
+ *
+ * RETURNS: 
+ */
+
+int
+mcastlist(struct in_multi * multi_ptr)
+{
+   USE_ARG(multi_ptr);
+
+   return 0;
+}
+#endif   /* IP_MULTICAST */
+
+/********* For Superloop AND Netmain builds *********************/
+
+/* FUNCTION: prep_modules()
+ * 
+ * Call the preparation functions for all modules.
+ * Each module can have a preparation function wherein it
+ * intializes the menu, nvparms, etc.
+ *
+ * PARAM1: 
+ *
+ * RETURNS:  0 on SUCCESS.
+ *
+ */
+
+
+#ifdef USE_PPP
+extern   int   ppp_setup(void);
+#endif   /* USE_PPP */
+
+#ifdef USE_MODEM
+extern   int   prep_modem(void);
+#endif   /* USE_MODEM */
+
+int prep_modules(void)
+{
+#ifdef IP_V6
+   ip6_addr host;
+   int i;
+#endif
+
+int e = 0;
+
+
+#ifdef IP_V6
+   for (i = 0; i < STATIC_NETS; i++)
+   {
+		/* zero out addresses */
+		{
+			int ifIndx;
+
+			for (ifIndx = 0; ifIndx < MAX_V6_ADDRS; ifIndx++)
+				netstatic[i].v6addrs[ifIndx] = (struct ip6_inaddr *)0;
+			for (ifIndx = 0; ifIndx < MAX_V6_ADDRS; ifIndx++)
+				netstatic[i].v6addrsExtd[ifIndx] = (struct ip6_inaddr *)0;
+		}
+   }
+   ip6_init();
+#endif
+
+#ifdef PING_APP
+   ping_init();
+#endif   /* PING_APP */
+
+
+#ifdef USE_CRYPTOENG
+   e = ce_init();
+   if(e != 0)
+   {
+      dprintf("ce_init() failed\n");
+      panic("prep_modules");
+   }
+#endif
+#ifdef USE_PPP
+   e = ppp_setup();
+   if (e != 0)
+   {
+      dprintf("PPP Module setup failed\n");
+      panic("prep_modules");
+   }
+#endif   /* USE_PPP */
+
+#ifdef USE_MODEM
+   e = prep_modem();
+   if (e != 0)
+   {
+      dprintf("Modem Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* USE_MODEM */
+
+#ifdef TELNET_SVR
+   e = prep_telnet();
+   if (e != 0)
+   {
+      dprintf("Telnet Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* TELNET_SVR */
+
+#ifdef DHCP_SERVER
+   e = prep_dhcpsrv();
+   if (e != 0)
+   {
+      dprintf("DHCP Server Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* DHCP_SERVER */
+
+#ifdef NATRT
+   e = prep_natrt();
+   if (e != 0)
+   {
+      dprintf("Nat Router Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* NATRT */
+
+#ifdef RIP_SUPPORT
+   e = prep_rip();
+   if (e != 0)
+   {
+      dprintf("Rip Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* RIP_SUPPORT */
+
+#ifdef INCLUDE_SNMP
+   e = prep_snmp();
+   if (e != 0)
+   {
+      dprintf("SNMP Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* INCLUDE_SNMP */
+
+#ifdef INICHE_SYSLOG
+   e = prep_syslog();
+   if (e != 0)
+   {
+      dprintf("Syslog Client prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* INICHE_SYSLOG */
+
+#ifdef SMTP_ALERTS
+   e = prep_smtp();
+   if (e != 0)
+   {
+      dprintf("SMTP Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* SMTP_ALERTS */
+
+#ifdef VFS_FILES
+   e = prep_vfs();
+   if (e != 0)
+   {
+      dprintf("VFS Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* VFS_FILES */
+
+
+#ifdef FTP_CLIENT
+   e = prep_ftpc();
+   if (e != 0)
+   {
+      dprintf("FTP Client Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* FTP_CLIENT */
+
+#ifdef WEBPORT
+   e = prep_http();
+   if (e != 0)
+   {
+      dprintf("Web Server Module prep failed\n");
+      panic("prep_modules");
+   }
+#endif   /* WEBPORT */
+
+#ifdef INCLUDE_SSLAPP
+   e = sslapp_init();
+   if(e != 0)
+   {
+      dprintf("sslapp_init() failed\n");
+      panic("prep_modules");
+   }
+#endif
+   return 0;
+}
+
+#endif   /* NO_INET_STACK */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c
new file mode 100644
index 0000000..eecfcf1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/timeouts.c
@@ -0,0 +1,360 @@
+/*
+ * FILENAME: timeouts.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Handles InterNiche task & application interval timers.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: inet_timer(),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+#include "in_utils.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "arp.h"
+#include "ip.h"
+
+#ifdef INICHE_TIMERS    /* build using interval timers? */
+#include "intimers.h"
+static void check_interval_timers(void);
+#endif
+
+#ifdef INCLUDE_TCP
+void  tcp_tick(void);
+#endif
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+/* Call igmp timeout routine */
+extern   unsigned long  igmp_cticks;
+extern   void igmp_fasttimo(void);
+#endif   /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+
+#ifdef USE_PPP
+extern   void ppp_timeisup(void);
+#endif
+#ifdef DHCP_CLIENT
+extern   int dhc_discover(int iface);
+extern   int dhc_second(void);
+#endif
+#ifdef DHCP_SERVER
+extern   void dhcp_timeisup(void);
+#endif
+#ifdef FTP_SERVER
+extern   void ftps_check(void);
+#endif
+#ifdef DNS_CLIENT
+extern   void dns_check(void);
+#endif
+#ifdef NATRT
+extern   void nat_timeisup(void);
+#endif
+#ifdef USE_MODEM
+extern   void dial_check(void);
+#endif
+#ifdef USE_COMPORT
+extern   void uart_check(void);
+#endif
+#ifdef PING_APP
+void ping_check(void);
+#endif
+#ifdef IP_V6
+void ip6_timer(void);
+static unsigned long v6timer_mod = 0L;
+#endif
+#ifdef TCP_ECHOTEST
+void tcp_echo_poll(void);
+#endif
+#if defined(TFTP_CLIENT) || defined(TFTP_SERVER)
+extern   void  tftp_tick(void);
+#endif
+#ifdef UDPSTEST
+extern void   udp_echo_poll(void);
+#endif /* UDPSTEST */
+#ifdef RIP_SUPPORT 
+extern void   rip_check(void);
+#endif /* RIP_SUPPORT */
+#ifdef INCLUDE_SNMP
+extern void snmp_check(void);
+#endif 
+#ifdef BTREE_ROUTES
+extern void   rtbtree_tmo(void);
+#endif   /* BTREE_ROUTES */
+#ifdef RAWIPTEST
+extern void   raw_testerq_poll(void);
+#endif /* RAWIPTEST */
+#ifdef WEBPORT
+extern   void  http_check(void);
+#endif
+#ifdef TELNET_SVR
+extern   void  tel_check(void);
+#endif
+#ifdef FTP_CLIENT
+void ftpc_periodic_timer(void);
+#endif
+#ifdef IP_FRAGMENTS
+extern u_long ire_cticks;
+extern u_char ip_reasm_process_timer_tick(void);
+#endif
+#ifdef USE_SNTP_V4
+extern int sntpv4_timeout(void);
+#endif
+
+/* if INICHE_TASKS is defined, this is done vxd_task() in task for Vxd */
+#ifndef INICHE_TASKS
+#ifdef USE_VXD
+extern void vxd_check(void);
+#endif
+#endif
+
+unsigned long nextppp = 0L;   /* tick for next call to ppp timer */
+
+void (*port_1s_callout)(void) = NULL;
+
+/* FUNCTION: inet_timer()
+ *
+ * This handles all TCP/IP related timeouts. Ideally this should be 
+ * called about 10 times a second; and no less than twice a second 
+ * (The minimum for TCP timeouts). Does NOT handle most
+ * application timeouts. 
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void
+inet_timer(void)
+{
+#ifdef IP_FRAGMENTS
+   /* run thru' the IP reassembly queue (once every second) */
+   if (ire_cticks < cticks)
+      ip_reasm_process_timer_tick ();
+#endif
+
+#ifdef INCLUDE_TCP
+   tcp_tick();          /* run TCP timers */
+#endif
+
+#ifdef INICHE_TIMERS    /* interval timers? */
+   check_interval_timers();
+#endif
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   /* Call igmp timeout routine */
+   if (igmp_cticks < cticks)  /* Call igmp timeout routine 5 times per sec */
+      igmp_fasttimo();
+#endif   /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+
+#ifdef USE_SNTP_V4
+      sntpv4_timeout ();
+#endif
+
+#ifdef USE_MODEM
+   dial_check();
+#endif   /* USE_MODEM */
+
+#ifdef USE_COMPORT
+   uart_check();
+#endif
+
+#ifdef UDPSTEST
+   udp_echo_poll();
+#endif
+
+#ifdef PING_APP
+   ping_check();  /* check for ping send/receive */
+#endif
+
+#ifdef RAWIPTEST
+   raw_testerq_poll();
+#endif
+
+
+#ifdef SUPERLOOP
+#ifdef WEBPORT
+      http_check();
+#endif 
+#ifdef TELNET_SVR
+      tel_check();
+#endif 
+#ifdef INCLUDE_SNMP
+      snmp_check();
+#endif 
+#endif /* SUPERLOOP */
+
+
+/* if INICHE_TASKS is defined, this is done vxd_task() in task for Vxd */
+#if (defined(USE_VXD) && !defined(INICHE_TASKS))
+   vxd_check();
+#endif
+
+/* !!!???  */
+#ifdef IP_V6
+   if ((v6timer_mod < cticks) ||  /* next call to ip6_timer is due */
+       (v6timer_mod > (cticks + (10 * TPS))) )  /* for when cticks wraps */
+   {
+      v6timer_mod = cticks + (TPS / 5);
+      ip6_timer();
+   }
+#endif
+
+
+
+   /* Some timer routines only need calling once a second: */
+   if ((nextppp < cticks) ||  /* next call to PPP is due */
+       (nextppp > (cticks+(10*TPS))) )  /* for when cticks wraps */
+   {
+      nextppp = cticks + TPS;
+
+      if (port_1s_callout != NULL)
+         (*port_1s_callout)();
+
+#ifdef USE_PPP
+      ppp_timeisup();
+#endif
+#ifdef DHCP_CLIENT
+      dhc_second();
+#endif
+#ifdef DHCP_SERVER
+      dhcp_timeisup();
+#endif
+#ifdef DNS_CLIENT
+      dns_check();
+#endif
+#ifdef NATRT
+      nat_timeisup();
+#endif
+#ifdef RIP_SUPPORT 
+      rip_check();
+#endif 
+#if defined(TFTP_CLIENT) || defined(TFTP_SERVER)
+      tftp_tick();
+#endif
+
+#ifdef BTREE_ROUTES
+      rtbtree_tmo();
+#endif   /* BTREE_ROUTES */
+#ifdef FTP_CLIENT
+      ftpc_periodic_timer();
+#endif
+#ifdef IPSEC
+      IPSecTimer();
+#endif
+   }
+}
+
+
+#ifdef INICHE_TIMERS
+
+struct intimer intimers[NUM_INTIMERS];
+
+/* FUNCTION: check_interval_timers()
+ *
+ * Check to see if any interval timers are ready to fire.
+ *
+ * RETURNS: NA
+ */
+
+static int numtimers = 0;     /* number of active timers */
+
+static void
+check_interval_timers(void)
+{
+   int   i;
+   int   found = 0;  /* number of valid timers found */
+
+   /* if no timers, just return */
+   if (numtimers > 0)
+   {
+      /* loop throught the timer list looking for active timers ready to fire */
+      for (i = 0; i < NUM_INTIMERS; i++)
+      {
+         if (intimers[i].callback)   /* is this timer active? */
+	 {
+            if ((intimers[i].tmo < cticks) && (!intimers[i].inuse))  /* timer ready fire? */
+            {
+               intimers[i].tmo = intimers[i].interval + cticks;   /* set next tmo */
+               intimers[i].inuse = TRUE;
+               intimers[i].callback(intimers[i].parm);      /* call user routine */
+               intimers[i].inuse = FALSE;
+            }
+            /* If we've examined all the active timers, we're done */
+            if (++found >= numtimers)
+               break;
+         }
+      }
+   }
+}
+
+/* FUNCTION: in_timerset()
+ *
+ * Create an interval timer
+ * 
+ * PARAM1: callback routine 
+ * PARAM2: number of milliseconds between callback calls
+ * PARAM3: parameter to pass to callbacks
+ *
+ * RETURNS: timer ID if OK, else if table is full.
+ */
+
+long
+in_timerset(void (*callback)(long), long msecs, long parm)
+{
+   int   i;
+
+   for(i = 0; i < NUM_INTIMERS; i++)
+   {
+      if(intimers[i].callback == NULL)
+      {
+         /* found empty table entry, set up new timer */
+         intimers[i].callback = callback;
+         intimers[i].parm = parm;
+         /* set interval, in TPS (cticks) units */
+         intimers[i].interval = (msecs * TPS)/1000;
+         intimers[i].tmo = intimers[i].interval + cticks;   /* first tmo */
+		 intimers[i].inuse = FALSE;
+         numtimers++;
+         return (long)&intimers[i];
+      }
+   }
+   return 0;
+}
+
+/* FUNCTION: in_timerkill()
+ *
+ * Delete a timer created previously by a call to in_timerset()
+ * 
+ * PARAM1: long timer Address of the timer to delete.
+ *
+ * RETURNS: 0 if OK, ENP error if timer not in list.
+ */
+
+
+int
+in_timerkill(long timer)
+{
+   int   i;
+
+   for(i = 0; i < NUM_INTIMERS; i++)
+   {
+      if(timer == (long)&intimers[i])
+      {
+         intimers[i].callback = NULL;
+         numtimers--;
+         return 0;      /* OK return */
+      }
+   }
+   dtrap();    /* timer to kill not found */
+   return ENP_PARAM;
+}
+
+#endif   /* INICHE_TIMERS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c b/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c
new file mode 100644
index 0000000..65c44bd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/allports/tk_misc.c
@@ -0,0 +1,358 @@
+/*
+ * FILENAME: tk_misc.c
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Routines to create Network Tasks for the Generic Multitasking systems ports
+ * of InterNiche TCP/IP NetOS package. Also contains other miscellaneous 
+ * routines for Multitasking ports.
+ *
+ * MODULE: ALLPORTS
+ *
+ * ROUTINES: create_apptasks(), tk_keyboard()
+ * ROUTINES: task_stats()
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "libport.h"
+
+/* Multitasking systems should use this file, however superloop
+ *systems need to be able to ifdef it away
+ */
+
+#ifndef SUPERLOOP /* whole file can be ifdeffed out */
+
+/* include project header. Define this in ipport.h to point to a file
+ * in your project directory, i.e. "..\******\osport.h"
+ */
+ 
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+#include OSPORT_H
+
+#ifdef WEBPORT
+extern struct inet_taskinfo httptask;
+extern long webport_wakes;
+#endif
+#ifdef FTP_SERVER
+extern struct inet_taskinfo ftpstask;
+extern long ftpsrv_wakes;
+#endif
+#ifdef FTP_CLIENT
+extern struct inet_taskinfo ftpctask;
+#endif
+#ifdef SMTP_ALERTS
+extern struct inet_taskinfo smtptask;
+extern long emailer_wakes;
+#endif
+#ifdef TELNET_SVR
+extern struct inet_taskinfo telnettask;
+extern long telnetsrv_wakes;
+#endif
+#ifdef USE_CRYPTOENG
+extern struct inet_taskinfo cuexecutetask;
+extern long cuexecute_wakes;
+#endif
+#ifdef USE_SYSLOG_TASK
+extern struct inet_taskinfo syslog_task;
+extern long syslog_wakes;
+#endif
+#ifdef INCLUDE_SNMP
+extern struct inet_taskinfo snmptask;
+extern long snmp_wakes;
+#endif
+#ifdef DNS_SERVER
+extern struct inet_taskinfo dnssrvtask;
+#endif
+#ifdef NICHVIEW
+extern struct inet_taskinfo browtask;
+extern long browtask_wakes;
+#endif
+#ifdef TK_STDIN_DEVICE
+extern struct inet_taskinfo keyboardtask;
+extern long keyboard_wakes;
+extern void kbdio(void);
+#endif
+#ifdef USE_SNTP_V4
+extern struct inet_taskinfo sntpv4apptask;
+#endif
+#ifndef NO_INET_STACK
+extern long netmain_wakes;
+#endif   /* NO_INET_STACK */
+#ifndef NO_INET_TICK
+extern long nettick_wakes;
+#endif   /* NO_INET_TICK */
+#ifdef PING_APP
+extern long pingcheck_wakes;
+#endif   /* #ifdef PING_APP */
+#ifdef TCP_ECHOTEST
+extern long echotest_wakes;
+#endif   /* TCP_ECHOTEST */
+#ifdef TCP_CIPHERTEST
+extern long ciphertest_wakes;
+#endif   /* TCP_CIPHERTEST */
+#ifdef IKE
+extern struct inet_taskinfo iketask;
+extern long ike_wakes;
+#endif
+#ifdef INCLUDE_SSLAPP
+extern struct inet_taskinfo sslapp_task;
+extern long sslapp_wakes;
+#endif
+/* per-application thread definitions */
+
+int
+create_apptasks(void)
+{
+int e = 0;
+#ifdef USE_CRYPTOENG
+   e = TK_NEWTASK(&cuexecutetask);
+   if (e != 0)
+   {
+      dprintf("cuexecutetask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef WEBPORT
+   e = TK_NEWTASK(&httptask);
+   if (e != 0)
+   {
+      dprintf("httptask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef FTP_SERVER
+   e = TK_NEWTASK(&ftpstask);
+   if (e != 0)
+   {
+      dprintf("ftpstask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef FTP_CLIENT
+   e = TK_NEWTASK(&ftpctask);
+   if (e != 0)
+   {
+      dprintf("ftpctask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef SMTP_ALERTS
+   e = TK_NEWTASK(&smtptask);
+   if (e != 0)
+   {
+      dprintf("smtptask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef TELNET_SVR
+   e = TK_NEWTASK(&telnettask);
+   if (e != 0)
+   {
+      dprintf("telnettask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef INCLUDE_SNMP
+   e = TK_NEWTASK(&snmptask);
+   if (e != 0)
+   {
+      dprintf("snmptask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef DNS_SERVER
+   e = TK_NEWTASK(&dnssrvtask);
+   if (e != 0)
+   {
+      dprintf("dnssrvtask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef NICHVIEW
+   e = TK_NEWTASK(&browtask);
+   if (e != 0)
+   {
+      dprintf("browtask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef TK_STDIN_DEVICE
+   e = TK_NEWTASK(&keyboardtask);
+   if (e != 0)
+   {
+      dprintf("keyboardtask create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef IKE
+   e = TK_NEWTASK(&iketask);
+   if (e != 0)
+   {
+      dprintf("IKE create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef USE_SYSLOG_TASK
+   e = TK_NEWTASK(&syslog_task);
+   if(e != 0)
+   {
+      dprintf("syslog_task create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef INCLUDE_SSLAPP
+   e = TK_NEWTASK(&sslapp_task);
+   if (e != 0)
+   {
+      dprintf("sslapp_task create error\n");
+      panic("create_apptasks");
+      return -1;  /* compiler warnings */
+   }
+#endif
+#ifdef USE_SNTP_V4
+   e = TK_NEWTASK(&sntpv4apptask);
+   if(e != 0)
+   {
+      dprintf("SNTPv4 application task create error\n");
+      panic("create_apptasks");
+      return -1;
+   }
+#endif
+/* 
+ * Altera Niche Stack Nios port modification:
+ * return error code, if any 
+ */
+   return e;
+}
+
+#ifdef TK_STDIN_DEVICE
+extern   void  kbdio(void);
+#endif
+
+#ifdef TK_STDIN_DEVICE
+TK_OBJECT(to_keyboard);
+TK_ENTRY(tk_keyboard);
+long     keyboard_wakes =  0;
+#endif   /* TK_STDIN_DEVICE */
+
+#ifdef TK_STDIN_DEVICE
+struct inet_taskinfo keyboardtask = {
+      &to_keyboard,
+      "console",
+      tk_keyboard,
+      TK_KEYBOARD_TPRIO,
+      IO_STACK_SIZE,
+};
+#endif
+
+
+/* FUNCTION: TK_ENTRY()
+ *
+ * Task to hand keystrokes to InerNiche menu system
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+#ifdef TK_STDIN_DEVICE
+TK_ENTRY(tk_keyboard)
+{
+   for (;;)
+   {
+      TK_SLEEP(1);   /* make keyboard yield some time */
+      kbdio(); /* let Iniche menu routines poll for char */
+      keyboard_wakes++; /* count wakeups */
+
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+#endif   /* TK_STDIN_DEVICE */
+
+
+
+/* FUNCTION: task_stats()
+ * 
+ * Print the "wake" statistics of all tasks.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+
+void
+task_stats(void * pio)
+{
+   ns_printf(pio, "Task wakeups:");
+
+#ifndef NO_INET_STACK
+   ns_printf(pio, "netmain: %lu\n", netmain_wakes);
+#endif
+#ifndef NO_INET_TICK
+   ns_printf(pio, "nettick: %lu\n", nettick_wakes);
+#endif
+#ifdef TK_STDIN_DEVICE
+   ns_printf(pio, "keyboard: %lu\n", keyboard_wakes);
+#endif
+#ifdef WEBPORT
+   ns_printf(pio, "webport: %lu  ", webport_wakes);
+#endif
+#ifdef FTP_SERVER
+   ns_printf(pio, "ftpsrv: %lu  ", ftpsrv_wakes);
+#endif
+#ifdef PING_APP
+   ns_printf(pio, "pingcheck: %lu  ", pingcheck_wakes);
+#endif
+#ifdef TELNET_SVR
+   ns_printf(pio, "telnetsrv: %lu  ", telnetsrv_wakes);
+#endif
+#ifdef USE_CRYPTOENG
+   ns_printf(pio, "USE_CRYPTOENG: %lu  ", cuexecute_wakes);
+#endif
+#ifdef USE_SYSLOG_TASK
+   ns_printf(pio, "USE_SYSLOG_TASK: %lu  ", syslog_wakes);
+#endif
+#ifdef SMTP_ALERTS
+   ns_printf(pio, "smtpclient: %lu  ", emailer_wakes);
+#endif
+#ifdef SNMP_SOCKETS
+   ns_printf(pio, "snmpsock: %lu  ", snmp_wakes);
+#endif
+#ifdef TCP_ECHOTEST
+   ns_printf(pio, "echotest: %lu  ", echotest_wakes);
+#endif
+#ifdef TCP_CIPHERTEST
+   ns_printf(pio, "ciphertest: %lu  ", ciphertest_wakes);
+#endif
+#ifdef USE_BROWSER
+   ns_printf(pio, "browtask: %lu  ", browtask_wakes);
+#endif
+#ifdef INCLUDE_SSLAPP
+   ns_printf(pio, "INCLUDE_SSLAPP: %lu  ", sslapp_wakes);
+#endif
+   ns_printf(pio, "\n");
+}
+
+
+#endif   /* SUPERLOOP - whole file can be ifdeffed out */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c
new file mode 100644
index 0000000..d989cb9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_close.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+* To provide your own implementation of a HAL function, include the file in   *
+* your Nios II IDE application project. When building the executable, the     *
+* Nios II IDE finds your function first, and uses it in place of the HAL      *
+* version.                                                                    *
+*                                                                             *
+******************************************************************************/
+
+#include "system.h"
+#include "sys/alt_sys_wrappers.h"
+#include "ipport.h"
+#include "tcpport.h"
+
+/*
+ * close() is called by an application to release a file descriptor. This 
+ * implementation vectors requests to either the HAL alt_close() function 
+ * (for files and device drivers) or the InterNiche soclose() function for
+ * sockets.
+ */
+ 
+int close (int fd)
+{
+  return (fd < ALT_MAX_FD) ? alt_close (fd) : t_socketclose ((long) fd);
+}
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c
new file mode 100644
index 0000000..1414a20
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_dev.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+*                                                                             *
+* Source for the Altera InterNiche device services.                           *
+*                                                                             *
+* Author EPS                                                                  *
+*                                                                             *
+******************************************************************************/
+
+/*******************************************************************************
+ *******************************************************************************
+ *
+ * InterNiche device services.
+ *
+ *******************************************************************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Imported services.
+ *
+ ******************************************************************************/
+
+#include "sys/alt_llist.h"
+#include "alt_iniche_dev.h"
+
+#ifdef IP_MULTICAST
+#include "ipmc/igmp_cmn.h"
+extern int mcastlist(struct in_multi *);
+#endif
+
+
+/*******************************************************************************
+ *
+ * InterNiche device service globals.
+ *
+ ******************************************************************************/
+
+/* List of InterNiche devices. */
+ALT_LLIST_HEAD(alt_iniche_dev_list);
+
+
+/*******************************************************************************
+ *
+ * InterNiche device service functions.
+ *
+ ******************************************************************************/
+
+/*
+ * iniche_devices_init
+ *
+ *   --> if_count               Number of interfaces before init.
+ *
+ *   <--                        Number of interfaces after init.
+ *
+ *   This function initializes the InterNiche devices.  The number of interfaces
+ * before initialization is specified by if_count.  This function returns the
+ * total number of interfaces after initialization.
+ */
+
+int iniche_devices_init(
+    int                         if_count)
+{
+    alt_iniche_dev              *p_dev;
+    alt_iniche_dev              *p_dev_list_end;
+    NET                         p_net;
+    ip_addr                     ipaddr,
+                                netmask,
+                                gw;
+    int                         use_dhcp;
+
+    /* Get the InterNiche device list. */
+    p_dev = (alt_iniche_dev *) (alt_iniche_dev_list.next);
+    p_dev_list_end = (alt_iniche_dev *) (&(alt_iniche_dev_list.next));
+
+    /* Initialize each InterNiche device. */
+    while (p_dev != p_dev_list_end)
+    {
+        /* Initialize the InterNiche device data record. */
+        p_dev->p_driver_data = p_dev;
+        p_dev->if_num = if_count;
+        p_dev->p_net = nets[p_dev->if_num];
+
+        /* Perform device specific initialization. */
+        (*(p_dev->init_func))(p_dev);
+
+        /* Get the interface IP address. */
+        p_net = p_dev->p_net;
+                
+        if (get_ip_addr(p_dev, &ipaddr, &netmask, &gw, &use_dhcp))
+        {
+#ifdef DHCP_CLIENT
+            /* 
+             * OR in the DHCP flag, if enabled. This will allow any
+             * application-specific flag setting in get_ip_addr(), such 
+             * as enabling AUTOIP, to occur 
+             */
+            if (use_dhcp) {
+                p_net->n_flags |= NF_DHCPC;
+            }
+#endif
+            p_net->n_ipaddr = ipaddr;
+            p_net->snmask = netmask;
+            p_net->n_defgw = gw;
+#ifdef IP_MULTICAST
+	    p_net->n_mcastlist = mcastlist;
+#if defined (IGMP_V1) || defined (IGMP_V2)
+            p_net->igmp_oper_mode = IGMP_MODE_DEFAULT;
+#endif  /* IGMPv1 or IGMPv2 */
+#endif  /* IP_MULTICAST */
+        }
+
+        /* Initialize next device. */
+        if_count++;
+        p_dev = (alt_iniche_dev *) p_dev->llist.next;
+    }
+
+    return (if_count);
+}
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c
new file mode 100644
index 0000000..fa12d36
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_fcntl.c
@@ -0,0 +1,74 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+******************************************************************************/
+
+#include <fcntl.h>
+#include <stdarg.h>
+#include "system.h"
+#include "sys/alt_sys_wrappers.h"
+#include "ipport.h"
+#include "tcpport.h"
+
+/*
+ * fcntl() is called by an application to release a file descriptor. This 
+ * implementation duplicates the code of the HAL alt_fcntl() function 
+ * (for files and device drivers) or calls the InterNiche bsd_ioctl for 
+ * sockets.
+ */
+ 
+int fcntl (int file, int cmd, ...)
+{
+  long     flags;
+  va_list  argp;
+
+  if (file < ALT_MAX_FD)
+  {
+    va_start(argp, cmd);
+    flags = va_arg(argp, long);
+    va_end(argp);
+    return alt_fcntl(file, cmd, flags);
+  }
+  else
+  {
+    va_start(argp, cmd);
+    flags = va_arg(argp, long);
+    va_end(argp);
+    return bsd_ioctl(file, cmd, flags);
+  }
+}
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c
new file mode 100644
index 0000000..aa88600
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_read.c
@@ -0,0 +1,64 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+* To provide your own implementation of a HAL function, include the file in   *
+* your Nios II IDE application project. When building the executable, the     *
+* Nios II IDE finds your function first, and uses it in place of the HAL      *
+* version.                                                                    *
+*                                                                             *
+******************************************************************************/
+
+#include <unistd.h>
+#include "sys/alt_sys_wrappers.h"
+#include "system.h"
+#include "ipport.h"
+#include "tcpport.h"
+
+/*
+ * The read() system call is used to read a block of data from a file or device.
+ * This implementation vectors requests to either the HAL alt_read() function 
+ * (for files and device drivers) or the InterNiche recvfrom() function for
+ * sockets.
+ */
+
+int read (int fd, void *ptr, size_t len)
+{
+  return (fd < ALT_MAX_FD) ? alt_read (fd, ptr, len)
+                           : recvfrom(fd, ptr, len, 0, NULL, NULL);
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c
new file mode 100644
index 0000000..eed9e14
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/alt_iniche_write.c
@@ -0,0 +1,72 @@
+/******************************************************************************
+*                                                                             *
+* License Agreement                                                           *
+*                                                                             *
+* Copyright (c) 2006 Altera Corporation, San Jose, California, USA.           *
+* All rights reserved.                                                        *
+*                                                                             *
+* Permission is hereby granted, free of charge, to any person obtaining a     *
+* copy of this software and associated documentation files (the "Software"),  *
+* to deal in the Software without restriction, including without limitation   *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
+* and/or sell copies of the Software, and to permit persons to whom the       *
+* Software is furnished to do so, subject to the following conditions:        *
+*                                                                             *
+* The above copyright notice and this permission notice shall be included in  *
+* all copies or substantial portions of the Software.                         *
+*                                                                             *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
+* DEALINGS IN THE SOFTWARE.                                                   *
+*                                                                             *
+* This agreement shall be governed in all respects by the laws of the State   *
+* of California and by the laws of the United States of America.              *
+*                                                                             *
+* Altera does not recommend, suggest or require that this reference design    *
+* file be used in conjunction or combination with any other product.          *
+******************************************************************************/
+
+/******************************************************************************
+*                                                                             *
+* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY.           *
+*                                                                             *
+* Overriding HAL Functions                                                    *
+*                                                                             *
+* To provide your own implementation of a HAL function, include the file in   *
+* your Nios II IDE application project. When building the executable, the     *
+* Nios II IDE finds your function first, and uses it in place of the HAL      *
+* version.                                                                    *
+*                                                                             *
+******************************************************************************/
+
+#include <unistd.h>
+#include "sys/alt_sys_wrappers.h"
+#include "system.h"
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifndef ALT_NICHESTACK_ALT_SYSCALL_H
+    #error "The NicheStack component header file 'os/alt_syscall.h' is not being used. \
+Please delete the HAL version of this file from the BSP."
+#endif
+/*
+ * The write() system call is used to write a block of data to a file or device.
+ * This implementation vectors requests to either the HAL alt_write() function 
+ * (for files and device drivers) or the InterNiche send() function for sockets.
+ */
+
+int write (int fd, const void *ptr, size_t len)
+{
+  if (fd < ALT_MAX_FD)
+  {
+    return alt_write (fd, ptr, len);
+  }
+  else
+  { 
+    return send (fd, (void*) ptr, len, 0);
+  }  
+}
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c
new file mode 100644
index 0000000..d32bf8b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.c
@@ -0,0 +1,383 @@
+/*
+ * FILENAME: autoip.c
+ *
+ * Copyright  2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *   AutoIP ARPs random IP addresses in a private, non-routed range.
+ *   range: 169.254.x.x
+ *   If nothing replys it assigns itself the address.
+ *
+ *   9/15/2000 - Created - Stan Breitlow
+ *
+ * MODULE: AUTOIP4
+ *
+ * ROUTINES: AutoIp_init(), AutoIp_tick(), 
+ * ROUTINES: AutoIp_arp_response(), AutoIp_send_arp_probe(), 
+ * ROUTINES: AutoIp_pick_address(), AutoIp_get_state(), 
+ * ROUTINES: AutoIp_set_net_vars(),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef USE_AUTOIP
+#ifndef DHCP_CLIENT
+#error DHCP_CLIENT must be defined with USE_AUTOIP
+#endif
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "ether.h"
+#include "arp.h"
+#include "dhcpclnt.h"
+
+#include "autoip.h"
+#include "upnp.h"
+
+/* Set defaults for Base & range on AUtoIP address pool */
+u_long   dBASE_AUTO_IP_ADDRESS =    0xA9FE0100;    /* 169.254.1.0 */
+u_long   dMAX_AUTO_IP_ADDRESS  =    0xA9FEFEFF;    /* 169.254.254.255 */
+
+#define  dRESPONSE_TIMEOUT       2000  /* 2  seconds */
+#define  dVERIFY_WAIT_TIME       1000  /* 1  second */
+#define  dNUMBER_OF_VERIFIES     3
+
+
+/* local protos */
+static ip_addr AutoIp_pick_address(void);
+static void AutoIp_set_net_vars(int iface);
+
+extern   void fixup_subnet_mask(int netnum); /* in ipnet.c */
+
+unshort rand_seed;   /* pseudo-random number */
+
+struct autoIP autoIPs[MAXNETS];
+
+/* FUNCTION: AutoIp_init()
+ * 
+ *   Initialize the sub modules
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0
+ */
+
+int
+AutoIp_init()
+{
+   int      iface;
+   void *   stack_garbage = &iface;    /* sort of random... */
+
+   /* look for an ethernet to seed the random numbers */
+   for(iface = 0; iface < MAXNETS; iface++)
+   {
+      if(nets[iface] == NULL)
+         break;
+
+      if(nets[iface]->n_mib->ifType == ETHERNET)
+      {
+         autoIPs[iface].state = AUTOIP_START;
+         autoIPs[iface].response_timer = 0;
+         autoIPs[iface].arp_attempts = 0;
+
+         /* seed with unique part of mac address  */
+         if(!rand_seed)
+         {
+            rand_seed = (unshort)(nets[iface]->mib.ifPhysAddress[3] + 
+               (nets[iface]->mib.ifPhysAddress[4] << 4) + 
+               (nets[iface]->mib.ifPhysAddress[5] << 8));
+         }
+      }
+      else
+         upnp[iface].state = UPNP_DISABLED;  /* Disable Non-ethernets */
+   }
+   /* XOR the random numbers from whatever garbage is on the stack.
+    * This may generate a compiler warning, but it's doing the right thing.
+    */
+   rand_seed ^= (unshort)(u_long)(stack_garbage);
+
+   return 0;
+}
+
+#ifndef HAL_TIMER_ALREADY
+u_long HAL_TIMER_get_ms_tick()
+{
+   return (cticks * (1000/TPS));
+}
+#endif
+
+/* FUNCTION: AutoIp_tick()
+ * 
+ * Called from Upnp_tick() every 100ms to run finite state machine
+ *
+ * PARAM1: void
+ *
+ * RETURNS: void
+ */
+
+void
+AutoIp_tick(int iface)
+{
+   switch (autoIPs[iface].state)
+   {
+   case AUTOIP_START:
+      autoIPs[iface].state = AUTOIP_ARP_PROBE;
+      break;
+
+   case AUTOIP_ARP_PROBE:
+
+      autoIPs[iface].try_address = AutoIp_pick_address();
+      AutoIp_send_arp_probe(iface);
+      autoIPs[iface].arp_attempts++;
+      autoIPs[iface].response_timer = HAL_TIMER_get_ms_tick() + dRESPONSE_TIMEOUT;
+      autoIPs[iface].state = AUTOIP_ARP_RESPONSE_WAIT;
+      break;
+
+   case AUTOIP_ARP_RESPONSE_WAIT:   
+
+      if (HAL_TIMER_get_ms_tick() > autoIPs[iface].response_timer)
+      {
+         /* No arp response within the time so  */
+         /* we will verify the address  */
+         autoIPs[iface].state = AUTOIP_ARP_VERIFY_PROBE;
+         autoIPs[iface].verify_attempts = 0;
+      }
+      break;
+
+   case AUTOIP_ARP_ADDRESS_USED:
+
+      if (autoIPs[iface].arp_attempts < 10) 
+      {
+         /* try again */
+         autoIPs[iface].state = AUTOIP_ARP_PROBE;
+      }
+      else
+      {
+         autoIPs[iface].state = AUTOIP_FAILED;
+      }
+      break;
+
+      /* The address appears to be free,  */
+      /* verify still not used */
+   case AUTOIP_ARP_VERIFY_PROBE:
+
+      AutoIp_send_arp_probe(iface);
+      autoIPs[iface].verify_attempts++;
+      autoIPs[iface].response_timer = HAL_TIMER_get_ms_tick() + dVERIFY_WAIT_TIME;
+      autoIPs[iface].state = AUTOIP_ARP_VERIFY_WAIT;
+      break;
+
+   case AUTOIP_ARP_VERIFY_WAIT:   
+
+      if (HAL_TIMER_get_ms_tick() > autoIPs[iface].response_timer)
+      {
+         /* If we have verified to our satisfaction */
+         /* take the address */
+         if (autoIPs[iface].verify_attempts >= dNUMBER_OF_VERIFIES)
+         {
+            autoIPs[iface].state = AUTOIP_GOT_ADDRESS;
+            /* Lets use this address */
+            AutoIp_set_net_vars(iface);
+         }
+         else
+         {
+            /* verify again */
+            autoIPs[iface].state = AUTOIP_ARP_VERIFY_PROBE;
+         }
+      }
+      break;
+
+   case AUTOIP_FAILED:
+      break;
+
+   default:
+      break;
+   }
+}
+
+
+
+/* FUNCTION: AutoIp_arp_response()
+ * 
+ *  If an ARP Probe gets a response, the TCP/IP Stack upcalls this function.
+ *  We will have to try another address.
+ *
+ * PARAM1: PACKET pkt
+ *
+ * RETURNS: void
+ */
+
+void
+AutoIp_arp_response(struct arp_hdr * arphdr, NET ifp)
+{
+   int iface;
+
+   iface = if_netnumber(ifp);
+
+   /* Check that we are in a mode that cares about all this */
+   if (autoIPs[iface].state == AUTOIP_ARP_RESPONSE_WAIT)
+   {
+      /* Check for someone else probing this as a target address, IE their
+       * target (probed) address is that same as the one we are trying
+       */
+      if (arphdr->ar_tpa == autoIPs[iface].try_address)
+      {
+         autoIPs[iface].state = AUTOIP_ARP_ADDRESS_USED;
+         return;
+      }
+
+      /* Also check for a response from the probed address.
+       * This means some already has the address.
+       */
+      if (arphdr->ar_spa == autoIPs[iface].try_address)
+      {
+         autoIPs[iface].state = AUTOIP_ARP_ADDRESS_USED;
+         return;
+      }
+   }
+}
+
+
+
+/* FUNCTION: AutoIp_send_arp_probe()
+ * 
+ * PARAM1: interface index
+ *
+ * RETURNS: void
+ */
+
+void
+AutoIp_send_arp_probe(int iface)
+{
+   PACKET pkt;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pkt = pk_alloc(4);  /* dummy packet */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (pkt == NULL)
+      return;
+
+   nets[iface]->n_ipaddr = 0;    /* our IP address needs to be 0 */
+   pkt->net = nets[iface];
+   pkt->fhost = autoIPs[iface].try_address;
+   send_arp(pkt, autoIPs[iface].try_address);
+}
+
+
+
+/* FUNCTION: AutoIp_pick_address()
+ * 
+ *   Pick a random auto IP address. Returns the address in network
+ * endian (big), which is how the IP, ARP & DHCP modules expect them.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: random IP address
+ */
+
+ip_addr
+AutoIp_pick_address(void)
+{
+   unshort  newrand = rand_seed--;  /* bump this down since cticks goes up */
+
+   newrand ^= (unshort)(cticks + 1);
+   while(newrand > dAUTO_IP_RANGE)
+      newrand >>= 1;
+   return(htonl(dBASE_AUTO_IP_ADDRESS + newrand));
+}
+
+
+/* FUNCTION: AutoIp_get_state()
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+int
+AutoIp_get_state(int iface)
+{
+   return(autoIPs[iface].state);
+}
+
+
+/* FUNCTION: AutoIp_set_net_vars()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+void
+AutoIp_set_net_vars(int iface)
+{
+   nets[iface]->n_ipaddr = autoIPs[iface].try_address;
+   nets[iface]->snmask   = htonl(0xFFFF0000);
+   nets[iface]->n_defgw  = 0x00000000;
+
+   if ( nets[iface]->snmask == 0 )
+   {
+      fixup_subnet_mask(iface);
+      dhc_states[iface].snmask = nets[iface]->snmask; 
+   }
+
+   /* fixup broadcast addresses  */
+   nets[iface]->n_netbr    = nets[iface]->n_ipaddr | ~nets[iface]->snmask;
+   nets[iface]->n_netbr42  = nets[iface]->n_ipaddr &  nets[iface]->snmask;
+   nets[iface]->n_subnetbr = nets[iface]->n_ipaddr | ~nets[iface]->snmask;
+
+   /* print IP address acquired through AutoIP - for user's benefit */
+   printf("Acquired IP address via AutoIPv4 for interface: %s\n", nets[iface]->name); 
+   printf("IP address : %s\n", print_ipad(nets[iface]->n_ipaddr));
+   printf("Subnet Mask: %s\n", print_ipad(nets[iface]->snmask));
+   printf("Gateway    : %s\n", print_ipad(nets[iface]->n_defgw));
+}
+
+
+
+/* FUNCTION: dhc_hostname()
+ *
+ * Called from the DHCP client to get a valid hostname for this machine. This
+ * is a default routine which returns a dummy name. The porting engineer is
+ * expected to define GETHOSTNAME_ALREADY and replace this with a system
+ * routine.
+ *
+ * Note - if MUST always return a string.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: pointer to ascii hostname string
+ */
+
+#ifndef DHCHOSTNAME_ALREADY
+
+/* globally overridable hostname */
+char * system_dhcp_hostname = "dummy";
+ 
+u_char *
+dhc_hostname()
+{
+   char * hostname;
+
+#ifdef ALWAYS_HAVE_NAME
+   hostname = get_device_name();
+   if(strcmp(hostname,"") == 0)
+   {
+      hostname = get_device_always_name(); 
+   }
+#else
+   hostname = system_dhcp_hostname;
+#endif
+
+   return (u_char*)hostname;
+}
+
+#endif   /* DHCHOSTNAME_ALREADY */
+
+#endif   /* USE_AUTOIP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h
new file mode 100644
index 0000000..8826fc2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/autoip.h
@@ -0,0 +1,58 @@
+/*  AutoIP.h
+
+   AutoIP, determines IP address by ARPing a trial address
+   and waiting for responses.
+
+   9/15/2000 - Created - Stan Breitlow
+
+*/
+
+#ifndef AUTOIP_H
+#define AUTOIP_H
+
+typedef enum 
+{
+  AUTOIP_START,
+  AUTOIP_GOT_ADDRESS,
+  AUTOIP_ARP_PROBE,
+  AUTOIP_ARP_RESPONSE_WAIT,
+  AUTOIP_ARP_ADDRESS_USED,
+  AUTOIP_ARP_VERIFY_WAIT,
+  AUTOIP_ARP_VERIFY_PROBE,
+  AUTOIP_FAILED
+} eAUTO_IP_STATE;
+
+/* "methods", or vairous modes of operation for the AutoIP code */
+
+typedef enum
+{
+   eIP_METHOD_DHCP_AUTO_FIXED,   /* Try DHCP then AuoIP */
+   eIP_METHOD_DHCP_FIXED,        /* Try DHCP */
+   eIP_METHOD_AUTO_FIXED,        /* Try AutoIP */
+   eIP_METHOD_FIXED              /* Used fixed (NV) address */
+} eIP_METHOD;
+
+
+extern u_long  dBASE_AUTO_IP_ADDRESS; /* base of auto-address pool */
+extern u_long  dMAX_AUTO_IP_ADDRESS;
+#define        dAUTO_IP_RANGE    (dMAX_AUTO_IP_ADDRESS - dBASE_AUTO_IP_ADDRESS)
+
+struct autoIP
+{
+   eAUTO_IP_STATE state;
+   u_long      response_timer;
+   ip_addr     try_address;
+   unshort     arp_attempts;
+   unshort     verify_attempts;
+};
+
+extern struct autoIP autoIPs[MAXNETS];
+
+int AutoIp_init(void);
+void AutoIp_tick(int iface);
+int AutoIp_get_state(int iface);
+void AutoIp_send_arp_probe(int iface);
+ 
+#endif /* AUTOIP_H */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h
new file mode 100644
index 0000000..35f73dc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/ds_app.h
@@ -0,0 +1,75 @@
+/*
+ * FILENAME: ds_app.h
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *   Definitions for sample AutoIP database.
+ *
+*/
+
+#ifndef _DS_APP_H_
+#define _DS_APP_H_   1
+
+/* If application programmer (user) has defined his own database then
+ * include his files inside the file "user_ds.h"; otherwise support
+ * our simple default system.
+ */
+#ifdef USER_DS_SUPPORT
+#include "user_ds.h"
+#else    /* use simple local system */
+
+
+/* AutoIP database - one for each iface entry. */
+
+struct ds_struct
+{
+   /* tag_IP_ADDRESS_MODE is one of the eIP_METHOD enums.
+    * If you don't want to use the default (auto IP), then
+    * set this value to some other enum prior to calling
+    * Upnp_init()
+    */
+   unshort  tag_IP_ADDRESS_MODE;
+
+   /* the rest of these are set during the autoIP process. */
+   u_char   tag_POLLING_ENABLED;    /* boolean */
+   u_long   tag_NET_FIXED_IP;
+   u_long   tag_NET_FIXED_SUBNET;
+   u_long   tag_NET_FIXED_GATEWAY;
+   u_long   tag_NET_IP_ADDRESS;
+   u_long   tag_NET_SUBNET;
+   u_long   tag_NET_GATEWAY;
+   char     tag_IP_ADDRESS_STRING[50];
+};
+
+/* The database: */
+extern struct ds_struct ds_structs[MAXNETS];
+
+
+/* Access macros */
+
+/* get routines set a value form the database. If the database
+ * entry is zero then the value is enchanged
+ */
+
+#define  DS_get_word(tag, iface, data) \
+   { *(unshort*)(data) = (unshort)ds_structs[iface].tag; }
+
+#define  DS_get_long(tag, iface, data) \
+   { *(u_long*)(data) = ds_structs[iface].tag; }
+
+
+/* Set routines set a value in the database */
+
+#define  DS_set_long(tag, iface, data) \
+   ds_structs[iface].tag = data;
+
+#define  DS_set_byte(tag, iface, data) \
+   ds_structs[iface].tag = data;
+
+#define  DS_set_string(tag, iface, data) \
+   { strncpy(ds_structs[iface].tag, data, sizeof(ds_structs[iface].tag));}
+
+#endif /* USER_DS_SUPPORT */
+#endif /* _DS_APP_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c
new file mode 100644
index 0000000..3dcd7f4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.c
@@ -0,0 +1,651 @@
+/*
+ * FILENAME: upnp.c
+ *
+ * Copyright  2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *   Universal plug and play
+ *
+ *   This file has all the top level UPnP managment routines.
+ *   It uses: 
+ *     - DHCP client for Addressing
+ *     - AutoIP for Addressing 
+ *     - SSDP for discovery 
+ *
+ *   9/15/2000 - Created - Stan Breitlow 
+ *
+ * MODULE: AUTOIP4
+ *
+ * ROUTINES: Upnp_init(), upnp_recv_dhcp_status(), upnp_tick(), 
+ * ROUTINES: Play (), Upnp_tick(), upnp_set_fixed_net_vars(), 
+ * ROUTINES: Upnp_GetDnsOptionsFromDhcpOptions(), 
+ * ROUTINES: upnp_add_net_vars_to_database(),
+ *
+ * PORTABLE: yes
+ */
+
+
+
+#include "ipport.h"
+
+#ifdef USE_UPNP
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "dhcpclnt.h"
+#include "dns.h"
+#include "dhcpclnt.h"
+#include "intimers.h"
+
+#include "autoip.h"
+#include "upnp.h"
+#include "ds_app.h"
+
+
+#ifndef USE_AUTOIP
+#error USE_AUTOIP must be defined with USE_UPNP
+#endif
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"    /* For nvparms struct */
+#endif   /* INCLUDE_NVPARMS */
+
+
+/* local objects */
+
+struct   tUPNP upnp[MAXNETS];
+long  upnp_timer;
+int   DHCP_WAIT_TIME = 300;   /* 30 seconds default */
+
+#ifndef USER_DS_SUPPORT
+struct ds_struct ds_structs[MAXNETS];  /* database */
+#endif
+
+/* local protos */
+
+int upnp_recv_dhcp_status(int iface, int state);
+static void upnp_set_fixed_net_vars(int iface);
+static void upnp_add_net_vars_to_database(int iface);
+static void Upnp_GetDnsOptionsFromDhcpOptions(void);
+static void upnp_add_Fixed_vars_to_database(int iface);
+
+extern void fixup_subnet_mask(int);
+
+#ifdef IN_MENUS
+#include "menu.h"
+extern struct menu_op upnpmenu[5];
+#endif   /* IN_MENUS */
+
+/* default method of getting IP address */
+eIP_METHOD addressing_method = eIP_METHOD_DHCP_AUTO_FIXED; 
+
+
+/* FUNCTION: Upnp_init()
+ * 
+ *   Initialize the sub modules
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+int Upnp_init(void)
+{
+   int   i;
+   int   e;
+   struct tUPNP * up;
+
+   e = AutoIp_init();
+   if (e)
+   {
+      dtrap();
+   }
+
+   for (i = 0; i < MAXNETS; i++)
+   {
+      up = &upnp[i];
+
+      /* Disable Auto-IP on unset nets. If a dynamic interface wants this later, 
+       * the creator will have to explicitly enable it.
+       */
+      if(nets[i] == NULL)
+      {
+         up->state = UPNP_DISABLED;
+         continue;
+      }
+
+      /* Only do this on ethernets */
+      if(nets[i]->n_mib->ifType != ETHERNET)
+         continue;
+
+      /* nets[] should already have info set from NV parms system or
+       * by other means. Save this info to the "UPnP database items now.
+       */
+      upnp_add_Fixed_vars_to_database(i);    /* set fixed info */
+      upnp_add_net_vars_to_database(i);      /* set tmp info */
+
+#ifdef INCLUDE_NVPARMS
+      /* Skip interfaces which are not flagged to be DHCP clients */
+      if (inet_nvparms.ifs[i].client_dhcp) /* is DHCP Client enabled ? */
+         nets[i]->n_flags |= NF_AUTOIP;  /* yes, then use AUTOIP too */
+#endif   /* INCLUDE_NVPARMS */
+
+      if (!(nets[i]->n_flags & NF_AUTOIP))
+      {
+         up->state = UPNP_DISABLED;
+         continue;
+      }
+
+      up->state = UPNP_START;
+      up->idle_timer = 0 ;
+      up->notify_delay = 0;
+      up->notify_count = 0;
+      up->got_dhcp_address = FALSE;
+
+      dhc_set_callback(i, upnp_recv_dhcp_status );
+
+      /* Check parameter database for IP setting */
+      DS_get_word(tag_IP_ADDRESS_MODE, i, &addressing_method);
+      up->ip_method = addressing_method;
+   }
+
+#ifdef IN_MENUS
+   install_menu(&upnpmenu[0]);
+   install_version("autoip3.1");
+#endif   /* IN_MENUS */
+
+#ifdef USER_SMTP_ALERTS
+   /* If "user smtp" service is supported, do the init now. */
+   UserSmtp_init();
+#endif
+
+   /* start the AutoIP interval timer */
+   upnp_timer = in_timerset(Upnp_tick, 100, 0L );
+   if(upnp_timer == 0)
+      return -1;
+
+   return 0;
+}
+
+
+
+/* FUNCTION: upnp_recv_dhcp_status()
+ *
+ *    Callback that receives status changes from the dhcp client.
+ *
+ * PARAM1: int iface
+ * PARAM2: int state
+ *
+ * RETURNS: 
+ */
+
+int upnp_recv_dhcp_status(int iface, int state)
+{
+    struct tUPNP * up;
+
+   up = &upnp[iface];
+
+   switch (state)
+   {
+   case DHCS_UNUSED:       /* no discovery attempted  */
+   case DHCS_INIT:         /* Ready to send a DISCOVER packet  */
+   case DHCS_INITREBOOT:   /* Have IP, ready to send REQUEST(skip DISCOVER) */
+   case DHCS_REBOOTING:    /* rebooting/reclaiming address  */
+   case DHCS_SELECTING:    /* discovery sent, but no offer yet  */
+   case DHCS_REQUESTING:   /* sent request; waiting for ACK|NAK  */
+   case DHCS_RENEWING:     /* Renewing the lease  */
+   case DHCS_REBINDING:    /* rebinding to new server  */
+   case DHCS_RESTARTING:  
+      break;
+
+      /* got a ACK we liked  */
+   case DHCS_BOUND:
+      up->got_dhcp_address = TRUE;
+      dhc_main_ipset(iface, state);
+      break;
+   }
+
+   return(0);
+}
+
+
+/* FUNCTION: upnp_tick()
+ * 
+ *   Called every 100ms to run finite state machine.
+ *   Manages the Address and Discover phases of AutoIP
+ *
+ * PARAM1: void
+ *
+ * RETURNS: void
+ */
+
+u_long   last_upnptick;
+
+void
+Upnp_tick(long dummy)
+{
+   int   iface;
+   struct tUPNP * up;
+   int   timerlag;
+
+   /* if we missed a long interval, derive a value to update the timer */
+   if((cticks - last_upnptick) > (TPS/10))
+   {
+      /* approx. number of 100ms intervals we missed. The "|10"
+       * on TPS is to prevent a divide by zero if TPS < 10 .
+       */
+      timerlag = (cticks - last_upnptick)/((TPS|10)/10);
+   }
+   else
+      timerlag = 0;
+
+   last_upnptick = cticks;
+
+   for(iface = 0; iface < MAXNETS; iface++)
+   {
+      /* first blank net means we're done with loop */
+      if(nets[iface] == NULL)
+         return;
+
+      up = &upnp[iface];
+
+      if(!up)     /* iface is not doing Auot IP, skip it. */
+         continue;
+
+      /* update timers if we had a long break */
+      if(timerlag)
+         up->idle_timer += timerlag;
+
+      switch (up->state)
+      {
+
+         /*-------------------------------------------------------- */
+         /* Let things settle before starting */
+         /*-------------------------------------------------------- */
+
+      case UPNP_START:
+
+         up->state = UPNP_INIT;
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Determine where to start the sequence. */
+         /* If the device is configured to use only fixed IP */
+         /* we will skip dhcp and AutoIP */
+         /*-------------------------------------------------------- */
+
+      case UPNP_INIT:
+
+         /* Use configured IP addressing method */
+         switch (up->ip_method)
+         {
+         default:
+         case eIP_METHOD_DHCP_AUTO_FIXED:
+         case eIP_METHOD_DHCP_FIXED: 
+
+            up->state = UPNP_DHCP_SEEK; 
+            break;
+
+         case eIP_METHOD_AUTO_FIXED: 
+
+            up->state = UPNP_AUTO_IP; 
+            /* turn off dhcp, otherwise it will reset  */
+            dhc_halt(iface);
+            break;
+
+         case eIP_METHOD_FIXED: 
+
+            up->state = UPNP_FIXED_IP; 
+            /* turn off dhcp, otherwise it will reset  */
+            dhc_halt(iface);
+            break;
+         }
+         up->idle_timer = 0;
+         break;
+
+         /*-------------------------------------------------------- */
+         /* We are waiting for the dhcp server to give us an address. */
+         /* We only wait so long before timing out. */
+         /*-------------------------------------------------------- */
+
+      case UPNP_DHCP_SEEK:
+
+         if (up->got_dhcp_address)
+         {
+            up->state = UPNP_GOT_DHCP_ADDRESS; 
+            break;
+         }
+
+         /* If dhcp dos not resolve after a while */
+         /* try auto IP if it is allowed by the configuration */
+         up->idle_timer++;
+         if (up->idle_timer >= (unsigned)DHCP_WAIT_TIME)
+         {
+            /* What is the next phase */
+            if (up->ip_method == eIP_METHOD_DHCP_AUTO_FIXED)
+               up->state = UPNP_AUTO_IP;
+            else
+               up->state = UPNP_FIXED_IP;
+            /* turn off dhcp, otherwise it will reset  */
+            dhc_halt(iface);
+         }
+         break;
+
+         /*-------------------------------------------------------- */
+         /* We go to this state if the dhcp client gets an address */
+         /* Set the active IP address to the found address */
+         /*-------------------------------------------------------- */
+
+      case UPNP_GOT_DHCP_ADDRESS:
+
+         /* put info in the database */
+         upnp_add_net_vars_to_database(iface);
+         /* Start the discovery phase */
+         /*      up->state = UPNP_SSDP_NOTIFY;  */
+         Upnp_GetDnsOptionsFromDhcpOptions();
+         up->state = UPNP_STARTUP_FINISHED; 
+         break;
+
+         /*-------------------------------------------------------- */
+         /* If we did not get an address from a dhcp server */
+         /* We will try to get an IP address via AutoIP,  */
+         /* this involve ARP probing. */
+         /*-------------------------------------------------------- */
+
+      case UPNP_AUTO_IP:
+
+         AutoIp_tick(iface);
+         switch (AutoIp_get_state(iface))
+         {
+         case AUTOIP_GOT_ADDRESS:  /* put info in the database */
+            upnp_add_net_vars_to_database(iface);
+            /*up->state = UPNP_SSDP_NOTIFY;  */
+            up->state = UPNP_STARTUP_FINISHED;
+            break;
+         case AUTOIP_FAILED:
+            up->state = UPNP_FIXED_IP;    
+            break;
+         default:
+            break;
+         }
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Use a hardcoded IP address */
+         /*-------------------------------------------------------- */
+
+      case UPNP_FIXED_IP:
+         /* Get the fix IP info back from the database */
+         upnp_set_fixed_net_vars(iface);
+
+         /* If the fixed IP address is zero, take down the iface (for now) */
+         nets[iface]->n_mib->ifOperStatus = NI_DOWN;
+
+         /* put info in the database */
+         upnp_add_net_vars_to_database(iface);
+         DS_set_byte(tag_POLLING_ENABLED, iface, 1);
+
+#ifdef USER_SMTP_ALERTS
+         /* If "user smtp" service is supported, do the init now. */
+         UserSmtp_LookupStart();
+#endif
+         switch (up->ip_method)
+         {
+         case eIP_METHOD_DHCP_AUTO_FIXED:
+         case eIP_METHOD_DHCP_FIXED: 
+         default:
+            up->state = UPNP_IDLE;
+            break;
+
+            /* This one will not look for a DHCP in the future */
+         case eIP_METHOD_FIXED: 
+            up->state = UPNP_IDLE_FIXED;
+            break;
+         }
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Tell the network about ourselves. */
+         /* Do this several times 1 second apart. */
+         /* This is recommended by the UPNP spec */
+         /*-------------------------------------------------------- */
+
+      case UPNP_SSDP_NOTIFY:
+
+         /* not using ssdp currently */
+         up->state = UPNP_STARTUP_FINISHED;
+
+         /*ssdp_notify(iface); */
+         up->notify_delay = 0;
+         up->state = UPNP_SSDP_WAIT;
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Wait after advertising */
+         /*-------------------------------------------------------- */
+
+      case UPNP_SSDP_WAIT:
+
+         if (++up->notify_delay > SSDP_NOTIFY_DELAY)
+         {
+            if (++up->notify_count > SSDP_NOTIFY_COUNT) 
+               up->state = UPNP_SSDP_DISCOVER;
+            else
+               up->state = UPNP_SSDP_NOTIFY;
+         }
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Look for the other devices we need */
+         /*-------------------------------------------------------- */
+
+      case UPNP_SSDP_DISCOVER:
+
+         /* skip anything here for now */
+         up->state = UPNP_STARTUP_FINISHED;
+         break;
+
+         /*-------------------------------------------------------- */
+         /* The startup phase is complete */
+         /* Let the system know it can "do its thing" */
+         /*-------------------------------------------------------- */
+
+      case UPNP_STARTUP_FINISHED:
+
+         DS_set_byte(tag_POLLING_ENABLED, iface, 1);
+         up->state = UPNP_IDLE;
+         up->idle_timer = 0;
+#ifdef USER_SMTP_ALERTS
+         UserSmtp_LookupStart();
+#endif 
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Spin here until its time to do monitoring and checkup stuff */
+         /*-------------------------------------------------------- */
+
+      case UPNP_IDLE:
+
+         up->idle_timer++;
+         if (up->idle_timer >= CHECKUP_TIME)
+         {
+            /* don't recheck if we have a dhcp address already */
+            if (up->got_dhcp_address == FALSE)
+            {
+               up->state = UPNP_DHCP_CHECKUP;
+            }
+            /* Mark net as up so we can try again */
+            nets[iface]->n_mib->ifOperStatus = NI_UP;
+            up->idle_timer = 0;
+         }
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Here we stay as fixed IP */
+         /*-------------------------------------------------------- */
+
+      case UPNP_IDLE_FIXED:
+         break;
+
+         /*-------------------------------------------------------- */
+         /* Check for a dhcp that might have come on-line  */
+         /*-------------------------------------------------------- */
+
+      case UPNP_DHCP_CHECKUP:
+
+         /* start dhcp again */
+         dhc_state_init(iface, TRUE);
+         dhc_set_callback(iface, upnp_recv_dhcp_status );
+         up->state = UPNP_DHCP_RESEEK;
+         up->idle_timer = 0;
+         break;
+
+         /*-------------------------------------------------------- */
+         /* We are in AutoIP mode or DHCP Failed->Fixed mode */
+         /* let's looking for a dhcp server again */
+         /*-------------------------------------------------------- */
+
+      case UPNP_DHCP_RESEEK:
+
+         if (up->got_dhcp_address)
+         {
+            up->state = UPNP_GOT_DHCP_ADDRESS; 
+            break;
+         }
+
+         /* If dhcp dos not resolve after a while return to idle */
+         up->idle_timer++;
+         if (up->idle_timer >= (unsigned)DHCP_WAIT_TIME)
+         {
+            /* Nothing found, back to idle */
+            up->state = UPNP_IDLE;
+            /* turn off dhcp, otherwise it will reset  */
+            dhc_halt(iface);
+         }
+         break;
+
+      case UPNP_DISABLED:
+         break;
+
+      default:
+         dtrap();
+         break;
+      } /* switch */
+   } /* for */
+
+#ifdef USER_SMTP_ALERTS
+   UserSmtp_Tick();
+#endif
+
+   USE_ARG(dummy);
+}
+
+
+
+/* FUNCTION: upnp_set_fixed_net_vars()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+static   void
+upnp_set_fixed_net_vars(int iface)
+{
+   NET ifp;
+
+   ifp = nets[iface];
+
+   /* Get the fixed IP address info out of database */
+   DS_get_long(tag_NET_FIXED_IP, iface, &ifp->n_ipaddr);
+   DS_get_long(tag_NET_FIXED_SUBNET, iface, &ifp->snmask);
+   DS_get_long(tag_NET_FIXED_GATEWAY, iface, &ifp->n_defgw);
+
+   if ( ifp->snmask == 0 )
+   {
+      fixup_subnet_mask(iface);
+      dhc_states[iface].snmask = ifp->snmask; 
+   }
+
+   /* fixup broadcast addresses  */
+   ifp->n_netbr    = ifp->n_ipaddr | ~ifp->snmask;
+   ifp->n_netbr42  = ifp->n_ipaddr &  ifp->snmask;
+   ifp->n_subnetbr = ifp->n_ipaddr | ~ifp->snmask;
+
+}
+
+
+/* FUNCTION: Upnp_GetDnsOptionsFromDhcpOptions()
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void
+Upnp_GetDnsOptionsFromDhcpOptions(void)
+{
+#ifdef DNS_CLIENT
+   int   i;
+   int   iface;
+
+   iface = 0;
+   i=0;
+   while ((i < DHC_MAXDNSRVS) && (i < MAXDNSSERVERS))
+   {
+      dns_servers[i] = dhc_states[iface].dnsrv[i];
+      i++;
+   }
+#endif /* DNS_CLIENT */
+}
+
+
+/* FUNCTION: upnp_add_net_vars_to_database()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+static   void
+upnp_add_net_vars_to_database(int iface)
+{
+   char  buf[32];
+   NET   ifp;
+
+   ifp = nets[iface];
+
+   /* Put this info in the database */
+   DS_set_long(tag_NET_IP_ADDRESS, iface, ifp->n_ipaddr);
+   DS_set_long(tag_NET_SUBNET, iface, ifp->snmask);
+   DS_set_long(tag_NET_GATEWAY, iface, ifp->n_defgw);
+
+   sprintf(buf,"%u.%u.%u.%u\0", PUSH_IPADDR(ifp->n_ipaddr));
+   DS_set_string(tag_IP_ADDRESS_STRING, iface, buf);
+}
+
+
+/* FUNCTION: upnp_add_net_vars_to_database()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+static   void
+upnp_add_Fixed_vars_to_database(int iface)
+{
+   NET   ifp;
+
+   ifp = nets[iface];
+
+   /* Put this info in the database */
+   DS_set_long(tag_NET_FIXED_IP, iface, ifp->n_ipaddr);
+   DS_set_long(tag_NET_FIXED_SUBNET, iface, ifp->snmask);
+   DS_set_long(tag_NET_FIXED_GATEWAY, iface, ifp->n_defgw);
+}
+
+#endif /* USE_UPNP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h
new file mode 100644
index 0000000..b13d063
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnp.h
@@ -0,0 +1,61 @@
+/*  UPNP.h
+
+   Universal plug and play
+
+   9/15/2000 - Created - Stan Breitlow
+
+*/
+
+#ifndef UPNP_H
+#define UPNP_H
+
+/* How long to wait for a DHCP address */
+extern int DHCP_WAIT_TIME;
+
+
+#define  SSDP_NOTIFY_DELAY    10       /* 1  second */
+#define  SSDP_NOTIFY_COUNT    3        /* 3  times  */
+#define  SECONDS_PER_MINUTE   60
+#define  TICKS_PER_SECOND     10
+#define  CHECKUP_TIME         5*SECONDS_PER_MINUTE*TICKS_PER_SECOND  /* 5  minutes  */
+
+typedef enum
+{
+   UPNP_START,
+   UPNP_INIT,
+   UPNP_DHCP_SEEK,
+   UPNP_GOT_DHCP_ADDRESS,
+   UPNP_AUTO_IP,
+   UPNP_FIXED_IP,
+   UPNP_SSDP_NOTIFY,
+   UPNP_SSDP_WAIT,
+   UPNP_SSDP_DISCOVER,
+   UPNP_STARTUP_FINISHED,
+   UPNP_IDLE,
+   UPNP_IDLE_FIXED,
+   UPNP_DHCP_CHECKUP,
+   UPNP_DHCP_RESEEK,
+   UPNP_DISABLED
+} eUPNP_STATE;
+
+
+struct tUPNP 
+{
+    eUPNP_STATE state;
+    eIP_METHOD  ip_method;
+    int     got_dhcp_address;   /* boolean */
+    u_long  idle_timer;
+    u_long  notify_delay;
+    u_long  notify_count;
+    int     local_iface;
+};
+
+extern struct tUPNP upnp[MAXNETS];
+
+
+int   Upnp_init(void);
+void  Upnp_tick(long);
+ 
+#endif /* UPNP_H */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c
new file mode 100644
index 0000000..4f023e6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/autoip4/upnpmenu.c
@@ -0,0 +1,266 @@
+/*
+ * FILENAME: upnpmenu.c
+ *
+ * Copyright  2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *   Universal plug and play menu stats & control user interface
+ *
+ * ROUTINES: upnp_stats(), upnp_disable(), upnp_restart(), 
+ * ROUTINES: upnp_base(),
+ *
+ *
+ * MODULE: AUTOIP4
+ *
+ * ROUTINES: 
+ *
+ * PORTABLE: yes
+ */
+
+
+
+#include "ipport.h"
+
+#ifdef USE_UPNP
+#ifdef IN_MENUS
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "menu.h"
+
+#include "autoip.h"
+#include "upnp.h"
+#include "ds_app.h"
+
+/* routine in ..\ip to get NET pointer from console text */
+extern NET if_netbytext(void * pio, char * cp);
+
+/* UPnP menu routines */
+int   upnp_stats(void * pio);
+int   upnp_disable(void * pio);
+int   upnp_restart(void * pio);
+int   upnp_base(void * pio);
+int   upnp_db(void * pio);
+
+char * upnp_states[] = /* match eUPNP_STATE enums to text */
+{
+   "START",
+   "INIT",
+   "DHCP_SEEK",
+   "GOT_DHCP_ADDRESS",
+   "AUTO_IP",
+   "FIXED_IP",
+   "SSDP_NOTIFY",
+   "SSDP_WAIT",
+   "SSDP_DISCOVER",
+   "STARTUP_FINISHED",
+   "IDLE",
+   "IDLE_FIXED",
+   "DHCP_CHECKUP",
+   "DHCP_RESEEK",
+   "DISABLED",
+};
+
+
+struct menu_op upnpmenu[]  = 
+{
+   "upnp",        stooges,          "Upnp menu",
+   "upstats",     upnp_stats,       "status of UPnP Interfaces",
+   "updisable",   upnp_disable,     "disable UPnP on an interface",
+   "uprestart",   upnp_restart,     "restart UPnP process on interface",
+   "upbase",      upnp_base,        "Set new base for UPnP address pool",
+   "updbase",     upnp_db,          "Dump UPnP database for interface",
+   NULL,
+};
+
+
+
+/* FUNCTION: upnp_stats()
+ * 
+ * Basic status dump menu routine 
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK, Else ENP_ error code
+ */
+
+int
+upnp_stats(void * pio)
+{
+   int   i;
+
+   ns_printf(pio, "UPnP stats:\n");
+   
+   for(i = 0; i < MAXNETS; i++)
+   {
+      if(nets[i] == NULL)
+         break;
+      ns_printf(pio, "iface %s; state:%s; current IP:%u.%u.%u.%u\n",
+         nets[i]->name, upnp_states[upnp[i].state],
+         PUSH_IPADDR(nets[i]->n_ipaddr));
+   }
+
+   return 0;
+}
+
+
+/* FUNCTION: upnp_disable()
+ * 
+ * Menu routine to disable UPnP on a specified interface
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK, Else ENP_ error code
+ */
+
+int
+upnp_disable(void * pio)
+{
+   char *   cp;
+   NET      ifp;
+   int      iface;
+
+   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+   if(!*cp)
+   {
+      ns_printf(pio, "please enter iface to disable UPnP\n");
+      return -1;
+   }
+   ifp = if_netbytext(pio, cp);
+   if(ifp == NULL)      /* error parsing iface name/number text? */
+      return -1;
+   iface = if_netnumber(ifp);
+   upnp[iface].state = UPNP_DISABLED;
+   ns_printf(pio, "Disabled UPnP in iface %s\n", ifp->name);
+   return 0;
+}
+
+
+/* FUNCTION: upnp_restart()
+ * 
+ * Menu routine to restart the Auto-Ip process on the specified interface
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS:  0 if OK, Else ENP_ error code
+ */
+
+int
+upnp_restart(void * pio)
+{
+   char *   cp;
+   NET      ifp;
+   int      iface;
+
+   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+   if(!*cp)
+   {
+      ns_printf(pio, "please enter iface to restart UPnP\n");
+      return -1;
+   }
+   ifp = if_netbytext(pio, cp);
+   if(ifp == NULL)      /* error parsing iface name/number text? */
+      return -1;
+   iface = if_netnumber(ifp);
+
+   /* skip the DHCP step and go right to autoIP */
+   upnp[iface].state = UPNP_START;
+   upnp[iface].ip_method = eIP_METHOD_AUTO_FIXED;
+   autoIPs[iface].state = AUTOIP_START;
+   autoIPs[iface].response_timer = 0;
+   autoIPs[iface].arp_attempts = 0;
+
+   ns_printf(pio, "(re)started UPnP in iface %s\n", ifp->name);
+   return 0;
+}
+
+
+/* FUNCTION: upnp_base()
+ * 
+ * Menu routine to change the address pool used by Auto IP
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS:  0 if OK, Else ENP_ error code
+ */
+
+int
+upnp_base(void * pio)
+{
+   char *   cp;
+   u_long   newbase;
+   u_long   oldrange;
+   unsigned mask;
+
+   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+   if(!*cp)
+   {
+      ns_printf(pio, "please enter IP address for new base\n");
+      return -1;
+   }
+
+   cp = parse_ipad(&newbase, &mask, cp);
+   if(cp)
+   {
+      ns_printf(pio, "Bad IP address: %s\n", cp);
+      return -1;
+   }
+
+   oldrange = dAUTO_IP_RANGE;
+   dBASE_AUTO_IP_ADDRESS = htonl(newbase);   /* store in local endian */
+   dMAX_AUTO_IP_ADDRESS = htonl(newbase + oldrange);
+
+   ns_printf(pio, "Changed base of Auto-IP address pool to %u.%u.%u.%u\n",
+      PUSH_IPADDR(newbase) );
+
+   return 0;
+}
+
+int
+upnp_db(void * pio)
+{
+   char *   cp;
+   NET      ifp;
+   int      iface;
+   ip_addr  addr;
+   ip_addr  mask;
+   ip_addr  gateway;
+
+   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+   if(!*cp)
+   {
+      ns_printf(pio, "please enter iface for database dump\n");
+      return -1;
+   }
+   ifp = if_netbytext(pio, cp);
+   if(ifp == NULL)      /* error parsing iface name/number text? */
+      return -1;
+   iface = if_netnumber(ifp);
+
+   /* Get the fixed IP info from database into tmp vars */
+   DS_get_long(tag_NET_FIXED_IP, iface, &addr);
+   DS_get_long(tag_NET_FIXED_SUBNET, iface, &mask);
+   DS_get_long(tag_NET_FIXED_GATEWAY, iface, &gateway);
+
+   ns_printf(pio, "iface:%s; ", ifp->name);
+   ns_printf(pio, " Fixed IP: %u.%u.%u.%u", PUSH_IPADDR(addr) );
+   ns_printf(pio, "  mask:  %u.%u.%u.%u", PUSH_IPADDR(mask) );
+   ns_printf(pio, "  gateway:  %u.%u.%u.%u\n", PUSH_IPADDR(gateway) );
+
+   /* Get the current IP info from database into tmp vars */
+   DS_get_long(tag_NET_IP_ADDRESS, iface, &addr);
+   DS_get_long(tag_NET_SUBNET, iface, &mask);
+   DS_get_long(tag_NET_GATEWAY, iface, &gateway);
+
+   ns_printf(pio, "Current ip: %u.%u.%u.%u", PUSH_IPADDR(addr));
+   ns_printf(pio, "  mask:  %u.%u.%u.%u", PUSH_IPADDR(mask));
+   ns_printf(pio, "  gateway:  %u.%u.%u.%u\n", PUSH_IPADDR(gateway));
+
+   return 0;
+}
+
+
+#endif   /* IN_MENUS */
+#endif   /* USE_UPNP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c
new file mode 100644
index 0000000..f94f956
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.c
@@ -0,0 +1,2424 @@
+/*
+ * FILENAME: ftpclnt.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTPCLIENT
+ *
+ * ROUTINES: fc_check(), fc_getreply(), fc_checklogin(), 
+ * ROUTINES: fc_checkcmd(), fc_endxfer(), fc_clearf(), fc_sendmore(), 
+ * ROUTINES: fc_getmore(), fc_dataconn(), fc_killsess(), fc_connect(), 
+ * ROUTINES: fc_get(), fc_put(), fc_connopen(), fc_senduser(), fc_sendpass(), 
+ * ROUTINES: fc_sendport(), fc_sendcmd(), fc_dir(), fc_pwd(), fc_chdir(), 
+ * ROUTINES: fc_settype(), fc_quit(), fc_ready(), fc_usercmd(), 
+ * ROUTINES: fc_hashmark(), fc_state(), fc_pasv(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* ftpclnt.c Generic FTP client. This file contains the guts of the 
+ * FTP client logic. There are several entry poins for user commands, 
+ * include connect, send, and recv. These initiate a change in the 
+ * connection's state machine which is should result in the 
+ * performance of the desired task. These jobs are driven by periodic 
+ * calls to fc_check, which can be made from a super loop, or a task 
+ * which sleeps on ftp_clients == NULL. 
+ * 1/12/97 - Created. John Bartas 
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+
+#ifdef FTP_CLIENT
+#include "ftpsrv.h"
+#include "ftpclnt.h"
+
+#ifdef IP_V6
+#include "socket6.h"
+#endif   /* IP_V6 */
+
+
+/* operating parmeters which may be overwritten by application code 
+ * 1. If the FTP Client sends any FTP command, and it doesn't receive 
+ * a reply for fc_replytmo seconds, then the FTP Client connection is 
+ * closed. 
+ * 2. If the FTP Client connection has remained idle ( no 
+ * commands sent ) for fc_activity_tmo seconds, then the FTP Client 
+ * connection is closed 
+ */
+int  fc_replytmo       =  20;    /* secs of inactivity for cmd timeout */
+int  fc_connect_tmo    =  300;   /* secs of inactivity for connect timeout */
+int  fc_activity_tmo   =  1200;  /* ftp client's inactivity timeout (secs) */
+
+/* Starting port number for data transfers of ftp client */
+#define FTP_START_DATA_PORT  8000  /* Refered RFC1700 Assigned nums */
+
+static unshort fc_next_port=FTP_START_DATA_PORT ;
+
+/* The FTP client's per-port message handler */
+extern   void fc_printf(ftpc *, char *, ...);   /* per-port response printer */
+
+/* internal routines */
+int   fc_connopen(ftpc * ftpconn);  /* initiate command connection */
+int   fc_getreply(ftpc * ftpconn, int * code);  /* check for ftpconn reply */
+int   fc_dataconn(ftpc * ftpconn);  /* initiate data connection */
+int   fc_checklogin(ftpc * ftpconn);/* see if user login is complete */
+int   fc_checkcmd(ftpc * ftpconn);  /* see if last cmd is complete */
+int   fc_sendmore(ftpc * ftpconn);  /* send more data on a STOR command */
+int   fc_getmore(ftpc * ftpconn);   /* send more data on a RETR command */
+int   fc_senduser(ftpc * ftpconn);
+int   fc_sendpass(ftpc * ftpconn);
+int   fc_sendport(ftpc * ftpconn);
+int   fc_usercmd(ftpc * ftpconn, int cmdcode, char * cmdarg);
+int   fc_sendcmd(ftpc * ftpconn);
+int   fc_ready(ftpc * ftpconn);     /* test session readiness for command */
+void  fc_hashmark(ftpc * ftpconn, ulong before, unsigned added);
+void  fc_killsess(ftpc * ftpconn);  /* clean up ftpconn resources */
+void  fc_clearf(ftpc * ftpconn);    /* reset ftpconn counters */
+void  fc_endxfer(ftpc * ftpconn);   /* end data xfer */
+
+#ifdef FC_LOG
+GEN_IO ftplog =NULL;       /* By default log o/p would goto std output */
+int      log_flag=FALSE;   /* By default, logging is disabled */
+/* Text strings for logstate and cmdstate. Update this if any change
+   is done to the states */
+char *   fc_str[]=   {
+   "0",
+   "FCL_CONNECTING", /* 1 */ 
+   "FCL_CONNECTED",  /* 2 */
+   "FCL_READY",      /* 3 */
+   "FCL_SENTUSER",   /* 4 */
+   "FCL_SENTPASS",   /* 5 */
+   "FCL_LOGGEDIN",   /* 6 */
+   "FCL_PENDING",    /* 7 */
+   "FCL_CLOSING",    /* 8 */
+   "9",
+   "FCC_RECVPORT",   /* 10*/
+   "FCC_RECVOK",     /* 11*/
+   "FCC_RECVCONN",   /* 12*/
+   "FCC_RECEIVING",  /* 13*/
+   "FCC_RECVDONE",   /* 14*/
+   "15",
+   "16",
+   "17",
+   "18",
+   "19",
+   "FCC_SENDPORT",   /* 20*/
+   "FCC_SENDOK",     /* 21*/
+   "FCC_SENDCONN",   /* 22*/
+   "FCC_SENDING",    /* 23*/
+   "FCC_SENDDONE",   /* 24*/
+   "25",
+   "26",
+   "27",
+   "28",
+   "29",
+   "FCC_NLSTPORT",   /* 30*/
+   "FCC_NLSTOK",     /* 31*/
+   "FCC_NLSTCONN",   /* 32*/
+   "FCC_NLSTING",    /* 33*/
+   "FCC_NLSTDONE",   /* 34*/
+   "35"
+};
+
+#define FC_CBLOG(fc) { \
+                        if (log_flag==TRUE)                              \
+                           log_printf(ftplog,"logstate=%s,cmdstate=%s\n",\
+                              fc_str[fc->logstate],fc_str[fc->cmdstate]);                \
+                     }
+#else /* FC_LOG */
+#define  FC_CBLOG(fc)   ;
+#endif   /* FC_LOG */
+
+/* Define FC_CBACK if FC_USECALLBACK is enabled */
+
+#ifdef FC_USECALLBACK
+void  (*fc_callback)(void * fc, int logstate, int cmdstate) = NULL ;
+#define FC_CBACK(fc) {if(fc_callback) \
+                         (*fc_callback)((void *)fc,fc->logstate,fc->cmdstate);}
+#else
+#define  FC_CBACK(fc)   ;
+#endif   /* FC_USECALLBACK */
+
+/* The user application can set a callback via fc_callback to receive 
+ * information when the logstate or cmdstate changes This feature is 
+ * available only when FC_USECALLBACK in enabled in ftpclnt.h If 
+ * FC_LOG is enabled, then the change of state is also logged. If 
+ * FC_USEBCALLBACK and FC_LOG are both disabled, FC_CALLBACK will 
+ * evaluate to empty braces. 
+ */
+#define FC_CALLBACK(fc) {                                                   \
+                           FC_CBACK(fc);                                    \
+                           FC_CBLOG(fc);                                    \
+                        }
+
+/* FC_SETLOGSTATE updates the logstate of ftpcon and calls 
+ * FC_CALLBACK. Hence, if FC_CALLBACK(fc) is {}, it evaluates to a 
+ * simple C assignment and there is no extra code. 
+ */
+#define  FC_SETLOGSTATE(fc,lstate)  {  fc->logstate=lstate; FC_CALLBACK(fc);  }
+
+struct ftpc *  ftp_clients =  NULL  ;  /* support multiple client links */
+
+struct   queue    ftpcq;      /* contains messages from other tasks */
+unsigned char ftpc_msgsize [FTPC_NUM_MSGS] = {0x10, 0x0C, 0x0C, 0x0C, 0x00, 0x20, 0x0C, 0x10, 0x0C, 0x0C, 0x0C, 0x00, 0x08};
+struct ftpc_msg_stats ftpc_msg_stats;
+struct ftpc_err ftpc_err;
+extern struct ftpc *  ftp_get_con(void * pio);
+
+#define  FC_MENULOG() ;
+
+
+/* FUNCTION: fc_check()
+ * 
+ * fc_check() - poll ftp clients for work. This does not need to be 
+ * called if(ftp_clients == NULL), else it should be called 
+ * periodicly to move FTP transactions. 
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0 if there are not more conenctions open,
+ *          1 if there are connections but no IO in progress,
+ *          2 if the is at least 1 file transfer going
+ */
+
+int  
+fc_check(void)
+{
+   ftpc * ftpconn;
+   ftpc * ftpc_next;
+   int   e; /* generic error holder */
+   int   retval = 0;
+
+   /* loop through active client list */
+   for (ftpconn = ftp_clients; ftpconn; ftpconn = ftpc_next)
+   {
+      ftpc_next = ftpconn->next;
+      if (ftpconn->in_use) /* make sure we're not being re-entered */
+         continue;
+      ftpconn->in_use++;   /* set re-entry flag */
+
+      e = 0;   /* clear error before each connection */
+      switch (ftpconn->logstate)
+      {
+      case FCL_CONNECTING:
+      case FCL_CONNECTED:
+         /* see if we timed out on non-blocking connect() */
+         if ((ftpconn->last_cmd + ((unsigned long)fc_connect_tmo * TPS)) < ftp_ticks)
+         {
+            fc_printf(ftpconn,
+             "FTP Connection timed out on non-blocking connect.\n");
+            e = -1;
+         }
+         else
+         {
+            e = fc_connopen(ftpconn);  /* keep polling until state goes READY */
+         }
+         break;
+      case FCL_SENTUSER:   /* check for reply to USER or PASS cmd */
+      case FCL_SENTPASS:
+         e = fc_checklogin(ftpconn);
+         if (ftpconn->logstate == FCL_LOGGEDIN)
+            fc_printf(ftpconn, "ftp user \"%s\" logged in.\n", ftpconn->username);
+         break;
+      case FCL_READY:      /* connected & ready, but not doing login */
+         if ((ftpconn->last_cmd + ((unsigned long)fc_activity_tmo*TPS)) < ftp_ticks)
+         {
+            fc_printf(ftpconn,
+             "FTP Connection timed out : No activity for %d secs\n",
+             fc_activity_tmo);
+            e=-1;
+         }
+         break;
+      case FCL_LOGGEDIN:   /* nothing to do here */
+         if ((ftpconn->last_cmd + ((unsigned long)fc_activity_tmo*TPS)) < ftp_ticks)
+         {
+            fc_printf(ftpconn,
+             "FTP Connection timed out : No activity for %d secs\n",
+             fc_activity_tmo);
+            e=-1;
+         }
+         break;
+      case FCL_PENDING:    /* command in progress */
+         e = fc_checkcmd(ftpconn);  /* push command to next state */
+         break;
+      case FCL_CLOSING:    /* close FTP connection */
+         e = -1;     /* mark for deletion */
+         break;
+      default:
+         e = -1;     /* mark for deletion */
+         break;
+      }
+      ftpconn->in_use--;   /* clear re-entry flag */
+
+      if (ftpconn->logstate == FCL_PENDING)
+         retval = 2;       /* At least 1 connection has transaction in progress */
+
+      /* delete any terminating connections */
+      if (e)
+      {
+#ifdef FC_LOG
+         if (log_flag == TRUE)
+         {
+            ftpconn->in_use++;   /* set re-entry flag */
+            log_printf(ftplog,"Closing FTP client connection.\n");
+            ftpconn->in_use--;   /* clear re-entry flag */
+         }
+#endif
+         ftpc_next = ftpconn->next; /* maintain pointer to next */
+         fc_killsess(ftpconn);
+      }
+   }
+   if((retval == 0) && (ftp_clients))
+      retval = 1;    /* at least one connection open */
+   return retval;
+}
+
+
+
+
+/* FUNCTION: fc_getreply()
+ * 
+ * fc_getreply() - check for a reply to and outstanding command. 
+ * Performs state machine actions if reply is ready. Does not handle 
+ * timeouts. 
+ * 
+ * PARAM1: ftpc * ftpconn
+ * PARAM2: int * replycode
+ *
+ * RETURNS: Returns: 0 if we have full command, -1 if error, 1 if no 
+ * reply yet. 
+ */
+
+int
+fc_getreply(ftpc * ftpconn, int * replycode)
+{
+   int   e;    /* error holder */
+   int   current; /* cuurent cmd text length */
+   char *   beginLine;
+   char *   endLine;
+   char *   cp;
+   int   rc =  1;
+
+   current = strlen(ftpconn->cmdbuf);
+   e = t_recv(ftpconn->cmd_sock, ftpconn->cmdbuf + current, 
+    CMDBUFSIZE - current, 0);
+   if (e < 0)  /* read error ? */
+   {
+      e = t_errno(ftpconn->cmd_sock);
+      if (e == EWOULDBLOCK)
+      {
+         /* If some reply info is left in buffer from a previous read,
+          * return code to this affect
+          */
+         if(ftpconn->cmdbuf[0] == 0)
+            return 1;   /* wait some more */
+      }
+      else
+      {
+         fc_printf(ftpconn, "ftp client read error %d\n", e);
+         return -1;
+      }
+   }
+   else if (e == 0) /* socket closed by server */
+   {
+      fc_printf(ftpconn, "ftp connection closed by server\n");
+      return -1;
+   }
+
+   /* add bytes read on last t_recv() to total bytes in buffer */
+   current += e;
+   /* null terminate after length of buffer */
+   ftpconn->cmdbuf[current] = 0;
+   beginLine = ftpconn->cmdbuf;
+   for (;;)
+   {
+      /* find CRLF at end of command buffer */
+      endLine = strstr(beginLine, "\r\n");
+      /* not a complete line yet so break and return no reply yet */
+      if (!endLine)
+         break;
+
+      /* scan reply code from decimal digits at beginning of line */
+      cp = beginLine;
+      *replycode = 0;
+      while ((*cp >= '0') && (*cp <= '9'))
+      {
+         *replycode = (*replycode * 10) + *cp - '0';
+         cp++;
+      }
+
+      /* if the character following the digits is not a dash 
+       * continuation character (see section 4.2 of RFC 959) and 
+       * three digits were read
+       */
+      if ((*cp != '-') && (cp == beginLine + 3))
+      {
+         if (ftpconn->options & FCO_VERB)
+            fc_printf(ftpconn, "ftp reply: %s", ftpconn->cmdbuf);
+         if (*replycode == 421)
+         {
+            fc_printf(ftpconn, "ftp closing session per code 421\n");
+            rc = -1;
+         }
+         else
+            rc = 0;  /* command is ready */
+         break;
+      }
+      /* we didn't see a complete reply so try starting at the
+         beginning of the next line */
+      beginLine = endLine + 2;
+   }
+   return rc;
+}
+
+
+
+/* FUNCTION: fc_checklogin()
+ * 
+ * fc_checklogin() - Check for a reply to an outstanding USER or PASS 
+ * command. Handle state changes if reply has arrived, do timeouts. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK (including no reply), if error returns -1. 
+ */
+
+int
+fc_checklogin(ftpc * ftpconn)
+{
+   int   e;
+   int   replycode;
+
+   e = fc_getreply(ftpconn, &replycode);
+   if (e == 1) /* reply not ready yet */
+   {
+      /* see if we should time out waiting for reply */
+      if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks)
+      {
+         fc_printf(ftpconn, "ftp login timed out\n");
+         return -1;
+      }
+      return 0;   /* else wait some more */
+   }
+   if (e != 0) /* fatal connection error? */
+      return -1;
+
+
+   if ( replycode == 220 )
+   {
+      /* remove all 220 commands from buffer */
+      /* We have remove all lines starting with 220 from cmd buf */
+      char *   curpos, *   nextpos;
+
+      curpos=ftpconn->cmdbuf ;
+      while ( (nextpos= strstr(curpos, "\r\n")) != NULL )
+      {
+         replycode = atoi(curpos);
+         if ( replycode == 220 )   /* keep searching */
+            curpos=nextpos+2;  
+         else 
+            break;
+      }
+      /* if there were any 220 commands */
+      if (curpos != ftpconn->cmdbuf)
+      {
+         int   reply_220_len; /* length of 220 commands */
+         int   remainder_len; /* length of remainder of command buffer */
+
+         /* compute length of 220 commands and length of remainder of
+            command buffer */
+         reply_220_len = curpos - ftpconn->cmdbuf;
+         remainder_len = sizeof(ftpconn->cmdbuf) - reply_220_len;
+
+         /* move the remainder of the command buffer to the front */
+         MEMMOVE(ftpconn->cmdbuf,curpos,remainder_len);
+         /* zero out the number of bytes removed at the tail end of buf */
+         MEMSET(ftpconn->cmdbuf + remainder_len,0,reply_220_len);
+      }
+   }
+
+   /* we have complete reply in ftpconn->cmdbuf */
+   if (replycode > 399 || replycode < 200) 
+   {
+      fc_printf(ftpconn, "User login failed, error.\n");
+      FC_SETLOGSTATE(ftpconn,FCL_READY);  /* not logged in */
+      return -1;
+   }
+
+   if (replycode < 230) /* ignore 220, 226, et.al. */
+   {
+      return 0;
+   }
+
+   /* code is now in range 230 - 399 */
+   switch (ftpconn->logstate)
+   {
+   case FCL_SENTUSER:   /* got reply to USER cmd */
+      if (replycode >= 300 && replycode < 399)  /* need password */
+      {
+         e = fc_sendpass(ftpconn);  /* send password */
+         if (e)
+            return e;
+      }
+      else
+         FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); 
+      break;      
+   case FCL_SENTPASS:   /* got reply to PASS cmd */
+      FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); 
+      break;
+   }
+   return 0;
+}
+
+
+
+
+/* FUNCTION: fc_checkcmd()
+ * 
+ * fc_checkcmd() - check for a reply to and outstanding command. 
+ * Performs state machine actions if reply is ready. Also does 
+ * timeouts. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, if error returns -1. 
+ */
+
+int
+fc_checkcmd(ftpc * ftpconn)
+{
+   int   e;
+   int   replycode;
+   char* cp;
+
+   /* if waiting for connect or doing data IO, just keep doing it */
+   switch (ftpconn->cmdstate)
+   {
+   case FCC_SENDING:
+      e = fc_sendmore(ftpconn);
+      return e;
+   case FCC_RECEIVING:
+   case FCC_NLSTING:
+      e = fc_getmore(ftpconn);
+      return e;
+   case FCC_SENDCONN:   /* we are trying to connect... */
+   case FCC_RECVCONN:
+   case FCC_NLSTCONN:
+      e = fc_dataconn(ftpconn);  /* poll data connect */
+      if (e == 1) /* data port connected? */
+      {
+         ftpconn->cmdstate++; /* go listen for result */
+         FC_CALLBACK(ftpconn);
+         e = 0;   /* definitely not an error */
+         /* If cmdstate is FCC_NLSTING or FCC_RECEIVING, 
+          * or FCC_SENDING display the message
+          */
+         if (ftpconn->cmdstate == FCC_SENDING)
+            fc_printf(ftpconn, "sending file... cticks = %lu\n", cticks);
+         else   /* FCC_NLSTING or FCC_RECEIVING */
+            fc_printf(ftpconn, "receiving file...\n");
+      }
+      else
+      {
+         /* see if we should time out waiting for connect */
+         if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks)
+         {
+            fc_printf(ftpconn, "ftp command timed out\n");
+            return -1;
+         }
+      }
+      return e;
+   }
+
+   /* fall to here if expecting a command reply */
+   e = fc_getreply(ftpconn, &replycode);
+   if (e == 1) /* reply not ready yet */
+   {
+      /* see if we should time out waiting for reply */
+      if ((ftpconn->last_cmd + ((unsigned long)fc_replytmo*TPS)) < ftp_ticks)
+      {
+         fc_printf(ftpconn, "ftp command timed out\n");
+         return -1;
+      }
+      else
+      {
+         return 0;   /* else wait some more */
+      }
+   }
+   else if (e != 0)  /* fatal connection error? */
+   {
+      return -1;
+   }
+   else     /* e=0 */
+   {
+      if (strstr(ftpconn->cmdbuf, "\r\n") == NULL)
+         return 0;
+   }
+
+
+   /* fall to here if we got whole reply */
+   e = 0;      /* clear error holder prior to case statement */
+   switch (ftpconn->cmdstate)
+   {
+   case FCC_SENDPORT:
+   case FCC_RECVPORT:
+   case FCC_NLSTPORT:
+      if (replycode < 200 || replycode > 299)   /* OK code? */
+      {
+         fc_printf(ftpconn, "ftp port command error %s\n", ftpconn->cmdbuf);
+         FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); 
+         break;   /* this is not fatal to command connection */
+      }
+      ftpconn->cmdstate++; /* bump to actual IO command */
+      FC_CALLBACK(ftpconn);
+      e = fc_usercmd(ftpconn, ftpconn->cmdstate, NULL);  /* send cmd */
+      break;
+   case FCC_SENDOK:
+   case FCC_RECVOK:
+   case FCC_NLSTOK:
+      if ((replycode == 150) || (replycode == 125))
+      {
+         ftpconn->cmdstate++; /* next state is handle actual connect */
+         FC_CALLBACK(ftpconn);
+      }
+      else  /* not a 150 code, clean up data conn */
+      {
+         fc_endxfer(ftpconn); /* kill data connection */
+         FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN);  /* back to base state */
+         e = 0;   /* don't kill command connection */
+      }
+      break;
+   case FCC_RECVDONE:   /* closing receive data connection */
+   case FCC_NLSTDONE:
+      fc_endxfer(ftpconn); /* cleanup resources */
+      /* fall to logstate logic */
+   case FCC_SENDDONE:   /* done with file send, awaiting reply */
+      FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN);  /* back to base state */
+      break;
+   case FCC_TYPE:
+      if (replycode == 200)
+         ftpconn->mode = ftpconn->newmode;
+      else
+         fc_printf(ftpconn, "type cmd failed\n");
+      FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN);  /* go back to idle state */
+      break;
+   case FCC_CWD:  /* get reply to Change Working Directory cmd */
+   case FCC_PWD:  /* get reply to Print Working Directory cmd */
+      if (replycode < 200 || replycode > 299)   /* check reply code */
+         fc_printf(ftpconn, "path error: %s", &ftpconn->cmdbuf[5]);
+      else     /* good reply, display to user */
+         fc_printf(ftpconn, "ftp: %s", &ftpconn->cmdbuf[4]);
+      FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN);  /* go back to idle state */
+      break;
+   case FCC_QUIT: /* get reply to QUIT command */
+      if (replycode < 200 || replycode > 299)   /* check reply code */
+         fc_printf(ftpconn, "quit error: %s", &ftpconn->cmdbuf[5]);
+      else     /* good reply, display to user */
+         fc_printf(ftpconn, "ftp: %s", &ftpconn->cmdbuf[4]);
+      FC_SETLOGSTATE(ftpconn,FCL_CLOSING);   /* go ahead and close conn */
+      break;
+      default:
+      dtrap(); /* bad case? */
+      e = -1;
+   }
+
+   /* Flush current command from cmdbuf */
+   cp = strstr(ftpconn->cmdbuf, "\r\n");    /* find end of command */
+   if((cp == NULL) || (*(cp + 2) == 0))
+   {
+      ftpconn->cmdbuf[0] = 0;    /* invalidate whole buffer */
+   }
+   else  /* there was another command in the buffer */
+   {
+      cp += 2;    /* point to next cmd (past CR/LF) */
+      MEMMOVE(ftpconn->cmdbuf, cp, strlen(cp) + 1);   /* move up next cmd */
+   }
+   return e;
+}
+
+/* FUNCTION: fc_showspeed()
+ * 
+ * show speed parameters of current transfer. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+void
+fc_showspeed(ftpc * ftpconn)
+{
+   unsigned secs;
+   u_long   ticks;
+   char *   oper;
+
+   switch (ftpconn->cmdstate)    /* set operation string */
+   {
+      case FCC_SENDING:
+      case FCC_SENDDONE:
+         oper = "Sent";     
+         break;
+      case FCC_RECEIVING:
+      case FCC_RECVDONE:
+         oper = "Received"; 
+         break;
+      case FCC_NLSTING:
+      case FCC_NLSTDONE:
+         oper = "Listed";   
+         break;
+      default:
+         return;
+   }
+
+   ticks = ftp_ticks - ftpconn->last_data;
+   secs = (unsigned)(ticks/TPS);
+   fc_printf(ftpconn, "%s %lu bytes in %d seconds (cticks = %lu)\n",
+      oper, ftpconn->datadone, secs, cticks);
+   /* show speed if samples are big enough */
+   if (secs > 0 && ftpconn->datadone > 1024)
+   {
+      fc_printf(ftpconn, "speed: %ld.%ld KB/s\n", 
+         (ftpconn->datadone/secs)/1024L,
+         (ftpconn->datadone/secs)%1024L );
+   }
+}
+
+/* FUNCTION: fc_endxfer()
+ * 
+ * fc_endxfer(ftpconn) - housekepping routine to clean up after a 
+ * data transfer. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+void
+fc_endxfer(ftpc * ftpconn)
+{
+   /* close file if open */
+   if (ftpconn->fp)
+      vfclose(ftpconn->fp);
+   ftpconn->fp = NULL;
+
+   /* close data socket if open */
+   if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL)
+      t_socketclose(ftpconn->data_sock);
+   ftpconn->data_sock = SYS_SOCKETNULL;
+
+   /* printf messages as required */
+   if (ftpconn->options & FCO_VERB)
+   {
+      fc_showspeed(ftpconn);
+   }
+
+   FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN); 
+   /* reset data transfer state variables */
+   fc_clearf(ftpconn);
+}
+
+
+
+/* FUNCTION: fc_clearf()
+ * 
+ * fc_clearf(ftpconn) - housekepping routine to set all file transfer 
+ * counters to zero. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+void
+fc_clearf(ftpc * ftpconn)
+{
+   /* clean up ftpconn counters, etc. */
+   ftpconn->datact = 0; /* clear count */
+   ftpconn->offset = 0; /* clear offset */
+   ftpconn->datadone = 0L;
+   ftpconn->filesize = 0L;
+   ftpconn->last_cmd = ftp_ticks; /* update last_cmd */
+}
+
+
+
+/* FUNCTION: fc_sendmore()
+ * 
+ * fc_XXXXmore() - called to drive file transfers. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Both return 0 if OK, if error returns -1. 
+ */
+
+int
+fc_sendmore(ftpc * ftpconn)
+{
+   int   e;
+
+   /* see if we need to read in buffer */
+   if (ftpconn->datact == 0)
+   {
+      ftpconn->offset = 0; /* reset databuf index */
+      ftpconn->datact = vfread(ftpconn->databuf, 1, FILEBUFSIZE, ftpconn->fp);
+      if (ftpconn->datact <= 0)  /* end of file? */
+      {
+         ftpconn->cmdstate = FCC_SENDDONE;   /* move to await reply? */
+         FC_CALLBACK(ftpconn);
+         fc_endxfer(ftpconn);    /* close data connection , etc. */
+         /* At this point we expect to receive the cmd "226 Transfer 
+          * complete at connection for <filename>" from the peer. 
+          * Hence the logstate should be FCL_PENDING. 
+          */
+         FC_SETLOGSTATE(ftpconn,FCL_PENDING); 
+         return 0;
+      }
+   }
+   e = t_send(ftpconn->data_sock, &ftpconn->databuf[ftpconn->offset],
+    ftpconn->datact, 0);
+   if (e <= 0)
+   {
+      e = t_errno(ftpconn->data_sock);
+      if((e == EWOULDBLOCK) ||
+         (e == ENOBUFS))
+      {
+         return 0;   /* Transient error, try again later */
+      }
+      else
+      {
+         fc_printf(ftpconn, "ftp data send error %d\n", e);
+         return -1;
+      }
+   }
+
+   /* fall to here if we sent data. Consider this command activity */
+   ftpconn->last_cmd = ftp_ticks;
+
+   /* do hash mark printfing */
+   if (ftpconn->options & FCO_HASH)
+      fc_hashmark(ftpconn, ftpconn->datadone, (unsigned)e);
+
+   ftpconn->offset += e;
+   ftpconn->datadone += (long)e;
+   ftpconn->datact -= e;
+   return 0;   
+}
+
+#define  FTPC_MAX_PRINTF_LEN  80
+
+
+
+/* FUNCTION: fc_getmore()
+ * 
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+int
+fc_getmore(ftpc * ftpconn)
+{
+   int   e;
+   int   read_size;
+
+   /* we will usually try to read a whole buffer full */
+   read_size = FILEBUFSIZE;
+   /* but if its for a list command, we read 1 byte less so that we 
+    * got room to null terminate what we've read so we can pass it to 
+    * fc_printf()
+    */
+   if (ftpconn->cmdstate == FCC_NLSTING)
+      read_size--;
+
+   e = t_recv(ftpconn->data_sock, ftpconn->databuf, read_size, 0);
+   if (e < 0)  /* socket error */
+   {
+      e = t_errno(ftpconn->data_sock);
+      if (e == EWOULDBLOCK)
+         return 0;   /* no data ready try again later */
+      fc_printf(ftpconn, "ftp data socket error %d\n", e);
+      return -1;
+   }
+   else if (e == 0)   /* server closed connection */
+   {
+      /* this is a normal transfer termination */
+      if (ftpconn->options & FCO_VERB)
+         fc_printf(ftpconn, "ftp server closed data connection\n");
+
+#if 0
+      /* close data socket if open */
+      if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL)
+         t_socketclose(ftpconn->data_sock);
+      ftpconn->data_sock = SYS_SOCKETNULL;
+#endif
+
+      ftpconn->cmdstate++; /* move to shutdown state */
+      FC_CALLBACK(ftpconn);
+      return 0;
+   }
+   else  /* e is positive byte count */
+   {
+      /* got data - consider this a command activity */
+      ftpconn->last_cmd = ftp_ticks;
+      ftpconn->offset = 0;       /* update data pointer & count */
+      ftpconn->datact = e;
+   }
+
+   if (ftpconn->cmdstate == FCC_NLSTING)
+   {
+      /* our homegrown version of printf() limits field sizes to 
+       * something like 132 bytes. this loop feeds the LIST output 
+       * to printf() 80 chars at a time so as not to exceed this limit
+       */
+      char *   cp;
+      char  c;
+      int   len;
+
+      /* null terminate the string so printf will handle it right */
+      ftpconn->databuf[e] = 0;
+      cp = ftpconn->databuf;
+      len = e;
+
+      /* while there's more than 80 chars left to printf */
+      while (len > FTPC_MAX_PRINTF_LEN)
+      {
+         /* save the 80th char in so we can restore it below */
+         c = *(cp + FTPC_MAX_PRINTF_LEN);
+         /* overwrite the 80th char with a null so printf will do
+            the right thing */
+         *(cp + FTPC_MAX_PRINTF_LEN) = 0;
+
+         /* print the 80 bytes */
+         fc_printf(ftpconn, "%s", cp);
+
+         /* put the overwritten byte back */
+         *(cp + FTPC_MAX_PRINTF_LEN) = c;
+         len -= FTPC_MAX_PRINTF_LEN;
+         cp += FTPC_MAX_PRINTF_LEN;
+      }
+
+      fc_printf(ftpconn, "%s", cp);
+      ftpconn->datadone += ftpconn->datact;
+      return 0;
+   }
+
+   e = vfwrite(ftpconn->databuf, 1, ftpconn->datact, ftpconn->fp);
+   if (e != (int)ftpconn->datact)
+   {
+      fc_printf(ftpconn, "ftp file write error\n");
+      return -1;
+   }
+   /* do hash mark printfing */
+   if (ftpconn->options & FCO_HASH)
+      fc_hashmark(ftpconn, ftpconn->datadone, ftpconn->datact);
+   ftpconn->datadone += (long)ftpconn->datact;
+   ftpconn->datact = 0;;
+   return 0;
+}
+
+
+
+
+/* FUNCTION: fc_dataconn()
+ * 
+ * fc_dataconn() - Initiate or check open of a data connection. If 
+ * ftpconn->data_sock is nonzero, this creates a socket and starts 
+ * the non-blocking connect, else it calls connect to see if 
+ * connection has completed. If connection completes 
+ * ftpconn->cmdstate is incremented. This handles both active and 
+ * passive opens, based on the FCP_PASV bit int ftpconn->options. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns -1 if error detected, 1 if we're now connected, 
+ * 0 if still * waiting. 
+ */
+
+int
+fc_dataconn(ftpc * ftpconn)
+{
+   int   e;
+   SOCKTYPE sock = SYS_SOCKETNULL;
+   struct sockaddr   ftpsin;  /* generic, will be cast to v4 or v6 format */
+   int      sinsize;          /* size of ftpsin after domain selection */
+
+   switch (ftpconn->domain)
+   {
+#ifdef IP_V4
+      case AF_INET:
+      {
+         struct sockaddr_in * ftpsin4;
+         /* fill in connect parameters for v4 connection */
+         sinsize = sizeof(struct sockaddr_in);
+         ftpsin4 = (struct sockaddr_in *)&ftpsin;
+         ftpsin4->sin_family = AF_INET;
+         ftpsin4->sin_addr.s_addr = ftpconn->fhost;
+         break;
+      }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      case AF_INET6:
+      {
+         struct sockaddr_in6 * ftpsin6;
+         /* fill in connect parameters for v6 connection */
+         sinsize = sizeof(struct sockaddr_in6);
+         ftpsin6 = (struct sockaddr_in6 *)&ftpsin;
+         ftpsin6->sin6_family = AF_INET;
+         IP6CPY(&ftpsin6->sin6_addr, &ftpconn->ip6_fhost);
+         break;
+      }
+#endif   /* IP_V4 */
+      default:
+         dtrap();    /* no domain setting */
+         return -1;
+   }
+
+   /* see if there is already a connection in progress */
+   if (ftpconn->data_sock && ftpconn->data_sock != SYS_SOCKETNULL)
+   {
+      /* see if we are listening (passive) or connecting (active) */
+      if ((ftpconn->options & FCO_PASV)==0)  /* server not passive, try accept */
+      {
+         sock = t_accept(ftpconn->data_sock, &ftpsin, &sinsize);
+         if (sock == SYS_SOCKETNULL)
+         {
+            e = t_errno(ftpconn->data_sock);
+            if (e == EWOULDBLOCK)
+               return 0;   /* normal return for waiting opens */
+            fc_printf(ftpconn, "ftp: error %d on listening socket\n", e);
+            return -1;
+         }
+         else  /* accept worked, we are connected */
+         {
+            t_socketclose(ftpconn->data_sock);  /* close listen socket */
+            ftpconn->data_sock = sock; /* install accepted data socket */
+
+            return 1;   /* return "connected" code */
+         }
+      }
+      else  /* server passive, we must poll active connect */
+      {
+         e = t_connect(sock, &ftpsin, sinsize);
+         if (e == 0)    /* connection completed OK */
+         {
+            ftpconn->cmdstate++; /* bump command to next state */
+            FC_CALLBACK(ftpconn);
+#ifdef IP_V4
+            if(ftpconn->domain == AF_INET)
+               ftpconn->dport = htons(((struct sockaddr_in *)(&ftpsin))->sin_port);
+#endif   /* IP_V4 */
+#ifdef IP_V6
+            if(ftpconn->domain == AF_INET6)
+               ftpconn->dport = htons(((struct sockaddr_in6*)(&ftpsin))->sin6_port);
+#endif   /* IP_V6 */
+            return 1;
+         }
+         e = t_errno(sock);   /* get socket error */
+         if (e == EINPROGRESS)   /* still connecting */
+            return 0;   /* normal return for PASV SENDCONN & RECVCONN */
+         fc_printf(ftpconn, "ftp: error %d open data connection\n", e);
+         return -1;
+      }
+   }
+
+   /* see if we should be listening or connecting */
+   if ((ftpconn->options & FCO_PASV)==0)  /* server not passive, do listen */
+   {
+      /* start TCP listen on data port, passing parms in local endian */
+
+      ftpconn->dport= fc_next_port;    /* Use a unique data port */
+
+      fc_next_port++;
+      if ( fc_next_port < FTP_START_DATA_PORT ) /* wraparound occurd ? */
+         fc_next_port = FTP_START_DATA_PORT ;
+
+      sock = t_tcplisten((u_short*)&ftpconn->dport, ftpconn->domain);
+
+      if (sock == SYS_SOCKETNULL)
+      {
+         e = t_errno(ftpconn->data_sock);
+         fc_printf(ftpconn, "ftp client data port list failed, error %d\n", e);
+         return -1;
+      }
+   }
+   else  /* server is passive, initiate connection */
+   {
+      sock = t_socket(ftpconn->domain, SOCK_STREAM, 0);
+      if (sock == SYS_SOCKETNULL)
+         return -1;  /* fatal, kill command connection */
+
+      /* make non-blocking connect call */
+      t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+      e = t_connect(sock, &ftpsin, sinsize);
+      if (e != 0)
+      {
+         e = t_errno(sock);   /* get socket error */
+         if (e != EINPROGRESS)   /* still connecting */
+         {
+            fc_printf(ftpconn, "ftp: error %d open data connection\n", e);
+            return -1;
+         }
+      }
+   }
+   /* update state variables */
+   ftpconn->last_cmd = ftp_ticks;
+   ftpconn->last_data = ftp_ticks;
+   ftpconn->data_sock = sock;
+   ftpconn->cmdstate++;
+   FC_CALLBACK(ftpconn);
+   return 0;
+}
+
+
+
+
+/* FUNCTION: fc_killsess()
+ * 
+ * fc_killsess() - the "destructor" for an ftp client session struct
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+void
+fc_killsess(ftpc * ftpconn)
+{
+   ftpc * ftpnext;
+   ftpc * ftplast;
+
+   if (ftpconn->cmd_sock && ftpconn->cmd_sock != INVALID_SOCKET)
+      t_socketclose(ftpconn->cmd_sock);
+   ftpconn->cmd_sock = INVALID_SOCKET;
+   if (ftpconn->data_sock && ftpconn->data_sock != INVALID_SOCKET)
+      t_socketclose(ftpconn->data_sock);
+   ftpconn->data_sock = INVALID_SOCKET;
+   if (ftpconn->fp)
+      vfclose(ftpconn->fp);
+
+   /* search ftp client list for ftpconn so we can unlink it */
+   ftpnext = ftp_clients;
+   ftplast = NULL;
+   while (ftpnext)
+   {
+      if (ftpnext == ftpconn) /* found connection to delete */
+      {
+         if (ftplast)   /* not at head of queue */
+            ftplast->next = ftpconn->next;   /* unlink */
+         else  /* it's head of queue */
+            ftp_clients = ftpconn->next;
+         break;
+      }
+      ftplast = ftpnext;
+      ftpnext = ftpnext->next;
+   }
+#ifdef NPDEBUG
+   if (!ftpnext)  /* not found in list ? */
+   {  dtrap(); }
+#endif
+   FTPC_FREE(ftpconn);  /* free structure memory */
+}
+
+
+
+/* FUNCTION: fc_connect()
+ *
+ * fc_connect() - initiate connect to an FTP server. If user name is 
+ * not passed, connection will be made, but no login will occur. If 
+ * username in given, password must be passed also if the server will 
+ * require it. Note that many BSD derived servers ask for the 
+ * password even if the UNIX user does not have one in his passwd 
+ * file.
+ *
+ *    this first parameter is a pointer to a binary IP address. This
+ * is 4 bytes long if the domain parameter is AF_INET, and 16 bytes
+ * long if AF_INET6.
+ *
+ * PARAM1: ip_addr fhost   -  ftp server to contact
+ * PARAM2: char * user     - user & passwd to log in with
+ * PARAM3: char * passwd
+ * PARAM4: void * pio
+ * PARAM5: int domain      - AF_INET or AF_INET6
+ *
+ * RETURNS: Returns NULL if error, else an ftpc structure. 
+ */
+
+ftpc *
+fc_connect(void * ipaddr,
+   char *   user,       /* user name */
+   char *   passwd,     /* optional password, may be NULL or "" */
+   void *   pio,        /* Handle to output device (for messages) */
+   int      domain)     /* AF_INET or AF_INET6 */
+{
+   ftpc * ftpconn;
+   int   e;
+
+   /* create connection structure */   
+   ftpconn = FTPC_ALLOC(sizeof(ftpc));
+   if (ftpconn == NULL)
+   {
+      fc_printf(NULL, "alloc failed\n");
+      return NULL;
+   }
+
+   /* fill in connection structure */
+   FC_SETLOGSTATE(ftpconn,0); 
+   ftpconn->mode = FTPTYPE_ASCII;
+   ftpconn->domain = domain;
+
+   /* make a copy of the passed FTP server IP address */
+   switch(domain)
+   {
+#ifdef IP_V4
+      case AF_INET:
+         /* IPv4 Host is passed in net endian */
+         ftpconn->fhost = *(ip_addr *)ipaddr;
+         break;
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      case AF_INET6:
+         IP6CPY(&ftpconn->ip6_fhost, (ip6_addr *)ipaddr);
+         break;
+#endif   /* IP_V6 */
+      default:
+         dtrap();
+         return NULL;
+   }
+
+   /* if user & pw passed, copy them; else leave as 0s */
+   if (user)
+      MEMCPY(ftpconn->username, user, FTPMAXUSERNAME);
+   if (passwd)
+      MEMCPY(ftpconn->password, passwd, FTPMAXUSERPASS);
+   ftpconn->next = ftp_clients;     /* link at front of list */
+   ftp_clients = ftpconn;
+
+#ifdef NPDEBUG
+   ftpconn->options |= FCO_VERB; /* turn on verbose for debug builds */
+#endif
+
+   ftpconn->pio = pio;
+
+   /* start the connection request */
+   e = fc_connopen(ftpconn);
+   if (e)
+   {
+      fc_printf(NULL, "connect error %d\n", e);
+      fc_killsess(ftpconn);
+      return NULL;
+   }
+   SignalFtpClient();       /* wake client maintainance task */
+   return ftpconn;
+}
+
+
+
+/* FUNCTION: fc_get()
+ * 
+ * fc_get() - Start the RETR of a file from the ftp server to the 
+ * local file system. 
+ *
+ * PARAM1: ftpc * fc
+ * PARAM2: char * sname
+ * PARAM3: char * dname
+ *
+ * RETURNS: Returns 0 if OK, else negtive error code 
+ */
+
+int 
+fc_get(ftpc * fc, char * sname, char * dname)
+{
+   int   e;
+   char *   mode;
+
+   /* make sure session is conencted and ready */
+   if (fc->logstate != FCL_LOGGEDIN)
+      return -1;
+
+   if (fc->mode == FTPTYPE_ASCII)
+      mode = "wt";   /* ANSI translated mode */
+   else
+      mode = "wb";   /* ANSI binary mode */
+
+   /* open emtpy file for receive */
+   fc->fp = vfopen(dname, mode);    /* check mode later */
+   if (fc->fp == NULL)
+   {
+      fc_printf(fc, "Unable to open local file %s\n", dname);
+      return -1;
+   }
+
+   MEMCPY(fc->ffilename, sname, sizeof(fc->ffilename));
+   FC_SETLOGSTATE(fc,FCL_PENDING); 
+
+   if ((fc->options & FCO_PASV)==0) /* server not passive */
+   {
+      e = fc_dataconn(fc);    /* this will start our listen */
+      if (e) return e;
+         }
+
+   fc->cmdstate = FCC_RECVPORT;
+   FC_SETLOGSTATE(fc,FCL_PENDING);  /* Maybe this is redundant */
+   e = fc_sendport(fc);
+   return e;
+}
+
+
+
+/* FUNCTION: fc_put()
+ * 
+ * fc_put() - Start the STOR of a local file to the ftp server. 
+ *
+ * PARAM1: ftpc * fc
+ * PARAM2: char * sname
+ * PARAM3: char * dname
+ *
+ * RETURNS: Returns 0 if OK, else negtive error code 
+ */
+
+int
+fc_put(ftpc * fc, char * sname, char * dname)
+{
+   int   e;
+   char *   mode;
+
+   /* make sure session is connected and ready */
+   if (fc->logstate != FCL_LOGGEDIN)
+      return -1;
+
+   /* open local file for send */
+   if (fc->mode == FTPTYPE_ASCII)
+      mode = "rt";   /* ANSI translated mode */
+   else
+      mode = "rb";   /* ANSI binary mode */
+
+   fc->fp = vfopen(sname, mode);
+   if (fc->fp == NULL)
+   {
+      fc_printf(fc, "Unable to open local file %s\n", sname);
+      return -1;
+   }
+
+   MEMCPY(fc->ffilename, dname, sizeof(fc->ffilename));
+   FC_SETLOGSTATE(fc,FCL_PENDING); 
+
+   if ((fc->options & FCO_PASV)==0) /* server not passive */
+   {
+      e = fc_dataconn(fc);    /* this will start our listen */
+      if (e) return e;
+   }
+
+   fc->cmdstate = FCC_SENDPORT;
+   FC_SETLOGSTATE(fc,FCL_PENDING); 
+   e = fc_sendport(fc);
+   return e;
+}
+
+
+
+
+/* FUNCTION: fc_connopen()
+ * 
+ * fc_connopen() - TCP active open routine. Provided so FTP client 
+ * et.al. can open an active TCP connection without blocking in TCP. 
+ * All parameters are passed in network endian. When calling for the 
+ * first time, ftpconn->fhost and ftpconn->dport should be set and 
+ * ftpconn->cmdstate should be 0. To poll for connection ready, 
+ * ftpconn->cmdstate is set to the value returned from the first call 
+ * and all other settings are ignored. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, -1 if error detected. 
+ */
+
+int 
+fc_connopen(ftpc * ftpconn)
+{
+   int      e;
+   SOCKTYPE sock;
+   struct sockaddr ftpsin;    /* cast as sockaddr_in or sockaddr_in6 */
+   int      sinsize;          /* size of ftpsin cast */
+   int      replycode;
+
+   if (ftpconn->logstate == FCL_CONNECTED)   /* connected but not ready */
+   {
+      e = fc_getreply(ftpconn, &replycode);
+      if (e == -1) return -1; /* return if error */
+         if (e == 1) return 0;   /* return if not ready yet */
+         /* fall to here if we have an FTP message after socket open */
+      if (replycode == 220)   /* got "ready" code? */
+      {
+         FC_SETLOGSTATE(ftpconn,FCL_READY);  /* ready to send USER cmd */
+         if (ftpconn->username[0])
+            return(fc_senduser(ftpconn));
+         else
+            return 0;
+      }
+      else  /* got code other than "ready" - this is bad. */
+      {
+         fc_printf(ftpconn, "connect failed; %s\n", ftpconn->cmdbuf);
+         return -1;     /* kill off client session */
+      }
+   }
+
+   switch (ftpconn->domain)
+   {
+#ifdef IP_V4
+      case AF_INET:
+      {
+         struct sockaddr_in * ftpsin4;
+         /* fill in connect parameters for v4 connection */
+         sinsize = sizeof(struct sockaddr_in);
+         ftpsin4 = (struct sockaddr_in *)&ftpsin;
+         ftpsin4->sin_family = AF_INET;
+         ftpsin4->sin_addr.s_addr = ftpconn->fhost;
+         ftpsin4->sin_port = htons(FTP_PORT);
+         break;
+      }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      case AF_INET6:
+      {
+         struct sockaddr_in6 * ftpsin6;
+         /* fill in connect parameters for v6 connection */
+         sinsize = sizeof(struct sockaddr_in6);
+         ftpsin6 = (struct sockaddr_in6 *)&ftpsin;
+         ftpsin6->sin6_family = AF_INET6;
+         ftpsin6->sin6_port = htons(FTP_PORT);
+         IP6CPY(&ftpsin6->sin6_addr, &ftpconn->ip6_fhost);
+         break;
+      }
+#endif   /* IP_V6 */
+      default:
+         dtrap();    /* no domain setting */
+         return -1;
+   }
+
+
+   /* if this client session already has a socket, see if it's connected */
+   if (ftpconn->logstate == FCL_CONNECTING)
+   {
+      /* poll t_connect() for complete */
+      e = t_connect(ftpconn->cmd_sock, &ftpsin, sinsize);
+      if (e)
+         e = t_errno(ftpconn->cmd_sock);
+      if (e == 0 || e == EISCONN)   /* socket connected to server OK */
+      {
+         FC_SETLOGSTATE(ftpconn,FCL_CONNECTED); 
+         return 0;
+      }
+      /* else handle connect error */
+      if (e == EINPROGRESS)   /* connect still in progress? */
+         return 0;   /* wait some more */
+      fc_printf(ftpconn, "ftp connect error %d\n", e);
+      return -1;
+   }
+
+   /* fall to here on first connect. Get a new socket: */
+   sock = t_socket(ftpconn->domain, SOCK_STREAM, 0);
+   if (sock == SYS_SOCKETNULL)
+      return -1;
+
+   ftpconn->cmd_sock = sock;
+
+   t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+
+   /* make initial non-blocking connect call */
+   e = t_connect(sock, &ftpsin, sinsize);
+   if (e != 0)
+   {
+      e = t_errno(sock);
+      if (e != EINPROGRESS)   /* still connecting */
+      {
+         return -1;
+      }
+   }
+   ftpconn->last_cmd = ftp_ticks;
+   FC_SETLOGSTATE(ftpconn,FCL_CONNECTING); 
+   return 0;
+}
+
+
+
+/* FUNCTION: fc_senduser()
+ * 
+ * state drivers - each of these is called from the state machine 
+ * switch table to push the connection from one state to another. 
+ * 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: All return 0 if OK, else non-zero error code 
+ */
+
+int
+fc_senduser(ftpc * ftpconn)
+{
+   /* try to log in with username */
+   sprintf(ftpconn->cmdbuf, "USER %s\r\n", ftpconn->username);
+   FC_SETLOGSTATE(ftpconn,FCL_SENTUSER); 
+   return (fc_sendcmd(ftpconn));
+}
+
+
+
+/* FUNCTION: fc_sendpass()
+ * 
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+int
+fc_sendpass(ftpc * ftpconn)
+{
+   sprintf(ftpconn->cmdbuf, "PASS %s\r\n", ftpconn->password);
+   FC_SETLOGSTATE(ftpconn,FCL_SENTPASS); 
+   return (fc_sendcmd(ftpconn));
+}
+
+
+
+/* FUNCTION: fc_sendport()
+ * 
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: 
+ */
+
+int
+fc_sendport(ftpc * ftpconn)
+{
+
+#ifdef IP_V4
+   if(ftpconn->domain == AF_INET)
+   {
+      ulong lp;
+      unshort  sp;
+
+      /* get my IP addr for this connection, set to local endian */
+      lp = htonl(ip_mymach(ftpconn->fhost));
+      sp = (unshort)ftpconn->dport;
+
+      /* format the port command from the fhost and dport info */
+      sprintf(ftpconn->cmdbuf, "PORT %u,%u,%u,%u,%u,%u\r\n",
+         (unsigned)(lp >> 24), (unsigned)(lp >> 16)&0xff, 
+         (unsigned)(lp >> 8)&0xff, (unsigned)(lp&0xff), 
+         (unsigned)(sp >> 8), (unsigned)(sp & 0xff));
+   }
+#endif   /* IPV4 */
+#ifdef IP_V6
+   if(ftpconn->domain == AF_INET6)
+   {
+      struct ip6_inaddr * myaddr;
+      char addrbuf[46];
+
+      /* get my IP addr for this connection & format into text */
+      myaddr = ip6_myaddr(&ftpconn->ip6_fhost, NULL);
+      if(myaddr == NULL)
+      {
+         dtrap();
+         return ENP_LOGIC;
+      }
+      inet_ntop(AF_INET6, &myaddr->addr, addrbuf, sizeof(addrbuf) );
+
+      /* format the port command from the fhost and dport info */
+      sprintf(ftpconn->cmdbuf, "EPRT |2|%s|%u|\r\n", addrbuf, ftpconn->dport);
+   }
+#endif   /* IP_V6 */
+
+   fc_clearf(ftpconn);  /* clear file xfer counters */
+   return (fc_sendcmd(ftpconn));
+}
+
+
+
+
+/* FUNCTION: fc_sendcmd()
+ * 
+ * fc_sendcmd(ftpc ftpconn) - send the command in the 
+ * ftpconn->cmdbuf. This is suitable for calling from the state 
+ * driver switch statement in fc_check() 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, else non-zero error code 
+ */
+
+int
+fc_sendcmd(ftpc * ftpconn)
+{
+   int   e;
+   int   send_len;
+
+   /*
+    * Altera Niche Stack Nios port modification:
+    * print cmdstate as %d rather than %s to remove build warning.
+    */
+   if(ftpconn->cmd_sock == INVALID_SOCKET)
+   {
+      dprintf("fc_sendcmd: bad socket; logstate: %d, cmdstate:%d \n",
+            ftpconn->logstate, ftpconn->cmdstate);
+      dtrap();
+      return -1;
+   }
+
+   /* do the printf first, else we run into state machine problems 
+   on speedy systems if command finishes while we're printfing */
+   if (ftpconn->options & FCO_VERB)
+      fc_printf(ftpconn, "ftp send: %s", ftpconn->cmdbuf);
+
+   send_len = strlen(ftpconn->cmdbuf);
+   /* these are short commands and should send all at once: */
+   e = t_send(ftpconn->cmd_sock, ftpconn->cmdbuf, send_len, 0);
+   if (e < 0)
+   {
+      e = t_errno(ftpconn->cmd_sock);
+      fc_printf(ftpconn, "send error %d on cmd %s", e, ftpconn->cmdbuf);
+      return -1;
+   }
+   /* verify that the whole buffer was sent */
+   if (e != send_len)
+   {
+      fc_printf(ftpconn,"partial send %d bytes on cmd %s",e,ftpconn->cmdbuf);
+      return -1;
+   }
+   ftpconn->last_cmd = ftp_ticks;
+   ftpconn->cmdbuf[0] = 0;    /* clear command buffer for reply */
+   return 0;
+}
+
+
+
+/* FUNCTION: fc_dir()
+ * 
+ * fc_dir() - start the ftp command to do a DIR ("ls" for you UNIX 
+ * folks) of the current directory of the server. Problems or results 
+ * are reported via fc_printf(). 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_dir(ftpc * ftpconn)
+{
+   int   e;
+
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+   if ((ftpconn->options & FCO_PASV)==0)  /* server not passive */
+   {
+      e = fc_dataconn(ftpconn);     /* this will start our listen */
+      if (e)   /* if error, kill session and exit */
+      {
+         fc_killsess(ftpconn);
+         return e;
+      }
+   }
+   ftpconn->cmdstate = FCC_NLSTPORT;   /* command state: sending list port */
+   FC_SETLOGSTATE(ftpconn,FCL_PENDING);   /* login state: cmd in progress */
+   e = fc_sendport(ftpconn);  /* kick off the port command */
+   return e;
+}
+
+
+
+/* FUNCTION: fc_pwd()
+ * 
+ * fc_pwd() - start the ftp command to return the Current Working 
+ * Directory. Problems or results are reported via fc_printf(). 
+ * 
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_pwd(ftpc * ftpconn)
+{
+   int   e;
+
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+   return(fc_usercmd(ftpconn, FCC_PWD, NULL));
+}
+
+
+
+/* FUNCTION: fc_chdir()
+ * 
+ * fc_chdir() - start the ftp command to return the Current Working 
+ * Directory. Problems or results are reported via fc_printf(). 
+ * 
+ * PARAM1: ftpc * ftpconn
+ * PARAM2: char * dirparm
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_chdir(ftpc * ftpconn, char * dirparm)
+{
+   int   e;
+
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+   return(fc_usercmd(ftpconn, FCC_CWD, dirparm));
+}
+
+
+
+/* FUNCTION: fc_settype()
+ * 
+ * fc_chdir() - start the ftp command to set the data type Problems 
+ * or results are reported via fc_printf(). 
+ *
+ * PARAM1: ftpc * ftpconn
+ * PARAM2: int typecode
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_settype(ftpc * ftpconn, int typecode)
+{
+   char *   typestring;
+   int   e;
+
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+
+   if (typecode == FTPTYPE_ASCII)
+      typestring = "A";
+   else if(typecode == FTPTYPE_IMAGE)
+      typestring = "I";
+   else
+      return ENP_PARAM; /* unsupported typecode */
+
+   ftpconn->newmode = typecode;  /* save type in case command works */
+   return(fc_usercmd(ftpconn, FCC_TYPE, typestring)); /* roll the bones */
+}
+
+
+
+/* FUNCTION: fc_quit()
+ * 
+ * fc_quit() - start the ftp command to end the ftp connection.
+ * Problems or results are reported via fc_printf(). 
+ * 
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_quit(ftpc * ftpconn)
+{
+   int   e;
+
+   if(ftpconn == NULL)
+   {
+      fc_printf(ftpconn, "ftp client not open\n");
+      return ENP_PARAM;
+   }
+
+   if(ftpconn->logstate != FCL_LOGGEDIN)
+   {
+      /* not logged in yet, just close the cmd socket */
+      if (ftpconn->cmd_sock && ftpconn->cmd_sock != INVALID_SOCKET)
+         t_socketclose(ftpconn->cmd_sock);
+      ftpconn->cmd_sock = INVALID_SOCKET;
+   }
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+   return(fc_usercmd(ftpconn, FCC_QUIT, NULL));
+}
+
+
+
+/* FUNCTION: fc_ready()
+ * 
+ * fc_ready() - Check to see if the passed session is ready to 
+ * initiate a new command. 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if ready, else ENP_ error code. 
+ */
+
+int
+fc_ready(ftpc * ftpconn)
+{
+   if(ftpconn == NULL)
+   {
+      fc_printf(ftpconn, "ftp client not open\n");
+      return ENP_PARAM;
+   }
+
+   if (ftpconn->logstate != FCL_LOGGEDIN)
+   {
+      if (ftpconn->logstate == FCL_PENDING)
+         fc_printf(ftpconn, "ftp client is busy, state %d\n", ftpconn->logstate);
+      else
+         fc_printf(ftpconn, "ftp client not logged in\n");
+      return ENP_BAD_STATE;
+   }
+   return 0;   /* ready for new command */
+}
+
+
+
+/* FUNCTION: fc_usercmd()
+ * 
+ * fc_usertcmd() - The guts of several simple ftp client commands. 
+ * Formats & send a command based on the passed code and an optional 
+ * text parameter. Problems or results are reported via fc_printf(). 
+ * 
+ * PARAM1: ftpc * ftpconn
+ * PARAM2: int cmdcode
+ * PARAM3: char * cmdarg
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_usercmd(ftpc * ftpconn, int cmdcode, char * cmdarg)
+{
+
+   ftpconn->cmdstate = cmdcode;     /* set command state */
+   FC_SETLOGSTATE(ftpconn,FCL_PENDING);   /* mark login state as busy */
+   switch (cmdcode)
+   {
+   case FCC_PWD:
+      strcpy(ftpconn->cmdbuf, "XPWD\r\n");
+      break;
+   case FCC_CWD:
+      sprintf(ftpconn->cmdbuf, "CWD %s\r\n", cmdarg);
+      break;
+   case FCC_TYPE:
+      sprintf(ftpconn->cmdbuf, "TYPE %s\r\n", cmdarg);
+      break;
+   case FCC_NLSTOK:
+      sprintf(ftpconn->cmdbuf, "NLST\r\n");
+      break;
+   case FCC_RECVOK:
+      sprintf(ftpconn->cmdbuf, "RETR %s\r\n", ftpconn->ffilename);
+      break;
+   case FCC_SENDOK:
+      sprintf(ftpconn->cmdbuf, "STOR %s\r\n", ftpconn->ffilename);
+      break;
+   case FCC_QUIT:
+      sprintf(ftpconn->cmdbuf, "QUIT\r\n");
+      break;
+      default:    /* bad parameter */
+      dtrap();
+      return ENP_PARAM;
+   }
+   return(fc_sendcmd(ftpconn));     /* send to server */
+}
+
+unsigned marksize = 4096;  /* units for hash marking */
+
+
+/* FUNCTION: fc_hashmark()
+ * 
+ * fc_hashmark() - called after each sucessfull network data block 
+ * transfer to handle the printing of hashmarks. 
+ * 
+ * PARAM1: ftpc * ftpconn
+ * PARAM2: ulong before
+ * PARAM3: unsigned added
+ *
+ * RETURNS: 
+ */
+
+void
+fc_hashmark(ftpc * ftpconn, 
+   ulong before,     /* data already moved before this transfer */
+   unsigned added)   /* additional data moved in this transfer */
+{
+   /* print a hash mark for each "marksize" boundary */
+   while (before/marksize < (before+added)/marksize)
+   {
+      fc_printf(ftpconn, "#");   /* call per-port printf */
+      if (added > marksize)   /* don't let "added" wrap */
+         added -= marksize;
+      else
+         added = 0;
+   }
+}
+
+
+
+/* fc_state() - display state info for passed connection */
+
+#ifdef NET_STATS
+
+char *   fc_statestr[]={
+   "started connect",
+   "connected but no \"220 ready\" msg",
+   "ready, but not logged in",
+   "sent user, waiting reply",
+   "user OK, sent password",
+   "cmd port open, no activity",
+   "command in progress",
+   "closing command connection",
+};
+
+
+
+/* FUNCTION: fc_state()
+ * 
+ * PARAM1: ftpc * fc
+ *
+ * RETURNS: 
+ */
+
+int
+fc_state(ftpc * fc)
+{
+   ns_printf(fc->pio,"state: %s, cmdstate: %d, mode:%s idle:%ld\n", 
+      fc_statestr[fc->logstate-1],
+      fc->cmdstate,
+      fc->mode == FTPTYPE_ASCII?"ascii":"binary", 
+      (ftp_ticks - fc->last_cmd)/TPS);
+   ns_printf(fc->pio,"server: %u.%u.%u.%u, data port:%d\n", 
+      PUSH_IPADDR(fc->fhost), fc->dport );
+   ns_printf(fc->pio,"Hashing: %s, passive: %s\n", 
+      (fc->options & FCO_HASH)?"ON":"OFF",
+      (fc->options & FCO_PASV)?"enabled":"off");
+
+   /* printf what's left of the last command. We do this by starting 
+    * with the second char, sice we may have nulled-out the first to 
+    * invalidate the buffer.
+    */
+   if(fc->cmdbuf[1])    /* don't bother if no text is set */
+      ns_printf(fc->pio, "last msg: %s", &fc->cmdbuf[3]);
+   /* if command in progess, show speed */
+   if(fc->logstate == 7)
+      fc_showspeed(fc);
+   return 0;
+}
+#endif   /* NET_STATS */
+
+
+
+/* FUNCTION: fc_pasv()
+ * 
+ * fc_pasv(ftpc ftpconn) - Start attempt to set FTP command session 
+ * to passive mode. This will cause the server to wait for client 
+ * (that's us) to initiate data transfers. This is usefull if we are 
+ * behind a firewall. Problems or results are reported via 
+ * fc_printf(). 
+ *
+ * PARAM1: ftpc * ftpconn
+ *
+ * RETURNS: Returns 0 if OK, else ENP_ error code. 
+ */
+
+int
+fc_pasv(ftpc * ftpconn)
+{
+   int   e;
+
+   if ((e = fc_ready(ftpconn)) != 0)
+      return e;
+
+   if (ftpconn->options & FCO_PASV) /* already passive? */
+      return ENP_LOGIC;
+
+   /* send PASV command to server */
+   ftpconn->cmdstate = FCC_PASV;    /* command state: sending pasv */
+   FC_SETLOGSTATE(ftpconn,FCL_LOGGEDIN);  /* login state: cmd in progress */
+
+#ifdef INWORKS
+   !!!!!!!!!
+
+   /* post-pasv operations */
+
+   ftpconn->options |= FCO_PASV;    /* set connection bit */
+
+#endif
+
+
+   return 0;
+}
+
+
+#ifdef OS_PREEMPTIVE
+/* FUNCTION: ftpc_process_rcvd_msgs ()
+ *
+ * It processes messages received from other tasks (such as console 
+ * task, Telnet server task, and timer task).  These messages provide 
+ * configuration parameters, initiate (or terminate) FTP transfer 
+ * requests, and provide periodic timeout notification.  This function 
+ * is invoked after the FTP client task returns from its wait for the 
+ * FTP client semaphore.
+ *
+ * This function is only used in multitasking environments.
+ *
+ * INPUT: None.
+ *
+ * OUTPUT: None.
+ */
+
+void ftpc_process_rcvd_msgs (void)
+{
+   struct ftpctask_msg * msgp;
+
+   while (ftpcq.q_len > 0)
+   {
+      LOCK_NET_RESOURCE (FTPCQ_RESID);
+      msgp = getq (&ftpcq);
+      UNLOCK_NET_RESOURCE (FTPCQ_RESID);
+   
+      if (!msgp) 
+      {
+         ++ftpc_err.empty_q;
+         return;
+      }
+
+      switch (msgp->type)
+      {
+         case FTPC_CNTRL_TRANSFER_MODE:
+         {
+            u_long transfer_mode;
+
+            ++ftpc_msg_stats.transfer_mode;
+            /* extract new transfer mode from rcvd message */
+            transfer_mode = *((u_long *)(&(msgp->parms [0])));
+            if (transfer_mode == FTPTYPE_ASCII)        
+               ftpc_process_asc_mode ((void *) (msgp->pio));
+            else
+               ftpc_process_bin_mode ((void *) (msgp->pio));
+            break;
+         }
+         case FTPC_CNTRL_CD:
+            ++ftpc_msg_stats.cd;
+            ftpc_process_chdir (((void *) (msgp->pio)), (char *) &(msgp->parms [0]));
+            break;
+         case FTPC_CNTRL_QUIT_FTP_SESS:
+            ++ftpc_msg_stats.quit_sess;
+            ftpc_process_quit_sess ((void *) (msgp->pio));
+            break;
+         case FTPC_CNTRL_VERBOSE:
+            ++ftpc_msg_stats.verbose;
+            ftpc_process_verbose ((void *) (msgp->pio));
+            break;
+         case FTPC_CNTRL_PASV:
+            ++ftpc_err.not_implemented;
+            break;
+         case FTPC_CNTRL_START_SESS:
+         {
+            u_long domain;
+            char * userp;
+            char * passwdp;
+
+            ++ftpc_msg_stats.start_sess;
+            domain = *((u_long *)((&(msgp->parms [0])) + 16));
+            userp = (char *) (((&(msgp->parms [0])) + 16) + sizeof (domain));
+            passwdp = userp + strlen (userp) + 1;
+            ftpc_process_open (((void *) (msgp->pio)), (&(msgp->parms [0])), domain, userp, passwdp);
+            break;
+         }
+         case FTPC_CNTRL_HASH_PRINT:
+            ++ftpc_msg_stats.hash_print;
+            ftpc_process_hash ((void *) (msgp->pio));
+            break;
+         case FTPC_CNTRL_MOVE_FILE:
+         {
+            u_long transfer_type;
+            char * sfilep;
+            char * dfilep;
+
+            ++ftpc_msg_stats.move_file;
+            transfer_type = *((u_long *)(&(msgp->parms [0])));
+            sfilep = (char *) (&(msgp->parms [0]) + sizeof (transfer_type));
+            dfilep = sfilep + strlen (sfilep) + 1;
+            ftpc_process_move (((void *) (msgp->pio)), transfer_type, sfilep, dfilep);
+            break;
+         }
+         case FTPC_CNTRL_PWD:
+            ++ftpc_msg_stats.pwd;
+            ftpc_process_pwd ((void *) (msgp->pio));
+            break;
+         case FTPC_CNTRL_LIST:
+            ++ftpc_msg_stats.list;
+            ftpc_process_list ((void *) (msgp->pio));
+            break;
+         case FPTC_CNTRL_PRINT_STATE:
+            ++ftpc_msg_stats.print_state;
+            ftpc_process_print_state ((void *) (msgp->pio));
+            break;
+         case FTPC_CNTRL_LOG:
+            ++ftpc_err.not_implemented;
+            break;
+         case FTPC_CNTRL_PERIODIC_TIMER:
+            ++ftpc_msg_stats.periodic_timer;
+            fc_check ();
+            break;
+         default:
+            /* increment error counter */
+            ++ftpc_err.bad_msgtype;
+            break;
+      }
+
+      /* free the message structure */
+      FTPC_FREE (msgp);
+   }
+}
+#endif /* OS_PREEMPTIVE */
+
+
+/* FUNCTION: ftpc_process_asc_mode ()
+ *
+ * This function sets the file transfer type for an ongoing FTP session 
+ * to ASCII.  it is either invoked directly from the FTP menu functions
+ * that process user input (for SUPERLOOP-type systems), or from the 
+ * message handler (ftpc_process_rcvd_msgs () (for multitasking 
+ * environments)).
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or return code from fc_settype ().
+ */
+
+int
+ftpc_process_asc_mode(void * pio)
+{
+   struct ftpc * tmpcon;
+   int e;
+
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   e = fc_settype (tmpcon, FTPTYPE_ASCII);
+   if (e)
+      ns_printf (pio,"ftp error %d setting type.\n", e);
+
+   return e;
+}
+
+
+/* FUNCTION: ftpc_process_bin_mode ()
+ *
+ * This function sets the file transfer type for an ongoing FTP session 
+ * to image (binary).
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or return code from fc_settype ().
+ */
+
+int
+ftpc_process_bin_mode(void * pio)
+{
+   struct ftpc * tmpcon;
+   int e;
+
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf (pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   e = fc_settype (tmpcon, FTPTYPE_IMAGE);
+   if (e)
+      ns_printf (pio,"ftp error %d setting type.\n", e);
+
+   return e;
+}
+
+
+/* FUNCTION: ftpc_process_chdir ()
+ *
+ * This function requests a change to a new working directory.
+ *
+ * INPUT: (1) Pointer to generic IO structure where request originated.
+ *        (2) Name of new working directory
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or return code from fc_chdir ().
+ */
+
+int
+ftpc_process_chdir(void * pio, char * dirstr)
+{
+   struct ftpc * tmpcon;
+   
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf (pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   return (fc_chdir (tmpcon, dirstr));
+}
+
+
+/* FUNCTION: ftpc_process_quit_sess ()
+ *
+ * This function requests a termination of the FTP session.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or return code from fc_quit ().
+ */
+
+int
+ftpc_process_quit_sess (void * pio)
+{
+   struct ftpc * tmpcon;
+
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   return (fc_quit (tmpcon));
+}
+
+
+/* FUNCTION: ftpc_process_verbose ()
+ *
+ * This function sets the verbose flag for the FTP session.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         0, otherwise.
+ */
+
+int
+ftpc_process_verbose(void * pio)
+{
+   struct ftpc * tmpcon;
+   
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   if (tmpcon->options & FCO_VERB)
+      tmpcon->options &= ~FCO_VERB;
+   else
+      tmpcon->options |= FCO_VERB;
+
+   ns_printf(pio,"ftp verbose mode %s\n", 
+    (tmpcon->options & FCO_VERB) ? "on":"off");
+
+   return 0;
+}
+
+
+/* FUNCTION: ftpc_process_open ()
+ *
+ * This function opens a new session to the specified FTP server.
+ *
+ * INPUT: (1) Pointer to generic IO structure where request originated.
+ *        (2) IP address (IPv4 or IPv6 address)
+ *        (3) domain (AF_INET or AF_INET6)
+ *        (4) username
+ *        (5) password
+ *
+ * OUTPUT: -1, if fc_connect () returns 0; otherwise, 0.
+ */
+
+int
+ftpc_process_open(void * pio, u_char * srvp, u_long domain, char * user, char * passwd)
+{
+   /* make the connection; this will add a connection to the list
+    * starting from "ftp_clients"
+    */
+   if (fc_connect (srvp, user, passwd, pio, domain) == NULL)
+      return -1;
+   else
+      return 0;
+}
+
+
+/* FUNCTION: ftpc_process_hash ()
+ *
+ * This function sets the hash print flag for the FTP session.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         0, otherwise.
+ */
+
+int
+ftpc_process_hash(void * pio)
+{
+   struct ftpc * tmpcon;
+   
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   if (tmpcon->options & FCO_HASH)
+      tmpcon->options &= ~FCO_HASH;
+   else
+      tmpcon->options |= FCO_HASH;
+
+   ns_printf(pio,"FTP hash mark printing turned %s\n", 
+    tmpcon->options & FCO_HASH?"on":"off");
+    
+   return 0;
+}
+
+
+/* FUNCTION: ftpc_process_move ()
+ *
+ * This function gets (or puts) a file from (or to) the FTP server.
+ *
+ * INPUT: (1) Pointer to generic IO structure where request originated.
+ *        (2) Direction of transfer (e.g., FTPC_GET_TRANSFER, etc.)
+ *        (3) source filename
+ *        (4) destination filename
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or, the return code from fc_get () or fc_put ().
+ */
+
+int
+ftpc_process_move(void * pio, int direction, char * sfile, char * dfile)
+{
+   struct ftpc * tmpcon;
+
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf (pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   if (direction == FTPC_GET_TRANSFER) 
+      return (fc_get (tmpcon, sfile, dfile));
+   else
+      return (fc_put (tmpcon, sfile, dfile));
+}
+
+
+/* FUNCTION: ftpc_process_pwd ()
+ *
+ * This function sends a request to obtain the current working directory.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or, the return code from fc_pwd ().
+ */
+
+int
+ftpc_process_pwd (void * pio)
+{
+   struct ftpc * tmpcon;
+
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   return (fc_pwd (ftp_get_con(pio)));
+}
+
+
+/* FUNCTION: ftpc_process_list ()
+ *
+ * This function sends a request to obtain a listing of the current working 
+ * directory.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: -1, if an FTP session doesn't exist for the originating console;
+ *         or, the return code from fc_dir ().
+ */
+
+int
+ftpc_process_list (void * pio)
+{
+   struct ftpc * tmpcon;
+
+   FC_MENULOG();
+   if ((tmpcon = ftp_get_con (pio)) == NULL)
+   {
+      ns_printf(pio,"ftp command connection not open\n");
+      return 1;
+   }
+
+   return (fc_dir (tmpcon));
+}
+
+
+/* FUNCTION: ftpc_process_print_state ()
+ *
+ * This function prints state information associated with the current FTP
+ * session.
+ *
+ * INPUT: Pointer to generic IO structure where request originated.
+ *
+ * OUTPUT: 0.
+ */
+
+int
+ftpc_process_print_state (void * pio)
+{
+   struct ftpc *  tmpcon   ;
+
+   if ((tmpcon = ftp_get_con(pio)) == NULL)
+   {
+      ns_printf(pio,"FTP client not open\n");
+   }
+/*
+ * Altera Niche Stack Nios port modification
+ * conditionally call fc_state; it may not be available
+ */
+#ifdef NET_STATS
+   else
+   {
+      fc_state(tmpcon);
+   }
+#endif
+
+#ifdef FC_LOG
+   if (log_flag==TRUE)
+   {
+#ifdef FC_LOGFILE
+      if (ftplog)
+      {
+         ns_printf(pio,"Logging to file is enabled\n");
+      }
+      else
+#endif   /*FC_LOGFILE */
+      ns_printf(pio,"Logging to STDIO is enabled\n");
+   }
+   else
+      ns_printf(pio,"Logging is disabled\n");
+
+#endif   /* FC_LOG */
+
+   return 0;
+}
+
+#endif /* FTP_CLIENT */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h
new file mode 100644
index 0000000..3cd4353
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpclnt.h
@@ -0,0 +1,244 @@
+/*
+ * FILENAME: FTPCLNT.H
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES:
+ *
+ * PORTABLE: yes
+ */
+
+/* ftpclnt.h Definitions for generic FTP client. 
+ * 1/12/97 - Created. John Bartas 
+ */
+#ifndef FTPCLNT_H
+#define  FTPCLNT_H
+
+/* Define the options enabled for FTP Client */
+#define  FC_USECALLBACK  1  /* Call callbacks when FTPClient changes state */
+#define  FC_LOG          1  /* Log FTP output to stdio/file */
+
+#ifdef NOTDEF  /* List of options disabled */
+#endif   /* NOTDEF */
+
+#ifdef SUPERLOOP
+#define SignalFtpClient()  /* define to nothing */
+#endif
+
+/* Define the structure used for each FTP connection */
+typedef struct ftpc 
+{
+   struct ftpc *  next; /* list link */
+   int   logstate;      /* loggin (FCL_) state */
+   int   cmdstate;      /* command (FCC_) state */
+   int   mode;          /* FTPTYPE_ASCII or FTPTYPE_IMAGE */
+   int   newmode;       /* mode to set if TYPE cmd succeeds */
+   int   in_use;        /* reentry flag */
+   int   domain;        /* AF_INET or AF_INET6 */
+   ip_addr fhost;       /* host, if connected (in net endian) */
+#ifdef IP_V6
+   ip6_addr ip6_fhost;  /* V6 host, if connected */
+#endif   /* IP_V4 */
+   unsigned options;    /* hash, pasv, etc */
+   unshort     dport;   /* data port */
+   SOCKTYPE cmd_sock;   /* command socket descriptor */
+   SOCKTYPE data_sock;  /* data socket descriptor */
+   char  username[FTPMAXUSERNAME];  /* name of connection user for login */
+   char  password[FTPMAXUSERPASS];  /* password for login */
+   char  ffilename[FTPMAXPATH+FTPMAXFILE];   /* name for foriegn file */
+   char  cmdbuf[CMDBUFSIZE];  /* command buffer */
+   char  databuf[FILEBUFSIZE];   /* buffer for FTP data */
+   VFILE * fp;    /* file in progress */
+   unsigned datact;  /* unprocessed data in databuf */
+   unsigned offset;  /* offset to data in databuf */
+   ulong    datadone;   /* data already moved in current transfer */
+   ulong    filesize;   /* file size of send/receive file */
+   ulong    last_cmd;   /* time of last cmdstate change */
+   ulong    last_data;  /* time of last data transfer activity */
+   void *   pio;     /* To support Generic I/O for client */
+} ftpc;
+
+extern   ftpc *   ftp_clients;   /* support multiple client links */
+
+extern   unsigned marksize;   /* units for hash marking */
+
+/* bits for ftpc options field: */
+#define  FCO_HASH    0x0001   /* hash mark printing */
+#define  FCO_PASV    0x0002   /* in passive mode */
+#define  FCO_VERB    0x0004   /* verbose mode */
+
+/* ftp client loggin states; If any change is done, also update fc_str[]. */
+#define  FCL_CONNECTING    1  /* started connect */
+#define  FCL_CONNECTED     2  /* connected but no "220 ready" msg */
+#define  FCL_READY         3  /* ready, but not logged in */
+#define  FCL_SENTUSER      4  /* sent user, waiting reply */
+#define  FCL_SENTPASS      5  /* user OK, sent password */
+#define  FCL_LOGGEDIN      6  /* cmd port open, no activity */
+#define  FCL_PENDING       7  /* command in progress (see FCC_* codes) */
+#define  FCL_CLOSING       8  /* closing command connection */
+
+/* ftp client command states; grouped by command type
+   If any change is done, also update fc_str[]. */
+#define  FCC_RECVPORT      10 /* sent port command, awaiting reply */
+#define  FCC_RECVOK        11 /* sent RETR command, awaiting reply */
+#define  FCC_RECVCONN      12 /* connecting for file receive */
+#define  FCC_RECEIVING     13 /* file receive in progress */
+#define  FCC_RECVDONE      14 /* done with RETR, awaiting final msg */
+
+#define  FCC_SENDPORT      20 /* sent port command, awaiting reply */
+#define  FCC_SENDOK        21 /* sent STOR command, awaiting reply */
+#define  FCC_SENDCONN      22 /* connecting for file send */
+#define  FCC_SENDING       23 /* data file send in progress */
+#define  FCC_SENDDONE      24 /* done with STOR, awaiting final msg */
+
+#define  FCC_NLSTPORT      30 /* sent port for NLST command */
+#define  FCC_NLSTOK        31 /* sent NLST for NLST command */
+#define  FCC_NLSTCONN      32 /* waiting for connect on data port */
+#define  FCC_NLSTING       33 /* waiting for connect on data port */
+#define  FCC_NLSTDONE      34 /* done with NLST, awaiting final msg */
+
+
+/* the non-data port commands: */
+
+#define  FCC_CWD           70 /* sent cwd command, awaiting reply */
+#define  FCC_PWD           80 /* sent pwd command, awaiting reply */
+#define  FCC_TYPE          90 /* sent TYPE command, awaiting reply */
+#define  FCC_PASV       100   /* sent PASV, awaiting reply */
+#define  FCC_QUIT       110   /* sent QUIT, awaiting reply (before closing) */
+
+/* Map ftp memory alloc/free routines */
+#define  FTPC_ALLOC(size)  (ftpc*)npalloc(size)
+#define  FTPC_FREE(buf) npfree(buf)
+
+
+/* ftp client extern entry points. The commands (all but fc_check) 
+ * initiate the transactions and return without blocking. The system 
+ * or caller must regularly call fc_check() to drive the transaction. 
+ * Completion is detected by checking fc_logstate.
+ */
+ftpc *   fc_connect(void * fhost, char * user, char * passwd,void * pio, int domain);
+int   fc_put(ftpc * fc, char * fname, char * lname);
+int   fc_get(ftpc * fc, char * fname, char * lname);
+int   fc_chdir(ftpc * ftpconn, char * dirparm);
+int   fc_pwd(ftpc * ftpconn);
+int   fc_dir(ftpc * ftpconn);
+int   fc_settype(ftpc * ftpconn, int type);
+int   fc_state(ftpc * ftpconn);
+int   fc_pasv(ftpc * ftpconn);
+int   fc_quit(ftpc * ftpconn);
+
+int   fc_check(void);   /* ftp client "task" entry point */
+
+/* log_printf is used in ftpclnt.c and ftpcprn.c */
+#ifdef FC_LOG
+#include "in_utils.h"            /* for GEN_IO */
+extern   GEN_IO         ftplog;  /* ftplog is "ptr to IO device" */
+#define  log_printf     ns_printf   /* Use genericIO to send log to stdio/file */
+extern   int            log_flag;   /* to dynamically enable/disable logging */
+#define  FC_LOGFILE     1        /* log to file */
+
+#else
+#define  log_printf     ;        /* Do nothing */
+#endif   /* FC_LOG */
+
+/* The user application can set a callback via fc_callback to receive 
+ * information when the logstate or cmdstate changes. Sometimes, the 
+ * callback might just be interested in the states, if it is using 
+ * only one FTP connection. In that case, it need not know about 
+ * ftpc. Hence the first argument is a "void instead of "ftpc If the 
+ * callback needs information about ftp connection, it can cast fc to 
+ * "ftpc *"
+ */
+#ifdef FC_USECALLBACK
+extern   void (*fc_callback)(void * fc, int logstate, int cmdstate);
+#endif
+
+/* types of messages sent to FTP client task from the console task,
+ * Telnet server task, or timer tick task.  These messages are
+ * deposited into the 'ftpcq' queue, and provide configuration 
+ * parameters, initiate (or terminate) FTP transfer requests, and 
+ * provide periodic timeout notification.
+ */
+#define FTPC_CNTRL_TRANSFER_MODE  0x0 /* ascii or binary */
+#define FTPC_CNTRL_CD             0x1
+#define FTPC_CNTRL_QUIT_FTP_SESS  0x2
+#define FTPC_CNTRL_VERBOSE        0x3
+#define FTPC_CNTRL_PASV           0x4
+#define FTPC_CNTRL_START_SESS     0x5
+#define FTPC_CNTRL_HASH_PRINT     0x6
+#define FTPC_CNTRL_MOVE_FILE      0x7 /* get or put */
+#define FTPC_CNTRL_PWD            0x8
+#define FTPC_CNTRL_LIST           0x9
+#define FPTC_CNTRL_PRINT_STATE    0xA
+#define FTPC_CNTRL_LOG            0xB
+#define FTPC_CNTRL_PERIODIC_TIMER 0xC
+
+#define FTPC_NUM_MSGS             0xD
+
+/* type of FTP transfer requested from client: GET or PUT */
+#define FTPC_GET_TRANSFER 0x1 
+#define FTPC_PUT_TRANSFER 0x2
+
+/* base structure for all messages sent to FTP client task */
+struct ftpctask_msg
+{
+   struct ftpctask_msg * next;
+   u_long type;
+   u_long pio;
+   u_char parms [1];
+};
+
+/* statistics on errors encountered by the FTP client task */
+struct ftpc_err
+{
+   u_long alloc_fail;
+   u_long empty_q;
+   u_long not_implemented;
+   u_long bad_msgtype;
+};
+
+/* statistics on the types of messages received by the FTP client task */
+struct ftpc_msg_stats
+{
+   u_long transfer_mode;
+   u_long cd;
+   u_long quit_sess;
+   u_long verbose;
+   u_long start_sess;
+   u_long hash_print;
+   u_long move_file;
+   u_long pwd;
+   u_long list;
+   u_long print_state;
+   u_long periodic_timer;
+};
+
+/* FTP client task message queue (contains messages from other tasks) */
+extern struct queue ftpcq;
+/* data structure to keep track of number of various types of messages
+ * received by the FTP client task.
+ */
+extern struct ftpc_msg_stats ftpc_msg_stats;
+/* data structure to keep track of errors encountered by the FTP client
+ * task during its operation.
+ */
+extern struct ftpc_err ftpc_err;
+
+void ftpc_process_rcvd_msgs (void);
+int ftpc_process_asc_mode(void * pio);
+int ftpc_process_bin_mode(void * pio);
+int ftpc_process_chdir(void * pio, char * dirstr);
+int ftpc_process_quit_sess (void * pio);
+int ftpc_process_verbose(void * pio);
+int ftpc_process_open(void * pio, u_char * srvp, u_long domain, char * user, char * passwd);
+int ftpc_process_hash (void * pio);
+int ftpc_process_move (void * pio, int direction, char * sfile, char * dfile);
+int ftpc_process_pwd (void * pio);
+int ftpc_process_list (void * pio);
+int ftpc_process_print_state (void * pio);
+
+#endif   /* FTPCLNT_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c
new file mode 100644
index 0000000..1d069f0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcport.c
@@ -0,0 +1,205 @@
+/*
+ * FILENAME: ftpcport.c
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP Client
+ *
+ * ROUTINES: ftpc_nvset(), prep_ftpc(), tk_ftpclnt()
+ *
+ * PORTABLE: NO
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+
+#ifdef FTP_CLIENT
+
+#include "ftpsrv.h"
+#include "ftpclnt.h"
+
+#ifndef SUPERLOOP
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+#include OSPORT_H
+#endif /* SUPERLOOP */
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"
+#endif /* INCLUDE_NVPARMS */
+
+#ifdef IN_MENUS
+#include "menu.h"
+#endif /* IN_MENUS */
+
+#ifdef IN_MENUS
+extern struct menu_op ftpmenu[];
+#endif /* IN_MENUS */
+
+#ifdef INCLUDE_NVPARMS
+/* Please see nvparms.h and nvparms.c regarding the usage of
+ * the following datatypes and functions.
+ */
+
+int ftpc_nvset(NV_FILE * fp);
+
+struct ftpc_nvparam ftpc_nvparms;
+
+struct nvparm_info ftpc_nvformats[] = 
+{
+   {"ftpc reply timout: %u\n"   , NVINT, NVBND_NOOP, \
+    &ftpc_nvparms.fc_replytmo    , NULL, }, 
+   {"ftpc activity timout: %u\n", NVINT, NVBND_NOOP, \
+    &ftpc_nvparms.fc_activity_tmo, NULL, }, 
+};
+
+#define NUMFTPC_FORMATS  \
+        (sizeof(ftpc_nvformats)/sizeof(struct nvparm_info))
+
+#endif /* INCLUDE_NVPARMS */
+
+#ifdef INCLUDE_NVPARMS
+
+/* FUNCTION: ftpc_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int ftpc_nvset(NV_FILE * fp)
+{
+int i = 0;
+
+   nv_fprintf(fp, ftpc_nvformats[i++].pattern, ftpc_nvparms.fc_replytmo);
+   nv_fprintf(fp, ftpc_nvformats[i++].pattern, ftpc_nvparms.fc_activity_tmo);
+   return 0;
+}
+
+struct nvparm_format ftpc_format = 
+{
+   NUMFTPC_FORMATS,
+   &ftpc_nvformats[0],
+   ftpc_nvset,
+   NULL
+};
+
+#endif /* INCLUDE_NVPARMS */
+
+
+/* FUNCTION: prep_ftpc()
+ * 
+ * PARAMS: NONE
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+int prep_ftpc(void)
+{
+int e = 0;
+#ifdef IN_MENUS
+   /* install the FTP Client commands */
+   e = install_menu(&ftpmenu[0]);
+#endif /* IN_MENUS */
+
+#ifdef INCLUDE_NVPARMS
+   e = install_nvformat(&ftpc_format, nv_formats);
+   if(e)
+   {
+      dprintf("unable to install FTPClient NVPARMS reconfigure nv_formats[]\n");
+      dtrap();
+   }
+#endif /* INCLUDE_NVPARMS */
+   return e;
+}
+
+
+#ifndef SUPERLOOP
+
+#ifdef FTP_CLIENT
+TK_OBJECT(to_ftpclnt);
+TK_ENTRY(tk_ftpclnt);
+long ftpclnt_wakes = 0;
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Use task priority and stack size values from ipport.h
+ */
+#ifdef FTP_CLIENT
+struct inet_taskinfo ftpctask = {
+      &to_ftpclnt,
+      "FTP client",
+      tk_ftpclnt,
+      TK_FTPCLNT_TPRIO,
+      TK_FTPCLNT_SSIZE,
+};
+#endif
+
+/* The FTP client task waits for the FTP semaphore to be signaled.
+ * The semaphore is signaled by other tasks such as console task, Telnet
+ * server task, and timer task after they have deposited a message into
+ * the FTP client task's message queue.  These messages provide 
+ * configuration parameters, initiate (or terminate) FTP transfer requests, 
+ * and provide periodic timeout notification.  The latter is currently
+ * where the bulk of the work (wrt transfers) is done.
+ */
+
+/* FUNCTION: tk_ftpclnt()
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+ 
+#ifdef FTP_CLIENT
+
+TK_ENTRY(tk_ftpclnt)
+{
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+#ifndef OS_PREEMPTIVE
+   for (;;)
+   {
+      int work;
+
+      work = fc_check();   /* Let client spin, get level of load */
+      switch(work)         /* base task action on work level */
+      {
+      case 2:
+         tk_yield();       /* quick give up of CPU in case it didn't block */
+         break;
+      case 1:
+         TK_SLEEP(1);      /* pass a time tick before checking again */
+         break;
+      case 0:
+         TK_BLOCK();       /* all done, go back to sleep */
+         break;
+      default:
+         dtrap();          /* bad return value */
+         break;
+      }
+      ftpclnt_wakes++;   /* count wakeups */
+      if (net_system_exit)
+         break;
+   }
+#else
+   for (;;)
+   {
+      wait_app_sem (FTPC_SEMID);
+      ftpclnt_wakes++; /* count wakeups */
+      ftpc_process_rcvd_msgs (); /* process messages received from other tasks */
+      if (net_system_exit)
+         break;
+   }
+#endif
+
+   TK_RETURN_OK();
+}
+
+#endif /* FTP_CLIENT */
+
+#endif /* SUPERLOOP */
+
+#endif /* FTP_CLIENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c
new file mode 100644
index 0000000..7109294
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpcprn.c
@@ -0,0 +1,137 @@
+/*
+ * FILENAME: ftpcprn.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES: fc_printf(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* The FTP client's message handler for this port. This is off by 
+ * itself without it's prototype included to please the incredibly 
+ * fussy Borland compiler again.... 
+ */
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+
+#ifdef FTP_CLIENT
+
+#include "ftpsrv.h"
+#include "ftpclnt.h"
+
+struct ftpc;
+extern   struct ftpc *  ftp_clients;   /* support multiple client links */
+extern   char *   prompt;
+
+
+/* The member  in_use of a FTP connection is turned ON when fc_printf() is 
+ * being done. FTP Client, unlike FTP Server has different entry points. 
+ * For example,
+ * -  When the user enters FTP commands from the command line, the FTP client
+ *    code gets executed. 
+ * -  fc_check() is called periodically to process FTP client connections. 
+ * Consider the following scenario.
+ * 1. The user executes PUT command, and the FTP client code
+ *    initiating the PUT uses fc_printf() immediately after sending the
+ *    PORT command using fc->cmdbuf. It would then check whether the command 
+ *    was properly sent or not. 
+ * 2. Now before this check can be done, fc_printf() calls tk_yield(), which
+ *    would call fc_check(). fc_check() would execute and do network I/O for
+ *    this connection and update the fc->cmdbuf based on the response for
+ *    PORT command. 
+ * 3. Now after fc_printf() is done, the check for PORT command would fail
+ *    because the fc->cmdbuf is modified.
+ *
+ * On a multitasking system, FTP client would be more susceptible to 
+ * these kind of problems. Hence a provision is provided wherein fc_check() 
+ * doesn't execute when fc_printf() is being done.
+*/
+
+
+
+/* FUNCTION: fc_printf()
+ * 
+ * fc_printf() - per-port function to handle messages from the FTP 
+ * client library. The messages may be sent to a console if your 
+ * system has one, logged, or just punted. For DOS demo .exe, we 
+ * print to screen and restore the user prompt. 
+ *
+ * PARAM1: struct ftpc * fc
+ * PARAM2: char * format
+ * PARAM3: long p1
+ * PARAM4: long p2
+ * PARAM5: long p3
+ * PARAM6: long p4
+ * PARAM7: long p5
+ *
+ * RETURNS: 
+ */
+
+#ifdef PRINTF_STDARG
+/* different fc_printf() functions depending on VA support */
+
+void
+fc_printf(struct ftpc * fc, char * format, ...)
+{
+   va_list a;
+   char linebuf[FTPMAXPATH];
+
+#else /* the non-STDARG version */
+
+void
+fc_printf(struct ftpc * fc, char * format, 
+   long  p1,   long  p2,   long  p3,   long  p4,   long  p5)
+{
+#endif /* PRINTF_STDARG */
+
+   char *   cp;
+   void *   pio=NULL;
+
+   /* make sure caller passed our sole supported fc. note: fc may be NULL 
+    * during fc_connect() call - this is OK. 
+    */
+   if (fc != NULL )
+   {
+      pio=(void *)fc->pio;
+      /* set re-entry flag. So that fc_check() doesn't process this 
+       * connection. If fc_check()->...->fc_printf() is called, then 
+       * in_use is already set, and the increment/decrement 
+       * below is harmless.
+       */
+      fc->in_use++;    
+   }
+   
+
+#ifdef PRINTF_STDARG
+   va_start(a,format);
+   vsprintf(linebuf,format,a);
+   va_end(a);
+   ns_printf(pio,linebuf);
+#else /* the non-STDARG version */
+   ns_printf(pio,format, p1, p2, p3, p4, p5);
+#endif /* PRINTF_STDARG */
+
+#ifdef FC_LOG
+   /* If logging is enabled, log it. Don't log to stdio. 
+    */
+   if ((log_flag == TRUE) && (ftplog!=NULL) )
+#ifdef PRINTF_STDARG
+      log_printf(ftplog,linebuf);
+#else /* the non-STDARG version */
+      log_printf(ftplog,format, p1, p2, p3, p4, p5);
+#endif /* PRINTF_STDARG */
+#endif
+
+   /* see if we should regenerate prompt */
+   cp = (format + (strlen(format)-1));
+   if (*cp == '\n' || *cp == '\r')  /* look for newline */
+      ns_printf(pio,prompt);
+
+   if(fc)
+      fc->in_use--;     /* clear re-entry flag */
+}
+
+#endif /* FTP_CLIENT */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c
new file mode 100644
index 0000000..df8a25d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpmenu.c
@@ -0,0 +1,971 @@
+/*
+ * FILENAME: ftpmenu.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTPCLIENT
+ *
+ * ROUTINES: ftp_get_con(), ftp_open(), ftp_get(), ftp_put(), 
+ * ROUTINES: ftp_move(), ftp_asc_mode(), ftp_bin_mode(), ftp_hash(), 
+ * ROUTINES: ftp_pwd(), ftp_chdir(), ftp_verbose(), ftp_quit(), 
+ * ROUTINES: ftp_list(), ftp_state(), ftp_pasv(), fc_file_out(), ftp_log(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* ftpmenu.c DOS demo menu hooks for FTP client. This is the 
+ * non-portable portion of the FTP client for the DOS demo package. 
+ * 1/12/97 - Created. John Bartas 
+ * 1/4/99  - Edited menu text -MPG- 
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+
+#ifdef FTP_CLIENT
+
+#include "ftpsrv.h"
+#include "ftpclnt.h"
+
+#include "menu.h"
+
+/* The FTP client's per-port message handler */
+extern   void fc_printf(ftpc *, char *, ...);   /* per-port response printer */
+
+int  ftp_open    (void * pio);
+int  ftp_move    (void * pio, int direction);
+int  ftp_get     (void * pio);
+int  ftp_put     (void * pio);
+int  ftp_asc_mode(void * pio);
+int  ftp_bin_mode(void * pio);
+int  ftp_hash    (void * pio);
+int  ftp_pwd     (void * pio);
+int  ftp_list    (void * pio);
+int  ftp_chdir   (void * pio);
+int  ftp_verbose (void * pio);
+int  ftp_state   (void * pio);
+int  ftp_pasv    (void * pio);
+int  ftp_quit    (void * pio);
+int  ftp_log     (void * pio);
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+struct menu_op ftpmenu[]   =  {
+   { "ftpc",  stooges,     "FTP client menu" },
+   { "ascii", ftp_asc_mode,"use ASCII transfer mode" },
+   { "binary",ftp_bin_mode,"use Binary transfer mode" },
+   { "cd",    ftp_chdir,   "change server's directory" },
+   { "fquit", ftp_quit,    "quit FTP session" },
+   { "fverb", ftp_verbose, "toggle verbose mode" },
+   { "fpasv", ftp_pasv,    "set server to passive mode" },
+   { "ftp",   ftp_open,    "open an FTP connection" },
+   { "hash",  ftp_hash,    "toggle hash mark printing" },
+   { "get",   ftp_get,     "GET a file" },
+   { "put",   ftp_put,     "PUT a file" },
+   { "pwd",   ftp_pwd,     "print working directory" },
+   { "ls",    ftp_list,    "list files in server directory" },
+#ifdef NET_STATS
+   { "fstate",ftp_state,   "display FTP client state" },
+#endif
+#ifdef FC_LOG
+   { "flog",  ftp_log,     "enable/disable logging" },
+#endif
+   { NULL },
+};
+
+#ifdef FC_LOG
+#define FC_MENULOG() {                                       \
+                        if ((log_flag==TRUE) && (ftplog!=NULL))                  \
+                           log_printf(ftplog,"%s%s\n", \
+                              prompt,((GEN_IO)pio)->inbuf);  \
+                     }
+#else
+#define  FC_MENULOG() ;
+#endif   /* FC_LOG */
+
+static char * ousage = "usage: ftp host username [password]\n";
+extern   char *   prompt;  /* system menu prompt */
+
+/* functions that are used to send messages to the FTP client task */
+int ftpc_send_msg1 (u_long type, u_long pio);
+
+int ftpc_send_msg2 (u_long type, u_long pio, u_char * argp, u_long arglen);
+
+int ftpc_send_msg4 (u_long type, 
+                    u_long pio, 
+                    u_char * arg1p, 
+                    u_long arg1len,
+                    u_char * arg2p, 
+                    u_long arg2len,
+                    u_char * arg3p, 
+                    u_long arg3len);
+
+int ftpc_send_msg5 (u_long type, 
+                    u_long pio, 
+                    u_char * arg1p,  /* address */
+                    u_long arg1len,
+                    u_char * arg2p,  /* domain */
+                    u_long arg2len,
+                    u_char * arg3p,  /* username */
+                    u_long arg3len,
+                    u_char * arg4p,  /* password */
+                    u_long arg4len);
+
+
+/* FUNCTION: ftp_get_con()
+ * 
+ * ftp_get_con() - Get the FTP connection for the particular pio 
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return NULL if a corresponding connection is not found. 
+ */
+
+struct ftpc *  
+ftp_get_con(void * pio)
+{
+   struct ftpc *  tmpcon   =  NULL  ;
+
+   tmpcon = ftp_clients ;
+   while ( tmpcon )
+   {
+      if (tmpcon->pio == pio )
+      {
+         return tmpcon;
+      }
+      else
+         tmpcon=tmpcon->next ;
+   }
+
+   /* We couldn't find a connection which uses pio */
+
+   return NULL ;
+}
+
+
+/* FUNCTION: ftp_open()
+ * 
+ * ftp_open() - Menu system function to open a new connection for FTP 
+ * commands. If a connection is already open, this function returns an 
+ * error to its caller. get host, user, password info from menu system's 
+ * command buffer.
+ *
+ * In multitasking environments, this function sends a message (with the
+ * various parameters from the user's request) to the FTP client task.
+ * In SUPERLOOP mode, it just directly invokes the function that uses
+ * the parameters provided to initiate a connection.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: -1 if an error occured; 0, if it initiated the opening of
+ * a session.
+ */
+
+int
+ftp_open(void * pio)
+{
+   char *   hostname=NULL;
+   char *   user;
+   char *   passwd;
+   char *   msg;
+   u_long     domain;        /* AF_INET or AF_INET6 */
+   u_char     server[16];    /* dual mode IP address */
+   u_long x;
+
+   GEN_IO io= (GEN_IO) pio ;
+
+   FC_MENULOG();
+   /* extract args from command buffer */
+   if ( io != NULL )
+      hostname = nextarg(io->inbuf);
+   if (*hostname == 0)
+   {
+      ns_printf(pio,ousage);
+      return -1;
+   }
+   user = nextarg(hostname);
+   *(user-1) = 0; /* null terminate hostname */
+   if (*user == 0)
+   {
+      ns_printf(pio,ousage);
+      return -1;
+   }
+   passwd = nextarg(user);
+   if (*passwd != 0) /* if passwrod was specd... */
+      *(passwd-1) = 0;  /* ...null terminate user */
+
+
+
+#ifdef IP_V6
+   /* Code for both dual-mode and  IP_V6 only:
+    * If there are colons in the host name, then assume
+    * it's IPv6, else set domain for IP_V4
+    */
+   if(strchr(hostname, ':'))
+      domain = AF_INET6;
+   else
+      domain = AF_INET;
+
+   if(inet_pton(domain, hostname, &server) !=0)
+      msg = pton_error;
+   else
+      msg = NULL;
+#else /* IP_V4 only */
+   {
+      unsigned int my_bits;   /* tmp, for subnet bits */
+      msg = parse_ipad((ip_addr*)&server, &my_bits, hostname);
+      domain = AF_INET;
+   }
+#endif /* IP_V4 */
+
+   if (msg)
+   {
+      ns_printf(pio,"FTP host address error: %s\n", msg);
+      return -1;
+   }
+
+   /* Supports only one client connection for each PIO */
+   if ( ftp_get_con(pio) != NULL )
+   {
+      ns_printf(pio,"ftp session already open\n");
+      return -1;
+   }
+
+   x = strlen (passwd) + 1;
+
+#ifdef OS_PREEMPTIVE
+   ftpc_send_msg5 (FTPC_CNTRL_START_SESS,
+                   (u_long) pio, 
+                   server,
+                   sizeof (server),
+                   (u_char *) &domain,
+                   sizeof (domain),
+                   (u_char *) user,
+                   (strlen (user) + 1),
+                   (u_char *) passwd,
+                   (strlen (passwd) + 1));
+#else
+   ftpc_process_open (pio, server, domain, user, passwd); 
+#endif                   
+                   
+   return 0;
+}
+
+
+/* FUNCTION: ftp_get()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ftp_get(void * pio)
+{
+   FC_MENULOG();
+   return ftp_move(pio,1);
+}
+
+
+/* FUNCTION: ftp_put()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ftp_put(void * pio)
+{
+   FC_MENULOG();
+   return ftp_move(pio,0);
+}
+
+
+/* FUNCTION: ftp_move()
+ * 
+ * ftp_move() - menu routine to start a file mvoe operation. Passed 
+ * flag tells us put(0) or get(1). 
+ *
+ * In multitasking environments, this function sends a message (with the
+ * various parameters from the user's request) to the FTP client task.
+ * In SUPERLOOP mode, it just directly invokes the function that uses
+ * the parameters provided to start the move.
+ *
+ * PARAM1: void * pio
+ * PARAM2: int direction
+ *
+ * RETURNS: -1 if an error occured; 0, if it initiated the move request.
+ */
+
+int
+ftp_move(void * pio, int direction)
+{
+   char *   sfile=NULL; /* name of source file to put/get */
+   char *   dfile;   /* optional name */
+   GEN_IO io= (GEN_IO) pio ;
+   unsigned long int transfer_type;
+
+   if ( ftp_get_con(pio) == NULL )
+   {
+      ns_printf(pio,"Open FTP session first\n");
+      return -1;
+   }
+
+   /* extract args from command buffer */
+   if ( io != NULL )
+      sfile = nextarg(io->inbuf);   /* name of source file */
+   if (!sfile || !*sfile)
+   {
+      ns_printf(pio,"usage: ftp put|get filename [destname]\n");
+      return -1;
+   }
+   dfile = nextarg(sfile);
+   if (dfile && *dfile) /* optional dest name given? */
+      *(dfile-1) = 0;   /* null terminate source file name */
+   else
+      dfile = sfile;    /* use foreign name for both */
+
+   if (direction) transfer_type = FTPC_GET_TRANSFER;
+   else transfer_type = FTPC_PUT_TRANSFER;
+   
+#ifdef OS_PREEMPTIVE
+   ftpc_send_msg4 (FTPC_CNTRL_MOVE_FILE, 
+                   (u_long) pio, 
+                   (u_char *) &transfer_type,
+                   sizeof (transfer_type),
+                   (u_char *) sfile,
+                   (strlen (sfile) + 1),
+                   (u_char *) dfile,
+                   (strlen (dfile) + 1));
+#else
+   ftpc_process_move (pio, transfer_type, sfile, dfile);
+#endif                   
+
+   return 0;
+}
+
+
+/* FUNCTION: ftp_asc_mode()
+ * 
+ * In multitasking environments, this function sends a message (with the
+ * filetype configuration (ASCII) from the user's request) to the FTP 
+ * client task.  In SUPERLOOP mode, it just directly invokes the function 
+ * that sets up the type of the transfer.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg2 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_asc_mode () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_asc_mode(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   unsigned long int transfer_mode = FTPTYPE_ASCII;
+
+   return (ftpc_send_msg2 (FTPC_CNTRL_TRANSFER_MODE, (u_long) pio,
+                           (u_char *) &transfer_mode, sizeof (transfer_mode)));
+#else
+   return (ftpc_process_asc_mode (pio));
+#endif   
+}
+
+
+/* FUNCTION: ftp_bin_mode()
+ * 
+ * In multitasking environments, this function sends a message (with the
+ * filetype configuration (image) from the user's request) to the FTP 
+ * client task.  In SUPERLOOP mode, it just directly invokes the function 
+ * that sets up the type of the transfer.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg2 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_asc_mode () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_bin_mode(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   unsigned long int transfer_mode = FTPTYPE_IMAGE;
+
+   return (ftpc_send_msg2 (FTPC_CNTRL_TRANSFER_MODE, (u_long) pio,
+                           (u_char *) &transfer_mode, sizeof (transfer_mode)));
+#else
+   return (ftpc_process_bin_mode (pio));
+#endif   
+}
+
+
+/* FUNCTION: ftp_hash()
+ * 
+ * In multitasking environments, this function sends a message (requesting
+ * that hashes be printed to display the progress of an ongoing file transfer) 
+ * to the FTP client task.  In SUPERLOOP mode, it just directly invokes the 
+ * function that provides the same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_hash () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_hash(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FTPC_CNTRL_HASH_PRINT, (u_long) pio));
+#else
+   return (ftpc_process_hash (pio));
+#endif
+}
+
+
+/* FUNCTION: ftp_pwd()
+ *
+ * In multitasking environments, this function sends a message (requesting
+ * the name of the current working directory at the server where the client
+ * is logged in) to the FTP client task.  In SUPERLOOP mode, it just directly 
+ * invokes the function that provides the same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_pwd () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_pwd(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FTPC_CNTRL_PWD, (u_long) pio));
+#else
+   return (ftpc_process_pwd (pio));
+#endif
+}
+
+
+/* FUNCTION: ftp_chdir()
+ *
+ * In multitasking environments, this function sends a message (requesting
+ * a change of the current working directory at the server where the client
+ * is logged in) to the FTP client task.  In SUPERLOOP mode, it just directly 
+ * invokes the function that provides the same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: -1 if a path to 'cd' to is not provided; otherwise, the return 
+ *          code from ftpc_send_msg2 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_chdir () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_chdir(void * pio)
+{
+   char *   cparm=NULL;
+   GEN_IO io= (GEN_IO) pio ;
+
+   FC_MENULOG();
+   if ( io != NULL )
+      cparm = nextarg(io->inbuf);
+   if (!cparm || !*cparm)
+   {
+      ns_printf(pio,"please specify path arg\n");
+      return -1;
+   }
+
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg2 (FTPC_CNTRL_CD, (u_long) pio, (u_char *) cparm, strlen (cparm) + 1));
+#else
+   return (ftpc_process_chdir (pio, cparm));
+#endif
+}
+
+
+/* FUNCTION: ftp_verbose()
+ * 
+ * In multitasking environments, this function sends a message (requesting
+ * that the client be verbose when displaying the state of an ongoing 
+ * transaction) to the FTP client task.  In SUPERLOOP mode, it just directly 
+ * invokes the function that provides the same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_verbose () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_verbose(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FTPC_CNTRL_VERBOSE, (u_long) pio));
+#else
+   return (ftpc_process_verbose (pio));
+#endif
+}
+
+
+/* FUNCTION: ftp_quit()
+ * 
+ * In multitasking environments, this function sends a message (requesting
+ * the termination of an ongoing FTP session) to the FTP client task.  In 
+ * SUPERLOOP mode, it just directly invokes the function that provides the 
+ * same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_quit_sess () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_quit(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FTPC_CNTRL_QUIT_FTP_SESS, (u_long) pio));
+#else
+   return (ftpc_process_quit_sess (pio));
+#endif
+}
+
+
+/* FUNCTION: ftp_list()
+ *
+ * In multitasking environments, this function sends a message (requesting
+ * a listing of the files in the current working directory at the server 
+ * where the client is logged in) to the FTP client task.  In SUPERLOOP 
+ * mode, it just directly invokes the function that provides the same 
+ * request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_list () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_list(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FTPC_CNTRL_LIST, (u_long) pio));
+#else
+   return (ftpc_process_list (pio));
+#endif
+}
+
+#ifdef NET_STATS
+
+
+/* FUNCTION: ftp_state()
+ *
+ * In multitasking environments, this function sends a message (requesting
+ * a display of the latest status of the currently open FTP session (if any)) 
+ * to the FTP client task.  In SUPERLOOP mode, it just directly invokes the 
+ * function that provides the same request to the FTP client.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Return code from ftpc_send_msg1 () for non-SUPERLOOP environments,
+ *          or the return code from ftpc_process_print_state () for SUPERLOOP
+ *          environments.
+ */
+
+int
+ftp_state(void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ftpc_send_msg1 (FPTC_CNTRL_PRINT_STATE, (u_long) pio));
+#else
+   return (ftpc_process_print_state (pio));
+#endif
+}
+#endif   /* NET_STATS */
+
+
+
+/* FUNCTION: ftp_pasv()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ftp_pasv(void * pio)
+{
+   int   e;
+   struct ftpc *  tmpcon   ;
+
+   FC_MENULOG();
+   if ( (tmpcon=ftp_get_con(pio)) == NULL )
+   {
+      ns_printf(pio,"FTP client not open\n");
+      return 0;
+   }
+
+   e = fc_pasv(tmpcon);
+   return e;
+}
+
+#ifdef FC_LOG
+/* Use of ftp_log needs some explanation.
+ * Each call to ftp_log toggles logging.  That is,
+ *    If logging is enabled, it is disabled.
+ *    If logging is disabled, it is enabled.
+ * If logging is disabled, and ftp_log is called, then 
+ *    If no arguments are passed, logging to stdio is enabled.
+ *    Else the argument is treated as filename and logging to file is enabled.
+ * If logging is enabled, and ftp_log is called, then the argument are not used.
+ * 
+ * If FC_LOGFILE is disabled, then "logging to FILE" feature is disabled.
+ * 
+ * EXAMPLE
+ * The flog command from menu prompt will invoke ftp_log().
+ * Assume that logging is disabled and FC_LOGFILE is enabled.
+ * 
+ * flog          - enables logging to stdio
+ * flog          - disables logging 
+ * flog ftp.log  - enables logging to file ftp.log
+ * flog          - disables logging 
+ * 
+ */
+#ifdef FC_LOGFILE
+char     fc_buf[FTPMAXFILE];
+
+
+/* FUNCTION: fc_file_out()
+ * 
+ * PARAM1: long s
+ * PARAM2: char *buf
+ * PARAM3: int len
+ *
+ * RETURNS: 
+ */
+
+int fc_file_out(long s, char * buf, int len)
+{
+   VFILE *fp = (VFILE *)s;
+
+   vfwrite(buf,len,1,fp);
+   return len;
+}
+
+struct GenericIO  fc_file_io  =  {  fc_buf,  fc_file_out,   0, NULL  }  ;
+#endif   /*FC_LOGFILE */
+
+
+
+/* FUNCTION: ftp_log()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ftp_log(void * pio)
+{
+
+   FC_MENULOG();
+   if (log_flag==TRUE)
+   {
+      /* Logging is enabled. Disable it */
+      log_flag=FALSE;
+#ifdef FC_LOGFILE
+      if (ftplog)
+      {
+         ns_printf(pio, "Logging to file disabled\n");
+         vfclose((VFILE *)fc_file_io.id);
+      }
+      else
+#endif   /*FC_LOGFILE */
+      ns_printf(pio, "Logging to STDIO disabled\n");
+   }
+   else
+   {
+      /* Logging is disabled. Enable it. If an argument is passed, 
+       * then it is name of logfile. Hence enable logging to file. If 
+       * no argument is passed, then enable logging to stdio. 
+       */
+#ifdef FC_LOGFILE
+      char *   filename=NULL;
+      GEN_IO   io= (GEN_IO) pio ;
+      VFILE *  fp;
+#endif   /*FC_LOGFILE */
+
+      log_flag=TRUE;
+      ftplog   =NULL;   /* By default log to stdio */     
+
+#ifdef FC_LOGFILE
+      /* extract args from command buffer */
+      if ( io != NULL )
+      {
+         filename = nextarg(io->inbuf);
+         if(*filename != 0)   /* user passed file name */
+         {
+            fp=vfopen(filename, "w");
+            if (fp==NULL)
+            {
+               ns_printf(pio, "Can't open file %s.", filename);
+            }
+            else
+            {
+               fc_file_io.id  = (long)fp;
+               ftplog   =  &fc_file_io;
+            }
+         }
+      }
+
+      if (ftplog)
+         ns_printf(pio, "Logging to file %s enabled\n", filename);
+      else
+#endif   /*FC_LOGFILE */
+      ns_printf(pio, "Logging to STDIO enabled\n");
+   }
+
+   return   0;
+}
+#endif   /* FC_LOG */
+
+
+
+#ifdef OS_PREEMPTIVE
+/* utility functions to send messages with zero or more parameters to the FTP client task */
+
+/* FUNCTION: ftpc_send_msg1 ()
+ *
+ * This function sends a zero- or one-parameter message to the FTP client task.  
+ * The list of messages that use this function include:
+ *
+ * FTPC_CNTRL_QUIT_FTP_SESS
+ * FTPC_CNTRL_VERBOSE
+ * FTPC_CNTRL_HASH_PRINT
+ * FTPC_CNTRL_PWD
+ * FTPC_CNTRL_LIST
+ * FPTC_CNTRL_PRINT_STATE
+ * FTPC_CNTRL_PERIODIC_TIMER (zero parameters; 'pio' arg is ignored)
+ *
+ * INPUT: (1) Type of message to be sent (FTPC_CNTRL_QUIT_FTP_SESS, etc.)
+ *        (2) Pointer to generic IO structure from where request originated
+ *
+ * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise.
+ */
+
+int ftpc_send_msg1 (u_long type, u_long pio)
+{
+   struct ftpctask_msg * msgp;
+
+   msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg));
+   if (!msgp)
+   {
+      ++ftpc_err.alloc_fail;
+      return -1;
+   }
+   
+   msgp->type = type;
+   msgp->pio = pio;
+
+   /* send message to FTP client task */
+   LOCK_NET_RESOURCE (FTPCQ_RESID);
+   putq(&ftpcq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (FTPCQ_RESID);
+
+   post_app_sem (FTPC_SEMID);
+
+   return 0;
+}
+
+
+/* FUNCTION: ftpc_send_msg2 ()
+ *
+ * This function sends a two-parameter message to the FTP client task.  
+ * The list of messages that use this function include:
+ *
+ * FTPC_CNTRL_TRANSFER_MODE
+ * FTPC_CNTRL_CD
+ *
+ * INPUT: (1) Type of message to be sent (FTPC_CNTRL_TRANSFER_MODE, etc.)
+ *        (2) Pointer to generic IO structure from where request originated
+ *        (3) Pointer to second parameter (in the message for the FTP client task)
+ *        (4) Length of second parameter (starting at 'argp')
+ *
+ * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise.
+ */
+
+int ftpc_send_msg2 (u_long type, u_long pio, u_char * argp, u_long arglen)
+{
+   struct ftpctask_msg * msgp;
+
+   msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arglen);
+   if (!msgp)
+   {
+      ++ftpc_err.alloc_fail;
+      return -1;
+   }
+   
+   msgp->type = type;
+   msgp->pio = pio;
+   memcpy (msgp->parms, argp, arglen);
+
+   /* send message to FTP client task */
+   LOCK_NET_RESOURCE (FTPCQ_RESID);
+   putq(&ftpcq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (FTPCQ_RESID);
+
+   post_app_sem (FTPC_SEMID);
+
+   return 0;
+}
+
+
+/* FUNCTION: ftpc_send_msg4 ()
+ *
+ * This function sends a four-parameter message to the FTP client task.  
+ * The list of messages that use this function include:
+ *
+ * FTPC_CNTRL_MOVE_FILE
+ *
+ * INPUT: (1) Type of message to be sent (FTPC_CNTRL_MOVE_FILE)
+ *        (2) Pointer to generic IO structure from where request originated
+ *        (3) Pointer to second parameter (in the message for the FTP client task)
+ *        (4) Length of second parameter (starting at 'arg1p')
+ *        (5) Pointer to third parameter (in the message for the FTP client task)
+ *        (6) Length of third parameter (starting at 'arg2p')
+ *        (7) Pointer to fourth parameter (in the message for the FTP client task)
+ *        (8) Length of fourth parameter (starting at 'arg3p')
+ *
+ * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise.
+ */
+
+int ftpc_send_msg4 (u_long type, 
+                    u_long pio, 
+                    u_char * arg1p, 
+                    u_long arg1len,
+                    u_char * arg2p, 
+                    u_long arg2len,
+                    u_char * arg3p, 
+                    u_long arg3len)
+{
+   struct ftpctask_msg * msgp;
+   unsigned char * startp;
+
+   msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arg1len + arg2len + arg3len);
+   if (!msgp)
+   {
+      ++ftpc_err.alloc_fail;
+      return -1;
+   }
+   
+   msgp->type = type;
+   msgp->pio = pio;
+   startp = &(msgp->parms[0]);
+   memcpy (startp, arg1p, arg1len);
+   memcpy (startp + arg1len, arg2p, arg2len);
+   memcpy (startp + arg1len + arg2len, arg3p, arg3len);
+
+   /* send message to FTP client task */
+   LOCK_NET_RESOURCE (FTPCQ_RESID);
+   putq(&ftpcq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (FTPCQ_RESID);
+
+   post_app_sem (FTPC_SEMID);
+
+   return 0;
+}
+
+
+/* FUNCTION: ftpc_send_msg5 ()
+ * 
+ * This function is used to send a five-parameter message to the FTP client task.
+ *
+ * FTPC_CNTRL_START_SESS
+ *
+ * INPUT: (1) Type of message to be sent (FTPC_CNTRL_MOVE_FILE)
+ *        (2) Pointer to generic IO structure from where request originated
+ *        (3) Pointer to second parameter (in the message for the FTP client task)
+ *        (4) Length of second parameter (starting at 'arg1p')
+ *        (5) Pointer to third parameter (in the message for the FTP client task)
+ *        (6) Length of third parameter (starting at 'arg2p')
+ *        (7) Pointer to fourth parameter (in the message for the FTP client task)
+ *        (8) Length of fourth parameter (starting at 'arg3p')
+ *        (9) Pointer to fifth parameter (in the message for the FTP client task)
+ *        (A) Length of fifth parameter (starting at 'arg4p')
+ *
+ * OUTPUT: -1, if storage for the message could not be allocated; 0, otherwise.
+ */
+
+int ftpc_send_msg5 (u_long type, 
+                    u_long pio, 
+                    u_char * arg1p,  /* address */
+                    u_long arg1len,
+                    u_char * arg2p,  /* domain */
+                    u_long arg2len,
+                    u_char * arg3p,  /* username */
+                    u_long arg3len,
+                    u_char * arg4p,  /* password */
+                    u_long arg4len)
+{
+   struct ftpctask_msg * msgp;
+   unsigned char * startp;
+
+   msgp = (struct ftpctask_msg *) FTPC_ALLOC (sizeof (struct ftpctask_msg) + arg1len + arg2len + arg3len + arg4len);
+   if (!msgp)
+   {
+      ++ftpc_err.alloc_fail;
+      return -1;
+   }
+   
+   msgp->type = type;
+   msgp->pio = pio;
+   startp = &(msgp->parms[0]);
+   memcpy (startp, arg1p, arg1len);
+   memcpy (startp + arg1len, arg2p, arg2len);
+   memcpy (startp + arg1len + arg2len, arg3p, arg3len);
+   memcpy (startp + arg1len + arg2len + arg3len, arg4p, arg4len);
+
+   /* send message to FTP client task */
+   LOCK_NET_RESOURCE (FTPCQ_RESID);
+   putq(&ftpcq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (FTPCQ_RESID);
+
+   post_app_sem (FTPC_SEMID);
+
+   return 0;
+}
+#endif /* OS_PREEMPTIVE */
+
+
+/* FUNCTION: ftpc_periodic_timer ()
+ *
+ * This function is invoked from timer task (tk_nettick), and is responsible for
+ * moving the file transfer to completion.
+ *
+ * INPUT: None.
+ * OUTPUT: None.
+ */
+
+void ftpc_periodic_timer (void)
+{
+#ifdef OS_PREEMPTIVE
+   /* the second ('pio') parameter is irrelevant */
+   ftpc_send_msg1(FTPC_CNTRL_PERIODIC_TIMER, 0);
+#else
+   fc_check();
+#endif   
+}
+
+#endif /* FTP_CLIENT */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h
new file mode 100644
index 0000000..039e955
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpport.h
@@ -0,0 +1,128 @@
+/*
+ * FILENAME: FTPPORT.H
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES:
+ *
+ * PORTABLE: yes
+ */
+
+/* ftpport.h FTP server's per-port definitions. 
+ * 1/12/97 - Created as part of cleanup. John Bartas 
+ */
+
+#ifndef _FTPPORT_H_
+#define  _FTPPORT_H_    1
+
+#include "ipport.h"
+#include "libport.h"
+#include "tcpapp.h"
+#include "userpass.h"
+
+/* Implementation defines: */
+#define  FTPMAXPATH     168   /* max path length, excluding file name */
+#define  FTPMAXFILE     16    /* max file name length w/o path */
+#define CMDBUFSIZE      256
+/* #define  CMDBUFSIZE     1024  // Texas Imperial Sw's WFTD sends a BIG welcome str */
+
+
+#ifndef FILEBUFSIZE     /* Allow override from ipport.h */
+#define  FILEBUFSIZE    (6*1024)
+#endif   /* FILEBUFSIZE */
+
+
+#ifdef MAX_USERLENGTH
+#define  FTPMAXUSERNAME    MAX_USERLENGTH
+#define  FTPMAXUSERPASS    MAX_USERLENGTH
+#else
+#define  FTPMAXUSERNAME    32
+#define  FTPMAXUSERPASS    24
+#endif
+
+/* default port for FTP data transfers. This can default to 20 (as 
+ * some interpret the RFC as recommending) or default to 0 to let the 
+ * sockets layer pick a port randomly. It could even point to a user 
+ * provided routine which determines a port number alogrithmically.
+ */
+#define  FTP_DATAPORT      20
+
+
+/* set up file system options for target system */
+
+#ifdef UNIX_VFS
+#define  FTP_SLASH   '/'   /* use UNIX style slash */
+#else
+#if ((!defined(AMD_NET186)) && (!defined(ACE_360)) && (!defined(ARM_PID)))
+#define  DRIVE_LETTERS     1     /* track drive as well as directory */
+#endif
+#define  DEFAULT_DRIVE   "c:"
+#define  FTP_SLASH   '\\'     /* use DOS style slash */
+#endif
+
+/* define clock tick info for DOS */
+#define  FTPTPS   TPS      /* number of ftps_loop calls per second */
+#define  ftpticks cticks
+
+
+#ifdef MINI_TCP   /* mini-sockets */
+/* Set the type of indentifier sockets will have */
+#define  SO_GET_FPORT(so) (((M_SOCK)so)->fport)
+#define  SO_GET_LPORT(so) (((M_SOCK)so)->lport)
+#else    /* not MINI_TCP, use BSDish sockets */
+unshort  SO_GET_FPORT(WP_SOCKTYPE so);
+unshort  SO_GET_LPORT(WP_SOCKTYPE so);
+#endif
+
+
+/* Added sys_ routines for FTP support */
+SOCKTYPE t_tcplisten(u_short * lport, int doamin);
+SOCKTYPE t_tcpopen(ip_addr host, u_short lport, u_short fport);
+
+
+/* define number of read-sends to do per ftp_check(). For best 
+ * performance, this times the FILEBUFSIZE should be about equal 
+ * to anicipated TCP window.
+ */
+#ifndef MAXSENDLOOPS    /* allow tuning from ipport.h */
+#ifdef TCP_ZEROCOPY
+#define  MAXSENDLOOPS   12 /* MAX number of loops */
+#else
+#define  MAXSENDLOOPS   1  /* MAX number of loops */
+#endif   /* not TCP_ZEROCOPY */
+#endif   /* no MAXSENDLOOPS */
+
+/* Configurable limit on max number of ftp sessions.  Setting this value to 0 or
+ * -1 results in no limitation on number of sessions.  The default value is 32.
+ */
+#ifndef MAX_FTPS_SESS   /* allow tuning from ipport.h */
+#define MAX_FTPS_SESS 32
+#endif  /* MAX_FTPS_SESS */
+
+/* map ftp's timer tick count to system's */
+#define  ftp_ticks   cticks
+
+/* map FTP server's alloc and free to local mem library */
+#define  FTPSALLOC(size)   npalloc(size)
+#define  FTPSFREE(ptr)     npfree(ptr)
+
+/* FTP Client related non-volatile parameters. Please see nvparms.h 
+ * and nvparms.c regarding the usage of the following structure.
+ */
+#ifdef INCLUDE_NVPARMS
+#ifdef FTP_CLIENT
+struct ftpc_nvparam
+{
+   int  fc_replytmo    ;  /* secs of inactivity (for a cmd) for timeout*/
+   int  fc_activity_tmo;  /* ftp client's inactivity timeout (secs) */
+};
+
+extern struct ftpc_nvparam ftpc_nvparms;
+#endif /* FTP_CLIENT */
+#endif /* INCLUDE_NVPARMS */
+
+#endif   /* _FTPPORT_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c
new file mode 100644
index 0000000..abfc932
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsport.c
@@ -0,0 +1,535 @@
+/*
+ * FILENAME: ftpsport.c
+ *
+ * Copyright  2000-2008 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTPSERVER
+ *
+ * ROUTINES: ftps_init(), ftps_check(), fs_lookupuser(), 
+ * ROUTINES: ftps_cleanup(), 
+ *
+ * PORTABLE: no
+ */
+
+/* Additional Copyrights: */
+
+/* ftpsport.c 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * The Port-dependant portion of the FTP Server code. 11/24/96 - 
+ * Created by John Bartas 
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+#include "ftpsrv.h"
+
+#ifndef SUPERLOOP
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+#include OSPORT_H
+#endif /* SUPERLOOP */
+
+struct sockaddr_in   ftpssin;
+
+#ifdef IP_V4
+SOCKTYPE ftps_sock = SYS_SOCKETNULL;
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+SOCKTYPE ftps_sock6 = SYS_SOCKETNULL;
+#endif   /* IP_V6 */
+
+
+#ifdef MINI_TCP
+#include "msring.h"
+#ifndef FTPS_NEWQLEN
+#define FTPS_NEWQLEN    4      /* max # buffered new connections */
+#endif /* ndef FTPS_NEWQLEN */
+struct msring ftps_msring;
+static M_SOCK ftps_msring_buf[FTPS_NEWQLEN + 1];
+#endif /* MINI_TCP */
+
+
+#if (defined(FTP_CLIENT) && defined(INCLUDE_NVPARMS))
+#include "nvparms.h"
+extern int  fc_replytmo    ;  /* secs of inactivity (for a cmd) for timeout*/
+extern int  fc_activity_tmo;  /* ftp client's inactivity timeout (secs) */
+#endif
+
+#ifdef FTP_SERVER
+extern int  ftps_init(void);
+extern void ftps_cleanup(void);
+extern void ftps_check(void);
+#endif
+
+
+
+/* FUNCTION: ftps_init()
+ * 
+ * ftps_init() - this is called by the ftp server demo package once 
+ * at startup time. It initializes the vfs and opens a tcp socket to 
+ * listen sfor web connections 
+ *
+ * If FTP_CLIENT and INCLUDE_NVPARMS are both enabled, then we need to
+ * change a couple of FTP_CLIENT parameters to that in the NV file.
+ *
+ * PARAM1: 
+ *
+ * RETURNS: Returns 0 if OK, non-zero if error. 
+ */
+
+int
+ftps_init()
+{
+   unshort  port;
+   int      opens = 0;
+
+   /* add default users for this port */
+   /* anonymous makes you enter a password, we just don't care what it is */
+   add_user("anonymous", "*", NULL);
+   add_user("guest", "guest", NULL);
+
+   port = FTP_PORT;
+
+#ifdef IP_V4
+   ftps_sock = t_tcplisten(&port, AF_INET);
+   if (ftps_sock == SYS_SOCKETNULL)
+      dprintf("FTP server: unable to start listen\n");
+   else
+      opens++;
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+   ftps_sock6 = t_tcplisten(&port, AF_INET6);
+   if (ftps_sock6 == SYS_SOCKETNULL)
+      dprintf("FTP server: unable to start IPv6 listen\n");
+   else
+      opens++;
+#endif   /* IP_V6 */
+
+   if (opens == 0)
+      return -1;
+
+#ifdef MINI_TCP
+   msring_init(&ftps_msring, ftps_msring_buf,
+               sizeof(ftps_msring_buf) / sizeof(ftps_msring_buf[0]));
+#endif /* MINI_TCP */
+
+#if (defined(FTP_CLIENT) && defined(INCLUDE_NVPARMS))
+   /* So the following code is included only when an NVFS exists. */
+
+   if (ftpc_nvparms.fc_replytmo > 0)
+      fc_replytmo = ftpc_nvparms.fc_replytmo ;
+
+   if (ftpc_nvparms.fc_activity_tmo > 0)
+      fc_activity_tmo = ftpc_nvparms.fc_activity_tmo ;
+
+#endif /* FTP_CLIENT & INCLUDE_NVPARMS */
+
+   return 0;
+}
+
+#ifndef MINI_TCP
+
+/* Accept a new FTP command connection
+ *
+ * Returns 0 if OK, or ENP error code 
+ */
+
+int
+ftp_accept(int domain, SOCKTYPE ftps_sock, int clientlen)
+{
+   SOCKTYPE socktmp;
+   struct sockaddr client;
+   int   err;
+   ftpsvr * ftps;
+
+   socktmp = t_accept(ftps_sock, &client, &clientlen);
+   if (socktmp != SYS_SOCKETNULL)
+   {
+      ftps = ftps_connection(socktmp);
+      if (ftps == NULL)
+         return ENP_NOMEM;    /* most likely problem */
+      ftps->domain = domain;
+   }
+   else
+   {
+      err = t_errno(ftps_sock);
+      if (err != EWOULDBLOCK)
+      {
+         return err;
+      }
+   }
+   return 0;
+}
+#endif   /* ndef MINI_TCP */
+
+
+/* FUNCTION: ftps_check()
+ * 
+ * ftp server task loop. For the PC DOS demo, this is called once 
+ * every main task loop. 
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+static int in_ftps_check = 0;    /* reentry guard */
+
+void
+ftps_check()
+{
+#ifdef MINI_TCP
+   SOCKTYPE  socktmp;
+#endif
+
+   in_ftps_check++;
+   if (in_ftps_check != 1)
+   {
+      in_ftps_check--;
+      return;
+   }
+
+#ifdef MINI_TCP
+
+   while (msring_del(&ftps_msring, &socktmp) == 0)
+   {
+      ftpsvr *e;
+      
+      e = ftps_connection(socktmp);
+      if (e == (ftpsvr *)NULL)
+      {
+         dprintf("ftp connection error\n");
+         continue;
+      }
+      m_ioctl(socktmp, SO_NONBLOCK, NULL);  /* make socket non-blocking */
+   }
+
+#ifndef SUPERLOOP
+   {
+      struct sockaddr_in   client;
+      int      block = TRUE;    /* flag to block FTP server task */
+      ftpsvr * ftp;
+
+      /* loop through ftp structs to see if it's OK to block task */
+      for (ftp = ftplist; ftp; ftp = ftp->next)
+      {
+         /* The ftp data sending and receiving states can hang if we  
+          * block the thread. If any session is in this state then 
+          * clear the block flag to avoid this.
+          */
+         if ((ftp->state == FTPS_SENDING) ||
+            (ftp->state == FTPS_RECEIVING))
+         {
+            block = FALSE;    /* don't block server task */
+            break;            /* no need to check any more sessions */
+         }
+      }
+      if (block)         /* flag should now be set */
+         TK_BLOCK();    /* sleep until a callback wakes us */
+   }
+#endif   /* SUPERLOOP */
+   /* nothing to do in the MINI_TCP & SUPERLOOP case since connects
+    * are callback driven and the superloop will poll us anyway.
+    */
+#elif defined(BLOCKING_APPS)  /* use blocking select to drive server app */
+   {
+      fd_set ftp_fdrecv;
+      fd_set ftp_fdsend;
+      ftpsvr *ftp;
+      int events;             /* return from select() */
+#ifndef USE_FDS
+      int recvs = 0;          /* number of entries in recv FD_SET array */
+      int sends = 0;
+#endif
+#ifdef FTP_IDLECONN_TMO
+      extern int    ftps_iotmo;     /* idle time in BLOCKING_APPS mode */
+#endif /* FTP_IDLECONN_TMO */
+
+#ifdef USE_FDS
+      FD_ZERO(&ftp_fdrecv);
+      FD_ZERO(&ftp_fdsend);
+#else
+      MEMSET(&ftp_fdrecv, 0, sizeof(fd_set));
+      MEMSET(&ftp_fdsend, 0, sizeof(fd_set));
+#endif  /* USE_FDS */
+
+      /* use the recv array to detect new connections */
+
+#ifdef IP_V4
+      if (ftps_sock != SYS_SOCKETNULL)
+      {
+         FD_SET(ftps_sock, &ftp_fdrecv);
+#ifndef USE_FDS
+         recvs++;
+#endif
+      }
+#endif
+#ifdef IP_V6
+      if (ftps_sock6 != SYS_SOCKETNULL)
+      {
+         FD_SET(ftps_sock6, &ftp_fdrecv);
+#ifndef USE_FDS
+         recvs++;
+#endif
+      }
+#endif
+
+      /* If no listening sockets, don't bother */
+#ifdef USE_FDS
+      if (FD_COUNT(&ftp_fdrecv) == 0)
+         return;
+#else
+      if (recvs == 0)
+         return;
+#endif  /* USE_FDS */
+
+      /* loop through ftp structs building read/write arrays for select */
+      for (ftp = ftplist; ftp; ftp = ftp->next)
+      {
+      /* add ftp server's open sockets to the FD lists based on
+       * their state. The server thread will block until one of
+       * these has activity.
+       */
+#ifdef USE_FDS
+         /* error checking is done in FD_SET */
+#else
+         if ((recvs > FD_SETSIZE) || (sends > FD_SETSIZE))
+         {
+            dtrap();    /* port needs bigger FD_SETSIZE */
+            break;      /* no point in looping any more */
+         }
+#endif  /* USE_FDS */
+
+         FD_SET(ftp->sock, &ftp_fdrecv);
+#ifndef USE_FDS
+         recvs++;
+#endif
+         if (ftp->datasock && (ftp->datasock != SYS_SOCKETNULL))
+         {
+            /* always add the data socket to the receive FD_SET */
+            FD_SET(ftp->datasock, &ftp_fdrecv);
+#ifndef USE_FDS
+            recvs++;
+#endif
+            /* only add the send socket if we are actively sending */
+            if (ftp->state == FTPS_SENDING)
+            {
+               FD_SET(ftp->datasock, &ftp_fdsend);
+#ifndef USE_FDS
+               sends++;
+#endif
+            }
+         }
+      }  /* end of for(ftplist) loop */
+
+      /* block until one of the sockets has activity */
+#ifndef FTP_IDLECONN_TMO
+      events = t_select(&ftp_fdrecv, &ftp_fdsend, (fd_set *)NULL, -1);
+#else /* do not block idle time, enable inactivity timeout */
+      events = t_select(&ftp_fdrecv, &ftp_fdsend, (fd_set *)NULL,
+                        (unsigned long)ftps_iotmo * FTPTPS); 
+#endif /* FTP_IDLECONN_TMO */
+
+#ifdef IP_V4
+      if (FD_ISSET(ftps_sock, &ftp_fdrecv))  /* got a connect to server listen? */
+      {
+         ftp_accept(AF_INET, ftps_sock, sizeof(struct sockaddr_in));
+         events--;
+      }
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+      if (FD_ISSET(ftps_sock6, &ftp_fdrecv))  /* got a connect v6 listen? */
+      {
+         ftp_accept(AF_INET6, ftps_sock6, sizeof(struct sockaddr_in6));
+         events--;
+      }
+#endif   /* IP_V6 */
+
+      if (events <= 0)  /* connect was only socket */
+      {
+         in_ftps_check--;
+         return;
+      }
+   }
+#else /* not BLOCKING_APPS, poll non-blocking sockets */
+
+#ifdef IP_V4
+   if (ftps_sock != SYS_SOCKETNULL)
+      ftp_accept(AF_INET, ftps_sock, sizeof(struct sockaddr_in));
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+   if (ftps_sock6 != SYS_SOCKETNULL)
+      ftp_accept(AF_INET6, ftps_sock6, sizeof(struct sockaddr_in6));
+#endif   /* IP_V6 */
+
+#endif   /* BLOCKING_APPS */
+
+   /* work on existing conections - data or command */
+   ftps_loop();
+
+   in_ftps_check--;
+   return;
+}
+
+
+
+
+/* FUNCTION: fs_lookupuser()
+ * 
+ * fs_lookupuser() lookup a user based on the name. Fill in user 
+ * struct in ftp, including password. If no password required, fill 
+ * in null string. Filled in data is in unencrypted form. This 
+ * particular port is for the user database in ..\misclib\userpass.c 
+ * 
+ * PARAM1: ftpsvr * ftp
+ * PARAM2: char * username
+ *
+ * RETURNS: Returns 0 if user found, else -1 if user invalid. 
+ */
+
+int
+fs_lookupuser(ftpsvr * ftp, char * username)
+{
+   int   i;
+
+   for (i = 0; i < NUM_NETUSERS; i++)
+   {
+      if (users[i].username[0] == 0)
+         continue;
+      if (strcmp(users[i].username, username) == 0)
+         break;
+   }
+
+   if (i >= NUM_NETUSERS)  /* username not found? */
+      return -1;
+
+   /* extract username from command  */
+   strncpy(ftp->user.username, username, FTPMAXUSERNAME);
+   strncpy(ftp->user.password, users[i].password, FTPMAXUSERPASS);
+   strcpy(ftp->user.home, "c:\\");  /* default for DOS port */
+   return 0;
+}
+
+void  delftp(ftpsvr * ftp);
+
+
+/* FUNCTION: ftps_cleanup()
+ * 
+ * Close down all the connections to FTP Server. Then close the
+ * socket used for FTP Server listen 
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void 
+ftps_cleanup(void)
+{
+   ftpsvr * ftp;
+   ftpsvr * ftpnext;
+
+   ftpnext = ftplist;   /* will be set to ftp at top of loop */
+
+   /* loop throught connection list */
+   while (ftpnext)
+   {
+      ftp = ftpnext;
+      ftpnext = ftp->next;   
+      delftp(ftp);   /* kill the connection */
+   }
+
+#ifdef IP_V4
+   if ( ftps_sock != INVALID_SOCKET )
+   {
+      sys_closesocket(ftps_sock);
+      ftps_sock = INVALID_SOCKET ;     
+   }
+#endif
+
+#ifdef IP_V6
+   if ( ftps_sock6 != INVALID_SOCKET )
+   {
+      sys_closesocket(ftps_sock6);
+      ftps_sock6 = INVALID_SOCKET ;     
+   }
+#endif
+}
+
+
+#ifndef SUPERLOOP
+
+#ifdef FTP_SERVER
+
+TK_OBJECT(to_ftpsrv);
+TK_ENTRY(tk_ftpsrv);
+long ftpsrv_wakes   =  0;
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Use task priority and stack size values from ipport.h
+ */
+struct inet_taskinfo ftpstask = {
+      &to_ftpsrv,
+      "FTP server",
+      tk_ftpsrv,
+      TK_FTPSRVR_TPRIO,
+      TK_FTPSRVR_SSIZE,
+};
+
+
+/* The application thread works on a "controlled polling" basis:
+ * it wakes up periodically and polls for work. If there is outstanding
+ * work, the next wake is accellerated to give better performance under
+ * heavy loads.
+ *
+ * The FTP task could aternativly be set up to use blocking sockets,
+ * in which case the loops below would only call the "xxx_check()"
+ * routines - suspending would be handled by the TCP code.
+ */
+
+/* FUNCTION: tk_ftpsrv()
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+TK_ENTRY(tk_ftpsrv)
+{
+   int e;
+
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+   e = ftps_init();
+   if (e)
+      TK_RETURN_ERROR();
+   exit_hook(ftps_cleanup);
+
+   for (;;)
+   {
+      ftps_check();     /* may block on select */
+#ifndef BLOCKING_APPS
+      tk_yield();       /* give up CPU if it didn't block */
+#else
+#ifdef MINI_TCP
+      tk_yield();       /* give up CPU, MINI_TCP doesn't select() */
+#endif   /* MINI_TCP */
+#endif   /* BLOCKING_APPS */
+      ftpsrv_wakes++;   /* count wakeups */
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+
+#endif   /* FTP_SERVER */
+
+#endif /* SUPERLOOP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c
new file mode 100644
index 0000000..969b47d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.c
@@ -0,0 +1,2061 @@
+/*
+ * FILENAME: ftpsrv.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTPSERVER
+ *
+ * ROUTINES: ftps_connection(), ftpputs(), ftp_getcmd(), 
+ * ROUTINES: ftp_flushcmd(), ftps_loop(), newftp(), delftp(), ftps_user(), 
+ * ROUTINES: ftps_password(), ftp_cmdpath(), ftp_make_filename()
+ * ROUTINES: ftp_leave_passive_state(), ftps_do_pasv(), ftps_cmd(),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+#include "ftpsrv.h"     /* FTP server includes */
+
+static u_long   max_ftps_conn = MAX_FTPS_SESS;
+
+u_long   ftps_connects  =  0; /* TCP connections tocmd port */
+u_long   ftps_sessions  =  0; /* user & password OK */
+u_long   ftps_badauth   =  0; /* user or password badK */
+u_long   ftps_txfiles   =  0; /* total data files sent */
+u_long   ftps_rxfiles   =  0; /* total data files received */
+u_long   ftps_txbytes   =  0; /* total data bytes received */
+u_long   ftps_rxbytes   =  0; /* total data bytes sent */
+u_long   ftps_dirs      =  0; /* total directory operations done */
+
+/* ftp server internal routines: */
+static int  ftp_getcmd(ftpsvr * ftp);
+static void ftp_flushcmd(ftpsvr * ftp);
+
+ftpsvr * newftp(void);
+void  delftp(ftpsvr * ftp);
+int   ftps_user(ftpsvr * ftp);
+int   ftps_password(ftpsvr * ftp);
+int   ftps_cmd(ftpsvr * ftp);
+int   ftp_sendfile(ftpsvr * ftp);
+int   ftp_getfile(ftpsvr * ftp);
+void  ftp_xfercleanup(ftpsvr * ftp);
+
+/* common FTP server reply tokens */
+char * ftp_cmdok   = "200 Command OK\r\n";
+char * ftp_ready   = "220 Service ready\r\n";
+char * ftp_needpass= "331 User name ok, need password\r\n";
+char * ftp_loggedin= "230 User logged in\r\n";
+char * ftp_fileok  = "150 File status okay; about to open data connection\r\n";
+char * ftp_closing = "226 Closing data connection, file transfer successful\r\n";
+char * ftp_badcmd  = "500 Unsupported command\r\n";
+char * ftp_noaccess= "550 Access denied\r\n";
+
+ftpsvr * ftplist   = NULL;   /* master list of FTP connections */
+
+int    notfatal    = 0;      /* unfatal error handling */
+
+/* ftp server timeouts, left as globals for app overrides: */
+int    ftps_iotmo  =  120;  /* Idle timeout during IO activity */
+int    ftps_lotmo  =  60;   /* Idle timeout during logins */
+
+#ifdef FTP_IDLECONN_TMO
+int    ftps_conntmo  = 0;   /* connection idle timeout, 0==no timeout */
+#endif
+
+
+/* if x is an upper case letter, this evaluates to x,
+ *  if x is a lower case letter, this evaluates to the upper case.
+ */
+#define  upper_case(x)  ((x)  &  ~0x20)
+
+u_short  listcmds =  0; /* number of LIST or DIR commands */
+
+#ifndef SUPERLOOP
+extern   TK_OBJECT(to_ftpsrv);
+#endif
+
+
+/* FUNCTION: ftps_connection()
+ * 
+ * ftps_connection() - Called whenever we have accepted a connection 
+ * on the FTP server listener socket. The socket passed will stay 
+ * open until we close it. 
+ *
+ * PARAM1: WP_SOCKTYPE sock
+ *
+ * RETURNS: Returns ftpsvr pointer if OK, else NULL
+ */
+
+ftpsvr *
+ftps_connection(SOCKTYPE sock)
+{
+   ftpsvr * ftp;
+   int   e;
+
+   ftps_connects++;           /* count connections */
+   
+   /* check if we have exceeded the maximum number of connections */
+   if ((max_ftps_conn > 0) && (ftps_connects > max_ftps_conn))
+   {
+      ftps_connects--;
+      t_socketclose(sock);
+      return NULL;
+   }
+
+   /* create new FTP connection */
+   if ((ftp = newftp()) == (ftpsvr *)NULL)
+   {
+      ftps_connects--;
+      t_socketclose(sock);
+      return NULL;
+   }
+
+   /* set the default data port we will connect to for data transfers 
+    * to be the same as the port that the client connected with just 
+    * in case we connect to a client that doesn't send PORT commands. 
+    * see section 3.2 ESTABLISHING DATA CONNECTIONS in RFC 959 for a 
+    * description of this, keeping in mind that what we are doing 
+    * here is setting the default "user-process data port". 
+    * 
+    * note that t_getpeername() can in theory fail, but its not clear 
+    * what we could do at this point to recover if it did and it only 
+    * makes a difference if we connect to clients that don't send 
+    * PORT commands anyway, so just use whatever port that we get back 
+    */
+   ftp->dataport = SO_GET_FPORT(sock);
+
+   ftp->sock = sock;    /* remember client socket */
+   ftp->state = FTPS_CONNECTING;
+   e = t_send(ftp->sock, ftp_ready, strlen(ftp_ready), 0);
+   if (e == -1)   /* did connection die already? */
+   {
+      dtrap();
+      delftp(ftp);
+      return NULL;
+   }
+
+   return ftp;
+}
+
+
+
+/* FUNCTION: ftpputs()
+ * 
+ * ftpputs() - put a string to an ftp command socket. 
+ *
+ * PARAM1: ftpsvr * ftp
+ * PARAM2: char * text
+ *
+ * RETURNS: Retuns 0 if OK -1 if error. ftpsvr is deleted on error. 
+ */
+
+int
+ftpputs(ftpsvr * ftp, char * text)
+{
+   int   bytes_to_send;
+   int   bytes_sent;
+   int   rc;
+
+   bytes_to_send = strlen(text);
+   for (bytes_sent = 0; bytes_to_send > 0; )
+   {
+      rc = t_send(ftp->sock, text + bytes_sent, bytes_to_send, 0);
+      if (rc < 0)
+      {
+         rc = t_errno(ftp->sock);
+         dtrap();       /* show errors to programmer */
+         ftp->state = FTPS_CLOSING;
+         return -1;
+      }
+      bytes_to_send -= rc;
+      bytes_sent += rc;
+      if (bytes_to_send > 0)
+         tk_yield();
+   }
+   /* bytes_to_send should end up 0 */
+   if (bytes_to_send < 0)
+   {
+      dtrap();
+   }
+   return 0;
+}
+
+#define  FTP_HASCMD     1
+#define  FTP_NOCMD      2
+#define  FTP_ERROR      3
+
+
+
+/* FUNCTION: ftp_getcmd()
+ * 
+ * ftp_getcmd() - Get a command from the ftp command stream. Trys to 
+ * read more data from a ftp client sock until a command is buffered. 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: FTP_HASCMD if a command is ready at ftp->cmdbuf, else 
+ * FTP_NOCMD if a command is not ready, or FTP_ERROR if there's a 
+ * serious data problem. If FTP_HASCMD is returned and the caller 
+ * processes the command, he should call ftp_flushcmd() so the 
+ * command doen't get processed again. 
+ */
+
+static int
+ftp_getcmd(ftpsvr * ftp)
+{
+   int   readval;
+   int   e;
+   char *   cp;
+
+   /* if we filled up the input buffer on the last pass and there was
+      no CRLF terminating a command in any of it */
+   if (ftp->cmdbuflen >= (CMDBUFSIZE - 1))
+   {
+      /* the input is bogus so discard it */
+      ftp->cmdbuflen = 0;
+   }
+
+   /* read as much data as will fit into the command buffer, leaving 
+    * room for the NULL that we are going to insert following the 
+    * first CRLF, below
+    */
+
+   readval = t_recv(ftp->sock, (ftp->cmdbuf + ftp->cmdbuflen), 
+    (CMDBUFSIZE - ftp->cmdbuflen - 1), 0);
+
+   if (readval == 0)
+      ftp->state = FTPS_CLOSING;
+
+   if (readval < 0)  /* error on socket? */
+   {
+      e = t_errno(ftp->sock);
+      if (e != EWOULDBLOCK)
+      {
+         /* let programmer see errors */
+         dprintf("ftpsvr cmd socket error %d\n", e);
+         delftp(ftp);   /* thats the end of this connection... */
+         return FTP_ERROR; /* error return */
+      }
+      else     /* no command ready */
+         return FTP_NOCMD;
+   }
+   ftp->cmdbuflen += readval;    /* add read data to hp */
+
+   if (ftp->cmdbuflen == 0)   /* nothing in buffer? */
+      return FTP_NOCMD;
+
+   ftp->lasttime = ftpticks;     /* this is activity; rest timeout */
+
+   cp = strstr(ftp->cmdbuf, "\r\n");   /* look for trailing CRLF */
+   if (cp)  /* look for trailing CRLF */
+   {
+      char *   src;
+      char *   dst;
+
+      /* point to first byte following the CRLF */
+      cp += 2;
+      /* if there's not already a null there */
+      if (*cp)
+      {
+         /* move all the characters following the CRLF up one so we got
+            room to insert a null to terminate the command after the CRLF */
+         /* note we do this here because some of the later code paths
+            treat the command like an ASCIIZ string */
+         dst = ftp->cmdbuf + ftp->cmdbuflen;
+         src = dst - 1;
+         while (src >= cp)
+            *dst-- = *src--;
+         /* increment the number of characters in the command buffer to
+            account for the NULL */
+         ftp->cmdbuflen++;
+         /* NULL terminate the command */
+         *cp = 0;
+      }
+
+      /* now, flip the characters at the beginning of the buffer that 
+       * could be an FTP command from lower to upper case since 
+       * the protocol's supposed to be case insensitive *
+       *
+       * we look at at most the first 4 bytes since no commands
+       * are more than 4 bytes long 
+       */
+
+      for (dst = ftp->cmdbuf; dst < (ftp->cmdbuf + 4); ++dst)
+      {
+         /* upper case, leave as is */
+         if ((*dst >= 'A') && (*dst <= 'Z'))
+            continue;
+         /* lower case gets flipped to upper */
+         if ((*dst >= 'a') && (*dst <= 'z'))
+         {
+            *dst = (char) (*dst + (char) ('A' - 'a'));
+            continue;
+         }
+         /* anthing else means we got to end of command so break */
+         break;
+      }
+      return FTP_HASCMD;   /* Got command */
+   }
+   else
+      return FTP_NOCMD;    /* NO command */
+}
+
+
+
+/* FUNCTION: ftp_flushcmd()
+ * 
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: 
+ */
+
+static void
+ftp_flushcmd(ftpsvr * ftp)
+{
+   char *   cp;
+   int   old_cmd_len;
+   int   rest_of_cmds_len;
+
+   /* find command terminating CRLF */
+ff_again:
+   cp = strstr(ftp->cmdbuf, "\r\n");
+   if (!cp)
+   {
+      /* might be clobbered CR at end of path (see CWD code) */
+      if ( (unsigned)strlen(ftp->cmdbuf) < ftp->cmdbuflen)
+      {
+         ftp->cmdbuf[strlen(ftp->cmdbuf)] = '\r';     /* put back CR */
+         goto ff_again;
+      }
+      dtrap();    /* prog error */
+      return;
+   }
+
+   /* cp now points to a CRLF followed by the NULL we inserted in 
+    * ftp_getcmd(), so if theres data in the buffer following the 
+    * NULL, then its the beginning of the next command 
+    */
+   /* point to where next comamnd will be if its there */
+   cp += 3;
+   /* compute the length of the old command */
+   old_cmd_len = cp - ftp->cmdbuf - 1;
+
+   /* compute the length of the rest of the commands in the buffer */
+   /* that's the number of bytes that had been read into the buffer, 
+    * less the length of the old command less 1 for the NULL that 
+    * we inserted to null terminate the old command 
+    */
+   rest_of_cmds_len = ftp->cmdbuflen - old_cmd_len - 1;
+
+   /* this will happen if we didn't insert a null after the command 
+    * because there was one there already, which will be the case 
+    * when the old command is the only data that's been read so far, 
+    * in which case the length of the rest of the commands is 0 
+    */
+
+   if (rest_of_cmds_len < 0)
+      rest_of_cmds_len = 0;
+
+   /* if there are any other commands left in the buffer */
+   if (rest_of_cmds_len)
+   {
+      /* move them to the front of the buffer */
+      MEMCPY(ftp->cmdbuf,cp,rest_of_cmds_len);
+   }
+
+   /* zero the data following rest of the commands for the length of 
+    * the old command or else you risk finding command termination 
+    * sequences when none have been received 
+    */
+   /* if there are no other commands, this zeroes the old command
+      from the buffer */
+   MEMSET(ftp->cmdbuf + rest_of_cmds_len,0,old_cmd_len + 1);
+
+   ftp->cmdbuflen = rest_of_cmds_len;
+}
+
+
+
+
+/* FUNCTION: ftps_loop()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void
+ftps_loop()
+{
+   ftpsvr * ftp;
+   ftpsvr * ftpnext;
+   int   cmdready;
+   int   e;    /* error holder */
+
+#ifndef MINI_TCP
+   struct sockaddr   client;  /* for BSDish accept() call */
+   int               clientsize;
+   SOCKTYPE data_sock;        /* socket for passive accept */
+#endif
+
+   ftpnext = ftplist;   /* will be set to ftp at top of loop */
+
+   /* loop throught connection list */
+   while (ftpnext)
+   {
+      ftp = ftpnext;
+      ftpnext = ftp->next;    /* remember next in case ftp is deleted */
+      if (ftp->inuse)   /* if we are blocked in guts, quit */
+         continue;
+      ftp->inuse++;  /* set reentry flag */
+      e = 0;         /* clear error holder */
+      /* see if a command is ready */
+      cmdready = ftp_getcmd(ftp);
+      if (cmdready == FTP_ERROR)
+         continue;
+
+      switch (ftp->state)
+      {
+      case FTPS_CONNECTING:
+      case FTPS_NEEDPASS:
+         /* check for shorter session timeout in these states */
+         if (ftp->lasttime + ((unsigned long)ftps_lotmo * FTPTPS) < ftpticks)
+         {
+            e = -1;  /* set flag to force deletion of ftps */
+            break;
+         }
+         if (cmdready != FTP_HASCMD)
+            break;
+         if (ftp->state == FTPS_CONNECTING)
+            e = ftps_user(ftp);
+         else
+            e = ftps_password(ftp);
+         break;
+      case FTPS_LOGGEDIN:
+         /* connection timeouts like this are really obnoxious and should 
+          * be disabled usless there is some compling reason your target 
+          * should do otherwise (like dialup charges).
+          */
+#ifdef FTP_IDLECONN_TMO
+         /* see if session has been idle for too long */
+         if((ftps_conntmo > 0) &&
+             (ftp->lasttime + ((unsigned long)ftps_conntmo * FTPTPS) < ftpticks))
+         {
+            dprintf("ftpsrv: timout of idle FTP session\n");
+            delftp(ftp);
+            break;
+         }
+#endif   /* FTP_IDLECONN_TMO */
+
+         if (cmdready == FTP_HASCMD)
+            e = ftps_cmd(ftp);
+         /* if we are in passive mode and the client hasn't connected yet */
+         if (ftp->passive_state == FTPS_PASSIVE_MODE)
+         {
+            /* check to see if the client connected */
+#ifndef MINI_TCP
+
+            /* Accept for either V4 or V6 
+             */
+	 data_sock = SYS_SOCKETNULL;
+#ifdef IP_V6
+         if (LONG2SO(ftp->datasock)->so_domain == AF_INET6)
+         {
+            struct sockaddr_in6 cli6;
+            char ipv6WrkBuffer[60];
+   
+            clientsize = sizeof(struct sockaddr_in6);
+            data_sock = t_accept(ftp->datasock, &cli6, &clientsize); 
+         }            
+#endif /* IP_V6 */
+            
+#ifdef IP_V4
+         if (LONG2SO(ftp->datasock)->so_domain == AF_INET)
+         {
+            clientsize = sizeof(struct sockaddr_in);
+            data_sock = t_accept(ftp->datasock, &client, &clientsize);
+         }
+#endif /* IP_V4 */
+
+            /* if client didn't connect, break to continue */
+            if (data_sock == SYS_SOCKETNULL)
+               break;
+            /* client connected, so close listening socket so we wont take
+             * any more connections to it.
+             */
+            t_socketclose(ftp->datasock);
+
+            /* the data socket we care about is now the actual connection
+             * to the client.
+             */
+            ftp->datasock = data_sock;
+
+#else    /* mini sockets */
+            /* mini-sockets sets data_sock in a callback. If client
+             * didn't connect yet, break to continue.
+             */
+            if(ftp->datasock->state & SS_ISCONNECTED == 0)
+               break;
+#endif
+            /* change our passive state so that we know we are connected
+               to the client on the data socket */
+            ftp->passive_state |= FTPS_PASSIVE_CONNECTED;
+            /* if we have already received our data transfer command */
+            if (ftp->passive_cmd)
+            {
+               /* then do the command */
+               IN_PROFILER(PF_FTP, PF_ENTRY);
+               switch (ftp->passive_cmd)
+               {
+               case 0x4c495354:     /* "LIST" */
+               case 0x4e4c5354:     /* "NLST" */
+                  if (fs_dodir(ftp, ftp->passive_cmd))
+                     ftpputs(ftp, "451 exec error\r\n");
+                  break;
+               case 0x52455452:     /* "RETR" */
+                  ftp_sendfile(ftp);
+                  break;
+               case 0x53544f52:     /* "STOR" */
+                  ftp_getfile(ftp);
+                  break;
+                  /* there is a serious logic error someplace */
+               default :
+                  dprintf("invalid passive_cmd\n");
+                  dtrap();
+               }
+               IN_PROFILER(PF_FTP, PF_EXIT);
+            }
+         }
+         break;
+      case FTPS_RECEIVING:    /* task suspended while doing IO */
+      case FTPS_SENDING:
+         /* check for shorter session timeout in these states */
+         if (ftp->lasttime + ((unsigned long)ftps_iotmo * FTPTPS) < ftpticks)
+         {
+            e = -1;  /* set flag to force deletion of ftps */
+            break;
+         }
+         IN_PROFILER(PF_FTP, PF_ENTRY);
+         if (ftp->state == FTPS_SENDING)
+            e = ftp_sendfile(ftp);
+         else     /* must be receiving */
+            e = ftp_getfile(ftp);
+         IN_PROFILER(PF_FTP, PF_EXIT);
+
+#ifndef SUPERLOOP
+         /* If not superloop and there is still more data to move,
+          * then make sure ftp server will wake up to finish the
+          * send/receive later. The the transfer finished, the ftps
+          * state will have returned to LOGGEDIN.
+          */
+         if(ftp->state != FTPS_LOGGEDIN)
+            TK_WAKE(&to_ftpsrv);     /* make sure we come back later */
+#endif
+         break;
+      case FTPS_CLOSING:
+         break;
+      default:    /* bad state? */
+         dtrap();
+         break;
+      }
+      /* if fatal error or connection closed */
+      /* if (e == 452) 
+      {      
+         ftp->state = FTPS_LOGGEDIN;
+         ftp_flushcmd(ftp); 
+         ftp->inuse--;
+      } */
+      if (e || (ftp->state == FTPS_CLOSING))
+         delftp(ftp);
+      else
+         ftp->inuse--;     /* set reentry flag */
+   }
+}
+
+
+
+/* FUNCTION: newftp()
+ * 
+ * newftp() - create a new ftpsvr structure. Put in master queue. 
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+ftpsvr *
+newftp()
+{
+   ftpsvr * ftp;
+
+   ftp = (ftpsvr *)FTPSALLOC(sizeof(ftpsvr));
+   if (!ftp)
+      return NULL;
+   ftp->next = ftplist;
+   ftp->lasttime = ftpticks;
+   ftplist = ftp;
+
+   /* make sure we have a valid domain */
+#if defined(IP_V4) || defined(MINI_IP)
+   ftp->domain = AF_INET;  /* default to IPv4 */
+#else
+   ftp->domain = AF_INET6;
+#endif
+   return(ftp);
+}
+
+
+
+/* FUNCTION: delftp()
+ * 
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: 
+ */
+
+void
+delftp(ftpsvr *ftp)
+{
+   ftpsvr *list;
+   ftpsvr *last;
+
+   last = NULL;
+   for (list = ftplist; list; list = list->next)
+   {
+      if (list == ftp)
+      {
+         /* found server to kill, unlink: */
+         if (last)
+            last->next = list->next;
+         else
+            ftplist = list->next;
+
+         if (ftp->sock)
+         {
+            t_socketclose(ftp->sock);
+            ftp->sock = 0;
+         }
+         if (ftp->datasock)
+         {
+            t_socketclose(ftp->datasock);
+            ftp->datasock = 0;
+         }
+
+#ifdef   TCP_ZEROCOPY
+         /* don't orphan any packets we may have stored in ftpsq */
+         while (ftp->ftpsq.q_len > 0)
+            tcp_pktfree ((PACKET)getq(&ftp->ftpsq) );
+#endif   /* TCP_ZEROCOPY or not */
+
+         FTPSFREE(ftp);
+         ftps_connects--;     /* decrement connection count */
+         break;
+      }
+      last = list;
+   }
+}
+
+
+
+/* the ftps_ server command handler routines. These are called when a 
+ * command is received in the ftp->cmdbuf. Which one is called 
+ * depends in the session state. These all process a command, maybe 
+ * change the state, (or kill the session) and flush the command. All 
+ * return 0 if OK (which may mean pending work) or negative error 
+ * code if a fatal error was detected. 
+ */
+
+
+
+/* FUNCTION: ftps_user()
+ * 
+ * ftps_user() - called when we get a command in the initial state 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: 
+ */
+
+int
+ftps_user(ftpsvr * ftp)
+{
+   char *   cp;
+   int   e;
+
+   /* make sure client's telling me about a user */
+   if (MEMCMP(ftp->cmdbuf, "USER", 4) != 0)
+   {
+      ftpputs(ftp, ftp_badcmd);
+      return -1;  /* signal main loop to kill session */
+   }
+   cp = strstr(ftp->cmdbuf, "\r\n");
+   if (!cp)
+   {
+      dtrap();
+      return -1;  /* signal main loop to kill session */
+   }
+   *cp = 0;    /* NULL terminate user name */
+
+   /* search user list */
+   e = fs_lookupuser(ftp, &ftp->cmdbuf[5]);
+   *cp = '\r';    /* put back buffer char we clobbered */
+   if (e)
+   {
+      ftp->state = FTPS_CONNECTING;
+      ftpputs(ftp, "530 Invalid user\r\n");
+      ftp_flushcmd(ftp);
+      return 0;   /* user not valid */
+   }
+
+   ftp->cwd[0] = FTP_SLASH;
+   ftp->cwd[1] = 0;
+#ifdef DRIVE_LETTERS
+   strcpy(ftp->drive, DEFAULT_DRIVE);
+#endif   /* DRIVE_LETTERS */
+   ftp->type = FTPTYPE_ASCII; /* RFC says make text the defaul type */
+
+
+   if (ftp->user.password[0] == '\0')  /* no password required? */
+   {
+      ftpputs(ftp, ftp_loggedin);
+      ftp->state = FTPS_LOGGEDIN;
+      ftps_sessions++;
+   }
+   else  /* require a password */
+   {
+      ftpputs(ftp, ftp_needpass);   /* message to client */
+      ftp->state = FTPS_NEEDPASS;   /* set proper state */
+   }
+   ftp_flushcmd(ftp);
+   return 0;
+}
+
+
+
+/* FUNCTION: ftps_password()
+ * 
+ * ftps_password() - called when we get a command in the 
+ * FTPS_NEEDPASS state. 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: Returns 0 if OK (which may mean pending work) 
+ * or negative error code if a fatal error was detected. 
+ */
+
+int
+ftps_password(ftpsvr * ftp)
+{
+   char *   password;
+   char *   cp;
+
+   if (MEMCMP(ftp->cmdbuf, "PASS", 4) != 0)
+   {
+      ftpputs(ftp, ftp_badcmd);
+      return -1;  /* signal main loop to kill session */
+   }
+   password = &ftp->cmdbuf[5];
+   cp = strstr(password, "\r\n");   /* find end of command */
+   if (!cp) /* require whole command to be in buffer */
+      return -1;  /* signal main loop to kill session */
+
+   *cp = 0;    /* NULL terminate */
+   /* password '*' means we accept any password, so don't even compare */
+   if (ftp->user.password[0] != '*')
+   {
+      if (strcmp(password, ftp->user.password) != 0)
+      {
+         ftp->state = FTPS_CONNECTING;
+         ftpputs(ftp, "530 Invalid password\r\n");
+
+         if (ftp->logtries++ > 2)
+            return -1;  /* too many failed logins, kill session */
+         else
+         {
+            ftp_flushcmd(ftp);
+            return 0;   /* wait for another user/pass try */
+         }
+      }
+   }
+   ftpputs(ftp, ftp_loggedin);   /* login OK, set up session */
+   ftp->state = FTPS_LOGGEDIN;
+   ftps_sessions++;
+   ftp_flushcmd(ftp);
+   return 0;
+}
+
+
+
+/* FUNCTION: ftp_cmdpath()
+ * 
+ * ftp_getpath() - extract path from an FTP command in C string form. 
+ * The returned pointer is to the ftp->cmdbuf area. 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: Returns NULL on any error after sending complain 
+ * string to client. 
+ */
+
+char *   
+ftp_cmdpath(ftpsvr * ftp)
+{
+   char *   cp;
+
+   cp = strchr(&ftp->cmdbuf[4], '\r');
+   if (!cp)
+   {
+      ftpputs(ftp, "501 garbled path\r\n");
+      return NULL;
+   }
+   *cp = 0;    /* null terminate path in buffer */
+   cp = &ftp->cmdbuf[4];
+   while (*cp == ' ') cp++;   /* bump past spaces */
+      if (strlen(cp) > FTPMAXPATH)
+   {
+      ftpputs(ftp, "553 path too long\r\n");
+      return NULL;
+   }
+   return cp;
+}
+
+
+
+/* FUNCTION: ftp_make_filename()
+ * 
+ * create a complete file name and path from the file specification 
+ * in the command buffer and the cwd associated with the current ftp 
+ * session. allow_empty_filespec specifies whether a file 
+ * specification is required (as is the case with RETR and STOR) or 
+ * whether it is optional (as is the case with NLST and LIST). 
+ *
+ * PARAM1: ftpsvr *ftp
+ * PARAM2: int allow_empty_filespec
+ *
+ * RETURNS: TRUE if success, FALSE if some error occurred 
+ */
+
+int ftp_make_filename(ftpsvr *ftp,int allow_empty_filespec)
+{
+   char *cp;
+   char *cp1;
+   int relative_path;
+
+   cp = ftp_cmdpath(ftp);
+   if(!cp)   return FALSE;   /* ftp_cmdpath() already sent error */
+
+   /* if there is no file spec in the command buffer and one is
+      required, xmit error response and fail function */
+   if(!(*cp) && !allow_empty_filespec)
+   {
+      ftpputs(ftp, "501 bad path\r\n");
+      return FALSE;
+   }
+
+   /* if the file spec is too long, xmit error response and fail */
+   if(strlen(cp) > FTPMAXPATH)
+   {
+      ftpputs(ftp, "552 Path/name too long\r\n");
+      return FALSE;
+   }
+   lslash(cp);
+
+   /* assume the path specified is not a relative path */
+   relative_path = FALSE;
+
+   /* working pointer to file name */
+   cp1 = ftp->filename;
+
+/* if this target system deals with DOS drive letters */
+#ifdef DRIVE_LETTERS
+   /* if the client specified path contains a colon in the right place */
+   if (*cp && (*(cp + 1) == ':'))
+   {
+      /* copy the drive: to the beginning of the filename */
+      *cp1++ = (char) upper_case(*cp);
+      *cp1++ = ':';
+
+      /* if the specified drive is the same as the current drive
+         and the client specified path does not start at the root */
+      if ((upper_case(*cp) == upper_case(ftp->drive[0])) &&
+         (*(cp + 2) != FTP_SLASH))
+      {
+         /* then its a relative path */
+         relative_path = TRUE;
+      }
+
+      /* bump past drive and colon in client path */
+      cp += 2;
+   }
+   /* client path does not contain a drive spec */
+   else
+   {
+      /* so use the current drive */
+      *cp1++ = ftp->drive[0];
+      *cp1++ = ':';
+      /* if client path does not start at the root */
+      if (*cp != FTP_SLASH)
+      {
+         /* its a relative path */
+         relative_path = TRUE;
+      }
+   }
+#else /* DRIVE_LETTERS */
+   /* target system is fortunate enough to not have to deal
+      with DOS drive letters */
+
+   /* if client path does not start at root */
+   if (*cp != FTP_SLASH)
+   {
+      /* else its a relative path */
+      relative_path = TRUE;
+   }
+#endif /* DRIVE_LETTERS */
+
+   /* if the client specified path is not relative */
+   if (!relative_path)
+   {
+      /* in this case, cp now points to past any drive info in
+         the path provided by the client and cp1 now points to past
+         any drive info in the constructed file name */
+      /* if the path provided by the client isn't absolute, append
+         a slash to the constructed file name. note this can happen
+         if the client specified a drive other than the default */
+      if (*cp != FTP_SLASH)
+         *cp1++ = FTP_SLASH;
+      /* append client path to our constructed file name */
+      strcpy(cp1,cp);
+   }
+   /* the client specified path was relative */
+   else
+   {
+      /* copy current working directory to file name (following
+         any drive letter stuff that might have been added above) */
+      strcpy(cp1, ftp->cwd);
+      cp1 = &ftp->filename[strlen(ftp->filename)-1]; /* point to end */
+
+      /* if ftp->cwd is not terminated with a slash and the file spec
+         is not empty, append a slash */
+      if ((*cp1 != FTP_SLASH) && *cp)
+      {
+         ++cp1;  /* increment ptr past last character to NULL */
+         *cp1++ = FTP_SLASH;
+         *cp1 = 0;
+      }
+
+      /* make sure the concatenation of the specified file name to
+         the current working directory wont be too big for the
+         file name field */
+      if ((strlen(ftp->filename) + strlen(cp)) >= sizeof(ftp->filename))
+      {
+         ftpputs(ftp,"501 file name too long\r\n");
+         return FALSE;
+      }
+
+      /* concatenate the file spec from the command line to the
+         current working directory */
+      strcat(ftp->filename, cp);
+   }
+
+   return TRUE; /* function succeeded */
+}
+
+
+/* FUNCTION: ftp_leave_passive_state()
+ * 
+ * this function is called to make the session leave passive state
+ *
+ * PARAM1: ftpsvr *ftp
+ *
+ * RETURNS: 
+ */
+
+void ftp_leave_passive_state(ftpsvr * ftp)
+{
+   /* there's a little confusion about whether this field is 0 or
+    *  -1 when the socket is unactive, so check for both
+    */
+   if ((ftp->datasock != SYS_SOCKETNULL) && (ftp->datasock != 0))
+      t_socketclose(ftp->datasock);
+   ftp->datasock = 0;
+   /* we aren't in passive mode anymore */
+   ftp->passive_state = 0;
+   /* no data transfer command received while in passive state */
+   ftp->passive_cmd = 0;
+   ftp->server_dataport = 0;
+}
+
+
+
+/* FUNCTION: ftps_do_pasv()
+ *
+ * handle IPv4 PASV command
+ *
+ * Called when the client requests a transfer in "passive" mode.
+ *
+ * PARAM1: ftpsvr *ftp
+ *
+ * RETURNS: 
+ */
+
+#ifdef IP_V4
+void ftps_do_pasv(ftpsvr * ftp)
+{
+   /* do_pasv() may re-enter if the client sends us a PASV while we 
+    * are transfering a file. This is an error on the client's part. 
+    * Its not clear that this can happen given the way the 
+    * main state machine works, but check for it just in case
+    */
+   if (ftp->passive_state & FTPS_PASSIVE_CONNECTED)
+   {
+      ftpputs(ftp,"425 Data transfer already in progress\r\n");
+      return;
+   }
+
+   /* This will happen if the client had sent us a PASV and then sent 
+    * us another one without an intervening data transfer command. 
+    */
+   if (ftp->passive_state & FTPS_PASSIVE_MODE)
+   {
+      ftp_leave_passive_state(ftp);
+   }
+
+   /* call sockets routine to do passive open */
+   ftps_v4pasv(ftp);
+
+   /* we are now in passive mode, but the client hasn't connected yet */
+   ftp->passive_state = FTPS_PASSIVE_MODE;
+
+   /* we haven't received a data transfer command from the client yet */
+   ftp->passive_cmd = 0;
+}
+#endif   /* IP_V4 */
+
+
+
+/* FUNCTION: ftps_cmd()
+ * 
+ * called when we get a command in the FTPS_LOGGEDIN state
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS:  Returns 0 if OK, else ftp error. 
+ */
+
+int
+ftps_cmd(ftpsvr * ftp)
+{
+   int   i;    /* scratch for command processing */
+   char *   cp;
+   char *   cp1;
+   u_long   lparm;   /* scratch, for parameter extraction */
+   u_short  sparm;   /* "" */
+   u_long   ftpcmd;  /* 4 char command as number for fast switching */
+   int   relative_path;
+
+   ftpcmd = 0L;
+   /* copy 4 bytes of ftp cmd text into local long value, replacing 
+   unprintable chars with blanks */
+   for (i = 0; i < 4; i++)
+   {
+      if (ftp->cmdbuf[i] >= ' ')
+         ftpcmd = (ftpcmd << 8) | ftp->cmdbuf[i];
+      else     /* space over unprintable characters */
+         ftpcmd = (ftpcmd << 8) | ' ';
+   }
+
+   /* switch on command */
+   switch (ftpcmd)
+   {
+   case 0x53595354:     /* "SYST" */
+      /* see what Netscape does with this */
+      ftpputs(ftp, "215 UNIX system type\r\n");
+      break;
+   case 0x54595045:     /* "TYPE" */
+      if ((ftp->cmdbuf[5] == 'A') || (ftp->cmdbuf[5] == 'a'))
+         ftp->type = FTPTYPE_ASCII;
+      else  /* we default all other types to binary */
+         ftp->type = FTPTYPE_IMAGE;
+      ftpputs(ftp, ftp_cmdok);
+      break;
+   case 0x50574420:     /* "PWD " */
+      sprintf(ftp->filebuf, "257 \"%s\"\r\n", uslash(ftp->cwd));
+      lslash(ftp->cwd);
+      ftpputs(ftp, ftp->filebuf);
+      break;
+   case 0x58505744:     /* "XPWD" */
+      sprintf(ftp->filebuf, "257 \"%s%s\"\r\n", DRIVE_PTR(ftp), ftp->cwd);
+      ftpputs(ftp, ftp->filebuf);
+      break;
+   case 0x55534552:     /* "USER" */
+      return(ftps_user(ftp));
+   case 0x504f5254:     /* PORT */
+      cp = &ftp->cmdbuf[5];   /* point to IP address text */
+      lparm = 0L;
+      for (i = 3; i >= 0; i--)   /* extract 4 digit IP address */
+      {
+         lparm |= (((u_long)atoi(cp)) << (i*8));
+         cp = strchr(cp, ',');   /* bump through number to comma */
+         if (!cp)    /* must be comma delimited */
+         {
+            ftpputs(ftp,"501 invalid PORT command\r\n");
+            break;
+         }
+         cp++;    /* point to next digit */
+      }
+      /* the C break key word really needs a parameter so constructs 
+       * like this aren't necessary, anyway, if this is true, its 
+       * because we broke out of the above for on an error and we 
+       */
+      if (!cp)
+         break;
+      sparm = (u_short)atoi(cp) << 8;
+      while (*cp >= '0')cp++; /* bump through number */
+         if (*cp != ',')   /* must be comma delimited */
+      {
+         ftpputs(ftp,"501 invalid PORT command\r\n");
+         break;
+      }
+      cp++;    /* point to next digit */
+      sparm |= atoi(cp);
+
+      /* this will happen if the client sends us a PORT while we are 
+       * transfering a file. this is an error on the client's part, 
+       */
+      /* actually, its not clear that this can happen given the way the
+         main state machine works, but check for it just in case */
+      if (ftp->passive_state & FTPS_PASSIVE_CONNECTED)
+      {
+         ftpputs(ftp,"425 Data transfer already in progress\r\n");
+         break;
+      }
+      /* this will happen if the client had sent us a PASV and then 
+       * sent us a PORT without an intervening data transfer command. 
+       */
+      if (ftp->passive_state & FTPS_PASSIVE_MODE)
+      {
+         ftp_leave_passive_state(ftp);
+      }
+
+      ftp->host = lparm;
+      ftp->dataport = sparm;
+      ftpputs(ftp, ftp_cmdok);
+      break;
+   case 0x51554954:     /* QUIT" */
+      /* if we don't have a file transfer going, kill sess now */
+      if ((ftp->state != FTPS_SENDING) && (ftp->state != FTPS_RECEIVING))
+      {
+         ftpputs(ftp, "221 Bye\r\n");     /* session terminating */
+         ftp->state = FTPS_CLOSING;
+         /*         delftp(ftp);  */
+         return -1;  /* signal main loop to kill session */
+      }
+      else
+         return 0;   /* return without flushing QUIT */
+   case 0x43574420:  /* "CWD " */
+      /* note the intent here is to end up with the client supplied 
+       * drive string (as in "c:") in the drive field, and the client 
+       * supplied current working directory, without any drive spec, 
+       * in the cwd field. to this end we construct the fully 
+       * qualified path, including the drive in the filename field 
+       * which will 
+       */
+      cp = ftp_cmdpath(ftp);
+      if (!cp) break;
+         lslash(cp);    /* convert slashes to local */
+
+      /* assume the path specified is not a relative path */
+      relative_path = FALSE;
+
+      /* point to beginning of file name */
+      cp1 = ftp->filename;
+
+      /* if this target system deals with DOS drive letters */
+#ifdef DRIVE_LETTERS
+      /* if the client specified path contains a colon in the right place */
+      if (*cp && (*(cp + 1) == ':'))
+      {
+         /* copy the drive: to the beginning of the filename */
+         *cp1++ = (char) upper_case(*cp);
+         *cp1++ = ':';
+
+         /* if the specified drive is the same as the current drive
+            and the client specified path does not start at the root */
+         if ((upper_case(*cp) == upper_case(ftp->drive[0])) &&
+             (*(cp + 2) != FTP_SLASH))
+         {
+            /* then its a relative path */
+            relative_path = TRUE;
+         }
+
+         /* bump past drive and colon in client path */
+         cp += 2;
+      }
+      /* client path does not contain a drive spec */
+      else
+      {
+         /* so use the current drive */
+         *cp1++ = ftp->drive[0];
+         *cp1++ = ':';
+         /* if client path does not start at the root */
+         if (*cp != FTP_SLASH)
+         {
+            /* its a relative path */
+            relative_path = TRUE;
+         }
+      }
+#else /* DRIVE_LETTERS */
+      /* target system is fortunate enough to not have to deal
+         with DOS drive letters */
+      /* if client path does not start at root */
+      if (*cp != FTP_SLASH)
+      {
+         /* else its a relative path */
+         relative_path = TRUE;
+      }
+#endif   /* DRIVE_LETTERS */
+
+      /* if the client specified path is not relative */
+      if (!relative_path)
+      {
+         /* in this case, cp now points to past any drive info in the 
+          * path provided by the client and cp1 now points to past 
+          *
+          * if the path provided by the client isn't absolute, append 
+          * a slash to the constructed file name. note this can 
+          * happen 
+          */
+         if (*cp != FTP_SLASH)
+            *cp1++ = FTP_SLASH;
+         strcpy(cp1,cp);
+      }
+      /* the client specified path was relative */
+      else
+      {
+         /* copy current working directory to file name (following
+            any drive letter stuff that might have been added above) */
+          strcpy(cp1, ftp->cwd);     /* copy cwd for change */
+          cp1 = ftp->filename + strlen(ftp->filename); /* start at end */
+          while (*cp)
+             {
+             if (*cp == '.' && *(cp+1) == '.')   /* double dot? */
+                {  /* back up 1 level */
+                if (strlen(ftp->cwd) < 2)  /* make sure we have room */
+                   {
+                      ftpputs(ftp, "550 Bad path\r\n");
+                      ftp_flushcmd(ftp);
+                      return 0;   /* not a fatal error */
+                   }
+                   /* null out last directory level */
+                while (*cp1 != FTP_SLASH && cp1 > ftp->filename)
+                   *cp1-- = 0;
+#ifdef DRIVE_LETTERS
+               if (cp1 > (ftp->filename + 2))
+#else /* DRIVE_LETTERS */
+               if(cp1 > ftp->filename)   /* if not at root... */
+#endif /* DRIVE_LETTERS */
+                  *cp1 = 0;   /* null over trailing slash */
+               cp += 2; /* bump past double dot */
+            }
+            else if(*cp == FTP_SLASH) /* embedded slash */
+               cp++;    /* just skip past it */
+            else  /* got a dir name, append to new path */
+            {
+               if(*(cp1-1) != FTP_SLASH) /* if not at top... */
+                  *cp1++ = FTP_SLASH;    /* add the slash to new path */
+               while(*cp && *cp != FTP_SLASH)  /* copy directory name */
+               {
+                  *cp1++ = *cp++;
+                  if(cp1 >= &ftp->filename[FTPMAXPATH+2]) /* check length */
+                  {
+                     ftpputs(ftp, "550 Path too long\r\n");
+                     ftp_flushcmd(ftp);
+                     return 0;   /* not a fatal error */
+                  }
+               }
+            }
+         } /* end of 'while(*cp)' loop */
+#ifdef DRIVE_LETTERS
+         if(cp1 == ftp->filename + 2)   /* if at root... */
+#else /* DRIVE_LETTERS */
+         if(cp1 == ftp->filename)   /* if at root... */
+#endif /* DRIVE_LETTERS */
+            cp1++;   /* bump past slash */
+         *cp1 = 0;   /* null terminate new path */
+      }
+
+      /* new drive and/or directory is now in ftp->filename */
+      /* verify path exists */
+      if (!fs_dir(ftp))
+      {
+         sprintf(ftp->filebuf, "550 Unable to find %s\r\n",ftp->filename);
+         ftpputs(ftp, ftp->filebuf);
+         break;
+      }
+
+#ifdef DRIVE_LETTERS
+
+      /* store the drive into the filename in the drive field */
+      ftp->drive[0] = ftp->filename[0];
+      ftp->drive[1] = ':';
+      ftp->drive[2] = 0;
+      /* store the file name sans drive info in the cwd field */
+      strcpy(ftp->cwd,ftp->filename + 2);
+
+#else /* DRIVE_LETTERS */
+
+      /* store the file name in the cwd field */
+      strcpy(ftp->cwd, ftp->filename);
+
+#endif /* DRIVE_LETTERS */
+
+      sprintf(ftp->filebuf, 
+         "200 directory changed to %s%s\r\n", DRIVE_PTR(ftp), ftp->cwd);
+      ftpputs(ftp, ftp->filebuf);      /* send reply to client */
+      break;
+   case 0x4c495354:   /* "LIST" */
+   case 0x4e4c5354:   /* "NLST" */
+      listcmds++;
+      /* attempt to create a complete path from the current working
+         directory and the file spec in the command buffer. */
+      if (!ftp_make_filename(ftp,TRUE))
+         break;
+
+      /* if we are in passive mode but the client hasn't connected to
+         data socket yet, just store the command so it will get executed
+         when the client connects */
+      if (ftp->passive_state == FTPS_PASSIVE_MODE)
+      {
+         ftp->passive_cmd = ftpcmd;
+         break;
+      }
+
+
+      /* generate the listing, if the function fails,
+         send an error message back to the client */
+      if (fs_dodir(ftp, ftpcmd))
+         ftpputs(ftp, "451 exec error\r\n");
+      break;
+
+#ifdef IP_V4
+   case 0x50415356:   /* "PASV" */
+      ftps_do_pasv(ftp);
+      break;
+#endif /* IP_V4 */
+
+#ifdef IP_V6
+   case 0x45505356:   /* "EPSV" - IPv6 extended PASV */
+      ftps_epsv(ftp);
+      break;
+   case 0x45505254:   /* "EPRT"  - IPv6 extended PORT */
+      ftps_eprt(ftp);
+      break;
+#endif /* IP_V6 */
+
+   /* some commands we know about and just don't do: */
+   case 0x4d414342:   /* "MACB" - ??? Netscape 3.0 for Win95 sends this */
+   case 0x53495a45:   /* "SIZE" - Netscape again. */
+   case 0x4f505453:   /* "OPTS" - IE 5.50 */
+      ftpputs(ftp, ftp_badcmd);
+      break;
+   case 0x52455452:   /* "RETR" */
+   case 0x53544f52:   /* "STOR" */
+      /* attempt to create a complete path from the current working
+         directory and the file spec in the command buffer. */
+      if (!ftp_make_filename(ftp,FALSE))
+         break;
+
+      /* ftp->filename now has drive:path/name of file to try for */
+
+      /* check for user permission */
+      if(fs_permit(ftp) == FALSE)
+      {
+         ftpputs(ftp, ftp_noaccess);
+         ftp_xfercleanup(ftp);
+         break;
+      }
+
+      /* verify that the name of the file we are trying to put or
+         get does not exist as a directory */
+      if(fs_dir(ftp))
+      {
+         ftpputs(ftp, "501 bad path\r\n");
+         ftp_xfercleanup(ftp);
+         break;
+      }
+
+      /* if we are in passive mode but the client hasn't connected to
+         data socket yet, just store the command so it will get executed
+         when the client connects */
+      if (ftp->passive_state == FTPS_PASSIVE_MODE)
+      {
+         ftp->passive_cmd = ftpcmd;
+         break;
+      }
+
+      IN_PROFILER(PF_FTP, PF_ENTRY);
+      if(ftpcmd == 0x52455452)   /* RETR */
+         ftp_sendfile(ftp);
+      else   /* must be STOR */
+         ftp_getfile(ftp);
+      IN_PROFILER(PF_FTP, PF_EXIT);
+
+      break;
+   case 0x44454c45:   /* "DELE" */
+      /* attempt to create a complete path from the current working
+         directory and the file spec in the command buffer. */
+      if (!ftp_make_filename(ftp,FALSE))
+      {
+         sprintf(ftp->filebuf, "550 Unable to parse filename  %s\r\n", \
+                 ftp->filename);
+
+         ftpputs(ftp, ftp->filebuf);
+         break;
+      }
+
+      lslash(ftp->filename);
+
+      /* ftp->filename now has drive:path/name of file to try for */
+
+      /* check if the file that the client wants to delete exists */
+      if (ftp->type == FTPTYPE_ASCII)
+         ftp->filep = vfopen(ftp->filename, "r");  /* ANSI translated mode */
+      else
+         ftp->filep = vfopen(ftp->filename, "rb"); /* ANSI binary mode */
+
+      if (ftp->filep == NULL)
+      {
+         /* if we appended VFS path to our constructed file name dont say so */
+         if (*(ftp->filename) == FTP_SLASH)
+            cp = ftp->filename + 1;
+         else
+            cp = ftp->filename;
+
+         sprintf(ftp->filebuf, "550 No such file %s\r\n", cp);
+         ftpputs(ftp, ftp->filebuf);
+         break;
+      }
+      else
+      {
+         vfclose(ftp->filep);
+      }
+
+      /* check for user permission */
+      if(fs_permit(ftp) == FALSE)
+      {
+         ftpputs(ftp, ftp_noaccess);
+         break;
+      }
+
+      if (vunlink(ftp->filename) != 0)
+      {
+         /* if we appended VFS path to our constructed file name dont say so */
+         if (*(ftp->filename) == FTP_SLASH)
+            cp = ftp->filename + 1;
+         else
+            cp = ftp->filename;
+
+         sprintf(ftp->filebuf, "550 Unable to delete file %s\r\n", cp);
+         ftpputs(ftp, ftp->filebuf);
+         break;
+      }
+      else
+      {
+         ftpputs(ftp, "250 DELE command successful\r\n");
+         break;
+      }
+   case 0x4e4f4f50:   /* "NOOP" */
+      ftpputs(ftp, ftp_cmdok);
+      break;
+   default:
+      sprintf(ftp->filebuf, "500 Unknown cmd %s", ftp->cmdbuf);
+      ftpputs(ftp, ftp->filebuf);
+    }
+   ftp_flushcmd(ftp);
+   return 0;
+}
+
+
+/* FUNCTION: ftp_xfercleanup()
+ * 
+ * Called after a file transfer to clean up session structure and 
+ * handle replys.
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: void
+ */
+
+void
+ftp_xfercleanup(ftpsvr * ftp)
+{
+   /* close any open file */
+   if(ftp->filep)
+   {
+      vfclose(ftp->filep);
+      ftp->filep = NULL;
+   }
+   /* close any open socket */
+   if (ftp->datasock != SYS_SOCKETNULL)
+   {
+      t_socketclose(ftp->datasock);
+      ftp->datasock = SYS_SOCKETNULL;
+   }
+   ftp->state = FTPS_LOGGEDIN;
+
+#ifdef   TCP_ZEROCOPY
+   /* don't orphan any packets we may have stored in ftpsq */
+   while (ftp->ftpsq.q_len > 0)
+      tcp_pktfree ((PACKET)getq(&ftp->ftpsq) );
+#endif   /* TCP_ZEROCOPY or not */
+
+   /* we aren't in passive mode anymore */
+   ftp_leave_passive_state(ftp);
+}
+
+
+
+#ifdef TCP_ZEROCOPY  /* use InterNiche Zero-copy TCP socket extensions */
+extern   PACKET tcp_pktalloc(int);
+extern   void tcp_pktfree(PACKET);
+int ftps_rxupcall(struct socket * so, PACKET pkt, int code);
+#endif   /* TCP_ZEROCOPY */
+
+
+/* FUNCTION: ftp_sendfile()
+ *
+ * Send a file. Filename, Port, type, and IP address are all 
+ * set in ftp structure. Returns 0 if OK, else ftp error. 
+ *
+ * 
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS:  Returns 0 if OK, else ftp error. 
+ */
+
+int
+ftp_sendfile(ftpsvr * ftp)
+{
+   int   e;
+   int   reterr = 0;
+   u_long   put_timer;  /* timer for max time to loop in this routine */
+
+#ifndef TCP_ZEROCOPY
+   int   bytes = 0;
+#endif
+
+   /* See if this is start of send */
+   if (ftp->state != FTPS_SENDING)
+   {
+      lslash(ftp->filename);
+      if (ftp->type == FTPTYPE_ASCII)
+         ftp->filep = vfopen(ftp->filename, "r");
+      else
+         ftp->filep = vfopen(ftp->filename, "rb");
+      if (!ftp->filep)
+      {
+         ftpputs(ftp, "451 aborted, can't open file\r\n");
+
+         /* if we are already connected to the client because we were 
+          * in passive mode, close the connection to client and exit 
+          */
+         if (ftp->passive_state & FTPS_PASSIVE_MODE)
+            ftp_leave_passive_state(ftp);
+         return 451;
+      }
+      ftpputs(ftp, "150 Here it comes...\r\n");
+      /* if we are not already connected from a previous PASV */
+      if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED))
+      {
+         /* connect to client */
+         ftp->datasock = FTP_TCPOPEN(ftp);
+         if (ftp->datasock == SYS_SOCKETNULL)
+         {
+            ftpputs(ftp, "425 Can't open data connection\r\n");
+            reterr = 425;
+            goto ftsnd_exit;
+         }
+      }
+
+#ifdef TCP_ZEROCOPY
+      ftp->iosize = tcp_mss(LONG2SO(ftp->datasock));
+#endif /* TCP_ZEROCOPY */
+
+      ftp->state = FTPS_SENDING;
+      ftp->filebuflen = 0;
+   }
+
+   /*
+    * loop below while sending, quit when we reach MAX number of 
+    * ftpticks we're allowed. The ftps_loop() routine will call us
+    * again later
+    */
+   put_timer = (ftpticks + FTPTPS);    /* set timeout tick */
+
+#ifdef TCP_ZEROCOPY
+   /* different loops for ZEROCOPY and plain sockets */
+   for (;;)
+   {
+      PACKET pkt;
+      if (ftp->pkt == NULL)   /* need to read more file data */
+      {
+         pkt = tcp_pktalloc(ftp->iosize);
+         if (!pkt)   /* if no buffer, try again later */
+            return 0;
+         e = vfread(pkt->nb_prot, 1, ftp->iosize, ftp->filep);
+         if (e < 0)
+         {
+            ftpputs(ftp, "451 aborted, file read error\r\n");
+            reterr = 451;
+            break;
+         }
+         pkt->nb_plen = (unsigned)e;
+      }
+      else  /* retry old packet saved in session structure */
+      {
+         pkt = ftp->pkt;
+      }
+
+      if (pkt->nb_plen)
+      {
+         e = tcp_xout(ftp->datasock, pkt);
+         if (e == ENP_RESOURCE)  /* blocked */
+         {
+            ftp->pkt = pkt;   /* save pkt for later */
+            tk_yield();       /* spin system */
+            return 0;         /* wait for socket to clear */
+         }
+         else if(e < 0)
+         {
+            ftpputs(ftp, "426 aborted, data send error\r\n");
+            reterr = 426;
+            if (pkt) 
+            {
+               tcp_pktfree(pkt);
+            }
+            break;
+         }
+         else  /* sent without error */
+         {
+            /* tcp layer will free pkt when data is acked, just 
+            clear to ftps pointer for now */
+            ftp->pkt = NULL;
+         }
+         ftp->lasttime = ftpticks;     /* reset timeout */
+         /*
+          * force return to let other FTP sessions run if we have had CPU
+          * continuously for a longish while
+          */
+         if (ftpticks > put_timer)
+            return 0;
+      }
+      else  /* end of file & all bytes sent */
+      {
+         tcp_pktfree(pkt);
+         ftp->pkt = NULL;
+         break;   /* fall to send termination logic */
+      }
+   }
+#else /* not TCP_ZEROCOPY */
+   for (;;)
+   {
+      if (ftp->filebuflen == 0)  /* need to read more file data */
+      {
+         /* if its an ASCII type transfer */
+         if (ftp->type == FTPTYPE_ASCII)
+         {
+            /* then we need to insert a CR before any LF that is not
+             * already preceeded by an LF.
+             * Since the last character we read before filling up the 
+             * file transfer buffer could be a lonely LF and in that 
+             * case we'd have no room to insert the CR before it and 
+             * it would be a righteous pain to keep track of this one 
+             * boundary condition in the state machine, we will 
+             * terminate the loop when there is still 1 byte left 
+             */
+            while (ftp->filebuflen < FILEBUFSIZE - 1)
+            {
+               int   next_char;
+               int   prev_char   =  0;
+
+               /* read next character from file */
+               next_char = vgetc(ftp->filep);
+               /* break on end of file */
+               if (next_char < 0)
+                  break;
+               /* if we read an LF */
+               if (next_char == '\n')
+               {
+                  /* and the previous char wasn't a CR */
+                  if (prev_char != '\r')
+                  {
+                     /* insert a CR ahead of the LF */
+                     ftp->filebuf[ftp->filebuflen] = '\r';
+                     ftp->filebuflen++;
+                  }
+               }
+               ftp->filebuf[ftp->filebuflen] = (char) next_char;
+               ftp->filebuflen++;
+               /* if we just read a LF, break. why? you ask. well 
+                * what happens if the last byte we read before 
+                * filling up the transfer buffer is a CR. when we 
+                * come back in here again and read the LF, that LF 
+                * looks like a lonely LF, so we'd end up inserting 
+                * another CR, which wouldn't be right. so to protect 
+                * against that and allow us to avoid storing the last 
+                * character read in the ftpsrv structure in order to 
+                * support this archaic feature, we just terminate the 
+                * read when we get to the end of a line on the 
+                * assumption that theres not going to be too many 
+                * people moving text 
+                */
+               if (next_char == '\n')
+                  break;
+               prev_char = next_char;
+            }
+         }
+         else  /* its a binary transfer so just read the data */
+         {
+            e = vfread(ftp->filebuf, 1, FILEBUFSIZE, ftp->filep);
+            if (e < 0)
+            {
+               ftpputs(ftp, "451 aborted, file read error\r\n");
+               reterr = 451;
+               break;
+            }
+            ftp->filebuflen = (unsigned)e;
+         }
+      }
+      bytes = (int)ftp->filebuflen;
+      if (bytes)
+      {
+         e = t_send(ftp->datasock, ftp->filebuf, bytes, 0);
+         if (e < 0)
+         {
+            /* See what kind of error it is. If we're out of sockbuf
+             * space or buffers then 
+             * return 0 to try again later. If its anything else then 
+             * it's serious and we should abort with an error 
+             */
+            e = t_errno(ftp->datasock);
+            if((e == EWOULDBLOCK) || (e == ENOBUFS))
+            {
+               return 0;   /* out of socket space, try layer */
+            }
+            ftpputs(ftp, "426 aborted, data send error\r\n");
+            reterr = 426;
+            break;
+         }
+         else  /* no send error */
+         {
+#ifdef NPDEBUG /* sanity test socket return values */
+            if (e > FILEBUFSIZE)
+            {  dtrap(); /* serious logic problem here */
+               return 0;
+            }
+#endif   /* NPDEBUG */
+            ftp->filebuflen -= e;
+#ifdef NPDEBUG
+            if ((int)ftp->filebuflen < 0)
+            {  dtrap(); 
+               return 0;
+            }
+#endif
+            if (e != bytes)   /* partial send on NBIO socket */
+            {
+               if (e != 0) /* sent some data, but not all - move buffer */
+               {
+                  MEMMOVE(ftp->filebuf, ftp->filebuf+e, ftp->filebuflen);
+               }
+               return 0;      /* try again later */
+            }
+         }
+
+         ftp->lasttime = ftpticks;     /* reset timeout */
+
+         /*
+          * force return to let other FTP sessions run if we have had CPU
+          * continuously for a longish while
+          */
+         if (ftpticks > put_timer)
+         {
+            return 0;
+         }
+      }
+      else  /* end of file & all bytes sent */
+         break;   /* fall to send termination logic */
+   }
+#endif   /* TCP_ZEROCOPY */
+
+ftsnd_exit:
+
+   /* get here if EOF or fatal error */
+
+#ifdef NPDEBUG
+   if (reterr == 0 && ftp->filebuflen != 0)  /* buffer should be empty */
+   {   dtrap();   }
+#endif
+
+   /* first reply to user if xfer was OK */
+   if (!reterr)
+      ftpputs(ftp, "226 Transfer OK, Closing connection\r\n");
+
+   ftp_xfercleanup(ftp);
+   return reterr;
+}
+
+
+/* FUNCTION: ftp_getfile()
+ * 
+ * Get a file from client. We open a connection to the client
+ * and he will send it to us. Filename, Port, type, and IP 
+ * address are all set in ftp structure. 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: Returns 0 if OK, else ftp error. 
+ */
+
+int
+ftp_getfile(ftpsvr * ftp)
+{
+   int   bytes;
+   int   e;
+   int   reterr   =  0;
+   u_long   get_timer;  /* ctick to force a return */
+
+   /* See if this is start of receive operation */
+   if (ftp->state != FTPS_RECEIVING)
+   {
+      lslash(ftp->filename);
+
+      if (ftp->type == FTPTYPE_ASCII)
+         ftp->filep = vfopen(ftp->filename, "w");
+      else
+         ftp->filep = vfopen(ftp->filename, "wb");
+      if (!ftp->filep)
+      {
+         ftpputs(ftp, "451 aborted, can't open file\r\n");
+
+         /* if we are already connected to the client because we were 
+          * in passive mode, close the connection to client and exit 
+          */
+         if (ftp->passive_state & FTPS_PASSIVE_MODE)
+            ftp_leave_passive_state(ftp);
+
+         return 550;
+      }
+      /* if we are not already connected from a previous PASV */
+      if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED))
+      {
+         ftp->datasock = FTP_TCPOPEN(ftp);
+         if (ftp->datasock == SYS_SOCKETNULL)
+         {
+            ftpputs(ftp, "425 Can't open data connection\r\n");
+            reterr = 425;
+            goto ftget_exit;
+         }
+      }
+      ftpputs(ftp, "150 Connecting for STOR\r\n");
+      ftp->state = FTPS_RECEIVING;
+#ifdef TCP_ZEROCOPY
+      ftp->rxcode = 0;
+      t_setsockopt(ftp->datasock, 0, SO_CALLBACK, (void*)ftps_rxupcall, 0);
+#endif   /* TCP_ZEROCOPY */
+   }
+
+   get_timer = ftpticks + FTPTPS;   /* set tick to timeout this loop */
+
+#ifdef TCP_ZEROCOPY
+   /* different data transfer loops for zerocopy option */
+   for (;;)
+   {
+      PACKET pkt;
+
+      /* handle any packets the upcall has queued for us */
+      while (ftp->ftpsq.q_len > 0)
+      {
+         LOCK_NET_RESOURCE(NET_RESID);       /* syncronize ftpsq with upcall */
+         pkt = (PACKET)getq(&(ftp->ftpsq));
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         if (ftp->rxcode && ftp->rxcode != ESHUTDOWN) /* network error? */
+         {
+            tcp_pktfree(pkt);
+            continue;
+         }
+         bytes = pkt->nb_plen;
+         e = vfwrite(pkt->nb_prot, 1, bytes, ftp->filep);
+         tcp_pktfree(pkt);
+                     
+         if (e == 0) /* memory allocation failed, not enough space to write a file on the server */
+         {            
+            ftpputs(ftp, "452 Insufficient storage space, file write error\r\n");
+            reterr = 0; /* not a fatal error to abort */
+            notfatal = 1;
+            goto ftget_exit;
+         }
+         if (e != bytes)
+         {
+            dtrap();
+            ftpputs(ftp, "450 File unavailable, file write error\r\n");
+            reterr = 0; /* not a fatal error to abort */
+            notfatal = 1; 
+            goto ftget_exit;
+         }
+         /* force return to let other FTP sessions run if we have had CPU
+          * continuously for a while.
+          */
+         if (ftpticks > get_timer)
+            break;
+
+#if !defined(CHRONOS) && !defined(SUPERLOOP)
+         /* the yield here not only lets other tasks run, but if we have
+          * incoming data in the rcvdq it gives pktdemux a chance to get it
+          * into our queue via the upcall. This is not an Issue on Chronos
+          * since it runs the Net task at a higher priority, and it's
+          * dangerous on superloops.
+          */
+         tk_yield();    /* let other tasks run */
+#endif   /* neither CHRONOS nor SUPERLOOP */
+
+      }
+      if (ftp->rxcode)  /* network error? */
+      {
+         if (ftp->rxcode == ESHUTDOWN) /* file receive done */
+            reterr = 0;    /* no error */
+         else
+         {
+            reterr = 426;
+            ftpputs(ftp, "426 aborted, data recv error\r\n");
+         }
+         break;   /* break out of for loop */
+      }
+      return 0;      /* done for now, let other things run */
+   }
+#else /* not TCP_ZEROCOPY */
+   for (;;)
+   {
+      bytes = t_recv(ftp->datasock, ftp->filebuf, 1024, 0);
+      if (bytes > 0)
+      {
+         e = vfwrite(ftp->filebuf, 1, bytes, ftp->filep);
+         if (e == 0) /* memory allocation failed, not enough space to write a file on the server */
+         {            
+            ftpputs(ftp, "452 Insufficient storage space, file write error\r\n");
+            reterr = 0; /* not a fatal error to abort */
+            notfatal = 1;
+            break;
+         }
+         if (e != bytes)
+         {
+            dtrap();
+            ftpputs(ftp, "450 File unavailable, file write error\r\n");
+            reterr = 0; /* not a fatal error to abort */
+            notfatal = 1;
+            break;
+         }
+         ftp->lasttime = ftpticks;     /* reset timeout */
+      }
+      if (bytes < 0) /* error, no data (EWOULDBLOCK) or finished */
+      {
+         e = t_errno(ftp->datasock);
+         if (e == EWOULDBLOCK)
+            return 0;      /* no work right now, let other things run */
+         else  /* probably socket cloesed due to end of file */
+         {
+            bytes = 0;
+            break;   /* break our of read loop to exit code */
+         }
+      }
+      else if(bytes == 0)     /* another form of broken? */
+      {
+         /*         bytes = -1; */
+         ftp->state = FTPS_CLOSING;
+         break;
+      }
+      /*
+       * force return to let other FTP sessions run if we have had CPU
+       * continuously for a longish while.
+       */
+      if (ftpticks > get_timer)
+         return 0;
+   }     /* end of forever loop */
+
+   if (bytes < 0)
+   {
+      ftpputs(ftp, "426 aborted, data recv error\r\n");
+      reterr = 426;
+   }
+#endif   /* TCP_ZEROCOPY or not */
+
+ftget_exit:
+
+   /* first reply to user if xfer was OK */
+   if (!reterr && !notfatal)
+      ftpputs(ftp, "226 Transfer OK, Closing connection\r\n");
+
+   ftp_xfercleanup(ftp);
+   return reterr;
+}
+
+
+#ifdef TCP_ZEROCOPY
+
+/* FUNCTION: ftps_rxupcall()
+ *
+ * Upcall handler for TCP_ZEROCOPY data processing. This is passed
+ * packets directly  from the sockets layer for fast, copyless processing
+ *
+ * PARAM1: struct socket * so
+ * PARAM2: PACKET pkt
+ * PARAM3: int code
+ *
+ * RETURNS: 0 if packet accepted, -1 if not.
+ */
+
+int
+ftps_rxupcall(struct socket * so, PACKET pkt, int code)
+{
+   ftpsvr * ftps;
+
+   for (ftps = ftplist; ftps; ftps = ftps->next)
+      if ((long)ftps->datasock == SO2LONG(so))
+         break;
+
+   if (!ftps)     /* can't find socket? */
+   {
+      /* if no pkt and code is set, this may be a reset (or
+       * other cleanup) of a stale socket for which we have
+       * already cleared out the ftps. In this case just return,
+       * else dtrap & return error code.
+       */
+      if (pkt || (code == 0))
+      {
+         dtrap();    /* If pkt or no code, tel programmer */
+         return -1;  /* return error code */
+      }
+      return 0;      /* not an error */
+   }
+   ftps->rxcode = code;    /* save code */
+
+   if (pkt)    /* save pkt, if any */
+      putq( &(ftps->ftpsq), pkt );
+
+#ifndef SUPERLOOP
+   /* If the queue is filling, spin server task */
+   if(ftps->ftpsq.q_len > 10)
+   {
+      TK_WAKE(&to_ftpsrv);    /* make sure it's awake */
+      tk_yield();             /* let FTP server task spin */
+   }
+#endif   /* SUPERLOOP */
+
+   ftps->lasttime = ftpticks;    /* reset timeout */
+
+   return 0;
+}
+#endif   /* TCP_ZEROCOPY or not */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h
new file mode 100644
index 0000000..d2a5d61
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsrv.h
@@ -0,0 +1,159 @@
+/*
+ * FILENAME: FTPSRV.H
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES:
+ *
+ * PORTABLE: yes
+ */
+
+/* ftpsrv.h FTP server for WebPort HTTP server. 
+ * 1/12/97 - Created. John Bartas 
+ */
+#ifndef FTPSVR_H
+#define  FTPSVR_H 1
+
+
+#ifdef VFS_FILES     /* from inet\ipport.h */
+#include "vfsfiles.h"
+#else /* map "vf" vcalls to native file system */
+#ifndef vfopen /* allow override in ftpport.h */
+#define  vfopen(file,   mode) fopen(file, mode)
+#define  vfread(buf, ct,   size, fp)   fread(buf,  ct,   size, fp)
+#define  vfwrite(buf,   ct,   size, fp)   fwrite(buf, ct,   size, fp)
+#define  vgetc(fp)   fgetc(fp)
+#define  vfclose(fp) fclose(fp)
+#define  vunlink(fp) remove(fp)
+#define  VFILE FILE
+#endif   /* vfsopen */ 
+#endif   /* VFS_FILES */
+
+#define  FTP_PORT 21 /* standard FTP command port */
+
+struct userstruct {
+   char  username[FTPMAXUSERNAME];
+   char  password[FTPMAXUSERPASS];
+   char  home[FTPMAXPATH+2];  /* user's "home" directory */
+   void *   group;   /* for use by port */
+};
+typedef struct userstruct userinfo;
+
+#ifndef ip_addr
+#define  ip_addr     u_long
+#endif
+
+struct ftpsvrs {
+   struct ftpsvrs *  next; /* list link */
+   int      inuse;      /* re-entry semaphore */
+   SOCKTYPE sock;    /* client command socket */
+   SOCKTYPE datasock;/* client   data  socket */
+   int      state;      /* one of FTPS_ defines below */
+   u_long   lasttime;   /* ftptick when last action occured */
+   userinfo user;
+   int      logtries;   /* retry count of logins */
+   int      type;       /* ASCII or BINARY */
+   VFILE *  filep;      /* pointer to open file during IO */
+#ifdef IP_V6
+   ip6_addr ip6_host;      /* host if domain == AF_INET6 */
+#endif   /*  IP_V6 */
+   ip_addr  host;       /* FTP client */
+   u_short  dataport;   /* client data TCP port */
+   char *   lastreply;  /* last reply string sent, for debugging */
+   unsigned int   passive_state; /* state info for PASV command */
+   u_long   passive_cmd;   /* file XFER command in passive state */
+   u_short  server_dataport;  /* data port we listen on in passive mode */
+#ifdef DRIVE_LETTERS
+   char  drive[4];      /* usually "c:\0" */
+#endif   /* DRIVE_LETTERS */
+   char  cwd[FTPMAXPATH+1];   /* current directory, e.g. "/" or "/tmp/foo/" */
+   char  filename[FTPMAXPATH+FTPMAXFILE];
+   char  cmdbuf[CMDBUFSIZE];  /* buffer for comamnds from client */
+   unsigned    cmdbuflen;     /* number of bytes currently receieved in cmdbuf */
+   char  filebuf[FILEBUFSIZE];   /* file buffer for data socket & file IO */
+   unsigned    filebuflen;    /* amount of data actually in filebuf */
+#ifdef TCP_ZEROCOPY
+   PACKET   pkt;           /* packet currently queued for send */
+   queue ftpsq;            /* queue of received PACKETs */
+   int   rxcode;           /* last receive code */
+   int   iosize;           /* optimal IO size (TCP MSS) */
+#endif   /* TCP_ZEROCOPY */
+   int   wFlag;            /* flags for write blocked, et. al. */
+   int   domain;           /* AF_INET or AF_INET6 */
+};
+typedef struct ftpsvrs ftpsvr;
+
+extern   ftpsvr * ftplist; /* master list of FTP connections */
+
+extern   u_long   ftps_connects;
+extern   u_long   ftps_txfiles;
+extern   u_long   ftps_rxfiles;
+extern   u_long   ftps_txbytes;
+extern   u_long   ftps_rxbytes;
+extern   u_long   ftps_dirs;
+
+
+/* ftpsvr.states: */
+#define  FTPS_CONNECTING   1     /* connected, no USER info yet */
+#define  FTPS_NEEDPASS     2     /* user OK, need password */
+#define  FTPS_LOGGEDIN     3     /* ready to rock */
+#define  FTPS_SENDING      4     /* sending a data file in progress */
+#define  FTPS_RECEIVING    5     /* receiveing a data file in progress */
+#define  FTPS_CLOSING      9     /* closing */
+
+#define  FTPTYPE_ASCII     1
+#define  FTPTYPE_IMAGE     2
+
+/* ftpsvr.passive_state bits */
+#define  FTPS_PASSIVE_MODE 0x01  /* session is in passive mode */
+#define  FTPS_PASSIVE_CONNECTED  0x02  /* client has connected to data port */
+
+/* FTP server internal commands */
+char *   ftp_cmdpath(ftpsvr * ftp); /* extract path from cmd text */
+char *   uslash(char * path);       /* make path into UNIX slashes */
+
+/* required OS dependant routines */
+int      fs_dodir(ftpsvr * ftp, u_long ftpcmd);
+void     lslash(char * path);       /* make path into local slashes */
+int      fs_dir(ftpsvr * ftp);      /* verify drive:/path exists */
+int      fs_permit(ftpsvr * ftp);   /* verify user permission */
+int      fs_lookupuser(ftpsvr * ftp, char * username);
+
+/* macro to insert optional drive letter in sprintfs */
+#ifdef DRIVE_LETTERS
+#define  DRIVE_PTR(ftp) ftp->drive
+#else /* drive not supported, insert pointer to null */
+#define  DRIVE_PTR(ftp) ""
+#endif
+
+/* prototype server exported routines */
+ftpsvr * ftps_connection(SOCKTYPE);   /* new connection */
+void     ftp_leave_passive_state(ftpsvr * ftp);
+void     ftps_loop(void);    /* periodic loop (tick) */
+int      ftps_v4pasv(ftpsvr * ftp);
+int      ftps_v6pasv(ftpsvr * ftp);
+void     ftps_eprt(ftpsvr * ftp);
+void     ftps_epsv(ftpsvr * ftp);
+
+/* define the macro/routine FTP_TCPOPEN() based on version ifdefs */
+
+#ifdef IP_V4   /* begin version mess */
+#ifndef IP_V6  /* IP_V4 only */
+SOCKTYPE ftp4open(ftpsvr * ftp);
+#define FTP_TCPOPEN(ftp) ftp4open(ftp)
+#else          /* IP_V4 and IP_V6 */
+SOCKTYPE FTP_TCPOPEN(ftpsvr * ftp);   /* dual mode uses routine */
+#endif  /* IP_V4 */
+#else   /* IP_V6 only */
+SOCKTYPE ftp6open(ftpsvr * ftp);
+#define FTP_TCPOPEN(ftp) ftp6open(ftp)
+#endif  /* IP_V6 only */
+
+#endif   /* FTPSVR_H */
+
+/* end of file ftpsrv.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c
new file mode 100644
index 0000000..f8e05ff
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpssock.c
@@ -0,0 +1,759 @@
+/*
+ * FILENAME: ftpssock.c
+ *
+ * Copyright  2000 - 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *    Sockets specific code for FTP. FTP Implementations on APIs 
+ * other than sockets need to replace these.
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES: ftp_cmdcb(), ftp_datacb(), t_tcplisten(), 
+ * ROUTINES: FTP_TCPOPEN(), ftp4open(), ftp6open(), SO_GET_FPORT(), 
+ * ROUTINES: SO_GET_LPORT(), ftps_v4pasv(), ftps_eprt(), ftps_epsv(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* ftpssock.c 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * The Sockets-dependant portion of the FTP Server code. 
+ * 11/24/96 - Created by John Bartas 
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+#include "ftpsrv.h"
+
+#ifdef IP_V6
+#include "socket6.h"
+#endif
+
+
+#ifdef MINI_TCP
+
+#include "msring.h"
+extern struct msring ftps_msring;
+
+#ifndef SUPERLOOP
+extern TK_OBJECT(to_ftpsrv);
+#endif
+
+
+/* ftp_cmcb() - ftp command connection callback */
+int
+ftp_cmdcb(int code, M_SOCK so, void * data)
+{
+   int e = 0;
+
+   switch(code)
+   {
+   case M_OPENOK:          /* new socket is connected */
+      msring_add(&ftps_msring, so);
+      break;
+   case M_CLOSED:          /* TCP lost socket connection */
+      break;               /* let stale conn timer catch these */
+   case M_RXDATA:          /* received data packet, let recv() handle it */
+   case M_TXDATA:          /* ready to send more, http_loop will do it */
+      e = -1;        /* return nonzero code to indicate we don't want it */
+      break;
+   default:
+      dtrap();             /* not a legal case */
+      return 0;
+   }
+
+#ifdef SUPERLOOP
+   ftps_loop();            /* give loop a spin */
+#else /* multitasking */
+   TK_WAKE(&to_ftpsrv);    /* wake webserver task */
+#endif
+
+   USE_VOID(data);
+   return e;
+
+}
+
+/* ftp_datacb() - ftp data socket connection callback */
+
+int
+ftp_datacb(int code, M_SOCK so, void * data)
+{
+   int      e = 0;
+
+   switch(code)
+   {
+   case M_OPENOK:          /* new socket is connected */
+      /* if this FTP was listening for a data connection,
+       * switch its listening socket for the data socket
+       * and close the listening socket
+       */
+      if (so->app_data)
+      {
+         ftpsvr * ftp;
+         M_SOCK old_so;
+
+         ftp = (ftpsvr *)(so->app_data);
+         old_so = ftp->datasock;
+         ftp->datasock = so;
+         if (old_so != SYS_SOCKETNULL)
+         {
+            UNLOCK_NET_RESOURCE(NET_RESID);
+            m_close(old_so);
+            LOCK_NET_RESOURCE(NET_RESID);
+         }
+      }
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      m_ioctl(so, SO_NONBLOCK, NULL);   /* make socket non-blocking */
+      LOCK_NET_RESOURCE(NET_RESID);
+      break;
+   case M_RXDATA:
+      e = -1;              /* return nonzero code to indicate we don't want it */
+      break;
+   case M_TXDATA:
+   case M_CLOSED:          /* lost ftp data socket connection */
+      break;
+   default:
+      dtrap();             /* not a legal case */
+      return 0;
+   }
+
+#ifdef SUPERLOOP
+   ftps_loop();            /* give loop a spin */
+#else /* multitasking */
+   TK_WAKE(&to_ftpsrv);    /* wake webserver task */
+#endif
+
+   USE_VOID(data);
+   return e;
+}
+
+
+#endif /* MINI_TCP */
+
+
+/* FUNCTION: t_tcplisten()
+ * 
+ * t_tcplisten() implementation for NetPort sockets. Local port 
+ * (lport) is passed in local endian. If lport is 0 (wildcard), then 
+ * selected value is filled in to caller's variable. 
+ *
+ * PARAM1: u_short * lport
+ *
+ * RETURNS: returns a listening socket, or SYS_SOCKETNULL if error. 
+ */
+
+
+#ifdef MINI_TCP
+SOCKTYPE
+t_tcplisten(u_short * lport, int domain)
+{
+   int   e;
+   SOCKTYPE sock;
+   struct sockaddr_in   ftpsin;
+
+   ftpsin.sin_addr.s_addr = INADDR_ANY;
+   ftpsin.sin_port = htons(*lport);
+
+   if (*lport == FTP_PORT)
+      sock = m_listen(&ftpsin, ftp_cmdcb, &e);
+   else
+      sock = m_listen(&ftpsin, ftp_datacb, &e);
+
+   if (sock == INVALID_SOCKET)
+   {
+listenerr:
+      dprintf("error %d starting listen on ftp server\n", e);
+      return SYS_SOCKETNULL;
+   }
+
+   /* put socket in non-blocking mode */
+   e = m_ioctl(sock, SO_NBIO, NULL);
+   if (e != 0)
+   {
+      m_close(sock);
+      goto listenerr;
+   }
+
+   /* if wildcard port requested, return assigned port */
+   if (*lport == 0)
+      *lport = htons(sock->lport);
+
+   return sock;
+}
+
+#else /* full-sockets TCP */
+
+SOCKTYPE
+t_tcplisten(u_short * lport, int domain)
+{
+   int   e;
+   SOCKTYPE sock;
+
+   sock = t_socket(domain, SOCK_STREAM, 0);
+   if (sock == SYS_SOCKETNULL)
+      return sock;
+
+   switch(domain)
+   {
+#ifdef IP_V4
+      case AF_INET:
+      {
+         struct sockaddr_in   ftpsin;
+         int addrlen = sizeof(ftpsin);
+
+         ftpsin.sin_family = AF_INET;
+         ftpsin.sin_addr.s_addr = INADDR_ANY;
+         ftpsin.sin_port = htons(*lport);
+         e = t_bind(sock, (struct sockaddr*)&ftpsin, addrlen);
+         if (e != 0)
+         {
+            e = t_errno(sock);
+            dtrap();
+            dprintf("error %d binding tcp listen on port %d\n",
+             e, htons(*lport));
+            return SYS_SOCKETNULL;
+         }
+         if(*lport == 0)   /* was it wildcard port? */
+            *lport = htons(ftpsin.sin_port); /* return it to caller */
+      }
+      break;
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      case AF_INET6:
+      {
+         struct sockaddr_in6   ftpsin6;
+         int addrlen = sizeof(ftpsin6);
+
+         IP6CPY(&ftpsin6.sin6_addr, &in6addr_any);
+         ftpsin6.sin6_port = htons(*lport);
+         ftpsin6.sin6_family = AF_INET6;
+         e = t_bind(sock, (struct sockaddr *)&ftpsin6, addrlen);
+         if (e != 0)
+         {
+            e = t_errno(sock);
+            dtrap();
+            dprintf("error %d binding ftp6 listen on port %d\n",
+             e, htons(*lport));
+            return SYS_SOCKETNULL;
+         }
+         if (*lport == 0)  /* was it wildcard port? */
+            *lport = htons(ftpsin6.sin6_port); /* return it to caller */
+      }
+      break;
+#endif   /* IP_V6 */
+      default:
+         dtrap();    /* bad domain parameter */
+         return SYS_SOCKETNULL;
+   } /* end switch(domain) */
+
+   /* For FTP, put socket in non-block mode */
+   t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+   
+   e = t_listen(sock, 5);
+   if (e != 0)
+   {
+      e = t_errno(sock);
+      dprintf("error %d starting listen on ftp server\n", e);
+      return SYS_SOCKETNULL;
+   }
+
+   return sock;   /* return listen sock to caller */
+}
+#endif   /* notdef MINI_TCP */
+
+
+
+
+/* FUNCTION: ftp4open()
+ * FUNCTION: ftp6open()
+ * FUNCTION: FTP_TCPOPEN() (may be macro)
+ * 
+ * FTP's TCP active open routine(s). Provided for FTP server to
+ * can open an active TCP connection, such as FTP data. Versions
+ * are provided for IPv4 and IPv6. The routine is intended to
+ * be mapped to the macro FTP_TCPOPEN(), which is also provided 
+ * as a dual-mode function below.
+ *
+ * PARAM1: ftpsrv * ftp
+ *
+ * RETURNS: Returns conencted socket if OK, 
+ * SYS_SOCKETNULL on error 
+ */
+
+#ifndef FTP_TCPOPEN     /* see if it's defined */
+
+/* dual-mode version */
+SOCKTYPE 
+FTP_TCPOPEN(ftpsvr * ftp)
+{
+#ifdef IP_V4
+   if(ftp->domain == AF_INET)
+      return(ftp4open(ftp));
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   if(ftp->domain == AF_INET6)
+      return(ftp6open(ftp));
+#endif   /* IP_V6 */
+
+   dtrap(); /* bad domain setting */
+   return SYS_SOCKETNULL;
+}
+#endif   /* FTP_TCPOPEN */
+
+
+#ifdef IP_V4
+SOCKTYPE 
+ftp4open(ftpsvr * ftp)
+{
+   int   e; /* error holder */
+   SOCKTYPE sock;
+   struct sockaddr_in   ftpsin;
+
+   sock = t_socket(AF_INET, SOCK_STREAM, 0);
+   if (sock == SYS_SOCKETNULL)
+      return sock;
+
+   /* Change the socket options to allow address re-use. A customer 
+    * requested this to ease implementing an FTP client with multiple 
+    * connections.
+    */
+   if (ftp->server_dataport)
+   {
+#ifndef MINI_TCP
+      int  opt = 1;	/* boolean option value holder */
+
+      e = t_setsockopt(sock, 0, SO_REUSEADDR, &opt, sizeof(opt));
+      if (e != 0)
+      {
+         e = t_errno(sock);
+         dtrap();
+         dprintf("error %d setting SO_REUSEADDR on port %d\n",
+               e, ftp->server_dataport);
+         return SYS_SOCKETNULL;
+      }
+
+      /* Bind local port to the socket we just created */
+      ftpsin.sin_family = AF_INET;
+      ftpsin.sin_addr.s_addr = INADDR_ANY;
+      ftpsin.sin_port = htons(ftp->server_dataport);
+
+      e = t_bind(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin));
+      if (e != 0)
+      {
+         e = t_errno(sock);
+         dtrap();
+         dprintf("error %d binding tcp listen on port %d\n",
+            e, ftp->server_dataport);
+         return SYS_SOCKETNULL;
+      }
+#else
+      sock->lport = htons(ftp->server_dataport);
+#endif   /* MINI_TCP */
+   }
+
+   ftpsin.sin_addr.s_addr = htonl(ftp->host);
+   ftpsin.sin_port = htons(ftp->dataport);
+
+#ifdef MINI_TCP
+   sock->app_data = NULL;
+   e = m_connect(sock, &ftpsin, ftp_datacb);
+#else
+   ftpsin.sin_family = AF_INET;
+   e = t_connect(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin));
+#endif
+   if (e != 0)
+   {
+      dtrap();
+#ifndef MINI_TCP
+      t_errno(sock); /* so debugger can see error */
+#endif
+      return SYS_SOCKETNULL;
+   }
+
+   /* FTP data socket can be in blocking or non-blocking mode */
+#ifdef MINI_TCP
+   m_ioctl(sock, SO_NBIO, NULL);
+#else
+   t_setsockopt(sock, 0, SO_NBIO, NULL, 0);
+#endif
+   
+   return sock;
+}
+#endif   /* IP_V4 */
+
+/* FUNCTION: ftp6open()
+ * 
+ * v6 version of FTP4open()
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: Returns conencted socket if OK, SYS_SOCKETNULL on error 
+ */
+
+#ifdef IP_V6
+SOCKTYPE 
+ftp6open(ftpsvr * ftp)
+{
+   int         e; /* error holder */
+   SOCKTYPE    sock;
+   struct sockaddr_in6  ftpsin;
+   unshort     lport;
+
+   lport = ftp->server_dataport;
+
+   sock = t_socket(AF_INET6, SOCK_STREAM, 0);
+   if (sock == SYS_SOCKETNULL)
+      return sock;
+
+   /* Change the socket options to allow address re-use. A customer 
+    * requested this to ease implementing an FTP client with multiple 
+    * connections.
+    */
+   if (lport)
+   {
+      int opt = 1;
+
+      e = t_setsockopt(sock, 0, SO_REUSEADDR, &opt, sizeof(opt));
+      if (e != 0)
+      {
+         e = t_errno(sock);
+         dtrap();
+         dprintf("error %d setting SO_REUSEADDR on port %d\n", e, lport);
+         return SYS_SOCKETNULL;
+      }
+
+      /* Bind local port to the socket we just created */
+      ftpsin.sin6_family = AF_INET6;
+      IP6CPY(&ftpsin.sin6_addr, &ip6unspecified);
+      ftpsin.sin6_port = htons(lport);
+
+      e = t_bind(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin));
+      if (e != 0)
+      {
+         e = t_errno(sock);
+         dtrap();
+         dprintf("error %d binding tcp listen on port %d\n", e, lport);
+         return SYS_SOCKETNULL;
+      }
+   }
+
+   IP6CPY(&ftpsin.sin6_addr, &ftp->ip6_host);
+   ftpsin.sin6_port = htons(ftp->dataport);
+
+   ftpsin.sin6_family = AF_INET6;
+   e = t_connect(sock, (struct sockaddr*)&ftpsin, sizeof(ftpsin));
+   if (e != 0)
+   {
+      dtrap();
+      t_errno(sock); /* so debugger can see error */
+      return SYS_SOCKETNULL;
+   }
+
+   /* FTP data socket can be in blocking or non-blocking mode */
+   t_setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+   
+   return sock;
+}
+#endif   /* IP_V6 */
+
+
+#ifndef MINI_TCP
+
+/* FUNCTION: SO_GET_FPORT()
+ * 
+ * Return the foreign port of a socket. No error checking is done. It's
+ * up to the caller to make sure this socket is connected before calling.
+ *
+ * PARAM1: the socket
+ *
+ * RETURNS: Returns the foreign port of the passed socket. 
+ */
+
+unshort
+SO_GET_FPORT(SOCKTYPE sock)
+{
+   struct sockaddr   client;
+   int      clientsize;
+   unshort port;
+
+   clientsize = sizeof(client);
+   t_getpeername(sock, &client, &clientsize);
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only case: */
+   port = ((struct sockaddr_in *)(&client))->sin_port;
+#else    /* dual mode */
+   if(clientsize == sizeof(struct sockaddr_in))
+      port = ((struct sockaddr_in *)(&client))->sin_port;
+   else
+      port = ((struct sockaddr_in6 *)(&client))->sin6_port;
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+   port = ((struct sockaddr_in6 *)(&client))->sin6_port;
+#endif   /* v6 only */
+
+      return (ntohs(port));
+}
+
+/* FUNCTION: SO_GET_LPORT()
+ * 
+ * Return the foreign port of a socket. No error checking is done. It's
+ * up to the caller to make sure this socket is connected before calling.
+ *
+ * PARAM1: the socket
+ *
+ * RETURNS: Returns the foreign port of the passed socket. 
+ */
+
+unshort
+SO_GET_LPORT(WP_SOCKTYPE sock)
+{
+   struct sockaddr_in   client;
+   int      clientsize;
+   unshort port;
+
+   clientsize = sizeof(client);
+   t_getsockname(sock, (struct sockaddr *) &client, &clientsize);
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only case: */
+   port = ((struct sockaddr_in *)(&client))->sin_port;
+#else    /* dual mode */
+   if(clientsize == sizeof(struct sockaddr_in))
+      port = ((struct sockaddr_in *)(&client))->sin_port;
+   else
+      port = ((struct sockaddr_in6 *)(&client))->sin6_port;
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+   port = ((struct sockaddr_in6 *)(&client))->sin6_port;
+#endif   /* v6 only */
+
+      return (ntohs(port));
+}
+
+#endif   /* MINI_TCP */
+
+
+/* error reporting mechanism for open sessions. "text" should start
+ * with an FTP code (e.g. "425 " since it will be sent to client
+ * on the command connection.
+ */
+extern int ftpputs(ftpsvr * ftp, char * text);
+
+static  char *   err   = "425 Can't open data connection\r\n";
+
+#ifdef IP_V4
+int
+ftps_v4pasv(ftpsvr * ftp)
+{
+   SOCKTYPE sock;
+   u_short  port;
+   unsigned long addr;
+   char  responseBuf[80];
+
+   /* create a TCP socket to listen on, it will be the data socket.
+    * First set port to 0 so sockets will pick one for us
+    */
+   port = 0;
+   sock = t_tcplisten(&port, AF_INET); /* call API to start listen */
+   if (sock == SYS_SOCKETNULL)   /* if socket creation failed */
+   {
+      ftpputs(ftp, err);
+      return EIEIO;
+   }
+
+   /* get our address and data port so we can tell the client
+    * what address to connect to.
+    */
+
+#ifdef MINI_TCP
+   sock->app_data = (void *)ftp;     /* ptr back to FTP server state */
+   addr = ntohl(ftp->sock->lhost);   /* address from connected cmd sock */
+   port = ntohs(sock->lport);        /* port from listening data sock */
+#else    /* BSDish sockets */
+{
+   struct sockaddr_in   our_addr;
+   int   sa_len = sizeof(our_addr);
+
+   if (t_getsockname(ftp->sock,(struct sockaddr *) &our_addr, &sa_len))
+   {
+      /* tell client pasv failed */
+      ftpputs(ftp,err);
+      return t_errno(sock);
+   }
+
+   /* extract and convert to local endian our command socket address */
+   addr = ntohl(our_addr.sin_addr.s_addr);
+
+   /* get our port on the data socket */
+   if (t_getsockname(sock,(struct sockaddr *) &our_addr, &sa_len))
+   {
+      /* close the socket we just opened */
+      t_socketclose(sock);
+      /* tell client pasv failed */
+      ftpputs(ftp,err);
+      return t_errno(sock);
+   }
+
+   /* extract and convert to local endian our data socket port */
+   port = ntohs(our_addr.sin_port);
+}
+#endif   /* MINI_TCP or BSD sockets */
+
+   /* create our response which tells the client what address and
+    * port to connect to
+    */
+   sprintf(responseBuf,
+    "227 Entering Passive Mode (%d,%d,%d,%d,%d,%d)\r\n",
+    (int) (addr >> 24), (int) ((addr >> 16) & 0xff),
+    (int) ((addr >> 8) & 0xff), (int) (addr & 0xff),
+    (int) (port >> 8),(int) (port & 0xff));
+   ftpputs(ftp,responseBuf);
+
+   ftp->server_dataport = port;
+   ftp->datasock = sock;
+
+   return 0;
+}
+#endif /* IP_V4 */
+
+#ifdef IP_V6
+
+void
+ftps_eprt(ftpsvr * ftp)
+{
+   char *   cp;         /* scratch command buffer pointer */
+   char     delimit;    /* delimiter, from string */
+   int      domain;     /* domain from command */
+   unshort  port;       /* port number form command */
+   char     addr[16];   /* local address buffer (binary) */
+   char     responseBuf[80];
+
+   /* point into command buffer after "EPSV " string */
+   cp = &ftp->cmdbuf[5];
+   delimit = *cp++;     /* read delimiter */
+
+   if(*cp == '1')
+      domain = AF_INET;
+   else if(*cp == '2')
+      domain = AF_INET6;
+   else
+   {
+      ftpputs(ftp,"501 Unsupported EPRT domain\r\n");
+      return;
+   }
+   if(domain != ftp->domain)
+   {
+      dtrap();    /* in theory this is possible.... */
+      ftpputs(ftp,"501 Mismatched EPRT domain\r\n");
+      return;
+   }
+
+   cp = strchr(cp, delimit);     /* advance to address */
+   if(!cp) 
+      goto eprt_error;
+   cp++;
+   if(inet_pton(domain, cp, &addr[0]))
+   {
+      /* Send detailed parse error message to console. */
+      dprintf("FTP EPRT addr error: %s\n", pton_error);
+      goto eprt_error;
+   }
+
+   cp = strchr(cp, delimit);     /* advance to port */
+   if(!cp) 
+      goto eprt_error;
+   cp++;
+   
+   port = (unshort)atoi(cp);
+   if(port == 0)
+      goto eprt_error;
+
+   /* got everything, fill in the ftps and ack the command */
+   ftp->dataport = port;
+
+   if(domain == AF_INET6)
+      IP6CPY(&ftp->ip6_host, (ip6_addr*)(&addr));
+   else
+      ftp->host = *(ip_addr*)(&addr[0]);
+
+   sprintf(responseBuf, "229 EPRT OK on port %u\r\n", port);
+   ftpputs(ftp,responseBuf);
+   return;
+
+eprt_error:
+   ftpputs(ftp,"501 Bad EPRT command\r\n");
+   return;
+}
+
+void
+ftps_epsv(ftpsvr * ftp)
+{
+   SOCKTYPE    sock;
+   u_short     port;
+   char        responseBuf[80];
+   struct sockaddr_in6   our_addr;     /* v6 type socket */
+   int         sa_len;
+
+   /* Run the same tests as the v4 ftps_do_pasv() */
+   if (ftp->passive_state & FTPS_PASSIVE_CONNECTED)
+   {
+      ftpputs(ftp,"425 Data transfer already in progress\r\n");
+      return;
+   }
+
+   /* This will happen if the client had sent us a PASV and then sent 
+    * us another one without an intervening data transfer command. 
+    */
+   if (ftp->passive_state & FTPS_PASSIVE_MODE)
+   {
+      ftp_leave_passive_state(ftp);
+   }
+
+   /* create a TCP socket to listen on, it will be the data socket.
+    * First set port to 0 so sockets will pick one for us
+    */
+   port = 0;
+   sock = t_tcplisten(&port, ftp->domain); /* call API to start listen */
+   if (sock == SYS_SOCKETNULL)   /* if socket creation failed */
+   {
+      ftpputs(ftp, err);
+      return;
+   }
+
+   /* get our address and data port so we can tell the client
+    * what address to connect to.
+    */
+   sa_len = sizeof(our_addr);
+   if (t_getsockname(sock, (struct sockaddr *)&our_addr, &sa_len))
+   {
+      /* close the socket we just opened */
+      t_socketclose(sock);
+      /* tell client pasv failed */
+      ftpputs(ftp,err);
+      return;
+   }
+
+   /* extract and convert to local endian our data socket port */
+   port = ntohs(our_addr.sin6_port);
+
+   /* respons to the EPSV command. */
+   sprintf(responseBuf,
+    "229 Entering Extended Passive Mode (|||%d|)\r\n", port );
+   ftpputs(ftp,responseBuf);
+
+   /* we are now in passive mode, but the client hasn't connected yet */
+   ftp->passive_state = FTPS_PASSIVE_MODE;
+
+   /* we haven't received a data transfer command from the client yet */
+   ftp->passive_cmd = 0;
+
+   ftp->server_dataport = port;
+   ftp->datasock = sock;
+
+   return;
+}
+#endif /* IP_V6 */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c
new file mode 100644
index 0000000..96a3739
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ftp/ftpsvfs.c
@@ -0,0 +1,233 @@
+/*
+ * FILENAME: ftpsvfs.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: FTP
+ *
+ * ROUTINES: fs_dodir(), lslash(), fs_dir(), fs_permit(), 
+ *
+ * PORTABLE: no
+ */
+
+/* Additional Copyrights: */
+
+/* ftpsvfs.c 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * FS dependent portions of FTP serer. This version for InteNiche 
+ * VFS. 
+ * 7/21/96 - Taken out of ftpsrv.c - John Bartas 
+ */
+
+#include "ftpport.h"    /* TCP/IP, sockets, system info */
+#include "ftpsrv.h"
+
+#include "vfsfiles.h"
+#include "in_utils.h"
+
+int ftpputs(ftpsvr * ftp, char * text);
+void ftp_leave_passive_state(ftpsvr * ftp);
+
+
+
+/* FUNCTION: fs_dodir()
+ * 
+ * fs_dodir() - do a "dir" (or "ls" for UNIX weenies) on the current 
+ * ftp directory, write the resulting text out ftps->datasock, which 
+ * is open before this is called. How you do the DIR and buffer is 
+ * local to this function. Any tmp files or buffers should be cleaned 
+ * up before you return. This is the VFS-only version.
+ *
+ * PARAM1: ftpsvr * ftp
+ * PARAM2: u_long ftpcmd
+ *
+ * RETURNS: Returns 0 if OK, else -1 if error. 
+ */
+
+int
+fs_dodir(ftpsvr * ftp, u_long ftpcmd)
+{
+   char *   cp;
+   int   bytes_to_send;
+   int   bytes_sent;
+   int   rc;
+   int   blocked;
+   struct vfs_file * vfp;
+
+   ftpputs(ftp, "150 Here it comes...\r\n");
+
+   /* if we are already connected to the client because we are in
+      passive mode, don't create connection to client */
+   if (!(ftp->passive_state & FTPS_PASSIVE_CONNECTED))
+   {
+      /* create a data connection back to the client */
+      ftp->datasock = FTP_TCPOPEN(ftp);
+      if (ftp->datasock == SYS_SOCKETNULL)
+      {
+         ftpputs(ftp, "425 Can't open data connection\r\n");
+         return 0;   /* not actually OK, but we handled error */
+      }
+   }
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* for each file in the file list */
+   for (vfp = vfsfiles; vfp; vfp = vfp->next)
+   {
+      /* if client asked for long version of file listing */
+      if (ftpcmd == 0x4c495354)  /* "LIST" */
+      {
+         /* print month, day, hour and minute, as in :
+         -rw-r--r--   1 jharan   jharan  11772 Jan 19 13:31 install.log */
+         /* since we don't have time stamps in the VFS, we lie about 
+          * the date and time. if the VF_WRITE bit is set, the file 
+          * is read/write so we display the roughly analogous 
+          * Unix file mask corresponding to 666 else 444 
+          */
+         sprintf(ftp->filebuf,
+          "%s 0 root root %11ld %s %2d %02d:%02d %s",
+          ((vfp->flags & VF_WRITE) ? "-rw-rw-rw-" : "-r--r--r--"),
+          vfp->real_size,"Jan",1,1,1,vfp->name);
+      }
+      else
+         /* else just give the client the file name */
+      strcpy(ftp->filebuf,vfp->name);
+
+      /* append a newline sequence to the end of the file listing */
+      cp = ftp->filebuf + strlen(ftp->filebuf);
+      *cp++ = '\r';
+      *cp++ = '\n';
+      *cp = 0;
+
+      /* get number of bytes to transmit */
+      bytes_to_send = cp - ftp->filebuf;
+
+      blocked = 0;
+      /* while there are bytes left to transmit */
+      for (bytes_sent = 0; bytes_to_send > 0; )
+      {
+         /* try to send as much as is left to transmit */
+         rc = t_send(ftp->datasock,ftp->filebuf + bytes_sent,bytes_to_send,0);
+
+         /* this means some sort of error occurred */
+         if (rc < 0)
+         {
+            /* get socket error. If it's s (hopefully) transient buffer shortage
+             * then just wait a bit and try again, up to a limit:
+             */
+            rc = t_errno(ftp->datasock);
+            if((rc == EWOULDBLOCK) || (rc == ENOBUFS))
+            {
+               if(blocked++ < 100)     /* don't loop here forever... */
+               {
+                  tk_yield();    /* let system spin a bit */
+                  continue;
+               }
+            }
+            ftpputs(ftp, "426 aborted, data send error\r\n");
+            break;
+         }
+
+         /* socket could be non-blocking, which means t_send() might have
+            sent something less than what was requested */
+         bytes_to_send -= rc;
+         bytes_sent += rc;
+
+#ifndef BLOCKING_APP
+         /* if the whole thing wasn't sent, it wont get any better
+          * if you don't yield to receive side
+          */
+         if (bytes_to_send > 0)
+            tk_yield();
+#endif
+      }
+
+      /* if this happens, we broke in the loop above because of a
+         socket error */
+      if (bytes_to_send > 0)
+         break;
+   }
+
+   /* unlock the VFS */
+   vfs_unlock();
+
+   /* if vfp is now NULL, then we exited the above loop without an
+      error, so we can report that the transfer went ok */
+   if (!vfp)
+      ftpputs(ftp, "226 Transfer OK, Closing connection\r\n");
+
+   /* close the data connection and leave passive state if we in it */
+   ftp_leave_passive_state(ftp);
+
+   return 0;   /* good return */
+}
+
+
+
+
+/* FUNCTION: lslash()
+ * 
+ * lslash() - format universal (UNIX) slashes '/' into local type. 
+ * PC-DOS version. 
+ *
+ * PARAM1: char * path
+ *
+ * RETURNS: 
+ */
+
+void
+lslash(char * path)
+{
+   char *   cp;
+
+   for (cp = path; *cp; cp++)
+      if (*cp == '\\')     /* DOS slash? */
+      *cp = '/';     /* convert to normal slash */
+}
+
+/* fs_dir() - verify drive/directory exists. */
+
+
+
+/* FUNCTION: fs_dir()
+ * 
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: 
+ */
+
+int
+fs_dir(ftpsvr * ftp)
+{
+   /* for the sake of web browsers that start off with a cd /, we
+      will allow that the directory "/" exists */
+   if (!strcmp(ftp->filename,"/"))
+      return TRUE;
+   /* otherwise the VFS is flat, so there are no directories */
+   return FALSE;  /* path/name not found */
+}
+
+
+
+
+/* FUNCTION: fs_permit()
+ * 
+ * fs_permit() - check if the logged in user has permision for this 
+ * file operation. Returns TRUE or FALSE. 
+ *
+ * PARAM1: ftpsvr * ftp
+ *
+ * RETURNS: 
+ */
+
+int
+fs_permit(ftpsvr * ftp)    /* verify user permission */
+{
+   USE_ARG(ftp);
+
+   return TRUE;
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h
new file mode 100644
index 0000000..f62438f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/app_ping.h
@@ -0,0 +1,145 @@
+/*
+ * FILENAME: app_ping.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Header file for  app_ping.c
+ * NOTE - this file may by included even if PING_APP is not defined in the
+ * system build, since UDP_ECHO and others use some of these values.
+ *
+ * MODULE: TCP
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef APP_PING_H
+#define  APP_PING_H     1
+
+#include "in_utils.h"
+
+struct PingInfo 
+{
+   u_long   delay;         /* delay between successive pings */
+   u_long   length;        /* ping packet length */
+   ip_addr  ipadd;   
+   u_long   nextping;      /* cticks value to do next ping */
+   long     times;         /* number of times to ping */
+   int      out;
+   int      in;
+   GEN_IO   pio;           /* To communicate with invocator of ping */
+   struct PingInfo * next; /* Next ping packet */
+};
+
+typedef struct PingInfo * PING_INFO ;
+
+extern   ip_addr  activehost; /* default ping host */
+
+#define  TIMEFOR1TICK      (1000/TPS)  /* Time between each tick in millisecs */
+
+
+int         ping_init(void);
+PING_INFO   ping_new (void);
+int         ping_delete(PING_INFO p);
+int         ping_addq(PING_INFO p);
+int         ping_delq(PING_INFO p);
+PING_INFO   ping_search(GEN_IO pio);
+int         ping_start(void * pio);
+int         ping_send(PING_INFO p);
+int         ping_end(void * pio);
+int         ping_setdelay(void * pio);
+int         ping_setlength(void * pio);   /* menu routine to set default ping size*/
+int         ping_sethost(void * pio);     /* set default host for pings, et.al. */
+int         pingUpcall(PACKET p);
+void        ping_check(void);
+PING_INFO   ping_demux(ip_addr fhost);
+int         ping_stats(void * pio);
+
+#define     PING_ALLOC(size)  npalloc(size) 
+#define     PING_FREE(ptr)    npfree(ptr)
+
+/* Note that some of the error codes listed below have been
+ * reused by other functions in this module.
+ */
+#define     PINGERRBASE       200
+
+/* List of error codes returned by ping_delq() */
+#define     PING_DELQ_BAD_OBJECT       (PINGERRBASE+11)
+#define     PING_DELQ_Q_EMPTY          (PINGERRBASE+12)
+#define     PING_DELQ_OBJ_NOT_FOUND    (PINGERRBASE+13)
+
+/* List of error codes returned by ping_delete() */
+#define     PING_DEL_NULL_ARGUMENT     (PINGERRBASE+21)
+
+/* List of error codes returned by ping_start() */
+#define     PING_ST_NOIP               (PINGERRBASE+31)
+#define     PING_ST_BAD_ARG2           (PINGERRBASE+32)
+#define     PING_ST_ALLOC_ERR          (PINGERRBASE+33)
+
+/* List of error codes returned by ping_end() */
+#define     PING_END_NO_SESSION        (PINGERRBASE+41)
+
+/* List of error codes returned by ping_setdelay() */
+#define     PING_DELAY_BAD_ARG         (PINGERRBASE+51)
+
+/* List of error codes returned by ping_setlength() */
+#define     PING_LEN_BAD_ARG           (PINGERRBASE+61)
+
+/* types of messages sent to PING client task from the console task,
+ * Telnet server task, or timer tick task.  These messages provide 
+ * configuration parameters, initiate (or terminate) ping requests, 
+ * and provide periodic timeout notification.
+ */
+#define PING_CNTRL_START_PING     0x1
+#define PING_CNTRL_END_PING       0x2
+#define PING_CNTRL_SET_PARM       0x3
+#define PING_CNTRL_PERIODIC_TIMER 0x4
+#define PING_CNTRL_LIST_STATS     0x5
+#define PING_DATA_ECHO_REPLY      0x6
+
+/* type of parameter sent in PING_CNTRL_SET_PARM message */
+#define PARM_TYPE_HOST   0x1
+#define PARM_TYPE_DELAY  0x2
+#define PARM_TYPE_LENGTH 0x3
+
+/* structure of message sent to PING client task.  Note that not all 
+ * parameters are used in all of the messages.
+ */
+struct pingtask_msg
+{
+   struct pingtask_msg * next;
+   u_char type;
+   u_long parm1;
+   u_long parm2;
+   u_long parm3;
+   u_long parm4;
+   u_long parm5;
+};
+
+/* Counters used by PING client code to keep track of error conditions 
+ * encountered during processing
+ */
+struct ping_err
+{
+   u_long alloc_fail;
+   u_long bad_msgtype;
+   u_long bad_parmtype;
+   u_long empty_q;
+};
+
+/* counters for the number of messages of various types received by 
+ * the PING client task
+ */
+struct ping_msg_stats
+{
+   u_long start_ping;
+   u_long end_ping;
+   u_long set_parm;
+   u_long periodic_timer;
+   u_long list_stats;   
+   u_long echo_reply;
+};
+
+extern struct queue pingRcvq;     /* contains messages from other tasks */
+
+#endif   /* APP_PING_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h
new file mode 100644
index 0000000..8904e42
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/arp.h
@@ -0,0 +1,127 @@
+/*
+ * FILENAME: arp.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * ARP related constats and definitions.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990 by NetPort Software. */
+
+
+#ifndef _ARP_H
+#define  _ARP_H   1
+
+#define  ET_ARP      htons(0x0806)  /* net endian 0x0806 */
+#define  MACADDSIZ   6              /* biggest mac address we use */
+
+
+/* The ARP table entry structure. It is empty (unused) if t_pro_addr 
+ * == 0L. The first three entrys match those specified by the MIB in 
+ * rfc 1156 for the Address Translation Tables. 
+ */
+ 
+struct arptabent  {
+   unsigned long  t_pro_addr;       /* protocol address */
+   unsigned char  t_phy_addr[6];    /* physical addr */
+   struct net *   net;     /* interface for which this entry is valid */
+   PACKET   pending;       /* packets waiting for resolution of this arp */
+   u_long   createtime;    /* time entry was created (cticks) */
+   u_long   lasttime;      /* time entry was last referenced */
+   unshort  flags;         /* mask of the ET flags */
+};
+
+#define  MAXARPS        8  /* maximum mumber of arp table entries */
+extern   struct arptabent  arp_table[MAXARPS];  /* the actual table */
+
+/* arp function prototypes */
+int   etainit (void);         /* init arp package */
+int   arprcv (PACKET);        /* arp received packet upcall */
+void  at_entry (ip_addr, char*, int);   /* make an entry in the arp table */
+void  arpReply (PACKET );
+int   et_send (PACKET pkt, struct arptabent * tp);
+int   send_arp (PACKET pkt, ip_addr dest_ip);
+int   send_via_arp (PACKET pkt, ip_addr dest_ip);
+
+struct arptabent * find_oldest_arp(ip_addr dest_ip);
+struct arptabent * make_arp_entry(ip_addr dest_ip, NET net);
+
+#ifdef DYNAMIC_IFACES
+int   clear_arp_entries(ip_addr dest_ip, NET ifp);
+#endif
+
+/* arp stats - In addition to MIB */
+extern   unsigned    arpReqsIn;     /* requests received */
+extern   unsigned    arpReqsOut;    /* requests sent */
+extern   unsigned    arpRepsIn;     /* replys received */
+extern   unsigned    arpRepsOut;    /* replys sent */
+
+
+/* Plummer's internals. All constants are already byte-swapped. */
+#define     ARETH      htons(1)       /* ethernet hardware type */
+#define     ARREQ      htons(1)       /* byte swapped request opcode */
+#define     ARREP      htons(2)       /* byte swapped reply opcode */
+#define     ARPIP      htons(0x0800)  /* IP type in net endian */
+#define     ARPHW      htons(1)       /* arp hardware type for ethernet, in net endian */
+#define     ARP8023HW  htons(6)       /* arp hardware type for IEEE 802.3 in net endian */
+
+/* have two arp headers because of problems with some hardware insisting
+ * 32 bit fields must be on 32 bit boundaries.
+ */
+ 
+#ifdef NO_CC_PACKING
+/* the ARP header as it appears on the wire: */
+struct arp_wire   {
+   unshort     ar_hd;      /* hardware type */
+   unshort     ar_pro;     /* protcol type */
+   char        ar_hln;     /* hardware addr length */
+   char        ar_pln;     /* protocol header length */
+   unshort     ar_op;      /* opcode */
+   char        data[20];   /* send IP, send eth, target IP, target eth */
+};
+
+/* offsets to fields in arp_wire->data[] */
+#define  AR_SHA   0
+#define  AR_SPA   6
+#define  AR_THA   10
+#define  AR_TPA   16
+#endif   /* NO_CC_PACKING */
+
+/* THE ARP header structure, with special macros around it to help
+ * with declaring it "packed". Also se NO_CC_PACKING #define.
+ */
+
+START_PACKED_STRUCT(arp_hdr)  /* macro to optionally pack struct */
+   unshort     ar_hd;      /* hardware type */
+   unshort     ar_pro;     /* protcol type */
+   char        ar_hln;     /* hardware addr length */
+   char        ar_pln;     /* protocol header length */
+   unshort     ar_op;      /* opcode */
+   char        ar_sha[6];  /* sender hardware address */
+   ip_addr     ar_spa;     /* sender protocol address */
+   char        ar_tha[6];  /* target hardware address */
+   ip_addr     ar_tpa;     /* target protocol address */
+END_PACKED_STRUCT(arp_hdr)
+
+/* bits for tp->flags */
+#define  ET_ETH2  1     /* this IP address uses Ethernet II */
+#define  ET_SNAP  2     /* this IP address uses snap headers */
+
+
+#ifdef IEEE_802_3
+/* 8 bytes of useless filler, required for IEEE 802.3 support */
+struct snap_hdr
+{
+   u_char   llc_etc[6];
+   unshort  type;       /* the pkt protocol, 0x0800 for IP, etc. */
+};
+#endif   /* IEEE_802_3 */
+
+#endif   /* _ARP_H 1 */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h
new file mode 100644
index 0000000..91a259c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/bsdsock.h
@@ -0,0 +1,154 @@
+/* FILENAME: bsdsock.h
+ *
+ * Copyright 2000 InterNiche Technologies Inc.  All rights reserved.
+ *
+ * BSD sockets porting aid
+ *
+ * #define BSD_SOCKETS in your ipport.h_h, and #include this in your
+ * application source to get the BSD-flavored sockets API.
+ *
+ * Then you get:
+ *   BSD_SOCKET as a retargetable "socket" type
+ *   BSD_SIZE_T as a retargetable "size" type
+ *   BSD_TIMEVAL_T as a retargetable "struct timeval" type
+ *   bsd_...() retargetable functions and macros for the BSD sockets API
+ *
+ * ...so you can write your code using these, and then re-target 
+ * them to various sockets-like platforms (we supply the InterNiche
+ * target, but these should be straightforward for modern Un*x 
+ * and mostly so for Winsock).
+ *
+ * MODULE: misclib
+ * ROUTINES: bsd_bind(), bsd_close(), bsd_connect(), bsd_errno(), 
+ *           bsd_listen(), bsd_recv(), bsd_send(), bsd_sendto(), 
+ *           bsd_shutdown(), bsd_socket()
+ * PORTABLE: yes
+ *
+ */
+
+#ifndef BSDSOCK_H
+#define BSDSOCK_H
+
+#include "tcpport.h"
+#include "socket.h"
+#include "sockcall.h"
+#include "nptcp.h"
+
+/*
+ * BSD_SOCKET - the type of a socket.  For InterNiche Release 1.x (x
+ * <= 7) sockets this is "long", so that is the default.  For BSD it
+ * would be "int".  For Winsock it would be "SOCKET".  Don't change
+ * this, override this default with your own macro prior to including
+ * this file.  
+ */
+#ifndef BSD_SOCKET
+#define BSD_SOCKET long
+#endif
+
+/*
+ * BSD_SIZE_T - the "size" type.  For InterNiche Release 1.x (x <= 7)
+ * this is "int".  
+ */
+#ifndef BSD_SIZE_T
+#define BSD_SIZE_T int
+#endif
+
+/*
+ * BSD_IN_ADDR_T - the "Internet Address" type.  Must be able to 
+ * hold a 32-bit IPv4 address.
+ */
+#ifndef BSD_IN_ADDR_T
+#define BSD_IN_ADDR_T unsigned long
+#endif
+
+/*
+ * BSD_TIMEVAL_T - the "struct timeval" type.  bsd_select() needs a
+ * structure with these fields for its timeout parameter.
+ */
+#ifndef BSD_TIMEVAL_T
+struct timeval
+{
+   long tv_sec;     /* seconds */
+   long tv_usec;    /* and microseconds */
+};
+#define BSD_TIMEVAL_T struct timeval
+#endif
+
+/*
+ * ioctl() request definitions
+ *
+ * The only ioctl() request presently supported is FIONBIO, so 
+ * rather than define the whole _IOC macro family we just 
+ * define FIONBIO.
+ */
+#define FIONBIO SO_NONBLOCK
+
+/*
+ * Some BSD sockets calls can be mapped to InterNiche sockets calls
+ * with straightforward macro definitions, so we do.
+ */
+#define bsd_bind(s, addr, addrlen)     t_bind((s), (addr), addrlen)
+#define bsd_close(s)                   t_socketclose((s))
+#define bsd_connect(s, addr, addrlen)  t_connect((s), (addr), addrlen)
+#define bsd_listen(s, backlog)         t_listen((s), (backlog))
+#define bsd_recv(s, buf, len, flags)   t_recv((s), (buf), (len), (flags))
+#define bsd_send(s, buf, len, flags)   t_send((s), (buf), (len), (flags))
+#define bsd_sendto(s, msg, len, flags, to, tolen) \
+            t_sendto((s), (msg), (len), (flags), (to), tolen)
+#define bsd_shutdown(s, how)           t_shutdown((s), (how))
+/* 
+ * Altera Niche Stack Nios port modification:
+ * fix build warning
+ */
+#ifdef ALT_INICHE
+#define bsd_socket(dom, type, proto)   t_socket((dom), (type), (proto))
+#else
+#define bsd_socket(dom, type, proto)   t_socket((dom), (type), 0)
+#endif
+/*
+ * BSD errno isn't the best choice for a multithreaded environment.
+ * The InterNiche sockets API provides a per-socket error which can be
+ * read via t_errno(s).  We suppose this could be re-targeted to errno
+ * for a Unix-like environment (or perhaps better, the SO_ERROR socket
+ * option), or WSAGetLastError() for a Winsock environment.  
+ */
+#define bsd_errno(s)                   t_errno((s))
+
+/*
+ * Some other BSD sockets calls require functions to do the mapping
+ * to InterNiche sockets calls; we provide the prototypes for those
+ * functions here, and the implementations in misclib/bsdsock.c.
+ */
+BSD_SOCKET bsd_accept(BSD_SOCKET s, 
+                      struct sockaddr * addr, int * addrlen);
+int bsd_getpeername(BSD_SOCKET s,
+                    struct sockaddr * addr, int * addrlen);
+int bsd_getsockname(BSD_SOCKET s,
+                    struct sockaddr * addr, int * addrlen);
+int bsd_getsockopt(BSD_SOCKET s,
+                   int level,
+                   int name,
+                   void * opt, int * optlen);
+BSD_IN_ADDR_T bsd_inet_addr(char * cp);
+int bsd_inet_aton(char * cp, struct in_addr * pin);
+char * bsd_inet_ntoa(struct in_addr in);
+int bsd_ioctl(BSD_SOCKET s, unsigned long request, ...);
+int bsd_recvfrom(BSD_SOCKET s,
+                 void * buf,
+                 BSD_SIZE_T len,
+                 int flags,
+                 struct sockaddr * from, int * fromlen);
+#ifdef SO_SELECT
+int bsd_select(int nfds,
+               fd_set * readfds,
+               fd_set * writefds,
+               fd_set * exceptfds,
+               struct timeval * timeout);
+#endif /* SO_SELECT */
+int bsd_setsockopt(BSD_SOCKET s,
+                   int level,
+                   int name,
+                   void * opt, int optlen);
+
+#endif  /* BSDSOCK_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h
new file mode 100644
index 0000000..3bdcd8b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/comline.h
@@ -0,0 +1,116 @@
+/*
+ * FILENAME: comline.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Definitions for comm lines to be used under PPP and SLIP.
+ *
+ * MODULE: INET
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1994, 1995 by NetPort Software. */
+
+
+#ifndef _COMLINE_H_
+#define  _COMLINE_H_
+
+#include "netbuf.h"
+
+/* Values for Line State ln_state. */
+
+typedef enum  {
+   LN_INITIAL,       /* not set up yet */
+   LN_DISCONNECTED,  /* line not connected (idle) */
+   LN_AUTOANS,       /* line ready (e.g. mode in autoanswer mode) */
+   LN_CONNECTING,    /* line is connecting (e.g. modem dialing) */
+   LN_CONNECTED,
+   LN_DISCONNECTING, /* e.g. modem in the process of hanging up */
+   LN_BROKEN,        /* hardware is missing, misconfigured, or broken */
+   LN_RESETTING      /* line is being reset - ignore incoming chars */
+} ln_states;
+
+
+/* API structure for PPP and SLIP line IO. One of these structures is
+ * created for each instance where a line layer, (UART, modem, slip, PPP,
+ * etc.) interfaces with another line layer. Example: PPP over AT modem
+ * over RS232 would have two of these, one between PPP and modem and
+ * another between modem and RS232 UART.
+ */
+
+struct com_line
+{
+   /* bring/check line up */
+   int   (*ln_connect)(struct com_line * lineptr);
+
+   /* disconnect the line */
+   int   (*ln_disconnect)(struct com_line *);
+
+   /* one of the send routines (the next two) may be NULL */
+   int   (*ln_putc)(struct com_line *, int byte);   /* send single char */
+   int   (*ln_write)(struct com_line *, PACKET pkt);
+
+   /* speed and state of the lower module */
+   long        ln_speed;      /* most recent detected speed */
+   ln_states   ln_state;
+
+   int   (*ln_getc)(struct com_line *, int byte);   /* receive single char */
+
+   /* types for the layers above and below this interface  */
+   int   upper_type;
+   int   lower_type;
+
+   void * upper_unit;         /* depends on upper_type, usually M_PPP */
+   int   lower_unit;          /* legacy ID for lower (UART level) drivers */
+};
+
+typedef struct com_line * LINEP;
+
+/* Values for upper_type and lower_type. Note that a modem could
+ * be both the lower layer to PPP code and upper layer to a
+ * UART driver.
+ */
+
+#define  LN_PPP      1     /* upper layer is PPP */
+#define  LN_SLIP     2     /* upper layer is SLIP */
+#define  LN_UART     3     /* lower layer is a UART */
+#define  LN_ATMODEM  4     /* upper/lower layer is a modem */
+#define  LN_PPPOE    5     /* lower layer is PPPOE */
+#define  LN_LBXOVER  6     /* lower is loopback crossover (for test) */
+#define  LN_PORTSET  7     /* (init) lower will be set by callback */
+
+
+/* UARTs under this line struct should support this API: */
+
+/* logical line operations on UARTs: */
+extern   int   ln_uinit(LINEP line);        /* assigned unit, sets up structs */
+extern   int   ln_uconnect(LINEP line);      /* move to connected state */
+extern   int   ln_udisconnect(LINEP line);   /* move to disconnected state */
+extern   int   ln_uputc(LINEP line, int byte);   /* send a single byte */
+
+
+/* lowest level UART API */
+extern   int   uart_init(int unit);   /* sets up hardware */
+extern   int   uart_putc(int unit, u_char);   /* send character to comm port */
+extern   int   uart_getc(int unit);    /* read next buffered char from com port */
+extern   int   uart_ready(int unit);   /* returns TRUE if uart is ready to send a char */
+extern   void  uart_close(int unit);   /* undoes uart_init */
+extern   int   uart_stats(void * pio, int unit);
+
+/* Struct contaning all configuration global params for Comport */
+
+#ifdef USE_COMPORT
+struct ComPortCfg
+{
+   int   comport;             /* PC comm port to default to */
+   int   LineProtocol;        /* 1=PPP, 2=SLIP */
+};
+
+extern struct ComPortCfg comportcfg;
+#endif   /* USE_COMPORT */
+
+#endif   /* _COMLINE_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h
new file mode 100644
index 0000000..d5ff81f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_api.h
@@ -0,0 +1,245 @@
+/*
+ * FILENAME: crypt_api.c
+ *
+ * Copyright 1999-2004 by InterNiche Technologies Inc. All rights reserved.
+ *
+ *
+ * ROUTINES: 
+ * ROUTINES: 
+ *
+ */
+#ifndef _CRYPT_API_H_
+#define _CRYPT_API_H_
+
+#define PRINT_BUFFER
+
+#define AES128_KEY_SIZE 16
+#define AES128_IV_SIZE  16
+#define DES64_KEY_SIZE 8
+#define DES64_IV_SIZE  8
+#define TDES192_KEY_SIZE 24
+#define TDES192_IV_SIZE  8
+
+
+#define MD5_DIGEST_LENGTH	16
+#define SHA1_DIGEST_LENGTH	20
+#define MAX_IV_SIZE		16	/* Max size of encryption IV */
+#define MAX_BLOCK_SIZE		16	/* Max size of encryption block */
+#define MAX_AUTH_DATA_SIZE	12	/* Bytes (96-bits) */
+#define MAX_DIGEST_SIZE		64	/* SHA-512 digest size in bytes */
+#define MAX_AUTH_KEY_SIZE	64	/* Max size of authentication key */
+#define MAX_ENCR_KEY_SIZE	64	/* Max size of encryption key */
+#define HMAC_MAX_CBLOCK     64
+#define ENTROPY_NEEDED 20  /* require 160 bits = 20 bytes of randomness */
+
+/*
+ * IPSEC Algorithms
+ */
+/* ESP Transforms from RFC 2407 (IPSEC-DOI) */
+#define ALG_ESP_DES_IV4		1
+#define ALG_ESP_DES		    2
+#define ALG_ESP_3DES		3
+#define ALG_ESP_RC5		    4
+#define ALG_ESP_IDEA		5
+#define ALG_ESP_CAST	 	6
+#define ALG_ESP_BLOWFISH	7
+#define ALG_ESP_3IDEA		8
+#define ALG_ESP_DES_IV32	9
+#define ALG_ESP_RC4		    10
+#define ALG_ESP_NULL	 	11
+#define ALG_ESP_AES	 	    12
+
+/* Private values used only at the API level. Not used internally */
+#define ALG_ESP_AES_128	 	201
+#define ALG_ESP_AES_192	 	202
+#define ALG_ESP_AES_256	 	203
+
+/* ESP Authentication Algorithms */
+#define ALG_ESP_HMAC_NULL	  0	 /* private value, not defined by spec */
+#define ALG_ESP_HMAC_MD5	  1
+#define ALG_ESP_HMAC_SHA	  2
+#define ALG_ESP_HMAC_SHA_256  5
+#define ALG_ESP_HMAC_SHA_384  6
+#define ALG_ESP_HMAC_SHA_512  7
+
+/* AH Transforms from RFC 2407 (IPSEC-DOI) */
+#define ALG_AH_NULL		  0
+#define ALG_AH_MD5		  2
+#define ALG_AH_SHA		  3
+#define ALG_AH_DES		  4
+#define ALG_AH_SHA_256	  5
+#define ALG_AH_SHA_384	  6
+#define ALG_AH_SHA_512	  7
+
+/* Compression Algorithms from RFC 2407 (IPSEC-DOI) */
+#define ALG_IPCOMP_OUI		1
+#define ALG_IPCOMP_DEFLATE	2
+#define ALG_IPCOMP_LZS		3
+
+typedef struct DigestAlgs_s 
+{
+   int alg;
+   int digest_len;
+   int ctx_len;
+   void (*init)(void *ctx);
+   void (*update)(void *ctx, unsigned char *data, int len);
+   void (*final)(unsigned char *digest, void *ctx);
+} DigestAlgs;
+
+typedef struct HmacContext_s 
+{
+	unsigned char ipad[64];
+	unsigned char opad[64];
+	const DigestAlgs *digest_alg;
+	void *digest_ctx;
+} HmacContext;
+
+typedef struct KeyedContext_s 
+{
+	int	keylen;
+	DigestAlgs	*digest_alg;
+	void	*key;
+	void	*digest_ctx;
+} KeyedContext;
+
+typedef struct EncrAlgs_s 
+{
+	int	alg;
+	int	blocksize;	/* Algorithm block length (bytes) */
+    int (*crypt)(unsigned char *in, unsigned int in_len, unsigned char *out, 
+       unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+} EncrAlgs;
+
+EncrAlgs *enc_alg_lookup(int alg);
+/*
+ * Generic HMAC authentication APIs
+ */
+HmacContext	*hmac_init(int alg, unsigned char *key, int keylen);
+void hmac_update(HmacContext *hctx, unsigned char *data, int len);
+void hmac_final(HmacContext *hctx, unsigned char *digest, int len);
+int	hmac_digest_len(HmacContext *hctx);
+
+/*
+ * Generic Keyed authentication APIs
+ */
+KeyedContext *keyed_init(int alg, unsigned char *key, int keylen);
+void keyed_update(KeyedContext *kctx, unsigned char *data, int len);
+void keyed_final(KeyedContext *kctx, unsigned char *digest, int len);
+int	keyed_digest_len(KeyedContext *kctx);
+
+int aes_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+int bf_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+
+int null_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+
+int des_do_ncbc(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+
+int des_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+
+int tdes_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned int out_len, unsigned char *key, unsigned char *iv, int enc);
+
+int hmac_ipsec_do(int alg_id, unsigned char *alg_key, int alg_keylen, void *in, 
+   unsigned int in_offset, unsigned char *digest, unsigned int digest_len);
+
+int keyed_do_ipsec(int alg_id, unsigned char *alg_key, int alg_keylen, void *in, 
+   unsigned int in_offset, unsigned char *digest, unsigned int digest_len);
+
+void md4_do(unsigned char *in, unsigned int in_len, unsigned char *digest);
+char bits2hex(unsigned int num);
+void convert2hex(char *out, char *msg, int size);
+int sha1_do(unsigned char *digest, unsigned char *text, unsigned int text_len);
+unsigned char *SHA1(const unsigned char *d, unsigned long n, unsigned char *md);
+int sha1_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest);
+int sha1_do3(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, char *digest);
+int sha1_do4(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, char *digest);
+int sha1_do5(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, 
+   unsigned char *s5, int s5_len, char *digest);
+int sha1_do6(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, 
+   unsigned char *s5, int s5_len, unsigned char *s6, int s6_len, char *digest);
+
+int md5_do(unsigned char *digest, unsigned char *text, unsigned int text_len);
+unsigned char *MD5(const unsigned char *d, unsigned long n, unsigned char *md);
+int md5_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest);
+int md5_do3(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, char *digest);
+int md5_do4(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, char *digest);
+int md5_do5(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, 
+   unsigned char *s5, int s5_len, char *digest);
+int md5_do6(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, 
+   unsigned char *s3, int s3_len, unsigned char *s4, int s4_len, 
+   unsigned char *s5, int s5_len, unsigned char *s6, int s6_len, char *digest);
+int des_do_ecb(unsigned char *in, unsigned char *out, unsigned char *key, int enc);
+
+int sha256_do(unsigned char *digest, unsigned char *text, unsigned int text_len);
+int sha256_do2(unsigned char *s1, int s1_len, unsigned char *s2, int s2_len, char *digest);
+int sha384_do(unsigned char *digest, unsigned char *text, unsigned int text_len);
+int sha512_do(unsigned char *digest, unsigned char *text, unsigned int text_len);
+
+int p2k_md5(unsigned char *digest, unsigned char *text, unsigned int text_len);
+
+#ifdef PRINT_BUFFER
+void print_buffer(unsigned char *buf, int len);
+#endif
+
+void *alloc_md5_ctx(void);
+void x_md5_init(void *ctx);
+void x_md5_update(void *ctx, unsigned char *data, int len);
+void x_md5_final(unsigned char *digest, void *ctx);
+
+void *alloc_sha1_ctx(void);
+void x_sha1_init(void *ctx);
+void x_sha1_update(void *ctx, unsigned char *data, int len);
+void x_sha1_final(unsigned char *digest, void *ctx);
+
+void *alloc_sha256_ctx(void);
+void x_sha256_init(void *ctx);
+void x_sha256_update(void *ctx, unsigned char *data, int len);
+void x_sha256_final(unsigned char *digest, void *ctx);
+
+void *alloc_sha384_ctx(void);
+void x_sha384_init(void *ctx);
+void x_sha384_update(void *ctx, unsigned char *data, int len);
+void x_sha384_final(unsigned char *digest, void *ctx);
+
+void *alloc_sha512_ctx(void);
+void x_sha512_init(void *ctx);
+void x_sha512_update(void *ctx, unsigned char *data, int len);
+void x_sha512_final(unsigned char *digest, void *ctx);
+
+void hmac_md5(unsigned char* auth_key, int key_len, unsigned char* text, 
+   int text_len, unsigned char* digest); 
+void hmac_sha(unsigned char *k, int lk, unsigned char *d, int ld, 
+   unsigned char *out, int t);
+
+int hmac_do(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *in, 
+   unsigned int in_len, unsigned char *digest, unsigned int digest_len);
+
+int hmac_do2(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *s1, 
+   unsigned int s1_len, unsigned char *s2, unsigned int s2_len, 
+   unsigned char *digest, unsigned int digest_len);
+
+int hmac_do3(int alg_id, unsigned char *alg_key, int alg_keylen, unsigned char *s1, 
+   unsigned int s1_len, unsigned char *s2, unsigned int s2_len, 
+   unsigned char *s3, unsigned int s3_len, 
+   unsigned char *digest, unsigned int digest_len);
+
+int rc4_do(unsigned char *in, unsigned int in_len, unsigned char *out, 
+   unsigned char *key, unsigned key_len);
+
+int concat_buffer(void *in, unsigned char **out, unsigned int in_offset, unsigned int *out_len);
+
+void crypt_test(void);
+
+#endif /* _CRYPT_API_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h
new file mode 100644
index 0000000..df9a5c7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/crypt_port.h
@@ -0,0 +1,241 @@
+/*
+ * FILENAME: crypt_port.h
+ *
+ * Copyright 2002-2003 InterNiche Technologies Inc.  All rights reserved.
+ *
+ * Crypt library configuration.
+ *
+ * MODULE: IPSECCRYPTO
+ *
+ * PORTABLE: yes
+ */
+#ifndef _CRYPT_PORT_H_
+#define _CRYPT_PORT_H_
+
+/* You enable the defines that you need in your particular application
+and undef the rest of the algorithms to reduce code space. */
+/* These are the highest level defines */
+
+#define USE_MD5                                1
+#define USE_SHA1                               1
+#define USE_MD4                                1
+#define USE_3DES                               1
+#define USE_DES                                1
+#define USE_RC4                                1
+#define USE_BF                                 1
+#define USE_AES                                1
+#define USE_SHA2                               1
+
+#define USE_HMAC        	               1
+
+#ifdef NOT_USED
+Make sure "NOT_USED" is really undefined                 
+
+/* Note SSL must be enables for this because it resides in SSL directory */
+#define USE_SSL_DSA                            1
+
+#endif 
+
+/* This define is used in CryptoEngine. It might help the performance. But
+this is totally platform dependent */
+
+#define KICK_CRYPTO_ENGINE  1
+
+/* This define compiles in the CryptoEngine demo. When you have IPSEC defined
+and USE_SEC_HARDWARE make sure this is undefed because with this macro defined
+different IDs are passed to hardware accelerator and therefore IPSEC would not
+work properly. In real applications there is no need for INCLUDE_CE_DEMO anyway
+and it should be undefed */
+
+#define INCLUDE_CE_DEMO    1
+
+/* This macro compiles in the hardware Security engine driver and links it
+to the application code. For example it should be turned on in MCF5235 and MCF5485
+platforms */
+
+/*#define USE_SEC_HARDWARE   1*/
+
+/* Note that most of the time
+either _HW or _SW macros for algorithms are enabled. But in some cases
+depending on product configuration both macros might be enabled */
+
+/* AES is isolated pretty good in current applicatiion code and
+probably it is safe to either enable software or hardware support (assuming it is 
+available) for AES  */
+
+#ifdef USE_AES
+#ifdef USE_SEC_HARDWARE
+#define USE_AES_HW         1
+#else
+#define USE_AES_SW         1
+#endif
+#endif
+
+#ifdef USE_DES
+
+#ifdef USE_SEC_HARDWARE
+#define USE_DES_HW         1
+#endif
+
+#define USE_DES_3DES      1
+
+#endif /* USE_DES */
+
+/* In the current code base 3DES is also pretty clean and
+perhaps it is safe to define either _HW or _SW for 3DES 
+algorithm */
+#ifdef USE_3DES 
+#define USE_DES_3DES      1
+
+#ifdef USE_SEC_HARDWARE
+#define USE_3DES_HW        1
+#else
+#define USE_3DES_SW        1
+#endif
+
+#endif  /* USE_3DES */
+
+#ifdef USE_DES_3DES
+/*  Here you can breakdown what you want to include even further */
+#define USE_DES_CBC_CKSM                       1  /* only used in SSL */
+#define USE_DES_CFB64_EDE                      1  /* only used in SSL */
+#define USE_DES_OFB64_EDE                      1  /* only used in SSL */
+#define USE_DES_CFB64_ENC                      1  /* only used in SSL */
+#define USE_DES_OFB64_ENC                      1  /* only used in SSL */
+#define USE_DES_ECB3_ENC                       1  /* only used in SSL */
+#define USE_DES_ECB_ENC                        1  /* used in SSL and MSCHAP */
+#define USE_DES_XCBC_ENC                       1  /* only used in SSL */
+
+/*#define USE_DES_CFB_ENC                      1*/  /* might be used in SSL */
+/*#define USE_DES_STR2KEY                      1*/  /* might be used in SSL */
+
+#endif
+
+#ifdef USE_MD5
+
+#ifdef USE_SEC_HARDWARE
+#define USE_MD5_HW        1
+#else
+#define USE_MD5_SW        1
+#endif
+
+#ifdef INCLUDE_SNMPV3         /* P2K algorithm is only used in SNMPV3 */
+#ifdef USE_SEC_HARDWARE
+#define USE_P2K_MD5_HW     1  /* This feature is not complete yet*/
+#else
+#define USE_P2K_MD5_SW     1
+#endif
+#endif
+
+#endif /* USE_MD5 */
+
+#ifdef USE_SHA1
+
+#ifdef USE_SEC_HARDWARE
+#define USE_SHA1_HW        1
+#else
+#define USE_SHA1_SW        1
+#endif
+
+#endif /* USE_SHA1 */
+
+
+#ifdef USE_HMAC
+
+#ifdef USE_SEC_HARDWARE
+#define USE_HMAC_HW        1
+#define USE_HMAC_MD5_HW    1
+#define USE_HMAC_SHA_HW    1
+#else
+#define USE_HMAC_SW        1
+#define USE_HMAC_MD5_SW    1
+#define USE_HMAC_SHA_SW    1
+#endif
+
+/* This macro could yield to hardware or software
+ computation based on definition of USE_HMAC_MD5_HW */
+#define USE_IPSEC_MD5      1
+
+/* This macro could yield to hardware or software
+ computation based on definition of USE_HMAC_SHA_HW */
+#define USE_IPSEC_SHA      1
+
+#ifdef USE_SHA2
+#define USE_HMAC_SHA_256  	                   1
+#define USE_HMAC_SHA_384  	                   1
+#define USE_HMAC_SHA_512  	                   1
+#define USE_IPSEC_SHA_256  	                   1
+#define USE_IPSEC_SHA_384  	                   1
+#define USE_IPSEC_SHA_512  	                   1
+#endif
+
+#endif /* USE_HMAC */
+
+/* a lot of code from the asyrmmetric libraries still reside in SSL directory
+and is not moved to crypt directory yet. Therefore compiling RSA require
+SSL to be enabled. */ 
+
+#ifdef ENABLE_SSL  
+#define USE_RSA                                1
+#endif
+
+/* Only one for the following should be defined */
+/* The prime number generation stuff may not work when
+ * EIGHT_BIT but I don't care since I've only used this mode
+ * for debuging the bignum libraries */
+#undef SIXTY_FOUR_BIT_LONG
+#undef SIXTY_FOUR_BIT
+#define THIRTY_TWO_BIT
+#undef SIXTEEN_BIT
+#undef EIGHT_BIT
+
+#ifndef EIGHT_BIT
+#define NUMPRIMES 2048
+#else
+#define NUMPRIMES 54
+#endif
+
+#define CRYPT_MALLOC(size) npalloc(size)
+#define CRYPT_FREE(p)      npfree(p)
+#define CRYPT_FREE_FUNC    npfree
+#define CRYPT_REALLOC(a,n)    nprealloc(a,n)
+#define CRYPT_ASSERT(x)
+
+#ifdef USE_PROFILER
+#define CRYPT_TICKS()   get_ptick()
+#else
+#define CRYPT_TICKS   CTICKS
+#endif /* USE_PROFILER */
+
+/* This is just a CE demo macro. Is has no other significance. */
+#define CU_MAX_BUF_SIZE (64*40)
+
+/* port specific defines */
+#define CU_ACQUIRE_RESOURCE(x)  ENTER_CRIT_SECTION(x)
+#define CU_RELEASE_RESOURCE(x)  EXIT_CRIT_SECTION(x)
+#define CU_TK_YIELD             tk_yield
+
+/* BIO library is only part of SSL code currently */
+#ifndef ENABLE_SSL  
+#define NO_BIO
+#endif
+
+#define NO_FP_API
+/*#define NO_STDIO*/
+#define NO_LHASH
+                                    
+#if defined(ENABLE_SSL) || defined(IKE) || defined(IPSEC)
+
+#define MD_RAND                                1
+#define CRYPT_LIB                              1
+#define USE_BN                                 1
+#define USE_DH                                 1
+#define USE_CRYPT_RAND                         1
+#define USE_RAND_WIN                           1
+#define USE_CRYPT_STACK                        1
+#define USE_CRYPT_ERR                          1
+#define USE_CRYPT_LHASH                        1
+
+#endif  
+
+#endif /* _CRYPT_PORT_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h
new file mode 100644
index 0000000..6b20426
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dhcpclnt.h
@@ -0,0 +1,266 @@
+/*
+ * FILENAME: dhcpclnt.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * dhcpclnt.h - was bootp.h, and then dhcp.h, and the IETF commitees aren't
+ * through with this poor protocol yet...
+ *
+ * MODULE: INET
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1995-1996 by NetPort Software. */
+
+
+#ifndef _DHCPCLNT_H
+#define  _DHCPCLNT_H 1
+
+/* List of enabled DHCP CLIENT options */
+#define  DHCP_REQLIST   1
+
+/* List of disabled DHCP CLIENT options */
+#ifdef NOTDEF
+#define  DHC_MAXDNSRVS  2 
+#endif
+
+#ifdef USE_AUTOIP /* AutoIP requires DNS option */
+#define  DHC_MAXDNSRVS  2 
+#endif   /* USE_AUTOIP */
+
+#define  BOOTP_SERVER_PORT    67
+#define  BOOTP_CLIENT_PORT    68
+
+/* DHCP packet types; from options field of bootp header */
+#define  DHCP_INVALIDOP 99
+#define  DHCP_DISCOVER  1
+#define  DHCP_OFFER     2
+#define  DHCP_REQUEST   3
+#define  DHCP_DECLINE   4
+#define  DHCP_ACK       5
+#define  DHCP_NAK       6
+#define  DHCP_RELEASE   7
+
+/* DHCP options we support: */
+
+#define  DHOP_PAD       0     /* single char of padding, always 0 */
+#define  DHOP_SNMASK    1     /* client's subnet mask */
+#define  DHOP_ROUTER    3     /* set default router */
+#define  DHOP_DNSRV     6     /* IP address of domain name server */
+#define  DHOP_NAME      12    /* name (maybe DNS-ish) of host */
+#define  DHOP_DOMAIN    15    /* name of host's domain */
+
+#define  DHOP_CADDR     50    /* client requested IP address */
+#define  DHOP_LEASE     51    /* lease time */
+#define  DHOP_OVLD      52    /* options are in sname and file fields too */
+#define  DHOP_TYPE      53    /* DHCP type of pkt; 1-7 above */
+#define  DHOP_SERVER    54    /* server ID (IP address) */
+#define  DHOP_REQLIST   55    /* client's parameter request list */
+#define  DHOP_MSG       56    /* message text explaining NAK or DECLINE */
+#define  DHOP_MAXSIZE   57    /* maximum DHCP message size */
+#define  DHOP_RENEWAL   58    /* renewal (T1) time */
+#define  DHOP_REBINDING 59    /* rebinding (T2) time */
+#define  DHOP_CLIENT    61    /* client ID (i.e. hardware address) */
+#define  DHOP_END       255   /* marks end of valid options */
+
+/* DHCP Client per-net states (for dhc_state). The states are as per 
+ * the description in RFC2131. DHCS_RESTARTING is a transient state. 
+ * It is just used to inform the application layer(user) that DHCP 
+ * Client is restarting the negotiation. Following is an example
+ * 
+ * 1. Client sends a REQUEST (it might be in DHCS_REBOOTING or 
+ *    DHCS_REQUESTING state).
+ * 2. Client doesn't receive a ACK/NAK. It retransmits
+ * 3. After few retransmits (as per RFC2131), the client needs to move back
+ *    to DHCS_INIT state. At this time, the user needs to be informed 
+ *    that the client is restarting. 
+ * 4. The Client calls the callback with state as DHCS_RESTARTING.
+ * 5. The Client moves to DHCS_INIT state.
+ * 
+ * There is another example where DHCS_RESTARTING is used.
+ * 1. Client is in DHCS_BOUND state. At the required time (when lease timer
+ *    t1 expires), it will move to DHCS_RENEWING state. It sends a REQUEST
+ *    to renew the lease
+ * 2. No ACK/NAK is received in DHCS_RENEWING state. When lease timer t2 
+ *    expires, the Client moves to DHCS_REBINDING state, and sends a
+ *    REQUEST to rebind the current IP address.
+ * 3. If no ACK/NAK comes and the lease expires, then the client should
+ *    stop all network processing and request network reinitialization.
+ *    That is, the IP address of the interface should be cleared and
+ *    Client should move to DHCS_INIT state. At this time, the user needs
+ *    to be informed that the client is restarting. 
+ * 4. The Client calls the callback with state as DHCS_RESTARTING.
+ * 5. The Client moves to DHCS_INIT state.
+ * 
+ */
+
+#define  DHCS_UNUSED       0  /* no discovery attempted */
+#define  DHCS_INIT         1  /* Ready to send a DISCOVER packet */
+#define  DHCS_INITREBOOT   2  /* Have IP, ready to send REQUEST(skip DISCOVER)*/
+#define  DHCS_REBOOTING    3  /* rebooting/reclaiming address */
+#define  DHCS_SELECTING    4  /* discovery sent, but no offer yet */
+#define  DHCS_REQUESTING   5  /* sent request; waiting for ACK|NAK */
+#define  DHCS_BOUND        6  /* got a ACK we liked */
+#define  DHCS_RENEWING     7  /* Renewing the lease */
+#define  DHCS_REBINDING    8  /* rebinding to new server */
+#define  DHCS_RESTARTING   9  /* Temp. state. Only to inform callback() */
+
+/* macro for writing IP address options to the options buffer. 
+Assumes the IP address is in local endian. */
+#if(BYTE_ORDER == BIG_ENDIAN)
+#define PUT_IP_OPT(ptr, code, ip)  {   \
+   *ptr++ = code;   \
+   *ptr++ = 4;      \
+   *(ptr++) = *(char*)(&ip);   \
+   *(ptr++) = *(((char*)(&ip))+1);   \
+   *(ptr++) = *(((char*)(&ip))+2);   \
+   *(ptr++) = *(((char*)(&ip))+3);   \
+   }
+#else
+#define PUT_IP_OPT(ptr, code, ip)  {   \
+   *ptr++ = code;   \
+   *ptr++ = 4;      \
+   *(ptr+3) = *(char*)(&ip);   \
+   *(ptr+2) = *(((char*)(&ip))+1);   \
+   *(ptr+1) = *(((char*)(&ip))+2);   \
+   *(ptr) = *(((char*)(&ip))+3);   \
+   ptr += 4;   \
+   }
+#endif
+
+/* macro for writing string options to the options buffer */
+#define PUT_STRING_OPT(ptr, code, string)  {   int len;\
+   *ptr++ = code;      \
+   len = strlen(string);   \
+   *ptr++ = (u_char)len;      \
+   strncpy((char*)ptr, (char*)string, len);   \
+   ptr += len;   \
+   }
+
+/* macro to extract IP option. extracted address is in NET endian */
+#define EXTRACT_IP_OPT(ptr, ip) { \
+   ptr++;   \
+   (ip) = *(long*)(ptr);   \
+   }
+
+#define  BOOTREQUEST    1     /* packet op codes */
+#define  BOOTREPLY      2
+
+/* DHCP hardware typres, from ARP section of RFC1700 */
+#define  ETHHWTYPE      1     /* ethernet hardware type */
+#define  LINEHWTYPE     20    /* Serial line hardware type */
+
+#define  RFC1084_MAGIC_COOKIE htonl(0x63825363)
+#define  RFC1084_PAD          ((unsigned  char) 0)
+#define  RFC1084_SUBNET_MASK  ((unsigned  char) 1)
+#define  RFC1084_GATEWAY      ((unsigned  char) 3)
+#define  RFC1084_END          ((unsigned  char) 255)
+
+#define  WHITESPACE  "\n\t "
+
+#define  ADDR_ERR_STRING      "Invalid ethernet address"
+
+#define  xtoi(x)     ((x>='a')&&(x<='f')?(x-'a'+10):((x>='A')&&(x<=  'F')?(x-'A'+10):(x-'0')))    
+
+#define  OP       0
+#define  HTYPE    1
+#define  HLEN     2
+#define  HOPS     3
+#define  CIADDR   12
+#define  YIADDR   16                  
+#define  SIADDR   20                  
+#define  CHADDR   28
+
+#define  BOOTP_OPTSIZE     64 /* older value */
+#define  DHCP_OPTSIZE   312   /* newer value */
+
+/* bit we mask into the op field of received packets internally. 
+ * This is set if the packet is DHCP (as opposed to plain bootp)
+ */
+#define  ISDHCP      0x04
+#define  isdhcp(bp)  (bp->op  &  ISDHCP)
+
+
+/* The structure of a bootp/dhcp packet. This is the
+ * UDP data area of a bootp or dhcp packet.
+ */
+
+struct bootp   {
+   unsigned char     op;
+   unsigned char     htype;
+   unsigned char     hlen;
+   unsigned char     hops;
+   unsigned long     xid;
+   unsigned short    secs;
+   unsigned short    flags;
+   unsigned long     ciaddr;
+   unsigned long     yiaddr;
+   unsigned long     siaddr;
+   unsigned long     giaddr;
+   unsigned char     chaddr[16];
+   unsigned char     sname[64];
+   unsigned char     file[128];
+   unsigned char     options[BOOTP_OPTSIZE]; /* was "vend" for bootp */
+};
+
+/* define sizes for both old bootppackets and newer dhcop packets. 
+ * Need to be aware the Windows95 and other broken systems send DHCP 
+ * packets in the bootp size, so you need to check both size and 
+ * options to 
+ */
+#define  BOOTPSIZE   (sizeof(struct bootp))
+#define  DHCPSIZE    (BOOTPSIZE  +  (DHCP_OPTSIZE-BOOTP_OPTSIZE))
+
+/* dhcp utility routines */
+u_char * find_opt(u_char opcode, u_char * opts);
+
+/* DHCP client per-interface state: */
+struct dhc_state  {
+   unsigned state;         /* one of the "DHCS" states below */
+   int      tries;         /* retry count of current state */
+   u_long   xid;           /* last xid sent */
+   u_short  secs;          /* seconds since client came up */
+   u_long   last_tick;     /* time of last DHCP packet */
+   u_long   lease;         /* lease; only valid if state == DHCS_BOUND */
+   u_long   t1 ;           /* lease related - renew timer */
+   u_long   t2 ;           /* lease related - rebind timer */
+   u_long   lease_start;   /* time  in cticks   of when  lease started */
+
+   /* Configuration  options  of outstanding request */
+   ip_addr  ipaddr;        /* IP address */
+   ip_addr  snmask;        /* subnet mask */
+   ip_addr  defgw;         /* default gateway (router) */
+
+   ip_addr  rly_ipaddr;    /* IP addr of our RELAY agent (if any) */
+
+   /* IP Address of the DHCP Server.
+    * Needed   to send  unicast  when  renewing IP Addr
+    */
+   ip_addr  srv_ipaddr;
+
+#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0)
+   ip_addr  dnsrv[DHC_MAXDNSRVS];   /* domain name server addresses */
+#endif   /* DHC_MAXDNSRVS */
+
+   int   (*callback)(int iface, int state);  /* callback when IPaddress set */
+};
+
+extern   struct dhc_state  dhc_states[MAXNETS]; /* DHCP client state of each net*/
+
+/* DHCP client entry points */
+int      dhc_init        (void);
+int      dhc_second      (void);
+int      dhc_alldone     (void);
+int      dhc_ifacedone   (int iface);
+void     dhc_state_init  (int iface, int init_flag);
+void     dhc_halt        (int iface);
+void     dhc_set_callback(int iface, int (*routine)(int,int) );
+int      dhc_stats       (void *pio);
+
+
+#endif   /* _DHCPCLNT_H */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h
new file mode 100644
index 0000000..345634f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dns.h
@@ -0,0 +1,216 @@
+/*
+ * FILENAME: dns.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * DNS defines for NetPort IP stack.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+
+#ifndef _DNS_H_
+#define  _DNS_H_  1
+
+/* set defaults of DNS variables, may override in ipport.h */
+
+#ifndef MAXDNSNAME
+#define  MAXDNSNAME     256   /* max length of name including domain */
+#endif
+
+#ifndef MAXDNSUDP
+#define  MAXDNSUDP      512   /* MAX allowable UDP size */
+#endif
+
+#ifndef MAXDNSSERVERS
+#define  MAXDNSSERVERS  3     /* MAX number of servers to try */
+#endif
+
+#ifndef MAXDNSADDRS
+#define  MAXDNSADDRS    10    /* MAX IP addresses to return via gethostbyname() */
+#endif
+
+#ifndef MAXDNSALIAS
+#define  MAXDNSALIAS    2     /* MAX number of alias names */
+#endif
+
+#define  DNS_QUERY       0    /* Op code for query */
+#define  DNS_UPDT        5    /* Op code for UPDATE request  */
+
+/* DNS Record types */
+#define  DNS_TYPE_QUERY    0     /* Type value for question record */
+#define  DNS_TYPE_IPADDR   1     /* Type value for IPv4 address */
+#define  DNS_TYPE_AUTHNS   2     /* Authoritative name server */
+#define  DNS_TYPE_ALIAS    5     /* Alias for queried name */
+#define  DNS_TYPE_PTR      12     /* Domain Name pointer */
+#define  DNS_TYPE_AAAA     0x1c  /* IPv6 address ("AAAA" record) */
+
+/* Description of data base entry for a single host.  */
+struct hostent
+{
+   char *   h_name;        /* Official name of host. */
+   char **h_aliases;       /* Alias list.  */
+   int   h_addrtype;       /* Host address type.  */
+   int   h_length;         /* Length of address.  */
+   char **h_addr_list;     /* List of addresses from name server.  */
+#define  h_addr   h_addr_list[0] /* Address, for backward compatibility.  */
+
+#ifdef DNS_CLIENT_UPDT
+   /* Extra variables passed in to Dynamic DNS updates. */
+   char *   h_z_name;      /* IN- zone name for UPDATE packet */
+   ip_addr  h_add_ipaddr;  /* IN- add this ip address for host name in zone */
+   u_long   h_ttl;         /* IN- time-to-live field for UPDATE packet */
+#endif /* DNS_CLIENT_UPDT */
+};
+
+
+/* basic internal structure of a client DNS entry. This one structure does double
+ * duty as a request manager and database entry.
+ */
+
+struct dns_querys
+{
+   struct dns_querys * next;
+   u_long   send_time;     /* ctick when last request was sent/received */
+   u_long   expire_time;   /* second (local) when this data expires */
+   unshort  tries;         /* retry count */
+   unshort  lport;         /* local (client) UDP port, for verification */
+   unshort  id;            /* ID of request, 0 == unused entry. */
+   int      replies;       /* number of replys to current request */
+   int      ipaddrs;       /* count of entries in ipaddr_list[] */
+   ip_addr  ipaddr_list[MAXDNSADDRS];  /* IP addresses (net endian) */
+   char *   addrptrs[MAXDNSADDRS];  /* pointers, for hostent.h_addr_list */
+   int      err;                    /* last ENP_ error if, if any */
+   int      rcode;                  /* last response code if replys > 1 */
+   char     dns_names[MAXDNSNAME];  /* buffer of names (usually w/domain) */
+   char     ptr_name[MAXDNSNAME];  /* The result of PTR query is stored here (just one for now) */
+   ip_addr  auths_ip;               /* IPv4 addresses of 1st auth server */
+   char *   alist[MAXDNSALIAS+1];   /* alias list, points into dns_names */
+
+   /* Most DNS queries need a hostent structure to return the data to
+    * the calling application; so we embed the hostent structure inside
+    * the query structure - one less alloced buffer to keep track of.
+    */
+   struct hostent he;               /* for return from gethostbyname() */
+   char     type;                   /* type of original query */
+
+#ifdef IP_V6
+   int      ip6addrs;                  /* count of entries in ip6_list */
+   char     ip6_list[MAXDNSADDRS][16]; /* IPv6 address from answers */
+   char     auths_ip6[16];             /* IPv6 addresses of 1st auth server */
+#endif   /* IP_V6 */
+};
+
+
+/* List of DNS objects */
+extern   struct dns_querys * dns_qs;
+
+/* Macros to allocate & free DNS objects */
+#ifndef DNC_ALLOC
+#define DNC_ALLOC(size) (struct dns_querys *)npalloc(size)
+#define DNC_FREE(ptr)   npfree((void *)ptr)
+#endif
+
+/* pending requests, can be used as a flag to spin dnsc_check() task */
+extern   unsigned    dnsc_active;
+
+/* DNS client statistics: */
+extern   ulong    dnsc_errors;   /* protocol/implementation runtime errors */
+extern   ulong    dnsc_requests; /* requests sent */
+extern   ulong    dnsc_OK;       /* OK replys received */
+extern   ulong    dnsc_unks;     /* error (unknown) replys received */
+extern   ulong    dnsc_tmos;     /* timeouts */
+
+
+/* DNS operational parameters which can be set at run time */
+extern   ip_addr  dns_servers[MAXDNSSERVERS];
+
+#ifdef   DNS_CLIENT_UPDT
+extern   char     soa_mname[MAXDNSNAME];
+#endif    /* DNS_CLIENT_UPDT */
+
+extern   unsigned dns_firsttry;  /* time to first retry, in seconds */
+extern   unsigned dns_trys;      /* max number of retrys */
+
+
+
+/* header format of a DNS packet over UDP */
+START_PACKED_STRUCT(dns_hdr)
+   unshort  id;         /* 16 bit unique query ID */
+   unshort  flags;      /* various bit fields, see below */
+   unshort  qdcount;    /* entries in the question field */
+   unshort  ancount;    /* resource records in the answer field */
+   unshort  nscount;    /* name server resource records */
+   unshort  arcount;    /* resource records in the additional records */
+END_PACKED_STRUCT(dns_hdr)
+
+#define  DNS_PORT    53    /* DNS reserved port on UDP */
+
+/* DNS header flags field defines */
+#define  DNSF_QR     0x8000   /* query (0), or response (1) */
+#define  DNSF_OPMASK 0x7800   /* 4 bit opcode kinds of query, 0==standard */
+#define  DNSF_AUTHOR 0x0400   /* authoritative */
+#define  DNSF_RECUR  0x0100   /* recursion */
+#define  DNSF_NONAME 0x0003   /* No such name. */ 
+#define  DNSF_AA     0x0400   /* set if Authoritive Answers */
+#define  DNSF_TC     0x0200   /* set if truncated message */
+#define  DNSF_RD     0x0100   /* Recursion Desired bit */
+#define  DNSF_RA     0x0080   /* Recursion Allowed bit */
+#define  DNSF_Z      0x0070   /* 3 reserved bits, must be zero */
+#define  DNSF_RCMASK 0x000F   /* Response Code mask */
+
+/* Reponse Code values: */
+#define  DNSRC_OK       0     /* good response */
+#define  DNSRC_EFORMAT  1     /* Format error */
+#define  DNSRC_ESERVER  2     /* Server Error */
+#define  DNSRC_ENAME    3     /* Name error */
+#define  DNSRC_EIMP     4     /* Not Implemented on server */
+#define  DNSRC_EREFUSE  5     /* Server refused operation */
+#define  DNSRC_UNSET    0xFF  /* No reponse yet (used only in dns_querys struct) */
+
+#ifdef DNS_CLIENT_UPDT
+
+/* Error codes used within Dynamic DNS Update operation */
+#define  DNSRC_EDOMAIN  6     /* Some name that ought not to exist, exists */
+#define  DNSRC_ERRSET   7     /* Some RRset that ought not to exist, exists*/
+#define  DNSRC_ENRRSET  8     /* Some RRset that ought to exist, does not */
+#define  DNSRC_NOTAUTH  9     /* Server is not authoritative for the zone */
+                              /* named in the zone section */
+#define  DNSRC_NOTZONE  10    /* A name used within the Update section */
+                              /* is not within the zone denoted        */
+#define  DNS_CLASS_NONE    254    /* CLASS NONE */
+
+#endif /* DNS_CLIENT_UPDT */
+
+/* DNS client external entry points: */
+int   dns_query(char * name, ip_addr * ip);     /* start a DNS query */
+int   dns_lookup(ip_addr * ip, char * name);    /* check query status */
+void  dnsc_check(void); /* spin once a second to drive retrys & timeouts */
+
+/* New (for v2.0) version of dns_query(), which takes a record type
+ * argument and fills in a pointer to the dns_query structure.
+ */
+int   dns_query_type(char * name, char type, ip_addr ipaddr,
+            unsigned long ttl, struct dns_querys ** dns_ptr);
+
+/* flags for in_reshost(); */
+#define  RH_VERBOSE     0x01  /* do informational printfs   */
+#define  RH_BLOCK       0x02  /* block with call to tk_yield()  */
+int   in_reshost(char * host, ip_addr * address, int flags);
+
+
+/* Return entry from host data base for host with NAME. This could be 
+ * in sockcall.h but is here because a non-TCP used may want DNS. 
+ */
+struct hostent * gethostbyname(char * name);
+int nslookup(char * name, char type, struct dns_querys **dns_entry);
+
+/* ....And the crufty v6 version (RFC2133).... */
+struct hostent *  gethostbyname2(char * name, int af);
+
+#endif   /* _DNS_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h
new file mode 100644
index 0000000..3f17096
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/dnsport.h
@@ -0,0 +1,40 @@
+/*
+ * FILENAME: dnsport.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: DNS
+ *
+ *
+ * PORTABLE: no
+ */
+
+/* dnsport.h
+ *
+ * Per-port DNS definition. Most of these are pretty much the same on all
+ * systems, but may require tuning for weird cases 
+ */
+
+#ifndef _DNSPORT_H_
+#define _DNSPORT_H_     1
+
+#define  UDPPORT_DNS 53 /* UDP port to use */
+
+typedef short int16_t;
+typedef unsigned short u_int16_t;
+typedef unsigned long u_int32_t;
+
+
+#ifndef NO_TIME_T
+typedef unsigned long time_t;
+
+/* a unix-y timeval structure */
+struct timeval {
+     unsigned long  tv_sec;
+     unsigned long  tv_usec;
+};
+#endif
+
+#endif  /* _DNSPORT_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h
new file mode 100644
index 0000000..62d88f7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ether.h
@@ -0,0 +1,94 @@
+/*
+ * FILENAME: ether.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * information common to all ethernet drivers
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990, 1993 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon */
+/* Portions Copyright 1983, 1985 by the Massachusetts Institute of Technology */
+
+#ifndef _ETHER_H_
+#define  _ETHER_H_   1
+
+
+/* initialization modes: 0 = rcv normal + broadcast packets */
+#define     LOOPBACK    0x01  /* send packets in loopback mode */
+#define     ALLPACK     0x02  /* receive all packets: promiscuous */
+#define     MULTI       0x04  /* receive multicast packets */
+
+/* ethernet packet header */
+
+START_PACKED_STRUCT(ethhdr)
+u_char   e_dst[6];
+u_char   e_src[6];
+unshort  e_type;
+END_PACKED_STRUCT(ethhdr)
+
+/* ETHHDR_SIZE - size of packet header structure for allocation 
+ * purposes Note this is a default -- it should be overridden in 
+ * ipport.h if the need arises. 
+ */
+
+#ifndef ETHHDR_SIZE
+#define  ETHHDR_SIZE (sizeof(struct ethhdr))
+#endif   /* ETHHDR_SIZE */
+
+/* ETHHDR_BIAS - where to locate the struct ethhdr within the 
+ * allocated space, as an offset from the start in bytes Note this is 
+ * a default -- it should be overridden in ipport.h if the need 
+ * arises. 
+ */
+
+#ifndef  ETHHDR_BIAS
+#define  ETHHDR_BIAS 0
+#endif   /* ETHHDR_BIAS */
+
+/* ET_DSTOFF - offset of destination address within Ethernet header
+ */
+#define ET_DSTOFF       (0)
+
+/* ET_SRCOFF - offset of source address within Ethernet header
+ */
+#define ET_SRCOFF       (6)
+
+/* ET_TYPEOFF - offset of Ethernet type within Ethernet header
+ */
+#define ET_TYPEOFF      (12)
+
+/* ET_TYPE_GET(e) - get Ethernet type from Ethernet header pointed to
+ *                  by char * e
+ * Note returned Ethernet type is in host order!
+ */
+#define ET_TYPE_GET(e)  \
+        (((unsigned)(*((e) + ET_TYPEOFF)) << 8) + \
+         (*((e) + ET_TYPEOFF + 1) & 0xff))
+
+/* ET_TYPE_SET(e, type) - set Ethernet type in Ethernet header pointed to
+ *                        by char * e to value (type)
+ * Note Ethernet type is value is expected to be in host order!
+ */
+#define ET_TYPE_SET(e, type) \
+        *((e) + ET_TYPEOFF) = (unsigned char)(((type) >> 8) & 0xff); \
+        *((e) + ET_TYPEOFF + 1) = (unsigned char)((type) & 0xff);
+
+/* minimum & maximun length legal ethernet packet sizes */
+#define     ET_MINLEN   60
+#define     ET_MAXLEN   1514
+#define     MINTU       60
+#define     MTU         1514
+
+extern   unsigned char  ETBROADCAST[];
+
+#endif   /* _ETHER_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h
new file mode 100644
index 0000000..45c9d87
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/genlist.h
@@ -0,0 +1,142 @@
+/*
+ * FILENAME: GENLIST.H
+ *
+ * Copyright 1999-2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES:
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* 
+ * GENERIC Implementation of a list. 
+ *
+ * 1999      - Implemented for use with SNMPv3 tables -AT-
+ * 2/21/2002 - Added niche_add_sorted() and moved from snmpv3 to h -AT-
+ */
+
+
+#ifndef GENLIST_H    /* Make sure the header file is included only once */
+#define  GENLIST_H            1
+
+#include "ipport.h"
+
+/* Generic list is used by SNMPv3 code and IPFILTER code. */
+#if (defined(INCLUDE_SNMPV3) || defined(USE_IPFILTER) || defined(INICHE_SYSLOG))
+#define USE_GENLIST     1
+#endif
+
+#define  GEN_MAX_ARRAY  10
+
+#ifndef GEN_ALLOC
+#define GEN_ALLOC(size) npalloc(size)
+#endif
+#ifndef GEN_FREE
+#define GEN_FREE(ptr)   npfree(ptr)    
+#endif
+
+#ifndef MEMCMP
+#define MEMCMP          memcmp
+#endif
+#ifndef MEMCPY
+#define MEMCPY          memcpy
+#endif
+
+#ifndef SUCCESS
+#define SUCCESS         0
+#endif
+#ifndef FAILURE
+#define FAILURE         1
+#endif
+
+
+#ifndef MAX_NAME_LEN      /* usually defined in snmpport.h */
+#define MAX_NAME_LEN    64  /* max number of subid's in a objid */
+#endif
+
+/* NicheElement had two members. One is a pointer to the DATA and the 
+ * other is a pointer to the next element. If there is no next 
+ * element, the pointer is NULL. GEN_STRUCT can be anything. 
+ * Following are some thoughts on the way things are declared and 
+ * intended. 
+ * 1. If there is only one list, GEN_STRUCT can be 
+ *    explicitly named to the STRUCT/CLASS 
+ * 2. If there are multiple lists, then GEN_STRUCT can be "void*" 
+ * and casting can be done whenever we are using it 
+ * 3. If we need a CLASS implementation, all the functions can be 
+ *   made as interfaces of the CLASS. So we just 
+ *   need a class wrapper. Further, it is assumed that GEN_STRUCT has 
+ *   two members defined as follows 
+ *      "long id;" 
+ *      "char name[MAX_NAME_LEN];" 
+ * The list can be a singly indexed list (that 
+ * is all elements can be uniquely identified by their IDs). Or it 
+ * can be doubly indexed list (all elements can be uniquely 
+ * identified by their ID and name combined). Lookup and deletion 
+ * from the list has been provided for this use. 
+ */
+struct TemplateStruct
+{
+   long     id;
+   char     name[MAX_NAME_LEN];
+};
+
+typedef struct TemplateStruct * GEN_STRUCT ;
+
+struct NicheElement
+{
+   GEN_STRUCT  p_data;           /* Pointer to element/data */       
+   struct     NicheElement *  next; /* Pointer to next data element */
+};
+
+typedef struct NicheElement * NICHE_ELE;
+
+
+struct NicheList
+{
+   NICHE_ELE   head  ;     /* First element of the list */
+   int         len_of_element;/* Len   of the   struct representing  element/data*/
+};
+
+typedef struct NicheList * NICHELIST;
+
+
+int        niche_list_constructor  (NICHELIST list, int len_of_ele);
+int        niche_list_destructor   (NICHELIST list);
+int        niche_add               (NICHELIST list, GEN_STRUCT ptr_data);
+int        niche_add_sorted        (NICHELIST list, GEN_STRUCT ptr_data);
+int        niche_add_id_and_name   (NICHELIST list, long id, char * name);
+int        niche_del               (NICHELIST list, GEN_STRUCT ptr_data);
+int        niche_del_id            (NICHELIST list, long id);
+int        niche_del_name          (NICHELIST list, char * name);
+int        niche_del_id_and_name   (NICHELIST list, long id, char * name);
+GEN_STRUCT niche_lookup_id         (NICHELIST list, long id);
+GEN_STRUCT niche_lookup_name       (NICHELIST list, char *name);
+GEN_STRUCT niche_lookup_id_and_name(NICHELIST list, long id, char *name);
+int        niche_lookup_multi_match(NICHELIST list, long id, char * name, 
+              GEN_STRUCT matches[]);
+int        niche_list_show         (NICHELIST list);
+int        niche_list_len          (NICHELIST list); 
+GEN_STRUCT niche_list_getat        (NICHELIST list,int index); 
+int        niche_element_show      (GEN_STRUCT ptr_data);
+
+
+
+#define  NICHE_ERRBASE                    2000
+
+#define  NICHE_NO_MEM                     (NICHE_ERRBASE+1)
+#define  NICHE_NO_MEM_FOR_DATA            (NICHE_ERRBASE+2)
+#define  NICHE_ADD_NOT_ENOUGH_MEMORY      (NICHE_ERRBASE+3)
+#define  NICHE_DEL_LIST_EMPTY             (NICHE_ERRBASE+4)
+#define  NICHE_DEL_NOT_FOUND              (NICHE_ERRBASE+5)
+#define  NICHE_DEL_NOT_ENOUGH_MEMORY      (NICHE_ERRBASE+6)
+#define  NICHE_LISTPTR_INVALID            (NICHE_ERRBASE+7)
+#define  NICHE_DUP_ENTRY                  (NICHE_ERRBASE+8)
+
+
+#endif   /*  GENLIST_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h
new file mode 100644
index 0000000..cd22b3e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/htcmptab.h
@@ -0,0 +1,123 @@
+/* htcmptab.h
+ *
+ *    Copyright 1996 2001 by NetPort software. All rights reserved.
+ *
+ *    Compression table for HTML compression. This files contains
+ * static data & thus should be included in only ONE source file per
+ * executable.
+ *
+!!!!!!!!!!!!!!!!!!  W A R N I N G !!!!!!!!!!!!!!!!!!!!
+ * If you change this table, be sure to recompile BOTH the VFS tables
+ * AND your application. If you don't do this you will get lots of 
+ * subtle, hard to find errors.
+ */
+
+#ifndef _HTCMPTAB_H_
+#define _HTCMPTAB_H_
+
+/* A one byte insertion value is derived for each of the 
+ * following common HTML strings by the following:
+ *
+ * low 7 bits is offset into array
+ * high bit always on
+ */
+
+char * htmltags[] = {
+"   <META HTTP-EQUIV=\"Content-Type\" CONTENT=\"text/html; charset=iso-8859-1\">",
+"   <META NAME=\"Author\" CONTENT=\"John Bartas\">",
+"<IMG HEIGHT=16 WIDTH=16 ALIGN=LEFT BORDER=0 SRC=",
+"blank2.gif",
+"<IMG HEIGHT=40 WIDTH=40 ALIGN=RIGHT BORDER=0 SRC=",
+"blank1.gif", 
+".src='hot1.gif';",
+" onMouseOut=",
+".src='hot2.gif';",
+"onMouseOut=",
+"onMouseOver=",
+"hot1.gif",
+"hot2.gif",
+"img",
+".src='blank1.gif';\") >",
+"<FONT FACE=",
+"<font face=",
+"Arial,Helvetica",
+"Arial",
+" TARGET=\"data\"",
+"<TABLE BORDER=",
+" BORDER=",
+"<TABLE",
+" CELLSPACING=",
+" CELLPADDING=",
+"CELL",
+"</TABLE>",
+"&nbsp;",
+"\r\n",
+"<!--#include ",
+"<!--#exec ",
+"</A>",
+"</BODY>",
+"</FORM>",
+"</H1>",
+"</H2>",
+"</H3>",
+"</H4>",
+"</HEAD>",
+"</HTML>",
+"</P>",
+"</PRE>",
+"</TITLE>",
+"<A ",
+"<BASE=",
+"<BODY>",
+"<DD>",
+"<DL>",
+"<FORM",
+"<H1",
+"<H2",
+"<H3",
+"<H4",
+"<HEAD>",
+"<HTML>",
+"<INPUT ",
+"<P>",
+"<PRE>",
+"<TITLE>",
+"ACTION=",
+"ALIGN=\"CENTER\"",
+"ALIGN=CENTER",
+"ALIGN=",
+"BGPROPERTIES=",
+"CENTER",
+"COLOR=\"#FFFFFF\"",
+"COLOR=",
+"HEIGHT=",
+"HREF=",
+"IMG ",
+"ISMAP",
+"LEFT",
+"LINK",
+"MAXLENGTH=",
+"METHOD=",
+"NAME=",
+"RIGHT",
+"SIZE=",
+"SRC=",
+"TEXT",
+"TYPE=",
+"WIDTH=",
+"html",
+"help",
+"<FONT ",
+"</FONT",
+"<font ",
+"</font>",
+"face",
+"size",
+"VALUE=",
+"SUBMIT",
+"FFFFFF",
+};
+
+int tagct = sizeof(htmltags)/sizeof(char*);
+
+#endif  /* _HTCMPTAB_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/icmp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/icmp.h
new file mode 100644
index 0000000..e98de1a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/icmp.h
@@ -0,0 +1,207 @@
+/*
+ * FILENAME: icmp.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * ICMP message handling
+ *
+ * MODULE: INET
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* Portions Copyright 1990,1993 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon */
+/* Portions Copyright 1983 by the Massachusetts Institute of Technology */
+
+#ifndef _ICMP_H_
+#define  _ICMP_H_ 1
+
+
+/* Define some ICMP messages */
+
+/* ICMP dest unreachable types */
+#define  DSTNET      0
+#define  DSTHOST     1
+#define  DSTPROT     2
+#define  DSTPORT     3
+#define  DSTFRAG     4
+#define  DSTSRC      5
+
+
+#define  ECHOREP     0     /* ICMP Echo reply */
+#define  DESTIN      3     /* Destination Unreachable */
+#define  SOURCEQ     4     /* Source quench */
+#define  REDIR       5     /* Redirect */
+#define  ECHOREQ     8     /* ICMP Echo request */
+#define  TIMEX       11    /* Time exceeded */
+#define  PARAM       12    /* Parameter problem */
+#define  TIMEREQ     13    /* Timestamp request */
+#define  TIMEREP     14
+#define  INFO        15    /* Information request */
+
+/* ICMP Time Exceeded codes */
+#define TIMEX_REASSY_FAILED 1 /* code 1 ("fragment reassembly time exceeded") */
+
+#define  ICMP_PROT   1     /* ICMP Protocol number on IP */
+#define  ICMPSIZE    sizeof(struct  ping) /* default size for ICMP packet */
+
+struct ping          /* ICMP Echo request/reply header */
+{
+   char     ptype;
+   char     pcode;
+   unshort  pchksum;
+   unshort  pid;
+   unshort  pseq;
+};
+
+/* structure of an icmp destination unreachable packet */
+
+#define  ICMPDUDATA     8  /* size of extra data */
+
+struct destun
+{
+   char     dtype;
+   char     dcode;
+   unshort  dchksum;
+   unshort  dno1;
+   unshort  dno2;
+   struct ip   dip;    /* the offending IP packet */
+   char     ddata[ICMPDUDATA];
+};
+
+/* structure of an icmp time exceeded packet */
+
+/* length of "user" data (just past the "inner" IP header).  This is 
+ * from the packet that the ICMP Time Exceeded message is being sent 
+ * in response to. */
+#define ICMPTIMEX_PAYLOAD_DATA_LEN 8
+#define ICMPTIMEX_HDR_LEN 8 /* length of the ICMP header */
+
+struct timex
+{
+   char     ttype;
+   char     tcode;
+   unshort  tchksum;
+   unshort  tno1;
+   unshort  tno2;
+   struct ip   tip;
+   char     tdata[8];
+};
+
+/* structure of a timestamp reply */
+
+START_PACKED_STRUCT(tstamp)
+   char     ttype;
+   char     tcode;
+   unshort txsum;
+   unshort tid;
+   unshort tseq;
+   char     stamps[3 * sizeof(u_long)];  /* some compilers do bad aligns */
+  /* long     dtstamp[3]; */ /* was "tstamp", use of structname upsets compilers */
+END_PACKED_STRUCT(tstamp)
+
+/* structure of an icmp redirect */
+
+struct redirect
+{
+   char     rdtype;
+   char     rdcode;
+   unshort  rdchksum;
+   ip_addr  rdgw;
+   struct ip   rdip;
+   char     rddata[8];
+};
+
+
+/* the snmp icmp variables */
+
+struct IcmpMib {
+   u_long   icmpInMsgs;          /* 1 - received icmp packets, including errors */
+   u_long   icmpInErrors;        /* 2 - bad sums, bad len, etc. */
+   u_long   icmpInDestUnreachs;  /* 3 - no comments for self explanitorys */
+   u_long   icmpInTimeExcds;     /* 4 */
+   u_long   icmpInParmProbs;     /* 5 */
+   u_long   icmpInSrcQuenchs;    /* 6 */
+   u_long   icmpInRedirects;     /* 7 */
+   u_long   icmpInEchos;         /* 8 */
+   u_long   icmpInEchoReps;      /* 9 */
+   u_long   icmpInTimestamps;    /* 10 */
+   u_long   icmpInTimestampReps; /* 11 */
+   u_long   icmpInAddrMasks;     /* 12 */
+   u_long   icmpInAddrMaskReps;  /* 13 */
+   u_long   icmpOutMsgs;         /* 14 - total sent icmps, including errors */
+   u_long   icmpOutErrors;       /* 15 - ICMP Layer errors ONLY (see rfc #1156) */
+   u_long   icmpOutDestUnreachs; /* 16 */
+   u_long   icmpOutTimeExcds;    /* 17 */
+   u_long   icmpOutParmProbs;    /* 18 */
+   u_long   icmpOutSrcQuenchs;   /* 19 */
+   u_long   icmpOutRedirects;    /* 20 */
+   u_long   icmpOutEchos;        /* 21 */
+   u_long   icmpOutEchoReps;     /* 22 */
+   u_long   icmpOutTimestamps;   /* 23 */
+   u_long   icmpOutTimestampReps;/* 24 */
+   u_long   icmpOutAddrMasks;    /* 25 */
+   u_long   icmpOutAddrMaskReps; /* 26 */
+};
+
+extern   struct IcmpMib icmp_mib;
+
+typedef struct IcmpMib * ICMPMIB;
+
+/* hook in icmp.c for linked application to peek at ICMP DU packets */
+extern   void (*icmpdu_hook)(PACKET p, struct destun * pdp);
+
+int   icmp_init(void);
+int   icmp_stats(void * pio);
+#ifndef MINI_IP
+void  icmp_destun(ip_addr, ip_addr, struct ip *, unsigned, NET);
+#else
+void  icmp_destun(ip_addr, struct ip *, unsigned, NET);
+#endif
+int   icmprcv(PACKET);
+void  icmp_du(PACKET p, struct destun * pdp);
+void  icmp_timex (struct ip * ip, char code);
+
+/* in ping.c: routines to send & receive icmp pings */
+int   icmpEcho(ip_addr, char*, unsigned, unshort);    /* send ping */
+
+/* pingUpcall() must be implemented in the app if PING_APP is definied */
+int   pingUpcall(PACKET);     /* upcall for ALL incoming ping packets */
+
+#ifdef INCLUDE_TCP   /* sockets ICMPDU callback */
+extern   void so_icmpdu(PACKET p, struct destun * pdp);
+#endif   /* INCLUDE_TCP */
+
+#ifndef _IPPORT_H_
+#error You must first include ipport.h
+#endif   /*  _IPPORT_H_ */
+
+#ifndef ETHHDR_BIAS
+#define ETHHDR_BIAS 0
+#endif
+
+/* Figure out a minimum value */
+#ifdef USE_PPPOE
+#define PINGHDRSMINLEN (44 + 8 + ETHHDR_BIAS + IPSECOPT_SIZE)
+#elif  defined(IEEE_802_3)
+#define PINGHDRSMINLEN (42 + 8 + ETHHDR_BIAS + IPSECOPT_SIZE)
+#else
+#define PINGHDRSMINLEN (34 + 8 + ETHHDR_BIAS + IPSECOPT_SIZE)
+#endif
+
+/* Figure out the actual value: minimum value padded out to 
+ * a multiple of ALIGN_TYPE
+ */
+#if ((PINGHDRSMINLEN & (ALIGN_TYPE - 1)) == 0)
+#define  PINGHDRSLEN  PINGHDRSMINLEN
+#else
+#define  PINGHDRSLEN  (PINGHDRSMINLEN + ALIGN_TYPE - (PINGHDRSMINLEN & (ALIGN_TYPE - 1)))
+#endif
+
+#endif   /* _ICMP_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ifmap.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ifmap.h
new file mode 100644
index 0000000..b18e510
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ifmap.h
@@ -0,0 +1,44 @@
+/*
+ * FILENAME: ifmap.h
+ *
+ * Copyright 2001 - 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * "Database" of iface to iface mappings. These are designed as an
+ * administrate and configuration tool - application code can
+ * set up the mappings, and the lower-level driver code will use
+ * it to build IP tunnels, PPPoE links, and other constructions
+ * that involve more than one interface. A lower
+ * iface can be paired with more than one upper (eg PPPoE) and
+ * Visa-versa.
+ *
+ * ROUTINES: ifmap_bind(), ifmap_nextupper(), ifmap_nextlower(), ifmap_del(),
+ *
+ * MODULE: PPP
+ *
+ */
+
+#ifndef _IFMAP__H_
+#define _IFMAP__H_ 1
+
+#ifndef MAX_IFPAIRS
+#define MAX_IFPAIRS MAXNETS
+#endif   /* MAX_IFPAIRS */
+
+
+struct iface_pair
+{
+   NET upper;
+   NET lower;
+};
+
+extern struct iface_pair ifpairs[MAX_IFPAIRS];
+
+
+NET   ifmap_nextupper(NET upper, NET lower);
+NET   ifmap_nextlower(NET upper, NET lower);
+int   ifmap_bind(NET upper, NET lower);
+void  ifmap_del(NET upper, NET lower);
+
+#endif /* _IFMAP__H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/in_utils.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/in_utils.h
new file mode 100644
index 0000000..0ef7524
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/in_utils.h
@@ -0,0 +1,131 @@
+/*
+ * FILENAME: in_utils.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* in_utils.h 03/11/97 - Created for Borland C cleanup. John Bartas 
+ */
+#ifndef IN_UTILS_H
+#define  IN_UTILS_H     1
+
+#include "ipport.h"
+#include "libport.h"
+
+#ifndef MAXIOSIZE
+#define MAXIOSIZE       156
+#endif
+
+struct GenericIO
+{
+   char *   inbuf;      /* Pointer to command line  */
+
+   /* Function to send the output string  */
+   int (* out)(long id, char * outbuf, int len);  
+
+   /* Identifier for the IO device. For TCP it would represent a SOCKET */
+   long id;
+
+   /* Get a character input from the I/O device This is needed to
+    * show scrollable items
+    */
+   int (*getch)(long id);
+};
+
+typedef struct GenericIO * GEN_IO ;
+extern   unsigned long  pingdelay;
+
+
+
+#ifdef SEG16_16
+/* macros for 16 bit seg:offset pointer manipulation */
+#ifndef _MK_FP
+#define _MK_FP(seg, offs) (void far *)(((unsigned long)seg << 16) \
+    + (unsigned long)(unsigned)offs)
+#endif
+#ifndef _FP_SEG
+#define  _FP_SEG(ptr)   (*((unsigned   far *)&(ptr)+1))
+#endif
+#ifndef _FP_OFF
+#define  _FP_OFF(ptr)   (*((unsigned   far *)&(ptr)))
+#endif
+#else /* not Intel 16-bit mode */
+#define  far   /* define to nothing */
+#endif   /* SEG16_16 */
+
+/* misc prototypes for TCP/IP demo system.*/
+extern   void  hexdump(void * pio, void * buffer, unsigned len);
+extern   char* nextcarg(char * args);
+extern   int   std_out(long s, char * buf, int len);
+extern   int   std_in(long s);
+extern   int   con_page(void * pio, int line);
+
+#ifdef MINI_IP
+/* MINI stack does not support gracefull net shutdown. If the port
+ * has not defined this call in ipport.h, then map it to exit ().
+ */
+#ifndef netexit
+#define netexit(err) exit(err);
+#endif /* netexit */
+ 
+#else  /* not MINI_IP */
+extern   void  netexit(int err);
+#endif
+
+/* Sometimes ns_printf can be #defined to dprintf, etc. In that case
+ * skip the standard declaration.
+ */
+
+#ifndef ns_printf
+extern   int   ns_printf(void * pio, char * format, ...);
+#endif
+
+/* InterNiche alloc/free entry points */
+int   mh_stats(void * IO);
+void  mheap_init(char * base, long size);
+char* calloc1(unsigned size);
+void  mem_free(char HUGE * buf);
+
+
+#ifdef INICHE_LIBS
+/* prototypes for routines in strlib.c file: */
+int   strlen(char * str);
+char* strcpy(char * str1, char * str2);
+char* strncpy(char * str1, char * str2, int max);
+int   strcmp(char * str1, char * str2);
+char* strcat(char * str1, char * str2);
+char* strchr(char * str, char chr);
+int   strncmp(char * str1, char * str2, int length);
+char * strstr(char * str1, char * str2);
+
+int   atoi(char *);
+#else /* not INICHE_LIBS, use compilers include files */
+#include "string.h"
+#endif   /* INICHE_LIBS */
+
+/* prototypes for routines in strilib.c file: */
+#ifdef INICHE_STRICMP
+int   stricmp(const char * s1, const char * s2);
+#endif   /* INICHE_STRICMP */
+#ifdef INICHE_STRNICMP
+int   strnicmp(const char * s1, const char * s2, int len);
+#endif   /* INICHE_STRNICMP */
+
+#ifdef INICHE_STRISTR
+char* stristr(char * str1, char * str2);
+#endif
+
+#ifdef __linux__
+#define FLUSH_STDOUT fflush(stdout);
+#else
+#define FLUSH_STDOUT
+#endif
+
+#endif   /* IN_UTILS_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log.h
new file mode 100644
index 0000000..c78748e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log.h
@@ -0,0 +1,52 @@
+#ifndef _INICHE_LOG_H_
+#define _INICHE_LOG_H_
+
+#include "iniche_log_port.h"
+
+/* Increase this as you add more options to glog menu */ 
+#define GLOG_MAX_ARGC 20
+
+typedef enum _logTypeEnum
+{
+   LOG_TYPE_NONE = 0,
+   LOG_TYPE_FATAL,
+   LOG_TYPE_CRITICAL,
+   LOG_TYPE_MAJOR,
+   LOG_TYPE_MINOR,
+   LOG_TYPE_WARNING,
+   LOG_TYPE_INFO,
+   LOG_TYPE_DEBUG,
+   
+   LOG_TYPE_MAX_NUM
+
+} logTypeEnum;
+
+typedef struct _log_data_t
+{
+   void * pio;
+#ifdef USE_LOGFILE
+   char log_fname[LOGFILE_NAME_SIZE];
+   NV_FILE *log_fp;
+#endif
+   unsigned long log_counts[LOG_TYPE_MAX_NUM];
+   int log_level;    /* This is the current log level */
+   int start_flag;
+   int stop_flag;
+   char **argv;
+   int argc;
+
+} log_data_t;
+
+int iniche_create_log(log_data_t **p, int log_level, char *fname, void *pio);
+void iniche_free_log(log_data_t **p);
+void log_with_type(log_data_t *p, logTypeEnum log_type, char *pstr, int printf_flag);
+
+void glog_with_type(logTypeEnum log_type, char *pstr, int printf_flag);
+int global_log_create(void);
+void global_log_free(void);
+
+int glog_app(void * pio);
+
+#endif   /* _INICHE_LOG_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log_port.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log_port.h
new file mode 100644
index 0000000..8c91d1c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/iniche_log_port.h
@@ -0,0 +1,18 @@
+#ifndef _INICHE_LOG_PORT_H_
+#define _INICHE_LOG_PORT_H_
+
+#include "ipport.h"
+#include "nvfsio.h"
+
+/* Note: USE_LOGFILE should be defined only of there exits a file system */
+#define USE_LOGFILE  1
+
+#define DEFAULT_LOG_LEVEL LOG_TYPE_DEBUG
+#define LOG_FILE_DEFAULT "./iniche.log"
+#define LOGFILE_NAME_SIZE 255
+#define LOG_MALLOC(size) npalloc(size)
+#define LOG_FREE(p)      npfree(p)
+
+#endif   /* _INICHE_LOG_PORT_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/intimers.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/intimers.h
new file mode 100644
index 0000000..8bcbd00
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/intimers.h
@@ -0,0 +1,40 @@
+/*
+ * FILENAME: intimers.c
+ *
+ * Copyright  2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Handles InterNiche task & application interval timers.
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef _INTIMERS_H
+#define _INTIMERS_H  1
+
+/* interval timer structure */
+struct intimer
+{
+   void     (*callback)(long parm);
+   long     parm;
+   u_long   interval;   /* fire interval, in TPS units */
+   u_long   tmo;        /* ctick to fire */
+   int      inuse;      /* reentrancy flag */
+};
+
+/* MAX number of interval timers in the system */
+#ifndef NUM_INTIMERS       /* Allow override from ipport.h */
+#define NUM_INTIMERS 5
+#endif
+
+extern struct intimer intimers[NUM_INTIMERS];   /* the timers */
+
+/* entry points to interval timer package */
+long  in_timerset(void (*callback)(long), long msecs, long parm);
+int   in_timerkill(long timer);
+
+#endif /* _INTIMERS_H */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ip.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ip.h
new file mode 100644
index 0000000..0061605
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ip.h
@@ -0,0 +1,498 @@
+/*
+ * FILENAME: ip.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * IP protocol definitions
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990, 1993 by NetPort Software.
+ * Portions Copyright 1986 by Carnegie Mellon 
+ * Portions Copyright 1983 by the Massachusetts Institute of 
+ * Technology 
+ */
+
+#ifndef _IPHFILE_H_
+#define  _IPHFILE_H_ 1
+
+/* For now, include IPv4 if it's not specificly excluded */
+#ifndef OMIT_IPV4
+#define IP_V4  1
+#endif
+
+/* Internet status. Keeps track of packets gone through and errors. 
+ * 10/16/90 - scrapped old structure in favor of MIB for SNMP support. 
+ * -JB- 
+ */
+struct IpMib   {
+   u_long   ipForwarding;     /* 1= we are a gateway; 2 = host */
+   u_long   ipDefaultTTL;     /* IP time to live */
+   u_long   ipInReceives;     /* total received datagrams (bad too) */
+   u_long   ipInHdrErrors;    /* Header Err (xsum, ver, ttl, etc) */
+   u_long   ipInAddrErrors;   /* nonsense IP addresses */
+   u_long   ipForwDatagrams;  /* routed packets */
+   u_long   ipUnknownProtos;  /* unknown protocol types */
+   u_long   ipInDiscards;     /* dropped (ie no buffer space) */
+   u_long   ipInDelivers;     /* delivered receive packets */
+   u_long   ipOutRequests;    /* sends (not includeing routed) */
+   u_long   ipOutDiscards;    /* sends dropped (no buffer) */
+   u_long   ipOutNoRoutes;    /* dropped, can't route */
+   u_long   ipReasmTimeout;   /* fragment reassembly timeouts */
+   u_long   ipReasmReqds;     /* frags received */
+   u_long   ipReasmOKs;       /* packets successfully reassembled */
+   u_long   ipReasmFails;     /* packets reassemblys failed */
+   u_long   ipFragOKs;        /* packets we fragmented for send */
+   u_long   ipFragFails;      /* packets we wanted to frag and couldnt */
+   u_long   ipFragCreates;    /* fragments we made */
+   u_long   ipRoutingDiscards;
+};
+
+typedef struct IpMib * IPMIB;
+extern   struct IpMib   ip_mib;
+
+
+/* This ip route structure was generated by the NetPort MIB compiler 
+ * from rfc1213. It replaces the old RtMib structure, which was built 
+ * by hand 
+ */
+/* More fields added to the table for RIP. This mechanism of adding 
+ * more fields to the same table saves lot of complexity of code. 
+ * That is there is only one Routing Table used by IP and RIP. Common 
+ * calls to add_route(), del_route, etc. Fields of RTMIB used by RIP 
+ * are as follows ipRouteDest; Destination ipRouteIfIndex; Interface 
+ * ( 1 based value) of this route ipRouteMetric1; Time To Live for 
+ * this route ipRouteNextHop; Gateway thru which we can reach 
+ * ipRouteDest ipRouteMask; Subnet Mask New fields for RIP are 
+ * ipRouteFlags; Flag is set to have triggered updates 
+ * ipRouteProxyRoute As needed by RIP2 ipRouteMainTimer To check for 
+ * Time To Live for this route ipRouteSecondaryTimer Extra time for 
+ * the entry to live !! ipRouteRouteTag As needed by RIP2 
+ * ipRouteDistMetric Distance metric of RIP2 We could have used 
+ * ipRouteMetric2, etc. but having a specific field makes code more 
+ * readable 
+ */
+
+struct RtMib
+{
+   /* btree code requires the AVL info to be attop of structure so that the
+    * same btree code can work on both IPv4 and IPv6 route tables. This must
+    * also match struct avl_node.
+    */
+#ifdef BTREE_ROUTES
+   struct avl_node * left;       /* btree brach to higher side of tree */
+   struct avl_node * right;      /* btree brach to lower side of tree */
+   enum AVLSKEW skew;            /* which branch is longer */
+   enum AVLTYPE treetype;        /* type of route v4 or v6 */
+#endif   /* BTREE_ROUTES */
+
+   u_long   ipRouteDest;
+   long     ipRouteIfIndex;   /* do not use as nets[] index! */
+   long     ipRouteMetric1;
+   long     ipRouteMetric2;
+   long     ipRouteMetric3;
+   long     ipRouteMetric4;
+   u_long   ipRouteNextHop;
+   long     ipRouteType;
+   long     ipRouteProto;
+   u_long   ipRouteAge;
+   u_long   ipRouteMask;
+   long     ipRouteMetric5;
+   void *   ipRouteInfo;   /* 32 bit ptr */
+
+   /* end of rfc1213 (MIB-2) fields */
+
+#ifdef RIP_SUPPORT
+   u_long   ipRouteMainTimer  ;
+   /* We keep the route entry for about 120s after the timeout has occured.
+    * This is done so that info about this broken route can be passed to
+    * other gateways
+    */
+   u_long   ipRouteSecondaryTimer   ; 
+   u_long   ipRouteProxyRoute;/* For   Proxy RIP-2,   0  if none */
+   /* Precisely the NextHop field of RIP2 pkt */
+   u_short  ipRouteRouteTag;  /* Route tag to send */
+   u_long   ipRouteDistMetric;
+#endif
+
+   /* flags for this route table entry (see below) */
+   int      ipRouteFlags   ; 
+
+   /* pointer to net for route. This is informationally redundant of 
+    * the field ipRouteIfIndex above, however it's more pratical now 
+    * that we support dynamic interfaces which do not appear in the 
+    * static nets[] array. 
+    */
+   struct net * ifp;
+
+};
+
+
+/* IP routing logic needs to ignore certain RIP_PRIVATE entries in 
+ * the route table, thus some RIP ipRouteFlags defines are set here. 
+ * These are also defined in RIP module with ifndefs for RIPp prots 
+ * to non-InterNiche IP stacks. 
+ */
+#define  RIP_PRIVATE    0x01  /* Private route entry */
+#define  RIP_TRIGGER    0x02  /* Do triggered update for entry */
+#define  RIP_VALID      0x04  /* valid RIP entry  */
+
+
+typedef struct RtMib * RTMIB;
+extern   RTMIB rt_mib;
+extern   unsigned ipRoutes;   /* number of entrys alloced */
+
+#ifdef BTREE_ROUTES
+/* AVL tree code entry points in rtbtree.c */
+enum AVLRES avlinsert(struct avl_node ** parent, struct avl_node * newnode);
+enum AVLRES avlremove(struct avl_node **n, void * key);
+void avldepthfirst(struct avl_node * n,
+   void(*func)(struct avl_node * n, long param, int depth),
+      long param, int depth);
+
+/* Define macros/routines to compare two nodes in the AVL tree. */
+#ifdef IP_V6
+int   AVL_LESS(struct avl_node * a, struct avl_node * b);
+int   AVL_GREATER(struct avl_node * a, struct avl_node * b);
+int   AVL_KEY_LESS(void * key, struct avl_node * b);
+int   AVL_KEY_GREATER(void * key, struct avl_node * b);
+#else    /* just IPV4, use fast macros */
+#define AVL_LESS(a, b) \
+   (htonl(((RTMIB)a)->ipRouteDest) < htonl(((RTMIB)b)->ipRouteDest))
+#define AVL_GREATER(a, b) \
+   (htonl(((RTMIB)a)->ipRouteDest) > htonl(((RTMIB)b)->ipRouteDest))
+#define AVL_KEY_LESS(key, b) \
+   ((*(ip_addr*)key) < htonl(((RTMIB)b)->ipRouteDest))
+#define AVL_KEY_GREATER(key, b) \
+   ((*(ip_addr*)key) > htonl(((RTMIB)b)->ipRouteDest))
+#endif   /* IP_V6 */
+      
+/* the actual access routines are different for IPv4 and IPv6 since
+ * they are based on IP address.
+ */
+#ifdef IP_V4
+struct avl_node * avlv4_access(struct avl_node * n, ip_addr key);
+#endif   /* IP_V4 */
+#ifdef IP_V6
+struct avl_node * avlv6_access(struct avl_node * n, ip6_addr * key);
+#endif   /* IP_V6 */
+#endif   /* BTREE_ROUTES */
+
+
+extern RTMIB cachedRoute;     /* last route entry used */
+
+extern   queue    bigfreeq;   /* big free buffers */
+extern   queue    lilfreeq;   /* small free buffers */
+
+
+/* values for ipRouteProto; */
+#define  IPRP_OTHER     1     /* none of the following */
+#define  IPRP_LOCAL     2     /* non-prot source, e.g., manually configured */
+#define  IPRP_NETMGMT   3     /* set via SNMP, CMIP, etc */
+#define  IPRP_ICMP      4     /* set via ICMP */
+#define  IPRP_EGP       5  
+#define  IPRP_GGP       6
+#define  IPRP_HELLO     7
+#define  IPRP_RIP       8  /* set via RIP */
+/* there's about 10 more we dont support */
+
+/* values for ipRouteType; */
+#define  IPRT_OTHER     1     /* none of the following */
+#define  IPRT_INVALID   2     /* invalidated */
+#define  IPRT_DIRECT    3     /* directly connected net */
+#define  IPRT_INDIRECT  4     /* non-local host/net/subnet */
+
+
+struct ip   {
+   u_char   ip_ver_ihl;    /* 4 bit version, 4 bit hdr len in 32bit words */
+   u_char   ip_tos;        /* Type of Service */
+   unshort  ip_len;        /* Total packet length including header */
+   unshort  ip_id;         /* ID for fragmentation */
+   unshort  ip_flgs_foff;  /* mask in flags as needed */
+   u_char   ip_time;       /* Time to live (secs) */
+   u_char   ip_prot;       /* protocol */
+   unshort  ip_chksum;     /* Header checksum */
+   ip_addr  ip_src;        /* Source name */
+   ip_addr  ip_dest;       /* Destination name */
+};
+
+
+/* Some useful definitions */
+
+#define  IPHSIZ   sizeof(struct  ip)   /* internet header size */
+#define  IP_VER   4     /* internet version */
+#define  IP_TSRV  0     /* default type of service */
+#define  IP_ID    0     /* kernel fills in IN id */
+#define  IP_FLGS  0     /* no fragmentation yet */
+
+/* fragmentation flag bits, for masking into 16bit flags/offset word */
+#define  IP_FLG_DF   0x4000   /* Don't   Fragment (DF) bit */
+#define  IP_FLG_MF   0x2000   /* More Fragments (MF) bit */
+#define  IP_FLG_MASK 0xe000   /* for masking out all flags from word */
+#define  IP_EXTRACT_FOFF 0x1fff /* mask to allow extraction of fragment offset field in IP header */
+
+#define  IP_FOFF  0      /* " " " */
+#ifndef  IP_TTL          /* maximum time to live */
+#define  IP_TTL   64     /* overridable from ipport.h_h */
+#endif
+#define  IP_TOS_DEFVAL 0 /* Routine Precedence, Normal Delay, Normal Throughput, Normal Reliability */ 
+#define  IPXSUM   0      /* initial checksum */
+
+/* ethernet-ish packet types in NET endian: */
+#define  IP_TYPE     htons(0x0800)
+#define  ARP_TYPE    htons(0x0806)
+
+/* Some macros for finding IP offsets in incoming packets */
+#define  ip_head(ppkt)     (struct  ip *)(ppkt->nb_prot)
+
+#define  ip_hlen(pip)      (((pip)->ip_ver_ihl  &  0x0f) << 2)
+#define  ip_data(pip)      ((char *)(pip) +  ip_hlen(pip))
+#define  ip_optlen(pip)    (ip_hlen(pip)  -  20)
+
+
+/* prototype IP routines */
+int      ip_write(u_char prot, PACKET);
+int      ip_write2(u_char prot, PACKET p, u_char * optp);
+int      ip_rcv(PACKET);      /* low level process of incomming IP */
+char *   ip_startup(void);
+
+#ifndef MINI_IP
+int      ip_demux(PACKET);    /* demux incoming IP to upper layers */
+int      ip_init(void);
+ip_addr  ip_mymach(ip_addr);
+int      ip_more(void);
+NET      iproute(ip_addr, ip_addr*);
+RTMIB    add_route(ip_addr dest, ip_addr mask, ip_addr nexthop, int iface, int type);
+int      del_route(ip_addr dest, ip_addr mask, int iface);
+RTMIB    rt_lookup(ip_addr host);
+#endif   /* MINI_IP */
+
+#ifdef IP_FRAGMENTS
+int   ip_reassm(PACKET newp);    /* process received IP fragments */
+#endif   /* IP_FRAGMENTS */
+
+#ifdef IP_RAW
+
+/* struct ipraw_ep - IP's endpoint for raw IP access
+ */
+struct ipraw_ep {
+   struct ipraw_ep * ipr_next;
+   ip_addr ipr_laddr;               /* local host IP address binding */
+   ip_addr ipr_faddr;               /* remote host IP address binding 
+                                     * (connection) */
+   int (*ipr_rcv)(PACKET, void*);   /* incoming packet handler */
+   void * ipr_data;                 /* user 'per-connection' token */
+   u_char ipr_prot;                 /* IP protocol ID binding */
+};
+
+/* ipraw_eps - pointer to list of raw IP endpoints 
+ */
+extern struct ipraw_ep * ipraw_eps;
+
+/* prototypes for raw IP API functions
+ */
+struct ipraw_ep * ip_raw_open(u_char prot, ip_addr laddr, ip_addr faddr,
+                              int (*handler)(PACKET, void *), void * data);
+void ip_raw_close(struct ipraw_ep * ep);
+int ip_raw_write(PACKET p);
+PACKET ip_raw_alloc(int datalen, int hdrincl);
+void ip_raw_free(PACKET p);
+int ip_raw_maxalloc(int hdrincl);
+
+#endif /* IP_RAW */
+
+#ifdef IP_V6
+int   ip6_init(void);         /* start the IPv6 layer */
+int   ip6_rcv(PACKET pkt);    /* receive a v6 pkt */
+#endif /* IP_V6 */
+
+#define  IN_MULTICAST(i)   (((long)(i) &  0xf0000000) == 0xe0000000)
+
+#ifdef IP_MULTICAST
+/*
+ * Internet multicast address structure.  There is one of these for each
+ * IP multicast group to which this host belongs on a given network
+ * interface.  They are kept in a linked list, rooted in the interface's 
+ * NET structure.
+ *
+ * IPv6 - Structure now contains both types of address. If both are
+ * present then either one may be valid, the other should be all zeros.
+ */
+struct in_multi
+{
+   unsigned long  inm_addr;      /* IPv4 multicast address */
+#ifdef IP_V6
+   ip6_addr    ip6addr;          /* IPv6 multicast address */
+#endif
+     NET   inm_netp;             /* back pointer to NET structure  */
+     unsigned inm_refcount;      /* no. membership claims by sockets */
+     unsigned inm_timer;         /* IGMP membership report timer */
+     u_char last2send_report;    /* were we the last to send report for this multicast group?
+                                  * 1 (true) or 0 (false) (used only for IGMPv2) */
+     struct in_multi * inm_next; /* ptr   to next  multicast   address */
+};
+
+/*
+ * Structure stored in mbuf in inpcb.ip_options
+ * and passed to ip_output when ip options are in use.
+ * The actual length of the options (including ipopt_dst)
+ * is in m_len.
+ */
+#define  MAX_IPOPTLEN   40
+#define  IP_MAX_MEMBERSHIPS   20
+
+#define  IM_ALLOC(size)    npalloc(size)
+#define  IM_FREE(ptr)      npfree(ptr)
+#define  INM_ALLOC(size)   npalloc(size)
+#define  INM_FREE(ptr)     npfree(ptr)
+
+/*
+ * Defaults and limits for multicast options
+ */
+#define  IP_DEFAULT_MULTICAST_TTL   1  /* limit m'casts to 1 hop  */
+#define  IP_DEFAULT_MULTICAST_LOOP  1  /* hear sends if a member  */
+#define  IP_MAX_MEMBERSHIPS         20 /* max memberships */
+
+/*
+ * Structure attached to inpcb.ip_moptions and
+ * passed to ip_output when IP multicast options are in use.
+ */
+struct ip_moptions
+{
+     struct net  *  imo_multicast_netp;/*   netp  for   outgoing multicasts */
+     u_char   imo_multicast_ttl;   /* TTL for outgoing multicasts */
+     u_char   imo_multicast_loop;  /* 1 => hear sends if a member */
+     u_short  imo_num_memberships;/*  no.   memberships this  socket */
+     struct in_multi * imo_membership[IP_MAX_MEMBERSHIPS];
+};
+
+/*
+ * Argument structure for IP_ADD_MEMBERSHIP and IP_DROP_MEMBERSHIP.
+ */
+struct ip_mreq
+{
+     ip_addr  imr_multiaddr;/*  IP multicast   address  of group */
+     ip_addr  imr_interface;/*  local IP address  of interface */
+};
+
+#endif   /* IP_MULTICAST */
+
+
+/*
+ * Socket options for use with [gs]etsockopt at the IP level.
+ * First word of comment is data type; bool is stored in int.
+ */
+#define  IP_OPTIONS        1  /* buf/ip_opts; set/get IP options */
+#define  IP_HDRINCL        2  /* int; header is included with data */
+#define  IP_TOS            3  /* int; IP type of service and preced. */
+#define  IP_TTL_OPT        4  /* int; IP time to live */
+#define  IP_RECVOPTS       5  /* bool; receive all IP opts w/dgram */
+#define  IP_RECVRETOPTS    6  /* bool; receive IP opts for response */
+#define  IP_RECVDSTADDR    7  /* bool; receive IP dst addr w/dgram */
+#define  IP_RETOPTS        8  /* ip_opts; set/get IP options */
+#define  IP_MULTICAST_IF   9  /* u_char; set/get IP multicast i/f  */
+#define  IP_MULTICAST_TTL  10 /* u_char; set/get IP multicast ttl */
+#define  IP_MULTICAST_LOOP 11 /* u_char; set/get IP multicast loopback */
+#define  IP_ADD_MEMBERSHIP 12 /* ip_mreq; add an IP group membership */
+#define  IP_DROP_MEMBERSHIP 13 /* ip_mreq; drop an IP group membership */
+#define  IP_SCOPEID        14 /* int; IPv6 IF scope  ID */ 
+
+int   ip2mac(PACKET, ip_addr ipaddr);     /* put IP packet on MAC layer */
+
+#ifdef NPDEBUG
+void  ip_dump(PACKET);  /* this needs printf, DEBUG = on */
+#endif
+
+int   ip_stats(void * pio);         /* print IP layer stats */
+int   ipr_stats(void * pio);        /* print IP reassembly stats */
+
+PACKET ip_copypkt(PACKET p);        /* copy packet into new buffer */
+
+/* IP/TCP checksummer; usually in assembly language somewhere... -JB- */
+unsigned short cksum(void*, unsigned);
+
+/* IPv4 broadcast address */
+#define INADDR_BROADCAST 0xffffffffL
+
+/* Host endian values for IP address class & subnet manipulation */
+#define  AMASK    htonl(0x80000000)
+#define  AADDR    htonl(0x00000000)
+#define  BMASK    htonl(0xC0000000)
+#define  BADDR    htonl(0x80000000)
+#define  CMASK    htonl(0xE0000000)
+#define  CADDR    htonl(0xC0000000)
+#define  IPLBA    htonl(0x7F000000) /* IP LoopBack net Address */
+
+
+/* ethernet & token ring protocol values in local endian: */
+#define     ARPTP    ntohs(0x0806)     /* ARP type */
+#define     IPTP     ntohs(0x0800)     /* IP type */
+
+#define     TCPTP    0x06     /* TCP type on IP (8 bit, no swap) */
+
+/*
+ * Address families, for socket() call and "domain" variables.
+ */
+
+#define  AF_INET     2     /* internetwork: UDP, TCP, etc. */
+#define  AF_INET6    3     /* IPv6 */
+#define  PF_INET6    AF_INET6
+
+/* If we are using IPSEC then we need to allow space for IPSEC headers,
+ * a trailer, and encapsulation.
+ */
+#ifdef IPSEC
+#ifndef IPSECOPT_SIZE   
+#define IPSECOPT_SIZE   98
+#endif
+#else
+#undef  IPSECOPT_SIZE
+#define IPSECOPT_SIZE   0
+#endif /* IPSEC */
+
+/* IP options */
+
+/* mask to determine option identifier */
+#define IPOPT_TYPE_MASK 0x1f
+
+/* IP Router Alert option (RFC 2113) */
+#define IP_RTR_ALERT_OPT 0x14
+#define IP_RTR_ALERT_OPT_DATA 0x94040000
+#define IP_RTR_ALERT_OPT_SIZE 0x4
+/* identifier for End of Option List option */
+#define EOL_OPT 0x0
+/* identifier for No Operation option */
+#define NOOP_OPT 0x1
+
+
+/* structure for converting ip_addr to 4 unsigned char values: */
+struct l2b  {
+   union {
+      unsigned long  iplong;
+      unsigned char  ipchar[4];
+   }ip;
+};
+
+/* boolean variable that indicates if the (UDP and TCP) socket library's 
+ * events (such as those used by tcp_sleep () and tcp_wakeup ()) map 
+ * into operating system primitives such as events, or if they map to 
+ * task suspend and task resume mechanisms.
+ */
+extern u_char so_evtmap;
+struct socket; /* forward declaration */
+/* function pointers (used only when SOCK_MAP_EVENTS is defined) for 
+ * port-specific routines that create and delete events that are used 
+ * in the operation of tcp_sleep () and tcp_wakeup ().
+ */
+extern int (*so_evtmap_create) (struct socket *);
+extern int (*so_evtmap_delete) (struct socket *);
+
+#endif   /* _IPHFILE_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ip6.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ip6.h
new file mode 100644
index 0000000..26ab906
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ip6.h
@@ -0,0 +1,464 @@
+/*
+ * FILENAME: ip6.h
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains definitions for code IPv6.
+ *
+ * If this file is included in a source along with the IPv4-ish "ip.h" file
+ * Then the IPv4 file should appear in the include list first. 
+ *
+ * MODULE: IPV6
+ *
+ * ROUTINES: 
+ *
+ * PORTABLE: yes
+ */
+
+
+#ifndef _IP6_H_
+#define _IP6_H_ 1
+
+/* Sanity test for #defines in ipport.h */
+#ifndef LINKED_PKTS
+#error IP_V6 option requires LINKED_PKTS option in ipport.h
+#endif
+
+#ifndef IP_MULTICAST
+#error IP_V6 option requires IP_MULTICAST option in ipport.h
+#endif
+
+
+/*
+ * THE IPv6 header
+ */
+struct ipv6
+{
+   u_char   ip_ver_flo[4];    /* 4 bits version (6), 8 bits class, & flow label */
+   u_short  ip_len;           /* payload length */
+   u_char   ip_nexthdr;       /* next header type 6 = TCP, etc */
+   u_char   ip_hopcount;      /* hops left until expires */
+   ip6_addr ip_src;           /* source and dest addresses */
+   ip6_addr ip_dest;
+};
+
+
+/*
+ * IP v6 extention headers
+ *
+ */
+
+struct ex6_hopopts     /* IPPROTO_HOPOPTS - type 0  */
+{
+   u_char    nexthdr;       /* type of next header */
+   u_char    extlen;		/* length of this header */
+   u_char    reserved;      /* reserved field */
+};
+
+struct ex6_destopts     /* IPPROTO_DSTOPTS - type 60 */
+{
+   u_char    nexthdr;       /* type of next header */
+   u_char    extlen;		/* length of this header */
+   u_char    reserved;      /* reserved field */
+};
+
+struct ex6_route     /* IPPROTO_ROUTE - type 43  */
+{
+   u_char   nexthdr;    /* type of next header */
+   u_char   extlen;     /* length of this header */
+   u_char   type;       /* routing header type */
+   u_char   segments;   /* segments left */
+      /* variable amount of data follows */
+};
+
+/* Fragment header */
+struct ex6_frag      /* IPPROTO_FRAGMENT - type 44 */
+{
+   u_char    nexthdr;       /* type of next header */
+   u_char    reserved;      /* reserved field */
+   unshort   offset;        /* offset and flag */
+   u_long    id;            /* IP packet identification */
+};
+
+#define op6_frag ex6_frag  /* cover rename */ 
+#define IPV6_MOREFRAGS  0x01  /* "more frags" flag in frag->offset */
+
+struct ex6_auth         /* IPPROTO_AH - type 51 */
+{
+   u_char    nexthdr;       /* type of next header */
+   u_char    reserved;      /* reserved field */
+
+
+};
+
+struct ex6_esp       /* IPPROTO_ESP - type 50 */
+{
+   u_char    nexthdr;       /* type of next header */
+   u_char    reserved;      /* reserved field */
+
+
+};
+
+
+
+
+/*
+ * An Interniche IP v6 address for this machine
+ */
+
+struct net;    /* predecl */
+
+struct ip6_inaddr
+{
+   struct ip6_inaddr *  next;    /* for application use */
+   ip6_addr             addr;    /* address value (maybe unassigned) */
+   int                  prefix;  /* number of bits in prefix */
+   struct net *         ifp;     /* iface associated with it (maybe NULL) */
+   int                  flags;   /* mask of the IA_ bits below */
+   u_long               tmo1;    /* expiration ctick if IA_LEASE flag set */
+   u_long               tmo2;    /* expiration ctick of address */
+   u_long               lasttm;  /* last action for dup checking, etc. */
+   int                  dups;    /* count of DADNS sent */
+};
+
+
+/* values for in6_addr->flags */
+#define IA_STATEMASK    0x03     /* low two bits have one of the following: */
+#define IA_TENTATIVE    0x00     /* address is being checked for duplicate */
+#define IA_PREFERRED    0x01     /* tmo1 field is end of "preferred" period */
+#define IA_DEPRECATE    0x02     /* address is being deprecated */
+
+#define IA_MFLAG        0x04     /* ManagedFlag, RFC-2462 */
+#define IA_OFLAG        0x08     /* OtherConfigFlag, RFC-2462 */
+#define IA_LEASE        0x10     /* tmo1 field is a finite lease */
+
+
+
+/* ipv6->nexthdr values. Names are from RFC-2292 (IPv6 raw sockets) */
+#define  IPPROTO_HOPOPTS   0  /* IPv6 Hop-by-Hop options */
+#define  IPPROTO_IPV6      41 /* IPv6 header */
+#define  IPPROTO_ROUTING   43 /* IPv6 Routing header */
+#define  IPPROTO_FRAGMENT  44 /* IPv6 fragmentation header */
+#define  IPPROTO_ESP       50 /* encapsulating security payload */
+#define  IPPROTO_AH        51 /* authentication header */
+#define  IPPROTO_ICMPV6    58 /* ICMPv6 */
+#define  IPPROTO_NONE      59 /* IPv6 no next header */
+#define  IPPROTO_DSTOPTS   60 /* IPv6 Destination options */
+
+
+#define  IPV6_MINMTU    1280   /* recommended path MTU for IPv6 Internet (rfc2460) */
+#define  IPV6_MAXMTU    1500   /* large path MTU for IPv6  */
+
+#define ND_DEFRALG_OLD  0     /* use oldest router */
+#define ND_DEFRALG_RR   1     /* use round robin router */
+
+#define ND_PMTU_ID   0        /* ideally comply with RFC1981 PMTU storage */
+#define ND_PMTU_MIN  1        /* minimally comply with RFC1981 PMTU storage */
+
+/* values for ND_send_RS_Flag */
+#define ND_SEND_RS  0        /* send out RS at init */
+#define ND_NOTSEND_RS  2     /* do not send out RS at init */
+
+extern ip6_addr allRoutersMcast;
+extern ip6_addr allNodesMcast;
+extern ip6_addr ip6unspecified;
+extern ip6_addr ip6loopback;
+extern ip6_addr ip6llloopback;
+
+extern NET ip6_lbnet;    /* loopback interface */
+
+extern ip6_route * rt6_lookup(ip6_addr * dest);
+
+
+/* define address testing macros (as per rfc2553) */
+#define __IPV6_ADDR_MC_SCOPE(a)		((a)->addr[1] & 0x0f)
+#define __IPV6_ADDR_SCOPE_NODELOCAL	0x01
+#define __IPV6_ADDR_SCOPE_LINKLOCAL	0x02
+#define __IPV6_ADDR_SCOPE_SITELOCAL	0x05
+#define __IPV6_ADDR_SCOPE_ORGLOCAL	0x08	/* just used in this file */
+#define __IPV6_ADDR_SCOPE_GLOBAL	0x0e
+
+/*
+ * Unicast Scope
+ * Note that we must check topmost 10 bits only, not 16 bits (see RFC2373).
+ */
+
+/* Macro to identify IPv6 multicast addresses */
+#define IN6_IS_ADDR_MULTICAST(ipaddr)  ((ipaddr)->addr[0] == 0xFF)
+
+/* Macro to identify IPv6 multicast scope */
+#define IN6_IS_ADDR_MCSCOPE(ipaddr)   ((ipaddr)->addr[1] & 0x0F)
+
+/* Macro to identify IPv6 global address - highest 3 bits are 001 */
+#define IN6_IS_ADDR_GLOBAL(ipaddr) (((ipaddr)->addr[0] & 0xE0) == 0x20)
+
+/* Macro to identify IPv6 Link-local addresses */
+#define IN6_IS_ADDR_LINKLOCAL(ipaddr) \
+     (((ipaddr)->addr[0] == 0xFE) && \
+     ((ipaddr)->addr[1] == 0x80))
+
+/* Macro to identify IPv6 Site-local addresses */
+#define IN6_IS_ADDR_SITELOCAL(ipaddr) \
+     (((ipaddr)->addr[0] == 0xFE) && \
+     ((ipaddr)->addr[1] == 0xC0))
+
+#define IN6_IS_ADDR_UNSPECIFIED(ipaddr) (IP6EQ(ipaddr, &ip6unspecified))
+#define IN6_IS_ADDR_LOOPBACK(ipaddr) \
+     ((IP6EQ(ipaddr, &ip6loopback)) || (IP6EQ(ipaddr, &ip6lllopback)))
+
+
+/* Following macros from RFc2553 are not currently used 
+int  IN6_IS_ADDR_V4MAPPED    (const struct in6_addr *);
+int  IN6_IS_ADDR_V4COMPAT    (const struct in6_addr *);
+*/
+
+#define IN6_IS_SCOPE_LINKLOCAL(a)	\
+	((IN6_IS_ADDR_LINKLOCAL(a)) ||	\
+	 (IN6_IS_ADDR_MC_LINKLOCAL(a)))
+
+
+#define IN6_IS_ADDR_MC_NODELOCAL(a)	\
+	(IN6_IS_ADDR_MULTICAST(a) &&	\
+	 (__IPV6_ADDR_MC_SCOPE(a) == __IPV6_ADDR_SCOPE_NODELOCAL))
+#define IN6_IS_ADDR_MC_LINKLOCAL(a)	\
+	(IN6_IS_ADDR_MULTICAST(a) &&	\
+	 (__IPV6_ADDR_MC_SCOPE(a) == __IPV6_ADDR_SCOPE_LINKLOCAL))
+#define IN6_IS_ADDR_MC_SITELOCAL(a)	\
+	(IN6_IS_ADDR_MULTICAST(a) && 	\
+	 (__IPV6_ADDR_MC_SCOPE(a) == __IPV6_ADDR_SCOPE_SITELOCAL))
+#define IN6_IS_ADDR_MC_ORGLOCAL(a)	\
+	(IN6_IS_ADDR_MULTICAST(a) &&	\
+	 (__IPV6_ADDR_MC_SCOPE(a) == __IPV6_ADDR_SCOPE_ORGLOCAL))
+#define IN6_IS_ADDR_MC_GLOBAL(a)	\
+	(IN6_IS_ADDR_MULTICAST(a) &&	\
+	 (__IPV6_ADDR_MC_SCOPE(a) == __IPV6_ADDR_SCOPE_GLOBAL))
+/*
+ * Macros to compare or copy IPv6 addresses. These may be replaced
+ * (in ipport.h) with macros or routines which are more efficient
+ * on a particular compiler.
+ */
+#ifndef  IP6EQ
+ /* compare two IP addresses, return TRUE if the same; else FALSE */
+#define IP6EQ(addrptr1, addrptr2) (!MEMCMP(addrptr1, addrptr2, sizeof(ip6_addr)))
+#endif
+
+/* Macro to copy IPv6 addresses */
+#ifndef  IP6CPY
+/* Copy addrptr2 into addrptr1 */
+#define IP6CPY(addrptr1, addrptr2) MEMCPY(addrptr1, addrptr2, sizeof(ip6_addr))
+#endif
+
+/*
+ * global IPv6 routines
+ */
+
+/* standard IPv6 to MAC send routines */
+extern   int   ip6_sendeth(PACKET pkt, struct in6_addr * router);
+extern   int   ip6_sendppp(PACKET pkt);
+
+/* Set up addresses of interface for IPv6 */
+int   ip6_ifaddrs(struct net * ifp);
+
+/* per-port routine to handle sending packets on odd MAC types */
+extern   int  (*ip6_portsend)(PACKET pkt, struct in6_addr * router);
+
+/* Routine to send an IPv6 packet */
+int   ip6_send(PACKET pkt, int fields);
+
+/* ip6_send() "fields" bits: */
+#define  IP6F_FLOW   0x01     /* Set Flow control field */
+#define  IP6F_LEN    0x02     /* Set length field from nb_plen */
+#define  IP6F_HOPS   0x04     /* Set hops */
+#define  IP6F_ROUTE  0x08     /* Set nexthop and iface */
+
+/* popular combinations */
+#define  IP6F_NOROUTE  (IP6F_FLOW | IP6F_LEN | IP6F_HOPS)
+#define  IP6F_ALL    0xFF     /* Set all fields */
+
+/* 
+ * default value for defualt life time of prefix 
+ * after a redirect to a router without 
+ * an RA.
+ */
+#define IP6_DEFAULT_LIFETIME (TPS * 5)
+
+#define IP6_2HOURSSECS (2 * 60 * 60)
+
+/* Routine to demux packet to upper protocols */
+int   ip6_demux(PACKET pkt, u_char type);
+
+/* IPv6 routing table lookup */
+struct ip6_inaddr * ip6_lookup(ip6_addr * findaddr, NET ifp);
+
+/* logical prep for a net to do IPv6 (reg type, etc) */
+int   ip6_device(struct net * ifp);
+
+/* build ipv6 mcast addr based on MAC addr */
+int   ip6_setmcast(struct net * ifp);
+
+/* build the struct containing a new IPv6 address */
+struct ip6_inaddr *  ip6_mkaddr(struct net * ifp, int type, ip6_addr * addr);
+
+/* routine to add in the IPv6 pseudo header cksum to a passed cksum */
+unshort   ip6_pseudosum(struct ipv6 *, u_long len, u_char nexthdr);
+
+/* send icmp6 parameter message. */
+void ip6_badparam(PACKET pip, int type, int code, u_long disp);
+
+/* routines to process IPv6 extension headers */
+int   ip6_routehdr(PACKET pkt, int hdr_disp);
+int   ip6_tvlopt(PACKET pkt, int z, int hdr_disp);
+
+
+/* fragmentation and reassembly */
+int   ip6_fragment(PACKET pkt, int fields);
+int   ip6_reasm(PACKET *pkt, int z, int hdr_disp);
+
+
+/* upper protocol handlers for received v6 pkts */
+int   udp6_rcv(PACKET pkt);
+int   tcp6_rcv(PACKET pkt);
+
+/* get path MTU to a IP6 host */
+int   ip6_pmtulookup(ip6_addr * faddr, NET ifp);
+
+/* get address of ours of matching type */
+struct ip6_inaddr * ip6_mataddr(ip6_addr * addr, NET reqifp);
+
+/* Formatting routines ip6addr <-> text */
+char *   print_ip6( /* IN */ ip6_addr * addr, /* OUT */ char * str);
+
+extern char * pton_error;     /* explanation of last inet_pton failure */
+
+/* RFC 2462 RetransTimer, in cticks */
+extern u_long ip6RetransTimer;
+
+/* format string tables for printf()ing IPv6 info */
+extern char * v6types[5];
+extern char * ip6addrstates[4];  /* index by "IA_TENTATIVE", etc */
+
+#ifndef IP6_ALLOC
+#define IP6_ALLOC(size)    (struct ip6_inaddr *)npalloc(size)
+#define IP6_FREE(ptr)      npfree(ptr)
+#endif /* IP6_ALLOC */
+
+unshort  cksum(void * buf, unsigned words16);   /* basic IP cksum */
+
+
+/* IPv6 Generic tunnel configuration info. These should be set up for
+ * each non-6to4 tunnel. If NV_PARMS is used they should be
+ * set from that, otherwise the system init code should fill
+ * these in before calling the prep_ routine. The IPv6 addresses
+ * in this struct are assigned by your tunnel provider (or your
+ * sys admin people if you ARE a tunnel provider). 
+ */
+
+/* Number of IPv6 tunnels (INCLUDING 6TO4) to be supported */
+#ifndef MAXTUNNELS            /* can override from ipport.h_h */
+#define MAXTUNNELS MAXNETS    /* max number of tunnels */
+#endif   /* MAXTUNNELS */
+
+
+struct tn_configinfo
+{
+   char *      ifname;     /* name of tunnel to set up (eg "tu0") */
+   ip6_addr    lhost6;     /* local v6 address (assigned by tunnel provider) */
+   int         lpflen;     /* local v6 addr prefix length */
+   ip_addr     fhost4;     /* IPv4 address of tunnel provider */
+};
+
+/* The actual configs. Note that these are pointers. NULL is OK, but app
+ * must provide the static memory for any tunnel if wants to configure.
+ * These are matched to tunnel interfaces via the ifname field. Lower
+ * interface to use may be set by if_bind() call, and defaults to first
+ * Ethernet if not set.
+ *
+ * 6to4 does not need one of these.
+ */
+extern struct tn_configinfo * tunnelcfg[MAXTUNNELS];
+
+
+/*
+ * Various ipv6 timers. ip6_timer is invoked by the system once a second, and
+ * it handles the others
+ */
+extern void ip6_timer(void);
+extern void nd_timer(void);
+extern void ping6_timer(void);
+extern void ip6_fragcheck(void);
+
+
+/* Routing functions. */
+
+/* get local address relative to a remote address */
+struct ip6_inaddr * ip6_myaddr(ip6_addr * dest, NET ifp);
+/* get our source addr to mtach dest addr */
+struct ip6_inaddr * ip6_matchmyaddr(ip6_addr * dest, NET ifp);
+
+/* get iface, nexthop, & source. Main external entry to routing code. */
+int   ip6_destif( PACKET pkt,
+            ip6_addr * dest,
+            ip6_addr ** source);
+
+
+ip6_route * rt6_route(ip6_addr * dest);   /* basic route select */
+
+ip6_route *rt6_addroute(
+   ip6_addr *  dest,       /* ultimate destination */
+   int         prefixlen,  /* 128 for exact route */
+   NET         ifp);
+   
+ 
+int rt6_addprefix(ip6_addr * a1,  int prefixlen, NET ifp,    
+   u_long   pmtu,          /* PMTU for this link */
+   u_long   invalid_time,  /* time at which invalid, in ticks */
+   u_long   life_time,     /* Preferred Lifetime */
+   int  flags
+   );
+
+int   rt6_delroute(ip6_addr * dest, int pflen, NET ifp);
+
+/* IPv6 logging macros */
+#ifdef IPV6LOGING
+extern char ipv6WrkBuffer[50];
+#define IPV6TIMEZ    { \
+	  IPV6LOG(("+ cticks %ld\n", cticks)); \
+	}
+#define IPV6DUMP(name, a,b) {dprintf(name); hexdump6(a,b); dprintf("+ EOD\n");}
+#define IPV6LOG(text) dprintf ## text
+#define IPV6CDUMP    nd_dump()
+#else
+#define IPV6LOG(text)
+#define IPV6DUMP(name, a,b)
+#define IPV6TIMEZ
+#define IPV6CDUMP
+#endif
+
+/* List of constants defined in rfc2461 - use later */
+/* Router constants: */
+#define MAX_INITIAL_RTR_ADVERT_INTERVAL  16   /* seconds */
+#define MAX_INITIAL_RTR_ADVERTISEMENTS    3   /* transmissions */
+#define MAX_FINAL_RTR_ADVERTISEMENTS      3   /* transmissions */
+#define MIN_DELAY_BETWEEN_RAS             3   /* seconds */
+#define MAX_RA_DELAY_TIME                 .5  /* seconds */
+/* Host constants: */
+#define MAX_RTR_SOLICITATION_DELAY        1   /* seconds */
+#define RTR_SOLICITATION_INTERVAL         4   /* seconds */
+#define MAX_RTR_SOLICITATIONS             3   /* transmissions */
+#define RTR_DEFAULT_LIFE                  (60 * 60 * 18)   /* seconds */
+/* Node constants: */
+#define MAX_MULTICAST_SOLICIT             3   /* transmissions */
+#define MAX_UNICAST_SOLICIT               3   /* transmissions */
+#define MAX_ANYCAST_DELAY_TIME            1   /* seconds */
+#define MAX_NEIGHBOR_ADVERTISEMENT        3   /* transmissions */
+#define REACHABLE_TIME               30000   /* milliseconds */
+#define RETRANS_TIMER                 1000   /* milliseconds */
+#define DELAY_FIRST_PROBE_TIME            5   /* seconds */
+#define MIN_RANDOM_FACTOR                 (1 / 2)
+#define MAX_RANDOM_FACTOR                 (3 / 2)
+#define REASM_TIMEOUT                     (TPS * 60)
+
+
+#endif   /* _IP6_H_ - whole file ifdef */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/libport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/libport.h
new file mode 100644
index 0000000..89b6e49
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/libport.h
@@ -0,0 +1,72 @@
+/*
+ * Filename: libport.h
+ *
+ * Copyright 2004 by InterNiche Technologies.
+ *
+ * All the platform specific defines for each port go here.
+ * All these should be re-examined with each new port of the code.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * 06/21/2004
+ *
+ */
+
+#ifndef _LIBPORT_H_
+#define _LIBPORT_H_   1
+
+#ifndef INICHE_LIBS   /* use Standard C libs; strlib (strcat, strcpy, etc) */
+#include <stdlib.h>   /* for atoi(), exit() */
+#include <string.h>
+#endif
+#ifdef PRINTF_STDARG
+#include <stdarg.h>
+#endif 
+
+/* options specific to the utilities library */
+
+/* enabled options */
+/*
+ * Altera Niche Stack modifcation 12-Feb-2008 (jrk):
+ * These are provided in newlib. Removing.
+ */
+//#define INICHE_STRICMP  1     /* no stricmp in C library */
+//#define INICHE_STRNICMP 1     /* no strnicmp in C library */
+//#define INICHE_STRISTR  1     /* no stristr in C library */
+
+#ifdef NOTDEF
+#define INCLUDE_FLASHFS 1     /* NV params read from flash */
+#endif
+
+#ifdef INCLUDE_FLASHFS
+#define FLASHBASE 0x70000000  /* memory address to build FFS on net186 */
+#define FLASHFIRM 0xD0000000  /* base of flash to store FFS net186 */
+#define NUMNVFILES 8          /* numnber of flash files allowed */
+#define NVFSIZE   (1024*4)    /* reserved size for each flash file */
+#endif
+
+/* misc prototypes for TCP/IP misclib port */
+void	panic(char * msg);
+#ifdef PRINTF_STDARG
+void  doprint(char * target, char * sp, va_list va);
+#else  /* PRINTF_STDARG */
+void  doprint(char * target, char * sp, int * vp);
+#endif /* PRINTF_STDARG */
+
+/* map memory routines to standard lib */
+#define MEMCPY(dst,src,size)  memcpy((void *)(dst),(void *)(src),(size))
+#define MEMMOVE(dst,src,size) memmove((void *)(dst),(void *)(src),(size))
+#define MEMSET(ptr,val,size)  memset((void *)(ptr),(val),(size))
+#define MEMCMP(p1,p2,size)    memcmp((void *)(p1),(void *)(p2),(size))
+
+#ifndef isdigit
+#define isdigit(_c)  ((_c >= '0' && _c <= '9') ? 1:0)
+#endif
+
+#endif /* _LIBPORT_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/mbuf.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/mbuf.h
new file mode 100644
index 0000000..563048e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/mbuf.h
@@ -0,0 +1,84 @@
+/*
+ * FILENAME: mbuf.h
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This is the definitions file for NetPort mbufs. These 
+ * are sytacticly used like BSD mbufs in the BSD derived C code, 
+ * however the actual buffer space managed is mapped inthe a NetPort 
+ * style PACKET structure. Concepts and Portions of this file are 
+ * adapted from the BSD sources.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. All rights reserved. */
+
+
+#ifndef _MBUF_H
+#define  _MBUF_H  1
+
+/* mbuf struct - just a wrapper for nb_buff */
+
+struct mbuf
+{
+   struct mbuf *  next;    /* queue link */
+   PACKET   pkt;           /* the nb_buff, w/actual contiguous buffer */
+   unsigned m_len;         /* length of m_data */
+   char *   m_data;        /* pointer to next data */
+   char *   m_base;        /* base of buffer, <= m_data */
+   unsigned m_memsz;       /* size of buffer at m_base */
+   struct mbuf *  m_next;  /* next mbuf in record (TCP) */
+   struct mbuf *  m_act;   /* start of next record (UDP) */
+   int      m_type;        /* as in UNIX; 0==free */
+};
+
+/* mbuf types */
+#define  MT_FREE     0     /* should be on free list */
+#define  MT_RXDATA   1     /* dynamic (data) allocation */
+#define  MT_TXDATA   2     /* dynamic (data) allocation */
+#define  MT_HEADER   3     /* packet header */
+#define  MT_SOCKET   4     /* socket structure */
+#define  MT_PCB      5     /* protocol control block */
+#define  MT_RTABLE   6     /* routing tables */
+#define  MT_HTABLE   7     /* IMP host tables */
+#define  MT_ATABLE   8     /* address resolution tables */
+#define  MT_SONAME   9     /* socket name */
+#define  MT_SOOPTS   10    /* socket options */
+#define  MT_FTABLE   11    /* fragment reassembly header */
+#define  MT_RIGHTS   12    /* access rights */
+#define  MT_IFADDR   13    /* interface address */
+
+/* flags to m_get */
+#define  M_DONTWAIT  0
+#define  M_WAIT      1
+
+#define  CLBYTES     1400
+#define  M_COPYALL   -1
+
+extern   struct mbuf *     m_getnbuf   __P ((int type, int len));
+
+void     m_adj(struct mbuf * mp, int len);
+int      mbuf_len (struct mbuf * m);
+
+/* map all the Mango & BSD mbuf "get()" calls in the nbuf wrapper */
+#define  m_getwithdata(type,  len)  m_getnbuf(type,   len)
+#define  m_get(waitflag,   type) m_getnbuf(type,   0)
+#define  MFREE(m, n)    ((n)  =  m_free(m))
+#define  mtod(mb, cast)    (cast)(mb->m_data)
+
+extern   struct mbuf *     m_copy   __P ((struct mbuf *, int, int));
+extern   struct mbuf *  m_free   __P ((struct mbuf *));
+extern   void  m_freem  __P ((struct mbuf *));
+extern   struct mbuf *  dtom  __P ((void *));
+
+#endif   /* _MBUF_H */
+
+/* end of file mbuf.h */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/memwrap.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/memwrap.h
new file mode 100644
index 0000000..2981dd8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/memwrap.h
@@ -0,0 +1,24 @@
+/*
+ * FILENAME: memwrap.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc.  All rights reserved.
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef MEMWRAP_H
+#define MEMWRAP_H
+
+int      wrap_stats(void * pio);
+char *   wrap_alloc(unsigned size, char * (*alloc_rtn)(unsigned));
+void     wrap_free(char * ptr, void (*free_rtn)(char *));
+
+#ifndef ALIGN_TYPE
+#error ALIGN_TYPE must be defined for this system
+#endif
+
+#endif /* MEMWRAP_H */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/menu.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/menu.h
new file mode 100644
index 0000000..661163d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/menu.h
@@ -0,0 +1,59 @@
+/*
+ * FILENAME: menu.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Structure for simple application menu system.
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990,1993 by NetPort Software */
+
+
+#ifndef MENU_H
+#define  MENU_H   1
+
+#include "in_utils.h"
+
+/* a menu can be defined as an array of these structures. Selecting a 
+ * key can invoke the corrosponding function. 
+ */
+
+struct menu_op                /* structure to describe each menu item */
+{
+   char *   opt;              /* the option name */
+   int (*func)(void * pio);   /* routine name to execute the option */
+   char *   desc;             /* description of the option */
+};
+
+#define  CBUFLEN     128            /* size of cbuf */
+extern   char        cbuf[CBUFLEN]; /* user command line buffer */
+
+#define  MAX_MENUS   25
+extern   struct menu_op *menus[MAX_MENUS];      /* master menu list */
+extern   char *versions[MAX_MENUS];             /* master version list */
+
+/* menu routine prototypes: */
+extern   int      install_menu(struct menu_op * newmenu);   /* add new menu */
+extern   int      install_version(char * version);       /* add new version */
+extern   char *   getcmd(void);           /* get cmdline into cbuf while spinning tasks */
+extern   void     showmenu(void * pio, struct menu_op *);
+extern   int      help(void * pio);       /* display menu prompt text */
+extern   int      stooges(void * pio);    /* called when system breaks */
+extern   int      do_command(void * pio); /* parse & perform command */
+extern   char *   nextarg(char*);         /* get nexxt arg from a string */
+extern   int      stlen(char*);           /* like strlen, but not exactly */
+extern   int      stcmp(char*, char*);    /* like strcmp, but not exactly */
+extern   int      setdebug (void * pio);
+extern   int      arp_stats(void * pio);
+extern   u_long   sysuptime(void);
+
+char **parse_args(char *buf, int argc, int *pargc_index);
+
+#endif   /* MENU_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/msring.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/msring.h
new file mode 100644
index 0000000..6d93b9a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/msring.h
@@ -0,0 +1,37 @@
+/* FILENAME: msring.h
+ *
+ * Definitions for ring buffer support for NicheLite M_SOCKs.
+ * See misclib/msring.c for implementation.
+ *
+ * PORTABLE: YES
+ * 
+ * MODULE: H
+ */
+
+#ifndef MSRING_H_
+#define MSRING_H_
+
+#ifdef MINI_TCP
+
+/* struct msring - a ring buffer structure for NicheLite sockets
+ */
+struct msring
+{
+   M_SOCK * buf;           /* ptr to storage for buffered M_SOCKs */
+   unsigned buflen;        /* length (in M_SOCKs) of buf */
+   unsigned in;            /* index into buf: where to add next M_SOCK */
+   unsigned out;           /* index into buf: where to delete next M_SOCK */
+};
+
+/* function prototypes */
+void msring_init(struct msring * ring,
+                 M_SOCK * buf,
+                 unsigned bufsize);
+void msring_add(struct msring * ring,
+                M_SOCK so);
+int msring_del(struct msring * ring,
+               M_SOCK * so);
+
+#endif /* MINI_TCP */
+
+#endif  /* MSRING_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nameser.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nameser.h
new file mode 100644
index 0000000..6ca3553
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nameser.h
@@ -0,0 +1,427 @@
+/*
+ * FILENAME: nameser.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: DNS
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *
+ * Portions Copyright (c) 1993 by Digital Equipment Corporation.
+ * 
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies, and that
+ * the name of Digital Equipment Corporation not be used in advertising or
+ * publicity pertaining to distribution of the document or software without
+ * specific, written prior permission.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS" AND DIGITAL EQUIPMENT CORP. DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL DIGITAL EQUIPMENT
+ * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
+ * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ * -
+ * --Copyright--
+ */
+
+#ifndef __ARPA_NAMESER_H__
+#define  __ARPA_NAMESER_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *      @(#)nameser.h 8.1 (Berkeley) 6/2/93
+ * $Id: nameser.h,v 1.1.2.2 2007/11/02 00:46:58 steveh Exp $
+ */
+/*
+ * revision information.  this is the release date in YYYYMMDD format.
+ * it can change every day so the right thing to do with it is use it
+ * in preprocessor commands such as "#if (__BIND > 19931104)".  do not
+ * compare for equality; rather, use it to determine whether your resolver
+ * is new enough to contain a certain feature.
+ */
+#define  __BIND   19950621 /* interface version stamp */
+
+/*
+ * Define constants based on rfc883
+ */
+#define  PACKETSZ 512   /* maximum packet size */
+#define  MAXDNAME 256   /* maximum domain name */
+#define  MAXCDNAME   255   /* maximum compressed domain name */
+#define  MAXLABEL 63 /* maximum length of domain label */
+#define  HFIXEDSZ 12 /* #/bytes of fixed data in header */
+#define  QFIXEDSZ 4  /* #/bytes of fixed data in query */
+#define  RRFIXEDSZ   10 /* #/bytes of fixed data in r record */
+#define  INT32SZ  4  /* for systems without 32-bit ints */
+#define  INT16SZ  2  /* for systems without 16-bit ints */
+#define  INADDRSZ 4  /* for sizeof(struct inaddr) != 4 */
+
+/*
+ * Internet nameserver port number
+ */
+#define  NAMESERVER_PORT   53
+
+/*
+ * Currently defined opcodes
+ */
+#define  QUERY    0x0   /* standard query */
+#define  IQUERY   0x1   /* inverse query */
+#define  STATUS   0x2   /* nameserver status query */
+   /*   0x3     0x3 reserved */
+#define  NS_NOTIFY_OP   0x4   /* notify secondary of SOA change */
+   /* non standard - supports ALLOW_UPDATES stuff from Mike Schwartz */
+# define UPDATEA 0x9    /* add resource record */
+# define UPDATED 0xa /* delete a specific resource record */
+# define UPDATEDA 0xb   /* delete all named resource record */
+# define UPDATEM 0xc /* modify a specific resource record */
+# define UPDATEMA 0xd   /* modify all named resource record */
+# define ZONEINIT 0xe   /* initial zone transfer */
+# define ZONEREF 0xf /* incremental zone referesh */
+
+/*
+ * Currently defined response codes
+ */
+#define  NSNOERROR   0  /* no error */
+#define  FORMERR  1  /* format error */
+#define  SERVFAIL 2  /* server failure */
+#define  NXDOMAIN 3  /* non existent domain */
+#define  NOTIMP   4  /* not implemented */
+#define  REFUSED  5  /* query refused */
+   /* non standard */
+# define NOCHANGE 0xf   /* update failed to change db */
+
+/* 
+ * DDNS response codes
+ */
+#define  YXDOMAIN (6)
+#define  YXRRSET (7)
+#define  NXRRSET (8)
+#define  NOTAUTH (9)
+#define  NOTZONE (10)
+
+#define  C_ANY    255   /* wildcard match */
+#define  C_NONE (254)
+#define  C_IN  1  /* the arpa internet */
+
+/*
+ * Type values for resources and queries
+ */
+#define  T_A   1  /* host address */
+#define  T_NS  2  /* authoritative server */
+#define  T_MD  3  /* mail destination */
+#define  T_MF  4  /* mail forwarder */
+#define  T_CNAME  5  /* canonical name */
+#define  T_SOA    6  /* start of authority zone */
+#define  T_MB  7  /* mailbox domain name */
+#define  T_MG  8  /* mail group member */
+#define  T_MR  9  /* mail rename name */
+#define  T_NULL   10 /* null resource record */
+#define  T_WKS    11 /* well known service */
+#define  T_PTR    12 /* domain name pointer */
+#define  T_HINFO  13 /* host information */
+#define  T_MINFO  14 /* mailbox information */
+#define  T_MX  15 /* mail routing information */
+#define  T_TXT    16 /* text strings */
+#define  T_RP  17 /* responsible person */
+#define  T_AFSDB  18 /* AFS cell database */
+#define  T_X25    19 /* X_25 calling address */
+#define  T_ISDN   20 /* ISDN calling address */
+#define  T_RT  21 /* router */
+#define  T_NSAP   22 /* NSAP address */
+#define  T_NSAP_PTR  23 /* reverse NSAP lookup (deprecated) */
+#define  T_SIG    24 /* security signature */
+#define  T_KEY    25 /* security key */
+#define  T_PX  26 /* X.400 mail mapping */
+#define  T_GPOS   27 /* geographical position (withdrawn) */
+#define  T_AAAA   28 /* IP6 Address */
+#define  T_LOC    29 /* Location Information */
+   /* non standard */
+#define  T_UINFO  100   /* user (finger) information */
+#define  T_UID    101   /* user ID */
+#define  T_GID    102   /* group ID */
+#define  T_UNSPEC 103   /* Unspecified format (binary data) */
+   /* Query type values which do not appear in resource records */
+#define  T_AXFR   252   /* transfer zone of authority */
+#define  T_MAILB  253   /* transfer mailbox records */
+#define  T_MAILA  254   /* transfer mail agent records */
+#define  T_ANY    255   /* wildcard match */
+
+/*
+ * Values for class field
+ */
+#define  C_IN  1  /* the arpa internet */
+#define  C_CHAOS  3  /* for chaos net (MIT) */
+#define  C_HS  4  /* for Hesiod name server (MIT) (XXX) */
+   /* Query class values which do not appear in resource records */
+#define  C_ANY    255   /* wildcard match */
+
+/*
+ * Status return codes for T_UNSPEC conversion routines
+ */
+#define  CONV_SUCCESS   0
+#define  CONV_OVERFLOW  (-1)
+#define  CONV_BADFMT (-2)
+#define  CONV_BADCKSUM  (-3)
+#define  CONV_BADBUFLEN (-4)
+
+#ifndef BYTE_ORDER
+
+#define  LITTLE_ENDIAN  1234  /* least-significant byte first (vax, pc) */
+#define  BIG_ENDIAN  4321  /* most-significant byte first (IBM, net) */
+#define  PDP_ENDIAN  3412  /* LSB first in word, MSW first in long (pdp)*/
+
+#if defined(vax) || defined(ns32000) || defined(sun386) || defined(i386) || \
+   defined(MIPSEL) || defined(_MIPSEL) || defined(BIT_ZERO_ON_RIGHT) || \
+   defined(__alpha__) || defined(__alpha)
+#define  BYTE_ORDER  LITTLE_ENDIAN
+#endif
+
+#if defined(sel) || defined(pyr) || defined(mc68000) || defined(sparc) || \
+   defined(is68k) || defined(tahoe) || defined(ibm032) || defined(ibm370) || \
+   defined(MIPSEB) || defined(_MIPSEB) || defined(_IBMR2) || defined(DGUX) ||\
+   defined(apollo) || defined(__convex__) || defined(_CRAY) || \
+   defined(__hppa) || defined(__hp9000) || \
+   defined(__hp9000s300) || defined(__hp9000s700) || \
+   defined (BIT_ZERO_ON_LEFT) || defined(m68k)
+#define  BYTE_ORDER  BIG_ENDIAN
+#endif
+
+#endif   /* BYTE_ORDER */
+
+#if !defined(BYTE_ORDER) || \
+   (BYTE_ORDER != BIG_ENDIAN && BYTE_ORDER != LITTLE_ENDIAN && \
+    BYTE_ORDER != PDP_ENDIAN)
+   {
+ /* you must determine what the correct bit order is for
+  * your compiler - the next line is an intentional error
+  * which will force your compiles to bomb until you fix
+  * the above macros.
+  */
+      error "Undefined or invalid BYTE_ORDER";
+   }
+#endif
+
+#ifdef NS_DDNS
+#define MAX_NAM_LEN 256
+
+struct ResRec
+{
+    struct ResRec *next;  /* pointer to next RR */
+	char name[MAX_NAM_LEN];   /* name */
+	unsigned short  type;      /* type */
+	unsigned short  dclass;     /* class */
+	unsigned long  ttl;         /* TTL */
+	short  RDlength;    /* length of Rdata */
+	int    flags;       /* keep track of processing within a chain */
+	char *RdataP;     /* Rdata, N.b., this still points into 
+	                   * the original msg! */
+};
+
+typedef struct ResRec RR;
+
+/* RR flags */
+#define RR_CH_MATCHED     (1)
+#define  NS_UPDATE (5)     /* DDNS update */
+
+struct DQDesc
+{
+	char zone[MAX_NAM_LEN];   /* ZONE */
+	RR   *perqsP;     /* pointer to prerequisites */
+	RR   *upsP;       /* pointer to updates */
+	RR   *addsP;      /* pointer to addition RRs */
+};
+
+typedef struct DQDesc DQDESC;
+
+DQDESC * dns_parse_ddqry(u_char * msg, int msglen, int buflen, int errCode);
+int dns_dynup(DQDESC * DQDp);
+
+#endif
+
+
+
+/*
+ * Structure for query header.  The order of the fields is machine- and
+ * compiler-dependent, depending on the byte/bit order and the layout
+ * of bit fields.  We use bit fields only in int variables, as this
+ * is all ANSI requires.  This requires a somewhat confusing rearrangement.
+ */
+#if 1 /* We don't use bit fields they are not portable ** Narayan **/
+   typedef struct 
+   {
+      unsigned short id;  /* query ident number  */
+      unsigned char bits [2];
+      unsigned short qdcount;   /* number of question entries */
+      unsigned short ancount;   /* number of answer entries */
+      unsigned short nscount;   /* number of authority entries */
+      unsigned short arcount;   /* number of resource entries */
+   } HEADER;
+
+#define  HEADER_GET_RCODE(x)  ((x)->bits  [1]   &  0xf)
+#define  HEADER_GET_PR(x)  ((x)->bits[1]  &  0x40)
+#define  HEADER_GET_RA(x)  ((x)->bits  [1]   &  0x80)
+#define  HEADER_GET_RD(x)  ((x)->bits  [0]   &  0x1)
+#define  HEADER_GET_TC(x)  ((x)->bits  [0]   &  0x2)
+#define  HEADER_GET_AA(x)  ((x)->bits  [0]   &  0x4)
+#define  HEADER_GET_OPCODE(x) (((x)->bits [0]   >> 3) &  0xF)
+#define  HEADER_GET_QR(x)  ((x)->bits  [0]   &  0x80)
+
+#define  HEADER_CLR_PR(x)  ((x)->bits  [1]   &  ~0x40)
+#define  HEADER_SET_PR(x)  ((x)->bits  [1]   |= 0x40)
+#define  HEADER_SET_RA(x)  ((x)->bits  [1]   |= 0x80)
+#define  HEADER_SET_RD(x)  ((x)->bits  [0]   |= 0x1)
+#define  HEADER_CLR_RD(x)  ((x)->bits  [0]   &= ~0x1)
+#define  HEADER_SET_TC(x)  ((x)->bits  [0]   |= 0x2)
+#define  HEADER_CLR_TC(x)  ((x)->bits  [0]   &= ~0x2)
+#define  HEADER_SET_AA(x)  ((x)->bits  [0]   |= 0x4)
+#define  HEADER_CLR_AA(x)  ((x)->bits  [0]   &= ~0x4)
+#define  HEADER_SET_RCODE(x,v)   {(x)->bits  [1]   |= ((v)  &  0xf);}
+#define  HEADER_SET_QR(x)  ((x)->bits  [0]   |= 0x80)
+#define  HEADER_CLR_QR(x)  ((x)->bits  [0]   &= ~0x80)
+#define  HEADER_SET_OPCODE(h,code)  {(h)->bits  [0]   |= ((code)  << 3);}
+#else /* Use BIT-Fields */
+   typedef struct 
+   {
+      unsigned id :16;    /* query identification number */
+#if BYTE_ORDER == BIG_ENDIAN
+      /* fields in third byte */
+      unsigned qr: 1;  /* response flag */
+      unsigned opcode: 4; /* purpose of message */
+      unsigned aa: 1;  /* authoritive answer */
+      unsigned tc: 1;  /* truncated message */
+      unsigned rd: 1;  /* recursion desired */
+      /* fields in fourth byte */
+      unsigned ra: 1;  /* recursion available */
+      unsigned pr: 1;  /* primary server reqd (nonstd) */
+      unsigned unused :2; /* unused bits (MBZ as of 4.9.3a3) */
+      unsigned rcode :4;  /* response code */
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN || BYTE_ORDER == PDP_ENDIAN
+      /* fields in third byte */
+      unsigned rd :1;  /* recursion desired */
+      unsigned tc :1;  /* truncated message */
+      unsigned aa :1;  /* authoritive answer */
+      unsigned opcode :4; /* purpose of message */
+      unsigned qr :1;  /* response flag */
+      /* fields in fourth byte */
+      unsigned rcode :4;  /* response code */
+      unsigned unused :2; /* unused bits (MBZ as of 4.9.3a3) */
+      unsigned pr: 1;  /* primary server reqd (nonstd) */
+      unsigned ra :1;  /* recursion available */
+#endif
+      /* remaining bytes */
+      unsigned qdcount :16;  /* number of question entries */
+      unsigned ancount :16;  /* number of answer entries */
+      unsigned nscount :16;  /* number of authority entries */
+      unsigned arcount :16;  /* number of resource entries */
+   } HEADER;
+#endif   /* 0 */
+
+/*
+ * Defines for handling compressed domain names
+ */
+#define  INDIR_MASK  0xc0
+
+/*
+ * Structure for passing resource records around.
+ */
+   struct rrec {
+        int16_t  r_zone;  /* zone number */
+        int16_t  r_class; /* class number */
+        int16_t  r_type;  /* type number */
+        u_int32_t   r_ttl;   /* time to live */
+        int   r_size;  /* size of data area */
+        char  *  r_data;  /* pointer to data */
+   };
+
+/*
+ * Inline versions of get/put short/long.  Pointer is advanced.
+ *
+ * These macros demonstrate the property of C whereby it can be
+ * portable or it can be elegant but rarely both.
+ */
+#define GETSHORT(s, cp) { \
+ u_char *t_cp = (u_char *)(cp); \
+ (s) = ((u_int16_t)t_cp[0] << 8) \
+     | ((u_int16_t)t_cp[1]) \
+     ; \
+ (cp) += INT16SZ; \
+}
+
+#define GETLONG(l, cp) { \
+ u_char *t_cp = (u_char *)(cp); \
+ (l) = ((u_int32_t)t_cp[0] << 24) \
+     | ((u_int32_t)t_cp[1] << 16) \
+     | ((u_int32_t)t_cp[2] << 8) \
+     | ((u_int32_t)t_cp[3]) \
+     ; \
+ (cp) += INT32SZ; \
+}
+
+#define PUTSHORT(s, cp) { \
+ u_int16_t t_s = (u_int16_t)(s); \
+ u_char *t_cp = (u_char *)(cp); \
+ *t_cp++ = (u_char)(t_s >> 8); \
+ *t_cp   = (u_char)t_s; \
+ (cp) += INT16SZ; \
+}
+
+#define PUTLONG(l, cp) { \
+ u_int32_t t_l = (u_int32_t)(l); \
+ u_char *t_cp = (u_char *)(cp); \
+ *t_cp++ = (u_char)(t_l >> 24); \
+ *t_cp++ = (u_char)(t_l >> 16); \
+ *t_cp++ = (u_char)(t_l >> 8); \
+ *t_cp   = (u_char)t_l; \
+ (cp) += INT32SZ; \
+}
+
+#define  syslog(l,fmt)
+#define  syslog1(l,fmt,a)
+#define  syslog2(l,fmt,a,b)
+#define  syslog3(l,fmt,a,b,c)
+#ifdef __cplusplus
+}
+#endif
+#endif   /* !__ARPA__NAMESER_H__ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/net.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/net.h
new file mode 100644
index 0000000..c935185
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/net.h
@@ -0,0 +1,478 @@
+/*
+ * FILENAME: net.h
+ *
+ * Copyright 1996- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Definitions for the basic network interface object, the NET structure.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1996 by NetPort Software. 
+ * Portions Copyright 1986 by Carnegie Mellon 
+ * Portions Copyright 1983,1984,1985 by the Massachusetts Institute 
+ * of Technology 
+ */
+
+#ifndef _NET_H_
+#define  _NET_H_  1
+
+#include "q.h"
+#include "profiler.h"
+
+#ifdef BTREE_ROUTES  /* These must be before #include "ip6mibs.h" */
+/* enum values to support the route table btree software */
+enum AVLSKEW {	NONE,	LEFT, RIGHT };
+enum AVLRES { BT_ERROR = 0, BT_OK, BT_BALANCE };
+
+/* types of btrees we support with rtbtree.c code */
+enum AVLTYPE { IPV4_ROUTE, IPV6_ROUTE  };
+
+typedef  unsigned long AVLDATUM;
+struct avl_node {
+   struct avl_node * left;       /* btree brach to higher side of tree */
+   struct avl_node * right;      /* btree brach to lower side of tree */
+   enum AVLSKEW skew;            /* which branch is longer */
+   enum AVLTYPE treetype;        /* type of route v4 or v6 */
+};
+#endif   /* BTREE_ROUTES */
+
+
+#ifdef IP_V6
+
+/*
+ * The basic IPv6 address; as per RFC2133
+ */
+
+struct in6_addr {
+   u_char   addr[16];   /* 128 bit IPv6 address */
+};
+
+typedef struct in6_addr ip6_addr;
+
+/*
+ * Many of the IPv6 MIB groups are kept on a per-iafce basis, so it's
+ * helpful to include them here
+ */
+#include "ip6mibs.h"
+
+#endif /* IP_V6 */
+
+
+
+/* some SNMP-derived net interface types, per rfc 1156, pg 14 */
+/* ...these values now assigned by RFC-1700 */
+#define  ETHERNET       6
+#define  TOKEN802       9
+#define  SLIP           28       /* SLIP, per rfc1213 */
+#define  PPP            23       /* PPP, per rfc1213 */
+#define  LOOPIFTYPE     24       /* loopback, per rfc1213 */
+
+/* ifType values not covered by RFCs */
+#define  EXTERN_IPX     205      /* netx.exe, not internal IPX  */
+#define  PPPOE          206      /* Not in RFC1156, add unique number */
+#define  IP6GIF         207      /* IPv6 Generic Interface Tunnel */
+#define  IP6TO4         208      /* IPv6 "6to4" tunnel */
+
+
+/* The following structure is the iface MIB from rfc1213. Most fields are
+ * simple counters and are used as such by the InterNiche networking code.
+ * Two exceptions are ifAdminStatus and ifOperStatus. We have tried to
+ * keep their use consistent with the RFC.
+ *    When an interface (NET) is created, it is marked down (i.e. the
+ * ifAdminStatus is set to the "down" position) so that it can safely
+ * be configured (a separate step), and then marked "up" once
+ * configuration is complete. A NET with ifAdminStatus==DOWN will
+ * not be used to send by the inet code.
+ *    ifOperStatus should indicate the actual state of the link. For
+ * ethernet this probably means UP almost all the time. For PPP it means
+ * UP when connected, DOWN other wise; thus a modem in AUTOANSWER would
+ * have the same ifAdminStatus and ifOperStatus (UP, DOWN) as a
+ * disconnected modem.
+ */
+
+struct IfMib
+{
+   u_long   ifIndex;          /*  1 - entry in nets[] */
+   char    *ifDescr;          /*  2 - string describing interface */
+   u_long   ifType;           /*  3 - Ether, token, etc */
+   u_long   ifMtu;            /*  4 - Max Transmission Unit */
+   u_long   ifSpeed;          /*  5 - Theoretical max in bits/sec */
+   u_char * ifPhysAddress;    /*  6 - node address */
+   u_long   ifAdminStatus;    /*  7 - up=1, down=2, testing=3 */
+   u_long   ifOperStatus;     /*  8 - up=1, down=2, testing=3 */
+   u_long   ifLastChange;     /*  9 - time of current ifOperState */
+   u_long   ifInOctets;       /* 10 - bytes received */
+   u_long   ifInUcastPkts;    /* 11 - DELIVERED unicast packets */
+   u_long   ifInNUcastPkts;   /* 12 - non-unicast delivered packets */
+   u_long   ifInDiscards;     /* 13 - dropped, ie no buffers */
+   u_long   ifInErrors;       /* 14 - bad received packets */
+   u_long   ifInUnknownProtos;/* 15 - unknown  protocols */
+   u_long   ifOutOctets;      /* 16 - bytes sent */
+   u_long   ifOutUcastPkts;   /* 17 - unicasts sent */
+   u_long   ifOutNUcastPkts;  /* 18 - non-unicast packets sent */
+   u_long   ifOutDiscards;    /* 19 - send dropped - non-error */
+   u_long   ifOutErrors;      /* 20 - send dropped - errors */
+   u_long   ifOutQLen;        /* 21 - packets queued for send */
+};
+
+typedef struct IfMib * IFMIB;
+
+extern   IFMIB ifmibs[];      /* preallocated interface MIB structures */
+
+#ifndef IF_NAMELEN
+#define IF_NAMELEN   4        /* default max length for iface names */
+#endif
+
+#ifdef IP_MULTICAST
+struct in_multi;     /* predecl */
+#endif   /* IP_MULTICAST */
+
+
+#ifndef MAX_V6_ADDRS          /* allow override from ipport.h */
+#define MAX_V6_ADDRS    5     /* link, site, global and Mcast, defgw */
+#endif
+
+#ifdef IP_V6
+struct net;
+/* prefix list */
+struct prefixList
+{
+   struct prefixList * next;         /* list link */
+   struct prefixList * prev;         /* list link */
+   ip6_addr prefix;        /* prefix */
+   struct net      * net;           /* IF pointer */
+   int      flags;         /* flags */
+   int      prefixLen;     /* prefix length */
+   u_long      pmtu;          /* PMTU for this link */
+   u_long   invalid_time;  /* time at which invalid, in ticks */
+   u_long   life_time;     /* Preferred Lifetime */
+   u_long saved_valid_lifetime;    /* lifetime, saved from the RA */
+};
+
+typedef struct prefixList RTR_PRFLIST;
+
+/* flags for prefixList */
+#define PREFX_TOO_BIG       (1 << 2)  /* indicates that an ICMP toobig */
+                                      /* has tried to set PMTU < 1280. */
+                                      /* even tho the PMTU is still >= 1280, */
+                                      /* all pkts must contain a frag hdr. */							                
+struct routerConfigEntry
+{
+	int MaxRtrAdvInterval;  /* The maximum time allowed between sending
+                            * unsolicited multicast Router Advertisements from
+                            * the interface, in seconds.
+                            */
+	int MinRtrAdvInterval;  /* The minimum time allowed between sending
+                            * unsolicited multicast Router Advertisements from
+                            * the interface, in seconds.
+                            */
+        u_long  nextRtrAdSend;  /* ctick time for next Rtr Ad. */
+        u_long  lastRtrAdSend;  /* ctick time for last Rtr Ad. */
+        int     initlRtrAds;    /* number of initial RA's sent */
+	u_long AdvLinkMTU;         /* The value to be placed in MTU options sent by the
+                            * router.
+                            */
+	int AdvReachableTime;   /* The value to be placed in the Reachable Time field
+                            * in the Router Advertisement messages sent by the
+                            * router.
+                            */
+	int AdvRetransTimer;    /* The value to be placed in the Retrans Timer field
+                            * in the Router Advertisement messages sent by the
+                            * router. 
+                            */
+	int AdvCurHopLimit;     /* The default value to be placed in the Cur Hop Limit
+                           * field in the Router Advertisement messages sent by
+                           * the router.
+                           */
+	int AdvDefaultLifetime; /* The value to be placed in the Router Lifetime field
+                            * of Router Advertisements sent from the interface,
+                            * in seconds.
+                            */
+  struct net * ifp;               /* pointer to nets entry */
+  unsigned int flags;     /* see values below */
+	RTR_PRFLIST *prefxEntries;  	 /* list of prefixes */
+};
+typedef struct routerConfigEntry RTR_CNFN;
+
+/* flags for RTR_CNFN */
+#define RTRCF_SND_ADS        1         /* router will send ads. */
+#define RTRCF_MANGD          (1 << 1)  /* managed configuration */  
+#define RTRCF_OTHR           (1 << 2)  /* other means of configuration */  
+#define RTRCF_INITRA         (1 << 3)  /* sending inital RA's */  
+#define RTRCF_READY2SEND     (1 << 4)  /* nextRtrAdSend has been set */  
+#define RTRCF_FWD            (1 << 5)  /* forward pkts - act as router. */  
+#endif  /* IP_V6 */
+
+
+/* The NET struct has all the actual interface characteristics which 
+ * are visible at the internet level and has pointers to the 
+ * interface handling routines. 
+ */
+
+struct net
+{
+   struct net * n_next;    /* pointer next net */
+   char  name[IF_NAMELEN]; /* device ID name */
+   int   (*n_init)(int);   /* net initialization routine */
+   /* MAC drivers can set one of the next two for sending; other
+    * should be left as NULL:
+    */
+   int   (*raw_send)(struct net *, char*, unsigned);   
+                           /* put raw data on media */
+   int   (*pkt_send)(struct netbuf *);    /* send packet on media */
+   int   (*n_close)(int);  /* net close routine */
+   int   (*n_reg_type)(unshort, struct net*); 
+                           /* register a MAC type, ie 0x0800 for IP */
+   void  (*n_stats)(void * pio, int iface);   
+                           /* per device-type (ODI, pktdrv) statistics dump */
+   int   n_lnh;            /* net's local net header  size */
+   int   n_mtu;            /* net's largest legal buffer size size */
+   ip_addr  n_ipaddr;      /* interface's internet address */
+   int      n_snbits ;     /* number of subnet bits */
+   ip_addr  snmask;        /* interface's subnet mask */
+   ip_addr  n_defgw;       /* the default gateway for this net */
+   ip_addr  n_netbr;       /* our network broadcast address */
+   ip_addr  n_netbr42;     /* our (4.2BSD) network broadcast  */
+   ip_addr  n_subnetbr;    /* our subnetwork broadcast address */
+   unsigned n_hal;         /* Hardware address length */
+   struct IfMib mib;       /* the actual iface MIB image */
+   IFMIB    n_mib;         /* pointer to mib for backward compatability */
+   void *   n_local;       /* pointer to custom info, null if unused */
+   void *   n_local2;      /* used only for MQX (contains pointer to MQX 
+                            * Ethernet configuration structure, 
+                            * ENET_CFG_STRUCT_PTR) or WinPcap 4.0-based
+                            * driver (contains pointer to struct wpcap_dev) */
+   int      n_flags;       /* mask of the NF_ bits below */
+
+#ifdef DYNAMIC_IFACES
+   int   (*n_setstate)(struct net*, int);
+                           /* set link state up/down */
+#endif   /* DYNAMIC_IFACES */
+
+#ifdef IP_V6
+   /* A V6 iface has a whole slew of IP addresses: */
+   struct   ip6_inaddr *  v6addrs[MAX_V6_ADDRS];
+   struct   ip6_inaddr *  v6addrsExtd[MAX_V6_ADDRS];   /* this allows for 2 IPv6 addrs, of each type, per IF. */
+   int      DupAddrDetectTransmits;       /* per RFC-2463 */
+   struct   ipv6If_mib     ip6_ifmib;     /* IPv6 MIb - per iface group */
+   struct   icmp6_mib      icmp6_ifmib;   /* and another for ICMP */
+   struct   ip6_inaddr     *ip6_lookupcache;   /* last router addr. */
+   int                     IPv6IFUp;      /* IPv6 IF up. */
+   void                    *lastDefRouter;  /* ndcache of last router. */
+   int                     ip6_dupchecks;   /* count of dupe NS checks to be done */
+   int                     ND_send_RS;   /* flag to send RS */
+   int                     cntRtrSols;  /* count of RS */
+   int                     lasttmRtrSols;  /* last time RS */
+   int                     gotRouter;     /* got a router */
+   RTR_CNFN             *  rtrConfig;    /* pointer to router config */
+#endif /* IP_V6 */
+
+#ifdef  IP_MULTICAST
+   /* register a multicast list */
+   int      (*n_mcastlist)(struct in_multi *);
+   struct in_multi * mc_list;
+#if defined (IGMP_V1) || defined (IGMP_V2)
+   /* boolean variable that indicates our belief in whether the 
+    * network currently "has" a  v1 router.  This variable is 
+    * set to false (0) at startup for IGMPv2, and is always true
+    * for IGMPv1.
+    */
+   u_char igmpv1_rtr_present; /* 1 (IGMP_TRUE) or 0 (IGMP_FALSE) */
+   /* this variable keeps track of when (in ticks) the last IGMPv1
+    * Host Membership Query message was received (the contents of
+    * this variable are only valid when we believe that the network
+    * has a v1 router).  This is only valid for a link that is
+    * configured in IGMPv2 mode.
+    */
+   u_long igmpv1_query_rcvd_time;
+   /* operating mode for IGMP on this link - IGMPv1 or IGMPv2 */
+   u_char igmp_oper_mode;   
+#endif /* IGMPv1 or IGMPv2 */
+#endif /* IP_MULTICAST */
+};
+
+typedef  struct net * NET;
+
+extern   unsigned    ifNumber;   /* how many links (number of nets[] used) */
+
+/*
+ * These serve as IPv6 address types AND indexes into the v6addrs
+ * table for key addresses.
+ */
+#define IPA_LINK     0     /* Link local IP v6 address */
+#define IPA_SITE     1     /* Site local IP v6 address  */
+#define IPA_GLOBAL   2     /* Global IP v6 address  */
+#define IPA_MCAST    3     /* Mcast, for Neighbor discovery */
+#define IPA_DEFGW    4     /* default gateway for IPv6 */
+
+
+/* bit definitions for net.n_flags */
+
+#define  NF_BCAST    0x0001   /* device supports broadcasts */
+#define  NF_MCAST    0x0002   /* device supports multicast */
+#define  NF_DYNIF    0x0004   /* Iface is a dynamic interface */
+#define  NF_NBPROT   0x0008   /* driver will maintain pkt->nb_prot field */
+#define  NF_GATHER   0x0010   /* driver supports scatter gather */
+#define  NF_IEEE48   0x0020   /* hardware has an IEEE 48 bit address */
+#define  NF_IEEE64   0x0040   /* hardware has an IEEE 64 bit address */
+#define  NF_IPV6     0x0080   /* Iface supports IPv6 */
+#define  NF_DHCPC    0x0100   /* Iface uses DHCP Client to obtain IP addr */
+#define  NF_AUTOIP   0x0200   /* Iface uses AutoIP to obtain IP addr */
+#define  NF_6TO4     0x0400   /* Iface is RFC-3056 "6to4" tunnel */
+
+#ifdef IP_MULTICAST
+/* prototype multicast routines in ipmc.c: */
+struct in_multi *    lookup_mcast(ip_addr addr, NET netp);
+struct in_multi *    in_addmulti(ip_addr *ap, struct net * netp, int type);
+void                 in_delmulti(struct in_multi * inm);
+NET *                mcaddr_net(ip_addr);
+#ifdef IP_V6
+struct in_multi *    v6_lookup_mcast(ip6_addr * addr, NET netp);
+NET *                v6mcaddr_net(ip_addr);
+#endif   /* IP_V6 */
+#endif   /* IP_MULTICAST */
+
+
+/* parameters to ni_set_state - match RFC-1213 ifXxxxStatus */
+#define  NI_UP     1
+#define  NI_DOWN   2
+
+#ifdef DYNAMIC_IFACES
+
+struct niconfig_0    /* struct for iface configuration info */
+{
+   ip_addr  n_ipaddr;
+   ip_addr  snmask;
+};
+
+int      ni_create(NET * ifp,    /* OUT - created handle */
+                   int (*create_device)(NET newifp, void * bindinfo),  /* IN */
+                   char *name,         /* IN - short text name of device */
+                   void *blindinfo);
+int      ni_get_config(NET, struct niconfig_0 *);
+int      ni_set_config(NET, struct niconfig_0 *);
+int      ni_set_state(NET, int opcode);
+int      ni_delete(NET ifp);
+#endif  /* DYNAMIC_IFACES */
+
+extern unsigned   ifNumber;      /* how many ifaces in system */
+
+/* In non-dynamic interface systems STATIC_NETS will be the same as 
+ * MAXNETS, so don't force all the ipport.h_h files to define it.
+ */
+#ifndef STATIC_NETS
+#define STATIC_NETS  MAXNETS
+#endif
+
+extern   NET   nets[MAXNETS];    /* pointers to the static network structs */
+extern   queue netlist;          /* master list of nets, static & dynamic */
+
+
+#ifndef MINI_IP   /* Declare things defined away in the mini version */
+/* define a way to convert NET pointers to index numbers */
+int      if_netnumber(NET);   /* get index into nets list for NET */
+NET      if_getbynum(int);    /* get static/dynamic NET from index */
+int      isbcast(NET ifc, u_char * addr); /* is MAC address broadcast? */
+extern   int   reg_type(unshort);   /* register prot type with all net drivers */
+
+extern   int   MaxLnh;        /* Largest local net header size */
+extern   int   MaxMtu;        /* Largest net MTU (packet) size */
+#endif   /* MINI_IP */
+
+
+/* alias macro to support older code */
+#define  net_num(net)   if_netnumber(net)
+
+extern   queue rcvdq;
+
+
+/* Macro for passing IP addresses to printf octet at a time. usage: 
+ * printf("IP is %u.%u.%u.%u\n", PUSH_IPADDR(ip)); Since we store IP 
+ * addresses in net endian, it's endian sensitive. 
+ */
+#if (BYTE_ORDER==LITTLE_ENDIAN)
+#define  PUSH_IPADDR(ip)\
+   (unsigned)(ip&0xff),\
+   (unsigned)((ip>>8)&0xff),\
+   (unsigned)((ip>>16)&0xff),\
+   (unsigned)(ip>>24)
+#else
+#define  PUSH_IPADDR(ip)\
+   (unsigned)(ip>>24),\
+   (unsigned)((ip>>16)&0xff),\
+   (unsigned)((ip>>8)&0xff),\
+   (unsigned)(ip&0xff)
+#endif
+
+/* Here are the debugging things. DEBUG is a global variable whose 
+ * value determines what sort of debugging messages will be displayed 
+ * by the system. 
+ */
+extern   unsigned NDEBUG;  /* Debugging options */
+
+
+/* BUGHALT on a gross applications level error
+ * that is detected in the network code
+ */
+#define  BUGHALT     0x01  /* deprecated */
+
+/* Works in conjuction with other options: BUGHALT: 
+ * Dump all arriving packets PROTERR: Dump header for level of error 
+ * NETTRACE, etc.: Dump headers at trace 
+ */
+#define DUMP 0x02
+
+
+#define  INFOMSG     0x04     /* Print general informational messages */
+#define  NETERR      0x08     /* Display net interface error messages */
+#define  PROTERR     0x10     /* Display protocol level error messages */
+#define  NETRACE     0x20     /* Trace packet in link level net layer */
+#define  TMO         0x40     /* Print message on timeout */
+#define  APTRACE     0x80     /* Trace packet through application */
+#define  TPTRACE     0x100    /* Transport protocol (UDP/TCP/RVD) trace */
+#define  IPTRACE     0x200    /* Trace packet in internet layer  */
+#define  UPCTRACE    0x400    /* trace upcall progress - DANGEROUS! */
+#define  LOSSY_RX    0x800    /* do lossey receive */
+#define  LOSSY_TX    0x1000   /* do lossey transmit */
+
+
+#ifdef  LOSSY_IO
+/* support for an option that allows us to deliberatly loose packets */
+extern int   in_lastloss;  /* packets since last loss */
+extern int   in_lossrate; /* number of packets to punt (3 is "1 in 3") */
+#endif   /* LOSSY_IO */
+
+/* add prototypes -JB- */
+int   Netinit(void);
+void  netclose(void);
+void  net_stats(void);
+
+
+/* C language misc prototypes for IP stack
+ * these are not strictly NET related, but have to go somewhere
+ */
+
+u_long   c_older(u_long ct1, u_long ct2);    /* return older ctick */
+void     panic(char * msg);         /* call on fatal errors, like UNIX panic() */
+unsigned long   getipadd(char *);   /* resolve hostname to IP address */
+char *   parse_ipad(unsigned long *, unsigned *, char *);
+char *   print_ipad(unsigned long); /* format IP addr for print */
+char *   startup(void);    /* master network "start" cmd, in startup.c */
+#ifndef MINI_IP
+void     exit_hook(void (*func)(void));   /* like atexit() */
+void     ip_exit(void);             /* call exit_hook funcs */
+#endif  /* MINI_IP */
+
+/* ip2mac() Trys to put IP packet on ethernet, resolving ip address via arp. */
+int      ip2mac(PACKET, ip_addr);
+void     pktdemux(void);            /* process received packets */
+
+#endif   /* _NET_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/netbuf.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/netbuf.h
new file mode 100644
index 0000000..e3d1084
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/netbuf.h
@@ -0,0 +1,177 @@
+/*
+ * FILENAME: netbuf.h
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Descriptions of the packet buffer structure, etc. 
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1993 by NetPort Software. 
+ * Portions Copyright 1986 by Carnegie Mellon 
+ * Portions Copyright 1983 by the Massachusetts Institute of 
+ * Technology
+ */
+ 
+/* Each buffer is in a 
+ * queue, either the free queue or the used queue (or the buffer is 
+ * currently being used by a user program or the interrupt level 
+ * routines, in which case it does not appear in a queue). When a 
+ * buffer is in a queue, it has a pointer to the next buffer in the 
+ * queue. If there is no next buffer, its pointer points at null. 
+ * Also, each buffer knows its own length. 
+ */
+
+#ifndef _NETBUF_H
+#define  _NETBUF_H   1
+
+/* 
+ * save socket options to be passed via the PACKET.
+ */
+struct ip_socopts
+{
+	u_char ip_tos;     /* TOS */
+	u_char ip_ttl;     /* TTL */
+	unsigned int  ip_scopeid; /* IF scope ID */
+};
+
+
+/* This include file gives the structure of PACKET buffers. 
+ * INCOMING: Incoming packets are always front-aligned in the 
+ * nb_buff field. The nb_prot pointer is set to nb_buff by the 
+ * receiver and advanced by each layer of the stack before 
+ * upcalling the next; ie the ethernet driver bumps the prot field 
+ * by 14 and decrements plen by 14. PACKETs are pk_alloc()ed by 
+ * the receiving net layer and pk_free()ed by the transport layer 
+ * or application when it's finished with them. OUTGOING: 
+ * Protocols install data into nb_buff with a front pad big enough 
+ * to accomadate the biggest likely protocol headers, ususally 
+ * about 62 bytes (14 ether + 24 IP + 24 TCP, where IP & TCP each 
+ * have option fields.) prot plen are set for this data, and the 
+ * protocol headers are prepended as the packet goes down the 
+ * stack. nb_buff is not used in this case except for overflow 
+ * checks. PACKETs are pk_alloc()ed by the sending protocol and 
+ * freed by the lower layer level that dispatches them, usually 
+ * net link layer driver. They can be held by ARP for several 
+ * seconds while awaiting arp replys on initial sends to a new IP 
+ * host, and the ARP code will free them when a reply comes in or 
+ * times out. 
+ */
+
+struct netbuf
+{
+   struct netbuf * next;   /* queue link */
+   char   * nb_buff;    /* beginning of raw buffer */
+   unsigned nb_blen;    /* length of raw buffer */
+   char   * nb_prot;    /* beginning of protocol/data */
+   unsigned nb_plen;    /* length of protocol/data */
+   long     nb_tstamp;  /* packet timestamp */
+   struct net *   net;  /* the interface (net) it came in on, 0-n */
+   ip_addr  fhost;      /* IP address asociated with packet */
+   unsigned short type; /* IP==0800 filled in by recever(rx) or net layer.(tx) */
+   unsigned inuse;      /* use count, for cloning buffer */
+   unsigned flags;      /* bitmask of the PKF_ defines */
+
+#ifdef PPP_MULTILINK
+   void * link;         /* which of Multiple links to use */
+#endif /* PPP_MULTILINK */
+   
+#ifdef MINI_TCP            /* Mini TCP has no mbuf wrappers, so: */
+   char *   m_data;        /* pointer to TCP data in nb_buff */
+   unsigned m_len;         /* length of m_data */
+   struct netbuf * m_next; /* sockbuf que link */
+#endif   /* MINI_TCP */
+
+#ifdef IP_MULTICAST
+   struct ip_moptions * imo;  /* IP multicast options */
+#endif
+
+#ifdef LINKED_PKTS
+   /* support scatter/gather - required for IPv6, tunneling, et.al. */
+   struct netbuf * pk_prev;   /* previous pkt in chain */
+   struct netbuf * pk_next;   /* next ptk in chain */
+   int      nb_tlen;          /* total length of nb_prots in pk_next list */
+#ifdef IP_V6
+   struct ipv6 * ip6_hdr;     /* "Current" IPv6 header */
+   struct in6_addr * nexthop; /* for pass to ipv6_send() */
+   int      nb_pmtu;          /* Path MTU for sends */
+#endif   /* IP_V6 */
+#endif   /* LINKED_PKTS */
+   struct ip_socopts *soxopts; /* socket options */
+};
+
+/* bits for pkt->flags field */
+#define  PKF_BCAST    0x01
+#define  PKF_MCAST    0x02
+#define  PKF_IPOPTS   0x04     /* ip_socopts present */
+#define  PKF_HEAPBUF  0x08     /* if bit is 1, buffer is allocated from the heap (i.e., it is a heap buffer); */
+                               /* if bit is 0, buffer is a regular (little or big) buffer */
+#define  PKF_INTRUNSAFE 0x10   /* if bit is 1, buffer can't be allocated or deallocated from interrupt-level; */
+                               /* if bit is 0, buffer can be allocated or deallocated from interrupt-level */
+
+#define  PKF_IPV6_GBL_PING  0x20  /* global ping, if MC scope == 0xE */   
+#define  PKF_IPV6_PREPEND_DONE  0x40  /* mark the prepend of eth data */
+                                      /* has been done to the head of */
+                                      /* this pkt. */
+                                       
+typedef struct netbuf * PACKET;     /* struct netbuf in netbuf.h */
+
+/* Indexes into the memestats [] array (defined in pktalloc.c) for various 
+ * failure and success conditions encountered in the packet buffer allocation 
+ * and deallocation processes.  The first three error counters 
+ * (bad_regular_buf_len, guard_band_violated, and multiple_free_err) are for 
+ * regular buffers only.  The 'inconsistent_location' field is a counter for 
+ * both regular and heap buffers.
+ */
+                                    /* number of times when pk_validate () discovered a buffer of length that
+                                     * is not greater than bigbufsiz (and is therefore assumed to be a "regular"
+                                     * buffer), but its length is neither lilbufsiz nor bigbufsiz */
+#define BAD_REGULAR_BUF_LEN_ERR   0
+                                    /* number of instances when pk_validate () discovered that a regular buffer's
+                                     * left or right guard band was violated */
+#define GUARD_BAND_VIOLATED_ERR   1
+                                    /* number of instances when pk_validate () discovered that a regular buffer
+                                     * (that was being freed via pk_free ()) already existed on the little or big
+                                     * free buffer queues */
+#define MULTIPLE_FREE_ERR         2
+                                    /* number of instances when pk_validate () discovered that a packet's 
+                                     * next pointer and inuse count are inconsistent.  When a packet is
+                                     * provided to the user, its next pointer is set to 0, and its inuse
+                                     * counter is set to 1.  An inuse count of >= 1 indicates that the packet
+                                     * is being used.  A non-zero next pointer indicates that the packet
+                                     * resides in the free queue (with a few exceptions, such as when the
+                                     * next pointer is utilized to queue up packets pending for an ARP 
+                                     * request). */
+#define INCONSISTENT_LOCATION_ERR 3
+#define MEMERR_NUM_STATS          4
+
+/* macros that allow atomic increment or decrements for shared variables.
+ * In environments that do not make use of ENTER_CRIT_SECTION () and 
+ * EXIT_CRIT_SECTION () macros, these operations are protected via the
+ * LOCK_NET_RESOURCE () and UNLOCK_NET_RESOURCE () macros.  See pktalloc.c
+ * for more details.
+ */
+#define INCR_SHARED_VAR(x,y,incr) {ENTER_CRIT_SECTION(&(x)); (x [y]) += (incr); EXIT_CRIT_SECTION(&(x));}
+#define DECR_SHARED_VAR(x,incr)   {ENTER_CRIT_SECTION(&(x)); (x) -= (incr); EXIT_CRIT_SECTION(&(x));}
+
+/* count & sizes for the fre buffer queues */
+extern   unsigned lilbufs;    /* number of small bufs to init */
+extern   unsigned lilbufsiz;  /* big enough for average packet */
+extern   unsigned bigbufs;    /* number of big bufs to init */
+extern   unsigned bigbufsiz;  /* big enough for max. ethernet packet */
+
+/* Pack buffer routines, Defined in the new system for each port: */
+PACKET   pk_alloc(unsigned size);      /* allocate a packet for sending */
+void     pk_free(PACKET);
+int      pk_init(void);    /* call at init time to set up for pk_allocs */
+PACKET   pk_prepend(PACKET pkt, int bigger);    /* prepend new buffer */
+PACKET   pk_gather(PACKET pkt, int headerlen);  /* "gather" a buffer list */
+
+#endif   /*  _NETBUF_H */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nios2/ipport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nios2/ipport.h
new file mode 100644
index 0000000..cc3e604
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nios2/ipport.h
@@ -0,0 +1,872 @@
+/*
+ * Filename: ipport.h (head)
+ *
+ * Copyright 2007 InterNiche Technologies. All rights reserved.
+ *
+ * All the platform specific defines for each port go here.
+ * All these should be re-examined with each new port of the code.
+ *
+ * This file for:
+ *   ALTERA Cyclone and Stratix Dev boards with the ALTERA Nios2 Core
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 (or later) as distributed by Altera/NIOS2
+ *
+ * 06/21/2004  Created.
+ * 12/20/2007  Split into head and tail sections.
+ */
+
+#ifndef _IPPORT_H_
+#define _IPPORT_H_ 1
+
+   /* This is a workaround for GCC newlib upgrade to 1.18 and beyond. 
+    * This is due to GCC newlib 1.18 and beyond choosen some of the error codes
+    * to be linux-specific but still used in UCOSII Interniche drivers
+    */
+#ifndef __LINUX_ERRNO_EXTENSIONS__
+#define __LINUX_ERRNO_EXTENSIONS__
+#endif
+
+ /*
+  * Altera Niche Stack Nios port modification:
+  * Note about "NOT_USED" nomenclature: Code within #ifdef NOT_USED
+  * is presented for illustrative purposes. Options within a NOT_USED
+  * block that you wish to enable should be moved out of the NOT_USED
+  * block and then allowed to build.
+  *
+  * Note that the Niche Stack source code makes extensive use of #ifdef
+  * rather than #if. Thus, to disable an option, move it into one of the
+  * NOT_USED blocks, rather than changing its assigned value to 0.
+  */
+#ifdef NOT_USED
+#error "NOT_USED" should not be defined
+ /* Code within these blocks will not be compiled; use to disable options! */
+#endif /* NOT_USED */
+
+/* TTYIO.C has redefintions of printf, sprintf. So to resolve declarations,
+ * we don't include stdio.h for compiling this file
+ */
+#ifndef _IN_TTYIO_
+#include <stdio.h>   /* C compiler files */
+#endif
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include "system.h"
+
+/*
+ * Altera Niche Stack Nios port modifcation:
+ * _POSIX_SOURCE not defined; newlib types.h contains u_int typedef.
+ * The following prevents nptypes.h from re-defining u_int.
+ */
+#define UINT_ALREADY
+#include "nptypes.h"   /* NicheStack data types */
+
+/* Options to trade off features for size. Do not enable options 
+ * for modules you don't have or your link will get unresolved 
+ * externals.
+ */
+
+/**** Nios MicroC/OS-II Configuration **************************************/
+#define UCOS_II         1  /* Build with uCOS-II RTOS (ver 2.76) */
+#define NPDEBUG         1  /* turn on debugging dprintf()s */
+
+#ifdef NOT_USED
+#define MINI_IP         1  /* NicheLite API */
+#endif /* NOT_USED */
+
+#ifdef OS_TICKS_PER_SEC
+    #define TPS            OS_TICKS_PER_SEC  /* cticks per second */
+#else
+#define TPS            20  /* cticks per second */
+#endif
+
+#ifdef NOT_USED
+/*
+ * Altera Niche Stack Nios port modifcation:
+ * Do not build with USE_SMSC91X; Altera's alt_iniche_dev facility,
+ * if used with device drivers for Ethernet interfaces supporting
+ * Niche Stack, will register initialization routines for each MAC.
+ * These are called sequentially at Niche Stack startup
+ */
+#define USE_SMSC91X     1  /* Build with SMSC LAN 91C111 Drivers */
+#endif /* NOT_USED */
+
+#define ALTERA_NIOS2    1  /* Build for the Altera NIOS 2 Cyclone Dev Board */
+#define ALT_INICHE      1  /* Altera build */
+
+#ifdef NOT_USED
+/*
+ * Altera Niche Stack Nios port modifcation:
+ * LED/LCD support is design specific. The underlying routines
+ * need to be mapped to talk to a device specific to the hardware
+ * design Nios is running on. Interniche LCD/LED support will not
+ * function unless these are modifed to support your specific design.
+ */
+#define USE_LCD         0  /* support LCD and LEDs */
+#endif /* NOT_USED */
+
+#define NO_INICHE_EXTENSIONS   1   /* NO Interniche Extensions to uC/OS-II */
+#define CHRONOS         1  /* Define CHRONOS Macro to hook into uCOS-II RTOS */
+#define OS_PREEMPTIVE   1  /* it's a preemptive OS */ 
+#define _SDS_CC_        1
+
+
+/* definitions for the BSD TCP code */
+#define LITTLE_ENDIAN 1234
+#define BIG_ENDIAN    4321
+#define BYTE_ORDER    LITTLE_ENDIAN
+ 
+#define STK_TOPDOWN     1  /* Stacks grow "top down" */
+#define ALIGN_TYPE   4  /* 32 bit alignment */
+
+/* define Ethernet header size and offset */
+#define ETHHDR_SIZE  (16)
+#define ETHHDR_BIAS  (2)
+
+/* Compiler idiosyncracies */
+
+/*
+ * define away 16-bit x86 hooks
+ */
+#define CONST        const
+
+#ifndef FAR
+#define FAR
+#endif
+
+#define far
+
+#ifndef HUGE
+#define HUGE
+#endif
+
+#define SOCKERRORS_ALREADY    1  /* uC/OS-II defines common errno() errors */
+
+#define NO_TIME_T       1     /* use definitions in time.h */
+
+
+/**** NicheStack Options **************************************************/
+
+/*
+ * Altera Niche Stack Nios port modifcation:
+ * The following settings which are commented with "defined in system.h"
+ * are generated based on a Nios II IDE (classic build flow) system library
+ * settings, or BSP build flow BSP settings, into the system.h file.
+ */
+#ifdef ALT_INICHE
+#include "system.h"
+
+#ifdef NOT_USED
+#define DHCP_CLIENT   1   /* include DHCP client code */
+#define TCP_ZEROCOPY   1   /* use Sockets zero-copy extensions */
+#define IP_FRAGMENTS   1   /* IP fragment reassembly */
+#define INCLUDE_TCP   1   /* this link will include NetPort TCP w/MIB */
+#define NET_STATS   1   /* include statistics printfs */
+#endif /* NOT_USED */
+#endif /* ALT_INICHE */
+
+#define INCLUDE_ARP   1   /* use Ethernet ARP */
+#define FULL_ICMP   1   /* use all ICMP || ping only */
+#define MULTI_HOMED   1   /* more than one net interface */
+#define BSD_SOCKETS     1  /* use BSD sockets API */
+#define NB_CONNECT   1   /* support Non-Blocking connects (TCP, PPP, et al) */
+#define IP_ROUTING   1   /* do real IP routing, not imbedded agent fake route */
+#define IP_RAW   1   /* build raw sockets support */
+#define IP_MULTICAST   1   /* support IP multicast capability in stack */
+#define BLOCKING_APPS   1   /* applications block rather than poll */
+
+/* Options which are disabled by default */
+#ifdef NOT_USED
+
+#define DNS_CLIENT   1   /* include DNS client code */
+#define BOOTPTAB   1   /* DHCP supports a UNIX-ish bootptab file */
+#define BTREE_ROUTES   1   /* Use binary tree IP route lookup */
+#define NO_UDP_CKSUM   1   /* omit code for UDP checksums */
+#define TCP_ECHOTEST   1   /* include a TCP Echo test */
+#define TCP_SACK   1   /* Selective ACK per rfc2018 */
+#define TCP_TIMESTAMP      
+#define TCP_WIN_SCALE      
+#define DNS_CLIENT_UPDT   1   /* Dynamic DNS client */
+#define DO_DELAY_ACKS   1   /* TCP ACK piggybacking */
+#define DYNAMIC_IFACES   1   /* Support runtime creation of interfaces */
+#define IEEE_802_3   1   /* Support IEEE 802.3 (RFC-1042) */
+#define IP_PMTU   1   /* path MTU discovery */
+#define IP_RAW_ACCESS   1   /* allow direct-receive of IP datagrams */
+#define LOSSY_IO   1   /* Do lossy packet IO for testing */
+#define RAWIPTEST   1   /* Test for raw sockets */
+#define ROUTE_TEST   1   /* Add menu & pseudo device for route metrics */
+#define SHARED_IPADDRS   1   /* Add code for one IP address on two ifaces */
+#define SUPPORT_SO_FULLMSS   1   /* Socket option for MAXS sized tcp segments */
+#define UDP_ECHO_SVR   1   /* built-in UDP Echo server */
+#define UDPSTEST   1   /* UDP Echo Sockets test app */
+#define USE_IPFILTER   1   /* IP Filtering (RFC-2669) */
+#define USE_SLIP   1   /* support SLIP driver iface(s) */
+#define HEAPBUFS        1     /* support heap-based buffers */
+#define HEAPBUFS_DEBUG  1     /* debug support for heapbufs */
+
+#endif /* NOT_USED */
+
+
+#ifdef IP_FRAGMENTS
+#define MAX_FRAG_PKTS      5  /* max IP pkts we can simultaneously reassemble */
+#endif /* IP_FRAGMENTS */
+
+#ifdef DNS_CLIENT
+#define MAXDNSSERVERS      3  /* max # of DNS servers to look at */
+#endif   /* DNS_CLIENT */
+
+#ifdef IP_MULTICAST
+#define ETHMCAST           1   /* convert MAC addr to multicast MAC addr */
+#define IGMP_V1            1   /* include IGMPv1 */
+#define IGMP_V2            1   /* include IGMPv2 */
+#define IP_MULTI_UMCTEST   1   /* include IP multicast test function */
+#endif
+
+
+/**** AllPorts Options *********************************************************/
+#define INICHE_TIMERS   1   /* Provide Interval timers */
+
+#ifdef NOT_USED
+
+#define TK_STDIN_DEVICE   1   /* Include stdin (uart) console code */
+
+#endif /* NOT_USED */
+
+
+/**** MiscLib Options *********************************************************/
+
+
+#ifdef NOT_USED
+#define IN_MENUS   1   /* support for InterNiche menu system */
+#define PING_APP   1   /* application provides a pingUpcall */
+#define INCLUDE_NVPARMS   1   /* non-volatile (NV) parameters logic */
+#define MEM_BLOCKS   1   /* old memory debug system */
+#define MEM_WRAPPERS   1   /* include debug wrappers on heap calls */
+#define PKT_CYCLES   1   /* Include Code to measure Packet Cycles */
+#define HEAP_STATS   1   /* include the heap statistics menu */
+#define PFDEBUG   1   /* Enable profiler debug code */
+#define RF_SIMULATION   1   /* simulate wireless networks */
+#define TESTMENU   1   /* Include special tests in menu */
+#define PING_REQ_OUTDEV 1 /* PING stops if console/socket unavailable */
+
+#endif /* NOT_USED */
+
+
+
+/**** "net" Options *********************************************************/
+
+#ifdef NOT_USED
+
+#define LOCKNET_CHECKING   1   /* Check protection of net resources */
+#define MAC_LOOPBACK   1   /* use MAC layer pseudo-Ethernet loopback driver */
+#define QUEUE_CHECKING   1   /* include code to check critical queues */
+
+#endif /* NOT_USED */
+
+
+
+/**** AutoIP Options *********************************************************/
+
+
+#ifdef NOT_USED
+
+#define USE_UPNP   1   /* Universal Plug & Pray */
+#define USE_AUTOIP   1   /* Automatic IPv4 address aquisition */
+
+#endif /* NOT_USED */
+
+
+
+/**** FTP Options *********************************************************/
+
+
+#ifdef NOT_USED
+
+#define FTP_SERVER         1  /* include FTP server code */
+#define FTP_CLIENT         1  /* include FTP client code */
+#define DRIVE_LETTERS    1
+#define FTP_IDLECONN_TMO 1
+
+#endif /* NOT_USED */
+
+#define MAXSENDLOOPS      50  /* MAX number of FTP server send loops */
+
+
+/**** Syslog Options ******************************************************/
+
+#ifdef NOT_USED
+
+#define INICHE_SYSLOG    1  /* support syslog client */
+#define USE_SYSLOG_QUEUE 1  /* use queue for syslogs */
+#define USE_SYSLOG_TASK  1  /* use task (not timer) for syslogs */
+
+#endif /* NOT_USED */
+
+
+/**** Telnet Options *********************************************************/
+
+#ifdef NOT_USED
+
+#define TELNET_SVR       1 /* then include this source file */
+
+#endif /* NOT_USED */
+
+
+
+
+/**** TFTP Options *********************************************************/
+
+#ifdef NOT_USED
+
+#define TFTP_CLIENT   1   /* include TFTP client code */
+#define TFTP_SERVER   1   /* include TFTP server code */
+
+#endif /* NOT_USED */
+
+
+
+/**** VFS Options *********************************************************/
+#define VFS_FILES          1  /* include Virtual File System */
+#define USE_MEMDEV         1  /* Psuedo VFS files mem and null */
+
+#ifdef NOT_USED
+
+#define VFS_UNITTEST       1  /* Include in VFS test menu */
+#define VFS_VERBOSE        1  /* Compile VFS in verbose debug mode */
+
+#endif /* NOT_USED */
+
+
+/**** Nios MicroC/OS-II Options ********************************************/
+
+#define PRINTF_STDARG      1  /* C compiler supports VARARGS */
+#define NATIVE_PRINTF      1  /* use target's printf() function */
+#define NO_CC_PACKING      1  /* C compiler can't pack structs */
+
+#ifdef NOT_USED
+#define C_CHECKSUM      1     /* C checksum function only */
+#endif /* NOT_USED */
+
+#define DELAY_REPLY     1     /* process incoming packets in background loop */
+
+/* Options for setting the MicroC/OS-II priorities and stack sizes
+ * for the various tasks used by the stack 
+ */
+
+/* task stack sizes */
+#define  DEMO_STACK_SIZE      (4096+8192)
+
+#define  NETHEAP_SIZE         0x30000
+
+/* task stack sizes */
+#define  NET_STACK_SIZE       (4096+8192)
+#define  APP_STACK_SIZE       (6144+8192) /* 4096 */     /* default for applications */
+#define  CLOCK_STACK_SIZE     (4096+8192)
+
+#define  IO_STACK_SIZE        (2048+8192)
+#define  WEB_STACK_SIZE       (APP_STACK_SIZE+8192)
+#define  FTP_STACK_SIZE       APP_STACK_SIZE
+#define  PING_STACK_SIZE      (4096+8192)
+#define  TN_STACK_SIZE        APP_STACK_SIZE
+#define  TCP_ECHO_STACK_SIZE  APP_STACK_SIZE
+
+/* TK_NETMAIN and TK_NETTICK are always used by NicheStack */
+/* These priorities must be defined */
+
+/* Note: Niche stack now uses TK_NETMAIN_TPRIO-1 (priority 1) for an 
+ * internal mutex. If you wish to run application tasks at a higher priority
+ * than Niche stack, all Niche stack task priority assignments must be 
+ * adjusted down (to higher interger values).
+ */
+#define TK_NETMAIN_TPRIO 2
+#define TK_NETMAIN_SSIZE NET_STACK_SIZE
+#define TK_NETTICK_TPRIO 3
+#define TK_NETTICK_SSIZE CLOCK_STACK_SIZE
+
+#define TK_APP_TPRIO 4
+
+#define TK_ECHOTEST_TPRIO 5
+#define TK_ECHOTEST_SSIZE TCP_ECHO_STACK_SIZE
+#define TK_CIPHERTEST_TPRIO 5
+#define TK_CIPHERTEST_SSIZE APP_STACK_SIZE
+#define TK_BROWCHECK_TPRIO 5
+#define TK_BROWCHECK_SSIZE (APP_STACK_SIZE)*4
+#define TK_CUEXECUTION_TPRIO 5
+#define	TK_CUEXECUTION_SSIZE APP_STACK_SIZE
+#define TK_WEBPORT_TPRIO 5
+#define	TK_WEBPORT_SSIZE WEB_STACK_SIZE
+#define TK_FTPCLNT_TPRIO 5
+#define TK_FTPCLNT_SSIZE FTP_STACK_SIZE
+#define TK_EMAILER_TPRIO 5
+#define TK_EMAILER_SSIZE APP_STACK_SIZE
+#define TK_DNSSRV_TPRIO 5
+#define TK_DNSSRV_SSIZE APP_STACK_SIZE
+#define TK_IKE_TPRIO 5
+#define TK_IKE_SSIZE APP_STACK_SIZE
+#define TK_FTPSRVR_TPRIO 6
+#define TK_FTPSRVR_SSIZE FTP_STACK_SIZE
+#define TK_TELNETSRV_TPRIO 7
+#define TK_TELNETSRV_SSIZE APP_STACK_SIZE
+#define TK_SNMP_TPRIO 8
+#define TK_SNMP_SSIZE APP_STACK_SIZE
+#define TK_KEYBOARD_TPRIO 9
+#define TK_KEYBOARD_SSIZE IO_STACK_SIZE
+#define TK_PINGCHECK_TPRIO 20
+#define TK_PINGCHECK_SSIZE PING_STACK_SIZE
+#define TK_SNTPC_TPRIO 21
+#define TK_SNTPC_SSIZE APP_STACK_SIZE
+#define TK_SNTPS_TPRIO 22
+#define TK_SNTPS_SSIZE APP_STACK_SIZE
+#define TK_SYSLOG_TPRIO 23
+#define TK_SYSLOG_SSIZE APP_STACK_SIZE
+
+/* library definitions */
+
+/*   moved to libport.h_h */
+
+#ifdef NATIVE_PRINTF
+/*
+ * Use native printf from the C library for debug output.
+ */
+#define dprintf  printf
+#define dputchar putchar
+#else
+/*
+** Use UART driver for debug output
+*/
+#ifdef putchar
+#undef putchar
+#endif
+#define putchar dputchar
+#define printf  dprintf
+#ifndef _IN_TTYIO_
+void dprintf( char *, ... );
+#endif
+void dputchar( int );
+#endif
+
+/* Send startup errors to the right place */
+#define initmsg  dprintf
+
+/* net stats printf with redirectable device: */
+extern int ns_printf( void * pio, char * format, ... );
+
+/* file system definitions */
+
+#ifdef VFS_FILES
+#define HT_EXTDEV      1  /* allow custom file devices (memdev, null, etc.) */
+#define HT_RWVFS       1  /* support read/write VFS */
+#define VFS_STRIPPATH  1  /* used to strip path from filenames in vfsfiles.c */
+#define UNIX_VFS       1  /* make VFS look UNIX-like */
+
+#ifdef NOTDEF   /* unused VFS options */
+#define HT_SYNCDEV     1  /* support sync to flash device */
+#endif /* NOTDEF */
+
+/* define pesky macros away */
+#define vfs_lock()      wait_app_sem(VFS_SEMID)
+#define vfs_unlock()    post_app_sem(VFS_SEMID)
+#undef  ferror
+
+/* set up memory device size and offset */
+#ifdef USE_MEMDEV
+#define MEMDEV_BASE 0x00200000
+#define MEMDEV_SIZE 0x00200000
+#else
+#undef MEMDEV_BASE
+#undef MEMDEV_SIZE
+#endif
+
+#endif /* VFS_FILES */
+
+/* UART include file for mdmport.h */
+#define UART_INCLUDE "../../nios2/uart.h"
+
+extern unsigned long cticks;  /* clock ticks since startup */
+void clock_init(void);   /* start clock tick counting; called at init time */
+void clock_c(void);      /* undo clock_init (ie: restore ISR vector */
+
+#define CMPTIME(T,C)  (((T)<=(C)) && (((C)-(T))<(60*TPS)))
+#define HISTORY(T)    CMPTIME((T),cticks)
+
+
+/* convert little/big endian - these should be efficient, 
+ * inline code or MACROs
+ */
+#define lswap(x) (((((x) >> 24) & 0x000000ff)) | \
+		  ((((x) >>  8) & 0x0000ff00)) | \
+		  (((x) & 0x0000ff00) <<  8) | \
+		  (((x) & 0x000000ff) << 24))
+#define htonl(l) (lswap(l))
+#define ntohl(l) (lswap(l))
+#define htons(s) ((((s) >> 8) & 0xff) | \
+		  (((s) << 8) & 0xff00))
+#define ntohs(s) htons(s)
+
+
+/* Stack supports two methods of protecting its queues and data
+ * structs from destructive re-entries by ISRs, multiple tasks, etc. One
+ * is to lock a "resource ID" which makes code wait when trying to access
+ * a shared resource, the other is a CRITICAL SECTION frame. You should
+ * use one or the other, not both. See manual for details.
+ */
+
+#include "includes.h"
+#include "tk_crnos.h"
+
+#define USE_RESOURCE_LOCKS 1
+#define BLOCKING_APPS      1  /* applications block rather than poll */
+#define TCPWAKE_ALREADY    1  /* ChronOS has it's own tcp_sleep & tcp_wakeup */
+/* use the sleep/wakeup in misclib/netmain.c */
+/*#define TCPWAKE_RTOS    1*/
+
+void tcp_sleep(void * event);
+void tcp_wakeup(void * event);
+
+/*#define  GLOBWAKE_SZ     200*/
+
+#define OSPORT_H "../nios2/osport.h"
+
+/* resource locking definitions have been moved to h/tk_crnos.h */
+
+#define SYS_SHORT_SLEEP      1
+
+#define YIELD tk_yield
+
+extern char * pre_task_setup(void);
+extern char * post_task_setup(void);
+
+
+/* define the various IP stack block and buffer allocation routines */
+
+char *   npalloc(unsigned size);
+void     npfree(void * ptr);
+
+#define RT_ALLOC(size)     npalloc(size)  /* route block alloc */
+#define RT_FREE(ptr)       npfree(ptr)
+#define NB_ALLOC(size)     npalloc(size)  /* netbuf structure alloc */
+#define NB_FREE(ptr)       npfree(ptr)
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * The triple speed mac driver utilizes a scatter-gather DMA controller to
+ * transfer data between Ethernet MAC and Nios system memory. For Nios
+ * systems with data cache, all packet data structures must therfore be
+ * marked as uncached. The "nc" palloc/pfree routines wrap the default
+ * npalloc()/npfree() with Nios II library calls to mark the returned
+ * pointers as cache-bypassed.
+ */
+#ifdef ALTERA_TRIPLE_SPEED_MAC
+char * ncpalloc(unsigned size);
+void ncpfree(void *ptr);
+#define BB_ALLOC(size)     ncpalloc(size)  /* Big packet buffer alloc */
+#define BB_FREE(ptr)       ncpfree(ptr)
+#define LB_ALLOC(size)     ncpalloc(size)  /* Little packet buffer alloc */
+#define LB_FREE(ptr)       ncpfree(ptr)
+#else /* Not ALTERA_TRIPLE_SPEED_MAC */
+#define BB_ALLOC(size)     npalloc(size)  /* Big packet buffer alloc */
+#define BB_FREE(ptr)       npfree(ptr)
+#define LB_ALLOC(size)     npalloc(size)  /* Little packet buffer alloc */
+#define LB_FREE(ptr)       npfree(ptr)
+#endif /* ALTERA_TRIPLE_SPEED_MAC */
+
+#define UC_ALLOC(size)     npalloc(size)  /* UDP connection block alloc */
+#define UC_FREE(ptr)       npfree(ptr)
+#define TK_ALLOC(size)     npalloc(size)  /* task control block */
+#define TK_FREE(ptr)       npfree(ptr)
+#define STK_ALLOC(size)    npalloc(size)  /* task stack */
+#define STK_FREE(ptr)      npfree(ptr)
+#define PMTU_ALLOC(size)   npalloc(size)  /* path MTU cache */
+#define PMTU_FREE(ptr)     npfree(ptr)
+
+#ifdef DYNAMIC_IFACES
+#define NET_ALLOC(size)    npalloc(size)  /* struct net */
+#define NET_FREE(ptr)      npfree(ptr)
+#define IFM_ALLOC(size)    npalloc(size)  /* struct IfMib */
+#define IFM_FREE(ptr)      npfree(ptr)
+#endif   /* DYNAMIC_IFACES */
+
+#define IPR_ALLOC(size)    npalloc(size)  /* IP reassembly block allocation */
+#define IPR_FREE(ptr)      npfree(ptr)    /* IP reassembly block deallocation */
+#define HB_ALLOC(size)     npalloc(size)  /* allocate block (greater than bigbufsiz) from heap */
+#define HB_FREE(ptr)       npfree(ptr)    /* return block (greater than bigbufsiz) to heap */
+
+extern void dtrap( void );
+
+/*
+ * Structure packing is achieved using NO_CC_PACKING
+ */
+#define START_PACKED_STRUCT(sname)    struct sname {
+#define END_PACKED_STRUCT(sname)      };
+
+int   prep_ppp(int);    /* in ..\ppp\sys_np.c */
+int   prep_ifaces(int firstIface);   /* set up interfaces */
+
+/* 
+ * define number and sizes of free packet buffers 
+ */
+#define NUMBIGBUFS   30
+#define NUMLILBUFS   30
+
+/* some maximum packet buffer numbers */
+#define MAXBIGPKTS   30
+#define MAXLILPKTS   30
+#define MAXPACKETS (MAXLILPKTS+MAXBIGPKTS)
+
+
+/********************* ipport.h_h common ****************************/
+
+#ifndef TRUE
+#define TRUE            1
+#endif
+
+#ifndef FALSE
+#define FALSE           0
+#endif
+
+#ifndef NULL
+#define NULL            ((void*)0)
+#endif
+
+#define PRINTF_STDARG   1     /* C compiler supports VARARGS */
+
+/*
+ * Set sizes of large and small packet buffers
+ * The web server frequently uses packets of about 160 bytes, so
+ * increase the small packet size, rather than use large buffers.
+ */
+#ifndef BIGBUFSIZE
+#define BIGBUFSIZE      1536
+#endif
+#ifndef LILBUFSIZE
+#ifdef WEBPORT
+#define LILBUFSIZE      200
+#else
+#define LILBUFSIZE      128
+#endif
+#endif
+
+#define COMMSIZE        64    /* max bytes in community string */
+
+#define MAX_NVSTRING   128    /* MAX length of an nvparms string */
+
+/* A portable macro to check whether a ptr is within a certain range.
+ * In an environment where selectors are important, this macro will
+ * be altered to reflect that.
+ */
+ 
+#define IN_RANGE(p1, len1, p2) \
+   (((p1) <= (p2)) && (((p1) + (len1)) > (p2)))
+
+/*
+ * Use the new FD_xxx() implementation for socket select()
+ */
+#define USE_FDS            1  /* use Standard C FD_xxx() macros */
+ 
+
+/* NicheStack error codes: generally full success is 0,
+ * definite errors are negative numbers, and indeterminate conditions
+ * are positive numbers. These may be changed if they conflict with
+ * defines in the target system. They apply to the all NicheStack
+ * modules. If you have to change these values, be sure to recompile
+ * ALL NicheStack sources.
+ */
+
+#define SUCCESS          0 /* whatever the call was, it worked */
+
+/* programming errors */
+#define ENP_PARAM      -10 /* bad parameter */
+#define ENP_LOGIC      -11 /* sequence of events that shouldn't happen */
+#define ENP_NOCIPHER   -12 /* No corresponding cipher found for the cipher id */
+
+/* system errors */
+#define ENP_NOMEM      -20 /* malloc or calloc failed */
+#define ENP_NOBUFFER   -21 /* ran out of free packets */
+#define ENP_RESOURCE   -22 /* ran out of other queue-able resource */
+#define SEND_DROPPED   ENP_RESOURCE /* full queue or similar lack of resource */
+#define ENP_BAD_STATE  -23 /* TCP layer error */
+#define ENP_TIMEOUT    -24 /* TCP layer error */
+
+#define ENP_NOFILE     -25 /* expected file was missing */
+#define ENP_FILEIO     -26 /* file IO error */
+
+/* net errors */
+#define ENP_SENDERR    -30 /* send to net failed at low layer */
+#define ENP_NOARPREP   -31 /* no ARP for a given host */
+#define ENP_BAD_HEADER -32 /* bad header at upper layer (for upcalls) */
+#define ENP_NO_ROUTE   -33 /* can't find a reasonable next IP hop */
+#define ENP_NO_IFACE   -34 /* can't find a reasonable interface */
+#define ENP_HARDWARE   -35 /* detected hardware failure */
+
+/* conditions that are not really fatal OR success: */
+#define ENP_SEND_PENDING 1 /* packet queued pending an ARP reply */
+#define ENP_NOT_MINE     2 /* packet was not of interest (upcall reply) */
+#define EHAVEOOB       217 /* out-of-band */
+#define EIEIO          227 /* bad input/output on socket */
+
+/* ARP holding packet while awaiting a response from fhost */
+#define ARP_WAITING    ENP_SEND_PENDING
+
+
+/* #define PID port resource IDs */
+#define NET_RESID         0     /* stack code resource lock */
+#define RXQ_RESID         1     /* received packet queue resource lock */
+#define FREEQ_RESID       2     /* free packet queue resource lock */
+#define CE_RESID          3     /* crypto-engine resource lock */
+#define PINGQ_RESID       4     /* PING client task's message queue lock */
+#define FTPCQ_RESID       5     /* FTP  client task's message queue lock */
+#define SNTPv4C_RESID     6     /* SNTP */
+#define RTP_RESID         7
+#define RTPQ_RESID        8
+#define RTSPQ_RESID       9
+#define RTPANNOUN_RESID   10
+#define RTPQHAR_RESID     11
+#define WIN_RESID         12
+#define RESID_NET         13
+#define RESID_FREEQ       14
+#define RESID_RCVDQ       15
+
+#define MAX_RESID         15
+
+/* application semaphore identifiers */
+#define PING_SEMID   1        /* PING client task */
+#define FTPC_SEMID   2        /* FTP client task */
+#define TFTP_SEMID   3
+#define RTP_SEMID    4
+#define VFS_SEMID    5
+
+#define MAX_SEMID    5
+ 
+/* Functions invoked to wait for or signal the occurence of events significant
+ * to the PING client and the FTP client tasks.
+ */
+void wait_app_sem (unsigned long int semid);
+void post_app_sem (unsigned long int semid);
+
+
+/* Global variables */
+
+extern int iniche_net_ready;
+
+unsigned short cksum(void *, unsigned);
+
+/* macros to get rid of "unused argument" warnings. With compilers that
+ * can suppress these warnings, define this to nothing.
+ */
+#define MUTE_WARNS         1  /* gen extra code to suppress compiler warnings */
+
+#define USE_ARG(x)            { x = x; }
+#define USE_VOID(x)           { x = x; }
+
+/* default setups of some sub-options */
+
+/* if any SNMP agent is used, then INCLUDE_SNMP should be enabled */
+#if (defined(INCLUDE_SNMPV1)||defined(INCLUDE_SNMPV2C)||defined(INCLUDE_SNMPV3))
+#define INCLUDE_SNMP    1  /* update SNMP counters in TCPIP stack */
+#endif
+
+#ifdef INCLUDE_SNMP
+#if !defined(PREBIND_AGENT) && !defined(SNMP_SOCKETS)
+#define PREBIND_AGENT   1   /* hardcode SNMP port into UDP */
+#endif
+#endif
+
+/*
+ * Altera Niche Stack Nios port modifcation:
+ * Add friendly pre-processor error check, to prevent
+ * cryptic link error
+ */
+#if (!defined(NET_STATS) && defined(IN_MENUS))
+#error NET_STATS must be defined for IN_MENUS
+#endif
+
+#if (!defined(USE_CRYPTOENG) && defined(TCP_CIPHERTEST))
+#error TCP_CIPHERTEST should not be defined if USE_CRYPTOENG is not used
+#endif
+
+#if defined(INCLUDE_SSLAPP) && !defined(ENABLE_SSL)
+#error ENABLE_SSL must be defined for INCLUDE_SSLAPP
+#endif
+
+#if defined(MINI_IP) && defined(HEAPBUFS)
+#error HEAPBUFS are not available in MINI_IP
+#endif
+
+#ifdef LB_XOVER
+#ifndef MULTI_HOMED
+#define MULTI_HOMED 1
+#endif
+#endif
+
+#ifdef MULTI_HOMED
+#ifndef IP_ROUTING
+#define IP_ROUTING 1    /* force IP routing on multi-homed compiles */
+#endif
+#endif
+
+#ifdef INCLUDE_TCP
+#ifndef FULL_ICMP
+#define FULL_ICMP 1     /* force full ICMP for TCP support */
+#endif
+#endif
+
+#ifdef MULTI_HOMED
+#define STATIC_NETS   4  /* static network interfaces to allow for... */  
+#else
+#define STATIC_NETS   1
+#endif
+
+#ifdef DYNAMIC_IFACES
+#define MAXNETS       8  /* max ifaces to support at one time */
+#else
+#define MAXNETS       STATIC_NETS
+#endif
+
+/* number of entries in IP routing table */
+#define RT_TABS      16
+
+#ifdef IP_FRAGMENTS
+#ifndef MAX_FRAG_PKTS
+#define MAX_FRAG_PKTS 5 /* max IP pkts we can simultaneously reassemble */
+#endif
+#endif
+
+#ifndef ALTERA_NIOS2
+#if defined(IN_MENUS) && defined(NATIVE_PRINTF)
+#error IN_MENUS do not work with NATIVE_PRINTF.
+#endif
+#endif
+
+
+/*
+ * temporary workaround for files which do not include libport.h
+ */
+#ifndef _LIBPORT_H_
+#include "libport.h"
+#endif
+
+/********************* ipport.h_h common ****************************/
+
+/*
+ * Altera Niche Stack Nios port modifications:
+ * - Prototypes to remove build warning.
+ */
+void evtmap_setup(void);
+u_char TK_OSTaskQuery(void);
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Provide delcaration of timeval struct used in Altera software examples
+ */
+#ifdef ALT_INICHE
+#include <unistd.h>
+#include <sys/time.h>
+#define BSD_TIMEVAL_T struct timeval
+#endif /* ALT_INICHE */
+
+#endif  /* _IPPORT_H_ */
+
+
+/**** ipport.h_h generated Tue, 22 Jan 2008 15:09:35 -0800 ****/
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nptcp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nptcp.h
new file mode 100644
index 0000000..3158f2a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nptcp.h
@@ -0,0 +1,348 @@
+/*
+ * FILENAME: nptcp.h
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * File to MAP TCP's Berserkly-isms into NetPort/InterNiche IP Stack.
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. All rights reserved. */
+
+
+#ifndef NPTCP_H
+#define  NPTCP_H
+
+#ifdef MINI_IP
+#error This file not for Mini-IP use
+#endif   /* MINI_IP */
+
+#ifndef _IPPORT_H_
+#error Include ipport.h before this file
+#endif   /* missing IPPORT_H */
+
+#define  NPPORT      1     /* flag for NetPort tcp port (not UNIX) */
+
+extern   NET iproute(ip_addr, ip_addr*);  /* prototype netport routing */
+
+
+
+/*
+ * NetPort IP routine to get this machine's IP address relative to a 
+ * destination IP address.
+ */
+extern   u_long ip_mymach(u_long ipaddr);
+
+/* flag for NetPort port */
+#define  NPPORT   1
+
+/* pretend we are a UNIX kernel */
+#define  KERNEL      1
+#define  INET_KERNEL    1
+
+/* Strange but true: just listing these here cuts 
+ * out some compile time warnings with some compilers:
+ */
+struct ip;   
+struct mbuf;
+struct uio;
+
+void  tcp_sleep(void * timeout);
+void  tcp_wakeup(void * wake);
+void  np_stripoptions(struct ip * ti, struct mbuf * m);
+int   in_broadcast(u_long ipaddr);     /* TRUE if ipaddr is broadcast */
+
+unshort  tcp_cksum(struct ip * pip);
+
+
+#ifdef TCP_ZEROCOPY  /* zero-copy sockets extensions */
+struct socket;
+void     tcp_data_upcall(struct socket *);   /* internal (invoke upcall) */
+int      tcp_xout(long s, PACKET pkt);       /* send */
+PACKET   tcp_pktalloc(int datasize);         /* get send buffer */
+void     tcp_pktfree(PACKET p);
+#endif
+
+/* Berkeley style "Internet address" */
+
+struct in_addr
+{
+   unsigned long  s_addr;
+};
+
+#define  INADDR_ANY     0L
+
+
+/* Berkeley style "Socket address" */
+
+struct sockaddr_in
+{
+   short    sin_family;
+   u_short  sin_port;
+   struct   in_addr  sin_addr;
+   char     sin_zero[8];
+};
+
+struct socket; /* predeclaration */
+
+/* BSD sockets errors */
+
+#ifndef SOCKERRORS_ALREADY    /* allow 3rd party override */
+
+#ifdef MCF5235_PLATFORM
+#define	EPERM 1		/* Not super-user */
+#define	ENOENT 2	/* No such file or directory */
+#define	ESRCH 3		/* No such process */
+#define	EINTR 4		/* Interrupted system call */
+#define	EIO 5		/* I/O error */
+#define	ENXIO 6		/* No such device or address */
+#define	E2BIG 7		/* Arg list too long */
+#define	ENOEXEC 8	/* Exec format error */
+#define	EBADF 9		/* Bad file number */
+#define	ECHILD 10	/* No children */
+#define	EAGAIN 11	/* No more processes */
+#define	ENOMEM 12	/* Not enough core */
+#define	EACCES 13	/* Permission denied */
+#define	EFAULT 14	/* Bad address */
+#define	ENOTBLK 15	/* Block device required */
+#define	EBUSY 16	/* Mount device busy */
+#define	EEXIST 17	/* File exists */
+#define	EXDEV 18	/* Cross-device link */
+#define	ENODEV 19	/* No such device */
+#define	ENOTDIR 20	/* Not a directory */
+#define	EISDIR 21	/* Is a directory */
+#define	EINVAL 22	/* Invalid argument */
+#define	ENFILE 23	/* Too many open files in system */
+#define	EMFILE 24	/* Too many open files */
+#define	ENOTTY 25	/* Not a typewriter */
+#define	ETXTBSY 26	/* Text file busy */
+#define	EFBIG 27	/* File too large */
+#define	ENOSPC 28	/* No space left on device */
+#define	ESPIPE 29	/* Illegal seek */
+#define	EROFS 30	/* Read only file system */
+#define	EMLINK 31	/* Too many links */
+#define	EPIPE 32	/* Broken pipe */
+#define	EDOM 33		/* Math arg out of domain of func */
+#define	ERANGE 34	/* Math result not representable */
+#define	ENOMSG 35	/* No message of desired type */
+#define	EIDRM 36	/* Identifier removed */
+#define	ECHRNG 37	/* Channel number out of range */
+#define	EL2NSYNC 38	/* Level 2 not synchronized */
+#define	EL3HLT 39	/* Level 3 halted */
+#define	EL3RST 40	/* Level 3 reset */
+#define	ELNRNG 41	/* Link number out of range */
+#define	EUNATCH 42	/* Protocol driver not attached */
+#define	ENOCSI 43	/* No CSI structure available */
+#define	EL2HLT 44	/* Level 2 halted */
+#define	EDEADLK 45	/* Deadlock condition */
+#define	ENOLCK 46	/* No record locks available */
+#define EBADE 50	/* Invalid exchange */
+#define EBADR 51	/* Invalid request descriptor */
+#define EXFULL 52	/* Exchange full */
+#define ENOANO 53	/* No anode */
+#define EBADRQC 54	/* Invalid request code */
+#define EBADSLT 55	/* Invalid slot */
+#define EDEADLOCK 56	/* File locking deadlock error */
+#define EBFONT 57	/* Bad font file fmt */
+#define ENOSTR 60	/* Device not a stream */
+#define ENODATA 61	/* No data (for no delay io) */
+#define ETIME 62	/* Timer expired */
+#define ENOSR 63	/* Out of streams resources */
+#define ENONET 64	/* Machine is not on the network */
+#define ENOPKG 65	/* Package not installed */
+#define EREMOTE 66	/* The object is remote */
+#define ENOLINK 67	/* The link has been severed */
+#define EADV 68		/* Advertise error */
+#define ESRMNT 69	/* Srmount error */
+#define	ECOMM 70	/* Communication error on send */
+#define EPROTO 71	/* Protocol error */
+#define	EMULTIHOP 74	/* Multihop attempted */
+#define	ELBIN 75	/* Inode is remote (not really error) */
+#define	EDOTDOT 76	/* Cross mount point (not really error) */
+#define EBADMSG 77	/* Trying to read unreadable message */
+#define EFTYPE 79	/* Inappropriate file type or format */
+#define ENOTUNIQ 80	/* Given log. name not unique */
+#define EBADFD 81	/* f.d. invalid for this operation */
+#define EREMCHG 82	/* Remote address changed */
+#define ELIBACC 83	/* Can't access a needed shared lib */
+#define ELIBBAD 84	/* Accessing a corrupted shared lib */
+#define ELIBSCN 85	/* .lib section in a.out corrupted */
+#define ELIBMAX 86	/* Attempting to link in too many libs */
+#define ELIBEXEC 87	/* Attempting to exec a shared library */
+#define ENOSYS 88	/* Function not implemented */
+#define ENMFILE 89      /* No more files */
+#define ENOTEMPTY 90	/* Directory not empty */
+#define ENAMETOOLONG 91	/* File or path name too long */
+#define ELOOP 92	/* Too many symbolic links */
+#define EOPNOTSUPP 95	/* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define ECONNRESET 104  /* Connection reset by peer */
+#define ENOBUFS 105	/* No buffer space available */
+#define EAFNOSUPPORT 106 /* Address family not supported by protocol family */
+#define EPROTOTYPE 107	/* Protocol wrong type for socket */
+#define ENOTSOCK 108	/* Socket operation on non-socket */
+#define ENOPROTOOPT 109	/* Protocol not available */
+#define ESHUTDOWN 110	/* Can't send after socket shutdown */
+#define ECONNREFUSED 111	/* Connection refused */
+#define EADDRINUSE 112		/* Address already in use */
+#define ECONNABORTED 113	/* Connection aborted */
+#define ENETUNREACH 114		/* Network is unreachable */
+#define ENETDOWN 115		/* Network interface is not configured */
+#define ETIMEDOUT 116		/* Connection timed out */
+#define EHOSTDOWN 117		/* Host is down */
+#define EHOSTUNREACH 118	/* Host is unreachable */
+#define EINPROGRESS 119		/* Connection already in progress */
+#define EALREADY 120		/* Socket already connected */
+#define EDESTADDRREQ 121	/* Destination address required */
+#define EMSGSIZE 122		/* Message too long */
+#define EPROTONOSUPPORT 123	/* Unknown protocol */
+#define ESOCKTNOSUPPORT 124	/* Socket type not supported */
+#define EADDRNOTAVAIL 125	/* Address not available */
+#define ENETRESET 126
+#define EISCONN 127		/* Socket is already connected */
+#define ENOTCONN 128		/* Socket is not connected */
+#define ETOOMANYREFS 129
+#define EPROCLIM 130
+#define EUSERS 131
+#define EDQUOT 132
+#define ESTALE 133
+#define ENOTSUP 134		/* Not supported */
+#define ENOMEDIUM 135   /* No medium (in tape drive) */
+#define ENOSHARE 136    /* No such host or network path */
+#define ECASECLASH 137  /* Filename exists with different case */
+#define EILSEQ 138
+#define EOVERFLOW 139	/* Value too large for defined data type */
+
+/* From cygwin32.  */
+#define EWOULDBLOCK EAGAIN	/* Operation would block */
+#define __ELASTERROR 2000	/* Users can add values starting here */
+
+#define     EHAVEOOB       2001
+#define     EIEIO          2002 /* bad input/output on Old Macdonald's farm :-) */
+
+#else  /* not MCF5235_PLATFORM */
+
+#define     ENOBUFS        1
+#define     ETIMEDOUT      2
+#define     EISCONN        3
+#define     EOPNOTSUPP     4
+#define     ECONNABORTED   5
+#define     EWOULDBLOCK    6
+#define     ECONNREFUSED   7
+#define     ECONNRESET     8
+#define     ENOTCONN       9
+#define     EALREADY       10
+#define     EINVAL         11
+#define     EMSGSIZE       12
+#define     EPIPE          13
+#define     EDESTADDRREQ   14
+#define     ESHUTDOWN      15
+#define     ENOPROTOOPT    16
+#define     EHAVEOOB       17
+#define     ENOMEM         18
+#define     EADDRNOTAVAIL  19
+#define     EADDRINUSE     20
+#define     EAFNOSUPPORT   21
+#define     EINPROGRESS    22
+#define     ELOWER         23    /* lower layer (IP) error */
+#define     ENOTSOCK       24    /* Includes sockets which closed while blocked */
+#define     EIEIO 27 /* bad input/output on Old Macdonald's farm :-) */
+
+#ifdef   IP_MULTICAST
+#define     ETOOMANYREFS   28
+#endif   /* IP_MULTICAST */
+
+#define     EFAULT         29
+#define     ENETUNREACH    30
+#endif
+
+#endif   /* SOCKERRORS_ALREADY - end 3rd party override */
+
+#ifndef NLONG_ALREADY 
+typedef u_long n_long;
+#endif
+#ifndef NTIME_ALREADY 
+typedef u_long n_time;
+#endif
+#ifndef UINT_ALREADY 
+typedef u_long u_int;
+#endif
+
+
+#ifndef MIN
+#define  MIN(a,b)    (a>b?b:a)
+#define  MAX(a,b)    (a>b?a:b)
+#endif
+
+/* this can be used to supress arg checking on broken compilers */
+#ifndef __P
+#define  __P(x)   x
+#endif
+
+#define     IFNETHDR_SIZE     MaxLnh
+#define     MAXOPTLEN      256   /* size of alloc for TCP options */
+
+#define     PR_SLOWHZ   2  /* TCP ticks per second */
+#define     PR_FASTHZ   5  /* 5 fast timeouts per second */
+
+/* IPPROTO_... definitions, from BSD <netinet/in.h> */
+#define     IPPROTO_IP     0  /* added for IP multicasting changes */
+#define     IPPROTO_IGMP   2  /* added for IP multicasting changes */
+#define     IPPROTO_TCP    6
+#define     IPPROTO_UDP    17
+#define     IPPROTO_RAW    255
+
+#define     IPPORT_RESERVED      1024
+#define     IPPORT_USERRESERVED     5000  /* more BSDness */
+
+extern   struct inpcb * GetTcpcbList(void);
+
+/* keep the INET_TRACE feature for later, define away for now. -JB- */
+#define  INET_TRACE(flags, text);
+
+/* fake IP route structure */
+struct route
+{
+   unshort  unused;  /* placeholder */
+};
+
+/* ip send routine for TCP layers */
+extern   int   ip_output   __P ((struct mbuf *, struct   ip_socopts * so_optsPack));
+
+/* mbuf checksumming routine */
+extern   u_short  in_cksum __P ((struct mbuf *, int));
+
+
+#ifdef DO_TCPTRACE
+#define  SETTP(tp,action)  tp=(action)
+#else
+#define  SETTP(tp,action)  (action)
+#endif
+
+extern   unshort  select_wait;
+
+int      nptcp_init(void);       /* called from tcpinit(), calls tcp_init() */
+int      tcp_stat(void * pio);   /* printf TCP MIB statistics */
+int      mbuf_stat(void * pio);  /* printf mbuf pool statistics */
+int      sock_list(void * pio);  /* list existing sockets */
+void     tcp_tick(void);         /* TCP clock tick - for timers, etc */
+int      udp_usrreq(struct socket * so, struct mbuf * m, struct mbuf * nam);
+
+#ifdef IP_RAW
+int      rawip_usrreq(struct socket * so, struct mbuf * m, struct mbuf * nam);
+#endif /* IP_RAW */
+
+int      tcp_bsdconnstat(void * pio);  /* BSD-ish TCP connection stats */
+int      tcp_bsdsendstat(void * pio);  /* BSD-ish TCP send stats */
+int      tcp_bsdrcvstat (void * pio);  /* BSD-ish TCP receive stats */
+
+/* end of file nptcp.h */
+
+#endif   /* NPTCP_H */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nptypes.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nptypes.h
new file mode 100644
index 0000000..ec7abd1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nptypes.h
@@ -0,0 +1,80 @@
+/*
+ * FILENAME: nptypes.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1997 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon */
+/* Portions Copyright 1983 by the Massachusetts Institute of Technology  */
+
+
+#ifndef NPTYPES_H
+#define  NPTYPES_H   1
+
+
+typedef  unsigned short unshort;
+typedef  unsigned long ulong;
+
+
+/* now do it the way the CMU snmp code likes it: */
+typedef   unsigned char u_char;
+typedef   unsigned short u_short;
+typedef   unsigned long u_long;
+
+typedef  unsigned long ip_addr;
+
+
+#ifdef NOT_USED
+
+/* general stuff C code */
+#ifndef  TRUE
+#define  TRUE  -1
+#endif
+
+#ifndef  FALSE
+#define  FALSE    0
+#endif
+
+#ifndef  NULL
+#define  NULL  ((void*)0)
+#endif
+
+#endif   /* NOT_USED */
+
+
+/* usefull macros: */
+
+/* Altera Niche Stack Nios port modification:
+ * Keep these macros defined.
+ */
+#ifndef min
+#define  min(x,y)          ((x) <= (y) ? (x) : (y))
+#endif
+#ifndef max
+#define  max(x,y)          ((x) >= (y) ? (x) : (y))
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification;
+ * Provide routines to extract individual octets of 
+ * an IP address. This is used by Altera example software
+ */
+#ifdef ALT_INICHE
+#define ip4_addr1(ipaddr) ((unsigned int)(ntohl(ipaddr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((unsigned int)(ntohl(ipaddr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((unsigned int)(ntohl(ipaddr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((unsigned int)(ntohl(ipaddr)) & 0xff)
+#endif /* ALT_INICHE */
+
+#endif   /* NPTYPES_H */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ns.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ns.h
new file mode 100644
index 0000000..d7acd18
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ns.h
@@ -0,0 +1,374 @@
+/*
+ * FILENAME: ns.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: DNS
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define  NS_USE_SENDTO_FOR_CLIENT
+
+/* interniche port includes for all DNS source files */
+#include "ipport.h"
+#include "vfsfiles.h"
+#include "dnsport.h"
+
+
+#ifndef __P /* for ansi */
+#define  __P(args)   args
+#endif
+#define  bcmp  MEMCMP
+
+#ifndef bcopy
+#define  bcopy(src,dst,len)   MEMCPY   (dst,src,len)
+#define  bzero(buf,len)       MEMSET   (buf, 0, len)
+#endif   /* bcopy */
+
+#define  strcasecmp  stricmp
+#define  strncasecmp strnicmp
+
+#define gettime(tvp) {u_long x; x = sysuptime (); (tvp)->tv_sec = x/100l;\
+ (tvp)->tv_usec = x/10000l;}
+
+extern   unsigned long  sysuptime (void); /* From dosmain.c */
+
+struct in_addr;   /* predecl */
+extern   char *   inet_ntoa   __P ((struct in_addr));
+extern   unsigned long  inet_addr   __P ((char *));
+
+/*extern char *print_ipad (struct in_addr);*/
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * inet_ntoa defined to bsd sockets layer
+ */
+#if !(defined (ALT_INICHE) && defined (BSD_SOCKETS))
+#define  inet_ntoa(x)   print_ipad  (*(long *)&x)
+#endif
+
+#ifndef USE_WINSOCK
+#define  SOCKET   long
+#define  GET_SOCK_ERR(x)   t_errno  (x)
+#else
+#define  GET_SOCK_ERR(x)   WSAGetLastError   ()
+#endif
+
+#include "webport.h"
+#include "in_utils.h"
+#include "nameser.h"
+#include "ns_debug.h"
+
+
+/*
+ * Global definitions and variables for the name server.
+ */
+/*
+ * Timeout time should be around 1 minute or so.  Using the
+ * the current simplistic backoff strategy, the sequence
+ * retrys after 4, 8, and 16 seconds.  With 3 servers, this
+ * dies out in a little more than a minute.
+ * (sequence RETRYBASE, 2*RETRYBASE, 4*RETRYBASE... for MAXRETRY)
+ */
+#define  MINROOTS 2     /* min number of root hints */
+#define  NSMAX    16    /* max number of NS addrs to try */
+#define  RETRYBASE   4  /* base time between retries */
+#define  MAXRETRY 3     /* max number of retries per addr */
+#define  MAXCNAMES   8  /* max # of CNAMES tried per addr */
+#define  MAXQUERIES  20 /* max # of queries to be made */
+/* (prevent "recursive" loops) */
+#define  INIT_REFRESH   600   /* retry time for initial secondary */
+/* contact (10 minutes) */
+
+#ifdef INTERNICHE
+#define  allmem   npalloc
+#define  allcmem(n,sz)  npalloc(n*sz)
+#define freemem(x) {if ((x) == NULL) {printf ("Free-ing null\n");}\
+   else npfree(x);}
+#else /* Not Interniche */
+#define  allmem(sz)  getmem   (sz,  MTYPE_DNS)
+#define  allcmem(n,sz)  getcmem  (n*sz,   MTYPE_DNS)
+#endif
+
+#ifdef USE_FLOATING_POINT
+#define  ALPHA    0.7   /* How much to preserver of old response time */
+#define  BETA  1.2      /* How much to penalize response time on failure */
+#define  GAMMA    0.98  /* How much to decay unused response times */
+#else /* NO FLOAT */
+#define  ALPHA    70    /* How much to preserver of old response time */
+#define  BETA  120      /* How much to penalize response time on failure */
+#define  GAMMA    98    /* How much to decay unused response times */
+#endif   /* FLOAT */
+
+struct zoneinfo   {
+   int      z_type;        /* type of zone */
+   int      z_auth;        /* zone is authoritative */
+   char *   z_origin;      /* root domain name of zone */
+   time_t   z_time;        /* time for next refresh */
+   time_t   z_lastupdate;  /* time of last refresh */
+   u_long   z_refresh;     /* refresh interval */
+   u_long   z_retry;       /* refresh retry interval */
+   u_long   z_expire;      /* expiration time for cached info */
+   u_long   z_minimum;     /* minimum TTL value */
+   u_long   z_serial;      /* changes if zone modified */
+   char *   z_source;      /* source location of data */
+   time_t   z_ftime;       /* modification time of source file */
+   int      z_addrcnt;     /* address count */
+   struct in_addr z_addr[NSMAX]; /* list of master servers for zone */
+   int      z_state;       /* state bits; see below */
+   u_short  z_xferpid;     /* xfer child pid */
+#ifdef ALLOW_UPDATES
+   /* non-zero if zone has been updated
+    * since last checkpoint
+    */
+   int hasChanged;
+#endif   /*ALLOW_UPDATES*/
+};
+
+/* zone types (z_type) */
+#define  Z_PRIMARY   1
+#define  Z_SECONDARY 2
+#define  Z_CACHE  3
+
+/* zone state bits */
+#define  Z_AUTH   0x01        /* should replace z_auth */
+#define  Z_NEED_XFER 0x02     /* waiting to do xfer */
+#define  Z_XFER_RUNNING 0x04  /* asynch. xfer is running */
+#define  Z_NEED_RELOAD  0x08  /* waiting to do reload */
+#define  Z_SYSLOGGED 0x10     /* have logged timeout */
+#define  Z_CHANGED   0x20     /* should replace hasChanged */
+#define  Z_FOUND  0x40        /* found in boot file when reloading */
+#define  Z_INCLUDE   0x80     /* set if include used in file */
+#define  Z_DB_BAD 0x100       /* errors when loading file */
+#define  Z_TMP_FILE  0x200    /* backup file for xfer is temporary */
+#ifdef ALLOW_UPDATES
+#define  Z_DYNAMIC   0x400       /* allow dynamic updates */
+#define  Z_DYNADDONLY   0x800    /* dynamic mode: add new data only */
+#endif   /*ALLOW_UPDATES*/
+
+/* xfer exit codes */
+#define  XFER_UPTODATE  0  /* zone is up-to-date */
+#define  XFER_SUCCESS   1  /* performed transfer successfully */
+#define  XFER_TIMEOUT   2  /* no server reachable/xfer timeout */
+#define  XFER_FAIL   3     /* other failure, has been logged */
+
+/*
+ * Structure for recording info on forwarded queries.
+ */
+struct ns_qinfo   {
+     u_short  q_id;     /* id of query */
+     u_short  q_nsid;   /* id of forwarded query */
+#ifdef NS_USE_SENDTO_FOR_CLIENT
+     SOCKET   q_dfd;    /* UDP file descriptor */
+#endif
+     struct sockaddr_in   q_from;  /* requestor's address */
+     char *   q_msg;    /* the message */
+     int   q_msglen;    /* len of message */
+     int   q_naddr;     /* number of addr's in q_addr */
+     int   q_curaddr;   /* last addr sent to */
+     struct fwdinfo *  q_fwd;   /* last forwarder used */
+     time_t   q_time;   /* time to retry */
+     struct ns_qinfo * q_next;  /* rexmit list (sorted by time) */
+     struct ns_qinfo * q_link;  /* storage list (random order) */
+     struct  qserv  {
+       struct sockaddr_in   ns_addr; /* addresses of NS's */
+       struct  databuf * ns;        /* databuf for NS record */
+       struct  databuf * nsdata;    /* databuf for server address */
+       struct  timeval   stime;     /* time first query started */
+       int   nretry;                /* # of times addr retried */
+     }  q_addr   [NSMAX]; /* addresses of NS's */
+     struct databuf *  q_usedns[NSMAX];  /* databuf for NS that we've tried */
+     int   q_nusedns;
+     int   q_cname;        /* # of cnames found */
+     int   q_nqueries;     /* # of queries required */
+     char *   q_cmsg;      /* the cname message */
+     int   q_cmsglen;      /* len of cname message */
+     struct qstream *  q_stream;   /* TCP stream, null if UDP */
+     int   q_system;   /* boolean, system query */
+};
+
+#define Q_NEXTADDR(qp,n) \
+ (((qp)->q_fwd == (struct fwdinfo *)0) ? \
+  &(qp)->q_addr[n].ns_addr : &(qp)->q_fwd->fwdaddr)
+
+#define  PRIMING_CACHE  42
+#define  QINFO_NULL  ((struct ns_qinfo *)0)
+
+#ifndef XFER
+extern   struct ns_qinfo * qfindid(void);
+extern   struct ns_qinfo * qnew(void);
+extern   struct ns_qinfo * retryqp; /* next query to retry */
+#endif   /* XFER */
+
+/*
+ * Return codes from ns_forw:
+ */
+#define  FW_OK    0
+#define  FW_DUP   1
+#define  FW_NOSERVER 2
+#define  FW_SERVFAIL 3
+
+struct qstream {
+   SOCKET   s_rfd;            /* stream file descriptor */
+   int      s_size;           /* expected amount of data to recive */
+   int      s_bufsize;        /* amount of data recived in s_buf */
+   char *   s_buf;            /* buffer of recived data */
+   char *   s_bufp;           /* pointer into s_buf of recived data */
+   struct qstream *  s_next;  /* next stream */
+   struct sockaddr_in s_from; /* address query came from */
+   u_long   s_time;           /* time stamp of last transaction */
+   int      s_refcnt;         /* number of outstanding queries */
+   u_short  s_tempsize;       /* temporary for size from net */
+};
+
+#define  QSTREAM_NULL   ((struct qstream *)0)
+extern   struct qstream *  streamq; /* stream queue */
+
+struct qdatagram  {
+   SOCKET   dq_dfd;              /* datagram file descriptor */
+   struct qdatagram * dq_next;   /* next datagram */
+   struct in_addr    dq_addr;    /* address of interface */
+};
+
+#define  QDATAGRAM_NULL ((struct qdatagram *)0)
+extern   struct qdatagram *   datagramq;  /* datagram queue */
+
+struct netinfo {
+     struct netinfo *  next;
+     u_long   net;
+     u_long   mask;
+     struct in_addr my_addr;
+};
+
+struct fwdinfo {
+     struct fwdinfo *  next;
+     struct sockaddr_in   fwdaddr;
+};
+
+struct nets {
+     char *   name;
+     long  net;
+     struct nets *  next;
+}; 
+
+/*
+ *  Statistics Defines
+ */
+
+struct DnsStats  {
+   u_long dns_dupqueries;   /* Duplicate queries */
+   u_long dns_outpkts;      /* Outbound DNS packets */
+   u_long dns_queries;      /* DNS queries */
+   u_long dns_inv_queries;  /* DNS inverse queries */
+   u_long dns_respok;       /* Good DNS responses */
+   u_long dns_respfail;     /* DNS responses failures */
+   u_long dns_respfmterr;   /* DNS responses format errors */
+   u_long dns_responses;    /* DNS responses */
+   u_long dns_dupresp;      /* DNS dup responses */
+   u_long dns_badresponses; /* DNS bad responses from servers */
+   u_long dns_martians;     /* DNS responses from unexpected sources */
+   u_long dns_prime_cache;  /* DNS number of times cache primed */
+   u_long dns_sysqueries;   /* DNS number of sysqueries sent */
+   u_long dns_check_ns;     /* DNS number of check_ns calls */
+};
+
+extern struct DnsStats dns_stats;
+
+#ifdef DNS_STATS
+#define  STATS_INCR(ind)   dns_stats   [ind]++
+#else
+#define  STATS_INCR(ind)
+#endif
+
+/* gross count of UDP packets in and out */
+#define  S_INPKTS 0
+#define  S_OUTPKTS   1
+/* gross count of queries and inverse queries received */
+#define  S_QUERIES   2
+#define  S_IQUERIES  3
+#define  S_DUPQUERIES   4
+#define  S_RESPONSES 5
+#define  S_DUPRESP   6
+#define  S_RESPOK 7
+#define  S_RESPFAIL  8
+#define  S_RESPFORMERR  9
+#define  S_SYSQUERIES   10
+#define  S_PRIMECACHE   11
+#define  S_CHECKNS   12
+#define  S_BADRESPONSES 13
+#define  S_MARTIANS  14
+
+#define  S_NSTATS 15 /* Careful! */
+#ifdef DNS_STATS
+extern   struct stats   stats[S_NSTATS];
+extern   unsigned long  typestats[T_ANY+1];
+#endif
+
+
+
+#ifdef DEBUG
+extern   int   debug;   /* debug flag */
+extern   FILE *   ddt;  /* debug file discriptor */
+#endif
+#ifndef XFER
+extern   struct qdatagram *   dqp;
+
+extern   struct itimerval  ival;    /* maintenance interval */
+extern   struct zoneinfo * zones;   /* zone information */
+extern   int   nzones;              /* number of zones in use */
+
+extern   int   forward_only;  /* true on slave server */
+#endif   /* XFER */
+
+#define  MAX_XFER_TIME     60 *  60 *  2  /* max seconds for an xfer */
+#define  XFER_TIME_FUDGE   10             /* MAX_XFER_TIME fudge */
+
+#ifndef XFER
+extern   int   xfer_running_cnt;          /* number of xfers running */
+extern   int   xfer_deferred_cnt;         /* number of deferred xfers */
+#define  MAX_XFERS_RUNNING       4        /* max value of xfer_running_cnt */
+#endif   /* XFER */
+
+#define  dn_skipname __dn_skipname
+
+#ifndef FULL_DNS
+#define  net_islocal(x) (0)
+#endif
+
+#define  NS_ROOT_CACHE_FILE "../dnssrv/root.dns"
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ns_debug.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ns_debug.h
new file mode 100644
index 0000000..840ca02
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ns_debug.h
@@ -0,0 +1,84 @@
+/*
+ * FILENAME: ns_debug.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: DNS
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/*
+ * Copyright (c) 1998, Neelum Inc. Sunnyvale, CA 94086. USA.
+ */
+
+/*
+ * $Id: ns_debug.h,v 1.1.2.1 2007/07/24 02:19:27 steveh Exp $
+ * $Log: ns_debug.h,v $
+ * Revision 1.1.2.1  2007/07/24 02:19:27  steveh
+ * moved from dnssrv to h
+ *
+ * Revision 7.1  2003/11/11 00:44:33  Satish
+ * V6_to_V7
+ *
+ * Revision 6.1  2002/05/31 21:48:19  frank
+ * V5_to_V6
+ *
+ * Revision 5.1  2001/06/22 23:34:56  frank
+ * V4_to_V5
+ *
+ * Revision 4.3  2001/06/22 20:44:40  frank
+ * V_to_V
+ *
+ * Revision 4.2  2001/06/22 20:44:39  frank
+ * V4_to_V
+ *
+ * Revision 4.1  2000/11/01 23:31:28  amba
+ * Initial revision
+ *
+ * Revision 1.1  1999/11/16 17:28:43  narayan
+ *  Version 1.5 Check-in
+ *
+ */
+#define  NSM_ERR  (1<<0l)  /* Errors  */
+#define  NSM_IO   (1<<1l)  /* When doing IO */
+#define  NSM_SYSQUERY   (1<<2l)  /* Sysquery  */
+#define  NSM_CACHE   (1<<3l)
+#define  NSM_DB   (1<<4l)
+#define  NSM_QUERY   (1<<5l)
+#define  NSM_RESP (1<<6l)
+#define  NSM_REQ  (1<<7l)
+#define  NSM_NS   (1<<8l)
+#define  NSM_ZONE (1<<9l)  /* Zone transfers */
+#define  NSM_RR   (1<<10l)
+#define  NSM_LOOKUP  (1<<11l)
+#define  NSM_RETRY   (1<<12l)
+#define  NSM_MISC (1<<13l)
+#define  NSM_MATCH   (1<<14l) /* Name matches  */
+#define  NSM_HASH (1<<15l) /* Hash matches  */
+#define  NSM_INIT (1<<16l) /* Init routines */
+#define  NSM_FORW (1<<17l) /* Forwarding  */
+
+#define  FP_QUERY(level,msg)
+
+#ifdef INTERNICHE
+#define  log_msg  printf
+#define  debug_prf   printf
+#endif
+
+#if defined(DEBUG) || defined(_DEBUG)
+extern   long  _ns_dbg;
+#define  NS_DEBUG(m,a)  if ((m)  &  _ns_dbg) debug_prf   a;
+#define ASSERT(exp) if (!(exp)) {    \
+ debug_prf ("ASSERT FAILED <%s> %s:%d\n",#exp, __FILE__, __LINE__);\
+ panic ("assert");}
+#else
+#define  NS_DEBUG(m,a)
+#define  ASSERT(x)
+#endif
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nvfsio.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nvfsio.h
new file mode 100644
index 0000000..6e4cd34
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nvfsio.h
@@ -0,0 +1,79 @@
+/*
+ * FILENAME: nvfsio.h
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Definitions for generic file system NV parm IO.
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef _NVFSIO_H_
+#define  _NVFSIO_H_  1
+
+/* define these only if building with NVPARMS */
+#ifdef INCLUDE_NVPARMS
+
+struct nvparm_info;
+struct nvparm_format;
+
+int   get_file_parms(char * filename, struct nvparm_format *, int *);
+
+#ifndef  NV_LINELENGTH
+#define  NV_LINELENGTH     80
+#endif
+
+/* map non-volatile parameters file IO to VFS or local disk system,
+ * as appropriate
+ */
+
+#ifdef HT_LOCALFS    /* write NV parameters file to disk */
+#define  NV_FILE        FILE
+#define  nv_fopen       fopen
+#define  nv_fclose      fclose
+#define  nv_fprintf     fprintf
+#define  nv_fgets       fgets
+#define  nv_fread       fread
+#define  nv_fwrite      fwrite
+#define  nv_fseek       fseek
+#else /* no HT_LOCALFS, must use VFS */
+#ifndef VFS_FILES
+#error must have VFS_FILES or HT_LOCALFS
+#endif   /* no VFSFILES */
+#define  NV_FILE        VFILE
+#define  nv_fopen       vfopen
+#define  nv_fclose      vfclose
+#define  nv_fread       vfread
+#define  nv_fwrite      vfwrite
+#define  nv_fseek       vfseek
+#ifndef  _NVFSIO_C_  /* Don't include varargs protottype in code file */
+int      nv_fprintf(NV_FILE * fd, char * format, ...);
+char *   nv_fgets(char * buffer, int maxlen, NV_FILE * fd);
+#endif   /* _NVFSIO_C_ */
+#endif   /*  HT_LOCALFS */
+
+
+/* optional per-port routine to write nvfs image to flash part */
+extern   void (*nv_writeflash)(void);
+
+#endif   /* INCLUDE_NVPARMS */
+
+#ifdef   HT_SYNCDEV
+
+/* The next two routines implement the mapping from vfs_sync to a 
+ * generic flash device, e.g. the AMD AM29F04. The flash code must
+ * export these routines for SYNCDEV to work.
+ */
+
+
+extern   int   ProgramFlash(u_long fd, char * buf, unsigned bytes_to_write);
+extern   int   EraseFlash(int sector);
+
+#endif /* HT_SYNCDEV */
+
+#endif   /* _NVFSIO_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/nvparms.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/nvparms.h
new file mode 100644
index 0000000..8ac3cf5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/nvparms.h
@@ -0,0 +1,238 @@
+/*
+ * FILENAME: nvparms.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. */
+
+
+#ifndef _NVPARMS_H
+#define  _NVPARMS_H  1
+
+#include "ipport.h"
+#include "libport.h"
+
+#ifdef INCLUDE_NVPARMS
+
+#ifndef MAX_NVSTRING
+#define  MAX_NVSTRING   128   /* MAX length of a nparms string */
+#endif /* MAX_NVSTRING */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "vfsfiles.h"
+#include "nvfsio.h"
+
+struct nvparm_info /* see explanation in nvparms.c */
+{
+   char * pattern; /* pattern to look for in file */
+   int    nvtype;
+   int    nvbound;
+   void * nvdata;
+
+   /* Optional Pointer to a function to parse proprietary nvparm types.
+    * This is usually initialised to null as most modules use generic
+    * nvparm data types unlike DHCP Server.
+    */
+   int    (*get_nvprop_type)(struct nvparm_info * nvinfo_ptr, char * parm);
+};
+
+extern struct nvparm_info ppp_nvformats[];
+
+/* Module specific nvparm_format structure */
+struct nvparm_format
+{
+   int count;          /* no. of elements in the info_ptr list */
+   struct nvparm_info * info_ptr;
+   int (*setfunc)(NV_FILE *);
+   struct nvparm_format * next_format;
+};
+
+extern struct nvparm_format ppp_format;
+
+
+int install_nvformat(struct nvparm_format * new_nvformat, 
+                     struct nvparm_format * head_nvformat);
+
+extern struct nvparm_format *nv_formats;
+
+/* per-iface structure. These match up the the nets[] array */
+struct ifinfo
+{
+   char        name[IF_NAMELEN]; /* name of interface */
+   ip_addr     ipaddr;           /* IP address for this iface */
+   ip_addr     subnet;           /* subnet mask for above */
+   ip_addr     gateway;          /* default gateway */
+   int         client_dhcp;      /* bool - Be DHCP client on this link */
+#ifdef IP_V6
+   ip6_addr   ipv6addr;          /* IPV6 global address */
+#endif
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   u_char      igmp_oper_mode;   /* IGMP protocol (v1 or v2) that will 
+                                  * be run on this link */
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+};
+
+
+/* Structure for NV data set/written by xxx_nv_parms() routines */
+struct inet_nvparam
+{
+   struct ifinfo  ifs[MAXNETS];  /* per-interface IP info */
+
+#ifdef DNS_CLIENT
+#ifndef MAXDNSSERVERS
+#define  MAXDNSSERVERS  3        /* MAX number of servers to try */
+#endif
+   ip_addr  dns_servers[MAXDNSSERVERS];   /* DNS servers */
+#ifdef DNS_CLIENT_UPDT
+   char     dns_zone_name[MAX_NVSTRING];  /* zone name   */
+   u_long   dns_update_server;            /* dynamic update server name   */
+#endif /* DNS_CLIENT_UPDT */
+#endif /* DNS_CLIENT */
+};
+
+#ifdef USE_COMPORT
+struct comport_nvparam
+{
+   int   comport;             /* PC comm port to default to */
+   int   LineProtocol;        /* 1=PPP, 2=SLIP */
+};
+
+extern struct comport_nvparam comport_nvparms;
+#endif /* USE_COMPORT */
+
+/* the IP stack's nvparm structure */
+extern struct inet_nvparam inet_nvparms;
+
+#ifdef USE_COMPORT
+extern   struct comport_nvparam comport_nvparms;
+#endif /* USE_COMPORT */
+
+extern   void (*set_nv_defaults)(void);
+
+int   get_nv_params(void);
+int   set_nv_params(void * pio);
+int   edit_nv_params(void * pio);
+int   if_configbyname(NET);
+
+
+#define NVINT             20
+#define NVCHAR            21
+#define NVUNSHORT         22
+#define NVIPDEC           23
+#define NVBOOL            24
+#define NVSTRING          25
+
+/* proprietary NVPARMS types for NicheStack */
+/* Necessary Evils for NETS array parms */
+#define NVIF_NETS         26    /* Can be no. or name */
+#define NVIPDEC_NETS      27
+#define NVSBDEC_NETS      28
+#define NVGTDEC_NETS      29
+#define NVBOOL_NETS       30
+#define NVCHAR_NETS       35
+
+/* Not so necessary Evils */
+#define NVDNSSRV          31    /* Special type for DNS Clients' Srv No. & IP's */
+#define NVLINEPROT        32
+#define NVIPV6DEC_NETS    33
+#define NVIP46DEC         34    /* used to read IPv4/IPv6 addresses */
+
+#define NVBND_NOOP        -1
+
+/* Module specific proprietary NVPARMS types that require/maintain function
+ * pointers to parse functions that are aware of these new nvparm datatypes
+ *
+ * While adding new types use codes in the range of 100 to 200 to aid error
+ * checking in the get_nv_value() routine in nvparms.c.
+ *
+ * Note that the values for all these macros need not be distinct, only the 
+ * types that are mapped to a particular parse function need to be distinct.
+ *
+ * So in this example only the macros in the NVPR_DHS_XXX_NETS block need to
+ * be distinct from each other and can be repeated in the NVPR_DHS_XX_POOL 
+ * block since they are mapped to two different parse functions. But all the
+ * values do need to be in the valid range of 100 - 200.
+ */
+
+#define NVPR_DHS_NIF_NETS 121
+#define NVPR_DHS_DGW_NETS 122
+#define NVPR_DHS_DNS_NETS 123
+#define NVPR_DHS_DOM_NETS 124
+#define NVPR_DHS_SNM_NETS 125
+#define NVPR_DHS_LEA_NETS 126
+
+#define NVPR_DHS_ID_POOL 127
+#define NVPR_DHS_HI_POOL 128
+#define NVPR_DHS_LW_POOL 129
+#define NVPR_DHS_IF_POOL 130
+
+#define NVPR_DHS_IDN_CLI 131
+#define NVPR_DHS_HNM_CLI 132
+#define NVPR_DHS_LEA_CLI 133
+#define NVPR_DHS_DIP_CLI 134
+#define NVPR_DHS_SNM_CLI 135
+#define NVPR_DHS_DGW_CLI 136
+#define NVPR_DHS_DNS_CLI 137
+
+
+
+/* nv_sectioninfo represents information about a section in the NV file. 
+ * 1. Name of the section 
+ * 2. Function to be called to parse a line in that section. 
+ * 3. Name of the list which contains all elements for 
+ * this section. (used only by the add/del menu commands) 
+ * 4. Function called to print usage of a command. 
+ * (used only by the add/del menu commands) So, for providing 
+ * implementation for a new section, the following needs to be done. 
+ * 1. Add a function to parse a line in that section. 
+ * 2. Add an entry to the v3_sections array. This would 
+ * ensure that all the values from the new section will be read 
+ * during init time. 
+ *
+ * To provide command line addition, deletion 
+ * commands for a table, information about list and function 
+ * displaying usage (of the command) should also be added to 
+ * v3_sections array. 
+ *
+ * If any application needs to read table/tables from a NV file,
+ * then it should do the following
+ * 1. Define a nv_sectioninfo array (e.g. v3_sections[] for SNMPv3)
+ * 2. Call nv_read_parse() to read and parse all the sections
+ *    from fname. 
+ *
+ * 2/22/2 - Moved from SNMPv3 -AT-
+ */
+
+struct nv_sectioninfo
+{
+   char * name  ;                   /* name of section */
+   int (*parse_func)(char * line);  /* Function to parse the section */
+   void * list;                     /* Name of list containing all elements */
+   void (*usage_func)(void * pio);  /* Function to print usage of cmd */
+};
+
+int nv_get_sec_num(char * buf, struct nv_sectioninfo *sec, int slen);
+int nv_read_parse(char *fname, struct nv_sectioninfo *sec,int slen);
+int nv_add_entry(void * pio, int index, struct nv_sectioninfo *sec);
+int nv_del_entry(void * pio, int index, struct nv_sectioninfo *sec);
+int nv_del_entry_byid(void * pio, int index, struct nv_sectioninfo *sec);
+
+
+#define  NOT_A_SECTION        -1
+
+#endif   /* INCLUDE_NVPARMS */
+
+#endif   /* _NVPARMS_H */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/pmtu.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/pmtu.h
new file mode 100644
index 0000000..833d80b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/pmtu.h
@@ -0,0 +1,81 @@
+/*
+ * FILENAME: pmtu.h
+ *
+ * Copyright 2001 InterNiche Technologies Inc.  All rights reserved.
+ *
+ * Path MTU cache definitions
+ *
+ * MODULE: INET
+ *
+ * PORTABLE: yes
+ *
+ */
+
+#ifndef PMTU_H_
+#define PMTU_H_
+
+#ifdef  IP_PMTU
+
+/*
+ * struct pmtucacheent - a Path MTU cache entry
+ */
+struct pmtucacheent
+{
+   ip_addr dest;              /* peer IP address, in network order */
+   u_long lastused;           /* time (cticks) entry was last referenced */
+   u_long lastchanged;        /* time (cticks) entry was last changed */
+   unsigned pmtu;             /* current path MTU estimate */
+};
+
+/*
+ * pmtu_maxcache: maximum number of Path MTU cache entries
+ *
+ * This global contains the limit on the number of Path MTU cache 
+ * entries retained by the stack.  It is intended to be set from 
+ * the IP_PMTU_MAXCACHE macro (so can be set by ipport.h) or
+ * overridden by the target's startup code *before startup*
+ * (i.e. before pmtucache_init() is called by ip_init()).
+ */
+extern int pmtu_maxcache;
+
+/*
+ * pmtu_timeout: time (in seconds) that a cached entry can remain
+ * without an update before it is invalidated
+ *
+ * This global contains the time limit after which a cached Path MTU 
+ * value will be re-initialized to force re-discovery.  A value of 
+ * 0 turns off this function (i.e. cached Path MTU values will be 
+ * able to hang around forever).  It is intended to be set from 
+ * the IP_PMTU_TIMEOUT macro (so can be set by ipport.h) or
+ * overridden by the target's startup code, preferably before startup
+ * (i.e. before pmtucache_init() is called by ip_init()).
+ */
+extern u_long pmtu_timeout;
+
+/*
+ * pmtu_llimit: lower limit for Path MTU guesses
+ *
+ * This global contains the lower limit for path MTU estimates made by
+ * pmtu_nextguess().  It is intended to be set from the IP_PMTU_LLIMIT
+ * macro (so can be set by ipport.h) or overridden by the target's
+ * startup code, preferably before startup (i.e. before
+ * pmtucache_init() is called by ip_init()).  
+ */
+extern unsigned pmtu_llimit;
+
+/*
+ * function prototypes
+ */
+int pmtucache_init(void);
+void pmtucache_exit(void);
+void pmtucache_set(ip_addr dest, unsigned pmtu);
+unsigned pmtucache_get(ip_addr dest);
+#ifdef  NET_STATS
+int pmtu_stats(void * pio);
+#endif  /* NET_STATS */
+
+#endif  /* IP_PMTU */
+
+#endif  /* PMTU_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/ppp_port.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/ppp_port.h
new file mode 100644
index 0000000..9374664
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/ppp_port.h
@@ -0,0 +1,151 @@
+/*
+ * Filename: ppp_port.h
+ *
+ * Copyright 2004 by InterNiche Technologies Inc. All rights reserved.
+ *
+ * NetPort PPP layer's per-port definitions. The portions of the PPP 
+ * stack which may need to be modified for new ports are placed in 
+ * this file.
+ *
+ * All these should be re-examined with each new port of the code.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * 06/21/2004
+ *
+ */
+
+#ifndef _PPP_PORT_H
+#define _PPP_PORT_H 1
+
+#include "ipport.h"  /* NetPort IP Stack definitions */
+
+#include "libport.h"    /* misclib option switches */
+#include "in_utils.h"   /* for resolving references to GEN_IO */
+
+#ifdef IN_MENUS
+#include "menu.h"
+#endif   /* IN_MENUS */
+
+#ifdef USE_PPP       /* whole file can be ifdeffed out */
+
+/* PPP options included in this port: */
+#define LOCAL_RAND   1  /* use random number generator in magic.c */
+
+#ifdef NOTDEF
+Unused PPP options listed here:
+#endif
+
+/* debug switches */
+#define DEBUGFSM     1  /* ConPrintf from the FSM layer  */
+#define DEBUGLCP     1  /* ConPrintf from the LCP layer  */
+#define DEBUGIPCP    1  /* ConPrintf from the IPCP layer */
+#define DEBUGCHAP    1  /* ConPrintf from the CHAP layer */
+#define DEBUGUPAP    1  /* ConPrintf from the UPAP layer */
+
+#define PPP_CONSOLE_LOG_STAT    0  /* disable console logging */
+#define PPP_BRIEF_CONSOLE_LOG   1  /* show brief msg on snd/rcv of PPPpkt */
+
+/* number of PPP interfaces in this port */
+#ifdef DYNAMIC_IFACES
+#define _NPPP 4  /* Allow creation of runtime ppp loopback iface */
+#elif defined(LB_XOVER)
+#define _NPPP	2  /* 2 loopback */
+#else
+#define _NPPP	1  /* 1 modem */
+#endif
+
+#ifdef LB_XOVER   /* define which two units loopback connects */
+#define LBUNIT1   0
+#define LBUNIT2   1
+#endif
+
+#define MAXNAMELEN   32   /* max length of hostname or name for auth */
+#define MAXSECRETLEN 32   /* max length of password or secret */
+#define MAX_DUMP_BYTES   1536 /* MAX bytes when ConPrintf-dumping pkt */
+
+#ifdef __BORLANDC__
+/* for borland port, bring in FP_SEG() macro */
+/* #include <dos.h> *************/
+/* #define _FP_SEG(u) FP_SEG(u) */
+#endif /* __BORLANDC__ */
+
+#define GetTickCount()	(cticks)
+
+extern int  do_dhcp_client;   /* TRUE if we should do DHCP over PPP */
+extern char * hostname; /* name of this system, for CHAP auth. */
+extern int  dhc_discover(int iface);   /* send DHCP discovery */
+
+extern unsigned NDEBUG;	/* debug printing bit mask in ..\inet */
+
+extern int PPPDEBUG;	/* Bitmask of PPP debug options */
+
+#define	PPPD_FILE		0x01	/* Send debug printfs to log file */
+#define	PPPD_CONS		0x02	/* send debug printfs to console */
+
+void	ppp_output(int unit,	u_char * data,	int len);
+
+/* set system wide defaults for datagram sizes */
+#define PPP_MRU 1500    /* received frames */
+#define PPP_MTU 1500    /* transmitted frames */
+
+#ifndef _PPP_PORT_C
+void  ConPrintf(const char * format, ...);
+#else
+/*
+void  ConPrintf();
+*/
+#endif
+
+/* the PPP alloc routines */
+#define MPPP_ALLOC(size) (M_PPP)npalloc(size)
+#define MPPP_FREE(ptr) npfree(ptr)
+
+extern int ppp_port_init(int iface);   /* per-port PPP init */
+
+#ifdef INCLUDE_NVPARMS
+struct ppp_nvparam
+{
+   /* PPP options: */
+   int      ppp_ConsoleLog;   /* bool - Log Modem & PPP events to console */
+   int      ppp_FileLog;      /* bool - Log Modem & PPP events to file */
+   unshort  ppp_keepalive;    /* seconds between PPP echos, 0=disable */
+   unshort  ppp_client_tmo;   /* timeout for connects as client */
+#ifdef PPP_VJC
+   int      ppp_request_vj;   /* bool - request that the other side do VJ compression */
+#endif   /* PPP_VJC */
+#ifdef   CHAP_SUPPORT   /* from ppp_port.h */
+   char     secret[MAX_NVSTRING];   /* secret for CHAP/MD5 hashing */
+   int      require_chap;     /* bool - require CHAP from PPP connections */
+#endif   /* CHAP_SUPPORT */
+#ifdef PAP_SUPPORT
+   int      require_pap;
+#endif   /* PAP_SUPPORT */
+   char     username[MAX_NVSTRING];
+   char     password[MAX_NVSTRING];
+   unshort  line_tmo;   /* idle modem line timeout, 0=infinite */
+   char     loginfile[MAX_NVSTRING];   /* path/name of file with login script */
+   char     logservefile[MAX_NVSTRING];   /* login server script */
+};
+
+extern struct ppp_nvparam ppp_nvparms;
+#endif   /* INCLUDE_NVPARMS */
+
+#ifdef IN_MENUS
+extern struct menu_op pppmenu[];
+#endif   /* IN_MENUS */
+
+#ifdef INCLUDE_NVPARMS 
+extern struct nvparm_info ppp_nvformats[];
+extern struct nvparm_format ppp_format;
+#endif   /* INCLUDE_NVPARMS */
+
+#endif /* USE_PPP */
+#endif   /* _PPP_PORT_H */
+/* end of file ppp_port.h */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/profiler.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/profiler.h
new file mode 100644
index 0000000..0a06be3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/profiler.h
@@ -0,0 +1,118 @@
+/*
+ * FILENAME: profiler.h
+ *
+ * Copyright  2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * MODULE: MISCLIB
+ *
+ *
+ * PORTABLE: no
+ */
+
+/* profiler.h Profile code for portions of the InterNiche TCP/IP 
+ * stack and related modules. 
+ */
+#ifndef _PROFILER_H_
+#define  _PROFILER_H_   1
+
+
+/* one of these structures is defined for every module to be profiled.
+ * They kept in an array and referenced by their "id" field.
+ * Additional pbuckets can be declared and added to the array
+ * at init time.
+ */
+struct pbucket
+{
+   char *   name;             /* text name of module */
+   u_long   ticks;
+   struct pbucket ** id;      /* self reference for error checking */
+};
+
+/* Declare the maximum number of profiling buckets */
+#ifndef NUM_PBUCKETS       /* allow override from ipport.h */
+#define  NUM_PBUCKETS   15
+#endif
+
+/* The actual array of profiling buckets */
+extern   struct pbucket in_pbuckets[NUM_PBUCKETS];
+
+extern   int   pfmodules;     /* current number of active pbuckets */
+
+
+/* Some predefined struct pbucket IDs for InterNiche modules. The IDs
+ * are addresses of the modules' "bucket" structures.
+ */
+
+extern struct pbucket * PF_IP;
+extern struct pbucket * PF_USUM;
+extern struct pbucket * PF_IDLE;
+extern struct pbucket * PF_TCP;
+extern struct pbucket * PF_TSUM;
+extern struct pbucket * PF_WEB ;
+extern struct pbucket * PF_FTP;
+extern struct pbucket * PF_FS;
+extern struct pbucket * PF_NAT;
+extern struct pbucket * PF_IPSEC;
+extern struct pbucket * PF_CRYPTOENG;
+
+/* opcodes for pf_ticklog() */
+#define  PF_ENTRY    1
+#define  PF_EXIT     2
+
+
+/* profiler system start & stop routines. This should be called either
+ * by application code or fome the profiler menu to bracket in time
+ * the software events to be profiled. NOTE: These do not accumulate -
+ * calling pf_start() wipes out all previous profile data.
+ */
+void  pf_start(void);
+void  pf_stop(void);
+
+/* This is called by the monitored code modules whenever they are
+ * entered or exited. See IN_PROFILER() macro.
+ */
+void  pf_ticklog(struct pbucket * id, int opcode);
+
+/* this is called to add a new module to profiling. The returned value is 
+ * the module ID which should be passed to IN_PROFILER() to begin/exit
+ * profiling the module. The passed name should be static text.
+ */
+
+void *   pf_addmodule(char * name);
+
+
+/* This port-provided routine should return a fast tick for profiling.
+ * Million ticks a sec or so is good. cticks is too slow to be suitable
+ * for this.
+ */
+extern   u_long   get_ptick(void);
+
+
+/* helper utility for calculating ticks percentages */
+void  pf_percent(u_long total, u_long ticks, int * pct, int * dec);
+
+
+/* To use the CPU cycles per packet (or connection) functions below, you
+ * must set "#define PKT_CYCLES 1" in ipport.h_h
+ */
+extern   int   pkc_start(void * pio);
+extern   int   pkc_del(void * pio);
+extern   int   pkc_ping(void * pio);
+extern   int   pkc_tcpecho(void * pio);
+extern   int   pkc_udpecho(void * pio);
+extern   int   pkc_calibrate(void * pio);
+extern   int   pkc_mode(void * pio);
+extern   int   pkc_data(void * pio);
+
+/* Macro so net sources can use profiler (or not) without littering the
+ * source code with ifdefs:
+ */
+#ifdef USE_PROFILER
+#define  IN_PROFILER(id, opcode)  pf_ticklog((struct pbucket *)id, opcode)
+#else
+#define  IN_PROFILER(id,  opcode)  /* define away */
+#endif   /* USE_PROFILER */
+
+#endif   /*  _PROFILER_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/q.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/q.h
new file mode 100644
index 0000000..e50b9f4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/q.h
@@ -0,0 +1,111 @@
+/*
+ * FILENAME: q.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Software Definitions for the basic queing package. See netq.h for
+ * some extensions.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1994 by NetPort 10/13/90 
+ * Portions Copyright 1986 by Carnegie Mellon 
+ * Portions Copyright 1983 by the Massachusetts Institute of 
+ * Technology 
+ */
+
+#ifndef _Q_H_
+#define  _Q_H_ 1
+
+struct   q_elt    {     /* queue element: cast to right type */
+   struct   q_elt   *   qe_next; /* it's just a pointer to next elt */
+};
+
+typedef struct q_elt * qp;    /* q pointer */
+
+#define  q_elt qp
+
+typedef   struct   queue   
+{        /* queue header */
+   q_elt q_head;        /* first element in queue */
+   q_elt q_tail;        /* last element in queue */
+   int   q_len;         /* number of elements in queue */
+   int   q_max;         /* maximum length */
+   int   q_min;         /* minimum length */
+} queue;
+
+/* The following macros implement most of the common queue operations */
+
+/* Add an element to the head of the queue */
+
+#define   q_addh(q, elt)    { \
+   if ((q)->q_head == 0) (q)->q_tail = (elt); \
+   (elt)->qe_next = (q)->q_head; \
+   (q)->q_head = (elt); \
+   (q)->q_len++; \
+   if(++((q)->q_len) > (q)->q_max) (q)->q_max = (q)->q_len; \
+}
+
+/* Add an element to the tail of a queue */
+
+#define   q_addt(q, elt)   { \
+   (elt)->qe_next = 0; \
+   if ((q)->q_head == 0) { \
+      (q)->q_head = (elt); \
+   } else { \
+      (q)->q_tail->qe_next = (elt); \
+   } \
+   (q)->q_tail = (elt); \
+   if(++((q)->q_len) > (q)->q_max) (q)->q_max = (q)->q_len; \
+}
+
+/* Add an element after a specified element in the queue.  If prev == */
+/* &q->q_head, can be used to add an element to the head of the queue */
+
+#define   q_adda(q, prev, new)   { \
+   if ((q)->q_tail == (prev) || (q)->q_tail == 0) { \
+      (q)->q_tail = (new); \
+   } \
+   (new)->qe_next = (prev)->qe_next; \
+   (prev)->qe_next = (new); \
+   if(++((q)->q_len) > (q)->q_max) (q)->q_max = (q)->q_len; \
+}
+
+/* Delete an element from a queue, given a pointer to the preceeding element */
+/* Will delete the first element if prev == &q->q_head */
+
+#define   q_dela(q, elt, prev)   { \
+   if ((q)->q_tail == (elt)) { \
+      if ((q)->q_head == (elt)) \
+         (q)->q_tail = 0; \
+      else \
+         (q)->q_tail = (prev); \
+   } \
+   (prev)->qe_next = (elt)->qe_next; \
+   (elt)->qe_next = 0; \
+   if(--((q)->q_len) < (q)->q_min) (q)->q_min = (q)->q_len; \
+}
+
+/* The above MACROs are quite dangerous; because of lack of 
+ * prototypeing, compile time snags, and no built in protection from 
+ * premeption. Though they are fast, Code seems to be less buggy if 
+ */
+/* full prototypes: */
+void     putq(queue*, void*);    /* add item to tail of queue */
+void *   getq(queue*);           /* de-queue item from head of queue */
+queue *  createq(void);
+qp       qdel(queue*, void*);    /* delete an item from a queue */
+
+#define  q_add(q,p)  putq(q,p)   /* allow old MIT names */
+#define  q_deq(q) getq(q)
+#define  aq_deq(q)   getq(q)     /* putq() and getq() are always atomic */
+#define  q_create()  createq() 
+
+#endif   /* _Q_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/snmp_vie.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/snmp_vie.h
new file mode 100644
index 0000000..f50b5b6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/snmp_vie.h
@@ -0,0 +1,1048 @@
+/* snmp_vie.h
+
+	'.h' file Generated by InterNiche Technologies Inc. MIB Compiler
+
+	Copyright 1993-2003 by InterNiche Technologies Inc.
+
+*/
+
+
+#ifndef SNMP_VIE_H
+#define SNMP_VIE_H
+
+/* Tokens for passing to "var_" routines. These can
+serve as offsets into the generated MIB group tables.
+*/
+
+
+/* tokens for 'system' group */
+#define SYSDESCR	0
+#define SYSOBJECTID	SYSDESCR+4
+#define SYSUPTIME	SYSOBJECTID+4
+#define SYSCONTACT	SYSUPTIME+4
+#define SYSNAME	SYSCONTACT+4
+#define SYSLOCATION	SYSNAME+4
+#define SYSSERVICES	SYSLOCATION+4
+#define SYSORLASTCHANGE	SYSSERVICES+4
+
+/* tokens for 'sysOREntry' group */
+#define SYSORINDEX	0
+#define SYSORID	SYSORINDEX+4
+#define SYSORDESCR	SYSORID+4
+#define SYSORUPTIME	SYSORDESCR+4
+
+/* tokens for 'interfaces' group */
+#define IFNUMBER	0
+
+/* tokens for 'ifEntry' group */
+#define IFINDEX	0
+#define IFDESCR	IFINDEX+4
+#define IFTYPE	IFDESCR+4
+#define IFMTU	IFTYPE+4
+#define IFSPEED	IFMTU+4
+#define IFPHYSADDRESS	IFSPEED+4
+#define IFADMINSTATUS	IFPHYSADDRESS+4
+#define IFOPERSTATUS	IFADMINSTATUS+4
+#define IFLASTCHANGE	IFOPERSTATUS+4
+#define IFINOCTETS	IFLASTCHANGE+4
+#define IFINUCASTPKTS	IFINOCTETS+4
+#define IFINNUCASTPKTS	IFINUCASTPKTS+4
+#define IFINDISCARDS	IFINNUCASTPKTS+4
+#define IFINERRORS	IFINDISCARDS+4
+#define IFINUNKNOWNPROTOS	IFINERRORS+4
+#define IFOUTOCTETS	IFINUNKNOWNPROTOS+4
+#define IFOUTUCASTPKTS	IFOUTOCTETS+4
+#define IFOUTNUCASTPKTS	IFOUTUCASTPKTS+4
+#define IFOUTDISCARDS	IFOUTNUCASTPKTS+4
+#define IFOUTERRORS	IFOUTDISCARDS+4
+#define IFOUTQLEN	IFOUTERRORS+4
+#define IFSPECIFIC	IFOUTQLEN+4
+
+/* tokens for 'atEntry' group */
+#define ATIFINDEX	0
+#define ATPHYSADDRESS	ATIFINDEX+4
+#define ATNETADDRESS	ATPHYSADDRESS+4
+
+/* tokens for 'ip' group */
+#define IPFORWARDING	0
+#define IPDEFAULTTTL	IPFORWARDING+4
+#define IPINRECEIVES	IPDEFAULTTTL+4
+#define IPINHDRERRORS	IPINRECEIVES+4
+#define IPINADDRERRORS	IPINHDRERRORS+4
+#define IPFORWDATAGRAMS	IPINADDRERRORS+4
+#define IPINUNKNOWNPROTOS	IPFORWDATAGRAMS+4
+#define IPINDISCARDS	IPINUNKNOWNPROTOS+4
+#define IPINDELIVERS	IPINDISCARDS+4
+#define IPOUTREQUESTS	IPINDELIVERS+4
+#define IPOUTDISCARDS	IPOUTREQUESTS+4
+#define IPOUTNOROUTES	IPOUTDISCARDS+4
+#define IPREASMTIMEOUT	IPOUTNOROUTES+4
+#define IPREASMREQDS	IPREASMTIMEOUT+4
+#define IPREASMOKS	IPREASMREQDS+4
+#define IPREASMFAILS	IPREASMOKS+4
+#define IPFRAGOKS	IPREASMFAILS+4
+#define IPFRAGFAILS	IPFRAGOKS+4
+#define IPFRAGCREATES	IPFRAGFAILS+4
+#define IPROUTINGDISCARDS	IPFRAGCREATES+4
+
+/* tokens for 'ipAddrEntry' group */
+#define IPADENTADDR	0
+#define IPADENTIFINDEX	IPADENTADDR+4
+#define IPADENTNETMASK	IPADENTIFINDEX+4
+#define IPADENTBCASTADDR	IPADENTNETMASK+4
+#define IPADENTREASMMAXSIZE	IPADENTBCASTADDR+4
+
+/* tokens for 'ipRouteEntry' group */
+#define IPROUTEDEST	0
+#define IPROUTEIFINDEX	IPROUTEDEST+4
+#define IPROUTEMETRIC1	IPROUTEIFINDEX+4
+#define IPROUTEMETRIC2	IPROUTEMETRIC1+4
+#define IPROUTEMETRIC3	IPROUTEMETRIC2+4
+#define IPROUTEMETRIC4	IPROUTEMETRIC3+4
+#define IPROUTENEXTHOP	IPROUTEMETRIC4+4
+#define IPROUTETYPE	IPROUTENEXTHOP+4
+#define IPROUTEPROTO	IPROUTETYPE+4
+#define IPROUTEAGE	IPROUTEPROTO+4
+#define IPROUTEMASK	IPROUTEAGE+4
+#define IPROUTEMETRIC5	IPROUTEMASK+4
+#define IPROUTEINFO	IPROUTEMETRIC5+4
+
+/* tokens for 'ipNetToMediaEntry' group */
+#define IPNETTOMEDIAIFINDEX	0
+#define IPNETTOMEDIAPHYSADDRESS	IPNETTOMEDIAIFINDEX+4
+#define IPNETTOMEDIANETADDRESS	IPNETTOMEDIAPHYSADDRESS+4
+#define IPNETTOMEDIATYPE	IPNETTOMEDIANETADDRESS+4
+
+/* tokens for 'icmp' group */
+#define ICMPINMSGS	0
+#define ICMPINERRORS	ICMPINMSGS+4
+#define ICMPINDESTUNREACHS	ICMPINERRORS+4
+#define ICMPINTIMEEXCDS	ICMPINDESTUNREACHS+4
+#define ICMPINPARMPROBS	ICMPINTIMEEXCDS+4
+#define ICMPINSRCQUENCHS	ICMPINPARMPROBS+4
+#define ICMPINREDIRECTS	ICMPINSRCQUENCHS+4
+#define ICMPINECHOS	ICMPINREDIRECTS+4
+#define ICMPINECHOREPS	ICMPINECHOS+4
+#define ICMPINTIMESTAMPS	ICMPINECHOREPS+4
+#define ICMPINTIMESTAMPREPS	ICMPINTIMESTAMPS+4
+#define ICMPINADDRMASKS	ICMPINTIMESTAMPREPS+4
+#define ICMPINADDRMASKREPS	ICMPINADDRMASKS+4
+#define ICMPOUTMSGS	ICMPINADDRMASKREPS+4
+#define ICMPOUTERRORS	ICMPOUTMSGS+4
+#define ICMPOUTDESTUNREACHS	ICMPOUTERRORS+4
+#define ICMPOUTTIMEEXCDS	ICMPOUTDESTUNREACHS+4
+#define ICMPOUTPARMPROBS	ICMPOUTTIMEEXCDS+4
+#define ICMPOUTSRCQUENCHS	ICMPOUTPARMPROBS+4
+#define ICMPOUTREDIRECTS	ICMPOUTSRCQUENCHS+4
+#define ICMPOUTECHOS	ICMPOUTREDIRECTS+4
+#define ICMPOUTECHOREPS	ICMPOUTECHOS+4
+#define ICMPOUTTIMESTAMPS	ICMPOUTECHOREPS+4
+#define ICMPOUTTIMESTAMPREPS	ICMPOUTTIMESTAMPS+4
+#define ICMPOUTADDRMASKS	ICMPOUTTIMESTAMPREPS+4
+#define ICMPOUTADDRMASKREPS	ICMPOUTADDRMASKS+4
+
+/* tokens for 'tcp' group */
+#define TCPRTOALGORITHM	0
+#define TCPRTOMIN	TCPRTOALGORITHM+4
+#define TCPRTOMAX	TCPRTOMIN+4
+#define TCPMAXCONN	TCPRTOMAX+4
+#define TCPACTIVEOPENS	TCPMAXCONN+4
+#define TCPPASSIVEOPENS	TCPACTIVEOPENS+4
+#define TCPATTEMPTFAILS	TCPPASSIVEOPENS+4
+#define TCPESTABRESETS	TCPATTEMPTFAILS+4
+#define TCPCURRESTAB	TCPESTABRESETS+4
+#define TCPINSEGS	TCPCURRESTAB+4
+#define TCPOUTSEGS	TCPINSEGS+4
+#define TCPRETRANSSEGS	TCPOUTSEGS+4
+#define TCPINERRS	TCPRETRANSSEGS+4
+#define TCPOUTRSTS	TCPINERRS+4
+
+/* tokens for 'tcpConnEntry' group */
+#define TCPCONNSTATE	0
+#define TCPCONNLOCALADDRESS	TCPCONNSTATE+4
+#define TCPCONNLOCALPORT	TCPCONNLOCALADDRESS+4
+#define TCPCONNREMADDRESS	TCPCONNLOCALPORT+4
+#define TCPCONNREMPORT	TCPCONNREMADDRESS+4
+
+/* tokens for 'udp' group */
+#define UDPINDATAGRAMS	0
+#define UDPNOPORTS	UDPINDATAGRAMS+4
+#define UDPINERRORS	UDPNOPORTS+4
+#define UDPOUTDATAGRAMS	UDPINERRORS+4
+
+/* tokens for 'udpEntry' group */
+#define UDPLOCALADDRESS	0
+#define UDPLOCALPORT	UDPLOCALADDRESS+4
+
+/* tokens for 'egp' group */
+#define EGPINMSGS	0
+#define EGPINERRORS	EGPINMSGS+4
+#define EGPOUTMSGS	EGPINERRORS+4
+#define EGPOUTERRORS	EGPOUTMSGS+4
+#define EGPAS	EGPOUTERRORS+4
+
+/* tokens for 'egpNeighEntry' group */
+#define EGPNEIGHSTATE	0
+#define EGPNEIGHADDR	EGPNEIGHSTATE+4
+#define EGPNEIGHAS	EGPNEIGHADDR+4
+#define EGPNEIGHINMSGS	EGPNEIGHAS+4
+#define EGPNEIGHINERRS	EGPNEIGHINMSGS+4
+#define EGPNEIGHOUTMSGS	EGPNEIGHINERRS+4
+#define EGPNEIGHOUTERRS	EGPNEIGHOUTMSGS+4
+#define EGPNEIGHINERRMSGS	EGPNEIGHOUTERRS+4
+#define EGPNEIGHOUTERRMSGS	EGPNEIGHINERRMSGS+4
+#define EGPNEIGHSTATEUPS	EGPNEIGHOUTERRMSGS+4
+#define EGPNEIGHSTATEDOWNS	EGPNEIGHSTATEUPS+4
+#define EGPNEIGHINTERVALHELLO	EGPNEIGHSTATEDOWNS+4
+#define EGPNEIGHINTERVALPOLL	EGPNEIGHINTERVALHELLO+4
+#define EGPNEIGHMODE	EGPNEIGHINTERVALPOLL+4
+#define EGPNEIGHEVENTTRIGGER	EGPNEIGHMODE+4
+
+/* tokens for 'snmp' group */
+#define SNMPINPKTS	0
+#define SNMPOUTPKTS	SNMPINPKTS+4
+#define SNMPINBADVERSIONS	SNMPOUTPKTS+4
+#define SNMPINBADCOMMUNITYNAMES	SNMPINBADVERSIONS+4
+#define SNMPINBADCOMMUNITYUSES	SNMPINBADCOMMUNITYNAMES+4
+#define SNMPINASNPARSEERRS	SNMPINBADCOMMUNITYUSES+4
+#define SNMPINTOOBIGS	SNMPINASNPARSEERRS+4
+#define SNMPINNOSUCHNAMES	SNMPINTOOBIGS+4
+#define SNMPINBADVALUES	SNMPINNOSUCHNAMES+4
+#define SNMPINREADONLYS	SNMPINBADVALUES+4
+#define SNMPINGENERRS	SNMPINREADONLYS+4
+#define SNMPINTOTALREQVARS	SNMPINGENERRS+4
+#define SNMPINTOTALSETVARS	SNMPINTOTALREQVARS+4
+#define SNMPINGETREQUESTS	SNMPINTOTALSETVARS+4
+#define SNMPINGETNEXTS	SNMPINGETREQUESTS+4
+#define SNMPINSETREQUESTS	SNMPINGETNEXTS+4
+#define SNMPINGETRESPONSES	SNMPINSETREQUESTS+4
+#define SNMPINTRAPS	SNMPINGETRESPONSES+4
+#define SNMPOUTTOOBIGS	SNMPINTRAPS+4
+#define SNMPOUTNOSUCHNAMES	SNMPOUTTOOBIGS+4
+#define SNMPOUTBADVALUES	SNMPOUTNOSUCHNAMES+4
+#define SNMPOUTGENERRS	SNMPOUTBADVALUES+4
+#define SNMPOUTGETREQUESTS	SNMPOUTGENERRS+4
+#define SNMPOUTGETNEXTS	SNMPOUTGETREQUESTS+4
+#define SNMPOUTSETREQUESTS	SNMPOUTGETNEXTS+4
+#define SNMPOUTGETRESPONSES	SNMPOUTSETREQUESTS+4
+#define SNMPOUTTRAPS	SNMPOUTGETRESPONSES+4
+#define SNMPENABLEAUTHENTRAPS	SNMPOUTTRAPS+4
+#define SNMPSILENTDROPS	SNMPENABLEAUTHENTRAPS+4
+#define SNMPPROXYDROPS	SNMPSILENTDROPS+4
+
+/* tokens for 'snmpTrap' group */
+#define SNMPTRAPOID	0
+#define SNMPTRAPENTERPRISE	SNMPTRAPOID+4
+
+/* tokens for 'snmpSet' group */
+#define SNMPSETSERIALNO	0
+
+/* tokens for 'snmpEngine' group */
+#define SNMPENGINEID	0
+#define SNMPENGINEBOOTS	SNMPENGINEID+4
+#define SNMPENGINETIME	SNMPENGINEBOOTS+4
+#define SNMPENGINEMAXMESSAGESIZE	SNMPENGINETIME+4
+
+/* tokens for 'snmpMPDStats' group */
+#define SNMPUNKNOWNSECURITYMODELS	0
+#define SNMPINVALIDMSGS	SNMPUNKNOWNSECURITYMODELS+4
+#define SNMPUNKNOWNPDUHANDLERS	SNMPINVALIDMSGS+4
+
+/* tokens for 'snmpTargetObjects' group */
+#define SNMPTARGETSPINLOCK	0
+#define SNMPUNAVAILABLECONTEXTS	SNMPTARGETSPINLOCK+4
+#define SNMPUNKNOWNCONTEXTS	SNMPUNAVAILABLECONTEXTS+4
+
+/* tokens for 'snmpTargetAddrEntry' group */
+#define SNMPTARGETADDRNAME	0
+#define SNMPTARGETADDRTDOMAIN	SNMPTARGETADDRNAME+4
+#define SNMPTARGETADDRTADDRESS	SNMPTARGETADDRTDOMAIN+4
+#define SNMPTARGETADDRTIMEOUT	SNMPTARGETADDRTADDRESS+4
+#define SNMPTARGETADDRRETRYCOUNT	SNMPTARGETADDRTIMEOUT+4
+#define SNMPTARGETADDRTAGLIST	SNMPTARGETADDRRETRYCOUNT+4
+#define SNMPTARGETADDRPARAMS	SNMPTARGETADDRTAGLIST+4
+#define SNMPTARGETADDRSTORAGETYPE	SNMPTARGETADDRPARAMS+4
+#define SNMPTARGETADDRROWSTATUS	SNMPTARGETADDRSTORAGETYPE+4
+
+/* tokens for 'snmpTargetParamsEntry' group */
+#define SNMPTARGETPARAMSNAME	0
+#define SNMPTARGETPARAMSMPMODEL	SNMPTARGETPARAMSNAME+4
+#define SNMPTARGETPARAMSSECURITYMODEL	SNMPTARGETPARAMSMPMODEL+4
+#define SNMPTARGETPARAMSSECURITYNAME	SNMPTARGETPARAMSSECURITYMODEL+4
+#define SNMPTARGETPARAMSSECURITYLEVEL	SNMPTARGETPARAMSSECURITYNAME+4
+#define SNMPTARGETPARAMSSTORAGETYPE	SNMPTARGETPARAMSSECURITYLEVEL+4
+#define SNMPTARGETPARAMSROWSTATUS	SNMPTARGETPARAMSSTORAGETYPE+4
+
+/* tokens for 'snmpNotifyEntry' group */
+#define SNMPNOTIFYNAME	0
+#define SNMPNOTIFYTAG	SNMPNOTIFYNAME+4
+#define SNMPNOTIFYTYPE	SNMPNOTIFYTAG+4
+#define SNMPNOTIFYSTORAGETYPE	SNMPNOTIFYTYPE+4
+#define SNMPNOTIFYROWSTATUS	SNMPNOTIFYSTORAGETYPE+4
+
+/* tokens for 'snmpNotifyFilterProfileEntry' group */
+#define SNMPNOTIFYFILTERPROFILENAME	0
+#define SNMPNOTIFYFILTERPROFILESTORTYPE	SNMPNOTIFYFILTERPROFILENAME+4
+#define SNMPNOTIFYFILTERPROFILEROWSTATUS	SNMPNOTIFYFILTERPROFILESTORTYPE+4
+
+/* tokens for 'snmpNotifyFilterEntry' group */
+#define SNMPNOTIFYFILTERSUBTREE	0
+#define SNMPNOTIFYFILTERMASK	SNMPNOTIFYFILTERSUBTREE+4
+#define SNMPNOTIFYFILTERTYPE	SNMPNOTIFYFILTERMASK+4
+#define SNMPNOTIFYFILTERSTORAGETYPE	SNMPNOTIFYFILTERTYPE+4
+#define SNMPNOTIFYFILTERROWSTATUS	SNMPNOTIFYFILTERSTORAGETYPE+4
+
+/* tokens for 'usmStats' group */
+#define USMSTATSUNSUPPORTEDSECLEVELS	0
+#define USMSTATSNOTINTIMEWINDOWS	USMSTATSUNSUPPORTEDSECLEVELS+4
+#define USMSTATSUNKNOWNUSERNAMES	USMSTATSNOTINTIMEWINDOWS+4
+#define USMSTATSUNKNOWNENGINEIDS	USMSTATSUNKNOWNUSERNAMES+4
+#define USMSTATSWRONGDIGESTS	USMSTATSUNKNOWNENGINEIDS+4
+#define USMSTATSDECRYPTIONERRORS	USMSTATSWRONGDIGESTS+4
+
+/* tokens for 'usmUser' group */
+#define USMUSERSPINLOCK	0
+
+/* tokens for 'usmUserEntry' group */
+#define USMUSERENGINEID	0
+#define USMUSERNAME	USMUSERENGINEID+4
+#define USMUSERSECURITYNAME	USMUSERNAME+4
+#define USMUSERCLONEFROM	USMUSERSECURITYNAME+4
+#define USMUSERAUTHPROTOCOL	USMUSERCLONEFROM+4
+#define USMUSERAUTHKEYCHANGE	USMUSERAUTHPROTOCOL+4
+#define USMUSEROWNAUTHKEYCHANGE	USMUSERAUTHKEYCHANGE+4
+#define USMUSERPRIVPROTOCOL	USMUSEROWNAUTHKEYCHANGE+4
+#define USMUSERPRIVKEYCHANGE	USMUSERPRIVPROTOCOL+4
+#define USMUSEROWNPRIVKEYCHANGE	USMUSERPRIVKEYCHANGE+4
+#define USMUSERPUBLIC	USMUSEROWNPRIVKEYCHANGE+4
+#define USMUSERSTORAGETYPE	USMUSERPUBLIC+4
+#define USMUSERSTATUS	USMUSERSTORAGETYPE+4
+
+/* tokens for 'vacmContextEntry' group */
+#define VACMCONTEXTNAME	0
+
+/* tokens for 'vacmSecurityToGroupEntry' group */
+#define VACMSECURITYMODEL	0
+#define VACMSECURITYNAME	VACMSECURITYMODEL+4
+#define VACMGROUPNAME	VACMSECURITYNAME+4
+#define VACMSECURITYTOGROUPSTORAGETYPE	VACMGROUPNAME+4
+#define VACMSECURITYTOGROUPSTATUS	VACMSECURITYTOGROUPSTORAGETYPE+4
+
+/* tokens for 'vacmAccessEntry' group */
+#define VACMACCESSCONTEXTPREFIX	0
+#define VACMACCESSSECURITYMODEL	VACMACCESSCONTEXTPREFIX+4
+#define VACMACCESSSECURITYLEVEL	VACMACCESSSECURITYMODEL+4
+#define VACMACCESSCONTEXTMATCH	VACMACCESSSECURITYLEVEL+4
+#define VACMACCESSREADVIEWNAME	VACMACCESSCONTEXTMATCH+4
+#define VACMACCESSWRITEVIEWNAME	VACMACCESSREADVIEWNAME+4
+#define VACMACCESSNOTIFYVIEWNAME	VACMACCESSWRITEVIEWNAME+4
+#define VACMACCESSSTORAGETYPE	VACMACCESSNOTIFYVIEWNAME+4
+#define VACMACCESSSTATUS	VACMACCESSSTORAGETYPE+4
+
+/* tokens for 'vacmMIBViews' group */
+#define VACMVIEWSPINLOCK	0
+
+/* tokens for 'vacmViewTreeFamilyEntry' group */
+#define VACMVIEWTREEFAMILYVIEWNAME	0
+#define VACMVIEWTREEFAMILYSUBTREE	VACMVIEWTREEFAMILYVIEWNAME+4
+#define VACMVIEWTREEFAMILYMASK	VACMVIEWTREEFAMILYSUBTREE+4
+#define VACMVIEWTREEFAMILYTYPE	VACMVIEWTREEFAMILYMASK+4
+#define VACMVIEWTREEFAMILYSTORAGETYPE	VACMVIEWTREEFAMILYTYPE+4
+#define VACMVIEWTREEFAMILYSTATUS	VACMVIEWTREEFAMILYSTORAGETYPE+4
+
+/* tokens for 'snmpCommunityMIBObjects' group */
+#define SNMPTRAPADDRESS	0
+#define SNMPTRAPCOMMUNITY	SNMPTRAPADDRESS+4
+
+/* tokens for 'snmpCommunityEntry' group */
+#define SNMPCOMMUNITYINDEX	0
+#define SNMPCOMMUNITYNAME	SNMPCOMMUNITYINDEX+4
+#define SNMPCOMMUNITYSECURITYNAME	SNMPCOMMUNITYNAME+4
+#define SNMPCOMMUNITYCONTEXTENGINEID	SNMPCOMMUNITYSECURITYNAME+4
+#define SNMPCOMMUNITYCONTEXTNAME	SNMPCOMMUNITYCONTEXTENGINEID+4
+#define SNMPCOMMUNITYTRANSPORTTAG	SNMPCOMMUNITYCONTEXTNAME+4
+#define SNMPCOMMUNITYSTORAGETYPE	SNMPCOMMUNITYTRANSPORTTAG+4
+#define SNMPCOMMUNITYSTATUS	SNMPCOMMUNITYSTORAGETYPE+4
+
+/* tokens for 'snmpTargetAddrExtEntry' group */
+#define SNMPTARGETADDRTMASK	0
+#define SNMPTARGETADDRMMS	SNMPTARGETADDRTMASK+4
+
+
+
+
+/* prototypes for "var_" routines in variables table.
+Simply delete any that aren't used */
+
+u_char *
+var_system(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_sysOREntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_interfaces(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_ifEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_atEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_ip(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_ipAddrEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_ipRouteEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_ipNetToMediaEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_icmp(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_tcp(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_tcpConnEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_udp(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_udpEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_egp(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_egpNeighEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmp(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpTrap(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpSet(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpEngine(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpMPDStats(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpTargetObjects(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpTargetAddrEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpTargetParamsEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpNotifyEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpNotifyFilterProfileEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpNotifyFilterEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_usmStats(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_usmUser(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_usmUserEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_vacmContextEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_vacmSecurityToGroupEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_vacmAccessEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_vacmMIBViews(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_vacmViewTreeFamilyEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpCommunityMIBObjects(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpCommunityEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+u_char *
+var_snmpTargetAddrExtEntry(struct variable * vp, 
+	oid* name, int * len, int exact, 
+	int * var_len);
+
+
+
+/* Recommended mib tables. If you edit these, be sure
+to correct the values of the corrosponding tokens above.*/
+
+/* MIB table for 'system' group */
+
+struct system_mib {
+	void  *	sysDescr;	/* 32 bit ptr */
+	oid  *	sysObjectID;	/* 32 bit ptr */
+	u_long	sysUpTime;
+	void  *	sysContact;	/* 32 bit ptr */
+	void  *	sysName;	/* 32 bit ptr */
+	void  *	sysLocation;	/* 32 bit ptr */
+	long  	sysServices;
+	u_long	sysORLastChange;
+};
+
+/* MIB table for 'sysOREntry' group */
+
+struct sysOREntry_mib {
+	long  	sysORIndex;
+	oid  *	sysORID;	/* 32 bit ptr */
+	void  *	sysORDescr;	/* 32 bit ptr */
+	u_long	sysORUpTime;
+};
+
+/* MIB table for 'interfaces' group */
+
+struct interfaces_mib {
+	long  	ifNumber;
+};
+
+/* MIB table for 'ifEntry' group */
+
+struct ifEntry_mib {
+	long  	ifIndex;
+	void  *	ifDescr;	/* 32 bit ptr */
+	long  	ifType;
+	long  	ifMtu;
+	u_long	ifSpeed;
+	void  *	ifPhysAddress;	/* 32 bit ptr */
+	long  	ifAdminStatus;
+	long  	ifOperStatus;
+	u_long	ifLastChange;
+	u_long	ifInOctets;
+	u_long	ifInUcastPkts;
+	u_long	ifInNUcastPkts;
+	u_long	ifInDiscards;
+	u_long	ifInErrors;
+	u_long	ifInUnknownProtos;
+	u_long	ifOutOctets;
+	u_long	ifOutUcastPkts;
+	u_long	ifOutNUcastPkts;
+	u_long	ifOutDiscards;
+	u_long	ifOutErrors;
+	u_long	ifOutQLen;
+	oid  *	ifSpecific;	/* 32 bit ptr */
+};
+
+/* MIB table for 'atEntry' group */
+
+struct atEntry_mib {
+	long  	atIfIndex;
+	void  *	atPhysAddress;	/* 32 bit ptr */
+	u_long	atNetAddress;
+};
+
+/* MIB table for 'ip' group */
+
+struct ip_mib {
+	long  	ipForwarding;
+	long  	ipDefaultTTL;
+	u_long	ipInReceives;
+	u_long	ipInHdrErrors;
+	u_long	ipInAddrErrors;
+	u_long	ipForwDatagrams;
+	u_long	ipInUnknownProtos;
+	u_long	ipInDiscards;
+	u_long	ipInDelivers;
+	u_long	ipOutRequests;
+	u_long	ipOutDiscards;
+	u_long	ipOutNoRoutes;
+	long  	ipReasmTimeout;
+	u_long	ipReasmReqds;
+	u_long	ipReasmOKs;
+	u_long	ipReasmFails;
+	u_long	ipFragOKs;
+	u_long	ipFragFails;
+	u_long	ipFragCreates;
+	u_long	ipRoutingDiscards;
+};
+
+/* MIB table for 'ipAddrEntry' group */
+
+struct ipAddrEntry_mib {
+	u_long	ipAdEntAddr;
+	long  	ipAdEntIfIndex;
+	u_long	ipAdEntNetMask;
+	long  	ipAdEntBcastAddr;
+	long  	ipAdEntReasmMaxSize;
+};
+
+/* MIB table for 'ipRouteEntry' group */
+
+struct ipRouteEntry_mib {
+	u_long	ipRouteDest;
+	long  	ipRouteIfIndex;
+	long  	ipRouteMetric1;
+	long  	ipRouteMetric2;
+	long  	ipRouteMetric3;
+	long  	ipRouteMetric4;
+	u_long	ipRouteNextHop;
+	long  	ipRouteType;
+	long  	ipRouteProto;
+	long  	ipRouteAge;
+	u_long	ipRouteMask;
+	long  	ipRouteMetric5;
+	oid  *	ipRouteInfo;	/* 32 bit ptr */
+};
+
+/* MIB table for 'ipNetToMediaEntry' group */
+
+struct ipNetToMediaEntry_mib {
+	long  	ipNetToMediaIfIndex;
+	void  *	ipNetToMediaPhysAddress;	/* 32 bit ptr */
+	u_long	ipNetToMediaNetAddress;
+	long  	ipNetToMediaType;
+};
+
+/* MIB table for 'icmp' group */
+
+struct icmp_mib {
+	u_long	icmpInMsgs;
+	u_long	icmpInErrors;
+	u_long	icmpInDestUnreachs;
+	u_long	icmpInTimeExcds;
+	u_long	icmpInParmProbs;
+	u_long	icmpInSrcQuenchs;
+	u_long	icmpInRedirects;
+	u_long	icmpInEchos;
+	u_long	icmpInEchoReps;
+	u_long	icmpInTimestamps;
+	u_long	icmpInTimestampReps;
+	u_long	icmpInAddrMasks;
+	u_long	icmpInAddrMaskReps;
+	u_long	icmpOutMsgs;
+	u_long	icmpOutErrors;
+	u_long	icmpOutDestUnreachs;
+	u_long	icmpOutTimeExcds;
+	u_long	icmpOutParmProbs;
+	u_long	icmpOutSrcQuenchs;
+	u_long	icmpOutRedirects;
+	u_long	icmpOutEchos;
+	u_long	icmpOutEchoReps;
+	u_long	icmpOutTimestamps;
+	u_long	icmpOutTimestampReps;
+	u_long	icmpOutAddrMasks;
+	u_long	icmpOutAddrMaskReps;
+};
+
+/* MIB table for 'tcp' group */
+
+struct tcp_mib {
+	long  	tcpRtoAlgorithm;
+	long  	tcpRtoMin;	/* UNITS:       "milliseconds"M */
+	long  	tcpRtoMax;	/* UNITS:       "milliseconds"M */
+	long  	tcpMaxConn;
+	u_long	tcpActiveOpens;
+	u_long	tcpPassiveOpens;
+	u_long	tcpAttemptFails;
+	u_long	tcpEstabResets;
+	u_long	tcpCurrEstab;
+	u_long	tcpInSegs;
+	u_long	tcpOutSegs;
+	u_long	tcpRetransSegs;
+	u_long	tcpInErrs;
+	u_long	tcpOutRsts;
+};
+
+/* MIB table for 'tcpConnEntry' group */
+
+struct tcpConnEntry_mib {
+	long  	tcpConnState;
+	u_long	tcpConnLocalAddress;
+	long  	tcpConnLocalPort;
+	u_long	tcpConnRemAddress;
+	long  	tcpConnRemPort;
+};
+
+/* MIB table for 'udp' group */
+
+struct udp_mib {
+	u_long	udpInDatagrams;
+	u_long	udpNoPorts;
+	u_long	udpInErrors;
+	u_long	udpOutDatagrams;
+};
+
+/* MIB table for 'udpEntry' group */
+
+struct udpEntry_mib {
+	u_long	udpLocalAddress;
+	long  	udpLocalPort;
+};
+
+/* MIB table for 'egp' group */
+
+struct egp_mib {
+	u_long	egpInMsgs;
+	u_long	egpInErrors;
+	u_long	egpOutMsgs;
+	u_long	egpOutErrors;
+	long  	egpAs;
+};
+
+/* MIB table for 'egpNeighEntry' group */
+
+struct egpNeighEntry_mib {
+	long  	egpNeighState;
+	u_long	egpNeighAddr;
+	long  	egpNeighAs;
+	u_long	egpNeighInMsgs;
+	u_long	egpNeighInErrs;
+	u_long	egpNeighOutMsgs;
+	u_long	egpNeighOutErrs;
+	u_long	egpNeighInErrMsgs;
+	u_long	egpNeighOutErrMsgs;
+	u_long	egpNeighStateUps;
+	u_long	egpNeighStateDowns;
+	long  	egpNeighIntervalHello;
+	long  	egpNeighIntervalPoll;
+	long  	egpNeighMode;
+	long  	egpNeighEventTrigger;
+};
+
+/* MIB table for 'snmp' group */
+
+struct snmp_mib {
+	u_long	snmpInPkts;
+	u_long	snmpOutPkts;
+	u_long	snmpInBadVersions;
+	u_long	snmpInBadCommunityNames;
+	u_long	snmpInBadCommunityUses;
+	u_long	snmpInASNParseErrs;
+	u_long	snmpInTooBigs;
+	u_long	snmpInNoSuchNames;
+	u_long	snmpInBadValues;
+	u_long	snmpInReadOnlys;
+	u_long	snmpInGenErrs;
+	u_long	snmpInTotalReqVars;
+	u_long	snmpInTotalSetVars;
+	u_long	snmpInGetRequests;
+	u_long	snmpInGetNexts;
+	u_long	snmpInSetRequests;
+	u_long	snmpInGetResponses;
+	u_long	snmpInTraps;
+	u_long	snmpOutTooBigs;
+	u_long	snmpOutNoSuchNames;
+	u_long	snmpOutBadValues;
+	u_long	snmpOutGenErrs;
+	u_long	snmpOutGetRequests;
+	u_long	snmpOutGetNexts;
+	u_long	snmpOutSetRequests;
+	u_long	snmpOutGetResponses;
+	u_long	snmpOutTraps;
+	long  	snmpEnableAuthenTraps;
+	u_long	snmpSilentDrops;
+	u_long	snmpProxyDrops;
+};
+
+/* MIB table for 'snmpTrap' group */
+
+struct snmpTrap_mib {
+	oid  *	snmpTrapOID;	/* 32 bit ptr */
+	oid  *	snmpTrapEnterprise;	/* 32 bit ptr */
+};
+
+/* MIB table for 'snmpSet' group */
+
+struct snmpSet_mib {
+	long  	snmpSetSerialNo;
+};
+
+/* MIB table for 'snmpEngine' group */
+
+struct snmpEngine_mib {
+	void  *	snmpEngineID;	/* 32 bit ptr */
+	long  	snmpEngineBoots;
+	long  	snmpEngineTime;	/* UNITS:        "seconds"M */
+	long  	snmpEngineMaxMessageSize;
+};
+
+/* MIB table for 'snmpMPDStats' group */
+
+struct snmpMPDStats_mib {
+	u_long	snmpUnknownSecurityModels;
+	u_long	snmpInvalidMsgs;
+	u_long	snmpUnknownPDUHandlers;
+};
+
+/* MIB table for 'snmpTargetObjects' group */
+
+struct snmpTargetObjects_mib {
+	long  	snmpTargetSpinLock;
+	u_long	snmpUnavailableContexts;
+	u_long	snmpUnknownContexts;
+};
+
+/* MIB table for 'snmpTargetAddrEntry' group */
+
+struct snmpTargetAddrEntry_mib {
+	void  *	snmpTargetAddrName;	/* 32 bit ptr */
+	oid  *	snmpTargetAddrTDomain;	/* 32 bit ptr */
+	void  *	snmpTargetAddrTAddress;	/* 32 bit ptr */
+	long  	snmpTargetAddrTimeout;
+	long  	snmpTargetAddrRetryCount;
+	void  *	snmpTargetAddrTagList;	/* 32 bit ptr */
+	void  *	snmpTargetAddrParams;	/* 32 bit ptr */
+	long  	snmpTargetAddrStorageType;
+	long  	snmpTargetAddrRowStatus;
+};
+
+/* MIB table for 'snmpTargetParamsEntry' group */
+
+struct snmpTargetParamsEntry_mib {
+	void  *	snmpTargetParamsName;	/* 32 bit ptr */
+	long  	snmpTargetParamsMPModel;
+	long  	snmpTargetParamsSecurityModel;
+	void  *	snmpTargetParamsSecurityName;	/* 32 bit ptr */
+	long  	snmpTargetParamsSecurityLevel;
+	long  	snmpTargetParamsStorageType;
+	long  	snmpTargetParamsRowStatus;
+};
+
+/* MIB table for 'snmpNotifyEntry' group */
+
+struct snmpNotifyEntry_mib {
+	void  *	snmpNotifyName;	/* 32 bit ptr */
+	void  *	snmpNotifyTag;	/* 32 bit ptr */
+	long  	snmpNotifyType;
+	long  	snmpNotifyStorageType;
+	long  	snmpNotifyRowStatus;
+};
+
+/* MIB table for 'snmpNotifyFilterProfileEntry' group */
+
+struct snmpNotifyFilterProfileEntry_mib {
+	void  *	snmpNotifyFilterProfileName;	/* 32 bit ptr */
+	long  	snmpNotifyFilterProfileStorType;
+	long  	snmpNotifyFilterProfileRowStatus;
+};
+
+/* MIB table for 'snmpNotifyFilterEntry' group */
+
+struct snmpNotifyFilterEntry_mib {
+	oid  *	snmpNotifyFilterSubtree;	/* 32 bit ptr */
+	void  *	snmpNotifyFilterMask;	/* 32 bit ptr */
+	long  	snmpNotifyFilterType;
+	long  	snmpNotifyFilterStorageType;
+	long  	snmpNotifyFilterRowStatus;
+};
+
+/* MIB table for 'usmStats' group */
+
+struct usmStats_mib {
+	u_long	usmStatsUnsupportedSecLevels;
+	u_long	usmStatsNotInTimeWindows;
+	u_long	usmStatsUnknownUserNames;
+	u_long	usmStatsUnknownEngineIDs;
+	u_long	usmStatsWrongDigests;
+	u_long	usmStatsDecryptionErrors;
+};
+
+/* MIB table for 'usmUser' group */
+
+struct usmUser_mib {
+	long  	usmUserSpinLock;
+};
+
+/* MIB table for 'usmUserEntry' group */
+
+struct usmUserEntry_mib {
+	void  *	usmUserEngineID;	/* 32 bit ptr */
+	void  *	usmUserName;	/* 32 bit ptr */
+	void  *	usmUserSecurityName;	/* 32 bit ptr */
+	oid  *	usmUserCloneFrom;	/* 32 bit ptr */
+	oid  *	usmUserAuthProtocol;	/* 32 bit ptr */
+	void  *	usmUserAuthKeyChange;	/* 32 bit ptr */
+	void  *	usmUserOwnAuthKeyChange;	/* 32 bit ptr */
+	oid  *	usmUserPrivProtocol;	/* 32 bit ptr */
+	void  *	usmUserPrivKeyChange;	/* 32 bit ptr */
+	void  *	usmUserOwnPrivKeyChange;	/* 32 bit ptr */
+	void  *	usmUserPublic;	/* 32 bit ptr */
+	long  	usmUserStorageType;
+	long  	usmUserStatus;
+};
+
+/* MIB table for 'vacmContextEntry' group */
+
+struct vacmContextEntry_mib {
+	void  *	vacmContextName;	/* 32 bit ptr */
+};
+
+/* MIB table for 'vacmSecurityToGroupEntry' group */
+
+struct vacmSecurityToGroupEntry_mib {
+	long  	vacmSecurityModel;
+	void  *	vacmSecurityName;	/* 32 bit ptr */
+	void  *	vacmGroupName;	/* 32 bit ptr */
+	long  	vacmSecurityToGroupStorageType;
+	long  	vacmSecurityToGroupStatus;
+};
+
+/* MIB table for 'vacmAccessEntry' group */
+
+struct vacmAccessEntry_mib {
+	void  *	vacmAccessContextPrefix;	/* 32 bit ptr */
+	long  	vacmAccessSecurityModel;
+	long  	vacmAccessSecurityLevel;
+	long  	vacmAccessContextMatch;
+	void  *	vacmAccessReadViewName;	/* 32 bit ptr */
+	void  *	vacmAccessWriteViewName;	/* 32 bit ptr */
+	void  *	vacmAccessNotifyViewName;	/* 32 bit ptr */
+	long  	vacmAccessStorageType;
+	long  	vacmAccessStatus;
+};
+
+/* MIB table for 'vacmMIBViews' group */
+
+struct vacmMIBViews_mib {
+	long  	vacmViewSpinLock;
+};
+
+/* MIB table for 'vacmViewTreeFamilyEntry' group */
+
+struct vacmViewTreeFamilyEntry_mib {
+	void  *	vacmViewTreeFamilyViewName;	/* 32 bit ptr */
+	oid  *	vacmViewTreeFamilySubtree;	/* 32 bit ptr */
+	void  *	vacmViewTreeFamilyMask;	/* 32 bit ptr */
+	long  	vacmViewTreeFamilyType;
+	long  	vacmViewTreeFamilyStorageType;
+	long  	vacmViewTreeFamilyStatus;
+};
+
+/* MIB table for 'snmpCommunityMIBObjects' group */
+
+struct snmpCommunityMIBObjects_mib {
+	u_long	snmpTrapAddress;
+	void  *	snmpTrapCommunity;	/* 32 bit ptr */
+};
+
+/* MIB table for 'snmpCommunityEntry' group */
+
+struct snmpCommunityEntry_mib {
+	void  *	snmpCommunityIndex;	/* 32 bit ptr */
+	void  *	snmpCommunityName;	/* 32 bit ptr */
+	void  *	snmpCommunitySecurityName;	/* 32 bit ptr */
+	void  *	snmpCommunityContextEngineID;	/* 32 bit ptr */
+	void  *	snmpCommunityContextName;	/* 32 bit ptr */
+	void  *	snmpCommunityTransportTag;	/* 32 bit ptr */
+	long  	snmpCommunityStorageType;
+	long  	snmpCommunityStatus;
+};
+
+/* MIB table for 'snmpTargetAddrExtEntry' group */
+
+/* This table augments the table snmpTargetAddrEntry */
+struct snmpTargetAddrExtEntry_mib {
+	struct	snmpTargetAddrEntry_mib *basetbl;	/* ptr to base table */
+	void  *	snmpTargetAddrTMask;	/* 32 bit ptr */
+	long  	snmpTargetAddrMMS;
+};
+
+/* Following is a List of new TEXTUAL CONVENTIONS defined
+   in the MIBs
+*/ 
+extern struct enumList en_TruthValue[] ;
+extern struct enumList en_RowStatus[] ;
+extern struct enumList en_StorageType[] ;
+extern struct enumList en_SnmpSecurityLevel[] ;
+#endif /* SNMP_VIE_H */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/snmpport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/snmpport.h
new file mode 100644
index 0000000..7e76f3c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/snmpport.h
@@ -0,0 +1,257 @@
+/*
+ * FILENAME: SNMPPORT.H
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: SNMPV1
+ *
+ * ROUTINES:
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* snmpport.h 
+ * Portions Copyright 1990, 1993 by NetPort Software. 
+ */
+
+#ifndef _SNMPPORT_H_
+#define  _SNMPPORT_H_   1
+
+
+/* includes for this port */
+#include "ipport.h"
+#include "libport.h"
+#include "socket.h"             /* for decl of struct sockaddr */
+
+/* options to trade off features for size: */
+#define ENABLE_SNMP_TRAPS    1  /* this SNMP can send traps */
+#define INICHE_TCPIP         1  /* SNMP will use InterNiche TCPIP stack */
+#define MIB_COUNTERS         1  /* instrument TCPIP stack */
+#define SNMP_32BIT_OID       1  /* Support parsing/building of 32-bit OIDs */
+#define SNMP_TEST_SP_TRAP    1  /* Test enterprise specific traps */
+#define SNMP_COUNTER64       1  /* support 64-bit datatypes */
+#define SNMP_SYSLOG          1  /* send syslog() msg for SETs, traps */
+
+#ifndef SNMP_SOCKETS
+#define PREBIND_AGENT   1   /* hardcode SNMP port into UDP */
+#endif
+
+
+#ifdef NOT_USED
+#endif
+
+/* If INCLUDE_SNMP is not defined, then SNMPv1 is not enabled in the 
+ * build. Hence we don't need to enable SNMPv1 Traps. This undef is 
+ * done to avoid the compilation errors resulting due to reference to 
+ * nvram parameters in snmpport.c 
+ */
+#ifndef INCLUDE_SNMP
+#ifdef ENABLE_SNMP_TRAPS
+#undef ENABLE_SNMP_TRAPS
+#endif
+#endif
+
+#ifndef DOS_TSR
+#define  SUBID_32BIT    1  /* 32 bit Object ID components */
+#endif   /* else default to 16 bits */
+
+
+#ifdef ENABLE_SNMP_TRAPS
+#define  SNMP_UDP_TRAPS     1  /* v1/v2c over UDP, see trap_out.c */
+#else   
+/* If traps are not enabled, then snmp_trap() does nothing */ 
+#define  snmp_trap 
+#endif
+
+#ifdef SUBID_32BIT
+/* most 32 bit CPUS will want 32 bit oid components: */
+#ifndef V3_OID_DEFINED
+typedef u_long   oid;
+#endif 
+#define  MAX_SUBID   0xFFFFFFFF
+#else    /* 16 bit sub IDs */
+/* this is for a 16 bit processor oid component: */
+typedef u_short   oid;
+#define  MAX_SUBID   0xFFFF
+#endif
+
+#ifdef  SNMP_32BIT_OID 
+typedef u_long oid32 ;
+#endif
+
+#ifdef SNMP_COUNTER64
+/* define the datatype to hold a 64-bit counter. 
+ * It can be done in a variety of ways (one 64bit value, 2 32bit values,
+ * 8 bytes, etc. Hence use a union to define it.
+ */
+
+typedef union counter64
+{
+   struct longlong
+   {
+      unsigned long h,l;  /* two 32bit values h is higher, l is lower */
+   }ll;
+   char s[8];             /* s0 is LSB, s7 is MSB */
+}Counter64;
+
+#endif /* SNMP_COUNTER64 */
+
+
+/* if you define MIB_COUNTERS, you need to provide the include file 
+ * which describes the MIB-2 SNMP groups counters: 
+ */
+#ifndef SNMPMIB_H_FILE /* if it is not already defined */
+#ifdef  INCLUDE_SNMPV3
+#define SNMPMIB_H_FILE "snmp_vie.h" /* define it */
+#else
+#define SNMPMIB_H_FILE "rfc1213_.h" /* define it */
+#endif
+#endif /* SNMPMIB_H_FILE */
+
+#ifdef MIB_COUNTERS
+extern struct variable;
+#include SNMPMIB_H_FILE 
+extern struct snmp_mib   SnmpMib;
+#endif
+
+#define  SNMP_PORT            161
+#define  SNMP_TRAP_PORT       162
+
+/* per-port local limitations */
+#define  MAX_NAME_LEN         64 /* max number of subid's in a objid */
+#define  MAX_OID_LEN          64 /* max length in bytes of an encoded oid */
+#define  MAX_COMMUNITY_SIZE   32 /* max chars in a community string */
+
+
+#ifdef ENABLE_SNMP_TRAPS
+#define  MAX_TRAP_TARGETS     3  /* max number of trap target info slots */
+#define  NETPORT_TEST_TRAP    80
+#endif
+
+/* Companies porting this code should get their own number from iana.org ! */
+#define  ENTERPRISE     18868    /* InterNiche Tech. enterprise number */
+
+
+#ifndef oidcpy
+#define  oidcpy(dest,src,len) MEMCPY((char*)dest,(char*)src,((int)(len)*sizeof(oid)))
+#endif
+
+#ifndef ntohs
+#define  ntohl(l) lswap(l) /* for intel 8086 systems */
+#define  ntohs(w) bswap(w)
+#endif
+
+#define  MIB1  1, 3, 6, 1, 2, 1     /* standard mib Object Id, from mib.h */
+#define  MIB2  1, 3, 6, 1, 2, 1     /* standard mib-II Object Id, from mib.h */
+
+#define  SYS_STRING_MAX    256      /* max length of sys group strings */
+
+#ifdef DOS_TSR
+#define  SNMPSIZ     500   /* MAX size of an snmp packet */
+#else
+#define  SNMPSIZ     1400  /* MAX size of an snmp packet */
+#endif
+
+extern   u_char   snmpbuf[SNMPSIZ]; /* global buffer for packet building */
+
+/* map Berkeley-ish bcopy call to Iniche macro: */
+#ifndef bcopy
+#define  bcopy(src,  dest, len)     MEMCPY(dest,   src,  len)
+#endif
+
+/* omit error handler from DOS TSR */
+#ifdef DOS_TSR
+#define  SNMPERROR(msg);   ;  /* map to no-op */
+#else
+int    SNMPERROR(char*);
+extern   char *   snmp_err_text;    /* Set to non-null by ERROR() */
+#endif
+
+
+/* SNMP needs a mechanism to find the agent's IP address. ip_mymach() 
+ * (MYMACHine) should return the IP address of the agent relative to 
+ * a passed IP address. For single homed agents, this will be the IP 
+ * address of the sole interface. For multi-home, some coding may be
+ * required.
+ */
+#ifdef MINI_IP
+#include "netbuf.h"           /* needed for net.h */
+#include "net.h"              /* needed for defn of "struct net" */
+extern struct net * m_netp;   /* needed for m_netp */
+#define ip_mymach(addr)  (m_netp->n_ipaddr)
+#else
+u_long  ip_mymach(u_long);    /* return 0L if IPX trap */
+#endif
+
+
+
+extern   char  sys_descr[SYS_STRING_MAX]; /* define in application */
+
+
+/* The SNMP_ENTRY macro is used to compile the external SNMP entry 
+points with special code needs. */
+/* #define SNMP_ENTRY loadds */
+/* #define SNMP_ENTRY */
+
+
+#define  far   /* define away intel segment/model support */
+
+/* macro to force SNMP entry points to do correct segment setup. This 
+ * was implemented to handle builds on intel x86 CPUs where we want 
+ * to use a data segment other then the default for SNMP data due to 
+ * the 64K limit and potentially large size of variables[] 
+ */
+/* Intel flavor */
+/* #define SNMP_ENTRY __far __loadds    */
+/* default */
+#define  SNMP_ENTRY
+
+/* SNMP Agent related non-volatile parameters. Please see nvparms.h
+ * and nvparms.c regarding the usage of the following structure.
+ */
+#ifdef INCLUDE_NVPARMS
+#ifdef INCLUDE_SNMP
+struct snmp_nvparam
+{
+   /* SNMP agent stuff: */
+   char     getcomm[MAX_NVSTRING];     /* get community string for our agent */
+   char     setcomm[MAX_NVSTRING];     /* set community string for our agent */
+   char     sysContact[MAX_NVSTRING];  /* setable mib2 sysGroup strings */
+   char     sysName[MAX_NVSTRING];     /* MIB-2 sysName */
+   char     sysLocation[MAX_NVSTRING]; /* MIB-2 sysLocation */
+   struct sockaddr trapTarget1;        /* IP address to send SNMP traps to. */
+   char     trapcomm1[MAX_NVSTRING];   /* community for trapTarget1 */
+};
+
+extern struct snmp_nvparam snmp_nvparms;
+#endif /* INCLUDE_SNMP */
+#endif /* INCLUDE_NVPARMS */
+
+extern char* print46_addr(struct sockaddr *ipaddr);
+ip_addr ip_myaddr(struct sockaddr *addr);
+extern int snmp_send_trap(u_char * data, int len, struct sockaddr * addr);
+
+
+/* Define SNMP_LOGOID and SNMP_LOGTRAP - funcs used to send syslog msgs.
+ * If SNMP_SYSLOG is enabled, map them to the corresponding functions
+ * Else make them no-ops.
+ */
+#ifdef SNMP_SYSLOG
+int snmp_logtrap(int type, char * msg);
+int snmp_logoid(char *community, oid * var_name, unsigned var_name_len, 
+   long err, u_char * var_val, u_char valuetype);
+#define SNMP_LOGOID     snmp_logoid
+#define SNMP_LOGTRAP    snmp_logtrap
+#else
+#define SNMP_LOGOID
+#define SNMP_LOGTRAP
+#endif
+
+
+#endif   /* _SNMPPORT_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/sockcall.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/sockcall.h
new file mode 100644
index 0000000..2021f53
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/sockcall.h
@@ -0,0 +1,123 @@
+/*
+ * FILENAME: sockcall.h
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * UNIX-ish Sockets library definitions and entry points. 
+ */
+
+#ifndef _SOCKCALL_H
+#define  _SOCKCALL_H 1
+
+#define  SYS_SOCKETNULL -1    /* error return from sys_socket. */
+#define  INVALID_SOCKET -1    /* WINsock-ish synonym for SYS_SOCKETNULL */
+#define  SOCKET_ERROR   -1    /* error return from send(), sendto(), et.al. */
+#define  SOL_SOCKET     -1    /* compatability parm for set/get sockopt */
+
+/* t_shutdown "how" parameter values */
+#ifndef SHUT_RD
+#define SHUT_RD         0     /* shutdown "read" half */
+#define SHUT_WR         1     /* shutdown "write" half */
+#define SHUT_RDWR       2     /* shutdown both "read" and "write" */
+#endif
+
+
+extern   long  t_socket (int, int, int);
+extern   int   t_bind (long, struct sockaddr *, int);
+extern   int   t_listen (long, int);
+extern   long  t_accept (long, struct sockaddr *, int *);
+extern   int   t_connect (long, struct sockaddr *, int);
+extern   int   t_getpeername (long, struct sockaddr *, int * addrlen);
+extern   int   t_getsockname (long, struct sockaddr *, int * addrlen);
+extern   int   t_setsockopt (long sock, int level, int op, void * data, int dlen);
+extern   int   t_getsockopt (long sock, int level, int op, void * data, int dlen);
+extern   int   t_recv (long, char *, int, int);
+extern   int   t_send (long, char *, int, int);
+extern   int   t_recvfrom (long s, char * buf, int len, int flags, struct sockaddr *, int*);
+extern   int   t_sendto (long s, char * buf, int len, int flags, struct sockaddr *, int);
+extern   int   t_shutdown (long, int);
+extern   int   t_socketclose (long);
+extern   int   t_errno(long s);
+
+extern   char * so_perror(int);  /* return an error string for a socket error */
+
+/* define a macro test for validating a passed socket */
+
+#ifndef SOC_CHECK    /* ports may replace this test */
+#define  SOC_RANGE(so)  /* null - this version doesn't need range setup */
+#define SOC_CHECK(so) \
+   {  struct socket * tmp; \
+      for(tmp = (struct socket *)(&soq); tmp; tmp = tmp->next) \
+      {  if(tmp == so) break; } \
+      if(tmp != so) \
+      { dtrap(); \
+         return SOCKET_ERROR; \
+      } \
+    }
+#endif   /* undefined SOC_CHECK */
+
+#ifdef SO_SELECT
+
+/*
+ * Altera Niche Stack modifcation 12-Feb-2008 (jrk):
+ * Niche Stack indicates it should be built with _POSIX_SOURCE
+ * defined, which prevents any collision between Niche Stack's fd_set
+ * implementation below and newlib. However, this conflicts
+ * with other Nios embedded source that depends on these definitions
+ * in newlib. The following will override the newlib implementation
+ * of fd_set for this object.
+ */
+#ifdef ALT_INICHE
+  #include "sys/types.h"
+  #undef fd_set
+#endif /* ALT_INICHE */
+
+/* the definitions to support the select() function. These are about 
+ * as UNIX-like as we can make 'em on embedded code. They are also 
+ * fairly compatable with WinSock's select() definitions.
+ */
+
+typedef struct   /* the select socket array manager */
+{ 
+   unsigned fd_count;               /* how many are SET? */
+   long     fd_array[FD_SETSIZE];   /* an array of SOCKETs */
+} fd_set;
+
+/* our select call - note the traditional "width" parameter is absent */
+int t_select(fd_set * in, fd_set * out, fd_set * ev, long tmo_seconds);
+
+/* Select-related functions are calls (not macros) to save space */
+#undef FD_ZERO
+#undef FD_CLR
+#undef FD_SET
+#undef FD_ISSET
+
+#define  FD_ZERO(set)         (((fd_set *)(set))->fd_count = 0)
+#define  FD_CLR(so, set)       ifd_clr((long)(so), (fd_set *)(set))
+#define  FD_SET(so, set)       ifd_set((long)(so), (fd_set *)(set))
+#define  FD_ISSET(so, set)     ifd_isset((long)(so), (fd_set *)(set))
+/* additional functionality */
+#define  FD_GET(i, set)       ifd_get((int)(i), (fd_set *)(set))
+#define  FD_COUNT(set)        (((fd_set *)(set))->fd_count)
+
+void ifd_clr(long so, fd_set *set);
+void ifd_set(long so, fd_set *set);
+int  ifd_isset(long so, fd_set *set);
+long ifd_get(unsigned i, fd_set *set);
+
+#endif   /* SO_SELECT */
+
+#endif   /* _SOCKCALL_H */
+
+/* end of file sockcall.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/socket.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/socket.h
new file mode 100644
index 0000000..273f382
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/socket.h
@@ -0,0 +1,201 @@
+/*
+ * FILENAME: socket.h
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef SOCKET_H
+#define  SOCKET_H 1
+
+/*
+ * Types
+ */
+#define     SOCK_STREAM    1     /* stream socket */
+#define     SOCK_DGRAM     2     /* datagram socket */
+#define     SOCK_RAW       3     /* raw-protocol interface */
+
+#ifndef NPPORT
+#define     SOCK_RDM       4     /* reliably-delivered message */
+#define     SOCK_SEQPACKET 5     /* sequenced packet stream */
+#endif   /* NPPORT*/
+
+/*
+ * Option flags per-socket.
+ */
+#define     SO_DEBUG       0x00001     /* turn on debugging info recording */
+#define     SO_ACCEPTCONN  0x00002     /* socket has had listen() */
+#define     SO_REUSEADDR   0x00004     /* allow local address reuse */
+#define     SO_KEEPALIVE   0x00008     /* keep connections alive */
+#define     SO_DONTROUTE   0x00010     /* just use interface addresses */
+#define     SO_BROADCAST   0x00020     /* permit sending of broadcast msgs */
+#define     SO_USELOOPBACK 0x00040     /* bypass hardware when possible */
+#define     SO_LINGER      0x00080     /* linger on close if data present */
+#define     SO_OOBINLINE   0x00100     /* leave received OOB data in line */
+#define     SO_TCPSACK     0x00200     /* Allow TCP SACK (Selective acknowledgment) */
+#define     SO_WINSCALE    0x00400     /* Set scaling window option */ 
+#define     SO_TIMESTAMP   0x00800     /* Set TCP timestamp option */ 
+#define     SO_BIGCWND     0x01000     /* Large initial TCP Congenstion window */ 
+#define     SO_HDRINCL     0x02000     /* user access to IP hdr for SOCK_RAW */
+#define     SO_NOSLOWSTART 0x04000     /* suppress slowstart on this socket */
+#define     SO_FULLMSS     0x08000     /* force packets to all be MAX size */
+
+extern   unshort socket_defaults;      /* default so_options fo new sockets */
+
+/* for compatability with second-rate stacks: */
+#define SO_EXPEDITE     SO_NOSLOWSTART
+#define SO_THROUGHPUT   SO_FULLMSS
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define  SO_SNDBUF      0x1001      /* send buffer size */
+#define  SO_RCVBUF      0x1002      /* receive buffer size */
+#define  SO_SNDLOWAT    0x1003      /* send low-water mark */
+#define  SO_RCVLOWAT    0x1004      /* receive low-water mark */
+#define  SO_SNDTIMEO    0x1005      /* send timeout */
+#define  SO_RCVTIMEO    0x1006      /* receive timeout */
+#define  SO_ERROR       0x1007      /* get error status and clear */
+#define  SO_TYPE        0x1008      /* get socket type */
+#define  SO_HOPCNT      0x1009      /* Hop count to get to dst   */
+#define  SO_MAXMSG      0x1010      /* get TCP_MSS (max segment size) */
+
+/* ...And some netport additions to setsockopt: */
+#define  SO_RXDATA      0x1011      /* get count of bytes in sb_rcv */
+#define  SO_TXDATA      0x1012      /* get count of bytes in sb_snd */
+#define  SO_MYADDR      0x1013      /* return my IP address */
+#define  SO_NBIO        0x1014      /* set socket into NON-blocking mode */
+#define  SO_BIO         0x1015      /* set socket into blocking mode */
+#define  SO_NONBLOCK    0x1016      /* set/get blocking mode via optval param */
+#define  SO_CALLBACK    0x1017      /* set/get zero_copy callback routine */
+
+/*
+ * TCP User-settable options (used with setsockopt).
+ * TCP-specific socket options use the 0x2000 number space.
+ */
+
+#define  TCP_ACKDELAYTIME 0x2001    /* Set time for delayed acks */
+#define  TCP_NOACKDELAY   0x2002    /* suppress delayed ACKs */
+#define  TCP_MAXSEG       0x2003    /* set maximum segment size */
+#define  TCP_NODELAY      0x2004    /* Disable Nagle Algorithm */
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct   linger
+{
+   int   l_onoff;    /* option on/off */
+   int   l_linger;   /* linger time */
+};
+
+
+/*
+ * Structure used by kernel to store most
+ * addresses.
+ */
+struct sockaddr
+{
+   u_short     sa_family;     /* address family */
+#ifdef IP_V6   /* V6 only or dual stacks */
+   char     sa_data[32];      /* big enough for unpacked sockaddr_in6 */
+#else          /* Ancient IPv4 only version */
+   char     sa_data[14];      /* up to 14 bytes of direct address */
+#endif
+};
+
+/*
+ * Structure used by kernel to pass protocol
+ * information in raw sockets.
+ */
+struct sockproto
+{
+   u_short     sp_family;     /* address family */
+   u_short     sp_protocol;   /* protocol */
+};
+
+/* Support for Large initial congestion window */
+#ifdef TCP_BIGCWND
+extern   int      use_default_cwnd;    /* Flag to use this on all sockets */
+extern   u_long   default_cwnd;        /* initial cwnd value to use */
+#endif   /* TCP_BIGCWND */
+
+/*
+ * Protocol families, same as address families for now.
+ */
+#define  PF_UNSPEC   AF_UNSPEC
+#define  PF_UNIX     AF_UNIX
+#define  PF_INET     AF_INET
+#define  PF_IMPLINK  AF_IMPLINK
+#define  PF_PUP      AF_PUP
+#define  PF_CHAOS    AF_CHAOS
+#define  PF_NS       AF_NS
+#define  PF_NBS      AF_NBS
+#define  PF_ECMA     AF_ECMA
+#define  PF_DATAKIT  AF_DATAKIT
+#define  PF_CCITT    AF_CCITT
+#define  PF_SNA      AF_SNA
+#define  PF_DECnet   AF_DECnet
+#define  PF_DLI      AF_DLI
+#define  PF_LAT      AF_LAT
+#define  PF_HYLINK   AF_HYLINK
+#define  PF_APPLETALK   AF_APPLETALK
+
+
+/*
+ * Maximum queue length specifiable by listen.
+ */
+#define     SOMAXCONN   5
+
+#define     MSG_OOB        0x1      /* process out-of-band data */
+#define     MSG_PEEK       0x2      /* peek at incoming message */
+#define     MSG_DONTROUTE  0x4      /* send without using routing tables */
+#define     MSG_NEWPIPE    0x8      /* New pipe for recvfrom call   */
+#define     MSG_EOR        0x10     /* data completes record */
+#define     MSG_DONTWAIT   0x20     /* this message should be nonblocking */
+
+/* utility functions defined in misclib\parseip.c */
+extern int inet46_addr(char *str, struct sockaddr *address); 
+extern void inet_setport(struct sockaddr *addr,int port);
+
+#endif   /* SOCKET_H */
+
+/* end of file socket.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/socket6.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/socket6.h
new file mode 100644
index 0000000..c996d85
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/socket6.h
@@ -0,0 +1,87 @@
+/*
+ * FILENAME: socket6.h
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Socket definitions for IP version 6, as defined by RFC-2133 and RFC-2292
+ *
+ * MODULE: IP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef _SOCKET6_H_
+#define _SOCKET6_H_ 1
+
+#include "ip6.h"
+#include "icmp6.h"
+#include "ip6mibs.h"
+
+
+/* Mapping of Interniche types to the UNIXy types used in the RFC.
+ * Comment these out if they conflict with other headers in your system.
+ */
+#define uint32_t  u_long
+#define size_t    unsigned
+
+
+
+#define INET_ADDRSTRLEN    16    /* length of printfed IPv4 addr */
+#define INET6_ADDRSTRLEN   46    /* max length of printed IPv6 addr */
+
+/* map posix types form the rfc to Iniche types */
+
+#define u_int16m_t   unshort
+#define u_int32m_t   u_long
+
+
+struct sockaddr_in6
+{
+   u_short        sin6_family;   /* AF_INET6 */
+   u_short        sin6_port;     /* transport layer port # */
+   u_long         sin6_flowinfo; /* IPv6 flow information */
+   ip6_addr       sin6_addr;     /* IPv6 address */
+};
+
+/* Use the unspecifed address as the wildcard IP address */
+#define in6addr_any ip6unspecified
+
+/* convert printable string to binary address */
+int   inet_pton(int af, const char * src, void * dst);
+
+/* convert binary address tp printable string */
+const char * inet_ntop(int af, const void * src, char * dst, size_t size);
+
+
+/* get data for prepending IP header (or something) onto mbuf */
+struct mbuf *  mbuf_prepend(struct mbuf * m, int size);
+
+
+/* ICMPv6 setsockopt filter structure and macros (RFC-2292) */
+
+struct icmp6_filter {
+  uint32_t  icmp6_filt[8];  /* 8*32 = 256 bits */
+};
+
+#define ICMP6_FILTER_WILLPASS(type, filterp) \
+    ((((filterp)->icmp6_filt[(type) >> 5]) & (1 << ((type) & 31))) != 0)
+#define ICMP6_FILTER_WILLBLOCK(type, filterp) \
+    ((((filterp)->icmp6_filt[(type) >> 5]) & (1 << ((type) & 31))) == 0)
+#define ICMP6_FILTER_SETPASS(type, filterp) \
+    ((((filterp)->icmp6_filt[(type) >> 5]) |=  (1 << ((type) & 31))))
+#define ICMP6_FILTER_SETBLOCK(type, filterp) \
+    ((((filterp)->icmp6_filt[(type) >> 5]) &= ~(1 << ((type) & 31))))
+#define ICMP6_FILTER_SETPASSALL(filterp) \
+    memset((filterp), 0xFF, sizeof(struct icmp6_filter))
+#define ICMP6_FILTER_SETBLOCKALL(filterp) \
+    memset((filterp), 0, sizeof(struct icmp6_filter))
+
+/* check if this addr can go out some IF */
+int ip6_addrcango(struct sockaddr_in6 * dest);
+
+
+#endif   /* _SOCKET6_H_*/
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/sockvar.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/sockvar.h
new file mode 100644
index 0000000..435b8a7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/sockvar.h
@@ -0,0 +1,249 @@
+/*
+ * FILENAME: sockvar.h
+ *
+ * Copyright 1997-2003 by InterNiche Technologies Inc. All rights reserved.
+ *
+ * Kernel structure per socket.
+ * Contains send and receive buffer queues,
+ * handle on protocol and pointer to protocol
+ * private data and error information.
+ *
+ * MODULE: H
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef SOCKVAR_H
+#define  SOCKVAR_H   1
+
+/*
+ * Variables for socket buffering.
+ */
+struct   sockbuf
+{
+   u_int    sb_cc;      /* actual chars in buffer */
+   u_int    sb_hiwat;   /* max actual char count */
+   u_int    sb_mbcnt;   /* chars of mbufs used */
+   u_int    sb_mbmax;   /* max chars of mbufs to use */
+   u_int    sb_lowat;   /* low water mark (not used yet)*/
+   u_int    sb_sel;     /* support select later? -JB- */
+   struct mbuf * sb_mb; /* the   mbuf  chain */
+   short    sb_flags;   /* flags, see below */
+   short    sb_timeo;   /* Snd/Rcv timeout */
+};
+
+struct socket
+{
+   struct   socket * next; /* ptr to next socket */
+   struct   inpcb * so_pcb;      /* protocol control block */
+   struct   protosw * so_proto;  /* protocol handle */
+#ifdef TCP_ZEROCOPY
+   int   (*rx_upcall) __P ((struct socket * so, void * pkt, int error));
+#endif
+#ifdef IP_MULTICAST
+   struct ip_moptions * inp_moptions;
+#endif   /* IP_MULTICAST */
+   u_long   so_options;    /* from socket call, see socket.h*/
+   int      so_domain;     /* AF_INET or AF_INET6 */
+   int      so_error;      /* error affecting connection */
+   int      so_req;        /* request for pass to tcp_usrreq() */
+   short    so_linger;     /* time to linger while closing */
+   short    so_state;      /* internal state flags SS_*, below */
+   short    so_timeo;      /* connection timeout */
+   char     so_type;       /* generic type, see socket.h   */
+   char     so_hopcnt;     /* Number of hops to dst   */
+
+   /*
+    * Variables for socket buffering.
+    */
+   struct   sockbuf  so_rcv,  so_snd;
+   u_int    so_oobmark;       /* chars to oob mark */
+
+   /*
+    * Variables for connection queueing.
+    * Socket where accepts occur is so_head in all subsidiary sockets.
+    * If so_head is 0, socket is not related to an accept.
+    * For head socket so_q0 queues partially completed connections,
+    * while so_q is a queue of connections ready to be accepted.
+    * If a connection is aborted and it has so_head set, then
+    * it has to be pulled out of either so_q0 or so_q.
+    * We allow connections to queue up based on current queue lengths
+    * and limit on number of queued connections for this socket.
+    */
+   struct   socket * so_head; /* back pointer to accept socket */
+   struct   socket * so_q0;   /* queue of partial connections */
+   struct   socket * so_q;    /* queue of incoming connections */
+   char     so_q0len;         /* partials on so_q0 */
+   char     so_qlen;          /* number of connections on so_q */
+   char     so_qlimit;        /* max number queued connections */
+   struct   ip_socopts * so_optsPack; /* pointer to options, to be given to PACKET */
+   /*
+    * Altera Niche Stack Nios port modification:
+    * Declare 'owner' as TK_OBJECT_REF as it is a subroutine
+    * instead of simply a void * -- to fix build warning
+    */
+   TK_OBJECT_REF(owner);      /* owning task id for tasking-based systems
+                               * (used only if SOCK_MAP_EVENTS is defined) */      
+};
+
+extern   queue soq;  /* Socket queue */
+
+/* sockbuf defines */
+#define  SB_MAX      (16*1024)   /* max chars in sockbuf */
+#define  SB_LOCK     0x01     /* lock on data queue (so_rcv only) */
+#define  SB_WANT     0x02     /* someone is waiting to lock */
+#define  SB_WAIT     0x04     /* someone is waiting for data/space */
+#define  SB_SEL      0x08     /* buffer is selected */
+#define  SB_COLL     0x10     /* collision selecting */
+#define  SB_NOINTR   0x40     /* operations not interruptible */
+#define  SB_MBCOMP   0x80     /* can compress mbufs */
+
+/*
+ * Socket state bits.
+ */
+#define  SS_NOFDREF           0x0001   /* no file table ref any more */
+#define  SS_ISCONNECTED       0x0002   /* socket connected to a peer */
+#define  SS_ISCONNECTING      0x0004   /* in process of connecting to peer */
+#define  SS_ISDISCONNECTING   0x0008   /*  in process  of disconnecting */
+#define  SS_CANTSENDMORE      0x0010   /* can't send more data to peer */
+#define  SS_CANTRCVMORE       0x0020   /* can't receive more data from peer */
+#define  SS_RCVATMARK         0x0040   /* at mark on input */
+#define  SS_PRIV              0x0080   /* privileged for broadcast, raw... */
+#define  SS_NBIO              0x0100   /* non-blocking ops */
+#define  SS_ASYNC             0x0200   /* async i/o notify */
+#define  SS_UPCALLED          0x0400   /* zerocopy data has been upcalled (for select) */
+#define  SS_INUPCALL          0x0800   /* inside zerocopy upcall (reentry guard) */
+#define  SS_UPCFIN            0x1000   /* inside zerocopy upcall (reentry guard) */
+#define  SS_WASCONNECTING     0x2000   /* SS_ISCONNECTING w/possible pending error */
+
+/*
+ * Macros for sockets and socket buffering.
+ */
+
+/* how much space is there in a socket buffer (so->so_snd or so->so_rcv) */
+#define sbspace(sb) ((((int)(sb)->sb_hiwat - (int)(sb)->sb_cc) >= 0) \
+     ? ((sb)->sb_hiwat -(sb)->sb_cc): 0 )
+
+/* do we have to send all at once on a socket? */
+#define   sosendallatonce(so) \
+    ((so)->so_proto->pr_flags & PR_ATOMIC)
+
+/* adjust counters in sb reflecting allocation of m */
+#define   sballoc(sb, m) { \
+   (sb)->sb_cc += (m)->m_len; \
+}
+/* adjust counters in sb reflecting freeing of m */
+#define   sbfree(sb, m) { \
+   (sb)->sb_cc -= (m)->m_len; \
+}
+/* set lock on sockbuf sb */
+#define sblock(sb) { \
+   while ((sb)->sb_flags & SB_LOCK) {          \
+      tcp_sleep ((char *)&(sb)->sb_flags);       \
+   }                      \
+   (sb)->sb_flags |= SB_LOCK;             \
+}
+/* release lock on sockbuf sb */
+#define   sbunlock(sb) {                   \
+   (sb)->sb_flags &= ~SB_LOCK;             \
+   tcp_wakeup((char *)&(sb)->sb_flags);       \
+}
+#define  sorwakeup(so)     sowakeup((so), &(so)->so_rcv)
+#define  sowwakeup(so)     sowakeup((so), &(so)->so_snd)
+#define  sowakeup(so,sb)   sbwakeup ((so), sb)
+
+/*
+ * Function proto-types for ANSI C
+ */
+extern   void  soisconnecting __P ((struct socket *));
+extern   void  soisconnected  __P ((struct socket *));
+extern   void  soisdisconnecting __P ((struct socket *));
+extern   void  soisdisconnected  __P ((struct socket *));
+extern   struct socket *   sonewconn   __P ((struct socket *));
+extern   void  soqinsque   __P ((struct socket *, struct socket *, int));
+extern   int   soqremque   __P ((struct socket *, int));
+extern   void  socantsendmore __P ((struct socket *));
+extern   void  socantrcvmore  __P ((struct socket *));
+extern   int   sbreserve   __P ((struct sockbuf *, unsigned long));
+extern   void  sbwakeup __P ((struct socket *, struct sockbuf *));
+extern   void  sbrelease   __P ((struct sockbuf *));
+extern   void  sbselqueue  __P ((struct sockbuf *));
+extern   void  sbappend __P ((struct sockbuf * sb, struct mbuf *));
+extern   void  sbappendrecord __P ((struct sockbuf * sb, struct mbuf *));
+extern   int   sbappendaddr   __P ((struct sockbuf *, struct sockaddr *, struct mbuf *));
+extern   void  sbflush  __P ((struct sockbuf *));
+extern   void  sbdrop   __P ((struct sockbuf *, int));
+extern   void  sbdropend   __P ((struct sockbuf *, struct mbuf *));
+extern   void  sbdroprecord   __P ((struct sockbuf *));
+#ifndef sowakeup
+extern   void  sowakeup __P ((struct socket *, struct sockbuf *));
+#endif
+extern   void  sbwait   __P ((struct sockbuf *));
+
+extern   void  insque   __P ((void *, void *));
+extern   void  remque   __P ((void *));
+
+/*
+ * socket.c
+ */
+extern   struct socket *   socreate __P ((int, int, int));
+extern   int   sobind   __P ((struct socket *, struct mbuf *));
+extern   int   solisten __P ((struct socket *, int));
+extern   void  sofree   __P ((struct socket *));
+extern   int   soabort  __P ((struct socket *));
+extern   int   soaccept __P ((struct socket *, struct mbuf *));
+extern   int   soconnect   __P ((struct socket *, struct mbuf *));
+extern   int   sodisconnect   __P ((struct socket *));
+extern   void  sorflush __P ((struct socket *));
+extern   int   sosetopt __P ((struct socket *, int, void *));
+extern   int   sogetopt __P ((struct socket *, int, void *));
+extern   void  sohasoutofband __P ((struct socket *));
+
+
+/* more socket.c and socket2.c */
+
+int   soreserve(struct socket * so, u_long sndcc, u_long rcvcc);
+int   sosend(struct socket * so, struct mbuf * nam, 
+            char * data, int * datalen, int flags);
+int   soreceive(struct socket * so, struct mbuf ** nam, 
+            char * data, int * datalen, int   flags);
+int   soshutdown(struct socket * so, int how);
+int   soclose(struct socket * so);
+void  sbcompress(struct sockbuf *, struct mbuf *, struct mbuf *);
+
+#endif   /* SOCKVAR_H */
+
+/* end of file sockvar.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/syslog.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/syslog.h
new file mode 100644
index 0000000..dfc6225
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/syslog.h
@@ -0,0 +1,162 @@
+/*
+ * FILENAME: syslog.h
+ *
+ * Copyright 2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Definitions syslog client
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _SYS_SYSLOG_H_
+#define _SYS_SYSLOG_H_
+
+#include "tcpapp.h"   /* for definition for sockaddr */
+
+#define _PATH_LOG     "sys.log"     /* name of log file */
+#define LOG_PORT      514           /* port of syslog server */
+#define LOG_IPADDR1   "10.0.0.20"   /* ipaddress of syslog server */
+#define LOG_IPADDR2   "fe80::20c:6eff:fe6c:8e46"  /* syslogd IP address */
+#define LOG_CRLF      "\r\n"        /* CRLF for the file system */
+#define LOG_YEAR      2004          /* start date(year) for the stack */
+#define LOG_MONTH     9             /* start date(month) for the stack */
+#define LOG_DAY       2             /* start date(day) for the stack */
+#define LOG_MAXSVRS   3            /* max number of default syslogds */
+
+/*
+ * priorities/facilities are encoded into a single 32-bit quantity, where the
+ * bottom 3 bits are the priority (0-7) and the top 28 bits are the facility
+ * (0-big number).  Both the priorities and the facilities map roughly
+ * one-to-one to strings in the syslogd(8) source code.  This mapping is
+ * included in this file.
+ *
+ * priorities (these are ordered)
+ */
+#define LOG_EMERG     0     /* system is unusable */
+#define LOG_ALERT     1     /* action must be taken immediately */
+#define LOG_CRIT      2     /* critical conditions */
+#define LOG_ERR       3     /* error conditions */
+#define LOG_WARNING   4     /* warning conditions */
+#define LOG_NOTICE    5     /* normal but significant condition */
+#define LOG_INFO      6     /* informational */
+#define LOG_DEBUG     7     /* debug-level messages */
+#define SEVERITY_MAX  8     /* total number of severities */
+
+#define LOG_PRIMASK   0x07  /* mask to extract priority part (internal) */
+/* extract priority */
+#define LOG_PRI(p)            ((p) & LOG_PRIMASK)
+#define LOG_MAKEPRI(fac, pri) ((fac) | (pri))
+
+
+/* facility codes */
+/* Facility #10 clashes in DEC UNIX, where                */
+/* it's defined as LOG_MEGASAFE for AdvFS  event logging. */
+#define LOG_KERN     (0<<3)   /* kernel messages */
+#define LOG_USER     (1<<3)   /* random user-level messages */
+#define LOG_MAIL     (2<<3)   /* mail system */
+#define LOG_DAEMON   (3<<3)   /* system daemons */
+#define LOG_AUTH     (4<<3)   /* authorization messages */
+#define LOG_SYSLOG   (5<<3)   /* messages generated internally by syslogd */
+#define LOG_LPR      (6<<3)   /* line printer subsystem */
+#define LOG_NEWS     (7<<3)   /* network news subsystem */
+#define LOG_UUCP     (8<<3)   /* UUCP subsystem */
+#define LOG_CRON     (9<<3)   /* clock daemon */
+#define LOG_AUTHPRIV (10<<3)  /* authorization messages (private) */
+#define LOG_FTP      (11<<3)  /* ftp daemon */
+#define LOG_NTP      (12<<3)  /* NTP subsystem */
+#define LOG_SECURITY (13<<3)  /* security subsystems (firewalling, etc.) */
+#define LOG_CONSOLE  (14<<3)  /* /dev/console output */
+/* other codes through 15 reserved for system use */
+#define LOG_LOCAL0   (16<<3)  /* reserved for local use */
+#define LOG_LOCAL1   (17<<3)  /* reserved for local use */
+#define LOG_LOCAL2   (18<<3)  /* reserved for local use */
+#define LOG_LOCAL3   (19<<3)  /* reserved for local use */
+#define LOG_LOCAL4   (20<<3)  /* reserved for local use */
+#define LOG_LOCAL5   (21<<3)  /* reserved for local use */
+#define LOG_LOCAL6   (22<<3)  /* reserved for local use */
+#define LOG_LOCAL7   (23<<3)  /* reserved for local use */
+
+#define LOG_NFACILITIES   24  /* current number of facilities */
+#define LOG_FACMASK   0x03f8  /* mask to extract facility part */
+/* facility of pri */
+#define LOG_FAC(p)   (((p) & LOG_FACMASK) >> 3)
+
+
+/*
+ * arguments to setlogmask.
+ */
+#define LOG_MASK(pri) (1 << (pri))           /* mask for one priority */
+#define LOG_UPTO(pri) ((1 << ((pri)+1)) - 1) /* all priorities through pri */
+
+/*
+ * Option flags for openlog.
+ *
+ * LOG_ODELAY no longer does anything.
+ * LOG_NDELAY is the inverse of what it used to be.
+ */
+#define LOG_PID      0x01   /* log the pid with each message */
+#define LOG_CONS     0x02   /* log on the console if errors in sending */
+#define LOG_ODELAY   0x04   /* delay open until first syslog() (default) */
+#define LOG_NDELAY   0x08   /* don't delay open */
+#define LOG_NOWAIT   0x10   /* don't wait for console forks: DEPRECATED */
+#define LOG_PERROR   0x20   /* log to stderr as well */
+#define LOG_FILE     0x40   /* Iniche specific - log to file */
+
+
+#ifdef INICHE_SYSLOG
+int  syslog_init(void);
+void closelog   (void);
+void openlog    (const char * iden, int logopt, int facility);
+void syslog     (int priority, const char * msg, ...);
+int  setlogmask (int maskpri);
+void openlogaddr(int facility, struct sockaddr *sa, int sa_len, char *fname);
+void closelogfac(int facility);
+#else
+/* INICHE_SYSLOG is not defined. Make all calls as "noop". */
+#define openlog
+#define setlogmask
+#define syslog
+#define openlogaddr
+#define closelogfac
+#endif /* else of INICHE_SYSLOG */
+
+/* vsyslog is not supported
+void vsyslog    (int priority, const char * msg, va_list args);
+*/
+
+#define  INET_NTOA         print_ipad
+
+#endif  /* _SYS_SYSLOG_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/task.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/task.h
new file mode 100644
index 0000000..9990f97
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/task.h
@@ -0,0 +1,81 @@
+/*
+ * FILENAME: task.h
+ *
+ * Copyright 1999- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains definitions for the multi-tasking package.
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1983 by the Massachusetts Institute of Technology */
+
+
+#ifndef _TASK_H_
+#define  _TASK_H_    1
+
+
+/* Pattern written into the stack area */
+#ifdef   SEG16_16
+#define  GUARDWORD   0x5354      /* hex for ST */
+#else
+#define  GUARDWORD   0x53544143  /* hex for STAC */
+#endif
+
+typedef  int   stack_t;       /* type of data in task stacks */
+
+/* NOTE: if you change this, be sure to change all the assembly which 
+ * depends on it too!!!
+ */
+struct task
+{ 
+   struct task *  tk_next;    /* pointer to next task */
+   stack_t *   tk_fp;         /* task's current frame ptr */
+   char *      tk_name;       /* the task's name */
+   int         tk_flags;      /* flag set if task is scheduled */
+   unsigned long      tk_count;      /* number of wakeups */
+   stack_t *   tk_guard;      /* pointer to lowest guardword */
+   unsigned    tk_size;       /* stack size */
+   stack_t *   tk_stack;      /* base of task's stack */
+   void *      tk_event;      /* event to wake blocked task */
+   unsigned long      tk_waketick;   /* tick to wake up sleeping task */
+};
+
+typedef struct task task;
+
+/* tk_flags bits */
+#define  TF_AWAKE       0x0001   /* task is ready to run */
+#define  TF_MAIN        0x0002   /* task is using system stack */
+
+extern   struct task *  tk_cur;  /* currently running task */
+
+extern   unsigned TDEBUG;        /* tasking debugging */
+extern   unsigned long   tk_wakeups;
+
+/* entry points to tasking system */
+task *   tk_init(stack_t * base, int st_size);
+task *   tk_new(task*, int(*)(int), int, char*, int);    /* fork a new task */
+void     tk_block(void);            /* switch to next runnable task */
+void     tk_exit(void);             /* kill & delete current task */ 
+void     tk_kill(task * tk_to_die); /* mark any task for death */
+void     tk_wake(task * tk);        /* mark a task to run */
+void     tk_sleep(long ticks);      /* sleep for number of ticks */
+void     tk_ev_block(void * event); /* block until event occurs */
+void     tk_ev_wake(void * event);  /* wake tasks waiting for event */
+
+
+/* non-portable task utility routines */
+stack_t * tk_frame(task *, int(*)(int), unsigned);
+void      tk_switch(task *);        /* run the next task */
+stack_t * tk_getsp(void);     /* get current stack pointer */
+
+/* the yield() macro */
+#define  tk_next()      {  tk_wake(tk_cur);  tk_block(); }
+
+#endif   /* _TASK_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/tcp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcp.h
new file mode 100644
index 0000000..130bc05
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcp.h
@@ -0,0 +1,96 @@
+/*
+ * FILENAME: tcp.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _TCP_H
+#define  _TCP_H   1
+
+#ifndef BYTE_ORDER
+Error - BYTE_ORDER must be defined, usually in ..\inet\ipport.h
+#endif
+
+
+typedef   u_long   tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+
+struct tcphdr
+{
+   u_short  th_sport;      /* source port */
+   u_short  th_dport;      /* destination port */
+   tcp_seq  th_seq;        /* sequence number */
+   tcp_seq  th_ack;        /* acknowledgement number */
+
+   u_char   th_doff;       /* data offset: high 4 bits only */
+
+   /* these macros get/set the raw value, usually 5 */
+#define  GET_TH_OFF(th) (th.th_doff >> 4)
+#define  SET_TH_OFF(th, off)  (th.th_doff =  (u_char)(off   << 4))
+
+   u_char   th_flags;
+#define     TH_FIN   0x01
+#define     TH_SYN   0x02
+#define     TH_RST   0x04
+#define     TH_PUSH     0x08
+#define     TH_ACK   0x10
+#define     TH_URG   0x20
+   u_short     th_win;     /* window */
+   u_short     th_sum;     /* checksum */
+   u_short     th_urp;     /* urgent pointer */
+};
+
+#define  TCPOPT_EOL        0
+#define  TCPOPT_NOP        1
+#define  TCPOPT_MAXSEG     2
+#define  TCPOPT_WINSCALE   3
+#define  TCPOPT_SACKOK     4
+#define  TCPOPT_SACKDATA   5
+#define  TCPOPT_RTT        8
+
+#endif   /* _TCP_H */
+
+/* end of file tcp.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpapp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpapp.h
new file mode 100644
index 0000000..cefa619
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpapp.h
@@ -0,0 +1,36 @@
+/*
+ * FILENAME: tcpapp.h
+ *
+ * Copyright 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Single include file for INterNicher TCP applications. This defines everything
+ * the app needs to call sockets. Works for Full-Sized stack or mini stack.
+ *
+ * MODULE: TCP
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. All rights reserved. */
+
+
+#ifndef _TCPAPP_H
+#define  _TCPAPP_H  1
+
+#include "ipport.h"
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+
+
+#ifdef MINI_TCP
+#include "msock.h"
+#else /* not MINI_TCP */
+#include "tcpport.h"   /* NetPort embedded system includes */
+#endif   /* MINI_TCP */
+
+#endif	/* _TCPAPP_H */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpport.h
new file mode 100644
index 0000000..8956b83
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/tcpport.h
@@ -0,0 +1,326 @@
+/*
+ * FILENAME: tcpport.h
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * TCP port dependent definitions. 
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: usually
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. All rights reserved. */
+
+
+#ifndef _TCPPORT_H
+#define  _TCPPORT_H  1
+
+#ifndef _IPPORT_H_
+#error You must first include ipport.h
+#endif   /*  _IPPORT_H_ */
+
+#ifdef MINI_TCP
+#error This file only for use with full-size TCP
+#endif
+
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+
+#ifdef IP_V6
+#include "ip6.h"
+#include "socket6.h"
+#endif   /* IP_V6 */
+
+
+/* Define a default TCP MSS *Max. Segment Size) which will allow us to send
+ * efficiently over our interface(s) without IP fragmenting. We default to
+ * regular ethernet, and reduce the size if we have to deal with slower (PPP) or
+ * badly designed legacy (802.3) links.
+ */
+
+#ifndef  TCP_MSS           /* allow override in ipport.h */
+#ifdef   IPSEC
+#define  TCP_MSS  0x04da   /* reduce to allow room for IPSEC encapsulation */
+#elif  defined(IEEE_802_3)
+#define  TCP_MSS  0x05ac   /* reduce for extra overhead of SNAP */
+#elif  defined(USE_PPP)
+#ifdef PPP_VJC
+#define  TCP_MSS  0x0530   /* reduce by another 128 (VJC_HDR_OFFSET) on PPP */
+#else
+#define  TCP_MSS  0x05b0   /* reduce to avoid fragments on PPP */
+#endif   /* PPP_VJC */
+#else
+#define  TCP_MSS  0x05b4   /* assume normal ethernet */
+#endif   /* media type */
+#endif   /* TCP_MSS */
+
+
+/* TCP code options - these need to preceed the nptcp.h include */
+#ifndef OMIT_IPV4
+#define  UDP_SOCKETS    1  /* support UDP (DGRAM) under sockets API */
+#endif
+
+#define  SO_SELECT      1  /* support select() call */
+#define  BSDTCP_STATS   1  /* printfs for extensive BSD statistics */
+
+#ifdef NOTDEF
+TCP options not used in this build:
+#define  DO_TCPTRACE    1  /* copius debug tracing of TCP logic */
+#endif
+
+#include "nptcp.h"      /* InterNIche<->BSD mappings */
+#include "mbuf.h"       /* BSD-ish Sockets includes */
+
+#ifdef INCLUDE_SNMP
+struct variable;
+#include "snmpport.h"
+extern   struct tcp_mib tcpmib;
+#else    /* no SNMP, support tcp_mib locally for tcp_stats() */
+struct TcpMib
+{
+   long     tcpRtoAlgorithm;
+   long     tcpRtoMin;
+   long     tcpRtoMax;
+   long     tcpMaxConn;
+   u_long   tcpActiveOpens;
+   u_long   tcpPassiveOpens;
+   u_long   tcpAttemptFails;
+   u_long   tcpEstabResets;
+   u_long   tcpCurrEstab;
+   u_long   tcpInSegs;
+   u_long   tcpOutSegs;
+   u_long   tcpRetransSegs;
+   void *   tcpConnTable;  /*32 bit ptr */
+   u_long   tcpInErrs;
+   u_long   tcpOutRsts;
+};
+extern   struct TcpMib  tcpmib; 
+#endif   /* INCLUDE_SNMP */
+
+#define  TCP_MIB_INC(varname) {tcpmib.varname++;}
+
+#ifdef CRUDE_ALLOCS
+
+/* prototype TCP ALLOC and FREE routines  */
+struct inpcb * INP_ALLOC(int size);       /* alloc internet control block "inpcb" */
+void  INP_FREE(struct inpcb *);           /* free internet control block */
+struct mbuf * MBU_ALLOC(int size);        /* alloc mbuf struct */
+struct socket * SOC_ALLOC(int size);      /* alloc a socket structure */
+void  SOC_FREE(struct socket *);          /* free a socket structure */
+struct tcpiphdr * TPH_ALLOC(int size);    /* alloc a TCP/IP header buffer */ 
+void  TPH_FREE(struct tcpiphdr *);        /* free a TCP/IP header buffer */ 
+struct tcpcb * TCB_ALLOC(int size);       /* ... tcp connection structure */
+void  TCB_FREE(struct tcpcb *);
+struct ip_socopts * SOCOPT_ALLOC(int size); /* socket options (IP_TOS, IP_TTL_OPT) */
+void  SOCOPT_FREE(struct ip_socopts *);
+
+#else /* not so CRUDE_ALLOCS */
+
+/* MAP ALLOC and FREE calls to port's memory manager */
+#define  INP_ALLOC(size)      (struct inpcb *)npalloc(size)
+#define  INP_FREE(ptr)        npfree((void*)ptr)
+#define  MBU_ALLOC(size)      (struct mbuf *)npalloc(size)
+#define  SOC_ALLOC(size)      (struct socket *)npalloc(size)
+#define  SOC_FREE(ptr)        npfree((void*)ptr)
+#define  TPH_ALLOC(size)      (struct tcpiphdr *)npalloc(size)
+#define  TPH_FREE(ptr)        npfree((void*)ptr)
+#define  TCB_ALLOC(size)      (struct tcpcb *)npalloc(size)
+#define  TCB_FREE(ptr)        npfree((void*)ptr)
+#define  SOCOPT_ALLOC(size)   (struct ip_socopts *)npalloc(size)
+#define  SOCOPT_FREE(ptr)     npfree((void*)ptr)
+
+#endif   /* alloc macros */
+
+#ifdef WEBPORT
+extern   int http_init(void);
+#endif
+
+#ifdef SO_SELECT
+/* define the size of the sockets arrays passed to select(). On UNIX 
+ * and winsock this is usually 64, but most embedded systems don't 
+ * need more than 1 or 2, and can't always afford to waste the space. 
+ * NOTE: These determine the size of set_fd structs, which are often 
+ */
+#ifndef FD_SETSIZE   /* let h_h files override */
+#define  FD_SETSIZE     12
+#endif   /* FD_SETSIZE */
+#endif   /* SO_SELECT */
+
+#ifdef DO_TCPTRACE
+/* void tcp_trace(char *, ...); */
+#define  tcp_trace   printf
+#endif
+
+
+/* Calculate mbuf reserved space for MAC + IP + TCP + OPTIONS.
+ * This is based on ethernet, 802.3 and and PPPoE since they are the
+ * largest of our default MAC header sizes.
+ */
+ 
+#ifndef ETHHDR_BIAS
+#define ETHHDR_BIAS 0
+#endif
+
+/* If we are using RFC-1323 TCP timestamp feature allow space for the
+ * option in each packet
+ */
+#ifdef TCP_TIMESTAMP
+#define  RTTMOPT_SIZE   12    /* Actual size plus alignment pad */
+#else
+#define  RTTMOPT_SIZE   0
+#endif /* TCP_TIMESTAMP */
+
+
+/* Figure out a minimum value */
+#ifdef USE_PPPOE
+#define  HDRSMINLEN  (64 + ETHHDR_BIAS + RTTMOPT_SIZE + IPSECOPT_SIZE)
+#elif  defined(IEEE_802_3)
+#define  HDRSMINLEN  (62 + ETHHDR_BIAS + RTTMOPT_SIZE + IPSECOPT_SIZE)
+#else
+#define  HDRSMINLEN  (54 + ETHHDR_BIAS + RTTMOPT_SIZE + IPSECOPT_SIZE)
+#endif
+
+/* Figure out the actual value: minimum value padded out to 
+ * a multiple of ALIGN_TYPE
+ */
+#if ((HDRSMINLEN & (ALIGN_TYPE - 1)) == 0)
+#define  HDRSLEN  HDRSMINLEN
+#else
+#define  HDRSLEN  (HDRSMINLEN + ALIGN_TYPE - (HDRSMINLEN & (ALIGN_TYPE - 1)))
+#endif
+
+
+/* macros to convert between 32-bit long socket descriptors and the 
+ * actual socket structure pointers. On most systems they just cast 
+ * the values. They are provided to support 48 bit "large model" 
+ * 386/pentium builds, which 
+ */
+
+#ifndef  LONG2SO
+#define  LONG2SO(ln)    ((struct socket *)ln)
+#define  SO2LONG(so)    ((long)so)
+#define  LONG2MBUF(ln)  ((struct mbuf *)ln)
+#define  MBUF2LONG(mb)  ((long)mb)
+#endif
+
+/*
+ * Altera Niche Stack modification:
+ * Ensure that socket FD's are always positive and greater 
+ * than ALT_MAX_FD.
+ */
+#ifdef ALT_INICHE
+
+#undef LONG2SO
+#undef SO2LONG
+#define LONG2SO(ln) ((struct socket *) ((ln - ALT_MAX_FD) << 2))
+#define SO2LONG(so) ((long) ((((unsigned long)so) >> 2) + ALT_MAX_FD))
+
+#endif /* ALT_INICHE */
+
+/* Now that TCP options are set up, include the sockets definitions */
+
+#include "socket.h"
+#include "sockvar.h"
+#include "sockcall.h"
+/*
+ * Altera Niche Stack Nios port modification
+ */
+#if defined (ALT_INICHE) && defined (BSD_SOCKETS)
+#include "bsdsock.h"
+#endif
+/* get a smart TCP_MSS for a socket. If socket is null then the default value
+ * frome the TCP_MSS defrinitions above is returned.
+ */
+int   tcp_mss (struct socket *);
+
+/* map protable "sys_" calls to InterNiche Sockets library */
+#ifdef INTEGRITY  /* Intergrity has it's own legacy mapping */
+#include "../ghsintl/isockmap.h"
+
+#else    /* InterNiche full-size stack BSD-ish sockets calls */
+
+#ifndef SYSMACRO_ALREADY   /* Allow override from ipport.h */
+/* Map ancient NetPort "sys_" socket calls to the newer (version 2.0)
+ * "standard" socket calls used in 2.0
+ */
+#define  sys_closesocket(sock)   t_socketclose(sock)
+#define  sys_send(sock, buf,  len,  flags)   t_send(sock,   buf,  len,  flags)
+#define  sys_recv(sock, buf,  len,  flags)   t_recv(sock,   buf,  len,  flags)
+#define  sys_accept(X,Y,L)       t_accept(X,Y,L)
+#define  sys_bind(X,Y,L)         t_bind(X,Y,L)
+#define  sys_socket              t_socket
+#define  sys_listen              t_listen
+#define  sys_errno(sock)         t_errno(sock)
+#define  sys_connect(X,Y,L)      t_connect(X,Y,L)
+#define  sys_shutdown            t_shutdown
+
+#define SYS_EWOULDBLOCK EWOULDBLOCK
+
+/* Map plain BSD socket routine names to Interniche t_" names. As always,
+ * allow this to be overridden by ipport.h_h
+ */
+#ifndef USER_SOCKETNAMES
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * BSD sockets support 
+ */
+#if defined (ALT_INICHE) && defined (BSD_SOCKETS)
+
+#define  socket(p1, p2, p3)                 bsd_socket(p1, p2, p3)
+#define  bind(p1, p2, p3)                   bsd_bind(p1, p2, p3)
+#define  connect(p1, p2, p3)                bsd_connect(p1, p2, p3)
+#define  listen(p1, p2)                     bsd_listen(p1, p2)
+#define  send(p1, p2, p3, p4)               bsd_send(p1, p2, p3, p4)
+#define  recv(p1, p2, p3, p4)               bsd_recv(p1, p2, p3, p4)
+#define  accept(p1, p2, p3)                 bsd_accept(p1, p2, p3)
+#define  sendto(p1, p2, p3, p4, p5, p6)     bsd_sendto(p1, p2, p3, p4, p5, p6)
+#define  recvfrom(p1, p2, p3, p4, p5, p6)   bsd_recvfrom(p1, p2, p3, p4, p5, p6)
+#define  setsockopt(p1, p2, p3, p4, p5)     bsd_setsockopt(p1, p2, p3, p4, p5)
+#define  select(p1, p2, p3, p4, p5)         bsd_select(p1, p2, p3, p4, p5)
+#define  inet_aton(p1, p2)                  bsd_inet_aton(p1, p2)
+#define  inet_ntoa(p1)                      bsd_inet_ntoa(p1)
+#define  getsockname(p1, p2, p3)            bsd_getsockname(p1, p2, p3)
+// There is no BSD close mapping; certain Niche stack code
+// calls socketclose() directly. In the Nios port, we map
+// close() to either the altera device-specific close routine,
+// or to t_socketclose() anyway.
+#define  socketclose(s)                     t_socketclose(s)
+#else /* not (ALT_INICHE && BSD_SOCKETS) */
+
+#define  socket(x,y,z)           t_socket(x,y,z)
+#define  bind(s,a,l)             t_bind(s,a,l)
+#define  connect(s,a,l)          t_connect(s,a,l)
+#define  listen(s,c)             t_listen(s,c)
+#define  send(s, b, l, f)        t_send(s, b, l, f)
+#define  recv(s, b, l, f)        t_recv(s, b, l, f)
+#define  accept(s,a,l)           t_accept(s, a, l)
+#define  sendto(s,b,l,f,a,x)     t_sendto(s,b,l,f,a,x)
+#define  recvfrom(s,b,l,f,a,x)   t_recvfrom(s,b,l,f,a,x)
+#define  socketclose(s)          t_socketclose(s)
+#define  setsockopt(s,l,o,d,x)   t_setsockopt(s,l,o,d,x)
+#endif
+
+#endif /* not (ALT_INICHE & BSD_SOCKETS */
+
+#endif   /* SYSMACRO_ALREADY */
+
+#endif   /* sockets mapping */
+
+
+#define  WP_SOCKTYPE long     /* WebPort socket type */
+#define  SOCKTYPE    long     /* preferred generic socket type */
+
+
+
+#endif   /* _TCPPORT_H */
+/* end of file tcpport.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_crnos.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_crnos.h
new file mode 100644
index 0000000..5b1a528
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_crnos.h
@@ -0,0 +1,147 @@
+/*
+ * FILENAME: tk_crnos.h
+ *
+ * Copyright  2001-2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Definitions to map NicheTask "TK_" macros to ChronOS/uCOS RTOS
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: yes (within uCOS systems)
+ */
+
+#ifndef TK_CRNOS_H
+#define TK_CRNOS_H
+
+#ifndef CHRONOS
+#error - must define CHRONOS in ipport.h to use this file
+#endif
+
+extern void TK_OSTaskResume(u_char * Id);
+
+/* define the default priority for all net related tasks */
+#define  NET_PRIORITY   0  /* not used on ChronOS */
+
+#ifdef NOT_DEF
+
+/* 
+ * Altera Niche Stack Nios port modification:
+ * OS_PRIO_SELF defined in ucosii.h, as is OS_EVENT
+ */
+
+/* Self-ID token for pass to ChronOS primitives */
+#ifdef ALT_INICHE
+#include "ucos_ii.h"
+#else
+#define OS_PRIO_SELF 0xFF
+#endif /* ALT_INICHE */
+
+#endif
+
+/* Define the CHRONOS object control TK_ macros...  */
+
+/* macros for task type, entry, and name */
+#define  TK_ENTRY(name)       void  name(void * parm)
+#define  TK_OBJECT(name)      u_char   name
+#define  TK_OBJECT_PTR(name)  u_char * name
+#define  TK_OBJECT_REF(name)  TK_OBJECT(name)
+#define  TK_ENTRY_PTR(name)   void(*name)(void*)
+
+#define  TK_THIS              TK_OSTaskQuery()
+
+#ifndef  TK_RETURN_ERROR
+#define  TK_RETURN_ERROR()   return
+#endif
+#ifndef  TK_RETURN_OK
+#define  TK_RETURN_OK()      return
+#endif
+
+
+/*
+ * synchronization primitives
+ * 
+ * Need one or the other of LOCK_NET_RESOURCE/UNLOCK_NET_RESOURCE and
+ * ENTER_CRIT_SECTION/EXIT_CRIT_SECTION.  These should be implementable
+ * as either functions or macros, so we allow e.g. ipport.h_h to 
+ * override these definitions by defining the names as macros.
+ * CHRONOS targets generally use LOCK_NET_RESOURCE/UNLOCK_NET_RESOURCE
+ * so we default to function declaractions for them.
+ */
+extern void LOCK_NET_RESOURCE(int res);
+extern void UNLOCK_NET_RESOURCE(int res);
+extern void irq_Mask(void);
+extern void irq_Unmask(void);
+
+#define  ENTER_CRIT_SECTION(p)      irq_Mask()
+#define  EXIT_CRIT_SECTION(p)       irq_Unmask()
+
+#ifdef NOTDEF
+/* set up pointers to CHRONOS semaphores as void * so we don't
+ * have to include ChronOS includes in every file in the build. In Addition
+ * RXQ_RESID and FREEQ_RESID are not real semaphores, but just placeholders.
+ * See the LOCK_NET_RESOURCE() code for details.
+ */
+#ifndef NET_RESID
+extern   void *      net_task_sem_ptr;
+#define  NET_RESID   (net_task_sem_ptr)
+#endif
+#ifndef PINGQ_RESID
+extern   void *      pingq_sem_ptr;
+#define  PINGQ_RESID  (pingq_sem_ptr)
+#endif
+#ifndef FTPCQ_RESID
+extern   void *      ftpcq_sem_ptr;
+#define  FTPCQ_RESID  (ftpcq_sem_ptr)
+#endif
+#ifndef RXQ_RESID
+extern   void *      receiveq_sem_ptr;
+#define  RXQ_RESID   (receiveq_sem_ptr)
+#endif
+#ifndef FREEQ_RESID
+extern   void *      freeq_sem_ptr;
+#define  FREEQ_RESID (freeq_sem_ptr)
+#endif
+
+#endif
+
+
+/* declare tasks which may need to be accessed by system code */
+extern   TK_OBJECT(to_pingcheck);
+extern   TK_OBJECT(to_netmain);
+extern   TK_OBJECT(to_emailer);
+extern   TK_OBJECT(to_ftpclnt);
+
+
+/* map TK_ macros to CHRONOS: */
+#define  TK_BLOCK()          OSTaskSuspend(OS_PRIO_SELF)
+extern OS_EVENT *rcvdq_sem_ptr;
+#define  TK_NETRX_BLOCK()    { \
+	                       INT8U err; \
+	                       OSSemPend(rcvdq_sem_ptr, TPS, &err); \
+	                       if ((err != OS_NO_ERR) && (err != OS_TIMEOUT)) \
+                                  dtrap(); \
+	                     }
+
+#define  TK_SLEEP(count)     OSTimeDly(count + 1)
+
+/* (Id) is always of type TK_OBJECT_PTR */
+#define  TK_WAKE(Id)         OSTaskResume(*(u_char*)(Id))
+
+/* (ev) is always of type TK_OBJECT_REF */
+#define  TK_WAKE_EVENT(ev)   OSTaskResume((u_char)(ev))
+
+/* Do tk_yield() as a function to avoid pointless delays */
+void tk_yield(void);
+#define TK_YIELD()           tk_yield()
+
+
+/* For ChronOS SignalPktDemux() is a routine which manually sets the net
+ * task to runnable. This is so we can call it from an ISR and not have
+ * ChronOS enable interrupts on us.
+ */
+#define  SignalPktDemux()     OSSemPost(rcvdq_sem_ptr)
+#define  SignalEmailTask()    OSTaskResume(to_emailer)
+#define  SignalFtpClient()    OSTaskResume(to_ftpclnt)
+
+#endif  /* TK_CRNOS_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_ntask.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_ntask.h
new file mode 100644
index 0000000..5f4fad4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/tk_ntask.h
@@ -0,0 +1,67 @@
+/*
+ * FILENAME: tk_ntask.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: yes
+ */
+
+#ifndef TK_NTASK_H
+#define TK_NTASK_H
+
+#ifndef INICHE_TASKS
+#error must define INICHE_TASKS in ipport.h to use this file
+#endif
+
+/* include the nichtask file in misclib */
+#include "task.h"
+
+/* the TK_ object macros, for defining task objects, etc. */
+#define  TK_ENTRY(name)       int   name(int parm)
+#define  TK_ENTRY_PTR(name)   int(*name)(int)
+#define  TK_OBJECT(name)      task *   name
+#define  TK_OBJECT_PTR(name)  task **  name
+
+#ifndef  TK_RETURN_ERROR
+#define  TK_RETURN_ERROR()    return   (-1)
+#endif
+#ifndef  TK_RETURN_OK
+#define  TK_RETURN_OK()       parm++;  return   (0)
+#endif
+
+/* the TK_ function macros: */
+#define  tk_yield()     {  tk_wake(tk_cur);  tk_block(); }
+#define  TK_APP_WAKE(ev)   tk_ev_wake(ev)
+#define  TK_WAKE(task)     tk_wake(*task)
+#define  TK_BLOCK()        tk_block()
+#define  TK_SLEEP(tks)     tk_sleep(tks)
+
+
+#define  NET_PRIORITY         0     /* not used on tasks */
+#define  MAIN_TASK_IS_NET     1     /* compiler main() is converted to net task */
+#define  TK_THIS  tk_cur
+#define  TK_NETMAINPARM       0     /* parameter to main/net task */
+/*#undef   TK_STDIN_DEVICE*/
+#define  TCPWAKE_ALREADY      1     /* tell tcp we already have this */
+
+#if !defined(STK_TOPDOWN) && !defined(STK_BOTTOMUP)
+#define  STK_TOPDOWN          1     /* Most CPU stacks are top down */
+#endif
+
+
+/* declare tasks which need to be accessed by system code */
+extern   task *   to_netmain;
+extern   task *   to_emailer;
+extern   task *   to_ftpclnt;
+extern   task *   to_pingcheck;
+
+/* define macros to  wake net task on packet receipt, etc */
+#define  SignalPktDemux()  tk_wake(to_netmain)
+#define  SignalEmailTask() tk_wake(to_emailer)
+#define  SignalFtpClient() tk_wake(to_ftpclnt)
+
+
+#endif  /* TK_NTASK_H */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/udp.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/udp.h
new file mode 100644
index 0000000..2e4fa16
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/udp.h
@@ -0,0 +1,153 @@
+/*
+ * FILENAME: udp.h
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * UDP protocol definitions
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990, 1993 by NetPort Software. */
+/* Copyright 1986 by Carnegie Mellon */
+/* Copyright 1983 by the Massachusetts Institute of Technology  */
+
+
+#ifndef _UDP_H_
+#define  _UDP_H_  1
+
+
+/* UDP Header structure */
+
+struct udp
+{
+   unshort  ud_srcp;    /* source port */
+   unshort  ud_dstp;    /* dest port */
+   unshort  ud_len;     /* length of UDP packet */
+   unshort  ud_cksum;   /* UDP checksum */
+};
+
+/* The UDP Connection structure */
+struct udp_conn
+{
+   struct udp_conn * u_next;
+   unshort  u_flags;    /* flags for this connection */
+   unshort  u_lport;    /* local port (host byte order) */
+   unshort  u_fport;    /* foreign port (host byte order) */
+   ip_addr  u_lhost;    /* local host IP address (network byte order) */
+   ip_addr  u_fhost;    /* foreign host IP address (network byte order) */
+#ifdef IP_V6
+   ip6_addr u_l6host;   /* local host IPv6 address */
+   ip6_addr u_f6host;   /* foreign host IPv6 address */
+#endif
+   int      (*u_rcv)(PACKET, void*);   /* incoming packet handler */
+   void *   u_data;     /* user 'per-connection' token */
+   int      (*u_durcv)();  /* incoming dest. unreach. handler */
+};
+
+/* Flags for use in u_flags: */
+#define UDPCF_V4     0x0001   /* flag: tied to IPv4 */
+#define UDPCF_V6     0x0002   /* flag: tied to IPv6 */
+
+/* UDP stats (MIB information), see RFC 1156 */
+struct UdpMib
+{
+   u_long   udpInDatagrams;   /* total delivered Datagrams */
+   u_long   udpNoPorts;       /* undelivered datagrams: unused port */
+   u_long   udpInErrors;      /* undelivered datagrams: other reasons */
+   u_long   udpOutDatagrams;  /* successfully sent datagrams */
+};
+
+extern   struct UdpMib  udp_mib;
+
+typedef  struct UdpMib * UDPMIB;
+
+typedef  struct udp_conn * UDPCONN;
+
+struct ph         /* pseudo header for checksumming */
+{
+   ip_addr  ph_src;  /* source address */
+   ip_addr  ph_dest; /* dest address */
+   char     ph_zero; /* zero (reserved) */
+   char     ph_prot; /* protocol */
+   unshort  ph_len;  /* udp length */
+};
+
+
+#define  UDP_PROT    17 /* UDP Internet protocol number */
+#define  UDPLEN   sizeof(struct  udp)
+
+#define  udp_head(pip)     ((struct udp *)ip_data((pip)))
+#define  udp_data(pup)     ((char *)(pup) +  sizeof(struct  udp))
+
+extern   UDPCONN  firstudp;
+
+/* Some reserved UDP ports */
+#define  RIP_PORT    520
+#define  DNS_PORT    53
+#define  SNMP_PORT   161
+
+/* estimate worst case header sizes for packet allocation */
+
+/* Figure out a minimum value 
+ * IP Hdr is 20 bytes and ethernet header is 14 bytes 
+ */
+#define UDP_LLHDR (34 + ETHHDR_BIAS  + IPSECOPT_SIZE) 
+
+#ifdef USE_PPPOE
+#define  UDPHDRSMINLEN  (10 + UDP_LLHDR)
+#elif  defined(IEEE_802_3)
+#define  UDPHDRSMINLEN  (8 + UDP_LLHDR)
+#else
+#define  UDPHDRSMINLEN  UDP_LLHDR
+#endif
+
+/* Figure out the actual value: minimum value padded out to 
+ * a multiple of ALIGN_TYPE
+ */
+#if ((UDPHDRSMINLEN & (ALIGN_TYPE - 1)) == 0)
+#define  UDPHDRSLEN  UDPHDRSMINLEN
+#else
+#define  UDPHDRSLEN  (UDPHDRSMINLEN + ALIGN_TYPE - (UDPHDRSMINLEN & (ALIGN_TYPE - 1)))
+#endif
+
+
+/* function prototypes -JB- */
+int      udpdemux(PACKET);
+int      udp_send(unshort /*fport*/, unshort /*lport*/, PACKET);
+
+void     udpswap(struct udp *);
+unshort  udp_socket(void);
+PACKET   udp_alloc(int, int);
+int      udp_maxalloc(void);
+void     udp_free(PACKET);
+UDPCONN  udp_open(ip_addr, unshort /*fport*/, unshort /*lport*/,
+   int(*)(PACKET, void * /*data*/) , void *  /*data*/);
+void     udp_close(UDPCONN);
+int      udp_stats(void * pio);
+
+
+#ifdef IP_V6
+PACKET   udp6_alloc(int, int);
+int      udp6_maxalloc(void);
+UDPCONN  udp6_open(ip6_addr * /*faddr*/, unshort /*fport*/, 
+                   unshort /*lport*/,
+                   int(*)(PACKET, void * /*data*/) , void *  /*data*/);
+int      udp6_send(ip6_addr * /*faddr*/, unshort /*fport*/, 
+                   unshort /*lport*/, PACKET);
+#endif
+
+/* some hardwired protocol callbacks: */
+int      snmp_upc(PACKET, unshort /*lport*/);      /* SNMPv1 receive upcall */
+int      v3_udp_recv(PACKET, unshort /*lport*/);   /* SNMPv3 receive upcall */
+int      dns_upcall(PACKET pkt, unshort);          /* DNS */
+int      rip_udp_recv(PACKET p, unshort);          /* RIP */
+
+#endif   /* _UDP_H_ */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/userpass.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/userpass.h
new file mode 100644
index 0000000..28c8879
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/userpass.h
@@ -0,0 +1,53 @@
+/*
+ * FILENAME: userpass.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * User & password defines for demo TCP/IP application. 
+ * This is used by FTP, WebPort, PPP(pap), and any other network 
+ * protocols which need a user name and password. 
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+
+#ifndef _USERPASS_H_
+#define  _USERPASS_H_   1
+
+
+/* these #defines can be overridden from ipport.h */
+#ifndef NUM_NETUSERS
+#define  NUM_NETUSERS   12
+#endif
+
+#ifndef MAX_USERLENGTH
+#define  MAX_USERLENGTH 32
+#endif
+
+
+/* the "app codes" for chgeck_permit() */
+#define  HTTP_USER      1
+#define  FTP_USER       2
+#define  PPP_USER       3
+#define  TELNET_USER    4
+
+struct userpass
+{
+   char  username[MAX_USERLENGTH];
+   char  password[MAX_USERLENGTH];
+   void *   permissions;   /* for use by porting apps. */
+};
+
+extern   struct userpass   users[NUM_NETUSERS];
+typedef  struct userpass   USER;
+
+int    add_user(char * username, char * password, void *);
+int    check_permit(char * username, char * password, int appcode, void *);
+char * get_password(char * user);
+
+#endif   /* _USERPASS_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/vfsfiles.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/vfsfiles.h
new file mode 100644
index 0000000..6ea65bc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/vfsfiles.h
@@ -0,0 +1,336 @@
+/*
+ * FILENAME: vfsfiles.h
+ *
+ * Copyright 1999-2008 By InterNiche Technologies Inc. All rights reserved
+ *
+ * NetPort "virtual" file system. This implements the vfopen(), 
+ * vfread(), etc, calls the Embedded WEB servers (et.al.) makes to do 
+ * file IO. These calls lookup names, descriptors, etc, to see if the 
+ * file is a "virtual" file in RAM/ROM/FLASH, or if it should fall 
+ * through to the local disk system (if any)
+ *
+ * MODULE: VFS
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* vfsfiles.h 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ */
+
+#ifndef _VFSFILES_H
+#define  _VFSFILES_H 1
+
+/* bit flag values for vfs_file.flags mask */
+#define     VF_HTMLCOMPRESSED    0x01  /* If HTML, file is tag-compressed */
+#define     VF_GIFCOMPRESSED     VF_HTMLCOMPRESSED /* If GIF, file is 0-compressed */
+
+#define     VF_AUTHBASIC   0x02  /* check Basic user auth */
+#define     VF_AUTHMD5     0x04  /* check MD5 user auth */
+
+#define     VF_MAPFILE     0x08  /* data pointer is a (struct mapfile*) */
+#define     VF_CVAR        0x10  /* it's C variable disply */
+
+#define     VF_WRITE       0x20  /* writable device */
+#define     VF_DYNAMICINFO 0x40  /* file info created dynamically */
+#define     VF_DYNAMICDATA 0x80  /* file data created dynamically */
+#define     VF_NONVOLATILE 0x100 /* copy to non-volatile storage on,close */
+#define     VF_STALE       0x200 /* contents of file have been changed */
+#define     VF_PUSH        0x400 /* It's a web server "push" file */
+#define     VF_NOCACHE     0x800
+#define     VF_NODATA      0x8000 /* file has a size, but no data actual data */
+
+#ifndef VFS_FILES /* set (or not) in ipport.h */
+
+/* If there's no VFS, just map vfs routines to local */
+#ifdef HT_LOCALFS
+
+#define  VFILE FILE
+#define  vfopen(n,m)    fopen(n,m)
+#define  vfclose(fd)    fclose(fd)
+#define  vfread(buf,i,j,fd)      fread(buf,i,j,fd)
+#define  vfseek(fd,off,m)        fseek(fd,off,m)
+#define  vfwrite(buf,siz,items,fd)  fwrite(buf,siz,items,fd)
+#define  vftell(fd)     ftell(fd)
+#define  vgetc(fd)      fgetc(fd)
+#define  vferror(fd)    ferror(fd)
+#define  vunlink(name)  remove(name)
+#define  vclearerr(fd)  clearerr(fd)
+
+#else /* no local file system either? */
+#error Don't compile this, the defines don't make sense
+#error Either VFS_FILES or HT_LOCALFS must be defined, or both.
+#endif   /* HT_LOCALFS */
+
+#else /* VFS_FILES - there IS a VFS system: */
+
+#ifndef HT_LOCALFS   /* Build defined VFS but no local FS */
+/* Map ansi routines and declarations to VFS */
+#ifndef NO_STDFILE_CALLS   /* Switch requested by GHS Integrity group */
+#undef  FILE
+#undef  fopen
+#undef  fclose
+#undef  fread
+#undef  fseek
+#undef  fwrite
+#undef  ftell
+#undef  getc
+#undef  ferror
+#undef  remove
+#undef  unlink
+#undef  clearerr
+
+#define  FILE                 VFILE
+#define  fopen(n,m)           vfopen(n,m)
+#define  fclose(fd)           vfclose(fd)
+#define  fread(buf,i,j,fd)    vfread(buf,i,j,fd)
+#define  fseek(fd,off,m)      vfseek(fd,off,m)
+#define  fwrite(buf,siz,items,fd)      vfwrite(buf,siz,items,fd)
+#define  ftell(fd)            vftell(fd)
+#define  getc(fd)             vgetc(fd)
+#define  ferror(fd)           vferror(fd)
+#define  remove(name)         vunlink(name)
+#define  unlink(name)         vunlink(name)
+#define  clearerr(fd)         vclearerr(fd)
+#endif   /* NO_STDFILE_CALLS */
+#endif   /* HT_LOCALFS */
+
+#define  FILENAMEMAX    16 /* max chars in a file name */
+
+#define  HTPATHMAX   128   /* max chars in a file name */
+
+extern   char  vfs_root_path[HTPATHMAX];  /* path to file system */
+
+#ifdef WEBPORT
+/* preserve compatibility with old-style webport path */
+extern   char *   http_root_path;
+/* predeclare structures to avoid compiler complaints */
+struct httpd;
+struct httpform;
+
+
+#ifdef SERVER_PUSH
+struct vfs_file;      /* predecl */
+typedef int   (*pushcall)(struct vfs_file * vp, struct httpd * hp);
+int   htpush_init(char * name, pushcall callbk);
+#endif   /* SERVER_PUSH */
+#endif   /* WEBPORT */
+
+/* The per-file structure for Web server virtual files. These are 
+ * kept in a linked list which may be build dynamically or 
+ * pre-compiled into the system image:
+ */
+
+struct vfs_file
+{
+   struct vfs_file * next;
+   char  name[FILENAMEMAX  +  1];   /* name of file under "path" */
+   unsigned short flags;
+   unsigned char *   data;    /* pointer to file data, NULL if none */
+   unsigned long  real_size;  /* size in bytes of file before compression */
+   unsigned long  comp_size;  /* size in bytes of file compressed */
+   unsigned long  buf_size;   /* size in bytes of current memory buffer */
+
+#ifdef WEBPORT
+   /* routine to call on GET, POST, or special SSIs; NULL if none */
+   int (*ssi_func)(struct vfs_file *, struct httpd *, char * args);
+   /* routine to call if file is treated as CGI executable */
+   int (*cgi_func)(struct httpd *, struct httpform *, char ** text);
+#ifdef SERVER_PUSH
+   pushcall pushfunc;
+#endif   /* SERVER_PUSH */
+#endif   /* WEBPORT */
+
+   void *   method;        /* pointer depends on flags */
+};
+
+
+#ifndef VFS_VFS_FILE_ALLOC    /* allow override form ipport.h */
+#define VFS_VFS_FILE_ALLOC() \
+   (struct vfs_file *) npalloc(sizeof(struct vfs_file))
+#define  VFS_VFS_FILE_FREE(x) npfree(x)
+#endif   /* VFS_VFS_FILE_ALLOC */
+
+
+extern   struct vfs_file * vfsfiles;   /* linked list of all vfiles */
+
+/* structures created for and returned from each vfopen() call. These
+ * are cleaned up by vfclose() calls.
+ */
+ 
+struct vfs_open
+{
+   struct vfs_open * next;
+   struct vfs_file * file;
+   unsigned char * cmploc;       /* current position in data buf */
+   unsigned char * tag;          /* current position in compressed tag, if any */
+   int   error;                  /* last error, if any */
+};
+
+typedef struct vfs_open VFILE;
+
+#define VFS_VFS_OPEN_ALLOC() \
+   (struct vfs_open *) npalloc(sizeof(struct vfs_open))
+#define  VFS_VFS_OPEN_FREE(x) npfree(x)
+
+extern   VFILE *  vfiles;  /* list of open files */
+
+/* for ".map" files, the data pointer actually points to a linked 
+list of these structures: */
+struct mapitem {
+   struct mapitem *  next;    /* list link */
+   char  name[FILENAMEMAX  +  1];   /* name of html file to GET */
+   int   x_min,   x_max;      /* X coordinate range */
+   int   y_min,   y_max;      /* Y coordinate range */
+};
+
+/* routines which map to standard buffered file routines: */
+VFILE*   vfopen(char * name, char * mode);
+int      vfflush(VFILE * vfd);
+void     vfclose(VFILE * vfd);
+int      vfread(char * buf, unsigned size, unsigned items, VFILE * vfd);
+int      vfwrite(char * buf, unsigned size, unsigned items, VFILE * vfd);
+int      vfseek(VFILE * vfd, long offset, int mode);
+long     vftell(VFILE * vfd);
+int      vgetc(VFILE * vfd);
+char     *vfgets(char * s, int lim, VFILE * fp);
+int      vfeof(VFILE * vfd);
+int      vferror(VFILE * vfd);
+/*
+ * Altera Niche Stack Nios port modification:
+ * Change prototype from char * name to const char to
+ * follow C library standard.
+ */
+int      vunlink(const char * name);
+void     vclearerr(VFILE * vfd);
+
+#ifdef HT_EXTDEV
+struct vfroutines {
+   struct vfroutines *  next; /* keep these in a list */
+   VFILE* (* r_fopen)(char * name, char * mode);
+   void   (* r_fclose)(VFILE * vfd);
+   int    (* r_fread)(char * buf, unsigned size, unsigned items, VFILE * vfd);
+   int    (* r_fwrite)(char * buf, unsigned size, unsigned items, VFILE * vfd);
+   int    (* r_fseek)(VFILE * vfd, long offset, int mode);
+   long   (* r_ftell)(VFILE * vfd);
+   int    (* r_fgetc)(VFILE * vfd);
+   int    (* r_unlink)(char*);
+};
+extern   struct vfroutines *  vfsystems;
+#endif
+
+void vfs_init(void);
+void vfs_file_detail(struct vfs_file * vfp, char * buf);
+int vfs_file_list(void * pio);
+
+#ifdef HT_RWVFS
+
+/* this constant defines the maximum amount of space that will be
+ * allocated to contain data buffers for the read/write file system
+ */
+
+#ifndef VFS_MAX_TOTAL_RW_SPACE   /* allow override */
+#define  VFS_MAX_TOTAL_RW_SPACE  0xffff
+#endif
+
+
+/* this counts the number of bytes that have been allocated for 
+ * buffers for the read/write file system so that the above maximum 
+ * can be enforced
+ */
+extern   unsigned long  vfs_total_rw_space;
+
+/* this constant defines the maximum number of dynamically allocated
+   files that can exist in the file system */
+#define  VFS_MAX_DYNA_FILES   0xff
+
+/* this counts the number of dynamically allocated files in the file
+   system so that the above maximum can be enforced */
+extern   unsigned long  vfs_total_dyna_files;
+
+#define  VFS_CLOSE_FRAG_FLOOR 255
+
+unsigned char *vf_alloc_buffer(unsigned long size);
+void vf_free_buffer(unsigned char * buffer, unsigned long size);
+
+void vfs_sync(struct vfs_file * vfp);
+void vfs_restore(void);
+
+extern   int   vfs_dir_stale;
+
+#ifndef VFS_MAX_FILE_IO_SIZE
+#define VFS_MAX_FILE_IO_SIZE (16 * 1024)
+#endif
+
+/* opens backing store media, clears it if clear !=0, returns handle 
+ * to media if successful, returns null and puts 
+ * error code (like errno) at perror if unsuccessful 
+ */
+void * vfs_sync_open(int clear, int * p_error);
+
+/* closes the backing store media. returns 0 if successful */
+int vfs_sync_close(void * fd);
+
+/* read len bytes into buf from the backing store referenced by fd at 
+ * the current backing store offset. increment offset by len. 
+ * returns 0 if successful 
+ */
+int vfs_sync_read(void * fd, void * buf, unsigned int len);
+
+/* write len bytes from buf to the backing store referenced by fd at 
+ * the current backing store offset. increment offset by len. 
+ * returns 0 if successful, error if not 
+ */
+int vfs_sync_write(void * fd, void * buf, unsigned int len);
+
+#endif   /* HT_RWVFS */
+
+/* this constant defines the maximum number of files that can be
+   concurrently open in the file system */
+#define  VFS_MAX_OPEN_FILES   0xff
+
+/* this counts the number of open files in the file system so that
+   the above maximum can be enforced */
+extern   unsigned long  vfs_open_files;
+
+extern   int   vfopen_error;
+
+#ifndef EOF
+#define  EOF   (-1)
+#endif   /* EOF */
+
+#ifndef EBADF
+#define  EBADF (-2)
+#endif
+
+/* internal support routines */
+struct vfs_file * vfslookup(char * name);    /* lookup vfs_file by file name */
+int    isvfile(VFILE*);    /* bool - is the VFILE virtual? */
+char * uslash(char * path);   /* make DOS slashes into UNIX */
+void set_vfopen_error(int error);
+int get_vfopen_error(void);
+VFILE * vf_alloc_and_link_vop(void);
+VFILE *vfopen_locked(char * name, char * mode);
+void vfclose_locked(VFILE * vfd);
+void vfunlink_flag_open_files(struct vfs_file * vfp);
+int vgetc_locked(VFILE * vfd);
+struct vfs_file * vfslookup_locked(char * name);
+int isvfile_locked(VFILE * vfp);
+int vfwrite_locked(char * buf, unsigned size, unsigned items, VFILE * vfd);
+
+/* fseek constants, if not in C library headers */
+#ifndef SEEK_CUR
+#define  SEEK_CUR    1
+#endif
+#ifndef SEEK_END
+#define  SEEK_END    2
+#endif
+#ifndef SEEK_SET
+#define  SEEK_SET    0
+#endif
+
+#endif  /* VFS_FILES */
+
+#endif  /* _VFSFILES_H */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/h/webport.h b/FPGA_nios/hit_pat_bsp/iniche/src/h/webport.h
new file mode 100644
index 0000000..f8002f2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/h/webport.h
@@ -0,0 +1,76 @@
+/* 
+ * Filename: webport.h 
+ *
+ * Per-port TCP/IP, sockets, system info includes.
+ */
+
+#ifndef _WEBPORT_H_
+#define _WEBPORT_H_ 1
+
+#ifndef HTML_COMP
+#include "libport.h"   /* NetPort embedded system includes */
+#include "tcpapp.h"
+
+#ifdef SMTP_ALERTS
+#include "smtpport.h"
+#include "smtpalrt.h"
+#endif   /* SMTP_ALERTS */
+
+/* forward declarations to stifle compiler warnings */
+struct httpd;
+struct httpform;
+struct vfs_file;
+struct map_item;
+
+#else   /* the html compiler's case */
+
+struct httpd;
+struct vfs_file;
+#include "nptypes.h"
+#endif
+
+/* Define HT_CONST to the "const" keyword used by the compiler.
+   Data generated by HTML compiler uses HT_CONST. If "const" declaration
+   is not desired, then HT_CONST can be changed to reflect that. */
+#define HT_CONST    const
+
+#define HTTPMAXSEND 4096    /* MAX we should send to sock in one loop */
+#define HTTPTMO   (12*TPS)    /* ticks to time out idle connection */
+#define HTTICKS   (cticks)    /* LONG - ticks since start */
+
+/* Define this if there is a local disk system to default to when the 
+named files are not found in the virtual file system */
+
+#ifdef   OMIT_VFS
+#define  HT_NOVFS    1     /* TRUE if there's no virtual files */
+#endif
+
+#define NP_ESCAPE_CHAR	     0xff
+
+#define __ARGS(x) x  /* for RSA md5.h security include */
+
+/* HTTP_ENTRY macro applied to all http code entry points: */
+#define  _HTTP_ENTRY _loadds
+
+extern long httpsock;   /* socket listening for http connections */
+extern struct sockaddr_in httpsin;
+
+int   http_init(void);   /* start up the web server */
+void  http_check(void);   /* demo http server task loop */
+
+/* define these away to nothing for now... */
+#define  ht_putfile(hp)
+#define  ht_putmore(hp)
+
+#define  ht_setfiletype(hp)   (FTYPE_NULL)   /* default file type */
+
+#define SYS_EWOULDBLOCK EWOULDBLOCK
+
+#ifdef HT_MD5AUTH
+extern char * make_nonce(struct httpd * hp, struct vfs_file * vfp);
+#endif
+
+#define HTTPVER_1_1      1   /* http version number 1.1 */
+#define HTTP_PORT        80  /* non-secure http port number */
+#define SSL_PORT         443 /* secure http port number */
+#endif /* _WEBPORT_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/et_arp.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/et_arp.c
new file mode 100644
index 0000000..b2fba80
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/et_arp.c
@@ -0,0 +1,1223 @@
+/*
+ * FILENAME: et_arp.c
+ *
+ * Copyright 1997-2007 by InterNiche Technologies Inc. All rights reserved
+ *
+ * Ethernet (and similar media) arp code.
+ * 
+ * Following is a description of the ARP API
+ * 1. Call etainit() during init time to do ARP related initializations
+ * 2. Call send_via_arp() to send a packet()
+ *    If ARP has an entry, et_send() is called to send the packet.
+ *    If ARP doesn't have an entry, a new entry is created, send_arp()
+ *       is called to send the ARP request and packet is queued.
+ * 3. When a ARP reply is received, arprcv() is called.
+ *    It updates the ARP table and sends pending packets 
+ *       (related to the received reply).
+ * 4. When a ARP request is received, then arpReply() is called
+ *    to send an ARP reply.
+ * 5. Call arp_stats() to display ARP table
+ * 6. When DYNAMIC_IFACES is enabled, call clear_arp_entries() to
+ *    clear all interface related entries in the ARP table.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: etainit(), et_send(), arp_free_pending(), 
+ * ROUTINES: arp_send_pending(), send_arp(), find_oldest_arp(), 
+ * ROUTINES: make_arp_entry(), arpReply(), arprcv(), 
+ * ROUTINES: send_via_arp(), arp_stats(), clear_arp_entries(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990 by NetPort Software  */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+#include "intimers.h"
+
+/* allow override in ipport.h_h */
+#ifndef ARPENT_TMO
+#define ARPENT_TMO      10    /* periodic ARP entry timeout (sec) */
+#endif
+
+#define arpsize         (ETHHDR_SIZE + sizeof(struct  arp_hdr))
+
+static long arp_timer = 0;    /* periodic timer handle */
+void cb_arpent_tmo(long);     /* timer callback function */
+
+                              /* last ARP entry used */
+struct arptabent *arpcache = (struct arptabent *)NULL;
+static u_long cachetime;      /* time we created arpcache entry */
+int arp_ageout = 600 * TPS;   /* APR table refresh age, in ticks */
+
+#ifdef USE_AUTOIP
+/* Auto Ip callback */
+extern void AutoIp_arp_response(struct arp_hdr * hdr, NET ifp);
+#endif
+
+/* arp stats - In addition to MIB */
+unsigned    arpReqsIn  = 0;   /* requests received */
+unsigned    arpReqsOut = 0;   /* requests sent */
+unsigned    arpRepsIn  = 0;   /* replys received */
+unsigned    arpRepsOut = 0;   /* replys sent */
+
+struct arptabent  arp_table[MAXARPS];     /* the actual table */
+
+#ifdef IEEE_802_3
+u_char snapdata[6] = {170, 170, 3, 0, 0, 0 };  /* per RFC-1042 */
+#endif
+
+
+/* FUNCTION: etainit()
+ * 
+ * PARAMS: none
+ *
+ * RETURNS: int               0 if OK, else nonzero
+ */
+
+int
+etainit(void)
+{
+   /* register ARP type with the Net Driver */
+   if (reg_type(ET_ARP) != 0)
+   {
+#ifdef NPDEBUG
+      dprintf("ARP: unable to register type with MAC Driver\n");
+#endif
+      return (1);
+   }
+   return (0);
+}
+
+
+
+/* FUNCTION: et_send()
+ * 
+ * Send a packet with ARP information
+ *
+ * PARAM1: PACKET             packet to send
+ * PARAM2: arptabent *        ARP entry pointer
+ *
+ * RETURNS: int               0 if OK, or the usual ENP_ errors 
+ *
+ * Fill in an outgoing ethernet-bound packet's ethernet 
+ * header and send it. Header info is in arp entry passed
+ * and MIB info in the packet header. 
+ */
+
+int
+et_send(PACKET pkt, struct arptabent *tp)
+{
+   char *ethhdr;
+   IFMIB etif = pkt->net->n_mib;    /* mib info for this ethernet interface */
+   int err;
+
+   tp->lasttime = cticks;
+   pkt->nb_prot -= ETHHDR_SIZE;  /* prepare for prepending ethernet header */
+   pkt->nb_plen += ETHHDR_SIZE;
+   ethhdr = pkt->nb_prot + ETHHDR_BIAS;
+
+#ifdef IEEE_802_3
+   /* If this arp host uses only SNAP, then use SNAP */
+   if ((tp->flags & (ET_ETH2|ET_SNAP)) == ET_SNAP)
+   {
+      struct snap_hdr * snap;
+      pkt->nb_prot -= 8;      /* IEEE SNAP header occupies 8 bytes */
+      pkt->nb_plen += 8;
+      ethhdr = pkt->nb_prot + ETHHDR_BIAS;
+      snap = (struct snap_hdr *)(pkt->nb_prot + ETHHDR_SIZE);
+      MEMMOVE(snap, snapdata, 6);
+      snap->type = ARPIP;
+   }
+#endif   /* IEEE_802_3 */
+
+   if (ethhdr < pkt->nb_buff)   /* sanity check pointer */
+      panic("et_send: prepend");
+
+   MEMMOVE(ethhdr + ET_DSTOFF, tp->t_phy_addr, 6);  /* set pkt's MAC dst addr */
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);  /* MAC src */
+
+   /* nice clean ethernet II header */
+   if ((tp->flags & (ET_ETH2|ET_SNAP)) != ET_SNAP)
+      ET_TYPE_SET(ethhdr, ntohs(ARPIP));
+
+#ifdef IEEE_802_3
+   if ((tp->flags & (ET_ETH2|ET_SNAP)) == ET_SNAP)
+   {
+      unsigned len8023;
+
+      len8023 = pkt->nb_plen - ETHHDR_SIZE;
+
+      /* As per RFC 1042 :
+       * a.) Length should be net endian.
+       * b.) Length should include 802.2 LLC and SNAP headers.
+       */
+
+      ET_TYPE_SET(ethhdr, len8023);
+   }
+#endif   /* IEEE_802_3 */
+
+   /* if a packet oriented send exists, use it: */
+   if (pkt->net->pkt_send)
+      err = pkt->net->pkt_send(pkt);   /* send packet to media */
+   else  /* else use older raw_send routine */
+   {
+      /* sent to media */
+      err = pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen);
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+
+   return (err);
+}
+
+
+
+/* FUNCTION: arp_free_pending()
+ *
+ * Free any pending packets for a ARP table entry
+ * 
+ * PARAM1: arptabent *        ARP table entry pointer
+ *
+ * RETURNS: none
+ *
+ * Free all pending packets for the specified ARP table entry.
+ * Clear the list (entry->pending) after freeing the packets
+ * and mark the entry "unused".
+ */
+
+void
+arp_free_pending(struct arptabent *entry)
+{
+   PACKET tmppkt;
+   PACKET nextpkt;
+
+   /* entry->pending has the linked list of all pending packets */
+   tmppkt = entry->pending;
+   entry->pending = (PACKET)NULL;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+
+   /* free all pending packets */
+   while (tmppkt)
+   {
+      nextpkt = tmppkt->next;        /* save the next packet in list */
+      tmppkt->next = (PACKET)NULL;
+      pk_free(tmppkt);               /* free current packet */
+      tmppkt = nextpkt;              /* process the next packet */
+   }
+
+   entry->t_pro_addr = 0;     /* mark the entry "unused" */
+
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+}
+
+
+
+/* FUNCTION: arp_send_pending()
+ * 
+ * Send any pending packets for an ARP entry
+ *
+ * PARAM1: arptabent *        ARP table entry
+ *
+ * RETURNS: none
+ *
+ * Send all pending packets for the specified ARP table entry.
+ * Clear the list (entry->pending) after sending the packets.
+ */
+
+void
+arp_send_pending(struct arptabent *entry)
+{
+   PACKET tmppkt = entry->pending;
+
+   /* entry->pending has the linked list of all pending packets */
+
+   /* send all pending packets */
+   while ((tmppkt = entry->pending) != (PACKET)NULL)
+   {
+      entry->pending = tmppkt->next;   /* unlink the next packet */
+      tmppkt->next = (PACKET)NULL;
+      et_send(tmppkt, entry);          /* try send again */
+   }
+}
+
+
+
+/* FUNCTION: send_arp()
+ * 
+ * Send an ARP request packet
+ *
+ * PARAM1: PACKET             packet to be send
+ * PARAM2: ip_addr            destination IP address of packet
+ *
+ * RETURNS: Returns 0 if OK, or the usual ENP_ errors 
+ *
+ * Send an arp for outgoing ethernet packet pkt, which has no
+ * current arp table entry. This means making a partial entry 
+ * and queuing the packet at the entry. Packet will be sent when 
+ * target IP host replies to the ARP we send herein. If no reply, 
+ * timeout will eventually free packet. 
+ */
+
+int
+send_arp(PACKET pkt, ip_addr dest_ip)
+{
+   struct arptabent *   oldest;
+   char * ethhdr;
+   NET net = pkt->net;
+   struct arp_hdr *  arphdr;
+   IFMIB etif = pkt->net->n_mib;    /* mib info for this ethernet interface */
+   PACKET arppkt;
+
+#ifdef IP_MULTICAST
+   /* The following data structure is used to map IP multicast to Ether
+    * broadcast.
+    */
+#ifdef ETHMCAST
+   union {
+      u_char c[4];
+      u_long l;
+   } dest_ip_ptr;
+#endif /* ETHMCAST */
+
+
+   /* If we are broadcasting or multicasting ... */
+   if ((dest_ip == 0xFFFFFFFF) ||  
+      ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask)))
+       || (IN_MULTICAST(ntohl(dest_ip)) ))
+#else
+   if ((dest_ip == 0xFFFFFFFF) ||   /* if we're broadcasting... */
+      ((dest_ip & ~(net->snmask)) == (0xFFFFFFFF & ~(net->snmask))))
+
+#endif /* IP_MULTICAST */
+   {
+      /* get unused or oldest entry in table */
+      oldest = make_arp_entry(dest_ip, pkt->net);
+
+      /* set MAC destination to ethernet broadcast (all FFs) */
+      MEMSET(oldest->t_phy_addr, 0xFF, 6);
+#ifdef IP_MULTICAST
+      /* If n_mcastlist routine is defined in the net structure,
+         map IP mcast to Ether multicast  */
+
+#ifdef ETHMCAST
+      if ((pkt->net->n_mcastlist) && (IN_MULTICAST(ntohl(dest_ip))))
+      {
+         /* If IP mcast to be mapped to Ethernet multicast */
+         dest_ip_ptr.l = dest_ip;
+         oldest->t_phy_addr[0] = 0x01;
+         oldest->t_phy_addr[1] = 0x00;
+         oldest->t_phy_addr[2] = 0x5e;
+         oldest->t_phy_addr[3] = (u_char )(dest_ip_ptr.c[1] & 0x7f);
+         oldest->t_phy_addr[4] = (u_char )dest_ip_ptr.c[2];
+         oldest->t_phy_addr[5] = (u_char )dest_ip_ptr.c[3];
+      }
+#endif /* ETHMCAST */
+#endif /* IP_MULTICAST */
+      return (et_send(pkt, oldest));
+   }
+
+   /* If packet is addressed to this Ethernet interface, and
+    * it's not a loopback address, then don't send it on the wire. 
+    * Instead, free the packet and return ENP_NO_ROUTE  
+    */
+   if ((pkt->fhost == pkt->net->n_ipaddr) &&
+      ((pkt->fhost & htonl(0xFF000000)) != htonl(0x7F000000)))
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_NO_ROUTE;
+   }
+
+   /* not broadcasting, so get a packet for an ARP request */
+   LOCK_NET_RESOURCE(FREEQ_RESID); 
+   arppkt = pk_alloc(arpsize);
+   if (!arppkt)
+   {
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_RESOURCE;
+   }
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   arppkt->nb_prot = arppkt->nb_buff;
+   arppkt->nb_plen = arpsize;
+   arppkt->net = pkt->net;
+
+   /* get unused or oldest entry in table */
+   oldest = make_arp_entry(dest_ip, pkt->net);
+
+   oldest->pending = pkt;           /* packet is "pended", not pk_free()d */
+
+   /* build arp request packet */
+   ethhdr = arppkt->nb_buff + ETHHDR_BIAS;     /* ethernet header at start of buffer */
+   arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */
+
+#ifdef IEEE_802_3
+   arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   arphdr->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+#endif /* IEEE_802_3 */
+
+   arphdr->ar_pro = ARPIP;
+   arphdr->ar_hln = 6;
+   arphdr->ar_pln = 4;
+   arphdr->ar_op = ARREQ;
+   arphdr->ar_tpa = dest_ip;        /* target's IP address */
+   arphdr->ar_spa = pkt->net->n_ipaddr;   /* my IP address */
+   MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6);
+   MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6);     /* destination to broadcast (all FFs) */
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);
+   ET_TYPE_SET(ethhdr, ntohs(ET_ARP));
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+      MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6);
+      MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4);
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6);
+      MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4);
+   }
+#endif   /* NO_CC_PACKING */
+
+#ifdef IEEE_802_3
+   /* If the build supports 802.3 we'll have to send an ARP with an 802.3
+    * header too. Don't return on error codes since we may still be able
+    * to send the real ARP request below.
+    */
+   {
+      PACKET pkt8023;
+      struct snap_hdr * snap;
+      unsigned len8023;
+
+      LOCK_NET_RESOURCE(FREEQ_RESID); 
+      pkt8023 = pk_alloc(arpsize + sizeof(struct snap_hdr) );
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      if (pkt8023)
+      {
+         pkt8023->nb_prot = pkt8023->nb_buff;
+         pkt8023->nb_plen = arpsize + sizeof(struct snap_hdr);
+         pkt8023->net = pkt->net;
+         ethhdr = pkt8023->nb_buff + ETHHDR_BIAS;
+         MEMMOVE(ethhdr, arppkt->nb_buff + ETHHDR_BIAS, 12);
+         len8023 = pkt8023->nb_plen - ETHHDR_SIZE;
+         ET_TYPE_SET(ethhdr, len8023);
+         snap = (struct snap_hdr *)(pkt8023->nb_buff + ETHHDR_SIZE);
+         MEMMOVE(snap, snapdata, 6);
+         snap->type = ET_ARP;
+         MEMMOVE(pkt8023->nb_buff + ETHHDR_SIZE + 8, arphdr, sizeof(struct arp_hdr));
+
+         /* send arp/snap request - if a packet oriented send exists, use it: */
+         if (net->pkt_send)
+            net->pkt_send(pkt8023);  /* driver should free pkt later */
+         else  /* use old raw send */
+         {
+            net->raw_send(pkt8023->net, pkt8023->nb_buff, arpsize);
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt8023);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         }
+         arpReqsOut++;
+      }
+   }
+#endif   /* IEEE_802_3 */
+
+#ifndef IEEE_802_3_ONLY
+   /* send arp request - if a packet oriented send exists, use it: */
+   if (net->pkt_send)
+      net->pkt_send(arppkt);  /* driver should free arppkt later */
+   else  /* use old raw send */
+   {
+      net->raw_send(arppkt->net, arppkt->nb_buff, arpsize);
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(arppkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+   arpReqsOut++;
+#else
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(arppkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif  /* IEEE_802_3_ONLY */
+   
+   return ENP_SEND_PENDING;
+}
+
+
+
+/* FUNCTION: find_oldest_arp()
+ *
+ * Find an ARP table entry or oldest unused table entry
+ *
+ * PARAM1: ip_addr            destination IP address
+ *
+ * RETURNS: arptabent *       LRU or first free entry in arp table
+ * 
+ * Return LRU or first free entry in arp table - preperatory to 
+ * making a new arp entry out of it. The IP address passed is that
+ * of new entry so we can recycle a previous entry for that IP,
+ * if it exists. 
+ *
+ * Old entries are removed from the table.
+ */
+
+struct arptabent * 
+find_oldest_arp(ip_addr dest_ip)
+{
+   struct arptabent *tp;
+   struct arptabent *exact  = (struct arptabent *)NULL;
+   struct arptabent *oldest = (struct arptabent *)NULL;
+   struct arptabent *empty  = (struct arptabent *)NULL;
+   unsigned long lticks = cticks;
+
+   /* find lru (or free) entry */
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+   {
+      /* age out old, pending entries */
+      if (tp->pending)
+      {
+         /* purge if pending for more than one second */
+         if ((lticks - tp->createtime) > TPS)
+         {
+            arp_free_pending(tp);   /* free pending packets */
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+         }
+      }
+      else if ((tp->t_pro_addr != 0) &&
+               ((int)(lticks - tp->createtime) >= arp_ageout) &&
+               ((int)(lticks - tp->lasttime)   >= TPS))
+      {
+         /* entry has "expired" and has not been reference in 1 sec. */
+         tp->t_pro_addr = 0;     /* mark entry as "unused" */
+      }
+
+      if (tp->t_pro_addr == dest_ip)   /* ip addr already has entry */
+      {
+         exact = tp;
+      }
+      else if (tp->t_pro_addr != 0)
+      {
+         if (!oldest || (tp->lasttime < oldest->lasttime))
+            oldest = tp;
+      }
+      else if (!empty)
+         empty = tp;          /* grab first empty slot */
+   }
+
+   return ((exact) ? exact : ((empty) ? empty : oldest));
+}
+
+
+
+/* FUNCTION: make_arp_entry()
+ *
+ * Create a new ARP table entry
+ *
+ * PARAM1: ip_addr            Remote IP address
+ * PARAM2: NET                Net interface
+ *
+ * RETURNS: arptabent *       pointer to arp table entry
+ *
+ * Find the first unused (or the oldest) arp table entry, and make
+ * a new entry to prepare it for an arp reply. If the IP address
+ * already has an entry, the entry is returned with only the
+ * timestamp modified. The ARP timer is started if it isn't already
+ * active.
+ */
+
+struct arptabent *   
+make_arp_entry(ip_addr dest_ip, NET net)
+{
+   struct arptabent *oldest;
+   unsigned long lticks = cticks;
+
+   /* find usable (or existing) ARP table entry */
+   oldest = find_oldest_arp(dest_ip);
+
+   /* If recycling entry, don't leak packets which may be stuck here */
+   if (oldest->pending && (oldest->t_pro_addr != dest_ip))
+   {
+      arp_free_pending(oldest);
+   }
+
+   /* partially fill in arp entry */
+   oldest->t_pro_addr = dest_ip;
+   oldest->net = net;
+   oldest->flags = 0;
+   MEMSET(oldest->t_phy_addr, '\0', 6);   /* clear mac address */
+   oldest->createtime = oldest->lasttime = lticks;
+
+   /* start a ARP timer if there isn't one already */
+   /* update the timeout value if there is a timer */
+   /* time is specified in milliseconds */
+   if (arp_timer == 0)
+   {
+      arp_timer = in_timerset(&cb_arpent_tmo, ARPENT_TMO * 1000, 0);
+   }
+   else
+   {
+      ((struct intimer *)arp_timer)->tmo =
+              ((struct intimer *)arp_timer)->interval + lticks;
+   }
+
+   return oldest;
+}
+
+
+
+/* FUNCTION: arpReply()
+ *
+ * Send an ARP reply
+ * 
+ * PARAM1: PACKET             ARP request packet
+ *
+ * RETURNS: none
+ *
+ * do arp reply to the passed arp request packet. packet 
+ * must be freed (or reused) herein. 
+ */
+
+void
+arpReply(PACKET pkt)
+{
+   PACKET outpkt;
+   struct arp_hdr *in;
+   struct arp_hdr *out;
+   char *ethout;
+   char *ethin;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   outpkt = pk_alloc(arpsize);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (!outpkt)
+   {
+      dtrap();
+      return;
+   }
+
+   outpkt->net = pkt->net;    /* send back out the iface it came from */
+
+   ethin = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS);
+   ethout = outpkt->nb_buff + ETHHDR_BIAS;
+
+#ifdef IEEE_802_3
+   if (MEMCMP(snapdata, pkt->nb_prot - 8, 6) == 0)
+   {
+      /* it's an IEEE 802.3 SNAP header */
+      struct snap_hdr * snap;
+      unsigned len8023;
+      ethin -= 8;
+      in = (struct arp_hdr *)(pkt->nb_prot);
+      out = (struct arp_hdr *)(outpkt->nb_buff + ETHHDR_SIZE + 8);
+      snap = (struct snap_hdr *)(outpkt->nb_buff + ETHHDR_SIZE);
+      outpkt->nb_plen = arpsize + 8;
+      len8023 = outpkt->nb_plen - ETHHDR_SIZE;
+      ET_TYPE_SET(ethout, len8023);  /* IEEE wants length in type field */
+      MEMMOVE(snap, snapdata, 6);
+      snap->type = ET_ARP;
+   }
+   else
+#endif   /* IEEE_802_3 */
+   {
+      ET_TYPE_SET(ethout, ntohs(ET_ARP));   /* 0x0806 - ARP type on ethernet */
+      in = (struct arp_hdr *)(pkt->nb_prot);
+      out = (struct arp_hdr *)(outpkt->nb_buff + ETHHDR_SIZE);
+      outpkt->nb_plen = arpsize;
+   }
+
+   /* prepare outgoing arp packet */
+#ifdef IEEE_802_3
+   out->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   out->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+#endif /* IEEE_802_3 */
+
+   out->ar_pro = ARPIP;
+   out->ar_hln = 6;
+   out->ar_pln = 4;
+   out->ar_op = ARREP;
+   out->ar_tpa = in->ar_spa;     /* swap IP addresses */
+   out->ar_spa = in->ar_tpa;
+   MEMMOVE(out->ar_tha, in->ar_sha, 6);    /* move his MAC address */
+   MEMMOVE(out->ar_sha, outpkt->net->n_mib->ifPhysAddress, 6);  /* fill in our mac address */
+
+   /* prepend ethernet unicast header to arp reply */
+   MEMMOVE(ethout + ET_DSTOFF, ethin + ET_SRCOFF, 6);
+   MEMMOVE(ethout + ET_SRCOFF, outpkt->net->n_mib->ifPhysAddress, 6);
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)out;
+      MEMMOVE(&arwp->data[AR_SHA], out->ar_sha, 6);
+      MEMMOVE(&arwp->data[AR_SPA], &out->ar_spa, 4);
+      MEMMOVE(&arwp->data[AR_THA], out->ar_tha, 6);
+      MEMMOVE(&arwp->data[AR_TPA], &out->ar_tpa, 4);
+   }
+#endif   /* NO_CC_PACKING */
+
+   /* if a packet oriented send exists, use it: */
+   if (outpkt->net->pkt_send)
+   {
+      outpkt->nb_prot = outpkt->nb_buff;
+      outpkt->net->pkt_send(outpkt);
+   }
+   else
+   {
+      outpkt->net->raw_send(pkt->net, outpkt->nb_buff, outpkt->nb_plen);
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(outpkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+   /* input 'pkt' will be freed by caller */
+   arpRepsOut++;
+}
+
+
+
+/* FUNCTION: arprcv()
+ *
+ * Process an incoming arp packet. 
+ * 
+ * PARAM1: PACKET             incoming packet
+ *
+ * RETURNS: int               0 if it was for us
+ *                            ENP_NOT_MINE if packet isn't for this IP address
+ *                            else a negative error code. 
+ */
+
+int
+arprcv(PACKET pkt)
+{
+   struct arp_hdr *arphdr;
+   struct arptabent *tp;
+   char *eth;
+#ifdef IEEE_802_3
+   int      ieee = FALSE;     /* TRUE if received packet is 802.3 */
+#endif
+
+   eth = pkt->nb_prot - (ETHHDR_SIZE - ETHHDR_BIAS);
+   arphdr = (struct arp_hdr *)(pkt->nb_prot);
+
+#ifdef IEEE_802_3
+   /* if SNAP header is present, then we have an 802 packet */
+   if (MEMCMP(snapdata, pkt->nb_prot - 8, 6) == 0)
+   {
+      ieee = TRUE;
+      eth -= 8;
+   }
+#ifdef IEEE_802_3_ONLY
+   else
+      goto drop;
+#endif   /* IEEE_802_3_ONLY */
+#endif   /* IEEE_802_3 */
+
+#ifdef NO_CC_PACKING    /* force ARP fields to local CPU valid boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+      MEMMOVE(&arphdr->ar_tpa, &arwp->data[AR_TPA], 4);
+      MEMMOVE(arphdr->ar_tha, &arwp->data[AR_THA], 6);
+      MEMMOVE(&arphdr->ar_spa, &arwp->data[AR_SPA], 4);
+      MEMMOVE(arphdr->ar_sha, &arwp->data[AR_SHA], 6);
+   }
+#endif   /* NO_CC_PACKING */
+
+#ifdef USE_AUTOIP
+   /* If we're doing Auto Ip, show ARPs to the Auto Ip code. Filter out
+    * our own ARPs which echoed from the hardware (NDIS & some real 
+    * hardware does this). 
+    */
+   {
+      if (MEMCMP(pkt->net->n_mib->ifPhysAddress, eth + ET_SRCOFF, 6) != 0)
+         AutoIp_arp_response(arphdr, pkt->net);
+   }
+#endif
+   USE_ARG(eth);
+
+   /* check ARP's target IP against our net's: */
+#ifdef IP_MULTICAST
+   if ((arphdr->ar_tpa != pkt->net->n_ipaddr) &&   /* if it's not for me.... */
+     (!IN_MULTICAST(ntohl(arphdr->ar_tpa))))
+#else
+   if (arphdr->ar_tpa != pkt->net->n_ipaddr)
+#endif /* IP_MULTICAST */
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);     /* not for us, dump & ret (proxy here later?) */
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return (ENP_NOT_MINE);
+   }
+
+   if (arphdr->ar_op == ARREQ)   /* is it an arp request? */
+   {
+      arpReqsIn++;   /* count these */
+      arpReply(pkt); /* send arp reply */
+      /* make partial ARP table entry */
+      make_arp_entry(arphdr->ar_spa, pkt->net);
+      /* fall thru to arp reply logic to finish our table entry */
+   }
+   else     /* ARP reply, count and fall thru to logic to update table */
+   {
+      arpRepsIn++;
+   }
+
+   /* scan table for matching entry */
+   /* check this for default gateway situations later, JB */
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+   {
+      if (tp->t_pro_addr == arphdr->ar_spa)     /* we found IP address, update entry */
+      {
+#ifdef IEEE_802_3
+         /* If it's an IEEE SNAP (802.3) set flag in arp table entry */
+         if (ieee)
+            tp->flags |= ET_SNAP;
+         else
+            tp->flags |= ET_ETH2;      /* else it's ethernet II */
+#endif   /* IEEE_802_3 */
+
+         MEMMOVE(tp->t_phy_addr, arphdr->ar_sha, 6);   /* update MAC adddress */
+         tp->lasttime = cticks;
+         if (tp->pending)     /* packet waiting for this IP entry? */
+         {
+            arp_send_pending(tp);
+         }
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+         return (0);
+      }
+   }
+
+#ifdef IEEE_802_3_ONLY
+drop:
+#endif /* IEEE_802_3_ONLY */
+   /* fall to here if packet is not in table */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(pkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   return ENP_NOT_MINE;
+}
+
+
+
+/* FUNCTION: send_via_arp()
+ *
+ * Send an IP packet on a media which supports ARP
+ * 
+ * PARAM1: PACKET             packet pointer
+ * PARAM2: ip_addr            destination IP address
+ *
+ * RETURNS: int               0 if packet went to mac sender
+ *                            ENP_SEND_PENDING if awaiting arp reply
+ *                            SEND_FAILED if error 
+ *
+ * Send a packet to the target IP address. The IP address may be the
+ * packet's dest_ip or a gateway/router. We check the ARP cache (and
+ * scan the ARP table if required) for a MAC address matching the
+ * passed dest_ip address. If the MAC address is not already known,
+ * we broadcast an arp request for the missing IP address and attach
+ * the packet to the "pending" pointer. The packet will be sent when
+ * the ARP reply comes in, or freed if we time out. 
+ *
+ * We flush the cache every second to force the regular freeing of any
+ * "pending" packets. We flush every entry on the ageout interval so
+ * bogus ARP addresses won't get permanently wedged in the table.
+ * This happens when someone replaces a PC's MAC adapter but does not
+ * change the PC's IP address. 
+ */
+
+int
+send_via_arp(PACKET pkt, ip_addr dest_ip)
+{
+   struct arptabent *tp;
+   unsigned long lticks = cticks;
+   int err;
+
+   /* don't allow zero dest */
+   if (dest_ip == 0)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return SEND_DROPPED; 
+   }
+
+   /* Force refresh of cache once a second */
+   if ((lticks - cachetime) > TPS)
+      arpcache = (struct arptabent *)NULL;
+
+   /* look at the last ARP entry used. Good chance it's ours: */
+   if (arpcache && (arpcache->t_pro_addr == dest_ip))
+      tp = arpcache;
+   else
+   {
+      /* scan arp table for an existing entry */
+      tp = find_oldest_arp(dest_ip);
+   }
+
+   if (tp->t_pro_addr == dest_ip)   /* we found our entry */
+   {
+      if (tp->pending)  /* arp already pending for this IP? */
+      {
+         if (lilfreeq.q_len < 2)
+         {
+            /* system is depleted of resources - free the
+             * pkt instead of queueing it - so that we are in a
+             * position to receive an arp reply 
+             */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt);  /* sorry, we have to dump this one.. */
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            err = SEND_DROPPED;    /* pkts already waiting for this IP entry */
+         }
+         else
+         {
+            PACKET tmppkt=tp->pending;
+
+            /* queue the packet in pending list */
+            while (tmppkt->next)     /* traverse to the last packet */
+               tmppkt = tmppkt->next;
+            tmppkt->next = pkt;      /* add new pkt to end of list */
+            if (pkt->next)
+            {
+               dtrap();              /* chain of pkts to be sent ??? */
+            }
+            err = ENP_SEND_PENDING; /* packet queued pending ARP reply */
+         }
+      }
+      else  /* just send it */
+      {
+         arpcache = tp;       /* cache this entry */
+         cachetime = lticks;  /* mark time we cached */
+         err = et_send(pkt, tp);
+      }
+   }
+   else
+      /* start the ARP process for this IP address */
+      err = send_arp(pkt, dest_ip);
+
+   return (err);
+}
+
+
+
+#ifdef NET_STATS
+
+/* FUNCTION: arp_stats()
+ * 
+ * Print ARP statistics to output stream
+ *
+ * PARAM1: void *             PIO structure
+ *
+ * RETURNS: int               0 if successful, else error code
+ */
+
+int
+arp_stats(void *pio)
+{
+   struct arptabent *atp;
+   int   i;
+   int   arp_entrys = 0;
+
+   ns_printf(pio, "arp Requests In: %u,   out: %u\n", arpReqsIn, arpReqsOut);
+   ns_printf(pio, "arp Replys   In: %u,   out: %u\n", arpRepsIn, arpRepsOut);
+
+   /* count number of arp entrys in use: */
+   for (i = 0; i < MAXARPS; i++)
+   {
+      if (arp_table[i].t_pro_addr != 0)
+         arp_entrys++;
+   }
+
+   if (arp_entrys > 0)
+   {
+      ns_printf(pio, "X)  MAC Address   iface pend flags   IP      ctime  ltime\n");
+      for (i = 0; i < MAXARPS; i++)
+      {
+         atp = &arp_table[i];
+         if (atp->t_pro_addr != 0)
+         {
+            ns_printf(pio, "%d)  ", i);
+
+            ns_printf(pio, "%02x%02x%02x-%02x%02x%02x ",
+                           atp->t_phy_addr[0],
+                           atp->t_phy_addr[1],
+                           atp->t_phy_addr[2],
+                           atp->t_phy_addr[3],
+                           atp->t_phy_addr[4],
+                           atp->t_phy_addr[5]);
+
+            ns_printf(pio, "  %d   %s    0x%02x %u.%u.%u.%u   %lu  %lu\n",
+                           if_netnumber(atp->net)+1,
+                           atp->pending?"Y":"N",
+                           atp->flags,
+                           PUSH_IPADDR(atp->t_pro_addr),
+                           (long)atp->createtime,
+                           (long)atp->lasttime);
+         }
+      }
+   }
+   else
+   {
+      ns_printf(pio, "Currently no arp table entrys.\n");
+   }
+
+   return 0;
+}
+#endif   /* NET_STATS */
+
+
+
+#ifdef DYNAMIC_IFACES 
+
+/* FUNCTION: clear_arp_entries()
+ *
+ * Clear selected ARP table entries
+ *
+ * PARAM1: ip_addr            IP address of entry to clear
+ * PARAM2: NET                net interface to clear
+ *
+ * RETURNS: int               number of entries cleared
+ * 
+ * Clear any ARP table entries which match the passed IP address
+ * or NET. This is for use when a dynamic interface is removed or
+ * shut down - we don't want ARP entries persisting.
+ */
+
+int
+clear_arp_entries(ip_addr dest_ip, NET ifp)
+{
+   struct arptabent *tp;
+   int   deleted = 0;
+
+   /* find and free matching entries */
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+   {
+      if ((dest_ip && (tp->t_pro_addr == dest_ip)) ||
+          (ifp && (ifp == tp->net)))
+      {
+         if (tp->pending)   /* clear any pending sends */
+         {
+            arp_free_pending(tp);
+         }
+         tp->t_pro_addr = 0;  /* clear table entry */
+         deleted++;
+      }
+   }
+
+   return (deleted);
+}
+#endif /* DYNAMIC_IFACES  */
+
+
+
+/* FUNCTION: cb_arpent_tmo()
+ *
+ * ARP timer callback function
+ *
+ * PARAM1: long               callback parameter (not used)
+ *
+ * RETURNS: none
+ *
+ * Check the ARP table for unresolved entries that have been
+ * pending too long. Assume these entries will never be resolved,
+ * and free their resources.
+ *
+ * If there are no more unresolved entries, cancel the timer.
+ */
+void
+cb_arpent_tmo(long arg)
+{
+   struct arptabent *tp;
+   int arp_count = 0;
+   unsigned long lticks = cticks;
+
+   for (tp = &arp_table[0]; tp < &arp_table[MAXARPS]; tp++)
+   {
+      if (tp->t_pro_addr != 0)
+      {
+         /* age out old, pending entries */
+         if (tp->pending && ((lticks - tp->createtime) > TPS))
+         {
+            /* purge if pending for more than one second */
+            arp_free_pending(tp);   /* free pending packets */
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+         }
+         else if (((int)(lticks - tp->createtime) >= arp_ageout) &&
+                  ((int)(lticks - tp->lasttime)   >= TPS))
+         {
+            /* entry has "expired" and has not been reference in 1 sec. */
+            tp->t_pro_addr = 0;     /* mark entry as "unused" */
+         }
+         else
+            arp_count++;
+      }
+   }
+
+   /* if there are no more "pending" entries, kill the timer */
+   if (arp_count == 0)
+   {
+      in_timerkill(arp_timer);
+      arp_timer = 0;
+   }
+      
+   USE_ARG(arg);
+}
+
+/* FUNCTION: grat_arp()
+ *
+ * grat_arp() - send a gratuitous ARP. 
+ *
+ * PARAM1 - NET
+ * PARAM2 - flag: 0 => ARP, 1 => ARP reply
+ *
+ * RETURNS: Returns 0 if OK, or the usual ENP_ errors 
+ */
+
+int
+grat_arp(NET net, int flag)
+{
+   char * ethhdr;
+   struct arp_hdr *  arphdr;
+   IFMIB etif = net->n_mib;    /* mib info for this ethernet interface */
+   PACKET arppkt;
+
+   /* get a packet for an ARP request */
+   LOCK_NET_RESOURCE(FREEQ_RESID); 
+   arppkt = pk_alloc(arpsize);
+   if (!arppkt)
+   {
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_RESOURCE;
+   }
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   arppkt->nb_prot = arppkt->nb_buff;
+   arppkt->nb_plen = arpsize;
+   arppkt->net = net;
+
+   /* build arp request packet */
+   ethhdr = arppkt->nb_buff + ETHHDR_BIAS;     /* ethernet header at start of buffer */
+   arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */
+
+#ifdef IEEE_802_3
+   arphdr->ar_hd = ARP8023HW; /* net endian 802.3 arp hardware type (ethernet) */
+#else
+   arphdr->ar_hd = ARPHW;     /* net endian Ethernet arp hardware type (ethernet) */
+#endif /* IEEE_802_3 */
+
+   arphdr->ar_pro = ARPIP;
+   arphdr->ar_hln = 6;
+   arphdr->ar_pln = 4;
+   
+   /* ARP req? */
+   if (flag == 0)
+      /* yup */
+      arphdr->ar_op = ARREQ;
+   else
+     /* nope */
+      arphdr->ar_op = ARREP;
+      
+   arphdr->ar_tpa = net->n_ipaddr;        /* target's IP address */
+   arphdr->ar_spa = net->n_ipaddr;   /* my IP address */
+   MEMMOVE(arphdr->ar_sha, etif->ifPhysAddress, 6);
+   MEMSET(ethhdr + ET_DSTOFF, 0xFF, 6);     /* destination to broadcast (all FFs) */
+   MEMMOVE(ethhdr + ET_SRCOFF, etif->ifPhysAddress, 6);
+   ET_TYPE_SET(ethhdr, ntohs(ET_ARP));
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+   {
+      struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+      MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6);
+      MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4);
+
+   /* ARP req? */
+   if (flag == 0)
+      /* yup */      
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6);
+   else
+      /* nope */
+      MEMMOVE(&arwp->data[AR_THA], arphdr->ar_sha, 6);
+      
+      MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4);
+   }
+#endif   /* NO_CC_PACKING */
+
+#ifdef IEEE_802_3
+   /* If the build supports 802.3 we'll have to send an ARP with an 802.3
+    * header too. Don't return on error codes since we may still be able
+    * to send the real ARP request below.
+    */
+   {
+      PACKET pkt8023;
+      struct snap_hdr * snap;
+      unsigned len8023;
+
+      LOCK_NET_RESOURCE(FREEQ_RESID); 
+      pkt8023 = pk_alloc(arpsize + sizeof(struct snap_hdr) );
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      if(pkt8023)
+      {
+         pkt8023->nb_prot = pkt8023->nb_buff;
+         pkt8023->nb_plen = arpsize + sizeof(struct snap_hdr);
+         pkt8023->net = arppkt->net;
+         ethhdr = pkt8023->nb_buff + ETHHDR_BIAS;
+         MEMMOVE(ethhdr, arppkt->nb_buff + ETHHDR_BIAS, 12);
+         len8023 = pkt8023->nb_plen - ETHHDR_SIZE;
+         ET_TYPE_SET(ethhdr, len8023);
+         snap = (struct snap_hdr *)(pkt8023->nb_buff + ETHHDR_SIZE);
+         MEMMOVE(snap, snapdata, 6);
+         snap->type = ET_ARP;
+         MEMMOVE(pkt8023->nb_buff + ETHHDR_SIZE + 8, arphdr, sizeof(struct arp_hdr));
+
+         /* send arp/snap request - if a packet oriented send exists, use it: */
+         if (net->pkt_send)
+            net->pkt_send(pkt8023);  /* driver should free pkt later */
+         else  /* use old raw send */
+         {
+            net->raw_send(pkt8023->net, pkt8023->nb_buff, arpsize);
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt8023);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         }
+         arpReqsOut++;
+      }
+   }
+#endif   /* IEEE_802_3 */
+
+#ifndef IEEE_802_3_ONLY
+   /* send arp request - if a packet oriented send exists, use it: */
+   if (net->pkt_send)
+      net->pkt_send(arppkt);  /* driver should free arppkt later */
+   else  /* use old raw send */
+   {
+      net->raw_send(arppkt->net, arppkt->nb_buff, arpsize);
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(arppkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+   arpReqsOut++;
+#else
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(arppkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif  /* IEEE_802_3_ONLY */
+   
+   return ENP_SEND_PENDING;
+}
+
+
+
+  /* end of file et_arp.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/icmp.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/icmp.c
new file mode 100644
index 0000000..0ec6cec
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/icmp.c
@@ -0,0 +1,633 @@
+/*
+ * FILENAME: icmp.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: icmprcv(), icmp_destun(), icmp_du(), icmp_stats(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1994 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon  */
+/* Portions Copyright 1984 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "pmtu.h"
+
+/* 
+ * Altera Niche Stack Nios port modification:
+ * Fix build warnings 
+ */
+#ifdef ALT_INICHE
+#ifdef IP_RAW
+int   ip_raw_input(PACKET P);
+#endif   /* IP_RAW */
+#endif /* ALT_INICHE */
+
+struct IcmpMib icmp_mib;   /* storage for MIB statistics */
+
+/* the callback for application to get a peek at icmp du packets */
+void (*icmpdu_hook)(PACKET p, struct destun * pdp) = NULL;
+
+
+/* FUNCTION: icmprcv()
+ *
+ * ICMP received packet upcall handler. Returns 0 if we processed the 
+ * packet, or ENP_NOT_MINE, or a negative error code. 
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: 
+ */
+
+#ifdef USER_PING_TSTAMP
+extern u_long user_UTCtime();
+struct align_stamps
+{
+   u_long dtstamp[3]; 
+};
+#endif /* USER_PING_TSTAMP */
+
+int
+icmprcv(PACKET p)      /* the incoming packet */
+{
+   unsigned len;        /* packet length, minus IP & MAC headers */
+   ip_addr host;        /* the foreign host */
+   struct ip * pip;
+   struct ping *  e;
+   unsigned short osum;
+   unsigned short xsum;
+#ifdef FULL_ICMP
+   struct redirect * rd;
+   struct destun *   pdp;
+#endif   /* FULL_ICMP */
+   char sav_ch = 0;
+   int i;
+
+   icmp_mib.icmpInMsgs++;                 /* received one more icmp */
+
+   pip = ip_head(p);                      /* find IP header */
+   len = p->nb_plen - (ip_hlen(pip));     /* strip IP header length */
+   host = p->fhost;                       /* filled in by IP layer */
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      dprintf("ICMP: p[%u] from %u.%u.%u.%u\n", len, PUSH_IPADDR(host));
+#endif
+
+   e = (struct ping *)ip_data(pip);       /* finally, extract ICMP header */
+
+   osum = e->pchksum;
+   e->pchksum = 0;
+
+   if (len&1)
+   {
+      sav_ch = *(((char *) e) + len);
+      ((char *)e)[len] = 0;
+   }
+
+   xsum = ~cksum(e, (len+1)>>1);
+   if (len&1) *(((char *) e) + len) = sav_ch;
+   if (xsum != osum)
+   {
+      e->pchksum = osum;
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ICMP: Bad xsum %04x should have been %04x\n",
+          osum, xsum);
+         if (NDEBUG & DUMP) ip_dump(p);
+      }
+#endif
+      icmp_mib.icmpInErrors++;
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_BAD_HEADER;
+   }
+
+   e->pchksum = osum;
+
+   switch (e->ptype) 
+   {
+   case ECHOREQ:  /* got ping request, send reply */
+      icmp_mib.icmpInEchos++;
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+         dprintf("ICMP: echo reply to %u.%u.%u.%u\n", PUSH_IPADDR(host));
+#endif
+      e->ptype = ECHOREP;
+      e->pchksum = 0;
+      if (len&1)  /* pad odd length packets for checksum routine */
+      {
+         sav_ch = *(((char *) e) + len);
+         ((char *)e)[len] = 0;
+      }
+
+      e->pchksum = ~cksum(e, (len+1)>>1);
+      if (len&1) *(((char *) e) + len) = sav_ch;
+      /* check to see if the destination is the IPv4 broadcast address,
+       * or if the destination is a multicast group address, or if the
+       * destination address is the subnet-directed broadcast 
+       */
+      if ((pip->ip_dest == 0xffffffff) || 
+#ifdef IP_MULTICAST
+          (IN_MULTICAST(ntohl(pip->ip_dest))) ||
+#endif
+          (pip->ip_dest == (p->net->n_ipaddr | (~(p->net->snmask)))))
+      {
+         pip->ip_src = p->net->n_ipaddr;
+      }
+      else pip->ip_src = pip->ip_dest;
+
+      pip->ip_dest = host;
+      icmp_mib.icmpOutEchoReps++;
+      icmp_mib.icmpOutMsgs++;
+      p->fhost = host;
+      p->nb_prot += ip_hlen(pip);      /* move pointer past IP to ICMP */
+      p->nb_plen = len;
+
+      i = ip_write(ICMP_PROT, p);
+      if (i < 0)
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (UPCTRACE))
+            dprintf("icmp: reply failed\n");
+#endif
+      }
+      /* reused p will be freed by net->xxx_send() */
+      return 0;
+   case ECHOREP:
+      icmp_mib.icmpInEchoReps++;
+      
+/* 
+ * Altera Niche Stack Nios port modification
+ */
+#if defined(ALT_INICHE) && !defined(PING_APP) && defined(IP_RAW)
+      return(ip_raw_input(p));
+#endif
+
+      /* The PING appplication expects the nb_prot field to point to
+       * the ICMP header, not the IP as it does here, NOR to the application
+       * data like a TCP or UDP app would. Adjust this here:
+       */
+      p->nb_prot += ip_hlen(pip);      /* move pointer past IP to ICMP */
+      p->nb_plen -= ip_hlen(pip);      /* subtract IP header size */
+#ifdef PING_APP
+      return(pingUpcall(p));
+#else    /* not a real ping app; but report ping reply if debugging... */
+#ifdef NPDEBUG
+      if ((NDEBUG & IPTRACE))
+      {
+         dprintf("Ping (icmp echo) reply from %u.%u.%u.%u, data len %d\n", 
+          PUSH_IPADDR(p->fhost), p->nb_plen);
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return(0);
+#endif   /* PING_APP */
+#ifdef FULL_ICMP
+   case DESTIN:
+      icmp_mib.icmpInDestUnreachs++;
+      pdp = (struct destun *)e;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+      {
+         dprintf("ICMP: got dest unreachable type ");
+         dprintf("%u on %u.%u.%u.%u ", pdp->dcode,
+          PUSH_IPADDR(pdp->dip.ip_dest));
+         dprintf("from %u.%u.%u.%u\n", PUSH_IPADDR(host));
+      }
+#endif   /* NPDEBUG */
+      icmp_du(p, pdp);
+      break;
+   case SOURCEQ:
+      icmp_mib.icmpInSrcQuenchs++;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+      {
+         dprintf("ICMP: source quench from %u.%u.%u.%u\n", PUSH_IPADDR(host));
+         if (NDEBUG & DUMP) ip_dump(p);
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      break;
+   case REDIR:          /* got an icmp redirect */
+      icmp_mib.icmpInRedirects++;
+      rd = (struct redirect *)e;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+      {
+         dprintf("ICMP: rcvd redirect for %u.%u.%u.%u ",
+          PUSH_IPADDR(rd->rdip.ip_dest));
+         dprintf("to %u.%u.%u.%u\n", PUSH_IPADDR(rd->rdgw));
+      }
+#endif   /* NPDEBUG */
+#ifdef IP_ROUTING
+      /* try to add/update route table */
+      add_route(rd->rdip.ip_dest, 0xFFFFFFFF, rd->rdgw, 
+       net_num(p->net), IPRP_ICMP);
+#endif   /* IP_ROUTING */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      break;
+   case TIMEX:
+      icmp_mib.icmpInTimeExcds++;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+      {
+         struct timex * pt =  (struct  timex *)e;
+
+         dprintf("ICMP: timex msg from %u.%u.%u.%u\n",
+          PUSH_IPADDR(p->fhost));
+         dprintf(" about %u.%u.%u.%u\n", PUSH_IPADDR(pt->tip.ip_dest));
+         if (NDEBUG & DUMP) ip_dump(p);
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      break;
+   case PARAM:
+      icmp_mib.icmpInParmProbs++;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+         dprintf("ICMP: got param problem message\n");
+      if (NDEBUG & DUMP)
+      {
+         ip_dump(p);
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      break;
+   case TIMEREQ:
+      icmp_mib.icmpInTimestamps++;
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+         dprintf("ICMP: got timestamp request\n");
+#endif   /* NPDEBUG */
+      e->ptype = TIMEREP;
+      e->pchksum = 0;
+
+#ifdef USER_PING_TSTAMP
+      {
+		  struct tstamp *tsp = (struct tstamp *)e;
+          struct align_stamps *sstmp = (struct align_stamps *)&tsp->stamps;
+
+		  /* 
+		   * user_UTCtime() must return UTC time in htonl((u_long)t) format.
+		   * we set the Receive Timestamp and Transmit Timestamp
+		   */
+		  sstmp->dtstamp[1] = sstmp->dtstamp[2] = user_UTCtime();
+	  }
+#endif /* USER_PING_TSTAMP */
+
+      e->pchksum = ~cksum(e, sizeof(struct tstamp)>>1);
+      pip->ip_src = pip->ip_dest;
+      pip->ip_dest = host;
+      icmp_mib.icmpOutMsgs++;
+      icmp_mib.icmpOutTimestampReps++;
+      p->nb_prot += ip_hlen(pip);      /* move pointer past IP to ICMP */
+      p->nb_plen = sizeof(struct tstamp);
+      p->fhost = host;
+      i = ip_write(ICMP_PROT, p);
+      if (i < 0)
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & UPCTRACE)
+            dprintf("icmp: can't send timestamp reply\n");
+#endif   /* NPDEBUG */
+      }
+      /* re-used packet was pk_free()d by net->send() */
+      return (0);
+   case INFO:
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+         dprintf("icmp: got info request\n");
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      break;
+#endif   /* FULL_ICMP */
+   default:
+#ifdef   NPDEBUG
+      if (NDEBUG & UPCTRACE)
+      {
+         dprintf("icmp: unhandled type %u\n", e->ptype);
+         if (NDEBUG & DUMP) ip_dump(p);
+      }
+#endif   /* NPDEBUG */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_NOT_MINE;
+   }
+#ifdef FULL_ICMP
+   return ENP_NOT_MINE;
+#endif   /* FULL_ICMP */
+}
+
+#ifdef FULL_ICMP
+
+#ifdef NPDEBUG
+static char *dsts[] = 
+{
+   "net", "host", "protocol", "port", "fragmentation needed",
+   "source route failed" };
+#endif   /* NPDEBUG */
+
+
+
+/* FUNCTION: icmp_destun()
+ *
+ * icmp_destun() - Send an ICMP destination unreachable packet.
+ * 
+ * PARAM1: ip_addr host
+ * PARAM2: ip_addr src_addr (source address for outgoing ICMP/IP packet header)
+ * PARAM3: struct ip *ip
+ * PARAM4: unsigned typecode     - type and code fields
+ * PARAM5: net packet came from 
+ *
+ * If the type field is 0, then type is assumed to be DESTIN.
+ *
+ * RETURNS: void
+ */
+
+void
+icmp_destun(ip_addr host,  /* host to complain to */
+   ip_addr src_addr, /* source address for outgoing ICMP/IP packet header */
+   struct ip * ip,   /* IP header of offending packet */
+   unsigned typecode,    /* type & code of DU to send (PROT, PORT, HOST) */
+   NET   net)        /* interface that this packet came in on */
+{
+   PACKET p;
+   struct destun *   d;
+   struct ip * pip;
+   int   i;
+
+#ifdef NPDEBUG
+   if (NDEBUG & PROTERR)
+      dprintf("icmp: sending %s dest unreachable to %u.%u.%u.%u\n",
+      dsts[typecode & 0xFF], PUSH_IPADDR(host));
+#endif   /* NPDEBUG */
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   p = pk_alloc(512 + IPHSIZ);   /* get packet to send icmp dest unreachable */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (p == NULL)
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & IPTRACE)
+         dprintf("icmp: can't alloc pkt\n");
+#endif   /* NPDEBUG */
+      icmp_mib.icmpOutErrors++;
+      return;
+   }
+
+   /* build the addresses in the IP header */
+   pip = (struct ip *)p->nb_prot;
+   pip->ip_src = src_addr;
+   pip->ip_dest = host;
+
+   /* allow space for icmp header */
+   p->nb_prot += sizeof(struct ip);
+   p->nb_plen -= sizeof(struct ip);
+   p->net = net;     /* Put in the interface that this packet came in on */
+
+   d = (struct destun *)p->nb_prot;
+
+   if (typecode & 0xFF00)               /* if the type was sent */
+      d->dtype = (char)(typecode >>8);  /* then use it */
+   else                                 /* else use default */
+      d->dtype = DESTIN;
+   d->dcode = (char)(typecode & 0xFF);
+   d->dno1 = d->dno2 = 0;
+#ifndef ICMP_SUPPRESS_PMTU
+   if ((typecode & 0xFF) == DSTFRAG)
+      d->dno2 = htons(net->n_mtu - net->n_lnh);
+#endif    /* ICMP_SUPPRESS_PMTU */
+   MEMCPY(&d->dip, ip, (sizeof(struct ip) + ICMPDUDATA));
+
+   d->dchksum = 0;
+   d->dchksum = ~cksum(d, sizeof(struct destun)>>1);
+
+   p->nb_plen =  sizeof(struct destun);
+   p->fhost = host;
+   i = ip_write(ICMP_PROT, p);
+   if (i < 0)
+   {
+      icmp_mib.icmpOutErrors++;
+#ifdef   NPDEBUG
+      if (NDEBUG & (IPTRACE|NETERR|PROTERR))
+         dprintf("ICMP: Can't send dest unreachable\n");
+#endif   /* NPDEBUG  */
+      return;
+   }
+   icmp_mib.icmpOutMsgs++;
+   icmp_mib.icmpOutDestUnreachs++;
+   return;
+}
+
+/* FUNCTION: icmp_timex ()
+ *
+ * icmp_timex () - Send an ICMP Time Exceeded message.
+ * 
+ * PARAM1: struct ip * ip - Pointer to IP header of packet in response to which 
+ *         an ICMP Time Exceeded message is being sent
+ * PARAM2: char code - code of ICMP Time Exceeded message
+ *
+ * RETURNS: void
+ */
+
+void icmp_timex (struct ip * ip, char code) 
+{
+   PACKET p;
+   struct timex * tx;
+   struct ip * pip;
+   int i;
+   u_char icmp_pkt_len;
+
+#ifdef NPDEBUG
+   if (NDEBUG & PROTERR)
+      dprintf("icmp: sending ICMP Time Exceeded with code %u to %u.%u.%u.%u\n",
+       code, PUSH_IPADDR((ntohs(ip->ip_src))));
+#endif   /* NPDEBUG */
+
+   icmp_pkt_len = ICMPTIMEX_HDR_LEN + ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN;
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   /* get packet to send ICMP message.  The total length of such a packet is the 
+    * length of the "outer" IP header, length of the ICMP header (ICMPTIMEX_HDR_LEN,
+    * 8 bytes), length of the "inner" IP header, and length of "user" data 
+    * (ICMPTIMEX_PAYLOAD_DATA_LEN, 8 bytes) (just past the "inner" IP header).  The 
+    * latter two items are from the packet that the ICMP Time Exceeded message is 
+    * being sent in response to. */
+   p = pk_alloc(MaxLnh + IPHSIZ + icmp_pkt_len);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (p == NULL)
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & IPTRACE)
+         dprintf("icmp: can't alloc pkt\n");
+#endif   /* NPDEBUG */
+      icmp_mib.icmpOutErrors++;
+      return;
+   }
+
+   /* build the addresses in the IP header */
+   pip = (struct ip *)p->nb_prot;
+   /* source IP address of packet is our address (i.e., destination IP address 
+    * in the datagram whose reassembly timed out) */
+   pip->ip_src = ip->ip_dest;
+   /* the destination address is the same as the source IP address of the 
+    * datagram whose reassembly timed out */
+   pip->ip_dest = ip->ip_src;
+
+   /* move past space for IP header to get to start of ICMP header */
+   p->nb_prot += sizeof(struct ip);
+
+   tx = (struct timex *) p->nb_prot;
+
+   tx->ttype = TIMEX;
+   tx->tcode = code;
+   tx->tno1 = tx->tno2 = 0;
+   MEMCPY(&tx->tip, ip, (ip_hlen(ip) + ICMPTIMEX_PAYLOAD_DATA_LEN));
+
+   tx->tchksum = 0;
+   tx->tchksum = ~cksum(tx, (icmp_pkt_len>>1));
+
+   p->nb_plen = icmp_pkt_len;
+   /* p->fhost is expected to be in network byte order */
+   p->fhost = pip->ip_dest;
+   i = ip_write(ICMP_PROT, p);
+   if (i < 0)
+   {
+      icmp_mib.icmpOutErrors++;
+#ifdef   NPDEBUG
+      if (NDEBUG & (IPTRACE|NETERR|PROTERR))
+         dprintf("ICMP: Can't send Time Exceeded\n");
+#endif   /* NPDEBUG  */
+      return;
+   }
+   icmp_mib.icmpOutMsgs++;
+   icmp_mib.icmpOutTimeExcds++;
+   return;
+}
+
+
+/* FUNCTION: icmp_du()
+ * 
+ *  process an incoming ICMP destination unreachable packet.
+ *
+ * PARAM1: PACKET p
+ * PARAM2: struct destun * pdp
+ *
+ * RETURNS: void
+ */
+
+void  
+icmp_du(PACKET p, struct destun * pdp)
+{
+   /* see if user app wants notification first */
+   if (icmpdu_hook)
+      icmpdu_hook(p, pdp);
+
+#ifdef INCLUDE_TCP
+   /* Tell the sockets layer so it can correct the problem. */
+   so_icmpdu(p, pdp);   /* this call should free packet p */
+#else
+
+#ifndef IP_PMTU
+   /* if it's a datagram-too-big message, ignore it -- As the
+    * build isn't using PMTU Discovery this packet is most 
+    * probably a Denial of Service Attack.
+    */
+    if(pdp->dcode == DSTFRAG)
+    {
+       goto done;
+    }
+#else  /* IP_PMTU */
+   /* if this is a datagram-too-big message, update the Path MTU cache */
+   if (pdp->dcode == DSTFRAG)
+      pmtucache_set(pdp->dip.ip_dest, htons(pdp->dno2));
+#endif
+
+done:
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p); /* else just free packet */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif   /* INCLUDE_TCP */
+}
+
+#endif   /* FULL_ICMP */
+
+#ifdef NET_STATS
+
+
+
+/* FUNCTION: icmp_stats()
+ * 
+ * icmp_stats() - Printf info about icmp MIB statistics.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+icmp_stats(void * pio)
+{
+   ns_printf(pio,"ICMP layer stats:\n");
+   ns_printf(pio,"icmpInMsgs %lu    icmpInErrors %lu\n",
+    icmp_mib.icmpInMsgs, icmp_mib.icmpInErrors);
+   ns_printf(pio,"In counters: DestUnreach %lu   TimeExceed %lu   ParmProb %lu\n",
+    icmp_mib.icmpInDestUnreachs, icmp_mib.icmpInTimeExcds,
+    icmp_mib.icmpInParmProbs);
+   ns_printf(pio,"SrcQuench %lu   Redirect %lu   Echo(ping) %lu   EchoReps %lu\n",
+    icmp_mib.icmpInSrcQuenchs, icmp_mib.icmpInRedirects,
+    icmp_mib.icmpInEchos, icmp_mib.icmpInEchoReps);
+   ns_printf(pio,"Timestmp  %lu   TStmpRep %lu    AddrMasks %lu   AddrMaskRep %lu\n",
+    icmp_mib.icmpInTimestamps, icmp_mib.icmpInTimestampReps,
+    icmp_mib.icmpInAddrMasks, icmp_mib.icmpInAddrMaskReps);
+
+   ns_printf(pio,"icmpOutMsgs %lu    icmpOutErrors %lu\n",
+    icmp_mib.icmpOutMsgs, icmp_mib.icmpOutErrors);
+   ns_printf(pio,"Out counts:  DestUnreach %lu   TimeExceed %lu   ParmProb %lu\n",
+    icmp_mib.icmpOutDestUnreachs, icmp_mib.icmpOutTimeExcds,
+    icmp_mib.icmpOutParmProbs);
+   ns_printf(pio,"SrcQuench %lu   Redirect %lu   Echo(ping) %lu   EchoReps %lu\n",
+    icmp_mib.icmpOutSrcQuenchs, icmp_mib.icmpOutRedirects,
+    icmp_mib.icmpOutEchos, icmp_mib.icmpOutEchoReps);
+   ns_printf(pio,"Timestmp  %lu   TStmpRep %lu    AddrMasks %lu   AddrMaskRep %lu\n",
+    icmp_mib.icmpOutTimestamps, icmp_mib.icmpOutTimestampReps,
+    icmp_mib.icmpOutAddrMasks, icmp_mib.icmpOutAddrMaskReps);
+
+   return 0;
+}
+
+#endif   /* NET_STATS */
+
+/* end of file icmp.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/iface.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/iface.c
new file mode 100644
index 0000000..5fb6b6a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/iface.c
@@ -0,0 +1,884 @@
+/*
+ * FILENAME: iface.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *  Generic interface support routines, including dynamic interface API.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: ni_create(), ni_delete(), ni_get_config(), ni_set_config()
+ * ROUTINES: new_iface(), del_iface(), if_listifs(), if_config(),
+ * ROUTINES: if_getbyname(), if_enable(), if_disable(), if_killsocks(),
+ * ROUTINES: ni_set_state(), if_getbynum(), isbcast(), reg_type(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1994 by NetPort Software */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#ifdef INCLUDE_ARP
+#include "arp.h"
+#endif
+
+#ifdef INCLUDE_TCP
+#ifdef MINI_TCP
+#include "mtcp.h"
+#else
+#include "tcpport.h"
+#include "../tcp/in_pcb.h"
+#endif /* MINI_TCP */
+#endif   /* INCLUDE_TCP */
+
+#ifdef IN_MENUS   /* need this for dynamic iface test menu */
+#include "menu.h"
+NET   if_getbypio(void * pio);   /* export for other modules */
+#endif
+
+
+queue netlist;          /* master list of nets, static & dynamic */
+
+#ifdef DYNAMIC_IFACES   /* create and delete can be ifdeffed out */
+
+#ifndef PLLISTLEN    /* allow override from ipport.h */
+#define PLLISTLEN 4  /* numer of protocols MACs can support */
+#endif
+
+/* master list of all MAC level protocols (IP, ARP, etc) */
+unshort  protlist[PLLISTLEN]; /* zero means unused entry */
+
+
+#ifndef NULLIP
+#define  NULLIP   0L
+#endif
+
+void if_killsocks(NET ifp);
+
+/* FUNCTION: ni_create()
+ *
+ * This creates a new dynamic interface structure. Once the memory struct
+ * and linked list are set up, the passed callback is called to set up
+ * hardware specific parameters like MTU size and callbacks - similar to
+ * what the "prep_" routine does for a static device. The various
+ * MAC protocols used by the system are registered with the device via
+ * the reg_typew and the device is then configured as UP.
+ *
+ * PARAM1: NET * newifp
+ * PARAM2: int (*create_device)(NET newifp, void * bindinfo)
+ * PARAM3: char * name
+ * PARAM4: void * bindinfo
+ *
+ * RETURNS: Returns 0 if OK, or an ENP_ error code. The address of the
+ * new structure is returned in the passed "newifp" parameter
+ */
+
+int
+ni_create(NET * newifp,    /* OUT - created handle */
+          int (*create_device)(NET newifp, void * bindinfo),   /* IN */
+          char * name,     /* IN */
+          void * bindinfo) /* IN */
+{
+   int   i;
+   int   err;
+   int   iface;      /* index into nets[], for legacy support */
+   struct net *   ifp;
+   struct IfMib * mib;
+
+   iface = netlist.q_len;  /* index to new interface */
+
+   /* Make sure we have spare slots in various net arrays */
+   if(iface >= MAXNETS)
+      return ENP_RESOURCE;
+
+   /* first allocate the memory */
+   ifp = (struct net *)NET_ALLOC(sizeof(struct net));
+   if (!ifp)
+      return ENP_NOMEM;
+   mib = &ifp->mib;   /* set MIB pointer for backward compatability */
+
+   /* set up pointers - add net to list */
+   putq(&netlist, ifp);
+   ifp->n_mib = mib;
+
+   /* support the old style nets[] array */
+   nets[iface] = ifp;
+
+   ifp->n_flags = NF_DYNIF;      /* set flags field */
+   if (name != NULL)
+   {
+      MEMCPY(ifp->name, name, IF_NAMELEN-1);
+      ifp->name[IF_NAMELEN-1] = 0;
+   }
+   err = (*create_device)(ifp, bindinfo);
+   if (err)
+      goto bad_create;
+
+   /* don't allow the max header or MTU size to grow. If this is
+    * a problem then set the MaxXxx ints at init time *BEFORE* 
+    * calling NetInit() or ip_startup().
+    */
+   if ((ifp->n_lnh > MaxLnh) ||
+       (ifp->n_mtu > MaxMtu))
+   {
+      dtrap();    /* programming, see note above */
+      err = ENP_LOGIC;
+      goto bad_create;
+   }
+
+   if (ifp->n_reg_type)    /* do we need to register types? */
+   {
+      for (i = 0; i < PLLISTLEN; i++)
+      {
+         if (protlist[i] == 0)
+            break;
+         ifp->n_reg_type(protlist[i], ifp);
+      }
+   }
+
+   err = ni_set_state(ifp, NI_UP);
+   if (err)
+      goto bad_create;
+
+   /* interface is created, no error */
+   ifNumber = netlist.q_len;
+   *newifp = ifp;
+   return 0;   /* OK return */
+
+bad_create:
+   /* user create routine returned an error. */
+   qdel(&netlist, (void*)ifp);      /* delete from list */
+   NET_FREE(ifp);
+   nets[iface] = NULL;
+   return err;
+}
+
+
+/* FUNCTION: ni_get_config()
+ *
+ * get IP address and subnet for a particular device.
+ *
+ * PARAM1: NET ifp
+ * PARAM2: struct niconfig_0 * cfg
+ *
+ * RETURNS: 0
+ */
+
+int
+ni_get_config(NET ifp, struct niconfig_0 * cfg)
+{
+   cfg->n_ipaddr = ifp->n_ipaddr;
+   cfg->snmask = ifp->snmask;
+
+   return 0;      /* OK return */
+}
+
+
+/* FUNCTION: ni_set_config()
+ * 
+ * set IP address and subnet for a particular device.
+ *
+ * PARAM1: NET ifp
+ * PARAM2: struct niconfig_0 * cfg
+ *
+ * RETURNS: 0
+ */
+
+int
+ni_set_config(NET ifp, struct niconfig_0 * cfg)
+{
+   int   err;
+
+   err = ni_set_state(ifp, NI_DOWN);   /* shut down iface around this...*/
+   if(err)
+      return err;
+
+   ifp->n_ipaddr = cfg->n_ipaddr;      /* set passed info */
+   ifp->snmask = cfg->snmask;
+
+   /* build broadcast addresses */
+   if(ifp->n_ipaddr != 0)
+   {
+      ifp->n_netbr = ifp->n_ipaddr | ~(ifp->snmask);
+      ifp->n_netbr42 = ifp->n_ipaddr & ifp->snmask;
+      ifp->n_subnetbr = ifp->n_ipaddr | ~(ifp->snmask);
+   }
+
+   err = ni_set_state(ifp, NI_UP);     /* restart iface */
+
+   return err;
+}
+
+
+/* FUNCTION: ni_delete()
+ * 
+ * PARAM1: NET ifp
+ *
+ * RETURNS: 
+ */
+
+int
+ni_delete(NET ifp)
+{
+   int iface;
+
+   if ((ifp->n_flags & NF_DYNIF) == 0) /* not a dynamic iface */
+      return ENP_PARAM;
+
+   ni_set_state(ifp, NI_DOWN);            /* mark iface as down */
+
+   if (qdel(&netlist, (void*)ifp)==NULL)  /* delete from list */
+      return ENP_PARAM;          /* interface not in queue */
+
+   /* remove ifp from nets[], filling it's hole */
+   for(iface = 0; iface < MAXNETS; iface++)
+   {
+      if(nets[iface] == ifp)     /* found ifp to delete */
+      {
+         /* move following nets[] entrys up 1 slot to cover deleted net */
+         for( ;  iface < (MAXNETS - 1); iface++)
+            nets[iface] = nets[iface + 1];
+         break;
+      }
+   }
+
+   ifNumber = netlist.q_len;     /* fix global if c   ount */
+   NET_FREE(ifp);
+
+   return 0;   /* no way this can fail? */
+}
+
+#ifdef IN_MENUS   /* need this for dynamic iface test menu */
+
+int   new_iface(void * pio);
+int   del_iface(void * pio);
+int   if_enable(void * pio);
+int   if_disable(void * pio);
+int   if_listifs(void * pio);
+int   if_config(void * pio);
+
+struct menu_op dynif_menu[8]   =  {
+   "dynif",  stooges, "Dynamic Interface menu" ,    /* menu ID */
+   "nicreate",    new_iface,     "Create new network interface",
+   "nidelete",    del_iface,     "Delete network interface",
+   "niup",        if_enable,     "Enable net interface",
+   "nidown",      if_disable,    "Disable net interface",
+   "niconfig",    if_config,     "Configure interface IP info",
+   "nilist",      if_listifs,    "List current interfaces",
+   NULL,
+};
+
+#ifdef MAC_LOOPBACK
+/* MAC loopback create routine (in macloop.c) */
+extern   int   lb_create(struct net * ifp, void * bindinfo);
+#endif   /* MAC_LOOPBACK */
+
+#ifdef USE_PPP
+/* ppp interface create routine */
+extern   int   ppp_create(struct net * ifp, void * bindinfo);
+#endif   /* USE_PPP */
+
+/* FUNCTION: new_iface()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+#define IF_MAXNAMES  12
+static char ifnames[IF_MAXNAMES][IF_NAMELEN];
+
+int
+new_iface(void * pio)
+{
+   int   i;
+   int   err;
+   NET   net;
+   char *   name;
+   char *   type;
+   char *   cp =  nextarg(((GEN_IO)pio)->inbuf);
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio, "please enter a name & type for new loopback iface\n");
+      ns_printf(pio, "valid types include:\n");
+#ifdef MAC_LOOPBACK
+      ns_printf(pio, "   lo\n");
+#endif
+#ifdef USE_PPP
+      ns_printf(pio, "   ppp\n");
+#endif
+      return -1;
+   }
+
+   /* get name buffer for ni_create to use */
+   name = NULL;
+   for(i = 0; i < IF_MAXNAMES; i++)
+   {
+      if(ifnames[i][0] == 0)  /* unused entry */
+      {
+         name = &ifnames[i][0];
+         break;
+      }
+   }
+   if (!name)
+      return -1;
+
+   strcpy(name, cp);       /* copy name arg into new buffer */
+   type = nextarg(cp);
+   cp = strchr(name, ' '); /* get end of first arg (name) */
+   if(cp)
+      *cp = '\0';          /* null terminate first arg */
+
+   err = -1;               /* assume error */
+
+#ifdef MUTE_WARNS
+   /* some compilers give a bogus warning below if we don't assign a
+    * gratuitous default value to net.
+    */
+    net = (NET)(netlist.q_head);
+#endif   /* MUTE_WARNS */
+#ifdef MAC_LOOPBACK
+   if(strnicmp(type, "lo", 2) == 0)
+   {
+      err = ni_create(&net, lb_create, name, NULL);
+   }
+#endif   /* MAC_LOOPBACK */
+#ifdef USE_PPP
+   if(strnicmp(type, "ppp", 3) == 0)
+   {
+      err = ni_create(&net, ppp_create, name, NULL);
+   }
+#endif   /* USE_PPP */
+
+   if (err)
+   {
+      ns_printf(pio, "Error %d creating iface name '%s' of type '%s'\n", 
+         err, name, type);
+      *name = 0;     /* free name buffer (mark as unused) */
+   }
+   else
+      ns_printf(pio, "Created iface %s, - %s\n", name, net->n_mib->ifDescr);
+
+   return err;
+}
+
+
+/* FUNCTION: del_iface()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+del_iface(void * pio)
+{
+   int   i;
+   int   err;
+   struct net *   net;
+   char *   cp =  nextarg(((GEN_IO)pio)->inbuf);
+   char *   netname;
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio, "enter a net name to delete\n");
+      return -1;
+   }
+   for (net = (struct net *)(netlist.q_head); net; net = net->n_next)
+   {
+      if (strcmp((char*)net->name, cp) == 0)
+         break;
+   }
+   if (!net)
+   {
+      ns_printf(pio, "didn't find interface \"%s\"\n", cp);
+      return -1;
+   }
+   netname = net->name;  /* save name to free if iface frees OK */
+   err = ni_delete(net);
+   /* since we found the iface in the list, assume error return means 
+    * it's not a static iface.
+    */
+   if (err)
+      ns_printf(pio, "%s is not a dynamic interface\n", cp);
+   else
+   {
+      /* if the name of the deleted iface is a string in our local static
+       * name buffer table, free the entry:
+       */
+      for(i = 0; i < IF_MAXNAMES; i++)
+      {
+         if(netname == &ifnames[i][0])    /* found name in table */
+         {
+            ifnames[i][0] = 0;      /* clear entry */
+            break;
+         }
+      }
+      ns_printf(pio, "deleted iface %s\n", cp);
+   }
+
+   return err;
+}
+
+/* FUNCTION: if_listifs()
+ * 
+ * list the current interfaces 
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+if_listifs(void * pio)
+{
+   NET   ifp;
+   IFMIB mib;
+   int   i = 1;   /* Ones based iface index */
+
+   for(ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next)
+   {
+      mib = ifp->n_mib;
+      ns_printf(pio, "%d - %s - %s ",
+         i++, ifp->name, mib->ifDescr);
+
+      ns_printf(pio, "(Admin:%s, Oper:%s)\n",
+         (mib->ifAdminStatus==NI_UP)?"up":"down" ,
+         (mib->ifOperStatus==NI_UP)?"up":"down" );
+   }
+   return 0;
+}
+
+
+/* FUNCTION: if_config()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+if_config(void * pio)
+{
+   char *   name;
+   char *   addr = NULL;
+   char *   mask = NULL;
+   unsigned bits;
+   NET ifp;
+   struct niconfig_0 cfg;
+
+   name = nextarg(((GEN_IO)pio)->inbuf);
+   if (*name)
+   {
+      addr = nextarg(name);
+   }
+   if (addr && *addr)
+   {
+      mask = nextarg(addr);
+      *(addr-1) = 0;    /* null terminate name text */
+      if (mask && *mask)
+      {
+         *(mask-1) = 0; /* null terminate addr text */
+      }
+   }
+   if (!(*name) || !(*addr))
+   {
+      ns_printf(pio, "specify if's name, ip_addr, [mask]\n");
+      return -1;
+   }
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+      if (strncmp(ifp->name, name, strlen(ifp->name)) == 0)
+      break;
+
+   if (!ifp)
+   {
+      ns_printf(pio, "Can't find iface %s\n", name);
+      return -1;
+   }
+   name = parse_ipad(&(cfg.n_ipaddr), &bits, addr);
+   if (name)
+   {
+      ns_printf(pio, "IP address parse error: %s\n", name);
+      return -1;
+   }
+   if (*mask)
+   {
+      name = parse_ipad(&(cfg.snmask), &bits, mask);
+      if (name)
+      {
+         ns_printf(pio, "subnet mask parse error: %s\n", name);
+         return -1;
+      }
+   }
+   else
+   {
+      cfg.snmask = 0L;
+      while (bits--)
+         cfg.snmask = (cfg.snmask << 1) | 1;
+   }
+   ni_set_config(ifp, &cfg);
+   return 0;
+}
+
+
+/* FUNCTION: if_enable()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+if_enable(void * pio)
+{
+   int   err;
+   NET   ifp;
+
+   ifp = if_getbypio(pio);
+   if(ifp == NULL)
+      return -1;
+
+   err = ni_set_state(ifp, NI_UP);
+   if(err)
+      ns_printf(pio, "Error %d enabling %s\n", err, ifp->name);
+   else
+      ns_printf(pio, "Enabled %s\n", ifp->name);
+
+   return err;
+}
+
+
+
+/* FUNCTION: if_disable()
+ *
+ * API call to disable an interface
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+if_disable(void * pio)
+{
+   int   err;
+   NET   ifp;
+
+   ifp = if_getbypio(pio);
+   if(ifp == NULL)
+      return -1;
+
+   err = ni_set_state(ifp, NI_DOWN);
+   if(err)
+      ns_printf(pio, "Error %d shuting down %s\n", err, ifp->name);
+   else
+      ns_printf(pio, "Shut down %s\n", ifp->name);
+
+   return (err);
+}
+
+#endif   /* IN_MENUS */
+
+
+/* FUNCTION: ni_set_state()
+ * 
+ * The NI API entry point to turn a network interface on or off.
+ * This is passed the NET and a code - NI_UP or NI_DOWN, from net.h
+ * NET is enabled or disabled, and the MIB ifAdminStatus flags set.
+ * Any sockets using the net are brutally terminated. 
+ * NET interfaces should toggle-able back and forth with this call.
+ * No check is made of the net's prior state, it is simple pushed 
+ * toward the desired state.
+ *
+ * PARAM1: NET ifp
+ * PARAM2: int opcode
+ *
+ * RETURNS: 0 if OK or ENP_ error from net's n_setstate routine.
+ */
+
+int
+ni_set_state(NET ifp, int opcode)
+{
+   int   err = 0;
+
+   if ((opcode != NI_DOWN) &&
+       (opcode != NI_UP))
+   {
+      return ENP_PARAM;
+   }
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   if (opcode == NI_DOWN)  /* clean up system tables */
+   {
+#ifdef INCLUDE_TCP
+      if_killsocks(ifp);      /* kill this iface's sockets */
+#endif   /* INCLUDE_TCP */
+      del_route(0, 0, if_netnumber(ifp));    /* delete any IP routes */
+      clear_arp_entries(NULLIP, ifp);        /* delete any ARP entries */
+   }
+
+   /* force if-mib AdminStatus flag to correct setting. This will
+    * keep devices without n_setstate() calls from receiving any
+    * packet to send from ip2mac().
+    */
+   if (opcode == NI_UP)
+      ifp->n_mib->ifAdminStatus = NI_UP;
+   else
+      ifp->n_mib->ifAdminStatus = NI_DOWN;
+
+   ifp->n_mib->ifLastChange = cticks * (100/TPS);
+   if (ifp->n_setstate) /* call state routine if any */
+      err = ifp->n_setstate(ifp, opcode);
+   else
+      err = 0; /* no routine == no error */
+
+   if(!err)
+   {
+      /* Get here if setstate was OK - set ifOperStatus */
+      if (opcode == NI_UP)
+         ifp->n_mib->ifOperStatus = NI_UP;
+      else
+         ifp->n_mib->ifOperStatus = NI_DOWN;
+   }
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   return err;
+}
+
+#endif   /* DYNAMIC_IFACES */
+
+
+/* FUNCTION: if_getbynum()
+ *
+ * Gets an interface pointer from the index number. This is the
+ * inverse of net_num() in ipnet.c - these two routines interconvert
+ * interface indexs<->pointers. Note that this handles dynamic
+ * interfaces as well as static.
+ *
+ * PARAM1: int ifnum - 0 based index to interface
+ *
+ * RETURNS: Returns NET pointer, or NULL if out of range
+ */
+
+NET
+if_getbynum(int ifnum)
+{
+   NET ifp;
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+   {
+      if(ifnum-- == 0)
+         return ifp;
+   }
+   dtrap();
+   return NULL;   /* list is not long enough */
+}
+
+
+/* FUNCTION: isbcast()
+ *
+ * isbcast(ifc, addr) - See if the address pointed to by addr is a 
+ * broadcast for the link layer interface ifc.
+ *
+ * 
+ * PARAM1: NET ifc
+ * PARAM2: unsigned char * addr
+ *
+ * RETURNS:  Returns TRUE if broadcast, else false. 
+ */
+
+int
+isbcast(NET ifc, unsigned char * addr)
+{
+#ifndef MULTI_HOMED
+   if (ifc != nets[0])
+      panic("isbcast: bad net");
+#endif
+
+#if (ALIGN_TYPE > 2)
+   /* On systems with 32bit alignment requirements we have to make
+    * sure our tests are aligned. Specifically, this results in "data
+    * abort" errors on the Samsung/ARM port. 
+    */
+   if((u_long)addr & (ALIGN_TYPE - 1))
+   {
+      /* check first two bytes */
+      if ((u_short)*(u_short*)(addr) != 0xFFFF)
+         return(FALSE);
+      if ((u_long)(*(u_long*)(addr + 2)) != 0xFFFFFFFF)
+         return FALSE;
+   }
+   else
+#endif /* ALIGN_TYPE > 4 */
+   {
+      /* check first four bytes for all ones. Since this is the fastest
+       * test, do it first
+       */
+      if ((u_long)(*(u_long*)addr) != 0xFFFFFFFF)
+         return FALSE;
+
+      /* check last two bytes */
+      if ((u_short)*(u_short*)(addr+4) != 0xFFFF)
+         return(FALSE);
+   }
+   
+   /* now reject any line type packets which don't support broadcast */
+   if ((ifc->n_mib->ifType == PPP) ||
+       (ifc->n_mib->ifType == SLIP))
+   {
+      return FALSE;
+   }
+
+   /* passed all tests, must be broadcast */
+   return(TRUE);
+}
+
+
+/* FUNCTION: reg_type()
+ *
+ * reg_type() - register prot type with a net drivers 
+ *
+ * 
+ * PARAM1: unshort type
+ *
+ * RETURNS: Returns 0 if OK, else non-zero error code. 
+ */
+
+int
+reg_type(unshort type)
+{
+   NET ifp;
+   int   e;
+
+#ifdef DYNAMIC_IFACES
+   unsigned i;
+   
+   /* add to master protocol list */
+   for (i = 0; i < PLLISTLEN; i++)
+   {
+      if (protlist[i] == type)   /* type already in list */
+         break;
+      if (protlist[i] == 0)      /* Found empty slot */
+      {
+         protlist[i] = type;     /* add new protocol type */
+         break;
+      }
+   }
+   if (i >= PLLISTLEN)
+      return ENP_RESOURCE;
+#endif   /* DYNAMIC_IFACES */
+
+   /* loop thru list of nets, making them all look at new type */
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+   {
+      if (ifp->n_reg_type)    /* make sure call exists */
+      {
+         e = (ifp->n_reg_type)(type, ifp);
+         if (e)
+            return e;   /* bails out if error */
+      }
+   }
+   return 0;   /* OK code */
+}
+
+#ifdef INCLUDE_TCP
+
+/* FUNCTION: if_killsocks()
+ * 
+ * This should find all the sockets associateds with a passed NET and 
+ * shut them down, ideally with a TCP reset for TCP sockets.
+ * Called by ni_set_state() whenever it is bringing down an interface.
+ *
+ * PARAM1: NET ifp - net that is going down
+ *
+ * RETURNS: void - this is a "best effort" routine.
+ */
+
+      /* kill this NETs sockets */
+void
+if_killsocks(NET ifp)
+{
+   struct socket * so;
+   struct socket * next;
+   NET      so_ifp;     /* interface of sockets in list */
+
+   /* reset any sockets with this iface IP address */
+   so = (struct socket *)(soq.q_head);
+   while(so)
+   {
+      if(so->so_pcb)
+         so_ifp = so->so_pcb->ifp;
+      else
+         so_ifp = NULL;
+      next = (struct socket *)so->next;
+      if (so_ifp == ifp)
+      {
+         /* this is a direct heavy-handed close. A reset is sent
+          * and all data is lost. The user should really have closed
+          * all the sockets gracfully first.... 
+          */
+         soabort(so);
+      }
+      so = next;
+   }
+}
+
+#endif   /* INCLUDE_TCP */
+
+
+#ifdef IN_MENUS
+
+/* FUNCTION: if_getbyname()
+ *
+ * Gets an interface pointer for the interface matching passed name.
+ *
+ * PARAM1: char * name;
+ *
+ * RETURNS: Returns NET pointer, or NULL if name no found
+ */
+
+NET
+if_getbyname(char * name)
+{
+   NET ifp;
+
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+      if (strncmp(ifp->name, name, strlen(ifp->name)) == 0)
+         break;
+
+   return ifp;
+}
+
+
+
+/* FUNCTION: if_getbypio()
+ *
+ * Gets an interface pointer matching the name in the passed PIO
+ * inbuf buffer 
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: Returns NET pointer, or NULL if name no found
+ */
+
+NET
+if_getbypio(void * pio)
+{
+   char * name;
+
+   name = nextarg(((GEN_IO)pio)->inbuf);
+   return(if_getbyname(name));
+}
+#endif
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip.c
new file mode 100644
index 0000000..8a60874
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip.c
@@ -0,0 +1,1407 @@
+/*
+ * FILENAME: ip.c
+ *
+ * Copyright 1997-2002 InterNiche Technologies Inc. All rights reserved
+ *
+ * This contains the base IP code except the received packet demuxer.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: ip_init(), ip_bldhead(), ip_write_internal(), ip_write(), 
+ * ROUTINES: ip_raw_write(), ip_fragment(), ip_mymach(), ip_dump(), 
+ * ROUTINES: iproute(), add_route(), del_route(), ip_data(), ip_optlen(), 
+ * ROUTINES: ip_copypkt()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon  */
+/* Portions Copyright 1984 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "arp.h"
+#include "ip.h"
+#include "icmp.h"
+#include "ip_reasm.h"
+
+static unsigned uid = 1;      /* base for unique IP packet ID */
+
+struct IpMib   ip_mib;     /* IP stats for snmp */
+
+#ifdef IP_ROUTING
+RTMIB    rt_mib;
+unsigned ipRoutes = RT_TABS;
+#endif   /* IP_ROUTING */
+
+#ifdef IP_MULTICAST
+int   ipmc_outopt(PACKET p, u_char prot);
+#endif   /* IP_MULTICAST */
+
+#ifdef IP_FRAGMENTS
+int   ip_fragment(PACKET p, ip_addr firsthop);
+#endif
+
+#ifdef IPSEC
+int   IPSecInit(void);
+int   ipsec_outbound(PACKET * pp);
+#endif
+
+/* function to obtain the length of the largest interrupt-safe buffer */
+extern unsigned pk_get_max_intrsafe_buf_len (void);
+/* compute the minimum of two quantities A and B */
+#define MIN(A,B) (((A)<(B))?(A):(B))
+/* number of fragments upto which we use ip_fragment_lc () for fragmentation 
+ * (but only if the original IP datagram passed to ip_fragment () is in an 
+ * interrupt-safe buffer) */
+#define FRAG_SCHEME_SWITCH_THRESHOLD 3
+
+/* FUNCTION: ip_init()
+ *
+ * ip_init() - Intialize the internet layer.
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: Returns SUCCESS (0) if everything went 
+ * OK, else returns a non-zero error code. 
+ */
+
+int
+ip_init(void)
+{
+
+   /* register IP type with link layer drivers */
+   if (reg_type(IP_TYPE) != 0)
+   {   
+#ifdef NPDEBUG
+      dprintf("IP_INIT: unable to register type with MAC driver\n");
+#endif
+      return(1);
+   }
+
+   /* initialize the IP mib */
+   MEMSET(&ip_mib, 0, sizeof(ip_mib));
+   ip_mib.ipForwarding = 2;   /* default to host, not gateway (router) */
+   ip_mib.ipDefaultTTL = IP_TTL;
+
+#ifdef IP_ROUTING
+   /* alloc space for the route table */
+   rt_mib = (struct RtMib*)RT_ALLOC(ipRoutes * sizeof(struct RtMib));
+   if (!rt_mib)
+   {
+#ifdef NPDEBUG
+      dprintf("IP_INIT ERROR: can't alloc route table\n");
+#endif   /* NPDEBUG */
+      return(ENP_NOMEM);
+   }
+
+  MEMSET(rt_mib,0, ipRoutes * sizeof(struct RtMib)) ;
+  ip_mib.ipForwarding = 1;   /* override default, be gateway (router) */
+#endif   /* IP_ROUTING */
+
+   /* set IP reassembly timeout */
+   ip_mib.ipReasmTimeout = IRE_TMO;
+
+#ifdef IPSEC
+   if (IPSecInit())
+   {
+#ifdef NPDEBUG
+      dprintf("IP_INIT: IPSecInit() failed\n");
+#endif   /* NPDEBUG */
+      return(1);
+   }
+#endif   /* IPSEC */
+
+   /* everything opened OK return 0 */
+   return(SUCCESS);
+}
+
+/* FUNCTION: ip_bldhead()
+ *
+ * ip_bldhead() - Prepend an IP header to p->nb_prot
+ *
+ * NOTE: this is no longer used by ip_write(), which inlines it
+ * so it can override the IP time-to-live with the multicast time-to-live
+ * and only calculate the IP header checksum once.  It remains as
+ * a utility function for the convenience of various pseudo-drivers
+ * that generate IP datagrams to exercise the stack.
+ * 
+ * PARAM1: PACKET p
+ * PARAM2: unsigned pid
+ * PARAM3: u_char prot
+ * PARAM4: unshort fragword
+ *
+ * RETURNS: void
+ */
+
+void
+ip_bldhead(PACKET p, unsigned pid, u_char prot, unshort fragword)
+{
+   struct ip * pip;
+   struct ip_socopts *sopts;
+
+   /* prepend IP header to packet data */
+   p->nb_prot -= sizeof(struct ip);       /* this assumes no send options! */
+   p->nb_plen += sizeof(struct ip);
+
+   pip = (struct ip*)p->nb_prot;
+
+   pip->ip_ver_ihl = 0x45;       /* 2 nibbles; VER:4, IHL:5. */
+   pip->ip_flgs_foff = fragword; /* fragment flags and offset */
+   pip->ip_id = htons((unshort)pid);   /* IP datagram ID */
+   pip->ip_len = htons((unshort)p->nb_plen);
+   pip->ip_prot = prot;          /* install protocol ID (TCP, UDP, etc) */
+
+   /* have IP_TOS or IP_TTL been set? */
+   if ((sopts = p->soxopts))
+   {
+	  /* yup */
+	  if (sopts->ip_ttl)
+         pip->ip_time = sopts->ip_ttl;
+	  else
+         pip->ip_time = (u_char)IP_TTL;     /* default number of hops, really */
+      pip->ip_tos = sopts->ip_tos;
+   }
+   else
+   {
+	  /* nope */
+      pip->ip_time = (u_char)IP_TTL;       /* default number of hops, really */
+      pip->ip_tos = IP_TOS_DEFVAL;
+   }
+   
+   pip->ip_chksum = IPXSUM;      /* clear checksum field for summing */
+   pip->ip_chksum = ~cksum(pip, 10);
+}
+
+/* FUNCTION: ip_write_internal()
+ *
+ * ip_write_internal() - common core for ip_write(), ip_raw_write().
+ * Routes and writes supplied packet.
+ *
+ * PARAM1: PACKET p; packet to send
+ *
+ * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if 
+ * waiting for ARP, else negative error code if error detected. 
+ */
+int
+ip_write_internal(PACKET p)
+{
+   ip_addr firsthop;
+#ifdef IP_MULTICAST
+   PACKET pkt2;
+   struct in_multi * inm;
+   unsigned i;
+   struct ip * pip;
+#endif /* IP_MULTICAST */
+   u_char intrsafe_buf;
+   u_long limit;
+   PACKET newpkt;
+   unsigned maxbuflen;
+
+#ifdef IP_MULTICAST
+   /* If destination address is multicast, process multicast options */
+   if (IN_MULTICAST(ntohl(p->fhost)))
+   {
+      if (p->imo != NULL)
+         if (p->imo->imo_multicast_netp)
+            p->net = p->imo->imo_multicast_netp;
+         else
+            p->net = iproute(p->fhost, &firsthop);
+      else
+      {
+         for (i = 0; i < ifNumber; i++)
+            if (nets[i]->n_mcastlist)
+            {
+               p->net = nets[i];
+               break;
+            }
+      }
+
+      /* Confirm that the outgoing interface supports multicast. */
+      if ((p->net == NULL) || (p->net->n_mcastlist) == NULL)
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (IPTRACE|PROTERR))
+         {
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+            dtrap();
+         }
+#endif
+         ip_mib.ipOutNoRoutes++;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NO_ROUTE);
+      }
+
+      /*
+       * If we belong to the destination multicast group
+       * on the outgoing interface, and the caller did not
+       * forbid loopback, put a copy of the packet on the
+       * received queue.
+       */
+      inm = lookup_mcast(p->fhost, p->net);
+      if ((inm != NULL) &&
+          ((p->imo == NULL) || p->imo->imo_multicast_loop)) 
+      {
+         p->type = IPTP;
+         pkt2 = ip_copypkt(p);
+         if (pkt2)
+         {
+            LOCK_NET_RESOURCE(RXQ_RESID);
+            putq(&rcvdq, (q_elt)pkt2);
+            UNLOCK_NET_RESOURCE(RXQ_RESID);
+            SignalPktDemux();
+         }
+      }
+
+      /*
+       * Multicasts with a time-to-live of zero may be looped-
+       * back, above, but must not be transmitted on a network.
+       * Also, multicasts addressed to the loopback interface
+       * are not sent -- a copy will already have been looped
+       * back above if this host actually belongs to the
+       * destination group on the loopback interface.
+       */
+      pip = (struct ip *)(p->nb_prot);
+      if ((pip->ip_time == 0) || 
+          ((p->fhost & htonl(0xFF000000)) == IPLBA) || 
+          (p->fhost == p->net->n_ipaddr))
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return(SUCCESS);
+      }
+
+      firsthop = p->fhost;
+
+      goto sendit;
+   }
+
+#endif /* IP_MULTICAST */
+
+   /* if this is a broadcast packet, use the caller-selected network */
+   if (p->fhost == 0xFFFFFFFF)
+   {
+      firsthop = p->fhost;
+   }
+   else
+   {
+      p->net = iproute(p->fhost, &firsthop);
+      if (p->net == NULL)
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (IPTRACE|PROTERR))
+         {
+            dprintf("ip_write_internal: pkt:%p len%u to %u.%u.%u.%u, can't route\n",
+                    p, p->nb_plen, PUSH_IPADDR(p->fhost));
+            dtrap();
+         }
+#endif   /* NPDEBUG */
+         ip_mib.ipOutNoRoutes++;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NO_ROUTE);
+      }
+   }
+
+#ifdef   IP_MULTICAST
+sendit:  /* label used for multicast packets to skip routing logic */
+#endif   /* IP_MULTICAST */
+
+#ifdef   NPDEBUG
+   if (NDEBUG & IPTRACE)
+   {
+      dprintf("ip_write: pkt[%u] to %u.%u.%u.%u,", 
+       p->nb_plen, PUSH_IPADDR(p->fhost));
+      dprintf(" route %u.%u.%u.%u\n", PUSH_IPADDR(firsthop));
+   }
+#endif
+
+#ifdef   IPSEC
+   IN_PROFILER(PF_IPSEC, PF_ENTRY);
+   ipsec_outbound(&p);
+   IN_PROFILER(PF_IPSEC, PF_EXIT);
+   if (p == NULL)
+   {
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_LOGIC;
+   }
+   if (!(p->fhost))
+   {
+      p->fhost = ((struct ip *)ip_head(p))->ip_dest;
+      if ((p->net = iproute(p->fhost, &firsthop)) == NULL)
+      {
+         ip_mib.ipOutNoRoutes++;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return ENP_NO_ROUTE;
+      }
+   }
+#endif   /* IPSEC */
+
+   /* If the packet is being sent to the same interface it will be sent
+    * from, short-cut things and just put it on the received queue.
+    */
+   if ((p->net->n_ipaddr == p->fhost) &&
+       ((p->fhost & htonl(0xff000000)) != htonl(0x7f000000)))
+   {
+      if (!(p->net->n_flags & NF_NBPROT))
+      {
+         /* We can't do this reliably for interfaces whose drivers
+          * don't set nb_prot to the start of the IP header -- 
+          * if they don't do that, we can't reliably fake a MAC
+          * header for arbitrary drivers here.  So we drop the
+          * packet here.  If you want to be able to do this, 
+          * change your driver(s) to set received packets' nb_prot 
+          * to just past its MAC headers (i.e. to the start of the
+          * IP or ARP protocol header) and nb_type to the protocol
+          * type, and set the NF_NBPROT flag in its interfaces'
+          * n_flags fields.
+          */
+#ifdef NPDEBUG
+         dtrap();
+#endif
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return ENP_LOGIC;
+      }
+      p->type = IPTP;
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      LOCK_NET_RESOURCE(RXQ_RESID);
+      putq(&rcvdq, (q_elt)p);
+      UNLOCK_NET_RESOURCE(RXQ_RESID);
+      LOCK_NET_RESOURCE(NET_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+
+      SignalPktDemux();
+
+      return SUCCESS;
+   }
+
+   /* determine if the buffer that needs to be transmitted is interrupt-safe */
+   intrsafe_buf = ((p->flags & PKF_INTRUNSAFE) ? 0 : 1);
+   /* obtain the length of the largest interrupt-safe buffer that can be 
+    * allocated via pk_alloc () */
+   maxbuflen = pk_get_max_intrsafe_buf_len ();
+   /* compute the maximum amount of data that can be sent in one chunk.  If
+    * the original buffer is interrupt-safe, we just need to consider the
+    * MTU of the egress interface.  If the original buffer is interrupt-
+    * unsafe, we compute the MIN of the largest interrupt-safe buffer that
+    * we can use and the MTU of the egress interface (since we must satisfy
+    * both constraints) */
+   if (!intrsafe_buf)
+       limit = MIN(maxbuflen,p->net->n_mtu);
+   else
+       limit = p->net->n_mtu;
+
+   if ((p->nb_plen + p->net->n_lnh) > limit)
+   {
+#ifdef IP_FRAGMENTS
+      int err;
+      err = ip_fragment(p, firsthop);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(err);
+#else
+      dtrap();    /* this should be caught by programmers during development */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_LOGIC;
+#endif   /* IP_FRAGMENTS */
+   }
+   else
+   {
+      /* fragmentation is not required; check to see if we need to copy out of
+       * an interrupt-unsafe buffer */ 
+      if (!intrsafe_buf)
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         newpkt = pk_alloc(p->nb_plen + p->net->n_lnh);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         if (newpkt == 0)
+         {
+            /* can't allocate interrupt-safe buffer, so free the packet that 
+             * we are working with */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NOBUFFER;
+         }
+         else
+         {
+            /* copy from interrupt-unsafe buffer into interrupt-safe buffer */
+            newpkt->nb_prot = newpkt->nb_buff + p->net->n_lnh;
+            MEMCPY(newpkt->nb_prot, p->nb_prot, p->nb_plen);
+            /* setup various fields in the newly allocated PACKET structure */
+            newpkt->nb_plen = p->nb_plen;
+            newpkt->net = p->net;
+            newpkt->fhost = p->fhost;
+            /* free the original packet since it is no longer needed */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            /* send packet to MAC layer. This will try to resolve MAC layer addressing 
+             * and send packet. ip2mac() can return SUCCESS, PENDING, or error codes. 
+             */
+            return(ip2mac(newpkt, firsthop));
+         }
+      }
+      else
+      {
+         /* since the packet is in an interrupt-safe buffer, it can be passed to 
+          * ip2mac () without any additional work. */
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return(ip2mac(p, firsthop));
+      }
+   }
+}
+
+/* FUNCTION: ip_write()
+ *
+ * ip_write() - Fill in the internet header in the packet p and send 
+ * the packet through the appropriate net interface. This will 
+ * involve using routing. Call with PACKET p->nb_plen & p->nb_prot 
+ * fields set to start of upper layer (e.g. UDP), and p->fhost set to 
+ * target IP address. 
+ * 
+ * PARAM1: u_char prot
+ * PARAM2: PACKET p
+ *
+ * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if 
+ * waiting for ARP, else negative error code if error detected. 
+ */
+
+int
+ip_write(
+   u_char   prot,
+   PACKET   p)
+{
+   struct ip * pip;
+   u_char ttl;
+   struct ip_socopts *sopts;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+
+   /* make room for IP header, and form a pointer to it (pip) */
+   p->nb_prot -= sizeof(struct ip);
+   p->nb_plen += sizeof(struct ip);
+   pip = (struct ip*)(p->nb_prot);
+
+   /* build the initial IP header:
+    * IP source address (ip_src) and IP destination address (ip_dest)
+    * should already have been filled in by upper-layer protocol
+    */
+   pip->ip_ver_ihl = 0x45;       /* 2 nibbles; VER:4, IHL:5. */
+   pip->ip_flgs_foff = 0;        /* clear fragmentation info field */
+   pip->ip_id = htons((unshort)uid);
+   uid++;
+   pip->ip_len = htons((unshort)(p->nb_plen));
+   pip->ip_prot = prot;
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+   ttl = IP_TTL;
+#ifdef IP_MULTICAST
+   if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL))
+      ttl = p->imo->imo_multicast_ttl;
+#endif /* IP_MULTICAST */
+
+   /* have IP_TOS or IP_TTL been set? */
+   if ((sopts = p->soxopts))
+   {
+	  /* yup */
+	  if (sopts->ip_ttl)
+         pip->ip_time = sopts->ip_ttl;
+	  else
+         pip->ip_time = ttl;
+      pip->ip_tos = sopts->ip_tos;
+   }
+   else
+   {
+	  /* nope */
+      pip->ip_time = ttl;
+      pip->ip_tos = IP_TOS_DEFVAL;
+   }
+   
+   /* checksum the IP header */
+   pip->ip_chksum = ~cksum(pip, 10);
+
+   /* do the actual write */
+   return (ip_write_internal(p));
+}
+
+
+/* FUNCTION: ip_write2 ()
+ *
+ * This function is used to fill in the IP header of an
+ * outgoing packet.  The first two parameters for this
+ * function are identical to ip_write (), and the
+ * third parameter is intended to allow the caller to
+ * specify a list of IP options to be inserted into the
+ * outgoing packet.  The caller is expected to provide
+ * a buffer that is large enough for the outgoing
+ * packet (including the IP options).  The third
+ * parameter is expected to be a pointer to a list of
+ * option types (each one byte long) to be inserted into 
+ * the packet, and is terminated by the EOL (0x00) option.
+ *
+ * INPUT: (1) Protocol value to be inserted into the
+ *            IP header field.
+ *        (2) Packet to be transmitted.
+ *        (3) Pointer to a list of option types (each one 
+ *            byte long) to be inserted into the packet, 
+ *            and is terminated by the EOL (0x00) option.
+ *
+ * OUTPUT: This function returns the return code from 
+ *         ip_write_internal ().
+ */
+
+int ip_write2 (u_char prot, PACKET p, u_char * optp)
+{
+   struct ip * pip;
+   u_char ttl;
+   struct ip_socopts * sopts;
+   u_char iphlen = sizeof (struct ip);
+   u_char * tmpp;
+   u_char iphlen_pad;
+   u_char i;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+
+   /* compute the total length of the options requested */
+   for (tmpp = optp; (*tmpp) != EOL_OPT; ++tmpp)
+   {
+      /* account for options, if any (caller has already created
+       * adequate space for the requested option) */
+      switch (*tmpp)
+      {
+         case IP_RTR_ALERT_OPT:
+            iphlen += IP_RTR_ALERT_OPT_SIZE;
+            break;
+         default:
+            break;
+      }
+   }
+
+   /* compute the amount of padding required, if any (to ensure
+    * that the IP header (including options) ends on a dword
+    * (four byte) boundary */
+   if (iphlen & 0x3)
+      iphlen_pad = 4 - (iphlen & 0x3);
+   else iphlen_pad = 0; /* no header padding required */
+
+   /* the packet passed to ip_write2 () has its nb_prot set to
+    * point to start of the protocol's (e.g., IGMP) data, and 
+    * nb_plen set to the length of that data.  locate start of 
+    * the IP header (account for IP options), and form a pointer 
+    * to it (pip) */
+   p->nb_prot -= (iphlen + iphlen_pad);
+   /* add padding length to the total length of the IP datagram */
+   p->nb_plen += (iphlen + iphlen_pad);
+   pip = (struct ip *) (p->nb_prot);
+
+   /* build the initial IP header:
+    * IP source address (ip_src) and IP destination address (ip_dest)
+    * should already have been filled in by upper-layer protocol
+    */
+   pip->ip_ver_ihl = ((IP_VER << 4) | ((iphlen + iphlen_pad) >> 2));
+   pip->ip_flgs_foff = 0; /* clear fragmentation info field */
+   pip->ip_id = htons((unshort)uid);
+   uid++;
+   pip->ip_len = htons((unshort)(p->nb_plen));
+   pip->ip_prot = prot;
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+   ttl = IP_TTL;
+#ifdef IP_MULTICAST
+   if ((IN_MULTICAST(ntohl(p->fhost))) && (p->imo != NULL))
+      ttl = p->imo->imo_multicast_ttl;
+#endif /* IP_MULTICAST */
+
+   /* have TOS or TTL been set (via socket options)? */
+   if ((sopts = p->soxopts))
+   {
+      if (sopts->ip_ttl)
+         pip->ip_time = sopts->ip_ttl;
+      else
+         pip->ip_time = ttl;
+      pip->ip_tos = sopts->ip_tos;
+   }
+   else
+   {
+      pip->ip_time = ttl;
+      pip->ip_tos = IP_TOS_DEFVAL;
+   }
+
+   /* point to the start of the IP options, and insert the options */
+   for (tmpp = (u_char *)(p->nb_prot + sizeof(struct ip)); *optp != EOL_OPT; ++optp)
+   {
+      /* caller has already provided adequate space for the requested options */
+      switch (*optp)
+      {
+         case IP_RTR_ALERT_OPT:
+            *((u_long *) tmpp) = htonl (IP_RTR_ALERT_OPT_DATA);
+            /* this option is 4 bytes long */
+            tmpp += IP_RTR_ALERT_OPT_SIZE;
+            break;
+         default:
+            break;
+      }
+   }
+
+   /* add one (or more) one-byte long End of Option options (if required) */
+   for (i = 0; i < iphlen_pad; ++i) *(tmpp + i) = 0;
+   
+   /* checksum the IP header */
+   pip->ip_chksum = ~cksum (pip, ((iphlen + iphlen_pad)/2));
+
+   /* do the actual write */
+   return (ip_write_internal (p));
+}
+
+
+#ifdef IP_RAW
+
+/* FUNCTION: ip_raw_write()
+ *
+ * ip_raw_write() - send the packet p through the appropriate net
+ * interface.  This will involve using routing.
+ *
+ * PARAM1: PACKET p; packet to send
+ *
+ * RETURNS: Returns 0 if sent OK, ENP_SEND_PENDING (1) if 
+ * waiting for ARP, else negative error code if error detected. 
+ */
+int
+ip_raw_write(PACKET p)
+{
+   struct ip * pip;
+
+   IN_PROFILER(PF_IP, PF_ENTRY);       /* measure time in IP */
+
+   ip_mib.ipOutRequests++;
+
+   /* form a pointer to IP header (pip) */
+   pip = (struct ip*)(p->nb_prot);
+   
+   /* if there's no IP id, give it one */
+   if (pip->ip_id == 0)
+   {
+      pip->ip_id = htons((unshort)uid);
+      uid++;
+   }
+
+   /* checksum the IP header */
+   pip->ip_chksum = IPXSUM;      /* clear checksum field */
+   pip->ip_chksum = ~cksum(pip, 10);
+
+   /* do the actual write */
+   return (ip_write_internal(p));
+}
+
+#endif /* IP_RAW */
+
+#ifdef IP_FRAGMENTS
+
+/* FUNCTION: ip_fragment_lc()
+ *
+ * Fragment an outgoing IP datagram that is too big for it's intended MAC.
+ * This function is invoked from ip_fragment ().
+ *
+ * If ip_fragment () computes the total number of fragments that will be
+ * created from the original IP datagram to be less than or equal to FRAG_-
+ * SCHEME_SWITCH_THRESHOLD and the original IP datagram is interrupt-safe, 
+ * then it invokes use ip_fragment_lc () for creating the child fragments.  
+ * This decreases the amount of copying that needs to be done in those 
+ * cases (as compared to ip_fragment ()); however, as the size of the
+ * original IP datagram increases, ip_fragment () becomes comparatively 
+ * more efficient.
+ * 
+ * PARAM1: PACKET p
+ * PARAM2: ip_addr firsthop
+ *
+ * RETURNS: (1) ENP_LOGIC, if the MTU is deemed "inadequate"
+ *          (2) ENP_RESOURCE, if the buffer for a generated fragment 
+ *              cannot be allocated
+ *          (3) Return code from the invocation of ip2mac () for any 
+ *              generated fragment, if less than zero
+ *          (4) Return code (greater than or equal to 0) from the 
+ *              invocation of ip2mac () for the last generated fragment
+ */
+
+int
+ip_fragment_lc(PACKET p, ip_addr firsthop)
+{
+   unsigned fragsize;   /* size for each fragment to send */
+   unsigned maxipsize;  /* Max size of IP data on this media */
+   unsigned numfrags;   /* number of fragmentswe will send */
+   unsigned foffset;    /* offset of current fragment, in bytes */
+   unshort  fraginfo;   /* IP header flags/fragment field */
+   int      left;       /* bytes left to send */
+   PACKET   pkt2;         /* packet for next fragment */
+   int      e;
+   struct ip * pip;
+   int      iphlen;     /* IP header length */
+   unshort  tmp_fraginfo   ;
+
+   ip_mib.ipFragOKs++;     /* count packets we fragmented */
+   pip = (struct ip *)(p->nb_prot);          /* get ptr to IP header */
+   iphlen = (pip->ip_ver_ihl & 0xf) << 2;    /* and its length */
+   left = (int)p->nb_plen - iphlen; /* bytes left to send in datagram */
+
+   /* Calculate a good size for fragments. 
+    * First, get biggest size an IP datagram can be, 
+    * then divide our outbound packet's length by that to get 
+    * the number of fragments, 
+    * then divide our outbound packet's length by the number 
+    * of fragments to get a fragment length that will result
+    * in similarly-sized segments (remembering to round this
+    * length up to a multiple of 8 because that's how the IP 
+    * Fragment Offset field is scaled).
+    */
+   maxipsize = p->net->n_mtu - (iphlen + p->net->n_lnh + 8);   /* 8 == for rounding up */
+   if (maxipsize < 64)  /* to small to use */
+   {
+      dtrap();    /* probably bad programming */
+      return ENP_LOGIC;
+   }
+   numfrags = (p->nb_plen/maxipsize) + 1;    /* number of fragments */
+   fragsize = (((p->nb_plen + (numfrags - 1)) / numfrags) + 7) & ~7; 
+   foffset = 0;
+
+   /* Now update from any previous info */
+   tmp_fraginfo = ntohs(pip->ip_flgs_foff);     /* get current frag info*/
+   if ( tmp_fraginfo & (~IP_FLG_MASK) )
+   {
+      /* When fragmenting an already fragmented packet, we need to
+         add the initial offset */
+      foffset = (tmp_fraginfo & (~IP_FLG_MASK))  ;
+      foffset <<= 3;    /* Multiply by 8 to get "offset in num of bytes" */
+   }
+
+   /* Loop through IP data area, sending it as fragments */
+   pkt2 = p;  /* init these to avoid compiler warnings */
+   e = 0;
+   while (left > 1)  /* more data left to send? */
+   {
+      p = pkt2;  /* move next fragment up */
+      pip = (struct ip *)(p->nb_prot);
+      p->nb_plen = min((int)fragsize, left) + iphlen; /* set size of fragment */
+      left -= fragsize; /* decrement count of bytes left to send */
+
+      /* set the IP datagram length */
+      pip->ip_len = htons((unshort)p->nb_plen);
+
+      /* build 16bit IP header field value for fragment flags & offset */
+      fraginfo = (unshort)(foffset >> 3);    /* offset, in 8 byte chunks */
+      fraginfo |= ((left>1)?IP_FLG_MF:0);    /* OR in MoreFrags flag */
+
+      if ( tmp_fraginfo & IP_FLG_MF )             
+      {
+         /* As flag is set in main packet, it should be set in all
+          * fragmented packets also 
+          */
+         fraginfo |= IP_FLG_MF;
+      }
+
+      pip->ip_flgs_foff = htons(fraginfo);   /* do htons macro on separate line */
+      /* set up & save next fragment (pkt2) since ip2mac() will delete p */
+      if (left > 1)
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pkt2 = pk_alloc(left + iphlen + MaxLnh);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         if (!pkt2)
+         {
+            dtrap();
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            ip_mib.ipFragFails++;
+            return ENP_RESOURCE;
+         }
+
+         pkt2->net = p->net;       /* copy critical parms to new packet */
+         pkt2->fhost = p->fhost;
+         /* Duplicate the IPHeader */
+         MEMCPY(pkt2->nb_prot, p->nb_prot, iphlen);
+         /* copy data for NEXT fragment from p to pkt2 */
+         MEMCPY(pkt2->nb_prot + iphlen, p->nb_prot + iphlen + fragsize, left);
+      }
+
+      /* we've changed the IP header, so recalculate the checksum */
+      pip->ip_chksum = IPXSUM;
+      pip->ip_chksum = ~cksum(pip, 10);
+
+      /* ip_dump(p); */
+
+      e = ip2mac(p, firsthop);   /* send fragment in p */
+      ip_mib.ipFragCreates++;
+      if (e < 0)
+      {
+         if (left > 1) 
+         {
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt2);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         }
+         return e;
+      }
+      foffset += fragsize;    /* offset for next fragment */
+   }
+   return e;
+}
+
+/* FUNCTION: ip_fragment ()
+ *
+ * This function fragments an IP datagram.  It can be invoked if either
+ * of the following two conditions are met:
+ *
+ * (a) if the outgoing IP datagram is larger than the MTU of the egress 
+ *     interface
+ *
+ * (b) if the outgoing IP datagram resides in a interrupt-unsafe buffer,
+ *     and is larger than the minimum of the largest interrupt-safe 
+ *     buffer and the MTU of the egress interface.
+ *
+ * In the latter case, the original datagram must be copied out into 
+ * multiple interrupt-safe buffers (which are then provided to ip2mac 
+ * () for transmission).
+ *
+ * If ip_fragment () computes the total number of fragments that will be
+ * created from the original IP datagram to be less than or equal to FRAG_-
+ * SCHEME_SWITCH_THRESHOLD and the original IP datagram is interrupt-safe, 
+ * then it invokes ip_fragment_lc () for creating the child fragments.  
+ * This decreases the amount of copying that needs to be done in those 
+ * cases (as compared to ip_fragment ()); however, as the size of the
+ * original IP datagram increases, ip_fragment () becomes comparatively 
+ * more efficient.
+ *
+ * PARAM1: Pointer to packet to be transmitted
+ * PARAM2: IP address of the next hop
+ *
+ * RETURNS: (1) 0, if the outgoing IP datagram has the DF bit set, or
+ *          (2) Return code from ip_fragment_lc () if the conditions for
+ *              the invocation of that function are met, or
+ *          (3) ENP_NOBUFFER, if the buffer for a generated fragment 
+ *              cannot be allocated
+ *          (4) Return code from the invocation of ip2mac () for a 
+ *              generated fragment, if less than zero
+ *          (5) 0, if everything went okay
+ */
+
+int ip_fragment(PACKET p, ip_addr firsthop)
+{
+   unsigned maxbuflen;
+   struct ip * pip;
+   u_char iphlen;
+   u_char l2hdr_len;
+   u_short useable_payload_len;
+   u_short total_payload_len;
+   u_short last_payload_len;
+   u_short maxl3_len;
+   u_short num_frags;
+   u_short i;
+   u_short amt_to_copy;
+   u_short parent_frag_offset;
+   u_short parent_mf;
+   PACKET newpkt;
+   struct ip * newpip;
+   int e;
+
+   pip = ip_head(p);
+   if ((ntohs(pip->ip_flgs_foff)) & IP_FLG_DF)
+   {
+      /* can't fragment a packet with the DF bit set */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      ip_mib.ipFragFails++;
+#ifdef FULL_ICMP
+      icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTFRAG, p->net);
+#endif   /* FULL_ICMP */
+      return 0;
+   }
+
+   maxbuflen = pk_get_max_intrsafe_buf_len ();
+
+   /* the maximum amount of data that will be sent to ip2mac ().  Please note that
+    * our definition of MTU is different from the traditional definition of that
+    * parameter (which excludes the data link layer header). */
+   maxl3_len = (unsigned short int) (MIN(maxbuflen, ((unsigned) p->net->n_mtu)));
+
+   /* get the length of the IP header of the original, unfragmented datagram */
+   iphlen = ip_hlen(pip);
+
+   /* obtain the useable payload length in an IP datagram (after accounting for the 
+    * length of the IP and data link layer headers) */
+   l2hdr_len = (u_char) p->net->n_lnh;
+   useable_payload_len = maxl3_len - iphlen - l2hdr_len;
+
+   /* IP fragments must always have a length that is a multiple of 8 bytes, so we
+    * need to round 'payload_len' down to the nearest multiple of 8 bytes. */
+   useable_payload_len &= (~((unsigned short int) 0x07));
+
+   /* compute the number of packets that we need to send.  First compute the total
+    * payload length of the "original" datagram (which could itself be a fragment). 
+    */
+   total_payload_len = (ntohs(pip->ip_len)) - iphlen;
+   num_frags = (total_payload_len / useable_payload_len);
+   if ((last_payload_len = (total_payload_len % useable_payload_len)) != 0)
+   {
+      /* we will have one additional (also last) fragment that is smaller than the 
+       * other fragments */
+      ++num_frags;
+   }
+
+   /* if we have a small number of fragments and the "original" IP datagram (i.e.,
+    * the one passed to this function) is interrupt-safe, then we use 
+    * ip_fragment_lc () for creating the child fragments.  This decreases the 
+    * amount of copying that needs to be done in those cases (as compared to this 
+    * function); however, for larger packets, ip_fragment () becomes more efficient 
+    * (than ip_fragment_lc ()). */
+   if ((num_frags <= FRAG_SCHEME_SWITCH_THRESHOLD) && (!(p->flags & PKF_INTRUNSAFE)))
+   {
+      return (ip_fragment_lc (p, firsthop));
+   }
+
+   parent_frag_offset = (((ntohs(pip->ip_flgs_foff)) & IP_EXTRACT_FOFF) << 3);
+   parent_mf = ((ntohs(pip->ip_flgs_foff)) & IP_FLG_MF);
+
+   /* irrespective of whether the parent buffer is interrupt-safe or not, we attempt 
+    * to allocate new buffers for all of the fragments.  Iterate thru' the original 
+    * datagram, copying fragments into the newly allocated data buffers.  If we want
+    * to send the fragments in reverse order, we just need to "reverse" the FOR loop.
+    */
+   for (i = 0; i < num_frags; ++i)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      newpkt = pk_alloc (useable_payload_len + iphlen + l2hdr_len); 
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+      if (newpkt == 0)
+      {
+         /* free the packet that we are working with */
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         ip_mib.ipFragFails++;
+         return ENP_NOBUFFER;
+      }
+      else
+      {
+         /* copy the IP header from the original datagram into the fragment */
+         MEMCPY((newpkt->nb_buff + l2hdr_len), p->nb_prot, iphlen);
+
+         /* compute the amount of payload that needs to be copied into each 
+          * child fragment */
+         if (i < (num_frags - 1))
+         {
+            amt_to_copy = useable_payload_len;
+         }
+         else
+         {
+            amt_to_copy = ((last_payload_len == 0) ? useable_payload_len : last_payload_len);
+         }
+         MEMCPY((newpkt->nb_buff + l2hdr_len + iphlen), p->nb_prot + iphlen + (useable_payload_len * i), amt_to_copy);
+
+         /* set up the various netbuf fields for the fragment */
+         newpkt->nb_prot = newpkt->nb_buff + l2hdr_len;
+         newpkt->nb_plen = iphlen + amt_to_copy;
+         newpkt->net = p->net;
+         newpkt->fhost = p->fhost;
+         /* type and nb_tstamp fields are not used in the egress direction, but we set 'type' anyway */
+         newpkt->type = htons(IPTP);
+
+         /* now set the Total Length, Fragment Offset, and More Fragments fields */
+         newpip = ip_head(newpkt);
+         newpip->ip_len = htons(newpkt->nb_plen);
+         /* the following statement will reset DF and MF bits */
+         newpip->ip_flgs_foff = htons((parent_frag_offset + (useable_payload_len * i)) >> 3);
+
+         /* set More Fragments flag appropriately as shown below.
+          * (1) Parent fragment offset = 0, MF = 0: original unfragmented datagram (all 
+          *     child fragments but the last will have the MF bit set)
+          * (2) Parent fragment offset = x, MF = 1: first or middle fragment (FF or MF)
+          *     (all child fragments will have the MF bit set)
+          * (3) Parent fragment offset > 0, MF = 0: last fragment (LF) (all child fragments
+          *     except the last will have the MF bit set) */
+         if (i < (num_frags - 1))
+         {
+            newpip->ip_flgs_foff |= htons(IP_FLG_MF);
+         }
+         else
+         {
+            if (parent_mf)
+            {
+               newpip->ip_flgs_foff |= htons(IP_FLG_MF);
+            }
+         }
+
+         /* finally, update the checksum */
+         newpip->ip_chksum = IPXSUM;
+         newpip->ip_chksum = ~cksum(newpip, (iphlen/2));
+
+         ip_mib.ipFragCreates++;
+
+         /* we're done; hand the packet off to ip2mac () */
+         e = ip2mac (newpkt, firsthop);
+         if (e < 0)
+         {
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            ip_mib.ipFragFails++;
+            return e;
+         }
+      } /* end if (successfully allocated PACKET for child fragment) */
+
+   } /* end FOR (all child fragments) */
+
+   /* free the parent buffer since all of the data from it have been copied 
+    * out into the child fragments */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   ip_mib.ipFragOKs++;     /* count packets we fragmented */
+
+   return 0;
+}
+
+#endif   /* IP_FRAGMENTS */
+
+
+/* FUNCTION: ip_mymach()
+ *
+ * Return the address of our machine relative to a certain foreign host. 
+ *
+ * 
+ * PARAM1: ip_addr host
+ *
+ * RETURNS: The address of our machine relative to a 
+ * certain foreign host. 
+ */
+
+ip_addr
+ip_mymach(ip_addr host)
+{
+#ifdef MULTI_HOMED
+   ip_addr temp;
+   NET tnet;
+#endif
+
+#ifdef   IP_LOOPBACK
+   /* if we're sending to a loopback address, give a loopback address */
+   if ((host & htonl(0xFF000000)) == IPLBA)
+      return host;
+#endif   /* IP_LOOPBACK */
+
+#ifndef MULTI_HOMED /* single static interface */
+   USE_ARG(host);
+   return(nets[0]->n_ipaddr);   /* always use address from only net */
+#else   /* MULTI_HOMED */
+   tnet = iproute(host, &temp);
+   if (tnet == 0)
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & (PROTERR|INFOMSG))
+         dprintf("IP: Couldn't route to %u.%u.%u.%u\n", PUSH_IPADDR(host));
+#endif   /* NPDEBUG */
+      return 0L;
+   }
+   return tnet->n_ipaddr;
+#endif /* MULTI_HOMED */
+}
+
+
+#ifdef NPDEBUG
+
+/* FUNCTION: ip_dump()
+ *
+ * dumps an IP header to the default output.
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: void
+ */
+
+void
+ip_dump(PACKET p)
+{
+   struct ip * pip;
+   unsigned char * cp;
+   unsigned short xsum, osum;
+
+   pip = ip_head(p);
+   osum = pip->ip_chksum;
+   pip->ip_chksum = 0;
+   xsum = ~cksum(pip, ip_hlen(pip) >> 1);
+
+   if (osum != xsum)          /* trap here if checksum is wrong */
+   {
+      dtrap();
+   }
+
+#ifdef NOTDEF
+   /* dtrap() is fatal in the default Windows implementation, so
+    * we comment it out */
+   dtrap();       /* use debugger to view variables & packet */
+#endif
+
+   ns_printf(NULL ,"IP packet header:\n");
+   cp = (unsigned char *)pip;    /* make char pointer for bitmasks */
+   ns_printf(NULL ,"ver/hlen: %02x, TOS: %02x, len: %04x, id: %04x\n",
+    *cp, *(cp+1), htons(pip->ip_len), htons(pip->ip_id));
+   ns_printf(NULL ,"flags/offs: %04x, TTL %02x, protocol: %02x, cksum: %04x (%s)\n",
+    htons(*(unshort*)(cp+6)), pip->ip_time, pip->ip_prot, 
+    htons(osum), (osum==xsum)?"ok":"bad");
+   ns_printf(NULL ,"src: %u.%u.%u.%u  ", PUSH_IPADDR(pip->ip_src));
+   ns_printf(NULL ,"dest: %u.%u.%u.%u\n", PUSH_IPADDR(pip->ip_dest));
+
+   pip->ip_chksum = osum;     /* fix what we clobbered */
+}
+#endif   /* NPDEBUG */
+
+
+
+/* FUNCTION: iproute()
+ *
+ * iproute() - Route a packet. Takes the internet address that we 
+ * want to send a packet to and returns the net interface to send it 
+ * through. 
+ *
+ * 
+ * PARAM1: ip_addr host
+ * PARAM2: ip_addr * hop1
+ *
+ * RETURNS: Returns NULL when unable to route, else returns a NET pointer.
+ */
+
+NET
+iproute(ip_addr host, ip_addr * hop1)
+{
+   int      i;
+   NET      ifp;
+#ifdef IP_ROUTING
+   RTMIB    rtp;
+#endif   /* IP_ROUTING */
+
+   if (host == 0L)      /* Sanity check parameter. */
+      return NULL;
+
+#ifdef IP_ROUTING
+#ifndef BTREE_ROUTES
+   /* its possible for this function to get called before the whole 
+    * stack has been initialized (tk_yield() gets called out of the 
+    * dialer code as part of PPP initialization), one symptom of 
+    * which is the routing table not being present yet. if this 
+    * happens, quit. 
+    */
+   if (rt_mib == NULL)
+      return NULL;
+#endif   /* BTREE_ROUTING */
+
+   /* see if the host matches the cached route */
+   if (cachedRoute)     /* don't test this if route is null  */
+   {
+      if (cachedRoute->ipRouteDest == host)    /* exact match */
+      {
+         *hop1 = cachedRoute->ipRouteNextHop;   /* fill in nexthop IP addr */
+         cachedRoute->ipRouteAge = cticks;      /* timestamp route entry */
+         return(cachedRoute->ifp); /* net to send on */
+      }
+   }
+
+   rtp = rt_lookup(host);
+   if(rtp)
+   {
+      cachedRoute = rtp;
+      *hop1 = rtp->ipRouteNextHop;  /* fill in IP dest (next hop) */
+      return(rtp->ifp);             /* return pointer to net */
+   }
+#endif   /* IP_ROUTING */
+
+   /* Check if it is on one of my nets 
+    *
+    * A note about style: for single-homed builds, we don't need to
+    * iterate through netlist, just look at the one-and-only net on
+    * the list.  So we always set up for the first net (which is also
+    * the initial state for the for loop that iterates through the
+    * list), but only build the iterator for multi-homed systems
+    * because single-homed systems are often memory-limited systems as
+    * well.  
+    */
+   ifp = (NET)(netlist.q_head);
+   i = 0;
+#ifdef MULTI_HOMED
+   for(; ifp; ifp = ifp->n_next, i++)
+#endif /* MULTI_HOMED */
+   {
+      if((ifp->snmask != 0) &&      /* skip ifaces with no IP or subnet mask set */
+         (ifp->n_ipaddr != 0) && 
+         ((ifp->n_ipaddr & ifp->snmask) == (host & ifp->snmask)))
+      {
+#ifdef IP_ROUTING
+         /* make a cached Route entry for next time */
+         cachedRoute = add_route(host, 0xFFFFFFFF, host, i, IPRP_OTHER);
+#ifdef NPDEBUG
+         if (cachedRoute == NULL)
+            dtrap();
+#endif   /* NPDEBUG */
+#endif   /* IP_ROUTING */
+         *hop1 = host;
+         return ifp;
+      }
+   }
+
+#ifdef IP_LOOPBACK
+   /* If it's a loopback packet (dest 127.x) and we got here, then 
+    * there's no loopback device. Route the packet to nets[0] and let 
+    */
+   if ((host & htonl(0xFF000000)) == IPLBA)
+   {
+      *hop1 = host;
+      return nets[0];
+   }
+#endif   /* IP_LOOPBACK */
+
+   /* The host isn't on a net I'm on, so send it to the default 
+    * gateway on the first net which has one. 
+    */
+   ifp = (NET)(netlist.q_head);
+#ifdef MULTI_HOMED
+   for(; ifp; ifp = ifp->n_next)
+#endif   /* MULTI_HOMED */
+   {
+      /* Check if this net has a gateway */
+      if(ifp->n_defgw)
+      {
+         *hop1 = ifp->n_defgw;
+         return ifp;
+      }
+   }
+
+#ifdef STRICT_SUBNETTING
+   return NULL ;
+#else
+   /* if no gateway is set, then change the first hop address to the 
+    * host we're trying to route to. this is just a kluge to make 
+    * this work with arp routing. otherwise, we would try to return 
+    * some sort of error indication. 
+    */
+   *hop1 = host;
+   return((NET)(netlist.q_head));
+#endif   /* STRICT_SUBNETTING */
+}
+
+
+#ifdef NO_IP_MACROS     /* Replace some macros with functions */
+
+/* FUNCTION: ip_data()
+ *
+ * Return pointer to IP data area which starts after the IP header. This accounts
+ * for any IP options which might be appended to the packet.
+ *
+ * PARAM1: struct ip * pip
+ *
+ * RETURNS: 
+ */
+
+unsigned char *   
+ip_data(struct ip * pip)
+{
+   u_char   ihl;
+
+   ihl = pip->ver_ihl_tos[IP_VER_IHL];    /* extract ip header len */
+   ihl &= 0x0f;   /* mask out version bits, ihl normally == 5 */
+   return((char *)(pip) + (ihl << 2)); /* convert to byte count & pointer */
+}
+
+
+/* FUNCTION: ip_optlen()
+ * 
+ * PARAM1: struct ip * pip
+ *
+ * RETURNS: 
+ */
+
+unsigned
+ip_optlen(struct ip * pip)
+{
+   u_char   ihl;
+
+   ihl = pip->ver_ihl_tos[IP_VER_IHL];    /* extract ip header len */
+   ihl &= 0x0f;   /* mask out version bits, ihl normally == 5 */
+   return((ihl - IP_IHL) << 2);
+}
+
+#endif   /* NO_IP_MACROS */
+
+
+/* FUNCTION: ip_copypkt()
+ * 
+ * Makes a copy of a packet in a new packet buffer.
+ *
+ * PARAM1: PACKET p
+ *
+ * RETURNS: a pointer to the new copy of the packet,
+ *          or NULL if no packet buffer could be allocated
+ */
+PACKET
+ip_copypkt(PACKET p)
+{
+   PACKET np;
+   int len;
+
+   /* figure out how much we need to copy from the packet, 
+    * and allocate a new buffer to hold it 
+    */
+   len = p->nb_plen + (p->nb_prot - p->nb_buff);
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   np = pk_alloc(len);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (np == NULL)
+   {
+#ifdef NPDEBUG
+      dprintf("ip_copypkt(): unable to obtain packet (len %d)\n", len);
+#endif
+      return NULL;
+   }
+
+   /* copy packet data into new buffer */
+   MEMCPY(np->nb_buff, p->nb_buff, len);
+
+   /* copy relevant packet fields */
+   np->nb_prot = np->nb_buff + (p->nb_prot - p->nb_buff);
+   np->nb_plen = p->nb_plen;
+   np->net = p->net;
+   np->fhost = p->fhost;
+   np->type = p->type;
+   np->nb_tstamp = p->nb_tstamp;
+
+   /* return pointer to the copy */
+   return np;
+}
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.c
new file mode 100644
index 0000000..ed92069
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.c
@@ -0,0 +1,1343 @@
+/*
+ * FILENAME: ip_reasm.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * IP reassembly.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: ip_reassm() 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software */
+
+#include "ipport.h"
+
+#ifdef IP_FRAGMENTS  /* whole file can be ifdeffed out */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "ip_reasm.h"
+#include "icmp.h"
+
+/* number of bytes currently used by the reassembly process - this is the sum of
+ * the lengths of the buffers used in the reassembly process */
+u_long ipr_curr_mem = 0;
+
+/* IRE statistics data structure */
+struct ire_stats ire_stats;
+
+/* head pointer to IP reassembly entry (IRE) queue */
+IREP h_ireq = 0;
+/* next invocation of timer tick processing routine */
+u_long ire_cticks = 0;
+
+IREP ip_reasm_match_frag_with_ire (struct ip * pip);
+IP_FRAGTYPE ip_reasm_determine_type_of_frag (struct ip * pip);
+int ip_reasm_check_mem_useage (u_short increment);
+int ip_reasm_incr_mem_useage (u_short increment);
+int ip_reasm_decr_mem_useage (u_short decrement);
+int ip_reasm_process_first_fragment (PACKET p);
+int ip_reassm (PACKET p);
+IPREASM_RC ip_reasm_compute_overlap (PACKET p, IREP irep, u_short * indexp, RFQP * last_rfqpp, u_short * frag_offsetp, u_char * hole_createdp);
+int ip_reasm_process_subsequent_fragments (PACKET p, IREP irep);
+u_char ip_reasm_find_ire (IREP irep);
+u_char ip_reasm_copy_queued_fragments_into_reassy_buffer (PACKET reassy_pkt, IREP irep);
+int ip_reasm_delete_ire (IREP irep);
+int ip_reasm_mark_compact_rfq (IREP irep);
+int ipr_stats(void * pio);
+#ifdef FULL_ICMP
+u_long ip_reasm_send_icmp_timex (IREP irep);
+#endif
+
+/* FUNCTION: ip_reasm_frag_match_frag_with_ire ()
+
+This function attempts to locate a IRE that corresponds to the received
+packet.  This requires a comparison of the source address, destination 
+address, identification, and protocol fields in the packet with their
+counterparts in the IRE entry.  Note that all multi-byte fields (such
+as IP source address, IP destination address, and identication) are 
+stored in network-byte order, so no host-network translations are 
+required prior to the comparison.
+
+INPUT: Pointer to start of IP header of received packet
+
+OUTPUT: Pointer to the IRE entry that has identical values for the source
+address, destination address, identification, and protocol fields in the
+packet being processed.  If no such entry is found, this function returns 
+NULL.
+*/
+
+IREP ip_reasm_match_frag_with_ire (struct ip * pip)
+{
+   ip_addr src;
+   ip_addr dest;
+   u_char prot;
+   u_short id;
+   IREP tmpp;
+ 
+   src = pip->ip_src;
+   dest = pip->ip_dest;
+   prot = pip->ip_prot;
+   id = pip->ip_id;
+
+   /* note that multi-byte fields such as the source address, destination address,
+    * and id fields are stored in the IRE structure in network byte order */
+   for (tmpp = h_ireq; tmpp; tmpp = tmpp->next)
+      {
+      if ((tmpp->src == src) && (tmpp->dest == dest) && 
+          (tmpp->prot == prot) && (tmpp->id == id))
+         {
+         return tmpp; /* we've found a match */
+         }
+      }
+
+   /* no match found */
+   return NULL;
+}
+
+/* FUNCTION: ip_reasm_determine_type_of_frag ()
+
+This function examines various fields in the IP header to determine
+if a packet is a complete packet (IP_CP), first fragment (IP_FF), 
+middle fragment (IP_MF), or last fragment (IP_LF).  It uses information 
+from the fields in the IP header to make that decision.
+
+   More Fragments (MF)     Fragmentation Offset    Classification
+   --------------------------------------------------------------
+   0                       0                       Complete Packet
+   0                       Non-zero                Last Fragment
+   1                       0                       First Fragment
+   1                       Non-zero                Middle Fragment
+
+INPUT: Pointer to start of IP header for packet
+
+OUTPUT: One of the various IP_FRAGTYPE values (IP_CP, IP_FF, IP_MF, 
+or IP_LF)
+*/
+
+IP_FRAGTYPE ip_reasm_determine_type_of_frag (struct ip * pip)
+{
+  u_short mf;
+  u_short foff;
+  IP_FRAGTYPE rc;
+
+  mf = (((ntohs(pip->ip_flgs_foff)) & IP_FLG_MF) >> 13);
+  foff = ((ntohs(pip->ip_flgs_foff)) & IP_EXTRACT_FOFF);
+
+  if (mf == 0)
+     {
+     if (foff == 0) {rc = IP_CP;}
+     else {rc = IP_LF;}
+     }
+  else
+     {
+     if (foff == 0) {rc = IP_FF;}
+     else {rc = IP_MF;}
+     }
+
+  return rc;
+}
+
+/* FUNCTION: ip_reasm_check_mem_useage ()
+
+This function computes the sum of the existing useage (as stored in 
+ipr_curr_mem) and the requested allocation (by a function in the IP 
+reassembly module).  If the sum total of the two items becomes greater 
+than IP_REASM_MAX_MEM, it returns ENP_RESOURCE (signifying that the 
+request would fail).
+
+The reassembly code calls this function to check to see if a memory 
+request would be successful before proceeding with its work (e.g., 
+allocating memory for an IRE and packet (from ip_reasm_process_first_-
+fragment ()), or a RFQ and packet (e.g. from ip_reasm_process_-
+subsequent_fragments ())).  If the check passes, the caller subsequently 
+invokes ip_reasm_incr_mem_useage () to record the increment.
+
+INPUT: Amount of memory increment being requested
+
+OUTPUT: ENP_RESOURCE, if the increment request can't be allowed; 
+otherwise it returns IPREASM_OK.
+*/
+
+int ip_reasm_check_mem_useage (u_short increment)
+{
+   /* sanity check */
+   if (ipr_curr_mem > IP_REASM_MAX_MEM)
+   {
+      /* this should never happen */
+      ++ire_stats.bad_max_mem;
+   }
+
+   /* check to see if we are already at limit OR if we may become over limit 
+    * after accepting this new fragment */
+   if ((ipr_curr_mem == IP_REASM_MAX_MEM) ||
+       (ipr_curr_mem + increment > IP_REASM_MAX_MEM))
+   {
+      /* return an error indication */
+      ++ire_stats.mem_check_fail;
+      return ENP_RESOURCE;
+   }
+
+   /* memory limits will not be exceeded with this increment */
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_incr_mem_useage ()
+
+This function increments the counter that is used to keep track of the amount
+of memory (IRE, RFQ, and packet buffers) that is currently being used by the
+IP reassembly module.
+
+INPUT: Number of bytes "taken" by the caller
+
+OUTPUT: Returns ENP_RESOURCE if the requested allocation will result in the 
+system exceeding the maximum limit or if the system has already exceeded 
+the prespecified limit for memory useage; otherwise, it returns IPREASM_OK.
+*/
+
+int ip_reasm_incr_mem_useage (u_short increment)
+{
+   /* sanity checks */
+   if (ipr_curr_mem > IP_REASM_MAX_MEM)
+   {
+      /* this should never happen */
+      ++ire_stats.bad_max_mem;
+      return ENP_RESOURCE;
+   }
+   if (ipr_curr_mem + increment > IP_REASM_MAX_MEM)
+   {
+      /* this should never happen since caller should have 
+       * checked prior to asking for the increment */
+      ++ire_stats.mem_incr_fail;
+      return ENP_RESOURCE;
+   }
+
+   ipr_curr_mem += increment;
+
+   /* successfully incremented memory useage counter */
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_decr_mem_useage ()
+
+This function decrements the counter that is used to keep track of the amount
+of memory (IRE, RFQ, and packet buffers) that is currently being used by the
+IP reassembly module.
+
+INPUT: Number of bytes "released" by the caller
+
+OUTPUT: Returns ENP_RESOURCE if the amount of memory being released is less 
+than the amount of memory currently outstanding or if the system has already 
+exceeded the prespecified limit for memory useage; otherwise, it returns 
+IPREASM_OK.
+*/
+
+int ip_reasm_decr_mem_useage (u_short decrement)
+{
+   /* sanity checks */
+   if (ipr_curr_mem > IP_REASM_MAX_MEM)
+   {
+      /* this should never happen */
+      ++ire_stats.bad_max_mem;
+      return ENP_RESOURCE;
+   }
+   if (ipr_curr_mem < decrement)
+   {
+      /* this should never happen since the current memory useage
+       * counter must always be greater than or at least equal to
+       * the allocation that is being "returned" */
+      ++ire_stats.mem_decr_fail;
+      return ENP_RESOURCE;
+   }
+
+   ipr_curr_mem -= decrement;
+
+   /* successfully decremented memory useage counter */
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_process_first_fragment ()
+
+This function processes the first fragment received for a fragment stream.
+(The first fragment received may or may not be the fragment with a
+Fragment Offset field of 0 (i.e., First Fragment (FF)) in the IP header.)
+If the memory resource checks pass, the function allocates an IRE entry
+for the new fragment stream.  The IRE entry is initialized, and linked
+into the global IRE queue (pointed to by h_ireq).  The memory useage
+counters are also incremented to include the new IRE entry.
+
+INPUT: Pointer to the received fragment
+
+OUTPUT: ENP_RESOURCE if the memory check (in ip_reasm_check_mem_useage ()) 
+or the allocation for an IRE fails; otherwise, it returns IPREASM_OK.
+*/
+
+int ip_reasm_process_first_fragment (PACKET p)
+{
+   struct ip * pip;
+   IREP irep;
+   IP_FRAGTYPE ftype;
+   u_char iphlen;
+   u_short frag_offset;
+   u_short total_len;
+   int rc;
+
+   /* this is a fragment from a hitherto unknown fragment stream; 
+    * check for resource limits before accepting it */
+   if ((rc = ip_reasm_check_mem_useage (p->nb_blen + (sizeof (IRE)))) != IPREASM_OK)
+   {
+      LOCK_NET_RESOURCE (FREEQ_RESID);
+      pk_free (p);
+      UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      ++ip_mib.ipReasmFails;
+      return rc;
+   }
+
+   /* we are ok wrt memory limits; since this is the first fragment, we need 
+    * to create an IRE entry */
+   irep = (IREP) IPR_ALLOC(sizeof(IRE));
+   if (irep == 0) 
+   {
+      LOCK_NET_RESOURCE (FREEQ_RESID);
+      pk_free (p);
+      UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      ++ip_mib.ipReasmFails;
+      return ENP_RESOURCE;
+   }
+
+   pip = ip_head(p);
+   iphlen = ip_hlen(pip);
+   ftype = ip_reasm_determine_type_of_frag (pip);
+   frag_offset = (((ntohs(pip->ip_flgs_foff)) & IP_EXTRACT_FOFF) << 3);
+   total_len = ntohs(pip->ip_len);
+
+   /* now setup various fields in the IRE entry (multi-byte fields stored in network 
+    * byte order) */
+   irep->src = pip->ip_src;
+   irep->dest = pip->ip_dest;
+   irep->prot = pip->ip_prot;
+   irep->id = pip->ip_id;
+   if (ftype == IP_LF)
+      {
+      irep->length = frag_offset + (total_len - iphlen);
+      }
+   else if (ftype == IP_FF)
+      {
+      /* these two fields are used during the reassembly process to copy the L2 and L3 
+       * headers into the reassembled packet.  They are also used when a reassembly times 
+       * out, and results in the transmission of an ICMP Time Exceeded message (with the
+       * code set to "fragment reassembly time exceeded").  Please note that the 'l2_hdr' 
+       * as set below may not be the start address for the L2 header (but it is adequate 
+       * for our use).  If the FF is never received, these fields stay at their initial
+       * value of 0. */
+      irep->l2_hdr = p->nb_buff;
+      irep->l3_hdr = (char *) pip;
+      }
+
+   /* note that the 'rcvd' and 'length' counters only keep track of the data part of 
+    * the IP datagram */
+   irep->rcvd = total_len - iphlen;
+   irep->age = 0;
+
+   /* all RFQs are compact when created */
+   irep->flags |= IPR_RFQ_COMPACT;
+
+   /* store PACKET pointer in the first location of the first RFQ */
+   irep->rfq.bufp[0] = p;
+   irep->rfq.frag_offset[0] = frag_offset;
+   /* the next pointer in the RFQ is already 0 */
+
+   p->nb_prot += iphlen;
+   p->nb_plen -= iphlen;
+
+   /* insert at start of global IRE list */
+   irep->next = h_ireq;
+   h_ireq = irep;
+
+   /* increment the memory useage */
+   ip_reasm_incr_mem_useage (p->nb_blen + (sizeof (IRE)));
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reassm ()
+
+This is the main entry point into the IP reassembly module, and is called
+when the stack has received a fragment that is destined for itself.  It
+first checks to see if the received fragment matches an existing IRE; if
+it doesn't, it invokes ip_reasm_process_first_fragment () which attempts
+to allocate and initialize a new IRE structure (to store this and 
+subsequently received fragments).  If a matching IRE already exists, this 
+function calls ip_reasm_process_subsequent_fragments () to process the 
+just received fragment.
+
+INPUT: Pointer to the received fragment
+
+OUTPUT: If either of the fragment processing functions fails, this function
+merely passes their return code back to its caller.  Otherwise, it returns
+IPREASM_OK indicating that the fragment was successfully processed.
+*/
+
+int ip_reassm (PACKET p)
+{
+   IREP irep;
+   struct ip * pip;
+   int rc1, rc2;
+
+   pip = ip_head(p);
+
+   /* we have just received a fragment, so let's start processing it.  First
+    * check for a matching IRE entry. */
+   irep = ip_reasm_match_frag_with_ire (pip);
+
+   if (!irep)
+   {
+      /* this is the first packet for a "new" fragment stream */
+      if ((rc1 = ip_reasm_process_first_fragment (p)) != IPREASM_OK)
+      {
+         /* ip_reasm_process_first_fragment () will free the packet */
+         return rc1;
+      }
+   }
+   else
+   {
+      /* a matching IRE already exists for this fragment */
+      if ((rc2 = ip_reasm_process_subsequent_fragments (p, irep)) != IPREASM_OK)
+      {
+         /* ip_reasm_process_subsequent_fragments () has already deleted the IRE entry */
+         return rc2;
+      }
+   }
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_compute_ovelap ()
+
+This function is invoked for all fragments received after the first fragment 
+(i.e., from ip_reasm_process_subsequent_fragments ()).  It "compares" the
+just received fragment with each of the fragments currently queued in that
+IRE to determine if there is any overlap in the payload portion.  Please note
+that fragments stored in an IRE only contain "unique" data (i.e., there is 
+no duplication).  Overlaps are handled by either dropping the just received
+or queued fragment (the one that is currently being compared with the just
+received fragment), or by modifying the start pointer and/or length of the 
+just received fragment.
+
+There are a total of 11 cases that arise when processing overlapping 
+fragments.  (The cases are numbered as A1, A2, ..., F2.  The table below 
+uses the following abbreviations.
+
+C   = fragment currently being examined (while traversing IRE queue)
+CS  = currstart (start offset of fragment currently being examined
+CE  = currend (end offset of fragment currently being examined
+JR  = just received fragment
+JRS = jrstart (start offset of just received fragment)
+JRE = jrend (end offset of just received fragment)
+
+A1: CS < JRS CE < JRE CE <  JRS C is to the left of JR with zero overlap.
+A2: CS < JRS CE < JRE CE >= JRS JR partially overlaps C on the latter's right.
+B1: CS > JRS CE > JRE CS >  JRE C is to the right of JR with zero overlap.
+B2: CS > JRS CE > JRE CS <= JRE JR partially overlaps C on the latter's left.
+C : CS = JRS CE = JRE           Both (i.e., C and JR) are identical.
+D1: CS = JRS CE > JRE           C is a superset of JR.
+D2: CS = JRS CE < JRE           C is a subset of JR.
+E1: CS < JRS CE = JRE           C is a superset of JR.
+E2: CS < JRS CE > JRE           C is a superset of JR.
+F1: CS > JRS CE = JRE           C is a subset of JR.
+F2: CS > JRS CE < JRE           C is a subset of JR.
+
+INPUTS: (1) Pointer to the received fragment
+        (2) Pointer to the IRE entry that corresponds to the just received 
+            fragment
+        (3) Pointer to store index into bufp (in RFQ)
+        (4) Pointer to store pointer to RFQ.
+            Parameters (3) and (4) are used together in the following manner.
+            (a) *indexp = INVALID_FRAG_INDEX, *last_rfqpp = non-zero: no empty 
+                slot found in RFQ(s) traversed, and *last_rfqpp points to the last 
+                RFQ that was processed.  This will result in a new RFQ being
+                allocated (and linked into *last_rfqpp), and the just received 
+                fragment will be stored in the first slot of the newly allocated
+                RFQ.
+            (b) *indexp != INVALID_FRAG_INDEX, *last_rfqpp = non-zero: empty 
+                slot found in RFQ(s) traversed.  This slot will be used to
+                store the just received fragment.
+        (5) Pointer to storage for the start offset of the just received
+            fragment (the start offset may be modified if an overlap is
+            detected)
+        (6) Pointer to storage for boolean variable that indicates if a
+            hole was created during the processing of the just received
+            fragment.  (A hole is created in a RFQ if the fragment 
+            currently being examined ('C') is dropped.)
+
+OUTPUT: (1) IPREASM_DROP_FRAG_BAD_PARAM, if the IRE pointer can't be validated, or
+        (2) IPREASM_DROP_FRAG_DUPLICATE, if the just received fragment is dropped
+            (because it doesn't contain any unique data), or
+        (3) IPREASM_ACCEPT_FRAG, if the just received fragment is "acceptable"
+            (i.e., contains "unique" data).
+*/
+
+IPREASM_RC ip_reasm_compute_overlap (PACKET p, IREP irep, u_short * indexp, 
+ RFQP * last_rfqpp, u_short * frag_offsetp, u_char * hole_createdp)
+{
+   RFQP rfqp;
+   PACKET currpkt;
+   struct ip * jrip;
+   u_short jrstart;
+   u_short jrend;
+   u_short currstart;
+   u_short currend;
+   u_short drop_len;
+   u_char iphlen;
+   u_short i;
+
+   if (ip_reasm_find_ire (irep) != IPREASM_TRUE)
+      {
+      ++ire_stats.bad_irep;
+      LOCK_NET_RESOURCE (FREEQ_RESID);
+      pk_free (p);
+      UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      return IPREASM_DROP_FRAG_BAD_PARAM;
+      }
+
+   jrip = ip_head(p);
+   iphlen = ip_hlen (jrip);
+   jrstart = (((ntohs(jrip->ip_flgs_foff)) & IP_EXTRACT_FOFF) << 3);
+   jrend =   jrstart + ((ntohs(jrip->ip_len)) - iphlen) - 1;
+   /* skip past the IP header of the just received fragment as we get ready 
+    * to compare for overlap between the just received fragment and the 
+    * fragments that are currently queued in the IRE entry for this fragment 
+    * chain */
+   p->nb_prot += iphlen;
+   p->nb_plen -= iphlen;
+
+   *frag_offsetp = jrstart;
+   *indexp = INVALID_FRAG_INDEX;
+   *last_rfqpp = 0;
+   *hole_createdp = IPREASM_FALSE;
+
+   rfqp = &(irep->rfq);
+
+   while (rfqp)
+      {
+      for (i = 0; i < IPR_MAX_FRAGS; ++i)
+         {
+         if ((currpkt = rfqp->bufp[i]) != 0)
+            {
+            currstart = rfqp->frag_offset[i];
+            currend = currstart + currpkt->nb_plen - 1;
+
+            if (currstart < jrstart)
+               {
+               if (currend < jrend) /* cases A1 and A2 */
+                  {
+                  if (currend < jrstart) /* A1 */
+                     {
+                     /* current fragment is to the left of the just received 
+                      * fragment, and there is zero overlap.  Move on to the 
+                      * next fragment in the RFQ. */
+                     }
+                  else /* A2 */
+                     {
+                     /* the just received fragment partially overlaps current 
+                      * fragment on the latter's right; increment start 
+                      * pointer and decrement length of just received fragment.
+                      * Move on to the next fragment in the RFQ. */
+                     drop_len = (currend - jrstart) + 1;
+                     p->nb_prot += drop_len;
+                     p->nb_plen -= drop_len;
+                     jrstart += drop_len;
+                     jrend = jrstart + p->nb_plen - 1;
+                     }
+                  }
+               else
+                  {
+                  /* currend is greater than or equal to jrend (cases E1 and E2).
+                   * The current fragment is a superset of the just received 
+                   * fragment.  Drop the just received fragment (and we're done). */
+                  LOCK_NET_RESOURCE (FREEQ_RESID);
+                  pk_free (p);
+                  UNLOCK_NET_RESOURCE (FREEQ_RESID);
+                  return IPREASM_DROP_FRAG_DUPLICATE;
+                  }
+               }
+            else if (currstart > jrstart)
+               {
+               if (currend > jrend) /* cases B1 and B2 */
+                  {
+                  if (currstart > jrend) /* B1 */
+                     {
+                     /* current fragment is to the right of the just received 
+                      * fragment, and there is zero overlap.  Move on to the 
+                      * next fragment in the RFQ. */
+                     }
+                  else /* B2 */
+                     {
+                     /* just received fragment partially overlaps current 
+                      * fragment on the latter's left; decrement length of 
+                      * just received fragment.  Move on to the next fragment 
+                      * in the RFQ. */
+                     p->nb_plen = currstart - jrstart;
+                     /* start offset remains unchanged, but jrend must be updated */
+                     jrend = jrstart + p->nb_plen - 1;
+                     }
+                  }
+               else if (currend == jrend) /* F1 */
+                  {
+                  /* current fragment is a subset of the just received fragment.  
+                   * Decrement the length of the just received fragment.  Move
+                   * on to the next fragment in the RFQ. */
+                  p->nb_plen = currstart - jrstart;
+                  jrend = jrstart + p->nb_plen - 1;
+                  }
+               else
+                  {
+                  /* currend is less than jrend (case F2).  current fragment is 
+                   * a subset of the just received fragment.  Drop current
+                   * fragment.  Move on to the next fragment in the RFQ.  Decrement
+                   * the amount of memory currently in use. */
+                  ip_reasm_decr_mem_useage (currpkt->nb_blen);
+                  irep->rcvd -= currpkt->nb_plen;
+                  LOCK_NET_RESOURCE (FREEQ_RESID);
+                  pk_free (currpkt);
+                  UNLOCK_NET_RESOURCE (FREEQ_RESID);
+                  rfqp->bufp[i] = 0; /* mark slot as unused */
+                  /* save the location of the empty slot */
+                  if ((*indexp) == INVALID_FRAG_INDEX) 
+                     {
+                     *indexp = i;
+                     *last_rfqpp = rfqp;
+                     }
+                  /* we've just created a hole; the array may no longer be "compact" */
+                  *hole_createdp = IPREASM_TRUE;
+                  }
+               }
+            else
+               {
+               /* currstart and jrstart are equal */
+               if (currend == jrend) /* case C */
+                  {
+                  /* the current fragment is identical to the just received 
+                   * fragment.  Drop the just received fragment (and we're done). */
+                  LOCK_NET_RESOURCE (FREEQ_RESID);
+                  pk_free (p);
+                  UNLOCK_NET_RESOURCE (FREEQ_RESID);
+                  return IPREASM_DROP_FRAG_DUPLICATE;
+                  }
+               else if (currend > jrend) /* case D1 */
+                  {
+                  /* current fragment is a superset of just received 
+                   * fragment.  Drop the just received fragment (and we're done). */
+                  LOCK_NET_RESOURCE (FREEQ_RESID);
+                  pk_free (p);
+                  UNLOCK_NET_RESOURCE (FREEQ_RESID);
+                  return IPREASM_DROP_FRAG_DUPLICATE;
+                  }
+               else
+                  {
+                  /* currend is less than jrend (case D2).  current fragment 
+                   * is a subset of the just received fragment.  Increment 
+                   * the start pointer and decrement the length of the just
+                   * received fragment.  Move on to the next fragment in 
+                   * the RFQ. */
+                  drop_len = (currend - jrstart) + 1;
+                  p->nb_prot += drop_len;
+                  p->nb_plen -= drop_len;
+                  jrstart += drop_len;
+                  jrend = jrstart + p->nb_plen - 1;
+                  }
+               }
+            } /* end if (PACKET buffer exists at this slot) */
+         else
+            {
+            if ((*indexp) == INVALID_FRAG_INDEX)
+               {
+               *indexp = i;
+               *last_rfqpp = rfqp;               
+               }
+            if (irep->flags & IPR_RFQ_COMPACT)
+               {
+               break;
+               }
+            }
+         } /* end FOR (0...(IPR_MAX_FRAGS - 1)) */
+
+      /* skip saving RFQ pointer if we've already found an empty slot */
+      if ((*indexp) == INVALID_FRAG_INDEX) 
+         {
+         *last_rfqpp = rfqp;
+         }
+      rfqp = rfqp->next;
+      } /* end while (rfqp) */
+
+   /* if no empty slots were found, (*last_rfqpp) will contain a pointer 
+    * to the last RFQ that we were working with */
+
+   *frag_offsetp = jrstart; /* stored in host byte order */
+
+   return IPREASM_ACCEPT_FRAG;
+}
+
+/* FUNCTION: ip_reasm_process_subsequent_fragments ()
+
+This function processes all fragments received after the first fragment 
+for a fragment stream.  If the memory resource check passes, this
+function first invokes ip_reasm_compute_overlap () to determine if the
+fragment has any unique data.  If it does, the function then queues the
+fragment into an available slot (in a RFQ).  If a slot isn't available,
+a new RFQ is allocated (but only if the memory resource check passes).
+If ip_reasm_compute_overlap () created one or more holes during its
+operation, this function invokes ip_reasm_mark_compact_rfq () to update
+the compact status of the IRE.
+
+After the initial processing listed above is complete, this function
+then checks to see if it has received all of the payload for the IP
+datagram being reassembled.  If it has, it attempts to allocate a
+reassembly buffer, and if successful, copies all of the received data
+(from the various fragments) into the reassembly buffer (via ip_reasm_-
+copy_queued_fragments_into_reassy_buffer ()).  After the copying is
+done, the IRE is no longer required and is deleted.  The reassembled 
+IP datagram is then passed back to the stack for further processing.
+
+INPUTS: (1) Pointer to the received fragment
+        (2) Pointer to IRE entry corresponding to just received fragment
+
+OUTPUT: (1) ENP_PARAM, if the IRE pointer can't be validated
+        (2) ENP_RESOURCE, if the memory check (in ip_reasm_check_mem_useage ()) 
+            or the allocation for a RFQ fails, or
+        (3) ENP_NOBUFFER, if the allocation for a buffer in which the
+            fragments will be reassembled in fails, or
+        (4) IPREASM_OK, if the received fragment completely overlaps already
+            queued fragments (and hence has been dropped), or if the fragment
+            has been processed successfully.
+*/
+
+int ip_reasm_process_subsequent_fragments (PACKET p, IREP irep)
+{
+   PACKET reassy_pkt;
+   struct ip * pip;
+   RFQP new_rfqp = 0;
+   int rc;
+   IP_FRAGTYPE ftype;
+   IPREASM_RC rc2;
+   u_short index;
+   RFQP rfqp;
+   u_short frag_offset;
+   u_char hole_created;
+
+   if (ip_reasm_find_ire (irep) != IPREASM_TRUE)
+      {
+      ++ire_stats.bad_irep;
+      LOCK_NET_RESOURCE (FREEQ_RESID);
+      pk_free (p);
+      UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      ++ip_mib.ipReasmFails;
+      return ENP_PARAM;
+      }
+
+   pip = ip_head(p);
+   ftype = ip_reasm_determine_type_of_frag (pip);
+   /* this fragment is a destined for an already queued fragment stream.
+    * we update the 'length' field for LFs here because ip_reasm_compute_overlap ()
+    * modifies the received fragment's nb_prot pointer (thereby making its IP header 
+    * inaccessible) */
+   if (ftype == IP_LF)
+      {
+      irep->length = (((ntohs(pip->ip_flgs_foff)) & IP_EXTRACT_FOFF) << 3) + ((ntohs(pip->ip_len)) - ip_hlen(pip));
+      }
+   else if (ftype == IP_FF)
+      {
+      irep->l2_hdr = p->nb_buff;
+      irep->l3_hdr = (char *) pip;
+      }
+
+   /* Check for overlap, and determine the increase in memory resource 
+    * requirements from the newly arrived fragment */
+   if ((rc2 = ip_reasm_compute_overlap (p, irep, &index, &rfqp, &frag_offset, &hole_created)) != IPREASM_ACCEPT_FRAG)
+      {
+      switch (rc2)
+         {
+         case IPREASM_DROP_FRAG_DUPLICATE:
+            /* this isn't really an error, since it indicates that the received 
+             * fragment's information is a duplicate of what is present in the 
+             * already queued fragments */
+            return IPREASM_OK;
+         case IPREASM_DROP_FRAG_BAD_PARAM:
+            /* this is a real error */
+            return ENP_PARAM;
+         /*
+          * Altera Niche Stack Nios port modification:
+          * Handle IPREASM_ACCEPT_FRAG case (will never
+          * get here per if() above) to remove build warning.
+          */
+         case IPREASM_ACCEPT_FRAG:
+            while(0);
+         }
+      }
+
+   /* this is a fragment from an existing fragment stream; 
+    * check for resource limits before accepting it.  For now
+    * assume that an extra RFQ is not required. */
+   if ((rc = ip_reasm_check_mem_useage (p->nb_blen)) != IPREASM_OK)
+      {
+      LOCK_NET_RESOURCE (FREEQ_RESID);
+      pk_free (p);
+      UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      ip_reasm_delete_ire (irep);
+      ++ip_mib.ipReasmFails;
+      return rc;
+      }
+
+   /* the two combinations of index and rfqp are as follows:
+    * (1) index = INVALID_FRAG_INDEX, rfqp = non-zero: no empty slot found in RFQ(s),
+    *     and rfqp points to the last RFQ that was processed
+    * (2) index != INVALID_FRAG_INDEX, rfqp = non-zero: empty slot found in RFQ(s) */
+   if (index != INVALID_FRAG_INDEX)
+      {
+      /* we have an empty slot in the PACKET array into which we can place 
+       * the just received fragment */
+      rfqp->bufp[index] = p;
+      rfqp->frag_offset[index] = frag_offset;
+      }
+   else
+      {
+      /* since we need to allocate an extra RFQ, check for memory useage again... */
+      if ((rc = ip_reasm_check_mem_useage (p->nb_blen + (sizeof (RFQ)))) != IPREASM_OK)
+         {
+         LOCK_NET_RESOURCE (FREEQ_RESID);
+         pk_free (p);
+         UNLOCK_NET_RESOURCE (FREEQ_RESID);
+         ip_reasm_delete_ire (irep);
+         ++ip_mib.ipReasmFails;
+         return rc;
+         }
+
+      /* no slots are available in the one (or more) existing RFQs; we 
+       * need to create a new RFQ to store the just received fragment */
+      new_rfqp = (RFQP) IPR_ALLOC (sizeof(RFQ));
+      if (new_rfqp == 0)
+         {
+         /* can't store the existing fragment, so we'll drop it */
+         LOCK_NET_RESOURCE (FREEQ_RESID);
+         pk_free (p);
+         UNLOCK_NET_RESOURCE (FREEQ_RESID);
+         ip_reasm_delete_ire (irep);
+         ++ip_mib.ipReasmFails;
+         return ENP_RESOURCE;
+         }
+      else
+         {
+         new_rfqp->bufp[0] = p;
+         new_rfqp->frag_offset[0] = frag_offset;
+         rfqp->next = new_rfqp;
+         /* newly allocated RFQ already has its next pointer set to 0 */
+         }
+      }
+      
+      /* check to see if the RFQ is still compact, but only if hole(s) were created 
+       * in ip_reasm_compute_overlap () */
+      if (hole_created)
+         {
+         if ((rc = ip_reasm_mark_compact_rfq (irep)) != IPREASM_OK)
+            {
+            /* an error return is due to a bad IRE pointer, which ip_reasm_mark_compact_rfq () logs */
+            LOCK_NET_RESOURCE (FREEQ_RESID);
+            pk_free (p);
+            UNLOCK_NET_RESOURCE (FREEQ_RESID);
+            ++ip_mib.ipReasmFails;
+            return rc;
+            }
+         }
+
+   /* compute the total number of bytes queued in this IRE.  Note 
+    * that the RHS has been updated to reflect the amount of "unique"
+    * data in the just received fragment (the IP header has been dropped,
+    * and perhaps additional duplicate data too (if present)) */
+   irep->rcvd += (u_short) (p->nb_plen);
+   ip_reasm_incr_mem_useage (p->nb_blen + ((new_rfqp == 0) ? 0 : (sizeof(RFQ))));
+
+   if (irep->length != 0)
+      {
+      /* we know the total length of the original unfragmented datagram; 
+       * let's check to see if we have all of the bytes... */
+      if (irep->rcvd == irep->length)
+         {
+         /* yes, we do; let's reassemble the entire datagram in one data buffer.
+          * Ensure that we allocate space for the data link header, IP header, 
+          * and the payload of the original, unfragmented datagram.  We pick 
+          * the data link layer and IP headers from the First Fragment (FF), 
+          * but we need to adjust some of the fields in the IP header after 
+          * reassembly is complete. */
+         pip = (struct ip *) irep->l3_hdr;
+         LOCK_NET_RESOURCE (FREEQ_RESID);
+         reassy_pkt = pk_alloc (irep->length + (irep->l3_hdr - irep->l2_hdr) + ip_hlen (pip));
+         UNLOCK_NET_RESOURCE (FREEQ_RESID);
+         if (reassy_pkt == 0)
+            {
+            /* the following call will delete all queued fragments, including
+             * the currently received one */
+            ip_reasm_delete_ire (irep);
+            ++ip_mib.ipReasmFails;
+            return ENP_NOBUFFER;
+            }
+         else
+            {
+            ip_reasm_copy_queued_fragments_into_reassy_buffer (reassy_pkt, irep);
+            /* free the IRE structure (and its constituent elements) */
+            ip_reasm_delete_ire (irep);
+            /* at this point, 'irep' is no longer a valid pointer, and so should 
+             * not be referenced.  We're done, and we now pass the packet for 
+             * demux'ing to the appropriate entity (e.g., UDP, TCP, etc.).  Note
+             * that ip_demux () expects 'nb_prot' to point to the beginning of 
+             * the IP header. */
+            ++ip_mib.ipReasmOKs;
+            ip_demux (reassy_pkt);
+            }
+         }
+      else
+         {
+         /* we haven't received all of the data yet, and so reassembly can't complete */
+         }
+      }
+   else
+      {
+      /* we haven't received the LF (so we don't know the total amount of data in 
+       * the original, unfragmented datagram), and therefore reassembly can't complete yet */
+      }
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_frag_find_ire ()
+
+This function searches thru' the IRE list (pointed to by h_ireq) to see if
+an IRE is on that list.  It is typically used to validate the IRE passed in
+to a function.
+
+INPUT: Pointer to IRE
+
+OUTPUT: This function returns a IPREASM_TRUE if the IRE exists in the master 
+IRE list; otherwise, it returns a IPREASM_FALSE.
+*/
+
+u_char ip_reasm_find_ire (IREP irep)
+{
+   IREP tmpp;
+
+   /* check to see if the IRE exists in the IREQ linked list */
+   for (tmpp = h_ireq; tmpp; tmpp = tmpp->next)
+      {
+      if (tmpp == irep) 
+         {
+         return IPREASM_TRUE;
+         }
+      }
+
+   return IPREASM_FALSE;
+}
+
+/* FUNCTION: ip_reasm_copy_queued_fragments_into_reassy_buffer ()
+
+This function copies all fragments queued in an IRE into a reassembly
+buffer.  After the copying is complete, it sets the various fields in
+the PACKET data structure and the IP header for the reassembled IP
+datagram.
+
+INPUT: (1) Pointer to struct netbuf data structure that will be used
+           to the reassembled IP datagram
+       (2) Pointer to IRE that contains the fragments being reassembled
+
+OUTPUT: This function always returns IPREASM_OK.
+*/
+
+u_char ip_reasm_copy_queued_fragments_into_reassy_buffer (PACKET reassy_pkt, IREP irep)
+{
+   struct ip * pip;
+   u_char offset;
+   RFQP rfqp;
+   u_short i;
+   PACKET p;
+   u_char iphlen;
+   char * writep;
+   PACKET sav_pkt = 0;
+
+   pip = (struct ip *) irep->l3_hdr;
+   iphlen = ip_hlen (pip);
+
+   /* copy the data link and IP layer headers into place.  These headers are 
+    * from the First Fragment (FF). */
+   offset = (u_char) ((irep->l3_hdr - irep->l2_hdr) + iphlen);
+   MEMCPY(reassy_pkt->nb_buff, irep->l2_hdr, offset);
+
+   rfqp = &(irep->rfq);
+   writep = reassy_pkt->nb_buff + offset;
+
+   while (rfqp)
+      {
+      for (i = 0; i < IPR_MAX_FRAGS; ++i)
+         {
+         if ((p = rfqp->bufp [i]) != 0)
+            {
+            /* note that rfqp->frag_offset[i] is the true value of the offset field, 
+             * and does not require any scaling (like the Fragment Offset field in 
+             * the IP header) */
+            MEMCPY((writep + rfqp->frag_offset[i]), p->nb_prot, p->nb_plen);
+            /* free fragment after we've copied data out from it (unless we need to
+             * save it so that we can copy some fields from it later (after exiting 
+             * from the loop)) */
+            if (!sav_pkt) sav_pkt = p;
+            else
+               {
+               ip_reasm_decr_mem_useage (p->nb_blen);
+               LOCK_NET_RESOURCE (FREEQ_RESID);
+               pk_free (p);
+               UNLOCK_NET_RESOURCE (FREEQ_RESID);
+               }
+            /* since we're done with the packet, mark slot as unused */
+            rfqp->bufp [i] = 0;
+            }
+         else
+            {
+            if (irep->flags & IPR_RFQ_COMPACT)
+               {
+               break;
+               }
+            }
+          }
+
+      rfqp = rfqp->next;
+      }
+
+   /* update various fields in the reassembled packet.  Some fields will be 
+    * picked from one of the constituent fragments (sav_pkt) which hasn't
+    * been deleted yet. */
+   reassy_pkt->nb_prot = reassy_pkt->nb_buff + (irep->l3_hdr - irep->l2_hdr);
+   reassy_pkt->nb_plen = irep->length + iphlen;
+   reassy_pkt->nb_tstamp = cticks;
+   reassy_pkt->flags |= ((sav_pkt->flags) & (PKF_BCAST | PKF_MCAST));
+   reassy_pkt->net = sav_pkt->net;
+   reassy_pkt->type = sav_pkt->type;
+   /* fhost is set by ip_demux () before handing off to the packet to its 
+    * intended destination (protocol) */
+
+   /* free the saved packet too, since we don't need it anymore */
+   ip_reasm_decr_mem_useage (sav_pkt->nb_blen);
+   LOCK_NET_RESOURCE (FREEQ_RESID);
+   pk_free (sav_pkt);
+   UNLOCK_NET_RESOURCE (FREEQ_RESID);
+
+   /* after the reassembly is complete, we update the following fields in
+    * the IP header: Total Length, Flags/Fragment Offset, header checksum */
+   pip = ip_head(reassy_pkt);
+   pip->ip_len = htons(reassy_pkt->nb_plen);
+   /* turn off More Fragments (MF) bit; the DF bit stays unchanged */
+   pip->ip_flgs_foff &= htons(~((u_short) IP_FLG_MF));
+   /* clear the Fragment Offset bits */
+   pip->ip_flgs_foff &= htons(~((u_short) IP_EXTRACT_FOFF)); 
+   /* the following isn't really required, and can be removed */
+   pip->ip_chksum = IPXSUM;
+   pip->ip_chksum = ~cksum (pip, (iphlen/2));
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_process_timer_tick ()
+
+This function processes the IRE list once every second.  It is invoked 
+from inet_timer ().  All IREs start off with an age of 0, and are 
+deleted when they reach an age of IRE_TMO.
+
+This function obtains the NET_RESID semaphore before proceeding with 
+its work.  This protects the consistency of shared data structures 
+(such as the IRE, etc.) between the timer and the packet processing 
+receive tasks.
+
+INPUT: None.
+
+OUTPUT: This function always returns IPREASM_OK.
+*/
+
+u_char ip_reasm_process_timer_tick (void)
+{
+   IREP tmpp;
+   IREP nxt_tmpp;
+
+   LOCK_NET_RESOURCE (NET_RESID);
+ 
+   for (tmpp = h_ireq; tmpp; tmpp = nxt_tmpp)
+      {
+      /* save the next pointer for the IRE that may be deleted */
+      nxt_tmpp = tmpp->next;
+      ++tmpp->age;
+      /* check to see if this entry has reached its max age (expired)? */
+      if (tmpp->age == IRE_TMO)
+         {
+         /* it has...and therefore must be deleted. */
+         ++ire_stats.ire_timed_out;
+#ifdef FULL_ICMP
+         /* send ICMP Time Exceeded message with code 1 ("fragment reassembly time exceeded") */
+         ip_reasm_send_icmp_timex (tmpp);
+#endif
+         ip_reasm_delete_ire (tmpp);
+         ++ip_mib.ipReasmFails;
+         }
+      }
+
+   /* set the time for the next invocation of this routine (one second later) */
+   ire_cticks = cticks + TPS;
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_delete_ire ()
+
+This function deletes an IRE.  When deleting an IRE, it also deletes any
+queued PACKETs (and RFQs, if any were allocated).  This code can be invoked
+in various scenarios:
+
+(1) when the IRE times out,
+(2) when all bytes (associated with a fragment stream) have been processed
+    (in ip_reasm_process_subsequent_fragments ()), or
+(4) in the event of an error (e.g., when memory resource consumption limits 
+    would be exceeded if a fragment was "accepted", or if storage cannot be
+    allocated for the reassembled packet).
+
+INPUT: Pointer to IRE
+
+OUTPUT: This function returns a ENP_PARAM if the IRE does not exist in the 
+master IRE list; otherwise, it returns a IPREASM_OK.
+*/
+
+int ip_reasm_delete_ire (IREP irep)
+{
+   RFQP rfqp, first_rfqp, prev_rfqp;
+   u_short i;
+   PACKET p;
+   IREP tmpp;
+   IREP prev_tmpp = 0;
+
+   /* check to see if the IRE exists in the master table; if it does,
+    * remove it and also update the pointers in that list */
+   for (tmpp = h_ireq; tmpp; tmpp = tmpp->next)
+      {
+      if (tmpp == irep) 
+         {
+         /* update the head pointer to the list */
+         if (tmpp == h_ireq) h_ireq = irep->next;
+         else prev_tmpp->next = irep->next;
+         break;
+         }
+      prev_tmpp = tmpp;
+      }
+
+   /* if the IRE entry does not exist in the master table, return an error 
+    * to the caller */
+   if (!tmpp)
+      {
+      ++ire_stats.bad_irep;
+      return ENP_PARAM;
+      }
+
+   /* free any queued packets (there may be none if the IRE is being deleted
+    * because the packet has been successfully reassembled) */
+   rfqp = first_rfqp = &(irep->rfq);
+
+   while (rfqp)
+      {
+      for (i = 0; i < IPR_MAX_FRAGS; ++i)
+         {
+         if ((p = rfqp->bufp [i]) != 0)
+            {
+            ip_reasm_decr_mem_useage (p->nb_blen);
+            LOCK_NET_RESOURCE (FREEQ_RESID);
+            pk_free (p);
+            UNLOCK_NET_RESOURCE (FREEQ_RESID);               
+            }
+         else
+            {
+            if (irep->flags & IPR_RFQ_COMPACT)
+               {
+               break;
+               }
+            }
+          }
+
+       prev_rfqp = rfqp;
+       rfqp = rfqp->next;
+       /* the first RFQ is statically allocated, and cannot be freed */
+       if (prev_rfqp != first_rfqp)
+          {
+          ip_reasm_decr_mem_useage (sizeof(RFQ));
+          IPR_FREE (prev_rfqp);
+          }
+      }
+
+   /* now free the parent entity */
+   ip_reasm_decr_mem_useage (sizeof(IRE));
+   IPR_FREE (irep);
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_mark_compact_rfq ()
+
+This function iterates thru' the RFQs inside an IRE to determine the
+compact/non-compact status of an IRE.
+
+INPUT: Pointer to IRE
+
+OUTPUT: This function returns a ENP_PARAM if the IRE does not exist in 
+the master IRE list; otherwise, it returns a IPREASM_OK.
+*/
+
+int ip_reasm_mark_compact_rfq (IREP irep)
+{
+   RFQP rfqp;
+   u_short i;
+   u_char empty_slot_discovered = IPREASM_FALSE;
+   u_char compact = IPREASM_TRUE;
+
+   if (ip_reasm_find_ire (irep) != IPREASM_TRUE)
+   {
+      ++ire_stats.bad_irep;
+      return ENP_PARAM;
+   }
+
+   rfqp = &(irep->rfq);
+
+   while (rfqp)
+      {
+      for (i = 0; i < IPR_MAX_FRAGS; ++i)
+         {
+         if (rfqp->bufp [i] == 0)
+            {            
+            empty_slot_discovered = IPREASM_TRUE;
+            }
+         else
+            {
+            if (empty_slot_discovered) 
+               {
+               compact = IPREASM_FALSE;
+               break;
+               }
+            }
+          }
+       rfqp = rfqp->next;
+      }
+
+   if (compact) 
+      {
+      irep->flags |= IPR_RFQ_COMPACT;
+      }
+   else 
+      {
+      irep->flags &= ~IPR_RFQ_COMPACT;
+      }
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ipr_stats ()
+
+This function prints information related to the operation of the IP reassembly 
+module.
+
+INPUT: Pointer to I/O device
+
+OUTPUT: This function always returns IPREASM_OK.
+*/
+
+int ipr_stats(void * pio)
+{
+   unsigned long ticks_elapsed = cticks;
+   u_short size_ire = sizeof(IRE);
+   u_short size_rfq = sizeof(RFQ);
+   IREP tmpp;
+   u_short count = 0;
+   RFQP rfqp;
+   u_short frag_count = 0;
+   u_short i;
+
+   ns_printf(pio,"IP reassembly statistics:\n");
+   ns_printf(pio,"Current memory useage %lu, ticks %lu, secs %lu, IRE %u, RFQ %u\n",ipr_curr_mem,ticks_elapsed,(ticks_elapsed/TPS),size_ire,size_rfq);
+   ns_printf(pio,"[ERR] IRE T/O %lu, IRE ptr %lu, max mem %lu, mem chk %lu, mem inc %lu, mem dec %lu\n",\
+    ire_stats.ire_timed_out,ire_stats.bad_irep,ire_stats.bad_max_mem,ire_stats.mem_check_fail,ire_stats.mem_incr_fail,ire_stats.mem_decr_fail);
+
+   ns_printf(pio,"Head of IRE queue %p\n",h_ireq); 
+   for (tmpp = h_ireq; tmpp; tmpp = tmpp->next)
+      {
+      ++count;
+      /* compute the total number of fragments queued awaiting reassembly for this IRE */
+      rfqp = &(tmpp->rfq);
+      while (rfqp)
+         {
+         for (i = 0; i < IPR_MAX_FRAGS; ++i)
+            {
+            if (rfqp->bufp [i] != 0)
+               {
+               ++frag_count;            
+               }
+            else
+               {
+               if (tmpp->flags & IPR_RFQ_COMPACT)
+                  {
+                  break;
+                  }
+               }
+            }
+         rfqp = rfqp->next;
+         } /* end WHILE (fragments queued) */
+      ns_printf(pio,"IRE %p [Frags queued %u] SA 0x%lx DA 0x%lx Prot %u Id %u Len %u Rcvd %u Age %lu L2H %p L3H %p Compact %u]\n",tmpp,frag_count,(ntohl(tmpp->src)),(ntohl(tmpp->dest)),tmpp->prot,(ntohs(tmpp->id)),tmpp->length,tmpp->rcvd,tmpp->age,tmpp->l2_hdr,tmpp->l3_hdr,((tmpp->flags) & IPR_RFQ_COMPACT));
+      } /* end FOR (IRE linked list) */
+
+   ns_printf(pio,"Found a total of %u IRE entries\n",count);
+
+   return IPREASM_OK;
+}
+
+/* FUNCTION: ip_reasm_send_icmp_timex ()
+
+This function sends the ICMP Time Exceeded message (with code 1 
+("fragment reassembly time exceeded") when an IP reassembly times
+out (i.e., was not completed in the stipulated time).  This message 
+can only be sent if we have received the First Fragment (FF) of 
+that fragment stream; if we haven't, this function returns without 
+sending any ICMP message.
+
+INPUT: Pointer to IRE
+
+OUTPUT: This function always returns IPREASM_OK.
+*/
+
+#ifdef FULL_ICMP
+u_long ip_reasm_send_icmp_timex (IREP irep)
+{
+   struct ip * pip;
+
+   /* we can only send an ICMP Time Exceeded message with code 1 ("fragment reassembly 
+    * time exceeded") if we have received the First Fragment (FF) of the original, 
+    * unfragmented datagram.  This is indicated by a non-zero value for the l2_hdr and
+    * l3_hdr fields in the IRE data structure. */
+   if (irep->l2_hdr)
+      {
+      pip = (struct ip *) irep->l3_hdr;
+      icmp_timex (pip, TIMEX_REASSY_FAILED);
+      }
+
+   return IPREASM_OK;
+}
+#endif
+
+#endif   /* IP_FRAGMENTS - whole file can be ifdeffed out */
+
+/* end of file ip_reasm.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.h b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.h
new file mode 100644
index 0000000..e3aa762
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ip_reasm.h
@@ -0,0 +1,130 @@
+/* ip_reasm.h 
+ *
+ * Header file for IP reassembly module (ip_reasm.c).
+ */
+#ifndef _IPREASM_H_
+#define _IPREASM_H_ 1
+
+/* upper limit on the amount of memory that can be consumed by the IP 
+ * reassembly module.  This counts memory consumed by the received
+ * fragments, IRE, and RFQ data structures. */
+#define IP_REASM_MAX_MEM 393216 /* 384K */
+
+/* return codes from functions in the IP reassembly module */
+#define IPREASM_OK 0     /* success */
+#define IPREASM_FAIL 1   /* failure */
+#define IPREASM_ERROR -1 /* failure */
+#define IPREASM_TRUE 1   /* true */
+#define IPREASM_FALSE 0  /* false */
+
+/* enumeration for return code from ip_reasm_compute_overlap () */
+enum ipreasm_rc
+{
+IPREASM_DROP_FRAG_DUPLICATE, /* drop just received fragment because it does not contain any unique 
+                              * data (i.e., data that is not present in one (or more) of the 
+                              * already queued fragments) */
+IPREASM_DROP_FRAG_BAD_PARAM, /* drop just received fragment because IRE pointer failed validation */
+IPREASM_ACCEPT_FRAG          /* accept just received fragment */
+};
+
+typedef enum ipreasm_rc IPREASM_RC;
+
+/* statistics data structure for the IP reassembly module */
+struct ire_stats
+{
+   u_long bad_irep;       /* bad IRE pointer supplied to function */
+   u_long ire_timed_out;  /* number of IREs that timed out while waiting 
+                           * for reassembly to complete */
+   u_long bad_max_mem;    /* number of instances when the IRE reassembly 
+                           * memory useage counter was greater than its max limit
+                           * (when checked in the ip_reasm_xxx_mem_useage () 
+                           * calls) */
+   u_long mem_check_fail; /* number of instances when a check in ip_reasm_-
+                           * check_mem_useage () indicated that the requested 
+                           * increment would cause the memory useage counter 
+                           * to go over limit */
+   u_long mem_incr_fail;  /* number of instances when a check in ip_reasm_-
+                           * incr_mem_useage () indicated that the requested 
+                           * increment would cause the memory useage counter 
+                           * to go over limit */
+   u_long mem_decr_fail;  /* number of instances when the memory counter was
+                           * smaller than the amount being decremented from it */
+};
+
+/* maximum lifetime of an IRE entry */
+#define IRE_TMO 120 /* 120 seconds */
+
+/* maximum number of fragments that can be stored in a RFQ (irrespective
+ * of whether it is statically or dynamically allocated).  See below for
+ * more information on RFQ. */
+#define IPR_MAX_FRAGS 16
+
+#define INVALID_FRAG_INDEX IPR_MAX_FRAGS /* legal values 0...15 */
+
+/* RFQ - this data structure contains pointers to queued fragments (PACKET)
+ * while they are awaiting reassembly.  One instance of this structure is 
+ * statically allocated inside a IRE; other instances can be dynamically 
+ * allocated if required.
+ */
+struct reasm_frag_queue
+   {
+   struct reasm_frag_queue * next;       /* pointer to the next RFQ */
+   struct netbuf * bufp [IPR_MAX_FRAGS]; /* array of slots containing PACKET pointers to received fragments */
+   u_short frag_offset [IPR_MAX_FRAGS];  /* starting offset of data in received fragments */
+   };
+
+typedef struct reasm_frag_queue RFQ;
+typedef struct reasm_frag_queue * RFQP;
+
+/* An IRE (or RFQ) is considered compact if there are no holes in the 
+ * RFQs, i.e., if all PACKET pointers (for the received fragments) are 
+ * clumped together (without any empty slots between them).  Holes are 
+ * created by the code in ip_reasm_compute_overlap () if it determines 
+ * that there is an overlap (between a just received fragment and an 
+ * already queued fragment) that requires it to drop the already queued 
+ * fragment.
+ *
+ * A compact RFQ allows us to stop (traversing the bufp array) when we 
+ * encounter the first empty slot; however, if the RFQ is not compact, 
+ * we must continue traversing until we reach a zero next pointer 
+ * before we can stop.
+ */
+#define IPR_RFQ_COMPACT 0x1 /* if bit is set, RFQ is compact, i.e., there are no holes in it */
+
+/* IRE - base data structure used for processing fragmented IP packets
+ * thru' reassembly.  Sibling fragments can be identified as having identical 
+ * values for the four-tuple of source IP address, destination IP 
+ * address, protocol, and identification fields.
+ */
+struct ip_reasm_entry
+   {
+   struct ip_reasm_entry * next; /* pointer to next entry in IRE list */
+   ip_addr src;    /* source IP address; stored in net endian format */
+   ip_addr dest;   /* destination IP address; stored in net endian format */
+   u_short id;     /* Identification field; stored in net endian format */
+   u_char prot;    /* Protocol field */
+   u_short length; /* length of original, unfragmented packet (in bytes) (only counts payload part of IP datagram) */
+   u_short rcvd;   /* number of bytes (of packet) received (only counts payload part of IP datagram) */
+   u_long age;     /* age - starts off at 0, and can go upto a max of the reassembly timeout (IRE_TMO) */
+   RFQ rfq;        /* queue of fragments waiting to be copied (delayed copy scheme) */
+   char * l2_hdr;  /* points to start of buffer of first fragment (FF); however, the actual
+                    * L2 header may start at an offset from the start of the buffer */
+   char * l3_hdr;  /* points to start of IP header of first fragment (FF) */
+   unsigned char flags; /* currently only bit 0 is used to indicate if RFQ is "compact" */
+   };
+
+typedef struct ip_reasm_entry IRE;
+typedef struct ip_reasm_entry * IREP;
+
+enum ip_frag_type
+{
+IP_CP = 0, /* 000; complete packet (i.e., not a fragment) */
+IP_FF = 1, /* 001; first fragment (i.e., one with Fragment Offset of 0) */
+IP_MF = 3, /* 011; middle fragment */
+IP_LF = 5  /* 101; last fragment */
+};
+
+typedef enum ip_frag_type IP_FRAGTYPE;
+
+#endif /* _IPREASM_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipdemux.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipdemux.c
new file mode 100644
index 0000000..19ba4e7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipdemux.c
@@ -0,0 +1,673 @@
+/*
+ * FILENAME: ipdemux.c
+ *
+ * Copyright 1997- 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: ip_rcv(), ip_demux(), ip_stats(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1996 by NetPort Software. 
+ * Portions Copyright 1986 by Carnegie Mellon 
+ * Portions Copyright 1984,1985 by the Massachusetts Institute of 
+ * Technology 
+ */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+
+#ifdef IP_MULTICAST
+#include "../ipmc/igmp.h"
+#endif
+
+#ifdef INCLUDE_TCP
+#define  TCP_PROT 6
+extern   int tcp_rcv(PACKET pkt);
+#endif
+
+#ifdef USE_IPFILTER
+int ipf_filter(PACKET p, int dir);
+#endif
+
+#ifdef NATRT
+extern unsigned char do_nat (PACKET p
+#ifdef IP_FRAGMENTS
+                             , PACKET ** pktpp,
+                             unsigned short int * pkt_countp
+#endif
+);
+extern void nat_free (void * ptr);
+extern   ip_addr  nat_inaddr; /* NAT's default internet address */
+#endif   /* NATRT */
+
+#ifdef IP_FRAGMENTS  /* in case we fragment natrouted pkt */
+int   ip_fragment(PACKET p, ip_addr firsthop);
+#endif   /* IP_FRAGMENTS */
+
+#ifdef IP_RAW
+int   ip_raw_input(PACKET P);
+#endif   /* IP_RAW */
+
+#ifdef INCLUDE_6TO4
+extern int  v6t_rcv(PACKET p);
+#endif   /* INCLUDE_6TO4 */
+
+#ifdef IPSEC
+void  ipsec_forward(PACKET *p);
+void  ipsec_inbound(PACKET *p);
+#endif   /* IPSEC */
+
+#ifdef RF_SIMULATION
+extern int rfsim_routing;   /* Bool, TRUE if we're doing this */
+extern int rfsim_send(void * vpkt, u_long firsthop);
+#endif /* RF_SIMULATION */
+
+int ip_rcv_phase2 (PACKET p);
+
+/* FUNCTION: ip_rcv()
+ *
+ * This is the IP receive upcall routine. It handles packets received 
+ * by network ISRs, etc. verifies their Ip headers and does the 
+ * upcall to the upper layer that should receive the packet. Returns 
+ * 0 if packet was processed succesfully, ENP_NOT_MINE if not for me, 
+ * or a negative error code if packet was badly formed. 
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: 
+ */
+
+int
+ip_rcv(PACKET p)
+{
+   struct ip * pip;     /* the internet header */
+   unsigned short csum; /* packet checksum */
+   unsigned short tempsum;
+   unsigned hdrlen;  /* length of IP header including options */
+   unsigned len;     /* total length including IP header */
+   unsigned short int num_pkts;
+   PACKET * pktp;
+   unsigned char i;
+   int rcvrc = -1;
+#ifdef NATRT
+   unsigned char rc_ret;
+#endif
+
+
+#ifdef NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      dprintf("ip_rcv: got packet, len:%d, if:%d\n",
+         p->nb_plen, net_num(p->net));
+#endif
+
+   IN_PROFILER(PF_IP, PF_ENTRY);
+
+   ip_mib.ipInReceives++;
+   pip = ip_head(p);
+
+   /* test received MAC len against IP header len */
+   if (p->nb_plen < (unsigned)htons(pip->ip_len))
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ip_rcv: bad pkt len\n");
+         if (NDEBUG & DUMP) ip_dump(p);
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+   }
+
+   /* use length from IP header; MAC value may be padded */
+   len = htons(pip->ip_len);
+   p->nb_plen = len;       /* fix pkt len */
+
+   if ( ((pip->ip_ver_ihl & 0xf0) >> 4) != IP_VER)
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ip_rcv: bad version number\n");
+         if (NDEBUG & DUMP) ip_dump(p);
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+   }
+
+   csum = pip->ip_chksum;
+   pip->ip_chksum = 0;
+   hdrlen = ip_hlen(pip);
+   tempsum = ~cksum(pip, hdrlen >> 1);
+
+   if (csum != tempsum)
+   {
+      pip->ip_chksum = csum;
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ip_rcv: bad xsum\n");
+         if (NDEBUG & DUMP) ip_dump(p);
+            }
+#endif
+      ip_mib.ipInHdrErrors++;
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_BAD_HEADER);
+   }
+
+   pip->ip_chksum = csum;
+
+
+#ifdef USE_IPFILTER
+   /* Do IP filtering. If packet is accepted, ipf_filter() returns
+    * SUCCESS. Discard the packet for all other return values 
+    */
+   if (ipf_filter(p,1) != SUCCESS)  /* 1 - inbound pkt */
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_NO_ROUTE;
+   }
+#endif
+
+    /* start off by assuming that we will only process the "current" packet;
+     * these values may get overwritten by the NAT module if it returns
+     * more than one packet back to this function (ip_rcv ()) */
+    num_pkts = 1;
+    pktp = &p;
+
+#ifdef NATRT   /* is this part of Network Address Translation box? */
+   {
+      IN_PROFILER(PF_NAT, PF_ENTRY);
+      if ((rc_ret = do_nat(p
+#ifdef IP_FRAGMENTS
+                             , &pktp,
+                             &num_pkts
+#endif
+                             )) == 0)
+      {
+         IN_PROFILER(PF_NAT, PF_EXIT);
+         return 0;
+      }
+      IN_PROFILER(PF_NAT, PF_EXIT);
+   }
+   /* NAT has returned one (or more) packets back to the stack for processing 
+    * by other modules */
+#endif   /* NATRT */
+
+   /* we need to process 'num_pkts' packets.  Pointers to these packets are stored
+    * in storage @ 'pktp' */
+   for (i = 0; i < num_pkts; ++i)
+   {
+      rcvrc = ip_rcv_phase2 (*(pktp + i));
+   }
+
+#ifdef NATRT
+   /* free any allocated storage */
+   if (pktp != &p) nat_free (pktp);
+#endif /* NATRT */
+
+   /* when multiple packets are processed in the loop above, the return code
+    * contains the return code for the last packet */
+   return rcvrc;
+}
+
+
+int ip_rcv_phase2 (PACKET p)
+{
+
+   struct ip * pip;     /* the internet header */
+   NET nt;
+   unsigned short tempsum;
+
+   pip = ip_head(p);
+   nt = p->net;      /* which interface it came in on */
+
+#ifdef IP_MULTICAST
+
+   if (IN_MULTICAST(ntohl(pip->ip_dest))) 
+   {
+      /* If we are acting as a multicast router, all multicast incoming
+       * packets will be passed to a multicast forwarding function.
+       * For release 1.5, there is no multicast router functionality
+       * added.
+       */
+      struct in_multi * inm;
+      /*
+       * See if we belong to the destination multicast group on the
+       * arrival interface.
+       */
+      inm = lookup_mcast(pip->ip_dest, nt);
+      if (inm == NULL) 
+      {
+         ip_mib.ipOutNoRoutes++;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return (ENP_NOT_MINE);
+      }
+      else
+         goto ours;
+   }
+#endif   /* IP_MULTICAST */
+
+   if ((pip->ip_dest != nt->n_ipaddr) &&  /* Quick check on our own addr */
+       (pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+       (pip->ip_dest != nt->n_netbr) &&   /* All subnet broadcast */
+       (pip->ip_dest != nt->n_netbr42) && /* All subnet bcast (4.2bsd) */
+       (pip->ip_dest != nt->n_subnetbr) &&/* Our subnet broadcast */
+       (nt->n_ipaddr & ~nt->snmask))      /* Know our own host address? */
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+         dprintf("ip_rcv: got pkt not for me; for %u.%u.%u.%u\n",
+       PUSH_IPADDR(pip->ip_dest));
+#endif
+
+#ifdef IP_ROUTING    /* if multi-homed router, try to route */
+      /* Do routing only if ipForwarding is enabled in the IP MIB. This
+       * is the switch for routing whether SNMP is used or not.
+       */
+      if (ip_mib.ipForwarding == 2)
+      {
+         ip_mib.ipOutDiscards++; /* Is this the right counter for these? */
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(p);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         IN_PROFILER(PF_IP, PF_EXIT);
+         return ENP_NO_ROUTE;
+      }
+      else
+      {
+         ip_addr firsthop;       /* fake nexthop for passing to iproute */
+         NET outnet;
+#ifdef IP_FRAGMENTS
+         int err;
+#endif
+
+         ip_mib.ipForwDatagrams++;  /* Count MIB-2 route attempts here */
+         if (pip->ip_time <= 1)     /* Time to Live (hopcount) expired? */
+         {
+            ip_mib.ipOutDiscards++; /* Is this the right counter for these? */
+#ifdef FULL_ICMP
+            icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, (TIMEX <<8), p->net);
+#endif   /* FULL_ICMP */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NO_ROUTE;
+         }
+
+         p->fhost = pip->ip_dest;   /* set packet's target IP in net endian */
+         if ((outnet = iproute(p->fhost, &firsthop)) == NULL)  /* find route */
+         {
+            ip_mib.ipOutNoRoutes++; /* count unroutable pkts */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_NO_ROUTE;
+         }
+
+#ifdef STRICT_ROUTE
+         /* make sure packet won't route back out iface it came in on. This
+          * used to be an absolute rule of IP routing, however newer technologies
+          * like NAT sometimes need to break this rule. We recommend you leave
+          * this code disabled unless you have a special need for it.
+          */
+         if (outnet == p->net)
+         {
+            ip_mib.ipOutNoRoutes++;
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return(ENP_NOT_MINE);
+         }
+#endif   /* STRICT_ROUTE */
+
+         /* Check to see if the packet was is addressed to one of our IP
+          * addresses other than the interface it was received on. If so,
+          * routing should have returned that interface and we can trap this
+          * situation by checking the interfaces IP address.
+          */
+         if(pip->ip_dest == outnet->n_ipaddr)
+            goto ours;
+
+         /* Make sure the packet is not a subnet broadcast for either the
+          * source or destination network.
+          */
+         if((pip->ip_dest == outnet->n_netbr) ||
+            (pip->ip_dest == p->net->n_netbr))
+         {
+            goto ours;            
+         }
+
+         /* Routed OK, prepare to send */
+         p->net = outnet;           /* set iface to send on */
+
+#ifdef IPSEC
+         IN_PROFILER(PF_IPSEC, PF_ENTRY);
+         ipsec_forward(&p);
+         IN_PROFILER(PF_IPSEC, PF_EXIT);
+         if (p == NULL)
+         {
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return ENP_LOGIC;
+         }
+         if (!(p->fhost))
+         {
+            pip = ip_head(p);
+            p->fhost = pip->ip_dest;
+            if ((outnet = iproute(p->fhost, &firsthop)) == NULL)
+            {
+               ip_mib.ipOutNoRoutes++;
+               LOCK_NET_RESOURCE(FREEQ_RESID);
+               pk_free(p);
+               UNLOCK_NET_RESOURCE(FREEQ_RESID);
+               IN_PROFILER(PF_IP, PF_EXIT);
+               return ENP_NO_ROUTE;
+            }
+         }
+#endif   /* IPSEC */
+
+         /* see if packet is too big for media of dest net */
+         if ((p->nb_plen + p->net->n_lnh) > (unsigned)outnet->n_mtu)
+         {
+#ifdef IP_FRAGMENTS
+            /* see if we're not supposed to fragment it */
+            if (ntohs(pip->ip_flgs_foff) & IP_FLG_DF)
+            {
+#ifdef FULL_ICMP
+               icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTFRAG, p->net);
+#endif   /* FULL_ICMP */
+               ip_mib.ipFragFails++;
+               LOCK_NET_RESOURCE(FREEQ_RESID);
+               pk_free(p);
+               UNLOCK_NET_RESOURCE(FREEQ_RESID);
+               IN_PROFILER(PF_IP, PF_EXIT);
+               return ENP_LOGIC;
+            }
+
+            /* fall to here if we're going to fragment it. */
+            pip->ip_time--;            /* datagram's hop count */
+            err = ip_fragment(p, firsthop);
+            IN_PROFILER(PF_IP, PF_EXIT);
+            return(err);
+#else /* IP fragments not supported? Bad news....*/
+            dtrap(); /* this should be caught by programmers during development */
+#ifdef FULL_ICMP
+            icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTFRAG, p->net);
+#endif   /* FULL_ICMP */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(p);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            return ENP_LOGIC;
+#endif   /* IP_FRAGMENTS */
+         }
+         pip->ip_time--;            /* datagram's hop count */
+         pip->ip_chksum = IPXSUM;   /* clear checksum field for summing */
+         pip->ip_chksum = ~cksum(pip, 10);   /* new xsum */
+         IN_PROFILER(PF_IP, PF_EXIT);
+#ifdef RF_SIMULATION
+         if(rfsim_routing)
+            return(rfsim_send(p, firsthop));
+#endif   /* RF_SIMULATION */
+         return(ip2mac(p, firsthop));
+      }
+#else /* not IP_ROUTING, punt the packet */
+      ip_mib.ipInAddrErrors++;
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return(ENP_NOT_MINE);
+#endif
+   }
+
+#if defined (IP_MULTICAST) || defined (IP_ROUTING)
+ours:
+#endif
+
+   /* Test for fragment: */
+   tempsum = htons(pip->ip_flgs_foff); /* borrow cksum variable */
+   if ((tempsum & IP_FLG_MF) ||  /* IP flag for "More Fragments" set? */
+       (tempsum & ~IP_FLG_MASK))  /* or offset to last frag? */
+   {
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ip_rcv: fragment from %u.%u.%u.%u\n", 
+          PUSH_IPADDR(pip->ip_src));
+         ip_dump(p);
+      }
+#endif
+      ip_mib.ipReasmReqds++;     /* got a reassemble request; ie a frag */
+#ifdef IP_FRAGMENTS
+      return(ip_reassm(p));
+#else
+      ip_mib.ipReasmFails++;     /* we don't do these */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(p);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      IN_PROFILER(PF_IP, PF_EXIT);
+      return ENP_NOT_MINE;    /* perhaps should be ENP_BAD_HEADER? */
+#endif
+   }
+
+   IN_PROFILER(PF_IP, PF_EXIT);
+
+#ifdef IPSEC
+   /* Since ip_rcv may be called re-entrantly, ensure that we EXIT from
+    * profiler before calling IPSEC
+    */
+   IN_PROFILER(PF_IPSEC, PF_ENTRY);
+   ipsec_inbound(&p);
+   IN_PROFILER(PF_IPSEC, PF_EXIT);
+   if (p == NULL)
+   {
+      return ENP_LOGIC;
+   }
+#endif /* IPSEC */
+
+   return(ip_demux(p));    /* demux to correct to upper layer */
+}
+
+/* FUNCTION: ip_demux()
+ *
+ * ip_demux() - actual upcall from IP to upper layers. This called by 
+ * ip_rcv to pass the packets to the upper layers. This is seperate 
+ * ip_rcv because it may need to be called by IP fragment reassembly 
+ * logic. 
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: Same return values as ip_rcv(). 
+ */
+
+int
+ip_demux(PACKET p)
+{
+   struct ip * pip;  /* the internet header */
+   int   err;
+
+   /* The packet is verified; the header is correct. Now we have
+    * to demultiplex it among our internet connections.
+    */
+   pip = (struct ip *)(p->nb_prot);
+
+#ifdef NPDEBUG
+   /* make sure the caller set p->nb_prot */
+   if(pip->ip_ver_ihl != 0x45)
+   {
+      if((pip->ip_ver_ihl < 0x45) ||
+         (pip->ip_ver_ihl > 0x47))
+      {
+         dprintf("ip_demux: bad IP type 0x%x\n", pip->ip_ver_ihl);
+         return ENP_LOGIC;
+      }
+   }
+#endif /* NPDEBUG */
+
+   /* for profiling purposes count the upper layers (UDP, ICMP) in the IP
+    * profile bucket. TCP will insert it's own nested profile calls 
+    */
+   IN_PROFILER(PF_IP, PF_ENTRY);
+   p->fhost = pip->ip_src;
+
+#ifdef NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+   {
+      dprintf("ip_demux: pkt prot %u from %u.%u.%u.%u\n",
+       pip->ip_prot, PUSH_IPADDR(pip->ip_src));
+      if (NDEBUG & DUMP) ip_dump(p);
+   }
+#endif
+
+   switch (pip->ip_prot)
+   {
+   case UDP_PROT:
+      ip_mib.ipInDelivers++;
+      err = udpdemux(p);
+      break;
+   case ICMP_PROT:
+      ip_mib.ipInDelivers++;
+      err = icmprcv(p);
+      break;
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   case IGMP_PROT:
+      ip_mib.ipInDelivers++;
+      err = igmp_input(p);
+      break;
+#endif   /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+#ifdef INCLUDE_TCP
+   case TCP_PROT:
+      ip_mib.ipInDelivers++;
+      err = tcp_rcv(p);
+      break;
+#endif   /* TCP support */
+#ifdef IPV6_TUNNEL
+   case 0x29:     /* IPv6 tunnel type */
+      err = v6t_rcv(p);
+      break;
+#endif /* IPV6_TUNNEL */
+   default: /* unknown upper protocol */
+#ifdef IP_RAW
+      ip_mib.ipInDelivers++;
+      err = ip_raw_input(p);
+      break;
+#else  /* IP_RAW */
+      ip_mib.ipUnknownProtos++;
+      /* set err so we can tell if the packet was handled by an
+       * upcall or not.
+       */
+      err = ENP_PARAM;
+      break;
+#endif /* IP_RAW */
+   }
+
+   IN_PROFILER(PF_IP, PF_EXIT);
+
+   if(err != ENP_PARAM)
+   {
+      return err;
+   }
+   /* fall to here if transport protocol not supported */
+
+#ifdef FULL_ICMP
+   /* nobody's listening for this packet. Unless it was broadcast or 
+    * multicast, send a destination unreachable. 
+    */
+   if ((pip->ip_dest != 0xffffffffL) &&   /* Physical cable broadcast addr*/
+#ifdef IP_MULTICAST
+       (!(IN_MULTICAST(ntohl(pip->ip_dest)))) && /* multicast address */
+#endif /* IP_MULTICAST */
+       (pip->ip_dest != p->net->n_netbr) &&   /* All subnet broadcast */
+       (pip->ip_dest != p->net->n_netbr42) && /* All subnet bcast (4.2bsd) */
+       (pip->ip_dest != p->net->n_subnetbr) &&   /* Our subnet broadcast */
+       (p->net->n_ipaddr ^ p->net->n_subnetbr))  /* Know our own host address? */
+   {
+
+#ifdef NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & IPTRACE))
+      {
+         dprintf("ip_demux: unhandled prot %u\n", pip->ip_prot);
+         if (NDEBUG & DUMP) ip_dump(p);
+      }
+#endif   /* NPDEBUG */
+      icmp_destun(pip->ip_src, p->net->n_ipaddr, pip, DSTPROT, p->net);
+   }
+#endif   /* FULL_ICMP */
+
+   ip_mib.ipUnknownProtos++;
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   return ENP_NOT_MINE;
+}
+
+#ifdef NET_STATS
+
+/* FUNCTION: ip_stats()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ip_stats(void * pio)
+{
+   ns_printf(pio,"IP MIB statistics:\n");
+   ns_printf(pio,"Gateway: %s     default TTL: %lu\n",
+     (ip_mib.ipForwarding == 1)?"YES":"NO", ip_mib.ipDefaultTTL);
+   ns_printf(pio,"rcv:  total: %lu    header err: %lu    address err: %lu\n",
+     ip_mib.ipInReceives, ip_mib.ipInHdrErrors, ip_mib.ipInAddrErrors);
+   ns_printf(pio,"rcv:  unknown Protocls: %lu    delivered: %lu\n",
+     ip_mib.ipUnknownProtos, ip_mib.ipInDelivers);
+   ns_printf(pio,"send: total: %lu    discarded: %lu     No routes: %lu\n",
+     ip_mib.ipOutRequests, ip_mib.ipOutDiscards, ip_mib.ipOutNoRoutes);
+   ns_printf(pio,"Routing; forwarded: %lu    discarded: %lu\n",
+     ip_mib.ipForwDatagrams, ip_mib.ipRoutingDiscards);
+   ns_printf(pio,"Recvd fragments: %lu, Frames reassembled: %lu\n",
+     ip_mib.ipReasmReqds, ip_mib.ipReasmOKs);
+   ns_printf(pio,"Pkts fragmented: %lu, Fragments sent: %lu, dropped: %lu\n",
+     ip_mib.ipFragOKs, ip_mib.ipFragCreates, ip_mib.ipFragFails);
+   ns_printf(pio,"Reasm.Timeout: %lu seconds,  Reasm.Errors: %lu\n",
+     ip_mib.ipReasmTimeout, ip_mib.ipReasmFails);
+
+   return 0;
+}
+
+#endif   /* NET_STATS */
+
+/* end of file ipdemux.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipmc.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipmc.c
new file mode 100644
index 0000000..d60637f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipmc.c
@@ -0,0 +1,242 @@
+/*
+ * FILENAME: ipmc.c
+ *
+ * Copyright 1997- 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains the code to handle IP multicast addreses. Works
+ * for both IPv4 and IPv6.
+ *
+ * MODULE: IP
+ *
+ * ROUTINES: in_addmulti(), in_delmulti(), 
+ * ROUTINES: mcaddr_net(), lookup_mcast(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef IP_MULTICAST
+
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#include "../ipmc/igmp.h"
+
+#ifdef IP_V6
+#include "ip6.h"
+#endif   /* IP_V6 */
+
+
+/* FUNCTION: in_addmulti()
+ *
+ * Add an address to the list of IP multicast addresses for a given interface.
+ *
+ * PARAM1: ip_addr * ap
+ * PARAM2: struct net * netp
+ * PARAM3: addrtype 6 if ip_addr is IPv6, else addr is v4
+ *
+ * RETURNS: 
+ */
+
+struct in_multi * 
+in_addmulti(ip_addr *ap, struct net *netp, int addrtype)
+{
+   struct in_multi *inm = (struct in_multi *)NULL;
+   int error;
+
+   /* check for good addr. */
+   if ((ap == (ip_addr *)NULL) || (*ap == 0))
+      return ((struct in_multi *)NULL);  
+
+   ENTER_CRIT_SECTION(netp);
+
+   /* See if address already in list. */
+#ifdef IP_V6
+   if(addrtype == 6)
+      inm = v6_lookup_mcast((ip6_addr*)ap, netp);
+#endif
+#ifdef IP_V4
+   if(addrtype != 6)
+      inm = lookup_mcast(*ap, netp);
+#endif
+
+   if (inm != (struct in_multi *)NULL) 
+   {
+      /* Found it; just increment the reference count. */
+      ++inm->inm_refcount;
+   }
+   else
+   {
+      /*
+       * New address; allocate a new multicast record
+       * and link it into the interface's multicast list.
+       */
+      inm = (struct in_multi *)INM_ALLOC(sizeof(*inm));
+
+      if (inm == (struct in_multi *)NULL) 
+      {
+         EXIT_CRIT_SECTION(netp);
+         return ((struct in_multi *)NULL);
+      }
+#ifdef IP_V6
+      if(addrtype == 6)
+         IP6CPY(&inm->ip6addr, (struct in6_addr *)ap);
+#endif
+#ifdef IP_V4
+      if(addrtype != 6)
+         inm->inm_addr = *ap;
+#endif
+      inm->inm_netp = netp;
+      inm->inm_refcount = 1;
+      inm->inm_next = netp->mc_list;
+      netp->mc_list = inm;
+
+      /*
+       * If net has a multicast address registration routine then ask
+       * the network driver to update its multicast reception
+       * filter appropriately for the new address.
+       */
+      if(netp->n_mcastlist)
+         error = netp->n_mcastlist(inm);
+      else
+         error = 0;
+#if defined (IGMP_V1) || defined (IGMP_V2)
+      /*
+       * Let IGMP know that we have joined a new IP multicast group.
+       */
+      if (inm->inm_addr) igmp_joingroup(inm);
+#endif      
+   }
+
+   EXIT_CRIT_SECTION(netp);
+   USE_ARG(error);
+
+   return (inm);
+}
+
+
+
+/* FUNCTION: in_delmulti()
+ *
+ * Delete a multicast address record.
+ *
+ * PARAM1: struct in_multi *inm
+ *
+ * RETURNS: 
+ */
+
+void
+in_delmulti(struct in_multi * inm)
+{
+   struct in_multi * p;
+   NET         netp = inm->inm_netp;
+   int error;
+
+   ENTER_CRIT_SECTION(inm);
+   if (--inm->inm_refcount == 0) 
+   {
+      /* Unlink from list.  */
+      for (p = netp->mc_list; p; p = p->inm_next)
+      {
+         if(p == inm)   /* inm is first in mc_list */
+         {
+            netp->mc_list = p->inm_next;  /* unlink */
+            break;
+         }
+         else if(p->inm_next == inm)   /* inm is next */
+         {
+            p->inm_next = inm->inm_next;  /* unlink */
+            break;
+         }
+      }
+
+      /*
+       * If net has a multicast address registration routine then ask
+       * the network driver to update its multicast reception
+       * filter appropriately for the deleted address.
+       */
+      if(netp->n_mcastlist)
+         error = netp->n_mcastlist(inm);
+      else
+         error = 0;
+#if defined (IGMP_V2)
+      /*
+       * No remaining claims to this record; let IGMP know that
+       * we are leaving the multicast group.
+       */
+      if (inm->inm_addr) igmp_leavegroup(inm);
+#endif      
+
+      IM_FREE(inm);
+   }
+
+   EXIT_CRIT_SECTION(inm);
+   USE_ARG(error);
+}
+
+
+
+#ifdef IP_V4
+
+/* FUNCTION: lookup_mcast()
+ *
+ * Look for the passed IPv4 address in the iface poassed.
+ *
+ * PARAM1: ip_addr addr
+ * PARAM2: NET netp
+ *
+ * RETURNS: pointer to mcast addr structure, or NULL if not found.
+ */
+
+struct in_multi *
+lookup_mcast(ip_addr addr, NET netp)
+{
+   struct in_multi * imp;
+
+   for (imp = netp->mc_list; imp; imp = imp->inm_next)
+   {
+      if(imp->inm_addr == addr)
+         return imp;
+   }
+   return NULL;   /* addr not found in mcast list */
+}
+#endif   /* IP_V4 */
+
+
+#ifdef IP_V6
+
+/* FUNCTION: v6_lookup_multi()
+ *
+ * Look for the passed IPv6 address in the iface poassed.
+ *
+ * PARAM1: ip6_addr * - address to match
+ * PARAM2: NET netp - interface to search
+ *
+ * RETURNS: pointer to mcast addr structure, or NULL if not found.
+ */
+
+struct in_multi *
+v6_lookup_mcast(ip6_addr * ipp, NET netp)
+{
+   struct in_multi * imp;
+
+   for (imp = netp->mc_list; imp; imp = imp->inm_next)
+   {
+      if(IP6EQ(&imp->ip6addr, ipp))
+         return imp;
+   }
+   return NULL;   /* addr not found in mcast list */
+
+}
+#endif   /* IP_V6 */
+
+#endif   /* IP_MULTICAST */
+
+
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipnet.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipnet.c
new file mode 100644
index 0000000..d98c874
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipnet.c
@@ -0,0 +1,727 @@
+/*
+ * FILENAME: ipnet.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * System code called from ip_startup(), et.al. to do low level
+ * initialization of network structures, packet queues, etc.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: Netinit(), netclose(), net_stats(), pktdemux(), 
+ * ROUTINES: c_older(), ip2mac(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1994 by NetPort Software  */
+/*  Copyright 1986 by Carnegie Mellon  */
+/*  Copyright 1984, 1985 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#ifdef INCLUDE_ARP
+#include "arp.h"
+#endif
+
+#include "ether.h"
+
+#ifdef DYNAMIC_IFACES   /* Install dynamic iface menu */
+#ifdef IN_MENUS   /* need this too */
+#include "menu.h"
+extern struct menu_op dynif_menu[];
+#endif /* IN_MENUS */
+#endif /* DYNAMIC_IFACES */
+
+#ifdef USE_PPPOE
+int   poe_rcv(PACKET pkt);
+#endif   /* USE_PPPOE */
+
+#ifdef  LOSSY_IO
+/* support for an option that allows us to deliberatly loose packets */
+int   in_lastloss = 0;  /* packets since last loss */
+int   in_lossrate = 10; /* number of packets to punt (30 is "1 in 30") */
+static unsigned long myrandVal = ((unsigned long)0x29823745);
+static unsigned long myrandMods = 222;
+unsigned long myrandNum  = 1;
+unsigned long myrandDenom = 20;
+#endif   /* LOSSY_IO */
+
+
+queue    rcvdq;         /* queue of all received (but undemuxed) packets */
+
+int      MaxLnh   =  0;       /* Length of the biggest local net header in the whole system */
+int      MaxMtu   =  0;       /* length of biggest MAC packet */
+
+unsigned NDEBUG = 0;       /* Debugging...*/
+
+void   fixup_subnet_mask(int);
+
+
+/* FUNCTION: Netinit()
+ *
+ * Netinit() - This routine does the basic initialization of the IP 
+ * protocol stack. It assumes the clock is already initialized. It 
+ * also assumes the net[] structures have been at least partially set 
+ * up, with n_mtu, n_lnh and init() variables set; and that ifNumber 
+ * has been set to the number of nets[]. It does (in order): - Packet 
+ * buffer initialization, creation of the free queue. - Per net 
+ * interface init. . 
+ *
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: Netinit() returns 0 if everything inited OK, else 
+ * a non-zero error code
+ */
+
+int
+Netinit()
+{
+   int   i; /* general counter variable */
+   int   e; /* error holder */
+
+#ifndef MULTI_HOMED
+   ifNumber = 1;     /* prevents weird behavior below... */
+#endif
+
+   /* set our largest header size and frames size */
+   for (i = 0; i < (int)ifNumber; i++)
+   {
+      /* sanity check on mtu, et.al. We added this because earlier 
+       * drivers were sloppy about setting them, but new
+       * logic depends on these sizes.
+       */
+      if (nets[i]->n_mib->ifType == ETHERNET)   /* ethernet? */
+      {
+         if (nets[i]->n_mtu == 0)   /* let device code override */
+            nets[i]->n_mtu = 1514;
+
+         if (nets[i]->n_lnh == 0)
+         {
+#ifdef IEEE_802_3
+            nets[i]->n_lnh = ETHHDR_SIZE + sizeof(struct snap_hdr);
+#else
+            nets[i]->n_lnh = ETHHDR_SIZE;
+#endif
+         }
+      }
+#ifdef IP_V6
+      /* Ignore IPv6 tunnels for lnh and mtu values */
+      if((nets[i]->n_mib->ifType == IP6GIF) ||
+         (nets[i]->n_mib->ifType == IP6TO4))
+      {
+         continue;
+      }
+#endif   /* IP_V6 */
+
+      MaxLnh = max(MaxLnh, nets[i]->n_lnh);
+      MaxMtu = max(MaxMtu, nets[i]->n_mtu);
+   }
+
+   /* set up the received packet queue */
+   rcvdq.q_head = rcvdq.q_tail = NULL;
+   rcvdq.q_max = rcvdq.q_min = rcvdq.q_len = 0;
+
+   /* initialize freeq */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   e = pk_init();
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (e)   /* report error (memory ran out?) */
+      return e;
+
+   /* packet buffers in freeq are now all set. */
+   exit_hook(netclose);       /* Clean up nets when we are unloaded */
+
+   /* now do the per-IP interface initializations */
+   for (i = 0; i < (int)ifNumber; i++)
+   {
+      if (nets[i]->n_init != NULL)  /* If iface has init routine... */
+      {
+         if ((e = (*nets[i]->n_init)(i)) != 0)  /* call init routine */
+         {
+            dprintf("init error %d on net[%d]\n", e, i);
+            nets[i]->n_mib->ifOperStatus = NI_DOWN;
+            continue;   /* ignore ifaces which fail */
+         }
+         /* If interface is ethernet, set bcast flag bit. This
+          * should really be done by the init routine, but we handle it
+          * here to support MAC drivers which predate the flags field.
+          */
+         if(nets[i]->n_mib->ifType == ETHERNET)
+            nets[i]->n_flags |= NF_BCAST;
+
+         /* set ifAdminStatus in case init() routine forgot to. IfOperStatus
+          * is not nessecarily up at this point, as in the case of a modem which
+          * is now in autoanswer mode.
+          */
+         nets[i]->n_mib->ifAdminStatus = NI_UP;
+
+         /* assign default names to unnamed ifaces */
+         if(nets[i]->name[0] == 0)     /* no name set by prep or init */
+         {
+            if(nets[i]->n_mib->ifType == ETHERNET)
+            {
+               nets[i]->name[0] = 'e';    /* "et1", "et2", etc. */
+               nets[i]->name[1] = 't';
+            }
+            else
+            {
+               nets[i]->name[0] = 'i';    /* "if1", "if2", etc. */
+               nets[i]->name[1] = 'f';
+            }
+            nets[i]->name[2] = (char)(i + '1');
+            nets[i]->name[3] = '\0';
+         }
+      }
+      /* check on subnet routing - if no mask then make one */
+      fixup_subnet_mask(i);      /* make mask for this net */
+
+      /* build broadcast addresses */
+      if(nets[i]->n_ipaddr != 0)
+      {
+         nets[i]->n_netbr = nets[i]->n_ipaddr | ~nets[i]->snmask;
+         nets[i]->n_netbr42 = nets[i]->n_ipaddr & nets[i]->snmask;
+         nets[i]->n_subnetbr = nets[i]->n_ipaddr | ~nets[i]->snmask;
+      }
+   }
+
+#if defined(DYNAMIC_IFACES) && defined(IN_MENUS)
+   /* Install dynamic iface menu */
+   install_menu(&dynif_menu[0]);
+#endif /* DYNAMIC_IFACES && IN_MENUS */
+
+   return(0);
+}
+
+/* FUNCTION: fixup_subnet_mask()
+ *
+ * fixup_subnet_mask() - If not subnet mask has been set by the 
+ * port's init code, make adefault on form the IP address 
+ *
+ * 
+ * PARAM1: int netnum
+ *
+ * RETURNS: 
+ */
+
+void
+fixup_subnet_mask(int netnum)      /* which of the nets[] to do. */
+{
+   u_long   smask;
+
+   if (nets[netnum]->snmask)  /* if mask is already set, don't bother */
+      return;
+
+   /* things depending on IP address class: */
+   if ((nets[netnum]->n_ipaddr & AMASK) == AADDR)
+      smask = 0xFF000000L;
+   else if((nets[netnum]->n_ipaddr & BMASK) == BADDR)
+      smask = 0xFFFF0000L;
+   else if((nets[netnum]->n_ipaddr & CMASK) == CADDR)
+      smask = 0xFFFFFF00L;
+   else
+   {
+      dtrap();    /* bad logic or setup values */
+      smask = 0xFFFFFF00L;
+   }
+   nets[netnum]->snmask = htonl(smask);
+}
+
+
+/* FUNCTION: netclose()
+ *
+ * netclose() - This routine is called to shut down the nets. It 
+ * calls the net_close routine associated with each network interface 
+ * which should release the adapter and any other resources which it 
+ * might have been using. 
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void
+netclose()
+{
+   NET ifp;
+   int index = 0;
+
+#ifdef NPDEBUG
+   if (NDEBUG & INFOMSG)   dprintf("netclose() called\n");
+#endif
+
+   for (ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next)
+   {
+      if (ifp->n_close)
+      {
+         dprintf("netclose: closing iface %s\n", ifp->n_mib->ifDescr);
+         (*(ifp->n_close))(index++);
+      }
+      else
+      {
+#ifdef NPDEBUG
+         if (NDEBUG & INFOMSG) dprintf("net %s: no close routine!\n", ifp->name);
+#endif
+         index++;
+      }
+   }
+}
+
+
+#ifdef SHARED_IPADDRS
+int   add_share_route(PACKET pkt);
+
+/* FUNCTION: add_share_route()
+ *
+ * Add a route table entry which forces Ip replies to the sender out the
+ * same interface the packet came in on. 
+ * 
+ * PARAM1: IP pkt, with np_prot pointingto header.
+ *
+ * RETURNS: 0 if oK, else ENP_ error code
+ */
+
+int
+add_share_route(PACKET pkt)
+{
+   int      iface;
+   ip_addr  nexthop;
+   RTMIB    rt;
+   struct ip * pip;
+   NET      ifp;
+
+   pip = (struct ip * )pkt->nb_prot;
+   rt = rt_lookup(pip->ip_src);
+   ifp = pkt->net;               /* net we received packet on */
+   iface = if_netnumber(ifp);    /* We need net index too.... */
+
+   /* if we already have a route, just patch the net & return. */
+   if(rt && (rt->ipRouteDest == pip->ip_src))
+   {
+      rt->ifp = ifp;
+      return 0;
+   }
+
+   /* Figure out what to use for a "next hop". If it appears
+    * to be a local IP address, then use the IP address of the
+    * sender; else if there is a route get the GW from that, else if
+    * the iface has one use that. As a last resort, fall back to using
+    * the sender's address as a next hop.
+    */
+   if((ifp->n_ipaddr & ifp->snmask)  ==
+      (pip->ip_src & ifp->snmask))
+   {
+         nexthop = pip->ip_src;
+   }
+   else if(rt)
+      nexthop = rt->ipRouteNextHop;
+   else if(pkt->net->n_defgw)
+      nexthop = ifp->n_defgw;
+   else
+      nexthop = pip->ip_src;
+
+
+   /* Now make an explicit route back to the sender */
+   rt = add_route(pip->ip_src, 0xFFFFFFFF, nexthop, iface, IPRP_OTHER);
+
+   if(rt)
+      return 0;
+   else
+      return ENP_RESOURCE;
+}
+#endif /* SHARED_IPADDRS */
+
+
+/* FUNCTION: pktdemux()
+ *
+ * pktdemux() - The received packet demuxing task. We try to run this 
+ * whenever there are unprocessed packets in rcvdq. It dequeues the 
+ * packet and sends it to a protocol stack based on type. 
+ *
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+
+void
+pktdemux()
+{
+   PACKET   pkt;
+   NET      ifc;                /* interface packet came from */
+   IFMIB    mib;
+   int      pkts;
+   char *   eth;
+
+   pkts = 0;   /* packets per loop */
+
+   while (rcvdq.q_len)
+   {
+      /* If we are low on free packets, don't hog CPU cycles */
+      if (pkts++ > bigfreeq.q_len)
+      {
+#ifdef SUPERLOOP
+         return;        /* don't hog stack on superloop */
+#else    /* SUPERLOOP */
+         tk_yield(); /* let application tasks process received packets */
+         pkts = 0;   /* reset counter */
+#endif   /* SUPERLOOP else */
+      }
+
+      /* If we get receive interupt from the net during this
+      lock, the MAC driver needs to wait or reschedule */
+      LOCK_NET_RESOURCE(RXQ_RESID);
+      pkt = (PACKET)q_deq(&rcvdq);
+      UNLOCK_NET_RESOURCE(RXQ_RESID);
+      if (!pkt) panic("pktdemux: got null pkt");
+      ifc = pkt->net;
+
+      mib = ifc->n_mib;
+      /* maintain mib stats for unicast and broadcast */
+      if (isbcast(ifc, (u_char*)pkt->nb_buff + ETHHDR_BIAS))
+         mib->ifInNUcastPkts++;
+      else
+         mib->ifInUcastPkts++;
+
+      if(mib->ifAdminStatus == NI_DOWN)
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);  /* dump packet from downed interface */
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         mib->ifInDiscards++;
+         continue;      /* next packet */
+      }
+
+#ifdef NPDEBUG
+      if (*(pkt->nb_buff - ALIGN_TYPE) != 'M' ||
+          *(pkt->nb_buff + pkt->nb_blen) != 'M')
+      {
+         dtrap();
+         panic("pktdemux: corrupt pkt");
+      }
+#endif   /* NPDEBUG */
+
+#ifdef  LOSSY_IO
+      if(NDEBUG & LOSSY_RX)
+      {
+         if(myloss())  
+         {
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt);        /* punt packet */
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            in_lastloss = (int)(cticks & 0x07) - 4;  /* pseudo random reset */
+            continue;            /* act as if we sent OK */
+         }
+      }
+#endif   /* LOSSY_IO */
+
+      /* see if driver set pkt->nb_prot and pkt->type */
+      if((ifc->n_flags & NF_NBPROT) == 0)
+      {
+         /* Set pkt->type and pkt->nb_prot based based on media type.
+          * Some device drivers pass nb_plen as the total length of the
+          * packet, while others subtract the MAC header. The latter is
+          * probably the right thing to do, but because of this historic
+          * inconsistency we don't try to fix it here - the longer size
+          * turns out to be harmless since the IP layer fixes the size
+          * based on the IP header length field.
+          */
+         switch(ifc->n_mib->ifType)
+         {
+         case ETHERNET:
+            /* get pointer to ethernet header */
+            eth = (pkt->nb_buff + ETHHDR_BIAS);
+#ifdef IEEE_802_3
+            /* see if it's got snap baggage */
+            if (ET_TYPE_GET(eth) <= 0x0600)
+            {
+               struct snap_hdr *snap;
+               snap = (struct snap_hdr *)(pkt->nb_buff + ETHHDR_SIZE);
+               pkt->type = (unshort)(snap->type);
+               pkt->nb_prot = pkt->nb_buff + pkt->net->n_lnh;
+            }
+            else
+            {
+               pkt->type = htons((unshort)ET_TYPE_GET(eth));
+               pkt->nb_prot = pkt->nb_buff + ETHHDR_SIZE;
+            }
+#else
+            pkt->type = htons((unshort)ET_TYPE_GET(eth));
+            pkt->nb_prot = pkt->nb_buff + pkt->net->n_lnh;
+#endif   /* IEEE_802_3 */
+            break;
+#if defined(USE_PPP) || defined(USE_SLIP) || defined(PROTOCOL_LIBS)
+         case PPP:   /* PPP or SLIP over a UART */
+         case SLIP:
+            pkt->nb_prot = pkt->nb_buff + MaxLnh;
+            pkt->type = IPTP;    /* only type our PPP supports */
+            break;
+#endif  /* USE_PPP || USE_SLIP */
+#ifdef USE_PPPOE
+         case PPPOE:
+            /* do not change type yet, for PPPoE */
+            break;
+#endif   /* USE_PPPOE */
+         default:    /* driver bug? */
+            dprintf("pktdemux: bad Iface type %ld\n",ifc->n_mib->ifType);
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+            continue;
+         }
+      }
+
+      /* pkt->nb_prot and pkt->type are now set. pass pkt to upper layer */
+      switch(pkt->type)
+      {
+      case IPTP:     /* IP type */
+         LOCK_NET_RESOURCE(NET_RESID);
+#ifdef SHARED_IPADDRS
+         add_share_route(pkt);
+#endif /* SHARED_IPADDRS */
+#ifdef IP_V4
+         ip_rcv(pkt);
+#else
+            /* don't care, it's IPv4 */
+            LOCK_NET_RESOURCE(FREEQ_RESID);
+            pk_free(pkt);
+            UNLOCK_NET_RESOURCE(FREEQ_RESID);
+#endif
+		UNLOCK_NET_RESOURCE(NET_RESID);
+         break;
+#ifdef INCLUDE_ARP
+      case ARPTP:       /* ARP type */
+         LOCK_NET_RESOURCE(NET_RESID);
+         arprcv(pkt);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         break;
+#endif   /* INCLUDE_ARP */
+#ifdef USE_PPPOE
+      case  htons(0x8863):
+      case  htons(0x8864):
+         LOCK_NET_RESOURCE(NET_RESID);
+         poe_rcv(pkt);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         break;
+#endif   /* USE_PPPOE */
+#ifdef IP_V6
+      case  htons(0x86DD):
+         /* Each received v6 pkt goes thru here exactly once, so set the
+          * outer (first, and usually only) ipv6 header pointer. Tunneled headers
+          * may exist further into the packet.
+          */
+         pkt->ip6_hdr = (struct ipv6 *)pkt->nb_prot;
+         LOCK_NET_RESOURCE(NET_RESID);
+         ip6_rcv(pkt);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         break;
+#endif
+      default:
+#ifdef NPDEBUG
+         if (NDEBUG & UPCTRACE)
+            dprintf("pktdemux: bad pkt type 0x%04x\n", ntohs(pkt->type));
+#endif   /* NPDEBUG */
+         ifc->n_mib->ifInUnknownProtos++;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);           /* return to free buffer */
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         break;
+      }
+      continue;
+   }
+}
+
+
+/* FUNCTION: c_older()
+ *
+ * c_older(ct1, ct2) - return the older of two tick counts. Assumes 
+ * both were set set by "ctX = cticks;" or other refernce to cticks. 
+ * Also assumes the two times are within a few days of each other. 
+ *
+ * 
+ * PARAM1: u_long ct1
+ * PARAM2: u_long ct2
+ *
+ * RETURNS: the older of the two passed tick counts
+ */
+
+u_long
+c_older(u_long ct1, u_long ct2)
+{
+
+   if (!(cticks & 0x80000000) || /* cticks has not wrapped recently, or */
+       (ct1 <= cticks && ct2 <= cticks) || /* both are below cticks or */
+       (ct1 >= cticks && ct2 >= cticks))   /* both are above cticks */
+   {
+      if (ct1 < ct2)
+         return(ct1);      /* then smaller is oldest */
+      else 
+         return(ct2);
+   }
+
+   /* else one is less than cticks, and one is greater.
+   the larger value is then the oldest */
+   if (ct1 >= ct2)
+      return(ct1);
+   else
+      return(ct2);
+}
+
+
+
+/* FUNCTION: ip2mac()
+ *
+ * Takes as input an outgoing IP packet with no MAC info 
+ * and trys to send it on the right MAC layer. For serial links (PPP) 
+ * just sends it to the iface driver. 
+ * 
+ * 
+ * PARAM1: PACKET pkt
+ * PARAM2: ip_addr dest_ip
+ *
+ * RETURNS: Returns 0 if packet went to mac sender; ENP_SEND_PENDING if 
+ * awaiting arp reply; ENP_NO_ROUTE if iface is down, or SENDERR if other 
+ * error.
+ */
+
+int
+ip2mac(PACKET pkt,         /* the packet itself, all set but for dest MAC address */
+   ip_addr  dest_ip)    /* the IP host or gateway to get MAC addr for */
+{
+   IFMIB ifmib = pkt->net->n_mib;   /* mib info for this interface */
+
+#ifdef  LOSSY_IO
+   if(NDEBUG & LOSSY_TX)
+   {
+      if(myloss())
+      {		  
+		  LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);                 /* punt packet */
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         in_lastloss = (int)(cticks & 0x07) - 4;  /* pseudo random reset */
+         return 0;                     /* act as if we sent OK */
+      }
+   }
+#endif   /* LOSSY_IO */
+
+   /* Always punt if iface ifAdminStatus is DOWN. ifOperStatus may 
+    * be down too, but our packet may be the event required to bring 
+    * it up - so don't worry about ifOperStatus here.
+    */
+   if(ifmib->ifAdminStatus == NI_DOWN)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return(ENP_NO_ROUTE);
+   }
+
+#ifdef LINKED_PKTS
+   /* If packet gather is not supported by the driver, then collect the
+    * fragments into one big buffer. Caller should have checked that buffer
+    * is smaller than driver's MTU.
+    */
+   if (((pkt->net->n_flags & NF_GATHER) == 0) &&   /* no gather flag, and... */
+       (pkt->pk_next))                             /* ...packet is scattered. */
+   {
+      pkt = pk_gather(pkt, pkt->net->n_lnh);
+      if (!pkt)
+         return ENP_NOBUFFER;
+   }
+#endif   /* LINKED_PKTS */
+
+   /* some interfaces (ie SLIP) just get the raw IP frame - no ARP needed */
+   if ((pkt->net->n_lnh == 0) ||    /* no MAC header */
+       (ifmib->ifType == PPP) ||     /* or PPP or SLIP... */
+       (ifmib->ifType == SLIP))
+   {
+      ifmib->ifOutUcastPkts++;   /* maintain MIB counters */
+      ifmib->ifOutOctets += pkt->nb_plen;
+
+      /* send packet on media */
+      if (pkt->net->pkt_send) /* favor using packet send */
+         pkt->net->pkt_send(pkt);   /* pkt will be freed by MAC code */
+      else  /* no packet send; try raw send */
+      {
+         pkt->net->raw_send(pkt->net, pkt->nb_prot, pkt->nb_plen);
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      }
+      return(SUCCESS);
+   }
+
+   /* don't allow unicast sends if NIC iface has no IP address. This
+    * is to prevent DHCP clients from sending prior to assignment.
+    */
+   if (pkt->net->n_ipaddr == 0L)
+   {
+      if (pkt->fhost != 0xFFFFFFFF) /* check for broadcast packet */
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         return ENP_SENDERR;
+      }
+   }
+
+#ifdef INCLUDE_ARP   /* must be ethernet or token ring */
+   return(send_via_arp(pkt, dest_ip));
+#else
+   dtrap();    /* Bad option combination? */
+   return ENP_NO_IFACE; /* sent to unknown interface type */
+#endif   /* INCLUDE_ARP */
+}
+
+#ifdef  LOSSY_IO
+/* 
+ * FUNCTION myrand(void)
+ * returns: unsigned int, pseudo random integer between 0 and 255.
+ */
+
+unsigned int
+myrand(void)
+{
+	unsigned int ret;
+	int i;
+	union
+	{
+		unsigned long L;
+		unsigned char C[4];
+	} U;
+
+		U.L = myrandVal;		
+		U.L += U.L % myrandMods;
+		myrandVal = U.L;
+		for (i = 0, ret = 0; i < 4; i++)
+			ret += U.C[i];
+		ret &= 0xff;
+		myrandMods = ret % 256 + 128 * myrandMods;
+
+	return ret;
+}
+
+/* 
+ * FUNCTION myloss(void)
+ * returns: int, 1 occurs ~ (myrandNum / myrandDenom) of the time.
+ *               0 occurs ~ ( 1 - (myrandNum / myrandDenom)) of the time.
+ */
+
+int
+myloss(void)
+{
+	if (myrand() < (myrandNum * 255 ) / myrandDenom)
+	   return 1;
+
+	return 0;
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipport.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipport.c
new file mode 100644
index 0000000..4f727d6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipport.c
@@ -0,0 +1,127 @@
+/*
+ * FILENAME: ipport.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: prep_ifaces(), netexit(),
+ *
+ * PORTABLE: no
+ */
+
+/* Additional Copyrights: */
+
+/* Portions Copyright 1994 by NetPort Software  */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#ifdef MAC_LOOPBACK
+extern   int  prep_lb(int already_found);
+#endif
+
+int(*port_prep)(int already_found) = NULL;
+
+u_char so_evtmap;
+int (*so_evtmap_create) (struct socket *);
+int (*so_evtmap_delete) (struct socket *);
+
+
+/* FUNCTION: prep_ifaces()
+ * 
+ * prep-ifaces() - prepare ifaces this stack may want to use. This is 
+ * passed the nets[] index of the first interface to set up.
+ *
+ * PARAM1: int ifaces_found
+ *
+ * RETURNS:  It the net index of the last interface it set up. If no 
+ * interfaces were set up, the returned value is the same as the 
+ * passed value. 
+ */
+
+int
+prep_ifaces(int ifaces_found)
+{
+   if (port_prep)
+      ifaces_found = port_prep(ifaces_found);
+
+#ifdef MAC_LOOPBACK
+   ifaces_found = prep_lb(ifaces_found);
+#endif   /* MAC_LOOPBACK */
+
+   ifNumber = ifaces_found;   /* set global interface counter */
+
+   initmsg("prepped %u interface%s, initializing...\n", 
+      ifaces_found, ifaces_found==1?"":"s");
+
+   return ifaces_found;
+}
+
+
+/* the the ipport.h did not define an exit func then map it to standard exit() */
+
+#ifndef PORT_EXIT_FUNC
+#define  PORT_EXIT_FUNC(code) exit(code)
+#endif
+
+int      net_system_exit   =  FALSE;
+
+
+
+/* FUNCTION: netexit()
+ * 
+ * netexit() - this is called in place of system exit().
+ * It undoes things like the clock tick and MAC drivers
+ * hook which will hose the OS if we leave them installed. On some
+ * embedded systems it may not be required. 
+ *
+ * PARAM1: int err
+ *
+ * RETURNS: SHould not return
+ */
+
+void
+netexit(int err)      /* exit error level */
+{
+   net_system_exit = TRUE; /* set flag for shutting down */
+   ip_exit();  /* do the exit_hook()ed stuff */
+
+   PORT_EXIT_FUNC(err);    /* should not return! */
+   USE_ARG(err);
+}
+
+
+/* FUNCTION: evtmap_setup ()
+ *
+ * setup event map for (UDP and TCP) socket library's events (such as 
+ * those used by tcp_sleep () and tcp_wakeup ()).  These events either 
+ * map into operating system primitives such as events, or into task 
+ * suspend and task resume mechanisms.  In the former case, this 
+ * function sets up the function pointers that will be used (by code
+ * in the sockets library (socket.c and socket2.c)) to create and delete 
+ * the corresponding events.  In the latter case, the function pointers 
+ * are set to 0, indicating that they are not used.
+ *
+ * INPUT: None.
+ * OUTPUT: None
+ */
+ 
+void evtmap_setup (void)
+{
+#ifdef SOCK_MAP_EVENTS
+   so_evtmap = TRUE;
+   so_evtmap_create = evtmap_create;
+   so_evtmap_delete = evtmap_delete;
+#else
+   so_evtmap = FALSE;
+   so_evtmap_create = 0;
+   so_evtmap_delete = 0;
+#endif   /* SOCK_MAP_EVENTS */ 
+
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipraw.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipraw.c
new file mode 100644
index 0000000..06dbb7d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipraw.c
@@ -0,0 +1,348 @@
+/*
+ * FILENAME: ipraw.c
+ *
+ * Copyright 2002 InterNiche Technologies Inc. All rights reserved
+ *
+ * Support for "raw" access to IP.
+ *
+ * MODULE: IP
+ *
+ * ROUTINES: ip_raw_open(), ip_raw_close(), ip_raw_input(),
+ * ROUTINES: ip_raw_alloc(), ip_raw_free(), ip_raw_maxalloc()
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#ifdef IP_RAW
+
+/* IEP_ALLOC(), IEP_FREE() - default macros to support allocation
+ *                           of raw IP endpoints
+ *
+ * These macros provide a default allocator based on the InterNiche
+ * npalloc() and npfree() functions.  They may be overridden from
+ * the target ipport.h file.
+ */
+#ifndef IEP_ALLOC
+#define IEP_ALLOC(size) npalloc(size)
+#endif  /* IEP_ALLOC */
+#ifndef IEP_FREE
+#define IEP_FREE(p)     npfree(p)
+#endif  /* IEP_FREE */
+
+/* ipraw_eps: head of list of raw IP endpoints
+ */
+struct ipraw_ep * ipraw_eps = NULL;
+
+/* FUNCTION: ip_raw_open()
+ *
+ * Opens an endpoint for reception of raw IP datagrams.
+ *
+ * PARAM1: u_char prot; IN - the IP protocol ID for which
+ *                      datagrams are to be received, or 0
+ *                      to receive traffic for all IP 
+ *                      protocol IDs not otherwise handled
+ *                      by the stack.
+ * PARAM2: ip_addr laddr; IN - the local IP address for which
+ *                        datagrams are to be received, in 
+ *                        network order; or 0 to receive traffic
+ *                        directed to any IP address.
+ * PARAM3: ip_addr faddr; IN - the remote peer IP address from 
+ *                        which datagrams are to be received, in 
+ *                        network order; or 0 to receive traffic
+ *                        from any peer IP address.
+ * PARAM4: int (*handler)(PACKET, void *); IN - pointer to an
+ *                                         upcall function to be
+ *                                         called on receipt of
+ *                                         matching packets
+ * PARAM5: void * data; IN - opaque token to be passed to the 
+ *                      upcall function; may be used to identify 
+ *                      the endpoint to the upcall function
+ *
+ * RETURNS: a pointer to the allocated endpoint structure, or
+ *          NULL if no endpoint was allocated.
+ */
+struct ipraw_ep *
+ip_raw_open(u_char prot,
+            ip_addr laddr,
+            ip_addr faddr,
+            int (*handler)(PACKET, void *),
+            void * data)
+{
+   struct ipraw_ep * ep;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   /* allocate a structure for the endpoint */
+   ep = (struct ipraw_ep *)IEP_ALLOC(sizeof(struct ipraw_ep));
+   if (ep == NULL)
+   {
+#ifdef NPDEBUG
+      if (NDEBUG & INFOMSG)
+         dprintf("IP: Couldn't allocate ep storage.\n");
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ep;
+   }
+
+   /* fill it in with the caller's requested binding */
+   ep->ipr_laddr = laddr;
+   ep->ipr_faddr = faddr;
+   ep->ipr_prot = prot;
+   ep->ipr_rcv = handler;
+   ep->ipr_data = data;
+
+   /* link it into the list 
+    * (at the head, because that's simple and fast) 
+    */
+   ep->ipr_next = ipraw_eps;
+   ipraw_eps = ep;
+
+   /* and return the pointer to the endpoint */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return ep;
+}
+
+/* FUNCTION: ip_raw_close()
+ * 
+ * Closes an endpoint.
+ *
+ * PARAM1: struct ipraw_ep * ep; IN - pointer to endpoint
+ *                               that is to be closed
+ * RETURNS: void
+ */
+void
+ip_raw_close(struct ipraw_ep * ep)
+{
+   struct ipraw_ep * prev_ep;
+   struct ipraw_ep * curr_ep;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   /* search the list of endpoints for the one we're supposed to close */
+   for (prev_ep = NULL, curr_ep = ipraw_eps;
+        curr_ep != NULL;
+        curr_ep = curr_ep->ipr_next)
+   {
+      if (curr_ep == ep)
+         break;
+      prev_ep = curr_ep;
+   }
+
+   /* if we didn't find it, we can't close it, so just return */
+   if (curr_ep == NULL)
+   {
+#ifdef NPDEBUG
+      /* caller passed pointer to endpoint not in list 
+       * -- not fatal, but may be programming error
+       */
+      dtrap();
+#endif /* NPDEBUG */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return;
+   }
+
+   /* unlink it from the list */
+   if (prev_ep)
+      prev_ep = curr_ep->ipr_next;
+   else
+      ipraw_eps = curr_ep->ipr_next;
+
+   /* free its storage */
+   IEP_FREE(curr_ep);
+
+   /* and return */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+}
+
+/* FUNCTION: ip_raw_input()
+ *
+ * Handles upcalls for raw IP endpoints, calling the endpoints'
+ * upcall functions when a matching packet is received.
+ *
+ * PARAM1: PACKET p; IN - the received packet
+ *
+ * RETURNS: 0 if the received packet was accepted (and presumably
+ *          freed); else an error code indicating that the
+ *          received packet was not accepted/processed
+ */
+int
+ip_raw_input(PACKET p)
+{
+   struct ip * pip;              /* the internet header */
+   struct ipraw_ep * ep;
+   struct ipraw_ep * next_ep;
+   struct ipraw_ep * matched_ep = NULL;
+   int err;
+   int delivered;
+
+   /* start out expecting to not deliver the packet */
+   delivered = 0;
+
+   /* get a pointer to the received packet's IP header */
+   pip = (struct ip *)(p->nb_prot);
+
+   /* search the list of raw-IP endpoints for matches */
+   for (ep = ipraw_eps; ep != NULL; ep = next_ep)
+   {
+      /* keep track of next endpoint -- defense against upcall
+       * function closing its own endpoint
+       */
+      next_ep = ep->ipr_next;
+
+      /* if this packet doesn't match the endpoint's filters (IP
+       * protocol ID, locally-bound address, connected-peer address)
+       * then skip ahead to next endpoint
+       */
+      if (ep->ipr_prot && ep->ipr_prot != pip->ip_prot)
+         continue;
+      if (ep->ipr_laddr && ep->ipr_laddr != pip->ip_dest)
+         continue;
+      if (ep->ipr_faddr && ep->ipr_faddr != pip->ip_src)
+         continue;
+
+      /* if the endpoint has a receive upcall function, 
+       * keep track of the endpoint
+       */
+      if (ep->ipr_rcv != NULL)
+      {
+         /* if we're already keeping track of a previously matched 
+          * endpoint,
+          * copy the packet into a new buffer,
+          * and pass the new copy to the previously matched 
+          * endpoint's upcall function 
+          * before we forget the previous endpoint
+          */
+         if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL))
+         {
+            PACKET p2;
+
+            p2 = ip_copypkt(p);
+            if (p2)
+            {
+               UNLOCK_NET_RESOURCE(NET_RESID);
+               err = ((*matched_ep->ipr_rcv)(p2, matched_ep->ipr_data));
+               LOCK_NET_RESOURCE(NET_RESID);
+               if (err)
+               {
+                  LOCK_NET_RESOURCE(FREEQ_RESID);
+                  pk_free(p2);
+                  UNLOCK_NET_RESOURCE(FREEQ_RESID);
+               }
+               else
+                  delivered = 1;
+            }
+         }
+         matched_ep = ep;
+      }
+   }
+
+   /* if we matched an endpoint, 
+    * pass the packet to its upcall function
+    * otherwise, return ENP_PARAM to indicate that the
+    * packet was not processed and freed
+    */
+   if ((matched_ep != NULL) && (matched_ep->ipr_rcv != NULL))
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      err = ((*matched_ep->ipr_rcv)(p, matched_ep->ipr_data));
+      LOCK_NET_RESOURCE(NET_RESID);
+      if (err == 0)
+         delivered = 1;
+   }
+   else
+   {
+      err = ENP_PARAM;
+      ip_mib.ipUnknownProtos++;
+   }
+
+   if (!delivered)
+      ip_mib.ipInDelivers--;
+
+   return err;
+}
+
+/* FUNCTION: ip_raw_alloc()
+ *
+ * Allocates a packet buffer for a raw IP datagram
+ *
+ * PARAM1: int reqlen; IN- requested buffer length, in bytes (octets).
+ * PARAM2: int hdrincl; IN- flag indicating whether application expects
+ *                      to build its own IP header; if so the length
+ *                      of the IP header must be included in reqlen
+ *
+ * RETURNS: a pointer to a packet buffer, or NULL if no buffer could
+ *          be allocated.  The returned buffer's nb_prot is set to point 
+ *          to the first location where the application should start
+ *          writing: to where the IP header should be written if 
+ *          inclhdr is non-zero, or to just past the IP header if 
+ *          inclhdr is zero.
+ */
+
+PACKET
+ip_raw_alloc(int reqlen, int hdrincl)
+{
+   int len;
+   PACKET p;
+
+   len = (reqlen + 1) & ~1;
+   if (!hdrincl)
+      len += IPHSIZ;
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   p = pk_alloc(len + MaxLnh);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (p)
+   {
+      if (!hdrincl)
+      {
+         p->nb_prot += IPHSIZ;
+         p->nb_plen -= IPHSIZ;
+      }
+   }
+   return p;
+}
+
+/* FUNCTION: ip_raw_free()
+ * 
+ * Frees an allocated packet buffer
+ *
+ * PARAM1: PACKET p; IN- packet buffer to be freed
+ *
+ * RETURNS: void
+ */
+
+void
+ip_raw_free(PACKET p)
+{
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+}
+
+/* FUNCTION: ip_raw_maxalloc()
+ * 
+ * Returns the maximum supportable packet buffer allocation
+ *
+ * RETURNS: an integer whose value may be taken as a practical maximum
+ *          for 
+ */
+
+int
+ip_raw_maxalloc(int hdrincl)
+{
+   int len;
+
+   len = bigbufsiz - MaxLnh;
+   if (!hdrincl)
+      len -= IPHSIZ;
+   return len;
+}
+
+#endif /* IP_RAW */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/iproute.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/iproute.c
new file mode 100644
index 0000000..7346021
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/iproute.c
@@ -0,0 +1,725 @@
+/*
+ * FILENAME: iproute.c
+ *
+ * Copyright 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * 	This contains IP routing code. There are two complete sets of 
+ * functions: one for BTREE_ROUTES and the other for nonhashed.
+ * 
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: rt_lookup(), add_route(), del_route(), 
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+
+#ifdef IP_ROUTING    /* whole file goes away without this */
+
+#ifdef RIP_SUPPORT
+#include "../rip/rip.h"
+#endif
+
+RTMIB cachedRoute = NULL;        /* last route entry we used */
+
+u_char   rtp_priority[] =  {  /* route table entry priorities, by protocol */
+   /* FOO */            0x00, /* empty entry, lowest priority */
+   /* IPRP_OTHER   1 */ 0xF0,
+   /* IPRP_LOCAL   2 */ 0xFF, /* hand entered = higest priority */
+   /* IPRP_NETMGMT 3 */ 0xF0,
+   /* IPRP_ICMP    4 */ 0xCA,
+   /* IPRP_EGP     5 */ 0xA0,
+   /* IPRP_GGP     6 */ 0x80,
+   /* IPRP_HELLO   7 */ 0x80,
+   /* IPRP_RIP     8 */ 0xB0,
+};
+
+
+
+#ifndef BTREE_ROUTES
+
+/* FUNCTION: rt_lookup()
+ *
+ * Look up passed host in the routing table. If a full address match
+ * is found it is returned, else a net match is returned (if one is
+ * found). The caller can distinguish by testing rtp->ipRouteDest.
+ *
+ * PARAM1: ip_addr   host
+ *
+ * RETURNS: Returns a pointer to the table entry; NULL if no suitable
+ * entry was found.
+ */
+
+RTMIB
+rt_lookup(ip_addr host)
+{
+   RTMIB    rtp;
+   RTMIB    netmatch;
+   unsigned char max_bits_matched = 0;
+   unsigned char curr_bits_matched;
+   ip_addr  entry_mask;
+   unsigned long int bitcount_mask;
+   unsigned long int extracted_bit;
+
+   netmatch = NULL;
+
+   /* see if it's in the route table. */
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+   {
+      if (rtp->ipRouteNextHop == 0L)   /* skip over empty entries */
+         continue;
+#ifdef RIP_SUPPORT
+      /* skip RIP private entries */
+      if (rtp->ipRouteFlags & RIP_PRIVATE)
+         continue;
+#endif
+      entry_mask = rtp->ipRouteMask;
+      /* check to see if we have a match in the route table */
+      if ((rtp->ipRouteDest & entry_mask) == (host & entry_mask))
+      {
+         /* check to see if current match is better than the previous best
+          * by computing the number of bits that matched */
+         for (curr_bits_matched = 0, bitcount_mask = 0x80000000; bitcount_mask > 0; bitcount_mask >>= 1)
+         {
+            extracted_bit = (ntohl(entry_mask)) & bitcount_mask;
+            if (extracted_bit) ++curr_bits_matched;
+         }
+         if (curr_bits_matched > max_bits_matched)
+         {
+            /* save a pointer to the best match */
+            max_bits_matched = curr_bits_matched;
+            netmatch = rtp;
+            /* if all 32 bits match, stop searching the route table */
+            if (max_bits_matched == 32)
+               break;
+         }
+      }
+   }
+
+   if (netmatch)
+      netmatch->ipRouteAge = cticks;   /* timestamp entry we used */
+
+   return netmatch;
+}
+
+
+/* FUNCTION: add_route()
+
+ * add_route(dest, mask, nexthop, metric); - Make an entry in the 
+ * route table directing dest to nexthop. If route already exists, 
+ * update it.
+ *
+ * PARAM1: ip_addr   dest
+ * PARAM2: ip_addr   mask
+ * PARAM3: ip_addr   nexthop
+ * PARAM4: int    ifc
+ * PARAM5: int    prot
+ *
+ * RETURNS: Returns a pointer to the table entry; so caller can 
+ * process it further, (ie add metrics), Returns NULL on error.
+ *
+ */
+
+RTMIB
+add_route(
+   ip_addr  dest,       /* ultimate destination */
+   ip_addr  mask,       /* net mask, 0xFFFFFFFF if dest is host address */
+   ip_addr  nexthop,    /* where to forward to */
+   int      iface,      /* interface (net) for nexthop */
+   int      prot)       /* how we know it: icmp, table, etc */
+{
+   RTMIB rtp;           /* scratch route table entrry pointer */
+   RTMIB newrt;         /* best entry for new route */
+   struct net * ifp;    /* interface (net) for nexthop */
+
+   newrt = NULL;     /* may be replaced with empty or more expendable entry */
+
+					 
+					 
+   /* set the route interface pointer according to the index passed. This allows 
+    * the passed index to be used to access dynamic interfaces, which do not appear 
+    * in the nets[] array.
+    */
+   ifp = if_getbynum(iface);
+   if(!ifp)
+      return NULL;
+
+   if (rt_mib == NULL)
+      return NULL;
+
+   /* Don't add null masks or IP addresses - they give false positives on
+    * net matches and don't belong here anyway.
+    */
+   if((dest == 0) || (mask == 0))
+   {
+      dtrap();    /* bad configuration? */
+      dprintf("add_route: rejected null parm; dest: %lx, mask: %lx\n",
+	      htonl(dest), htonl(mask) );
+      return NULL;
+   }
+
+
+
+   /* if it's already in the route table, just update it. */
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+   {
+      if (rtp->ipRouteDest == dest) /* found existing entry for target */
+      {
+         rtp->ipRouteNextHop = nexthop;      /* fix entry */
+         rtp->ipRouteAge = cticks;           /* timestamp it */
+         /* set the rfc1213 1-based SNMP-ish interface index */
+         rtp->ipRouteIfIndex = (long)(iface) + 1;
+         rtp->ipRouteProto = prot;           /* icmp, or whatever */
+         rtp->ipRouteMask = mask;
+         rtp->ifp = ifp;
+         return(rtp);   /* just update and exit */
+      }
+      /* if we didn't find empty slot yet, look for good slot to recycle */
+      if (!newrt || (newrt->ipRouteProto != 0))
+      {
+         if (!rtp->ipRouteNextHop)  /* found empty slot for use */
+         {
+            newrt = rtp;   /* record empty route for use */
+            newrt->ipRouteProto = 0;
+            continue;
+         }
+         /* else see if the new route has higher priority than this slot: */
+         if (rtp_priority[prot] >= rtp_priority[rtp->ipRouteProto])
+         {
+            if (!newrt)
+            {
+               newrt = rtp;
+               continue;
+            }
+
+            /* see if rtp is less important then newrtp */
+            if (rtp_priority[rtp->ipRouteProto] < 
+                rtp_priority[newrt->ipRouteProto])
+            {
+               newrt = rtp;   /* save lower priority entry for recycle */
+            }
+            else if(rtp_priority[rtp->ipRouteProto] == 
+                rtp_priority[newrt->ipRouteProto])
+            {
+               /* if equal priority, keep the older entry for deletion */
+               if (c_older(rtp->ipRouteAge, newrt->ipRouteAge) == rtp->ipRouteAge)
+                  newrt = rtp;   /* got an older one */
+            }
+         }
+      }
+   }
+
+   /* fall to here if not in table: create a new route */
+   if (newrt)  /* did we find an empty or lower priority route entry? */
+      rtp = newrt;   /* create new entry in lowest priority slot */
+   else  /* all slots have higher priority, new entry looses */
+      return NULL;
+
+   /* set default value in new route entry, caller can modiy further. */
+   rtp->ifp = ifp;
+   rtp->ipRouteDest = dest;
+   rtp->ipRouteIfIndex = (long)(if_netnumber(ifp)) + 1; /* set interface number */
+   rtp->ipRouteMetric1 = ip_mib.ipDefaultTTL;
+   rtp->ipRouteMetric2 = -1;
+   rtp->ipRouteMetric3 = -1;
+   rtp->ipRouteMetric4 = -1;
+   rtp->ipRouteNextHop = nexthop;
+   rtp->ipRouteProto = prot;                 /* icmp, or whatever */
+
+   if ((dest & mask) == (nexthop & mask))
+      rtp->ipRouteType = IPRT_DIRECT;
+   else
+      rtp->ipRouteType = IPRT_INDIRECT;
+
+   rtp->ipRouteAge = cticks;        /* timestamp it */
+   rtp->ipRouteMask = mask;
+   rtp->ipRouteMetric5 = -1;
+   return(rtp);
+}
+
+/* FUNCTION: del_route()
+ *
+ * del_route() - delete entries from the routing table. Mask of 
+ * 0xFFFFFFFF will cause only exact dest address matches to be 
+ * deleted. Mask of 0L will delete all routes for passed interface. 
+ * iface is net index, else -1 is wildcard interface. 
+ *
+ * 
+ * PARAM1: ip_addr dest
+ * PARAM2: ip_addr mask
+ * PARAM3: int iface
+ *
+ * RETURNS: Returns number of route table entries deleted. 
+ */
+
+int
+del_route(ip_addr dest, ip_addr mask, int iface)
+{
+   RTMIB rtp;
+   int   retval   =  0;
+   struct net * ifp;
+
+   /* set the route interface pointer according to the index passed. This allows 
+    * the passed index to be used to access dynamic interfaces, which do not appear 
+    * in the nets[] array.
+    */
+   if(iface == -1)
+      ifp = NULL;    /* wildcard */
+   else
+      ifp = if_getbynum(iface);
+
+   if (rt_mib == NULL)     /* Make sure we're up */
+      return 0;
+
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+   {
+      if (!rtp->ipRouteNextHop)  /* empty slot */
+         continue;
+      if(ifp != NULL && ifp != rtp->ifp)
+         continue;   /* interface didn't match */
+      if ((rtp->ipRouteDest & mask) == (dest & mask))
+      {
+         MEMSET(rtp, 0, sizeof(*rtp)); /* clear entry */
+         retval++;
+      }
+      if (cachedRoute == rtp) /* clear cache if it's being deleted */
+         cachedRoute = NULL;
+   }
+   return retval;
+}
+
+
+#else /**** end of non BTREE_ROUTES versions ****/
+
+int   rtbtree_clean = 20;    /* number of seconds between cleanups */
+int   rtbtree_last = 0;      /* seconds since last cleanup */
+RTMIB btreeRoot = (RTMIB)0;  /* BTree parent pointer. */
+
+/* array of all masks which are used in the routing table. This exisist to speed 
+ * searchs - we only have to search for masks we know are in the tree somewhere.
+ * first entry is always 0xFFFFFFFF,
+ */
+
+static ip_addr rt_masks[32] = { 0xFFFFFFFF } ;
+
+
+/* FUNCTION: rtp_fillin()
+ *
+ * Fill in the passed RTP structure from the other parameters.
+ *
+ * PARAM1: RTMIB    rtp,      route entry to fill in 
+ * PARAM2: ip_addr  dest,     ultimate destination 
+ * PARAM3: ip_addr  mask,     net mask, 0xFFFFFFFF if dest is host address
+ * PARAM4: ip_addr  nexthop,  where to forward to
+ * PARAM5: struct net * ifp   interface (net) for nexthop
+ * PARAM : int      prot      how we know it: icmp, table, etc
+ *
+ * RETURNS: NA
+ */
+
+static void
+rtp_fillin(RTMIB rtp, ip_addr  dest, ip_addr  mask,
+   ip_addr  nexthop, struct net * ifp, int prot)
+{
+   rtp->ipRouteDest = dest;            /* fill in entry */
+   rtp->ipRouteNextHop = nexthop;
+   rtp->ipRouteAge = cticks;           /* timestamp it */
+   rtp->ipRouteProto = prot;           /* icmp, or whatever */
+   rtp->ipRouteMask = mask;
+   rtp->ifp = ifp;
+
+   /* set the rfc1213 1-based SNMP-ish interface index */
+   rtp->ipRouteIfIndex = (long)(if_netnumber(ifp)) + 1;
+
+   if ((dest & mask) == (nexthop & mask))
+      rtp->ipRouteType = IPRT_DIRECT;
+   else
+      rtp->ipRouteType = IPRT_INDIRECT;
+
+   rtp->ipRouteMetric1 = ip_mib.ipDefaultTTL;
+   rtp->ipRouteMetric2 = -1;
+   rtp->ipRouteMetric3 = -1;
+   rtp->ipRouteMetric4 = -1;
+   rtp->ipRouteMetric5 = -1;
+}
+
+
+/* FUNCTION: rttmo()
+ *
+ * Helper (callback) function. This is passed to avlremove() by rtbtree_tmo()
+ * and is called back once for every route table entry.
+ *
+ * PARAM1: struct RtMib * n - The route table entry to examine.
+ * PARAM2: long param       - Unused
+ * PARAM3: int depth        - Unused
+ *
+ * RETURNS: NA
+ */
+
+static u_long rtb_delctick;
+
+static void
+rttmo(struct avl_node * node, long param, int depth)
+{
+   RTMIB rt = (RTMIB)node;
+
+   /* only time out the routes with type "other". Entries set by RIP,
+    * SNMP, users, etc., should have their own mechanisms for cleanup.
+    */
+   if(rt->ipRouteProto != IPRP_OTHER)
+      return;
+
+   if (!btreeRoot)
+	   return;
+
+   /* Check timestamp to see when this was last used */
+   if((rt->ipRouteAge < rtb_delctick) ||
+      (rt->ipRouteAge > cticks))     /* catch cticks wrapping */
+   {
+      ip_addr key;      /* for pass to avlremove() */
+
+       /* If the cached route is the one being deleted then clear the cache */
+      if (rt == cachedRoute)
+         cachedRoute = NULL;
+    
+	  ((RTMIB)node)->ipRouteNextHop = 0; /* clear route */
+      key = htonl(((RTMIB)node)->ipRouteDest);     /* pass key in machine endian */
+	  avlremove((struct avl_node **)&btreeRoot, (void*)&key);
+   }
+   USE_ARG(depth);
+   USE_ARG(param);
+}
+
+/* FUNCTION: rtbtree_tmo()
+ *
+ * Called once a second from misclib\timeouts.c to clear out any stale route
+ * table entries. Doing this every second is usually overkill, so there is
+ * a user settable throttle (rtbtree_clean) for the number of seconds
+ * between cleanups.
+ *
+ * PARAM1: NA
+ *
+ * RETURNS: NA
+ */
+
+void
+rtbtree_tmo()
+{
+   if(rtbtree_last++ < rtbtree_clean)
+      return;
+
+   if (!btreeRoot)
+	   return;
+
+   rtbtree_last = 0;
+   rtb_delctick = cticks - (rtbtree_clean * TPS);
+
+   avldepthfirst((struct avl_node *)btreeRoot, rttmo, 0, 0);
+}
+
+RTMIB rt_lookup_masked(ip_addr host, ip_addr mask);  /* predecl */
+
+/* The next few functions are identical to the ones of the same names
+ * defined in the non btree code above. Their descriptions are not
+ * duplicated hereunder to avoid confusion.
+ */
+
+RTMIB
+rt_lookup(ip_addr host)
+{
+   int      i;    /* mask array index */
+   ip_addr  mask;
+   RTMIB    rtp;
+
+   for(i = 0; i < 32; i++)
+   {
+      if(rt_masks[i] == 0)    /* no more masks? */
+         return NULL;
+      mask = rt_masks[i];
+      rtp = rt_lookup_masked(host & mask, mask);
+      if(rtp)
+         return rtp;
+   }
+   return NULL;
+}
+
+RTMIB
+rt_lookup_masked(ip_addr host, ip_addr mask)
+{
+   RTMIB    rtp;
+   ip_addr  hostval;       /* local endian value of host */
+   ip_addr  tmp;
+
+   /* convert search IP address to local endian so the "<" and ">"
+    * tests work corrently 
+    */
+   hostval = htonl(host);     
+
+   rtp = btreeRoot;       /* start at parent of tree */
+
+   /* binary tree search loop. This should be FAST. */
+   while(rtp)
+   {
+      tmp = htonl(rtp->ipRouteDest);
+#ifdef RIP_SUPPORT 
+      /* skip RIP private entries */
+      if ( rtp->ipRouteFlags & RIP_PRIVATE )
+         goto nextroute;
+#endif
+
+      /* if exact match of both mask and entry then we are done */
+      if((mask == rtp->ipRouteMask) && (hostval == tmp))
+      {
+         rtp->ipRouteAge = cticks;   /* timestamp entry we used */
+         return rtp;    /* return route entry or NULL */
+      }
+
+
+#ifdef RIP_SUPPORT
+nextroute:
+#endif
+      /* search the correct branch of the binary tree */
+      if(hostval < tmp)
+         rtp = (RTMIB)rtp->left;
+      else                    /* hostval > tmp */
+         rtp = (RTMIB)rtp->right;
+   }
+
+   return NULL;      /* didn't find a match */
+}
+
+/* FUNCTION: rt_lookup_unmasked()
+ *
+ * Look up passed host in the routing table, using exact host match
+ *
+ * PARAM1: ip_addr   host
+ *
+ * RETURNS: Returns a pointer to the table entry; NULL if no 
+ * entry was found.
+ */
+
+RTMIB
+rt_lookup_unmasked(ip_addr host)
+{
+   RTMIB    rtp;
+   ip_addr  hostval;       /* local endian value of host */
+   ip_addr  tmp;
+
+   /* convert search IP address to local endian so the "<" and ">"
+    * tests work corrently 
+    */
+   hostval = htonl(host);     
+
+   rtp = btreeRoot;       /* start at parent of tree */
+
+   /* binary tree search loop. This should be FAST. */
+   while(rtp)
+   {
+      tmp = htonl(rtp->ipRouteDest);
+
+      /* if exact match of entry then we are done */
+      if(hostval == tmp)
+      {
+         rtp->ipRouteAge = cticks;   /* timestamp entry we used */
+         return rtp;    /* return route entry or NULL */
+      }
+
+      /* search the correct branch of the binary tree */
+      if(hostval < tmp)
+         rtp = (RTMIB)rtp->left;
+      else                    /* hostval > tmp */
+         rtp = (RTMIB)rtp->right;
+   }
+
+   return NULL;      /* didn't find a match */
+}
+
+RTMIB
+add_route(
+   ip_addr  dest,       /* ultimate destination */
+   ip_addr  mask,       /* net mask, 0xFFFFFFFF if dest is host address */
+   ip_addr  nexthop,    /* where to forward to */
+   int      iface,      /* interface (net) for nexthop */
+   int      prot)       /* how we know it: icmp, table, etc */
+{
+   RTMIB rtp;           /* scratch route table entry pointer */
+   struct net * ifp;    /* interface (net) for nexthop */
+   int      i;          /* masks array index */
+
+   ifp = if_getbynum(iface);
+   if(!ifp)
+      return NULL;
+
+   if (!rt_mib)
+	   return NULL;
+
+   /* Don't add null masks or IP addresses - they give false positives on
+    * net matches and don't belong here anyway.
+    */
+   if((dest == 0) || (mask == 0))
+   {
+      dtrap();    /* bad configuration? */
+      return NULL;
+   }
+
+   /* Check that host portion of dest and host portion of mask don't overlap */
+   if((~mask & dest) != 0)
+   {
+      dtrap();    /* programming error or bad user input */
+      return NULL;
+   }
+
+   /* add mask to array */
+   for(i = 0; i < 32; i++)
+   {
+      if(rt_masks[i] == mask)    /* Mask already in table? */
+         break;                  /* don't add it again */
+
+      /* This array is ordered, highest value first. See if new mask goes here */
+      if(rt_masks[i] < mask)     /* mask gets inserted here */
+      {
+         int j;      /* secondary index */
+         /* move subsequent masks back one slot */
+         for(j = 31; j > i; j--)
+            rt_masks[j] = rt_masks[j - 1];
+         rt_masks[i] = mask;     /* put new mask in it's slot */
+         break;                  /* done inserting mask */
+      }
+   }   
+
+   /* this is just to find a particular entry, 
+    * so exact mask.
+	*/
+   rtp = rt_lookup_unmasked(dest); 
+   if(rtp && (rtp->ipRouteDest == dest))  /* found existing entry */
+   {
+      /* just update and exit */
+      rtp_fillin(rtp, dest, mask, nexthop, ifp, prot);
+      return(rtp);
+   }
+
+   /* fall to here if no entry found. Make new route entry */
+   /* find an empty entry */
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+      if (!rtp->ipRouteNextHop)  /* empty slot */
+         break;
+
+   if (rtp >= (rt_mib + ipRoutes))
+	   return NULL;
+
+   /* set default values in new route entry */
+   rtp_fillin(rtp, dest, mask, nexthop, ifp, prot);
+
+#ifdef RIP_TRIGGERED_UPDATES
+   rtp->ipRouteFlags |= RIP_TRIGGER ; 
+   rtp->ipRouteFlags |= RIP_VALID ;
+#endif   /* RIP_TRIGGERED_UPDATES */
+
+   /* add route to tree. */
+  if(avlinsert((struct avl_node **)&btreeRoot, (struct avl_node *)rtp) == BT_ERROR)
+  {
+	dprintf("*** add_route - avlinsert, BT_ERROR\n");
+	dtrap();
+	return NULL;
+  }
+
+   return(rtp);
+}
+
+static int rtdeletions;    /* count routes deleted for wildcard */
+
+static void
+rtdel(struct avl_node * node, long param, int depth)
+{
+   struct RtMib * n = (struct RtMib *)node;
+   ip_addr key;
+
+   if (!btreeRoot)
+	   return;
+
+   if(n->ifp == (struct net *)param)
+   {
+      /* If the cached route is the one being deleted then clear the cache */
+      if (n == cachedRoute)
+         cachedRoute = NULL;
+      /* delete the entry n. */
+	  n->ipRouteNextHop = 0; /* clear route */
+      key = htonl(n->ipRouteDest);     /* pass key in machine endian */
+      avlremove((struct avl_node **)&btreeRoot, (void*)&key);
+      rtdeletions++;
+   }
+   USE_ARG(depth);
+}
+  
+int
+del_route(ip_addr dest, ip_addr mask, int iface)
+{
+   struct net * ifp;
+   ip_addr key;
+
+   if(!rt_mib)    /* no route yet? */
+      return 0;
+
+   /* set the route interface pointer according to the index passed. This allows 
+    * the passed index to be used to access dynamic interfaces, which do not appear 
+    * in the nets[] array.
+    */
+   if(iface == -1)
+      ifp = NULL;    /* wildcard */
+   else
+      ifp = if_getbynum(iface);
+
+   /* If an iface was specified and a mask was given then just delete
+    * the passed IP address entry and return.
+    */
+   if(mask == 0xFFFFFFFF)
+   {
+      struct avl_node * delnode;    /* node to delete */
+
+       /* If the cached route is the one being deleted then clear the cache */
+      if (cachedRoute->ipRouteDest == dest)
+         cachedRoute = NULL;
+
+      /* call btree route to remove the actual entry */
+      delnode = avlv4_access((struct avl_node *)btreeRoot, (ntohl(dest)));
+      if(!delnode)
+      {
+         dtrap();    /* node not in tree??? */
+         return 0;   /* deleted 0 entries */
+      }
+	  ((RTMIB)delnode)->ipRouteNextHop = 0; /* clear route */
+      key = htonl((((RTMIB)delnode)->ipRouteDest));
+      avlremove((struct avl_node **)&btreeRoot, &key);
+      return 1;      /* done, deleted one route entry */
+   }
+
+   /* fall to here if we are doing a wildcard delete. To do this we
+    * traverse the whole tree, using a callback function to delete any
+    * entry with the passed net. This is not really reentrant since
+    * we use a static variable to count deletions, but the only ill
+    * effect of reentering will be a bogus return count..
+    */
+
+   if(ifp == NULL)
+   {
+      dtrap();    /* illegal parameter combo */
+      return ENP_PARAM;
+   }
+
+   rtdeletions = 0;     /* init number of routes deleted */
+   avldepthfirst((struct avl_node *)btreeRoot, rtdel, (long)ifp, 0);
+   return(rtdeletions);
+}
+
+#endif /* BTREE_ROUTES or not */
+
+#endif   /* IP_ROUTING  whole file */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipstart.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipstart.c
new file mode 100644
index 0000000..d54013f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/ipstart.c
@@ -0,0 +1,311 @@
+/*
+ * FILENAME: ipstart.c
+ *
+ * Copyright 1996- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Network startup file. The idea is the main() routine (or 
+ * whatever) application calls ip_startup(), which does all the low
+ * level work of finding interfaces, starting IP, Arp, SNMP, etc
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: ip_startup(), exit_hook(), ip_exit(), 
+ * ROUTINES: if_netnumber(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990 - 1994 by NetPort Software */
+/* Portions Copyright 1986 by Carnegie Mellon */
+
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+
+#ifdef INCLUDE_ARP
+#include "arp.h"
+#endif
+
+#ifdef IP_MULTICAST
+#include "../ipmc/igmp.h"
+#endif
+
+#ifdef NATRT
+extern   int nat_init(void);
+#endif
+
+#if (defined(USE_PPP) && defined(LB_XOVER))
+extern   int ppp_lb_add_routes(void);
+#endif 
+
+
+#ifndef MULTI_HOMED     /* if single interface, set up everything here */
+/* if your compiler complains about the next line, it means 
+your ipport.h defined MAXNETS != 1 without defining MULTI_HOMED */
+#if (MAXNETS != 1)
+#error MULTI_HOMED must be defined if "MAXNETS" is greater than 1
+#endif   /* MAXNETS != 1 */
+#endif   /* MULTI_HOMED */
+
+/* static memory for interface structs and interface mib data */
+struct net  netstatic[STATIC_NETS];  /* actual net structs */
+
+/* pointer array to all nets, to support older code */
+struct net *   nets[MAXNETS];
+
+#ifdef IP_MULTICAST
+extern   ip_addr  igmp_all_hosts_group;
+#endif
+
+
+#ifdef INCLUDE_TCP
+extern   int tcpinit(void);
+extern  void evtmap_setup(void);
+#endif
+
+#ifdef USE_IPFILTER
+int  ipf_init(void);
+void ipf_cleanup(void);
+#endif
+
+unsigned ifNumber = 0;        /* number of net interfaces */
+
+char * ipmcfail_str = "unable to initialize IP Multicast";
+
+
+/* FUNCTION: ip_startup()
+ *
+ * startup() - Start up a customized IP stack as defined by ipport.h 
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: returns NULL if OK, or text of an error message 
+ */
+
+char *   
+ip_startup()
+{
+   int   e; /* error holder */
+   int   i;
+
+   /* thread nets[] and attach mib data to nets[] arrays */
+   for (i = 0; i < STATIC_NETS; i++)
+   {
+      nets[i] = &netstatic[i];   /* set up array of pointers */
+      nets[i]->n_mib = &nets[i]->mib;   /* set mib pointer */
+
+      /* add static iface to end of nets list */
+      putq(&netlist, nets[i]);
+   }
+
+   /* call port routine to locate and init network interfaces. */
+   ifNumber = (unsigned)prep_ifaces(ifNumber);
+
+   if (ifNumber < 1)    /* no static interfaces? */
+   {
+#ifdef DYNAMIC_IFACES
+      /* print a debug message and hope user knows what he's doing */
+      dprintf("unable to find any working interfaces");
+#else /* static ifaces only */
+      /* no static and no dynamic interfaces is probably a bug... */
+      return("unable to find any working interfaces");
+#endif   /* DYNAMIC_IFACES */
+   }
+
+   /* throw away any unused static nets */
+   for (i = ifNumber; i < STATIC_NETS; i++)
+   {
+      qdel(&netlist, (qp)nets[i]);  /* remove from queue */
+      nets[i] = NULL;               /* remove from array */
+   }
+
+
+   /* The sequence of events when initing the net & interface systems 
+    * is very important. Be very carefull about altering the order of 
+    * the following statements. 
+    */
+   /* once these are done, we should call ip_exit before quiting IP */
+   clock_init();           /* start clock system */
+   exit_hook(clock_c);
+
+   e = Netinit();    /* start net interface(s) */
+   if (e)
+   {
+      return("unable to initialize net");
+   }
+
+#ifdef INCLUDE_ARP
+   e = etainit();          /* startup ARP layer */
+   if (e)
+   {
+      ip_exit();
+      return("unable to initialize arp");
+   }
+#endif
+
+#ifdef IP_V4
+   e = ip_init();       /* start up IP layer */
+   if (e)
+   {
+      ip_exit();
+      return("unable to initialize IP");
+   }
+#endif /* IP_V4 */
+
+#ifdef IP_V6
+   e = ip6_init();       /* start up IPv6 */
+   if (e)
+   {
+      ip_exit();
+      return("unable to initialize IPv6");
+   }
+#endif /* IP_V6 */
+
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   /* Join the All hosts group on every interface that IP multicast is
+    * supported
+    */
+   e = igmp_init();         /* Initialize igmp */
+   if (e)
+   {
+      ip_exit();
+      return(ipmcfail_str);
+   }
+
+   for (i = 0; i < (int)ifNumber; i++)
+   {
+      if (nets[i]->n_mcastlist != NULL)
+         if ((in_addmulti(&igmp_all_hosts_group, nets[i], 4) == NULL))
+      {
+         ip_exit();
+         return(ipmcfail_str);
+      }
+   }
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */   
+
+#ifdef INCLUDE_TCP
+   e = tcpinit();
+   if (e)
+   {
+      ip_exit();
+      return("unable to initialize TCP");
+   }
+   
+   /* setup event map for (UDP and TCP) socket library's events (such as 
+    * those used by tcp_sleep () and tcp_wakeup ()).  These events either 
+    * map into operating system primitives such as events or semaphores, 
+    * or into task suspend and task resume mechanisms.
+    */
+   evtmap_setup ();
+#endif   /* INCLUDE_TCP */
+
+#ifdef NATRT
+   nat_init();
+#endif   /* NATRT */
+
+#if (defined(USE_PPP) && defined(LB_XOVER))
+   ppp_lb_add_routes();
+#endif   /* USE_PPP */
+
+#ifdef USE_IPFILTER
+   e = ipf_init();
+   if (e)
+      return("unable to initialize IP Filter table");
+   else
+      exit_hook(ipf_cleanup);
+#endif
+
+   return(NULL);     /* we got through with no errors */
+}
+
+
+#define  NUMCLOSERS  15
+static void (*closers[NUMCLOSERS])(void);
+static int nclosers = 0;
+
+/* FUNCTION: exit_hook()
+ *
+ * This is called to add a routine to a list of callbacks which
+ * will be called if the net is gracefully shut down. Sort of like
+ * "atexit()", but works on C system which don't support atecit()
+ *
+ * PARAM1: void (*func
+ *
+ * RETURNS: 
+ */
+
+void
+exit_hook(void (*func)(void))
+{
+   if (nclosers >= (NUMCLOSERS-1))
+      panic("exit_hook");
+
+   closers[++nclosers] = func;
+}
+
+
+/* FUNCTION: ip_exit()
+ *
+ * ip_exit() - undo net hooks as part of shutting down stack.
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+
+void
+ip_exit()
+{
+   int   n;
+
+   for (n=nclosers; n; n--)
+   {
+#ifdef NPDEBUG
+      dprintf("ip_exit: calling func %p\n", closers[n]);
+#endif
+      if(closers[n])
+      {
+         (*closers[n])();
+         closers[n] = NULL;
+      }
+   }
+}
+
+
+
+/* FUNCTION: if_netnumber()
+ *
+ * Get the index given a particular NET pointer.
+ * For static nets this will be and index into nets, however dynamic
+ * nets will NOT have a nets entry. For these, the index is the
+ * current position in the interfaces queue "netlist".
+ * 
+ * PARAM1: NET pointer
+ *
+ * RETURNS: net index for passed net pointer
+ */
+
+int
+if_netnumber(NET nptr)
+{
+   unsigned i;
+   NET ifp;
+
+   for(ifp = (NET)(netlist.q_head), i = 0; ifp; ifp = ifp->n_next, i++)
+   {
+      if(ifp == nptr)
+        return (int)i;
+   }
+
+   panic("bad net ptr");
+   return 0;
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/pmtu.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/pmtu.c
new file mode 100644
index 0000000..82ff157
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/pmtu.c
@@ -0,0 +1,407 @@
+/*
+ * FILENAME: pmtu.c
+ *
+ * Copyright 2001 InterNiche Technologies Inc.  All rights reserved.
+ *
+ * Path MTU cache supporting functions
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: pmtucache_init(), pmtucache_exit(), pmtu_firstguess(),
+ * ROUTINES: pmtu_nextguess(), pmtucache_set(), pmtucache_get(),
+ * ROUTINES: pmtu_stats()
+ *
+ * PORTABLE: yes
+ *
+ */
+
+#include "ipport.h"
+
+#ifdef  IP_PMTU
+
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "pmtu.h"
+
+/*
+ * IP_PMTU_MAXCACHE: maximum number of Path MTU cache entries
+ * 
+ * This macro is used to set the initial/default limit on the number
+ * of Path MTU cache entries retained by the stack.  It is intended to
+ * be overrideable from ipport.h.
+ */
+#ifndef IP_PMTU_MAXCACHE
+#define IP_PMTU_MAXCACHE      4
+#endif
+
+/*
+ * pmtu_maxcache: maximum number of Path MTU cache entries
+ *
+ * This global contains the limit on the number of Path MTU cache 
+ * entries retained by the stack.  It is intended to be set from 
+ * the IP_PMTU_MAXCACHE macro (so can be set by ipport.h) or
+ * overridden by the target's startup code *before startup*
+ * (i.e. before pmtucache_init() is called by ip_init()).
+ */
+int pmtu_maxcache = IP_PMTU_MAXCACHE;
+
+/*
+ * pmtucache: the Path MTU cache
+ */
+struct pmtucacheent * pmtucache = NULL;
+
+/*
+ * pmtucache_mru: ptr to the most-recently-used cached entry
+ */
+struct pmtucacheent * pmtucache_mru = NULL;
+
+/*
+ * IP_PMTU_TIMEOUT: time (in seconds) that a cached entry can remain
+ * without an update before it is invalidated
+ * 
+ * This macro is used to set the the time limit after which a cached
+ * Path MTU value will be re-initialized to force re-discovery.  A
+ * value of 0 turns off this function (i.e. cached Path MTU values
+ * will be able to hang around forever).  It is intended to be
+ * overrideable from ipport.h.
+ */
+#ifndef IP_PMTU_TIMEOUT
+#define IP_PMTU_TIMEOUT       3600
+#endif
+
+/*
+ * pmtu_timeout: time (in seconds) that a cached entry can remain
+ * without an update before it is invalidated
+ *
+ * This global contains the time limit after which a cached Path MTU 
+ * value will be re-initialized to force re-discovery.  A value of 
+ * 0 turns off this function (i.e. cached Path MTU values will be 
+ * able to hang around forever).  It is intended to be set from 
+ * the IP_PMTU_TIMEOUT macro (so can be set by ipport.h) or
+ * overridden by the target's startup code, preferably before startup
+ * (i.e. before pmtucache_init() is called by ip_init()).
+ */
+u_long pmtu_timeout = IP_PMTU_TIMEOUT;
+
+/*
+ * IP_PMTU_LLIMIT: lower limit for Path MTU guesses
+ * 
+ * This macro is used to set a lower limit below which pmtu_nextguess()
+ * will not make lower guesses for the path MTU estimate.  It is 
+ * intended to be overrideable from ipport.h.
+ */
+#ifndef IP_PMTU_LLIMIT
+#define IP_PMTU_LLIMIT        256
+#endif
+
+/*
+ * pmtu_llimit: lower limit for Path MTU guesses
+ *
+ * This global contains the lower limit below which pmtu_nextguess()
+ * will not make lower guesses for the path MTU estimate.  It is
+ * intended to be set from the IP_PMTU_LLIMIT macro (so can be set by
+ * ipport.h) or overridden by the target's startup code, preferably
+ * before startup (i.e. before pmtucache_init() is called by
+ * ip_init()).  
+ */
+unsigned pmtu_llimit = IP_PMTU_LLIMIT;
+
+/*
+ * PMTU_EXPIRED() - macro to determine if a timestamp has expired
+ *
+ * This is implemented as a macro to inline it yet keep the 
+ * implementation consistent across uses.
+ */
+#ifndef PMTU_EXPIRED
+#define PMTU_EXPIRED(timestamp) (cticks > (timestamp) + pmtu_timeout * TPS)
+#endif  /* PMTU_EXPIRED */
+
+/*
+ * FUNCTION: pmtucache_init()
+ *
+ * Initializes the path MTU cache.  Memory is allocated for the path
+ * MTU cache and all cache entries are marked as unused.  pmtucache_exit()
+ * is installed as an exit hook function to free the cache when the stack
+ * terminates.
+ *
+ * RETURNS: SUCCESS (0) if the path MTU cache was successfully
+ *          initialized; ENP_NOMEM if the memory could not be 
+ *          allocated.
+ */
+int
+pmtucache_init(void)
+{
+   int i;
+
+   pmtucache = (struct pmtucacheent *) 
+      PMTU_ALLOC(sizeof(struct pmtucacheent) * pmtu_maxcache);
+
+   if (pmtucache == NULL)
+      return ENP_NOMEM;
+
+   for (i = 0; i < pmtu_maxcache; i++)
+      MEMSET(&pmtucache[i], 0, sizeof(struct pmtucacheent));
+
+   pmtucache_mru = NULL;
+
+   exit_hook(&pmtucache_exit);
+
+   return 0;
+}
+
+/*
+ * FUNCTION: pmtucache_exit()
+ *
+ * Frees resources allocated for the path MTU cache in preparation
+ * for the termination of the stack. 
+ */
+void
+pmtucache_exit(void)
+{
+   /* if we allocated memory for the cache, free it */
+   if (pmtucache != NULL)
+   {
+      PMTU_FREE(pmtucache);
+      pmtucache = NULL;
+   }
+
+   pmtucache_mru = NULL;
+}
+
+/*
+ * FUNCTION: pmtu_firstguess()
+ *
+ * Returns a "first guess" path MTU for a given peer host IP address.
+ *
+ * PARAM1: ip_addr dest; the peer host IP address in network order.
+ * 
+ * RETURNS: an initial guess at the path MTU for the given peer 
+ *          host IP address.
+ */
+static
+unsigned
+pmtu_firstguess(ip_addr dest)
+{
+   ip_addr firsthop;
+   NET out_net;
+
+   /* On what net will IP try to send to this host?  
+    * If we don't know, our first guess for the path MTU is
+    * the largest IP datagram we can fit in a big packet buffer.
+    * If we do know, then our first guess for the path MTU is 
+    * the largest IP datagram we can send on that network.
+    */
+   out_net = iproute(dest, &firsthop);
+   if (out_net == NULL)
+      return (bigbufsiz - MaxLnh);
+   else
+      return (out_net->n_mtu - out_net->n_lnh);
+}
+
+/*
+ * FUNCTION: pmtu_nextguess()
+ *
+ * Returns a "next guess" path MTU for a given previous estimate.
+ *
+ * PARAM1: unsigned estimate; a previous path MTU estimate which is
+ *         now supposed to be too large.
+ * 
+ * RETURNS: a next guess at the path MTU.
+ */
+static
+unsigned
+pmtu_nextguess(unsigned estimate)
+{
+   /* If the previous estimate is equal to or below the lower 
+    * limit, keep it.
+    */
+   if (estimate <= pmtu_llimit)
+      return estimate;
+
+   /* Else, make a new estimate that is half of the previous 
+    * estimate, or the lower limit, whichever is higher.
+    */
+   return max(estimate >> 1, pmtu_llimit);
+}
+
+/*
+ * FUNCTION: pmtucache_set()
+ *
+ * Sets the path MTU cache entry for the given peer host IP address
+ * to contain a new estimate.
+ *
+ * PARAM1: ip_addr dest; the IP address of the peer (destination) 
+ *         host, in network order.
+ * PARAM2: unsigned estimate; the new path MTU estimate for the
+ *         peer.  May be 0, in which case pmtucache_set() will guess
+ *         a path MTU estimate.
+ */
+void
+pmtucache_set(ip_addr dest,
+              unsigned estimate)
+{
+   int i;
+   struct pmtucacheent * lru = NULL;
+
+   /* search through the cache for matching dest, and keep
+    * track of which entry is least-recently-used in lru 
+    */
+   for (i = 0; i < pmtu_maxcache; i++)
+   {
+      if (pmtucache[i].dest == dest)
+      {
+         /* found it! make it the most-recently-used entry */
+         pmtucache_mru = &pmtucache[i];
+set:
+         /* estimate may have come from an ICMP destination-unreachable
+          * (datagram too big) message, and may therefore be 0, so we
+          * may have to guess.
+          */
+          if (estimate == 0)
+             pmtucache_mru->pmtu = pmtu_nextguess(pmtucache_mru->pmtu);
+          else
+             pmtucache_mru->pmtu = estimate;
+         pmtucache_mru->lastused = pmtucache_mru->lastchanged = cticks;
+         return;
+      }
+      if ((lru == NULL) ||
+          (pmtucache[i].lastused < lru->lastused) ||
+          (pmtucache[i].dest == 0))
+         lru = &pmtucache[i];
+   }
+
+   /* if we didn't find an entry, recycle the least-recently-used
+    * entry to make one
+    */ 
+   if ((i >= pmtu_maxcache) && (lru != NULL))
+   {
+      pmtucache_mru = lru;
+      pmtucache_mru->dest = dest;
+      if (estimate)
+         pmtucache_mru->pmtu = estimate;
+      else
+         pmtucache_mru->pmtu = pmtu_firstguess(dest);
+      goto set;
+   }
+}
+
+/*
+ * FUNCTION: pmtucache_get()
+ *
+ * Gets the current path MTU estimate for a peer host IP address 
+ * from the path MTU cache.
+ *
+ * PARAM1: ip_addr dest; the IP address of the peer (destination) 
+ *         host, in network order.
+ *
+ * RETURNS: the current path MTU estimate for the given host.
+ */
+unsigned
+pmtucache_get(ip_addr dest)
+{
+   int i;
+   struct pmtucacheent * lru = NULL;
+
+   /* do a quick check of the most-recently-used entry */
+   if ((pmtucache_mru != NULL) &&
+       (pmtucache_mru->dest == dest))
+   {
+get:
+      /* if the cached estimate has timed out, restart discovery
+       * with a first-guess path MTU estimate */
+      if (PMTU_EXPIRED(pmtucache_mru->lastchanged))
+      {
+         pmtucache_mru->lastused = pmtucache_mru->lastchanged = cticks;
+         pmtucache_mru->pmtu = pmtu_firstguess(dest);
+      }
+      /* update the last-used time and return the cached estimate */
+      pmtucache_mru->lastused = cticks;
+      return pmtucache_mru->pmtu;
+   }
+
+   /* search through the cache for matching dest, and keep
+    * track of which entry is least-recently-used in lru 
+    */
+   for (i = 0; i < pmtu_maxcache; i++)
+   {
+      if (pmtucache[i].dest == dest)
+      {
+         /* found it! make it the most-recently-used entry and go return it */
+         pmtucache_mru = &pmtucache[i];
+         goto get;
+      }
+      if ((lru == NULL) ||
+          (pmtucache[i].lastused < lru->lastused) ||
+          (pmtucache[i].dest == 0))
+         lru = &pmtucache[i];
+   }
+
+   /* if we didn't find an entry, recycle the least-recently-used
+    * entry to make one, and start it with a first-guess estimate
+    */ 
+   if ((i >= pmtu_maxcache) && (lru != NULL))
+   {
+      pmtucache_mru = lru;
+      pmtucache_mru->dest = dest;
+      pmtucache_mru->pmtu = pmtu_firstguess(dest);
+      pmtucache_mru->lastchanged = cticks;
+      return pmtucache_mru->pmtu;
+   }
+
+   /* if we didn't find a least-recently-used entry, something's
+    * probably not right with the cache, so return our first-guess
+    * estimate and hope for the best
+    */
+   return pmtu_firstguess(dest);
+}
+
+#ifdef NET_STATS
+/*
+ * FUNCTION: pmtu_stats()
+ *
+ * Prints the path MTU cache and other statistical information.
+ *
+ * PARAM1: void * pio;
+ *
+ * RETURNS: SUCCESS (0).
+ */
+int
+pmtu_stats(void * pio)
+{
+   struct pmtucacheent * mru = pmtucache_mru;
+   int i;
+
+   ns_printf(pio, "path MTU cache timeout (ticks) = %lu\n", pmtu_timeout);
+   ns_printf(pio, "path MTU lower limit = %u\n", pmtu_llimit);
+
+   if (pmtucache == NULL)
+   {
+      ns_printf(pio, "no path MTU cache established\n");
+      return 0;
+   }
+
+   ns_printf(pio, "current time (ticks) = %lu\n", cticks);
+
+   ns_printf(pio, "host,       mtu,  lastused, lastchanged\n");
+
+   for (i = 0; i < pmtu_maxcache; i++)
+   {
+      if (pmtucache[i].dest != 0)
+      {
+         ns_printf(pio, "%u.%u.%u.%u   %d   %lu   %lu   %s%s\n",
+                   PUSH_IPADDR(pmtucache[i].dest),
+                   pmtucache[i].pmtu,
+                   pmtucache[i].lastused,
+                   pmtucache[i].lastchanged,
+                   PMTU_EXPIRED(pmtucache[i].lastchanged) ? "EXP " : "",
+                   (&pmtucache[i] == mru) ? "MRU" : "");
+      }
+   }
+
+   return 0;
+}
+
+#endif  /* NET_STATS */
+
+#endif  /* IP_PMTU */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/rtbtree.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/rtbtree.c
new file mode 100644
index 0000000..bd2dd3b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/rtbtree.c
@@ -0,0 +1,884 @@
+/*
+ * FILENAME: rtbtree.c
+ *
+ * Copyright 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * IP Routing table binary tree code, heavily based on the public domain
+ * "avltree.c" file. The original avltree.c is not copyrighted and is
+ * explicitly assigned to the public domain. Code is based on the
+ * ancient Algorithm documented by Knuth.
+ * InterNiche has formatted it to our code standards doc (although it was very
+ * clean to begin with) and modified it to keep the btree links directly in the
+ * route table structure. This modification avoids an extra set of alloc/free
+ * macros.
+ *
+ * MODULE: ip
+ *
+ * ROUTINES: avlrotleft(), avlrotright(), avlleftgrown(), 
+ * ROUTINES: avlrightgrown(), avlinsert(), avlleftshrunk(), avlrightshrunk(), 
+ * ROUTINES: avlfindhighest(), avlfindlowest(), avlremove(), avlaccess(), 
+ * ROUTINES: avldepthfirst(), avlbreadthfirst()
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+
+#ifdef BTREE_ROUTES
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+/* FUNCTION: avlrotleft()
+ * 
+ *  avlrotleft: perform counterclockwise rotation
+ *
+ *  Parameters:
+ *
+ *    n           Address of a pointer to a node
+ *
+ * PARAM1: struct avl_node * n
+ *
+ * RETURNS: 
+ */
+
+void
+avlrotleft(struct avl_node ** n)
+{
+	struct avl_node * tmp = *n;
+
+	*n = (*n)->right;
+	tmp->right = (*n)->left;
+	(*n)->left = tmp;
+}
+
+
+/* FUNCTION: avlrotright()
+ * 
+ *  avlrotright: perform clockwise rotation
+ *
+ *  Parameters:
+ *
+ *    n           Address of a pointer to a node
+ *
+ * PARAM1: struct avlnode *n
+ *
+ * RETURNS: 
+ */
+
+void
+avlrotright(struct avl_node ** n)
+{
+	struct avl_node * tmp = *n;
+
+	*n = (*n)->left;
+	tmp->left = (*n)->right;
+	(*n)->right = tmp;
+}
+
+
+
+/* FUNCTION: avlleftgrown()
+ * 
+ *  avlleftgrown: helper function for avlinsert
+ *
+ *  Parameters:
+ *
+ *    n           Address of a pointer to a node. This node's left 
+ *                subtree has just grown due to item insertion; its 
+ *                "skew" flag needs adjustment, and the local tree 
+ *                (the subtree of which this node is the root node) may 
+ *                have become unbalanced.
+ *
+ *  Return values:
+ *
+ *    BT_OK          The local tree could be rebalanced or was balanced 
+ *                from the start. The parent activations of the avlinsert 
+ *                activation that called this function may assume the 
+ *                entire tree is valid.
+ *
+ *    BT_BALANCE     The local tree was balanced, but has grown in height.
+ *                Do not assume the entire tree is valid.
+ *
+ * PARAM1: struct avl_node *n
+ *
+ * RETURNS: 
+ */
+
+enum AVLRES
+avlleftgrown(struct avl_node ** n)
+{
+   struct avl_node * rtp = *n;
+
+   switch (rtp->skew) 
+   {
+   case LEFT:
+      if (rtp->left->skew == LEFT) 
+      {
+         rtp->skew = rtp->left->skew = NONE;
+         avlrotright(n);
+      }
+      else 
+      {
+         switch (rtp->left->right->skew) 
+         {
+         case LEFT:
+            rtp->skew = RIGHT;
+            rtp->left->skew = NONE;
+            break;
+
+         case RIGHT:
+            rtp->skew = NONE;
+            rtp->left->skew = LEFT;
+            break;
+
+         default:
+            rtp->skew = NONE;
+            rtp->left->skew = NONE;
+         }
+         rtp->left->right->skew = NONE;
+         avlrotleft(&(rtp->left));
+         avlrotright(n);
+      }
+      return BT_OK;
+
+   case RIGHT:
+      rtp->skew = NONE;
+      return BT_OK;
+
+   default:
+      rtp->skew = LEFT;
+      return BT_BALANCE;
+   }
+}
+
+
+
+/* FUNCTION: avlrightgrown()
+ * 
+ *  avlrightgrown: helper function for avlinsert
+ *
+ *  See avlleftgrown for details.
+ *
+ * PARAM1: struct avl_node *n
+ *
+ * RETURNS: 
+ */
+
+enum AVLRES
+avlrightgrown(struct avl_node ** n)
+{
+   struct avl_node * rtp = *n;
+
+   switch (rtp->skew) 
+   {
+   case LEFT:     
+      rtp->skew = NONE;
+      return BT_OK;
+
+   case RIGHT:
+      if (rtp->right->skew == RIGHT) 
+      { 
+         rtp->skew = rtp->right->skew = NONE;
+         avlrotleft(n);
+      }
+      else 
+      {
+         switch (rtp->right->left->skew) 
+         {
+         case RIGHT:
+            rtp->skew = LEFT;
+            rtp->right->skew = NONE;
+            break;
+
+         case LEFT:
+            rtp->skew = NONE;
+            rtp->right->skew = RIGHT;
+            break;
+
+         default:
+            rtp->skew = NONE;
+            rtp->right->skew = NONE;
+         }
+         rtp->right->left->skew = NONE;
+         avlrotright(&(rtp->right));
+         avlrotleft(n);
+      }
+      return BT_OK;
+
+   default:
+      rtp->skew = RIGHT;
+      return BT_BALANCE;
+   }
+}
+
+
+
+/* FUNCTION: avlinsert()
+ * 
+ *  avlinsert: insert a node into the AVL tree.
+ *
+ *  Parameters:
+ *
+ *    n           Address of a pointer to a node.
+ *
+ *    d           Item to be inserted.
+ *
+ *  Return values:
+ *
+ *    BT_ERROR    The datum provided could not be inserted, either due 
+ *                to AVLKEY collision (the tree already contains another
+ *                item with which the same AVLKEY is associated), or
+ *                due to insufficient memory.
+ *
+ *    BT_OK       None of the subtrees of the node that n points to 
+ *                has grown, the AVL tree is valid.
+ *
+ *    BT_BALANCE  One of the subtrees of the node that n points to 
+ *                has grown, the node's "skew" flag needs adjustment,
+ *                and the AVL tree may have become unbalanced.
+ *
+ * That latter two return values are distinguished so that when avlinsert
+ * recursively calls itself, the number returned tells the parent activation
+ * if the AVL tree may have become unbalanced.
+ *
+ *
+ * PARAM1: struct avl_node *n
+ * PARAM2: AVLDATUM d
+ *
+ * RETURNS: 
+ */
+
+enum AVLRES
+avlinsert(struct avl_node ** parent, struct avl_node * new)
+{
+   enum AVLRES tmp;
+   
+   if (!(*parent))
+   {
+      *parent = new;
+      new->left = new->right = NULL;
+      new->skew = NONE;
+      return BT_BALANCE;
+   }
+
+   if (AVL_LESS(new, *parent))
+   {
+      if ((tmp = avlinsert(&(*parent)->left, new)) == BT_BALANCE) 
+      {
+         return avlleftgrown(parent);
+      }
+      return tmp;
+   }
+   if (AVL_GREATER(new, *parent)) 
+   {
+      if ((tmp = avlinsert(&(*parent)->right, new)) == BT_BALANCE) 
+      {
+         return avlrightgrown(parent);
+      }
+      return tmp;
+   }
+   return BT_ERROR;
+}
+
+
+/* FUNCTION: avlleftshrunk()
+ * 
+ *  avlleftshrunk: helper function for avlremove and avlfindlowest
+ *
+ *  Parameters:
+ *
+ *    n           Address of a pointer to a node. The node's left
+ *                subtree has just shrunk due to item removal; its
+ *                "skew" flag needs adjustment, and the local tree
+ *                (the subtree of which this node is the root node) may
+ *                have become unbalanced.
+ *
+ *   Return values:
+ *
+ *    BT_OK          The parent activation of the avlremove activation
+ *                that called this function may assume the entire
+ *                tree is valid.
+ *
+ *    BT_BALANCE     Do not assume the entire tree is valid.
+ *
+ * PARAM1: struct avl_node **n
+ *
+ * RETURNS: 
+ */
+
+enum AVLRES
+avlleftshrunk(struct avl_node ** n)
+{
+   struct avl_node * rtp = *n;
+
+   switch (rtp->skew) 
+   {
+   case LEFT:
+      rtp->skew = NONE;
+      return BT_BALANCE;
+
+   case RIGHT:
+      if (rtp->right->skew == RIGHT) 
+      {
+         rtp->skew = rtp->right->skew = NONE;
+         avlrotleft(n);
+         return BT_BALANCE;
+      }
+      else if (rtp->right->skew == NONE) 
+      {
+         rtp->skew = RIGHT;
+         rtp->right->skew = LEFT;
+         avlrotleft(n);
+         return BT_OK;
+      }
+      else 
+      {
+         switch (rtp->right->left->skew) 
+         {
+         case LEFT:
+            rtp->skew = NONE;
+            rtp->right->skew = RIGHT;
+            break;
+
+         case RIGHT:
+            rtp->skew = LEFT;
+            rtp->right->skew = NONE;
+            break;
+
+         default:
+            rtp->skew = NONE;
+            rtp->right->skew = NONE;
+         }
+         rtp->right->left->skew = NONE;
+         avlrotright(&(rtp->right));
+         avlrotleft(n);
+         return BT_BALANCE;
+      }
+
+   default:
+      rtp->skew = RIGHT;
+      return BT_OK;
+   }
+}
+
+
+/* FUNCTION: avlrightshrunk()
+ * 
+ *  avlrightshrunk: helper function for avlremove and avlfindhighest
+ *
+ *  See avlleftshrunk for details.
+ *
+ * PARAM1: struct avl_node **n
+ *
+ * RETURNS: 
+ */
+
+enum AVLRES
+avlrightshrunk(struct avl_node ** n)
+{
+   struct avl_node * rtp = *n;
+
+   switch (rtp->skew) 
+   {
+   case RIGHT:
+      rtp->skew = NONE;
+      return BT_BALANCE;
+
+   case LEFT:
+      if (rtp->left->skew == LEFT) 
+      {
+         rtp->skew = rtp->left->skew = NONE;
+         avlrotright(n);
+         return BT_BALANCE;
+      }
+      else if (rtp->left->skew == NONE) 
+      {
+         rtp->skew = LEFT;
+         rtp->left->skew = RIGHT;
+         avlrotright(n);
+         return BT_OK;
+      }
+      else 
+      {
+         switch (rtp->left->right->skew) 
+         {
+         case LEFT:
+            rtp->skew = RIGHT;
+            rtp->left->skew = NONE;
+            break;
+
+         case RIGHT:
+            rtp->skew = NONE;
+            rtp->left->skew = LEFT; 
+            break;
+
+         default:
+            rtp->skew = NONE;
+            rtp->left->skew = NONE;
+         }
+         rtp->left->right->skew = NONE;
+         avlrotleft(&(rtp->left));
+         avlrotright(n);
+         return BT_BALANCE;
+      }
+
+   default:
+      rtp->skew = LEFT;
+      return BT_OK;
+   }
+}
+
+
+/* FUNCTION: avlfindhighest()
+ * 
+ *  avlfindhighest: replace a node with a subtree's highest-ranking item.
+ *
+ *  Parameters:
+ *
+ *    target      Pointer to node to be replaced.
+ *
+ *    tree        Address of pointer to subtree.
+ *
+ *    res         Pointer to variable used to tell the caller whether
+ *                further checks are necessary; analog to the return
+ *                values of avlleftgrown and avlleftshrunk (see there). 
+ *
+ *
+ * PARAM1: struct avl_node *target
+ * PARAM2: struct avl_node **n
+ * PARAM3: enum AVLRES *res
+ *
+ * RETURNS: 
+ *
+ *    1           A node was found; the target node has been replaced.
+ *
+ *    0           The target node could not be replaced because
+ *                the subtree provided was empty.
+ *
+ */
+
+int
+avlfindhighest(struct avl_node * target, struct avl_node ** tree, enum AVLRES * res)
+{
+   struct avl_node * tmp;
+
+   *res = BT_BALANCE;
+   if (!(*tree)) 
+   {
+      return 0;
+   }
+   if ((*tree)->right) 
+   {
+      if (!avlfindhighest(target, &(*tree)->right, res)) 
+      {
+         return 0;
+      }
+      if (*res == BT_BALANCE) 
+      {
+         *res = avlrightshrunk(tree);
+      }
+      return 1;
+   }
+
+   /* Fall to here if tree is the highest item in the sub tree.
+    * At this point the original avl code just copied the data key
+    * from *tree to target. We need to copy many data items and the
+    * easiest way seems to be to save target's btree info into *tree
+    * and then copy all of *tree into target.
+    */
+
+   tmp = (*tree)->left;            /* save new *tree value */
+   (*tree)->left = target->left;
+   (*tree)->right = target->right;
+   (*tree)->skew = target->skew;
+   MEMCPY(target, *tree, sizeof(struct RtMib));
+
+   (*tree)->right = 0;
+   (*tree)->left = 0;
+   ((RTMIB)*tree)->ipRouteNextHop = 0; /* mark empty */
+   *tree = tmp;
+   return 1;
+}
+
+
+/* FUNCTION: avlfindlowest()
+ * 
+ *  avlfindlowest: replace node with a subtree's lowest-ranking item.
+ *
+ *  See avlfindhighest for the details.
+ *
+ * PARAM1: struct avl_node *target
+ * PARAM2: struct avl_node **n
+ * PARAM3: enum AVLRES *res
+ *
+ * RETURNS: 
+ */
+
+int
+avlfindlowest(struct avl_node * target, struct avl_node **tree, enum AVLRES * res)
+{
+   struct avl_node * tmp;
+
+   *res = BT_BALANCE;
+   if (!(*tree))
+   {
+      return 0;
+   }
+   if ((*tree)->left)
+   {
+      if (!avlfindlowest(target, &(*tree)->left, res)) 
+      {
+         return 0;
+      }
+      if (*res == BT_BALANCE) 
+      {
+         *res =  avlleftshrunk(tree);
+      }
+      return 1;
+   }
+   tmp = (*tree)->right;            /* save new *tree value */
+   (*tree)->left = target->left;
+   (*tree)->right = target->right;
+   (*tree)->skew = target->skew;
+   MEMCPY(target, *tree, sizeof(struct RtMib));
+
+   (*tree)->right = 0;
+   (*tree)->left = 0;
+   ((RTMIB)*tree)->ipRouteNextHop = 0; /* mark empty */
+   *tree = tmp;
+   return 1;
+}
+
+
+
+/* FUNCTION: avlremove()
+ * 
+ *  avlremove: remove an item from the tree.
+ *
+ *  Parameters:
+ *
+ *    n           trunk of AVL tree.
+ *
+ *    key         AVLKEY of item to be removed.
+ *
+ *
+ * PARAM1: struct avl_node **n
+ * PARAM2: int key
+ *
+ * RETURNS: 
+ *
+ *   BT_OK        None of the subtrees of the node that n points to
+ *                has shrunk, the AVL tree is valid.
+ *
+ *   BT_BALANCE   One of the subtrees of the node that n points to
+ *                has shrunk, the node's "skew" flag needs adjustment,
+ *                and the AVL tree may have become unbalanced.
+ *
+ *   BT_ERROR     The tree does not contain an item yielding the
+ *                AVLKEY value provided by the caller.
+ *
+ * If return is not BT_ERROR then the item has been removed. The exact
+ * value of nonzero yields is of no concern to user code; when
+ * avlremove recursively calls itself, the number returned tells
+ * the parent activation if the AVL tree may have become unbalanced.
+ */
+
+enum AVLRES
+avlremove(struct avl_node **n, void * key)
+{
+   enum AVLRES tmp;
+
+#ifdef NPDEBUG
+   if (!n || !(*n)) 
+   {
+      dtrap();
+      return BT_ERROR;
+   }
+#endif /* NPDEBUG */
+
+    /* end recur at (*n) == 0 */
+    if (*n == 0)
+   	  return BT_OK;
+
+   /* recurse if IP to delete is on left side of tree (lower) */
+   if (AVL_KEY_LESS(key, (*n)))
+   {
+      if ((tmp = avlremove(&(*n)->left, key)) == BT_BALANCE) 
+      {
+         return avlleftshrunk(n);
+      }
+      return tmp;
+   }
+
+   /* recurse if IP to delete is on right side of tree (higher) */
+   if (AVL_KEY_GREATER(key, (*n)))
+   {
+      if ((tmp = avlremove(&(*n)->right, key)) == BT_BALANCE) 
+      {
+         return avlrightshrunk(n);
+      }
+      return tmp;
+   }
+
+   /* get to here if *n contains IP to delete */
+
+   /* find node with which to replace n. If n has a left (lower)
+    * branch, move it up to  replace n; else use right.
+    */
+   if ((*n)->left)
+   {
+      if (avlfindhighest(*n, &(*n)->left, &tmp)) 
+      {
+         if (tmp == BT_BALANCE) 
+         {
+            tmp = avlleftshrunk(n);
+         }
+         return tmp;
+      }
+   }
+   if ((*n)->right)
+   {
+      if (avlfindlowest(*n, &(*n)->right, &tmp)) 
+      {
+         if (tmp == BT_BALANCE) 
+         {
+            tmp = avlrightshrunk(n);
+         }
+         return tmp;
+      }
+   }
+
+   (*n)->right = 0;
+   (*n)->left = 0;
+   ((RTMIB)*n)->ipRouteNextHop = 0; /* mark empty */
+   *n = NULL;
+   return BT_BALANCE;
+}
+
+
+/* FUNCTION: avlv4_access()
+ * FUNCTION: avlv6_access()
+ * 
+ *  Retrieve the route entry for IP address. The v4 version takes a
+ * v4 address; the v6 version takes a pointer to a v6 address.
+ *
+ *
+ * PARAM1: struct avl_node * n - Pointer to the root node.
+ * PARAM2: ip_addr key      - IP address to be accessed.
+ *
+ * RETURNS: pointer to route table entry containing passed IP address if
+ *          found, else NULL if not found.
+ *
+ */
+
+struct avl_node *
+avlv4_access(struct avl_node * n, ip_addr key)
+{
+   if (!n)
+   {
+      return NULL;
+   }
+   if (key < htonl(((RTMIB)n)->ipRouteDest) )
+   {
+      return avlv4_access(n->left, key);
+   }
+   if (key > htonl(((RTMIB)n)->ipRouteDest) )
+   {
+      return avlv4_access(n->right, key);
+   }
+   return (n);
+}
+
+#ifdef IP_V6
+struct avl_node *
+avlv6_access(struct avl_node * n, ip6_addr * key)
+{
+   int result;
+
+   if (!n)
+   {
+      return NULL;
+   }
+
+   result = MEMCMP(key, &((struct ipv6Route_mib *)n)->ipv6RouteDest, 16);
+   if (result < 0)
+   {
+      return avlv6_access(n->left, key);
+   }
+   if (result > 0)
+   {
+      return avlv6_access(n->right, key);
+   }
+   return (n);
+}
+#endif   /* IP_V6 */
+
+
+/* FUNCTION: avldepthfirst()
+ * 
+ *  avldepthfirst: depth-first tree traversal.
+ *
+ *  Parameters:
+ *
+ *    n          Pointer to the root node.
+ *
+ *    f          Worker function to be called for every node.
+ *
+ *    param      Additional parameter to be passed to the
+ *               worker function
+ *
+ *    depth      Recursion depth indicator. Allows the worker function
+ *               to determine how many levels the node being processed
+ *               is below the root node. Can be used, for example,
+ *               for selecting the proper indentation width when
+ *               avldepthfirst ist used to print a tree dump to
+ *               the screen.
+ *
+ *               Most of the time, you will want to call avldepthfirst
+ *               with a "depth" value of zero.
+ *
+ * PARAM1: struct avl_node *n
+ * PARAM2: AVLWORKER *f
+ * PARAM3: int param
+ * PARAM4: int depth
+ *
+ * RETURNS: 
+ */
+
+void
+avldepthfirst(
+   struct avl_node * n,
+   void(*func)(struct avl_node * n, long param, int depth),
+   long param,
+   int depth)
+{
+   if(!n)
+      return;
+
+   avldepthfirst(n->left, func, param, depth + 1);
+   (*func)(n, param, depth);
+   avldepthfirst(n->right, func, param, depth +1);
+}
+
+#ifdef NOTDEF
+/* FUNCTION: avlbreadthfirst()
+ * 
+ *  avlbreadthfirst: breadth-first tree traversal.
+ * 
+ *  See avldepthfirst for details.
+ *
+ * PARAM1: struct avl_node *n
+ * PARAM2: AVLWORKER *f
+ * PARAM3: int param
+ *
+ * RETURNS: 
+ */
+
+void
+avlbreadthfirst(struct avl_node * n, AVLWORKER * f, int param)
+{
+    struct queue   q;
+
+   if (!n) return;
+      qinit(&q);
+   qappend(&q, n);
+   while (qremove(&q, &n)) 
+   {
+      (*f)(n, param, 0);
+      if (n->left) qappend(&q, n->left);
+         if (n->right) qappend(&q, n->right);
+   }
+}
+#endif   /* NOTDEF */
+
+#ifdef IP_V6
+
+/* The next four routines are macros on IPv4 only builds. On
+ * builds which include IPv6, they are implemented by the following
+ * code, which contains #ifdefs for IPv4 (dual mode) support.
+ */
+
+int
+AVL_LESS(struct avl_node * a, struct avl_node * b)
+{
+   int result;
+
+#ifdef IP_V4
+   if(a->treetype == IPV4_ROUTE)
+      return((htonl(((RTMIB)a)->ipRouteDest) < htonl(((RTMIB)b)->ipRouteDest)));
+#endif   /* IP_V4 */
+
+   /* fall to here if the route type is IPv6 */
+   result = MEMCMP(&((ip6_route *)a)->ipv6RouteDest, &((ip6_route *)b)->ipv6RouteDest, 16);
+
+   if(result < 0)
+      return TRUE;
+   else
+      return FALSE;
+}
+
+int
+AVL_GREATER(struct avl_node * a, struct avl_node * b)
+{
+   int result;
+
+#ifdef IP_V4
+   if(a->treetype == IPV4_ROUTE)
+      return((htonl(((RTMIB)a)->ipRouteDest) > htonl(((RTMIB)b)->ipRouteDest)));
+#endif   /* IP_V4 */
+
+   /* fall to here if the route type is IPv6 */
+   result = MEMCMP(&((ip6_route *)a)->ipv6RouteDest, &((ip6_route *)b)->ipv6RouteDest, 16);
+
+   if(result > 0)
+      return TRUE;
+   else
+      return FALSE;
+}
+
+int
+AVL_KEY_LESS(void * key, struct avl_node * b)
+{
+   int result;
+
+#ifdef IP_V4
+   if(b->treetype == IPV4_ROUTE)
+      return(((*(ip_addr*)key) < htonl(((RTMIB)b)->ipRouteDest)));
+#endif   /* IP_V4 */
+
+   /* fall to here if the route type is IPv6 */
+   result = MEMCMP(key, &((ip6_route *)b)->ipv6RouteDest, 16);
+
+   if(result < 0)
+      return TRUE;
+   else
+      return FALSE;
+}
+
+int
+AVL_KEY_GREATER(void * key, struct avl_node * b)
+{
+   int result;
+
+#ifdef IP_V4
+   if(b->treetype == IPV4_ROUTE)
+      return(((*(ip_addr*)key) > htonl(((RTMIB)b)->ipRouteDest)));
+#endif   /* IP_V4 */
+
+   /* fall to here if the route type is IPv6 */
+   result = MEMCMP(key, &((ip6_route *)b)->ipv6RouteDest, 16);
+
+   if(result > 0)
+      return TRUE;
+   else
+      return FALSE;
+}
+#endif   /* IP_V6 */
+
+
+#endif /* BTREE_ROUTES */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ip/udp.c b/FPGA_nios/hit_pat_bsp/iniche/src/ip/udp.c
new file mode 100644
index 0000000..a5d5d46
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ip/udp.c
@@ -0,0 +1,694 @@
+/*
+ * FILENAME: udp.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * UDP send and receive routines
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: udpdemux(), udp_send(), udpswap(), udp_socket(), 
+ * ROUTINES: udp_alloc(), udp_maxalloc(), udp_free(), udp_stats()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990, 1993 by NetPort Software. */
+/* Portions Copyright 1986 by Carnegie Mellon  */
+/* Portions Copyright 1984 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+
+#ifdef IP_MULTICAST
+#include "tcpport.h"
+#endif
+
+
+struct UdpMib  udp_mib;    /* udp stats block */
+
+extern   UDPCONN  firstudp;
+#ifdef IP_MULTICAST
+extern int udp_soinput(PACKET pkt, void *so_ptr);
+#endif
+
+
+/* FUNCTION: udpdemux()
+ *
+ * This routine handles incoming UDP packets. They're handed to it by 
+ * the internet layer. It demultiplexes the incoming packet based on 
+ * the local port and upcalls the appropriate routine. 
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: 0 if OK or ENP error code
+ */
+
+int
+udpdemux(PACKET p)
+{
+   struct ip * pip;  /* IP header below this layer */
+   struct udp *   pup;  /* UDP header of this layer */
+   struct ph   php;     /* pseudo header for checksumming */
+   UDPCONN con;      /* UDP connection for table lookup */
+   unsigned short osum, xsum; /* scratch checksum holders */
+   unsigned plen; /* packet length */
+   int   e;    /* general error holder */
+
+   /* First let's verify that it's a valid UDP packet. */
+   pip = ip_head(p);       /* we'll need IP header info */
+   pup = (struct udp*)ip_data(pip);   /*  also need UDP header */
+   plen = htons(pup->ud_len);
+
+   if (plen > p->nb_plen)
+   {
+#ifdef   NPDEBUG
+/* 
+ * Altera Niche Stack Nios port modification:
+ * cast arg to unsigned long to remove build warning
+ */
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+         dprintf("UDP: bad len pkt: rcvd: %u, hdr: %u.\n",
+                 p->nb_plen, (unsigned int)(htons(pup->ud_len) + UDPLEN));
+#endif
+      udp_mib.udpInErrors++;
+      udp_free(p);
+      return ENP_BAD_HEADER;
+   }
+
+   osum = pup->ud_cksum;
+   /* did other guy use checksumming? */
+   if (osum)
+   {
+      if (plen & 1) ((char *)pup)[plen] = 0;
+         php.ph_src = p->fhost;
+      php.ph_dest = pip->ip_dest;
+      php.ph_zero = 0;
+      php.ph_prot = UDP_PROT;
+      php.ph_len  = pup->ud_len;
+
+      pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1);
+      xsum = ~cksum(pup, (plen+1)>>1);
+      if (!xsum)
+         xsum = 0xffff;
+      pup->ud_cksum = osum;
+      if (xsum != osum)
+      {
+#ifdef   NPDEBUG
+         if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+         {
+            dprintf("UDPDEMUX: bad xsum %04x right %04x from %u.%u.%u.%u\n",
+                    osum, xsum, PUSH_IPADDR(p->fhost));
+            if (NDEBUG & DUMP)
+               ip_dump(p);
+         }
+#endif
+         udp_mib.udpInErrors++;
+         udp_free(p);
+         return ENP_BAD_HEADER;
+      }
+   }
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+#endif
+
+   /* Prior to upcall, adjust nb_prot for size of IP and UDP headers */
+   e = (sizeof(struct udp) + ip_hlen(pip));
+   p->nb_plen -= e;
+   p->nb_prot += e;
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+   {
+      dprintf("UDP: pkt[%u] from %u.%u.%u.%u:%d to %d\n",
+       plen, PUSH_IPADDR(p->fhost), pup->ud_srcp, pup->ud_dstp);
+   }
+#endif
+
+   /* check for special cases - we have a built-in snmp agent and 
+    * echo server. We do SNMP before trying the demux table so 
+    * external application programs can examine SNMP packets that 
+    */
+#ifdef PREBIND_AGENT
+#ifdef INCLUDE_SNMPV3      /* If V3 is present, call SNMPV3 upcall */
+   if (pup->ud_dstp == SNMP_PORT)
+   {
+      udp_mib.udpInDatagrams++;
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      e = v3_udp_recv(p, pup->ud_srcp);      /* upcall imbedded snmp agent */
+      LOCK_NET_RESOURCE(NET_RESID);
+      if (e != ENP_NOT_MINE)
+         return(e);
+      /* else SNMP pkt was not for imbedded agent, fall to try demux table */
+   }
+#else                   /* Else call V1's upcall, if V1 is present */
+   if (pup->ud_dstp == SNMP_PORT)
+   {
+      udp_mib.udpInDatagrams++;
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      e = snmp_upc(p, pup->ud_srcp);      /* upcall imbedded snmp agent */
+      LOCK_NET_RESOURCE(NET_RESID);
+      if (e != ENP_NOT_MINE)
+         return(e);
+      /* else SNMP pkt was not for imbedded agent, fall to try demux table */
+   }
+#endif   /* INCLUDE_SNMPV3 */
+#endif   /* PREBIND_AGENT */
+
+   /* run through the demux table and try to upcall it */
+
+   for (con = firstudp; con; con = con->u_next)
+   {
+#ifdef IP_V6
+      /* we only want to check UDP-over-IPv4 connections */
+      if (!(con->u_flags & UDPCF_V4))
+         continue;
+#endif
+
+      /* enforce all three aspects of tuple matching. Old code
+      assumed lport was unique, which is not always so. */
+      if (con->u_lport && (con->u_lport != pup->ud_dstp))
+         continue;
+      if (con->u_fport && (con->u_fport != pup->ud_srcp))
+         continue;
+      if (con->u_fhost && (con->u_fhost != p->fhost))
+         continue;
+
+#ifdef INCLUDE_TCP /* makes udp_soinput() available */
+#ifdef IP_MULTICAST
+      /* In the case of multicast, check if there is multicast membership
+       * attached to this socket and if so, is the incoming packet
+       * addressed to the multicast address
+       */
+      if (IN_MULTICAST(ntohl(pip->ip_dest)))
+      {
+         struct socket *soptr = (struct socket *)con->u_data;
+
+         if ((con->u_rcv == udp_soinput) && (soptr->inp_moptions != NULL))
+         {
+            u_short  i;
+            struct ip_moptions *imo = soptr->inp_moptions;
+
+            for (i = 0; i < imo->imo_num_memberships; ++i)
+            {
+               if ((imo->imo_membership[i]->inm_netp == p->net) &&
+                   (imo->imo_membership[i]->inm_addr == pip->ip_dest))
+               {
+                  goto found;
+               }
+            }
+            continue;
+         }
+      }
+      found:
+
+#endif /* IP_MULTICAST */
+#endif /* INCLUDE_TCP */
+
+      /* if this endpoint has been bound to a local interface address,
+       * make sure the packet was received on that interface address
+       */
+      if (!IN_MULTICAST(ntohl(pip->ip_dest)))
+      {
+         if ((con->u_lhost != 0) && (con->u_lhost != pip->ip_dest)) 
+            continue;
+      }
+
+      /* fall to here if we found it */
+      udp_mib.udpInDatagrams++;
+      if (con->u_rcv)         /* if upcall address is set... */
+      {
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         e = ((*con->u_rcv)(p, con->u_data));   /* upcall it */
+         LOCK_NET_RESOURCE(NET_RESID);
+      }
+      else
+         e = ENP_LOGIC;
+
+      /* if error occurred in upcall or there was no upcall hander
+         its up to this routine to free the packet buffer */
+      if (e)
+      {
+         udp_mib.udpInErrors++;
+         udp_free(p);
+      }
+
+      return(e);
+   }
+
+#ifdef DNS_CLIENT
+   /* see if this is a DNS reply packet */
+   if (pup->ud_srcp == DNS_PORT)    /* sent from DNS port? */
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      e = dns_upcall(p, pup->ud_dstp);    /* upcall dns client code */
+      LOCK_NET_RESOURCE(NET_RESID);
+      udp_mib.udpInDatagrams++;
+      if (e != ENP_NOT_MINE)  /* if mine, return here */
+      {
+         /* the DNS upcall does not appear to free the packet, so
+            we have to do it */
+         udp_free(p);
+         return(e);
+      }
+   }
+#endif   /* DNS_CLIENT */
+
+#ifdef RIP_SUPPORT
+   /* see if this is a RIP packet */
+   if (pup->ud_srcp == RIP_PORT)    /* sent from DNS port? */
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      e = rip_udp_recv(p, pup->ud_dstp);     /* upcall RIP code */
+      LOCK_NET_RESOURCE(NET_RESID);
+      /* note that the RIP upcall does appear to free the packet,
+         so we don't do it */
+      udp_mib.udpInDatagrams++;
+      if (e != ENP_NOT_MINE)  /* if mine, return here */
+         return(e);
+   }
+#endif   /* RIP_SUPPORT */
+
+#ifdef UDP_ECHO_SVR
+   /* finally, see if this is an echo packet */
+   if (pup->ud_dstp == 7)     /* echo port */
+   {
+      udp_mib.udpInDatagrams++;
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      e = udp_send(pup->ud_srcp, 7, p);      /* echo it */
+      LOCK_NET_RESOURCE(NET_RESID);
+      return(e);
+   }
+#endif   /* UDP_ECHO_SVR */
+
+   /* Fall to here if packet is not for us. Check if the packet was 
+    * sent to an ip broadcast address. If it was, don't send a 
+    * destination unreachable. 
+    */
+   if ((pip->ip_dest == 0xffffffffL) ||   /* Physical cable broadcast addr*/
+       (pip->ip_dest == p->net->n_netbr) ||   /* All subnet broadcast */
+       (pip->ip_dest == p->net->n_netbr42) || /* All subnet bcast (4.2bsd) */
+       (pip->ip_dest == p->net->n_subnetbr))  /* Our subnet broadcast */
+   {
+#ifdef   NPDEBUG
+      if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+         dprintf("UDP: ignoring ip broadcast\n");
+#endif
+      udp_mib.udpInErrors++;
+      udp_free(p);
+      return ENP_NOT_MINE;
+   }
+
+#ifdef   NPDEBUG
+   if ((NDEBUG & UPCTRACE) && (NDEBUG & TPTRACE))
+   {
+      dprintf("UDP: unexpected port %04x\n", pup->ud_dstp);
+      if (NDEBUG & DUMP) 
+         ip_dump(p);
+   }
+#endif
+
+#ifdef FULL_ICMP
+   /* send destination unreachable.  Swap back all the swapped information */
+   /* so that the destun packet format is correct */
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+#endif   /* BYTE_ORDER */
+   
+   icmp_destun(p->fhost, p->net->n_ipaddr, pip, DSTPORT, p->net);
+#endif   /* FULL_ICMP */
+
+   udp_mib.udpNoPorts++;
+   udp_free(p);
+   return ENP_NOT_MINE;
+}
+
+
+/* FUNCTION: udp_send()
+ *
+ * udp_send() - Prepend a udp header on a packet, checksum it and 
+ * pass it to IP for sending. PACKET p should have fhost set to 
+ * target IP address, nb_prot pointing to udpdata, & nb_plen set 
+ * before call. If you expect to get any response to this packet you 
+ * should have opened a UDPCONN with udp_open() prior to calling 
+ * this. 
+ *
+ * 
+ * PARAM1: unshort fport
+ * PARAM2: unshort lport
+ * PARAM3: PACKET p
+ *
+ * RETURNS: Returns 0 if sent OK, else non-zero error code if error 
+ * detected. 
+ */
+
+int
+udp_send(unshort fport, unshort lport, PACKET p)
+{
+   struct udp* pup;
+   struct ph   php;
+   struct ip * pip;
+   int         udplen;
+   int         e;
+   ip_addr     src_ip;    /* source IP, for checksumming purposes */
+
+#ifdef   NPDEBUG
+   if (NDEBUG & (INFOMSG|TPTRACE))
+      dprintf("UDP: pkt [%u] %04x -> %u.%u.%u.%u:%04x\n", p->nb_plen, lport,
+    PUSH_IPADDR(p->fhost), fport);
+#endif
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   /* prepend UDP header to upper layer's data */
+   p->nb_prot -= sizeof(struct udp);
+   pup = (struct udp*)p->nb_prot;
+   udplen = p->nb_plen + sizeof(struct udp);
+   p->nb_plen = udplen;
+   if (udplen & 1) ((char *)pup)[udplen] = 0;
+
+      pup->ud_len = (unshort)udplen;   /* fill in the UDP header */
+   pup->ud_srcp = lport;
+   pup->ud_dstp = fport;
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   udpswap(pup);
+#endif   /* BYTE_ORDER */
+   
+#ifdef MULTI_HOMED
+   /* getting the source IP address for a broadcast is a bit tricky: */
+   if (p->fhost == 0xffffffff)
+   {
+      if (!p->net)
+      {
+         dtrap();    /* programmer forgot to select iface */
+         /* it would appear that the callers of udp_send() expect it
+            to do cleanup on failure, so free the packet buffer here */
+         udp_free(p);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         return ENP_NO_IFACE;
+      }
+      src_ip = p->net->n_ipaddr;
+   }
+   else
+#endif   /* MULTI_HOMED */
+
+   /* set the IP addresses in the IP header. The pseudo header used for
+    * checksumming overlays the addresses on the IP header area in the
+    * buffer, so setting them there (which we need to do for cksum
+    * anyway) sets up for IP too.
+    */
+   src_ip = ip_mymach(p->fhost);
+   php.ph_src = src_ip;
+   php.ph_dest = p->fhost;
+
+#ifdef NO_UDP_CKSUM
+   /* If no UDP checksum support, just zero the checksum field */
+   pup->ud_cksum = 0;
+#else
+   /* finish filling in the pseudo header required for checksumming */
+   php.ph_zero = 0;
+   php.ph_prot = UDP_PROT;
+   php.ph_len = pup->ud_len;
+   pup->ud_cksum = cksum(&php, sizeof(struct ph)>>1);
+   pup->ud_cksum = ~cksum(pup, (udplen+1)>>1);
+   if (pup->ud_cksum == 0)
+      pup->ud_cksum = 0xffff;
+#endif
+
+   /* need to fill in IP addresses at this layer too */
+   pip = (struct ip *)(p->nb_prot - sizeof(struct ip));
+   pip->ip_src = src_ip;
+   pip->ip_dest = p->fhost;
+
+   udp_mib.udpOutDatagrams++;
+
+   p->nb_plen = udplen;       /* nb_prot was adjusted above */
+   e = ip_write(UDP_PROT, p);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return e;
+}
+
+
+/* FUNCTION: udpswap()
+ *
+ * udpswap(udp header) - swap the fields in a udp header for transmission
+ * on the net. This is not needed on little endian CPUs.
+ * 
+ * PARAM1: struct udp *pup
+ *
+ * RETURNS: void
+ */
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+void
+udpswap(struct udp *pup)
+{
+
+   pup->ud_srcp = htons(pup->ud_srcp);
+   pup->ud_dstp = htons(pup->ud_dstp);
+   pup->ud_len = htons(pup->ud_len);
+   pup->ud_cksum = htons(pup->ud_cksum);
+}
+#endif   /* BYTE_ORDER */
+
+
+/* FUNCTION: udp_socket()
+ *
+ * udp_socket() - Select a port number at random, but avoid reserved 
+ * ports from 0 thru 1024. Also leave range from 1025 thru 1199 
+ * available for explicit application use. 
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: Returns a useable port 
+ * number in local endian 
+ */
+
+
+#define  MINSOCKET   1200
+static unshort usocket = 0;   /* next socket to grab */
+
+unshort
+udp_socket(void)
+{
+   UDPCONN tmp;
+
+   if (usocket < MINSOCKET)
+   {
+      /* logic for for init and after wraps */
+      usocket = (unshort)(cticks & 0x7fff);
+      if (usocket < MINSOCKET)
+         usocket += MINSOCKET;
+   }
+   /* scan existing connections, making sure socket isn't in use */
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+   {
+      if (tmp->u_lport == usocket)
+      {
+         usocket++;     /* bump socket number */
+         tmp = firstudp;   /* restart scan */
+         continue;
+      }
+   }
+   return usocket++;
+}
+
+
+
+/* FUNCTION: udp_alloc()
+ *
+ * udp_alloc(sizes) - returns a pointer to a packet buffer big enough 
+ * for the specified sizes.
+ *
+ * 
+ * PARAM1: int datalen
+ * PARAM2: int optlen
+ *
+ * RETURNS:  Returns buffer, or NULL in no buffer was available. 
+ */
+
+PACKET
+udp_alloc(int datalen, int optlen)
+{
+   int   len;
+   PACKET p;
+
+   len = (datalen + sizeof(struct udp) + 1) & ~1;
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   p = pk_alloc(len + UDPHDRSLEN + optlen);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (p != (PACKET)NULL)
+   {
+      /* set prot pointers past end of UDP header  */
+      len = sizeof(struct ip) + (optlen >> 2) + sizeof(struct udp);
+      p->nb_prot += len;
+      p->nb_plen -= len;
+   }
+
+   return (p);
+}
+
+
+/* FUNCTION: udp_maxalloc()
+ *
+ * udp_maxalloc() - returns the largest allocation possible
+ *                  using udp_alloc()
+ *
+ * RETURNS: an int indicating the largest allocation possible
+ *          using udp_alloc(); i.e. if the sum of udp_alloc()
+ *          arguments datalen + optlen is greater than the
+ *          returned value, the allocation will fail
+ */
+
+int
+udp_maxalloc(void)
+{
+#ifdef HEAPBUFS
+   /* if heap buffers are available, the largest UDP datagram that can be
+    * created is ((2^16 - 1) - (size of IP and UDP headers)) */
+   return (0xFFFF - (sizeof (struct ip) + sizeof (struct udp)));
+#else
+   /* if heap buffers are not available, the largest size of a UDP datagram
+    * is constrained by what will fit inside a big buffer */
+   return (bigbufsiz - UDPHDRSLEN);
+#endif
+}
+
+
+/* FUNCTION: udp_free()
+ *
+ * udp_free() - frees an allocated packet buffer
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: void
+ */
+
+void
+udp_free(PACKET p)
+{
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+}
+
+#ifdef NET_STATS
+
+
+/* FUNCTION: udp_stats()
+ *
+ * udp_stats() - print UDP stats
+ *
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+udp_stats(void * pio)
+{
+   ns_printf(pio,"UDP MIB dump:\n");
+   ns_printf(pio,"In: Good: %lu    No Port: %lu     Bad: %lu\n",
+      udp_mib.udpInDatagrams, udp_mib.udpNoPorts, udp_mib.udpInErrors);
+   ns_printf(pio,"Out: %lu\n", udp_mib.udpOutDatagrams);
+   return 0;
+}
+
+/* FUNCTION: udpsock_list()
+ * 
+ * Display information about all the existing UDP sockets.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS:  0 if successfull, else error code.
+ */
+
+/* for display purpose (udpsock_list()), maintain a list of
+ * hardcoded UDP ports on which we are listening.
+ */
+static unshort sbindlist[] = {
+#ifdef PREBIND_AGENT
+   SNMP_PORT,
+#endif
+#ifdef DNS_CLIENT
+   DNS_PORT,
+#endif
+#ifdef RIP_SUPPORT
+   RIP_PORT,
+#endif
+#ifdef UDP_ECHO_SVR
+   7,
+#endif
+   0     /* 0 marks the end of the list */
+};
+
+int
+udpsock_list(void * pio)
+{
+   UDPCONN con;      /* UDP connection for table lookup */
+   int i, len;
+
+   if (!firstudp)
+   {
+      ns_printf(pio,"No UDP sockets\n");
+      return 0;
+   }
+
+   ns_printf(pio, "Here is a list of all UDP sockets (normal/lightweight).\n");
+   ns_printf(pio, "UDP sock, hosts          ,     ports,    IPv6 addrs");
+
+   for (con = firstudp; con; con = con->u_next)
+   {
+#ifdef IP_V4
+      if (con->u_flags & UDPCF_V4)
+      {
+         ns_printf(pio,"\n%lx,  %u.%u.%u.%u", con, PUSH_IPADDR(con->u_fhost));
+         ns_printf(pio,"->%u.%u.%u.%u ", PUSH_IPADDR(con->u_lhost));
+      }
+      else
+         ns_printf(pio,"\n%lx,  - (v6 socket) -  ", con);
+#endif
+      ns_printf(pio,", %u->%u, ", con->u_lport, con->u_fport);
+
+
+#ifdef IP_V6
+      if (con->u_flags & UDPCF_V6)
+      {
+         char  ip6buf[46];
+         ns_printf(pio,"%s ", print_ip6(&con->u_f6host, &ip6buf[0]));
+         ns_printf(pio,"-> %s", print_ip6(&con->u_l6host, &ip6buf[0]));
+      }
+#endif   /* IP_V6 */
+
+   }
+   ns_printf(pio,"\n");
+
+   len = sizeof(sbindlist)/sizeof(unshort);
+   if (len > 1)
+   {
+      ns_printf(pio,"UDP also listens on :");
+      for (i=0; i<len-1; i++)
+         ns_printf(pio," %u ", sbindlist[i]);
+      ns_printf(pio,"\n");
+   }
+   return 0;
+}
+
+#endif   /* NET_STATS */
+
+/* end of file udp.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.c b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.c
new file mode 100644
index 0000000..ef80de1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.c
@@ -0,0 +1,164 @@
+/*
+ * FILENAME: igmp.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains code that is executed for all links
+ * that are configured to run IGMPv1.
+ */
+
+/*
+ * MODULE: IPMC
+ *
+ * ROUTINES: igmpv1_input()
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* This file contains the routines to implement the Internet Group Management
+ * Protocol.(IGMP).
+ *
+ * Copyright (c) 1988 Stephen Deering.
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+ 
+#include "ipport.h"
+
+#if defined (IP_MULTICAST) && defined (IGMP_V1)
+
+#include "tcpport.h"
+
+#include "../tcp/in_pcb.h"
+#include "../tcp/protosw.h"
+
+#include "igmp.h"
+#include "igmp_cmn.h"
+
+/* externs */
+extern ip_addr igmp_all_hosts_group;
+extern u_long igmp_timers_are_running;
+extern struct igmp_stats igmpstats;
+
+/* FUNCTION: igmpv1_input ()
+ * 
+ * This function processes incoming packets for all physical links
+ * that are configured to run IGMPv1.  It is invoked from igmp_input ()
+ * after the packet has passed validation tests.  Incoming packets can 
+ * either be IGMPv1 Host Membership Queries or Reports.  Note that 
+ * IGMP is only used to report membership in IPv4 multicast group
+ * addresses.
+ *
+ * INPUT: Packet to be processed thru' the IGMPv1 state machine(s).
+ *
+ * OUTPUT: This function returns IGMP_ERR if it is passed an "unknown"
+ * packet type.  Otherwise, it returns IGMP_OK.
+ */
+
+int igmpv1_input(PACKET p)
+{
+   struct igmp *  igmp;
+   struct ip *    pip;
+   struct in_multi * inm;
+   NET netp  = p->net;
+   int rc;
+         
+   pip = ip_head (p);
+   igmp = (struct igmp *) (ip_data (pip));
+
+   switch (igmp->igmp_type) 
+   {
+   case IGMP_HOST_MEMBERSHIP_QUERY:
+      ++igmpstats.igmpv1mode_v1_queries_rcvd;
+      /*
+       * Start the timers in all of our membership records for
+       * the interface on which the query arrived, except those
+       * that are already running and those that belong to the
+       * "all-hosts" group.
+       */
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+      {
+         /* skip all IPv6 entries - they are indicated by 
+          * an IPv4 address field of 0 */
+         if (inm->inm_addr == 0)
+            continue;
+         /* skip IPv4 multicast address of 224.0.0.1 (note that
+          * the IPv4 address stored in inm_addr is in network 
+          * byte order */
+         if (inm->inm_addr != igmp_all_hosts_group)
+         {
+            if (inm->inm_timer == 0)
+            {
+               inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr);
+               /* increment the count of running timers */
+               ++igmp_timers_are_running;            
+            }   
+         }
+      }
+      rc = IGMP_OK;
+      break;
+
+   case IGMP_HOST_MEMBERSHIP_REPORT:
+      ++igmpstats.igmpv1mode_v1_reports_rcvd;
+      /*
+       * If we belong to the group being reported and have a 
+       * running timer for that group, stop our timer for that 
+       * group.
+       */
+      inm = lookup_mcast(igmp->igmp_group, netp);
+      if (inm != NULL) 
+      {
+         if (inm->inm_timer > 0)
+         {
+            inm->inm_timer = 0;
+            /* decrement the count of running timers */
+            --igmp_timers_are_running;
+            ++igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer;
+         }
+      }
+      rc = IGMP_OK;
+      break;
+      
+   default:
+      ++igmpstats.igmpv1mode_unknown_pkttype;
+      rc = IGMP_ERR;
+      break;   
+   }
+
+   /* we're done with the received packet; return packet buffer back 
+    * to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      
+   return rc;
+}
+
+#endif   /* IP_MULTICAST and IGMPv1 */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.h b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.h
new file mode 100644
index 0000000..79aff0d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp.h
@@ -0,0 +1,117 @@
+/*
+ * FILENAME: igmp.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: IPMC
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/*
+ * FILENAME: igmp.h
+ *
+ *
+ * Internet Group Management Protocol (IGMP) definitions.
+ *
+ * Copyright (c) 1988 Stephen Deering.
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)igmp.h 8.1 (Berkeley) 6/10/93
+ */
+
+#ifndef IGMP_H
+#define IGMP_H
+
+/* Internet Group Management Protocol (IGMP) definitions. */
+
+#ifdef IP_MULTICAST
+
+/* protocol identifier for IGMP in IP header */
+#define  IGMP_PROT 2
+
+/* IGMP message format.*/
+struct igmp {
+   u_char   igmp_type;  /* version & type of IGMP message  */
+   u_char   igmp_code;  /* unused, should be zero          */
+   u_short  igmp_cksum; /* IP-style checksum               */
+   ip_addr  igmp_group; /* group address being reported    */
+};                      /* (zero for queries)              */
+
+/* message types, incl. version number */
+#define  IGMP_HOST_MEMBERSHIP_QUERY 0x11
+#define  IGMP_HOST_MEMBERSHIP_REPORT 0x12
+
+/* max delay for response to Query message (10 seconds)  */
+#define  IGMP_MAX_HOST_REPORT_DELAY 10
+/* all-hosts multicast address group (224.0.0.1) */ 
+#define  INADDR_ALLHOSTS_GROUP   0xe0000001
+
+/*
+ * Internet Group Management Protocol (IGMP),
+ * implementation-specific definitions.
+ *
+ * Written by Steve Deering, Stanford, May 1988.
+ *
+ * MULTICAST 1.1
+ */
+ 
+/*
+ * Macro to compute a random timer value between 1 and (IGMP_MAX_REPORTING_
+ * DELAY * countdown frequency).  We generate a "random" number by adding
+ * the total number of IP packets received, our primary IP address, and the
+ * multicast address being timed-out.  The 4.3 random() routine really
+ * ought to be available in the kernel!
+ */
+#define IGMP_RANDOM_DELAY(multiaddr) \
+      /* struct in_addr multiaddr; */ \
+      ( (ip_mib.ipInReceives + \
+      ntohl(nets[0]->n_ipaddr) + \
+      ntohl((multiaddr)) \
+      ) \
+      % (IGMP_MAX_HOST_REPORT_DELAY * PR_FASTHZ) + 1 \
+      )
+
+int igmp_init (void);
+int igmp_input (PACKET p);
+void igmp_joingroup (struct in_multi *);
+void igmp_leavegroup (struct in_multi *);
+void igmp_fasttimo (void);
+
+extern ip_addr igmp_all_hosts_group;
+extern u_long igmp_cticks;
+
+#endif   /* IP_MULTICAST */
+
+#endif   /* IGMP_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.c b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.c
new file mode 100644
index 0000000..fcf26ce
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.c
@@ -0,0 +1,431 @@
+/* igmp2.c 
+ *
+ * This file contains code that is executed for all links
+ * that are configured to run IGMPv2.
+ */
+
+#include "ipport.h"
+
+#if defined (IP_MULTICAST) && defined (IGMP_V2)
+
+#include "tcpport.h"
+
+#include "../tcp/in_pcb.h"
+#include "../tcp/protosw.h"
+
+#include "igmp.h"
+#include "igmp_cmn.h"
+#include "igmp2.h"
+
+/* prototypes */
+int igmpv2_input (PACKET p);
+int igmpv2_process_report (PACKET p);
+int igmpv2_process_query (PACKET p);
+void igmpv2_chk_set_timer (struct in_multi * inm, u_short max_resp_time);
+#ifdef IGMPv2_CHK_RTR_ALERT_OPT
+u_char igmpv2_chk4_rtr_alert_opt (struct ip * pip);
+#endif
+
+/* externs */
+extern ip_addr igmp_all_hosts_group;
+extern ip_addr igmp_all_rtrs_group;
+extern u_long igmp_timers_are_running;
+extern struct igmp_stats igmpstats;
+
+
+/* FUNCTION: igmpv2_input ()
+ * 
+ * This function processes incoming packets for all physical links
+ * that are configured to run IGMPv2.  It is invoked from igmp_input ()
+ * after the packet has passed validation tests.  The received
+ * packet can be any of the following types - IGMPv1 Host Membership 
+ * Query, IGMPv1 Host Membership Report, IGMPv2 Membership Query,
+ * IGMPv2 Membership Report, or IGMPv2 Leave Group.  Note that 
+ * IGMP is only used to report membership in IPv4 multicast group
+ * addresses.
+ *
+ * INPUT: Packet to be processed thru' the IGMPv2 state machine(s).
+ *
+ * OUTPUT: This function can return any of the following three values:
+ * (1) return code from igmpv2_process_query (), (2) return code
+ * from igmpv2_process_report (), IGMP_OK (for a received Leave Group
+ * message only), or IGMP_ERR (for a message of an "unknown" type).
+ */
+
+int igmpv2_input (PACKET p)
+{
+   struct igmp * igmp;
+   struct ip * pip;
+   u_char type;
+   int rc;
+
+   pip = ip_head (p);    
+   igmp = (struct igmp *) (ip_data (pip));   
+   /* extract the IGMP packet type from received packet */
+   type = igmp->igmp_type;
+
+   switch (type) 
+   {
+      case IGMP_HOST_MEMBERSHIP_QUERY:
+         rc = igmpv2_process_query (p);
+         break;
+
+      case IGMP_HOST_MEMBERSHIP_REPORT:
+      case IGMPv2_MEMBERSHIP_REPORT:
+         rc = igmpv2_process_report (p);
+         break;
+         
+      case IGMPv2_LEAVE_GROUP:
+         /* Leave messages are typically addressed to the all-routers 
+          * multicast address group (224.0.0.2).  We do not implement 
+          * multicast router functionality, and therefore, do not 
+          * expect to receive such messages.  However, according to
+          * RFC 2236, some implementations of an older version of the 
+          * IGMPv2 specification send leave messages to the group 
+          * being left.  If we do receive such a message, we will 
+          * drop it. */       
+         ++igmpstats.igmpv2mode_v2_leave_msgs_rcvd;
+         rc = IGMP_OK;
+         break;               
+
+      default:     
+         ++igmpstats.igmpv2mode_unknown_pkttype;
+         rc = IGMP_ERR;         
+         break;
+   } /* end SWITCH */
+
+   /* we're done processing the received packet; return packet buffer 
+    * back to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   
+   return rc;
+}
+
+
+/* FUNCTION: igmpv2_process_report ()
+ * 
+ * This function processes a received packet that is either an 
+ * IGMPv1 Host Membership Report or a IGMPv2 Membership Report.
+ *
+ * INPUT: Report packet to be processed thru' the IGMPv2 state 
+ * machine for a group whose membership is being reported.
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+
+int igmpv2_process_report (PACKET p)
+{
+   struct igmp * igmp;
+   struct ip * pip;
+   NET netp;
+   struct in_multi * inm;
+
+   netp = p->net;
+   pip = ip_head (p);
+   igmp = (struct igmp *) (ip_data (pip));   
+   
+   /* If we receive a IGMP (v1 or v2) report for a multicast group 
+    * that we have a timer running for, the IGMPv2 specification 
+    * requires that we stop the timer (and thereby cancel the 
+    * future transmission of our report).
+    
+    * However, we will use the following table to guide our actions
+    * instead.  Scenario #4 causes us to not cancel the timer, 
+    * since we have received a IGMPv2 report, but we believe that 
+    * the querier on the network is running IGMPv1, and therefore 
+    * will not be able to understand the IGMPv2 report.  As a 
+    * result, we let our timer run, and if it expires, we will 
+    * send out a report.
+
+    * The type of a received report can be determined by examining 
+    * the first byte of the IGMP message.  This byte is 0x12 for a 
+    * IGMPv1 Host Membership Report, and 0x16 for a Version 2 
+    * Membership Report.
+    
+    * Scenario# igmpv1_rtr_present Type of rcvd report Cancel timer
+    * =============================================================
+    * 1         No                 IGMPv1              Yes 
+    * 2         No                 IGMPv2              Yes
+    * 3         Yes                IGMPv1              Yes
+    * 4         Yes                IGMPv2              No
+
+    * In scenario #1 and #2, we have a IGMPv2-capable router that 
+    * can understand both IGMPv1 and IGMPv2 reports.  In scenario 
+    * #3, we have a IGMPv1-capable router that can understand IGMPv1 
+    * reports. In scenario #4, we have a IGMPv1-capable router that
+    * cannot understand a IGMPv2 report.  It is possible that the 
+    * IGMPv1-capable router in scenario #4 is also capable of 
+    * processing IGMPv2 packets (it has "downgraded" itself because
+    * there are IGMPv1 routers on that network); however, we do not
+    * know that, and hence we don't cancel our timer (for the 
+    * subsequent transmission of a IGMPv1 report).
+    */
+   inm = lookup_mcast(igmp->igmp_group, netp);
+   if (inm != NULL) 
+   {
+      if (inm->inm_timer != 0)
+      {
+         /* we have a timer running */
+         if (!(netp->igmpv1_rtr_present && 
+             igmp->igmp_type == IGMPv2_MEMBERSHIP_REPORT))
+         {
+            /* cancel timer */
+            inm->inm_timer = 0;
+            /* decrement the count of running timers */
+            --igmp_timers_are_running;
+            /* indicate that we are not the last host to send a 
+             * report for this group */
+            inm->last2send_report = IGMP_FALSE;
+            ++igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer;
+         }
+      }
+      else
+      {
+         /* we don't have a timer running; perhaps the source
+          * host has just joined the group, and has sent an
+          * unsolicited report */
+         ++igmpstats.igmpv2mode_v12_reports_rcvd_no_timer;   
+      }
+   }
+   else 
+   {
+      /* since the Reports are sent the group address, we should
+       * never receive them unless we are a member of that group
+       * on that interface.  Even if imperfect filtering at the 
+       * device level causes reports for unregistered groups to 
+       * be passed up to the IP module, ip_rcv_phase2 () is 
+       * responsible for dropping them, and so we should never
+       * receive such packets. */
+      ++igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd;
+   }
+   
+   return IGMP_OK;   
+}
+
+
+/* FUNCTION: igmpv2_process_query ()
+ * 
+ * This function processes a received packet that is either an 
+ * IGMPv1 Host Membership Query, or an IGMPv2 General Query,
+ * or an IGMPv2 Group-Specific Query.  IGMPv1 Host Membership 
+ * Query and IGMPv2 General Query require processing thru' all
+ * of the IGMPv2 state machines on a link.  The IGMPv2 Group-
+ * Specific Query only requires processing thru' the IGMPv2
+ * state machine for the group that is being queried.
+ *
+ * INPUT: Query packet to be processed thru' the IGMPv2 state 
+ * machine(s).
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+
+int igmpv2_process_query (PACKET p)
+{
+   struct igmp * igmp;
+   struct ip * pip;
+   NET netp;
+   u_short max_resp_time;
+   u_char process_all;
+   struct in_multi * inm;
+
+   netp = p->net;
+   pip = ip_head (p);
+   igmp = (struct igmp *) (ip_data (pip));
+
+   if (igmp->igmp_code == 0)
+   {
+      /* this is a IGMPv1 Host Membership Query */
+      netp->igmpv1_rtr_present = IGMP_TRUE;
+      netp->igmpv1_query_rcvd_time = cticks;      
+      ++igmpstats.igmpv2mode_v1_queries_rcvd;
+      /* set maximum time to respond to the equivalent of 10 
+       * seconds worth of "ticks" (the timeout routine is
+       * intended to be invoked PR_FASTHZ (5) times a second,
+       * so each tick is equal to 200 ms) */
+      max_resp_time = IGMP_MAX_HOST_REPORT_DELAY * PR_FASTHZ;
+      process_all = IGMP_TRUE;
+   }
+   else
+   {
+      /* this is either a IGMPv2 General Query or 
+       * a IGMPv2 Group-Specific Query */
+      if (igmp->igmp_group == 0)
+      {
+         /* this is a IGMPv2 General Query */
+         ++igmpstats.igmpv2mode_v2_general_queries_rcvd;
+         process_all = IGMP_TRUE;
+      }
+      else
+      {
+         /* this is a IGMPv2 Group-Specific Query */       
+         ++igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd;
+         process_all = IGMP_FALSE;
+      }
+      
+      /* irrespective of whether received message is a 
+       * IGMPv2 General Query or a IGMPv2 Group-Specific Query,
+       * set maximum time to respond to value extracted 
+       * from received message. The value in the message
+       * is in tenths of a second.  max_resp_time is in
+       * units of ticks (where one tick is 200 ms) */
+      max_resp_time = (igmp->igmp_code * PR_FASTHZ) / 10;
+   }
+   
+   /* process all entries in a link's multicast address linked
+    * list (pointed to by mc_list) as part of the response to
+    * the received IGMPv1 Host Membership Query or IGMPv2 General
+    * Query message */
+   if (process_all)
+   {
+      for (inm = netp->mc_list; inm; inm = inm->inm_next)
+      {
+         /* skip all IPv6 entries - they are indicated by 
+          * an IPv4 address field of 0 */
+         if (!(inm->inm_addr)) continue;
+         /* skip IPv4 multicast address of 224.0.0.1 (note that
+          * the IPv4 address stored in inm_addr is in network 
+          * byte order */
+         if (inm->inm_addr != igmp_all_hosts_group)
+            igmpv2_chk_set_timer (inm, max_resp_time);
+      } /* end FOR (iterate thru' mc_list on net) */
+   } /* end IF (process all) */
+   else
+   {
+      /* process one (for IGMPv2 Group-Specific Query) entry (the 
+       * one that corresponds to the address listed in the received 
+       * query) - it should be present in the link's multicast
+       * address list */
+      inm = lookup_mcast(igmp->igmp_group, netp);
+      if (inm != NULL)
+         igmpv2_chk_set_timer (inm, max_resp_time);
+      else ++igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd;
+   } /* end ELSE (process ALL) */
+   
+   /* return success; caller will the received packet back to the 
+    * free pool */
+   return IGMP_OK;
+}
+
+
+/* FUNCTION: igmpv2_chk_set_timer ()
+ * 
+ * This function checks to see if a timer needs to be
+ * (re)started in response to a received Query message.
+ * Unlike IGMPv1, IGMPv2 requires that a running timer be
+ * restarted if the remaining time on the timer is greater
+ * than the Max Response Time specified in the IGMPv2
+ * General Query/Group-Specific Query message or 10
+ * seconds for a IGMPv1 Host Membership Query message.
+ *
+ * INPUT: (1) Multicast address data structure that is being
+ *            processed in igmpv2_process_query ().
+ *        (2) Max Response Time (either extracted from the
+ *            received IGMPv2 Query message, or 10 seconds
+ *            for an IGMPv1 Query message), expressed in
+ *            200 ms tick units.
+ *
+ * OUTPUT: None.
+ */
+
+void igmpv2_chk_set_timer (struct in_multi * inm, u_short max_resp_time)
+{  
+   
+   /* restart a timer if this entry already has a timer running
+    * but the scheduled expiry is later than what the router
+    * router has indicated in the just received Query message.
+    * Or, if a timer is not running at all, we start one.
+
+    * Otherwise, the current timer for this group is scheduled 
+    * to expire within the duration indicated in the Query 
+    * message, so we let it continue. 
+    */
+   if ((inm->inm_timer > max_resp_time) ||
+       (inm->inm_timer == 0))
+   {
+      if (inm->inm_timer == 0) ++igmp_timers_are_running;
+      inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY (max_resp_time, inm->inm_addr);                     
+   }
+
+   return;
+}
+
+
+/* FUNCTION: igmpv2_chk4_rtr_alert_opt ()
+ * 
+ * This function checks for the presence of the IP Router
+ * Alert option in the received IGMPv2 packet.  It is
+ * invoked from igmp_validate () (which, in turn, is
+ * invoked from igmp_input ()) to validate the received
+ * packet before it is fed into the IGMP state machine(s).
+ *
+ * INPUT: (1) Pointer to the start of the IP header of
+ *            the received packet.
+ *
+ * OUTPUT: This function returns IGMP_TRUE if it finds
+ *         the IP Router Alert option in the received
+ *         packet, and IGMP_FALSE otherwise.
+ */
+
+u_char igmpv2_chk4_rtr_alert_opt (struct ip * pip)
+{
+   u_char * optp;
+   u_long * rtr_alert_optp;
+   u_char total_optlen;
+   u_char optlen;
+   u_char optval;
+
+   total_optlen = ip_hlen (pip) - sizeof (struct ip);
+
+   if (total_optlen > 0)
+   {
+      /* point to just past the end of the IP header */
+      optp = (u_char *) (pip + 1);
+  
+      while (total_optlen > 0)
+      {
+         /* only the lowermost 5 bits are significant */    
+         optval = (*optp) & IPOPT_TYPE_MASK;
+         switch (optval)
+         {
+            case EOL_OPT:
+               /* we've encountered the End of Option List option, 
+                * and so setting optlen isn't necessary */
+               optlen = 1;
+               /* we're done - we couldn't locate the IP Router Alert 
+                * option in this IP header */
+               return IGMP_FALSE;
+         
+            case NOOP_OPT:
+               /* skip past the one byte of the No Operation option */
+               optlen = 1;
+               break;
+         
+            case IP_RTR_ALERT_OPT:
+               rtr_alert_optp = (u_long *) optp; 
+               if ((ntohl (*rtr_alert_optp)) == IP_RTR_ALERT_OPT_DATA)
+                  /* found the option, return success */
+                  return IGMP_TRUE;
+               else return IGMP_FALSE;
+          
+            default:
+               /* extract the length of the current option, and compute
+                * the total length of this option */
+               optlen = (*(optp + 1)) + 2;
+               break;
+         }
+         
+         /* skip past the bytes associated with the current option to 
+          * point to the next option. */
+         optp += optlen;
+         total_optlen -= optlen;
+      } /* end WHILE */
+   }
+
+   /* didn't find IP Alert option in IP header of rcvd packet */
+   return IGMP_FALSE;
+}
+
+#endif /* IP_MULTICAST and IGMPv2 */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.h b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.h
new file mode 100644
index 0000000..e1316ee
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp2.h
@@ -0,0 +1,39 @@
+/* igmp2.h
+ *
+ * Companion header file for igmp2.c.
+ */
+
+#ifndef IGMP2_H
+#define IGMP2_H
+
+#ifdef IP_MULTICAST
+
+/* IGMPv2 message types */
+#define  IGMPv2_MEMBERSHIP_REPORT      0x16
+#define  IGMPv2_LEAVE_GROUP            0x17
+
+/* compute a random delay; the first parameter is the Maximum
+ * Response Time (expressed in units of 200 ms ticks) extracted 
+ * from the received Query packet 
+ */
+#define IGMPv2_RANDOM_DELAY(mrt,multiaddr) \
+   ( \
+    (ip_mib.ipInReceives + ntohl(nets[0]->n_ipaddr) + ntohl((multiaddr))) \
+    % mrt + 1 \
+   )
+
+/* Version 1 Router Present Timeout (400 seconds) */
+#define IGMPv1_RTR_PRESENT_TMO 400
+
+/* all-routers multicast group address (224.0.0.2) */
+#define INADDR_ALLRTRS_GROUP 0xe0000002
+
+/* maximum delay when setting a timer for a subsequent 
+ * transmission of an unsolicited IGMPv2 Membership
+ * Report. */
+#define UNSOLIC_RPT_INTERVAL 10 /* 10 seconds */
+
+#endif /* IGMP2_H */
+
+#endif /* IP_MULTICAST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.c b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.c
new file mode 100644
index 0000000..71c7733
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.c
@@ -0,0 +1,747 @@
+/* igmp_cmn.c 
+ *
+ * This file contains all of the code that is common to IGMPv1 
+ * and IGMPv2 protocol implementations.
+ */
+
+#include "ipport.h"
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+
+#include "tcpport.h"
+
+#include "../tcp/in_pcb.h"
+#include "../tcp/protosw.h"
+
+#include "igmp.h"
+#include "igmp2.h"
+#include "igmp_cmn.h"
+
+/* number of running IGMP timers at any given instant */
+u_long igmp_timers_are_running = 0;
+/* time in ticks for the next invocation of IGMP timeout routine */
+u_long igmp_cticks = 0;
+/* IGMPv1 and v2 statistics data structure */
+struct igmp_stats igmpstats;
+/* IP address for all-hosts multicast address group (224.0.0.1) */
+ip_addr igmp_all_hosts_group;
+/* IP address for all-routers multicast address group (224.0.0.2) */
+ip_addr igmp_all_rtrs_group;
+
+/* prototypes */
+void igmp_send (u_char type, struct in_multi * inm);
+int igmp_validate (PACKET p);
+int igmp_print_stats (void * pio);
+void rip_input(PACKET p);
+
+/* externs */
+extern int igmpv1_input (PACKET p);
+extern int igmpv2_input (PACKET p);
+#ifdef IGMP_V2
+extern u_char igmpv2_chk4_rtr_alert_opt (struct ip * pip);
+#endif
+
+
+/* FUNCTION: igmp_init ()
+ * 
+ * This function initializes the IGMP module.  It sets
+ * up each link to operate in the appropriate mode
+ * (IGMPv1 or IGMPv2).  It also initializes the count
+ * of running IGMP timers.  (A IGMP timer is defined
+ * as running of the inm_timer field of the owning 
+ * multicast address data structure) is greater than zero.)  
+ * It also sets up the IGMP timeout routine (igmp_fasttimo ())
+ * to be invoked once every 200 ms.
+ *
+ * INPUT: None.
+ *
+ * OUTPUT: None.
+ */
+
+int igmp_init(void)
+{
+   NET ifp;
+
+   /*
+    * To avoid byte-swapping the same value over and over again.
+    */
+   igmp_all_hosts_group = htonl(INADDR_ALLHOSTS_GROUP);
+   igmp_all_rtrs_group = htonl(INADDR_ALLRTRS_GROUP);
+
+   /* note that the IGMP operational mode configuration for a
+    * given link (i.e., whether it should run IGMPv1 or IGMPv2)
+    * has already been validated, so no additional checks are 
+    * required here. 
+    */
+   for (ifp = (NET) netlist.q_head; ifp; ifp = ifp->n_next)
+   {
+      if (ifp->igmp_oper_mode == IGMP_MODE_V1)
+      {
+         ifp->igmpv1_rtr_present = 1;
+      }
+      else
+      {
+         ifp->igmpv1_rtr_present = 0;
+         /* not really required, only referred to if IGMPv1 router is 
+          * "present" */
+         ifp->igmpv1_query_rcvd_time = 0;
+      }
+   }
+
+   /*
+    * Call igmp_fasttimo PR_FASTHZ (5) times per second
+    */
+   igmp_cticks = cticks + TPS/PR_FASTHZ;
+
+   /* there are no timers running initially */
+   igmp_timers_are_running = 0;
+
+   return IGMP_OK;
+}
+
+
+/* FUNCTION: igmp_input ()
+ * 
+ * This function is invoked by igmp_demux () to provide a
+ * received IGMP packet to the IGMP module.  It first
+ * validates the received packet via igmp_validate ().
+ * If the validation succeeds, this function then hands
+ * off the packet to the IGMPv1 or IGMPv2 protocol
+ * modules for further processing.  The decision of which
+ * protocol module to hand the packet off to is determined
+ * by the operating mode that is configured for that link.
+ *
+ * The IGMPv1 and IGMPv2 protocol modules are responsible
+ * for returning the received packet buffer back to the
+ * free pool (after they have processed the packet).
+ *
+ * INPUT: Received packet.
+ *
+ * OUTPUT: This function can return any one of the following
+ * four values: (1) return code from igmp_validate (), (2) 
+ * return code from igmpv1_input (), (3) return code from 
+ * igmpv2_input (), or (4) IGMP_ERR.  The latter value is 
+ * returned if the operating mode is not correctly configured
+ * to a valid IGMP operating mode.
+ */
+
+int igmp_input (PACKET p)
+{
+   u_char mode;
+   int rc;
+     
+   ++igmpstats.igmp_total_rcvd;
+   
+   /* validate the received packet; if validation fails,
+    * drop the packet and return */
+   if ((rc = igmp_validate (p)) != IGMP_OK) goto end;
+
+   /* determine the operating mode for IGMP on the ingress link */
+   mode = p->net->igmp_oper_mode;
+   
+   /* feed packet to IGMPv1 or IGMPv2 code based on the operating
+    * mode of the ingress link */
+   switch (mode)
+   {
+#ifdef IGMP_V1   
+      case IGMP_MODE_V1:   
+         return (igmpv1_input (p)); 
+#endif
+#ifdef IGMP_V2         
+      case IGMP_MODE_V2:       
+         return (igmpv2_input (p));
+#endif
+      default:
+         ++igmpstats.igmp_bad_oper_mode;     
+         rc = IGMP_ERR;
+         break;
+   }
+   
+end:   
+   /* return packet buffer back to free pool */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      
+   return rc;
+}
+
+
+/* FUNCTION: igmp_fasttimo ()
+ * 
+ * This function is invoked by inet_timer () to periodically 
+ * service the IGMPv1 and IGMPv2 modules.  It traverses thru'
+ * all of the interfaces in a system, and decrements all
+ * running timers.  (A IGMP timer is defined as running if 
+ * the inm_timer field of the owning multicast address data 
+ * structure) is greater than zero.)  If the decremented timer 
+ * reaches zero, this function sends out a IGMP report for 
+ * the relevant multicast group.
+ * 
+ * If the link is running in IGMPv2 mode and also has a 
+ * v1 router "present", this function checks to determine
+ * if it has heard from the router in the last IGMPv1_RTR_PRESENT_TMO 
+ * seconds.  If it hasn't, the v1 router is marked "absent".
+ * Subsequent query requests from the v1 router will again
+ * lead the v1 router to be marked as present on the link.
+ *
+ * Once a timer has expired, this function decrements the
+ * count of running timers by one.  This function also sets
+ * up the tick counter for its next invocation (by inet_timer ())
+ * (which is 200 ms into the future). 
+ *
+ * INPUT: None.
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_fasttimo (void)
+{
+   struct in_multi * inm;
+   NET ifp;
+     
+   LOCK_NET_RESOURCE (NET_RESID);
+   
+   /*
+    * Quick check to see if any work needs to be done, in order
+    * to minimize the overhead of fasttimo processing.
+    */
+   if (!igmp_timers_are_running)
+   {
+      UNLOCK_NET_RESOURCE (NET_RESID);
+      return;
+   }
+
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+   {
+      for (inm = ifp->mc_list; inm; inm = inm->inm_next)
+      {
+         /* skip IPv6 entries */
+         if (inm->inm_addr == 0) 
+               continue;
+
+         if (inm->inm_timer == 0)   /* timer not set */
+         {
+            /* do nothing */
+         }
+         else if (--inm->inm_timer == 0)  /* timer expired */
+         {
+            /* send membership report in appropriate format */
+            if (ifp->igmpv1_rtr_present)
+            {
+               /* always true for IGMPv1, may be true for IGMPv2 */
+               igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm);
+            }
+            else
+            {
+               igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm);
+            }
+
+            /* for IGMPv2, indicate that we were the last to send 
+             * a Report for this multicast group (relevant for 
+             * IGMPv2 only).  also check to see if we should mark 
+             * the IGMPv1 router as "absent". */
+            if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+            {
+               inm->last2send_report = IGMP_TRUE;
+               
+               if (ifp->igmpv1_rtr_present)
+               {
+                  if (cticks > (ifp->igmpv1_query_rcvd_time + (IGMPv1_RTR_PRESENT_TMO * TPS)))
+                  {
+                     /* we haven't heard from the IGMPv1 router for a duration
+                      * greater than or equal to Version 1 Router Present Timeout 
+                      * (400 seconds), and will now update the igmpv1_rtr_present 
+                      * variable to reflect that.
+                      */
+                     ifp->igmpv1_rtr_present = IGMP_FALSE;
+                     ifp->igmpv1_query_rcvd_time = 0;
+                  }
+               }  
+            }
+
+            /* decrement the count of running IGMP timers */
+            --igmp_timers_are_running;
+         }
+         else
+         {
+            /* timer is still counting down */
+         }
+      }     
+   }
+
+   /* Setup time for the next call into igmp_fasttimo ()
+    * (200 ms later). */
+   igmp_cticks = cticks + TPS/PR_FASTHZ;
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+   
+   return;
+}
+
+/* FUNCTION: igmp_send ()
+ * 
+ * This function is used by the IGMPv1 and IGMPv2 protocol modules
+ * to create and transmit a packet of a particular type.  IGMPv2
+ * Membership Reports and Leave Group messages have the IP Router
+ * Alert option appended to them.
+ *
+ * IGMPv2 Leave Group messages are addressed to the all-routers
+ * multicast group; all other messages are addressed to the
+ * relevant group itself.  The egress interface for the message
+ * is the interface on which the multicast group address data
+ * structure resides.
+ *
+ * When sending a packet that requires options in the IP header,
+ * this function invokes ip_write2 () to transmit the outgoing
+ * packet.  The third parameter to ip_write2 () is a list of
+ * IP options.  The list is terminated by the EOL option.  If
+ * the list of IP options only contains the EOL option, the
+ * ip_write2 () function does not include any options in the
+ * outgoing packet.  (Note that the stack does not "fully" 
+ * support IP options.)
+ *
+ * INPUT: (1) Type of IGMP packet to be transmitted
+ *        (2) Pointer to multicast group address structure for
+ *            which IGMP message is being sent
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_send (u_char type, struct in_multi * inm)
+{
+   PACKET p;
+   struct igmp * igmp;
+   struct ip_moptions * imop;
+   struct ip_moptions simo;
+   struct ip * pip;
+   u_char * tmpp;
+   u_char opts [2] = {IP_RTR_ALERT_OPT, EOL_OPT};
+   u_char * optp;
+   u_char reqd_len;
+
+   /* compute length of buffer required for outgoing packet.
+    * also account for the length of the IP Router Alert 
+    * option, if required. */   
+   reqd_len = MaxLnh + sizeof (struct ip) + sizeof (struct igmp);
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      reqd_len += IP_RTR_ALERT_OPT_SIZE;
+   }
+
+   /* obtain a packet to send the IGMP message */
+   LOCK_NET_RESOURCE (FREEQ_RESID);
+   p = pk_alloc (reqd_len);
+   UNLOCK_NET_RESOURCE (FREEQ_RESID);
+   
+   /* log an error and return if the allocation fails */   
+   if (!p)
+   {
+      ++igmpstats.igmp_pkt_alloc_fail;
+      return;
+   }
+
+   /* Need to fill in the source and destination ip addresses */
+   pip = (struct ip *) p->nb_prot;
+   pip->ip_src = inm->inm_netp->n_ipaddr;
+   /* Leave Group messages are sent to the all-routers multicast group */
+   if (type == IGMPv2_LEAVE_GROUP)
+   {
+      /* igmp_all_rtrs_group is already in network byte order */
+      pip->ip_dest = igmp_all_rtrs_group;
+   }
+   else
+      pip->ip_dest = inm->inm_addr;
+   
+   p->fhost = pip->ip_dest;
+
+   tmpp = (((u_char *) p->nb_prot) + sizeof (struct ip));
+
+   /* when transmitting an IGMP packet, our IGMP module will insert
+    * data for the Router Alert option in the following types of
+    * packets: Version 2 Membership Report (0x16) and Leave Group 
+    * (0x17) */
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      /* provide space for ip_write2 () to write option-related data */
+      tmpp += IP_RTR_ALERT_OPT_SIZE;
+      optp = &(opts [0]); /* one option (IP Router Alert) */
+   }
+   /* outgoing packet does not require any options */
+   else 
+      optp = &(opts [1]);
+   /* point to the start of the IGMP header */
+   igmp = (struct igmp *) tmpp;
+   
+   igmp->igmp_type = type;
+   igmp->igmp_code = 0;
+   
+   /* all messages (Report or Leave) have Group Address field 
+    * set to the group being reported or left */
+   igmp->igmp_group = inm->inm_addr;
+   igmp->igmp_cksum = 0;
+   igmp->igmp_cksum = ~cksum((void*)igmp, IGMP_MINLEN>>1);
+
+   imop = &simo;
+   MEMSET(imop, 0, sizeof(simo));
+   imop->imo_multicast_netp = inm->inm_netp;
+   imop->imo_multicast_ttl = 1;
+   /* we do not want our own reports to be looped back */
+   imop->imo_multicast_loop = 0;
+
+   /* set nb_prot to point to the beginning of the IGMP data,
+    * and nb_plen to the length of the IGMP data, and attach
+    * the multicast options structure to the outgoing packet */
+   p->nb_prot = (char *) tmpp;
+   p->nb_plen = sizeof(struct igmp);
+   p->imo = imop;
+   
+   ip_write2 (IGMP_PROT, p, optp);
+
+   if (type == IGMPv2_LEAVE_GROUP)
+      ++igmpstats.igmpv2mode_v2_leave_msgs_sent;
+   else if (type == IGMPv2_MEMBERSHIP_REPORT)
+      ++igmpstats.igmpv2mode_v2_reports_sent;
+   else if (type == IGMP_HOST_MEMBERSHIP_REPORT)
+      ++igmpstats.igmp_v1_reports_sent;
+}
+
+
+/* FUNCTION: igmp_joingroup ()
+ * 
+ * This function is used to send the first IGMP Membership Report
+ * (IGMPv1 or IGMPv2, as appropriate) for a group on the device.
+ * Membership in the 224.0.0.1 group is not reported.  After
+ * sending the report, this function also starts a timer that will
+ * trigger a second transmission of the report (unless it is
+ * supressed by a received report).
+ *
+ * INPUT: (1) Pointer to multicast group address structure for
+ *            which IGMP Membership Report message is being sent
+ *
+ * OUTPUT: None.
+ */
+ 
+void igmp_joingroup(struct in_multi * inm)
+{
+   NET ifp;
+
+   /* extract the network interface to which this multicast
+    * address is "attached" */
+   ifp = inm->inm_netp;
+
+   if (inm->inm_addr == igmp_all_hosts_group)
+   {
+      inm->inm_timer = 0;
+   }
+   else 
+   {
+      /* send unsolicited membership report in appropriate format */
+      if (ifp->igmpv1_rtr_present)
+      {
+         /* always true for IGMPv1, may be true for IGMPv2 */
+         igmp_send (IGMP_HOST_MEMBERSHIP_REPORT, inm);
+         /* set a delay timer (with a duration of 
+          * IGMP_MAX_HOST_REPORT_DELAY) for a second unsolicited report */
+         inm->inm_timer = (unsigned) IGMP_RANDOM_DELAY(inm->inm_addr);
+      }
+      else
+      {
+         igmp_send (IGMPv2_MEMBERSHIP_REPORT, inm);
+         /* the delay time duration is the Unsolicited Report Interval */
+         inm->inm_timer = (unsigned) IGMPv2_RANDOM_DELAY ((UNSOLIC_RPT_INTERVAL * PR_FASTHZ), inm->inm_addr);
+      }
+      
+      /* for IGMPv2, indicate that we were the last to send 
+       * a Report for this multicast group (relevant for 
+       * IGMPv2 only). */
+      if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+      {
+         inm->last2send_report = IGMP_TRUE;
+      }
+
+      ++igmp_timers_are_running;
+   }
+   
+   return;
+}     
+
+
+/* FUNCTION: igmp_leavegroup ()
+ * 
+ * This function is used to send the IGMPv2 Leave Group message.
+ * for a group on the device.  This occurs when the reference
+ * count for a group's membership becomes zero.  This function
+ * will only send a Leave Group message when the link (on which
+ * the multicast address group structure resides) is configured 
+ * for IGMPv2 operation and has not been downgraded to IGMPv1
+ * (because of the presence of a IGMPv1 router on the link).
+ *
+ * It is possible that we skip sending a Leave Group message 
+ * even though we are the only member of a group.  Consider
+ * the case where the host that last responded to a query has since
+ * then left the group.  If we decide to leave immediately after
+ * that, we will skip sending the leave message.  In such a
+ * scenario, the Group Membership Interval timer in the IGMP
+ * router will help the router determine when there are no
+ * members of the group on that link.
+ *
+ * INPUT: (1) Pointer to multicast group address structure for
+ *            which IGMPv2 Leave Group message is being sent.
+ *
+ * OUTPUT: None.
+ */
+
+void igmp_leavegroup (struct in_multi * inm)
+{
+   NET ifp;
+
+   ifp = inm->inm_netp;
+
+   if ((ifp->igmp_oper_mode == IGMP_MODE_V2) && 
+       !ifp->igmpv1_rtr_present)
+   {
+      if (inm->last2send_report == IGMP_TRUE)
+         igmp_send (IGMPv2_LEAVE_GROUP, inm);
+   }
+   
+   return;
+}
+
+
+/* FUNCTION: igmp_validate ()
+ * 
+ * This function is used to validate the contents of a 
+ * received packet.  It performs the following tests on
+ * a received message.
+ *
+ * (a) validate the length of IGMP message
+ * (b) validate the checksum
+ * (c) validate that an IGMPv1 Host Membership Query or an  
+ *     IGMPv2 General Query is sent to the all hosts-address
+ * (d) validate that IGMPv2 Group-Specific Query carries
+ *     a valid multicast group address, and is not addressed
+ *     to 224.0.0.1 multicast group
+ * (e) validate that the Group Address field in a received 
+ *     IGMP Membership Report is identical to the destination
+ *     address field in the IP header, and that the group
+ *     address is a valid multicast group address
+ * (f) validate that a received IGMPv2 General Query, IGMPv2 
+ *     Group-Specific Query, IGMPv2 Membership Report, and 
+ *     IGMPv2 Leave Group message includes the IP Router
+ *     Alert option.
+ *
+ * Note.  This function does not free the packet even if
+ * the validation fails.
+ *
+ * INPUT: (1) Received IGMP packet.
+ *
+ * OUTPUT: This function returns ENP_BAD_HEADER if the
+ *         validation fails; otherwise, it returns
+ *         IGMP_OK.
+ */
+
+int igmp_validate (PACKET p)
+{
+   struct ip * pip;
+   int igmplen;
+   struct igmp * igmp;
+   u_short osum;
+   u_short xsum;  
+   u_char type;
+   ip_addr mcgrp_addr;
+   u_char resp_time;
+
+   pip = ip_head (p);
+
+   /* compute length of IGMP packet (after accounting for IP header, 
+    * including the IP Router Alert option (if present)) */
+   igmplen = p->nb_plen - ip_hlen (pip);
+
+   /* validate length (IGMP_MINLEN is 8 bytes) */
+   if (igmplen != IGMP_MINLEN) 
+   {
+      ++igmpstats.igmp_badlen_rcvd;
+      return ENP_BAD_HEADER;
+   }
+
+   /* validate checksum */
+   igmp = (struct igmp *) (ip_data (pip));
+   osum = igmp->igmp_cksum;
+   igmp->igmp_cksum = 0;
+   xsum = ~cksum(igmp, igmplen>>1);
+   if (xsum != osum)
+   {
+      igmp->igmp_cksum = osum;
+      ++igmpstats.igmp_badsum_rcvd;
+      return ENP_BAD_HEADER;
+   }
+   
+   /* extract the IGMP packet type, Group Address, and Max Response Time 
+    * (unused for IGMPv1) fields from received packet */
+   type = igmp->igmp_type;
+   mcgrp_addr = ntohl(igmp->igmp_group); 
+   resp_time = igmp->igmp_code;
+      
+   if (type == IGMP_HOST_MEMBERSHIP_QUERY)
+   {
+      if ((resp_time == 0) || /* IGMPv1 Query */
+          ((resp_time > 0) && (mcgrp_addr == 0))) /* IGMPv2 General Query */     
+      {
+         /* if this is a IGMPv1 Host Membership Query or a IGMPv2 
+          * General Query, it must be addressed to the all-hosts 
+          * group */
+         if (pip->ip_dest != igmp_all_hosts_group) 
+         {
+            ++igmpstats.igmp_bad_queries_rcvd;
+            return ENP_BAD_HEADER;
+         }     
+      }
+      
+      if ((resp_time > 0) && (mcgrp_addr != 0))
+      {
+         /* this is a IGMPv2 Group-Specific Query. */
+         if (p->net->igmp_oper_mode == IGMP_MODE_V1)
+         {
+            /* IGMPv1 code does not understand a IGMPv2 Group-
+             * Specific Query */
+            return ENP_BAD_HEADER; 
+         }
+         
+         /* check to make sure that the group address field carries
+          * a valid multicast address; if it doesn't, we
+          * drop the packet.  Also drop packets that
+          * carry the multicast address for the all-hosts
+          * group. */
+         if ((!IN_MULTICAST(mcgrp_addr)) ||
+             /* igmp_all_hosts_group is already in network byte order */
+             (igmp->igmp_group == igmp_all_hosts_group))
+         {
+            ++igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd;
+            /* caller will free received packet */
+            return ENP_BAD_HEADER;
+         }   
+      }      
+   }         
+   
+   /* check to ensure that a received IGMPv1 or v2 Report has the 
+    * same IP host group address in its IP destination field and 
+    * its IGMP group address field, and that the group address is
+    * a valid multicast address */
+   if ((type == IGMP_HOST_MEMBERSHIP_REPORT) ||
+       (type == IGMPv2_MEMBERSHIP_REPORT))
+   {
+      if ((igmp->igmp_group != pip->ip_dest) ||
+          (!IN_MULTICAST(mcgrp_addr)))
+      {
+         ++igmpstats.igmp_bad_reports_rcvd;
+         return ENP_BAD_HEADER;    
+      }
+   }      
+
+   /*
+    * After receiving an IGMP packet, our IGMP module will check for the
+    * presence of the Router Alert option in the following types of
+    * packets.  Packets that do not have the option will be discarded.
+
+    * (a) Version 2 General Query (0x11) (differentiated from a Version 1
+          Host Membership Query by having a Max Response Time > 0)
+    * (b) Version 2 Group-Specific Query (0x11)
+    * (c) Version 2 Membership Report (0x16)
+    * (d) Version 2 Leave Group (0x17)
+
+    * Version 1 Host Membership Reports and Version 1 Host Membership Query
+    * packets will not be checked for the IP Router Alert option.
+    */
+#ifdef IGMP_V2    
+   if ((type == IGMPv2_LEAVE_GROUP) || 
+       (type == IGMPv2_MEMBERSHIP_REPORT) ||
+       ((type == IGMP_HOST_MEMBERSHIP_QUERY) && (igmp->igmp_code > 0)))
+       
+   {
+      if (!igmpv2_chk4_rtr_alert_opt (pip))
+      { 
+         ++igmpstats.igmpv2mode_v2_rtr_alert_missing;
+         return ENP_BAD_HEADER;
+      }
+   }
+#endif   
+
+   /* validation successful */
+   return IGMP_OK;
+}
+
+
+/* FUNCTION: igmp_print_stats ()
+ * 
+ * This function is invoked by the CLI command parser in response
+ * to the user's "igmp" command.  It prints out various statistics
+ * related to the IGMPv1 and IGMPv2 modules.  Note that these
+ * statistics are for the protocol module (and are across all
+ * links).  The statistics are grouped into three categories:
+ * receive-related, transmit-related, and error-related.
+ *
+ * INPUT: Pointer to I/O device where the output will be directed
+ *        to.
+ *
+ * OUTPUT: This function always returns IGMP_OK.
+ */
+   
+int igmp_print_stats (void * pio)
+{  
+   NET ifp;
+  
+   for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+   {
+      ns_printf (pio, "%s: mode: %u [%s] ", 
+                 ifp->name, 
+                 ifp->igmp_oper_mode, 
+                 ((ifp->igmp_oper_mode == IGMP_MODE_V1)? "v1":"v2"));
+      /* if a link has been configured for IGMPv2, display the status
+       * of the v1 router-related variables too */
+      if (ifp->igmp_oper_mode == IGMP_MODE_V2)
+      {           
+         ns_printf (pio, "v1 rtr: %u [%s] v1 last query: %x [now %x]\n",
+                    ifp->igmpv1_rtr_present,
+                    ((ifp->igmpv1_rtr_present == IGMP_TRUE)? "present" : "absent"),
+                    ifp->igmpv1_query_rcvd_time,
+                    cticks);
+      }
+      else ns_printf (pio, "\n");
+   }   
+
+   /* rx and timer statistics */
+   ns_printf (pio, "[Rx ] IGMP messages rcvd: %lu, timers running: %lu\n", igmpstats.igmp_total_rcvd, igmp_timers_are_running);
+   
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v1-mode links): %lu\n", igmpstats.igmpv1mode_v1_queries_rcvd);
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Reports rcvd: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd);
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv1mode_v1_reports_rcvd_canceled_timer);
+      
+   ns_printf (pio, "[Rx ] IGMPv1 Host Membership Queries rcvd (by v2-mode links): %lu\n", igmpstats.igmpv2mode_v1_queries_rcvd);
+   ns_printf (pio, "[Rx ] IGMPv2 General Queries rcvd: %lu, Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_general_queries_rcvd, igmpstats.igmpv2mode_v2_grp_specific_queries_rcvd);
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd causing timer cancellation: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_canceled_timer);   
+   ns_printf (pio, "[Rx ] IGMP Host Membership Reports rcvd with no local timer: %lu\n", igmpstats.igmpv2mode_v12_reports_rcvd_no_timer);
+   ns_printf (pio, "[Rx ] IGMPv2 Leave Group messages rcvd: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_rcvd);
+   
+   /* tx statistics */
+   ns_printf (pio, "[Tx ] IGMPv2 Leave Group messages sent: %lu, Membership Reports sent: %lu\n", igmpstats.igmpv2mode_v2_leave_msgs_sent, igmpstats.igmpv2mode_v2_reports_sent);
+   ns_printf (pio, "[Tx ] IGMPv1 Host Membership Reports sent: %lu\n", igmpstats.igmp_v1_reports_sent);
+
+   /* error statistics */
+   ns_printf (pio, "[Err] IGMP packets rcvd with bad length: %lu\n", igmpstats.igmp_badlen_rcvd);
+   ns_printf (pio, "[Err] IGMP packets rcvd with bad checksum: %lu\n", igmpstats.igmp_badsum_rcvd);
+   ns_printf (pio, "[Err] Packet buffer allocation failures: %lu, Bad IGMP Oper Mode config: %lu\n",igmpstats.igmp_pkt_alloc_fail, igmpstats.igmp_bad_oper_mode);
+   ns_printf (pio, "[Err] Bad IGMP Queries rcvd: %lu, Bad IGMP Reports rcvd: %lu\n", igmpstats.igmp_bad_queries_rcvd, igmpstats.igmp_bad_reports_rcvd); 
+   ns_printf (pio, "[Err] Bad IGMPv2 Group-Specific Queries rcvd: %lu\n", igmpstats.igmpv2mode_v2_bad_grp_specific_queries_rcvd);
+   ns_printf (pio, "[Err] IGMPv2 Group-Specific Queries rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v2_unknown_grp_specific_queries_rcvd);
+   ns_printf (pio, "[Err] IGMP Membership Reports rcvd with unknown Group Address: %lu\n", igmpstats.igmpv2mode_v12_unknown_grp_reports_rcvd);
+   ns_printf (pio, "[Err] Number of IGMPv2 messages rcvd without Router Alert option: %lu\n", igmpstats.igmpv2mode_v2_rtr_alert_missing); 
+   ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v1-mode links: %lu\n", igmpstats.igmpv1mode_unknown_pkttype);
+   ns_printf (pio, "[Err] IGMP packets of unknown type rcvd by v2-mode links: %lu\n", igmpstats.igmpv2mode_unknown_pkttype);
+   
+   return IGMP_OK;
+}
+
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.h b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.h
new file mode 100644
index 0000000..4025f2b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/igmp_cmn.h
@@ -0,0 +1,189 @@
+/* igmp_cmn.h
+ * 
+ * Companion header file to igmp_cmn.c.
+ */
+ 
+#ifndef IGMP_CMN_H
+#define IGMP_CMN_H
+
+#ifdef IP_MULTICAST
+ 
+/* each link has its own IGMP operating mode: it can
+ * choose to run either IGMPv1 or IGMPv2.
+ */ 
+#define IGMP_MODE_V1 0x1
+#define IGMP_MODE_V2 0x2
+
+/* If the configuration file for the TCP/IP stack does 
+ * not specify a particular IGMP protocol to run on a link, 
+ * the software uses the following logic to select the
+ * IGMP protocol on that link.
+ */
+#if defined (IGMP_V1) && !defined (IGMP_V2)
+#define IGMP_MODE_DEFAULT IGMP_MODE_V1
+#elif !defined (IGMP_V1) && defined (IGMP_V2)
+#define IGMP_MODE_DEFAULT IGMP_MODE_V2
+#elif defined (IGMP_V1) && defined (IGMP_V2)
+#define IGMP_MODE_DEFAULT IGMP_MODE_V2
+#endif
+
+#define IGMP_TRUE 1
+#define IGMP_FALSE 0
+
+#define IGMP_ERR -1
+#define IGMP_FAIL -1
+#define IGMP_OK 0
+
+/* length of IGMP message */
+#define  IGMP_MINLEN 8
+ 
+/*
+IGMPv1 and IGMPv2 statistics data structure:
+
+(1) igmp_total_rcvd: 
+Total number of IGMP (v1 or v2) messages received.
+
+(2) igmpv1mode_v1_queries_rcvd:
+Total number of IGMPv1 Host Membership Queries received
+by device on a link operating in IGMPv1 mode
+
+(3) igmpv1mode_v1_reports_rcvd:
+Total number of IGMPv1 Host Membership Reports received
+by device on a link operating in IGMPv1 mode.
+
+(4) igmpv1mode_v1_reports_rcvd_canceled_timer:
+Total number of IGMPv1 Host Membership Reports received
+(by device on a link operating in IGMPv1 mode) for a
+group for which a timer was running. 
+
+(5) igmpv2mode_v1_queries_rcvd: 
+Number of IGMPv1 Host Membership Queries received by device
+on a link operating in IGMPv2 mode.
+
+(6) igmpv2mode_v2_general_queries_rcvd:
+Number of IGMPv2 General Queries received by device on a link 
+operating in IGMPv2 mode.
+
+(7) igmpv2mode_v2_grp_specific_queries_rcvd:
+Number of valid IGMPv2 Group-Specific Queries received by 
+device on a link operating in IGMPv2 mode.
+
+(8) igmpv2mode_v12_reports_rcvd_canceled_timer:
+Number of IGMPv1/v2 Reports received that resulted in the
+cancelation of a local timer.
+
+(9) igmpv2mode_v12_reports_rcvd_no_timer:
+Number of IGMPv1/v2 Reports received that did not have a
+local timer running.
+
+(10) igmpv2mode_v2_leave_msgs_rcvd:
+Number of IGMPv2 Leave Group messages received by device on a
+link operating in IGMPv2 mode.
+
+(11) igmp_badlen_rcvd:
+Total number of IGMP (v1 or v2) messages that do not 
+have a length of 8 bytes.
+
+(12) igmp_badsum_rcvd:
+Total number of IGMP (v1 or v2) messages that do not 
+have the correct checksum.
+
+(13) igmp_pkt_alloc_fail:
+Count of failures in allocating packet buffer for outgoing 
+IGMPv1/v2 packet.
+
+(14) igmp_bad_oper_mode:
+Number of instances when a received packet could not be
+forwarded to either of the IGMP protocol modules (v1 or
+v2) due to an incorrect configuration of the IGMP operating
+mode for the ingress link.
+
+(15) igmp_bad_queries_rcvd:
+Number of IGMPv1 Host Membership Query or a IGMPv2 General 
+Query messages received that are not addressed to 224.0.0.1.
+
+(16) igmp_bad_reports_rcvd:
+Number of IGMPv1/v2 reports where the IP destination address
+field is not identical to the IGMP group address or the
+IGMP group address is not a multicast address
+
+(17) igmpv1mode_unknown_pkttype:
+Number of packets of unknown type (e.g, not IGMPv1 Host
+Membership Query or IGMPv1 Host Membership Report) received 
+by device on a link opertating in v1 mode.
+
+(18) igmpv2mode_v2_bad_grp_specific_queries_rcvd:
+Number of invalid IGMPv2 Group-Specific Queries (e.g, those
+having a multicast group id of 224.0.0.1 or an invalid multicast 
+address) received by device on a link operating in IGMPv2 mode.
+
+(19) igmpv2mode_v2_unknown_grp_specific_queries_rcvd:
+Number of IGMPv2 Group-Specific Queries received with a group
+address that is not registered for the ingress interface.
+
+(20) igmpv2mode_v12_unknown_grp_reports_rcvd:
+Number of IGMPv1/v2 Membership Reports received with a group
+address that is not registered for the ingress interface.
+
+(21) igmpv2mode_v2_rtr_alert_missing:
+Number of IGMPv2 General Query, IGMPv2 Group-Specific Query,
+IGMPv2 Membership Report, or IGMPv2 Leave Group messages
+received without the IP Router Alert option.
+
+(22) igmpv2mode_unknown_pkttype:
+Number of packets that are of a type other than a IGMPv1/v2 
+Query, IGMPv1/v2 Report, or IGMPv2 Leave Group received by 
+device on a link operating in IGMPv2 mode.
+
+(23) igmp_v1_reports_sent:
+Total number of IGMPv1 Host Membership Reports sent by 
+device on a link operating in IGMPv1 or IGMPv2 mode.
+
+(24) igmpv2mode_v2_leave_msgs_sent:
+Number of IGMPv2 Leave Group messages sent by device on a 
+link operating in IGMPv2 mode.
+
+(25) igmpv2mode_v2_reports_sent:
+Number of IGMPv2 Membership Report messages sent by device
+on a link operating in IGMPv2 mode.
+*/
+
+struct igmp_stats {
+/* rx-related statistics */
+u_long igmp_total_rcvd;
+
+u_long igmpv1mode_v1_queries_rcvd;
+u_long igmpv1mode_v1_reports_rcvd;
+u_long igmpv1mode_v1_reports_rcvd_canceled_timer;
+
+u_long igmpv2mode_v1_queries_rcvd;
+u_long igmpv2mode_v2_general_queries_rcvd;
+u_long igmpv2mode_v2_grp_specific_queries_rcvd;
+u_long igmpv2mode_v12_reports_rcvd_canceled_timer;
+u_long igmpv2mode_v12_reports_rcvd_no_timer;
+u_long igmpv2mode_v2_leave_msgs_rcvd;
+
+/* error-related statistics */
+u_long igmp_badlen_rcvd;
+u_long igmp_badsum_rcvd;
+u_long igmp_pkt_alloc_fail;
+u_long igmp_bad_oper_mode;
+u_long igmp_bad_queries_rcvd;
+u_long igmp_bad_reports_rcvd;
+u_long igmpv1mode_unknown_pkttype;
+u_long igmpv2mode_v2_bad_grp_specific_queries_rcvd;
+u_long igmpv2mode_v2_unknown_grp_specific_queries_rcvd;
+u_long igmpv2mode_v12_unknown_grp_reports_rcvd;
+u_long igmpv2mode_v2_rtr_alert_missing;
+u_long igmpv2mode_unknown_pkttype;
+
+/* tx-related statistics */
+u_long igmp_v1_reports_sent;
+u_long igmpv2mode_v2_leave_msgs_sent;
+u_long igmpv2mode_v2_reports_sent;
+};
+
+#endif /* IGMP_CMN_H */
+
+#endif /* IP_MULTICAST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/ipopt.c b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/ipopt.c
new file mode 100644
index 0000000..cd93836
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/ipopt.c
@@ -0,0 +1,435 @@
+/*
+ * FILENAME: ipopt.c
+ *
+ * Copyright 1997- 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains the code to handle IP multicast options
+ *
+ *
+ * MODULE: IPMC
+ *
+ * ROUTINES: ip_setmoptions(), ip_getmoptions(), 
+ * ROUTINES: ip_freemoptions(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+
+#ifdef IP_MULTICAST
+
+#include "tcpport.h"
+#include "../tcp/in_pcb.h"
+#include "../tcp/protosw.h"
+
+/* base of linked lists for
+ * multicast addresses indexed by
+ * net index
+ */
+
+int   ip_setmoptions(int optname, struct socket *so, void *val);
+int   ip_getmoptions(int optname, struct socket *so, void *arg);
+void  igmp_joingroup(struct in_multi *inm);
+void  igmp_leavegroup(void);
+
+
+
+/* FUNCTION: IPADDR_TO_NETP()
+ * 
+ * PARAM1: ip_addr addr
+ * PARAM2: NET* netp
+ *
+ * RETURNS: 
+ */
+
+void
+IPADDR_TO_NETP(ip_addr addr, NET* netp)
+{
+   u_short  idx   =  0;
+   *netp = nets[idx];
+/*
+ * If ip address is not specified, return the first intfc that supports
+ * multicast
+ */
+   if (addr == AADDR) 
+   {
+      for (idx = 0; idx < ifNumber; idx++)
+      {
+         if (nets[idx]->n_mcastlist)
+         {
+            *netp = nets[idx];
+            break;
+         }
+      }
+   }
+   else  /* ip address specified- return the corresponding interface */
+   {
+      while ((*netp != NULL) && ((*netp)->n_ipaddr != addr))
+      {
+         idx++;
+         if (idx >= ifNumber)
+         {
+            *netp = NULL;
+            break;
+         }
+         else
+            *netp = nets[idx];
+      }
+   }
+}
+
+
+
+/*
+ * Set the IP multicast options in response to user setsockopt().
+ */
+
+
+/* FUNCTION: ip_setmoptions()
+ * 
+ * PARAM1: int optname
+ * PARAM2: struct socket *so
+ * PARAM3: void *val
+ *
+ * RETURNS: 
+ */
+
+int
+ip_setmoptions(int optname, struct socket * so, void * val)
+{
+   int   error =  0;
+   u_short  i;
+   struct ip_mreq *  mreq;
+   struct net *   netp  =  NULL;
+   struct ip_moptions * imo   =  so->inp_moptions;
+   struct ip_moptions **imop  =  &so->inp_moptions;
+   ip_addr addr;
+
+
+   if (imo == NULL) 
+   {
+   /*
+    * No multicast option buffer attached to the pcb;
+    * allocate one and initialize to default values.
+    */
+      imo = (struct ip_moptions*)IM_ALLOC(sizeof(*imo));
+
+      if (imo == NULL)
+         return (ENOBUFS);
+      *imop = imo;
+      imo->imo_multicast_netp = NULL;
+      imo->imo_multicast_ttl = IP_DEFAULT_MULTICAST_TTL;
+      imo->imo_multicast_loop = IP_DEFAULT_MULTICAST_LOOP;
+      imo->imo_num_memberships = 0;
+   }
+
+   switch (optname) 
+   {
+
+   case IP_MULTICAST_IF:
+      /*
+       * Select the interface for outgoing multicast packets.
+       */
+      addr = *(ip_addr *)val;
+         /*
+          * AADDR is used to remove a previous selection.
+          * When no interface is selected, a default one is
+          * chosen every time a multicast packet is sent.
+          */
+      if (addr == AADDR) 
+      {
+         imo->imo_multicast_netp = NULL;
+         break;
+      }
+         /*
+          * The selected interface is identified by its local
+          * IP address.  Find the interface and confirm that
+          * it supports multicasting.
+          */
+      IPADDR_TO_NETP(addr, &netp);
+      if ((netp == NULL) || (netp->n_mcastlist) == NULL) 
+      {
+         error = EADDRNOTAVAIL;
+         break;
+      }
+      if (addr != AADDR) 
+         imo->imo_multicast_netp = netp;
+      break;
+
+   case IP_MULTICAST_TTL:
+      /*
+       * Set the IP time-to-live for outgoing multicast packets.
+       */
+      imo->imo_multicast_ttl = *(u_char *)val;
+      break;
+
+   case IP_MULTICAST_LOOP:
+      /*
+       * Set the loopback flag for outgoing multicast packets.
+       * Must be zero or one.
+       */
+      if (*(u_char *)val > 1) 
+      {
+         error = EINVAL;
+         break;
+      }
+      imo->imo_multicast_loop = *(u_char *)(val);
+      break;
+
+   case IP_ADD_MEMBERSHIP:
+      /*
+       * Add a multicast group membership.
+       * Group must be a valid IP multicast address.
+       */
+      mreq = (struct ip_mreq *)val;
+      if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) 
+      {
+         error = EINVAL;
+         break;
+      }
+      /*
+       * If no interface address was provided, use the interface of
+       * the route to the given multicast address.
+       * For the Iniche stack implementation, look for a default
+       * interface that supports multicast.
+       */
+      IPADDR_TO_NETP(mreq->imr_interface, &netp);
+      /*
+       * See if we found an interface, and confirm that it
+       * supports multicast.
+       */
+      if (netp == NULL || (netp->n_mcastlist) == NULL) 
+      {
+         error = EADDRNOTAVAIL;
+         break;
+      }
+      /*
+       * See if the membership already exists or if all the
+       * membership slots are full.
+       */
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+      {
+         if (imo->imo_membership[i]->inm_netp == netp &&
+             imo->imo_membership[i]->inm_addr
+             == mreq->imr_multiaddr)
+         {
+            break;
+         }
+      }
+      if (i < imo->imo_num_memberships) 
+      {
+         error = EADDRINUSE;
+         break;
+      }
+      if (i == IP_MAX_MEMBERSHIPS) 
+      {
+         error = ETOOMANYREFS;
+         break;
+      }
+      /*
+       * Everything looks good; add a new record to the multicast
+       * address list for the given interface.
+       */
+      if ((imo->imo_membership[i] =
+          in_addmulti(&mreq->imr_multiaddr, netp, 4)) == NULL) 
+      {
+         error = ENOBUFS;
+         break;
+      }
+      ++imo->imo_num_memberships;
+      break;
+
+   case IP_DROP_MEMBERSHIP:
+      /*
+       * Drop a multicast group membership.
+       * Group must be a valid IP multicast address.
+       */
+      mreq = (struct ip_mreq *)val;
+      if (!IN_MULTICAST(ntohl(mreq->imr_multiaddr))) 
+      {
+         error = EINVAL;
+         break;
+      }
+      /*
+       * If an interface address was specified, get a pointer
+       * to its ifnet structure. If an interface address was not
+       * specified, get a pointer to the first interface that
+       * supports multicast.
+       */
+      IPADDR_TO_NETP(mreq->imr_interface, &netp);
+      if (netp == NULL) 
+      {
+         error = EADDRNOTAVAIL;
+         break;
+      }
+
+      /*
+       * Find the membership in the membership array.
+       */
+      for (i = 0; i < imo->imo_num_memberships; ++i) 
+      {
+         if ((netp == NULL ||
+             imo->imo_membership[i]->inm_netp == netp) &&
+             imo->imo_membership[i]->inm_addr ==
+             mreq->imr_multiaddr)
+         {
+            break;
+         }
+      }
+      if (i == imo->imo_num_memberships) 
+      {
+         error = EADDRNOTAVAIL;
+         break;
+      }
+      /*
+       * Give up the multicast address record to which the
+       * membership points.
+       */
+      in_delmulti(imo->imo_membership[i]);
+      /*
+       * Remove the gap in the membership array.
+       */
+      for (++i; i < imo->imo_num_memberships; ++i)
+         imo->imo_membership[i-1] = imo->imo_membership[i];
+      --imo->imo_num_memberships;
+      break;
+
+      default:
+      error = EOPNOTSUPP;
+      break;
+   }
+
+      /*
+       * If all options have default values, no need to keep the mbuf.
+       */
+   if (imo->imo_multicast_netp == NULL &&
+       imo->imo_multicast_ttl == IP_DEFAULT_MULTICAST_TTL &&
+       imo->imo_multicast_loop == IP_DEFAULT_MULTICAST_LOOP &&
+       imo->imo_num_memberships == 0) 
+   {
+      IM_FREE(*imop);
+      *imop = NULL;
+   }
+   return (error);
+}
+
+/*
+ * Return the IP multicast options in response to user getsockopt().
+ */
+
+
+/* FUNCTION: ip_getmoptions()
+ * 
+ * PARAM1: int optname
+ * PARAM2: struct socket *so
+ * PARAM3: void *val
+ *
+ * RETURNS: 
+ */
+
+int
+ip_getmoptions(int optname, struct socket * so, void * val)
+{
+   u_char * ttl;
+   u_char * loop;
+   ip_addr *addr;
+   struct ip_moptions*  imo   =  so->inp_moptions;
+
+   /* The following code will be commented out for Iniche stack.
+    * Don't allocate a buffer here.
+    *
+    *        *mp = m_get(M_WAIT, MT_SOOPTS);
+    */
+   switch (optname) 
+   {
+
+   case IP_MULTICAST_IF:
+      addr = (ip_addr *)(val);
+      if (imo == NULL || imo->imo_multicast_netp == NULL)
+         *addr = AADDR;
+      else
+         *addr = imo->imo_multicast_netp->n_ipaddr;
+      return (0);
+
+   case IP_MULTICAST_TTL:
+      ttl = (u_char *)val;
+      if (imo == NULL)
+         *ttl = IP_DEFAULT_MULTICAST_TTL;
+      else
+         *ttl = imo->imo_multicast_ttl;
+      return (0);
+
+   case IP_MULTICAST_LOOP:
+      loop = (u_char *)val;
+      if (imo == NULL)
+         *loop = IP_DEFAULT_MULTICAST_LOOP;
+      else
+         *loop = imo->imo_multicast_loop;
+      return (0);
+
+      default:
+      return (EOPNOTSUPP);
+   }
+}
+
+/*
+ * Discard the IP multicast options.
+ */
+
+
+/* FUNCTION: ip_freemoptions()
+ * 
+ * PARAM1: struct ip_moptions *imo
+ *
+ * RETURNS: 
+ */
+
+void
+ip_freemoptions(struct ip_moptions * imo)
+{
+   u_short  i;
+
+   if (imo != NULL) 
+   {
+      for (i = 0; i < imo->imo_num_memberships; ++i)
+         in_delmulti(imo->imo_membership[i]);
+      npfree(imo);
+   }
+}
+
+
+
+#endif   /* IP_MULTICAST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/u_mctest.c b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/u_mctest.c
new file mode 100644
index 0000000..f1d88a8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/ipmc/u_mctest.c
@@ -0,0 +1,291 @@
+/*
+ * FILENAME: u_mctest.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: IPMC
+ *
+ * ROUTINES: u_mctest_init(), u_mctest_run()
+ *
+ * PORTABLE: yes
+ */
+
+/*
+ * u_mctest.c            (c) Bob Quinn           2/4/97
+ *
+ * Released to the public domain
+ *
+ * Description:
+ *  Tries out BSD-compatible Multicast APIs, and sends multicast 
+ *  messages in response to multicast messages received.  
+ */
+#include "ipport.h"
+
+// altera changes begin (cadler@altera.com)
+// IP_MULTI_UMCTEST now controlled from ipport.h
+//#ifdef INCLUDE_TCP
+//#define IP_MULTI_UMCTEST  /* define to enable u_mctest.c */
+//#endif
+// altera changes end (cadler@altera.com)
+
+#ifdef IP_MULTI_UMCTEST
+#ifdef IP_MULTICAST
+
+#include "tcpport.h"
+#include "menu.h"
+
+#define  BUFSIZE     1024
+#define  TTL_VALUE   2
+#define  TEST_ADDR "234.5.6.7"
+#define  TEST_ADDR1 "234.1.2.3"
+#define  TEST_ADDR2 "234.4.5.6"
+#define  TEST_PORT   3456
+#define  LOOPMAX     3
+
+extern   struct net  netstatic[MAXNETS];
+extern   char * itoa(int, char *, int);
+extern   u_long inet_addr(char far *);
+int u_mctest_run(void * pio);
+
+// altera changes begin (cadler@altera.com)
+#ifdef IN_MENUS
+// altera changes end (cadler@altera.com)
+struct menu_op u_mctest_menu[]   =  {
+   { "u_mctestc",  stooges,  "u_mctest client menu" },
+   { "u_mctest", u_mctest_run, "run udp multicast test" },
+   {  NULL },
+};
+// altera changes begin (cadler@altera.com)
+#endif //IN_MENUS
+// altera changes end (cadler@altera.com)
+
+
+/* FUNCTION: u_mctest_init()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void u_mctest_init()
+{
+   printf("mctest init called\n");
+// altera changes begin (cadler@altera.com)
+#ifdef IN_MENUS
+// altera changes end (cadler@altera.com)
+   install_menu(u_mctest_menu);
+// altera changes begin (cadler@altera.com)
+#endif //IN_MENUS
+// altera changes end (cadler@altera.com)
+}
+
+
+/* FUNCTION: u_mctest_run()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int u_mctest_run(void * pio)
+{
+    struct sockaddr_in   stLocal, stTo, stFrom;
+    char  achIn[BUFSIZE];
+    char  achOut[] = "Message number:              ";
+    long  s;
+    int   i, iRet, iTmp;
+    struct ip_mreq stMreq;
+    u_char cTmp;
+    unsigned long endtime;
+
+   /* get a datagram socket */
+   s = t_socket(AF_INET,SOCK_DGRAM, 0);
+
+   if (s == INVALID_SOCKET) 
+   {
+      ns_printf (pio,"t_socket() failed, Err: %d\n", t_errno(s));
+      exit(1);
+   }
+
+   /* avoid EADDRINUSE error on bind() */ 
+   iTmp = 1;
+   iRet = t_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (char *)&iTmp, sizeof(iTmp));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() SO_REUSEADDR failed, Err: %d\n",
+       t_errno(s));
+   }
+
+   /* name the socket */
+   stLocal.sin_family =   AF_INET;
+   stLocal.sin_addr.s_addr = htonl(INADDR_ANY);
+   stLocal.sin_port =   htons(TEST_PORT);
+   iRet = t_bind(s, (struct sockaddr*) &stLocal, sizeof(struct sockaddr_in));
+   if (iRet == SOCKET_ERROR) 
+   {
+      printf ("t_bind() failed, Err: %d\n",
+       t_errno(s));
+   }
+
+   /* join the multicast group. TEST_ADDR */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR);
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR);
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP,
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+                     t_errno(s));
+   } 
+   tk_yield();
+
+   /* join the multicast group. TEST_ADDR1 */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR1);
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR1);
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, 
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+                     t_errno(s));
+   }
+   tk_yield();
+
+   /* join the multicast group. TEST_ADDR2 */
+
+   ns_printf (pio,"Joining multicast group: %s\n", TEST_ADDR2);
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR2);
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, 
+                       (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_ADD_MEMBERSHIP failed, Err: %d\n",
+                     t_errno(s));
+   }
+   tk_yield();
+
+   /* set TTL to traverse up to multiple routers */
+   cTmp = TTL_VALUE;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_TTL, (char *)&cTmp, sizeof(cTmp));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_MULTICAST_TTL failed, Err: %d\n",
+                     t_errno(s));
+   }
+
+   /* enable loopback */
+   cTmp = 1;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_MULTICAST_LOOP, (char *)&cTmp, sizeof(cTmp));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_MULTICAST_LOOP failed, Err: %d\n",
+                     t_errno(s));
+   }
+
+   /* assign our destination address */
+   stTo.sin_family =      AF_INET;
+   stTo.sin_addr.s_addr = inet_addr(TEST_ADDR1);
+   stTo.sin_port =        htons(TEST_PORT);
+   ns_printf (pio,"Now sending to (and receiving from) multicast group: %s\n",
+                  TEST_ADDR1);
+
+   for (i = 0; i < LOOPMAX; i++)
+   {
+      static int iCounter = 1;
+
+      /* send to the multicast address */
+      sprintf(&achOut[16], "%d", iCounter++);
+      iRet = t_sendto(s, achOut, sizeof(achOut), 0, (struct sockaddr*)&stTo,
+                      sizeof(struct sockaddr_in));
+      if (iRet < 0) 
+      {
+         /*      perror("sendto() failed\n"); */
+         ns_printf (pio,"t_sendto() failed, Error: %d\n", t_errno(s));
+         /*     exit(1); */
+         goto exitloop;
+      }
+
+      /* make the socket non-blocking */
+      iTmp = 1;
+      iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&iTmp, sizeof(iTmp));
+      if (iRet == SOCKET_ERROR) 
+      {
+         ns_printf (pio,"t_setsockopt() SO_NONBLOCK (1) failed, Err: %d\n",
+                        t_errno(s));
+      }
+
+      /* loop around for 5 seconds waiting to receive datagrams */
+      endtime = cticks + (TPS * 5);
+
+      while (cticks < endtime)
+      {
+         int sa_size = sizeof(struct sockaddr_in);
+         tk_yield();
+
+         iRet = t_recvfrom(s, achIn, BUFSIZE, 0, (struct sockaddr*)&stFrom, &sa_size);
+         if (iRet < 0) 
+         {
+            if (t_errno(s) != EWOULDBLOCK)
+            {
+               /*      perror("recvfrom() failed\n"); */
+               ns_printf (pio,"t_recvfrom() failed, Error: %d\n", t_errno(s));
+               /*     exit(1); */
+               goto exitloop;
+            }
+         }
+         if (iRet > 0)
+         {
+            ns_printf(pio,"From host:%s port:%d, %s\n",
+             print_ipad(stFrom.sin_addr.s_addr),
+             ntohs(stFrom.sin_port), achIn);
+         }
+      }   /* end while (cticks...) */
+
+      /* make the socket blocking */
+      cTmp = 0;
+      iRet = t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, (char *)&cTmp, sizeof(cTmp));
+      if (iRet == SOCKET_ERROR) 
+      {
+         ns_printf (pio,"t_setsockopt() SO_NONBLOCK (0) failed, Err: %d\n",
+                        t_errno(s));
+      }
+   }   /* end for(;;) */
+
+exitloop:
+   /* delete the multicast group. */
+   stMreq.imr_multiaddr = inet_addr(TEST_ADDR);
+   stMreq.imr_interface = netstatic[0].n_ipaddr;
+   iRet = t_setsockopt(s, IPPROTO_IP, IP_DROP_MEMBERSHIP, (char *)&stMreq, sizeof(stMreq));
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_setsockopt() IP_DROP_MEMBERSHIP failed, Err: %d\n",
+                     t_errno(s));
+   }
+
+#ifdef NOT_USED
+#error t_shutdown is not used with UDP sockets
+   iRet = t_shutdown(s, 1);
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_shutdown failed.  Err: %d\n", t_errno(s));
+   }
+#endif
+
+   iRet = t_socketclose(s);
+   if (iRet == SOCKET_ERROR) 
+   {
+      ns_printf (pio,"t_socketclose() failed.  Err: %d\n", t_errno(s));
+   }
+
+   return(0);
+}  /* end main() */  
+
+#endif   /* IP_MULTI_UMCTEST */
+#endif   /* IP_MULTICAST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/app_ping.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/app_ping.c
new file mode 100644
index 0000000..ec04676
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/app_ping.c
@@ -0,0 +1,1140 @@
+/*
+ * FILENAME: app_ping.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Generic ping command 
+ * for sample utilitys. This uses the utilities in ..\inet\ping.c 
+ * which comtains the fully portable but less functional ping lower 
+ * layer. This is somewhat attached to the menus system, but outside 
+ * of that is fairly portable; assumeing cticks & other NetPort IP 
+ * system basics are present.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: ping_init(), ping_new(), ping_delete(), ping_addq(), 
+ * ROUTINES: ping_delq(), ping_search(), ping_cmd_start(),  ping_send(), 
+ * ROUTINES:ping_end(), pingUpcall(), ping_recv(), ping_check(),
+ * ROUTINES: ping_demux(), ping_stats(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software */
+
+#include "ipport.h"
+
+#ifdef PING_APP   /* whole file can be ifdefed out */
+
+#include "in_utils.h"
+
+/* On superloop systems, define away task supoport */
+
+#ifdef SUPERLOOP
+#define  TK_WAKE(task)
+#define  TK_BLOCK()
+#endif   /* SUPERLOOP */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+
+#include "menu.h"
+#include "app_ping.h"
+
+#include "dns.h"      
+
+
+PING_INFO pingq = NULL;    /* Pointer to the first ping session */
+
+
+struct queue    pingRcvq;     /* contains messages from other tasks */
+extern char *   prompt;
+ip_addr ping4_activehost = 0; /* default ping host */
+u_long ping4_delay = TPS;     /* 1 second between pings */
+u_long ping4_deflength = 64;     /* default ping packet data length */
+
+int ping_cmd_end (void * pio);
+int ping_cmd_start (void * pio);
+int ping_cmd_list_stats (void * pio);
+int ping_send_msg1 (u_char type, u_long parm1);
+void ping_process_periodic_timer_msg (void);
+void ping_process_rcvd_reply_pkt (PACKET pkt);
+int ping_process_ping_parm (u_long type, u_long value);
+int ping_process_start_ping_req (u_long dest, u_long count, void * pio);
+
+struct ping_msg_stats ping_msg_stats;
+struct ping_err ping_err;
+
+#ifdef IN_MENUS
+/* array of menu option, see menu.h */
+/*
+ * Altera Niche Stack Nios port modification:
+ * braces to remove build warning
+ */
+struct menu_op settings[] =
+{
+   { "ping",     stooges,             "menu to set/view values for ping" },
+   { "ping",     ping_cmd_start,      "Ping [host] [#times]" },
+   { "endping",  ping_cmd_end,        "terminate the current ping session" },
+   { "pstats",   ping_stats,          "display statistics about ping" },
+   /* 'pstats' could use 'ping_cmd_list_stats' to enqueue for main loop processing */
+   { NULL },
+};
+#endif   /* IN_MENUS */
+
+extern   char *   pingdata;   /* default ping data in ..\net\ping.c */
+#ifndef OS_PREEMPTIVE
+static int in_pingcomp = 0;   /* re-entrancy guard */
+#endif
+
+/* FUNCTION: ping_init()
+ * 
+ * Initialize for pinging operations. Presently this function adds
+ * the ping menu to MAIN menu.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0
+ */
+
+int 
+ping_init(void)
+{
+   pingq=NULL ;    
+
+#ifdef IN_MENUS
+   install_menu(settings);
+#endif   /* IN_MENUS */
+   return 0;
+}
+
+
+/* FUNCTION: ping_new()
+ * 
+ * 1. Allocate memory for a PingInfo structure Initialise elements
+ *    to default values.
+ * 2. Add it to the global queue, so that ping_check() can do the
+ * house keeping. 
+ *
+ * PARAM1: none
+ *
+ * RETURNS: Pointer to the newly allocated structure 
+ */
+
+PING_INFO 
+ping_new(void)
+{
+   PING_INFO p;
+
+   p=(PING_INFO)PING_ALLOC(sizeof(struct PingInfo)) ;
+   if ( p == NULL )
+   {
+      /* Memory allocation failed. */
+      dtrap();
+   }
+   else
+   {
+      if ( ping_addq(p) != SUCCESS )
+      {
+         /* Can't add to queue */
+         dtrap();
+         ping_delete(p);
+         p=NULL;
+      }
+      else
+      {
+         p->delay      =ping4_delay;
+         p->length     =ping4_deflength;
+         p->ipadd      =ping4_activehost;
+         p->nextping   =0;
+         p->times      =1L;
+         p->pio        =NULL;
+         p->out        =0;             /* reset counters */
+         p->in         =0;
+      }
+   }
+
+   return p;
+}
+
+
+/* FUNCTION: ping_delete()
+ * 
+ * 1. Remove the PingInfo structure from the global queue.
+ * 2. Free memory allocated for it.
+ *
+ * PARAM1: PING_INFO p - Pointer to PingInfo structure (IN)
+ *
+ * RETURNS: 0 on SUCCESS or ENP_ error code.
+ */
+
+int 
+ping_delete(PING_INFO p)
+{
+   int   retValue=SUCCESS;
+
+   if ( p == NULL )
+      return PING_DEL_NULL_ARGUMENT ;
+
+   /* Remove the connection from the queue */
+   retValue = ping_delq(p) ;
+   if ( retValue != SUCCESS )
+   {
+      dtrap();
+   }
+
+   PING_FREE(p);
+   p=NULL;
+
+   return retValue;
+}
+
+
+
+/* FUNCTION: ping_addq()
+ * 
+ * Add a PingInfo object to global queue (of open connections)
+ *
+ * PARAM1: PING_INFO p - Pointer to object to be added
+ *
+ * RETURNS: 0 on SUCCESS or ENP_ error code.
+ */
+
+int 
+ping_addq(PING_INFO p)
+{
+   if ( pingq == NULL )     
+   {
+      /* Queue is empty */
+      pingq=p;
+      p->next = NULL ;
+   }
+   else
+   {
+      /* Add it to the front of the queue */
+      p->next = pingq ;
+      pingq=p;
+   }
+   return SUCCESS ;
+}
+
+
+
+/* FUNCTION: ping_delq()
+ * 
+ * Delete a PingInfo object from the global queue
+ * No Free (deallocation) is done. Only the queue is updated 
+ *
+ * PARAM1: PING_INFO p - Pointer to object to be deleted
+ *
+ * RETURNS: 0 on SUCCESS or ENP_ error code.
+ */
+
+int 
+ping_delq(PING_INFO p)
+{
+   PING_INFO temp_obj;
+   PING_INFO prev_obj;
+
+   if ( p == NULL )
+   {
+      return PING_DELQ_BAD_OBJECT ;
+   }
+
+   if ( pingq == NULL )     
+   {
+      /* Queue is empty */
+      return PING_DELQ_Q_EMPTY ;
+   }
+   else
+   {
+      /* Find the item and delete it */
+
+      /* Check if it is the first item */
+      if ( pingq == p )
+      {
+         /* Yes it is the first in the queue */
+         pingq=p->next ;
+         return SUCCESS ;
+      }
+
+      /* Find in the rest of the queue */
+      prev_obj = pingq ;
+      temp_obj = pingq->next ;
+
+      while ( temp_obj !=NULL ) 
+      {
+         if ( temp_obj == p )
+         {
+            prev_obj->next = temp_obj->next ;
+            return SUCCESS ;
+         }
+         prev_obj = temp_obj ;
+         temp_obj = temp_obj->next ;
+      }
+
+      if ( temp_obj == NULL )
+         return PING_DELQ_OBJ_NOT_FOUND ;
+
+   }
+   return SUCCESS;
+}
+
+
+/* FUNCTION: ping_search()
+ * 
+ * Ping can be done by multiple 
+ * mechnisms (standard menu, telnet etc.). We will have only one ping 
+ * session per mechanism. It is assumed that each mechanism (eg a 
+ * telnet session) will use a unique GEN_IO structure. This function 
+ * searches the list of PingInfo structures to find a match. Returns 
+ * a pointer to PingInfo struct on success. Otherwise returns NULL. 
+ * Remarks : This function can be used for finding out if we already 
+ * have ping session or not (for a particular telnet session). It 
+ * will be used when 1. User wants to do a new ping 2. User wants to 
+ * terminate an earlier ping.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: Pointer to PingInfo structure (if found). Otherwise NULL. 
+ */
+
+PING_INFO 
+ping_search(GEN_IO pio)
+{
+   PING_INFO p;
+
+   p=pingq;
+   while ( p )
+   {
+      if ( p->pio == pio )
+         break ;
+      else
+         p = p->next ;
+   }
+
+   return p;
+}
+
+
+/* FUNCTION: ping_cmd_start()
+ * 
+ * Called from menus to do a ping. 
+ * Will handle an optional hosts name to ping and number of times to 
+ * ping on the command line. Defaults to 1 ping to the active host. 0 
+ * times will ping forever.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: 0 on success, or one of the PING error codes
+ */
+
+int
+ping_cmd_start (void * pio)
+{
+   char *   arg2;
+   char *   arg3;
+   char *   name;
+   ip_addr ipadd;
+   long  ping_times=1L;
+#ifdef OS_PREEMPTIVE
+   struct pingtask_msg * msgp;
+#endif   
+   int   e;
+
+   ipadd = 0;
+   arg2  = nextarg(((GEN_IO)pio)->inbuf);       /* get 1 or 2 args from command line */
+   arg3  = nextarg(arg2);
+   name  = arg2 ;
+
+   if (*arg3)  /* If arg3 is present, null terminate arg2 */
+   {
+      while (*arg2 > ' ') arg2++ ;  /* scan to end of arg2 */
+         *arg2 = 0;  /* null terminate string */
+      arg2 = name;   /* Restore arg2 to start of string */
+   }
+
+   /* The second argument is either hostname(IP/dnsname) or number of times */
+   if (*arg2)  /* first arg may be number or host */
+   {
+      /* if it's all digits, assume number */
+      while (*arg2 > ' ')
+      {
+         if (*arg2 > '9' || *arg2 < '0')
+         {
+            /* not a digit; assume arg2 is a name */
+            e = in_reshost(name, &ipadd, RH_VERBOSE | RH_BLOCK);
+            if (e)
+            {
+               ns_printf(pio,"Unable to set up ping host \"%s\"\n", name);
+               return -1;
+            }
+            break;   /* with arg2 pointer at non-digit && non-space */
+         }
+         arg2++;     /* check next char of arg */
+      }
+      if (*arg2 <= ' ') /* 2nd arg looks like a count */
+      {
+         ping_times = atol(name);
+         if ((ping_times == 0) && (*name !='0'))
+            ping_times=-1;    /* So that the error below can be displayed */ 
+      }
+   }
+   if (*arg3)  /* if user specified 2 args, 2nd ard is ping_times */
+   {
+      ping_times = atol(arg3);
+      if ((ping_times == 0) && (*arg3 !='0'))
+         ping_times=-1;    /* So that the error below can be displayed */ 
+   }
+
+   if (ping_times < 0)
+   {
+      ns_printf(pio,"last arg must be number of times to ping (1-n)\n");
+      ns_printf(pio,"or use 0 to ping forever. Default is 1\n");
+      return PING_ST_BAD_ARG2;
+   }
+
+   if (!ipadd)
+   {
+      ns_printf(pio,"No IP address specified, will use default active host if one exists\n");
+   }
+
+   if (ping_times != 1)
+      ns_printf(pio,"Use 'endping' to stop pinging, and 'icmpstat' and/or 'pstats' to examine the results...\n");
+
+#ifndef OS_PREEMPTIVE
+   return (ping_process_start_ping_req (ipadd, ping_times, pio));
+#else
+   msgp = (struct pingtask_msg *) PING_ALLOC (sizeof (struct pingtask_msg));
+   if (!msgp)
+   {
+      ++ping_err.alloc_fail;
+      return PING_ST_ALLOC_ERR;
+   }
+   
+   /* send message for PING client task */
+   msgp->type = PING_CNTRL_START_PING;
+   msgp->parm1 = (u_long) ipadd;
+   msgp->parm2 = ping_times;
+   msgp->parm3 = (u_long) pio;
+
+   LOCK_NET_RESOURCE (PINGQ_RESID);
+   putq(&pingRcvq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (PINGQ_RESID);
+
+   post_app_sem (PING_SEMID);
+#endif
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_send()
+ * 
+ * Send a single ping packet based on static parms.
+ *  This should be called only after start_ping() has 
+ * set things up. It's designed to be called from a timed polling 
+ * routine until all the pings are sent.
+ *
+ * PARAM1: PING_INFO p
+ *
+ * RETURNS: 0 on success, or -1 if error
+ */
+
+int
+ping_send(PING_INFO p)
+{
+   int   e;          /* error holder */
+
+#ifdef PING_REQ_OUTDEV
+   /* We can have a variety of output devices thru pio mechanism. Eg. 
+    * console, telnet client, etc. So consider the following scenario 
+    * 1. InterNiche s/w with TELNET Server is running on 10.22 2. 
+    * User (TELNET Client) does a TELNET connection from 10.20 3. 
+    * User issues a ping-forever command. All ping output is being 
+    * displayed in user's TELNET window. 4. User closes the TELNET 
+    * client before terminating ping session. Now when PING 
+    * application tries to display its output, it fails. In this case 
+    * we close the ping session. 
+    */
+   if (ns_printf(p->pio,"ping %d to %s: ",p->out,print_ipad(p->ipadd)) == 0) 
+   {
+      /* Output device is no longer available for display */
+      ping_delete(p);   /* shut off ping */
+      return -1;
+   }
+#endif
+
+   e = icmpEcho(p->ipadd, NULL, p->length, (unshort)p->out);
+
+   p->times--;    /* count another one done */
+
+   if (e == 0)
+   {
+      p->out++;
+#ifdef PING_REQ_OUTDEV
+      ns_printf(p->pio,"ping %d sent...\n",p->out);
+#endif
+   }
+   else if(e == ARP_WAITING)
+   {
+#ifdef PING_REQ_OUTDEV
+      ns_printf(p->pio,"Arping for host...\n");
+#endif
+      p->out++;
+   }
+   else
+   {
+#ifdef PING_REQ_OUTDEV
+      ns_printf(p->pio,"Ping send failure %d\n",e);
+#endif
+      ping_end(p->pio);    /* shut off ping */
+      return -1;
+   }
+   p->nextping = cticks + p->delay;    /* set time for next ping */
+
+   return 0;
+}
+
+
+
+/* FUNCTION: ping_end()
+ *
+ * End an ongoing ping session. Calls ping_delete() to free 
+ * resources used for ping session.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: SUCCESS or PING_END_NO_SESSION
+ */
+
+int
+ping_end(void * pio)
+{
+   PING_INFO p;
+
+   p = ping_search((GEN_IO)pio);
+   if ( p == NULL )
+   {
+      ns_printf(pio,"No ongoing ping session found.\n");
+      return PING_END_NO_SESSION;
+   }
+
+#ifdef PING_REQ_OUTDEV
+   if (p->out > 1)   /* print complete msg after multiple pings */
+   {
+      ns_printf(pio,"ping complete; sent %d, received %d\n",p->out,p->in);
+   }
+#endif
+
+   ping_delete(p);
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: ping_demux()
+ * 
+ * Find out the PingInfo structure 
+ * corresponding to the received packet. This is tricky ,because we 
+ * just know the source of the ping reply. So we need to go through 
+ * the ping session list and find out the session that pinged to this 
+ * IP address. Pitfalls : Say if two telnet sessions ping to the same 
+ * host at the same time, and the destination replies, output of ping 
+ * will always go to the first telnet session !!!
+ *
+ * PARAM1: ip_addr fhost - IP addres of machine that sent the ping reply (IN)
+ *
+ * RETURNS: Pointer to PingInfo structure or NULL 
+ */
+
+PING_INFO 
+ping_demux(ip_addr fhost)
+{
+   PING_INFO p=pingq;
+
+   while ( p )
+   {
+      if ( p->ipadd == fhost )
+         break;
+      else
+         p=p->next;
+   }
+
+   return p;
+}
+
+
+/* FUNCTION: ping_recv()
+ * 
+ * This function is only used in non-preemptive mode.  It retrieves received
+ * ICMP Echo Reply packets (from where pingUpcall () had deposited them)
+ * and processes them.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+#ifndef OS_PREEMPTIVE 
+void
+ping_recv(void)
+{
+   PACKET pkt;   
+
+   /* Process all the replies that have come */
+   while (pingRcvq.q_len)
+   {
+      pkt = (PACKET)getq(&pingRcvq);
+      if (!pkt)
+         panic("ping_check: no pkt");
+      ping_process_rcvd_reply_pkt (pkt);
+   }
+}
+#endif
+
+/* FUNCTION: ping_process_start_ping_req ()
+ * 
+ * This function is common to all operating environments.  It is invoked
+ * after the user's ping request has been (largely) validated.  It does 
+ * a few additional checks, and then creates a ping structure for the new 
+ * session, and sends out the first ping request.
+ *
+ * INPUTS: (1) Destination of ping request, 
+ *         (2) number of ping requests to send, and 
+ *         (3) pointer to generic IO structure (from where the request
+ *             was initiated).
+ *
+ * OUTPUT: 0, or one of the ping error codes.
+ */
+int ping_process_start_ping_req (u_long dest, u_long count, void * pio)
+{
+   PING_INFO p;
+   int   e;
+   
+   /* check to make sure that we have a valid host */
+   if (dest == 0)
+   {
+      if (ping4_activehost == 0) return PING_ST_NOIP;
+      else dest = ping4_activehost;
+   }
+
+   /* Does the invoker of this command already has another ping going ? */
+   p = ping_search((GEN_IO)pio);
+   if ( p != NULL )
+   {
+      /* End the previous session */
+      ns_printf(pio,"Terminating earlier ping operation.\n");
+      ping_end(pio);
+   }
+
+   p = ping_new();
+   if ( p == NULL )
+   {
+      dtrap();
+      ns_printf(pio,"Error allocating memory for new ping.\n");
+      return PING_ST_ALLOC_ERR;
+   }
+
+   /* Now we are ready to use p */
+   p->ipadd = (ip_addr) dest;
+   p->times = count;
+   p->pio   = (GEN_IO)pio;
+
+   /* if it is ping-forever, then delay should be atleaast 2 timeticks */
+   if ((p->times == 0) && (p->delay < 2))
+   {
+      p->delay=2;
+      ns_printf(pio,"Ping delay is too low for continuous pinging.\n");
+      ns_printf(pio,"Hence delay for this session is %ld ms.\n", 
+       p->delay*TIMEFOR1TICK);
+   }
+
+   e = ping_send(p); /* send 1st ping */
+
+   return e;
+}
+
+
+/* FUNCTION: ping_cmd_end ()
+ * 
+ * This function is invoked to request the termination of a previously
+ * started ping session.  For OS_PREEMPTIVE builds, this function
+ * sends a message to the PING client task requesting the termination.
+ * For other builds, this function executes in the context of the
+ * task processing the user request.
+ *
+ * INPUT: (1) pointer to generic IO structure (from where the termination 
+ *            request was initiated).
+ *
+ * OUTPUT: Return code from ping_end () for non-OS_PREEMPTIVE environment, and
+ *         return code from ping_send_msg1 () for OS_PREEMPTIVE environments.
+ */
+
+int ping_cmd_end (void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ping_send_msg1 (PING_CNTRL_END_PING, ((u_long) pio)));
+#else
+   return (ping_end (pio));
+#endif
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_process_ping_parm
+ * 
+ * This function sets the destination host, delay, and length fields for
+ * subsequent ping requests.
+ * 
+ * INPUT: (1) Type of parameter being sent (e.g., PARM_TYPE_HOST)
+ *        (2) Value for parameter being sent
+ *
+ * OUTPUT: Return code from ping_process_ping_parm () for non-OS_PREEMPTIVE
+ *         environments; 0 if successful and PING_ST_ALLOC_ERR if 
+ *         couldn't allocate memory for message to PING client task
+ *         (for multitasking environments).
+ */
+ 
+int ping_set_parm (u_long parm_type, u_long value)
+{
+#ifdef OS_PREEMPTIVE
+   struct pingtask_msg * msgp;
+
+   msgp = (struct pingtask_msg *) PING_ALLOC (sizeof (struct pingtask_msg));
+   if (!msgp)
+   {
+      ++ping_err.alloc_fail;
+      return PING_ST_ALLOC_ERR;
+   }
+   
+   /* send message to PING client task */
+   msgp->type = PING_CNTRL_SET_PARM;
+   msgp->parm1 = parm_type;
+   msgp->parm2 = value;
+
+   LOCK_NET_RESOURCE (PINGQ_RESID);
+   putq(&pingRcvq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (PINGQ_RESID);
+
+   post_app_sem (PING_SEMID);
+#else
+   return (ping_process_ping_parm (parm_type, value));
+#endif   
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_process_ping_parm
+ * 
+ * This function sets the destination host, delay, and length fields for
+ * subsequent ping requests.
+ * 
+ * INPUT: (1) Type of parameter being sent (e.g., PARM_TYPE_HOST)
+ *        (2) Value for parameter being sent
+ *
+ * OUTPUT: 0 if successful, or PING_ST_BAD_ARG2 if an unrecognized type
+ *         is encountered.
+ */
+
+int ping_process_ping_parm (u_long type, u_long value)
+{
+   switch (type)
+   {
+      case PARM_TYPE_HOST:
+         ping4_activehost = (ip_addr) value;
+         break;
+      case PARM_TYPE_DELAY:
+         ping4_delay = value;
+         break;
+      case PARM_TYPE_LENGTH:
+         ping4_deflength = value;
+         break;
+      default:
+         ++ping_err.bad_parmtype;
+         return PING_ST_BAD_ARG2;
+   }
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_check ()
+ *
+ * This function is invoked from inet_timer.  For multitasking systems,
+ * it deposits a PING_CNTRL_PERIODIC_TIMER message into the message
+ * queue for the PING client task (the receipt of which triggers the
+ * invocation of the ping_process_periodic_timer_msg () function).  For 
+ * non-preemptive systems, it invokes the ping_process_periodic_timer_msg () 
+ * function directly to perform periodic processing (e.g. sending 
+ * additional ping requests for ongoing sessions).
+ *
+ * INPUT: None.
+ *
+ * OUTPUT: None.
+ */
+void
+ping_check(void)
+{
+#ifndef OS_PREEMPTIVE
+   if (in_pingcomp)  /* guard against re-entry */
+      return;
+   in_pingcomp++;    /* set re-entry flag */
+
+   ping_recv();   /* check receives here */
+
+   ping_process_periodic_timer_msg ();
+
+   in_pingcomp--;    /* clear re-entry flag */
+#else
+   /* second parameter to ping_send_msg1 () is irrelevant */
+   ping_send_msg1 (PING_CNTRL_PERIODIC_TIMER, 0);
+#endif
+
+   return;      
+}
+
+
+/* FUNCTION: ping_cmd_list_stats ()
+ * 
+ * This function is invoked from the menu system to request the ping
+ * configuration and latest ping statistics.
+ *
+ * INPUT: Pointer to generic IO structure from where the request originated.
+ *
+ * OUTPUT: Return code from ping_stats (for non-preemptive).  For 
+ *         preemptive environments, return code from ping_send_msg1 ().
+ */
+ 
+void
+ping_process_periodic_timer_msg (void)
+{
+   PING_INFO p = pingq;
+   PING_INFO nextp;
+   GEN_IO pio;
+
+   /* Send more ping packets, if so configured. */
+   while (p)
+   {
+      nextp = p->next ;
+      if ((p->nextping != 0) && (p->nextping <= cticks))
+      {
+         if (p->times != 0)
+         {
+            ping_send(p);
+         }
+         else
+         {
+            pio = p->pio;
+#ifdef PING_REQ_OUTDEV
+            ns_printf(pio, prompt); /* print prompt before p->pio is freed */
+#endif
+            ping_end(pio);            
+         }
+      }
+      p = nextp;
+   }
+
+}
+
+
+/* ping_cmd_list_stats ()
+ * 
+ * This function is invoked from the menu system to request the ping
+ * configuration and latest ping statistics.
+ *
+ * INPUT: Pointer to generic IO structure from where the request originated.
+ *
+ * OUTPUT: Return code from ping_stats (for SUPERLOOP).  For other
+ *         operating environments, return code from ping_send_msg1 ().
+ */
+
+int 
+ping_cmd_list_stats (void * pio)
+{
+#ifdef OS_PREEMPTIVE
+   return (ping_send_msg1 (PING_CNTRL_LIST_STATS, ((u_long) pio)));
+#else
+   return (ping_stats (pio));
+#endif
+
+}
+
+
+/* FUNCTION: ping_stats()
+ * 
+ * Display statistics about ping sessions.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: SUCCESS.
+ */
+
+int
+ping_stats(void * pio)
+{
+   PING_INFO p=pingq;
+   u_long cnt=0;
+
+   ns_printf(pio,"Default ping delay time: %lu ms\n", ping4_delay*TIMEFOR1TICK);
+   ns_printf(pio,"Default ping host: %s\n", print_ipad(ping4_activehost));
+   ns_printf(pio,"Default ping data length: %lu bytes\n", ping4_deflength);
+
+   while (p)
+   {
+      cnt++;
+      ns_printf(pio,"Statistics about pinging %s\n",
+       print_ipad(p->ipadd) );
+      ns_printf(pio,"Times=%ld, Length=%d, Delay=%ld\n",
+       p->times, p->length, p->delay*TIMEFOR1TICK );
+      ns_printf(pio,"Packets : sent=%d, received=%d\n\n",
+       p->out, p->in);
+      p=p->next;
+   }
+
+   ns_printf(pio,"There are %lu ongoing ping sessions.\n",cnt);
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: pingUpcall()
+ *
+ * called from ICMP layer when we receive an ICMP Echo Reply.
+ * The received packet is queued in pingRcvq for the SUPERLOOP
+ * operating environment.  For multitasking environments, it 
+ * is encapsulated inside a message structure (of type 
+ * PING_DATA_ECHO_REPLY) that is then sent to the PING client 
+ * task.
+ *
+ * PARAM1: PACKET p -  Pointer to the received packet (IN)
+ *
+ * RETURNS: 0 for SUPERLOOP; return code from ping_send_msg1 ()
+ *          for other operating environments. 
+ */
+
+int 
+pingUpcall(PACKET p)
+{
+#ifndef OS_PREEMPTIVE
+   putq(&pingRcvq, (q_elt)p);
+#else   
+   return (ping_send_msg1 (PING_DATA_ECHO_REPLY, ((u_long) p)));
+#endif
+   
+   return 0;
+}
+
+
+/* FUNCTION: ping_process_rcvd_reply_pkt ()
+ * 
+ * This function is invoked to process a received ICMP Echo Reply
+ * packet.  It validates the received reply, and then prints out
+ * status information for the relevant ping session.  This function
+ * is common to all operating environments.
+ *
+ * INPUT: Pointer to received packet.
+ *
+ * OUTPUT: None.
+ */
+void
+ping_process_rcvd_reply_pkt (PACKET pkt)
+{
+   struct ping *  pp;
+   u_char * pdata;
+   int   i, dataend, pdlen;
+   int   data_len;      /* length of DATA in recived ping */
+   int   save_seq;
+   ip_addr save_host;
+   PING_INFO p;
+
+   pp = (struct ping *)pkt->nb_prot;
+   /* the upcalled packet included the ICMP header. Strip this off
+    * for the purposes of reporting data size
+    */
+   data_len = pkt->nb_plen -= sizeof(struct ping);
+   save_seq = (unsigned)pp->pseq;
+   save_host = pkt->fhost;
+
+   /* If the ping data fields looks like one of our defaults, verify
+    * the contents. This relies on the code in ..\inet\ping.c
+    */
+   pdata = (u_char*)(pp+1);   /* pointer to ping data */
+   pdlen = strlen(pingdata);
+   if (strncmp(pingdata, (char*)pdata, pdlen) == 0)
+   {
+      pdata += pdlen;      /* point past verified text */
+      dataend = pkt->nb_plen - pdlen;
+      for (i = pdlen; i < dataend; i++)
+      {
+         /*
+          * Altera Niche Stack Nios port modification:
+          * cast arg to remove build warning
+          */
+         if (*pdata++ != (u_char)(i & 0xFF))
+         {
+            dprintf("ping data mismatch at byte %u\n",
+            (unsigned int)(i + pdlen + sizeof(struct ping)) );
+            break;
+         }
+      }
+   }
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(pkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   /* Output the result at the caller's output device */
+   /* For that, first find out the sender of this ping */
+
+   p = ping_demux(save_host) ;
+   if ( p != NULL )
+   {
+      p->in++;
+#ifdef PING_REQ_OUTDEV
+      if (ns_printf(p->pio,"got ping reply; data len %d seq %d from %s\n",
+                    data_len, save_seq, print_ipad(save_host)) == 0)
+      {
+         /* Output device is no longer available for display */
+         ping_delete(p);   /* shut off ping */
+      }
+      else if (ns_printf(p->pio,prompt) == 0)
+      {
+         /* Output device is no longer available for display */
+         ping_delete(p);   /* shut off ping */
+      }
+#endif
+         
+   }
+#ifndef TESTMENU  /* don't flood console if testing */
+   else
+   {
+      dprintf("Could not find invoker of ping %s\n",print_ipad(pkt->fhost));
+   }
+#endif
+}
+
+#ifdef OS_PREEMPTIVE
+/* FUNCTION: ping_send_msg1 ()
+ *
+ * This function is used to send a message with zero or one parameters
+ * to the PING client task.
+ * 
+ * INPUT: (1) Type of message being sent (e.g., PING_CNTRL_START_PING)
+ *        (2) Parameter #1 of message being sent (optional; not used
+ *            for messages that do not require a parameter (such as
+ *            the PING_CNTRL_PERIODIC_TIMER message).
+ *
+ * OUTPUT: 0 if successful, or PING_ST_ALLOC_ERR if the message structure
+ *         cannot be allocated.
+ * 
+ */
+ 
+int 
+ping_send_msg1 (u_char type, u_long parm1)
+{
+   struct pingtask_msg * msgp;
+
+   msgp = (struct pingtask_msg *) PING_ALLOC (sizeof (struct pingtask_msg));
+   if (!msgp)
+   {
+      ++ping_err.alloc_fail;
+      return PING_ST_ALLOC_ERR;
+   }
+   
+   /* send message to PING client task */
+   msgp->type = type;
+   msgp->parm1 = parm1;
+
+   LOCK_NET_RESOURCE (PINGQ_RESID);
+   putq(&pingRcvq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (PINGQ_RESID);
+
+   post_app_sem (PING_SEMID);
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_process_rcvd_msgs ()
+ * 
+ * This function is used in multitasking environments.  It processes
+ * messages received from other tasks (such as console task, Telnet
+ * server task, and timer task).  These messages provide configuration
+ * parameters, initiate (or terminate) ping requests, and provide
+ * periodic timeout notification.  This function is invoked after the
+ * PING client task returns from its wait for the PING client
+ * semaphore.
+ *
+ * INPUT: None.
+ *
+ * OUTPUT: None.
+ */
+
+void 
+ping_process_rcvd_msgs (void)
+{
+   struct pingtask_msg * msgp;
+
+   LOCK_NET_RESOURCE (PINGQ_RESID);
+   msgp = getq (&pingRcvq);
+   UNLOCK_NET_RESOURCE (PINGQ_RESID);
+   
+   if (!msgp) 
+   {
+      ++ping_err.empty_q;
+      return;
+   }
+
+   switch (msgp->type)
+   {
+      case PING_CNTRL_START_PING:
+         /* message parameters: destination (IP address), number of ping requests, 
+          * pointer to GEN_IO structure */
+         ++ping_msg_stats.start_ping;
+         ping_process_start_ping_req (msgp->parm1, msgp->parm2, ((void *) msgp->parm3));
+         break;
+      case PING_CNTRL_END_PING:
+         /* parameter: pointer to GEN_IO structure */
+         ++ping_msg_stats.end_ping;
+         ping_end ((void *) msgp->parm1);
+         break;
+      case PING_CNTRL_SET_PARM:
+         /* parameters: type of parameter (PARM_TYPE_HOST, PARM_TYPE_DELAY, or 
+          * PARM_TYPE_LENGTH), value for parameter */
+         ++ping_msg_stats.set_parm;
+         ping_process_ping_parm (msgp->parm1, msgp->parm2);
+         break;
+      case PING_CNTRL_PERIODIC_TIMER:
+         ++ping_msg_stats.periodic_timer;
+         ping_process_periodic_timer_msg ();
+         break;
+      case PING_CNTRL_LIST_STATS:
+         /* parameter: pointer to GEN_IO structure */
+         ++ping_msg_stats.list_stats;
+         ping_stats ((void *) msgp->parm1);
+         break;         
+      case PING_DATA_ECHO_REPLY:
+         ++ping_msg_stats.echo_reply;
+         /* parameter: pointer to received packet containing ICMP Echo Reply */
+         ping_process_rcvd_reply_pkt ((PACKET) msgp->parm1);
+         break;
+      default:
+         /* increment error counter */
+         ++ping_err.bad_msgtype;
+         break;
+   }
+
+   /* free the data structure containing the just processed message */
+   PING_FREE (msgp);
+
+   return;
+}
+#endif /* OS_PREEMPTIVE */
+
+#endif   /* PING_APP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/bsdsock.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/bsdsock.c
new file mode 100644
index 0000000..1d2d60e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/bsdsock.c
@@ -0,0 +1,645 @@
+/* FILENAME: bsdsock.c
+ *
+ * Copyright 2000 InterNiche Technologies Inc.  All rights reserved.
+ *
+ * BSD sockets porting aid
+ *
+ * MODULE: misclib
+ * ROUTINES: bsd_accept(), bsd_getpeername(), bsd_getsockname(),
+ *           bsd_getsockopt(), bsd_inet_aton(), bsd_inet_ntoa(),
+ *           bsd_recvfrom(), bsd_select(), bsd_setsockopt(), 
+ *           bsd_i_sockoptlen()
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+
+#ifdef BSD_SOCKETS
+
+#include <stdarg.h>
+
+#include "netbuf.h"
+#include "net.h"
+
+#ifdef IP_MULTICAST
+#include "ip.h"
+#endif
+
+#include "bsdsock.h"
+
+#include "sockvar.h"
+
+
+/* FUNCTION: bsd_accept()
+ *
+ * Accept a connection on a socket
+ *
+ * PARAM1: s; IN - socket descriptor for the listening socket
+ * PARAM2: addr; OUT - ptr to buffer for return of accepted peer's address;
+ *               may be NULL if return of address is not requested
+ * PARAM3: addrlen; IN/OUT - ptr to int; on entry, specifies the length
+ *                  in bytes of addr; on successful return, specifies the
+ *                  length of the returned address; may be NULL if 
+ *                  addr is also NULL
+ * RETURNS: A socket descriptor if successful, -1 if an error occurred.  
+ *          The error is available via bsd_errno(s).
+ */
+BSD_SOCKET
+bsd_accept(BSD_SOCKET s,
+           struct sockaddr * addr, int * addrlen)
+{
+   struct socket * so;
+   struct sockaddr laddr;
+   long lret;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* if we were given a buffer for the peer's address, also get the
+    * buffer's length 
+    */
+   if (addr != NULL)
+   {
+      if (addrlen == 0)
+      {
+         so->so_error = EFAULT;
+         return -1;
+      }
+   }
+
+   lret = t_accept(s, &laddr, addrlen);
+
+   /* if we were successful, and we were given a buffer for the peer's
+    * address: copy the peer's address back into the buffer, but limit
+    * the copy to the lesser of the buffer's length and sizeof(struct
+    * sockaddr_in), which is all that t_accept() can return as a peer
+    * address.  
+    */
+   if ((lret != -1) && (addr != NULL))
+   {
+      if (*addrlen > sizeof(struct sockaddr_in))
+         *addrlen = sizeof(struct sockaddr_in);
+      MEMCPY(addr, &laddr, *addrlen);
+   }
+
+   return lret;
+}
+
+/* FUNCTION: bsd_getpeername()
+ *
+ * Get the name of the connected peer
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: name; OUT - ptr to buffer for return of peer's address
+ * PARAM3: addrlen; IN/OUT - ptr to int; on entry, specifies the length
+ *                  in bytes of name; on successful return, specifies the
+ *                  length of the returned name
+ * RETURNS: 0 if successful, -1 if an error occurred.  The error is
+ *          available via bsd_errno(s).
+ */
+int
+bsd_getpeername(BSD_SOCKET s,
+                struct sockaddr * name, int * namelen)
+{
+   struct socket * so;
+   struct sockaddr lname;
+   int lnamelen;
+   int lret;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* if the buffer length is bogus, fail */
+   if (namelen == NULL)
+   {
+      so->so_error = EFAULT;
+      return -1;
+   }
+   lnamelen = *namelen;
+
+   lret = t_getpeername(s, &lname, &lnamelen);
+
+   /* if we were successful: copy the peer's address back into the
+    * buffer, but limit the copy to the lesser of the buffer's length
+    * and sizeof(struct sockaddr_in), which is all that
+    * t_getpeername() can return as a peer address, and pass the
+    * copied length back to the caller.  
+    * For IPV6 addresses, or for dual IPV4/IPV6 stack, 
+    * the max size is sizeof(struct sockaddr_in6)
+    */
+   if (lret != -1)
+   {
+#ifndef IP_V6
+      if (lnamelen > sizeof(struct sockaddr_in))
+         lnamelen = sizeof(struct sockaddr_in);
+#else
+      if (lnamelen > sizeof(struct sockaddr_in6))
+         lnamelen = sizeof(struct sockaddr_in6);
+
+#endif
+      MEMCPY(name, &lname, lnamelen);
+      *namelen = lnamelen;
+   }
+
+   return lret;
+}
+
+/* FUNCTION: bsd_getsockname()
+ *
+ * Gets the name of the socket.
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: name; OUT - ptr to buffer for return of peer's address
+ * PARAM3: addrlen; IN/OUT - ptr to int; on entry, specifies the length
+ *                  in bytes of name; on successful return, specifies the
+ *                  length of the returned name
+ * RETURNS: 0 if successful, -1 if an error occurred.  The error is
+ *          available via bsd_errno(s).
+ */
+int
+bsd_getsockname(BSD_SOCKET s,
+                struct sockaddr * name, int * namelen)
+{
+   struct socket * so;
+   struct sockaddr lname;
+   int lnamelen;
+   int lret;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* if the buffer length is bogus, fail */
+   if (namelen == NULL)
+   {
+      so->so_error = EFAULT;
+      return -1;
+   }
+   lnamelen = *namelen;
+
+   lret = t_getsockname(s, &lname, &lnamelen);
+
+   /* if we were successful: copy the peer's address back into the
+    * buffer, but limit the copy to the lesser of the buffer's length
+    * and sizeof(struct sockaddr_in), which is all that
+    * t_getpeername() can return as a peer address, and pass the
+    * copied length back to the caller.  
+    * For IPV6 addresses, or for a dual IPV4/IPV6 stack, 
+    * the max size copied is sizeof(struct sockaddr_in6)
+    *
+    */
+   if (lret != -1)
+   {
+#ifndef IP_V6
+      if (lnamelen > sizeof(struct sockaddr_in))
+         lnamelen = sizeof(struct sockaddr_in);
+#else
+      if (lnamelen > sizeof(struct sockaddr_in6))
+         lnamelen = sizeof(struct sockaddr_in6);
+#endif
+      MEMCPY(name, &lname, lnamelen);
+      *namelen = lnamelen;
+   }
+
+   return lret;
+}
+
+/* FUNCTION: bsd_i_sockoptlen()
+ *
+ * Get the minimum length of a named socket option
+ *
+ * PARAM1: level; IN - the level of the option
+ * PARAM2: name; IN - the name of the option
+ * RETURNS: minimum length of the named socket option, in bytes
+ */
+int 
+bsd_i_sockoptlen(int level,
+                 int name)
+{
+   USE_ARG(level);
+
+   switch (name)
+   {
+   case SO_BIO:
+   case SO_NBIO:
+      /* these don't use an option value */
+      return 0;
+   case SO_LINGER:
+      /* this option is a struct linger */
+      return sizeof(struct linger);
+   case SO_RCVTIMEO:
+   case SO_SNDTIMEO:
+      /* these options are type short */
+      return sizeof(short);
+   case SO_KEEPALIVE:
+   case SO_DONTROUTE:
+   case SO_BROADCAST:
+   case SO_REUSEADDR:
+   case SO_OOBINLINE:
+   case SO_SNDBUF:
+   case SO_RCVBUF:
+   case SO_NONBLOCK:
+   case SO_ERROR:
+   case SO_TYPE:
+      /* these options are type int */
+      return sizeof(int);
+#ifdef TCP_ZEROCOPY
+   case SO_CALLBACK:
+      /* this option is a pointer to a function returning int */
+      return sizeof(int (*)());
+#endif /* TCP_ZEROCOPY */
+#ifdef IP_MULTICAST
+   case IP_MULTICAST_IF:
+      /* this option is type ip_addr */
+      return sizeof(ip_addr);
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+      /* these options are type u_char */
+      return sizeof(u_char);
+   case IP_ADD_MEMBERSHIP:
+   case IP_DROP_MEMBERSHIP:
+      /* these options are struct ip_mreq */
+      return sizeof(struct ip_mreq);
+#endif /* IP_MULTICAST */
+   case IP_TOS:
+/*
+ * Altera Niche Stack Nios port modification:
+ * IP_TTL_OPT == SOREUSEADDR. This causes a build erro
+ * due to duplicate cases. Removing this one. They both
+ * return the same value (sizeof(int)).
+ */
+  // case IP_TTL_OPT:
+      return sizeof(int);
+   default:
+      /* we don't know what type these options are */
+      return 0;
+   }
+   
+}
+
+/* FUNCTION: bsd_getsockopt()
+ *
+ * Get a socket option value
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: level; IN - the level of the option to get
+ * PARAM3: name; IN - the name of the option to get
+ * PARAM4: opt; OUT - ptr to buffer for return of option value; may be
+ *              NULL
+ * PARAM5: optlen; IN/OUT - ptr to int; on entry, specifies the length
+ *                 in bytes of opt; on successful return, specifies the
+ *                 length of the returned option; may be NULL if opt is
+ *                 also NULL
+ * RETURNS: 0 if successful, -1 if an error occurred.  The error is
+ *          available via bsd_errno(s).
+ */
+int
+bsd_getsockopt(BSD_SOCKET s,
+               int level,
+               int name,
+               void * opt, int * optlen)
+{
+   struct socket * so;
+   int loptlen;
+   int e;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* make sure supplied option value is big enough for the 
+    * named option, else fail w/error EFAULT
+    */
+   loptlen = bsd_i_sockoptlen(level, name);
+   if ((optlen == NULL) || (*optlen < loptlen))
+   {
+      so->so_error = EFAULT;
+      return -1;
+   }
+
+   e = t_getsockopt(s, level, name, opt, loptlen);
+
+   /* if it worked, copy the option length back for the caller's use */
+   if (e == 0)
+   {
+      *optlen = loptlen;
+   }
+
+   return e;
+   
+}
+
+/*
+ * FUNCTION: bsd_ioctl()
+ *
+ * Perform a control operation on a socket
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: request; IN - requested control operation
+ * PARAM3: arg; IN/OUT - arguments as required for control operation
+ * RETURNS: 0 if successful, -1 if an error occurred.  The error is
+ *          available via bsd_errno(s).
+ */
+int
+bsd_ioctl(BSD_SOCKET s, 
+          unsigned long request, ...)
+{
+   struct socket * so;
+   va_list argptr;
+   int iarg;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   va_start(argptr, request);
+
+   switch (request)
+   {
+   case FIONBIO:
+      iarg = va_arg(argptr, int);
+      va_end(argptr);
+      return t_setsockopt(s, SOL_SOCKET, SO_NONBLOCK, &iarg, sizeof(iarg));
+   default:
+      so->so_error = EINVAL;
+      return -1;
+   }
+}
+
+
+#ifdef NOT_USED
+#error use inet_addr() in misclib/parseip.c
+/*
+ * FUNCTION: bsd_inet_addr()
+ *
+ * Parses a dotted-decimal Internet address
+ *
+ * PARAM1: cp; IN - dotted-decimal Internet address 
+ * RETURNS: The parsed Internet address, in network order
+ */
+BSD_IN_ADDR_T
+bsd_inet_addr(char * cp)
+{
+   BSD_IN_ADDR_T ret;
+   ip_addr addr;
+   unsigned sbits;
+   char * err;
+
+   err = parse_ipad(&addr, &sbits, cp);
+   if (err == NULL)
+   {
+      /* return the address as success */
+      ret = addr;
+   }
+   else
+   {
+      /* return failure */
+      ret = 0;
+   }
+   return ret;
+}
+
+
+/*
+ * FUNCTION: bsd_inet_aton()
+ *
+ * Parses a dotted-decimal Internet address
+ *
+ * PARAM1: cp; IN - dotted-decimal Internet address 
+ * PARAM2: pin; OUT - pointer to buffer where parsed address is to be
+ *                    returned
+ * RETURNS: 1 if parsing was successful,
+ *          0 if parsing failed.
+ */
+int
+bsd_inet_aton(char * cp, struct in_addr * pin)
+{
+   ip_addr addr;
+   unsigned sbits;
+   char * err;
+
+   err = parse_ipad(&addr, &sbits, cp);
+   if (err == NULL)
+   {
+      /* if the caller gave us a buffer, copy the returned address
+       * into it
+       */
+      if (pin != NULL)
+         pin->s_addr = addr;
+      /* return success */
+      return 1;
+   }
+   else
+   {
+      /* return failure */
+      return 0;
+   }
+}
+#endif
+
+
+
+/*
+ * FUNCTION: bsd_inet_ntoa()
+ *
+ * Formats an Internet address into its printable dotted-decimal
+ * representation.
+ *
+ * PARAM1: in; IN - Internet Address (in network order)
+ * RETURNS: pointer to null-terminated string containing dotted-decimal
+ *          printable representation of in
+ */
+char *
+bsd_inet_ntoa(struct in_addr in)
+{
+   return print_ipad(in.s_addr);
+}
+
+/* FUNCTION: bsd_recvfrom()
+ *
+ * Receive data from a socket
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: buf; OUT - ptr to buffer for return of received data
+ * PARAM3: len; IN - length (in bytes) of buf
+ * PARAM4: flags; IN - flags to be applied to the recvfrom() operation
+ * PARAM5: from; OUT - ptr to buffer for return of sending peer's name;
+ *               may be NULL if return of name is not requested
+ * PARAM6: fromlen; IN/OUT - ptr to int; on entry, specifies the length
+ *                  in bytes of from; on successful return, specifies the
+ *                  length of the returned name; may be NULL if 
+ *                  from is also NULL
+ * RETURNS: the number of bytes received (>= 0), or -1 if an error
+ *          occurred.  The error is available via bsd_errno(s).
+ */
+int
+bsd_recvfrom(BSD_SOCKET s,
+             void * buf,
+             BSD_SIZE_T len,
+             int flags,
+             struct sockaddr * from, int * fromlen)
+{
+   struct socket * so;
+   struct sockaddr lfrom;
+   int lfromlen = 0;
+   int lret;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* if we were given a buffer for the peer's address, also get the
+    * buffer's length 
+    */
+   if (from != NULL)
+   {
+      if (fromlen == NULL)
+      {
+         so->so_error = EFAULT;
+         return -1;
+      }
+      lfromlen = *fromlen;
+   }
+
+   lret = t_recvfrom(s, (char *)buf, len, flags, &lfrom, &lfromlen );
+
+   /* if we were successful, and we were given a buffer for the peer's
+    * name: copy the peer's name back into the buffer, but limit
+    * the copy to the lesser of the buffer's length and sizeof(struct
+    * sockaddr_in), which is all that t_recvfrom() can return as a peer
+    * name.
+    * For IPV6 addresses or dual IPV4/IPV6 stack, the max size copied
+    * is sizeof(struct sockaddr_in6)
+    */
+   if ((lret != -1) && (from != NULL))
+   {
+#ifndef IP_V6
+      if (lfromlen > sizeof(struct sockaddr_in))
+         lfromlen = sizeof(struct sockaddr_in);
+#else
+      if (lfromlen > sizeof(struct sockaddr_in6))
+         lfromlen = sizeof(struct sockaddr_in6);
+
+#endif
+      MEMCPY(from, &lfrom, lfromlen);
+      *fromlen = lfromlen;
+   }
+
+   return lret;
+}
+
+#ifdef SO_SELECT
+/* FUNCTION: bsd_select()
+ *
+ * Synchronous I/O multiplexing (for sockets)
+ *
+ * PARAM1: nfds; IN - the number of fds to be checked in each set (readfds,
+ *               writefds, exceptfds): not used in this release
+ * PARAM2: readfds; IN/OUT - fd set containing descriptors to be examined
+ *                  for readiness to read (i.e. received data is present
+ *                  and can be retreived by recv() or recvfrom() without
+ *                  blocking); on successful return, will contain 
+ *                  only those descriptors that are ready to read
+ * PARAM3: writefds; IN/OUT - fd set containing descriptors to be examined
+ *                   for readiness to write (e.g. send() or sendto() could
+ *                   succeed without blocking, or socket has connect()ed);
+ *                   on successful return, will contain only those 
+ *                   descriptors that are ready to write
+ * PARAM4: exceptfds; IN/OUT - fd set containing descriptors to be examined
+ *                    for exceptional conditions (i.e. out-of-band data
+ *                    pending on socket); on successful return
+ * PARAM5: timeout; IN - ptr to a struct timeval, which should be set to
+ *                  indicate the maximum interval to wait for any 
+ *                  descriptor(s) to become ready; may be NULL, indicating 
+ *                  that select() can wait indefinitely for any descriptor(s) 
+ *                  to become ready
+ * RETURNS: if successful, the number of ready file descriptors in all
+ *          the fd sets (may be 0 if the timeout expired), or -1 if an
+ *          error occured.  The error would be available via bsd_errno(s).
+ */
+int 
+bsd_select(int nfds,
+           fd_set * readfds,
+           fd_set * writefds,
+           fd_set * exceptfds,
+           BSD_TIMEVAL_T * timeout)
+{
+   long ltv;    /* timeout expressed in ticks */
+   long tps;    /* local copy of TPS */
+
+   USE_ARG(nfds);
+
+   if (timeout != NULL)
+   {
+      /* This turning of a struct timeval into a tick-count timeout
+       * assumes that TPS (ticks-per-second) is a reasonably small
+       * integer, and that tv_usec may be anywhere from 0 to one
+       * million (i.e. any number of microseconds up to one second).
+       * So we scale tv_usec from microseconds to something reasonable
+       * based on TPS, multiply it by TPS, then scale it the rest of
+       * the way to ticks-per-second.
+       */
+      tps = TPS;
+      if (tps >= 1000)
+      {
+         ltv = (((timeout->tv_usec + 50) / 100) * tps) / 10000;
+      }
+      else if (tps >= 100)
+      {
+         ltv = (((timeout->tv_usec + 500) / 1000) * tps) / 1000;
+      }
+      else if (tps >= 10)
+      {
+         ltv = (((timeout->tv_usec + 5000) / 10000) * tps) / 100;
+      }
+      else
+      {
+         ltv = (((timeout->tv_usec + 50000) / 100000) * tps) / 10;
+      }
+      ltv += (timeout->tv_sec * TPS);
+   }
+   else {
+      /*
+       * NULL timeout: wait indefinitely in t_select()
+       */
+      ltv = -1;
+   }
+
+   return (t_select(readfds, writefds, exceptfds, ltv));
+}
+#endif /* SO_SELECT */
+
+/* FUNCTION: bsd_setsockopt()
+ *
+ * Set a socket option value
+ *
+ * PARAM1: s; IN - socket descriptor 
+ * PARAM2: level; IN - the level of the option to set
+ * PARAM3: name; IN - the name of the option to set
+ * PARAM4: opt; OUT - ptr to buffer containing option value; may be
+ *              NULL
+ * PARAM5: optlen; IN - specifies the length in bytes of the option 
+ *                 value in opt
+ * RETURNS: 0 if successful, -1 if an error occurred.  The error is
+ *          available via bsd_errno(s).
+ */
+int 
+bsd_setsockopt(BSD_SOCKET s,
+               int level,
+               int name,
+               void * opt, int optlen)
+{
+   struct socket * so;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   /* make sure supplied option value is big enough for the 
+    * named option, else fail w/error EFAULT
+    */
+   if (optlen < bsd_i_sockoptlen(level, name))
+   {
+      so->so_error = EFAULT;
+      return -1;
+   }
+
+   return t_setsockopt(s, level, name, opt, optlen);
+}
+
+#endif /* BSD_SOCKETS */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cksum.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cksum.c
new file mode 100644
index 0000000..cd57570
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cksum.c
@@ -0,0 +1,233 @@
+/* FILE: cksum.c
+ *
+ * Internet checksum function
+ *
+ */
+ 
+#include "ipport.h"
+
+#ifdef ALTERA_NIOS
+#include "sys/alt_cache.h"
+#endif
+
+#ifndef C_CHECKSUM
+unsigned short asm_cksum (void *, unsigned);
+#endif
+#ifdef ALT_CKSUM
+unsigned short alt_cksum (void *, unsigned);
+#endif
+  
+/* Figure out how many checksum choices we have. There is always
+ * a C version. If 'C_CHECKSUM' is not defined, then we have an
+ * assembly version, and there is a third choice specifically for
+ * Altera NIOS-II systems.
+ */
+#ifdef ALT_CKSUM
+#define MAX_CKSUM_SELECT  3
+#else
+#ifndef C_CHECKSUM
+#define MAX_CKSUM_SELECT  2
+#else
+#define MAX_CKSUM_SELECT  1
+#endif
+#endif
+
+/* checksum algorithm selection 
+ * 1 = C code
+ * 2 = assembly language
+ * 3 = alternate checksum accelerator
+ */
+static int cksum_select = MAX_CKSUM_SELECT;
+
+
+/* FUNCTION: ccksum.c
+ *
+ * C language checksum example from RFC 1071
+ *
+ * PARAM1: ptr          pointer to data to be checksum-ed
+ * PARAM2: count        number of 16-bit words to process
+ *
+ * RETURN: ccksum       16-bit checksum value
+ *
+ * The InterNiche Stack guarentees that data is 16-bit aligned
+ * and odd byte lengths are padded with zero, so processing can
+ * be done in 16-bit chunks.
+ */
+
+unsigned short
+ccksum (void *ptr, unsigned words)
+{
+   unsigned short *addr = (unsigned short *)ptr;
+   unsigned long sum = 0;
+   int count = (int)words;
+
+   while (--count >= 0)
+   {
+      /*  This is the inner loop */
+      sum += *addr++;
+   }
+
+   /*  Fold 32-bit sum to 16 bits */
+   sum = (sum & 0xffff) + (sum >> 16);
+   sum = (sum & 0xffff) + (sum >> 16);
+
+   /* checksum = ~sum; *//* removed for MIT IP stack */
+   return ((unsigned short)sum);
+}
+
+
+
+/* FUNCTION: cksum
+ *
+ * Compute checksum using the function selected by "cksum_select"
+ *
+ * PARAM1: addr         pointer to data to be checksum-ed
+ * PARAM2: count        number of 16-bit words to process
+ *
+ * RETURN: ccksum       16-bit checksum value
+ *
+ * "cksum_select" selects which function is used to compute the checksum: 
+ *    1 = C implementation
+ *    2 = assembly language implementation
+ *    3 = user-supplied alternate implementation
+ */
+
+unsigned short
+cksum (void *ptr, unsigned count)
+{
+   switch (cksum_select)
+   {
+      case 1:
+      default:
+         return (ccksum(ptr, count));
+ #ifndef C_CHECKSUM
+      case 2:
+         return (asm_cksum(ptr, count));
+#endif
+#ifdef ALT_CKSUM
+      case 3:
+#ifdef ALTERA_NIOS2
+         alt_dcache_flush_all();
+         return (alt_cksum((void *)((unsigned long)ptr & 0x7FFFFFFF), count));
+#else
+#endif
+         return (alt_cksum(ptr, count));
+#endif
+   }
+}
+
+
+
+#ifdef IN_MENUS
+
+#include "menu.h"
+int do_cksum (void *);
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * add braces to remove build warning
+ */
+struct menu_op cksummenu[]  =  {  /* array of menu option, see menu.h */
+   { "chksum",   stooges,       "checksum menu" },    /* menu ID */
+   { "cksum",    do_cksum,      "set/get checksum selection" },
+   { NULL,       NULL,          NULL }
+};
+
+
+/* FUNCTION: cksum_init()
+ * 
+ * Install checksum test menu
+ * 
+ * PARAMS: none
+ * 
+ * RETURN: 0 if successful, otherwise non-zero error code
+ */
+
+int
+cksum_init(void)
+{
+   install_menu(cksummenu);
+   return (0); 
+}
+
+
+
+/* FUNCTION: cksum_alg
+ * 
+ * Selects which checksum algorithm to use
+ * 
+ * PARAM1: int alg      algorithm choice
+ *                        1 = C checksum
+ *                        2 = assembly language checksum (optional)
+ *                        3 = Altera CI checksum (optional)
+ * 
+ * RETURN: none
+ */
+
+void
+cksum_alg(int alg)
+{
+  if ((1 <= alg) && (alg <= MAX_CKSUM_SELECT))
+  {
+#if 1
+      cksum_select = alg;
+#else
+      cksum_select = 1;
+#endif
+  }
+}
+
+
+
+/* FUNCTION: which_cksum
+ * 
+ * Get the current checksum algorithm selection
+ * 
+ * PARAMS: none
+ * 
+ * RETURN: int            current value of cksum_select
+ */
+
+int
+which_cksum(void)
+{
+   return (cksum_select);
+}
+
+
+
+/* FUNCTION: do_cksum()
+ * 
+ * PARAM1: void *             console output descriptor
+ *
+ * RETURNS: int               0 if successful, else error code
+ */
+
+int
+do_cksum (void * pio)
+{
+   char *cp = nextarg(((GEN_IO)pio)->inbuf);
+   int value;
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio, "current checksum selection is %d\n", cksum_select);
+      ns_printf(pio, "valid selection range is: 1..%d\n", MAX_CKSUM_SELECT);
+      return (-1);
+   }
+   value = atol(cp);
+   if ((1 <= value) && (value <= MAX_CKSUM_SELECT))
+   {
+      cksum_alg(value);
+   }
+   else
+   {
+      ns_printf(pio, "invalid csum parameter value\n");
+      ns_printf(pio, "valid selection range is: 1..%d\n", MAX_CKSUM_SELECT);
+      return (-1);
+   }
+
+   return (0);
+}
+
+#endif  /* IN_MENUS */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cu_srv.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cu_srv.c
new file mode 100644
index 0000000..aa8f229
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/cu_srv.c
@@ -0,0 +1,613 @@
+/*
+ * FILENAME: cu_srv.c
+ *
+ * Copyright  2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Test program for TCP sockets API. Implements Crypto Engine server
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: tcp_scipher_init(), tcp_scipher_close(), tcp_cipher_cleanup(), 
+ * ROUTINES: tcp_cipher_init(), tcp_cipher_recv(), tcp_cipher_poll(), 
+ * ROUTINES: tcp_cipher_stats()
+ *
+ * PORTABLE: yes
+ */
+
+#include <string.h> 
+#include "ipport.h"     /* NetPort embedded system includes */
+
+#ifdef TCP_CIPHERTEST     /* whole file can be ifdeffed out */
+#include "ce.h"
+#include "cu_srv.h"
+
+#ifndef WINSOCK
+#include "tcpport.h"    /* NetPort embedded system includes */
+#include "in_utils.h"
+#ifndef sock_noblock
+#define  sock_noblock(sock,flag) setsockopt(sock,SOL_SOCKET,SO_NBIO,NULL,0)
+#endif
+#endif
+
+
+/* This global switch can be set prior to calling tcp_cipher_init() */
+int      tcpcipher_server =  TRUE;
+
+static int in_cipherpoll = 0;   /* re-entry flag */
+
+static SOCKTYPE elisten_sock =         INVALID_SOCKET; /* Crypto Engine server socket -
+                                                   listening socket descriptor */
+static SOCKTYPE esvr_sock    =         INVALID_SOCKET; /* Crypto Engine server active socket - 
+                                                   connected socket descriptor */
+
+/* Do we need to close the server's active socket? */
+static int      esvr_sock_close = FALSE;
+
+#ifdef NPDEBUG
+static void printBufferInHex(void *pio, unsigned char *buf, int len)
+{
+	ns_printf(pio, "tcp_cipher::printBufferInHex Input buffer = ");
+	if (buf == NULL) {
+		ns_printf(pio, "NULL \n");
+		return;
+	}
+	while (len)
+	{
+	        printf("%02x", *buf);
+		
+		if (--len>0)
+			buf++;
+	}
+	printf("\n");
+	return;
+}
+
+static void printBuffer(void *pio, unsigned char *buf, int len)
+{
+	ns_printf(pio, "tcp_cipher::printBuffer output buffer = ");
+	if (buf == NULL) {
+		ns_printf(pio, "NULL \n");
+		return;
+	}
+	while (len)
+	{
+	        ns_printf(pio, "%c", *buf);
+		
+		if (--len>0)
+			buf++;
+	}
+	ns_printf(pio, "\n");
+	return;
+}
+#endif
+
+/*static void copyStr(unsigned char *key, unsigned char c, int len)
+{
+	int i;
+	for (i=0; i<len; i++)
+	{
+		*key=c;
+		key++;
+	}
+}*/
+
+#ifdef NPDEBUG
+static void binary_op(void *pio, char byte)
+{
+   int count=8;				/* Number of bits in a byte.	*/
+
+   while(count--)
+      {
+					/* AND the high order bit (the
+					 * left one) If the bit is set,
+					 * print a ONE.			*/
+      ns_printf(pio, "%d", ( byte & 128 ) ? 1 : 0 );
+
+					/* Move all the bits LEFT.	*/
+      byte <<= 1;
+      } 
+
+   ns_printf(pio, "\n");
+}
+#endif
+
+static void cb(void *pio, void *conn, unsigned char *buf, int len, int status, int retCode)
+{
+   USE_ARG(retCode);
+	USE_VOID(conn);
+	USE_VOID(pio);
+	done=1;
+
+	if (status == CE_DONE) {
+		cipherOutBuf=buf;		
+		cipherOutBufLen=len;
+	}
+
+	return;
+}
+
+void tcpCipher_getCipherId(ServerInBuffer *srvInBufPtr)
+{
+	short cipherId;
+	int   e;          /* error holder */
+	cipherId=getCipherId(srvInBufPtr->encryptionAsymetricAlg,
+                        srvInBufPtr->encryptionSymetricAlg,
+				            srvInBufPtr->authenticationAlg);
+	srvOutBuf.cipherId=htons(cipherId);
+	e = send(esvr_sock, (char *)&srvOutBuf, sizeof(srvOutBuf), 0);
+	if (e < 0)
+	{
+		 /* Print the error to console */
+		e = t_errno(esvr_sock);
+		ns_printf(NULL,
+                 "TCP Crypto Engine server::tcpCipher_getCipherId, error %d sending reply\n", e);
+		dtrap();
+	}
+	return;
+}
+
+void tcpCipher_freeCipher(ServerInBuffer *srvInBufPtr)
+{	
+	freeCipher(srvInBufPtr->cipherId);
+	return;
+}
+
+void processInputBuffer(ServerInBuffer *srvInBufPtr)
+{
+	unsigned char flags;
+	int ret_code;
+	unsigned short cipherId;
+	unsigned short bufLen;
+	unsigned char *buffer=NULL;
+   unsigned char priv_key_len=16;
+   unsigned char iv_len=16;
+	
+   unsigned char priv_key[16]=
+		{0x6c,0x3e,0xa0,0x47,0x76,0x30,0xce,0x21,
+       0xa2,0xce,0x33,0x4a,0xa7,0x46,0xc2,0xcd};
+       
+   unsigned char iv[16]=
+		{0xc7,0x82,0xdc,0x4c,0x09,0x8c,0x66,0xcb,
+       0xd9,0xcd,0x27,0xd8,0x25,0x68,0x2c,0x81};       
+
+   struct securityParameters secParm;
+   struct inputParameters inpParm;           
+   
+   secParm.auth_key=NULL;
+   secParm.auth_key_len=0;
+   secParm.priv_key=priv_key;
+   secParm.priv_key_len=priv_key_len;
+   secParm.iv=iv;
+   secParm.iv_len=iv_len;
+   secParm.cipher_len=NULL;   
+		
+	if (srvInBufPtr->encryptionSymetricAlg>0)
+	{
+		ns_printf(NULL, "tcp_cipher::processInputBuffer encryptionSymetricAlg = %d \n",
+			             srvInBufPtr->encryptionSymetricAlg);
+		tcpCipher_getCipherId(srvInBufPtr);
+		return;
+	}
+
+   if (srvInBufPtr->action==DELETE_CIPHER)
+	{
+		ns_printf(NULL, "tcp_cipher::processInputBuffer encryptionSymetricAlg = %d \n",
+			             srvInBufPtr->encryptionSymetricAlg);
+		tcpCipher_freeCipher(srvInBufPtr);
+		return;
+	}
+
+	bufLen = ntohs(srvInBufPtr->bufLen);
+
+    flags=srvInBufPtr->flags;
+
+   #ifdef NPDEBUG
+	   binary_op(NULL, flags);
+   #endif
+
+    cipherId=ntohs(srvInBufPtr->cipherId);
+	
+   #ifdef NPDEBUG
+	   ns_printf(NULL, "cipher id = %x \n", cipherId);
+	   ns_printf(NULL, "flags = %x \n", flags);
+	   printBufferInHex(NULL, srvInBufPtr->buffer, bufLen);
+	   /*ns_printf(NULL, "buffer = %s \n", srvInBufPtr->buffer);*/
+	   ns_printf(NULL, "buffer length = %d \n", bufLen);
+   #endif
+
+	if (srvInBufPtr->bufLen>0)
+	{
+	    buffer = (unsigned char *)npalloc(bufLen);
+		MEMCPY(buffer, srvInBufPtr->buffer, bufLen);
+	}
+
+   #ifdef NPDEBUG
+	   ns_printf(NULL, "tcp_cipher::processInputBuffer buffer = ");
+	   printBufferInHex(NULL, srvInBufPtr->buffer, bufLen);
+   #endif
+
+	/*auth_key=(unsigned char *)npalloc(key_len);
+			
+	copyStr(auth_key, 0xaa, auth_key_len);*/
+   	
+	inpParm.cid=cipherId;
+   inpParm.flags=flags;
+   inpParm.pConn=NULL;
+   inpParm.inBuf=buffer;
+   inpParm.inBufLen=bufLen;
+   inpParm.outBuf=NULL;
+   inpParm.cb=cb;
+
+   ret_code=ce_crypt(NULL, 
+             &inpParm,
+             &secParm);
+   if (ret_code == SUCCESS)
+	    ce_do();
+	
+   #ifdef NPDEBUG
+	   ns_printf(NULL, "tcp_cipher::processInputBuffer done = %d \n", done);
+	   ns_printf(NULL, "tcp_cipher::processInputBuffer output buffer = \n");
+	   printBuffer(NULL, cipherOutBuf, cipherOutBufLen);		 		
+   #endif
+	
+	npfree(buffer);
+	buffer=NULL;	
+}
+
+void
+tcp_cipher_recv(void)
+{
+   int   len;        /* length of recv data */
+   int   e;          /* error holder */
+   unsigned i;       /* generic index */
+   int   count;      /* select return */
+   fd_set fd_recv;   /* fd for recv */
+   fd_set fd_accept; /* fd for accept */
+   struct sockaddr_in client;
+   SOCKTYPE tmpsock; /* scratch socket */  
+   ServerInBuffer srvInBuf;
+
+   if (elisten_sock == INVALID_SOCKET)
+      return;  /* Crypto Engine Server not set up, don't bother */
+
+#ifdef USE_FDS
+   /* initialize FD arrays */
+   FD_ZERO(&fd_recv);
+   FD_ZERO(&fd_accept);
+#endif
+
+   i = 0;
+   count = 0;
+   
+   if (tcpcipher_server)
+   {
+      if (esvr_sock != INVALID_SOCKET)
+      {
+#ifdef USE_FDS
+         FD_SET(esvr_sock, &fd_recv); 
+         ++i;
+#else
+         fd_recv.fd_array[i++] = esvr_sock;
+#endif
+         ns_printf(NULL, "added esvr_sock to fd_recv \n");
+      }
+   }
+
+#ifndef USE_FDS
+   fd_recv.fd_count = i;
+#endif
+
+   /* make this a short timeout since elisten may be created soon */
+   if (elisten_sock != INVALID_SOCKET)
+   {
+#ifdef USE_FDS
+      FD_SET(elisten_sock, &fd_accept);
+#else
+      fd_accept.fd_array[0] = elisten_sock;
+      fd_accept.fd_count = 1;	  
+
+#endif
+      count = t_select(&fd_recv, (fd_set *)NULL, &fd_accept, 1);	  
+   }
+   else 
+   {
+      if (i)   /* if no fd_set sockets filled in, don't bother */
+         count = t_select(&fd_recv, (fd_set *)NULL, (fd_set *)NULL, 1);
+   }
+
+   /* While the t_select() was executing, commands can be 
+    * executed from cmd-prompt and sockets can be cleaned up. 
+    * Check for that. 
+    */
+   if (elisten_sock == INVALID_SOCKET)
+      return;  /* Crypto Engine Server not set up, don't bother */
+
+   for (i = 0; i < fd_recv.fd_count; i++)
+   {
+#ifdef USE_FDS
+      tmpsock = FD_GET(i, &fd_recv);
+      if (tmpsock == INVALID_SOCKET)
+         continue;
+#else
+      tmpsock = fd_recv.fd_array[i];
+#endif
+      MEMSET((char *)&srvInBuf, 0, sizeof(srvInBuf));
+      len = recv(tmpsock, (char *)&srvInBuf, sizeof(srvInBuf), 0);
+
+      if (len > 0)
+      {
+         processInputBuffer(&srvInBuf);
+      }
+
+      if (len < 0)
+      {
+         e = t_errno(tmpsock);
+         if (e != EWOULDBLOCK)
+         {
+         ns_printf(NULL,"TCP Crypto Engine Server recv error %d\n", e);
+         }
+      }
+      else if (len == 0)
+      {
+         ns_printf(NULL,"TCPCipher:socket closed by other side\n");
+         socketclose(esvr_sock);
+         esvr_sock = INVALID_SOCKET;
+      }
+   }
+
+   if (done)
+   {
+#ifdef NPDEBUG
+      printBuffer(NULL, cipherOutBuf, cipherOutBufLen);
+#endif
+      e = send(esvr_sock, (char *)cipherOutBuf, cipherOutBufLen, 0);
+      if (e < 0)
+      {
+/* Print the error to console */
+         e = t_errno(esvr_sock);
+         ns_printf(NULL,
+               "TCP Crypto Engine Server server, error %d sending reply\n", e);
+      }
+      npfree(cipherOutBuf);
+      cipherOutBuf=NULL;
+      done=0;
+   }
+
+   /* if no server listen to poll, return now */
+   if (elisten_sock == INVALID_SOCKET)
+      return;
+
+#ifdef NOTDEF
+   MEMSET(&client, 0, sizeof(client));
+   client.sin_family = AF_INET;
+   client.sin_addr.s_addr = INADDR_ANY;
+   client.sin_port = htons(CIPHER_PORT);
+#endif
+
+   /* check for received client connection on server */
+   len = sizeof(client);
+   tmpsock = accept(elisten_sock, (struct sockaddr*)&client, &len );
+   if (tmpsock != INVALID_SOCKET)
+   {
+      if (esvr_sock == INVALID_SOCKET)
+      {
+         esvr_sock = tmpsock;
+      }
+      else  /* we already have a connection */
+      {
+         dprintf("tcpCipher: rejected extra connection\n");
+         socketclose(tmpsock);   /* refuse to serve another */
+      }
+   }
+}
+
+
+
+/* FUNCTION: tcp_cipher_poll()
+ * 
+ * Do routine processing for  Crypto Engine Server
+ * 1. Check if client packets have been received for TCP Crypto Engine 
+ *    Server. If yes, send a reply.
+ * 2. Check if Crypto Engine replys have been recieved for TCP Crypto Engine Clients.
+ *    If yes, update data structures, display messages.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_cipher_poll(void)
+{
+   if (elisten_sock == INVALID_SOCKET)
+      return;  /* Crypto Engine Server not set up, don't bother */
+
+   in_cipherpoll++;    /* don't re-enter from tk_yield() */
+   if (in_cipherpoll != 1)
+   {
+      in_cipherpoll--;
+      return;
+   }
+
+   tcp_cipher_recv();
+
+   in_cipherpoll--;
+}
+
+/* FUNCTION: tcp_scipher_init()
+ * 
+ * Initialize the TCP Crypto Engine Server. If the flag tcpcipher_server is false,
+ * then Server Init is not done.
+ * 
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int 
+tcp_scipher_init(void * pio)
+{
+   int   e;    /* error holder */
+   struct sockaddr_in   me;   /* my IP info, for bind() */
+   int   opt;
+
+   if (tcpcipher_server)
+   {
+      ns_printf(pio,"tcp Crypto Engine srv - starting.\n");
+
+      /* open TCP socket */
+      elisten_sock = socket(AF_INET, SOCK_STREAM, 0);
+      if (elisten_sock == INVALID_SOCKET)
+      {
+         ns_printf(pio,"TCP Crypto Engine: bad socket: %d\n", elisten_sock);
+         return TCPE_BAD_SOCKET ;
+      }
+
+      opt = 1;
+      e = t_setsockopt(elisten_sock, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt));
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         dtrap();
+         dprintf("error %d setting SO_REUSEADDR on port %d\n", e, CIPHER_PORT);
+         return SYS_SOCKETNULL;
+      }
+
+      me.sin_family = AF_INET;
+      me.sin_addr.s_addr = INADDR_ANY;
+      me.sin_port = htons(CIPHER_PORT);
+
+      e = bind(elisten_sock, (struct sockaddr*)&me, sizeof(me));
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         ns_printf(pio,"tcp_Cipher: bad socket bind: %d, %s\n", e, so_perror(e) );
+         socketclose(elisten_sock);
+         elisten_sock = INVALID_SOCKET;
+         return TCPE_BIND_FAILED ;
+      }
+      e = listen(elisten_sock, 3);
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         ns_printf(pio,"tcp_Cipher: bad socket listen: %d %s\n", e, so_perror(e));
+         socketclose(elisten_sock);
+         elisten_sock = INVALID_SOCKET;
+         return TCPE_LISTEN_FAILED;
+      }
+      /* for listen socket into Non-blocking mode so we can poll accept */
+      sock_noblock(elisten_sock, TRUE);
+   }
+   else
+      ns_printf(pio,"tcp Crypto Engine server not enabled\n");
+
+   return SUCCESS;
+}
+
+/* FUNCTION: tcp_cipher_init()
+ * 
+ * Initialize TCP Crypto Engine Server
+ * Remarks : This function has been defined so that a clean interface 
+ * is provided for TCP Crypto Engine Server.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_cipher_init(void)
+{
+   return tcp_scipher_init(NULL);
+}
+
+/* FUNCTION: tcp_scipher_close()
+ * 
+ * Close the TCP Crypto Engine Server.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_scipher_close(void * pio)
+{
+   int   e = 0;               /* scratch error holder */
+   int   retval = 0;          /* return last non-zero error */
+
+   if (esvr_sock != INVALID_SOCKET)
+   {
+      e = socketclose(esvr_sock);
+      if (e)
+      {
+         retval = e = t_errno(esvr_sock);
+         ns_printf(pio,"tcp Crypto Engine server: close error %d %s\n",
+                       e, so_perror(e));
+      }
+      else
+      {
+         ns_printf(pio,"tcp Crypto Engine srv - closing.\n");
+         esvr_sock = INVALID_SOCKET;
+      }
+   }
+
+   if (elisten_sock == INVALID_SOCKET)
+      return e;
+
+   e = socketclose(elisten_sock);
+   if (e)
+   {
+      retval = e = t_errno(elisten_sock);
+      ns_printf(pio,"tcp Crypto Engine: server close error %d %s\n",
+                    e, so_perror(e) );
+   }
+   elisten_sock = INVALID_SOCKET;
+
+   return retval;
+}
+
+
+
+/* FUNCTION: tcp_cipher_cleanup()
+ *
+ * Cleanup all TCP Crypto Engine related data structures.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_cipher_cleanup(void)
+{
+   tcp_scipher_close(NULL);
+}
+
+/* FUNCTION: tcp_cipher_stats()
+ * 
+ * Show statistics about all TCP Crypto Engine Clients and Servers
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_cipher_stats(void * pio)
+{
+   ns_printf(
+	   pio,"Showing TCP Crypto Engine statistics.\n");
+   if ( esvr_sock == INVALID_SOCKET )
+   {
+      ns_printf(pio,"   There are no Server connections.\n");
+   }
+   else
+   {
+      ns_printf(pio,"   There is one Server connection.\n");
+   }
+
+   return SUCCESS;
+}
+
+#endif   /* TCP_CIPHERTEST */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/dhcsetup.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/dhcsetup.c
new file mode 100644
index 0000000..a10cc78
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/dhcsetup.c
@@ -0,0 +1,184 @@
+/*
+ * FILENAME: dhcsetup.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *  This file is a place holder for functionality on top of 
+ * DHCP CLIENT. Presently it contains the DHCP CLIENT's setup 
+ * function. It initializes the DHCP Client and waits untill the DHCP 
+ * Client gets the IP Address.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: dhc_setup(), dhc_main_ipset()
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef DHCP_CLIENT
+#include "dhcpclnt.h"
+#include "nvparms.h"    /* For nvparms struct */
+#include "netbuf.h"     /* To remove warnings for net.h */
+#include "net.h"        /* For nets[] */
+#include "in_utils.h"   /* For netexit() */
+
+
+int dhc_main_ipset(int iface, int state);
+
+
+
+/* FUNCTION: dhc_setup()
+ *
+ * dhc_setup() : The setup function for DHCP Client. This function 
+ * interfaces with the DHCP Client.
+ * 1. It initializes the DHCP Client 
+ * 2. For each interface,
+ *    A. It checks if DHCP Client is needed to get the IP Address
+ *    B. If yes, it initializes the DHCP Client for 
+ *       that interface Also sets the callback.
+ *    C. Then it calls dhc_second() once, so that DHCP Client's state
+ *       machine gets a chance to start.
+ * 3. Waits till DHCP Client activity completes on 
+ *    all interfaces. Then it returns. If it doesn't conclude in 30 
+ *    seconds, it uses the old IP addresses and returns. 
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: void
+ */
+
+void
+dhc_setup(void)
+{  
+   int      iface;
+   ulong    dhcp_started;
+   ip_addr  dhcp_saveaddr[STATIC_NETS];
+   int      e;
+   int      dhcnets = 0;   /* number of nets doing DHCP */
+
+   e = dhc_init();
+
+   if (e)
+   {
+      printf("Error starting DHCP client code.\n");
+      netexit(1);
+   }
+
+   dhcp_started = cticks;  /* init timeout */
+
+   for (iface = 0; iface < STATIC_NETS; iface++)
+   {
+      if (!nets[iface])
+         continue; /* no valid iface for this network */
+
+#ifdef INCLUDE_NVPARMS
+      if (inet_nvparms.ifs[iface].client_dhcp)
+         nets[iface]->n_flags |= NF_DHCPC ; /* use DHCP Client on this iface */
+#endif   /* INCLUDE_NVPARMS */
+
+      if (!(nets[iface]->n_flags & NF_DHCPC))
+         continue;
+
+      /* If callback is not already in use (by AutoIP) grab it for
+       * our printf routine.
+       */
+      if(dhc_states[iface].callback == NULL)
+      {
+         dhc_set_callback(iface, dhc_main_ipset);
+      }
+
+      /* start DHCP on the iface - first save the default address */
+      dhcp_saveaddr[iface] = nets[iface]->n_ipaddr;
+
+      if (dhcp_saveaddr[iface] == 0L)  /* see if there is a default */
+         dhc_state_init(iface, TRUE);  /* Put DHCPClient in INIT state */
+      else
+         dhc_state_init(iface, FALSE); /* Put DHCPClient in INIT-REBOOT state */
+
+      e=dhc_second();                  /* To send the DISCOVER/REQUEST pkt */
+      if (e)
+      {
+         printf("Error sending DHCP packet on iface %d.\n", iface);
+         netexit(1);
+      }
+
+#ifndef USE_AUTOIP
+      /* If we are not using Auto IP then we want to block below waiting
+       * for DHCP completion. If we are using Auto IP then we want to
+       * return and let the Auto IP code handle the DHCP completion.
+       * "dhcnets" is a flag which allows this.
+       */
+      dhcnets++;
+#endif
+   }
+
+   if(dhcnets == 0)  /* no nets doing DHCP? */
+      return;
+      
+   /* wait for DHCP activity to conclude */
+   /* 
+    * Altera Niche Stack Nios port modification:
+    * Increase DHCP timeout to > 2 minutes 
+    */
+   while (((cticks - dhcp_started) < (130*TPS)) &&
+      (dhc_alldone() == FALSE))
+   {
+      /* let other tasks spin. This is required, since some systems
+       * increment cticks in tasks, or use a polling task to receive
+       * packets. Without this activity this loop will never exit.
+       */
+      tk_yield();
+      pktdemux();
+#ifdef SUPERLOOP
+      dhc_second ();
+#endif
+   }
+
+   if (dhc_alldone() == FALSE)   /* dhcp timed out? */
+   {
+      dprintf("DHCP timed out, going back to default IP address(es)\n");
+      /* go back to defaults */
+      for (iface = 0; iface < STATIC_NETS; iface++)
+      {
+         if (dhc_ifacedone(iface) == FALSE)
+         {
+            dhc_halt(iface);
+            nets[iface]->n_ipaddr = dhcp_saveaddr[iface];
+         }
+      }
+   }
+}
+
+
+/* FUNCTION: dhc_main_ipset()
+ * 
+ * callback when DHCP completes OK
+ *
+ * PARAM1: int iface
+ * PARAM2: int state
+ *
+ * RETURNS: 
+ */
+
+int
+dhc_main_ipset(int iface, int state)
+{
+   if ( state == DHCS_BOUND )
+   {
+      /* print IP address acquired through DHCP Client - for user's benefit */
+      printf("Acquired IP address via DHCP client for interface: %s\n",
+              nets[iface]->name);
+
+      printf("IP address : %s\n", print_ipad(nets[iface]->n_ipaddr));
+      printf("Subnet Mask: %s\n", print_ipad(nets[iface]->snmask));
+      printf("Gateway    : %s\n", print_ipad(nets[iface]->n_defgw));
+   }
+   return 0;
+}
+
+#endif   /* DHCP_CLIENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/genlist.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/genlist.c
new file mode 100644
index 0000000..5fc5b4a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/genlist.c
@@ -0,0 +1,904 @@
+/*
+ * FILENAME: genlist.c
+ *
+ * Copyright 1999- 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * GENERIC Implementation of a list. Used by SNMPv3, IPFILTER.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: niche_list_constructor(), niche_list_destructor(), 
+ * ROUTINES: niche_add(), niche_add_sorted(), niche_add_id_and_name(), 
+ * ROUTINES: niche_del(), niche_del_id(), 
+ * ROUTINES: niche_del_name(), niche_del_id_and_name(), 
+ * ROUTINES: niche_lookup_id(), niche_lookup_name(), 
+ * ROUTINES: niche_lookup_id_and_name(), niche_list_show(), niche_list_len(), 
+ * ROUTINES: niche_list_getat(), niche_element_show(), 
+ * ROUTINES: niche_lookup_multi_match(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* 
+ * 1999      - Implemented for use with SNMPv3 tables -AT-
+ * 2/21/2002 - Added niche_add_sorted() and moved from snmpv3 to misclib -AT-
+ */
+
+
+#include "genlist.h"
+
+#ifdef USE_GENLIST   /* If USE_GENLIST is supported, compile this file */
+
+/* Implementation notes 
+ * 1. Allocation done by niche_add*() routines for new elements
+ * 2. Free() done by niche_del*() routines for elements to be deleted.
+ * 3. Each element is assumed to have a "long id" and "char name[]" as
+ *    members
+ * 4. niche_list_destructor() deletes all elements from the list.
+ *
+ * Usability notes 
+ *
+ * WHEN CAN THIS GENERIC LIST BE USED ???
+ *
+ * It is perfect for the following requirements. The implementation has
+ * two fields ( number, name ) , and in places where only one of them is
+ * used for indexing, the other field can be used to store some other
+ * value, or left blank. If the "name" field is not to be  used, then
+ * the size of "char array" can be reduced to 1 char to save memory.
+ *
+ * 1. For a list having number based indexing
+ * 2. For a list having name based indexing
+ * 3. For a doubly indexed list based on number,name.
+ * In all the above cases, it is assumed that all entries can be 
+ * uniquely identfied based on the index. All the functions for
+ * list manipulation can be used as such. And the function
+ * "niche_lookup_multi_match()" has no significance in this context,
+ * and should not be used.
+ *
+ * 4. For a list having more than 2 indices.
+ * The addition and deletion functions remain the same. The LOOKUP problem
+ * in this case is that the "number,name" based dual index can't identify
+ * a unique entry. Hence a special function has been provided. Its
+ * "niche_lookup_multi_match()". It is an extenstion of the function
+ * "niche_lookup_id_and_name()". It accepts one more argument, which is
+ * a array of pointers. All the matched entries are returned via this array.
+ * This function returns the "number of entries in the array".
+ * 
+ *
+ *
+ * 1. call niche_list_constructor() to init a new list. For eg.
+ *    struct AppElement
+ *    {
+ *       long id;
+ *       char   name[MAX_NAME_LEN];
+ *    };
+ *
+ *    struct NicheList app_list;
+ *    NICHELIST p_app_list = &app_list;
+ *
+ *    niche_list_constructor(p_app_list,sizeof(AppElement));
+ *
+ * 2. Call niche_add*() to add elements to the list. For eg.
+ *    struct AppElement ele1 = { 1000, "router" };   
+ *    niche_add(p_app_list,&ele1);
+ *    niche_add_id_and_name(p_app_list,1000,"bridge");
+ *    niche_add_id_and_name(p_app_list,1000,"gateway");
+ *    niche_add_id_and_name(p_app_list,1001,"gateway");
+ * 3. Use niche_lookup*() to find elements in the list.
+ *    struct AppElement *ele2, *ele3;
+ *    ele2=niche_lookup_id(p_app_list,1000);  // Looks for first match 
+ *    if ( ele2 == NULL )
+ *    {
+ *       // not found 
+ *    }
+ *    ele3=niche_lookup_id_and_name(p_app_list,1000,"router");  
+ *    if ( ele3 == NULL )
+ *    {
+ *       // not found 
+ *    }
+ * 4. Use niche_del*() to delete elements from the list. For eg.
+ *    niche_del_id(p_app_list1000);  // Delete all elements with "id=1000"
+ *    niche_del_id_and_name(p_app_list1001,"gateway");
+ * 5. Use niche_list_destructor() delete all elements from the list.
+ *    niche_list_destructor(p_app_list);
+ */
+
+#ifndef V3_STATIC_TABLES
+
+/* FUNCTION: niche_list_constructor()
+ * 
+ * Initialize a list so that it can be used for storing data.
+ *
+ * PARAM1: NICHELIST list - List to be initialized
+ * PARAM2: int len_of_ele - Sizeof  each data element
+ *
+ * REMARKS: The list should be DEFINED/ALLOCATED in the calling program.
+ * This function just does initialization.
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_list_constructor(NICHELIST list, int len_of_ele)
+{
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   list->len_of_element =  len_of_ele  ;
+   list->head  =  NULL  ;
+   return   SUCCESS;
+}
+
+
+/* FUNCTION: niche_list_destructor()
+ * 
+ * Cleanup a list. That is remove all elements from the list.
+ *
+ * PARAM1: NICHELIST list - List to be cleaned up
+ *
+ * REMARKS: The list should be FREE'ED in the calling program.
+ * This function deletes all the elements in the list.
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_list_destructor(NICHELIST list)
+{
+   NICHE_ELE   tmp;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      list->head=tmp->next;
+      GEN_FREE(tmp->p_data);
+      GEN_FREE(tmp);
+      tmp=list->head;
+   }
+   return   SUCCESS;
+}
+
+
+/* FUNCTION: niche_add()
+ * 
+ * Add an element to the list.
+ *
+ * PARAM1: NICHELIST list
+ * Pointer to the list in reference. (IN/OUT)
+ * PARAM2: GEN_STRUCT ptr_data
+ * Pointer to the element (containing data) to be put. (IN)
+ *
+ * REMARKS: Nothing is done to the "element". Memory is allocated to
+ * store a new element, and then the new element is popullated
+ * and added to the list.
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_add(NICHELIST list, GEN_STRUCT ptr_data)
+{
+   NICHE_ELE   tmp;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   /* Allocate memory for the new element */
+   tmp   = (NICHE_ELE) GEN_ALLOC(sizeof(struct NicheElement));
+   if ( tmp == NULL )
+   {
+      return   NICHE_NO_MEM   ;
+   }
+
+   /* Allocate memory for the DATA to be stored in the element */
+
+   tmp->p_data = (GEN_STRUCT) GEN_ALLOC(list->len_of_element);
+   if ( tmp->p_data == NULL )
+   {
+      GEN_FREE(tmp);
+      return   NICHE_NO_MEM_FOR_DATA;
+   }
+
+   MEMCPY(tmp->p_data, ptr_data,list->len_of_element);   /* Fill up the data in it */
+   tmp->next   =  NULL  ;
+
+   /* Now add to the list */
+   if ( list->head == NULL )  /* List is empty */
+   {
+      list->head  =  tmp   ;        /* add as the first element */
+   }
+   else
+   {
+      /* If the element is in the list, then don't add a duplicate */
+      NICHE_ELE   ind_tmp;
+      ind_tmp  =  list->head  ;
+      while ( ind_tmp )
+      {
+         if ( MEMCMP(tmp->p_data, ind_tmp->p_data,list->len_of_element) == 0 )
+         {
+            GEN_FREE(tmp->p_data);
+            GEN_FREE(tmp);
+            return   NICHE_DUP_ENTRY;
+         }
+         ind_tmp=ind_tmp->next;
+      }
+
+      tmp->next   =  list->head;
+      list->head  =  tmp;
+   }  
+   return   SUCCESS;
+}
+
+/* FUNCTION: niche_add_sorted()
+ * 
+ * Add an element to the list such that the list remains sorted by "id".
+ *
+ * PARAM1: NICHELIST list
+ * Pointer to the list in reference. (IN/OUT)
+ * PARAM2: GEN_STRUCT ptr_data
+ * Pointer to the element (containing data) to be put. (IN)
+ *
+ * REMARKS: Nothing is done to the "element". Memory is allocated to
+ * store a new element, and then the new element is popullated
+ * and added to the list.
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_add_sorted(NICHELIST list, GEN_STRUCT ptr_data)
+{
+   NICHE_ELE newele;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   /* Allocate memory for the new element */
+   newele = (NICHE_ELE) GEN_ALLOC(sizeof(struct NicheElement));
+   if ( newele == NULL )
+   {
+      return   NICHE_NO_MEM   ;
+   }
+
+   /* Allocate memory for the DATA to be stored in the element */
+
+   newele->p_data = (GEN_STRUCT) GEN_ALLOC(list->len_of_element);
+   if ( newele->p_data == NULL )
+   {
+      GEN_FREE(newele);
+      return   NICHE_NO_MEM_FOR_DATA;
+   }
+
+   MEMCPY(newele->p_data, ptr_data,list->len_of_element);   /* Fill up the data in it */
+   newele->next   =  NULL  ;
+
+   /* Now add to the list */
+   if ( list->head == NULL )  /* List is empty */
+   {
+      list->head  =  newele   ;        /* add as the first element */
+   }
+   else if (list->head->p_data->id > newele->p_data->id)
+   {
+      newele->next = list->head;
+      list->head = newele   ;        /* add as the first element */
+   }
+   else
+   {
+      /* If the element is in the list, then don't add a duplicate */
+      NICHE_ELE tmpent;
+      NICHE_ELE saveent;
+      saveent = list->head  ;
+      tmpent = saveent->next;
+      while ( tmpent )
+      {
+         if (tmpent->p_data->id == newele->p_data->id)
+         {
+            /* Duplicate entry !!! Keep the new one */
+            GEN_FREE(tmpent->p_data);
+            tmpent->p_data = newele->p_data ;
+            GEN_FREE(newele);
+            return   NICHE_DUP_ENTRY;
+         }
+         if (tmpent->p_data->id > newele->p_data->id)
+         {
+            /* Insert the new entry before tmpent.  
+             * That is between saveent and tmpent. */
+            break;
+         }
+         /* update pointers to check the next item in the list */
+         saveent=tmpent;
+         tmpent=tmpent->next;
+      }
+      /* Insert the new entry after saveent */
+      newele->next=saveent->next;
+      saveent->next = newele;
+
+   }  
+   return   SUCCESS;
+}
+
+/* later: check for duplicate entries */
+
+/* FUNCTION: niche_add_id_and_name()
+ * 
+ * Add an element to the list.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long id - Id of the new element (IN)
+ * PARAM3: char *name - Name of the new element (IN)
+ *
+ * REMARKS: Nothing is done to the "element". Memory is allocated to
+ * store a new element, and then the new element is popullated
+ * and added to the list.
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_add_id_and_name(NICHELIST list, long id, char * name)
+{
+
+   GEN_STRUCT  tmp_ele;
+   int         ret_code;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp_ele  = (GEN_STRUCT) GEN_ALLOC (list->len_of_element);
+   if ( tmp_ele == NULL )
+   {
+      ret_code =  NICHE_ADD_NOT_ENOUGH_MEMORY;
+   }
+   else
+   {
+      tmp_ele->id =  id;
+      strcpy(tmp_ele->name, name);
+      ret_code = niche_add(list, tmp_ele);
+      GEN_FREE(tmp_ele);
+   }
+
+   return   ret_code;
+}
+
+
+
+/* FUNCTION: niche_del()
+ * 
+ * Delete an element from the list.  This should do an exact 
+ * match [of DATA] and delete the entry 
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: GEN_STRUCT ptr_data - Element to be deleted(IN)
+ *
+ * REMARKS: Memory is FREE'ED to for the element, and then the element 
+ * is removed from the list
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_del(NICHELIST list, GEN_STRUCT ptr_data)
+{
+   NICHE_ELE   tmp,prev;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=prev=list->head;
+
+   /* Check is list is empty */
+   if ( tmp == NULL )
+   {
+      return   NICHE_DEL_LIST_EMPTY ;
+   }
+
+   /* Check if the element is the first one in the list */
+   /* compare all the contents */
+   if (  MEMCMP ( tmp->p_data , ptr_data, list->len_of_element ) == 0 )
+   {
+      /* match found */
+      list->head=tmp->next;
+      GEN_FREE(tmp->p_data);
+      GEN_FREE(tmp);
+      return   SUCCESS;
+   }
+
+   tmp=prev->next;
+
+   while ( tmp )
+   {
+      if (  MEMCMP ( tmp->p_data , ptr_data, list->len_of_element ) == 0 )
+      {
+         /* match found */
+         prev->next=tmp->next;
+         GEN_FREE(tmp->p_data);
+         GEN_FREE(tmp);
+         return   SUCCESS;
+      }
+      else
+      {
+         prev=tmp;
+         tmp=tmp->next;
+      }
+   };
+
+   return   NICHE_DEL_NOT_FOUND;
+}
+
+
+/* FUNCTION: niche_del_id()
+ * 
+ * Delete an element from the list.
+ * Delete all entries where "id" is matched
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long    id - ID of the element (IN)
+ *
+ * REMARKS: Memory is FREE'ED to for the element, and then the element 
+ * is removed from the list
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_del_id(NICHELIST list, long    id)
+{
+   NICHE_ELE   tmp,prev;
+   int   del_cnt=0;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=prev=list->head;
+
+   /* Check if list is empty */
+   if ( tmp == NULL )
+   {
+      return   NICHE_DEL_LIST_EMPTY ;
+   }
+
+   /* Delete all the HEAD elements that match our condition */
+   do
+   {
+      /* Check if the element is the first one in the list */
+      if ( tmp->p_data->id == id ) 
+      {
+         /* match found */
+         list->head=tmp->next;
+         GEN_FREE(tmp->p_data);
+         GEN_FREE(tmp);
+         del_cnt++;
+      }
+      else
+      {
+         /* Match failed */
+         break;
+      }
+      tmp=prev=list->head;
+   }  while (list->head);
+
+      tmp=prev->next;
+
+   while ( tmp )
+   {
+      if ( tmp->p_data->id == id )
+      {
+         /* match found */
+         prev->next=tmp->next;
+         GEN_FREE(tmp->p_data);
+         GEN_FREE(tmp); 
+         tmp=prev->next;      /* point to the next element */
+         del_cnt++;
+      }
+      else
+      {
+         prev=tmp;
+         tmp=tmp->next;
+      }
+   };
+
+   if ( del_cnt == 0 )
+   {
+      return   NICHE_DEL_NOT_FOUND;
+   }
+   else
+   {
+      return   del_cnt;
+   }
+}
+
+
+/* FUNCTION: niche_del_name()
+ * 
+ * Delete an element from the list.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: char *name - Name of the element (IN)
+ *
+ * REMARKS: Memory is FREE'ED to for the element, and then the element 
+ * is removed from the list
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_del_name(NICHELIST list, char * name)
+{
+   NICHE_ELE   tmp,prev;
+   int   del_cnt=0;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=prev=list->head;
+
+   /* Check if list is empty */
+   if ( tmp == NULL )
+   {
+      return   NICHE_DEL_LIST_EMPTY ;
+   }
+
+   /* Delete all the HEAD elements that match our condition */
+   do
+   {
+      /* Check if the element is the first one in the list */
+      if ( strcmp(tmp->p_data->name, name) == 0 )
+      {
+         /* match found */
+         list->head=tmp->next;
+         GEN_FREE(tmp->p_data);
+         GEN_FREE(tmp);
+         del_cnt++;
+      }
+      else
+      {
+         /* Match failed */
+         break;
+      }
+      tmp=prev=list->head;
+   }  while (list->head);
+
+      tmp=prev->next;
+
+   while ( tmp )
+   {
+      if ( strcmp(tmp->p_data->name, name) == 0 ) 
+      {
+         /* match found */
+         prev->next=tmp->next;
+         GEN_FREE(tmp->p_data);
+         GEN_FREE(tmp);
+         del_cnt++;
+      }
+      else
+      {
+         prev=tmp;
+         tmp=tmp->next;
+      }
+   };
+
+   if ( del_cnt == 0 )
+   {
+      return   NICHE_DEL_NOT_FOUND;
+   }
+   else
+   {
+      return   del_cnt;
+   }
+}
+
+
+/* FUNCTION: niche_del_id_and_name()
+ * 
+ * Delete an element from the list.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long id - ID of the element (IN)
+ * PARAM3: char *name - Name of the element (IN)
+ *
+ * REMARKS: Memory is FREE'ED to for the element, and then the element 
+ * is removed from the list
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int        
+niche_del_id_and_name(NICHELIST list, long id, char * name)
+{
+   GEN_STRUCT  tmp_ele;
+   int         ret_code;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp_ele  = (GEN_STRUCT) GEN_ALLOC (list->len_of_element);
+   if ( tmp_ele == NULL )
+   {
+      ret_code =  NICHE_DEL_NOT_ENOUGH_MEMORY;
+   }
+   else
+   {
+      tmp_ele->id =  id;
+      strcpy(tmp_ele->name, name);
+      ret_code = niche_del(list, tmp_ele);
+      GEN_FREE(tmp_ele);
+   }
+
+   return   ret_code;
+}
+
+#endif /* ifndef of V3_STATIC_TABLES */
+
+/* FUNCTION: niche_lookup_id()
+ * 
+ * Lookup for the first element which has this ID.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long    id - ID of the element (IN)
+ *
+ * RETURNS: Pointer to the element or NULL (if not found)
+ */
+
+GEN_STRUCT  
+niche_lookup_id(NICHELIST list, long    id)
+{
+   NICHE_ELE   tmp;
+
+   if ( list == NULL )
+      return   NULL;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      if (tmp->p_data->id == id )
+      {
+         return (GEN_STRUCT)(tmp->p_data);
+      }
+      else
+      {
+         tmp=tmp->next;
+      }
+   }
+
+   return   NULL;
+}
+
+
+/* FUNCTION: niche_lookup_name()
+ * 
+ * Lookup for the first element which has this name.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: char *name - name of the element (IN)
+ *
+ * RETURNS: Pointer to the element or NULL (if not found)
+ */
+
+GEN_STRUCT  
+niche_lookup_name(NICHELIST list, char * name)
+{
+   NICHE_ELE   tmp;
+
+   if ( list == NULL )
+      return   NULL;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      if (strcmp(tmp->p_data->name, name) == 0 )
+      {
+         return (GEN_STRUCT)(tmp->p_data);
+      }
+      else
+      {
+         tmp=tmp->next;
+      }
+   }
+
+   return   NULL;
+}
+
+
+/* FUNCTION: niche_lookup_id_and_name()
+ * 
+ * Lookup for the first element which has this ID,name.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long    id - ID of the element (IN)
+ * PARAM3: char *name - name of the element (IN)
+ *
+ * RETURNS: Pointer to the element or NULL (if not found)
+ */
+
+GEN_STRUCT  
+niche_lookup_id_and_name(NICHELIST list, long    id, char * name)
+{
+   NICHE_ELE   tmp;
+
+   if ( list == NULL )
+      return   NULL;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      if ( ( tmp->p_data->id == id ) &&
+( strcmp(tmp->p_data->name, name) == 0 ) )
+      {
+         return (GEN_STRUCT)(tmp->p_data);
+      }
+      else
+      {
+         tmp=tmp->next;
+      }
+   }
+
+   return   NULL;
+}
+
+
+/* FUNCTION: niche_list_show()
+ * 
+ * List all elements in the list
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int niche_list_show(NICHELIST list)
+{
+   NICHE_ELE   tmp;
+   int   cnt=0;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      niche_element_show(tmp->p_data);
+      tmp=tmp->next;
+      cnt++;
+   }
+
+   if ( cnt == 0 )
+      printf("List is empty.\n");
+   else
+      printf("List length =%d.\n", cnt);
+
+   return   SUCCESS;
+}
+
+
+/* FUNCTION: niche_list_len()
+ * 
+ * 
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int niche_list_len(NICHELIST list)
+{
+   NICHE_ELE   tmp;
+   int   cnt=0;
+
+   if ( list == NULL )
+      return   NICHE_LISTPTR_INVALID;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      cnt++;
+      tmp=tmp->next;
+   }
+
+   return   cnt;
+}
+
+
+/* FUNCTION: niche_list_getat()
+ * 
+ * 
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: int index - Position of the item to be found. (0 based)
+ *
+ * RETURNS: Pointer to data (element at INDEX) or NULL
+ */
+
+GEN_STRUCT niche_list_getat(NICHELIST list, int index)
+{
+   NICHE_ELE   tmp;
+   int   cnt=0;
+
+   if ( list == NULL )
+      return   NULL;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      if ( cnt == index )
+      {
+         return   tmp->p_data;
+      }
+      cnt++;
+      tmp=tmp->next;
+   }
+
+   /* We don't have so many elements in the list */
+   return   NULL;
+}
+
+
+/* FUNCTION: niche_element_show()
+ * 
+ * Display the values of an element.
+ *
+ * PARAM1: GEN_STRUCT ptr_data - Pointer to the element. (IN)
+ *
+ * RETURNS: SUCCESS / error code
+ */
+
+int niche_element_show(GEN_STRUCT ptr_data)
+{
+   if ( ptr_data == NULL )
+      return   FAILURE;
+
+   printf("Id= %ld, name=%s\n", ptr_data->id,ptr_data->name);
+
+   return   SUCCESS;
+}
+
+/* FUNCTION: niche_lookup_multi_match()
+ * 
+ * Lookup for the first element which has this ID,name.
+ * Check the whole list , and return all the entries 
+ * where this condition is matched.
+ *
+ * PARAM1: NICHELIST list - Pointer to the list in reference. (IN/OUT)
+ * PARAM2: long id - ID of the element (IN)
+ * PARAM3: char *name - name of the element (IN)
+ * PARAM4: GEN_STRUCT matches[]
+ * An array of pointers to hold the MATCHED entries
+ * Maximum size of this array is assumed  to GEN_MAX_ARRAY
+ *
+ * RETURNS: Number of entries matched.
+ */
+
+int  
+niche_lookup_multi_match(NICHELIST list, long id, char * name, 
+   GEN_STRUCT  matches[])
+{
+   NICHE_ELE   tmp;
+   int   cnt=0;
+
+   if ( list == NULL )
+      return   0;
+
+   if ( matches == NULL )
+      return   0;
+
+   tmp=list->head;
+   while ( tmp )
+   {
+      if ( ( tmp->p_data->id == id ) &&
+         ( strcmp(tmp->p_data->name, name) == 0 ) )
+      {
+         matches[cnt]=tmp->p_data   ;
+         cnt++;
+      }
+      tmp=tmp->next;
+   }
+
+   return   cnt;
+}
+
+#endif   /* USE_GENLIST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/in_utils.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/in_utils.c
new file mode 100644
index 0000000..7c9b653
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/in_utils.c
@@ -0,0 +1,619 @@
+/*
+ * FILENAME: in_utils.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Misc commands for InterNiche menu system & diagnostic suite. 
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: do_trap(), nextarg(), hexdump(), print_ipad(), 
+ * ROUTINES: print_uptime(), panic(), print_eth(), uslash(), ns_printf(), 
+ * ROUTINES: std_out(), std_in(), con_page(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software */
+
+
+#include "ipport.h"
+#ifdef MQX
+#include <fio.h>
+#endif
+
+#if defined(NATIVE_PRINTF) || defined(PRINTF_STDARG)
+#include <stdarg.h>
+#endif
+
+#ifdef NATIVE_PRINTF
+#include <stdio.h>
+#endif
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "ether.h"
+#include "arp.h"
+#include "menu.h"
+#include "in_utils.h"
+
+
+
+/* FUNCTION: do_trap()
+ *
+ * try to hook system debugger
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 0
+ */
+
+int
+do_trap(void)
+{
+   dtrap();
+   return 0;
+}
+
+
+
+/* FUNCTION: nextarg()
+ *
+ * nextarg() - returns a pointer to next arg in string passed. args 
+ * are printable ascii sequences of chars delimited by spaces. If 
+ * string ends without more args, then a pointer to the NULL 
+ * terminating the string is returned. 
+ *
+ * 
+ * PARAM1: char * argp
+ *
+ * RETURNS:  pointer to next arg in string 
+ */
+
+char *   
+nextarg(char * argp)
+{
+   while (*argp > ' ')argp++; /* scan past current arg */
+      while (*argp == ' ')argp++;   /* scan past spaces */
+      return (argp);
+}
+
+
+
+/* FUNCTION: hexdump()
+ *
+ * hexdump() - does a hex dump to console of a passed buffer. The 
+ * buffer is declared as void so structs can be passed with the 
+ * Compiler fussing. 
+ *
+ * 
+ * PARAM1: void * pio
+ * PARAM2: void * buffer
+ * PARAM3: unsigned len
+ *
+ * RETURNS: void
+ */
+
+#define  HEX_BYTES_PER_LINE   16
+
+void
+hexdump(void * pio, void * buffer, unsigned len)
+{
+   u_char * data  =  (u_char *)buffer;
+   unsigned int count;
+   char  c;
+
+   while (len)
+   {
+      /* display data in hex */
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+         ns_printf(pio, "%02x ", *(data + count));
+      /* display data in ascii */
+      for (count = 0; (count < HEX_BYTES_PER_LINE) && (count < len); ++count)
+      {
+         c = *(data + count);
+         ns_printf(pio, "%c", ((c >= 0x20) && (c < 0x7f)) ? c : '.');
+      }
+      ns_printf(pio,"\n");
+      len -= count;
+      data += count;
+   }
+}
+
+
+
+/* FUNCTION: print_ipad()
+ *
+ * Formatted print of an IP address, deprecated in favor of PUSH_IPADDR() macro
+ *
+ * PARAM1: unsigned long ipaddr
+ *
+ * RETURNS: pointer to formatted text
+ */
+
+char     ipreturn[18];     /* buffer for return */
+
+char *   
+print_ipad(unsigned long ipaddr)
+{
+   struct l2b  ip;
+
+   ip.ip.iplong = ipaddr;
+   sprintf(ipreturn, "%u.%u.%u.%u", 
+    ip.ip.ipchar[0],
+    ip.ip.ipchar[1],
+    ip.ip.ipchar[2],
+    ip.ip.ipchar[3]);
+
+   return ipreturn;
+}
+
+
+
+/* FUNCTION: print_uptime()
+ *
+ * format a neat time string from a SNMP TIMETICKS
+ * uptime format variable.
+ *
+ * Note: NOT REENTRANT
+ * 
+ * PARAM1: unsigned long timetick
+ *
+ * RETURNS:  pointer to formatted text
+ */
+
+static char tistring[24];     /* buffer for return */
+
+char *   
+print_uptime(unsigned long timetick)
+{
+   unsigned seconds, minutes, hours;
+
+   timetick = timetick/100;   /* turn timetick into seconds */
+   seconds = (unsigned)(timetick%60);
+   timetick = timetick/60;    /* turn timetick into minutes */
+   minutes = (unsigned)(timetick%60);
+   timetick = timetick/60;    /* turn timetick into hours */
+   hours = (unsigned)(timetick%24);
+   timetick = timetick/24;    /* turn timetick into days */
+
+   if (timetick)  /* Is there a whole number of days? */
+      sprintf(tistring, "%ld days, %dh:%dm:%ds", 
+    timetick, hours, minutes, seconds);
+   else if (hours)
+      sprintf(tistring, "%d hours, %dm:%ds", hours, minutes, seconds);
+   else
+      sprintf(tistring, "%d minutes, %d sec.", minutes, seconds);
+   return tistring;
+}
+
+
+
+/* FUNCTION: panic()
+ *
+ * Fatal system error
+ *
+ * PARAM1: char *             error message
+ *
+ * RETURN: none
+ *
+ * Called if Software detects fatal system error. msg is
+ * a string describing problem. There is no return from this 
+ * routine. What this should do varies with the implementation. In a 
+ * testing or development environment it should print messages, hook 
+ * debuggers, etc. In an imbedded controller, it should probably try
+ * to restart (ie warmboot) the system. 
+ */
+
+/* allow to be ifdeffed out on systems which already have a panic */
+#ifndef PANIC_ALREADY
+
+void
+panic(char * msg)
+{
+   dprintf("panic: %s\n", msg);
+   dtrap();                   /* try to hook debugger */
+   netexit(1);                /* try to clean up */
+}
+#endif  /* PANIC_ALREADY */
+
+
+
+/* FUNCTION: print_eth()
+ *
+ * print_eth() - pretty-print an ethernet address. Hex chars can be 
+ * separated by "spacer" character passed. Returns a pointer to a tmp 
+ * buffer with the formatted address 
+ *
+ * 
+ * PARAM1: char * addr
+ * PARAM2: char spacer
+ *
+ * RETURNS:  pointer to formatted text
+ */
+
+char     eth_prt_buf[18];  /* buffer for return */
+
+char *   
+print_eth(char * addr, char spacer)
+{
+   int   i;
+   char *   out   =  eth_prt_buf;
+
+   /* loop through 6 bytes of ethernet address */
+   for (i = 0; i < 6; i++)
+   {
+      /* high nibble */
+      *out = (char)(((*addr >> 4) & 0x0f) + 0x30);
+      if (*out > '9')   /* need to make it A-F? */
+         (*out) += 7;
+      out++;
+
+      /* low nibble */
+      *out = (char)((*addr & 0x0f) + 0x30);  /* low nibble to digit */
+      if (*out > '9')   /* need to make it A-F? */
+         (*out) += 7;   /* eg 0x3a -> 0x41 ('A') */
+      out++;
+
+      /* optional spacer character */
+      if (spacer && i < 5)
+         *out++ = spacer;
+      addr++;
+   }
+   *out = 0;
+   return eth_prt_buf;
+}
+
+
+
+
+/* FUNCTION: uslash()
+ *
+ * uslash() - turn DOS slashes("\") into UNIX slashs ("/"). That's 
+ * not to imple that UNIX slashes are right or better, just to be 
+ * consistent. 
+ *
+ * 
+ * PARAM1: char * path
+ *
+ * RETURNS:  pointer to formatted text
+ */
+
+char *   
+uslash(char * path)
+{
+   char *   cp;
+
+   for (cp = path; *cp; cp++)
+      if (*cp == '\\')
+      *cp = '/';
+   return path;
+}
+
+
+
+/* FUNCTION: ns_printf()
+ *
+ * A generic printf() routine. It uses information from the
+ * GenericIO structure to send the output to appropriate device.
+ * Uses vsprintf() to make the output string.
+ * The GenericIO structure contains a pointer to the function to
+ * be used for device type (e.g. file, or telnet connection)
+ * and an id identifing the specific device. For example,
+ * for printing to a file, the function would point to fprintf 
+ * and the id would be handle to file.
+ *
+ * PARAM1: void * vio      - Pointer to GenericIO structure (IN)
+ * PARAM2: char * format   - Format string
+ * followed by parameters as in printf.
+ * PARAM3: ...             - variables to format
+ *
+ * RETURNS: Number of bytes that were output, or a negative error
+ * code if an error occured.
+ */
+
+/* First use #defines to set memory & output for this system: */
+
+#if 0
+#ifndef npalloc
+extern   char * npalloc(unsigned);
+#endif   /* npalloc */
+#ifndef npfree
+void           npfree (void *);
+#endif   /* npfree */
+
+#ifndef NATIVE_PRINTF
+#ifdef PRINTF_STDARG
+int doprint(char *target, unsigned tlen, CONST char *sp, va_list va);
+#else
+int doprint(char *target, unsigned tlen, CONST char *sp, int FAR * vp);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+#endif
+
+/* ns_printf's output can be directed to goto /dev/null. In such
+ * cases, we don't want the following implementation and can omit
+ * it with this ifdef:
+ */
+#ifndef ns_printf
+
+int 
+ns_printf(void * vio, char * format, ...)
+{
+   char *   outbuf=NULL;
+   int   ret_value   ;
+   int   buf_size =  MAXIOSIZE   ;
+   GEN_IO pio = (GEN_IO)vio;  /* convert void* to our IO device type */
+
+#if defined(NATIVE_PRINTF) || defined(PRINTF_STDARG)
+   va_list argList;
+#else /* NATIVE_PRINTF || PRINTF_STRING */
+   int * next_arg=(int *)  &format;
+   next_arg +=  sizeof(char *)/sizeof(int) ;
+#endif   /* NATIVE_PRINTF || PRINTF_STRING */
+
+   /* a NULL pio means just dump the output to stdout */
+   if (pio == NULL)
+   {
+#ifdef NATIVE_PRINTF
+      /* use the target system's ANSI routines */
+      va_start(argList,format);
+      ret_value = vprintf(format,argList);
+      va_end(argList);
+      return ret_value;
+#else /* not NATIVE_PRINTF */
+      /* use our homegrown versions */
+#ifdef PRINTF_STDARG
+      va_start(argList,format);
+      doprint(NULL,0,format,argList);
+      va_end(argList);
+#else    /* not PRINTF_STDARG */
+      doprint(NULL,0,format,next_arg);
+#endif   /* PRINTF_STDARG */
+      /* The return value here is not accurate-later */
+      return strlen(format);
+#endif   /* NATIVE_PRINTF */
+   }
+
+   /* Check if the output function is set */
+   if (pio->out == NULL)
+   {
+      /* Programming mistake. Output function not set. */
+      return -1;
+   }
+
+   /* Allocate memory for the output string 
+    * If the format string is greater than MAXIOSIZE, then
+    * we surely need to allocate a bigger block
+    */
+   ret_value = strlen(format); 
+   if (ret_value >= MAXIOSIZE)
+   {
+      buf_size += ret_value ;
+   }
+
+   outbuf=(char *)npalloc(buf_size); 
+
+   if (outbuf == NULL)
+   {
+      return -2;
+   }
+
+   /* Now populate the output string */
+
+#ifdef NATIVE_PRINTF
+   /* use the target system's ANSI routines */
+   va_start(argList,format);
+   ret_value = vsprintf(outbuf,format,argList);
+   va_end(argList);
+#else /* NATIVE_PRINTF */
+   /* use the homegrown routines */
+#ifdef PRINTF_STDARG
+   va_start(argList,format);
+   doprint(outbuf,buf_size,format,argList);
+   va_end(argList);
+#else    /* not PRINTF_STDARG */
+   doprint(outbuf,buf_size,format,next_arg);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+
+#ifdef NATIVE_PRINTF
+   /* Check if we have overwritten the output buffer */
+   if ((int)strlen(outbuf) > buf_size)
+   {
+      /* Might want a more robust determination of whether outbuf 
+       * got overflowed, like putting a magic number at the end of it 
+       * before vsprintf call and verifying its still there afterwards
+       */
+      /* Yes , we have overwritten. Truncate the output string.
+       * Some memory in the heap has been corrupted, but it is too
+       * late to rectify.
+       */
+      panic("ns_printf:Buffer overflow");
+      outbuf[buf_size-1]=0;   /* Null terminate the string */
+   }
+#endif
+
+   ret_value =(pio->out)(pio->id,outbuf,strlen(outbuf)) ;
+
+   /* Free memory for the output string */
+   npfree(outbuf); 
+
+   /* since ns_printf() can get called repeatedly down in the bowels 
+    * of a single command interpretting function, spin tk_yield() so 
+    * that some packets get a chance to get received 
+    */
+   tk_yield();
+
+   return ret_value ;
+}
+#endif      /* ns_printf */
+
+
+
+/* FUNCTION: std_out()
+ *
+ * Function which outputs the contents to standard output.
+ * This function can be used with the GenericIO structure.
+ *
+ * PARAM1: long s    - Index to the output device. As there is only one
+ *         output device for standard output, this value
+ *         will not be meaningful to this function. (IN)
+ * PARAM2: char *buf - Buffer of data (IN)
+ * PARAM3: int len   - Length of data in buffer (IN)
+ *         Length is needed so that we can output hex data also.
+ *
+ * RETURNS: Number of bytes send to standard output. 
+ */
+
+int std_out(long s, char * buf, int len)
+{
+   /* puts(buf); - This does newline expansion return 
+    * write(0,buf,len); - This doesn't printf(buf); - This has 
+    * problems when printf format strings (eg %s) is part of data. 
+    */
+   printf("%s",buf);
+   USE_ARG(s);
+   return len;
+}
+
+#ifdef IN_MENUS
+
+
+/* FUNCTION: std_in()
+ *
+ * Returns the value of input char. Returns 0 if no char ready.
+ *
+ * PARAM1: long s - may someday be a device descriptor.
+ *
+ * RETURNS: Returns the input char, or 0 if no char ready.
+ */
+
+extern   int kbhit(void);
+extern   int getch(void);
+
+int 
+std_in(long s)
+{
+   USE_ARG(s);
+
+#ifdef MQX
+   return (getchar ());
+#else
+   if (!kbhit())
+   {
+      return 0;
+   }
+   else
+   {
+      return (getch());
+   }
+#endif
+}
+
+#endif   /* IN_MENUS */
+
+
+
+/* FUNCTION: con_page()
+ *
+ *  implement simple 'page' mechanism.  Blocks respectfully (other
+ * tasks not blocked) until some input arrives.
+ *
+ * PARAM1: void * vio   - Pointer to GEN_IO structure (IN)
+ * PARAM2: int lines    - Current line count (IN)
+ *
+ * RETURNS: 1 if we got a break, 0 to keep printing
+ */
+
+int
+con_page(void * vio, int lines)
+{
+   int   ch;
+   GEN_IO pio = (GEN_IO)vio;  /* convert void* to our IO device type */
+
+   if (lines % 20 == 0)   /* Time to get user input */
+   {
+      if (pio && pio->getch)   /*if i/p func is supplied*/
+      {
+         ns_printf(pio,"....press any key for more (ESC to break)....");
+
+         do 
+         {
+            ch = (pio->getch)(pio->id);
+            if (ch == 0)
+               tk_yield();    /* Give timeslice to other processes */
+         } while (ch == 0) ;
+
+            /* if there is fatal error, we don't want to do any I/O */
+         if (ch == -1)   /* fatal error */
+            return 1 ;
+
+         ns_printf(pio,"\n");
+         if (ch == 27)   /* ESC key pressed */
+            return 1 ;
+      }
+   }
+   return  0;
+}
+
+char **parse_args(char *buf, int argc, int *pargc_index)
+{
+   /* This routine assumes buf is a null terminated string */
+   int i;
+   int len;
+   char *bp = buf;
+   char **pargv = NULL;
+   *pargc_index = 0;
+   if (buf == NULL)
+   {
+      return (NULL);
+   }
+   len = strlen(buf);
+   if (len <= 0)
+   {
+      return (NULL);
+   }
+   pargv = (char **) npalloc(argc * sizeof(char *));
+   if (pargv == NULL)
+   {
+      return (NULL);
+   }
+   /* skip the initial blanks if any */
+   while (*bp == ' ')
+   {
+      bp++;
+   }
+   while ((*bp != '\0') && ((*pargc_index) < argc))
+   {
+      pargv[(*pargc_index)] = bp;
+      (*pargc_index)++;
+      while (*bp != ' ' && *bp != '\0')
+      {
+         bp++; 
+      }
+      while (*bp == ' ' && *bp != '\0')
+      {
+         bp++; 
+      }
+   }
+   for (i = 0; i < len; i++)
+   {
+      if (buf[i] == ' ')
+         buf[i] = '\0';
+   }
+
+#if 0
+   for (i = 0; i < *pargc_index; i++)
+   {
+      printf("pargv[%d] = %s\n", i, pargv[i]);
+   }
+#endif
+
+   return (pargv);
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_log.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_log.c
new file mode 100644
index 0000000..f7b9bd7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_log.c
@@ -0,0 +1,326 @@
+
+#include "ipport.h"
+
+#ifdef INCLUDE_INICHE_LOG
+
+#include <time.h>
+
+#include "iniche_log_port.h"
+#include "iniche_log.h"
+
+#include "in_utils.h"
+
+#ifdef ENABLE_SSL
+#include "../ssl/ssl_cfg.h"
+#endif
+
+#ifdef SSLDEBUG
+extern int sslverbose;
+#endif
+
+#include "menu.h"
+
+extern time_t convLocalTimeToString(char *timeBuffer);
+
+log_data_t *p_global_log = NULL;
+
+
+static char *logTypeStr[LOG_TYPE_MAX_NUM] = 
+{
+   "NONE", /* LOG_TYPE_NONE */
+   "FATAL", /* LOG_TYPE_FATAL */
+   "CRITICAL", /* LOG_TYPE_CRITICAL */
+   "MAJOR", /* LOG_TYPE_MAJOR */
+   "MINOR", /* LOG_TYPE_MINOR */
+   "WARNING", /* LOG_TYPE_WARNING */
+   "INFO", /* LOG_TYPE_INFO */
+   "DEBUG", /* LOG_TYPE_DEBUG */
+};
+
+void iniche_free_log(log_data_t **p)
+{
+   if(*p == NULL)
+   {
+      return;
+   }
+#ifdef USE_LOGFILE
+   if((*p)->log_fp)
+   {
+      nv_fclose((*p)->log_fp);
+      (*p)->log_fp = NULL;
+   }
+#endif
+   if((*p)->argv)
+   {
+      LOG_FREE((*p)->argv);
+      (*p)->argv = NULL;
+   }
+   LOG_FREE(*p);
+   *p = NULL;
+}
+
+int iniche_create_log(log_data_t **p, int log_level, char *fname, void *pio)
+{
+   int i;
+   /* This routine assumes a NULL pointer is passed */
+   if(*p == NULL)
+   {
+      *p = (log_data_t *) LOG_MALLOC(sizeof(log_data_t));
+      if(*p == NULL)
+      {
+         return(-1);
+      }
+      memset(*p, 0, sizeof(log_data_t));
+   }
+   else
+   {
+      for(i = 0; i < LOG_TYPE_MAX_NUM; i++)
+      {
+         (*p)->log_counts[i] = 0;
+      }
+   }
+   if((log_level >= LOG_TYPE_NONE) && (log_level < LOG_TYPE_MAX_NUM))
+   {
+      (*p)->log_level = log_level;
+   }
+   else
+   {
+      (*p)->log_level = DEFAULT_LOG_LEVEL;
+   }
+#ifdef USE_LOGFILE
+   if(fname)
+   {
+      strcpy((*p)->log_fname, fname);
+   }
+   else
+   {
+      strcpy((*p)->log_fname, LOG_FILE_DEFAULT);
+   }
+   if((*p)->log_fp)
+   {
+      nv_fclose((*p)->log_fp);
+      (*p)->log_fp = NULL;
+   }
+   (*p)->log_fp = nv_fopen((*p)->log_fname, "w");
+   if((*p)->log_fp == NULL)
+   {
+      iniche_free_log(p);
+      return(-1);
+   }
+#endif
+   (*p)->pio = pio;
+   return(0);
+}
+
+void log_with_type(log_data_t *p, logTypeEnum log_type, char *pstr, int printf_flag)
+{
+   char timeBuffer[100];
+   if(log_type >  LOG_TYPE_NONE && log_type < LOG_TYPE_MAX_NUM)
+   {
+      if(p == NULL)
+      {
+         return;
+      }
+      if(log_type > p->log_level)
+      {
+         return;
+      }
+      p->log_counts[log_type]++;
+      if(pstr)
+      {
+         convLocalTimeToString(timeBuffer);
+#ifdef USE_LOGFILE
+         if(p->log_fp)
+         {
+            nv_fprintf(p->log_fp, "%s %lu %s %s\n", logTypeStr[log_type], p->log_counts[log_type], timeBuffer, pstr);
+         }
+#endif
+         if(printf_flag)
+         {
+            ns_printf(p->pio, "%s %lu %s %s\n", logTypeStr[log_type], p->log_counts[log_type], timeBuffer, pstr);
+         }
+      }
+   }
+}   /* log_with_type() */
+
+void glog_with_type(logTypeEnum log_type, char *pstr, int printf_flag)
+{
+   log_data_t *p = p_global_log;
+   log_with_type(p, log_type, pstr, printf_flag);
+}   /* glog_with_type() */
+
+int global_log_create(void)
+{
+   return(iniche_create_log(&p_global_log, DEFAULT_LOG_LEVEL, LOG_FILE_DEFAULT, NULL));
+}
+
+void global_log_free(void)
+{
+   iniche_free_log(&p_global_log);
+}
+
+void glog_usage(log_data_t *p)
+{
+   ns_printf(p->pio, "\n"); 
+   ns_printf(p->pio, "usage: glog [options]\n"); 
+   ns_printf(p->pio, "options:  [stop]\n"); 
+   ns_printf(p->pio, "          [start]\n"); 
+   ns_printf(p->pio, "          [info]\n"); 
+   ns_printf(p->pio, "          [<module_name> <debug_flag>]\n"); 
+   ns_printf(p->pio, "          [-l <log_level = 0, 1, .., 7>]\n");    
+#ifdef USE_LOGFILE
+   ns_printf(p->pio, "          [-f <file_name>]\n");    
+#endif
+}
+
+void glog_info(log_data_t *p)
+{
+   ns_printf(p->pio, "\n"); 
+   ns_printf(p->pio, "glog info:\n"); 
+   ns_printf(p->pio, "glog level = %d [%s] \n", p->log_level, logTypeStr[p->log_level]);
+#ifdef USE_LOGFILE
+   ns_printf(p->pio, "glog filename = %s\n", p->log_fname);
+#endif
+#ifdef SSLDEBUG
+   ns_printf(p->pio, "module: ssl: flags = %x\n", sslverbose);
+#endif
+}
+
+int glog_process_args(log_data_t *p)
+{
+   if(p->argc < 2)
+   {
+      glog_usage(p);
+      return(0);
+   }
+   else if(p->argc == 2)
+   {
+      /* In this case we have a default server on the passed port as a parameter */
+      if(strcmp(p->argv[1], "?") == 0)
+      {
+         glog_usage(p);
+         return(0);
+      }
+      else if(strcmp(p->argv[1], "info") == 0) 
+	  {
+         glog_info(p);
+         return(0);
+      }
+   }
+   if(p->argc >= 2)
+   {
+      int i = 1; 
+      while(i < p->argc)
+      {
+         if(strcmp(p->argv[i], "start") == 0) 
+	     {
+            p->start_flag = 1;
+            i += 1;
+         }
+         else if(strcmp(p->argv[i], "stop") == 0) 
+	     {
+            p->stop_flag = 1;
+            i += 1;
+         }
+         else if(strcmp(p->argv[i], "-l") == 0) 
+	     {
+            p->log_level = atoi(p->argv[i+1]);
+            i += 2;
+         }
+#ifdef USE_LOGFILE
+         else if(strcmp(p->argv[i], "-f") == 0) 
+	     {
+            strcpy(p->log_fname, p->argv[i+1]);
+            i += 2;
+         }
+#endif
+#ifdef SSLDEBUG
+         else if(strcmp(p->argv[i], "ssl") == 0) 
+	     {
+            sslverbose = atoi(p->argv[i+1]);
+            i += 2;
+         }
+#endif
+         else
+         {
+            ns_printf(p->pio, "invalid option: %s\n", p->argv[i]);
+            return(-1);
+         }
+      }
+   }   
+   return(0);
+}
+
+int glog_app(void * pio)
+{
+   int i;
+   char *buf;
+   buf = (char *) ((GEN_IO)pio)->inbuf;
+   ns_printf(pio,"%s\n", buf);
+   if(p_global_log == NULL)
+   {
+      p_global_log = (log_data_t *) LOG_MALLOC(sizeof(log_data_t));
+      if(p_global_log == NULL)
+      {
+         ns_printf(pio,"glog_app: LOG_MALLOC() failed\n");
+         return(-1);
+      }
+      memset(p_global_log, 0, sizeof(log_data_t));      
+      p_global_log->log_level = DEFAULT_LOG_LEVEL;
+#ifdef USE_LOGFILE
+      strcpy(p_global_log->log_fname, LOG_FILE_DEFAULT);
+#endif
+   }
+   if(p_global_log->argv)
+   {
+      LOG_FREE(p_global_log->argv);
+      p_global_log->argv = NULL;
+   }
+   p_global_log->argv = parse_args(buf, GLOG_MAX_ARGC, &(p_global_log->argc));
+   if(p_global_log->argv == NULL)
+   {
+      ns_printf(pio, "parse_args() failed for %s\n", buf);
+      return(-1);
+   }   
+#if 0
+   for(i = 0; i < p_global_log->argc; i++)
+   {
+      ns_printf(pio, "%s ", p_global_log->argv[i]);
+   }
+   ns_printf(pio,"\n");
+#endif
+   if(glog_process_args(p_global_log))
+   {
+      ns_printf(pio, "glog_process_args() failed\n");
+      return(-1);
+   }
+   /* Here now we can configure our log app */
+   if(p_global_log->stop_flag)
+   {
+      glog_with_type(LOG_TYPE_INFO, "INICHE LOG stopped", 1);
+      iniche_free_log(&p_global_log);
+      return(0);
+   }
+   
+   if(p_global_log->start_flag)
+   {
+#ifdef USE_LOGFILE
+      if(iniche_create_log(&p_global_log, p_global_log->log_level, p_global_log->log_fname, pio))
+#else
+      if(iniche_create_log(&p_global_log, p_global_log->log_level, NULL, pio))
+#endif
+      {
+         ns_printf(pio,"iniche_create_log() failed\n");
+      }
+      else
+      {
+         ns_printf(pio,"starting glog:\n");
+         glog_with_type(LOG_TYPE_INFO, "INICHE LOG initialized", 1);
+      }
+      p_global_log->start_flag = 0;
+   }
+   return 0;
+}
+
+#endif /* INCLUDE_INICHE_LOG */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_qsort.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_qsort.c
new file mode 100644
index 0000000..a112e8c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/iniche_qsort.c
@@ -0,0 +1,174 @@
+
+#include "ipport.h"
+
+#ifdef INCLUDE_QSORT
+
+#define CUTOFF 8
+
+static void shortsort(char *lo, char *hi, unsigned width, int (*comp)(const void *, const void *));
+static void swap(char *p, char *q, unsigned int width);
+
+void iniche_qsort(void *base, unsigned num, unsigned width, int (*comp)(const void *, const void *))
+{
+  char *lo, *hi;
+  char *mid;
+  char *loguy, *higuy;
+  unsigned size;
+  char *lostk[30], *histk[30];
+  int stkptr;
+
+  if (num < 2 || width == 0) return;
+  stkptr = 0;
+
+  lo = base;
+  hi = (char *) base + width * (num - 1);
+
+recurse:
+  size = (hi - lo) / width + 1;
+
+  if (size <= CUTOFF) 
+  {
+    shortsort(lo, hi, width, comp);
+  }
+  else 
+  {
+    mid = lo + (size / 2) * width;
+    swap(mid, lo, width);
+
+    loguy = lo;
+    higuy = hi + width;
+
+    for (;;) 
+    {
+      do { loguy += width; } while (loguy <= hi && comp(loguy, lo) <= 0);
+      do { higuy -= width; } while (higuy > lo && comp(higuy, lo) >= 0);
+      if (higuy < loguy) break;
+      swap(loguy, higuy, width);
+    }
+
+    swap(lo, higuy, width);
+
+    if (higuy - 1 - lo >= hi - loguy) 
+    {
+      if (lo + width < higuy) 
+      {
+        lostk[stkptr] = lo;
+        histk[stkptr] = higuy - width;
+        ++stkptr;
+      }
+
+      if (loguy < hi) 
+      {
+        lo = loguy;
+        goto recurse;
+      }
+    }
+    else
+    {
+      if (loguy < hi) 
+      {
+        lostk[stkptr] = loguy;
+        histk[stkptr] = hi;
+        ++stkptr;
+      }
+
+      if (lo + width < higuy) 
+      {
+        hi = higuy - width;
+        goto recurse;
+      }
+    }
+  }
+
+  --stkptr;
+  if (stkptr >= 0) 
+  {
+    lo = lostk[stkptr];
+    hi = histk[stkptr];
+    goto recurse;
+  }
+  else
+    return;
+}
+
+static void shortsort(char *lo, char *hi, unsigned width, int (*comp)(const void *, const void *))
+{
+  char *p, *max;
+
+  while (hi > lo) 
+  {
+    max = lo;
+    for (p = lo+width; p <= hi; p += width) if (comp(p, max) > 0) max = p;
+    swap(max, hi, width);
+    hi -= width;
+  }
+}
+
+static void swap(char *a, char *b, unsigned width)
+{
+  char tmp;
+
+  if (a != b)
+  {
+    while (width--) 
+    {
+      tmp = *a;
+      *a++ = *b;
+      *b++ = tmp;
+    }
+  }
+}
+
+void *iniche_bsearch(const void *key,
+   const void *base0, size_t nmemb, size_t size,
+   int (*compar)(const void *, const void *)) 
+{  
+   const char *base = base0;
+   size_t lim;
+   int cmp;
+   const void *p;  
+   for(lim = nmemb; lim != 0; lim >>= 1) 
+   {
+      p = base + (lim >> 1) * size;
+      cmp = (*compar)(key, p);
+      if (cmp == 0)
+         return ((void *)p);
+      if (cmp > 0) 
+      {  /* key > p: move right */
+         base = (char *)p + size;
+         lim--;
+      }  /* else move left */
+   }
+   return(NULL);
+}
+
+#if 0
+void iniche_swap(void *v[], int i, int j)
+{
+   void *temp;
+   temp = v[i];
+   v[i] = v[j];
+   v[j] = temp;
+}
+
+void iniche_qsort(void *v[], int left, int right, int (*comp)(void *, void *))
+{
+   int i, last;
+   void swap(void *v[], int, int);
+   if(left >= right)
+      return;
+   iniche_swap(v, left, (left+right)/2);
+   last = left;
+   for(i = left+1, i <= right; i++)
+   {
+      if((*comp)(v[i], v[left]) < 0)
+      {
+         iniche_swap(v, ++last, i);
+      }
+   }
+   iniche_swap(v, left, last);
+   iniche_qsort(v, left, last-1, comp);
+   iniche_qsort(v, last+1, right, comp);
+}
+#endif
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/localtime.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/localtime.c
new file mode 100644
index 0000000..22a51fa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/localtime.c
@@ -0,0 +1,115 @@
+
+#include "ipport.h"
+
+#include <time.h>
+
+#ifdef INCLUDE_LOCAL_TIME
+
+#define BASE_YEAR	1970
+#define START_WDAY	4	/* constant. don't change */
+#define SECS_PER_MIN	60
+#define SECS_PER_HOUR	(SECS_PER_MIN*60)
+#define SECS_PER_DAY	(SECS_PER_HOUR*24)
+
+static unsigned int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+static unsigned long tzoffset;		/* timezone offset in seconds */
+
+static void secs_to_tm (unsigned long t, struct tm *tm)
+{
+	unsigned long days, rem;
+	unsigned int y, mon;
+	days = t/SECS_PER_DAY;
+	rem = t - (days*SECS_PER_DAY);
+	tm->tm_hour = rem / SECS_PER_HOUR;
+	rem -= tm->tm_hour*SECS_PER_HOUR;
+	tm->tm_min = rem / SECS_PER_MIN;
+	rem -= tm->tm_min*SECS_PER_MIN;
+	tm->tm_sec = rem;
+	tm->tm_wday = (days + START_WDAY) % 7;
+	y = BASE_YEAR;
+	while (days >= 365) {
+		if ((y % 4) == 0) {
+			if (days == 365)
+				break;
+			/* leap year */
+			days--;
+		}
+		days -= 365;
+		y++;
+	}
+	tm->tm_year = y - 1900;
+	tm->tm_yday = days;
+
+	/* Set correct # of days for feburary */
+	month_days[1] = ((y % 4) == 0) ? 29 : 28;
+
+	for (mon = 0; mon < 12; mon++) {
+		if (days < month_days[mon]) {
+			tm->tm_mon = mon;
+			break;
+		}
+		days -= month_days[mon];
+	}
+	if (mon == 12)  {
+		/* PANIC */
+		printf ("secs_to_tm:remaining days=%d\n", days);
+	}
+
+	tm->tm_mday = days + 1;
+	tm->tm_isdst = 0;
+	/* tm->tm_gmtoff = 0; */
+}
+
+void settimezone (int hours, int mins)
+{
+	tzoffset = hours*SECS_PER_HOUR + mins*SECS_PER_MIN;
+}
+
+struct tm *
+localtime ( const time_t *timep)
+{
+	static struct tm tm;
+	unsigned long t;
+
+	t = *timep + tzoffset;
+	secs_to_tm (t, &tm);
+	return &tm;
+}
+
+struct tm *
+gmtime (const time_t *timep)
+{
+	static struct tm tm;
+	unsigned long t;
+
+	t = *timep;
+	secs_to_tm (t, &tm);
+	return &tm;
+}
+
+time_t 
+time (time_t *tp)
+{
+	long int t;
+
+	t = (long int) (cticks / TPS);
+	if (tp)
+		*tp = t;
+	return t;
+}
+#endif /* INCLUDE_LOCAL_TIME */
+
+time_t convLocalTimeToString(char *timeBuffer)
+{
+   time_t dateTime;
+   struct tm *tmDateTime;
+
+   time(&dateTime);
+   tmDateTime = localtime((const time_t *)&dateTime);
+   sprintf(timeBuffer, "%02d:%02d:%02d", tmDateTime->tm_hour, 
+	  tmDateTime->tm_min, tmDateTime->tm_sec); 
+
+   return(dateTime);
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memdev.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memdev.c
new file mode 100644
index 0000000..8ffa160
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memdev.c
@@ -0,0 +1,396 @@
+/*
+ * FILENAME: memdev.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Memory device for VFS on diskless target systems. 
+ * Currently only supports ftp read of memory image, and read/ write 
+ * to "null" device. 
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: init_memdev(), md_fopen(), md_fclose(), md_fread(), 
+ * ROUTINES: md_fwrite(), md_fseek(), md_ftell(), md_fgetc(), md_unlink(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef MEMDEV_SIZE   /* whole file can be ifdeffed */
+
+#ifndef VFS_FILES /* These devices require VFS */
+#error MEMDEV devices require VFS system
+#endif
+#ifndef HT_EXTDEV /* ...also VFS external devices feature... */
+#error MEMDEV devices require VFS external devices
+#endif
+
+#include "vfsfiles.h"
+
+/* The memory device IO routines */
+VFILE* md_fopen(char * name, char * mode);
+void   md_fclose(VFILE * vfd);
+int    md_fread(char * buf, unsigned size, unsigned items, VFILE * vfd);
+int    md_fwrite(char * buf, unsigned size, unsigned items, VFILE * vfd);
+int    md_fseek(VFILE * vfd, long offset, int mode);
+long   md_ftell(VFILE * vfd);
+int    md_fgetc(VFILE * vfd);
+int    md_unlink(char*);
+
+/* The memory device VFS call structure. This is registered with the 
+ * VFS system at init time. Thereafter calls to the memory device 
+ * file 
+ */
+
+struct vfroutines mdio  =
+{
+   NULL,       /* list link */
+   md_fopen, 
+   md_fclose, 
+   md_fread, 
+   md_fwrite, 
+   md_fseek,
+   md_ftell, 
+   md_fgetc, 
+   md_unlink, 
+};
+
+
+
+#ifndef MEMDEV_BASE
+#error memdev needs a base address defined in ipport.h
+/* examples:
+...Ace360:
+#define  MEMDEV_BASE    0x400000
+#define  MEMDEV_SIZE    0x200000
+#else
+...PowerPC MBX board:
+#define  MEMDEV_BASE    0x000000
+#define  MEMDEV_SIZE    0x200000
+*/
+#endif   /* not MEMDEV_BASE */
+
+
+struct vfs_file   mdlist[] = 
+{
+   {  NULL,          /* list link */
+      "mem2M",       /* name of file */
+      VF_NODATA,     /* flags (compression, etc) */
+      NULL,          /* name of data array */
+      MEMDEV_SIZE,   /* length of original file data */
+      MEMDEV_SIZE,   /* length of compressed file data */
+      0,             /* block size */
+#ifdef WEBPORT
+      NULL,          /* SSI data routine */
+      NULL,          /* CGI routine */
+#ifdef SERVER_PUSH
+      NULL,          /* push callback */
+#endif
+#endif
+      &mdio,
+   },
+   {  &mdlist[0],    /* list link */
+      "mem1M",       /* name of file */
+      VF_NODATA,     /* flags (compression, etc) */
+      NULL,          /* name of data array */
+      MEMDEV_SIZE/2,   /* length of original file data */
+      MEMDEV_SIZE/2,   /* length of compressed file data */
+      0,             /* block size */
+#ifdef WEBPORT
+      NULL,          /* SSI data routine */
+      NULL,          /* CGI routine */
+#ifdef SERVER_PUSH
+      NULL,          /* push callback */
+#endif
+#endif
+      &mdio,
+   },
+   {  &mdlist[1],    /* list link */
+      "mem512K",     /* name of file */
+      VF_NODATA,     /* flags (compression, etc) */
+      NULL,          /* name of data array */
+      MEMDEV_SIZE/4,   /* length of original file data */
+      MEMDEV_SIZE/4,   /* length of compressed file data */
+      0,             /* block size */
+#ifdef WEBPORT
+      NULL,          /* SSI data routine */
+      NULL,          /* CGI routine */
+#ifdef SERVER_PUSH
+      NULL,          /* push callback */
+#endif
+#endif
+      &mdio,
+   },
+   {  &mdlist[2],    /* list link */
+      "null",        /* name of file */
+      VF_WRITE|VF_NODATA,      /* flags (compression, etc) */
+      NULL,          /* name of data array */
+      MEMDEV_SIZE,   /* length of original file data */
+      MEMDEV_SIZE,   /* length of compressed file data */
+      0,             /* block size */
+#ifdef WEBPORT
+      NULL,          /* SSI data routine */
+      NULL,          /* CGI routine */
+#ifdef SERVER_PUSH
+      NULL,          /* push callback */
+#endif
+#endif
+      &mdio,
+   },
+};
+
+int mdlist_size = sizeof(mdlist)/sizeof(struct vfs_file);
+
+
+/* FUNCTION: init_memdev()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+int
+init_memdev(void)
+{
+   /* add our IO pointer to master list */
+   mdio.next = vfsystems;
+   vfsystems = &mdio;
+
+   /* add the memory device files to vfs list */
+   mdlist[0].next = vfsfiles;
+   vfsfiles = &mdlist[3];
+
+   return 0;
+}
+
+
+/* FUNCTION: md_fopen()
+ * 
+ * PARAM1: char * name
+ * PARAM2: char * mode
+ *
+ * RETURNS: 
+ */
+
+VFILE* 
+md_fopen(char * name, char * mode)
+{
+   USE_ARG(mode);
+   USE_ARG(name);
+   return NULL;
+}
+
+
+
+/* FUNCTION: md_fclose()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+void   
+md_fclose(VFILE * vfd)
+{
+   USE_ARG(vfd);
+}
+
+
+
+/* FUNCTION: md_fread()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned size
+ * PARAM3: unsigned items
+ * PARAM4: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int    
+md_fread(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+   u_long   bcount;     /* number of bytes put in caller's buffer */
+   u_long   location;   /* current offset into file */
+   unsigned long file_size = MEMDEV_SIZE;
+   if(vfd && vfd->file)
+   {
+      file_size = vfd->file->real_size; 
+/*      printf("md_fread(): name = %s, file_size = %lu\n", vfd->file->name, file_size);*/
+   }
+/*
+   else
+   {
+      printf("md_fread(): No name: file_size = %lu\n", vfd->file->name, file_size);
+   }*/
+#ifdef SEG16_16   /* 16-bit x86 must include segment. */
+   if(vfd->cmploc == (u_char*)0xFFFFFFFF)   /* at EOF */
+      return 0;
+   location = (u_long)(((char huge *)vfd->cmploc) - ((char huge *)vfd->file->data));
+#else
+   location = (u_long)(vfd->cmploc - vfd->file->data);
+#endif   /* SEG16_16 */
+
+   bcount = (items * (u_long)size);     /* number of bytes to transfer */
+
+   /* if near end of memory, trim read count accordingly */
+   if ((location + bcount) > file_size)
+      bcount = ((u_long)file_size - location);
+
+   /* trap bogus size items and end-of-x86 memory conditions */
+   if((location >= file_size) ||
+      (bcount  & 0xFFFF0000) ||
+      (bcount == 0))
+   {
+      return 0;
+   }
+
+
+   /* Use VF_NODATA if memory devices have a size, but no
+      data. This can be used to measure file read speed
+      without introducing an undefined data copy. */
+   /* VF_NODATA is defined in ../h/vfsfiles.h */
+   
+   if (!(vfd->file->flags & VF_NODATA))
+   {
+      if (vfd->file->name[0] == 'm')   /* memory device */
+         MEMCPY(buf, vfd->cmploc + MEMDEV_BASE, (unsigned)bcount);
+   }
+
+
+   /* else for null device or files without data,
+      use whatever garbage is in the buffer */
+
+   /* before returning, adjust file position ptr for next read */
+#ifdef SEG16_16   /* 16-bit x86 must update seg too. */
+   {
+      char huge * cp;
+      cp = (char huge *)vfd->cmploc;
+      cp += bcount;  /* adjust location */
+      if(cp > (char huge*)vfd->cmploc)    /* make sure memory didn't wrap */
+         vfd->cmploc = (u_char *)cp;
+      else     /* read wrapped memory, set pointer to EOF value */
+         vfd->cmploc = (u_char*)(0xFFFFFFFF);  /* EOF */
+   }
+#else
+   vfd->cmploc += bcount;  /* adjust location */
+#endif
+   
+   return ((int)bcount/size);
+}
+
+
+
+/* FUNCTION: md_fwrite()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned size
+ * PARAM3: unsigned items
+ * PARAM4: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int    
+md_fwrite(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+   if (vfd->file->name[0] == 'm')   /* memory device */
+      return 0;   /* not writable device */
+
+   vfd->cmploc += (items * size);   /* adjust location */
+
+   USE_ARG(buf);     /* supress compiler warnings */
+
+   return (items);
+}
+
+
+
+/* FUNCTION: md_fseek()
+ * 
+ * PARAM1: VFILE * vfd
+ * PARAM2: long offset
+ * PARAM3: int mode
+ *
+ * RETURNS: 
+ */
+
+int
+md_fseek(VFILE * vfd, long offset, int mode)
+{
+   USE_ARG(vfd);     /* supress compiler warnings */
+   USE_ARG(offset);
+   USE_ARG(mode);
+   return 0;
+}
+
+
+
+/* FUNCTION: md_ftell()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+long   
+md_ftell(VFILE * vfd)
+{
+   USE_ARG(vfd);     /* supress compiler warnings */
+   return MEMDEV_SIZE;
+}
+
+
+
+/* FUNCTION: md_fgetc()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int    
+md_fgetc(VFILE * vfd)
+{
+   unsigned location;   /* current offset infile */
+   int   retval   =  0;
+
+   location = vfd->cmploc - vfd->file->data;
+   if (location >= vfd->file->real_size)     /* at end of file? */
+      return EOF;
+
+   if (!(vfd->file->flags & VF_NODATA))
+   {
+      if (vfd->file->name[0] == 'm')   /* memory device */
+         retval = (int)(*vfd->cmploc) & 0xFF ;
+   }
+
+   /* else for null device or files without data, 
+      use whatever is in retval */
+
+   vfd->cmploc++;    /* adjust location */
+   return retval;
+}
+
+
+
+/* FUNCTION: md_unlink()
+ * 
+ * PARAM1: char * filename
+ *
+ * RETURNS: 
+ */
+
+int    
+md_unlink(char * filename)
+{
+   USE_ARG(filename);     /* supress compiler warnings */
+   return 0;
+}
+
+#endif   /* MEMDEV_SIZE - whole file can be ifdeffed out */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memio.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memio.c
new file mode 100644
index 0000000..f66e325
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memio.c
@@ -0,0 +1,397 @@
+/*
+ * FILENAME: memio.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * memio.c calloc() & free() workalikes (calloc1() and mem_free()) 
+ * designed for embedded systems. 8/21/98 - first use, on AMD Net186. 
+ *
+ * MODULE: MPC860
+ *
+ * ROUTINES: sizeof(), mheap_init(), calloc1(), mem_free(), mh_stats(),
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "in_utils.h"
+#include "memwrap.h"
+
+
+extern unsigned memtrapsize;     /* alloc size to dtrap on */
+
+struct mem_block
+{
+#ifdef NPDEBUG
+   int         pattern;       /* pattern for testing overwrites */
+#endif   /* NPDEBUG */
+   struct mem_block *   next; /* pointer to next block */
+   unsigned    size;          /* size of block (excluding this header) */
+};
+
+/* define a pattern for putting in every mem block - this is used to 
+ * check for overwrites. This declaration assumes ALIGN_TYPE is the 
+ * same as 
+ */
+
+#if (ALIGN_TYPE == 4)
+#define  MEM_PATTERN    0x6D656D70  /* ascii for MEMP */
+#elif (ALIGN_TYPE == 2)
+#define  MEM_PATTERN    0x6D65      /* ascii for ME */
+#else
+#define  MEM_PATTERN    0x6D        /* ascii M */
+#endif
+
+#define MEMBLOCKSIZE ((sizeof(struct mem_block) & (ALIGN_TYPE - 1)) ? \
+   ((sizeof(struct mem_block) + ALIGN_TYPE) & ~(ALIGN_TYPE - 1)) : \
+   (sizeof(struct mem_block)))
+
+struct mem_block *   mh_free;
+struct mem_block *   mheap_base;
+
+long     mh_startfree;  /* heap size (in bytes) at init time */
+long     mh_totfree;    /* current free heap size */
+long     mh_minfree;    /* minimum free heap size seen */
+long     mh_failed;     /* number of times alloc failed */
+
+
+
+/* FUNCTION: mheap_init()
+ *
+ * Called at system init time to set up heap for use. MUST be called
+ * before any calls to calloc1(). Takes a single contiguous memory space
+ * and sets it up to be used by calloc1() anbd mem_free().
+ *
+ * PARAM1: char * base - address for start of heap area in memory
+ * PARAM2: long size  - size of heap area at address.
+ *
+ * RETURNS: void
+ */
+
+
+void
+mheap_init(char * base, long size)
+{
+   /* make sure the heap is aligned */
+   if ((long)base & (ALIGN_TYPE-1))
+   {
+      base = (char*)(((long)base + (ALIGN_TYPE-1)) & ~(ALIGN_TYPE-1));
+      size -= (ALIGN_TYPE-1);
+   }
+
+   mheap_base = (struct mem_block *)base;
+   mh_free = (struct mem_block *)base;
+
+   /* trim heap to multiple of ALIGN_TYPE */
+   size &= ~(ALIGN_TYPE-1);
+
+   /* start with no free space (we will add to this) */
+   mh_totfree = 0;
+
+#ifdef SEG16_16
+   if (size > 0x0000FFF0)  /* segment limits force multiple blocks */
+   {
+      unsigned seg, offset;
+      struct mem_block *   tmp;
+
+      tmp = mh_free;
+      seg = _FP_SEG(mh_free);
+      offset = _FP_OFF(mh_free);
+      while (size >= 0)
+      {
+         tmp->size = ((size>0xFFF0)?0xFFF0:(unsigned)size) - MEMBLOCKSIZE;
+         mh_totfree += tmp->size;
+         size -= 0xFFF0;
+         seg += 0x0FFF;
+#ifdef NPDEBUG
+         tmp->pattern = MEM_PATTERN;    /* set pattern for testing overwrites */
+#endif   /* NPDEBUG */
+         tmp->next = _MK_FP(seg, offset);
+         if (size >= 0) /* need more entrys? */
+            tmp = tmp->next;  /* prepare for next loop */
+         else
+            tmp->next = NULL; /* terminate list */
+      } 
+   }
+   else  /* make one big free block */
+#endif   /* SEG16_16 */
+   {
+      mh_free->size = (unsigned)size - MEMBLOCKSIZE;
+      mh_totfree += mh_free->size;
+      mh_free->next = NULL;
+#ifdef NPDEBUG
+      mh_free->pattern = MEM_PATTERN;     /* set pattern for testing overwrites */
+#endif   /* NPDEBUG */
+   }
+
+   /* set starting and minimum free space from the just-initialized total */
+   mh_startfree = mh_minfree = mh_totfree;
+}
+
+
+
+/* FUNCTION: calloc1()
+ *
+ * Similar to standard calloc(), except it only takes 1 size arg.
+ *
+ * PARAM1: unsigned size
+ *
+ * RETURNS: pointer to memif OK, else NULL
+ */
+
+char *   
+calloc1(unsigned size)
+{
+   unsigned lostsize;      /* size of data block plus struct */
+   struct mem_block *   bp;
+   struct mem_block *   newb;
+   struct mem_block *   lastb;
+
+#if (ALIGN_TYPE > 1)
+   /* increase requested size enough to ensure future alignment */
+   if ((long)size & (ALIGN_TYPE-1))
+   {
+      size = (size + ALIGN_TYPE) & ~(ALIGN_TYPE-1);
+   }
+#endif
+
+   lostsize = size + MEMBLOCKSIZE;  /* size we will take from heap */
+
+   ENTER_CRIT_SECTION(mh_free);
+   bp = mh_free;                    /* init vars for list search */
+   lastb = NULL;
+   while (bp)
+   {
+#ifdef NPDEBUG
+      if (bp->pattern != MEM_PATTERN)  /* test for corruption */
+      {
+         dtrap();
+         EXIT_CRIT_SECTION(mh_free);
+         return NULL;   /* probably should be panic */
+      }
+#endif   /* NPDEBUG */
+      if (bp->size >= size)   /* take first-fit free block */
+      {
+         /* Decide if the block is big enough to be worth dividing */
+         if (bp->size > (size + (MEMBLOCKSIZE * 2)))
+         {
+            /* Divide block and return front part to caller. First
+             * make a new block after the portion we will return
+             */
+            newb = (struct mem_block *)((char*)(bp) + lostsize);
+            newb->size = bp->size - lostsize;
+            newb->next = bp->next;
+#ifdef NPDEBUG
+            newb->pattern = MEM_PATTERN;   /* set test pattern */
+#endif   /* NPDEBUG */
+
+            /* modify bp to reflect smaller size we will return */
+            bp->next = newb;
+            bp->size = size;
+         }
+         else  /* not worth fragmenting block, return whole thing */
+         {
+            lostsize = bp->size + MEMBLOCKSIZE;       /* adjust lostsize */
+         }
+         if (lastb)   /* unlink block from queue */
+            lastb->next = bp->next;
+         else
+            mh_free = bp->next;
+
+         /* keep statistics */
+         mh_totfree -= lostsize;
+         if (mh_totfree < mh_minfree)
+            mh_minfree = mh_totfree;
+         bp->next = mheap_base;     /* tag next ptr with illegal value */
+         EXIT_CRIT_SECTION(mh_free);
+         return((char*)(bp) + MEMBLOCKSIZE);
+      }
+      lastb = bp;
+      bp = bp->next;
+   }
+   EXIT_CRIT_SECTION(mh_free);
+   mh_failed++;   /* count out of memory conditions */
+   return NULL;   /* failure return - no memory */
+}
+
+
+/* FUNCTION: mem_free()
+ * 
+ * Find block which contains buf and insert it in free 
+ * list. Maintains list in order, low to high memory. 
+ *
+ * PARAM1: char HUGE * buf - buffer to add to free list.
+ *
+ * RETURNS: void
+ */
+
+void
+mem_free(char HUGE * buf)
+{
+   struct mem_block  HUGE *   freep;
+   struct mem_block  HUGE *   tmp;
+   struct mem_block  HUGE *   last;
+   int   merged   =  0; /* indicates freep not merged into free list */
+
+   /* find pointer to prepended mem_block struct */
+   freep = (struct mem_block*)(buf - MEMBLOCKSIZE);
+   if (freep->next != mheap_base)      /* sanity check next ptr for tag */
+      panic("mem_free");
+
+   mh_totfree += ((unsigned long)freep->size + MEMBLOCKSIZE);
+
+   last = NULL;
+   for (tmp = mh_free; tmp; tmp = tmp->next)
+   {
+#ifdef NPDEBUG
+      if (tmp->pattern != MEM_PATTERN) /* test for corruption */
+      {
+         dtrap();    /* memory is corrupt, tell programmer! */
+         return;     /* probably should be panic */
+      }
+#endif   /* NPDEBUG */
+      if (freep < tmp)  /* found slot to insert freep */
+      {
+         /* see if we can merge with next block */
+         if (((char*)freep + freep->size + MEMBLOCKSIZE) == (char*)tmp)
+         {
+            freep->next = tmp->next;
+            freep->size += (tmp->size + MEMBLOCKSIZE);
+            if (last)
+               last->next = freep;
+            else
+               mh_free = freep;
+            merged++;
+         }
+#ifdef MEMIO_DEBUG
+         /* this and the test below check for conditions where the end of a block
+          * being freed is just a few bytes away from an adjacent block. This
+          * usually means the block size of off by the size of the mgt header.
+          * These tests chould be enabled and run for a while after any port of
+          * or surgery to this file.
+          */
+         else
+         if (((char HUGE *)freep + freep->size + MEMBLOCKSIZE) > (char HUGE *)(tmp - 3))
+         {
+            dprintf("memfree: this-end: %p, next: %p\n",
+               ((char*)freep + freep->size + MEMBLOCKSIZE), tmp );
+            dtrap();
+         }
+#endif
+         /* ...and see if we can merge with previous block */
+         if (last && (((char*)last + last->size + MEMBLOCKSIZE) == (char*)freep))
+         {
+            last->size += (freep->size + MEMBLOCKSIZE);
+            if (merged) /* if already merged, preserve next ptr */
+            {
+               last->next = freep->next;
+            }
+            merged++;
+         }
+#ifdef MEMIO_DEBUG
+         else
+         if (last && (((char HUGE *)last + last->size + MEMBLOCKSIZE) > (char HUGE *)(freep-3)))
+         {
+            dprintf("memfree: last-end: %p, this: %p\n",
+               ((char*)last + last->size + MEMBLOCKSIZE), freep );
+
+            dtrap();
+         }
+#endif
+            
+         /* if didn't merge with either adjacent block, insert into list */
+         if (!merged)   
+         {
+            if (last)
+            {
+               freep->next = last->next;
+               last->next = freep;
+            }
+            else     /* no last, put at head of list */
+            {
+               freep->next = mh_free;
+               mh_free = freep;
+            }
+            mh_totfree -= MEMBLOCKSIZE;   /* we didn't get a header back */
+         }
+         return;
+      }
+      last = tmp;       /* set "last" pointer for next loop */
+   }
+   /* got to end of list without finding slot for freep; add to end */
+   if (last)
+   {
+      /* See if we can merge it with last block */
+      if (((char*)last + last->size + MEMBLOCKSIZE) == (char*)freep)
+      {
+         last->size += (freep->size + MEMBLOCKSIZE);
+      }
+      else
+      {
+         freep->next = last->next;
+         last->next = freep;
+      }
+   }
+   else     /* there was no free list */
+   {
+      mh_free = freep;
+      freep->next = NULL;
+   }
+}
+
+
+#ifdef HEAP_STATS
+
+/* FUNCTION: mh_stats()
+ *
+ * The console routine to printf the heap stats.
+ *
+ * PARAM1: void * pio - output device (NULL for console)
+ *
+ * RETURNS: 0
+ */
+
+int
+mh_stats(void * pio)
+{
+   int   i  =  0;
+   unsigned long freeheap = 0;
+   struct mem_block *   tmp;
+
+   ns_printf(pio, "free list:\n");
+   for (tmp = mh_free; tmp; tmp = tmp->next)
+   {
+      freeheap += tmp->size;
+      ns_printf(pio, "%d: at %p, 0x%x bytes\n", i, tmp, tmp->size);
+      if(tmp->next == mheap_base)   /* was tmp alloced during ns_printf? */
+      {
+         ns_printf(pio, "list collision, terminating dump\n");  
+         break;
+      }
+      i++;
+   }
+
+   ns_printf(pio, "heap; start: %lu,  min: %lu,  current: %lu;  actual: %lu ",
+      mh_startfree, mh_minfree, mh_totfree, freeheap);
+   ns_printf(pio, "alloc failed: %lu\n", mh_failed);
+
+#ifdef MEM_WRAPPERS
+   wrap_stats(pio);     /* list optional wrapper stats */
+#endif
+
+   return 0;
+}
+
+#else
+/* if HEAP_STATS is not used, provide a dummy function */
+
+int
+mh_stats(void * pio)
+{
+   ns_printf(pio, "no heap stats on this build\n");
+   return 0;
+}
+
+#endif   /* HEAP_STATS */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memwrap.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memwrap.c
new file mode 100644
index 0000000..5befae2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/memwrap.c
@@ -0,0 +1,222 @@
+/* memwrap.c
+
+   Wrapper routines for heap managment routines. These routines bracket
+ the comventional heap functions like alloc and free, and collect
+ diagnostic information. Markers to detect buffer overwrites are installed
+ before and after the allocated blocks, and checked on frees. A table
+ is also kept to track how many blocks of each size are allocated and
+ freed. This information can be used to spot memory leaks and optimize
+ heap usage by the applications.
+
+
+*/
+
+#include "ipport.h"
+#include "in_utils.h"
+#include "memwrap.h"    /* include this AFTER ALIGN_TYPE */
+
+
+#ifdef MEM_WRAPPERS     /* whole file can be ifdeffed */
+
+extern int memtrapsize;     /* alloc size to dtrap on */
+
+struct memman
+{
+#if (ALIGN_TYPE > 1)
+   char  status[ALIGN_TYPE];  /* Marker flag, free flag */
+#else
+   char  status[2];           /* need at least two bytes */
+#endif   /* ALIGN_TYPE */
+   unsigned length;           /* size of alloced block */
+   char * data;               /* pointer to alloced data */
+};
+
+
+/* memory call counters */
+struct WrapMemStats
+{
+   unsigned long brallocs;    /* alloc call counter */
+   unsigned long brfrees;     /* free call counter */
+   unsigned long brallocb;    /* alloced byte counter */
+   unsigned long brfreeb;     /* freed byte counter */
+   unsigned long brfailed;    /* alloc routine failures */
+   unsigned long brmaxmem;    /* max. memory alloced at one time */
+   unsigned brmaxsize;        /* largest single alloc */
+   char * br_hiaddr;          /* highest address alloced */
+   char * br_loaddr;          /* lowest address alloced */
+} brmem;
+
+#ifndef MAXHIT
+#define MAXHIT 30
+#endif   /* MAXHIT */
+
+/* struct to track how many of each block size we alloc */
+struct memhit
+{
+   unsigned size;             /* zero until entry is used */
+   unsigned long blocks;      /* total alloc calls for this size */
+   unsigned long curr;        /* current bytes alloced for this size */
+} hitct[MAXHIT];
+
+int
+wrap_stats(void * pio)
+{
+   int   i;                   /* hitct index */
+   unsigned long cblocks;     /* current blocks outstanding */
+   char  outbuf[50];
+
+   ns_printf(pio, "wrappers: allocs: %lu,  frees: %lu,  allocbytes: %lu   freebytes: %lu\n",
+      brmem.brallocs, brmem.brfrees, brmem.brallocb, brmem.brfreeb );
+
+   ns_printf(pio, "alloced: current bytes: %lu  max bytes: %lu\n",
+      brmem.brallocb - brmem.brfreeb, brmem.brmaxmem );
+
+   ns_printf(pio, "biggest block: %u,  allocs failed: %lu\n",
+      brmem.brmaxsize, brmem.brfailed );
+
+   ns_printf(pio, "Block sizes, in size[alloc - free = cur] format:");
+   for(i = 0; i < MAXHIT; i++)
+   {
+      if(hitct[i].size == 0) break;
+      if(i%3 == 0)
+         ns_printf(pio, "\n");
+
+      cblocks = hitct[i].curr/hitct[i].size; /* current blocks of this size */
+      sprintf(outbuf, "%5u[%lu-%lu=%lu]",
+         hitct[i].size,
+         hitct[i].blocks,              /* allocated blocks of this size */
+         hitct[i].blocks - cblocks,    /* - freed blocks of this size */
+         cblocks);                     /* = current blocks of this size */
+      if(strlen(outbuf) > 50) panic("wrap");
+      ns_printf(pio, "%-26s", outbuf);
+   }
+   ns_printf(pio, "\n");
+   return 0;
+}
+
+
+char *
+wrap_alloc(unsigned size, char *(*alloc_rtn)(unsigned))
+{
+   int      i;
+   int      free;
+   int      wrapsize;      /* size to alloc including wrap info */
+   char *   cp;
+   struct memman * manp;
+
+   if(size == memtrapsize)
+   {
+      dtrap();
+   }
+
+   /* allocate block big enough for caller plus warpping struct */
+   wrapsize = size + sizeof(struct memman) + ALIGN_TYPE;
+   cp = (*alloc_rtn)(wrapsize);
+
+   if(!cp)  /* alloc couldn't get memory */
+   {
+      brmem.brfailed++;
+      return NULL;
+   }
+
+   manp = (struct memman *)cp;      /* set mgt structure */
+   cp += sizeof(struct memman);     /* set pointer to return */
+
+   /* check for newest hi/low address */
+   if(cp > brmem.br_hiaddr)
+      brmem.br_hiaddr = cp;
+   if((cp < brmem.br_loaddr) || (brmem.br_loaddr == NULL))
+      brmem.br_loaddr = cp;
+
+   /* fill in wrapping structure for later wrap_free() checking */
+   manp->status[0] = 'M';     /* add memory marker */
+   manp->status[1] = 'M';     /* mark as NOT free */
+   manp->data = cp;
+   manp->length = size;
+   *(cp + size) = 'M';     /* end memory marker */
+
+   /* keep track of hits on each block size */
+   free = -1;  /* use -1 to indicate no free hitct[] entry */
+   for(i = 0; i < MAXHIT; i++)
+   {
+      if(hitct[i].size == size)  /* found entry for this size */
+      {
+         hitct[i].curr += size;
+         hitct[i].blocks++;
+         break;
+      }
+      if(hitct[i].size == 0)  /* size not in array */
+      {
+         free = i;   /* remember first free slot */
+         break;      /* make new entry */
+      }
+   }
+   if(free != -1)  /* see if we should start an entry for this size */
+   {
+      hitct[i].curr = hitct[i].size = size;
+      hitct[i].blocks = 1;
+   }
+
+   brmem.brallocs++;
+   brmem.brallocb += size;
+   if(brmem.brmaxsize < size) /* new record for a single alloc? */
+      brmem.brmaxsize = size;
+   if(brmem.brmaxmem < (brmem.brallocb - brmem.brfreeb)) /* new record for allocation? */
+      brmem.brmaxmem = brmem.brallocb - brmem.brfreeb;
+
+   return (cp);
+}
+
+void
+wrap_free(char * ptr, void(*free_rtn)(char *))
+{
+   int      i;
+   char *   cp;
+   struct memman * manp;
+
+   /* make sure the pointer is within the previously allocated range */
+   if((ptr > brmem.br_hiaddr) ||
+      (ptr < brmem.br_loaddr))
+   {
+      dtrap(); /* maybe this should be a panic.... */
+      return;
+   }
+
+   /* back up from pointer to get memory manager struct */
+   manp = (struct memman *)ptr;
+   manp--;
+   cp = manp->data;
+   if(manp->status[0] != 'M')    /* Make sure marker is present */
+   {
+      dtrap(); /* bad pointer or corrupt memory */
+      return;  /* don't confuse system free() */
+   }
+   if(manp->status[1] == 'F')    /* Double free ? */
+   {
+      dtrap(); /* bad pointer or corrupt memory */
+      return;  /* don't confuse system free() */
+   }
+   manp->status[1] = 'F';     /* mark as free */
+   if(*(cp + manp->length) != 'M')
+   {
+      dtrap();    /* should be panic */
+      return;
+   }
+   brmem.brfrees++;
+   brmem.brfreeb += manp->length;
+   for(i = 0; i < MAXHIT; i++)
+   {
+      if(hitct[i].size == manp->length)
+      {
+         hitct[i].curr -= manp->length;
+         break;
+      }
+   }
+
+   cp = (char*)manp;
+   
+   free_rtn(cp);   /* memory came through wrap_alloc(), free it */
+}
+
+#endif   /* MEM_WRAPPERS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menulib.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menulib.c
new file mode 100644
index 0000000..487c6a7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menulib.c
@@ -0,0 +1,430 @@
+/*
+ * FILENAME: menulib.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Misc utility routines for Interniche menuing system
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: setdebug(), set_upc(), snmp_stat(), iface_stats(), 
+ * ROUTINES: ifstats(), linkstats(), settrapsize(), if_configbyname()
+ * ROUTINES: if_netbytext
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software */
+
+
+#include "ipport.h"
+#include "in_utils.h"
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "ether.h"
+#include "arp.h"
+
+#include "menu.h"
+#include "nvparms.h"
+
+int ifstats(void * pio, struct net * ifp);
+char * print_uptime(unsigned long timetick);
+
+unsigned atoh(char *);
+
+#ifdef IP_V6
+#include "ip6.h"
+#endif
+
+/* FUNCTION: setdebug()
+ *
+ * setdebug() - toggle NDEBUG protocol stack debugging options
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+setdebug(void * pio)
+{
+#ifdef NPDEBUG
+     char *   cp;
+
+   /* get an optional parameter */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+
+   /* if no parameter was entered */
+   if (!*cp)
+   {
+      if (NDEBUG)
+      { NDEBUG &= UPCTRACE;
+         ns_printf(pio,"IP stack debug tracing off\n");
+      }
+      else
+      { NDEBUG |= INFOMSG|IPTRACE|PROTERR|TPTRACE;
+         ns_printf(pio,"IP stack debug tracing on\n");
+      }
+   }
+   else
+   {
+      /* '?' means display NDEBUG value, else set NDEBUG flag to parameter value */
+      if (*cp != '?')
+      {
+#ifdef IN_MENUS
+         NDEBUG = atoh(cp);
+#endif
+      }
+      ns_printf(pio,"NDEBUG is now 0x%x\n",NDEBUG);
+   }
+#else
+   ns_printf(pio,"not a DEBUG compile.\n");
+#endif
+   return 0;
+}
+
+
+
+/* FUNCTION: set_upc()
+ *
+ * toggle state of upcall variable
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+set_upc(void * pio)
+{
+   if (NDEBUG & UPCTRACE)
+      NDEBUG &= ~UPCTRACE;
+   else
+      NDEBUG |= UPCTRACE;
+
+   ns_printf(pio,"Upcall debugging %sabled\n", 
+    (NDEBUG&UPCTRACE)?"en":"dis");
+
+   return 0;
+}
+
+
+/* FUNCTION: if_configbyname(NET ifp)
+ *
+ * Configure the passed net interface from a set of NV parameters with
+ * same name. This allows the NV system to specify parameters for
+ * dynamic interfaces, and also frees the NV file from having to
+ * specifiy the nets in the order they come up.
+ *
+ *
+ * PARAM1: NET to configure - should have ifp->name set up.
+ *
+ * RETURNS: Returns 0 if OK, -1 if name not found
+ */
+
+#ifdef   INCLUDE_NVPARMS   /* only if using NV parms */
+int
+if_configbyname(NET ifp)
+{
+   int   i;
+
+   /* search the NV parameters "nets" array for for our name */
+   for(i = 0; i < MAXNETS; i++)
+   {
+      if(strncmp(inet_nvparms.ifs[i].name, ifp->name, IF_NAMELEN - 1) == 0)
+      {
+         /* found a matching name, set our IP congif from NV entry */
+         ifp->n_ipaddr = inet_nvparms.ifs[i].ipaddr;
+         ifp->snmask = inet_nvparms.ifs[i].subnet;
+         ifp->n_defgw = inet_nvparms.ifs[i].gateway;
+         return 0;
+      }
+   }
+   return -1;
+}
+#endif   /* INCLUDE_NVPARMS */
+
+/* FUNCTION: if_netbytext()
+ *
+ * get a net pointer based on a user text string. The string may be a ones
+ * based number index (eg "1", "2") or an iface name ("pp0"). Prints error
+ * message to passed output device if text does not map to an interface.
+ * 
+ *
+ * PARAM1: void * pio   - output stream for error reporting
+ * PARAM2: char * iftext - text of interface.
+ *
+ * RETURNS: pointer to iface if OK, else NULL.
+ */
+
+
+NET
+if_netbytext(void * pio, char * iftext)
+{
+   unsigned iface;
+   NET      ifp;
+
+   if((strlen(iftext) == 1) && (isdigit(*iftext)))
+   {
+      iface = (unsigned)(*iftext - '0') - 1;
+      if((iface >= ifNumber) ||
+         ((ifp = if_getbynum((int)iface)) == NULL))
+      {
+           ns_printf(pio,"interface number must be 1 to %d.\n", ifNumber);
+           return NULL;
+      }
+      else
+         return (ifp);
+   }
+   else     /* not a single digit, look up as name */
+   {
+      for(ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+      {
+         if(strcmp(iftext, ifp->name) == 0)
+            return ifp;
+      }
+      if(!ifp)
+           ns_printf(pio,"no interface named \"%s\".\n", iftext);
+   }
+   return NULL;
+}
+
+
+/* FUNCTION: iface_stats()
+ * 
+ * menu routine to get iface number and invoke stats
+ *
+ * PARAM1: void * pio - output stream
+ *
+ * RETURNS: 0
+ */
+
+int
+iface_stats(void * pio)
+{
+   char *   cp;
+   struct net * ifp;
+
+   ifp = (NET)(netlist.q_head);   /* default to first net */
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* get console arg */
+   if(cp && *cp)     /* arg is present on command line */
+   {
+      ifp = if_netbytext(pio, cp);
+      if(ifp == NULL)      /* error parsing iface name/number text? */
+         return -1;
+   }
+
+   ifstats(pio, ifp);
+   return 0;
+}
+
+
+/* FUNCTION: ifstats()
+ *
+ * per-iface portion of iface_stats()
+ *
+ * PARAM1: void * pio   - output stream
+ * PARAM2: int ifc      - interface to dump
+ *
+ * RETURNS: 0
+ */
+
+int
+ifstats(void * pio, struct net * ifp)
+{
+   ns_printf(pio, "Interface %s - %s \n", 
+      ifp->name, ifp->n_mib->ifDescr);
+#ifdef IP_V4
+   ns_printf(pio,"IPv4 address: %s, " , print_ipad(ifp->n_ipaddr));
+   ns_printf(pio,"subnet mask: %s, ", print_ipad(ifp->snmask));
+   ns_printf(pio,"gateway: %s\n"    , print_ipad(ifp->n_defgw));
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   if(ifp->n_flags & NF_IPV6)
+   {
+      int i;
+      char ip6buf[46];     /* tmp buffer for ipv6 address text */
+
+      for(i = 0; i < MAX_V6_ADDRS; i++)
+      {
+         if(ifp->v6addrs[i])
+         {
+            ns_printf(pio,"IPv6 %6s addr: %s", v6types[i], 
+               print_ip6(&(ifp->v6addrs[i]->addr), ip6buf));
+            ns_printf(pio," - %s\n", 
+               ip6addrstates[ifp->v6addrs[i]->flags & IA_STATEMASK]);
+         }
+      }
+   }
+   else
+      ns_printf(pio,"No IPv6 addresses\n");
+#endif   /* IP_V6 */
+   ns_printf(pio,"Status; Admin:%s Oper:%s for: %s\n", 
+      ifp->n_mib->ifAdminStatus==1?"up":"down",
+      ifp->n_mib->ifOperStatus==1?"up":"down",
+      print_uptime(sysuptime() - (ifp->n_mib->ifLastChange)));
+   ns_printf(pio,"rcvd: errors:%lu   dropped:%lu   station:%lu   bcast:%lu   bytes:%lu\n",
+      ifp->n_mib->ifInErrors, ifp->n_mib->ifInDiscards,
+      ifp->n_mib->ifInUcastPkts, ifp->n_mib->ifInNUcastPkts,
+      ifp->n_mib->ifInOctets);
+   ns_printf(pio,"sent: errors:%lu   dropped:%lu   station:%lu   bcast:%lu   bytes:%lu\n",
+      ifp->n_mib->ifOutErrors, ifp->n_mib->ifOutDiscards,
+      ifp->n_mib->ifOutUcastPkts, ifp->n_mib->ifOutNUcastPkts,
+      ifp->n_mib->ifOutOctets);
+   ns_printf(pio,"MAC address: ");
+   hexdump(pio,ifp->n_mib->ifPhysAddress, 6);
+   ns_printf(pio," \n");
+
+#ifdef IP_MULTICAST
+   /* Print any multicast addresses assign to this iface */
+   if(ifp->mc_list)
+   {
+      struct in_multi * imp;
+
+      ns_printf(pio, "   Multicast addresses: \n");
+      for (imp = ifp->mc_list; imp; imp = imp->inm_next)
+      {
+#ifdef IP_V6
+         {
+            char ip6buf[40];     /* tmp buffer for ipv6 address text */
+            ns_printf(pio, "   %s\n", print_ip6(&(imp->ip6addr), ip6buf));
+            continue;
+         }
+#endif   /* IP_V6 */
+         ns_printf(pio, "   %s\n",  print_ipad(imp->inm_addr) );
+      }
+   }
+#endif   /* IP_MULTICAST */
+
+
+   return 0;
+}
+
+
+
+
+
+/* FUNCTION: linkstats()
+ * 
+ * printf stats for link interface. default to iface 1
+ *
+ * PARAM1: void * pio   - output stream
+ *
+ * RETURNS: 0 if OK, else -1 if arg is bad.
+ */
+
+int
+linkstats(void * pio)
+{
+   int      iface =  1;
+   char *   cp;
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+
+   if (*cp)
+   {
+      iface = atoi(cp);
+      if (iface < 1 || iface > (int)ifNumber)
+      {
+         ns_printf(pio,"interface number must be 1 to %d.\n", ifNumber);
+         return -1;
+      }
+   }
+   iface--;
+
+   if (nets[iface]->n_stats)
+      nets[iface]->n_stats(pio,iface);  /* actually call the stats */
+   else
+      ns_printf(pio,"no stats routine for interface %d\n", iface+1);
+   return 0;
+}
+
+
+/* FUNCTION: settrapsize()
+ *
+ * settrapsize() - This sets a value which will cause the memory 
+ * managment monitoring code to trap to a debugger if a malloc is 
+ * attempted for this size. This is usefull when a memory leak is 
+ * occuring of memory buffers on an unusual size, as often happens 
+ * with networking code. It has nothing to do with SNMP traps. 
+ * Returns no meaningfull value; declared as int to make compiler 
+ * happy. 
+ *
+ * 
+ * PARAM1: void * pio   - output stream
+ *
+ * RETURNS: 0
+ */
+
+extern   int   memtrapsize;   /* in memman.c or user heap code */
+
+int
+settrapsize(void * pio) 
+{
+   char *   cp;
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+
+   memtrapsize = atoi(cp);
+   ns_printf(pio,"malloc trap size set to %d\n", memtrapsize);
+   return 0;
+}
+
+/* FUNCTION: send_grat_arp()
+ * 
+ * menu routine to get iface number and send gratuitouts ARP
+ *
+ * PARAM1: void * pio - output stream
+ *
+ * RETURNS: 0
+ */
+
+int grat_arp(NET net, int flag);
+
+int
+send_grat_arp(void * pio)
+{
+   char *   cp;
+   struct net * ifp;
+   int  flag;
+
+   ifp = (NET)(netlist.q_head);   /* default to first net */
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* get console arg */
+   if(cp && *cp)     /* arg is present on command line */
+   {
+      if (*cp == 'a')
+         flag = 0;
+      else
+      if (*cp == 'r')
+         flag = 1;
+      else
+      {
+          ns_printf(pio,"USAGE: sendarp (a|r) [net]\n");
+          return 0;         
+      }      
+   }
+
+   cp = nextarg(cp);    /* get console arg */
+   if(cp && *cp)     /* arg is present on command line */
+   {
+      ifp = if_netbytext(pio, cp);
+      if(ifp == NULL)      /* error parsing iface name/number text? */
+         return -1;
+   }
+   
+   grat_arp(ifp, flag);
+
+   USE_ARG(flag);   
+
+   return 0;
+}
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menus.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menus.c
new file mode 100644
index 0000000..eb7f452
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/menus.c
@@ -0,0 +1,445 @@
+/*
+ * FILENAME: menus.c
+ *
+ * Copyright  1993-2007 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: do_command(), stooges(), showmenu(), help(), 
+ * ROUTINES: kbdio(), stcmp(), stlen(), install_menu()
+ * ROUTINES: install_version()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1992 by NetPort Software */
+
+
+#include "ipport.h"
+#ifdef MQX
+#include <fio.h>
+#endif
+
+#ifdef IN_MENUS
+
+#include "menu.h"
+
+extern   int  nummenus;       /* items in menus[] */
+extern   char *prompt;
+
+/* the following two routines are DOS-isms menuing requires from the port */
+extern   int kbhit(void);     /* TRUE if console char (keyboard) is ready */
+extern   int getch(void);     /* get next console char */
+
+
+
+/* FUNCTION: do_command()
+ *
+ * do_command() - this is called when we have a complete command 
+ * string in cbuf[]. It looks up the command in the menus and 
+ * executes it. Prints error messages as appropriate. 
+ *
+ * 
+ * PARAM1: void * pio   - device for ns_printf() output
+ *
+ * RETURNS: Returns 0 if the command passed was found in menus
+ *  (or otherwise understood), returns -1 if not. 
+ */
+
+int
+do_command(void * pio)
+{
+   struct menu_op *mp;
+   struct menu_op *mp1   =  NULL;
+   char *inbuf = ((GEN_IO)pio)->inbuf;
+   int   i;
+   int   l;
+
+   mp1 = NULL;                /* clear menu command pointer */
+   if (inbuf[0] == '?')    /* is user after help? */
+   {
+      help(pio);
+      ns_printf(pio,"\n");
+      return 0;
+   }
+
+#ifdef INCLUDE_SHELL
+   if (inbuf[0] == '!') /* User want an OS shell command? */
+   {
+      system(&inbuf[1]);   /* call system */
+      return 0;
+   }
+#endif   /* INCLUDE_SHELL */
+
+   /* scan the various menus for the user command: */
+   for (i = 0; i < nummenus; i++)   /* menu loop */
+   {
+      mp = menus[i];    /* get pointer to next menu list */
+      if (!mp) break;
+         mp++;          /* bump past menu ID */
+      while (mp->opt)   /* scan this menu's options for cmd */
+      {      
+         l = stcmp(mp->opt, inbuf);
+         if (l == 0 || l > stlen(inbuf))  /* got a match */
+         {
+            if(stlen(inbuf) == (int)strlen(mp->opt))    /* was it an exact match? */
+            {
+               mp1 = mp;
+               goto menu_do_cmd;    /* quit searching and go do it */
+            }
+
+            if (mp1) /* we already had a partial match */
+            {
+               ns_printf(pio,"Ambiguous command: %s \n", inbuf);
+               return -1;
+            }
+            mp1 = mp;      /* remember the matching entry */
+         }
+         mp++;
+      }
+   }
+   if (!mp1)
+   {
+      ns_printf(pio,"Unknown command: %s\n", inbuf);
+      return -1;
+   }
+
+menu_do_cmd:
+   if ( mp1->func )  /* Has the function been specified ? */
+      (mp1->func)(pio); /* call the menu command's function */
+
+   return 0;   /* we found the command */
+}
+
+
+
+/* FUNCTION: stooges()
+ *
+ * Called when an unused menu routine hook is exececuted. This means
+ * a serious programming error occured.
+ *
+ * PARAM1: void * pio   - device for ns_printf() output
+ *
+ * RETURNS: 0
+ */
+
+int
+stooges(void * pio)
+{
+   return 0;
+}
+
+
+
+/* FUNCTION: showmenu()
+ *
+ * Loop through the passed menu struct, displaying the options
+ * and descriptions.
+ *
+ * PARAM1: void * pio   - device for ns_printf() output
+ * PARAM2: struct menu_op * menu
+ *
+ * RETURNS: void
+ */
+
+void
+showmenu(void * pio, struct menu_op * menu)     /* menu to display */   
+{
+   ns_printf(pio,"SNMP Station: %s commands:\n", menu->opt);   /* 1st item is menu ID */
+   menu++;
+   while (menu->opt)
+   {
+      ns_printf(pio,"   %-8s - %s\n", menu->opt, menu->desc);
+      menu++;
+   }
+}
+
+
+/* FUNCTION: help()
+ *
+ * help() - printf the commands and descriptions from the app's 
+ * menus. Returns no meaningfull value, declared an int to suppress 
+ * compiler warnings when assigned to menus. 
+ *
+ * 
+ * PARAM1: void * pio   - device for ns_printf() output
+ *
+ * RETURNS: 0
+ */
+
+int
+help(void * pio)
+{
+   char *   argp;
+   int   i,l;
+
+   /* help command line should still be in inbuf */
+   argp = nextarg(((GEN_IO)pio)->inbuf);     /* get first arg after "help" or '?' */
+
+   /* handle simple '?' or 'help' cases first */
+   if (!*argp)
+   {
+      showmenu(pio,menus[0]);
+      ns_printf(pio,"Also try 'help [");
+      for (i = 0; i < nummenus; i++)   /* menu loop */
+      {
+         if (!menus[i]) break;
+            if (i != 0) ns_printf(pio,"|");  /* separate IDs w/vertical bars */
+            ns_printf(pio,"%s", menus[i]->opt); /* print each menu ID */
+      }
+      ns_printf(pio,"]'\n");
+      return 0;
+   }
+   /* else - should be a parm after help */
+   for (i = 0; i < nummenus; i++)   /* menu loop */
+   {
+      if (!menus[i]) break;
+         l = stcmp(argp, menus[i]->opt);
+      if (l == 0 || l > stlen(argp))      /* found a menu matching parm */
+      {
+         showmenu(pio,menus[i]);
+         return 0;
+      }
+   }
+   ns_printf(pio,"unknown help parameter %s\n", argp);
+   return 0;
+}
+
+
+/* FUNCTION: kbdio()
+ *
+ * Called by the system whenever a console character is ready. Calls
+ * kbhit() to test, so it can be used for polling. If an enter ASCII
+ * (13 or 10) is received, it calls do_command() with the currently
+ * buffered input characters. 
+ *
+ * This does not block.
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+
+ 
+/* command line buffer. Directly referenced only by kbdio() */
+char     cbuf[CBUFLEN];     
+
+/* re-entry prevention flag for kbdio */
+static int in_docmd = 0;
+
+/* pointer to next available byte in cbuf */
+char *   nextcb   =  &cbuf[0];
+
+/* Generic IO structure that do_command() will be called with */
+struct GenericIO  std_io   =  {  cbuf, std_out, 0, std_in   }  ;
+
+void
+kbdio(void)
+{
+   int   key;
+#ifdef MQX
+   _mqx_uint avl;
+   _mqx_int rc;
+#endif
+
+   if(in_docmd)   /* don't poll while doing command */
+      return;
+
+#ifdef MQX
+   rc = ioctl (stdin, IO_IOCTL_CHAR_AVAIL, &avl);
+   if (!avl) return;
+   key = fgetc (stdin);  
+#else
+   if(!kbhit())   /* if no key waiting, just return */
+      return;
+   key = getch();        /* get keystroke */
+#endif
+
+   if(key == 13 || key == 10)
+   {
+      if(nextcb == cbuf)   /* no data in cbuf */
+      {
+#ifndef KBDIO_NO_ECHO      
+         putchar('\n');
+#endif
+         printf("%s", prompt);         
+         FLUSH_STDOUT;
+         return;
+      }
+
+      /* else there's data in cbuf */
+      *nextcb   =  0;    /* null terminate string */
+#ifndef KBDIO_NO_ECHO      
+      putchar('\n');
+#endif      
+      in_docmd++; /* set anti-polling flag while doing command */
+      do_command(&std_io); /* lookup and execute command */
+      nextcb   =  cbuf;
+      in_docmd--;
+      printf(prompt);
+      FLUSH_STDOUT;
+   }
+
+   if(key  >= ' ' && key < 127)  /* got printable char */
+   {
+      if(nextcb >= &cbuf[CBUFLEN-1])
+         return;  /* buffer full */
+      *nextcb++ = (char)key;
+#ifndef KBDIO_NO_ECHO      
+      putchar(key);
+#endif      
+      FLUSH_STDOUT;
+   }
+   else if(key == 8)    /* backspace */
+   {
+      if(nextcb == cbuf)
+         return;     /* don't backspace if no chars in buf */
+      *nextcb   =  0; /* clear last char from buffer */
+      nextcb--;
+#ifndef KBDIO_NO_ECHO      
+      putchar(8);
+      putchar(' ');
+      putchar(8);
+#endif      
+      FLUSH_STDOUT;
+   }
+   else if(key == 27)   /* escape */
+   {
+      while(nextcb > cbuf) /* reset buffer */
+      {
+         nextcb--;
+         putchar(8);
+         putchar(' ');
+         putchar(8);
+      }
+      cbuf[0]  =  27;   /* leave ESC in first byte */
+      cbuf[1]  =  0;    /* clean up string */
+      FLUSH_STDOUT;
+      /* next char will overwrite ESC */
+   }
+   else if(key == 3) /* ctrl-C */
+   {
+      /* should we quit() here? */
+   }
+   return;
+}
+
+
+
+/* FUNCTION: stcmp()
+ *
+ * stcmp() - special string compare routine. returns 0 if strings 
+ * match, else returns char where 1st mismatch occured. ie: 
+ * stcmp("help", "helper") returns a 5. stcmp("help", "nohelp") 
+ * returns a 1. Also: treats space as end of string. 
+ *
+ * 
+ * PARAM1: char * string1
+ * PARAM2: char * string2
+ *
+ * RETURNS: 0 if strings match, else returns char where 1st mismatch occured.
+ */
+
+int
+stcmp(char * s1, char * s2)
+{
+   int   ct =  1;    /* byte being checked */
+
+   while(*s1 && *s1 != ' ')  /* read to 1st space or end */
+   {
+      if(*s1++ != *s2++) return(ct);
+         ct++;
+   }
+   if(*s2) return(ct);  /* s2 was longer than s1 */
+      return(0);
+}
+
+
+/* FUNCTION: stlen()
+ *
+ * stlen() - return length of string passed. space char counts as end 
+ * of string. 
+ *
+ * 
+ * PARAM1: char * string
+ *
+ * RETURNS: return length of string passed
+ */
+
+int
+stlen(char * st1)
+{
+   int   retval   =  0;
+
+   while(*st1 && *st1 != ' ')   /* find first NULL or space */
+   {
+      st1++;
+      retval++;
+   }
+   return(retval);
+}
+
+
+/* FUNCTION: install_menu()
+ *
+ * Add new menu to master list. 
+ * 
+ * PARAM1: menu_op *          pointer to new menu struct
+ *
+ * RETURNS: int               0 if OK, -1 if no more slots 
+ */
+
+int
+install_menu(struct menu_op * newmenu)
+{
+   int   i;
+
+   for (i = 0; i < MAX_MENUS; i++)
+   {
+      if (menus[i] == newmenu)      /* duplicate */
+         return (0);
+
+      if (menus[i] == (struct menu_op *)NULL)
+      {
+         menus[i] =  newmenu;
+         return (0);          /* installed OK */
+      }         
+   }
+
+   dtrap();                   /* bad programming? */
+   return (-1);               /* no room in master list */
+}
+
+
+
+/* FUNCTION: install_version()
+ *
+ * register a module version string
+ *
+ * PARAM1: char *             version string
+ *
+ * RETURN: int                0 if successful, -1 if table is full
+ */
+int
+install_version(char *version)
+{
+   int i;
+
+   for (i = 0; i < MAX_MENUS; i++)
+   {
+      if (versions[i] == NULL)   /* empty slot */
+      {
+         versions[i] = version;
+         return 0;
+      }
+   }
+
+   /* table is full; notify caller */
+   dtrap();
+   return -1;
+}
+
+#endif   /* IN_MENUS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/msring.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/msring.c
new file mode 100644
index 0000000..158d02e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/msring.c
@@ -0,0 +1,131 @@
+/* FILENAME: msring.c
+ *
+ * Copyright 2002 InterNiche Technologies.  All rights reserved.
+ * 
+ * PORTABLE: YES
+ *
+ * MODULE: MISCLIB
+ *
+ * This file provides support for ring buffers of NicheLite M_SOCKs.
+ * These are useful with NicheLite TCP server applications; the server
+ * can use a ring buffer in its callback function to buffer newly-
+ * received connections until it can safely add them to its work queue
+ * from its normal thread context.
+ *
+ * The application is expected to provide two storage areas:
+ * a struct msring, and an array of M_SOCKs.  The array will be 
+ * used to buffer the new M_SOCKs, and the struct msring will be
+ * used to manage the buffer.
+ *
+ * The application should call msring_init() to initialize the ring,
+ * call msring_add() from its callback function to add the new M_SOCK
+ * to its buffer, then call msring_del() from its normal thread 
+ * context to test for the presence of a buffered M_SOCK and remove
+ * it from the buffer (returning it to the application).
+ *
+ * Note that the array of M_SOCKs should be sized to hold one more than
+ * the maximum number of expected M_SOCKs.  If the ring is full when
+ * the callback function calls msring_add(), the new M_SOCK will be
+ * dropped!
+ *
+ * Implementation details:
+ *
+ * msring.in is the index to where the next M_SOCK added should be stored.
+ * msring.out is the index from where the next M_SOCK deleted should be
+ * deleted.
+ * Hence, msring.in == msring.out is the "ring empty" state, and
+ * (msring.in + 1) % msring.buflen == msring.out is the "ring full"
+ * state.
+ *
+ */
+
+#include "ipport.h"
+#include "tcpapp.h"
+
+#ifdef MINI_TCP
+
+#include "msring.h"
+
+/* FUNCTION: msring_init()
+ *
+ * Initializes an M_SOCK ring to an empty state.
+ * 
+ * PARAM1: struct msring * ring; a pointer to the struct msring that
+ *                               is to be initialized
+ * PARAM2: M_SOCK * buf; a pointer to an array of M_SOCKs that is
+ *                       to be used to store the M_SOCKs in the ring
+ * PARAM3: unsigned bufsize; the size (in M_SOCKs) of buf
+ *
+ * RETURNS: void
+ */
+void
+msring_init(struct msring * ring,
+            M_SOCK * buf,
+            unsigned buflen)
+{
+   ring->in = ring->out = 0;
+   ring->buf = buf;
+   ring->buflen = buflen;
+}
+
+/* FUNCTION: msring_add()
+ *
+ * Adds an M_SOCK to an M_SOCK ring.
+ * 
+ * PARAM1: struct msring * ring; a pointer to the struct msring to which
+ *                               the M_SOCK is to be added
+ * PARAM2: M_SOCK so; the M_SOCK that is to be added to the ring
+ *
+ * RETURNS: void
+ */
+void
+msring_add(struct msring * ring,
+           M_SOCK so)
+{
+   if (((ring->in + 1) & ring->buflen) == ring->out)
+   {
+      /* the ring is full, and we are going to drop this socket */
+      dtrap();
+      return;
+   }
+
+   /* add the socket to the ring */
+   ring->buf[ring->in] = so;
+   if (ring->in + 1 < ring->buflen)
+      ring->in = ring->in + 1;
+   else
+      ring->in = 0;
+}
+
+/* FUNCTION: msring_del()
+ *
+ * Removes an M_SOCK from an M_SOCK ring, returning it to the caller.
+ * 
+ * PARAM1: struct msring * ring; a pointer to the struct msring to which
+ *                               the M_SOCK is to be added
+ * PARAM2: M_SOCK * so; a pointer to an M_SOCK where the removed M_SOCK
+ *                      can be returned to the caller
+ *
+ * RETURNS: an integer indicating the success or failure of the call.
+ *          0 indicates success, with an M_SOCK returned in so.
+ *          -1 indicates failure, typically that there are no more
+ *          M_SOCKs in the ring.
+ */
+int
+msring_del(struct msring * ring,
+           M_SOCK * so)
+{
+   /* if ring empty, return failure */
+   if (ring->in == ring->out)
+      return -1;
+   
+   /* get one socket from the ring and return success */
+   *so = ring->buf[ring->out];
+   if (ring->out + 1 < ring->buflen)
+      ring->out = ring->out + 1;
+   else
+      ring->out = 0;
+   return 0;
+}
+
+#endif  /* MINI_TCP */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/netmain.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/netmain.c
new file mode 100644
index 0000000..ce55436
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/netmain.c
@@ -0,0 +1,582 @@
+/*
+ * FILENAME: netmain.c
+ *
+ * Copyright 1998-2008 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Main file for the Generic Multitasking systems port of 
+ * InterNiche TCP/IP NetOS package.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: prep_ifaces(), netmain(), 
+ * ROUTINES: tcp_sleep(), tcp_wakeup(), 
+ * ROUTINES: ...and all the "tk_xxx" application tasks
+ *
+ * Contents of this file are enabled when any
+ * tasking system is in place (that is SUPERLOOP is disabled).
+ *
+ * PORTABLE: yes
+ */
+
+#define IN_NETMAIN_C    1  /* some ipport.h ports need to know this */
+
+#include "ipport.h"
+
+/* Multitasking systems should use these functions, however superloop
+ *systems need to be able to ifdef it away
+ */
+
+#ifndef SUPERLOOP /* whole file can be ifdeffed out */
+
+#ifdef OSPORT_H
+#include OSPORT_H
+#endif
+
+/* various network entry points */
+extern   char* ip_startup(void);
+extern   void  inet_timer(void);
+extern   void  netmain_init(void); /* initialize all modules */
+extern   int   create_apptasks(void);
+extern   int   prep_modules(void);
+
+#ifdef DNS_CLIENT
+#include "dns.h"
+#endif
+
+#ifdef TCP_ECHOTEST
+extern   int   tcp_echo_init(void);
+extern   void  tcp_echo_cleanup(void);
+extern   void  tcp_echo_poll(void);
+#endif
+
+#ifdef TCP_CIPHERTEST
+extern   int   tcp_cipher_init(void);
+extern   void  tcp_cipher_cleanup(void);
+extern   void  tcp_cipher_poll(void);
+#endif
+
+#ifdef PING_APP
+#ifndef OS_PREEMPTIVE
+void  ping_recv(void);     /* check for ping reply */
+#else
+void ping_process_rcvd_msgs (void);
+#endif
+#endif
+
+#ifdef USE_BROWSER
+void  peg_check(void);     /* check for PEG events & post them */
+#endif
+
+#ifdef USE_LCD
+void update_display(void);
+#endif
+
+/* include project header. Define this in ipport.h to point to a file
+ * in your project directory, i.e. "..\mpc860\osport.h"
+ */
+ 
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+
+
+#ifdef MINI_IP
+#define net_system_exit (FALSE)
+#else
+extern int net_system_exit;   /* TRUE if system is shutting down */
+#endif
+
+#ifndef TK_RETURN_UNREACHABLE
+#define TK_RETURN_UNREACHABLE() TK_RETURN_OK()
+#endif
+
+
+#ifndef APP_STACK_SIZE
+#define APP_STACK_SIZE  4096  /* default on the large side */
+#endif
+
+#ifndef SYS_SHORT_SLEEP
+#define SYS_SHORT_SLEEP 1
+#endif
+
+
+/* Define thread prototypes.  */
+
+#ifndef NO_INET_STACK
+TK_OBJECT(to_netmain);
+TK_ENTRY(tk_netmain);
+
+long     netmain_wakes  =  0;
+#endif   /* NO_INET_STACK */
+
+#ifndef NO_INET_TICK
+TK_OBJECT(to_nettick);
+TK_ENTRY(tk_nettick);
+long     nettick_wakes  =  0;
+#endif   /* NO_INET_TICK */
+
+/* per-application thread definitions */
+#ifdef PING_APP
+TK_OBJECT(to_pingcheck);
+TK_ENTRY(tk_pingcheck);
+long     pingcheck_wakes   =  0;
+#endif
+
+#ifdef TCP_ECHOTEST
+TK_OBJECT(to_echotest);
+TK_ENTRY(tk_echotest);
+long     echotest_wakes =  0;
+#endif
+
+#ifdef TCP_CIPHERTEST
+TK_OBJECT(to_ciphertest);
+TK_ENTRY(tk_ciphertest);
+long     ciphertest_wakes =  0;
+#endif
+
+#ifdef USE_SNTP_V4
+TK_OBJECT(to_sntpv4);
+TK_ENTRY(tk_sntpv4);
+long     sntpv4_wakes   =  0;
+extern int sntpv4_task (void);
+#endif
+/* 
+ * Altera Niche Stack Nios port modification:
+ * Defines for the priorities and stack sizes are setup 
+ * in ipport.h. Note that we are providing individual
+ * priorities pre-assigned. This is to allow user-control
+ * of setting prioritesi in the uC/OS environment where
+ * each task must have a unqique priority; the original
+ * stack port code automatically assigned priority values.
+ */
+struct inet_taskinfo nettasks[]  =  {
+#ifndef NO_INET_STACK
+   {
+      &to_netmain,   /* netmain should always be first in this array */
+      "Inet main",
+      tk_netmain,
+      TK_NETMAIN_TPRIO,
+      TK_NETMAIN_SSIZE,
+   },
+#endif   /* NO_INET_STACK */
+#ifndef NO_INET_TICK
+  
+   {
+      &to_nettick,
+      "clock tick",
+      tk_nettick,
+      TK_NETTICK_TPRIO,
+      TK_NETTICK_SSIZE,
+   },
+#endif   /* NO_INET_TICK */
+   /************** optional application threads ***************/
+#ifdef PING_APP
+   {
+      &to_pingcheck,
+      "PING client",
+      tk_pingcheck,
+      TK_PINGCHECK_TPRIO,
+      TK_PINGCHECK_SSIZE,
+   },
+#endif
+#ifdef TCP_ECHOTEST
+   {
+      &to_echotest,
+      "tcp echo",
+      tk_echotest,
+      TK_ECHOTEST_TPRIO,
+      TK_ECHOTEST_SSIZE,
+   },
+#endif
+
+#ifdef TCP_CIPHERTEST
+   {
+      &to_ciphertest,
+      "Crypto Engine Server",
+      tk_ciphertest,
+      TK_CIPHERTEST_TPRIO,
+      TK_CIPHERTEST_SSIZE,
+   },
+#endif
+
+#ifdef USE_SNTP_V4
+   {
+      &to_sntpv4,
+      "SNTPv4 client",
+      tk_sntpv4,
+      TK_SNTPC_TPRIO,
+      TK_SNTPC_SSIZE*4,
+   },
+#endif
+
+};
+
+int      num_net_tasks  = sizeof(nettasks)/sizeof(struct inet_taskinfo);
+
+int iniche_net_ready = FALSE;
+
+
+
+/* FUNCTION: netmain()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+int
+netmain(void)
+{
+   int   i;
+   int   e;
+
+   iniche_net_ready = FALSE;
+
+   e = prep_modules();
+
+   /* Create the threads for net, timer, and apps */
+   for (i = 0; i < num_net_tasks; i++)
+   {
+      e = TK_NEWTASK(&nettasks[i]);
+      if (e != 0)
+      {
+         dprintf("task create error\n");
+         panic((char *)&nettasks[i].name);
+         return -1;  /* compiler warnings */
+      }
+   }
+   
+   e = create_apptasks();
+   if (e != 0) 
+   {
+      dprintf("task create error\n");
+      panic("netmain");
+      return -1;  /* compiler warnings */
+   }
+
+#ifndef NO_INET_STACK
+#ifdef MAIN_TASK_IS_NET
+   tk_netmain(TK_NETMAINPARM);
+   panic("net task return");
+   return -1;
+#else
+   return 0;
+#endif
+#endif   /* NO_INET_STACK */
+}
+
+/* FUNCTION: tk_netmain()
+ *
+ * Main thread for starting the net. After startup, it settles into
+ * a loop handling received packets. This loop sleeps until a packet
+ * has been queued in rcvdq; at which time it should be awakend by the
+ * driver which queued the packet.
+ *
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+#ifndef NO_INET_STACK
+TK_ENTRY(tk_netmain)
+{
+   netmain_init(); /* initialize all modules */
+
+   iniche_net_ready = TRUE;    /* let the other threads spin */
+
+   for (;;)
+   {
+      TK_NETRX_BLOCK();
+      netmain_wakes++;  /* count wakeups */
+
+      /* see if there's newly received network packets */
+      if (rcvdq.q_len)
+         pktdemux();
+
+      /* do not kill packet demux on net_system_exit. It may be
+       * vital to a clean shutdown 
+       */
+#ifdef USE_LCD
+      update_display();
+#endif
+   }
+
+   USE_ARG(parm);  /* TK_ENTRY macro defines tk_netmain with 1 arg parm */
+   TK_RETURN_UNREACHABLE();
+}
+#endif   /* NO_INET_STACK */
+
+
+
+/* FUNCTION: tk_nettick
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+#ifdef DHCP_CLIENT
+extern   int dhc_second(void);
+#endif
+
+#ifndef NO_INET_TICK
+TK_ENTRY(tk_nettick)
+{
+   /* wait till the stack is initialized */
+   while (!iniche_net_ready)
+   {
+      /* The DHCP Client state machine might need some cycles
+       * at this point. This is needed when we start by sending a
+       * request and then we receive a NAK. At this point the DHCP
+       * client is reset to INIT state and dhc_second() needs to be
+       * run to restart it.
+       */
+#ifdef DHCP_CLIENT
+      dhc_second();
+#endif
+      TK_SLEEP(1);
+   }
+
+   for (;;)
+   {
+      TK_SLEEP(SYS_SHORT_SLEEP);
+      nettick_wakes++;  /* count wakeups */
+      inet_timer();  /* let various timeouts occur */
+      /* do not kill timers on net_system_exit. They may be
+       * vital to a clean shutdown 
+       */
+   }
+   USE_ARG(parm);  /* TK_ENTRY macro defines tk_nettick with 1 arg parm */
+   TK_RETURN_UNREACHABLE();
+}
+#endif   /* NO_INET_TICK */
+
+
+
+/* the application threads which follow work on a "controlled 
+ * polling" basis: they wake up periodically and poll for work. If 
+ * there is outstanding work, the next wake is accellerated to give 
+ * better performance under heavy loads. The FTP and Web tasks could 
+ * aternativly be set up to use blocking sockets, in which case the 
+ * loops below would only cann the "xxx_check()" routines - 
+ * suspending would be handled by the TCP code. 
+ */
+
+
+#ifdef PING_APP
+
+/* The PING client task waits for the ping semaphore to be signaled.
+ * The semaphore is signaled by other tasks such as console task, Telnet
+ * server task, and timer task after they have deposited a message into
+ * the PING client task's message queue.  These messages provide 
+ * configuration parameters, initiate (or terminate) ping requests, and 
+ * provide periodic timeout notification.
+ */
+
+/* FUNCTION: tk_pingcheck()
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+extern   PING_INFO   pingq;
+
+TK_ENTRY(tk_pingcheck)
+{
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+   for (;;)
+   {
+#ifndef OS_PREEMPTIVE
+      ping_recv();         /* check for ping reply */
+      TK_BLOCK();          /* block right here, upcall will wake us */
+      pingcheck_wakes++;   /* count wakeups */
+#else
+      wait_app_sem (PING_SEMID);
+      pingcheck_wakes++; /* count wakeups */
+      ping_process_rcvd_msgs (); /* process messages from other tasks */
+#endif  /* OS_PREEMPTIVE */
+
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+#endif /* PING_APP */
+
+
+/* FUNCTION: tk_echotest()
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+#ifdef TCP_ECHOTEST
+TK_ENTRY(tk_echotest)
+{
+   int e;
+
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+   e=tcp_echo_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(tcp_echo_cleanup);
+   }
+
+   for (;;)
+   {
+      tcp_echo_poll();     /* This blocks on select() */
+      tk_yield();          /* give up CPU in case it didn't block */
+      echotest_wakes++;    /* count wakeups */
+
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+#endif /* TCP_ECHOTEST */
+
+/* FUNCTION: tk_ciphertest()
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+#ifdef TCP_CIPHERTEST
+TK_ENTRY(tk_ciphertest)
+{
+   int e;
+
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+   e=tcp_cipher_init();
+   if ( e == SUCCESS )
+   {
+      exit_hook(tcp_cipher_cleanup);
+   }
+
+   for (;;)
+   {
+      tcp_cipher_poll();     /* This blocks on select() */
+      tk_yield();          /* give up CPU in case it didn't block */
+      ciphertest_wakes++;    /* count wakeups */
+
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+#endif /* TCP_CIPHERTEST */
+
+
+
+#ifdef USE_SNTP_V4
+
+TK_ENTRY(tk_sntpv4)
+{
+   while (!iniche_net_ready)
+      TK_SLEEP(1);      
+
+   for (;;)
+   {
+      sntpv4_task ();
+      if (net_system_exit)
+         break;
+   }
+
+   TK_RETURN_OK();
+}
+
+#endif /* USE_SNTP_V4 */
+
+
+#ifdef  TCPWAKE_RTOS
+
+/* If we're using a tasking system that does not explicitly
+ * support blocking on events (i.e. tcp_sleep()) add the support
+ * here:
+ */
+#ifndef MAX_EVENTS
+#define  MAX_EVENTS  12
+#endif
+
+/* declare an array of structs to store blocking events */
+
+struct tk_wait_event
+{
+   void *   event;
+   TK_OBJECT_REF(task);
+};
+
+struct tk_wait_event tk_eventlist[MAX_EVENTS];
+
+/* debug counters */
+long     tcp_no_taskslot   =  0;
+
+
+/* FUNCTION: tcp_sleep()
+ * 
+ * PARAM1: void * event
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_sleep(void * event)
+{
+   int   i;
+
+   /* search event array for an unused slot */
+   for (i = 0; i < MAX_EVENTS; i++)
+   {
+      if (tk_eventlist[i].event == 0)     /* found a slot */
+      {
+         tk_eventlist[i].event = event;   /* save event to wake up on */
+         tk_eventlist[i].task = TK_THIS;  /* save calling task */
+         UNLOCK_NET_RESOURCE(NET_RESID);  /* free stack mutex */
+         TK_BLOCK();                      /* suspend calling task */
+         LOCK_NET_RESOURCE(NET_RESID);    /* we woke up - reenter stack */
+         tk_eventlist[i].event = NULL;    /* clear array entry */
+         return;
+      }
+   }
+   /* fall to here if we ran out of free event slots. Best thing to do is
+    * let system spin, then return to caller for another sleep test.
+    */
+   tcp_no_taskslot++;
+   tk_yield();
+}
+
+
+/* FUNCTION: tcp_wakeup()
+ * 
+ * PARAM1: void * event
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_wakeup(void * event)
+{
+   int   i;
+
+   /* search event array for blocked event */
+   for (i = 0; i < MAX_EVENTS; i++)
+   {
+      if (tk_eventlist[i].event == event) /* found one */
+         TK_WAKE_EVENT(tk_eventlist[i].task);   /* wake the task */
+   }
+}
+#endif   /* TCPWAKE_RTOS */
+
+
+#endif   /* SUPERLOOP - whole file can be ifdeffed out */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nextcarg.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nextcarg.c
new file mode 100644
index 0000000..cc04b91
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nextcarg.c
@@ -0,0 +1,74 @@
+/*
+ * FILENAME: nextcarg.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: nextcarg(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software */
+
+#include "ipport.h"
+#include "in_utils.h"
+
+
+
+/* FUNCTION: nextcarg()
+ *
+ * nextcarg() - return next arg from comma delimited arg list passed. 
+ * Current (passed) arg is NULL terminated. If the arg points to a 
+ * string enclosed in quotes, the following happens. 1. say 
+ * arg="string in quotes", other_arg 2. Move the string so that first 
+ * quote is overwritten. arg=string in quotes", other_arg 3. Put a 
+ * NULL instead of the last quote. That is , arg=string in quotes 4. 
+ * nextarg=other_arg The above logic will allow the caller to use 
+ * nextcarg() seamlessly, irrespective of whether the input string is 
+ * enclosed in quotes or not. Returns pointer to next arg, or NULL if 
+ * no more args. 
+ *
+ * 
+ * PARAM1: char * arg
+ *
+ * RETURNS: 
+ */
+
+char *   
+nextcarg(char * arg)
+{
+   char *   cp;
+
+   cp = strchr(arg, ',');
+
+   /* NULL terminate passed arg weather cp is set or not: */
+   if ( *arg == '\"' )
+   {
+      unsigned len = cp-arg-1 ;
+      MEMMOVE(arg,arg+1,len);  /* Move the string so that
+                                  the first quote is overwritten */
+      while (*arg != '\"' )
+         arg++;
+   }
+   else
+   {
+      while (*arg != ',' && *arg > ' ')
+         arg++;
+   }
+   *arg = 0;
+
+   if (!cp) /* no next arg; return NULL */
+      return NULL;
+
+   cp++;       /* move cp past comma */
+   while (*cp <= ' ') cp++;
+      return cp;
+}
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nrmenus.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nrmenus.c
new file mode 100644
index 0000000..4e83745
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nrmenus.c
@@ -0,0 +1,2126 @@
+/*
+ * FILENAME: nrmenus.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Software Menus for InterNiche sample/demo TTY console.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: do_dtrap(), ishexdigit(), hexnibble(), 
+ * ROUTINES: atoh(), atohl(), hex2bin(), agent(), setcommstr(), dumpqueues(), 
+ * ROUTINES: dumpbufs(), qname(), showver(), sendtrap(), dump_bytes(), 
+ * ROUTINES: menu_exit(), udpecho(), tcpecho(), show_routes(), 
+ * ROUTINES: mn_add_route(), set_ipaddr(), gethostbynametest(), gethost2test()
+ * ROUTINES: ping_sethost(), ping_setdelay(), ping_setlength(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1996 by NetPort */
+
+
+#include "ipport.h"
+
+
+#ifdef IN_MENUS
+
+#include "in_utils.h"
+
+#include "q.h"          /* need these 3 to pull in ifNumber */
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+#include "menu.h"
+#include "app_ping.h"
+#include "pmtu.h"
+
+#include "dns.h"
+
+#include "nvparms.h"
+
+#ifdef INCLUDE_INICHE_LOG
+#include "iniche_log.h"
+#endif
+
+#ifdef IP_V6
+#include "ip6.h"
+#endif   /* IP_V6 */
+
+#ifndef TIMEFOR1TICK
+#define TIMEFOR1TICK       (1000/TPS)
+#endif
+
+#define  t_time   unsigned long
+
+extern   int   station_state(void * pio);
+extern   int   mh_stats(void * pio);
+extern   int   set_upc(void * pio);
+extern   int   iface_stats(void * pio);
+extern   int   linkstats(void * pio);
+extern   int   dumpbufs(void * pio);
+extern   int   dump_buf_estats (void * pio);
+#ifdef HEAPBUFS
+extern   int   dump_hbuf_stats (void * pio);
+#endif
+extern   int   dumpqueues(void * pio);
+extern   int   showver (void * pio);
+extern   int   dns_state (void * pio);
+extern   int   set_nv_params (void * pio);
+extern   int   edit_nv_params(void * pio);
+
+#ifdef INCLUDE_TCP
+#ifndef MINI_TCP
+extern   int   mbuf_stat(void * pio);
+extern   int   mbuf_list(void * pio);
+#endif   /* MINI_TCP */
+extern   int   tcp_stat(void * pio);
+extern   int   sock_list(void * pio);
+extern   int   tcp_bsdconnstat(void * pio);
+extern   int   tcp_bsdsendstat(void * pio);
+extern   int   tcp_bsdrcvstat(void * pio);
+#endif   /* INCLUDE_TCP */
+
+#ifdef IP_ROUTING
+int   show_routes    (void * pio);
+int   mn_add_route   (void * pio);
+extern RTMIB btreeRoot;
+#endif   /* IP_ROUTING */
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+extern   int igmp_print_stats (void * pio);
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+
+extern   int   vfs_dir(void * pio);
+extern   int   tk_stats(void * pio);
+
+#ifdef UDPSTEST
+extern   int   udpecho(void * pio);
+extern   int   udp_secho_init(void * pio);
+extern   int   udp_cecho_close(void * pio);
+extern   int   udp_secho_close(void * pio);
+extern   int   udp_echo_stats(void * pio);
+extern   int   udp_sendecho(void * pio, ip_addr fhost, int len, long times);
+#endif
+
+#ifdef TCP_ECHOTEST
+extern   int   tcpecho(void * pio);
+extern   int   tcp_secho_init (void * pio);
+extern   int   tcp_secho_close(void * pio);
+extern   int   tcp_cecho_close(void * pio);
+extern   int   tcp_echo_stats (void * pio);
+extern   int   tcp_sendecho(void * pio, ip_addr fhost, long len, long times);
+#endif
+
+#ifdef TCP_CIPHERTEST
+extern   int   tcp_scipher_init (void * pio);
+extern   int   tcp_scipher_close(void * pio);
+extern   int   tcp_cipher_stats (void * pio);
+#endif
+
+#ifdef DNS_CLIENT
+int gethostbynametest(void * pio);
+int nslookup_reverse(void * pio);
+extern int setdnssvr(void * pio);
+extern int dnc_database(void * pio);
+#ifdef IP_V6
+int gethost2test(void * pio);
+#endif   /* IP_V6 */
+#endif   /* DNS_CLIENT */
+
+#ifdef DNS_CLIENT_UPDT
+extern   int   nsupdatetest (void * pio);
+extern   int   dns_update(char * soa, char * dname, ip_addr ipaddr, u_long ttl,
+                           void * pio);
+extern u_long dns_update_server;
+static int setupdns(void * pio);
+
+#endif /* DNS_CLIENT_UPDT */
+
+#ifdef DNS_CLIENT_TEST_UPDT
+extern int nsddnstest(void * pio);
+#endif /* DNS_CLIENT_TEST_UPDT */
+
+
+#ifdef DHCP_CLIENT
+int   dhc_stats      (void * pio);
+#endif
+
+
+#ifdef NS_DDNS
+void dns_dumpcache(void * pio);
+#endif
+
+int send_grat_arp(void * pio);
+
+#ifdef  LOSSY_IO
+int   setlossy(void * pio);
+extern unsigned long myrandNum;
+extern unsigned long myrandDenom;
+#endif
+
+#ifdef   MINI_PING
+int   mini_ping(void * pio);
+#endif   /* MINI_PING */
+
+int   menu_exit (void * pio);
+int   do_dtrap (void * pio);
+int   defaulttype(void * pio);
+int   dump_bytes(void * pio);
+int   set_ipaddr(void * pio);
+
+char * qname(PACKET pkt);  /* get name of queue packet is in */
+
+extern   ip_addr  activehost;    /* common host parameter */
+extern   u_long   pingdelay;     /* common delay parameter (1 second) */
+extern   int      deflength;     /* common length parameter */
+
+extern   int   settrapsize(void * pio);
+
+#ifdef USE_PROFILER
+extern   struct menu_op profmenu[5];
+#endif
+
+#ifdef NATRT
+extern   void  nat_re_init(void);   /* refresh NAT router's parameters */
+#endif
+
+#ifdef ROUTE_TEST
+extern   struct menu_op rt_menu[10];
+#endif   /* ROUTE_TEST */
+
+#ifdef CHANGE_PWD
+int   change_pwd(void * pio);
+#endif
+int   list_users(void * pio);
+int   menu_add_user(void * pio);
+unsigned atoh(char * buf);
+int set_cdelay(void * pio);
+int set_chost(void * pio);
+int set_clength(void * pio);
+
+#ifdef PING_APP
+int ping_set_parm (unsigned long int parm_type, unsigned long int value);
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+/* array of menu options, see menu.h */
+struct menu_op mainmenu[]  = 
+{
+   { "general",  stooges,          "main menu" } ,      /* menu ID */
+   { "help",     help,             "help with menus" } ,
+   { "state",    station_state,    "show current station setup" } ,
+   { "sendarp",  send_grat_arp,    "send a gratuitous ARP" },
+#ifdef UDPSTEST
+   { "uesend",   udpecho, "open UDP echo client, send UDP echo packet" } ,
+   { "uesinit",  udp_secho_init,   "start UDP echo server" } ,
+   { "uechalt",  udp_cecho_close,  "close UDP echo client" } ,
+   { "ueshalt",  udp_secho_close,  "close UDP echo server" } ,
+   { "uestats",  udp_echo_stats,   "UDP echo statistics" } ,
+#endif
+#ifdef TCP_ECHOTEST
+   { "tesend",   tcpecho, "open TCP echo client, send TCP echo packet" } ,
+   { "tesinit",  tcp_secho_init,   "start TCP echo server" } ,
+   { "teshalt",  tcp_secho_close,  "close TCP echo server" } ,
+   { "techalt",  tcp_cecho_close,  "close TCP echo client" } ,
+   { "testats",  tcp_echo_stats,   "TCP echo statistics" } ,
+#endif
+#ifdef TCP_CIPHERTEST
+   { "tesCipherInit",  tcp_scipher_init,   "start Crypto Engine server" } ,
+   { "tesServerCipherhalt",  tcp_scipher_close,  "close Crypto Engine server" } ,
+   { "teCipherstats",  tcp_cipher_stats,   "Crypto Engine statistics" } ,
+#endif
+
+#ifdef PING_APP
+   /* delay, host, and length parameters (used by PING_APP) */
+   { "p4delay",  ping_setdelay,    "set milliseconds to wait between pings" },
+   { "p4host",   ping_sethost,     "set default active IP host" },
+   { "p4length", ping_setlength,   "set default ping packet length" },
+#endif
+
+   /* common delay, host, and length parameters (used by various applications) */
+   { "delay",    set_cdelay,       "set common delay parameter" },
+   { "host",     set_chost,        "set common host parameter" },
+   { "length",   set_clength,      "set common length parameter" },
+
+   { "quit",     menu_exit,        "quit station program" } ,
+#ifdef   MINI_PING
+   { "ping",     mini_ping,        "send a ping" } ,
+#endif   /* MINI_PING */
+#ifdef INCLUDE_NVPARMS
+   { "nvset",    set_nv_params,    "set non-volatile parameters" } ,
+   { "nvedit",   edit_nv_params,   "edit non-volatile parameters" } ,
+#endif
+#ifdef DNS_CLIENT_UPDT  
+   { "setupdns",    setupdns,       "set server for dynamic update" } ,
+#endif /* DNS_CLIENT_UPDT */  
+   { "setip",    set_ipaddr,       "set interface IP address" } ,
+   { "version",  showver,          "display version information" } ,
+   { "!command", NULL,             "pass command to OS shell" } ,
+   { NULL } ,
+};
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+/* array of menu options, see menu.h */
+struct menu_op diagmenu[]  =
+{
+   { "diagnostic",stooges,      "diagnostic aid menu" } ,
+#if defined(NET_STATS) && defined(INCLUDE_ARP)
+   { "arps",     arp_stats,     "display ARP stats and table" } ,
+#endif   /* INCLUDE_ARP && NET_STATS */
+   { "buffers",  dumpbufs,      "display free q buffer stats" } ,
+   { "bufstat",  dump_buf_estats, "display buffer error statistics" } ,
+#ifdef HEAPBUFS
+   { "hbufstat", dump_hbuf_stats, "display heap buffer diagnostics" } ,
+#endif
+   { "queues",   dumpqueues,    "dump packet buffer queues" } ,
+   { "dbytes",   dump_bytes,    "dump block of memory" } ,
+   { "debug",    setdebug,      "set IP stack debug tracing" } ,
+   { "dtrap",    do_dtrap,      "try to hook debugger" } ,
+#ifdef INCLUDE_INICHE_LOG
+   { "glog",     glog_app,     "glog [options]" } ,
+#endif
+#ifdef VFS_FILES
+   { "dir",      vfs_dir,       "directory of VFS files" } ,
+#endif   /* VFS_FILES */
+#ifdef  LOSSY_IO
+   { "lossy",    setlossy,      "set lossy packet IO options" } ,
+#endif
+#if defined(NET_STATS) || defined(IP_V6)
+   { "iface",    iface_stats,   "display net interface stats" } ,
+#endif
+   { "linkstats",linkstats,     "display link layer specific stats" } ,
+#ifdef HEAP_STATS    /* statistics keeping npalloc() and npfree() */
+   { "memory",   mh_stats,      "list currently alloced memory" } ,
+#endif   /* HEAP_STATS */
+
+#ifdef DNS_CLIENT
+   { "nsdatabase", dnc_database,   "dump DNS client database" } ,
+   { "nslookup", gethostbynametest,"do DNS gethostbyname()" } ,
+   { "nslookupr", nslookup_reverse, "do reverse DNS" } ,
+   { "setdnssvr", setdnssvr,       "set up DNS Servers" } ,
+#ifdef IP_V6
+   { "ns2lookup",   gethost2test,  "do DNS gethostbyname2( AF_INET6)" } ,
+#endif   /* IP_V6 */
+
+#ifdef  NS_DDNS 
+   { "dnsdump", dns_dumpcache,  "dump DNS cache" } ,
+#endif  /* NS_DDNS */
+
+#ifdef DNS_CLIENT_TEST_UPDT
+   { "nsddnstest", nsddnstest,  "do Dynamic DNS test" } ,
+#endif  /* DNS_CLIENT_TEST_UPDT */ 
+
+#ifdef  DNS_CLIENT_UPDT 
+   { "nsupdate", nsupdatetest,  "do Dynamic DNS update" } ,
+#endif  /* DNS_CLIENT_UPDT */
+#ifdef NET_STATS
+   { "dnsstats", dns_state,     "DNS setup & statistics" } ,
+#endif
+#endif   /* DNS_CLIENT */
+
+#ifdef INCLUDE_TCP
+#ifdef NET_STATS
+#ifndef MINI_TCP
+   { "mbuf",     mbuf_stat,      "display mbuf stats" } ,
+   { "mlist",    mbuf_list,      "display mbufs in use" } ,
+#endif   /* MINI_TCP */
+   { "tcp",      tcp_stat,       "display TCP stats" } ,
+   { "sockets",  sock_list,      "display socket list" } ,
+   { "tbconn",   tcp_bsdconnstat,"tcp BSD connection stats" } ,
+   { "tbsend",   tcp_bsdsendstat,"tcp BSD send stats" } ,
+   { "tbrcv",    tcp_bsdrcvstat, "tcp BSD receive stats" } ,
+#endif   /* NET_STATS */
+#endif   /* INCLUDE_TCP */
+
+#ifdef IP_ROUTING
+   { "routes",   show_routes,    "display IP route table" } ,
+   { "rtadd",    mn_add_route,   "manually add IP route to table" } ,
+#endif   /* IP_ROUTING */
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   { "igmp",     igmp_print_stats, "Print IGMPv1/v2 statistics" } ,
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+
+   { "allocsize",settrapsize,    "set size for alloc() breakpoint" } ,
+#ifdef NET_STATS
+   { "ipstat",   ip_stats,       "display IP layer stats" } ,
+   { "iprstat",  ipr_stats,      "display IP reassembly stats" } ,
+   { "icmpstat", icmp_stats,     "display ICMP layer stats" } ,
+   { "udp",      udp_stats,      "display UDP layer stats" } ,
+#endif
+   { "upcall",   set_upc,        "trace received packets" } ,
+#if defined(INICHE_TASKS) || defined(CHRONOS)
+   { "tkstats",  tk_stats,       "tasking system status" } ,
+#endif
+#ifdef DHCP_CLIENT
+#ifdef NET_STATS
+   { "dcstats",  dhc_stats,      "DHCP Client statistics" } ,
+#endif
+#endif
+#ifdef IP_PMTU
+#ifdef NET_STATS
+   { "pmtu",     pmtu_stats,     "Path MTU cache statistics" } ,
+#endif
+#endif
+#ifdef CHANGE_PWD
+   { "changepwd",change_pwd,    "change user password" } ,
+#endif
+#ifdef NET_STATS
+   { "users",    list_users,    "list all users" } ,
+   { "adduser",  menu_add_user, "add a new user" } ,
+#endif
+   { NULL } ,
+};
+
+struct menu_op *  menus[MAX_MENUS] =   /* array of ptrs to menu groups */
+{
+   &mainmenu[0],  /* general menu should come 1st */
+   &diagmenu[0],  /* Diagnostic menu              */
+#ifdef ROUTE_TEST
+   &rt_menu[0],
+#endif   /* ROUTE_TEST */
+#ifdef USE_PROFILER
+   &profmenu[0],
+#endif
+   /* add new menus here */
+   NULL,          /* spare slot(s) for dymanic menu additions */
+   NULL,          /* Eg., RIP , NATRT, TELNET, PING install dynamic menus */
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL           /* NULL slot at end - end of menus marker */
+};
+
+int nummenus = (sizeof(menus)/sizeof(void*)); /* number of menus */
+
+/* module version array */
+char *versions[MAX_MENUS] =
+{
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
+   NULL
+};
+
+NET      if_netbytext(void * pio, char * iftext);
+int      if_configbyname(NET);   /* configure a net based on it's name */
+
+
+/* FUNCTION: do_dtrap()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int do_dtrap(void * pio)
+{
+   USE_VOID(pio);
+   dtrap();
+   return 0;
+}
+
+
+#ifdef  LOSSY_IO
+extern int  in_lossrate;
+
+int
+setlossy(void * pio)
+{
+   char *   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+
+   if(*cp == 'r')
+   {
+      NDEBUG |= LOSSY_RX;
+   }
+   else if(*cp == 't')
+   {
+      NDEBUG |=  LOSSY_TX;
+   }
+   else if(*cp == 'o')
+   {
+      NDEBUG &= ~(LOSSY_TX|LOSSY_RX);
+   }
+   else if(isdigit(*cp))
+   {
+	   int i,j;
+
+      i = atoi(cp);
+
+	  if (i <= 0)
+	  {
+         ns_printf(pio, "usage:  denominator[%d] <= 0.\n", i);
+         ns_printf(pio, "usage:  ['rx'|'tx'|'off'|numerator denominator ]\nusage:   where numerator/denominator will be the loss rate.\n");
+	  }
+	  else
+	  {
+           cp =  nextarg(cp);
+
+		   if(isdigit(*cp))
+		   {
+              j = atoi(cp);
+	          if (j <= 0)
+			  {
+                 ns_printf(pio, "usage:  *** denominator[%d] <= 0.\n", j);
+                 ns_printf(pio, "usage:  ['rx'|'tx'|'off'|numerator denominator ]\nusage:   where numerator/denominator will be the loss rate.\n");
+			  }
+			  else
+	          if (i >= j)
+			  {
+                 ns_printf(pio, "usage:  *** numerator[%d] >= denominator[%d].\n", i,j);
+                 ns_printf(pio, "usage:  ['rx'|'tx'|'off'|numerator denominator ]\nusage:   where numerator/denominator will be the loss rate.\n");
+			  }
+			  else
+			  {
+			     myrandNum = i;
+			     myrandDenom = j;
+			  }
+		   }
+		   else
+                 ns_printf(pio, "usage:  ['rx'|'tx'|'off'|numerator denominator ]\nusage:   where numerator/denominator will be the loss rate.\n");
+	  }
+   }
+   else
+   {
+      ns_printf(pio, "usage:  ['rx'|'tx'|'off'|numerator denominator ]\nusage:   where numerator/denominator will be the loss rate.\n");
+   }
+
+   if((NDEBUG & (LOSSY_RX|LOSSY_TX)) == 0)
+      ns_printf(pio, "lossy data is disabled\n");
+   else
+   {
+      ns_printf(pio, "pkt loss rate currently %d in %d ", myrandNum, myrandDenom);
+      if(NDEBUG & LOSSY_RX)
+         ns_printf(pio, "RX ");
+      if(NDEBUG & LOSSY_TX)
+         ns_printf(pio, "TX");
+      ns_printf(pio, "\n");
+   }
+   
+   return 0;
+}
+#endif   /* LOSSY_IO */
+
+extern   queue    bigfreeq;   /* big free buffers */
+extern   queue    lilfreeq;   /* small free buffers */
+extern   unsigned    lilbufs;
+extern   unsigned    bigbufs;
+
+
+
+/* FUNCTION: dumpqueues()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+dumpqueues(void * pio)
+{
+   ns_printf(pio,"bigfreeq: head:%p, tail:%p, len:%d, min:%d, max:%d\n",
+    (void far *)bigfreeq.q_head, (void far *)bigfreeq.q_tail, 
+    bigfreeq.q_len, bigfreeq.q_min, bigfreeq.q_max);
+
+   ns_printf(pio,"lilfreeq: head:%p, tail:%p, len:%d, min:%d, max:%d\n",
+    (void far *)lilfreeq.q_head, (void far *)lilfreeq.q_tail, 
+    lilfreeq.q_len, lilfreeq.q_min, lilfreeq.q_max);
+
+   ns_printf(pio,"rcvdq: head:%p, tail:%p, len:%d, min:%d, max:%d\n",
+    (void far *)rcvdq.q_head, (void far *)rcvdq.q_tail, 
+    rcvdq.q_len, rcvdq.q_min, rcvdq.q_max);
+
+   return 0;
+}
+
+
+
+#ifdef NPDEBUG
+extern   PACKET   pktlog[MAXPACKETS];
+#endif
+
+/* FUNCTION: dumpbufs()
+ *
+ * dumpbufs() - dump packet free queues
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+dumpbufs(void * pio)
+{
+#ifdef NPDEBUG
+   int   i;
+   PACKET pkt;
+   int   lines =  1; /* output line count for paging */
+   char *   cp;
+   int   offset   =  0;
+
+   /* optional parameter is how far into the each buffer to start display */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+   if (cp && *cp)
+   {
+      offset = atoi(cp);
+   }
+
+   ns_printf(pio,"PACKET    len  buffer    que data offset %d\n",offset);
+   for (i = 0; i < (int)(lilbufs+bigbufs); i++ )
+   {
+      pkt = pktlog[i];
+      ns_printf(pio,"%p,%4d,%p,%s:",
+       pkt, pkt->nb_blen, pkt->nb_buff, qname(pkt));
+      hexdump(pio,pkt->nb_buff + offset, 12);
+      lines++;
+      if ( con_page(pio,lines) )
+         return 0 ;
+   }
+
+#else
+   ns_printf(pio,"Not debug build\n");
+#endif
+   return 0;
+}
+
+#ifdef INCLUDE_TCP
+#ifdef NET_STATS
+char * socket_queue_name(PACKET pkt);
+#endif   /* NET_STATS */
+#endif   /* INCLUDE_TCP */
+
+
+/* FUNCTION: qname()
+ *
+ * return 3 char name of queue PACKET is in
+ * 
+ * PARAM1: PACKET pkt
+ *
+ * RETURNS: 
+ */
+
+char * qname(PACKET pkt)
+{
+   qp tmp;
+#ifdef INCLUDE_TCP
+#ifdef NET_STATS
+   char *   so_queue_name;
+#endif /* NET_STATS   */
+#endif /* INCLUDE_TCP */
+
+   /* search for packet in the known queues: */
+   for (tmp = lilfreeq.q_head; tmp; tmp = tmp->qe_next)
+      if (tmp == (qp)pkt)
+      return "lil";
+   for (tmp = bigfreeq.q_head; tmp; tmp = tmp->qe_next)
+      if (tmp == (qp)pkt)
+      return "big";
+   for (tmp = rcvdq.q_head; tmp; tmp = tmp->qe_next)
+      if (tmp == (qp)pkt)
+      return "rcv";
+
+#ifdef INCLUDE_TCP
+#ifdef NET_STATS
+   /* check to see if the packet is in one of the socket queues */
+   so_queue_name = socket_queue_name(pkt);
+   if (so_queue_name)
+      return so_queue_name;
+#endif /* NET_STATS */
+#endif /* INCLUDE_TCP */
+
+   return "non";
+}
+
+
+
+/* FUNCTION: showver()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+showver(void * pio)
+{
+   int i;
+   extern   char *name;
+
+   /* NicheStack version */
+   ns_printf(pio,"%s\n", name);
+
+   /* module versions */
+   for (i = 0; i < MAX_MENUS; i++)
+   {
+      if (versions[i] != (char *)NULL)
+         ns_printf(pio, "%s,", versions[i]);
+   }
+   ns_printf(pio, "\n");
+
+   return 0;
+}
+
+
+extern   char *   prompt;
+char *   oldprompt   = "OOPS> ";
+
+/* if we have to deal with Intel's 16 bit segmented architecture */
+#ifdef SEG16_16
+
+/* FUNCTION: dump_bytes()
+ *
+ * segment:offset version of dump_bytes()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+dump_bytes(void * pio)
+{
+   char *   cp;
+   unshort  seg,  offset;
+   int   length;
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* see if user put addr on cmd line */
+   if (!*cp)
+      goto db_prompt;
+   seg = (unshort)atoh(cp);
+cp = strchr(cp, ':');   /* find colon in string */
+   if (!cp)
+      goto db_prompt;
+   cp++;
+   offset = (unshort)atoh(cp);
+   cp = nextarg(cp);    /* see if user specified length to dump */
+   if (*cp)    /* cp should point to end of args or length */
+      length = (int)atoh(cp);
+   else     /* no length on command line, set a reasonable default */
+      length = 16;
+
+   hexdump(pio,_MK_FP(seg, offset), length);
+   return 0;
+
+db_prompt:     /* prompt user for correct format */
+   ns_printf(pio,"enter memory location in hex seg:offset form, followed by optional length.\n");
+   return -1;
+}
+
+#else    /* SEG16_16 */
+
+/* FUNCTION: dump_bytes()
+ *
+ * flat memory version of dump_bytes()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+dump_bytes(void * pio)
+{
+   char *   cp;
+   unsigned int address;
+   int   length;
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* see if user put addr on cmd line */
+   if (!*cp)
+      goto db_prompt;
+   address = atoh(cp);
+   cp = nextarg(cp);    /* see if user specified length to dump */
+   if (*cp)    /* cp should point to end of args or length */
+      length = (int)atoh(cp);
+   else     /* no length on command line, set a reasonable default */
+      length = 16;
+
+   hexdump(pio,(void *) address, length);
+   return 0;
+
+db_prompt:     /* prompt user for correct format */
+   ns_printf(pio,"enter memory location in hex, followed by optional length.\n");
+   return -1;
+}
+
+#endif      /* SEG16_16 */
+
+
+/* FUNCTION: menu_exit()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+menu_exit(void * pio)
+{
+   USE_VOID(pio);
+   netexit(0);    /* shut down hardware & exit to system */
+   return 0;   /* keeps compiler from whining */
+}
+
+
+#ifdef UDPSTEST
+
+/* FUNCTION: udpecho()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int udpecho(void * pio)
+{
+   long  times =  1;
+   char *   arg2;
+
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);  /* get iteration arg from cmd line */
+   if (arg2 && *arg2)
+      times = atol(arg2);
+
+   if (times < 1)
+   {
+      ns_printf(pio,"command line arg must be number of echos to send\n");
+      return -1;
+   }
+   if (activehost == 0L)
+   {
+      ns_printf(pio,"IP host to echo to must be set with \"host\" command\n");
+      return -1;
+   }
+
+   /* send echo - this prints it's own errors */
+   udp_sendecho(pio,activehost, deflength, times);
+
+   return 0;
+}
+#endif   /* UDPSTEST */
+
+#ifdef TCP_ECHOTEST
+
+/* FUNCTION: tcpecho()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int tcpecho(void * pio)
+{
+   long  times =  1;
+   char *   arg2;
+
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);  /* get iteration arg from cmd line */
+   if (arg2 && *arg2)
+      times = atol(arg2);
+
+   if (times < 1)
+   {
+      ns_printf(pio,"command line arg must be number of echos to send\n");
+      return -1;
+   }
+   if (activehost == 0L)
+   {
+      ns_printf(pio,"IP host to echo to must be set with \"host\" command\n");
+      return -1;
+   }
+
+   /* send echo - this prints it's own errors */
+   tcp_sendecho(pio,activehost, (long)deflength, times);
+
+   return 0;
+}
+#endif   /* TCP_ECHOTEST */
+
+#ifdef IP_ROUTING
+
+char *   route_prots[] =
+{
+   "foo",
+   "OTHER",
+   "LOCAL",
+   "NETMGT",
+   "ICMP",
+   "EGP",
+   "GGP",
+   "HELLO",
+   "RIP",
+};
+
+
+#ifdef BTREE_ROUTES
+
+/* FUNCTION: btree_routes()
+ * 
+ * Helper function for displaying routes in the binary tree. A pointer to
+ * this is passed to avldepthfirst();
+ *
+ * PARAM1: current RtMib
+ * PARAM2: pointer to pio
+ * PARAM3: depth in tree
+ *
+ * RETURNS: 
+ */
+
+static int brtcount;
+
+void
+btree_routes(struct avl_node * node, long param, int depth)
+{
+   struct RtMib * rtp = (struct RtMib *)node;
+   void * pio = (void*)param;
+
+   if (!rtp->ipRouteNextHop)  /* empty slot */
+      return;
+
+   brtcount++;
+
+   /* if this is first entry then display heading */
+   if(brtcount == 1)
+      ns_printf(pio,"..IPaddr.......mask.........nexthop...iface..type\n");
+
+   while(depth--)
+      ns_printf(pio, " ");
+
+   ns_printf(pio,"%u.%u.%u.%u  %u.%u.%u.%u  %u.%u.%u.%u  %d   %s\n",
+      PUSH_IPADDR(rtp->ipRouteDest),
+      PUSH_IPADDR(rtp->ipRouteMask),
+      PUSH_IPADDR(rtp->ipRouteNextHop),
+      (int)rtp->ipRouteIfIndex,
+      route_prots[(int)rtp->ipRouteProto]);
+}
+#endif   /* BTREE_ROUTES */
+
+
+/* FUNCTION: show_routes()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int 
+show_routes(void * pio)
+{
+   int   rtcount  =  0;
+
+#ifdef BTREE_ROUTES
+   brtcount = 0;
+   avldepthfirst((struct avl_node *)btreeRoot, btree_routes, (long)pio, 0);
+   rtcount = brtcount;
+#else /* not BTREE_ROUTES */
+   RTMIB rtp;
+
+   if(!rt_mib)    /* system not fully up yet */
+      return -1;
+
+   for (rtp = rt_mib; rtp < rt_mib + ipRoutes; rtp++)
+   {
+      if (!rtp->ipRouteNextHop)  /* empty slot */
+         continue;
+
+      rtcount++;
+      if (rtcount == 1)
+         ns_printf(pio,"..IPaddr.......mask.........nexthop...iface..type\n");
+      ns_printf(pio,"%u.%u.%u.%u  %u.%u.%u.%u  %u.%u.%u.%u  %d   %s\n",
+       PUSH_IPADDR(rtp->ipRouteDest),
+       PUSH_IPADDR(rtp->ipRouteMask),
+       PUSH_IPADDR(rtp->ipRouteNextHop),
+       (int)rtp->ipRouteIfIndex,
+       route_prots[(int)rtp->ipRouteProto]);
+   }
+#endif   /* BTREE_ROUTES */
+
+   if (rtcount == 0)
+      ns_printf(pio,"no IP routes set\n");
+
+   return 0;
+}
+
+
+/* FUNCTION: mn_add_route()
+ *
+ * menu routine to manually add a route. format is target.ip 
+ * target.mask next.hop iface. 
+ *
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int mn_add_route(void * pio)
+{
+   char *   cp;      /* text for interface index */
+   int      ifindex; /* value of interface index */
+   unsigned snbits;
+   int      i;
+   char *   errmsg;
+   RTMIB    rtp;
+   NET      ifp;
+   struct ip_args
+   {  /* for reading in IP addresses from console buf */
+      char *   text;
+      ip_addr  ipaddr;
+   }  ipargs[4];
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* start of command line args */
+   for (i = 0; i <= 3; i++)   /* read in 4 args */
+   {
+      ipargs[i].text = cp;
+
+      if (i == 3) /* last arg is not an IP address, so we're done */
+         break;
+
+      /* null terminate IP address arg */
+      cp = strchr(ipargs[i].text, ' ');
+      if (cp)
+      {
+         *cp++ = '\0';  /* terminate this arg */
+         while (*cp == ' ')cp++; /* find next arg */
+            }
+      else  /* no space after arg == bogus command line */
+      {
+         ns_printf(pio,"usage: target.ip target.mask next.hop iface \n");
+         ns_printf(pio," where 1st 3 parms are in IP dot notation, last is digit 1-%d\n",
+          ifNumber);
+         return -1;
+      }
+      /* call parse_ipad to fill in IP address from text */
+      errmsg = parse_ipad(&ipargs[i].ipaddr, &snbits, ipargs[i].text);
+      if (errmsg)
+      {
+         ns_printf(pio,"bad IP format \"%s\" in arg %d, \n problem: %s\n", 
+          ipargs[i].text, i, errmsg);
+         return -1;
+      }
+   }
+
+   ifp = if_netbytext(pio, ipargs[i].text);
+   if (ifp == NULL)
+      return -1;
+   else
+      ifindex = if_netnumber(ifp);
+   
+   rtp = add_route(ipargs[0].ipaddr, ipargs[1].ipaddr, ipargs[2].ipaddr,
+      ifindex, IPRP_LOCAL);
+
+   if (!rtp)
+   {
+      ns_printf(pio,"add_route failed, table full?\n");
+      return -1;
+   }
+   return 0;
+}
+
+#endif   /* IP_ROUTING */
+
+#ifdef DNS_CLIENT_UPDT  
+/* FUNCTION: setupdns()
+ *
+ * Allows console user to set the IP address of the server to be used for 
+ * dynamic update.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+setupdns(void * pio)
+{
+   char *   cp;
+   char *   iptext;
+   unsigned int snbits;
+   
+   iptext = nextarg(((GEN_IO)pio)->inbuf);    /* see if user put addr on cmd line */
+   if (!*iptext)
+   {
+      ns_printf(pio, "usage: setupdns X.X.X.X\n");
+      return -1;
+   }
+
+   for (cp = iptext; *cp > ' '; cp++)  /* find end of IP text */
+      ;
+
+   *cp = 0;    /* null terminate iptext */ 
+   cp = parse_ipad(&dns_update_server, &snbits, iptext);
+   if (cp)
+   {
+      ns_printf(pio, "IP address error: %s\n", cp);
+      return -1;
+   }
+
+   ns_printf(pio, "DNS dynamic update server is set to %s \n", iptext);
+}
+#endif /* DNS_CLIENT_UPDT */
+
+
+/* FUNCTION: set_ipaddr()
+ *
+ * Allows console user to set an IP address of an interface on the fly. Usefull
+ * for testing, but dangerous in field.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+set_ipaddr(void * pio)
+{
+   char *   cp;
+   char *   iptext;
+   ip_addr  ipaddr;
+   ip_addr  mask;
+   unsigned int snbits;
+   struct net * ifp;
+   int      iface = 0;
+
+   ns_printf(pio, "WARNING: 'setip' will kill all current net connections!!!!\n");
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* see if user put addr on cmd line */
+   if (!*cp)
+   {
+      ns_printf(pio, "usage: setip X.X.X.X [iface (name or 1-n)]\n");
+      return -1;
+   }
+   iptext = cp;   /* save pointer to IP spec */
+
+   cp = nextarg(cp); /* see if user specified interface number */
+   if (*cp)
+   {
+      ifp = if_netbytext(pio, cp);
+      if(ifp == NULL)
+         return -1;
+      iface = if_netnumber(ifp);
+   }
+   else  /* no iface number given, default to first static */
+   {
+      ifp = nets[0];
+   }
+
+   for (cp = iptext; *cp > ' '; cp++)  /* find end of IP text */
+      ;
+
+   *cp = 0;    /* null terminate iptext */ 
+   cp = parse_ipad(&ipaddr, &snbits, iptext);
+   if (cp)
+   {
+      ns_printf(pio, "IP address error: %s\n", cp);
+      return -1;
+   }
+
+   ns_printf(pio, "replacing net %s IP address ", ifp->name);
+   ns_printf(pio, "%u.%u.%u.%u", PUSH_IPADDR(ifp->n_ipaddr) );
+
+   /* replace IP adress in nets[] structure */
+   ifp->n_ipaddr = ipaddr;
+
+   /* make default subnet mask */
+   mask = (ip_addr) ~0;    /* all 1s */
+   while (snbits--)
+      mask = mask >> 1;
+
+   ifp->snmask = htonl(~mask);
+
+   ns_printf(pio, " with %u.%u.%u.%u in RAM variables\n", 
+    PUSH_IPADDR(ifp->n_ipaddr) );
+
+#ifdef INCLUDE_NVPARMS
+   inet_nvparms.ifs[iface].ipaddr = ipaddr;
+   inet_nvparms.ifs[iface].subnet = htonl(~mask);
+
+   ns_printf(pio, "Use \"nvset\" to back up to flash or disk\n");
+#else
+   USE_ARG(iface);
+#endif
+
+#ifdef NATRT
+   nat_re_init();    /* refresh NAT router's parameters */
+#endif
+
+   return 0;
+}
+
+#ifdef DNS_CLIENT
+
+#ifdef IP_V6
+
+/* FUNCTION: gethost2test()
+ *
+ * Resolve a host name to IP address via a call to gethostbyname2()
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int
+gethost2test(void * pio)
+{
+   char *   cp;
+   struct hostent *  p;
+
+   /* see if user put name on cmd line */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+   if (!cp || !*cp)
+   {
+      ns_printf(pio, "usage: ns2lookup host_name\n");
+      return -1;
+   }
+
+   /* call gethostbyname() to resolve the passed name */
+   p = gethostbyname2(cp, AF_INET6);
+
+   if (!p)
+   {
+      ns_printf(pio,"gethostbyname2() returned NULL\n");
+      return 0;
+   }
+
+   ns_printf(pio,"gethostbyname2() succeeded\n");
+   ns_printf(pio," h_name is %s\n",p->h_name ? p->h_name : "NULL");
+
+   ns_printf(pio," h_addrtype = %d\n",p->h_addrtype);
+   ns_printf(pio," h_length = %d\n",p->h_length);
+   ns_printf(pio," h_addr_list are\n");
+   if (!(p->h_addr_list))
+      ns_printf(pio,"\tno addresses\n");
+   else
+   {
+      char ** cpp;
+      for(cpp = p->h_addr_list; *cpp; cpp++)
+      {
+         char ip6buf[40];     /* tmp buffer for ipv6 address text */
+         ns_printf(pio,"\t%s\n",  print_ip6((struct in6_addr *)(*cpp), ip6buf));
+      }
+   }
+
+   return 0;
+}
+#endif   /* IP_V6 */
+
+/* FUNCTION: gethostbynametest()
+ *
+ * Resolve a host name to IP address via a call to gethostbyname()
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int
+gethostbynametest(void * pio)
+{
+   char *   cp;
+   struct hostent *  p;
+
+   /* see if user put name on cmd line */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+   if (!cp || !*cp)
+   {
+      ns_printf(pio, "usage: nslookup host_name\n");
+      return -1;
+   }
+
+   /* call gethostbyname() to resolve the passed name */
+   p = gethostbyname(cp);
+
+   if (!p)
+   {
+      ns_printf(pio,"gethostbyname() returned NULL\n");
+      return 0;
+   }
+
+   ns_printf(pio,"gethostbyname() succeeded\n");
+   ns_printf(pio,"h_name is %s\n",p->h_name ? p->h_name : "NULL");
+
+   ns_printf(pio,"h_addrtype = %d\n",p->h_addrtype);
+   ns_printf(pio,"h_length = %d\n",p->h_length);
+   ns_printf(pio,"h_addr_list are\n");
+   if (!(p->h_addr_list) || !(*p->h_addr_list))
+      ns_printf(pio,"\tno addresses\n");
+   else
+   {
+      char ** cpp;
+      u_char * ucp;
+
+      for(cpp = p->h_addr_list; *cpp; cpp++)
+      {
+         ucp = (unsigned char *) (*cpp);
+         ns_printf(pio,"\t%d.%d.%d.%d\n",
+          *ucp, *(ucp + 1), *(ucp + 2), *(ucp + 3));
+      }
+   }
+
+   return 0;
+}
+
+int
+nslookup_reverse(void * pio)
+{
+   int status = -1;
+   char *cp = NULL;
+   struct dns_querys * dns_entry = NULL;
+   /* see if user put name on cmd line */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+   if(!cp || !*cp)
+   {
+      ns_printf(pio, "usage: nslookupr domainname\n");
+   }
+   else
+   {
+      if(nslookup(cp, DNS_TYPE_PTR, &dns_entry))
+      {
+         ns_printf(pio,"nslookup() failed\n");
+      }
+      else
+      {
+         if(dns_entry)
+         {
+            ns_printf(pio,"%s    name = %s\n",dns_entry->dns_names, dns_entry->ptr_name);
+            status = 0;
+         }
+         else
+         {
+            ns_printf(pio,"nslookup() dns_entry is NULL\n");
+         }
+      }
+   }
+   return(status);
+}
+
+/* FUNCTION: setdnssvr()
+ * 
+ * Allows console user to set a DNS Server's IP address. Useful for testing 
+ * the DNS Client.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 on success, or an error code of -1.
+ */
+
+int setdnssvr(void * pio)
+{
+   char * cp;
+   char * iptext;
+   unsigned int subnet;     /* dummy for passing to parse_ipad() */
+   int   svr_num;
+
+   cp = nextarg(((GEN_IO)pio)->inbuf);    /* see if user put addr on cmd line */
+   if (!*cp)
+   {
+      ns_printf(pio, "usage: setdnssvr X.X.X.X [Server No. (1-%d)]\n", MAXDNSSERVERS);
+      return -1;
+   }
+   iptext = cp;   /* save pointer to IP spec */
+
+   cp = nextarg(cp); /* see if user specified server number */
+   if (*cp)
+   {
+      svr_num = atoi(cp);
+      if (svr_num < 1 || svr_num > MAXDNSSERVERS)
+      {
+         ns_printf(pio, "DNS server number must be 1-%d\n", MAXDNSSERVERS);
+         return -1;
+      }
+   }
+   else  /* no server number given, default to first server */
+   {
+      svr_num = 1;
+   }
+
+   for (cp = iptext; *cp > ' '; cp++)  /* find end of IP text */
+      ;
+
+   *cp = 0;    /* null terminate iptext */ 
+
+   cp = parse_ipad(&dns_servers[svr_num-1], &subnet, iptext);
+
+   if (cp)
+   {
+      ns_printf(pio, "IP address error: %s\n", cp);
+      return -1;
+   }
+
+#ifdef INCLUDE_NVPARMS
+   MEMCPY(inet_nvparms.dns_servers, dns_servers, sizeof(dns_servers));
+   ns_printf(pio, "Use \"nvset\" to back up to flash or disk\n");
+#endif
+
+   return 0;
+}
+#ifdef DNS_CLIENT_UPDT
+
+/* FUNCTION: nsupdatetest()
+ * 
+ * Allows the user to add the ip address of a domain name using the
+ * Dynamic DNS update protocol as specified in rfc 2136.
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static int 
+nsupdatetest(void * pio)
+{
+   char *   cp;
+   char * ucp;
+   char dnbuf[1025];         /* buffer for domain name */
+   unsigned snbits;          /* output of parse_ipaddr- subnet value */
+   ip_addr ipout;            /* output of parse_ipaddr- ip address */
+   unsigned long r_ttl;
+   int p;                   /* Return code from sending update packet */
+   unsigned short del_flag = 0;
+
+   /* see if user put ADD on cmd line */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+ 
+   if (!strncmp(cp, "add",3) && (!strncmp(cp, "delete",6)))
+   {
+      ns_printf(pio,"usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+      ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+      return -1;
+   }
+   if (strncmp(cp, "delete",6) == 0)
+      del_flag = 1;
+
+   /* get next parameter.  This must be the domain name.*/
+   cp = nextarg(cp);
+   if (!*cp)
+   {
+      ns_printf(pio, "usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+      ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+      return -1;
+   }
+
+   strcpy(dnbuf,cp);
+   ucp = &dnbuf[0];
+   while (*ucp != ' ') ucp++;
+   *ucp = '\0';
+
+   /* If this is a delete operation, call dns_update with zero values for */
+   /* ttl and ip_addr                                                     */
+   if (del_flag == 1)
+   {
+      r_ttl = 0; /* ttl is 0 */
+      ipout = 0; /* ip address is 0 */
+
+      /* Final parameter is an ip address */
+      cp = nextarg(cp);
+      if (parse_ipad(&ipout, &snbits, cp))
+	  {
+         ns_printf(pio, "usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+         ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+         return -1;
+	  }
+
+      p = dns_update(soa_mname, dnbuf, ipout, r_ttl, pio);
+      if (p >= 0)
+         ns_printf(pio, "Update function returned the following response: %d\n",p);
+      else
+         ns_printf(pio, "Authoritative name server not found\n");
+      return 0;
+   }
+      
+   /* Next parameter must be ttl */
+   cp = nextarg(cp);
+   if (!(isdigit(*cp)))
+   {
+      ns_printf(pio, "usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+      ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+      return -1;
+   }
+   else
+      r_ttl = atol(cp);
+
+   /* Next parameter must be class- in this case an A */
+   cp = nextarg(cp);
+   if (*cp != 'A')
+   {
+      ns_printf(pio, "usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+      ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+      return -1;
+   }
+
+   /* Final parameter is an ip address */
+   cp = nextarg(cp);
+   if (parse_ipad(&ipout, &snbits, cp))
+   {
+      ns_printf(pio, "usage: nsupdate add <domain name> <ttl> A <ip addr>\n");
+      ns_printf(pio,"usage: nsupdate delete <domain name>\n");
+      return -1;
+   }
+   p = dns_update(soa_mname, dnbuf, ipout, r_ttl, pio);
+   if (p >= 0)
+   {
+      ns_printf(pio, "Update function returned the following error: %d\n",p);
+   }
+   else
+      ns_printf(pio, "Authoritative name server not found\n");
+   return 0;
+}
+#endif   /* DNS_CLIENT_UPDT */
+#endif   /* DNS_CLIENT */
+
+#ifdef PING_APP
+/* FUNCTION: ping_setdelay()
+ *
+ * Set the default delay between successive ping requests.
+ * This value affects all sessions.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: -1 if 'delay' parameter is missing from command 
+ * line or if the string->numeric conversion failed; otherwise,
+ * return code from ping_set_parm ().
+ */
+
+int
+ping_setdelay(void * pio)
+{
+   u_long newdelay;
+   char * arg = nextarg(((GEN_IO)pio)->inbuf);
+   char * termp;
+
+   if (arg && (*arg))
+   {
+      newdelay = strtoul (arg, &termp, 10);
+      if ((*termp == '\0') && ((*arg) != '-'))
+      {
+         ns_printf(pio,"Set inter-ping delay to %lu ms.\n", newdelay);
+         /* delay parameter is specified in number of ticks */
+         return (ping_set_parm (PARM_TYPE_DELAY, (newdelay/TIMEFOR1TICK)));
+      }
+      else
+      {
+         return -1;
+      }
+   }
+
+   return -1;
+}
+
+/* FUNCTION: ping_setlength()
+ *
+ * Set the default value of length of ping packets.
+ * This value affects all sessions.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: -1 if 'length' parameter is missing from command 
+ * line or if the string->numeric conversion failed; otherwise,
+ * return code from ping_set_parm ().
+ */
+
+int
+ping_setlength(void * pio)    /* menu routine to set default ping size */
+{
+   u_long newlen;
+   char * arg = nextarg(((GEN_IO)pio)->inbuf);
+   char * termp;
+
+   if (arg && (*arg))
+   {
+      newlen = strtoul (arg, &termp, 10);
+      if ((*termp == '\0') && ((*arg) != '-'))
+      {
+         ns_printf(pio,"Set ping length to %lu bytes.\n", newlen); 
+         return (ping_set_parm (PARM_TYPE_LENGTH, newlen));
+      }
+      else
+      {
+         return -1;
+      }
+   }
+
+   return -1;
+}
+
+/* FUNCTION: ping_sethost()
+ * 
+ * Set the default host to be pinged.
+ * This value affects all sessions.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: Return code from in_reshost () (if it returns an
+ * error), or the return code from ping_set_parm () (if 
+ * in_reshost () succeeded), or -1 if 'host' parameter is missing 
+ * from command line.
+ */
+
+int
+ping_sethost(void * pio)   /* set default host for pings, et.al. */
+{
+   int e;
+   char * arg =  nextarg(((GEN_IO)pio)->inbuf);
+   ip_addr newhost;
+
+   if (arg && (*arg))
+   {
+      e = in_reshost(arg, &newhost, RH_VERBOSE | RH_BLOCK);
+      if (!e)
+      {
+         printf ("Set ping host to %u.%u.%u.%u.\n", PUSH_IPADDR (newhost));
+         return (ping_set_parm (PARM_TYPE_HOST, ((u_long) newhost)));
+      }
+      else
+      {
+         return e;
+      }
+   }
+
+   return -1; 
+}
+#endif /* PING_APP */
+
+#ifdef   MINI_PING
+int
+mini_ping(void * pio)
+{
+   int err;
+
+   if(!activehost)
+   {
+      ns_printf(pio,"set host first\n");
+      return 1;
+   }
+
+   err = icmpEcho(activehost, NULL, deflength, 88);
+   if(err == 0)
+      ns_printf(pio,"ping sent, check icmp for reply\n");
+   else
+      ns_printf(pio,"ping send error %d\n", err);
+
+   return err;   
+}
+#endif   /* MINI_PING */
+
+/* FUNCTION: set_cdelay()
+ *
+ * Set the common default delay.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: -1 if 'delay' parameter is missing from command 
+ * line or if the string->numeric conversion failed; otherwise,
+ * this function returns SUCCESS.
+ */
+
+int
+set_cdelay(void * pio)
+{
+   u_long newdelay;
+   char * arg = nextarg(((GEN_IO)pio)->inbuf);
+   char * termp;
+
+   if (arg && (*arg))
+   {
+      newdelay = strtoul (arg, &termp, 10);
+      if ((*termp == '\0') && ((*arg) != '-'))
+      {
+         ns_printf(pio,"Set common delay parameter to %lu ms.\n", newdelay);
+         pingdelay = newdelay/TIMEFOR1TICK;
+         return SUCCESS;
+      }
+      else
+      {
+         return -1;
+      }
+   }
+
+   return -1;
+}
+
+/* FUNCTION: set_clength()
+ *
+ * Set the common length parameter.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: -1 if 'length' parameter is missing from command 
+ * line or if the string->numeric conversion failed; otherwise,
+ * this function returns SUCCESS.
+ */
+
+int
+set_clength(void * pio)    /* menu routine to set default ping size */
+{
+   u_long newlen;
+   char * arg = nextarg(((GEN_IO)pio)->inbuf);
+   char * termp;
+
+   if (arg && (*arg))
+   {
+      newlen = strtoul (arg, &termp, 10);
+      if ((*termp == '\0') && ((*arg) != '-'))
+      {
+         ns_printf(pio,"Set common length parameter to %lu bytes.\n", newlen); 
+         deflength = newlen;
+         return SUCCESS;
+      }
+      else
+      {
+         return -1;
+      }
+   }
+
+   return -1;
+}
+
+/* FUNCTION: set_chost()
+ * 
+ * Set the common host parameter.
+ *
+ * PARAM1: GEN_IO pio - device for console output
+ *
+ * RETURNS: -1 if 'host' parameter is missing from command 
+ * line, or return code from in_reshost () (if it returns an
+ * error), or SUCCESS (0).
+ */
+
+int
+set_chost(void * pio)   /* set default host for pings, et.al. */
+{
+   int   e;
+   char * arg =  nextarg(((GEN_IO)pio)->inbuf);
+   ip_addr newhost;
+
+   if (arg && (*arg))
+   {
+      e = in_reshost(arg, &newhost, RH_VERBOSE | RH_BLOCK);
+      if (!e)
+      {
+         printf ("Set common host parameter to %u.%u.%u.%u.\n", PUSH_IPADDR (newhost));
+         activehost = newhost;
+         return SUCCESS;
+      }
+      else
+      {
+         return e;
+      }
+   }
+
+   return -1;
+}
+
+#ifdef CHANGE_PWD /* allow user to change password */
+
+/* FUNCTION: get1ch()
+ * 
+ * Get 1 char from input device of pio.
+ *
+ * PARAM1: void * vio - device for console input/output
+ *
+ * RETURNS: received char, else -1.
+ */
+
+#include "userpass.h"
+
+int get1ch(void *vio)
+{
+   int ch=-1;
+   GEN_IO pio = (GEN_IO)vio;  /* convert void* to our IO device type */
+
+   if ( pio && pio->getch )   /*if i/p func is supplied*/
+   {
+      do 
+      {
+         ch = (pio->getch)(pio->id);
+         if ( ch == 0 )
+            tk_yield();    /* Give timeslice to other processes */
+      } while ( ch == 0 ) ;
+   }
+   return ch;
+}
+
+/* FUNCTION: change_pwd()
+ * 
+ * Change the password of a user.
+ *
+ * PARAM1: void * vio - device for console input/output
+ *
+ * RETURNS: 0 on success, else -1.
+ */
+
+int
+change_pwd(void * pio)
+{
+   char * user;
+   char * cp =  nextarg(((GEN_IO)pio)->inbuf);
+   char oldpwd[MAX_USERLENGTH];
+   char newpwd[MAX_USERLENGTH];
+   int i;
+   int ch;
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio,"Error - User name not specfied\n");
+      ns_printf(pio,"Usage: changepwd <username>\n");
+      return -1;
+   }
+
+   user = cp; /* point to start of user name */
+   while ((*cp != ' ') && (*cp != '\n') && (*cp != '\r') && (*cp != '\t'))
+      cp++;
+   *cp = 0; /* null terminate user name */
+
+   /* get the current password */
+   ns_printf(pio,"Enter old password> ");
+   i=0;
+   do
+   {
+      ch = get1ch(pio);
+      if ((ch != ' ') && (ch != '\n') && (ch != '\r') && (ch != '\t'))
+      {
+         oldpwd[i++] = ch;
+         ns_printf(pio,"*");
+      }
+      else
+      {
+         oldpwd[i]=0; /* overwrite linefeed with null, to null-terminate */
+         ns_printf(pio,"\n");
+         break;
+      }
+   } while (ch != -1);
+
+   ns_printf(pio,"Enter new password> ");
+   i=0;
+   do
+   {
+      ch = get1ch(pio);
+      if ((ch != ' ') && (ch != '\n') && (ch != '\r') && (ch != '\t'))
+      {
+         newpwd[i++] = ch;
+         ns_printf(pio,"*");
+      }
+      else
+      {
+         newpwd[i]=0; /* overwrite linefeed with null, to null-terminate */
+         ns_printf(pio,"\n");
+         break;
+      }
+   } while (ch != -1);
+
+   if (add_user(user,oldpwd,newpwd) == TRUE)
+      ns_printf(pio,"Password successfully changed.\n");
+   else
+   {
+      ns_printf(pio,"Error - couldn't change password.\n");
+      return -1;
+   }
+
+   return 0;
+}
+#endif /* CHANGE_PWD */
+
+#endif   /* IN_MENUS */
+
+
+
+/* FUNCTION: ishexdigit()
+ *
+ * some hex digit manipulation routines:
+ * 
+ * PARAM1: char digit
+ *
+ * RETURNS: 
+ */
+
+int   /* boolean */
+ishexdigit(char digit)  /* return TRUE is char is hex digit */
+{
+   if (isdigit(digit))
+      return TRUE;
+
+   digit |= 0x20;       /* mask letters to lowercase */
+   if ((digit >= 'a') && (digit <= 'f'))
+      return TRUE;
+   else
+      return FALSE;
+}
+
+
+
+/* FUNCTION: hexnibble()
+ * 
+ * PARAM1: char digit
+ *
+ * RETURNS: 
+ */
+
+unsigned hexnibble(char digit)
+{
+   if (digit <= '9')
+      return (digit-'0'    );
+
+   digit &= ~0x20;   /* letter make uppercase */
+   return (digit-'A')+10 ;
+}
+
+
+
+/* FUNCTION: atoh()
+ *
+ * atoh() - convert hex ascii string to unsigned. number may be preceeded
+ * by whitspace or "0x". Halts at first non hex digit character.
+ *
+ * 
+ * PARAM1: char * buf
+ *
+ * RETURNS: 
+ */
+
+unsigned
+atoh(char * buf)
+{
+   unsigned retval = 0;
+   char *   cp;
+   char  digit;
+
+   cp = buf;
+
+   /* skip past spaces and tabs */
+   while (*cp == ' ' || *cp == 9)
+      cp++;
+
+   /* while we see digits and the optional 'x' */
+   while (ishexdigit(digit = *cp++) || (digit == 'x'))
+   {
+      /* its questionable what we should do with input like '1x234', 
+       * or for that matter '1x2x3', what this does is ignore all 
+       */
+      if (digit == 'x')
+         retval = 0;
+      else
+         retval = (retval << 4) + hexnibble(digit);
+   }
+
+   return retval;
+}
+
+
+/* FUNCTION: atohl()
+ *
+ * atohl() - same as atoh() above, except returns a long
+ * 
+ * PARAM1: char * buf
+ *
+ * RETURNS: 
+ */
+
+unsigned long
+atohl(char * buf)
+{
+   unsigned long retval = 0;
+   char *   cp;
+   char  digit;
+
+   cp = buf;
+
+   /* skip past spaces and tabs */
+   while (*cp == ' ' || *cp == 9)
+      cp++;
+
+   /* while we see digits and the optional 'x' */
+   while (ishexdigit(digit = *cp++) || (digit == 'x'))
+   {
+      /* its questionable what we should do with input like '1x234', 
+       * or for that matter '1x2x3', what this does is ignore all 
+       */
+      if (digit == 'x')
+         retval = 0;
+      else
+         retval = (retval << 4) + hexnibble(digit);
+   }
+
+   return retval;
+}
+
+
+/* FUNCTION: hex2bin()
+ *
+ * hex2bin() - convert hexadecimal text into binary. Returns 0 if OK 
+ * else error code in invalid hex char encountered in input string. 
+ *
+ * 
+ * PARAM1: char * inbuf
+ * PARAM2: unsigned char * outbuf
+ * PARAM3: int bcount
+ *
+ * RETURNS: 
+ */
+
+int
+hex2bin(char * inbuf, unsigned char * outbuf, int bcount)
+{
+   int   i;
+   char *   cp =  inbuf;
+
+   for (i = 0; i < bcount; i++)
+   {
+      if (ishexdigit(*cp))
+         outbuf[i] = (unsigned char)(hexnibble(*cp) << 4);
+      else
+         return -1;
+      cp++;
+      if (ishexdigit(*cp))
+         outbuf[i] |= (unsigned char)hexnibble(*cp);
+      else
+         return -1;
+      cp++;
+   }
+   return 0;
+}
+
+
+/* 
+ * Altera Niche Stack Nios port modification:
+ * Wrap these routines with IN_MENUS so that they only
+ * build if the globals above they depend on (also wrapped with
+ * IN_MENUS) build
+ */
+#ifdef IN_MENUS
+
+#ifdef PING_APP   /* only if app ping is there  */
+#include "app_ping.h"
+
+int ping_process_ping_parm (u_long, u_long);
+struct ping_err ping_err;
+
+
+/* FUNCTION: ping_set_parm
+ * 
+ * This function sets the destination host, delay, and length fields for
+ * subsequent ping requests.
+ * 
+ * INPUT: (1) Type of parameter being sent (e.g., PARM_TYPE_HOST)
+ *        (2) Value for parameter being sent
+ *
+ * OUTPUT: Return code from ping_process_ping_parm () for non-OS_PREEMPTIVE
+ *         environments; 0 if successful and PING_ST_ALLOC_ERR if 
+ *         couldn't allocate memory for message to PING client task
+ *         (for multitasking environments).
+ */
+ 
+int ping_set_parm (u_long parm_type, u_long value)
+{
+#ifdef OS_PREEMPTIVE
+   struct pingtask_msg * msgp;
+
+   msgp = (struct pingtask_msg *) PING_ALLOC (sizeof (struct pingtask_msg));
+   if (!msgp)
+   {
+      ++ping_err.alloc_fail;
+      return PING_ST_ALLOC_ERR;
+   }
+   
+   /* send message to PING client task */
+   msgp->type = PING_CNTRL_SET_PARM;
+   msgp->parm1 = parm_type;
+   msgp->parm2 = value;
+
+   LOCK_NET_RESOURCE (PINGQ_RESID);
+   putq(&pingRcvq, (q_elt)msgp);
+   UNLOCK_NET_RESOURCE (PINGQ_RESID);
+
+   post_app_sem (PING_SEMID);
+#else
+   return (ping_process_ping_parm (parm_type, value));
+#endif   
+
+   return 0;
+}
+
+
+/* FUNCTION: ping_process_ping_parm
+ * 
+ * This function sets the destination host, delay, and length fields for
+ * subsequent ping requests.
+ * 
+ * INPUT: (1) Type of parameter being sent (e.g., PARM_TYPE_HOST)
+ *        (2) Value for parameter being sent
+ *
+ * OUTPUT: 0 if successful, or PING_ST_BAD_ARG2 if an unrecognized type
+ *         is encountered.
+ */
+
+int ping_process_ping_parm (u_long type, u_long value)
+{
+   switch (type)
+   {
+      case PARM_TYPE_HOST:
+         activehost = (ip_addr) value;
+         break;
+      case PARM_TYPE_DELAY:
+         pingdelay = value;
+         break;
+      case PARM_TYPE_LENGTH:
+         deflength = value;
+         break;
+      default:
+         ++ping_err.bad_parmtype;
+         return PING_ST_BAD_ARG2;
+   }
+
+   return 0;
+}
+
+#endif  /* PING_APP */
+
+#endif /* Altera modification: IN_MENUS */
+
+/* end of file nrmenus.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvfsio.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvfsio.c
new file mode 100644
index 0000000..3d74308
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvfsio.c
@@ -0,0 +1,329 @@
+/*
+ * FILENAME: nvfsio.c
+ *
+ * Copyright 1998-2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * This file contains the generic code to read a text file which contains
+ * a name/value list of non-volatile parameters.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: nv_fgets(), nv_fprintf(),
+ * ROUTINES: vfs_sync_open(), vfs_sync_close(), vfs_sync_read(), 
+ * ROUTINES: vfs_sync_write(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software  
+ * 2/7/98 - Created from routines in nvparms.c -JB- 
+ */
+
+
+#include "ipport.h"
+
+
+#ifdef NATIVE_PRINTF
+#include <stdarg.h>
+#include <stdio.h>
+#endif
+
+#include "libport.h"
+
+/* build these only if using NVPARMS */
+#ifdef INCLUDE_NVPARMS
+
+#define  _NVFSIO_C_  1
+
+#include "vfsfiles.h"
+#include "nvfsio.h"
+#include "nvparms.h"
+
+#ifndef HT_LOCALFS
+/* If there is no local file system, include code for NV parameters
+ * read (nv_fgets) and write (nv_fprintf) routines
+ */
+
+
+/* FUNCTION: nv_fgets()
+ *
+ * nv_fgets(char buf, unsigned maxlen, FILE fp) - fgets for reading a 
+ * line from a .nv file. This routine is provided for legacy code. 
+ * FILE parameter is cast as a void* to deal with compiler 
+ * crustiness. read data from the VFS file handle into the buffer 
+ * until: we read an end of file condition or any sort of line end 
+ * (CR or LF), or maxlen bytes of data have been read into the 
+ * buffer. 
+ *
+ * 
+ * PARAM1: char * buffer
+ * PARAM2: int maxlen
+ * PARAM3: NV_FILE * fd
+ *
+ * RETURNS: returns NULL if we encountered an EOF and no data were 
+ * read, otherwise returns address of buffer.
+ */
+
+char *   
+nv_fgets(char * buffer, int maxlen, NV_FILE * fd)
+{
+   int   bytes_read  =  0;
+   int   in_char;
+   int   read_eof =  FALSE;
+   char *   rc =  buffer;
+
+   while (TRUE)
+   {
+      /* terminate if we've read our maximum number of bytes */
+      /* leaving room for the newline and null at the end */
+      if (bytes_read >= (maxlen - 2))
+         break;
+      /* read a byte */
+      in_char = vgetc((VFILE*)fd);
+      /* terminate if EOF */
+      if (in_char < 0)
+      {
+         read_eof = TRUE;
+         break;
+      }
+      /* terminate if end of line */
+      if (in_char == 0xa)
+         break;
+      /* if we see a return, don't copy it since the code that calls
+         this appears to be expecting newline conversion to be done */
+      if (in_char == 0xd)
+         continue;
+      /* copy the read character into the buffer */
+      *(buffer + bytes_read) = (char) (in_char & 0xff);
+      ++bytes_read;
+   }
+   /* tack a newline on the end since the caller expects to see one */
+   *(buffer + bytes_read) = 0xa;
+   /* null terminate input */
+   *(buffer + bytes_read + 1) = 0;
+   /* if no bytes were read and we read an EOF character, return NULL */
+   if ((!bytes_read) && read_eof)
+      rc = (char *) 0;
+   return rc;
+}
+
+
+/* FUNCTION: nv_fprintf()
+ * 
+ * PARAM1: NV_FILE * fd
+ * PARAM2: char * format
+ * PARAM3: ...
+ *
+ * RETURNS: 
+ */
+
+#ifdef PRINTF_STDARG
+/* different nv_fprintf() functions depending on VA support */
+#include <stdarg.h>
+
+int
+nv_fprintf(NV_FILE * fd, char * format, 
+   ...)
+{
+   int   len,  err;
+   char  linebuf[NV_LINELENGTH];
+   va_list a;
+
+   va_start(a, format);
+   err = vsprintf(linebuf, format, a);
+   va_end(a);
+
+#else /* the non-STDARG version */
+
+int
+nv_fprintf(NV_FILE * fd, char * format, int arg1)
+{
+   int len, err;
+   char linebuf[NV_LINELENGTH];
+
+   doprint(linebuf, NV_LINELENGTH, format, &arg1);
+
+#endif   /* PRINTF_STDARG */
+
+   /* output string now in linebuf, rest of function is the same */
+
+   /* check for buffer overflow */
+   len = strlen(linebuf);
+   if (len > NV_LINELENGTH) panic("nv_fprintf");
+
+      /* write formatted buffer to VF device */
+   err = vfwrite(linebuf, len, 1, fd);
+   return err;
+}
+
+#endif   /* HT_LOCALFS */
+
+
+#ifdef   HT_SYNCDEV
+
+/* default routine to convert Linear address to seg/offset. This 
+ * default just handles the long to pointer cast and will work on 
+ * most 32 bit linear 
+ */
+
+#ifndef LinToSeg
+#define  LinToSeg(addr) ((void*)(addr))
+#endif
+
+/* this variable is used to keep track of the current location in flash
+ * where reads and writes are occuring. it contains the physical address
+ * of the location in flash and must be converted to a long pointer
+ * before being deferenced 
+ */
+unsigned long vfs_flash_address;
+
+/* FUNCTION: *vfs_sync_open()
+ *
+ * PARAM1: int clear
+ * PARAM2: int *p_error
+ *
+ * RETURNS: VFS file handle of open device, NULL if error.
+ */
+
+void *
+vfs_sync_open(int clear, int * p_error)
+{
+   unsigned short sector;
+   int   rc;
+
+   /* clear != 0 => clear backing store */
+   if (clear)
+   {
+      /* so erase the flash */
+      for (sector = VFS_BK_STORE_FIRST_SECTOR;
+          sector <= VFS_BK_STORE_LAST_SECTOR; ++sector)
+      {
+         rc = EraseFlash(sector);
+         if (rc != TRUE)
+         {
+            /* the AMD flash driver doesn't tell you why a failure
+               occured, so this is the best we can do */
+            *p_error = 1;
+            dprintf("EraseFlash(%d) failed\n",sector);
+            return NULL;
+         }
+      }
+   }
+
+   /* put the "file" pointer at the beginning of the flash backing store */
+   vfs_flash_address = VFS_BK_STORE_BASE_ADDRESS;
+
+   /* return the address of the file pointer */
+   return (void *) &vfs_flash_address;
+}
+
+
+
+/* FUNCTION: vfs_sync_close()
+ * 
+ * PARAM1: void *xfd
+ *
+ * RETURNS: 0
+ */
+
+int
+vfs_sync_close(void * xfd)
+{
+   /* more compiler warning suppression */
+   unsigned long *fd = xfd;
+
+   USE_ARG(fd);
+   /* this close can't fail, so return 0 */
+   return 0;
+}
+
+
+/* FUNCTION: vfs_sync_read()
+ *
+ * read len bytes of data into by buf from fd.
+ * 
+ * PARAM1: void *xfd
+ * PARAM2: void *buf
+ * PARAM3: unsigned int len
+ *
+ * RETURNS: 0 if successful or the non-zero reason for the error if not
+ */
+
+int
+vfs_sync_read(void * xfd, void * buf, unsigned int len)
+{
+   unsigned long *fd = xfd;
+
+   /* if caller is trying to read past end of backing store */
+   if ((*fd + len) >
+       (VFS_BK_STORE_BASE_ADDRESS + VFS_BK_STORE_SIZE))
+   {
+      dprintf("vfs_sync_read() tried to read 0x%x bytes at 0x%lx\n",
+       len,*fd);
+      vfs_sync_close(fd);
+      return 1;   /* its the only error that can occur */
+   }
+
+   /* copy the data in flash to the caller buffer */
+   MEMCPY(buf,LinToSeg(*fd),len);
+
+   /* increase the "file" pointer by the amount of data read */
+   *fd += len;
+   return 0;
+}
+
+
+/* FUNCTION: vfs_sync_write()
+ * 
+ * writes len bytes of data pointed to by buf to fd.
+ *
+ * PARAM1: void *xfd
+ * PARAM2: void *buf
+ * PARAM3: unsigned int len
+ *
+ * RETURNS: 0 if successful or the non-zero reason for the error if not
+ */
+
+ 
+int
+vfs_sync_write(void * xfd, void * buf, unsigned int len)
+{
+   unsigned int bytes_to_write;
+   unsigned long *fd = xfd;
+   int   rc;
+
+   /* if caller is trying to write past end of backing store */
+   if ((*fd + len) > (VFS_BK_STORE_BASE_ADDRESS + VFS_BK_STORE_SIZE))
+   {
+      dprintf("vfs_sync_write() tried to write 0x%x bytes at 0x%lx\n",
+       len,*fd);
+      vfs_sync_close(fd);
+      return 1;
+   }
+
+   /* while there's data left to write */
+   while (len)
+   {
+      /* chose a reasonable chunk to write at a time */
+      bytes_to_write =
+      (len > VFS_MAX_FILE_IO_SIZE) ? VFS_MAX_FILE_IO_SIZE : len;
+      /* write the chunk to the flash driver */
+      rc = ProgramFlash(*fd, buf, (int) bytes_to_write);
+      /* the flash driver returns TRUE when successful */
+      if (rc != TRUE)
+      {
+         dprintf("ProgramFlash(0x%lx,buf,0x%x) failed\n",*fd,len);
+         vfs_sync_close(fd);
+         return 2;
+      }
+      /* increase the "file pointer" by the amount written */
+      *fd += bytes_to_write;
+      /* decrease whats remaining to write by the amount written */
+      len -= bytes_to_write;
+   }
+   return 0;   /* success */
+}
+#endif   /* HT_SYNCDEV */
+
+#endif   /* INCLUDE_NVPARMS */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvparms.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvparms.c
new file mode 100644
index 0000000..7e3c158
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/nvparms.c
@@ -0,0 +1,1367 @@
+/*
+ * FILENAME: nvparms.c
+ *
+ * Copyright 1998- 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: get_file_parms(), get_nv_value(), get_nv_params(), 
+ * ROUTINES: get_nvif_nets(), get_nvipdec_nets(), get_nvbool_nets(), 
+ * ROUTINES: get_nvbool(), get_nvint(), get_nvunshort(), get_nvstring(), 
+ * ROUTINES: get_nvipdec(), get_nvdnssrv(), nv_bool(), set_nv_params(), 
+ * ROUTINES: inet_nvset(), comport_nvset(), install_nvformat(), 
+ * ROUTINES: edit_nv_params(), nv_get_sec_num(), nv_read_parse(), 
+ * ROUTINES: nv_add_entry(), nv_del_entry(),  nv_del_entry_byid(), 
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* nvparms.c 
+ * Portions Copyright 1996 by NetPort Software Code for a generic 
+ * Non-Volatile parameters system. For the basic demo, we assume nv 
+ * parms can just be written to a file. On an embedded system, this 
+ * probably needs to be replaced with code to write them to nvram or 
+ * flash. The following routines get/set the nvram data from a file 
+ * into the single global nv_parms structure. Programmers should read 
+ * NV data by calling get_nv_params() and then reading the data 
+ * itrems from the structure. Writing NV data is done by setting the 
+ * data in the structure and calling set_nv_params(), to ensure 
+ * backup to NV storage. Most routines silently return 0 if OK, else 
+ * print an error message to console and return -1. 
+ */
+
+#include "ipport.h"
+#include "libport.h"
+
+#ifdef   INCLUDE_NVPARMS   /* whole file can be ifdeffed out */
+
+#ifndef VFS_FILES
+#ifndef HT_LOCALFS
+#error Must have VFS to use NV parameters system
+#endif   /* HT_LOCALFS */
+#endif   /* VFS_FILES  */
+
+#include "vfsfiles.h"
+#include "nvparms.h"
+#include "ip.h"
+#include "in_utils.h"
+
+#include "nvfsio.h"
+
+#ifdef DNS_CLIENT
+#include "dns.h"
+#endif   /* DNS_CLIENT */
+
+#ifndef MINI_IP
+#include "nptcp.h"
+#include "socket.h"     /* for inet46_print_addr */
+#ifdef IP_V6
+#include "socket6.h"    /* for inet_pton */
+#endif
+#endif /* !MINI_IP */
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+#include "../ipmc/igmp_cmn.h"
+char * igmp_bld_err_str = "Build does not support requested IGMP protocol.\n";
+char * igmp_bad_prot_err_str = "Unknown IGMP protocol number.\n";
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ 
+
+char *   nvfilename  = "webport.nv";
+
+/* the IP stack's nvparm structure */
+struct inet_nvparam inet_nvparms;
+
+#ifdef USE_COMPORT
+struct comport_nvparam comport_nvparms;
+#endif   /* USE_COMPORT */
+
+void   nv_bool(char * string, int * boolptr);
+
+/* nvram (actually, file data) get functions */
+int get_nvif_nets(struct nvparm_info * nvinfo_ptr, char * parm);
+int get_nvipdec_nets(struct nvparm_info * nvinfo_ptr, char * parm);
+int get_nvbool_nets(struct nvparm_info * nvinfo_ptr, char* parm);
+int get_nvbool(struct nvparm_info * nvinfo_ptr, char* parm);
+int get_nvint(struct nvparm_info * nvinfo_ptr, char* parm);
+int get_nvunshort(struct nvparm_info * nvinfo_ptr, char* parm);
+int get_nvstring(struct nvparm_info * nvinfo_ptr, char* parm);
+int get_nvipdec(struct nvparm_info * nvinfo_ptr, char * parm);
+int get_nvipv6dec_nets(struct nvparm_info * nvinfo_ptr, char * parm);
+int get_nvip46dec(struct nvparm_info * nvinfo_ptr, char * parm);
+ 
+#ifdef DNS_CLIENT
+int get_nvdnssrv(struct nvparm_info * nvinfo_ptr, char * parm);
+#endif   /* DNS_CLIENT */
+
+/* Non-volatile parameters are read from a disk file and filled into 
+ * their runtime tables below. We do this with an array of "nvparm_info" 
+ * structures, where each entry has text for a single parameter name, 
+ * a parameter type, an optional bound, and a pointer to a variable to 
+ * store the parsed data. Each Module has an array of "nvparm_info" 
+ * structures which it keeps track of with the "nvparm_format" structure.
+ * The "nvparm_format" structure has a pointer to the array of "nvparm_info"'s
+ * a count for the size of the array, a pointer to a "set" routine to generate 
+ * and initialize a default NV file, and finally a pointer to the next module's
+ * "nvparm_format" structure. The get_file_parms() routine is called with the
+ * name of the file to parse and a pointer to an "nvparm_format" linked list. 
+ * It scans the file line by line, looks up the parameters in each module's
+ * "nvparm_format" structure's "nvparm_info" array, and calls the appropriate
+ * generic parse function to set the associated variable. 
+ */
+
+struct nvparm_info inet_nvformats[] = 
+{
+   {"   Net interface: %u\n",        NVIF_NETS,    NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+   /* first five iterate for MAXNETS number of nets */
+   {"IP address: %u.%u.%u.%u\n",     NVIPDEC_NETS, NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+   {"subnet mask: %u.%u.%u.%u\n",    NVSBDEC_NETS, NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+   {"gateway: %u.%u.%u.%u\n",        NVGTDEC_NETS, NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+   {"DHCP Client: %s\n",             NVBOOL_NETS,  NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   {"IGMP mode: %u\n",               NVCHAR_NETS,  NVBND_NOOP, \
+    &(inet_nvparms.ifs[0]), NULL},
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ 
+
+#ifdef DNS_CLIENT
+   /* hardcode number of DNS servers, should match MAXDNSSERVERS */
+   {"DNS server: 1 - %u.%u.%u.%u\n", NVDNSSRV,     NVBND_NOOP, \
+    &inet_nvparms.dns_servers[0], NULL, }, 
+   {"DNS server: 2 - %u.%u.%u.%u\n", NVDNSSRV,     NVBND_NOOP, \
+    &inet_nvparms.dns_servers[0], NULL, }, 
+   {"DNS server: 3 - %u.%u.%u.%u\n", NVDNSSRV,     NVBND_NOOP, \
+    &inet_nvparms.dns_servers[0], NULL, }, 
+#ifdef DNS_CLIENT_UPDT
+   {"DNS zone name: - %s\n",         NVSTRING,     MAX_NVSTRING, \
+    &inet_nvparms.dns_zone_name[0], NULL, },
+   {"DNS dynamic_update name: 1 - %u.%u.%u.%u\n",  NVDNSSRV,     NVBND_NOOP, \
+    &inet_nvparms.dns_update_server, NULL, },
+#endif   /* DNS_CLIENT_UPDT */
+#endif   /* DNS_CLIENT */
+#ifdef IP_V6
+   {"IPV6 address: %s\n",        NVIPV6DEC_NETS, NVBND_NOOP, \
+    &inet_nvparms.ifs[0], NULL, },
+#endif
+};
+
+#define NUMINET_FORMATS  \
+        (sizeof(inet_nvformats)/sizeof(struct nvparm_info))
+
+
+#ifdef USE_COMPORT
+/* Comport nvparms live here, since SLIP which lives in the .\net directory
+ * could be using the comport nvparms.
+ */
+struct nvparm_info comport_nvformats[] = 
+{
+   {"Comm port: %c\n"    , NVINT, NVBND_NOOP, &comport_nvparms.comport, NULL, },
+   {"line protocol: %s\n", NVINT, NVBND_NOOP, &comport_nvparms.LineProtocol, NULL, },
+};
+
+#define NUMCOMPORT_FORMATS  \
+        (sizeof(comport_nvformats)/sizeof(struct nvparm_info))
+
+#endif   /* USE_COMPORT */
+
+
+/* per-port routine to pre-initialize new NV parameters */
+void (*set_nv_defaults)(void) = NULL;
+
+#ifdef HT_SYNCDEV
+/* per-port routine to write nvfs image to flash part */
+void (*nv_writeflash)(void) = NULL;
+#endif
+
+char *   IPerr = "Bad IP address format in NV file line %d\nerror: %s\n";
+
+static int netidx = -1; /* index of nets[] to configure */
+
+static int line;      /* line number of input file currently being processed */
+
+
+char * get_nv_value(char *linebuf,struct nvparm_format *parmformat);
+
+int inet_nvset(NV_FILE * fp);
+
+#ifdef USE_COMPORT
+int comport_nvset(NV_FILE * fp);
+#endif   /* USE_COMPORT */
+
+#ifdef USE_COMPORT
+struct nvparm_format comport_format =
+{
+   NUMCOMPORT_FORMATS,
+   &comport_nvformats[0],
+   comport_nvset,
+   NULL,
+}; 
+#endif   /* USE_COMPORT */
+
+struct nvparm_format inet_format =
+{
+   NUMINET_FORMATS,
+   &inet_nvformats[0],
+   inet_nvset,
+#ifdef USE_COMPORT
+   &comport_format,
+#else
+   (struct nvparm_format *)NULL,
+#endif   /* USE_COMPORT */
+};
+
+struct nvparm_format *nv_formats = &inet_format;
+
+
+/* FUNCTION: get_file_parms()
+ *
+ * get_file_parms() - Open an InterNiche style parameters text file, 
+ * read it a line at a time, and call the set functions in the 
+ * descriptor array passed. Returns 0 if no error, else one of the 
+ * ENP_ errors. 
+ *
+ * 
+ * PARAM1: char * filename
+ * PARAM2: struct nvparm_info *parminfo
+ * PARAM3: int array_items
+ * PARAM4: int *readline
+ *
+ * RETURNS: 
+ */
+
+int
+get_file_parms(char * filename,       /* file to read (w/path) */
+   struct nvparm_format * parmformat, /* array of parmeter descriptors */
+   int * readline)                    /* count of lines read from file */
+{
+   char  linebuf[NV_LINELENGTH];      /* make sure you have a big stack */
+   NV_FILE * fp;                      /* file with nvram data */
+   int      retval = 0;               /* value to return from this function */
+   char *retstr=NULL;
+
+   fp = nv_fopen(filename, "r");
+   if (!fp)
+   {
+      printf("Unable to open NV Parameters file \"%s\"\n", filename);
+      return ENP_NOFILE;
+   }
+
+   *readline = 0;                     /* no parameters read yet */
+
+   /* the main file reading loop */
+   for ((*readline) = 1; ; (*readline)++)
+   {
+      if (nv_fgets(linebuf, NV_LINELENGTH, fp) != linebuf)
+      {
+         retval = 0;
+         break;
+      }
+
+      retstr=get_nv_value(linebuf,parmformat);
+
+      if (retstr)
+      {
+         printf("%s %d, file %s\n", retstr,*readline, filename);
+         printf("content: %s\n", linebuf);
+         printf("Try moving %s to another directory & re-run executable\n",
+          filename);
+         retval=ENP_PARAM;
+         break;
+      }
+   }
+   nv_fclose(fp);
+   return retval;
+}
+
+/* FUNCTION: get_nv_value()
+ *
+ * get_nv_value() - Process the line which contains information
+ * about the nvparm. General format is <str>: <value>
+ * From the <str>, identify the entry in parminfo,
+ * and call the set functions in the descriptor array passed. 
+ *
+ * 
+ * PARAM1: char *linebuf - line which is to be processed
+ * PARAM2: struct nvparm_info *parminfo
+ * PARAM3: int array_items
+ *
+ * RETURNS: Returns NULL if no error, else error string.
+ */
+
+char *
+get_nv_value(char *linebuf, struct nvparm_format *parmformat)   
+{
+   char *   colon_pos;  /* position of colon char ':' in input line */
+   char *   lf_pos;     /* position of linefeed in input line */
+   int j, err;
+   struct nvparm_info * curr_infoptr;
+
+   if (linebuf[0] == '\n' || linebuf[0] == '\r')   /* blank line */
+      return NULL; /* skip this line */
+   if (linebuf[0] == '#')  /* see if line is commented out */
+      return NULL; /* skip this line */
+   lf_pos = strchr(linebuf, '\n');     /* find possible linefeed */
+   if (lf_pos)       /* if linefeed exists, null it over */
+      *lf_pos = '\0';
+   lf_pos = strchr(linebuf, '\r');     /* find possible carriage-return */
+   if (lf_pos)       /* if carriage-return exists, null it over */
+      *lf_pos = '\0';
+   /* make sure line has a colon and sanity check colon position */
+   colon_pos = strchr(linebuf, ':');
+   if (colon_pos < &linebuf[5] || colon_pos > &linebuf[50])
+   {
+      return "get_nv_params: Missing or displaced colon in line";
+   }
+
+   /* search nvparm_format's to figure out which parameter it is */
+   while (parmformat && parmformat->info_ptr)
+   {
+      curr_infoptr = parmformat->info_ptr;
+
+      for (j = 0; j < parmformat->count; j++)
+      {
+         if (strncmp(linebuf, curr_infoptr->pattern, colon_pos-linebuf) == 0)
+         {
+            switch(curr_infoptr->nvtype)
+            {
+            case NVBOOL:
+               err = get_nvbool(curr_infoptr, colon_pos+2);
+               break;
+            case NVINT:
+               err = get_nvint(curr_infoptr, colon_pos+2);
+               break;
+            case NVUNSHORT:
+               err = get_nvunshort(curr_infoptr, colon_pos+2);
+               break;
+            case NVSTRING:
+               err = get_nvstring(curr_infoptr, colon_pos+2);
+               break;
+            case NVIPDEC:
+               err = get_nvipdec(curr_infoptr, colon_pos+2);
+               break;
+            case NVIP46DEC:
+               err = get_nvip46dec(curr_infoptr, colon_pos+2);
+               break;
+#ifdef DNS_CLIENT
+            case NVDNSSRV:
+               err = get_nvdnssrv(curr_infoptr, colon_pos+2);
+               break;
+#endif
+            case NVIF_NETS:
+               err = get_nvif_nets(curr_infoptr, colon_pos+2);
+               break;
+            case NVIPDEC_NETS:
+            case NVSBDEC_NETS:
+            case NVGTDEC_NETS:
+            case NVCHAR_NETS:
+               err = get_nvipdec_nets(curr_infoptr, colon_pos+2);
+               break;
+#ifdef IP_V6
+            case NVIPV6DEC_NETS:
+               err = get_nvipv6dec_nets(curr_infoptr, colon_pos+2);
+               break;
+#endif
+            case NVBOOL_NETS:
+               err = get_nvbool_nets(curr_infoptr, colon_pos+2);
+               break;
+            default:    /* proprietary nvtype or is it unknown nvtype ? */
+               if (curr_infoptr->nvtype >= 100 && curr_infoptr->nvtype <=200)
+               {
+                  if (curr_infoptr->get_nvprop_type)
+                  {
+                     err = curr_infoptr->get_nvprop_type(curr_infoptr, colon_pos+2);
+                  }
+                  else
+                  {
+                     printf("Expecting pointer to proprietary nvparm type ");
+                     printf("parse function.\n");
+                     printf("Please check configuration of the nvparm_info ");
+                     printf("for the pattern = %s\n", curr_infoptr->pattern);
+                     dtrap();
+                     err = 1;
+                  }
+               }
+               else
+               {
+                  dprintf("get_nv_value: unknown nvtype in nvparm_format %d\n", \
+                          curr_infoptr->nvtype );
+                  err = 1;
+               }
+               break;
+            }
+
+            if (err)
+               return "error setting value in line";
+            else
+               return NULL;
+         }
+         curr_infoptr++;
+      }
+      parmformat = parmformat->next_format;
+   }
+   return "Unknown NV parameter string or format in line" ;
+}
+
+/* FUNCTION: get_nv_params()
+ *
+ * get_nv_params() - Read BV params from file or flash into NV 
+ * streucture. This is usually called from main()/netmain() Returns: 
+ * silently return 0 if OK, else print an error message to console 
+ * and return -1. 
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+int
+get_nv_params()
+{
+   int   e;
+   NV_FILE * fp;
+
+   /* Just in case Demo Applications want to parse webport.nv again */
+   netidx = -1; /* reset index of nets[] to configure */
+
+   /* invoke the generic parm reader to get TCP/IP system parameters */
+   e = get_file_parms(nvfilename, nv_formats, &line);
+   if (e == ENP_NOFILE)
+   {
+      printf("Creating sample file\n");
+      fp = nv_fopen(nvfilename, "w+");
+      if (fp)
+      {
+         if (set_nv_defaults)   /* see if app wants to init defaults */
+            set_nv_defaults();
+         set_nv_params(NULL);   /* write defaults to new file */
+
+         /* now try again from the flash file we just set up */
+         e = get_file_parms(nvfilename, nv_formats, &line);
+      }
+      else
+         printf("Can't create sample file either.\n");
+   }
+   return(e);
+}
+
+
+
+
+/* FUNCTION: getnet()
+ *
+ * get_nvif_nets() - get number of next interface to set up
+ * 
+ * Networks in the .nv file can be indexed by ones based numbering, zero 
+ * based numbering, or names. On the first net we figure out which, then 
+ * enforce the system on the remaining nets.
+ *
+ * PARAM1: char * parm
+ * PARAM2: struct nvparm_info * nvinfo_ptr
+ *
+ * RETURNS: 0 if OK, else -1
+ */
+
+static enum { 
+   ZERO_BASED, ONES_BASED, NAME_BASED 
+} iftype = ZERO_BASED;     /* default... */
+
+int
+get_nvif_nets(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+   int   newnet;
+
+   if(netidx == -1)  /* first net in nv file */
+   {
+      /* see if net parameter is name or number */
+      if((*parm >= '0') && (*parm <= '9'))
+      {
+         /* see if first number is zero or one. */
+         if(*parm == '0')
+            iftype = ZERO_BASED;
+         else if(*parm == '1')
+            iftype = ONES_BASED;
+         else
+         {
+            printf("First Net number must be 0 or 1");
+            return -1;
+         }
+      }
+      else
+         iftype = NAME_BASED;
+   }
+
+   switch(iftype)
+   {
+   case ONES_BASED:
+      newnet = atoi(parm);
+      if (newnet < 1 || newnet > MAXNETS)
+      {
+         printf("Net numbers must be 1-%d", MAXNETS);
+         return -1;
+      }
+      newnet--;      /* convert to zero based C array index */
+      goto check_nextnet;
+   case ZERO_BASED:
+      newnet = atoi(parm);
+      if (newnet < 0 || newnet >= MAXNETS)
+      {
+         printf("Net numbers must be 0-%d", MAXNETS - 1 );
+         return -1;
+      }
+check_nextnet:
+      if (newnet != (netidx + 1))
+      {
+         printf("next net should be %d", netidx + 1);
+         return -1;
+      }
+      netidx = newnet;
+      /* set ones based index number as textual name */
+
+      *(((struct ifinfo *)(nvinfo_ptr->nvdata) + netidx)->name) = \
+      (char)('1' + netidx);   
+
+      break;
+   case NAME_BASED:
+      if(isdigit(*parm))
+      {
+         printf("Net must be all single digits or all names");
+         printf("which don't start with a digit\n");
+         return -1;
+      }
+      if(strlen(parm) >= IF_NAMELEN)
+      {
+         printf("interface names must be shorter than %d chars", IF_NAMELEN);
+         return -1;
+      }
+      netidx++;   /* bump index to next ifs entry */
+      /* copy in name */
+      strncpy(((struct ifinfo *)(nvinfo_ptr->nvdata) + netidx)->name, parm, \
+              IF_NAMELEN - 1);
+      break;
+   }
+   return 0;   /* OK return */
+}
+
+/* IP address options */
+
+
+/* FUNCTION: get_nvipdec_nets()
+ *
+ * getip - get Internet ip address for the NETS array
+ *
+ * 
+ * PARAM1: char * parm
+ *
+ * RETURNS: 
+ */
+
+int 
+get_nvipdec_nets(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+   char *   cp;
+   unsigned subnet;     /* dummy for passing to parse_ipad() */
+
+   switch(nvinfo_ptr->nvtype)
+   {
+   case NVIPDEC_NETS:
+      cp = parse_ipad((ip_addr *)&(((struct ifinfo *)(nvinfo_ptr->nvdata) + \
+                      netidx)->ipaddr), &subnet, parm);
+      break;
+   case NVSBDEC_NETS:
+      cp = parse_ipad((ip_addr *)&(((struct ifinfo *)(nvinfo_ptr->nvdata) + \
+                      netidx)->subnet), &subnet, parm);
+      break;
+   case NVGTDEC_NETS:
+      cp = parse_ipad((ip_addr *)&(((struct ifinfo *)(nvinfo_ptr->nvdata) + \
+                      netidx)->gateway), &subnet, parm);
+      break;
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+   case NVCHAR_NETS:
+      {
+      struct ifinfo * ifip;
+      u_char cval;
+
+      ifip = ((struct ifinfo *) (nvinfo_ptr->nvdata)) + netidx;
+      /* extract the IGMP operating mode (1 for v1, 2 for v2) from 
+       * configuration file */
+      cval = (u_char) atoi (parm);
+
+      switch (cval)
+      {
+      case IGMP_MODE_V1:
+#ifdef IGMP_V1
+         cp = 0;
+         ifip->igmp_oper_mode = cval;
+#else
+         /* return an error if the configuration file specifies
+          * support for IGMPv1, but the protocol is not compiled
+          * into the build.
+          */
+         cp = igmp_bld_err_str;
+#endif
+         break;
+      case IGMP_MODE_V2:
+#ifdef IGMP_V2
+         cp = 0;
+         ifip->igmp_oper_mode = cval;
+#else
+         /* return an error if the configuration file specifies
+          * support for IGMPv2, but the protocol is not compiled
+          * into the build.
+          */
+         cp = igmp_bld_err_str;
+#endif
+         break;
+      default:
+         /* indicate failure if mode is not one of the two expected 
+          * values (1 for IGMPv1, 2 for IGMPv2) */
+         cp = igmp_bad_prot_err_str;
+         break;
+      } /* end SWITCH */
+
+      if (!cp) 
+         printf ("interface: %s, cval: %u, netidx: %u\n", ifip->name, cval, netidx);
+      }
+      break;
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */ 
+   default:   /* Bad programming ? */
+      dprintf("get_nv_value: unknown nvtype in nvparm_format %d\n", \
+               nvinfo_ptr->nvtype );
+      return -1;
+   }
+
+   if (cp)
+   {
+      printf(IPerr, line, cp);
+      return -1;
+   }
+   return 0;
+}
+
+#ifdef IP_V6
+/* IPV6 address options */
+
+
+/* FUNCTION: get_nvipv6dec_nets()
+ *
+ * getip - get Internet ip address for the NETS array
+ *
+ * 
+ * PARAM1: char * parm
+ *
+ * RETURNS: 
+ */
+
+int 
+get_nvipv6dec_nets(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+   int stat;
+
+   switch(nvinfo_ptr->nvtype)
+   {
+
+   case NVIPV6DEC_NETS:
+      stat = inet_pton(AF_INET6, (const char *)parm, 
+                   (ip6_addr *)&((struct ifinfo *)(nvinfo_ptr->nvdata) + \
+                   netidx)->ipv6addr );
+      break;
+
+   default:   /* Bad programming ? */
+      dprintf("get_nv_value: unknown nvtype in nvparm_format %d\n", \
+               nvinfo_ptr->nvtype );
+      return -1;
+   }
+
+   if (stat)
+   {
+      printf(IPerr, line, parm);
+      return -1;
+   }
+   return 0;
+}
+
+#endif   /* IP_V6 */
+
+/* FUNCTION: get_nvbool_nets()
+ *
+ * Parse boolean parameters for the NETS Array.
+ *
+ * Right now we only use this to check if the DHCP client
+ * is enabled on the iface. Can be extended for other Nets
+ * boolean variables.
+ * 
+ * PARAM1: char* parm
+ *
+ * RETURNS:
+ */
+
+int
+get_nvbool_nets(struct nvparm_info * nvinfo_ptr, char* parm)
+{
+   nv_bool(parm, &(((struct ifinfo *)(nvinfo_ptr->nvdata) + \
+                   netidx)->client_dhcp));
+   return 0;
+}
+
+#ifdef DNS_CLIENT
+
+/* FUNCTION: get_nvdnssrv()
+ * 
+ * PARAM1: struct nvparm_info * nvinfo_ptr
+ * PARAM2: char * parm
+ *
+ * RETURNS: 
+ */
+
+int 
+get_nvdnssrv(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+   char *   cp;
+   unsigned subnet;     /* dummy for passing to parse_ipad() */
+   int   svr_num;
+
+   svr_num = atoi(parm);
+   if (svr_num < 1 || svr_num > MAXDNSSERVERS)
+   {
+      printf("Error in line %d; DNS server number must be 1-%d\n",
+       line, MAXDNSSERVERS);
+      return -1;
+   }
+   parm += 4;  /* point to IP address field */
+
+   cp = parse_ipad((ip_addr *)nvinfo_ptr->nvdata + (svr_num - 1), \
+                   &subnet, parm);
+
+   if (cp)
+   {
+      printf(IPerr, line, cp);
+      return -1;
+   }
+   return 0;
+}
+#endif   /* DNS_CLIENT */
+
+/* FUNCTION: get_nvbool()
+ *
+ * 
+ * PARAM1: char* parm
+ *
+ * RETURNS: 
+ */
+int
+get_nvbool(struct nvparm_info * nvinfo_ptr, char* parm)
+{
+   nv_bool(parm, (int *)(nvinfo_ptr->nvdata));
+   return 0;
+}
+
+
+/* FUNCTION: get_nvint()
+ * 
+ * PARAM1: char* parm
+ *
+ * RETURNS: 
+ */
+
+int
+get_nvint(struct nvparm_info * nvinfo_ptr, char* parm)
+{
+   *(int *)nvinfo_ptr->nvdata = (int)atoi(parm);
+   return 0;
+}
+
+
+/* FUNCTION: get_nvunshort()
+ * 
+ * PARAM1: char* parm
+ *
+ * RETURNS: 
+ */
+
+int
+get_nvunshort(struct nvparm_info * nvinfo_ptr, char* parm)
+{
+   *(unshort *)nvinfo_ptr->nvdata = (unshort)atoi(parm);
+   return 0;
+}
+
+/* FUNCTION: get_nvstring()
+ * 
+ * PARAM1: char* parm
+ *
+ * RETURNS: 
+ */
+
+int
+get_nvstring(struct nvparm_info * nvinfo_ptr, char* parm)
+{
+   strncpy((char *)(nvinfo_ptr->nvdata), parm, nvinfo_ptr->nvbound);
+   return 0;
+}
+
+
+/* FUNCTION: get_nvipdec()
+ *
+ * get_nvipdec - get Internet ip address
+ *
+ * 
+ * PARAM1: char * parm
+ *
+ * RETURNS: 
+ */
+int 
+get_nvipdec(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+   char *   cp;
+   unsigned subnet;   /* dummy for passing to parse_ipad() */
+
+   cp = parse_ipad((ip_addr *)(nvinfo_ptr->nvdata), &subnet, parm);
+   if (cp)
+   {
+      printf(IPerr, line, cp);
+      return -1;
+   }
+   return 0;
+}
+
+/* FUNCTION: get_nvip46dec()
+ *
+ * get_nvip46dec - get Internet IPv4/IPv6 address
+ * 
+ * PARAM1: char * parm
+ *
+ * RETURNS: 
+ */
+
+
+int 
+get_nvip46dec(struct nvparm_info * nvinfo_ptr, char * parm)
+{
+#ifndef MINI_IP
+   return inet46_addr(parm, (struct sockaddr *)nvinfo_ptr->nvdata);
+#else
+   return -1;
+#endif /* !MINI_IP */
+}
+
+
+/* FUNCTION: set_nv_params()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+set_nv_params(void * pio)
+{
+   NV_FILE * fp;        /* file with nvram data */
+   struct nvparm_format * curr_format = nv_formats;
+
+   fp = nv_fopen(nvfilename, "w");
+   if (!fp)
+   {
+      ns_printf(pio, "Unable to open NV Parameters file \"%s\"\n", nvfilename);
+      return -1;
+   }
+
+   while (curr_format)
+   {
+      curr_format->setfunc(fp);
+      curr_format = curr_format->next_format;
+   }
+
+   nv_fclose(fp);
+
+#ifdef HT_SYNCDEV
+   if (nv_writeflash)   /* make sure pointer is set */
+      nv_writeflash();  /* call optional per-port flash write routine */
+#endif
+
+   return 0;
+}
+
+/* FUNCTION: inet_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int inet_nvset(NV_FILE * fp)
+{
+int j=0;
+struct l2b ip;  /* structure for IP address conversions */
+int iface;      /* nets[] index */
+
+   /* fill in nvparms from set active values */
+
+   /* IP addressing parameters and IGMP mode section: */
+
+   for (iface = 0; iface < MAXNETS; iface++)
+   {
+      j = 0;    /* inet_nvformats element currently being witten */
+      nv_fprintf(fp, inet_nvformats[j++].pattern, iface);
+
+      ip.ip.iplong = inet_nvparms.ifs[iface].ipaddr;
+      nv_fprintf(fp, inet_nvformats[j++].pattern,  ip.ip.ipchar[0], 
+                 ip.ip.ipchar[1], ip.ip.ipchar[2], ip.ip.ipchar[3]);
+
+      ip.ip.iplong = inet_nvparms.ifs[iface].subnet;
+      nv_fprintf(fp, inet_nvformats[j++].pattern,  ip.ip.ipchar[0], 
+                 ip.ip.ipchar[1], ip.ip.ipchar[2], ip.ip.ipchar[3]);
+
+      ip.ip.iplong = inet_nvparms.ifs[iface].gateway;
+      nv_fprintf(fp, inet_nvformats[j++].pattern,  ip.ip.ipchar[0], 
+                 ip.ip.ipchar[1], ip.ip.ipchar[2], ip.ip.ipchar[3]);
+
+      nv_fprintf(fp, inet_nvformats[j++].pattern, 
+                 (inet_nvparms.ifs[iface].client_dhcp)?"YES":"NO");
+
+#if defined (IP_MULTICAST) && (defined (IGMP_V1) || defined (IGMP_V2))
+      nv_fprintf(fp, inet_nvformats[j++].pattern, 
+                 inet_nvparms.ifs[iface].igmp_oper_mode);
+#endif /* IP_MULTICAST and (IGMPv1 or IGMPv2) */
+   }
+
+#ifdef DNS_CLIENT
+   {
+      int   i;
+      for (i = 0; i < MAXDNSSERVERS; i++)
+      {
+         ip.ip.iplong = inet_nvparms.dns_servers[i];
+         nv_fprintf(fp, inet_nvformats[j++].pattern,  ip.ip.ipchar[0], 
+                    ip.ip.ipchar[1], ip.ip.ipchar[2], ip.ip.ipchar[3]);
+      }
+   }
+
+#ifdef DNS_CLIENT_UPDT
+   nv_fprintf(fp, inet_nvformats[j++].pattern, inet_nvparms.dns_zone_name);
+#endif   /* DNS_CLIENT_UPDT */
+
+#endif   /* DNS_CLIENT */
+
+   return 0;
+}
+
+#ifdef USE_COMPORT
+/* FUNCTION: comport_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int comport_nvset(NV_FILE * fp)
+{
+int i = 0;
+
+   if (comport_nvparms.comport != '1'  && comport_nvparms.comport !='2' )
+      comport_nvparms.comport='1';
+
+   nv_fprintf(fp, comport_nvformats[i++].pattern, comport_nvparms.comport);
+
+   nv_fprintf(fp, comport_nvformats[i++].pattern, 
+              (comport_nvparms.LineProtocol == PPP) ? "PPP":"SLIP");
+
+   return 0;
+}
+#endif   /* USE_COMPORT */
+
+/* FUNCTION: nv_bool()
+ *
+ * set a passed boolean variable from a passed string
+ * 
+ * PARAM1: char * string
+ * PARAM2: int * boolptr
+ *
+ * RETURNS: 
+ */
+
+void
+nv_bool(char * string, int * boolptr)
+{
+   if (stricmp(string, "yes") == 0)
+      *boolptr = TRUE;
+   else if(stricmp(string, "true") == 0)
+      *boolptr = TRUE;
+   else
+      *boolptr = FALSE;
+}
+
+/* FUNCTION: edit_nv_params()
+ * Edit the value of the param in the nvram structure.
+ * This function allows any (well almost) nvram parameter to be
+ * configured from the command prompt. 
+ * Usage:
+ *    nvedit <whole line as it appears in webport.nv file>
+ *    nvedit <str>: <value>
+ * Example:
+ *    nvedit PPP Console Logging: YES
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+extern   char *   nextarg(char*); /* get next arg from a string */
+
+int
+edit_nv_params(void * pio)
+{
+   char *retstr=NULL;
+   char *   cp;
+
+   /* see if user put name on cmd line */
+   cp = nextarg(((GEN_IO)pio)->inbuf);
+   if (!cp || !*cp)
+   {
+      ns_printf(pio, "usage: nvedit <name of variable>: <value>\n");
+      return -1;
+   }
+
+   retstr = get_nv_value(cp, nv_formats);
+   if (retstr)
+   {
+      ns_printf(pio, retstr);
+      return -1;
+   }
+
+   return 0;
+}
+
+/* FUNCTION: install_nvformat()
+ *
+ * install_nvformat() - Link a new nvparm_format structure to the end 
+ * of a list of nvparm_format structures.
+ *
+ * PARAM1: struct nvparm_format * new_nvformat
+ * PARAM2: struct nvparm_format * head_nvformat
+ *
+ * RETURNS: 0 for OK, -1 for Error.
+ */
+
+int
+install_nvformat(struct nvparm_format * new_nvformat, 
+                 struct nvparm_format * head_nvformat)
+{
+struct nvparm_format * curr_format = head_nvformat;
+
+   if (!curr_format || !new_nvformat)
+   {
+      dprintf("Bad Call to install_nvformat\n");
+      return -1;
+   }
+
+   while (curr_format->next_format)
+      curr_format = curr_format->next_format;
+
+   curr_format->next_format = new_nvformat;
+   return 0;
+}
+
+
+/* Include genlist.h for defn of NICHE_DUP_ENTRY, addition, deletion
+ * of entries in the generic list. */
+
+#include "genlist.h" 
+
+
+/* FUNCTION: nv_get_sec_num()
+ * 
+ * Get the index for the corresponding section.
+ *
+ * PARAM1: char *buf    - buf points to a section name. 
+ * PARAM2: struct nv_sectioninfo *sec - array contain info about sections
+ * PARAM3: int slen     - len of sec[]
+ *
+ * RETURNS: Index to section array or NOT_A_SECTION 
+ */
+
+int
+nv_get_sec_num(char * buf, struct nv_sectioninfo *sec, int slen)
+{
+   int   index,sec_index=NOT_A_SECTION;
+
+   for (index=0; index < slen ; index++ )
+   {
+      if (strncmp(buf, sec[index].name, strlen(sec[index].name)) == 0)
+      {
+         sec_index = index ;
+         break;
+      }
+   }
+   if ( index == slen )  /* Match not found */
+   {
+      /* There is some unknown/disabled section. Ignore it */
+      sec_index = NOT_A_SECTION ;
+   }
+   return sec_index ;
+}
+
+/* FUNCTION: nv_read_parse()
+ * 
+ * Read in the non-volative parameters from a disk or flash file.
+ *
+ * PARAM1: char *fname  - name of file to be read
+ * PARAM2: struct nv_sectioninfo *sec - list of sections and their info.
+ * PARAM3: int slen  - len of sec[] array
+ *
+ * RETURNS: SUCCESS or error number
+
+ * ALGORITHM : Following algo. will be used for parse the whole NV file.
+ *
+ * 1. Read the whole file line by line.
+ * 2. If there is any error, then return with error code
+ * 3. For each line read
+ *    a. skip if it is blank line or a comment line
+ *    b. If it starts with "[", then update sec_index. "sec_index" is
+ *       an index into the sec[] array. Initially it is set to
+ *       NOT_A_SECTION. When a match occurs, it will index the respective
+ *       section in sec array. As in C language, indices for 
+ *       sec[] start with 0.
+ *    c. If it doen't start with "[", check sec_index
+ *       a. If sec_index is NOT_A_SECTION, then continue
+ *       b. Otherwise call the parse_routine for the section indexed
+ *          by sec_index.
+ * 4. Close the file and return.
+ *
+ */
+
+/* to be able to read long lines of ipfilter.nv, defined NV_LONGLINE */
+#define NV_LONGLINE  (NV_LINELENGTH+20)
+
+int nv_read_parse(char *fname, struct nv_sectioninfo *sec,int slen)
+{
+   char * cp;                    /* scratch */
+   FILE * fp;                    /* input file */
+   unsigned line;                 /* current line in input file */
+   int sec_index= NOT_A_SECTION; /* init to not in a list */
+   int ret_code = SUCCESS;
+   static char linebuf[NV_LONGLINE]; /* scratch local buffer for file reading */
+
+   fp = (FILE *)nv_fopen(fname, "r");
+   if (!fp)
+   {
+      return ENP_NOFILE;
+   }
+
+   line = 0;
+   while (nv_fgets(linebuf, NV_LONGLINE, fp) == linebuf)
+   {
+      line++;      
+      if ((linebuf[0] == '#') || /* see if line is commented out */
+          (linebuf[0] == ' ') ||  /* or starts with whitespace */
+          (linebuf[0] == '\t') || /* or starts with whitespace */
+          (linebuf[0] == '\n') || /* or is empty */
+          (linebuf[0] == '\r'))   /* or is empty */
+      {
+         continue;
+      }
+      cp = strchr(linebuf, '\n');   /* find possible linefeed */
+      if (cp)     /* if linefeed exists, null it over */
+         *cp = '\0';
+
+      cp = strchr(linebuf, '#');    /* find possible in-line comment */
+      if (cp)     /* if comment char exists, null it over */
+         *cp = '\0';
+
+      if (linebuf[0] == '[')
+      {
+         sec_index = nv_get_sec_num(&linebuf[1],sec,slen);
+         continue;
+      }
+
+      /* fall to here if linebuf should contain a record */
+      if (sec_index == NOT_A_SECTION)
+         continue;
+      else 
+      {
+         ret_code = sec[sec_index].parse_func(linebuf);
+         if (ret_code != SUCCESS )
+         {
+            dprintf("Error #%d (line %d of %s)\n",ret_code,line,fname);
+            if ( ret_code == NICHE_DUP_ENTRY )
+               continue;
+            else
+            {
+               nv_fclose(fp);
+               return ret_code;
+            } 
+         }
+      }
+   }
+
+   if (line < 1)
+   {
+      ret_code  = ENP_PARAM ;
+   }
+
+   nv_fclose(fp);
+   return ret_code;
+}
+
+#ifdef USE_GENLIST
+
+/* FUNCTION: nv_add_entry()
+ * 
+ * Add an entry to a table. The table is found from
+ * the index'th entry in sec[].  
+ *
+ * Here is the generic idea
+ * - Same parsing function is used to parse an entry from NV file
+ *   and parse the user command on cmdline. 
+ * - Hence the same nv_sectioninfo struct is used to reference the
+ *   parsing function.
+ * - When user enters a cmd (on cmdline) to add an entry to table,
+ *   nv_add_entry() can be used to parse the info and add it to the table.
+ * - Similarly, user enters a cmd (on cmdline) to del an entry in table,
+ *   nv_del_entry() can be used to delete the entry in the table.
+ *
+ * PARAM1: void *pio - Pointer to GenericIO structure
+ * PARAM2: int index - Index in sec[] array.
+ * PARAM3: struct nv_sectioninfo * sec
+ *
+ * RETURNS: SUCCESS or error code.
+ */
+
+int 
+nv_add_entry(void * pio, int index, struct nv_sectioninfo *sec)
+{
+   char *   cp;
+   int   err;
+
+   if ( index == NOT_A_SECTION )
+   {
+      ns_printf(pio,"Could not find info about table. Can't process cmd.\n");
+      return -1;
+   }
+
+   cp = nextarg( ((GEN_IO)pio)->inbuf );  /* see if user put parm on cmd line */
+   if (!*cp)
+   {
+      if ( sec[index].usage_func )
+         sec[index].usage_func(pio);
+      return -1;
+   }
+
+   err=sec[index].parse_func(cp);
+
+   if ( err == SUCCESS )
+      return SUCCESS;
+   else
+   {
+      ns_printf(pio,"Error #%d\n",err);
+      return -1;
+   }
+}
+
+/* FUNCTION: nv_del_entry()
+ * 
+ * Delete an entry (row) from a table. The information
+ * about the table is given by the entry in section table.
+ *
+ * The information on the cmdline, is the index. So if its "5", then
+ * index is 5 (0 based index) and hence the 6th entry/row in the table
+ * is to be deleted.
+ *
+ * Example :
+ * Say for deleting an entry in SNMPv3 group table, user enters the
+ * following command on the command line
+ *    "v3delgroup 3"
+ * v3_del_group() gets called with inbuf member of pio pointing to the cmdline.
+ * It calls nv_del_entry(). It passes a ptr to sec[] and corresponding
+ * index into this array. Hence sec[index] contains information about
+ * the table (SNMpv3 group table in this case) to be modified. 
+ * nv_del_entry() parses the cmdline, that is pio->inbuf, and then 
+ * calls niche_del() to delete the 4th entry/row in the SNMPv3 group table.
+ *
+ * PARAM1: void *pio
+ * PARAM2: int index
+ * PARAM3: struct nv_sectioninfo * sec
+ * 1. Pointer to GenericIO structure
+ * 2. Index in sec[] array.
+ * 3. Pointer to sec[] array
+ *
+ * RETURNS: SUCCESS or error code.
+ */
+
+int 
+nv_del_entry(void * pio, int index, struct nv_sectioninfo *sec)
+{
+   GEN_STRUCT entry;
+   char *   cp;
+
+   if ( index == NOT_A_SECTION )
+   {
+      ns_printf(pio,"Could not find info about table. Can't process cmd.\n");
+      return -1;
+   }
+
+   cp = nextarg( ((GEN_IO)pio)->inbuf );  /* see if user put parm on cmd line */
+   if (!*cp)
+   {
+      if ( sec[index].usage_func )
+         sec[index].usage_func(pio);
+      return -1;
+   }
+
+   entry = niche_list_getat((NICHELIST)sec[index].list,atoi(cp));
+   if ( entry )
+   {
+      niche_del((NICHELIST)sec[index].list,entry);
+      return SUCCESS;
+   }
+   else
+      return -1;
+}
+
+/* FUNCTION: nv_del_entry_byid()
+ * 
+ * Delete an entry (row) from a table. The information
+ * about the table is given by the entry in section table.
+ *
+ * The information on the cmdline is "id" of entry.
+ * Hence the entry in the table with similar "id" needs to be deleted.
+ *
+ * PARAM1: void *pio
+ * PARAM2: int index
+ * PARAM3: struct nv_sectioninfo * sec
+ * 1. Pointer to GenericIO structure
+ * 2. Index in sec[] array.
+ * 3. Pointer to sec[] array
+ *
+ * RETURNS: SUCCESS or error code.
+ */
+
+int 
+nv_del_entry_byid(void * pio, int index, struct nv_sectioninfo *sec)
+{
+   char *   cp;
+
+   if ( index == NOT_A_SECTION )
+   {
+      ns_printf(pio,"Could not find info about table. Can't process cmd.\n");
+      return -1;
+   }
+
+   cp = nextarg( ((GEN_IO)pio)->inbuf );  /* see if user put parm on cmd line */
+   if (!*cp)
+   {
+      if ( sec[index].usage_func )
+         sec[index].usage_func(pio);
+      return -1;
+   }
+
+   return niche_del_id((NICHELIST)sec[index].list,atoi(cp));
+}
+
+
+#endif /* USE_GENLIST */
+
+#endif   /* INCLUDE_NVPARMS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/parseip.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/parseip.c
new file mode 100644
index 0000000..f0c2503
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/parseip.c
@@ -0,0 +1,597 @@
+/*
+ * FILENAME: parseip.c
+ *
+ * Copyright 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * parse_ipad() function and wrapper function inet_addr() for IP applications
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: parse_ipad(), inet_addr(), print46_addr(), 
+ * ROUTINES: inet46_addr(), inet_setport(), 
+ * ROUTINES: hextoa(), inet_pton(), inet_ntop(), print_ip6(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 NetPort Software, all rights reserved. */
+
+
+#include "ipport.h"
+#include "in_utils.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "nvparms.h"
+#include "ip.h"
+#ifndef MINI_IP
+#include "nptcp.h"
+#include "socket.h"
+#ifdef IP_V6
+#include "socket6.h"
+#endif
+#endif /* !MINI_IP */
+
+extern unsigned atoh(const char *);
+#ifdef IP_V6
+char *print_ip6(ip6_addr *, char *);
+#endif
+
+
+/* FUNCTION: parse_ipad()
+ *
+ * parse_ipad(long_out, string_in); Looks for an IP address in 
+ * string_in buffer, makes an IP address (in big endian) in long_out. 
+ * returns NULL if OK, else returns a pointer to a string describing 
+ * problem. 
+ *
+ * 
+ * PARAM1: ip_addr * ipout
+ * PARAM2: unsigned * sbits
+ * PARAM3: char * stringin
+ *
+ * RETURNS: 
+ */
+
+char *   
+parse_ipad(ip_addr * ipout,   /* pointer to IP address to set */
+   unsigned *  sbits,      /* default subnet bit number */
+   char *   stringin)      /* buffer with ascii to parse */
+{
+   char *   cp;
+   int   dots  =  0; /* periods imbedded in input string */
+   int   number;
+   union   
+   {
+      u_char   c[4];
+      u_long   l;
+   } retval;
+   char *   toobig   = "each number must be less than 255";
+
+   cp = stringin;
+   while (*cp)
+   {
+      if (*cp > '9' || *cp < '.' || *cp == '/')
+         return("all chars must be digits (0-9) or dots (.)");
+      if (*cp == '.')dots++;
+         cp++;
+   }
+
+   if ( dots < 1 || dots > 3 )
+      return("string must contain 1 - 3 dots (.)");
+
+   cp = stringin;
+   if ((number = atoi(cp)) > 255)   /* set net number */
+      return(toobig);
+
+   retval.c[0] = (u_char)number;
+
+   while (*cp != '.')cp++; /* find dot (end of number) */
+      cp++;             /* point past dot */
+
+   if (dots == 1 || dots == 2) retval.c[1] = 0;
+      else
+   {
+      number = atoi(cp);
+      while (*cp != '.')cp++; /* find dot (end of number) */
+         cp++;             /* point past dot */
+      if (number > 255) return(toobig);
+         retval.c[1] = (u_char)number;
+   }
+
+   if (dots == 1) retval.c[2] = 0;
+      else
+   {
+      number = atoi(cp);
+      while (*cp != '.')cp++; /* find dot (end of number) */
+         cp++;             /* point past dot */
+      if (number > 255) return(toobig);
+         retval.c[2] = (u_char)number;
+   }
+
+   if ((number = atoi(cp)) > 255)
+      return(toobig);
+   retval.c[3] = (u_char)number;
+
+   if (retval.c[0] < 128) *sbits = 8;
+      else if(retval.c[0] < 192) *sbits = 16;
+      else *sbits = 24;
+
+      *ipout = retval.l;      /* everything went OK, return number */
+   return(NULL);        /* return OK code (no error string) */
+}
+
+
+/* FUNCTION: inet_addr()
+ * 
+ * PARAM1: char far *str
+ *
+ * RETURNS: u_long ipaddr
+ */
+
+u_long 
+inet_addr(char FAR * str)
+{
+   u_long   ipaddr;
+   unsigned bits ;    
+   /* parse_ipad expects a "char and we are passing "char far Hence 
+    * we need to make the conversion. Usually this function will be 
+    * used for debugging, so I think we can bear the STRCPY overhead.
+    */
+   static char nearBuf[30];
+
+   strcpy((char FAR *)nearBuf,str);
+   if ( parse_ipad(&ipaddr,&bits,nearBuf) == NULL )
+   {
+      return ipaddr ;
+   }
+   else
+   {
+      return (u_long)NULL ;
+   }
+}
+
+/* FUNCTION: hextoa()
+ *
+ * convert a single nibble to a hex char for print
+ *
+ * PARAM1: value to print in low 4 bits of unshort
+ *
+ * RETURNS: character 0-9 or A-F
+ */
+
+char
+hextoa(int val)
+{
+   val &= 0x0f;
+   if(val < 10)
+      return (char)(val + '0');
+   else
+      return (char)(val + 55);   /* converts 10-15 -> "A-F" */
+}
+
+
+/* FUNCTION: inet_pton()
+ *
+ * inet_addr for v6 - parse the passed string into an IPv6 address
+ *
+ * This is part of the RFC-2133 IPv6 sockets spec. We've added the feature that
+ * pton_error points to an explanatory string if we return a 1.
+ * 
+ * PARAM1: IN - type of address AF_INET for v4 or AF_INET6 for v6 
+ * PARAM2: IN - string containing v4/v6 address
+ * PARAM3: OUT - resulting v4/v6 address
+ *
+ * RETURNS: 0 if OK, 1 if bad addr format, -1 if bad af arg.
+ */
+
+char * pton_error = "";
+
+int
+inet_pton(int af, const char * src, void * dst)
+{
+  /* 
+   * Altera modification:
+   * Conditionally declare variables to remove build warning
+   */
+#if defined(IP_V6)
+   const char *   cp;      /* char after previous colon */
+   unshort *      dest;    /* word pointer to dst */
+   int            colons;  /* number of colons in src */
+   int            words;   /* count of words written to dest */
+#endif
+
+#if defined(IP_V4) || defined(MINI_IP)
+   /* RFC 2133 wants us to support both types of address */
+   if(af == AF_INET)    /* wants a v4 address */
+   {
+      u_long ip4addr;
+      unsigned sbits;
+      char * err;
+      
+      err = parse_ipad(&ip4addr, &sbits, (char *) src);
+      if(err == NULL)
+      {
+         /* copy the parsed address into caller's buffer, and 
+          * return success
+          */
+         MEMCPY(dst, &ip4addr, sizeof (u_long));
+         return 0;
+      }
+      else
+      {
+         /* return failure */
+         pton_error = "IPv4 address parse failure";
+         return 1;
+      }
+   }
+#endif /* IP_V4 */
+
+#ifdef IP_V6
+
+   if(af != AF_INET6)
+   {
+      pton_error = "bad domain";
+      return -1;
+   }
+
+   /* count the number of colons in the address */
+   cp = src;
+   colons = 0;
+   while(*cp)
+      if(*cp++ == ':') colons++;
+
+   if(colons < 2 || colons > 7)
+   {
+      pton_error = "must have 2-7 colons";
+      return 1;
+   }
+
+   /* loop through address text, parseing 16-bit chunks */
+   cp = src;
+   dest = dst;
+   words = 0;
+
+   if(*cp == ':') /* leading colon has implied zero, e.g. "::1" */
+   {
+      *dest++ = 0;
+      words++;
+      cp++;       /* bump past leading colon, eg ":!" */
+   }
+
+   while(*cp > ' ')
+   {
+      if(words >= 8)
+      {
+	              /* !!!??? */
+	              dprintf("***  inet_pton: logic error?\n");
+         dtrap();    /* logic error? */
+         pton_error = "internal";
+         return 1;
+      }
+      if(*cp == ':')   /* found a double-colon? */
+      {
+         int i;
+
+         for(i = (8 - colons); i > 0; i--)
+         {
+            *dest++ = 0;   /* add zeros to dest address */
+            words++;       /* count total words */
+         }
+         cp++;             /* bump past double colon */
+         if(*cp <= ' ')    /* last colon was last char? */
+         {
+            *dest++ = 0;   /* add one final zero */
+            words++;       /* count total words */
+         }
+      }
+      else
+      {
+         unshort wordval;
+
+         wordval = htons(atoh(cp));    /* get next 16 bit word */
+         if((wordval == 0) && (*cp != '0'))  /* check format */
+         {
+            pton_error = "must be hex numbers or colons";
+            return 1;
+         }
+         *dest++ = wordval;
+         words++;       /* count total words set in dest */
+         cp = strchr((char *)cp, ':');   /* find next colon */
+         if(cp)                  /* bump past colon */
+            cp++;
+         else                 /* no more colons? */
+            break;            /* done with parsing */
+      }
+   }
+   if(words != 8)
+   {
+      pton_error = "too short - missing colon?";
+      return 1;
+   }
+   
+#endif /* IP_V6 */   
+   return 0;
+}
+
+
+/* FUNCTION: inet_ntop()
+ *
+ * Format an IP address for printing.
+ *
+ * PARAM1: int                AF_INET for v4, AF_INET6 for v6
+ * PARAM2: void *             ptr to v4 or v6 address to format
+ * PARAM3: char *             ptr to output buffer
+ * PARAM4: size_t             size of output buffer (bytes)
+ *
+ * RETURNS: char *            ptr to string if OK, else NULL.
+ *
+ * This is part of the RFC-2133 IPv6 sockets spec.
+ * The passed buffer should be big enough for
+ * address output (40 bytes).
+ */
+
+const char *
+inet_ntop(int af, const void *addr, char *str, size_t size)
+{
+   char *cp;
+
+#if defined(IP_V4) || defined(MINI_IP)
+   if (af == AF_INET)
+   {
+      u_long   ip4addr;
+
+      ip4addr = *(u_long*)addr;
+      cp = print_ipad(ip4addr);
+      if (strlen(cp) < size)
+      {
+         strcpy(str, cp);
+         return (str);
+      }
+   }
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+   if (af == AF_INET6)
+   {
+      char ip6buf[48];
+
+      cp = print_ip6((ip6_addr *)addr, ip6buf);
+      if (strlen(cp) < size)
+      {
+         strcpy(str, ip6buf);
+         return (str);
+      }
+   }
+#endif
+
+   return ((const char *)NULL);
+}
+
+
+#ifdef IP_V6
+
+/* FUNCTION: print_ip6()
+ *
+ * Format an IPv6 address for printing. Passed buffer MUST be big
+ * enough for address output (40 bytes).
+ * 
+ * PARAM1: IN - v6 address to format
+ * PARAM2: OUT - string ready to print
+ *
+ * RETURNS: Pointer to string.
+ */
+
+char *
+print_ip6(ip6_addr * addr, char * str)
+{
+   int         i;
+   unshort *   up;
+   char *      cp;
+   unshort     word;
+   int         skip = 0;   /* skipping zeros flag */
+
+   if(addr == NULL)     /* trap NULL pointers */
+      return NULL;
+
+   up = (unshort*)addr;
+   cp = str;
+
+   for(i = 0; i < 8; i++)  /* parse 8 16-bit words */
+   {
+      word = htons(*up);
+      up++;
+
+      /* If word has a zero value, see if we can skip it */
+      if(word == 0)
+      {
+         /* if we haven't already skipped a zero string... */
+         if(skip < 2)
+         {
+            /* if we aren't already skipping one, start */
+            if(!skip)
+            {
+               skip++;
+               if (i == 0)
+                  *cp++ = ':';
+            }
+            continue;
+         }
+      }
+      else
+      {
+         if(skip == 1)  /* If we were skipping zeros... */
+         {
+            skip++;        /* ...stop now */
+            *cp++ = ':';   /* make an extra colon */
+         }
+      }
+
+      if(word & 0xF000)
+         *cp++ = hextoa(word >> 12);
+      if(word & 0xFF00)
+         *cp++ = hextoa((word & 0x0F00) >> 8);
+      if(word & 0xFFF0)
+         *cp++ = hextoa((word & 0x00F0) >> 4);
+      *cp++ = hextoa(word & 0x000F);
+      *cp++ = ':';
+   }
+   if(skip == 1)  /* were we skipping training zeros? */
+   {
+      *cp++ = ':';
+      *cp = 0;
+   }
+   else
+      *--cp = 0;  /* turn trailing colon into null */
+   return str;
+}
+
+#endif
+
+
+#ifndef MINI_IP
+
+/* FUNCTION: print46_addr()
+ * 
+ * Print the address into a string and return a pointer to it.
+ *
+ * PARAM1: struct v3_host *host
+ *
+ * RETURNS: Pointer to string with the address in readable format.
+ */
+
+char * print46_addr(struct sockaddr *ipaddr)
+{
+   if (ipaddr->sa_family == AF_INET)
+   {
+      struct sockaddr_in * addr = (struct sockaddr_in *)ipaddr;
+      return print_ipad(addr->sin_addr.s_addr);
+   }
+#ifdef IP_V6
+   else
+   {
+      struct sockaddr_in6 * addr = (struct sockaddr_in6 *)ipaddr;
+      static char namebuf[46];  /* max len of IPv6 addr */
+      return (char *)inet_ntop(AF_INET6,&addr->sin6_addr, namebuf, sizeof(namebuf));
+   }
+#endif
+
+   return NULL;
+}
+
+/* FUNCTION: inet46_addr()
+ * 
+ * PARAM1: char far *str
+ * PARAM2: struct sockaddr *addr
+ *
+ * inet_pton() is available only if IP_V6 is defined.
+ * Also, it expects us to pass the family !!
+ * So, it can't be used for more generic needs.
+ *
+ * inet46_addr() 
+ * 1. Detects the address family 
+ * 2. Appropriately parses the IPv4/IPv6 address.
+ * 3. If IP_V6 is disabled, it doesn't parse IPv6 adddresses.
+ *
+ * RETURNS: Parsed IP address (IPv4/IPv6) in "address".
+ * Returns 0 on success, else error.
+ *
+ */
+
+int 
+inet46_addr(char * str, struct sockaddr *address)
+{
+   /* Read the IPv4/IPv6 address */
+   address->sa_family = AF_INET; /* assume IPv4 address by default */
+
+   if ((str[1] == '.') || (str[2] == '.') || (str[3] == '.'))
+   {
+      struct sockaddr_in *addr = (struct sockaddr_in *)address;
+      addr->sin_addr.s_addr = inet_addr(str);
+      addr->sin_family = AF_INET;
+   }
+#ifdef IP_V6
+   else
+   {
+      struct sockaddr_in6 *addr = (struct sockaddr_in6 *)address;
+      inet_pton(AF_INET6, str, &addr->sin6_addr);
+      addr->sin6_family = AF_INET6;
+   }
+#endif
+
+   return 0;
+}
+
+
+/* FUNCTION: inet_setport()
+ *
+ * Utility function to set the destination port in the sockaddr structure.
+ * Sets the port for both IPv4 and IPv6 addresses.
+ *
+ * PARAM1: struct sockaddr *addr
+ * PARAM2: int port
+ *
+ * RETURNS: -
+ */
+
+void inet_setport(struct sockaddr *addr,int port) 
+{
+   if (addr->sa_family == AF_INET)
+   {
+      struct sockaddr_in *si = (struct sockaddr_in *)addr;
+      si->sin_port = htons(port);  
+   }
+#ifdef IP_V6
+   else
+   {
+      /* addr->sa_family = AF_INET6 */
+      struct sockaddr_in6 *si = (struct sockaddr_in6 *)addr;
+      si->sin6_port = htons(port);
+   }
+#endif
+
+}
+
+/*
+ *Function Name:convert_ip()
+ *
+ *Parameters:
+ *
+ *Description:
+ *
+ *Returns:
+ *
+ */
+
+unsigned long convert_ip(const char *p)
+{
+   const char *cp = p;
+   unsigned long dw;
+   unsigned char *lpb = (unsigned char *) &dw;
+   int n = 0;
+   unsigned short v = 0;
+   dw = 0;
+   while(*cp)
+   {
+      if( *cp == '.')
+      {
+         lpb[n] = (unsigned char) v;
+         v = 0;
+         n++;
+         if(n > 3)
+         {
+            return dw;
+         }
+      }
+      else if(((*cp >= '0') && (*cp <= '9')))
+      {
+         v = (v * 10) + (*cp - '0');
+      }
+      cp++;
+   }
+   lpb[n] = (unsigned char) v;
+   return dw;
+}  /* convert_ip() */
+
+#endif /* !MINI_IP */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/pcycles.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/pcycles.c
new file mode 100644
index 0000000..bc27b88
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/pcycles.c
@@ -0,0 +1,858 @@
+/*
+ * FILENAME: pcycles.c
+ *
+ * Copyright  2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Routines to measure processing time for various types of packets.
+ *
+ * MODULE: MISCLIB
+ *
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef   PKT_CYCLES     /* whole file can be ifdeffed */
+    
+#ifndef USE_PROFILER
+#error need USE_PROFILER to use PKT_CYCLES
+#endif
+
+#ifndef DYNAMIC_IFACES
+#error need DYNAMIC_IFACES to use PKT_CYCLES
+#endif
+
+#include "in_utils.h"
+#include "menu.h"
+#include "profiler.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+#include "tcpport.h"
+#include "tcp.h"
+
+#ifdef NOTDEF
+#undef INCLUDE_TCP
+#define DEBUG_PCKTCP
+#endif
+
+extern   void     ip_bldhead(PACKET p, 
+   unsigned pid, u_char prot, unshort fragword);
+extern   int   deflength;
+
+/* pseudo iface to generate traffic and measure respose times */
+NET      pc_if;
+static int     pcn_rx_mode = 0;     /* 0 == direct to ip_rcv(); 1 == via pktdemux */
+static u_long  pcn_starttime;       /* pticks at start of current transaction */
+static int     pcn_active;          /* TRUE if we're activly testing */
+
+/* Per-session send and receive counters. They are named from 
+ * the stack's perspective, i.e. a packet passed to this code
+ * from the stack is a "send"
+ */
+static   u_long   pcn_sends;           /* echo replies in current session */
+static   u_long   pcn_recvs;           /* echo replies in current session */
+
+static   char *   cyname = "cy0";      /* iface name */
+static   int      pcn_ipid = 0;        /* ID for IP packets */
+static   u_char   test_prot;           /* protocol of current test */
+static   u_long   calibration = 0;     /* pticks/sec */
+
+/* TCP port numbers for connection */
+static   unshort  client_port = 1024;
+static   unshort  echo_port = 7;
+
+/* sequence and ack numbers, from client's perspective */
+static   u_long   tcpseq;
+static   u_long   tcpack;
+
+static   u_char   tcp_sentflags;    /* last flags passed to pkt_send() */
+static   PACKET   pkc_bldtcp(int ip_length, u_char flags);
+
+
+/* internal to this file */
+int      pkc_rep(void * pio, u_char prot);
+PACKET   pkc_bldip(u_char prot, int length);
+
+
+
+/* MAC routines to implement to pseudo net */
+
+/* Standard MAC net initialization routine */
+
+int
+pcn_n_init(int iface)
+{
+   dtrap();   /* never called??? */
+   USE_ARG(iface);
+   return 0;
+}
+
+/* Standard MAC PACKET send routine */
+
+int
+pcn_pkt_send(struct netbuf * pkt)
+{
+   pcn_sends++;         /* echo replies in current session */
+
+   if(test_prot == IPPROTO_TCP)
+   {
+      struct ip * pip;
+      struct tcphdr * ptcp;
+      int datalen;
+
+      /* extract and save TCP fields needed to interact with stack */
+      pip = (struct ip *)(pkt->nb_prot);
+      ptcp = (struct tcphdr *)ip_data(pip);
+      datalen = (int)htons(pip->ip_len);
+      datalen -= (sizeof(struct ip) + ((ptcp->th_doff & 0xf0) >> 2));
+      tcp_sentflags = ptcp->th_flags;
+
+      tcpseq = htonl(ptcp->th_ack);    /* next SEQ is after his ACK */
+      tcpack = htonl(ptcp->th_seq)  + datalen;  /* ack data */
+
+#ifdef DEBUG_PCKTCP
+      dprintf("send (tcp) pkt:%p flags: %4x, seq:%lx ack %lx pkt-len %d\n", 
+        pkt, tcp_sentflags, tcpseq, tcpack, pkt->nb_plen);
+#endif /* DEBUG_PCKTCP */
+
+      /* if he sent RESET bit then break the test loop */
+      if(tcp_sentflags & TH_RST)
+      {
+         pcn_active = FALSE;
+         return 0;
+      }
+
+      /* if he sent a SYN or FIN we need to add it to data sequence */
+      if(tcp_sentflags & (TH_SYN|TH_FIN))
+      {
+         tcpack++;
+      }
+
+      /* if this is a packet with no data then the stack has not saved 
+       * a pointer to it for a later retry. This means we must free
+       * it now:
+       */
+      if(htons(pip->ip_len) ==
+         (((pip->ip_ver_ihl & 0x0F) + GET_TH_OFF((*ptcp))) << 2))
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      }
+
+      /* If the test loop is done then this is probably a straggling
+       * FIN pkt or a retry of some sort. Ack it now. We deliver the
+       * packet via the rcvdq to avoid potential intinite recursion
+       * issues.
+       */
+      if(!pcn_active)
+      {
+         pkt = pkc_bldtcp(40, TH_ACK);   /* build ack of FIN */
+         if(pkt)
+         {
+            putq(&rcvdq, (qp)pkt);     /* queue ACK of FIN for stack.  */
+            SignalPktDemux();          /* make sure it spins */
+         }
+      }
+   }
+
+   return 0;
+}
+
+/* Standard MAC close routine */
+
+int
+pcn_n_close(int iface)
+{
+   NET ifp = if_getbynum(iface);
+   if(ifp == NULL)
+      return ENP_PARAM;
+
+   ifp->mib.ifAdminStatus = ifp->mib.ifOperStatus = NI_DOWN;
+   return 0;
+}
+
+
+
+/* callback routine for cycle net creation */
+int
+pcn_init(NET ifp, void * bindinfo)
+{
+   int   iface;
+   
+   ifp->n_init = pcn_n_init;           /* set normal callback routines */
+   ifp->pkt_send = pcn_pkt_send;
+   ifp->n_close = pcn_n_close;
+   ifp->n_lnh = 0;                     /* No mac header */
+   ifp->mib.ifPhysAddress = (u_char*)"";  /* null MAC address */
+   ifp->mib.ifType = SLIP;             /* fake SLIP - simple and headerless */
+   ifp->n_lnh = 0;                     /* net's local net header  size */
+   ifp->n_mtu = 1500;                  /* largest legal buffer size */
+   ifp->mib.ifType = LOOPIFTYPE;
+   ifp->mib.ifDescr = (u_char*)"Packet timing test device";
+   ifp->n_flags = NF_NBPROT;
+
+   /* set a default local network address */
+   ifp->n_ipaddr = htonl(0xC0800101);
+   ifp->snmask = htonl(0xFFFFFF00);
+
+   /* add a locally configured route to this iface */
+   iface = if_netnumber(ifp);
+   if(add_route(ifp->n_ipaddr, ifp->snmask, ifp->n_ipaddr, 
+            iface, IPRP_LOCAL) == NULL)
+   {
+      return ENP_RESOURCE;
+   }
+
+   USE_VOID(bindinfo);
+   return 0;
+}
+
+
+int
+pkc_start(void * pio)
+{
+   int      err;        /* error holder */
+
+   err = ni_create(&pc_if, pcn_init, cyname, NULL);
+   if(err)
+   {
+      ns_printf(pio, "error %d creating cycle measure device\n", err);
+      return (err);
+   }
+
+   ns_printf(pio, "Created cycle measure device %s\n", cyname);
+   return 0;
+}
+
+   /* calibrate pticks to real time */
+
+int
+pkc_calibrate(void * pio)
+{
+   u_long   ptime;      /* scratch ptick holder */
+   u_long   ctime;      /* end ctick for ptick calibration */
+   int      seconds;    /* number of seconds to run */
+   char *   arg   =  nextarg( ((GEN_IO)pio)->inbuf );
+
+   seconds = atoi(arg);
+   if(seconds <= 0)
+   {
+      ns_printf(pio, "usage: calibrate X (X is number of seconds)\n");
+      return -1;
+   }
+   ns_printf(pio, "calibrating pticks...");
+
+   ctime = cticks;
+   while(cticks == ctime)     /* wait for next ctick to start */
+      tk_yield();
+
+   ptime = get_ptick();       /* get current value of fast hardware timer */
+   ctime = cticks + (TPS * (u_long)seconds); 
+                              /* get slow real time stop value */
+
+   while(ctime != cticks)     /* wait desired number of seconds */
+      tk_yield();
+
+   ptime = get_ptick() - ptime;    /* get elapsed pticks */
+
+   calibration = ptime/seconds;
+   ns_printf(pio, "done, %lu pticks/sec\n", calibration);
+   
+   return 0;
+}
+
+
+int
+pkc_del(void * pio)
+{
+   int err;
+   
+   /* Since this is not real hardware we don't really need a gracefull
+    * shutdown. Just delete the dynamic iface
+    */
+   if(pc_if == NULL)
+      err = -1;
+   else
+   {
+      err = ni_delete(pc_if);
+      pc_if = NULL;
+   }
+
+   ns_printf(pio, "Deleting cycle iface, code\n");
+   return(err);
+}
+
+/* toggle pcn_rx_mode. */
+
+int
+pkc_mode(void * pio)
+{
+   pcn_rx_mode = !pcn_rx_mode;
+
+   ns_printf(pio, "Pkt Cycle tests set to use %s.\n",
+      pcn_rx_mode?"rcvdq and pktdemux":"direct ip_rcv call");
+
+   return 0;
+}
+
+
+
+/* pkc_bldip() - build the fake received packet IP layer. Building the
+ * transport header is handled in the various routine below. IP header
+ * is built at pkt->nb_prot and nb_plen is adjusted.
+ */
+
+PACKET
+pkc_bldip(u_char prot, int length)
+{
+   PACKET      pkt;
+   struct ip * pip;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pkt = pk_alloc(length + MaxLnh);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if(!pkt)
+      return NULL;
+   pkt->net = pc_if;
+   pkt->nb_plen = length;
+   pkt->nb_prot = pkt->nb_buff + MaxLnh + sizeof(struct ip);
+   pkt->type = IP_TYPE;
+
+   pip = (struct ip *)pkt->nb_prot;
+
+   ip_bldhead(pkt, pcn_ipid++, prot, 0);
+   pip = (struct ip *)pkt->nb_prot;
+   pip->ip_len = htons((unshort)length);
+
+   pip->ip_src = pip->ip_dest = pc_if->n_ipaddr;
+
+   pip->ip_chksum = 0;
+   pip->ip_chksum = ~cksum(pip, 10);
+
+   return pkt;
+}
+
+
+void
+pck_xchgpkt(PACKET pkt)
+{
+   if(pcn_rx_mode == 0)    /* direct feed to IP */
+      ip_rcv(pkt);
+   else     /* send it up through the rcvdq */
+   {
+      putq(&rcvdq, (qp)pkt);  /* enqueue pkt */
+      SignalPktDemux();       /* wake demuxer task */
+      tk_yield();             /* let demux task spin */
+   }
+}
+
+#ifdef TCP_ECHOTEST  /* next few routines needed only for TCP */
+
+extern SOCKTYPE esvr_sock;    /* Echo server socket in tcp_echo.c */
+
+/* pkc_bldtcp() - build a tcp packet based on passed parameters. This
+ * allocates it's own packet buffer and returns it.
+ *
+ * Returns NULL if error
+ */
+
+static PACKET
+pkc_bldtcp(int ip_length, u_char flags)
+{
+   PACKET pkt;
+   struct tcphdr * ptcp;
+
+   pkt = pkc_bldip(IPPROTO_TCP, ip_length);
+   if(!pkt)
+      return NULL;
+
+   ptcp = (struct tcphdr *)(pkt->nb_prot + 20);
+
+   ptcp->th_sport = htons(client_port);
+   ptcp->th_dport = htons(echo_port);
+   ptcp->th_seq = htonl(tcpseq);
+   ptcp->th_ack = htonl(tcpack);
+   ptcp->th_doff = 0x50;
+   ptcp->th_win = htons(0x2000);
+   ptcp->th_urp = 0;
+   ptcp->th_sum = 0;
+   ptcp->th_flags = flags;
+   ptcp->th_sum = tcp_cksum((struct ip *)(pkt->nb_prot));
+
+#ifdef DEBUG_PCKTCP
+   dprintf("bldpkt (tcp) flags: %4x, seq:%lx ack %lx, ip-len:%d\n", 
+        flags, tcpseq, tcpack, ip_length);
+#endif   /* DEBUG_PCKTCP */
+
+   return pkt;
+}
+
+/* pck_tcpconn() - make the tcp echo connection. 
+ */
+
+int
+pck_tcpconn(void * pio)
+{
+   PACKET pkt;
+   u_long conn_tmo;
+
+   client_port++;          /* use a different port each time */
+   tcpseq = 0x00100000;    /* reset sequence number */
+
+    /* make and send a syn packet */
+   pkt = pkc_bldtcp(40, TH_SYN);
+   if(!pkt)
+   {
+      ns_printf(pio, "pck_tcpconn: no pkt\n");
+      return -1;
+   }
+   pck_xchgpkt(pkt);
+
+   /* Make sure that stack responded properly */
+   if(tcp_sentflags != (TH_SYN|TH_ACK))
+   {
+      ns_printf(pio, "pck_tcpconn: no syn-ack\n");
+      return -1;
+   }
+   
+   /* make and send the ACK packet */
+   pkt = pkc_bldtcp(40, TH_ACK);
+   if(!pkt)
+   {
+      ns_printf(pio, "pck_tcpconn: no pkt\n");
+      return -1;
+   }
+   pck_xchgpkt(pkt);
+
+   /* Give server a chance to accept the connection */
+   conn_tmo = cticks + TPS;
+   while(conn_tmo > cticks)
+   {
+      if(esvr_sock != INVALID_SOCKET)
+         break;
+      tk_yield();    /* spin while TCP server socket is invalid */
+   }
+
+   return 0;
+}
+
+
+/* close tcp connection */
+
+int
+pck_tcpfin(void * pio)
+{
+   PACKET   pkt;
+   u_long   tmpseq;
+
+   /* make and send a FIN packet */
+   pkt = pkc_bldtcp(40, TH_FIN|TH_ACK);
+   if(!pkt)
+   {
+      ns_printf(pio, "pck_tcpfin: no pkt\n");
+      return -1;
+   }
+   tmpseq = tcpseq;     /* save pre-fin sequence number */
+   pck_xchgpkt(pkt);
+
+   /* see if the stack responded with a FIN bit */
+   if((tcp_sentflags & TH_FIN) == 0)
+   {
+      /* NicheStack will ACK our FIN before sending his own FIN.
+       * If this happens then return without error. His FIN 
+       * will be acked by the pkt_send() routine.
+       */
+      if(tcpseq == (tmpseq + 1))
+         return 0;
+      ns_printf(pio, "pck_tcpfin: no ACK of FIN\n");
+      return -1;
+   }
+
+   /* ACK his FIN to complete the close */
+   pkt = pkc_bldtcp(40, TH_FIN);
+   if(!pkt)
+   {
+      ns_printf(pio, "pck_tcpfin: no pkt\n");
+      return -1;
+   }
+   pck_xchgpkt(pkt);
+   return 0;
+}
+
+/* tcp_hdrfixup() - prepare tcp header for next itteration */
+
+static void
+tcp_hdrfixup(char * pbuf)
+{
+   struct   tcphdr * ptcp;
+   u_long   seq_change;
+   u_long   ack_change;
+   u_long   tcpsum;
+
+   /* Change the sequence and ACK numbers to reflect the data sent and
+    * received. We get this info from tcpseq and tcpack values set in
+    * pck_pkt_send. Since we change the TCP header we also need to fix
+    * the checksum.
+    */
+   ptcp = (struct tcphdr *)(pbuf + sizeof (struct ip));
+   seq_change = tcpseq - htonl(ptcp->th_seq);
+   seq_change = htonl(seq_change);
+   ack_change = tcpack - htonl(ptcp->th_ack);
+   ack_change = htonl(ack_change);
+
+   tcpsum = ((~(u_long)ptcp->th_sum) & 0x0000ffff);
+   tcpsum += (u_short)(seq_change >> 16);
+   tcpsum += (u_short)(seq_change & 0x0000ffff);
+   tcpsum += (u_short)(ack_change >> 16);
+   tcpsum += (u_short)(ack_change & 0x0000ffff);
+
+   while(tcpsum  & 0xffff0000)   /* if overflow, add high bits back in */
+      tcpsum = (tcpsum & 0x0000ffff) + (tcpsum >> 16);
+
+   ptcp->th_seq = htonl(tcpseq);    /* set the new seq number */
+   ptcp->th_ack = htonl(tcpack);    /* set the new ACK number */
+   ptcp->th_sum = ~(unshort)tcpsum; /* set new checksum */
+}
+#endif /* TCP_ECHOTEST */
+
+void
+pc_printstat(void * pio, u_long itterations, u_long pticks, char * typetext)
+{
+   u_long mult;      /* multiplier to avoid data over flow */
+   u_long pt_pkts;
+   u_long msecs;
+   u_long decimal;
+
+   ns_printf(pio, "Ran %lu reps in %lu ticks; ", itterations, pticks);
+   if(calibration && pticks)
+   {
+      if(pticks/itterations < 1)
+         mult = 10000000;
+      else if (pticks/itterations < 1000)
+         mult = 10000;
+      else if (pticks/itterations < 1000000)
+         mult = 10;
+      else
+         mult = 1;
+
+      if(mult <= 10)
+         pt_pkts = (pticks * mult) / itterations;  /* pticks/packet (scaled) */
+      else
+         pt_pkts = pticks * (mult / itterations);  /* pticks/packet (scaled) */
+
+      /* figure microseconds per pkt. First check for 32 bit overflow... */
+      if((calibration / (10000000 / mult)) > 0)
+      {
+
+         msecs = pt_pkts / (calibration / (10000000 / mult));
+         decimal = msecs;
+         msecs /= 10;
+         decimal -= (msecs * 10);
+
+         ns_printf(pio, "%lu.%lu u_secs per %s", 
+            msecs, decimal, typetext );
+      }
+   }
+   ns_printf(pio, "\n");
+   return;
+}
+
+/* mock up an incoming ping packet and pass it up to IP layer. */
+
+int
+pkc_ping(void * pio)
+{
+   return(pkc_rep(pio, ICMP_PROT));
+}
+   
+
+int
+pkc_rep(void * pio, u_char prot)
+{
+   u_long   itterations;   /* number of pings (from cmd line) */
+   struct   ping * png;    /* ping (ICMP) header to pass to stack */
+   struct   udp * pup;     /* UCP header to pass to stack */
+   u_long   pticks;        /* elpased profiler (fast) ticks */
+   int      ip_len;        /* length of IP packet */
+   int      err;           /* return error holder */
+   PACKET   pkt;           /* packet to send */
+   char     pbuf[40];      /* packet header buffer */
+   int      headerslen;    /* total length of headers */
+   char *   typetext;      /* printable pkt type */
+   char *   arg   =  nextarg( ((GEN_IO)pio)->inbuf );
+#ifdef DEBUG_PCKTCP
+   struct tcphdr * ptcp;
+#endif
+
+   if(pc_if == NULL)
+   {
+      ns_printf(pio, "Open test device with pcmake first.\n");
+      return -1;
+   }
+
+   if(*arg != 0)
+      itterations = (u_long)atol(arg);
+   else
+      itterations = 1;     /* default to one */
+
+   test_prot = prot;       /* save prot for pcn_pkt_send() call */
+   pcn_active = TRUE;      /* now officially testing */
+
+   switch (prot)           /* more per-protocol setup */
+   {
+   case ICMP_PROT:
+      {
+      int pingsize = sizeof(struct ping) + deflength;
+      headerslen = sizeof(struct ip) + sizeof(struct ping);
+      ip_len = deflength + headerslen;    /* allow for IP and ICMP headers */
+      typetext = "ping";
+      pkt = pkc_bldip(prot, ip_len);   /* get basic IP pkt */
+      /* build icmp header after IP */
+      png = (struct ping *)(pkt->nb_prot + sizeof(struct ip));
+      png->ptype = ECHOREQ;
+      png->pseq = 1;
+      png->pchksum = 0;
+      if (ip_len & 1)  /* pad odd length packets  for checksum routine */
+         *(pkt->nb_prot + sizeof(struct ip) + pingsize) = 0;
+      png->pchksum = ~cksum(png, (pingsize + 1) >> 1);
+      break;
+      }
+   case UDP_PROT:
+      {
+      unshort udplen;
+      headerslen = sizeof(struct ip) + sizeof(struct udp);
+      ip_len = deflength + headerslen;    /* allow for IP and ICMP headers */
+      udplen= ip_len - sizeof(struct ip);
+      typetext = "UDP echo";
+      pkt = pkc_bldip(prot, ip_len);   /* get basic IP pkt */
+      /* build UDP header after IP */
+      pup = (struct udp *)(pkt->nb_prot + sizeof(struct ip));
+      pup->ud_dstp = htons(7);            /* dest port is echo */
+      pup->ud_srcp = htons(udp_socket()); /* get a free port for source */
+      pup->ud_len = htons(udplen);        /* IP length minus IP header */
+      pup->ud_cksum = 0;                  /* no cksum, leave that for TCP */
+      break;
+      }
+#ifdef TCP_ECHOTEST
+   case IPPROTO_TCP:
+      err = pck_tcpconn(pio);        /* make the tcp echo connection */
+      if(err)
+      {
+         ns_printf(pio, "TCP setup error\n");
+         return -1;
+      }
+      headerslen = sizeof(struct ip) + sizeof(struct tcphdr);
+      ip_len = deflength + headerslen;    /* allow for IP and transport headers */
+      typetext = "TCP echo";
+      pkt = pkc_bldtcp(ip_len, TH_ACK);
+      break;
+#endif /* TCP_ECHOTEST */
+   default:
+      dtrap();    /* bad prot arg */
+      return -1;
+   }
+
+   MEMCPY(pbuf, pkt->nb_prot, headerslen);   /* save copy of headers */
+
+   ns_printf(pio, "Sending %d %ss into stack...\n", itterations, typetext);
+   
+   pcn_starttime = get_ptick();
+   pcn_sends = pcn_recvs = 0;       /* clear counters */
+   err = 0;
+
+   /* main loop for sending packets. pcn_sends is incremented by the 
+    * pck_pkt_send routine, which should be called before pck_xchgpkt()
+    * returns. Since pck_pkt_send() does not free the packet, just keep
+    * sending the same one. This saves a lot of allocating packets and 
+    * copying.
+    */
+   while(pcn_recvs++ < itterations)
+   {
+      pck_xchgpkt(pkt);
+      if(pcn_sends < pcn_recvs)    /* make sure we got response */
+      {
+         err = -1;
+         ns_printf(pio, "Lost pkt #%lu, aborting.\n", pcn_recvs);
+         break;
+      }
+      if(!pcn_active)      /* see if we got reset or something */
+      {
+         err = -1;
+         ns_printf(pio, "reset, aborting.\n");
+         break;
+      }
+      pc_if->mib.ifInNUcastPkts++;
+      pc_if->mib.ifInOctets += ip_len;
+
+      /* modify the TCP header for the next pass */
+      if((prot == IPPROTO_TCP) && 
+         (pcn_recvs < itterations))    /* skip last pass */
+      {
+         tcp_hdrfixup(&pbuf[0]);
+      }
+      MEMCPY(pkt->nb_prot, pbuf, headerslen);   /* restore headers from copy */
+
+#ifdef DEBUG_PCKTCP
+      /* Double-check the checksum modification */
+      if((prot == IPPROTO_TCP) &&
+         (pcn_recvs < itterations))    /* skip last pass */
+      {
+         u_short  tcpsum;
+
+         ptcp = (struct tcphdr *)(pkt->nb_prot + sizeof (struct ip));
+         tcpsum = ptcp->th_sum;     /* save sum to check */
+         ptcp->th_sum = 0;          /* zero pkt buffer sum for computation */
+         ptcp->th_sum = tcp_cksum((struct ip *)(pkt->nb_prot));
+         if(ptcp->th_sum != tcpsum)
+         {
+            dtrap();
+            break;
+         }
+      }
+#endif   /* DEBUG_PCKTCP */
+   }
+
+   /* If there was no error in the main loop, print results */
+   if(!err)
+   {
+      pticks = get_ptick() - pcn_starttime;
+
+      if(prot == IPPROTO_TCP)
+         pck_tcpfin(pio);    /* close tcp connection before we printf */
+
+      pc_printstat(pio, itterations, pticks, typetext);
+   }
+   pcn_active = FALSE;               /* Officially done testing */
+
+   /* If we got an error the packet is probably freed, else free it here: */
+   if(err == 0){
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+   return err;
+}
+
+int
+pkc_tcpecho(void * pio)
+{
+#ifdef TCP_ECHOTEST
+   return(pkc_rep(pio, IPPROTO_TCP));
+#else
+   ns_printf(pio, "No TCP_ECHOTEST in this build\n");
+   return -1;
+#endif
+}
+
+int
+pkc_udpecho(void * pio)
+{
+   return(pkc_rep(pio, UDP_PROT));
+}
+
+
+int
+pkc_tcpsess(void * pio)
+{
+#ifdef TCP_ECHOTEST
+   u_long   itterations;   /* number of sessions (from cmd line) */
+   u_long   sessions;      /* number already done */
+   u_long   pticks;
+   int      err;
+   int      ip_len;
+   char *   arg   =  nextarg( ((GEN_IO)pio)->inbuf );
+   PACKET   pkt;
+
+   if(pc_if == NULL)
+   {
+      ns_printf(pio, "Open test device with pcmake first.\n");
+      return -1;
+   }
+
+   if(*arg != 0)
+      itterations = (u_long)atol(arg);
+   else
+      itterations = 1;     /* default to one */
+
+   test_prot = 6;          /* save prot for pcn_pkt_send() call */
+   pcn_active = TRUE;      /* now officially testing */
+   ns_printf(pio, "Timing %d TCP echo sessions...\n", itterations);
+
+   sessions = err = 0;
+   ip_len = deflength + sizeof(struct ip) + sizeof(struct tcphdr);
+
+   pcn_starttime = get_ptick();
+
+   while(sessions++ < itterations)
+   {
+      err = pck_tcpconn(pio);        /* make the tcp echo connection */
+      if(err)
+      {
+         ns_printf(pio, "TCP setup error\n");
+         break;
+      }
+
+      pcn_sends = pcn_recvs = 0;    /* clear counters */
+      pkt = pkc_bldtcp(ip_len, TH_ACK);
+      pck_xchgpkt(pkt);             /* send a single echo packet */
+      if(pcn_sends < pcn_recvs)     /* make sure we got response */
+      {
+         err = -1;
+         ns_printf(pio, "Lost data pkt in loop #%lu, aborting.\n", sessions);
+         break;
+      }
+      if(!pcn_active)      /* see if we got reset or something */
+      {
+         err = -1;
+         ns_printf(pio, "reset, aborting.\n");
+         break;
+      }
+      pc_if->mib.ifInNUcastPkts++;
+      pc_if->mib.ifInOctets += ip_len;
+
+   }
+
+   pticks = get_ptick() - pcn_starttime;
+
+   /* If there was no error in the main loop, print results */
+   if(!err)
+   {
+      pticks = get_ptick() - pcn_starttime;
+      pck_tcpfin(pio);    /* close tcp connection before we printf */
+      pc_printstat(pio, itterations, pticks, "TCP echo session");
+   }
+   pcn_active = FALSE;               /* Officially done testing */
+
+   return err;
+
+#else /* TCP_ECHOTEST */
+   ns_printf(pio, "No TCP in this build\n");
+   return -1;
+#endif
+}
+
+int
+pkc_data(void * pio)
+{
+   ns_printf(pio, "pkt Cycle measurement status:\n");
+   ns_printf(pio, "  Device is %s\n", pc_if?"open":"closed");
+   if(calibration == 0)
+      ns_printf(pio, "  Profile ticks not calibrated\n");
+   else
+      ns_printf(pio, "  Profile ticks calibrated at %d ticks/sec\n", calibration);
+   if(pcn_rx_mode)
+      ns_printf(pio, "  receives use rcvdq and a task switch\n");
+   else
+      ns_printf(pio, "  receives passed direct to ip_rcv()\n");
+
+   return 0;
+}
+
+#endif   /* PKT_CYCLES  */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/profiler.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/profiler.c
new file mode 100644
index 0000000..c67f055
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/profiler.c
@@ -0,0 +1,539 @@
+/*
+ * FILENAME: profiler.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * profiler.c Profile code for portions of the InterNiche TCP/IP 
+ * stack and related modules. 
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: pf_start(), pf_stop(), pf_stats(), pm_start(), 
+ * ROUTINES: pm_stop(), pf_ticklog(),
+ *
+ * PORTABLE: no
+ */
+
+
+#include "ipport.h"
+
+#ifdef USE_PROFILER  /* whole file can be ifdeffed */
+
+#include "in_utils.h"
+#include "menu.h"
+#include "profiler.h"
+
+
+static u_long   start_tick;
+static u_long   stop_tick;
+static u_long   last_tick;
+
+
+struct pbucket * PF_IP;
+struct pbucket * PF_USUM;
+struct pbucket * PF_IDLE;
+struct pbucket * PF_TCP;
+struct pbucket * PF_TSUM;
+struct pbucket * PF_WEB ;
+struct pbucket * PF_FTP;
+struct pbucket * PF_FS;
+struct pbucket * PF_NAT;
+struct pbucket * PF_IPSEC;
+struct pbucket * PF_OTHER;       /* bucket for everything we don't track */
+struct pbucket * PF_CRYPTOENG;
+
+/* predefine the array of pbuckets for modules we can profile by default */
+
+struct pbucket in_pbuckets[NUM_PBUCKETS];
+
+
+#define  NEST_DEPTH     8
+static struct pbucket * current;
+static struct pbucket * nested[NEST_DEPTH];
+static int     nestindex;
+static int     pfinitialized = FALSE;
+static int     pfrunning = 0;
+
+int   pfmodules;     /* number of modules being profiled */
+
+
+/* If you have trouble when enabling the profiler (especially
+ * if you have added modeuls at runtime), then enable the define
+ * below for some error checking. Don't leave it on for general
+ * use since it slows things up quite a bit.
+ */
+
+#ifdef NOTDEF
+#define PFDEBUG
+#endif
+
+/* FUNCTION: pf_start()
+ * 
+ * lowest level profile start primitive. This is exported for
+ * applications to call
+ *
+ * PARAM1: N/A
+ *
+ * RETURNS: N/A
+ */
+
+void
+pf_start()
+{
+   int i;
+
+   if(pfrunning)
+      return;
+
+   if(pfinitialized == FALSE)
+   {
+      int module = 0;
+
+      /* skip past any runtime added modules */
+      while(in_pbuckets[module].name)
+         module++;
+
+      PF_IP = &in_pbuckets[module];
+      in_pbuckets[module].name = "IP";
+      in_pbuckets[module++].id = &PF_IP;
+
+      PF_USUM = &in_pbuckets[module];
+      in_pbuckets[module].name = "UDP sum";
+      in_pbuckets[module++].id = &PF_USUM;
+
+      PF_OTHER = &in_pbuckets[module];
+      in_pbuckets[module].name = "other";
+      in_pbuckets[module++].id = &PF_OTHER;
+
+#ifdef INICHE_TASKS /* idle loop */
+      PF_IDLE = &in_pbuckets[module];
+      in_pbuckets[module].name = "idle";
+      in_pbuckets[module++].id = &PF_IDLE;
+#endif
+
+#ifdef INCLUDE_TCP
+      PF_TCP = &in_pbuckets[module];  /* TCP layer & sockets */
+      in_pbuckets[module].name = "TCP";
+      in_pbuckets[module++].id = &PF_TCP;
+
+      PF_TSUM = &in_pbuckets[module];   /* TCP checksumming  */
+      in_pbuckets[module].name = "TCP sum";
+      in_pbuckets[module++].id = &PF_TSUM;
+#endif
+#ifdef WEBPORT
+      PF_WEB = &in_pbuckets[module];
+      in_pbuckets[module].name = "WebPort";
+      in_pbuckets[module++].id = &PF_WEB;
+#endif
+#ifdef FTP_SERVER
+      PF_FTP = &in_pbuckets[module];
+      in_pbuckets[module].name = "FTP srv";
+      in_pbuckets[module++].id = &PF_FTP;
+#endif
+#ifdef VFS_FILES
+      PF_FS = &in_pbuckets[module];  /* VFS (may include native) */
+      in_pbuckets[module].name = "VFS";
+      in_pbuckets[module++].id = &PF_FS;
+#endif
+#ifdef NATRT
+      PF_NAT = &in_pbuckets[module];  /* NAT routing */
+      in_pbuckets[module].name = "NAT";
+      in_pbuckets[module++].id = &PF_NAT;
+#endif
+#ifdef IPSEC
+      PF_IPSEC = &in_pbuckets[module];  /* IPSEC */
+      in_pbuckets[module].name = "IPSEC";
+      in_pbuckets[module++].id = &PF_IPSEC;
+#endif
+#ifdef USE_CRYPTOENG
+      PF_CRYPTOENG = &in_pbuckets[module];  
+      in_pbuckets[module].name = "CryptoEngine";
+      in_pbuckets[module++].id = &PF_CRYPTOENG;
+#endif
+
+      pfinitialized = TRUE;
+
+      /* end of firsttime setup. */
+   }
+   
+   pfmodules = 0;    /* init active module count */
+
+   /* reset all the bucket times to zero */
+   for (i = 0; i < NUM_PBUCKETS; i++)
+   {
+      in_pbuckets[i].ticks = 0;
+      if(in_pbuckets[i].name)
+         pfmodules++;      /* count active modules */
+   }
+
+   /* Call the routine which gets the current "profile tick" count. This
+    * is generally not the same as cticks - it should be much faster.
+    * This routine should be implemented by all hardware ports (BSPs)
+    * which support profiling. If it shows up as unresolved during
+    * link time then you need to provide it.
+    */
+   start_tick = get_ptick();     /* call hardware tick routine */
+
+   last_tick = start_tick;
+   pfrunning = 1;
+   nestindex = 0;       /* now supended profile threads */
+   current = NULL;      /* no current profile thread. */
+}
+
+
+
+/* FUNCTION: pf_stop()
+ * 
+ * lowest level profile stop primitive. This is exported for
+ * applications to call
+ *
+ * PARAM1: N/A
+ *
+ * RETURNS: N/A
+ */
+
+void
+pf_stop()
+{
+   if (!pfrunning)
+      return;
+
+   stop_tick = get_ptick();
+
+   pfrunning = 0;
+}
+
+
+/* FUNCTION: pf_addmodule()
+ * 
+ * this is called to add a new module to profiling. The returned value is 
+ * the module ID which should be passed to IN_PROFILER() to begin/exit
+ * profiling the module. The passed name should be static text.
+ *
+ *
+ * PARAM1: char * name of module
+ *
+ * RETURNS: Id of module or NULL if error .
+ */
+
+
+void *
+pf_addmodule(char * name)
+{
+   int i;
+
+   if(pfmodules >= (NUM_PBUCKETS - 2))
+      return NULL;
+
+   for (i = 0; i < NUM_PBUCKETS; i++)
+   {
+      if(in_pbuckets[i].name == NULL)  /* found empty bucket? */
+      {
+         in_pbuckets[i].name = name;
+         in_pbuckets[i].ticks = 0;
+         in_pbuckets[i].id = (struct pbucket**)(&(in_pbuckets[i].id));
+         return ((void*)in_pbuckets[i].id);
+      }
+   }
+   return 0;      /* no empty buckets */
+}
+
+
+/* FUNCTION: pf_ticklog()
+ * 
+ * Exported routine called by profiled modules to indicate when
+ * they are being entered or exited.
+ *
+ * PARAM1: int id     - module ID (e.g. PF_TCP)
+ * PARAM2: int opcode - PF_ENRY or PF_EXIT
+ *
+ * RETURNS: 
+ */
+
+void
+pf_ticklog(struct pbucket * id, int opcode)
+{
+   u_long   now;        /* current tick */
+   u_long   elapsed;    /* ticks since last call */
+
+#ifdef PFDEBUG
+   if((id->id != id) || (if->name == NULL))
+   {
+      dtrap();    /* invalid id parameter */
+      return;
+   }
+   if ((opcode != PF_ENTRY) && (opcode != PF_EXIT))
+   {
+      dtrap();    /* bogus opcode passed */
+      return;
+   }
+#endif /* PFDEBUG */
+
+   /* don't do this if we're not profiling */
+   if (!pfrunning)
+      return;
+
+   /* get current tick value */
+   now = get_ptick();
+
+   /* figure out elapsed tick count - check for wrap */
+   if(now >= last_tick)
+      elapsed = now - last_tick;
+   else        /* tick wrapped */
+      elapsed = now + ((u_long)0xFFFFFFFF - last_tick) + 1;
+
+   /* see if we are entering or exiting a profile section */
+   if (opcode == PF_ENTRY)
+   {
+      if (nestindex >= NEST_DEPTH)
+      {
+#ifdef PFDEBUG
+         printf("pf_ticklog(): exceeded profile nesting limit\n");
+#endif
+/*         dtrap();*/    /* exceeded profile nesting limit */
+         return;
+      }
+
+#ifdef PFDEBUG
+      if(current == id)
+      {
+         dtrap();    /* double entry in same module */
+      }
+#endif /* PFDEBUG */
+
+      /* see if we are preempting another running profile bucket */
+      if (current)
+      {
+         current->ticks += elapsed;       /* save count for prempted module */
+         nested[nestindex++] = current;   /* "push" prempted bucket */
+      }
+      else
+         PF_OTHER->ticks += elapsed;
+
+      current = id;     /* switch current bucket to passed ID */
+   }
+   else  /* opcode == PF_EXIT */
+   {
+      id->ticks += elapsed;
+
+      /* see if we had preempted another running profile bucket */
+      if (nestindex)
+         current = nested[--nestindex];   /* restore preempted bucket */
+      else
+         current = NULL;
+   }
+
+   last_tick = now;
+}
+
+
+#ifdef IN_MENUS
+
+static   int   pm_start(void * pio);
+static   int   pm_stop(void * pio);
+static   int   pf_stats(void * pio);
+static   int   pm_wrap(void * pio);
+extern   int   pkc_tcpsess(void * pio);
+
+struct menu_op profmenu[] =
+{
+   "profile",  stooges,       "profiler menu",      /* menu ID */
+   "pbegin",   pm_start,      "begin profiling",
+   "pend",     pm_stop,       "end profiling",
+   "pwrap",    pm_wrap,       "Wrap menu command inside profile start/stop",
+   "pdump",    pf_stats,      "dump profile data",
+#ifdef   PKT_CYCLES
+   "pcmake",   pkc_start,     "Create pkt cycle pseudo driver",
+   "pcdel",    pkc_del,       "Delete pkt cycle pseudo driver",
+   "pcalb",    pkc_calibrate, "Calibrate profile ticks value",
+   "pcrecv",   pkc_mode,      "Toggle use of rcvdq in pkt cycle tests",
+   "pcping",   pkc_ping,      "Generate ping rx from pseudo driver",
+   "pctcp",    pkc_tcpecho,   "Generate TCP echo packets from pseudo driver",
+   "pcudp",    pkc_udpecho,   "Generate UDP echo REQ from pseudo driver",
+   "pcsess",   pkc_tcpsess,   "Do entire TCP echo sessions",
+   "pcdata",   pkc_data,      "Display current  pkt cycle data",
+#endif   /*PKT_CYCLES  */
+   NULL,
+};
+
+
+/* the rest of this file in Iniche Menus system interface */
+
+/* FUNCTION: pf_percent()
+ * 
+ * pf_percent() - helper routine to calculate the percentage the passed
+ * "ticks" is of the passed "total".
+ *
+ * PARAM1: total - number to take the percent from
+ * PARAM2: ticks - take this percentage of total
+ * PARAM3: pct - (OUT) percentage ticks is of total (0 - 99)
+ * PARAM4: dec - (OUT) decmal point for pct
+ *
+ * RETURNS: values in pct and dec
+ */
+
+void
+pf_percent(u_long total, u_long ticks, int * pct, int * dec)
+{
+   u_long percent;
+   u_long decimal;
+
+   /* avoid divide by zero and other wierd math */
+   if((total < 1) || (ticks > total))
+   {
+      *pct = *dec = 0;
+      return;
+   }
+
+   /* Calculate integers for percentage and decimal place.
+    * for large values, avoid letting the data wrap.
+    * for small values of total, avoid losing the first three
+    * significant figures.
+    */
+
+   if(ticks > 10000)
+   {
+      percent = (int)(ticks / (total / 100) );
+      decimal = (int)(ticks / (total / 1000) );
+      decimal -= (percent * 10);
+   }
+   else     /* small value */
+   {
+      percent = (int)((ticks * 100) / total);
+      decimal = (int)((ticks * 1000) / total);
+      decimal -= (percent * 10);
+   }
+   *pct = (int)percent;
+   *dec = (int)decimal;
+}
+
+/* FUNCTION: pf_stats()
+ * 
+ * Menu routine - profile info dump routine.
+ 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+static int
+pf_stats(void * pio)
+{
+   int   i;
+   int   pct;
+   int   dec;
+   u_long   total;
+
+   if (pfrunning)
+   {
+      ns_printf(pio, "Profiling, please stop first.\n");
+      return -1;
+   }
+
+   /* get total elapsed ticks. Check for wrap. If it wrapped more than
+    * once then we are hosed:
+    */
+   if(stop_tick > start_tick)
+      total = stop_tick - start_tick;
+   else
+      total = stop_tick + (0xFFFFFFFF - start_tick);
+
+   ns_printf(pio, "total ticks:%10lu\n", total);
+
+   if (total == 0)
+      return 0;
+
+   ns_printf(pio, "  module  ticks     (percent)\n");
+
+   /* display the bucket times */
+   for (i = 0; i< NUM_PBUCKETS; i++)
+   {
+      /* skip entrys which are not set */
+      if (in_pbuckets[i].name == NULL)
+         continue;
+      pf_percent(total, in_pbuckets[i].ticks, &pct, &dec);
+      ns_printf(pio, "%11s %10lu (%3u.%u)\n", in_pbuckets[i].name,
+         in_pbuckets[i].ticks, pct, dec );
+   }
+
+   return 0;
+}
+
+
+/* FUNCTION: pm_start()
+ * 
+ * Menu routine - wrapper for pf_Start()
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+static   int
+pm_start(void * pio)
+{
+   pf_start();
+   ns_printf(pio, "Profiling started.\n");
+   return 0;
+}
+
+
+
+/* FUNCTION: pm_stop()
+ * 
+ * Menu routine - wrapper for pf_Stop()
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+static   int
+pm_stop(void * pio)
+{
+   pf_stop();
+   ns_printf(pio, "Profiling stopped.\n");
+   pf_stats(pio);
+   return 0;
+}
+
+/* FUNCTION: pm_wrap()
+ * 
+ * Menu routine - wrap another menu command in a profile start/stop
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+static   int
+pm_wrap(void * pio)
+{
+   char * arg;
+
+   arg = nextarg( ((GEN_IO)pio)->inbuf );
+   if(*arg == 0)
+   {
+      ns_printf(pio, "usage: pwrap menu command [and args]");
+      return -1;
+   }
+
+   ns_printf(pio, "profiling command \"%s\"\n", arg);
+
+   /* move args up to front of cmd buf for pass to menus */
+   MEMMOVE(((GEN_IO)pio)->inbuf, arg, strlen(arg) );
+
+   pf_start();             /* start profiling */
+   do_command(pio );       /* recurse into menu system */
+   pf_stop();              /* stop profiling */
+   pf_stats(pio);          /* show what happend */
+   return 0;
+}
+
+#endif   /* IN_MENUS */
+
+#endif   /*  USE_PROFILER */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rawiptst.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rawiptst.c
new file mode 100644
index 0000000..c1c32ac
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rawiptst.c
@@ -0,0 +1,1298 @@
+/*
+ * FILENAME: rawiptst.c
+ *
+ * Copyright 1995-2002 InterNiche Technologies Inc. All rights reserved.
+ *
+ * Test program for raw IP sockets API.  Implements raw IP 
+ * testers which send and receive datagrams from raw sockets.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: raw_testerq_lock(), raw_testerq_unlock(),
+ * ROUTINES: raw_tester_new(), raw_tester_del(), raw_tester_delid(),
+ * ROUTINES: raw_tester_findid(), 
+ * ROUTINES: raw_testerq_poll(),
+ * ROUTINES: raw_ristart(), raw_ridelete(), raw_rilist(), raw_risend(),
+ * ROUTINES: raw_rihalt(), raw_ribind(), raw_riconnect(), raw_richeck(),
+ * ROUTINES: raw_rihdrincl(), raw_test_init()
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"     /* NetPort embedded system includes */
+
+#ifdef RAWIPTEST        /* whole file can be ifdef'd out */
+
+#include "tcpport.h"    /* NetPort embedded system includes */
+#include "in_utils.h"
+#include "dns.h"
+#include "menu.h"
+
+/* RAWIPTEST_BUFLEN - length of buffer used for receives and sends
+ *
+ * Ideally, this should be large enough to hold the largest datagram
+ * you expect to send or receive, including its IP header.
+ *
+ * You can override this definition from ipport.h if desired.
+ */
+#ifndef RAWIPTEST_BUFLEN
+#define RAWIPTEST_BUFLEN      1536
+#endif  /* RAWIPTEST_BUFLEN */
+
+/* build up a sockets-API abstraction
+ */
+#ifndef SOCKTYPE
+#define SOCKTYPE        long
+#endif /* SOCKTYPE */
+
+#define  socket(x,y,z)           t_socket(x,y,z)
+#define  bind(s,a,al)            t_bind(s,a)
+#define  connect(s,a,al)         t_connect(s,a)
+#define  send(s,b,l,f)           t_send(s,b,l,f)
+#define  sendto(s,b,l,f,a,al)    t_sendto(s,b,l,f,a)
+#define  recvfrom(s,b,l,f,a,al)  t_recvfrom(s,b,l,f,a)
+#define  socketclose(s)          t_socketclose(s)
+#define  getsockopt(s,l,o,d,dl)  t_getsockopt(s,o,d)
+#define  setsockopt(s,l,o,d,dl)  t_setsockopt(s,o,d)
+
+/* raw_tester_buf[] - buffer used for receives and sends
+ */
+static char raw_tester_buf[RAWIPTEST_BUFLEN];
+
+extern   ip_addr  activehost;    /* default host to send to */
+extern   u_long   pingdelay;     /* time (ticks) to delay between sends */
+extern   int      deflength;     /* default send data length */
+
+static   char *   echodata =    "UDP echo number:            ";
+
+/* List of error codes used by this file */
+#define  RITE_BASE                  (-9100)
+#define  RITE_ALLOC_ERROR           (RITE_BASE+1)
+#define  RITE_SOCKET_FAILED         (RITE_BASE+2)
+#define  RITE_SETOPT_FAILED         (RITE_BASE+3)
+#define  RITE_TESTER_NOTFOUND       (RITE_BASE+4)
+
+#define  SUCCESS                    0
+
+/* struct raw_tester - raw IP socket tester
+ */
+struct raw_tester
+{
+   struct raw_tester * next;     /* next raw_tester in queue */
+   void * pio;                   /* where to write console output */
+   unsigned id;                  /* tester identification */
+   SOCKTYPE sock;                /* socket for this tester */
+   unsigned conn : 1;            /* flag: socket is connected */
+   unsigned sending : 1;         /* flag: tester is sending */
+   unsigned rxcheck : 1;         /* flag: check received data */
+   unsigned long sendtoaddr;     /* IP address (network order) to send to */
+   long sendcount;               /* how many sends to do */
+   long sendsdone;               /* how many sends done */
+   int sendlen;                  /* # bytes to send each time */
+   unsigned long senddelay;      /* ticks to delay after each send */
+   unsigned long lastsendtime;   /* tick count at last send */
+   int senderr;                  /* socket error that stopped sending */
+};
+
+/* raw_testerq - queue of testers
+ */
+static struct raw_tester * raw_testerq = NULL;
+
+/* raw_testerq_locked - flag indicating that raw_testerq is locked
+ *                      for modification
+ */
+static volatile int raw_testerq_locked = 0;
+
+/* raw_tester_idseq - identification sequence for raw tester
+ */
+static unsigned raw_tester_idseq = 0;
+
+/* FUNCTION: raw_testerq_lock()
+ *
+ * Unconditionally locks the raw_testerq, blocking until locked.
+ *
+ * RETURNS: void
+ */
+void
+raw_testerq_lock(void)
+{
+   do {
+      while (raw_testerq_locked)
+         tk_yield();
+      raw_testerq_locked++;
+      if (raw_testerq_locked != 1)
+         raw_testerq_locked--;
+   } 
+   while (raw_testerq_locked != 1);
+}
+
+/* FUNCTION: raw_testerq_unlock()
+ *
+ * Unlocks the raw_testerq.
+ *
+ * RETURNS: void
+ */
+void
+raw_testerq_unlock(void)
+{
+   raw_testerq_locked--;
+}
+
+/* FUNCTION: raw_tester_new()
+ *
+ * Creates a new raw IP tester.  Allocates memory for a new 
+ * raw_tester structure, fills it in, links it to the queue.
+ */
+int
+raw_tester_new(void * pio, 
+               int protocol)
+{
+   struct raw_tester * newtester;
+   int e;
+
+   /* allocate storage for the tester state */
+   newtester = (struct raw_tester *) npalloc(sizeof(struct raw_tester));
+   if (newtester == NULL)
+   {
+      ns_printf(pio, "raw_tester_new: npalloc() failed\n");
+      return RITE_ALLOC_ERROR;
+   }
+
+   /* give it a new ID */
+   newtester->id = raw_tester_idseq++;
+
+   /* keep track of where to write console output */
+   newtester->pio = pio;
+
+   /* make a socket of given protocol */
+   newtester->sock = socket(PF_INET, SOCK_RAW, protocol);
+   if (newtester->sock == -1)
+   {
+      ns_printf(pio, "raw_tester_new: [%u] socket() failed\n",
+                newtester->id);
+      npfree(newtester);
+      return RITE_SOCKET_FAILED;
+   }
+
+   /* put the socket in non-blocking mode 
+    * NOTE this needs changing for non-InterNiche stacks
+    */
+   e = t_setsockopt(newtester->sock, SO_NBIO, NULL);
+   if (e == -1)
+   {
+      ns_printf(pio, 
+                "raw_tester_new: [%u] t_setsockopt() failed, err %d\n",
+                newtester->id, t_errno(newtester->sock));
+      socketclose(newtester->sock);
+      npfree(newtester);
+      return RITE_SETOPT_FAILED;
+   }
+
+   /* lock the tester queue */
+   raw_testerq_lock();
+
+   /* link the tester state into the queue */
+   newtester->next = raw_testerq;
+   raw_testerq = newtester;
+
+   /* unlock the tester queue */
+   raw_testerq_unlock();
+
+   /* and return the ID of the new tester */
+   return newtester->id;
+}
+
+/* FUNCTION: raw_tester_del()
+ *
+ * Deletes a raw IP tester.  Removes it from the tester queue,
+ * closes its socket (if open), frees its storage.
+ * Assumes tester queue is locked.
+ *
+ * PARAM1: struct raw_tester * tester; IN- ptr to tester to delete
+ * 
+ * RETURNS:
+ *
+ */
+int
+raw_tester_del(struct raw_tester * tester)
+{
+   struct raw_tester * qtester;     /* current entry in queue */
+   struct raw_tester * pqtester;    /* previous entry in queue */
+
+   /* locate the tester in the queue */
+   for (pqtester = NULL, qtester = raw_testerq; 
+        qtester != NULL;
+        pqtester = qtester, qtester = qtester->next)
+      if (qtester == tester)
+         break;
+
+   /* if we didn't find it, bail out */
+   if (qtester == NULL)
+      return RITE_TESTER_NOTFOUND;
+
+   /* unlink it from the queue */
+   if (pqtester == NULL)
+      raw_testerq = qtester->next;
+   else
+      pqtester->next = qtester->next;
+
+   /* if it's got a socket, close it */
+   if (qtester->sock != INVALID_SOCKET)
+   {
+      socketclose(qtester->sock);
+   }
+
+   /* free its storage */
+   npfree(qtester);
+
+   /* and return success */
+   return SUCCESS;
+}
+
+/* FUNCTION: raw_tester_delid()
+ *
+ * Deletes a raw IP tester.  Removes it from the tester queue,
+ * closes its socket (if open), frees its storage.
+ * Assumes tester queue is locked.
+ *
+ * PARAM1: unsigned id; IN- ID of tester to delete
+ * 
+ * RETURNS: integer indicating success or failure.
+ */
+int
+raw_tester_delid(unsigned id)
+{
+   struct raw_tester * qtester;     /* current entry in queue */
+   struct raw_tester * pqtester;    /* previous entry in queue */
+
+   /* locate the tester in the queue */
+   for (pqtester = NULL, qtester = raw_testerq; 
+        qtester != NULL;
+        pqtester = qtester, qtester = qtester->next)
+      if (qtester->id == id)
+         break;
+
+   /* if we didn't find it, bail out */
+   if (qtester == NULL)
+      return RITE_TESTER_NOTFOUND;
+
+   /* unlink it from the queue */
+   if (pqtester == NULL)
+      raw_testerq = qtester->next;
+   else
+      pqtester->next = qtester->next;
+
+   /* if it's got a socket, close it */
+   if (qtester->sock != INVALID_SOCKET)
+   {
+      socketclose(qtester->sock);
+   }
+
+   /* free its storage */
+   npfree(qtester);
+
+   /* and return success */
+   return SUCCESS;
+}
+
+/* FUNCTION: raw_tester_findid()
+ *
+ * Deletes a raw IP tester.  Removes it from the tester queue,
+ * closes its socket (if open), frees its storage.
+ * Assumes tester queue is locked.
+ *
+ * PARAM1: unsigned id; IN- ID of tester to delete
+ * 
+ * RETURNS: integer indicating success or failure.
+ */
+struct raw_tester *
+raw_tester_findid(unsigned id)
+{
+   struct raw_tester * qtester;     /* current entry in queue */
+
+   /* locate the tester in the queue */
+   for (qtester = raw_testerq; 
+        qtester != NULL;
+        qtester = qtester->next)
+      if (qtester->id == id)
+         break;
+
+   /* return pointer to it (or NULL if not found) */
+   return qtester;
+}
+
+/* FUNCTION: raw_testerq_poll()
+ *
+ * Polls all the raw testers for work
+ *
+ * RETURNS: void
+ */
+void
+raw_testerq_poll(void)
+{
+   struct raw_tester * tester;
+   struct raw_tester * nexttester;
+   int len;
+   struct sockaddr_in addr;
+   struct ip * pip;
+   unsigned addrlen;
+   char * dptr;
+   unsigned donedata;
+   int hdrincl;
+   int match;
+   int e;
+
+   /* only proceed if we can lock the tester queue immediately */
+   if (raw_testerq_locked++)
+   {
+      raw_testerq_locked--;
+      return;
+   }
+
+   /* iterate through the testers, checking for work to do */
+   for (tester = raw_testerq; tester != NULL; tester = nexttester)
+   {
+
+      /* keep track of which tester is next,
+       * so we know what to do next 
+       * even if we have to delete the current one due to error
+       */
+      nexttester = tester->next;
+
+      if (tester->sock != INVALID_SOCKET)
+      {
+         do 
+         {
+            /* find out whether the socket has the IP_HDRINCL option set
+             */
+            e = getsockopt(tester->sock, IPPROTO_IP, IP_HDRINCL,
+                           &hdrincl, sizeof(hdrincl));
+            if (e < 0)
+            {
+               ns_printf(tester->pio,
+                         "raw_testerq_poll: [%d] getsockopt error %d\n",
+                         tester->id, t_errno(tester->sock));
+               tester->sending = 0;
+               break;
+            }
+
+            /* check the tester for received data */
+            addrlen = sizeof(addr);
+            len = recvfrom(tester->sock, 
+                           raw_tester_buf, sizeof(raw_tester_buf), 0,
+                           (struct sockaddr *)&addr, &addrlen);
+            if (len < 0)
+            {
+               e = t_errno(tester->sock);
+               if (e != EWOULDBLOCK)
+               {
+                  ns_printf(tester->pio, 
+                            "raw_testerq_poll: [%d] recvfrom() error %d\n",
+                            tester->id, e);
+                  e = raw_tester_del(tester);
+               }
+               break;
+            }
+
+            /* if requested, verify received data
+             * this leaves match set as follows:
+             *   0 if the received data is not verified
+             *   1 if the received data matches what we send
+             *   -1 if the received data does not match what we send
+             */
+            match = 0;
+            if (tester->rxcheck)
+            {
+               dptr = raw_tester_buf;
+               if (hdrincl)
+               {
+                  pip = (struct ip *)dptr;
+                  dptr += (pip->ip_ver_ihl & 0xf) << 2;
+               }
+               donedata = 0;
+               while (dptr < raw_tester_buf + len)
+               {
+                  if (*dptr != (char)(donedata & 0xff))
+                  {
+                     match = -1;
+                     break;
+                  }
+                  dptr++;
+                  donedata++;
+               }
+               if (match == 0)
+                  match = 1;
+            }
+
+            ns_printf(tester->pio,
+                      "raw_testerq_poll: [%d] rcvd %d bytes %sfrom %u.%u.%u.%u\n",
+                      tester->id, len, 
+                      (match > 0) ? "(OK) " : (match < 0) ? "(not OK) " : "",
+                      PUSH_IPADDR(addr.sin_addr.s_addr));
+
+         }
+         while (len > 0);
+
+         /* if tester is sending, and it's time to do the next send...
+          */
+         if ((tester->sending) &&
+             ((tester->sendsdone == 0) ||
+              (cticks - tester->lastsendtime > tester->senddelay)))
+         {
+            dptr = raw_tester_buf;
+
+            if (hdrincl)
+            {
+               /* XXX fill in the IP header */
+               pip = (struct ip *)dptr;
+               dptr += sizeof(struct ip);
+            }
+
+            /* fill the buffer out to the send length with data:
+             * sequence 0, 1, 2, ..., 255, 0, 1, 2, ..., 255 until
+             * we reach the send length
+             * (note that if we built the IP header above its
+             * size is included in the send length!)
+             */
+            donedata = 0;
+            while (dptr - raw_tester_buf < tester->sendlen)
+            {
+               *dptr++ = (char)((donedata++) & 0xff);
+            }
+
+            /* send the buffer 
+             */
+            if (tester->conn && (tester->sendtoaddr == 0))
+            {
+               e = send(tester->sock, raw_tester_buf, tester->sendlen, 0);
+               if (e < 0)
+               {
+                  ns_printf(tester->pio,
+                            "raw_testerq_poll: [%d] send error %d\n",
+                            tester->id, t_errno(tester->sock));
+                  tester->senderr = t_errno(tester->sock);
+                  tester->sending = 0;
+                  continue;
+               }
+            }
+            else
+            {
+               addr.sin_family = AF_INET;
+               addr.sin_port = 0;
+               addr.sin_addr.s_addr = tester->sendtoaddr;
+               e = sendto(tester->sock, raw_tester_buf, tester->sendlen, 0,
+                          (struct sockaddr *)&addr, &addrlen);
+               if (e < 0)
+               {
+                  ns_printf(tester->pio,
+                            "raw_testerq_poll: [%d] sendto error %d (to %u.%u.%u.%u)\n",
+                            tester->id, t_errno(tester->sock),
+                            PUSH_IPADDR(tester->sendtoaddr));
+                  tester->senderr = t_errno(tester->sock);
+                  tester->sending = 0;
+                  continue;
+               }
+            }
+            tester->lastsendtime = cticks;
+            tester->sendsdone++;
+
+            /* if we're done, stop sending
+             */
+            if (tester->sendcount && tester->sendsdone >= tester->sendcount)
+            {
+               tester->sending = 0;
+            }
+         }
+
+      }
+      
+   }
+
+   /* unlock the receiver queue */
+   raw_testerq_unlock();
+}
+
+
+/* FUNCTION: raw_ristart()
+ *
+ * Starts (creates) a new raw IP tester.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_ristart(void * pio)
+{
+   char * arg2;
+   int prot;
+   unsigned id;
+
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires IP protocol ID\n");
+      return -1;
+   }
+   prot = atoi(arg2);
+   if ((prot < 0) || (prot > 255))
+   {
+      ns_printf(pio, "IP protocol ID must be between 0 and 255 inclusive\n");
+      return -1;
+   }
+
+   id = raw_tester_new(pio, prot);
+   if (id < 0)
+   {
+      ns_printf(pio, "unable to create new tester: error %d\n", id);
+      return -1;
+   }
+   ns_printf(pio, "started new tester [%d]\n", id);
+   return 0;
+}
+
+/* FUNCTION: raw_ridelete()
+ *
+ * Deletes a raw IP tester.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_ridelete(void * pio)
+{
+   char * arg2;
+   long lid;
+   unsigned id;
+   int e;
+
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   raw_testerq_lock();
+   e = raw_tester_delid(id);
+   raw_testerq_unlock();
+   if (e < 0)
+   {
+      ns_printf(pio, "unable to delete tester [%d]: error %d\n", id, e);
+      return -1;
+   }
+   ns_printf(pio, "deleted tester [%d]\n", id);
+   return 0;
+}
+
+/* FUNCTION: raw_rilist()
+ *
+ * Displays a list of raw IP testers with state information for each.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_rilist(void * pio)
+{
+   char * arg2;
+   long lid;
+   unsigned id;
+   unsigned listall;
+   struct raw_tester * tester;
+
+   /* figure out whether we're supposed to list a specified ID
+    * or all IDs: all IDs is indicated by the absence of the ID
+    * argument
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      listall = 1;
+#ifdef MUTE_WARNS
+      id = 0;
+#endif /* MUTE_WARNS */
+   }
+   else
+   {
+      listall = 0;
+      lid = atol(arg2);
+      id = (unsigned)lid;
+      if (((long)id) != lid)
+      {
+         ns_printf(pio, "invalid ID %ld\n", lid);
+         return -1;
+      }
+   }
+
+   /* at this point, either listall should be 1 (meaning all IDs
+    * are to be listed) or listall should be 0 and id should be the
+    * ID to be listed
+    */
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* if no testers, say as much; else list appropriately */
+   if (raw_testerq == NULL)
+   {
+      ns_printf(pio, "no raw testers\n");
+   }
+   else
+   {
+      for (tester = raw_testerq; tester != NULL; tester = tester->next)
+      {
+         if (listall || tester->id == id)
+         {
+            ns_printf(pio, "ID %u%c,%ssending (%ld/%ld, err %d)\n",
+                      tester->id, 
+                      ((pio == tester->pio) ? '*' : ' '),
+                      ((tester->sending) ? " " : " not "),
+                      tester->sendsdone,
+                      tester->sendcount,
+                      tester->senderr);
+         }
+      }
+   }
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success */
+   return 0;
+}
+
+/* FUNCTION: raw_risend()
+ *
+ * Tells a tester to begin sending.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_risend(void * pio)
+{
+   char * arg2;
+   char * arg3;
+   char * arg4;
+   long lid;
+   unsigned id;
+   struct raw_tester * tester;
+   unsigned long hostaddr;
+   unsigned hostaddrfound;
+   long sendcount;
+   int e;
+
+   /* get first argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* get optional second and third arguments:
+    *   host address to which to send 
+    *     defaults to activehost for un-connected testers
+    *     defaults to connected address for connected testers
+    *   send count
+    *     defaults to 1
+    *     0 means send forever (or until otherwise stopped)
+    */
+   hostaddrfound = 0;
+   hostaddr = activehost;
+   sendcount = 1;
+   arg3 = nextarg(arg2);
+   arg4 = nextarg(arg3);
+   if (*arg4)
+   {
+      /* there's a third argument, so make sure the second argument
+       * (presumed at this point to be a host address) is null-terminated
+       */
+      arg2 = arg3;
+      while (*arg2 > ' ') 
+         arg2++;
+      *arg2 = 0;
+   }
+
+   /* the second argument (arg3) is either a host address (name or 
+    * IP address) or it's a send count
+    * so we look at it to see if it's all digits -- 
+    * if it's not, then we guess it's a host address
+    * if it is, then we guess it's a send count
+    */
+   if (arg3 && *arg3)
+   {
+      arg2 = arg3;
+      while (*arg2 > ' ')
+      {
+         if (*arg2 > '9' || *arg2 < '0')
+         {
+            e = in_reshost(arg3, &hostaddr, RH_VERBOSE | RH_BLOCK);
+            if (e)
+            {
+               ns_printf(pio, "Unable to resolve host name \"%s\"\n", arg3);
+               return -1;
+            }
+            hostaddrfound = 1;
+            break;
+         }
+         arg2++;
+      }
+      if (*arg2 <= ' ')
+      {
+         sendcount = atol(arg3);
+         if ((sendcount == 0) && (*arg3 != '0'))
+            sendcount = -1;
+      }
+   }
+
+   /* if there's a third argument,
+    * assume it's a send count
+    */
+   if (arg4 && *arg4)
+   {
+      sendcount = atol(arg4);
+      if ((sendcount == 0) && (*arg4 != '0'))
+         sendcount = -1;
+   }
+
+   /* make sure we the host address makes sense
+    */
+   if (hostaddrfound && (hostaddr == 0))
+   {
+      ns_printf(pio, 
+                "specify valid host address, or use default host address\n");
+      return -1;
+   }
+
+   /* make sure the send count makes sense
+    */
+   if (sendcount < 0)
+   {
+      ns_printf(pio, 
+                "last argument must be send count (>= 1)\n");
+      ns_printf(pio,
+                "or 0 to send without limit; default is 1.\n");
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* if the tester is already sending, we will stop this action
+    */
+   if (tester->sending)
+   {
+      ns_printf(pio, "Terminating previous send on ID [%d]\n", id);
+      tester->sending = 0;
+   }
+
+   /* set the tester up to send:
+    * take sendcount from argument
+    * take sendlen and senddelay from globals deflength and pingdelay
+    *   (same as used by ping)
+    * if hostaddr argument present, use it as sendtoaddr;
+    * else let sendtoaddr default:
+    *   if the socket is connected, to the connected address;
+    *   else to global activehost (same as used by ping)
+    */
+   tester->sendcount = sendcount;
+   tester->sendsdone = 0;
+   tester->senderr = 0;
+   if (deflength > sizeof(raw_tester_buf))
+   {
+      ns_printf(pio, "Send length limited to %d bytes\n",
+                id, sizeof(raw_tester_buf));
+      tester->sendlen = sizeof(raw_tester_buf);
+   }
+   else
+      tester->sendlen = deflength;
+   tester->senddelay = pingdelay;
+   if (hostaddrfound)
+      tester->sendtoaddr = hostaddr;
+   else
+   {
+      if (tester->conn)
+         tester->sendtoaddr = 0;
+      else
+         tester->sendtoaddr = activehost;
+   }
+   tester->sending = 1;
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* poll once to get things going */
+   raw_testerq_poll();
+
+   /* and return success */
+   return 0;
+}
+
+/* FUNCTION: raw_rihalt()
+ *
+ * Tells a tester to stop sending.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_rihalt(void * pio)
+{
+   char * arg2;
+   long lid;
+   unsigned id;
+   struct raw_tester * tester;
+
+   /* get argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* if the tester is sending, stop it
+    */
+   if (tester->sending)
+   {
+      ns_printf(pio, "Terminating previous send on ID [%d]\n", id);
+      tester->sending = 0;
+   }
+   else
+   {
+      ns_printf(pio, "ID [%d] not sending\n", id);
+   }
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success */
+   return 0;
+}
+
+/* FUNCTION: raw_ribind()
+ *
+ * Tells a tester to bind to a given IP address.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_ribind(void * pio)
+{
+   char * arg2;
+   char * arg3;
+   long lid;
+   unsigned id;
+   unsigned long bindaddr;
+   struct raw_tester * tester;
+   struct sockaddr_in addr;
+   int e;
+
+   /* get argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* get second argument: host address to bind to (required)
+    */
+   arg3 = nextarg(arg2);
+   if (!arg3 || !*arg3)
+   {
+      ns_printf(pio, "requires host address to bind to\n");
+      return -1;
+   }
+
+   e = in_reshost(arg3, &bindaddr, RH_VERBOSE | RH_BLOCK);
+   if (e)
+   {
+      ns_printf(pio, "Unable to resolve host name \"%s\"\n", arg3);
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* bind the tester's socket to the given address
+    */
+   addr.sin_family = AF_INET;
+   addr.sin_port = 0;
+   addr.sin_addr.s_addr = bindaddr;
+   e = bind(tester->sock, (struct sockaddr *)&addr, sizeof(addr));
+   if (e < 0)
+   {
+      ns_printf(pio, "ID [%d] bind error %d to address %u.%u.%u.%u\n", 
+                id, t_errno(tester->sock), PUSH_IPADDR(bindaddr));
+   }
+   else
+   {
+      ns_printf(pio, "ID [%d] bound to address %u.%u.%u.%u\n", 
+                id, PUSH_IPADDR(bindaddr));
+      e = 0;
+   }
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success/failure */
+   return e;
+}
+
+/* FUNCTION: raw_riconnect()
+ *
+ * Tells a tester to connect to a given IP address.
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_riconnect(void * pio)
+{
+   char * arg2;
+   char * arg3;
+   long lid;
+   unsigned id;
+   unsigned long connaddr;
+   struct raw_tester * tester;
+   struct sockaddr_in addr;
+   int e;
+
+   /* get argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* get second argument: host address to connect to (required)
+    */
+   arg3 = nextarg(arg2);
+   if (!arg3 || !*arg3)
+   {
+      ns_printf(pio, "requires host address to connect to\n");
+      return -1;
+   }
+
+   e = in_reshost(arg3, &connaddr, RH_VERBOSE | RH_BLOCK);
+   if (e)
+   {
+      ns_printf(pio, "Unable to resolve host name \"%s\"\n", arg3);
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* connect the tester's socket to the given address
+    */
+   addr.sin_family = AF_INET;
+   addr.sin_port = 0;
+   addr.sin_addr.s_addr = connaddr;
+   e = connect(tester->sock, (struct sockaddr *)&addr, sizeof(addr));
+   if (e < 0)
+   {
+      ns_printf(pio, "ID [%d] connect error %d to address %u.%u.%u.%u\n", 
+                id, t_errno(tester->sock), PUSH_IPADDR(connaddr));
+   }
+   else
+   {
+      if (connaddr == 0)
+      {
+         ns_printf(pio, "ID [%d] disconnected\n", id);
+         tester->conn = 0;
+      }
+      else
+      {
+         ns_printf(pio, "ID [%d] connected to address %u.%u.%u.%u\n", 
+                   id, PUSH_IPADDR(connaddr));
+         tester->conn = 1;
+      }
+      e = 0;
+   }
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success/failure */
+   return e;
+}
+
+/* FUNCTION: raw_richeck()
+ *
+ * Tells a tester to toggle its "verify received data" setting
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_richeck(void * pio)
+{
+   char * arg2;
+   long lid;
+   unsigned id;
+   struct raw_tester * tester;
+
+   /* get argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* if the tester is verifying received data, stop it; else start
+    */
+   ns_printf(pio, "Turning receive verification %s for ID [%d]\n", 
+             (tester->rxcheck) ? "off" : "on",
+             id);
+   tester->rxcheck = (tester->rxcheck) ? 0 : 1;
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success */
+   return 0;
+}
+
+/* FUNCTION: raw_rihdrincl()
+ *
+ * Tells a tester to toggle its "include IP header" setting
+ *
+ * PARAM1: void * pio; IN- ptr to GEN_IO object for command-line output
+ *
+ * RETURNS: an integer indicating success or failure; 
+ *          zero indicates success; values <0 indicate failure
+ */
+int
+raw_rihdrincl(void * pio)
+{
+   char * arg2;
+   long lid;
+   unsigned id;
+   struct raw_tester * tester;
+   int hdrincl;
+   int optlen;
+   int e;
+
+   /* get argument: tester ID (required) 
+    */
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio, "requires raw IP tester ID\n");
+      return -1;
+   }
+   lid = atol(arg2);
+   id = (unsigned)lid;
+   if (((long)id) != lid)
+   {
+      ns_printf(pio, "invalid ID %ld\n", lid);
+      return -1;
+   }
+
+   /* lock the queue */
+   raw_testerq_lock();
+
+   /* look for the tester */
+   tester = raw_tester_findid(id);
+   if (tester == NULL)
+   {
+      ns_printf(pio, "ID [%d] not found\n", id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* find out whether the socket has the IP_HDRINCL option set
+    */
+   optlen = sizeof(hdrincl);
+   e = getsockopt(tester->sock, IPPROTO_IP, IP_HDRINCL,
+                  &hdrincl, &optlen);
+   if (e < 0)
+   {
+      ns_printf(pio,
+                "getsockopt error %d on ID [%d]\n",
+                t_errno(tester->sock), tester->id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* if the tester is verifying received data, stop it; else start
+    */
+   ns_printf(pio, "Turning IP_HDRINCL %s for ID [%d]\n", 
+             (hdrincl) ? "off" : "on", id);
+   hdrincl = (hdrincl) ? 0 : 1;
+   e = setsockopt(tester->sock, IPPROTO_IP, IP_HDRINCL,
+                  &hdrincl, sizeof(hdrincl));
+   if (e < 0)
+   {
+      ns_printf(pio,
+                "setsockopt error %d on ID [%d]\n",
+                t_errno(tester->sock), tester->id);
+      raw_testerq_unlock();
+      return -1;
+   }
+
+   /* unlock the queue */
+   raw_testerq_unlock();
+
+   /* and return success */
+   return 0;
+}
+
+#ifdef IN_MENUS
+/* raw_tester_menu[] - NicheTool command menu for raw IP testing
+ */
+struct menu_op raw_tester_menu[] =
+{
+   "rawiptest",   stooges,       "menu to control raw IP testing",
+   "ristart",     raw_ristart,   "start a raw IP tester",
+   "ridelete",    raw_ridelete,  "delete a raw IP tester",
+   "rilist",      raw_rilist,    "list raw IP testers",
+   "risend",      raw_risend,    "tell a raw IP tester to start sending",
+   "rihalt",      raw_rihalt,    "tell a raw IP tester to stop sending",
+   "ribind",      raw_ribind,    "bind a raw IP tester to a host address",
+   "riconnect",   raw_riconnect, "connect a raw IP tester to a host address",
+   "richeck",     raw_richeck,   "toggle receive data verification",
+   "rihdrincl",   raw_rihdrincl, "toggle IP_HDRINCL socket option",
+   NULL,
+};
+#endif /* IN_MENUS */
+
+/* FUNCTION: raw_test_init()
+ * 
+ * Initialize for raw IP testing operations. Presently this function adds
+ * the raw IP testing menu.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0
+ */
+int
+raw_test_init(void)
+{
+#ifdef IN_MENUS
+   install_menu(raw_tester_menu);
+#endif /* IN_MENUS */
+   return 0;
+}
+
+#endif      /* RAWIPTEST */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/reshost.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/reshost.c
new file mode 100644
index 0000000..4c0a6f7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/reshost.c
@@ -0,0 +1,127 @@
+/*
+ * FILENAME: reshost.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Mid level API for DNS resolutions.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: in_reshost(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software */
+
+
+#include "ipport.h"
+#include "netbuf.h"
+#include "net.h"
+
+#include "in_utils.h"
+
+#include "dns.h"      
+
+
+
+
+/* FUNCTION: in_reshost()
+ *
+ * in_reshost(char addr, ip_addr result, int flags) Resolve an IP 
+ * address text string into an actual IP address. Calls DNS if 
+ * supported. flags word is a bit mask of the RH_ values in dns.h 
+ * Returns 0 if address was set, else one of the ENP_ error codes 
+ *
+ * 
+ * PARAM1: char * host     - IN - textual IP address or host name
+ * PARAM2: ip_addr * address - OUT - address if successful
+ * PARAM3: int    flags    - IN - RH_VERBOSE, RH_BLOCK
+ *
+ * RETURNS: 
+ */
+
+int
+in_reshost(char * host, /* IN - textual IP address or host name */
+   ip_addr *   address, /* OUT - address if successful */
+   int   flags)         /* IN - RH_VERBOSE, RH_BLOCK */
+{
+   char *   cp;      /* error holder */
+   unsigned snbits;  /* for pass to parse_ipad() */
+#ifdef DNS_CLIENT
+   int   e;          /* Net error code */
+   u_long   tmo;     /* timeout for blocking calls */
+   int   blocking =  flags &  RH_BLOCK;
+#endif   /* DNS_CLIENT */
+   int   verbose  =  flags &  RH_VERBOSE;
+
+   cp = parse_ipad(address, &snbits, host);
+
+   if (!cp) /* worked, string was parsable dot notation */
+      return 0;
+
+#ifndef DNS_CLIENT
+   if (verbose)
+      dprintf("Unable to parse IP host %s.\nerror: %s\n", host, (char*)cp);
+   return ENP_PARAM;
+#else /* DNS_CLIENT enabled in build */
+
+   if (verbose)
+      dprintf("can't parse %s (%s), trying DNS\n", host, cp);
+
+   tmo = cticks + (5 * TPS);  /* set timeout value */
+
+   if (dns_servers[0])  /* dont bother if no servers are set */
+   {
+      if (verbose)
+         dprintf("trying DNS lookup...\n");
+      e = dns_query(host, address);
+      if (e == ENP_SEND_PENDING)
+      {
+         if (blocking)
+         {
+            while (tmo > cticks)
+            {
+               tk_yield();
+               e = dns_query(host, address);
+               if (e == 0)
+                  goto rh_got_dns;
+            }
+         }
+         if (verbose)
+            dprintf("DNS inquiry sent\n");
+         return 0;
+      }
+      else if(e == 0)
+      {
+         rh_got_dns:
+         /* DNS resolution worked */
+         if (verbose)
+            dprintf("active host found via DNS (%u.%u.%u.%u)\n", 
+          PUSH_IPADDR(*address));
+         return 0;
+      }
+      else if(e == ENP_TIMEOUT)  /* timeout? */
+      {
+         if (verbose)
+            dprintf("DNS timeout");
+      }
+      else
+      {
+         if (verbose)
+            dprintf("DNS error %d", e);
+      }
+      if (verbose)
+         dprintf(", host not set\n");
+      return e;
+   }
+
+   if (verbose)
+      dprintf("DNS/host-parse failed.\n");
+   return ENP_PARAM;
+#endif   /* DNS_CLIENT */
+}
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rfsim.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rfsim.c
new file mode 100644
index 0000000..dacbc08
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rfsim.c
@@ -0,0 +1,249 @@
+/*
+ * FILENAME: rfsim.c
+ *
+ * Copyright  2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Code to simulate wireless networks by adding a controlled latency and
+ * loss rate to routed packets. Target startup code should call sim_init()
+ * to ready this for use.
+ *
+ * So far this has only been used on MPC860 builds, using the FADS 860T
+ * with two 10Mbs ethernets.
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: In Theory
+ */
+
+
+#include "ipport.h"
+
+
+#ifdef RF_SIMULATION
+
+#ifndef INICHE_TIMERS
+#error rfsim requires INICHE_TIMERS
+#endif
+
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "menu.h"
+
+int      rfsim_routing;   /* Bool, TRUE if we're doing this */
+u_long   sim_latency;      /* Ave time to hold pkt, in TPS.  */
+
+static int  lossrate;      /* loss will be 1 in rate pkts */
+static int  deviation;     /* deviation in loss rate */
+
+u_long simpkts;
+u_long simdrops;
+u_long simlastloss;
+
+/* The rfsim menu routines */
+int   simstart(void *);
+int   simquit(void *);
+int   simtime(void *);
+int   simstat(void *);
+int   simloss(void *);
+void  rfsim_timer(void);
+
+struct menu_op sim_menu[] = {
+   "rfsim",   stooges,    "RF simulation",      /* menu ID */
+   "simstart", simstart,   "start the routing delay",
+   "simquit",  simquit,    "stop the routing delay",
+   "simtime",  simtime,    "set the sim time (in ms)",
+   "simloss",  simloss,    "set/clear sim loss rate (1 in n)",
+   "simdump",  simstat,    "dump sim stats",
+   NULL, NULL, NULL
+};
+
+long  simtimer;
+queue simq;
+
+/* sim_init(0 - called to set up the rfsim system */
+
+int
+sim_init()
+{
+   int err;
+   err = install_menu(sim_menu);
+   if(err)
+      return err;
+
+   return 0;
+}
+
+/* rfsim_send() - called from IP routing to send packets when
+ * the global rfsim_routing flag is TRUE.
+ */
+
+int
+rfsim_send(void * vpkt, u_long firsthop)
+{
+   PACKET pkt;
+
+   pkt = (PACKET)vpkt;
+   
+   /* set time to eventually send the pkt */
+   pkt->nb_tstamp = cticks + sim_latency;
+
+   /* hijack the fhost field to hold the IP address */
+   pkt->fhost = (ip_addr)firsthop;
+   putq(&simq, (qp)pkt);
+   return 0;
+}
+
+void
+rfsim_timer()
+{
+   ip_addr     hop;
+   struct ip * pip;
+   PACKET      pkt;
+
+   /* send al packets which have timed out */
+   while(((PACKET)(simq.q_head))->nb_tstamp < cticks)
+   {
+      pkt = (PACKET)getq(&simq); /* get pkt to send */
+      hop = pkt->fhost;          /* get hop from host field */
+      pip = ip_head(pkt);        /* get real host address */
+      pkt->fhost = pip->ip_dest; /* restore host field */
+      simpkts++;
+
+      /* see if it's time to drop a packet */
+      if((lossrate) && 
+         ((simpkts - simlastloss) > lossrate) && 
+         ((cticks & deviation) == 1))
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);           /* drop instead of send */
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         simlastloss = simpkts;  /* reset drop timer */
+         simdrops++;             /* count drops */
+      }
+      else
+         ip2mac(pkt, hop);          /* send pkt to hardware */
+   }
+   return;
+}
+
+int
+simstart(void * pio)
+{
+   simtimer = in_timerset(rfsim_timer, 20);
+   if(simtimer == 0)
+      return ENP_RESOURCE;
+
+   ns_printf(pio, "rfsim slowdown active, latency is %d ticks.\n",
+      sim_latency);
+   rfsim_routing = TRUE;
+   simpkts = simlastloss = simdrops = 0;
+   return 0;
+}
+
+
+int
+simquit(void * pio)
+{
+   PACKET   pkt;
+   ip_addr  hop;
+   struct ip * pip;
+   
+   if(simtimer)
+   {
+      in_timerkill(simtimer);
+      simtimer = 0;
+   }
+
+   /* send all queued packets */
+   while(simq.q_head)
+   {
+      pkt = (PACKET)getq(&simq); /* get pkt to send */
+      hop = pkt->fhost;          /* get hop from host field */
+      pip = ip_head(pkt);        /* get real host address */
+      pkt->fhost = pip->ip_dest; /* restore host field */
+      ip2mac(pkt, hop);          /* send pkt to hardware */
+   }
+   rfsim_routing = FALSE;
+   ns_printf(pio, "rfsim stopped\n");
+   return 0;
+}
+
+
+int
+simtime(void * pio)
+{
+   char *   arg;
+   long     msecs;
+
+   arg = nextarg(((GEN_IO)pio)->inbuf);
+   msecs = atol(arg);
+   if(msecs == 0)
+   {
+      ns_printf(pio, "To set latency to 0 just shut sim off\n");
+      return 0;
+   }
+   sim_latency = (msecs * TPS)/1000;
+   ns_printf(pio, "SIM Latency now %d ms. (%d ticks)\n", msecs, sim_latency);
+
+   return 0;
+}
+
+int
+simstat(void * pio)
+{
+   ns_printf(pio, "rfsim %sactive, latency is %d ticks.\n",
+      rfsim_routing?"":"in", sim_latency);
+
+   ns_printf(pio, "rfsim queue; current:%ld, max:%ld\n",
+      simq.q_len, simq.q_max);
+
+   ns_printf(pio, "pkts delayed: %ld, dropped: %ld,  drop rate: %d in %d\n",
+      simpkts, simdrops, lossrate?1:0, lossrate);
+
+   return 0;
+}
+
+
+int
+simloss(void * pio)
+{
+   char *   arg;
+   int      rate;
+
+   arg = nextarg(((GEN_IO)pio)->inbuf);
+   if(arg == NULL || *arg == 0)
+   {
+      ns_printf(pio, "lossrate is %d in %d; enter new rate (1 in 'rate') to change\n",
+         lossrate?0:1, lossrate);
+      return 0;
+   }
+   rate = atoi(arg);
+
+   if(rate == 0 && *arg != '0')
+   {
+      ns_printf(pio, "Please enter a number.\n");
+      return -1;
+   }
+   lossrate = rate;     /* set rate of loss */
+
+   /* set deviation mask for loss */
+   if(lossrate < 11)
+      deviation = 0x01;
+   else if(lossrate < 30)
+      deviation = 0x03;
+   else if(lossrate < 101)
+      deviation = 0x07;
+   else if(lossrate < 1000)
+      deviation = 0x01f;
+
+   ns_printf(pio, "lossrate set to 1 in %d packets\n",
+      lossrate);
+
+   return 0;
+}
+
+#endif   /* RF_SIMULATION */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rttest.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rttest.c
new file mode 100644
index 0000000..f2ef6b4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/rttest.c
@@ -0,0 +1,744 @@
+/*
+ * FILENAME: rttest.c
+ *
+ * Copyright  2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Pseudo driver for speed testing routing & routing and 
+ * NAT. This works by by installing itself as an InterNiche MAC 
+ * driver which allows the user to generate IP or NAT routing 
+ * traffic. 
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: rt_help(), rtcreate_device(), rt_init(), 
+ * ROUTINES: rt_pkt_send(), rt_close(), rt_reg_type(), rt_stats(), rt_send(), 
+ * ROUTINES: nt_send(), rt_setprot(), rt_statistics(), rt_startup(), rt_done(),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef ROUTE_TEST    /* Whole file can be ifdeffed */
+
+#ifndef IP_ROUTING
+#error Must define IP_ROUTING to use ROUTE_TEST
+#endif   /* IP_ROUTING */
+
+#ifndef DYNAMIC_IFACES
+#error Must define DYNAMIC_IFACES to use ROUTE_TEST
+#endif   /* DYNAMIC_IFACES */
+
+#ifdef NATRT
+#include "../natrt/natport.h"
+#endif /* NATRT */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+#include "udp.h"
+#include "tcp.h"
+
+#include "nvparms.h"
+#include "menu.h"
+
+NET      nt_ifp;     /* this driver (the creatyed test driver) */
+int      lb_index;   /* index of loopback iface */
+int      rt_index;   /* index of this test iface */
+
+int   rtdrv_prep(int ifaces);
+
+int   rt_init(int iface);           /* net initialization routine */
+int   rt_pkt_send(struct netbuf *); /* send packet on media */
+int   rt_close(int  iface);         /* net close routine */
+int   rt_reg_type(unshort type, struct net*);   /* register a MAC type */
+void  rt_stats(void * pio, int iface);   
+
+struct nt_stats   {
+   long  udp_pkts_sent;
+   long  udp_bytes_sent;
+   long  tcp_pkts_sent;
+   long  tcp_bytes_sent;
+   long  udp_pkts_recv;
+   long  udp_bytes_recv;
+   long  tcp_pkts_recv;
+   long  tcp_bytes_recv;
+   long  other_pkts;
+};
+
+struct nt_stats   ntstat;
+
+int rt_send(void * pio);
+int rt_startup(void * pio);
+int rt_done(void * pio);
+int nt_send(void * pio);
+int rt_setprot(void * pio);
+int rt_statistics(void * pio);
+int rt_help(void * pio);
+
+struct menu_op rt_menu[]   =
+{
+   "rtest",    stooges,          "Route test",      /* menu ID */
+   "rstart",   rt_startup,       "Create route test device",
+   "rdone",    rt_done,          "Delete route test device",
+   "rsend",    rt_send,          "send packets through route code",
+#ifdef NATRT
+   "nsend",    nt_send,          "send packets through Nat",
+#endif
+   "rprot",    rt_setprot,       "set route test protocol (tcp or udp)",
+   "rstat",    rt_statistics,    "show/clear route route test statistics",
+   "rthelp",   rt_help,          "help with route TEST",
+   NULL, 0, NULL,
+};
+
+
+
+/* FUNCTION: rt_help()
+ * 
+ * menu routine
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+rt_help(void * pio)
+{
+   ns_printf(pio, "Use \"rstart\" to create a test iface first, then:\n");
+   ns_printf(pio, "\"rsend\" to start a packet burst through router\n");
+   ns_printf(pio, "\"nsend\" to start a packet burst through NAT\n");
+   ns_printf(pio, "\"rstat\" to display the resulting statstics\n");
+   ns_printf(pio, "\"rstat 0\" to reset statistics\n");
+   ns_printf(pio, "\"rprot\" to set protocol as 6(TCP) or 17(UDP)\n");
+   ns_printf(pio, "\"length\" to set length of test packets\n");
+   ns_printf(pio, "\"rdone\" to delete the test iface\n");
+   return 0;
+}
+
+char *   nat_mac  = "RTRTST";    /* fake MAC address */
+
+u_char   ntprot   =  6;       /* protocol of test pkts, 6==tcp, 17==udp */
+u_short  nt_sport =  1200; /* source and dest ports */
+u_short  nt_dport =  80;
+ip_addr   nt_srcaddr;
+ip_addr   nt_destaddr;
+
+extern   int      deflength;     /* use ping packet length */
+extern   void     ip_bldhead(PACKET p, 
+   unsigned pid, u_char prot, unshort fragword);
+extern   void     nat_re_init(void);
+
+static  int    save_nat_inet;
+static  int    save_nat_localnet;
+
+/* test driver routines */
+
+/* FUNCTION: rtcreate_device()
+ * 
+ * the "ni_create()" entry to create a dynamic rttest device.
+ * 
+ * PARAM1: NET ifp
+ * PARAM2: void * bindinfo
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rtcreate_device(NET ifp, void * bindinfo)
+{
+   USE_VOID(bindinfo);
+
+   /* set up  an InterNiche net structure for a fake ethernet interface */
+   ifp->n_lnh = ETHHDR_SIZE;        /* space reserved for ethernet header */
+   ifp->n_hal = 6;                  /* hardware address length */
+   ifp->n_mtu = 1514;               /* max frame size */
+   ifp->n_mib->ifAdminStatus = 2;   /* status = down */
+   ifp->n_mib->ifOperStatus = 2;    /* will be set up in init()  */
+   ifp->n_mib->ifLastChange = cticks * (100/TPS);
+   ifp->n_mib->ifType = ETHERNET;
+   ifp->n_mib->ifDescr = (u_char*)"Routing/NAT test driver";
+   ifp->n_mib->ifPhysAddress = (u_char*)nat_mac;
+
+   /* install our virtual driver routines */
+   ifp->n_init = rt_init;
+   ifp->pkt_send = rt_pkt_send;
+   ifp->n_close = rt_close;
+   ifp->n_stats = rt_stats;
+   ifp->n_reg_type = rt_reg_type;
+
+   /* set a custom name for ndis device */
+   ifp->name[0] = 'r';
+   ifp->name[1] = 't';
+   ifp->name[2] = 's';
+
+#ifdef INCLUDE_NVPARMS   /* only if using NV parms */
+   /* search the NV parameters for iface setup for our name. If this
+    * fails we just default to what's already in the ifp.
+    */
+   if_configbyname(ifp);
+#endif   /* INCLUDE_NVPARMS */
+
+   nt_ifp = ifp;     /* save our iface for later use */
+
+   rt_index = if_netnumber(nt_ifp);    /* get numeric index */
+
+   return(rt_init(rt_index));
+}
+
+
+/* interface initialization routine */
+
+
+
+/* FUNCTION: rt_init()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS:  0 if OK or an ENP error code
+ */
+
+int
+rt_init(int iface)
+{
+   if (nets[iface] != nt_ifp)
+   {
+      dtrap(); /* serious code error */
+      return ENP_LOGIC;
+   }
+   return 0;
+}
+
+
+
+
+
+/* FUNCTION: rt_pkt_send()
+ * 
+ * MAC interface send packet call for test device. In this case
+ * it is called whenever a packet sent from this device has been
+ * routed through the loopback driver and back to this interface.
+ * All we need to do is count them and free the buffer.
+ *
+ * PARAM1: struct netbuf * pkt
+ *
+ * RETURNS:  0 if OK or an ENP error code
+ */
+
+int
+rt_pkt_send(struct netbuf * pkt)
+{
+   struct ip * pip;
+   struct IfMib * mib;
+
+   pip = (struct ip *)(pkt->nb_prot + ETHHDR_SIZE);
+
+   if (pip->ip_prot == 6)
+   {
+      ntstat.tcp_pkts_recv++;
+      ntstat.tcp_bytes_recv += pkt->nb_plen;
+   }
+   else if(pip->ip_prot == 17)
+   {
+      ntstat.udp_pkts_recv++;
+      ntstat.udp_bytes_recv += pkt->nb_plen;
+   }
+   else
+   {
+      ntstat.other_pkts++;
+   }
+
+   mib = nt_ifp->n_mib;
+   mib->ifOutOctets += pkt->nb_plen;
+   mib->ifOutUcastPkts++;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(pkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: rt_close()
+ * 
+ * PARAM1: int  iface
+ *
+ * RETURNS:   0 if OK or an ENP error code
+ */
+
+int
+rt_close(int  iface)
+{
+   USE_ARG(iface);
+   return 0;
+}
+
+
+/* FUNCTION: rt_reg_type()
+ * 
+ * register a MAC type - no-op on this device.
+ *
+ * PARAM1: unshort type
+ * PARAM2: struct net * ifp
+ *
+ * RETURNS:   0 if OK or an ENP error code
+ */
+
+int
+rt_reg_type(unshort type, struct net * ifp)
+{
+   USE_ARG(type);
+   USE_ARG(ifp);
+   return 0;
+}
+
+
+
+
+/* FUNCTION: rt_stats()
+ * 
+ * PARAM1: void * pio
+ * PARAM2: int iface
+ *
+ * RETURNS: void
+ */
+
+void
+rt_stats(void * pio, int iface)
+{
+   rt_statistics(pio);
+   USE_ARG(iface);
+}
+
+
+/* NAT test menu routines */
+
+#define  TESTIP      1
+#define  TESTNAT     2
+
+static int rttest = TESTNAT;
+
+
+
+/* FUNCTION: rt_send()
+ *
+ * Menu routine to generate the stream of test packets into the IP code. This is
+ * just a wrapper which sets a flag and call nt_send().
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rt_send(void * pio)
+{
+   int   err;
+
+#ifdef NATRT
+   /* Since test defaults to NAT, we have to unNAT it here. */
+   /* stuff the indexes into nvparms structure */
+   natrt_nvparms.nat_inet = save_nat_inet;
+   natrt_nvparms.nat_localnet = save_nat_localnet;
+   nat_re_init();       /* restart NAT with original ifaces */
+#endif   /* NATRT */
+
+   rttest = TESTIP;     /* set for IP */
+   err = nt_send(pio);
+   rttest = TESTNAT;
+
+#ifdef NATRT
+   /* stuff the indexes into nvparms structure */
+   natrt_nvparms.nat_inet = lb_index;
+   natrt_nvparms.nat_localnet = rt_index;
+   nat_re_init();       /* restart NAT with original ifaces */
+#endif   /* NATRT */
+
+   return err;
+}
+
+
+
+
+/* FUNCTION: nt_send()
+ * 
+ * Menu routine to generate the stream of test packets into the IP or
+ * NAT code.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+nt_send(void * pio)
+{
+   int      count;      /* number of test packets to generate */
+   u_long   timer;      /* speed timer for statstics */
+   u_long   pkts;       /* local counters for speed test */
+   u_long   bytes;
+   u_long   timeout;    /* timeout for stuck systems */
+   PACKET   master;
+   PACKET   tmp;
+   struct ethhdr *   eth;
+   struct ip *       pip;
+   struct tcphdr *   ptcp;
+   int      ipid  =  0; /* IP header ID for sent packets */
+   char *   arg   =  nextarg( ((GEN_IO)pio)->inbuf );
+   struct arptabent *   arp;
+
+   count = atol(arg);
+   if (count < 1)
+   {
+      ns_printf(pio, "usage: rtsend|ntsend count (count is number >1)\n");
+      return -1;
+   }
+
+   if (deflength > 1506)
+   {
+      ns_printf(pio, "oversize length (%d) - max test length is 1506\n",
+       deflength);
+      return -1;
+   }
+   if (nt_ifp == NULL)
+   {
+      ns_printf(pio, "Create device with rstart first.\n");
+      return -1;
+   }
+
+   /* make ARP table entries for both target IP addresses - the one 
+    * on the loopback iface, and this one. We test for arp creation,
+    * but don't waste message on it since it's fantisticly unlikely.
+    */
+   arp = make_arp_entry(nt_destaddr, nets[lb_index]);
+   if (arp == NULL)
+      return ENP_RESOURCE;
+   MEMCPY(arp->t_phy_addr, "LPBACK", 6);
+   arp = make_arp_entry(nt_srcaddr, nt_ifp);
+   if (arp == NULL)
+      return ENP_RESOURCE;
+   MEMCPY(arp->t_phy_addr, nat_mac, 6);
+
+   ns_printf(pio, "%s test: starting send of %ld pkts, %d bytes each...",
+    (rttest == TESTIP)?"Route":"NAT", count, deflength);
+
+   /* build template send packet */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   master = pk_alloc(deflength);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (master == NULL)
+   {
+      dprintf("Can't get a buffer for %d bytes\n", deflength);
+      return -1;
+   }
+
+   eth = (struct ethhdr*)(master->nb_buff + ETHHDR_BIAS);
+   eth->e_type = htons(0x0800);     /* put IP packet type in header & pkt */
+
+   master->nb_prot = master->nb_buff + sizeof(struct ip) + ETHHDR_SIZE;
+   master->nb_plen = deflength - (sizeof(struct ip) + ETHHDR_SIZE);
+   ip_bldhead(master, ipid, ntprot, 0);
+   pip = (struct ip *)master->nb_prot;
+
+   pip->ip_src = nt_srcaddr;
+   pip->ip_dest = nt_destaddr;
+
+   /* set the port numbers as though pkt is TCP. This will also work 
+    * for UDP since UDPs port numbers happen to be at the same offsets.
+    */
+   ptcp = (struct tcphdr *)(pip + 1);
+   ptcp->th_dport = htons(80);
+   ptcp->th_sport = htons(1200);
+
+   master->nb_prot += ETHHDR_SIZE;  /* ignore ether header */
+
+   if (rttest != TESTIP)
+   {
+   }
+
+   /* record starting counts in the iface MIB */
+   pkts = nt_ifp->n_mib->ifOutUcastPkts;
+   bytes = nt_ifp->n_mib->ifOutOctets;
+
+   timer = cticks;      /* note start time */
+   while (count--)
+   {
+      timeout = cticks + TPS;
+      while (bigfreeq.q_len < (bigfreeq.q_max/4))
+      {
+         tk_yield();
+         if (timeout < cticks)
+         {
+            ns_printf(pio, "timeout waiting for buffers, Aborting...\n");
+            break;
+         }
+      }
+
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      tmp = pk_alloc(deflength);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      if (tmp == NULL)
+      {
+         ns_printf(pio, "error - ran out of buffers!!! Aborting...\n");
+         break;
+      }
+
+      MEMCPY(tmp->nb_buff, master->nb_buff, 54);
+
+      tmp->type = 0x0800;
+      tmp->nb_prot = tmp->nb_buff + ETHHDR_SIZE;
+      tmp->nb_plen = master->nb_plen;
+      pip = (struct ip *)tmp->nb_prot;
+      pip->ip_id = ipid++;
+      pip->ip_chksum = 0;
+      pip->ip_chksum = ~cksum(pip, ip_hlen(pip) >> 1);
+
+      /* packet is ready. We want it to look like it came from a 
+       * private net and is to be NAT routed to the modified MAC 
+       * loopback driver, which will swap the IP addersses and port
+       * and send it back for a return trip to us. To do this we
+       * simple insert it in the reced queue
+       */
+      tmp->net = nt_ifp;
+      putq(&rcvdq, (qp)tmp);
+      SignalPktDemux();
+   }
+
+   /* conver start time and count to delta time and counts */
+   timer = cticks - timer;
+   pkts = nt_ifp->n_mib->ifOutUcastPkts - pkts;
+   bytes = nt_ifp->n_mib->ifOutOctets - bytes;
+
+   /* pretty-print results */
+   ns_printf(pio, "\nDone, %ld and %ld/%d seconds.\n",
+                  timer/TPS, timer % TPS, TPS);
+
+   if (timer > 0) /* avoid divide by zero, CPUs hate that... */
+   {
+      ns_printf(pio, "speed %ld pkts/sec round trip, %ld bytes/sec\n", 
+                     (pkts/timer) * TPS, (bytes/timer) * TPS);
+      ns_printf(pio, "or %ld pkts/sec one way.\n", 
+                     (pkts/timer) * TPS * 2);
+   }
+
+   /* don't forget to free the 'master' packet */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(master);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: rt_setprot()
+ * 
+ * Menu routine to set type type of test packet - TCP or UDP.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rt_setprot(void * pio)
+{
+   int   newprot;
+   char *   arg   =  nextarg(cbuf);
+
+   newprot = atoi(arg);
+
+   if (newprot == 6)
+      ns_printf(pio, "setting Nat test prot to TCP\n");
+   else if(newprot == 17)
+      ns_printf(pio, "setting Nat test prot to UDP\n");
+   else
+   {
+      ns_printf(pio, "protocol must be 6 (TCP) or 17 (UDP)\n");
+      return -1;
+   }
+
+   ntprot = (u_char)newprot;
+   return 0;
+}
+
+
+
+/* FUNCTION: rt_statistics()
+ * 
+ * Menu routine to dump or clear stats.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rt_statistics(void * pio)
+{
+   char *   arg   =  nextarg(cbuf);
+
+   if (arg && (*arg == '0'))
+   {
+      ns_printf(pio, "Clearing NAT test stats to zero\n");
+      ntstat.udp_pkts_sent = 0;
+      ntstat.udp_bytes_sent = 0;
+      ntstat.tcp_pkts_sent = 0;
+      ntstat.tcp_bytes_sent = 0;
+      ntstat.udp_pkts_recv = 0;
+      ntstat.udp_bytes_recv = 0;
+      ntstat.tcp_pkts_recv = 0;
+      ntstat.tcp_bytes_recv = 0;
+      ntstat.other_pkts = 0;
+      return 0;
+   }
+
+   ns_printf(pio, "TCP sent; pkts: %ld bytes: %ld\n",
+    ntstat.tcp_pkts_sent,
+    ntstat.tcp_bytes_sent);
+   ns_printf(pio, "TCP recv; pkts: %ld bytes: %ld\n",
+    ntstat.tcp_pkts_recv,
+    ntstat.tcp_bytes_recv);
+   ns_printf(pio, "UDP sent; pkts: %ld bytes: %ld\n",
+    ntstat.udp_pkts_sent,
+    ntstat.udp_bytes_sent);
+   ns_printf(pio, "UDP recv; pkts: %ld bytes: %ld\n",
+    ntstat.udp_pkts_recv,
+    ntstat.udp_bytes_recv);
+
+   ns_printf(pio, "Other pkts received %ld\n", ntstat.other_pkts);
+
+
+   return 0;
+}
+
+
+
+/* FUNCTION: rt_startup()
+ * 
+ * Menu routine to create the dynamic device which generates the IP or
+ * NAT test traffic.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rt_startup(void * pio)
+{
+   int      err;
+   NET      tmp;
+   ip_addr  tmpip;
+   struct niconfig_0 cfg;
+
+   if (nt_ifp != NULL)
+   {
+      ns_printf(pio, "rt test aaalready has device\n");
+      return 0;
+   }
+
+   err = ni_create(&tmp, rtcreate_device, "rt0", NULL);
+   if (err || (tmp != nt_ifp))
+   {
+      ns_printf(pio, "rt test:error %d creating test device\n", err);
+      return -1;
+   }
+
+   /* set up the new ifaces IP address and subnet mask */
+   cfg.n_ipaddr = htonl(0xc0a40001);
+   cfg.snmask = htonl(0xFFFF0000);
+   err = ni_set_config(tmp, &cfg);
+   if (err)
+   {
+      ns_printf(pio, "rt test device config error %d\n", err);
+      return -1;
+   }
+
+   /* make a source address on the local net */
+   tmpip = htonl(nt_ifp->n_ipaddr);       /* start with out local address */
+   tmpip++;          /* add 1 - make it not our address */
+   nt_srcaddr = htonl(tmpip);
+
+   nt_destaddr = htonl(0x7f000002);       /* set dest addr */
+
+   /* verify there is a loopback iface & keep it's index */
+   for (lb_index = 0; lb_index < (int)ifNumber; lb_index++)
+   {
+      if (nets[lb_index]->n_ipaddr == htonl(0x7f000001))
+         break;
+   }
+   if (lb_index >= (int)ifNumber)
+   {
+      dprintf("NAT test: Error; need loopback interface\n");
+      return ENP_LOGIC;
+   }
+
+#ifdef NATRT
+   /*
+    * Set NAT up with this device as the private net and the
+    * loopback device as a public net.
+    */
+   save_nat_inet = natrt_nvparms.nat_inet;      /* Save nvparms entries */
+   save_nat_localnet = natrt_nvparms.nat_localnet;
+   /* stuff the indexes into nvparms structure */
+   natrt_nvparms.nat_inet = lb_index;
+   natrt_nvparms.nat_localnet = rt_index;
+   nat_re_init();       /* restart NAT with test ifaces */
+#endif   /* NATRT */
+
+   ns_printf(pio, "rt test device ready.\n   device IP %u.%u.%u.%u.\n",
+    PUSH_IPADDR(nt_ifp->n_ipaddr) );
+   ns_printf(pio, "   Pkt source address: %u.%u.%u.%u\n",
+    PUSH_IPADDR(nt_srcaddr));
+   ns_printf(pio, "   dest address: %u.%u.%u.%u\n",
+    PUSH_IPADDR(nt_destaddr));
+
+   return 0;
+}
+
+
+
+/* FUNCTION: rt_done()
+ * 
+ * Menu routine to delete the dynamic device which generates the IP or
+ * NAT test traffic.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 if OK or an ENP error code
+ */
+
+int
+rt_done(void * pio)
+{
+   int   err;
+
+#ifdef NATRT
+   /* Restore the original NAT device proior ot installing this test */
+   /* stuff the indexes into nvparms structure */
+   natrt_nvparms.nat_inet = lb_index;
+   natrt_nvparms.nat_localnet = rt_index;
+   nat_re_init();       /* restart NAT with original ifaces */
+#endif   /* NATRT */
+
+   err = ni_delete(nt_ifp);
+   if (err)
+   {
+      ns_printf(pio, "rt test device delete error %d\n", err);
+      return -1;
+   }
+   nt_ifp = NULL;
+   return 0;
+}
+
+#endif   /* ROUTE_TEST */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/soperr.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/soperr.c
new file mode 100644
index 0000000..2816ba2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/soperr.c
@@ -0,0 +1,77 @@
+/*
+ * FILENAME: soperror.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * soperror.c Implement a "perror()" like function for InterNiche 
+ * sockets errors 
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: so_perror(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"     /* NetPort embedded system includes */
+
+#ifdef INCLUDE_TCP
+#ifndef MINI_TCP        /* not for NicheLite */
+ 
+#include "tcpport.h"
+
+char *   so_emessages[] =
+{
+   "",               /*  0 */
+   "ENOBUFS",        /*  1 */
+   "ETIMEDOUT",      /*  2 */
+   "EISCONN",        /*  3 */
+   "EOPNOTSUPP",     /*  4 */
+   "ECONNABORTED",   /*  5 */
+   "EWOULDBLOCK",    /*  6 */
+   "ECONNREFUSED",   /*  7 */
+   "ECONNRESET",     /*  8 */
+   "ENOTCONN",       /*  9 */
+   "EALREADY",       /* 10 */
+   "EINVAL",         /* 11 */
+   "EMSGSIZE",       /* 12 */
+   "EPIPE",          /* 13 */
+   "EDESTADDRREQ",   /* 14 */
+   "ESHUTDOWN",      /* 15 */
+   "ENOPROTOOPT",    /* 16 */
+   "EHAVEOOB",       /* 17 */
+   "ENOMEM",         /* 18 */
+   "EADDRNOTAVAIL",  /* 19 */
+   "EADDRINUSE",     /* 20 */
+   "EAFNOSUPPORT",   /* 21 */
+   "EINPROGRESS",    /* 22 */
+   "ELOWER",         /* 23  lower layer (IP) error */
+};
+
+
+/* FUNCTION: so_perror()
+ *
+ * so_perror() - return a pointer to a static string which is a short 
+ * mnemonic for the socket error message. 
+ *
+ * 
+ * PARAM1: int ecode
+ *
+ * RETURNS: error text string
+ */
+
+char *   
+so_perror(int ecode)
+{
+   if (ecode < (sizeof(so_emessages)/sizeof(char*)))
+      return(so_emessages[ecode]);
+   else
+      return "";
+}
+
+#endif   /*  MINI_TCP */
+#endif   /* INCLUDE_TCP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strilib.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strilib.c
new file mode 100644
index 0000000..e6c74b1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strilib.c
@@ -0,0 +1,142 @@
+/*
+ * FILENAME: strilib.c
+ *
+ * Copyright 1998-2003 By InterNiche Technologies Inc. All rights reserved
+ *
+ * The file contains source for Common but not quite 
+ * universal C library string functions. These are used by the http 
+ * server, emailer, and perhaps others. This file has implementation 
+ * for three functions, each of which can be enabled at compile time 
+ * with a switch. INICHE_STRICMP enables stricmp() INICHE_STRNICMP 
+ * enables strnicmp() INICHE_STRISTR enables stristr() 
+ * Created for minimal C lib support.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: stricmp(), strnicmp(), stristr(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort software John Bartas 
+ */
+
+#include "in_utils.h"
+
+/* our version of toupper() - convert lower case to upper case */
+#define INICHE_TOUPPER(c) (((c >= 'a') && (c <= 'z')) ? (c & ~0x20) : c)
+
+
+#ifdef INICHE_STRICMP   /* bring in stricmp() */
+
+int strnicmp(const char * s1, const char * s2, int len); /* forward decl. */
+
+
+/* FUNCTION: stricmp()
+ *
+ * stricmp() - string compare which ignores case. Returns 0 if 
+ * strings match. 
+ *
+ * 
+ * PARAM1: char * s1
+ * PARAM2: char * s2
+ *
+ * RETURNS: 
+ */
+
+int
+stricmp(const char * s1, const char * s2)
+{
+   int   l1,   l2;
+
+   l1 = strlen(s1);  /* get both lengths */
+   l2 = strlen(s2);
+
+   /* call strnicmp with maximum length */
+   return( strnicmp(s1, s2, ( l1 > l2 )?l1:l2 ));
+}
+
+#endif   /* INICHE_STRICMP */
+
+#ifdef INICHE_STRNICMP  /* bring in strnicmp() */
+
+/* FUNCTION: strnicmp()
+ *
+ * strnicmp() - string compare which ignores case but limits compare 
+ * size. Returns 0 if strings match. 
+ *
+ * 
+ * PARAM1: char * s1
+ * PARAM2: char * s2
+ * PARAM3: int len
+ *
+ * RETURNS: 
+ */
+
+int
+strnicmp(const char * s1, const char * s2, int len)
+{
+   char  c1,   c2;
+
+   while (len--)
+   {
+      c1 = (char)(*s1++);
+      c1 = INICHE_TOUPPER(c1);
+      c2 = (char)(*s2++);
+      c2 = INICHE_TOUPPER(c2);
+      if (c1 == c2)
+      {
+         if (c1 == 0)   /* end of both strings */
+            return 0;   /* they match */
+         continue;   /* check next char */
+      }
+      else if(c1 < c2)
+         return -1;
+      else  /* c1 > c2 */
+         return 1;
+   }
+   return 0;
+}
+
+#endif   /* INICHE_STRNICMP */
+
+#ifdef INICHE_STRISTR   /* bring in stricmp() */
+
+
+
+/* FUNCTION: stristr()
+ *
+ * stristr(str1, str2) - look for str2 (case insensitive) inside str1
+ * 
+ * PARAM1: char * str1
+ * PARAM2: char * str2
+ *
+ * RETURNS: 
+ */
+
+char * 
+stristr(char * str1, char * str2)
+{
+   char  c1,   c2;
+   c1 = (char)(*str2); /* 1st char of sub-string in upper case */
+   c1 = INICHE_TOUPPER(c1);
+
+   while (*str1)
+   {
+      c2 = (char)(*str1); /* c1=toupper(*str2) */
+      c2 = INICHE_TOUPPER(c2);
+      if (c1 == c2)  /* found first char of str2 in str1 */
+      {
+         if (strnicmp(str1, str2, strlen(str2)) == 0)
+         {
+            return str1;   /* found str2 at str1 */
+         }
+      }
+      str1++;
+   }
+   return (char*)0;
+}
+
+#endif   /* INICHE_STRISTR */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strlib.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strlib.c
new file mode 100644
index 0000000..b11f024
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strlib.c
@@ -0,0 +1,239 @@
+/*
+ * FILENAME: strlib.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Universal string  functions, provided for systems with no C library. 
+ * Created for minimal C lib support. Portions of this are still only 
+ * lightly tested. Caveat Emptor. -JB- 
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: strlen(), strcpy(), strncpy(), strcmp(), strncmp(), 
+ * ROUTINES: strcat(), strchr(), strstr(),  *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* Portions Copyright 1993 by NetPort software. */
+
+#include "ipport.h"
+#include "in_utils.h"
+
+
+#ifdef INICHE_LIBS
+
+/* FUNCTION: strlen()
+ * 
+ * PARAM1: char *             source string 
+ *
+ * RETURNS: int               string length (excluding NUL)
+ */
+int
+strlen(char *str)
+{
+   int  len = 0;
+
+   while (*str++)
+      len++;
+   return (len);
+}
+
+
+
+/* FUNCTION: strcpy()
+ * 
+ * Copy the source string into the destination string
+ *
+ * PARAM1: char *             destination string
+ * PARAM2: char *             source string
+ *
+ * RETURNS: char *            destination string
+ */
+char *   
+strcpy(char *dest, char *src)
+{
+   char *ret = dest;
+
+   while ((*dest++ = *src++) != '\0')
+      /* null */ ;
+
+   return (ret);
+}
+
+
+
+/* FUNCTION: strncpy()
+ * 
+ * Copy a maximum of 'maxcopy' characters from the source string to 
+ * the destination string
+ *
+ * PARAM1: char *             destination string
+ * PARAM2: char *             source string
+ * PARAM3: int maxcopy        maximum number of characters to copy
+ *
+ * RETURNS: char *            destination string
+ *
+ * Characters are copied from the source string to the destination string,
+ * up to a maximum of 'maxcopy' characters. If the length of the source
+ * string is less than 'maxcopy', the destination is padded with NULs.
+ * If the length of the source string is greater than or equal to 'maxcopy',
+ * the destination string is not terminated with a NUL. 
+ */
+char *   
+strncpy(char * dest, char * src, int maxcopy)
+{
+   char *ret = dest;
+
+   while (--maxcopy >= 0)
+   {   
+      if ((*dest++ = *src) != '\0')
+         ++src;
+   }
+
+   return (ret);
+}
+
+
+
+/* FUNCTION: strcmp()
+ * 
+ * Compare two strings
+ *
+ * PARAM1: char *             string 1
+ * PARAM2: char *             string 2
+ *
+ * RETURNS: int                 0 if the strings are equal
+ *                            < 0 if string1 is less than string2
+ *                            > 0 if string1 is greater than string2
+ *
+ * String1 is less than string2 if string1 is shorter than string2.
+ */
+int
+strcmp(char * str1, char * str2)
+{
+   while (*str1 == *str2)
+   {
+      ++str1;
+      ++str2;
+   }
+
+   return (*str1 - *str2);
+}
+
+
+
+/* FUNCTION: strncmp()
+ * 
+ * Compare the first N characters of two strings
+ *
+ * PARAM1: char *             string1
+ * PARAM2: char *             string2
+ * PARAM3: int                N, maximum number of characters to compare
+ *
+ * RETURNS: int                 0 if the strings are equal
+ *                            < 0 if string1 < string2
+ *                            > 0 if string1 > string2
+ *
+ * Similar to strcmp() except that the comparison is performed only
+ * on the first N characters of each string.
+ */
+int 
+strncmp(char *str1, char *str2, int length)
+{
+   if (length <= 0)
+      return 0;
+
+   while ((--length > 0) && (*str1 == *str2))
+   {
+      ++str1;
+      ++str2;
+   }
+
+   return (*str1 - *str2);
+}
+
+
+
+/* FUNCTION: strcat()
+ *
+ * Append string2 to string1
+ * 
+ * PARAM1: char *             string1
+ * PARAM2: char *             string2
+ *
+ * RETURNS: char *            result string (string1)
+ */
+char *   
+strcat(char *str1, char *str2)
+{
+   char *cp = str1;
+
+   while (*cp)    /* find null at the end of str1 */
+      cp++;
+
+   do
+   {
+      *cp++ = *str2;
+   } while (*str2++);
+
+   return (str1);
+}
+
+
+
+/* FUNCTION: strchr()
+ * 
+ * Find the first occurance of a character in a string
+ *
+ * PARAM1: char *             string
+ * PARAM2: char               character
+ *
+ * RETURNS: char *            position of character in string or NULL
+ */
+char * 
+strchr(char *str, char chr)
+{
+   do
+   {
+      if (*str == chr)
+         return (str);
+   } while (*str++ != '\0');
+
+   return ((char *)NULL);     /* character not found */
+}
+
+
+
+/* FUNCTION: strstr()
+ *
+ * Find the first occurance of string2 within string1
+ *
+ * PARAM1: char *             string1
+ * PARAM2: char *             string2
+ *
+ * RETURNS: char *            position of string2 within string1 or NULL
+ */
+char * 
+strstr(char * str1, char * str2)
+{
+   int len1 = strlen(str1);
+   int len2 = strlen(str2);
+
+   while (len1 >= len2)
+   {
+      if (*str1 == *str2)
+      {
+         if (strncmp(str1, str2, len2) == 0)
+            return (str1);
+      }
+      ++str1;
+      --len1;
+   }
+
+   return ((char *)NULL);
+}
+
+#endif   /* INICHE_LIBS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strtol.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strtol.c
new file mode 100644
index 0000000..f268db8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/strtol.c
@@ -0,0 +1,260 @@
+
+#include "ipport.h"
+
+#ifdef INICHE_STRTOL
+
+#include <ctype.h>
+#include <errno.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*
+ * The table below is used to convert from ASCII digits to a
+ * numerical equivalent.  It maps from '0' through 'z' to integers
+ * (100 for non-digit characters).
+ */
+
+static char cvtIn[] = {
+    0, 1, 2, 3, 4, 5, 6, 7, 8, 9,		/* '0' - '9' */
+    100, 100, 100, 100, 100, 100, 100,		/* punctuation */
+    10, 11, 12, 13, 14, 15, 16, 17, 18, 19,	/* 'A' - 'Z' */
+    20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+    30, 31, 32, 33, 34, 35,
+    100, 100, 100, 100, 100, 100,		/* punctuation */
+    10, 11, 12, 13, 14, 15, 16, 17, 18, 19,	/* 'a' - 'z' */
+    20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+    30, 31, 32, 33, 34, 35};
+
+/*
+ *----------------------------------------------------------------------
+ *
+ * strtoul --
+ *
+ *	Convert an ASCII string into an integer.
+ *
+ * Results:
+ *	The return value is the integer equivalent of string.  If endPtr
+ *	is non-NULL, then *endPtr is filled in with the character
+ *	after the last one that was part of the integer.  If string
+ *	doesn't contain a valid integer value, then zero is returned
+ *	and *endPtr is set to string.
+ *
+ * Side effects:
+ *	None.
+ *
+ *----------------------------------------------------------------------
+ */
+
+      /* String of ASCII digits, possibly
+				 * preceded by white space.  For bases
+				 * greater than 10, either lower- or
+				 * upper-case digits may be used. */
+                
+     /* Where to store address of terminating character, or NULL. */
+
+    /* Base for conversion.  Must be less
+				 * than 37.  If 0, then the base is chosen
+				 * from the leading characters of string:
+				 * "0x" means hex, "0" means octal, anything
+				 * else means decimal.*/
+unsigned long 
+strtoul(const char *string, char **endPtr, int base)
+{
+    const char *p;
+    unsigned long int result = 0;
+    unsigned digit;
+    int anyDigits = 0;
+    int negative=0;
+    int overflow=0;
+
+    /*
+     * Skip any leading blanks.
+     */
+
+    p = string;
+    while (isspace((unsigned char)(*p))) {
+	p += 1;
+    }
+    if (*p == '-') {
+        negative = 1;
+        p += 1;
+    } else {
+        if (*p == '+') {
+            p += 1;
+        }
+    }
+
+    /*
+     * If no base was provided, pick one from the leading characters
+     * of the string.
+     */
+    
+    if (base == 0)
+    {
+	if (*p == '0') {
+	    p += 1;
+	    if ((*p == 'x') || (*p == 'X')) {
+		p += 1;
+		base = 16;
+	    } else {
+
+		/*
+		 * Must set anyDigits here, otherwise "0" produces a
+		 * "no digits" error.
+		 */
+
+		anyDigits = 1;
+		base = 8;
+	    }
+	}
+	else base = 10;
+    } else if (base == 16) {
+
+	/*
+	 * Skip a leading "0x" from hex numbers.
+	 */
+
+	if ((p[0] == '0') && ((p[1] == 'x') || (p[1] == 'X'))) {
+	    p += 2;
+	}
+    }
+
+    /*
+     * Sorry this code is so messy, but speed seems important.  Do
+     * different things for base 8, 10, 16, and other.
+     */
+
+    if (base == 8) {
+	unsigned long maxres = ULONG_MAX >> 3;
+	for ( ; ; p += 1) {
+	    digit = *p - '0';
+	    if (digit > 7) {
+		break;
+	    }
+	    if (result > maxres) { overflow = 1; }
+	    result = (result << 3);
+	    if (digit > (ULONG_MAX - result)) { overflow = 1; }
+	    result += digit;
+	    anyDigits = 1;
+	}
+    } else if (base == 10) {
+	unsigned long maxres = ULONG_MAX / 10;
+	for ( ; ; p += 1) {
+	    digit = *p - '0';
+	    if (digit > 9) {
+		break;
+	    }
+	    if (result > maxres) { overflow = 1; }
+	    result *= 10;
+	    if (digit > (ULONG_MAX - result)) { overflow = 1; }
+	    result += digit;
+	    anyDigits = 1;
+	}
+    } else if (base == 16) {
+	unsigned long maxres = ULONG_MAX >> 4;
+	for ( ; ; p += 1) {
+	    digit = *p - '0';
+	    if (digit > ('z' - '0')) {
+		break;
+	    }
+	    digit = cvtIn[digit];
+	    if (digit > 15) {
+		break;
+	    }
+	    if (result > maxres) { overflow = 1; }
+	    result = (result << 4);
+	    if (digit > (ULONG_MAX - result)) { overflow = 1; }
+	    result += digit;
+	    anyDigits = 1;
+	}
+    } else if ( base >= 2 && base <= 36 ) {
+	unsigned long maxres = ULONG_MAX / base;
+	for ( ; ; p += 1) {
+	    digit = *p - '0';
+	    if (digit > ('z' - '0')) {
+		break;
+	    }
+	    digit = cvtIn[digit];
+	    if (digit >= ( (unsigned) base )) {
+		break;
+	    }
+	    if (result > maxres) { overflow = 1; }
+	    result *= base;
+	    if (digit > (ULONG_MAX - result)) { overflow = 1; }
+	    result += digit;
+	    anyDigits = 1;
+	}
+    }
+
+    /*
+     * See if there were any digits at all.
+     */
+
+    if (!anyDigits) {
+	p = string;
+    }
+
+    if (endPtr != 0) {
+	/* unsafe, but required by the strtoul prototype */
+	*endPtr = (char *) p;
+    }
+
+    if (overflow) {
+/*	errno = ERANGE;*/
+	return ULONG_MAX;
+    } 
+    if (negative) {
+	return -result;
+    }
+    return result;
+}
+
+long int
+strtol(
+    const char *string,		/* String of ASCII digits, possibly
+				 * preceded by white space.  For bases
+				 * greater than 10, either lower- or
+				 * upper-case digits may be used.
+				 */
+    char **endPtr,		/* Where to store address of terminating
+				 * character, or NULL. */
+    int base			/* Base for conversion.  Must be less
+				 * than 37.  If 0, then the base is chosen
+				 * from the leading characters of string:
+				 * "0x" means hex, "0" means octal, anything
+				 * else means decimal.
+				 */)
+{
+    const char *p;
+    long result;
+
+    /*
+     * Skip any leading blanks.
+     */
+
+    p = string;
+    while (isspace((unsigned char)(*p))) {
+	p += 1;
+    }
+
+    /*
+     * Check for a sign.
+     */
+
+    if (*p == '-') {
+	p += 1;
+	result = -(strtoul(p, endPtr, base));
+    } else {
+	if (*p == '+') {
+	    p += 1;
+	}
+	result = strtoul(p, endPtr, base);
+    }
+    if ((result == 0) && (endPtr != 0) && (*endPtr == p)) {
+	*endPtr = (char *) string;
+    }
+    return result;
+}
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/syslog.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/syslog.c
new file mode 100644
index 0000000..31c1d36
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/syslog.c
@@ -0,0 +1,1811 @@
+/*
+ * FILENAME: syslog.c
+ *
+ * Copyright 2004 By InterNiche Technologies Inc. All rights reserved.
+ *
+ * Implements the syslog client for InterNiche Stack.
+ * API is based on the BSD syslog specification.
+ * This syslog client also allows different applications to send
+ * logs to different syslog servers. 
+ *
+ * Usability notes.
+ * Applications can use syslog as follows.
+ * 1. Use syslog directly. Just call syslog() to send the log.
+ * 2. Use syslog when needed.
+ *    Call openlog() to open logging for a facility/application.
+ *    Call syslog() to send logs.
+ *    Call closelog() when done.
+ * 3. Use syslog with special features (for InterNiche syslog client)
+ *    We have defined a special mechanism where-in different
+ *    applications can send logs to different syslog servers.
+ *    To use this feature, use the following sequence.
+ *    Call openlog() to open logging for a facility/application.
+ *    Call openlogaddr() to set the syslog server address.
+ *    Call syslog() to send logs to the specific syslog server.
+ *    Call closelogfac() when done. This will close the logging
+ *       session for the particular application.
+ *
+ * Additional information about the syslog client
+ * 1. Call setlogmask() to mask the priorities of syslog messages.
+ * 2. Calling closelog() closes all logging sessions, including
+ *    the default. On a subsequent syslog() call, default session
+ *    is recreated.
+ * 3. syslog() does the following
+ *    - If LOG_CONS option was set, then log to console
+ *    - If LOG_FILE option was set, then log to file.
+ *    - Send message/log to syslog server
+ * 4. If no facility/application is specified in syslog(),
+ *    then the default facility LOG_USER is used.
+ * 5. Here are some of the default values
+ *    Default facility - LOG_USER
+ *    Default severity - LOG_NOTICE
+ *    Default options  - LOG_FILE
+ * 6. The test cases/functions provided at the end of the 
+ *    file can be viewed for sample usage.
+ * 7. sl_defparams.enable flag can be used to enable/disable syslog
+ * 8. sl_defparams.enable flag can be used to enable/disable 
+ *    local logging of syslog messages - not currently supported. 
+ * 
+ *    
+ * Interoperability notes.
+ * - The openlog(), syslog(), closelog(), setlogmask() functions 
+ *    work as per the BSD specs (manpages).
+ * - In addition to the above, specific functions like
+ *    openlogaddr() and closelogfac() are provided.
+ * - Support for other BSD syslog functions (like vsyslog())
+ *    is not provided.
+ *
+ * Integration notes.
+ * - At system startup, call syslog_init() to initialize the syslog client
+ *   Mainly needed to install the syslog sub-menu
+ * - At system shutdown, call closelog() to cleanup the syslog client
+ *   - Close the open log file
+ *   - Release all the resources used by syslog client
+ *     (free all nodes in sl_list). 
+ * - Syslog packets are sent over UDP. If SYSLOG_SOCKETS is defined,
+ *   then sockets API is used for it. Otherwise lightweight API is used.
+ *
+ *
+ * 09/02/2004 - created -AT-
+ * 10/04/2004 - support for lightweight API -AT-
+ * 
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: closelog(), openlog(), sl_create_default(), 
+ * ROUTINES: sl_print_date(), syslog(), 
+ * ROUTINES: setlogmask(), openlogaddr(), closelogfac(), 
+ * ROUTINES: sl_lw_udpsend(), sl_udpsend(), sl_logger(), 
+ * ROUTINES: sl_set_syslogd(), sl_enable(), sl_stats(), 
+ * ROUTINES: sl_test1(), sl_test2(), sl_test3(), sl_test4(), 
+ * ROUTINES: sl_testsev(), sl_testfac(), sl_testdate(), sl_testall(), 
+ * ROUTINES: sl_nvset(), sl_nvinfo(), syslog_init(), prep_syslog(), 
+ *
+ * PORTABLE: yes
+ * Port-dependent macros have been provided in syslog.h
+ * and can be finetuned for the specific port.
+ *
+ */
+
+
+#include "ipport.h"   /* InterNiche embedded system includes */
+
+#ifdef INICHE_SYSLOG  /* whole file can be ifdefed out */
+
+#include "syslog.h"
+#include "genlist.h"  /* generic linked list */
+#include "vfsfiles.h"
+#include "in_utils.h"
+#include "menu.h"
+#include "udp.h"       /* decl of udp_alloc(), udp_send() */
+#include "q.h"
+#include "intimers.h"
+#ifdef USE_SNTP_V4
+#include "..\sntp\sntpv4.h"
+#endif
+
+#ifndef SUPERLOOP
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+#include OSPORT_H
+#endif   /* SUPERLOOP */
+
+#ifndef SUPERLOOP
+extern TK_OBJECT(to_syslog);
+#endif   /* not SUPERLOOP */
+
+/* if TCP is being used, then use sockets, else lightweight UDP API */
+#ifdef INCLUDE_TCP
+#define SYSLOG_SOCKETS   1  /* use sockets() */ 
+#endif
+
+
+/* syslog_info structure contains all parameters (facility specific) *
+ * for sending a syslog message/log to a syslog server.              *
+ * sl_list will maintain a dynamic linked list of syslog_info nodes. *
+ * All nodes in sl_list can be indexed using the facility value.     *
+ */
+typedef struct syslog_info
+{
+   long facility;           /* application using syslog */
+   char iden[MAX_NAME_LEN]; /* name of the facility */
+   int  logopt;             /* options for logging */
+   SOCKTYPE sock;           /* client socket   */
+   struct sockaddr sa;      /* sa and sa_len are needed for sendto() */
+   int sa_len;
+   VFILE  *fp;              /* log file */
+   char * fname;            /* name of log file */
+}syslog_info;
+
+/* sl_defval global defines the default values used by               *
+ * the syslog client. Default settings can be adjusted               *
+ * via sl_defval.                                                    *
+ */
+static syslog_info sl_defval = 
+{ LOG_USER, "", LOG_FILE, INVALID_SOCKET };
+
+/* sl_def points to the node in sl_list with default settings.       *
+ * By using sl_def, we don't have to do a lookup in sl_list          *
+ * for the default case.                                             *
+ */
+static syslog_info *sl_def = NULL;
+static long sl_mask = LOG_UPTO(LOG_DEBUG);/* default - allow all severities */
+
+/* syslog_stats contains counters for statisical needs               *
+ */
+struct syslog_stats
+{
+   long callcnt;                   /* num of times syslog() was called */
+   long severity[SEVERITY_MAX];    /* a counter for each severity */
+   long facility[LOG_NFACILITIES];/* a counter for each facility */
+};
+
+struct syslog_stats slstats;
+
+/* Define sl_list. As all genlist API expect a pointer to NicheList,
+ * lets define syslog_list and make sl_list point to it.
+ * We will refer to sl_list in all the API.
+ */
+struct NicheList syslog_list;
+NICHELIST sl_list = &syslog_list;
+
+int sl_udpsend(syslog_info *sli, char * outbuf, int len);
+extern u_long inet_addr(char far * str);
+extern char *print46_addr(struct sockaddr *ipaddr);
+
+/* Syslog Client related non-volatile parameters. Please see nvparms.h
+ * and nvparms.c regarding the usage of the following structure.
+ */
+struct sl_nvparam
+{
+   char   logfile[MAX_NVSTRING];  /* name of log file */
+   unshort year;                  /* device start date (year, month, day) */
+   unshort month;
+   unshort day;
+   unshort enable;                /* 1/0 - enable/disable syslog clnt */
+   unshort locallog;            /* 1/0 - enable/disable local log */
+   unshort pad;                   /* pad to make syslogd 32-bit aligned */
+   /* syslogd array holds IP addresses of default syslog servers/daemons */
+   struct sockaddr syslogd[LOG_MAXSVRS] ; 
+};
+
+struct sl_nvparam sl_defparms = 
+{ 
+   _PATH_LOG, LOG_YEAR, LOG_MONTH, LOG_DAY, 1, 0,
+};
+
+/* structure to encapsulate all time-related fields */
+struct sl_time
+{
+   u_short year;
+   u_char month;
+   u_char day;
+   u_char hours;
+   u_char minutes;
+   u_char seconds;
+};
+
+int syslog_init_flag = 0;
+#ifdef USE_SYSLOG_QUEUE
+typedef struct syslog_item_st
+{
+   int priority;
+   int buf_size;
+   char *outbuf;
+}  syslog_item_st;
+
+#ifndef USE_SYSLOG_TASK
+long syslog_timer = 0;
+#endif
+void syslog_handler(long foo);
+queue syslog_queue;
+#endif
+
+/* FUNCTION: closelog()
+ *
+ * Release all the resources used by syslog client
+ * - Close the open log files
+ * - Close the open sockets 
+ * - Free all nodes in sl_list 
+ *
+ * PARAM1: -
+ *
+ * RETURNS: -
+ */
+
+void 
+closelog(void)
+{
+   /* Release all resourses used by syslog client */
+   int len,i;
+   syslog_info * tmp;
+
+   len = niche_list_len(sl_list);
+
+   /* close the socket and file used by each facility */
+   for (i=0; i < len; i++)
+   {
+      tmp = (syslog_info *) niche_list_getat(sl_list,i);
+#ifdef SYSLOG_SOCKETS
+      if (tmp->sock != INVALID_SOCKET)
+      {
+         socketclose(tmp->sock);
+         tmp->sock = INVALID_SOCKET;
+      }
+#endif
+      if (tmp->fp != NULL)
+      {
+         vfclose(tmp->fp);
+         tmp->fp = NULL;
+      }
+   }
+
+   /* Use niche_list_destructor() delete all elements from the list. */
+   niche_list_destructor(sl_list);
+
+   sl_def = NULL;  
+}
+
+/* FUNCTION: openlog()
+ *
+ * Note the iden and logopt values for the facility.
+ * And use them for future syslog() calls for this facility.
+ * 
+ * This function creates a new node for this facility in sl_list
+ * and puts all the information in the node. syslog() refers
+ * to this information.
+ *
+ * PARAM1: -
+ *
+ * RETURNS: -
+ */
+
+void 
+openlog(const char * iden, int logopt, int facility)
+{
+   syslog_info *tmp;
+   tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+
+   if (tmp)
+   {
+      /* we already have an entry for this facility - update it */
+   }
+   else
+   {
+      /* add an entry for this facility */
+      if (niche_add_id_and_name(sl_list,facility,(char *)iden) != SUCCESS)
+         return;
+      tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+      tmp->fp = NULL;
+      tmp->sock = INVALID_SOCKET;
+      tmp->sa_len = 0;
+   }
+
+   strcpy(tmp->iden,iden);
+   tmp->logopt = logopt;
+}
+
+/* FUNCTION: sl_create_default()
+ *
+ * Create an entry for default syslog messages.
+ * And make sl_def point to it.
+ *
+ * PARAM1: -
+ *
+ * RETURNS: -
+ */
+
+void
+sl_create_default(void)
+{
+   if (!sl_def)
+   {      
+      /* default entry does not exist - create it */
+      openlog(sl_defval.iden, sl_defval.logopt, sl_defval.facility);
+      sl_def = (syslog_info *)niche_lookup_id(sl_list,sl_defval.facility);
+      if (!sl_def)
+         return;     /* can't add new node - out of memory ?? */
+
+      openlogaddr(sl_defval.facility, &sl_defparms.syslogd[0], 
+         sizeof(struct sockaddr_in),  _PATH_LOG);
+   }
+}
+
+/* FUNCTION: sl_print_date_sl()
+ *
+ * Print today's date and time in the passed buffer.
+ *
+ * InterNiche stack has a concept of timeticks (ticks since the
+ * system was up). Thats it. It starts with 0 and gets updated
+ * at evertime time tick.
+ *
+ * For the syslog message, we need to print the date.
+ * This is done using the following algorithm.
+ * 1. Year, month, day fields of sl_defparms denote the system startup date.
+ *    (LOG_YEAR, LOG_MONTH, LOG_DAY are default values for date)
+ * 2. Using timetick, we can find out number of days since the system was up.
+ * 3. We add the number of days to start date to get today's date.
+ *
+ * PARAM1: char * outbuf              - buffer to print date on(OUT)
+ * PARAM2: int priority               - priority of the message (IN)
+ * PARAM3: unsigned long timetick     - timeticks since system was up (IN)
+ *
+ * RETURNS: -
+ */
+void
+sl_print_date_sl(char * outbuf, int priority, unsigned long timetick)
+{
+   /* first print the priority, date, time */
+   unsigned seconds, minutes, hours;
+   int year = sl_defparms.year;
+   int month = sl_defparms.month;
+   int day = sl_defparms.day;
+   int days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+   timetick = timetick/100;   /* turn timetick into seconds */
+   seconds = (unsigned)(timetick%60);
+   timetick = timetick/60;    /* turn timetick into minutes */
+   minutes = (unsigned)(timetick%60);
+   timetick = timetick/60;    /* turn timetick into hours */
+   hours = (unsigned)(timetick%24);
+   timetick = timetick/24;    /* turn timetick into days */
+
+   /* add the days (since system was up) */
+   while (timetick)
+   {
+      /* add days, 1 month at a time */
+      if ((days[month-1] - day) >= (int)timetick)
+      {
+         day+= timetick;
+         timetick = 0;
+      }
+      else
+      {
+         /* advance by 1 month */
+         timetick -= days[month-1] - day +1 ;
+         day=1;  /* start of next month */
+         month++; /* advance to next month */
+         if (month >12)
+         {
+            /* advance to next year */
+            month=1;
+            year++;
+            /* reset the number of days in FEB for this year */
+            if ((((year %4) == 0) && (year % 100 !=0)) || ((year % 400) == 0))
+               days[1] =29;
+            else
+               days[1] =28;
+         }
+      }
+   }
+
+   sprintf(outbuf,"<%d>%04d-%02d-%02d %02d:%02d:%02d ",
+      priority, year, month, day, hours, minutes, seconds);
+}
+
+#ifdef USE_SNTP_V4
+void
+sl_conv_ntpts2ymdhms (struct ntp_timestamp * ntptsp, struct sl_time * sltp)
+{
+   USE_ARG(ntptsp);
+
+   sltp->year = 1970;
+   sltp->month = 1;
+   sltp->day = 1;
+   sltp->hours = 0;
+   sltp->minutes = 0;
+   sltp->seconds = 0;
+}
+
+void
+sl_print_date_ntp(char * outbuf, int priority, unsigned long timetick)
+{
+   struct ntp_timestamp ntpts;
+   int rc;
+   struct sl_time slt;
+
+   if ((rc = sntpv4_get_time (&ntpts)) == SNTPV4_OK)
+   {
+      /* convert from NTP timestamp format to year/month/day/hour/minute/second format */
+      sl_conv_ntpts2ymdhms (&ntpts, &slt);
+      sprintf(outbuf,"<%d>%04d-%02d-%02d %02d:%02d:%02d ",
+         priority, slt.year, slt.month, slt.day, slt.hours, slt.minutes, slt.seconds);
+   }
+   else
+   {
+      sl_print_date_sl (outbuf, priority, timetick);
+   }   
+}
+#endif /* USE_SNTP_V4 */
+
+void
+sl_print_date(char * outbuf, int priority, unsigned long timetick)
+{
+#ifndef USE_SNTP_V4
+   sl_print_date_sl (outbuf, priority, timetick);
+#else
+   sl_print_date_ntp (outbuf, priority, timetick);
+#endif /* USE_SNTP_V4 */
+}
+
+/* FUNCTION: syslog()
+ *
+ * PARAM1: int priority
+ * PARAM2: const char * msg
+ * PARAM3: variable argument list (like printf)
+ *
+ * RETURNS: -
+ */
+
+#ifndef NATIVE_PRINTF
+#ifdef PRINTF_STDARG
+int doprint(char * target, unsigned tlen, CONST char * sp, va_list va);
+#else
+int doprint(char * target, unsigned tlen, CONST char * sp, int FAR * vp);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+
+#if 0
+void 
+syslog(int priority, const char * msg, ...)
+{
+   syslog_info *tmp;
+
+   char * outbuf=NULL;
+   char * outbuf2;
+   int   ret_value   ;
+   int   buf_size =  MAXIOSIZE   ;
+#if defined(NATIVE_PRINTF) || defined(PRINTF_STDARG)
+   va_list argList;
+#else /* NATIVE_PRINTF || PRINTF_STRING */
+   int * next_arg=(int *)&msg;
+   next_arg +=  sizeof(char *)/sizeof(int) ;
+#endif   /* NATIVE_PRINTF || PRINTF_STRING */
+
+   /* priority = (facility | severity) */
+   int severity = LOG_PRI(priority);
+   int facility = priority & LOG_FACMASK;
+
+   /* check if syslog client is enabled or not */
+   if (!sl_defparms.enable)
+      return;  /* do nothing - because syslog client is disabled */
+
+   /* ignore severites disabled via sl_mask */
+   if (!((1 << severity) & sl_mask))
+      return;
+
+   /* If we have specific info for this facility, use it.
+    * Else use the default information.
+    */
+   tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+   if (!tmp || !tmp->sa_len)
+   {
+      if (!sl_def)
+         sl_create_default();
+
+      if (!tmp)
+         tmp = sl_def;   /* use the default settings */
+   }
+
+   /* update counters */
+   slstats.callcnt++;
+   slstats.severity[severity]++;
+   slstats.facility[facility>>3]++;
+
+   /* Allocate memory for the output string 
+    * If the format string is greater than MAXIOSIZE, then
+    * we surely need to allocate a bigger block
+    */
+   ret_value = strlen(msg); 
+   if ( ret_value >= MAXIOSIZE )
+   {
+      buf_size += ret_value ;
+   }
+
+   outbuf=(char *)npalloc(buf_size); 
+
+   if ( outbuf == NULL )
+   {
+      return ;
+   }
+
+   /* Now populate the output string */
+#ifdef LOG_PRINTDATE
+   sl_print_date(outbuf, priority, sysuptime());
+#else
+   sprintf(outbuf,"<%d> ", priority);
+#endif
+
+   strcat(outbuf, tmp->iden);
+   strcat(outbuf, ":");
+   outbuf2 = outbuf + strlen(outbuf);
+
+#ifdef NATIVE_PRINTF
+   /* use the target system's ANSI routines */
+   va_start(argList,msg);
+   ret_value = vsprintf(outbuf2,msg,argList);
+   va_end(argList);
+#else /* NATIVE_PRINTF */
+   /* use the homegrown routines */
+#ifdef PRINTF_STDARG
+   va_start(argList,msg);
+   doprint(outbuf2,buf_size,(char *)msg,argList);
+   va_end(argList);
+#else    /* not PRINTF_STDARG */
+   doprint(outbuf2,buf_size,msg,next_arg);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+
+#ifdef NATIVE_PRINTF
+   /* Check if we have overwritten the output buffer */
+   if ( (int)strlen(outbuf) > buf_size )
+   {
+      /* Might want a more robust determination of whether outbuf 
+       * got overflowed, like putting a magic number at the end of it 
+       * before vsprintf call and verifying its still there afterwards
+       */
+      /* Yes , we have overwritten. Truncate the output string.
+       * Some memory in the heap has been corrupted, but it is too
+       * late to rectify.
+       */
+      panic("ns_printf:Buffer overflow");
+      outbuf[buf_size-1]=0;   /* Null terminate the string */
+   }
+#endif
+
+   /* log to console */
+   if (tmp->logopt & LOG_CONS)
+      ns_printf(NULL,"%s\n",outbuf);
+
+   /* log to file */
+   if ((tmp->logopt & LOG_FILE) && tmp->fp)
+   {
+      vfwrite(outbuf,1,strlen(outbuf),tmp->fp);
+      vfwrite(LOG_CRLF,1,2,tmp->fp);
+   }
+   
+   ret_value = sl_udpsend(tmp, outbuf, strlen(outbuf));
+
+   /* Free memory for the output string */
+   npfree(outbuf); 
+
+   /* since syslog() can get called repeatedly down in the bowels 
+    * of a single command interpreting function, spin tk_yield() so 
+    * that some packets get a chance to get received 
+    */
+   tk_yield();
+
+   return ;
+}
+#endif
+
+/* FUNCTION: setlogmask()
+ *
+ * An application has a log priority mask that determines which 
+ * calls to syslog(3) may be logged. All other calls will be ignored. 
+ * Logging is enabled for the priorities that have the corresponding bit 
+ * set in mask. The initial mask is such that logging is enabled for 
+ * all priorities. The setlogmask() function sets this logmask for 
+ * the current process, and returns the previous mask. 
+ * If the mask argument is 0, the current logmask is not modified. 
+ *
+ * PARAM1: int maskpri
+ *
+ * RETURNS: -
+ */
+
+int  
+setlogmask (int maskpri)
+{
+   int tmp = (int) sl_mask;
+
+   /* if maskpri is 0, don't do anything */
+   if (maskpri)
+   {
+      sl_mask = maskpri;
+   }
+   return tmp;   /* return the old mask */
+}
+
+/* FUNCTION: openlogaddr()
+ *
+ * PARAM1: int facility
+ * PARAM2: struct sockaddr *sa
+ * PARAM3: int sa_len
+ * PARAM4: char * fname          - name of facility specific logfile
+ *
+ * RETURNS: -
+ */
+
+void 
+openlogaddr(int facility, struct sockaddr *sa, int sa_len, char *fname)
+{
+   syslog_info *tmp;
+   int e=0;
+
+   tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+   if (!tmp)
+   {
+      /* entry doesn't exist for this facility - create one */
+      openlog(sl_defval.iden, sl_defval.logopt, facility);
+      tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+      if (!tmp)
+         return;     /* can't add new node - out of memory ?? */
+   }
+
+#ifdef SYSLOG_SOCKETS
+   /* open UDP socket */
+   tmp->sock = socket(sa->sa_family, SOCK_DGRAM, 0);
+   if (tmp->sock == INVALID_SOCKET)
+   {
+      dprintf("syslog: can't create socket\n");
+      return ;  /* can't create socket */
+   }
+
+   /* make client socket a connected socket */
+   e = connect(tmp->sock, sa, sa_len);
+   if (e != 0)
+   {
+      e = t_errno(tmp->sock);
+      dprintf("syslog: client connect error: %d\n", e);
+      tmp->sock = INVALID_SOCKET;
+      return;
+   }
+
+   /* put socket into non-blocking mode */
+   setsockopt(tmp->sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+#else
+   USE_ARG(e);
+#endif /* SYSLOG_SOCKETS */
+
+   /* save the destination information */
+   tmp->sa = *sa;
+   tmp->sa_len = sa_len;
+
+   if (fname)  
+   {
+      tmp->fp = vfopen(fname,"wb");
+      if (!tmp->fp)
+      {
+         dprintf("syslog: client can't open file %s\n", fname);
+         return;
+      }
+      tmp->fname = fname;
+   }
+}
+
+/* FUNCTION: closelogfac()
+ *
+ * Cleanup the entry for this facility/application.
+ *
+ * PARAM1: int facility
+ *
+ * RETURNS: -
+ */
+
+void 
+closelogfac(int facility)
+{
+   syslog_info *tmp;
+   tmp = (syslog_info *)niche_lookup_id(sl_list,facility);
+   if (tmp)
+   {
+#ifdef SYSLOG_SOCKETS
+      if (tmp->sock != INVALID_SOCKET)
+      {
+         socketclose(tmp->sock);
+         tmp->sock = INVALID_SOCKET;
+      }
+#endif
+      if (tmp->fp != NULL)
+      {
+         vfclose(tmp->fp);
+         tmp->fp = NULL;
+      }
+      niche_del(sl_list, (GEN_STRUCT)tmp);
+      /* reset sl_def, if this was the default facility */
+      if (sl_def == tmp)
+         sl_def = NULL;
+   }
+}
+
+/* FUNCTION: sl_lw_udpsend()
+ *
+ * Send data using Lightweight UDP API
+ * Support both IPv4 and IPv6 addresses.
+ *
+ * PARAM1: struct sockaddr  *sa
+ * PARAM2: char * outbuf
+ * PARAM3: int len
+ *
+ * RETURNS: 
+ *    - ENP_NOMEM if out of memory
+ *    - returns -1 is address family is not supported
+ *    - return value given by udp_send()
+ */
+
+
+#ifndef SYSLOG_SOCKETS
+
+int
+sl_lw_udpsend(char * data, int len, struct sockaddr *addr)
+{ 
+   PACKET pkt;
+
+   if (addr->sa_family == AF_INET)
+   {
+      struct sockaddr_in *sin;
+      sin = (struct sockaddr_in *)addr;
+   
+      pkt = udp6_alloc(len,0);
+      if (!pkt)
+         return ENP_NOMEM;
+      pkt->nb_plen = len;
+      
+      MEMCPY(pkt->nb_prot, data, len);
+      pkt->fhost = sin->sin_addr.s_addr;
+   
+      /* underlying stack will free the packet once its sent */
+      return udp_send(sin->sin_port, LOG_PORT, pkt);
+   }
+#ifdef IP_V6
+   else if (addr->sa_family == AF_INET6)
+   {
+      struct sockaddr_in6 *sin;
+      sin = (struct sockaddr_in6 *)addr;
+   
+      pkt = udp6_alloc(len,0);
+      if (!pkt)
+         return ENP_NOMEM;
+      pkt->nb_plen = len;
+      MEMCPY(pkt->nb_prot, data, len);
+   
+      /* underlying stack will free the packet once its sent */
+      return udp6_send(&sin->sin6_addr, sin->sin6_port, LOG_PORT, pkt);
+   }
+#endif
+   else
+   {
+      return -1;  /* address family not supported */
+   }
+   
+}
+
+#endif
+
+
+/* FUNCTION: sl_udpsend()
+ *
+ * Send the syslog message via UDP.
+ * Send it using sockets or lightweight API.
+ * If SYSLOG_SOCKETS is defined, use sockets. Else use Lightweight API.
+ *
+ * PARAM1: syslog_info *sli
+ * PARAM2: char * outbuf
+ * PARAM3: int len
+ *
+ * RETURNS: -
+ */
+
+int 
+sl_udpsend(syslog_info *sli, char * outbuf, int len)
+{
+   int ret_value=0;
+
+#ifdef SYSLOG_SOCKETS
+   /* If sli doesn't have a socket of its own, use default socket.
+    * This can happen if application calls openlog(), syslog().
+    */
+
+   if (sli->sock == INVALID_SOCKET)
+      sli= sl_def;
+
+
+   /* send log to syslogd using sockets */
+   if (sli->sock)
+   {
+      ret_value = sendto(sli->sock, outbuf, len, 0, &sli->sa, sli->sa_len);
+   }
+
+#else
+   /* send log to syslogd using lightweight API */
+   if (!sli->sa_len)
+      sli= sl_def;
+  
+   ret_value = sl_lw_udpsend(outbuf, len, &sli->sa);
+
+   /* If multiple servers (syslog daemons) are present, then
+    * send log to all of them.
+    * Do it only for messages sent to default syslogd.
+    */
+   if ((LOG_MAXSVRS > 1) && (sli == sl_def))
+   {
+      int i;
+      for (i=1; i < LOG_MAXSVRS; i++)
+      {
+         ret_value = sl_lw_udpsend(outbuf, len, &sl_defparms.syslogd[i]);
+      }
+   }
+#endif
+
+   return ret_value;
+}
+
+
+#ifdef IN_MENUS
+
+char *severitynames[SEVERITY_MAX] = {
+   "emerg",     /* index 0 */
+   "alert",     /* index 1 */
+   "crit",      /* index 2 */
+   "err",       /* index 3 */
+   "warning",   /* index 4 */
+   "notice",    /* index 5 */
+   "info",      /* index 6 */
+   "debug",     /* index 7 */
+};
+
+char * facnames[LOG_NFACILITIES] = {
+   "kern",      /* index 0 */
+   "user",      /* index 1 */
+   "mail",      /* index 2 */
+   "daemon",    /* index 3 */
+   "auth",      /* index 4 */
+   "syslog",    /* index 5 */
+   "lpr",       /* index 6 */
+   "news",      /* index 7 */
+   "uucp",      /* index 8 */
+   "cron",      /* index 9 */
+   "authpriv",  /* index 10 */
+   "ftp",       /* index 11 */
+   "ntp",       /* index 12 */
+   "security",  /* index 13 */
+   "console",   /* index 14 */
+   "notused",   /* index 15 */
+   "local0",    /* index 16 */
+   "local1",    /* index 17 */
+   "local2",    /* index 18 */
+   "local3",    /* index 19 */
+   "local4",    /* index 20 */
+   "local5",    /* index 21 */
+   "local6",    /* index 22 */
+   "local7",    /* index 23 */
+};
+
+
+/* FUNCTION: sl_logger()
+ * 
+ * Send logs from command-line similar to BSD "logger" utility.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_logger(void * pio)
+{
+   ns_printf(pio,"Yet to be implemented.\n");
+   return 0;
+}
+
+/* FUNCTION: sl_set_syslogd()
+ * 
+ * Set the IP address of default syslog servers.
+ * Usage  : slsetd <num> <addr>
+ * Example: slsetd 0 10.0.0.20
+ *          slsetd 1 10.0.0.90
+ *          slsetd 2 fe80::2a0:ccff:fee0:ac23
+ *
+ * LOG_MAXSVRS defines the max. number of syslog servers supported.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_set_syslogd(void * pio)
+{
+   int index;
+   char * cp = nextarg(((GEN_IO)pio)->inbuf);    
+   char * arg;
+   if (!*cp) /* see if user put addr on cmd line */
+   {
+      ns_printf(pio, "Usage  : slsetd <num> <addr>\n");
+      ns_printf(pio, "Example: slsetd 0 10.0.0.20\n");
+      ns_printf(pio, "         slsetd 1 10.0.0.90\n");
+      ns_printf(pio, "         slsetd 2 fe80::2a0:ccff:fee0:ac23\n");
+      return -1;
+   }
+
+   index = atoi(cp);
+   if (index < 0 || index >= LOG_MAXSVRS)
+   {
+      ns_printf(pio, "Usage  : slsetd <num> <addr>\n");
+      ns_printf(pio, "Number should be between 0 and %d\n",LOG_MAXSVRS);
+      return -1;
+   }
+
+   arg  = nextarg(cp);
+   if (!arg)
+   {
+      ns_printf(pio, "Usage  : slsetd <num> <addr>\n");
+      ns_printf(pio, "addr should be a valid IPv4/IPv6 address.\n");
+      return -1;
+   }
+
+   /* Read the IPv4/IPv6 address */
+   inet46_addr(arg,&sl_defparms.syslogd[index]);
+
+   /* cleanup the prevailing entry for default servers */
+   closelogfac(sl_defval.facility);
+
+   /* The next call to syslog() will use the new default address. 
+    * It will find that sl_def is NULL and so it will call sl_create_default()
+    * to create an entry for the default facility.
+    */
+
+   return 0;
+}
+
+/* FUNCTION: sl_enable()
+ * 
+ * Enable/disable syslog.
+ * Usage  : slenable <flag>
+ * Example: slsetd 0 
+ *          slsetd 1
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_enable(void * pio)
+{
+   int value;
+   char * cp = nextarg(((GEN_IO)pio)->inbuf);    
+   if (!*cp) /* see if user put addr on cmd line */
+   {
+      ns_printf(pio, "Current syslog client setting : %s\n",
+         sl_defparms.enable ? "enabled" : "disabled" ); 
+      ns_printf(pio, "Usage  : slsetd <flag>\n");
+      ns_printf(pio, "         flag = 1/0 (enable/disable)");
+      ns_printf(pio, "Example: slsetd 0\n");
+      ns_printf(pio, "         slsetd 1\n");
+      return -1;
+   }
+
+   value = atoi(cp);
+   if (value < 0 || value > 1)
+   {
+      ns_printf(pio, "Usage  : slsetd <flag>\n");
+      ns_printf(pio, "         flag = 1/0 (enable/disable)");
+      return -1;
+   }
+
+   sl_defparms.enable = value;
+   ns_printf(pio, "New syslog client setting : %s\n",
+      sl_defparms.enable ? "enabled" : "disabled" ); 
+
+   return 0;
+}
+
+/* FUNCTION: sl_stats()
+ * 
+ * Show statistics for syslog client.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+int
+sl_stats(void * pio)
+{
+   int i,len;
+   ns_printf(pio, "Current syslog client setting : %s\n",
+      sl_defparms.enable ? "enabled" : "disabled" ); 
+   ns_printf(pio, "Statistics for syslog client.\n");
+   ns_printf(pio, " num of syslog() calls = %ld\n", slstats.callcnt);
+   for (i=0 ; i < SEVERITY_MAX; i++)
+   {
+      if (i && (i%4 == 0))
+         ns_printf(pio,"\n");
+      ns_printf(pio, " %s = %ld", severitynames[i], slstats.severity[i]);
+   }
+   for (i=0 ; i < LOG_NFACILITIES; i++)
+   {
+      if (i%4 == 0)
+         ns_printf(pio,"\n");
+      ns_printf(pio, " %s = %ld", facnames[i], slstats.facility[i]);
+   }
+   ns_printf(pio, "\nDefault values: logopt = %d, facility = %s(%d)\n",
+      sl_defval.logopt, facnames[sl_defval.facility>>3], 
+      sl_defval.facility);
+   for (i=0; i < LOG_MAXSVRS; i++)
+   {
+      ns_printf(pio, " syslogd%d = %s, Port = %d\n", i+1,
+         print46_addr(&sl_defparms.syslogd[i]), LOG_PORT);
+   }
+
+   len = niche_list_len(sl_list);
+   if (len)
+   {
+      syslog_info *tmp;
+      struct sockaddr_in *sin;
+      ns_printf(pio,"Individual settings for each facility:\n");
+      for (i=0; i < len; i++)
+      {
+         tmp = (syslog_info *)niche_list_getat(sl_list,i);
+         if (!tmp)
+         {
+            dtrap();
+            continue;  /* can this happen ? */
+         }
+         ns_printf(pio, " facility = %s(%d), iden = %s, logopt = %d\n",
+            facnames[tmp->facility>>3], tmp->facility, tmp->iden, tmp->logopt);
+         sin = (struct sockaddr_in *) &tmp->sa;
+         ns_printf(pio, " IP Addr = %s, Log filename = %s\n",
+            INET_NTOA(sin->sin_addr.s_addr), tmp->fname);
+      }
+   }
+#ifdef SYSLOG_SOCKETS
+   ns_printf(pio,"Syslog client uses sockets API for network I/O.\n");
+#else
+   ns_printf(pio,"Syslog client uses lightweight API for network I/O.\n");
+#endif
+   return 0;
+}
+
+/* FUNCTION: sl_test1()
+ * 
+ * Call syslog() to send logs from command-line.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_test1(void * pio)
+{
+   syslog(LOG_INFO|LOG_SYSLOG, "Running syslog command slt1");
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+
+   return 0;
+}
+
+/* FUNCTION: sl_test2()
+ * 
+ * Call openlog(), syslog() to send logs from command-line.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_test2(void * pio)
+{
+   openlog("InicheLog", (LOG_CONS|LOG_FILE), LOG_SYSLOG);
+   syslog(LOG_INFO|LOG_SYSLOG, "Running syslog command slt2");
+
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+   ns_printf(pio,"Also displayed log message on console - pl. verify.\n");
+
+   USE_VOID(pio);
+   return 0;
+}
+
+/* FUNCTION: sl_test3()
+ * 
+ * Call openlog(), syslog(), closelog() to send logs from command-line.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_test3(void * pio)
+{
+   openlog("InicheLog", (LOG_CONS|LOG_FILE), LOG_SYSLOG);
+   syslog(LOG_INFO|LOG_SYSLOG, "Running syslog command slt3");
+   closelog();
+
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+   ns_printf(pio,"Also displayed log message on console - pl. verify.\n");
+   ns_printf(pio,"closelog() must have cleared settings. Verify via slstats.\n");
+
+   USE_VOID(pio);
+   return 0;
+}
+
+/* FUNCTION: sl_test4()
+ * 
+ * Call openlog(), openlogaddr(), syslog(), closelogfac() to send 
+ * to a specific syslog server. 
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+#define SL_L0FILENAME   "syslocal.log"
+
+int
+sl_test4(void * pio)
+{
+   char *   arg2;
+   struct sockaddr_in sa;
+   int fac = LOG_LOCAL0;
+  
+   arg2 = nextarg(((GEN_IO)pio)->inbuf);
+   if ( (arg2 == NULL) || arg2[0] == 0 )
+   {
+      ns_printf(pio,"Run syslog test 4.\n");
+      ns_printf(pio,"Usage:slt3 <syslogd IPaddress in dotted form>\n");
+      return SUCCESS ;
+   }
+
+   ns_printf(pio, "Starting test4. Facility used = %s(%d). Log filename = %s\n", 
+      facnames[fac>>3], fac, SL_L0FILENAME );
+   openlog("InicheLog", (LOG_CONS|LOG_FILE), fac);
+   sa.sin_family = AF_INET;
+   sa.sin_addr.s_addr = inet_addr(arg2);
+   sa.sin_port = htons(LOG_PORT);  
+   openlogaddr(fac, (struct sockaddr *)&sa, 
+      sizeof(struct sockaddr_in),  SL_L0FILENAME);
+   syslog(LOG_INFO|fac, "Running syslog command slt4");
+   closelogfac(fac);
+
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+   ns_printf(pio,"Also displayed log message on console - pl. verify.\n");
+   ns_printf(pio,"closelog() must have cleared settings. Verify via slstats.\n");
+
+   USE_VOID(pio);
+   return SUCCESS;
+}
+
+/* FUNCTION: sl_testsev()
+ * 
+ * Call syslog() to send logs from command-line.
+ * Send one log for each severity.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_testsev(void * pio)
+{
+   int i;
+   for (i=0; i < SEVERITY_MAX; i++)
+      syslog(i|LOG_SYSLOG, "syslog clnt - testsev %s", severitynames[i]);
+
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+
+   return 0;
+}
+
+/* FUNCTION: sl_testfac()
+ * 
+ * Call syslog() to send logs from command-line.
+ * Send one log for each facility.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_testfac(void * pio)
+{
+   int i;
+   for (i=0; i < LOG_NFACILITIES; i++)
+      syslog(LOG_INFO|(i<<3), "syslog clnt - testfac %s", facnames[i]);
+   ns_printf(pio,"Log message sent to default syslog server.\n");
+   return 0;
+}
+
+/* FUNCTION: sl_testdate()
+ * 
+ * Test the function sl_print_date()
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_testdate(void * pio)
+{
+   char buf[40];
+
+   sl_print_date(buf,0,sysuptime());
+   ns_printf(pio,"Today's date:        %s\n", buf);
+
+   sl_print_date(buf,0,360000*24*3); /* advance 3 days */
+   ns_printf(pio,"3 days from start:   %s\n", buf);
+
+   sl_print_date(buf,0,360000*24*30); /* advance 30 days */
+   ns_printf(pio,"30 days from start:  %s\n", buf);
+
+   sl_print_date(buf,0,(unsigned long)360000*24*365); /* advance 365 days */
+   ns_printf(pio,"365 days from start: %s\n", buf);
+
+   sl_print_date(buf,0,(unsigned long)360000*24*395); /* advance 395 years */
+   ns_printf(pio,"395 days from start: %s\n", buf);
+
+   return 0;
+}
+
+/* FUNCTION: sl_testall()
+ * 
+ * Run all the individual syslog client tests.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+sl_testall(void * pio)
+{
+   sl_test1(pio);
+   sl_test2(pio);
+   sl_test3(pio);
+   /* slt4 test needs an argument */
+   strcpy(((GEN_IO)pio)->inbuf, "slt4 ");
+   strcat(((GEN_IO)pio)->inbuf, LOG_IPADDR1);
+   sl_test4(pio);
+   sl_testsev(pio);
+   sl_testfac(pio);
+   return 0;
+}
+
+int sl_nvinfo(void * pio);
+
+struct menu_op slogmenu[] = {
+ {  "syslog",   stooges,     "syslog client commands"        },
+ {  "logger",   sl_logger,   "send logs to syslog server"    },
+ {  "slstat",   sl_stats,    "display syslog statistics",    },
+ {  "slsetd",   sl_set_syslogd,"set default syslogd addr",   },
+ {  "slenable", sl_enable,   "enable/disable syslog client", },
+ {  "slt1",     sl_test1,    "test syslog()",                },
+ {  "slt2",     sl_test2,    "test openlog(), syslog()",     },
+ {  "slt3",     sl_test3,    "test open, send, closelog()",  },
+ {  "slt4",     sl_test4,    "test sending to diff syslogd", },
+ {  "sltsev",   sl_testsev,  "test all severities"           },
+ {  "sltfac",   sl_testfac,  "test all facilities"           },
+ {  "sltall",   sl_testall,  "run all the above tests"       },
+ {  "sltdate",  sl_testdate ,"test the date calculation func"},
+#ifdef INCLUDE_NVPARMS
+ {  "slnvinfo", sl_nvinfo   ,"info. read from nv file"       },
+#endif
+ {  NULL,       NULL,        NULL,                           },
+};
+
+
+#endif /* IN_MENUS */
+
+
+#ifdef INCLUDE_NVPARMS
+
+#include "nvparms.h"
+#include "ip.h"
+
+/* Please see nvparms.h and nvparms.c regarding the usage of
+ * the following datatypes and functions.
+ */
+struct nvparm_info sl_formats[] = 
+{
+   {"syslogd1: %s\n"           , NVIP46DEC , NVBND_NOOP  , \
+    &sl_defparms.syslogd[0]    , NULL, }, 
+   {"syslogd2: %s\n"           , NVIP46DEC , NVBND_NOOP  , \
+    &sl_defparms.syslogd[1]    , NULL, }, 
+   {"syslog file: %s\n"        , NVSTRING, MAX_NVSTRING  , \
+    &sl_defparms.logfile[0]    , NULL, }, 
+   {"syslog year: %u\n"        , NVUNSHORT, NVBND_NOOP   , \
+    &sl_defparms.year          , NULL, }, 
+   {"syslog month: %u\n"       , NVUNSHORT, NVBND_NOOP   , \
+    &sl_defparms.month         , NULL, }, 
+   {"syslog day: %u\n"         , NVUNSHORT, NVBND_NOOP   , \
+    &sl_defparms.day           , NULL, }, 
+   {"syslog enable: %u\n"      , NVUNSHORT, NVBND_NOOP   , \
+    &sl_defparms.enable        , NULL, }, 
+   {"syslog locallog: %u\n"    , NVUNSHORT, NVBND_NOOP   , \
+    &sl_defparms.locallog      , NULL, }, 
+};
+
+#define NUMSL_FORMATS (sizeof(sl_formats)/sizeof(struct nvparm_info))
+
+/* FUNCTION: sl_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int sl_nvset(NV_FILE * fp)
+{
+   int i = 0;
+   /* syslog client setup: */
+   nv_fprintf(fp, sl_formats[i++].pattern, print46_addr(&sl_defparms.syslogd[0]));
+   nv_fprintf(fp, sl_formats[i++].pattern, print46_addr(&sl_defparms.syslogd[1]));
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.logfile);
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.year);
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.month);
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.day);
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.enable);
+   nv_fprintf(fp, sl_formats[i++].pattern, sl_defparms.locallog);
+   return 0;
+}
+
+struct nvparm_format sl_format = 
+{
+   NUMSL_FORMATS,
+   &sl_formats[0],
+   sl_nvset,
+   NULL
+};
+
+#ifdef IN_MENUS
+/* FUNCTION: sl_nvinfo()
+ * 
+ * PARAM1: void * pio - output stream
+ *
+ * RETURNS: 
+ */
+int sl_nvinfo(void * pio)
+{
+   int i = 0;
+   /* print syslog client info read from nv file */
+   ns_printf(pio, sl_formats[i++].pattern, print46_addr(&sl_defparms.syslogd[0]));
+   ns_printf(pio, sl_formats[i++].pattern, print46_addr(&sl_defparms.syslogd[1]));
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.logfile);
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.year);
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.month);
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.day);
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.enable);
+   ns_printf(pio, sl_formats[i++].pattern, sl_defparms.locallog);
+   return 0;
+}
+#endif /* IN_MENUS */
+#endif /* INCLUDE_NVPARMS */
+
+/* FUNCTION: syslog_init()
+ * 
+ * Initialize the syslog client.
+ * - Initialize sl_list 
+ * - Initialize default values (from those read from nv file)
+ *
+ * PARAM1: -
+ *
+ * RETURNS: SUCCESS / error code
+ * Returns 0 (SUCCESS) on success.
+ */
+
+int syslog_init(void)
+{
+   syslog(LOG_INFO|LOG_SYSLOG, "syslog client started");
+   return SUCCESS;
+}
+
+
+/* FUNCTION: prep_syslog()
+ * 
+ * Prepare the syslog client to work with rest of the system.
+ * - Install syslog client's sub-menu
+ * - Install syslog client's nvparms
+ *
+ * PARAM1: -
+ *
+ * RETURNS: SUCCESS / error code
+ * Returns 0 (SUCCESS) on success.
+ */
+int prep_syslog(void)
+{
+   int e = 0;
+   if(syslog_init_flag)
+   {
+      /* already initialized */
+      return(0);
+   }
+   niche_list_constructor(sl_list, sizeof(syslog_info));
+#ifdef USE_SYSLOG_QUEUE
+   /* create and initialize syslog queue */
+   memset(&syslog_queue, 0, sizeof(queue));
+#endif
+   /* create syslog timer */
+#ifndef USE_SYSLOG_TASK
+   syslog_timer = in_timerset(syslog_handler, 1000, 0L);
+   if(syslog_timer == 0)
+   {
+      dprintf("failed to create syslog timer\n");      
+      return(-1);
+   }
+#endif
+#ifdef IN_MENUS
+   e = install_menu(&slogmenu[0]);
+#endif
+#ifdef INCLUDE_NVPARMS
+   e = install_nvformat(&sl_format, nv_formats);
+   if(e)
+      dprintf("unable to install syslog NVPARMS, reconfigure nv_formats[]\n");
+   if(LOG_MAXSVRS < 2)
+   {
+      /* with nvparms, LOG_MAXSVRS should be 2 or more */
+      dtrap();
+   }
+#endif   /* INCLUDE_NVPARMS */
+#ifdef LOG_IPADDR1
+   inet46_addr(LOG_IPADDR1, &sl_defparms.syslogd[0]);
+   inet_setport(&sl_defparms.syslogd[0], LOG_PORT);
+#endif
+#ifdef LOG_IPADDR2
+   inet46_addr(LOG_IPADDR2, &sl_defparms.syslogd[1]);
+   inet_setport(&sl_defparms.syslogd[1], LOG_PORT);
+#endif
+   syslog_init_flag = 1;
+   return e;
+}
+
+#ifdef USE_SYSLOG_QUEUE
+void syslog_handler(long foo)
+{
+   int ret_value;
+   int facility;
+   syslog_info *tmp;
+   syslog_item_st *sl_item = NULL;
+   if(syslog_init_flag == 0)
+   {
+      return;
+   }
+   while(1)
+   {
+      /* May be the best approach would be to send upto like n syslogs and then return */
+      sl_item = (syslog_item_st *) getq(&syslog_queue);  /* de-queue item from head of queue */
+      if(sl_item == NULL)
+      {
+         break;
+      }
+      facility = sl_item->priority & LOG_FACMASK;
+      /* If we have specific info for this facility, use it.
+       * Else use the default information.
+       */
+      tmp = (syslog_info *)niche_lookup_id(sl_list, facility);
+      if(!tmp || !tmp->sa_len)
+      {
+         if (!sl_def)
+            sl_create_default();
+         if (!tmp)
+            tmp = sl_def;   /* use the default settings */
+      }
+      /* log to console */
+      if (tmp->logopt & LOG_CONS)
+         ns_printf(NULL, "%s\n", sl_item->outbuf);
+      /* log to file */
+      if((tmp->logopt & LOG_FILE) && tmp->fp)
+      {
+         vfwrite(sl_item->outbuf, 1, strlen(sl_item->outbuf), tmp->fp);
+         vfwrite(LOG_CRLF, 1, 2, tmp->fp);
+      }   
+      ret_value = sl_udpsend(tmp, sl_item->outbuf, strlen(sl_item->outbuf));
+      npfree(sl_item->outbuf); 
+      npfree(sl_item); 
+   }
+   USE_ARG(foo);
+}
+
+void syslog(int priority, const char * msg, ...)
+{
+   syslog_item_st *sl_item = NULL;
+   syslog_info *tmp;
+   char *outbuf2;
+   int ret_value;
+#if defined(NATIVE_PRINTF) || defined(PRINTF_STDARG)
+   va_list argList;
+#else /* NATIVE_PRINTF || PRINTF_STRING */
+   int * next_arg = (int *) &msg;
+#endif   /* NATIVE_PRINTF || PRINTF_STRING */
+   /* priority = (facility | severity) */
+   int severity = LOG_PRI(priority);
+   int facility = priority & LOG_FACMASK;
+
+#if !defined(NATIVE_PRINTF) && !defined(PRINTF_STDARG)
+   next_arg +=  sizeof(char *)/sizeof(int) ;
+#endif
+
+   if(syslog_init_flag == 0)
+   {
+      return;
+   }
+   /* check if syslog client is enabled or not */
+   if (!sl_defparms.enable)
+      return;  /* do nothing - because syslog client is disabled */
+   /* ignore severites disabled via sl_mask */
+   if (!((1 << severity) & sl_mask))
+      return;
+   
+   sl_item = (syslog_item_st *) npalloc(sizeof(syslog_item_st)); 
+   if(sl_item == NULL)
+   {
+      return;
+   }
+   sl_item->priority = priority;
+   sl_item->buf_size = MAXIOSIZE;
+
+   /* Allocate memory for the output string 
+    * If the format string is greater than MAXIOSIZE, then
+    * we surely need to allocate a bigger block
+    */
+   ret_value = strlen(msg); 
+   if ( ret_value >= MAXIOSIZE )
+   {
+      sl_item->buf_size += ret_value ;
+   }
+   sl_item->outbuf = (char *)npalloc(sl_item->buf_size); 
+   if(sl_item->outbuf == NULL)
+   {
+      npfree(sl_item);
+      return;
+   }
+   /* If we have specific info for this facility, use it.
+    * Else use the default information.
+    */
+   tmp = (syslog_info *)niche_lookup_id(sl_list, facility);
+   if(!tmp || !tmp->sa_len)
+   {
+      if (!sl_def)
+         sl_create_default();
+      if (!tmp)
+         tmp = sl_def;   /* use the default settings */
+   }
+   /* update counters */
+   slstats.callcnt++;
+   slstats.severity[severity]++;
+   slstats.facility[facility>>3]++;
+   /* Now populate the output string */
+   sl_print_date(sl_item->outbuf, priority, sysuptime());
+   strcat(sl_item->outbuf, tmp->iden);
+   strcat(sl_item->outbuf, ":");
+   outbuf2 = sl_item->outbuf + strlen(sl_item->outbuf);
+#ifdef NATIVE_PRINTF
+   /* use the target system's ANSI routines */
+   va_start(argList, msg);
+   ret_value = vsprintf(outbuf2, msg, argList);
+   va_end(argList);
+#else /* NATIVE_PRINTF */
+   /* use the homegrown routines */
+#ifdef PRINTF_STDARG
+   va_start(argList,msg);
+   doprint(outbuf2, sl_item->buf_size, (char *)msg, argList);
+   va_end(argList);
+#else    /* not PRINTF_STDARG */
+   doprint(outbuf2, sl_item->buf_size, msg, next_arg);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+#ifdef NATIVE_PRINTF
+   /* Check if we have overwritten the output buffer */
+   if((int)strlen(sl_item->outbuf) > sl_item->buf_size)
+   {
+      /* Might want a more robust determination of whether outbuf 
+       * got overflowed, like putting a magic number at the end of it 
+       * before vsprintf call and verifying its still there afterwards
+       */
+      /* Yes , we have overwritten. Truncate the output string.
+       * Some memory in the heap has been corrupted, but it is too
+       * late to rectify.
+       */
+      panic("ns_printf:Buffer overflow");
+      sl_item->outbuf[sl_item->buf_size-1] = 0;   /* Null terminate the string */
+   }
+#endif
+   /* we are done here: add it to queue */
+   putq(&syslog_queue, (void*) sl_item);  /* add item to the tail of syslog queue */
+}
+#else
+void syslog(int priority, const char * msg, ...)
+{
+   syslog_info *tmp;
+   char *outbuf = NULL;
+   char *outbuf2;
+   int ret_value;
+   int buf_size =  MAXIOSIZE   ;
+#if defined(NATIVE_PRINTF) || defined(PRINTF_STDARG)
+   va_list argList;
+#else /* NATIVE_PRINTF || PRINTF_STRING */
+   int * next_arg = (int *) &msg;
+   next_arg +=  sizeof(char *)/sizeof(int) ;
+#endif   /* NATIVE_PRINTF || PRINTF_STRING */
+   /* priority = (facility | severity) */
+   int severity = LOG_PRI(priority);
+   int facility = priority & LOG_FACMASK;
+   /* check if syslog client is enabled or not */
+   if (!sl_defparms.enable)
+      return;  /* do nothing - because syslog client is disabled */
+   /* ignore severites disabled via sl_mask */
+   if (!((1 << severity) & sl_mask))
+      return;
+   /* If we have specific info for this facility, use it.
+    * Else use the default information.
+    */
+   tmp = (syslog_info *)niche_lookup_id(sl_list, facility);
+   if(!tmp || !tmp->sa_len)
+   {
+      if (!sl_def)
+         sl_create_default();
+      if (!tmp)
+         tmp = sl_def;   /* use the default settings */
+   }
+   /* update counters */
+   slstats.callcnt++;
+   slstats.severity[severity]++;
+   slstats.facility[facility>>3]++;
+   /* Allocate memory for the output string 
+    * If the format string is greater than MAXIOSIZE, then
+    * we surely need to allocate a bigger block
+    */
+   ret_value = strlen(msg); 
+   if ( ret_value >= MAXIOSIZE )
+   {
+      buf_size += ret_value ;
+   }
+   outbuf = (char *)npalloc(buf_size); 
+   if(outbuf == NULL)
+   {
+      return ;
+   }
+   /* Now populate the output string */
+   sl_print_date(outbuf, priority, sysuptime());
+   strcat(outbuf, tmp->iden);
+   strcat(outbuf, ":");
+   outbuf2 = outbuf + strlen(outbuf);
+#ifdef NATIVE_PRINTF
+   /* use the target system's ANSI routines */
+   va_start(argList, msg);
+   ret_value = vsprintf(outbuf2, msg, argList);
+   va_end(argList);
+#else /* NATIVE_PRINTF */
+   /* use the homegrown routines */
+#ifdef PRINTF_STDARG
+   va_start(argList,msg);
+   doprint(outbuf2,buf_size,(char *)msg,argList);
+   va_end(argList);
+#else    /* not PRINTF_STDARG */
+   doprint(outbuf2,buf_size,msg,next_arg);
+#endif   /* PRINTF_STDARG */
+#endif   /* NATIVE_PRINTF */
+#ifdef NATIVE_PRINTF
+   /* Check if we have overwritten the output buffer */
+   if ( (int)strlen(outbuf) > buf_size )
+   {
+      /* Might want a more robust determination of whether outbuf 
+       * got overflowed, like putting a magic number at the end of it 
+       * before vsprintf call and verifying its still there afterwards
+       */
+      /* Yes , we have overwritten. Truncate the output string.
+       * Some memory in the heap has been corrupted, but it is too
+       * late to rectify.
+       */
+      panic("ns_printf:Buffer overflow");
+      outbuf[buf_size-1]=0;   /* Null terminate the string */
+   }
+#endif
+   /* log to console */
+   if (tmp->logopt & LOG_CONS)
+      ns_printf(NULL,"%s\n",outbuf);
+   /* log to file */
+   if ((tmp->logopt & LOG_FILE) && tmp->fp)
+   {
+      vfwrite(outbuf,1,strlen(outbuf),tmp->fp);
+      vfwrite(LOG_CRLF,1,2,tmp->fp);
+   }   
+   ret_value = sl_udpsend(tmp, outbuf, strlen(outbuf));
+
+   /* Free memory for the output string */
+   npfree(outbuf); 
+
+   /* since syslog() can get called repeatedly down in the bowels 
+    * of a single command interpreting function, spin tk_yield() so 
+    * that some packets get a chance to get received 
+    */
+   tk_yield();
+
+   return ;
+}
+#endif
+
+#ifdef USE_SYSLOG_QUEUE
+#ifdef USE_SYSLOG_TASK
+#ifndef SUPERLOOP
+
+TK_OBJECT(to_syslog);
+TK_ENTRY(tk_syslog);
+long syslog_wakes = 0;
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Create task entries for all optional add-on apps
+ */
+struct inet_taskinfo syslog_task = 
+{
+   &to_syslog,
+   "syslog task",
+   tk_syslog,
+   TK_SYSLOG_TPRIO,
+   TK_SYSLOG_SSIZE,
+};
+
+void syslog_cleanup(void)
+{
+   return;
+}
+
+/* The application thread works on a "controlled polling" basis: 
+ * it wakes up periodically and polls for work.
+ *
+ * The FTP task could aternativly be set up to use blocking sockets,
+ * in which case the loops below would only call the "xxx_check()"
+ * routines - suspending would be handled by the TCP code.
+ */
+
+/* FUNCTION: tk_syslog
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+TK_ENTRY(tk_syslog)
+{
+   int err;
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+   err = syslog_init();
+   if( err == SUCCESS )
+   {
+      exit_hook(syslog_cleanup);
+   }
+   else
+   {
+      dtrap();  
+   }
+   for (;;)
+   {
+      syslog_handler(0);         /* will block on select */
+      tk_yield();          /* give up CPU in case it didn't block */
+      syslog_wakes++;   /* count wakeups */
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+
+#endif /* not SUPERLOOP */
+#endif /* USE_SYSLOG_TASK */
+#endif /* USE_SYSLOG_QUEUE */
+
+#endif /* INICHE_SYSLOG */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/task.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/task.c
new file mode 100644
index 0000000..224f6ed
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/task.c
@@ -0,0 +1,488 @@
+/*
+ * FILENAME: task.c
+ *
+ * Copyright 1999- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: tk_init(), tk_new(), int    (), tk_block (), 
+ * ROUTINES: tk_exit(), tk_kill(), tk_stats(), tk_del(), tk_wake(), 
+ * ROUTINES: tk_sleep(), tk_ev_block(), tk_ev_wake(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1984 by the Massachusetts Institute of Technology */
+
+#include   "ipport.h"
+
+#ifdef INICHE_TASKS  /* whole file can be ifdeffed out */
+
+#include   "task.h"
+#include   "libport.h"
+#include   "profiler.h"
+
+task * tk_cur;                /* a pointer to the current task */
+unsigned TDEBUG = 0;          /* DEBUG flag */
+u_long   tk_wakeups  =  0;    /* count fo task switches */
+u_long   tk_allocfail = 0;    /* number of resource allocation failures */
+
+static task * tk_died = NULL;
+
+void  tk_del(task * tk);   /* remove tasks resources */
+
+/* FUNCTION: tk_init()
+ * 
+ * tk_init() - Initialize the tasking system. Create the first task, 
+ * and set its stack pointer to the main program stack. The first 
+ * task always uses the main system startup stack for compatability 
+ * with compiler provided "startup" files. The circular list of tasks 
+ * contains only the original task, so originally set its next task 
+ * pointer to point to itself. This routine returns to the caller 
+ * with a pointer to the first task, or error it returns NULL. 
+ *
+ * PARAM1: stack_t * st_base
+ * PARAM2: int st_size
+ *
+ * RETURNS: 
+ */
+
+task *
+tk_init(stack_t * st_base, int st_size)
+{
+   task *tk;      /* pointer to the first task */
+   stack_t * sp;
+
+   /* create the first task */
+   tk = (task*)TK_ALLOC(sizeof(struct task));
+
+   /* return immediately if task structure could not be
+    * allocated.  The caller must handle this scenario.
+    */
+   if (!tk) 
+   {
+      ++tk_allocfail;
+      return(tk);
+   }
+
+   tk_cur = tk;      /* It is the currently running task */
+   /* Task is running thus does not need to be awakened. */
+   tk->tk_flags = TF_MAIN; /* mark it as using system stack */
+   tk->tk_name = "Main";
+   tk->tk_next = tk;       /* task is only one in list */
+   tk->tk_count = 0;
+   tk->tk_size = st_size;
+   tk->tk_stack = st_base;
+
+   /* fill the system stack with the guardword */
+   sp = tk_getsp();
+#ifdef STK_TOPDOWN   /* Intel x86 "top down" stack */
+   while (sp > st_base)
+   {
+      sp--; /* stop when sp == base */
+      *sp = GUARDWORD;
+   }
+#elif STK_BOTTOMUP   /* stack moves from bottom up */
+   {  stack_t * stacktop = st_base + st_size/sizeof(stack_t);
+      while (sp < stacktop)
+      {
+         sp++;
+         *sp = GUARDWORD;
+      }
+   }
+#else
+#error You must define a stack type! (STK_TOPDOWN or STK_BOTTOMUP)
+#endif
+
+   tk->tk_guard = sp;   /* set address for stack check */
+
+#ifdef   DEBUG
+   if (TDEBUG)
+      dprintf("tk_init: Initial stack size = %d\n", tk->tk_size);
+#endif
+
+   return(tk);
+}
+
+
+/* FUNCTION: tk_new()
+ *
+ * Create a new task with stksiz bytes of stack, and place 
+ * it in the circular list of tasks after prev_tk. Awaken it so that 
+ * it will run, and set it up so that when it does run, it will start 
+ * runing routine start. This routine does not affect the execution 
+ * of the currently running task. Returns a pointer to the new task, 
+ * or NULL if there isn't enough memory for the new task 
+ *
+ * 
+ * PARAM1: task * prev_tk
+ * PARAM2: task code routine
+ * PARAM3: size of stack
+ * PARAM4: name for new task
+ * PARAM5: arg for task (deprecated)
+ *
+ * RETURNS: 
+ */
+
+task * 
+tk_new(task * prev_tk,     /* predecessor (sp?) to the new task */
+   int    (*start)(int),   /* Where the new task starts execution. */
+   int      stksiz,  /* The size in bytes of the stack of the new task. */
+   char   * name,    /* The task's name as a string */
+   int      arg)     /* argument to the task */
+{
+   task * tk;     /* a pointer to the new task */
+   stack_t * sp;  /* pointer to task stack area for fill */
+
+   /* create the new task */
+   tk = (task *)TK_ALLOC(sizeof(task));
+   if (tk == NULL)
+   {
+      ++tk_allocfail;
+      return NULL;        /* if no memory left, return null */
+   }
+   tk->tk_size = stksiz;
+   tk->tk_stack = (stack_t *)STK_ALLOC(stksiz);
+   if (tk->tk_stack == NULL)
+   {
+      ++tk_allocfail;
+      TK_FREE(tk);
+      return NULL;
+   }
+
+   /* set it up to run */
+   tk->tk_fp = tk_frame (tk, start, arg);
+
+   /* fill stack with guardword */
+   sp = tk->tk_fp;
+
+#ifdef STK_TOPDOWN   /* Intel x86 "top down" stack */
+   sp--;
+   while (sp > tk->tk_stack)
+   {
+      sp--;
+      *sp = GUARDWORD;
+   }
+#else /* stack moves from bottom up */
+   dtrap(); /* untested */
+   x = stksiz - (sp - tk->tk_stack);   /* bytes to fill */
+   x = x/(sizeof(stack_t));
+   x++;
+   sp++;
+   while (x++ > 0)
+      *sp++ = GUARDWORD;   
+#endif
+
+   tk->tk_guard = sp;
+   tk->tk_flags |= TF_AWAKE;  /* Schedule the task to run. */
+   tk->tk_next = prev_tk->tk_next;  /* Fit it in after prev_tk. */
+   prev_tk->tk_next = tk;
+   tk->tk_name = name;        /* Set its name */
+   tk->tk_count = 0;          /* init the count */
+
+   return (tk);
+}
+
+
+
+/* FUNCTION: tk_block ()
+ *
+ * Block the currently running task and run the next task in the 
+ * circular list of tasks that is awake. Before returning, see if any 
+ * cleanup has to be done for another task. 
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void
+tk_block () 
+{
+   char msg[255];
+   task * tk = tk_cur;     /* the next task to run */
+
+   /* check if the guard word is still intact */
+   if (*(tk->tk_guard) != GUARDWORD)
+   {
+      sprintf(msg, "tk_block stack: task name = %s", tk->tk_name);
+      panic(msg);
+      return;
+   }
+
+#ifdef NPDEBUG
+   if (TDEBUG)
+      dprintf("TASK: Task %s blocking.\n", tk->tk_name);
+#endif
+
+   IN_PROFILER(PF_IDLE, PF_ENTRY);      /* measure time in the idle loop */
+
+   /* find the next ready to run task */
+   do 
+   {
+      tk = tk->tk_next;
+      /* see if a sleeping task is ready to wake */
+      if (tk->tk_waketick && tk->tk_waketick < cticks)
+      {
+         tk->tk_waketick = 0; /* clear wakeup tick flag */
+         break;   /* go run this task */
+      }
+   } while ((tk->tk_flags & TF_AWAKE) == 0);
+
+   IN_PROFILER(PF_IDLE, PF_EXIT);
+
+   tk->tk_flags &= ~TF_AWAKE;    /* clear wake flag before it runs */
+   tk_switch (tk);      /* Run the next task. */
+
+#ifdef NPDEBUG
+   if (TDEBUG)
+      dprintf("TASK: Task %s running\n", tk_cur->tk_name);
+#endif
+
+   if (tk_died) 
+   {
+      tk_del(tk_died);  /* delete dead task */
+      tk_died = NULL;   /* clear pointer/flag */
+   }
+}
+
+
+
+/* FUNCTION: tk_exit()
+ *
+ * tk_exit() : destroy the current task. Accomplished by setting a 
+ * flag indicating that an exit has occured and then entering the 
+ * scheduler loop. When tk_block() returns for some other task and 
+ * finds this flag set, it deallocates the task which exited. This is 
+ * necessary because we still need a stack to run on. The task 
+ * removes itself from the circular list of tasks in the system so 
+ * that it cannot be awoken after it has exited. Otherwise, the exit 
+ * might be done in the context of the task itself, which would prove 
+ * disastrous. This routine never returns. 
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: no
+ */
+
+void
+tk_exit() 
+{
+   tk_kill(tk_cur);  /* kill current task, save in tk_to_die */
+   tk_block();       /* this should delete tk_to_die */
+   panic("tk_exit"); /* should never return from block */
+}
+
+
+/* FUNCTION: tk_kill()
+ *
+ * tk_kill(task) - kill a task. A special case is if you're killing 
+ * yourself, you die the instant your task blocks. 
+ *
+ * 
+ * PARAM1: task * tk - task to die
+ *
+ * RETURNS: void
+ */
+
+void
+tk_kill(task * tk_to_die)
+{
+   task *tk;
+
+   if(tk_died)       /* Is another task in the process of dying? */
+   {
+      tk_yield();    /* this should allow it to finish */
+      if(tk_died)    /* Other task still dying? */
+      {
+         dtrap();    /* system bug */
+      }
+   }
+   /* hunt for the task which tk_to_die is the successor of */
+   for (tk = tk_cur; tk->tk_next != tk_to_die; tk = tk->tk_next) ;
+
+   /* now patch around tk_to_die */
+   tk->tk_next = tk_to_die->tk_next;
+
+   /* If I'm killing myself, die the next time I block */
+   if (tk_cur == tk_to_die) 
+   {
+      tk_died = tk_cur;
+   }
+   else
+      tk_del(tk_to_die);
+}
+
+
+/* FUNCTION: tk_stats()
+ *
+ * tk_stats() - print out tasking system status
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+tk_stats(void * pio) 
+{
+#ifdef NET_STATS
+   task *tk;
+   char *   state;
+
+   ns_printf(pio, "tasking status:");
+   ns_printf(pio, "task wakeups: %D\n", tk_wakeups);
+   ns_printf(pio, "   name          \tstate   \tstack\tused\twakes\n");
+
+   tk = tk_cur;
+   do    /* measure stack usage using guardword pattern */
+   {
+      stack_t * up;
+      int   i; /* number of unused words in stack area */
+
+      up = tk->tk_guard;
+#ifdef STK_TOPDOWN
+      for (i = tk->tk_size/sizeof(stack_t) -1; i; i--)
+         if (*up++ != GUARDWORD) break;
+#else /* BOTTOMUP */
+      for (i = tk->tk_size/sizeof(stack_t) -1; i; i--)
+         if (*up-- != GUARDWORD) break;
+#endif
+
+      if (tk == tk_cur)
+         state = "running ";
+      else if(tk->tk_event)
+         state = "event_wt";
+      else if(tk->tk_waketick)
+         state = "sleeping";
+      else if(tk->tk_flags & TF_AWAKE)
+         state = "ready   ";
+      else
+         state = "blocked ";
+
+      ns_printf(pio, "%-18s\t%s\t%u\t%u\t%lu\n", 
+       tk->tk_name, state,
+       tk->tk_size, i*sizeof(stack_t), tk->tk_count);
+      tk = tk->tk_next;
+   } while (tk != tk_cur);
+#else
+   USE_VOID(pio);
+#endif
+   return 0;
+}
+
+
+
+/* FUNCTION: tk_del()
+ * 
+ * PARAM1: task * tk
+ *
+ * RETURNS: 
+ */
+
+void
+tk_del(task * tk)
+{
+   if (tk_cur == tk) /* don't delete running task! */
+      panic("tk_del");
+   /* free stack if it's not system stack */
+   if ((tk->tk_flags & TF_MAIN) == 0)
+      STK_FREE(tk->tk_stack);
+   TK_FREE(tk);
+}
+
+
+
+/* FUNCTION: tk_wake()
+ * 
+ * PARAM1: task * tk
+ *
+ * RETURNS: 
+ */
+
+void
+tk_wake(task * tk)
+{
+   tk->tk_flags |= TF_AWAKE;
+   tk_wakeups++;
+   tk->tk_count++;
+}
+
+
+/* FUNCTION: tk_sleep()
+ *
+ * tk_sleep()- put current task to sleep for passed tick count.
+ *
+ * 
+ * PARAM1: long ticks
+ *
+ * RETURNS: 
+ */
+
+void
+tk_sleep(long ticks)
+{
+   tk_cur->tk_flags &= ~TF_AWAKE;   /* put task to sleep */
+   tk_cur->tk_waketick = cticks + ticks;  /* set wake time */
+   tk_block();
+   tk_wakeups++;
+   tk_cur->tk_count++;
+}
+
+
+/* FUNCTION: tk_ev_block()
+ *
+ * tk_ev_block() - block current task until an event occurs. The 
+ * event is signaled by calling tk_ev_wake() with a pointer match the 
+ * one passed here. 
+ *
+ * 
+ * PARAM1: void * event
+ *
+ * RETURNS: 
+ */
+
+void
+tk_ev_block(void * event)
+{
+   tk_cur->tk_flags &= ~TF_AWAKE;   /* put task to sleep */
+   tk_cur->tk_event = event;        /* set wake event */
+   tk_block();                      /* wait for tk_ev_wake() */
+   tk_wakeups++;
+   tk_cur->tk_count++;
+}
+
+
+/* FUNCTION: tk_ev_wake()
+ *
+ * tk_ev_wake() - wake any tasks sleeping on the passed event. This 
+ * does not wake up tk_cur. 
+ *
+ * 
+ * PARAM1: void * event
+ *
+ * RETURNS: 
+ */
+
+void
+tk_ev_wake(void * event)
+{
+   task * tk;
+   /* look though task list - skip tk_cur */
+   for (tk = tk_cur->tk_next; tk != tk_cur; tk = tk->tk_next)
+   {
+      if (tk->tk_event == event) /* is task wait for this event */
+      {
+         tk->tk_event = NULL;    /* clear the event */
+         tk->tk_flags |= TF_AWAKE;  /* wake the task */
+      }
+   }
+}
+
+#endif   /* INICHE_TASKS -  whole file can be ifdeffed out */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcp_echo.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcp_echo.c
new file mode 100644
index 0000000..cb681b3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcp_echo.c
@@ -0,0 +1,1147 @@
+/*
+ * FILENAME: tcp_echo.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Test program for TCP sockets API. Implements an echo 
+ * server and client
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: tcp_client_add(), tcp_client_del(), 
+ * ROUTINES: tcp_client_from_pio(), tcp_client_from_sock(), tcp_secho_init(), 
+ * ROUTINES: tcp_secho_close(), tcp_cecho_close(), tcp_echo_cleanup(), 
+ * ROUTINES: tcp_echo_init(), tcp_sendecho(), tcp_send_an_echo(), 
+ * ROUTINES: echo_svr_upcall(), tcp_echo_recv(), tcp_echo_poll(), 
+ * ROUTINES: tcp_echo_stats(),
+ *
+ * PORTABLE: yes
+ */
+
+ 
+#include "ipport.h"     /* NetPort embedded system includes */
+
+#ifdef TCP_ECHOTEST     /* whole file can be ifdeffed out */
+
+#ifndef WINSOCK
+#include "tcpport.h"    /* NetPort embedded system includes */
+#include "in_utils.h"
+#ifndef sock_noblock
+#define  sock_noblock(sock,flag) setsockopt(sock,SOL_SOCKET,SO_NBIO,NULL,0)
+#endif
+#endif
+
+
+#define  ECHO_PORT               7  /* standard UDP/TCP echo port */
+
+/* The states of a TCP_ECHO Client. Either it is IDLE or BUSY exchaning
+   TCP Echo packets */
+#define  TCP_IDLE                1
+#define  TCP_BUSY                2
+
+/* TCP_IDLE_TIMEOUT is used to cleanup idle TCP Echo Client connections 
+   If a TCP Echo Client has not been used for this long, delete it */
+#define  TCP_IDLE_TIMEOUT        600   /* value in seconds */
+
+/* TCP_MAX_ECHO_CONN defines the maximum simultaneous TCP Echo 
+ * Clients connections allowed. This is required because for polling 
+ * TCP Echo Clients we are using t_select() call. t_select() uses 
+ * fd_set array, which can hold a maximum of FD_SETSIZE sockets. As 
+ * one socket is needed to poll TCP Echo Server, the maximum 
+ * available for TCP Echo Clients is 
+ */
+#define  TCP_MAX_ECHO_CONN       FD_SETSIZE-1   /* max TCP Echo Client conns*/
+
+
+SOCKTYPE elisten_sock =         INVALID_SOCKET; /* echo server socket */
+SOCKTYPE esvr_sock    =         INVALID_SOCKET; /* echo server active socket */
+
+extern   int                    kbhit(void); /* from Microsquash|Borland lib*/
+extern   char *                  prompt;
+
+/* This global switch can be set prior to calling tcp_echos_init() */
+int      tcpecho_server =  TRUE;
+
+/* Do we need to close the server's active socket? */
+int      esvr_sock_close = FALSE;
+
+#ifndef  ECHOBUFSIZE
+#define  ECHOBUFSIZE    (8*1024) 
+#endif
+
+/* List of error codes used by this file */
+
+#define  TCPE_BASE                  400
+#define  TCPE_ALLOC_ERROR           (TCPE_BASE+1)
+#define  TCPE_NODE_NOT_FOUND        (TCPE_BASE+2)
+#define  TCPE_CANT_OPEN_SOCKET      (TCPE_BASE+3)
+#define  TCPE_CONNECT_FAILED        (TCPE_BASE+4)
+#define  TCPE_SEND_FAILED           (TCPE_BASE+5)
+#define  TCPE_BAD_SOCKET            (TCPE_BASE+6)
+#define  TCPE_BIND_FAILED           (TCPE_BASE+7)
+#define  TCPE_LISTEN_FAILED         (TCPE_BASE+8)
+#define  TCPE_CLIENT_NOT_FOUND      (TCPE_BASE+9)
+#define  TCPE_TIME_NOT_RIPE         (TCPE_BASE+10)
+#define  TCPE_ALL_SOCKS_USED        (TCPE_BASE+11)
+#define  TCPE_BLOCKED               (TCPE_BASE+12)
+
+#define  SUCCESS                    0
+
+
+/* Structure for holding information regarding a TCP Client connection */
+
+struct TcpClient
+{
+   SOCKTYPE sock;                /* client socket */
+   void *   pio;                 /* Output messages go to this device */
+   ip_addr  rhost;               /* TCP Echos to be sent to this host */
+   u_long   replies;             /* Number of burst replies received */
+   u_long   times;               /* Number of bursts is to be sent */
+   u_long   send_cnt ;           /* Number of the reply to be sent(counter) */
+   int      state;               /* state of the TCP connection */
+   u_long   ticks;               /* ClockTick when next burst is to be sent */
+   u_long   delay;               /* Delay between two Echo bursts */
+   u_long   len;                 /* Length of TCP each burst to be sent */
+   u_long   tot_sent;            /* Total echo bytes sent */
+   u_long   tot_rcvd;            /* Total echo bytes received */
+   struct   TcpClient * next;
+   char     inbuf[ECHOBUFSIZE];  /* per-client data buffer */
+   int      sending;             /* non-zero while client is in send loop */
+};
+
+char *   srv_inbuf   =  NULL;
+
+typedef struct TcpClient * TCPCLIENT ;
+TCPCLIENT tcpq;                  /* Start node for queue of TCP clients */
+
+
+int         tcp_client_add(void *  pio);
+int         tcp_client_del(TCPCLIENT tcpclient);
+TCPCLIENT tcp_client_from_pio (void *  pio);
+TCPCLIENT tcp_client_from_sock(SOCKTYPE  sock);
+int         tcp_secho_init (void * pio);
+int         tcp_secho_close(void * pio);   
+int         tcp_cecho_close(void * pio);
+int         tcp_send_an_echo(TCPCLIENT tcpclient);
+void        tcp_echo_poll(void);
+int         tcp_echo_init(void);
+void        tcp_echo_cleanup(void);
+int         tcp_echo_stats(void * pio);
+int         tcp_sendecho(void * pio, ip_addr fhost, long len, long times);
+
+
+/* FUNCTION: tcp_client_add()
+ *
+ * Add a new client to the Queue
+ * 1. Allocates memory for a new node
+ * 2. Adds to queue
+ * 3. Initialized data members
+ *
+ * 
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number 
+ */
+
+int
+tcp_client_add(void * pio)
+{
+   TCPCLIENT tmpclient;
+   int   num_of_conn=0;
+
+   tmpclient=tcpq;
+   while (tmpclient)
+   {
+      num_of_conn++;
+      tmpclient=tmpclient->next;
+   }
+
+   if (num_of_conn >= TCP_MAX_ECHO_CONN)
+   {
+      return TCPE_ALL_SOCKS_USED;
+   }
+
+   /* Allocate memory */
+   tmpclient = (TCPCLIENT)npalloc(sizeof(struct TcpClient)) ;
+   if (tmpclient == NULL)
+   {
+      ns_printf(pio,"Allocation error.\n");
+      return TCPE_ALLOC_ERROR;
+   }
+
+   /* Add the new node to the head of the queue */
+   tmpclient->next = tcpq;
+   tcpq=tmpclient;
+
+   /* Initialize data members */
+   tmpclient->sock      = INVALID_SOCKET;
+   tmpclient->pio       = pio;
+   tmpclient->rhost     = 0;
+   tmpclient->times     = 1;        /* Count of total EchoPkts to be sent */
+   tmpclient->send_cnt  = 0;        /* Num of Echo Pkts sent till now */
+   tmpclient->ticks     = cticks;   /* Timetick to track sending of echos */
+   tmpclient->state     = TCP_IDLE ;   /* Are we sending TCP Echos? No. */
+   tmpclient->replies   = 0;        /* Num of replies received so far */
+   tmpclient->len       = 64;       /* Default value of Echo Pkt */
+   tmpclient->tot_sent  = 0;
+   tmpclient->tot_rcvd  = 0;
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tcp_client_del()
+ * 
+ * Cleanup stuff for a TCP Echo Client Three things to be done here
+ * 1. Close the underlying socket 
+ * 2. Remove node from the Q
+ * 3. Free the memory used by the node
+ *
+ * PARAM1: TCPCLIENT tcpclient - Pointer to TCP Echo Client connection
+ *
+ * RETURNS: 0 on SUCCESS or error number 
+ */
+
+int 
+tcp_client_del(TCPCLIENT tcpclient)
+{
+   int   e;
+   TCPCLIENT tmpclient, prevclient;
+
+   /* Close the underlying socket */
+   if (tcpclient->sock != INVALID_SOCKET)
+   {  
+      e = socketclose(tcpclient->sock);
+      if (e)
+      {
+         e = t_errno(tcpclient->sock);
+         ns_printf(tcpclient->pio,"tcp echo: close error %d\n", e);
+      }
+   }
+
+   /* Remove from the q */
+   if (tcpq == tcpclient)
+   {
+      /* It is the first node */
+      tcpq = tcpq->next;
+   }
+   else
+   {
+      prevclient=tcpq;
+      tmpclient=tcpq->next;
+      while (tmpclient)
+      {
+         if (tmpclient == tcpclient)
+         {
+            /* Found the node in the list */
+            prevclient->next=tmpclient->next ;
+            break;
+         }
+         else
+         {
+            prevclient=tmpclient;
+            tmpclient=tmpclient->next ;
+         }
+      }
+
+      /* Was the node found in Q ? */
+      if (tmpclient == NULL)
+      {
+         /* Node not found in Q !! */
+         dtrap();
+         return TCPE_NODE_NOT_FOUND ;
+      }
+   }
+
+   npfree(tcpclient);
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tcp_client_from_pio()
+ * 
+ * Return the TCP Echo Client connect for a particular session.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: Pointer to TCPCLIENT. NULL if connection not found.  
+ */
+
+TCPCLIENT
+tcp_client_from_pio(void * pio)
+{
+   TCPCLIENT tmpclient=tcpq;
+
+   while (tmpclient)
+   {
+      if (tmpclient->pio == pio)
+         break ;
+      else
+         tmpclient=tmpclient->next;
+   }
+
+   return tmpclient;
+}
+
+
+
+/* FUNCTION: tcp_client_from_sock()
+ * 
+ * Return the TCP Echo Client connection for a particular session.
+ *
+ * PARAM1: SOCKTYPE sock
+ *
+ * RETURNS: Pointer to TCPCLIENT. NULL if connection not found. 
+ */
+
+TCPCLIENT
+tcp_client_from_sock(SOCKTYPE sock)
+{
+   TCPCLIENT tmpclient=tcpq;
+
+   while (tmpclient)
+   {
+      if (tmpclient->sock == sock)
+         break ;
+      else
+         tmpclient=tmpclient->next;
+   }
+
+   return tmpclient;
+}
+
+
+
+/* FUNCTION: tcp_secho_init()
+ * 
+ * Initialize the TCP Echo Server. If the flag tcpecho_server is false,
+ * then Server Init is not done.
+ * 
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int 
+tcp_secho_init(void * pio)
+{
+   int   e;    /* error holder */
+   struct sockaddr_in   me;   /* my IP info, for bind() */
+   int   opt;
+
+   if (tcpecho_server)
+   {
+      ns_printf(pio,"tcp echo srv - starting.\n");
+
+      /* open TCP socket */
+      elisten_sock = socket(AF_INET, SOCK_STREAM, 0);
+      if (elisten_sock == INVALID_SOCKET)
+      {
+         ns_printf(pio,"TCP echo: bad socket: %d\n", elisten_sock);
+         return TCPE_BAD_SOCKET ;
+      }
+
+      opt = 1;
+      e = t_setsockopt(elisten_sock, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt));
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         dtrap();
+         dprintf("error %d setting SO_REUSEADDR on port %d\n", e, ECHO_PORT);
+         return SYS_SOCKETNULL;
+      }
+
+      me.sin_family = AF_INET;
+      me.sin_addr.s_addr = INADDR_ANY;
+      me.sin_port = htons(ECHO_PORT);
+
+      e = bind(elisten_sock, (struct sockaddr*)&me, sizeof(me));
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         ns_printf(pio,"tcp_echo: bad socket bind: %d, %s\n", e, so_perror(e));
+         socketclose(elisten_sock);
+         elisten_sock = INVALID_SOCKET;
+         return TCPE_BIND_FAILED ;
+      }
+      e = listen(elisten_sock, 3);
+      if (e != 0)
+      {
+         e = t_errno(elisten_sock);
+         ns_printf(pio,"tcp_echo: bad socket listen: %d %s\n", e, so_perror(e));
+         socketclose(elisten_sock);
+         elisten_sock = INVALID_SOCKET;
+         return TCPE_LISTEN_FAILED;
+      }
+      /* for listen socket into Non-blocking mode so we can poll accept */
+      sock_noblock(elisten_sock, TRUE);
+   }
+   else
+      ns_printf(pio,"tcp echo server not enabled\n");
+
+   srv_inbuf = (char *)npalloc(ECHOBUFSIZE);
+   if (srv_inbuf == NULL)
+   {
+      ns_printf(pio, "tcp server: alloc failed\n");
+      socketclose(elisten_sock);
+      elisten_sock = INVALID_SOCKET;
+      return TCPE_LISTEN_FAILED;
+   }
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tcp_secho_close()
+ * 
+ * Close the TCP Echo Server.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_secho_close(void * pio)
+{
+   int   e  =  0;       /* scratch error holder */
+   int   retval   =  0; /* return last non-zero error */
+
+   if (esvr_sock != INVALID_SOCKET)
+   {
+      e = socketclose(esvr_sock);
+      if (e)
+      {
+         retval = e = t_errno(esvr_sock);
+         ns_printf(pio,"tcp echo server: close error %d %s\n", e, so_perror(e));
+      }
+      else
+      {
+         ns_printf(pio,"tcp echo srv - closing.\n");
+         esvr_sock = INVALID_SOCKET;
+      }
+   }
+
+   if (srv_inbuf)
+   {
+      npfree(srv_inbuf);
+      srv_inbuf=NULL;
+   }
+   if (elisten_sock == INVALID_SOCKET)
+      return e;
+
+   e = socketclose(elisten_sock);
+   if (e)
+   {
+      retval = e = t_errno(elisten_sock);
+      ns_printf(pio,"tcp echo: server close error %d %s\n", e, so_perror(e));
+   }
+   elisten_sock = INVALID_SOCKET;
+
+   return retval;
+}
+
+
+/* FUNCTION: tcp_cecho_close()
+ *
+ * Close the TCP Echo Client.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_cecho_close(void * pio)
+{
+   TCPCLIENT  tcpclient;
+
+   tcpclient=tcp_client_from_pio(pio);
+   if (tcpclient == NULL)
+   {
+      ns_printf(pio,"No TCP Echo Client found for this session.\n");   
+      return TCPE_CLIENT_NOT_FOUND ;
+   }
+   else
+   {
+      ns_printf(pio,"Closing TCP Echo Client.\n");   
+      return tcp_client_del(tcpclient);
+   }
+
+}
+
+
+/* FUNCTION: tcp_echo_cleanup()
+ *
+ * Cleanup all TCP Echo related data structures.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_echo_cleanup(void)
+{
+   TCPCLIENT  tcpclient=tcpq;
+   TCPCLIENT  nextclient;
+
+   /* Close all the open clients */
+   while (tcpclient)
+   {
+      nextclient=tcpclient->next; 
+      tcp_client_del(tcpclient);
+      tcpclient=nextclient;
+   }
+
+   tcp_secho_close(NULL);
+}
+
+
+/* FUNCTION: tcp_echo_init()
+ * 
+ * Initialize TCP Echo Server
+ * Remarks : This function has been defined so that a clean interface 
+ * is provided for TCP Echo.
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_echo_init(void)
+{
+   return tcp_secho_init(NULL);
+}
+ 
+
+/* FUNCTION: tcp_sendecho()
+ * 
+ * Send TCP Echo packets to a TCP Echo Server. If a TCP Echo Client
+ * has not be created, then it is done (one per GenericIO device).
+ * Also, if the TCP Echo Server IP address is different from the
+ * one being used earlier, then socket reinitialization is done.
+ *
+ * PARAM1: void * pio      - device for console output
+ * PARAM2: ip_addr fhost   - IP Address of TCP Echo Server (IN)
+ * PARAM3: long len        - Length of TCP Echo pkt to be sent (IN)
+ * PARAM4: long times)     - Number of TCP Echo pkts to be sent (IN)
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_sendecho(void * pio,
+   ip_addr  fhost,      /* already in net endian */
+   long     len,
+   long     times)
+{
+   struct sockaddr_in   sa;
+   int   e;
+   SOCKTYPE tmp;
+   TCPCLIENT tcpclient;
+
+   /* If client socket isn't open or host has changed, open it */
+   tcpclient = tcp_client_from_pio(pio);
+   if (tcpclient == NULL)   /* not found */
+   {
+      if ((e=tcp_client_add(pio)) != SUCCESS)
+      {
+         if (e == TCPE_ALL_SOCKS_USED)
+         {
+            ns_printf(pio,"All TCP Echo Client connections are in use.\n");
+            ns_printf(pio,"Please try at a later time.\n");
+         }
+         return e;
+      }
+      tcpclient = tcp_client_from_pio(pio);
+   }
+
+   if (tcpclient->sock == INVALID_SOCKET || fhost != tcpclient->rhost)
+   {
+      int opt;
+
+      if (tcpclient->sock != INVALID_SOCKET) /* host changed */
+      {
+         socketclose(tcpclient->sock);
+         tcpclient->sock=INVALID_SOCKET;
+      }
+
+      /* (re)open new socket to client for echo */
+      tmp = socket(AF_INET, SOCK_STREAM, 0);
+      if (tmp == INVALID_SOCKET)
+      {
+         ns_printf(pio,"tcp echo: can't open socket\n");
+         tcp_client_del(tcpclient);
+         return TCPE_CANT_OPEN_SOCKET ;
+      }
+
+      e = t_setsockopt(tmp, SOL_SOCKET, SO_KEEPALIVE, &opt, sizeof(opt));
+
+      sa.sin_family = AF_INET;
+      /* host is already in network endian */
+      sa.sin_addr.s_addr = tcpclient->rhost = fhost;
+      sa.sin_port = htons(ECHO_PORT);
+
+      e = connect(tmp, (struct sockaddr*)&sa, sizeof(sa));
+      if (e != 0)
+      {
+         e = t_errno(tmp);
+         ns_printf(pio,"tcp_echo: bad socket connect: %d %s\n", e, so_perror(e));
+         tcp_client_del(tcpclient);
+         return TCPE_CONNECT_FAILED ;
+      }
+      /* Put in non-block mode */
+      sock_noblock(tmp, TRUE);      
+      tcpclient->sock = tmp;
+   }
+
+
+   tcpclient->replies   = 0;
+   tcpclient->times     = times;
+   tcpclient->delay     = pingdelay;
+   tcpclient->ticks     = cticks;
+   tcpclient->state     = TCP_BUSY ;
+   tcpclient->len       = len ;
+   tcpclient->send_cnt  = 0 ;
+
+   return tcp_send_an_echo(tcpclient);
+}
+
+ 
+
+/* FUNCTION: tcp_send_an_echo()
+ * 
+ * Send a TCP Echo packet from our client to remote server
+ *
+ * PARAM1: TCPCLIENT tcpclient - Pointer to client's connection (IN)
+ *
+ * RETURNS: 0 on SUCCESS or error number 
+ */
+
+int
+tcp_send_an_echo(TCPCLIENT tcpclient)
+{
+   int   e;
+   u_long   total;
+   u_long   sendsize;
+   u_long   starttime;
+   int      block;
+   u_long   words;      /* send data word index */
+   u_long   dataval;
+   u_long   sent  =  0; /* sent in this loop */
+
+   if (tcpclient->ticks > cticks)  
+      return TCPE_TIME_NOT_RIPE ;
+   if (tcpclient->sending)    /* guard against re-entry */
+      return TCPE_BLOCKED;
+   tcpclient->sending++;
+
+   ns_printf(tcpclient->pio,"sending TCP echo %ld to %s\n", 
+    tcpclient->send_cnt, print_ipad(tcpclient->rhost));
+
+   total = tcpclient->len;
+   block = 0;
+   starttime = cticks;
+   while (total > sent)
+   {
+      tcpclient->ticks = cticks + tcpclient->delay;   /* back off time for next send */
+      sendsize = total - sent;
+      if (sendsize > ECHOBUFSIZE)
+         sendsize = ECHOBUFSIZE;
+
+      /* write pattern into full-size data for integrity test */
+      dataval = (tcpclient->tot_sent + sent)/4;    /* data for first word of buffer */
+      for (words = 0; words < (ECHOBUFSIZE/4); words++)
+         *((u_long*)tcpclient->inbuf + words) = dataval++;
+
+      e = send(tcpclient->sock, tcpclient->inbuf, (int)sendsize, 0);
+      if (e < 0)
+      {
+         e = t_errno(tcpclient->sock);
+         if (e == EWOULDBLOCK)
+         {
+            tk_yield();
+            continue;
+         }
+         ns_printf(tcpclient->pio,"error %d sending TCP echo number %ld\n", 
+            e, tcpclient->send_cnt);
+         ns_printf(tcpclient->pio,"   on byte %ld\n", e);
+
+         tcpclient->sending--;
+         return TCPE_SEND_FAILED;
+      }
+      sent += e;
+      if ((block += e) >= ECHOBUFSIZE)
+      {
+         ns_printf(tcpclient->pio, ".");
+         block -= ECHOBUFSIZE;
+      }
+      tk_yield();    /* let other tasks run */
+   }
+
+   tcpclient->send_cnt++;  /* keep counters current */
+   tcpclient->tot_sent += sent;
+   ns_printf(tcpclient->pio, "\ntcpecho: echoed %ld bytes", sent);
+
+   if (total > ECHOBUFSIZE)   /* see if we should print performance numbers */
+   {
+      u_long   endticks;
+      u_long   bps;
+      int   fraction;
+
+      /* wait for all data to come back */
+      endticks = cticks + (5*TPS);        /* use endticks for timeout */
+      while ((tcpclient->tot_rcvd < tcpclient->tot_sent) &&
+          (cticks > endticks))
+      {
+         tk_yield();
+      }
+
+      endticks = cticks - starttime;
+      if (endticks > 0) /* avoid divide by 0 */
+      {
+         bps = sent/endticks;    /* bytes per tick */
+         bps *= TPS;             /* convert to bytes/Sec */
+         bps /= 1024;            /* KBytes/Sec */
+         fraction = (int)endticks % TPS;
+         endticks /= TPS;
+         ns_printf(tcpclient->pio, " in %d and %d/%d seconds.\n%ld KBytes/sec", 
+          (int)endticks, fraction, TPS, bps);
+      }
+   }
+   ns_printf(tcpclient->pio, "\n");
+
+   tcpclient->sending--;   /* clear reentry flag */
+   return SUCCESS;
+}
+
+
+#ifdef TCP_ZEROCOPY
+
+
+/* FUNCTION: echo_svr_upcall()
+ *
+ * echo_svr_upcall() - TCP ZEROCOPY callback for echo server socket.
+ *
+ * 
+ * PARAM1: SOCKTYPE esrv_sock
+ * PARAM2: PACKET inpkt
+ * PARAM3: int err
+ *
+ * RETURNS: 
+ */
+
+int 
+echo_svr_upcall(SOCKTYPE sock, PACKET inpkt, int err)
+{
+   int   e;
+
+   if (sock != esvr_sock)
+   {
+      dtrap();
+   }
+
+   if (err)
+   {
+      if (inpkt)
+         tcp_pktfree(inpkt);
+      /* If this is a graceful close from the client then start our 
+       * close too, else just print a message to console.
+       */
+      if (err == ESHUTDOWN)
+      {
+         /* tell tcp_echo_recv() to close the socket */
+         esvr_sock_close = TRUE;
+      }
+      else
+         dprintf("echo server callback error %d\n", err);
+      e = 0;   /* should this be an error??? later */
+   }
+   else     /* return echo */
+   {
+      e = tcp_xout(sock, inpkt);
+      if (e > 0)  /* ignore codes like ENP_SEND_PENDING */
+         e = 0;
+   }
+   return e;
+}
+#endif   /* TCP_ZEROCOPY */
+
+
+
+
+/* FUNCTION: tcp_echo_recv()
+ *
+ * tcp_echo_recv() - check for and process received echo data
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+
+
+void
+tcp_echo_recv(void)
+{
+   int   len;        /* length of recv data */
+   int   e;          /* error holder */
+   unsigned i;       /* generic index */
+   int   count;      /* select return */
+   fd_set fd_recv;   /* fd for recv */
+   fd_set fd_accept; /* fd for accept */
+   TCPCLIENT tmpclient = tcpq;
+   struct sockaddr_in client;
+   SOCKTYPE tmpsock; /* scratch socket */
+
+   if (elisten_sock == INVALID_SOCKET && tcpq == NULL)
+      return;  /* Echo not set up, don't bother */
+
+#ifdef USE_FDS
+   FD_ZERO(&fd_recv);
+   FD_ZERO(&fd_accept);
+#endif
+
+   /* select on all open data sockets */
+   i = 0;
+   count = 0;
+#ifdef USE_FDS
+   while (tmpclient)
+   {
+      if (tmpclient->sock != INVALID_SOCKET)
+      {
+         FD_SET(tmpclient->sock, &fd_recv);
+         i++;
+      }
+      tmpclient=tmpclient->next;
+   }
+#else
+   while (tmpclient)
+   {
+      if (tmpclient->sock != INVALID_SOCKET)
+         fd_recv.fd_array[i++] = tmpclient->sock ;
+      tmpclient=tmpclient->next;
+   }
+#endif  /* USE_FDS */
+
+#ifndef TCP_ZEROCOPY
+   /* if we need to listen for server receives too */
+#ifdef USE_FDS
+   if (tcpecho_server && (esvr_sock != INVALID_SOCKET))
+   {
+      FD_SET(esvr_sock, &fd_recv);
+   }
+#else
+   if (tcpecho_server)
+   {
+      if (esvr_sock != INVALID_SOCKET)
+         fd_recv.fd_array[i++] = esvr_sock;
+   }
+#endif  /* USE_FDS */
+#else
+   /* if we need to close the server's active socket */
+   if (esvr_sock_close != FALSE)
+   {
+      if (esvr_sock != INVALID_SOCKET)
+      {
+         socketclose(esvr_sock);
+         esvr_sock = INVALID_SOCKET;
+      }
+      esvr_sock_close = FALSE;
+   }
+#endif   /* TCP_ZEROCOPY */
+
+#ifndef USE_FDS
+   fd_recv.fd_count = i;
+#endif
+
+   /* make this a short timeout since elisten may create soon */
+   if (elisten_sock != INVALID_SOCKET)
+   {
+#ifdef USE_FDS
+      FD_SET(elisten_sock, &fd_accept);
+#else
+      fd_accept.fd_array[0] = elisten_sock;
+      fd_accept.fd_count = 1;
+#endif  /* USE_FDS */
+      count = t_select(&fd_recv, NULL, &fd_accept, 1);
+   }
+   else 
+   {
+      if (i)   /* if no fd_set sockets filled in, don't bother */
+         count = t_select(&fd_recv, NULL, NULL, 1);
+   }
+
+   /* While the t_select() was executing, commands can be 
+    * executed from cmd-prompt and sockets can be cleaned up. 
+    * Check for that. 
+    */
+   if (elisten_sock == INVALID_SOCKET && tcpq == NULL)
+      return;  /* Echo not set up, don't bother */
+
+   for (i = 0; i < fd_recv.fd_count; i++)
+   {
+#ifdef USE_FDS
+      tmpsock = FD_GET(i, &fd_recv);
+      if (tmpsock == INVALID_SOCKET)
+         continue;
+#else
+      tmpsock = fd_recv.fd_array[i];
+#endif  /* USE_FDS */
+
+      /* Find out the client connection corresponding to this socket */
+      tmpclient = tcp_client_from_sock(tmpsock);
+
+      /* try a receive. Pick buffer according to client or server */
+      if (tmpclient)    /* found a client for this one */
+         len = recv(tmpsock, tmpclient->inbuf, ECHOBUFSIZE, 0);
+#ifndef TCP_ZEROCOPY
+      else if (tmpsock == esvr_sock)
+         len = recv(tmpsock, srv_inbuf, ECHOBUFSIZE, 0);
+#endif   /* TCP_ZEROCOPY */
+      else
+      {
+         continue;
+      }
+
+      if (len < 0)
+      {
+         e = t_errno(tmpsock);
+         if (e != EWOULDBLOCK)
+         {
+            if (tmpsock != esvr_sock)
+               ns_printf(tmpclient->pio,"TCP echo recv error %d\n", e);
+            else
+               ns_printf(NULL,"TCP echo recv error %d\n", e);
+         }
+      }
+      else if (len == 0)
+      {
+         ns_printf(NULL,"TCPECHO:socket closed by other side\n");
+         if (tmpsock == esvr_sock)
+         {
+            socketclose (tmpsock);
+            esvr_sock = INVALID_SOCKET;
+         }
+         else
+         {
+            if (tmpclient == NULL)
+            {
+               dtrap();
+            }          
+            else
+            {
+               tmpclient->sock = INVALID_SOCKET ;
+               tcp_client_del(tmpclient);
+            }
+         }
+      }
+      else  /* if (len > 0) - got some echo data */
+      {
+#ifndef TCP_ZEROCOPY
+         if (tmpsock == esvr_sock)
+         {
+            /* we must be server, send echo reply */
+            if (tcpecho_server)
+            {
+               e = send(esvr_sock, srv_inbuf, len, 0);
+               if (e < 0)
+               {
+                  /* Print the error to console */
+                  e = t_errno(esvr_sock);
+                  ns_printf(NULL,
+                   "TCP echo server, error %d sending reply\n", e);
+               }
+            }
+         }
+         else     /* not the server socket, must be client */
+#endif   /* TCP_ZEROCOPY */
+         {
+            /* If not a bulk test, print info */
+            if (tmpclient->len <= ECHOBUFSIZE)
+            {
+               ns_printf(tmpclient->pio,"TCP echo reply from:%s, len:%d, reply:%lu", 
+                print_ipad(tmpclient->rhost), len, tmpclient->replies);
+               ns_printf(tmpclient->pio,"\n%s",prompt);
+            }
+            else
+            {
+               u_long   dataval;
+               u_long * rxbuf =  (u_long*)(tmpclient->inbuf);
+               u_long * rxend =  (u_long*)(tmpclient->inbuf +  (len  &  ~3));
+
+               dataval = tmpclient->tot_rcvd/4;
+
+               /* adjust for odd sized previous receives */
+               if (tmpclient->tot_rcvd & 3)
+               {
+                  MEMMOVE(rxbuf, tmpclient->inbuf + (len & 3), len);
+                  rxend--;
+                  dataval++;     /* ignore sliced word */
+               }
+
+               while (rxbuf < rxend)
+               {
+                  if (*rxbuf != dataval)
+                  {
+                     ns_printf(tmpclient->pio,
+                      "tcp_echo data error; got %lu, expected %lu\n",
+                      *rxbuf, dataval);
+                  }
+                  rxbuf++;
+                  dataval++;
+               }
+            }
+            tmpclient->replies++;
+            tmpclient->tot_rcvd += len;
+         }
+      }
+   }
+
+   /* if no server listen to poll, return now */
+   if (elisten_sock == INVALID_SOCKET)
+      return;
+
+#ifdef NOTDEF
+   MEMSET(&client, 0, sizeof(client));
+   client.sin_family = AF_INET;
+   client.sin_addr.s_addr = INADDR_ANY;
+   client.sin_port = htons(ECHO_PORT);
+#endif
+
+   /* check for received echo connection on server */
+   len = sizeof(client);
+   tmpsock = accept(elisten_sock, (struct sockaddr*)&client, &len);
+   if (tmpsock != INVALID_SOCKET)
+   {
+      if (esvr_sock == INVALID_SOCKET)
+      {
+         esvr_sock = tmpsock;
+#ifdef TCP_ZEROCOPY
+         t_setsockopt(esvr_sock, SOL_SOCKET, SO_CALLBACK, (void*)echo_svr_upcall, 0);
+#endif   /* TCP_ZEROCOPY */
+      }
+      else  /* we already have a connection */
+      {
+         dprintf("tcpecho: rejected extra connection\n");
+         socketclose(tmpsock);   /* refuse to serve another */
+      }
+   }
+}
+
+
+
+/* FUNCTION: tcp_echo_poll()
+ * 
+ * Do routine processing for TCP  Echos.
+ * 1. Check is Echo packets has been received for TCP Echo 
+ *    Server. If yes, send a reply.
+ * 2. Check if Echo replys have been recieved for TCP Echo Clients.
+ *    If yes, update data structures, display messages.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 
+ */
+
+static int in_echopoll = 0;   /* re-entry flag */
+
+void
+tcp_echo_poll(void)
+{
+   TCPCLIENT tmpclient = tcpq;
+
+   if (elisten_sock == INVALID_SOCKET && tcpq == NULL)
+      return;  /* Echo not set up, don't bother */
+
+   in_echopoll++;    /* don't re-enter from tk_yield() */
+   if (in_echopoll != 1)
+   {
+      in_echopoll--;
+      return;
+   }
+   tcp_echo_recv();
+
+   /* Check if we need to send TCP Echo packets */
+   tmpclient=tcpq;
+   while (tmpclient)
+   {
+      if (tmpclient->state == TCP_BUSY)
+      {
+         if (tmpclient->send_cnt  >= tmpclient->times)
+         {
+            /* Previous "techo" command has completed */
+            tmpclient->state = TCP_IDLE ;
+         }
+         else
+         {
+            if (tmpclient->replies)
+            {
+               if (tcp_send_an_echo(tmpclient) == SUCCESS)
+                  ns_printf(tmpclient->pio,"%s",prompt);
+            }
+         }
+      }
+
+      if (tmpclient->ticks + (TCP_IDLE_TIMEOUT*TPS) < cticks)
+      {
+         /* This client has been lying around ldle for a long time */
+         ns_printf(tmpclient->pio,"Deleting idle TCP Echo Client.\n%s",prompt);
+         tcp_client_del(tmpclient);
+      }
+
+
+      tmpclient=tmpclient->next;
+   }
+
+   in_echopoll--;
+}
+
+
+/* FUNCTION: tcp_echo_stats()
+ * 
+ * Show statistics about all TCP Echo Clients and Servers
+ *
+ * PARAM1: void * pio - device for console output
+ *
+ * RETURNS: 0 on SUCCESS or error number. 
+ */
+
+int
+tcp_echo_stats(void * pio)
+{
+   ns_printf(pio,"Showing TCP Echo statistics.\n");
+   if (esvr_sock == INVALID_SOCKET)
+   {
+      ns_printf(pio,"   There are no Server connections.\n");
+   }
+   else
+   {
+      ns_printf(pio,"   There is one Server connection.\n");
+   }
+
+   if (tcpq == NULL)
+      ns_printf(pio,"   There are no Client connections.\n");
+   else
+   {
+      TCPCLIENT tmpclient=tcpq;
+      int   cnt=0;
+      while (tmpclient)
+      {
+         cnt++;
+         ns_printf(pio,"   Total bytes for Client %d: sent=%ld,rcvd=%ld\n",
+          cnt, tmpclient->tot_sent, tmpclient->tot_rcvd);
+         tmpclient=tmpclient->next;
+      }
+      ns_printf(pio,"   Total Client connections=%d.\n",cnt);
+   }
+   return SUCCESS;
+}
+
+
+#endif   /* TCP_ECHOTEST */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcpcksum.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcpcksum.c
new file mode 100644
index 0000000..dff3c25
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tcpcksum.c
@@ -0,0 +1,114 @@
+/*
+ * FILENAME: tcpcksum.c
+ *
+ * Copyright 1997 - 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *  General purpose TCP checksum routine. Uses internet cksum()
+ *  routine to do actual 1's complement buffer calc, this is
+ *  usually optimized in assembly language.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: tcp_cksum(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* Portions Copyright 1997-1998 by InterNice Technologies Inc */
+
+
+#include "ipport.h"
+
+#if defined(INCLUDE_TCP) || defined(NATRT) || defined(USE_PPP) || defined(MINI_TCP)
+
+#include "tcpapp.h"
+#include "ip.h"
+#include "tcp.h"
+
+
+/* FUNCTION: tcp_cksum()
+ *
+ * tcp_cksum(struct ip - The IP header passed is assumed to be 
+ * prepended to the rest of a TCP packet, i.e. followed by TCP header 
+ * and data to be checksummed. Returns the correct checksum for the 
+ * packet. The packet data is unchanged 
+ *
+ * 
+ * PARAM1: struct ip * pip
+ *
+ * RETURNS: 
+ */
+
+unshort
+tcp_cksum(struct ip * pip)
+{
+   unshort  iphlen;  /* length of IP header, usually 20 */
+   unshort  tcplen;  /* length of TCP header and data */
+   char *   tcpdata;    /* pointer to end of tcp data, for 0 padding */
+   char     oddchar;    /* tmp save of odd char we 0 for pad */
+   unshort  oldsum;
+   unshort  newsum;
+   struct tcphdr * tp;
+
+#ifdef MUTE_WARNS    /* stifle compiler warnings */
+   tcpdata = (char *)NULL;
+#endif   /* MUTE_WARNS */
+
+   IN_PROFILER(PF_TSUM, PF_ENTRY);
+
+   oddchar = 0;
+
+   iphlen = (unshort)ip_hlen(pip);
+   tcplen = htons(pip->ip_len) - iphlen;
+
+   tp = (struct tcphdr*)ip_data(pip);     /* get TCP header */
+   oldsum = tp->th_sum;       /* Save passed checksum */
+
+   /* The TCP checksum spec. says to Init TCP header cksum field to 0 before
+    * summing. We also need to include in the sum a protocol type (always 6
+    * for TCP). the Ip length, and the IP addresses. Nominally this is done 
+    * by constructing a "pseudo header" and prepending it to the tcp header
+    * and data to be summed. Instead, we add the type & length (they 
+    * cannot overflow a 16 bit field) and put them in the cksum field. 
+    * We include the IP addresses by passing them to the lower level 
+    * fast sum routine. This results in their values being factored into 
+    * the sum and the cksum field contributes zero.
+    */
+   tp->th_sum = htons(tcplen + 6);
+
+   /* zero pad odd sized packets for checksumming */
+   if (tcplen & 1)   
+   {
+      tcpdata = ((char*)pip) + iphlen + tcplen;    /* end of packet */
+      oddchar = *tcpdata;
+      *tcpdata = '\0';        /* zero out pad byte */
+      tcplen++;               /* bump length to pass to cksum() */
+   }
+
+   /* Pass a pointer to the beginning of the IP address area into the IP header
+    * the the low level sum routine. Add the size of these two IP addresses to
+    * the length, and convert the length to 16 bit words.
+    */
+   newsum = ~cksum(((char*)tp) - 8, (tcplen + 8) >> 1);
+
+   /* If the old checksum is 0xffff, but the actual checksum is 0x0000,
+    * declare that to be a match.
+    */
+   if ((newsum != oldsum) && (oldsum == 0xffff) && (newsum == 0x0000))
+      newsum = 0xffff;
+
+   /* restore what we clobbered */
+   tp->th_sum = oldsum;       /* put back passed checksum */
+   if (oddchar)
+      *tcpdata = oddchar;     /* restore odd byte if we zeroed it */
+
+   IN_PROFILER(PF_TSUM, PF_EXIT);
+
+   return newsum;
+}
+
+#endif   /* INCLUDE_TCP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/testmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/testmenu.c
new file mode 100644
index 0000000..52bd7eb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/testmenu.c
@@ -0,0 +1,519 @@
+/*
+ * FILENAME: testmenu.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: pktwait(), setpktct(), ping_flood(), arp_flood (),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef TESTMENU   /* whole file can be ifdeffed away */
+
+#ifndef IN_MENUS
+#error TEXTNEBU requires 
+#endif   /* IN_MENUS */
+ 
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+
+#ifdef INCLUDE_SNMP
+#include "snmpport.h"    /* lengths for nvparms SNMP strings */
+#endif
+
+#include "nvparms.h"
+#include "menu.h"
+#include "in_utils.h"
+
+#ifdef DNS_CLIENT
+#include "dns.h"
+#endif   /* DNS_CLIENT */
+
+#ifdef PING_APP
+#include "app_ping.h"
+#endif
+
+extern   int   deflength;  /* int ..\misclib\app_ping.c */
+extern   unsigned lilbufsiz;
+extern   unsigned bigbufsiz;
+
+int      ping_flood(void * pio);
+int      arp_flood(void * pio);
+int      setpktct(void * pio);
+int      udp_flood(void * pio);
+int      setfport(void * pio);
+int      flood_addr(void * pio);
+int      bigq_drain(void * pio);
+int      pktq_drain(void * pio);
+int      freeq_refill(void * pio);
+int      bigq_refill(void * pio);
+
+
+static   u_short  fport = 5001;  /* default UDP port */
+
+long     pktcount =  100;
+
+#ifdef NOTDEF  /* code for main.c: */
+#ifdef TESTMENU   /* after menus.h */
+extern   struct menu_op testmenu[10];
+#endif   /* TESTMENU */
+#ifdef TESTMENU   /* after ping_init() */
+install_menu(testmenu);
+#endif   /* TESTMENU */
+#endif   /* NOTDEF */
+
+
+
+struct menu_op testmenu[]  =  {  /* array of menu option, see menu.h */
+   "test",  stooges, "test menu" ,    /* menu ID */
+   "fping",    ping_flood,    "flood pings, don't wait for reply" ,
+   "farp",     arp_flood,     "flood ARPS, don't wait for reply" ,
+   "fcount",   setpktct,      "flood packet count",
+   "fport",    setfport,      "flood packet port number (UDP)",
+   "fudp",     udp_flood,     "send UDP flood",
+   "faddr",    flood_addr,    "add/delete/list UDP flood addresses",
+   "bqdrain",  bigq_drain,    "drain [arg] pkts fropm big freeq",
+   "qdrain",   pktq_drain,    "drain all free pkt queue (forces pkt loss errors)",
+   "bqrefill", bigq_refill,   "restore [arg] drained big queue pkts",
+   "qrefill",  freeq_refill,  "restore all drained queue pkts",
+   NULL,
+};
+
+
+
+
+/* FUNCTION: pktwait()
+ *
+ * pktwait() - utility routine for flood tests - waits until a packet 
+ * of deflen size if free. Times out after a few seconds if we;re 
+ * stuck . Returns 0 if packet is ready, else -1 if timeout 
+ *
+ * 
+ * PARAM1: char * app
+ * PARAM2: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+pktwait(char * app, void * pio)
+{
+   u_long   tmo;
+
+   tmo = cticks + (3 * TPS);  /* 3 second timeout */
+   if (deflength > (int)lilbufsiz)
+   {
+      while (bigfreeq.q_len < 1)
+      {
+         tk_yield();
+         if (tmo < cticks)
+         {
+            ns_printf(pio, "%s flood timeout\n", app);
+            return -1;
+         }
+      }
+   }
+   else  /* can use a little packet */
+   {
+      while (lilfreeq.q_len < 1)
+      {
+         tk_yield();
+         if (tmo < cticks)
+         {
+            ns_printf(pio, "%s flood timeout\n",app);
+            return -1;
+         }
+      }
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: setpktct()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+setpktct(void * pio)
+{
+   char *   cp =  nextarg(((GEN_IO)pio)->inbuf);
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio,"flood packet count is %ld\n", pktcount);
+      ns_printf(pio,"To change it, put new number on command line\n");
+      return -1;
+   }
+   pktcount = atol(cp);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: ping_flood()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+ping_flood(void * pio)
+{
+   long  i,e;
+
+   ns_printf(pio, "sending ping flood of %ld pkts to %u.%u.%u.%u..", 
+    pktcount, PUSH_IPADDR(activehost) );
+
+   for (i = 0; i < pktcount; i++)
+   {
+      if (pktwait("ping", pio))
+         return -1;
+
+      e = icmpEcho(activehost, NULL, deflength, (unshort)i);
+      if (e < 0)
+      {
+         ns_printf(pio, "ping flood send error %d on pkt %ld\n",e,i);
+         return -1;
+      }
+      if ((i & 0x0f) == 0x0f)
+         ns_printf(pio, ".");
+   }
+   return 0;
+}
+
+#define  arpsize  (ETHHDR_SIZE   +  sizeof(struct  arp_hdr))
+
+
+
+
+/* FUNCTION: arp_flood ()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+arp_flood (void * pio)
+{
+   PACKET arppkt;
+   struct ethhdr *   ethhdr;
+   struct arp_hdr *  arphdr;
+   NET net;
+   long  i;
+   int   e;
+   ip_addr ipaddr;
+
+#ifdef MULTI_HOMED
+   ip_addr phost;    /* phoney host for pass to iproute */
+   net = iproute(activehost, &phost);
+#else
+   net = nets[0];
+#endif
+
+   if (!net)
+   {
+      ns_printf(pio, "ARP flood: no route");
+      return -1;
+   }
+
+   ns_printf(pio, "sending ARP flood of %ld pkts to %u.%u.%u.%u..", 
+    pktcount, PUSH_IPADDR(activehost) );
+
+
+   for (i = 0; i < pktcount; i++)
+   {
+      if (pktwait("ARP", pio))
+         return -1;
+
+      /******** code cribbed from et_arp.c: ********/
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      arppkt = pk_alloc(arpsize);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      if (!arppkt)
+         return ENP_RESOURCE;
+      arppkt->nb_prot = arppkt->nb_buff;
+      arppkt->nb_plen = arpsize;
+      arppkt->net = net;
+
+      /* build arp request packet */
+      ethhdr = (struct ethhdr *)(arppkt->nb_buff + ETHHDR_BIAS);     /* ethernet header at start of buffer */
+      arphdr = (struct arp_hdr *)(arppkt->nb_buff + ETHHDR_SIZE); /* arp header follows */
+      arphdr->ar_hd = ARPHW;     /* net endian arp hardware type (ethernet) */
+      arphdr->ar_pro = ARPIP;
+      arphdr->ar_hln = 6;
+      arphdr->ar_pln = 4;
+      arphdr->ar_op = ARREQ;
+      arphdr->ar_tpa = activehost;        /* target's IP address */
+
+      /* FLOOD TEST MOD: just for grins, rotate our IP address so we 
+       * flood everybody's arp tables. Remember that we store IP 
+       * addresses 
+       */
+      ipaddr = i & (0x00FFFFFE & htonl(~net->snmask));   /* make host portion */
+      arphdr->ar_spa = (net->n_ipaddr | htonl(ipaddr));  /* add net portion */
+
+      MEMCPY(arphdr->ar_sha, net->n_mib->ifPhysAddress, 6);
+      MEMSET(&(ethhdr->e_dst[0]), 0xFF, 6);     /* destination to broadcast (all FFs) */
+      MEMCPY(ethhdr->e_src, net->n_mib->ifPhysAddress, 6);
+      ethhdr->e_type = ET_ARP;   /* 0x0806 - ARP type on ethernet */
+
+#ifdef NO_CC_PACKING    /* move ARP fields to proper network boundaries */
+      {
+         struct arp_wire * arwp  =  (struct  arp_wire *)arphdr;
+         MEMMOVE(&arwp->data[AR_SHA], arphdr->ar_sha, 6);
+         MEMMOVE(&arwp->data[AR_SPA], &arphdr->ar_spa, 4);
+         MEMMOVE(&arwp->data[AR_THA], arphdr->ar_tha, 6);
+         MEMMOVE(&arwp->data[AR_TPA], &arphdr->ar_tpa, 4);
+      }
+#endif   /* NO_CC_PACKING */
+
+      /* send arp request - if a packet oriented send exists, use it: */
+      if (net->pkt_send)
+         e = net->pkt_send(arppkt);    /* driver should free arppkt later */
+      else  /* use old raw send */
+      {
+         e = net->raw_send(arppkt->net, arppkt->nb_buff, arpsize);
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(arppkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      }
+
+      arpReqsOut++;
+      /******** end of code cribbed from et_arp.c: ********/
+
+      if (e < 0)
+      {
+         ns_printf(pio, "ARP flood send error %d on pkt %ld\n",e,i);
+         return -1;
+      }
+      if ((i & 0x0f) == 0x0f)
+         ns_printf(pio, ".");
+   }
+
+   return 0;
+}
+
+int
+setfport(void * pio)
+{
+   char *   cp =  nextarg(((GEN_IO)pio)->inbuf);
+
+   if (!*cp)   /* no arg given */
+   {
+      ns_printf(pio,"flood port number is %ld\n", fport);
+      ns_printf(pio,"To change it, put new number on command line\n");
+      return -1;
+   }
+   fport = (u_short)atoi(cp);
+   return 0;
+}
+
+#define MAXFLOODTARGETS 20
+ip_addr floodtargs[MAXFLOODTARGETS];
+
+int
+udp_flood(void * pio)
+{
+   int      i;          /* index */
+   int      e;          /* tmp error holder */
+   int      send_err;   /* total send error count */
+   int      no_pkt;     /* times packet get failed */
+   u_short  lport;      /* local port for send (random) */
+   PACKET   p;
+   int      addr_index; /* index into floodtargs[] */
+
+   ns_printf(pio, "sending UDP flood of %ld pkts to %u.%u.%u.%u\n", 
+      pktcount, PUSH_IPADDR(activehost) );
+
+   lport = udp_socket();
+   e = send_err = no_pkt = 0;
+
+   addr_index = 0;
+   for (i = 0; i < pktcount; i++)
+   {
+      p = udp_alloc((unsigned)deflength, 0);        /* get packet for sending */
+      if(!p)
+      {
+/*         ns_printf(pio, "pkt alloc failed on send #%d\n", i); */
+         no_pkt++;
+         continue;
+      }
+      p->nb_plen = deflength;
+      /* if floodtargs array has any entries rotate through them, else send all
+       * of the packets to activehost
+       */
+      if(floodtargs[0] == 0)
+         p->fhost = activehost;
+      else
+      {
+         p->fhost = floodtargs[addr_index++];   /* get next host */
+         if(floodtargs[addr_index++] == 0)      /* wrap if at end of list */
+            addr_index = 0;
+      }
+      e = udp_send(lport, fport, p);
+      if(e)
+      {
+         send_err++;
+/*          ns_printf(pio, "UDP send error %d on %d\n", e, i); */
+         continue;
+      }
+   }
+   ns_printf(pio, "sent %d pkts, %d errors, %d no-pkt, last return code: %d\n", 
+      i - no_pkt, send_err, no_pkt, e);
+   return e;
+}
+
+
+int
+flood_addr(void * pio)
+{
+   char *   cp =  nextarg(((GEN_IO)pio)->inbuf);
+   char     arg;     /* first char of second arg - a, d, or l. */
+   char *   hosttext;
+   ip_addr  host;
+   unsigned i;
+
+   if (!*cp)   /* no arg given */
+      goto fa_usage;
+
+   arg = ((*cp) | 0x40);   /* force arg to lowercase */
+
+   if(arg == 'l')     /* user wants list */
+   {
+      ns_printf(pio, "Current flood target list:\n");
+      for(i = 0; i < MAXFLOODTARGETS; i++)
+      {
+         if (floodtargs[i] == 0)
+            break;
+         ns_printf(pio, "%u.%u.%u.%u\n", PUSH_IPADDR(floodtargs[i]));
+      }
+      return 0;
+   }
+   /* make sure arg is 'a' or 'd' ('l' is handled above */
+   if((arg != 'a') && (arg != 'd'))
+   {
+      ns_printf(pio, "Arg must begin with 'a' or 'd'\n");
+      goto fa_usage;
+   }
+   hosttext = nextarg(cp);
+   if(!(*hosttext))
+      goto fa_usage;
+
+   cp = parse_ipad(&host, &i, hosttext);
+   if(cp)
+   {
+      ns_printf(pio, "%s\n", cp);
+      goto fa_usage;
+   }
+
+   for(i = 0; i < MAXFLOODTARGETS; i++)
+   {
+      if((arg == 'a') && (floodtargs[i] == 0))
+      {
+         floodtargs[i] = host;
+         ns_printf(pio, "Added host %u.%u.%u.%u\n", PUSH_IPADDR(host));
+         return 0;
+      }
+      if((arg == 'd') && (floodtargs[i] == host))
+      {
+         floodtargs[i] = 0;
+         ns_printf(pio, "Deleted host %u.%u.%u.%u\n", PUSH_IPADDR(host));
+         for( ; i < (MAXFLOODTARGETS - 1); i++)    /* move up rest of list */
+            floodtargs[i] = floodtargs[i + 1];
+         floodtargs[i] = 0;      /* clear last entry */
+         return 0;
+      }
+   }
+   ns_printf(pio, "Sorry, %s\n", arg=='a'?"flood target table full":"Host not in list");
+   return -1;
+
+fa_usage:
+   ns_printf(pio, "Usage: faddr <add|delete|list> X.X.X.X\n");
+   return -1;
+}
+
+/* tmp storage for queues */
+struct queue bigqback;
+struct queue lilqback;
+
+/* q_drain() - utility routine to drain qsrc into qdest */
+
+static void
+q_drain(struct queue * qsrc, struct queue * qdest)
+{
+   while(qsrc->q_len)
+   {
+      putq(qdest, getq(qsrc));
+   }
+}
+
+int
+bigq_drain(void * pio)
+{
+   int count;
+
+   count = atoi(nextarg(((GEN_IO)pio)->inbuf)); /* get count from arg */
+   if(count == 0)    /* if no count given, move whole queue */
+      count = bigfreeq.q_len;
+
+   ns_printf(pio, "draining %d pkts from bigfreeq into tmp que\n", count);
+   while((count--) && (bigfreeq.q_len))
+      putq(&bigqback, getq(&bigfreeq));
+   return 0;
+}
+
+int
+pktq_drain(void * pio)
+{
+   ns_printf(pio, "draining both free queue into tmp que\n");
+   q_drain(&bigfreeq, &bigqback);
+   q_drain(&lilfreeq, &lilqback);
+   return 0;
+}
+
+int
+freeq_refill(void * pio)
+{
+   ns_printf(pio, "restoring free pkts queues\n");
+   q_drain(&bigqback, &bigfreeq);
+   q_drain(&lilqback, &lilfreeq);
+   return 0;
+}
+
+int
+bigq_refill(void * pio)
+{
+   int count;
+
+   count = atoi(nextarg(((GEN_IO)pio)->inbuf)); /* get count from arg */
+   if(count == 0)    /* if no count given, move whole queue */
+      count = bigfreeq.q_len;
+
+   ns_printf(pio, "restoring %d pkts to bigfreeq from tmp que\n", count);
+   while((count--) && (bigqback.q_len))
+      putq(&bigfreeq, getq(&bigqback));
+   return 0;
+}
+
+#endif   /* TESTMENU - whole file can be ifdeffed away */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tk_crnos.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tk_crnos.c
new file mode 100644
index 0000000..1aea7f5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/tk_crnos.c
@@ -0,0 +1,284 @@
+/*
+ * FILENAME: tk_crnos.c
+ *
+ * Copyright  2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Wrapper and utility Functions to map NicheTask "TK_" macros to ChronOS
+ *
+ * MODULE: MISCLIB
+ *
+ * PORTABLE: yes (within ChronOS & uCOS systems)
+ *
+ * These wrapper functions for native ChronOS functions are dependant on the
+ * the implemenation of the project/target directory osport.c file.
+ *
+ * Modified: 10-21-2008 (skh)
+ */
+
+#include "ipport.h"
+
+#ifdef CHRONOS
+
+#include "ucos_ii.h"
+#include "os_cpu.h"
+
+#include OSPORT_H
+
+extern int num_net_tasks;
+extern struct inet_taskinfo nettasks[];
+
+ /* 
+  * Q and Mutex used by tcp_sleep/wakeup
+  */
+extern OS_EVENT *global_wakeup_Mutex;
+extern struct TCP_PendPost global_TCPwakeup_set[];
+extern int global_TCPwakeup_setIndx;
+extern u_long tcp_sleep_count;
+extern u_long tcp_wakeup_count;
+
+void     TK_OSTaskResume(u_char * Id);
+void     TK_OSTimeDly(void);
+u_char   TK_OSTaskQuery(void);
+
+
+
+void TK_OSTimeDly(void)
+{
+   OSTimeDly(2);
+}
+
+
+
+void TK_OSTaskResume(u_char * Id)
+{
+INT8U err;
+
+   err = OSTaskResume(*Id);
+   
+#ifdef NPDEBUG
+   if ((err != OS_NO_ERR) && (err != OS_TASK_NOT_SUSPENDED))
+   {
+      dprintf("ChronOS API call failure, to Resume Suspended Task!\n");
+      dtrap();
+      panic("TK_OSTaskResume");      
+   }
+#endif
+}
+
+
+
+/* count of the number of times we timed-out waiting on a semaphore */
+u_long tcp_sleep_timeout = 0;
+
+
+/* FUNCTION: tck_sleep()
+ *
+ * Put a task to sleep until an event occurs.
+ * On entry, the caller is holding the NET_RESID resource.
+ *
+ * PARAM1: void *             sleep event object
+ *
+ * RETURN: none
+ */
+void
+tcp_sleep(void * event)
+{
+   int i;
+   INT8U err;
+
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+   {
+      if (global_TCPwakeup_set[i].soc_event == NULL)
+      {
+         global_TCPwakeup_set[i].soc_event = event;
+         global_TCPwakeup_set[i].ctick = cticks;
+         if (i > global_TCPwakeup_setIndx)
+            global_TCPwakeup_setIndx = i;
+
+         tcp_sleep_count++;
+
+         /* Give up the lock before going to sleep. This can
+          * potentially cause a context switch to the task
+          * signaling the event.
+          */
+         UNLOCK_NET_RESOURCE(NET_RESID);
+
+         /* don't wait forever in case we miss the event */
+         OSSemPend(global_TCPwakeup_set[i].semaphore, TPS, &err);
+         if (err == 10)
+         {
+            ++tcp_sleep_timeout;
+
+            /* clear the entry */
+            global_TCPwakeup_set[i].ctick = 0;
+            global_TCPwakeup_set[i].soc_event = NULL;
+         }
+
+         /* Regain the lock */
+         LOCK_NET_RESOURCE(NET_RESID);
+         return;
+      }
+   }
+
+   /* The table is full. Try calling TK_YIELD() and hope for the best.
+    * The user should increase the size of the table.
+    * We'll record the max index for debugging purposes.
+    */
+   global_TCPwakeup_setIndx = i;
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   TK_YIELD();
+   LOCK_NET_RESOURCE(NET_RESID);
+}
+
+
+
+/* FUNCTION: tcp_wakeup()
+ *
+ * Wake up any tasks that might be waiting on this event.
+ *
+ * PARAM1: void *             wakeup event object
+ *
+ * RETURN: none
+ */
+void
+tcp_wakeup(void *event)
+{
+   int i;
+
+   OSSchedLock();
+
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+   {
+      if ((global_TCPwakeup_set[i].ctick != 0) &&
+          (global_TCPwakeup_set[i].soc_event == event))
+      {
+         /* signal the event */
+         OSSemPost(global_TCPwakeup_set[i].semaphore);
+
+         /* clear the entry */
+         global_TCPwakeup_set[i].ctick = 0;
+         global_TCPwakeup_set[i].soc_event = NULL;
+
+         tcp_wakeup_count++;
+      }
+   }
+
+   OSSchedUnlock();
+}
+
+
+
+u_char TK_OSTaskQuery(void)
+{
+   OS_TCB task_data;
+   INT8U err, task_prio;
+
+   err = OSTaskQuery(OS_PRIO_SELF, &task_data);
+
+   if (err == OS_NO_ERR)
+   {
+      task_prio = task_data.OSTCBPrio;
+   }
+   else
+   {
+      dprintf("ChronOS API call failure, unable to identify task!");
+      panic("TK_OSTaskQuery");
+      return 0;
+   }
+   
+   return task_prio;
+}
+
+
+
+void
+tk_yield(void)
+{
+   /* To ensure cycles to the lower priority tasks we should really
+    * delay by two ticks, but that really hurts performance on some
+    * long-tick targets. One tick works better overall....
+    */
+   OSTimeDly(1);
+}
+
+
+extern struct inet_taskinfo * nettask;
+extern int num_net_tasks;
+
+int
+tk_stats(void * pio)
+{
+   int      t;    /* index into ChronOS TCB table */
+   OS_TCB * tcb;  /* ChronOS Task Control Block */
+   OS_STK * sp;   /* scratch stack pointer */
+   int      stackuse;
+   char     name[OS_TASK_NAME_SIZE+1];
+   INT8U    err;
+   
+
+   ns_printf(pio, "ChronOS RTOS stats:\n");
+
+#ifdef NO_INICHE_EXTENSIONS
+   ns_printf(pio, "Context switches; Delay:  %lu\n",
+      OSCtxSwCtr);
+#else
+   ns_printf(pio, "Context switches; Delay:  %lu, Interrupt: %lu\n",
+      OSCtxSwCtr, OSCtxIntCtr);
+#endif
+
+   ns_printf(pio, "       name     prio. state    wakeups stack-size stack-use \n");
+
+   
+   for (t = 0; t <= OS_LOWEST_PRIO ; t++)
+   {
+      /* get pointer to TCB and see if entry is in use and not a mutex */
+      tcb = OSTCBPrioTbl[t];
+      if ((tcb == NULL) || (tcb == (OS_TCB *)1))
+         continue;
+
+      OSTaskNameGet(tcb->OSTCBPrio, (INT8U *)&name, &err);
+
+#ifdef NO_INICHE_EXTENSIONS
+      ns_printf(pio, "%15s %2d    0x%04x,    ---   ",
+                     name, tcb->OSTCBPrio, tcb->OSTCBStat);
+#else
+      ns_printf(pio, "%15s %2d    0x%04x, %9ld,",
+                     name, tcb->OSTCBPrio, tcb->OSTCBStat, tcb->wakeups);
+#endif
+
+      /* Find lowest non-zero value in stack so we can estimate the
+       * unused portion. Subtracting this from size gives us the used
+       * portion of the stack.
+       */
+#if OS_TASK_CREATE_EXT_EN > 0
+      if(tcb->OSTCBStkBottom && tcb->OSTCBStkSize)
+      {
+         sp = tcb->OSTCBStkBottom + 1;
+         while(*sp == 0)
+            sp++;
+         /* This OS traditionally keeps the size in OS_STK (int) units rather
+          * than bytes, so convert back to bytes for display.
+          */
+         stackuse = (tcb->OSTCBStkSize - (sp - tcb->OSTCBStkBottom)) * sizeof(OS_STK);
+         ns_printf(pio, "%6d,      %6d\n",
+            tcb->OSTCBStkSize * sizeof(OS_STK),  stackuse);
+      }
+      else
+#endif
+      {
+         ns_printf(pio, "No stack data\n");
+      }
+   }
+
+   ns_printf(pio, "tcp_sleep_count = %lu, tcp_wakeup_count = %lu\n",
+                  tcp_sleep_count, tcp_wakeup_count);
+   ns_printf(pio, "global_TCPwakeup_setIndx = %d, tcp_sleep_timeout = %lu\n",
+                  global_TCPwakeup_setIndx, tcp_sleep_timeout);
+
+   return 0;
+}
+
+
+#endif /* CHRONOS */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/ttyio.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/ttyio.c
new file mode 100644
index 0000000..126c5b8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/ttyio.c
@@ -0,0 +1,850 @@
+/*
+ * FILENAME: ttyio.c
+ * 
+ * Copyright 1997- 2006 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Portions Copyright 1986 by Carnegie Mellon
+ * Portions Copyright 1984 by the Massachusetts Institute of Technology
+ *
+ * Copyright (c) 1982, 1986, 1988 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation and other 
+ * materials related to such distribution and use acknowledge that 
+ * the software was developed by the University of California, Berkeley.
+ * The name of the University may not be used to endorse or promote 
+ * products derived from this software without specific prior written 
+ * permission. THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * Rights, responsibilities and use of this software are controlled by
+ * the agreement found in the "LICENSE.H" file distributed with this
+ * source code.  "LICENSE.H" may not be removed from this distribution,
+ * modified, enhanced nor references to it omitted.
+ *
+ * This printf currently understands: %d, %x, %u, %ld, %lx, %s, %c, %p.
+ * %lu is treated as %ld; This only works for values up to 2147483647.
+ *
+ * This code is is NOT reentrant or sharable. It 
+ * is designed for DOS TSRs, device drivers, etc. not for a system 
+ * library. If you are working on an embedded system which already 
+ * supports a printf, you should try to use that. Field width support 
+ * is switchable via FIELDWIDTH below.
+ *
+ * Numerics are not trucated to fit field widths.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: dprintf(), printf(), sprintf(), snprintf(), vsnprintf(),
+ * ROUTINES: doprint(), hexword(), hexbyte(), declong(),
+ * ROUTINES: setnum(), fplen()
+ *
+ * PORTABLE: yes
+ */
+
+#define  _IN_TTYIO_  1  /* switch to help out ipport.h */
+
+#include "ipport.h"
+
+/* if target should not use target build environment's printf */
+#ifndef NATIVE_PRINTF
+
+#ifdef PRINTF_STDARG
+#include <stdarg.h>
+#endif
+
+#define  FIELDWIDTH     1        /* flag to switch in Field Width code */
+#define  LINESIZE       144      /* max # chars per field */
+
+int      maxfieldlen = LINESIZE; /* this can be set to control precision */
+
+#ifdef FIELDWIDTH
+int   setnum(char **);           /* fetch fieldwidth value from string */
+int   fplen(CONST char *, void *);     /* get field length of var */
+#endif   /* FIELDWIDTH */
+
+char     digits[] =  {"0123456789ABCDEF"};
+
+#ifdef PRINTF_STDARG
+int doprint(char *target, unsigned tlen, CONST char *sp, va_list va);
+#else
+int doprint(char *target, unsigned tlen, char *sp, int *vp);
+#endif
+
+extern void  dputchar(int chr);         /* port-defined putchar substitue */
+
+#ifdef dprintf
+#undef dprintf
+#endif
+
+#ifdef printf
+#undef printf
+#endif
+
+#define doputchar(c) {outctxp->outlen++;if(outctxp->target){if(outctxp->outlen < outctxp->tlen) *(outctxp->target++) = c;}else dputchar(c);}
+
+#ifdef PRINTF_STDARG
+
+/* FUNCTION: dprintf()
+ * 
+ * PARAM1: char * fmt
+ * PARAM2: ...
+ *
+ * RETURNS: int n           number of characters output
+ */
+
+int 
+dprintf(CONST char * fmt, ...)
+{
+   va_list a;
+   int n;
+
+   va_start(a, fmt);
+   n = doprint(NULL, 32767, fmt, a);
+   va_end(a);
+
+   return (n);
+}
+
+
+/* FUNCTION: printf()
+ * 
+ * PARAM1: char * fmt
+ * PARAM2: ...
+ *
+ * RETURNS: 
+ */
+int
+printf(CONST char * fmt, ...)
+{
+   va_list a;
+   int n;
+
+   va_start(a, fmt);
+   n = doprint(NULL, 32767, fmt, a);
+   va_end(a);
+
+   return (n);
+}
+
+#ifndef NATIVE_SPRINTF
+
+/* FUNCTION: sprintf()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: char * fmt
+ * PARAM3: ...
+ *
+ * RETURNS: 
+ */
+
+int
+sprintf(char * buf, CONST char *   fmt, ...)
+{
+   va_list a;
+   int n;
+
+   va_start(a, fmt);
+   n = doprint(buf, 32767, fmt, a);
+   va_end(a);
+
+   return (n);
+}
+#endif   /* NATIVE_SPRINTF */
+
+#ifndef NATIVE_SNPRINTF
+
+/* FUNCTION: snprintf()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned buflen
+ * PARAM3: char * fmt
+ * PARAM4: ...
+ *
+ * RETURNS: 
+ */
+
+int
+snprintf(char * buf, unsigned buflen, CONST char * fmt, ...)
+{
+   va_list a;
+   int len;
+
+   va_start(a, fmt);
+   len = doprint(buf, buflen, fmt, a);
+   va_end(a);
+   return len;
+}
+
+/* FUNCTION: vsnprintf()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned buflen
+ * PARAM3: char * fmt
+ * PARAM4: va_list a
+ *
+ * RETURNS: 
+ */
+int
+vsnprintf(char * buf, unsigned buflen, CONST char * fmt, va_list a)
+{
+   return doprint(buf, buflen, fmt, a);
+}
+
+int
+vsprintf(char * buf, CONST char * fmt, va_list a)
+{
+   return(vsnprintf(buf, 32767, fmt, a));
+}
+
+#endif   /* NATIVE_SNPRINTF */
+
+#else    /* PRINTF_STDARG */
+
+/* FUNCTION: dprintf()
+ * 
+ * PARAM1: char *sp
+ * PARAM2: int var
+ *
+ * RETURNS: 
+ */
+
+void
+dprintf(char * sp,      /* pointer to format string */
+   int   var)  /* 1st of n variables on stack */
+{
+   doprint(NULL, 32767, sp, &var);   /* printf to stdio */
+}
+
+
+
+/* FUNCTION: printf()
+ * 
+ * PARAM1: char *sp
+ * PARAM2: int var
+ *
+ * RETURNS: 
+ */
+
+void
+printf(char * sp, /* pointer to format string */
+   int   var)  /* 1st of n variables on stack */
+{
+   doprint(NULL, 32767, sp, &var);   /* printf to stdio */
+}
+
+#ifndef NATIVE_SPRINTF
+
+/* FUNCTION: sprintf()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: char * fmt
+ * PARAM3: int arg1
+ *
+ * RETURNS: 
+ */
+
+void
+sprintf(char * buf, char * fmt, int arg1)
+{
+   doprint(buf, 32767, fmt, &arg1);
+}
+#endif   /* NATIVE_SPRINTF */
+
+
+#ifndef NATIVE_SNPRINTF
+
+/* FUNCTION: snprintf()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned buflen
+ * PARAM3: char * fmt
+ * PARAM4: int arg1
+ *
+ * RETURNS: 
+ */
+
+int
+snprintf(char * buf, unsigned buflen, char * fmt, int arg1)
+{
+   return doprint(buf, buflen, fmt, &arg1);
+}
+#endif   /* NATIVE_SNPRINTF */
+
+#endif   /* PRINTF_STDARG */
+
+
+/* struct output_ctx - output context, used by doprint() and
+ * its helper functions
+ */
+struct output_ctx {
+   char * target;  
+   unsigned tlen;
+   unsigned outlen;
+};
+
+/* local doprint helper routines. All take target as in doprint() */
+static void hexbyte(struct output_ctx * outctxp,
+                    unsigned x);
+static void hexword(struct output_ctx * outctxp,
+                    unsigned x);
+static void declong(struct output_ctx * outctxp,
+                    long lg);
+
+/* FUNCTION: doprint()
+ * 
+ * PARAM1: char * target; NULL for output to stdio, else buffer pointer
+ * PARAM2: int tlen; target buffer length in bytes (ignored for stdio)
+ * PARAM3: char * sp; printf()-style format string
+ * PARAM4: va_list va; pointer to variables
+ *
+ * RETURNS: number of characters that would have been printed in a 
+ *          target buffer of infinite length, not including the
+ *          trailing '\0'
+ */
+
+int
+doprint(char *target,
+        unsigned tlen,
+        CONST char *sp,
+#ifdef PRINTF_STDARG
+        va_list va)
+#else
+        int *vp)         /* pointer to variables for tools w/o <stdarg.h> */ 
+#endif   /* PRINTF_STDARG */
+{
+   char *cp;
+   unsigned prefill, postfill, fieldlen;     /* varibles for field len padding */
+   int   swap;       /* flag and temp holder for prefill-postfill swap */
+   unsigned char fillchar;
+   unsigned minfieldlen;
+   int   i  =  0;
+   unsigned tmp = 0;
+   unsigned long lng = 0;
+   struct output_ctx outctx;
+   struct output_ctx * outctxp = &outctx;
+#ifdef PRINTF_STDARG
+   unsigned w0 = 0;
+#ifdef SEG16_16
+   unsigned w1;
+#endif
+   int   i0 = 0;
+   unsigned char c = 0;
+   char *   cap = 0;
+   void *   varp;
+#endif   /* PRINTF_STDARG */
+
+   outctx.target = target;
+   outctx.tlen = tlen;
+   outctx.outlen = 0;
+
+   while (*sp)
+   {
+      if (*sp != '%')
+      {
+         doputchar(*sp++);
+         continue;
+      }
+
+      /* fall to here if sp ==> '%' */
+      sp++;       /* point past '%' */
+
+      /* see if any field width control stuff is present */
+      cp = (char *)sp;       /* save pointer to filed width data in cp */
+
+      while (*sp == '-' || (*sp >= '0' && *sp <= '9') || *sp == '.')
+         sp++;       /* scan past field control goodies */
+
+#ifdef PRINTF_STDARG
+      switch (*sp)
+      {
+      case 'p':      /* '%p' - pointer */
+#ifdef SEG16_16   /* do seg:offset variety */
+         w0 = va_arg(va, unsigned);
+         w1 = va_arg(va, unsigned);
+#else /* 32 bit flat */
+         lng = va_arg(va, unsigned long);
+#endif /* SEG16_16 */   /* else fall to 32 bit code */
+         break;
+      case 'x':      /* '%x' - this always does 0 prefill */
+         tmp = va_arg(va, unsigned);
+         break;
+      case 'd':      /* '%d' */
+         i0 = va_arg(va, int);
+         break;
+      case 'u':      /* '%u' */
+         w0 = va_arg(va, unsigned);
+         break;
+      case 'c':      /* '%c' */
+         c = (unsigned char)va_arg(va, unsigned);
+         break;
+      case 's':      /* '%s' */
+         cap = va_arg(va, char *);
+         break;
+      case 'l':
+         if (sp[1] == 'x' || sp[1] == 'd' || sp[1] == 'u')  /* '%lx', '%ld', or '%lu' */
+         {
+            lng = va_arg(va, unsigned long);
+         }
+         /*  else   '%l?', ignore it */
+         break;
+      default:       /* %?, ignore it */
+         break;
+      }  /* end switch *sp */
+#endif   /* PRINTF_STDARG */
+
+#ifdef FIELDWIDTH
+      prefill = postfill = 0;       /* default to no filling */
+      fillchar = ' ';               /* ...but fill with spaces, if filling */
+      swap = TRUE;                  /* ...and swap prefill & postfill */
+      if (sp != cp)  /* if there's field control stuff... */
+      {
+         if (*cp == '-')      /* field is to be left adjusted */
+         {
+            swap = FALSE;     /* leave pXXfill unswaped */
+            cp++;
+         }
+         else swap = TRUE;    /* we will swap prefill & postfill later */
+
+            /* set prefill, postfill for left adjustment */
+         if (*cp == '0')   /* fill char is '0', not space default */
+         {
+            cp++;
+            fillchar = '0';
+         }
+         else fillchar = ' ';
+
+            minfieldlen = setnum(&cp);    /* get number, advance cp */
+#ifdef PRINTF_STDARG
+         switch (*sp)
+         {
+         case 's':
+            varp = (void *)&cap;
+            break;
+         case 'd':
+            varp = (void *)&i0;
+            break;
+         case 'u':
+            varp = (void *)&w0;
+            break;
+         case 'l':
+            varp = (void *)&lng;
+            break;
+            default:
+            varp = NULL;
+            break;
+         }
+         fieldlen = fplen(sp, varp);
+#else
+         fieldlen = fplen(sp, vp);        /* figger display size of this var */
+#endif   /* PRINTF_STDARG */
+         if (*cp == '.')   /* do we have a max field size? */
+         {
+            cp++;       /* point to number past '.' */
+            maxfieldlen = setnum(&cp);
+         }
+         else
+         {
+            maxfieldlen = LINESIZE;
+         }
+
+         if (maxfieldlen < (int)fieldlen)
+         {
+            fieldlen = maxfieldlen;
+         }
+         if (minfieldlen > fieldlen)
+         {
+            postfill = minfieldlen - fieldlen;
+         }
+         else
+         {
+            postfill = 0;
+         }
+         if ((postfill + fieldlen) > LINESIZE)
+         {
+            postfill = 0;   /* sanity check*/
+         }
+      }
+
+      if (swap)      /* caller wanted right adjustment, swap prefill/postfill */
+      {
+         swap = (int)prefill;
+         prefill = postfill;
+         postfill = (unsigned)swap;
+      }
+
+      while (prefill--)
+      {
+         doputchar(fillchar); /* do any pre-field padding */
+      }
+#endif   /* FIELDWIDTH */
+
+
+#ifdef PRINTF_STDARG
+      switch (*sp)
+      {
+      case 'p':      /* '%p' - pointer */
+#ifdef SEG16_16   /* do seg:offset variety */
+         hexword(outctxp, w1);   /* display segment word */
+         doputchar(':');
+         hexword(outctxp, w0);   /* display offset word */
+#else /* 32 bit flat */
+         hexword(outctxp, (unsigned)(lng >> 16));
+         hexword(outctxp, (unsigned)(lng & 0x0000FFFF));
+#endif /* SEG16_16 */   /* else fall to 32 bit code */
+         break;
+      case 'x':      /* '%x' - this always does 0 prefill */
+         if (tmp > 255)
+            hexword(outctxp, tmp);
+         else
+            hexbyte(outctxp, tmp);
+         break;
+      case 'd':      /* '%d' */
+         declong(outctxp, (long) i0);
+         break;
+      case 'u':      /* '%u' */
+         declong(outctxp, (unsigned long) w0);
+         break;
+      case 'c':      /* '%c' */
+         doputchar(c);
+         break;
+      case 's':      /* '%s' */
+         i = 0;
+         while (cap  && (*cap) && (i++ < maxfieldlen))
+            doputchar(*cap++);
+         break;
+      case 'l':
+         sp++;
+         if (*sp == 'x')      /* '%lx' */
+         {
+            hexword(outctxp, (unsigned)(lng >> 16));
+            hexword(outctxp, (unsigned)(lng & 0x0000FFFF));
+         }
+         else if(*sp == 'd' || *sp == 'u')   /* '%ld' or '%lu' */
+         {
+            declong(outctxp, lng);    /* we treat %lu as %ld. */
+         }
+         /*  else   '%l?', ignore it */
+         break;
+      default:       /* %?, ignore it */
+         break;
+      }  /* end switch *sp */
+#else /* PRINTF_STDARG */
+      switch (*sp)
+      {
+      case 'p':      /* '%p' - pointer */
+#ifdef SEG16_16   /* do seg:offset variety */
+         /* display segment word */
+         hexword(outctxp, (unsigned)*(vp+1));
+         doputchar(':');
+         /* display offset word */
+         hexword(outctxp, (unsigned)*vp);
+         vp += 2;          /* bump var pointer past two words */
+#else /* 32 bit flat */
+         lng = *vp;
+         hexword(outctxp, (unsigned)(lng >> 16));
+         hexword(outctxp, (unsigned)(lng & 0x0000FFFF));
+         vp += 4/sizeof(*vp); /* 2 or 1 */ 
+#endif /* SEG16_16 */   /* else fall to 32 bit code */
+         break;
+      case 'x':      /* '%x' - this always does 0 prefill */
+         tmp = *(unsigned *)vp++;
+         if (tmp > 255)
+            hexword(outctxp, tmp);
+         else
+            hexbyte(outctxp, tmp);
+         break;
+      case 'd':      /* '%d' */
+         declong(outctxp, (long)*vp++);
+         break;
+      case 'u':      /* '%u' */
+         declong(outctxp, (unsigned long)*(unsigned *)vp);
+         vp++;
+         break;
+      case 'c':      /* '%c' */
+         doputchar((unsigned char)(*vp++));
+         break;
+      case 's':      /* '%s' */
+         cp = *(char **)vp;
+         vp += sizeof(char*)/sizeof(int);   
+         i = 0;
+         while (*cp && i++ < maxfieldlen)
+            doputchar(*cp++);
+         break;
+      case 'l':
+         sp++;
+         if (*sp == 'x')      /* '%lx' */
+         {
+            /*          lng = *vp;      */
+            lng = *((unsigned long *) vp);
+            hexword(outctxp, (unsigned)(lng >> 16));
+            hexword(outctxp, (unsigned)(lng & 0x0000FFFF));
+            vp += 4/sizeof(*vp); /* 2 or 1 */ 
+         }
+         else if(*sp == 'd' || *sp == 'u')   /* '%ld' or '%lu' */
+         {
+            /* we treat %lu as %ld. */
+            declong(outctxp, *(long  *)vp);
+            vp += 2;
+         }
+         /*  else   '%l?', ignore it */
+         break;
+     default:       /* %?, ignore it */
+         break;
+      }  /* end switch *sp */
+#endif   /* PRINTF_STDARG */
+
+#ifdef   FIELDWIDTH
+      while (postfill--)
+      {
+         doputchar(fillchar);   /* do any post-field padding */
+      }
+#endif   /* FIELDWIDTH */
+
+      sp++;       /* point past '%?' */
+
+   }  /* end while *sp */
+
+   if (outctxp->target)
+      *(outctxp->target) = '\0';   /* Null terminate the string */
+
+   return (int)(outctxp->outlen);
+}
+
+
+
+
+/* FUNCTION: hexword()
+ *
+ * hexword(x) - print 16 bit value as hexadecimal
+ * 
+ * PARAM1: char ** targ
+ * PARAM2: unsigned x
+ *
+ * RETURNS: 
+ */
+
+static void
+hexword(struct output_ctx * outctxp, unsigned x)
+{
+   doputchar(digits[(x >> 12) & 0x0f]);
+   doputchar(digits[(x >>  8) & 0x0f]);
+   doputchar(digits[(x >>  4) & 0x0f]);
+   doputchar(digits[x & 0x0f]);
+}
+
+
+
+/* FUNCTION: hexbyte()
+ * 
+ * PARAM1: char ** targ
+ * PARAM2: unsigned  x
+ *
+ * RETURNS: 
+ */
+
+static void
+hexbyte(struct output_ctx * outctxp, unsigned  x)
+{
+   doputchar(digits[(x >> 4) & 0x0f]);
+   doputchar(digits[x & 0x0f]);
+}
+ 
+
+/* FUNCTION: declong()
+ *
+ * declong(char*, long) - print a long to target as a decimal number. 
+ * Assumes signed, prepends '-' if negative. 
+ *
+ * 
+ * PARAM1: char ** targ
+ * PARAM2: long lg
+ *
+ * RETURNS: 
+ */
+
+/* This should be local to declong, but Microsoft C 5.1 
+ * breaks if it is. They use implicit lib calls to do long integer 
+ * math, and the calls pass pointers to the longs, which assumes the 
+ * longs are in local data space. Sheeeesh. -JB- 
+ */
+long tens;
+
+static void
+declong(struct output_ctx * outctxp, long  lg)
+{
+   int   digit;
+
+   if (lg == 0)
+   {
+      doputchar('0');
+      return;
+   }
+   else if(lg < 0L)
+   {
+      doputchar('-');
+      lg = -lg;
+   }
+
+   /* make "tens" the highest power of 10 smaller than lg */
+   tens = 1;
+   while ((lg/10) >= tens) 
+      tens *= 10;
+
+   while (tens)
+   {
+      digit = (int)(lg/tens);    /* get highest digit in lg */
+
+      doputchar(digits[digit]);
+
+      lg -= ((long)digit * tens);
+      tens /= 10;
+   }
+}
+
+
+#ifdef FIELDWIDTH
+
+/* FUNCTION: setnum()
+ *
+ * returns the value of fieldwidth digits from a 
+ * printf format string. fptr should be a pointer to a pointer to one 
+ * or more fieldwidth digits. On return, is advanced past the digits 
+ * and the value of the digits is returned as an int. 
+ *
+ * 
+ * PARAM1: char ** nptr
+ *
+ * RETURNS: returns the value of fieldwidth digits from a 
+ * printf format string
+ */
+
+int      snval;   /* return value, breaks if on stack */
+
+int
+setnum(char ** nptr)
+{
+   snval = 0;
+
+   while (**nptr >= '0' && **nptr <= '9') /* scan through digits */
+   {
+      snval *= 10;      /* calculate return value */
+      snval += **nptr - '0';
+      /* bump pointer (not pointer to pointer) past valid digits */   
+      (*nptr)++;
+   }
+   return(snval);
+}
+
+
+/* FUNCTION: fplen()
+ *
+ * fplen(sp, varp) - returns the number of chars required to print 
+ * the value pointed to by varp when formatted according to the string 
+ * pointed to by sp. 
+ *
+ * 
+ * PARAM1: char * sp
+ * PARAM2: void * varp
+ *
+ * RETURNS: 
+ */
+
+long     lng1, lng2;    /* scratch value for longs */
+
+int
+fplen(CONST char * sp, void * varp)
+{
+   char *   cp;
+
+   /* define the maximum digits needed to display a long value in 
+    * decimal. Say , sizeof(long) = 4. So it has 8*4=32 bits. 
+    * 2^10=1024. So for every 10 bits, we can show 3 digits. So for 
+    * long, this value would be 32*3/10=96/10=9. And then we add one 
+    * more digit for the roundoff. max_long_dig is used to prevent 
+    * long overflow in lng1. There are better ways to prevent this, 
+    * but very difficult to verify whether we made the perfect fix. 
+    * Hence for now, this should do. 
+    */
+   static int max_long_dig = (8 * sizeof(long) * 3)/10+1;
+
+
+
+   snval = 0;     /* use this for return value */
+   lng1 = 1;   /* for figuring lengths of decimal numbers */
+
+   switch (*sp)      /* switch on conversion char */
+   {
+   case 's':
+      cp = *(char**)varp;
+      while   (*cp++) snval++;
+         return(snval);
+   case 'c':
+      return(1);
+   case 'x':
+      return(4);
+   case 'p':
+      return(9);
+   case 'd':
+   case 'u':
+      lng2 = *(long *)varp;
+      if (lng2 == 0) return(1);
+         if (lng2 < 0)        /* if variable value is negative... */
+      {   if (*sp == 'd')  /* format is signded decimal */ 
+         {   snval++;   /* add space for '-' sign */
+            lng2 = -lng2;
+         }
+         else     /* *sp == 'u' - format is unsigned */
+            lng2 &= 0xffff;
+      }
+      while (lng1 <= lng2)
+      {
+         lng1 *= 10;
+         snval++;
+         if ( snval >= max_long_dig )
+         {
+            /* If we don't stop now, there lng1 will have long overflow */
+            break;
+         }
+      }
+      return(snval);
+   case 'l':
+      switch (*(sp+1))
+      {
+      case 'x':   /* '%lx' always 8 bytes */
+         return(8);
+      case 'u':      /* treat %lu like %ld */
+      case 'd':
+         lng2 = (*(long *)(varp));
+         if (lng2 == 0) return(1);
+            if (lng2 < 0)
+         {
+            snval++;       /* add space for '-' sign */
+            lng2 = -lng2;
+         }
+         while (lng1 <= lng2)
+         {
+            lng1 *= 10;
+            snval++;
+            if ( snval >= max_long_dig )
+            {
+               /* If we don't stop now, there lng1 will have long overflow */
+               break;
+            }
+         }
+         return(snval);
+         default:
+         return(0);
+      }         
+      default:
+      return(0);
+   }
+}
+#endif   /* FIELDWIDTH */
+
+#endif   /* NATIVE_PRINTF */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/udp_echo.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/udp_echo.c
new file mode 100644
index 0000000..c483485
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/udp_echo.c
@@ -0,0 +1,751 @@
+/*
+ * FILENAME: udp_echo.c
+ *
+ * Copyright 1995 - 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Test program for UDP sockets API. Implements UDP echo 
+ * server and client DESIGN DESCRIPTION The structure UdpClient is 
+ * used to maintain per-connection information. (connection is a 
+ * misnomer here. Better word can be operation/transaction).
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: udp_client_add(), udp_client_del(), 
+ * ROUTINES: udp_client_from_pio(), udp_cecho_init(), udp_secho_init(), 
+ * ROUTINES: udp_cecho_close(), udp_secho_close(), udp_sendecho(), 
+ * ROUTINES: udp_send_an_echo(), udp_echo_poll(), udp_echo_init(), 
+ * ROUTINES: udp_echo_cleanup(), udp_echo_stat
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"     /* NetPort embedded system includes */
+
+#ifdef  UDPSTEST        /* whole file can be ifdefed out */
+
+#include "tcpport.h"    /* NetPort embedded system includes */
+#include "in_utils.h"
+
+
+#define  ECHO_PORT               7  /* standard UDP/TCP echo port */
+
+#define  UDP_IDLE                1
+#define  UDP_BUSY                2
+#define  UDP_IDLE_TIMEOUT        600   /* value in seconds */
+                                      /* If a UDP Echo client has not been
+                                         used for this long, delete it */
+SOCKTYPE es_sock =              INVALID_SOCKET; /* echo server socket */
+
+extern   int                    kbhit(void);/* from Microsquash|Borland lib*/
+extern   ip_addr                 activehost; /* host for ping, echo, etc.   */
+extern   char *                  prompt;
+
+static   char *   echodata =    "UDP echo number:            ";
+
+/* List of error codes used by this file */
+#define  UDPE_BASE                  300
+#define  UDPE_BAD_SOCKET            (UDPE_BASE+1)
+#define  UDPE_BIND_FAILED           (UDPE_BASE+2)
+#define  UDPE_CONNECT_FAILED        (UDPE_BASE+3)
+#define  UDPE_ALLOC_ERROR           (UDPE_BASE+4)
+#define  UDPE_SRV_BAD_SOCKET        (UDPE_BASE+5)
+#define  UDPE_SRV_BIND_FAILED       (UDPE_BASE+6)
+#define  UDPE_NO_CONN_FOUND         (UDPE_BASE+7)
+#define  UDPE_NODE_NOT_FOUND        (UDPE_BASE+8)
+#define  UDPE_SRV_CLOSE_ERR         (UDPE_BASE+9)
+#define  UDPE_CLIENT_EXISTS         (UDPE_BASE+10)
+#define  UDPE_ERR_SENDING_ECHO      (UDPE_BASE+11)
+#define  UDPE_TIME_NOT_RIPE         (UDPE_BASE+12)
+
+#define  SUCCESS                    0
+
+/* Structure for holding information regarding a UDP Client connection */
+
+struct UdpClient
+{
+   SOCKTYPE sock;             /* client socket   */
+   void *   pio;              /* Output messages go to this device */
+   ip_addr  rhost;            /* UDP Echos to be sent to this host   */
+   u_long   replies;          /* Number of replies received  */
+   u_long   times;            /* Number of times ECHO is to be sent  */
+   u_long   send_cnt ;        /* Number of the reply to be sent(counter)  */
+   int      state;            /* state of the UDP connection   */
+   u_long   ticks;            /* ClockTick when next EchoPkt is to be sent */
+   u_long   delay;            /* Delay between two Echo packets   */
+   int      len;              /* Lenght of UDP pkt to be sent  */
+   u_long   tot_sent;         /* Total echo pkts sent */
+   u_long   tot_rcvd;         /* Total echo pkts received   */
+   struct   UdpClient * next; /* Pointer to the next client connection  */
+};
+
+typedef struct UdpClient * UDPCLIENT ;
+
+UDPCLIENT udpq;                  /* Start node for queue of UDP clients */
+
+int      udp_client_add(void * pio, SOCKTYPE sock, ip_addr host);
+int      udp_client_del(UDPCLIENT udpclient);
+UDPCLIENT udp_client_from_pio(void * pio);
+int      udp_cecho_init(void * pio);
+int      udp_secho_init(void * pio);
+int      udp_cecho_close(void * pio);
+int      udp_secho_close (void * pio);
+int      udp_sendecho(void * pio, ip_addr rhost, int len, long times);   
+int      udp_send_an_echo(UDPCLIENT udpclient);
+void     udp_echo_poll(void);
+int      udp_echo_init(void);
+void     udp_echo_cleanup(void);
+int      udp_echo_stats(void * pio);
+
+static int in_udpechoq = 0;   /* re-entry/queue protection flag */
+
+
+/* FUNCTION: udp_client_add()
+ *
+ * Add a new client to the Queue. Allocates memory for a new node,
+ * Adds to node to queue,  initializes data members
+ *
+ * PARAM1: void * pio      - GenericIO structure (IN) 
+ * PARAM2: SOCKTYPE sock   - Client Socket (IN)
+ * PARAM3: ip_addr host    - Host to whom echo packets are to be sent 
+ *
+ * RETURNS:  SUCCESS or error number 
+ */
+
+int
+udp_client_add(void * pio, SOCKTYPE sock, ip_addr host)
+{
+   UDPCLIENT tmpclient;
+
+   in_udpechoq++;
+
+   /* Allocate memory */
+   tmpclient = (UDPCLIENT) npalloc( sizeof(struct UdpClient) ) ;
+   if ( tmpclient == NULL )
+   {
+      ns_printf(pio,"Allocation error.\n");
+      in_udpechoq--;
+      return UDPE_ALLOC_ERROR;
+   }
+
+   /* Add the new node to the queue */
+   if ( udpq == NULL )
+   {
+      udpq = tmpclient ;
+      tmpclient->next=NULL;
+   }
+   else
+   {
+      /* Insert it at the beginning */
+      tmpclient->next = udpq;
+      udpq=tmpclient ;
+   }
+
+   /* Initialize data members */
+   tmpclient->sock      = sock;        /* UDP Echo Client's socket           */
+   tmpclient->pio       = pio;      /* Client's I/O device                */
+   tmpclient->rhost     = host;     /* UDP Echo Server's IP addr          */
+   tmpclient->times     = 1;        /* Count of total EchoPkts to be sent */
+   tmpclient->send_cnt  = 0;        /* Num of Echo Pkts sent till now     */
+   tmpclient->ticks     = cticks;   /* Timetick to track sending of echos */
+   tmpclient->state     = UDP_IDLE ;   /* Are we sending UDP Echos? No.      */
+   tmpclient->replies   = 0 ;       /* Num of replies received so far     */
+   tmpclient->len       = 64 ;      /* Default value of Echo Pkt          */
+   tmpclient->tot_sent  = 0;
+   tmpclient->tot_rcvd  = 0;
+
+   in_udpechoq--;
+
+   return SUCCESS ;
+}
+
+
+/* FUNCTION: udp_client_del()
+ *
+ * Purpose : Cleanup stuff for a UDP Echo 
+ * Client Three things to be done here 1. Close the underlying socket 
+ * 2. Remove node from the Q 3. Free the memory used by the node
+ *
+ * PARAM1: UDPCLIENT udpclient - Pointer to UDP Echo Client connection 
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int 
+udp_client_del(UDPCLIENT udpclient)
+{
+   int   e;
+   UDPCLIENT tmpclient,prevclient;
+
+   in_udpechoq++;
+
+   if ( udpclient->sock != INVALID_SOCKET )
+   {
+      /* Close the underlying socket */
+      e = socketclose(udpclient->sock);
+      if (e)
+      {
+         /* socketclose() must have free'd the socket. Hence we
+          * can't do
+          * e = t_errno(udpclient->sock);
+          */
+         ns_printf(udpclient->pio,"udp echo: close error %d\n", e);
+      }
+   }
+
+   /* Remove from the q */
+   if ( udpq == udpclient )
+   {
+      /* It is the first node */
+      udpq = udpq->next;
+   }
+   else
+   {
+      prevclient=udpq;
+      tmpclient=udpq->next;
+      while ( tmpclient )
+      {
+         if ( tmpclient == udpclient )
+         {
+            /* Found the node in the list */
+            prevclient->next=tmpclient->next ;
+            break;
+         }
+         else
+         {
+            prevclient=tmpclient;
+            tmpclient=tmpclient->next ;
+         }
+      }
+
+      /* Was the node found in Q ? */
+      if (tmpclient == NULL )
+      {
+         /* Node not found in Q !! */
+         dtrap();
+         in_udpechoq--;
+         return UDPE_NODE_NOT_FOUND ;
+      }
+   }
+
+   npfree(udpclient);
+
+   in_udpechoq--;   
+   return SUCCESS;
+}
+
+
+/* FUNCTION: udp_client_from_pio()
+ *
+ * Return the UDP Echo Client connect for a particular session
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: Pointer to UDPCLIENT; or NULL if connection not found
+ */
+
+UDPCLIENT
+udp_client_from_pio(void * pio)
+{
+   UDPCLIENT tmpclient=udpq;
+
+   while ( tmpclient )
+   {
+      if ( tmpclient->pio == pio )
+         break ;
+      else
+         tmpclient=tmpclient->next;
+   }
+
+   return tmpclient;
+}
+
+
+
+/* FUNCTION: udp_cecho_init()
+ *
+ *  Do the initialization for a 
+ * UDP Echo Client. (for the session identified by pio)
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: SUCCESS  or error number 
+ */
+
+int 
+udp_cecho_init(void * pio)
+{
+   int   e;    /* error holder */
+   struct sockaddr_in   me;   /* my IP info, for bind() */
+   struct sockaddr_in   him;  /* server's IP info, for client connect() */
+   SOCKTYPE sock;
+
+   UDPCLIENT udpclient;
+
+   udpclient=udp_client_from_pio(pio);
+   if (udpclient != NULL )
+   {
+      ns_printf(pio,"UDP Echo Client has already been started.\n");
+      return UDPE_CLIENT_EXISTS ;
+   }
+
+   ns_printf(pio,"udp echo client is starting.\n");
+
+   /* open UDP socket */
+   sock = socket(AF_INET, SOCK_DGRAM, 0);
+   if (sock == INVALID_SOCKET)
+   {
+      ns_printf(pio,"udp_echo: bad socket: %d\n", sock);
+      return UDPE_BAD_SOCKET ;
+   }
+
+   me.sin_family = AF_INET;
+   me.sin_addr.s_addr = INADDR_ANY;
+   me.sin_port = 0;  /* let UDP pick a client port */
+
+   e = bind(sock, (struct sockaddr*)&me, sizeof(me));
+   if (e != 0)
+   {
+      e = t_errno(sock);
+      ns_printf(pio,"udp_echo: bind error: %d\n", e);
+      socketclose(sock);
+      return UDPE_BIND_FAILED;
+   }
+
+   /* make client socket a connected socket */
+   him.sin_family = AF_INET;
+   if (activehost)
+      him.sin_addr.s_addr = activehost;
+   else
+      him.sin_addr.s_addr = 0x0100007f;   /* for testing */
+
+   him.sin_port = htons(ECHO_PORT);
+   e = connect(sock, (struct sockaddr *)&him, sizeof(him));
+   if (e != 0)
+   {
+      e = t_errno(sock);
+      ns_printf(pio,"udp_echo: client connect error: %d\n", e);
+      return UDPE_CONNECT_FAILED;
+   }
+
+   /* put socket into non-blocking mode */
+   setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+
+   udp_client_add(pio,sock,activehost);
+
+   return SUCCESS;
+}
+
+
+
+/* FUNCTION: udp_secho_init()
+ *
+ * Initialize the UDP Echo server ( to listen to UDP port 7)
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int 
+udp_secho_init(void * pio)
+{
+   int   e;    /* error holder */
+   struct sockaddr_in   me;   /* my IP info, for bind() */
+   SOCKTYPE sock;
+
+   if ( es_sock != INVALID_SOCKET )
+   {
+      ns_printf(pio,"udp echo server is already running.\n" );
+      return SUCCESS;
+   }
+   ns_printf(pio,"udp echo server is starting.\n" );
+
+   /* open UDP socket */
+   sock = socket(AF_INET, SOCK_DGRAM, 0);
+   if (sock == INVALID_SOCKET)
+   {
+      ns_printf(pio,"udp_echo: bad socket: %d\n", sock);
+      return UDPE_SRV_BAD_SOCKET;
+   }
+
+   me.sin_family = AF_INET;
+   me.sin_addr.s_addr = INADDR_ANY;
+   me.sin_port = htons(ECHO_PORT);
+
+   e = bind(sock, (struct sockaddr*)&me, sizeof(me));
+   if (e != 0)
+   {
+      e = t_errno(sock);
+      ns_printf(pio,"udp_echo: bind error: %d\n", e);
+      socketclose(sock);
+      return UDPE_SRV_BIND_FAILED;
+   }
+
+   es_sock = sock;
+
+   /* put socket into non-blocking mode */
+   setsockopt(sock, SOL_SOCKET, SO_NBIO, NULL, 0);
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: udp_cecho_close()
+ *
+ * Close the UDP Echo Client for a particular session.
+ * This function in turn calls udp_client_del().
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int
+udp_cecho_close(void * pio)
+{
+   UDPCLIENT udpclient;
+
+   udpclient=udp_client_from_pio(pio);
+   if (udpclient == NULL )
+   {
+      ns_printf(pio,"echo socket not open\n");
+      return UDPE_NO_CONN_FOUND;
+   }
+
+   ns_printf(pio,"udp echo - closing client socket\n");
+
+   udp_client_del(udpclient);
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: udp_secho_close()
+ *
+ * Cleanup the UDP Echo Server
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int
+udp_secho_close(void * pio)
+{
+   int   e=0;
+   SOCKTYPE sock;
+
+   sock = es_sock;
+   es_sock = INVALID_SOCKET;
+
+   if ( sock != INVALID_SOCKET )
+   {
+      ns_printf(pio,"udp echo - closing server socket\n");
+      e = socketclose(sock);
+      if (e)
+      {
+         e = t_errno(sock);
+         ns_printf(pio,"udp echo: close error %d\n", e);
+      }
+   }
+
+   if ( e )
+      return UDPE_SRV_CLOSE_ERR ;
+   else
+      return SUCCESS ;
+}
+
+
+/* FUNCTION: udp_sendecho()
+ *
+ * Send UDP Echo packets to a remote host. When a UDP Echo Client is 
+ * initialized for a session, rhost field is set to the global 
+ * variable activehost. If this function is called for a different 
+ * rhost, then 1. The previous client connection is closed. 2. A new 
+ * client connection is started for this new rhost.
+ *
+ * PARAM1: void * pio
+ * PARAM2: ip_addr rhost   - IP Address of remote host
+ * PARAM3: int len         - Length of packet to be sent
+ * PARAM4: long times      - Number of times packet is to be sent
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int
+udp_sendecho(void * pio,
+   ip_addr rhost,    /* already in net endian */
+   int   len,        /* length to send */
+   long  times)      /* packet length, number of times to send */
+{
+   int   e;
+   UDPCLIENT udpclient;
+
+   udpclient=udp_client_from_pio(pio);
+
+   if (udpclient == NULL || rhost != udpclient->rhost)
+   {
+      if ( udpclient == NULL )
+      {
+         ns_printf(pio,"echo socket not open. Opening....\n");
+      }
+      else
+      {
+         ns_printf(pio,"host changed, restarting client socket \n");
+         udp_client_del(udpclient);
+      }
+
+      activehost = rhost;
+      e = udp_cecho_init(pio);
+      if (e) 
+         return e;
+
+      udpclient=udp_client_from_pio(pio);
+   }
+
+   udpclient->replies   = 0;
+   udpclient->times     = times;
+   udpclient->delay     = pingdelay;
+   udpclient->ticks     = cticks;
+   udpclient->state     = UDP_BUSY ;
+   udpclient->len       = len ;
+   udpclient->send_cnt  = 0 ;
+
+   return udp_send_an_echo(udpclient);
+}
+
+
+/* FUNCTION: udp_send_an_echo()
+ *
+ * Send an Echo packet for a UDP Echo Client.
+ *
+ * PARAM1: UDPCLIENT udpclient
+ *
+ * RETURNS: 0 if SUCCESS or error number
+ */
+
+int
+udp_send_an_echo(UDPCLIENT udpclient)
+{
+   int   e;
+
+   if ( udpclient->ticks > cticks )  
+      return UDPE_TIME_NOT_RIPE ;
+
+   udpclient->ticks += udpclient->delay;  /* Set time for sending next packet*/
+
+   ns_printf(udpclient->pio,"sending UDP echo %ld to %s\n",
+    udpclient->send_cnt,print_ipad(udpclient->rhost));
+
+   sprintf(echodata + 17, "%-9lu", udpclient->send_cnt );
+   e = t_send(udpclient->sock, echodata, udpclient->len, 0);
+   if (e != udpclient->len)
+   {
+      e = t_errno(udpclient->sock);
+      ns_printf(udpclient->pio,"error %d sending UDP echo number %ld\n", e, 
+       udpclient->send_cnt );
+      ns_printf(udpclient->pio,"UDP Echo Server at %s is possibly shut down\n",
+         print_ipad(udpclient->rhost));
+      udp_client_del(udpclient);
+      return UDPE_ERR_SENDING_ECHO ;
+   }
+
+   udpclient->send_cnt ++;
+   udpclient->tot_sent ++;
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: udp_echo_poll()
+ * 
+ * Poll all the UDP Echo related activities. That includes a UDP
+ * Echo Server and UDP Echo Clients for each I/O session.
+ *
+ * PARAM1: 
+ *
+ * RETURNS: void
+ */
+
+static char inbuf[TCP_MSS];
+
+void
+udp_echo_poll()
+{
+   struct sockaddr_in   him;  /* IP info of current rhost */
+   int   len;
+   int   e;
+   UDPCLIENT tmpclient,nextclient;
+
+   in_udpechoq++;    /* don't re-entry from tk_yield() */
+   if (in_udpechoq != 1)
+   {
+      in_udpechoq--;
+      return;
+   }
+
+   /* check for received echo packet */
+   if (es_sock != INVALID_SOCKET)
+   {
+      int   sa_size = sizeof(him);
+      len = recvfrom(es_sock, inbuf, TCP_MSS, 0, (struct sockaddr *)&him, &sa_size);
+      if (len < 0)
+      {
+         e = t_errno(es_sock);
+         if (e != EWOULDBLOCK)
+            dprintf("UDP echo server socket error %d\n", e);
+      }
+      else if(len == 0)
+      {
+         dtrap(); /* socket closed? */
+         udp_secho_close(NULL);
+      }
+      else  /* if(len > 0) */
+         sendto(es_sock, inbuf, len, 0, (struct sockaddr *)&him, sizeof(him));
+   }
+
+   for (tmpclient = udpq; tmpclient; tmpclient = nextclient)
+   {
+      nextclient=tmpclient->next;
+
+      /* check for received echo reply */
+      len = t_recv(tmpclient->sock, inbuf, TCP_MSS, 0);
+      if (len < 0)
+      {
+         e = t_errno(tmpclient->sock);
+         if (e != EWOULDBLOCK)
+            ns_printf(tmpclient->pio,"UDP echo client socket error %d\n", e);
+      }
+      else if(len == 0)
+      {
+         dtrap(); /* socket closed? */
+         tmpclient->sock=INVALID_SOCKET;
+         udp_client_del(tmpclient);
+         continue;
+      }
+      else  /* if(len > 0) - got some echo data */
+      {
+         ns_printf(tmpclient->pio,"UDP echo reply; len:%d, reply:%lu", 
+          len, tmpclient->replies);
+         tmpclient->replies++;
+         tmpclient->tot_rcvd++;
+         /* see if it's one of ours, print number if so */
+         if (strncmp(inbuf, echodata, 16) == 0)
+            ns_printf(tmpclient->pio,", Our send#:%ld",atol((&inbuf[17])));
+         ns_printf(tmpclient->pio,"\n%s",prompt);
+      }
+
+      if ( tmpclient->state == UDP_BUSY )
+      {
+         if ( tmpclient->send_cnt  >= tmpclient->times )
+         {
+            /* Previous "udecho" command has completed */
+            tmpclient->state = UDP_IDLE ;
+         }
+         else
+         {
+            if ( udp_send_an_echo(tmpclient) == SUCCESS )
+               ns_printf(tmpclient->pio,"%s",prompt);
+         }
+      }
+      if ( tmpclient->ticks + (UDP_IDLE_TIMEOUT*TPS) < cticks )
+      {
+         /* This client has been lying around ldle for a long time */
+         ns_printf(tmpclient->pio,"Deleting idle UDP Echo Client.\n%s",prompt);
+         udp_client_del(tmpclient);
+      }
+   }
+
+   in_udpechoq--;
+}
+
+
+
+/* FUNCTION: udp_echo_init()
+ * 
+ * Do the initialization for UDP Echo - start UDP Echo Server
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0 on SUCCESS or error number 
+ */
+
+int
+udp_echo_init(void)
+{
+   return udp_secho_init(NULL);
+}
+
+
+
+/* FUNCTION: udp_echo_cleanup()
+ * 
+ * Clean up UDP Echo Server and UDP Echo Clients.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: 0 on SUCCESS or error number 
+ */
+
+void
+udp_echo_cleanup(void)
+{
+   UDPCLIENT tmpclient=udpq;
+   UDPCLIENT nextclient;
+
+   /* Close the Echo Server sockets */
+   udp_secho_close(NULL);
+
+   /* Do the cleanup for each client connection */
+   while ( tmpclient )
+   {
+      nextclient=tmpclient->next;
+      udp_client_del(tmpclient);
+      tmpclient=nextclient;
+   }
+}
+
+
+
+/* FUNCTION: udp_echo_stats()
+ * 
+ *  Show statistics about all UDP Echo Clients and Servers
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0 on SUCCESS or error number
+ */
+
+int
+udp_echo_stats(void * pio)
+{
+   ns_printf(pio,"Showing UDP Echo statistics.\n");
+   if ( es_sock == INVALID_SOCKET )
+   {
+      ns_printf(pio,"   There are no Server connections.\n");
+   }
+   else
+   {
+      ns_printf(pio,"   There is one Server connection.\n");
+   }
+
+   if ( udpq == NULL )
+      ns_printf(pio,"   There are no Client connections.\n");
+   else
+   {
+      UDPCLIENT tmpclient=udpq;
+      int   cnt=0;
+      while (tmpclient)
+      {
+         cnt++;
+         ns_printf(pio,"   Total pkts for Client %d: sent=%ld,rcvd=%ld\n",
+          cnt,tmpclient->tot_sent,tmpclient->tot_rcvd);
+         tmpclient=tmpclient->next;
+      }
+      ns_printf(pio,"   Total Client connections=%d.\n",cnt);
+   }
+   return SUCCESS;
+}
+
+#endif      /* UDPSTEST */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/misclib/userpass.c b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/userpass.c
new file mode 100644
index 0000000..643bc4e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/misclib/userpass.c
@@ -0,0 +1,237 @@
+/*
+ * FILENAME: userpass.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * userpass.c user & password management for demo TCP/IP application. 
+ * This is used by FTP, WebPort, PPP(pap), and any other network 
+ * protocols which need a user name and password.
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: add_user(), check_permit(), get_password()
+ * ROUTINES: list_users(), menu_add_user(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+#include "in_utils.h"
+#include "userpass.h"
+#include "menu.h"
+
+struct userpass users[NUM_NETUSERS];
+
+
+/* FUNCTION: add_user()
+ *
+ * Add a username & password to the user database.
+ *
+ * PARAM1: char *             username string
+ * PARAM2: char *             password string or NULL
+ * PARAM3: void *             permissions
+ *
+ * RETURNS: int               TRUE if user/password combo accepted, else FALSE 
+ *
+ * The 'permissions' parameter is not used by the demo package,
+ * but could be used for extra checking for the application.
+ * Duplicate user/password combinations are accepted in case two
+ * different apps (e.g. FTP and PPP try to register the same user.
+ * A second entry is not created for duplicate calls. 
+ *
+ * If the username and password match with an existing entry, then
+ * we check if "permissions" is present or not. If "permissions" is
+ * present, then it is used as a new password. Hence the add_user()
+ * call can be used to change the password for an existing user.
+ * Refer change_pwd() for sample use.
+ * 
+ */
+
+int
+add_user(char *username, char *password, void *permissions)
+{
+   int   i;
+
+   if (username == (void *)NULL)
+      return FALSE;  /* don't allow null user */
+
+   if (password == (void *)NULL)
+      password = ""; /* allow null password */
+
+   /* validate parameters */
+   if ((strlen(username) >= MAX_USERLENGTH) ||
+       (strlen(password) >= MAX_USERLENGTH) ||
+       (permissions && (strlen(permissions) >= MAX_USERLENGTH)))
+   {
+      return FALSE;
+   }
+
+   /* look for an empty slot or a matching user/passwd entry */
+   for (i = 0; i < NUM_NETUSERS; i++)
+   {
+      if (users[i].username[0] == 0)      /* found empty slot */
+      {
+         strncpy(users[i].username, username, MAX_USERLENGTH);
+         strncpy(users[i].password, password, MAX_USERLENGTH);
+         users[i].permissions = permissions;
+         return TRUE;
+      }
+      else if ((strcmp(users[i].username, username) == 0) &&
+               (strcmp(users[i].password, password) == 0))
+      {
+         if (permissions) 
+         {
+               /* assume that in this case permissions points to
+                * new password */
+            strncpy(users[i].password, (void *)permissions, MAX_USERLENGTH);
+         }
+         return TRUE;
+      }
+   }
+
+   return FALSE;
+}
+
+
+
+/* FUNCTION: check_permit()
+ *
+ * check_permit() - This is called from applciations which want to 
+ * verify a user/password combination. Two extra parameters are 
+ * provided for the application's use. These are: - appcode is one of 
+ * the defines in userpass.h. this will identify the calling module. 
+ * - permissions. This may be used by apps as needed. 
+ *
+ * 
+ * PARAM1: char *    username
+ * PARAM2: char *    password
+ * PARAM3: int       appcode
+ * PARAM4: void *    permissions
+ *
+ * RETURNS: TRUE if use is allowed, FALSE if not.
+ */
+
+int
+check_permit(char * username, 
+   char *   password, 
+   int      appcode,       /* application which called us */
+   void *   permissions)   /* NULL if not used */
+{
+   int   i;
+
+   for (i = 0; i < NUM_NETUSERS; i++)
+   {
+      if (strcmp(users[i].username, username) == 0)
+         break;
+   }
+
+   if (i >= NUM_NETUSERS)
+      return FALSE;
+
+
+   if (strcmp(users[i].password, password) != 0)
+      return FALSE;
+
+   /* add any further checking based on appcode & permissions here: */
+   USE_ARG(appcode);
+   USE_VOID(permissions); 
+
+   return TRUE;   /* this user is allowed in */
+}
+
+
+/* FUNCTION: get_password()
+ *
+ * get_password() - This is called from applications which want to 
+ * find out the password for a particular user.
+ * 
+ * PARAM1: char *    user
+ *
+ * RETURNS: valid password (if user is found) or NULL.
+ */
+
+char *
+get_password(char * user)
+{
+   int   i;
+
+   for (i = 0; i < NUM_NETUSERS; i++)
+   {
+      if (strcmp(users[i].username, user) == 0)
+         break;
+   }
+
+   if (i >= NUM_NETUSERS)
+      return NULL;
+   else
+      return users[i].password;
+}
+
+#ifdef NET_STATS
+
+/* FUNCTION: list_users()
+ *
+ * add_user() - List all users (username & password) int the database. 
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+
+int
+list_users(void * pio) 
+{
+   int i;
+   int cnt=0;
+
+   ns_printf(pio,"List of users and their passwords.\n");
+   for (i = 0; i < NUM_NETUSERS; i++)
+   {
+      if (users[i].username[0] == 0)
+         continue;   /* empty entry */
+
+       ns_printf(pio, "%s, %s\n", 
+          users[i].username, users[i].password);
+       cnt++;
+   }
+
+   ns_printf(pio,"Total number of users : %d\n",cnt);
+   return 0;
+}
+
+/* FUNCTION: menu_add_user()
+ *
+ * menu_add_user() - Add user from CLI.
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+
+int
+menu_add_user(void * pio) 
+{
+   char * arg =  nextarg(((GEN_IO)pio)->inbuf);
+   char * next;
+
+   if (!arg || !*arg)   /* no arg given */
+   {
+      ns_printf(pio,"Error - User name not specfied\n");
+      ns_printf(pio,"Usage: adduser username, password\n");
+      return -1;
+   }
+
+   next = nextcarg(arg);
+   if (!next)
+   {
+      ns_printf(pio,"Error - Password not specfied\n");
+      ns_printf(pio,"Usage: adduser username, password\n");
+      return -1;
+   }
+   add_user(arg,next,NULL);
+
+   return 0;
+}
+
+#endif
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcpclnt.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcpclnt.c
new file mode 100644
index 0000000..373b73e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcpclnt.c
@@ -0,0 +1,1507 @@
+/*
+ * FILENAME: dhcpclnt.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * DHCP Client code for InterNiche IP stack.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: dhc_get_srv_ipaddr(), dhc_init(), 
+ * ROUTINES: dhc_set_callback(), dhc_upcall(), dhc_buildheader(), 
+ * ROUTINES: dhc_discover(), dhc_rx_offer(), dhc_request(), dhc_setip(), 
+ * ROUTINES: dhc_resetip(), dhc_decline(), dh_getlong(), dhc_extract_opts(), 
+ * ROUTINES: dhc_stats(), dhc_second(), dhc_halt(), dhc_reclaim(), 
+ * ROUTINES: dhc_state_init(), dhc_alldone(), dhc_ifacedone(), 
+ * ROUTINES: dhc_set_state(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. */
+
+#include "ipport.h"
+
+#ifdef DHCP_CLIENT   /* ifdef out whole file */
+
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "udp.h"
+#include "dhcpclnt.h"
+
+/* A lot of the following variables are named similarly to variables 
+ * of similar function in the dhcp server code. n general the 
+ * difference is that the client names start with "dhc_" and the 
+ * server versions 
+ */
+UDPCONN dhc_conn = NULL;
+
+long     xids  =  0x22334455;    /* seed for unique request IDs */
+
+/* DHCP client statistics: */
+ulong      dsc_errors    = 0; /* protocol/implementation runtime errors */
+ulong      dsc_discovers = 0; /* discovers sent */
+ulong      dsc_offers    = 0; /* offers recieved */
+ulong      dsc_requests  = 0; /* requests sent */
+ulong      dsc_acks      = 0; /* acks received */
+ulong      dsc_bpreplys  = 0; /* plain bootp replys received */
+ulong      dsc_declines  = 0; /* declines sent */
+ulong      dsc_releases  = 0; /* releases sent */
+ulong      dsc_naks      = 0; /* naks received */
+ulong      dsc_renew     = 0; /* unicast requests sent to renew lease */
+ulong      dsc_rebind    = 0; /* broadcast requests sent to renew lease */
+ulong      dsc_rlyerrs   = 0; /* runtime errors due to DHCP Relay agents */
+
+/* reqlist contains the list of options to be requested in a DISCOVER 
+ * pkt. reqlist is used only if DHCP_REQLIST is enabled. 
+ */
+#ifdef DHCP_REQLIST
+u_char   reqlist[]   =  {  DHOP_SNMASK,DHOP_ROUTER,   DHOP_DNSRV, DHOP_DOMAIN }  ;
+
+/* u_char reqlist[] = { DHOP_SNMASK,DHOP_ROUTER, DHOP_DNSRV, 
+ * DHOP_DOMAIN,0x2c,0x2e,0x2f }; 
+ */
+int      reqlist_len = sizeof(reqlist)/sizeof(u_char);
+#endif   /* DHCP_REQLIST */
+
+struct dhc_state  dhc_states[MAXNETS]; /* DHCP client state of each net. */
+
+#ifdef NET_STATS
+static char *dhc_state_str[] = 
+{
+   "unused",
+   "init",
+   "init-reboot",
+   "rebooting",
+   "selecting",
+   "requesting",
+   "bound",
+   "renewing",
+   "rebinding",
+   "restarting",
+};
+#endif
+
+#define  DHC_BCASTFLAG  0x8000            /* for the flags field of pkt */
+#define  DHC_INFINITY   0xffffffff        /* That is, "-1" */
+#define  DHC_MAX_TRIES  4                 /* Max num of retires to tbe done */
+#define  DHC_RETRY_TMO  4                 /* Timeout(secs) for retries */
+#define  DHCPDATA       ((void*)0xFFFFFFFD)  /* tag for pass to udp_open() */
+
+/* DHCP functions used within this file */
+int      dhc_upcall      (PACKET pkt, void * data); 
+int      dhc_discover    (int iface);    /* send a dhcp discover packet */
+int      dhc_reclaim     (int iface);    /* try to reclaim previous address */
+int      dhc_setip       (int iface);    /* set iface's IP addr */
+int      dhc_resetip     (int iface);    /* reset iface's IP addr */
+int      dhc_request     (int iface, int xid_flag); /* Send a request */
+int      dhc_rx_offer    (int iface, struct bootp * bp, unsigned bplen);
+int      dhc_decline     (int iface, struct bootp * bp, unsigned bplen);
+int      dhc_buildheader (int iface, struct bootp * outbp);
+int  dhc_extract_opts(int iface, u_char * opts);
+void     dhc_set_state   (int iface, int state);
+
+extern   void fixup_subnet_mask(int netnum);  /* from ipnet.c */
+static long dh_getlong( u_char *ptr ); 
+
+extern char *  dhc_hostname(void);  /* returns a name for this machine */
+extern char * name; /* name of product */
+
+/* DC_DOMAINNAME - domain name to be used for this DHCP Client.
+ * Used for option 81 in the DHCP Request.
+ * Proper value for this macro must be defined in dhcpclnt.h or ipport.h
+ * If it is not defined, then the following value will be used.
+ */
+#ifndef DC_DOMAINNAME
+#define DC_DOMAINNAME  "iniche"
+#endif
+
+/* FUNCTION: dhc_get_srv_ipaddr()
+ * 
+ * PARAM1: u_char *options - the ones after "magic cookie"
+ *
+ * RETURNS: 
+ */
+
+ip_addr 
+dhc_get_srv_ipaddr(u_char *options /* after magic cookie */) 
+{
+    u_char * opts;
+    u_char   optlen;
+   ip_addr srv_ipaddr = 0;
+
+   if ((opts = find_opt(DHOP_SERVER, options)) != NULL) 
+   {
+      opts++;
+      optlen = *opts;
+      opts++;
+      srv_ipaddr = dh_getlong(opts);
+      opts += optlen;
+   }
+
+   return (srv_ipaddr);
+} 
+
+
+/* dhc_init() - this must set up the default fields above, read in 
+ * bootptab file (if supported) and open UDP socket for listens. 
+ * Returns 0 if OK, else negative error code from net.h file 
+ */
+
+
+/* FUNCTION: dhc_init()
+ * 
+ * This must set up the default fields above, read in 
+ * bootptab file (if supported) and open UDP socket for listens. 
+ *
+ * PARAM1: void
+ *
+ * RETURNS: Returns 0 if OK, else negative error code from net.h file 
+ */
+
+int
+dhc_init(void)
+{
+   int   i;
+
+   /* open UDP connection to receive incoming DHCP replys */
+   dhc_conn = udp_open(0L,    /* wildcard foriegn host */
+      BOOTP_SERVER_PORT, BOOTP_CLIENT_PORT,
+      dhc_upcall, DHCPDATA);
+
+   if (!dhc_conn)
+      return ENP_RESOURCE;
+
+   for (i = 0; i < MAXNETS; i++)
+   {
+      dhc_states[i].state = DHCS_UNUSED;
+      dhc_states[i].tries = 0;
+   }
+
+   return 0;
+}
+
+
+
+/* FUNCTION: dhc_set_callback()
+ *
+ * dhc_set_callback() : This interface allows the caller to set a 
+ * calling back for a interface. When DHCP Client gets an ACK, it 
+ * callings this routine. This mechanism is provider so that the 
+ * caller can do some processing when the interface is up (like doing 
+ * initializations or blinking LEDs , etc.). 
+ *
+ * 
+ * PARAM1: int iface
+ * PARAM2: int (*routine)(int
+ * PARAM3: int
+ *
+ * RETURNS: 
+ */
+
+void
+dhc_set_callback(int iface, int (*routine)(int,int) )
+{
+   dhc_states[iface].callback = routine;
+}
+
+
+
+/* FUNCTION: dhc_upcall()
+ *
+ * dhc_upcall() - DHCP client UDP callback. Called from stack 
+ * whenever we get a bootp (or DHCP) reply. Returns 0 or error code. 
+ * . 
+ * 
+ * PARAM1: PACKET pkt
+ * PARAM2: void * data
+ *
+ * RETURNS: If the processing was sucessfull, the packet is freed and 0 is 
+ * returned. Otherwise the packet is NOT free'ed and an error code is 
+ * returned
+ */
+
+int
+dhc_upcall(PACKET pkt, void * data)
+{
+   struct bootp * bp;
+   int      len      =  pkt->nb_plen;  /* len of UDP data - the bootp/dhcp struct */
+   int      dhcptype =  0;    /* DHCP type - not valid if bootp */
+   int      e;
+   int      iface;
+   u_char * opts;          /* scratch options pointer */
+
+   if (data != DHCPDATA)
+   {
+      dtrap();
+      return ENP_LOGIC;    /* internal logic error */
+   }
+
+   /* punt if packet didn't come in a net we sent on */
+   iface = net_num(pkt->net);
+   if (dhc_states[iface].state == DHCS_UNUSED)
+      return ENP_NOT_MINE;
+
+   bp = (struct bootp *)pkt->nb_prot;
+
+   /*   Validate various fields   */
+   if ((len < (sizeof(struct bootp)-BOOTP_OPTSIZE) ) || 
+       (bp->op != BOOTREPLY) ||
+       (*(u_long*)(&bp->options) != RFC1084_MAGIC_COOKIE))
+   {
+      dtrap();
+      dsc_errors++;
+      return ENP_NOT_MINE;
+   }
+
+   /* punt offers or replys which are not for me */
+   if(MEMCMP(bp->chaddr, pkt->net->mib.ifPhysAddress, pkt->net->n_hal))
+      return ENP_NOT_MINE;    /* not an error, just ignore it */
+
+   /* see if it's full DHCP or plain bootp by looking for dhcp type option */
+   opts = find_opt(DHOP_TYPE ,&bp->options[4]);
+   if (opts && *opts == DHOP_TYPE)
+   {
+      dhcptype = *(opts+2);
+      bp->op |= ISDHCP;       /* tag packet for isdhcp() macro */
+   }
+
+   if (isdhcp(bp))
+   {
+      switch (dhcptype)
+      {
+      case DHCP_DISCOVER:
+      case DHCP_REQUEST:
+      case DHCP_DECLINE:
+      case DHCP_RELEASE:
+         dsc_errors++;     /* these should only be upcalled to a server */
+         return ENP_NOT_MINE;
+      }
+
+      switch (dhc_states[iface].state)
+      {
+      case DHCS_INIT:
+      case DHCS_INITREBOOT:
+         /* How can we receive any response when we never sent one */
+      case DHCS_BOUND:
+         /* If there are multiple DHCP Servers, and one of them is slow
+            in responding, we might get OFFER pkts when are in BOUND state */
+         dsc_errors++;     /* these should only be upcalled to a server */
+         return ENP_NOT_MINE;
+      case DHCS_SELECTING:
+         /* We will respond to the first offer packet that we receive ) */
+         if ( dhcptype == DHCP_OFFER ) /* got offer back from server */
+         {
+            dsc_offers++;
+            dhc_states[iface].srv_ipaddr = dhc_get_srv_ipaddr(&bp->options[4]);
+            if (dhc_states[iface].srv_ipaddr == 0 )
+            {
+               dtrap(); /* didn't receive server-identifier option */
+               dsc_errors++;
+               dhc_states[iface].srv_ipaddr = pkt->fhost;   /* Try using fhost */
+            }
+
+            if (bp->hops)
+            {
+               /* OFFER is received via DHCP Relay Agent. Remember the
+                * IP addr of DHCP Relay Agent, so that packets from other
+                * DHCP Relay Agents can be discarded 
+                */
+               dhc_states[iface].rly_ipaddr = pkt->fhost;   /* Try using fhost */
+            }
+            else
+               dhc_states[iface].rly_ipaddr = 0;
+
+            e = dhc_rx_offer(iface,bp,pkt->nb_plen);     /* send request */
+            if (e)
+            {
+               dsc_errors++;
+               dhc_set_state(iface,DHCS_INIT);
+               dtrap();
+               return ENP_NOT_MINE;
+            }
+            else
+               dhc_set_state(iface,DHCS_REQUESTING);
+         }
+         else
+         {
+            /* We can't receive any other packet in this state. 
+             * Report an error and remain in SELECTING state, so that 
+             * an OFFER packet from another DHCP server can be 
+             * accepted. If we timeout waiting for a OFFER packet, 
+             * then dhc_second() will transition to DHCS_INIT state. 
+             */
+            dsc_errors++;
+            if ( dhcptype == DHCP_NAK ) 
+               dsc_naks++;
+            return ENP_NOT_MINE;
+         }
+         break;
+      case DHCS_REQUESTING:
+      case DHCS_REBINDING:
+      case DHCS_RENEWING:
+         /* If the ACK/NACK is not from the same server which sent 
+          * the OFFER packet, then discard it. in DHCS_REBOOTING 
+          * state, srv_ipaddr is 0. Hence don't check in that state 
+          */
+         if ( dhc_states[iface].srv_ipaddr != 
+             dhc_get_srv_ipaddr(&bp->options[4]) )
+         {
+            dsc_errors++;
+            return ENP_NOT_MINE;
+         }
+         if (dhc_states[iface].rly_ipaddr &&
+            (dhc_states[iface].rly_ipaddr != pkt->fhost))
+         {
+            dsc_rlyerrs++;
+            dsc_errors++;
+            return ENP_NOT_MINE;
+         }
+      case DHCS_REBOOTING:
+         if ( dhcptype == DHCP_ACK )   /* Server OKed our request */
+         {
+            dsc_acks++;
+            dhc_extract_opts(iface,&bp->options[4]);
+            if ( dhc_states[iface].lease == DHC_INFINITY )
+            {
+               dhc_states[iface].t1 = DHC_INFINITY ;
+               dhc_states[iface].t2 = DHC_INFINITY ;
+            }
+            else
+            {
+               dhc_states[iface].t1 = dhc_states[iface].lease/2     ;
+               dhc_states[iface].t2 = (dhc_states[iface].lease/8)*7 ;
+            }
+            dhc_states[iface].lease_start = cticks;   /* to calc lease expiry */
+            dhc_states[iface].srv_ipaddr = dhc_get_srv_ipaddr(&bp->options[4]); 
+            if (dhc_states[iface].srv_ipaddr == 0 )
+            {
+               dtrap(); /* didn't receive server-identifier option */
+               dsc_errors++;
+               dhc_states[iface].srv_ipaddr = pkt->fhost;   /* Try using fhost */
+            }
+            if (bp->hops)
+            {
+               /* OFFER is received via DHCP Relay Agent. Remember the
+                * IP addr of DHCP Relay Agent, so that packets from other
+                * DHCP Relay Agents can be discarded 
+                */
+               dhc_states[iface].rly_ipaddr = pkt->fhost;   /* Try using fhost */
+            }
+            else
+               dhc_states[iface].rly_ipaddr = 0;
+
+            dhc_setip(iface);
+            dhc_set_state(iface,DHCS_BOUND);
+         }
+         else if ( dhcptype == DHCP_NAK ) /* Server denied our request */
+         {
+            dhc_set_state(iface,DHCS_INIT);
+            dsc_naks++;
+         }
+         else
+         {
+            /* In REQUESTING state, we might receive a retransmitted
+             * OFFER, which we should discard, but it's not an error,
+             * so we log it.
+             */
+            if ((dhc_states[iface].state == DHCS_REQUESTING) &&
+                (dhcptype == DHCP_OFFER))
+            {
+               dsc_offers++;
+               return ENP_NOT_MINE;
+            }
+            /* In RENEWING, REBINDING, or REBOOTING states, we should
+             * only receive ACK or NAK, and in REQUESTING state we
+             * should only receive ACK or NAK or OFFER; these are
+             * accounted for above, so we log whatever this is as an
+             * error and discard it with no change to our state.
+             */
+            dsc_errors++;
+            return ENP_NOT_MINE;
+         }
+         break;
+      default:    /* bad state */
+         dtrap();
+         dhc_set_state(iface,DHCS_INIT);
+         dsc_errors++;
+         return -1;
+      }
+   }
+   else     /* plain bootp reply */
+   {
+      dsc_bpreplys++;
+      dhc_extract_opts(iface,&bp->options[4]);
+      dhc_states[iface].ipaddr = bp->yiaddr;
+      dhc_setip(iface);
+
+      /* Set values so that DHCP State Machine remains happy */
+      dhc_set_state(iface,DHCS_BOUND);
+      dhc_states[iface].t1    = DHC_INFINITY ;
+   }
+
+   udp_free(pkt);
+   return 0;
+}
+
+
+/* FUNCTION: dhc_buildheader()
+ *
+ * dhc_buildheader() - build BOOTP request header 
+ *
+ * 
+ * PARAM1: int iface
+ * PARAM2: struct bootp * outbp
+ *
+ * RETURNS: Returns 0 on success, else an ENP_ error code. 
+ */
+
+int
+dhc_buildheader(int iface, struct bootp * outbp)
+{
+   int   addrlen;    /* length of hardware address */
+
+   MEMSET(outbp, 0, sizeof(struct bootp));   /* most of this is 0 anyway */
+   outbp->op = BOOTREQUEST;
+
+   /* map SNMPish hardware types into bootp types */
+   switch (nets[iface]->n_mib->ifType)
+   {
+   case ETHERNET:       /* ETHERNET defined in net.h */
+      outbp->htype = ETHHWTYPE;  /* defined in dhcp.h */
+   break;
+   case PPP:
+   case SLIP:
+      outbp->htype = LINEHWTYPE;    /* line type for PPP or SLIP */
+   break;
+      default:
+      dtrap();
+      return ENP_LOGIC;             /* this shouldn't happen */
+   }
+
+   addrlen = min(16, nets[iface]->n_hal);
+   outbp->hlen = (u_char)addrlen;
+   outbp->hops = 0;
+   if(dhc_states[iface].state == DHCS_RENEWING) 
+      outbp->flags = 0; /* Renewing needs unicast */
+   else
+      outbp->flags = htons(DHC_BCASTFLAG); /* Othwise broadcast */
+   outbp->xid = dhc_states[iface].xid;
+   outbp->secs = dhc_states[iface].secs;
+#ifdef NPDEBUG
+   /* make sure net[] has a MAC address, even if length is zero */
+   if(nets[iface]->mib.ifPhysAddress == NULL)
+   {
+      dtrap();
+      return ENP_LOGIC;
+   }
+#endif
+   MEMCPY(outbp->chaddr, nets[iface]->mib.ifPhysAddress, addrlen);
+
+   /* return success */
+   return 0;
+}
+
+unsigned long sysuptime(void);
+
+
+/* FUNCTION: dhc_discover()
+ *
+ * dhc_discover() - Send initial DHCP discovery packet for the passed 
+ * interface. 
+ *
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: Returns 0 if ok, else non-zero ENP_ error. 
+ */
+
+int
+dhc_discover(int iface)
+{
+   PACKET pkt;
+   struct bootp * outbp;   /* pointer to bootp block in buffer to build */
+   u_char * opts;       /* scratch pointer to DHCP options field */
+   long     leasetime;
+   int      e;
+
+   /* get a UDP packet buffer for DHCP sending */
+   pkt = udp_alloc(sizeof(struct bootp), 0);
+   if (!pkt) 
+      return ENP_NOMEM;
+   pkt->nb_plen = sizeof(struct bootp);
+
+   /* start a new DHCP transaction */
+   dhc_states[iface].xid = xids++;
+   dhc_states[iface].secs = (unsigned short)(sysuptime()/100L);
+
+   /* set up DHCP/BOOTP header in buffer */
+   outbp = (struct bootp *)pkt->nb_prot;     /* overlay bootp struct on buffer */
+   e = dhc_buildheader(iface,outbp);
+   if (e)
+      return e;
+
+   /* and turn it into a DHCP DISCOVER packet */
+   *(long*)(&outbp->options) = RFC1084_MAGIC_COOKIE; 
+   opts = &outbp->options[4];    /* encode options after cookie */
+   *opts++ = DHOP_TYPE;
+   *opts++ = 1;   /* length of option field */
+   *opts++ = DHCP_DISCOVER;
+   leasetime = -1L ;    /* ask for infinite lease */
+   PUT_IP_OPT(opts, DHOP_LEASE, leasetime);
+
+   /* if we already have an IP address, try to get it from the server */
+   if (nets[iface]->n_ipaddr != 0)
+   {
+      ip_addr my_ip = htonl(nets[iface]->n_ipaddr);
+      PUT_IP_OPT(opts, DHOP_CADDR, my_ip);
+   }
+
+   /* If there is a list of options to be requested from server, include it*/
+#ifdef DHCP_REQLIST
+   if ( reqlist_len > 0 )
+   {
+      int   i;
+      *opts++ = DHOP_REQLIST ;
+      *opts++ = (u_char)reqlist_len ;
+
+      for (i=0 ; i < reqlist_len ; i++ )
+         *opts++ = reqlist[i];
+   }
+#endif   /* DHCP_REQLIST */
+
+   *opts++ = DHOP_END;
+
+   /* last_tick needs to be set in case we are doing a retry. It 
+    * prevents dhc_second from calling us to do another retry while 
+    * we are stuck 
+    */
+   dhc_states[iface].last_tick = cticks;
+
+   pkt->fhost = 0xFFFFFFFF;   /* broadcast discovery request */
+   pkt->net = nets[iface];    /* send out caller spec'ed net */
+
+   /* we need to change the DHCP state before sending to avoid a 
+    * race condition with the expected reply 
+    */
+   if (dhc_states[iface].state != DHCS_SELECTING)
+      dhc_set_state(iface, DHCS_SELECTING);
+
+   udp_send(BOOTP_SERVER_PORT, BOOTP_CLIENT_PORT, pkt);
+   dsc_discovers++;
+
+   /* state info is the same even if udp_send() failed */
+   dhc_states[iface].last_tick = cticks;     /* set this again, post udp_send */
+   dhc_states[iface].tries++;
+
+   return 0;
+}
+
+
+/* FUNCTION: dhc_rx_offer()
+ *
+ * dhc_rx_offer() - process the received DHCPOFFER Process the 
+ * received DHCP-OFFER and populate dhc_states[]. Then call 
+ * dhc_request() to send a request packet. 
+ *
+ * 
+ * PARAM1: int iface
+ * PARAM2: struct bootp * bp
+ * PARAM3: unsigned bplen
+ *
+ * RETURNS: 0 if OK, else ENP_ error
+ */
+
+int
+dhc_rx_offer(int iface, struct bootp * bp, unsigned bplen)
+{
+   u_char * opts;
+   int   e;
+
+   if (dhc_states[iface].xid != bp->xid)
+      return ENP_NOT_MINE;
+
+   opts = &bp->options[4];    /* examine options after cookie */
+   e = dhc_extract_opts(iface,opts);
+   if (e)   /* parse error? */
+   {
+      dtrap();
+      return e;
+   }
+   if (!bp->yiaddr)  /* require an IP address */
+   {
+      dhc_decline(iface,bp, bplen);
+      return ENP_NOT_MINE;
+   }
+   dhc_states[iface].ipaddr = bp->yiaddr;
+
+   /* if we got here, we must like the offer -- send a DHCP REQUEST */
+   return (dhc_request(iface,FALSE));
+}
+
+
+/* FUNCTION: dhc_request()
+ * 
+ * dhc_request() - called when 
+ * 1. we have received a DHCP offer (via dhc_rx_offer() ). 
+ * 2. we have to renew a lease with a DHCP server. ( via dhc_reclaim() ). 
+ * 3. we have to rebind to a different DHCP server. 
+ * 4. we are in INIT-REBOOT state (via dhc_reclaim() ). 
+ * This should format & send a request. Values are picked from 
+ * dhc_states[]. It handles the specific nuances of a REQUEST 
+ * depending on the state of DHCP Client. It implements the following 
+ * table of RFC2131 (sec 4.3.6). 
+ * --------------------------------------------------------------------- 
+ * |              |INIT-REBOOT |SELECTING |RENEWING   |REBINDING | 
+ * --------------------------------------------------------------------- 
+ * |broad/unicast |broadcast   |broadcast |unicast    |broadcast | 
+ * |server-ip     |MUST NOT    |MUST      |MUST NOT   |MUST NOT  | 
+ * |requested-ip  |MUST        |MUST      |MUST NOT   |MUST NOT  | 
+ * |ciaddr        |zero        |zero      |IP address |IP address| 
+ * --------------------------------------------------------------------- 
+ * In a DISCOVER->OFFER->REQUEST scenario, we need to use the same 
+ * XID, SECS field as in OFFER packet. This is controlled via 
+ * xid_flag. If xid_flag is TRUE, then use a new XID. Else use the 
+ * old one.
+ *
+ * PARAM1: int iface
+ * PARAM2: int xid_flag
+ *
+ * RETURNS:  Returns 0 if ok, else non-zero ENP_ error. 
+ */
+
+int
+dhc_request(int iface,int xid_flag)
+{
+   struct  bootp *   outbp;
+   PACKET  pkt;         /* Outgoing packet */
+   u_char  *   opts; /* scratch pointer to DHCP options field */
+   ip_addr opt_ip;      /* IP address temporary */
+   int      e;       /* error holder */
+
+   /* get a UDP packet buffer for sending DHCP request */
+   pkt = udp_alloc(sizeof(struct bootp) + DHCP_OPTSIZE - BOOTP_OPTSIZE, 0);
+   if (!pkt) 
+      return ENP_NOMEM;
+   pkt->nb_plen = sizeof(struct bootp) - BOOTP_OPTSIZE;
+
+   if ( xid_flag == TRUE )
+   {
+      dhc_states[iface].xid  = xids++;
+      dhc_states[iface].secs = 0;
+   }
+
+   /* build a BOOTP request header */
+   outbp = (struct bootp *)pkt->nb_prot;
+   e     = dhc_buildheader(iface,outbp);
+   if (e)
+      return e;
+
+   /* turn it into a DHCP REQUEST packet */
+   *(long*)(&outbp->options) = RFC1084_MAGIC_COOKIE; 
+   opts    = &outbp->options[4];    /* encode options after cookie */
+   *opts++ = DHOP_TYPE;
+   *opts++ = 1;   /* length of option field */
+   *opts++ = DHCP_REQUEST;
+
+   /* append the options that we want to request */
+   if ((dhc_states[iface].state == DHCS_SELECTING) ||
+       (dhc_states[iface].state == DHCS_REQUESTING) ||
+       (dhc_states[iface].state == DHCS_REBOOTING) ||
+       (dhc_states[iface].state == DHCS_INITREBOOT))
+   {
+      opt_ip = ntohl(dhc_states[iface].ipaddr);
+      PUT_IP_OPT(opts, DHOP_CADDR, opt_ip);
+   }
+   if (dhc_states[iface].snmask)
+   {
+      opt_ip = ntohl(dhc_states[iface].snmask);
+      PUT_IP_OPT(opts, DHOP_SNMASK, opt_ip);
+   }
+   if (dhc_states[iface].defgw)
+   {
+      opt_ip = ntohl(dhc_states[iface].defgw);
+      PUT_IP_OPT(opts, DHOP_ROUTER, opt_ip);
+   }
+#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0)
+   {
+      int   i;
+      u_char * optlen=NULL;
+      for (i = 0; i < DHC_MAXDNSRVS; i++)
+      {
+         if (dhc_states[iface].dnsrv[i])
+         {
+            if (i == 0)
+            {
+               *opts++ = DHOP_DNSRV;
+               optlen  = opts;
+               *opts++ = 0;
+            }
+            /* Copy the IP address in nw byte order */
+            opt_ip = dhc_states[iface].dnsrv[i];
+            MEMCPY((char *)opts, (char *)&opt_ip,4);
+            opts+=4;
+            *optlen += 4;
+         }
+      }
+   }
+#endif
+
+   if (dhc_states[iface].lease)
+   {
+      PUT_IP_OPT(opts, DHOP_LEASE, dhc_states[iface].lease);
+   }
+
+   /* If there is a list of options to be requested from server, include it*/
+#ifdef DHCP_REQLIST
+   if ( reqlist_len > 0 )
+   {
+      int   i;
+      *opts++ = DHOP_REQLIST ;
+      *opts++ = (u_char)reqlist_len ;
+
+      for (i=0 ; i < reqlist_len ; i++ )
+         *opts++ = reqlist[i];
+   }
+#endif   /* DHCP_REQLIST */
+
+   /* only set client IP address (ours) when renewing or rebinding */
+   if ((dhc_states[iface].state == DHCS_RENEWING)
+       || (dhc_states[iface].state == DHCS_REBINDING))
+   {
+      outbp->ciaddr = nets[iface]->n_ipaddr;
+   }
+
+   /* RFC 2131, section 4.3.5 ref to server-ip is option 54 0x36, not 
+    * siaddr: p. 16 number 3: "The client broadcasts a DHCPREQUEST 
+    * message that MUST include the 'server identifier' option to 
+    * indicate which server it has selected. . . ." p. 31 bullet 1: 
+    * "Client inserts the address of the selected server in 'server 
+    * identifier'. . . ." RFC 951, p. 4 definition of 'siaddr' is 
+    * "server IP address; returned in bootreply by server." 
+    */
+   /* Only include server identifier option when selecting a server. */
+   if ((dhc_states[iface].state == DHCS_SELECTING) ||
+       (dhc_states[iface].state == DHCS_REQUESTING))
+   {
+      opt_ip = ntohl(dhc_states[iface].srv_ipaddr);
+      PUT_IP_OPT(opts, DHOP_SERVER, opt_ip);
+   }
+
+#ifdef USE_AUTOIP
+   /* add hostname (code 12) */
+   PUT_STRING_OPT(opts, 12, dhc_hostname()); 
+#endif /* USE_AUTOIP */
+
+   /* Client Fully Qualified Domain Name */
+   PUT_STRING_OPT(opts, 81, DC_DOMAINNAME); 
+   /* Vendor Class Identifier */
+   PUT_STRING_OPT(opts, 60, name); 
+
+   *opts++ = DHOP_END;  /* Mark the end of options */
+
+   /* figure out whether to send via unicast or broadcast */
+   if (dhc_states[iface].state == DHCS_RENEWING)
+   {
+      pkt->fhost = dhc_states[iface].srv_ipaddr;
+   }
+   else
+   {
+      pkt->fhost = 0xFFFFFFFF;   /* broadcast request */
+   }
+
+   pkt->net = nets[iface];    /* send out caller spec'ed net */
+   pkt->nb_plen = (char *)opts - (char *)outbp;
+   udp_send(BOOTP_SERVER_PORT, BOOTP_CLIENT_PORT, pkt);
+   dsc_requests++;
+
+   dhc_states[iface].last_tick = cticks;
+   dhc_states[iface].tries++;
+
+   return 0;   /* return OK code */
+}
+
+
+#ifdef MINI_IP
+
+/* FUNCTION: fixup_subnet_mask()
+ *
+ * This is a workalike to the function of the same name in the ip directory.
+ * If we are using MINI_IP then dhcp needs it's own copy of this.
+ * 
+ * PARAM1: int netnum
+ *
+ * RETURNS: 
+ */
+
+void
+fixup_subnet_mask(int netnum)      /* which of the nets[] to do. */
+{
+   u_long   smask;
+
+   if (m_netp->snmask)  /* if mask is already set, don't bother */
+      return;
+
+   /* things depending on IP address class: */
+   if ((m_netp->n_ipaddr & AMASK) == AADDR)
+      smask = 0xFF000000L;
+   else if((m_netp->n_ipaddr & BMASK) == BADDR)
+      smask = 0xFFFF0000L;
+   else if((m_netp->n_ipaddr & CMASK) == CADDR)
+      smask = 0xFFFFFF00L;
+   else
+   {
+      dtrap();    /* bad logic or setup values */
+      smask = 0xFFFFFF00L;
+   }
+   m_netp->snmask = htonl(smask);
+}
+#endif /* MINI_IP */
+
+
+/* FUNCTION: dhc_setip()
+ *
+ * dhc_setip() : Set the IP address (& other paras) for the interface 
+ * It is called when we have received an ACK. That is, we have the IP 
+ * address and other information needed for this interface. If the 
+ * subnet mask has not been specified by the DHCP Server, then we 
+ * will calculate one from the IP Address using fixup_subnet_mask() 
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: Returns 0 if ok, else non-zero ENP error.
+ */
+
+int
+dhc_setip(int iface)
+{
+   nets[iface]->n_ipaddr = dhc_states[iface].ipaddr;
+   nets[iface]->snmask   = dhc_states[iface].snmask;
+   nets[iface]->n_defgw  = dhc_states[iface].defgw;
+
+   if ( nets[iface]->snmask == 0 )
+   {
+      fixup_subnet_mask(iface);
+      dhc_states[iface].snmask = nets[iface]->snmask; 
+   }
+
+   /* fixup broadcast addresses */
+   nets[iface]->n_netbr    = nets[iface]->n_ipaddr | ~nets[iface]->snmask;
+   nets[iface]->n_netbr42  = nets[iface]->n_ipaddr &  nets[iface]->snmask;
+   nets[iface]->n_subnetbr = nets[iface]->n_ipaddr | ~nets[iface]->snmask;
+
+   return 0;   /* return OK code */
+}
+
+
+/* FUNCTION: dhc_resetip()
+ *
+ * dhc_resetip() : Reset the IP address (& other paras) for the 
+ * interface It is called when we didn't receive a ACK/NAK for the 
+ * interface when RENEWING/REBINDING. 
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: Returns 0 if ok, else non-zero error. 
+ */
+
+int
+dhc_resetip(int iface)
+{
+   /* reset the ipaddress */
+   nets[iface]->n_ipaddr = 0;
+   nets[iface]->snmask   = 0;
+   nets[iface]->n_defgw  = 0;
+
+   /* reset the broadcast addresses */
+   nets[iface]->n_netbr    = 0;
+   nets[iface]->n_netbr42  = 0;
+   nets[iface]->n_subnetbr = 0;
+
+   return 0;   /* return OK code */
+}
+
+
+
+/* FUNCTION: dhc_decline()
+ * 
+ * dhc_decline() - send a decline packet to server. This is usually 
+ * because he didn't send us an IP address. 
+ *
+ * PARAM1: int iface
+ * PARAM2: struct bootp * bp
+ * PARAM3: unsigned bplen
+ *
+ * RETURNS: Returns 0 if ok, else non-zero ENP_ error. 
+ */
+
+int
+dhc_decline(int iface,struct bootp * bp, unsigned bplen)
+{
+   struct bootp * outbp;
+   PACKET pkt;
+   u_char * opts;    /* scratch pointer to DHCP options field */
+
+   /* get a UDP packet buffer for sending DHCP */
+   pkt = udp_alloc(bplen, 0);
+   if (!pkt) 
+      return ENP_NOMEM;
+   pkt->nb_plen = bplen;
+
+   outbp = (struct bootp *)pkt->nb_prot;
+   MEMCPY(outbp, bp, bplen);
+   outbp->op = BOOTREQUEST;
+
+   /* find DHCP TYPE option so we can overwrite it */   
+   opts = find_opt(DHOP_TYPE, &outbp->options[4]);
+   opts += 2;     /* point to actual op code */
+   *opts = DHCP_DECLINE;   /* overwrite op code */
+
+   pkt->fhost = 0xFFFFFFFF;   /* broadcast decline pkt */
+   pkt->net = nets[iface];    /* send out caller speced net */
+   udp_send(BOOTP_SERVER_PORT, BOOTP_CLIENT_PORT, pkt);
+   dsc_declines++;   /* count declines sent */
+   return 0;
+}
+
+
+
+/* FUNCTION: dh_getlong()
+ *
+ * dh_getlong() - routine to extract a 'long' from an arbitrary 
+ * address NB: value is expected to remain in network byte order! 
+ *
+ * 
+ * PARAM1:  u_char *ptr 
+ *
+ * RETURNS: the extracted 32 bit value
+ */
+
+static   long dh_getlong( u_char *ptr )
+{
+     long  v;
+     u_char * p2 =  (u_char *)&v;
+
+   *p2++ = *ptr++;
+   *p2++ = *ptr++;
+   *p2++ = *ptr++;
+   *p2++ = *ptr++;
+
+   return v;
+}
+
+
+/* FUNCTION: dhc_extract_opts()
+ * 
+ * dhc_extract_opts() - extract certain interesting options from the 
+ * options string passed. These options are filled in to the fields 
+ * passed. 
+ *
+ * PARAM1: int iface
+ * PARAM2: u_char * opts
+ *
+ * RETURNS: Returns 0 if opts string was parsed OK, else non-zero if 
+ * there was a parse error. 0 return doesn't mean all (or even any) 
+ * of the options passed were filled in with good values. 
+ */
+
+int
+dhc_extract_opts(int iface, u_char *opts)
+{
+   u_char *end = opts + DHCP_OPTSIZE;  /* limit scope of search */
+   u_char optlen;
+
+   /* first, clear the options */
+   dhc_states[iface].snmask = 0; 
+   dhc_states[iface].defgw = 0; 
+   dhc_states[iface].lease = 0; 
+#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0)
+   MEMSET(dhc_states[iface].dnsrv, 0, sizeof(dhc_states[iface].dnsrv));
+#endif   /* DHC_MAXDNSRVS */
+
+   /* then fill them in from the DHCP data */
+   while (opts <= end)
+   {
+      switch (*opts++)
+      {
+      case DHOP_PAD:
+         break;
+      case DHOP_END:
+         return 0;   /* only good exit point */
+      case DHOP_SNMASK:
+         opts++;
+         dhc_states[iface].snmask = dh_getlong(opts);
+         opts += 4;
+         break;
+      case DHOP_ROUTER:
+         optlen = *opts++;
+         if (optlen >= 4)
+            dhc_states[iface].defgw = dh_getlong(opts);
+         opts += optlen;
+         break;
+      case DHOP_LEASE:
+         opts++;
+         dhc_states[iface].lease = htonl(dh_getlong(opts));
+         opts += 4;
+         break;
+      case DHOP_DNSRV:
+         optlen = *opts++;
+#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0)
+         {
+            int i = 0;
+
+            while ((optlen >= 4) && (i < DHC_MAXDNSRVS))
+            {
+               dhc_states[iface].dnsrv[i] = dh_getlong(opts);
+               optlen -= 4;
+               opts += 4;
+               i++;
+            }
+         }
+#endif   /* DHC_MAXDNSRVS */
+         opts += optlen;
+         break;
+      default:
+         opts += ((*opts) + 1);
+         break;
+      }
+   }
+   dtrap();
+   return -1;
+}
+
+/* dhc_stats() - print dhcp client statistics. Returns 0 if ok, else 
+ * non-zero error. 
+ */
+#ifdef NET_STATS
+
+
+/* FUNCTION: dhc_stats()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int
+dhc_stats(void *pio)
+{
+   int   i;
+   ns_printf(pio ,"dhcp client stats:\n");
+   ns_printf(pio ,"all errors:      %lu\n", dsc_errors);
+   ns_printf(pio ,"discover sent:   %lu\n", dsc_discovers);
+   ns_printf(pio ,"offers rcvd:     %lu\n", dsc_offers);
+   ns_printf(pio ,"requests sent:   %lu\n", dsc_requests);
+   ns_printf(pio ,"acks received:   %lu\n", dsc_acks);
+   ns_printf(pio ,"bootp replys:    %lu\n", dsc_bpreplys);
+   ns_printf(pio ,"declines sent:   %lu\n", dsc_declines);
+   ns_printf(pio ,"releases sent:   %lu\n", dsc_releases);
+   ns_printf(pio ,"naks received:   %lu\n", dsc_naks);
+   ns_printf(pio ,"renew req sent:  %lu\n", dsc_renew);
+   ns_printf(pio ,"rebind req sent: %lu\n", dsc_rebind);
+   ns_printf(pio ,"relay agent errs:%lu\n", dsc_rlyerrs);
+
+   for ( i=0 ; i < MAXNETS ; i++ )
+   {
+      ns_printf(pio ,"Interface %d state = %s\n",i+1,
+       dhc_state_str[ dhc_states[i].state ] );
+      if ( dhc_states[i].state == DHCS_UNUSED )
+         continue;
+      else
+      {
+         ns_printf(pio ,"   tries=%d, xid=%lu, secs=%d\n", 
+          dhc_states[i].tries,dhc_states[i].xid,dhc_states[i].secs);
+         ns_printf(pio ,"   lease=%lu, t1=%lu, t2=%lu\n", 
+          dhc_states[i].lease,dhc_states[i].t1,dhc_states[i].t2);
+         ns_printf(pio ,
+          "   ip=%u.%u.%u.%u, snmask=%u.%u.%u.%u, gw=%u.%u.%u.%u\n", 
+          PUSH_IPADDR(dhc_states[i].ipaddr),
+          PUSH_IPADDR(dhc_states[i].snmask),
+          PUSH_IPADDR(dhc_states[i].defgw)  );
+         ns_printf(pio , "   serverip=%u.%u.%u.%u\n", 
+          PUSH_IPADDR(dhc_states[i].srv_ipaddr) );
+#if defined(DHC_MAXDNSRVS) && (DHC_MAXDNSRVS > 0)
+         {
+            int   dnsindex;
+            for (dnsindex=0; dnsindex < DHC_MAXDNSRVS ; dnsindex++ )
+            {
+               ns_printf(pio , "   DNS%d=%u.%u.%u.%u\n", dnsindex+1,
+                  PUSH_IPADDR(dhc_states[i].dnsrv[dnsindex]) );
+            }
+         }
+#endif
+      }
+   }
+   return 0;
+}
+#endif   /* NET_STATS */
+
+
+/* FUNCTION: dhc_second()
+ *
+ * dhc_second() - dhcp client timer. system should call this once a 
+ * second for retries, lease renewal, etc. 
+ *
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: Returns 0 or ENP_ error code 
+ */
+
+int
+dhc_second(void)
+{
+   int   iface;
+   int   tries;
+   int   e;
+   u_long   half_time;
+
+   for (iface = 0; iface < MAXNETS; iface++)
+   {
+      switch (dhc_states[iface].state)
+      {
+      case DHCS_INIT:         /* Send a discover packet */
+         e = dhc_discover(iface);
+         /* Error while sending a discover packet */
+         if (e)
+         {
+            dtrap();
+            return e;
+         }
+         dhc_set_state(iface,DHCS_SELECTING);
+         break;
+      case DHCS_INITREBOOT:   /* Send a request packet */
+         e = dhc_reclaim(iface);
+         if (e)
+         {
+            dtrap();
+            return e;
+         }
+         dhc_set_state(iface,DHCS_REBOOTING);
+         break;
+      case DHCS_SELECTING:
+         /* Send discover packet on timeout */
+      case DHCS_REBOOTING:
+      case DHCS_REQUESTING:
+         /* Discovery timeout = DHC_RETRY_TMO secs * (2 ** retries), max 64 */
+
+         tries = dhc_states[iface].tries ;
+
+         /* Set the exponential count */
+         if ( tries >= DHC_MAX_TRIES) 
+            tries= DHC_MAX_TRIES;
+         if ( cticks > (dhc_states[iface].last_tick + 
+             (((u_long) (DHC_RETRY_TMO*TPS)) << tries ) ) )
+         {
+            /* Timeout while waiting for a OFFER/ACK/NAK. Retransmit */
+            switch(dhc_states[iface].state)
+            {
+            case DHCS_SELECTING:
+               dhc_discover(iface);
+               break;
+            case DHCS_REQUESTING:
+               dhc_request(iface,FALSE);
+               break;
+            case DHCS_REBOOTING:
+               dhc_reclaim(iface);
+               break;
+            default:
+               dtrap(); /* bogus state */
+               break;
+            }
+         }
+         if ( tries == DHC_MAX_TRIES && 
+             (dhc_states[iface].state !=DHCS_SELECTING) )
+         {
+            /* We have tried enough. Restart from INIT state */
+            dhc_set_state(iface,DHCS_RESTARTING);
+            dhc_resetip(iface);
+            dhc_set_state(iface,DHCS_INIT);
+         }
+         break;
+      case DHCS_REBINDING:
+         /* Check for timeout. Retry if we didn't get a ACK/NAK response. */
+
+         if ( (dhc_states[iface].lease*TPS+dhc_states[iface].lease_start) > cticks )
+         {
+            /* See if we need to retransmit. If we have waiting for 
+             * half the time between last transmit and lease, then we 
+             * need to retransmit. Also the minimum retransmit 
+             * interval is 60 secs. 
+             */
+            half_time = (dhc_states[iface].lease_start + 
+             dhc_states[iface].lease*TPS - 
+             dhc_states[iface].last_tick)/2;
+
+            if ( half_time < 60*TPS )
+               half_time = 60*TPS;
+            if ( dhc_states[iface].last_tick + half_time < cticks )
+            {
+               dhc_request(iface,FALSE);
+            }
+         }
+         else
+         {
+            /* Lease has expired. We didn't receive a ACK/NAK. Hence restart*/
+            dhc_set_state(iface,DHCS_RESTARTING);
+            dhc_resetip(iface);
+            dhc_set_state(iface,DHCS_INIT);
+         }
+         break;
+
+      case DHCS_BOUND:
+         /* Test for lease expiry. The RENEW timer. */
+         if ( (dhc_states[iface].t1 != DHC_INFINITY) &&
+             (((dhc_states[iface].t1*TPS)+dhc_states[iface].lease_start) < cticks ) )
+         {
+            /* Time to renew. Send a UNICAST to the DHCP server */
+            dhc_set_state(iface,DHCS_RENEWING);
+            e = dhc_reclaim(iface); /* unicast */ 
+            if (e)
+            {
+               dtrap();
+               return e;
+            }
+            dsc_renew++;
+         }
+         break;
+      case DHCS_RENEWING:
+         /* Test for lease expiry. The REBIND timer. */
+         if ( (dhc_states[iface].t2*TPS+dhc_states[iface].lease_start) > cticks )
+         {
+            /* See if we need to retransmit. If we have waiting for 
+             * half the time between last transmit and t2, then we 
+             * need to retransmit. Also the minimum retransmit 
+             * interval is 60 secs. 
+             */
+            half_time = (dhc_states[iface].lease_start +
+             dhc_states[iface].t2*TPS - 
+             dhc_states[iface].last_tick)/2;
+
+            if ( half_time < 60*TPS )
+               half_time = 60*TPS;
+            if ( dhc_states[iface].last_tick + half_time < cticks )
+            {
+               dhc_request(iface,FALSE);
+            }
+         }
+         else
+         {
+            /* No Response has come from the Server that assigned our 
+             * IP. Hence send a broadcast packet to see if we can 
+             * lease this IP from some other server 
+             */
+            dhc_set_state(iface,DHCS_REBINDING);
+            e = dhc_request(iface,TRUE);  /* broadcast */
+            if (e)
+            {
+               dtrap();
+               return e;
+            }
+            dsc_rebind++;
+         }
+         break;
+      case DHCS_UNUSED:
+      default:
+         continue;
+      }
+   }
+   return 0;
+}
+
+
+/* FUNCTION: dhc_halt()
+ *
+ * dhc_halt() - stop dhcp all client activity for the passed iface.
+ *
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: void
+ */
+
+void
+dhc_halt(int iface)
+{
+   if (iface < 0 || iface > MAXNETS)
+   {
+      dtrap();
+      return;
+   }
+   /* clear dhc_states entry - (kills retrys) */
+   MEMSET(&dhc_states[iface], 0, sizeof(struct dhc_state));
+   dhc_states[iface].state = DHCS_UNUSED;
+}
+
+
+/* FUNCTION: dhc_reclaim()
+ *
+ * dhc_reclaim() - send a "request" for the address currently in the 
+ * passed interface. This is an alternative to dhc_discover() for 
+ * machines which have previously been assigned an address via DHCP, 
+ * saved it in flash, been through a power cycle, and now want to try 
+ * to reclaim previous address from the server. This works by setting 
+ * parameters of dhc_states[] and calling dhc_request() 
+ *
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: Returns 0 if DHCP request was sent OK, else non-zero error. 
+ */
+
+int   
+dhc_reclaim(int iface)
+{
+   /* punt if IP address is not set */
+   if (nets[iface]->n_ipaddr == 0L)
+   {
+      dtrap();    /* programming bug? */
+      return ENP_LOGIC;
+   }
+
+   dhc_states[iface].ipaddr = nets[iface]->n_ipaddr;
+   dhc_states[iface].snmask = nets[iface]->snmask;
+   dhc_states[iface].defgw  = nets[iface]->n_defgw;
+
+#ifdef IP_ROUTING
+   /* If the DHCP Server is on other network, route the request
+    * from the same DHCP relay agent. To do that, add a route.
+    */
+   if (dhc_states[iface].rly_ipaddr)
+   {
+      if (dhc_states[iface].srv_ipaddr)
+      {
+         /* yes, earlier negotiation was done via a relay agent */
+         if ( !add_route(dhc_states[iface].srv_ipaddr, 0xFFFFFFFF,
+             dhc_states[iface].rly_ipaddr, iface, IPRP_LOCAL))
+         {
+            /* route was not added. check this case */
+            dtrap(); 
+         }
+      }
+      else
+      {
+         /* DHCP relay IP address is set, but DHCP Server IP address is
+          * not set ! How can this happen ?
+          */
+         dtrap();
+      }
+   }
+#endif  /* IP_ROUTING */
+
+   /* send the request */
+   return(dhc_request(iface,TRUE));  
+}
+
+
+/* FUNCTION: dhc_state_init()
+ * 
+ * dhc_state_init() : Initiate the DHCP Client for a interface into a 
+ * starting state. Either INIT or INITREBOOT. If the DHCP Client is 
+ * in INIT state, it would start by sending a DISCOVER packet. If it 
+ * is in INITREBOOT state, it would try to use the earlier IP address 
+ * by sending a REQUEST packet. Returns nothing. 
+ *
+ * PARAM1: int iface
+ * PARAM2: int init_flag
+ *
+ * RETURNS: void
+ */
+
+void 
+dhc_state_init(int iface, int init_flag)
+{
+   int state = (init_flag == TRUE) ? DHCS_INIT : DHCS_INITREBOOT;
+   
+   dhc_set_state(iface, state);
+}
+
+
+/* FUNCTION: dhc_alldone()
+ * 
+ * dhc_alldone() : Check if DHCP activities on all interfaces is done 
+ * or not. 
+ *
+ * PARAM1: void
+ *
+ * RETURNS: Return TRUE if all valid interfaces are done. Return FALSE 
+ * otherwise. 
+ */
+
+int 
+dhc_alldone(void)
+{
+   int   i;
+   for ( i=0 ; i < MAXNETS ; i++ )
+   {
+      if ( ( dhc_states[i].state == DHCS_UNUSED ) || 
+          ( dhc_states[i].state == DHCS_BOUND  )  )
+      {
+         continue ;
+      }
+      else
+      {
+         return FALSE ;
+      }
+   }
+   return TRUE ;
+}
+
+
+/* FUNCTION: dhc_ifacedone()
+ *
+ * dhc_ifacedone() : Check if DHCP activities on a interface is done 
+ * or not. Return TRUE if done (or if DHCP Client is not used on the 
+ * interface). Return FALSE otherwise. 
+ *
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+int 
+dhc_ifacedone(int iface)
+{
+   if ( ( dhc_states[iface].state == DHCS_UNUSED ) || 
+       ( dhc_states[iface].state == DHCS_BOUND  )  )
+   {
+      return TRUE ;
+   }
+   else
+   {
+      return FALSE ;
+   }
+}
+
+
+/* FUNCTION: dhc_set_state()
+ *
+ * dhc_set_state() : Set the new state for the interface and call the 
+ * callback routine. That way applications can track about the state 
+ * of DHCP Client 
+ *
+ * 
+ * PARAM1: int iface
+ * PARAM2: int state
+ *
+ * RETURNS: 
+ */
+
+void dhc_set_state(int iface, int state)
+{
+   dhc_states[iface].state = state; /* Set the new state */
+   dhc_states[iface].tries = 0;     /* Reset the number of tries */
+
+   /* If callback is set, call it */
+   if (dhc_states[iface].callback)
+      dhc_states[iface].callback(iface,state);
+}
+
+#endif   /* DHCP_CLIENT - ifdef out whole file */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcputil.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcputil.c
new file mode 100644
index 0000000..054e204
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/dhcputil.c
@@ -0,0 +1,59 @@
+/*
+ * FILENAME: dhcputil.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * DHCP utilities which apply to both client and server
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: find_opt(),  *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. */
+
+
+#include "ipport.h"
+
+
+#ifdef DHCP_CLIENT   /* find_opt() is used only by DHCP client */
+
+#include "dhcpclnt.h"
+
+
+/* FUNCTION: find_opt()
+ *
+ * find_opt() - Search an options string for a particular option 
+ * code. 
+ *
+ * 
+ * PARAM1: u_char opcode
+ * PARAM2: u_char * opts
+ *
+ * RETURNS:  Return pointer to that code if found, NULL if not found.
+ */
+
+u_char * 
+find_opt(u_char opcode, u_char * opts)
+{
+   u_char * end   =  opts  +  DHCP_OPTSIZE;  /* limit scope of search */
+
+   while (opts < end)
+   {
+      if (*opts == opcode) /* found it */
+         return opts;
+      if (*opts == DHOP_END)  /* end of options; opcode not found */
+         return NULL;
+      if (*opts == DHOP_PAD)  /* PAD has only 1 byte */
+         opts++;
+      else     /* all other options should have a length field */
+         opts += (*(opts+1))+2;
+   }
+   /* no DHOP_END option?? */
+   return NULL;
+}
+
+#endif   /* DHCP_CLIENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/dnsclnt.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/dnsclnt.c
new file mode 100644
index 0000000..7997647
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/dnsclnt.c
@@ -0,0 +1,3628 @@
+/*
+ * FILENAME: dnsclnt.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * DNS Client code for NetPort IP stack
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: dns_query(), dnc_sendreq(), dnc_copyout(), 
+ * ROUTINES: dnc_copyin(), dnc_del(), dnc_new(), dns_check(), 
+ * ROUTINES: badreply(), dns_upcall(), dnc_lookup(), dns_lookup(), 
+ * ROUTINES: gethostbyname(), dns_state(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef DNS_CLIENT    /* ifdef out whole file */
+
+#include <time.h>
+#include "libport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "udp.h"
+#include "dns.h"
+#ifndef MINI_IP
+#include "nptcp.h"
+#endif
+#include "ns.h"
+
+#ifdef IP_V6
+#include "ip6.h"
+#endif
+
+#ifdef DNS_CLIENT_UPDT
+#ifndef NS_DDNS
+#define NS_DDNS
+#endif
+#include "nameser.h"
+#endif
+
+/*#define DEBUG_DNSCLNT_C*/
+
+#define DEFAULT_TTL_TIME 300 /* seconds */
+#define DNS_TTL_FACTOR 1 /* upscale TTL */
+#define DNC_TIMEOUT_TICKS (10 * TPS)
+#define DNS_QUERY_WAIT  1 /* seconds */
+#define DNS_QUERY_RETRY 5
+
+/* List for querie/database records. */
+struct dns_querys * dns_qs = NULL;
+
+unshort  dnsids   =  0x1234;  /* seed for unique request IDs */
+
+/* DNS client statistics: */
+ulong      dnsc_errors = 0;      /* protocol/implementation runtime errors */
+ulong      dnsc_requests = 0;    /* requests sent */
+ulong      dnsc_replies = 0;     /* replys received */
+ulong      dnsc_good = 0;        /* usable replys received */
+ulong      dnsc_tmos = 0;        /* timeouts */
+ulong      dnsc_retry = 0;       /* total retries */
+
+#ifdef DNS_CLIENT_UPDT
+ulong     dnsc_updates = 0;     /* Dynamic DNS Updates sent */
+ip_addr   dns_update_server;    /* IP addr of dynamic update server */
+#endif /* DNS_CLIENT_UPDT */
+
+/* pending requests, can be used as a flag to spin dns_check() task */
+unsigned   dnsc_active = 0;
+
+/* retry info, can be overwritten by application code */
+unsigned dns_firsttry = 4; /* time to first retry, in seconds */
+unsigned dns_trys = 5;     /* max number of retrys */
+
+ip_addr dns_servers[MAXDNSSERVERS]; /* need to be set from NV parameters */
+
+#ifdef  DNS_CLIENT_UPDT
+char    soa_mname[MAXDNSNAME];
+
+/* internal routines */
+static struct hostent* getsoa(char *);
+#endif  /* DNS_CLIENT_UPDT */
+
+/* internal routines */
+static int  dnc_sendreq(struct dns_querys *);
+int  dnc_copyout(char * dest, char * src);
+static int  dnc_copyin(char * dest, char * src, struct dns_hdr * dns);
+static void dnc_del(struct dns_querys *);
+static struct dns_querys * dnc_new(void);
+static int  badreply(struct dns_hdr * dns, char * text);
+static void dnc_set_answer(struct dns_querys *, unshort type, char * cp, int rdlen);
+static int  dnc_lookup(char * name, struct dns_querys ** cacheentry);
+
+
+
+#ifdef DEBUG_DNSCLNT_C
+
+void dump_dns_qs(char *text)
+{
+   struct dns_querys *p;
+   int i;
+#ifdef IP_V6
+   char ip6buf[40];     
+#endif
+
+   if (dns_qs == NULL)
+   {
+      printf("dump_dns_qs(): %s: dns_qs is NULL\n", text);
+      return;
+   }
+
+   printf("dump_dns_qs(): %s\n", text);
+   for (p = dns_qs; p; p = p->next)
+   {
+      printf("dns_names = %s send_time = %lu, expire_time = %lu\n", 
+             p->dns_names, p->send_time, p->expire_time);
+      printf("tries = %lu lport = %lu, id = %lu, replies = %lu \n", 
+             p->tries, p->lport, p->id, p->replies);
+#ifdef IP_V6
+      printf("ipaddrs = %lu ip6addrs = %lu, type = %lu, err = %lu rcode = %lu\n", 
+             p->ipaddrs, p->ip6addrs, p->type, p->err, p->rcode);
+#else
+      printf("ipaddrs = %lu type = %lu, err = %lu rcode = %lu\n", 
+             p->ipaddrs, p->type, p->err, p->rcode);
+#endif
+      printf("auths_ip = %u.%u.%u.%u\n", PUSH_IPADDR(p->auths_ip));
+#ifdef IP_V6
+      printf("auths_ip6 = %s\n", print_ip6((struct in6_addr *)(p->auths_ip6), ip6buf));
+#endif
+      if (p->ipaddrs)
+      {
+         printf("IPv4 addresses: (ipaddr_list)\n");
+         for (i = 0; i < p->ipaddrs; i++)
+         {
+            printf("\t%u.%u.%u.%u\n", PUSH_IPADDR(p->ipaddr_list[i]));
+         }
+      }
+#ifdef IP_V6
+      if (p->ip6addrs)
+      {
+         printf("IPv6 addresses: (ip6_list)\n");
+         for (i = 0; i < p->ip6addrs; i++)
+         {
+            printf("\t%s\n", print_ip6((struct in6_addr *)(&p->ip6_list[i][0]), ip6buf));
+         }
+      }
+#endif
+   }
+}
+
+#endif
+
+
+
+void reverse_string(char * s)
+{
+   int c, i, j;
+   for (i = 0, j =strlen(s)-1; i<j; i++, j--)
+   {
+      c = s[i];
+      s[i] = s[j];
+      s[j] = c;
+   }
+} 
+
+
+
+void reverse_domain_addr(char *dest, char *src)
+{
+   int len;
+   int ti, i;
+   char temp[255];
+
+   dest[0] = '\0';
+   len = strlen(src);
+   ti = 0;
+   for (i = len - 1; i >= 0; i--)
+   {
+      if (src[i] == '.')
+      {
+         temp[ti] = '\0';
+         reverse_string(temp);
+         strcat(dest, temp);
+         strcat(dest, ".");
+         ti = 0;
+      }
+      else
+      {
+         temp[ti] = src[i];
+         ti++;
+      }
+   }
+   temp[ti] = '\0';
+   reverse_string(temp);
+   strcat(dest, temp);
+}
+
+
+
+/* FUNCTION: dns_query()
+ *
+ * dns_query() - starts the process of sending out a DNS request for 
+ * a domain name. This is hardwired for the basic question "what is 
+ * the IP address of named host?". It creates the control structures 
+ * and calls dnc_sendreq() to send the actual packet. Caller should 
+ * poll dns_lookup for results. 
+ *
+ * Old version, for backward API compatibility. This is implemented
+ * as a wrapper for the new function
+ *
+ *
+ * PARAM1: char * name
+ * PARAM2: ip_addr * ip
+ *
+ * RETURNS: Returns 0 if IP address was filled in 
+ * from cache, ENP_SEND_PENDING if query was launched OK, or one of 
+ * the ENP error codes. 
+ */
+
+int
+dns_query(char *name, ip_addr *ip_ptr)
+{
+   int      err;
+   struct dns_querys * dns_entry;
+
+   /* Do query for an "A" record (DNS_TYPE_IPADDR) */
+   err = dns_query_type(name, DNS_TYPE_IPADDR,
+                        (ip_addr)0, (unsigned long)0, &dns_entry);
+
+   if ((err == 0) && (ip_ptr != (ip_addr *)NULL))
+      *ip_ptr = dns_entry->ipaddr_list[0];
+
+   return err;
+}
+
+
+
+/* FUNCTION: dns_query_type()
+ *
+ * New (for v2.0) version of dns_query()
+ * This creates the control structures and calls dnc_sendreq() to
+ * send the DNS query packet. Caller should 
+ * poll dns_lookup for results. 
+ *
+ *
+ * PARAM1: char * name - IN - host name to look up
+ * PARAM2: char type - IN - type of query (V4, V6, SERVER, etc.)
+ * PARAM3: ip address. (for updates) 
+ * PARAM4: ttl (for updates) 
+ * PARAM5: dns_querys ** dnsptr - OUT - dns entry 
+ *
+ * RETURNS: Returns 0 if IP address was filled in 
+ * from cache, ENP_SEND_PENDING if query was launched OK, or one of 
+ * the ENP error codes. 
+ */
+
+int
+dns_query_type(char * name, char type, ip_addr ipaddr,
+               unsigned long ttl, struct dns_querys ** dns_ptr)
+{
+   struct dns_querys *  dns_entry;
+   int   e;
+
+   /* see if we already have an entry for this name in the cache */
+   e = dnc_lookup(name, dns_ptr);
+   if (e == 0) /* no error */
+   {
+      return 0;
+   }
+   else if (e == ENP_SEND_PENDING)   /* waiting for previous query */
+      return e;   
+   
+   /* else find a free entry so we can start a query */
+   dns_entry = dnc_new();
+   if (dns_entry == NULL)
+      return ENP_RESOURCE;
+
+   /* prepare entry for use and copy in name. The name for the query will
+    * be replaced by the reply, and other strings (alias, server name) may
+    * be added to the buffer if room permits.
+    */
+   strncpy(dns_entry->dns_names, name, MAXDNSNAME-1);  /* copy in name */
+
+   dns_entry->tries = 0;      /* no retries yet */
+   dns_entry->id = dnsids++;  /* set ID for this transaction */
+   if (dnsids == 0)              /* don't allow ID of 0 */
+      dnsids++;
+
+   dns_entry->ipaddr_list[0] = 0L;  /* non-zero when it succeeds */
+
+   /* get UDP port for packet, keep for ID */
+   dns_entry->lport = udp_socket();
+   dnsc_active++;       /* maintain global dns pending count */
+   dnsc_requests++;     /* count this request */
+
+#ifdef DNS_CLIENT_UPDT
+   /* load up input parameters for DNS UPDATE request */
+   dns_entry->he.h_z_name = name;
+   dns_entry->he.h_add_ipaddr = ipaddr;
+   dns_entry->he.h_ttl = ttl;
+#endif  /* DNS_CLIENT_UPDT */
+
+   dns_entry->type = type;    /* set type of DNS query */
+   *dns_ptr = dns_entry;      /* return DNS entry */
+
+   e = dnc_sendreq(dns_entry);
+   if (e == 0) /* first packet sent OK */
+      return ENP_SEND_PENDING;
+   else  /* some kind of error */
+      return e;
+
+   USE_ARG(ttl);
+   USE_ARG(ipaddr);
+}
+
+
+
+/* FUNCTION: dnc_sendreq()
+ *
+ * dnc_sendreq() - Sends out a DNS request packet based on the query 
+ * info in dns_entry. This is intended to be called from 
+ * dns_query() or dns_check(). 
+ *
+ * 
+ * PARAM1: int entry
+ *
+ * RETURNS: Returns 0 if OK, or one of the ENP error codes. 
+ */
+
+static int
+dnc_sendreq(struct dns_querys * dns_entry)
+{      
+   PACKET pkt;
+   struct dns_hdr *  dns;  /* outgoing dns header */
+   char *   cp;   /* scratch pointer for building question field */
+   int   server;  /* index of server to use */
+   
+   
+   /* figure out which server to try */
+   for (server = 0; server < MAXDNSSERVERS; server++)
+   {
+      if (dns_servers[server] == 0L)
+         break;
+   }
+   if (server == 0)  /* no servers set? */
+   {
+      dprintf("No DNS servers configured\n");
+      dtrap();
+      return ENP_LOGIC;
+   }
+   server = dns_entry->tries % server;
+
+   /* allocate packet for DNS request */
+   if ((pkt = udp_alloc(MAXDNSUDP, 0)) == NULL)
+      return ENP_RESOURCE;
+
+   /* fill in DNS header. Most fields are cleared to 0s */
+   dns = (struct dns_hdr *)pkt->nb_prot;
+   MEMSET(dns, 0, sizeof(struct dns_hdr));
+   dns->id = dns_entry->id;
+
+#ifdef DNS_CLIENT_UPDT
+   /* If this is an UPDATE packet, format the DNS packet differently */
+   
+   if (dns_entry->type == DNS_UPDT)
+   {
+	  char * domP = NULL;
+
+      dns->qdcount = htons(1);      /* Set zone count to 1 */
+      dns->nscount = htons(1);      /* Set update count to 1 */
+      dns->flags = htons(0x2800);   /* Set opcode field to 5 */
+
+      /* format zone name into UPDATE packet */
+      cp = (char*)(dns + 1);      /* point at next byte past header */
+
+      
+	   /*
+		* get domain name from host name.
+		*/
+	   if ((domP = strstr(dns_entry->he.h_z_name, ".")) == NULL)
+	   {
+         badreply(dns, "bad domain name.\n");
+         return -1;	   
+	   }	  
+	  
+	  cp += dnc_copyout(cp, domP + 1);
+
+      /* finish off zone section. We write these two 16 bit words a
+       * byte at a time since cp may be on an odd address and some
+       * machines
+       */
+      *cp++ = 0;  /* high byte of type */
+      *cp++ = 6;  /* type 6 = soa */
+      *cp++ = 0;  /* high byte of class */
+      *cp++ = 1;  /* class 1 == internet */
+
+
+      /* Put in NAME and TYPE */
+	  /* host name */
+      cp += dnc_copyout(cp, dns_entry->he.h_z_name);
+      *cp++ = 0;  /* high byte of type */
+      *cp++ = 1;  /* type 1 == host address, type 6 = soa */
+      *cp++ = 0;     /* high byte of class */
+	  /* is it a delete? */
+      if (dns_entry->he.h_ttl == 0)
+         *cp++ = (char)DNS_CLASS_NONE;  /* class = NONE */
+      else      
+		 *cp++ = 1;     /* class 1 == internet */
+
+      /* Put in TTL value */
+      *cp++ = (unsigned char)(dns_entry->he.h_ttl >> 24);
+      *cp++ = (unsigned char)(dns_entry->he.h_ttl >> 16);
+      *cp++ = (unsigned char)(dns_entry->he.h_ttl >> 8);
+      *cp++ = (unsigned char)dns_entry->he.h_ttl;
+
+      /* Put in RDLENGTH which is length of ip address ie 4 */
+      *cp++ = 0;  /* low byte of length */
+      *cp++ = 4;
+      /* Put in IP address */
+      MEMCPY(cp, &dns_entry->he.h_add_ipaddr, 4);
+      cp += 4;
+
+      dnsc_updates++;
+   }
+   else
+   {
+#endif  /* DNS_CLIENT_UPDT */
+
+
+      dns->qdcount = htons(1);      /* 1 question */
+      dns->flags = htons(DNSF_RD);  /* Recursion Desired */
+
+      /* format name into question field after header */
+      cp = (char*)(dns + 1);  /* point at next byte past header */
+      cp += dnc_copyout(cp, dns_entry->dns_names);
+
+      /* finish off question field. We write these two 16 bit words a 
+       * byte at a time since cp may be on an odd address and some 
+       * machines 
+       */
+      *cp++ = 0;  /* high byte of type */
+      *cp++ = dns_entry->type;  /* type 1 == host address, type 6 = soa */
+      *cp++ = 0;  /* high byte of class */
+      *cp++ = 1;  /* class 1 == internet */
+
+#ifdef DNS_CLIENT_UPDT  
+   }
+   pkt->fhost = dns_update_server;
+
+#else
+   pkt->fhost = dns_servers[server];
+#endif /* DNS_CLIENT_UPDT */
+   pkt->nb_plen = cp - (char*)dns;     /* length of packet */
+   dns_entry->send_time = cticks;   /* note time we send packet */
+
+   return (udp_send(DNS_PORT, dns_entry->lport, pkt));
+}
+
+
+
+#ifdef DNS_CLIENT_UPDT
+
+static char DDNSZone[MAXDNSNAME];
+
+/* FUNCTION: dns_sendDDNSReq()
+ * 
+ * Create and send a DDNS request
+ *
+ * PARAM1: char *             pointer to zone name
+ * PARAM2: int                length of prerequisites
+ * PARAM3: int                number of prerequisites
+ * PARAM4: char *             pointer to prerequisites
+ * PARAM5: int                length of updates.
+ * PARAM6: int                number of updates
+ * PARAM7: char *             pointer to updates
+ *
+ * RETURNS: int               0 if OK, or one of the ENP_ error codes. 
+ *
+ * Formats and sends a full DDNS req.
+ * Only called by nsddnstest() at the moment.
+ */
+
+int
+dns_sendDDNSReq(char *zone, int lenPreqs, int numPreqs,
+                char *preqsP, int lenUps, int numUps, char *upsP)
+{      
+   PACKET pkt;
+   struct dns_hdr *  dns;  /* outgoing dns header */
+   char *   cp;   /* scratch pointer for building question field */
+   int   server;  /* index of server to use */
+   struct dns_querys *  dns_entry;
+ 
+   /* else find a free entry so we can start a query */
+   dns_entry = dnc_new();
+   if (dns_entry == NULL)
+      return -1;
+
+   /* prepare entry for use and copy in name. The name for the query will
+    * be replaced by the reply, and other strings (alias, server name) may
+    * be added to the buffer if room permits.
+    */
+   strncpy(dns_entry->dns_names, zone, MAXDNSNAME-1);  /* copy in zone */
+   strncpy(DDNSZone, zone, MAXDNSNAME-1);  /* save zone */
+
+   dns_entry->tries = 0;      /* no retries yet */
+   dns_entry->id = dnsids++;  /* set ID for this transaction */
+   if (dnsids == 0)              /* don't allow ID of 0 */
+      dnsids++;
+
+   dns_entry->ipaddr_list[0] = 0L;  /* non-zero when it succeeds */
+
+   /* get UDP port for packet, keep for ID */
+   dns_entry->lport = udp_socket();
+   dnsc_active++;       /* maintain global dns pending count */
+   dnsc_requests++;     /* count this request */
+
+   /* load up input parameters in case it's DNS UPDATE request */
+   dns_entry->he.h_z_name = DDNSZone;
+   dns_entry->he.h_add_ipaddr = 0;
+   dns_entry->he.h_ttl = 0;
+   dns_entry->send_time = cticks;   /* note time we send packet */
+
+   dns_entry->type = NS_UPDATE;    /* set type of DNS query */
+
+   /* allocate packet for DNS request */
+   if ((pkt = udp_alloc(MAXDNSUDP, 0)) == NULL)
+      return ENP_RESOURCE;
+
+   /* fill in DNS header. Most fields are cleared to 0s */
+   dns = (struct dns_hdr *)pkt->nb_prot;
+   MEMSET(dns, 0, sizeof(struct dns_hdr));
+   
+   dns->qdcount = htons(1);      /* Set zone count to 1 */
+   dns->ancount = htons(numPreqs);    /* Set number of prerequisites */
+   dns->nscount = htons(numUps);      /* number of updates */
+   dns->flags = htons(0x2800);   /* Set opcode field to 5 */
+
+   /* format zone name into UPDATE packet */
+   cp = (char *)(dns + 1);      /* point at next byte past header */	  
+  
+   cp += dnc_copyout(cp, zone);
+
+   /* finish off zone section. We write these two 16 bit words a
+    * byte at a time since cp may be on an odd address and some
+    * machines
+    */
+   *cp++ = 0;  /* high byte of type */
+   *cp++ = 6;  /* type 6 = soa */
+   *cp++ = 0;  /* high byte of class */
+   *cp++ = 1;  /* class 1 == internet */
+
+   /* put prereqs. */
+   MEMCPY(cp, preqsP, lenPreqs);
+   cp += lenPreqs;
+
+   /* put updates. */
+   memcpy(cp, upsP, lenUps);
+   cp += lenUps;
+
+   pkt->fhost = dns_update_server;
+
+   pkt->nb_plen = cp - (char *)dns;     /* length of packet */
+   
+   return (udp_send(DNS_PORT, dns_entry->lport, pkt));
+}
+
+#endif  /* DNS_CLIENT_UPDT */
+
+
+
+/* FUNCTION: dnc_copyout()
+ *
+ * dnc_copyout() - copy a domain name from user "dot" text format to 
+ * DNS header format. dest buffer is assumed to be large enough, 
+ * which means at least as big as src string.
+ * 
+ * PARAM1: char * dest
+ * PARAM2: char * src
+ *
+ * RETURNS:  Returns length of string copied. 
+ */
+
+int
+dnc_copyout(char * dest, char * src)
+{
+   int   namelen; /* length of name segment */
+   char *   cp;   /* pointer to dest string we're building */
+   char *   fld, *   next; /* pointers into src */
+
+   cp = dest;
+   next = src; /* will be assigned to "this" on first pass */
+
+   while (next)   /* 1 loop per field in dot-delimited string */
+   {
+      fld = next;
+      next = strchr(fld, '.');   /* find next dot in string */
+      if (next)   /* if not last field... */
+      {
+         namelen = next - fld;   /* length of this field */
+         next++;  /* bump next pointer past dot */
+      }
+      else  /* no dot means end of string */
+         namelen = strlen(fld);
+
+      *cp++ = (char)(namelen & 0xFF);  /* put length in dest buffer */
+      MEMCPY(cp, fld, namelen);     /* follow with string data */
+      cp += namelen;    /* point past name to next length byte */
+   }
+   *cp++ = 0;  /* null terminate string */
+   return (cp - dest);
+}
+
+
+
+/* FUNCTION: dnc_copyin()
+ *
+ * dnc_copyin() - the inverse of copyout above - it copies a dns 
+ * format domain name to "dot" formatting. 
+ *
+ * 
+ * PARAM1: char * dest
+ * PARAM2: char * src
+ * PARAM3: struct dns_hdr * dns
+ *
+ * RETURNS: Returns length of string copied, 0 if error. 
+ */
+
+int
+dnc_copyin(char * dest, char * src, struct dns_hdr * dns)
+{
+   unshort   namelen; /* length of name segment */
+   char *   cp;   /* pointer to dest string we're building */
+   char *   fld, *   next; /* pointers into src */
+   int   donelen;    /* number of bytes moved */
+   unshort offset;
+
+   cp = dest;
+   next = src; /* will be assigned to "this" on first pass */
+   donelen = 0;
+
+   while (next)   /* 1 loop per field in dot-delimited string */
+   {
+      fld = next;
+      namelen = *fld++;
+      if (namelen == 0)
+      break;   /* done */
+      if ((namelen & 0xC0) == 0xC0)
+      {
+         fld--;
+         offset = (unshort)*fld; /* get first byte of offset code */
+         fld++;
+         offset &= 0x3f;             /* mask our high two bits */
+         offset <<= 8;               /* make it high byte of word */
+         offset += (unshort)*fld; /* add low byte of word */
+         fld = offset + (char *)dns;  /* ptr into domain name */
+         namelen = *fld++;
+      }
+      if (namelen + donelen > MAXDNSNAME) /* check for overflow */
+         return 0;   /* error */
+      MEMCPY(cp, fld, namelen);
+      donelen += (namelen+1); /* allow for dot/len byte */
+      cp += namelen;
+      *cp++ = '.';
+      next = fld + namelen;
+   }
+   *(cp-1) = 0;   /* null terminate string (over last dot) */
+   return donelen + 1;  /* include null in count */
+}
+
+
+
+/* FUNCTION: dnc_del()
+ *
+ * Delete a DNS entry
+ *
+ * PARAM1: dns_querys *       ptr to entry to delete
+ *
+ * RETURN: none
+ */
+
+static void
+dnc_del(struct dns_querys *entry)
+{
+   struct dns_querys *tmp, *last;
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dnc_del()");
+#endif
+
+   /* find passed dns entry in list */
+   last = (struct dns_querys *)NULL;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   for (tmp = dns_qs; tmp; tmp = tmp->next)
+   {
+      if (tmp == entry)  /* found entry in list */
+      {
+         if (last)          /* unlink */
+            last->next = tmp->next;
+         else
+            dns_qs = tmp->next;
+         break;
+      }
+      last = tmp;
+   }
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   DNC_FREE(entry);  /* free the memory */
+   dnsc_active--;    /* one less active entry */
+}
+
+
+
+/* FUNCTION: dnc_ageout()
+ *
+ * See if we can age out any of the DNS entries.
+ * 
+ * PARAM1: void
+ *
+ * RETURNS: void
+ */
+
+static void
+dnc_ageout()
+{
+   struct dns_querys *dns_entry, *tmpp;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   /* See if we can expire any old entries */
+   for (dns_entry = dns_qs; dns_entry; dns_entry = tmpp)
+   {
+      tmpp = dns_entry->next;
+      if ((dns_entry->ipaddrs != 0)
+#ifdef IP_V6
+          || (dns_entry->ip6addrs != 0)
+#endif
+         )
+      {
+         /* If entry has expired then delete it. */
+         if ((cticks - dns_entry->send_time) > (dns_entry->expire_time * TPS))
+         {
+            dnc_del(dns_entry);
+         }
+      }
+   }
+   UNLOCK_NET_RESOURCE(NET_RESID);
+}
+
+
+
+/* FUNCTION: dnc_new()
+ *
+ * Create a new DNS cache entry
+ *
+ * PARAMS: none
+ *
+ * RETURN: dns_querys *       ptr to new entry or NULL
+ */
+
+static struct dns_querys *
+dnc_new(void)
+{
+   struct dns_querys * dns_entry;
+
+   dns_entry = DNC_ALLOC(sizeof(struct dns_querys));  /* get new entry */
+   if (dns_entry)
+   {
+       /* set respose code to an illegal value. Response will overwrite */
+       dns_entry->rcode = DNSRC_UNSET;
+
+       /* set legacy hostent alias pointer to dns_entry alias list */
+       dns_entry->he.h_aliases = &dns_entry->alist[0];
+
+       /* Put new entry in the DNS database/request list */
+       LOCK_NET_RESOURCE(NET_RESID);
+       dns_entry->next = dns_qs;
+       dns_qs = dns_entry;
+       UNLOCK_NET_RESOURCE(NET_RESID);
+   }
+
+   return dns_entry;
+}
+
+
+
+/* FUNCTION: dns_check()
+ *
+ * Periodic check for DNS client activity
+ *
+ * PARAMS: none
+ *
+ * RETURN: none
+ *
+ * Poll once a second to drive DNS timeouts and 
+ * retrys. Can be skipped when dnsc_active == 0 
+ */
+
+void
+dns_check(void)
+{
+   struct dns_querys * dns_entry;
+   int   trysec;  /* seconds to wait for next try */
+
+   dnc_ageout();     /* age out expired entries */
+
+   for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+   {
+      if (dns_entry->id == 0) /* skip non-active request entrys */
+         continue;
+      
+      /* If we already have a reply we like, don't send */
+      if (dns_entry->rcode == DNSRC_OK)
+         continue;
+      
+      /* If it's a name error then punt the request if it is
+         over 10 seconds old */
+      if ((dns_entry->rcode == DNSRC_ENAME) &&
+          ((cticks - dns_entry->send_time) > DNC_TIMEOUT_TICKS))
+      {
+         goto timeout;
+      }
+
+      /* it is an active request; see if it's time to retry */
+      trysec = (dns_firsttry << dns_entry->tries);
+      if ((cticks - dns_entry->send_time) > (TPS * (unsigned long)trysec))
+      {
+         if (dns_entry->tries >= dns_trys)   /* retried out */
+         {
+timeout:
+            LOCK_NET_RESOURCE(NET_RESID);
+            dnc_del(dns_entry);
+            UNLOCK_NET_RESOURCE(NET_RESID);
+            dnsc_tmos++;      /* count timeouts */
+            /* After a timeout we return because the list is now altered.
+             * We'll process the rest of it on the next time tick.
+             */
+            return;
+         }
+         dnsc_retry++;           /* count total retries */
+         dns_entry->tries++;  /* count entry retries */		 
+		 
+         dnc_sendreq(dns_entry);
+      }
+   }
+}
+
+
+
+/* FUNCTION: badreply()
+ *
+ * dns_badreply() - per-port handler for less than ideal DNS replys. 
+ * 
+ * 
+ * PARAM1: struct dns_hdr * dns
+ * PARAM2: char * text
+ *
+ * RETURNS: Returns ENP code if problem should kill transaction, else 0 
+ */
+
+static int 
+badreply(struct dns_hdr *dns, char *text)
+{
+   dnsc_errors++;
+#ifdef NPDEBUG
+   dprintf("DNS error: %s; flags %x\n", text, htons(dns->flags));
+#endif   /* NPDEBUG */
+   /* don't kill request, let it retry with another server */
+
+   USE_ARG(dns);
+   USE_ARG(text);
+
+   return 0;
+}
+
+
+
+static
+char *
+getshort(char *cp, unshort *val)
+{
+   unsigned char *ucp = (unsigned char *)cp;
+
+   *val = (unshort)((*ucp << 8) | (*(ucp+1)));
+   return (cp+2);
+}
+
+
+
+static
+char *
+getlong(char *cp, u_long *val)
+{
+   unsigned char *ucp = (unsigned char *)cp;
+
+   *val = (u_long)((*(ucp)   << 24) |
+                   (*(ucp+1) << 16) |
+                   (*(ucp+2) <<  8) |
+                   (*(ucp+3)));
+   return (cp+4);
+}
+
+
+
+static char *
+getoffset(char * cp, char * dns, unshort * offsetp)
+{
+   unshort  offset;
+
+   /* bump past name field in answer, keeping offset to text */
+   if ((*cp & 0xC0) == 0xC0)  /* is it an offset? */
+   {
+      offset = (unshort)(*cp++); /* get first byte of offset code */
+      offset &= 0x3f;   /* mask our high two bits */
+      offset <<= 8;     /* make it high byte of word */
+      offset += (unshort)(*cp++);   /* add low byte of word */
+   }
+   else  /* text for name is right here */
+   {
+      offset = (unshort)(cp - dns);   /* save offset */
+      while (*cp++ != 0);  /* scan past name */
+   }
+   *offsetp = offset;
+   return cp;
+}
+
+
+
+static void
+dnc_set_answer(struct dns_querys * dns_entry, unshort type, char * cp, int rdlen)
+{
+   int   addrx;      /* index into address lists */
+   int i;
+
+   /* save reply IP addresses in array of IP addresses so long
+    * as there is room for them.
+    */
+   if (type == DNS_TYPE_PTR)
+   {
+      /* The first character usually is STX? */
+      MEMCPY(dns_entry->ptr_name, cp + 1, rdlen -1);
+      dns_entry->ptr_name[rdlen-1] = '\0';
+      /* replace STX and ETX charachters */
+      for (i = 0; i < (int)(strlen(dns_entry->ptr_name) - 1); i++)
+      {
+         if (dns_entry->ptr_name[i] <= 0x1F)
+         {
+            dns_entry->ptr_name[i] = '.';
+         }
+      }
+      return;
+   }
+#ifdef IP_V4
+   if (type == DNS_TYPE_IPADDR)
+   {
+      if (dns_entry->ipaddrs < MAXDNSADDRS)
+      {
+         addrx = dns_entry->ipaddrs++;      /* set index */
+         MEMCPY(&dns_entry->ipaddr_list[addrx], cp, 4);
+      }
+      return;
+   }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   if (type == DNS_TYPE_AAAA)     /* IPv6 address */
+   {
+      if (dns_entry->ip6addrs < MAXDNSADDRS)
+      {
+         addrx = dns_entry->ip6addrs++;      /* set index */
+         MEMCPY(&dns_entry->ip6_list[addrx], cp, 16);
+      }
+      return;
+   }
+#endif   /* IP_V6 */
+}
+
+
+
+/* FUNCTION: dnc_savename()
+ *
+ * Save a passed name in the passed dns_query structure. name is given
+ * via an offset into the dns packet.
+ *
+ * 
+ * PARAM1: dns_query structure to add name to
+ * PARAM2: pointer to dns header
+ * PARAM3: offset into dns header for name info
+ * PARAM3: TRUE if name is an alias
+ *
+ * RETURNS: void
+ */
+
+void
+dnc_savename(struct dns_querys *  dns_entry,
+             struct dns_hdr * dns, 
+             int offset,
+             int aliasflag)
+{
+   char * cp;     /* pointer to dns_names[] name buffer */
+
+   /* find next available space in name buffer */
+   cp = dns_entry->dns_names;
+   while (*cp)
+   {
+      if (*cp)
+         cp += (strlen(cp) + 1); /* end of name (if any) */
+
+      /* check for buffer overflow */
+      if (cp >= &dns_entry->dns_names[MAXDNSNAME])
+      {
+         dtrap();    /* ran out of buffer space for names */
+         return;
+      }
+      if (*cp == 0)
+         break;
+   }
+
+   /* copy dns-format name into buffer as text */
+   dnc_copyin(cp, offset + (char*)(dns), dns);
+
+   /* Set pointer(s) in dns structures to new name */
+   if (aliasflag)
+   {
+      int alias;     /* alias name index */
+      /* Set the next alias pointer. First we have to find out
+       * how many aliases are already in dns_entry.
+       */
+      for (alias = 0; alias < MAXDNSALIAS; alias++)
+      {
+         if (dns_entry->alist[alias] == NULL)
+            break;
+      }
+      if (alias >= MAXDNSALIAS)
+          return;
+      /* set alias pointer to alias name in dns_names[] buffer */
+      dns_entry->alist[alias] = cp;
+   }
+   else  /* set the name pointer(s) */
+   {
+      /* The hostent name field always points to dns_name */
+      dns_entry->he.h_name = cp;
+   }
+   return;
+}
+
+
+
+/* FUNCTION: dns_upcall()
+ *
+ * dns_upcall() - called from the UDP layer whenever we receive a DNS 
+ * packet (one addressed to port 53). p_nb_prot points to UDP data, 
+ * which should be DNS header. Return 0 if OK, or ENP code. 
+ *
+ * 
+ * PARAM1: PACKET pkt
+ * PARAM2: unshort lport
+ *
+ * RETURNS: 
+ */
+
+int
+dns_upcall(PACKET pkt, unshort lport)
+{
+   int      i;          /* record index */
+   char *   cp;         /* scratch pointer for building question field */
+   unshort  flags;      /* dns->flags in local endian */
+   unshort  rcode;      /* response code */
+   unshort  queries;    /* number of question records in reply */
+   unshort  answers;    /* number of answer records in reply */
+   unshort  records;    /* total records in reply */
+   unshort  type;       /* various fields from the reply */
+   unshort  netclass;   /* class of net (1 == inet) */
+   u_long   ttl;        /* records time to live */
+   unshort  rdlength;   /* length of record data */
+   unshort  offset;     /* scratch offset to domain name text */
+   unshort  nameoffset = 0;   /* offset to name in query */
+   unshort  authoffset = 0;   /* offset to first auth server name */
+   struct dns_hdr *  dns;     /* incoming dns header */
+   struct dns_querys *dns_entry = NULL;
+
+   dnsc_replies++;
+   dns = (struct dns_hdr *)pkt->nb_prot;
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dns_upcall() 1");
+#endif
+
+   for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+   {
+      if ((dns_entry->id == dns->id) &&
+          (dns_entry->lport == lport))
+      {
+         break;
+      }
+   }
+
+   /* make sure we found our entry in the table */
+   if (dns_entry == NULL)
+      return ENP_NOT_MINE;         /* do not free pkt here */
+
+   dns_entry->replies++;           /* count total replies */
+
+   /* If we already have a reply we liked then punt this one */
+   if (dns_entry->rcode == DNSRC_OK)
+   {
+      return 0;
+   }
+   
+   flags = htons(dns->flags);      /* extract data fromheader */
+   rcode = flags & DNSF_RCMASK;    /* Response code */
+   queries = htons(dns->qdcount);    /* number of questions */
+   answers = htons(dns->ancount);  /* number of answers */
+   records = queries + answers + htons(dns->nscount) + htons(dns->arcount);
+
+   /* check DNS flags for good response value */
+   if (!(flags & DNSF_QR))
+      return (badreply(dns, "not reply"));
+
+   /* looks like we got an answer to the query */
+   dns_entry->rcode = rcode;
+
+#ifdef DNS_CLIENT_UPDT
+  {
+     int opcode = (flags & DNSF_OPMASK) >> 11;   /* Op code */
+
+     /* If UPDATE opcode set the ip address field to non zero and return */
+     if (opcode == DNS_UPDT)
+     {
+        dns_entry->ipaddr_list[0] = 0xff;
+        return 0;
+     }
+  }
+#endif /* DNS_CLIENT_UPDT */
+
+   if (rcode != DNSRC_OK) 
+   {
+      unshort ecode = (rcode & (DNSF_AUTHOR | DNSF_RECUR | DNSF_NONAME));
+      
+      if (!ecode)
+         return (badreply(dns, "bad response code"));
+   }
+
+   if ((answers < 1) && !(rcode & DNSF_NONAME))
+      return (badreply(dns, "no answers"));
+   cp = (char*)(dns+1);    /* start after DNS entry */
+   /* Since we're going to store new DNS info, clean out the old info */
+   MEMSET(dns_entry->alist, 0, sizeof(dns_entry->alist));
+   dns_entry->ipaddrs = 0;
+#ifdef IP_V6
+   dns_entry->ip6addrs = 0;
+   MEMSET(dns_entry->ip6_list, 0, sizeof(dns_entry->ip6_list));
+   MEMSET(dns_entry->auths_ip6, 0, sizeof(dns_entry->auths_ip6));
+#endif   /* IP_V6 */
+   /* loop through remaining records - answers, auth, and RRs */
+   for (i = 0; i < records; i++)
+   {
+      /* Get offset to record's name */
+      cp = getoffset(cp, (char *)dns, &offset);
+      /* get records type and class from packet bytes */
+      cp = getshort(cp, &type);
+      cp = getshort(cp, &netclass);
+      if (netclass != 1)
+         return badreply(dns, "class not internet");
+      if (i < queries)  /* just skip of echos question record */
+         continue;
+      /* Get the Time and data-length */
+      cp = getlong(cp, &ttl);       /* 4 byte time to live field */
+      cp = getshort(cp, &rdlength); /* length of record data */
+      switch (type)
+      {
+      case DNS_TYPE_IPADDR:   /* IPv4 address for a name */
+      case DNS_TYPE_PTR:  /* alias */
+#ifdef IP_V6
+      case DNS_TYPE_AAAA:     /* IPv6 address */
+#endif   /* IP_V6 */
+         if ((type == DNS_TYPE_IPADDR) && (rdlength != 4))
+            return (badreply(dns, "IPADDR len not 4"));
+         dnsc_good++;
+         if (i < (queries + answers))   /* If record is an answer... */
+         {
+            if (nameoffset == 0)
+            {
+               /* save first answer name over request name */
+               nameoffset = offset;
+
+               /* save the name in the local DNS structure */
+               dnc_savename(dns_entry, dns, offset, 0);
+            }
+            dnc_set_answer(dns_entry, type, cp, rdlength);    /* save the answer */
+            dns_entry->expire_time = ttl * DNS_TTL_FACTOR; 
+            if (dns_entry->expire_time == 0)
+            {
+               dns_entry->expire_time = DEFAULT_TTL_TIME * DNS_TTL_FACTOR;
+            }
+         }
+         else  /* auth record or additional record */
+         {
+            if (offset == nameoffset)   /* another addr for query? */
+            {
+               dnc_set_answer(dns_entry, type, cp, rdlength);
+            }
+            else if (offset == authoffset) /* auth server IP address */
+            {
+               if (type == DNS_TYPE_IPADDR)
+                  MEMCPY(&dns_entry->auths_ip, cp, 4);
+#ifdef IP_V6
+               if (type == DNS_TYPE_AAAA)
+                  MEMCPY(&dns_entry->auths_ip6, cp, 16);
+#endif   /* IP_V6 */
+            }
+         }
+         break;
+      case DNS_TYPE_AUTHNS: /* authoritative name server */
+         /* What we really want for the name server is it's IP address,
+          * however this record only contains a name, ttl, etc. We save 
+          * the offset to the name, hoping that one of the additional 
+          * records will have the IP address matching this name.
+          */
+         if (authoffset == 0)  /* only save first one */
+            authoffset = cp - (char*)dns;
+         break;
+      case DNS_TYPE_ALIAS:  /* alias */
+         /* save name in dns rec as an alias */
+         dnc_savename(dns_entry, dns, offset, 1);
+         break;
+      default:       /* unhandled record type, ignore it. */
+         break;
+      }
+      cp += rdlength;   /* bump past trailing data to next record */
+   }
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dns_upcall() 2");
+#endif
+   return 0;
+}
+
+
+
+/* FUNCTION: dnc_lookup()
+ *
+ * dnc_lookup() - check cache for a pending or completed DNS client 
+ * request. Passed entry index is filled in if DNS query was resolved 
+ * without error, else this returns non-zero ENP_ error code. 
+ *
+ * 
+ * PARAM1: char * name
+ * PARAM2: int * cacheindex
+ *
+ * RETURNS: ENP_SEND_PENDING if request is still on the net, or ENP_TIMEOUT
+ * id request timed out (or was never made), or 0 (SUCCESS) if passed 
+ * name found in cache, or ENP_PARAM if 
+ */
+
+static  int
+dnc_lookup(char * name, struct dns_querys ** cacheentry)
+{
+   struct dns_querys * dns_entry;
+   int      alias;
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dnc_lookup()");
+#endif
+   /* look through the cache for the passed name */
+   for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+   {
+      if (strcmp(dns_entry->dns_names, name) == 0)
+         break;
+
+      if ((dns_entry->he.h_name) &&
+          (strcmp(dns_entry->he.h_name, name) == 0))
+      {
+         break;
+      }
+
+      for (alias = 0; alias < MAXDNSALIAS; alias++)
+      {
+         if ((dns_entry->alist[alias]) &&
+            (strcmp(dns_entry->alist[alias], name) == 0))
+               goto found_name;
+      }
+   }
+
+found_name:
+
+   /* if not found, return error */
+   if (dns_entry == NULL)
+      return ENP_PARAM;
+
+   /* else, prepare to return entry index */
+   if (cacheentry != NULL)
+      *cacheentry = dns_entry;
+
+   /* if completed request, return success */
+   if (dns_entry->rcode != DNSRC_UNSET)
+      return 0;
+
+   /* incomplete request -- return pending or timed-out status */
+   if (dns_entry->tries < dns_trys) /* still trying? */
+      return ENP_SEND_PENDING;
+   else
+      return ENP_TIMEOUT;
+}
+
+
+
+/* FUNCTION: dns_lookup()
+ *
+ * dns_lookup() - check state of a DNS client request previously 
+ * launched with dns_query(). Passed IP address is filled in (in net 
+ * endian) if DNS query was resolved without error, else this clears 
+ * passed Ip address and returns non-zero ENP_ code. 
+ *
+ * 
+ * PARAM1: ip_addr * ip
+ * PARAM2: char * name
+ *
+ * RETURNS: ENP_SEND_PENDING if request is still on the net, or ENP_TIMEOUT
+ * if request timed out (or was never made), or 0 (SUCCESS) if passed IP 
+ * is filled in and everything is peachy, or other ENP errors if 
+ * detected. 
+ */
+
+int   
+dns_lookup(ip_addr * ip, char * name)
+{
+   struct dns_querys * dns_entry;
+   int      err;
+
+   *ip = 0L;
+   err = dnc_lookup(name, &dns_entry);
+   if (err)
+      return err;
+   *ip = dns_entry->ipaddr_list[0];    /* return IP address */
+   return 0;
+}
+
+
+
+/* static hostent structure for gethostbyname to return when it's
+ * been passed a "name" which is just a dot notation IP address. */
+static struct hostent dnc_hostent;
+static ip_addr dnc_addr;         /* actual output in hostent */
+static char *dnc_addrptrs[2];    /* pointer array for hostent */
+#define DNC_NAME_SIZE      31
+static char dnc_name[DNC_NAME_SIZE+1];        /* IP address string */
+
+
+/* FUNCTION: dns_query_do()
+ *
+ * Perform a DNS query
+ *
+ * PARAM1: char *             host name being queried
+ * PARAM2: char               query type
+ * PARAM3: dns_querys **      address of ptr to query result
+ *
+ * RETURNS: dns_querys *      ptr to query result or NULL
+ *
+ * Issue a DNS query and wait for completion or timeout. If successful,
+ * store the query results in 'p_entry'. Return the result of the query
+ * or NULL if the query failed.
+ */
+
+struct dns_querys *
+dns_query_do(char *name, char type, struct dns_querys **p_entry)
+{
+   int err = 0;
+   int loop_cnt = 0;
+
+   /* we will call dnc_lookup() until it either succeeds, fails
+    * or we time out trying */
+   err = dns_query_type(name, type, (ip_addr)0, (unsigned long)0, p_entry);
+   do
+   {
+      err = dnc_lookup(name, p_entry);
+      if (err != ENP_SEND_PENDING)
+         break;
+#ifndef SUPERLOOP
+      TK_SLEEP(DNS_QUERY_WAIT * TPS);
+#else
+      {
+         u_long uTicks = cticks;
+
+         /* don't TK_SLEEP - hang around */
+         while ((cticks - uTicks) < DNS_QUERY_WAIT * TPS)
+            tk_yield();				
+      }
+#endif
+      loop_cnt++;
+   } while (loop_cnt < DNS_QUERY_RETRY);  
+
+   if (err)
+   {
+      printf("dns_query_do(): err = %d, loop_cnt = %d\n", err, loop_cnt);
+   }
+
+   return (*p_entry);
+}
+
+
+
+/* FUNCTION: gethostbyname()
+ *
+ * Get host information for named host
+ *
+ * PARAM1: char *             host name
+ *
+ * RETURNS: hostent *         ptr to host entry structure or NULL
+ *
+ * Implements a "standard" Unix version of gethostbyname().
+ * Returns a pointer to a hostent structure if successful, NULL
+ * if not successful. The returned structure should NOT be 
+ * freed by the caller.
+ */
+
+struct hostent *
+gethostbyname(char *name)
+{
+   int      i;
+   char *cp;
+   unsigned int snbits;
+   struct dns_querys *dns_entry = NULL;
+   struct hostent *ho;
+   
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("gethostbyname()");
+#endif
+
+   /* if the name is a dot notation IP address, just return the address */
+   cp = parse_ipad(&dnc_addr, &snbits, name);
+   if (!cp)    
+   {
+      /* fill in the static hostent structure and return it */
+      strncpy(dnc_name, name, (size_t)DNC_NAME_SIZE);
+      dnc_name[DNC_NAME_SIZE] = '\0';
+      dnc_hostent.h_name = &dnc_name[0];
+      dnc_hostent.h_aliases = NULL;  /* we don't do the aliases */
+      dnc_hostent.h_addrtype = AF_INET; /* AF_INET */
+      dnc_hostent.h_length = 4;   /* length of IP address */
+      dnc_hostent.h_addr_list = &dnc_addrptrs[0];
+      dnc_addrptrs[0] = (char*)&dnc_addr;
+      dnc_addrptrs[1] = NULL;
+
+      return (&dnc_hostent);
+   }
+
+   /* get the name to IP address mapping information */
+   dns_entry = dns_query_do(name, DNS_TYPE_IPADDR, &dns_entry);
+   if (dns_entry == NULL)
+   {
+      printf("gethostbyname(): NULL entry\n");
+      return (NULL);
+   }
+   if (dns_entry->ipaddrs == 0)  /* no IPv4 address? */
+   {
+      printf("gethostbyname(): no IPv4 addresses\n");
+      return (NULL);
+   }
+   /* Set up the hostent fields for IPv4. */
+   ho = &dns_entry->he;
+   ho->h_addrtype = AF_INET;
+   ho->h_length = 4;   /* length of IP address */
+   ho->h_addr_list = &dns_entry->addrptrs[0];
+
+   /* fill in the address pointer list in hostent structure */
+   for (i = 0; i < dns_entry->ipaddrs; i++)
+   {
+      dns_entry->addrptrs[i] = (char *)&dns_entry->ipaddr_list[i];
+#ifdef NPDEBUG
+      dprintf("+++ gethostbyname addr = %lx\n", *((ulong *)dns_entry->addrptrs[i]));
+#endif
+   }
+   dns_entry->addrptrs[i] = (char *)NULL;    /* last one gets a NULL */
+   
+   return (ho);
+}
+ 
+
+
+int prep_reverse_name(char *name, char *append_str, char *mod_str)
+{
+   int name_len, append_len;
+
+   if ((name == NULL) || (append_str == NULL) || (mod_str == NULL))
+   {
+      return (-1);
+   }
+   name_len = strlen(name);
+   append_len = strlen(append_str);
+   if ((name_len == 0) || (append_len == 0))
+   {
+      return (-1);
+   }
+
+   reverse_domain_addr(mod_str, name);
+#if 0
+   sprintf(mod_str, "%s.%s", mod_str, append_str);
+#else
+   strcat(mod_str, ".");
+   strcat(mod_str, append_str);
+#endif
+
+   return (0);
+}
+
+
+
+int 
+nslookup(char * name, char type, struct dns_querys **dns_entry)
+{
+   char modified_name[255];
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("nslookup()");
+#endif
+
+   switch (type)
+   {
+   case DNS_TYPE_PTR:
+      if (prep_reverse_name(name, "in-addr.arpa", modified_name) == 0)
+      {
+         *dns_entry = dns_query_do(modified_name, type, dns_entry);
+         if (*dns_entry == NULL)
+         {
+#ifdef DEBUG_DNSCLNT_C
+            printf("nslookup(): NULL DNS entry\n");
+#endif
+            return (-1);
+         }
+      }
+      break;
+   default:
+#ifdef DEBUG_DNSCLNT_C
+      printf("nslookup(): type %d not supported\n", type);
+#endif
+      return (-1);
+      break;
+   }
+
+   return (0);
+}
+
+
+
+#ifdef IP_V6
+
+struct hostent *
+gethostbyname2(char * name, int af)
+{
+   int i;
+   struct hostent *ho;
+   struct dns_querys *dns_entry = NULL;
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("gethostbyname2()");
+#endif
+
+   if (af == AF_INET)
+   {
+      ho = gethostbyname(name);
+      return (ho);
+   }
+   else if (af == AF_INET6)
+   {
+      dns_entry = dns_query_do(name, DNS_TYPE_AAAA, &dns_entry);
+      if (dns_entry == NULL)
+      {
+         printf("gethostbyname2(): NULL entry\n");
+         for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+         {
+            if (strcmp(dns_entry->dns_names, name))
+            {
+               printf("gethostbyname2(): %s is dns_ds\n", name);
+            }
+         }
+         return (NULL);
+      }
+   }
+   else
+   {
+      return (NULL);
+   }
+
+   if (dns_entry->ip6addrs == 0)     /* no IPv6 address? */
+      return (NULL);
+
+   /* Rework the hostent fields for IPv6 */
+   ho = &dns_entry->he;
+   ho->h_addrtype = AF_INET6;
+   ho->h_length = 16;   /* length of IP address */
+   /* fill in the address pointer list in hostent structure */
+   for (i = 0; i < dns_entry->ip6addrs; i++)
+      dns_entry->addrptrs[i] = &dns_entry->ip6_list[i][0];
+   dns_entry->addrptrs[i] = NULL;     /* last one gets a NULL */
+   ho->h_addr_list = &dns_entry->addrptrs[0];
+
+   return (ho);
+}
+
+#endif /* IP_V6 */
+
+
+
+#ifdef DNS_CLIENT_UPDT
+
+/* FUNCTION: dns_update()
+ *
+ * dns_update- sends a DNS UPDATE packet to the authoritative server
+ * of the specified domain name. Send DNS_TYPE_AUTHNS to get hostent. It then sends
+ * the DNS_UPDT packet to the authoritative server.
+ *
+ * 
+ * PARAM1: char * soa_mname     domain name
+ * PARAM2: char * hname         host name
+ * PARAM3: ip_addr ipaddress   ip address
+ * PARAM4: unsigned long ttl   ttl value
+ * PARAM5: IO handle for output (NULL is OK)
+ *
+ * RETURNS: 0 if successful
+ *          negative ENP error if internal error occurs (eg timeout)
+ *          else one of the DNSRC_ errors (all positive).
+ */
+
+int
+dns_update(char * soa_mname, char * hname, ip_addr ipaddr,
+            unsigned long ttl, void *pio)
+{
+   int      err;
+   u_long   tmo;
+   struct dns_querys *dns_entry;
+   unsigned char *ucp;
+   ip_addr save_dns_srvr;
+   char *domP;  
+   
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dns_update()");
+#endif
+
+   /*
+    * get domain name from host name.
+    */
+   if ((domP = strstr(hname, ".")) == NULL)
+   {
+         dprintf("bad domain name.\n");
+         return -1;
+   }
+
+   /* get authoritative name server for specified domain. We will
+    * call dns_query_type() until it either succeeds, fails or
+    * we time out trying.
+    */
+   tmo = cticks + (10 * TPS);
+   err = dns_query_type(domP + 1, DNS_TYPE_AUTHNS, (ip_addr)0,
+            (unsigned long)0, &dns_entry);
+
+   do
+   {
+      if ((err = dnc_lookup(domP + 1, &dns_entry)) == 0)
+         break;
+      tk_yield();
+   } while  (cticks < tmo);
+   if (err)
+   {      
+       /* kill the entry */
+      dnc_del(dns_entry);
+      return err;
+   }
+
+   /* Get here if we received a hostent structure. Send the update packet
+    * to the received IP address (first in list) by swapping the address
+    * into the list of DNS servers.
+    */
+
+   if (dns_entry->he.h_addr_list)
+   {
+      ucp = (unsigned char *) *(dns_entry->he.h_addr_list);
+      MEMCPY(&save_dns_srvr, dns_servers, 4);   /* save 1st DNS server */
+      MEMCPY(dns_servers, ucp, 4);              /* swap in AUTHS address */
+
+      ns_printf(pio," sending update packet to %u.%u.%u.%u\n",
+         *ucp, *(ucp + 1), *(ucp + 2), *(ucp + 3));
+   }
+
+   /* 
+    * kill the entry, 
+    */
+   dnc_del(dns_entry);
+
+   /*
+    * if this is a delete, we first kill any
+    * exiting entry.
+    */
+   if (ttl == 0L)
+   {
+      int found = 0;
+      int alias;
+
+      /* yup - search for it */
+      /* look through the cache for the passed name */
+      for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+      {
+         if (strcmp(dns_entry->dns_names, hname) == 0)
+         {
+            found = 1;
+            break;
+         }
+   
+         if ((dns_entry->he.h_name) &&
+              (strcmp(dns_entry->he.h_name, hname) == 0))
+         {
+             found = 1;
+             break;
+         }
+
+         for (alias = 0; alias < MAXDNSALIAS; alias++)
+         {
+            if ((dns_entry->alist[alias]) &&
+                (strcmp(dns_entry->alist[alias], hname) == 0))
+            {
+               found = 1;
+               break;
+            }
+         }
+      }
+   
+      if (found)
+      {
+         /* kill the entry */
+         dnc_del(dns_entry);
+      }
+   }
+
+   tmo = cticks + (10 * TPS);
+   err = dns_query_type(hname, DNS_UPDT, ipaddr, ttl, &dns_entry);
+ 
+   while (cticks < tmo)
+   {
+      if ((err = dnc_lookup(hname, &dns_entry)) == 0)
+         break;
+      tk_yield();   
+   }
+
+   MEMCPY(&dns_servers[0], &save_dns_srvr, 4);
+
+   if (dns_entry->rcode == DNSRC_NOTAUTH)
+   {
+      ns_printf(pio," DNS server replies with - not authoritative.\n");
+      dns_entry->rcode = DNSRC_UNSET;
+      dns_entry->id = 0;
+      dns_entry->dns_names[0] = 0;
+      dns_entry->he.h_name = 0;
+      return 0;
+   }
+   dns_entry->ipaddrs = ipaddr;
+
+   if (!err)
+      err = dns_entry->rcode;
+
+   /* if delete then kill entry */
+   if (ttl == 0L)
+   {
+      /* kill the entry */
+      dnc_del(dns_entry);
+   }
+   return err;
+}
+
+#endif  /* DNS_CLIENT_UPDT */
+
+
+
+#ifdef NET_STATS
+
+/* FUNCTION: dns_state()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+dns_state(void * pio)
+{
+   struct dns_querys * dns_entry;
+   int   i;
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dns_state()");
+#endif   
+
+   ns_printf(pio,"DNS servers:");
+   for (i = 0; i < MAXDNSSERVERS; i++)
+      ns_printf(pio,"%u.%u.%u.%u ", PUSH_IPADDR(dns_servers[i]));
+
+   ns_printf(pio,"\nDNS cache:\n");
+   for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+   {
+#ifdef IP_V6
+      if (dns_entry->he.h_addrtype == AF_INET6)
+      {
+         ns_printf(pio, "name: %s\n", dns_entry->he.h_name);
+         if (!(dns_entry->he.h_addr_list))
+            ns_printf(pio,"\tno addresses\n");
+         else
+         {
+            char ** cpp;
+            for (cpp = dns_entry->he.h_addr_list; *cpp; cpp++)
+            {
+               char ip6buf[40];     /* tmp buffer for ipv6 address text */
+               ns_printf(pio,"\t%s\n",  print_ip6((struct in6_addr *)(*cpp), ip6buf));
+            }
+         }
+         ns_printf(pio,"retry:%d, ID:%d, rcode:%d, err:%d\n",
+          dns_entry->tries, dns_entry->id, dns_entry->rcode, dns_entry->err);
+      }
+      else 
+#endif
+      if (dns_entry->he.h_addrtype == AF_INET)
+      {
+         ns_printf(pio,"name: %s\n", dns_entry->he.h_name);
+         if (!(dns_entry->he.h_addr_list))
+            ns_printf(pio,"\tno addresses\n");
+         else
+         {
+            char ** cpp;
+            u_char * ucp;
+            for (cpp = dns_entry->he.h_addr_list; *cpp; cpp++)
+            {
+               ucp = (unsigned char *) (*cpp);
+               ns_printf(pio,"\t%d.%d.%d.%d\n", *ucp, *(ucp + 1), *(ucp + 2), *(ucp + 3));
+            }
+         }
+         ns_printf(pio,"retry:%d, ID:%d, rcode:%d, err:%d\n",
+          dns_entry->tries, dns_entry->id, dns_entry->rcode, dns_entry->err);
+      }
+   }
+   ns_printf(pio,"protocol/implementation runtime errors:%lu\n", dnsc_errors);
+   ns_printf(pio,"requests sent:%lu\n", dnsc_requests);
+#ifdef DNS_CLIENT_UPDT
+   ns_printf(pio, "Updates sent:%lu\n", dnsc_updates);
+#endif /* DNS_CLIENT_UPDT */
+   ns_printf(pio,"replies received:%lu\n", dnsc_replies);
+   ns_printf(pio,"usable replies:%lu\n", dnsc_good);
+   ns_printf(pio,"total retries:%lu\n", dnsc_retry);
+   ns_printf(pio,"timeouts:%lu\n", dnsc_tmos);
+
+   return 0;
+}
+
+
+
+int
+dnc_database(void * pio)
+{
+   struct dns_querys *dns_entry;
+   struct hostent *p;
+   char **cpp;
+   int i;
+
+   if (dns_qs == NULL)
+   {
+      ns_printf(pio, "No DNS entries.\n");
+      return 0;
+   }
+
+#ifdef DEBUG_DNSCLNT_C
+   dump_dns_qs("dnc_database()");
+#endif
+
+   /* look through the cache for the passed name */
+   for (dns_entry = dns_qs; dns_entry; dns_entry = dns_entry->next)
+   {
+      if (dns_entry->rcode != DNSRC_OK)
+      {
+         ns_printf(pio, "Query for %s: ", dns_entry->dns_names);
+         if (dns_entry->rcode == DNSRC_UNSET)
+            ns_printf(pio, "no reply\n");
+         else
+            ns_printf(pio, "bad reply code was %d.\n", dns_entry->rcode);
+         continue;
+      }
+      if (dns_entry->he.h_name)
+      {
+         ns_printf(pio, "name: %s, ", dns_entry->he.h_name);
+      }
+      p = &dns_entry->he;
+      if (*p->h_aliases)
+      {
+         ns_printf(pio, "\n  Aliases: ");
+         for (cpp = p->h_aliases; *cpp; cpp++)
+         {
+            ns_printf(pio, "%s, ", *cpp);
+         }
+      }
+#ifdef IP_V4
+      if (dns_entry->ipaddrs)
+      {
+         if (p->h_addrtype == AF_INET)
+         {
+            ns_printf(pio, "\n  IPv4 addrs: ");
+            for (i = 0; i < dns_entry->ipaddrs; i++)
+            {
+               ns_printf(pio, "%u.%u.%u.%u, ", 
+                         PUSH_IPADDR(dns_entry->ipaddr_list[i]));
+            }
+         }
+      }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      if (dns_entry->ip6addrs)
+      {
+         if (p->h_addrtype == AF_INET6)
+         {
+            ns_printf(pio, "\n  IPv6 addrs: ");
+            for (i = 0; i < dns_entry->ip6addrs; i++)
+            {
+               char ip6buf[40];     /* tmp buffer for ipv6 address text */
+               ns_printf(pio, "%s ", 
+                  print_ip6((struct in6_addr *)(&dns_entry->ip6_list[i][0]), ip6buf));
+            }
+         }
+      }
+#endif   /* IP_V6 */
+      ns_printf(pio, "\n  Age (in seconds): %lu, Expires in %lu seconds (ttl)", 
+         (cticks - dns_entry->send_time)/TPS, dns_entry->expire_time);
+
+      ns_printf(pio, "\n");
+   }
+
+   return (0);
+}
+
+#endif   /* NET_STATS */
+
+
+#ifdef DNS_CLIENT_TEST_UPDT
+
+#define MAX_DDNS_STR_LEN 256
+
+typedef struct ResRec RR;
+
+struct ddnsReq
+{
+	char *zone;
+	RR   *preqs;
+	RR   *ups;
+};
+
+typedef struct ddnsReq DDNSREQS;
+
+static DDNSREQS DDNSReqs;
+static int nsddnsLineNo;
+
+static char *DDNSTestFile = "..\\dnssrv\\ddnstest.txt";
+/* static char DDNSzone[MAX_DDNS_STR_LEN] = {0}; */
+
+static char *  nsddnsZone(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsPreqs(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsUps(void * pio, FILE *fp, char *inWrk);
+static int nsddnsMsgs(void * pio, FILE *fp, char *inWrk);
+extern int dns_sendDDNSReq(char *zone, int lenPreqs, int numPreqs,
+                           char *preqsP, int lenUps, int numUps, char *upsP);
+
+
+/* FUNCTION: nsddnstest()
+ * 
+ * Read command file and send test DDNS reqs.
+ *
+ * Uses recursive descent to parse file.
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int 
+nsddnstest(void * pio)
+{
+   FILE * fp;
+   char *wrk;
+   char inBuf[MAX_DDNS_STR_LEN];
+   int err = 0;
+   RR   *rrP;
+   RR   *rrP2;
+   char *preqsP;
+   char *upsP;
+   int preqsLen;
+   int preqsCount;
+   int upsLen;
+   int upsCount;
+   unsigned long delTicks;
+
+   nsddnsLineNo = 0;
+   MEMSET(&DDNSReqs, 0, sizeof(DDNSReqs));
+
+   fp = fopen(DDNSTestFile, "r");
+
+   if (!fp)
+   {
+      ns_printf(pio, "nsddnstest: can't open input file %s\n", DDNSTestFile);
+      fclose(fp);
+      return -1;
+   }
+
+   while ((wrk = fgets(inBuf, sizeof(inBuf), fp)))
+   {
+      nsddnsLineNo++;
+      if ((inBuf[0] == ';') || (inBuf[0] == '\n') || (inBuf[0] == '\t') || (inBuf[0] == ' '))
+         continue;
+
+      if ((wrk = strstr(wrk, "msg")))
+      {
+         err = nsddnsMsgs(pio, fp, wrk);
+         if (err)
+         {
+            dprintf("*** nsddnstest, bad msg\n");
+            break;
+         }
+      }
+
+      if (!DDNSReqs.zone)
+      {
+         ns_printf(pio, "nsddnstest: no ZONE\n");
+         goto FREEIT;
+      }
+
+      if (!DDNSReqs.ups)
+      {
+         ns_printf(pio, "nsddnstest: no UPDATEs\n");
+         goto FREEIT;
+      }
+
+      /* create DDNS msg and send it */
+
+      /* got preqs? */
+      if (DDNSReqs.preqs)
+      {
+         char *preqsWrkP;
+
+         /* yup get length and count */
+         preqsCount = preqsLen = 0;
+         rrP = DDNSReqs.preqs;
+         while (rrP)
+         {
+            preqsCount++;
+            preqsLen += rrP->RDlength;
+            rrP = rrP->next;
+         }
+
+         preqsWrkP = preqsP = (char *)npalloc(preqsLen);
+
+         rrP = DDNSReqs.preqs;
+         while (rrP)
+         {
+            MEMCPY(preqsWrkP, rrP->RdataP, rrP->RDlength);
+            preqsWrkP += rrP->RDlength;
+            rrP = rrP->next;
+         }
+      }
+
+      /* package updates */
+      upsCount = upsLen = 0;
+      rrP = DDNSReqs.ups;
+      while (rrP)
+      {
+         upsCount++;
+         upsLen += rrP->RDlength;
+         rrP = rrP->next;
+      }
+
+      wrk = upsP = (char *)npalloc(upsLen);
+
+      rrP = DDNSReqs.ups;
+      while (rrP)
+      {
+         MEMCPY(wrk, rrP->RdataP, rrP->RDlength);
+         wrk += rrP->RDlength;
+         rrP = rrP->next;
+      }
+
+      /* send the pkt to server */
+      dns_sendDDNSReq(DDNSReqs.zone, preqsLen, preqsCount,
+                      preqsP, upsLen, upsCount, upsP);
+
+FREEIT:
+
+      if (DDNSReqs.zone)
+         npfree(DDNSReqs.zone);
+
+      rrP = DDNSReqs.preqs;
+      while (rrP)
+      {
+         rrP2 = rrP->next;
+         if (rrP->RdataP)
+            npfree(rrP->RdataP);	   
+         npfree(rrP);
+         rrP = rrP2;
+      }
+
+      rrP = DDNSReqs.ups;
+      while (rrP)
+      {
+         rrP2 = rrP->next;
+         if (rrP->RdataP)
+            npfree(rrP->RdataP);	   
+         npfree(rrP);
+         rrP = rrP2;
+      }
+
+      DDNSReqs.zone = NULL;
+      DDNSReqs.preqs = NULL;
+      DDNSReqs.ups = NULL;
+
+
+      /* give time for processing between UDP pkts */
+      delTicks = cticks;
+      while ((cticks - delTicks) < (TPS * 3))
+         tk_yield();
+   }  /* while */
+
+   fclose(fp);
+   return err;
+}
+
+
+
+/* FUNCTION: nsddnsMsgs()
+ * 
+ * Process a "msg" command
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static int  
+nsddnsMsgs(void * pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   int fbrace = 0;
+
+   nsddnsLineNo--;
+   inBuf[0] = 0;
+
+   /* got "msg" find "{" ... "}"*/
+   do
+   {
+      nsddnsLineNo++;
+      if (inBuf[0] == ';')
+         continue;
+
+      if (!fbrace)
+      {
+         if ((wrk = strstr(wrk, "{")) == NULL)
+            continue;
+         else
+            wrk++;
+      }
+
+      fbrace = 1;	
+
+RELOOP:		
+      if ((*wrk == '\n') || (*wrk == ';'))
+         continue;
+
+      wrk2 = wrk;
+		/* got "zone"? */
+      if ((wrk = strstr(wrk2, "zone")))
+      {
+         /* yup - process "zone" */
+         if (!(wrk = nsddnsZone(pio, fp, wrk)))
+            return -1;
+         else
+         {
+            wrk = strcpy(inBuf, wrk);
+            goto RELOOP; /* GOTO! */
+         }
+      }
+      else
+      {
+         /* got "preqs"? */
+         if ((wrk = strstr(wrk2, "preqs")))
+         {
+            /* yup - process "preqs" */
+            if (!(wrk = nsddnsPreqs(pio, fp, wrk)))
+               return -1;
+            else
+            {
+               wrk = strcpy(inBuf, wrk);
+               goto RELOOP; /* GOTO! */
+            }
+         }
+         else
+            /* got "ups"? */
+            if ((wrk = strstr(wrk2, "ups")))
+            {
+               /* yup - process "ups" */
+               if (!(wrk = nsddnsUps(pio, fp, wrk)))
+                  return -1;
+               else
+               {
+                  wrk = strcpy(inBuf, wrk);
+                  goto RELOOP; /* GOTO! */
+               }
+            }
+      }
+
+      /* got "}"? */
+      if ((wrk = strstr(wrk2, "}")))
+      return 0;
+   }
+   while ((wrk = fgets(inBuf, sizeof(inBuf), fp)));
+
+   /* was EOF? */
+   if (!wrk)
+   {
+      ns_printf(pio, "msg has no body, line [%d]\n", nsddnsLineNo);
+   }
+
+   return -1;
+}
+
+
+
+static char * nsddnsRrexistsvi(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsRrexistsvd(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsRrnexist(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsRrninus(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsRrnNinus(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsRr(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsdRrs(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsdaRr(void * pio, FILE *fp, char *inWrk);
+static char * nsddnsdRr(void * pio, FILE *fp, char *inWrk);
+
+
+/* FUNCTION: nsddnsPreqs
+ * 
+ * Process a "preqs" command
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char *  
+nsddnsPreqs(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   int fbrace = 0;
+
+   nsddnsLineNo--;
+   inBuf[0] = 0;
+
+   do
+   {
+      nsddnsLineNo++;
+      if (inBuf[0] == ';')
+         continue;
+
+      if (!fbrace)
+      {
+         if ((wrk = strstr(wrk, "{")) == NULL)
+            continue;
+         else
+            wrk++;
+      }
+
+      fbrace = 1;
+
+      /* found "{" - get prerequisites */
+
+RELOOP:		
+      if ((*wrk == '\n') || (*wrk == ';'))
+         continue;
+
+      wrk2 = wrk;
+      wrk = strtok(wrk, "{ \t\n}");
+
+      if (wrk)
+      {
+         wrk2 = wrk + strlen(wrk) + 1;
+
+         /* RRset exists (value independent) */
+         if (strcmp(wrk, "rrexistsvi") == 0)
+         {
+            if (!(wrk = nsddnsRrexistsvi(pio, fp, wrk2)))
+               return -1;
+            else
+            {
+               wrk = strcpy(inBuf, wrk);
+               goto RELOOP; /* GOTO! */
+            }
+         }
+         else
+         /* RRset exists (value dependent) */
+            if (strcmp(wrk, "rrexistsvd") == 0)
+            {
+               if (!(wrk = nsddnsRrexistsvd(pio, fp, wrk2)))
+                  return -1;
+               else
+               {
+                  wrk = strcpy(inBuf, wrk);
+                  goto RELOOP; /* GOTO! */
+               }
+            }
+            else
+               /* RRset does not exist */
+               if (strcmp(wrk, "rrnexist") == 0)
+               {
+                  if (!(wrk = nsddnsRrnexist(pio, fp, wrk2)))
+                     return -1;
+                  else
+                  {
+                     wrk = strcpy(inBuf, wrk);
+                     goto RELOOP; /* GOTO! */
+                  }
+               }
+               else
+                  /* name in use */
+                  if (strcmp(wrk, "rrninus") == 0)
+                  {
+                     if (!(wrk = nsddnsRrninus(pio, fp, wrk2)))
+                        return -1;
+                     else
+                     {
+                        wrk = strcpy(inBuf, wrk);
+                        goto RELOOP; /* GOTO! */
+                     }
+                  }
+                  else
+                     /* name not in use */
+                     if (strcmp(wrk, "rrnninus") == 0)
+                     {
+                        if (!(wrk = nsddnsRrnNinus(pio, fp, wrk2)))
+                           return -1;
+                        else
+                        {
+                           wrk = strcpy(inBuf, wrk);
+                           goto RELOOP; /* GOTO! */
+                        }
+                     }
+                     else
+                     {
+                        ns_printf(pio, "preqs bad command, line [%d]\n", nsddnsLineNo);
+                        return NULL;
+                     }
+      }
+      else
+         wrk = wrk2;
+
+      /* got "}"? */
+      if ((wrk = strstr(wrk, "}")))
+      {
+         nsddnsLineNo++;
+         return fgets(inBuf, sizeof(inBuf), fp);
+      }
+   }
+   while ((wrk = fgets(inBuf, sizeof(inBuf), fp)));
+
+   /* was EOF? */
+   if (!wrk2)
+   {
+      ns_printf(pio, "preqs has no body, line [%d]\n", nsddnsLineNo);
+   }
+
+   return NULL;
+}
+
+
+
+#define TYPE_RDLENGTH_SIZE (2 + 2 + 4 + 2) /* TYPE, CLASS, TTL, and RDLENGTH */
+
+/* FUNCTION: nsddnsRrexistsvi()
+ *
+ * Process a "rrexistsvi" command
+ *
+ *  CLASS    TYPE     RDATA    Meaning
+ *  ------------------------------------------------------------
+ *   ANY      rrset    empty    RRset exists (value independent)
+ *
+ * RRset exists (value independent).  At least one RR with a
+ *        specified NAME and TYPE (in the zone and class specified by
+ *        the Zone Section) must exist.
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+extern int dnc_copyout(char * dest, char * src);
+
+static char *  
+nsddnsRrexistsvi(void * pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   int len;
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rrexistsvi expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* got "rrexistsvi" find "{" ... "}"*/
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+
+   RRp->type = atoi(wrk2);
+   RRp->dclass = C_ANY;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+   wrk += len;
+
+   PUTSHORT(RRp->type, wrk);
+
+   PUTSHORT(RRp->dclass, wrk);
+
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+	
+
+   RRp->next = DDNSReqs.preqs;
+   DDNSReqs.preqs = RRp;
+   wrk = wrk2 + strlen(wrk2) + 1;
+	   
+   /* got "}"? */
+   if ((wrk = strstr(wrk, "}")))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rrexistsvi expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsRrexistsvd()
+ *
+ *
+ *  CLASS    TYPE     RDATA    Meaning
+ *  ------------------------------------------------------------
+ *   zone     rrset    rr       RRset exists (value dependent)
+ *
+ * RRset exists (value dependent).  A set of RRs with a
+ *        specified NAME and TYPE exists and has the same members
+ *        with the same RDATAs as the RRset specified here in this
+ *        Section.
+ *
+ * Process a "rrexistsvdd" command
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+static char *  
+nsddnsRrexistsvd(void * pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+   short len2;
+   unsigned long addr;
+   unsigned sbitz = 0;
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rrexistsvi expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* found "{" - get exists (value dependent) */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+
+   RRp->type = atoi(wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+   RRp->dclass = C_IN;
+  
+   /* SOA */
+   if (RRp->type == T_SOA)
+   {
+
+      /*
+       * 3.3.13. SOA RDATA format
+       *
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     MNAME                     /
+       *    /                                               /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     RNAME                     /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    SERIAL                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    REFRESH                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                     RETRY                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    EXPIRE                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    MINIMUM                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       */
+
+      char zmail[MAX_DDNS_STR_LEN];
+      int mlen;
+      int SOAlen;
+      int domLen;
+      unsigned long serial;
+      u_long zserial;
+      u_long zrefresh;
+      u_long zretry;
+      u_long zexpire;
+      u_long zminimum;
+
+      zserial = atol(wrk2);  /* serial */
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zrefresh = atol(wrk2);  
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zretry = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zexpire = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zminimum = atol(wrk2); 
+
+      mlen = dnc_copyout(zmail, "z.z"); 
+
+      /* alloc memory for full RR */
+      RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + 
+		   (SOAlen = len + /* comp len of SOA */
+		   mlen + /* comp len of mail addr */
+		   5 * 4 /* 5 longs */));
+
+      MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + SOAlen);
+      MEMCPY(wrk, RRp->name, len);
+
+      RRp->RDlength = len + TYPE_RDLENGTH_SIZE + SOAlen;
+
+      wrk += len;
+      domLen = len;
+
+      /* PUTSHORT() is equivalent to an htons() */
+      PUTSHORT(RRp->type, wrk);
+      PUTSHORT(RRp->dclass, wrk);
+      wrk += 4; /* TTL = 0 */
+     
+      /* length */
+      len2 = len = SOAlen;
+      PUTSHORT(len, wrk);
+
+      /* SOA */
+      MEMCPY(wrk, RRp->name, domLen);
+      wrk += domLen;
+      MEMCPY(wrk, zmail, mlen);
+      wrk += mlen;
+
+      PUTLONG(zserial, wrk);
+      PUTLONG(zrefresh, wrk);
+      PUTLONG(zretry, wrk);
+      PUTLONG(zexpire, wrk);
+      PUTLONG(zminimum, wrk);
+   }
+   else
+   {
+      /* CNAME */
+      if ((RRp->type == T_CNAME) || (RRp->type == T_NS))
+      {
+         char zname[MAX_DDNS_STR_LEN];
+         int cnameLen;
+
+         cnameLen = dnc_copyout(zname, wrk2); 
+
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + cnameLen);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + cnameLen;
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + cnameLen);
+         MEMCPY(wrk, RRp->name, len);
+
+         wrk += len;
+
+         /* PUTSHORT() is equivalent to an htons() */
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+         wrk += 4; /* TTL = 0 */
+
+         PUTSHORT(cnameLen, wrk);
+         MEMCPY(wrk, zname, cnameLen);
+      }
+      else
+      {
+
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+
+         MEMCPY(wrk, RRp->name, len);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + sizeof(addr);
+
+         wrk += len;
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+
+         wrk += 4; /* TTL = 0 */
+
+         if (parse_ipad(&addr,  &sbitz, wrk2) != NULL)
+         {
+            ns_printf(pio, "bad IP addr, line [%d]\n", nsddnsLineNo);
+            return NULL;
+         }
+
+         len2 = len = sizeof(addr);
+         PUTSHORT(len, wrk);
+         MEMCPY(wrk, &addr, len2);
+      }
+   }
+
+   RRp->next = DDNSReqs.preqs;
+   DDNSReqs.preqs = RRp;
+   wrk = wrk2 + strlen(wrk2) + 1;
+   
+   /* got "}"? */
+   if ((wrk = strstr(wrk, "}")))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rrexistsvdd expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsRrnexist()
+ * 
+ * Process a "rrnexist" command
+ *
+ *
+ *  CLASS    TYPE     RDATA    Meaning
+ *  ------------------------------------------------------------
+ *   NONE     rrset    empty    RRset does not exist
+ *
+ * RRset does not exist.  No RRs with a specified NAME and TYPE
+ *      (in the zone and class denoted by the Zone Section) can exist.
+ *
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+static char *  
+nsddnsRrnexist(void * pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+
+   /* got "rrnexist" find "{" ... "}"*/
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rrexistsvi expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* found "{" - get exists (value independent) */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+
+   RRp->type = atoi(wrk2);
+	
+   RRp->next = DDNSReqs.preqs;
+   DDNSReqs.preqs = RRp; 
+
+   RRp->dclass = C_NONE;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+
+   wrk += len;
+   PUTSHORT(RRp->type, wrk);
+   PUTSHORT(RRp->dclass, wrk);
+   wrk += 4; /* TTL = 0 */
+   PUTSHORT(0, wrk);
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+   
+   /* got "}"? */
+   if ((wrk = strstr(wrk, "}")))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rrnexist expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsRrninus()
+ * 
+ * Process a "rrninus" command
+ *
+ *  CLASS    TYPE     RDATA    Meaning
+ *  ------------------------------------------------------------
+ *   ANY      ANY      empty    Name is in use
+ *
+ * Name is in use.  At least one RR with a specified NAME (in
+ *        the zone and class specified by the Zone Section) must exist.
+ *       Note that this prerequisite is NOT satisfied by empty
+ *       nonterminals.
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char *  
+nsddnsRrninus(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rrexistsvi expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* found "{" - get exists (value independent) */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+	
+   RRp->next = DDNSReqs.preqs;
+   DDNSReqs.preqs = RRp;
+   RRp->dclass = C_ANY;
+   RRp->type = T_ANY;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+
+   wrk += len;
+   PUTSHORT(RRp->type, wrk);
+   PUTSHORT(RRp->dclass, wrk);
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+   
+   /* got "}"? */
+   if ((wrk = strstr(wrk, "}")))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rrninus expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsRrnNinus()
+ *
+ * Process a "rrnninus" command
+ *
+ *
+ *  CLASS    TYPE     RDATA    Meaning
+ *  ------------------------------------------------------------
+ *   NONE     ANY      empty    Name is not in use
+ *
+ * Name is not in use.  No RR of any type is owned by a
+ *    specified NAME.  Note that this prerequisite IS satisfied by
+ *       empty nonterminals.
+ *
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char *  
+nsddnsRrnNinus(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* got "rrnninus" find "{" ... "}"*/
+
+   /* found "{" - get exists (value independent) */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+	
+   RRp->next = DDNSReqs.preqs;
+   DDNSReqs.preqs = RRp;
+   RRp->dclass = C_NONE;
+   RRp->type = C_ANY;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+
+   wrk += len;
+   PUTSHORT(RRp->type, wrk);
+   PUTSHORT(RRp->dclass, wrk);
+   wrk += 4; /* TTL = 0 */
+   PUTSHORT(0, wrk);
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+   
+   /* got "}"? */
+   if ((wrk = strstr(wrk, "}")))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rrnninus expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsUps()
+ * 
+ * Process a "ups" command
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char *  
+nsddnsUps(void *pio, FILE *fp, char *inWrk)
+{
+	char *wrk = inWrk;
+	char *wrk2;
+	char inBuf[MAX_DDNS_STR_LEN];
+	int fbrace = 0;
+
+	nsddnsLineNo--;
+    inBuf[0] = 0;
+
+   /* got "ups" find "{" ... "}"*/
+
+   do
+   {
+      nsddnsLineNo++;
+      if (inBuf[0] == ';')
+         continue;
+
+      if (!fbrace)
+      {
+         if ((wrk = strstr(wrk, "{")) == NULL)
+            continue;
+         else
+            wrk++;
+      }
+
+      fbrace = 1;
+
+      if (*wrk == '\n')
+         continue;
+
+RELOOP:
+      if ((*wrk == '\n') || (*wrk == ';'))
+         continue;
+
+      /* found "{" - get prerequisites */
+      wrk2 = wrk;
+      wrk = strtok(wrk, "{ \t\n}");
+
+      if (wrk)
+      {
+         wrk2 = wrk + strlen(wrk) + 1;
+
+         /* add RRs to an RRset */
+         if (strcmp(wrk, "rr") == 0)
+         {
+            if (!(wrk = nsddnsRr(pio, fp, wrk2)))
+               return NULL;
+            else
+            {
+               wrk = strcpy(inBuf, wrk);
+               goto RELOOP; /* GOTO! */
+            }
+         }
+         else
+         /* delete an RRset */
+            if (strcmp(wrk, "drrs") == 0)
+            {
+               if (!(wrk = nsddnsdRrs(pio, fp, wrk2)))
+                  return NULL;
+               else
+               {
+                  wrk = strcpy(inBuf, wrk);
+                  goto RELOOP; /* GOTO! */
+               }
+            }
+            else
+               /* delete all RRsets from a name */
+               if (strcmp(wrk, "darr") == 0)
+               {
+                  if (!(wrk = nsddnsdaRr(pio, fp, wrk2)))
+                     return NULL;
+                  else
+                  {
+                     wrk = strcpy(inBuf, wrk);
+                     goto RELOOP; /* GOTO! */
+                  }
+               }
+               else
+                  /* delete an R from an RRset */
+                  if (strcmp(wrk, "drr") == 0)
+                  {
+                     if (!(wrk = nsddnsdRr(pio, fp, wrk2)))
+                        return NULL;
+                     else
+                     {
+                        wrk = strcpy(inBuf, wrk);
+                        goto RELOOP; /* GOTO! */
+                     }
+                  }
+      }
+      else 
+         wrk = wrk2;
+ 
+      /* got "}"? */
+      if ((wrk = strstr(wrk, "}")))
+      {
+         nsddnsLineNo++;
+         return fgets(inBuf, sizeof(inBuf), fp);
+      }
+   }
+   while ((wrk = fgets(inBuf, sizeof(inBuf), fp)));
+
+   ns_printf(pio, "ups has no body, line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsRr()
+ * 
+ * Process a "rr" command, add RR to RRset
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char * 
+nsddnsRr(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+   short len2;
+   short shortWork;
+   unsigned long addr;
+   unsigned sbitz = 0;
+
+   /* got "rr" find "{" ... "}"*/
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rr expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   } 
+
+   /* found "{" - get name, type , data */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2); 
+
+   /* get type  */
+   wrk2 = strtok(NULL, "{, \t}");
+   RRp->type = atoi(wrk2);
+
+   /* get data  */
+   wrk2 = strtok(NULL, "{, \t}");
+   RRp->dclass = C_IN;
+
+   /* SOA */
+   if (RRp->type == T_SOA)
+   {
+      /*
+       * 3.3.13. SOA RDATA format
+       *
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     MNAME                     /
+       *    /                                               /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     RNAME                     /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    SERIAL                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    REFRESH                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                     RETRY                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    EXPIRE                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    MINIMUM                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       */
+
+      char zmail[MAX_DDNS_STR_LEN];
+      int mlen;
+      int SOAlen;
+      int domLen;
+      unsigned long serial;
+      u_long zserial;
+      u_long zrefresh;
+      u_long zretry;
+      u_long zexpire;
+      u_long zminimum;
+
+      zserial = atol(wrk2);  /* serial */
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zrefresh = atol(wrk2);  
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zretry = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zexpire = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zminimum = atol(wrk2); 
+
+       mlen = dnc_copyout(zmail, "z.z"); 
+
+      /* alloc memory for full RR */
+      RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + 
+		   (SOAlen = len + /* comp len of SOA */
+		   mlen + /* comp len of mail addr */
+		   5 * 4 /* 5 longs */)
+		   );
+      MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + 
+		   SOAlen);
+
+      MEMCPY(wrk, RRp->name, len);
+
+      RRp->RDlength = len + TYPE_RDLENGTH_SIZE + 
+		   SOAlen;
+
+      wrk += len;
+      domLen = len;
+
+      /* PUTSHORT() is equivalent to an htons() */
+      PUTSHORT(RRp->type, wrk);
+      PUTSHORT(RRp->dclass, wrk);
+      wrk += 4; /* TTL = 0 */
+     
+      /* length */
+      len2 = len = SOAlen;
+      PUTSHORT(len, wrk);
+
+      /* SOA */
+      MEMCPY(wrk, RRp->name, domLen);
+      wrk += domLen;
+      MEMCPY(wrk, zmail, mlen);
+      wrk += mlen;
+
+      PUTLONG(zserial, wrk);
+      PUTLONG(zrefresh, wrk);
+      PUTLONG(zretry, wrk);
+      PUTLONG(zexpire, wrk);
+      PUTLONG(zminimum, wrk);
+   }
+   else
+   {
+      /* CNAME */
+      if ((RRp->type == T_CNAME) || (RRp->type == T_NS))
+      {
+         char zname[MAX_DDNS_STR_LEN];
+         int cnameLen;
+
+         cnameLen = dnc_copyout(zname, wrk2); 
+
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + cnameLen);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + cnameLen;
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + cnameLen);
+         MEMCPY(wrk, RRp->name, len);
+
+         wrk += len;
+
+         /* PUTSHORT() is equivalent to an htons() */
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+         wrk += 4; /* TTL = 0 */
+
+         PUTSHORT(cnameLen, wrk);
+         MEMCPY(wrk, zname, cnameLen);
+      }
+      else
+      {
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+
+         MEMCPY(wrk, RRp->name, len);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + sizeof(addr);
+
+         wrk += len;
+
+         /* PUTSHORT() is equivalent to an htons() */
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+         wrk += 4; /* TTL = 0 */
+     
+         if (parse_ipad(&addr,  &sbitz, wrk2) != NULL)
+         {
+            ns_printf(pio, "bad IP addr, line [%d]\n", nsddnsLineNo);
+            return NULL;
+         }
+
+         len2 = len = sizeof(addr);
+         PUTSHORT(len, wrk);
+         MEMCPY(wrk, &addr, len2);
+      }
+   } 
+
+   RRp->next = DDNSReqs.ups;
+   DDNSReqs.ups = RRp;
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+		   
+   /* got "}"? */
+   if (strstr(wrk, "}"))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "rr expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsdRrs()
+ * 
+ * Process a "drrs" command, delete RR set
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char * 
+nsddnsdRrs(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+
+   /* got "drrs" find "{" ... "}"*/
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rr expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   } 
+
+   /* found "{" - get name, type , data */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+
+   RRp->type = atoi(wrk2);
+
+   RRp->dclass = C_ANY;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+
+   wrk += len;
+
+   PUTSHORT(RRp->type, wrk);
+   PUTSHORT(RRp->dclass, wrk);
+   wrk += 4; /* TTL = 0 */
+   PUTSHORT(0, wrk);
+
+   RRp->next = DDNSReqs.ups;
+   DDNSReqs.ups = RRp;
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+		   
+   /* got "}"? */
+   if (strstr(wrk, "}"))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+  ns_printf(pio, "drrs expects '}', line [%d]\n", nsddnsLineNo);
+  return NULL;
+}
+
+
+/* FUNCTION: nsddnsdaRr()
+ * 
+ * Process a "darr" command, delete all RR from a set
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char * 
+nsddnsdaRr(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+
+   /* got "darr" find "{" ... "}"*/
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rr expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   } 
+
+   /* found "{" - get name */
+   wrk2 = strtok(wrk, "{ \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   RRp->type = T_ANY;
+   RRp->dclass = C_ANY;
+
+   /* alloc memory for full RR */
+   RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE);
+   MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE);
+
+   MEMCPY(wrk, RRp->name, len);
+   wrk += len;
+   RRp->RDlength = len + TYPE_RDLENGTH_SIZE;
+
+   PUTSHORT(RRp->type, wrk);
+   PUTSHORT(RRp->dclass, wrk);
+   wrk += 4; /* TTL = 0 */
+   PUTSHORT(0, wrk);
+
+   RRp->next = DDNSReqs.ups;
+   DDNSReqs.ups = RRp;
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+		   
+   /* got "}"? */
+   if (strstr(wrk, "}"))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+  ns_printf(pio, "darr expects '}', line [%d]\n", nsddnsLineNo);
+  return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsdRr()
+ * 
+ * Process a "drr" command, delete an RR from an RR set
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char * 
+nsddnsdRr(void *pio, FILE *fp, char *inWrk)
+{
+   char *wrk = inWrk;
+   char *wrk2;
+   char inBuf[MAX_DDNS_STR_LEN];
+   RR *RRp;
+   short len;
+   short len2;
+   unsigned long addr;
+   unsigned sbitz = 0;
+
+   /* got "drr" find "{" ... "}"*/
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "rr expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   } 
+
+   /* found "{" - get name, type , data */
+   wrk2 = strtok(wrk, "{, \t}");
+
+   RRp = (RR*) npalloc(sizeof(RR));
+   MEMSET(RRp, 0, sizeof(RR));
+
+   len = dnc_copyout(RRp->name, wrk2);
+
+   wrk2 = strtok(NULL, "{, \t}");
+
+   RRp->type = atoi(wrk2);
+   RRp->dclass = C_NONE;
+
+   wrk2 = strtok(NULL, "{, \t}");
+   RRp->dclass = C_NONE;
+
+   /* SOA */
+   if (RRp->type == T_SOA)
+   {
+      /*
+       * 3.3.13. SOA RDATA format
+       *
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     MNAME                     /
+       *    /                                               /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    /                     RNAME                     /
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    SERIAL                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    REFRESH                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                     RETRY                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    EXPIRE                     |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       *    |                    MINIMUM                    |
+       *    |                                               |
+       *    +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+       */
+
+      char zmail[MAX_DDNS_STR_LEN];
+      int mlen;
+      int SOAlen;
+      int domLen;
+      u_long zserial;
+      u_long zrefresh;
+      u_long zretry;
+      u_long zexpire;
+      u_long zminimum;
+
+      zserial = atol(wrk2);  /* serial */
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zrefresh = atol(wrk2);  
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zretry = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zexpire = atol(wrk2); 
+
+      wrk2 = strtok(NULL, "{, \t}");
+      zminimum = atol(wrk2); 
+
+       mlen = dnc_copyout(zmail, "z.z"); 
+
+       /* alloc memory for full RR */
+       RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + 
+		   (SOAlen = len + /* comp len of SOA */
+		   mlen + /* comp len of mail addr */
+		   5 * 4 /* 5 longs */));
+
+       MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + SOAlen);
+       MEMCPY(wrk, RRp->name, len);
+
+       RRp->RDlength = len + TYPE_RDLENGTH_SIZE + SOAlen;
+
+       wrk += len;
+       domLen = len;
+
+       /* PUTSHORT() is equivalent to an htons() */
+       PUTSHORT(RRp->type, wrk);
+       PUTSHORT(RRp->dclass, wrk);
+       wrk += 4; /* TTL = 0 */
+     
+       /* length */
+       len2 = len = SOAlen;
+       PUTSHORT(len, wrk);
+
+       /* SOA */
+       MEMCPY(wrk, RRp->name, domLen);
+       wrk += domLen;
+       MEMCPY(wrk, zmail, mlen);
+       wrk += mlen;
+
+       PUTLONG(zserial, wrk);
+       PUTLONG(zrefresh, wrk);
+       PUTLONG(zretry, wrk);
+       PUTLONG(zexpire, wrk);
+       PUTLONG(zminimum, wrk);
+   }
+   else
+   {
+      /* CNAME */
+      if ((RRp->type == T_CNAME) || (RRp->type == T_NS))
+      {
+         char zname[MAX_DDNS_STR_LEN];
+         int cnameLen;
+
+         cnameLen = dnc_copyout(zname, wrk2); 
+
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + cnameLen);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + cnameLen;
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + cnameLen);
+         MEMCPY(wrk, RRp->name, len);
+
+         wrk += len;
+
+         /* PUTSHORT() is equivalent to an htons() */
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+         wrk += 4; /* TTL = 0 */
+
+         PUTSHORT(cnameLen, wrk);
+         MEMCPY(wrk, zname, cnameLen);
+      }   
+      else
+      {
+         /* alloc memory for full RR */
+         RRp->RdataP = wrk = (char *) npalloc(len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+         MEMSET(wrk, 0, len + TYPE_RDLENGTH_SIZE + sizeof(addr));
+
+         MEMCPY(wrk, RRp->name, len);
+         RRp->RDlength = len + TYPE_RDLENGTH_SIZE + sizeof(addr);
+
+         wrk += len;
+         PUTSHORT(RRp->type, wrk);
+         PUTSHORT(RRp->dclass, wrk);
+         wrk += 4; /* TTL = 0 */
+
+         if (parse_ipad(&addr, &sbitz, wrk2) != NULL)
+         {
+            ns_printf(pio, "bad IP addr, line [%d]\n", nsddnsLineNo);
+            return NULL;
+         }
+
+         len2 = len = sizeof(addr);
+         PUTSHORT(len, wrk);
+
+         MEMCPY(wrk, &addr, len2);
+      }
+   }
+
+   RRp->next = DDNSReqs.ups;
+   DDNSReqs.ups = RRp;
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+		   
+   /* got "}"? */
+   if (strstr(wrk, "}"))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+  ns_printf(pio, "drr expects '}', line [%d]\n", nsddnsLineNo);
+  return NULL;
+}
+
+
+
+/* FUNCTION: nsddnsZone()
+ * 
+ * Process a "zone" command
+ *
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+static char *  
+nsddnsZone(void * pio, FILE *fp, char *inWrk)
+{
+   char *wrk2;
+   char *wrk = inWrk;
+   char inBuf[MAX_DDNS_STR_LEN];
+
+   if (DDNSReqs.zone)
+   {
+      ns_printf(pio,"only one ZONE is allowed, line [%d]\n", nsddnsLineNo);
+      return NULL;
+   }
+
+   /* got "zone" find "{" ... "}"*/
+
+   if ((wrk = strstr(wrk, "{")) == NULL)
+   {
+      ns_printf(pio, "zone expects '{', line [%d]\n", nsddnsLineNo);
+      return NULL;
+   } 
+
+   wrk2 = strtok(wrk, "{ \t}");
+
+   DDNSReqs.zone = (char *)npalloc(strlen(wrk2) + 1);
+   strcpy(DDNSReqs.zone, wrk2);
+
+   wrk = wrk2 + strlen(wrk2) + 1;
+
+   /* got "}"? */
+   if (strstr(wrk, "}"))
+   {
+      nsddnsLineNo++;
+      return fgets(inBuf, sizeof(inBuf), fp);
+   }
+
+   ns_printf(pio, "zone expects '}', line [%d]\n", nsddnsLineNo);
+   return NULL;
+}
+
+#endif /* DNS_CLIENT_UPDT */
+
+#endif   /* DNS_CLIENT */
+
+/* end of file dnsclnt.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/heapbuf.h b/FPGA_nios/hit_pat_bsp/iniche/src/net/heapbuf.h
new file mode 100644
index 0000000..5c1ce64
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/heapbuf.h
@@ -0,0 +1,71 @@
+/* heapbuf.h
+ *
+ * Buffers allocated from the heap are called heap buffers.  The other two 
+ * types of buffers, little buffers and big buffers, are referred to as 
+ * regular buffers.
+ */
+
+#ifndef _HEAPBUF_H_
+#define _HEAPBUF_H_ 1
+
+/* enumerated type that is used to describe whether the heap memory
+ * is "protected" (i.e., its consistency is maintained) via semaphores 
+ * (HEAP_ACCESS_BLOCKING) or other mechanisms that do not cause the 
+ * caller to block (such as by disabling/enabling interrupts) (HEAP_-
+ * ACCESS_NONBLOCKING).
+ */
+enum heap_type
+{
+HEAP_ACCESS_BLOCKING,
+HEAP_ACCESS_NONBLOCKING
+};
+
+/* Data structure that is used to contain information about heap-based
+ * allocations (primarily for debugging purposes).  Since this data
+ * structure is managed via the primitives in q.c/q.h, the 'next' field
+ * must be the first field in the data structure.  This data structure
+ * is referred to as a PHLE in the code and documentation.
+ */
+struct priv_hbuf_list
+{
+   struct priv_hbuf_list * next; /* must be first field in structure */
+   struct netbuf * netbufp;      /* pointer to PACKET */
+   char * databufp;              /* pointer to data buffer */
+   u_long length;                /* length of data buffer, including guard band */
+};
+
+typedef struct priv_hbuf_list PHLE;
+typedef struct priv_hbuf_list * PHLEP;
+
+/* Indexes into the hbufstats [] array for various failure and success conditions 
+ * encountered in the heap buffer allocation and deallocation processes */
+#define TOOBIG_ALLOC_ERR             0 /* number of times allocation requested a length greater than 
+                                        * MAX_ALLOC_FROM_HEAP */
+#define LIMIT_EXCEEDED_ERR           1 /* number of times a request for an allocation from the heap would
+                                        * have caused the max threshold (MAX_TOTAL_HEAP_ALLOC) to be exceeded */
+#define NB_ALLOCFAIL_ERR             2 /* number of times couldn't allocate struct netbuf block from heap */
+#define DB_ALLOCFAIL_ERR             3 /* number of times couldn't allocate data buffer block from heap */
+#define PHLEB_ALLOCFAIL_ERR          4 /* number of times couldn't allocate private heapbuf list element block from heap */
+#define HB_ALLOC_SUCC                5 /* number of times successfully allocated memory for struct netbuf 
+                                        * and data buffer (and private heapbuf list block, if HEAPBUFS_DEBUG 
+                                        * is defined) */
+#define INCONSISTENT_HBUF_LEN_ERR    6 /* number of instances when either (1) packet being freed was greater 
+                                        * than bigbufsiz (in 'nb_blen' field), but 'flags' did not have 
+                                        * PKF_HEAPBUF flag set OR (2) when packet being freed had a length 
+                                        * field in 'nb_blen' that was not consistent with what was stored 
+                                        * in the corresponding entry in the private heapbuf list */
+#define NO_PHLE_ERR                  7 /* number of times packet being freed did not match any entry in the
+                                        * private heapbuf list */
+#define HB_GUARD_BAND_VIOLATED_ERR   8 /* number of instances when pk_validate () discovered that a heap buffer's
+                                        * left or right guard band was violated */
+#define HBUF_NUM_STATS               9 /* number of entries in hbufstats array */
+
+/* maximum amount of memory that can be allocated from the heap at 
+ * any given time (this is the sum total of all heap-based allocations) */
+#define MAX_TOTAL_HEAP_ALLOC 524288 /* 512K bytes */
+
+/* maximum amount of memory that can allocated from the heap in one 
+ * request (i.e., via one call to pk_alloc ()) */
+#define MAX_INDIVIDUAL_HEAP_ALLOC 65535
+
+#endif /* _HEAPBUF_H_ */
\ No newline at end of file
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/ifmap.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/ifmap.c
new file mode 100644
index 0000000..0b123c1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/ifmap.c
@@ -0,0 +1,170 @@
+/*
+ * FILENAME: ifmap.c
+ *
+ * Copyright 2001 - 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ * "Database" of iface to iface mappings. These are designed as an
+ * administrate and configuration tool - application code can
+ * set up the mappings, and the lower-level driver code will use
+ * it to build IP tunnels, PPPoE links, and other constructions
+ * that involve more than one interface. A lower
+ * iface can be paired with more than one upper (eg PPPoE) and
+ * Visa-versa.
+ *
+ * ROUTINES: ifmap_bind(), ifmap_nextupper(), ifmap_nextlower(), ifmap_del(),
+ *
+ * MODULE: PPP
+ *
+ * PORTABLE: YES
+ *
+ */
+
+
+#include "ipport.h"
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "ifmap.h"
+
+/* the actual pairs database: */
+struct iface_pair ifpairs[MAX_IFPAIRS];
+
+
+/* FUNCTION: ifmap_bind()
+ * 
+ * bind a pair of ifaces together.
+ *
+ * PARAM1: NET upper
+ * PARAM2: NET lower
+ *
+ * RETURNS: 0 if OK or ENP_RESOURCE if it can't get a free entry.
+ */
+
+int
+ifmap_bind(NET upper, NET lower)
+{
+   int i;
+
+   for(i = 0; i < MAX_IFPAIRS; i++)
+   {
+      if((ifpairs[i].lower == NULL) &&
+         (ifpairs[i].upper == NULL))
+      {
+         ifpairs[i].lower = lower;
+         ifpairs[i].upper = upper;
+         return 0;
+      }
+   }
+   return ENP_RESOURCE;      /* no free array entries */
+}
+
+/* FUNCTION: ifmap_nextupper()
+ * 
+ * Get the upper iface of a bound pair for the passed lower iface.
+ * This returns the first match if "lower" is NULL, else the next
+ * match after the passed lower.
+ *
+ * PARAM1: NET upper
+ * PARAM2: NET lower
+ *
+ * RETURNS: 
+ */
+
+NET
+ifmap_nextupper(NET upper, NET lower)
+{
+   int i;
+   int matched = FALSE;
+
+   for(i = 0; i < MAX_IFPAIRS; i++)
+   {
+      if(ifpairs[i].lower == lower)
+      {
+         if((upper == NULL) ||
+           (matched))
+         {
+            return ifpairs[i].upper;
+         }
+         else if(ifpairs[i].upper == upper)
+            matched = TRUE;
+      }
+   }
+   return NULL;     /* not found, or no "next" */
+}
+
+/* FUNCTION: ifmap_nextlower()
+ * 
+ * Get the lower iface of a bound pair for the passed upper iface.
+ *
+ * PARAM1: NET upper
+ * PARAM2: NET lower
+ *
+ * RETURNS: pointer tp lower iface, NULL if error
+ */
+
+NET
+ifmap_nextlower(NET upper, NET lower)
+{
+   int i;
+   int matched = FALSE;
+
+   for(i = 0; i < MAX_IFPAIRS; i++)
+   {
+      if(ifpairs[i].upper == upper)
+      {
+         if((lower == NULL) ||
+            (matched))
+         {
+            return ifpairs[i].lower;
+         }
+         else if(ifpairs[i].lower == lower)
+            matched = TRUE;
+      }
+   }
+   return NULL;     /* not found */
+}
+
+/* FUNCTION: ifmap_del()
+ * 
+ * delete all instances  of interface pairs which match the passed
+ * NET parameters. NULL NET is treated as a wildcard.
+ *
+ * PARAM1: NET upper
+ * PARAM2: NET lower
+ *
+ * RETURNS: 
+ */
+ 
+void
+ifmap_del(NET upper, NET lower)
+{
+   int   i;
+
+   /* loop through pairs */
+   for(i = 0; i < MAX_IFPAIRS; i++)
+   {
+      if(ifpairs[i].lower == lower)
+      {
+         if((ifpairs[i].upper == upper) ||
+            (upper == NULL))
+         {
+            /* lower matches, and upper is match or wildcard. */
+            ifpairs[i].upper = ifpairs[i].lower = NULL;
+         }
+      }
+      if(ifpairs[i].upper == upper)
+      {
+         if((ifpairs[i].lower == lower) ||
+            (lower == NULL))
+         {
+            /* upper matches, and lower is match or wildcard. */
+            ifpairs[i].upper = ifpairs[i].lower = NULL;
+         }
+      }
+   }
+}
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/macloop.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/macloop.c
new file mode 100644
index 0000000..fd320c8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/macloop.c
@@ -0,0 +1,577 @@
+/*
+ * FILENAME: macloop.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * macloop.c loopback driver to loop packets back at MAC layer, as 
+ * opposed to IP layer loopback. This emulates and ethernet driver, 
+ * even to the point of supporting ARP.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: prep_lb(), lb_raw_send(), lb_pkt_send(), lb_init(), lb_stats(), 
+ * ROUTINES: lb_reg_type(), lb_close(), 
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1996 by NetPort Software. */
+
+#include "ipport.h"
+
+#ifdef MAC_LOOPBACK  /* whole file can be ifdeffed away */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ether.h"
+#include "arp.h"
+#include "ip.h"
+
+#ifdef IP_V6
+#include "ip6.h"
+extern int ip6_dupchecks;
+#endif   /* IP_V6 */
+
+#include "tcp.h"
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"       /* for if_configbyname() prototype */
+#endif
+
+/* define LB_RAW_SEND to use raw send instead of pkt send. The raw send 
+ * is slower, but it's a more realistic test. 
+*/
+/*
+#ifdef LB_RAW_SEND
+*/
+
+/* declare the MAC loopback iface routines */
+int   lb_init(int iface);
+int   lb_reg_type(unshort type, struct net * netp);
+int   lb_raw_send(struct net * netp, char * buffer, unsigned length);
+int   lb_pkt_send(PACKET pkt);
+int   lb_close(int iface);
+
+#ifdef NET_STATS
+void  lb_stats(void *, int iface);
+#else
+#define lb_stats NULL
+#endif   /* NET_STATS */
+
+#ifdef DYNAMIC_IFACES   /* dynamic extensions */
+int   lb_setstate(struct net * ifp, int state);
+int   lb_create(struct net * ifp, void * bindinfo);
+#endif   /* DYNAMIC_IFACES */
+
+/* internal */
+void  lb_ifsetup(NET netp);
+
+/* these will be set TRUE as types are registered */
+int   acceptIP  =  FALSE;
+int   acceptARP =  FALSE;
+
+static char lpbhaddr[6]= {'L', 'P', 'B', 'A', 'C', 'K'}; 
+
+static int lbnets = 0;     /* number of loopback nets set up */
+
+/* FUNCTION: prep_lb()
+ *
+ * Prep routine for static MAC loopback driver. This does
+ * it's work be calling lb_ifsetup(), which is shared with the
+ * dynamic MAC loopback driver logic.
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: index of static MAC iface
+ */
+
+int
+prep_lb(int iface)
+{
+   if (iface >= STATIC_NETS)   /* Max static entries usued? */
+      return(iface);    /* return count we were passed */
+
+   lb_ifsetup(nets[iface]);
+
+   lbnets++;
+   return (iface+1); /* return index of next iface */
+}
+
+/* FUNCTION: lb_ifsetup()
+ *
+ * Set up net interface routine pointers, etc, before 
+ * trying to init the net. Be sure the space for these is
+ * already allocated.
+ *
+ * 
+ * PARAM1: NET structure to be filled in
+ *
+ * RETURNS: void
+ */
+
+void
+lb_ifsetup(NET netp)
+{
+   IFMIB mib;
+
+   netp->n_ipaddr = htonl(0x7f000001);     /* 127.0.0.1 */
+   netp->n_defgw  = htonl(0x00000000);
+   netp->snmask   = htonl(0xFF000000);
+   netp->n_lnh = ETHHDR_SIZE;   /* space reserved for ethernet header */
+#ifdef IEEE_802_3
+   netp->n_lnh += sizeof(struct snap_hdr);   /* The bloated version */
+#endif
+   netp->n_hal = 6;    /* hardware address length */
+   netp->n_mib->ifType = LOOPIFTYPE;
+
+   /*
+    * Yes! In Interniche Stack Lingo, MTU for Ethernet II and IEEE 802.3 is
+    * identical. Since the n_mtu field indicates the total frame size sent on
+    * the wire, and not MTU in the usual sense. If things are correctly set up
+    * then (n_mtu - n_lnh) should give us the actual MTU (or the MTU in the 
+    * usual sense of the term.
+    */
+#ifdef IEEE_802_3
+   netp->n_mtu = 1514; /* max frame size */
+#else
+   netp->n_mtu = 1514; /* max frame size */
+#endif
+
+   if(netp->name[0] == 0)
+   {
+      netp->name[0] = 'l';
+      netp->name[1] = 'o';
+      netp->name[2] = (char)('0' + lbnets);
+   }
+   netp->n_flags |= NF_NBPROT;
+
+#ifdef IP_V6
+   {
+   int i;
+   int keepDup;
+   char * cp;
+
+   netp->n_flags |= NF_IPV6;  /* set flag for v6 compatability */
+
+   /* set up the standard v6 loopback addresses */
+   for(i = IPA_LINK; i <= IPA_GLOBAL; i++)
+   {
+
+	   							      IPV6LOG(("+ lb_ifsetup   ip6_dupchecks = %d, i = %d\n", ip6_dupchecks, i));
+
+
+      keepDup = ip6_dupchecks;  /* loopback can't affect DAD */
+      netp->v6addrs[i] = ip6_mkaddr(netp, i, &ip6loopback);
+	  ip6_dupchecks = keepDup;
+      netp->v6addrs[i]->prefix = 128;
+      netp->v6addrs[i]->flags = IA_PREFERRED;
+
+							      IPV6LOG(("+ lb_ifsetup  2 ip6_dupchecks = %d, i = %d\n", ip6_dupchecks, i));
+
+
+      cp = (char *)&netp->v6addrs[i]->addr;
+      switch(i)
+        {
+         case IPA_LINK:
+            *cp++ = (char)0xFE;     /* paste in the link-local prefix */
+            *cp   = (char)0x80;
+            break;
+         case IPA_SITE:
+            *cp++ = (char)0xFE;     /* paste in the site-local prefix */
+            *cp   = (char)0xC0;
+            break;
+         case IPA_GLOBAL:     /* leave it all zeros */
+            break;
+         default:
+            dtrap();
+         }
+	  				              IPV6DUMP("+ lb_ifsetup addr = \n", (char *)&netp->v6addrs[i]->addr, 16);
+							      IPV6LOG(("+ lb_ifsetup   netp->v6addrs[i]->flags = %d\n", netp->v6addrs[i]->flags));
+   }
+   }
+#endif   /* IP_V6 */
+
+   /* search the NV parameters for iface setup for our name. If this
+    * fails we just default to what's already in the ifp.
+    */
+#ifdef INCLUDE_NVPARMS
+   if_configbyname(netp);
+#endif
+#ifdef DYNAMIC_IFACES   /* dynamic extensions */
+   netp->n_setstate = lb_setstate;
+#endif  /* DYNAMIC_IFACES */
+
+   mib = netp->n_mib;
+   mib->ifAdminStatus = 2;  /* status = down */
+   mib->ifOperStatus = 2;   /* will be set up in init()  */
+   mib->ifLastChange = cticks * (100 / TPS);
+   mib->ifPhysAddress = (u_char *)&lpbhaddr[0];
+   mib->ifDescr = (u_char *)"loopback (pseudo ethernet)";
+   mib->ifIndex = if_netnumber(netp);
+
+#ifdef IP_V6
+   /* IPv6 has very specific requirements for loopback behaviour */
+   mib->ifType = LOOPIFTYPE;
+#else
+   /* For IPV4 it's convenient to masquerade as ethernet, so we can
+    * test ARP, DHCP, etc., in loopback.
+    */
+   mib->ifType = ETHERNET;
+#endif
+
+   mib->ifSpeed = 10000000;
+   mib->ifMtu = 1500;         /* ethernetish default */
+
+   /* install our hardware driver routines */
+   netp->n_init = lb_init;
+#ifdef LB_RAW_SEND
+   netp->raw_send = lb_raw_send;
+#else /* use packet send */
+   netp->pkt_send = lb_pkt_send;
+#endif   /* LB_RAW_SEND */
+   netp->n_close = lb_close;
+   netp->n_stats = lb_stats;
+}
+
+
+#ifdef LB_RAW_SEND
+/* FUNCTION: lb_raw_send()
+ *
+ * lb_raw_send() - this loopback send routine goes through the 
+ * motions as though it's going to send a packet on an ethernet 
+ * device, then just drops it in the received packet queue. 
+ *
+ * 
+ * PARAM1: struct net * netp
+ * PARAM2: char * buffer
+ * PARAM3: unsigned length
+ *
+ * RETURNS: 0 if OK, else ENP_ error code
+ */
+
+int
+lb_raw_send(struct net * netp, char * buffer, unsigned length)
+{
+   struct ethhdr *   eth;
+   IFMIB mib;
+   PACKET pkt;
+
+#ifdef NPDEBUG
+   /* Sanity check interface pointer */
+   if(netp->raw_send != lb_raw_send)
+   {
+      dprintf("macloop: bad net\n");
+      dtrap();
+   }
+#endif
+
+   /* Don't send if iface is logically down */
+   if(netp->n_mib->ifAdminStatus != NI_UP)
+   {
+      netp->n_mib->ifOutDiscards++; /* bump mib counter for these */
+      return ENP_LOGIC;    /* right thing to do? */
+   }
+
+   /* maintain mib xmit stats */
+   mib = netp->n_mib;
+   if (*buffer & 0x01)  /* see if multicast bit is on */
+      mib->ifOutNUcastPkts++;
+   else
+      mib->ifOutUcastPkts++;
+   mib->ifOutOctets += length;
+
+   /* at this point we make the logical switch from sending to receiving */
+
+   /* fill in a packet for the "received" buffer */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pkt = pk_alloc(length);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (!pkt)
+   {
+      mib->ifInDiscards++;
+      return ENP_RESOURCE;
+   }
+   MEMCPY(pkt->nb_buff, buffer, length);
+   pkt->nb_prot = pkt->nb_buff + ETHHDR_SIZE;   /* point to IP header */
+   pkt->nb_plen = length - ETHHDR_SIZE;   /* IP length */
+   pkt->net = netp;
+   eth = (struct ethhdr *)(pkt->nb_buff + ETHHDR_BIAS);
+   MEMCPY(eth->e_dst, (void *)lpbhaddr, 6);
+   MEMCPY(eth->e_src, (void *)lpbhaddr, 6);
+   pkt->type = eth->e_type;
+
+   mib->ifInOctets += length;
+
+   /* queue the packet in rcvdq */
+   putq(&rcvdq, (q_elt)pkt);
+
+   /* Most ports should now wake the packet demuxer task */
+   SignalPktDemux();
+
+   return 0;   /* OK return */
+}
+#else
+/* FUNCTION: lb_raw_send()
+ *
+ * lb_raw_send() - this loopback send routine goes through the 
+ * motions as though it's going to send a packet on an ethernet 
+ * device, then just drops it in the received packet queue. 
+ *
+ * 
+ * PARAM1: struct net * netp
+ * PARAM2: char * buffer
+ * PARAM3: unsigned length
+ *
+ * RETURNS: 0 if OK, else ENP_ error code
+ */
+
+int
+lb_pkt_send(PACKET pkt)
+{
+   NET      netp;
+   IFMIB    mib;
+   int      length;
+   struct ethhdr *   eth;
+#ifdef ROUTE_TEST
+   struct ip *       pip;  /* headers for packet alterations */
+   struct tcphdr *   ptcp;
+#endif /* ROUTE_TEST */
+
+   netp = pkt->net;
+
+#ifdef NPDEBUG
+   /* Sanity check interface pointer */
+   if(netp->pkt_send != lb_pkt_send)
+   {
+      dprintf("macloop: bad net\n");
+      dtrap();
+   }
+#endif
+
+   length= pkt->nb_plen;
+   mib = netp->n_mib;
+
+   /* Don't send if iface is logically down */
+   if(mib->ifAdminStatus != NI_UP)
+   {
+      mib->ifOutDiscards++; /* bump mib counter for these */
+      return ENP_LOGIC;    /* right thing to do? */
+   }
+
+   /* maintain mib xmit stats */
+   if (*(pkt->nb_prot + ETHHDR_BIAS) & 0x01)  /* see if multicast bit is on */
+      mib->ifOutNUcastPkts++;
+   else
+      mib->ifOutUcastPkts++;
+   mib->ifOutOctets += length;
+
+   /* at this point we make the logical switch from sending to receiving. 
+    * nb_prot, nb_plen and type should be set to the MAC (ethernet) header
+    * by the send_via_arp() code.
+    */
+   eth = (struct ethhdr *)(pkt->nb_prot + ETHHDR_BIAS);
+   pkt->type = eth->e_type;
+   pkt->nb_prot += ETHHDR_SIZE;
+   pkt->nb_plen -= ETHHDR_SIZE;
+   mib->ifInOctets += length;
+
+#ifdef IEEE_802_3
+   /* See if sender is legacy IEEE machine. If we were not using the 
+    * NF_NBPROT bit in this device we could skip this step and the packet
+    * would get trapped by the logic in pktdemux.c
+    */
+   if(pkt->type >= 0x0600)
+   {
+      struct snap_hdr * snap;
+
+      /* set up type and nb_prot for SNAP packet */
+      snap = (struct snap_hdr *)(((char*)eth) + ETHHDR_SIZE - ETHHDR_BIAS);
+
+      pkt->type = snap->type;
+      pkt->nb_prot += sizeof(struct snap_hdr);
+      pkt->nb_plen -= sizeof(struct snap_hdr);
+   }
+#endif
+
+#ifdef ROUTE_TEST
+   pip = (struct ip *)pkt->nb_prot;    /* hunt for IP header */
+
+   /* If the two IP addreses are not both 127.1, then we may be doing a 
+    * routing simulation. Try swapping the IP addresses so the "received"
+    * packet doesn't keep looping back to this driver 
+    */
+   if((eth->e_type == htons(0x0800)) &&   /* make sure we found IP packet */
+      (pip->ip_ver_ihl == 0x45) &&        /* and that we found IP header */
+      (pip->ip_src != pip->ip_dest))
+   {
+      ip_addr tmp;      /* tmp vars for swapping */
+      unshort port;
+
+      tmp = pip->ip_src;         /* swap IP addresses */
+      pip->ip_src = pip->ip_dest;
+      pip->ip_dest = tmp;
+
+      /* If it's UDP or TCP, swap the ports too. This lets us do NAT 
+       * simulations.
+       */
+      if((pip->ip_prot == 6) ||     /* 6 - TCP */
+         (pip->ip_prot == 17))      /* 17 - UDP */
+      {
+         /* use the tcp header struct. The UDP ports are in the same 
+          * locations, so this works for UDP too.
+          */
+         ptcp = (struct tcphdr *)(pip + 1);
+         port = ptcp->th_sport;
+         ptcp->th_sport = ptcp->th_dport;
+         ptcp->th_dport = port;
+      }
+   }
+#endif   /* ROUTE_TEST */
+
+   /* queue the packet in rcvdq */
+   putq(&rcvdq, (q_elt)pkt);
+
+   /* Most ports should now wake the packet demuxer task */
+   SignalPktDemux();
+
+   return 0;   /* OK return */
+}
+
+#endif /* LB_RAW_SEND cs packet send */
+
+
+
+/* FUNCTION: lb_init()
+ *
+ * This is the statis iface init routine.
+ *
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+int
+lb_init(int iface)
+{
+   IFMIB mib;
+
+   mib = nets[iface]->n_mib;
+   mib->ifAdminStatus = 1;    /* set to UP */
+   mib->ifOperStatus = 1;
+   mib->ifLastChange = cticks * (100/TPS);
+
+   return 0;
+}
+
+#ifdef NET_STATS
+
+
+/* FUNCTION: lb_stats()
+ *
+ * lb_stats() - the nets[] stats routine for the MAC loopback driver
+ *
+ * 
+ * PARAM1: void * pio
+ * PARAM2: int iface
+ *
+ * RETURNS: 
+ */
+
+void
+lb_stats(void * pio, int iface)
+{
+   IFMIB mib;
+
+   mib = nets[iface]->n_mib;
+   ns_printf(pio,"status for MAC level looback driver\n");
+   ns_printf(pio,"Types registered: ARP:%s, IP:%s\n", 
+    acceptARP?"YES":"NO", acceptIP?"YES":"NO" );
+   ns_printf(pio,"status: ADMIN:%s OPERATIONAL:%s\n",
+    (mib->ifAdminStatus==1)?"UP":"DOWN",
+    (mib->ifOperStatus==1)?"UP":"DOWN");
+}
+
+#endif   /* NET_STATS */
+
+
+
+/* FUNCTION: lb_reg_type()
+ * 
+ * PARAM1: unshort type
+ * PARAM2: struct net * netp
+ *
+ * RETURNS: 
+ */
+
+int
+lb_reg_type(unshort type, struct net * netp)
+{
+   if (type == htons(0x0800))
+      acceptIP = TRUE;
+   else if(type == htons(0x0806))
+      acceptIP = TRUE;
+   else
+      return -1;  /* this is an error - we only do ARP and IP */
+
+   USE_ARG(netp);
+   return 0;
+}
+
+
+
+/* FUNCTION: lb_close()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+int
+lb_close(int iface)
+{
+   IFMIB mib;
+
+   mib = nets[iface]->n_mib;
+   acceptIP = FALSE;
+   acceptARP = FALSE;
+   mib->ifAdminStatus = 2; /* set both SNMP MIB statuses to disabled */
+   mib->ifOperStatus = 2;
+   return 0;
+}
+
+#ifdef DYNAMIC_IFACES   /* dynamic extensions */
+
+int
+lb_setstate(struct net * ifp, int state)
+{
+   /* no physical work to do on loopback device. Just set state */
+   if(state == NI_UP)
+   {
+      ifp->n_mib->ifAdminStatus = 1; /* set both SNMP MIB statuses to enabled */
+      ifp->n_mib->ifOperStatus = 1;
+   }
+   else
+   {
+      ifp->n_mib->ifAdminStatus = 2; /* set both SNMP MIB statuses to disabled */
+      ifp->n_mib->ifOperStatus = 2;
+   }
+   return 0;
+}
+
+int
+lb_create(struct net * ifp, void * bindinfo)
+{
+   USE_VOID(bindinfo);
+
+   lb_ifsetup(ifp);
+   ifp->name[2] = '0' + ifNumber;   /* tag name with device index */
+   return 0;
+}
+
+#endif   /* DYNAMIC_IFACES */
+
+#endif   /* MAC_LOOPBACK - whole file can be ifdeffed away */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/ping.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/ping.c
new file mode 100644
index 0000000..f0878a5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/ping.c
@@ -0,0 +1,140 @@
+/*
+ * FILENAME: ping.c
+ *
+ * Copyright 1996- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * API call for simple ICMP echo ("ping").
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: icmpEcho(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1994 by NetPort software. */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "icmp.h"
+
+char *   pingdata =  "Ping from NetPort IP stack";  /* default ping data */
+
+
+
+/* FUNCTION: icmpEcho()
+ *
+ * icmpEcho() - ICMP Echo Request (the guts of "ping") Callable from 
+ * Applications. Sends a single "ping" (ICMP echo request) to the 
+ * specified host. Replys are upcalled via Queue event so we can send 
+ * the application's window a Message as we get a reply or timeout. 
+ * 
+ * 
+ * PARAM1: ip_addr host
+ * PARAM2: char * data
+ * PARAM3: unsigned length of data
+ * PARAM4: unshort pingseq
+ *
+ * RETURNS: Returns 0 if started OK, else negative error message. 
+ */
+
+int
+icmpEcho(ip_addr host,  /* host to ping - 32 bit, network-endian */
+   char *   data,       /* ping data, NULL if don't care */
+   unsigned datalen,     /* length of data to attach to ping request */
+   unshort  pingseq)    /* ping sequence number */
+{
+   PACKET   p;
+   int      ip_err;
+   struct ping *  e;
+   struct ip *    pip;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   p = pk_alloc(PINGHDRSLEN + datalen);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (!p)
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & IPTRACE)
+         dprintf("icmp: can't alloc packet\n");
+#endif
+      return(ENP_NOBUFFER);
+   }
+
+   p->nb_prot = p->nb_buff + PINGHDRSLEN;
+   p->nb_plen = datalen;
+   p->fhost = host;
+
+   if(host == 0xFFFFFFFF)  /* broadcast? */
+      p->net = nets[0];    /* then use first iface */
+
+   /* copy in data field */
+   if (data)
+   {
+      MEMCPY(p->nb_prot, data, datalen);
+   }
+   else  /* caller didn't specify data */
+   {
+      unsigned   donedata;
+      strcpy(p->nb_prot, pingdata);
+      donedata = (unsigned)strlen(pingdata);
+      while (donedata < datalen)
+      {
+         *(p->nb_prot + donedata) = (char)((donedata) & 0x00FF);
+         donedata++;
+      }
+   }
+
+   /* adjust packet pointers to icmp ping header */
+   p->nb_prot -= sizeof(struct ping);
+   p->nb_plen += sizeof(struct ping);
+
+   /* fill in icmp ping header */
+   e = (struct ping *)p->nb_prot;
+   e->ptype = ECHOREQ;
+   e->pcode = 0;
+   e->pid = 0;
+   e->pseq = pingseq;
+
+   /* Calculate the checksum */
+   e->pchksum = 0;
+   if (datalen & 1)  /* if data size is odd, pad with a zero */
+      *((char*)(e+1) + datalen) = 0;
+
+   e->pchksum = ~cksum(e, (ICMPSIZE+datalen+1)>>1);
+
+   /* need to fill in IP addresses at this layer too */
+   pip = (struct ip *)(p->nb_prot - sizeof(struct ip));
+   pip->ip_src = ip_mymach(host);
+   pip->ip_dest = host;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   ip_err = ip_write(ICMP_PROT, p);    /* send down to IP layer */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   /* Errors are negative. A zero means send was OK. a positive number
+    * usually means we had to ARP. Assume this will work and count a send.
+    */
+   if(ip_err < 0)
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & NETERR)
+         dprintf("icmp: can't send echo request\n");
+#endif
+      /* rfc 1156 seems to say not to count these. (pg 48) -JB- */
+      /* LOCK_NET_RESOURCE(FREEQ_RESID); */
+      /* pk_free(p); */
+      /* UNLOCK_NET_RESOURCE(FREEQ_RESID); */
+      return(ip_err);
+   }
+   /* fall to here if we sent echo request OK */
+   icmp_mib.icmpOutMsgs++;
+   icmp_mib.icmpOutEchos++;
+
+   return(0);
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/pktalloc.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/pktalloc.c
new file mode 100644
index 0000000..f3a3ef0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/pktalloc.c
@@ -0,0 +1,1024 @@
+/*
+ * FILENAME: pktalloc.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Code to manage the queues of free packet buffers.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: pk_init(), pk_alloc(), pk_validate(), pk_free()
+ * ROUTINES: pk_prepend(), pk_gather()
+ * ROUTINES: pk_alloc_heapbuf(), pk_validate_heapbuf(), pk_free_heapbuf()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990-1994 by NetPort Software  */
+/* Portions Copyright 1986 by Carnegie Mellon  */
+/* Portions Copyright 1984, 1985 by the Massachusetts Institute of Technology  */
+
+/*
+ * Since the various allocation and deallocation functions listed in this 
+ * file can be invoked from both process (or background code for SUPERLOOP-
+ * type systems) and interrupt-level, they must be designed to provide 
+ * mutual exclusion as appropriate (e.g., between task <-> task and between 
+ * task <-> interrupt handler) to ensure the integrity of the various shared 
+ * data structures.
+ *
+ * Shared data structures are "protected" via the {LOCK_NET_RESOURCE 
+ * (FREEQ_RESID) and UNLOCK_NET_RESOURCE (FREEQ_RESID)} or {INCR_SHARED_VAR 
+ * () or DECR_SHARED_VAR ()} or {ENTER_CRIT_SECTION () and EXIT_CRIT_SECTION 
+ * ()} macros (depending upon the design of the target system).  Note that 
+ * the INCR_SHARED_VAR () and DECR_SHARED_VAR (), in turn, use ENTER_CRIT_-
+ * SECTION () and EXIT_CRIT_SECTION () to provide the mutual exclusion.
+ */
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#ifdef HEAPBUFS
+#include "heapbuf.h"
+#endif
+
+
+/* We maintain 2 queues of free buffers, one for smallish packets
+ * like ARPs, TCP acks,and PINGs; and big buffers for large datagrams
+ * like FTP transfers.
+ */
+queue   bigfreeq;    /* big free buffers */
+queue   lilfreeq;    /* small free buffers */
+
+unsigned lilbufs = NUMLILBUFS;      /* number of small bufs to init */
+unsigned lilbufsiz = LILBUFSIZE;    /* big enough for most non-full size packets */
+unsigned bigbufs = NUMBIGBUFS;      /* number of big bufs to init */
+unsigned bigbufsiz = BIGBUFSIZE;    /* big enough for max. ethernet packet */
+
+#ifdef NPDEBUG
+PACKET pktlog[MAXPACKETS]; /* record where the packets are */
+#endif
+
+#ifdef HEAPBUFS
+#ifdef HEAPBUFS_DEBUG
+/* private heapbuf list queue - contains list of all current heapbuf allocations,
+ * and is used for debugging purposes */
+queue phlq;
+#endif /* HEAPBUFS_DEBUG */
+/* variable that is used to indicate whether accesses to the heap may potentially
+ * block (HEAP_ACCESS_BLOCKING) or not (HEAP_ACCESS_NONBLOCKING) */
+enum heap_type heap_type;
+/* data structure that keeps track of various failure and success statistics 
+ * for the heap buffer allocation and deallocation processes */
+u_long hbufstats [HBUF_NUM_STATS];
+/* amount of memory currently allocated from the heap for heap buffers */
+u_long heap_curr_mem;
+/* high watermark for 'heap_curr_mem' */
+u_long heap_curr_mem_hi_watermark;
+
+/* allocate a heap buffer */
+PACKET pk_alloc_heapbuf (unsigned len);
+/* validate a returned heap buffer */
+int pk_validate_heapbuf (PACKET pkt);
+/* deallocate a heap buffer */
+void pk_free_heapbuf (PACKET pkt);
+/* dump heap buffer statistics */
+int dump_hbuf_stats (void * pio);
+#endif /* HEAPBUFS */
+
+
+/* dump regular (and heap buffer, when HEAPBUFS are defined) error statistics */
+int dump_buf_estats (void * pio);
+
+/* statistics data structure that contains counters for various
+ * error conditions encountered when processing "regular" (little
+ * and big) and heap buffers (the latter only when HEAPBUFS is defined) */
+u_long memestats [MEMERR_NUM_STATS];
+
+#define PKTALLOC_TRUE 1
+#define PKTALLOC_FALSE 0
+
+/* FUNCTION: pk_init()
+ *
+ * Initialize the free queues for use by pk_alloc() and pk_free() for "regular" 
+ * (little and big) buffers.  
+ *
+ * This function also initializes heap buffer-related data structures, such
+ * as the total amount of heap memory allocated (for use in heap buffers), 
+ * the high watermark of the total amount of heap memory allocated (for use
+ * in heap buffers), and the heap's access type.  The last parameter is specific
+ * to the target system that this code is being ported to, and care must be
+ * taken to ensure that it is set correctly.
+ *
+ * If NPDEBUG is not defined, the user can use ALIGN_BUFS to force a
+ * specific alignment for a (little or big) buffer's start address.
+ * Note that the current implementation requires that ALIGN_BUFS be
+ * a power of 2.
+ * 
+ * INPUT: none
+ *
+ * OUTPUT: Returns 0 if OK; in the event of an error (such as when an allocation
+ * for a PACKET buffer or a data buffer fails, or if there is an inconsistency
+ * between (bigbufs + lilbufs) and MAXPACKETS) it returns -1. 
+ */
+
+int pk_init (void)
+{
+   PACKET packet;
+   unsigned i;
+   unsigned numpkts = bigbufs + lilbufs;
+   u_char align_req;
+   
+#ifdef ALIGN_BUFS
+   align_req = ALIGN_BUFS;
+#else
+   align_req = 0;
+#endif
+
+   for (i = 0; i < numpkts; i++)
+   {
+      packet = (PACKET)NB_ALLOC(sizeof(struct netbuf));
+      if (packet == NULL)
+         goto no_pkt_buf;
+
+#ifdef NPDEBUG
+      if (i >= MAXPACKETS)
+      {
+         dprintf("pk_init: bad define\n");
+         return -1;
+      }
+      pktlog[i] = packet;     /* save for debugging */
+#endif
+
+      packet->nb_tstamp = 0L;
+
+      if (i < bigbufs)
+      {
+#ifdef NPDEBUG
+         {
+            int j;
+
+            /* for DEBUG compiles, bracket the data area with special chars */
+            packet->nb_buff = (char *)BB_ALLOC(bigbufsiz+ALIGN_TYPE+1);
+            if (!(packet->nb_buff))
+               goto no_pkt_buf;
+
+            /* Add memory markers for sanity check */
+            for(j = 0; j < ALIGN_TYPE; j++)
+               *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */
+
+            *(packet->nb_buff + bigbufsiz + ALIGN_TYPE) = 'M';
+            packet->nb_buff += ALIGN_TYPE;   /* bump buf past MMs */
+         }
+#else
+         packet->nb_buff = (char *)BB_ALLOC(bigbufsiz + align_req);
+#ifdef ALIGN_BUFS
+         /* align start of buffer pointer to desired offset */
+         packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1)));
+#endif
+#endif
+         if (!(packet->nb_buff))
+            goto no_pkt_buf;
+         packet->nb_blen = bigbufsiz;
+         q_add(&bigfreeq, packet);        /* save it in big pkt free queue */
+      }
+      else     /* get a small buffer */
+      {
+#ifdef NPDEBUG
+         {
+            int j;
+
+            /* for DEBUG compiles, bracket the data area with special chars */
+            packet->nb_buff = (char *)LB_ALLOC(lilbufsiz+ALIGN_TYPE+1);
+            if (!(packet->nb_buff))
+               goto no_pkt_buf;
+
+            /* Add memory markers for sanity check */
+            for(j = 0; j < ALIGN_TYPE; j++)
+               *(packet->nb_buff + j) = 'M'; /* MMs at start of buf */
+
+            *(packet->nb_buff + lilbufsiz + ALIGN_TYPE) = 'M';
+            packet->nb_buff += ALIGN_TYPE;
+         }
+#else
+         packet->nb_buff = (char *)LB_ALLOC(lilbufsiz + align_req);
+#ifdef ALIGN_BUFS
+         /* align start of buffer pointer to desired offset */
+         packet->nb_buff += (ALIGN_BUFS - (((u_long) packet->nb_buff) & (ALIGN_BUFS - 1)));
+#endif
+#endif
+         if (!(packet->nb_buff))
+            goto no_pkt_buf;
+         packet->nb_blen = lilbufsiz;
+         q_add(&lilfreeq, packet);        /* save it in little free queue */
+      }
+   }
+   bigfreeq.q_min = bigbufs;
+   lilfreeq.q_min = lilbufs;
+
+   USE_ARG(align_req);
+
+#ifdef HEAPBUFS
+   /* initialize the counters that keep track of the total amount of memory 
+    * allocated from the heap and the corresponding high watermark */
+   heap_curr_mem = 0;
+   heap_curr_mem_hi_watermark = 0;
+   /* set the heap's access type to blocking */
+   heap_type = HEAP_ACCESS_BLOCKING;
+#endif
+
+   return 0;
+
+no_pkt_buf:
+#ifdef NPDEBUG
+   dprintf("Netinit: calloc failed getting buffer %d\n", i);
+#endif
+   return(-1);
+}
+
+/* FUNCTION: pk_alloc ()
+ *
+ * This function is invoked to allocate memory.  If the requested allocation
+ * is greater than bigbufsiz, this function will return 0 if HEAPBUFS is 
+ * not defined; however, if HEAPBUFS is defined, it will attempt to allocate
+ * a buffer from the heap via pk_alloc_heapbuf ().  After obtaining a regular
+ * little or big) or heap buffer that meets the caller's requirements, this
+ * function initializes various fields in the struct netbuf structure that 
+ * corresponds to the just allocated data buffer.  Note that all struct 
+ * netbuf fields are not initialized in this function; the remaining fields 
+ * are initialized in either pk_init () (for regular buffers) or in 
+ * pk_alloc_heapbuf () (for heap buffers).
+ * 
+ * INPUT: Length of requested allocation
+ *
+ * OUTPUT: 0 if the request cannot be satisfied, or a pointer to the struct
+ * netbuf structure that corresponds to the just allocated data buffer.
+ */
+
+PACKET pk_alloc(unsigned len)
+{
+   PACKET p;
+
+   if (len > bigbufsiz) /* caller wants oversize buffer? */
+   {
+#ifdef HEAPBUFS
+      if ((p = pk_alloc_heapbuf (len)) == NULL)
+         return NULL;
+#else
+      return(NULL);
+#endif
+   }
+   else
+   {
+      if ((len > lilbufsiz) || (lilfreeq.q_len == 0)) /* must use a big buffer */
+         p = (PACKET)getq(&bigfreeq);
+      else
+         p = (PACKET)getq(&lilfreeq);
+
+      if (!p)
+         return NULL;
+   }
+
+   p->nb_prot = p->nb_buff + MaxLnh;   /* point past biggest mac header */
+   p->nb_plen = 0;   /* no protocol data there yet */
+   p->net = NULL;
+
+#ifdef LINKED_PKTS
+   p->pk_next = p->pk_prev = NULL;
+#ifdef IP_V6
+   p->ip6_hdr = NULL;      /* No "Current" IPv6 header */
+   p->nexthop = NULL;      /* no next hop  */
+   p->nb_pmtu = 1240;      /* Set minimum IPv6 Path MTU */
+#endif   /* IP_V6 */
+#endif /* LINKED_PKTS */
+
+   p->inuse = 1;  /* initially buffer in use by 1 user */
+
+   /* note that 'type' and 'fhost' fields are not set in pk_alloc () */
+   return(p);
+}
+
+/* FUNCTION: pk_validate ()
+ *
+ * This function is invoked to validate the regular or heap buffer that 
+ * is being returned.  If the buffer being returned is a heap buffer,
+ * this function invokes pk_validate_heapbuf () to perform most of the
+ * validation (of the heap buffer); otherwise, it does the validation 
+ * itself.
+ * 
+ * One check that is common to both regular and heap buffers is a check
+ * for the consistency of the next pointer and inuse count.  Two other
+ * checks performed by this function for regular buffers include examining 
+ * the little and big buffer free queues to determine if the packet has 
+ * already been freed, and an examination of the guard bands (at the 
+ * beginning and end of the data buffer).
+ * 
+ * INPUT: Pointer to the struct netbuf structure that corresponds to the
+ * data buffer that is being freed.
+ *
+ * OUTPUT: 0 if the buffer being freed was successfully validated, or
+ * -1 if the validation failed.
+ */
+
+int pk_validate(PACKET pkt)   /* check if pk_free() can free the pkt */
+{
+   PACKET   p;
+#ifdef NPDEBUG
+   int      j;
+#endif
+
+   /* If packet link is non-zero, then this packet is
+    * part of a chain and deleted this packet would break
+    * the chain and cause memory leak for subsequent pkts.
+    * Note that heapbufs do not use the 'next' field at all.
+    */
+   if ((pkt->next) && (pkt->inuse >= 1))
+   {
+      INCR_SHARED_VAR (memestats, INCONSISTENT_LOCATION_ERR, 1);   
+      return -1;
+   }
+
+#ifdef HEAPBUFS
+   if (pkt->flags & PKF_HEAPBUF) /* check private heapbuf list queue */
+   {
+      return (pk_validate_heapbuf (pkt));
+   }
+   else  
+#endif /* HEAPBUFS */
+   {
+      /* check if the packet is already in a freeq */
+      if (pkt->nb_blen == bigbufsiz)  /* check in bigfreeq */
+      {
+         ENTER_CRIT_SECTION(&bigfreeq);
+         for (p=(PACKET)bigfreeq.q_head; p; p = p->next)
+            if (p == pkt)
+            {
+               dprintf("pk_free: buffer %p already in bigfreeq\n", pkt);
+               EXIT_CRIT_SECTION(&bigfreeq);
+               INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1);
+               return -1;
+            }
+         EXIT_CRIT_SECTION(&bigfreeq);
+      }
+      else if (pkt->nb_blen == lilbufsiz)  /* check in lilfreeq */
+      {
+         ENTER_CRIT_SECTION(&lilfreeq);
+         for (p=(PACKET)lilfreeq.q_head; p; p = p->next)
+            if (p == pkt)
+         {
+            dprintf("pk_free: buffer %p already in lilfreeq\n", pkt);
+            EXIT_CRIT_SECTION(&lilfreeq);
+            INCR_SHARED_VAR (memestats, MULTIPLE_FREE_ERR, 1);
+            return -1;
+         }
+         EXIT_CRIT_SECTION(&lilfreeq);
+      }
+      else
+      {
+         /* log an error */
+         INCR_SHARED_VAR (memestats, BAD_REGULAR_BUF_LEN_ERR, 1);
+         return -1;
+      }
+   }
+
+#ifdef NPDEBUG
+   /* check for corruption of memory markers (the guard bands are only
+    * present when NPDEBUG is defined) */
+   for (j = ALIGN_TYPE; j > 0; j--)
+   {
+      if (*(pkt->nb_buff - j) != 'M')
+      {
+         INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1);
+         return -1;
+      }
+   }
+   if (*(pkt->nb_buff + pkt->nb_blen) != 'M')
+   {
+      INCR_SHARED_VAR (memestats, GUARD_BAND_VIOLATED_ERR, 1);
+      return -1;
+   }
+#endif /* NPDEBUG */
+
+   return 0;
+}
+
+/* FUNCTION: pk_free ()
+ *
+ * This function is invoked to return a previously allocated buffer
+ * or a chain of previously allocated buffers (the latter only if 
+ * LINKED_PKTS is defined).
+ * 
+ * This function first invokes pk_validate () to validate the buffer
+ * being returned.  If the validation fails, this function either
+ * returns immediately (if it was processing the return of only one
+ * buffer) or continues with the next buffer in the chain (if it was
+ * processing a chain of buffers).
+ * 
+ * Each invocation of pk_free () will decrement a buffer's inuse count 
+ * by 1; when the count reaches 0, the buffer is ready to be returned
+ * back (to its free queue or the heap).
+ *
+ * After the validation is successful, this function invokes pk_free_-
+ * heapbuf () if the buffer is a heap buffer.  However, if the buffer
+ * being returned is a regular buffer, this function just adds the 
+ * buffer back to the appropriate (little or big) buffer free queue.
+ * 
+ * INPUT: Pointer to the struct netbuf structure that corresponds to the
+ * data buffer that is being freed.
+ *
+ * OUTPUT: None.
+ */
+
+void pk_free(PACKET pkt)   /* PACKET to place in free queue */
+{
+   int e;
+
+#ifdef LINKED_PKTS
+   /* If we support scatter/gather, then we have to loop through the
+    * whole chain of packets that were passed.
+    */
+   while(pkt)
+   {
+      PACKET pknext;
+      pknext = pkt->pk_next;
+#endif /* LINKED_PKTS */
+
+      /* validate the pkt before freeing */
+      e = pk_validate(pkt);
+      if (e)
+      {
+      /* pk_validate () has already recorded the type of error that has occured */
+#ifdef LINKED_PKTS
+         if (e == -1)
+         {
+            pkt = pknext;
+            continue; /* skip this pkt, examine the next pkt */
+         }
+#endif
+         return;
+      }
+      if (pkt->inuse-- > 1)   /* more than 1 owner? */
+         return;  /* packet was cloned, don't delete yet */
+
+#ifdef HEAPBUFS
+      if (pkt->flags & PKF_HEAPBUF)
+      {
+         pk_free_heapbuf (pkt);
+      }
+      else 
+#endif /* HEAPBUFS */
+      {
+         if (pkt->nb_blen == bigbufsiz)
+            q_add(&bigfreeq, (qp)pkt);
+         else if (pkt->nb_blen == lilbufsiz)
+            q_add(&lilfreeq, (qp)pkt);
+      }
+#ifdef LINKED_PKTS
+      pkt = pknext;
+   }
+#endif 
+
+}
+
+#ifdef LINKED_PKTS
+
+PACKET
+pk_prepend(PACKET pkt, int bigger)
+{
+   PACKET newpkt;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   newpkt = pk_alloc(bigger);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if(!newpkt)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return NULL;
+   }
+   newpkt->nb_prot = newpkt->nb_buff;  /* no MAC prepend */
+
+   /* set lengths of this buffer - no data yet */
+   newpkt->nb_plen = 0;       /* nothing in this buffer */
+   newpkt->nb_tlen = pkt->nb_tlen;  /* total chain length unchanged */
+
+   newpkt->pk_next = pkt;
+   newpkt->pk_prev = NULL;
+   /* ensure that the newly allocated buffer's PKF_HEAPBUF and 
+    * PKF_INTRUNSAFE flags aren't overwritten */
+   newpkt->flags |= (pkt->flags & (~(PKF_HEAPBUF | PKF_INTRUNSAFE)));
+   newpkt->net = pkt->net;
+   pkt->pk_prev = newpkt;     /* link new pkt */
+   return(newpkt);
+}
+
+PACKET
+pk_gather(PACKET pkt, int headerlen)
+{
+   PACKET   newpkt;
+   PACKET   tmppkt;
+   int      oldlen, newlen;
+   char *   cp;
+
+   oldlen = pkt->nb_tlen;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   newpkt = pk_alloc(oldlen + headerlen);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if(!newpkt)
+      return NULL;
+
+   newpkt->nb_prot = newpkt->nb_buff + headerlen;
+   /* ensure that the newly allocated buffer's PKF_HEAPBUF and 
+    * PKF_INTRUNSAFE flags aren't overwritten */
+   newpkt->flags |= (pkt->flags & (~(PKF_HEAPBUF | PKF_INTRUNSAFE)));
+   newpkt->net = pkt->net;
+   newpkt->pk_prev = newpkt->pk_next = NULL;
+
+   tmppkt = pkt;        /* save packet for pk_free call below */
+   newlen = 0;
+   cp = newpkt->nb_prot;
+   while(pkt)
+   {
+      MEMCPY(cp, pkt->nb_prot, pkt->nb_plen);
+      newlen += pkt->nb_plen;
+      cp += pkt->nb_plen;  /* bump pointer to data */
+      pkt = pkt->pk_next;  /* next packet in chain */
+   }
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(tmppkt);     /* free last packet in chain */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if(newlen != oldlen)    /* make sure length was right */
+      panic("pk_gather");
+
+   newpkt->nb_plen = newlen;
+   return newpkt;
+}
+
+#endif /* LINKED_PKTS */
+
+/* FUNCTION: pk_get_max_intrsafe_buf_len()
+ *
+ * This function is invoked to obtain the length of the largest interrupt-safe
+ * buffer that can be allocated in the system.
+ * 
+ * INPUT: None.
+ *
+ * OUTPUT: This function always returns the length of a big buffer (bigbufsiz).
+ */
+
+unsigned pk_get_max_intrsafe_buf_len(void)
+{
+   return bigbufsiz;
+}
+
+/* FUNCTION: pk_alloc_heapbuf ()
+ *
+ * This function is invoked by pk_alloc () to allocate a buffer from the heap.
+ * Note that all struct netbuf fields are not initialized in this function; 
+ * the remaining fields are initialized in pk_alloc ().
+ *
+ * This function first checks to make sure that the current allocation will
+ * not cause either the max individual heap allocation limit (MAX_INDIVIDUAL_-
+ * HEAP_ALLOC) or the total heap allocation limit (MAX_TOTAL_HEAP_ALLOC) to 
+ * be exceeded.  If both checks pass, it then attempts to allocate storage 
+ * for a struct netbuf, data buffer, and if the optional HEAPBUFS_DEBUG flag 
+ * is defined, for a private heapbuf list element (PHLE) entry (which is used 
+ * only for debug purposes).  If either of these allocations fail, this 
+ * function will return 0 (signifying a failure).
+ *
+ * If all of the constituent allocations are successful, this function then
+ * initializes various fields in the struct netbuf data structure (and the
+ * PHLE entry, if HEAPBUFS_DEBUG is defined), and returns a pointer to the 
+ * struct netbuf structure to its caller (which, in turn, passes it back to 
+ * its caller).
+ * 
+ * INPUT: Length of requested allocation
+ *
+ * OUTPUT: 0 if the request cannot be satisfied, or a pointer to the struct
+ * netbuf structure that corresponds to the just allocated data buffer.
+ */
+
+#ifdef HEAPBUFS
+PACKET pk_alloc_heapbuf (unsigned len)
+{
+   u_long increment;
+   u_char limit_exceeded = PKTALLOC_FALSE;
+   PACKET p;
+   u_char num_guard_bytes;
+#ifdef HEAPBUFS_DEBUG
+   PHLEP phlep;
+#endif
+#ifdef NPDEBUG
+   u_char i;
+   char * bufp;
+#endif
+
+   /* check to see if the caller is requesting more than the maximum 
+    * allowed individual allocation */
+   if (len > MAX_INDIVIDUAL_HEAP_ALLOC)
+   {
+      INCR_SHARED_VAR (hbufstats, TOOBIG_ALLOC_ERR, 1);
+      return(NULL);
+   }
+
+#ifdef NPDEBUG
+   num_guard_bytes = ALIGN_TYPE + 1;
+#else
+   num_guard_bytes = 0;
+#endif
+
+   /* check to make sure that this allocation will not cause us to
+    * exceed the maximum total allocation allowed from the heap.  First
+    * compute the increment. */
+   increment = sizeof (struct netbuf) + (len + num_guard_bytes);
+#ifdef HEAPBUFS_DEBUG
+   /* also account for the size of the debug structure if HEAPBUFS_DEBUG
+    * is enabled */
+   increment += sizeof (PHLE);
+#endif
+   ENTER_CRIT_SECTION(&heap_curr_mem);
+   heap_curr_mem += increment;
+   if (heap_curr_mem > MAX_TOTAL_HEAP_ALLOC)
+   {
+      limit_exceeded = PKTALLOC_TRUE;
+   }
+   EXIT_CRIT_SECTION(&heap_curr_mem);
+   if (limit_exceeded)
+   {
+      INCR_SHARED_VAR (hbufstats, LIMIT_EXCEEDED_ERR, 1);
+      DECR_SHARED_VAR (heap_curr_mem, increment);
+      return(NULL);
+   }
+
+   if (heap_type == HEAP_ACCESS_BLOCKING) UNLOCK_NET_RESOURCE (FREEQ_RESID);
+      
+   /* attempt to allocate a buffer for struct netbuf from the heap */
+   if ((p = ((struct netbuf *) HB_ALLOC (sizeof (struct netbuf)))) == 0)
+   {
+      /* restore state that existed prior to call into pk_alloc () */
+      if (heap_type == HEAP_ACCESS_BLOCKING) LOCK_NET_RESOURCE (FREEQ_RESID);
+      INCR_SHARED_VAR (hbufstats, NB_ALLOCFAIL_ERR, 1);
+      DECR_SHARED_VAR (heap_curr_mem, increment);
+      return(NULL);
+   }
+   /* attempt to allocate data buffer from heap */
+   if ((p->nb_buff = HB_ALLOC (len + num_guard_bytes)) == 0)
+   {
+      HB_FREE (p);
+      if (heap_type == HEAP_ACCESS_BLOCKING) LOCK_NET_RESOURCE (FREEQ_RESID);
+      INCR_SHARED_VAR (hbufstats, DB_ALLOCFAIL_ERR, 1);
+      DECR_SHARED_VAR (heap_curr_mem, increment);
+      return(NULL);
+   }
+#ifdef HEAPBUFS_DEBUG
+   /* obtain storage for private heapbuf list element to help keep track of the heapbuf allocation */
+   if ((phlep = ((PHLEP) HB_ALLOC (sizeof(PHLE)))) == 0)
+   {
+      HB_FREE (p->nb_buff);
+      HB_FREE (p);
+      if (heap_type == HEAP_ACCESS_BLOCKING) LOCK_NET_RESOURCE (FREEQ_RESID);
+      INCR_SHARED_VAR (hbufstats, PHLEB_ALLOCFAIL_ERR, 1);
+      DECR_SHARED_VAR (heap_curr_mem, increment);
+      return(NULL);
+   }
+   else
+   {
+      phlep->netbufp = p;
+      phlep->databufp = p->nb_buff;
+      phlep->length = len + num_guard_bytes;
+   }
+#endif
+
+   p->next = 0;
+   p->nb_tstamp = 0L;
+   /* mark buffer as being from heap and not interrupt-safe */
+   p->flags = (PKF_HEAPBUF | PKF_INTRUNSAFE);
+#ifdef NPDEBUG
+   /* Add memory markers at start and end of block (to help detect memory corruption) */
+   bufp = p->nb_buff;
+   for (i = 0; i < ALIGN_TYPE; i++)
+       *(bufp + i) = 'M';
+   *(bufp + len + ALIGN_TYPE) = 'M';
+   p->nb_buff += ALIGN_TYPE;   /* increment buffer's start pointer past guard band */
+#endif
+   p->nb_blen = len;
+
+   if (heap_type == HEAP_ACCESS_BLOCKING) LOCK_NET_RESOURCE (FREEQ_RESID);
+#ifdef HEAPBUFS_DEBUG
+   /* add element describing current allocation into the private heapbuf list.  This
+    * manipulation is already protected via ENTER_CRIT_SECTION () and EXIT_CRIT_SECTION
+    * macros. */
+   q_add(&phlq, (qp)phlep);
+#endif
+   /* increment the count of successfull allocations */
+   INCR_SHARED_VAR (hbufstats, HB_ALLOC_SUCC, 1);
+
+   /* update the high watermark if appropriate */
+   ENTER_CRIT_SECTION(&heap_curr_mem);
+   if (heap_curr_mem > heap_curr_mem_hi_watermark)
+   {
+      heap_curr_mem_hi_watermark = heap_curr_mem;
+   }
+   EXIT_CRIT_SECTION(&heap_curr_mem);
+
+   return p;
+}
+
+/* FUNCTION: pk_validate_heapbuf ()
+ *
+ * This function is invoked to validate the heap buffer that is being 
+ * returned.  It performs a few basic validations such as 
+ *
+ * - verifying that the length of the buffer is indeed greater than 
+ *   bigbufsiz (since in the current design, a request for a buffer 
+ *   less than bigbufsiz will always be allocated from the little or 
+ *   big buffer queues),
+ *
+ * - checking to see if a corresponding entry exists in the private
+ *   heapbuf list queue and if it does, that the length field in the
+ *   PHLE entry is consistent with the buffer's own length field (note
+ *   that the PHLE only exists if HEAPBUFS_DEBUG is defined), and
+ *
+ * - checking to ensure that the guard bands have not been overwritten.
+ * 
+ * INPUT: Pointer to the struct netbuf structure that corresponds to the
+ * data buffer that is being validated (prior to being freed).
+ *
+ * OUTPUT: 0 if the buffer being freed was successfully validated, or
+ * -1 if the validation failed.
+ */
+
+int pk_validate_heapbuf (PACKET pkt)
+{
+#ifdef HEAPBUFS_DEBUG
+   PHLEP phlep;
+#endif
+   u_char start_offset;
+   u_char num_guard_bytes;
+#ifdef NPDEBUG
+   int j;
+#endif
+
+#ifdef NPDEBUG
+   start_offset = ALIGN_TYPE;
+   num_guard_bytes = ALIGN_TYPE + 1;
+#else
+   start_offset = num_guard_bytes = 0;
+#endif
+
+   /* check for consistency with the nb_blen field */
+   if (pkt->nb_blen <= bigbufsiz)  
+   {
+      INCR_SHARED_VAR (hbufstats, INCONSISTENT_HBUF_LEN_ERR, 1);
+      return -1;
+   }
+
+#ifdef HEAPBUFS_DEBUG
+   ENTER_CRIT_SECTION(&phlq);
+   for (phlep=(PHLEP)phlq.q_head; phlep; phlep = phlep->next)
+   {
+       if ((phlep->netbufp == pkt) && (phlep->databufp == (pkt->nb_buff - start_offset)))
+       {
+          /* found a matching entry; perform consistency check */
+          if (phlep->length != (pkt->nb_blen + num_guard_bytes))
+          {
+             EXIT_CRIT_SECTION(&phlq);
+             INCR_SHARED_VAR (hbufstats, INCONSISTENT_HBUF_LEN_ERR, 1);
+             return -1;
+          }
+          else
+             break;
+       }
+   }
+   EXIT_CRIT_SECTION(&phlq);
+
+   if (phlep == 0)
+   {
+      /* since we don't have a record of this allocation in the private heapbuf, 
+       * list return an error */
+      INCR_SHARED_VAR (hbufstats, NO_PHLE_ERR, 1);
+      return -1;
+   }
+#endif /* HEAPBUFS_DEBUG */
+
+#ifdef NPDEBUG
+   /* check for corruption of memory markers (the guard bands are only
+    * present when NPDEBUG is defined) */
+   for (j = ALIGN_TYPE; j > 0; j--)
+   {
+      if (*(pkt->nb_buff - j) != 'M')
+      {
+         INCR_SHARED_VAR (hbufstats, HB_GUARD_BAND_VIOLATED_ERR, 1);
+         return -1;
+      }
+   }
+   if (*(pkt->nb_buff + pkt->nb_blen) != 'M')
+   {
+      INCR_SHARED_VAR (hbufstats, HB_GUARD_BAND_VIOLATED_ERR, 1);
+      return -1;
+   }
+#endif /* NPDEBUG */
+
+   /* packet has passed the validation checks */
+   return 0;
+}
+
+/* FUNCTION: pk_free_heapbuf ()
+ *
+ * This function is invoked to return a previously allocated heap 
+ * buffer.  The buffer being returned has already been validated
+ * (via pk_validate_heapbuf ()).
+ * 
+ * If HEAPBUFS_DEBUG is defined, this function first attempts to
+ * locate and delete the matching PHLE entry from the PHL queue.
+ * This function then returns the storage for the struct netbuf,
+ * data buffer, and (if HEAPBUFS_DEBUG is defined) PHLE back to
+ * the heap.  After the deallocation is complete, it updates the
+ * counter that keep track of the total heap memory useage.
+ * 
+ * INPUT: Pointer to the struct netbuf structure that corresponds 
+ * to the data buffer that is being freed.
+ *
+ * OUTPUT: None.  Even if this function fails to find a PHLE entry 
+ * that corresponds to the buffer that is being freed, it returns 
+ * silently after incrementing the corresponding error counter.
+ */
+
+void pk_free_heapbuf (PACKET pkt)
+{
+   u_char start_offset;
+   u_char num_guard_bytes;
+   char * bufp;
+#ifdef HEAPBUFS_DEBUG
+   PHLEP phlep;
+#endif
+   u_long len;
+   u_long decrement;
+
+#ifdef NPDEBUG
+   start_offset = ALIGN_TYPE;
+   num_guard_bytes = ALIGN_TYPE + 1;
+#else
+   start_offset = num_guard_bytes = 0;
+#endif
+
+   bufp = pkt->nb_buff - start_offset;
+   len = pkt->nb_blen + num_guard_bytes;
+#ifdef HEAPBUFS_DEBUG
+   /* update private heapbuf list - remove element */
+   ENTER_CRIT_SECTION(&phlq);
+   for (phlep=(PHLEP)phlq.q_head; phlep; phlep = phlep->next)
+   { 
+      if ((phlep->netbufp == pkt) && (phlep->databufp == bufp))
+      {
+         /* found a matching entry; remove it... */
+         break;
+      }
+   }
+   EXIT_CRIT_SECTION(&phlq);
+
+   /* did we find the private heapbuf list entry corresponding to this allocation? */
+   if (phlep == 0)
+   {
+      /* No; we were able to validate this PACKET earlier, 
+       * but the corresponding PHL entry has now disappeared! */
+      INCR_SHARED_VAR (hbufstats, NO_PHLE_ERR, 1);
+      return;
+   }
+   else
+   {
+      /* delete PHLE entry from its queue.  This deletion is protected via 
+       * ENTER_CRIT_SECTION () and EXIT_CRIT_SECTION () macros. */
+      qdel(&phlq, phlep);
+   }
+#endif /* HEAPBUFS_DEBUG */
+
+   if (heap_type == HEAP_ACCESS_BLOCKING) UNLOCK_NET_RESOURCE (FREEQ_RESID);
+   
+   HB_FREE (pkt);
+   HB_FREE (bufp);
+#ifdef HEAPBUFS_DEBUG
+   HB_FREE (phlep);
+#endif /* HEAPBUFS_DEBUG */
+   
+   if (heap_type == HEAP_ACCESS_BLOCKING) LOCK_NET_RESOURCE (FREEQ_RESID);
+   /* decrement the global counter that is used to keep track of the total
+    * heap allocation */
+   decrement = sizeof (struct netbuf) + len;
+#ifdef HEAPBUFS_DEBUG
+   /* also account for the size of the debug structure if HEAPBUFS_DEBUG
+    * is enabled */
+   decrement += sizeof (PHLE);
+#endif
+   DECR_SHARED_VAR (heap_curr_mem, decrement);
+
+   return;
+}
+
+/* FUNCTION: dump_hbuf_stats ()
+ *
+ * This function prints out various error and non-error statistics
+ * related to heap buffers onto the system console.
+ * 
+ * INPUT: Pointer to I/O structure for console.
+ *
+ * OUTPUT: This function always returns 0.
+ */
+
+int dump_hbuf_stats (void * pio)
+{
+   u_long hb_local [HBUF_NUM_STATS];
+   u_long heap_curr_mem_local;
+   u_long heap_curr_mem_hi_watermark_local;
+#ifdef HEAPBUFS_DEBUG
+   PHLEP phlep;
+   u_short count = 0;
+   u_long max_alloc = 0;
+   u_long min_alloc = 0xFFFFFFFF;
+   u_long total_alloc = 0;
+#endif
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+
+   ENTER_CRIT_SECTION(&hbufstats);
+   MEMCPY (&hb_local, &hbufstats, sizeof(hbufstats));
+   EXIT_CRIT_SECTION(&hbufstats);
+   
+   ENTER_CRIT_SECTION(&heap_curr_mem);
+   heap_curr_mem_local = heap_curr_mem;
+   heap_curr_mem_hi_watermark_local = heap_curr_mem_hi_watermark;
+   EXIT_CRIT_SECTION(&heap_curr_mem);
+
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   ns_printf(pio, "Heap buffer error and other statistics:\n");
+   ns_printf(pio, "Current total allocation %lu, high watermark %lu\n",heap_curr_mem_local,heap_curr_mem_hi_watermark_local);
+   ns_printf(pio, "Successful allocations %lu, size netbuf %u, size PHLE %u\n",hb_local[HB_ALLOC_SUCC],sizeof(struct netbuf),sizeof(PHLE));
+   ns_printf(pio, "Bad request size failures %lu, Max heap allocation exceeded failures %lu\n",hb_local[TOOBIG_ALLOC_ERR],hb_local[LIMIT_EXCEEDED_ERR]);
+   ns_printf(pio, "netbuf allocation failures %lu, data buffer allocation failures %lu\n",hb_local[NB_ALLOCFAIL_ERR],hb_local[DB_ALLOCFAIL_ERR]);
+   ns_printf(pio, "Inconsistent fields %lu, Guard band violations %lu\n",hb_local[INCONSISTENT_HBUF_LEN_ERR],hb_local[HB_GUARD_BAND_VIOLATED_ERR]);
+#ifdef HEAPBUFS_DEBUG
+   ns_printf(pio, "Private heapbuf list element allocation failures %lu, missing private heapbuf list element entry %lu\n",hb_local[PHLEB_ALLOCFAIL_ERR],hb_local[NO_PHLE_ERR]);
+   
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   ENTER_CRIT_SECTION(&phlq);
+   for (phlep=(PHLEP)phlq.q_head; phlep; phlep = phlep->next)
+   {
+      if (max_alloc < phlep->length) max_alloc = phlep->length;
+      if (min_alloc > phlep->length) min_alloc = phlep->length;
+
+      total_alloc += phlep->length;
+      ++count; 
+   }
+   EXIT_CRIT_SECTION(&phlq);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   if (count == 0)
+      ns_printf (pio, "No heap buffers currently allocated\n");
+   else
+      ns_printf(pio, "Number of heap buffers currently allocated %lu, min length %lu, max length %lu, total allocation %lu\n", \
+       count, min_alloc, max_alloc, total_alloc);
+#endif /* HEAPBUFS_DEBUG */
+
+   return 0;
+}
+#endif /* HEAPBUFS */
+
+/* FUNCTION: dump_buf_estats ()
+ *
+ * This function prints out various error statistics related to regular 
+ * and heap buffers onto the system console.  The first three error 
+ * counters (bad_regular_buf_len, guard_band_violated, and multiple_-
+ * free_err) are for regular buffers only.  The 'inconsistent_location' 
+ * field is a counter for both regular and heap buffers.
+ * 
+ * INPUT: Pointer to I/O structure for console.
+ *
+ * OUTPUT: This function always returns 0.
+ */
+
+int dump_buf_estats (void * pio)
+{
+   u_long mlocal [MEMERR_NUM_STATS];
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   ENTER_CRIT_SECTION(&memestats);
+   MEMCPY (&mlocal, &memestats, sizeof(memestats));
+   EXIT_CRIT_SECTION(&memestats);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+
+   ns_printf(pio, "Regular buffer error statistics:\n");
+   ns_printf(pio, "Bad buffer length %lu, Guard band violations %lu\n",mlocal[BAD_REGULAR_BUF_LEN_ERR],mlocal[GUARD_BAND_VIOLATED_ERR]);
+   ns_printf(pio, "Multiple frees %lu, Inconsistent location %lu\n",mlocal[MULTIPLE_FREE_ERR],mlocal[INCONSISTENT_LOCATION_ERR]);
+
+   return 0;
+}
+
+
+/* end of file pktalloc.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/q.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/q.c
new file mode 100644
index 0000000..7aeb432
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/q.c
@@ -0,0 +1,178 @@
+/*
+ * FILENAME: q.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Simple queuing system for internal use by the stack.
+ * All other general-purpose queue manipulation routines are macros 
+ * defined in "q.h". 10/18/90 - Added interrupt protection to all 
+ * routines -JB- 9/19/93 - Modified for Browser -JB- 
+ *
+ * 
+ * MODULE: INET
+ *
+ * ROUTINES: getq(), putq(), qdel(),  *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1993 by NetPort Software  */
+/*  Copyright 1986 by Carnegie Mellon  */
+/*  Copyright 1984 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "q.h"
+
+/* If the build is not using LOCKNET checking then define the macro away */
+
+#ifndef LOCKNET_CHECKING
+#define LOCKNET_CHECK(q)      /* define away */
+#endif
+
+/* Optional macro to dtrap if queue is corrupted. It tests that the queue 
+ * head & item count are either both set to zero(NULL), or neither is zero.
+ * It also checks the length of the queue with the number of elements
+ * actually present.
+ */
+
+#ifdef QUEUE_CHECKING
+extern void panic(char * msg);
+
+#define QUEUE_CHECK(q) \
+   {                                                    \
+      q_elt temp=q->q_head;                             \
+      int len=0;                                        \
+      if(((q->q_head != NULL) && (q->q_len == 0)) ||    \
+         ((q->q_head == NULL) && (q->q_len != 0)))      \
+            panic("q");                                 \
+      while (temp)                                      \
+      {                                                 \
+         len++;                                         \
+         temp=temp->qe_next;                            \
+      }                                                 \
+      if (len != q->q_len)                              \
+      {                                                 \
+         dtrap();                                       \
+      }                                                 \
+   }
+
+#else
+#define QUEUE_CHECK(q)      /* define away */
+#endif
+
+/* FUNCTION: getq()
+ *
+ * Dequeue and return the first element of the specified queue.  
+ *
+ * PARAM1: queue * q
+ *
+ * RETURNS: pointer to the first element if any, or 0 if the queue is empty.
+ */
+
+void*
+getq(queue * q)
+{
+   q_elt   temp;        /* temp for result */
+
+
+   ENTER_CRIT_SECTION(q);     /* shut off ints, save old state */   
+
+   LOCKNET_CHECK(q);          /* make sure queue is protected */
+
+   if ((temp = q->q_head) == 0)  /* queue empty? */
+   {
+      EXIT_CRIT_SECTION(q);
+      return (0);             /* yes, show none */
+   }
+
+   q->q_head = temp->qe_next; /* else unlink */
+   temp->qe_next = 0;         /* avoid dangling pointers */
+   if (q->q_head == 0)        /* queue empty? */
+      q->q_tail = 0;          /* yes, update tail pointer too */
+   q->q_len--;                /* update queue length */
+   if (q->q_len < q->q_min)
+      q->q_min = q->q_len;
+
+   QUEUE_CHECK(q);         /* make sure queue is not corrupted */
+
+   EXIT_CRIT_SECTION(q);   /* restore caller's int state */
+
+   return ((void*)temp);
+}
+
+
+/* FUNCTION: putq()
+ *
+ * q_add(que, item) - Adds an item to tail of queue. 
+ *
+ * 
+ * PARAM1: queue * q - queue to add item to
+ * PARAM2: void * elt - item to add
+ *
+ * RETURNS: void
+ */
+
+void
+putq(
+   queue   *   q,       /* the queue */
+   void *   elt)        /* element to delete */
+{
+   ENTER_CRIT_SECTION(q);
+   LOCKNET_CHECK(q);       /* make sure queue is protected */
+   q_addt(q, (qp)elt);     /* use macro to do work */
+   QUEUE_CHECK(q);         /* make sure queue is not corrupted */
+   EXIT_CRIT_SECTION(q);   /* restore int state */
+}
+
+/* FUNCTION: qdel()
+ *
+ * delete an item from the midst of a queue. Fix the head & tail and 
+ * all counters. 
+ *
+ * 
+ * PARAM1: queue * q
+ * PARAM2: void * elt
+ *
+ * RETURNS: Return pointer to queue member if found, else NULL. 
+ */
+
+qp
+qdel(queue * q, void * elt)
+{
+   qp qptr;
+   qp qlast;
+
+   /* search queue for element passed */
+   ENTER_CRIT_SECTION(q);
+   qptr = q->q_head;
+   qlast = NULL;
+   while (qptr)
+   {
+      if (qptr == (qp)elt)
+      {
+         /* found our item; dequeue it */
+         if (qlast)
+            qlast->qe_next = qptr->qe_next;
+         else     /* item was at head of queqe */
+            q->q_head = qptr->qe_next;
+
+         /* fix queue tail pointer if needed */
+         if (q->q_tail == (qp)elt)
+            q->q_tail = qlast;
+
+         /* fix queue counters */
+         q->q_len--;
+         if (q->q_len < q->q_min)
+            q->q_min = q->q_len;
+         EXIT_CRIT_SECTION(q);   /* restore int state */
+         return (qp)elt;   /* success exit point */
+      }
+      qlast = qptr;
+      qptr = qptr->qe_next;
+   }
+   EXIT_CRIT_SECTION(q);   /* restore int state */
+   return NULL;   /* item not found in queue */
+}
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.c
new file mode 100644
index 0000000..99fb8fb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.c
@@ -0,0 +1,199 @@
+/*
+ * FILENAME: slip.c
+ *
+ * Copyright 1997 - 2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Slip support for 
+ * frame oriented UARTS such as Motorola MC68302 UART. This should 
+ * work on any frame-oriented UART system with only minor 
+ * modifications.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: slipstrip(), slipstuff(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1994, 1995 by NetPort Software */
+
+#include "ipport.h"
+
+#ifdef USE_SLIP   /* whole file can be ifdeffed out */
+
+#include "slip.h"
+#include "slipport.h"
+
+u_char   slipbuf[SLIPBUFSIZ];
+
+
+
+/* FUNCTION: slipstrip()
+ *
+ * slipstrip() - Take a received block of bytes (a frame) and strip 
+ * out the slip escape characters. This is for UARTs which can be 
+ * programmed to interupt only on receipt of a pre-framed block of 
+ * bytes. This logic assumes all frames are a single slip frame. This 
+ * routine scans the passed buffer and does the reverse byte-stuffing 
+ * to convert the SLIP frame into a normal IP frame, ready to be 
+ * passed to the IP entry point - ip_rcv() on the NetPort stack. 
+ * Caller may want to verify the first byte in the buffer is the 
+ * first byte of a valid IP packet before passing to IP. Returns a 
+ * pointer to start of stripped frame, usually 1 byte after the 
+ * pointer passed. also returns the new length in the length variable 
+ * passed. 
+ *
+ * 
+ * PARAM1: u_char * bytes
+ * PARAM2: unsigned * buflen
+ *
+ * RETURNS: Returns NULL if a problem with the frame was detected. 
+ */
+
+char *   
+slipstrip(u_char * bytes, unsigned * buflen)
+{
+   char *   newhead; /* new start of packet */
+   u_char * cp;      /* scratch pointer */
+   unsigned length = *buflen; /* scratch length */
+
+   cp = bytes;
+   newhead = (char*)cp;
+
+   /* this tests for an RFC recommended enhancement */
+   if (*cp == SL_END)   /* 1st char used to clear buffer? */
+   {
+      length--;
+      newhead++;  /* point past leading frame marker */
+      cp++;
+   }
+
+#ifdef FAST_SLIP
+   /* if there are no slip ESCAPE chars, take fast path: */
+   if (MEMCHR(cp, SL_ESC, length) == NULL)
+   {
+      *buflen = length - 1;   /* truncate END byte */
+      return(newhead);
+   }
+#endif   /* FAST_SLIP */
+
+   /* scan frame byte by byte for SLIP special chars */
+   while (length--)
+   {
+      switch (*cp)
+      {
+      case SL_END:   /* end of frame */
+         *buflen = cp - (u_char*)newhead;
+         return newhead;
+      case SL_ESC:   /* got a "stuffed" byte */
+         if (*(cp+1) == SL_ESC_ESC) /* stuffed an esc */
+         {
+            *cp = SL_ESC;
+            MEMMOVE(cp+1, cp+2, length);  /* move up rest of data */
+         }
+         else if(*(cp+1) == SL_ESC_END)   /* stuffed an end */
+         {
+            *cp = SL_END;
+            MEMMOVE(cp+1, cp+2, length);  /* move up rest of data */
+         }
+      break;
+         default:
+      break;
+      }
+      cp++;
+   }
+   return NULL;   /* got through whole length without an SL_END char */
+}
+
+/* FUNCTION: slipstuff()
+ *
+ * slipstuff(buf, len) - the inverse of slipstrip(). This accepts a 
+ * raw IP packet bound for the SLIP port and does the required byte 
+ * stuffing. It checks that the buffer passed is big enough for the 
+ * result, which will be several bytes larger than the frame passed. 
+ * If the FAST_SLIP compile option is used, it further assumes the 
+ * buffer passed has a byte prepended for an SL_END char. Returns 
+ * pointer to new packet if OK, usually 1 byte less than the buffer 
+ * passed. datalen has new number of bytes in the packet if OK. 
+ *  
+ * 
+ * PARAM1: u_char * buf
+ * PARAM2: unsigned * datalen
+ * PARAM3: unsigned buflen
+ *
+ * RETURNS: Returns NULL if the passed buffer was not big enough.
+ */
+
+char *   
+slipstuff(u_char * buf, unsigned * datalen, unsigned buflen)
+{
+   u_char * inbuf;
+   u_char * outbuf;
+   unsigned newlength;
+   unsigned dlength;    /* scratch length holder */
+
+   dlength = *datalen;
+
+#ifdef FAST_SLIP
+   /* if there are no slip ESCAPE chars, take fast path: */
+   if (MEMCHR(buf, SL_ESC, dlength) == NULL)
+   {
+      if (MEMCHR(buf, SL_END, dlength) == NULL)
+      {
+         *(buf + dlength) = SL_END; /* new END char at back */
+         buf--;
+         *buf = SL_END; /* prepend END byte at front */
+         *datalen += 2; /* adjust return length for 2 added bytes */
+         return (char*)buf;
+      }
+   }
+#endif   /* FAST_SLIP */
+
+   MEMCPY(slipbuf, buf, dlength);      /* make a copy of buffer */
+   inbuf = slipbuf;
+   *buf = SL_END;    /* start packet with an END char, per RFC 1055 */
+   outbuf = buf+1;
+   newlength = 1 + dlength;
+
+   while (dlength--)
+   {
+      switch (*inbuf)
+      {
+      case SL_END:   /* replace "END" chars with ESC_ENDs */
+         *outbuf++ = SL_ESC;
+         *outbuf++ = SL_ESC_END;
+         newlength += 1;
+      break;
+      case SL_ESC:   /* replace imbedded escapes with ESC_ESCs */
+         *outbuf++ = SL_ESC;
+         *outbuf++ = SL_ESC_ESC;
+         newlength += 1;
+      break;
+         default:    /* not a special char, just move it. */
+         *outbuf++ = *inbuf;  /* inbuf is bumped below */
+      }
+      inbuf++;
+
+      /* make sure we don't overwrite end of buffer */
+      if (newlength > (buflen - (SLIPHDR_SIZE + SLIPHDR_BIAS + 1)))
+      {
+#ifdef NPDEBUG
+         dprintf("slipstuff overflow: %d\r\n", newlength);
+#endif
+         return NULL;
+      }
+   }
+   /* now add the END char to end */
+   *outbuf = SL_END;
+   newlength++;
+
+   *datalen = newlength;   /* return length of "stuffed" packet */
+   return (char*)buf;      /* return pointer to packet */
+}
+
+#endif   /* USE_SLIP */
+/* end of file slip.c */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.h b/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.h
new file mode 100644
index 0000000..2bfcc31
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/slip.h
@@ -0,0 +1,80 @@
+/*
+ * FILENAME: slip.h
+ *
+ * Copyright 1997 - 2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Slip support
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* Portions Copyright 1994, 1995 by NetPort Software */
+
+#ifndef _SLIP_H_
+#define  _SLIP_H_
+
+#include "comline.h"
+
+/* standard defines. These are decimal versions of the 
+values given in octal in the slip RFC. */
+#define  SL_ESC         219
+#define  SL_END         192
+#define  SL_ESC_END     220
+#define  SL_ESC_ESC     221
+
+/* MAX size of SLIP packet. See RFC before modifying */
+#define  SLIPSIZ        1006
+
+/* MAX size of SLIP Buffer. This has to accomodate 1006 bytes excluding
+ * the ESCAPE characters. So assuming the 1006 frame required by the RFC
+ * is full of escape characters then the min Buffer Size to guarantee
+ * reception and transmission would be 2012 bytes. However just for the
+ * sake of rounding off 2048 has been selected.
+ */
+#define  SLIPBUFSIZ     2048
+
+extern   u_char   slipbuf[SLIPBUFSIZ];
+extern   u_char   slipoutbuf[SLIPBUFSIZ];
+extern   u_char   slipinbuf[SLIPBUFSIZ];
+
+#define  SLIPHDR_SIZE   1
+
+/* Set this is to 3 to force alignment of pkt->nb_prot on a 4 byte
+ * boundary so that IP and TCP headers meet alignment requriements
+ * of architectures such as ARM, NEC, etc.
+ *
+ * To force alignment on ARM, NEC, etc. set SLIPHDR_BIAS to 3.
+ */
+#ifndef SLIPHDR_BIAS
+#define SLIPHDR_BIAS    3
+#endif
+
+struct slip_errors
+{
+   unsigned    serr_noends;         /* didn't find SL_END where expected */
+   unsigned    serr_overflow;       /* frame overflowed buffer */
+   unsigned    serr_connect;        /* loer level connect failed */
+   unsigned    serr_nobuff;         /* buffer alloc failed */
+   unsigned    serr_noframe;        /* got char outside of SLIP frame */
+   unsigned    serr_iphdr;          /* SLIP data was not IP packet */
+   unsigned    serr_c0noise;        /* Line noise or Peer Bug introdues spurious 0xc0 */
+};
+
+/* slip internal utilites */
+char *   slipstrip(u_char * bytes, unsigned * length);
+char *   slipstuff(u_char * buf, unsigned * pkt_len, unsigned buf_len);
+
+/* slip byte & frame receive entry points */
+int   slip_rxframe(int line, u_char * buffer, unsigned length);
+int   slip_rxbyte(struct com_line * line, int byte);
+
+#define  SLIP_TEST_HEADER     1  /* this tests for an RFC recommended enhancement */
+
+#endif   /* _SLIP_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/slipif.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/slipif.c
new file mode 100644
index 0000000..42ef818
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/slipif.c
@@ -0,0 +1,494 @@
+/*
+ * FILENAME: slipif.c
+ *
+ * Copyright 1997 - 2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * SLIP driver for Netport demo package. Developed and 
+ * tested primarily on PC UART hardware. This should be compatable to 
+ * any byte-oriented UART. Frame oriented UARTS such as Motorola 
+ * MC68302 may by supported by using the call to ln_write() instead 
+ * of ln_putc().
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: prep_slip(), slip_pkt_send(), slip_rxbyte(), 
+ * ROUTINES: slip_rxframe(), slip_init(), slip_stats(), slip_reg_type(), 
+ * ROUTINES: slip_close(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1994, 1995 by NetPort Software 6/25/97 */
+
+#include "ipport.h"
+
+#ifdef USE_SLIP   /* whole file can be ifdeffed out */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "slip.h"
+
+#include "slipport.h"   /* slip "port" file - what usrt, etc */
+
+#ifdef NPDEBUG
+/* macro to sanity check device number */
+#define check_iface(ifc) \
+   if(nets[ifc]->n_mib->ifType != SLIP)   \
+   {  dtrap(); }
+#else
+#define  check_iface(if);
+#endif   /* NPDEBUG */
+
+/* declare the SLIP iface routines */
+int   slip_init(int iface);
+int   slip_reg_type(unshort type, struct net * netp);
+int   slip_pkt_send(PACKET netp);
+int   slip_close(int iface);
+void  slip_stats(void * pio,int iface);
+
+static char slipmac[6]= {'S','L', 'I', 'P', 'I', 'F'}; 
+
+int      slip_ifs =  1; /* default, may by overwritted before prep_slip() call */
+
+struct slip_errors   slip_error[_NSLIP];  /* error counters */
+
+/* Lookup tables to map iface to unit and unit to iface. */
+int      slip_unit_map[_NSLIP];
+int      slip_iface_map[_NSLIP];
+
+struct com_line   slip_lines[_NSLIP];
+int      slip_units  =  0; /* unit numbers */
+
+u_char   slipoutbuf[SLIPBUFSIZ];
+u_char   slipinbuf[SLIPBUFSIZ];
+
+/* FUNCTION: prep_slip()
+ *
+ * prep_slip() - This prepares the slip logic for calls to 
+ * slip_init() It should be called at init time before any other slip 
+ * calls are make, and also before any network activity starts. 
+ * Parameter passed in the index of the next available nets[] 
+ * structure. 
+ *
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS:  Returns index of next available iface after slip 
+ * interfaces.
+ */
+
+int
+prep_slip(int iface)
+{
+   int   i;
+   int   unit;
+
+   for (i = iface; i < (iface + _NSLIP); i++)
+   {
+      if (slip_units >= _NSLIP)  /* run out of line units? */
+         return (i); /* that's all we can do */
+
+      /* set up net interface routine pointers, MIB, etc, before trying to
+      init the net. */
+      nets[i]->n_mib->ifAdminStatus = 2;  /* status = down */
+      nets[i]->n_mib->ifOperStatus = 2;   /* will be set up on connect  */
+      nets[i]->n_mib->ifLastChange = cticks * (100/TPS);
+      nets[i]->n_mib->ifPhysAddress = (u_char*)&slipmac[0];
+      nets[i]->n_mib->ifType = SLIP;
+      nets[i]->n_mib->ifDescr = (u_char*)"SLIP";
+
+      /* set header and max frame lengths for SLIP including HDR + Bias */
+      nets[i]->n_mtu = SLIPSIZ + SLIPHDR_SIZE + SLIPHDR_BIAS ;
+
+      /* slip frame delimited size + alignment offset */
+      nets[i]->n_lnh = SLIPHDR_SIZE + SLIPHDR_BIAS;
+      nets[i]->n_hal = 0;                 /* hardware address length */
+
+      nets[i]->n_flags |= NF_NBPROT;      /* we set nb_prot fields in driver */
+
+      /* install our hardware driver routines */
+      nets[i]->n_init = slip_init;
+      nets[i]->pkt_send = slip_pkt_send;
+      nets[i]->raw_send = NULL;
+      nets[i]->n_close = slip_close;
+      nets[i]->n_stats = slip_stats;
+
+      /* set up slip line driver define in ipport.h */
+      unit = slip_units++; /* bump counter for next unit */
+      slip_lines[unit].ln_connect = SLIP_connect;
+      slip_lines[unit].ln_disconnect = SLIP_disconnect;
+      slip_lines[unit].ln_write = SLIP_write;
+      slip_lines[unit].ln_putc = SLIP_putc;
+      slip_lines[unit].ln_state = LN_INITIAL;
+      slip_lines[unit].ln_getc = slip_rxbyte;
+ 
+      slip_lines[unit].lower_type = SLIP;
+      slip_lines[unit].upper_unit = (void *)unit;
+
+      /* set up the unit <-> iface mappings */
+      slip_unit_map[iface] = unit;
+      slip_iface_map[unit] = iface;
+   }
+   return (i); /* return index of next iface */
+}
+
+
+/* FUNCTION: slip_pkt_send()
+ *
+ * slip_pkt_send() - this routine sends a passed IP frame on the slip 
+ * link indicated by netp. It's the struct net pkt_send routine for 
+ * slip. 
+ *
+ * 
+ * PARAM1: PACKET pkt
+ *
+ * RETURNS: 0 if no error detected, else ENP_ error code
+ */
+
+int
+slip_pkt_send(PACKET pkt)
+{
+   IFMIB mib;
+   char *   buffer;
+   unsigned length;
+   int   iface,   unit, e=0;  /* make sure e is set */
+
+   iface = net_num(pkt->net);
+   check_iface(iface);
+   unit = slip_unit_map[iface];
+
+   mib = nets[iface]->n_mib;
+   if (slip_lines[unit].ln_state != LN_CONNECTED)
+   {
+      mib->ifAdminStatus = 1;
+
+      e = slip_lines[unit].ln_connect(&slip_lines[unit]);
+      if (e)
+      {
+         dprintf("slip connect failed; %s error\n",
+          e==1?"temporary":"permanant");
+         slip_error[unit].serr_connect++; /* count slip errors */
+         return ENP_BAD_STATE;
+      }
+      mib->ifOperStatus = 1;
+   }
+   length = pkt->nb_plen;
+
+   /* copy pkt->nb_prot data into SLIP out buffer, so that we don't run over
+    * pkt buffer while stuffing escape characters.
+    */
+   MEMCPY(&slipoutbuf[SLIPHDR_SIZE + SLIPHDR_BIAS], pkt->nb_prot, pkt->nb_plen);
+
+   buffer = slipstuff((u_char*)&slipoutbuf[SLIPHDR_SIZE + SLIPHDR_BIAS], &length, SLIPBUFSIZ);
+   if (buffer == NULL)
+   {
+      slip_error[unit].serr_overflow++;   /* count slip errors */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_NOBUFFER;
+   }
+
+   /* if line driver has a "write" command use it, else send bytes */
+   if (slip_lines[unit].ln_write)
+      e = slip_lines[unit].ln_write(&slip_lines[unit], pkt);    /* to frame-oriented UART hardware */
+   else
+   {
+      while (length--)
+         if ((e = slip_lines[unit].ln_putc(&slip_lines[unit], (int)(*buffer++))) != 0)
+      break;
+   }
+
+   /* maintain mib xmit stats */
+   if (e)   /* line send failed */
+      mib->ifOutErrors++;
+   else
+   {
+      mib->ifOutNUcastPkts++;
+      mib->ifOutOctets += length;
+   }
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(pkt);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   return 0;
+}
+
+
+
+/* FUNCTION: slip_rxbyte()
+ *
+ * slip_rxbyte() - pass received UART bytes to slip logic. It is 
+ * generally OK to call this from the UART ISR, although you may need 
+ * to add code somewhere to wake to packet demux task. Returns 0 if 
+ * ok, or -1 if buffer overrun. 
+ *
+ * 
+ * PARAM1: int unit
+ * PARAM2: int byte
+ *
+ * RETURNS: 
+ */
+
+static unsigned sb_index = 0;
+static c0_noise = FALSE;
+
+int
+slip_rxbyte(struct com_line * line, int byte)
+{
+int unit;
+
+   unit = (int)line->upper_unit;
+
+   /* Try to check if c0 has us, caught in a trap ! */
+   if (sb_index == 0 && (c0_noise == TRUE)  && byte == SL_END)
+   {
+      c0_noise = FALSE;
+      return -1;
+   }
+
+   /* if buffer is empty, wait for flush */
+   if (sb_index == 0 && byte != SL_END)
+   {
+      slip_error[unit].serr_noframe++; /* count slip errors */
+      return 0;
+   }
+
+   /* check for buffer overflow */
+   if (sb_index >= SLIPBUFSIZ)
+   {
+      sb_index = 0;  /* flush buffer */
+      slip_rxframe(unit, slipinbuf, sb_index); /* try to recover frame */
+      slip_error[unit].serr_overflow++;   /* count slip errors */
+      return -1;
+   }
+
+   slipinbuf[sb_index++] = (u_char)byte;    /* put byte in buffer */
+
+   /* check for end of frame */
+   if ((byte == SL_END) && /* char is end marker? */
+       (sb_index > 1))      /* and data's in buffer? */
+   {
+      slip_rxframe(unit, slipinbuf, sb_index); /* pass frame to receiver */
+      sb_index = 0;  /* clear buffer */
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: slip_rxframe()
+ *
+ * slip_rxframe() - Process received UART frames. It is generally OK 
+ * to call this from the UART ISR, although you may need to add code 
+ * somewhere to wake to packet demux task. Returns 0 if ok, negative 
+ * error code 
+ *
+ * 
+ * PARAM1: int unit
+ * PARAM2: u_char * buffer
+ * PARAM3: unsigned length
+ *
+ * RETURNS: 
+ */
+
+int
+slip_rxframe(int unit, u_char * buffer, unsigned length)
+{
+   PACKET pkt; /* inet packet for incoming frame */
+   int   iface;
+   IFMIB mib;
+
+   iface = slip_iface_map[unit];
+   check_iface(iface);
+
+   /* get slip escape characters out of buffer */
+   buffer = (u_char*)slipstrip(buffer, &length);
+   if (buffer == NULL)
+   {
+      slip_error[unit].serr_noends++;  /* count slip errors */
+      return -1;
+   }
+
+   /* Try to detect a spurious 0xc0 byte that has been either incorrectly
+    * sent by a buggy PEER or has been caused by line noise. Such a spurious
+    * byte should result in a length 0 IP packet on the next frame.
+    */
+   if(length == 0)
+   {
+      c0_noise = TRUE;
+      slip_error[unit].serr_c0noise++;   /* count slip errors */
+      return -1;
+   }
+
+   /* test for IP packet type;  0x45 | 0x46 | 0x47 are OK */
+   if (*buffer < 0x045 || *buffer > 0x047)
+   {
+      slip_error[unit].serr_iphdr++;   /* count slip errors */
+      return -1;
+   }
+
+   mib = nets[iface]->n_mib;
+
+   /* fill in a packet for the received buffer */
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pkt = pk_alloc(length);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (!pkt)
+   {
+      slip_error[unit].serr_nobuff++;  /* count slip errors */
+      mib->ifInDiscards++;
+      return ENP_RESOURCE;
+   }
+
+   /* fill in packet fields and give packet to upper layer */
+
+   /* point to start of IP header */
+   pkt->nb_prot = pkt->nb_buff + SLIPHDR_SIZE + SLIPHDR_BIAS;
+
+   MEMCPY(pkt->nb_prot, buffer, length);  /* copy in SLIP packet */
+   *pkt->nb_buff = 0;                     /* so broadcast stats are OK */
+   pkt->nb_plen = length;
+   pkt->net = nets[iface];
+   pkt->type = IPTP;                      /* packet verified as IP above */
+   pkt->nb_tstamp = cticks;
+
+   mib->ifInOctets += length;
+
+   /* queue the packet in rcvdq */
+   LOCK_NET_RESOURCE(RXQ_RESID);
+   putq(&rcvdq, (q_elt)pkt);
+   UNLOCK_NET_RESOURCE(RXQ_RESID);
+
+   /* Most ports should now wake the packet demuxer task */
+   SignalPktDemux();
+
+   return 0;   /* OK return */
+}
+
+
+
+/* FUNCTION: slip_init()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 0 if OK, else ENP error code.
+ */
+
+int
+slip_init(int iface)
+{
+IFMIB mib;
+int   unit, e = 0;  /* make sure e is set */
+
+   check_iface(iface);
+   unit = slip_unit_map[iface];
+
+   mib = nets[iface]->n_mib;
+
+   if (slip_lines[unit].ln_state != LN_CONNECTED)
+   {
+      mib->ifAdminStatus = 1;
+
+      e = slip_lines[unit].ln_connect(&slip_lines[unit]);
+      if (e)
+      {
+         dprintf("slip connect failed; %s error\n",
+          e==1?"temporary":"permanant");
+         slip_error[unit].serr_connect++; /* count slip errors */
+         return ENP_BAD_STATE;
+      }
+      mib->ifOperStatus = 1;
+   }
+
+   return 0;
+}
+
+#ifdef NET_STATS
+
+/* FUNCTION: slip_stats()
+ *
+ * slip_stats) - the nets[] stats routine for SLIP
+ *
+ * 
+ * PARAM1: void * pio
+ * PARAM2: int iface
+ *
+ * RETURNS: void
+ */
+
+void
+slip_stats(void * pio,int iface)
+{
+   int   unit  =  slip_unit_map[iface];
+
+   ns_printf(pio,"SLIP interface: \n");
+   ns_printf(pio,"last baud: %ld \n", slip_lines[unit].ln_speed );
+
+   ns_printf(pio,"state: line %s, Admin %s, Oper %s\n", 
+    (slip_lines[unit].ln_state == LN_CONNECTED)?"UP":"DOWN",
+    (nets[iface]->n_mib->ifAdminStatus == 1)?"UP":"DOWN",
+    (nets[iface]->n_mib->ifOperStatus == 1)?"UP":"DOWN");
+
+   ns_printf(pio,"missing END byte:   %u\n", slip_error[unit].serr_noends);
+   ns_printf(pio,"overflowed buffer:  %u\n", slip_error[unit].serr_overflow);
+   ns_printf(pio,"connects failed:    %u\n", slip_error[unit].serr_connect);
+   ns_printf(pio,"buffer alloc fail:  %u\n", slip_error[unit].serr_nobuff);
+   ns_printf(pio,"char outside frame: %u\n", slip_error[unit].serr_noframe);
+   ns_printf(pio,"data not IP packet: %u\n", slip_error[unit].serr_iphdr);
+   ns_printf(pio,"spurious c0 bytes : %u\n", slip_error[unit].serr_c0noise);
+
+   uart_stats(pio,unit);      /* dump UART stats */
+}
+
+#endif   /* NET_STATS */
+
+
+
+/* FUNCTION: slip_reg_type()
+ * 
+ * PARAM1: unshort type
+ * PARAM2: struct net * netp
+ *
+ * RETURNS: 
+ */
+
+int
+slip_reg_type(unshort type, struct net * netp)
+{
+   USE_ARG(type);
+   USE_ARG(netp);
+   return 0;
+}
+
+
+
+/* FUNCTION: slip_close()
+ * 
+ * PARAM1: int iface
+ *
+ * RETURNS: 
+ */
+
+int
+slip_close(int iface)
+{
+   IFMIB mib;
+   int   unit  =  slip_unit_map[iface];
+
+   slip_lines[unit].ln_disconnect(&slip_lines[unit]);
+
+   mib = nets[iface]->n_mib;
+   mib->ifAdminStatus = 2; /* set both SNMP MIB statuses to disabled */
+   mib->ifOperStatus = 2;
+
+   return 0;
+}
+
+#endif   /* USE_SLIP */
+
+/* end of file slipif.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/slipport.h b/FPGA_nios/hit_pat_bsp/iniche/src/net/slipport.h
new file mode 100644
index 0000000..ec09653
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/slipport.h
@@ -0,0 +1,62 @@
+/*
+ * FILENAME: slipport.h
+ *
+ * Copyright 1997 - 2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * SLIP port file for most demo builds. Maps serial line 
+ * calls to Comm port calls or to Hayes modem dialer.
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: no
+ */
+
+
+#include "ipport.h"
+
+#include UART_INCLUDE
+
+#define  _NSLIP   1  /* number of slip lines to support */
+
+#ifdef USE_MODEM
+#include "../modem/mdmport.h"
+#endif
+
+extern   struct slip_errors   slip_error[_NSLIP];
+
+extern   int slip_byte(int unit, int byte);  /* input from uart */
+
+#define  FAST_SLIP   1  /* optimize SLIP en/decoding w/ memchr() */
+
+#ifdef FAST_SLIP
+#define  MEMCHR(buf, chr,  len)  memchr(buf, chr,  len)
+#endif   /* FAST_SLIP */
+
+
+/* map slip line driver routine macros to actual routines */
+
+#define  SLIP_PCUART 1
+
+
+#ifdef SLIP_MODEM /* do slip over Hayes dialup modem */
+#define  SLIP_connect   modem_connect
+#define  SLIP_hangup    modem_hangup
+#define  SLIP_write     NULL
+#define  SLIP_putc      modem_putc
+#define  SLIP_state     modem_lstate
+#define  SLIP_speed     modem_speed
+#define  SLIP_init      modem_init
+#endif
+
+#ifdef SLIP_PCUART   /* do slip on raw PC uart */
+#define  SLIP_connect    ln_uconnect
+#define  SLIP_disconnect ln_udisconnect
+#define  SLIP_write      NULL
+#define  SLIP_putc       ln_uputc
+#define  SLIP_state      ln_ustate
+#define  SLIP_speed      ln_uspeed
+#define  SLIP_init       ln_uinit
+#endif
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/net/udp_open.c b/FPGA_nios/hit_pat_bsp/iniche/src/net/udp_open.c
new file mode 100644
index 0000000..cbd0f88
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/net/udp_open.c
@@ -0,0 +1,174 @@
+/*
+ * FILENAME: udp_open.c
+ *
+ * Copyright  2000-2007 By InterNiche Technologies Inc. All rights reserved
+ *
+ * UDP layer's open, close and support routines.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: udp_open(), udp_close(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1990 by NetPort Software  */
+/*  Copyright 1986 by Carnegie Mellon  */
+/*  Copyright 1984,1985 by the Massachusetts Institute of Technology  */
+
+
+#include "ipport.h"
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "udp.h"
+
+
+UDPCONN firstudp = NULL;
+
+/* FUNCTION: udp_open()
+ *
+ * udp_open() - Create a UDP connection and enter it in the demux 
+ * table. 
+ *
+ * 
+ * PARAM1: ip_addr fhost
+ * PARAM2: unshort fsock
+ * PARAM3: unshort lsock
+ * PARAM4: int (*handler)(PACKET, void * ); - callback
+ * PARAM5: void * data
+ *
+ * RETURNS:  Returns a pointer to the connections structure for use a a 
+ * handle if Success, else returns NULL.
+ */
+
+UDPCONN udp_open(
+   ip_addr  fhost,      /* foreign host, 0L for any */
+   unshort  fsock,      /* foreign socket, 0 for any */
+   unshort  lsock,      /* local socket */
+   int (*handler)(PACKET, void*),   /* rcv upcall */
+   void *   data)       /* random data, returned on upcalls to aid demuxing */
+{
+   UDPCONN con;
+   UDPCONN ocon;
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * cast 'data' to remove build warning
+ */
+#ifdef   NPDEBUG
+   if (NDEBUG & INFOMSG)
+      dprintf("udp_open: host %u.%u.%u.%u, lsock %u, fsock %u, foo %04x\n",
+    PUSH_IPADDR(fhost),lsock, fsock, (unsigned int)data);
+#endif
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   ocon = NULL;
+   for (con = firstudp; con; con = con->u_next)
+   {
+      ocon = con;       /* remember last con in list */
+
+#ifdef IP_V6
+      /* we only want to check UDP-over-IPv4 connections */
+      if (!(con->u_flags & UDPCF_V4))
+         continue;
+#endif
+
+      if (con->u_lport == lsock && con->u_fport == fsock &&
+          con->u_lhost == 0 && con->u_fhost == fhost)
+      {
+#ifdef   NPDEBUG
+         if (NDEBUG & (INFOMSG|PROTERR))
+            dprintf("UDP: Connection already exists.\n");
+#endif
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         return(NULL);
+      }
+   }
+
+   con = (UDPCONN)UC_ALLOC(sizeof(struct udp_conn));
+   if (con == 0)
+   {
+#ifdef   NPDEBUG
+      if (NDEBUG & INFOMSG)
+         dprintf("UDP: Couldn't allocate conn storage.\n");
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return(NULL);
+   }
+
+   if (ocon)   /* ocon is end of list */
+      ocon->u_next = con;  /* add new connection to end */
+   else  /* no list, start one */
+      firstudp = con;
+
+   con->u_next = 0;
+
+   con->u_lport = lsock;      /* fill in connection info */
+   con->u_fport = fsock;
+   con->u_lhost = 0;
+   con->u_fhost = fhost;
+   con->u_rcv   = handler;
+   con->u_data  = data;
+   con->u_flags = UDPCF_V4;
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return(con);
+}
+
+
+/* FUNCTION: udp_close()
+ *
+ * udp_close(UDPCONN) - close a udp connection - remove the 
+ * connection from udp's list of connections and deallocate it. 
+ *
+ * 
+ * PARAM1: UDPCONN con
+ *
+ * RETURNS: void
+ */
+
+void
+udp_close(UDPCONN con)
+{
+   UDPCONN pcon;
+   UDPCONN lcon;
+
+#ifdef NPDEBUG
+   if ((con == NULL) || (firstudp == NULL))
+   {
+      dtrap(); /* bad programming! */
+      return;
+   }
+#endif   /* NPDEBUG */
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   /* find connection in list and unlink it */
+   lcon = NULL;   /* clear ptr to last connection */
+   for (pcon = firstudp; pcon; pcon = pcon->u_next)
+   {
+      if (pcon == con)  /* found connection to delete */
+      break;
+      lcon = pcon;   /* remember last connection */
+   }
+
+   if (!pcon)
+   {
+      dtrap(); /* prog error - connenction not in list */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return;
+   }
+
+   if (lcon)   /* in con is not head of list */
+      lcon->u_next = con->u_next;   /* unlink */
+   else
+      firstudp = con->u_next; /* remove from head */
+
+   UC_FREE(con);  /* free memory for structure */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+}
+/* end of file udp_open.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/asm_cksum.S b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/asm_cksum.S
new file mode 100644
index 0000000..41a5fdf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/asm_cksum.S
@@ -0,0 +1,168 @@
+/* FILE: asm_cksum.c
+ *
+ * Internet checksum calculation for Altera NIOS-II processor.
+ * Refer to RFC 1071 for details.
+ */
+
+/* FUNCTION: asm_cksum
+ *
+ * Internet checksum calculation
+ *
+ * PARAM1: ptr	     r4, pointer to packet data (16-bit aligned)
+ * PARAM2: count     r5, number of unsigned halfwords
+ *
+ *  RETURN: cksum     r2, 16-bit checksum
+ */
+
+/*
+ * r2 = accum
+ * r4 = ptr
+ * r5 = count
+ * r6 = carry accum
+ * r7 = load
+ * r8 = carry
+ * r9 = odd
+ * r10 = temp
+ */
+
+      .text
+
+      .global	  asm_cksum
+
+asm_cksum:
+      mov   r2, zero		       /* accumulator = 0 */
+      ble   r5, zero, done	       /* count <= 0 ? */
+
+      mov   r6, zero		       /* carry accumulator */
+
+      andi  r3, r4, 2		       /* ptr 32-bit aligned? */
+      beq   r3, zero, asm1
+      ldhu  r2, (r4)		       /* no - process first 16-bits */
+      addi  r4, r4, 2
+      subi  r5, r5, 1
+/*
+ * adjust ptr by ((count/2) mod 16) * 4 bytes
+ * jump to location: loop0 - (count/2 mod 16) * 4 instructions
+ */
+asm1:
+      movia r11, loop0
+      andi  r9, r5, 1		       /* r9 = last halfword flag */
+      srai  r5, r5, 1		       /* count = number of words */
+      andi  r10, r5, 0xf	       /* modulo 16 */
+      slli  r10, r10, 2		       /*      * 4 bytes per word */
+      add   r4, r10, r4		       /* adjust ptr */
+      slli  r10, r10, 2		       /*      * 4 instructions per 4 bytes */
+      sub   r11, r11, r10
+      jmp   r11
+      
+loop:
+      addi  r4, r4, 64		       /* increment data pointer */
+
+      ldw   r7, -64(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -60(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -56(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -52(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -48(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -44(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -40(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -36(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -32(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -28(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -24(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -20(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -16(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -12(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -8(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+
+      ldw   r7, -4(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+loop0:
+      subi  r5, r5, 16
+      bge   r5, zero, loop
+/*
+ * process last halfword (if any)
+ */
+      beq   r9, zero, fold
+      ldhu  r7, 0(r4)
+      add   r2, r7, r2
+      cmpltu r8, r2, r7
+      add   r6, r8, r6
+      
+fold:
+      srli  r7, r2, 16
+      andi  r2, r2, 0xffff
+      add   r2, r7, r2		    /* add the upper and lower halfwords */
+      add   r2, r6, r2		    /* add the carries */
+/* the accumulator is 18 bits */
+      srli  r7, r2, 16
+      andi  r2, r2, 0xffff
+      add   r2, r7, r2		    /* add 2 carry bits to lower halfword */
+/* the accumulator is 17 bits */
+      srli  r7, r2, 16
+      andi  r2, r2, 0xffff
+      add   r2, r7, r2		    /* add carry to lower halfword */
+
+done:
+      ret			    		/* r2 = 16-bit checksum */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/brdutils.c b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/brdutils.c
new file mode 100644
index 0000000..3f6c46e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/brdutils.c
@@ -0,0 +1,241 @@
+/*
+ * FILENAME: brdutils.c
+ *
+ * Copyright 2004 InterNiche Technologies Inc. All rights reserved.
+ *
+ * Target Board utility functions for InterNiche TCP/IP.
+ * This one for the ALTERA Cyclone board with the ALTERA Nios2 Core running 
+ * with the uCOS-II RTOS.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * MODULE  : NIOS2GCC
+ * ROUTINES: dtrap(), clock_init(), clock_c(), kbhit() getch().
+ * PORTABLE: no
+ *
+ * 06/21/2004
+ * 
+ */
+
+#include "ipport.h"
+
+#include "fcntl.h"
+#include "unistd.h"
+#include "sys/alt_irq.h"
+
+#ifdef UCOS_II
+#include "includes.h"  /* Standard includes for uC/OS-II */
+#endif
+
+void dtrap(void);
+int  kbhit(void);
+int  getch(void);
+void clock_c(void);
+void clock_init(void);
+void cticks_hook(void);
+#ifdef USE_LCD
+extern void update_display(void);
+#endif
+
+int kb_last = EOF;
+
+void irq_Mask(void);
+void irq_Unmask(void);
+
+/* dtrap() - function to trap to debugger */
+void
+dtrap(void)
+{
+   printf("dtrap - needs breakpoint\n");
+}
+
+int
+kbhit()
+{
+   static int kbd_init = 0;
+   int   kb;
+   
+   if (!kbd_init)
+   {
+      /* we really should read the flags, OR in O_NONBLOCK, and write
+       * the flags back to STDIN, but the NIOS-II/HAL implementation
+       * will only let us modify O_NONBLOCK and O_APPEND, so we'll
+       * just write the new flag value.
+       */
+      if (fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK) != 0)
+      {
+         printf("F_SETFL failed.\n");
+         dtrap();
+      }
+      kbd_init = 1; 
+   }
+
+   /* we have to do a read to see if there is a character available.
+    * we save the character, if there was one, to be read later. */
+   if (kb_last == EOF)
+   {
+      kb = getchar();
+      if (kb < 0)       /* any error means no character present */
+         return (FALSE);
+         
+      /* there was a character, and we read it. */
+      kb_last = kb;
+   }
+
+   return (TRUE);
+}
+
+int 
+getch()
+{
+int chr;
+
+   if(kb_last != EOF)
+   {
+      chr = kb_last;
+      kb_last = EOF;
+   }
+   else
+      chr = getchar();
+
+   return chr;
+}
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add clock_init and clock_c as empty routines to support superloop
+ */
+#ifdef SUPERLOOP
+void clock_init(void)
+{
+   /* null */ ;
+}
+
+void clock_c(void)
+{
+   /* null */ ;
+}
+
+#else /* !SUPERLOOP */
+
+/*
+ * system clock : NO OP - start clock tick counting;
+ * called at init time.
+ * 
+ */
+int OS_TPS;
+int cticks_factor;
+int cticks_initialized = 0;
+
+void clock_init(void)
+{
+   OS_TPS = OS_TICKS_PER_SEC;
+   cticks_factor = 0;
+   cticks = 0;
+   cticks_initialized = 1;
+}
+
+/* undo effects of clock_init (i.e. restore ISR vector) 
+ * NO OP since using RTOS's timer.
+ */
+void clock_c(void)
+{
+   /* null */ ;
+}
+
+
+/* This function is called from the uCOS-II OSTimeTickHook() routine.
+ * Use the uCOS-II/Altera HAL BSP's timer and scale cticks as per TPS.
+ */
+
+void
+cticks_hook(void)
+{
+   if (cticks_initialized) 
+   {
+      cticks_factor += TPS;
+      if (cticks_factor >= OS_TPS)
+      {
+         cticks++;
+         cticks_factor -= OS_TPS;
+#ifdef USE_LCD
+         update_display();
+#endif
+      }
+   }
+}
+
+#endif /* SUPERLOOP */
+
+/* Level of Nesting in irq_Mask() and irq_Unmask() */
+int irq_level = 0;
+
+/* Latch on to Altera's NIOS2 BSP */
+static alt_irq_context cpu_statusreg;
+
+#ifdef NOT_DEF
+#define IRQ_PRINTF   1
+#endif
+
+/* Disable Interrupts */
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * The old implementation of the irq_Mask and irq_unMask functions
+ * was incorrect because it didn't implement nesting of the interrupts!
+ * The InterNiche handbook specification implies that nesting is
+ * something that is supported, and the code seems to need it as 
+ * well.
+ *
+ * From Section 2.2.3.1 on the NicheStack Handbook:
+ * "Note that it is not sufficient to simply disable interrupts in 
+ * ENTER_CRIT_SECTION() and enable them in EXIT_CRIT_SECTION()
+ * because calls to ENTER_CRIT_SECTION() can be nested."
+ */
+void
+irq_Mask(void)
+{
+   alt_irq_context  local_cpu_statusreg;
+
+   local_cpu_statusreg = alt_irq_disable_all();
+	
+   if (++irq_level == 1)
+   {
+      cpu_statusreg = local_cpu_statusreg;
+   }
+}
+
+
+/* Re-Enable Interrupts */
+void
+irq_Unmask(void)
+{
+   if (--irq_level == 0)
+   {
+      alt_irq_enable_all(cpu_statusreg);
+   }
+}
+
+
+#ifdef USE_PROFILER
+
+/* FUNCTION: get_ptick
+ * 
+ * Read the hig-resolution timer
+ * 
+ * PARAMS: none
+ * 
+ * RETURN: current high-res timer value
+ */
+u_long
+get_ptick(void)
+{
+   return (alt_nticks());
+}
+
+#endif  /* USE_PROFILER */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osport.h b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osport.h
new file mode 100644
index 0000000..41832da
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osport.h
@@ -0,0 +1,156 @@
+/* 
+ * File name : osport.h
+ *
+ * Map InterNiche tasking primitives to ChronOS or set up NicheTask.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * 06/21/2004
+ * 
+ */
+
+/* We don't guard osport.h with OSPORT_H on purpose -AK- */
+
+#ifndef osport_h
+#define osport_h
+
+#include "ipport.h"
+
+#ifdef UCOS_II
+#include "includes.h"
+#endif /* UCOS_II */
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "arp.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+#include "nvparms.h"
+#include "nvfsio.h"
+#include "menu.h"
+#include "app_ping.h"
+
+#include "task.h"
+
+// These definitions came in the standard port of the InterNiche sources
+// They are not used in the Nios II port
+#if 0
+
+#define  DEMO_STACK_SIZE      4096
+
+#define  NETHEAP_SIZE         0x30000
+
+/* task stack sizes */
+#define  NET_STACK_SIZE       4096
+#define  APP_STACK_SIZE       6144 /* 4096 */     /* default for applications */
+#define  CLOCK_STACK_SIZE     4096
+
+#define  IO_STACK_SIZE        2048
+#define  WEB_STACK_SIZE       APP_STACK_SIZE
+#define  FTP_STACK_SIZE       APP_STACK_SIZE
+#define  PING_STACK_SIZE      4096
+#define  TN_STACK_SIZE        APP_STACK_SIZE
+#define  TCP_ECHO_STACK_SIZE  APP_STACK_SIZE
+
+#endif
+
+// Note: These definitions below have moved into the ipport.h file
+#if 0
+
+#define  DEMO_STACK_SIZE      (4096+8192)
+
+#define  NETHEAP_SIZE         0x30000
+
+/* task stack sizes */
+#define  NET_STACK_SIZE       (4096+8192)
+#define  APP_STACK_SIZE       (6144+8192) /* 4096 */     /* default for applications */
+#define  CLOCK_STACK_SIZE     (4096+8192)
+
+#define  IO_STACK_SIZE        (2048+8192)
+#define  WEB_STACK_SIZE       (APP_STACK_SIZE+8192)
+#define  FTP_STACK_SIZE       APP_STACK_SIZE
+#define  PING_STACK_SIZE      (4096+8192)
+#define  TN_STACK_SIZE        APP_STACK_SIZE
+#define  TCP_ECHO_STACK_SIZE  APP_STACK_SIZE
+
+#endif
+
+#ifdef INICHE_TASKS
+#define TK_ENTRY(name)       int name(int parm)
+#define TK_ENTRY_PTR(name)   int(*name)(int)
+#define TK_OBJECT(name)      task * name
+#define TK_OBJECT_PTR(name)  task ** name
+#define TK_RETURN_ERROR()    return (-1)
+#define TK_RETURN_OK()       parm++; return (0)
+#define NET_PRIORITY         0     /* not used on tasks */
+#define MAIN_TASK_IS_NET     1     /* compiler main() is converted to net task */
+#define TK_NETMAINPARM       0     /* parameter to main/net task */
+#endif
+
+/* table with an entry for each internet task/thread. This is filled
+in the netmain.c, so it should have the same values in the same order 
+in all ports */
+
+struct inet_taskinfo {
+   TK_OBJECT_PTR(tk_ptr);  /* pointer to static task object */
+   char * name;            /* name of task */
+   TK_ENTRY_PTR(entry);    /* pointer to code to start task at */
+   int   priority;         /* priority of task */
+   int   stacksize;        /* size (bytes) of task's stack */
+   char* stackbase;        /* base of task's stack */
+};
+
+#ifdef ALT_INICHE
+extern void alt_iniche_init(void);
+#endif /* ALT_INICHE */
+
+int TK_NEWTASK(struct inet_taskinfo * nettask);
+
+extern char * pre_task_setup(void);
+extern char * post_task_setup(void);
+
+extern int netmain(void);
+extern TK_OBJECT(to_netmain);
+
+extern int num_net_tasks;
+extern struct inet_taskinfo nettasks[];
+
+extern void dtrap(void);
+
+/* UCOS_II pend/post */
+#undef TK_CRON_DIAGS
+#define  GLOBWAKE_SZ     20
+#define  GLOBWAKE_PURGE_DELT     (TPS * 2)
+ 
+struct wake_event
+{
+   void *wake_sem;
+   void *soc_event;        
+   char *name;
+};
+
+struct TCP_PendPost
+{
+   u_long   ctick;           /* time entry was added */
+   void     *soc_event;      /* wakeup event */	
+   OS_EVENT *semaphore;      /* semaphore to wait on */
+};
+ 
+
+
+#ifdef MINI_IP
+#define net_system_exit (FALSE)
+#else
+extern int net_system_exit;   /* TRUE if system is shutting down */
+#endif /* MINI_IP */
+
+extern int iniche_net_ready;
+
+#endif /* osport_h */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osportco.c b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osportco.c
new file mode 100644
index 0000000..2f44742
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/osportco.c
@@ -0,0 +1,481 @@
+/*
+ * FILENAME: osportco.c
+ *
+ * Copyright  2004 By InterNiche Technologies Inc. All rights reserved
+ *
+ * Code to map NicheTask "TK_" macros and other port routines
+ * to uCOS-II RTOS on ALTERA Cyclone board with the ALTERA Nios2 Core.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * MODULE  : Nios II
+ * PORTABLE: no
+ *
+ * 06/21/2004
+ * 10/21/2008 (skh)
+ *
+ */
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Rearranged ipport.h and includes.h, using UCOS_II to not compile the file
+ */
+#include "ipport.h"        /* from Interniche directory */
+#ifdef UCOS_II             /* Whole file is #ifdef'ed away if no uCOS-II */
+
+#include "includes.h"      /* from Nios2 uCOS-II directory */
+
+#include "os_cpu.h"
+
+#include "osport.h"
+
+#include "in_utils.h"
+#include "memwrap.h"
+
+extern OS_EVENT *mheap_sem_ptr;
+extern OS_EVENT *rcvdq_sem_ptr;
+#ifdef OS_PREEMPTIVE
+extern OS_EVENT *resid_semaphore[MAX_RESID+1];
+extern OS_EVENT *app_semaphore[MAX_SEMID+1];
+#endif
+#if OS_TASK_CREATE_EXT_EN > 0
+struct wake_event global_tcb_ext[OS_LOWEST_PRIO+1];
+#endif
+
+/* state of ints, saved by XXlock_net_res() */
+int   netq_intmask;
+
+extern int netmain(void);
+
+int old_mode;
+
+unsigned long cticks;
+
+#ifndef TCPWAKE_RTOS
+/*
+ * Q and Mutex used by tcp_sleep/wakeup
+ */
+struct TCP_PendPost global_TCPwakeup_set[GLOBWAKE_SZ];
+int global_TCPwakeup_setIndx;
+u_long tcp_sleep_count = 0;
+u_long tcp_wakeup_count = 0;
+#endif
+
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * This seems to be a sample main() program. We provide these
+ * in our (web server, simple socket serve) software examples,
+ * and generally allow you to write your own main. Disabling
+ */
+#ifndef ALT_INICHE
+
+INT8U app_priority = 13;    /* first/next priority to try for application */
+
+
+
+/* Define C code main entry point.  */
+
+int
+main(void)
+{
+   INT8U mute_err;
+   int priort;
+   int i;
+
+   iniche_net_ready = 0;
+   
+/* OSInit(); */
+   OSTimeSet(0);
+
+   /* create all of the various semaphores */
+   mheap_sem_ptr = OSSemCreate(1);      /* npalloc() heap */
+   if (!mheap_sem_ptr)
+      panic("mheap_sem_ptr create err");
+
+   rcvdq_sem_ptr = OSSemCreate(0);      /* RCVD queue "ready" */
+   if (!rcvdq_sem_ptr)
+      panic("rcvdq_sem_ptr create err"); 
+
+#ifdef OS_PREEMPTIVE
+   for (i = 0; i <= MAX_RESID; i++)
+   {
+      resid_semaphore[i] = OSSemCreate(1);
+      if (!resid_semaphore[i])
+         panic("resid_semaphore create err");  
+   }
+   for (i = 0; i <= MAX_SEMID; i++)
+   {
+      app_semaphore[i] = OSSemCreate(1);
+      if (!app_semaphore[i])
+         panic("app_semaphore create err");  
+   }
+#endif  /* OS_PREEMPTIVE */
+
+#ifndef TCPWAKE_RTOS
+   /* 
+    * clear global_TCPwakeup_set
+    */
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+   {
+      global_TCPwakeup_set[i].ctick = 0;
+      global_TCPwakeup_set[i].soc_event = NULL;
+      global_TCPwakeup_set[i].semaphore = OSSemCreate(0);
+      if (!global_TCPwakeup_set[i].semaphore)
+         panic("globwake_semaphore create err");  
+   }
+   global_TCPwakeup_setIndx = 0;
+
+#endif /* TCPWAKE_RTOS */
+
+   /* We have to lock scheduler while creating net tasks. Even though the RTOS
+    * technically running yet, the ISR hooks to change tasks don't know this.
+    * Since the UART uses interrupts heavly, we have to resort to this to
+    * get console output during net_init.
+    */
+   OSLockNesting++;
+   netmain();        /* Create net tasks */
+   OSLockNesting--;
+
+   dprintf("+++ uCOS init, app_priority = %d\n", app_priority);
+
+   OSStart();        /* Jump to uCOS-II - Start system; never returns */
+   panic("uCOS-II returned");
+
+   return 0;
+}
+
+
+u_char
+uCOS_self(void)
+{
+   /* Return uCOS currently running task ID */
+   return(OSTCBCur->OSTCBPrio);
+}
+#endif /* if not defined: ALT_INICHE */
+
+
+extern void irq_Mask(void);
+extern void irq_Unmask(void);
+
+void
+LOCK_NET_RESOURCE(int resid)
+{
+   INT8U error = 0;
+   int   errct = 0;
+
+   if ((0 <= resid) && (resid <= MAX_RESID))
+   {
+      do
+      {
+         OSSemPend(resid_semaphore[resid], 0, &error);
+         /* 
+          * Sometimes we get a "timeout" error even though we passed a zero
+          * to indicate we'll wait forever. When this happens, try again:
+          */
+         if ((error == 10) && (++errct > 1000))
+         {
+            panic("lock NET");   /* fatal */
+            return;
+         }
+      } while (error == 10);
+   }
+   else
+      dtrap();
+}
+
+void
+UNLOCK_NET_RESOURCE(int resid)
+{
+   INT8U error = 0;
+
+   if ((0 <= resid) && (resid <= MAX_RESID))
+   {
+      error = OSSemPost(resid_semaphore[resid]);
+      if (error != OS_NO_ERR)
+      {
+         panic("unlock NET");
+      }
+   }
+   else
+      dtrap();
+}
+
+
+/* 
+ * Altera Niche Stack Nios port modification:
+ * TK_NEWTASK was significantly modified to remove the automatic
+ * priority assignment scheme. A task created with TK_NEWTASK
+ * should have its priority assigned in the inet_taskinfo
+ * pointer passed in to TK_NEWTASK. Task priority and stack
+ * size assignments for various Interniche features are specified
+ * in ipport.h. For application tasks, you must assign your own.
+ */
+
+/*
+ * Here's the workaround to an unusual quirk of uCOS-II - It
+ * cannot have multiple tasks of the same priority. Networking systems
+ * are best done with a few threads which have equal priority and thus 
+ * ensure fair CPU sharing without convoluted priority balancing. This 
+ * means we have to guess a priority for each of our net tasks and then
+ * code tk_yield() to force a non-zero delay (one tick), to ensure that all
+ * the network tasks get a round-robin slot to do their thing. Of course
+ * we could alter the code's design to be optimized for a strictly
+ * prioritized RTOS, but that would penalize all the non-preemptive and
+ * non-prioritized systems we also support.
+ */
+
+extern TK_ENTRY(tk_netmain);        /* in netmain.c */
+extern long     netmain_wakes;
+
+#ifdef TK_STDIN_DEVICE
+extern TK_ENTRY(tk_keyboard);       /* in netmain.c */
+extern long     keyboard_wakes;
+#endif
+
+extern TK_ENTRY(tk_nettick);        /* in netmain.c */
+extern long     nettick_wakes;
+
+
+int
+TK_NEWTASK(struct inet_taskinfo * nettask)
+{
+   INT8U    error;
+   OS_STK * stack;
+
+   stack = (OS_STK*)npalloc(nettask->stacksize);
+   if(!stack)
+      panic("stack alloc");
+
+#if OS_TASK_CREATE_EXT_EN > 0
+   error = OSTaskCreateExt(
+      nettask->entry,
+      NULL,
+      stack + (nettask->stacksize/sizeof(OS_STK)) - 1,
+      nettask->priority,
+      nettask->priority,
+      stack, 
+      (INT32U)nettask->stacksize / sizeof(OS_STK),
+      NULL,
+      OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
+#else
+#ifndef TCPWAKE_RTOS
+#error  !TCPWAKE_RTOS requires OS_TASK_CREATE_EXT_EN
+#endif
+   error = OSTaskCreate(
+      (void (*)(void *)) nettask->entry,
+      NULL,
+      stack + (nettask->stacksize/sizeof(OS_STK)) - 1,
+      nettask->priority);
+#endif
+   /* If we go here, then there's another task using our priority */
+   /* Tell the user and exit with an error */
+   if (error == OS_PRIO_EXIST)
+   { 
+     char curr_task[OS_TASK_NAME_SIZE];
+     INT8U err;
+     OSTaskNameGet(nettask->priority, (INT8U*)curr_task, &err);
+     curr_task[OS_TASK_NAME_SIZE-1]=0;
+    
+     printf("Priority requested for task \"%s\" (Prio:%d) conflicts with "\
+            "already running task \"%s\" (Prio: %d)\n",
+             nettask->name, nettask->priority, curr_task, nettask->priority);
+             
+     printf("You may wish to check your task priority settings in "\
+            "\"<bsp path>\\iniche\\src\\h\\nios2\\ipport.h\" against "\
+            "the priority settings in your application and recompile.\n\n");
+   }
+   else if (error == OS_PRIO_INVALID)
+   {
+     printf("Priority requested for task \"%s\" (Prio:%d) exceeds "\
+            "available priority levels in the system (OS_LOWEST_PRIO = %d)\n\n",
+             nettask->name, nettask->priority, OS_LOWEST_PRIO);
+             
+     printf("Please modify the tasks priority level, or modify the "\
+            "\"Lowest assignable priority\" setting in the MicroC/OS-II "\
+            "component\n");
+   }
+   else if (error != OS_NO_ERR)
+   {                          /* All other errors are fatal */
+      printf("Task create error /(MicroC/OS-II error code:%d/) on %s\n",
+             error, nettask->name);
+      return (-1);
+   }
+
+   /* Include the task name, so that uc/osII (os aware) debuggers can
+    * display it.
+    */
+   OSTaskNameSet(nettask->priority, (INT8U*)&nettask->name[0], &error);
+
+   nettask->stackbase = (char*)stack;
+   *nettask->tk_ptr = (INT8U)nettask->priority;  
+
+   printf("Created \"%s\" task (Prio: %d)\n",
+         (char *)nettask->name, nettask->priority);
+
+   return (0);
+}
+
+
+
+#ifdef OS_PREEMPTIVE
+
+/* FUNCTION: wait_app_sem()
+ *
+ * Wait on an application semaphore
+ *
+ * PARAM1: unsigned long      semaphore ID
+ *
+ * RETURN: none
+ *
+ * This function is invoked by the PING and FTP client tasks to block while
+ * they wait for the corresponding application event to be signaled.
+ * The application event is signaled by the console task, or the 
+ * Telnet server task, or the timer task upon the occurance of a relevant
+ * event (e.g., configuration inputs from user, initiation of a new session,
+ * or a periodic timeout notification.
+ */
+void
+wait_app_sem(unsigned long semid)
+{
+   INT8U error = 0;
+   int   errct = 0;
+
+   if ((0 <= semid) && (semid <= MAX_SEMID))
+   {
+      do
+      {
+         OSSemPend(app_semaphore[semid], 0, &error);
+         /* 
+          * Sometimes we get a "timeout" error even though we passed a zero
+          * to indicate we'll wait forever. When this happens, try again:
+          */
+         if ((error == 10) && (++errct > 1000))
+         {
+            panic("lock NET");   /* fatal */
+            return;
+         }
+      } while (error == 10);
+   }
+   else
+      dtrap();
+}
+
+
+
+/* FUNCTION: post_app_sem()
+ *
+ * Post an application semaphore
+ *
+ * PARAM1: unsigned long      semaphore ID
+ *
+ * RETURN: none
+ *
+ * This function is invoked by the console task, or the Telnet server task,
+ * or the timer task upon the occurence of an event such as a configuration
+ * input from user, initiation of a new session, or a periodic timeout
+ * notification. It signals the corresponding application event.
+ */
+
+void
+post_app_sem(unsigned long semid)
+{
+   INT8U error;
+
+   if ((0 <= semid) && (semid <= MAX_SEMID))
+   {
+      error = OSSemPost(app_semaphore[semid]);
+      if (error != OS_NO_ERR)
+      {
+         panic("unlock NET");
+      }
+   }
+   else
+      dtrap();
+}
+
+#endif   /* OS_PREEMPTIVE */
+
+
+
+/* Rest of file is for TEST Purposes Only and is excluded unless we're
+ * doing lock_net checking.
+ */
+
+#ifdef LOCKNET_CHECKING
+
+#include "q.h"       /* InterNiche queue defines */
+
+/* locally define external items involved in checking locks */
+extern queue rcvdq;
+extern queue bigfreeq;
+extern queue lilfreeq;
+extern int iniche_net_ready;
+extern queue mfreeq;
+
+extern int irq_level;  /* level of nesting in irq_Mask() and irq_Unmask() */
+
+/* FUNCTION: LOCKNET_CHECK()
+ *
+ * If the passed queue is one of the sensitive ones then make sure
+ * the related resource is locked.
+ *
+ * PARAM1: queue * q
+ *
+ * RETURNS: nothing, panics if test fails
+ */
+
+void
+LOCKNET_CHECK(struct queue * q)
+{
+
+   /* Don't start checking until the net is up */
+   if(!iniche_net_ready)
+      return;
+
+#ifdef INCLUDE_TCP
+#ifndef MINI_TCP
+   /* On uCOS/Nichestack/TCP builds, check the mbuf free queue is locked
+    * by the NET_RESID semaphore. If it's not we panic().
+    */
+   if(q == &mfreeq)
+   {
+      /* A non-zero from OSSemAccept() means the semaphore was NOT locked */
+      if (OSSemAccept(resid_semaphore[NET_RESID]) != 0)
+      {
+         panic("locknet_check1");
+      }
+   }
+#endif /* not MINI_TCP */
+#endif /* INCLUDE_TCP */
+
+   /* quick return if it's not one of the other sensitive queues */
+   if((q != &rcvdq) &&
+      (q != &bigfreeq) &&
+      (q != &lilfreeq))
+   {
+      return;
+   }
+
+   /* Since the Nios2 build uses interrupt disabling to protect these
+    * queues, we just need to check the Interrupt state. We use look at
+    * the irq_level to get the current interrupt state, if interrupts
+    * were not then we are going to panic().
+    */
+
+   if(irq_level != 1)    /* Get current interupt state */
+   {
+      panic("locknet_check2");
+   }
+   return;
+}
+
+#endif /* LOCKNET_CHECKING */
+
+#endif /* UCOS_II */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/targnios.c b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/targnios.c
new file mode 100644
index 0000000..998114e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/targnios.c
@@ -0,0 +1,887 @@
+/*
+ * FILENAME: targnios.c
+ *
+ * Copyright 2004-2008 InterNiche Technologies Inc. All rights reserved.
+ *
+ * Target board support routines for InterNiche TCP/IP.
+ * This one for the ALTERA Cyclone board with the ALTERA Nios2 Core running
+ * with the uCOS-II RTOS.
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * MODULE: NIOS2GCC
+ * ROUTINES: prep_enet(), pre_task_setup(), post_task_setup()
+ * PORTABLE: no
+ *
+ * 06/21/2004
+ * 10/21/2008 (skh)
+ * 
+ */
+
+#include "ipport.h"
+#include "libport.h"
+#include "in_utils.h"
+#include "memwrap.h"
+#ifdef VFS_FILES
+#include "vfsfiles.h"
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Conditionally include OS-dependant code.
+ */
+#ifndef SUPERLOOP
+#include "osport.h"
+#endif
+
+#ifdef UCOS_II
+/* If uCOS-II, bring in the needed include files */
+#include "includes.h"
+#endif
+
+#ifdef USE_PPP
+#include "ppp_port.h"
+#include "comline.h"
+#include "ifmap.h"
+#include "../mppp/mppp.h"
+extern int ppp_default_type;  /* in ppp code */
+extern int ppp_static;     /* number static PPP ifaces to set */
+#endif   /* USE_PPP */
+
+#ifdef USE_MODEM
+#include "../modem/mdmport.h"
+#endif
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"
+#endif
+
+#ifdef SMTP_ALERTS
+#include "smtpport.h"
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Include headers for cache-bypass macros and 
+ * to the device abstraction layer code that handles
+ * generic MAC initialization 
+ */
+#ifdef ALT_INICHE
+#include "alt_iniche_dev.h"
+#include "sys/alt_cache.h"
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Move conditional compilation on SUPERLOOP so that the following
+ * code will be used w/ SUPERLOOP
+ */
+
+#include <ether.h>
+
+extern int (*port_prep)(int);
+
+extern struct net netstatic[MAXNETS];   
+
+#if defined(MEMDEV_SIZE) && defined(VFS_FILES)
+int   init_memdev(void);
+#endif
+
+#ifdef INCLUDE_NVPARMS
+void nv_defaults(void);   /* set default Integrator NV parameters */
+#endif  /* INCLUDE_NVPARMS */
+
+extern int (*port_prep)(int);
+extern int prep_armintcp(int ifaces_found);
+
+#ifdef USE_PPP
+extern int prep_ppp(int ifaces_found);
+extern int   (*ppp_type_callback)(LINEP);
+extern int   ppp_type_setup(LINEP);
+#endif
+#ifdef USE_SLIP
+extern int prep_slip(int ifaces_found);
+#endif
+#ifdef USE_SMSC91X
+extern int prep_s91(int ifaces_found);
+#endif
+
+OS_EVENT *rcvdq_sem_ptr;
+OS_EVENT *mheap_sem_ptr;
+#ifdef OS_PREEMPTIVE
+OS_EVENT *resid_semaphore[MAX_RESID+1];
+OS_EVENT *app_semaphore[MAX_SEMID+1];
+#endif
+
+#ifndef TCPWAKE_RTOS
+/*
+ * Q and Mutex used by tcp_sleep/wakeup
+ */
+extern struct TCP_PendPost global_TCPwakeup_set[GLOBWAKE_SZ];
+extern int global_TCPwakeup_setIndx;
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Provide init routine to call after multi-tasking
+ * has started to create uc/OS resources.
+ *
+ * Do not build this portion with SUPERLOOP
+ */
+#ifdef ALT_INICHE
+#ifndef SUPERLOOP
+
+extern OS_EVENT *resid_semaphore[MAX_RESID+1];
+
+void alt_iniche_init(void)
+{
+   int i;
+
+   /* initialize the npalloc() heap semaphore */
+   mheap_sem_ptr = OSSemCreate(1);
+   if (!mheap_sem_ptr)
+      panic("mheap_sem_ptr create err"); 
+
+   rcvdq_sem_ptr = OSSemCreate(0);
+   if (!rcvdq_sem_ptr)
+      panic("rcvdq_sem_ptr create err"); 
+
+#ifdef OS_PREEMPTIVE
+   for (i = 0; i <= MAX_RESID; i++)
+   {
+      resid_semaphore[i] = OSSemCreate(1);
+      if (!resid_semaphore[i])
+         panic("resid_semaphore create err");  
+   }
+   for (i = 0; i <= MAX_SEMID; i++)
+   {
+      app_semaphore[i] = OSSemCreate(1);
+      if (!app_semaphore[i])
+         panic("app_semaphore create err");  
+   }
+#endif  /* OS_PREEMPTIVE */
+
+#ifndef TCPWAKE_RTOS
+   /* 
+    * clear global_TCPwakeup_set
+    */
+   for (i = 0; i < GLOBWAKE_SZ; i++)
+   {
+      global_TCPwakeup_set[i].ctick = 0;
+      global_TCPwakeup_set[i].soc_event = NULL;
+      global_TCPwakeup_set[i].semaphore = OSSemCreate(0);
+      if (!global_TCPwakeup_set[i].semaphore)
+         panic("globwake_semaphore create err");  
+   }
+   global_TCPwakeup_setIndx = 0;
+#endif  /* TCPWAKE_RTOS */
+}
+#endif /* !SUPERLOOP */
+#endif /* ALT_INICHE */
+
+
+/* hardware setup called from main before anything else (e.g.
+ * before tasks, printf, memory alloc, etc. 
+ *
+ * Return NULL if OK, else brief error message
+ */
+
+char *
+pre_task_setup()
+{
+#ifdef USE_LCD
+   write_leds(0);
+   write_7seg_raw(0x0000);
+#endif
+
+   /* preset buffer counts; may be overridden from command line */
+   bigbufs = MAXBIGPKTS;
+   lilbufs = MAXLILPKTS;
+   bigbufsiz = BIGBUFSIZE;
+   lilbufsiz = LILBUFSIZE;
+
+   /* Install callback to prep_armintcp from prep_ifaces() */
+   port_prep = prep_armintcp;
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * The alt_iniche_dev initialization code provides
+ * for calling get_ip_addr() (which is in *application* 
+ * code) for IP address assignment, for each mac (net).
+ * The following is thus disabled.
+ */
+#ifndef ALT_INICHE
+#ifndef INCLUDE_NVPARMS
+   {
+      int i = 0;              /* network index */
+
+#ifdef USE_SMSC91X
+      /* Ethernet */
+      if (i < MAXNETS)
+      {
+         netstatic[i].n_ipaddr = htonl(0x0a000064);  /* 10.0.0.100 */
+         netstatic[i].snmask = htonl(0xff000000);    /* 255.0.0.0 */
+         netstatic[i].n_defgw = htonl(0x0a000001);   /* 10.0.0.1 */
+#ifdef DHCP_CLIENT
+         netstatic[i].n_flags |= NF_DHCPC;
+#endif
+         i++;
+      }
+#endif /* SMSC91x */
+
+#ifdef USE_PPP
+      /* PPP */
+      if (i < MAXNETS)
+      {
+         netstatic[i].n_ipaddr = htonl(0xc0a80301);  /* 192.168.3.1 */
+         netstatic[i].snmask = htonl(0xffffff00);    /* 255.255.255.0 */
+         netstatic[i].n_defgw = htonl(0x00000000);   /* 0.0.0.0 */
+         i++;
+      }
+
+#ifdef LB_XOVER
+      if (i < MAXNETS)
+      {
+         netstatic[i].n_ipaddr = htonl(0x00000000);
+         netstatic[i].snmask = htonl(0x00000000);
+         netstatic[i].n_defgw = htonl(0x00000000);
+         i++;
+      }
+#endif /* LB_XOVER */
+#endif /* USE_PPP */
+
+#ifdef MAC_LOOPBACK
+      /* loopback */
+      if (i < MAXNETS)
+      {
+         netstatic[i].n_ipaddr = htonl(0x7f000001); /* 127.0.0.1 */
+         netstatic[i].snmask = htonl(0xff000000);   /* 255.0.0.0 */
+         netstatic[i].n_defgw = htonl(0x00000000);  /* 0.0.0.0 */
+         i++;
+      }
+#endif /* MAC_LOOPBACK */
+   }
+
+#else  /* INCLUDE_NVPARMS is used */
+
+   /* set callback to set up default NV values. The generic NV system 
+    * code in misclib\nvparams.c may call this NIOS2INI specific 
+    * routine if it is set.
+    */
+   set_nv_defaults = nv_defaults;   /* set nv parameter init routine */
+
+#endif /* INCLUDE_NVPARMS */
+
+#endif /* not ALT_INICHE */
+
+#ifdef   USE_PPP
+#ifdef   MINI_IP
+   /* If we are using the mini IP layer and PPP, then  overwrite the 
+    * NDIS hook with the PPP prep routine 
+    */
+   port_prep = prep_ppp;
+#endif   /* MINI_IP */
+
+   /* for all PPP implementations, set a callback so the we can
+    * set the device type of new PPP links.
+    */
+   ppp_default_type = LN_PORTSET;
+   ppp_type_callback = ppp_type_setup;
+
+   /* Set the number of static PPP ifaces. Allow one each for modem and
+    * PPPOE, and two for Loopback-crossover.
+    */
+   ppp_static = 1;   /* base for modem or UART direct connect */
+
+#ifdef LB_XOVER
+   ppp_static += 2;     /* add pair for loopback crosover */
+#endif   /* LB_XOVER */
+
+
+#ifdef NOTDEF
+   /* This little block of code is usefully for testing PPPoE in loopback
+    * on windows (e.g. bouncing the packets off the NDIS driver) but for
+    * most purposes should not be used.
+    */
+#ifdef USE_PPPOE
+#ifdef PPPOE_LBTEST
+   ppp_static += 2;     /* loopback test needs 2 interfaces */
+#else
+   ppp_static++;
+#endif   /* PPPOE_LBTEST */
+#endif   /* USE_PPPOE */
+#endif   /* NOTDEF */
+
+#endif   /* USE_PPP */
+
+
+   return NULL;
+}
+
+/* more setup called after tasks are set up
+ *
+ * Return NULL if OK, else brief error message
+ */
+
+char *
+post_task_setup()
+{
+   return NULL;
+}
+
+
+/*
+ * memtrapsize - memory allocator trap size
+ */
+unsigned memtrapsize = 0;
+
+#ifdef INCLUDE_NVPARMS
+
+/* FUNCTION: nv_defaults()
+ *
+ * This is called from the NV parameters syystem if there is
+ * no NV file in flash. It builds a list of functional default
+ * NV values for testing and/or system generation.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: void
+ */
+
+static char * logfilename = "login.nv";
+static char * srvfilename = "server.nv";
+static char * natfilename = "natdb.nv";
+
+
+void
+nv_defaults()
+{
+   int   iface = 0;
+   VFILE *fp;
+   int   e;
+
+   /* store default IP info */
+#ifdef USE_SMSC91X
+   inet_nvparms.ifs[iface].ipaddr =  htonl(0x0a000067);   /* 10.0.0.106 */
+#ifdef USE_PPPOE
+   inet_nvparms.ifs[iface].subnet = htonl(0xfffe0000);    /* 255.254.0.0 */
+   inet_nvparms.ifs[iface].gateway = htonl(0x00000000);   /* 0.0.0.0 */
+#else
+   inet_nvparms.ifs[iface].subnet = htonl(0xff000000);    /* 255.0.0.0 */
+   inet_nvparms.ifs[iface].gateway = htonl(0x0a000001);   /* 10.0.0.1 */
+#endif
+   inet_nvparms.ifs[iface].client_dhcp = 0;
+
+   dprintf("nv_defaults: set net %d IP to %u.%u.%u.%u\n",
+    iface, PUSH_IPADDR(inet_nvparms.ifs[iface].ipaddr) );
+
+   iface++;
+#endif /* */
+
+#ifdef USE_PPP
+   /* PPP */
+   inet_nvparms.ifs[iface].ipaddr = htonl(0x00000000);
+   inet_nvparms.ifs[iface].subnet = htonl(0xffffff00);    /* 255.255.255.0 */
+   inet_nvparms.ifs[iface].gateway = htonl(0xc0a80801);   /* 192.168.8.1 */
+   iface++;
+
+#ifdef LB_XOVER
+   inet_nvparms.ifs[iface].ipaddr = htonl(0x00000000);
+   inet_nvparms.ifs[iface].subnet = htonl(0x00000000);
+   inet_nvparms.ifs[iface].gateway = htonl(0x00000000);
+   iface++;
+#endif /* LB_XOVER */
+
+#endif /* USE_PPP */
+
+   /* loopback */
+   inet_nvparms.ifs[iface].ipaddr = htonl(0x00000000);
+   inet_nvparms.ifs[iface].subnet = htonl(0x00000000);
+   inet_nvparms.ifs[iface].gateway = htonl(0x00000000);
+
+#ifdef USE_COMPORT
+   comport_nvparms.LineProtocol = 1;
+#endif   /* defined (USE_PPP) || defined(USE_SLIP) */
+
+#ifdef   USE_PPP
+   ppp_nvparms.ppp_ConsoleLog = 0;    /* Log Modem & PPP events to console */
+   ppp_nvparms.ppp_FileLog = 0;       /* Log Modem & PPP events to file */
+   ppp_nvparms.ppp_keepalive = 0;     /* seconds between PPP echos, 0=disable */
+   ppp_nvparms.ppp_client_tmo = 500;  /* timeout for connects as client */
+   ppp_nvparms.line_tmo = 300;
+#ifdef PPP_VJC
+   ppp_nvparms.ppp_request_vj = 1;    /* request that the other side do VJ compression */
+#endif   /* PPP_VJC */
+#ifdef PAP_SUPPORT
+   ppp_nvparms.require_pap = 0;
+#endif   /* PAP_SUPPORT */
+#ifdef USE_PPPOE
+   strcpy(ppp_nvparms.username, "ppptest2");
+   strcpy(ppp_nvparms.password, "2ppptest");
+   strcpy(ppp_nvparms.secret, "2ppptest");
+#endif   /* USE_PPPOE */
+#endif   /* USE_PPP */
+
+#ifdef USE_MODEM
+   strcpy(modem_nvparms.dial_phone, "YOUR_ISP_PHONE\n");
+   strcpy(ppp_nvparms.username, "YOUR_ISP_NAME");
+   strcpy(ppp_nvparms.password, "YOUR_ISP_PASSWORD");
+   strcpy(modem_nvparms.modem_init, "AT&D0&C1\n");
+   strcpy(ppp_nvparms.loginfile, logfilename);
+   strcpy(ppp_nvparms.logservefile, srvfilename);
+#endif   /* USE_MODEM */
+
+#ifdef USE_COMPORT
+   comport_nvparms.comport = '2';
+   comport_nvparms.LineProtocol = 1;
+#endif   /* USE_COMPORT */
+
+#ifdef NATRT
+   natrt_nvparms.nat_enabled = 1;
+   natrt_nvparms.nat_inet = 1;
+   natrt_nvparms.nat_localnet = 0;
+   natrt_nvparms.tcp_timeout = 300;
+   natrt_nvparms.udp_timeout = 500;
+#endif   /* NATRT */
+
+#ifdef SMTP_ALERTS
+   smtp_nvparms.mserver = htonl(0x00000000);
+   strcpy(smtp_nvparms.rcpt, "\n");
+#endif /* SMTP_ALERTS */
+
+#ifdef DNS_CLIENT_UPDT
+   strcpy(inet_nvparms.dns_zone_name, "iniche.com");   /* zone name */
+#endif /* DNS_CLIENT_UPDT */
+
+   /* create the login script file */
+   fp = nv_fopen(logfilename, "w+");
+   if (fp == NULL)
+      dprintf("error creating %s\n", logfilename);
+   else
+   {
+      e = nv_fprintf(fp, "#\n#empty login.nv\n#\n");
+      if (e < 1)
+      {
+         dprintf("nv_defaults: error writing %s\n", logfilename);
+      }
+      nv_fclose(fp);
+   }
+
+   /* create the some required NV files */
+   nv_fopen(srvfilename, "w+");
+   nv_fopen(natfilename, "w+");
+
+}
+
+#endif  /* INCLUDE_NVPARMS */
+
+int 
+prep_armintcp(int ifaces_found)
+{
+/*
+ * Altera Niche Stack Nios port modification:
+ * Call iniche_devices_init, in alt_iniche_dev.c, 
+ * to step through all devices and all their respective
+ * low-level initialization routines.
+ */
+#ifdef ALT_INICHE
+   ifaces_found = iniche_devices_init(ifaces_found);
+#endif
+
+#ifdef USE_SMSC91X
+   ifaces_found = prep_s91(ifaces_found);
+#endif
+
+#ifdef USE_PPP
+   ifaces_found = prep_ppp(ifaces_found);
+#endif
+
+#ifdef USE_SLIP
+   ifaces_found = prep_slip(ifaces_found);
+#endif
+
+   return ifaces_found;
+}
+
+
+#ifdef UCOS_II
+OS_EVENT * mheap_sem_ptr;
+OS_EVENT * rcvdq_sem_ptr;
+#endif
+
+
+char *
+npalloc_base(unsigned size, int cacheable)
+{
+char * ptr;
+void *(*alloc_rtn)(size_t size) = cacheable ? malloc : alt_uncached_malloc;
+
+#ifdef UCOS_II
+   INT8U err;
+#endif
+
+#ifdef UCOS_II
+   OSSemPend(mheap_sem_ptr, 0, &err);
+   if(err)
+   {
+      int errct = 0;
+
+      /* sometimes we get a "timeout" error even though we passed a zero
+       * to indicate we'll wait forever. When this happens, try again:
+       */
+      while(err == 10)
+      {
+         if(errct++ > 1000)
+         {
+            panic("npalloc");    /* fatal? */
+            return NULL;
+         }
+         OSSemPend(mheap_sem_ptr, 0, &err);
+      }
+   }
+#endif
+
+#ifdef   MEM_WRAPPERS
+   ptr = wrap_alloc(size, alloc_rtn);
+#else
+   ptr = (*alloc_rtn)(size);
+#endif
+
+#ifdef UCOS_II 
+   err = OSSemPost(mheap_sem_ptr);
+#endif
+   
+   if(!ptr)
+      return NULL;
+
+   MEMSET(ptr, 0, size);
+   return ptr;      
+}
+
+void
+npfree_base(void *ptr, int cacheable)
+{
+   void (*free_rtn)(void *ptr) = cacheable ? free : alt_uncached_free;
+#ifdef UCOS_II
+   INT8U err;
+
+   OSSemPend(mheap_sem_ptr, 0, &err);
+   if (err)
+   {
+      int errct = 0;
+
+      /* sometimes we get a "timeout" error even though we passed a zero
+       * to indicate we'll wait forever. When this happens, try again:
+       */
+      while (err == 10)
+      {
+         if (errct++ > 1000)
+         {
+            panic("npfree");    /* fatal? */
+            return;
+         }
+         OSSemPend(mheap_sem_ptr, 0, &err);
+      }
+   }
+   
+#ifdef   MEM_WRAPPERS
+   wrap_free((char*)ptr, free_rtn);
+#else
+   (*free_rtn)(ptr);
+#endif
+
+   err = OSSemPost(mheap_sem_ptr);
+#else
+#ifdef   MEM_WRAPPERS
+   wrap_free((char*)ptr, free_rtn);
+#else
+   (*free_rtn)(ptr);
+#endif
+#endif
+
+}
+
+char *
+npalloc(unsigned size)
+{
+   return npalloc_base(size, 1);
+}
+
+void
+npfree(void *ptr)
+{
+   if(ptr) {
+      npfree_base(ptr, 1);
+   }
+}
+
+
+/*
+ * Altera Niche Stack Nios port modification:
+ *
+ * ncpalloc()/ncpfree(): Uncached memory allocation/free
+ * uncached version of the built-in npalloc()/npfree().
+ *
+ * These routines should be used in Nios II systems on
+ * any data structure or buffer that may be touched outside
+ * the CPU (i.e. DMA) for cache coherency purposes.
+ *
+ * If no DMA is present in the system the conentional npalloc()
+ * and npfree() may be used directly.
+ *
+ * The main Nios II Interniche port configuration file, ipport.h,
+ * contains macro definitions that assign specific memory
+ * allocation calls to these routines.
+ */
+#ifdef ALT_INICHE
+char * ncpalloc(unsigned size)
+{
+   return npalloc_base(size, 0);
+}
+
+void ncpfree(void *ptr)
+{
+   if(ptr) {
+      npfree_base(ptr, 0);
+   }
+}
+
+#endif /* ALT_INICHE defined */
+
+#ifdef   USE_PPP
+
+/* FUNCTION: ppp_type_setup(M_PPP)
+ *
+ * This per port routine is called via ppp_type_callback whenver
+ * ppp sets up a new PPP link. It should set the PPP line type 
+ * (line->lower_type) based on local port configuration info 
+ * (either hardcoded or read from FLASH). Possible options include:
+ *
+ * LN_ATMODEM - Hayes compatible dialup modem.
+ * LN_PPPOE - PPP over ethernet (also needs some ethernet setup)
+ * LN_LBXOVER - Loopback/crossover links for testing
+ * LN_UART - direct connect via RS-232 (or similar) UART.
+ *
+ *    The MPPP passed already has the ifp attached and configured 
+ * from NVparms, so you can use if name and IP addressing info to
+ * select the types. If you need to set up other PPP mappings (like 
+ * selecting a modem, uart, or ethernet device) this is a good place 
+ * to do it.
+ *
+ * returns 0 if OK or ENP error code
+ */
+
+   /* Table to allocate PPPs in the following order:
+    * 
+    * #ifdef LB_XOVER, assign first two to LB_XOVER client & server
+    * #ifdef USE_MODEM, assign one to modem
+    * #else ifdef USE_COMPORT, assign one to UART
+    * #ifdef USE_PPPOE, assign one (or two if loopback) 
+    *                   which will map to NDIS ethernet.
+    */
+
+static   int   ppps_already = 0;
+static   int   ppp_types[] = 
+{
+#ifdef LB_XOVER
+   LN_LBXOVER, LN_LBXOVER,
+#endif
+#ifdef USE_MODEM
+   LN_ATMODEM,
+#else 
+#ifdef USE_COMPORT
+   LN_UART,
+#endif   /* USE_COMPORT */
+#endif   /* USE_MODEM */
+#ifdef USE_PPPOE
+   LN_PPPOE,
+#ifdef PPPOE_LBTEST
+   LN_PPPOE,         /* PPPOE loopback test needs second interface */
+#endif   /* PPPOE_LBTEST */
+#endif   /* USE_PPPOE */
+
+   /* extra entry are LB_XOVER for testing */
+#ifdef LB_XOVER
+   LN_LBXOVER, LN_LBXOVER,
+   LN_LBXOVER, LN_LBXOVER,
+#endif
+};
+
+
+int
+ppp_type_setup(LINEP line)
+{
+   int err = 0;
+
+   /* make sure we're not off the end of the static table */
+   if (ppps_already >= (sizeof(ppp_types)/sizeof(int)))
+   {
+      /* If table is fully assigned, then set a default */
+#ifdef USE_PPPOE
+      line->lower_type = LN_PPPOE;
+#else
+#ifdef USE_MODEM
+      line->lower_type = LN_ATMODEM;
+#else
+#ifdef USE_COMPORT
+      line->lower_type = LN_UART;
+#else
+      /* use whatever's last in the table */
+      line->lower_type = ppp_types[(sizeof(ppp_types)/sizeof(int)) - 1];
+#endif /* USE_COMPORT */
+#endif /* USE_MODEM */
+#endif /* USE_PPPOE */
+      dprintf("ppp_type_setup: defaulting type to %d\n", line->lower_type);
+   }
+   else
+   {
+      /* assign next type from table */
+      line->lower_type = ppp_types[ppps_already++];
+   }
+
+   /* If it's PPPoE we need to assign it to an ethernet interface too */
+#ifdef USE_PPPOE
+   if(line->lower_type == LN_PPPOE)
+   {
+      NET ifp;
+
+      /* find first ethernet interface */
+      for(ifp = (NET)netlist.q_head; ifp; ifp = ifp->n_next)
+      {
+         if(ifp->mib.ifType == ETHERNET)
+         {
+            M_PPP mppp;
+            /* bind PPP iface for this line (upper) to ethernet (lower) */
+            mppp = (M_PPP)(line->upper_unit);
+            ifmap_bind(mppp->ifp, ifp);
+#ifdef PPPOE_LBTEST
+            /* for PPPOE loopback it helps to add routes */
+#endif   /* PPPOE_LBTEST */
+            break;
+         }
+      }
+      /* If no ethernet was found then set error code */
+      if(!ifp)
+         err = ENP_LOGIC;
+   }
+#endif   /* USE_PPPOE */
+
+   return err;   /* OK return */
+}
+
+
+
+/* FUNCTION: ln_uinit()
+ *
+ * Initializes the device specified in the com_line struct
+ *
+ * PARAM1: line         pointer to com_line structure
+ *
+ * RETURN: 0 if successful, otherwise an error code
+ */
+
+int
+ln_uinit(LINEP line)
+{
+   int   unit;
+   int   err;
+
+   if (line->ln_state != LN_INITIAL)
+   {
+      dtrap();       /* don't call this multiple times */
+      return (0);      /* return OK anyway... */
+   }
+
+   if (units_set++ > 0)
+   {
+      dtrap();    /* trying to set up multiple UARTs unsupported */
+   }
+   unit = 1;  /* channel 1 == unit 1 */
+   err = uart_init(unit);  /* open UART and assign comport */
+   
+   if (err)
+      return (err);    /* report hardware failures */
+
+   line->lower_unit = unit;
+   line->ln_state = LN_CONNECTED;
+   uarts[unit].line = line;
+
+   return (0);
+}
+
+
+
+/* FUNCTION: ln_uconnect()
+ *
+ * Put PPP device into the 'connected' state
+ *
+ * PARAM1: line;        pointer to com_line structure 
+ * 
+ * RETURN: 0 if successful, otherwise an error code
+ */
+int
+ln_uconnect(LINEP line)
+{
+   int   err;
+   
+   if (line->ln_state == LN_INITIAL) 
+   {
+      err = ln_uinit(line);
+      if (err)
+         return (err);   /* report hardware failures */
+   }
+   line->ln_state = LN_CONNECTED;
+
+   /* Indicate to PPP that lower link is now up */
+   ppp_lowerup((M_PPP)(line->upper_unit), LCP_STATE);
+
+   return (0);
+}
+
+
+
+/* FUNCTION: ln_udisconnect()
+ *
+ * 'Disconnect' the PPP device
+ *
+ * PARAM1: line         pointer to com_line structure
+ *
+ * RETURN: 0 (always successful)
+ */
+
+int
+ln_udisconnect(LINEP line)
+{
+   line->ln_state = LN_DISCONNECTED;
+   return (0);
+}
+
+
+
+/* FUNCTION: ln_putc()
+ *
+ * send a single byte to the PPP device 
+ *
+ * PARAM1: line         pointer to com_line structure
+ * PARAM2: ch           character to be sent
+ *
+ * RETURN: 0 if successful, otherwise an error code
+ */
+
+int
+ln_uputc(LINEP line, int ch)
+{
+   return (uart_putc(line->lower_unit, (u_char)ch));
+}
+
+#endif   /* USE_PPP */
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Removed conditioanl compilation on SUPERLOOP to here.
+ */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/nios2/uart.h b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/uart.h
new file mode 100644
index 0000000..122bbcb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/nios2/uart.h
@@ -0,0 +1,29 @@
+/*
+ * FILENAME: uart.h 
+ *
+ * Copyright 2004 InterNiche Technologies.  All rights reserved.
+ *
+ * DESCRIPTION: serial communication device support definitions
+ *
+ * This file for:
+ *   ALTERA Cyclone Dev board with the ALTERA Nios2 Core.
+ *   SMSC91C11 10/100 Ethernet Controller
+ *   GNU C Compiler provided by ALTERA Quartus Toolset.
+ *   Quartus HAL BSP
+ *   uCOS-II RTOS Rel 2.76 as distributed by Altera/NIOS2
+ *
+ * MODULE  : nios2gcc
+ * PORTABLE: no
+ *
+ */
+
+#ifndef UART_H
+#define UART_H
+
+/* Until we have the uart drivers for the Altera NIOS2 Cyclone dev board
+ * this is a place holder file to allow a PPP build with LB_XOVER.
+ * 
+ * Add more here later -AK- 
+ */
+
+#endif  /* UART_H */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.c
new file mode 100644
index 0000000..123696b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.c
@@ -0,0 +1,443 @@
+/*
+ * FILENAME: in_pcb.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: in_pcballoc(), in_pcbbind(), ip6_pcbbind(), in_pcbconnect(), 
+ * ROUTINES: in_pcbdisconnect(), in_pcbdetach(), in_setsockaddr(), 
+ * ROUTINES: in_setpeeraddr(), in_pcblookup(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#include "ipport.h"
+#include "tcpport.h"
+#include "protosw.h"
+#include "in_pcb.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+/* 2/9/00 - modified in_pcblookup() put the matched pcb at the head 
+ * of the list to speed future searches. The stats below are to gauge 
+ * the success of this.
+ */
+long     inpcb_cachehits   =  0;
+long     inpcb_cachemiss   =  0;
+
+
+/* FUNCTION: in_pcballoc()
+ *
+ * Allocate a protocol control block and prepare it for use.
+ *
+ * PARAM1: struct socket *so
+ * PARAM2: struct inpcb *head
+ *
+ * RETURNS: PCB if OK, NULL if out of memory.
+ */
+
+int
+in_pcballoc(struct socket * so, 
+   struct inpcb * head)
+{
+   struct inpcb * inp;
+
+   inp = INP_ALLOC (sizeof (*inp));
+   if (inp == 0)
+      return ENOMEM;
+   inp->inp_head = head;
+   inp->inp_socket = so;
+
+   /* Set Path MTU to a very small default. It should get expanded 
+    * later by v4 or v6 specific SYN code. We don't want it zero 
+    * in case it doesn't get expanded promptly.
+    */
+   inp->inp_pmtu = 512;
+   insque(inp, head);
+   so->so_pcb = inp;
+   return 0;
+}
+
+
+/* FUNCTION: in_pcbdetach()
+ * 
+ * PARAM1: struct inpcb *inp
+ *
+ * RETURNS: 
+ */
+
+void
+in_pcbdetach(struct inpcb * inp)
+{
+   struct socket *   so =  inp->inp_socket;
+
+   so->so_pcb = 0;
+   sofree(so);
+   remque(inp);
+   INP_FREE (inp);
+}
+
+
+
+#ifdef IP_V4   /* The rest of this file are specific to v4 */
+
+/* FUNCTION: in_pcbbind()
+ * 
+ * Guts of socket "bind" call for TCP.
+ *
+ * PARAM1: struct inpcb *inp
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 0 if OK, else one of the socket error codes
+ */
+
+
+int
+in_pcbbind(
+   struct inpcb * inp,
+   struct mbuf *  nam)
+{
+   struct socket *   so =  inp->inp_socket;
+   struct inpcb * head  =  inp->inp_head;
+   struct sockaddr_in * sin;
+   u_short  lport =  0;
+
+
+   if (inp->inp_lport || inp->inp_laddr.s_addr != INADDR_ANY)
+      return (EINVAL);
+   if (nam == 0)
+      goto noname;
+   sin = mtod(nam, struct sockaddr_in *);
+
+   /*
+    * removed test here for "if (nam->m_len != sizeof (*sin))"
+    * since it really complicatges supporting dual IPv4/v6, and 
+    * the 2.0 stack now checks this in t_bind(). -JB-
+    */
+   if (sin->sin_addr.s_addr != INADDR_ANY) 
+   {
+      if (ip_mymach(sin->sin_addr.s_addr) != sin->sin_addr.s_addr)
+      return (EADDRNOTAVAIL);
+   }
+   lport = sin->sin_port;
+   if (lport) 
+   {
+      int   wild  =  0;
+
+      /* even GROSSER, but this is the Internet */
+      if ((so->so_options & SO_REUSEADDR) == 0 &&
+          ((so->so_proto->pr_flags & PR_CONNREQUIRED) == 0 ||
+          (so->so_options & SO_ACCEPTCONN) == 0))
+      {
+         wild = INPLOOKUP_WILDCARD;
+      }
+      if (in_pcblookup(head,
+          0L, 0, sin->sin_addr.s_addr, lport, wild))
+      {
+         return (EADDRINUSE);
+      }
+   }
+   inp->inp_laddr = sin->sin_addr;
+noname:
+   if (lport == 0)
+   {
+      do 
+      {
+         if (head->inp_lport++ < IPPORT_RESERVED ||
+             head->inp_lport > IPPORT_USERRESERVED)
+         {
+            head->inp_lport = IPPORT_RESERVED;
+         }
+         lport = htons(head->inp_lport);
+      } while(in_pcblookup(head, 0L, 0, inp->inp_laddr.s_addr, lport, 0));
+   }
+   inp->inp_lport = lport;
+   return (0);
+}
+
+
+/* FUNCTION: in_pcbconnect()
+ *
+ * Connect from a socket to a specified address.
+ * Both address and port must be specified in argument sin.
+ * If don't have a local address for this socket yet,
+ * then pick one.
+ * 
+ * PARAM1: struct inpcb *inp
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 
+ */
+
+int
+in_pcbconnect(struct inpcb * inp, 
+   struct mbuf *  nam)
+{
+   unsigned long ifaddr;
+   struct sockaddr_in * sin   =  mtod(nam,   struct sockaddr_in *);
+
+   if (nam->m_len < sizeof (*sin))
+      return (EINVAL);
+   if (sin->sin_family != AF_INET)
+      return (EAFNOSUPPORT);
+   if (sin->sin_port == 0)
+      return (EADDRNOTAVAIL);
+   /*
+    * If the destination address is INADDR_ANY,
+    * use the primary local address.
+    * If the supplied address is INADDR_BROADCAST,
+    * and the primary interface supports broadcast,
+    * choose the broadcast address for that interface.
+    */
+   if (sin->sin_addr.s_addr == INADDR_ANY)
+   {
+      if (inp && inp->ifp)
+         sin->sin_addr.s_addr = inp->ifp->n_ipaddr;
+      else
+         return (EADDRNOTAVAIL);
+   }
+   else if (sin->sin_addr.s_addr == INADDR_BROADCAST)
+      return (EADDRNOTAVAIL);
+
+
+   if (inp->inp_laddr.s_addr == INADDR_ANY) 
+   {
+#ifdef MULTI_HOMED
+      ip_addr hop1;     /* dummy for pass to iproute() */
+      NET npnet;     /* the netport iface we can send on */
+      /* call netport stack's IP routing */
+      npnet = iproute(sin->sin_addr.s_addr, &hop1);
+      if (!npnet)
+         return EADDRNOTAVAIL;
+      ifaddr = npnet->n_ipaddr;  /* local address for this host */
+#else    /* not netport MULTI_HOMED, use 0th (only) iface */
+      ifaddr = nets[0]->n_ipaddr;
+#endif   /* MULTI_HOMED */
+   }
+   else  /* inp->inp_laddr.s_addr != INADDR_ANY */
+      ifaddr = inp->inp_laddr.s_addr;  /* use address passed */
+
+   if (in_pcblookup(inp->inp_head,
+       sin->sin_addr.s_addr,
+       sin->sin_port,
+       ifaddr,
+       inp->inp_lport,
+       0))
+   {
+      return (EADDRINUSE);
+   }
+   if (inp->inp_laddr.s_addr == INADDR_ANY) 
+   {
+      if (inp->inp_lport == 0)
+         (void)in_pcbbind(inp, (struct mbuf *)0);
+      inp->inp_laddr.s_addr = ifaddr;
+   }
+   inp->inp_faddr = sin->sin_addr;
+   inp->inp_fport = sin->sin_port;
+   return 0;
+}
+
+
+
+/* FUNCTION: in_pcbdisconnect()
+ * 
+ * PARAM1: struct inpcb *inp
+ *
+ * RETURNS: 
+ */
+
+void
+in_pcbdisconnect(struct inpcb * inp)
+{
+
+   inp->inp_faddr.s_addr = INADDR_ANY;
+   inp->inp_fport = 0;
+   if (inp->inp_socket->so_state & SS_NOFDREF)
+      in_pcbdetach (inp);
+}
+
+/* FUNCTION: in_setsockaddr()
+ * 
+ * PARAM1: struct inpcb *inp
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 
+ */
+
+void
+in_setsockaddr(struct inpcb * inp, 
+   struct mbuf *  nam)
+{
+   struct sockaddr_in * sin;
+
+   nam->m_len = sizeof (*sin);
+   sin = mtod(nam, struct sockaddr_in *);
+   MEMSET(sin, 0, sizeof (*sin));
+   sin->sin_family = AF_INET;
+   sin->sin_port = inp->inp_lport;
+   sin->sin_addr = inp->inp_laddr;
+}
+
+
+
+/* FUNCTION: in_setpeeraddr()
+ * 
+ * PARAM1: struct inpcb *inp
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 
+ */
+
+void
+in_setpeeraddr(
+   struct inpcb * inp,
+   struct mbuf *  nam)
+{
+   struct sockaddr_in * sin;
+
+   nam->m_len = sizeof (*sin);
+   sin = mtod(nam, struct sockaddr_in *);
+   MEMSET(sin, 0, sizeof (*sin));
+   sin->sin_family = AF_INET;
+   sin->sin_port = inp->inp_fport;
+   sin->sin_addr = inp->inp_faddr;
+}
+
+
+
+/* FUNCTION: in_pcblookup()
+ *
+ * Find a TCP connection in the passed list which matches the
+ * parameters passed.
+ *
+ * PARAM1: struct inpcb *head
+ * PARAM2: u_long faddr
+ * PARAM3: unshort xfport
+ * PARAM4: u_long laddr
+ * PARAM5: unshort xlport
+ * PARAM6: int flags
+ *
+ * RETURNS: NULL if not found, else entry in inpcb list.
+ */
+
+
+struct inpcb * 
+in_pcblookup(struct inpcb * head, 
+   u_long   faddr, 
+   unshort  xfport,
+   u_long   laddr,
+   unshort  xlport,
+   int   flags)
+{
+   struct inpcb * inp, *   match =  0;
+   unshort  fport =  xfport; 
+   unshort  lport =  xlport;
+   int   matchwild   =  3;
+   int   wildcard;
+
+   for (inp = head->inp_next; inp != head; inp = inp->inp_next) 
+   {
+      if (inp->inp_lport != lport)
+         continue;
+
+      /* Skip non IPv4 sockets */
+      if(inp->inp_socket->so_domain != AF_INET)
+         continue;
+
+      wildcard = 0;
+      if (inp->inp_laddr.s_addr != INADDR_ANY) 
+      {
+         if (laddr == INADDR_ANY)
+            wildcard++;
+         else if (inp->inp_laddr.s_addr != laddr)
+            continue;
+      }
+      else 
+      {
+         if (laddr != INADDR_ANY)
+            wildcard++;
+      }
+      if (inp->inp_faddr.s_addr != INADDR_ANY) 
+      {
+         if (faddr == INADDR_ANY)
+            wildcard++;
+         else if (inp->inp_faddr.s_addr != faddr ||
+             inp->inp_fport != fport)
+         {
+            continue;
+         }
+      } else 
+      {
+         if (faddr != INADDR_ANY)
+            wildcard++;
+      }
+      if (wildcard && (flags & INPLOOKUP_WILDCARD) == 0)
+         continue;
+      if (wildcard < matchwild) 
+      {
+         match = inp;
+         matchwild = wildcard;
+         if (matchwild == 0)
+            break;
+      }
+   }
+   if (match == NULL)
+      return match;
+
+   if (head->inp_next == match)  /* got cache hit? */
+   {
+      inpcb_cachehits++;
+   }
+   else
+   {
+      inpcb_cachemiss++;
+      /* "cache" the match to be first checked next time. */
+      match->inp_next->inp_prev = match->inp_prev; /*unlink match */
+      match->inp_prev->inp_next = match->inp_next;
+
+      /* relink match as head->inp_next */
+      match->inp_next = head->inp_next;
+      head->inp_next = match;
+      match->inp_prev = head;
+      match->inp_next->inp_prev = match;
+   }
+   return (match);
+}
+#endif /* IP_V4 */
+
+#endif /* INCLUDE_TCP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.h
new file mode 100644
index 0000000..3802126
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/in_pcb.h
@@ -0,0 +1,120 @@
+/*
+ * FILENAME: in_pcb.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+*/
+
+#ifndef _IN_PCB_H
+#define  _IN_PCB_H   1
+
+/*
+ * Common structure pcb for internet protocol implementation.
+ * Here are stored pointers to local and foreign host table
+ * entries, local and foreign socket numbers, and pointers
+ * up (to a socket structure) and down (to a protocol-specific)
+ * control block.
+ */
+
+struct inpcb
+{
+   struct   inpcb *  inp_next, *inp_prev;   /* list links */
+   struct   inpcb *  inp_head;      /* chain of inpcb's for this protocol */
+
+   /* The same connection PCB is used for IPv4 and IPv6. Only one of the
+    * two following address pairs will be set, depending on the
+    * inp->socket->domain field (AF_INET or AF_INET6).
+    */
+   struct   in_addr  inp_faddr;  /* foreign host table entry */
+   struct   in_addr  inp_laddr;  /* local host table entry */
+
+#ifdef IP_V6
+   ip6_addr ip6_faddr;           /* foreign host address */
+   ip6_addr ip6_laddr;           /* local host address (should be on ifp) */
+   ip6_addr nexthop6;            /* next hop if (ifp is set) */
+#endif   /* IP_V6 */
+
+   int      inp_flags;           /* mask of INPF_XXX bits (defined below) */
+   int      inp_pmtu;            /* Path MTU (max dgram size) */
+   u_short  inp_fport;           /* foreign port */
+   u_short  inp_lport;           /* local port */
+   struct   socket * inp_socket; /* back pointer to socket */
+   char *   inp_ppcb;            /* pointer to per-protocol (TCP, UDP) pcb */
+   NET      ifp;                 /* interface if connected */
+};
+
+#define     INPLOOKUP_WILDCARD   1
+#define     INPLOOKUP_SETLOCAL   2
+
+#define     INPF_ROUTESET    0x01     /* nexthop and ifp are set */
+
+#define     sotoinpcb(so)     ((struct inpcb *)(so)->so_pcb)
+
+extern   int   in_pcballoc __P ((struct socket *, struct inpcb *));
+extern   int   in_pcbbind  __P ((struct inpcb *, struct mbuf *));
+extern   int   in_pcbconnect  __P ((struct inpcb *, struct mbuf *));
+extern   void  in_pcbdisconnect  __P ((struct inpcb *));
+extern   void  in_pcbdetach   __P ((struct inpcb *));
+extern   void  in_setsockaddr __P ((struct inpcb *, struct mbuf *));
+extern   void  in_setpeeraddr __P ((struct inpcb *, struct mbuf *));
+extern   void  in_losing   __P ((struct inpcb *));
+extern   void  in_rtchange __P ((struct inpcb *));
+
+extern   struct inpcb * in_pcblookup   __P ((struct inpcb *, 
+            u_long,  unshort, u_long,  unshort, int));
+extern   void  in_pcbnotify   __P ((struct inpcb *, struct in_addr *, 
+   int, void (*) (struct inpcb *)));
+
+#ifdef IP_V6
+/* IPv6 version of some of these routines */
+extern   int   ip6_pcbbind  __P ((struct inpcb *, struct mbuf *));
+extern   struct inpcb * ip6_pcblookup   __P ((struct inpcb *, 
+            ip6_addr *,  unshort, ip6_addr *,  unshort, int));
+extern   int   ip6_pcbconnect(struct inpcb * inp, struct mbuf *  nam);
+extern   void  ip6_pcbdisconnect(struct inpcb * inp);
+extern   void  ip6_setsockaddr(struct inpcb *, struct mbuf * nam);
+extern   void  ip6_setpeeraddr(struct inpcb *,struct mbuf *  nam);
+#endif   /* IP_V6 */
+
+
+#endif   /* _IN_PCB_H */
+
+/* end of file in_pcb.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/nptcp.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/nptcp.c
new file mode 100644
index 0000000..73f274a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/nptcp.c
@@ -0,0 +1,1623 @@
+/*
+ * FILENAME: nptcp.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * nptcp.c NetPort TCP layer's emulation of BSD routines called by 
+ * the TCP code. 
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: pffindtype(), pffindproto(), m_getnbuf(), m_free(), 
+ * ROUTINES: m_freem(), m_copy(), m_adj(), mbuf_len (), dtom(), remque (), 
+ * ROUTINES: insque(), nptcp_init(), tcp_rcv(), ip_output(), in_broadcast(), 
+ * ROUTINES: np_stripoptions(), tcp_stat(), tcp_bsdconnstat(), 
+ * ROUTINES: tcp_bsdsendstat(), tcp_bsdrcvstat(), mbuf_stat(), mbuf_list(), 
+ * ROUTINES: sock_list(), *search_mbuf_queue(), *socket_queue_name(), 
+ * ROUTINES: so_icmpdu(), tcp_tick(),
+ *
+ * PORTABLE: yes
+ *
+ * NOTE: CSUM_DEMO is used in this file to make some minor performance-
+ *       related code changes. These changes may or may not be needed
+ *       under normal circumstances.
+ */
+
+#include "ipport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "tcpport.h"
+#include "in_pcb.h"
+#include "ip.h"
+#include "icmp.h"
+#include "udp.h"
+#include "protosw.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+#ifdef IP_V6
+#include "socket6.h"
+#endif   /* IP_V6 */
+
+unshort  select_wait;      /* select wait bits */
+
+
+extern   unsigned lilbufs;
+extern   unsigned bigbufs;
+
+extern   int   ip_write(u_char prot, PACKET pkt);
+
+#ifdef INCLUDE_SNMP
+struct tcp_mib tcpmib;     /* mib stats for TCP layer */
+#else
+struct TcpMib  tcpmib;  /* mib stats for TCP layer */
+#endif
+
+#ifdef DO_DELAY_ACKS
+int tcp_fasttimo(void);
+#endif
+
+#ifdef TCP_MENUS
+#include "menu.h"
+extern struct menu_op tcpmenu[5];
+#endif   /* IN_MENUS */
+
+#ifdef TCP_WIN_SCALE
+/* default value for window scaling option */
+u_char default_wind_scale = 0;
+#endif   /* TCP_WIN_SCALE */
+
+int      TCPTV_MSL   = (30 * PR_SLOWHZ);  /* max seg lifetime default */
+
+/* protocol switch table entry, for TCP: */
+struct protosw tcp_protosw =  {
+   SOCK_STREAM,   
+   IPPROTO_TCP,
+   PR_CONNREQUIRED|PR_WANTRCVD,
+   tcp_input,
+#ifdef CTL_INPUT
+   tcp_ctlinput,
+#endif   /* CTL_INPUT */
+#ifdef CTL_OUTPUT
+   tcp_ctloutput,
+#endif
+   tcp_usrreq,
+   tcp_init,
+#ifdef DO_DELAY_ACKS
+   tcp_fasttimo,
+#endif
+   tcp_slowtimo,
+};
+
+#ifdef UDP_SOCKETS
+struct protosw udp_protosw =  {
+   SOCK_DGRAM,          /* type - datagram */
+   IPPROTO_UDP,         /* number (UDP over IP) */
+   PR_ATOMIC|PR_ADDR,   /* flags */
+   NULL,    /* input, not for us */
+#ifdef CTL_INPUT
+   NULL,
+#endif   /* CTL_INPUT */
+#ifdef CTL_OUTPUT
+   NULL,
+#endif
+   udp_usrreq, /* this is where all the real work happens */
+   NULL,    /* state-less UDP needs no init call */
+#ifdef DO_DELAY_ACKS
+   NULL,
+#endif
+   NULL,
+};
+#endif   /* UDP_SOCKETS */
+
+#ifdef IP_RAW
+struct protosw rawip_protosw =  {
+   SOCK_RAW,            /* type - raw */
+   IPPROTO_RAW,         /* number (raw IP) */
+   PR_ATOMIC|PR_ADDR,   /* flags */
+   NULL,                /* input, not for us */
+#ifdef CTL_INPUT
+   NULL,
+#endif   /* CTL_INPUT */
+#ifdef CTL_OUTPUT
+   NULL,
+#endif
+   rawip_usrreq,        /* this is where all the real work happens */
+   NULL,                /* state-less UDP needs no init call */
+#ifdef DO_DELAY_ACKS
+   NULL,
+#endif
+   NULL,
+};
+#endif   /* IP_RAW */
+
+#ifdef NET_STATS
+char *   tcpstates[] = 
+{
+   "CLOSED",
+   "LISTEN",
+   "SYN_SENT",
+   "SYN_RCVD",
+   "ESTABLISHED",
+   "CLOSE_WAIT",
+   "FIN_WAIT_1",
+   "CLOSING",
+   "LAST_ACK",
+   "FIN_WAIT_2",
+   "TIME_WAIT",
+};
+#endif   /* NET_STATS */
+
+
+
+/* FUNCTION: pffindtype()
+ * 
+ * PARAM1: int domain
+ * PARAM2: int type
+ *
+ * RETURNS: 
+ */
+
+struct protosw *  
+pffindtype(int domain, int type)
+{
+
+   /* check that the passed domain is vaid for the build */
+   if (domain != AF_INET)
+   {
+#ifdef IP_V6
+      if(domain != AF_INET6)
+#endif
+      {
+         dtrap();    /* programming error */
+         return NULL;
+      }
+   }
+
+   if (type == SOCK_STREAM)
+      return &tcp_protosw;
+#ifdef UDP_SOCKETS
+   else if(type == SOCK_DGRAM)
+      return &udp_protosw;
+#endif   /* UDP_SOCKETS */
+#ifdef IP_RAW
+   else if(type == SOCK_RAW)
+      return &rawip_protosw;
+#endif  /* IP_RAW */
+   else
+      return NULL;
+}
+
+
+
+/* FUNCTION: pffindproto()
+ * 
+ * PARAM1: int domain
+ * PARAM2: int protocol
+ * PARAM3: int type
+ *
+ * RETURNS: 
+ */
+
+struct protosw *  
+pffindproto(int domain, int protocol, int type)
+{
+#ifdef IP_RAW
+   if (type == SOCK_RAW)
+      return(pffindtype(domain, type));
+#endif
+
+   switch (protocol)
+   {
+#ifdef BSD_SOCKETS
+   case IPPROTO_TCP:
+      if (type == SOCK_STREAM)
+         break;
+      /* IPPROTO_TCP protocol on non-SOCK_STREAM type socket */
+      dtrap();
+      return NULL;
+   case IPPROTO_UDP:
+      if (type == SOCK_DGRAM)
+         break;
+      /* IPPROTO_UDP protocol on non-SOCK_DGRAM type socket */
+      dtrap();
+      return NULL;
+#endif /* BSD_SOCKETS */
+   case 0:
+      /* let protocol default based on socket type */
+      break;
+   default:
+      /* unknown/unsupported protocol on socket */
+      dtrap();
+      return NULL;
+   }
+   return(pffindtype(domain, type));   /* map to findtype */
+}
+
+struct mbstats {
+   u_long   allocs;
+   u_long   frees;
+}  mbstat;
+
+struct queue   soq;     /* A socket queue */
+struct queue   mbufq;   /* A netport queue for in-use mbufs */
+struct queue   mfreeq;  /* A netport queue for free mbufs */
+
+
+
+/* FUNCTION: m_getnbuf()
+ *
+ * m_getnbuf() - the sole mbuf get routine for this port. These no 
+ * version with a wait option. This gets a netport style nbuf to hold 
+ * the data & maps it into a structure designed to fool the BSD TCP 
+ * code into thinking it's an mbuf. 
+ *
+ * 
+ * PARAM1: int type
+ * PARAM2: int len
+ *
+ * RETURNS: 
+ */
+
+struct mbuf *  
+m_getnbuf(int type, int len)
+{
+   struct mbuf *  m;
+   PACKET pkt = NULL;
+
+#ifdef NPDEBUG
+   if (type < MT_RXDATA || type > MT_IFADDR)
+   {
+      dtrap(); /* is this OK? */
+   }
+#endif
+
+   /* if caller has data (len >= 0), we need to allocate 
+    * a packet buffer; else all we need is the mbuf */
+   if (len != 0)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pkt = pk_alloc(len + HDRSLEN);
+
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      if (!pkt)
+         return NULL;
+   }
+
+   m = (struct mbuf *)getq(&mfreeq);
+   if (!m)
+   {
+      if (pkt) 
+      {
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      }
+      return NULL;
+   }
+   m->m_type = type;
+   if (len == 0)
+   {
+      m->pkt = NULL;
+      m->m_base = NULL;    /* caller better fill these in! */
+      m->m_memsz = 0;
+   }
+   else
+   {
+      m->pkt = pkt;
+      /* set m_data to the part where tcp data should go */
+      m->m_base = m->m_data = pkt->nb_prot = pkt->nb_buff + HDRSLEN;
+      m->m_memsz = pkt->nb_blen - HDRSLEN;
+   }
+   m->m_len = 0;
+   m->m_next = m->m_act = NULL;
+   mbstat.allocs++;        /* maintain local statistics */
+   putq(&mbufq, (qp)m);
+   return m;
+}
+
+
+/* FUNCTION: m_free()
+ *
+ * m_free() frees mbufs allocated above. Retuns pointer to "next" 
+ * mbuf. 
+ *
+ * 
+ * PARAM1: struct mbuf * m
+ *
+ * RETURNS: 
+ */
+
+
+struct mbuf *  
+m_free(struct mbuf * m)
+{
+   struct mbuf *  nextptr;
+
+#ifdef NPDEBUG
+   if (mbufq.q_len < 1)
+      panic("mfree: q_len");
+
+   if (m->m_type < MT_RXDATA || m->m_type > MT_IFADDR)
+   {
+      if (m->m_type == MT_FREE)
+      {
+         dtrap(); /* debug double free of mbuf by tcp_in() */
+         return m->m_next; /* seems harmless, though.... */
+      }
+      else
+         panic("m_free: type");
+   }
+#endif   /* NPDEBUG */
+
+   nextptr = m->m_next;    /* remember value to return */
+
+   if (qdel(&mbufq, m) == NULL)
+      panic("m_free: missing");
+
+   m->m_type = MT_FREE;    /* this may seem silly, but helps error checking */
+
+   if (m->pkt)
+   {
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(m->pkt);     /* free up the netport buffer */
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   }
+   mbstat.frees++;
+   putq(&mfreeq, (qp)m);
+   return nextptr;
+}
+
+
+
+/* FUNCTION: m_freem()
+ *
+ *  m_freem() frees a list of mbufs
+ *
+ * 
+ * PARAM1: struct mbuf * m
+ *
+ * RETURNS: 
+ */
+
+void
+m_freem(struct mbuf * m)
+{
+   while (m != NULL)
+      m = m_free(m);
+}
+
+
+
+/* FUNCTION: m_copy()
+ *
+ * m_copy() - Make a copy of an mbuf chain starting "off" bytes from 
+ * the beginning, continuing for "len" bytes. If len is M_COPYALL, 
+ * copy to end of mbuf. Returns pointer to the copy. 
+ *
+ * 
+ * PARAM1: struct mbuf * m
+ * PARAM2: int off
+ * PARAM3: int len
+ *
+ * RETURNS: 
+ */
+
+struct mbuf *  
+m_copy(struct mbuf * m, int off, int len)
+{
+   struct mbuf *  nb, * head, *  tail;
+   int   tocopy;
+
+   if (len == 0)  /* nothing to do */
+      return NULL;
+
+#ifdef NPDEBUG
+   /* sanity test parms */
+   if (off < 0 || (len < 0 && len != M_COPYALL))
+   {
+      dtrap();
+      return NULL;
+   }
+#endif   /* NPDEBUG */
+
+   /* move forward through mbuf q to "off" point */
+   while (off > 0) 
+   {
+      if (!m)
+      {
+         dtrap();
+         return NULL;
+      }
+      if (off < (int)m->m_len)
+         break;
+      off -= m->m_len;
+      m = m->m_next;
+   }
+
+   head = tail = NULL;
+
+   while (len > 0)
+   {
+      if (m == NULL) /* at end of queue? */
+      {
+         panic("m_copy: bad len");
+         return NULL;
+      }
+      tocopy = (int)MIN(len, (int)(m->m_len - off));
+
+      /* mbuf data is expected to be aligned according to 
+       * ALIGN_TYPE, so if the offset isn't aligned, we must 
+       * copy the buffer instead of cloning it.
+       * Also, don't permit multiple clones; they sometimes
+       * lead to corrupted data.
+       */
+      if ((off & (ALIGN_TYPE - 1)) ||
+          (m->pkt->inuse != 1))
+      {
+         if ((nb = m_getwithdata (m->m_type, tocopy)) == NULL)
+            goto nospace;
+         MEMCPY(nb->m_data, m->m_data+off, tocopy);
+         nb->m_len = tocopy;  /* set length of data we just moved into new mbuf */
+
+         tcpstat.tcps_mcopies++;
+         tcpstat.tcps_mcopiedbytes += tocopy;
+      }
+      else
+      {
+         /* Rather than memcpy every mbuf's data, "clone" the data by 
+          * making a duplicate of the mbufs involved and bumping the 
+          * inuse count of the actual packet structs
+          */
+         if ((nb = m_getwithdata (m->m_type, 0)) == NULL)
+            goto nospace;
+
+         m->pkt->inuse++;     /* bump pkt use count to clone it */
+
+         /* set up new mbuf with pointers to cloned packet */
+         nb->pkt = m->pkt;
+         nb->m_base = m->m_base;
+         nb->m_memsz = m->m_memsz;
+         nb->m_data = m->m_data + off;
+         nb->m_len = tocopy;
+
+         tcpstat.tcps_mclones++;
+         tcpstat.tcps_mclonedbytes += tocopy;
+      }
+
+      len -= tocopy;
+      off = 0;
+      if (tail)      /* head & tail are set by first pass thru loop */
+         tail->m_next = nb;
+      else
+         head = nb;
+      tail = nb;     /* always make new mbuf the tail */
+      m = m->m_next;
+
+   }
+
+   return head;
+
+nospace:
+   m_freem (head);
+   return NULL;
+}
+
+
+
+
+/* FUNCTION: m_adj()
+ * 
+ * slice "length" data from the head of an mbuf
+ *
+ * PARAM1: struct mbuf * mp
+ * PARAM2: int len
+ *
+ * RETURNS: 
+ */
+
+void
+m_adj(struct mbuf * mp, int len)
+{
+   struct mbuf *  m;
+   int   count;
+
+   if ((m = mp) == NULL)
+      return;
+
+   if (len >= 0) 
+   {
+      while (m != NULL && len > 0) 
+      {
+         if (m->m_len <= (unsigned)len)
+         {
+            len -= m->m_len;
+            m->m_len = 0;
+            m = m->m_next;
+         }
+         else
+         {
+            m->m_len -= len;
+            m->m_data += len;
+            break;
+         }
+      }
+   } 
+   else
+   {
+      /*
+       * Trim from tail.  Scan the mbuf chain,
+       * calculating its length and finding the last mbuf.
+       * If the adjustment only affects this mbuf, then just
+       * adjust and return.  Otherwise, rescan and truncate
+       * after the remaining size.
+       */
+      len = -len;
+      count = 0;
+      for (;;) 
+      {
+         count += m->m_len;
+         if (m->m_next == (struct mbuf *)0)
+            break;
+         m = m->m_next;
+      }
+      if (m->m_len >= (unsigned)len)
+      {
+         m->m_len -= len;
+         return;
+      }
+      count -= len;
+      /*
+       * Correct length for chain is "count".
+       * Find the mbuf with last data, adjust its length,
+       * and toss data from remaining mbufs on chain.
+       */
+      for (m = mp; m; m = m->m_next)
+      {
+         if (m->m_len >= (unsigned)count)
+         {
+            m->m_len = count;
+            break;
+         }
+         count -= m->m_len;
+      }
+      while ((m = m->m_next) != (struct mbuf *)NULL)
+         m->m_len = 0;
+   }
+}
+
+
+/* FUNCTION: mbuf_len ()
+ * 
+ *   mbuf_len() - Compute the length of a chain of m_bufs.
+ *
+ * PARAM1: struct mbuf *m
+ *
+ * RETURNS: 
+ */
+
+int
+mbuf_len (struct mbuf * m)
+{
+   int   len   =  0;
+
+   while (m)
+   {
+      len += m->m_len;
+      m = m->m_next;
+   }
+   return len;
+}
+
+
+
+/* FUNCTION: dtom()
+ * 
+ * dtom() - given a data pointer, return the mbuf it's in.
+ *
+ * PARAM1: void * data
+ *
+ * RETURNS: 
+ */
+
+struct mbuf *  
+dtom(void * data)
+{
+   qp qptr;
+   struct mbuf *  m;
+
+   for (qptr = mbufq.q_head; qptr; qptr = qptr->qe_next)
+   {
+      m = (struct mbuf *)qptr;
+
+      if (IN_RANGE(m->m_base, m->m_memsz, (char*)data))
+         return (struct mbuf *)qptr;
+      else
+         continue;
+
+   }
+
+   panic("dtom");    /* data not found in any "in use" mbuf */
+   return NULL;
+}
+
+
+/* FUNCTION: remque ()
+ *
+ * remque() - Used for removing overlapping tcp segments from input 
+ * queue. Adapted from BSD/Mango, but "struct queue" conflicted with 
+ * NetPort struct; so it uses the a contrived BSDq structure. 
+ *
+ * 
+ * PARAM1: void *arg
+ *
+ * RETURNS: 
+ */
+
+struct bsdq {
+   struct bsdq *  next; /* for overlaying on ipovly, et.al. */
+   struct bsdq *  prev;
+};
+
+
+void
+remque (void * arg)
+{
+   struct bsdq *  old;
+
+   old = (struct bsdq *)arg;
+   if (!old->prev) return;
+      old->prev->next = old->next;
+   if (old->next)
+      old->next->prev = old->prev;
+}
+
+
+
+/* FUNCTION: insque()
+ * 
+ * PARAM1: void * n
+ * PARAM2: void * p
+ *
+ * RETURNS: 
+ */
+
+void
+insque(void * n, void * p)
+{
+   struct bsdq *  newe, *  prev;
+
+   newe = (struct bsdq *)n;
+   prev = (struct bsdq *)p;
+   newe->next = prev->next;
+   newe->prev = prev;
+   prev->next = newe;
+   if (newe->next)
+      newe->next->prev = newe;
+}
+
+
+/* FUNCTION: nptcp_init()
+ *
+ * nptcp_init() - set up TCP to run. This assumes netport IP, packet 
+ * quques, interfaces, et.al., are already up. This routine is called 
+ * by the port file, which should already have done port specific 
+ * setup, does NetPort TCP general setup, and then calls tcp_init() 
+ * to do BSD TCP generic setup. 
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: Returns 0 if OK, else non-zero error code. 
+ */
+
+int
+nptcp_init()
+{
+   int   i;
+   /* total netport buffers:
+    * Get twice the number of packet buffers plus 3, to help
+    * support UDP. if you are receiving UDP packets faster
+    * than your UDP server can process them, its possible for 
+    * all of your packet buffers to end up in the UDP socket's 
+    * receive queue. each of these packet buffers has associated with 
+    * it 2 mbufs, one for the packet buffer itself and one for the 
+    * address of the remote host that the packet came from. in order 
+    * for this socket queue to get emptied and the receive buffers to 
+    * get freed, the socket has to be read and what's the first thing 
+    * that soreceive() does to try to do this? it tries to allocate 
+    * an mbuf, so if you only have twice as many mbufs as packet 
+    * buffers, soreceive() can't complete and the packet buffers stay 
+    * on the queue, so we allocate 3 extra mbufs in the hope that 
+    * this will allow soreceive() to complete and free up the packet 
+    * buffers. yes, its kind of an ugly hack and 3 is a wild guess.
+    */
+   unsigned bufcount = (lilbufs + bigbufs) * 2 + 3;
+   struct mbuf *  m; /* scratch mbuf for mfreeq init */
+
+   MEMSET(&soq, 0, sizeof(soq));    /* Set socket queue to NULLs */
+   MEMSET(&mbufq, 0, sizeof(mbufq));
+   MEMSET(&mfreeq, 0, sizeof(mfreeq));
+   for (i = 0; i < (int)bufcount; i++)
+   {
+      m = MBU_ALLOC(sizeof(struct mbuf));
+      if (!m)  /* malloc error, bail out */
+         panic("tcpinit");
+      m->m_type = MT_FREE;
+      m->m_len = 0;
+      m->m_data = NULL;
+      putq(&mfreeq, (qp)m);
+   }
+   mfreeq.q_min = (int)bufcount;   /* this should match q_max and q_len */
+
+#ifdef INCLUDE_SNMP                /* SNMP initialization */
+   tcpmib.tcpRtoAlgorithm = 4;     /* Van Jacobson's algorithm */
+   tcpmib.tcpRtoMin = TCPTV_MIN * 1000;      /* PR_SLOWHZ */
+   tcpmib.tcpRtoMax = TCPTV_REXMTMAX * 1000; /* PR_SLOWHZ */
+#endif
+
+   tcp_init();    /* call the BSD init in tcp_usr.c */
+
+#ifdef TCP_MENUS
+   install_menu(&tcpmenu[0]);
+#endif   /* IN_MENUS */
+
+   return 0;   /* good return */
+}
+
+
+/* FUNCTION: tcp_rcv()
+ *
+ * tcp_rcv(PACKET pkt) - called from IP stack whenever it receives a 
+ * TCP packet. data is passed in a NetPort netbuf structure. Returns 
+ * 0 if packet was processed succesfully, ENP_NOT_MINE if not for me, 
+ * or a negative error code if packet was badly formed. In practice, 
+ * the return value is usually ignored. 
+ *
+ * 
+ * PARAM1: PACKET pkt
+ *
+ * RETURNS: 
+ */
+
+#ifdef IP_V4
+ 
+int
+tcp_rcv(PACKET pkt)     /* NOTE: pkt has nb_prot pointing to IP header */
+{
+   struct mbuf *  m_in;
+   struct ip * bip;  /* IP header, berkeley version */
+   struct tcphdr *   tcpp;
+   unshort  len;  /* scratch length holder */
+
+   /* For TCP, the netport IP layer is modified to set nb_prot to the 
+    * start of the IP header (not TCP). We need to do some further
+    * mods which the BSD code expects:
+    */
+   bip = (struct ip *)pkt->nb_prot;    /* get ip header */
+   len = ntohs(bip->ip_len);  /* get length in local endian */
+
+   /* verify checksum of received packet */
+
+   tcpp = (struct tcphdr *)ip_data(bip);
+   if (tcp_cksum(bip) != tcpp->th_sum)
+   {
+      TCP_MIB_INC(tcpInErrs);    /* keep MIB stats */
+      tcpstat.tcps_rcvbadsum++;  /* keep BSD stats */
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);  /* punt packet */
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_BAD_HEADER;
+   }
+
+   m_in = m_getnbuf(MT_RXDATA, 0);
+   if (!m_in){
+      LOCK_NET_RESOURCE(FREEQ_RESID);
+      pk_free(pkt);
+      UNLOCK_NET_RESOURCE(FREEQ_RESID);
+      return ENP_RESOURCE;  
+   }
+
+   IN_PROFILER(PF_TCP, PF_ENTRY);      /* measure time in TCP */
+
+   /* subtract IP header length from total IP packet length */
+   len -= ((unshort)(bip->ip_ver_ihl & 0x0f) << 2);
+   bip->ip_len = len;   /* put TCP length in struct for TCP code to use */
+
+   /* set mbuf to point to start of IP header (not TCP) */
+   m_in->pkt = pkt;
+   m_in->m_data = pkt->nb_prot;
+   m_in->m_len = pkt->nb_plen;
+   m_in->m_base = pkt->nb_buff;     /* ??? */
+   m_in->m_memsz = pkt->nb_blen;    /* ??? */
+
+   tcp_input(m_in, pkt->net);
+
+   IN_PROFILER(PF_TCP, PF_EXIT);      /* measure time in TCP */
+
+   return 0;
+}
+
+
+/* FUNCTION: ip_output()
+ *
+ * ip_output() - called by tcp_output() to send a tcp segment on the 
+ * IP layer. We convert the mbufs passed into a PACKET, set a few 
+ * things up for NetPort IP, and pass it on down. Returns 0 if no 
+ * error, negative "NP" error if lower layers fail, postive error 
+ * from nptcp.h if TCP/Sockets fails. 
+ *
+ * 
+ * PARAM1: struct mbuf * data
+ *
+ * RETURNS: 
+ */
+
+int
+ip_output(struct mbuf * data, struct   ip_socopts * so_optsPack) /* mbuf chain with data to send */
+{
+   struct ip * bip;
+   struct tcphdr *   tcpp;
+   PACKET pkt;
+   struct mbuf *  m1, * m2, * mtmp; /* temp mbuf pointers */
+   int   e;    /* error holder */
+   int   total;
+
+   /* reassemble mbufs into a contiguous packet. Do this with as 
+    * little copying as possible. Typically the mbufs will be either 
+    * 1) a single mbuf with iptcp header info only (e.g.tcp ACK 
+    * packet), or 2) iptcp header with data mbuf chained to it, or 3) 
+    * #2) with a tiny option data mbuf between header and data. 
+    */
+   if ((data->m_next))
+   {
+      m1 = data;
+      m2 = data->m_next;
+
+      /* If m2 is small (e.g. options), copy it to m1 and free it */
+      while (m2 && (m2->m_len < 10))
+      {
+         pkt = m1->pkt;
+         if ((pkt->nb_buff + pkt->nb_blen) > /* make sure m2 will fit in m1 */
+             (m1->m_data + m1->m_len + m2->m_len))
+         {
+            MEMCPY((m1->m_data + m1->m_len), m2->m_data, m2->m_len);
+            m1->m_len += m2->m_len;
+            m1->m_next = m2->m_next;
+            m_free(m2);    /* free this m2.... */
+            m2 = m1->m_next;  /* ...and thread the next one */
+            tcpstat.tcps_oappends++;
+         }
+         else     /* if won't fit, fall to next copy */
+            break;
+      }
+
+      while (m2)  /* If we still have two or more buffers, more copying: */
+      {
+         /* try prepending m1 to m2, first see if it fits: */
+         e = m2->m_data - m2->pkt->nb_buff;  /* e is prepend space */
+         if (e < MaxLnh)
+         { 
+#ifdef NPDEBUG
+            dprintf("nptcp: MaxLnh:%d, e:%d\n", MaxLnh, e);
+#endif
+            panic("tcp_out:mbuf-nbuf");   /* sanity check */
+         }
+
+         if ((m1->m_len < (unsigned)(e - MaxLnh))  /* leave room for MAC */
+             && ((m1->m_len & (ALIGN_TYPE - 1)) == 0)  /* and stay aligned */
+             && ((m2->m_data - m2->pkt->nb_buff) == HDRSLEN))   /* be at start */
+         {
+            MEMCPY((m2->m_data - m1->m_len), m1->m_data, m1->m_len);
+            m2->m_data -= m1->m_len;   /* fix target to reflect prepend */
+            m2->m_len += m1->m_len;
+            m_free(m1);    /* free head (copied) mbuf */
+            data = m1 = m2;   /* move other mbufs up the chain */
+            m2 = m2->m_next;  /* loop to while(m2) test */
+            tcpstat.tcps_oprepends++;
+         }
+         else     /* if won't fit, fall to next copy */
+            break;
+      }
+
+      if (m2)  /* If all else fails, brute force copy: */
+      {
+         total = 0;
+         for (mtmp = m1; mtmp; mtmp = mtmp->m_next)
+            total += mtmp->m_len;
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pkt = pk_alloc(total + HDRSLEN);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         if (!pkt)
+            return ENOBUFS;
+         pkt->nb_prot = pkt->nb_buff + MaxLnh;
+
+         mtmp = m1;
+         while (mtmp)
+         {
+            MEMCPY(pkt->nb_prot, mtmp->m_data, mtmp->m_len);
+            pkt->nb_prot += mtmp->m_len;
+            pkt->nb_plen += mtmp->m_len;
+            m2 = mtmp;
+            mtmp = mtmp->m_next;
+            if (m2 != data)   /* save original head */
+               m_free(m2);
+            tcpstat.tcps_ocopies++;
+         }
+         pkt->nb_prot -= total;     /* fix data pointer */
+
+         /* release the original mbufs packet install the new one */
+         LOCK_NET_RESOURCE(FREEQ_RESID);
+         pk_free(data->pkt);
+         UNLOCK_NET_RESOURCE(FREEQ_RESID);
+         data->pkt = pkt;
+         data->m_len = pkt->nb_plen;
+         data->m_next = NULL;
+         data->m_data = pkt->nb_prot;
+         data->m_len = total;
+      }
+   }
+
+   if ((data->m_data < (data->pkt->nb_buff + MaxLnh)))
+      panic("ip_output: overflow");
+
+   pkt = data->pkt;
+
+   /* do we have options? */
+   if (so_optsPack)
+	   pkt->soxopts = so_optsPack;   /* yup */
+#ifdef IP6_ROUTING
+   else
+   {
+      panic("ip_output: no so_optsPack for the IPv6 scope");     
+   }
+#endif
+
+   /* fill in dest host for IP layer */
+   bip = (struct ip *)data->m_data;
+   pkt->fhost = bip->ip_dest;
+
+   /* make enough IP header for cksum calculation */
+   bip->ip_ver_ihl = 0x45;
+   bip->ip_len = htons(bip->ip_len);   /* make net endian for calculation */
+   tcpp = (struct tcphdr *)ip_data(bip);
+#ifdef CSUM_DEMO
+   if (!(tcpp->th_flags & TH_SYN))
+   tcpp->th_flags |= TH_PUSH;     /* force the PSH flag in TCP hdr */
+#endif
+   tcpp->th_sum = tcp_cksum(bip);
+
+   pkt->nb_prot = (char*)(bip + 1);    /* point past IP header */
+   pkt->nb_plen = data->m_len - sizeof(struct ip);
+
+   e = ip_write(IPPROTO_TCP, pkt);
+
+   /* ip_write() is now responsable for data->pkt, so... */
+   data->pkt = NULL;
+   m_freem(data);
+
+   if (e < 0)
+   {
+      /* don't report dropped sends, it causes socket applications to 
+      bail when a TCP retry will fix the problem */
+      if (e == SEND_DROPPED)
+         return 0;
+      return e;
+   }
+   else
+      return 0;
+}
+#endif   /* IP_V4 */
+
+
+
+/* FUNCTION: in_broadcast()
+ *
+ * Determine if the passed IP address is a braodcast or not.
+ * Currently no support for subnet broadcasts.
+ *
+ * PARAM1: u_long ipaddr
+ *
+ * RETURNS: TRUE if broadcast, else FALSE
+ */
+
+int
+in_broadcast(u_long ipaddr)   /* passed in net endian */
+{
+   if (ipaddr == 0xffffffff)
+      return TRUE;
+
+   return FALSE;
+}
+
+
+/* FUNCTION: np_stripoptions()
+ *
+ * np_stripoptions - This replaces BSD ip_stripoptions. The 
+ * functionality is slightly different. Called from tcp_in.c 
+ *
+ * 
+ * PARAM1: struct ip * ti
+ * PARAM2: struct mbuf * m
+ *
+ * RETURNS: void
+ */
+
+void
+np_stripoptions(struct ip * ti, struct mbuf * m)
+{
+   int   ihlen;
+
+   /* get the IP header length in octets */
+   ihlen = (ti->ip_ver_ihl & 0x0f) << 2;
+
+   /* if it's <= 20 octets, there are no IP header options to strip */
+   if (ihlen <= 20)
+      return;
+
+   /* figure out how much to strip: we want to keep the 20-octet IP header */
+   ihlen -= 20;
+
+   /* remove the stripped options from the IP datagram length */
+   ti->ip_len -= ihlen;
+
+   /* and from the IP header length (which will be 5*4 octets long) */
+   ti->ip_ver_ihl = (ti->ip_ver_ihl & 0xf0) | 5;
+
+   /* move the 20-octet IP header up against the IP payload */
+   MEMMOVE( ((char*)ti) + ihlen, ti, 20);
+   m->m_len -= ihlen;
+   m->m_data += ihlen;
+}
+
+
+#ifdef NET_STATS
+#ifdef BSDTCP_STATS
+
+/* FUNCTION: tcp_stat()
+ *
+ * The next few routines pretty-print stats. #define-ing ns_printf 
+ * away will minmize space at the expense of utility. They support
+ * many ancient (but sometimes still usefull) BSD counters.
+ *
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+tcp_stat(void * pio)
+{
+   /* MIB-2 tcp group counters */ 
+   ns_printf(pio,"tcpRtoAlgorithm %lu,\ttcpRtoMin %lu\n",
+    tcpmib.tcpRtoAlgorithm, tcpmib.tcpRtoMin);
+   ns_printf(pio,"tcpRtoMax %lu,\ttcpMaxConn %lu\n",
+    tcpmib.tcpRtoMax, tcpmib.tcpMaxConn);
+   ns_printf(pio,"tcpActiveOpens %lu,\ttcpPassiveOpens %lu\n",
+    tcpmib.tcpActiveOpens, tcpmib.tcpPassiveOpens);
+   ns_printf(pio,"tcpAttemptFails %lu,\ttcpEstabResets %lu\n",
+    tcpmib.tcpAttemptFails, tcpmib.tcpEstabResets);
+   ns_printf(pio,"tcpCurrEstab %lu,\ttcpInSegs %lu\n",
+    tcpmib.tcpCurrEstab, tcpmib.tcpInSegs);
+   ns_printf(pio,"tcpOutSegs %lu,\ttcpRetransSegs %lu\n",
+    tcpmib.tcpOutSegs, tcpmib.tcpRetransSegs);
+   ns_printf(pio,"tcpInErrs %lu,\ttcpOutRsts %lu\n",
+    tcpmib.tcpInErrs, tcpmib.tcpOutRsts);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: tcp_bsdconnstat()
+ *
+ * BSD connection statistics
+ *
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+tcp_bsdconnstat(void * pio)
+{
+   ns_printf(pio,"connections initiated: %lu,\tconnections accepted: %lu\n",
+    tcpstat.tcps_connattempt, tcpstat.tcps_accepts);
+   ns_printf(pio,"connections established: %lu,\tconnections dropped: %lu\n",
+    tcpstat.tcps_connects, tcpstat.tcps_drops);
+   ns_printf(pio,"embryonic connections dropped: %lu,\tconn. closed (includes drops): %lu\n",
+    tcpstat.tcps_conndrops, tcpstat.tcps_closed);
+   ns_printf(pio,"segs where we tried to get rtt: %lu,\ttimes we succeeded: %lu\n",
+    tcpstat.tcps_segstimed, tcpstat.tcps_rttupdated);
+   ns_printf(pio,"delayed acks sent: %lu,\tconn. dropped in rxmt timeout: %lu\n",
+    tcpstat.tcps_delack, tcpstat.tcps_timeoutdrop);
+   ns_printf(pio,"retransmit timeouts: %lu,\tpersist timeouts: %lu\n",
+    tcpstat.tcps_rexmttimeo, tcpstat.tcps_persisttimeo);
+   ns_printf(pio,"keepalive timeouts: %lu,\tkeepalive probes sent: %lu\n",
+    tcpstat.tcps_keeptimeo, tcpstat.tcps_keepprobe);
+#ifdef TCP_SACK
+   ns_printf(pio,"sack connections: %lu,\tconns dropped in keepalive: %lu\n",
+      tcpstat.tcps_sackconn, tcpstat.tcps_keepdrops);
+#else
+   ns_printf(pio,"conns dropped in keepalive: %lu\n",
+      tcpstat.tcps_keepdrops);
+#endif   /* TCP_SACK */
+
+   return 0;
+}
+
+
+
+
+/* FUNCTION: tcp_bsdsendstat()
+ * 
+ * BSD TCP send stats
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+tcp_bsdsendstat(void * pio)
+{
+
+   ns_printf(pio,"total packets sent: %lu,\tdata packets sent: %lu\n",
+    tcpstat.tcps_sndtotal, tcpstat.tcps_sndpack);
+   ns_printf(pio,"data bytes sent: %lu,\tdata packets retransmitted: %lu\n",
+    tcpstat.tcps_sndbyte, tcpstat.tcps_sndrexmitpack);
+   ns_printf(pio,"data bytes retransmitted: %lu,\tack-only packets sent: %lu\n",
+    tcpstat.tcps_sndrexmitbyte, tcpstat.tcps_sndacks);
+   ns_printf(pio,"window probes sent: %lu,\tpackets sent with URG only: %lu\n",
+    tcpstat.tcps_sndprobe, tcpstat.tcps_sndurg);
+   ns_printf(pio,"window update-only packets sent: %lu,\tcontrol (SYN|FIN|RST) packets sent: %lu\n",
+    tcpstat.tcps_sndwinup, tcpstat.tcps_sndctrl);
+#ifdef TCP_SACK
+   ns_printf(pio,"sack hdrs sent: %lu,\tsack based data resends: %lu\n",
+    tcpstat.tcps_sacksent, tcpstat.tcps_sackresend);
+#endif   /* TCP_SACK */
+
+   return 0;
+}
+
+
+
+/* FUNCTION: tcp_bsdrcvstat()
+ *
+ *  BSD TCP receive stats
+ *
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+tcp_bsdrcvstat(void * pio)
+{
+   ns_printf(pio,"total packets received: %lu,\tpackets received in sequence: %lu\n",
+    tcpstat.tcps_rcvtotal, tcpstat.tcps_rcvpack);
+   ns_printf(pio,"bytes received in sequence: %lu,\tpackets received with ccksum errs: %lu\n",
+    tcpstat.tcps_rcvbyte, tcpstat.tcps_rcvbadsum);
+   ns_printf(pio,"packets received with bad offset: %lu,\tpackets received too short: %lu\n",
+    tcpstat.tcps_rcvbadoff, tcpstat.tcps_rcvshort);
+   ns_printf(pio,"duplicate-only packets received: %lu,\tduplicate-only bytes received: %lu\n",
+    tcpstat.tcps_rcvduppack, tcpstat.tcps_rcvdupbyte);
+   ns_printf(pio,"packets with some duplicate data: %lu,\tdup. bytes in part-dup. packets: %lu\n",
+    tcpstat.tcps_rcvpartduppack, tcpstat.tcps_rcvpartdupbyte);
+   ns_printf(pio,"out-of-order packets received: %lu,\tout-of-order bytes received: %lu\n",
+    tcpstat.tcps_rcvoopack, tcpstat.tcps_rcvoobyte);
+   ns_printf(pio,"packets with data after window: %lu,\tbytes rcvd after window: %lu\n",
+    tcpstat.tcps_rcvpackafterwin, tcpstat.tcps_rcvbyteafterwin);
+   ns_printf(pio,"packets rcvd after close: %lu,\trcvd window probe packets: %lu\n",
+    tcpstat.tcps_rcvafterclose, tcpstat.tcps_rcvwinprobe);
+   ns_printf(pio,"rcvd duplicate acks: %lu,\trcvd acks for unsent data: %lu\n",
+    tcpstat.tcps_rcvdupack, tcpstat.tcps_rcvacktoomuch);
+   ns_printf(pio,"rcvd ack packets: %lu,\tbytes acked by rcvd acks: %lu\n",
+    tcpstat.tcps_rcvackpack, tcpstat.tcps_rcvackbyte);
+   ns_printf(pio,"rcvd window update packets: %lu\n", tcpstat.tcps_rcvwinupd);
+   ns_printf(pio,"rcvd predictive header hits; acks:%lu, data:%lu\n",
+    tcpstat.tcps_predack, tcpstat.tcps_preddat);
+#ifdef TCP_SACK
+   ns_printf(pio,"sack hdrs recv: %lu,\tmax sack blocks in hdr: %lu\n",
+    tcpstat.tcps_sackrcvd, tcpstat.tcps_sackmaxblk);
+#endif   /* TCP_SACK */
+
+   return 0;
+}
+
+#endif   /* BSDTCP_STATS */
+
+
+
+/* FUNCTION: mbuf_stat()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 0
+ */
+
+int
+mbuf_stat(void * pio)
+{
+   ns_printf(pio,"mfreeq: head:%p, tail:%p, len:%d, min:%d, max:%d\n",
+    (void*)mfreeq.q_head, (void*)mfreeq.q_tail, 
+    mfreeq.q_len, mfreeq.q_min, mfreeq.q_max);
+
+   ns_printf(pio,"mbufq: head:%p, tail:%p, len:%d, min:%d, max:%d\n",
+    (void*)mbufq.q_head, (void*)mbufq.q_tail, 
+    mbufq.q_len, mbufq.q_min, mbufq.q_max);
+
+   ns_printf(pio,"mbuf allocs: %lu, frees: %lu\n", mbstat.allocs, mbstat.frees);
+
+   ns_printf(pio,"m_copy copies: %lu, copied bytes: %lu\n", 
+    tcpstat.tcps_mcopies, tcpstat.tcps_mcopiedbytes);
+   ns_printf(pio,"m_copy clones: %lu, cloned bytes: %lu\n",
+    tcpstat.tcps_mclones, tcpstat.tcps_mclonedbytes);
+
+   ns_printf(pio,"ip_output appends: %lu, prepends: %lu, copies: %lu\n",
+    tcpstat.tcps_oappends, tcpstat.tcps_oprepends, 
+    tcpstat.tcps_ocopies);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: mbuf_list()
+ * 
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+mbuf_list(void * pio)
+{
+   struct mbuf *  mb;
+
+   ns_printf(pio,"mbufs in use: \n");
+   for (mb = (struct mbuf *)mbufq.q_head; mb; mb = mb->next)
+      ns_printf(pio,"type %d, pkt:%lx, data:%lx, len:%d\n",
+    mb->m_type, mb->pkt, mb->m_data, mb->m_len);
+   return 0;
+}
+
+
+
+extern int udpsock_list(void * pio);
+
+/* FUNCTION: sock_list()
+ * 
+ * Display information about all the existing TCP and UDP sockets.
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS:  0 if successfull, else error code.
+ */
+
+int
+sock_list(void * pio)
+{
+   struct inpcb * inp;
+   struct socket *   so;
+   struct tcpcb * tp;
+
+   if (tcb.inp_next == NULL)
+   {
+      ns_printf(pio,"No TCP sockets\n");
+      return 0;
+   }
+
+   ns_printf(pio,
+    "TCP sock, fhost,     ports,    opts, rxbytes, txbytes, snd_una, snd_nxt, state:\n");
+   for (inp = tcb.inp_next; inp != &tcb; inp = inp->inp_next) 
+   {
+      tp = intotcpcb(inp);
+      so = inp->inp_socket;
+      if (!so)
+      {
+         ns_printf(pio,"No socket\n");
+         continue;
+      }
+
+#ifdef IP_V4
+      if(so->so_domain == AF_INET)
+      ns_printf(pio,"%lx,  %u.%u.%u.%u", so, PUSH_IPADDR(inp->inp_faddr.s_addr));
+#endif
+#ifdef IP_V6
+      if(so->so_domain == AF_INET6)
+      {
+         char  ip6buf[46];
+         ns_printf(pio,"%lx,  %s(v6), ", so, print_ip6(&inp->ip6_faddr, &ip6buf[0]));
+      }
+#endif   /* IP_V6 */
+
+      ns_printf(pio,", %u->%u, ", htons(inp->inp_lport), htons(inp->inp_fport));
+      ns_printf(pio,"0x%x, %u, %u, %ld, %ld, ", (unsigned)so->so_options,
+       (unsigned)so->so_rcv.sb_cc,(unsigned)so->so_snd.sb_cc,
+       tp->snd_una, tp->snd_nxt);
+      if ((tp->t_state < 0) || 
+          (tp->t_state >= sizeof(tcpstates)/sizeof(tcpstates[0])))
+         ns_printf(pio, "???\n");
+      else
+         ns_printf(pio, "%s\n", tcpstates[tp->t_state]);
+   }
+
+   return udpsock_list(pio);
+}
+
+
+
+/* FUNCTION: *search_mbuf_queue()
+ *
+ * this function searches the mbuf queue headed by mbuf for an mbuf 
+ * containing the PACKET structure addressed by pkt. 
+ *
+ * 
+ * PARAM1: struct mbuf *mbuf
+ * PARAM2: PACKET pkt
+ *
+ * RETURNS: 
+ */
+
+struct mbuf * search_mbuf_queue(struct mbuf * mbuf, PACKET pkt)
+{
+   for ( ; mbuf; mbuf = mbuf->next)
+   {
+      if (mbuf->pkt == pkt)
+         return mbuf;
+   }
+   return 0;
+}
+
+
+/* FUNCTION: *socket_queue_name()
+ *
+ * this function checks to see if the passed in PACKET structure is 
+ * in one of the socket queues. returns a pointer to name describing 
+ * what queue the PACKET structure 
+ *
+ * 
+ * PARAM1: PACKET pkt
+ *
+ * RETURNS: 
+ */
+
+char * socket_queue_name(PACKET pkt)
+{
+   struct inpcb * inp;
+   struct socket *   so;
+
+   /* no sockets to search thru */
+   if (tcb.inp_next == NULL)
+   {
+      return 0;
+   }
+
+   /* for each control block */
+   for (inp = tcb.inp_next; inp != &tcb; inp = inp->inp_next) 
+   {
+      /* get the associated socket */
+      so = inp->inp_socket;
+      /* if there is an associate socket */
+      if (so)
+      {
+         /* check to see if the pkt is in the rcv mbuf queue */
+         if (search_mbuf_queue(so->so_rcv.sb_mb,pkt))
+            return "sor";
+         /* check to see if the pkt is in the send mbuf queue */
+         if (search_mbuf_queue(so->so_snd.sb_mb,pkt))
+            return "snd";
+      }
+   }
+   /* not found in any socket queue */
+   return 0;
+}
+
+#endif   /* NET_STATS */
+
+
+/* FUNCTION: so_icmpdu()
+ *
+ * so_icmpdu() - Called from NetPort UDP layer whenever it gets a 
+ * ICMP destination unreachable packet (and is linked with this 
+ * sockets layer) Tries to find the offending socket, notify caller, 
+ * and shut it down. 
+ *
+ * 
+ * PARAM1: PACKET p
+ * PARAM2: struct destun * pdp
+ *
+ * RETURNS: 
+ */
+
+void
+so_icmpdu(PACKET p, struct destun * pdp)
+{
+   ip_addr lhost;    /* IP address of originator (our iface) */
+   ip_addr fhost;    /* IP address we sent to */
+   unshort  fport;   /* TCP/UDP port we sent to */
+   unshort  lport;   /* TCP/UDP port we sent from */
+   struct inpcb * inp;
+   struct socket *   so;
+   struct tcpcb * tp;
+
+   /* extract information about packet which generated DU */
+   fhost = htonl(pdp->dip.ip_dest);
+   lhost = htonl(pdp->dip.ip_src);
+   lport = htons(*(unshort*)(&pdp->ddata[0]));
+   fport = htons(*(unshort*)(&pdp->ddata[2]));
+
+#ifndef IP_PMTU
+   /* if it's a datagram-too-big message, ignore it -- As the
+    * build isn't using PMTU Discovery this packet is most 
+    * probably a Denial of Service Attack.
+    */
+    if(pdp->dcode == DSTFRAG)
+    {
+       goto done;
+    }
+#endif   /* IP_PMTU */
+
+   /* if it's a TCP connection, clean it up */
+   if (pdp->dip.ip_prot == TCPTP)
+   {
+      /* find associated data structs and socket */
+      inp = in_pcblookup(&tcb, fhost, fport, lhost, lport, INPLOOKUP_WILDCARD);
+      if (inp == 0)
+         goto done;
+      so = inp->inp_socket;
+      if (so == 0)
+         goto done;
+      tp = intotcpcb(inp);
+      if (tp)
+      {
+         if (tp->t_state <= TCPS_LISTEN)
+         {
+            goto done;
+         }
+
+#ifdef ICMP_TCP_DOS
+         {
+         struct ip * pip;
+         struct tcpiphdr * ti;
+
+         pip = ip_head(p);  /* find IP header */
+         ti = (struct tcpiphdr *)p->nb_prot;
+
+         if(!((tp->snd_una <=  ti->ti_seq) && (ti->ti_seq <= tp->snd_nxt)))
+            goto done;
+
+         /* If we get an ICMP Type 3 (Destination Unreachable) - Code 2
+          * (Protocol Unreachable) message and during the life of a TCP
+          * connection, then its most probably a Denial of Service Attack.
+          * As the only other interpretation would be that the support for
+          * the transport protocol has been removed from the host sending
+          * the error message during the life of the corresponding 
+          * connection. As in common practice this is higly unlikely in most
+          * cases, we will treat this message as a DOS attack.
+          */
+         if(pdp->dcode == DSTPROT)
+         {
+            if((tp->t_state >= TCPS_ESTABLISHED) && (tp->t_state <= TCPS_TIME_WAIT))
+               goto done;
+         }
+
+        /* Note some ICMP error messages generated by intermediate routers,
+         * include more than the recommended 64 bits of the IP Data. If the
+         * TCP ACK number happens to be present then use it in detecting a
+         * Denial of Service attack.
+         *
+         * This way we can ensure that the TCP Acknowledgement number should
+         * correspond to data that have already been acknowledged. This way
+         * we can further reduce the possiblity of considering a spoofed ICMP
+         * packet by a factor of 2.
+         */
+        if(pip->ip_len >= 32)
+        {
+            if(!(ti->ti_seq <= tp->rcv_nxt))
+               goto done;
+        }
+   }
+#endif
+
+         tcp_close(tp);
+      }
+      so->so_error = ECONNREFUSED;  /* set error for socket owner */
+   }   
+#ifdef UDP_SOCKETS   /* this sockets layer supports UDP too */
+   else if(pdp->dip.ip_prot == UDP_PROT)
+   {
+      UDPCONN tmp;
+      /* search udp table (which keeps hosts in net endian) */
+      for (tmp = firstudp; tmp; tmp = tmp->u_next)
+         if ((tmp->u_fport == fport || tmp->u_fport == 0) &&
+             (tmp->u_fhost == htonl(fhost)) &&
+             (tmp->u_lport == lport))
+         {
+            break;   /* found our UDP table entry */
+         }
+      if (!tmp) 
+         goto done;
+      so = (struct socket *)tmp->u_data;
+      /* May be non-socket (lightweight) UDP connection. */
+      if (so->so_type != SOCK_DGRAM)
+         goto done;
+      so->so_error = ECONNREFUSED;  /* set error for socket owner */
+      /* do a select() notify on socket here */
+      sorwakeup(so);
+      sowwakeup(so);
+   }
+#endif   /* UDP_SOCKETS */
+   else
+      goto done;
+
+#ifdef IP_PMTU
+   /* if this is a datagram-too-big message, update the Path MTU cache */
+   if (pdp->dcode == DSTFRAG)
+      pmtucache_set(pdp->dip.ip_dest, htons(pdp->dno2));
+#endif   /* IP_PMTU */
+
+done:
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p); /* done with original packet */
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   return;
+}
+
+
+/* FUNCTION: tcp_tick()
+ *
+ * tcp_tick() - Run the tcp timers. This should be called at least 
+ * TPS times per second. 
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+unsigned long nextslow = 0L;     /* next slow tcp timer time */
+static int in_tcptick = 0;       /* reentry gaurd */
+
+void
+tcp_tick()
+{
+   /* guard against re-entry */
+   if (in_tcptick)
+      return;
+   in_tcptick++;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   if (cticks >= nextslow) /* time to do it again */
+   {
+      tcp_slowtimo();      /* call routine in BSD tcp_timr.c */
+#ifdef CSUM_DEMO
+      nextslow = cticks + (TPS/5);  /* another 200 ms */
+#else
+      nextslow = cticks + (TPS/2);  /* another 500 ms */
+#endif
+   }
+
+#ifdef DO_DELAY_ACKS
+   tcp_fasttimo();
+#endif   /* DO_DELAY_ACKS */
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   in_tcptick--;
+}
+
+
+#endif /* INCLUDE_TCP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/protosw.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/protosw.h
new file mode 100644
index 0000000..bce5ab4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/protosw.h
@@ -0,0 +1,239 @@
+/*
+ * FILENAME: protosw.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ * Protocol switch table.
+ *
+ * Each protocol has a handle initializing one of these structures,
+ * which is used for protocol-protocol and system-protocol communication.
+ *
+ * A protocol is called through the pr_init entry before any other.
+ * Thereafter it is called every 200ms through the pr_fasttimo entry and
+ * every 500ms through the pr_slowtimo for timer based actions.
+ * The system will call the pr_drain entry if it is low on space and
+ * this should throw away any non-critical data.
+ *
+ * Protocols pass data between themselves as chains of mbufs using
+ * the pr_input and pr_output hooks.  Pr_input passes data up (towards
+ * UNIX) and pr_output passes it down (towards the imps); control
+ * information passes up and down on pr_ctlinput and pr_ctloutput.
+ * The protocol is responsible for the space occupied by any the
+ * arguments to these entries and must dispose it.
+ *
+ * The userreq routine interfaces protocols to the system and is
+ * described below.
+ *
+ * MODULE: INET
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef PROTOSW_H
+#define  PROTOSW_H   1
+
+struct ifnet;  /* pre-declaration to supress warnings */
+
+struct protosw
+{
+   short    pr_type;             /* socket type used for */
+   short    pr_protocol;         /* protocol number */
+   short    pr_flags;            /* see below */
+
+   /* protocol-protocol hooks */
+   void     (*pr_input) __P ((struct mbuf *, NET ifp));
+
+#ifdef CTL_INPUT
+   /* input to protocol (from below) */
+   void     (*pr_ctlinput)__P ((int, struct sockaddr *));   
+   /* control input (from below) */
+#endif
+#ifdef CTL_OUTPUT
+   /* control output (from above) */
+   int      (*pr_ctloutput) __P((int, struct socket *, int, int, void *));
+#endif
+
+   /* user-protocol hook */
+   int      (*pr_usrreq) __P ((struct socket *, struct mbuf *, struct mbuf *));
+
+   /* user request: see list below */
+   /* utility hooks */
+   void     (*pr_init) __P ((void));  /* initialization hook */
+#ifdef DO_DELAY_ACKS
+   int      (*pr_fasttimo) __P ((void));  /* fast timeout (200ms) */
+#endif
+      void     (*pr_slowtimo) __P ((void));  /* slow timeout (500ms) */
+};
+
+/*
+ * Values for pr_flags
+ */
+#define     PR_ATOMIC   0x01     /* exchange atomic messages only */
+#define     PR_ADDR        0x02  /* addresses given with messages */
+/* in the current implementation, PR_ADDR needs PR_ATOMIC to work */
+#define     PR_CONNREQUIRED   0x04     /* connection required by protocol */
+#define     PR_WANTRCVD    0x08     /* want PRU_RCVD calls */
+#define     PR_RIGHTS   0x10     /* passes capabilities */
+
+/*
+ * The arguments to usrreq are:
+ *   (*protosw[].pr_usrreq)(up, req, m, nam, opt);
+ * where up is a (struct socket *), req is one of these requests,
+ * m is a optional mbuf chain containing a message,
+ * nam is an optional mbuf chain containing an address,
+ * and opt is a pointer to a socketopt structure or nil.
+ * The protocol is responsible for disposal of the mbuf chain m,
+ * the caller is responsible for any space held by nam and opt.
+ * A non-zero return from usrreq gives an
+ * UNIX error number which should be passed to higher level software.
+ */
+#define     PRU_ATTACH        0  /* attach protocol to up */
+#define     PRU_DETACH        1  /* detach protocol from up */
+#define     PRU_BIND       2  /* bind socket to address */
+#define     PRU_LISTEN        3  /* listen for connection */
+#define     PRU_CONNECT       4  /* establish connection to peer */
+#define     PRU_ACCEPT        5  /* accept connection from peer */
+#define     PRU_DISCONNECT       6  /* disconnect from peer */
+#define     PRU_SHUTDOWN      7  /* won't send any more data */
+#define     PRU_RCVD       8  /* have taken data; more room now */
+#define     PRU_SEND       9  /* send this data */
+#define     PRU_ABORT      10 /* abort (fast DISCONNECT, DETATCH) */
+#define     PRU_CONTROL       11 /* control operations on protocol */
+#define     PRU_SENSE      12    /* return status into m */
+#define     PRU_RCVOOB        13 /* retrieve out of band data */
+#define     PRU_SENDOOB       14 /* send out of band data */
+#define     PRU_SOCKADDR      15 /* fetch socket's address */
+#define     PRU_PEERADDR      16 /* fetch peer's address */
+#define     PRU_CONNECT2      17 /* connect two sockets */
+
+/* begin for protocols internal use */
+#define     PRU_FASTTIMO      18 /* 200ms timeout */
+#define     PRU_SLOWTIMO      19 /* 500ms timeout */
+#define     PRU_PROTORCV      20 /* receive from below */
+#define     PRU_PROTOSEND        21 /* send to below */
+#define     PRU_NREQ       21
+
+#ifdef PRUREQUESTS
+char *   prurequests[]  =  {
+   "ATTACH",   "DETACH",   "BIND",      "LISTEN",
+   "CONNECT",   "ACCEPT",   "DISCONNECT",   "SHUTDOWN",
+   "RCVD",      "SEND",      "ABORT",   "CONTROL",
+   "SENSE",   "RCVOOB",   "SENDOOB",   "SOCKADDR",
+   "PEERADDR",   "CONNECT2",   "FASTTIMO",   "SLOWTIMO",
+   "PROTORCV",   "PROTOSEND",
+};
+#endif
+
+
+/*
+ * The arguments to the ctlinput routine are
+ *   (*protosw[].pr_ctlinput)(cmd, arg);
+ * where cmd is one of the commands below, and arg is
+ * an optional argument (caddr_t).
+ *
+ * N.B. The IMP code, in particular, pressumes the values
+ *      of some of the commands; change with extreme care.
+ * TODO:
+ *   spread out codes so new ICMP codes can be
+ *   accomodated more easily
+ */
+
+#define  PRC_IFDOWN           0     /* interface transition */
+#define  PRC_ROUTEDEAD        1     /* select new route if possible */
+#define  PRC_QUENCH           4     /* some said to slow down */
+#define  PRC_MSGSIZE          5     /* message size forced drop */
+#define  PRC_HOSTDEAD         6     /* normally from IMP */
+#define  PRC_HOSTUNREACH      7     /* ditto */
+#define  PRC_UNREACH_NET      8     /* no route to network */
+#define  PRC_UNREACH_HOST     9     /* no route to host */
+#define  PRC_UNREACH_PROTOCOL 10    /* dst says bad protocol */
+#define  PRC_UNREACH_PORT     11    /* bad port # */
+#define  PRC_UNREACH_NEEDFRAG 12    /* IP_DF caused drop */
+#define  PRC_UNREACH_SRCFAIL  13    /* source route failed */
+#define  PRC_REDIRECT_NET     14    /* net routing redirect */
+#define  PRC_REDIRECT_HOST    15    /* host routing redirect */
+#define  PRC_REDIRECT_TOSNET  16    /* redirect for type of service & net */
+#define  PRC_REDIRECT_TOSHOST 17    /* redirect for tos & host */
+#define  PRC_TIMXCEED_INTRANS 18    /* packet lifetime expired in transit */
+#define  PRC_TIMXCEED_REASS   19    /* lifetime expired on reass q */
+#define  PRC_PARAMPROB        20    /* header incorrect */
+#define  PRC_NCMDS            21
+
+
+#ifdef PRCREQUESTS
+char   * prcrequests[]  =  {
+   "IFDOWN", "ROUTEDEAD", "#2", "#3",
+   "QUENCH", "MSGSIZE", "HOSTDEAD", "HOSTUNREACH",
+   "NET-UNREACH", "HOST-UNREACH", "PROTO-UNREACH", "PORT-UNREACH",
+   "FRAG-UNREACH", "SRCFAIL-UNREACH", "NET-REDIRECT", "HOST-REDIRECT",
+   "TOSNET-REDIRECT", "TOSHOST-REDIRECT", "TX-INTRANS", "TX-REASS",
+   "PARAMPROB"
+};
+#endif
+
+
+/*
+ * The arguments to ctloutput are:
+ *   (*protosw[].pr_ctloutput)(req, so, level, optname, optval);
+ * req is one of the actions listed below, so is a (struct socket *),
+ * level is an indication of which protocol layer the option is intended.
+ * optname is a protocol dependent socket option request,
+ * optval is a pointer to a mbuf-chain pointer, for value-return results.
+ * The protocol is responsible for disposal of the mbuf chain *optval
+ * if supplied,
+ * the caller is responsible for any space held by *optval, when returned.
+ * A non-zero return from usrreq gives an
+ * UNIX error number which should be passed to higher level software.
+ */
+
+#define     PRCO_GETOPT    0
+#define     PRCO_SETOPT    1
+#define     PRCO_NCMDS     2
+#ifdef PRCOREQUESTS
+
+char   * prcorequests[] =
+{
+   "GETOPT",
+   "SETOPT",
+};
+#endif
+
+extern   struct protosw *  pffindtype  __P ((int, int));
+extern   struct protosw *  pffindproto __P ((int, int, int));
+
+#endif   /* PROTOSW_H */
+
+/* end of file protosw.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/rawsock.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/rawsock.c
new file mode 100644
index 0000000..66d28e5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/rawsock.c
@@ -0,0 +1,438 @@
+/*
+ * FILENAME: rawsock.c
+ *
+ * Copyright 2002 InterNiche Technologies Inc. All rights reserved.
+ *
+ * Raw IP access for sockets -- provides sockets-API access to the 
+ * InterNiche lightweight API's raw IP endpoints.
+ *
+ * MODULE: TCP
+ *
+ * ROUTINES: rawip_lookup(), rawip_soinput(), rawip_usrreq()
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef IP_RAW        /* can ifdef away whole file */
+
+#include "mbuf.h"    /* sockets/BSDish includes */
+#include "socket.h"
+#include "sockvar.h"
+#include "sockcall.h"
+#include "protosw.h"
+
+#include "ip.h"
+
+/* list of active raw-IP endpoints */
+extern struct ipraw_ep * ipraw_eps;
+
+/* FUNCTION: rawip_lookup()
+ * 
+ * Locate raw IP endpoint for a socket.
+ *
+ * PARAM1: struct socket * so; IN- socket for which raw IP endpoint
+ *                             is to be located.
+ *
+ * RETURNS: pointer to the matching raw IP endpoint,
+ *          or NULL if no matching raw IP endpoint is found.
+ */
+
+struct ipraw_ep *
+rawip_lookup(struct socket * so)
+{
+   struct ipraw_ep * tmp;
+
+   for (tmp = ipraw_eps; tmp; tmp = tmp->ipr_next)
+      if (tmp->ipr_data == (void*)so)
+      return (tmp);
+
+   return NULL;   /* didn't find it */
+}
+
+/* FUNCTION: rawip_soinput()
+ *
+ * Raw IP upcall handler for Raw IP endpoints with corresponding sockets. 
+ * Return 0 if OK, else nonzero error code. 
+ * 
+ * PARAM1: PACKET pkt
+ * PARAM2: void * so_ptr
+ *
+ * RETURNS: 0 if successful, else a non-zero error code which 
+ *          indicates that the packet has not been accepted.
+ */
+
+int
+rawip_soinput(PACKET pkt, void * so_ptr)
+{
+   struct mbuf *  m_in;    /* packet/data mbuf */
+   struct socket *   so =  (struct  socket *)so_ptr;
+   struct sockaddr_in   sin;
+
+   LOCK_NET_RESOURCE(NET_RESID); 
+
+   /* make sure we're not flooding input buffers */
+   if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat)
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   /* alloc mbuf for received data */
+   m_in = m_getnbuf(MT_RXDATA, 0);
+   if (!m_in)
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   /* set data mbuf to point to start of IP header */
+   m_in->pkt = pkt;
+   m_in->m_base = pkt->nb_buff;
+   m_in->m_memsz = pkt->nb_blen;
+   m_in->m_data = pkt->nb_prot;
+   m_in->m_len = pkt->nb_plen;
+
+   /* if this socket doesn't have IP_HDRINCL set, adjust the
+    * mbuf to skip past the IP header
+    */
+   if (!(so->so_options & SO_HDRINCL))
+   {
+      unsigned int ihl = 
+         (((struct ip *)(pkt->nb_prot))->ip_ver_ihl & 0x0f) << 2;
+      m_in->m_data += ihl;
+      m_in->m_len -= ihl;
+   }
+
+   /* fill in net address info for pass to socket append()ers */
+   sin.sin_addr.s_addr = pkt->fhost;
+   sin.sin_port = 0;
+   sin.sin_family = AF_INET;
+
+   /* attempt to append address information to mbuf */
+   if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in))
+   {
+      /* set the pkt field in the mbuf to NULL so m_free() below wont 
+       * free the packet buffer, because that is left to the 
+       * underlying stack
+       */
+      m_in->pkt = NULL;
+      /* free only the mbuf itself */
+      m_free(m_in);
+      /* return error condition so caller can free the packet buffer */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   tcp_wakeup(&so->so_rcv);   /* wake anyone waiting for this */
+
+   sorwakeup(so);    /* wake up selects too */
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return 0;
+}
+
+
+/* FUNCTION: rawip_usrreq()
+ *
+ * proto_tab's usr_req call function for raw IP protocol. Maps the 
+ * sockets requests to NicheStack raw IP interface. Returns 0 
+ * if no error, negative "NP" error if lower layers fail, postive 
+ * error from nptcp.h if TCP/Sockets fails. 
+ * 
+ * PARAM1: struct socket * so
+ * PARAM2: struct mbuf * m
+ * PARAM3: struct mbuf * nam
+ *
+ * RETURNS: 
+ */
+
+int
+rawip_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+   int   e;    /* error from IP stack */
+   PACKET pkt; /* packet for sending */
+   struct sockaddr_in * sin;
+   struct ipraw_ep * ep;
+   ip_addr fhost; /* host to send to/recv from (network byte order) */
+   ip_addr lhost; /* local IP address to bind to (network byte order) */
+   u_char prot;
+   struct ip * pip;
+   int   req;
+   NET   ifp;     /* ptr to network interface structure */
+
+   req = so->so_req;    /* get request from socket struct */
+
+   switch (req) 
+   {
+   case PRU_ATTACH:
+      /* fake small windows so sockets asks us to move data */
+      so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = 
+         ip_raw_maxalloc(so->so_options & SO_HDRINCL);
+      /* make a raw IP endpoint */
+      prot = (u_char)(MBUF2LONG(nam));
+      /* unlock the net resource; IP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      ep = ip_raw_open(prot, 0L, 0L, rawip_soinput, so);
+      LOCK_NET_RESOURCE(NET_RESID);
+      if (!ep)
+         return(EINVAL);
+      return 0;
+   case PRU_DETACH:
+      /* delete the raw IP endpoint */
+      ep = rawip_lookup(so);
+      if (!ep)
+         return(EINVAL);
+      /* unlock the net resource; IP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      ip_raw_close(ep);
+      LOCK_NET_RESOURCE(NET_RESID);
+      return 0;
+   case PRU_CONNECT:
+      /* "connect" the raw IP endpoint to a peer IP address:
+       * this sets a filter for received IP datagrams and sets
+       * a default address for sending
+       */
+      /* fall through to shared bind logic */
+   case PRU_BIND:
+      /* do bind parameters lookups and tests */
+      if (nam == NULL)
+         return(EINVAL);
+      sin = mtod(nam, struct sockaddr_in *);
+      if (sin == NULL)
+         return(EINVAL);
+      if (nam->m_len != sizeof (*sin))
+         return(EINVAL);
+      ep = rawip_lookup(so);
+      if (!ep)
+         return(EINVAL);
+      if (req == PRU_BIND)
+      {
+         /* bind the socket to a local interface IP address.
+          *
+          * if the caller-supplied address is INADDR_ANY,
+          * don't bind to a specific address; else, 
+          * make sure the caller-supplied address is
+          * an interface IP address and if so, bind to that
+          */
+         if (sin->sin_addr.s_addr == INADDR_ANY)
+         {
+            lhost = 0L;
+         }
+         else
+         {
+            lhost = sin->sin_addr.s_addr;
+            /* verify that lhost is a local interface address */
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+               if (ifp->n_ipaddr == lhost)
+                  break;
+            if (ifp == NULL)
+               return(EADDRNOTAVAIL);
+         }
+
+         /* bind the endpoint */
+         ep->ipr_laddr = lhost;
+      }
+      else /* PRU_CONNECT */
+      {
+         /* connect the socket to a remote IP address.
+          *
+          * if the caller-supplied address is INADDR_ANY,
+          * use the wildcard address; else, use the caller-
+          * supplied address
+          */
+         if (sin->sin_addr.s_addr == INADDR_ANY)
+            fhost = 0L;
+         else
+            fhost = sin->sin_addr.s_addr;
+         /* connect the IP endpoint */
+         ep->ipr_faddr = fhost;
+         /* mark the socket as connected or disconnected, as appropriate */
+         if (fhost != 0L) {
+            so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+            so->so_state |= SS_ISCONNECTED;
+         }
+         else
+         {
+            so->so_state &= ~SS_ISCONNECTED;
+         }
+         /* since socket was in listen state, packets may be queued */
+         sbflush(&so->so_rcv);   /* dump these now */
+      }
+      return 0;
+   case PRU_SEND:
+      /* do parameter lookups and tests */
+      if (!m)  /* no data passed? */
+         return(EINVAL);
+
+      ep = rawip_lookup(so);
+      if (!ep)
+      {
+         m_free(m);
+         /* may be bogus socket, but more likely the connection may 
+         have closed due to ICMP dest unreachable from other side. */
+         return(ECONNREFUSED);
+      }
+
+      if (nam == NULL)  /* no sendto() info passed, must be send() */
+      {
+         if (!(so->so_state & SS_ISCONNECTED))
+            return (ENOTCONN);
+         fhost = ep->ipr_faddr;
+      }
+      else 
+      {
+         if (so->so_state & SS_ISCONNECTED)
+            return (EISCONN);
+         if (nam->m_len != sizeof (*sin))
+         {
+            dtrap();
+            return (EINVAL);
+         }
+         sin = mtod(nam, struct sockaddr_in *);
+         fhost = sin->sin_addr.s_addr;
+      }
+
+      /* since our pkt->nb_buff size is tied to max packet size, we 
+       * assume our raw IP datagrams are always in one mbuf and that the 
+       * mbuf -- but check anyway
+       */
+      if (m->m_len > (unsigned)ip_raw_maxalloc(so->so_options & SO_HDRINCL))
+      {
+         dtrap(); /* should never happen */
+         return EMSGSIZE;  /* try to recover */
+      }
+      /* get a packet buffer for send */
+      pkt = ip_raw_alloc(m->m_len, so->so_options & SO_HDRINCL);
+      if (!pkt)
+      {
+         m_free(m);
+         return ENOBUFS;   /* report buffer shortages */
+      }
+      MEMCPY(pkt->nb_prot, m->m_data, m->m_len);
+      pkt->nb_plen = m->m_len;
+      /* finished with mbuf, free it now */
+      m_free(m);
+      pkt->fhost = fhost;
+
+      /* if we're being asked to send to 255.255.255.255 (a local-net
+       * broadcast), figure out which interface to send the broadcast
+       * on, based on the IP address that the socket is bound to: if
+       * it has been bound to an interface address, we should send the
+       * broadcast on that interface; else, we look for the first
+       * interface that can support broadcasts and is up; if we still
+       * don't have an interface we look for the first interface that
+       * is up; if (after all that) we don't have an interface then we
+       * fail with error EADDRNOTAVAIL; and finally, if we're built
+       * for a single-homed configuration where there's only one
+       * interface, we might as well use it, so we do.  
+       */
+      if (fhost == 0xffffffff)
+      {
+#ifdef MULTI_HOMED
+         if (ep->ipr_laddr != 0L)
+         {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+               if (ifp->n_ipaddr == ep->ipr_laddr)
+                  break;
+         }
+         else {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+               if ((ifp->n_flags & NF_BCAST) &&
+                   (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+                  break;
+         }
+         if (ifp == NULL)
+         {
+            for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+               if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+                  break;
+            if (ifp == NULL)
+               return(EADDRNOTAVAIL);
+         }
+         pkt->net = ifp;
+#else  /* single-homed */
+         pkt->net = (NET)(netlist.q_head);
+#endif /* MULTI_HOMED */
+      }
+
+#ifdef IP_MULTICAST
+
+      /* If the socket has an IP moptions structure for multicast options,
+       * place a pointer to this structure in the PACKET structure.
+       */
+      if (so->inp_moptions)
+         pkt->imo = so->inp_moptions;
+
+#endif   /* IP_MULTICAST */
+
+      if (so->so_options & SO_HDRINCL)
+      {
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         e = ip_raw_write(pkt);
+         LOCK_NET_RESOURCE(NET_RESID);
+      }
+      else
+      {
+         pip = (struct ip *)(pkt->nb_prot - IPHSIZ);
+         if (ep->ipr_laddr)
+            pip->ip_src = ep->ipr_laddr;
+         else
+         {
+            if (fhost == 0xffffffff)
+               pip->ip_src = pkt->net->n_ipaddr;
+            else
+               pip->ip_src = ip_mymach(fhost);
+         }
+         pip->ip_dest = fhost;
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         e = ip_write(ep->ipr_prot, pkt);
+         LOCK_NET_RESOURCE(NET_RESID);
+      }         
+      if (e < 0) 
+         return(e);
+      return 0;
+   case PRU_SOCKADDR:
+      /* fall through to share PRU_PEERADDR prefix */
+   case PRU_PEERADDR:
+      if (nam == NULL)
+         return(EINVAL);
+      sin = mtod(nam, struct sockaddr_in *);
+      if (sin == NULL)
+         return(EINVAL);
+      ep = rawip_lookup(so);
+      if (!ep)
+         return(EINVAL);
+      sin->sin_port = 0;
+      nam->m_len = sizeof(*sin);
+      if (req == PRU_SOCKADDR)
+      {
+         sin->sin_addr.s_addr = ep->ipr_laddr;
+      }
+      else /* PRU_PEERADDR */
+      {
+         sin->sin_addr.s_addr = ep->ipr_faddr;
+      }
+      return 0;
+   case PRU_DISCONNECT:
+   case PRU_RCVD:
+      dtrap();
+      return 0;
+   case PRU_LISTEN:     /* don't support these for raw IP */
+   case PRU_ACCEPT:
+   default:
+      return EOPNOTSUPP;
+   }
+}
+
+#endif   /* IP_RAW */
+#endif /* INCLUDE_TCP */
+
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/sockcall.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/sockcall.c
new file mode 100644
index 0000000..638376d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/sockcall.c
@@ -0,0 +1,1150 @@
+/*
+ * FILENAME: sockcall.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: t_socket(), t_bind (), t_listen(), t_accept(), 
+ * ROUTINES: t_connect(), t_getpeername(), t_getsockname(), t_setsockopt(), 
+ * ROUTINES: t_getsockopt(), t_recv (), t_recvfrom(), t_sendto (), 
+ * ROUTINES: t_shutdown(), t_socketclose(), sockargs (), sock_recvit(), 
+ * ROUTINES: sock_sendit(), t_errno()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "protosw.h"
+#include "in_pcb.h"
+#include "tcp.h"
+#include "udp.h"
+#include "ip.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+
+#ifdef INCLUDE_INICHE_LOG
+#include "iniche_log.h"
+#endif
+/*#define SOCKDEBUG  1*/
+/*#define TRACE_DEBUG*/
+
+/* Internal helper functions */
+static struct mbuf * sockargs(void *, int, int);
+static int  t_getname(long s, struct sockaddr * addr, int * addrlen, int opcode);
+
+
+/* bitmask for connection state bits which determine if send/recv is OK */
+#define  SO_IO_OK (SS_ISCONNECTED|SS_ISCONNECTING|SS_ISDISCONNECTING)
+
+
+/* Domain check is an option for testing validity of
+ * passed sockaddr_in sizes for the socket's domain
+ * (IN_ADDR for IPv6, or IP_ADDR5 for IPv6)
+ */
+
+#ifdef NPDEBUG
+void
+DOMAIN_CHECK(struct socket * so, int size)
+{
+#ifdef IP_V4
+   if((so->so_domain == AF_INET) &&
+      (size < sizeof(struct sockaddr_in)))
+   {
+      dtrap(); /* programmer passed wrong structure */
+   }
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+   if((so->so_domain == AF_INET6) &&
+      (size != sizeof(struct sockaddr_in6)))
+   {
+      dtrap(); /* programmer passed wrong structure */
+   }
+#endif   /* IP_V6 */
+}
+#else    /* not debug build */
+#define    DOMAIN_CHECK(so, size)   /* define away to nothing */
+#endif
+
+
+
+/* FUNCTION: t_socket()
+ * 
+ * PARAM1: int family
+ * PARAM2: int type
+ * PARAM3: int proto
+ *
+ * RETURNS: 
+ */
+
+long
+t_socket(int family, 
+   int   type, 
+   int   proto)
+{
+   struct socket *   so;
+
+   INET_TRACE (INETM_SOCKET, ("SOCK:sock:family %d, typ %d, proto %d\n",
+    family, type, proto));
+   LOCK_NET_RESOURCE(NET_RESID);
+   if ((so = socreate (family, type, proto)) == NULL) 
+   {  /* can't really return error info since no socket.... */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return SOCKET_ERROR;
+   }
+   SOC_RANGE(so);
+   so->so_error = 0;
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return SO2LONG(so);
+}
+
+
+
+/* FUNCTION: t_bind ()
+ * 
+ * PARAM1: long s
+ * PARAM2: struct sockaddr *addr
+ *
+ * RETURNS: 0 if OK, else one of the socket error codes
+ */
+
+int
+t_bind (long s, 
+   struct sockaddr * addr,
+   int addrlen)
+{
+   struct mbuf *     nam;
+   struct sockaddr   sa;
+   struct sockaddr * sap;
+   struct socket *   so;
+   int               err;
+
+   so = LONG2SO(s);  /* convert long to socket */
+   SOC_CHECK(so);
+   DOMAIN_CHECK(so, addrlen);
+
+   so->so_error = 0;
+   if (addr == (struct sockaddr *)NULL) 
+   {
+      MEMSET ((void *)&sa, 0, sizeof(sa));
+      addrlen = sizeof(sa);
+      sa.sa_family = so->so_domain;
+      sap = &sa;
+   } else
+      sap = addr;
+
+   if ((nam = sockargs (sap, addrlen, MT_SONAME)) == NULL) 
+   {
+      so->so_error = ENOMEM;
+      return SOCKET_ERROR;
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+   err = sobind (so, nam);
+   m_freem(nam);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   if (err) 
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: t_listen()
+ * 
+ * PARAM1: long s
+ * PARAM2: int backlog
+ *
+ * RETURNS: 
+ */
+
+int
+t_listen(long s, 
+   int   backlog)
+{
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);  /* convert long to socket */
+   SOC_CHECK(so);
+   so->so_error = 0;
+   INET_TRACE (INETM_SOCKET, ("SOCK:listen:qlen %d\n", backlog));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   err = solisten (so, backlog);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if (err != 0) 
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: t_accept()
+ * 
+ * PARAM1: long s
+ * PARAM2: struct sockaddr * addr
+ *
+ * RETURNS: 
+ */
+
+long
+t_accept(long s, 
+   struct sockaddr * addr,
+   int * addrlen)
+{
+#ifdef SOCKDEBUG
+   char logbuf[10];
+#endif
+   struct socket *   so;
+   struct mbuf *  nam;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   DOMAIN_CHECK(so, *addrlen);
+
+   so->so_error = 0;
+   INET_TRACE (INETM_SOCKET,
+      ("INET:accept:so %x so_qlen %d so_state %x\n", so, so->so_qlen, so->so_state));
+   if ((so->so_options & SO_ACCEPTCONN) == 0)
+   {
+      so->so_error = EINVAL;
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+   }
+   if ((so->so_state & SS_NBIO) && so->so_qlen == 0)
+   {
+      so->so_error = EWOULDBLOCK;
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+   while (so->so_qlen == 0 && so->so_error == 0)
+   {
+      if (so->so_state & SS_CANTRCVMORE)
+      {
+         so->so_error = ECONNABORTED;
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         return SOCKET_ERROR;
+      }
+      tcp_sleep ((char *)&so->so_timeo);
+   }
+   if (so->so_error)
+   {
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return SOCKET_ERROR;
+   }
+   nam = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+   if (nam == NULL) 
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      so->so_error = ENOMEM;
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_accept[%d]: %d", __LINE__, so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+   }
+   { 
+      struct socket *aso = so->so_q;
+      if (soqremque (aso, 1) == 0)
+         panic("accept");
+      so = aso;
+   }
+   (void)soaccept (so, nam);
+#ifdef TRACE_DEBUG
+   { struct sockaddr_in *sin;
+      sin = mtod(nam, struct sockaddr_in *);
+      INET_TRACE (INETM_SOCKET, ("INET:accept:done so %lx port %d addr %lx\n",
+       so, sin->sin_port, sin->sin_addr.s_addr));
+   }
+#endif   /* TRACE_INET */
+   /* return the addressing info in the passed structure */
+   if (addr != NULL)
+      MEMCPY(addr, nam->m_data, *addrlen);
+   m_freem (nam);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   SOC_RANGE(so);
+   return SO2LONG(so);
+}
+
+/* FUNCTION: t_connect()
+ * 
+ * PARAM1: long s
+ * PARAM2: struct sockaddr *addr
+ *
+ * RETURNS: 
+ */
+
+int
+t_connect(long s, 
+   struct sockaddr * addr,
+   int   addrlen)
+{
+   struct socket *   so;
+   struct mbuf *  nam;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   DOMAIN_CHECK(so, addrlen);
+
+#ifdef NB_CONNECT
+   /* need to test non blocking connect bits in case this is a 
+      poll of a previous request */
+   if (so->so_state & SS_NBIO)
+   {
+      if (so->so_state & SS_ISCONNECTING) /* still trying */
+      {
+         so->so_error = EINPROGRESS;
+         return SOCKET_ERROR;
+      }
+      if (so->so_state & SS_ISCONNECTED)  /* connected OK */
+      {
+         so->so_error = 0;
+         return 0;
+      }
+      if (so->so_state & SS_WASCONNECTING)
+      {
+         so->so_state &= ~SS_WASCONNECTING;
+         if (so->so_error) /* connect error - maybe timeout */
+            return SOCKET_ERROR;
+      }
+   }
+#endif   /*  NB_CONNECT */
+
+   so->so_error = 0;
+
+   if ((nam = sockargs (addr, addrlen, MT_SONAME))
+       == NULL)
+   {
+      so->so_error = ENOMEM;
+      return SOCKET_ERROR;
+   }
+
+#ifdef TRACE_DEBUG
+   { struct sockaddr_in *sin = (struct sockaddr_in *)uap->sap;
+      INET_TRACE (INETM_SOCKET, ("INET: connect, port %d addr %lx\n",
+       sin->sin_port, sin->sin_addr.s_addr));
+   }
+#endif   /* TRACE_DEBUG */
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   if ((so->so_error = soconnect (so, nam)) != 0)
+      goto bad;
+
+#ifdef NB_CONNECT
+   /* need to test non blocking connect bits after soconnect() call */
+   if ((so->so_state & SS_NBIO)&& (so->so_state & SS_ISCONNECTING))
+   {
+      so->so_error = EINPROGRESS;
+      goto bad;
+   }
+#endif   /*  NB_CONNECT */
+   INET_TRACE (INETM_SOCKET, ("INET: connect, so %x so_state %x so_error %d\n",
+    so, so->so_state, so->so_error));
+
+   while ((so->so_state & SS_ISCONNECTING) && so->so_error == 0) 
+   {
+      tcp_sleep ((char *)&so->so_timeo);
+   }
+bad:
+   if (so->so_error != EINPROGRESS)
+      so->so_state &= ~(SS_ISCONNECTING|SS_WASCONNECTING);
+   m_freem (nam);
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   if (so->so_error)
+   {
+/*      printf("t_connect(): so_error = %d\n", so->so_error);*/
+      return SOCKET_ERROR;
+
+   }
+      return 0;
+}
+
+
+
+/* FUNCTION: t_getpeername()
+ * 
+ * PARAM1: long s
+ * PARAM2: struct sockaddr * addr
+ * PARAM3: pointer to int with sockaddr length (v4 vs v6)
+ *
+ * RETURNS: 
+ */
+
+int
+t_getpeername(long s, struct sockaddr * addr, int * addrlen)
+{
+   return(t_getname(s, addr, addrlen, PRU_PEERADDR));
+}
+
+
+/* FUNCTION: t_getsockname()
+ * 
+ * PARAM1: long s
+ * PARAM2: struct sockaddr *addr
+ * PARAM3: pointer to int with sockaddr length (v4 vs v6)
+ *
+ * RETURNS: 
+ */
+
+int 
+t_getsockname(long s, struct sockaddr * addr, int * addrlen)
+{
+   return(t_getname(s, addr, addrlen, PRU_SOCKADDR));
+}
+
+
+/* FUNCTION: t_getname()
+ * 
+ * Worker function for getpeername and getsockname.
+ *
+ * PARAM1: long s
+ * PARAM2: struct sockaddr *addr
+ * PARAM3: pointer to int with sockaddr length (v4 vs v6)
+ * PARAM4: opcode for call - peername or sockname
+ *
+ * RETURNS: 
+ */
+
+static int
+t_getname(long s, struct sockaddr * addr, int * addrlen, int opcode)
+{
+   struct socket *   so;
+   struct mbuf *  m;
+   int   err;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+
+   so->so_error = 0;
+   INET_TRACE (INETM_SOCKET, ("INET:get[sock|peer]name so %x\n", so));
+   if((opcode == PRU_PEERADDR) && (so->so_state & SS_ISCONNECTED) == 0)
+   {
+      so->so_error = ENOTCONN;
+      return SOCKET_ERROR;
+   }
+   LOCK_NET_RESOURCE(NET_RESID);
+   m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+   if (m == NULL) 
+   {
+      so->so_error = ENOMEM;
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return SOCKET_ERROR;
+   }
+   so->so_req = opcode;
+   if ((err = (*so->so_proto->pr_usrreq)(so, 0, m)) != 0)
+      goto bad;
+
+#ifdef IP_V4
+   if(so->so_domain == AF_INET)
+   {
+      if(*addrlen < sizeof(struct sockaddr_in))
+      {
+         dtrap();    /* programming error */
+         m_freem(m);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         return EINVAL;
+      }
+      MEMCPY(addr, m->m_data, sizeof(struct sockaddr_in));
+      *addrlen = sizeof(struct sockaddr_in);
+   }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   if(so->so_domain == AF_INET6)
+   {
+      if(*addrlen < sizeof(struct sockaddr_in6))
+      {
+         dtrap();    /* programming error */
+         m_freem(m);
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         return EINVAL;
+      }
+      MEMCPY(addr, m->m_data, sizeof(struct sockaddr_in6));
+      *addrlen = sizeof(struct sockaddr_in6);
+   }
+#endif   /* IP_V6 */
+
+
+bad:
+   m_freem(m);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   if (err) 
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: t_setsockopt()
+ * 
+ * PARAM1: long s
+ * PARAM2: int name
+ * PARAM3: void *arg
+ *
+ * RETURNS: 
+ */
+
+int
+t_setsockopt(long s,
+   int   level,
+   int   name,
+   void * arg,
+   int arglen)
+{
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   USE_ARG(arglen);
+
+   LOCK_NET_RESOURCE (NET_RESID);
+
+   so->so_error = 0;
+   INET_TRACE (INETM_SOCKET,
+    ("INET: setsockopt: name %x val %x valsize %d\n",
+    name, val));
+
+   /* is it a level IP_OPTIONS call? */
+   if (level != IP_OPTIONS)
+   {
+      if ((err = sosetopt (so, name, arg)) != 0) 
+      {
+         so->so_error = err;
+         UNLOCK_NET_RESOURCE (NET_RESID);
+         return SOCKET_ERROR;
+      }
+   }
+   else
+   {
+   /* level 1 options are for the IP packet level.
+    * the info is carried in the socket CB, then put 
+    * into the PACKET.
+    */
+      if (!so->so_optsPack)
+      {
+         so->so_optsPack = (struct ip_socopts *) SOCOPT_ALLOC (sizeof(struct ip_socopts *));
+         if (!so->so_optsPack) 
+         {
+            so->so_error = ENOMEM;
+            UNLOCK_NET_RESOURCE (NET_RESID);
+            return SOCKET_ERROR;
+         }
+      }
+      
+      if (name == IP_TTL_OPT)
+         so->so_optsPack->ip_ttl = (u_char)(*(int *)arg);
+      else
+      if (name == IP_TOS)
+         so->so_optsPack->ip_tos = (u_char)(*(int *)arg);
+	   else
+	   if (name == IP_SCOPEID)
+            so->so_optsPack->ip_scopeid = (u_char)(*(u_int *)arg);
+      else
+      {
+         UNLOCK_NET_RESOURCE (NET_RESID);
+         return SOCKET_ERROR;
+      }   
+   }
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+   return 0;
+}
+
+
+
+/* FUNCTION: t_getsockopt()
+ * 
+ * PARAM1: long s
+ * PARAM2: int name
+ * PARAM3: void *arg
+ *
+ * RETURNS: 
+ */
+
+int
+t_getsockopt(long s,
+   int   level,
+   int   name,
+   void *   arg,
+   int   arglen)
+
+{
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   USE_ARG(level);
+   USE_ARG(arglen);
+
+   LOCK_NET_RESOURCE (NET_RESID);
+
+   INET_TRACE (INETM_SOCKET,
+    ("INET: getsockopt: name %x val %x valsize %d\n",
+    name, val));
+
+   /* is it a level IP_OPTIONS call? */
+   if (level != IP_OPTIONS)
+   {
+      if ((err = sogetopt (so, name, arg)) != 0) 
+      {
+         so->so_error = err;
+         UNLOCK_NET_RESOURCE (NET_RESID);
+         return SOCKET_ERROR;
+      }
+   }
+   else
+   {
+      /* level 1 options are for the IP packet level.
+       * the info is carried in the socket CB, then put 
+       * into the PACKET.
+       */
+      if (name == IP_TTL_OPT)
+      {
+         if (!so->so_optsPack) *(int *)arg = IP_TTL;
+         else *(int *)arg = (int)so->so_optsPack->ip_ttl;
+      }
+      else if (name == IP_TOS)
+      {
+         if (!so->so_optsPack) *(int *)arg = IP_TOS_DEFVAL;
+         else *(int *)arg = (int)so->so_optsPack->ip_tos;
+      }
+      else
+      {
+         UNLOCK_NET_RESOURCE (NET_RESID);
+         return SOCKET_ERROR;
+      }
+   }   
+   so->so_error = 0;
+
+   UNLOCK_NET_RESOURCE (NET_RESID);
+   return 0;
+}
+
+
+
+/* FUNCTION: t_recv ()
+ * 
+ * PARAM1: long s
+ * PARAM2: char *buf
+ * PARAM3: int len
+ * PARAM4: int flag
+ *
+ * RETURNS: 
+ */
+
+int
+t_recv (long s, 
+   char *   buf,
+   int   len, 
+   int   flag)
+{
+#ifdef SOCKDEBUG
+   char logbuf[10];
+#endif
+   struct socket *   so;
+   int   err;
+   int   sendlen = len;
+
+   so = LONG2SO(s);
+#ifdef SOC_CHECK_ALWAYS
+   SOC_CHECK(so);
+#endif
+   if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+   {
+      so->so_error = EPIPE;
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_recv: %d", so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+   }
+   so->so_error = 0;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   IN_PROFILER(PF_TCP, PF_ENTRY);        /* measure time in TCP */
+   INET_TRACE (INETM_IO, ("INET:recv: so %x, len %d\n", so, len));
+   err = soreceive(so, NULL, buf, &len, flag);
+   IN_PROFILER(PF_TCP, PF_EXIT);        /* measure time in TCP */
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if(err)
+   {
+      so->so_error = err;
+#ifdef SOCKDEBUG
+      sprintf(logbuf, "t_recv: %d", so->so_error);
+      glog_with_type(LOG_TYPE_DEBUG, logbuf, 1);
+#endif
+      return SOCKET_ERROR;
+   }
+
+   /* return bytes we sent - the amount we wanted to send minus
+    * the amount left in the buffer.
+    */
+   return (sendlen - len);
+}
+
+
+
+/* FUNCTION: t_recvfrom()
+ * 
+ * PARAM1: long s
+ * PARAM2: char *buf
+ * PARAM3: int len
+ * PARAM4: int flags
+ * PARAM5: struct sockaddr *from
+ *
+ * RETURNS: 
+ */
+
+int
+t_recvfrom(long s, 
+   char *   buf,
+   int   len, 
+   int   flags,
+   struct sockaddr * from,
+   int * fromlen)
+{
+   struct socket *   so;
+   struct mbuf *     sender = NULL;
+   int   err;
+   int   sendlen = len;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   so->so_error = 0;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   err = soreceive(so, &sender, buf, &len, flags);
+
+   /* copy sender info from mbuf to sockaddr */
+   if (sender)
+   {
+      MEMCPY(from, (mtod(sender, struct sockaddr *)), *fromlen );
+      m_freem (sender);
+   }
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if(err)
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+
+   /* OK return: amount of data actually sent */
+   return (sendlen - len);
+}
+
+
+
+/* FUNCTION: t_sendto ()
+ * 
+ * PARAM1: long s
+ * PARAM2: char *buf
+ * PARAM3: int len
+ * PARAM4: int flags
+ * PARAM5: struct sockaddr *to
+ *
+ * RETURNS: 
+ */
+
+int
+t_sendto (long s, 
+   char *   buf,
+   int   len, 
+   int   flags,
+   struct sockaddr * to,
+   int   tolen)
+{
+   struct socket *   so;
+   int   sendlen;
+   int   err;
+   struct mbuf *     name;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   so->so_error = 0;
+
+   switch (so->so_type)
+   {
+   case SOCK_STREAM:
+      /* this is a stream socket, so pass this request through
+       * t_send() for its large-send support.
+       */
+      return t_send(s, buf, len, flags);
+      /*NOTREACHED*/
+   case SOCK_DGRAM:
+      /* datagram (UDP) socket -- prepare to check length */
+      sendlen = udp_maxalloc();
+      break;
+#ifdef IP_RAW
+   case SOCK_RAW:
+      /* raw socket -- prepare to check length */
+      sendlen = ip_raw_maxalloc(so->so_options & SO_HDRINCL);
+      break;
+#endif /* IP_RAW */
+   default:
+      /* socket has unknown type */
+      dtrap();
+      so->so_error = EFAULT;
+      return SOCKET_ERROR;
+      /*NOTREACHED*/
+   }
+
+   /* fall through for non-stream sockets: SOCK_DGRAM (UDP) and
+    * SOCK_RAW (raw IP)
+    */
+
+   /* check length against underlying stack's maximum */
+   if (len > sendlen)
+   {
+      so->so_error = EMSGSIZE;
+      return SOCKET_ERROR;
+   }
+
+   /* if a sockaddr was passed, wrap it in an mbuf and pas it into the
+    * bowels of the BSD code; else assume this is a bound UDP socket
+    * and this call came from t_send() below.
+    */
+
+   if (to)  /* sockaddr was passed */
+   {
+      name = sockargs(to, tolen, MT_SONAME);
+      if(name == NULL)
+      {
+         so->so_error = ENOMEM;
+         return SOCKET_ERROR;
+      }
+   }
+   else     /* hope user called bind() first... */
+      name = NULL;
+   
+   sendlen = len;
+
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   err = sosend (so, name, buf, &sendlen, flags);
+
+   if (name)
+      m_freem(name);
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if (err != 0)
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+
+   return (len - sendlen);
+}
+
+
+
+
+/* FUNCTION: t_send()
+ * 
+ * PARAM1: long s
+ * PARAM2: char *buf
+ * PARAM3: int len
+ * PARAM4: int flags
+ *
+ * RETURNS: 
+ */
+
+int
+t_send(long s, 
+   char *   buf,
+   int      len, 
+   int      flags)
+{
+   struct socket *   so;
+   int   e;       /* error holder */
+   int   total_sent  =  0;
+   int   maxpkt;
+   int   sendlen;
+   int   sent;
+
+   so = LONG2SO(s);
+#ifdef SOC_CHECK_ALWAYS
+   SOC_CHECK(so);
+#endif
+   if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+   {
+      so->so_error = EPIPE;
+      return SOCKET_ERROR;
+   }
+   so->so_error = 0;
+
+   /* If this is not a stream socket, assume it is bound and pass to
+    * t_sendto() with a null sockaddr
+    */
+   if (so->so_type != SOCK_STREAM)
+      return(t_sendto(s, buf, len, flags, NULL, 0));
+
+   maxpkt = TCP_MSS;
+   if(so->so_pcb)
+   { 
+      struct tcpcb * tp;
+      tp = intotcpcb(so->so_pcb);   /* get tcp structure with mss */
+      if(tp->t_maxseg)              /* Make sure it's set */
+         maxpkt = tp->t_maxseg;
+   }
+
+   IN_PROFILER(PF_TCP, PF_ENTRY);       /* measure time in TCP */
+
+   while (len)
+   {
+      if (len > maxpkt)
+         sendlen = maxpkt;  /* take biggest block we can */
+      else
+         sendlen = len;
+      sent = sendlen;
+
+      LOCK_NET_RESOURCE(NET_RESID);
+      e = sosend (so, NULL, buf, &sendlen, flags);
+      UNLOCK_NET_RESOURCE(NET_RESID);
+ 
+      if (e != 0)  /* sock_sendit failed? */
+      {
+         /* if we simply ran out of bufs, report back to caller. */
+         if ((e == ENOBUFS) || (e == EWOULDBLOCK))
+         {
+            /* if we actually sent something before running out
+             * of buffers, report what we sent; 
+             * else, report the error and let the application 
+             * retry the call later
+             */
+            if (total_sent != 0)
+            {
+               so->so_error = 0;
+               break;      /* break out of while(len) loop */
+            }
+         }
+         so->so_error = e;
+         return SOCKET_ERROR;
+      }
+      /* if we can't send anymore, return now */
+      if (sendlen != 0)
+         break;         /* break out of while(len) loop */
+
+      /* adjust numbers & pointers, and go do next send loop */
+      sent -= sendlen;        /* subtract anything that didn't get sent */
+      buf += sent;
+      len -= sent;
+      total_sent += sent;
+   }
+
+   IN_PROFILER(PF_TCP, PF_EXIT);        /* measure time in TCP */
+   return total_sent;
+}
+
+
+
+/* FUNCTION: t_shutdown()
+ * 
+ * PARAM1: long               socket handle
+ * PARAM2: int                shutdown action
+ *
+ * RETURNS: 
+ */
+
+int
+t_shutdown(long s, int   how)
+{
+   struct socket *so;
+   int   err;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   so->so_error = 0;
+   INET_TRACE (INETM_SOCKET, ("INET:shutdown so %x how %d\n", so, how));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   err = soshutdown(so, how);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if (err != 0)
+   {
+      so->so_error = err;
+      return SOCKET_ERROR;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: t_socketclose()
+ * 
+ * PARAM1: long s
+ *
+ * RETURNS: 
+ */
+
+int
+t_socketclose(long s)
+{
+   struct socket *   so;
+   int   err;
+
+   so = LONG2SO(s);
+   SOC_CHECK(so);
+   so->so_error = 0;
+   INET_TRACE ((INETM_CLOSE|INETM_SOCKET), ("INET:close, so %lx\n",so));
+
+   LOCK_NET_RESOURCE(NET_RESID);
+   err = soclose(so);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   if (err != 0) 
+   {
+      /* do not do the following assignment since the socket structure
+         addressed by so has been freed by this point, jharan 12-10-98 */
+      /*      so->so_error = err;   */
+      return SOCKET_ERROR;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: sockargs ()
+ * 
+ * PARAM1: void *arg
+ * PARAM2: int arglen
+ * PARAM3: int type
+ *
+ * RETURNS: 
+ */
+
+static struct mbuf  * 
+sockargs (void * arg, 
+   int   arglen, 
+   int   type)
+{
+   struct mbuf *  m;
+
+   LOCK_NET_RESOURCE(NET_RESID);    /* protect mfreeq */
+   m = m_getwithdata (type, arglen);
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   if (m == NULL)
+      return NULL;
+   m->m_len = arglen;
+   MEMCPY(mtod (m, char *), arg, arglen);
+   return m;
+}
+
+
+
+
+/* the rest are NetPort additions and won't be covered in generic 
+ * socket documentation:
+ */
+
+
+/* FUNCTION: t_errno()
+ *
+ * t_errno() - return last error on a socket. Return value is 
+ * undefined if the socket has not previously reported an error. 
+ *
+ * 
+ * PARAM1: long s
+ *
+ * RETURNS: int               socket error code or
+ *                            ENOTSOCK if socket not found
+ */
+
+int
+t_errno(long s)
+{
+   struct socket *so = LONG2SO(s);
+   struct socket *tmp;
+   int errcode = ENOTSOCK;
+
+   LOCK_NET_RESOURCE(NET_RESID);    /* protect soq */
+
+   /* search socket queue for passed socket. This routine should
+    * not use SOC_CHECK since it can be ifdeffed out, and we must
+    * be ready to return EPIPE if the socket does not exist.
+    */
+   for (tmp = (struct socket *)(&soq); tmp; tmp = tmp->next)
+   {
+      if (tmp == so)  /* found socket, return error */
+      {
+         errcode = so->so_error;
+         break;
+      }
+   }
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+
+   return errcode;
+}
+
+
+
+
+#endif /* INCLUDE_TCP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket.c
new file mode 100644
index 0000000..2967788
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket.c
@@ -0,0 +1,1431 @@
+/*
+ * FILENAME: socket.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: socreate (), sobind(), solisten(), sofree(), 
+ * ROUTINES: soclose(), soabort(), soaccept(), soconnect(), sodisconnect(), 
+ * ROUTINES: sosend(), soreceive(), soshutdown(), sorflush(), sosetopt(), 
+ * ROUTINES: sogetopt(), sohasoutofband()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "protosw.h"
+#include "in_pcb.h"
+#include "ip.h"         /* for IP-layer socket options */
+#include "tcp.h"        /* for TCP-layer socket options */
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+
+
+/* default so_options value for new sockets. This can be set by applications 
+ * (user code) at runtime, but it will apply to ALL new sockets in the system.
+ */
+
+#define  SO_DEFAULTS    SO_OOBINLINE
+
+#ifdef SO_TCPSACK
+#define SO_TCPSACK_DEF SO_TCPSACK
+#else
+#define SO_TCPSACK_DEF  0
+#endif /* SO_TCPSACK */
+
+#ifdef SO_WINSCALE
+#define SO_WINSCALE_DEF SO_WINSCALE
+#else
+#define SO_WINSCALE_DEF 0
+#endif /* SO_WINSCALE */
+
+#ifdef SO_TIMESTAMP
+#define SO_TIMESTAMP_DEF SO_TIMESTAMP
+#else
+#define SO_TIMESTAMP_DEF   0
+#endif /* SO_TIMESTAMP */
+
+#ifdef SO_BIGCWND
+#define SO_BIGCWND_DEF SO_BIGCWND
+#else
+#define SO_BIGCWND_DEF  0
+#endif /* SO_BIGCWND */
+
+/* always force inline OOB data, big in others if defined in build */
+unshort socket_defaults = (SO_OOBINLINE | SO_TCPSACK_DEF |
+            SO_WINSCALE_DEF | SO_TIMESTAMP_DEF | SO_BIGCWND_DEF);
+
+/*
+ * Socket operation routines.
+ * These routines are called by the routines in
+ * sockcall.c or from a system process, and
+ * implement the semantics of socket operations by
+ * switching out to the protocol specific routines.
+ */
+
+#ifdef IP_MULTICAST
+int   ip_setmoptions(int optname, struct socket *so, void *arg);
+int   ip_getmoptions(int optname, struct socket *so, void *arg);
+int   ip_freemoptions(struct ip_moptions *imo);
+#endif   /* IP_MULTICAST */
+
+/* FUNCTION: socreate ()
+ * 
+ * PARAM1: int dom
+ * PARAM2: int type
+ * PARAM3: int proto
+ *
+ * RETURNS: 
+ */
+
+struct socket *   
+socreate (int dom, int type, int proto)
+{
+   struct protosw *prp;
+   struct socket *so;
+   int   error;
+   int rc;
+
+   if (proto)
+      prp = pffindproto(dom, proto, type);
+   else
+      prp = pffindtype(dom, type);
+   if (prp == 0)
+      return NULL;
+   if (prp->pr_type != type)
+      return NULL;
+   if ((so = SOC_ALLOC (sizeof (*so))) == NULL)
+      return NULL;
+   so->next = NULL;
+   putq(&soq,(qp)so);
+
+   so->so_options = socket_defaults;
+   so->so_domain = dom;
+   so->so_state = 0;
+   so->so_type = (char)type;
+   so->so_proto = prp;
+
+#ifdef IP_MULTICAST
+   so->inp_moptions = NULL;
+#endif   /* IP_MULTICAST */
+
+   so->so_req = PRU_ATTACH;
+   error = (*prp->pr_usrreq)(so,(struct mbuf *)0, LONG2MBUF((long)proto));
+   if (error) goto bad;
+
+   if (so_evtmap)
+   {                       
+      rc = (*so_evtmap_create) (so);
+      if (rc != 0)
+      {
+bad:   
+         so->so_state |= SS_NOFDREF;
+         sofree (so);
+         return NULL;   
+      }
+      /*
+       * Altera Niche Stack Nios port modification:
+       * Remove (void *) cast since -> owner is now TK_OBJECT
+       * to fix build warning.
+       */
+      so->owner = TK_THIS;
+   }
+
+   return so;
+}
+
+
+
+/* FUNCTION: sobind()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 0 if OK, else one of the socket error codes
+ */
+
+int
+sobind(struct socket * so, 
+   struct mbuf *  nam)
+{
+   int   error;
+
+   so->so_req = PRU_BIND;
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+   return (error);
+}
+
+
+
+/* FUNCTION: solisten()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: int backlog
+ *
+ * RETURNS: 0 if OK, else one of the socket error codes
+ */
+
+int
+solisten(struct socket * so, 
+   int   backlog)
+{
+   int   error;
+
+   so->so_req = PRU_LISTEN;
+   error = (*so->so_proto->pr_usrreq)(so,
+    (struct mbuf *)0, (struct mbuf *)0);
+   if (error) 
+   {
+      return (error);
+   }
+   if (so->so_q == 0) 
+   {
+      so->so_q = so;
+      so->so_q0 = so;
+      so->so_options |= SO_ACCEPTCONN;
+   }
+   if (backlog < 0)
+      backlog = 0;
+   so->so_qlimit = (char)MIN(backlog, SOMAXCONN);
+   return 0;
+}
+
+
+
+/* FUNCTION: sofree()
+ * 
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+sofree(struct socket * so)
+{
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: sofree, so %lx so_pcb %lx so_state %x so_head %lx\n",
+    so, so->so_pcb, so->so_state, so->so_head));
+
+   if (so->so_pcb || (so->so_state & SS_NOFDREF) == 0)
+      return;
+   if (so->so_head) 
+   {
+      if (!soqremque(so, 0) && !soqremque(so, 1))
+         panic("sofree");
+      so->so_head = 0;
+   }
+   sbrelease(&so->so_snd);
+   sorflush(so);
+#ifdef SAVE_SOCK_ENDPOINTS
+   if (so->so_endpoint)
+      _socket_free_entry (so);
+#endif   /* SAVE_SOCK_ENDPOINTS */
+
+#ifdef IP_MULTICAST
+   /* multicast opts? */
+   if (so->inp_moptions)
+	   ip_freemoptions(so->inp_moptions);
+#endif   /* IP_MULTICAST */
+
+   /* IP_TOS opts? */
+   if (so->so_optsPack)
+      SOCOPT_FREE(so->so_optsPack);
+	   
+   qdel(&soq, so);   /* Delete the socket entry from the queue */
+   
+   if (so_evtmap)  
+      (*so_evtmap_delete) (so);
+   
+   SOC_FREE(so);
+}
+
+
+/* FUNCTION: soclose()
+ * 
+ * Close a socket on last file table reference removal.
+ * Initiate disconnect if connected.
+ * Free socket when disconnect complete.
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+int
+soclose(struct socket * so)
+{
+   int   error =  0;
+   struct socket *   tmpso;
+   unsigned long endtime;
+
+   /* Check whether the closing socket is in the socket queue.  If it is
+    * not, return a EINVAL error code to the caller.
+    */
+   for ((tmpso=(struct socket *)soq.q_head);tmpso != NULL;tmpso=tmpso->next)
+   {
+      if (so == tmpso)
+         break;
+   }
+   if ( tmpso == NULL)
+      return EINVAL;
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: soclose, so %lx  so_pcb %lx so_state %x so_q %lx\n",
+    so, so->so_pcb, so->so_state, so->so_q));
+   if (so->so_options & SO_ACCEPTCONN)
+   {
+      while (so->so_q0 != so)
+         (void) soabort(so->so_q0);
+      while (so->so_q != so)
+         (void) soabort(so->so_q);
+   }
+   /* for datagram-oriented sockets, dispense with further tests */
+   if (so->so_type != SOCK_STREAM)
+   { 
+      so->so_req = PRU_DETACH;
+      error = (*so->so_proto->pr_usrreq)(so,
+       (struct mbuf *)0, (struct mbuf *)0);
+      goto discard;
+   }
+
+   if (so->so_pcb == 0)
+      goto discard;
+   if (so->so_state & SS_ISCONNECTED) 
+   {
+      if ((so->so_state & SS_ISDISCONNECTING) == 0) 
+      {
+         error = sodisconnect(so);
+         if (error)
+            goto drop;
+      }
+      if (so->so_options & SO_LINGER) 
+      {
+         if ((so->so_state & SS_ISDISCONNECTING) &&
+             (so->so_state & SS_NBIO))
+         {
+            goto drop;
+         }
+         endtime = cticks + (unsigned long)so->so_linger * TPS;         
+         while ((so->so_state & SS_ISCONNECTED) && (cticks < endtime))
+         {
+            tcp_sleep((char *)&so->so_timeo);
+         }
+      }
+      else  /* Linger option not set */
+      {
+         /* If socket still has send data just return now, leaving the 
+          * socket intact so the data can be sent. Socket should be cleaned
+          * up later by timers.
+          */
+         if(so->so_snd.sb_cc)
+         {
+            so->so_state |= SS_NOFDREF;   /* mark as OK to close */
+            return 0;
+         }
+      }
+   }
+drop:
+   if (so->so_pcb) 
+   {
+      int   error2;
+      so->so_req = PRU_DETACH;
+      error2 = (*so->so_proto->pr_usrreq)(so,
+       (struct mbuf *)0, (struct mbuf *)0);
+      if (error == 0)
+         error = error2;
+   }
+discard:
+   if (so->so_state & SS_NOFDREF)
+   {
+      /* panic("soclose");  - non-fatal - degrade to dtrap() for now */
+      dtrap();
+   }
+   so->so_state |= SS_NOFDREF;
+   sofree(so);
+   return (error);
+}
+
+
+
+/* FUNCTION: soabort()
+ * 
+ * Must be called at splnet...
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+int
+soabort(struct socket * so)
+{
+   so->so_req = PRU_ABORT;
+   return(*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0);
+}
+
+
+
+/* FUNCTION: soaccept()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf * nam
+ *
+ * RETURNS: 
+ */
+
+int
+soaccept(struct socket * so, 
+   struct mbuf *  nam)
+{
+   int   error;
+
+   if ((so->so_state & SS_NOFDREF) == 0)
+      panic("soaccept");
+   so->so_state &= ~SS_NOFDREF;
+   so->so_req = PRU_ACCEPT;
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+
+   return (error);
+}
+
+
+
+/* FUNCTION: soconnect()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf *nam
+ *
+ * RETURNS: 
+ */
+
+int
+soconnect(struct socket * so, 
+   struct mbuf *  nam)
+{
+   int   error;
+
+   if (so->so_options & SO_ACCEPTCONN)
+      return (EOPNOTSUPP);
+   /*
+    * If protocol is connection-based, can only connect once.
+    * Otherwise, if connected, try to disconnect first.
+    * This allows user to disconnect by connecting to, e.g.,
+    * a null address.
+    */
+   if (so->so_state & (SS_ISCONNECTED|SS_ISCONNECTING) &&
+       ((so->so_proto->pr_flags & PR_CONNREQUIRED) ||
+       (sodisconnect(so) != 0)))
+   {
+      error = EISCONN;
+   }
+   else
+   {
+      so->so_req = PRU_CONNECT;
+      error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, nam);
+   }
+   return error;
+}
+
+
+
+/* FUNCTION: sodisconnect()
+ * 
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+int
+sodisconnect(struct socket * so)
+{
+   int   error;
+
+   INET_TRACE (INETM_SOCKET|INETM_CLOSE,
+    ("INET: sodisconnect, so %lx so_state %x\n", so, so->so_state));
+
+   if ((so->so_state & SS_ISCONNECTED) == 0) 
+   {
+      error = ENOTCONN;
+      goto bad;
+   }
+   if (so->so_state & SS_ISDISCONNECTING) 
+   {
+      error = EALREADY;
+      goto bad;
+   }
+   so->so_req = PRU_DISCONNECT;
+   error = (*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0);
+
+bad:
+   return (error);
+}
+
+
+
+/* FUNCTION: sosend()
+ * 
+ * Send on a socket.
+ * If send must go all at once and message is larger than
+ * send buffering, then hard error.
+ * Lock against other senders.
+ * If must go all at once and not enough room now, then
+ * inform user that this would block and do nothing.
+ * Otherwise, if nonblocking, send as much as possible.
+ *
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf *nam
+ * PARAM3: char * data;
+ * PARAM4: int * data_length;
+ * PARAM5: int flags
+ *
+ * RETURNS: 0 if OK or BSD socket error code
+ */
+
+int
+sosend(struct socket *so, 
+       struct mbuf *nam,      /* sockaddr, if UDP socket, NULL if TCP */
+       char  *data,           /* data to send */
+       int   *data_length,    /* IN/OUT  length of (remaining) data */
+       int   flags)
+{
+   struct mbuf *head = (struct mbuf *)NULL;
+   struct mbuf *m;
+   int   space;
+   int   resid;
+   int   len;
+   int   error = 0;
+   int   dontroute;
+   int   first = 1;
+
+   resid = *data_length;
+
+   /*
+    * In theory resid should be unsigned.
+    * However, space must be signed, as it might be less than 0
+    * if we over-committed, and we must use a signed comparison
+    * of space and resid.  On the other hand, a negative resid
+    * causes us to loop sending 0-length segments to the protocol.
+    */
+   if (resid < 0)
+      return (EINVAL);
+
+   INET_TRACE (INETM_IO, ("INET:sosend: so %lx resid %d sb_hiwat %d so_state %x\n",
+               so, resid, so->so_snd.sb_hiwat, so->so_state));
+
+   if (sosendallatonce(so) && (resid > (int)so->so_snd.sb_hiwat))
+      return (EMSGSIZE);
+
+   dontroute = (flags & MSG_DONTROUTE) &&
+               ((so->so_options & SO_DONTROUTE) == 0) &&
+               (so->so_proto->pr_flags & PR_ATOMIC);
+
+#define     snderr(errno)     {  error =  errno;   goto  release; }
+
+restart:
+   sblock(&so->so_snd);
+   do 
+   {
+      if (so->so_error) 
+      {
+         error = so->so_error;
+         so->so_error = 0;          /* ??? */
+         goto release;
+      }
+      if (so->so_state & SS_CANTSENDMORE)
+         snderr(EPIPE);
+      if ((so->so_state & SS_ISCONNECTED) == 0) 
+      {
+         if (so->so_proto->pr_flags & PR_CONNREQUIRED)
+            snderr(ENOTCONN);
+         if (nam == 0)
+            snderr(EDESTADDRREQ);
+      }
+      if (flags & MSG_OOB)
+         space = 1024;
+      else 
+      {
+         space = (int)sbspace(&so->so_snd);
+         if ((sosendallatonce(so) && (space < resid)) ||
+             ((resid >= CLBYTES) && (space < CLBYTES) &&
+              (so->so_snd.sb_cc >= CLBYTES) &&
+              ((so->so_state & SS_NBIO) == 0) &&
+              ((flags & MSG_DONTWAIT) == 0)))
+         {
+            if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT))
+            {
+               if (first)
+                  error = EWOULDBLOCK;
+               goto release;
+            }
+            sbunlock(&so->so_snd);
+            sbwait(&so->so_snd);
+            goto restart;
+         }
+      }
+      if ( space <= 0 ) 
+      {
+         /* no space in socket send buffer - see if we can wait */
+         if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT))
+         {
+            if (first)     /* report first error */
+               error = EWOULDBLOCK;
+            goto release;
+         }
+         /* If blocking socket, let someone else run */
+         sbunlock(&so->so_snd);
+         sbwait(&so->so_snd);
+         goto restart;
+      }
+
+      while (space > 0) 
+      {
+         len = resid;
+         if ( so->so_type == SOCK_STREAM )
+         {
+            m = m_getwithdata(MT_TXDATA, len);
+            if (!m)   
+               snderr(ENOBUFS);
+            MEMCPY(m->m_data, data, len);
+            so->so_snd.sb_flags |= SB_MBCOMP;   /* allow compression */
+         }
+         else
+         {
+            m = m_get (M_WAIT, MT_TXDATA);
+            m->m_data = data;
+         }
+         INET_TRACE (INETM_IO,
+          ("sosend:got %d bytes so %lx mlen %d, off %d mtod %x\n",
+             len, so, m->m_len, m->m_off, mtod (m, caddr_t)));
+
+         *data_length -= len;
+         resid -= len;
+         data += len;
+         m->m_len = len;
+         if (head == (struct mbuf *)NULL)
+            head = m;
+         if (error)
+            goto release;
+         if (*data_length <= 0)
+            break;
+      }
+
+      if (dontroute)
+         so->so_options |= SO_DONTROUTE;
+
+      so->so_req = (flags & MSG_OOB) ? PRU_SENDOOB : PRU_SEND;
+      error = (*so->so_proto->pr_usrreq)(so, head, nam);
+
+      if (dontroute)
+         so->so_options &= ~SO_DONTROUTE;
+
+      head = (struct mbuf *)NULL;
+      first = 0;
+   } while ((resid != 0) && (error == 0));
+
+release:
+   sbunlock(&so->so_snd);  
+   if (head)
+      m_freem(head);
+   return error;
+}
+
+
+
+/* FUNCTION: soreceive()
+ * 
+ * Implement receive operations on a socket.
+ * We depend on the way that records are added to the sockbuf
+ * by sbappend*.  In particular, each record (mbufs linked through m_next)
+ * must begin with an address if the protocol so specifies,
+ * followed by an optional mbuf containing access rights if supported
+ * by the protocol, and then zero or more mbufs of data.
+ * In order to avoid blocking network interrupts for the entire time here,
+ * we splx() while doing the actual copy to user space.
+ * Although the sockbuf is locked, new data may still be appended,
+ * and thus we must maintain consistency of the sockbuf during that time.
+ *
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf **aname
+ * PARAM3: char * data
+ * PARAM4: int * datalen;
+ * PARAM5: int flags
+ *
+ * RETURNS: 
+ */
+
+int
+soreceive(struct socket * so, 
+   struct mbuf **aname,
+   char * data,
+   int * datalen,
+   int   flags)
+{
+   struct mbuf *  m;
+   int   len;
+   int   error =  0;
+   int   offset;
+   struct protosw *  pr =  so->so_proto;
+   struct mbuf *  nextrecord;
+   int   moff;
+   int   lflags;
+
+   if (aname)
+      *aname = 0;
+   if (flags & MSG_OOB) 
+   {
+      m = m_get (M_WAIT, MT_RXDATA);
+      if (m == NULL)
+         return ENOBUFS;
+      lflags = flags & MSG_PEEK;
+
+      so->so_req = PRU_RCVOOB;
+      error = (*pr->pr_usrreq)(so, m, LONG2MBUF((long)lflags));
+      if (error == 0)
+      {
+         do 
+         {
+            len = *datalen;
+            if (len > (int)m->m_len)
+               len = m->m_len;
+
+            MEMCPY(data, mtod(m, char*), len);
+            data += len;
+            *datalen = len;
+            m = m_free(m);
+         } while (*datalen && (error == 0) && m);
+      }
+
+      if (m)
+         m_freem(m);
+      return (error);
+   }
+
+restart:
+   sblock (&so->so_rcv);
+   INET_TRACE (INETM_IO,
+    ("INET:soreceive sbcc %d soerror %d so_state %d *datalen %d\n",
+    so->so_rcv.sb_cc, so->so_error, so->so_state, *datalen));
+
+   /* If no data is ready, see if we should wait or return */
+   if (so->so_rcv.sb_cc == 0) 
+   {
+      if (so->so_error) 
+      {
+         error = so->so_error;
+         so->so_error = 0;
+         goto release;
+      }
+      if (so->so_state & SS_CANTRCVMORE)
+         goto release;
+      if ((so->so_state & SS_ISCONNECTED) == 0 &&
+          (so->so_proto->pr_flags & PR_CONNREQUIRED)) 
+      {
+         error = ENOTCONN;
+         goto release;
+      }
+      if (*datalen == 0)
+         goto release;
+      if ((so->so_state & SS_NBIO) || (flags & MSG_DONTWAIT)) 
+      {
+         error = EWOULDBLOCK;
+         goto release;
+      }
+      sbunlock(&so->so_rcv);
+      sbwait(&so->so_rcv);
+      goto restart;
+   }
+   m = so->so_rcv.sb_mb;
+   if (m == 0)
+      panic("sorecv 1");
+   nextrecord = m->m_act;
+   if (pr->pr_flags & PR_ADDR) 
+   {
+      if (m->m_type != MT_SONAME) 
+      {
+         dprintf ("sorecv:type %d not nam", m->m_type);
+         panic("sorecv 2");
+      }
+      if (flags & MSG_PEEK) 
+      {
+         if (aname)
+            *aname = m_copy (m, 0, m->m_len);
+         m = m->m_next;
+      } else 
+      {
+         sbfree (&so->so_rcv, m);
+         if (aname) 
+         {
+            *aname = m;
+            m = m->m_next;
+            (*aname)->m_next = 0;
+            so->so_rcv.sb_mb = m;
+         } else 
+         {
+            MFREE(m, so->so_rcv.sb_mb);
+            m = so->so_rcv.sb_mb;
+         }
+         if (m)
+            m->m_act = nextrecord;
+      }
+   }
+   moff = 0;
+   offset = 0;
+   while (m && (*datalen > 0) && (error == 0))
+   {
+      if (m->m_type != MT_RXDATA && m->m_type != MT_HEADER)
+         panic("sorecv 3");
+      len = *datalen;
+      so->so_state &= ~SS_RCVATMARK;
+      if (so->so_oobmark && (len > (int)(so->so_oobmark - offset)))
+         len = (int)(so->so_oobmark - offset);
+      if (len > (int)(m->m_len - moff))
+         len = m->m_len - moff;
+
+      INET_TRACE (INETM_IO, ("INET: soreceive, so %lx %d bytes, flags %x\n",
+                  so, len, flags));
+
+      /*
+       * Copy mbufs info user buffer, then free them.
+       * Sockbuf must be consistent here (points to current mbuf,
+       * it points to next record) when we drop priority;
+       * we must note any additions to the sockbuf when we
+       * block interrupts again.
+       */
+
+      MEMCPY(data, (mtod(m, char *) + moff), len);
+      data += len;
+      *datalen -= len;
+
+      if (len == (int)(m->m_len - moff))
+      {
+         if (flags & MSG_PEEK) 
+         {
+            m = m->m_next;
+            moff = 0;
+         } else 
+         {
+            nextrecord = m->m_act;
+            sbfree(&so->so_rcv, m);
+            {
+               MFREE(m, so->so_rcv.sb_mb);
+               m = so->so_rcv.sb_mb;
+            }
+            if (m)
+               m->m_act = nextrecord;
+         }
+      } else 
+      {
+         if (flags & MSG_PEEK)
+            moff += len;
+         else 
+         {
+            m->m_data += len;
+            m->m_len -= len;
+            so->so_rcv.sb_cc -= len;
+         }
+      }
+      if (so->so_oobmark) 
+      {
+         if ((flags & MSG_PEEK) == 0) 
+         {
+            so->so_oobmark -= len;
+            if (so->so_oobmark == 0) 
+            {
+               so->so_state |= SS_RCVATMARK;
+               break;
+            }
+         } else
+            offset += len;
+      }
+   }
+
+   if ((flags & MSG_PEEK) == 0) 
+   {
+      if (m == 0)
+         so->so_rcv.sb_mb = nextrecord;
+      else if (pr->pr_flags & PR_ATOMIC)
+         (void) sbdroprecord(&so->so_rcv);
+      if (pr->pr_flags & PR_WANTRCVD && so->so_pcb)
+      {
+         so->so_req = PRU_RCVD;
+         (*pr->pr_usrreq)(so, (struct mbuf *)0,
+          (struct mbuf *)0);
+      }
+   }
+release:
+   sbunlock(&so->so_rcv);
+   return (error);
+}
+
+
+/* FUNCTION: soshutdown()
+ *
+ * PARAM1: struct socket *    socket structure
+ * PARAM2: int                shutdown action
+ *                               0 = shutdown read half of connection
+ *                               1 = shutdown write half of connection
+ *                               2 = shutdown both halves of connection
+ *
+ * RETURNS: int               0 if successful, else error code
+ */
+int
+soshutdown(struct socket *so, int how)
+{
+   how++;   /* convert 0,1,2 into 1,2,3 */
+   if (how & 1)   /* caller wanted READ or BOTH */
+      sorflush(so);
+
+   if (how & 2)   /* caller wanted WRITE or BOTH */
+   {
+      sbflush(&so->so_snd); /* flush the socket send queue */
+      so->so_req = PRU_SHUTDOWN;
+      return ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0));
+   }
+
+   return 0;
+}
+
+
+
+/* FUNCTION: sorflush()
+ * 
+ * PARAM1: struct socket *    socket structure
+ *
+ * RETURNS: none
+ *
+ * Closes the "read" half of the socket connection. No more data
+ * can be received on the socket, and any data currently in the 
+ * socket receive buffer is discarded. Wakeup any processes waiting
+ * on the socket.
+ */
+void
+sorflush(struct socket * so)
+{
+   struct sockbuf *sb =  &so->so_rcv;
+   int   s;
+
+   sblock(sb);
+   socantrcvmore(so);
+   sbunlock(sb);
+   sbrelease(sb);
+   MEMSET((char *)sb, 0, sizeof (*sb));
+   s = so->so_error;
+   so->so_error = ESHUTDOWN;
+   sorwakeup(so);
+   so->so_error = s;
+}
+
+
+
+/* FUNCTION: sosetopt()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: int optname
+ * PARAM3: void *arg
+ *
+ * RETURNS: 
+ */
+
+int
+sosetopt(struct socket * so, 
+   int   optname,
+   void *   arg)
+{
+   int   error =  0;
+
+   switch (optname) 
+   {
+   case SO_LINGER:
+      so->so_linger = (short)((struct linger *)arg)->l_linger;
+      /* fall thru... */
+
+   case SO_KEEPALIVE:
+   case SO_DONTROUTE:
+   case SO_BROADCAST:
+   case SO_REUSEADDR:
+   case SO_OOBINLINE:
+   case SO_TCPSACK:
+   case SO_NOSLOWSTART:
+#ifdef SUPPORT_SO_FULLMSS
+   case SO_FULLMSS:
+#endif
+      if (*(int *)arg) 
+         so->so_options |= optname;
+      else
+         so->so_options &= ~optname;
+      break;
+
+#ifdef TCP_BIGCWND
+   case SO_BIGCWND:
+      /* Set Large initial congestion window on this socket. This should
+       * only be done on TCP sockets, and only before they are opened.
+       */
+      if(so->so_type != SOCK_STREAM)
+         return EINVAL;
+      if (*(int *)arg)
+      {
+         so->so_options |= optname;
+         default_cwnd = TCP_MSS * (*(int *)arg);
+      }
+      else
+         so->so_options &= ~optname;    
+      break;
+#endif /* TCP_BIGCWND */
+
+   case SO_SNDBUF:
+   case SO_RCVBUF:
+      if (sbreserve(optname == SO_SNDBUF ?
+          &so->so_snd : &so->so_rcv,
+          (u_long) * (int *)arg) == 0) 
+      {
+         error = ENOBUFS;
+         goto bad;
+      }
+      break;
+
+   case SO_RCVTIMEO:
+      so->so_rcv.sb_timeo = *(short *)arg;
+      break;
+
+   case SO_NBIO:     /* set socket into NON-blocking mode */
+      so->so_state |= SS_NBIO;
+      break;
+
+   case SO_BIO:   /* set socket into blocking mode */
+      so->so_state &= ~SS_NBIO;
+      break;
+
+   case SO_NONBLOCK:    /* set blocking mode according to arg */
+      /* sanity check the arg parameter */
+      if (!arg)
+      {
+         error = ENP_PARAM;
+         break;
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (*(int *) arg)
+         so->so_state |= SS_NBIO;   /* set non-blocking mode */
+      else
+         so->so_state &= ~SS_NBIO;  /* set blocking mode */
+      break;
+
+#ifdef IP_MULTICAST
+
+   case IP_MULTICAST_IF:
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+   case IP_ADD_MEMBERSHIP:
+   case IP_DROP_MEMBERSHIP:
+      error = ip_setmoptions(optname, so, arg);
+      break;
+
+#endif   /* IP_MULTICAST */
+
+#ifdef IP_RAW
+
+   case IP_HDRINCL:
+      /* try to make sure that the argument pointer is valid */
+      if (arg == NULL)
+      {
+         error = ENP_PARAM;
+         break;
+      }
+      /* set the socket option flag based on the pointed-to argument */
+      if (*(int *)arg)
+         so->so_options |= SO_HDRINCL;
+      else
+         so->so_options &= ~SO_HDRINCL;
+      break;
+
+#endif   /* IP_RAW */
+
+#ifdef DO_DELAY_ACKS
+   case TCP_ACKDELAYTIME:
+   case TCP_NOACKDELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if(!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      if(optname == TCP_ACKDELAYTIME)
+         /* Convert MS to TPS */
+         tp->t_delacktime = (((*(int*)(arg))*TPS)/1000);
+      else
+         tp->t_delacktime = 0;
+
+      break;
+   }
+#endif   /* DO_DELAY_ACKS */
+
+   case TCP_NODELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if(!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      /* try to make sure that the argument pointer is valid */
+      if (arg == NULL)
+      {
+         error = ENP_PARAM;
+         break;
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (*(int *) arg)
+         tp->t_flags |= TF_NODELAY;   /* Disable Nagle Algorithm */
+      else
+         tp->t_flags &= ~TF_NODELAY;  /* Enable Nagle Algorithm */
+
+      break;
+   }
+
+#ifdef TCP_ZEROCOPY
+   case SO_CALLBACK:    /* install ZERO_COPY callback routine */
+      /*
+       * This generates warnings on many compilers, even when it's 
+       * doing the right thing. Just make sure the "void * arg" data
+       * pointer converts properly to a function pointer.
+       */
+      so->rx_upcall = (int (*)(struct socket *, void*, int))arg;
+      break;
+#endif   /* TCP_ZEROCOPY */
+
+   case SO_MAXMSG:
+   case TCP_MAXSEG:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if(!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      if (tp->t_state != TCPS_CLOSED)
+      {
+         error = EINVAL;
+         break;
+      }
+      tp->t_maxseg = *(int*)(arg);    /* set TCP MSS */
+      tp->t_flags |= TF_MAXSEG;   /* mark as user set max seg */
+      break;
+   }
+   default:
+      error = ENOPROTOOPT;
+      break;
+   }
+bad:
+   return (error);
+}
+
+
+
+/* FUNCTION: sogetopt()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: int optname
+ * PARAM3: void *val
+ *
+ * RETURNS: 
+ */
+
+int
+sogetopt(struct socket * so, 
+   int   optname,
+   void *   val)
+{
+   int   error =  0;
+
+   /* sanity check the val parameter */
+   if (!val)
+   {
+      return ENP_PARAM;
+   }
+
+   switch (optname) 
+   {
+   case SO_MYADDR:
+      /* Get my IP address. */
+      if (so->so_state & SS_ISCONNECTED)
+      {
+         *(u_long *)val = so->so_pcb->ifp->n_ipaddr;
+      }
+      else  /* not connected, use first iface */
+         *(u_long *)val = nets[0]->n_ipaddr;
+      break;
+   case SO_LINGER:
+      {
+         struct linger *   l  =  (struct  linger *)val;
+         l->l_onoff = so->so_options & SO_LINGER;
+         l->l_linger = so->so_linger;
+      }
+      break;
+
+   case SO_KEEPALIVE:
+   case SO_OOBINLINE:
+   case SO_DONTROUTE:
+   case SO_REUSEADDR:
+   case SO_BROADCAST:
+   case SO_TCPSACK:
+      *(int *)val = so->so_options & optname;
+      break;
+
+   case SO_SNDLOWAT:
+      *(int *)val = (int)so->so_snd.sb_lowat;
+      break;
+
+   case SO_RCVLOWAT:
+      *(int *)val = (int)so->so_rcv.sb_lowat;
+      break;
+
+   case SO_SNDBUF:
+      *(int *)val = (int)so->so_snd.sb_hiwat;
+      break;
+
+   case SO_RCVBUF:
+      *(int *)val = (int)so->so_rcv.sb_hiwat;
+      break;
+
+   case SO_RXDATA:   /* added, JB */
+      *(int *)val = (int)so->so_rcv.sb_cc;
+      break;
+
+   case SO_TXDATA:   /* added for rel 1.8 */
+      *(int *)val = (int)so->so_snd.sb_cc;
+      break;
+
+   case SO_TYPE:
+      *(int *)val = so->so_type;
+      break;
+
+   case SO_ERROR:
+      *(int *)val = so->so_error;
+      so->so_error = 0;
+      break;
+
+   case SO_MAXMSG:
+   case TCP_MAXSEG:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if(!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      *(int *)val = tp->t_maxseg;     /* Fill in TCP MSS for current socket */
+      break;
+   }
+ 
+   case SO_SNDTIMEO:
+      *(short*)val = so->so_snd.sb_timeo;
+      break;
+
+   case SO_RCVTIMEO:
+      *(short*)val = so->so_rcv.sb_timeo;
+      break;
+
+   case SO_HOPCNT:
+      *(int *)val = so->so_hopcnt;
+      break;
+
+   case SO_NONBLOCK:    /* get blocking mode according to val */
+      /* if the non-blocking I/O bit is set in the state */
+      if (so->so_state & SS_NBIO)
+         *(int *)val = 1;   /* return 1 in val */
+      else
+         *(int *)val = 0;     /* return 0 in val */
+      break;
+
+#ifdef IP_MULTICAST
+
+   case IP_MULTICAST_IF:
+   case IP_MULTICAST_TTL:
+   case IP_MULTICAST_LOOP:
+      error = ip_getmoptions(optname, so, val);
+      break;
+
+#endif   /* IP_MULTICAST */
+
+#ifdef IP_RAW
+
+   case IP_HDRINCL:
+      /* indicate based on header-include flag in socket state */
+      if (so->so_options & SO_HDRINCL)
+         *(int *)val = 1;
+      else
+         *(int *)val = 0;
+      break;
+
+#endif   /* IP_RAW */
+
+#ifdef DO_DELAY_ACKS
+   case TCP_ACKDELAYTIME:
+   case TCP_NOACKDELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if (!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      if (optname == TCP_ACKDELAYTIME)
+      {
+         /* Convert TPS to MS */
+         *(int*)(val) = (tp->t_delacktime * 1000)/TPS;
+      }
+      else
+      {
+         if (tp->t_delacktime == 0)
+            *(int *)val = 1;  /* NO ACK DELAY is Enabled */
+         else
+            *(int *)val = 0;  /* NO ACK DELAY is NOT Enabled */		 
+      }
+
+      break;
+   }
+#endif   /* DO_DELAY_ACKS */
+      
+   case TCP_NODELAY:
+   {
+      struct inpcb * inp;
+      struct tcpcb * tp;
+
+      if(so->so_type != SOCK_STREAM)
+      {
+         error = EINVAL;
+         break;
+      }
+      inp = (struct inpcb *)(so->so_pcb);
+      tp = intotcpcb(inp);
+      if (!tp)
+      {
+         error = ENOTCONN;
+         break;
+      }
+      /* try to make sure that the argument pointer is valid */
+      if (val == NULL)
+      {
+         error = ENP_PARAM;
+         break;
+      }
+      /* if contents of integer addressed by arg are non-zero */
+      if (tp->t_flags & TF_NODELAY)
+         *(int *)val = 1;  /* Nagle Algorithm is Enabled */
+      else
+         *(int *)val = 0;  /* Nagle Algorithm is NOT Enabled */
+
+      break;
+   }
+
+   default:
+      return ENOPROTOOPT;
+   }
+   return error;     /* no error */
+}
+
+
+
+/* FUNCTION: sohasoutofband()
+ * 
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+sohasoutofband(struct socket * so)
+{
+   so->so_error = EHAVEOOB;   /* WILL be picked up by the socket */
+   sorwakeup (so);
+}
+
+
+
+#endif /* INCLUDE_TCP */
+
+/* end of file socket.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket2.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket2.c
new file mode 100644
index 0000000..522fbb6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/socket2.c
@@ -0,0 +1,903 @@
+/*
+ * FILENAME: socket2.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ * Primitive routines for operating on sockets and socket buffers,
+ * Procedures to manipulate state flags of socket
+ * and do appropriate wakeups.  Normal sequence from the
+ * active (originating) side is that soisconnecting() is
+ * called during processing of connect() call,
+ * resulting in an eventual call to soisconnected() if/when the
+ * connection is established.  When the connection is torn down
+ * soisdisconnecting() is called during processing of disconnect() call,
+ * and soisdisconnected() is called when the connection to the peer
+ * is totally severed.  The semantics of these routines are such that
+ * connectionless protocols can call soisconnected() and soisdisconnected()
+ * only, bypassing the in-progress calls when setting up a ``connection''
+ * takes no time.
+ *
+ * From the passive side, a socket is created with
+ * two queues of sockets: so_q0 for connections in progress
+ * and so_q for connections already made and awaiting user acceptance.
+ * As a protocol is preparing incoming connections, it creates a socket
+ * structure queued on so_q0 by calling sonewconn().  When the connection
+ * is established, soisconnected() is called, and transfers the
+ * socket structure to so_q, making it available to accept().
+ * 
+ * If a socket is closed with sockets on either
+ * so_q0 or so_q, these sockets are dropped.
+ *
+ * If higher level protocols are implemented in
+ * the kernel, the wakeups done here will sometimes
+ * cause software-interrupt process scheduling.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: soisconnecting(), soisconnected(), 
+ * ROUTINES: soisdisconnecting(), soisdisconnected(), sonewconn(), 
+ * ROUTINES: soqinsque(), soqremque(), socantsendmore(), socantrcvmore(), 
+ * ROUTINES: sbselqueue(), sbwait(), sbwakeup(), sowakeup(), soreserve(), 
+ * ROUTINES: sbreserve(), sbrelease(), sbappend(), sbappendrecord(), 
+ * ROUTINES: sbappendaddr(), sbcompress(), sbflush(), sbdrop(), sbdropend(), 
+ * ROUTINES: sbdroprecord(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#include "ipport.h"
+#include "tcpport.h"
+#include "protosw.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+/* Initial TCP window sizes, etc. */
+extern   u_long   tcp_sendspace;
+extern   u_long   tcp_recvspace;
+extern   u_char   default_wind_scale;
+
+/* FUNCTION: soisconnecting()
+ *
+ * Called by the protocol layers when a socket is connecting. Sets
+ * the required flags and does the wakeup() call.
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+soisconnecting(struct socket * so)
+{
+   so->so_state &= ~(SS_ISCONNECTED|SS_ISDISCONNECTING);
+   so->so_state |= SS_ISCONNECTING;
+   tcp_wakeup ((char *)&so->so_timeo);
+}
+
+
+
+/* FUNCTION: soisconnected()
+ * 
+ * Called by the protocol layers when a socket has connected. Sets
+ * the required flags and does the wakeup() call.
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+soisconnected(struct socket * so)
+{
+   struct socket *   head  =  so->so_head;
+
+   if (head) 
+   {
+      if (soqremque(so, 0) == 0)
+         panic("soisconnected");
+      soqinsque(head, so, 1);
+      sorwakeup(head);
+      tcp_wakeup ((char *)&head->so_timeo);
+   }
+
+   so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+   so->so_state |= SS_ISCONNECTED;
+   so->so_error = 0;
+   tcp_wakeup  ((char *)&so->so_timeo);
+   sorwakeup (so);
+   sowwakeup (so);
+}
+
+
+
+/* FUNCTION: soisdisconnecting()
+ * 
+ * Called by the protocol layers when a socket is disconnecting. Sets
+ * the required flags and does the wakeup() calls.
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+soisdisconnecting(struct socket * so)
+{
+   so->so_state &= ~SS_ISCONNECTING;
+   so->so_state |= (SS_ISDISCONNECTING|SS_CANTRCVMORE|SS_CANTSENDMORE);
+   tcp_wakeup  ((char *)&so->so_timeo);   
+   sowwakeup (so);
+   sorwakeup (so);
+}
+
+
+
+/* FUNCTION: soisdisconnected()
+ * 
+ * Called by the protocol layers when a socket is disconnected. Sets
+ * the required flags and does the wakeup() calls.
+ * 
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+soisdisconnected(struct socket * so)
+{
+   if (so->so_state & SS_ISCONNECTING)
+      so->so_state |= SS_WASCONNECTING;
+   so->so_state &= ~(SS_ISCONNECTING|SS_ISCONNECTED|SS_ISDISCONNECTING);
+   so->so_state |= (SS_CANTRCVMORE|SS_CANTSENDMORE);
+   tcp_wakeup ((char *)&so->so_timeo);
+   sowwakeup (so);
+   sorwakeup (so);
+}
+
+
+/* FUNCTION: sonewconn()
+ * 
+ * When an attempt at a new connection is noted on a socket
+ * which accepts connections, sonewconn is called.  If the
+ * connection is possible (subject to space constraints, etc.)
+ * then we allocate a new structure, properly linked into the
+ * data structure of the original socket, and return this.
+ *
+ * PARAM1: struct socket *head
+ *
+ * RETURNS: 
+ */
+
+struct socket *   
+sonewconn(struct socket * head)
+{
+   struct socket *   so;
+   int rc;  
+
+   if (head->so_qlen + head->so_q0len > 3 * head->so_qlimit / 2)
+      goto bad;
+   if ((so = SOC_ALLOC (sizeof (*so))) == NULL)
+      goto bad;
+   so->next = NULL;
+   putq(&soq,(qp)so);      /* Place newly created socket in a queue */
+   so->so_type = head->so_type;
+   so->so_options = head->so_options &~ (unshort)SO_ACCEPTCONN;
+   so->so_linger = head->so_linger;
+   so->so_state = head->so_state | (unshort)SS_NOFDREF;
+   so->so_proto = head->so_proto;
+   so->so_timeo = head->so_timeo;
+   so->so_rcv.sb_hiwat = (u_int)tcp_recvspace;
+   so->so_snd.sb_hiwat = (u_int)tcp_sendspace;
+   soqinsque (head, so, 0);
+   so->so_req = PRU_ATTACH;
+   so->so_domain = head->so_domain;
+
+   if ((*so->so_proto->pr_usrreq)(so, (struct mbuf *)0, (struct mbuf *)0))
+      goto bad2;
+   if (so_evtmap)
+   {
+      rc = (*so_evtmap_create) (so);                       
+      if (rc != 0) goto bad2;
+      so->owner = head->owner;
+   }
+   return (so);
+   
+bad2:
+   (void) soqremque (so, 0);
+   qdel(&soq, so);   /* Delete the socket entry from the queue */
+   SOC_FREE(so);  /* Free the socket structure */
+bad:
+   return ((struct socket *)0);
+}
+
+
+
+/* FUNCTION: soqinsque()
+ * 
+ * PARAM1: struct socket * head
+ * PARAM2: struct socket * so
+ * PARAM3: int q
+ *
+ * RETURNS: 
+ */
+
+void
+soqinsque(struct socket * head, 
+   struct socket *   so,
+   int   q)
+{
+   so->so_head = head;
+   if (q == 0) 
+   {
+      head->so_q0len++;
+      so->so_q0 = head->so_q0;
+      head->so_q0 = so;
+   } else 
+   {
+      head->so_qlen++;
+      so->so_q = head->so_q;
+      head->so_q = so;
+   }
+}
+
+
+
+/* FUNCTION: soqremque()
+ * 
+ * PARAM1: struct socket * so
+ * PARAM2: int q
+ *
+ * RETURNS: 
+ */
+
+int
+soqremque(struct socket * so, int q)
+{
+   struct socket *   head, *  prev, *  next;
+
+   head = so->so_head;
+   prev = head;
+   for (;;) 
+   {
+      next = q ? prev->so_q : prev->so_q0;
+      if (next == so)
+         break;
+      if (next == head)
+         return (0);
+      prev = next;
+   }
+   if (q == 0) 
+   {
+      prev->so_q0 = next->so_q0;
+      head->so_q0len--;
+   } else 
+   {
+      prev->so_q = next->so_q;
+      head->so_qlen--;
+   }
+   next->so_q0 = next->so_q = 0;
+   next->so_head = 0;
+   return 1;
+}
+
+
+/* FUNCTION: socantsendmore()
+ * 
+ * Socantsendmore indicates that no more data will be sent on the
+ * socket; it would normally be applied to a socket when the user
+ * informs the system that no more data is to be sent, by the protocol
+ * code (in case PRU_SHUTDOWN).  Socantrcvmore indicates that no more data
+ * will be received, and will normally be applied to the socket by a
+ * protocol when it detects that the peer will send no more data.
+ * Data queued for reading in the socket may yet be read.
+ *
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 
+ */
+
+void
+socantsendmore(struct socket * so)
+{
+   so->so_state |= SS_CANTSENDMORE;
+   sowwakeup(so);
+}
+
+
+
+/* FUNCTION: socantrcvmore()
+ * 
+ * PARAM1: struct socket * so
+ *
+ * RETURNS: 
+ */
+
+void
+socantrcvmore(struct socket * so)
+{
+   so->so_state |= SS_CANTRCVMORE;
+   sorwakeup(so);
+}
+
+/*
+ * Socket select/wakeup routines.
+ */
+
+
+/* FUNCTION: sbselqueue()
+ * 
+ * Queue a process for a select on a socket buffer. 
+ *
+ * PARAM1: struct sockbuf * sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbselqueue(struct sockbuf * sb)
+{
+   sb->sb_flags |= SB_SEL;
+}
+
+
+/* FUNCTION: sbwait()
+ * 
+ * Wait for data to arrive at/drain from a socket buffer.
+ *
+ * PARAM1: struct sockbuf *sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbwait(struct sockbuf * sb)
+{
+   sb->sb_flags |= SB_WAIT;
+   tcp_sleep ((char *)&sb->sb_cc);
+   sb->sb_flags &= ~SB_WAIT;
+}
+
+
+
+/* FUNCTION: sbwakeup()
+ * 
+ *
+ * Wakeup processes waiting on a socket buffer.
+ *
+ * PARAM1: struct sockbuf *sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbwakeup(struct socket * so, struct sockbuf * sb)
+{
+   if (sb->sb_flags & SB_SEL) 
+   {
+      select_wait = 0;
+#ifndef SOCK_MAP_EVENTS
+      tcp_wakeup ((char *)&select_wait);
+#else
+      tcp_wakeup2 (so->owner);
+#endif      
+      sb->sb_flags &= ~SB_SEL;
+   }
+
+#ifdef SOCK_WAKEALWAYS  /* Always wake the socket? */
+   /* Systems Like Green Hills Integrity RTOS, need to process socket
+      input even if looks like no one is blocked on the socket */
+   tcp_wakeup ((char *)&sb->sb_cc); /* signal wake on socket */
+#else /* older BSD style code - only call tcp_wakeup if blocked */
+   if (sb->sb_flags & SB_WAIT)   /* is sockbuf's WAIT flag set? */
+   {
+      tcp_wakeup ((char *)&sb->sb_cc);   /* call port wakeup routine */
+   }
+#endif   /* SOCK_WAKEALWAYS */
+}
+
+
+/*
+ * Socket buffer (struct sockbuf) utility routines.
+ *
+ * Each socket contains two socket buffers: one for sending data and
+ * one for receiving data.  Each buffer contains a queue of mbufs,
+ * information about the number of mbufs and amount of data in the
+ * queue, and other fields allowing select() statements and notification
+ * on data availability to be implemented.
+ *
+ * Data stored in a socket buffer is maintained as a list of records.
+ * Each record is a list of mbufs chained together with the m_next
+ * field.  Records are chained together with the m_act field. The upper
+ * level routine soreceive() expects the following conventions to be
+ * observed when placing information in the receive buffer:
+ *
+ * 1. If the protocol requires each message be preceded by the sender's
+ *   name, then a record containing that name must be present before
+ *   any associated data (mbuf's must be of type MT_SONAME).
+ * 2. If the protocol supports the exchange of ``access rights'' (really
+ *   just additional data associated with the message), and there are
+ *   ``rights'' to be received, then a record containing this data
+ *   should be present (mbuf's must be of type MT_RIGHTS).
+ * 3. If a name or rights record exists, then it must be followed by
+ *   a data record, perhaps of zero length.
+ *
+ * Before using a new socket structure it is first necessary to reserve
+ * buffer space to the socket, by calling sbreserve().  This should commit
+ * some of the available buffer space in the system buffer pool for the
+ * socket (currently, it does nothing but enforce limits).  The space
+ * should be released by calling sbrelease() when the socket is destroyed.
+ */
+
+
+/* FUNCTION: soreserve()
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: u_long sndcc
+ * PARAM3: u_long rcvcc
+ *
+ * RETURNS: 
+ */
+
+int
+soreserve(struct socket * so, 
+   u_long   sndcc, 
+   u_long   rcvcc)
+{
+   if (sbreserve(&so->so_snd, sndcc) == 0)
+      goto bad;
+   if (sbreserve(&so->so_rcv, rcvcc) == 0)
+      goto bad2;
+   return (0);
+bad2:
+   sbrelease(&so->so_snd);
+bad:
+   return (ENOBUFS);
+}
+
+
+/* FUNCTION: sbreserve()
+ * 
+ *
+ * Allot mbufs to a sockbuf.
+ * Attempt to scale cc so that mbcnt doesn't become limiting
+ * if buffering efficiency is near the normal case.
+ *
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: u_long cc
+ *
+ * RETURNS: 
+ */
+
+int
+sbreserve(struct sockbuf * sb, u_long cc)
+{
+#ifdef COMPILER_32BIT
+   if (cc > (u_long)SB_MAX * CLBYTES / (2 * MSIZE + CLBYTES))
+      return (0);
+#endif
+   sb->sb_hiwat = cc;
+   sb->sb_mbmax = MIN(cc * 2, SB_MAX);
+   return (1);
+}
+
+
+/* FUNCTION: sbrelease()
+ *
+ * Free mbufs held by a socket, and reserved mbuf space.
+ *
+ * 
+ * PARAM1: struct sockbuf *sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbrelease(struct sockbuf * sb)
+{
+   sbflush(sb);
+   sb->sb_hiwat = sb->sb_mbmax = 0;
+}
+
+/*
+ * Routines to add and remove
+ * data from an mbuf queue.
+ *
+ * The routines sbappend() or sbappendrecord() are normally called to
+ * append new mbufs to a socket buffer, after checking that adequate
+ * space is available, comparing the function sbspace() with the amount
+ * of data to be added.  sbappendrecord() differs from sbappend() in
+ * that data supplied is treated as the beginning of a new record.
+ * To place a sender's address, optional access rights, and data in a
+ * socket receive buffer, sbappendaddr() should be used.  To place
+ * access rights and data in a socket receive buffer, sbappendrights()
+ * should be used.  In either case, the new data begins a new record.
+ * Note that unlike sbappend() and sbappendrecord(), these routines check
+ * for the caller that there will be enough space to store the data.
+ * Each fails if there is not enough space, or if it cannot find mbufs
+ * to store additional information in.
+ *
+ * Reliable protocols may use the socket send buffer to hold data
+ * awaiting acknowledgement.  Data is normally copied from a socket
+ * send buffer in a protocol with m_copy for output to a peer,
+ * and then removing the data from the socket buffer with sbdrop()
+ * or sbdroprecord() when the data is acknowledged by the peer.
+ */
+
+
+/* FUNCTION: sbappend()
+ * 
+ * Append mbuf chain m to the last record in the
+ * socket buffer sb.  The additional space associated
+ * the mbuf chain is recorded in sb.  Empty mbufs are
+ * discarded and mbufs are compacted where possible.
+ *
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: struct mbuf *m
+ *
+ * RETURNS: 
+ */
+
+void
+sbappend(struct sockbuf * sb, struct mbuf * m)
+{
+   struct mbuf *  n;
+
+   if (m == 0)
+      return;
+   ENTER_CRIT_SECTION(sb);
+   if ((n = sb->sb_mb) != NULL) 
+   {
+      while (n->m_act)
+         n = n->m_act;
+      while (n->m_next)
+         n = n->m_next;
+   }
+   sbcompress(sb, m, n);
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+/* FUNCTION: sbappendrecord()
+ *
+ * As above, except the mbuf chain begins a new record.
+ * 
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: struct mbuf *m0
+ *
+ * RETURNS: 
+ */
+
+void
+sbappendrecord(struct sockbuf * sb, 
+   struct mbuf *  m0)
+{
+   struct mbuf *  m;
+
+   if (m0 == 0)
+      return;
+   ENTER_CRIT_SECTION(sb);    /* protect so_rcv operations */
+   if ((m = sb->sb_mb) != NULL)
+      while (m->m_act)
+      m = m->m_act;
+   /*
+    * Put the first mbuf on the queue.
+    * Note this permits zero length records.
+    */
+   sballoc(sb, m0);
+   if (m)
+      m->m_act = m0;
+   else
+      sb->sb_mb = m0;
+   m = m0->m_next;
+   m0->m_next = 0;
+   sbcompress(sb, m, m0);
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+
+/* FUNCTION: sbappendaddr()
+ *
+ * Append address and data, and optionally, rights
+ * to the receive queue of a socket.  Return 0 if
+ * no space in sockbuf or insufficient mbufs.
+ *
+ * 
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: struct sockaddr *asa
+ * PARAM3: struct mbuf *m0
+ *
+ * RETURNS: 
+ */
+
+int
+sbappendaddr(struct sockbuf * sb, 
+   struct sockaddr * asa,
+   struct mbuf *  m0)
+{
+   struct mbuf *  m, *  n;
+   int   space =  sizeof   (*asa);
+
+   ENTER_CRIT_SECTION(sb);
+   for (m = m0; m; m = m->m_next)
+      space += m->m_len;
+   if (space > (int)sbspace(sb))
+   {
+      EXIT_CRIT_SECTION(sb);
+      return (0);
+   }
+   if ((m = m_getwithdata (MT_SONAME, sizeof (struct sockaddr))) == NULL)
+   {
+      EXIT_CRIT_SECTION(sb);
+      return 0;
+   }
+   *mtod(m, struct sockaddr *) = *asa;
+   m->m_len = sizeof (*asa);
+   sballoc (sb, m);
+   if ((n = sb->sb_mb) != NULL) 
+   {
+      while (n->m_act)
+         n = n->m_act;
+      n->m_act = m;
+   } else
+      sb->sb_mb = m;
+   if (m->m_next)
+      m = m->m_next;
+   if (m0)
+      sbcompress(sb, m0, m);
+
+   EXIT_CRIT_SECTION(sb);
+   return (1);
+}
+
+
+
+/* FUNCTION: sbcompress()
+ *
+ * Compress mbuf chain m into the socket
+ * buffer sb following mbuf n.  If n
+ * is null, the buffer is presumed empty.
+ * 
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: struct mbuf *m
+ * PARAM3: struct mbuf *n
+ *
+ * RETURNS: 
+ */
+
+void
+sbcompress(struct sockbuf * sb, 
+   struct mbuf *  m,
+   struct mbuf *  n)
+{
+
+   while (m) 
+   {
+      if (m->m_len == 0) 
+      {
+         m = m_free(m);
+         continue;
+      }
+      if (m->m_type != MT_RXDATA && 
+          m->m_type != MT_TXDATA && 
+          m->m_type != MT_SONAME) 
+      {
+         dprintf ("sbcomp:bad type %d\n", m->m_type);
+         panic ("sbcomp:bad");
+      }
+      /* If there is room for all the data in M in N, then
+       * just copy the data to N.  Note that sbdrop will 
+       * increment the n->m_data pointer, so that we must
+       * correct n->m_memsz.
+       */
+      if ( n && (sb->sb_flags & SB_MBCOMP) &&
+          ((n->m_len + m->m_len) <
+          n->m_memsz - (n->m_data - n->m_base) ) ) 
+      {
+         MEMCPY(n->m_data+n->m_len, m->m_data, m->m_len);
+         sballoc(sb, m);
+         n->m_len += m->m_len;
+         m = m_free(m);
+         continue;
+      }
+      sballoc(sb, m);
+      if (n)
+         n->m_next = m;
+      else
+         sb->sb_mb = m;
+      n = m;
+      m = m->m_next;
+      n->m_next = 0;
+   }
+}
+
+
+
+/* FUNCTION: sbflush()
+ *
+ * Free all mbufs in a sockbuf.
+ *
+ * 
+ * PARAM1: struct sockbuf *sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbflush(struct sockbuf * sb)
+{
+   ENTER_CRIT_SECTION(sb);
+   if (sb->sb_flags & SB_LOCK)
+      panic("sbflush");
+   while ((sb->sb_mbcnt) || (sb->sb_cc))
+      sbdrop (sb, (int)sb->sb_cc);
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+
+/* FUNCTION: sbdrop()
+ *
+ * Drop data from (the front of) a sockbuf.
+ * 
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: int len
+ *
+ * RETURNS: 
+ */
+
+void
+sbdrop(struct sockbuf * sb, int len)
+{
+   struct mbuf *  m, *  mn;
+   struct mbuf *  next;
+
+   ENTER_CRIT_SECTION(sb);
+   if ((m = sb->sb_mb) != NULL)
+      next = m->m_act;
+   else
+      next = NULL;
+   while (len > 0) 
+   {
+      if (m == 0) 
+      {
+         if (next == 0)
+            panic("sbdrop");
+         m = next;
+         next = m->m_act;
+         continue;
+      }
+      if (m->m_len > (unsigned)len) 
+      {
+         m->m_len -= len;
+         m->m_data += len;
+         sb->sb_cc -= len;
+         break;
+      }
+      len -= m->m_len;
+      sbfree (sb, m);
+      MFREE(m, mn);
+      m = mn;
+   }
+   while (m && m->m_len == 0) 
+   {
+      sbfree(sb, m);
+      MFREE(m, mn);
+      m = mn;
+   }
+   if (m) 
+   {
+      sb->sb_mb = m;
+      m->m_act = next;
+   } else
+      sb->sb_mb = next;
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+
+/* FUNCTION: sbdropend()
+ *
+ * Drop data from the end of a socket buffer
+ * 
+ * PARAM1: struct sockbuf *sb
+ * PARAM2: struct mbuf *m
+ *
+ * RETURNS: 
+ */
+
+void
+sbdropend(struct sockbuf * sb, struct mbuf * m)
+{
+   struct mbuf *  nmb, *   pmb;
+   int   len;
+   ENTER_CRIT_SECTION(sb);
+   len = mbuf_len(m);
+   if (len > 0)
+      m_adj(sb->sb_mb, -len); /* Adjust the lengths of the mbuf chain */
+   nmb = sb->sb_mb;
+   pmb = NULL;
+   if (sb->sb_mb->m_len == 0)
+      sb->sb_mb = NULL;
+   while (nmb && (nmb->m_len !=0))  /* Release mbufs that have a 0 len */
+   {
+      pmb = nmb;  /* Remember previous */
+      nmb = nmb->m_next;    
+   }
+   if (nmb && (nmb->m_len == 0)) /* Assume once 0 len found, all the rest */
+   {                             /* are zeroes */ 
+      if (pmb != NULL)
+         pmb->m_next = NULL;
+      m_freem(nmb);            
+   }
+   sb->sb_cc -= len;       /* Do a sbfree using the len */
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+/* FUNCTION: sbdroprecord()
+ *
+ * Drop a record off the front of a sockbuf
+ * and move the next record to the front.
+ *
+ * 
+ * PARAM1: struct sockbuf *sb
+ *
+ * RETURNS: 
+ */
+
+void
+sbdroprecord(struct sockbuf * sb)
+{
+   struct mbuf *  m, *  mn;
+
+   ENTER_CRIT_SECTION(sb);
+   m = sb->sb_mb;
+   if (m)
+   {  sb->sb_mb = m->m_act;
+      do 
+      {  sbfree(sb, m);
+         MFREE(m, mn);
+      } while ((m = mn) != NULL);
+         }
+   EXIT_CRIT_SECTION(sb);
+}
+
+
+#endif /* INCLUDE_TCP */
+
+/* end of file socket2.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/soselect.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/soselect.c
new file mode 100644
index 0000000..5facf13
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/soselect.c
@@ -0,0 +1,465 @@
+/*
+ * FILENAME: soselect.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * soselect.c Sockets library select() support. This will probably 
+ * need to be modified on a per-port basis. If your sockets code does 
+ * not rely on select() calls, then you can omit this file form the 
+ * build. 
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: t_select(), sock_selscan(), sock_select(), 
+ * ROUTINES: in_pcbnotify(), void (), tcp_notify(), FD_CLR(), FD_SET(), 
+ * ROUTINES: FD_ISSET(),
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef SO_SELECT  /* whole file can be ifdeffed out */
+
+#include "protosw.h"
+#include "in_pcb.h"
+
+/* Select routines in this file: */
+int sock_selscan(fd_set * ibits, fd_set * obits);
+int sock_select(long sock, int flags);
+
+#define  SOREAD      1
+#define  SOWRITE     2
+
+
+/* FUNCTION: t_select()
+ *
+ * t_select() - implement a UNIX-like socket select call. Causes the 
+ * calling process to block waiting for activity on any of a list of 
+ * sockets. Arrays of socket descriptions are passed for read, write, 
+ * and exception event. Any of these may be NULL if the event is not 
+ * of interest. A timeout is also passed, which is given in cticks 
+ * (TPS ticks per second). Returns the number of sockets which had an 
+ * event occur. 
+ *
+ * 
+ * PARAM1: fd_set *in
+ * PARAM2: fd_set *out
+ * PARAM3: fd_set *ex
+ * PARAM4: long tv
+ *
+ * RETURNS: 
+ */
+
+int
+t_select(fd_set * in,   /* lists of sockets to watch */
+   fd_set * out,
+   fd_set * ex,
+   long  tv)   /* ticks to wait */
+{
+   fd_set obits[3], ibits [3];
+   u_long   tmo;
+   int   retval   =  0;
+
+   MEMSET(&obits, 0, sizeof(obits));
+   MEMSET(&ibits, 0, sizeof(ibits));
+
+   if (in)
+      MEMCPY(&ibits[0], in, sizeof(fd_set));
+   if (out)
+      MEMCPY(&ibits[1], out, sizeof(fd_set));
+   if (ex)
+      MEMCPY(&ibits[2], ex, sizeof(fd_set));
+   tmo = cticks + tv;
+
+   /* if all the fd_sets are empty, just block;  else do a real select() */
+   if ((ibits[0].fd_count == 0) && (ibits[1].fd_count == 0) &&
+       (ibits[2].fd_count == 0))
+   {
+      if (tv > 0)      /* make sure we don't block on nothing forever */
+      {
+#ifdef SUPERLOOP
+         while (tmo > cticks)
+         {
+            tk_yield();
+         }
+#else
+         TK_SLEEP(tv);
+#endif
+      }
+   }
+   else
+   {
+#ifdef SOC_CHECK_ALWAYS
+      int i, j;
+      struct socket * so;
+
+      for (i = 0; i < 3; i++)
+      {
+         for (j = 0; j < ibits[i].fd_count; j++)
+         {
+            so = LONG2SO(ibits[i].fd_array[j]);
+            SOC_CHECK(so);
+         }
+      }
+#endif /* SOC_CHECK_ALWAYS */
+
+      /* Lock the net semaphore before going into selscan. Upon
+       * return we will either call tcp_sleep(), which unlocks the
+       * semaphore, or fall into the unlock statement.
+       */
+      LOCK_NET_RESOURCE(NET_RESID);
+      while ((retval = sock_selscan(ibits, obits)) == 0)
+      {
+         if (tv != -1L) 
+         {
+            if (tmo <= cticks)
+               break;
+         }
+         select_wait = 1;
+         tcp_sleep (&select_wait);
+      }
+      UNLOCK_NET_RESOURCE(NET_RESID);
+
+   }
+
+   if (retval >= 0)
+   {
+      if (in)
+         MEMCPY(in, &obits[0], sizeof(fd_set));
+      if (out)
+         MEMCPY(out, &obits[1], sizeof(fd_set));
+      if (ex)
+         MEMCPY(ex, &obits[2], sizeof(fd_set));
+   }
+   return retval;
+}
+
+
+/* FUNCTION: sock_selscan()
+ *
+ * sock_selscan() - internal non-blocking routine under t_select(). 
+ * This scans the two FD lists passed for activity by calling the 
+ * subroutine sock_select() on a per-socket basis. 
+ *
+ * 
+ * PARAM1: fd_set * ibits
+ * PARAM2: fd_set * obits
+ *
+ * RETURNS: 
+ */
+
+int
+sock_selscan(fd_set * ibits, fd_set * obits)
+{
+   fd_set *in, *out;
+   int   which;
+   int   sock;
+   int   flag  =  0;
+   int   num_sel  =  0;
+
+   for (which = 0; which < 3; which++)
+   {
+      switch (which)
+      {
+      case 0:
+         flag = SOREAD; break;
+
+      case 1:
+         flag = SOWRITE; break;
+
+      case 2:
+         flag = 0; break;
+      }
+      in = &ibits [which];
+      out = &obits [which];
+      for (sock = 0; sock < (int)in->fd_count; sock++)
+      {
+         if (sock_select (in->fd_array[sock], flag))
+         {
+            FD_SET(in->fd_array[sock], out);
+            num_sel++;
+         }
+      }
+   }
+   return num_sel;
+}
+
+
+/* FUNCTION: sock_select()
+ *
+ * sock_select - handle the select logic for a single event on a 
+ * single socket. This is called multiple times from sock_selscan 
+ * above. Retuns 1 if socket is ready for event, 0 if not. 
+ *
+ * 
+ * PARAM1: long sock
+ * PARAM2: int flag
+ *
+ * RETURNS: 
+ */
+
+int
+sock_select(long sock, int flag)
+{
+   struct socket *   so;
+   int   ready =  0;
+
+   so = LONG2SO(sock);
+
+   switch (flag) 
+   {
+   case SOREAD:
+      /* can we read something from so? */
+      if (so->so_rcv.sb_cc)
+      {
+         ready = 1;
+         break;
+      }
+      if (so->so_state & SS_CANTRCVMORE)
+      {  ready = 1;
+         break;
+      }
+      if (so->so_qlen)  /* attach is ready */
+      {
+         ready = 1;
+         break;
+      }
+
+#ifdef TCP_ZEROCOPY
+      /* zerocopy sockets with a callback set should wbe awakened
+      if there is pending data which has been upcalled */
+      if ((so->rx_upcall) && (so->so_state & SS_UPCALLED))
+      {
+         so->so_state &= ~SS_UPCALLED; /* clear flag */
+         {
+            ready = 1;
+            break;
+         }
+      }
+#endif   /* TCP_ZEROCOPY */
+
+      /* fall to here if so is not ready to read */
+      so->so_rcv.sb_flags |= SB_SEL;   /* set flag for select wakeup */
+      break;
+
+   case SOWRITE:
+      if ((sbspace(&(so)->so_snd) > 0) && 
+          ((((so)->so_state&SS_ISCONNECTED) || 
+            ((so)->so_proto->pr_flags&PR_CONNREQUIRED)==0) || 
+           ((so)->so_state & SS_CANTSENDMORE)))
+      {
+         ready = 1;
+         break;
+      }
+      sbselqueue (&so->so_snd);
+      break;
+
+   case 0:
+      if (so->so_oobmark || (so->so_state & SS_RCVATMARK))
+      {
+         ready = 1;
+         break;
+      }
+      if (so->so_error &&
+          (so->so_error != EINPROGRESS) &&
+          (so->so_error != EWOULDBLOCK))
+      {
+         ready = 1;
+         break;
+      }
+      sbselqueue(&so->so_rcv);
+      break;
+   }
+
+   return ready;
+}
+
+
+/* FUNCTION: in_pcbnotify()
+ *
+ * Pass some notification to all connections of a protocol
+ * associated with address dst.  Call the protocol specific
+ * routine (if any) to handle each connection.
+ *
+ * 
+ * PARAM1: struct inpcb *head
+ * PARAM2: struct in_addr *dst
+ * PARAM3: int errnum
+ * PARAM4: void (*notify
+ *
+ * RETURNS: 
+ */
+
+void
+in_pcbnotify(struct inpcb * head, 
+   struct in_addr *  dst,
+   int   errnum,
+   void (*notify) __P ((struct inpcb *)))
+{
+   struct inpcb * inp, *   oinp;
+
+   for (inp = head->inp_next; inp != head;) 
+   {
+      if (inp->inp_faddr.s_addr != dst->s_addr ||
+          inp->inp_socket == 0) 
+      {
+         inp = inp->inp_next;
+         continue;
+      }
+      if (errnum) 
+         inp->inp_socket->so_error = errnum;
+      oinp = inp;
+      inp = inp->inp_next;
+      if (notify)
+         (*notify)(oinp);
+   }
+}
+
+
+
+/* FUNCTION: tcp_notify()
+ * 
+ * Notify a tcp user of an asynchronous error;
+ * just wake up so that he can collect error status.
+ *
+ * 
+ * PARAM1: struct inpcb *inp
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_notify(struct inpcb * inp)
+{
+   tcp_wakeup(&inp->inp_socket->so_timeo);
+   sorwakeup(inp->inp_socket);
+   sowwakeup(inp->inp_socket);
+}
+
+
+/* the next three routines are derived from FD_XXX() macros, which is how they 
+are traditionally implemented. */
+
+
+/* FUNCTION: ifd_clr()
+ * 
+ * PARAM1: long               socket
+ * PARAM2: fd_set *           file descriptor set
+ *
+ * RETURNS: none
+ *
+ * Removes the socket from the file descriptor set, and
+ * compacts the fd_set.
+ */
+
+void
+ifd_clr(long sock, fd_set *set)
+{
+   u_int i;
+
+   for (i = 0; i < set->fd_count ; i++) 
+   {
+      if (set->fd_array[i] == sock)
+      {
+         while (i + 1 < set->fd_count)
+         {
+            set->fd_array[i] = set->fd_array[i + 1];
+            i++;
+         }
+         set->fd_count--;
+         return;
+      }
+   }
+
+#ifdef NPDEBUG
+   dtrap(); /* socket wasn't found in array */
+#endif
+}
+
+
+
+/* FUNCTION: ifd_set()
+ * 
+ * PARAM1: long               socket
+ * PARAM2: fd_set *           file descriptor set
+ *
+ * RETURNS: none
+ *
+ * Adds the socket to the file descriptor set. dtrap() is
+ * called if the fd_set structure is already full.
+ */
+
+void
+ifd_set(long sock, fd_set *set)
+{
+   if (set->fd_count < FD_SETSIZE)
+      set->fd_array[set->fd_count++] = sock;
+#ifdef NPDEBUG
+   else
+      dtrap();
+#endif
+}
+
+
+
+/* FUNCTION: ifd_isset()
+ * 
+ * PARAM1: long               socket
+ * PARAM2: fd_set *           file descriptor set
+ *
+ * RETURNS: int               TRUE if socket is a member of the fd_set
+ *
+ * Tests if a socket is a member of a file descriptor set.
+ */
+
+int   /* actually, boolean */
+ifd_isset(long sock, fd_set *set)
+{
+   u_int   i;
+
+   for (i = 0; i < set->fd_count ; i++)
+   {
+      if (set->fd_array[i] == sock)
+         return TRUE;
+   }
+   return FALSE;
+}
+
+
+
+/* FUNCTION: ifd_get()
+ * 
+ * PARAM1: unsigned int       file descriptor set index
+ * PARAM2: fd_set *           file descriptor set
+ *
+ * RETURNS: long              socket or INVALID_SOCKET
+ *
+ * If index is less than the number of elements in the fd_set array,
+ * returns the index_th element, otherwise returns INVALID_SOCKET.
+ *
+ * NOTE: This is not part of the original FD_XXX() functionality.
+ */
+
+long
+ifd_get(unsigned i, fd_set *set)
+{
+   if (i < set->fd_count)
+      return set->fd_array[i];
+   else
+   {
+#ifdef NPDEBUG
+      dtrap();
+#endif
+      return INVALID_SOCKET;
+   }
+}
+
+#endif   /* SO_SELECT */
+#endif /* INCLUDE_TCP */
+
+/* end of file socket.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_fsm.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_fsm.h
new file mode 100644
index 0000000..fcd3254
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_fsm.h
@@ -0,0 +1,111 @@
+/*
+ * FILENAME: tcp_fsm.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ * TCP FSM state definitions.
+ * Per RFC793, September, 1981.
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#ifndef _TCP_FSM_H
+#define  _TCP_FSM_H  1
+
+#define     TCP_NSTATES    11
+
+#define     TCPS_CLOSED          0  /* closed */
+#define     TCPS_LISTEN          1  /* listening for connection */
+#define     TCPS_SYN_SENT        2  /* active, have sent syn */
+#define     TCPS_SYN_RECEIVED    3  /* have send and received syn */
+/* states < TCPS_ESTABLISHED are those where connections not established */
+#define     TCPS_ESTABLISHED     4  /* established */
+#define     TCPS_CLOSE_WAIT      5  /* rcvd fin, waiting for close */
+/* states > TCPS_CLOSE_WAIT are those where user has closed */
+#define     TCPS_FIN_WAIT_1      6  /* have closed, sent fin */
+#define     TCPS_CLOSING      7  /* closed xchd FIN; await FIN ACK */
+#define     TCPS_LAST_ACK        8  /* had fin and close; await FIN ACK */
+/* states > TCPS_CLOSE_WAIT && < TCPS_FIN_WAIT_2 await ACK of FIN */
+#define     TCPS_FIN_WAIT_2      9  /* have closed, fin is acked */
+#define     TCPS_TIME_WAIT       10 /* in 2*msl quiet wait after close */
+
+#define     TCPS_HAVERCVDSYN(s)     ((s)  >= TCPS_SYN_RECEIVED)
+
+/* This macro was changed per customer issue report: 12/23/05
+Panic seen in function “dtom” after the 2MSL TCP timer expires
+A FIN/ACK is received by the NetStack after the server has unilaterally 
+closed the connection. NetStack has already sent a FIN towards the client. 
+The FIN/ACK is processed by the TCP layer (tcp_input()) and incorrectly 
+sent to the TCP reassembly queue because this should happen only during the 
+TCP established state. As a result of this, the reassembly queue pointers 
+indicate data is available. The socket is kept until the 2 MSL timer 
+expires (about 2 minutes). At that point the clock_tick thread in the 
+NetStack performs the cleanup of the socket and the associated tcp control 
+block structure. When it tries to free the mbufs in the reassembly queue 
+it fails because although the pointers indicate data is present, 
+all the mbufs have been freed up at that point. This causes the dtom function to panic. 
+ */
+#define     TCPS_HAVERCVDFIN(s)     ((s)  >= TCPS_TIME_WAIT)
+
+#ifdef   TCPOUTFLAGS
+/*
+ * Flags used when sending segments in tcp_output.
+ * Basic flags (TH_RST,TH_ACK,TH_SYN,TH_FIN) are totally
+ * determined by state, with the proviso that TH_FIN is sent only
+ * if all data queued for output is included in the segment.
+ */
+u_char   tcp_outflags[TCP_NSTATES]  =
+{
+   TH_RST|TH_ACK,             /* CLOSED */
+   0,                         /* LISTEN */
+   TH_SYN,                    /* SYN SENT */
+   TH_SYN|TH_ACK,             /* SYN RECEIVED */
+   TH_ACK,                    /* ESTABLISHED */
+   TH_ACK,                    /* CLOSE WAIT */
+   TH_FIN|TH_ACK,             /* FIN WAIT 1 */
+   TH_FIN|TH_ACK,             /* CLOSING */
+   TH_FIN|TH_ACK,             /* LAST ACK */
+   TH_ACK,                    /* FIN WAIT 2 */
+   TH_ACK,                    /* TIME_WAIT */
+};
+#endif /* TCPOUTFLAGS */
+
+#endif
+
+/* end of file tcp_fsm.h */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_in.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_in.c
new file mode 100644
index 0000000..d11fe60
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_in.c
@@ -0,0 +1,2184 @@
+/*
+ * FILENAME: tcp_in.c
+ *
+ * Copyright 1997-2008 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: TCP
+ *
+ * ROUTINES: tcp_reass(), tcp_input(), tcp_dooptions(), 
+ * ROUTINES: tcp_pulloutofband(), tcp_xmit_timer(), tcp_mss(), 
+ * ROUTINES: in_localaddr(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "in_pcb.h"
+#include "ip.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+#ifdef IP_V6
+#include "socket6.h"
+#endif   /* IP_V6 */
+
+#define  TRACE_RESET 1
+#ifdef TRACE_RESET  /* this can be usefull for tracing tcp_input() logic: */
+int      dropline;
+#define  GOTO_DROP   {  dropline=__LINE__;   goto  drop; }
+#define  GOTO_DROPWITHRESET   {  dropline=__LINE__;   goto  dropwithreset; }
+#else /* the production flavor: */
+#define  GOTO_DROP   {  goto  drop; }
+#define  GOTO_DROPWITHRESET   {  goto  dropwithreset; }
+#endif
+
+char     tcpprintfs  =  0;
+char     tcprexmtthresh =  3;
+struct   tcpiphdr tcp_saveti;
+
+
+int   tcp_reass   __P ((struct tcpcb *, struct tcpiphdr *, struct mbuf *));
+void  tcp_xmit_timer(struct tcpcb * tp);
+extern   void  tcp_pulloutofband __P ((struct socket *, struct tcpiphdr *, 
+            struct mbuf *));
+extern   void  tcp_dooptions  __P ((struct tcpcb *, struct mbuf *, 
+            struct tcpiphdr *));
+#ifdef IP_V6
+int ip6_tcpmss(struct socket * so, NET ifp);
+#endif
+
+/* FUNCTION: tcp_reass()
+ * 
+ * Insert segment ti into reassembly queue of tcp with
+ * control block tp.  tcp_input() does the common case inline
+ * (segment is the next to be received on an established connection,
+ * and the queue is empty), avoiding linkage into and removal
+ * from the queue and repetition of various conversions.
+ * Set DELACK for segments received in order, but ack immediately
+ * when segments are out of order (so fast retransmit can work).
+ *
+ * PARAM1: struct tcpcb *tp
+ * PARAM2: struct tcpiphdr *ti
+ * PARAM3: struct mbuf *ti_mbuf
+ *
+ * RETURNS:  Return TH_FIN if reassembly now includes a segment with FIN.
+ */
+
+int
+tcp_reass(struct tcpcb * tp, 
+   struct tcpiphdr * ti,
+   struct mbuf *  ti_mbuf)
+{
+   struct tcpiphdr * q;
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+   struct mbuf *  m;
+   int   flags;
+
+   /*
+    * Call with ti==0 after become established to
+    * force pre-ESTABLISHED data up to user socket.
+    */
+   if (ti == 0)
+      goto present;
+
+   /*
+    * Find a segment which begins after this one does.
+    */
+   for (q = tp->seg_next; q != (struct tcpiphdr *)tp;
+       q = (struct tcpiphdr *)q->ti_next)
+   {
+      if (SEQ_GT(q->ti_seq, ti->ti_seq))
+      break;
+   }
+
+   /*
+    * If there is a preceding segment, it may provide some of
+    * our data already.  If so, drop the data from the incoming
+    * segment.  If it provides all of our data, drop us.
+    */
+   if ((struct tcpiphdr *)q->ti_prev != (struct tcpiphdr *)tp) 
+   {
+      long  i;
+      q = (struct tcpiphdr *)q->ti_prev;
+      /* conversion to int (in i) handles seq wraparound */
+      i = q->ti_seq + q->ti_len - ti->ti_seq;
+      if (i > 0) 
+      {
+         if (i >= (long)ti->ti_len) 
+         {
+            tcpstat.tcps_rcvduppack++;
+            tcpstat.tcps_rcvdupbyte += ti->ti_len;
+            GOTO_DROP;
+         }
+         m_adj (ti_mbuf, (int)i);
+         ti->ti_len -= (short)i;
+         ti->ti_seq += (tcp_seq)i;
+      }
+      q = (struct tcpiphdr *)(q->ti_next);
+   }
+   tcpstat.tcps_rcvoopack++;
+   tcpstat.tcps_rcvoobyte += ti->ti_len;
+
+   /*
+    * While we overlap succeeding segments trim them or,
+    * if they are completely covered, dequeue them.
+    */
+   while (q != (struct tcpiphdr *)tp) 
+   {
+      int   i  =  (int)((ti->ti_seq +  ti->ti_len) -  q->ti_seq);
+      if (i <= 0)
+         break;
+      if (i < (int)(q->ti_len))
+      {
+         q->ti_seq += i;
+         q->ti_len -= (u_short)i;
+         m_adj (dtom(q), (int)i);
+         break;
+      }
+      q = (struct tcpiphdr *)q->ti_next;
+      m = dtom(q->ti_prev);
+      remque (q->ti_prev);
+      m_freem (m);
+   }
+
+   /*
+    * Stick new segment in its place.
+    */
+   insque(ti, q->ti_prev);
+
+present:
+   /*
+    * Present data to user, advancing rcv_nxt through
+    * completed sequence space.
+    */
+   if (TCPS_HAVERCVDSYN (tp->t_state) == 0)
+      return (0);
+   ti = tp->seg_next;
+   if (ti == (struct tcpiphdr *)tp || ti->ti_seq != tp->rcv_nxt)
+      return (0);
+   if (tp->t_state == TCPS_SYN_RECEIVED && ti->ti_len)
+      return (0);
+   do 
+   {
+      tp->rcv_nxt += ti->ti_len;
+      flags = ti->ti_flags & TH_FIN;
+      remque(ti);
+      m = dtom(ti);
+      ti = (struct tcpiphdr *)ti->ti_next;
+      if (so->so_state & SS_CANTRCVMORE)
+         m_freem (m);
+      else
+         sbappend (&so->so_rcv, m);
+   } while (ti != (struct tcpiphdr *)tp && ti->ti_seq == tp->rcv_nxt);
+      sorwakeup(so);
+   return (flags);
+drop:
+   /**m_freem (dtom(ti));**/
+   m_freem (ti_mbuf);
+   return (0);
+}
+
+
+/* FUNCTION: tcp_input()
+ *
+ * TCP input routine, follows pages 65-76 of the
+ * protocol specification dated September, 1981 very closely.
+ *
+ * 
+ * PARAM1: struct mbuf * m
+ * PARAM2: NET ifp - iface packet was received on
+ *
+ * RETURNS: void
+ */
+
+void
+tcp_input(struct mbuf * m, NET ifp)
+{
+#ifdef IP_V4
+   struct ip * pip;
+   struct in_addr laddr;
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   /* Storage for received packet's IPv6 addresses on stack. */
+   ip6_addr    ip6_src;
+   ip6_addr    ip6_dst;
+#endif   /* IP_V6 */
+   struct tcpiphdr * ti;
+   struct inpcb * inp;
+   struct mbuf *  om =  0;
+   int   len,  tlen, off;
+   struct tcpcb * tp =  0;
+   int   tiflags;
+   struct socket *   so =  NULL;
+   int   todrop,  acked,   ourfinisacked, needoutput  =  0;
+   int   dropsocket  =  0;
+   long  iss   =  0;
+   tcp_win  rx_win;     /* scaled window from received segment */
+
+#ifdef DO_TCPTRACE
+   int   ostate;
+#endif
+
+
+   tcpstat.tcps_rcvtotal++;
+   TCP_MIB_INC(tcpInSegs);    /* keep MIB stats */
+
+#ifdef IP_V4
+#ifdef IP_V6     /* skip test on v4  only builds */
+   if(m->pkt->type == IPTP)   /* IPv4 packet */
+#endif
+   {
+      /*
+       * Get IP and TCP header together in first mbuf.
+       * Note: IP leaves IP header in first mbuf.
+       */
+      pip = mtod(m, struct ip *);
+      if (pip->ip_ver_ihl > 0x45)   /* IP v4, 5 dword hdr len */
+      {
+         np_stripoptions(pip, (struct mbuf *)m);
+         pip = mtod(m, struct ip *);
+      }
+      if (m->m_len < ((sizeof (struct ip) + sizeof (struct tcphdr))))
+      {
+         tcpstat.tcps_rcvshort++;
+         return;
+      }
+      tlen = pip->ip_len;     /* this was fudged by IP layer */
+
+      /* The following is needed in the cases where the size of the
+       * overlay structure is larger than the size of the ip header.
+       * This can happen if the ih_next and ih_prev pointers in the
+       * overlay structure are larger than 32 bit pointers.
+       */
+      ti = (struct tcpiphdr *)(m->m_data + sizeof(struct ip) - 
+         sizeof(struct ipovly));
+      if ((char *)ti < m->pkt->nb_buff)
+      {
+         panic("tcp_input");
+      }
+   }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+#ifdef IP_V4
+   else        /* dual-mode requires else to avoid compiler warnings */
+#endif /* IP_V4 */
+   if(m->pkt->type == htons(0x86DD))   /* IPv6 packet */
+   {
+      struct ipv6 * pip6;
+      pip6 = m->pkt->ip6_hdr;
+      tlen = htons(pip6->ip_len);
+      if(tlen < sizeof (struct tcphdr))
+      {
+         tcpstat.tcps_rcvshort++;
+         return;
+      }
+
+      /* "ti" is partial overlay structure design for IPv4. It includes 
+       * the TCP header as it's last 20 bytes. Since the tcp_reassm() logic
+       * will overwrite the IPv6 src & dest addresses in the IP header, 
+       * we save these in local storage before using "ti".
+       */
+      IP6CPY(&ip6_src, &pip6->ip_src);
+      IP6CPY(&ip6_dst, &pip6->ip_dest);
+
+      ti = (struct tcpiphdr *)(m->m_data - sizeof(struct ipovly));
+      if ((char *)ti < m->pkt->nb_buff)
+      {
+         panic("tcp_input");
+      }
+   }
+   else
+   {
+      dtrap();
+      return;
+   }
+#endif   /* IP_V6 */
+
+   /*
+    * Check that TCP offset makes sense,
+    * pull out TCP options and adjust length.
+    */
+
+   off = GET_TH_OFF(ti->ti_t) << 2;
+   if (off < sizeof (struct tcphdr) || off > tlen) 
+   {
+#ifdef DO_TCPTRACE
+      tcp_trace("tcp off: src %x off %d\n", ti->ti_src, off);
+#endif
+      tcpstat.tcps_rcvbadoff++;
+      TCP_MIB_INC(tcpInErrs);   /* keep MIB stats */
+      GOTO_DROP;
+   }
+   tlen -= (int)off;
+   ti->ti_len = (u_short)tlen;
+   if (off > sizeof (struct tcphdr)) 
+   {
+      int olen;      /* length of options field */
+      u_char * op;   /* scratch option pointer */
+
+      olen = off - sizeof (struct tcphdr);   /* get options length */
+      om = m_getwithdata (MT_RXDATA, olen);  /* get mbuf for opts */
+      if (om == 0)
+         GOTO_DROP;
+      om->m_len = olen;       /* set mbuf length */
+      /* set pointer to options field at end of TCP header */
+      if(m->pkt->type == htons(0x86DD))   /* IPv6 packet */
+         op = (u_char*)(m->m_data + 20);  /* past TCP header */
+      else
+         op = (u_char*)(m->m_data + 40);  /* past IP + TCP */
+      MEMCPY(om->m_data, op, olen); /* copy to new mbuf */
+
+      /* strip options from data mbuf. This actually just cuts the first 
+       * m_len bytes from the TCP header, but it leaves the mbuf members 
+       * set so the adjustment below does the right thing.
+       */
+      m->m_data += om->m_len;
+      m->m_len -= om->m_len;
+   }
+   tiflags = ti->ti_flags;
+
+#if (BYTE_ORDER == LITTLE_ENDIAN)
+   /* Convert TCP protocol specific fields to host format. */
+   ti->ti_seq = ntohl(ti->ti_seq);
+   ti->ti_ack = ntohl(ti->ti_ack);
+   ti->ti_urp = ntohs(ti->ti_urp);
+#endif   /* endian */
+
+
+   /*
+    * Locate pcb for segment.
+    */
+findpcb:
+
+   switch(m->pkt->type)
+   {
+#ifdef IP_V4
+   case  IPTP:   /* IPv4 packet */
+      /* Drop TCP and IP headers; TCP options were dropped above. */
+      m->m_data += 40;
+      m->m_len -= 40;
+
+      inp = in_pcblookup(&tcb, ti->ti_src.s_addr, ti->ti_sport, 
+         ti->ti_dst.s_addr, ti->ti_dport, INPLOOKUP_WILDCARD);
+      break;
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   case htons(0x86DD):   /* IPv6 packet */
+      /* Drop TCP header; TCP options were dropped above. */
+      m->m_data += 20;
+      m->m_len -= 20;
+
+      inp = ip6_pcblookup(&tcb, &ip6_src, ti->ti_sport, 
+         &ip6_dst, ti->ti_dport, INPLOOKUP_WILDCARD);
+      break;
+#endif   /* IP_V6 */
+   default:
+      dtrap();
+      return;
+   }
+
+   
+   /*
+    * If the state is CLOSED (i.e., TCB does not exist) then
+    * all data in the incoming segment is discarded.
+    * If the TCB exists but is in CLOSED state, it is embryonic,
+    * but should either do a listen or a connect soon.
+    */
+   if (inp == 0)
+      GOTO_DROPWITHRESET;
+   tp = intotcpcb (inp);
+   if (tp == 0)
+      GOTO_DROPWITHRESET;
+   if (tp->t_state == TCPS_CLOSED)
+      GOTO_DROP;
+   so = inp->inp_socket;
+#ifdef DO_TCPTRACE
+   if (so->so_options & SO_DEBUG) 
+   {
+      ostate = tp->t_state;
+      tcp_saveti = *ti;
+   }
+#endif
+
+   /* figure out the size of the other guy's receive window */
+   rx_win = (tcp_win)(ntohs(ti->ti_win));    /* convert endian */
+
+#ifdef TCP_WIN_SCALE
+   /* Both the WINDSCLAE flag and send_wind_scale should be set if he 
+    * negtitiated this at connect itme.
+    */
+   if((tp->t_flags & TF_WINSCALE) &&
+      (tp->snd_wind_scale))
+   {
+      rx_win <<= tp->snd_wind_scale;         /* apply scale */
+   }
+#endif /* TCP_WIN_SCALE */
+
+   if (so->so_options & SO_ACCEPTCONN) 
+   {
+      so = sonewconn(so);
+      if (so == 0)
+         GOTO_DROP;
+      /*
+       * This is ugly, but ....
+       *
+       * Mark socket as temporary until we're
+       * committed to keeping it.  The code at
+       * ``drop'' and ``dropwithreset'' check the
+       * flag dropsocket to see if the temporary
+       * socket created here should be discarded.
+       * We mark the socket as discardable until
+       * we're committed to it below in TCPS_LISTEN.
+       */
+      dropsocket++;
+
+      inp = (struct inpcb *)so->so_pcb;
+      inp->ifp = ifp;      /* save iface to peer */
+
+      switch(so->so_domain)
+      {
+#ifdef IP_V4
+      case AF_INET:
+         inp->inp_laddr = ti->ti_dst;
+#ifdef IP_PMTU
+         inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr);
+#else    /* not compiled for pathmtu, guess based on iface */
+         inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40);
+#endif   /* IP_PMTU */
+         break;
+#endif   /* end v4 */
+
+#ifdef IP_V6
+      case AF_INET6:
+         IP6CPY(&inp->ip6_laddr, &ip6_dst);
+         inp->inp_pmtu = ip6_pmtulookup(&ip6_src, ifp);
+         break;
+#endif   /* end v6 */
+      }
+
+      inp->inp_lport = ti->ti_dport;
+      tp = intotcpcb(inp);
+      tp->t_state = TCPS_LISTEN;
+   }
+
+   /*
+    * Segment received on connection.
+    * Reset idle time and keep-alive timer.
+    */
+   tp->t_idle = 0;
+   tp->t_timer[TCPT_KEEP] = tcp_keepidle;
+
+   /*
+    * Process options if not in LISTEN state,
+    * else do it below (after getting remote address).
+    */
+   if (om && tp->t_state != TCPS_LISTEN) 
+   {
+      tcp_dooptions(tp, om, ti);
+      om = 0;
+   }
+
+   acked = (int)(ti->ti_ack - tp->snd_una);
+
+#ifdef TCP_SACK
+   /* If we received a TCP SACK header, indicate we need output now */
+   if(tp->t_flags & TF_SACKREPLY)
+   {
+      needoutput = 1;            /* set tcp_input local flag */
+   }
+   /* If new data has been acked and we have a sack hole list 
+    * for the peer then see if the ack covers any sack holes
+    */
+   if((acked > 0) &&
+      (tp->sack_hole_start[0] != 0) )
+   {
+      int i,j;
+      for (i = 0; i < SACK_BLOCKS; i++)
+      {
+         /* see if the ack covers this sack hole */
+         if(ti->ti_ack >= tp->sack_hole_end[i])
+         {
+            /* if hole is not the last one in the list, move up 
+             * the trainling holes 
+             */
+            if((i < (SACK_BLOCKS - 1)) && 
+               (tp->sack_hole_start[i + 1] != 0))
+            {
+               for(j = i; j < SACK_BLOCKS - 1; j++)
+               {
+                  tp->sack_hole_start[j] = tp->sack_hole_start[j + 1];
+                  tp->sack_hole_end[j] = tp->sack_hole_end[j + 1];
+               }
+            }
+            else  /* hole is at end of list */
+            {
+               /* delete the hole */
+               tp->sack_hole_start[i] = tp->sack_hole_end[i] = 0;
+            }
+         }
+      }
+   }
+#endif /* TCP_SACK */
+
+
+   /*
+    * Calculate amount of space in receive window,
+    * and then do TCP input processing.
+    * Receive window is amount of space in rcv queue,
+    * but not less than advertised window.
+    */
+   { long win;
+
+      win = (long)sbspace(&so->so_rcv);
+      if (win < 0)
+         win = 0;
+      tp->rcv_wnd = (tcp_win)MAX((u_long)win, (tp->rcv_adv - tp->rcv_nxt));
+   }
+
+
+   /*
+    * Header prediction: check for the two common cases
+    * of a uni-directional data xfer.  If the packet has
+    * no control flags, is in-sequence, the window didn't
+    * change and we're not retransmitting, it's a
+    * candidate.  If the length is zero and the ack moved
+    * forward, we're the sender side of the xfer.  Just
+    * free the data acked & wake any higher level process
+    * that was blocked waiting for space.  If the length
+    * is non-zero and the ack didn't move, we're the
+    * receiver side.  If we're getting packets in-order
+    * (the reassembly queue is empty), add the data to
+    * the socket buffer and note that we need a delayed ack.
+    */
+   if ((tp->t_state == TCPS_ESTABLISHED) &&
+       ((tiflags & (TH_SYN|TH_FIN|TH_RST|TH_URG|TH_ACK)) == TH_ACK) &&
+       (ti->ti_seq == tp->rcv_nxt) &&
+       (rx_win && rx_win == tp->snd_wnd) &&
+       (tp->snd_nxt == tp->snd_max))
+   {
+      if (ti->ti_len == 0)
+      {
+         if (SEQ_GT(ti->ti_ack, tp->snd_una) &&
+             SEQ_LEQ(ti->ti_ack, tp->snd_max) &&
+             tp->snd_cwnd >= tp->snd_wnd) 
+         {
+            /*
+             * this is a pure ack for outstanding data.
+             */
+            ++tcpstat.tcps_predack;
+            if (tp->t_rttick && 
+#ifdef TCP_TIMESTAMP
+               ((tp->t_flags & TF_TIMESTAMP) == 0) && 
+#endif /* TCP_TIMESTAMP */
+               (SEQ_GT(ti->ti_ack, tp->t_rtseq)))
+            {
+               tcp_xmit_timer(tp);
+            }
+
+            tcpstat.tcps_rcvackpack++;
+            tcpstat.tcps_rcvackbyte += acked;
+            sbdrop(&so->so_snd, acked);
+            tp->snd_una = ti->ti_ack;
+            m_freem(m);
+
+            /*
+             * If all outstanding data are acked, stop
+             * retransmit timer, otherwise restart timer
+             * using current (possibly backed-off) value.
+             * If process is waiting for space,
+             * wakeup/selwakeup/signal.  If data
+             * are ready to send, let tcp_output
+             * decide between more output or persist.
+             */
+            if (tp->snd_una == tp->snd_max)
+               tp->t_timer[TCPT_REXMT] = 0;
+            else if (tp->t_timer[TCPT_PERSIST] == 0)
+               tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+
+            if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL))
+               sowwakeup(so);
+
+            /* If there is more data in the send buffer, and some is
+             * still unsent, then call tcp_output() to try to send it
+             */
+            if (so->so_snd.sb_cc > (tp->snd_nxt - tp->snd_una))
+               (void) tcp_output(tp);
+            return;
+         }
+      }
+      else if (ti->ti_ack == tp->snd_una &&
+          tp->seg_next == (struct tcpiphdr *)tp &&
+          ti->ti_len <= sbspace(&so->so_rcv))
+      {
+         int   adv;
+
+#ifdef TCP_ZEROCOPY
+         /* This may be a window probe sent because a zerocopy application
+          * has closed the TCP window by sitting on all the bigbufs. If so,
+          * we want to drop this byte and send an ACK for the pervious one.
+          */
+         if (so->rx_upcall && (ti->ti_len == 1) && (bigfreeq.q_len < 2))
+         {
+            goto drop_probe;
+         }
+#endif   /* TCP_ZEROCOPY */
+
+         /* this may also be a garden-variety probe received because
+          * the socket sendbuf was full.
+          */
+         if(tp->rcv_wnd == 0)
+         {
+#ifdef TCP_ZEROCOPY
+drop_probe:
+#endif   /* TCP_ZEROCOPY */
+            /* we should probably do some elegant handling of the TCP state
+             * info in this seg, but Windows NT 4.0 has a nasty bug where it
+             * will hammer us mericilessly with these probes (one customer
+             * reports thousands per second) so we just dump it ASAP to
+             * save cycles.
+             */
+            tcpstat.tcps_rcvwinprobe++;
+            m_freem (m);      /* free the received mbuf */
+            tcp_output(tp);   /* send the ack now... */
+            return;
+         }
+
+         /*
+          * this is a pure, in-sequence data packet
+          * with nothing on the reassembly queue and
+          * we have enough buffer space to take it.
+          */
+         ++tcpstat.tcps_preddat;
+         tp->rcv_nxt += ti->ti_len;
+         tcpstat.tcps_rcvpack++;
+         tcpstat.tcps_rcvbyte += ti->ti_len;
+         /*
+          * Add data to socket buffer.
+          */
+         sbappend(&so->so_rcv, m);
+         sorwakeup(so);
+#ifdef TCP_ZEROCOPY
+         /* if it's a zerocopy socket, push data up to user */
+         if (so->rx_upcall)
+            tcp_data_upcall(so);
+#endif   /* TCP_ZEROCOPY */
+
+         /*
+          * If this is a short packet, then ACK now - with Nagel
+          *   congestion avoidance sender won't send more until
+          *   he gets an ACK.
+          */
+         if (tiflags & TH_PUSH)
+            tp->t_flags |= TF_ACKNOW;
+         else
+            tp->t_flags |= TF_DELACK;
+
+         /* see if we need to send an ack */
+         adv = (int)(tp->rcv_wnd - (tcp_win)(tp->rcv_adv - tp->rcv_nxt));
+
+         if ((adv >= (int)(tp->t_maxseg * 2)) ||
+             (tp->t_flags & TF_ACKNOW))
+         {
+#ifdef DO_DELAY_ACKS
+            if(tp->t_delacktime)   /* doing delayed acks on timer */
+            {
+               if(tp->t_delackcur != 0)  /* ack timeout not set? */
+                  tp->t_delackcur = tp->t_delacktime;  /* set it */
+               tp->t_flags |= TF_DELACK;
+               tp->t_flags &= ~TF_ACKNOW;
+               return;
+            }
+#endif   /* DO_DELAY_ACKS */
+
+            tp->t_flags |= TF_ACKNOW;
+            tp->t_flags &= ~TF_DELACK;
+            tcp_output(tp);   /* send the ack now... */
+         }
+
+         return;
+      }
+   }
+
+   switch (tp->t_state) 
+   {
+
+   /*
+    * If the state is LISTEN then ignore segment if it contains an RST.
+    * If the segment contains an ACK then it is bad and send a RST.
+    * If it does not contain a SYN then it is not interesting; drop it.
+    * Don't bother responding if the destination was a broadcast.
+    * Otherwise initialize tp->rcv_nxt, and tp->irs, select an initial
+    * tp->iss, and send a segment:
+    *     <SEQ=ISS><ACK=RCV_NXT><CTL=SYN,ACK>
+    * Also initialize tp->snd_nxt to tp->iss+1 and tp->snd_una to tp->iss.
+    * Fill in remote peer address fields if not previously specified.
+    * Enter SYN_RECEIVED state, and process any other fields of this
+    * segment in this state.
+    */
+   case TCPS_LISTEN: 
+   {
+         struct mbuf *  am;
+
+         if (tiflags & TH_RST)
+            GOTO_DROP;
+         if (tiflags & TH_ACK)
+            GOTO_DROPWITHRESET;
+         if ((tiflags & TH_SYN) == 0)
+            GOTO_DROP;
+         if(in_broadcast(ti->ti_dst.s_addr))
+            GOTO_DROP;
+         am = m_getwithdata (MT_SONAME, sizeof (struct sockaddr));
+         if (am == NULL)
+            GOTO_DROP;
+
+#ifdef IP_V4
+         if(inp->inp_socket->so_domain == AF_INET)
+         {
+         struct sockaddr_in * sin;
+         am->m_len = sizeof (struct sockaddr_in);
+         sin = mtod(am, struct sockaddr_in *);
+         sin->sin_family = AF_INET;
+         sin->sin_addr = ti->ti_src;
+         sin->sin_port = ti->ti_sport;
+         /* Assuming pcbconnect will work, we put the sender's address in 
+          * the inp_laddr (after saving a local laddr copy). If the connect
+          * fails we restore the inpcb before going to drop:
+          */
+         laddr = inp->inp_laddr;    /* save tmp laddr */
+         if (inp->inp_laddr.s_addr == INADDR_ANY)
+            inp->inp_laddr = ti->ti_dst;
+         if (in_pcbconnect (inp, am)) 
+         {
+            inp->inp_laddr = laddr;
+            (void) m_free(am);
+            GOTO_DROP;
+         }
+         
+         inp->ifp = ifp;      /* set interface for conn.*/
+         
+         (void) m_free (am);
+         }
+#endif   /* end v4 */
+#ifdef IP_V6
+         if(inp->inp_socket->so_domain == AF_INET6)
+         {
+            struct sockaddr_in6 * sin;
+            int      local_unspecified = FALSE;
+                      
+            am->m_len = sizeof (struct sockaddr_in6);
+            sin = mtod(am, struct sockaddr_in6 *);
+            sin->sin6_family = AF_INET6;
+            IP6CPY(&sin->sin6_addr, &ip6_src);
+            sin->sin6_port = ti->ti_sport;
+            /* if socket has no local address, copy in pkt dest */
+            if(IP6EQ(&inp->ip6_laddr, &ip6unspecified))
+            {
+               IP6CPY(&inp->ip6_laddr, &ip6_dst);
+               local_unspecified = TRUE;  /* set flag in case connect fails */
+            }
+            
+            inp->ifp = ifp;      /* set interface for conn
+                                    for routing, maybe changed by ip6_pcbconnect */
+                        
+            if (ip6_pcbconnect (inp, am))
+            {
+               if(local_unspecified)   /* need to restore unspecified addr? */
+                  IP6CPY(&inp->ip6_laddr, &ip6unspecified);
+               (void) m_free(am);
+               GOTO_DROP;
+            }
+            (void) m_free(am);
+         }
+#endif   /* end v6 */
+
+         tp->t_template = tcp_template(tp);
+         if (tp->t_template == 0) 
+         {
+            SETTP(tp, tcp_drop(tp, ENOBUFS));
+            dropsocket = 0;      /* socket is already gone */
+            GOTO_DROP;
+         }
+         if (om) 
+         {
+            tcp_dooptions(tp, om, ti);
+            om = 0;
+         }
+         if (iss)
+            tp->iss = iss;
+         else
+            tp->iss = tcp_iss;
+         tcp_iss += (unsigned)(TCP_ISSINCR/2);
+         tp->irs = ti->ti_seq;
+         tcp_sendseqinit(tp);
+         tcp_rcvseqinit(tp);
+         tp->t_flags |= TF_ACKNOW;
+         tp->t_state = TCPS_SYN_RECEIVED;
+         tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT;
+         dropsocket = 0;      /* committed to socket */
+         tcpstat.tcps_accepts++;
+         goto trimthenstep6;
+      }
+
+   /*
+    * If the state is SYN_SENT:
+    *   if seg contains an ACK, but not for our SYN, drop the input.
+    *   if seg contains a RST, then drop the connection.
+    *   if seg does not contain SYN, then drop it.
+    * Otherwise this is an acceptable SYN segment
+    *   initialize tp->rcv_nxt and tp->irs
+    *   if seg contais ack then advance tp->snd_una
+    *   if SYN has been acked change to ESTABLISHED else SYN_RCVD state
+    *   arrange for segment to be acked (eventually)
+    *   continue processing rest of data/controls, beginning with URG
+    */
+   case TCPS_SYN_SENT:
+      inp->ifp = ifp;
+      if ((tiflags & TH_ACK) &&
+          (SEQ_LEQ(ti->ti_ack, tp->iss) ||
+          SEQ_GT(ti->ti_ack, tp->snd_max)))
+      {
+         GOTO_DROPWITHRESET;
+      }
+      if (tiflags & TH_RST) 
+      {
+         if (tiflags & TH_ACK)
+            SETTP(tp, tcp_drop(tp, ECONNREFUSED));
+         GOTO_DROP;
+      }
+      if ((tiflags & TH_SYN) == 0)
+         GOTO_DROP;
+      if (tiflags & TH_ACK) 
+      {
+         tp->snd_una = ti->ti_ack;
+         if (SEQ_LT(tp->snd_nxt, tp->snd_una))
+            tp->snd_nxt = tp->snd_una;
+      }
+      tp->t_timer[TCPT_REXMT] = 0;
+      tp->irs = ti->ti_seq;
+      tcp_rcvseqinit(tp);
+      if (inp->inp_laddr.s_addr != ti->ti_dst.s_addr) 
+      {
+         /* 
+          * the IP interface may have changed address since we sent our SYN
+          * (e.g. PPP brings link up as a result of said SYN and gets new
+          * address via IPCP); if so we need to update the inpcb and the
+          * TCP header template with the new address.
+          */
+         if ((m->pkt->net != NULL)
+             && (m->pkt->net->n_ipaddr == ti->ti_dst.s_addr)) 
+      /* send an ack */
+         {
+            inp->inp_laddr = ti->ti_dst;
+            if (tp->t_template != NULL)
+               tp->t_template->ti_src = ti->ti_dst;
+         }
+      }
+      tp->t_flags |= TF_ACKNOW;
+      if (tiflags & TH_ACK && SEQ_GT(tp->snd_una, tp->iss)) 
+      {
+         tcpstat.tcps_connects++;
+         tp->t_state = TCPS_ESTABLISHED;
+         soisconnected (so);
+         tp->t_maxseg = tcp_mss(so);
+         (void) tcp_reass (tp, (struct tcpiphdr *)0, m);
+         /*
+          * if we didn't have to retransmit the SYN,
+          * use its rtt as our initial srtt & rtt var.
+          */
+         if (tp->t_rttick) 
+         {
+            tcp_xmit_timer(tp);
+         }
+      } else
+         tp->t_state = TCPS_SYN_RECEIVED;
+
+      trimthenstep6:
+      /*
+       * Advance ti->ti_seq to correspond to first data byte.
+       * If data, trim to stay within window,
+       * dropping FIN if necessary.
+       */
+      ti->ti_seq++;
+      if ((tcp_win)ti->ti_len > tp->rcv_wnd) 
+      {
+         todrop = ti->ti_len - (u_short)tp->rcv_wnd;
+         /* XXX work around 4.2 m_adj bug */
+         if (m->m_len) 
+         {
+            m_adj(m, -todrop);
+         }
+         else 
+         {
+            /* skip tcp/ip header in first mbuf */
+            m_adj(m->m_next, -todrop);
+         }
+         ti->ti_len = (u_short)tp->rcv_wnd;
+         tiflags &= ~TH_FIN;
+         tcpstat.tcps_rcvpackafterwin++;
+         tcpstat.tcps_rcvbyteafterwin += todrop;
+      }
+      tp->snd_wl1 = ti->ti_seq - 1;
+      tp->rcv_up = ti->ti_seq;
+      goto step6;
+   }
+
+   /*
+    * States other than LISTEN or SYN_SENT.
+    * First check that at least some bytes of segment are within 
+    * receive window.  If segment begins before rcv_nxt,
+    * drop leading data (and SYN); if nothing left, just ack.
+    */
+   todrop = (int)(tp->rcv_nxt - ti->ti_seq);
+   if (todrop > 0) 
+   {
+      if (tiflags & TH_SYN) 
+      {
+         tiflags &= ~TH_SYN;
+         ti->ti_seq++;
+         if (ti->ti_urp > 1) 
+            ti->ti_urp--;
+         else
+            tiflags &= ~TH_URG;
+         todrop--;
+      }
+      /*
+       * Altera Niche Stack Nios port modification:
+       * Add parenthesis to remove implicit order of operaton
+       * & possible build warning.
+       */
+      if ((todrop > (int)ti->ti_len) ||
+          ((todrop == (int)ti->ti_len) && 
+          (tiflags&TH_FIN) == 0)) 
+      {
+         tcpstat.tcps_rcvduppack++;
+         tcpstat.tcps_rcvdupbyte += ti->ti_len;
+         /*
+          * If segment is just one to the left of the window,
+          * check two special cases:
+          * 1. Don't toss RST in response to 4.2-style keepalive.
+          * 2. If the only thing to drop is a FIN, we can drop
+          *    it, but check the ACK or we will get into FIN
+          *    wars if our FINs crossed (both CLOSING).
+          * In either case, send ACK to resynchronize,
+          * but keep on processing for RST or ACK.
+          */
+         if ((tiflags & TH_FIN && todrop == (int)ti->ti_len + 1) ||
+            (tiflags & TH_RST && ti->ti_seq == tp->rcv_nxt - 1))
+         {
+            todrop = ti->ti_len;
+            tiflags &= ~TH_FIN;
+            tp->t_flags |= TF_ACKNOW;
+         }
+         else
+            goto dropafterack;
+      }
+      else 
+      {
+         tcpstat.tcps_rcvpartduppack++;
+         tcpstat.tcps_rcvpartdupbyte += todrop;
+      }
+      m_adj(m, todrop);
+      ti->ti_seq += todrop;
+      ti->ti_len -= (u_short)todrop;
+      if (ti->ti_urp > (u_short)todrop)
+         ti->ti_urp -= (u_short)todrop;
+      else 
+      {
+         tiflags &= ~TH_URG;
+         ti->ti_urp = 0;
+      }
+   }
+
+   /*
+    * If new data are received on a connection after the
+    * user processes are gone, then RST the other end.
+    */
+   if ((so->so_state & SS_NOFDREF) &&
+       tp->t_state > TCPS_CLOSE_WAIT && ti->ti_len) 
+   {
+      tp = tcp_close(tp);
+      tcpstat.tcps_rcvafterclose++;
+      GOTO_DROPWITHRESET;
+   }
+
+   /*
+    * If segment ends after window, drop trailing data
+    * (and PUSH and FIN); if nothing left, just ACK.
+    */
+   todrop = (int)((ti->ti_seq + (short)ti->ti_len) - (tp->rcv_nxt+tp->rcv_wnd));
+   if (todrop > 0) 
+   {
+      tcpstat.tcps_rcvpackafterwin++;
+      if (todrop >= (int)ti->ti_len) 
+      {
+         tcpstat.tcps_rcvbyteafterwin += ti->ti_len;
+         /*
+          * If a new connection request is received
+          * while in TIME_WAIT, drop the old connection
+          * and start over if the sequence numbers
+          * are above the previous ones.
+          */
+         if (tiflags & TH_SYN &&
+             tp->t_state == TCPS_TIME_WAIT &&
+             SEQ_GT(ti->ti_seq, tp->rcv_nxt)) 
+         {
+            iss = (tcp_seq)(tp->rcv_nxt + (TCP_ISSINCR));
+            if (iss & 0xff000000)
+            {
+               iss = 0L;
+            }
+            (void) tcp_close(tp);
+            goto findpcb;
+         }
+         /*
+          * If window is closed can only take segments at
+          * window edge, and have to drop data and PUSH from
+          * incoming segments.  Continue processing, but
+          * remember to ack.  Otherwise, drop segment
+          * and ack.
+          */
+         if ((tp->rcv_wnd == 0) && (ti->ti_seq == tp->rcv_nxt))
+         {
+            tp->t_flags |= TF_ACKNOW;
+            tcpstat.tcps_rcvwinprobe++;
+         } else
+            goto dropafterack;
+      } else
+         tcpstat.tcps_rcvbyteafterwin += todrop;
+      /* XXX work around m_adj bug */
+      if (m->m_len) 
+      {
+         m_adj(m, -todrop);
+      }
+      else 
+      {
+         /* skip tcp/ip header in first mbuf */
+         m_adj(m->m_next, -todrop);
+      }
+      ti->ti_len -= (u_short)todrop;
+      tiflags &= ~(TH_PUSH|TH_FIN);
+   }
+
+
+   /*
+    * If the RST bit is set examine the state:
+    * SYN_RECEIVED STATE:
+    *   If passive open, return to LISTEN state.
+    *   If active open, inform user that connection was refused.
+    * ESTABLISHED, FIN_WAIT_1, FIN_WAIT2, CLOSE_WAIT STATES:
+    *   Inform user that connection was reset, and close tcb.
+    * CLOSING, LAST_ACK, TIME_WAIT STATES
+    *   Close the tcb.
+    */
+
+#ifdef DOS_RST
+   /* DOS_RST - Fix for "Denial of Service (DOS) using RST"
+    * An intruder can send RST packet to break on existing TCP
+    * connection. It means that if a RST is received in
+    * ESTABLISHED state from an intruder, then the connection gets
+    * closed between the original peers. To overcome this 
+    * vulnerability, it is suggested that we accept RST only when
+    * the sequence numbers match. Else we send an ACK.
+    */
+   if ((tiflags & TH_RST) && (tp->t_state == TCPS_ESTABLISHED) &&
+      (ti->ti_seq != tp->rcv_nxt))
+   {
+      /* RST received in established state and sequnece numbers
+       * don't match.
+       */
+#ifdef DO_TCPTRACE
+     tcp_trace("rcvd RST with seq num mismatch - ignoring RST, sending ACK.\n");
+#endif
+      tiflags &= ~TH_RST;  /* clear reset flag */
+      goto dropafterack;   /* send an ack and drop current packet */
+   }
+#endif /* DOS_RST */
+
+   if (tiflags&TH_RST) 
+   {
+      switch (tp->t_state) 
+      {
+   
+      case TCPS_SYN_RECEIVED:
+         so->so_error = ECONNREFUSED;
+         goto close;
+   
+      case TCPS_ESTABLISHED:
+         TCP_MIB_INC(tcpEstabResets);     /* keep MIB stats */
+      case TCPS_FIN_WAIT_1:
+      case TCPS_FIN_WAIT_2:
+      case TCPS_CLOSE_WAIT:
+         so->so_error = ECONNRESET;
+         close:
+         tp->t_state = TCPS_CLOSED;
+         tcpstat.tcps_drops++;
+         SETTP(tp, tcp_close(tp));
+#ifdef TCP_ZEROCOPY
+         if (so->rx_upcall)
+            so->rx_upcall(so, NULL, ECONNRESET);
+#endif   /* TCP_ZEROCOPY */
+         GOTO_DROP;
+   
+      case TCPS_CLOSING:
+      case TCPS_LAST_ACK:
+      case TCPS_TIME_WAIT:
+         SETTP(tp, tcp_close(tp));
+         GOTO_DROP;
+      }
+   }
+
+   /*
+    * If a SYN is in the window, then this is an
+    * error and we send an RST and drop the connection.
+    */
+
+#ifdef DOS_SYN
+   if ((tiflags & TH_SYN) && (tp->t_state == TCPS_ESTABLISHED))
+   {
+      /* DOS_SYN - Fix for "Denial of Service (DOS) attack using SYN"
+       * An intruder can send SYN to reset the connection.
+       * Hence normal behaviour can cause a vulnerability.
+       * To protect against this attack, just ignore the SYN packet
+       * when we are in established state.
+       * One solution is to send an ACK.
+       * But our guess is that just dropping the SYN should also
+       * work fine.
+       */
+#ifdef DO_TCPTRACE
+     tcp_trace("rcvd SYN in established state - ignoring SYN.\n");
+#endif
+      GOTO_DROP;
+   }
+#else
+   if (tiflags & TH_SYN) 
+   {
+      tp = tcp_drop(tp, ECONNRESET);
+      GOTO_DROPWITHRESET;
+   }
+#endif /* end of else of DOS_SYN */
+
+   /*
+    * If the ACK bit is off we drop the segment and return.
+    */
+   if ((tiflags & TH_ACK) == 0)
+      GOTO_DROP;
+
+   /*
+    * Ack processing.
+    */
+   switch (tp->t_state) 
+   {
+
+   /*
+    * In SYN_RECEIVED state if the ack ACKs our SYN then enter
+    * ESTABLISHED state and continue processing, otherwise
+    * send an RST.
+    */
+   case TCPS_SYN_RECEIVED:
+      if (SEQ_GT(tp->snd_una, ti->ti_ack) ||
+          SEQ_GT(ti->ti_ack, tp->snd_max))
+      {
+         TCP_MIB_INC(tcpEstabResets);     /* keep MIB stats */
+         GOTO_DROPWITHRESET;
+      }
+      tcpstat.tcps_connects++;
+      tp->t_state = TCPS_ESTABLISHED;
+      soisconnected(so);
+      tp->t_maxseg = tcp_mss(so);
+      (void) tcp_reass(tp, (struct tcpiphdr *)0, m);
+      tp->snd_wl1 = ti->ti_seq - 1;
+      /* fall into ... */
+
+   /*
+    * In ESTABLISHED state: drop duplicate ACKs; ACK out of range
+    * ACKs.  If the ack is in the range
+    *   tp->snd_una < ti->ti_ack <= tp->snd_max
+    * then advance tp->snd_una to ti->ti_ack and drop
+    * data from the retransmission queue.  If this ACK reflects
+    * more up to date window information we update our window information.
+    */
+   case TCPS_ESTABLISHED:
+   case TCPS_FIN_WAIT_1:
+   case TCPS_FIN_WAIT_2:
+   case TCPS_CLOSE_WAIT:
+   case TCPS_CLOSING:
+   case TCPS_LAST_ACK:
+   case TCPS_TIME_WAIT:
+
+      if (SEQ_LEQ(ti->ti_ack, tp->snd_una)) 
+      {
+         if (ti->ti_len == 0 && rx_win == tp->snd_wnd) 
+         {
+            tcpstat.tcps_rcvdupack++;
+            /*
+             * If we have outstanding data (not a
+             * window probe), this is a completely
+             * duplicate ack (ie, window info didn't
+             * change), the ack is the biggest we've
+             * seen and we've seen exactly our rexmt
+             * threshhold of them, assume a packet
+             * has been dropped and retransmit it.
+             * Kludge snd_nxt & the congestion
+             * window so we send only this one
+             * packet.  If this packet fills the
+             * only hole in the receiver's seq.
+             * space, the next real ack will fully
+             * open our window.  This means we
+             * have to do the usual slow-start to
+             * not overwhelm an intermediate gateway
+             * with a burst of packets.  Leave
+             * here with the congestion window set
+             * to allow 2 packets on the next real
+             * ack and the exp-to-linear thresh
+             * set for half the current window
+             * size (since we know we're losing at
+             * the current window size).
+             */
+            if (tp->t_timer[TCPT_REXMT] == 0 ||
+                ti->ti_ack != tp->snd_una)
+            {
+               tp->t_dupacks = 0;
+            }
+            else if (++tp->t_dupacks == tcprexmtthresh) 
+            {
+               tcp_seq onxt = tp->snd_nxt;
+               u_short  win   =
+               MIN(tp->snd_wnd, tp->snd_cwnd) / 2 /
+               tp->t_maxseg;
+
+               if (win < 2)
+                  win = 2;
+               tp->snd_ssthresh = (u_short)(win * tp->t_maxseg);
+
+               tp->t_timer[TCPT_REXMT] = 0;
+               tp->t_rttick = 0;
+               tp->snd_nxt = ti->ti_ack;
+               tp->snd_cwnd = tp->t_maxseg;
+               (void) tcp_output(tp);
+
+               if (SEQ_GT(onxt, tp->snd_nxt))
+                  tp->snd_nxt = onxt;
+               GOTO_DROP;
+            }
+         } else
+            tp->t_dupacks = 0;
+         break;
+      }
+      tp->t_dupacks = 0;
+      if (SEQ_GT(ti->ti_ack, tp->snd_max)) 
+      {
+         tcpstat.tcps_rcvacktoomuch++;
+         goto dropafterack;
+      }
+      acked = (int)(ti->ti_ack - tp->snd_una);
+      tcpstat.tcps_rcvackpack++;
+      tcpstat.tcps_rcvackbyte += acked;
+
+      /*
+       * If transmit timer is running and timed sequence
+       * number was acked, update smoothed round trip time.
+       * Since we now have an rtt measurement, cancel the
+       * timer backoff (cf., Phil Karn's retransmit alg.).
+       * Recompute the initial retransmit timer.
+       */
+      if((tp->t_rttick) && 
+#ifdef TCP_TIMESTAMP
+         ((tp->t_flags & TF_TIMESTAMP) == 0) && 
+#endif /* TCP_TIMESTAMP */
+         (SEQ_GT(ti->ti_ack, tp->t_rtseq)))
+         tcp_xmit_timer(tp);
+
+      /*
+       * If all outstanding data is acked, stop retransmit
+       * timer and remember to restart (more output or persist).
+       * If there is more data to be acked, restart retransmit
+       * timer, using current (possibly backed-off) value.
+       */
+      if (ti->ti_ack == tp->snd_max) 
+      {
+         tp->t_timer[TCPT_REXMT] = 0;
+         needoutput = 1;
+      } else if (tp->t_timer[TCPT_PERSIST] == 0)
+         tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+      /*
+       * When new data is acked, open the congestion window.
+       * If the window gives us less than ssthresh packets
+       * in flight, open exponentially (maxseg per packet).
+       * Otherwise open linearly (maxseg per window,
+       * or maxseg^2 / cwnd per packet).
+       */
+      {
+         tcp_win  cw =  tp->snd_cwnd;
+         u_short  incr  =  tp->t_maxseg;
+
+         if (cw > tp->snd_ssthresh)
+            incr = MAX( (incr * incr / cw), (ALIGN_TYPE << 2) );
+
+         tp->snd_cwnd = MIN(cw + (u_short)incr, (IP_MAXPACKET));
+      }
+      if (acked > (int)so->so_snd.sb_cc) 
+      {
+         tp->snd_wnd -= (u_short)so->so_snd.sb_cc;
+         sbdrop(&so->so_snd, (int)so->so_snd.sb_cc);
+         ourfinisacked = 1;
+      } 
+      else 
+      {
+         sbdrop(&so->so_snd, acked);
+         tp->snd_wnd -= (u_short)acked;
+         ourfinisacked = 0;
+      }
+
+      if (so->so_snd.sb_flags & (SB_WAIT | SB_SEL))
+         sowwakeup(so);
+
+      tp->snd_una = ti->ti_ack;
+      if (SEQ_LT(tp->snd_nxt, tp->snd_una))
+         tp->snd_nxt = tp->snd_una;
+
+
+      switch (tp->t_state) 
+      {
+
+      /*
+       * In FIN_WAIT_1 STATE in addition to the processing
+       * for the ESTABLISHED state if our FIN is now acknowledged
+       * then enter FIN_WAIT_2.
+       */
+      case TCPS_FIN_WAIT_1:
+         if (ourfinisacked) 
+         {
+            /*
+             * If we can't receive any more
+             * data, then closing user can proceed.
+             * Starting the timer is contrary to the
+             * specification, but if we don't get a FIN
+             * we'll hang forever.
+             */
+            if (so->so_state & SS_CANTRCVMORE) 
+            {
+               soisdisconnected(so);
+               tp->t_timer[TCPT_2MSL] = tcp_maxidle;
+            }
+            tp->t_state = TCPS_FIN_WAIT_2;
+         }
+         break;
+
+       /*
+       * In CLOSING STATE in addition to the processing for
+       * the ESTABLISHED state if the ACK acknowledges our FIN
+       * then enter the TIME-WAIT state, otherwise ignore
+       * the segment.
+       */
+      case TCPS_CLOSING:
+         if (ourfinisacked) 
+         {
+            tp->t_state = TCPS_TIME_WAIT;
+            tcp_canceltimers(tp);
+            tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+            soisdisconnected(so);
+         }
+         break;
+
+      /*
+       * In LAST_ACK, we may still be waiting for data to drain
+       * and/or to be acked, as well as for the ack of our FIN.
+       * If our FIN is now acknowledged, delete the TCB,
+       * enter the closed state and return.
+       */
+      case TCPS_LAST_ACK:
+         if (ourfinisacked) 
+         {
+            SETTP(tp, tcp_close(tp));
+            GOTO_DROP;
+         }
+         break;
+
+      /*
+       * In TIME_WAIT state the only thing that should arrive
+       * is a retransmission of the remote FIN.  Acknowledge
+       * it and restart the finack timer.
+       */
+      case TCPS_TIME_WAIT:
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+         goto dropafterack;
+      }
+   }
+
+step6:
+   /*
+    * Update window information.
+    * Don't look at window if no ACK: TAC's send garbage on first SYN.
+    */
+   if ((tiflags & TH_ACK) &&
+       /*
+        * Altera Niche Stack Nios port modification:
+        * Add parenthesis to remove implicit order of operation
+        * & possible build warnings.
+        */
+       (SEQ_LT(tp->snd_wl1, ti->ti_seq) || (tp->snd_wl1 == ti->ti_seq &&
+       (SEQ_LT(tp->snd_wl2, ti->ti_ack) ||
+       ((tp->snd_wl2 == ti->ti_ack) && (rx_win > tp->snd_wnd)))))) 
+   {
+      /* keep track of pure window updates */
+      if ((ti->ti_len == 0) &&
+          (tp->snd_wl2 == ti->ti_ack) &&
+          (rx_win > tp->snd_wnd))
+      {
+         tcpstat.tcps_rcvwinupd++;
+      }
+      tp->snd_wnd = rx_win;
+      tp->snd_wl1 = ti->ti_seq;
+      tp->snd_wl2 = ti->ti_ack;
+      if (tp->snd_wnd > tp->max_sndwnd)
+         tp->max_sndwnd = tp->snd_wnd;
+      needoutput = 1;
+   }
+
+   /*
+    * Process segments with URG.
+    */
+   if ((tiflags & TH_URG) && ti->ti_urp &&
+       TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+   {
+      /*
+       * This is a kludge, but if we receive and accept
+       * random urgent pointers, we'll crash in
+       * soreceive.  It's hard to imagine someone
+       * actually wanting to send this much urgent data.
+       */
+      if (ti->ti_urp + so->so_rcv.sb_cc > SB_MAX) 
+      {
+         ti->ti_urp = 0;         /* XXX */
+         tiflags &= ~TH_URG;     /* XXX */
+         goto dodata;         /* XXX */
+      }
+      /*
+       * If this segment advances the known urgent pointer,
+       * then mark the data stream.  This should not happen
+       * in CLOSE_WAIT, CLOSING, LAST_ACK or TIME_WAIT STATES since
+       * a FIN has been received from the remote side. 
+       * In these states we ignore the URG.
+       *
+       * According to RFC961 (Assigned Protocols),
+       * the urgent pointer points to the last octet
+       * of urgent data.  We continue, however,
+       * to consider it to indicate the first octet
+       * of data past the urgent section
+       * as the original spec states.
+       */
+      if (SEQ_GT(ti->ti_seq+ti->ti_urp, tp->rcv_up)) 
+      {
+         tp->rcv_up = ti->ti_seq + ti->ti_urp;
+         so->so_oobmark = so->so_rcv.sb_cc +
+         (tp->rcv_up - tp->rcv_nxt) - 1;
+         if (so->so_oobmark == 0)
+            so->so_state |= SS_RCVATMARK;
+         sohasoutofband(so);
+         tp->t_oobflags &= ~(TCPOOB_HAVEDATA | TCPOOB_HADDATA);
+      }
+      /*
+       * Remove out of band data so doesn't get presented to user.
+       * This can happen independent of advancing the URG pointer,
+       * but if two URG's are pending at once, some out-of-band
+       * data may creep in... ick.
+       */
+      if ( (ti->ti_urp <= ti->ti_len)
+#ifdef SO_OOBINLINE
+       && (so->so_options & SO_OOBINLINE) == 0
+#endif
+       )
+      {
+         tcp_pulloutofband(so, ti, m);
+      }
+   } else
+      /*
+       * If no out of band data is expected,
+       * pull receive urgent pointer along
+       * with the receive window.
+       */
+   if (SEQ_GT(tp->rcv_nxt, tp->rcv_up))
+      tp->rcv_up = tp->rcv_nxt;
+dodata:                       /* XXX */
+
+   /*
+    * Process the segment text, merging it into the TCP sequencing queue,
+    * and arranging for acknowledgment of receipt if necessary.
+    * This process logically involves adjusting tp->rcv_wnd as data
+    * is presented to the user (this happens in tcp_usrreq.c,
+    * case PRU_RCVD).  If a FIN has already been received on this
+    * connection then we just ignore the text.
+    */
+   if ((ti->ti_len || (tiflags&TH_FIN)) &&
+       TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+   {
+
+      /* Do the common segment reassembly case inline */
+      if((ti->ti_seq == tp->rcv_nxt) &&
+         (tp->seg_next == (struct tcpiphdr *)(tp) ) &&
+         (tp->t_state == TCPS_ESTABLISHED))
+      {
+#ifdef DO_DELAY_ACKS
+         if (tp->t_delacktime)
+         {
+            if (tp->t_delackcur == 0)    /* need to set ack timer? */
+               tp->t_delackcur = tp->t_delacktime;
+            tp->t_flags |= TF_DELACK;
+         }
+         else
+         {
+            tp->t_flags |= TF_ACKNOW;
+         }
+#else    /* not DO_DELAY_ACKS */
+            tp->t_flags |= TF_ACKNOW;
+#endif   /* DO_DELAY_ACKS */
+
+         tp->rcv_nxt += ti->ti_len;
+         tiflags = ti->ti_flags & TH_FIN;
+         tcpstat.tcps_rcvpack++;
+         tcpstat.tcps_rcvbyte += ti->ti_len;
+         sbappend(&so->so_rcv, (m));
+         sorwakeup(so);
+#ifdef TCP_SACK
+         tp->sack_seqct = 0;     /* clear sack valid block count */
+#endif /* TCP_SACK */
+      }
+      else     /* received out of sequence segment */
+      {
+         /* Drop it in the reassmbly queue */
+         tiflags = tcp_reass(tp, ti, m);
+         tp->t_flags |= TF_ACKNOW;
+
+#ifdef TCP_SACK      
+         /* If doing SACK and there's data, then save sack info. and
+          * set flag to send sack header on next ack
+          */
+         if((tp->t_flags & TF_SACKOK) && (m->m_len > 0))
+            tcp_setsackinfo(tp, ti);
+#endif /* TCP_SACK */
+      }
+
+
+      /*
+       * Note the amount of data that peer has sent into
+       * our window, in order to estimate the sender's
+       * buffer size.
+       */
+      len = (int)(so->so_rcv.sb_hiwat - (tp->rcv_adv - tp->rcv_nxt));
+      if (len > (int)tp->max_rcvd)
+         tp->max_rcvd = (u_short)len;
+#ifdef TCP_ZEROCOPY
+      if (so->rx_upcall)
+      {
+         tcp_data_upcall(so);
+         /* if we have FIN and app has all data, do shutdown */
+         if ((tiflags & TH_FIN) &&
+            (so->so_rcv.sb_cc == 0))
+         {
+            so->rx_upcall(so, NULL, ESHUTDOWN);
+            so->so_state |= SS_UPCFIN;    /* flag that upcall was FINed */
+         }
+      }
+#endif   /* TCP_ZEROCOPY */
+   } 
+   else
+   {
+      m_freem(m);
+      tiflags &= ~TH_FIN;
+   }
+
+   /*
+    * If FIN is received ACK the FIN and let the user know
+    * that the connection is closing.
+    */
+   if (tiflags & TH_FIN) 
+   {
+      if (TCPS_HAVERCVDFIN(tp->t_state) == 0) 
+      {
+         socantrcvmore(so);
+         tp->t_flags |= TF_ACKNOW;
+         tp->rcv_nxt++;
+      }
+      switch (tp->t_state) 
+      {
+
+       /*
+       * In SYN_RECEIVED and ESTABLISHED STATES
+       * enter the CLOSE_WAIT state.
+       */
+      case TCPS_SYN_RECEIVED:
+      case TCPS_ESTABLISHED:
+         tp->t_state = TCPS_CLOSE_WAIT;
+         break;
+
+       /*
+       * If still in FIN_WAIT_1 STATE FIN has not been acked so
+       * enter the CLOSING state.
+       */
+      case TCPS_FIN_WAIT_1:
+         tp->t_state = TCPS_CLOSING;
+         break;
+
+       /*
+       * In FIN_WAIT_2 state enter the TIME_WAIT state,
+       * starting the time-wait timer, turning off the other 
+       * standard timers.
+       */
+      case TCPS_FIN_WAIT_2:
+         tp->t_state = TCPS_TIME_WAIT;
+         tcp_canceltimers(tp);
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+         soisdisconnected(so);
+         break;
+
+      /*
+       * In TIME_WAIT state restart the 2 MSL time_wait timer.
+       */
+      case TCPS_TIME_WAIT:
+         tp->t_timer[TCPT_2MSL] = 2 * TCPTV_MSL;
+         break;
+      }
+   }
+#ifdef DO_TCPTRACE
+   if (so->so_options & SO_DEBUG)
+      tcp_trace("TCP_IN: state: %d, tcpcb: %x saveti: %x", 
+    ostate, tp, &tcp_saveti);
+#endif
+   /*
+    * Return any desired output.
+    */
+   if (needoutput || (tp->t_flags & TF_ACKNOW))
+      (void) tcp_output(tp);
+   return;
+
+dropafterack:
+   /*
+    * Generate an ACK dropping incoming segment if it occupies
+    * sequence space, where the ACK reflects our state.
+    */
+   if (tiflags & TH_RST)
+      GOTO_DROP;
+   m_freem (m);
+   tp->t_flags |= TF_ACKNOW;
+   (void) tcp_output (tp);
+   return;
+
+dropwithreset:
+   TCP_MIB_INC(tcpInErrs);    /* keep MIB stats */
+   if (om) 
+   {
+      (void) m_free(om);
+      om = 0;
+   }
+
+   /* Don't reset resets */
+   if (tiflags & TH_RST)
+      GOTO_DROP;
+
+   /*
+    * Generate a RST, dropping incoming segment.
+    * Make ACK acceptable to originator of segment.
+    * Don't bother to respond if destination was broadcast.
+    */
+#ifdef IP_V4
+   if (in_broadcast(ti->ti_dst.s_addr))
+      GOTO_DROP;
+#endif
+
+#ifdef IP_V6
+   if(m->pkt->type == htons(0x86DD))
+   {
+      /* restore the received IP addresses for pass to the 
+       * tcp_repond routine - they may have been corrupted. 
+       */
+      IP6CPY(&(m->pkt->ip6_hdr->ip_src), &ip6_src);
+      IP6CPY(&(m->pkt->ip6_hdr->ip_dest), &ip6_dst);
+   }
+#endif   /* IP_V6 */
+
+   if (tiflags & TH_ACK)
+      tcp_respond (tp, ti, (tcp_seq)0, ti->ti_ack, TH_RST, m);
+   else
+   {
+      if (tiflags & TH_SYN)
+         ti->ti_seq++;
+      tcp_respond(tp, ti, ti->ti_seq, (tcp_seq)0, TH_RST|TH_ACK, m);
+   }
+   /* destroy temporarily created socket */
+   if (dropsocket)
+      (void) soabort(so);
+   return;
+
+drop:
+   if (om)
+      (void) m_free(om);
+   /*
+    * Drop space held by incoming segment and return.
+    */
+#ifdef DO_TCPTRACE
+   if (tp && (tp->t_inpcb->inp_socket->so_options & SO_DEBUG))
+      tcp_trace("drop: state %d, tcpcb: %x, saveti: %x",
+    ostate, tp, &tcp_saveti);
+#endif
+   m_freem(m);
+   /* destroy temporarily created socket */
+   if (dropsocket)
+      (void) soabort(so);
+   return;
+}
+
+
+
+/* FUNCTION: tcp_dooptions()
+ * 
+ * Parse received TCP options appended to the TCP header 
+ *
+ * PARAM1: struct tcpcb * tp
+ * PARAM2: struct mbuf * om
+ * PARAM3: struct tcpiphdr * ti
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_dooptions(struct tcpcb * tp, 
+   struct mbuf *  om,
+   struct tcpiphdr * ti)
+{
+   u_char * cp;   /* pointer into option buffer */
+   int   opt;     /* current option code */
+   int   optlen;  /* length of current option */
+   int   cnt;     /* byte count left in header */
+   struct socket * so = tp->t_inpcb->inp_socket;
+#ifdef TCP_TIMESTAMP
+   int   gotstamp = FALSE;    /* TRUE if we got a timestamp */
+#endif   /* TCP_TIMESTAMP */
+
+
+   cp = mtod(om, u_char *);
+   cnt = om->m_len;
+   for (; cnt > 0; cnt -= optlen, cp += optlen) 
+   {
+      opt = cp[0];
+      if (opt == TCPOPT_EOL)
+         break;
+      if (opt == TCPOPT_NOP)
+         optlen = 1;
+      else 
+      {
+         optlen = cp[1];
+         if (optlen <= 0)
+            break;
+      }
+
+      switch (opt) 
+      {
+      case TCPOPT_MAXSEG:
+      {
+         u_short mssval;
+         if (optlen != 4)
+            continue;
+         if (!(ti->ti_flags & TH_SYN))    /* MSS only on SYN */
+            continue;
+         mssval = *(u_short *)(cp + 2);
+         mssval = ntohs(mssval);
+         tp->t_maxseg = (u_short)MIN(mssval, (u_short)tcp_mss(so));
+         break;
+      }
+#ifdef TCP_SACK
+      case TCPOPT_SACKOK:
+      {
+         if(optlen != 2)
+            continue;
+
+         if (!(ti->ti_flags & TH_SYN))    /* only legal on SYN, SYN/ACK */
+            continue;
+
+         /* If SACK is OK with our socket and the other side then
+          * set the t_flags bit which will allow it.
+          */
+         if(so->so_options & SO_TCPSACK)
+         {
+            tp->t_flags |= TF_SACKOK;
+            tcpstat.tcps_sackconn++;
+         }
+         break;
+      }
+      case TCPOPT_SACKDATA:   /* got a SACK info packet */
+         if(tp->t_flags & TF_SACKOK)
+            tcp_resendsack(cp, tp);
+         break;
+#endif   /* TCP_SACK */
+
+#ifdef TCP_WIN_SCALE
+      case TCPOPT_WINSCALE:   /* window scale offer */
+      {
+         if (optlen != 3)
+            continue;
+         if (!(ti->ti_flags & TH_SYN))    /* only legal on SYN, SYN/ACK */
+            continue;
+         tp->snd_wind_scale = *(cp + 2);
+         tp->t_flags |= TF_WINSCALE;
+         /* Here's a a trick that's not in the literature. If the other side has
+          * agreed to let us do scaled windows but sent set his scale as 0, 
+          * then it means he's not ever going to get his window over 64K, and 
+          * in practice. probably no where near that high. Some TCPs (like 
+          * Microsoft's Win 2K) get really confused by disparate window sizes.
+          * If we put a lid on our size too, things work a lot better.
+          */
+         if(tp->snd_wind_scale == 0)
+            so->so_rcv.sb_hiwat = (32 * 1024);
+         break;
+      }
+#endif /* TCP_WIN_SCALE */
+
+#ifdef TCP_TIMESTAMP
+      case TCPOPT_RTT:     /* round trip time option */
+         if (optlen != 10)
+            continue;
+
+         if((so->so_options & SO_TIMESTAMP) == 0)
+            continue;
+
+         gotstamp = TRUE;     /* set flag indicating we found timestamp */
+
+         /* Timestamp options are only legal on SYN packets or on connections
+          * where we got one on the SYN packet 
+          */
+         if((ti->ti_flags & TH_SYN) ||
+            (tp->t_flags & TF_TIMESTAMP))
+         {
+            /* If it's on a SYN packet, mark the connection as doing timestamps */
+            if(ti->ti_flags & TH_SYN)
+            {
+               tp->t_flags |= TF_TIMESTAMP;
+               /* 
+                * Reduce our MSS for this connection to reflect the size of
+                * the option we now have to add to every packet.
+                */
+               tp->t_maxseg -= 12;
+               break;
+            }
+
+            /* See if we should save his timestamp for our replys. RFC-1323
+             * goes into detail about how to do this in section 3.4.
+             */
+            if((ti->ti_seq <= tp->last_ack) &&
+               (tp->last_ack < (ti->ti_seq + ti->ti_len)))
+            {
+               tp->ts_recent = tcp_getseq(cp + 2);
+            }
+            /* If the received segment acknowledges new data then update our
+             * round trip time. Again, from RFC-1323: (3.3)
+             */
+            if(ti->ti_t.th_ack > tp->snd_una)
+            {
+               tp->t_rttick = tcp_getseq(cp + 6);  /* extract echoed tick count */
+               tcp_xmit_timer(tp);     /*  pass to routine */
+            }
+         }
+         break;
+#endif   /* TCP_TIMESTAMP */
+
+      default:
+         break;
+      }
+   }
+   (void) m_free(om);
+
+#ifdef TCP_TIMESTAMP
+   /* 
+    * On syn/ack packets see if we should be timestamping or not. The
+    * tp->t_flags TF_TIMESTAMP bit was already set above if we sent a
+    * SYN w/RTTM and peer acked it in kind, but if we sent RTTM in
+    * a SYN and this syn/ack did NOT echo it then the peer is not 
+    * doing RTTM and we should not pester it with options it probably
+    * doesn't understand.
+    */
+   if((ti->ti_flags & (TH_SYN|TH_ACK)) == (TH_SYN|TH_ACK))
+   {
+      if(!gotstamp)
+         tp->t_flags &= ~TF_TIMESTAMP;
+   }
+#endif /* TCP_TIMESTAMP */
+
+   return;
+}
+
+
+
+/* FUNCTION: tcp_pulloutofband()
+ *
+ * Pull out of band byte out of a segment so
+ * it doesn't appear in the user's data queue.
+ * It is still reflected in the segment length for
+ * sequencing purposes.
+ *
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: struct tcpiphdr *ti
+ * PARAM3: struct mbuf *m
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_pulloutofband(struct socket * so, 
+   struct tcpiphdr * ti,
+   struct mbuf *  m)
+{
+   int   cnt   =  ti->ti_urp  -  1;
+
+   /**m = dtom(ti);**/
+   while (cnt >= 0) 
+   {
+      if (m->m_len > (unsigned)cnt) 
+      {
+         char *   cp =  mtod(m,  char *) +  cnt;
+         struct tcpcb * tp =  sototcpcb(so);
+
+         tp->t_iobc = *cp;
+         tp->t_oobflags |= TCPOOB_HAVEDATA;
+         MEMCPY(cp, cp+1, (unsigned)(m->m_len - cnt - 1));
+         m->m_len--;
+         return;
+      }
+      cnt -= m->m_len;
+      m = m->m_next;
+      if (m == 0)
+         break;
+   }
+   panic("tcp_pulloutofband");
+}
+
+
+
+
+/* FUNCTION: tcp_xmit_timer()
+ * 
+ * PARAM1: struct tcpcb * tp
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_xmit_timer(struct tcpcb * tp)
+{
+   int delta;
+   int rtt;
+
+#ifdef NPDEBUG
+   if(tp->t_rttick == 0){ dtrap(); return; }
+#endif
+
+   tcpstat.tcps_rttupdated++;
+
+   /* get  this rtt. Convert from cticks to TCP slow ticks */
+   rtt = (int)((cticks - tp->t_rttick) / (TPS/2));
+   if(tp->t_srtt != 0)
+   {
+      if(rtt == 0)      /* fast path for small round trip */
+      {
+         /* if either the rtt or varience is over 1, reduce it. */
+         if(tp->t_srtt > 1)
+            tp->t_srtt--;
+         if(tp->t_rttvar > 1)
+            tp->t_rttvar--;
+      }
+      else
+      {
+      /*
+       * srtt is stored as fixed point with 3 bits
+       * after the binary point (i.e., scaled by 8).
+       * The following magic is equivalent
+       * to the smoothing algorithm in rfc793
+       * with an alpha of .875
+       * (srtt = rtt/8 + srtt*7/8 in fixed point).
+       */
+      delta = ((rtt - 1) << 2) - (int)(tp->t_srtt >> 3);
+      if ((tp->t_srtt += delta) <= 0)
+         tp->t_srtt = 1;
+      /*
+       * We accumulate a smoothed rtt variance
+       * (actually, a smoothed mean difference),
+       * then set the retransmit timer to smoothed
+       * rtt + 2 times the smoothed variance.
+       * rttvar is stored as fixed point
+       * with 2 bits after the binary point
+       * (scaled by 4).  The following is equivalent
+       * to rfc793 smoothing with an alpha of .75
+       * (rttvar = rttvar*3/4 + |delta| / 4).
+       * This replaces rfc793's wired-in beta.
+       */
+      if (delta < 0)
+         delta = -delta;
+      delta -= (short)(tp->t_rttvar >> 1);
+      if ((tp->t_rttvar += delta) <= 0)
+         tp->t_rttvar = 1;
+      }
+   }
+   else  /* srtt is zero, nedd to initialize it */
+   {
+      /* 
+       * No rtt measurement yet - use the
+       * unsmoothed rtt.  Set the variance
+       * to half the rtt (so our first
+       * retransmit happens at 2*rtt)
+       */
+      if(rtt < 1)
+         rtt = 1;
+      tp->t_srtt = rtt << 3;
+      tp->t_rttvar = rtt << 1;
+   }
+   tp->t_rttick = 0;       /* clear RT timer */
+   tp->t_rxtshift = 0;
+   TCPT_RANGESET(tp->t_rxtcur, 
+    ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1,
+    TCPTV_MIN, TCPTV_REXMTMAX);
+}
+
+
+#ifdef IP_V4
+int
+ip4_tcpmss(struct socket * so)
+{
+   NET ifp;
+
+   ifp = so->so_pcb->ifp;
+   return(ifp->n_mtu - (40 + ifp->n_lnh));
+}
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+int
+ip6_tcpmss(struct socket * so, NET ifp)
+{
+   int pmtu;
+   
+   pmtu = ip6_pmtulookup(&so->so_pcb->ip6_faddr, ifp);
+   return pmtu - 20;
+}
+#endif   /* IP_V6 */
+
+
+/* FUNCTION: tcp_mss()
+ *
+ * Find TCP_MSS for socket passed.
+ *
+ * PARAM1: socket
+ *
+ * RETURNS: 
+ */
+
+
+int
+tcp_mss(struct socket * so)
+{
+   int   mss;     /* MSS value to return */
+   struct inpcb * inp;
+   struct tcpcb * tp;
+#ifdef IP_V6
+   NET  ifp = 0;
+#endif
+
+   if ((so == NULL) ||
+       (so->so_pcb == NULL) ||
+       (so->so_pcb->ifp == NULL))
+   {
+      if (so->so_domain == AF_INET)  /* IPv4 */
+         return TCP_MSS;            /* user defined */
+#ifdef IP_V6
+      else                          /* IPv6 */
+      {
+           /* no ifp */
+           return 1220;               /* RFC2460 defined, less IPv6/TCP hdrs */
+      }
+#endif   /* IP_V6 */
+   }
+#ifdef IP_V6
+   else
+   	if (so && so->so_pcb && so->so_pcb->ifp)
+   		  ifp = so->so_pcb->ifp;
+   	else
+        return 1220;               /* RFC2460 defined, less IPv6/TCP hdrs */
+#endif   /* IP_V6 */
+
+
+#ifdef IP_V4   /* Begin messy domain defines */
+#ifndef IP_V6  /* V4 only version */
+   mss = ip4_tcpmss(so);
+#else          /* dual mode */
+   if (so->so_domain == AF_INET)              /* IPv4 */
+      mss = ip4_tcpmss(so);
+   else                                      /* IPv6 */
+      mss = ip6_tcpmss(so, ifp);
+#endif         /* end of dual mode */
+#else          /* no IP_v4, assume V6 only */
+      mss = ip6_tcpmss(so, ifp);
+#endif         /* end messy domain defines */
+
+   if (mss > TCP_MSS)    /* check upper limit from compile */
+      mss = TCP_MSS;
+
+   /* check upper limit which may be set by setsockopt() */
+   inp = (struct inpcb *)so->so_pcb;         /* Map socket to IP cb */
+   tp = (struct tcpcb *)inp->inp_ppcb;       /* Map IP to TCP cb */
+   
+   /* has user set max seg? */
+   if (tp->t_flags & TF_MAXSEG)
+      return tp->t_maxseg;    /* yup */
+      
+   if (tp->t_maxseg && (mss > tp->t_maxseg))  /* check tcp's mss */
+   {
+      mss = tp->t_maxseg;        /* limit new MSS to set MSS */
+   }
+
+   return mss;
+}
+
+
+
+#endif /* INCLUDE_TCP */
+
+/* end of file tcp_in.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_menu.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_menu.c
new file mode 100644
index 0000000..807acaf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_menu.c
@@ -0,0 +1,275 @@
+/*
+ * FILENAME: tcp_menu.c
+ *
+ * Copyright 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ * TCp menu for testing exotic TCP options
+ *
+ * MODULE: TCP
+ *
+ * ROUTINES: tcp_winscale(), tcp_cwndsize(), tcp_cdump(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef TCP_MENUS  /* whole file can be ifdeffed out */
+
+#ifndef IN_MENUS
+#error TCP_MENUS requires IN_MENUS
+#endif
+
+
+#include "tcpport.h"
+#include "protosw.h"
+#include "in_pcb.h"
+#include "tcp.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "menu.h"
+
+int   tcp_setwin(void * pio);
+int   tcp_cwndsize(void * pio);
+int   tcp_cdump(void * pio); 
+int   so_setopts(void * pio); 
+int   tp_setflags(void * pio); 
+
+struct menu_op tcpmenu[] = {
+   "tcp", stooges, "TCP test menus",
+#ifdef TCP_BIGCWND
+   "tcwnd",    tcp_cwndsize,  "set congestion window (MSS factor)",
+#endif   /* TCP_BIGCWND */
+   "twinset",  tcp_setwin,    "set default TCP window (Kbytes)",
+#ifdef NET_STATS
+   "tcdump",   tcp_cdump,     "dump connection details",
+#endif   /* NET_STATS */
+   "sosetopts",so_setopts,    "set default socket options",
+   NULL, NULL, NULL
+};
+
+
+extern   u_long   tcp_recvspace;
+
+
+
+int
+tcp_setwin(void * pio)
+{
+   u_long   i;
+   char *   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+
+   i = atol(cp);
+   if(i == 0)
+   {
+      ns_printf(pio, "window value must be number of K-bytes, currently %uKB\n",
+         (int)(tcp_recvspace/1024) );
+      return -1;
+   }
+   tcp_recvspace = i * 1024L;
+   default_wind_scale = 0;
+   if(tcp_recvspace > (64L * 1024L))
+   {
+#ifdef TCP_WIN_SCALE
+      u_long tmp;
+      tmp = tcp_recvspace;
+      while(tmp & 0xFFFF0000)
+      {
+         default_wind_scale++;
+         tmp >>= 1;
+      }
+      ns_printf(pio, "tcp window scaling factor set to %d, ", (int)default_wind_scale);
+#else
+      ns_printf(pio, "Size must be < 64K, or recompile w/TCP_WIN_SCALE\n");
+      tcp_recvspace = (32L * 1024L);
+#endif
+   }
+
+   ns_printf(pio, "window set to %ld\n", tcp_recvspace);
+   return 0;
+}
+
+
+#ifdef TCP_BIGCWND
+int
+tcp_cwndsize(void * pio)
+{
+   int      i;
+   char *   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+
+   i = atoi(cp);
+   if(i < 1)
+   {
+      ns_printf(pio, "c-window must be scale, 1 - 255; currently %s\n",
+         default_cwnd);
+      return -1;
+   }
+   default_cwnd = (i * TCP_MSS);
+   use_default_cwnd = 1;
+   ns_printf(pio, "default initial congestion window set to %d\n", default_cwnd);
+   return 0;
+}
+#endif   /* TCP_BIGCWND */
+
+
+#ifdef NET_STATS
+
+void
+dump_so_options(void * pio, unshort options)
+{
+   if(options & SO_DEBUG)ns_printf(pio, "SO_DEBUG ");
+   if(options & SO_ACCEPTCONN)ns_printf(pio, "ACCEPTCONN ");
+   if(options & SO_REUSEADDR)ns_printf(pio, "REUSEADDR ");
+   if(options & SO_KEEPALIVE)ns_printf(pio, "KEEPALIVE ");
+   if(options & SO_DONTROUTE)ns_printf(pio, "DONTROUTE ");
+   if(options & SO_BROADCAST)ns_printf(pio, "BROADCAST ");
+   if(options & SO_USELOOPBACK)ns_printf(pio, "USELOOPBACK ");
+   if(options & SO_LINGER)ns_printf(pio, "LINGER ");
+   if(options & SO_OOBINLINE)ns_printf(pio, "OOBINLINE ");
+   if(options & SO_TCPSACK)ns_printf(pio, "TCPSACK ");
+   if(options & SO_WINSCALE)ns_printf(pio, "WINSCALE ");
+   if(options & SO_TIMESTAMP)ns_printf(pio, "TIMESTAMP ");
+   if(options & SO_BIGCWND)ns_printf(pio, "BIGCWND ");
+
+   return;
+}
+
+void
+dump_tp_tpflags(void * pio, unshort flags)
+{
+   if(flags & TF_ACKNOW)ns_printf(pio, "ACKNOW ");
+   if(flags & TF_DELACK)ns_printf(pio, "DELACK ");
+   if(flags & TF_NODELAY)ns_printf(pio, "NODELAY ");
+   if(flags & TF_NOOPT)ns_printf(pio, "NOOPT ");
+   if(flags & TF_SENTFIN)ns_printf(pio, "SENTFIN ");
+   if(flags & TF_SACKOK)ns_printf(pio, "SACKOK ");
+   if(flags & TF_SACKNOW)ns_printf(pio, "SACKNOW ");
+   if(flags & TF_WINSCALE)ns_printf(pio, "WINSCALE ");
+   if(flags & TF_TIMESTAMP)ns_printf(pio, "TIMESTAMP ");
+
+   return;
+}
+
+extern char *   tcpstates[11];   /* in nptcp.c */
+
+int
+tcp_cdump(void * pio)
+{
+   unsigned fport;
+   unsigned lport;
+   struct socket * so;
+   struct tcpcb * tp;
+   struct inpcb * inp;
+   char *   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+
+#ifdef MUTE_WARNS
+   tp = NULL;  /* stifle idiot compiler warnings */
+   inp = NULL;
+#endif   /* MUTE_WARNS */
+   
+   fport = atoi(cp);
+   if((fport == 0) && (*cp != '0'))
+   {
+      ns_printf(pio, "need port number(s), fport[,lport]\n");
+      return -1;      
+   }
+   cp = strchr(cp, ',');   /* see if there's a comma */
+   if(cp)
+      lport = (unsigned)atoi((cp+1));
+   else
+      lport = 0;     /* wildcard */
+
+   /* look for matching connection */
+   for(so = (struct socket *)soq.q_head; so; so = so->next)
+   {
+      inp = (struct inpcb *)so->so_pcb;
+      if(!inp)
+         continue;
+      tp = (struct tcpcb *)inp->inp_ppcb;
+      if(!tp)
+         continue;
+      if(inp->inp_fport != htons(fport))
+         continue;
+      if((inp->inp_lport == htons(lport)) ||
+         (lport == 0))
+            break;
+   }
+   if(!so)
+   {
+      ns_printf(pio, "no socket matching ports %u,%u\n", fport,lport);
+      return -1;            
+   }
+
+   /* if we get here then so, inp and tp are all set */
+   ns_printf(pio,"IP: %u.%u.%u.%u, %u->%u, ", 
+      PUSH_IPADDR(inp->inp_faddr.s_addr),
+      htons(inp->inp_lport), htons(inp->inp_fport));
+
+   ns_printf(pio,"options: 0x%x, so_rcv.cc:%u, so_snd.cc:%u\n",
+      (unsigned)so->so_options,
+      (unsigned)so->so_rcv.sb_cc,(unsigned)so->so_snd.sb_cc);
+
+   ns_printf(pio, "snd_wnd:%d, rcv_wnd:%d, snd_cwnd:%d\n", 
+      tp->snd_wnd, tp->rcv_wnd, tp->snd_cwnd);
+
+#ifdef TCP_WIN_SCALE
+   ns_printf(pio, "snd_wnd_scale:%d, rcv_wnd_scale:%d\n",
+      tp->snd_wind_scale, tp->rcv_wind_scale);
+#endif
+
+   ns_printf(pio, "%s, snd_una:0x%lx, snd_nxt:0x%lx\n",
+      tcpstates[tp->t_state], tp->snd_una, tp->snd_nxt);
+
+   ns_printf(pio, "so_options: ");
+   dump_so_options(pio, so->so_options);
+   ns_printf(pio, "\nTCP flags: ");
+   dump_tp_tpflags(pio, tp->t_flags);
+   ns_printf(pio, "rtt:%d srtt:%d, \n", tp->t_rttick, tp->t_srtt);
+
+   return 0;
+}
+#endif   /* NET_STATS */
+
+extern int hex2bin(char * inbuf, unsigned char * outbuf, int bcount);
+
+int
+so_setopts(void * pio)
+{
+   int      err;
+   unshort  newopts;
+   char *   cp =  nextarg( ((GEN_IO)pio)->inbuf );
+
+   if(!cp || !*cp)
+   {
+      ns_printf(pio, "current default socket options are 0x%x\n",
+         socket_defaults);      
+#ifdef NET_STATS
+      dump_so_options(pio, socket_defaults);      
+      ns_printf(pio, "\n");      
+#endif   /* NET_STATS */
+      ns_printf(pio, "Enter new hex value to change them.\n");      
+      return 0;
+   }
+   err = hex2bin(cp, (u_char*)(&newopts), 2);
+   if(err)
+   {
+      ns_printf(pio, "Can't parse hex %s\n", cp);
+      return -1;
+   }
+   socket_defaults = htons(newopts);
+   ns_printf(pio, "default socket options set to 0x%x\n", socket_defaults);
+#ifdef NET_STATS
+   dump_so_options(pio, socket_defaults);      
+   ns_printf(pio, "\n");      
+#endif   /* NET_STATS */
+
+   return 0;
+}
+
+
+#endif   /* IN_MENUS - whole file can be ifdeffed out */
+#endif /* INCLUDE_TCP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_out.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_out.c
new file mode 100644
index 0000000..b6c7921
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_out.c
@@ -0,0 +1,1103 @@
+/*
+ * FILENAME: tcp_out.c
+ *
+ * Copyright 1997-2000 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcp_output(), tcp_setpersist()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define     TCPOUTFLAGS
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "in_pcb.h"
+#include "ip.h"
+#include "pmtu.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+
+/*
+ * Initial options. We always Use TCP MSS. In cases where we use other
+ * options we make the options buffer large enough for full sized option
+ * data header so that we can use it for option building later. We start
+ * by defining all the header sizes.
+ */
+
+#define  MSSOPT_LEN     4
+
+#ifdef TCP_SACK
+#define  SACKOPT_LEN    ((SACK_BLOCKS * 8) + 2)
+#else
+#define  SACKOPT_LEN    0
+#endif
+
+#ifdef TCP_WIN_SCALE
+#define  SWINOPT_LEN    4  /* actually 3, but round upwards */
+#else
+#define  SWINOPT_LEN    0
+#endif
+
+#ifdef TCP_TIMESTAMP
+#define  STAMPOPT_LEN   10
+#else
+#define  STAMPOPT_LEN   0
+#endif
+
+
+/* Add up all the option sizes for the worst case option buffer size */
+#define  OPTBUF_LEN (MSSOPT_LEN + SACKOPT_LEN + SWINOPT_LEN + STAMPOPT_LEN)
+
+/* create the buffer and fill in the MSS option */
+u_char   tcp_optionbuf[OPTBUF_LEN];
+
+static int   bld_options(struct tcpcb *, u_char *, int, struct socket *);
+
+
+/*
+ * TCP Headers and IPv6
+ *
+ *   The tcp_output() routine gets it's send data from an mbuf 
+ * queue in the socket structure. These mbufs contain only the 
+ * data to send, no headers. The tcp_output() code prepends an 
+ * IP/TCP header to this data for sending. In the old v4 code 
+ * this header was placed in a space in the front of the PACKET 
+ * containing the data mbuf. This  space had previously been  
+ * reserved for this purpose by getnbuf(). If there is no mbuf 
+ * data to send, then an mbuf large enough for the TCP/IP header
+ * structure "ti" is allocated.
+ * 
+ *   "ti" is a BSD invention. It contains an "overlay" IP header followed by
+ * a real TCP header. The overlay IP header has IP addresses at the end of 
+ * structure where a real IP header would, however the beginning of the 
+ * structure contains pointers which are used by the tcp_input() socket
+ * code to link the received TCP reassembly queue. When we are sending 
+ * packets (below) the v4 IP header is constructed in the "ti" structure,
+ * and the complete IP/TCP header is passed down to the IP layer in a single
+ * contiguous buffer.
+ * 
+ *   For IPv6, the IP header is 40 bytes instead of 20, and IPv6 is far more 
+ * likely than IPv4 to insert a field between the IP and TCP headers. For 
+ * these reasons, it's not as beneficial to keep the IP and TCP headers in a 
+ * contiguous buffer. So we don't. Instead we require that the system support 
+ * a scatter/gather version of the PACKET structures on which the mbufs are 
+ * mapped. The IPv6 code allocates a seperate mbuf for the IP header, and 
+ * builds the IP header seperatly from the TCP header. 
+ * 
+ *    Since we also want to support a dual-mode stack, we still maintain 
+ * the old "ti" strucuture for use by the the v4 packets, as well as 
+ * seperate IPv6 header mbuf used by the v6 code path. Thus the mbufs 
+ * allocated for TCP headers are still (about) 40 bytes in size.
+ */
+
+
+/* FUNCTION: tcp_output()
+ *
+ * Tcp output routine: figure out what should be sent and send it.
+ *
+ * PARAM1: struct tcpcb * tp 
+ *
+ * RETURNS: 0 if OK, else a sockets error code.
+ */
+
+int
+tcp_output(struct tcpcb * tp)
+{
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+   int   len;
+   long  win;
+   int   off,  flags,   error;
+   struct mbuf *  m;
+   struct tcpiphdr * ti;
+   unsigned optlen = 0;
+   int   idle, sendalot;
+   struct mbuf *  sendm;   /* mbuf which contains data to send */
+   struct mbuf * tcp_mbuf; /* mbuf containing TCP header */
+   int   bufoff;           /* offset of data in sendm->m_data */
+
+#ifdef TCP_SACK
+   int   sack_resend;
+   int   sack_hole = 0;    /* next sack hole to fill */
+
+   if(tp->t_flags & TF_SACKREPLY)
+   {
+      /* we are resending based on a received SACK header */
+      sack_resend = TRUE;
+      tp->t_flags &= ~TF_SACKREPLY;    /* clear flag */
+   }
+   else
+      sack_resend = FALSE;
+#endif /* TCP_SACK */
+   
+   /*
+    * Determine length of data that should be transmitted,
+    * and flags that will be used.
+    * If there is some data or critical controls (SYN, RST)
+    * to send, then transmit; otherwise, investigate further.
+    */
+   idle = (tp->snd_max == tp->snd_una);
+
+again:
+   sendalot = 0;
+   off = (int)(tp->snd_nxt - tp->snd_una);
+   win = (long)tp->snd_wnd;   /* set basic send window */
+   if (win > (long)tp->snd_cwnd) /* see if we need congestion control */
+   {
+      win = (int)(tp->snd_cwnd & ~(ALIGN_TYPE-1)); /* keep data aligned */
+   }
+
+   /*
+    * If in persist timeout with window of 0, send 1 byte.
+    * Otherwise, if window is small but nonzero
+    * and timer expired, we will send what we can
+    * and go to transmit state.
+    */
+   if (tp->t_force) 
+   {
+      if (win == 0)
+         win = 1;
+      else 
+      {
+         tp->t_timer[TCPT_PERSIST] = 0;
+         tp->t_rxtshift = 0;
+      }
+   }
+
+#ifdef TCP_SACK
+   /* See if we need to adjust the offset for a sack resend */
+   if(sack_resend)
+   {
+      off = (int)(tp->sack_hole_start[sack_hole] - tp->snd_una);
+      /* if this hole's already been acked then punt and move to next hole */
+      if(off < 0)
+      {
+         /* clear out the acked hole */
+         tp->sack_hole_start[sack_hole] = tp->sack_hole_end[sack_hole] = 0;
+         /* see if we're done with SACK hole list (2 tests) */
+         if(++sack_hole >= SACK_BLOCKS)
+            return 0;
+         if(tp->sack_hole_start[sack_hole] == tp->sack_hole_end[sack_hole])
+            return 0;
+         goto again;
+      }
+      tp->snd_nxt = tp->sack_hole_start[sack_hole];
+      len = (int)(tp->sack_hole_end[sack_hole] - tp->sack_hole_start[sack_hole]);
+      len = (int)MIN(len, (int)win);
+   }
+   else
+#endif /* TCP_SACK */
+   {
+      /* set length of packets which are not sack resends */
+      len = (int)MIN(so->so_snd.sb_cc, (unsigned)win) - off;
+   }
+
+   flags = tcp_outflags[tp->t_state];
+
+
+   /* See if we need to build TCP options field. This test should be fast. */
+
+#if (defined(TCP_TIMESTAMP) | defined(TCP_SACK))	   
+   if((flags & TH_SYN) ||
+/*   !!!???   (so->so_options & SO_TIMESTAMP) ||  */
+	  (tp->t_flags & TF_SACKNOW)
+	 )
+   {
+      optlen = bld_options(tp, &tcp_optionbuf[optlen], flags, so);
+   }
+#else
+   /* If other options not defined this build then don't bother to call bld_options() except 
+    * on SYN packets
+    */
+   if(flags & TH_SYN)
+   {
+      optlen = bld_options(tp, &tcp_optionbuf[optlen], flags, so);
+   }
+#endif
+
+   if (len < 0)
+   {
+      /*
+       * If FIN has been sent but not acked,
+       * but we haven't been called to retransmit,
+       * len will be -1.  Otherwise, window shrank
+       * after we sent into it.  If window shrank to 0,
+       * cancel pending retransmit and pull snd_nxt
+       * back to (closed) window.  We will enter persist
+       * state below.  If the window didn't close completely,
+       * just wait for an ACK.
+       */
+      len = 0;
+      if (win == 0) 
+      {
+         tp->t_timer[TCPT_REXMT] = 0;
+         tp->snd_nxt = tp->snd_una;
+      }
+   }
+
+   if (len > (int)tp->t_maxseg)
+   {
+      len = tp->t_maxseg;
+      sendalot = 1;
+   }
+
+#ifdef IP_V4
+#ifdef IP_PMTU
+   {
+      int pmtu = tp->t_inpcb->inp_pmtu - 40;
+
+      if (len > pmtu)
+      {
+         len = pmtu - 40;
+         sendalot = 1;
+      }
+   }
+#endif /* IP_PMTU */
+   /* We don't need a pmtu test for IPv6. V6 code limits t_maxseg to
+    * the Path MTU, so the test above the v4 ifdef above covers us.
+    */
+#endif /* IP_V4 */
+
+   if (SEQ_LT(tp->snd_nxt + len, tp->snd_una + so->so_snd.sb_cc))
+      flags &= ~TH_FIN;
+   win = (long)(sbspace(&so->so_rcv));
+
+   /*
+    * If our state indicates that FIN should be sent
+    * and we have not yet done so, or we're retransmitting the FIN,
+    * then we need to send.
+    */
+   if ((flags & TH_FIN) &&
+       (so->so_snd.sb_cc == 0) &&
+       ((tp->t_flags & TF_SENTFIN) == 0 || tp->snd_nxt == tp->snd_una))
+   {
+      goto send;
+   }
+   /*
+    * Send if we owe peer an ACK.
+    */
+   if (tp->t_flags & TF_ACKNOW)
+      goto send;
+   if (flags & (TH_SYN|TH_RST))
+      goto send;
+   if (SEQ_GT(tp->snd_up, tp->snd_una))
+      goto send;
+
+   /*
+    * Sender silly window avoidance.  If connection is idle
+    * and can send all data, a maximum segment,
+    * at least a maximum default-size segment do it,
+    * or are forced, do it; otherwise don't bother.
+    * If peer's buffer is tiny, then send
+    * when window is at least half open.
+    * If retransmitting (possibly after persist timer forced us
+    * to send into a small window), then must resend.
+    */
+   if (len)
+   {
+      if (len == (int)tp->t_maxseg)
+         goto send;
+      if ((idle || tp->t_flags & TF_NODELAY) &&
+          len + off >= (int)so->so_snd.sb_cc)
+      {
+         goto send;
+      }
+      if (tp->t_force)
+         goto send;
+      if (len >= (int)(tp->max_sndwnd / 2))
+         goto send;
+      if (SEQ_LT(tp->snd_nxt, tp->snd_max))
+         goto send;
+   }
+
+   /*
+    * Compare available window to amount of window
+    * known to peer (as advertised window less
+    * next expected input).  If the difference is at least two
+    * max size segments or at least 35% of the maximum possible
+    * window, then want to send a window update to peer.
+    */
+   if (win > 0)
+   {
+      int   adv   =  (int)win -  (int)(tp->rcv_adv -  tp->rcv_nxt);
+
+      if (so->so_rcv.sb_cc == 0 && adv >= (int)(tp->t_maxseg * 2))
+         goto send;
+      if (100 * (u_int)adv / so->so_rcv.sb_hiwat >= 35)
+         goto send;
+   }
+
+   /*
+    * TCP window updates are not reliable, rather a polling protocol
+    * using ``persist'' packets is used to insure receipt of window
+    * updates.  The three ``states'' for the output side are:
+    *   idle         not doing retransmits or persists
+    *   persisting      to move a small or zero window
+    *   (re)transmitting   and thereby not persisting
+    *
+    * tp->t_timer[TCPT_PERSIST]
+    *   is set when we are in persist state.
+    * tp->t_force
+    *   is set when we are called to send a persist packet.
+    * tp->t_timer[TCPT_REXMT]
+    *   is set when we are retransmitting
+    * The output side is idle when both timers are zero.
+    *
+    * If send window is too small, there is data to transmit, and no
+    * retransmit or persist is pending, then go to persist state.
+    * If nothing happens soon, send when timer expires:
+    * if window is nonzero, transmit what we can,
+    * otherwise force out a byte.
+    */
+   if (so->so_snd.sb_cc && tp->t_timer[TCPT_REXMT] == 0 &&
+       tp->t_timer[TCPT_PERSIST] == 0) 
+   {
+      tp->t_rxtshift = 0;
+      tcp_setpersist(tp);
+   }
+
+   /*
+    * No reason to send a segment, just return.
+    */
+   return (0);
+
+send:
+   ENTER_CRIT_SECTION(tp);
+
+   /* Limit send length to the current buffer so as to
+    * avoid doing the "mbuf shuffle" in m_copy().
+    */
+   bufoff = off;
+   sendm = so->so_snd.sb_mb;
+   if (len)
+   {
+      /* find mbuf containing data to send (at "off") */
+      while (sendm)  /* loop through socket send list */
+      {
+         bufoff -= sendm->m_len;
+         if (bufoff < 0)   /* if off is in this buffer, break */
+            break;
+         sendm = sendm->m_next;
+      }
+      if (!sendm) { dtrap();  /* shouldn't happen */ }
+      bufoff += sendm->m_len; /* index to next data to send in msend */
+
+      /* if socket has multiple unsent mbufs, set flag for send to loop */
+      if ((sendm->m_next) && (len > (int)sendm->m_len))
+      {
+         flags &= ~TH_FIN; /* don't FIN on segment prior to last */
+         sendalot = 1;     /* set to send more segments */
+      }
+      if((flags & TH_FIN) && (so->so_snd.sb_cc > (unsigned)len))
+      {
+         /* This can happen on slow links (PPP) which retry the last 
+          * segment - the one with the FIN bit attached to data.
+          */
+         flags &= ~TH_FIN; /* don't FIN on segment prior to last */
+      }
+
+      /* only send the rest of msend */
+      len = min(len, (int)sendm->m_len);
+
+      /* if we're not sending starting at sendm->m_data (in which 
+       * case bufoff != 0), then we will copy the data; else we would 
+       * write IP/TCP headers over sent but un-ack'ed data in sendm. 
+       * Similarly, if sendm->m_data is not aligned with respect to 
+       * sendm->m_base and ALIGN_TYPE, we will copy the data to 
+       * ensure that it (and the then-prepended IP/TCP headers) will 
+       * be aligned according to ALIGN_TYPE. 
+       */
+      if ((bufoff != 0) ||       /* data not front aligned in send mbuf? */
+          (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) != 0))
+      {
+         len = min(len, (int)(sendm->m_len - bufoff));   /* limit len again */
+
+         /* One more test - if this data is not aligned with the front
+          * of the m_data buffer then we can't use it in place, else we
+          * might write the IP/TCP header over data that has not yet
+          * been acked. In this case we must make sure our send
+          * fits into a little buffer and send what we can.
+          */
+         if ((len > (int)(lilbufsiz - HDRSLEN)) && /* length is bigger the small buffer? */
+             (bigfreeq.q_len < 2))      /* and we are low on big buffers */
+         {
+            len = lilbufsiz - HDRSLEN;
+         }
+      }
+   }
+
+   /* if send data is sufficiently aligned in packet, prepend TCP/IP header
+    * in the space provided. 
+    */
+   if (len && (bufoff == 0) && 
+       (sendm->pkt->inuse == 1) &&
+       (((sendm->m_data - sendm->m_base) & (ALIGN_TYPE - 1)) == 0) && 
+       (optlen == 0))
+   {
+      /* get an empty mbuf to "clone" the data */
+      m = m_getnbuf(MT_TXDATA, 0);
+      if (!m)
+      {
+         EXIT_CRIT_SECTION(tp);
+         return (ENOBUFS);
+      }
+      m->pkt = sendm->pkt; /* copy packet location in new mbuf */
+      m->pkt->inuse++;     /* bump packet's use count */
+      m->m_base = sendm->m_base; /* clone mbuf members */
+      m->m_memsz = sendm->m_memsz;
+      m->m_len = len + TCPIPHDRSZ;  /* adjust clone for header */
+      m->m_data = sendm->m_data - TCPIPHDRSZ;
+   }
+   else  /* either no data or data is not front aligned in mbuf */
+   {
+      /* Grab a header mbuf, attaching a copy of data to be 
+       * transmitted, and initialize the header from 
+       * the template for sends on this connection.
+       */
+      m = m_getwithdata (MT_HEADER, IFNETHDR_SIZE + TCPIPHDRSZ);
+      if (m ==(struct mbuf *)NULL)
+      {
+         EXIT_CRIT_SECTION(tp);
+         return ENOBUFS;
+      }
+
+      m->m_len = TCPIPHDRSZ;
+      m->m_data += IFNETHDR_SIZE;/* Move this to sizeof tcpip hdr leave*/
+      /* 14 bytes for ethernet header      */
+
+      if (len) /* attach any data to send */
+      {
+         m->m_next = m_copy(so->so_snd.sb_mb, off, (int) len);
+         if (m->m_next == 0)
+         {
+            m_freem(m);
+            EXIT_CRIT_SECTION(tp);
+            return ENOBUFS;
+         }
+      }
+   }
+   EXIT_CRIT_SECTION(tp);
+
+   if (len) 
+   {
+      if (tp->t_force && len == 1)
+         tcpstat.tcps_sndprobe++;
+      else if (SEQ_LT(tp->snd_nxt, tp->snd_max)) 
+      {
+         tcpstat.tcps_sndrexmitpack++;
+         tcpstat.tcps_sndrexmitbyte += len;
+#ifdef TCP_SACK
+      if(sack_resend)
+         tcpstat.tcps_sackresend++;
+#endif
+      } 
+      else 
+      {
+         tcpstat.tcps_sndpack++;
+         tcpstat.tcps_sndbyte += len;
+      }
+   }
+   else if (tp->t_flags & TF_ACKNOW)
+   {
+      tcpstat.tcps_sndacks++;
+   }
+   else if (flags & (TH_SYN|TH_FIN|TH_RST))
+      tcpstat.tcps_sndctrl++;
+   else if (SEQ_GT(tp->snd_up, tp->snd_una))
+      tcpstat.tcps_sndurg++;
+   else
+      tcpstat.tcps_sndwinup++;
+
+   ti = (struct tcpiphdr *)(m->m_data+sizeof(struct ip)-sizeof(struct ipovly));
+   if ((char *)ti < m->pkt->nb_buff)
+   {
+      panic("tcp_out- packet ptr underflow\n");
+   }
+   tcp_mbuf = m;        /* flag TCP header mbuf */
+
+#ifdef IP_V6  /* Dual mode code */
+   if(so->so_domain == AF_INET6)
+   {
+      m = mbuf_prepend(m, sizeof(struct ipv6));
+      if(m == NULL)
+      {
+         /* this can happen when we run out of mbufs or pkt buffers
+          * That is, mfreeq is empty or (lilfreeq, bigfreeq) are empty.
+          * One solution is to find out which one is getting full and
+          * then increase them.
+          */
+         dtrap();             /* This is really rare... */
+         m_freem(tcp_mbuf);   /* Free TCP/data chain */
+         return ENOBUFS;
+      }
+
+      /* strip overlay from front of TCP header */
+      tcp_mbuf->m_data += sizeof(struct ipovly);
+      tcp_mbuf->m_len -= sizeof(struct ipovly);
+   }
+#endif   /* end IP_V6 */
+
+   if (tp->t_template == 0)
+      panic("tcp_output");
+
+   MEMCPY((char*)ti, (char*)tp->t_template, sizeof(struct tcpiphdr));
+
+   /*
+    * Fill in fields, remembering maximum advertised
+    * window for use in delaying messages about window sizes.
+    * If resending a FIN, be sure not to use a new sequence number.
+    */
+   if (flags & TH_FIN && tp->t_flags & TF_SENTFIN && 
+       tp->snd_nxt == tp->snd_max)
+   {
+      tp->snd_nxt--;
+   }
+
+   ti->ti_seq = htonl(tp->snd_nxt);
+   ti->ti_ack = htonl(tp->rcv_nxt);
+
+   /*
+    * If we're sending a SYN, check the IP address of the interface
+    * that we will (likely) use to send the IP datagram -- if it's
+    * changed from what is in the template (as it might if this is
+    * a retransmission, and the original SYN caused PPP to start
+    * bringing the interface up, and PPP has got a new IP address
+    * via IPCP), update the template and the inpcb with the new 
+    * address.
+    */
+   if (flags & TH_SYN)
+   {
+      struct inpcb * inp;
+      inp = (struct inpcb *)so->so_pcb;
+
+      switch(so->so_domain)
+      {
+#ifdef IP_V4
+      case AF_INET:
+      {
+         ip_addr src;
+
+#ifdef INCLUDE_PPP
+
+         if(((flags & TH_ACK) == 0) && /* SYN only, not SYN/ACK */
+            (inp->ifp) &&              /* Make sure we have iface */
+            (inp->ifp->mib.ifType == PPP))   /* only PPP type */
+         {
+            dtrap(); /* remove after confirmed to work in PPP */ 
+            src = ip_mymach(ti->ti_dst.s_addr);
+
+         if (src != ti->ti_src.s_addr)
+         {
+            ti->ti_src.s_addr = src;
+            tp->t_template->ti_src.s_addr = src;
+            tp->t_inpcb->inp_laddr.s_addr = src;
+         }
+         }
+#endif   /* INCLUDE_PPP */
+
+         /* If this is a SYN (not a SYN/ACK) then set the pmtu */
+         if((flags & TH_ACK) == 0)
+         {
+#ifdef IP_PMTU
+            inp->inp_pmtu = pmtucache_get(inp->inp_faddr.s_addr);
+#else    /* not compiled for pathmtu, guess based on iface */
+            {
+               NET ifp;
+               /* find iface for route. Pass "src" as nexthop return */
+               ifp = iproute(ti->ti_dst.s_addr, &src);
+               if(ifp)
+                  inp->inp_pmtu = ifp->n_mtu - (ifp->n_lnh + 40);
+               else
+                  inp->inp_pmtu = 580;  /* Ugh. */
+            }
+#endif   /* IP_PMTU */
+         }
+         break;
+      }
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+      case AF_INET6:
+      {
+         struct ip6_inaddr * local;
+         
+         local = ip6_myaddr(&tp->t_inpcb->ip6_faddr, inp->ifp);
+
+         /* If we got a local address & it's not the one in the pcb, then
+          * we assume it changed at the iface and fix it in the pcb. Unlike 
+          * v4, we don't have an IP header yet, not do we have a template 
+          * to worry about.
+          */
+         if((local) && 
+            (!IP6EQ(&local->addr, &tp->t_inpcb->ip6_laddr)))
+         {
+            IP6CPY(&tp->t_inpcb->ip6_laddr, &local->addr);
+         }
+         /* If this is a SYN (not a SYN/ACK) then set the pmtu */
+         if((flags & TH_ACK) == 0)
+         {
+            inp->inp_pmtu = ip6_pmtulookup(&inp->ip6_laddr, inp->ifp);
+         }
+         break;
+      }
+#endif   /* IP_V6 */
+      default:
+         dtrap();    /* bad domain setting */
+      }
+   }
+
+   /* fill in options if any are set */
+   if (optlen)
+   {
+      struct mbuf * mopt;
+
+      mopt = m_getwithdata(MT_TXDATA, MAXOPTLEN);
+      if (mopt == NULL) 
+      {
+         m_freem(m);
+         return (ENOBUFS);
+      }
+
+      /* insert options mbuf after after tmp_mbuf */
+      mopt->m_next = tcp_mbuf->m_next;
+      tcp_mbuf->m_next = mopt;
+
+      /* extend options to aligned address */
+      while(optlen & 0x03)
+         tcp_optionbuf[optlen++] = TCPOPT_EOL;
+
+      MEMCPY(mtod(mopt, char *), tcp_optionbuf, optlen);
+      mopt->m_len = optlen;
+      /* use portable macro to set tcp data offset bits */
+      SET_TH_OFF(ti->ti_t, ((sizeof (struct tcphdr) + optlen) >> 2));
+   }
+
+   ti->ti_flags = (u_char)flags;
+   /*
+    * Calculate receive window. Don't shrink window,
+    * but avoid silly window syndrome.
+    */
+   if (win < (long)(so->so_rcv.sb_hiwat / 4) && win < (long)tp->t_maxseg)
+      win = 0;
+   if (win < (long)(tp->rcv_adv - tp->rcv_nxt))
+      win = (long)(tp->rcv_adv - tp->rcv_nxt);
+
+   /* do check for Iniche buffer limits -JB- */
+   if (bigfreeq.q_len == 0)   /* If queue length is 0, set window to 0 */
+   {
+      win = 0;
+   }
+   else if(win > (((long)bigfreeq.q_len - 1) * (long)bigbufsiz))
+   {
+      win = ((long)bigfreeq.q_len - 1) * bigbufsiz;
+   }
+
+#ifdef TCP_WIN_SCALE
+   if(tp->t_flags & TF_WINSCALE)
+   {
+      ti->ti_win = htons((u_short)(win >> tp->rcv_wind_scale)); /* apply scale */
+   }
+   else
+#endif /* TCP_WIN_SCALE */
+   {
+      ti->ti_win = htons((u_short)win);
+   }
+
+   if (SEQ_GT(tp->snd_up, tp->snd_nxt)) 
+   {
+      ti->ti_urp = htons((u_short)(tp->snd_up - tp->snd_nxt));
+      ti->ti_flags |= TH_URG;
+   }
+   else
+   {
+      /*
+       * If no urgent pointer to send, then we pull
+       * the urgent pointer to the left edge of the send window
+       * so that it doesn't drift into the send window on sequence
+       * number wraparound.
+       */
+      tp->snd_up = tp->snd_una;        /* drag it along */
+   }
+   /*
+    * If anything to send and we can send it all, set PUSH.
+    * (This will keep happy those implementations which only
+    * give data to the user when a buffer fills or a PUSH comes in.)
+    */
+   if (len && off+len == (int)so->so_snd.sb_cc)
+      ti->ti_flags |= TH_PUSH;
+
+   /*
+    * In transmit state, time the transmission and arrange for
+    * the retransmit.  In persist state, just set snd_max.
+    */
+   if (tp->t_force == 0 || tp->t_timer[TCPT_PERSIST] == 0) 
+   {
+      tcp_seq startseq = tp->snd_nxt;
+
+      /*
+       * Advance snd_nxt over sequence space of this segment.
+       */
+      if (flags & TH_SYN)
+         tp->snd_nxt++;
+
+      if (flags & TH_FIN)
+      {
+         tp->snd_nxt++;
+         tp->t_flags |= TF_SENTFIN;
+      }
+      tp->snd_nxt += len;
+      if (SEQ_GT(tp->snd_nxt, tp->snd_max)) 
+      {
+         tp->snd_max = tp->snd_nxt;
+         /*
+          * Time this transmission if not a retransmission and
+          * not currently timing anything.
+          */
+         if (tp->t_rttick == 0) 
+         {
+            tp->t_rttick = cticks;
+            tp->t_rtseq = startseq;
+            tcpstat.tcps_segstimed++;
+         }
+      }
+
+      /*
+       * Set retransmit timer if not currently set,
+       * and not doing an ack or a keep-alive probe.
+       * Initial value for retransmit timer is smoothed
+       * round-trip time + 2 * round-trip time variance.
+       * Initialize shift counter which is used for backoff
+       * of retransmit time.
+       */
+      if (tp->t_timer[TCPT_REXMT] == 0 &&
+          tp->snd_nxt != tp->snd_una) 
+      {
+         tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+         if (tp->t_timer[TCPT_PERSIST]) 
+         {
+            tp->t_timer[TCPT_PERSIST] = 0;
+            tp->t_rxtshift = 0;
+         }
+      }
+   }
+   else
+   {
+      if (SEQ_GT(tp->snd_nxt + len, tp->snd_max))
+         tp->snd_max = tp->snd_nxt + len;
+   }
+
+#ifdef DO_TCPTRACE
+   tcp_trace("tcp_output: sending, state %d, tcpcb: %x",
+    tp->t_state, tp );
+#endif
+
+#ifdef MUTE_WARNS
+   error = 0;
+#endif
+
+#ifdef IP_V4
+#ifdef IP_V6     /* Test domain on v4/v6 builds */
+   if(so->so_domain != AF_INET6)
+#endif   /* IP_V6 */
+   {
+      struct ip * pip;
+   
+      pip = mtod(m, struct ip *);
+      /* Fill in IP length and send to IP level. */
+      pip->ip_len = (u_short)(TCPIPHDRSZ + optlen + len);
+      error = ip_output(m, so->so_optsPack);
+   }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   if(so->so_domain == AF_INET6)
+   {
+      struct ipv6 * pip6;
+
+      /* fill in ipv6 header src & dest from socket info */
+      pip6 = (struct ipv6 *)m->m_data;
+      IP6CPY(&pip6->ip_src, &tp->t_inpcb->ip6_laddr);
+      IP6CPY(&pip6->ip_dest, &tp->t_inpcb->ip6_faddr);
+
+      /* send down to glue layer to IPv6 */
+      /* and don't forget the so_optsPack */
+      if (tp)
+         if (tp->t_inpcb)
+			      if (tp->t_inpcb->inp_socket)
+                  error = tcp6_send(tp, m, &ti->ti_t,
+                     (sizeof(struct ipv6) + sizeof(struct tcphdr) + optlen + len),
+                     tp->t_inpcb->inp_socket->so_optsPack);
+      			else
+                  error = tcp6_send(tp, m, &ti->ti_t,
+                    (sizeof(struct ipv6) + sizeof(struct tcphdr) + optlen + len),
+                    (struct   ip_socopts *)0);          
+   }
+#endif   /* IP_V6 */
+
+   if (error)
+   {
+      if (error == ENOBUFS)   /* ip_output needed a copy buffer it couldn't get */
+      {
+         if (m->m_type == MT_FREE)  /* ip_output() probably freed first mbuf */
+            m = m->m_next;
+         m_freem(m); /* free the mbuf chain */
+         tcp_quench(tp->t_inpcb);
+         return (error);
+      }
+      return (error);
+   }
+
+   /*
+    * Data sent (as far as we can tell).
+    */
+
+   TCP_MIB_INC(tcpOutSegs);   /* keep MIB stats */
+   tcpstat.tcps_sndtotal++;
+
+#ifdef TCP_SACK
+   /* If we're doing a sack driven resend then update the sack info.*/
+   if(sack_resend)
+   {
+      /* snd_nxt has been maintined by the above code to reflect 
+       * the amount of data space covered by the send, so we use 
+       * it to update sack_start.
+       */
+      if((tp->sack_hole_start[sack_hole] + len) != tp->snd_nxt)
+      {
+         dtrap(); /* tmp debug ... can this happen? */
+      }
+      tp->sack_hole_start[sack_hole] = tp->snd_nxt;
+
+      /* If the sack hole is filled, move to next hole */
+      if(tp->sack_hole_start[sack_hole] >= tp->sack_hole_end[sack_hole])
+      {
+         /* set next byte to send to end of hole */
+         tp->snd_nxt = tp->sack_hole_end[sack_hole];
+         /* Done with hole, flag this by clearing out values */
+         tp->sack_hole_start[sack_hole] = tp->sack_hole_end[sack_hole] = 0;
+         sack_hole++;      /* move on to next hole */
+
+         /* If next hole has no set data then we are done */
+         if(tp->sack_hole_start[sack_hole] == tp->sack_hole_end[sack_hole])
+         {
+            sendalot = 0;     /* done with sack-based resent */
+         }
+      }
+   }
+#endif /* TCP_SACK */
+
+#ifdef TCP_TIMESTAMP
+   /* save last ACK to peer for timestamp features */
+   if(tp->t_flags & TF_TIMESTAMP)
+      tp->last_ack = htonl(ti->ti_ack);
+#endif   /* TCP_TIMESTAMP */
+
+   /*
+    * If this advertises a larger window than any other segment,
+    * then remember the size of the advertised window.
+    * Any pending ACK has now been sent.
+    */
+   if (win > 0 && SEQ_GT(tp->rcv_nxt+win, tp->rcv_adv))
+      tp->rcv_adv = tp->rcv_nxt + (unsigned)win;
+   tp->t_flags &= ~(TF_ACKNOW|TF_SACKNOW|TF_DELACK);
+   if (sendalot)
+      goto again;
+   return (0);
+}
+
+
+
+/* FUNCTION: tcp_setpersist()
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: NA
+ */
+
+void
+tcp_setpersist(struct tcpcb * tp)
+{
+   int   t;
+
+   t = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1;
+
+   if (tp->t_timer[TCPT_REXMT])
+      panic("tcp_output REXMT");
+   /*
+    * Start/restart persistance timer.
+    */
+   TCPT_RANGESET(tp->t_timer[TCPT_PERSIST],
+    t * tcp_backoff[tp->t_rxtshift],
+    TCPTV_PERSMIN, TCPTV_PERSMAX);
+   if (tp->t_rxtshift < TCP_MAXRXTSHIFT)
+      tp->t_rxtshift++;
+
+}
+
+
+/* FUNCTION: bld_options()
+ *
+ * Build tcp options for tp passed in buffer passed. No length checking
+ * is done on the buffer.
+ *
+ * PARAM1: struct tcpcb * tp
+ * PARAM1: char * cp         - buffer for building options
+ * PARAM3: int flags         - option flags of pkt to send
+ *
+ * RETURNS: length of option data added to buffer
+ */
+
+static int
+bld_options(struct tcpcb * tp, u_char * cp, int flags, struct socket * so)
+{
+   int      len;
+   u_short  mss;
+
+   if(tp->t_flags & TF_NOOPT)    /* no options allowed? */
+      return 0;
+
+   /* Alway put MSS option on SYN packets */
+   if (flags & TH_SYN)
+   {
+      mss   =  (u_short)tcp_mss(so);
+
+      /* always send MSS option on SYN, fill in MSS parm */
+      *(cp + 0) = TCPOPT_MAXSEG;
+      *(cp + 1) = MSSOPT_LEN;               /* length byte */
+      *(cp + 2)  = (u_char) ((mss & 0xff00) >> 8);
+      *(cp + 3)  = (u_char) (mss & 0xff);
+      len = 4;
+      cp += 4;
+   }
+   else
+      len = 0;
+
+#ifdef TCP_SACK
+
+	IPV6LOG(("+  bld_options SACK tp->t_flags = %x\n", (unsigned int)tp->t_flags));   
+	IPV6LOG(("+ bld_options SACK (tp->t_flags & (TF_SACKNOW|TF_SACKOK)) = %x\n", 
+		(unsigned int)(tp->t_flags & (TF_SACKNOW|TF_SACKOK))));   
+   
+   
+   /* on SYN and SYN/ACK pkts attach SACK OK option */
+   if((flags & TH_SYN) &&
+      (so->so_options & SO_TCPSACK))
+   {
+      *cp++ = TCPOPT_SACKOK;
+      *cp++ = 2;  /* length */
+      len += 2;
+   }
+
+   /* If we should be sending a SACK data option packet, prepare it */
+   if((tp->t_flags & (TF_SACKNOW|TF_SACKOK)) == (TF_SACKNOW|TF_SACKOK))
+   {
+      int tmp;
+      tmp = tcp_buildsack(tp, cp);
+      len += tmp;
+      cp += tmp;
+   }
+#endif /* TCP_SACK */
+
+#ifdef TCP_WIN_SCALE
+   /* TCP Window Scale options only go on packets with SYN bit set */
+   if((flags & TH_SYN) &&
+      (so->so_options & SO_WINSCALE))
+   {
+      if(flags & TH_ACK)   /* sending a SYN/ACK */
+      {
+         if(tp->t_flags & TF_WINSCALE)    /* did he offer to scale? */
+         {
+            /* On SYN/ACKs, reply to scale offer */
+            *cp++ = TCPOPT_WINSCALE ;  /* window scale option */
+            *cp++ = 3;                 /* option length */
+            *cp++ = tp->rcv_wind_scale;
+            len += 3;
+         }
+      }
+      else     /* sending a SYN */
+      {
+         /* send scale offer with plain SYNs */
+         *cp++ = TCPOPT_WINSCALE ;  /* window scale option */
+         *cp++ = 3;                 /* option length */
+         *cp++ = tp->rcv_wind_scale;
+         *cp++ = TCPOPT_NOP;        /* Pad out to 4 bytes. */
+         len += 4;
+      }
+   }
+#endif   /* TCP_WIN_SCALE */
+
+#ifdef TCP_TIMESTAMP
+   /* 
+    * Only add timestamp (RTTM) option IF option flag is set AND
+    * it's a SYN packet OR 
+    * we've already agreed to use RTTM.
+    */
+   if((so->so_options & SO_TIMESTAMP) &&
+      (((flags & (TH_SYN|TH_ACK)) == TH_SYN)|| 
+       (tp->t_flags & TF_TIMESTAMP)))
+   {
+      *cp = TCPOPT_RTT;     /* window scale option */
+      *(cp + 1) = 10;       /* option length */
+
+      /* set set our send time for echo */
+      tcp_putseq(cp + 2, cticks);
+
+      /* echo the last time we got from peer */
+      tcp_putseq(cp + 6, tp->ts_recent);
+      cp += 10;
+      len += 10;
+   }
+#endif   /* TCP_TIMESTAMP */
+
+   USE_ARG(so);
+   return len;
+}
+
+
+
+#endif /* INCLUDE_TCP */
+
+
+/* end of file tcp_out.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_seq.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_seq.h
new file mode 100644
index 0000000..3f6f377
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_seq.h
@@ -0,0 +1,80 @@
+/*
+ * FILENAME: tcp_seq.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: TCP
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _TCP_SEQ_H
+#define  _TCP_SEQ_H  1
+
+/*
+ * TCP sequence numbers are 32 bit integers operated
+ * on with modular arithmetic.  These macros can be
+ * used to compare such integers.
+ */
+#define     SEQ_LT(a,b)    ((long)((a)-(b))  <  0)
+#define     SEQ_LEQ(a,b)   ((long)((a)-(b))  <= 0)
+#define     SEQ_GT(a,b)    ((long)((a)-(b))  >  0)
+#define     SEQ_GEQ(a,b)   ((long)((a)-(b))  >= 0)
+
+
+/*
+ * Macros to initialize tcp sequence numbers for
+ * send and receive from initial send and receive
+ * sequence numbers.
+ */
+#define   tcp_rcvseqinit(tp) \
+   (tp)->rcv_adv = (tp)->rcv_nxt = (tp)->irs + 1
+
+#define   tcp_sendseqinit(tp) \
+   (tp)->snd_una = (tp)->snd_nxt = (tp)->snd_max = (tp)->snd_up = \
+       (tp)->iss
+
+#define     TCP_ISSINCR    (long)(0x0001F4FF)   /* increment for tcp_iss each second */
+
+#ifdef KERNEL
+extern   tcp_seq     tcp_iss;    /* tcp initial send seq # */
+#endif
+
+#endif
+
+/* end of file tcp_seq.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_subr.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_subr.c
new file mode 100644
index 0000000..4f4f9ee
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_subr.c
@@ -0,0 +1,569 @@
+/*
+ * FILENAME: tcp_subr.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcp_init(), tcp_template(), tcp_respond(), 
+ * ROUTINES: tcp_newtcpcb(), tcp_drop(), tcp_close(), tcp_quench(),
+ * ROUTINES: tcp_getseq(), tcp_putseq(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "protosw.h"
+#include "in_pcb.h"
+#include "ip.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+int      tcp_ttl  =  TCP_TTL;
+
+struct   tcpstat  tcpstat;
+struct  inpcb  tcb;
+
+
+#ifdef TCP_BIGCWND      /* Support for Large initial congestion window */
+int      use_default_cwnd = 1;         /* Flag to use this on all sockets */
+u_long   default_cwnd = (2*TCP_MSS);  /* initial cwnd value to use */
+#endif   /* TCP_BIGCWND */
+
+
+/* FUNCTION: tcp_init()
+ * 
+ * Tcp initialization
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_init()
+{
+   tcp_iss = 1;      /* wrong */
+   tcb.inp_next = tcb.inp_prev = &tcb;
+}
+
+
+
+/* FUNCTION: tcp_template()
+ *
+ * Create template to be used to send tcp packets on a connection.
+ * Call after host entry created, allocates an mbuf and fills
+ * in a skeletal tcp/ip header, minimizing the amount of work
+ * necessary when the connection is used.
+ *
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: 
+ */
+
+struct tcpiphdr * 
+tcp_template(struct tcpcb * tp)
+{
+   struct inpcb * inp   =  tp->t_inpcb;
+   struct tcpiphdr * n;
+
+   if ((n = tp->t_template) == 0)
+   {
+      n = (struct tcpiphdr *)TPH_ALLOC (sizeof (*n));
+      if (n == NULL)
+         return (0);
+   }
+   n->ti_next = n->ti_prev = 0;
+   n->ti_len = htons(sizeof (struct tcpiphdr) - sizeof (struct ip));
+   n->ti_src = inp->inp_laddr;
+   n->ti_dst = inp->inp_faddr;
+   n->ti_sport = inp->inp_lport;
+   n->ti_dport = inp->inp_fport;
+   n->ti_seq = 0;
+   n->ti_ack = 0;
+   n->ti_t.th_doff = (5 << 4);   /* NetPort */
+   n->ti_flags = 0;
+   n->ti_win = 0;
+   n->ti_sum = 0;
+   n->ti_urp = 0;
+   return (n);
+}
+
+
+/* FUNCTION: tcp_respond()
+ *
+ * Send a single message to the TCP at address specified by
+ * the given TCP/IP header.  If flags==0, then we make a copy
+ * of the tcpiphdr at ti and send directly to the addressed host.
+ * This is used to force keep alive messages out using the TCP
+ * template for a connection tp->t_template.  If flags are given
+ * then we send a message back to the TCP which originated the
+ * segment ti, and discard the mbuf containing it and any other
+ * attached mbufs.
+ *
+ * In any case the ack and sequence number of the transmitted
+ * segment are as specified by the parameters.
+ *
+ * 
+ * PARAM1: struct tcpcb *tp
+ * PARAM2: struct tcpiphdr *ti
+ * PARAM3: tcp_seq ack
+ * PARAM4: tcp_seq seq
+ * PARAM5: int flags
+ * PARAM6: struct mbuf *ti_mbuf
+ *
+ * RETURNS: 
+ */
+
+#define  xchg(a,b,type) {  type  t; t=a;  a=b;  b=t;  }
+
+void
+tcp_respond(struct tcpcb * tp,
+   struct tcpiphdr * ti,
+   tcp_seq  ack,
+   tcp_seq  seq,
+   int   flags,
+   struct mbuf *  ti_mbuf)
+{
+   int      tlen;       /* tcp data len - 0 or 1 */
+   int      domain;     /* AF_INET or AF_INET6 */
+   int      win = 0;    /* window to use in sent packet */
+   struct mbuf *  m;    /* mbuf to send */
+   struct tcpiphdr * tmp_thdr;   /* scratch */
+
+   if (tp)
+      win = (int)sbspace(&tp->t_inpcb->inp_socket->so_rcv);
+
+   /* Figure out of we can recycle the passed buffer or if we need a 
+    * new one. Construct the easy parts of the the TCP and IP headers.
+    */
+   if (flags == 0)   /* sending keepalive from timer */
+   {
+      /* no flags == need a new buffer */
+      m = m_getwithdata (MT_HEADER, 64);
+      if (m == NULL)
+         return;
+      tlen = 1;   /* Keepalives have one byte of data */
+      m->m_len = TCPIPHDRSZ + tlen;
+      /*
+       * Copy template contents into the mbuf and set ti to point
+       * to the header structure in the mbuf.
+       */
+      tmp_thdr = (struct tcpiphdr *)((char *)m->m_data+sizeof(struct ip)
+         - sizeof(struct ipovly));
+      if ((char *)tmp_thdr < m->pkt->nb_buff)
+      {
+         panic("tcp_respond- packet ptr underflow\n");
+      }
+      MEMCPY(tmp_thdr, ti, sizeof(struct tcpiphdr));
+      ti = tmp_thdr;
+      flags = TH_ACK;
+      domain = tp->t_inpcb->inp_socket->so_domain;
+   }
+   else  /* Flag was passed (e.g. reset); recycle passed mbuf */
+   {
+      m = ti_mbuf;   /*dtom(ti);*/
+      if(m->pkt->type == IPTP)   /* IPv4 packet */
+         domain = AF_INET;
+      else
+         domain = AF_INET6;
+
+      m_freem(m->m_next);
+      m->m_next = 0;
+      tlen = 0;         /* NO data */
+      m->m_len = TCPIPHDRSZ;
+      xchg(ti->ti_dport, ti->ti_sport, u_short);
+      if(m->pkt->type == IPTP)
+         xchg(ti->ti_dst.s_addr, ti->ti_src.s_addr, u_long);
+      if (flags & TH_RST)  /* count resets in MIB */
+         TCP_MIB_INC(tcpOutRsts);   /* keep MIB stats */
+   }
+
+   /* finish constructing the TCP header */
+   ti->ti_seq = htonl(seq);
+   ti->ti_ack = htonl(ack);
+   ti->ti_t.th_doff = 0x50;      /* NetPort: init data offset bits */
+   ti->ti_flags = (u_char)flags;
+   ti->ti_win = htons((u_short)win);
+   ti->ti_urp = 0;
+
+   /* Finish constructing IP header and send, based on IP type in use */
+   switch(domain)
+   {
+#ifdef IP_V4
+      case AF_INET:
+      {
+         struct ip * pip;
+
+         pip = (struct ip *)((char*)ti+sizeof(struct ipovly)-sizeof(struct ip));
+
+         pip->ip_len = (unshort)(TCPIPHDRSZ + tlen);
+
+         /* If our system's max. MAC header size is geater than the size 
+          * of the MAC header in the received packet then we need to 
+          * adjust the IP header offset to allow for this. Since the packets 
+          * are only headers they should always fit.
+          */
+         if(pip >= (struct ip *)(m->pkt->nb_buff + MaxLnh))
+         {
+            m->m_data = (char*)pip; /* headers will fit, just set pointer */
+         }
+         else     /* MAC may not fit, adjust pointer and move headers back */
+         {
+            m->m_data = m->pkt->nb_prot = m->pkt->nb_buff + MaxLnh;  /* new ptr */
+            MEMMOVE(m->m_data, pip, TCPIPHDRSZ);  /* move back tcp/ip headers */
+         }
+
+         /*
+          * In the case of a SYN DOS attack, many RST|ACK replies
+          *   have no tp structure and need to be freed.
+          */
+         if (!tp)
+              m_freem(m);
+         else
+		 {
+			 if ((tp->t_inpcb) && (tp->t_inpcb->inp_socket))
+				ip_output(m, tp->t_inpcb->inp_socket->so_optsPack);
+			 else
+				ip_output(m, (struct   ip_socopts *)NULL);
+		 }
+
+         break;
+      }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      case AF_INET6:
+      {
+         struct ipv6 *  pip6;
+         struct mbuf *  ip_m;     /* IP header's mbuf */
+
+         /* Get mbuf space for the IP header. mbuf m shold contain the
+          * TCP header somewhere, so set m_dsata to that and try to prepend 
+          * an IPv6 header.
+          */
+         m->m_data = (char*)&ti->ti_t;    /* TCP header */
+         m->m_len = sizeof(struct tcphdr);
+         ip_m = mbuf_prepend(m, sizeof(struct ipv6));
+         if(!ip_m)
+         {
+            m_free(m);
+            return;
+         }
+
+         pip6 = (struct ipv6 *)ip_m->m_data;
+
+         /* we have to find the IPv6 addresses. If a packet was passed
+          * then get them form that, otherwise get them from the passed tp.
+          * we should always have one or the other.
+          */
+         if(ti_mbuf)
+         {
+            ip6_addr       tmp;
+            struct ipv6 * inpip = ti_mbuf->pkt->ip6_hdr;
+
+            /* pip6 and inpip may be the same, so swap the IP addresses
+             * through a tmp variable.
+             */
+            IP6CPY(&tmp, &inpip->ip_src);
+            IP6CPY(&pip6->ip_src, &inpip->ip_dest);
+            IP6CPY(&pip6->ip_dest, &tmp);
+         }
+         else if(tp)
+         {
+            struct inpcb * inp = tp->t_inpcb;
+
+            IP6CPY(&pip6->ip_src, &inp->ip6_laddr);
+            IP6CPY(&pip6->ip_dest, &inp->ip6_faddr);
+         }
+         else
+         {
+            dtrap();
+            break;
+         }
+         /* best effort send */
+         /* send down to glue layer to IPv6 */
+         /* and don't forget the so_optsPack */
+         if (tp)
+            if (tp->t_inpcb)
+			         if (tp->t_inpcb->inp_socket)
+                  tcp6_send(tp, ip_m, &ti->ti_t, 
+                     sizeof(struct ipv6) + sizeof(struct tcphdr) + tlen,
+                     tp->t_inpcb->inp_socket->so_optsPack);
+			         else
+                  tcp6_send(tp, ip_m, &ti->ti_t, 
+                     sizeof(struct ipv6) + sizeof(struct tcphdr) + tlen,
+                     (struct   ip_socopts *)0);
+
+         break;
+      }
+#endif   /* IP_V6 */
+      default:
+         dtrap();
+         break;
+   }
+   return;
+}
+
+#undef xchg
+
+
+/* FUNCTION: tcp_newtcpcb()
+ *
+ * Create a new TCP control block, making an
+ * empty reassembly queue and hooking it to the argument
+ * protocol control block.
+ *
+ * 
+ * PARAM1: struct inpcb *inp
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_newtcpcb(struct inpcb * inp)
+{
+   struct tcpcb * tp;
+   short t_time;
+
+   tp = TCB_ALLOC(sizeof (*tp));
+   if (tp == NULL)
+      return (struct tcpcb *)NULL;
+   tp->seg_next = tp->seg_prev = (struct tcpiphdr *)tp;
+   tp->t_maxseg = TCP_MSS;
+   tp->t_flags = 0;        /* sends options! */
+   tp->t_inpcb = inp;
+   /*
+    * Init srtt to TCPTV_SRTTBASE (0), so we can tell that we have no
+    * rtt estimate.  Set rttvar so that srtt + 2 * rttvar gives
+    * reasonable initial retransmit time.
+    */
+   tp->t_srtt = TCPTV_SRTTBASE;
+   tp->t_rttvar = TCPTV_SRTTDFLT << 2;
+
+   t_time = ((TCPTV_SRTTBASE >> 2) + (TCPTV_SRTTDFLT << 2)) >> 1;
+   TCPT_RANGESET(tp->t_rxtcur, t_time, TCPTV_MIN, TCPTV_REXMTMAX);
+
+   /* Set initial congestion window - RFC-2581, pg 4. */
+   tp->snd_cwnd = 2 * TCP_MSS;
+
+#ifdef TCP_BIGCWND
+   /* See if we should set a large initial congestion window (RFC-2518) */
+   if((use_default_cwnd) ||
+      (inp->inp_socket->so_options & SO_BIGCWND))
+   {
+      tp->snd_cwnd = default_cwnd;
+   }
+#endif
+
+
+#ifdef TCP_WIN_SCALE
+   /* set TCP window scaling factor to outgoing window. The window we are
+    * sending is what we are silling to receive, so rfc1323 calls this the
+    * "rcv.wind.scale". We will try to negotiate this on the syn/ack
+    * handshake and back off to zero if it fails.
+    */
+   tp->rcv_wind_scale = default_wind_scale;
+#endif   /* TCP_WIN_SCALE */
+
+#ifdef DO_DELAY_ACKS
+   tp->t_delacktime = 1;
+#endif   /* DO_DELAY_ACKS */
+
+   tp->snd_ssthresh = 65535;  /* Start with high slow-start threshold */
+
+   inp->inp_ppcb = (char *)tp;
+   return (tp);
+}
+
+
+/* FUNCTION: tcp_drop()
+ *
+ * Drop a TCP connection, reporting
+ * the specified error.  If connection is synchronized,
+ * then send a RST to peer.
+ *
+ * 
+ * PARAM1: struct tcpcb *tp
+ * PARAM2: int err
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_drop(struct tcpcb * tp, int err)
+{
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+
+   if (TCPS_HAVERCVDSYN(tp->t_state)) 
+   {
+      tp->t_state = TCPS_CLOSED;
+      (void) tcp_output(tp);
+      tcpstat.tcps_drops++;
+   }
+   else
+      tcpstat.tcps_conndrops++;
+   so->so_error = err;
+#ifdef TCP_ZEROCOPY
+   if (so->rx_upcall)
+      so->rx_upcall(so, NULL, err);
+#endif   /* TCP_ZEROCOPY */
+   return (tcp_close(tp));
+}
+
+
+/* FUNCTION: tcp_close()
+ *
+ * Close a TCP control block:
+ *   discard all space held by the tcp
+ *   discard internet protocol block
+ *   wake up any sleepers
+ *
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_close(struct tcpcb * tp)
+{
+   struct tcpiphdr * t;
+   struct inpcb * inp   =  tp->t_inpcb;
+   struct socket *   so =  inp->inp_socket;
+   struct mbuf *  m;
+
+   t = tp->seg_next;
+   while (t != (struct tcpiphdr *)tp) 
+   {
+      t = (struct tcpiphdr *)t->ti_next;
+      m = dtom(t->ti_prev);
+      remque(t->ti_prev);
+      m_freem (m);
+   }
+   if (tp->t_template)
+      TPH_FREE (tp->t_template);
+   TCB_FREE (tp);
+   inp->inp_ppcb = 0;
+   soisdisconnected(so);
+   in_pcbdetach(inp);
+   tcpstat.tcps_closed++;
+   return ((struct tcpcb *)0);
+}
+
+
+/* FUNCTION: tcp_quench()
+ *
+ * When a source quench is received, close congestion window
+ * to one segment.  We will gradually open it again as we proceed.
+ *
+ * 
+ * PARAM1: struct inpcb *inp
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_quench(struct inpcb * inp)
+{
+   struct tcpcb * tp =  intotcpcb(inp);
+
+   if (tp)
+      tp->snd_cwnd = tp->t_maxseg;
+}
+
+
+/* FUNCTION: tcp_putseq()
+ *
+ * put tcp seq in options header
+ *
+ * PARAM1: char * cp - pointer to buffer to insert number
+ * PARAM2: 32 bit number to insert
+ *
+ * RETURNS: pointer to end of buffer (cp + 4)
+ */
+
+/* tcp_putseq()  */
+
+u_char *
+tcp_putseq(u_char * cp, tcp_seq seq)
+{
+   int   i;
+
+   cp += 3;                /* do low byte first */
+   for(i = 0; i< 4; i++)   /* put 4 bytes into buffer */
+   {
+      *cp-- = (u_char)(seq & 0xFF);  /* back through buffer */
+      seq >>= 8;
+   }
+   return (cp + 5);
+}
+
+/* FUNCTION: tcp_getseq()
+ *
+ * SACK utility to extract a long (tcp seq) from a character pointer. It
+ * does this bytewise so that the long does not have to be on a 32 bit
+ * boundary, as is the case in SACK options headers.
+ * 
+ * PARAM1: char * cp - pointer to 32 bit net-endian number
+ *
+ * RETURNS: a long in local endian
+ */
+
+u_long
+tcp_getseq(u_char * cp)
+{
+   int i;
+   ulong seq = 0;
+
+   for(i = 0; i < 4; i++)
+   {
+      seq <<= 8;
+      seq += (u_long)*(cp++);
+   }
+   return seq;
+}
+
+#endif /* INCLUDE_TCP */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.c
new file mode 100644
index 0000000..19e4614
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.c
@@ -0,0 +1,438 @@
+/*
+ * FILENAME: tcp_timr.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcp_fasttimo(), tcp_slowtimo(), tcp_canceltimers(), 
+ * ROUTINES: tcp_timers(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "protosw.h"
+#include "in_pcb.h"
+#include "ip.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+
+int      tcp_keepidle   =  TCPTV_KEEP_IDLE;
+int      tcp_keepintvl  =  TCPTV_KEEPINTVL;
+int      tcp_maxidle;
+
+#ifdef DO_DELAY_ACKS
+
+/* FUNCTION: tcp_fasttimo()
+ *
+ * Fast timeout routine for processing delayed acks. This should be
+ * called once per ctick to get the delayed ACK timing correct.
+ * 
+ * PARAM1: none.
+ *
+ * RETURNS: none.
+ */
+
+void
+tcp_fasttimo(void)
+{
+   struct inpcb * inp;
+   struct tcpcb * tp;
+
+   inp = tcb.inp_next;
+   if (inp)
+      for (; inp != &tcb; inp = inp->inp_next)
+   {
+      if ((tp = (struct tcpcb *)inp->inp_ppcb) &&
+          (tp->t_flags & TF_DELACK)) 
+      {
+         if(--tp->t_delackcur <= 0)
+         {
+            tp->t_delackcur = tp->t_delacktime;
+            tp->t_flags &= ~TF_DELACK;
+            tp->t_flags |= TF_ACKNOW;
+            tcpstat.tcps_delack++;
+            (void) tcp_output(tp);
+         }
+      }
+   }
+}
+#endif   /* DO_DELAY_ACKS */
+
+
+
+/* FUNCTION: tcp_slowtimo()
+ *
+ * Tcp protocol timeout routine called every 500 ms.
+ * Updates the timers in all active tcb's and
+ * causes finite state machine actions if timers expire.
+ *
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_slowtimo(void)
+{
+   struct inpcb * ip, * ipnxt;
+   struct tcpcb * tp;
+   int   i;
+   struct socket * so, * sonext;
+   struct sockbuf *  sb;
+
+   tcp_maxidle = TCPTV_KEEPCNT * tcp_keepintvl;
+
+   /* search through open sockets */
+   for (so = (struct socket *)soq.q_head; so != NULL; so = sonext)
+   {
+      sonext = so->next;
+
+      /* for SOCK_STREAM (TCP) sockets, we must do slow-timeout 
+       * processing and (optionally) processing of pending 
+       * zero-copy socket upcalls.
+       */
+      if (so->so_type == SOCK_STREAM)
+      {
+         ip = so->so_pcb;
+         if (!ip)
+            continue;
+         ipnxt = ip->inp_next;
+
+         tp = intotcpcb(so->so_pcb);
+         if (!tp)
+            continue;
+
+         for (i = 0; i < TCPT_NTIMERS; i++) 
+         {
+            if (tp->t_timer[i] && --tp->t_timer[i] == 0) 
+            {
+               /* call usrreq to do actual work */
+               so->so_req = PRU_SLOWTIMO;
+               (void) tcp_usrreq(so, (struct mbuf *)0, 
+                                 LONG2MBUF((long)i));
+
+               /* If ip disappeared on us, handle it */
+               if (ipnxt->inp_prev != ip)
+                  goto tpgone;
+            }
+         }
+      
+#ifdef TCP_ZEROCOPY
+         /* also nudge sockets which may have missed an upcall. We have
+          * to test for a variety of problems, as ending up here usually
+          * means the system doesn't have enough buffers to be doing this
+          * well.
+          */
+         if (so->rx_upcall)         /* If call back set... */
+         {
+            u_int ready = so->so_rcv.sb_cc;
+
+            /* If socket has data, try to deliver it to app */
+            if (ready > 0)
+            {
+               tcp_data_upcall(so);
+               if (ready != so->so_rcv.sb_cc)   /* did app accept any data? */
+                  tcp_output(tp);   /* may need to push out a Window update */
+            }
+
+            /* else, no current data... */
+            else
+            {
+               /* if the connection is shutting down, but the application
+                * hasn't been informed, do so now
+                */
+               if ((tp->t_state > TCPS_ESTABLISHED) &&
+                   ((so->so_state & SS_UPCFIN) == 0))
+               {
+                  so->rx_upcall(so, NULL, ESHUTDOWN);
+                  so->so_state |= SS_UPCFIN;
+               }
+            }
+         }
+#endif   /* TCP_ZEROCOPY */
+
+         tp->t_idle++;
+      }
+
+      /* wake up anyone sleeping in a select() involving this socket */
+      sb = &so->so_rcv;
+      if (sb->sb_flags & SB_SEL) 
+      {
+         select_wait = 0;
+#ifndef SOCK_MAP_EVENTS
+         tcp_wakeup ((char *)&select_wait);
+#else
+         tcp_wakeup2 (so->owner);
+#endif
+         sb->sb_flags &= ~SB_SEL;
+      }
+      sb = &so->so_snd;
+      if (sb->sb_flags & SB_SEL) 
+      {
+         select_wait = 0;         
+#ifndef SOCK_MAP_EVENTS
+         tcp_wakeup ((char *)&select_wait);
+#else
+         tcp_wakeup2 (so->owner);
+#endif
+         sb->sb_flags &= ~SB_SEL;
+      }
+
+      /* wake any thread with a timer going for a connection state change */     
+      tcp_wakeup((char*)&so->so_timeo);
+
+tpgone:
+      ;
+   }
+
+   tcp_iss += (unsigned)(TCP_ISSINCR/PR_SLOWHZ);      /* increment iss */
+
+   if (tcp_iss & 0xff000000)
+      tcp_iss = 0L;
+}
+
+
+/* FUNCTION: tcp_canceltimers()
+ *
+ * Cancel all timers for TCP tp.
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_canceltimers(struct tcpcb * tp)
+{
+   int   i;
+
+   for (i = 0; i < TCPT_NTIMERS; i++)
+      tp->t_timer[i] = 0;
+}
+
+unsigned char tcp_backoff [TCP_MAXRXTSHIFT + 1] =
+{ 1, 2, 4, 8, 16, 32, 64, 64, 64, 64, 64, 64, 64 };
+
+
+
+/* FUNCTION: tcp_timers()
+ *
+ * TCP timer processing.
+ * 
+ * PARAM1: struct tcpcb *tp
+ * PARAM2: int timer
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_timers(struct tcpcb * tp, int timer)
+{
+   int   rexmt;
+
+   switch (timer) 
+   {
+
+   /*
+    * 2 MSL timeout in shutdown went off.  If we're closed but
+    * still waiting for peer to close and connection has been idle
+    * too long, or if 2MSL time is up from TIME_WAIT, delete connection
+    * control block.  Otherwise, check again in a bit.
+    */
+   case TCPT_2MSL:
+      if (tp->t_state != TCPS_TIME_WAIT &&
+          tp->t_idle <= tcp_maxidle)
+      {
+         tp->t_timer[TCPT_2MSL] = (short)tcp_keepintvl;
+      }
+      else
+         tp = tcp_close(tp);
+      break;
+
+   /*
+    * Retransmission timer went off.  Message has not
+    * been acked within retransmit interval.  Back off
+    * to a longer retransmit interval and retransmit one segment.
+    */
+   case TCPT_REXMT:
+      TCP_MIB_INC(tcpRetransSegs);     /* keep MIB stats */
+      if (++tp->t_rxtshift > TCP_MAXRXTSHIFT) 
+      {
+         tp->t_rxtshift = TCP_MAXRXTSHIFT;
+         tcpstat.tcps_timeoutdrop++;
+         tp = tcp_drop(tp, ETIMEDOUT);
+         break;
+      }
+      tcpstat.tcps_rexmttimeo++;
+      rexmt = ((tp->t_srtt >> 2) + tp->t_rttvar) >> 1;
+      rexmt *= tcp_backoff[tp->t_rxtshift];
+      TCPT_RANGESET(tp->t_rxtcur, rexmt, TCPTV_MIN, TCPTV_REXMTMAX);
+      tp->t_timer[TCPT_REXMT] = tp->t_rxtcur;
+      /*
+       * If losing, let the lower level know and try for
+       * a better route.  Also, if we backed off this far,
+       * our srtt estimate is probably bogus.  Clobber it
+       * so we'll take the next rtt measurement as our srtt;
+       * move the current srtt into rttvar to keep the current
+       * retransmit times until then. Don't clobber with rtt
+       * if we got it from a timestamp option.
+       */
+      if((tp->t_rxtshift > TCP_MAXRXTSHIFT / 4) &&
+         ((tp->t_flags & TF_TIMESTAMP) == 0))
+      {
+         tp->t_rttvar += (tp->t_srtt >> 2);
+         tp->t_srtt = 0;
+      }
+      tp->snd_nxt = tp->snd_una;
+      /*
+       * If timing a segment in this window, stop the timer.
+       */
+      tp->t_rttick = 0;
+      /*
+       * Close the congestion window down to one segment
+       * (we'll open it by one segment for each ack we get).
+       * Since we probably have a window's worth of unacked
+       * data accumulated, this "slow start" keeps us from
+       * dumping all that data as back-to-back packets (which
+       * might overwhelm an intermediate gateway).
+       *
+       * There are two phases to the opening: Initially we
+       * open by one mss on each ack.  This makes the window
+       * size increase exponentially with time.  If the
+       * window is larger than the path can handle, this
+       * exponential growth results in dropped packet(s)
+       * almost immediately.  To get more time between 
+       * drops but still "push" the network to take advantage
+       * of improving conditions, we switch from exponential
+       * to linear window opening at some threshhold size.
+       * For a threshhold, we use half the current window
+       * size, truncated to a multiple of the mss.
+       *
+       * (the minimum cwnd that will give us exponential
+       * growth is 2 mss.  We don't allow the threshhold
+       * to go below this.)
+       *
+       * Vers 1.9 - Skip slow start if the SO_NOSLOWSTART socket option
+       * is set.
+       */
+      if((tp->t_inpcb->inp_socket->so_options & SO_NOSLOWSTART) == 0)
+      {
+         u_int win = MIN(tp->snd_wnd, tp->snd_cwnd);
+         win = win / 2 / tp->t_maxseg;
+         if (win < 2)
+            win = 2;
+         tp->snd_cwnd = tp->t_maxseg;
+         tp->snd_ssthresh = (u_short)win * tp->t_maxseg;
+      }
+      (void) tcp_output(tp);
+      break;
+
+   /*
+    * Persistance timer into zero window.
+    * Force a byte to be output, if possible.
+    */
+   case TCPT_PERSIST:
+      tcpstat.tcps_persisttimeo++;
+      tcp_setpersist(tp);
+      tp->t_force = 1;
+      (void) tcp_output(tp);
+      tp->t_force = 0;
+      break;
+
+   /*
+    * Keep-alive timer went off; send something
+    * or drop connection if idle for too long.
+    */
+   case TCPT_KEEP:
+      tcpstat.tcps_keeptimeo++;
+      if (tp->t_state < TCPS_ESTABLISHED)
+         goto dropit;
+      if (tp->t_inpcb->inp_socket->so_options & SO_KEEPALIVE &&
+          tp->t_state <= TCPS_CLOSE_WAIT) 
+      {
+         if (tp->t_idle >= tcp_keepidle + tcp_maxidle)
+            goto dropit;
+         /*
+          * Send a packet designed to force a response
+          * if the peer is up and reachable:
+          * either an ACK if the connection is still alive,
+          * or an RST if the peer has closed the connection
+          * due to timeout or reboot.
+          * Using sequence number tp->snd_una-1
+          * causes the transmitted zero-length segment
+          * to lie outside the receive window;
+          * by the protocol spec, this requires the
+          * correspondent TCP to respond.
+          */
+         tcpstat.tcps_keepprobe++;
+
+         /*
+          * The keepalive packet must have nonzero length
+          * to get a 4.2 host to respond.
+          */
+         tcp_respond(tp, tp->t_template, tp->rcv_nxt - 1,
+            tp->snd_una - 1, 0, (struct mbuf *)NULL);
+
+         tp->t_timer[TCPT_KEEP] = (short)tcp_keepintvl;
+      }
+      else
+         tp->t_timer[TCPT_KEEP] = (short)tcp_keepidle;
+      break;
+      dropit:
+      tcpstat.tcps_keepdrops++;
+      tp = tcp_drop (tp, ETIMEDOUT);
+      break;
+   }
+   return tp;
+}
+tcp_seq tcp_iss;
+
+#endif /* INCLUDE_TCP */
+
+
+/* end of file tcp_timr.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.h
new file mode 100644
index 0000000..db0442f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_timr.h
@@ -0,0 +1,147 @@
+/*
+ * FILENAME: tcp_timr.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: TCP
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _TCP_TIMER_H
+#define  _TCP_TIMER_H   1
+
+/*
+ * Definitions of the TCP timers.  These timers are counted
+ * down PR_SLOWHZ times a second.
+ */
+#define     TCPT_NTIMERS   4
+
+#define     TCPT_REXMT     0     /* retransmit */
+#define     TCPT_PERSIST   1     /* retransmit persistance */
+#define     TCPT_KEEP      2     /* keep alive */
+#define     TCPT_2MSL      3     /* 2*msl quiet time timer */
+
+/*
+ * The TCPT_REXMT timer is used to force retransmissions.
+ * The TCP has the TCPT_REXMT timer set whenever segments
+ * have been sent for which ACKs are expected but not yet
+ * received.  If an ACK is received which advances tp->snd_una,
+ * then the retransmit timer is cleared (if there are no more
+ * outstanding segments) or reset to the base value (if there
+ * are more ACKs expected).  Whenever the retransmit timer goes off,
+ * we retransmit one unacknowledged segment, and do a backoff
+ * on the retransmit timer.
+ *
+ * The TCPT_PERSIST timer is used to keep window size information
+ * flowing even if the window goes shut.  If all previous transmissions
+ * have been acknowledged (so that there are no retransmissions in progress),
+ * and the window is too small to bother sending anything, then we start
+ * the TCPT_PERSIST timer.  When it expires, if the window is nonzero,
+ * we go to transmit state.  Otherwise, at intervals send a single byte
+ * into the peer's window to force him to update our window information.
+ * We do this at most as often as TCPT_PERSMIN time intervals,
+ * but no more frequently than the current estimate of round-trip
+ * packet time.  The TCPT_PERSIST timer is cleared whenever we receive
+ * a window update from the peer.
+ *
+ * The TCPT_KEEP timer is used to keep connections alive.  If an
+ * connection is idle (no segments received) for TCPTV_KEEP_INIT amount of time,
+ * but not yet established, then we drop the connection.  Once the connection
+ * is established, if the connection is idle for TCPTV_KEEP_IDLE time
+ * (and keepalives have been enabled on the socket), we begin to probe
+ * the connection.  We force the peer to send us a segment by sending:
+ *   <SEQ=SND.UNA-1><ACK=RCV.NXT><CTL=ACK>
+ * This segment is (deliberately) outside the window, and should elicit
+ * an ack segment in response from the peer.  If, despite the TCPT_KEEP
+ * initiated segments we cannot elicit a response from a peer in TCPT_MAXIDLE
+ * amount of time probing, then we drop the connection.
+ */
+
+#define     TCP_TTL        30    /* default time to live for TCP segs */
+
+/*
+ * Time constants.
+ */
+
+extern   int   TCPTV_MSL;  /* max seg lifetime - NOT a constant! */
+
+#define     TCPTV_SRTTBASE    0     /* base roundtrip time; if 0, no idea yet */
+
+#define  TCPTV_SRTTDFLT    (3*PR_SLOWHZ)        /* assumed RTT if no info */
+#define  TCPTV_PERSMIN     (5*PR_SLOWHZ)        /* retransmit persistance */
+#define  TCPTV_PERSMAX     (60*PR_SLOWHZ)       /* maximum persist interval */
+#define  TCPTV_KEEP_INIT   (75*PR_SLOWHZ)       /* initial connect keep alive */
+#define  TCPTV_KEEP_IDLE   (120*60*PR_SLOWHZ)   /* dflt time before probing */
+#define  TCPTV_KEEPINTVL   (75*PR_SLOWHZ)       /* default probe interval */
+#define  TCPTV_KEEPCNT     8                    /* max probes before drop */
+#define  TCPTV_MIN         (1*PR_SLOWHZ)        /* minimum allowable value */
+#define  TCPTV_REXMTMAX    (64*PR_SLOWHZ)       /* max allowable REXMT value */
+#define  TCP_LINGERTIME    120                  /* linger at most 2 minutes */
+#define  TCP_MAXRXTSHIFT   12                   /* maximum retransmits */
+
+#ifdef   TCPTIMERS
+char *   tcptimers[] =
+{
+   "REXMT",
+   "PERSIST",
+   "KEEP",
+   "2MSL"
+};
+#endif
+
+/*
+ * Force a time value to be in a certain range.
+ */
+#define   TCPT_RANGESET(tv, value, tvmin, tvmax) { \
+   (tv) = (short)(value); \
+   if ((tv) < (tvmin)) \
+      (tv) = (short)(tvmin); \
+   else if ((tv) > (tvmax)) \
+      (tv) = (short)(tvmax); \
+}
+
+extern   int   tcp_keepidle;     /* time before keepalive probes begin */
+extern   int   tcp_keepintvl;    /* time between keepalive probes */
+extern   int   tcp_maxidle;      /* time to drop after starting probes */
+extern   int   tcp_ttl;          /* time to live for TCP segs */
+
+extern   unsigned char  tcp_backoff[TCP_MAXRXTSHIFT   +  1];
+
+#endif   /* _TCP_TIMER_H */
+
+/* end of file tcp_timr.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_usr.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_usr.c
new file mode 100644
index 0000000..2460064
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_usr.c
@@ -0,0 +1,617 @@
+/*
+ * FILENAME: tcp_usr.c
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcp_usrreq(), tcp_attach(), tcp_disconnect(), 
+ * ROUTINES: tcp_usrclosed(),
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "protosw.h"
+#include "in_pcb.h"
+#include "ip.h"
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+
+/*
+ * TCP protocol interface to socket abstraction.
+ */
+extern   char *   tcpstates[];
+struct   tcpcb *  tcp_newtcpcb   __P ((struct inpcb *));
+extern   int   tcp_attach  __P ((struct socket *));
+extern   struct tcpcb * tcp_disconnect __P ((struct tcpcb *));
+extern   struct tcpcb * tcp_usrclosed  __P ((struct tcpcb *));
+extern   struct tcpcb * tcp_timers  __P ((struct tcpcb *, int));
+
+
+
+/* FUNCTION: tcp_usrreq()
+ *
+ * Process a TCP user request for TCP tb.  If this is a send request
+ * then m is the mbuf chain of send data.  If this is a timer expiration
+ * (called from the software clock routine), then timertype tells which timer.
+ * 
+ * PARAM1: struct socket *so
+ * PARAM2: struct mbuf *m
+ * PARAM3: struct mbuf *nam
+ *
+ * RETURNS: 0 if OK, or nonzero socket error code.
+ */
+
+int
+tcp_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+   struct inpcb * inp;
+   struct tcpcb * tp;
+   int   error =  0;
+   int   req;
+
+#ifdef DO_TCPTRACE
+   int   ostate;
+#endif
+
+   req = so->so_req;    /* get request from socket struct */
+   inp = sotoinpcb(so);
+   /*
+    * When a TCP is attached to a socket, then there will be
+    * a (struct inpcb) pointed at by the socket, and this
+    * structure will point at a subsidary (struct tcpcb).
+    */
+   if (inp == 0 && req != PRU_ATTACH) 
+   {
+      return (EINVAL);
+   }
+
+   if (inp)
+      tp = intotcpcb(inp);
+   else  /* inp and tp not set, make sure this is OK: */
+   { 
+      if (req == PRU_ATTACH)
+         tp = NULL;  /* stifle compiler warnings about using unassigned tp*/
+      else
+      {
+         dtrap(); /* programming error? */
+         return EINVAL;
+      }
+   }
+
+   switch (req) 
+   {
+   /*
+    * TCP attaches to socket via PRU_ATTACH, reserving space,
+    * and an internet control block.
+    */
+   case PRU_ATTACH:
+      if (inp) 
+      {
+         error = EISCONN;
+         break;
+      }
+      error = tcp_attach(so);
+      if (error)
+         break;
+      if ((so->so_options & SO_LINGER) && so->so_linger == 0)
+         so->so_linger = TCP_LINGERTIME;
+#ifdef   DO_TCPTRACE
+      SETTP(tp, sototcpcb(so));
+#endif
+      break;
+
+   /*
+    * PRU_DETACH detaches the TCP protocol from the socket.
+    * If the protocol state is non-embryonic, then can't
+    * do this directly: have to initiate a PRU_DISCONNECT,
+    * which may finish later; embryonic TCB's can just
+    * be discarded here.
+    */
+   case PRU_DETACH:
+      if (tp->t_state > TCPS_LISTEN)
+         SETTP(tp, tcp_disconnect(tp));
+      else
+         SETTP(tp, tcp_close(tp));
+      break;
+
+   /*
+    * Give the socket an address.
+    */
+   case PRU_BIND:
+
+      /* bind is quite different for IPv4 and v6, so we use two 
+       * seperate pcbbind routines. so_domain was checked for 
+       * validity way up in t_bind()
+       */
+#ifdef IP_V4
+      if(inp->inp_socket->so_domain == AF_INET)
+      {
+         error = in_pcbbind(inp, nam);
+         break;
+      }
+#endif /* IP_V4 */
+#ifdef IP_V6
+      if(inp->inp_socket->so_domain == AF_INET6)
+      {
+         error = ip6_pcbbind(inp, nam);
+         break;
+      }
+#endif /* IP_V6 */
+      dtrap();    /* not v4 or v6? */
+      error = EINVAL;
+      break;
+   /*
+    * Prepare to accept connections.
+    */
+   case PRU_LISTEN:
+      if (inp->inp_lport == 0)
+         error = in_pcbbind(inp, (struct mbuf *)0);
+      if (error == 0)
+         tp->t_state = TCPS_LISTEN;
+      break;
+
+   /*
+    * Initiate connection to peer.
+    * Create a template for use in transmissions on this connection.
+    * Enter SYN_SENT state, and mark socket as connecting.
+    * Start keep-alive timer, and seed output sequence space.
+    * Send initial segment on connection.
+    */
+   case PRU_CONNECT:
+      if (inp->inp_lport == 0) 
+      {
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      error = in_pcbbind(inp, (struct mbuf *)0);
+#else    /* dual mode */
+      if(so->so_domain == AF_INET)
+         error = in_pcbbind(inp, (struct mbuf *)0);
+      else
+         error = ip6_pcbbind(inp, (struct mbuf *)0);
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+      error = ip6_pcbbind(inp, (struct mbuf *)0);
+#endif   /* end v6 only */
+
+         if (error)
+            break;
+      }
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      error = in_pcbconnect(inp, nam);
+#else    /* dual mode */
+      if(so->so_domain == AF_INET)
+         error = in_pcbconnect(inp, nam);
+      else
+         error = ip6_pcbconnect(inp, nam);
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+      error = ip6_pcbconnect(inp, nam);
+#endif   /* end v6 only */
+
+      if (error)
+         break;
+      tp->t_template = tcp_template(tp);
+      if (tp->t_template == 0) 
+      {
+
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+         in_pcbdisconnect(inp);
+#else    /* dual mode */
+         if(so->so_domain == AF_INET)
+            in_pcbdisconnect(inp);
+         else
+            ip6_pcbdisconnect(inp);
+#endif   /* end dual mode code */
+#else    /* no v4, v6 only */
+         ip6_pcbdisconnect(inp);
+#endif   /* end v6 only */
+
+         error = ENOBUFS;
+         break;
+      }
+
+      soisconnecting(so);
+      tcpstat.tcps_connattempt++;
+      tp->t_state = TCPS_SYN_SENT;
+      tp->t_timer[TCPT_KEEP] = TCPTV_KEEP_INIT;
+      tp->iss = tcp_iss; 
+      tcp_iss += (tcp_seq)(TCP_ISSINCR/2);
+      tcp_sendseqinit(tp);
+      error = tcp_output(tp);
+      if (!error)
+         TCP_MIB_INC(tcpActiveOpens);     /* keep MIB stats */
+      break;
+
+   /*
+    * Create a TCP connection between two sockets.
+    */
+   case PRU_CONNECT2:
+      error = EOPNOTSUPP;
+      break;
+
+   /*
+    * Initiate disconnect from peer.
+    * If connection never passed embryonic stage, just drop;
+    * else if don't need to let data drain, then can just drop anyways,
+    * else have to begin TCP shutdown process: mark socket disconnecting,
+    * drain unread data, state switch to reflect user close, and
+    * send segment (e.g. FIN) to peer.  Socket will be really disconnected
+    * when peer sends FIN and acks ours.
+    *
+    * SHOULD IMPLEMENT LATER PRU_CONNECT VIA REALLOC TCPCB.
+    */
+   case PRU_DISCONNECT:
+      SETTP(tp, tcp_disconnect(tp));
+      break;
+
+   /*
+    * Accept a connection.  Essentially all the work is
+    * done at higher levels; just return the address
+    * of the peer, storing through addr.
+    */
+   case PRU_ACCEPT: 
+   {
+         struct sockaddr_in * sin   =  mtod(nam,   struct sockaddr_in *);
+#ifdef IP_V6
+         struct sockaddr_in6 * sin6 = mtod(nam,   struct sockaddr_in6 *);
+#endif
+
+#ifdef IP_V6
+         if (so->so_domain == AF_INET6)
+         {
+            nam->m_len = sizeof (struct sockaddr_in6);
+            sin6->sin6_port = inp->inp_fport;
+            sin6->sin6_family = AF_INET6;
+            IP6CPY(&sin6->sin6_addr, &inp->ip6_faddr);
+         }
+#endif
+
+#ifdef IP_V4
+         if (so->so_domain == AF_INET)
+         {
+            nam->m_len = sizeof (struct sockaddr_in);
+            sin->sin_family = AF_INET;
+            sin->sin_port = inp->inp_fport;
+            sin->sin_addr = inp->inp_faddr;
+         }
+#endif
+         if ( !(so->so_domain == AF_INET) &&
+              !(so->so_domain == AF_INET6)
+             )
+         {
+            dprintf("*** PRU_ACCEPT bad domain = %d\n", so->so_domain);
+            dtrap();
+         } 
+         TCP_MIB_INC(tcpPassiveOpens);    /* keep MIB stats */
+         break;
+      }
+
+   /*
+    * Mark the connection as being incapable of further output.
+    */
+   case PRU_SHUTDOWN:
+      socantsendmore(so);
+      tp = tcp_usrclosed(tp);
+      if (tp)
+         error = tcp_output(tp);
+      break;
+
+   /*
+    * After a receive, possibly send window update to peer.
+    */
+   case PRU_RCVD:
+      (void) tcp_output(tp);
+      break;
+
+   /*
+    * Do a send by putting data in output queue and updating urgent
+    * marker if URG set.  Possibly send more data.
+    */
+   case PRU_SEND:
+      if (so->so_pcb == NULL)
+      {                    /* Return EPIPE error if socket is not connected */
+         error = EPIPE;
+         break;
+      }
+      sbappend(&so->so_snd, m);
+      error = tcp_output(tp);
+      if (error == ENOBUFS)
+         sbdropend(&so->so_snd,m);  /* Remove data from socket buffer */
+      break;
+
+   /*
+    * Abort the TCP.
+    */
+   case PRU_ABORT:
+      SETTP(tp, tcp_drop(tp, ECONNABORTED));
+      break;
+
+   case PRU_SENSE:
+      /*      ((struct stat *) m)->st_blksize = so->so_snd.sb_hiwat; */
+      dtrap();    /* does this ever happen? */
+      return (0);
+
+   case PRU_RCVOOB:
+      if ((so->so_oobmark == 0 &&
+          (so->so_state & SS_RCVATMARK) == 0) ||
+#ifdef SO_OOBINLINE
+       so->so_options & SO_OOBINLINE ||
+#endif
+       tp->t_oobflags & TCPOOB_HADDATA) 
+       {
+         error = EINVAL;
+         break;
+      }
+      if ((tp->t_oobflags & TCPOOB_HAVEDATA) == 0) 
+      {
+         error = EWOULDBLOCK;
+         break;
+      }
+      m->m_len = 1;
+      *mtod(m, char *) = tp->t_iobc;
+      if ((MBUF2LONG(nam) & MSG_PEEK) == 0)
+         tp->t_oobflags ^= (TCPOOB_HAVEDATA | TCPOOB_HADDATA);
+      break;
+
+   case PRU_SENDOOB:
+      if (so->so_pcb == NULL)
+      {                    /* Return EPIPE error if socket is not connected */
+         error = EPIPE;
+         break;
+      }
+      if (sbspace(&so->so_snd) == 0) 
+      {
+         m_freem(m);
+         error = ENOBUFS;
+         break;
+      }
+      /*
+       * According to RFC961 (Assigned Protocols),
+       * the urgent pointer points to the last octet
+       * of urgent data.  We continue, however,
+       * to consider it to indicate the first octet
+       * of data past the urgent section.
+       * Otherwise, snd_up should be one lower.
+       */
+      sbappend(&so->so_snd, m);
+      tp->snd_up = tp->snd_una + so->so_snd.sb_cc;
+      tp->t_force = 1;
+      error = tcp_output(tp);
+      if (error == ENOBUFS)
+         sbdropend(&so->so_snd,m);  /* Remove data from socket buffer */
+      tp->t_force = 0;
+      break;
+
+   case PRU_SOCKADDR:
+
+   /* sockaddr and peeraddr have to switch based on IP type */
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      in_setsockaddr(inp, nam);
+#else /* dual mode */
+      if(so->so_domain == AF_INET6)
+         ip6_setsockaddr(inp, nam);
+      else
+         in_setsockaddr(inp, nam);
+#endif   /* dual mode */
+#else    /* IP_V6 */
+         ip6_setsockaddr(inp, nam);
+#endif
+      break;         
+
+   case PRU_PEERADDR:
+#ifdef IP_V4
+#ifndef IP_V6  /* v4 only */
+      in_setpeeraddr(inp, nam);
+#else /* dual mode */
+      if(so->so_domain == AF_INET6)
+         ip6_setpeeraddr(inp, nam);
+      else
+         in_setpeeraddr(inp, nam);
+#endif   /* dual mode */
+#else    /* IP_V6 */
+         ip6_setpeeraddr(inp, nam);
+#endif
+      break;
+
+   case PRU_SLOWTIMO:
+      SETTP(tp, tcp_timers(tp, (int)MBUF2LONG(nam)));
+#ifdef DO_TCPTRACE
+      req |= (long)nam << 8;        /* for debug's sake */
+#endif
+      break;
+
+      default:
+      panic("tcp_usrreq");
+   }
+#ifdef DO_TCPTRACE
+   if (tp && (so->so_options & SO_DEBUG))
+      tcp_trace("usrreq: state: %d, tcpcb: %x, req: %d",
+    ostate, tp, req);
+#endif
+   return (error);
+}
+
+
+/* compiled defaults for TCP buffers, may be overwritten at init time */
+
+u_long   tcp_sendspace  =  1024*8;
+u_long   tcp_recvspace  =  1024*8;
+
+
+/* FUNCTION: tcp_attach()
+ *
+ * Attach TCP protocol to socket, allocating
+ * internet protocol control block, tcp control block,
+ * bufer space, and entering LISTEN state if to accept connections.
+ * 
+ * PARAM1: struct socket *so
+ *
+ * RETURNS: 0 if OK, or nonzero error code.
+ */
+
+int
+tcp_attach(struct socket * so)
+{
+   struct tcpcb * tp;
+   struct inpcb * inp;
+   int   error;
+
+   if (so->so_snd.sb_hiwat == 0 || so->so_rcv.sb_hiwat == 0) 
+   {
+      error = soreserve(so, tcp_sendspace, tcp_recvspace);
+      if (error)
+         return (error);
+   }
+   error = in_pcballoc(so, &tcb);
+   if (error)
+      return (error);
+   inp = sotoinpcb(so);
+   tp = tcp_newtcpcb(inp);
+   if (tp == 0) 
+   {
+      int   nofd  =  so->so_state   &  SS_NOFDREF; /* XXX */
+
+      so->so_state &= ~SS_NOFDREF;     /* don't free the socket yet */
+      in_pcbdetach(inp);
+      so->so_state |= nofd;
+      return (ENOBUFS);
+   }
+   tp->t_state = TCPS_CLOSED;
+   return (0);
+}
+
+
+/* FUNCTION: tcp_disconnect()
+ *
+ * Initiate (or continue) disconnect.
+ * If embryonic state, just send reset (once).
+ * If in ``let data drain'' option and linger null, just drop.
+ * Otherwise (hard), mark socket disconnecting and drop
+ * current input data; switch states based on user close, and
+ * send segment to peer (with FIN).
+ *
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_disconnect(struct tcpcb * tp)
+{
+   struct socket *   so =  tp->t_inpcb->inp_socket;
+
+   if (tp->t_state < TCPS_ESTABLISHED)
+      tp = tcp_close(tp);
+   else if ((so->so_options & SO_LINGER) && so->so_linger == 0)
+      tp = tcp_drop(tp, 0);
+   else 
+   {
+      soisdisconnecting(so);
+      sbflush(&so->so_rcv);
+      tp = tcp_usrclosed(tp);
+      if (tp)
+         (void) tcp_output(tp);
+   }
+   return (tp);
+}
+
+
+
+/* FUNCTION: tcp_usrclosed()
+ *
+ * User issued close, and wish to trail through shutdown states:
+ * if never received SYN, just forget it.  If got a SYN from peer,
+ * but haven't sent FIN, then go to FIN_WAIT_1 state to send peer a FIN.
+ * If already got a FIN from peer, then almost done; go to LAST_ACK
+ * state.  In all other cases, have already sent FIN to peer (e.g.
+ * after PRU_SHUTDOWN), and just have to play tedious game waiting
+ * for peer to send FIN or not respond to keep-alives, etc.
+ * We can let the user exit from the close as soon as the FIN is acked.
+ * 
+ * PARAM1: struct tcpcb *tp
+ *
+ * RETURNS: 
+ */
+
+struct tcpcb * 
+tcp_usrclosed(struct tcpcb * tp)
+{
+
+   switch (tp->t_state) 
+   {
+   case TCPS_CLOSED:
+   case TCPS_LISTEN:
+   case TCPS_SYN_SENT:
+      tp->t_state = TCPS_CLOSED;
+      tp = tcp_close(tp);
+      break;
+
+   case TCPS_SYN_RECEIVED:
+   case TCPS_ESTABLISHED:
+      tp->t_state = TCPS_FIN_WAIT_1;
+      break;
+
+   case TCPS_CLOSE_WAIT:
+      tp->t_state = TCPS_LAST_ACK;
+      break;
+   }
+   if (tp && tp->t_state >= TCPS_FIN_WAIT_2)
+      soisdisconnected(tp->t_inpcb->inp_socket);
+   return (tp);
+}
+
+#endif /* INCLUDE_TCP */
+
+
+/* end of file tcp_usr.c */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_var.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_var.h
new file mode 100644
index 0000000..d4cf4ae
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_var.h
@@ -0,0 +1,314 @@
+/*
+ * FILENAME: tcp_var.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: TCP
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _TCP_VAR_H
+#define  _TCP_VAR_H  1
+
+#ifndef  IP_MAXPACKET
+#define  IP_MAXPACKET   (24<<10)    /* maximum packet size */
+#endif
+
+#ifndef  SACK_BLOCKS    /* allow ipport.h to override */
+#define  SACK_BLOCKS    3
+#endif   /*  SACK_BLOCKS */
+
+#ifdef TCP_WIN_SCALE
+extern   u_char   default_wind_scale;  /* default scaling value */
+#undef TCP_WIN_SHORT                   /* force 32-bit windows */
+#endif   /* TCP_WIN_SCALE */
+
+#ifdef TCP_WIN_SHORT
+typedef  u_short  tcp_win;    /* original 1 bit window size */
+#else
+typedef  u_long   tcp_win;    /* scale windows up to 32 bits */
+#endif   /* TCP_WIN_SCALE */
+
+
+/* default window sizes from tcp_usr.c */
+extern   u_long   tcp_sendspace;
+extern   u_long   tcp_recvspace;
+
+/*
+ * Tcp control block, one per tcp; fields:
+ */
+struct tcpcb
+{
+   struct   tcpiphdr *  seg_next;   /* sequencing queue */
+   struct   tcpiphdr *  seg_prev;
+   int      t_state;             /* state of this connection */
+   int      t_timer[TCPT_NTIMERS];  /* tcp timers */
+   int      t_rxtshift;          /* log(2) of rexmt exp. backoff */
+   int      t_rxtcur;            /* current retransmit value */
+   int      t_dupacks;           /* consecutive dup acks recd */
+   u_short  t_maxseg;            /* maximum segment size */
+   char     t_force;             /* 1 if forcing out a byte */
+   u_short  t_flags;             /* mask of the TF_ state bits below */
+   struct tcpiphdr * t_template; /* skeletal packet for transmit */
+   struct inpcb * t_inpcb;       /* back pointer to internet pcb */
+   /*
+    * The following fields are used as in the protocol specification.
+    * See RFC783, Dec. 1981, page 21.
+    */
+   /* send sequence variables */
+   tcp_seq     snd_una;    /* send unacknowledged */
+   tcp_seq     snd_nxt;    /* send next */
+   tcp_seq     snd_up;     /* send urgent pointer */
+   tcp_seq     snd_wl1;    /* window update seg seq number */
+   tcp_seq     snd_wl2;    /* window update seg ack number */
+   tcp_seq     iss;        /* initial send sequence number */
+   tcp_win     snd_wnd;    /* send window */
+   /* receive sequence variables */
+   tcp_win     rcv_wnd;    /* receive window */
+   tcp_seq     rcv_nxt;    /* receive next */
+   tcp_seq     rcv_up;     /* receive urgent pointer */
+   tcp_seq     irs;        /* initial receive sequence number */
+
+   /*
+    * Additional variables for this implementation.
+    */
+   /* receive variables */
+   tcp_seq     rcv_adv;    /* advertised window */
+
+   /* retransmit variables */
+   /* highest sequence number sent used to recognize retransmits */
+   tcp_seq   snd_max;
+
+   /* congestion control (for slow start, source quench, retransmit after loss) */
+   tcp_win  snd_cwnd;      /* congestion-controlled window */
+
+   /* snd_cwnd size threshhold for for slow start exponential to
+    * linear switch
+    */
+   tcp_win  snd_ssthresh;
+
+   /*
+    * transmit timing stuff.
+    * srtt and rttvar are stored as fixed point; for convenience in smoothing,
+    * srtt has 3 bits to the right of the binary point, rttvar has 2.
+    * "Variance" is actually smoothed difference.
+    */
+   int      t_idle;        /* inactivity time */
+   u_long   t_rttick;      /* cticks if timing RTT, else 0 */
+   tcp_seq  t_rtseq;       /* sequence number being timed */
+   int      t_srtt;        /* smoothed round-trip time */
+   int      t_rttvar;      /* variance in round-trip time */
+   tcp_win  max_rcvd;      /* most peer has sent into window */
+   tcp_win  max_sndwnd;    /* largest window peer has offered */
+   /* out-of-band data */
+   char     t_oobflags;    /* have some */
+   char     t_iobc;        /* input character */
+#define     TCPOOB_HAVEDATA   0x01
+#define     TCPOOB_HADDATA    0x02
+
+#ifdef TCP_SACK
+   /* seq numbers in last SACK option sent. sack_seq[0] is last segment
+    * which triggered a SACK.
+    */
+   tcp_seq  sack_seq[SACK_BLOCKS];
+   int      sack_seqct;    /* number of valid sack_seq[] entries */
+
+   /* start & end of current SACK hole(s) to fill with a send. If these are
+    * both zero then there is no SACK hole specified for the send. These
+    * are updated whever a sack header is received and cleared when the
+    * missing segments are send by the rexmit timer.
+    */
+   tcp_seq  sack_hole_start[SACK_BLOCKS];
+   tcp_seq  sack_hole_end[SACK_BLOCKS];
+
+   /* The seq number in our send stream which triggered the last sack
+    * option header from the other side.
+    */
+   tcp_seq  sack_trigger;
+#endif /* TCP_SACK */
+
+#ifdef TCP_WIN_SCALE
+   /* Scales factors if TF_TIMESTAMP bit is set */
+   u_char   snd_wind_scale;      /* RFC-1323 Snd.Wind.Scale (S) */
+   u_char   rcv_wind_scale;      /* RFC-1323 Rcv.Wind.Scale (R) */
+#endif   /* TCP_WIN_SCALE */
+
+#ifdef TCP_TIMESTAMP
+   u_long   ts_recent;           /* RFC-1323 TS.Recent (peer's timestamp) */
+   tcp_seq  last_ack;            /* RFC-1323 Last.ACK (last ack to peer) */
+#endif   /* TCP_TIMESTAMP */
+
+#ifdef DO_DELAY_ACKS
+   long     t_delacktime;        /* Time (in cticks) for delaying ACK */
+   long     t_delackcur;         /* Time left Time for delaying this ACK */
+#endif   /* DO_DELAY_ACKS */
+};
+
+
+/* bit values for tcpcb.t_flags field */
+#define     TF_ACKNOW      0x0001     /* ack peer immediately */
+#define     TF_DELACK      0x0002     /* ack, but try to delay it */
+#define     TF_NODELAY     0x0004     /* don't delay packets to coalesce */
+#define     TF_NOOPT       0x0008     /* don't use tcp options */
+#define     TF_SENTFIN     0x0010     /* have sent FIN */
+#define     TF_SACKOK      0x0020     /* negotiated SACK on this conn.*/
+#define     TF_SACKNOW     0x0040     /* send SACK option packet now */
+#define     TF_WINSCALE    0x0080     /* negotiated a scaled window */
+#define     TF_TIMESTAMP   0x0100     /* negotiated timestamp option */
+#define     TF_SACKREPLY   0x0200     /* send reply to peer's sack options */
+#define     TF_MAXSEG      0x0400     /* user has set max seg */
+
+
+#ifdef TCP_SACK
+int      tcp_buildsack(struct tcpcb * tp, u_char * opt);
+void     tcp_resendsack(u_char * opt, struct tcpcb * tp);
+u_char * tcp_putseq(u_char * cp, tcp_seq seq);
+u_long   tcp_getseq(u_char * cp);
+void     tcp_setsackinfo(struct tcpcb * tp, struct tcpiphdr * ti);
+#endif /* TCP_SACK */
+
+
+#define     intotcpcb(ip)     ((struct tcpcb *)(ip)->inp_ppcb)
+#define     sototcpcb(so)     (intotcpcb(sotoinpcb(so)))
+
+/*
+ * TCP statistics.
+ * Many of these should be kept per connection,
+ * but that's inconvenient at the moment.
+ */
+struct   tcpstat
+{
+   u_long   tcps_connattempt;    /* connections initiated */
+   u_long   tcps_accepts;        /* connections accepted */
+   u_long   tcps_connects;       /* connections established */
+   u_long   tcps_drops;          /* connections dropped */
+   u_long   tcps_conndrops;      /* embryonic connections dropped */
+   u_long   tcps_closed;         /* conn. closed (includes drops) */
+   u_long   tcps_segstimed;      /* segs where we tried to get rtt */
+   u_long   tcps_rttupdated;     /* times we succeeded */
+   u_long   tcps_delack;         /* delayed acks sent */
+   u_long   tcps_timeoutdrop;    /* conn. dropped in rxmt timeout */
+   u_long   tcps_rexmttimeo;     /* retransmit timeouts */
+   u_long   tcps_persisttimeo;   /* persist timeouts */
+   u_long   tcps_keeptimeo;      /* keepalive timeouts */
+   u_long   tcps_keepprobe;      /* keepalive probes sent */
+   u_long   tcps_keepdrops;      /* connections dropped in keepalive */
+
+   u_long   tcps_sndtotal;       /* total packets sent */
+   u_long   tcps_sndpack;        /* data packets sent */
+   u_long   tcps_sndbyte;        /* data bytes sent */
+   u_long   tcps_sndrexmitpack;  /* data packets retransmitted */
+   u_long   tcps_sndrexmitbyte;  /* data bytes retransmitted */
+   u_long   tcps_sndacks;        /* ack-only packets sent */
+   u_long   tcps_sndprobe;       /* window probes sent */
+   u_long   tcps_sndurg;         /* packets sent with URG only */
+   u_long   tcps_sndwinup;       /* window update-only packets sent */
+   u_long   tcps_sndctrl;        /* control (SYN|FIN|RST) packets sent */
+
+   u_long   tcps_rcvtotal;       /* total packets received */
+   u_long   tcps_rcvpack;        /* packets received in sequence */
+   u_long   tcps_rcvbyte;        /* bytes received in sequence */
+   u_long   tcps_rcvbadsum;      /* packets received with ccksum errs */
+   u_long   tcps_rcvbadoff;      /* packets received with bad offset */
+   u_long   tcps_rcvshort;       /* packets received too short */
+   u_long   tcps_rcvduppack;     /* duplicate-only packets received */
+   u_long   tcps_rcvdupbyte;     /* duplicate-only bytes received */
+   u_long   tcps_rcvpartduppack; /* packets with some duplicate data */
+   u_long   tcps_rcvpartdupbyte; /* dup. bytes in part-dup. packets */
+   u_long   tcps_rcvoopack;      /* out-of-order packets received */
+   u_long   tcps_rcvoobyte;      /* out-of-order bytes received */
+   u_long   tcps_rcvpackafterwin;   /* packets with data after window */
+   u_long   tcps_rcvbyteafterwin;   /* bytes rcvd after window */
+   u_long   tcps_rcvafterclose;  /* packets rcvd after "close" */
+   u_long   tcps_rcvwinprobe;    /* rcvd window probe packets */
+   u_long   tcps_rcvdupack;      /* rcvd duplicate acks */
+   u_long   tcps_rcvacktoomuch;  /* rcvd acks for unsent data */
+   u_long   tcps_rcvackpack;     /* rcvd ack packets */
+   u_long   tcps_rcvackbyte;     /* bytes acked by rcvd acks */
+   u_long   tcps_rcvwinupd;      /* rcvd window update packets */
+
+   u_long   tcps_mcopies;        /* m_copy() actual copies */
+   u_long   tcps_mclones;        /* m_copy() clones */
+   u_long   tcps_mcopiedbytes;   /* m_copy() # bytes copied */
+   u_long   tcps_mclonedbytes;   /* m_copy() # bytes cloned */
+
+   u_long   tcps_oprepends;      /* ip_output() prepends of header to data */
+   u_long   tcps_oappends;       /* ip_output() appends of data to header */
+   u_long   tcps_ocopies;        /* ip_output() copies */
+   u_long   tcps_predack;        /* VJ predicted-header acks */
+   u_long   tcps_preddat;        /* VJ predicted-header data packets */
+   u_long   tcps_zioacks;        /* acks recvd during zio sends */
+#ifdef TCP_SACK
+   u_long   tcps_sackconn;       /* connections which negotiated SACK */
+   u_long   tcps_sacksent;       /* SACK option headers sent */
+   u_long   tcps_sackresend;     /* segs resent because of recv SACKs */
+   u_long   tcps_sackrcvd;       /* SACK option headers received */
+   u_long   tcps_sackmaxblk;     /* most SACK blocks in a received option field */
+#endif /* TCP_SACK */
+};
+
+extern   struct inpcb tcb; /* head of queue of active tcpcb's */
+extern   struct tcpstat    tcpstat; /* tcp statistics */
+extern   struct tcpcb *    tcp_timers  __P ((struct tcpcb *, int));
+extern   struct tcpcb *    tcp_disconnect __P ((struct tcpcb *));
+extern   struct tcpcb *    tcp_usrclosed  __P ((struct tcpcb *));
+extern   struct tcpcb *    tcp_close   __P ((struct tcpcb *));
+extern   struct tcpcb *    tcp_drop __P ((struct tcpcb *, int));
+extern   struct tcpcb *    tcp_newtcpcb   __P ((struct inpcb *));
+
+extern   int   tcp_usrreq __P ((struct socket *, struct mbuf *, struct mbuf *));
+extern   int   tcp_output __P ((struct tcpcb *));
+extern   int   tcp_ctloutput __P ((int, struct socket *, int, int, void *));
+extern   void  tcp_input __P ((struct mbuf *, NET ifp));
+extern   void  tcp_slowtimo   __P ((void));
+extern   void  tcp_canceltimers  __P ((struct tcpcb *));
+extern   void  tcp_init __P ((void));
+extern   void  tcp_setpersist __P ((struct tcpcb *));
+extern   void  tcp_notify __P ((struct inpcb *));
+extern   void  tcp_quench __P ((struct inpcb *));
+extern   void  tcp_respond __P ((struct tcpcb *, struct tcpiphdr *, u_long,
+                 u_long, int, struct mbuf *));
+extern   struct tcpiphdr * tcp_template __P ((struct tcpcb *));
+
+/* IPv6 TCP send (to IP layer) routine */
+extern   int   tcp6_send(struct tcpcb * tp, struct mbuf * m,
+                  struct tcphdr *, int totallen, struct   ip_socopts * so_optsPack);
+
+#endif
+
+/* end of file tcp_var.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_zio.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_zio.c
new file mode 100644
index 0000000..7190c40
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcp_zio.c
@@ -0,0 +1,272 @@
+/*
+ * FILENAME: tcp_zio.c
+ *
+ * Copyright 1999- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * tcp_zio.x Socket zero-copy extensions for InterNIche TCP/IP 
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcp_xout(), tcp_pktalloc(), tcp_pktfree(), 
+ * ROUTINES: tcp_data_upcall(),
+ *
+ * PORTABLE: yes
+ */
+
+
+#include "ipport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef TCP_ZEROCOPY  /* whole file can be ifdeffed out */
+
+#include "tcpport.h"
+#include "protosw.h"
+#include "in_pcb.h"
+#include "tcp.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+
+
+/* bitmask for connection state bits which determine if send/recv is OK */
+#define  SO_IO_OK (SS_ISCONNECTED|SS_ISCONNECTING|SS_ISDISCONNECTING)
+
+
+
+/* FUNCTION: tcp_xout()
+ *
+ * tcp_xout(so, pkt) - send a packet (previously allocated by a call 
+ * to tcp_pktalloc()) on a socket. Packet is freed by tcp_xout()if 
+ * OK, not freed if there's an error. Note: pkt->n_prot points to 
+ * data to be sent. The TCP/IP layers will prepend headers to this 
+ * data. Returns 0 if OK or one of the ENP error codes. If the error 
+ * code is ENP_SEND_PENDING then the socket errno is set with a BSD 
+ * error code, but the packet is queued on the socket's send buffer 
+ * and so must not be freed by the application. 
+ *
+ * 
+ * PARAM1: long s
+ * PARAM2: PACKET pkt
+ *
+ * RETURNS: 
+ */
+
+int
+tcp_xout(long s, PACKET pkt)  /* socket & packet to send */
+{
+   struct socket *   so;
+   struct mbuf *  m;
+   int   err;
+
+   so = LONG2SO(s);  /* convert long to socket */
+
+   if (!(so->so_state & SS_INUPCALL))
+   {
+      LOCK_NET_RESOURCE(NET_RESID);
+   }
+
+   if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+   {
+      err = ENP_BAD_STATE;   /* socket is not connected! */
+      goto errexit;
+   }
+
+   /* make sure space in sockbuf is available */
+   if ((so->so_snd.sb_cc + pkt->nb_plen) > so->so_snd.sb_hiwat)
+   {
+      /*
+       * If there's received packets, try processing them. They may ACK some
+       * data in the socket
+       *
+       * NOTE if your target needs to poll a network device
+       * driver to fetch received packets, you can #define POLLED_RX in
+       * ipport.h so that this will let the driver have some cycles 
+       * to fetch the incoming packets and put them on the rcvdq.
+       */
+#ifndef POLLED_RX
+      if (rcvdq.q_len)
+#endif
+      {
+         UNLOCK_NET_RESOURCE(NET_RESID);
+         tk_yield();    /* let the system spin once */
+         LOCK_NET_RESOURCE(NET_RESID);
+      }
+
+      if ((so->so_state & SO_IO_OK) != SS_ISCONNECTED)
+      {
+         err = ENP_BAD_STATE;    /* socket was disconnected in tk_yield() */
+         goto errexit;
+      }
+
+      /* still choked? */
+      if ((so->so_snd.sb_cc + pkt->nb_plen) > so->so_snd.sb_hiwat)
+      {
+         err = ENP_RESOURCE;     /* not allowed, use t_send() */
+         goto errexit;
+      }
+      tcpstat.tcps_zioacks++;   
+   }
+   IN_PROFILER(PF_TCP, PF_ENTRY);      /* measure time in TCP */
+
+   m = m_getnbuf(MT_TXDATA, 0);
+   if (m == (struct mbuf *)NULL)
+   {
+      err = ENP_NOBUFFER;     /* is this reasonable? */
+      goto errexit;
+   }
+
+   m->pkt = pkt;
+   m->m_base = m->m_data = pkt->nb_prot;
+   m->m_memsz = pkt->nb_blen - HDRSLEN;
+   m->m_len = pkt->nb_plen;
+
+   sbappend(&so->so_snd, m);
+   err = tcp_output((struct tcpcb *)(so->so_pcb->inp_ppcb));
+
+   if (!(so->so_state & SS_INUPCALL))
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+   }
+
+   IN_PROFILER(PF_TCP, PF_EXIT);      /* measure time in TCP */
+
+   if (err)
+   {
+      so->so_error =  err;
+      return ENP_SEND_PENDING;
+   }
+   return 0;
+
+errexit:
+   /* return error (as return, not as socket error) */
+   if (!(so->so_state & SS_INUPCALL))
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+   }
+   return err;
+}
+
+
+
+/* FUNCTION: tcp_pktalloc()
+ *
+ * tcp_alloc(int datasize) - request a data buffer for sending tcp 
+ * data to tcp_xout(). Generally datasize must be smaller than the 
+ * tcp data size of smallest device, usually about 1440 bytes. 
+ * Packets allocated with this should be freed either implicitly by a 
+ * successful send call to tcp_xout(), or explicitly by a call to 
+ * tcp_pktfree(). Returns a PACKET structure if OK, else NULL. 
+ *
+ * 
+ * PARAM1: int datasize
+ *
+ * RETURNS: 
+ */
+
+PACKET
+tcp_pktalloc(int datasize)
+{
+   PACKET pkt;
+
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pkt = pk_alloc(datasize + HDRSLEN);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+   if (!pkt)
+      return NULL;
+
+   /* save space for tcp/ip/MAC headers */
+   pkt->nb_prot = pkt->nb_buff + HDRSLEN;
+   pkt->nb_plen = pkt->nb_blen;
+   return pkt;
+}
+
+
+
+/* FUNCTION: tcp_pktfree()
+ *
+ * tcp_pktfree(PACKET p) - free a packet allocated by (presumably) 
+ * tcp_pktalloc(). This is a simple wrapper around pk_free() to lock 
+ * and unlock the free-queue resource. 
+ *
+ * 
+ * PARAM1: PACKET p
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_pktfree(PACKET p)
+{
+   LOCK_NET_RESOURCE(FREEQ_RESID);
+   pk_free(p);
+   UNLOCK_NET_RESOURCE(FREEQ_RESID);
+}
+
+
+/* FUNCTION: tcp_data_upcall()
+ *
+ * tcp_do_upcall(so) - called by tcp_input() when data is received 
+ * for a socket with an upcall handler set. The upcall handler is a 
+ * socket structure member, set by the app via a call to 
+ * setsockopt(SO_CALLBACK, ptr). The upcall routine description is as 
+ * follows: int rx_upcall(struct socket so, PACKET pkt, int error); 
+ * where: so - socket which got data. pkt - pkt containing recieved 
+ * data, or NULL if error. error - 0 if good pkt, else BSD socket 
+ * error The upcall() returns 0 if it accepted data, non-zero if not. 
+ * End of file is signaled to the upcall by ESHUTDOWN error code. If 
+ * LOCK_NET_RESOURCE() is used, the resource is already locked when 
+ * the upcall is called. The upcall will NOT be called from inside a 
+ * CRIT_SECTION macro pairing. 
+ *
+ * 
+ * PARAM1: struct socket * so
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_data_upcall(struct socket * so)
+{
+   struct mbuf *  m;
+   PACKET pkt;
+   int   e;
+
+   /* don't upcall application if there's no data */
+   if (so->so_rcv.sb_cc == 0)
+      return;
+
+   /* don't re-enter the upcall routine */
+   if (so->so_state & SS_INUPCALL)
+      return;
+
+   /* Set flags. SS_UPCALLED is used by select() logic to wake sockets blocked
+   on receive, SS_INUPCALL is the re-entry guard. */
+   so->so_state |= (SS_UPCALLED|SS_INUPCALL);
+
+   m = so->so_rcv.sb_mb;
+   while (m)
+   {
+      /* TCP code left pkt pointers at IP header, need to fix: */
+      pkt = m->pkt;        /* get pkt from mbuf */
+      pkt->nb_prot = m->m_data;
+      pkt->nb_plen = m->m_len;
+
+      /* pass buffer to the app */
+      e = so->rx_upcall(so, (void*)m->pkt, 0);
+
+      if (e)   /* if app returned error, quit */
+         break;
+
+      /* dequeue the mbuf data the application just accepted */      
+      m->pkt = NULL;    /* pkt is now the appp's responsability */
+      sbfree(&so->so_rcv, m);
+      MFREE(m, so->so_rcv.sb_mb);
+      m = so->so_rcv.sb_mb;
+   }
+   so->so_state &= ~SS_INUPCALL;    /* clear re-entry flag */
+   return;
+}
+
+#endif   /* TCP_ZEROCOPY - whole file can be ifdeffed out */
+#endif /* INCLUDE_TCP */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpip.h b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpip.h
new file mode 100644
index 0000000..140378b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpip.h
@@ -0,0 +1,111 @@
+/*
+ * FILENAME: tcpip.h
+ *
+ * Copyright 1997-2007 By InterNiche Technologies, Inc. All rights reserved.
+ *
+ *
+ * MODULE: INET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/*
+ * Copyright (c) 1982, 1986 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. [rescinded 22 July 1999]
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _TCPIP_H
+#define  _TCPIP_H 1
+
+/*
+ * Tcp/Ip-like header, after ip options removed. First part of IPv4
+ * header if overwritten with double linked list links.
+ */
+
+#ifndef IP_V6
+struct ip6_addr;  /* predecl for v4 only builds */
+#endif
+
+struct ipovly
+{
+   struct ipovly *   ih_next;    /* list link */
+   struct ipovly *   ih_prev;    /* list link */
+   u_short  padword;             /* unused - for compilers that don't pad structures */
+   u_short  ih_len;              /* protocol length */
+   struct   in_addr  ih_src;     /* source internet address */
+   struct   in_addr  ih_dst;     /* destination internet address */
+};
+
+struct tcpiphdr
+{
+     struct  ipovly ti_i; /* overlaid ip structure */
+     struct tcphdr  ti_t; /* tcp header */
+};
+
+/* The following definition is somewhat mis-named, since it really
+ * indicates the size of the overlay structure, not the IP head.
+ * on 32 bit IPv4 systems this is usually the same, but on IPv6 or
+ * systems with poiunters which are not 32 bits these sizes may
+ * NOT be the same.
+ */
+#ifdef IP_V6
+#define TCPIPHDRSZ (sizeof (struct tcpiphdr))
+#else
+#define TCPIPHDRSZ 40
+#endif
+
+#define  ti_next  ti_i.ih_next
+#define  ti_prev  ti_i.ih_prev
+#define  ti_x1    ti_i.ih_x1
+#define  ti_pr    ti_i.ih_pr
+#define  ti_len   ti_i.ih_len
+#define  ti_src   ti_i.ih_src
+#define  ti_dst   ti_i.ih_dst
+#define  ti_sport ti_t.th_sport
+#define  ti_dport ti_t.th_dport
+#define  ti_seq   ti_t.th_seq
+#define  ti_ack   ti_t.th_ack
+
+/* For NetPort/InterNiche, omit bitfields and use SET_TH_OFF()
+ * and GET_TH_OFF macros
+ */
+/* #define ti_x2 ti_t.th_x2 #define ti_off ti_t.th_off 
+ */
+
+#define  ti_flags ti_t.th_flags
+#define  ti_win   ti_t.th_win
+#define  ti_sum   ti_t.th_sum
+#define  ti_urp   ti_t.th_urp
+
+#endif   /* _TCPIP_H */
+
+/* end of file tcpip.h */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpport.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpport.c
new file mode 100644
index 0000000..397f0fa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpport.c
@@ -0,0 +1,117 @@
+/*
+ * FILENAME: tcpport.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ * InterNiche TCP layer's per-port routines. The portions of 
+ * the TCP stack which may need to be modified for new ports are 
+ * placed in this file.
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: tcpinit(), tcp_sleep(), tcp_wakeup(),
+ *
+ * PORTABLE: no
+ */
+
+/* Additional Copyrights: */
+/* Portions Copyright 1997 by InterNice Technologies Inc. */
+
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+
+#include "in_pcb.h"
+#include "tcp_timr.h"
+#include "ip.h"   /* the NetPort ip.h */
+
+/* bring to window sizes from tcp_usr.c for overwriting */
+extern   u_long   tcp_sendspace;
+extern   u_long   tcp_recvspace;
+
+
+/* FUNCTION: tcpinit()
+ *
+ * tcpinit() - Set up TCP to run. Code to do port specific setup is 
+ * in this file. This calls code for generic NetPort but setup in 
+ * nptcp.c. This assumes netport IP, packet quques, interfaces, 
+ * et.al., are already up. Returns 0 if OK, else non-zero error code. 
+ *
+ * 
+ * PARAM1: none
+ *
+ * RETURNS: 0 if OK, else one of the ENP_ error codes
+ */
+
+int
+tcpinit(void)
+{
+   int   e; /* error holder */
+
+#ifdef DOS_TSR
+   /* reduce some defaults to conserve TSR resources */
+   tcp_sendspace = (TCP_MSS) * 2;
+   tcp_recvspace = (TCP_MSS) * 2;
+   TCPTV_MSL =    (4 * PR_SLOWHZ);     /* max seg lifetime default */
+#endif
+
+   e = nptcp_init();    /* call the NetPort init in nptcp.c */
+   if (e)
+      return e;
+
+   return 0;   /* good return */
+}
+
+
+
+#ifndef TCPWAKE_ALREADY
+
+/* the tcp process sleep and wakeup system.
+ * these are the superloop versions, for other versions you need 
+ * to define them in you port files and set TCPWAKE_ALREADY.
+ *
+ * A true multitasking version of these is in ..\misclib\netmain.c
+ */
+
+
+void *   last_arg;   /* for debugging */
+
+/* FUNCTION: tcp_sleep()
+ * 
+ * PARAM1: void * timeout
+ *
+ * RETURNS: void
+ */
+
+void
+tcp_sleep(void * timeout)
+{
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   tk_yield(); /* let the system run a bit... */
+   LOCK_NET_RESOURCE(NET_RESID);
+
+   last_arg = timeout;
+}
+
+
+
+/* FUNCTION: tcp_wakeup()
+ * 
+ * PARAM1: void * wake
+ *
+ * RETURNS: void
+ */
+
+void
+tcp_wakeup(void * wake)
+{
+   last_arg = wake;
+}
+#endif   /* TCPWAKE_ALREADY */
+
+#endif /* INCLUDE_TCP */
+
+
+/* end of file tcpport.c */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpsack.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpsack.c
new file mode 100644
index 0000000..950f48f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/tcpsack.c
@@ -0,0 +1,394 @@
+/*
+ * FILENAME: tcpsack.c
+ *
+ * Copyright 2001 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TCP
+ *
+ * ROUTINES: tcp_resendsack(), tcp_buildsack(), 
+ *
+ * PORTABLE: yes
+ */
+
+#include "ipport.h"
+#include "tcpport.h"
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef TCP_SACK      /* Whole file goes away w/o this ifdef */
+
+#include "tcp.h"
+#include "tcp_fsm.h"
+#include "tcp_seq.h"
+#include "tcp_timr.h"
+#include "tcp_var.h"
+#include "tcpip.h"
+#include "in_pcb.h"
+
+
+int tcp_sackComp(tcp_seq * qs1, tcp_seq * qs2);
+
+
+/* FUNCTION: tcp_resendsack()
+ *
+ * Resend data which is indicated to be missing by a SACK option.
+ *
+ * 
+ * PARAM1: char * opt - pointer to received SACK option
+ * PARAM2: struct tcpcb * tp - the connection.
+ *
+ * RETURNS: 
+ */
+
+void
+tcp_resendsack(u_char * opt, struct tcpcb * tp)
+{
+   int      len;        /* length of SACK header as read from header */
+   int      blocks;     /* number of blocks in received header */
+   int      holes;      /* number of SACK holes written to tp */
+   int      i,j;        /* scratch */
+   tcp_seq  start;      /* start sequence of current hole */
+   tcp_seq  end;        /* end sequence of current hole */
+   tcp_seq  nextstart;     /* start of next hole */
+   tcp_seq  sack_trigger;  /* sequnce number which triggered sack header */
+   tcp_seq  seq;           /* scratch sequnce number */
+   tcp_seq	Sacks[SACK_BLOCKS][2];
+
+   tcpstat.tcps_sackrcvd++;
+
+   len = (int)*(opt + 1);     /* length of options fields */
+
+   /* Length should be (n (blocks) * 8) + 2 bytes. Verify this: */
+   if((len & 0x07) != 0x02)
+   {
+      dtrap();    /* Badly formed sack header */
+      return;
+   }
+
+   /* Set up to traverse block list: */
+   opt += 2;                     /* point to block list */
+   blocks = len >> 3;            /* number of blocks */
+
+   if(blocks > (int)tcpstat.tcps_sackmaxblk)
+      tcpstat.tcps_sackmaxblk = blocks;
+
+   /* extract all the sack opts < SACK_BLOCKS */
+   for(i = 0; (i < blocks) && (i < SACK_BLOCKS); i++)
+   {
+      Sacks[i][0] = tcp_getseq(opt + i * 2 * sizeof(tcp_seq));   /* start */
+      Sacks[i][1] = tcp_getseq(opt + i * 2 * sizeof(tcp_seq) + sizeof(tcp_seq));  /* end */
+   }
+   blocks = i;
+ 
+   /* sort */   
+#ifdef INCLUDE_QSORT
+      iniche_qsort((char *)Sacks, blocks, 2 * sizeof(tcp_seq),
+         (int (*) (const void *, const void *))tcp_sackComp);
+#else
+   qsort((char *)Sacks, blocks, 2 * sizeof(tcp_seq),
+    (int (*) (const void *, const void *))tcp_sackComp);
+#endif
+
+   /* |- blocks are now in ascending order */
+
+      IPV6LOG(("+  tcp_resendsack tp->snd_una = %lx, tp->snd_max = %lx\n", tp->snd_una, tp->snd_max));
+
+   for(i = 0; i < blocks; i++)
+       IPV6LOG(("+ %lx, %lx \n", Sacks[i][0], Sacks[i][1]));
+
+
+   /* SACK sends a block list, but what we are interested in is the holes
+    * which precede each block so we can fill these holes. The loop below
+    * finds the holes, in order, and resends the segments to fill them.
+    */
+   start = tp->snd_una;    /* 1st hole starts at last unacked byte */
+   for(i = 0, holes = 0; i < blocks; i++, holes++)
+   {
+      /* end of this block will be start of next hole */
+      nextstart = Sacks[i][1];
+
+	  if (start == Sacks[i][0])
+	  {
+		  start = nextstart;
+		  continue;
+	  }
+
+	  end = Sacks[i][0]; 
+
+      /* Add the SACK hole to the tp. Any old holes info is overwritten. The
+       * Resend timer should end up using the latest SACK info when if
+       * fires instead of the snd_una field.
+       */
+      tp->sack_hole_start[holes] = start;
+      tp->sack_hole_end[holes] = end;
+     
+   IPV6LOG(("+  tcp_resendsack = %lx, %lx \n", start, end));
+	  
+      start = nextstart;
+   }
+
+   /* room for end hole? */
+   if ((holes < SACK_BLOCKS) && (start < tp->snd_max))
+   {
+      /* Add the SACK hole to the tp. Any old holes info is overwritten. The
+       * Resend timer should end up using the latest SACK info when if
+       * fires instead of the snd_una field.
+       */
+      tp->sack_hole_start[holes] = start;
+      tp->sack_hole_end[holes] = tp->snd_max;
+	  holes++;
+
+
+   IPV6LOG(("+  tcp_resendsack end = %lx, %lx \n", start, end));
+
+
+   }
+
+
+   /* if we have identified SACK holes to fill, and the triggering seq is
+    * not the same as the last one we parsed, set resend time to fire ASAP
+    */
+   if((holes) && (tp->sack_trigger != sack_trigger))
+   {
+      tp->t_timer[TCPT_REXMT] = 1;        /* go off on next tcp_slowtmo() */
+      tp->sack_trigger = sack_trigger;    /* save new trigger */
+      tp->t_flags |= TF_SACKREPLY;         /* flag for tcp_input() */
+   }
+
+   /* fill in any remaining holes with zeros */
+   while(holes < SACK_BLOCKS)
+   {
+      tp->sack_hole_start[holes] = 0;
+      tp->sack_hole_end[holes] = 0;
+      holes++;
+   }
+   return;
+}
+
+
+/* FUNCTION: tcp_setsackinfo()
+ *
+ * Called from tcp_input() to store the information to send a sack
+ * request header later on.
+ *
+ * PARAM1: struct tcpcb * tp - connection to SACK
+ * PARAM2: struct tcpiphdr * ti - received segment header
+ *
+ * RETURNS: length of option field, 0 if none was built.
+ */
+
+void
+tcp_setsackinfo(struct tcpcb * tp, struct tcpiphdr * ti)
+{
+   int i;
+
+
+   IPV6LOG(("+  tp->t_flags |= TF_SACKNOW, ti->ti_seq = %lx \n", ti->ti_seq));
+    
+   
+   /* if the received seq is not the last one for which we built 
+    * a sack header, then build new sack data blocks. Code in 
+    * tcpsack.c will use this info to generate sack headers.
+    */
+   if(tp->sack_seq[0] != ti->ti_seq)
+   {
+      /* check for deeper dupes and for new seq being earlier */
+      for(i = 0; i < tp->sack_seqct; i++)
+         if(tp->sack_seq[i] == ti->ti_seq)
+			 return;   /* dupe */
+		 else
+         if(tp->sack_seq[i] > ti->ti_seq)
+		 {
+			/* new seq is earlier than an entry, wipe out! */
+            tp->sack_seq[0] = ti->ti_seq;
+            tp->sack_seqct = 1;
+			return;
+		 }
+	   
+	  /* rotate the older sack sequences toward back of list */
+      for(i = SACK_BLOCKS - 1; i > 0; i--)
+         tp->sack_seq[i] = tp->sack_seq[i - 1];
+
+      if(tp->sack_seqct < SACK_BLOCKS)
+         tp->sack_seqct++;    /* indicate another valid block */
+
+      /* save segment number which triggered SACK at front of list */
+      tp->sack_seq[0] = ti->ti_seq;
+   }
+   tp->t_flags |= TF_SACKNOW; /* set flag to send SACK */
+
+   return;
+}
+
+
+
+
+/* FUNCTION: tcp_buildsack()
+ *
+ * Build a TCP option field for SACK info
+ *
+ * PARAM1: struct tcpcb * tp - connection to SACK
+ * PARAM2: u_char * opt - pointer to option buffer to build.
+ *
+ * RETURNS: length of option field, 0 if none was built.
+ */
+
+int
+tcp_buildsack(struct tcpcb * tp, u_char * opt)
+{
+   int      blocks;  /* number of sack info blocks created */
+   int      len;     /* length of sack data header */
+   int      indx;
+   int      sack_Cnt;
+   tcp_seq  start;   /* scratch */
+   tcp_seq  end;
+   struct tcpiphdr * ti;
+   struct tcpiphdr * next;
+   tcp_seq bag_end[SACK_BLOCKS]; 
+
+   *opt = TCPOPT_SACKDATA;     /* fill in option type */
+
+      IPV6LOG(("+  tcp_buildsack \n"));
+
+
+   for(blocks = 0; blocks < tp->sack_seqct; blocks++)  
+   {
+
+      IPV6LOG(("+  SACK[%d] = %lx \n", blocks, tp->sack_seq[blocks]));
+
+   }
+
+       for(ti = tp->seg_next; ti != (struct tcpiphdr *)tp;
+         ti = (struct tcpiphdr *)(ti->ti_next) )
+      {
+	        IPV6LOG(("+  reasm  = %lx , %lx\n", ti->ti_t.th_seq, ti->ti_t.th_seq + ti->ti_i.ih_len));
+	}
+
+   len = 2;          /* init for just type and len bytes */
+
+   /* build sack block list from reasm queue */
+   for(blocks = 0, sack_Cnt = 0; blocks < tp->sack_seqct; blocks++, sack_Cnt++)
+   {
+      /* Search reasm queue for holes. We will use the info from the
+       * reasm queue to flesh out the hole list entry in the sack 
+       * header. The list is build in tcp_in() when it sets the 
+       * TF_SACKNOW flag which got us here.
+       */
+      for(ti = tp->seg_next; ti != (struct tcpiphdr *)tp;
+         ti = (struct tcpiphdr *)(ti->ti_next) )
+      {
+         if((ti->ti_t.th_seq <= tp->sack_seq[blocks]) &&
+            ((ti->ti_t.th_seq + ti->ti_i.ih_len) > tp->sack_seq[blocks]))
+         {
+            break;   /* found segment containing sack seq. */
+         }
+      }
+      if(ti == (struct tcpiphdr *)tp)
+      {
+          /* 
+		   * sack_seq not in reasm queue, remove it from SACK.
+           */
+		   for (indx = blocks; indx < tp->sack_seqct - 1; indx++)
+		   {			   
+			  /* merge */
+		      tp->sack_seq[indx] = tp->sack_seq[indx + 1];
+              bag_end[indx] = bag_end[indx + 1];
+
+		   	        IPV6LOG(("+ move down 2  = %d, %lx\n", indx));
+		   }
+
+		   /* dec. counts */
+		   tp->sack_seqct--;
+		   if (indx < sack_Cnt)
+			  sack_Cnt--;
+
+         /* Break out of
+          * for(blocks) loop, finish option header, and return.
+          */
+         break;
+      }
+
+      /* find end of sack block by searching reasm queue for
+       * next hole or end of queue.
+       */
+      next = (struct tcpiphdr *)(ti->ti_next);
+      end = ti->ti_seq + ti->ti_len;   /* end of segment */
+      while(next != (struct tcpiphdr *)tp)
+      {
+         /* if this blocks data is adjacent to next, keep looking */
+         if(end >= next->ti_seq)
+         {
+            ti = next;
+            end = ti->ti_seq + ti->ti_len;   /* next end of new segment */
+            next = (struct tcpiphdr *)(ti->ti_next);
+         }
+         else  /* hole follows it, exit search loop */
+         {
+            break;
+         }
+      }
+
+	  /* save the endpoint of this block */
+	  bag_end[blocks] = end;
+   } /* for */
+
+   /* go thru merging blocks with common ends */
+   for(blocks = 0; blocks < sack_Cnt - 1; blocks++)
+	   if (bag_end[blocks] == bag_end[blocks + 1])
+	   {
+           /* move down over dupe, save older seq */
+		   for (indx = blocks; indx < tp->sack_seqct - 1; indx++)
+		   {			   
+			   /* merge */
+		      tp->sack_seq[indx] = tp->sack_seq[indx + 1];
+              bag_end[indx] = bag_end[indx + 1];
+		   	        IPV6LOG(("+ move down   = %d, %lx\n", indx, bag_end[indx]));
+		   }
+
+		   /* dec. counts */
+		   tp->sack_seqct--;
+		   if (blocks < sack_Cnt)
+			  sack_Cnt--;
+	   }
+
+   /* punch out 1 - 3 options */
+   for(blocks = 0; (blocks < sack_Cnt) && (blocks < 3); blocks++)
+   {
+
+	        IPV6LOG(("+  SACK start  = %lx, end = %lx \n", tp->sack_seq[blocks], bag_end[blocks]));
+
+
+      /* set the SACK "hole" data at the correct offsets in opt buffer */
+      tcp_putseq((opt + 2 + (8 * blocks)) , tp->sack_seq[blocks]);
+      tcp_putseq((opt + 6 + (8 * blocks)) , bag_end[blocks]);
+      len += 8;
+   }
+
+   if(len == 2)   /* if no blocks were set return a zero */
+      return 0;
+
+   tcpstat.tcps_sacksent++;
+   *(opt + 1) = (u_char)len;
+   return len;
+}
+
+
+/* FUNCTION: tcp_sackComp()
+ * 
+ * PARAM1: tcp_seq *qs1
+ * PARAM2: tcp_seq *qs2
+ *
+ * RETURNS: 
+ */
+
+int
+tcp_sackComp(tcp_seq * qs1, tcp_seq * qs2)
+{
+   return (int)(*qs1 - *qs2);
+}
+
+#endif   /* TCP_SACK */
+#endif /* INCLUDE_TCP */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tcp/udpsock.c b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/udpsock.c
new file mode 100644
index 0000000..c4becfc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tcp/udpsock.c
@@ -0,0 +1,560 @@
+/*
+ * FILENAME: udpsock.c
+ *
+ * Copyright  2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: INET
+ *
+ * ROUTINES: udp_lookup(), udp_soinput(), udp_usrreq()
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+/* udpsock.c 
+ * Portions Copyright 1997 by InterNiche Technologies Inc. All rights 
+ * reserved. Glue layer lightweight UDP API and UDP under sockets. 
+ * This maps the sockets calls - sendto(), recvfrom(), etc - to the 
+ * lightweight API for sockets purists. 
+ */
+
+
+#include "ipport.h"
+#include "tcpport.h" /* UDP_SOCKETS is defined (or not) in here */
+
+#ifdef INCLUDE_TCP  /* include/exclude whole file at compile time */
+#ifdef UDP_SOCKETS   /* can ifdef away whole file */
+
+#include "mbuf.h"    /* sockets/BSDish includes */
+#include "socket.h"
+#include "sockvar.h"
+#include "sockcall.h"
+#include "protosw.h"
+
+#include "udp.h"  /* from NetPort INET directory */
+
+/* list of actice UDP "connections" */
+extern   UDPCONN  firstudp;
+
+#ifdef IP_V4
+int udp4_sockbind(struct socket *so, struct mbuf *nam, int req);
+int udp4_socksend(struct socket *so, struct mbuf *m, struct mbuf *nam);
+int udp4_sockaddr(struct socket *so, struct mbuf *nam , int req);
+#endif
+
+#ifdef IP_V6
+extern int udp6_sockbind(struct socket *so, struct mbuf *nam, int req );
+extern int udp6_socksend(struct socket *so, struct mbuf *m, struct mbuf *nam);
+extern int udp6_sockaddr(struct socket *so, struct mbuf *nam , int req);
+extern int udp6_soinput(PACKET pkt, void *so_ptr );
+#endif
+
+/* FUNCTION: udp_lookup()
+ * 
+ * udp_lookup() - Return socket's matching UDP connection in 
+ * ..\inet\udp's internal list. Return NULL if not found. 
+ *
+ * PARAM1: struct socket * so
+ *
+ * RETURNS: 
+ */
+
+UDPCONN
+udp_lookup(struct socket * so)
+{
+   UDPCONN tmp;
+
+   for (tmp = firstudp; tmp; tmp = tmp->u_next)
+      if (tmp->u_data == (void*)so)
+      return (tmp);
+
+   return NULL;   /* didn't find it */
+}
+
+/* FUNCTION: udp_soinput()
+ *
+ * UDP upcall handler for UDP connections mapped to sockets. Return 0 
+ * if OK, else nonzero error code. 
+ *
+ * 
+ * PARAM1: PACKET pkt
+ * PARAM2: void * so_ptr
+ *
+ * RETURNS: 
+ */
+
+int
+udp_soinput(PACKET pkt, void * so_ptr)
+{
+   struct mbuf *  m_in;    /* packet/data mbuf */
+   struct socket *   so =  (struct  socket *)so_ptr;
+   struct sockaddr_in   sin;
+   struct udp *   udpp;
+
+   LOCK_NET_RESOURCE(NET_RESID); 
+
+   /* make sure we're not flooding input buffers */
+   if ((so->so_rcv.sb_cc + pkt->nb_plen) >= so->so_rcv.sb_hiwat)
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   /* alloc mbuf for received data */
+   m_in = m_getnbuf(MT_RXDATA, 0);
+   if (!m_in)
+   {
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   /* set data mbuf to point to start of UDP data */
+   m_in->pkt = pkt;
+   m_in->m_data = pkt->nb_prot;
+   m_in->m_len = pkt->nb_plen;
+   m_in->m_base = pkt->nb_buff;
+   m_in->m_memsz = pkt->nb_blen;
+
+   /* fill in net address info for pass to socket append()ers */
+   sin.sin_addr.s_addr = pkt->fhost;
+   udpp = (struct udp *)(pkt->nb_prot - sizeof(struct udp));
+   sin.sin_port = htons(udpp->ud_srcp);
+   sin.sin_family = AF_INET;
+
+   /* attempt to append address information to mbuf */
+   if (!sbappendaddr(&so->so_rcv, (struct sockaddr *)&sin, m_in))
+   {
+      /* set the pkt field in the mbuf to NULL so m_free() below wont 
+       * free the packet buffer, because that is left to the 
+       */
+      m_in->pkt = NULL;
+      /* free only the mbuf itself */
+      m_free(m_in);
+      /* return error condition so caller can free the packet buffer */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      return ENOBUFS;
+   }
+
+   tcp_wakeup(&so->so_rcv);   /* wake anyone waiting for this */
+
+   sorwakeup(so);    /* wake up selects too */
+
+   UNLOCK_NET_RESOURCE(NET_RESID);
+   return 0;
+}
+
+
+/* FUNCTION: udp_usrreq()
+ *
+ * proto_tab's usr_req call function for UDP protocol. Maps the 
+ * sockets requests into NetPort lightweight UDP interface. Returns 0 
+ * if no error, negative "NP" error if lower layers fail, postive 
+ * error from nptcp.h if TCP/Sockets fails. 
+ *
+ * 
+ * PARAM1: struct socket * so
+ * PARAM2: struct mbuf * m
+ * PARAM3: struct mbuf * nam
+ *
+ * RETURNS: 
+ */
+
+int
+udp_usrreq(struct socket * so, 
+   struct mbuf *  m,
+   struct mbuf *  nam)
+{
+   UDPCONN udpconn = (UDPCONN)NULL;
+   int   req;
+
+   req = so->so_req;    /* get request from socket struct */
+
+   switch (req) 
+   {
+   case PRU_ATTACH:
+      /* fake small windows so sockets asks us to move data */
+      so->so_rcv.sb_hiwat = so->so_snd.sb_hiwat = udp_maxalloc();
+
+#ifdef IP_V4
+      /* make a NetPort UDP connection */
+      /* unlock the net resource; UDP will immediatly re-lock it */
+      if (so->so_domain  == AF_INET){
+        UNLOCK_NET_RESOURCE(NET_RESID);
+        udpconn = udp_open(0L, 0, udp_socket(), udp_soinput, so);
+        LOCK_NET_RESOURCE(NET_RESID);
+      }
+#endif
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        UNLOCK_NET_RESOURCE(NET_RESID);
+        udpconn = udp6_open(0L, 0, udp_socket(), udp6_soinput, so);
+        LOCK_NET_RESOURCE(NET_RESID);
+      }
+#endif
+      if (!udpconn)
+         return(EINVAL);
+      return 0;
+   case PRU_DETACH:
+      /* delete the NetPort UDP connection */
+      udpconn = udp_lookup(so);
+      if (!udpconn)
+         return(EINVAL);
+      /* unlock the net resource; UDP will immediatly re-lock it */
+      UNLOCK_NET_RESOURCE(NET_RESID);
+      udp_close(udpconn);
+      LOCK_NET_RESOURCE(NET_RESID);
+      return 0;
+   case PRU_CONNECT:
+      /* Install foreign port for UDP, making a virtual connection */
+      /* fall to shared bind logic */
+   case PRU_BIND:
+      /* do bind parameters lookups and tests */
+      if (nam == NULL)
+         return(EINVAL);
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+        return udp4_sockbind(so, nam, req );
+      }
+#endif
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_sockbind(so, nam, req);
+      }
+#endif
+      dtrap();   /* invalid address */
+      return EINVAL;
+   case PRU_SEND:
+      /* do parameter lookups and tests */
+      if (!m)  /* no data passed? */
+         return(EINVAL);
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+        return udp4_socksend(so, m, nam );
+      }
+#endif
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_socksend(so, m, nam);
+      }
+#endif
+      dtrap();   /* invalid address */
+      return EINVAL;
+
+   case PRU_SOCKADDR:
+      /* fall through to share PRU_PEERADDR prefix */
+   case PRU_PEERADDR:
+      if (nam == NULL)
+         return(EINVAL);
+#ifdef IP_V4
+      if (so->so_domain == AF_INET){
+        return udp4_sockaddr(so, nam, req );
+      }
+#endif
+#ifdef IP_V6
+      if (so->so_domain == AF_INET6){
+        return udp6_sockaddr(so, nam, req);
+      }
+#endif
+      dtrap();   /* invalid address */
+      return EINVAL;
+
+   case PRU_DISCONNECT:
+   case PRU_RCVD:
+      dtrap();
+      return 0;
+   case PRU_LISTEN:     /* don't support these for UDP */
+   case PRU_ACCEPT:
+   default:
+      return EOPNOTSUPP;
+   }
+}
+
+#ifdef IP_V4
+int udp4_sockbind(struct socket *so, struct mbuf *nam, int req ) 
+{
+  struct sockaddr_in * sin;
+  UDPCONN udpconn;
+  UDPCONN udptmp;
+  u_short  fport;   /* foreign port (local byte order) */
+  u_short  lport;   /* local port (local byte order) */
+  ip_addr fhost; /* host to send to/recv from (network byte order) */
+  ip_addr lhost; /* local IP address to bind to (network byte order) */
+  NET ifp;
+
+  sin = mtod(nam, struct sockaddr_in *);
+  if (sin == NULL)
+    return(EINVAL);
+  if (nam->m_len != sizeof (*sin))
+    return(EINVAL);
+  udpconn = udp_lookup(so);
+  if (!udpconn)
+     return(EINVAL);
+  if (req == PRU_BIND)
+  {
+    /* bind the socket to a local UDP port,
+     * and optionally a local interface IP address.
+     *
+     * if the caller-supplied port is 0, try to get
+     * the port from the UDP endpoint, or pick a new
+     * unique port; else, use the caller-supplied
+     * port
+     */
+    if (sin->sin_port == 0)
+    {
+      if (udpconn->u_lport != 0)
+        lport = udpconn->u_lport;
+      else
+        lport = udp_socket();
+    }
+    else
+    {
+      lport = ntohs(sin->sin_port);
+    }
+    /* if the caller-supplied address is INADDR_ANY,
+     * don't bind to a specific address; else, 
+     * make sure the caller-supplied address is
+     * an interface IP address and if so, bind to that
+     */
+    if (sin->sin_addr.s_addr == INADDR_ANY)
+    {
+      lhost = 0L;
+    }
+    else
+    {
+      lhost = sin->sin_addr.s_addr;
+#ifndef UDP_SKIP_LCL_ADDR_CHECK
+      /* verify that lhost is a local interface address */
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+        if (ifp->n_ipaddr == lhost)
+          break;
+      if (ifp == NULL)
+        return(EADDRNOTAVAIL);
+#endif /* UDP_SKIP_LCL_ADDR_CHECK */
+    }
+
+    /* make sure we're not about to collide with an
+     * existing binding
+     */
+    if (!(so->so_options & SO_REUSEADDR))
+      for (udptmp = firstudp; udptmp; udptmp = udptmp->u_next)
+        if ((udptmp->u_lport == lport) && (udptmp != udpconn))
+          return(EADDRINUSE);
+    /* bind the UDP endpoint */
+    udpconn->u_lport = lport;
+    udpconn->u_lhost = lhost;
+  }
+  else /* PRU_CONNECT */
+  {
+    /* connect the socket to a remote IP address and
+     * UDP port.
+     */
+    fport = ntohs(sin->sin_port);
+    /* if the caller-supplied address is INADDR_ANY,
+     * use the wildcard address; else, use the caller-
+     * supplied address
+     */
+    if (sin->sin_addr.s_addr == INADDR_ANY)
+      fhost = 0L;
+    else
+      fhost = sin->sin_addr.s_addr;
+    /* prepare to bind the socket to the appropriate 
+     * local interface address for the to-be-connected 
+     * peer
+     */
+    lhost = ip_mymach(fhost);
+    if (lhost == 0)
+      return(ENETUNREACH);
+    /* if the socket hasn't been bound to a local
+     * port yet, do so now
+     */
+    lport = udpconn->u_lport;
+    if (lport == 0)
+      lport = udp_socket();
+    /* bind and connect the UDP endpoint */
+    udpconn->u_lhost = lhost;
+    udpconn->u_lport = lport;
+    udpconn->u_fhost = fhost;
+    udpconn->u_fport = fport;
+    /* mark the socket as connected */
+    so->so_state &= ~(SS_ISCONNECTING|SS_ISDISCONNECTING);
+    so->so_state |= SS_ISCONNECTED;
+    /* since socket was in listen state, packets may be queued */
+    sbflush(&so->so_rcv);   /* dump these now */
+  }
+  return 0;
+}
+
+int udp4_socksend(struct socket *so, struct mbuf *m, 
+		struct mbuf *nam ) 
+{
+  int e;
+  struct sockaddr_in * sin;
+  UDPCONN udpconn;
+  u_short  fport;   /* foreign port (local byte order) */
+  ip_addr fhost;
+  PACKET pkt;
+#ifdef MULTI_HOMED
+  NET ifp;
+#endif
+
+  udpconn = udp_lookup(so);
+  if (!udpconn)
+  {
+    m_free(m);
+    /* may be bogus socket, but more likely the connection may 
+       have closed due to ICMP dest unreachable from other side. */
+    return(ECONNREFUSED);
+  }
+
+  if (nam == NULL)  /* no sendto() info passed, must be send() */
+  { 
+    if (so->so_state & SS_ISCONNECTED)
+    {
+      fport = udpconn->u_fport;
+      fhost = udpconn->u_fhost;
+    }
+    else
+      return (EINVAL);
+  }
+  else if(nam->m_len != sizeof (*sin))
+  {
+    dtrap();
+    return (EINVAL);
+  }
+  else
+  {
+    sin = mtod(nam, struct sockaddr_in *);
+    fhost = sin->sin_addr.s_addr;
+    /* use caller's fport if specified, ours may be a wildcard */
+    if (sin->sin_port)   /* caller gets to change fport on the fly */
+      fport = ntohs(sin->sin_port);
+    else  /* use port already set in UDP connection */
+    {
+      if (udpconn->u_fport == 0) /* don't send to port 0 */
+        return (EINVAL);
+      fport = udpconn->u_fport;
+    }
+  }
+  /* fhost and fport are now set */
+
+  /* since our pkt->nb_buff size is tied to max packet size, we 
+   * assume our UDP datagrams are always in one mbuf and that the 
+   * mbuf 
+   */
+  if (m->m_len > (unsigned)udp_maxalloc()) /* but check anyway:*/
+  {
+    dtrap(); /* should never happen */
+    return EMSGSIZE;  /* try to recover */
+  }
+  pkt = udp_alloc(m->m_len, 0);    /* get a NetPort buffer for send */
+  if (!pkt)
+  {
+    m_free(m);
+    return ENOBUFS;   /* report buffer shortages */
+  }
+  MEMCPY(pkt->nb_prot, m->m_data, m->m_len);
+  pkt->nb_plen = m->m_len;
+  /* finished with mbuf, free it now */
+  m_free(m);
+  pkt->fhost = fhost;
+
+  /* if we're being asked to send to 255.255.255.255 (a local-net
+     * broadcast), figure out which interface to send the broadcast
+     * on, based on the IP address that the socket is bound to: if
+     * it has been bound to an interface address, we should send the
+     * broadcast on that interface; else, we look for the first
+     * interface that can support broadcasts and is up; if we still
+     * don't have an interface we look for the first interface that
+     * is up; if (after all that) we don't have an interface then we
+     * fail with error EADDRNOTAVAIL; and finally, if we're built
+     * for a single-homed configuration where there's only one
+     * interface, we might as well use it, so we do.  
+   */
+  if (fhost == 0xffffffff)
+  {
+#ifdef MULTI_HOMED
+    if (udpconn->u_lhost != 0L)
+    {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+        if (ifp->n_ipaddr == udpconn->u_lhost)
+          break;
+    }
+    else {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+        if ((ifp->n_flags & NF_BCAST) &&
+          (ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+           break;
+    }
+    if (ifp == NULL)
+    {
+      for (ifp = (NET)(netlist.q_head); ifp; ifp = ifp->n_next)
+        if ((ifp->n_mib) && (ifp->n_mib->ifAdminStatus == NI_UP))
+          break;
+      if (ifp == NULL)
+        return(EADDRNOTAVAIL);
+    }
+    pkt->net = ifp;
+#else  /* single-homed */
+    pkt->net = (NET)(netlist.q_head);
+#endif /* MULTI_HOMED */
+  }
+
+#ifdef IP_MULTICAST
+
+  /* If the socket has an IP moptions structure for multicast options,
+   * place a pointer to this structure in the PACKET structure.
+   */
+  if (so->inp_moptions)
+     pkt->imo = so->inp_moptions;
+
+#endif   /* IP_MULTICAST */
+
+   /* have we set options? */
+   if (so->so_optsPack)
+	   pkt->soxopts = so->so_optsPack; /* yup - copy to pkt */
+
+  /* unlock the net resource; UDP will immediately re-lock it */
+  UNLOCK_NET_RESOURCE(NET_RESID);
+  e = udp_send(fport, udpconn->u_lport, pkt);
+  LOCK_NET_RESOURCE(NET_RESID);
+  if (e < 0) 
+     return(e);
+  return 0;
+}
+
+int udp4_sockaddr(struct socket *so, struct mbuf *nam , int req)
+{
+  struct sockaddr_in * sin;
+  UDPCONN udpconn;
+
+  sin = mtod(nam, struct sockaddr_in *);
+  if (sin == NULL)
+     return(EINVAL);
+  udpconn = udp_lookup(so);
+  if (!udpconn)
+     return(EINVAL);
+  nam->m_len = sizeof(*sin);
+  if (req == PRU_SOCKADDR)
+  {
+     sin->sin_family = AF_INET;
+     sin->sin_port = htons(udpconn->u_lport);
+     sin->sin_addr.s_addr = udpconn->u_lhost;
+  }
+  else /* PRU_PEERADDR */
+  {
+    sin->sin_family = AF_INET;
+    sin->sin_port = htons(udpconn->u_fport);
+    sin->sin_addr.s_addr = udpconn->u_fhost;
+  }
+  return 0;
+}
+
+#endif      /* IP_V4 */
+
+#endif   /* UDP_SOCKETS */
+#endif /* INCLUDE_TCP */
+
+/* end of file sockudp.c */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telerr.c b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telerr.c
new file mode 100644
index 0000000..0b2b29e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telerr.c
@@ -0,0 +1,90 @@
+/*
+ * FILENAME: telerr.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ * ROUTINES: tel_err_str()
+ *
+ * PORTABLE: yes
+ */
+
+
+/* File telerr.c Implementation file for Telnet Server This file 
+ * contains description for all the errors. A call to tel_err_str() 
+ * returns the description of the error. 
+ */
+#include "telnet.h"
+
+#ifdef TELNET_SVR       /* Then include this source file */
+#ifdef TEL_SHOW_MSG
+
+
+struct ErrorInfo  {
+    int   err;
+    char *   str;
+};
+
+struct ErrorInfo  tel_err[]=  {
+     {  TRUE                          , "success"                               },
+     {  FALSE                         , "failure"                               },
+     {  TELBASE                       , "Base value for telnet errors"          },
+     {  TEL_NEW_ALLOC_ERR             , "Cant alloc mem for new conn"           },
+     {  TEL_NEW_CANT_ALLOC_RECV_BUF   , "Cant alloc mem for receive buffer"     },
+     {  TEL_NEW_CANT_ALLOC_SEND_BUF   , "Cant alloc mem for send buffer"        },
+     {  TEL_NEW_CANT_ADD_TO_Q         , "Cant add new connectionto queue"       },
+     {  TEL_NEW_CANT_ALLOC_OPTIONS    , "Cant alloc mem for options"            },
+     {  TEL_NEW_CANT_ALLOC_CMD_BUF    , "Cant alloc mem for command bufer"      },
+     {  TEL_DELQ_Q_EMPTY              , "Q is empty. Entry cant be removed"     },
+     {  TEL_DELQ_CONN_NOT_FOUND       , "Conn not found in Q. Cant remove"      },
+     {  TEL_DEL_NULL_ARGUMENT         , "Cant delete a NULL pointer"            },
+     {  TEL_INIT_CANT_OPEN_SOCKET     , "Cant open socket for Telnet Server"    },
+     {  TEL_INIT_BIND_FAILED          , "Cant bind socket"                      },
+     {  TEL_INIT_LISTEN_FAILED        , "listen() failed on socket"             },
+     {  TEL_INIT_ASYNCSELECT          , "ASyncSelect() failed on socket"        },
+     {  TEL_INIT_RCVBUF               , "RCVBUF size for socket cant be set"    },
+     {  TEL_INIT_SNDBUF               , "SNDBUF size for socket cant be set"    },
+     {  TEL_INIT_STARTUP_ERR          , "WSAStartup() failed"                   },
+     {  TEL_CHECK_NO_LISTEN_SOCK      , "Cant find listen socket"               },
+     {  TEL_PROC_TCP_CLOSED           , "Underlying TCP conn was closed"        },
+     {  TEL_PROC_FATAL_ERROR          , "Fatal error while doing TCP read()"    },
+     {  TEL_PROC_LOGGED_OUT           , "User had logged out of telnet sess"    },
+     {  TEL_PROC_AUTH_FAILED          , "User could not login(invalid password)"},
+     {  TEL_PROC_TIMED_OUT            , "Connection timed out."                 },
+     {  TEL_SP_BAD_SIZE               , "Cant do BS,ESC processing:bad ip size" },
+     {  TEL_N_CMD_UNKNOWN             , "Received unknown Telnet command"       },
+     {  TEL_N_NO_IAC                  , "Telnet cmd doesn't start with IAC"     },
+     {  TEL_N_NO_SB                   , "No SB found in sub-negotiation cmd"    },
+     {  TEL_N_NO_SE                   , "No SE found in sub-negotiation cmd"    },
+};
+
+/* FUNCTION: tel_err_str()
+ * 
+ * 
+ *
+ * PARAM1: int value - Error value (IN)
+ *
+ * RETURNS: Pointer to string , if error value is recognised, 
+ * otherwise NULL.
+ */
+
+char * tel_err_str(int value)
+{
+   int   i;
+   int   errCount=sizeof(tel_err)/sizeof(struct ErrorInfo);
+
+   for ( i=0 ; i < errCount ; i++ )
+   {
+      if ( tel_err[i].err == value )
+         return tel_err[i].str ;
+   }
+   return NULL;
+}
+
+#endif   /*  TEL_SHOW_MSG */
+#endif   /* TELNET_SVR - Whole file can be ifdeffed out */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telmenu.c
new file mode 100644
index 0000000..0e4685e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telmenu.c
@@ -0,0 +1,239 @@
+/*
+ * FILENAME: telmenu.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ * ROUTINES: tel_menu_init(), tel_show_opt(), tel_show_stats(), 
+ * ROUTINES: tel_close_sess(), 
+ *
+ * PORTABLE: yes
+ */
+
+
+/* File telmenu.c Implementation of menus for TELNET 
+ * 1/4/99 - Edited menu text -MPG- 
+ */
+#include "telnet.h"
+
+#ifdef TELNET_SVR       /* Then include this source file */
+#ifdef TEL_MENU
+
+#include "menu.h"
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+struct menu_op telmenu[]   =  {
+   { "telnet",    stooges,       "TELNET server menu" } ,
+   { "tshow",     tel_show_opt,  "show the options values for all sessions" } ,
+   { "tstats",    tel_show_stats,"show the statistics of all TELNET sessions" } ,
+   { "logout",    NULL,          "logout of the TELNET session" } ,
+   { "exit",      NULL,          "logout of the TELNET session" } ,
+   { NULL } ,
+};
+
+/* Macro to show TRUE=1 and FALSE=0 in output */
+#define  TEL_BOOL(X)    (  (X==TRUE)   ?  1  :  0  )
+
+
+/* FUNCTION: tel_menu_init()
+ * 
+ * Install the telnet menus into system menus.
+ *
+ * PARAM1: none()
+ *
+ * RETURNS: SUCCESS or error number.
+ */
+
+int
+tel_menu_init()
+{
+   install_menu(telmenu);
+   install_version("telnet3.1");
+   return SUCCESS ;
+}
+
+
+/* FUNCTION: tel_show_opt()
+ * 
+ * Show the values of options of all telnet sessions.
+ *
+ * PARAM1: void * pio - Pointer to GenericIO structure (IN)
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int tel_show_opt(void * pio)
+{
+   TEL_CONN tconn;
+
+   int   opt_cnt  =  sizeof(struct  TelOptionList)/sizeof(struct  TelnetOption)  ;
+   TEL_OPT opt;
+   int   i;
+   int   cnt=0;
+
+   tconn=telq;
+
+   if ( tconn == NULL )
+   {
+      ns_printf(pio,"There are no open telnet sessions.\n");
+   }
+   else
+   {
+      ns_printf(pio,"Showing OPTION values for each telnet session....\n");
+   }
+
+   while ( tconn != NULL )
+   {
+      cnt++;
+      ns_printf(pio,"\nSession %d : Socket is %lu......\n",cnt,tconn->sock);
+
+      opt = (TEL_OPT)tconn->options ;
+      for (i=0 ; i < opt_cnt ; ++i )
+      {
+         ns_printf(pio,"[%d]%s: configurable=%d\n", 
+          opt->option, 
+          TEL_OPT_STR(opt->option), 
+          TEL_BOOL(opt->config));
+         ns_printf(pio,"   For Local Session:value=%d, req sent=%d, nego=%d\n",
+          TEL_BOOL(opt->l_value), 
+          TEL_BOOL(opt->l_req_sent), 
+          TEL_BOOL(opt->l_negotiate) );
+         ns_printf(pio,"   For Remote Session:value=%d, req sent=%d, nego=%d\n",
+          TEL_BOOL(opt->r_value), 
+          TEL_BOOL(opt->r_req_sent), 
+          TEL_BOOL(opt->r_negotiate) );
+         opt++;
+      }
+
+      tconn=tconn->next;
+   }
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tel_show_stats()
+ * 
+ * Show telnet statistics. 
+ *
+ * PARAM1: void * pio - Pointer to GenericIO structure (IN)
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int tel_show_stats(void * pio)
+{
+   TEL_CONN tconn;
+
+   int   cnt=0;
+
+   ns_printf(pio,"Total connections opened = %ld\n",tel_stats.conn_opened);
+   ns_printf(pio,"Total connections closed = %ld\n",tel_stats.conn_closed);
+
+   tconn=telq;
+
+   while ( tconn != NULL )
+   {
+      cnt++;
+      ns_printf(pio,"\nTelnet Session %d: Showing statistics for socket %lu.\n",
+       cnt,tconn->sock);
+
+      ns_printf(pio,"Bytes rcvd=%ld, Cmds rcvd = %ld\n",
+       tconn->stats.rcvd, tconn->stats.cmds );
+
+      tconn=tconn->next;
+   }
+
+   ns_printf(pio,"Number of ongoing telnet sessions = %d.\n",cnt);
+
+   ns_printf(pio,"Global variables (current value,default value)\n");
+   ns_printf(pio,"Recv buf size: %d,%d\n", tglob.tel_recv_buf_size, 
+      TEL_RECV_BUF_SIZE );
+   ns_printf(pio,"Send buf size: %d,%d\n", tglob.tel_send_buf_size, 
+      TEL_SEND_BUF_SIZE );
+   ns_printf(pio,"Listen port: %d,%d\n", tglob.tel_port, 
+      TELNET_PORT       );
+   ns_printf(pio,"Max login tries allowed: %d,%d\n", tglob.tel_max_login_tries,
+      TEL_MAX_LOGIN_TRIES);
+   ns_printf(pio,"Idle timeout: %d,%d\n", tglob.tel_idle_time,
+      TEL_IDLE_TIME  );
+
+   return SUCCESS;
+
+}
+
+#ifdef CLOSE_SESS    /* Right now tel_close_sess doesn't work */
+
+
+/* FUNCTION: tel_close_sess()
+ * 
+ * Show telnet statistics. 
+ *
+ * PARAM1: void * pio - Pointer to GenericIO structure (IN)
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int tel_close_sess(void * pio)
+{
+   TEL_CONN tconn;
+   char *   cp;
+   int   cnt=0;
+   int   sess_num;
+
+   cp = nextarg(pio->inbuf);  /* see if user put parm on cmd line */
+   if (!*cp)
+   {
+      ns_printf(pio,"usage:tclose <Telnet Session Number>\n");
+      ns_printf(pio,"Telnet Session Number can be found from tstats command.\n");
+      ns_printf(pio,"Eg:tclose 1\n");
+      return -1;
+   }
+
+   sess_num=atoi(cp);
+   if ( sess_num <= 0 )
+   {
+      ns_printf(pio,"Invalid session number %d.\n",sess_num);
+      return -1;
+   }
+
+   tconn=telq;
+
+   while ( tconn != NULL )
+   {
+      cnt++;
+      if ( cnt == sess_num )
+      {
+         /* Close this telnet session */
+         if ( pio == &(tconn->tel_io) )
+         {
+            ns_printf(pio,"Session can't close itself. Use logout.\n");
+            return -1;
+         }
+         else
+         {
+            tel_delete(tconn);
+            ns_printf(pio,"Telnet session %d successfully closed.\n",cnt);
+            return SUCCESS;
+         }
+      }
+      else
+      {
+         tconn=tconn->next;
+      }
+   }
+
+   ns_printf(pio,"Could not find session %d.\n",sess_num);
+
+   return -1;
+}
+#endif
+
+#endif   /* TEL_MENU */
+#endif   /* TELNET_SVR */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.c b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.c
new file mode 100644
index 0000000..4c99993
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.c
@@ -0,0 +1,1145 @@
+/*
+ * FILENAME: t.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: MISCLIB
+ *
+ * ROUTINES: tel_new(), tel_addq(), tel_delq(), 
+ * ROUTINES: tel_delete(), tel_loop(), tel_tcp_send(), tel_tcp_recv(), 
+ * ROUTINES: tel_process(), tel_conn_from_sock(), tel_read(), 
+ * ROUTINES: tel_sp_char_proc(), tel_proc_cmd(
+ *
+ * PORTABLE: yes
+ */
+
+
+/* File telnet.c Implementation file for Telnet Server 
+ */
+#include "telnet.h"
+
+#ifdef TELNET_SVR       /* Then include this source file */
+
+static int max_telnet_conn = MAX_TELNET_SESS;
+static int telnet_connect  = 0;  /* Current count of telnet connections */
+
+TEL_CONN telq=NULL;     /* Start of queue of open connections */
+/* last_error is used to store the last error for functions
+ * that return meaningful values (eg funcs returning char *)    
+ */
+long     last_error;    
+
+struct TelStatistics tel_stats;
+
+#ifdef TEL_USERAUTH
+char *tel_login_prompt  = "\nlogin: ";
+char *tel_passwd_prompt = "password: ";
+#endif
+
+/* extra space in cmdbuf kept, to account for increased space due to
+ * potential CRLF substitution */
+#define TEL_CRLFPAD    10 
+
+
+/* FUNCTION: tel_new()
+ * 
+ * Allocate memory for a new TelnetConn object 
+ * A TelnetConn object holds all information about a
+ * telnet connection. Also it adds the new object to the
+ * open connection queue (telq).
+ *
+ * PARAM1: None
+ *
+ * RETURNS: A pointer to the NEW telnet object. NULL if error.
+ */
+
+TEL_CONN tel_new()
+{
+   TEL_CONN tconn;
+
+   /* Increment the count of connections and compare against configured max */
+   telnet_connect++;
+   if (max_telnet_conn > 0)
+   {
+      if (telnet_connect > max_telnet_conn)
+      {                   /* connection max exceeded */
+         telnet_connect--;/* decrement count of connections */ 
+         return NULL;     /* do not accept connection */
+      }
+   }
+
+   tconn=(TEL_CONN)TEL_ALLOC(sizeof(struct TelnetConn));
+   if (tconn == NULL)
+   {
+      last_error = TEL_NEW_ALLOC_ERR;
+      return NULL;
+   }
+
+   tconn->cmdbuf = (char *) TEL_ALLOC(tglob.tel_recv_buf_size);
+   if (tconn->cmdbuf == NULL)
+   {
+      /* Could not Allocate space for receive buffer */
+      TEL_FREE(tconn);
+      last_error = TEL_NEW_CANT_ALLOC_CMD_BUF;
+      return NULL;
+   }
+
+   tconn->txbuf = (char *) TEL_ALLOC(tglob.tel_send_buf_size);
+   if (tconn->txbuf == NULL)
+   {
+      /* Could not Allocate space for send(transmit) buffer */
+      TEL_FREE(tconn->cmdbuf);
+      TEL_FREE(tconn);
+      last_error = TEL_NEW_CANT_ALLOC_SEND_BUF;
+      return NULL;
+   }
+
+   tconn->rxbuf = (char *) TEL_ALLOC(tglob.tel_recv_buf_size);
+   if (tconn->rxbuf == NULL)
+   {
+      /* Could not Allocate space for receive buffer */
+      TEL_FREE(tconn->txbuf);
+      TEL_FREE(tconn->cmdbuf);
+      TEL_FREE(tconn);
+      last_error = TEL_NEW_CANT_ALLOC_RECV_BUF;
+      return NULL;
+   }
+
+   tconn->options = (struct TelOptionList *) 
+   TEL_ALLOC(sizeof(struct TelOptionList));
+   if (tconn->options == NULL)
+   {
+      /* Could not Allocate space for options */
+      TEL_FREE(tconn->rxbuf);
+      TEL_FREE(tconn->txbuf);
+      TEL_FREE(tconn->cmdbuf);
+      TEL_FREE(tconn);
+      last_error = TEL_NEW_CANT_ALLOC_OPTIONS;
+      return NULL;
+   }
+   else
+   {
+      /* Copy the default options and their values */
+      *(tconn->options)=tel_opt_list;
+   }
+
+   if (tel_addq(tconn) != SUCCESS)
+   {
+      /* Could not add to queue ! Wierd */
+      TEL_FREE(tconn->options);
+      TEL_FREE(tconn->rxbuf);
+      TEL_FREE(tconn->txbuf);
+      TEL_FREE(tconn->cmdbuf);
+      TEL_FREE(tconn);
+      last_error = TEL_NEW_CANT_ADD_TO_Q;
+      return NULL;
+   }
+
+   /* If user authentication is enabled, then login, password need to be
+      verified */
+#ifdef TEL_USERAUTH
+   tconn->state = TEL_LOGIN;
+   tconn->prompt= tel_login_prompt;
+   tconn->tries = 0;
+#else
+   tconn->state = TEL_NORMAL;
+   tconn->prompt= prompt;
+#endif
+
+   tel_start_timer(&tconn->curr_tick);
+   tconn->cmdsize=0;
+   tconn->txsize=0;
+   tconn->rxsize=0;
+   tconn->inserver=0;
+
+   tel_stats.conn_opened++;
+
+   return tconn;
+}
+
+/* FUNCTION: tel_connection()
+ *
+ * Handle accept of a new telnet connection - basicly a wrapper
+ * for tel_new();
+ *
+ * PARAM1: temp_sock - new socket returned from accept
+ *
+ *
+ * RETURNS: Pointer to new connection if OK, else NULL (e.g. alloc failed)
+ */
+
+TEL_CONN
+tel_connection(SOCKTYPE temp_sock)
+{
+   TEL_CONN temp_conn;
+
+   temp_conn = tel_new();
+   if (temp_conn != NULL)
+   {
+      temp_conn->sock = temp_sock;
+      temp_conn->tel_io.id = (long)temp_sock;
+      temp_conn->tel_io.out = tel_tcp_send;
+      /* mark the connection in use, so that it isn't 
+         processed by the tk_yield() inside ns_printf(). */
+      temp_conn->inserver = 1;
+      tel_start_nego(temp_conn);
+      ns_printf(&temp_conn->tel_io,
+                "Welcome to InterNiche Telnet Server 1.0\n");
+      if (temp_conn->state == TEL_NORMAL)
+      {
+         ns_printf(&temp_conn->tel_io,
+                   "Please type ? or help for more information.\n");
+      }
+      ns_printf(&temp_conn->tel_io,"\n%s",temp_conn->prompt);
+   }
+   else
+   {
+      dprintf("Error #%ld opening new connection.\n",last_error);
+      return NULL;
+   }
+
+   /* It's safe to allow processing now. */
+   temp_conn->inserver = 0;
+
+   return temp_conn;
+}
+
+
+/* FUNCTION: tel_addq()
+ * 
+ * Add a telnet object to global queue (of open connections)
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to object to be added
+ *
+ * REMARKS: No Allocation is done. Only the queue is updated
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int tel_addq(TEL_CONN tconn)
+{
+   if (telq == NULL)     
+   {
+      /* Queue is empty */
+      telq=tconn;
+      telq->next = NULL;
+   }
+   else
+   {
+      /* Add it to the front of the queue */
+      tconn->next = telq;
+      telq=tconn;
+   }
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tel_delq()
+ * 
+ * Delete a telnet object from the  global queue 
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to object to be deleted
+ *
+ * REMARKS: No Free (deallocation) is done. Only the queue is updated
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int tel_delq(TEL_CONN tconn)
+{
+   TEL_CONN temp_conn;
+   TEL_CONN prev_conn;
+   int retval = TEL_DELQ_CONN_NOT_FOUND;     /* assume no connection */
+
+   /* Check for empty queue */
+   if (telq == (TEL_CONN)NULL)
+   {     
+      retval = TEL_DELQ_Q_EMPTY;
+   }
+   else
+   {
+      /* Find the item and delete it */
+      prev_conn = (TEL_CONN)NULL;
+      temp_conn = telq;
+
+      LOCK_NET_RESOURCE(NET_RESID);
+
+      while (temp_conn != (TEL_CONN)NULL) 
+      {
+         if (temp_conn == tconn)
+         {
+            if (prev_conn == (TEL_CONN)NULL)    /* first entry in list */
+               telq = tconn->next;
+            else                                /* middle of list */
+               prev_conn->next = tconn->next;
+            retval = SUCCESS;    /* found a connection */
+            break;
+         }
+
+         /* advance to next list entry */
+         prev_conn = temp_conn;
+         temp_conn = temp_conn->next;
+      }
+   
+      UNLOCK_NET_RESOURCE(NET_RESID);
+   }
+
+   return retval;
+}
+
+
+
+/* FUNCTION: tel_delete()
+ * 
+ * Free memory for a the TelnetConn object 
+ * A TelnetConn object holds all information about a
+ * telnet connection. This function frees all memory that
+ * was allocated for the object. It also deletes the object
+ * the telq (Queue of open telnet connections)
+ * Also close the underlying TCP connection.
+ *
+ * PARAM1: TEL_CONN tconn - A pointer to the telnet object. 
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int tel_delete(TEL_CONN tconn)
+{
+   int   retValue=SUCCESS;
+
+   if (tconn == NULL)
+      return TEL_DEL_NULL_ARGUMENT;
+
+   /* Remove the connection from the queue */
+   retValue = tel_delq(tconn);
+   if (retValue != SUCCESS)
+   {
+      dtrap();
+   }
+
+   /* Close the underlying TCP connection */
+   sys_closesocket(tconn->sock);
+
+   if (tconn->options)
+   {
+      TEL_FREE(tconn->options);
+      tconn->options=NULL;
+   }
+
+   if (tconn->rxbuf)
+   {
+      TEL_FREE(tconn->rxbuf);
+      tconn->rxbuf=NULL;
+   }
+   else
+   {
+      /* What ? Receive buffer has already been freed !! */
+      dtrap();
+   }
+
+   if (tconn->txbuf)
+   {
+      TEL_FREE(tconn->txbuf);
+      tconn->txbuf=NULL;
+   }
+   else
+   {
+      /* What ? Send buffer has already been freed !! */
+      dtrap();
+   }
+
+   if (tconn->cmdbuf)
+   {
+      TEL_FREE(tconn->cmdbuf);
+      tconn->cmdbuf=NULL;
+   }
+   else
+   {
+      /* What ? Command buffer has already been freed !! */
+      dtrap();
+   }
+
+   TEL_FREE(tconn);
+
+   telnet_connect--;   /* Decrement count of connections */
+   tel_stats.conn_closed++;
+
+   return retValue;
+}
+
+
+/* FUNCTION: tel_loop()
+ * 
+ * Check the status of each open telnet connection.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: SUCCESS , else error number
+ */
+
+int tel_loop()
+{
+   TEL_CONN temp_conn;
+   TEL_CONN next_conn;
+   int e;
+
+   temp_conn=telq;
+
+   while (temp_conn != NULL)
+   {
+      next_conn = temp_conn->next;
+      if (temp_conn->inserver == 0)    /* is this connection blocked? */
+      {
+         temp_conn->inserver++;    /* set re-entry prevention flag */
+         e=tel_process(temp_conn);
+         /* There are some cases when the connection would have been
+          * deleted 
+          */
+         if ((e == TEL_PROC_TIMED_OUT)   || (e ==  TEL_PROC_TCP_CLOSED)  ||
+             (e == TEL_PROC_FATAL_ERROR) || (e ==  TEL_PROC_AUTH_FAILED) ||
+             (e == TEL_PROC_LOGGED_OUT))
+         {
+            ; /* Do nothing. Memory pointed by temp_conn is already freed */
+         }
+         else
+            temp_conn->inserver--;    /* reset re-entry prevention flag */
+      }
+      temp_conn=next_conn;
+   }
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tel_tcp_send()
+ * 
+ * Function which outputs the contents to telnet session.
+ * This function can be used with the GenericIO structure.
+ *
+ * PARAM1: long s - Index to the output device. In this case, it
+ * will be the socket number of telnet session.(IN)
+ * PARAM2: char *buf - Buffer of data (IN)
+ * PARAM3: int len - Length of data in buffer (IN)
+ * Length is needed so that we can output hex data also.
+ *
+ * REMARKS: This function provides the translation from \n to \r\n.
+ * Telnet needs CRLF sequence. So all occurances of LF
+ * are replaced by CRLF. 
+ * Algorithm   : The algorithm used for this is as follows.
+ * 1. Scan the input string and find out the position
+ * of all occurances of LF. And the count (num_of_newln).
+ * 2. Let us assume that the string is now having 
+ * num_of_newln+1 blocks, each separated by LF.
+ * 3. The size of new string would be oldlength+num_of_newln.
+ * 4. Move the last block to end of new string.
+ * 5. Insert a CR just before the first char of this block.
+ * 6. Now move the second last block to its new position.
+ * Insert a CR just before its first char.
+ * 7. Repeat for all blocks.
+ * We could have used a simpler (to code) algorithm where
+ * we move the whole block everytime we find LF and insert
+ * a CR. A typical case of time-space tradeoff.
+ *
+ * RETURNS: Number of bytes sent.
+ */
+
+int
+tel_tcp_send(long desc, char *buf, int len)
+{
+   int   i;
+   int   newln_pos[TEL_MAX_NEWLN];
+   int   num_of_newln=0;
+   int   start,end;
+   TEL_CONN t;
+   SOCKTYPE s;
+
+   s = (SOCKTYPE)desc;     /* set socket from genericIO descriptor */
+
+   t = tel_conn_from_sock(s);
+
+   if (t == NULL)
+   {
+      /* Whoops !! No telnet connection corresponding to this sock ? 
+       * One scenario when this happens for InterNiche stack is as 
+       * follows. 
+       * 1. User Opens TELNET session. 
+       * 2. User does TCP Echo (via TCP Echo Client) 
+       * 3. User closes TELNET connection (w/o closing TCP Echo Client conn) 
+       * 4. After a while tcp_echo_poll() realises that the TCP 
+       *    Echo Client has been idle for a long time and so it 
+       *    a. Sends a message informtion intention to clean up TCPEchoClient. 
+       *       (Thats when tel_tcp_send() hits this dtrap()) 
+       *    b. Closes the TCP Echo Client. 
+       */
+      dtrap();
+      return 0;
+   }
+   else
+   {
+      if (t->options->binary.l_value == FALSE)
+      {
+         /* Substitue LF by CRLF if we have NON-BINARY mode for peer */
+         /* First find all newline(LF) posltions */
+
+         for (i=0; i < len; i++)
+         {
+            if (buf[i] == '\n')
+            {
+               if (num_of_newln >= TEL_MAX_NEWLN)
+               {
+                  /* There are more that TEL_MAX_NEWLN newline chars in this str*/
+                  dtrap();
+               }
+               else
+               {
+                  newln_pos[num_of_newln++]=i;        
+               }
+            }
+         }
+
+         /* Now insert CR before all LF */
+         end=len;
+         for (i= num_of_newln-1; i >= 0; i--)
+         {
+            start=newln_pos[i];
+            MEMMOVE(buf+start+i+1,buf+start, end-start);
+            buf[start+i]  ='\r';   /* insert CR */
+            buf[start+i+1]='\n';   /* insert LF. Somehow MEMMOVE was making it 0 */
+            end=start;
+         }
+         buf[len+num_of_newln] = 0;   /* NULL terminate */
+      }
+
+      /* Some data will be written. Update the timer */
+      tel_start_timer(&(t->curr_tick));
+
+      return sys_send(s, buf, len+num_of_newln, 0);
+   }
+}
+
+
+/* FUNCTION: tel_tcp_recv()
+ * 
+ * Function which inputs from a telnet session.
+ * This function can be used with the GenericIO structure.
+ *
+ * PARAM1: SOCKTYPE s
+ * 1. Socket form which input is to be done (IN)
+ *
+ * RETURNS: The first byte that has been received.
+ * Value -1 is returned if some error occured.
+ * Value 0 is returned if nothing was received
+ * TELNET uses GenericIO mechanism to do I/O. Normal TELNET input 
+ * (for example commands, options) are done in TEL_NORMAL state.
+ * So, when a command is received in TEL_NORMAL state, TELNET calls
+ * the corresponding routines to execute it. The routine uses ns_printf
+ * to send output to the TELNET client. Sometimes, this routine might
+ * need prompting from the TELNET clinet (For example, while displaying
+ * a big buffer, prompting of "Press any key to continue" can be done
+ * after showing a screenfull of information). So in such a case, 
+ * via the GenericIO structure, tel_tcp_recv() would be called, and
+ * the connection will be in TEL_PROC_CMD state. When the command
+ * processing is done, the connection should return to TEL_NORMAL state.
+ * This is achieved by doing the state change when the user has pressed
+ * a key.
+ * In "Press any key to continue" kindof scenarios, this works perfectly.
+ * There can be some other scenarios. Lets take UDP ECHO (udecho command).
+ * The user type the command to do 10 echos. The corresponding routine
+ * starts processing, and keeps checking for user input. If any key has
+ * been pressed, it stops doing UDP ECHOs. So this routine would periodically
+ * call tel_tcp_recv() to see is any data has arrived. For cases like
+ * 10 echos, the user may not press any key. So, we should have some
+ * mechanism to return to normal state. This is done by doing a check
+ * when the execution of the routine is over. It is made sure that TELNET
+ * connection is returns to normal state.
+ */
+
+int
+tel_tcp_recv(long iodesc)
+{
+   TEL_CONN t;
+   SOCKTYPE s = (SOCKET)iodesc;
+
+   t = tel_conn_from_sock(s);
+   if (t == NULL)
+   {
+      /* Whoops !! No telnet connection corresponding to this sock ? */
+      dtrap();
+      return -1;
+   }
+   else
+   {
+      t->state = TEL_PROC_CMD;
+      if (t->rxsize == 0 )
+      {
+         if (tel_read(t) != SUCCESS)
+            return -1;     /* some fatal error on this connection */
+      }
+
+      if (t->rxsize == 0 )
+      {
+         return 0;   /* No data was received */
+      }
+      else
+      {
+         t->state = TEL_NORMAL;
+         t->rxsize= 0;  /* discard all new input */
+         return ((int)(t->rxbuf[0]));  /* Return the first char received */
+      }
+   }
+}
+
+
+/* FUNCTION: tel_process()
+ * 
+ * Do the processing for the open connection. If some date
+ * needs to be sent, send it, and if some data has been
+ * received, process it.
+ * 1. If the lower TCP layer has closed, then cleanup up
+ * the telnet session.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection
+ *
+ * RETURNS: SUCCESS , else error number
+ * later-if connection is open for a long time, close the connection
+ */
+
+int tel_process(TEL_CONN tconn)
+{
+
+   int   e;
+   int   old_cmdsize;
+
+#ifdef  TEL_SESS_TIMEOUT
+   /* Terminate the session if it has been idling around long enough */
+   if (tel_check_timeout(tconn->curr_tick,(u_long)tglob.tel_idle_time) == SUCCESS)
+   {
+      tel_delete(tconn);
+      return TEL_PROC_TIMED_OUT;
+   }
+#endif
+
+   if (tconn->state == TEL_PROC_CMD)
+      return SUCCESS;
+
+   if ((e=tel_read(tconn)) != SUCCESS)
+      return e;
+
+   if (tconn->rxsize > 0)
+   {
+      /* Process telnet commands and strip them out of rxbuf */
+      if (tel_parse(tconn) != SUCCESS)
+      {
+         /* Error in parsing the received string */
+         dtrap();
+      }
+
+      /* Now see if we have some new DATA */
+      if (tconn->rxsize > 0)
+      {
+         /* Add it to cmdbuf, so that it contains all the unprocessed
+            command till now */
+
+         /* do a sanity check, so that cmdbuf is not exceeded */
+         if (tconn->cmdsize+tconn->rxsize > 
+            (tglob.tel_recv_buf_size- TEL_CRLFPAD))
+         {
+            /* received more data than can be held by cmdbuf.
+             * ignore it for now - in future/later, increase sizeof cmdbuf
+             */
+
+            /* find out how much of received data can be used. Keep
+             * extra buffer of 10 for CRLF processing in tel_sp_char_proc() */
+            int tobeused=tglob.tel_recv_buf_size - tconn->cmdsize - TEL_CRLFPAD;
+
+            old_cmdsize=tconn->cmdsize;
+            if (tobeused > 0)
+            {
+               MEMCPY(tconn->cmdbuf+tconn->cmdsize,tconn->rxbuf,tobeused);
+               tconn->cmdsize+=tobeused;
+            }
+            tconn->rxsize=0;
+            /* put CRLF at the end of it, so that cmdline is processed */
+            tconn->cmdbuf[tglob.tel_recv_buf_size-TEL_CRLFPAD-2]= TEL_CR;
+            tconn->cmdbuf[tglob.tel_recv_buf_size-TEL_CRLFPAD-1]= TEL_LF;
+            ns_printf(&tconn->tel_io, "Cmd too big (%d bytes), truncating \n",
+               tglob.tel_recv_buf_size-TEL_CRLFPAD);
+         }
+         else
+         {
+            old_cmdsize=tconn->cmdsize;
+            MEMCPY(tconn->cmdbuf+tconn->cmdsize,tconn->rxbuf,tconn->rxsize);
+            tconn->cmdsize+=tconn->rxsize;
+            tconn->rxsize=0;
+         }
+
+         /* Do processing for special characters like BackSpace, ESC
+            and prepare output buffer to be ECHOed */
+         tel_sp_char_proc(tconn->cmdbuf,&(tconn->cmdsize),
+          tconn->txbuf,&(tconn->txsize), old_cmdsize);
+
+         if (tconn->options->echo.l_value == TRUE)
+         {
+            if (tconn->txsize >  0 && tconn->state !=TEL_PASSWORD)
+            {
+               /* Echo the data back to the terminal */
+               sys_send(tconn->sock,tconn->txbuf,tconn->txsize,0);
+            }
+         }
+         tconn->txsize=0;     /* Discard the output buffer */
+
+         /* Check if we have received a CRLF. If yes, then we have 
+          * received a whole command and can execute it. Do this only 
+          * if the received buffer has atleast 2 bytes 
+          */
+         if (tconn->cmdsize > 1)
+         {
+            /* Do menu-command processing in non-binary mode */
+
+            if (tconn->options->binary.r_value == FALSE)
+            {
+               /* process all commands in cmdbuf*/
+               e=tel_proc_cmd(tconn);
+               if (e != SUCCESS) 
+               {
+                  /* This can happen if the user logs out */
+                  return e;
+               }
+            }
+            else
+            {
+               /* Binary mode . Do nothing */
+               tconn->cmdsize=0;
+            }
+         }
+         else
+         {
+            /* Do nothing. */
+         }
+
+      }
+      else
+      {
+         /* do some sanity checking */
+         if (tconn->rxsize < 0)
+         {
+            dtrap();
+            tconn->rxsize=0;
+         }
+      }
+
+   }
+   else
+   {
+      /* do some sanity checking */
+      if (tconn->rxsize < 0)
+      {
+         dtrap();
+         tconn->rxsize=0;
+      }
+   }
+
+   return SUCCESS;   /* OK return */
+}
+
+
+/* FUNCTION: tel_conn_from_sock()
+ * 
+ * Find the TelnetConn for a particular socket.
+ *
+ * PARAM1: SOCKET s - Socket  (IN)
+ *
+ * RETURNS: Pointer to TelnetConn structure or NULL
+ */
+
+TEL_CONN 
+tel_conn_from_sock(SOCKET s)
+{
+   TEL_CONN t;
+
+   for (t = telq; t != (TEL_CONN)NULL; t = t->next)
+   {
+      if (t->sock == s)
+         break;
+   }
+
+   return t;
+}
+
+
+
+/* FUNCTION: tel_read()
+ * 
+ * Read data from a open telnet session
+ *
+ * PARAM1: TEL_CONN t - Pointer to telnet connection (IN)
+ *
+ * RETURNS: 1. SUCCESS if 0 or more bytes received
+ * 2. error code if the underlying TCP connection was broken
+ */
+
+int
+tel_read(TEL_CONN t)
+{
+
+   int   readval,e;
+   readval= sys_recv(t->sock, t->rxbuf, tglob.tel_recv_buf_size , 0);
+
+   if (readval == 0)   
+   {
+      /* The underlying TCP connection has been closed */
+      tel_delete(t);
+      return TEL_PROC_TCP_CLOSED;
+   }
+   else if (readval < 0) /* error on socket? */
+   {
+      e = sys_errno(t->sock);
+      if (e == SYS_EWOULDBLOCK)
+      {
+         readval=0;
+      }
+      else
+      {
+         /*
+          * Altera Niche Stack Nios port modification:
+          * Change %p to %d to fix build warning
+          */
+         dprintf("telnet: error %d on socket %d\n", e, (unsigned int)t->sock);
+         tel_delete(t);    /* thats the end of this connection... */
+         return TEL_PROC_FATAL_ERROR; /* error return */
+      }
+   }
+   else
+   {
+      /* Some data was read. Update the timer */
+      tel_start_timer(&(t->curr_tick));
+   }
+
+   t->rxsize=readval;
+   t->stats.rcvd+=readval;
+
+
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tel_sp_char_proc()
+ * 
+ * Process special characters like BackSpace, ESC(erase line).
+ * This function modifies both the input buffer and the
+ * output buffer. The erased chars, lines are removed from
+ * input buffer and output is generated to be sent
+ * to the telnet peer.
+ *
+ * PARAM1: char *buf - Pointer to buffer having unprocessed string (IN/OUT)
+ * PARAM2: int *in_size - Pointer to size of input buffer (IN/OUT)
+ * PARAM3: char *obuf - Pointer to output buffer (OUT)
+ * PARAM4: int *obuf_size - Pointer to size of output buffer (OUT)
+ * PARAM5: int old_size - Previous size of the bufer (IN)
+ *
+ * RETURNS: SUCCESS or error number.
+ */
+
+int
+tel_sp_char_proc(char * buf, int * in_size, char * obuf, int * obuf_size, 
+   int   old_size)
+{
+   int   i=old_size;
+   int   out_size=0;
+   int   remaining=*in_size-old_size;
+   int   prev_crlf;
+   int   chars_in_cmd;
+
+   if (remaining <= 0)
+      return TEL_SP_BAD_SIZE;
+
+   /* Telnet RFC says that EC (EraseCharacter), EL (EraceLine) 
+    * commands are always preceded by an IAC. But we don't receive it 
+    * that way via telnet client. Maybe it is true when two processes 
+    * communicate via telnet ! Hence provide the hook here also.
+    */
+   while (remaining > 0) 
+   {
+      if (buf[i] == TEL_BACKSP)
+      {
+         /* update the input/command buffer */
+
+         remaining -= 2;
+
+         if (*in_size > 1)     /* if there is a char to erase */
+         {
+            (*in_size) -= 2;   /* reduce size of input buffer */
+
+            i--;
+
+            /* Update the output buffer */
+            obuf[out_size++] = TEL_BACKSP;
+            obuf[out_size++] = TEL_SPACE;
+            obuf[out_size++] = TEL_BACKSP;
+         }
+         else 
+         {
+            (*in_size) = '\0';    /* reduce size of input buffer */
+         }
+
+         /* If we are at end of string. no need for MEMMOVE*/
+         if (remaining > 0) 
+         {
+            MEMMOVE(buf+i, buf+i+2, remaining);
+         }
+      }
+      else if (buf[i] == TEL_ESC)
+      {
+         /* find the start of previous command */
+         prev_crlf = i-1;
+         while (prev_crlf >= 0)
+         {
+            if ((buf[prev_crlf]  ==TEL_CR) && 
+                ((buf[prev_crlf+1]==TEL_LF) || (buf[prev_crlf+1]==TEL_CRNUL)))
+            {
+               break;
+            }
+            else
+            {
+               prev_crlf--;
+            }
+         }
+         if (prev_crlf < 0)    /* No CRLF found */
+         {
+            prev_crlf = 0;
+            chars_in_cmd = i+1;
+         }
+         else
+         {
+            prev_crlf+=2;     /* Move past CRLF */
+            chars_in_cmd = i+1-prev_crlf;
+         }
+
+         /* chars_in_cmd contains the number of chars including ESC
+            key which are to be erased */
+         i=prev_crlf;
+         remaining--;
+         (*in_size)-=chars_in_cmd;    /* reduce size of input buffer */
+
+         if (remaining > 0)
+         {
+            MEMMOVE(buf+prev_crlf,buf+prev_crlf+chars_in_cmd,remaining);
+         }
+
+         /* Now update the output buffer */
+         while (--chars_in_cmd > 0)
+         {
+            obuf[out_size++] = TEL_BACKSP;
+            obuf[out_size++] = TEL_SPACE;
+            obuf[out_size++] = TEL_BACKSP;
+         }
+      }
+      else if (buf[i] == TEL_CR &&  buf[i+1] == TEL_CRNUL)
+      {
+         /* For UNIX systems, we receive CR,CRNULL when the <Enter> 
+          * key is pressed. But to make the cursor to goto start of 
+          * next line, UNIX systems (like everyone else) need CR,LF. 
+          * Hence make the substitution in output over here.
+          */
+         obuf[out_size++] = buf[i];
+         obuf[out_size++] = TEL_LF;
+         i+=2;
+         remaining-=2;
+      }
+      else
+      {
+         obuf[out_size++] = buf[i];
+         remaining--;
+         i++;
+      }
+   }
+
+   *obuf_size = out_size;
+   return SUCCESS;
+}
+
+
+/* FUNCTION: tel_proc_cmd()
+ * 
+ * Process the data that we have received till now.
+ * If there any commands in it, call tel_exec_cmd() to execute them.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection. (IN)
+ *
+ * REMARKS: The members cmdbuf, cmdsize of tconn are modified in this
+ * function.
+ *
+ * RETURNS: SUCCESS or error number 
+ */
+
+int
+tel_proc_cmd(TEL_CONN tconn)
+{
+   int   i;
+   int   nextpos=0;
+   static char cmd[TEL_RECV_BUF_SIZE];
+
+   for (i=0; i < tconn->cmdsize; i++)
+   {
+      /* Treat CR or CR+LF or CR+CRNUL as command terminators     
+       * When RETURN/ENTER key is pressed ,
+       *    BSD2.6 client returns CR,CRNUL, 
+       *    Win9x/Win2000 returns CR,LF 
+       *    Windows XP returns CR 
+       */ 
+      if ((tconn->cmdbuf[i] == TEL_CR))
+      {
+         /* Yes we got one command. Execute it */
+         if (i==nextpos)    /* User has just pressed <CRLF> */
+         {
+#ifdef TEL_USERAUTH
+            if (tconn->state == TEL_PASSWORD)
+            {
+               /* User has entered the password */
+               if (TEL_CHECK_PERMIT(tconn->name,"") == TRUE)
+               {
+                  /* Valid user. So goto NORMAL state */
+                  tconn->state =TEL_NORMAL;
+                  tconn->prompt=prompt;
+                  ns_printf(&(tconn->tel_io),"\nWelcome %s\n",tconn->name);
+               }
+               else
+               {
+                  /* Invalid password. Try again */
+                  if (tconn-> tries >= tglob.tel_max_login_tries)
+                  {
+                     /* We have given enough attempts. Terminate connection */
+                     tel_delete(tconn);
+                     return TEL_PROC_AUTH_FAILED;
+                  }
+                  tconn->state=TEL_LOGIN;
+                  tconn->prompt=tel_login_prompt;
+               }
+            }
+#endif
+         }
+         else
+         {
+            tconn->stats.cmds++;
+
+            MEMCPY(cmd,tconn->cmdbuf+nextpos,i-nextpos);
+            cmd[i]=0;   /* Null terminate */
+
+            if (tconn->state == TEL_NORMAL)
+            {
+               /* Handle the special case of logging out */
+               if (stricmp(cmd,"logout") == 0 ||
+                   stricmp(cmd,"exit") == 0)
+               {
+                  tel_delete(tconn);
+                  return TEL_PROC_LOGGED_OUT;
+               }
+               tconn->tel_io.inbuf=cmd;
+               tconn->tel_io.getch=tel_tcp_recv;
+               if (tel_exec_cmd(&(tconn->tel_io)) == 0)
+               {
+                  /* Command was properly executed. Return to
+                   * normal state. 
+                   * Consider the following calling sequence.
+                   * tel_exec_cmd()->do_command()->dumpbuf()->
+                   *   con_page()->tel_tcp_recv()
+                   * If the TELNET client closed connection
+                   * then tel_tcp_recv() would cleanup the telnet connection.
+                   * But do_command() & hence tel_exec_cmd() would still return 0.  
+                   * In that case, tel_exec_cmd() can't detect  it. 
+                   * Hence check if tconn is valid.
+                   */
+                  TEL_CONN tmp=telq;
+                  while (tmp && tmp != tconn)  /* search all connections */
+                     tmp=tmp->next;
+                  if (!tmp)  /* couldn't find tconn */
+                     return TEL_PROC_LOGGED_OUT;
+            
+                  if (tconn->state == TEL_PROC_CMD)
+                     tconn->state = TEL_NORMAL;
+               }
+            }
+#ifdef TEL_USERAUTH
+            else if (tconn->state == TEL_LOGIN)
+            {
+               /* User has entered the login name */
+               strncpy(tconn->name,cmd,MAX_USERLENGTH);
+               tconn->prompt=tel_passwd_prompt;
+               tconn->state =TEL_PASSWORD;
+               tconn->tries++;
+            }
+            else if (tconn->state == TEL_PASSWORD)
+            {
+               /* User has entered the password */
+               if (TEL_CHECK_PERMIT(tconn->name,cmd) == TRUE)
+               {
+                  /* Valid user. So goto NORMAL state */
+                  tconn->state =TEL_NORMAL;
+                  tconn->prompt=prompt;
+                  ns_printf(&(tconn->tel_io),"\nWelcome %s\n",tconn->name);
+               }
+               else
+               {
+                  /* Invalid password. Try again */
+                  if (tconn-> tries >= tglob.tel_max_login_tries)
+                  {
+                     /* We have given enough attempts. Terminate connection */
+                     tel_delete(tconn);
+                     return TEL_PROC_AUTH_FAILED;
+                  }
+                  tconn->state=TEL_LOGIN;
+                  tconn->prompt=tel_login_prompt;
+               }
+            }
+#endif   /* TEL_USERAUTH */
+         }
+
+         /* Show the prompt */
+         ns_printf(&tconn->tel_io,tconn->prompt);
+         nextpos=i+1;   /* Position of start of new command */
+         if (nextpos < tconn->cmdsize)
+         {
+            /* Discard the extra linefeed related char sent by BSD/Win9x */
+            if ((tconn->cmdbuf[i+1]==TEL_LF) || (tconn->cmdbuf[i+1]==TEL_CRNUL))
+               nextpos++;
+         }
+
+         /* Send the GA command if it is not suppressed */
+         if (tconn->options->sga.l_value == FALSE)
+         {
+            tel_send_cmd(tconn->sock,TEL_GOAHEAD,0);
+         }
+      }              
+
+   }
+
+   /* The commands has been processed. So remove them from cmdbuf*/
+   if (nextpos == 0)  /* No cmds were found */
+   {
+      /* Do nothing */
+   }
+   else if (nextpos == tconn->cmdsize)
+   {
+      /* Whole string in cmdbuf has been processed */
+      tconn->cmdsize=0;
+   }
+   else if (nextpos < tconn->cmdsize)
+   {
+      /* We need to remove the processed string from cmdbuf,
+         so that cmdbuf contains only the unprocessed input */
+      tconn->cmdsize-=nextpos;
+      MEMMOVE(tconn->cmdbuf,tconn->cmdbuf+nextpos,tconn->cmdsize);
+   }
+   else     /* nextpos > tconn->rxsize */
+   {
+      /* What? We processed ahead of the buffer !! */
+      dtrap();
+   }
+
+   return SUCCESS;
+}
+
+
+#endif   /* #ifdef TELNET_SVR */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.h b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.h
new file mode 100644
index 0000000..ccc4294
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telnet.h
@@ -0,0 +1,350 @@
+/*
+ * FILENAME: telnet.h
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ *
+ * PORTABLE: yes
+ */
+
+/* telnet.h Header file for Telnet Some #defines have been taken from 
+ * NCSA Telnet code. 
+ */
+#ifndef TELNET_H
+#define  TELNET_H                1
+
+
+#include "telport.h"
+
+/* the data member state of TelnetConn can have the following values */
+#define  TEL_NORMAL           1  /* connection is normal    */
+#define  TEL_PROC_CMD         2  /* processing some cmd     */
+#define  TEL_LOGIN            3  /* accepting user login    */
+#define  TEL_PASSWORD         4  /* accepting user password */
+
+
+#define  TEL_RECV_BUF_SIZE    512
+#define  TEL_SEND_BUF_SIZE    2048
+
+#define  TELNET_PORT          23
+#define  TEL_MAX_NEWLN        20 /* max newln in str for tel_tcp_send()*/
+
+#define  TEL_MAX_LOGIN_TRIES  5
+#define  TEL_IDLE_TIME        600 /* time in sec for which conn can be idle */
+
+
+struct TelGlobals  /* Struct contaning all global params of Telnet */
+{
+   int tel_recv_buf_size  ; /* TEL_RECV_BUF_SIZE   */
+   int tel_send_buf_size  ; /* TEL_SEND_BUF_SIZE   */
+   int tel_port           ; /* TELNET_PORT         */
+   int tel_max_login_tries; /* TEL_MAX_LOGIN_TRIES */
+   int tel_idle_time      ; /* TEL_IDLE_TIME       */
+};
+
+extern struct TelGlobals tglob;  
+
+/* TelnetOption is used to store information about options that are 
+ * concerned with DO,DONT,WILL,WONT commands A TELNET connection is a 
+ * two way communication channel. That means, options must be 
+ * negotiated separately for each direction of data flow, if that is 
+ * desired. (RFC 856) Hence we have l_ prefix to denote parameters 
+ * pertaining to local session and r_ prefix to denote parameters 
+ * pertaining to remote session. WILL command is used to negotiate 
+ * options for local telnet session. DO command is used to negotiate 
+ * options for remote telnet session. Conversely, when we receive a 
+ * WILL command, the option is being negotiated for the remote telnet 
+ * session. And when we receive a DO command, the option is being 
+ * negotiated for the local telnet session. 
+ */
+struct TelnetOption
+{
+   int   option   ;     /* Option that we are refering to */
+   int   config   ;     /* Whether it is configurable or not (TRUE/FALSE) */
+   int   l_value  ;     /* value for local telnet-enabled/disabled (TRUE/FALSE) */
+   int   r_value  ;     /* value for remote telnet-enabled/disabled (TRUE/FALSE) */
+   int l_negotiate;   /* Do we negotiate for this option when a new
+                         telnet connection is started ? (TRUE/FALSE) */
+   int r_negotiate;   /* Do we negotiate for this option when a new
+                         telnet connection is started ? (TRUE/FALSE) */
+   int l_req_sent ;   /* Have we sent a telnet cmd for a change in value
+                         of this option ? (TRUE/FALSE) */
+   int r_req_sent ;   /* Have we sent a telnet cmd for a change in value
+                         of this option ? (TRUE/FALSE) */
+};
+
+typedef struct TelnetOption * TEL_OPT;
+
+
+/* This structure contains a list of all the options that we will be 
+ * supporting. There will be a global variable "tel_def_options" 
+ * which will contain default values for all these options. A new 
+ * telnet session starts with these default values and updates them 
+ * based on negotiations. To have automatic telnet processing of an 
+ * option, we will have the requirement that all the members of this 
+ * strucure are of type "struct TelnetOption". If support for a a new 
+ * option is to be added, then the following needs to be done. 
+ * 1. Add * it in this structure. 
+ * 2. Add its default value in "tel_def_options" 
+ * 3. Use its values whereever required. Its values will be 
+ *    automatically negotiated at the start of telnet session. 
+ *    And they also be dynamically changed if it is negotiated midway 
+ *    through the session. If its value needs to be changed midway 
+ *    through the session, then code should be added to send a telnet 
+ *    command to the peer. 
+ */
+struct TelOptionList {
+     struct TelnetOption  binary;
+     struct TelnetOption  echo  ;
+     struct TelnetOption  sga   ;
+     struct TelnetOption  status;
+};
+
+
+
+/* Structures to maintain various statistics */
+
+struct TelStatistics       /* statistics for telnet server */
+{
+   long  conn_opened;   /* Total num of connections opened till date */
+   long  conn_closed;   /* Total num of connections closed till date */
+};
+
+struct TelSessStats        /* statistics for a telnet session */
+{
+   u_long   rcvd;       /* total bytes received    */
+   u_long   cmds;       /* total commands executed */
+};
+
+
+/* Structure to maintain TCP/IP sockets */
+
+struct TelnetConn
+{
+   struct TelnetConn *  next;    /* Pointer to the next socket  */
+   int            state;         /* state of the protocol.  */
+   u_long         curr_tick;     /*   time-tick   of last  data  receive   */
+   SOCKTYPE       sock;          /* the open socket we are using  */
+   char *         rxbuf;         /* input data from the client */
+   char *         txbuf;         /* Output data for the client   */
+   char *         cmdbuf;        /* Buffer which contains data from user*/
+   int            rxsize;        /* size of valid data in rxbuf  */
+   int            txsize;        /* size of unsent data in txbuf   */
+   int            cmdsize;       /* size of cmdbuf   */
+   int            inserver;      /* telnet server's renetry guard flag  */
+   char *         prompt;           /* current prompt for this session  */
+   struct TelOptionList *  options; /* Options for a telnet session   */
+   struct GenericIO     tel_io;     /* I/O structure used for ns_printf  */
+   struct TelSessStats  stats;      /* Statistics for this session  */
+#ifdef TEL_USERAUTH
+   /* If we support authentication, We just need to remember the name. If session needs
+    * password, permissions, etc., it can access the user database
+    */
+   char   name[MAX_USERLENGTH];
+   int                  tries;   /* Num of times user has tried to login*/
+#endif
+
+};
+
+typedef struct TelnetConn * TEL_CONN ;
+
+
+
+#define  TEL_CMD_LOW             236
+
+/* Telnet Command codes. The description of each of them is in 
+ * tel_cmd_str[]. So, SE-TEL_CMD_LOW would give the index into 
+ * tel_cmd_str[]. That is tel_cmd_str[SE-TEL_CMD_LOW] is the 
+ * description for SE 
+ */
+/* The following constants would be part of a packet. Packet would be 
+ * put in a char[]. If we don't put the (char) before these constant 
+ * values, then we face problems with Microsoft compiler in 
+ * situations like "if ( == IAC ) ". Here even if is IAC, the 
+ * comparison would fail. Because the compiler would have generated 
+ * an extra command CBW for IAC. CBW (ConvertByteToWord) makes a 
+ * signed extension and hence for constant values greater that 127, 
+ * that would become "FF XX" where XX is the hex representation of 
+ * the constant. 
+ */
+#define  TEL_EOF                 236
+#define  TEL_SUSP                237
+#define  TEL_ABORT               238
+
+#define  TEL_SE                  240
+#define  TEL_NOP                 241
+#define  TEL_DM                  242
+#define  TEL_BREAK               243
+#define  TEL_IP                  244
+#define  TEL_AO                  245
+#define  TEL_AYT                 246
+#define  TEL_EC                  247
+#define  TEL_EL                  248
+#define  TEL_GOAHEAD             249
+#define  TEL_SB                  250
+#define  TEL_WILL                251
+#define  TEL_WONT                252
+#define  TEL_DO                  253
+#define  TEL_DONT                254
+#define  TEL_IAC                 255
+
+/* Assigned Telnet Options. Description is in tel_opt_str[] */
+
+#define  TEL_BINARY              0
+#define  TEL_ECHO                1
+#define  TEL_RECONNECT           2
+#define  TEL_SGA                 3
+#define  TEL_AMSN                4
+#define  TEL_STATUS              5
+#define  TEL_TIMING              6
+#define  TEL_RCTAN               7
+#define  TEL_OLW                 8
+
+#define  TEL_CR                  0x0d  /* Ascii Carriage Return */
+#define  TEL_LF                  0x0a  /* Ascii LineFeed */
+#define  TEL_CRNUL               0x00  /* NULL that follows CR in telnet*/
+#define  TEL_BACKSP              0x08  /* Ascii BackSpace key */
+#define  TEL_ESC                 0x1B  /* Ascii ESCAPE key */
+#define  TEL_SPACE               0x20  /* Ascii SPACE key */
+
+
+/* The following macros are used to display description for various codes.
+   Description is included only if option is set */
+#ifdef TEL_SHOW_MSG
+
+#define  TEL_CMD_STR_SIZE  20
+#define  TEL_OPT_STR_SIZE  256
+extern   char *   tel_cmd_str [TEL_CMD_STR_SIZE];
+extern   char *   tel_opt_str [TEL_OPT_STR_SIZE];
+#define  TEL_CMD_STR(X)    ((X<TEL_CMD_LOW)  ? "" : tel_cmd_str[X-TEL_CMD_LOW])
+#define  TEL_OPT_STR(X)    tel_opt_str[X]
+extern   char *   tel_err_str (int value);   /* telerr.c */
+
+#else
+
+#define  TEL_CMD_STR(X)  ""
+#define  TEL_OPT_STR(X)  ""
+
+#endif   /* TEL_SHOW_MSG */
+
+
+/* List of error values used by telnet */
+
+#define  TELBASE                                2000
+
+/* used by tel_new() */
+#define  TEL_NEW_ALLOC_ERR                      (TELBASE+11)
+#define  TEL_NEW_CANT_ALLOC_RECV_BUF            (TELBASE+12)
+#define  TEL_NEW_CANT_ALLOC_SEND_BUF            (TELBASE+13)
+#define  TEL_NEW_CANT_ADD_TO_Q                  (TELBASE+14)
+#define  TEL_NEW_CANT_ALLOC_OPTIONS             (TELBASE+15)
+#define  TEL_NEW_CANT_ALLOC_CMD_BUF             (TELBASE+16)
+
+/* used by tel_delq() */
+#define  TEL_DELQ_Q_EMPTY                       (TELBASE+21)
+#define  TEL_DELQ_CONN_NOT_FOUND                (TELBASE+22)
+
+/* used by tel_delete() */
+#define  TEL_DEL_NULL_ARGUMENT                  (TELBASE+31)
+
+/* used by tel_init() */
+#define  TEL_INIT_CANT_OPEN_SOCKET              (TELBASE+41)
+#define  TEL_INIT_BIND_FAILED                   (TELBASE+42)
+#define  TEL_INIT_LISTEN_FAILED                 (TELBASE+43)
+#define  TEL_INIT_ASYNCSELECT                   (TELBASE+44)
+#define  TEL_INIT_RCVBUF                        (TELBASE+45)
+#define  TEL_INIT_SNDBUF                        (TELBASE+46)
+#define  TEL_INIT_STARTUP_ERR                   (TELBASE+47)
+
+/* used by tel_check() */
+#define  TEL_CHECK_NO_LISTEN_SOCK               (TELBASE+51)
+
+/* used by tel_process() */
+#define  TEL_PROC_TCP_CLOSED                    (TELBASE+61)
+#define  TEL_PROC_FATAL_ERROR                   (TELBASE+62)
+#define  TEL_PROC_LOGGED_OUT                    (TELBASE+63)
+#define  TEL_PROC_AUTH_FAILED                   (TELBASE+64)
+#define  TEL_PROC_TIMED_OUT                     (TELBASE+65)
+
+/* used by tel_sp_char_proc() */
+
+#define  TEL_SP_BAD_SIZE                        (TELBASE+71)
+
+
+/* Some peculiar error values. All error codes starting with TEL_N 
+ * are compulsorily NEGATATIVE values. These would be used at places 
+ * where positive values have some meaning.
+ */
+#define  TEL_N_CMD_UNKNOWN                      -1
+#define  TEL_N_NO_IAC                           -2
+#define  TEL_N_NO_SB                            -3 
+#define  TEL_N_NO_SE                            -4
+
+
+/* List of global variables used in various files */
+
+extern   struct TelOptionList    tel_opt_list;
+extern   struct TelStatistics    tel_stats;  /* stats for all telnet sessions */
+
+extern   TEL_CONN telq;          /* Start of queue of open connections*/
+extern   long     last_error;    /* last error that occured */
+extern   char *   prompt;        /* For InterNiche stack is defined in main.c */
+
+
+
+/* X=start position, Y=number of bytes to skip, Z=current size of buffer */
+#define  tel_move(X,Y,Z)   MEMMOVE(X,X+Y,Z-Y)
+
+
+/* List of functions in telnet.c */
+
+TEL_CONN tel_new(void);
+int      tel_delete(TEL_CONN tconn);
+int      tel_addq(TEL_CONN tconn);
+int      tel_delq(TEL_CONN tconn);
+int      tel_loop(void);
+int      tel_tcp_send(long s, char * buf, int len);
+int      tel_process(TEL_CONN tcon);
+TEL_CONN tel_conn_from_sock(SOCKTYPE s);
+int      tel_read(TEL_CONN tconn);
+int      tel_sp_char_proc(char * buf, int * in_size, char * obuf, 
+            int * obuf_size,  int   old_size);
+int      tel_proc_cmd(TEL_CONN tconn);
+TEL_CONN tel_connection(SOCKTYPE temp_sock);
+
+
+/* List of functions in telport.c */
+
+int      tel_init(void);
+void     tel_cleanup(void);
+void     tel_check(void);
+void     tel_start_timer(unsigned long * timer);
+int      tel_check_timeout(unsigned long timer, u_long interval);
+int      tel_proc_subcmd(TEL_CONN tconn, u_char * cmd, int cmd_len);
+int      tel_tcp_recv(long iodesc);
+int      tel_nvram_init(void);
+
+
+/* List of functions in telparse.c */
+
+int      tel_parse(TEL_CONN tconn);
+int      tel_parse_cmd(TEL_CONN tconn, u_char * pos);
+void     tel_parse_option (TEL_CONN tconn, int cmd, int new_opt);
+void     tel_start_nego(TEL_CONN tconn);
+int      tel_parse_subcmd(TEL_CONN tconn, u_char * cmd);
+int      tel_send_cmd(SOCKTYPE sock, int cmd, int option);
+TEL_OPT  tel_opt_search(struct TelOptionList *list,int find);
+
+
+/* List of functions in telmenu.c */
+
+int      tel_menu_init(void);
+int      tel_show_opt(void * pio);
+int      tel_show_stats(void * pio);
+int      tel_close_sess(void * pio);
+
+#endif   /* TELNET_H */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telparse.c b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telparse.c
new file mode 100644
index 0000000..ec8a314
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telparse.c
@@ -0,0 +1,685 @@
+/*
+ * FILENAME: telparse.c
+ *
+ * Copyright 1998- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ * ROUTINES: tel_parse(), tel_parse_cmd(), tel_parse_option(), 
+ * ROUTINES: tel_start_nego(), tel_parse_subcmd(), tel_opt_search(), 
+ * ROUTINES: tel_send_cmd(),  
+ *
+ * PORTABLE: yes
+ */
+
+
+/* File telparse.c Implementation file for Telnet Server 
+ */
+#include "telnet.h"
+
+#ifdef TELNET_SVR       /* Then include this source file */
+
+
+/* Local variables */
+
+#ifdef TEL_SHOW_MSG
+
+char *   tel_cmd_str[20]={
+   "EOF",
+   "Suspend Process",
+   "Abort Process",
+   "Unknown (239)",
+   "Subnegotiation End",
+   "NOP",
+   "Data Mark",
+   "Break",
+   "Interrupt Process",
+   "Abort Output",
+   "Are You There",
+   "Erase Character",
+   "Erase Line",
+   "Go Ahead",
+   "Subnegotiate",
+   "Will",
+   "Won't",
+   "Do",
+   "Don't",
+   "IAC",
+};
+
+char *   tel_opt_str[256]={      /* ascii strings for Telnet options */
+   "Binary",                     /* 0 */
+   "Echo",
+   "Reconnection",
+   "Supress Go Ahead",
+   "Message Size Negotiation",
+   "Status",                              /* 5 */
+   "Timing Mark",
+   "Remote Controlled Trans and Echo",
+   "Output Line Width",
+   "Output Page Size",
+   "Output Carriage-Return Disposition",     /* 10 */
+   "Output Horizontal Tab Stops",
+   "Output Horizontal Tab Disposition",
+   "Output Formfeed Disposition",
+   "Output Vertical Tabstops",
+   "Output Vertical Tab Disposition",        /* 15 */
+   "Output Linefeed Disposition",
+   "Extended ASCII",
+   "Logout",
+   "Byte Macro",
+   "Data Entry Terminal",                    /* 20 */
+   "SUPDUP",
+   "SUPDUP Output",
+   "Send Location",
+   "Terminal Type",
+   "End of Record",                       /* 25 */
+   "TACACS User Identification",
+   "Output Marking",
+   "Terminal Location Number",
+   "3270 Regime",
+   "X.3 PAD",                             /* 30 */
+   "Negotiate About Window Size",
+   "Terminal Speed",
+   "Toggle Flow Control",
+   "Linemode",
+   "X Display Location",                  /* 35 */
+   "Environment",
+   "Authentication",
+   "Data Encryption",
+   "39",
+   "40","41","42","43","44","45","46","47","48","49",
+   "50","51","52","53","54","55","56","57","58","59",
+   "60","61","62","63","64","65","66","67","68","69",
+   "70","71","72","73","74","75","76","77","78","79",
+   "80","81","82","83","84","85","86","87","88","89",
+   "90","91","92","93","94","95","96","97","98","99",
+   "100","101","102","103","104","105","106","107","108","109",
+   "110","111","112","113","114","115","116","117","118","119",
+   "120","121","122","123","124","125","126","127","128","129",
+   "130","131","132","133","134","135","136","137","138","139",
+   "140","141","142","143","144","145","146","147","148","149",
+   "150","151","152","153","154","155","156","157","158","159",
+   "160","161","162","163","164","165","166","167","168","169",
+   "170","171","172","173","174","175","176","177","178","179",
+   "180","181","182","183","184","185","186","187","188","189",
+   "190","191","192","193","194","195","196","197","198","199",
+   "200","201","202","203","204","205","206","207","208","209",
+   "210","211","212","213","214","215","216","217","218","219",
+   "220","221","222","223","224","225","226","227","228","229",
+   "230","231","232","233","234","235","236","237","238","239",
+   "240","241","242","243","244","245","246","247","248","249",
+   "250","251","252","253","254",
+   "Extended Options List"                /* 255 */
+};
+
+#endif   /* TEL_SHOW_MSG */
+
+
+/* FUNCTION: tel_parse()
+ * 
+ * Parse the input string that has been just received 
+ * (Would have been copied into rxbuf of tconn)
+ * All the telnet commands present in rxbuf would be
+ * processed and stripped out. So at the end of this
+ * routine, rxbuf will not contain any telnet commands.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection (IN)
+ *
+ * RETURNS: SUCCESS or error number
+ * later- we may have to search ahead for DM 
+ */
+
+int tel_parse(TEL_CONN tconn)
+{
+   u_char * curr_pos=(u_char *)tconn->rxbuf;
+   u_char * mark     =(u_char *)tconn->rxbuf+tconn->rxsize;
+   int   bytes_to_skip=0;
+
+   while ( curr_pos < mark )
+   {
+      /* Scan through the whole buffer for special characters */
+      while ( curr_pos < mark && (*curr_pos) != TEL_IAC )
+      {
+         curr_pos++;
+      }
+
+      if ( curr_pos >= mark )    /* We have parsed everything we received */
+         break ;
+
+      if ( (*curr_pos) == TEL_IAC )    /* Check it again, just to be safe */
+      {
+         if ( (*(curr_pos+1)) == TEL_IAC )   /* padded IAC. So its data */
+         {
+            info_printf(("Padded IAC.\n"));
+            bytes_to_skip=1;
+
+            tel_move(curr_pos,bytes_to_skip,(mark-curr_pos));
+            tconn->rxsize   -=bytes_to_skip;
+            mark            -=bytes_to_skip;
+
+            continue ;
+         }
+         else
+         {
+            bytes_to_skip= tel_parse_cmd(tconn,curr_pos);
+
+            if ( bytes_to_skip < 0 )
+            {
+               dprintf("Error %d in tel_parse_cmd()\n",bytes_to_skip);
+               /* Either it can be error in ExecCmd or OptionCmd. So 
+                * let us assume that there was error in ExecCmd. 
+                * ExecCmd is of 2 bytes.
+                */
+               bytes_to_skip=2; 
+            }
+
+            tel_move(curr_pos,bytes_to_skip,(mark-curr_pos));
+            tconn->rxsize   -=bytes_to_skip;
+            mark            -=bytes_to_skip;
+
+            continue ;
+         }
+      }
+   }
+
+   return SUCCESS;
+}
+
+
+
+
+/* int tel_move(char int skip, int buf_size) 
+ * { 
+ *    MEMMOVE(curr_pos,curr_pos+skip,buf_size-skip);
+ * } 
+ */
+
+
+/* FUNCTION: tel_parse_cmd()
+ * 
+ * Parse the command and take action on it.
+ * If we it is a sub-cmd, then call tel_parse_subcmd()
+ * to have it processed. For DO/WILL/DONT/WONT option 
+ * negotiation, call tel_parse_option()
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection (IN)
+ * PARAM2: u_char * pos - Postion of command in rxbuf (IN)
+ *
+ * RETURNS: Length of the command processed. Returns negative number
+ * if any error occurs.
+ */
+
+int
+tel_parse_cmd(TEL_CONN tconn, u_char * pos)
+{
+
+    int   retValue=2; /* By default we process 2 chars:IAC, and CMD */
+   /* DO,DONT,WILL,WONT process 3*/
+   /* Subnegotiation processes n chars */
+
+   info_printf(("RECV: %s %s\r\n",TEL_CMD_STR(*(pos+1)),TEL_OPT_STR(*(pos+2))));
+
+   if ( (*pos) == TEL_IAC )
+   {
+      /* Check the next byte */
+      if ( (*(pos+1)) >= TEL_SE ) /* SE is the lowest numbered telnet cmd */
+      {
+
+         switch ( (*(pos+1)) )
+         {
+         case TEL_AYT    :  /* received a telnet Are-You-There command     */
+            /* Send back some visible evidence that we got it */
+            ns_printf(&(tconn->tel_io),"Got Are-You-There cmd.\n%s",
+             tconn->prompt);
+            break;
+
+         case TEL_IP     :  /* received a telnet Interrupt Process command */
+            /* terminate previous task on this session */
+            /* For example, if pinging is going on, terminate it */
+            break;
+
+         case TEL_AO     :  /* received a telnet Abort Output command      */
+            /* In a preemptive system, set the tel_io structure such 
+             * that output goes to /dev/null. That is the telnet peer 
+             * should not get any messages. This command does not 
+             * have much use on a non-preemptive OS.
+             */
+            break;
+         case TEL_EL     :  /* received a telnet erase line command        */
+         case TEL_EC     :  /* received a telnet erase character command   */
+         case TEL_BREAK  :  /* received a telnet Break command             */
+         case TEL_DM     :  /* received a telnet Data Mark command         */
+         case TEL_NOP    :  /* received a telnet No Operation command      */
+         case TEL_SE     :  /* received a telnet Subnegotiation End command*/
+         case TEL_ABORT  :  /* received a telnet Abort Process command     */
+         case TEL_SUSP   :  /* received a telnet Suspend Process command   */
+         case TEL_EOF    :  /* received a telnet EOF command               */
+         case TEL_GOAHEAD:  /* received   telnet go ahead option           */
+            dprintf("Got telnet cmd %d.\n",*(pos+1));
+            break;
+
+         case TEL_DO     :  /* received a telnet DO negotiation            */
+         case TEL_DONT   :  /* received a telnet DONT option               */
+         case TEL_WILL   :  /* received a telnet WILL option               */
+         case TEL_WONT   :  /* received a telnet WONT option               */
+            tel_parse_option(tconn,*(pos+1),*(pos+2));
+            retValue=3;
+            break ;
+         case TEL_SB     :  /* received   telnet sub-options negotiation   */
+            retValue = tel_parse_subcmd(tconn,pos) ;
+            break ;
+         }
+      }
+      else
+      {
+         dtrap();
+         dprintf("Unknown telnet cmd %d:%d\n",*pos,*(pos+1) );
+         return TEL_N_CMD_UNKNOWN;
+      }
+   }  
+   else
+   {
+     /* Some other character . For eg. ESC. 
+        Right now we are not processing it */
+      return TEL_N_NO_IAC;
+   }
+
+   return retValue ;     
+}
+
+
+/* FUNCTION: tel_parse_option()
+ * 
+ * Parse a DO/DONT/WILL/WONT negotiation option and
+ * take appropriate action. Appropriate action include 
+ * setting values for the option and sending a reply to
+ * the peer.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to TelnetConn (IN)
+ * PARAM2: int cmd - Option Cmd. It can be either of DO/DONT/WILL/WONT (IN)
+ * PARAM3: int new_opt - Option that we are refering to (IN)
+ *
+ * REMARKS: NCSA telnet implementation has got a SWITCH->CASE 
+ * for each option. So if a new option is to be added,
+ * 1. The parameter needs to be added to telnet structure,
+ * 2. Additions to be done to SWITCH for the new option.
+ * 3. New set of similar code. More chances of bug. Bulkier
+ * code. Advantage would be minimal reduction in processing
+ * time. 
+ * Hence we have a generic structure TelnetOption to hold
+ * values for an option. There is a global structure tel_opt_list
+ * which is a collection of all the supported options.
+ * When a new telnet session is created, it starts with
+ * a copy of the default options. This function is 
+ * a generic mechanism to manipulate values for these options.
+ * So if this function works perfect, it works so for
+ * all the options.
+ *
+ * RETURNS: Nothing.
+ * Algorithm   : The algorithm used here is as follows.
+ * 1. For each telnet session, there is an structure containing
+ * all the options supported.
+ * 2. If we can't find "new_opt"  for this session, then
+ *    a. Give negative reply for received DO/WILL cmd
+ *    b. Do nothing for received DONT/WILL. This is a rare
+ *    condition. Because
+ *    (i) A DONT/WONT is either a reply
+ *    (ii) Or DONT/WONT is done halfway thru a session
+ *    to disable a previously agreed option.
+ * 3. If a DO OPTION is received
+ *    a. If the value is already set, do nothing.
+ *    b. Check if the option is configurable. Otherwise
+ *    reply with a WONT.
+ *    c. Check if we had sent a WILL request for this option.
+ *    If yes, enable the option. If no, enable the option
+ *    and reply with a WILL.
+ * 4. If a DONT OPTION is received,
+ *    a. If the option is already disabled, do nothing.
+ *    b. Otherwise check if we had sent a request.
+ *    If yes, then disable this option. 
+ *    If no,  then diable this option and reply with WONT.
+ * 5. WILL, WONT will have similar explanations. 
+ * 6. Each option will have two set of values. One for the
+ * local TELNET session & other for the REMOTE telnet session.
+ *    a. DO,DONT manipulate values  for the LOCAL telnet session
+ *    b. WILL,WONT manipulate values for the REMOTE 
+ *    telnet session
+ */
+
+void 
+tel_parse_option(TEL_CONN tconn, int cmd, int new_opt)
+{
+   TEL_OPT opt;
+
+   opt=tel_opt_search(tconn->options,new_opt);
+   if ( opt == NULL )
+   {
+      info_printf(("[%d] not found in option list.\n",new_opt));
+   }
+
+   switch ( cmd )
+   {
+   case TEL_DO  :   /* received a telnet DO negotiation            */
+      /* First check if we have new_opt */
+      if ( opt == NULL )
+      {
+         /* We don't support new_opt */
+         tel_send_cmd(tconn->sock,TEL_WONT,new_opt);
+      }
+      else
+      {
+         if ( opt->l_value == TRUE )  /* it is already set */
+         {
+            /* Do Nothing */
+         }      
+         else
+         {
+            if ( opt->config == FALSE ) 
+            {
+               /* Not configurable via telnet */
+               tel_send_cmd(tconn->sock,TEL_WONT,new_opt);
+            }
+            else
+            {
+               /* Have we asked for this option ? */
+               if ( opt->l_req_sent == FALSE )
+               {
+                  /* Tell peer that we accept the offer*/
+                  tel_send_cmd(tconn->sock,TEL_WILL,new_opt );
+               }
+               opt->l_value = TRUE;
+            }
+         }
+
+         if ( opt->l_req_sent == TRUE )
+         {
+            /* Yes, we had requested this option & got a response */
+            opt->l_req_sent = FALSE;
+         }
+      }
+      break ;
+
+   case TEL_DONT:   /* received a telnet DONT option               */
+      /* First check if we have new_opt */
+      if ( opt == NULL )
+      {
+         /* We don't support new_opt */
+      }
+      else
+      {
+         /* We receive DONT for an OPTION, under two conditions 1. We 
+          * had sent a "WILL Option" command 2. Previously we had 
+          * agreed for this parameter via (a) Local machine : WILL 
+          * ... , reply DO (b) Remote machine : DO ... , reply WILL 
+          * And now halfway thru the session, the PEER wants to 
+          * disable this option. This can be done only if the option 
+          * is configurable. Hence we don't need to verify it again 
+          * over here. Similar argument is valid for WONT also. 
+          */
+         if ( opt->l_value == TRUE )  /* it is set */
+         {
+            /* Have we asked for this option ? */
+            if ( opt->l_req_sent == FALSE )
+            {
+               /* Tell peer that we agree */
+               tel_send_cmd(tconn->sock,TEL_WONT,new_opt);
+            }
+            opt->l_value = FALSE;
+         }
+         else    /* Option is already disabled */
+         {  
+            /* do nothing */
+         }      
+
+         if ( opt->l_req_sent == TRUE )
+         {
+            /* Yes, we had requested this option & got a response */
+            opt->l_req_sent = FALSE;
+         }
+      }
+      break ;
+
+   case TEL_WILL:   /* received a telnet WILL option               */
+      /* First check if we have new_opt */
+      if ( opt == NULL )
+      {
+         /* We don't support new_opt */
+         tel_send_cmd(tconn->sock,TEL_DONT,new_opt);
+      }
+      else
+      {
+         if ( opt->r_value == TRUE )  /* it is already set */
+         {
+            /* do nothing */
+            info_printf(("WILL %s rcvd. .\n", TEL_CMD_STR(new_opt) ));
+         }      
+         else
+         {
+            if ( opt->config == FALSE ) 
+            {
+               /* Not configurable via telnet */
+               tel_send_cmd(tconn->sock,TEL_DONT,new_opt);
+            }
+            else
+            {
+               /* Have we asked for this option ? */
+               if ( opt->r_req_sent == FALSE )
+               {
+                  /* Tell peer that we accept the offer*/
+                  tel_send_cmd(tconn->sock,TEL_DO,new_opt);
+               }
+               opt->r_value = TRUE;
+            }
+         }
+
+         if ( opt->r_req_sent == TRUE )
+         {
+            /* Yes, we had requested this option & got a response */
+            opt->r_req_sent = FALSE;
+         }
+      }
+
+      break ;
+
+   case TEL_WONT:   /* received a telnet WONT option               */
+      /* First check if we have new_opt */
+      if ( opt == NULL )
+      {
+         /* We don't support new_opt */
+      }
+      else
+      {
+         if ( opt->r_value == TRUE )  /* it is set */
+         {
+            /* Have we asked for this option ? */
+            if ( opt->r_req_sent == FALSE )
+            {
+               /* Tell peer that we accept the offer*/
+               tel_send_cmd(tconn->sock,TEL_DONT,new_opt);
+            }
+            opt->r_value = FALSE;
+         }
+         else    /* Option is already disabled */
+         {  
+            /* do nothing */
+         }      
+
+         if ( opt->r_req_sent == TRUE )
+         {
+            /* Yes, we had requested this option & got a response */
+            opt->r_req_sent = FALSE;
+         }
+      }
+
+      break ;
+      default :
+         dtrap();    /* This should't happen !!!! */
+   }
+}
+
+
+/* FUNCTION: tel_start_nego()
+ * 
+ * Search the TelOptionList and start negotiations for
+ * marked options. That is if l_negotiate or r_negotiate
+ * field for an option is TRUE, then send the WILl or DO
+ * command for that option. And set l_req_sent or l_req_sent
+ * to TRUE. When the reply comes from the peer, then
+ * tel_parse_option() will update the values of the option.
+ *
+ * PARAM1: TEL_CONN tconn
+ * Pointer to  TelnetConn for which options are to be
+ * negotiated (IN)
+ *
+ * RETURNS: void
+ */
+
+void
+tel_start_nego(TEL_CONN tconn)
+{
+
+   int   cnt   =  sizeof(struct  TelOptionList)/sizeof(struct  TelnetOption)  ;
+   TEL_OPT opt;
+   int   i;
+
+   opt = (TEL_OPT)tconn->options ;
+
+   for ( i=0 ; i < cnt ; i++ )
+   {
+      if ( opt->l_negotiate == TRUE )
+      {
+         tel_send_cmd(tconn->sock,TEL_WILL,opt->option);
+         opt->l_req_sent=TRUE;
+         info_printf(("WILL %s\n",TEL_OPT_STR(opt->option)));
+      }
+      if ( opt->r_negotiate == TRUE )
+      {
+         tel_send_cmd(tconn->sock,TEL_DO,opt->option);
+         opt->r_req_sent=TRUE;
+         info_printf(("DO %s\n",TEL_OPT_STR(opt->option)));
+      }
+
+      opt++;
+   }
+}
+
+
+/* FUNCTION: tel_parse_subcmd()
+ * 
+ * Parse the sub-command and take action on it.
+ * Sub command start with SB and end with SE.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection (IN)
+ * PARAM2: u_char *cmd - Postion of command in rxbuf (IN)
+ *
+ * RETURNS: 
+ */
+
+int
+tel_parse_subcmd(TEL_CONN tconn, u_char * cmd)
+{
+   /* Do some meaningful stuff here later */
+
+   int   maxlen=255; /* If subcommand doesn't get completed in 255 chars, stop*/
+   int   cmd_len=0;
+   u_char * curr_pos;
+
+   if ( (*cmd+1) != TEL_SB )
+      return TEL_N_NO_SB;
+
+   curr_pos=cmd+2;      /* go past IAC, SB */
+
+   while ( !( (*curr_pos)==TEL_IAC && (*curr_pos+1)==TEL_SE ) )
+   {
+      curr_pos++;
+      cmd_len++;
+
+      if ( curr_pos - cmd > maxlen )
+         return TEL_N_NO_SE ;
+   }
+
+   tel_proc_subcmd(tconn,cmd+2,cmd_len);
+
+   return cmd_len+4 ;
+}
+
+
+/* FUNCTION: tel_opt_search()
+ * 
+ * Search the TelOptionList. If the option to be searched
+ * is found, then return a pointer to that TelnetOption element.
+ * If search fails, return NULL. TelOptionList is a structure
+ * will all members of type "TelnetOption". ASKJB to see 
+ * if it is portable.
+ *
+ * PARAM1: struct TelOptionList *list - Ptr to TelOptionList to be searched(IN)
+ * PARAM2: int find - Option to be searched (IN)
+ *
+ * RETURNS: A pointer to the found option element. If search fails,
+ * it returns NULL.
+ */
+
+TEL_OPT
+tel_opt_search(struct TelOptionList * list, int find)
+{
+   int   cnt   =  sizeof(struct  TelOptionList)/sizeof(struct  TelnetOption)  ;
+   TEL_OPT opt;
+   int   i;
+
+   if ( list == NULL )  /* sanity check */
+      return NULL ;  
+
+   opt = (TEL_OPT)list ;
+
+   for ( i=0 ; i < cnt ; i++ )
+   {
+      if ( opt->option == find )
+         return (opt);
+      opt++;
+   }
+
+   return NULL ;
+}
+
+
+
+/* FUNCTION: tel_send_cmd()
+ * 
+ * Send a telnet command. It can be a command for negotiation
+ * also. This function will handle only exec commands
+ * (Abort Output, IP, etc.) , and option commands 
+ * (DO,DONT,WILL,WONT). It will not handle sub-negotiation,
+ * as it requires random number of bytes to be sent. So for
+ * sub-negotiation, we will first fill the buffer and
+ * then use the send command. ExecCmd is of 2 bytes,
+ * and OptionCmd is of 3 bytes. For ExecCmd, the third
+ * parameter is ignored.
+ *
+ * PARAM1: SOCKET sock - Socket on which the command has to be sent (IN)
+ * PARAM2: int cmd - Command (IN)
+ * PARAM3: int option - Option  (IN)
+ *
+ * RETURNS: Whatever is returned by SEND.
+ */
+
+int     
+tel_send_cmd(SOCKET sock, int cmd, int option)
+{
+   unsigned char small_buf[3];
+   small_buf[0]=(u_char)TEL_IAC;
+   small_buf[1]=(u_char)cmd;
+   small_buf[2]=(u_char)option;
+
+   if ( cmd < TEL_WILL )   /* then it is a ExecCmd */
+      return sys_send(sock,(char *) small_buf,2,0);
+   else                    /* OptionCmd- DO/DONT/WILL/WONT */
+      return sys_send(sock,(char *) small_buf,3,0);
+}
+
+
+
+#endif   /* TELNET_SVR  */ 
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.c b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.c
new file mode 100644
index 0000000..87fe5aa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.c
@@ -0,0 +1,902 @@
+/*
+ * FILENAME: telport.c
+ *
+ * Copyright 1997- 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ * ROUTINES: tel_init(), tel_start_timer(), tel_check_timeout(), 
+ * ROUTINES: tel_cleanup(), tel_check(), tel_proc_subcmd(), sys_send(), 
+ * ROUTINES: sys_closesocket(), SocketMsg(), 
+ *
+ * PORTABLE: Within interniche systems
+ */
+
+/* 
+ * Define USE_FDS to enable using FD_xxx() functions, rather than
+ * ad hoc code. 
+ *
+ * TODO: Remove old code after testing.
+ *
+ * #define USE_FDS      1        // use FD_xxx() functions
+ */
+
+/* File telport.c File containing porting dependent stuff 
+ */
+#include "telnet.h"
+
+#ifdef TELNET_SVR       /* Then include this source file */
+
+#ifndef SUPERLOOP
+#ifndef OSPORT_H
+#error Need to define OSPORT_H
+#endif
+#include OSPORT_H
+#endif   /* SUPERLOOP */
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"
+struct telnet_nvparam telnet_nvparms;
+#endif   /* INCLUDE_NVPARMS */
+
+#ifdef IP_V4
+struct sockaddr_in   tel_sin;
+SOCKTYPE tel_listen = INVALID_SOCKET;
+#endif /* IPv4 */
+
+#ifdef IP_V6
+struct sockaddr_in6  tel_sin6;
+SOCKTYPE tel_listen6 = INVALID_SOCKET;
+#endif /* IP_V6 */
+
+#ifdef MINI_TCP
+#include "msring.h"
+/*
+ * struct sockaddr_in   tel_sin;
+ * SOCKTYPE tel_listen = INVALID_SOCKET;
+ */
+#ifndef TEL_NEWQLEN
+#define TEL_NEWQLEN     4      /* max # buffered new sessions */
+#endif
+
+static struct msring tel_msring;
+static M_SOCK tel_msring_buf[TEL_NEWQLEN + 1];
+#endif   /* MINI_TCP */
+
+#ifndef TEL_INICHE_IP
+struct WSAData WSData;
+int   StartupError=-1;
+HWND ViewhWnd=0;
+char *   prompt= "INET> " ;
+#endif   /* ndef TEL_INICHE_IP */
+
+/* Initialize the global variables */
+
+struct TelGlobals tglob =
+{
+   TEL_RECV_BUF_SIZE  ,
+   TEL_SEND_BUF_SIZE  ,
+   TELNET_PORT        ,
+   TEL_MAX_LOGIN_TRIES,
+   TEL_IDLE_TIME      ,
+};
+
+/* later - read these from NVRAM also */
+
+/* Default values for various options of a telnet connection */
+
+struct TelOptionList tel_opt_list   =  {
+     {  TEL_BINARY  ,  TRUE, FALSE,   FALSE,   FALSE,   FALSE,   FALSE,   FALSE },
+     {  TEL_ECHO    ,  TRUE, FALSE,   FALSE,   TRUE,    TRUE,    FALSE,   FALSE },
+     {  TEL_SGA     ,  TRUE, FALSE,   FALSE,   TRUE,    TRUE,    FALSE,   FALSE },
+     {  TEL_STATUS  ,  TRUE, FALSE,   FALSE,   TRUE,    TRUE,    FALSE,   FALSE },
+};
+
+#ifdef MINI_TCP
+/* telnet command connection callback */
+#ifndef SUPERLOOP
+extern TK_OBJECT(to_telnetsrv);
+#endif   /* not SUPERLOOP */
+int
+tel_cmdcb(int code, M_SOCK so, void * data)
+{
+   int e = 0;
+
+   switch(code)
+   {
+   case M_OPENOK:          /* new socket is connected */
+      msring_add(&tel_msring, so);
+      break;
+   case M_CLOSED:          /* TCP lost socket connection */
+      break;               /* let stale conn timer catch these */
+   case M_RXDATA:          /* received data packet, let recv() handle it */
+   case M_TXDATA:          /* ready to send more, loop will do it */
+      e = -1;        /* return nonzero code to indicate we don't want it */
+      break;
+   default:
+      dtrap();             /* not a legal case */
+      return 0;
+   }
+
+#ifdef SUPERLOOP
+#ifndef NINI_TCP
+   tel_check();            /* give loop a spin */
+#endif
+#else /* multitasking */
+   TK_WAKE(&to_telnetsrv);    /* wake server task */
+#endif
+
+   USE_VOID(data);
+   return e;
+}
+#endif /* MINI_TCP */
+
+
+#ifndef MINI_TCP
+
+/* FUNCTION: telnet_listen()
+ * 
+ * Opens a listen socket on TELNET port. Works for IPv4 or IPv6
+ *
+ * PARAM1: domain - AF_INET or AF_INET6
+ *
+ * RETURNS: listen socket if OK, else INVALID_SOCKET
+ */
+
+SOCKTYPE
+telnet_listen(int domain, struct sockaddr * sin, int sin_size)
+{
+   int      e;
+   SOCKTYPE sock;
+
+   /* start up an TELNET port listen */
+   sock = t_socket(domain, SOCK_STREAM, 0);
+   if (sock == INVALID_SOCKET)
+      return INVALID_SOCKET;
+
+#ifdef IP_V4
+   if(domain == AF_INET)
+      ((struct sockaddr_in *)sin)->sin_family = domain;
+#endif
+
+#ifdef IP_V6
+   if(domain == AF_INET6)
+      ((struct sockaddr_in6 *)sin)->sin6_family = domain;
+#endif
+
+   e = t_bind(sock, (struct sockaddr*)sin, sin_size);
+   if (e)
+   {
+      e = t_errno(sock);
+      dprintf("error %d binding telnet server\n", e);
+      return INVALID_SOCKET;
+   }
+
+   e = t_listen(sock, 5);
+   if (e)
+   {
+      e=t_errno(sock);
+      dprintf("error %d starting listen on telnet server\n", e);
+      return INVALID_SOCKET;
+   }
+   return sock;
+}
+#endif   /* not MINI_TCP */
+
+
+
+/* FUNCTION: tel_init()
+ * 
+ * Does the initialization for telnet. Opens a listen socket on TELNET port.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: SUCCESS , else error number
+ */
+
+int tel_init()
+{
+
+#ifdef INCLUDE_NVPARMS  
+   tel_nvram_init();
+#endif /* INCLUDE_NVPARMS  */
+
+
+#ifdef TEL_INICHE_IP
+
+#ifdef MINI_TCP
+   {
+      int e;
+      msring_init(&tel_msring, tel_msring_buf,
+               sizeof(tel_msring_buf) / sizeof(tel_msring_buf[0]));
+      tel_sin.sin_addr.s_addr = htonl(INADDR_ANY);
+      tel_sin.sin_port        = htons(tglob.tel_port);   /* telnet port */
+      tel_listen = m_listen(&tel_sin, tel_cmdcb, &e);
+      if (tel_listen == INVALID_SOCKET)
+      {
+         dprintf("error %d starting listen on telnet server\n", e);
+      }
+   }
+#else /* BSD-ish sockets */
+
+#ifdef IP_V4
+   tel_sin.sin_addr.s_addr = htonl(INADDR_ANY);
+   tel_sin.sin_port        = htons(tglob.tel_port);   /* telnet port */
+   tel_listen = telnet_listen(AF_INET, 
+            (struct sockaddr *)(&tel_sin), sizeof(tel_sin) );
+   if(tel_listen == INVALID_SOCKET)
+      return TEL_INIT_CANT_OPEN_SOCKET;
+
+   t_setsockopt(tel_listen, 0, SO_NBIO, NULL, 0);     /* make non-blocking */
+#endif   /* IP_V4 */
+
+#ifdef IP_V6
+   IP6CPY(&tel_sin6.sin6_addr, &ip6unspecified) ;
+   tel_sin6.sin6_port        = htons(tglob.tel_port);   /* telnet port */
+   tel_listen6 = telnet_listen(AF_INET6,
+            (struct sockaddr *)(&tel_sin6), sizeof(tel_sin6) );
+   if(tel_listen6 == INVALID_SOCKET)
+      return TEL_INIT_CANT_OPEN_SOCKET;
+
+   t_setsockopt(tel_listen6, 0, SO_NBIO, NULL, 0);    /* make non-blocking */
+#endif   /* IP_V6 */
+
+#endif   /* MINI_TCP or not */
+
+ 
+   /* Install telnet menu into system menus */
+   tel_menu_init();
+
+#else    /* Demo using Winsock stack */
+
+   StartupError = WSAStartup(0x0101,&WSData);
+   if ( StartupError )
+   {
+      return TEL_INIT_STARTUP_ERR ;
+   }
+
+   e = WSAAsyncSelect(tel_listen,ViewhWnd,WM_TELNET_MSG,FD_ACCEPT);
+   if ( e != 0 )
+   {
+      e = WSAGetLastError();
+      dprintf("error %s starting listen on telnet server.\n",e);
+      return TEL_INIT_ASYNCSELECT ;
+   }
+
+   e=setsockopt(tel_listen,SOL_SOCKET,SO_RCVBUF,
+      (char far *)&tglob.tel_recv_buf_size, sizeof(int));
+   if ( e != 0 )
+   {
+      e = WSAGetLastError();
+      dprintf("error %s setting RCVBUF on telnet socket \n",e);
+      return TEL_INIT_RCVBUF ;
+   }
+
+   e=setsockopt(tel_listen,SOL_SOCKET,SO_SNDBUF,
+      (char far *)&tglob.tel_send_buf_size, sizeof(int));
+   if ( e != 0 )
+   {
+      e = WSAGetLastError();
+      dprintf("error %s setting SNDBUF on telnet socket \n",e);
+      return TEL_INIT_SNDBUF ;
+   }
+#endif   /* else of ifdef TEL_INICHE_IP */
+
+   tel_stats.conn_opened=0;
+   tel_stats.conn_closed=0;
+
+#ifdef TEL_USERAUTH
+   /* If user authentication is enabled, then add user,password info */
+   TEL_ADD_USER("guest", "guest", NULL);
+   TEL_ADD_USER("root",  "root",  NULL);
+#endif
+
+   return SUCCESS ;
+}
+
+/* FUNCTION: tel_nvram_init()
+ * 
+ * This function reads the values from Non-volatile RAM (nvram)
+ * and initializes global variables with those values.
+ * Most of the global variables involved can't have a value
+ * of 0. So if the nvram value is 0, don't use it.
+ *
+ * PARAM1: none
+ *
+ * REMARKS: For InterNiche TCP/IP stack, nvram parameters are
+ * stored in a file ( for eg. webport.nv ). During initialization,
+ * values would have been read into the nvram structure(nvparms.h).
+ * So we just have to use those values.
+ * Note       : This function is called during tel_init() after all other
+ * tel_*_init() calls, so that nvram values override the
+ * default values.
+ *
+ * RETURNS: SUCCESS or error code.
+ */
+
+#ifdef INCLUDE_NVPARMS  
+int 
+tel_nvram_init(void)
+{
+   /* So the following code is included only when an NVFS exists. */
+
+   if ( telnet_nvparms.tel_recv_buf_size > 0 )
+      tglob.tel_recv_buf_size = telnet_nvparms.tel_recv_buf_size ;
+
+   if ( telnet_nvparms.tel_send_buf_size > 0 )
+      tglob.tel_send_buf_size = telnet_nvparms.tel_send_buf_size ;
+
+   if ( telnet_nvparms.tel_port > 0 )
+      tglob.tel_port = telnet_nvparms.tel_port ;
+
+   if ( telnet_nvparms.tel_max_login_tries > 0 )
+      tglob.tel_max_login_tries = telnet_nvparms.tel_max_login_tries ;
+
+   if ( telnet_nvparms.tel_idle_time > 0 )
+      tglob.tel_idle_time = telnet_nvparms.tel_idle_time ;
+
+   return SUCCESS ;
+}
+#endif /* INCLUDE_NVPARMS */
+
+
+/* FUNCTION: tel_start_timer()
+ * 
+ * PARAM1: unsigned long *timer - Pointer to value to hold timer ( OUT )
+ *
+ * REMARKS: We will have this function for portability reasons.
+ *
+ * RETURNS: none
+ */
+
+void
+tel_start_timer(unsigned long * timer)
+{
+#ifdef TEL_INICHE_IP
+   u_long   current_clock_tick   =  cticks   ;
+#else
+   u_long   current_clock_tick   =  (u_long)clock()   ;
+#endif
+
+   *timer=current_clock_tick;
+}
+
+
+/* FUNCTION: tel_check_timeout()
+ * 
+ * Compares the CURRENT TICKS with the passed values
+ *
+ * PARAM1: unsigned long timer - Timer ( In )
+ * PARAM2: u_long interval - Interval in seconds
+ *
+ * REMARKS: We will have this function for portability reasons.
+ *
+ * RETURNS: SUCCESS if timeout, error FAILURE
+ */
+
+#ifdef  TEL_SESS_TIMEOUT
+
+int
+tel_check_timeout(unsigned long timer, u_long interval)
+{
+#ifdef TEL_INICHE_IP
+   int   ticks_per_sec  =  TPS   ;
+   u_long   current_clock_tick   =  cticks   ;
+#else
+   int   ticks_per_sec  =  CLOCKS_PER_SEC ;
+   u_long   current_clock_tick   =  (u_long)clock()   ;
+#endif
+
+   if ( interval * ticks_per_sec + timer <= current_clock_tick )
+   {
+      return SUCCESS ;
+   }
+
+   return FAILURE ;
+}
+#endif /* TEL_SESS_TIMEOUT */
+
+
+/* FUNCTION: tel_cleanup()
+ * 
+ * Does the cleanup for telnet. Closes all open sockets,
+ * and other stuff.
+ *
+ * PARAM1: none
+ *
+ * RETURNS: -
+ */
+
+void 
+tel_cleanup()
+{
+   TEL_CONN temp_conn;
+   TEL_CONN next_conn;
+
+#ifdef IP_V4
+   if(tel_listen)
+      sys_closesocket(tel_listen);
+#endif
+#ifdef IP_V6
+   if(tel_listen6)
+      sys_closesocket(tel_listen6);
+#endif
+
+   /* Close all the open telnet sessions */
+   temp_conn=telq;
+
+   while ( temp_conn != NULL )
+   {
+      next_conn=temp_conn->next;
+
+      /* Do cleanup at telnet layer. Closing socket,
+         removing from queues, freeing memory */
+      tel_delete(temp_conn);
+
+      temp_conn=next_conn;
+   }
+
+#ifndef TEL_INICHE_IP
+   WSACleanup();
+#endif
+
+}
+
+/* FUNCTION: tel_accept()
+ * 
+ * Accept on the blocking telnet socket. Caller should already 
+ * have determined that accept will succedd via a call to select(). 
+ * This routine is designed to support eigther v4 or v6 sockets.
+ *
+ * PARAM1: socket to accept on
+ * PARAM2: size of sockaddr (v4 or v6)
+ *
+ * RETURNS: -
+ */
+
+#ifndef MINI_TCP
+void
+tel_accept(SOCKTYPE listensock, int size_sockaddr)
+{
+   SOCKTYPE temp_sock;
+   struct   sockaddr client;  /* generic v4/v6 sockaddr */
+   int      sizep;
+   int      err;
+
+   /* got a connect to server listen */
+   sizep = size_sockaddr;
+   temp_sock = t_accept(listensock, (struct sockaddr *)&client, &sizep);
+
+   if ( temp_sock != INVALID_SOCKET )
+   {
+      tel_connection(temp_sock);
+   }
+   else
+   {
+      err = t_errno(listensock);
+      if(err != EWOULDBLOCK)
+         dprintf("telnet accept err %d\n", err);
+   }
+   return;
+}
+#endif   /* MINI_TCP */
+
+/* tel_check() re-entrancy protection */
+int      inside_tel_check  =  0;
+
+
+/* FUNCTION: tel_check()
+ * 
+ * See if we have a new connection pending. And do processing
+ * for each of the open connections.
+ *
+ * PARAM1: void
+ *
+ * RETURNS: -
+ */
+
+#ifdef MINI_TCP
+
+/* connect is handled by callback, so tel_check is minimal here */
+void tel_check(void)
+{
+   M_SOCK so;
+
+   if ( tel_listen == INVALID_SOCKET )
+      return ;
+
+   while(msring_del(&tel_msring, &so) == 0)
+   {
+      if(tel_connection(so) == 0)
+      {
+         dprintf("telnet connection error\n");
+         continue;
+      }
+      m_ioctl(so, SO_NONBLOCK, NULL);   /* make socket non-blocking */
+   }
+
+   tel_loop();
+}
+
+#else   /* not MINI_TCP */
+
+void tel_check(void)
+{
+
+#ifdef IP_V4
+#ifndef IP_V6     /* V4 only */
+   if(tel_listen == INVALID_SOCKET )
+      return ;
+#else             /* V4/V6 Dual mode version */
+   if((tel_listen == INVALID_SOCKET ) && 
+      (tel_listen6 == INVALID_SOCKET ))
+   {
+      return ;
+   }
+#endif   /* IP_V6 */
+#endif   /* IP_V4 */
+#ifdef IP_V6      /* V6 only */
+   if(tel_listen6 == INVALID_SOCKET )
+      return ;
+#endif   /* IP_V6 */
+
+   /* don't recurse into this function */
+   if (inside_tel_check)
+      return;
+
+   inside_tel_check++;
+
+#ifdef BLOCKING_APPS  /* use blocking select to drive server app */
+   {
+      fd_set tl_fdrecv;    /* fd_set arrays */
+      TEL_CONN tl;
+      int   events;        /* return from select() */
+      int   recvs = 0;     /* number of entries in each array */
+
+#ifdef USE_FDS
+      FD_ZERO(&tl_fdrecv);
+#else
+      MEMSET(&tl_fdrecv, 0, sizeof(fd_set));
+#endif  /* USE_FDS */
+
+#ifdef IP_V4
+      /* use the recv array to detect new connections */
+      FD_SET(tel_listen, &tl_fdrecv);
+      recvs++;
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      /* use the recv array to detect new connections */
+      FD_SET(tel_listen6, &tl_fdrecv);
+      recvs++;
+#endif   /* IP_V6 */
+
+      /* loop through TEL_CONN structs building read & write 
+       * arrays for select 
+       */
+      for (tl = telq; tl; tl = tl->next)
+      {
+#ifdef USE_FDS
+         /* error checking is done in FD_SET() */
+         FD_SET(tl->sock, &tl_fdrecv);
+         recvs++;
+#else
+         if (recvs >= FD_SETSIZE) /* too many open connections for select */
+         {
+            dtrap(); /* out of resource, tell engineer? */
+            break;
+         }
+         else
+         {
+            FD_SET(tl->sock, &tl_fdrecv);
+            recvs++;
+         }
+#endif  /* USE_FDS */
+      }
+       /* block until one of the sockets has activity. */
+#ifndef  TEL_SESS_TIMEOUT    
+      events = t_select(&tl_fdrecv, (fd_set *)NULL, (fd_set *)NULL, -1);
+#else    /* session is closed with timeout */
+      events = t_select(&tl_fdrecv, (fd_set *)NULL, (fd_set *)NULL,
+                        TEL_IDLE_TIME);  /* enable inactivity timeout */
+#endif   /* TEL_SESS_TIMEOUT */
+
+#ifdef IP_V4
+      if (FD_ISSET(tel_listen, &tl_fdrecv))
+      {
+         tel_accept(tel_listen, sizeof(struct sockaddr_in));
+         events--;
+      }
+#endif   /* IP_V4 */
+#ifdef IP_V6
+      if (FD_ISSET(tel_listen6, &tl_fdrecv))
+      {
+         tel_accept(tel_listen6, sizeof(struct sockaddr_in6));
+         events--;
+      }
+#endif   /* IP_V6 */
+
+      if (events <= 0)   /* connects were only sockets */
+      {
+         inside_tel_check--;
+         return;
+      }
+   }
+
+
+#else /* not BLOCKING_APPS, poll non-blocking sockets */
+
+#ifdef IP_V4
+   tel_accept(tel_listen, sizeof(struct sockaddr_in));
+#endif   /* IP_V4 */
+#ifdef IP_V6
+   tel_accept(tel_listen6, sizeof(struct sockaddr_in6));
+#endif   /* IP_V6 */
+
+#endif      /* BLOCKING_APPS */
+
+   inside_tel_check--;
+   tel_loop();
+}
+#endif   /* MINI_TCP */
+
+
+
+
+/* FUNCTION: tel_proc_subcmd()
+ * 
+ * Process the sub-negotiation command
+ * The command starts from the next byte following IAC-SB.
+ * Length does not include IAC-SB and IAC-SE chars.
+ *
+ * PARAM1: TEL_CONN tconn - Pointer to telnet connection (IN)
+ * PARAM2: u_char *cmd - Pointer to command (IN)
+ * PARAM3: int cmd_len - Length of command (IN)
+ *
+ * REMARKS: Support for subnegotiation of options can be added here.
+ *
+ * RETURNS: SUCCESS or error number
+ */
+
+int
+tel_proc_subcmd(TEL_CONN tconn, u_char * cmd, int cmd_len)
+{
+   USE_ARG(tconn);
+   USE_ARG(cmd);
+   USE_ARG(cmd_len);
+   return SUCCESS ;
+}
+
+
+#ifndef TEL_INICHE_IP
+
+
+/* FUNCTION: sys_send()
+ * 
+ * Do a TCP send() on WinSock.
+ *
+ * PARAM1: SOCKTYPE s
+ * PARAM2: char FAR * buf
+ * PARAM3: int len
+ * PARAM4: int flags
+ *
+ * RETURNS: 
+ */
+
+int 
+sys_send(SOCKTYPE s, char FAR * buf, int len, int flags)
+{
+   int   e;
+   int   counter  =  0;
+   int   sent  =  0;
+#define  WIN_LOOPCOUNT  100
+
+   if (len == 0)
+   {
+      dtrap();
+      return 0;
+   }
+
+   e = send(s, buf, len, flags);
+   if (e == len) /* If we sent everything, just return */
+      return e;
+
+   /* check if we need to do winmsgloop here - later !! */
+   /* Check what to do when partial send occurs */
+   return e;
+}
+
+
+/* FUNCTION: sys_closesocket()
+ * 
+ * Call the corresponding socket routine to close the
+ * underlying TCP socket.
+ *
+ * PARAM1: SOCKTYPE s - Socket which to be closed (IN)
+ *
+ * REMARKS: This could easily be changed to a #define 
+ *
+ * RETURNS: as per standard
+ */
+
+int
+sys_closesocket(SOCKTYPE s)
+{
+   return(closesocket(s));
+}
+
+
+/* FUNCTION: SocketMsg()
+ * 
+ * Upcall routine from Windows application when some data
+ * has arrived on a particular socket.
+ *
+ * PARAM1: UINT socket - Socket on which data has arrived (IN)
+ * PARAM2: LONG params - More info. (IN)
+ *
+ * RETURNS: Nothing
+ */
+
+void
+SocketMsg(UINT socket, LONG params)
+{
+   tel_check();
+}
+
+#endif   /* ndef TEL_INICHE_IP */
+
+
+#ifndef SUPERLOOP
+
+TK_OBJECT(to_telnetsrv);
+TK_ENTRY(tk_telnetsrv);
+long telnetsrv_wakes = 0;
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Create task entries for all optional add-on apps
+ */
+struct inet_taskinfo telnettask = {
+      &to_telnetsrv,
+      "telnet server",
+      tk_telnetsrv,
+      TK_TELNETSRV_TPRIO,
+      TK_TELNETSRV_SSIZE,
+};
+
+/* The application thread works on a "controlled polling" basis: 
+ * it wakes up periodically and polls for work.
+ *
+ * The FTP task could aternativly be set up to use blocking sockets,
+ * in which case the loops below would only call the "xxx_check()"
+ * routines - suspending would be handled by the TCP code.
+ */
+
+/* FUNCTION: tk_telnetsrv
+ * 
+ * PARAM1: n/a
+ *
+ * RETURNS: n/a
+ */
+
+TK_ENTRY(tk_telnetsrv)
+{
+   int err;
+
+   while (!iniche_net_ready)
+      TK_SLEEP(1);
+
+   err = tel_init();
+   if( err == SUCCESS )
+   {
+      exit_hook(tel_cleanup);
+   }
+   else
+   {
+      dtrap();    /* tel_init()  shouldn't ever fail */
+   }
+
+   for (;;)
+   {
+      tel_check();         /* will block on select */
+      tk_yield();          /* give up CPU in case it didn't block */
+      telnetsrv_wakes++;   /* count wakeups */
+
+      if (net_system_exit)
+         break;
+   }
+   TK_RETURN_OK();
+}
+
+#endif /* not SUPERLOOP */
+
+
+#ifdef INCLUDE_NVPARMS
+/* Please see nvparms.h and nvparms.c regarding the usage of 
+ * the following datatypes and functions.
+ */
+
+struct nvparm_info telnet_nvformats[] = 
+{
+   {"telnet recv buf: %u\n"       , NVINT, NVBND_NOOP, \
+    &telnet_nvparms.tel_recv_buf_size  , NULL, }, 
+
+   {"telnet send buf: %u\n"       , NVINT, NVBND_NOOP, \
+    &telnet_nvparms.tel_send_buf_size  , NULL, }, 
+
+   {"telnet port: %u\n"           , NVINT, NVBND_NOOP, \
+    &telnet_nvparms.tel_port           , NULL, }, 
+
+   {"telnet max login tries: %u\n", NVINT, NVBND_NOOP, \
+    &telnet_nvparms.tel_max_login_tries, NULL, }, 
+
+   {"telnet idle time: %u\n"      , NVINT, NVBND_NOOP, \
+    &telnet_nvparms.tel_idle_time      , NULL, }, 
+};
+
+#define NUMTELNET_FORMATS  \
+        (sizeof(telnet_nvformats)/sizeof(struct nvparm_info))
+
+/* FUNCTION: telnet_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int telnet_nvset(NV_FILE * fp)
+{
+int i = 0;
+
+   nv_fprintf(fp, telnet_nvformats[i++].pattern, \
+              telnet_nvparms.tel_recv_buf_size  );
+
+   nv_fprintf(fp, telnet_nvformats[i++].pattern, \
+              telnet_nvparms.tel_send_buf_size  );
+
+   nv_fprintf(fp, telnet_nvformats[i++].pattern, \
+              telnet_nvparms.tel_port           );
+
+   nv_fprintf(fp, telnet_nvformats[i++].pattern, \
+              telnet_nvparms.tel_max_login_tries);
+
+   nv_fprintf(fp, telnet_nvformats[i++].pattern, \
+              telnet_nvparms.tel_idle_time      );
+
+   return 0;
+} 
+
+struct nvparm_format telnet_format = 
+{
+   NUMTELNET_FORMATS,
+   &telnet_nvformats[0],
+   telnet_nvset,
+   NULL,
+};
+
+#endif   /* INCLUDE_NVPARMS */
+
+
+/* FUNCTION: prep_telnet()
+ *
+ * PARAMS: NONE
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+int prep_telnet(void)
+{
+int e = 0;
+
+#ifdef INCLUDE_NVPARMS
+   e = install_nvformat(&telnet_format, nv_formats);
+
+   if(e)
+   {
+      dprintf("unable to install Telnet NVPARMS, reconfigure nv_formats[]\n");
+      dtrap();
+   }
+#endif   /* INCLUDE_NVPARMS */
+   return e;
+}
+
+#endif   /* #ifdef TELNET_SVR */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.h b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.h
new file mode 100644
index 0000000..06290d4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/telnet/telport.h
@@ -0,0 +1,220 @@
+/*
+ * FILENAME: telport.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: TELNET
+ *
+ *
+ * PORTABLE: no
+ */
+
+/* telport.h - Telnet Server port definitions 
+ */
+#ifndef TELPORT_H
+#define TELPORT_H                1
+
+
+/* List of hash defines which control what the code does */
+
+#define TEL_USERAUTH             1
+#define TEL_INICHE_IP            1 
+
+#ifdef NOTDEF
+#define TEL_SHOW_MSG             1
+#define TEL_SESS_TIMEOUT         1
+#endif /* NOTDEF */
+
+#ifdef TEL_INICHE_IP
+#define TEL_MENU                 1  /* enabled for InterNiche stack */
+#endif
+
+/* Meanings of various Hash defines 
+ *
+ * TEL_INICHE_IP: If this is defined, then TELNET implementation is 
+ * tightly bound to InterNiche's TCP/IP * stack. This affects 
+ * routing tables and various other things. 
+ * 
+ * TEL_SHOW_MSG: If this is defined, then description will be shown 
+ * for error messages and for various options which were negotiated. 
+ * This option can be disabled if running short of memory. 
+ * 
+ * TEL_USERAUTH: If login-password scenario is desired, then this 
+ * option should be enabled. If this option is disabled, user 
+ * directly starts working at the prompt 
+ *
+ * TEL_SESS_TIMEOUT: If this is defined,then TELNET Server will 
+ * close a TELNET session if there 
+ * has not been any activity for TEL_IDLE_TIME seconds. 
+ *
+ * TEL_MENU: Use this to enable the menu commands. The default 
+ * implementation provides use of menu commands on InterNiche's
+ * command prompt. It is done in tel_menu_init(). If menus are to be
+ * used with some other architecture, then customization can be done
+ * in tel_menu_init().
+ */
+
+
+#ifdef TEL_INICHE_IP    /* if we are using Local stack */
+
+#include "ipport.h"
+#include "tcpapp.h"
+#include "nvparms.h"
+#include "menu.h"
+
+
+char *    print_ipad(unsigned long);
+#define     INET_NTOA         print_ipad
+#define     stat_printf       printf
+#define     info_printf(x)
+
+#define     INADDR_NONE       0xffffffff  /* usually part of winsock.h */
+#define     FAILURE                 -1
+
+#define     TEL_ALLOC(size)   npalloc(size) 
+#define     TEL_FREE(ptr)     npfree(ptr)
+
+#define     tel_exec_cmd      do_command
+
+#define     SOCKET            SOCKTYPE
+
+#else
+
+#include <windows.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <memory.h>
+#include <winsock.h>
+#include <time.h>
+#include <string.h>
+#include "in_utils.h"
+
+#define  dtrap();                   _asm  {  int   3  }  ;
+#define  INET_NTOA(X)               inet_ntoa(*(struct   in_addr*)&X)
+#define  WM_TELNET_MSG              WM_USER+102
+#define  USE_ARG(X)                 (X++)
+
+extern   int dprintf(const char * format, ...);
+#define  stat_printf dprintf
+/*#define info_printf dprintf */
+
+#define  info_printf
+
+/* struct in_addr is a union of 3 fields, third being u_long. Hence 
+ * in the above #define, we are casting from u_long to pointer to 
+ * u_long to pointer to struct in_addr to contents of struct in_addr 
+ * I don't like doing it, but have to save 1 extra function call
+ */
+/* now do it the way the CMU snmp code likes it: */
+typedef   unsigned long  ip_addr;
+
+/* map memory routines to standard lib */
+#define  MEMCPY(dst,src,size)    memcpy(dst,src,size)
+#define  MEMMOVE(dst,src,size)   memmove(dst,src,size)
+#define  MEMSET(ptr,val,size)    memset(ptr,val,size)
+#define  MEMCMP(p1,p2,size)      memcmp(p1,p2,size)
+
+#define  TEL_ALLOC(size)   calloc(1,size)   
+#define  TEL_FREE(ptr)     free(ptr)
+
+#define  SUCCESS                 0
+#define  FAILURE                 -1
+
+#ifndef TRUE
+#define  TRUE                    -1
+#endif
+
+#ifndef FALSE
+#define  FALSE                   0
+#endif
+
+#ifndef   NULL
+#define     NULL  ((void*)0)
+#endif   /* NULL */
+
+#define     tel_exec_cmd      do_command
+
+#endif      /* else of TEL_INICHE_IP */
+
+
+#define  TEL_NV_FILE   "telnet.nv"
+
+
+#ifdef TEL_INICHE_IP
+
+u_long inet_addr(char far * str);
+extern   int    udp_send(unshort /*fport*/, unshort   /*lport*/, PACKET);
+extern   PACKET udp_alloc(int, int);
+extern   void   pk_free(PACKET);
+extern   char * nextcarg(char * arg);  /* next comma-delimited arg */
+
+#include "menu.h"
+
+#else    /* Not Iniche stack, assume Winsock */
+
+/* Most Winsock recv() implementations are slightly goofy, so... */
+/* winsock functions we intercept: */
+
+int      sys_send        (SOCKET s, char FAR * buf, int len, int flags);
+int      sys_closesocket (SOCKET s);
+#define  sys_errno(X)      WSAGetLastError()
+#define  sys_accept        accept
+#define  sys_recv          recv
+#define  sys_bind          bind
+#define  sys_socket        socket
+#define  sys_listen        listen
+
+#define  SYS_EWOULDBLOCK   WSAEWOULDBLOCK
+
+extern   HWND  ViewhWnd;
+void        SocketMsg(UINT socket, LONG params);
+typedef unsigned char u_char;
+
+
+#endif   /* TEL_INICHE_IP */
+
+
+
+#ifdef  TEL_USERAUTH
+#include "userpass.h"
+
+#ifndef MAX_USERLENGTH
+#define  MAX_USERLENGTH 32
+#endif
+
+#ifndef TELNET_USER
+#define  TELNET_USER    4
+#endif 
+
+#define  TEL_CHECK_PERMIT(X,Y)   check_permit(X,Y,TELNET_USER,NULL)
+#define  TEL_ADD_USER            add_user
+
+/* Configurable limit on max number of telnet sessions.  Setting this value to 0 or
+ * -1 results in no limitation on number of sessions.  The default setting is 32.
+ */
+#ifndef  MAX_TELNET_SESS
+#define  MAX_TELNET_SESS 32
+#endif   /* MAX_TELNET_SESS */
+#endif   /* TEL_USERAUTH */
+
+/* Telnet Server related non-volatile parameters. Please see nvparms.h 
+ * and nvparms.c regarding the usage of the following structure.
+ */
+#ifdef TEL_INICHE_IP
+#ifdef INCLUDE_NVPARMS
+struct telnet_nvparam
+{
+   int tel_recv_buf_size  ; 
+   int tel_send_buf_size  ; 
+   int tel_port           ; 
+   int tel_max_login_tries; 
+   int tel_idle_time      ; 
+};
+#endif   /* INCLUDE_NVPARMS */
+#endif   /* TEL_INICHE_IP */
+
+#endif   /* TELPORT_H  */
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftp.h b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftp.h
new file mode 100644
index 0000000..342a8eb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftp.h
@@ -0,0 +1,186 @@
+/* tftp.h
+
+   Contains structures of TFTP packet headers and such. 
+
+   Copyright 1998 by InterNiche Technologies Inc. All rights reserved.
+   Copyright 1992 by NetPort Software.
+   Copyright 1986 by Carnegie Mellon
+   Copyright 1984 by the Massachusetts Institute of Technology
+*/
+
+#ifndef _TFTP_H_
+#define _TFTP_H_ 1
+
+
+#define  NORMLEN     512   /* normal length of received packet */
+
+/* read or write request packet */
+struct tfreq {
+   unshort    tf_op;       /* 1 (read) or 2 (write) */
+   /* this is followed by two variable-length zero-terminated
+    * octet strings: one for the filename, one for the mode.
+    */
+};
+
+/* data packet */
+struct tfdata {
+   unshort   tf_op;        /* always 3 */
+   unshort   tf_block;
+   char      tf_data[NORMLEN];
+};
+
+/* structure of an ack packet */
+struct   tfack {
+   unshort   tf_op;        /* would be 4 */
+   unshort   tf_block;
+};
+
+/* error packet */
+struct tferr {
+   unshort   tf_op;        /* would be 5 */
+   unshort    tf_code;
+   char      tf_err[1]; };
+
+/* TFTP added definitions */
+#ifndef PUT
+#define  GET   1
+#define  PUT   2
+#endif
+
+#define  ASCII       1
+#define  OCTET       2
+#define  TEST        3
+
+/* TFTP opcodes */
+#define  TF_RRQ      1     /* read  request */
+#define  TF_WRQ      2     /* write request */
+#define  TF_DATA     3     /* data packet */
+#define  TF_ACK      4     /* acknowledgement packet */
+#define  TF_ERROR    5     /* error packet */
+
+/* TFTP error codes */
+#define  ERRTXT      0     /* see the enclosed text */
+#define  FNOTFOUND   1     /* file not found */
+#define  ACCESS      2     /* access violation */
+#define  DISKFULL    3     /* don't even ask. */
+#define  ILLTFTP     4     /* illegal TFTP operation */
+#define  BADTID      5     /* unkown transfer ID */
+#define  FEXISTS     6     /* file already exists */
+#define  NOUSER      7     /* no such user */
+
+extern char * tferrors[8]; /* text for the above errors */
+
+/* TFTP states */
+#define  DATAWAIT    1     /* GET: sent req; waiting for data */
+#define  ACKWAIT     2     /* PUT: sent data; waiting for ack */
+#define  DEAD        3     /* a killed connection, waiting for cleanup */
+#define  TIMEOUT     4     /* connection timed out */
+#define  RCVERR      5     /* connection got error from other side */
+#define  RCVACK      6     /* PUT: got ack, sending data */
+#define  RCVDATA     7     /* GET: sent ack; waiting for next block */
+#define  RCVLASTDATA 8     /* GET: received last block of file (A block > 512 bytes) */
+#define  SENTLAST    9     /* PUT: sent last packet, awaiting ack */
+#define  TERMINATED  10    /* PUT: sent last packet & and got ack for it */
+
+#define  TFTPPORT    69    /* TFTP's well known port */
+
+struct tftpbuf {
+   char * data;      /* tftpudp managed buffer, to support zero-copy */
+   unsigned dlen;    /* length of valid data in buffer, 0 if none */
+   void * udp_use;   /* packet handle for UDP api to use */
+};
+
+typedef struct tftpbuf * TFTPBUF;
+
+/* The TFTP connection structure. Contains connection info, and data for
+   timeout calculations. */
+
+struct tfconn {
+   struct tfconn * next;      /* queue link */
+   void*       tf_conn;       /* NetPort UDPCONN handle or socket */
+   VFILE *     tf_fd;         /* file descriptor for xfer */
+   struct tftpbuf   tf_inbuf; /* Buffer for file data rcv */
+   struct tftpbuf   tf_outbuf;/* Buffer for file data xmit */
+   unsigned    tf_lastlen;    /* length of last sent pkt */
+   unsigned    tf_flen;       /* bytes to send in next data send */
+   unshort     tf_expected;   /* most recent full processed block ( ack & all) */
+   ip_addr     tf_fhost;      /* foreign host */
+   unshort     tf_fport;      /* foreign port */
+   unshort     tf_lport;      /* local port */
+   unsigned    tf_state;      /* state of connection */
+   int         tf_tries;      /* # of retries already done */
+   unsigned    tf_mode;       /* mode = OCTET, [net]ASCII, ... */
+   unsigned    tf_dir;        /* direction of the transfer */
+   long        tf_size;       /* # of bytes transferred */
+   unsigned    tf_rcv;        /* # of packets received */
+   unsigned    tf_snt;        /* # of packets sent */
+   unsigned    tf_ous;        /* # of out of sequence packets */
+   unsigned    tf_tmo;        /* # of timeouts */
+   unsigned    tf_rsnd;       /* # of resends */
+   u_long      tf_start;      /* start time of transfer */
+   u_long      tf_srtt;       /* average measured round trip time */
+   u_long      tf_rt;         /* current timeout */
+   u_long      tf_sent;       /* time that pkt was sent */
+   u_long      tf_tick;       /* ctick for next event timeout */
+   int         tf_NR;         /* number rexmissions of this pkt */
+   int         tf_NR_last;    /* "   "   " of prev pkt */
+   /* callback at end of transfer */
+   int (* callback)(int status, struct tfconn *, char * msg);
+};
+
+extern struct tfconn * tftp_conns;   /* list of active connections */
+
+#define TFC_SUCCESS  0
+#define TFC_ZEROFILE -1    /* tried to send 0 length file */
+#define TFC_DISKFULL -2    /* local disk full (or simlar fault) */
+#define TFC_FOREIGN  -3    /* error from foreign host */
+#define TFC_FILEREAD -4    /* file read error */
+#define TFC_FILEOPEN -5    /* file open error */
+#define TFC_BUFFER   -6    /* buffer alloc error */
+#define TFC_TIMEOUT  -7    /* timed out waiting for peer reply */
+#define TFC_UDPSEND  -8    /* error returned by tftp_udpsend() */
+#define TFC_BADLEN   -9    /* bad data length received from peer */
+#define TFC_BADSTATE -10   /* TFTP state machine in unrecognized state */
+
+#define   dos_eof   26   /* control Z */
+
+/* TFTP API entry point to initiate client transfers */
+char *    tftpuse(ip_addr fhost, char *fname, char *rmfile, 
+      unsigned dir, unsigned mode,
+      int (*callback)(int, struct tfconn*, char*) );   /* callback */
+
+struct tfconn * tfmkcn(void);   /* alloc and enqueue tfconn struct */
+
+void   tftprcv(struct tfconn *cn, unshort port);   /* tftp client's packet receive routine */
+void   tftptmo (struct tfconn * cn);   /*   timeout handler   */
+void   tfcleanup(struct tfconn * cn);   /* disconnect, free & dequeue tfconn & members */
+int    tfsndreq(struct tfconn * cn, char * fname);
+void   tfsnderr(struct tfconn * cn, unsigned code, char *text);
+int    tfsndata(struct tfconn * cn);
+void   tf_good (struct tfconn * cn);   /* fixed tmo info (srtt,etc) when OK packet is received */
+int    tf_write(struct tfconn * cn, unsigned len);   /* write next file block to net */
+void   tfkill  (struct tfconn * cn);
+int    tfsndack(struct tfconn * cn);
+void   tf_full (struct tfconn * cn);
+void   tfdoack (struct tfconn * cn);
+
+extern char *tftplog;
+
+/* server API */
+int   tfsinit(int(*alert)(ip_addr,char*,unshort), 
+         int (*done)(int,struct tfconn *,char*));
+void  tfs_on(void);     /* toggle tftp server ON */
+void  tfs_off(void);    /* toggle tftp server OFF */
+int   tfshnd(ip_addr host, unshort fport, char * udata);
+
+
+/* API to UDP layer - this can map to sockets or other API */
+int   tftp_init(void);
+void* tftp_udplisten(ip_addr fhost, unshort fport, unshort * lport, void *);
+void  tftp_udpbuffer(struct tfconn * cn, int size);
+void  tftp_udpfree(struct tfconn * cn);
+int   tftp_udpsend(struct tfconn *, void * outbuf, int outlen);
+int   tftp_udpclose(void * conn);   /* close socket or UDPCONN */
+
+#endif /*  _TFTP_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpcli.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpcli.c
new file mode 100644
index 0000000..7bef6be
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpcli.c
@@ -0,0 +1,191 @@
+/* tftpcli.c
+ *
+ * Copyright 1998 by InterNiche Technologies Inc. All rights reserved.
+ * Copyright 1995 by NetPort Software.
+ * Copyright 1986 by Carnegie Mellon
+ * Copyright 1984 by the Massachusetts Institute of Technology
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tftpuse(), tfsndreq()
+ *
+ * TFTP client code - uses common code in tftputil.c and udp
+ * interface in tftpudp.c
+ *
+ * PORTABLE: yes
+ *
+*/
+
+#include "tftpport.h"
+
+#ifdef TFTP_CLIENT
+
+#include "tftp.h"
+
+
+/* FUNCTION: tftpuse()
+ *
+ * Entry point for tftp transfers.
+ *
+ * PARAM1: ip_addr            IP address of foreign host
+ * PARAM2: char *             name of local file
+ * PARAM3: char *             name of remote file
+ * PARAM4: unsigned           transfer direction: PUT or GET
+ * PARAM5: unsigned           transfer mode: ASCII or OCTET
+ * PARAM6: int (*)()          transfer "done" callback function
+ *
+ * RETURN: char *             NULL if successful, else error message
+ *
+ * Called from app to initiate a tftp transfer. A user-supplied 
+ * callback function is invoked when the transfer is complete.
+ *
+ * Retuns NULL if transer started without errors, else returns
+ * a pointer to text describing the error.
+ */
+
+char * 
+tftpuse(ip_addr fhost, char *fname, char *rmfile, unsigned dir,
+        unsigned mode, int (*callback)(int, struct tfconn*, char*))
+{
+   struct tfconn * cn;
+
+   cn = tfmkcn();
+   if (cn == (struct tfconn *)NULL)
+      return ("alloc failed");
+
+   cn->tf_mode = mode;
+   cn->tf_start = cticks;
+   cn->tf_fhost = fhost;
+   cn->tf_dir = dir;
+   cn->tf_mode = mode;
+   cn->tf_fport = TFTPPORT;
+   cn->tf_lport = 0;          /* let tftp_udplisten() assign port */
+   cn->tf_fhost = fhost;
+   cn->callback = callback;
+
+   /* Open client tftp connection. Note that foreign port is wildcard
+      since server will select it's own when it replys */
+   cn->tf_conn = tftp_udplisten(cn->tf_fhost, 0, &cn->tf_lport, (void*)cn);
+   if (cn->tf_conn == (void *)NULL)
+      return ("Couldn't open UDP connection");
+
+   if (dir == GET) 
+   {
+      if (mode == ASCII)
+         cn->tf_fd = vfopen(fname, "w");
+      else if (mode == OCTET)
+         cn->tf_fd = vfopen(fname, "wb");
+      else 
+         return ("Invalid mode");
+
+      if (cn->tf_fd == (VFILE *)NULL)
+      {
+         cn->tf_state = DEAD;
+         return ("Couldn't open local file");
+      }
+      if (tfsndreq(cn, rmfile) != 0)
+         return "Initial request failed";
+      cn->tf_expected = 1;
+      cn->tf_state = DATAWAIT;
+   }
+   else if (dir == PUT)
+   {
+      if (mode == ASCII)
+         cn->tf_fd = vfopen(fname, "r");
+      else if (mode == OCTET)
+         cn->tf_fd = vfopen(fname, "rb");
+      else 
+         return ("Invalid mode");
+
+      if (cn->tf_fd == (VFILE *)NULL)
+         return ("Couldn't open file to send");
+
+      if (tfsndreq(cn, rmfile) != 0)
+         return "Initial request failed";
+      cn->tf_expected = 0;
+   }
+   else   /* not tftp PUT or GET? */
+   {
+      dtrap();   /* prog error */
+      return ("bad direction parm");
+   }
+
+   return ((char *)NULL);
+}
+
+
+
+/* FUNCTION: tfsndreq()
+ *
+ * Send an initial TFTP client transfer request
+ *
+ * PARAM1: tfconn *           TFTP connection
+ * PARAM2: char *             remote file name
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Build a TFTP read or write request packet and send it.
+ */
+
+int
+tfsndreq(struct tfconn * cn, char * fname)
+{
+   int err;
+   int reqlen;    /* length of tftp request data */
+   TFTPBUF p;
+   struct tfreq *ptreq;
+   char *cp;
+
+   /* calculate request length: 
+    *   size of request header
+    *   + length of filename in octets + NUL
+    *   + length of mode string + NUL
+    */
+   reqlen = sizeof(struct tfreq) + strlen(fname) + 1;
+   if (cn->tf_mode == OCTET)
+      reqlen += 6;   /* for "octet\0" */
+   else if (cn->tf_mode == ASCII)
+      reqlen += 9;   /* for "netascii\0" */
+   else
+   {
+      dtrap();   /* bad mode; prog error */
+      return FALSE;
+   }
+
+   tftp_udpbuffer(cn, reqlen);
+   if (cn->tf_outbuf.data == NULL)
+      return ENP_NOBUFFER;
+   p = &cn->tf_outbuf;
+   ptreq = (struct tfreq *)p->data;
+
+   if (cn->tf_dir == GET) 
+      ptreq->tf_op = TF_RRQ;
+   else if (cn->tf_dir == PUT) 
+      ptreq->tf_op = TF_WRQ;
+   else 
+   {
+      dtrap();
+      return ENP_PARAM;
+   }
+
+   /* point past request header for filename, and copy filename
+    * and transfer mode strings into request */
+   cp = (char*)ptreq + sizeof(ptreq->tf_op);
+   strcpy(cp, fname);
+   cp += strlen(cp) + 1;
+   strcpy(cp, (cn->tf_mode == ASCII) ? "netascii" : "octet");
+
+   err = tf_write(cn, reqlen);
+   if (err == 0)
+      cn->tf_state = ACKWAIT;
+   else
+   {
+      dtrap();   /* Initial request failed? */
+      tfkill(cn);
+   }
+
+   return err;
+}
+
+#endif   /* TFTP_CLIENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpmenu.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpmenu.c
new file mode 100644
index 0000000..ea1e822
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpmenu.c
@@ -0,0 +1,276 @@
+/* tftpmenu.c
+ *
+ * Copyright 1998 by InterNiche Technologies Inc.
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tftp_srv(), tftp_get(), tftp_put(),
+ * ROUTINES: tftpio(), tftp_state(), tfc_done()
+ *
+ * menu hooks for TFTP 
+ *
+ * PORTABLE: yes
+ *
+ * 1/1/98 - Created. John Bartas
+ */
+
+#include "tftpport.h"   /* TCP/IP, sockets, system info */
+#include "tftp.h"
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "menu.h"
+
+int tftp_srv(void *pio);
+int tftp_get(void *pio);
+int tftp_put(void *pio);
+int tftp_state(void *pio);
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+#ifdef IN_MENUS
+struct menu_op tftpmenu[] = {
+#ifdef TFTP_CLIENT
+   { "tftpc",    stooges,     "tftp client menu" } ,
+   { "tfget",    tftp_get,     "tftp GET a file" } ,
+   { "tfput",    tftp_put,     "tftp PUT a file" } ,
+#endif /* TFTP_CLIENT */
+#ifdef TFTP_SERVER
+#if defined(TFTP_SERVER) && !defined(TFTP_CLIENT)
+   { "tftps",    stooges,      "tftp server menu" } ,
+   { "tfsrv",    tftp_srv,     "Toggle tftp server on/off" } ,
+#else
+   { "tfsrv",    tftp_srv,     "Toggle tftp server on/off" } ,
+#endif
+#endif /* TFTP_SERVER */
+#ifdef NET_STATS
+   { "tfstate",  tftp_state,  "Display tftp stats" } ,
+#endif
+   { NULL },
+};
+#endif /* IN_MENUS */
+
+static char * usage = "usage: tf%s host sourcefile [destfile]\n";
+
+extern char * prompt;   /* system menu prompt */
+
+#ifdef TFTP_SERVER
+extern int tftp_server_on;
+#endif /* TFTP_SERVER */
+
+/* internal routines */
+static int tftpio(int direction, void *pio);
+#ifdef TFTP_CLIENT
+static int tfc_done(int status, struct tfconn *cn, char *msg);
+#endif
+
+void *last_pio;  /* lame attempt at supporting pio */
+
+
+#ifdef TFTP_SERVER
+
+/* FUNCITON: tftp_srv()
+ *
+ * Toggle TFTP Server on/off
+ *
+ * PARAM1: void *             PIO struct
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ */
+
+int
+tftp_srv(void *pio)
+{
+   if (tftp_server_on == TRUE)
+      tfs_off();
+   else
+      tfs_on();
+
+   ns_printf(pio, "tftp server %s\n", tftp_server_on==TRUE?"ON":"OFF");
+
+   return 0;
+}
+
+#endif /* TFTP_SERVER */
+
+
+
+/* FUNCTION: tftp_get()
+ *
+ * Initiate TFTP Client "get" operation
+ *
+ * PARAM1: void *             PIO struct
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Call TFTP client get/put routine to "get" a file.
+ */
+
+int
+tftp_get(void * pio)
+{
+   return tftpio(GET, pio);
+}
+
+
+
+/* FUNCTION: tftp_put()
+ *
+ * Initiate TFTP Client "put" operation
+ *
+ * PARAM1: void *             PIO struct
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Call TFTP client get/put routine to "put" a file.
+ */
+
+int
+tftp_put(void * pio)
+{
+   return tftpio(PUT, pio);
+}
+
+
+
+/* FUNCTION: tftpio()
+ *
+ * Common TFTP Client "get"/"put" processing
+ *
+ * PARAM1: void *             PIO struct
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Initialte a file transfer operation for a TFTP client.
+ */
+
+static int 
+tftpio(int dir, void * pio)
+{
+   ip_addr fhost;
+   char *dfile;      /* source & dest file names */
+   char *sfile;
+   char *hostname = NULL;
+   char *msg;
+   int  e;
+   GEN_IO io = (GEN_IO)pio;
+
+   /* extract args from command buffer */
+   if (io != (GEN_IO)NULL)
+      hostname = nextarg(io->inbuf);
+   if ((hostname == (char *)NULL) || (*hostname == '\0'))
+   {
+      ns_printf(pio, usage, (dir==PUT) ? "put" : "get");
+      return -1;
+   }
+   sfile = nextarg(hostname);
+   *(sfile-1) = '\0';         /* null terminate hostname */
+   if (*sfile == '\0')
+   {
+      ns_printf(pio, usage, (dir==PUT) ? "put" : "get");
+      return -1;
+   }
+   dfile = nextarg(sfile);
+   if (*dfile != '\0')        /* if dfile was specified... */
+      *(dfile-1) = '\0';      /* ...null terminate sfile */
+   else                       /* if not specified default to sfile */
+      dfile = sfile;
+
+   msg = parse_ipad(&fhost, (unsigned *)&e, hostname);
+   if (msg)
+   {
+      ns_printf(pio,"TFTP host address error: %s\n", msg);
+      return -1;
+   }
+   /* if we're getting the file, swap src,dest file names */
+   if (dir == GET)
+   {
+      msg = sfile;
+      sfile = dfile;
+      dfile = msg;
+   }
+
+   last_pio = pio;   /* save pio for callback */
+
+   /* call tftp client code to create the session and start the transfer */
+#ifdef TFTP_CLIENT
+   msg = tftpuse(fhost, sfile, dfile, dir, OCTET, tfc_done);
+#endif
+   if (msg)
+      ns_printf(pio, "TFTP client error: %s\n", msg);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: tftp_state()
+ *
+ * Display TFTP status on the PIO output stream
+ *
+ * PARAM1: void *             PIO struct
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ */
+
+int
+tftp_state(void *pio)
+{
+   struct tfconn * cn;
+   int nconns = 0;
+
+#ifdef TFTP_SERVER
+   ns_printf(pio, "tftp server state %s\n", tftp_server_on?"ON":"OFF");
+#endif /* TFTP_SERVER */
+
+   for (cn = tftp_conns; cn; cn = cn->next)
+   {
+      ns_printf(pio, "connection: %s %u.%u.%u.%u, state:%d, bytes moved: %ld \n",
+                cn->tf_dir==PUT?"put to":"get from", 
+                PUSH_IPADDR(cn->tf_fhost), cn->tf_state, cn->tf_size);
+      nconns++;
+   }
+   ns_printf(pio, "%d connections open\n", nconns);
+
+   return 0;
+}
+
+
+#ifdef TFTP_CLIENT
+
+/* FUNCTION: tfc_done()
+ *
+ * TFTP Client "done" callback function
+ *
+ * PARAM1: int                completion status code
+ * PARAM2: tfconn *           TFTP connection
+ * PARAM3: char *             completion status message
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Print transfer completion statistics on the "current" output stream.
+ */
+
+int
+tfc_done(int status, struct tfconn *cn, char *msg)
+{
+   ip_addr fhost = cn->tf_fhost;
+   unsigned dir = cn->tf_dir;
+
+   ns_printf(last_pio, "tftp %s %u.%u.%u.%u done; ",
+             (dir == PUT) ? "to" : "from", PUSH_IPADDR(fhost));
+
+   ns_printf(last_pio, "msg: %s, status:%s(%d)\n",
+             msg ? msg : "None", (status == 0) ? "ok" : "error", status);
+
+   last_pio = NULL;  /* clear this - default back to console */
+
+   return 0;
+}
+
+#endif /* TFTP_CLIENT */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.c
new file mode 100644
index 0000000..a5d18e0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.c
@@ -0,0 +1,105 @@
+/* tftpport.c
+ *
+ * Copyright 1998 by InterNiche Technologies Inc. All rights reserved.
+ * Copyright 1995 by NetPort Software.
+ * Copyright 1986 by Carnegie Mellon
+ * Copyright 1984 by the Massachusetts Institute of Technology
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tftp_init(), tfs_done()
+ *
+ * TFTP per-port code
+ *
+ * PORTABLE: yes
+ */
+
+#include "tftpport.h"
+#include "tftp.h"
+
+#include "q.h"
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+
+#include "menu.h"
+
+int tfs_done(int, struct tfconn *, char *);
+
+#ifdef IN_MENUS
+extern struct menu_op tftpmenu[];
+#endif
+
+
+/* FUNCTION: tftp_init()
+ *
+ * Initialize TFTP
+ *
+ * PARAMS: none
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Open a UDP port for listen on tftp port, do any prep 
+ * required for client UDP use.
+ */
+
+int
+tftp_init(void)
+{
+#ifdef TFTP_SERVER
+   int e;
+
+   e = tfsinit(NULL, tfs_done);
+   if (e)
+      dprintf("tftp server start err %d\n", e);
+#endif   /* TFTP_SERVER */
+
+#ifdef IN_MENUS
+   if (install_menu(tftpmenu))
+      dprintf("tftp client menu failure\n");
+   install_version("tftp3.1");
+#endif   /* IN_MENUS */
+
+   return 0;
+}
+
+
+
+#ifdef TFTP_SERVER
+
+/* FUNCTION: tfs_done()
+ *
+ * TFTP Server's "done" callback function
+ *
+ * PARAM1: int                completion status code
+ * PARAM2: tfconn *           TFTP connection 
+ * PARAM3: char *             status message
+ *
+ * RETURN: int                0 if successful, otherwise ENP_ error code
+ *
+ * Print completion status information on the Console
+ */
+
+int
+tfs_done(int status, struct tfconn * cn, char * msg)
+{
+   ip_addr fhost = cn->tf_fhost;
+   unsigned dir = cn->tf_dir;
+
+   if (status == 0)
+   {
+      ns_printf(NULL, "tftp server: moved %lu bytes %s ",
+                cn->tf_size, (dir==PUT) ? "to" : "from");
+   }
+   else  /* error of some kind */
+   {
+      ns_printf(NULL, "tftp server error: status %d, msg: %s, host:",
+                status, (msg) ? msg : "None");
+   }
+   ns_printf(NULL, "%u.%u.%u.%u\n", PUSH_IPADDR(fhost));
+
+   return 0;
+}
+
+#endif  /* TFTP_SERVER */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.h b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.h
new file mode 100644
index 0000000..573eed0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpport.h
@@ -0,0 +1,69 @@
+/* tftpport.h
+
+   Copyright 1998-2000 by InterNiche Technologies Inc.
+
+   TFTP per-port definitions.
+   
+   12/26/98 - Created as part of cleanup. John Bartas
+*/
+
+#ifndef _TFTPPORT_H_
+#define _TFTPPORT_H_ 1
+
+#include "ipport.h"
+
+/* version 1.5 VFS hooks */
+#ifdef VFS_FILES
+#include "vfsfiles.h"
+#else
+#define vfopen(n,m)     fopen(n,m)
+#define vfclose(fd)     fclose(fd)
+#define vferror(fd)     ferror(fd)
+#define vfread(buf,i,j,fd)    fread(buf,i,j,fd)
+#define vfwrite(buf,i,j,fd)   fwrite(buf,i,j,fd)
+#define vfseek(fd,off,m)      fseek(fd,off,m)
+#define VFILE FILE
+#endif
+
+#ifdef NOTDEF
+#define ZEROCOPY_API 1     /* IP buffers can be marked in use */
+#endif
+
+#define TFTPSERVER  (void*)(-99L)   /* fake session for server */
+
+/* map TFTP's alloc & free routines to heap for this port */
+#ifndef TFC_ALLOC
+#define TFC_ALLOC(size) (struct tfconn *)npalloc(sizeof(struct tfconn))
+#define TFC_FREE(ptr) npfree(ptr)
+#endif
+
+#define	MAXTFTPS	   4  /* max. concurrent sessions */
+
+/*  Constants for round trip time estimation and retry timeout.
+    All calculation is done in clock ticks (at TPS rate) but
+    only the initial estimate and the upper limits are specified in ticks;
+    the rest of the algorithm uses dimensionless multipliers.  */
+
+#ifndef   TF_MAXTMO
+#define   TF_MAXTMO   (15*TPS)   /* upper limit on retry timeout timer */
+#endif
+
+#ifndef   TF_MINTMO
+#define   TF_MINTMO   (1*TPS)    /* lower limit on retry timeout timer */
+#endif
+
+/*  Constants for limiting the number of retries.  
+    Either or both of these can be zero to *not* limit the number of
+    retries.  */
+
+#ifndef   TFTPTRIES
+#define   TFTPTRIES   (4)        /* # of retries on packet transmission */
+#endif
+
+#ifndef   REQTRIES
+#define   REQTRIES    (5)        /* # of retries on initial request */
+#endif
+
+#endif /* _TFTPORT_H_ */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpsrv.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpsrv.c
new file mode 100644
index 0000000..e7998f6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpsrv.c
@@ -0,0 +1,288 @@
+/*   tftpsrv.c
+ *
+ * Copyright 1998 by InterNiche Technologies Inc. All rights reserved.
+ * Copyright 1995 by NetPort Software.
+ * Copyright 1986 by Carnegie Mellon
+ * Copyright 1984 by the Massachusetts Institute of Technology
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tfsinit(), tfs_on(), tfs_off(), tfshnd()
+ *
+ *  TFTP server code - uses common code in tftputil.c and udp
+ *  interface in tftpudp.c
+ *
+ *  PORTABLE: yes
+ */
+
+#include "tftpport.h"
+
+int tftp_server_on = FALSE;   /* TFTP server enable/disable state */
+
+#ifdef TFTP_SERVER
+
+#include "tftp.h"
+
+/* user-supplied callback functions (see tfsinit()) */
+static int (*tfs_alert)(ip_addr, char *, unshort);
+static int (*tfs_done)(int status, struct tfconn *, char *);
+
+extern int ntftps;
+u_long refusedt = 0;      /*  time of most recent transfer refusal  */
+void * tftpsconn = NULL;   /* server UDPCONN or socket */
+
+
+/* FUNCTION: tfsinit()
+ *
+ * Initialize the TFTP server
+ *
+ * PARAM1: int (*)()          alert function pointer
+ * PARAM2: int (*)()          done function pointer
+ *
+ * RETURNS: int               0 if successful, otherwise error code
+ *
+ * This opens a UDP connection but does not turn on the server.
+ * That needs to done by an explicit call to tfs_on().
+ *
+ * alert() is a function which the server will call whenever it receives
+ * a request for a transfer. This function will be called in the following
+ * way:
+ *     alert(ip_addr, file_name, direction)
+ *
+ * alert() should return TRUE if it wishes to allow the transfer and
+ * FALSE otherwise.  
+ *
+ * done() is a function that the server will call to inform the invoker
+ * that this file transfer is complete or aborted.
+ */
+
+int
+tfsinit(int (*alert)(ip_addr, char *, unshort),    /* notification callback */
+        int (*done)(int, struct tfconn *, char *)) /* xfer complete callback */
+{
+   unshort lport = TFTPPORT;  /* for pass to tftp_udplisten() */
+
+   /* open server tftp connection to receive incoming requests
+   with wildcard foriegn host & wildcard foriegn port */
+   tftpsconn = tftp_udplisten(0L, 0, &lport, TFTPSERVER);
+
+   if (!tftpsconn)
+      return ENP_RESOURCE;
+
+   tfs_done = done;
+   tfs_alert = alert;
+
+   return 0;
+}
+
+#endif  /* TFTP_SERVER */
+
+
+
+/*
+ * The following functions are required to be defined, even if 
+ * there is no TFTP Server configured. If there is no TFTP Server,
+ * the functions are simply "no-ops".
+ */
+
+/* FUNCTION: tfs_on()
+ *
+ * Enable the TFTP server
+ *
+ * PARAMS: none
+ *
+ * RETURNS: none
+ */
+
+void
+tfs_on() 
+{
+#ifdef TFTP_SERVER
+   tftp_server_on = TRUE;
+#endif
+}
+
+
+
+/* FUNCTION: tfs_off()
+ *
+ * Disable the TFTP server
+ *
+ * PARAMS: none
+ *
+ * RETURNS: none
+ */
+
+void
+tfs_off() 
+{
+#ifdef TFTP_SERVER
+   tftp_server_on = FALSE;
+#endif
+}
+
+
+
+/* FUNCTION: tfshnd()
+ *
+ * Handle an initial incoming TFTP packet
+ *
+ * PARAM1: ip_addr            IP address of sender
+ * PARAM2: unshort            Sender's port number
+ * PARAM3: char *             Pointer to sender's data
+ *
+ * RETURNS: int               0 if successful, otherwise ENP_ error code
+ *
+ * Opening a UDP connection (immediately so that we can report errors).
+ * If the server is OFF then the tftp will be refused; otherwise more
+ * checking will be done.  Call the alert function and verify that the
+ * "user" wishes to allow the TFTP. Report an error if not. Finally,
+ * spawn a session to oversee the TFTP and cleanup when it's done.  
+ */
+
+int
+tfshnd(ip_addr host, unshort fport, char *udata)
+{
+#ifdef TFTP_SERVER
+   struct tfreq *ptreq;
+   char *file, *smode, *tmp;
+   struct tfconn *cn = NULL;
+   unsigned mode;
+   int e = 0;  /* error value to return */
+
+   /* Do we have room to do this transfer?  */
+   if (ntftps >= MAXTFTPS) 
+   {
+      dprintf("TFTP Serve:  Ignoring req, too many connections\n");
+      return ENP_RESOURCE;
+   }
+
+   ptreq = (struct tfreq *)udata;
+   ptreq->tf_op = htons(ptreq->tf_op);
+   if ((ptreq->tf_op != TF_RRQ) && (ptreq->tf_op != TF_WRQ))
+   {
+      dprintf("TFTP Server: bad init opcode %u\n", ptreq->tf_op);
+      return ENP_LOGIC;
+   }
+
+   /* make conn now, in case we send errors */
+   cn = tfmkcn();
+   if (cn == (struct tfconn *)NULL) 
+   {
+      dprintf("TFTP Server: session Alloc failed\n");
+      return ENP_RESOURCE;
+   }
+   cn->tf_start = cticks;
+   cn->tf_fhost = host;
+   cn->tf_fport = fport;
+   cn->tf_lport = TFTPPORT;   /* errors come from std port for now */
+
+   if (tftp_server_on != TRUE) 
+   {
+      dprintf("TFTP Server: got req while off\n");
+      tfsnderr(cn, ERRTXT, "Transfers currently disabled.");
+      tfcleanup(cn);
+      return 0;   /* this is not an error */
+   }
+
+   /* get a pointer to the file name */
+   file = (char*)ptreq + sizeof(ptreq->tf_op);
+
+   if (tfs_alert)             /* call user's security function */
+   {
+      int code;
+      unshort xmode = (unshort)(ptreq->tf_op == TF_RRQ ? PUT : GET);
+
+      code = (*tfs_alert)(host, file, xmode);
+      if (code == 0)
+      {
+         tfsnderr(cn, ERRTXT, "Transfer refused.");
+         refusedt = cticks;
+         tfcleanup(cn);
+         return 0;
+      }
+   }
+
+   /* determine the transfer mode. 
+    * convert the transfer mode to lower case for easier comparison.
+    */
+   smode = file + strlen(file)+1;
+   for (tmp = smode; *tmp; tmp++)
+      if ((*tmp >= 'A') && (*tmp <= 'Z'))
+         *tmp += ('a' - 'A');
+
+   if ((strcmp(smode, "image") == 0) || (strcmp(smode, "octet") == 0))
+      mode = OCTET;
+   else if (strcmp(smode, "netascii") == 0)
+      mode = ASCII;
+   else 
+   {
+      dprintf("TFTP Server:  Bad mode %s in req\n", smode);
+      tfsnderr(cn, ERRTXT, "Bad mode");
+      tfcleanup(cn);
+      return ENP_LOGIC;
+   }
+
+   /* open a UDP connection for data transfer with this host */
+   cn->tf_lport = 0;          /* let UDP select local port */
+   cn->tf_conn = tftp_udplisten(host, fport, &cn->tf_lport, (void*)cn);
+   if (cn->tf_conn == (void *)NULL) 
+   {
+      dprintf("TFTP Server: UDP listen error\n");
+      tfcleanup(cn);
+      return ENP_RESOURCE;
+   }
+   cn->tf_mode = mode;
+   cn->callback = tfs_done;
+
+   /* is it a read request or a write request? */
+   if (ptreq->tf_op == TF_RRQ) 
+   {
+      cn->tf_dir = PUT;
+      if (cn->tf_mode == ASCII)   /* let file sys handle netascii */
+         cn->tf_fd = vfopen(file, "r");
+      else
+         cn->tf_fd = vfopen(file, "rb");
+
+      if (cn->tf_fd == (VFILE *)NULL) 
+      {
+         dprintf("TFTP server: couldn't open file\n");
+         tfsnderr(cn, FNOTFOUND, " ");
+         if (tfs_done)
+            (*tfs_done)(TFC_FILEOPEN, cn, file);
+         tfcleanup(cn);
+         return ENP_FILEIO;
+      }
+      cn->tf_expected = 1;    /* start with block number 1 */
+      cn->tf_flen = NORMLEN;
+      cn->tf_state = RCVACK;  /* consider request to first ack */
+   }
+   else  /* ptreq->tf_op == TF_WRQ */
+   {
+      cn->tf_dir = GET;
+      if (cn->tf_mode == ASCII)   /* let file sys handle netascii */
+         cn->tf_fd = vfopen(file, "w");
+      else
+         cn->tf_fd = vfopen(file, "wb");
+
+      if (cn->tf_fd == (VFILE *)NULL) 
+      {
+         dprintf("TFTP Server: couldn't open file\n");
+         tfsnderr(cn, ACCESS, " ");
+         if (tfs_done)
+            (*tfs_done)(TFC_FILEOPEN, cn, file);
+         tfcleanup(cn);
+         return ENP_FILEIO;
+      }
+      cn->tf_expected = 0;    /* ack block number 0 */
+      e = tfsndack(cn);
+      cn->tf_expected = 1;    /* start with block number 1 */
+      cn->tf_state = DATAWAIT;
+   }
+
+   return e;   /* OK return */
+#else
+   return 0;
+#endif  /* TFTP_SERVER */
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpudp.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpudp.c
new file mode 100644
index 0000000..a5a5e84
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftpudp.c
@@ -0,0 +1,314 @@
+/* FILE: tftpudp.c
+ *
+ * Copyright 1998 by InterNiche Technologies, Inc. All rights reserved.
+ * Copyright 1996 by NetPort Software.
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tftp_udplisten(), tftp_udpsend(), tftp_upcall(),
+ * ROUTINES: tftp_udpbuffer(), tftp_udpfree(), tftp_udpclose()
+ *
+ * UDP API (Sockets or lightweight) dependant portion of the TFTP code.
+ *
+ * PORTABLE: yes
+ */
+
+#include "tftpport.h"
+#include "tftp.h"
+
+#include "q.h"         /* get netport IP stack defines */
+#include "netbuf.h"
+#include "net.h"
+#include "ip.h"
+#include "udp.h"
+
+
+UDPCONN tftp_conn;
+
+static int tftp_upcall(PACKET pkt, void * data);
+
+
+/* FUNCTION: tftp_udplisten()
+ *
+ * Start a UDP listen for TFTP 
+ *
+ * PARAM1: ip_addr            IP address of foreign host
+ * PARAM2: unshort            foreign port
+ * PARAM3: unshort            local port or zero
+ * PARAM4: void *             callback data parameter value
+ *
+ * RETURNS: void *            connection ID (socket or UDPCONN)
+ *                            or NULL.
+ *
+ * Start a UDP listen on fhost & ports passed. This is used by the
+ * TFTP code to establish a receive endpoint prior to sending UDP
+ * datagrams. If lport is 0, a useable value is obtained from the UDP layer.
+ *
+ * The "ptr" parameter is callback data. It will be the tfconn ptr for 
+ * a client, TFTPSERVER for a server.
+ *
+ * Returns connection ID (socket or UDPCONN) if successful, else 
+ * returns NULL if there is an error.
+ */
+
+void *
+tftp_udplisten(ip_addr fhost, unshort fport, unshort * lport, void *ptr)
+{
+   UDPCONN u;
+   unshort tmpport;  /* tmp holder for local port value */
+
+   /* first, get a local port for use on this connection */
+   if (*lport == 0)   /* caller wants us to allocate one */
+      tmpport = udp_socket();
+   else  /* use port passed */
+      tmpport = *lport;
+
+   if (ptr == NULL)
+      ptr = TFTPSERVER;  /* indicate server */
+
+   u = udp_open(fhost, fport, tmpport, tftp_upcall, (void *)ptr);
+
+   if (u)
+   {
+      *lport = tmpport;       /* return local port to caller */
+      return ((void *)u);     /* success */
+   }
+   else
+      return (void *)NULL;    /* error */
+}
+
+
+
+/* FUNCTION: tftp_udpsend()
+ *
+ * Send a UDP datagram
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: void *             UDP data buffer
+ * PARAM3: int                UDP data buffer length
+ *
+ * RETURNS: int               0 if success, else error code
+ */
+
+int
+tftp_udpsend(struct tfconn *conn, void *outbuf, int outlen)
+{
+   PACKET pkt;
+   int e;   /* error holder */
+
+   pkt = (PACKET)conn->tf_outbuf.udp_use;
+
+   /* sanity check buffer pointer */
+   if ((char *)outbuf != pkt->nb_prot)
+   {
+      /* this is OK on retrys, but not initial sends */
+      if (((char *)outbuf <= pkt->nb_buff) ||  /* null outbuf == bad */
+         (conn->tf_tmo == 0)) /* this is not a retry */
+      {
+         dtrap();
+         return ENP_LOGIC;
+      }
+   }
+
+   pkt->nb_prot = (char*)outbuf;
+   pkt->nb_plen = outlen;
+   pkt->fhost = conn->tf_fhost;
+   pkt->net = NULL;  /* force it to route */
+
+#ifdef ZEROCOPY_API  /* packet can be marked in use, not freed */
+   pkt->inuse = 2;   /* clone it so it won't pk_free() on send */
+#else    /* need to copy data in case we have to retry */
+   {
+      PACKET pkt2;   /* packet to send & free */
+
+      pkt2 = udp_alloc(outlen, 0);
+      if (!pkt2)
+         return ENP_NOBUFFER;
+
+      pkt2->nb_plen = pkt->nb_plen;
+      pkt2->fhost = pkt->fhost;
+      pkt2->net = NULL;
+      MEMCPY(pkt2->nb_prot, pkt->nb_prot, outlen);
+      pkt = pkt2; /* send duplicate pkt, keep original in tf_conn */
+   }
+#endif
+
+   e = udp_send(conn->tf_fport, conn->tf_lport, pkt);
+
+   if (e < 0)
+   {
+#ifdef NPDEBUG
+      dprintf("tftp_udpsend(): udp_send() error %d\n", e);
+#endif
+      return e;
+   }
+   else
+      return 0;
+}
+
+
+
+/* FUNCTION: tftp_upcall()
+ *
+ * UDP callback function
+ *
+ * PARAM1: PKT                received UDP datagram packet
+ * PARAM2: void *             caller-supplied data
+ *
+ * RETURNS: int               0 if success, else error code
+ */
+
+int
+tftp_upcall(PACKET pkt, void * data)
+{
+   struct tfconn * cn;
+   struct udp * pup;
+
+   /* get pointer to UDP header */
+   pup = (struct udp *)pkt->nb_prot;
+   pup -= 1;
+
+   /* Find tftp session this packet is for. */
+   if (data == TFTPSERVER)    /* tftp server connection */
+   {
+#ifdef TFTP_SERVER
+      int err;
+      /* call server for new session here */
+      err = tfshnd(pkt->fhost, pup->ud_srcp, pkt->nb_prot);
+#endif /* TFTP_SERVER */
+      udp_free(pkt);
+     /* do not return an error to the udp layer */
+   }
+   else  /* TFTP server child connection */
+   {
+      cn = (struct tfconn *)data;
+      if (cn->tf_fhost != pkt->fhost)   /* sanity check */
+      {
+         dtrap();
+         return ENP_NOT_MINE;
+      }
+
+      if (cn->tf_inbuf.udp_use)
+      {
+         dtrap(); /* ever happen? */
+      }
+
+      cn->tf_inbuf.data = pkt->nb_prot;
+      cn->tf_inbuf.dlen = pkt->nb_plen;
+      cn->tf_inbuf.udp_use = (void*)pkt;
+
+      tftprcv(cn, pup->ud_srcp);    /* process the packet */
+
+      if (cn->tf_inbuf.udp_use)     /* pkt may be freed in upcall */
+      {
+         udp_free(pkt);
+         cn->tf_inbuf.udp_use = (PACKET)NULL;
+      }
+   }
+
+   return 0;
+}
+
+
+
+/* FUNCTION: tftp_udpbuffer()
+ *
+ * Obtain a packet buffer for UDP output
+ *
+ * PARAM1: tfconn *           TFTP connection block
+ * PARAM2: int                UDP data length
+ *
+ * RETURNS: none
+ *
+ * Called by tftp to ask UDP layer for a packet buffer. If a buffer
+ * is obtained, the data is filled into the passed cn->tf_outbuf.
+ * Otherwise, everything in tf_outbuf is cleared.
+ *
+ * The lightweight API grabs a buffer from the UDP layer to avoid doing a 
+ * data copy. Sockets will probably need to calloc.....
+ */
+
+void
+tftp_udpbuffer(struct tfconn *cn, int size)
+{
+   PACKET pkt;
+
+   if (cn->tf_outbuf.udp_use)
+   {
+      pkt = (PACKET)cn->tf_outbuf.udp_use;
+      if (pkt->nb_plen >= (unsigned)size)
+      {
+         /* recycle existing buffer */
+         pkt->nb_prot = (char *)cn->tf_outbuf.data;
+         return;
+      }
+      else
+      {
+         udp_free(pkt);       /* old packet was too small */
+      }
+   }
+
+   pkt = udp_alloc(size, 0);
+   if (!pkt) /* alloc failed, clear outbuf pointers */
+   {
+      cn->tf_outbuf.data = NULL;
+      cn->tf_outbuf.dlen = 0;
+      cn->tf_outbuf.udp_use = NULL;
+   }
+   else  /* return buffer pointer */
+   {
+      cn->tf_outbuf.data = pkt->nb_prot;
+      cn->tf_outbuf.dlen =  size;
+      cn->tf_outbuf.udp_use = (void *)pkt;   /* so we can find struct later */
+   }
+}
+
+
+
+/* FUNCTION: tftp_udpfree()
+ *
+ * Free a UDP buffer that has been ACKed
+ *
+ * PARAM1: tfconn *           TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Called to free the udp buffer after it has been acked. 
+ */
+
+void
+tftp_udpfree(struct tfconn *cn)
+{
+   PACKET pkt;
+
+   pkt = (PACKET)cn->tf_outbuf.udp_use;
+#ifdef ZEROCOPY_API
+   pkt->inuse = 1;   /* free this copy - "unclone" it */
+#endif
+   udp_free(pkt);
+   cn->tf_outbuf.udp_use = NULL;
+   cn->tf_outbuf.data = NULL;
+}
+
+
+
+/* FUNCTION: tftp_udpclose()
+ *
+ * Close the TFTP connection
+ *
+ * PARAM1: void *             TFTP connection handle
+ *
+ * RETURNS: int               0 if success, else error code
+ *
+ * Call udp_close() to close the connection. 
+ */
+
+int
+tftp_udpclose(void * conn)
+{
+   UDPCONN cn = (UDPCONN)conn;
+
+   udp_close(cn);
+   return 0;   /* no ability to detect error on this API */
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftputil.c b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftputil.c
new file mode 100644
index 0000000..9be8556
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/tftp/tftputil.c
@@ -0,0 +1,858 @@
+/*   tftputil.c
+ *
+ * Copyright 1998-1999 by InterNiche Technologies, Inc. All rights reserved.
+ * Copyright 1995 by NetPort Software.
+ * Copyright 1986 by Carnegie Mellon
+ * Copyright 1984 by the Massachusetts Institute of Technology
+ *
+ * MODULE: TFTP
+ *
+ * ROUTINES: tfmkcn(), tfcleanup(), tftptmo(), tf_good(), tfdodata()
+ * ROUTINES: tf_full(), tfsnderr(), tfdoerr(), tfsndack(), tf_write()
+ * ROUTINES: tfsndata(), tfdoack(), tftprcv(), tfkill()
+ * ROUTINES: tftp_tick(), check_state()
+ *
+ * TFTP Client and Server utility routines
+ *
+ * PORTABLE: yes
+ */
+
+#include "tftpport.h"
+
+#include "tftp.h"
+
+/* internal routine */
+static void check_state(struct tfconn * cn);
+
+struct tfconn * tftp_conns = NULL;   /* list of active connections */
+int ntftps = 0;   /* number of connections */
+
+
+/* FUNCTION: tfmkcn()
+ *
+ * Setup a TFTP connection block
+ *
+ * PARAMS: none
+ *
+ * RETURN: struct tfconn *    TFTP connection block
+ *                            or NULL if error
+ *
+ * Allocates and initializes a TFTP connection block.
+ */
+
+struct tfconn * 
+tfmkcn(void)
+{
+   struct tfconn * cn;
+
+   cn = (struct tfconn *)TFC_ALLOC(sizeof(struct tfconn));
+   if (cn == (struct tfconn *)NULL)
+      return (struct tfconn *)NULL;
+
+   ntftps++;
+   cn->next = tftp_conns;   /* add this tfconn to list */
+   tftp_conns = cn;
+
+   cn->tf_srtt = cn->tf_rt = TPS/2;   /* init round trip timer with large-ish guess */
+   if (cn->tf_rt > TF_MAXTMO)
+      cn->tf_rt = TF_MAXTMO;
+   else if (cn->tf_rt < TF_MINTMO)
+      cn->tf_rt = TF_MINTMO;
+   cn->tf_NR_last = 1;   /* fake last packet Number retrys */
+
+   return cn;
+}
+
+
+
+/* FUNCTION: tfcleanup()
+ *
+ * TFTP cleanup routine
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Called when we are done with the connection. 
+ * Unlink the connection block from the TFTP list, and free
+ * any allocated resources.
+ */
+
+void
+tfcleanup(struct tfconn *cn)
+{
+   struct tfconn *tmp, *last;
+
+   /* unlink cn from list */
+   /* traverse list, looking of cn to free */
+   last = (struct tfconn *)NULL;
+   for (tmp = tftp_conns; tmp; tmp = tmp->next)
+   {
+      if (tmp == cn)
+      {
+         if (last)   /* unlink from list */
+            last->next = tmp->next;
+         else   /* was first in list, fix list pointer */
+            tftp_conns = tmp->next;
+         break;
+      }
+      last = tmp;
+   }
+
+   if (tmp == (struct tfconn *)NULL)      /* connection not in master list? */
+   {
+      dtrap();   /* serious prog error..... */
+   }
+
+   if (cn->tf_fd != (VFILE *)NULL)
+      vfclose(cn->tf_fd);     /* close any open file */
+   if (cn->tf_outbuf.data)
+      tftp_udpfree(cn);       /* free any data buffer */
+   if (cn->tf_conn != 0)
+      tftp_udpclose(cn->tf_conn);   /* close the connection */
+
+   TFC_FREE(cn);              /* free the connection block */
+   ntftps--;
+}
+
+
+
+/* FUNCTION: tftptmo()
+ *
+ * Handle a TFTP timeout event 
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * TFTP timed out waiting for a reply. Try resending the
+ * previous packet, unless maximum retry limit has been exceeded,
+ * in which case give up and kill the connection.
+ */
+
+void 
+tftptmo(struct tfconn *cn)
+{
+   TFTPBUF p;
+
+   cn->tf_tmo++;
+   /* if we have more tries... */
+   if (--cn->tf_tries >= 0)
+   {
+      int e;
+
+      cn->tf_rsnd++;
+      cn->tf_NR++;
+      /* do the actual retry. Don't use tf_write() since it will re-init 
+         the round trip & retry count values. */
+      p = &cn->tf_outbuf;
+      e = tftp_udpsend(cn, p->data, cn->tf_lastlen);
+      if (e < 0)
+      {
+         if (cn->callback)
+         {
+            if (e == ENP_NOBUFFER)
+               cn->callback(TFC_BUFFER, cn, "UDP alloc failed");
+            else
+               cn->callback(TFC_UDPSEND, cn, "UDP send failed");
+         }
+         tfkill(cn);    /* UDP send error, kill tftp session */
+      }
+      else  /* udp retry packet sent OK */
+      {
+         cn->tf_rt <<= 1;      /* double round trip est. */
+         if (cn->tf_rt > TF_MAXTMO)
+            cn->tf_rt = TF_MAXTMO;
+         cn->tf_tick = cticks + cn->tf_rt;   /* set time to do next retry */
+      }
+   }
+   else 
+   {
+      cn->tf_state = TIMEOUT;
+   }
+}
+
+
+
+/* FUNCTION tf_good()
+ *
+ * Do timing calculations after good receives
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Calculate the round-trip time and refine the connection's
+ * round-trip estimate.
+ */
+
+void
+tf_good(struct tfconn *cn)
+{
+   unsigned long trt;
+
+   trt = cticks - cn->tf_sent;  /*  Measured round trip time  */
+   /* set smoothed round trip time based on measured */
+   if ((cn->tf_srtt > trt) && (cn->tf_srtt > 1))
+      cn->tf_srtt--;
+   else if ((cn->tf_srtt) < trt)
+      cn->tf_srtt++;
+   /* set the retry time: experimental algorithm: */
+   trt += cn->tf_srtt + 1;
+   if (trt < TF_MINTMO)
+      trt = TF_MINTMO;
+   else if (trt > TF_MAXTMO)
+      trt = TF_MAXTMO;
+   cn->tf_rt = trt;
+
+   cn->tf_NR_last = cn->tf_NR;
+   cn->tf_NR = 0;
+}
+
+
+
+/* FUNCTION: tfdodata()
+ *
+ * Process a received data packet
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: TFTPBUF            received data buffer
+ * PARAM3: unsigned int       data length
+ *
+ * RETURNS: int               TRUE if OK, FALSE if error
+ *
+ * Process a data packet received for TFTP connection cn.
+ * Handle out of sequence blocks and check on block length.
+ * If a block is way too short (len < tftp header size), send
+ * back an error message and abort the transfer. If the block
+ * is less than NORMLEN bytes long, shut down the transfer; we're done.
+ * Otherwise, just write it to disk (if necessary).
+ */
+
+int /* BOOL */
+tfdodata(struct tfconn * cn, TFTPBUF p, unsigned len)
+{
+   char * data;
+   struct tfdata *ptfdat;
+
+   if (len < 4) 
+   {
+      tfsnderr(cn, ERRTXT, "Bad len (too short)");
+      if (cn->callback)
+         cn->callback(TFC_BADLEN, cn, "short data from peer");
+      tfkill(cn);
+      return FALSE;
+   }
+
+   if (cn->tf_state != DATAWAIT)
+   {
+      tfsnderr(cn, ERRTXT, "Rcvd unexpected data block");
+      return FALSE;
+   }
+
+   /* point to tftp header at front of packet */
+   ptfdat = (struct tfdata *)p->data;
+   len -= 4;   /* subtract length of header from data */
+
+   if (htons(ptfdat->tf_block) != cn->tf_expected)
+   {
+      /* We got a retransmission of a packet we have already tried to ACK.
+       * If we retransmit the ACK, and the old ACK finally gets through also,
+       * our correspondent will resend the next data block, and we will do
+       * the same thing for it, on through to the end of the file.  So we
+       * shouldn't retransmit the ACK until we are convinced that the first
+       * one was actually lost.  We will become convinced if our own timeout
+       * waiting for the next data packet expires.
+       */
+      cn->tf_ous++;   
+      return FALSE;
+   }
+   tf_good(cn);   /* adjust timer values */
+
+   cn->tf_size += len;        /* update file statistics */
+   cn->tf_flen = len;
+
+   /* write UDP data into file */
+   if (len > 0)
+   {
+      data = ptfdat->tf_data;
+      if ((int)vfwrite(data, 1, len, cn->tf_fd) != (int)len)
+      {
+         tf_full(cn);
+         return FALSE;
+      }
+   }
+   
+   /* Send the ack. If len < NORMLEN, we've reached end-of-file */
+   tfsndack(cn);
+   if (len < NORMLEN)         /* last data block */
+   {
+      if (cn->tf_fd)          /* close the open file */
+      {
+         vfclose(cn->tf_fd);
+         cn->tf_fd = (VFILE *)NULL;
+      }
+      cn->tf_state = RCVLASTDATA;   /* get ready to close the connection */
+   }
+
+   cn->tf_expected++;
+   return TRUE;
+}
+
+
+
+/* FUNCTION: tf_full()
+ *
+ * Handle the "disk full" condition
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Handle disk full condition by sending error packet and killing
+ * this connection.
+ */
+
+void
+tf_full(struct tfconn *cn)
+{
+   tfsnderr(cn, DISKFULL, " ");
+   tfkill(cn);   
+   if (cn->callback)
+       cn->callback(TFC_DISKFULL, cn, tferrors[DISKFULL] );
+}
+
+
+
+/*  */
+
+char * tferrors[] = 
+{
+   "See text",
+   "File not found",
+   "Access violation",
+   "Disk full",
+   "Illegal TFTP operation",
+   "Unknown transfer ID",
+   "File already exists",
+   "No such user"
+};
+
+
+/* FUNCTION: tfsnderr()
+ *
+ * Send an error packet
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: unsigned int       error code
+ * PARAM3: char *             error message text (if error code is zero)
+ *
+ * RETURNS: none
+ *
+ * Send an error packet. If the code is nonzero, use a pre-defined
+ * error message. Otherwise, copy the text into the packet.
+ */
+
+void
+tfsnderr(struct tfconn * cn, unsigned code, char *text)
+{
+   unsigned len;
+   struct tferr *perr;
+
+   /* use pre-defined error message? */
+   if (code != ERRTXT)
+      text = tferrors[code];
+
+   /* length = header + string + NUL */
+   len = 4 + strlen(text) + 1;
+
+   /* allocate a buffer and fill in the fields */
+   tftp_udpbuffer(cn, len);
+   if (cn->tf_outbuf.data != (char *)NULL)
+   {
+      perr = (struct tferr *)(cn->tf_outbuf.data);
+      perr->tf_op = htons(TF_ERROR);
+      perr->tf_code = htons(code);
+      strcpy(perr->tf_err, text);
+      
+      /* send the error message */
+      tftp_udpsend(cn, perr, len);
+
+      /* free now; there are no retrys on these */
+      tftp_udpfree(cn);
+   }
+}
+
+
+
+/* FUNCTION: tfdoerr()
+ *
+ * Process an incoming error packet 
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: TFTPBUF            received data buffer
+ * PARAM3: unsigned int       data length
+ *
+ * RETURNS: int               TRUE if OK, FALSE if error
+ *
+ * If the connection is still alive, kill it. Pass the 
+ * error message to the app via the callback function.
+ */
+
+void
+tfdoerr(struct tfconn *cn, TFTPBUF p, unsigned len)
+{
+   struct tferr *perr;
+   int tferror;               /* tftp protocol error */
+   char *errtxt;              /* text of/for error */
+
+   /* if connection is dead, don't worry about this... */
+   if ((cn->tf_state != DEAD) && (cn->tf_state != TERMINATED))
+   {
+      tfkill(cn);
+
+      /* get the error code and error message */
+      perr = (struct tferr *)p->data;
+      tferror = htons(perr->tf_code);     /* get tftp error code (see rfc) */
+      if ((tferror > 0) && (tferror < 8))
+         errtxt = tferrors[tferror];      /* get pre-defined error text */
+      else
+      {
+         /* not a known error, try to extract text from tftp packet */
+         errtxt = perr->tf_err;
+         if ((*errtxt <= ' ') || (*errtxt >= 0x7f) ||
+             (strlen(errtxt) > 100))   /* make sure it's printable */
+         {
+            errtxt = "bogus tftp error text";
+         }
+      }
+
+      /* notify app of error */
+      if (cn->callback)
+         cn->callback(TFC_FOREIGN, cn, errtxt);
+   }
+
+   USE_ARG(len);
+}
+
+
+
+/* FUNCTION: tfsndack()
+ *
+ * ACK the latest block
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: int               0 if success, else error code
+ *
+ * Build and send ack for latest block
+ */
+
+int
+tfsndack(struct tfconn *cn)
+{
+   struct tfack *pack;
+   int e = ENP_NOBUFFER;
+
+   /* allocate buffer for ACK */
+   tftp_udpbuffer(cn, sizeof(struct tfack));
+   if (cn->tf_outbuf.data)
+   {
+      pack = (struct tfack *)(cn->tf_outbuf.data);
+
+      cn->tf_lastlen = sizeof(struct tfack);
+      pack->tf_op = TF_ACK;   /* in local endian, tf_write will fix */
+      pack->tf_block = cn->tf_expected;
+
+      /* send the ACK */
+      e = tf_write(cn, sizeof(struct tfack));
+   }
+
+   return e;
+}
+
+
+
+/* FUNCTION: tf_write()
+ *
+ * Send a TFTP packet
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: unsigned int       packet length
+ *
+ * Write (send) a tftp packet to the other host
+ */
+
+int
+tf_write(struct tfconn *cn, unsigned len)
+{
+   struct tfack * packet;
+
+   packet = (struct tfack *)(cn->tf_outbuf.data);
+   if (packet == NULL)
+   {
+      dtrap(); /* prog error */
+      return ENP_NOBUFFER;
+   }
+
+   if ((packet->tf_op != TF_RRQ) && (packet->tf_op != TF_WRQ))
+   {
+      packet->tf_block = htons(packet->tf_block);
+      cn->tf_tries = TFTPTRIES;
+   }      
+   else 
+      cn->tf_tries = REQTRIES;
+
+   packet->tf_op = htons(packet->tf_op);   /* convert op to net format */
+
+   cn->tf_lastlen = len;
+   cn->tf_snt++;
+   cn->tf_sent = cticks;
+   cn->tf_tick = cticks + cn->tf_rt;   /* set time to retry */
+   cn->tf_NR = 1;
+
+   return (tftp_udpsend(cn, cn->tf_outbuf.data, len));
+}
+
+
+
+/* FUNCTION: tfsndata()
+ *
+ * Send a TFTP data block
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: int               0 if success, else error code
+ *
+ * Allocate a TFTP data buffer (packet). Read the next chunk
+ * of file data, and send it. If this is a retry, use the 
+ * previous chunk of file data.
+ */
+
+int
+tfsndata(struct tfconn *cn)
+{
+   struct tfdata *tfdata;
+   int bytes = 0;   /* bytes read from file */
+   int err;
+
+   tftp_udpbuffer(cn, sizeof(struct tfdata));
+   if (cn->tf_outbuf.data == NULL)
+      return ENP_NOBUFFER;
+
+   tfdata = (struct tfdata *) (cn->tf_outbuf.data);
+   tfdata->tf_op = TF_DATA;
+   tfdata->tf_block = cn->tf_expected;
+
+   /* load file data into tftp buffer */
+   if (!cn->tf_NR)   /* if this is NOT a retry, read in new data */
+   {
+      /* read next block from the file */
+      bytes = vfread(tfdata->tf_data, 1, NORMLEN, cn->tf_fd);
+      if (bytes < NORMLEN)      /* end of file? */
+      {
+         if (vferror(cn->tf_fd))   /* see if it's an error */
+         {
+            if (cn->callback)
+                cn->callback(TFC_FILEREAD, cn, "file read error");
+            tfcleanup(cn);    /* free resources */
+            return FALSE;
+         }
+         /* else at End Of File; fall through to do last send */
+      }
+
+      cn->tf_flen = bytes;   /* bytes in last packet sent */
+      cn->tf_size += bytes;   /* total bytes sent so far */
+   }
+   else
+   {
+      dtrap();   /* can this happen? */
+   }
+
+   /* send the data block */
+   err = tf_write(cn, sizeof(struct tfdata)-NORMLEN+bytes);
+   if (err == 0)   /* if sent OK, wait for reply */
+   {
+      /* update tftp state */
+      cn->tf_state = (cn->tf_flen == NORMLEN) ? ACKWAIT : SENTLAST;
+   }
+   else   /* else kill connection */
+   {
+      if (cn->callback)
+      {
+         if (err == ENP_NOBUFFER)
+            cn->callback(TFC_BUFFER, cn, "UDP alloc failed");
+         else
+            cn->callback(TFC_UDPSEND, cn, "UDP send failed");
+      }
+      tfkill(cn);
+   }
+
+   return err;
+}
+
+
+
+/* FUNCTION: tfdoack()
+ *
+ * Handle an incoming ack
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ */
+
+void
+tfdoack(struct tfconn *cn)
+{
+   struct tfack *ack;
+   TFTPBUF p = &cn->tf_inbuf;
+
+   ack = (struct tfack *)(p->data);
+
+   if (htons(ack->tf_block) != cn->tf_expected) 
+   {
+      /* We have received an ACK,
+         but not for the data block we sent.  It must be for
+         a duplicate, since we wouldn't have sent
+         the current data block if we hadn't gotten an ACK for
+         the previous one.  This duplicate ACK means either
+         that the network resent a packet that it wasn't sure
+         got through, or else the other end resent the ACK
+         because our current data block is lost or late.
+         In either case, we can safely ignore this extra ACK,
+         and if the ACK we want doesn't come our own timer will
+         get us started again.  It isn't safe to resend the current
+         data block now unless we are absolutely certain that the
+         other end won't reack it if the earlier send was just delayed.
+       */
+      cn->tf_ous++;
+   }
+   else 
+   {
+      tf_good(cn);
+      /* If ack was for last packet, we are done with this connection */
+      if (cn->tf_state == SENTLAST)
+      {
+         if (cn->tf_fd)       /* close the file */
+         {
+            vfclose(cn->tf_fd);
+            cn->tf_fd = (VFILE *)NULL;
+         }
+         cn->tf_state = TERMINATED;
+      }
+      else
+         cn->tf_state = RCVACK;
+
+      tftp_udpfree(cn);    /* free acked data buffer */
+      cn->tf_expected++;   /* ready to do next block */
+   }
+}
+
+
+
+/* FUNCTION: tftprcv()
+ *
+ * Handle an incoming TFTP packet
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ * PARAM2: unshort            port number
+ *
+ * RETURN: none
+ *
+ * This is upcalled from the tftpudp.c code which handles UDP semantics. 
+ * Note that contents of cn->tf_inbuf are only good for the duration of
+ * this upcall.
+ */
+
+void
+tftprcv(struct tfconn *cn, unshort fport)
+{
+   TFTPBUF p;
+   struct tfdata *pdata;
+   unshort op;
+   unsigned len;
+
+   p = &cn->tf_inbuf;   /* data is in connection's buffer */
+   len = p->dlen;      /* size of received data in buffer */
+
+   /* If tf_fport is still not set, this should be ack for first block */
+   if (cn->tf_fport == TFTPPORT)
+   {
+      struct tfack * ack = (struct tfack *)(p->data);
+
+      if (htons(ack->tf_block) <= 1)   /* only do this on first block */
+         cn->tf_fport = fport;   /* set port from upcalled value */
+   }
+   cn->tf_rcv++;
+   pdata = (struct tfdata *) (p->data);
+   op = htons(pdata->tf_op);
+   pdata->tf_op = op;
+
+   switch (op)
+   {
+   case TF_RRQ:   /* retry of original req? */
+   case TF_WRQ:
+      break;      /* silently ignore... */
+   case TF_DATA:
+      tfdodata(cn, p, len);
+      break;
+   case TF_ACK:
+      tfdoack(cn);
+      break;
+   case TF_ERROR:
+      tfdoerr(cn, p, len);
+      break;
+   default:
+      dtrap(); /* printf("TFTPRCV: Got bad opcode %u.\n", op); */
+      tfsnderr(cn, ILLTFTP, " ");
+      break;
+   }
+   check_state(cn);   /* see if we need to send something */
+}
+
+
+
+/* FUNCTION: tfkill()
+ *
+ * Kill a connection
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Mark the connection "dead", and set the timer to clean up later.
+ * Close any open files NOW.
+ */
+
+void
+tfkill(struct tfconn *cn)
+{
+   if (cn->tf_fd)
+   {
+      vfclose(cn->tf_fd);
+      cn->tf_fd = (VFILE *)NULL;
+   }
+   cn->tf_state = DEAD;             /* will get cleaned up later */
+   cn->tf_tick = cticks + TPS;      /* clean up after one second */
+}
+
+
+
+static int in_tftp_tick = 0;  /* re-entry guard */
+
+/* FUNCTION: tftp_tick()
+ *
+ * TFTP task/superlook handler
+ *
+ * PARAMS: none
+ *
+ * RETURNS: none
+ *
+ * This function scans all tftp connections to see if any states have
+ * timed out. This should be called on every received tftp packet and
+ * 1 second timer. 
+ */
+
+void
+tftp_tick(void)
+{
+   struct tfconn * cn, * nextcn;
+
+   if (in_tftp_tick)   /* avoid re-entring */
+      return;
+
+   in_tftp_tick++;
+
+   for (cn = tftp_conns; cn; cn = nextcn)
+   {
+      nextcn = cn->next;   /* in case cn is deleted in check_state */
+      if (cn->tf_tick > cticks)   /* time for state check? */
+         continue;
+      check_state(cn);
+   }
+
+   in_tftp_tick--;
+}
+
+
+
+/* FUNCTION: check_state()
+ *
+ * Check for activity on a TFTP connection
+ *
+ * PARAM1: struct tfconn *    TFTP connection block
+ *
+ * RETURNS: none
+ *
+ * Check the current state of a TFTP connection, and take the
+ * appropriate action.
+ */
+
+static void
+check_state(struct tfconn * cn)
+{
+   char *msg;
+
+   /* prevent clock ticks from re-entering. Do not exit
+   this routine without decrementing this counter! */
+   in_tftp_tick++;
+
+   switch (cn->tf_state)
+   {
+   case DATAWAIT:    /* waiting for data? */
+   case ACKWAIT:     /* waiting for ack? */
+   case SENTLAST:    /* sent last data block? */
+      if (cn->tf_tick <= cticks)   /* timeout now? */
+         tftptmo(cn);
+      break;
+   case TIMEOUT:
+      tfsnderr(cn, ERRTXT, "Retry limit exceeded, giving up");
+      if (cn->callback)
+         cn->callback(TFC_TIMEOUT, cn, "retry limit exceeded");
+      tfkill(cn);
+      break;
+   case RCVLASTDATA:   /* receive last incoming block of file */
+   case TERMINATED:   /* sent last outgoing block of file */
+      if (cn->callback)
+      {
+         if (cn->tf_size == 0L)
+            cn->callback(TFC_ZEROFILE, cn, "zero length file");
+         else
+         {
+            unsigned secs, tenths, elapsed;
+
+            msg = cn->tf_inbuf.data;
+            /* calculate elapsed ticks for transfer */
+            elapsed = (unsigned)(cticks - cn->tf_start);
+            /* convert to seconds and 10ths of a second */
+            secs = elapsed/TPS;
+            tenths = ((unsigned)(cticks - cn->tf_start) - (secs*TPS))/2;
+
+            sprintf(msg, "Transferred %lu bytes in %u.%u seconds", 
+                    cn->tf_size, secs, tenths);
+            cn->callback(TFC_SUCCESS, cn, msg);
+         }
+      }
+      cn->tf_state = DEAD;
+      break;
+   case RCVACK:   /* got an ack */
+      tfsndata(cn);      /* send more data */
+      break;
+   case RCVDATA:
+      tfsndack(cn);
+      break;
+   case DEAD:
+      tfcleanup(cn);
+      break;
+   default:
+      dtrap();   /* bad state */
+      if (cn->callback)
+         cn->callback(TFC_BADSTATE, cn, " ");
+      tfkill(cn);
+      break;
+   }
+   
+   in_tftp_tick--;
+}
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsfiles.c b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsfiles.c
new file mode 100644
index 0000000..2590a7e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsfiles.c
@@ -0,0 +1,1932 @@
+/*
+ * FILENAME: vfsfiles.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: VFS
+ *
+ * ROUTINES: vfopen(), set_vfopen_error(), get_vfopen_error(), 
+ * ROUTINES: vf_alloc_and_link_vop(), *vf_alloc_buffer(), vf_free_buffer(), 
+ * ROUTINES: vfopen_locked(), vfclose_locked(), vunlink_flag_open_files(),
+ * ROUTINES: vfread(), vfwrite_locked(), vfseek(), vftell(), vgetc_locked(),
+ * ROUTINES: vfslookup_locked(), (), vfslookup(), strippath(), 
+ * ROUTINES: isvfile_locked(), (), isvfile(), vferror(), vclearerr(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* vfsfiles.c 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * InterNIche virtual file system. This implements the vfopen(), 
+ * vfread(), etc, calls the Embedded WEB servers and similar devices 
+ * to do file IO. These calls lookup names, descriptors, etc, to see
+ * if the file is a "virtual" file in RAM/ROM/FLASH, or if it should 
+ * fall through to the local disk system (if any) 
+ * 7/24/96 - Created by John Bartas 
+ * 12/10/98 - Added RWVFS hooks for writable file support -JB- 
+ * 12/26/98 - Separated from WebPort sources. 
+ */
+
+#include "ipport.h"
+
+#ifdef VFS_FILES
+
+#include "vfsport.h"    /* per-port include */
+
+#include "vfsfiles.h"   /* overlay vfs stuff on system file IO */
+
+#include "profiler.h"   /* InterNiche profile utility */
+ 
+/* if this sort of thing is needed, it should probably be in ipport.h */
+#ifdef NOTDEF
+#ifdef HT_LOCALFS
+#include <fcntl.h>   /* Standard lib stuff for file IO */
+#include <io.h>
+#endif   /* HT_LOCALFS */
+#endif   /* NOTDEF */
+
+#ifdef WEBPORT
+#include "httpd.h"   /* local NetPort HTML includes */
+#include "cgi.h"
+#endif   /* WEBPORT */
+
+#ifdef HTML_COMPRESSION
+#include "htcmptab.h"   /* tag table, for compression */
+#endif   /* HTML_COMPRESSION */
+
+/* path to file system root. This must use UNIX slashes, and should not
+be NULL. A single slash is OK. */
+#ifdef HT_LOCALFS
+/* if there's a local FS (e.g. a disk), force vfs created files to 
+ * live in a special directory. This can be changed at startup 
+ * time.
+ */
+char     vfs_root_path[HTPATHMAX]   =  { "/vfs/" };
+#else /* the vfs is the whole file system */
+char     vfs_root_path[HTPATHMAX]   =  { "/" };
+#endif   /* HT_LOCALFS */
+
+#ifdef VFS_STRIPPATH
+/* preserve compatibility with old-style webport path */
+char *   http_root_path =  &vfs_root_path[0];
+#endif   /* VFS_STRIPPATH */
+
+#ifdef HT_EXTDEV
+/* list of alternate file IO routine sets */
+struct vfroutines *  vfsystems   =  NULL;
+#endif   /* HT_EXTDEV */
+
+
+#ifdef HT_RWVFS
+
+/* this counts the number of bytes that have been allocated for 
+ * buffers for the read/write file system so that the above maximum 
+ * can be enforced
+ */
+unsigned long vfs_total_rw_space;
+
+/* this counts the number of dynamically allocated files in the file
+   system so that the above maximum can be enforced */
+unsigned long vfs_total_dyna_files;
+
+/* this flag gets set during successful unlink operations so that
+ * vfs_sync() knows to sync the file system even though none of the 
+ * files in it show that they are stale
+ */
+int      vfs_dir_stale;
+
+#endif   /* HT_RWVFS */
+
+
+/* this counts the number of open files in the file system so that
+   the above maximum can be enforced */
+unsigned long vfs_open_files;
+
+#ifdef VFS_STRIPPATH
+char * strippath(char * name);
+#endif   /* VFS_STRIPPATH */
+
+VFILE * vfiles = NULL;  /* list of open files */
+
+/* list of files */
+struct vfs_file * vfsfiles =  NULL;
+
+#ifdef VFS_UNIT_TEST
+
+/* this flag determines whether the VFS logs the file names that are
+   passed to it */
+int      vfs_log_file_name =  0;
+
+#endif   /* VFS_UNIT_TEST */
+
+/* vfopen_error is used as a place to store errors that occur in vfopen() */
+/* the porting engineer might want to replace this with a macro that
+   defines vfopen to be errno, depending on his target system */
+int      vfopen_error   =  0;
+
+
+
+/* FUNCTION: set_vfopen_error()
+ * 
+ * this function sets the vfopen() error indication. it is called from
+ * vfopen() when errors occur
+ *
+ * PARAM1: int error
+ *
+ * RETURNS: 
+ */
+
+void set_vfopen_error(int error)
+{
+   vfopen_error = error;
+}
+
+
+
+/* FUNCTION: get_vfopen_error()
+ * 
+ * this function returns the last error that occurred in a call to 
+ * vfopen(). the porting engineer might want to define errno to be 
+ * equal to this function, depending on his target system 
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+int get_vfopen_error()
+{
+   return vfopen_error;
+}
+
+
+
+/* FUNCTION: vf_alloc_and_link_vop()
+ * 
+ * this function allocates a VFILE structure and links it to the
+ * beginning of the linked list of open files
+ *
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+VFILE * vf_alloc_and_link_vop()
+{
+   struct vfs_open * vop;
+
+   /* enforce maximum number of simultaneously open files */
+   if (vfs_open_files >= VFS_MAX_OPEN_FILES)
+   {
+#ifdef VFS_VERBOSE
+      dprintf("vfs_open_files too big (%ld) in vf_alloc_and_link_vop()\n",
+       vfs_open_files);
+#endif   /* VFS_VERBOSE */
+      return NULL;
+   }
+
+   /* allocate a structure to represent the open file */
+   vop = VFS_VFS_OPEN_ALLOC();
+
+   /* if the allocation succeeded */
+   if (vop)
+   {
+      /* add to the beginning of the list of open files */
+      vop->next = vfiles;
+      vfiles = vop;
+      /* increment the count of open files */
+      vfs_open_files++;
+   }
+#ifdef VFS_VERBOSE
+   else
+      dprintf("VFS_VFS_OPEN_ALLOC() failed in vf_alloc_and_link_vop()\n");
+#endif   /* VFS_VERBOSE */
+
+   return vop;
+}
+
+#ifdef HT_RWVFS
+
+
+
+/* FUNCTION: *vf_alloc_buffer()
+ * 
+ * PARAM1: unsigned long size
+ *
+ * RETURNS: 
+ */
+
+unsigned char * vf_alloc_buffer(unsigned long size)
+{
+   unsigned char *buffer;
+#ifdef MUTE_WARNS
+   unsigned int long_size,int_size;
+#endif   /* MUTE_WARNS */
+
+   /* make sure the requested allocation does not exceed the total
+      memory space reserved for file buffers */
+   if ((vfs_total_rw_space + size) > VFS_MAX_TOTAL_RW_SPACE)
+      return NULL;
+
+   /* the file sizes in the vfs_file structures are all unsigned 
+    * longs, but npalloc() only can allocate sizes expressed in 
+    * unsigned ints, so if your longs are bigger than your ints, you 
+    * can't allocate memory 
+    * any bigger than what will fit in an unsigned int 
+    */
+#ifdef MUTE_WARNS
+   /* the idiotic hoops you got to jump through to suppress compiler
+      warnings */
+   long_size   =  sizeof(unsigned   long);
+   int_size = sizeof(unsigned int);
+   if (long_size > int_size)
+#else
+   if (sizeof(unsigned long) > sizeof (unsigned int))
+#endif   /* MUTE_WARNS */
+   {
+      unsigned long mem_mask;
+
+      /* what this does is create a mem_mask containing 0xffff0000 on 
+       * most systems where this "if" expression will evaluate to 
+       * true (2 byte ints, 4 byte longs). if any of those upper bits 
+       * are on in your requested size, you otta luck.
+       */
+#ifdef MUTE_WARNS
+      switch (int_size)
+#else
+      switch (sizeof(unsigned int))
+#endif   /* MUTE_WARNS */
+      {
+      case 2 :
+         mem_mask = 0xffff0000;
+         break;
+         default :
+            dtrap();    /* you have a weird compiler */
+         return NULL;
+      }
+
+      if (size & mem_mask)
+         return NULL;
+   }
+
+   /* try to allocate a buffer of the requested size */
+   buffer = (unsigned char *) npalloc((unsigned int) size);
+
+   /* if the allocation succeeded */
+   if (buffer)
+   {
+      /* add size to the count of total buffer space allocated */
+      vfs_total_rw_space += size;
+   }
+
+   return buffer;
+}
+
+
+
+/* FUNCTION: vf_free_buffer()
+ * 
+ * PARAM1: unsigned char *buffer
+ * PARAM2: unsigned long size
+ *
+ * RETURNS: 
+ */
+
+void vf_free_buffer(unsigned char * buffer, unsigned long size)
+{
+   /* free the buffer */
+   if (buffer)
+      npfree(buffer);
+
+   /* and subtract its size from the total buffer space count */
+   vfs_total_rw_space -= size;
+}
+
+#endif   /* HT_RWVFS */
+
+
+
+/* FUNCTION: vfopen_locked()
+ * 
+ * PARAM1: char * name
+ * PARAM2: char * mode
+ *
+ * RETURNS: 
+ */
+
+VFILE *
+vfopen_locked(char * name, char * mode)
+{
+   struct vfs_file * vfp;
+   struct vfs_open * vop;
+
+   /* clear any previous vfopen() error */
+   set_vfopen_error(0);
+
+   /* the old code used to do special handling of '?' in files for 
+    * the benefit of the web server. the web server should be doing 
+    * this now. this is here to make sure that its doing it 
+    */
+   if (strchr(name,'?'))
+   {
+      dtrap();
+      return NULL;
+   }
+
+   /* determine if the file exists */
+   /* if the directory exists, vfp will point to its directory entry
+      structure else vfp will be NULL */
+   vfp = vfslookup_locked(name);
+
+   /* if the file exists */
+   if (vfp)
+   {
+
+#ifdef HT_RWVFS
+
+      /* if mode begins with 'w' we will truncate to end of file */
+      /* make sure the file is writable before proceeding */
+      if ((*mode == 'w') && !(vfp->flags & VF_WRITE))
+      {
+         set_vfopen_error(ENP_FILEIO);
+#ifdef VFS_VERBOSE
+         dprintf("mode w with no VF_WRITE\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+#endif   /* HT_RWVFS */
+
+      /* allocate a VFILE structure to represent the open file */
+      vop = vf_alloc_and_link_vop();
+
+      /* check for failure */
+      if (!vop)
+      {
+         set_vfopen_error(ENP_NOMEM);
+#ifdef VFS_VERBOSE
+         dprintf("vf_alloc_and_link_vop() failed 1\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+      /* link to the file's directory entry structure */
+      vop->file = vfp;
+
+      /* by default start at the beginning of the file */
+      /* note that vfp->data could be NULL at this point since empty
+         files might have no data buffer allocated to them */
+      vop->cmploc = vfp->data;   /* start at beginning of file */
+
+#ifdef HT_RWVFS
+
+      /* if mode begins with 'a', seek to end of file */
+      if (*mode == 'a')
+      {
+         if (vfp->data)
+         {
+            vop->cmploc = vfp->data + vfp->comp_size;
+         }
+      }
+
+      /* if mode begins with 'w', truncate to end of file */
+      if (*mode == 'w')
+      {
+         /* set the size of the file before compression to 0 */
+         vfp->real_size = 0;
+         /* set the size of the compressed data to 0 */
+         vfp->comp_size = 0;
+         /* note we leave the pointer to the file buffer and its length
+            alone since first writes will go to it */
+         /* flag that the file has been modified */
+         vfp->flags |= VF_STALE;
+
+         /* turn off the compression flag */
+         vfp->flags &= ~VF_HTMLCOMPRESSED;
+      }
+
+#endif   /* HT_RWVFS */
+
+      return vop;
+   }
+
+#ifdef HT_EXTDEV
+
+   /* if the mode implies that the file should be created if it
+      does not exist */
+   if (*mode != 'r')
+   {
+      /* see if one of the other systems wants to create this file */
+      /* if none of the below devices can open the file, continue on */
+      struct vfroutines *  vfs;
+
+      for (vfs = vfsystems; vfs; vfs = vfs->next)
+      {
+         if ((vop = vfs->r_fopen(name, mode)) != NULL)
+         {
+            return vop;
+         }
+      }
+   }
+
+#endif   /* HT_EXTDEV */
+
+#ifdef HT_LOCALFS
+   /* compare the passed name to a vfs_root_path. if the name does
+    * not begin with it, pass it to the native file 
+    * system fopen()
+    */
+   if (strncmp(name, vfs_root_path, strlen(vfs_root_path)))
+   {
+      return (VFILE *) fopen(name, mode);
+   }
+#endif   /* HT_LOCALFS */
+
+#ifdef HT_RWVFS
+
+   /* if the mode implies that the file should be created if it
+      does not exist */
+   if (*mode != 'r')
+   {
+      /* enforce maximum number of files */
+      if (vfs_total_dyna_files >= VFS_MAX_DYNA_FILES)
+      {
+         set_vfopen_error(ENP_NOMEM);
+#ifdef VFS_VERBOSE
+         dprintf("vf_total_dyna_files too big in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+      /* make sure the file name is not too long for the VFS */
+      if (strlen(name) > FILENAMEMAX)
+      {
+         set_vfopen_error(ENP_PARAM);
+#ifdef VFS_VERBOSE
+         dprintf("file name too long in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+      /* allocate a vfs_file structure to hold the new file entry in */
+      vfp = VFS_VFS_FILE_ALLOC();
+
+      /* check for memory allocation failure */
+      if (!vfp)
+      {
+         set_vfopen_error(ENP_NOMEM);
+#ifdef VFS_VERBOSE
+         dprintf("VFS_VFS_FILE_ALLOC() failed in vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+      /* allocate a VFILE structure to represent the open file */
+      vop = vf_alloc_and_link_vop();
+
+      /* check for memory allocation failure */
+      if (!vop)
+      {
+         VFS_VFS_FILE_FREE(vfp); /* free the allocated vfs_file entry */
+         set_vfopen_error(ENP_NOMEM);
+#ifdef VFS_VERBOSE
+         dprintf("vf_alloc_and_link_vop() failed 2\n");
+#endif   /* VFS_VERBOSE */
+         return NULL;
+      }
+
+      /* add the vfs_file structure to the head of the list */
+
+      vfp->next = vfsfiles;
+      vfsfiles = vfp;
+
+      /* increment count of total files */
+      vfs_total_dyna_files++;
+
+      /* remove leading directory separator before storing name */
+      if (*name == '/' || *name == '\\')
+         name++;
+
+      /* store the converted name in the directory entry structure */
+      strcpy(vfp->name,name);
+
+      /* set the flags */
+      vfp->flags = VF_DYNAMICINFO   /* the directory entry was allocated */
+      | VF_WRITE        /* the file is writable */
+      | VF_NONVOLATILE  /* the file is non-volatile */
+      | VF_STALE;       /* the file is stale */
+
+      /* the rest of the vfs_file structure fields remain with the 
+       * zeroes that npalloc() is guaranteed to init its data with. 
+       * note that this means the data pointer contains a null 
+       * because we don't allocate any buffer to hold the data 
+       * in until the first write 
+       */
+      /* link to the file's directory entry structure */
+      vop->file = vfp;
+
+      /* the cmploc and tag fields of the vop retain their NULLs from 
+       * npalloc(). cmploc contains NULL because there is no data 
+       * buffer to point to yet. tag contains NULL because no 
+       * decompression operation has started yet
+       */
+      return vop;
+   }
+
+#endif   /* HT_RWVFS */
+
+#ifdef HT_LOCALFS
+
+   /* pass the open to the local file system */
+   return (VFILE *) fopen(name,mode);
+
+#else
+
+   set_vfopen_error(ENP_NOFILE);
+#ifdef VFS_VERBOSE
+   dprintf("fell thru to end of vfopen_locked()\n");
+#endif   /* VFS_VERBOSE */
+   return NULL;
+
+#endif   /* HT_LOCALFS */
+}
+
+
+
+/* FUNCTION: vfopen()
+ * 
+ * PARAM1: char * name
+ * PARAM2: char * mode
+ *
+ * RETURNS: 
+ */
+
+VFILE *
+vfopen(char * name, char * mode)
+{
+   VFILE *vfd;
+
+#ifdef VFS_UNIT_TEST
+   if (vfs_log_file_name)
+      dprintf("vfopen() passed >%s<,%s\n",name,mode);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+
+   vfd = vfopen_locked(name,mode);
+
+   vfs_unlock();
+
+   return vfd;
+}
+
+
+
+/* FUNCTION: vfclose_locked()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+void 
+vfclose_locked(VFILE * vfd)
+{
+   VFILE * vtmp;
+   VFILE * vlast;
+
+   vlast = NULL;
+
+   /* see if vfd is in our list of open virtual files. We
+      can't use isvfile() since we need a pointer to last. */
+   vtmp = vfiles;
+   while (vtmp)
+   {
+      /* if this is the one we are looking for, exist search loop */
+      if (vfd == vtmp)
+         break;
+
+      /* bump the next and previous pointers along to try the next one */
+      vlast = vtmp;
+      vtmp = vtmp->next;
+   }
+
+   /* if the passed in handle was not in the list we maintain */
+   if (vfd != vtmp)
+   {
+
+#ifdef HT_LOCALFS
+      /* default to call on local system */
+      fclose((FILE*)vfd);
+#endif   /* HT_LOCALFS */
+      return;
+   }
+
+   /* the passed in handle is in the list we maintain */
+
+   /* this not really a forever loop. it exists so we can break easily
+      and deal with all the ifdefs */
+   while (1)
+   {
+      struct vfs_file * vfp   =  vfd->file;
+#ifdef HT_RWVFS
+      unsigned char *new_buffer;
+
+      /* vfd->file will be null if somebody unlinked the file after
+       * this handle was created to point to it. if the file itself 
+       * is gone there is nothing left to do, so break to list 
+       * deletion code at bottom of loop
+       */
+      if (vfp == NULL)
+         break;
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfp->method)
+      {
+         /* call that file system's fclose() */
+         struct vfroutines *  vfs   =  (struct  vfroutines*)(vfp->method);
+
+         vfs->r_fclose(vfd);
+         break;   /* break to list deletion code after end of phoney loop */
+      }
+#endif   /* HT_EXTDEV */
+
+#ifdef HT_RWVFS
+
+      /* if the buffer containing the data was allocated dynamically, 
+       * and there are VFS_CLOSE_FRAG_FLOOR bytes of unused data 
+       * between the end of the file and the end of the buffer 
+       */
+      if ((vfp->flags & VF_DYNAMICDATA) &&
+          ((vfp->buf_size - vfp->comp_size) > VFS_CLOSE_FRAG_FLOOR) &&
+          vfp->data) /* this last test is a sanity check */
+      {
+         /* try to reclaim the unused data */
+
+         /* allocate a new buffer just big enough for the data */
+         new_buffer = vf_alloc_buffer(vfp->comp_size);
+
+         /* if the allocation worked */
+         if (new_buffer)
+         {
+            /* copy the old buffer to the new one */
+            MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size));
+            /* free the old buffer */
+            vf_free_buffer(vfp->data,vfp->buf_size);
+            /* update the buffer pointer and size to reflect the
+               just big enough buffer */
+            vfp->data = new_buffer;
+            vfp->buf_size = vfp->comp_size;
+         }
+      }
+
+#ifdef VFS_AUTO_SYNC
+      /* if the file's flags indicate that the file is non-volatile
+         and that it has been changed */
+      if ((vfp->flags & (VF_NONVOLATILE | VF_STALE)) ==
+          (VF_NONVOLATILE | VF_STALE))
+      {
+         /* store the non-volatile files to whatever backing store 
+          * the system provides. note that it is up to the vfs_sync() 
+          * function to clear the VF_STALE bits in whatever files it 
+          * successfully stores. this way if a given attempt fails, 
+          * the unsuccessfully saved files get another chance on the 
+          * next call to vfs_sync(). note also that the sync function 
+          * is passed the pointer to the vfs_file so that if all it 
+          * does is sync the single file, then only that 
+          * file's VF_STALE flag can be cleared. 
+          */
+         vfs_sync(vfp);
+      }
+#endif   /* VFS_AUTO_SYNC */
+
+#endif   /* HT_RWVFS */
+
+      /* break to list deletion code below */
+      break;
+
+   }
+
+   if (vlast)  /* unlink from list of open files */
+      vlast->next = vtmp->next;
+   else
+      vfiles = vtmp->next;
+
+   /* free structure addressed by open handle */
+   VFS_VFS_OPEN_FREE(vtmp);
+   /* decrement the number of open files */
+   vfs_open_files--;
+   return;
+}
+
+
+
+/* FUNCTION: vfclose()
+ * 
+ * PARAM1: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+void vfclose(VFILE * vfd)
+{
+   vfs_lock();
+
+   vfclose_locked(vfd);
+
+   vfs_unlock();
+}
+
+/* FUNCTION: vfflush()
+ * 
+ * PARAM1: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+int vfflush(VFILE * vfd)
+{
+   vfs_lock();
+
+   printf("vfflush(): This function needs to be implemented\n");
+
+   vfs_unlock();
+   return(0);
+}
+
+char * vfgets(char * s, int lim, VFILE * fp) 
+{
+   int   c   = EOF;
+   char* ret = s;
+
+   while ( --lim > 0 && (c = vgetc(fp)) != EOF)
+      if (( *ret ++ = c) == '\n')
+         break;
+   *ret = '\0';
+   return ( c == EOF && ret == s) ? NULL : s;
+}
+ 
+/* FUNCTION: vfeof()
+ * 
+ * PARAM1: VFILE *vfd
+ *
+ * RETURNS: 1 if the file pointer is at EOF, otherwise 0
+ */
+ 
+int vfeof(VFILE * vfd)
+{
+   int c = 0;
+
+#ifdef HT_LOCALFS
+   return(feof((FILE*)vfd));
+#endif
+   if ((c = vgetc(vfd)) == EOF )
+   {
+      return 1;
+   }   
+   return 0;
+}
+
+#ifdef HT_RWVFS
+
+
+
+/* FUNCTION: vunlink_flag_open_files()
+ * 
+ * fix up references to deleted file in list of currently 
+ * open VFILEs 
+ *
+ * PARAM1: struct vfs_file *vfp
+ *
+ * RETURNS: 
+ */
+
+void vunlink_flag_open_files(struct vfs_file * vfp)
+{
+   VFILE * vtmp;
+
+   /* for all open files */
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+   {
+      /* if the open file handle is referencing the file we are
+         deleting, set that reference to NULL */
+      if (vtmp->file == vfp)
+         vtmp->file = NULL;
+   }
+}
+
+#endif   /* HT_RWVFS */
+
+
+
+/* FUNCTION: vunlink()
+ * 
+ * PARAM1: char *name
+ *
+ * RETURNS: 
+ */
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Change prototype from char * name to const char to
+ * follow C library standard.
+ */
+int
+vunlink(const char * const_name)
+{
+   struct vfs_file * vfp;
+   int   rc =  0;
+#ifdef VFS_AUTO_SYNC
+   int   do_sync  =  0;
+#endif
+#ifdef   HT_RWVFS
+   struct vfs_file * vtmp;
+   struct vfs_file * vflast;
+   struct vfs_file * vfnext;
+#endif
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Change prototype from char * name to const char to
+ * follow C library standard.
+ */
+   char * name = malloc(strlen(const_name)+1);
+   strcpy(name, const_name);
+
+#ifdef VFS_UNIT_TEST
+   if (vfs_log_file_name)
+      dprintf("vunlink() passed >%s<\n",name);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* see if the converted name is one of the one's in our list */
+   /* if it isn't */
+   if ((vfp = vfslookup_locked(name)) == NULL)
+   {
+      vfs_unlock();
+
+#ifdef HT_LOCALFS
+      /* default to call on local system */
+      return remove(name);
+#else
+      /* no local file system, so return error condition */
+      free(name);
+      return -1;
+#endif   /* HT_LOCALFS */
+   }
+
+#ifdef   HT_RWVFS
+   /* save the next link pointer since in one path through the code, 
+    * the vfs_file structure gets freed before its unlinked from the 
+    * list
+    */
+   vfnext = vfp->next;
+
+   /* search list of files to determine predecessor in list */
+   vflast = NULL;
+   for (vtmp = vfsfiles; vtmp != NULL; vtmp = vtmp->next)
+   {
+      if (vtmp == vfp)
+         break;
+      vflast = vtmp;
+   }
+
+   /* this shouldn't happen since vfslookup_locked() already searched
+      the list, but just in case */
+   if (vtmp == NULL)
+   {
+      dtrap();
+      vfs_unlock();
+      free(name);
+      return -1;
+   }
+
+   /* this is not really a forever loop. it exists so we can break easily
+      and deal with all the ifdefs */
+   while (1)
+   {
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfp->method)
+      {
+         /* call that file system's unlink() */
+         struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfp->method);
+
+         rc = vfs->r_unlink(name);
+         break;   /* break to list deletion code after end of phoney loop */
+      }
+#endif   /* HT_EXTDEV */
+
+      /* if the file is not write enabled, return error condition */
+      if (!(vfp->flags & VF_WRITE))
+      {
+         vfs_unlock();
+         free(name);
+         return -1;
+      }
+
+      /* if the data buffer containing the file's data was dynamically
+         allocated and is not null */
+      if ((vfp->flags & VF_DYNAMICDATA) && (vfp->data))
+      {
+         /* free the buffer */
+         vf_free_buffer(vfp->data,vfp->buf_size);
+      }
+
+      /* if the vfs_file structure itself was allocated dynamically */
+      if (vfp->flags & VF_DYNAMICINFO)
+      {
+         /* decrement count of total files */
+         vfs_total_dyna_files--;
+
+         /* free the vfs_file structure */
+         VFS_VFS_FILE_FREE(vfp);
+      }
+
+      /* since we modified the list we maintain, do a sync, but after
+         the vfs_file has been deleted from the list */
+#ifdef VFS_AUTO_SYNC
+      do_sync = 1;
+#endif
+      /* we were successful at our unlink */
+      rc = 0;
+
+      break;
+   }
+
+   /* delete the vfs_file structure from the list headed by vfsfiles */
+   if (vflast)
+      vflast->next = vfnext;
+   else
+      vfsfiles = vfnext;
+
+   /* fix up references to deleted file in list of currently open VFILEs */
+   vunlink_flag_open_files(vfp);
+
+   /* flag that the directory is stale so vfs_sync() knows it has to do
+      something */
+   vfs_dir_stale = TRUE;
+
+#ifdef VFS_AUTO_SYNC
+   /* if we need to sync the backing store, call the function to do it */
+   if (do_sync)
+   {
+      /* a NULL passed to vfs_sync() means that only the directory
+         structure itself was changed */
+      vfs_sync(NULL);
+   }
+#endif   /* VFS_AUTO_SYNC */
+
+#else    /* HT_RWVFS */
+
+   /* unlinks not allowed on read-only VFS */
+   rc = -1;
+
+#endif   /* HT_RWVFS */
+   vfs_unlock();
+   free(name);
+   return rc;
+}
+
+
+
+/* FUNCTION: vfread()
+ * 
+ * vfread() - fread for vfs. if vfd parm is a vfs handle, this gets 
+ * data from the virtual file system, doing uncompression on the fly. 
+ * If vfd is not in vfs, this can be ifdefed to fall to a native 
+ * fread() call. Parameters and returns are identical to fread(); 
+ *
+ * PARAM1: char * buf
+ * PARAM2: unsigned size
+ * PARAM3: unsigned items
+ * PARAM4: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int 
+vfread(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+   unsigned bcount;  /* number of bytes put in caller's buffer */
+
+   IN_PROFILER(PF_FS, PF_ENTRY);
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* if the file is in our list of open files */
+   if (isvfile_locked(vfd))
+   {
+
+#ifdef HT_RWVFS
+      /* the caller is trying to read a handle to a file that's been
+         deleted, so he gets 0 data back */
+      if (vfd->file == NULL)
+      {
+         vfs_unlock();
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return 0;
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      /* if the file was created by an external file system */
+      if (vfd->file->method)
+      {
+         struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfd->file->method);
+         int   rc;
+
+         /* call that system's fread() */
+         rc = vfs->r_fread(buf,size,items,vfd);
+         vfs_unlock();
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return rc;
+      }
+#endif   /* HT_EXTDEV */
+
+#ifdef HT_RWVFS
+      /* the data pointer can be NULL if somebody tries to read from 
+       * a freshly created file, in which case there is no data in 
+       * the file, so return 0
+       */
+      if (!(vfd->file->data))
+      {
+         vfs_unlock();
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return 0;
+      }
+#endif   /* HT_RWVFS */
+
+      bcount = items * size;  /* number of bytes to transfer */
+
+#ifdef HTML_COMPRESSION
+      if (vfd->file->flags & VF_HTMLCOMPRESSED)
+      {
+         int   chr;  /* next char to process */
+
+         while (bcount)
+         {
+            chr = vgetc_locked(vfd);
+            if (chr == EOF)
+            {
+               vfs_unlock();
+               IN_PROFILER(PF_FS, PF_EXIT);
+               return(((items*size)-bcount)/size);
+            }
+
+            *buf++ = (char)chr;
+            bcount--;
+         }
+         vfs_unlock();
+         IN_PROFILER(PF_FS, PF_EXIT);
+         return(items); /* filled user buffer, return # items copied */
+      }
+      else  /* else fall to faster non-compression code */
+#endif   /* HTML_COMPRESSION */
+      {  /* get here to do simple uncompressed data read */
+         unsigned location = vfd->cmploc - vfd->file->data;
+
+         if (((unsigned long)location + bcount) > vfd->file->comp_size)
+            bcount = (unsigned)(vfd->file->comp_size - location);
+         MEMCPY(buf, vfd->cmploc, bcount);
+         vfd->cmploc += bcount;
+      }
+      vfs_unlock();
+      IN_PROFILER(PF_FS, PF_EXIT);
+      return (bcount/size);
+   }
+
+   vfs_unlock();
+   IN_PROFILER(PF_FS, PF_EXIT);
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(fread(buf, size, items, (FILE*)vfd));
+#else
+   return 0;
+#endif   /* HT_LOCALFS */
+}
+
+/* VFS_WRITE_BUF_INC defines how much the size of the buffer used to
+   store file system data is increased at a time */
+#define  VFS_WRITE_BUF_INC 8192
+#define VFS_ROUND_UP(x) \
+   (((((x) - 1) / VFS_WRITE_BUF_INC) + 1) * VFS_WRITE_BUF_INC)
+
+
+
+/* FUNCTION: vfwrite_locked()
+ * 
+ * PARAM1: char * buf
+ * PARAM2: unsigned size
+ * PARAM3: unsigned items
+ * PARAM4: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+int 
+vfwrite_locked(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+#ifndef HT_RWVFS
+#ifndef HT_LOCALFS
+#ifndef HT_EXTDEV
+
+   /* if the file is in our list of files */
+   if (isvfile_locked(vfd))
+   {
+      vfd->error = ENP_LOGIC;
+      return 0;
+   }
+
+   /* I know this is ugly but its the simplist way I can figure to 
+    * suppress those annoying "parameter not used" compiler warnings. 
+    * its a damned shame given that it results in the 
+    * generation of superfluous code
+    */
+   USE_ARG(buf);
+   USE_ARG(size);
+   USE_ARG(items);
+
+   return EBADF;
+
+#endif   /* HT_EXTDEV */
+#endif   /* HT_LOCALFS */
+#endif   /* HT_RWVFS */
+
+#ifdef HT_RWVFS
+   unsigned int bcount; /* number of bytes to write */
+   unsigned long current_offset;
+   struct vfs_file * vfp;
+#endif   /* HT_RWVFS */
+
+   /* if the file is not in our list of files */
+   if (!isvfile_locked(vfd))
+   {
+#ifdef HT_LOCALFS
+      /* default to call on local system */
+      return(fwrite(buf, size, items, (FILE*)vfd));
+#else
+      return EBADF;
+#endif   /* HT_LOCALFS */
+
+   }
+   /* this file is in our list of files */
+
+#ifdef HT_EXTDEV
+   /* if the file was created by an external file system */
+   if (vfd->file->method)
+   {
+      struct vfroutines *  vfs   =  (struct  vfroutines*)   (vfd->file->method);
+      int   rc;
+
+      /* call that system's fwrite() */
+      rc = vfs->r_fwrite(buf,size,items,vfd);
+      return rc;
+   }
+#endif
+
+   /* if we don't support writes, set an error */
+#ifndef HT_RWVFS
+
+   vfd->error = ENP_LOGIC;
+   return 0;
+
+#else    /* HT_RWVFS */
+
+   /* the caller is trying to write to a file that's been deleted,
+      so he writes 0 data */
+   if (vfd->file == NULL)
+   {
+      return 0;
+   }
+
+   vfp = vfd->file;
+
+   /* if the file is not writable, return error condition */
+   if (!(vfp->flags & VF_WRITE))
+   {
+      vfd->error = ENP_FILEIO;
+      return 0;
+   }
+
+   /* compute number of bytes to write */
+   bcount = size * items;
+
+   /* get rid of this degenerate case up front */
+   if (bcount == 0)
+   {
+      return 0;
+   }
+
+   /* if the file currently has no data buffer */
+   if (vfp->data == NULL)
+   {
+      /* compute the size of the buffer to be created */
+      /* we round up the size of the data to be written so we dont have
+         the overhead of a memory allocation on every write */
+      unsigned long buf_size = VFS_ROUND_UP((unsigned long)bcount);
+
+      /* allocate a buffer of that size */
+      vfp->data = vf_alloc_buffer(buf_size);
+
+      /* if the allocation failed */
+      if (!(vfp->data))
+      {
+         vfd->error = ENP_NOMEM;
+         return 0;
+      }
+
+      /* store the size of the allocated buffer */
+      vfp->buf_size = buf_size;
+
+      /* store the number of bytes written in the real and compressed
+         file sizes */
+      vfp->real_size = bcount;
+      vfp->comp_size = bcount;
+
+      /* set the file pointer to the first byte following the last
+         byte written */
+      vfd->cmploc = vfp->data + bcount;
+
+      /* turn off the compression flag */
+      vfp->flags &= ~VF_HTMLCOMPRESSED;
+
+      /* the data in the file is stale */
+      vfp->flags |= VF_STALE;
+
+      /* the buffer data was dynamically allocated */
+      vfp->flags |= VF_DYNAMICDATA;
+
+      /* copy the data to be written to the file buffer */
+      MEMCPY(vfp->data,buf,bcount);
+
+      /* return the number of "items" written */
+      return items;
+   }
+
+   /* compute the current offset into the file */
+   current_offset = vfd->cmploc - vfp->data;
+
+   /* if the data to be written wont fit into the file buffer */
+   if ((current_offset + bcount) > vfp->buf_size)
+   {
+      /* compute the size of a new buffer to hold the data */
+      unsigned long new_buf_size = VFS_ROUND_UP(current_offset + bcount);
+      unsigned char *new_buffer;
+
+      /* allocate a new buffer */
+      new_buffer = vf_alloc_buffer(new_buf_size);
+
+      /* check for allocation failure */
+      if (!new_buffer)
+      {
+         vfd->error = ENP_NOMEM;
+         return 0;
+      }
+
+      /* copy the old buffer contents to the new buffer */
+      MEMCPY(new_buffer,vfp->data,(unsigned int) (vfp->comp_size));
+
+      /* if the old buffer had been dynamically allocated */
+      if (vfp->flags & VF_DYNAMICDATA)
+      {
+         /* free it */
+         vf_free_buffer(vfp->data,vfp->buf_size);
+      }
+
+      /* store the new buffer in the file structure */
+      vfp->data = new_buffer;
+
+      /* store the new buffer size in the file structure */
+      vfp->buf_size = new_buf_size;
+
+      /* the new buffer was dynamically allocated */
+      vfp->flags |= VF_DYNAMICDATA;
+
+      /* set the current file pointer to point into the new data 
+       * buffer note that this means the VFS does not support 
+       * simultaneous opens of the same file, since for that to work, 
+       * all the other cmploc's that point to this file would 
+       * have to be updated also 
+       */
+      vfd->cmploc = vfp->data + current_offset;
+   }
+
+   /* copy the data to the current file pointer */
+   MEMCPY(vfd->cmploc,buf,bcount);
+
+   /* update the current file pointer */
+   vfd->cmploc += bcount;
+
+   /* if the resulting current offset is greater than the file size */
+   if (current_offset + bcount > vfp->comp_size)
+   {
+      /* update the "compressed" file size */
+      vfp->comp_size = current_offset + bcount;
+   }
+
+   /* since we turn off the compression bit below, the "real" size and
+      the compressed size must be the same */
+   vfp->real_size = vfp->comp_size;
+
+   /* turn off the compression flag */
+   vfp->flags &= ~VF_HTMLCOMPRESSED;
+
+   /* the data in the file is stale */
+   vfp->flags |= VF_STALE;
+
+   /* return the number of "items" written */
+   return items;
+
+#endif   /* HT_RWVFS */
+}
+
+
+
+/* FUNCTION: vfwrite()
+ * 
+ * vfwrite() - This is included to support integration with native 
+ * file systems. Parameters and returns are identical to fwrite(); 
+ * except that on some error conditions EBADF is returned instead of 
+ * 0 
+ *
+ * PARAM1: char * buf
+ * PARAM2: unsigned size
+ * PARAM3: unsigned items
+ * PARAM4: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+int
+vfwrite(char * buf, unsigned size, unsigned items, VFILE * vfd)
+{
+   int   rc;
+
+   IN_PROFILER(PF_FS, PF_ENTRY);
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* do the write */
+   rc = vfwrite_locked(buf, size, items, vfd);
+
+   /* unlock the VFS */
+   vfs_unlock();
+
+   IN_PROFILER(PF_FS, PF_EXIT);
+
+   return rc;
+}
+
+
+
+
+/* FUNCTION: vfseek()
+ * 
+ * vfseek : Returns 0 on success. Otherwise returns a nonzero value.
+ *
+ * PARAM1: VFILE * vfd
+ * PARAM2: long offset
+ * PARAM3: int mode
+ *
+ * RETURNS: 
+ */
+
+int 
+vfseek(VFILE * vfd, long offset, int mode)
+{
+   /* lock the VFS */
+   vfs_lock();
+
+   if (isvfile_locked(vfd))
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to seek a file that's been deleted,
+         so return an error indication */
+      if (vfd->file == NULL)
+      {
+         vfs_unlock();
+         return -1;
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+      {
+         struct vfroutines *vfp = (struct vfroutines*)(vfd->file->method);
+         int   rc;
+
+         rc = vfp->r_fseek(vfd, offset, mode);
+         vfs_unlock();
+         return rc;
+      }
+#endif   /* HT_EXTDEV */
+      /* this vfseek() currently only supports seek to exact
+         end or begining of file */
+      switch (mode)
+      {
+      case SEEK_SET:
+         vfd->cmploc = vfd->file->data + offset;
+         break;
+      case SEEK_CUR:
+         /* If the file is compressed, then the following
+          * adjustment is inaccurate. Currently we don't have
+          * any scenario where this happens. - handle later */
+         vfd->cmploc += offset; 
+         break;
+      case SEEK_END:
+         vfd->cmploc = vfd->file->data + vfd->file->comp_size + offset;
+         break;
+      }
+      vfs_unlock();
+      return(0);
+   }
+
+   vfs_unlock();
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(fseek((FILE*)vfd, offset, mode));
+#else
+   return -1;
+#endif   /* HT_LOCALFS */
+}
+
+
+
+/* FUNCTION: vftell()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+long
+vftell(VFILE * vfd)
+{
+   /* lock the VFS */
+   vfs_lock();
+
+   if (isvfile_locked(vfd))
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to ftell a deleted file,
+         so return an error condition */
+      if (vfd->file == NULL)
+      {
+         vfs_unlock();
+         return -1;
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+      {
+         struct vfroutines *  vfp   =  (struct  vfroutines*)   (vfd->file->method);
+         long  rc;
+
+         rc = vfp->r_ftell(vfd);
+         vfs_unlock();
+         return rc;
+      }
+#endif   /* HT_EXTDEV */
+      /* if file has been fseeked to end, return uncompressed size.
+         else return current location in compression stream */
+      if (vfd->cmploc == vfd->file->data + vfd->file->comp_size)
+      {
+         vfs_unlock();
+
+         return vfd->file->comp_size;
+      }
+      else
+      {
+         vfs_unlock();
+
+         return (vfd->cmploc - vfd->file->data);
+      }
+   }
+
+   vfs_unlock();
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(ftell((FILE*)vfd));
+#else
+   return EBADF;
+#endif   /* HT_LOCALFS */
+}
+
+
+
+/* FUNCTION: vgetc_locked()
+ * 
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int
+vgetc_locked(VFILE * vfd)
+{
+   int   chr;
+
+   if (isvfile_locked(vfd))
+   {
+#ifdef HT_RWVFS
+      /* the caller is trying to read a file that's been deleted,
+         so return an error condition */
+      if (vfd->file == NULL)
+      {
+         return EOF;
+      }
+#endif   /* HT_RWVFS */
+
+#ifdef HT_EXTDEV
+      if (vfd->file->method)
+      {
+         struct vfroutines *  vfp   =  (struct  vfroutines*)   (vfd->file->method);
+         return (vfp->r_fgetc(vfd));
+      }
+#endif   /* HT_EXTDEV */
+
+#ifdef HT_RWVFS
+      /* a freshly created file might not have a data buffer associated
+         with it yet */
+      if (vfd->file->data == NULL)
+         return EOF;
+
+#endif   /* HT_RWVFS */
+
+#ifdef HTML_COMPRESSION
+      if (vfd->file->flags & VF_HTMLCOMPRESSED)
+      {
+         if (vfd->tag)  /* last read ended inside a tag? */
+         {
+            chr = *vfd->tag++;
+            if (chr == '\0')  /* at end of tag? */
+            {
+               vfd->tag = NULL;  /* clear tag flag */
+               if (vfd->cmploc >= (vfd->file->data + vfd->file->comp_size))
+                  return EOF;
+               else
+                  chr = *vfd->cmploc++;   /* get next char from file */
+            }
+            else  /* got valid char from inside tag */
+               return (chr);
+         }
+         else  /* not in a tag; get next char in file */
+         {
+            if (vfd->cmploc >= (vfd->file->data + vfd->file->comp_size))
+               return EOF;
+            else
+               chr = *vfd->cmploc++;
+         }
+#ifdef FOREIGN_LANG_SUPPORT
+         if (chr == NP_ESCAPE_CHAR )      /* escape char ? */
+         {
+            /* If the current char is an ESCAPE char, then
+             * we are interested in the next char 
+             * Then next char has HIGH-BIT-SET, and it is
+             * not a HTML TAG */
+            chr = *vfd->cmploc++;
+         }
+         else
+#endif
+         if (chr & 0x80)   /* compressed HTML tag? */
+         {
+            /* find tag and insert it as source */
+            vfd->tag = (u_char*) htmltags[chr & 0x7f];
+            chr = *vfd->tag++;
+         }
+      }
+      else  /* HTML compression flag not set */
+      {
+#endif   /* HTML_COMPRESSION */
+         /* Check to see if read has advanced to end of file */
+         if (vfd->cmploc >= (vfd->file->data + vfd->file->comp_size))
+            chr = EOF;
+         else  /* else just get next char to return */
+            chr = *(vfd->cmploc++);
+#ifdef HTML_COMPRESSION
+      }  /* need to close brace form if...else; */
+#endif   /* HTML_COMPRESSION */
+
+      return chr;
+   }
+
+#ifdef HT_LOCALFS
+   /* default to call on local system */
+   return(getc((FILE*)vfd));
+#else
+   dtrap(); /* can this happen? */
+   return EOF;
+#endif   /* HT_LOCALFS */
+}
+
+
+
+/* FUNCTION: vgetc()
+ * 
+ * PARAM1: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+int
+vgetc(VFILE * vfd)
+{
+   int   rc;
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* get the character */
+   rc = vgetc_locked(vfd);
+
+   /* unlock the VFS */
+   vfs_unlock();
+   return rc;
+}
+
+
+
+
+/* FUNCTION: vfslookup_locked()
+ * 
+ * vfn_lookup() - lookup a vfs_file entry by name. Pass file name may 
+ * have path prepended and/or cgi parameters appended. Return pointer 
+ * to vfs_file struct if it exists, else NULL. 
+ * 
+ * vfslookup_locked() should be called by functions internal to the
+ * VFS that have already locked the VFS
+ *
+ * PARAM1: char * name
+ *
+ * RETURNS: 
+ */
+
+struct vfs_file * 
+vfslookup_locked(char * name)
+{
+   struct vfs_file * vp;
+
+#ifdef VFS_STRIPPATH
+   char *   cp;
+
+   /* If root path is prepended to name, skip past it */
+   if (*name == '/' || *name == '\\')
+   {
+      cp = strippath(name);
+
+      if (!cp) /* strippath coundn't match our path */
+      {
+         /* Files like "/hub47.gif" need to be taken care of */
+         if (*name == '/' || *name == '\\')
+            name++;
+      }
+      else
+         name = cp ;
+   }
+#endif   /* VFS_STRIPPATH */
+
+   /* see if there is a question mark in the file name */
+   if (strchr(name,'?'))
+   {
+      dtrap(); /* is this still allowed? */
+      return NULL;
+   }
+
+   for (vp = vfsfiles; vp; vp = vp->next)    /* search vfs list for name */
+   {
+      if (strcmp(name, vp->name) == 0)
+         return vp;
+   }
+
+   return NULL;   /* fall to here if not found in for loop */
+}
+
+
+
+/* FUNCTION: vfslookup()
+ * 
+ * vfslookup() should be called by code that is external to the VFS
+ * (like the web server) that has not locked the VFS
+ *
+ * PARAM1: char * name
+ *
+ * RETURNS: 
+ */
+
+struct vfs_file * 
+vfslookup(char * name) 
+{
+   struct vfs_file * vp;
+
+#ifdef VFS_UNIT_TEST
+   if (vfs_log_file_name)
+      dprintf("vfslookup() passed >%s<\n",name);
+#endif   /* VFS_UNIT_TEST */
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* do the lookup */
+   vp = vfslookup_locked(name);
+
+   /* unlock the VFS */
+   vfs_unlock();
+   return vp;
+}
+
+#ifdef VFS_STRIPPATH
+
+
+
+/* FUNCTION: strippath()
+ * 
+ * strippath() - Compares the path prepended to a passed file 
+ * path/name to the http_root_path variable. If the passed file 
+ * path/name matches http_root_path, it strips http_root_path from 
+ * the path/name and returns the remaining path/name portion for 
+ * lookup in the cfs table. 
+ *
+ * PARAM1: char * name
+ *
+ * RETURNS: Returns NULL if passed path/name does NOT 
+ * have the http_root_path prepended; or on any error. 
+ */
+
+char * 
+strippath(char * name)
+{
+   char *   path; /* pointer into system path */
+   char *   ptmp; /* another pointer into path */
+   char *   ntmp; /* pointer into name text */
+   int   dirlen;
+
+   ntmp = uslash(name);      /* uslash() is defined in misclib\in_utils.c */
+   path = http_root_path; /* The servers root path, at least one UNIX slash */
+   while (*path && *ntmp)
+   {
+      while (*path == '/') path++;   /* strip leading slash */
+         if (*path == 0)
+         break;
+      /* find number of chars in this directory layer's name */
+      ptmp = strchr(path, '/');   /* location of next slash in path */
+      if (ptmp)
+         dirlen = ptmp - path;
+      else
+         dirlen = strlen(path);
+
+      while (*ntmp == '/') ntmp++;   /* strip leading slash */
+         if (strncmp(ntmp, path, dirlen) == 0)
+      {
+         path += dirlen;
+         ntmp += dirlen;
+      }
+      else
+         return NULL;   /* didn't match */
+   }
+   if (*path == '\0')
+   {
+      while (*ntmp == '\\' || *ntmp == '/')
+         ntmp++;
+      return ntmp;
+   }
+   else
+      return NULL;
+}
+
+#endif   /* VFS_STRIPPATH */
+
+
+
+/* FUNCTION: isvfile_locked()
+ * 
+ * isvfile_locked() should be called by functions internal to the VFS
+ * that have already locked it
+ *
+ * PARAM1: VFILE *vfp
+ *
+ * RETURNS: 
+ */
+
+int
+isvfile_locked(VFILE * vfp)
+{
+   VFILE * vtmp;
+
+   for (vtmp = vfiles; vtmp; vtmp = vtmp->next)
+      if (vtmp == vfp)
+      return TRUE;
+
+   return FALSE;  /* passed pointer not found in list */
+}
+
+
+
+/* FUNCTION: isvfile()
+ * 
+ * isvfile() should be called by code that is external to the VFS
+ * (like the web server) that has not locked the VFS
+ *
+ * PARAM1: VFILE *vfp
+ *
+ * RETURNS: 
+ */
+
+int
+isvfile(VFILE * vfp)
+{
+   int   rc;
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* do the lookup */
+   rc = isvfile_locked(vfp);
+
+   /* unlock the VFS */
+   vfs_unlock();
+   return rc;
+}
+
+
+
+/* FUNCTION: vferror()
+ * 
+ * vferror() - get last error (if any) for passed file. The type of 
+ * error will vary with implementation, however 0 should always be 
+ * "no error". 
+ *
+ * PARAM1: VFILE * vfd
+ *
+ * RETURNS: 
+ */
+
+int
+vferror(VFILE * vfd)
+{
+   /* lock the VFS */
+   vfs_lock();
+
+   if (isvfile_locked(vfd))
+   {
+      vfs_unlock();
+
+      return vfd->error;
+   }
+
+   vfs_unlock();
+
+#ifdef HT_LOCALFS
+   return(ferror((FILE*)vfd));
+#else /* not a VFILE, and no local FS */
+   return -1;  /* should this be an error? */
+#endif   /* HT_LOCALFS */
+}
+
+
+
+/* FUNCTION: vclearerr()
+ * 
+ * PARAM1: VFILE *vfd
+ *
+ * RETURNS: 
+ */
+
+void vclearerr(VFILE * vfd)
+{
+   /* lock the VFS */
+   vfs_lock();
+
+   if (isvfile_locked(vfd))
+   {
+      vfs_unlock();
+
+      vfd->error = 0;
+      return;
+   }
+
+   vfs_unlock();
+
+#ifdef HT_LOCALFS
+   clearerr((FILE *) vfd);
+#endif   /* HT_LOCALFS */
+}
+
+#endif   /* VFS_FILES */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.c b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.c
new file mode 100644
index 0000000..15749cf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.c
@@ -0,0 +1,108 @@
+/*
+ * FILENAME: vfsport.c
+ *
+ * Copyright 2002 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: VFS
+ *
+ * ROUTINES: vfs_nvset(), prep_vfs().
+ *
+ * PORTABLE: NO
+ */
+
+#include "ipport.h"
+#include "libport.h"
+#include "in_utils.h"
+
+#ifdef VFS_FILES
+
+#include "vfsport.h"
+
+#ifdef INCLUDE_NVPARMS
+#include "nvparms.h"
+#endif   /* INCLUDE_NVPARMS */
+
+#ifdef IN_MENUS
+#include "menu.h"
+#endif   /* IN_MENUS */
+
+#ifdef IN_MENUS
+extern struct menu_op vfs_menu[];
+#endif   /* IN_MENUS */
+
+
+#ifdef INCLUDE_NVPARMS
+/* Please see nvparms.h and nvparms.c regarding the usage of
+ * the following datatypes and functions.
+ */
+
+struct vfs_nvparam vfs_nvparms;
+
+extern char vfs_root_path[MAX_NVSTRING];  /* root path of http vfs files */
+
+struct nvparm_info vfs_nvformats[] = 
+{
+   {"http root: %s\n", NVSTRING, MAX_NVSTRING, &vfs_nvparms.httppath, NULL, }, 
+};
+
+#define NUMVFS_FORMATS  \
+        (sizeof(vfs_nvformats)/sizeof(struct nvparm_info))
+
+#endif /* INCLUDE_NVPARMS */
+
+
+#ifdef INCLUDE_NVPARMS
+
+/* FUNCTION: vfs_nvset()
+ * 
+ * PARAM1: NV_FILE * fp
+ *
+ * RETURNS: Silent return of 0 for OK
+ */
+int vfs_nvset(NV_FILE * fp)
+{
+int i = 0;
+
+   nv_fprintf(fp, vfs_nvformats[i++].pattern, vfs_root_path);
+   return 0;
+}
+
+struct nvparm_format vfs_format = 
+{
+   NUMVFS_FORMATS,
+   &vfs_nvformats[0],
+   vfs_nvset,
+   NULL
+};
+
+#endif   /* INCLUDE_NVPARMS */
+
+
+/* FUNCTION: prep_vfs()
+ *
+ * PARAMS: NONE
+ *
+ * RETURNS: Error Code or 0 for OK
+ */
+int prep_vfs(void)
+{
+int e = 0;
+
+#ifdef IN_MENUS
+   /* install the VFS commands */
+   e = install_menu(&vfs_menu[0]);
+#endif   /* IN_MENUS */
+
+#ifdef INCLUDE_NVPARMS
+   e = install_nvformat(&vfs_format, nv_formats);
+   if(e)
+   {
+      dprintf("unable to install VFS NVPARMS, reconfigure nv_formats[]\n");
+      dtrap();
+   }
+#endif   /* INCLUDE_NVPARMS */
+   return e;
+}
+
+#endif /* VFS_FILES */
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.h b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.h
new file mode 100644
index 0000000..eabe0a0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsport.h
@@ -0,0 +1,45 @@
+/*
+ * FILENAME: vfsport.h
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: VFS
+ *
+ *
+ * PORTABLE: no
+ */
+
+/* Additional Copyrights: */
+
+/* vfsport.h 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ */
+
+#ifndef _VFSPORT_H_
+#define  _VFSPORT_H_    1
+
+#include "ipport.h"
+#include "libport.h"
+#include "vfsfiles.h"
+
+/* the web server still makes heaviest use of the vfs. Includes it's
+vfs setup here:*/
+#ifdef WEBPORT
+#include "webport.h"
+#endif
+
+/* Virtual File System related non-volatile parameters. Please see nvparms.h 
+ * and nvparms.c regarding the usage of the following structure.
+ */
+#ifdef INCLUDE_NVPARMS
+struct vfs_nvparam
+{
+   char     httppath[HTPATHMAX]; /* root path of http vfs files */
+};
+
+extern struct vfs_nvparam vfs_nvparms;
+#endif   /* INCLUDE_NVPARMS */
+
+#endif   /* _VFSPORT_H_ */
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfssync.c b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfssync.c
new file mode 100644
index 0000000..3275079
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfssync.c
@@ -0,0 +1,434 @@
+/*
+ * FILENAME: vfssync.c
+ *
+ * Copyright 1999- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: VFS
+ *
+ * ROUTINES: vfs_sync(), vfs_restore()
+ *
+ * PORTABLE: yes
+ */
+
+/* target system independent implementation of vfs_sync() and 
+ * vfs_restore() 
+ */
+#include "ipport.h"
+#include "vfsfiles.h"
+
+#if defined(HT_SYNCDEV) && defined(HT_RWVFS)
+
+#define  VFS_BACKING_STORE_TAG "VFS"
+
+/* these functions store and retrieve a VFS to and from a backing store */
+
+/* the format of the binary backing store file is shown below.
+ * all numeric fields are in local endian format.
+ *
+ * <tag> - the 4 byte null terminated string "VFS"
+ * <dir len> - 4 byte unsigned long contain the number of entries in
+ *             the linked list of vfs_file structures.
+ * the remaining entries are repeated <dir len> times
+ * <file name len> - 2 byte unsigned short containing the length of
+ *             the following file name.
+ * <file name> - <file name len> bytes that constitute the file name.
+ * <flags> - 2 byte unsigned short containing the vfs_file struct
+ *           flags field.
+ * <real size> - 4 byte unsigned long containing the vfs_file struct
+ *           real_size field (file size before compression).
+ * <comp size> - 4 byte unsigned long containing the vfs_file struct
+ *           comp_size field (size of actual file)
+ * <file data> - <comp size> bytes of binary data that constitute the
+ *           file's contents (what vfs_file.data will point to)
+ */
+
+
+/* FUNCTION: vfs_sync()
+ * 
+ * PARAM1: struct vfs_file *vfp
+ *
+ * RETURNS: 
+ */
+
+void vfs_sync(struct vfs_file * vfp)
+{
+   void *   fd;
+   unsigned long file_count = 0;    /* # of files we are going to sync */
+   unsigned long stale_count = 0;   /* # of files that we found stale */
+   unsigned short file_name_len; /* working file name length */
+   unsigned long bytes_written;
+   unsigned int bytes_to_write;
+   int   rc;
+
+   /* count the numbers of non-volatile and stale files */
+   /* I know we are using a function parameter is a working pointer 
+    * here, and that would normally be a sleezy thing to do, but this 
+    * implementation of vfs_sync() doesn't use its parameter as such 
+    * and doing this is an easy way to avoid the argument not 
+    * used compiler warnings 
+    */
+   for (vfp = vfsfiles; vfp; vfp = vfp->next)
+   {
+      /* skip files that aren't non-volatile */
+      if (!(vfp->flags & VF_NONVOLATILE))
+         continue;
+
+#ifdef HT_EXTDEV
+      /* if the file is handled by an external file system, its up to 
+       * it to deal with the file, so skip files 
+       * that are handled by an external fiel system
+       */
+      if (vfp->method)
+         continue;
+#endif   /* HT_EXTDEV */
+
+      /* we are going to sync all non-volatile files */
+      file_count++;
+      /* count the non-volatile stale ones too */
+      if (vfp->flags & VF_STALE)
+         stale_count++;
+   }
+
+   /* if it is not true that there are any non-volatile, stale files 
+    * or the directory is stale, then there is nothing to do so return 
+    */
+   if (!(stale_count || vfs_dir_stale))
+      return;
+
+   /* open and truncate an existing backing store, or create a new one if it
+      does not exist */
+   fd = vfs_sync_open(1,&rc);
+   if (!fd)
+   {
+      dprintf("vfs_sync_open() in vfs_sync() failed, error = %d\n",rc);
+      return;
+   }
+
+   /* write the tag used to identify file as a backing store file */
+   rc = vfs_sync_write(fd,VFS_BACKING_STORE_TAG,
+    strlen(VFS_BACKING_STORE_TAG) + 1);
+   if (rc)
+      return;
+
+   /* write the number of files to be synced */
+   if (vfs_sync_write(fd,&file_count,sizeof(file_count)))
+      return;
+
+   /* for each file in the VFS */
+   for (vfp = vfsfiles; vfp; vfp = vfp->next)
+   {
+      /* skip files that aren't non-volatile */
+      if (!(vfp->flags & VF_NONVOLATILE))
+         continue;
+#ifdef HT_EXTDEV
+      /* if the file is handled by an external file system, its up to 
+       * it to deal with the file, so skip files 
+       * that are handled by an external file system 
+       */
+      if (vfp->method)
+         continue;
+#endif   /* HT_EXTDEV */
+
+      /* write the length of the file name */
+      file_name_len = (unsigned short) strlen(vfp->name);
+      if (vfs_sync_write(fd,&file_name_len,sizeof(file_name_len)))
+         return;
+
+      /* write the file name (note no null termination) */
+      if (vfs_sync_write(fd,vfp->name,file_name_len))
+         return;
+
+      /* write the file flags */
+      if (vfs_sync_write(fd,&(vfp->flags),sizeof(vfp->flags)))
+         return;
+
+      /* write the file real_size */
+      if (vfs_sync_write(fd,&(vfp->real_size),sizeof(vfp->real_size)))
+         return;
+
+      /* write the file comp_size */
+      if (vfs_sync_write(fd,&(vfp->comp_size),sizeof(vfp->comp_size)))
+         return;
+
+      /* write the file contents */
+      for (bytes_written = 0;
+          bytes_written < vfp->comp_size; bytes_written += bytes_to_write)
+      {
+         bytes_to_write = (unsigned int) (vfp->comp_size - bytes_written);
+         if (bytes_to_write > VFS_MAX_FILE_IO_SIZE)
+            bytes_to_write = VFS_MAX_FILE_IO_SIZE;
+         if (vfs_sync_write(fd,vfp->data + bytes_written,bytes_to_write))
+            return;
+      }
+
+      /* the file is no longer stale */
+      vfp->flags &= ~VF_STALE;
+
+      /* easy sanity check */
+      file_count--;
+   }
+
+   /* close the backing store file */
+   rc = vfs_sync_close(fd);
+   if (rc)
+      dprintf("vfs_sync_close() failed in vfs_sync(), error = %d\n",rc);
+
+   /* reset the flag that indicates that the directory is stale */
+   vfs_dir_stale = FALSE;
+
+   /* this should never happen if it does, either the above logic is 
+    * screwed up or somebody went and messed with the VFS while 
+    * we had it locked 
+    */
+   if (file_count)
+      dprintf("file_count remains %ld in vfs_sync()\n",file_count);
+}
+
+
+
+/* FUNCTION: vfs_restore()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void vfs_restore()
+{
+   void *   fd;
+   struct vfs_file * vfp;
+   char  tag_string[sizeof(VFS_BACKING_STORE_TAG)];
+   unsigned long file_count;  /* # of files we are going to restore */
+   /* working file contents variables */
+   unsigned short file_name_len;    /* working file name length */
+   char  file_name[FILENAMEMAX   +  1];
+   unsigned short flags;
+   unsigned long real_size;
+   unsigned long comp_size;
+   unsigned char *buffer;
+   unsigned long bytes_read;
+   unsigned int bytes_to_read;
+   int   rc;
+
+   /* open existing backing store, fail if it does not exist */
+   fd = vfs_sync_open(0,&rc);
+
+   /* if the open fails, we will assume here its because it does not 
+    * exist, which is ok since that just means that we haven't had 
+    * anything to sync yet
+    */
+   if (!fd)
+   {
+      return;
+   }
+
+   /* read the tag at the beginning of the file */
+   if (vfs_sync_read(fd,tag_string,sizeof(tag_string)))
+      return;
+
+   /* if its not our tag, tell user and bail */
+   if (strcmp(tag_string,VFS_BACKING_STORE_TAG))
+   {
+      vfs_sync_close(fd);
+#ifdef NPDEBUG
+      dprintf("backing store tag is not present\n");
+#endif   /* NPDEBUG */
+      return;
+   }
+
+   /* read the number of file entries */
+   if (vfs_sync_read(fd,&file_count,sizeof(file_count)))
+      return;
+
+   /* for each file entry */
+   for ( ; file_count; file_count--)
+   {
+      /* read the length of the file name */
+      if (vfs_sync_read(fd,&file_name_len,sizeof(file_name_len)))
+         return;
+      if (file_name_len > FILENAMEMAX)
+      {
+#ifdef NPDEBUG
+         dprintf("file_name_len = %d\n",file_name_len);
+#endif   /* NPDEBUG */
+         break;
+      }
+
+      /* note that we read the file information into locals rather 
+       * than directly into a linked vfs_file structure because it 
+       * makes the clean up after a read error or memory allocation 
+       * failure a lot simpler
+       */
+      /* read the file name */
+      if (vfs_sync_read(fd,file_name,file_name_len))
+         return;
+
+      /* null terminate the file name */
+      file_name[file_name_len] = 0;
+
+      /* read the flags field */
+      if (vfs_sync_read(fd,&flags,sizeof(flags)))
+         return;
+
+      /* read the real (uncompressed) file size */
+      if (vfs_sync_read(fd,&real_size,sizeof(real_size)))
+         return;
+
+      /* read the actual (compressed) file size */
+      if (vfs_sync_read(fd,&comp_size,sizeof(comp_size)))
+         return;
+
+      /* if the file is not empty */
+      if (comp_size)
+      {
+         /* allocate a buffer to hold its contents */
+         buffer = vf_alloc_buffer(comp_size);
+         /* if the allocation failed */
+         if (!buffer)
+         {
+            dprintf("buffer allocation failed for %s\n",file_name);
+            break;
+         }
+
+         /* read the file contents into the buffer */
+         for (bytes_read = 0;
+             bytes_read < comp_size; bytes_read += bytes_to_read)
+         {
+            bytes_to_read = (unsigned int) (comp_size - bytes_read);
+            if (bytes_to_read > VFS_MAX_FILE_IO_SIZE)
+               bytes_to_read = VFS_MAX_FILE_IO_SIZE;
+            if (vfs_sync_read(fd,buffer + bytes_read,bytes_to_read))
+            {
+               vf_free_buffer(buffer,comp_size);
+               return;
+            }
+         }
+      }
+      else
+      {
+         /* file is empty, so associated file contents buffer is NULL */
+         buffer = NULL;
+      }
+
+      /* at this point we have read all the file contents into locals 
+       * and the allocated buffer, so the backing store file pointer 
+       * is now pointing to the data for the next VFS file, which 
+       * means its safe to "continue" below and still have to 
+       * loop work right 
+       */
+      /* see if its already in the VFS that came with the executable */
+      vfp = vfslookup_locked(file_name);
+
+      /* if its in the VFS that came with the executable */
+      if (vfp)
+      {
+         /* if its not write enabled */
+         if (!(vfp->flags & VF_WRITE))
+         {
+            /* free the allocated buffer and continue. note that this 
+             * could happen if in an older version of the executable 
+             * the file was writable and somebody had written to it, 
+             * but then in the current executable the file is not 
+             * writable. in this case I think the executable should 
+             * take precedence 
+             */
+            vf_free_buffer(buffer,comp_size);
+            continue;
+         }
+
+#ifdef HT_EXTDEV
+         /* the VFS that came with the executable is saying this file 
+          * belongs to another file system, yet its in our list of 
+          * files. believe the executable and toss the file contents 
+          */
+         if (vfp->method)
+         {
+            vf_free_buffer(buffer,comp_size);
+            continue;
+         }
+
+#endif   /* HT_EXTDEV */
+
+         /* the following is a sanity check, it should never happen 
+          * so long as this function is only called once at startup 
+          * since it would imply that a file or its contents got 
+          * added dynamically before this function was called 
+          */
+         if (vfp->flags & (VF_DYNAMICDATA | VF_DYNAMICINFO))
+         {
+#ifdef NPDEBUG
+            dprintf("existing vfp is dynamic in vfs_restore %s,%s,0x%x\n",
+             file_name,vfp->name,vfp->flags);
+#endif   /* NPDEBUG */
+            dtrap();
+         }
+      }
+      else  /* its not in the VFS that came with the executable */
+      {
+         /* enforce maximum number of files */
+         if (vfs_total_dyna_files >= VFS_MAX_DYNA_FILES)
+         {
+#ifdef NPDEBUG
+            dprintf("vfs_total_dyna_files exceeded for %s\n",file_name);
+#endif   /* NPDEBUG */
+            /* note that vf_free_buffer() checks for buffer == NULL,
+               so calling this without checking is not a bug */
+            vf_free_buffer(buffer,comp_size);
+            break;
+         }
+
+         /* allocate a vfs_file structure to hold the new file entry in */
+         vfp = VFS_VFS_FILE_ALLOC();
+
+         /* check for memory allocation failure */
+         if (!vfp)
+         {
+#ifdef NPDEBUG
+            dprintf("vfs_file allocation for %s failed\n",file_name);
+#endif   /* NPDEBUG */
+            vf_free_buffer(buffer,comp_size);
+            break;
+         }
+
+         /* add the vfs_file structure to the head of the list */
+
+         vfp->next = vfsfiles;
+         vfsfiles = vfp;
+
+         /* increment count of total files */
+         vfs_total_dyna_files++;
+
+         /* store the passed in name in the directory entry structure */
+         strcpy(vfp->name,file_name);
+      }
+
+      /* we now have a valid vfp and all its contents in locals, all
+         that is left is to load it up */
+      /* the file might have been stored with the stale bit on, but
+         it aint stale now, so turn it off */
+      vfp->flags = flags & ~VF_STALE;
+      vfp->data = buffer;
+      vfp->real_size = real_size;
+      vfp->comp_size = comp_size;
+      /* since we allocated a buffer just big enough to hold the contents,
+         buf_size gets comp_size */
+      vfp->buf_size = comp_size;
+   }
+
+   /* close the backing store file */
+   rc = vfs_sync_close(fd);
+   if (rc)
+      dprintf("vfs_sync_close() failed in vfs_restore(), error = %d\n",rc);
+
+   /* this should never happen if it does, either the above logic is 
+    * screwed up or somebody went and messed with the VFS while 
+    * we had it locked 
+    */
+   if (file_count)
+      dprintf("file_count remains %ld in vfs_restore()\n",file_count);
+}
+
+#endif   /* HT_SYNCDEV && HT_RWVFS */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsutil.c b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsutil.c
new file mode 100644
index 0000000..e6dafee
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/iniche/src/vfs/vfsutil.c
@@ -0,0 +1,1190 @@
+/*
+ * FILENAME: vfsutil.c
+ *
+ * Copyright 1997- 2000 By InterNiche Technologies Inc. All rights reserved
+ *
+ *
+ * MODULE: VFS
+ *
+ * ROUTINES: vfs_file_detail(), vfs_file_list(), 
+ * ROUTINES: vfs_change_flag(), vfs_set_flag(), vfs_clear_flag(), 
+ * ROUTINES: vfs_do_sync(), vfs_open_list(), vfs_dir(), 
+ * ROUTINES: vfs_unit_scan_index(), vfs_unit_scan_file_name(), 
+ * ROUTINES: vfs_unit_list(), vfs_unit_vfopen(), vfs_unit_vfclose(), 
+ * ROUTINES: vfs_unit_vunlink(), vfs_unit_vfread(), vfs_unit_vfwrite(), 
+ * ROUTINES: vfs_unit_vfseek(), vfs_unit_vftell(), vfs_unit_vgetc(), 
+ * ROUTINES: vfs_unit_vferror(), vfs_unit_vclearerr(), 
+ * ROUTINES: vfs_tog_log_file_name(), vfs_led_test(), vfs_init(), 
+ *
+ * PORTABLE: yes
+ */
+
+/* Additional Copyrights: */
+
+/* vfsutil.c 
+ * Portions Copyright 1996 by NetPort Software. All rights reserved. 
+ * InterNiche virtual file system. This implements the vfopen(), 
+ * vfread(), etc, calls the Embedded WEB servers and similar devices 
+ * to do file IO. These calls lookup names, descriptors, etc, to see 
+ * if the file is a "virtual" file in RAM/ROM/FLASH, or if it should 
+ * fall through to the local disk system (if any) 
+ * 12/26/98 - Separated from WebPort sources. -JB- 
+ */
+
+#include "ipport.h"
+
+#ifdef VFS_FILES
+
+#include "vfsport.h" /* per-port include */
+#include "vfsfiles.h"   /* overlay vfs stuff on system file IO */
+
+#include "menu.h"
+
+#ifdef IN_MENUS
+
+/* VFS system commands */
+
+struct vfs_flag_map_struct
+{
+   char  flag_name;  /* how flag bit is identified in display */
+   char  editable;   /* can flag bit be modified by user */
+   unsigned short bit_mask;   /* mask representing position of bit */
+};
+
+/* the VFS commands use the following array to map vfs_file.flags field
+   bits to displayable characters */
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+struct vfs_flag_map_struct vfs_flag_map[] =
+{
+   { 'H',  1, VF_HTMLCOMPRESSED } ,
+   { 'B',  1, VF_AUTHBASIC } ,
+   { '5',  1, VF_AUTHMD5 } ,
+   { 'M',  1, VF_MAPFILE } ,
+   { 'V',  0, VF_CVAR } ,
+   { 'W',  1, VF_WRITE } ,
+   { 'I',  0, VF_DYNAMICINFO } ,
+   { 'D',  0, VF_DYNAMICDATA } ,
+   { 'N',  1, VF_NONVOLATILE } ,
+   { 'S',  0, VF_STALE } ,
+#ifdef WEBPORT
+   { 's',  0, 0 } , /* these last three are special cases */
+   { 'c',  0, 0 } ,
+#endif   /* WEBPORT */
+#ifdef HT_EXTDEV
+   { 'm',  0  ,0 } ,
+#endif   /* HT_EXTDEV */
+   { 0, 0, 0 }   /* array terminator */
+};
+
+#define  VFS_FLAG_MAP_LEN  (sizeof(vfs_flag_map)/sizeof(vfs_flag_map[0]))
+
+/* maximum length of a buffer where a file's details (e.g., name, start
+ * address, length, etc.) are created.  (The string generated is used 
+ * when a file listing is generated.
+ */
+#define FILEDETAIL_MAXLEN 80
+
+
+/* FUNCTION: vfs_file_detail()
+ * 
+ * this function creates a detailed file directory listing for the
+ * file addressed by the vfp parameter in the buffer addressed by buf
+ *
+ * PARAM1: struct vfs_file *vfp
+ * PARAM2: char *buf
+ *
+ * RETURNS: 
+ */
+
+void vfs_file_detail(struct vfs_file * vfp, char * buf)
+{
+   int   i;
+   char  name_string[FILENAMEMAX +  1];
+   char  flag_string[VFS_FLAG_MAP_LEN  +  1];
+
+   /* make a string containing the name of the file padded to
+      the max file name length */
+   strcpy(name_string,vfp->name);
+   i = strlen(name_string);
+   while (i < FILENAMEMAX)
+      name_string[i++] = ' ';
+   name_string[FILENAMEMAX] = 0;
+
+   /* make a string listing the bits of vfp->flags */
+   /* note that loop below terminates when bit_mask is 0 because the 
+    * last 3 chars of the flags field are not derived from bits 
+    * in the flags field
+    */
+   for (i = 0; vfs_flag_map[i].bit_mask; ++i)
+   {
+      flag_string[i] =
+      (char) ((vfp->flags & vfs_flag_map[i].bit_mask)
+       ? vfs_flag_map[i].flag_name : '-');
+   }
+
+#ifdef WEBPORT
+
+   /* a non-null ssi_func field is represented by a 's' */
+   flag_string[i] =
+(char) (vfp->ssi_func ? vfs_flag_map[i].flag_name : '-');
+   i++;
+
+   /* a non-null cgi_func field is represented by a 'c' */
+   flag_string[i] =
+(char) (vfp->cgi_func ? vfs_flag_map[i].flag_name : '-');
+   i++;
+
+#endif   /* WEBPORT */
+
+#ifdef HT_EXTDEV
+
+   /* a non-null method field is represented by a 'm' */
+   flag_string[i] =
+(char) (vfp->method ? vfs_flag_map[i].flag_name : '-');
+   i++;
+
+#endif   /* HT_EXTDEV */
+
+   /* terminate flags string */
+   flag_string[i] = 0;
+
+   /* format it all into the caller supplied buffer */
+   snprintf(buf, FILEDETAIL_MAXLEN, "%s %s %p %8lx %8lx %8lx",
+            name_string, flag_string, vfp->data,
+            vfp->real_size, vfp->comp_size, vfp->buf_size);
+}
+
+
+
+/* FUNCTION: vfs_file_list()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_file_list(void * pio)
+{
+   struct vfs_file * vfp;
+   int   file_count  =  0;
+   char  buffer[FILEDETAIL_MAXLEN];
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* for each file in the file list */
+   for (vfp = vfsfiles; vfp; vfp = vfp->next)
+   {
+      /* create a line of file listing */
+      vfs_file_detail(vfp,buffer);
+
+      /* and write it out */
+      ns_printf(pio,"%s\n",buffer);
+
+      file_count++;
+      if ( con_page(pio,file_count) )
+         break ;
+   }
+
+   ns_printf(pio,"total files = %d\n",file_count);
+
+#ifdef HT_RWVFS
+
+   ns_printf(pio,"dynamically allocated files = %ld, buffer space = 0x%lx\n",
+    vfs_total_dyna_files,vfs_total_rw_space);
+
+#endif   /* HT_RWVFS */
+
+   vfs_unlock();
+
+   return 0;
+}
+
+#ifdef HT_RWVFS
+
+
+
+/* FUNCTION: vfs_change_flag()
+ * 
+ * PARAM1: void *pio
+ * PARAM2: int set
+ *
+ * RETURNS: 
+ */
+
+int vfs_change_flag(void * pio, int set)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   char *   cp;
+   struct vfs_file * vfp;
+   VFILE *vfd;
+   struct vfs_flag_map_struct *  pmap;
+   int   bit_changed =  FALSE;
+   char  flag_name;
+   char  file_name[FILENAMEMAX   +  1];
+
+   /* scan out first and second args to command */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+      arg2 = nextarg(arg1);
+
+   /* if two args are not present, tell the user how to do the command */
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio,"usage:%s <file name> <bit>\n",
+       set ? "vfssetflag" : "vfsclearflag");
+      return 1;
+   }
+
+   /* get pointer to space at end of first arg */
+   cp = strchr(arg1,' ');
+   /* it had better be non-NULL */
+   if (!cp)
+   {
+      dtrap();
+      return 2;
+   }
+
+   /* copy and null terminate the file name */
+   MEMCPY(file_name,arg1,cp - arg1);
+   file_name[cp - arg1] = 0;
+
+   /* get the name of the flag from the second arg */
+   flag_name = *arg2;
+
+   /* search the flag map array for the specified flag name */
+   for (pmap = vfs_flag_map;
+       pmap < (vfs_flag_map + VFS_FLAG_MAP_LEN); ++pmap)
+   {
+      if (pmap->flag_name == flag_name)
+         break;
+   }
+
+   /* if the search failed, tell the user */
+   if (pmap >= vfs_flag_map + VFS_FLAG_MAP_LEN)
+   {
+      ns_printf(pio,"%c is not a valid bit identifier\n",flag_name);
+      return 3;
+   }
+
+   /* if the flag is not editable, tell the user */
+   if (!(pmap->editable))
+   {
+      ns_printf(pio,"Flag %c may not be modified\n",flag_name);
+      return 4;
+   }
+
+   /* lock the VFS */
+   vfs_lock();
+
+   /* see if the file exists */
+   vfp = vfslookup_locked(file_name);
+   if (!vfp)
+   {
+      vfs_unlock();
+      ns_printf(pio,"file name %s is not in the VFS\n",file_name);
+      return 5;
+   }
+
+   /* open the file for read access */
+   vfd = vfopen_locked(file_name,"r");
+
+   /* since we already verified that the file exists above and we've 
+    * locked the file system to prevent others from unlinking it, the 
+    * above open should work. 
+    * If it doesn't work, something is very wrong
+    */
+   if (!vfd)
+   {
+      vfs_unlock();
+      dtrap();
+      return 6;
+   }
+
+   /* if we are setting the bit, set it */
+   if (set)
+   {
+      /* if its not set now */
+      if (!(vfp->flags & pmap->bit_mask))
+      {
+         /* set it and flag that we changed it */
+         vfp->flags |= pmap->bit_mask;
+         bit_changed = TRUE;
+      }
+   }
+   else  /* else reset it */
+   {
+      /* if its set now */
+      if (vfp->flags & pmap->bit_mask)
+      {
+         /* reset it and flag that we changed it */
+         vfp->flags &= ~(pmap->bit_mask);
+         bit_changed = TRUE;
+      }
+   }
+
+#ifdef HTML_COMPRESSION
+
+   /* if its the compression bit we are fidding and we actually 
+    * changed something, then we want to set the real_size field 
+    * accordingly 
+    */
+   if ((pmap->bit_mask == VF_HTMLCOMPRESSED) && bit_changed)
+   {
+      /* if the compression bit is being turned off, then the "size 
+       * before compression" is the same as its actual 
+       * compressed size
+       */
+      if (!set)
+         vfp->real_size = vfp->comp_size;
+      else
+      /* we are turning the compression bit on, so we need to run the 
+       * decompression algorithm on the file to determine 
+       * how big it was before it was compressed 
+       */
+      {
+         unsigned long count;
+
+         count = 0;
+         while (vgetc_locked(vfd) != EOF)
+            ++count;
+         vfp->real_size = count;
+      }
+   }
+
+#endif   /* HTML_COMPRESSION */
+
+   /* if we actually changed something,
+      set the stale bit so when we close the file, it will get synced */
+   if (bit_changed)
+      vfp->flags |= VF_STALE;
+
+   vfclose_locked(vfd);
+
+   vfs_unlock();
+
+   return 0;   /* success */
+}
+
+
+
+/* FUNCTION: vfs_set_flag()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_set_flag(void * pio)
+{
+   return vfs_change_flag(pio,TRUE);
+}
+
+
+
+/* FUNCTION: vfs_clear_flag()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_clear_flag(void * pio)
+{
+   return vfs_change_flag(pio,FALSE);
+}
+
+#ifdef HT_SYNCDEV    /* Do we support sync to flash device? */
+
+
+
+/* FUNCTION: vfs_do_sync()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_do_sync(void * pio)
+{
+   /* this implementation will not be suitable for target systems in 
+    * which vfs_sync() determines what it should do based on the 
+    * parameter that is passed to it. this implementation only makes 
+    * sense if vfs_sync() does the same thing, that is syncs the 
+    * entire file system to backing store, irrespective of the 
+    * parameter that is passed to it. if the target system's 
+    * implementation of vfs_sync() DOES function differently based on 
+    * the parameter passed to it, this command should be modified to 
+    * allow the appropriate parameters to be passed to it
+    */
+   ns_printf(pio,"VFS sync initiated\n");
+   vfs_lock();
+   vfs_sync(NULL);
+   vfs_unlock();
+   ns_printf(pio,"VFS sync completed\n");
+
+   return 0;
+}
+#endif   /* HT_SYNCDEV */
+
+#endif   /* HT_RWVFS */
+
+
+
+/* FUNCTION: vfs_open_list()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_open_list(void * pio)
+{
+   VFILE * vfd;
+   unsigned long count = 0;
+   unsigned long orphans = 0;
+
+   vfs_lock();
+
+   for (vfd = vfiles; vfd; vfd = vfd->next)
+   {
+      /* if the file that the handle is pointing at still exists */
+      if (vfd->file)
+      {
+         /* display its name */
+         ns_printf(pio,"%s\n",vfd->file->name);
+      }
+      else  /* else the file was deleted since the open */
+      {
+         /* so just increment the count of orphans */
+         orphans++;
+      }
+      count++;
+   }
+
+   vfs_unlock();
+   ns_printf(pio,"total files open = %ld\n",count);
+   if (orphans)
+      ns_printf(pio,"total orphans = %ld\n",orphans);
+   return 0;
+}
+
+
+
+
+
+/* FUNCTION: vfs_dir()
+ * 
+ * vfs_dir() - a vfs dir command for the menus
+ *
+ * PARAM1: void * pio
+ *
+ * RETURNS: 
+ */
+
+int
+vfs_dir(void * pio)
+{
+   return vfs_file_list(pio);
+}
+
+#ifdef VFS_UNIT_TEST
+
+/* code in here is used to unit test the VFS */
+/* it was thrown together quick, so pardon the spare comments */
+
+#define  VFS_NUM_UNIT_TEST_FDS   10
+
+VFILE *vfs_unit_test_fds[VFS_NUM_UNIT_TEST_FDS];
+
+unsigned int atoh(char *buf);
+unsigned long atohl(char *buf);
+
+
+
+/* FUNCTION: vfs_unit_scan_index()
+ * 
+ * PARAM1: void *pio
+ * PARAM2: char *arg
+ * PARAM3: unsigned int *pindex
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_scan_index(void * pio, char * arg, unsigned int * pindex)
+{
+   *pindex = atoh(arg);
+   if (*pindex >= VFS_NUM_UNIT_TEST_FDS)
+   {
+      ns_printf(pio,"bad index 0x%x\n",*pindex);
+      return 1;
+   }
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_scan_file_name()
+ * 
+ * PARAM1: void *pio
+ * PARAM2: char *arg
+ * PARAM3: char *file_name
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_scan_file_name(void * pio, char * arg, char * file_name)
+{
+   char *   cp;
+
+   /* get pointer to space at end of first arg */
+   cp = strchr(arg,' ');
+
+   /* if no space, make cp point to null and end of string */
+   if (!cp)
+      cp = arg + strlen(arg);
+
+   /* check for too long */
+   if ((cp - arg) > FILENAMEMAX)
+   {
+      ns_printf(pio,"bad file name\n");
+      return 1;
+   }
+
+   /* copy and null terminate the file name */
+   MEMCPY(file_name,arg,cp - arg);
+   file_name[cp - arg] = 0;
+
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_list()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_list(void * pio)
+{
+   int   i;
+
+   for (i = 0; i < VFS_NUM_UNIT_TEST_FDS; i++)
+      ns_printf(pio,"%d %p\n",i,vfs_unit_test_fds[i]);
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vfopen()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vfopen(void * pio)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   char *   arg3  =  NULL;
+   unsigned int index;
+   VFILE *vfd;
+   char  file_name[FILENAMEMAX   +  1];
+   char  mode[FILENAMEMAX  +  1];
+
+   /* scan out the index, file name and mode to pass to vfopen() */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+   {
+      arg2 = nextarg(arg1);
+      if (arg2)
+         arg3 = nextarg(arg2);
+   }
+
+   /* if three args are not present, tell the user how to do the command */
+   if (!arg3 || !*arg3)
+   {
+      ns_printf(pio,"usage:vfsvfopen <index> <file name> <mode>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   /* get and verify file_name */
+   if (vfs_unit_scan_file_name(pio,arg2,file_name))
+      return 1;
+
+   /* get and verify mode */
+   if (vfs_unit_scan_file_name(pio,arg3,mode))
+      return 1;
+
+   ns_printf(pio,"calling vfopen(%s,%s) index 0x%x\n",file_name,mode,index);
+
+   vfd = vfopen(file_name,mode);
+
+   ns_printf(pio,"vfopen() returned %p\n",vfd);
+   ns_printf(pio,"get_vfopen_error() returned %d\n",get_vfopen_error());
+
+   vfs_unit_test_fds[index] = vfd;
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vfclose()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vfclose(void * pio)
+{
+   char *   arg1;
+   unsigned int index;
+
+   /* scan out the index */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsvfclose <index>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   ns_printf(pio,"calling vfclose(%p) index 0x%x\n",
+    vfs_unit_test_fds[index],index);
+
+   vfclose(vfs_unit_test_fds[index]);
+
+   vfs_unit_test_fds[index] = 0;
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vunlink()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vunlink(void * pio)
+{
+   char *   arg1;
+   int   rc;
+   char  file_name[FILENAMEMAX   +  1];
+
+   /* scan out the file name */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsvunlink <file name>\n");
+      return 1;
+   }
+
+   /* get and verify file_name */
+   if (vfs_unit_scan_file_name(pio,arg1,file_name))
+      return 1;
+
+   ns_printf(pio,"calling vunlink(%s)\n",file_name);
+
+   rc = vunlink(file_name);
+
+   ns_printf(pio,"vunlink() returned %d\n",rc);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vfread()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vfread(void * pio)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   unsigned int index;
+   unsigned int count;
+   int   rc;
+   char  in_buf[256];
+
+   /* scan out the index and count */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+   {
+      arg2 = nextarg(arg1);
+   }
+
+   /* if two args are not present, tell the user how to do the command */
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio,"usage:vfsvfread <index> <count>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   /* get byte count to read */
+   count = atoh(arg2);
+   if (count > sizeof(in_buf))
+   {
+      ns_printf(pio,"bad count 0x%x\n",count);
+      return 1;
+   }
+
+   ns_printf(pio,"calling vfread() of 0x%x bytes fd %p\n",
+    count,vfs_unit_test_fds[index]);
+
+   rc = vfread(in_buf,1,count,vfs_unit_test_fds[index]);
+
+   ns_printf(pio,"vfread() returned %d\n",rc);
+   hexdump(pio,in_buf,count);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vfwrite()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vfwrite(void * pio)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   unsigned int index;
+   int   count;
+   unsigned int line_len;
+   unsigned long byte_count = 0;
+   int   i;
+   int   len;
+   int   rc;
+   char  out_buf[30];
+
+   /* scan out the index and count */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+   {
+      arg2 = nextarg(arg1);
+   }
+
+   /* if two args are not present, tell the user how to do the command */
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio,"usage:vfsvfwrite <index> <count>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   /* get line count to write */
+   count = (int) atoh(arg2);
+
+   ns_printf(pio,"calling vfwrite() of 0x%x lines fd %p\n",
+    count,vfs_unit_test_fds[index]);
+
+   for (i = 0; i < count; i++)
+   {
+      sprintf(out_buf,"line number = %x ",i);
+      len = strlen(out_buf);
+      /* pad out buffer to constant length */
+      for (; len < 24; len++)
+      {
+         out_buf[len] = (char) ('A' + ((i + len) % 26));
+      }
+      out_buf[len] = 0;
+      line_len = strlen(out_buf);
+      rc = vfwrite(out_buf,1,line_len,vfs_unit_test_fds[index]);
+      if (rc != (int) line_len)
+      {
+         ns_printf(pio,"vfwrite() returned %d\n",rc);
+         break;
+      }
+      byte_count += line_len;
+   }
+
+   ns_printf(pio,"%ld (0x%lx) bytes written\n",byte_count,byte_count);
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vfseek()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vfseek(void * pio)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   char *   arg3  =  NULL;
+   unsigned int index;
+   unsigned long offset;
+   unsigned int mode;
+   int   rc;
+
+   /* scan out the index, offset and mode */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+   {
+      arg2 = nextarg(arg1);
+      if (arg2)
+         arg3 = nextarg(arg2);
+   }
+
+   /* if three args are not present, tell the user how to do the command */
+   if (!arg3 || !*arg3)
+   {
+      ns_printf(pio,"usage:vfsfseek <index> <offset> <mode>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   /* get offset and mode */
+   offset = atohl(arg2);
+   mode = atoh(arg3);
+
+   ns_printf(pio,"calling vfseek(%p,0x%lx,0x%x)\n",
+    vfs_unit_test_fds[index],offset,mode);
+
+   rc = vfseek(vfs_unit_test_fds[index],offset,mode);
+
+   ns_printf(pio,"vfseek() returned %d\n",rc);
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vftell()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vftell(void * pio)
+{
+   char *   arg1;
+   unsigned int index;
+   long  rc;
+
+   /* scan out the index, offset and mode */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsftell <index>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   ns_printf(pio,"calling vftell(%p)\n",vfs_unit_test_fds[index]);
+
+   rc = vftell(vfs_unit_test_fds[index]);
+
+   ns_printf(pio,"vftell() returned %ld\n",rc);
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vgetc()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vgetc(void * pio)
+{
+   char *   arg1;
+   char *   arg2  =  NULL;
+   unsigned int index;
+   unsigned int count;
+   unsigned int i;
+   int   rc;
+   char  in_buf[256];
+
+   /* scan out the index and count */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+   if (arg1)
+   {
+      arg2 = nextarg(arg1);
+   }
+
+   /* if two args are not present, tell the user how to do the command */
+   if (!arg2 || !*arg2)
+   {
+      ns_printf(pio,"usage:vfsvgetc <index> <count>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   /* get byte count to read */
+   count = atoh(arg2);
+   if (count > sizeof(in_buf))
+   {
+      ns_printf(pio,"bad count 0x%x\n",count);
+      return 1;
+   }
+
+   ns_printf(pio,"calling vgetc() of 0x%x times on fd %p\n",
+    count,vfs_unit_test_fds[index]);
+
+   for (i = 0; i < count; ++i)
+   {
+      rc = vgetc(vfs_unit_test_fds[index]);
+      if (rc == EOF)
+         break;
+      in_buf[i] = (char) rc;
+   }
+
+   ns_printf(pio,"%d (0x%x) bytes read\n",i,i);
+   hexdump(pio,in_buf,i);
+
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vferror()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vferror(void * pio)
+{
+   char *   arg1;
+   unsigned int index;
+   int   rc;
+
+   /* scan out the index, offset and mode */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsferror <index>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   ns_printf(pio,"calling vferror(%p)\n",vfs_unit_test_fds[index]);
+
+   rc = vferror(vfs_unit_test_fds[index]);
+
+   ns_printf(pio,"vferror() returned %d\n",rc);
+   return 0;
+}
+
+
+
+/* FUNCTION: vfs_unit_vclearerr()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_unit_vclearerr(void * pio)
+{
+   char *   arg1;
+   unsigned int index;
+
+   /* scan out the index, offset and mode */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsclearerr <index>\n");
+      return 1;
+   }
+
+   /* get and verify index */
+   if (vfs_unit_scan_index(pio,arg1,&index))
+      return 1;
+
+   ns_printf(pio,"calling vclearerr(%p)\n",vfs_unit_test_fds[index]);
+
+   vclearerr(vfs_unit_test_fds[index]);
+   return 0;
+}
+
+extern   int   vfs_log_file_name;
+
+
+
+/* FUNCTION: vfs_tog_log_file_name()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_tog_log_file_name(void * pio)
+{
+   vfs_log_file_name = !vfs_log_file_name;
+   ns_printf(pio,"file name logging is %s\n",
+    vfs_log_file_name ? "on" : "off");
+   return 0;
+}
+
+#ifdef AMD_NET186
+
+/* defined in net186 flash.c */
+void PostLEDs(unsigned char value);
+
+
+
+/* FUNCTION: vfs_led_test()
+ * 
+ * PARAM1: void *pio
+ *
+ * RETURNS: 
+ */
+
+int vfs_led_test(void * pio)
+{
+   char *   arg1;
+   unsigned int value;
+
+   /* scan out the value */
+   arg1 = nextarg(((GEN_IO) pio)->inbuf);
+
+   /* if arg not present, tell the user how to do the command */
+   if (!arg1 || !*arg1)
+   {
+      ns_printf(pio,"usage:vfsled <LED value>\n");
+      return 1;
+   }
+
+   /* get line count to write */
+   value = atoh(arg1);
+
+   ns_printf(pio,"calling PostLEDs(0x%x)\n",value);
+
+   PostLEDs((unsigned char) (value & 0xff));
+   return 0;
+}
+
+#endif   /* AMD_NET186 */
+
+#endif   /* VFS_UNIT_TEST */
+
+/*
+ * Altera Niche Stack Nios port modification:
+ * Add braces to remove build warning
+ */
+struct menu_op vfs_menu[]  =
+{
+   { "vfs", stooges, "VFS commands" } ,
+   { "vfsfilelist", vfs_file_list, "display vfs_file structure info" } ,
+#ifdef HT_RWVFS
+   { "vfssetflag", vfs_set_flag, "set bit in vfs_file flags field" } ,
+   { "vfsclearflag", vfs_clear_flag, "clear bit in vfs_file flags field" } ,
+#ifdef HT_SYNCDEV
+   { "vfssync", vfs_do_sync, "sync the VFS to backing store" } ,
+#endif
+#endif   /* HT_RWVFS */
+   { "vfsopenlist", vfs_open_list, "list currently open VFS files" } ,
+#ifdef VFS_UNIT_TEST
+   { "vfsunitlist", vfs_unit_list, "list unit test VFILE array" } ,
+   { "vfsvfopen", vfs_unit_vfopen, "vfsvfopen <index> <file name> <mode>" } ,
+   { "vfsvfclose", vfs_unit_vfclose, "vfsvfclose <index>" } ,
+   { "vfsvunlink", vfs_unit_vunlink, "vfsvunlink <file name>" } ,
+   { "vfsvfread", vfs_unit_vfread, "vfsvfread <index> <count>" } ,
+   { "vfsvfwrite", vfs_unit_vfwrite, "vfsvfwrite <index> <count>" } ,
+   { "vfsvfseek", vfs_unit_vfseek, "vfsvfseek <index> <offset> <mode>" } ,
+   { "vfsvftell", vfs_unit_vftell, "vfsvftell <index>" } ,
+   { "vfsvgetc", vfs_unit_vgetc, "vfsvgetc <index> <count>" } ,
+   { "vfsvferror", vfs_unit_vferror, "vfsferror <index>" } ,
+   { "vfsvclearerr", vfs_unit_vclearerr, "vfsclearerr <index>" } ,
+   { "vfslogname", vfs_tog_log_file_name, "toggle display of passed file names" } ,
+#ifdef AMD_NET186
+   { "vfsled", vfs_led_test, "vfsled <led value>" } ,
+#endif   /* AMD_NET186 */
+#endif   /* VFS_UNIT_TEST */
+   { NULL } 
+};
+#endif   /* IN_MENUS */
+
+
+
+/* FUNCTION: vfs_init()
+ * 
+ * PARAM1: 
+ *
+ * RETURNS: 
+ */
+
+void vfs_init()
+{
+#ifdef HT_SYNCDEV    /* Do we support sync to flash device? */
+#ifdef HT_RWVFS
+   vfs_lock();
+   /* restore the RAM resident VFS from whatever backing store has
+      been provided */
+   vfs_restore();
+   vfs_unlock();
+#endif   /* HT_RWVFS */
+#endif   /* HT_SYNCDEV */
+
+#ifdef INCLUDE_NVPARMS
+   strncpy(vfs_root_path, vfs_nvparms.httppath, HTPATHMAX);
+#endif   /* INCLUDE_NVPARMS */
+
+}
+
+#endif   /* VFS_FILES */
+
+
diff --git a/FPGA_nios/hit_pat_bsp/linker.h b/FPGA_nios/hit_pat_bsp/linker.h
new file mode 100644
index 0000000..959ba01
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/linker.h
@@ -0,0 +1,103 @@
+/*
+ * linker.h - Linker script mapping information
+ *
+ * Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys'
+ * SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+ *
+ * Generated: Fri Oct 11 10:12:20 CEST 2024
+ */
+
+/*
+ * DO NOT MODIFY THIS FILE
+ *
+ * Changing this file will have subtle consequences
+ * which will almost certainly lead to a nonfunctioning
+ * system. If you do modify this file, be aware that your
+ * changes will be overwritten and lost when this file
+ * is generated again.
+ *
+ * DO NOT MODIFY THIS FILE
+ */
+
+/*
+ * License Agreement
+ *
+ * Copyright (c) 2008
+ * Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#ifndef __LINKER_H_
+#define __LINKER_H_
+
+
+/*
+ * BSP controls alt_load() behavior in crt0.
+ *
+ */
+
+#define ALT_LOAD_EXPLICITLY_CONTROLLED
+
+
+/*
+ * Base address and span (size in bytes) of each linker region
+ *
+ */
+
+#define CALIBRATION_RAM_REGION_BASE 0x18403400
+#define CALIBRATION_RAM_REGION_SPAN 640
+#define DDR3_RAM_BEFORE_EXCEPTION_REGION_BASE 0x8000000
+#define DDR3_RAM_BEFORE_EXCEPTION_REGION_SPAN 288
+#define DDR3_RAM_REGION_BASE 0x8000120
+#define DDR3_RAM_REGION_SPAN 134217440
+#define DESCRIPTOR_MEMORY_REGION_BASE 0x18400000
+#define DESCRIPTOR_MEMORY_REGION_SPAN 8192
+#define EXT_FLASH_AVL_MEM_REGION_BASE 0x14000020
+#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108832
+#define ONCHIP_FLASH_DATA_REGION_BASE 0x18200000
+#define ONCHIP_FLASH_DATA_REGION_SPAN 1441792
+#define RESET_REGION_BASE 0x14000000
+#define RESET_REGION_SPAN 32
+
+
+/*
+ * Devices associated with code sections
+ *
+ */
+
+#define ALT_EXCEPTIONS_DEVICE DDR3_RAM
+#define ALT_RESET_DEVICE EXT_FLASH_AVL_MEM
+#define ALT_RODATA_DEVICE DDR3_RAM
+#define ALT_RWDATA_DEVICE DDR3_RAM
+#define ALT_TEXT_DEVICE DDR3_RAM
+
+
+/*
+ * Initialization code at the reset address is allowed (e.g. no external bootloader).
+ *
+ */
+
+#define ALT_ALLOW_CODE_AT_RESET
+
+#endif /* __LINKER_H_ */
diff --git a/FPGA_nios/hit_pat_bsp/linker.x b/FPGA_nios/hit_pat_bsp/linker.x
new file mode 100644
index 0000000..96fefb2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/linker.x
@@ -0,0 +1,402 @@
+/*
+ * linker.x - Linker script
+ *
+ * Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys'
+ * SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+ *
+ * Generated: Fri Oct 11 10:12:20 CEST 2024
+ */
+
+/*
+ * DO NOT MODIFY THIS FILE
+ *
+ * Changing this file will have subtle consequences
+ * which will almost certainly lead to a nonfunctioning
+ * system. If you do modify this file, be aware that your
+ * changes will be overwritten and lost when this file
+ * is generated again.
+ *
+ * DO NOT MODIFY THIS FILE
+ */
+
+/*
+ * License Agreement
+ *
+ * Copyright (c) 2008
+ * Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+MEMORY
+{
+    ddr3_ram_BEFORE_EXCEPTION : ORIGIN = 0x8000000, LENGTH = 288
+    ddr3_ram : ORIGIN = 0x8000120, LENGTH = 134217440
+    reset : ORIGIN = 0x14000000, LENGTH = 32
+    ext_flash_avl_mem : ORIGIN = 0x14000020, LENGTH = 67108832
+    onchip_flash_data : ORIGIN = 0x18200000, LENGTH = 1441792
+    descriptor_memory : ORIGIN = 0x18400000, LENGTH = 8192
+    calibration_ram : ORIGIN = 0x18403400, LENGTH = 640
+}
+
+/* Define symbols for each memory base-address */
+__alt_mem_ddr3_ram = 0x8000000;
+__alt_mem_ext_flash_avl_mem = 0x14000000;
+__alt_mem_onchip_flash_data = 0x18200000;
+__alt_mem_descriptor_memory = 0x18400000;
+__alt_mem_calibration_ram = 0x18403400;
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+ENTRY( _start )
+
+/*
+ * The alt_load() facility is disabled. This typically happens when an
+ * external bootloader is provided or the application runs in place.
+ * The LMA (aka physical address) of each section defaults to its VMA.
+ */
+
+SECTIONS
+{
+
+    /*
+     * Output sections associated with reset and exceptions (they have to be first)
+     */
+
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > reset
+
+    .exceptions :
+    {
+        PROVIDE (__ram_exceptions_start = ABSOLUTE(.));
+        . = ALIGN(0x20);
+        KEEP (*(.irq));
+        KEEP (*(.exceptions.entry.label));
+        KEEP (*(.exceptions.entry.user));
+        KEEP (*(.exceptions.entry.ecc_fatal));
+        KEEP (*(.exceptions.entry));
+        KEEP (*(.exceptions.irqtest.user));
+        KEEP (*(.exceptions.irqtest));
+        KEEP (*(.exceptions.irqhandler.user));
+        KEEP (*(.exceptions.irqhandler));
+        KEEP (*(.exceptions.irqreturn.user));
+        KEEP (*(.exceptions.irqreturn));
+        KEEP (*(.exceptions.notirq.label));
+        KEEP (*(.exceptions.notirq.user));
+        KEEP (*(.exceptions.notirq));
+        KEEP (*(.exceptions.soft.user));
+        KEEP (*(.exceptions.soft));
+        KEEP (*(.exceptions.unknown.user));
+        KEEP (*(.exceptions.unknown));
+        KEEP (*(.exceptions.exit.label));
+        KEEP (*(.exceptions.exit.user));
+        KEEP (*(.exceptions.exit));
+        KEEP (*(.exceptions));
+        PROVIDE (__ram_exceptions_end = ABSOLUTE(.));
+    } > ddr3_ram
+
+    PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions));
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+        *(.rel.dyn)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(4);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table .gcc_except_table.*)
+        *(.dynamic)
+        PROVIDE (__CTOR_LIST__ = ABSOLUTE(.));
+        KEEP (*(.ctors))
+        KEEP (*(SORT(.ctors.*)))
+        PROVIDE (__CTOR_END__ = ABSOLUTE(.));
+        PROVIDE (__DTOR_LIST__ = ABSOLUTE(.));
+        KEEP (*(.dtors))
+        KEEP (*(SORT(.dtors.*)))
+        PROVIDE (__DTOR_END__ = ABSOLUTE(.));
+        KEEP (*(.jcr))
+        . = ALIGN(4);
+    } > ddr3_ram = 0x3a880100 /* NOP instruction (always in big-endian byte ordering) */
+
+    .rodata :
+    {
+        PROVIDE (__ram_rodata_start = ABSOLUTE(.));
+        . = ALIGN(4);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+        . = ALIGN(4);
+        PROVIDE (__ram_rodata_end = ABSOLUTE(.));
+    } > ddr3_ram
+
+    PROVIDE (__flash_rodata_start = LOADADDR(.rodata));
+
+    .rwdata :
+    {
+        PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
+        . = ALIGN(4);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x8000);
+        PROVIDE(gp = _gp);
+
+        *(.rwdata .rwdata.*)
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(4);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+        PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
+    } > ddr3_ram
+
+    PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata));
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end = ABSOLUTE(.);
+    } > ddr3_ram
+
+    /*
+     *
+     * One output section mapped to the associated memory device for each of
+     * the available memory devices. These are not used by default, but can
+     * be used by user applications by using the .section directive.
+     *
+     * The output section used for the heap is treated in a special way,
+     * i.e. the symbols "end" and "_end" are added to point to the heap start.
+     *
+     */
+
+    .ddr3_ram :
+    {
+        PROVIDE (_alt_partition_ddr3_ram_start = ABSOLUTE(.));
+        *(.ddr3_ram .ddr3_ram. ddr3_ram.*)
+        . = ALIGN(4);
+        PROVIDE (_alt_partition_ddr3_ram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        end = ABSOLUTE(.);
+        __alt_stack_base = ABSOLUTE(.);
+    } > ddr3_ram
+
+    PROVIDE (_alt_partition_ddr3_ram_load_addr = LOADADDR(.ddr3_ram));
+
+    .ext_flash_avl_mem :
+    {
+        PROVIDE (_alt_partition_ext_flash_avl_mem_start = ABSOLUTE(.));
+        *(.ext_flash_avl_mem .ext_flash_avl_mem. ext_flash_avl_mem.*)
+        . = ALIGN(4);
+        PROVIDE (_alt_partition_ext_flash_avl_mem_end = ABSOLUTE(.));
+    } > ext_flash_avl_mem
+
+    PROVIDE (_alt_partition_ext_flash_avl_mem_load_addr = LOADADDR(.ext_flash_avl_mem));
+
+    .onchip_flash_data :
+    {
+        PROVIDE (_alt_partition_onchip_flash_data_start = ABSOLUTE(.));
+        *(.onchip_flash_data .onchip_flash_data. onchip_flash_data.*)
+        . = ALIGN(4);
+        PROVIDE (_alt_partition_onchip_flash_data_end = ABSOLUTE(.));
+    } > onchip_flash_data
+
+    PROVIDE (_alt_partition_onchip_flash_data_load_addr = LOADADDR(.onchip_flash_data));
+
+    .descriptor_memory :
+    {
+        PROVIDE (_alt_partition_descriptor_memory_start = ABSOLUTE(.));
+        *(.descriptor_memory .descriptor_memory. descriptor_memory.*)
+        . = ALIGN(4);
+        PROVIDE (_alt_partition_descriptor_memory_end = ABSOLUTE(.));
+    } > descriptor_memory
+
+    PROVIDE (_alt_partition_descriptor_memory_load_addr = LOADADDR(.descriptor_memory));
+
+    .calibration_ram :
+    {
+        PROVIDE (_alt_partition_calibration_ram_start = ABSOLUTE(.));
+        *(.calibration_ram .calibration_ram. calibration_ram.*)
+        . = ALIGN(4);
+        PROVIDE (_alt_partition_calibration_ram_end = ABSOLUTE(.));
+    } > calibration_ram
+
+    PROVIDE (_alt_partition_calibration_ram_load_addr = LOADADDR(.calibration_ram));
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    /* Altera debug extensions */
+    .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) }
+}
+
+/* provide a pointer for the stack */
+
+/*
+ * Don't override this, override the __alt_stack_* symbols instead.
+ */
+__alt_data_end = 0x10000000;
+
+/*
+ * The next two symbols define the location of the default stack.  You can
+ * override them to move the stack to a different memory.
+ */
+PROVIDE( __alt_stack_pointer = __alt_data_end );
+PROVIDE( __alt_stack_limit   = __alt_stack_base );
+
+/*
+ * This symbol controls where the start of the heap is.  If the stack is
+ * contiguous with the heap then the stack will contract as memory is
+ * allocated to the heap.
+ * Override this symbol to put the heap in a different memory.
+ */
+PROVIDE( __alt_heap_start    = end );
+PROVIDE( __alt_heap_limit    = 0x10000000 );
diff --git a/FPGA_nios/hit_pat_bsp/mem_init.mk b/FPGA_nios/hit_pat_bsp/mem_init.mk
new file mode 100644
index 0000000..cf936be
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/mem_init.mk
@@ -0,0 +1,455 @@
+
+#########################################################################
+#######     M E M   I N I T    M A K E F I L E   C O N T E N T     ######
+#########################################################################
+
+#########################################################################
+# This file is intended to be included by public.mk
+#
+#
+# The following variables must be defined before including this file:
+# - ELF
+#
+# The following variables may be defined to override the default behavior:
+# - HDL_SIM_DIR
+# - HDL_SIM_INSTALL_DIR
+# - MEM_INIT_DIR
+# - MEM_INIT_INSTALL_DIR
+# - QUARTUS_PROJECT_DIR
+# - SOPC_NAME
+# - SIM_OPTIMIZE
+# - RESET_ADDRESS
+#
+#########################################################################
+
+#------------------------------------------------------------------------------
+#                         The adjust-path macro
+#
+# If Make is launched from Windows through
+# Windows Subsystem for Linux (WSL).  The adjust-path macro converts absolute windows 
+# paths into unix style paths (Example: c:/dir -> /c/dir). 
+# The adjust_path_mixed function converts WSL path to Windows path.
+# This will ensure paths are readable by GNU Make.
+#------------------------------------------------------------------------------
+
+UNAME = $(shell uname -r)
+ifeq ($(findstring Microsoft,$(UNAME)),Microsoft)
+	WINDOWS_EXE = .exe
+endif
+
+eq = $(and $(findstring $(1),$(2)),$(findstring $(2),$(1)))
+
+ifdef WINDOWS_EXE 
+	adjust-path = $(if $1,$(shell wslpath "$1"),)
+	adjust-path-mixed = $(if $(call eq,$(shell echo $1 | head -c 5),/mnt/),$(shell echo $1 | sed 's/\/mnt\///g;s/\//:\//1'),$1)
+else # !WINDOWS_EXE
+	adjust-path = $1
+	adjust-path-mixed = $1
+endif
+
+
+ifeq ($(MEM_INIT_FILE),)
+# MEM_INIT_FILE should be set equal to the working relative path to this
+# mem_init.mk makefile fragment
+MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST)))
+endif
+
+ifeq ($(ELF2DAT),)
+ELF2DAT := elf2dat
+endif
+
+ifeq ($(ELF2HEX),)
+ELF2HEX := elf2hex$(WINDOWS_EXE)
+endif
+
+ifeq ($(ELF2FLASH),)
+ELF2FLASH := elf2flash$(WINDOWS_EXE)
+endif
+
+ifeq ($(FLASH2DAT),)
+FLASH2DAT := flash2dat
+endif
+
+ifeq ($(ALT_FILE_CONVERT),)
+ALT_FILE_CONVERT := alt-file-convert$(WINDOWS_EXE)
+endif
+
+ifeq ($(NM),)
+NM := nios2-elf-nm$(WINDOWS_EXE)
+endif
+
+ifeq ($(MKDIR),)
+MKDIR := mkdir -p
+endif
+
+ifeq ($(RM),)
+RM := rm -f
+endif
+
+ifeq ($(CP),)
+CP := cp
+endif
+
+ifeq ($(ECHO),)
+ECHO := echo
+endif
+
+MEM_INIT_DIR ?= mem_init
+HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim
+
+ifdef QUARTUS_PROJECT_DIR
+MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))
+ifdef SOPC_NAME
+HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim
+endif
+endif
+
+MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd
+
+MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip
+
+#-------------------------------------
+# Default Flash Boot Loaders
+#-------------------------------------
+
+BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2
+BOOT_LOADER_CFI_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec
+BOOT_LOADER_CFI_BE_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec
+
+ifdef WINDOWS_EXE
+	BOOT_LOADER_CFI=$(shell wslpath -w $(BOOT_LOADER_CFI_LOC))
+	BOOT_LOADER_CFI_BE=$(shell wslpath -w $(BOOT_LOADER_CFI_BE_LOC))
+else # !WINDOWS_EXE
+	BOOT_LOADER_CFI=$(BOOT_LOADER_CFI_LOC)
+	BOOT_LOADER_CFI_BE=$(BOOT_LOADER_CFI_BE_LOC)
+endif
+
+#-------------------------------------
+# Default Target
+#-------------------------------------
+
+.PHONY: default_mem_init
+ifeq ($(QSYS),1)
+default_mem_init: mem_init_generate
+else
+default_mem_init: mem_init_install
+endif
+#-------------------------------------
+# Runtime Macros
+#-------------------------------------
+
+define post-process-info
+	@echo Post-processing to create $@...
+endef
+
+target_stem = $(notdir $(basename $@))
+
+mem_start_address = $($(target_stem)_START)
+mem_end_address = $($(target_stem)_END)
+mem_span = $($(target_stem)_SPAN)
+mem_width = $($(target_stem)_WIDTH)
+mem_hex_width = $($(target_stem)_HEX_DATA_WIDTH)
+mem_endianness = $($(target_stem)_ENDIANNESS)
+mem_create_lanes = $($(target_stem)_CREATE_LANES)
+
+mem_pad_flag = $($(target_stem)_PAD_FLAG)
+mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG)
+mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG)
+
+flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS)
+flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS)
+flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG)
+
+elf2dat_extra_args = $(mem_pad_flag)
+elf2hex_extra_args = $(mem_no_zero_fill_flag)
+elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag)
+flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
+
+#------------------------------------------------------------------------------
+#                              BSP SPECIFIC CONTENT
+#
+# The content below is controlled by the BSP and SOPC System
+#------------------------------------------------------------------------------
+#START OF BSP SPECIFIC
+
+#-------------------------------------
+# Global Settings
+#-------------------------------------
+
+
+# The following TYPE comment allows tools to identify the 'type' of target this 
+# makefile is associated with. 
+# TYPE: BSP_MEMINIT_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to 
+# generate this makefile. A makefile variable is provided for VERSION as well. 
+# ACDS_VERSION: 19.1
+ACDS_VERSION := 19.1
+
+# This following BUILD_NUMBER comment indicates the build number of the tool 
+# used to generate this makefile. 
+# BUILD_NUMBER: 670
+
+# Optimize for simulation
+SIM_OPTIMIZE ?= 0
+
+# The CPU reset address as needed by elf2flash
+RESET_ADDRESS ?= 0x14000000
+
+# The specific Nios II ELF file format to use.
+NIOS2_ELF_FORMAT ?= elf32-littlenios2
+
+#-------------------------------------
+# Pre-Initialized Memory Descriptions
+#-------------------------------------
+
+# Memory: calibration_ram
+MEM_0 := q_sys_calibration_ram
+$(MEM_0)_NAME := calibration_ram
+$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE
+HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex
+MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex
+DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat
+SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym
+$(MEM_0)_START := 0x18403400
+$(MEM_0)_END := 0x1840367f
+$(MEM_0)_SPAN := 0x00000280
+$(MEM_0)_HIERARCHICAL_PATH := calibration_ram
+$(MEM_0)_WIDTH := 16
+$(MEM_0)_HEX_DATA_WIDTH := 16
+$(MEM_0)_ENDIANNESS := --little-endian-mem
+$(MEM_0)_CREATE_LANES := 0
+
+.PHONY: calibration_ram
+calibration_ram: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym
+
+# Memory: ddr3_ram
+MEM_1 := ddr3_ram
+$(MEM_1)_NAME := ddr3_ram
+$(MEM_1)_MEM_INIT_FILE_PARAM_NAME := ABS_RAM_MEM_INIT_FILENAME
+$(MEM_1)_START := 0x08000000
+$(MEM_1)_END := 0x0fffffff
+$(MEM_1)_SPAN := 0x08000000
+$(MEM_1)_HIERARCHICAL_PATH := ddr3_ram
+$(MEM_1)_WIDTH := 32
+$(MEM_1)_HEX_DATA_WIDTH := 32
+$(MEM_1)_ENDIANNESS := --little-endian-mem
+$(MEM_1)_CREATE_LANES := 0
+
+
+# Memory: descriptor_memory
+MEM_2 := q_sys_descriptor_memory
+$(MEM_2)_NAME := descriptor_memory
+$(MEM_2)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE
+HEX_FILES += $(MEM_INIT_DIR)/$(MEM_2).hex
+MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_2).hex
+DAT_FILES += $(HDL_SIM_DIR)/$(MEM_2).dat
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_2).dat
+SYM_FILES += $(HDL_SIM_DIR)/$(MEM_2).sym
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_2).sym
+$(MEM_2)_START := 0x18400000
+$(MEM_2)_END := 0x18401fff
+$(MEM_2)_SPAN := 0x00002000
+$(MEM_2)_HIERARCHICAL_PATH := descriptor_memory
+$(MEM_2)_WIDTH := 32
+$(MEM_2)_HEX_DATA_WIDTH := 32
+$(MEM_2)_ENDIANNESS := --little-endian-mem
+$(MEM_2)_CREATE_LANES := 0
+
+.PHONY: descriptor_memory
+descriptor_memory: check_elf_exists $(MEM_INIT_DIR)/$(MEM_2).hex $(HDL_SIM_DIR)/$(MEM_2).dat $(HDL_SIM_DIR)/$(MEM_2).sym
+
+# Memory: ext_flash
+MEM_3 := ext_flash
+$(MEM_3)_NAME := ext_flash
+HEX_FILES += $(MEM_INIT_DIR)/$(MEM_3).hex
+MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_3).hex
+$(MEM_3)_START := 0x14000000
+$(MEM_3)_END := 0x17ffffff
+$(MEM_3)_SPAN := 0x04000000
+$(MEM_3)_HIERARCHICAL_PATH := ext_flash
+$(MEM_3)_WIDTH := 32
+$(MEM_3)_HEX_DATA_WIDTH := 8
+$(MEM_3)_ENDIANNESS := --little-endian-mem
+$(MEM_3)_CREATE_LANES := 0
+$(MEM_3)_CFI_FLAGS := --base=$($(MEM_3)_START) --end=$($(MEM_3)_END) --reset=$(RESET_ADDRESS)
+$(MEM_3)_BOOT_LOADER_FLAG := --boot="$(BOOT_LOADER_CFI)"
+
+.PHONY: ext_flash
+ext_flash: check_elf_exists $(MEM_INIT_DIR)/$(MEM_3).hex
+
+# Memory: onchip_flash
+MEM_4 := onchip_flash
+$(MEM_4)_NAME := onchip_flash
+$(MEM_4)_MEM_INIT_FILE_PARAM_NAME := INIT_FILENAME
+HEX_FILES += $(MEM_INIT_DIR)/$(MEM_4).hex
+MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_4).hex
+DAT_FILES += $(HDL_SIM_DIR)/$(MEM_4).dat
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_4).dat
+SYM_FILES += $(HDL_SIM_DIR)/$(MEM_4).sym
+HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_4).sym
+FLASH_FILES += $(MEM_4).flash
+$(MEM_4)_START := 0x18200000
+$(MEM_4)_END := 0x1835ffff
+$(MEM_4)_SPAN := 0x00160000
+$(MEM_4)_HIERARCHICAL_PATH := onchip_flash
+$(MEM_4)_WIDTH := 32
+$(MEM_4)_HEX_DATA_WIDTH := 8
+$(MEM_4)_ENDIANNESS := --little-endian-mem
+$(MEM_4)_CREATE_LANES := 0
+$(MEM_4)_CFI_FLAGS := --base=$($(MEM_4)_START) --end=$($(MEM_4)_END) --reset=$(RESET_ADDRESS)
+
+.PHONY: onchip_flash
+onchip_flash: check_elf_exists $(MEM_INIT_DIR)/$(MEM_4).hex $(HDL_SIM_DIR)/$(MEM_4).dat $(HDL_SIM_DIR)/$(MEM_4).sym $(MEM_4).flash
+
+
+#END OF BSP SPECIFIC
+
+#-------------------------------------
+# Pre-Initialized Memory Targets
+#-------------------------------------
+
+.PHONY: mem_init_install mem_init_generate mem_init_clean
+
+ifeq ($(QSYS),1)
+# Target mem_init_install is deprecated for QSys based systems
+# To initialize onchip memories for Quartus II Synthesis with Qsys based systems:
+#  1) Use "make mem_init_genearate"
+#  2) Add the generated mem_init/meminit.qip file to your Quartus II Project
+#
+mem_init_install:
+	$(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project)
+
+else # QSYS != 1, if SopcBuilder based system
+
+ifneq ($(MEM_INIT_INSTALL_DIR),)
+mem_init_install: $(MEM_INIT_INSTALL_FILES)
+endif
+
+ifneq ($(HDL_SIM_INSTALL_DIR),)
+mem_init_install: $(HDL_SIM_INSTALL_FILES)
+endif
+
+mem_init_install: mem_init_generate
+ifeq ($(MEM_INIT_INSTALL_DIR),)
+	@echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable."
+endif
+ifeq ($(HDL_SIM_INSTALL_DIR),)
+	@echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable."
+endif
+
+$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/%
+	@$(MKDIR) $(@D)
+	@$(CP) -v $< $@
+
+$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/%
+	@$(MKDIR) $(@D)
+	@$(CP) -v $< $@
+
+endif # QSYS == 1
+
+
+mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE)
+
+mem_init_clean:
+	@$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES)
+
+.PHONY: hex dat sym flash
+
+hex: check_elf_exists $(HEX_FILES)
+
+dat: check_elf_exists $(DAT_FILES)
+
+sym: check_elf_exists $(SYM_FILES)
+
+flash: check_elf_exists $(FLASH_FILES)
+
+#-------------------------------------
+# Pre-Initialized Memory Rules
+#-------------------------------------
+
+.PHONY: check_elf_exists
+check_elf_exists: $(call adjust-path,$(ELF))
+ifeq ($(ELF),)
+	$(error ELF var not set in mem_init.mk)
+endif
+
+$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(call adjust-path,$(ELF))
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	$(ELF2DAT) --infile=$(call adjust-path-mixed,$<) --outfile=$@ \
+		--base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \
+		$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)
+
+$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat
+	@true
+
+ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $(call adjust-path-mixed,$<) $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \
+			$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@
+			
+ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$(call adjust-path-mixed,$<) --output=$@ \
+			--base=$(mem_start_address) --end=$(mem_end_address) --reset=$(RESET_ADDRESS) \
+			--out-data-width=$(mem_hex_width) $(flash_mem_boot_loader_flag)
+
+ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
+	$(ELF_TO_HEX_CMD_WITH_BOOTLOADER), \
+	$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
+	))
+
+$(HEX_FILES): %.hex: $(call adjust-path,$(ELF))
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	$(ELF_TO_HEX_CMD)
+
+$(SYM_FILES): %.sym: $(call adjust-path,$(ELF))
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	$(NM) -n $(call adjust-path-mixed,$<) > $@
+
+$(FLASH_FILES): %.flash: $(call adjust-path,$(ELF))
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	$(ELF2FLASH) --input=$(call adjust-path-mixed,$<) --output=$@ --sim_optimize=$(SIM_OPTIMIZE) $(elf2flash_extra_args)
+
+#
+# Function generate_spd_entry
+# Arg1: path to the memory initialization file
+# Arg2: Type HEX or DAT
+# Arg3: Output spd file to append
+gen_spd_entry.BASE_FILE = $(basename $(notdir $1))
+gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME)
+gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH)
+gen_spd_entry.SETTINGS = $(strip \
+	path=\"$1\" \
+	type=\"$2\" \
+	$(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \
+	$(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \
+)
+define gen_spd_entry
+$(ECHO) "<file $(gen_spd_entry.SETTINGS) />" >> $3
+endef
+
+$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES))
+$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES))
+
+$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE)
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	@$(RM) $@
+	@$(ECHO) "<?xml version=\"1.0\" encoding=\"UTF-8\"?>" > $@
+	@$(ECHO) "<simPackage>" >> $@
+	@$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true
+	@$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true
+	@$(ECHO) "</simPackage>" >> $@
+
+.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE)
+
+$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE)
+	$(post-process-info)
+	@$(MKDIR) $(@D)
+	@$(RM) $@
+	@$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@
+
+.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE)
diff --git a/FPGA_nios/hit_pat_bsp/memory.gdb b/FPGA_nios/hit_pat_bsp/memory.gdb
new file mode 100644
index 0000000..d6cec49
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/memory.gdb
@@ -0,0 +1,62 @@
+# memory.gdb - GDB memory region definitions
+#
+# Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys'
+# SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+#
+# Generated: Fri Oct 11 10:12:20 CEST 2024
+
+# DO NOT MODIFY THIS FILE
+#
+# Changing this file will have subtle consequences
+# which will almost certainly lead to a nonfunctioning
+# system. If you do modify this file, be aware that your
+# changes will be overwritten and lost when this file
+# is generated again.
+#
+# DO NOT MODIFY THIS FILE
+
+# License Agreement
+#
+# Copyright (c) 2008
+# Altera Corporation, San Jose, California, USA.
+# All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# This agreement shall be governed in all respects by the laws of the State
+# of California and by the laws of the United States of America.
+
+# Define memory regions for each memory connected to the CPU.
+# The cache attribute is specified which improves GDB performance
+# by allowing GDB to cache memory contents on the host.
+
+# ddr3_ram
+memory 0x8000000 0x10000000 cache
+
+# ext_flash_avl_mem
+memory 0x14000000 0x18000000 cache
+
+# onchip_flash_data
+memory 0x18200000 0x18360000 cache
+
+# descriptor_memory
+memory 0x18400000 0x18402000 cache
+
+# calibration_ram
+memory 0x18403400 0x18403680 cache
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_alarm_start.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_alarm_start.d
new file mode 100644
index 0000000..008b27d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_alarm_start.d
@@ -0,0 +1,20 @@
+obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_alarm.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h system.h \
+ linker.h
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_busy_sleep.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_busy_sleep.d
new file mode 100644
index 0000000..488cf80
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_busy_sleep.d
@@ -0,0 +1,10 @@
+obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_busy_sleep.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_close.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_close.d
new file mode 100644
index 0000000..d1106f3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_close.d
@@ -0,0 +1,52 @@
+obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush.d
new file mode 100644
index 0000000..58099b0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \
+ HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_cache.h
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_all.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_all.d
new file mode 100644
index 0000000..8c9b5ca
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_all.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \
+ HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_cache.h
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d
new file mode 100644
index 0000000..cceb745
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_dcache_flush_no_writeback.o: \
+ HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \
+ linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev.d
new file mode 100644
index 0000000..cade27e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \
+ linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev_llist_insert.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev_llist_insert.d
new file mode 100644
index 0000000..d0d1745
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dev_llist_insert.d
@@ -0,0 +1,11 @@
+obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_errno.h
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_errno.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_rxchan_open.d
new file mode 100644
index 0000000..6359b76
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_rxchan_open.d
@@ -0,0 +1,53 @@
+obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \
+ HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \
+ system.h linker.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dma.h:
+
+HAL/inc/sys/alt_dma_dev.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_txchan_open.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_txchan_open.d
new file mode 100644
index 0000000..aa9a93c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_dma_txchan_open.d
@@ -0,0 +1,53 @@
+obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \
+ HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \
+ system.h linker.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dma.h:
+
+HAL/inc/sys/alt_dma_dev.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_ctors.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_ctors.d
new file mode 100644
index 0000000..0898fbc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_ctors.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_dtors.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_dtors.d
new file mode 100644
index 0000000..abdadfa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_do_dtors.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_entry.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_entry.d
new file mode 100644
index 0000000..fde9510
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_entry.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_ecc_fatal_entry.o: HAL/src/alt_ecc_fatal_entry.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_exception.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_exception.d
new file mode 100644
index 0000000..9d775a4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ecc_fatal_exception.d
@@ -0,0 +1,17 @@
+obj/HAL/src/alt_ecc_fatal_exception.o: HAL/src/alt_ecc_fatal_exception.c \
+ HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/sys/alt_exceptions.h \
+ HAL/inc/alt_types.h system.h linker.h HAL/inc/sys/alt_cache.h
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_exceptions.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_environ.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_environ.d
new file mode 100644
index 0000000..5ff8770
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_environ.d
@@ -0,0 +1,4 @@
+obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c \
+ iniche/inc/os/alt_syscall.h
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_errno.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_errno.d
new file mode 100644
index 0000000..a48266f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_errno.d
@@ -0,0 +1,6 @@
+obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_entry.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_entry.d
new file mode 100644
index 0000000..cf58c70
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_entry.d
@@ -0,0 +1,6 @@
+obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \
+ linker.h
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_muldiv.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_muldiv.d
new file mode 100644
index 0000000..a1e5556
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_muldiv.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_trap.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_trap.d
new file mode 100644
index 0000000..ef4edc6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exception_trap.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_execve.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_execve.d
new file mode 100644
index 0000000..6cdf9e2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_execve.d
@@ -0,0 +1,11 @@
+obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \
+ iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exit.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exit.d
new file mode 100644
index 0000000..ae032ed
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_exit.d
@@ -0,0 +1,43 @@
+obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ HAL/inc/sys/alt_sim.h UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h \
+ HAL/inc/sys/alt_log_printf.h
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_sim.h:
+
+UCOSII/inc/os/alt_hooks.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
+
+HAL/inc/sys/alt_log_printf.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fcntl.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fcntl.d
new file mode 100644
index 0000000..c2eea34
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fcntl.d
@@ -0,0 +1,50 @@
+obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_lock.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_lock.d
new file mode 100644
index 0000000..15e8a8d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_lock.d
@@ -0,0 +1,45 @@
+obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_unlock.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_unlock.d
new file mode 100644
index 0000000..6a1bc0c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fd_unlock.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \
+ HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_dev.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_dev.d
new file mode 100644
index 0000000..c944126
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_dev.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_file.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_file.d
new file mode 100644
index 0000000..ac24a13
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_find_file.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_flash_dev.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_flash_dev.d
new file mode 100644
index 0000000..6991935
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_flash_dev.d
@@ -0,0 +1,51 @@
+obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \
+ HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \
+ HAL/inc/sys/alt_flash_types.h HAL/inc/priv/alt_dev_llist.h \
+ HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_flash_dev.h:
+
+HAL/inc/sys/alt_flash_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fork.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fork.d
new file mode 100644
index 0000000..18d88ae
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fork.d
@@ -0,0 +1,10 @@
+obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fs_reg.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fs_reg.d
new file mode 100644
index 0000000..834a14b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fs_reg.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fstat.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fstat.d
new file mode 100644
index 0000000..dd2fa85
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_fstat.d
@@ -0,0 +1,52 @@
+obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_warning.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/priv/alt_file.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_get_fd.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_get_fd.d
new file mode 100644
index 0000000..06d8977
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_get_fd.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getchar.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getchar.d
new file mode 100644
index 0000000..aa88591
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getchar.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getpid.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getpid.d
new file mode 100644
index 0000000..ab536f5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_getpid.d
@@ -0,0 +1,4 @@
+obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c \
+ iniche/inc/os/alt_syscall.h
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gettod.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gettod.d
new file mode 100644
index 0000000..b1ee731
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gettod.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \
+ iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gmon.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gmon.d
new file mode 100644
index 0000000..2c2ae24
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_gmon.d
@@ -0,0 +1,22 @@
+obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \
+ linker.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h
+
+HAL/inc/priv/nios2_gmon_data.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush.d
new file mode 100644
index 0000000..0c35ff0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \
+ HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_cache.h
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush_all.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush_all.d
new file mode 100644
index 0000000..55ae550
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_icache_flush_all.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \
+ HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_cache.h
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic.d
new file mode 100644
index 0000000..c4edbc9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic.d
@@ -0,0 +1,17 @@
+obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_iic_isr_register.h HAL/inc/priv/alt_legacy_irq.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_iic_isr_register.h:
+
+HAL/inc/priv/alt_legacy_irq.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic_isr_register.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic_isr_register.d
new file mode 100644
index 0000000..25f37ad
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_iic_isr_register.d
@@ -0,0 +1,20 @@
+obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \
+ system.h linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/priv/alt_iic_isr_register.h \
+ HAL/inc/sys/alt_irq_entry.h HAL/inc/priv/alt_irq_table.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/priv/alt_iic_isr_register.h:
+
+HAL/inc/sys/alt_irq_entry.h:
+
+HAL/inc/priv/alt_irq_table.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_entry.d
new file mode 100644
index 0000000..6441411
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_entry.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_instruction_exception_entry.o: \
+ HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \
+ HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h
+
+HAL/inc/sys/alt_exceptions.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_register.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_register.d
new file mode 100644
index 0000000..cce2ee1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_instruction_exception_register.d
@@ -0,0 +1,14 @@
+obj/HAL/src/alt_instruction_exception_register.o: \
+ HAL/src/alt_instruction_exception_register.c \
+ HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \
+ HAL/inc/priv/alt_exception_handler_registry.h
+
+HAL/inc/sys/alt_exceptions.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/priv/alt_exception_handler_registry.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_io_redirect.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_io_redirect.d
new file mode 100644
index 0000000..607e73f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_io_redirect.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ioctl.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ioctl.d
new file mode 100644
index 0000000..6fd9e00
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_ioctl.d
@@ -0,0 +1,55 @@
+obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \
+ HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/ioctl.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_entry.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_entry.d
new file mode 100644
index 0000000..c2477c1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_entry.d
@@ -0,0 +1,5 @@
+obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_handler.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_handler.d
new file mode 100644
index 0000000..8d09c3d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_handler.d
@@ -0,0 +1,36 @@
+obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \
+ linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os/alt_hooks.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_register.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_register.d
new file mode 100644
index 0000000..e7860eb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_register.d
@@ -0,0 +1,43 @@
+obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \
+ linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_legacy_irq.h UCOSII/inc/os/alt_hooks.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq_entry.h HAL/inc/priv/alt_irq_table.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_legacy_irq.h:
+
+UCOSII/inc/os/alt_hooks.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq_entry.h:
+
+HAL/inc/priv/alt_irq_table.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_vars.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_vars.d
new file mode 100644
index 0000000..1dc6bb6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_irq_vars.d
@@ -0,0 +1,8 @@
+obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \
+ system.h linker.h
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_isatty.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_isatty.d
new file mode 100644
index 0000000..f87adca
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_isatty.d
@@ -0,0 +1,53 @@
+obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \
+ system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_errno.h \
+ HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_kill.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_kill.d
new file mode 100644
index 0000000..627e134
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_kill.d
@@ -0,0 +1,8 @@
+obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_link.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_link.d
new file mode 100644
index 0000000..9c3ae47
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_link.d
@@ -0,0 +1,10 @@
+obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_load.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_load.d
new file mode 100644
index 0000000..b466280
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_load.d
@@ -0,0 +1,8 @@
+obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h
+
+HAL/inc/sys/alt_load.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_macro.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_macro.d
new file mode 100644
index 0000000..b6c30c4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_macro.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_printf.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_printf.d
new file mode 100644
index 0000000..ddd7cdb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_log_printf.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_lseek.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_lseek.d
new file mode 100644
index 0000000..cab4832
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_lseek.d
@@ -0,0 +1,52 @@
+obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_main.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_main.d
new file mode 100644
index 0000000..19b7ef2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_main.d
@@ -0,0 +1,55 @@
+obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \
+ linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_sys_init.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os/alt_hooks.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ HAL/inc/priv/alt_file.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/sys/alt_log_printf.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_sys_init.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os/alt_hooks.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/sys/alt_log_printf.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_mcount.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_mcount.d
new file mode 100644
index 0000000..4fa3643
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_mcount.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_open.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_open.d
new file mode 100644
index 0000000..7c1ebcb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_open.d
@@ -0,0 +1,52 @@
+obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_printf.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_printf.d
new file mode 100644
index 0000000..0fe3550
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_printf.d
@@ -0,0 +1,3 @@
+obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h
+
+HAL/inc/sys/alt_stdio.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putchar.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putchar.d
new file mode 100644
index 0000000..fa6d19f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putchar.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putcharbuf.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putcharbuf.d
new file mode 100644
index 0000000..e8cbed1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putcharbuf.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_putcharbuf.o: HAL/src/alt_putcharbuf.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putstr.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putstr.d
new file mode 100644
index 0000000..a28ce55
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_putstr.d
@@ -0,0 +1 @@
+obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_read.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_read.d
new file mode 100644
index 0000000..3ae0e6a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_read.d
@@ -0,0 +1,52 @@
+obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_release_fd.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_release_fd.d
new file mode 100644
index 0000000..0337b8e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_release_fd.d
@@ -0,0 +1,46 @@
+obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h HAL/inc/priv/alt_file.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_file.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_cached.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_cached.d
new file mode 100644
index 0000000..286e239
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_cached.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \
+ HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h \
+ system.h linker.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_cache.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_uncached.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_uncached.d
new file mode 100644
index 0000000..0e3cf81
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_remap_uncached.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \
+ HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h \
+ system.h linker.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_cache.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_rename.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_rename.d
new file mode 100644
index 0000000..8194e9b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_rename.d
@@ -0,0 +1,11 @@
+obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \
+ iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_sbrk.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_sbrk.d
new file mode 100644
index 0000000..bb8d492
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_sbrk.d
@@ -0,0 +1,17 @@
+obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c iniche/inc/os/alt_syscall.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \
+ linker.h HAL/inc/sys/alt_stack.h
+
+iniche/inc/os/alt_syscall.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_stack.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_settod.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_settod.d
new file mode 100644
index 0000000..82a8fb0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_settod.d
@@ -0,0 +1,15 @@
+obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_software_exception.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_software_exception.d
new file mode 100644
index 0000000..ee4cb97
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_software_exception.d
@@ -0,0 +1,6 @@
+obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \
+ system.h linker.h
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_stat.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_stat.d
new file mode 100644
index 0000000..dcbaac8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_stat.d
@@ -0,0 +1,3 @@
+obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c iniche/inc/os/alt_syscall.h
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_tick.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_tick.d
new file mode 100644
index 0000000..387e18f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_tick.d
@@ -0,0 +1,36 @@
+obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/os/alt_hooks.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_times.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_times.d
new file mode 100644
index 0000000..dd21e20
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_times.d
@@ -0,0 +1,15 @@
+obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_free.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_free.d
new file mode 100644
index 0000000..0e13c65
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_free.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \
+ HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h \
+ system.h linker.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_cache.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_malloc.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_malloc.d
new file mode 100644
index 0000000..4e009ee
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_uncached_malloc.d
@@ -0,0 +1,13 @@
+obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \
+ HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h \
+ system.h linker.h
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/sys/alt_cache.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_unlink.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_unlink.d
new file mode 100644
index 0000000..73b98a5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_unlink.d
@@ -0,0 +1,11 @@
+obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \
+ iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_usleep.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_usleep.d
new file mode 100644
index 0000000..469f741
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_usleep.d
@@ -0,0 +1,36 @@
+obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c system.h linker.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_alarm.h HAL/inc/priv/alt_busy_sleep.h \
+ iniche/inc/os/alt_syscall.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+HAL/inc/priv/alt_busy_sleep.h:
+
+iniche/inc/os/alt_syscall.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_wait.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_wait.d
new file mode 100644
index 0000000..576748e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_wait.d
@@ -0,0 +1,8 @@
+obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h iniche/inc/os/alt_syscall.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+iniche/inc/os/alt_syscall.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_write.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_write.d
new file mode 100644
index 0000000..3899fa6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/alt_write.d
@@ -0,0 +1,55 @@
+obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/inc/os/alt_syscall.h \
+ HAL/inc/sys/alt_log_printf.h
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_warning.h:
+
+HAL/inc/priv/alt_file.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/inc/os/alt_syscall.h:
+
+HAL/inc/sys/alt_log_printf.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/altera_nios2_gen2_irq.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/altera_nios2_gen2_irq.d
new file mode 100644
index 0000000..d706692
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/altera_nios2_gen2_irq.d
@@ -0,0 +1,15 @@
+obj/HAL/src/altera_nios2_gen2_irq.o: HAL/src/altera_nios2_gen2_irq.c \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \
+ linker.h HAL/inc/altera_nios2_gen2_irq.h
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/altera_nios2_gen2_irq.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/crt0.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/crt0.d
new file mode 100644
index 0000000..4bac550
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/crt0.d
@@ -0,0 +1,10 @@
+obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \
+ HAL/inc/sys/alt_log_printf.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/sys/alt_log_printf.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_a.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_a.d
new file mode 100644
index 0000000..8df99c7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_a.d
@@ -0,0 +1,8 @@
+obj/HAL/src/os_cpu_a.o: HAL/src/os_cpu_a.S UCOSII/inc/os_cfg.h system.h \
+ linker.h
+
+UCOSII/inc/os_cfg.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_c.d b/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_c.d
new file mode 100644
index 0000000..f892d96
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/HAL/src/os_cpu_c.d
@@ -0,0 +1,31 @@
+obj/HAL/src/os_cpu_c.o: HAL/src/os_cpu_c.c HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h system.h linker.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_env_lock.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_env_lock.d
new file mode 100644
index 0000000..187a08c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_env_lock.d
@@ -0,0 +1,31 @@
+obj/UCOSII/src/alt_env_lock.o: UCOSII/src/alt_env_lock.c \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_malloc_lock.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_malloc_lock.d
new file mode 100644
index 0000000..d8ee445
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/alt_malloc_lock.d
@@ -0,0 +1,31 @@
+obj/UCOSII/src/alt_malloc_lock.o: UCOSII/src/alt_malloc_lock.c system.h \
+ linker.h HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_core.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_core.d
new file mode 100644
index 0000000..1e740c5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_core.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_core.o: UCOSII/src/os_core.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_dbg.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_dbg.d
new file mode 100644
index 0000000..becc47a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_dbg.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_dbg.o: UCOSII/src/os_dbg.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_flag.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_flag.d
new file mode 100644
index 0000000..936731e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_flag.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_flag.o: UCOSII/src/os_flag.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mbox.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mbox.d
new file mode 100644
index 0000000..9428b5f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mbox.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_mbox.o: UCOSII/src/os_mbox.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mem.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mem.d
new file mode 100644
index 0000000..989e358
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mem.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_mem.o: UCOSII/src/os_mem.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mutex.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mutex.d
new file mode 100644
index 0000000..2787d0f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_mutex.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_mutex.o: UCOSII/src/os_mutex.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_q.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_q.d
new file mode 100644
index 0000000..1e668ff
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_q.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_q.o: UCOSII/src/os_q.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_sem.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_sem.d
new file mode 100644
index 0000000..238f13c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_sem.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_sem.o: UCOSII/src/os_sem.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_task.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_task.d
new file mode 100644
index 0000000..935bd61
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_task.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_task.o: UCOSII/src/os_task.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_time.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_time.d
new file mode 100644
index 0000000..cbf5ca3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_time.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_time.o: UCOSII/src/os_time.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_tmr.d b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_tmr.d
new file mode 100644
index 0000000..97cc0e0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/UCOSII/src/os_tmr.d
@@ -0,0 +1,26 @@
+obj/UCOSII/src/os_tmr.o: UCOSII/src/os_tmr.c UCOSII/inc/ucos_ii.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h system.h linker.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h
+
+UCOSII/inc/ucos_ii.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/alt_sys_init.d b/FPGA_nios/hit_pat_bsp/obj/alt_sys_init.d
new file mode 100644
index 0000000..9694730
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/alt_sys_init.d
@@ -0,0 +1,173 @@
+obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \
+ HAL/inc/sys/alt_sys_init.h HAL/inc/altera_nios2_gen2_irq.h \
+ drivers/inc/altera_avalon_sysid_qsys.h drivers/inc/altera_avalon_timer.h \
+ HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_warning.h \
+ drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \
+ UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \
+ drivers/inc/altera_avalon_uart_fd.h drivers/inc/altera_eth_tse.h \
+ drivers/inc/iniche/altera_eth_tse_iniche.h iniche/inc/alt_iniche_dev.h \
+ iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpport.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/profiler.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/tcpport.h drivers/inc/altera_eth_tse_regs.h HAL/inc/io.h \
+ HAL/inc/alt_types.h drivers/inc/iniche/ins_tse_mac.h \
+ drivers/inc/altera_msgdma.h drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h \
+ drivers/inc/altera_msgdma_csr_regs.h drivers/inc/altera_avalon_tse.h \
+ drivers/inc/altera_eth_tse_regs.h drivers/inc/altera_msgdma.h \
+ drivers/inc/altera_generic_quad_spi_controller.h \
+ HAL/inc/sys/alt_flash_dev.h HAL/inc/sys/alt_flash_types.h \
+ drivers/inc/altera_onchip_flash.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+HAL/inc/sys/alt_sys_init.h:
+
+HAL/inc/altera_nios2_gen2_irq.h:
+
+drivers/inc/altera_avalon_sysid_qsys.h:
+
+drivers/inc/altera_avalon_timer.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_warning.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
+
+drivers/inc/altera_eth_tse.h:
+
+drivers/inc/iniche/altera_eth_tse_iniche.h:
+
+iniche/inc/alt_iniche_dev.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/iniche/ins_tse_mac.h:
+
+drivers/inc/altera_msgdma.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_avalon_tse.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+drivers/inc/altera_msgdma.h:
+
+drivers/inc/altera_generic_quad_spi_controller.h:
+
+HAL/inc/sys/alt_flash_dev.h:
+
+HAL/inc/sys/alt_flash_types.h:
+
+drivers/inc/altera_onchip_flash.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d
new file mode 100644
index 0000000..91c44fc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d
@@ -0,0 +1,19 @@
+obj/drivers/src/altera_avalon_sysid_qsys.o: \
+ drivers/src/altera_avalon_sysid_qsys.c \
+ drivers/inc/altera_avalon_sysid_qsys.h HAL/inc/alt_types.h \
+ drivers/inc/altera_avalon_sysid_qsys_regs.h HAL/inc/io.h \
+ HAL/inc/alt_types.h system.h linker.h
+
+drivers/inc/altera_avalon_sysid_qsys.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_avalon_sysid_qsys_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_sc.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_sc.d
new file mode 100644
index 0000000..cbaca62
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_sc.d
@@ -0,0 +1,42 @@
+obj/drivers/src/altera_avalon_timer_sc.o: \
+ drivers/src/altera_avalon_timer_sc.c HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h system.h linker.h \
+ drivers/inc/altera_avalon_timer.h HAL/inc/sys/alt_dev.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ HAL/inc/sys/alt_warning.h drivers/inc/altera_avalon_timer_regs.h \
+ HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/sys/alt_log_printf.h
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+system.h:
+
+linker.h:
+
+drivers/inc/altera_avalon_timer.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_warning.h:
+
+drivers/inc/altera_avalon_timer_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_log_printf.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_ts.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_ts.d
new file mode 100644
index 0000000..b5e8348
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_ts.d
@@ -0,0 +1,31 @@
+obj/drivers/src/altera_avalon_timer_ts.o: \
+ drivers/src/altera_avalon_timer_ts.c system.h linker.h \
+ HAL/inc/sys/alt_timestamp.h HAL/inc/alt_types.h \
+ drivers/inc/altera_avalon_timer.h HAL/inc/sys/alt_dev.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ HAL/inc/sys/alt_warning.h drivers/inc/altera_avalon_timer_regs.h \
+ HAL/inc/io.h HAL/inc/alt_types.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_timestamp.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_avalon_timer.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_warning.h:
+
+drivers/inc/altera_avalon_timer_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_vars.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_vars.d
new file mode 100644
index 0000000..1e0d399
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_timer_vars.d
@@ -0,0 +1,21 @@
+obj/drivers/src/altera_avalon_timer_vars.o: \
+ drivers/src/altera_avalon_timer_vars.c drivers/inc/altera_avalon_timer.h \
+ HAL/inc/alt_types.h HAL/inc/sys/alt_dev.h system.h linker.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ HAL/inc/sys/alt_warning.h
+
+drivers/inc/altera_avalon_timer.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_warning.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse.d
new file mode 100644
index 0000000..fa1cad4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse.d
@@ -0,0 +1,84 @@
+obj/drivers/src/altera_avalon_tse.o: drivers/src/altera_avalon_tse.c \
+ drivers/inc/altera_avalon_tse.h drivers/inc/altera_eth_tse_regs.h \
+ HAL/inc/alt_types.h HAL/inc/io.h HAL/inc/alt_types.h system.h linker.h \
+ iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ drivers/inc/altera_msgdma.h HAL/inc/sys/alt_dev.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/sys/alt_cache.h
+
+drivers/inc/altera_avalon_tse.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+drivers/inc/altera_msgdma.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse_system_info.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse_system_info.d
new file mode 100644
index 0000000..3320fba
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_tse_system_info.d
@@ -0,0 +1,88 @@
+obj/drivers/src/altera_avalon_tse_system_info.o: \
+ drivers/src/altera_avalon_tse_system_info.c iniche/src/h/nios2/ipport.h \
+ system.h linker.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ drivers/inc/altera_avalon_tse.h drivers/inc/altera_eth_tse_regs.h \
+ HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_msgdma.h \
+ HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h \
+ drivers/inc/altera_avalon_tse_system_info.h \
+ drivers/inc/altera_avalon_tse.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+drivers/inc/altera_avalon_tse.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_msgdma.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_tse_system_info.h:
+
+drivers/inc/altera_avalon_tse.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_fd.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_fd.d
new file mode 100644
index 0000000..0077584
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_fd.d
@@ -0,0 +1,58 @@
+obj/drivers/src/altera_avalon_uart_fd.o: \
+ drivers/src/altera_avalon_uart_fd.c HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h drivers/inc/altera_avalon_uart.h \
+ HAL/inc/sys/termios.h HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h drivers/inc/altera_avalon_uart_fd.h
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+HAL/inc/sys/alt_warning.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_init.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_init.d
new file mode 100644
index 0000000..2cec24f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_init.d
@@ -0,0 +1,73 @@
+obj/drivers/src/altera_avalon_uart_init.o: \
+ drivers/src/altera_avalon_uart_init.c HAL/inc/sys/alt_dev.h system.h \
+ linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \
+ drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \
+ HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h drivers/inc/altera_avalon_uart_fd.h \
+ drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/sys/ioctl.h:
+
+HAL/inc/sys/alt_errno.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+HAL/inc/sys/alt_warning.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
+
+drivers/inc/altera_avalon_uart_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d
new file mode 100644
index 0000000..9209025
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d
@@ -0,0 +1,74 @@
+obj/drivers/src/altera_avalon_uart_ioctl.o: \
+ drivers/src/altera_avalon_uart_ioctl.c HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \
+ drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h \
+ drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \
+ HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h drivers/inc/altera_avalon_uart_fd.h \
+ HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/ioctl.h:
+
+HAL/inc/sys/alt_errno.h:
+
+drivers/inc/altera_avalon_uart_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+HAL/inc/sys/alt_warning.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_read.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_read.d
new file mode 100644
index 0000000..3a2d81c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_read.d
@@ -0,0 +1,74 @@
+obj/drivers/src/altera_avalon_uart_read.o: \
+ drivers/src/altera_avalon_uart_read.c HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \
+ drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \
+ HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h drivers/inc/altera_avalon_uart_fd.h \
+ HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h drivers/inc/altera_avalon_uart_regs.h \
+ HAL/inc/io.h HAL/inc/alt_types.h
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/ioctl.h:
+
+HAL/inc/sys/alt_errno.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+HAL/inc/sys/alt_warning.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_avalon_uart_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_write.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_write.d
new file mode 100644
index 0000000..d6b1c6f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_avalon_uart_write.d
@@ -0,0 +1,73 @@
+obj/drivers/src/altera_avalon_uart_write.o: \
+ drivers/src/altera_avalon_uart_write.c HAL/inc/sys/alt_dev.h system.h \
+ linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \
+ HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \
+ drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h \
+ drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \
+ HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h drivers/inc/altera_avalon_uart_fd.h
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/sys/ioctl.h:
+
+HAL/inc/sys/alt_errno.h:
+
+drivers/inc/altera_avalon_uart_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_avalon_uart.h:
+
+HAL/inc/sys/termios.h:
+
+HAL/inc/sys/alt_warning.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+drivers/inc/altera_avalon_uart_fd.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_generic_quad_spi_controller.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_generic_quad_spi_controller.d
new file mode 100644
index 0000000..78debfb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_generic_quad_spi_controller.d
@@ -0,0 +1,33 @@
+obj/drivers/src/altera_generic_quad_spi_controller.o: \
+ drivers/src/altera_generic_quad_spi_controller.c HAL/inc/io.h \
+ HAL/inc/alt_types.h HAL/inc/alt_types.h \
+ drivers/inc/altera_generic_quad_spi_controller_regs.h \
+ drivers/inc/altera_generic_quad_spi_controller.h \
+ HAL/inc/sys/alt_flash_dev.h HAL/inc/sys/alt_flash_types.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ HAL/inc/priv/alt_busy_sleep.h HAL/inc/sys/alt_debug.h \
+ HAL/inc/sys/alt_cache.h
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_generic_quad_spi_controller_regs.h:
+
+drivers/inc/altera_generic_quad_spi_controller.h:
+
+HAL/inc/sys/alt_flash_dev.h:
+
+HAL/inc/sys/alt_flash_types.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+HAL/inc/priv/alt_busy_sleep.h:
+
+HAL/inc/sys/alt_debug.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_msgdma.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_msgdma.d
new file mode 100644
index 0000000..f09c17a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_msgdma.d
@@ -0,0 +1,87 @@
+obj/drivers/src/altera_msgdma.o: drivers/src/altera_msgdma.c \
+ drivers/inc/altera_msgdma_descriptor_regs.h HAL/inc/io.h \
+ HAL/inc/alt_types.h drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h drivers/inc/altera_msgdma.h \
+ HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \
+ drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/priv/alt_busy_sleep.h \
+ HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_stdio.h \
+ HAL/inc/sys/alt_cache.h
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma.h:
+
+HAL/inc/sys/alt_dev.h:
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+HAL/inc/priv/alt_busy_sleep.h:
+
+HAL/inc/sys/alt_errno.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/sys/alt_stdio.h:
+
+HAL/inc/sys/alt_cache.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_onchip_flash.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_onchip_flash.d
new file mode 100644
index 0000000..30b72fb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/altera_onchip_flash.d
@@ -0,0 +1,31 @@
+obj/drivers/src/altera_onchip_flash.o: drivers/src/altera_onchip_flash.c \
+ HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/alt_types.h \
+ HAL/inc/sys/alt_debug.h HAL/inc/sys/alt_cache.h \
+ drivers/inc/altera_onchip_flash.h HAL/inc/sys/alt_flash_dev.h \
+ HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_dev_llist.h drivers/inc/altera_onchip_flash_regs.h \
+ HAL/inc/priv/alt_busy_sleep.h
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/sys/alt_debug.h:
+
+HAL/inc/sys/alt_cache.h:
+
+drivers/inc/altera_onchip_flash.h:
+
+HAL/inc/sys/alt_flash_dev.h:
+
+HAL/inc/sys/alt_flash_types.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_onchip_flash_regs.h:
+
+HAL/inc/priv/alt_busy_sleep.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/drivers/src/iniche/ins_tse_mac.d b/FPGA_nios/hit_pat_bsp/obj/drivers/src/iniche/ins_tse_mac.d
new file mode 100644
index 0000000..84e3b8b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/drivers/src/iniche/ins_tse_mac.d
@@ -0,0 +1,162 @@
+obj/drivers/src/iniche/ins_tse_mac.o: drivers/src/iniche/ins_tse_mac.c \
+ HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \
+ iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/in_utils.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/q.h \
+ iniche/src/h/ether.h drivers/inc/altera_avalon_timer_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_avalon_tse.h drivers/inc/altera_eth_tse_regs.h \
+ drivers/inc/altera_msgdma.h HAL/inc/sys/alt_dev.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \
+ drivers/inc/altera_msgdma_csr_regs.h \
+ drivers/inc/altera_msgdma_descriptor_regs.h \
+ drivers/inc/altera_msgdma_response_regs.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h UCOSII/inc/os/alt_sem.h \
+ UCOSII/inc/priv/alt_sem_ucosii.h UCOSII/inc/os/alt_flag.h \
+ UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/sys/alt_cache.h drivers/inc/altera_eth_tse_regs.h \
+ drivers/inc/iniche/altera_eth_tse_iniche.h iniche/inc/alt_iniche_dev.h \
+ iniche/src/h/tcpport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ drivers/inc/iniche/ins_tse_mac.h drivers/inc/altera_msgdma.h \
+ drivers/inc/altera_msgdma_prefetcher_regs.h \
+ drivers/inc/altera_msgdma_csr_regs.h drivers/inc/iniche/ins_tse_mac.h \
+ iniche/src/h/socket.h iniche/src/h/tcpapp.h
+
+HAL/inc/io.h:
+
+HAL/inc/alt_types.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/ether.h:
+
+drivers/inc/altera_avalon_timer_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_avalon_tse.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+drivers/inc/altera_msgdma.h:
+
+HAL/inc/sys/alt_dev.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_dev_llist.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/altera_msgdma_descriptor_regs.h:
+
+drivers/inc/altera_msgdma_response_regs.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+UCOSII/inc/os/alt_sem.h:
+
+UCOSII/inc/priv/alt_sem_ucosii.h:
+
+UCOSII/inc/os/alt_flag.h:
+
+UCOSII/inc/priv/alt_flag_ucosii.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/sys/alt_cache.h:
+
+drivers/inc/altera_eth_tse_regs.h:
+
+drivers/inc/iniche/altera_eth_tse_iniche.h:
+
+iniche/inc/alt_iniche_dev.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+drivers/inc/iniche/ins_tse_mac.h:
+
+drivers/inc/altera_msgdma.h:
+
+drivers/inc/altera_msgdma_prefetcher_regs.h:
+
+drivers/inc/altera_msgdma_csr_regs.h:
+
+drivers/inc/iniche/ins_tse_mac.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/tcpapp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/allports.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/allports.d
new file mode 100644
index 0000000..5ecc599
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/allports.d
@@ -0,0 +1,86 @@
+obj/iniche/src/allports/allports.o: iniche/src/allports/allports.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ether.h iniche/src/h/arp.h iniche/src/h/ip.h \
+ iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/allports/../ipmc/igmp_cmn.h iniche/src/h/menu.h \
+ iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/allports/../nios2/osport.h iniche/src/h/nvparms.h \
+ iniche/src/h/nvfsio.h iniche/src/h/app_ping.h iniche/src/h/task.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ether.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/allports/../ipmc/igmp_cmn.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/allports/../nios2/osport.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/timeouts.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/timeouts.d
new file mode 100644
index 0000000..44a370e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/timeouts.d
@@ -0,0 +1,64 @@
+obj/iniche/src/allports/timeouts.o: iniche/src/allports/timeouts.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/intimers.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/intimers.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/tk_misc.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/tk_misc.d
new file mode 100644
index 0000000..22617ac
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/allports/tk_misc.d
@@ -0,0 +1,81 @@
+obj/iniche/src/allports/tk_misc.o: iniche/src/allports/tk_misc.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/allports/../nios2/osport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/h/nvparms.h iniche/src/h/libport.h iniche/src/h/nvfsio.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/app_ping.h \
+ iniche/src/h/task.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/allports/../nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_close.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_close.d
new file mode 100644
index 0000000..782b2a7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_close.d
@@ -0,0 +1,78 @@
+obj/iniche/src/alt_iniche_close.o: iniche/src/alt_iniche_close.c system.h \
+ linker.h HAL/inc/sys/alt_sys_wrappers.h iniche/inc/os/alt_syscall.h \
+ iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_sys_wrappers.h:
+
+iniche/inc/os/alt_syscall.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_dev.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_dev.d
new file mode 100644
index 0000000..30dc2da
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_dev.d
@@ -0,0 +1,80 @@
+obj/iniche/src/alt_iniche_dev.o: iniche/src/alt_iniche_dev.c \
+ HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h iniche/inc/alt_iniche_dev.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h iniche/src/ipmc/igmp_cmn.h
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/alt_types.h:
+
+iniche/inc/alt_iniche_dev.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ipmc/igmp_cmn.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_fcntl.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_fcntl.d
new file mode 100644
index 0000000..3a5f3aa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_fcntl.d
@@ -0,0 +1,78 @@
+obj/iniche/src/alt_iniche_fcntl.o: iniche/src/alt_iniche_fcntl.c system.h \
+ linker.h HAL/inc/sys/alt_sys_wrappers.h iniche/inc/os/alt_syscall.h \
+ iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+system.h:
+
+linker.h:
+
+HAL/inc/sys/alt_sys_wrappers.h:
+
+iniche/inc/os/alt_syscall.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_read.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_read.d
new file mode 100644
index 0000000..e3685a0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_read.d
@@ -0,0 +1,78 @@
+obj/iniche/src/alt_iniche_read.o: iniche/src/alt_iniche_read.c \
+ HAL/inc/sys/alt_sys_wrappers.h iniche/inc/os/alt_syscall.h system.h \
+ linker.h iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+HAL/inc/sys/alt_sys_wrappers.h:
+
+iniche/inc/os/alt_syscall.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_write.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_write.d
new file mode 100644
index 0000000..f13b3c8
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/alt_iniche_write.d
@@ -0,0 +1,78 @@
+obj/iniche/src/alt_iniche_write.o: iniche/src/alt_iniche_write.c \
+ HAL/inc/sys/alt_sys_wrappers.h iniche/inc/os/alt_syscall.h system.h \
+ linker.h iniche/src/h/nios2/ipport.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+HAL/inc/sys/alt_sys_wrappers.h:
+
+iniche/inc/os/alt_syscall.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nios2/ipport.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/autoip.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/autoip.d
new file mode 100644
index 0000000..613d0f2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/autoip.d
@@ -0,0 +1,41 @@
+obj/iniche/src/autoip4/autoip.o: iniche/src/autoip4/autoip.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnp.d
new file mode 100644
index 0000000..a862959
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnp.d
@@ -0,0 +1,41 @@
+obj/iniche/src/autoip4/upnp.o: iniche/src/autoip4/upnp.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnpmenu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnpmenu.d
new file mode 100644
index 0000000..6a22239
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/autoip4/upnpmenu.d
@@ -0,0 +1,41 @@
+obj/iniche/src/autoip4/upnpmenu.o: iniche/src/autoip4/upnpmenu.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpclnt.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpclnt.d
new file mode 100644
index 0000000..e5f9d20
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpclnt.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ftp/ftpclnt.o: iniche/src/ftp/ftpclnt.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcport.d
new file mode 100644
index 0000000..cad8997
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcport.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ftp/ftpcport.o: iniche/src/ftp/ftpcport.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcprn.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcprn.d
new file mode 100644
index 0000000..7f0e1da
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpcprn.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ftp/ftpcprn.o: iniche/src/ftp/ftpcprn.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpmenu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpmenu.d
new file mode 100644
index 0000000..1a432cf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpmenu.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ftp/ftpmenu.o: iniche/src/ftp/ftpmenu.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsport.d
new file mode 100644
index 0000000..9ca9ace
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsport.d
@@ -0,0 +1,116 @@
+obj/iniche/src/ftp/ftpsport.o: iniche/src/ftp/ftpsport.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h iniche/src/ftp/ftpsrv.h \
+ iniche/src/h/vfsfiles.h iniche/src/ftp/../nios2/osport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/arp.h iniche/src/h/ip.h iniche/src/h/icmp.h \
+ iniche/src/h/udp.h iniche/src/h/nvparms.h iniche/src/h/nvfsio.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/app_ping.h \
+ iniche/src/h/task.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
+
+iniche/src/ftp/ftpsrv.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/ftp/../nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsrv.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsrv.d
new file mode 100644
index 0000000..a9a1a4a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsrv.d
@@ -0,0 +1,83 @@
+obj/iniche/src/ftp/ftpsrv.o: iniche/src/ftp/ftpsrv.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h iniche/src/ftp/ftpsrv.h \
+ iniche/src/h/vfsfiles.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
+
+iniche/src/ftp/ftpsrv.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpssock.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpssock.d
new file mode 100644
index 0000000..f89cfef
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpssock.d
@@ -0,0 +1,83 @@
+obj/iniche/src/ftp/ftpssock.o: iniche/src/ftp/ftpssock.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h iniche/src/ftp/ftpsrv.h \
+ iniche/src/h/vfsfiles.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
+
+iniche/src/ftp/ftpsrv.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsvfs.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsvfs.d
new file mode 100644
index 0000000..b2e7590
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ftp/ftpsvfs.d
@@ -0,0 +1,85 @@
+obj/iniche/src/ftp/ftpsvfs.o: iniche/src/ftp/ftpsvfs.c \
+ iniche/src/ftp/ftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/tcpapp.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/userpass.h iniche/src/ftp/ftpsrv.h \
+ iniche/src/h/vfsfiles.h iniche/src/h/in_utils.h
+
+iniche/src/ftp/ftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/userpass.h:
+
+iniche/src/ftp/ftpsrv.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/h/in_utils.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/et_arp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/et_arp.d
new file mode 100644
index 0000000..35e21bc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/et_arp.d
@@ -0,0 +1,62 @@
+obj/iniche/src/ip/et_arp.o: iniche/src/ip/et_arp.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ether.h iniche/src/h/arp.h iniche/src/h/ip.h \
+ iniche/src/h/intimers.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ether.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/intimers.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/icmp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/icmp.d
new file mode 100644
index 0000000..901cf58
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/icmp.d
@@ -0,0 +1,59 @@
+obj/iniche/src/ip/icmp.o: iniche/src/ip/icmp.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/pmtu.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/pmtu.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iface.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iface.d
new file mode 100644
index 0000000..2b1b924
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iface.d
@@ -0,0 +1,88 @@
+obj/iniche/src/ip/iface.o: iniche/src/ip/iface.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/arp.h iniche/src/h/tcpport.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/ip/../tcp/in_pcb.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ip/../tcp/in_pcb.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip.d
new file mode 100644
index 0000000..d646423
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip.d
@@ -0,0 +1,61 @@
+obj/iniche/src/ip/ip.o: iniche/src/ip/ip.c iniche/src/h/nios2/ipport.h \
+ system.h linker.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/ip/ip_reasm.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/ip/ip_reasm.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip_reasm.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip_reasm.d
new file mode 100644
index 0000000..78bc5f3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ip_reasm.d
@@ -0,0 +1,41 @@
+obj/iniche/src/ip/ip_reasm.o: iniche/src/ip/ip_reasm.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipdemux.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipdemux.d
new file mode 100644
index 0000000..8b06a0f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipdemux.d
@@ -0,0 +1,62 @@
+obj/iniche/src/ip/ipdemux.o: iniche/src/ip/ipdemux.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/ip/../ipmc/igmp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/ip/../ipmc/igmp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipmc.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipmc.d
new file mode 100644
index 0000000..0876610
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipmc.d
@@ -0,0 +1,55 @@
+obj/iniche/src/ip/ipmc.o: iniche/src/ip/ipmc.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/ip.h \
+ iniche/src/ip/../ipmc/igmp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/ip/../ipmc/igmp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipnet.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipnet.d
new file mode 100644
index 0000000..da8b485
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipnet.d
@@ -0,0 +1,59 @@
+obj/iniche/src/ip/ipnet.o: iniche/src/ip/ipnet.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/arp.h iniche/src/h/ether.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ether.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipport.d
new file mode 100644
index 0000000..2f92c98
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipport.d
@@ -0,0 +1,55 @@
+obj/iniche/src/ip/ipport.o: iniche/src/ip/ipport.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipraw.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipraw.d
new file mode 100644
index 0000000..8df89d7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipraw.d
@@ -0,0 +1,55 @@
+obj/iniche/src/ip/ipraw.o: iniche/src/ip/ipraw.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iproute.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iproute.d
new file mode 100644
index 0000000..21696b7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/iproute.d
@@ -0,0 +1,55 @@
+obj/iniche/src/ip/iproute.o: iniche/src/ip/iproute.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipstart.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipstart.d
new file mode 100644
index 0000000..d2d12c5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/ipstart.d
@@ -0,0 +1,64 @@
+obj/iniche/src/ip/ipstart.o: iniche/src/ip/ipstart.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/h/arp.h iniche/src/ip/../ipmc/igmp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/ip/../ipmc/igmp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/pmtu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/pmtu.d
new file mode 100644
index 0000000..5699beb
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/pmtu.d
@@ -0,0 +1,41 @@
+obj/iniche/src/ip/pmtu.o: iniche/src/ip/pmtu.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/rtbtree.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/rtbtree.d
new file mode 100644
index 0000000..fd3b420
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/rtbtree.d
@@ -0,0 +1,41 @@
+obj/iniche/src/ip/rtbtree.o: iniche/src/ip/rtbtree.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/udp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/udp.d
new file mode 100644
index 0000000..5f7a741
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ip/udp.d
@@ -0,0 +1,87 @@
+obj/iniche/src/ip/udp.o: iniche/src/ip/udp.c iniche/src/h/nios2/ipport.h \
+ system.h linker.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/ip.h \
+ iniche/src/h/icmp.h iniche/src/h/udp.h iniche/src/h/tcpport.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/mbuf.h \
+ iniche/src/h/socket.h iniche/src/h/sockvar.h iniche/src/h/sockcall.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp.d
new file mode 100644
index 0000000..c29dd24
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp.d
@@ -0,0 +1,83 @@
+obj/iniche/src/ipmc/igmp.o: iniche/src/ipmc/igmp.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/ipmc/../tcp/in_pcb.h iniche/src/ipmc/../tcp/protosw.h \
+ iniche/src/ipmc/igmp.h iniche/src/ipmc/igmp_cmn.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ipmc/../tcp/in_pcb.h:
+
+iniche/src/ipmc/../tcp/protosw.h:
+
+iniche/src/ipmc/igmp.h:
+
+iniche/src/ipmc/igmp_cmn.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp2.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp2.d
new file mode 100644
index 0000000..1ea406c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp2.d
@@ -0,0 +1,86 @@
+obj/iniche/src/ipmc/igmp2.o: iniche/src/ipmc/igmp2.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/ipmc/../tcp/in_pcb.h iniche/src/ipmc/../tcp/protosw.h \
+ iniche/src/ipmc/igmp.h iniche/src/ipmc/igmp_cmn.h \
+ iniche/src/ipmc/igmp2.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ipmc/../tcp/in_pcb.h:
+
+iniche/src/ipmc/../tcp/protosw.h:
+
+iniche/src/ipmc/igmp.h:
+
+iniche/src/ipmc/igmp_cmn.h:
+
+iniche/src/ipmc/igmp2.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp_cmn.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp_cmn.d
new file mode 100644
index 0000000..487ca64
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/igmp_cmn.d
@@ -0,0 +1,86 @@
+obj/iniche/src/ipmc/igmp_cmn.o: iniche/src/ipmc/igmp_cmn.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/ipmc/../tcp/in_pcb.h iniche/src/ipmc/../tcp/protosw.h \
+ iniche/src/ipmc/igmp.h iniche/src/ipmc/igmp2.h \
+ iniche/src/ipmc/igmp_cmn.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ipmc/../tcp/in_pcb.h:
+
+iniche/src/ipmc/../tcp/protosw.h:
+
+iniche/src/ipmc/igmp.h:
+
+iniche/src/ipmc/igmp2.h:
+
+iniche/src/ipmc/igmp_cmn.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/ipopt.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/ipopt.d
new file mode 100644
index 0000000..69dda25
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/ipopt.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ipmc/ipopt.o: iniche/src/ipmc/ipopt.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/ipmc/../tcp/in_pcb.h iniche/src/ipmc/../tcp/protosw.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/ipmc/../tcp/in_pcb.h:
+
+iniche/src/ipmc/../tcp/protosw.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/u_mctest.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/u_mctest.d
new file mode 100644
index 0000000..acd1727
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/ipmc/u_mctest.d
@@ -0,0 +1,78 @@
+obj/iniche/src/ipmc/u_mctest.o: iniche/src/ipmc/u_mctest.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/app_ping.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/app_ping.d
new file mode 100644
index 0000000..c0ef651
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/app_ping.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/app_ping.o: iniche/src/misclib/app_ping.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/bsdsock.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/bsdsock.d
new file mode 100644
index 0000000..cf7590f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/bsdsock.d
@@ -0,0 +1,83 @@
+obj/iniche/src/misclib/bsdsock.o: iniche/src/misclib/bsdsock.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/ip.h \
+ iniche/src/h/bsdsock.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/sockvar.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/sockvar.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cksum.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cksum.d
new file mode 100644
index 0000000..f97b019
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cksum.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/cksum.o: iniche/src/misclib/cksum.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cu_srv.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cu_srv.d
new file mode 100644
index 0000000..2da0370
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/cu_srv.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/cu_srv.o: iniche/src/misclib/cu_srv.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/dhcsetup.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/dhcsetup.d
new file mode 100644
index 0000000..303494b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/dhcsetup.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/dhcsetup.o: iniche/src/misclib/dhcsetup.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/genlist.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/genlist.d
new file mode 100644
index 0000000..4c6ab95
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/genlist.d
@@ -0,0 +1,43 @@
+obj/iniche/src/misclib/genlist.o: iniche/src/misclib/genlist.c \
+ iniche/src/h/genlist.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h
+
+iniche/src/h/genlist.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/in_utils.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/in_utils.d
new file mode 100644
index 0000000..d990c8e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/in_utils.d
@@ -0,0 +1,71 @@
+obj/iniche/src/misclib/in_utils.o: iniche/src/misclib/in_utils.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/ether.h \
+ iniche/src/h/arp.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/ether.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_log.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_log.d
new file mode 100644
index 0000000..78e0f17
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_log.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/iniche_log.o: iniche/src/misclib/iniche_log.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_qsort.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_qsort.d
new file mode 100644
index 0000000..4e70c1a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/iniche_qsort.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/iniche_qsort.o: iniche/src/misclib/iniche_qsort.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/localtime.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/localtime.d
new file mode 100644
index 0000000..1253593
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/localtime.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/localtime.o: iniche/src/misclib/localtime.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memdev.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memdev.d
new file mode 100644
index 0000000..0675aa5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memdev.d
@@ -0,0 +1,43 @@
+obj/iniche/src/misclib/memdev.o: iniche/src/misclib/memdev.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/vfsfiles.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memio.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memio.d
new file mode 100644
index 0000000..c36eee3
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memio.d
@@ -0,0 +1,48 @@
+obj/iniche/src/misclib/memio.o: iniche/src/misclib/memio.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/memwrap.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/memwrap.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memwrap.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memwrap.d
new file mode 100644
index 0000000..707fc5c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/memwrap.d
@@ -0,0 +1,48 @@
+obj/iniche/src/misclib/memwrap.o: iniche/src/misclib/memwrap.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/memwrap.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/memwrap.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menulib.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menulib.d
new file mode 100644
index 0000000..8efbe20
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menulib.d
@@ -0,0 +1,73 @@
+obj/iniche/src/misclib/menulib.o: iniche/src/misclib/menulib.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/ip.h \
+ iniche/src/h/icmp.h iniche/src/h/ether.h iniche/src/h/arp.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/nvparms.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/ether.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/nvparms.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menus.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menus.d
new file mode 100644
index 0000000..eb4e833
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/menus.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/menus.o: iniche/src/misclib/menus.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/msring.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/msring.d
new file mode 100644
index 0000000..7c330f0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/msring.d
@@ -0,0 +1,73 @@
+obj/iniche/src/misclib/msring.o: iniche/src/misclib/msring.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/netmain.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/netmain.d
new file mode 100644
index 0000000..a494868
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/netmain.d
@@ -0,0 +1,81 @@
+obj/iniche/src/misclib/netmain.o: iniche/src/misclib/netmain.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/misclib/../nios2/osport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/h/nvparms.h iniche/src/h/libport.h iniche/src/h/nvfsio.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/app_ping.h \
+ iniche/src/h/task.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/misclib/../nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nextcarg.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nextcarg.d
new file mode 100644
index 0000000..7b03895
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nextcarg.d
@@ -0,0 +1,45 @@
+obj/iniche/src/misclib/nextcarg.o: iniche/src/misclib/nextcarg.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nrmenus.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nrmenus.d
new file mode 100644
index 0000000..5e33e05
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nrmenus.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/nrmenus.o: iniche/src/misclib/nrmenus.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvfsio.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvfsio.d
new file mode 100644
index 0000000..0c11648
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvfsio.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/nvfsio.o: iniche/src/misclib/nvfsio.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvparms.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvparms.d
new file mode 100644
index 0000000..395d66a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/nvparms.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/nvparms.o: iniche/src/misclib/nvparms.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/parseip.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/parseip.d
new file mode 100644
index 0000000..023a242
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/parseip.d
@@ -0,0 +1,66 @@
+obj/iniche/src/misclib/parseip.o: iniche/src/misclib/parseip.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/nvparms.h \
+ iniche/src/h/ip.h iniche/src/h/nptcp.h iniche/src/h/socket.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/socket.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/pcycles.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/pcycles.d
new file mode 100644
index 0000000..04c17a1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/pcycles.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/pcycles.o: iniche/src/misclib/pcycles.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/profiler.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/profiler.d
new file mode 100644
index 0000000..20da97c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/profiler.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/profiler.o: iniche/src/misclib/profiler.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rawiptst.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rawiptst.d
new file mode 100644
index 0000000..8e79f65
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rawiptst.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/rawiptst.o: iniche/src/misclib/rawiptst.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/reshost.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/reshost.d
new file mode 100644
index 0000000..5963e6d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/reshost.d
@@ -0,0 +1,57 @@
+obj/iniche/src/misclib/reshost.o: iniche/src/misclib/reshost.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/in_utils.h \
+ iniche/src/h/libport.h iniche/src/h/dns.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/dns.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rfsim.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rfsim.d
new file mode 100644
index 0000000..01613a5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rfsim.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/rfsim.o: iniche/src/misclib/rfsim.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rttest.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rttest.d
new file mode 100644
index 0000000..75ce574
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/rttest.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/rttest.o: iniche/src/misclib/rttest.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/soperr.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/soperr.d
new file mode 100644
index 0000000..a8badb9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/soperr.d
@@ -0,0 +1,73 @@
+obj/iniche/src/misclib/soperr.o: iniche/src/misclib/soperr.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strilib.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strilib.d
new file mode 100644
index 0000000..8d0d101
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strilib.d
@@ -0,0 +1,45 @@
+obj/iniche/src/misclib/strilib.o: iniche/src/misclib/strilib.c \
+ iniche/src/h/in_utils.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/libport.h
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strlib.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strlib.d
new file mode 100644
index 0000000..6539f77
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strlib.d
@@ -0,0 +1,45 @@
+obj/iniche/src/misclib/strlib.o: iniche/src/misclib/strlib.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strtol.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strtol.d
new file mode 100644
index 0000000..365e2fa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/strtol.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/strtol.o: iniche/src/misclib/strtol.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/syslog.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/syslog.d
new file mode 100644
index 0000000..e2fa603
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/syslog.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/syslog.o: iniche/src/misclib/syslog.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/task.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/task.d
new file mode 100644
index 0000000..72827f7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/task.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/task.o: iniche/src/misclib/task.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcp_echo.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcp_echo.d
new file mode 100644
index 0000000..79f9a01
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcp_echo.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/tcp_echo.o: iniche/src/misclib/tcp_echo.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcpcksum.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcpcksum.d
new file mode 100644
index 0000000..9c61afd
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tcpcksum.d
@@ -0,0 +1,78 @@
+obj/iniche/src/misclib/tcpcksum.o: iniche/src/misclib/tcpcksum.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/ip.h iniche/src/h/tcp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/testmenu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/testmenu.d
new file mode 100644
index 0000000..11322aa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/testmenu.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/testmenu.o: iniche/src/misclib/testmenu.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tk_crnos.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tk_crnos.d
new file mode 100644
index 0000000..d00b349
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/tk_crnos.d
@@ -0,0 +1,81 @@
+obj/iniche/src/misclib/tk_crnos.o: iniche/src/misclib/tk_crnos.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/misclib/../nios2/osport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/h/nvparms.h iniche/src/h/libport.h iniche/src/h/nvfsio.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/app_ping.h \
+ iniche/src/h/task.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/misclib/../nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/ttyio.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/ttyio.d
new file mode 100644
index 0000000..51f4a94
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/ttyio.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/ttyio.o: iniche/src/misclib/ttyio.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/udp_echo.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/udp_echo.d
new file mode 100644
index 0000000..d0e9a76
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/udp_echo.d
@@ -0,0 +1,41 @@
+obj/iniche/src/misclib/udp_echo.o: iniche/src/misclib/udp_echo.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/userpass.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/userpass.d
new file mode 100644
index 0000000..aa2b9f0
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/misclib/userpass.d
@@ -0,0 +1,52 @@
+obj/iniche/src/misclib/userpass.o: iniche/src/misclib/userpass.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/userpass.h iniche/src/h/menu.h iniche/src/h/in_utils.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/userpass.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcpclnt.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcpclnt.d
new file mode 100644
index 0000000..feb1ede
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcpclnt.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/dhcpclnt.o: iniche/src/net/dhcpclnt.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcputil.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcputil.d
new file mode 100644
index 0000000..d943e38
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dhcputil.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/dhcputil.o: iniche/src/net/dhcputil.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dnsclnt.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dnsclnt.d
new file mode 100644
index 0000000..b65b0ec
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/dnsclnt.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/dnsclnt.o: iniche/src/net/dnsclnt.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ifmap.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ifmap.d
new file mode 100644
index 0000000..dfbc449
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ifmap.d
@@ -0,0 +1,57 @@
+obj/iniche/src/net/ifmap.o: iniche/src/net/ifmap.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/ifmap.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/ifmap.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/macloop.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/macloop.d
new file mode 100644
index 0000000..7e3c5ef
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/macloop.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/macloop.o: iniche/src/net/macloop.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ping.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ping.d
new file mode 100644
index 0000000..ee8c202
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/ping.d
@@ -0,0 +1,57 @@
+obj/iniche/src/net/ping.o: iniche/src/net/ping.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/pktalloc.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/pktalloc.d
new file mode 100644
index 0000000..683be44
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/pktalloc.d
@@ -0,0 +1,55 @@
+obj/iniche/src/net/pktalloc.o: iniche/src/net/pktalloc.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/q.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/q.d
new file mode 100644
index 0000000..461ccb2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/q.d
@@ -0,0 +1,43 @@
+obj/iniche/src/net/q.o: iniche/src/net/q.c iniche/src/h/nios2/ipport.h \
+ system.h linker.h iniche/src/h/nptypes.h HAL/inc/includes.h \
+ HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \
+ HAL/inc/alt_types.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h \
+ HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h iniche/src/h/libport.h \
+ iniche/src/h/q.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slip.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slip.d
new file mode 100644
index 0000000..1b86159
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slip.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/slip.o: iniche/src/net/slip.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slipif.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slipif.d
new file mode 100644
index 0000000..5f5125b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/slipif.d
@@ -0,0 +1,41 @@
+obj/iniche/src/net/slipif.o: iniche/src/net/slipif.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/udp_open.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/udp_open.d
new file mode 100644
index 0000000..cf7c97c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/net/udp_open.d
@@ -0,0 +1,57 @@
+obj/iniche/src/net/udp_open.o: iniche/src/net/udp_open.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/udp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/udp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/asm_cksum.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/asm_cksum.d
new file mode 100644
index 0000000..d6584ef
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/asm_cksum.d
@@ -0,0 +1 @@
+obj/iniche/src/nios2/asm_cksum.o: iniche/src/nios2/asm_cksum.S
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/brdutils.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/brdutils.d
new file mode 100644
index 0000000..9cef2aa
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/brdutils.d
@@ -0,0 +1,43 @@
+obj/iniche/src/nios2/brdutils.o: iniche/src/nios2/brdutils.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h HAL/inc/sys/alt_irq.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+HAL/inc/sys/alt_irq.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/osportco.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/osportco.d
new file mode 100644
index 0000000..1a3bdd7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/osportco.d
@@ -0,0 +1,85 @@
+obj/iniche/src/nios2/osportco.o: iniche/src/nios2/osportco.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/nios2/osport.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/q.h \
+ iniche/src/h/profiler.h iniche/src/h/arp.h iniche/src/h/ip.h \
+ iniche/src/h/icmp.h iniche/src/h/udp.h iniche/src/h/nvparms.h \
+ iniche/src/h/libport.h iniche/src/h/nvfsio.h iniche/src/h/menu.h \
+ iniche/src/h/in_utils.h iniche/src/h/app_ping.h iniche/src/h/task.h \
+ iniche/src/h/in_utils.h iniche/src/h/memwrap.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/memwrap.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/targnios.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/targnios.d
new file mode 100644
index 0000000..1153793
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/nios2/targnios.d
@@ -0,0 +1,122 @@
+obj/iniche/src/nios2/targnios.o: iniche/src/nios2/targnios.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/h/memwrap.h iniche/src/h/vfsfiles.h iniche/src/nios2/osport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/q.h iniche/src/h/profiler.h iniche/src/h/arp.h \
+ iniche/src/h/ip.h iniche/src/h/icmp.h iniche/src/h/udp.h \
+ iniche/src/h/nvparms.h iniche/src/h/nvfsio.h iniche/src/h/menu.h \
+ iniche/src/h/in_utils.h iniche/src/h/app_ping.h iniche/src/h/task.h \
+ iniche/inc/alt_iniche_dev.h iniche/src/h/tcpport.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_cache.h iniche/src/h/ether.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/memwrap.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/nios2/osport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/arp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/nvfsio.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/app_ping.h:
+
+iniche/src/h/task.h:
+
+iniche/inc/alt_iniche_dev.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/sys/alt_cache.h:
+
+iniche/src/h/ether.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/in_pcb.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/in_pcb.d
new file mode 100644
index 0000000..2019470
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/in_pcb.d
@@ -0,0 +1,78 @@
+obj/iniche/src/tcp/in_pcb.o: iniche/src/tcp/in_pcb.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/nptcp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/nptcp.d
new file mode 100644
index 0000000..16a0f0d
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/nptcp.d
@@ -0,0 +1,100 @@
+obj/iniche/src/tcp/nptcp.o: iniche/src/tcp/nptcp.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/in_pcb.h iniche/src/h/ip.h iniche/src/h/icmp.h \
+ iniche/src/h/udp.h iniche/src/tcp/protosw.h iniche/src/h/tcp.h \
+ iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/icmp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/rawsock.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/rawsock.d
new file mode 100644
index 0000000..d76e9b4
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/rawsock.d
@@ -0,0 +1,87 @@
+obj/iniche/src/tcp/rawsock.o: iniche/src/tcp/rawsock.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/tcp/protosw.h iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/sockcall.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/sockcall.d
new file mode 100644
index 0000000..13146be
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/sockcall.d
@@ -0,0 +1,90 @@
+obj/iniche/src/tcp/sockcall.o: iniche/src/tcp/sockcall.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h iniche/src/h/tcp.h \
+ iniche/src/h/udp.h iniche/src/h/ip.h iniche/src/tcp/tcp_timr.h \
+ iniche/src/tcp/tcp_var.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/h/udp.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket.d
new file mode 100644
index 0000000..a8a0b34
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket.d
@@ -0,0 +1,92 @@
+obj/iniche/src/tcp/socket.o: iniche/src/tcp/socket.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h iniche/src/h/ip.h \
+ iniche/src/h/tcp.h iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket2.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket2.d
new file mode 100644
index 0000000..d0a4ca6
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/socket2.d
@@ -0,0 +1,76 @@
+obj/iniche/src/tcp/socket2.o: iniche/src/tcp/socket2.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/soselect.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/soselect.d
new file mode 100644
index 0000000..e15c45a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/soselect.d
@@ -0,0 +1,78 @@
+obj/iniche/src/tcp/soselect.o: iniche/src/tcp/soselect.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_in.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_in.d
new file mode 100644
index 0000000..9ca707f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_in.d
@@ -0,0 +1,93 @@
+obj/iniche/src/tcp/tcp_in.o: iniche/src/tcp/tcp_in.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/in_pcb.h iniche/src/h/ip.h iniche/src/h/tcp.h \
+ iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_menu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_menu.d
new file mode 100644
index 0000000..96656ea
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_menu.d
@@ -0,0 +1,41 @@
+obj/iniche/src/tcp/tcp_menu.o: iniche/src/tcp/tcp_menu.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_out.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_out.d
new file mode 100644
index 0000000..115d916
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_out.d
@@ -0,0 +1,95 @@
+obj/iniche/src/tcp/tcp_out.o: iniche/src/tcp/tcp_out.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/in_pcb.h iniche/src/h/ip.h iniche/src/h/pmtu.h \
+ iniche/src/h/tcp.h iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/pmtu.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_subr.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_subr.d
new file mode 100644
index 0000000..926b9b2
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_subr.d
@@ -0,0 +1,95 @@
+obj/iniche/src/tcp/tcp_subr.o: iniche/src/tcp/tcp_subr.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h iniche/src/h/ip.h \
+ iniche/src/h/tcp.h iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_timr.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_timr.d
new file mode 100644
index 0000000..186b496
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_timr.d
@@ -0,0 +1,95 @@
+obj/iniche/src/tcp/tcp_timr.o: iniche/src/tcp/tcp_timr.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h iniche/src/h/ip.h \
+ iniche/src/h/tcp.h iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_usr.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_usr.d
new file mode 100644
index 0000000..1396054
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_usr.d
@@ -0,0 +1,95 @@
+obj/iniche/src/tcp/tcp_usr.o: iniche/src/tcp/tcp_usr.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/protosw.h iniche/src/tcp/in_pcb.h iniche/src/h/ip.h \
+ iniche/src/h/tcp.h iniche/src/tcp/tcp_fsm.h iniche/src/tcp/tcp_seq.h \
+ iniche/src/tcp/tcp_timr.h iniche/src/tcp/tcp_var.h \
+ iniche/src/tcp/tcpip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/tcp.h:
+
+iniche/src/tcp/tcp_fsm.h:
+
+iniche/src/tcp/tcp_seq.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/tcp/tcp_var.h:
+
+iniche/src/tcp/tcpip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_zio.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_zio.d
new file mode 100644
index 0000000..6043ffc
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcp_zio.d
@@ -0,0 +1,41 @@
+obj/iniche/src/tcp/tcp_zio.o: iniche/src/tcp/tcp_zio.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpport.d
new file mode 100644
index 0000000..01a7cbf
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpport.d
@@ -0,0 +1,80 @@
+obj/iniche/src/tcp/tcpport.o: iniche/src/tcp/tcpport.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/tcp/in_pcb.h iniche/src/tcp/tcp_timr.h iniche/src/h/ip.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/tcp/in_pcb.h:
+
+iniche/src/tcp/tcp_timr.h:
+
+iniche/src/h/ip.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpsack.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpsack.d
new file mode 100644
index 0000000..14a1bee
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/tcpsack.d
@@ -0,0 +1,73 @@
+obj/iniche/src/tcp/tcpsack.o: iniche/src/tcp/tcpsack.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/udpsock.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/udpsock.d
new file mode 100644
index 0000000..4da389c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tcp/udpsock.d
@@ -0,0 +1,87 @@
+obj/iniche/src/tcp/udpsock.o: iniche/src/tcp/udpsock.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpport.h iniche/src/h/libport.h \
+ iniche/src/h/q.h iniche/src/h/netbuf.h iniche/src/h/net.h \
+ iniche/src/h/profiler.h iniche/src/h/ip.h iniche/src/h/nptcp.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/h/bsdsock.h iniche/src/h/tcpport.h \
+ iniche/src/h/mbuf.h iniche/src/h/socket.h iniche/src/h/sockvar.h \
+ iniche/src/h/sockcall.h iniche/src/tcp/protosw.h iniche/src/h/udp.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/tcp/protosw.h:
+
+iniche/src/h/udp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telerr.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telerr.d
new file mode 100644
index 0000000..89e275b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telerr.d
@@ -0,0 +1,88 @@
+obj/iniche/src/telnet/telerr.o: iniche/src/telnet/telerr.c \
+ iniche/src/telnet/telnet.h iniche/src/telnet/telport.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/nvparms.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/userpass.h
+
+iniche/src/telnet/telnet.h:
+
+iniche/src/telnet/telport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telmenu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telmenu.d
new file mode 100644
index 0000000..8e3a23e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telmenu.d
@@ -0,0 +1,88 @@
+obj/iniche/src/telnet/telmenu.o: iniche/src/telnet/telmenu.c \
+ iniche/src/telnet/telnet.h iniche/src/telnet/telport.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/nvparms.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/userpass.h
+
+iniche/src/telnet/telnet.h:
+
+iniche/src/telnet/telport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telnet.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telnet.d
new file mode 100644
index 0000000..b3dd6e9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telnet.d
@@ -0,0 +1,88 @@
+obj/iniche/src/telnet/telnet.o: iniche/src/telnet/telnet.c \
+ iniche/src/telnet/telnet.h iniche/src/telnet/telport.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/nvparms.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/userpass.h
+
+iniche/src/telnet/telnet.h:
+
+iniche/src/telnet/telport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telparse.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telparse.d
new file mode 100644
index 0000000..d771f0e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telparse.d
@@ -0,0 +1,88 @@
+obj/iniche/src/telnet/telparse.o: iniche/src/telnet/telparse.c \
+ iniche/src/telnet/telnet.h iniche/src/telnet/telport.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/nvparms.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/userpass.h
+
+iniche/src/telnet/telnet.h:
+
+iniche/src/telnet/telport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telport.d
new file mode 100644
index 0000000..a79c7f1
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/telnet/telport.d
@@ -0,0 +1,88 @@
+obj/iniche/src/telnet/telport.o: iniche/src/telnet/telport.c \
+ iniche/src/telnet/telnet.h iniche/src/telnet/telport.h \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/tcpapp.h iniche/src/h/q.h \
+ iniche/src/h/netbuf.h iniche/src/h/net.h iniche/src/h/profiler.h \
+ iniche/src/h/tcpport.h iniche/src/h/libport.h iniche/src/h/ip.h \
+ iniche/src/h/nptcp.h iniche/src/h/mbuf.h iniche/src/h/socket.h \
+ iniche/src/h/sockvar.h iniche/src/h/sockcall.h iniche/src/h/bsdsock.h \
+ iniche/src/h/nvparms.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/userpass.h
+
+iniche/src/telnet/telnet.h:
+
+iniche/src/telnet/telport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/tcpapp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/tcpport.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/nptcp.h:
+
+iniche/src/h/mbuf.h:
+
+iniche/src/h/socket.h:
+
+iniche/src/h/sockvar.h:
+
+iniche/src/h/sockcall.h:
+
+iniche/src/h/bsdsock.h:
+
+iniche/src/h/nvparms.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/userpass.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpcli.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpcli.d
new file mode 100644
index 0000000..2cb6e0b
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpcli.d
@@ -0,0 +1,45 @@
+obj/iniche/src/tftp/tftpcli.o: iniche/src/tftp/tftpcli.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpmenu.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpmenu.d
new file mode 100644
index 0000000..e2b2211
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpmenu.d
@@ -0,0 +1,69 @@
+obj/iniche/src/tftp/tftpmenu.o: iniche/src/tftp/tftpmenu.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h \
+ iniche/src/tftp/tftp.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/libport.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/tftp/tftp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpport.d
new file mode 100644
index 0000000..45d6ca7
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpport.d
@@ -0,0 +1,69 @@
+obj/iniche/src/tftp/tftpport.o: iniche/src/tftp/tftpport.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h \
+ iniche/src/tftp/tftp.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/menu.h iniche/src/h/in_utils.h \
+ iniche/src/h/libport.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/tftp/tftp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpsrv.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpsrv.d
new file mode 100644
index 0000000..063007f
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpsrv.d
@@ -0,0 +1,45 @@
+obj/iniche/src/tftp/tftpsrv.o: iniche/src/tftp/tftpsrv.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpudp.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpudp.d
new file mode 100644
index 0000000..c82c546
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftpudp.d
@@ -0,0 +1,64 @@
+obj/iniche/src/tftp/tftpudp.o: iniche/src/tftp/tftpudp.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h \
+ iniche/src/tftp/tftp.h iniche/src/h/q.h iniche/src/h/netbuf.h \
+ iniche/src/h/net.h iniche/src/h/q.h iniche/src/h/profiler.h \
+ iniche/src/h/ip.h iniche/src/h/udp.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/tftp/tftp.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/netbuf.h:
+
+iniche/src/h/net.h:
+
+iniche/src/h/q.h:
+
+iniche/src/h/profiler.h:
+
+iniche/src/h/ip.h:
+
+iniche/src/h/udp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftputil.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftputil.d
new file mode 100644
index 0000000..6e55df5
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/tftp/tftputil.d
@@ -0,0 +1,48 @@
+obj/iniche/src/tftp/tftputil.o: iniche/src/tftp/tftputil.c \
+ iniche/src/tftp/tftpport.h iniche/src/h/nios2/ipport.h system.h linker.h \
+ iniche/src/h/nptypes.h HAL/inc/includes.h HAL/inc/os_cpu.h \
+ HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \
+ UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \
+ HAL/inc/priv/alt_alarm.h UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h \
+ iniche/src/h/tk_crnos.h iniche/src/h/libport.h iniche/src/h/vfsfiles.h \
+ iniche/src/tftp/tftp.h
+
+iniche/src/tftp/tftpport.h:
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/tftp/tftp.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsfiles.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsfiles.d
new file mode 100644
index 0000000..85c4fe9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsfiles.d
@@ -0,0 +1,48 @@
+obj/iniche/src/vfs/vfsfiles.o: iniche/src/vfs/vfsfiles.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/vfs/vfsport.h iniche/src/h/vfsfiles.h \
+ iniche/src/h/profiler.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/vfs/vfsport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/h/profiler.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsport.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsport.d
new file mode 100644
index 0000000..09717ae
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsport.d
@@ -0,0 +1,50 @@
+obj/iniche/src/vfs/vfsport.o: iniche/src/vfs/vfsport.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/in_utils.h iniche/src/h/libport.h \
+ iniche/src/vfs/vfsport.h iniche/src/h/vfsfiles.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/vfs/vfsport.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfssync.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfssync.d
new file mode 100644
index 0000000..23f100e
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfssync.d
@@ -0,0 +1,43 @@
+obj/iniche/src/vfs/vfssync.o: iniche/src/vfs/vfssync.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/h/vfsfiles.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/h/vfsfiles.h:
diff --git a/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsutil.d b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsutil.d
new file mode 100644
index 0000000..3a2d1b9
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/obj/iniche/src/vfs/vfsutil.d
@@ -0,0 +1,52 @@
+obj/iniche/src/vfs/vfsutil.o: iniche/src/vfs/vfsutil.c \
+ iniche/src/h/nios2/ipport.h system.h linker.h iniche/src/h/nptypes.h \
+ HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \
+ HAL/inc/nios2.h HAL/inc/alt_types.h UCOSII/inc/os_cfg.h \
+ HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \
+ UCOSII/inc/ucos_ii.h HAL/inc/os_cpu.h iniche/src/h/tk_crnos.h \
+ iniche/src/h/libport.h iniche/src/vfs/vfsport.h iniche/src/h/vfsfiles.h \
+ iniche/src/h/menu.h iniche/src/h/in_utils.h iniche/src/h/libport.h
+
+iniche/src/h/nios2/ipport.h:
+
+system.h:
+
+linker.h:
+
+iniche/src/h/nptypes.h:
+
+HAL/inc/includes.h:
+
+HAL/inc/os_cpu.h:
+
+HAL/inc/sys/alt_irq.h:
+
+HAL/inc/nios2.h:
+
+HAL/inc/alt_types.h:
+
+UCOSII/inc/os_cfg.h:
+
+HAL/inc/sys/alt_alarm.h:
+
+HAL/inc/sys/alt_llist.h:
+
+HAL/inc/priv/alt_alarm.h:
+
+UCOSII/inc/ucos_ii.h:
+
+HAL/inc/os_cpu.h:
+
+iniche/src/h/tk_crnos.h:
+
+iniche/src/h/libport.h:
+
+iniche/src/vfs/vfsport.h:
+
+iniche/src/h/vfsfiles.h:
+
+iniche/src/h/menu.h:
+
+iniche/src/h/in_utils.h:
+
+iniche/src/h/libport.h:
diff --git a/FPGA_nios/hit_pat_bsp/public.mk b/FPGA_nios/hit_pat_bsp/public.mk
new file mode 100644
index 0000000..0a9de2a
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/public.mk
@@ -0,0 +1,443 @@
+#------------------------------------------------------------------------------
+#                       BSP "PUBLIC" MAKEFILE CONTENT
+#
+# This file is intended to be included in an application or library
+# Makefile that is using this BSP. You can create such a Makefile with
+# the nios2-app-generate-makefile or nios2-lib-generate-makefile
+# commands.
+#
+# The following variables must be defined before including this file:
+#
+#     ALT_LIBRARY_ROOT_DIR
+#         Contains the path to the BSP top-level (aka root) directory
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+#                                  PATHS
+#------------------------------------------------------------------------------
+
+
+
+# Path to the provided linker script.
+BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x
+
+# Include paths:
+# The path to root of all header files that a library wishes to make
+# available for an application's use is specified here. Note that this
+# may not be *all* folders within a hierarchy. For example, if it is
+# desired that the application developer type:
+#   #include <sockets.h>
+#   #include <ip/tcpip.h>
+# With files laid out like this:
+#   <root of library>/inc/sockets.h
+#   <root of library>/inc/ip/tcpip.h
+#
+# Then, only <root of library>/inc need be added to the list of include
+# directories. Alternatively, if you wish to be able to directly include
+# all files in a hierarchy, separate paths to each folder in that
+# hierarchy must be defined.
+
+# The following are the "base" set of include paths for a BSP.
+# These paths are appended to the list that individual software
+# components, drivers, etc., add in the generated portion of this
+# file (below).
+ALT_INCLUDE_DIRS_TO_APPEND += \
+        $(ALT_LIBRARY_ROOT_DIR) \
+        $(ALT_LIBRARY_ROOT_DIR)/drivers/inc
+
+# Additions to linker library search-path:
+# Here we provide a path to "our self" for the application to construct a
+# "-L <path to BSP>" out of. This should contain a list of directories,
+# relative to the library root, of all directories with .a files to link
+# against.
+ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR)
+
+
+#------------------------------------------------------------------------------
+#                               COMPILATION FLAGS
+#------------------------------------------------------------------------------
+# Default C pre-processor flags for a BSP:
+ALT_CPPFLAGS += -pipe
+
+
+#------------------------------------------------------------------------------
+#                              MANAGED CONTENT
+#
+# All content between the lines "START MANAGED" and "END MANAGED" below is
+# generated based on variables in the BSP settings file when the
+# nios2-bsp-generate-files command is invoked. If you wish to persist any
+# information pertaining to the build process, it is recomended that you
+# utilize the BSP settings mechanism to do so.
+#------------------------------------------------------------------------------
+#START MANAGED
+
+# The following TYPE comment allows tools to identify the 'type' of target this 
+# makefile is associated with. 
+# TYPE: BSP_PUBLIC_MAKEFILE
+
+# This following VERSION comment indicates the version of the tool used to 
+# generate this makefile. A makefile variable is provided for VERSION as well. 
+# ACDS_VERSION: 19.1
+ACDS_VERSION := 19.1
+
+# This following BUILD_NUMBER comment indicates the build number of the tool 
+# used to generate this makefile. 
+# BUILD_NUMBER: 670
+
+# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with 
+# design component names. 
+SOPCINFO_FILE := D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+
+# Big-Endian operation. 
+# setting BIG_ENDIAN is false
+
+
+# BMX present. 
+# setting BMX is false
+
+# Path to the provided C language runtime initialization code. 
+BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o
+
+# Name of BSP library as provided to linker using the "-msys-lib" flag or 
+# linker script GROUP command. 
+# setting BSP_SYS_LIB is ucosii_bsp
+BSP_SYS_LIB := ucosii_bsp
+ELF_PATCH_FLAG  += --thread_model ucosii
+
+# Type identifier of the BSP library 
+# setting BSP_TYPE is ucosii
+ALT_CPPFLAGS += -D__hal__
+BSP_TYPE := ucosii
+
+# CDX present. 
+# setting CDX is false
+
+# CPU Name 
+# setting CPU_NAME is cpu
+CPU_NAME = cpu
+ELF_PATCH_FLAG  += --cpu_name $(CPU_NAME)
+
+# Hardware Divider present. 
+# setting HARDWARE_DIVIDE is false
+ALT_CFLAGS += -mno-hw-div
+
+# Hardware Multiplier present. 
+# setting HARDWARE_MULTIPLY is true
+ALT_CFLAGS += -mhw-mul
+
+# Hardware Mulx present. 
+# setting HARDWARE_MULX is false
+ALT_CFLAGS += -mno-hw-mulx
+
+# Debug Core present. 
+# setting HAS_DEBUG_CORE is true
+CPU_HAS_DEBUG_CORE = 1
+
+# Qsys generated design 
+# setting QSYS is 1
+QSYS := 1
+ELF_PATCH_FLAG += --qsys true
+
+# Design Name 
+# setting SOPC_NAME is q_sys
+SOPC_NAME := q_sys
+
+# SopcBuilder Simulation Enabled 
+# setting SOPC_SIMULATION_ENABLED is false
+ELF_PATCH_FLAG  += --simulation_enabled false
+
+# The SOPC System ID 
+# setting SOPC_SYSID is 4207856382
+SOPC_SYSID_FLAG += --id=4207856382
+ELF_PATCH_FLAG  += --id 4207856382
+
+# The SOPC System ID Base Address 
+# setting SOPC_SYSID_BASE_ADDRESS is 0x18403d68
+SOPC_SYSID_FLAG += --sidp=0x18403d68
+ELF_PATCH_FLAG  += --sidp 0x18403d68
+
+# The SOPC Timestamp 
+# setting SOPC_TIMESTAMP is 1728634208
+SOPC_SYSID_FLAG += --timestamp=1728634208
+ELF_PATCH_FLAG  += --timestamp 1728634208
+
+# Enable driver ioctl() support. This feature is not compatible with the 
+# 'small' driver; ioctl() support will not be compiled if either the UART 
+# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are 
+# enabled. none 
+# setting altera_avalon_uart_driver.enable_ioctl is false
+
+# Small-footprint (polled mode) driver none 
+# setting altera_avalon_uart_driver.enable_small_driver is false
+
+# Auto Negotiation Timeout in milliseconds none 
+# setting altera_eth_tse_driver_ucosii_iniche.autoneg_timeout is 2500
+
+# CheckLink Timeout in milliseconds none 
+# setting altera_eth_tse_driver_ucosii_iniche.checklink_timeout is 10000
+
+# "No MDIO" Timeout in microseconds none 
+# setting altera_eth_tse_driver_ucosii_iniche.nomdio_timeout is 1000000
+
+# Build a custom version of newlib with the specified space-separated compiler 
+# flags. The custom newlib build will be placed in the <bsp root>/newlib 
+# directory, and will be used only for applications that utilize this BSP. 
+# setting hal.custom_newlib_flags is none
+
+# Enable support for a subset of the C++ language. This option increases code 
+# footprint by adding support for C++ constructors. Certain features, such as 
+# multiple inheritance and exceptions are not supported. If false, adds 
+# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code 
+# footprint. none 
+# setting hal.enable_c_plus_plus is true
+
+# When your application exits, close file descriptors, call C++ destructors, 
+# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds 
+# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk. none 
+# setting hal.enable_clean_exit is true
+
+# Add exit() support. This option increases code footprint if your "main()" 
+# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to 
+# ALT_CPPFLAGS in public.mk, and reduces footprint none 
+# setting hal.enable_exit is true
+
+# Causes code to be compiled with gprof profiling enabled and the application 
+# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to 
+# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none 
+# setting hal.enable_gprof is false
+
+# Enables lightweight device driver API. This reduces code and data footprint 
+# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file 
+# descriptors. Instead, driver routines are called directly. The open(), 
+# close(), and lseek() routines will always fail if called. The read(), 
+# write(), fstat(), ioctl(), and isatty() routines only work for the stdio 
+# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. 
+# The Altera Host and read-only ZIP file systems can't be used if 
+# hal.enable_lightweight_device_driver_api is true. 
+# setting hal.enable_lightweight_device_driver_api is false
+
+# Adds code to emulate multiply and divide instructions in case they are 
+# executed but aren't present in the CPU. Normally this isn't required because 
+# the compiler won't use multiply and divide instructions that aren't present 
+# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in 
+# public.mk. none 
+# setting hal.enable_mul_div_emulation is false
+ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION
+
+# Certain drivers are compiled with reduced functionality to reduce code 
+# footprint. Not all drivers observe this setting. The altera_avalon_uart and 
+# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled 
+# operation. CAUTION: Several device drivers are disabled entirely. These 
+# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and 
+# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash 
+# access routines) to fail. You can define a symbol provided by each driver to 
+# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to 
+# ALT_CPPFLAGS in public.mk. none 
+# setting hal.enable_reduced_device_drivers is false
+
+# Turns on HAL runtime stack checking feature. Enabling this setting causes 
+# additional code to be placed into each subroutine call to generate an 
+# exception if a stack collision occurs with the heap or statically allocated 
+# data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to 
+# ALT_CPPFLAGS in public.mk. none 
+# setting hal.enable_runtime_stack_checking is false
+
+# The BSP is compiled with optimizations to speedup HDL simulation such as 
+# initializing the cache, clearing the .bss section, and skipping long delay 
+# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When 
+# this setting is true, the BSP shouldn't be used to build applications that 
+# are expected to run real hardware. 
+# setting hal.enable_sim_optimize is false
+
+# Causes the small newlib (C library) to be used. This reduces code and data 
+# footprint at the expense of reduced functionality. Several newlib features 
+# are removed such as floating-point support in printf(), stdin input routines, 
+# and buffered I/O. The small C library is not compatible with Micrium 
+# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none 
+# setting hal.enable_small_c_library is false
+
+# Enable SOPC Builder System ID. If a System ID SOPC Builder component is 
+# connected to the CPU associated with this BSP, it will be enabled in the 
+# creation of command-line arguments to download an ELF to the target. 
+# Otherwise, system ID and timestamp values are left out of public.mk for 
+# application Makefile "download-elf" target definition. With the system ID 
+# check disabled, the Nios II EDS tools will not automatically ensure that the 
+# application .elf file (and BSP it is linked against) corresponds to the 
+# hardware design on the target. If false, adds --accept-bad-sysid to 
+# SOPC_SYSID_FLAG in public.mk. none 
+# setting hal.enable_sopc_sysid_check is true
+
+# C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' 
+# tells the compilter not to generate GP-relative accesses. 'local' will 
+# generate GP-relative accesses for small data objects that are not external, 
+# weak, or uninitialized common symbols. Also use GP-relative addressing for 
+# objects that have been explicitly placed in a small data section via a 
+# section attribute. provides the default set of debug symbols typically 
+# required to debug a typical application. 'global' is same as 'local' but also 
+# generate GP-relative accesses for small data objects that are external, weak, 
+# or common. none 
+# setting hal.make.cflags_mgpopt is -mgpopt=global
+ALT_CFLAGS += -mgpopt=global
+
+# Enable BSP generation to query if SOPC system is big endian. If true ignores 
+# export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none 
+# setting hal.make.ignore_system_derived.big_endian is false
+
+# If true, prevents GCC from using BMX instructions. If false, GCC uses BMX 
+# instructions if present in the CPU. none 
+# setting hal.make.ignore_system_derived.bmx_present is false
+
+# If true, prevents GCC from using CDX instructions. If false, GCC uses CDX 
+# instructions if present in the CPU. none 
+# setting hal.make.ignore_system_derived.cdx_present is false
+
+# Enable BSP generation to query if SOPC system has a debug core present. If 
+# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core 
+# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if 
+# no debug core is found in the system. none 
+# setting hal.make.ignore_system_derived.debug_core_present is false
+
+# Enable BSP generation to query if SOPC system has FPU present. If true 
+# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found 
+# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU 
+# is not found in the system. none 
+# setting hal.make.ignore_system_derived.fpu_present is false
+
+# Enable BSP generation to query if SOPC system has hardware divide present. If 
+# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no 
+# division is found in system. If true ignores export of 'ALT_CFLAGS += 
+# -mhw-div' if division is found in the system. none 
+# setting hal.make.ignore_system_derived.hardware_divide_present is false
+
+# Enable BSP generation to query if SOPC system floating point custom 
+# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS 
+# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to 
+# public.mk if the custom instruction is found in the system. none 
+# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false
+
+# Enable BSP generation to query if SOPC system floating point custom 
+# instruction without a divider is present. If true ignores export of 
+# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += 
+# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the 
+# system. none 
+# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false
+
+# Enable BSP generation to query if SOPC system has multiplier present. If true 
+# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier 
+# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if 
+# multiplier is found in the system. none 
+# setting hal.make.ignore_system_derived.hardware_multiplier_present is false
+
+# Enable BSP generation to query if SOPC system has hardware mulx present. If 
+# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx 
+# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' 
+# if mulx is found in the system. none 
+# setting hal.make.ignore_system_derived.hardware_mulx_present is false
+
+# Enable BSP generation to query if SOPC system has simulation enabled. If true 
+# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none 
+# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false
+
+# Enable BSP generation to query SOPC system for system ID base address. If 
+# true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 
+# 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. none 
+# setting hal.make.ignore_system_derived.sopc_system_base_address is false
+
+# Enable BSP generation to query SOPC system for system ID. If true ignores 
+# export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += 
+# --id=<sysid>' to public.mk. none 
+# setting hal.make.ignore_system_derived.sopc_system_id is false
+
+# Enable BSP generation to query SOPC system for system timestamp. If true 
+# ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 
+# 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. none 
+# setting hal.make.ignore_system_derived.sopc_system_timestamp is false
+
+# Slave descriptor of STDERR character-mode device. This setting is used by the 
+# ALT_STDERR family of defines in system.h. none 
+# setting hal.stderr is debug_uart
+ELF_PATCH_FLAG  += --stderr_dev debug_uart
+
+# Slave descriptor of STDIN character-mode device. This setting is used by the 
+# ALT_STDIN family of defines in system.h. none 
+# setting hal.stdin is debug_uart
+ELF_PATCH_FLAG  += --stdin_dev debug_uart
+
+# Slave descriptor of STDOUT character-mode device. This setting is used by the 
+# ALT_STDOUT family of defines in system.h. none 
+# setting hal.stdout is debug_uart
+ELF_PATCH_FLAG  += --stdout_dev debug_uart
+
+
+#------------------------------------------------------------------------------
+#                 SOFTWARE COMPONENT & DRIVER INCLUDE PATHS
+#------------------------------------------------------------------------------
+
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/drivers/inc
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/drivers/inc/iniche
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/iniche/inc
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/iniche/src/h
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/iniche/src/h/nios2
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/iniche/src/nios2
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc
+ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc
+
+#------------------------------------------------------------------------------
+#        SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS
+#------------------------------------------------------------------------------
+
+ALT_CPPFLAGS += -DALTERA_TRIPLE_SPEED_MAC
+ALT_CPPFLAGS += -DALT_INICHE
+ALT_CPPFLAGS += -D__ucosii__
+
+#------------------------------------------------------------------------------
+#        SOFTWARE COMPONENT & DRIVER SETTING-PRODUCED DEFINITIONS
+#------------------------------------------------------------------------------
+
+ALT_CPPFLAGS += -DALTERA_AUTONEG_TIMEOUT_THRESHOLD=2500
+ALT_CPPFLAGS += -DALTERA_CHECKLINK_TIMEOUT_THRESHOLD=10000
+ALT_CPPFLAGS += -DALTERA_NOMDIO_TIMEOUT_THRESHOLD=1000000
+
+#END MANAGED
+
+
+#------------------------------------------------------------------------------
+#                             LIBRARY INFORMATION
+#------------------------------------------------------------------------------
+# Assemble the name of the BSP *.a file using the BSP library name
+# (BSP_SYS_LIB) in generated content above.
+BSP_LIB := lib$(BSP_SYS_LIB).a
+
+# Additional libraries to link against:
+# An application including this file will prefix each library with "-l".
+# For example, to include the Newlib math library "m" is included, which
+# becomes "-lm" when linking the application.
+ALT_LIBRARY_NAMES += m
+
+# Additions to linker dependencies:
+# An application Makefile will typically add these directly to the list 
+# of dependencies required to build the executable target(s). The BSP
+# library (*.a) file is specified here.
+ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB)
+
+# Is this library "Makeable"?
+# Add to list of root library directories that support running 'make'
+# to build them. Because libraries may or may not have a Makefile in their
+# root, appending to this variable tells an application to run 'make' in
+# the library root to build/update this library.
+MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR)
+
+# Additional Assembler Flags
+# -gdwarf2 flag is required for stepping through assembly code
+ALT_ASFLAGS += -gdwarf2
+
+#------------------------------------------------------------------------------
+#                       FINAL INCLUDE PATH LIST
+#------------------------------------------------------------------------------
+# Append static include paths to paths specified by OS/driver/sw package 
+# additions to the BSP thus giving them precedence in case a BSP addition
+# is attempting to override BSP sources.
+ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND)
+
+
+
diff --git a/FPGA_nios/hit_pat_bsp/settings.bsp b/FPGA_nios/hit_pat_bsp/settings.bsp
new file mode 100644
index 0000000..2ba743c
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/settings.bsp
@@ -0,0 +1,2001 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
+        <BspType>ucosii</BspType>
+        <BspVersion>default</BspVersion>
+        <BspGeneratedTimeStamp>11-Oct-2024 10:12:19</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1728634339674</BspGeneratedUnixTimeStamp>
+        <BspGeneratedLocation>D:\hit20v3\software\hit_pat\software\hit_pat_bsp</BspGeneratedLocation>
+        <BspSettingsFile>settings.bsp</BspSettingsFile>
+        <SopcDesignFile>D:\hit20v3\software\hit_pat\q_sys.sopcinfo</SopcDesignFile>
+        <JdiFile>default</JdiFile>
+        <Cpu>cpu</Cpu>
+        <SchemaVersion>1.9</SchemaVersion>
+        <Setting>
+                <SettingName>hal.sys_clk_timer</SettingName>
+                <Identifier>ALT_SYS_CLK</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>sys_clk_timer</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.timestamp_timer</SettingName>
+                <Identifier>ALT_TIMESTAMP_CLK</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.max_file_descriptors</SettingName>
+                <Identifier>ALT_MAX_FD</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>16</Value>
+                <DefaultValue>32</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.</Description>
+                <Restrictions>If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_instruction_related_exceptions_api</SettingName>
+                <Identifier>ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>true</Value>
+                <DefaultValue>false</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.</Description>
+                <Restrictions>These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.allow_code_at_reset</SettingName>
+                <Identifier>ALT_ALLOW_CODE_AT_RESET</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.</Description>
+                <Restrictions>If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_alt_load</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</Description>
+                <Restrictions>This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_alt_load_copy_rodata</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_alt_load_copy_rwdata</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_alt_load_copy_exceptions</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_exception_stack</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.</Description>
+                <Restrictions>The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.exception_stack_size</SettingName>
+                <Identifier>none</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>1024</Value>
+                <DefaultValue>1024</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Size of the exception stack in bytes.</Description>
+                <Restrictions>Only used if hal.linker.enable_exception_stack is true.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.exception_stack_memory_region_name</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>ddr3_ram</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.</Description>
+                <Restrictions>Only used if hal.linker.enable_exception_stack is true.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.enable_interrupt_stack</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.</Description>
+                <Restrictions>The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.interrupt_stack_size</SettingName>
+                <Identifier>none</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>1024</Value>
+                <DefaultValue>1024</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Size of the interrupt stack in bytes.</Description>
+                <Restrictions>Only used if hal.linker.enable_interrupt_stack is true.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.linker.interrupt_stack_memory_region_name</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>ddr3_ram</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>none</DestinationFile>
+                <Description>Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.</Description>
+                <Restrictions>Only used if hal.linker.enable_interrupt_stack is true.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.stdin</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>debug_uart</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.stdout</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>debug_uart</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.stderr</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>debug_uart</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.log_port</SettingName>
+                <Identifier>none</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.build_pre_process</SettingName>
+                <Identifier>BUILD_PRE_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before BSP built.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ar_pre_process</SettingName>
+                <Identifier>AR_PRE_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before archiver execution.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_defined_symbols</SettingName>
+                <Identifier>BSP_CFLAGS_DEFINED_SYMBOLS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-DTSE_MY_SYSTEM</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ar_post_process</SettingName>
+                <Identifier>AR_POST_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed after archiver execution.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.as</SettingName>
+                <Identifier>AS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>nios2-elf-gcc</Value>
+                <DefaultValue>nios2-elf-gcc</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Assembler command. Note that CC is used for .S files.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.build_post_process</SettingName>
+                <Identifier>BUILD_POST_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed after BSP built.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_debug</SettingName>
+                <Identifier>BSP_CFLAGS_DEBUG</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-g</Value>
+                <DefaultValue>-g</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ar</SettingName>
+                <Identifier>AR</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>nios2-elf-ar</Value>
+                <DefaultValue>nios2-elf-ar</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Archiver command. Creates library files.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.rm</SettingName>
+                <Identifier>RM</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>rm -f</Value>
+                <DefaultValue>rm -f</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command used to remove files during 'clean' target.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cxx_pre_process</SettingName>
+                <Identifier>CXX_PRE_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before each C++ file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_warnings</SettingName>
+                <Identifier>BSP_CFLAGS_WARNINGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-Wall</Value>
+                <DefaultValue>-Wall</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_arflags</SettingName>
+                <Identifier>BSP_ARFLAGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-src</Value>
+                <DefaultValue>-src</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_optimization</SettingName>
+                <Identifier>BSP_CFLAGS_OPTIMIZATION</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-O0</Value>
+                <DefaultValue>-O0</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.as_post_process</SettingName>
+                <Identifier>AS_POST_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed after each assembly file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cc_pre_process</SettingName>
+                <Identifier>CC_PRE_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before each .c/.S file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_asflags</SettingName>
+                <Identifier>BSP_ASFLAGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-Wa,-gdwarf2</Value>
+                <DefaultValue>-Wa,-gdwarf2</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.as_pre_process</SettingName>
+                <Identifier>AS_PRE_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before each assembly file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_undefined_symbols</SettingName>
+                <Identifier>BSP_CFLAGS_UNDEFINED_SYMBOLS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cc_post_process</SettingName>
+                <Identifier>CC_POST_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed after each .c/.S file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cxx_post_process</SettingName>
+                <Identifier>CXX_POST_PROCESS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Command executed before each C++ file is compiled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cc</SettingName>
+                <Identifier>CC</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>nios2-elf-gcc -xc</Value>
+                <DefaultValue>nios2-elf-gcc -xc</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>C compiler command.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cxx_flags</SettingName>
+                <Identifier>BSP_CXXFLAGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_inc_dirs</SettingName>
+                <Identifier>BSP_INC_DIRS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cxx</SettingName>
+                <Identifier>CXX</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>nios2-elf-gcc -xc++</Value>
+                <DefaultValue>nios2-elf-gcc -xc++</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>C++ compiler command.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.bsp_cflags_user_flags</SettingName>
+                <Identifier>BSP_CFLAGS_USER_FLAGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>makefile_variable</DestinationFile>
+                <Description>Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.cflags_mgpopt</SettingName>
+                <Identifier>CFLAGS_MGPOPT</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>-mgpopt=global</Value>
+                <DefaultValue>-mgpopt=global</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' tells the compilter not to generate GP-relative accesses. 'local' will generate GP-relative accesses for small data objects that are not external, weak, or uninitialized common symbols. Also use GP-relative addressing for objects that have been explicitly placed in a small data section via a section attribute. provides the default set of debug symbols typically required to debug a typical application. 'global' is same as 'local' but also generate GP-relative accesses for small data objects that are external, weak, or common.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.sopc_system_id</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=&lt;sysid>' and 'ELF_PATCH_FLAG  += --id=&lt;sysid>' to public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.sopc_system_timestamp</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=&lt;timestamp>' and 'ELF_PATCH_FLAG  += --timestamp=&lt;timestamp>' to public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.sopc_system_base_address</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=&lt;address>' and 'ELF_PATCH_FLAG  += --sidp=&lt;address>' to public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.sopc_simulation_enabled</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG  += --simulation_enabled' to public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.fpu_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.cdx_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>If true, prevents GCC from using CDX instructions. If false, GCC uses CDX instructions if present in the CPU.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.bmx_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>If true, prevents GCC from using BMX instructions. If false, GCC uses BMX instructions if present in the CPU.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.hardware_multiplier_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.hardware_mulx_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.hardware_divide_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.debug_core_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.big_endian</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -meb' to public.mk if big endian system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_exit</SettingName>
+                <Identifier>ALT_NO_EXIT</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_small_c_library</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_clean_exit</SettingName>
+                <Identifier>ALT_NO_CLEAN_EXIT</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_runtime_stack_checking</SettingName>
+                <Identifier>ALT_STACK_CHECK</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to ALT_CPPFLAGS in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_gprof</SettingName>
+                <Identifier>ALT_PROVIDE_GMON</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_c_plus_plus</SettingName>
+                <Identifier>ALT_NO_C_PLUS_PLUS</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_reduced_device_drivers</SettingName>
+                <Identifier>ALT_USE_SMALL_DRIVERS</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_lightweight_device_driver_api</SettingName>
+                <Identifier>ALT_USE_DIRECT_DRIVERS</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>
+                <Restrictions>The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_mul_div_emulation</SettingName>
+                <Identifier>ALT_NO_INSTRUCTION_EMULATION</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_sim_optimize</SettingName>
+                <Identifier>ALT_SIM_OPTIMIZE</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.</Description>
+                <Restrictions>When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>common</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.enable_sopc_sysid_check</SettingName>
+                <Identifier>none</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.custom_newlib_flags</SettingName>
+                <Identifier>CUSTOM_NEWLIB_FLAGS</Identifier>
+                <Type>UnquotedString</Type>
+                <Value>none</Value>
+                <DefaultValue>none</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Build a custom version of newlib with the specified space-separated compiler flags.</Description>
+                <Restrictions>The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>hal.log_flags</SettingName>
+                <Identifier>ALT_LOG_FLAGS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.</Description>
+                <Restrictions>hal.log_port must be set for this to be used.</Restrictions>
+                <Enabled>false</Enabled>
+                <Group>none</Group>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_max_tasks</SettingName>
+                <Identifier>OS_MAX_TASKS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>5</Value>
+                <DefaultValue>10</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of tasks</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_lowest_prio</SettingName>
+                <Identifier>OS_LOWEST_PRIO</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>20</Value>
+                <DefaultValue>20</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Lowest assignable priority</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_thread_safe_newlib</SettingName>
+                <Identifier>OS_THREAD_SAFE_NEWLIB</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Thread safe C library</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_arg_chk_en</SettingName>
+                <Identifier>OS_ARG_CHK_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable argument checking</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_cpu_hooks_en</SettingName>
+                <Identifier>OS_CPU_HOOKS_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable uCOS-II hooks</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_debug_en</SettingName>
+                <Identifier>OS_DEBUG_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable debug variables</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_sched_lock_en</SettingName>
+                <Identifier>OS_SCHED_LOCK_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSSchedLock() and OSSchedUnlock()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_task_stat_en</SettingName>
+                <Identifier>OS_TASK_STAT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable statistics task</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_task_stat_stk_chk_en</SettingName>
+                <Identifier>OS_TASK_STAT_STK_CHK_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Check task stacks from statistics task</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_tick_step_en</SettingName>
+                <Identifier>OS_TICK_STEP_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable tick stepping feature for uCOS-View</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_event_name_size</SettingName>
+                <Identifier>OS_EVENT_NAME_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>32</Value>
+                <DefaultValue>32</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of name of Event Control Block groups</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_max_events</SettingName>
+                <Identifier>OS_MAX_EVENTS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>60</Value>
+                <DefaultValue>60</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of event control blocks</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_task_idle_stk_size</SettingName>
+                <Identifier>OS_TASK_IDLE_STK_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>512</Value>
+                <DefaultValue>512</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Idle task stack size</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.miscellaneous.os_task_stat_stk_size</SettingName>
+                <Identifier>OS_TASK_STAT_STK_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>512</Value>
+                <DefaultValue>512</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Statistics task stack size</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_change_prio_en</SettingName>
+                <Identifier>OS_TASK_CHANGE_PRIO_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskChangePrio()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_create_en</SettingName>
+                <Identifier>OS_TASK_CREATE_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskCreate()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_create_ext_en</SettingName>
+                <Identifier>OS_TASK_CREATE_EXT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskCreateExt()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_del_en</SettingName>
+                <Identifier>OS_TASK_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskDel()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_name_size</SettingName>
+                <Identifier>OS_TASK_NAME_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>32</Value>
+                <DefaultValue>32</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of task name</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_profile_en</SettingName>
+                <Identifier>OS_TASK_PROFILE_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include data structure for run-time task profiling</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_query_en</SettingName>
+                <Identifier>OS_TASK_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskQuery</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_suspend_en</SettingName>
+                <Identifier>OS_TASK_SUSPEND_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskSuspend() and OSTaskResume()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.task.os_task_sw_hook_en</SettingName>
+                <Identifier>OS_TASK_SW_HOOK_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTaskSwHook()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.time.os_time_tick_hook_en</SettingName>
+                <Identifier>OS_TIME_TICK_HOOK_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTimeTickHook()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.time.os_time_dly_resume_en</SettingName>
+                <Identifier>OS_TIME_DLY_RESUME_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTimeDlyResume()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.time.os_time_dly_hmsm_en</SettingName>
+                <Identifier>OS_TIME_DLY_HMSM_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTimeDlyHMSM()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.time.os_time_get_set_en</SettingName>
+                <Identifier>OS_TIME_GET_SET_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSTimeGet and OSTimeSet()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_flag_en</SettingName>
+                <Identifier>OS_FLAG_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flag_wait_clr_en</SettingName>
+                <Identifier>OS_FLAG_WAIT_CLR_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flag_accept_en</SettingName>
+                <Identifier>OS_FLAG_ACCEPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flag_del_en</SettingName>
+                <Identifier>OS_FLAG_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flag_query_en</SettingName>
+                <Identifier>OS_FLAG_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flag_name_size</SettingName>
+                <Identifier>OS_FLAG_NAME_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>32</Value>
+                <DefaultValue>32</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_flags_nbits</SettingName>
+                <Identifier>OS_FLAGS_NBITS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>16</Value>
+                <DefaultValue>16</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.event_flag.os_max_flags</SettingName>
+                <Identifier>OS_MAX_FLAGS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>20</Value>
+                <DefaultValue>20</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_mutex_en</SettingName>
+                <Identifier>OS_MUTEX_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for Mutex Semaphores</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mutex.os_mutex_accept_en</SettingName>
+                <Identifier>OS_MUTEX_ACCEPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMutexAccept()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mutex.os_mutex_del_en</SettingName>
+                <Identifier>OS_MUTEX_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMutexDel()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mutex.os_mutex_query_en</SettingName>
+                <Identifier>OS_MUTEX_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMutexQuery</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_sem_en</SettingName>
+                <Identifier>OS_SEM_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.semaphore.os_sem_accept_en</SettingName>
+                <Identifier>OS_SEM_ACCEPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.semaphore.os_sem_set_en</SettingName>
+                <Identifier>OS_SEM_SET_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.semaphore.os_sem_del_en</SettingName>
+                <Identifier>OS_SEM_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.semaphore.os_sem_query_en</SettingName>
+                <Identifier>OS_SEM_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_mbox_en</SettingName>
+                <Identifier>OS_MBOX_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for mailboxes</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mailbox.os_mbox_accept_en</SettingName>
+                <Identifier>OS_MBOX_ACCEPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMboxAccept()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mailbox.os_mbox_del_en</SettingName>
+                <Identifier>OS_MBOX_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMboxDel()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mailbox.os_mbox_post_en</SettingName>
+                <Identifier>OS_MBOX_POST_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMboxPost()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mailbox.os_mbox_post_opt_en</SettingName>
+                <Identifier>OS_MBOX_POST_OPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMboxPostOpt()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.mailbox.os_mbox_query_en</SettingName>
+                <Identifier>OS_MBOX_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMboxQuery()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_q_en</SettingName>
+                <Identifier>OS_Q_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for Queues</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_accept_en</SettingName>
+                <Identifier>OS_Q_ACCEPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQAccept()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_del_en</SettingName>
+                <Identifier>OS_Q_DEL_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQDel()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_flush_en</SettingName>
+                <Identifier>OS_Q_FLUSH_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQFlush()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_post_en</SettingName>
+                <Identifier>OS_Q_POST_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code of OSQFlush()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_post_front_en</SettingName>
+                <Identifier>OS_Q_POST_FRONT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQPostFront()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_post_opt_en</SettingName>
+                <Identifier>OS_Q_POST_OPT_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQPostOpt()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_q_query_en</SettingName>
+                <Identifier>OS_Q_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSQQuery()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.queue.os_max_qs</SettingName>
+                <Identifier>OS_MAX_QS</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>20</Value>
+                <DefaultValue>20</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of Queue Control Blocks</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_mem_en</SettingName>
+                <Identifier>OS_MEM_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for memory management</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.memory.os_mem_query_en</SettingName>
+                <Identifier>OS_MEM_QUERY_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>1</Value>
+                <DefaultValue>1</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Include code for OSMemQuery()</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.memory.os_mem_name_size</SettingName>
+                <Identifier>OS_MEM_NAME_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>32</Value>
+                <DefaultValue>32</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of memory partition name</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.memory.os_max_mem_part</SettingName>
+                <Identifier>OS_MAX_MEM_PART</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>60</Value>
+                <DefaultValue>60</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of memory partitions</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.os_tmr_en</SettingName>
+                <Identifier>OS_TMR_EN</Identifier>
+                <Type>Boolean</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable code for timers</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_task_tmr_stk_size</SettingName>
+                <Identifier>OS_TASK_TMR_STK_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>512</Value>
+                <DefaultValue>512</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Stack size for timer task</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_task_tmr_prio</SettingName>
+                <Identifier>OS_TASK_TMR_PRIO</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>0</Value>
+                <DefaultValue>0</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Priority of timer task (0=highest)</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_tmr_cfg_max</SettingName>
+                <Identifier>OS_TMR_CFG_MAX</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>16</Value>
+                <DefaultValue>16</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Maximum number of timers</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_tmr_cfg_name_size</SettingName>
+                <Identifier>OS_TMR_CFG_NAME_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>16</Value>
+                <DefaultValue>16</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of timer name</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_tmr_cfg_ticks_per_sec</SettingName>
+                <Identifier>OS_TMR_CFG_TICKS_PER_SEC</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>10</Value>
+                <DefaultValue>10</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Rate at which timer management task runs (Hz)</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>ucosii.timer.os_tmr_cfg_wheel_size</SettingName>
+                <Identifier>OS_TMR_CFG_WHEEL_SIZE</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>2</Value>
+                <DefaultValue>2</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Size of timer wheel (number of spokes)</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.iniche_default_if</SettingName>
+                <Identifier>INICHE_DEFAULT_IF</Identifier>
+                <Type>QuotedString</Type>
+                <Value>NOT_USED</Value>
+                <DefaultValue>NOT_USED</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Deprecated setting: Default MAC interface. This setting was formerly used by Altera networking example applications. It need not be assigned a valid value for the use of networking example designs in Nios II 8.0. If you are using this setting in a project, it is recomended that you remove the dependency. This setting may be removed in a future release.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.enable_dhcp_client</SettingName>
+                <Identifier>DHCP_CLIENT</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>true</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Use DHCP to automatically assign IP address</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.enable_ip_fragments</SettingName>
+                <Identifier>IP_FRAGMENTS</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>true</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Reassemble IP packet fragments</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.enable_include_tcp</SettingName>
+                <Identifier>INCLUDE_TCP</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>true</Value>
+                <DefaultValue>true</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable TCP protocol</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.enable_tcp_zerocopy</SettingName>
+                <Identifier>TCP_ZEROCOPY</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>false</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Use TCP zero-copy</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_iniche.enable_net_stats</SettingName>
+                <Identifier>NET_STATS</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>false</DefaultValue>
+                <DestinationFile>system_h_define</DestinationFile>
+                <Description>Enable statistics</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_eth_tse_driver_ucosii_iniche.autoneg_timeout</SettingName>
+                <Identifier>ALTERA_AUTONEG_TIMEOUT_THRESHOLD</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>2500</Value>
+                <DefaultValue>2500</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Auto Negotiation Timeout in milliseconds</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_eth_tse_driver_ucosii_iniche.checklink_timeout</SettingName>
+                <Identifier>ALTERA_CHECKLINK_TIMEOUT_THRESHOLD</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>10000</Value>
+                <DefaultValue>10000</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>CheckLink Timeout in milliseconds</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_eth_tse_driver_ucosii_iniche.nomdio_timeout</SettingName>
+                <Identifier>ALTERA_NOMDIO_TIMEOUT_THRESHOLD</Identifier>
+                <Type>DecimalNumber</Type>
+                <Value>1000000</Value>
+                <DefaultValue>1000000</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>"No MDIO" Timeout in microseconds</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_avalon_uart_driver.enable_small_driver</SettingName>
+                <Identifier>ALTERA_AVALON_UART_SMALL</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>false</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Small-footprint (polled mode) driver</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <Setting>
+                <SettingName>altera_avalon_uart_driver.enable_ioctl</SettingName>
+                <Identifier>ALTERA_AVALON_UART_USE_IOCTL</Identifier>
+                <Type>BooleanDefineOnly</Type>
+                <Value>false</Value>
+                <DefaultValue>false</DefaultValue>
+                <DestinationFile>public_mk_define</DestinationFile>
+                <Description>Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.</Description>
+                <Restrictions>none</Restrictions>
+                <Enabled>false</Enabled>
+                <Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
+        </Setting>
+        <MemoryMap>
+                <slaveDescriptor>ddr3_ram</slaveDescriptor>
+                <addressRange>0x08000000 - 0x0FFFFFFF</addressRange>
+                <addressSpan>134217728</addressSpan>
+                <attributes>memory</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>ext_flash_avl_mem</slaveDescriptor>
+                <addressRange>0x14000000 - 0x17FFFFFF</addressRange>
+                <addressSpan>67108864</addressSpan>
+                <attributes>flash, memory, non-volatile</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>onchip_flash_data</slaveDescriptor>
+                <addressRange>0x18200000 - 0x1835FFFF</addressRange>
+                <addressSpan>1441792</addressSpan>
+                <attributes>flash, memory, non-volatile</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>descriptor_memory</slaveDescriptor>
+                <addressRange>0x18400000 - 0x18401FFF</addressRange>
+                <addressSpan>8192</addressSpan>
+                <attributes>memory</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>eth_tse</slaveDescriptor>
+                <addressRange>0x18403000 - 0x184033FF</addressRange>
+                <addressSpan>1024</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>calibration_ram</slaveDescriptor>
+                <addressRange>0x18403400 - 0x1840367F</addressRange>
+                <addressSpan>640</addressSpan>
+                <attributes>memory</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>frame_timer</slaveDescriptor>
+                <addressRange>0x18403C00 - 0x18403C1F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes>timer</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>debug_uart</slaveDescriptor>
+                <addressRange>0x18403C20 - 0x18403C3F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes>printable</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>output_pio</slaveDescriptor>
+                <addressRange>0x18403C40 - 0x18403C5F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>sys_clk_timer</slaveDescriptor>
+                <addressRange>0x18403C60 - 0x18403C7F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes>timer</attributes>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>msgdma_rx_prefetcher_csr</slaveDescriptor>
+                <addressRange>0x18403C80 - 0x18403C9F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>msgdma_tx_prefetcher_csr</slaveDescriptor>
+                <addressRange>0x18403CA0 - 0x18403CBF</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>udp_generator</slaveDescriptor>
+                <addressRange>0x18403CC0 - 0x18403CDF</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>msgdma_rx_csr</slaveDescriptor>
+                <addressRange>0x18403CE0 - 0x18403CFF</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>msgdma_tx_csr</slaveDescriptor>
+                <addressRange>0x18403D00 - 0x18403D1F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>ext_flash_avl_csr</slaveDescriptor>
+                <addressRange>0x18403D20 - 0x18403D3F</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>button_pio</slaveDescriptor>
+                <addressRange>0x18403D40 - 0x18403D4F</addressRange>
+                <addressSpan>16</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>sensor_interface</slaveDescriptor>
+                <addressRange>0x18403D50 - 0x18403D5F</addressRange>
+                <addressSpan>16</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>onchip_flash_csr</slaveDescriptor>
+                <addressRange>0x18403D60 - 0x18403D67</addressRange>
+                <addressSpan>8</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>sysid</slaveDescriptor>
+                <addressRange>0x18403D68 - 0x18403D6F</addressRange>
+                <addressSpan>8</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <LinkerSection>
+                <sectionName>.text</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <LinkerSection>
+                <sectionName>.rodata</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <LinkerSection>
+                <sectionName>.rwdata</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <LinkerSection>
+                <sectionName>.bss</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <LinkerSection>
+                <sectionName>.heap</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <LinkerSection>
+                <sectionName>.stack</sectionName>
+                <regionName>ddr3_ram</regionName>
+        </LinkerSection>
+        <SoftwarePackageInfo>
+                <name>altera_iniche</name>
+                <version>default</version>
+        </SoftwarePackageInfo>
+        <IgnoredFileInfo>
+                <componentName>altera_eth_tse_driver_ucosii_iniche</componentName>
+                <fileName>altera_avalon_tse.c</fileName>
+        </IgnoredFileInfo>
+</sch:Settings>
\ No newline at end of file
diff --git a/FPGA_nios/hit_pat_bsp/summary.html b/FPGA_nios/hit_pat_bsp/summary.html
new file mode 100644
index 0000000..ed4ba82
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/summary.html
@@ -0,0 +1,4294 @@
+<html xmlns:gen="http://www.altera.com/embeddedsw/bsp/schema">
+<title>Altera Nios II BSP Summary</title>
+<body>
+<h3>BSP Description</h3>
+<table border="1" bgcolor="#FFFFCC" width="90%">
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Type:</td><td>ucosii</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>D:\hit20v3\software\hit_pat\q_sys.sopcinfo</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">Quartus JDI File:</td><td>default</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">CPU:</td><td>cpu</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Settings File:</td><td>settings.bsp</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>11-Oct-2024 10:12:19</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1728634339674</td>
+</tr>
+<tr mode="wrap">
+<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>D:\hit20v3\software\hit_pat\software\hit_pat_bsp</td>
+</tr>
+</table>
+<br>
+<h3>Nios II Memory Map</h3>
+<table border="1" bgcolor="#FFFFCC" width="90%">
+<tr bgcolor="#77BBFF" mode="wrap">
+<th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>sysid</td><td>0x18403D68 - 0x18403D6F</td><td>8</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>onchip_flash_csr</td><td>0x18403D60 - 0x18403D67</td><td>8</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>sensor_interface</td><td>0x18403D50 - 0x18403D5F</td><td>16</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>button_pio</td><td>0x18403D40 - 0x18403D4F</td><td>16</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>ext_flash_avl_csr</td><td>0x18403D20 - 0x18403D3F</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>msgdma_tx_csr</td><td>0x18403D00 - 0x18403D1F</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>msgdma_rx_csr</td><td>0x18403CE0 - 0x18403CFF</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>udp_generator</td><td>0x18403CC0 - 0x18403CDF</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>msgdma_tx_prefetcher_csr</td><td>0x18403CA0 - 0x18403CBF</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>msgdma_rx_prefetcher_csr</td><td>0x18403C80 - 0x18403C9F</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>sys_clk_timer</td><td>0x18403C60 - 0x18403C7F</td><td>32</td><td class="listing">timer</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>output_pio</td><td>0x18403C40 - 0x18403C5F</td><td>32</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>debug_uart</td><td>0x18403C20 - 0x18403C3F</td><td>32</td><td class="listing">printable</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>frame_timer</td><td>0x18403C00 - 0x18403C1F</td><td>32</td><td class="listing">timer</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>calibration_ram</td><td>0x18403400 - 0x1840367F</td><td>640</td><td class="listing">memory</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>eth_tse</td><td>0x18403000 - 0x184033FF</td><td>1024</td><td class="listing">&nbsp;</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>descriptor_memory</td><td>0x18400000 - 0x18401FFF</td><td>8192</td><td class="listing">memory</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>onchip_flash_data</td><td>0x18200000 - 0x1835FFFF</td><td>1441792</td><td class="listing">flash, memory, non-volatile</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>ext_flash_avl_mem</td><td>0x14000000 - 0x17FFFFFF</td><td>67108864</td><td class="listing">flash, memory, non-volatile</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>ddr3_ram</td><td>0x08000000 - 0x0FFFFFFF</td><td>134217728</td><td class="listing">memory</td>
+</tr>
+</table>
+<br>
+<br>
+<h3>Linker Regions</h3>
+<table border="1" bgcolor="#FFFFCC" width="90%">
+<tr bgcolor="#77BBFF" mode="wrap">
+<th align="left" width="15%">Region</th><th align="left" width="40%">Address Range</th><th align="left" width="15%">Size</th><th align="left" width="15%">Memory</th><th align="left" width="15%">Offset</th>
+</tr>
+</table>
+<br>
+<br>
+<h3>Linker Section Mappings</h3>
+<table border="1" bgcolor="#FFFFCC" width="50%">
+<tr bgcolor="#77BBFF" mode="wrap">
+<th align="left" width="50%">Section</th><th align="left" width="50%">Region</th>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.text</td><td>ddr3_ram</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.rodata</td><td>ddr3_ram</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.rwdata</td><td>ddr3_ram</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.bss</td><td>ddr3_ram</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.heap</td><td>ddr3_ram</td>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>.stack</td><td>ddr3_ram</td>
+</tr>
+</table>
+<br>
+<br>
+<h3>Software Packages</h3>
+<table border="1" bgcolor="#FFFFCC" width="50%">
+<tr bgcolor="#77BBFF" mode="wrap">
+<th align="left" width="15%">Software Package</th><th align="left" width="15%">Version</th>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>altera_iniche</td><td>default</td>
+</tr>
+</table>
+<br>
+<br>
+<h3>Files Ignored During BSP Generate</h3>
+<table border="1" bgcolor="#FFFFCC" width="90%">
+<tr bgcolor="#77BBFF" mode="wrap">
+<th align="left" width="50%">Component Name</th><th align="left" width="50%">File Name</th>
+</tr>
+<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
+<td>altera_eth_tse_driver_ucosii_iniche</td><td>altera_avalon_tse.c</td>
+</tr>
+</table>
+<br>
+<br>
+<h3>Settings</h3>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_avalon_uart_driver.enable_ioctl</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALTERA_AVALON_UART_USE_IOCTL</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_avalon_uart_driver.enable_small_driver</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALTERA_AVALON_UART_SMALL</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Small-footprint (polled mode) driver</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_eth_tse_driver_ucosii_iniche.autoneg_timeout</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALTERA_AUTONEG_TIMEOUT_THRESHOLD</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>2500</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>2500</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Auto Negotiation Timeout in milliseconds</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_eth_tse_driver_ucosii_iniche.checklink_timeout</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALTERA_CHECKLINK_TIMEOUT_THRESHOLD</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>10000</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>10000</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>CheckLink Timeout in milliseconds</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_eth_tse_driver_ucosii_iniche.nomdio_timeout</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALTERA_NOMDIO_TIMEOUT_THRESHOLD</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1000000</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1000000</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>"No MDIO" Timeout in microseconds</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.enable_dhcp_client</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>DHCP_CLIENT</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>true</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Use DHCP to automatically assign IP address</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.enable_include_tcp</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>INCLUDE_TCP</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>true</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>true</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable TCP protocol</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.enable_ip_fragments</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>IP_FRAGMENTS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>true</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Reassemble IP packet fragments</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.enable_net_stats</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>NET_STATS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable statistics</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.enable_tcp_zerocopy</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>TCP_ZEROCOPY</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Use TCP zero-copy</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">altera_iniche.iniche_default_if</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>INICHE_DEFAULT_IF</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>NOT_USED</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>NOT_USED</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>QuotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Deprecated setting: Default MAC interface. This setting was formerly used by Altera networking example applications. It need not be assigned a valid value for the use of networking example designs in Nios II 8.0. If you are using this setting in a project, it is recomended that you remove the dependency. This setting may be removed in a future release.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.custom_newlib_flags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CUSTOM_NEWLIB_FLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Build a custom version of newlib with the specified space-separated compiler flags.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>The custom newlib build will be placed in the &lt;bsp root&gt;/newlib directory, and will be used only for applications that utilize this BSP.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_c_plus_plus</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_NO_C_PLUS_PLUS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_clean_exit</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_NO_CLEAN_EXIT</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_exit</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_NO_EXIT</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_gprof</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_PROVIDE_GMON</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_instruction_related_exceptions_api</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>false</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>true</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>BooleanDefineOnly</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_lightweight_device_driver_api</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_USE_DIRECT_DRIVERS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_mul_div_emulation</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_NO_INSTRUCTION_EMULATION</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_reduced_device_drivers</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_USE_SMALL_DRIVERS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_runtime_stack_checking</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_STACK_CHECK</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to ALT_CPPFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_sim_optimize</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_SIM_OPTIMIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_small_c_library</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.enable_sopc_sysid_check</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.allow_code_at_reset</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_ALLOW_CODE_AT_RESET</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_alt_load</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_alt_load_copy_exceptions</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_alt_load_copy_rodata</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_alt_load_copy_rwdata</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_exception_stack</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.enable_interrupt_stack</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.exception_stack_memory_region_name</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>ddr3_ram</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>Only used if hal.linker.enable_exception_stack is true.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.exception_stack_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1024</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1024</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of the exception stack in bytes.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>Only used if hal.linker.enable_exception_stack is true.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.interrupt_stack_memory_region_name</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>ddr3_ram</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>Only used if hal.linker.enable_interrupt_stack is true.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.linker.interrupt_stack_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1024</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1024</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>none</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of the interrupt stack in bytes.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>Only used if hal.linker.enable_interrupt_stack is true.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.log_flags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_LOG_FLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>hal.log_port must be set for this to be used.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.log_port</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ar</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AR</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>nios2-elf-ar</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>nios2-elf-ar</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Archiver command. Creates library files.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ar_post_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AR_POST_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed after archiver execution.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ar_pre_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AR_PRE_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before archiver execution.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.as</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>nios2-elf-gcc</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>nios2-elf-gcc</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Assembler command. Note that CC is used for .S files.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.as_post_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AS_POST_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed after each assembly file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.as_pre_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>AS_PRE_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before each assembly file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_arflags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_ARFLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-src</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-src</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_asflags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_ASFLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-Wa,-gdwarf2</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-Wa,-gdwarf2</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_debug</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_DEBUG</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-g</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-g</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_defined_symbols</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_DEFINED_SYMBOLS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-DTSE_MY_SYSTEM</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_optimization</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_OPTIMIZATION</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-O0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-O0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_undefined_symbols</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_UNDEFINED_SYMBOLS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_user_flags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_USER_FLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cflags_warnings</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CFLAGS_WARNINGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-Wall</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-Wall</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_cxx_flags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_CXXFLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.bsp_inc_dirs</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BSP_INC_DIRS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.build_post_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BUILD_POST_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed after BSP built.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.build_pre_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>BUILD_PRE_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before BSP built.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cc</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CC</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>nios2-elf-gcc -xc</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>nios2-elf-gcc -xc</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C compiler command.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cc_post_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CC_POST_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed after each .c/.S file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cc_pre_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CC_PRE_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before each .c/.S file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cflags_mgpopt</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CFLAGS_MGPOPT</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>-mgpopt=global</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>-mgpopt=global</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' tells the compilter not to generate GP-relative accesses. 'local' will generate GP-relative accesses for small data objects that are not external, weak, or uninitialized common symbols. Also use GP-relative addressing for objects that have been explicitly placed in a small data section via a section attribute. provides the default set of debug symbols typically required to debug a typical application. 'global' is same as 'local' but also generate GP-relative accesses for small data objects that are external, weak, or common.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cxx</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CXX</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>nios2-elf-gcc -xc++</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>nios2-elf-gcc -xc++</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>C++ compiler command.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cxx_post_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CXX_POST_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before each C++ file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.cxx_pre_process</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>CXX_PRE_PROCESS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command executed before each C++ file is compiled.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.big_endian</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -meb' to public.mk if big endian system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.bmx_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>If true, prevents GCC from using BMX instructions. If false, GCC uses BMX instructions if present in the CPU.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.cdx_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>If true, prevents GCC from using CDX instructions. If false, GCC uses CDX instructions if present in the CPU.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.debug_core_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.fpu_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.hardware_divide_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.hardware_multiplier_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.hardware_mulx_present</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.sopc_simulation_enabled</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG  += --simulation_enabled' to public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.sopc_system_base_address</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=&lt;address&gt;' and 'ELF_PATCH_FLAG  += --sidp=&lt;address&gt;' to public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.sopc_system_id</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=&lt;sysid&gt;' and 'ELF_PATCH_FLAG  += --id=&lt;sysid&gt;' to public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.ignore_system_derived.sopc_system_timestamp</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>public_mk_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=&lt;timestamp&gt;' and 'ELF_PATCH_FLAG  += --timestamp=&lt;timestamp&gt;' to public.mk.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.make.rm</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>RM</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>rm -f</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>rm -f</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>makefile_variable</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Command used to remove files during 'clean' target.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.max_file_descriptors</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_MAX_FD</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.stderr</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>debug_uart</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.stdin</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>debug_uart</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.stdout</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>debug_uart</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.sys_clk_timer</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_SYS_CLK</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>sys_clk_timer</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">hal.timestamp_timer</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>ALT_TIMESTAMP_CLK</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>none</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>UnquotedString</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flag_accept_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_ACCEPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flag_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flag_name_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_NAME_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flag_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flag_wait_clr_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_WAIT_CLR_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_flags_nbits</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAGS_NBITS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.event_flag.os_max_flags</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MAX_FLAGS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mailbox.os_mbox_accept_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_ACCEPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMboxAccept()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mailbox.os_mbox_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMboxDel()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mailbox.os_mbox_post_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_POST_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMboxPost()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mailbox.os_mbox_post_opt_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_POST_OPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMboxPostOpt()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mailbox.os_mbox_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMboxQuery()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.memory.os_max_mem_part</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MAX_MEM_PART</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>60</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>60</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of memory partitions</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.memory.os_mem_name_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MEM_NAME_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of memory partition name</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.memory.os_mem_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MEM_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMemQuery()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_arg_chk_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_ARG_CHK_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable argument checking</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_cpu_hooks_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_CPU_HOOKS_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable uCOS-II hooks</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_debug_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_DEBUG_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable debug variables</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_event_name_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_EVENT_NAME_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of name of Event Control Block groups</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_max_events</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MAX_EVENTS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>60</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>60</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of event control blocks</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_sched_lock_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SCHED_LOCK_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSSchedLock() and OSSchedUnlock()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_task_idle_stk_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_IDLE_STK_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Idle task stack size</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_task_stat_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_STAT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable statistics task</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_task_stat_stk_chk_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_STAT_STK_CHK_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Check task stacks from statistics task</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_task_stat_stk_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_STAT_STK_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Statistics task stack size</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.miscellaneous.os_tick_step_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TICK_STEP_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable tick stepping feature for uCOS-View</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mutex.os_mutex_accept_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MUTEX_ACCEPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMutexAccept()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mutex.os_mutex_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MUTEX_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMutexDel()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.mutex.os_mutex_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MUTEX_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSMutexQuery</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_flag_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_FLAG_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_lowest_prio</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_LOWEST_PRIO</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Lowest assignable priority</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_max_tasks</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MAX_TASKS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>10</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>5</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of tasks</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_mbox_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MBOX_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for mailboxes</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_mem_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MEM_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for memory management</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_mutex_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MUTEX_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for Mutex Semaphores</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_q_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for Queues</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_sem_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SEM_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_thread_safe_newlib</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_THREAD_SAFE_NEWLIB</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Thread safe C library</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.os_tmr_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TMR_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Enable code for timers</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_max_qs</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_MAX_QS</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>20</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of Queue Control Blocks</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_accept_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_ACCEPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQAccept()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQDel()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_flush_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_FLUSH_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQFlush()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_post_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_POST_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code of OSQFlush()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_post_front_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_POST_FRONT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQPostFront()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_post_opt_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_POST_OPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQPostOpt()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.queue.os_q_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_Q_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSQQuery()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.semaphore.os_sem_accept_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SEM_ACCEPT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.semaphore.os_sem_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SEM_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.semaphore.os_sem_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SEM_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.semaphore.os_sem_set_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_SEM_SET_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_change_prio_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_CHANGE_PRIO_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskChangePrio()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_create_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_CREATE_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskCreate()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_create_ext_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_CREATE_EXT_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskCreateExt()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_del_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_DEL_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskDel()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_name_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_NAME_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>32</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of task name</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_profile_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_PROFILE_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include data structure for run-time task profiling</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_query_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_QUERY_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskQuery</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_suspend_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_SUSPEND_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskSuspend() and OSTaskResume()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.task.os_task_sw_hook_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_SW_HOOK_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTaskSwHook()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.time.os_time_dly_hmsm_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TIME_DLY_HMSM_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTimeDlyHMSM()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.time.os_time_dly_resume_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TIME_DLY_RESUME_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTimeDlyResume()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.time.os_time_get_set_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TIME_GET_SET_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTimeGet and OSTimeSet()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.time.os_time_tick_hook_en</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TIME_TICK_HOOK_EN</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>1</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>Boolean</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Include code for OSTimeTickHook()</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_task_tmr_prio</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_TMR_PRIO</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>0</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Priority of timer task (0=highest)</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_task_tmr_stk_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TASK_TMR_STK_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>512</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Stack size for timer task</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_tmr_cfg_max</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TMR_CFG_MAX</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Maximum number of timers</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_tmr_cfg_name_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TMR_CFG_NAME_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>16</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of timer name</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_tmr_cfg_ticks_per_sec</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TMR_CFG_TICKS_PER_SEC</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>10</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>10</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Rate at which timer management task runs (Hz)</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<table border="1" bgcolor="#FFFFCC" width="60%">
+<tr bgcolor="#77BBFF">
+<td align="left" width="15%">Setting Name:</td><td align="left">ucosii.timer.os_tmr_cfg_wheel_size</td>
+</tr>
+<tr>
+<td width="20%">Identifier:</td><td>OS_TMR_CFG_WHEEL_SIZE</td>
+</tr>
+<tr>
+<td width="20%">Default Value:</td><td>2</td>
+</tr>
+<tr>
+<td width="20%">Value:</td><td>2</td>
+</tr>
+<tr>
+<td width="20%">Type:</td><td>DecimalNumber</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Destination:</td><td>system_h_define</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Description:</td><td>Size of timer wheel (number of spokes)</td>
+</tr>
+<tr mode="wrap">
+<td width="20%">Restrictions:</td><td>none</td>
+</tr>
+</table>
+<br>
+<br>
+<br>
+</body>
+</html>
diff --git a/FPGA_nios/hit_pat_bsp/system.h b/FPGA_nios/hit_pat_bsp/system.h
new file mode 100644
index 0000000..e032648
--- /dev/null
+++ b/FPGA_nios/hit_pat_bsp/system.h
@@ -0,0 +1,822 @@
+/*
+ * system.h - SOPC Builder system and BSP software package information
+ *
+ * Machine generated for CPU 'cpu' in SOPC Builder design 'q_sys'
+ * SOPC Builder design path: D:/hit20v3/software/hit_pat/q_sys.sopcinfo
+ *
+ * Generated: Fri Oct 11 10:12:20 CEST 2024
+ */
+
+/*
+ * DO NOT MODIFY THIS FILE
+ *
+ * Changing this file will have subtle consequences
+ * which will almost certainly lead to a nonfunctioning
+ * system. If you do modify this file, be aware that your
+ * changes will be overwritten and lost when this file
+ * is generated again.
+ *
+ * DO NOT MODIFY THIS FILE
+ */
+
+/*
+ * License Agreement
+ *
+ * Copyright (c) 2008
+ * Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#ifndef __SYSTEM_H_
+#define __SYSTEM_H_
+
+/* Include definitions from linker script generator */
+#include "linker.h"
+
+
+/*
+ * CPU configuration
+ *
+ */
+
+#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
+#define ALT_CPU_BIG_ENDIAN 0
+#define ALT_CPU_BREAK_ADDR 0x18402820
+#define ALT_CPU_CPU_ARCH_NIOS2_R1
+#define ALT_CPU_CPU_FREQ 50000000u
+#define ALT_CPU_CPU_ID_SIZE 1
+#define ALT_CPU_CPU_ID_VALUE 0x00000000
+#define ALT_CPU_CPU_IMPLEMENTATION "fast"
+#define ALT_CPU_DATA_ADDR_WIDTH 0x1d
+#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
+#define ALT_CPU_DCACHE_LINE_SIZE 32
+#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
+#define ALT_CPU_DCACHE_SIZE 2048
+#define ALT_CPU_EXCEPTION_ADDR 0x08000120
+#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
+#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
+#define ALT_CPU_FLUSHDA_SUPPORTED
+#define ALT_CPU_FREQ 50000000
+#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
+#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
+#define ALT_CPU_HARDWARE_MULX_PRESENT 0
+#define ALT_CPU_HAS_DEBUG_CORE 1
+#define ALT_CPU_HAS_DEBUG_STUB
+#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
+#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define ALT_CPU_HAS_JMPI_INSTRUCTION
+#define ALT_CPU_ICACHE_LINE_SIZE 32
+#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
+#define ALT_CPU_ICACHE_SIZE 2048
+#define ALT_CPU_INITDA_SUPPORTED
+#define ALT_CPU_INST_ADDR_WIDTH 0x1d
+#define ALT_CPU_NAME "cpu"
+#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
+#define ALT_CPU_OCI_VERSION 1
+#define ALT_CPU_RESET_ADDR 0x14000000
+
+
+/*
+ * CPU configuration (with legacy prefix - don't use these anymore)
+ *
+ */
+
+#define NIOS2_BIG_ENDIAN 0
+#define NIOS2_BREAK_ADDR 0x18402820
+#define NIOS2_CPU_ARCH_NIOS2_R1
+#define NIOS2_CPU_FREQ 50000000u
+#define NIOS2_CPU_ID_SIZE 1
+#define NIOS2_CPU_ID_VALUE 0x00000000
+#define NIOS2_CPU_IMPLEMENTATION "fast"
+#define NIOS2_DATA_ADDR_WIDTH 0x1d
+#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
+#define NIOS2_DCACHE_LINE_SIZE 32
+#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
+#define NIOS2_DCACHE_SIZE 2048
+#define NIOS2_EXCEPTION_ADDR 0x08000120
+#define NIOS2_FLASH_ACCELERATOR_LINES 0
+#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
+#define NIOS2_FLUSHDA_SUPPORTED
+#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
+#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
+#define NIOS2_HARDWARE_MULX_PRESENT 0
+#define NIOS2_HAS_DEBUG_CORE 1
+#define NIOS2_HAS_DEBUG_STUB
+#define NIOS2_HAS_EXTRA_EXCEPTION_INFO
+#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define NIOS2_HAS_JMPI_INSTRUCTION
+#define NIOS2_ICACHE_LINE_SIZE 32
+#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
+#define NIOS2_ICACHE_SIZE 2048
+#define NIOS2_INITDA_SUPPORTED
+#define NIOS2_INST_ADDR_WIDTH 0x1d
+#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
+#define NIOS2_OCI_VERSION 1
+#define NIOS2_RESET_ADDR 0x14000000
+
+
+/*
+ * Define for each module class mastered by the CPU
+ *
+ */
+
+#define __ALTERA_AVALON_ONCHIP_MEMORY2
+#define __ALTERA_AVALON_PIO
+#define __ALTERA_AVALON_SYSID_QSYS
+#define __ALTERA_AVALON_TIMER
+#define __ALTERA_AVALON_UART
+#define __ALTERA_ETH_TSE
+#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER
+#define __ALTERA_MEM_IF_DDR3_EMIF
+#define __ALTERA_MSGDMA
+#define __ALTERA_NIOS2_GEN2
+#define __ALTERA_ONCHIP_FLASH
+#define __SENSOR_RECON
+#define __UDP_GENERATOR
+
+
+/*
+ * System configuration
+ *
+ */
+
+#define ALT_DEVICE_FAMILY "MAX 10"
+#define ALT_ENHANCED_INTERRUPT_API_PRESENT
+#define ALT_IRQ_BASE NULL
+#define ALT_LOG_PORT "/dev/null"
+#define ALT_LOG_PORT_BASE 0x0
+#define ALT_LOG_PORT_DEV null
+#define ALT_LOG_PORT_TYPE ""
+#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
+#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
+#define ALT_NUM_INTERRUPT_CONTROLLERS 1
+#define ALT_STDERR "/dev/debug_uart"
+#define ALT_STDERR_BASE 0x18403c20
+#define ALT_STDERR_DEV debug_uart
+#define ALT_STDERR_IS_UART
+#define ALT_STDERR_PRESENT
+#define ALT_STDERR_TYPE "altera_avalon_uart"
+#define ALT_STDIN "/dev/debug_uart"
+#define ALT_STDIN_BASE 0x18403c20
+#define ALT_STDIN_DEV debug_uart
+#define ALT_STDIN_IS_UART
+#define ALT_STDIN_PRESENT
+#define ALT_STDIN_TYPE "altera_avalon_uart"
+#define ALT_STDOUT "/dev/debug_uart"
+#define ALT_STDOUT_BASE 0x18403c20
+#define ALT_STDOUT_DEV debug_uart
+#define ALT_STDOUT_IS_UART
+#define ALT_STDOUT_PRESENT
+#define ALT_STDOUT_TYPE "altera_avalon_uart"
+#define ALT_SYSTEM_NAME "q_sys"
+
+
+/*
+ * altera_iniche configuration
+ *
+ */
+
+#define INCLUDE_TCP
+#define INICHE_DEFAULT_IF "NOT_USED"
+
+
+/*
+ * button_pio configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_button_pio altera_avalon_pio
+#define BUTTON_PIO_BASE 0x18403d40
+#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define BUTTON_PIO_CAPTURE 0
+#define BUTTON_PIO_DATA_WIDTH 9
+#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
+#define BUTTON_PIO_DRIVEN_SIM_VALUE 0
+#define BUTTON_PIO_EDGE_TYPE "NONE"
+#define BUTTON_PIO_FREQ 50000000
+#define BUTTON_PIO_HAS_IN 1
+#define BUTTON_PIO_HAS_OUT 0
+#define BUTTON_PIO_HAS_TRI 0
+#define BUTTON_PIO_IRQ -1
+#define BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define BUTTON_PIO_IRQ_TYPE "NONE"
+#define BUTTON_PIO_NAME "/dev/button_pio"
+#define BUTTON_PIO_RESET_VALUE 0
+#define BUTTON_PIO_SPAN 16
+#define BUTTON_PIO_TYPE "altera_avalon_pio"
+
+
+/*
+ * calibration_ram configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_calibration_ram altera_avalon_onchip_memory2
+#define CALIBRATION_RAM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define CALIBRATION_RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define CALIBRATION_RAM_BASE 0x18403400
+#define CALIBRATION_RAM_CONTENTS_INFO ""
+#define CALIBRATION_RAM_DUAL_PORT 1
+#define CALIBRATION_RAM_GUI_RAM_BLOCK_TYPE "AUTO"
+#define CALIBRATION_RAM_INIT_CONTENTS_FILE "q_sys_calibration_ram"
+#define CALIBRATION_RAM_INIT_MEM_CONTENT 0
+#define CALIBRATION_RAM_INSTANCE_ID "NONE"
+#define CALIBRATION_RAM_IRQ -1
+#define CALIBRATION_RAM_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define CALIBRATION_RAM_NAME "/dev/calibration_ram"
+#define CALIBRATION_RAM_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define CALIBRATION_RAM_RAM_BLOCK_TYPE "AUTO"
+#define CALIBRATION_RAM_READ_DURING_WRITE_MODE "DONT_CARE"
+#define CALIBRATION_RAM_SINGLE_CLOCK_OP 0
+#define CALIBRATION_RAM_SIZE_MULTIPLE 1
+#define CALIBRATION_RAM_SIZE_VALUE 640
+#define CALIBRATION_RAM_SPAN 640
+#define CALIBRATION_RAM_TYPE "altera_avalon_onchip_memory2"
+#define CALIBRATION_RAM_WRITABLE 1
+
+
+/*
+ * ddr3_ram configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_ddr3_ram altera_mem_if_ddr3_emif
+#define DDR3_RAM_BASE 0x8000000
+#define DDR3_RAM_IRQ -1
+#define DDR3_RAM_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define DDR3_RAM_NAME "/dev/ddr3_ram"
+#define DDR3_RAM_SPAN 134217728
+#define DDR3_RAM_TYPE "altera_mem_if_ddr3_emif"
+
+
+/*
+ * debug_uart configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_debug_uart altera_avalon_uart
+#define DEBUG_UART_BASE 0x18403c20
+#define DEBUG_UART_BAUD 115200
+#define DEBUG_UART_DATA_BITS 8
+#define DEBUG_UART_FIXED_BAUD 1
+#define DEBUG_UART_FREQ 50000000
+#define DEBUG_UART_IRQ 4
+#define DEBUG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define DEBUG_UART_NAME "/dev/debug_uart"
+#define DEBUG_UART_PARITY 'N'
+#define DEBUG_UART_SIM_CHAR_STREAM ""
+#define DEBUG_UART_SIM_TRUE_BAUD 0
+#define DEBUG_UART_SPAN 32
+#define DEBUG_UART_STOP_BITS 1
+#define DEBUG_UART_SYNC_REG_DEPTH 2
+#define DEBUG_UART_TYPE "altera_avalon_uart"
+#define DEBUG_UART_USE_CTS_RTS 0
+#define DEBUG_UART_USE_EOP_REGISTER 0
+
+
+/*
+ * descriptor_memory configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_descriptor_memory altera_avalon_onchip_memory2
+#define DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DESCRIPTOR_MEMORY_BASE 0x18400000
+#define DESCRIPTOR_MEMORY_CONTENTS_INFO ""
+#define DESCRIPTOR_MEMORY_DUAL_PORT 0
+#define DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO"
+#define DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "q_sys_descriptor_memory"
+#define DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 0
+#define DESCRIPTOR_MEMORY_INSTANCE_ID "NONE"
+#define DESCRIPTOR_MEMORY_IRQ -1
+#define DESCRIPTOR_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define DESCRIPTOR_MEMORY_NAME "/dev/descriptor_memory"
+#define DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "AUTO"
+#define DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DESCRIPTOR_MEMORY_SINGLE_CLOCK_OP 0
+#define DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1
+#define DESCRIPTOR_MEMORY_SIZE_VALUE 8192
+#define DESCRIPTOR_MEMORY_SPAN 8192
+#define DESCRIPTOR_MEMORY_TYPE "altera_avalon_onchip_memory2"
+#define DESCRIPTOR_MEMORY_WRITABLE 1
+
+
+/*
+ * eth_tse configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_eth_tse altera_eth_tse
+#define ETH_TSE_BASE 0x18403000
+#define ETH_TSE_ENABLE_MACLITE 0
+#define ETH_TSE_FIFO_WIDTH 32
+#define ETH_TSE_IRQ -1
+#define ETH_TSE_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define ETH_TSE_IS_MULTICHANNEL_MAC 0
+#define ETH_TSE_MACLITE_GIGE 0
+#define ETH_TSE_MDIO_SHARED 0
+#define ETH_TSE_NAME "/dev/eth_tse"
+#define ETH_TSE_NUMBER_OF_CHANNEL 1
+#define ETH_TSE_NUMBER_OF_MAC_MDIO_SHARED 1
+#define ETH_TSE_PCS 0
+#define ETH_TSE_PCS_ID 0
+#define ETH_TSE_PCS_SGMII 1
+#define ETH_TSE_RECEIVE_FIFO_DEPTH 2048
+#define ETH_TSE_REGISTER_SHARED 0
+#define ETH_TSE_RGMII 1
+#define ETH_TSE_SPAN 1024
+#define ETH_TSE_TRANSMIT_FIFO_DEPTH 2048
+#define ETH_TSE_TYPE "altera_eth_tse"
+#define ETH_TSE_USE_MDIO 1
+
+
+/*
+ * ext_flash_avl_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller
+#define EXT_FLASH_AVL_CSR_BASE 0x18403d20
+#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512"
+#define EXT_FLASH_AVL_CSR_IRQ 5
+#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define EXT_FLASH_AVL_CSR_IS_EPCS 0
+#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr"
+#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024
+#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256
+#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536
+#define EXT_FLASH_AVL_CSR_SPAN 32
+#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096
+#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller"
+
+
+/*
+ * ext_flash_avl_mem configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller
+#define EXT_FLASH_AVL_MEM_BASE 0x14000000
+#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512"
+#define EXT_FLASH_AVL_MEM_IRQ -1
+#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define EXT_FLASH_AVL_MEM_IS_EPCS 0
+#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem"
+#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024
+#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256
+#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536
+#define EXT_FLASH_AVL_MEM_SPAN 67108864
+#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096
+#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller"
+
+
+/*
+ * frame_timer configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_frame_timer altera_avalon_timer
+#define FRAME_TIMER_ALWAYS_RUN 0
+#define FRAME_TIMER_BASE 0x18403c00
+#define FRAME_TIMER_COUNTER_SIZE 32
+#define FRAME_TIMER_FIXED_PERIOD 0
+#define FRAME_TIMER_FREQ 50000000
+#define FRAME_TIMER_IRQ -1
+#define FRAME_TIMER_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define FRAME_TIMER_LOAD_VALUE 4999
+#define FRAME_TIMER_MULT 2.0E-8
+#define FRAME_TIMER_NAME "/dev/frame_timer"
+#define FRAME_TIMER_PERIOD 5000
+#define FRAME_TIMER_PERIOD_UNITS "clocks"
+#define FRAME_TIMER_RESET_OUTPUT 0
+#define FRAME_TIMER_SNAPSHOT 0
+#define FRAME_TIMER_SPAN 32
+#define FRAME_TIMER_TICKS_PER_SEC 10000
+#define FRAME_TIMER_TIMEOUT_PULSE_OUTPUT 1
+#define FRAME_TIMER_TYPE "altera_avalon_timer"
+
+
+/*
+ * hal configuration
+ *
+ */
+
+#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
+#define ALT_MAX_FD 16
+#define ALT_SYS_CLK SYS_CLK_TIMER
+#define ALT_TIMESTAMP_CLK none
+
+
+/*
+ * msgdma_rx_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_rx_csr altera_msgdma
+#define MSGDMA_RX_CSR_BASE 0x18403ce0
+#define MSGDMA_RX_CSR_BURST_ENABLE 0
+#define MSGDMA_RX_CSR_BURST_WRAPPING_SUPPORT 0
+#define MSGDMA_RX_CSR_CHANNEL_ENABLE 0
+#define MSGDMA_RX_CSR_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_RX_CSR_CHANNEL_WIDTH 8
+#define MSGDMA_RX_CSR_DATA_FIFO_DEPTH 32
+#define MSGDMA_RX_CSR_DATA_WIDTH 32
+#define MSGDMA_RX_CSR_DESCRIPTOR_FIFO_DEPTH 8
+#define MSGDMA_RX_CSR_DMA_MODE 2
+#define MSGDMA_RX_CSR_ENHANCED_FEATURES 0
+#define MSGDMA_RX_CSR_ERROR_ENABLE 1
+#define MSGDMA_RX_CSR_ERROR_ENABLE_DERIVED 1
+#define MSGDMA_RX_CSR_ERROR_WIDTH 6
+#define MSGDMA_RX_CSR_IRQ -1
+#define MSGDMA_RX_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define MSGDMA_RX_CSR_MAX_BURST_COUNT 2
+#define MSGDMA_RX_CSR_MAX_BYTE 2048
+#define MSGDMA_RX_CSR_MAX_STRIDE 1
+#define MSGDMA_RX_CSR_NAME "/dev/msgdma_rx_csr"
+#define MSGDMA_RX_CSR_PACKET_ENABLE 1
+#define MSGDMA_RX_CSR_PACKET_ENABLE_DERIVED 1
+#define MSGDMA_RX_CSR_PREFETCHER_ENABLE 1
+#define MSGDMA_RX_CSR_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_RX_CSR_RESPONSE_PORT 2
+#define MSGDMA_RX_CSR_SPAN 32
+#define MSGDMA_RX_CSR_STRIDE_ENABLE 0
+#define MSGDMA_RX_CSR_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_RX_CSR_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_RX_CSR_TYPE "altera_msgdma"
+
+
+/*
+ * msgdma_rx_prefetcher_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_rx_prefetcher_csr altera_msgdma
+#define MSGDMA_RX_PREFETCHER_CSR_BASE 0x18403c80
+#define MSGDMA_RX_PREFETCHER_CSR_BURST_ENABLE 0
+#define MSGDMA_RX_PREFETCHER_CSR_BURST_WRAPPING_SUPPORT 0
+#define MSGDMA_RX_PREFETCHER_CSR_CHANNEL_ENABLE 0
+#define MSGDMA_RX_PREFETCHER_CSR_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_RX_PREFETCHER_CSR_CHANNEL_WIDTH 8
+#define MSGDMA_RX_PREFETCHER_CSR_DATA_FIFO_DEPTH 32
+#define MSGDMA_RX_PREFETCHER_CSR_DATA_WIDTH 32
+#define MSGDMA_RX_PREFETCHER_CSR_DESCRIPTOR_FIFO_DEPTH 8
+#define MSGDMA_RX_PREFETCHER_CSR_DMA_MODE 2
+#define MSGDMA_RX_PREFETCHER_CSR_ENHANCED_FEATURES 0
+#define MSGDMA_RX_PREFETCHER_CSR_ERROR_ENABLE 1
+#define MSGDMA_RX_PREFETCHER_CSR_ERROR_ENABLE_DERIVED 1
+#define MSGDMA_RX_PREFETCHER_CSR_ERROR_WIDTH 6
+#define MSGDMA_RX_PREFETCHER_CSR_IRQ 3
+#define MSGDMA_RX_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define MSGDMA_RX_PREFETCHER_CSR_MAX_BURST_COUNT 2
+#define MSGDMA_RX_PREFETCHER_CSR_MAX_BYTE 2048
+#define MSGDMA_RX_PREFETCHER_CSR_MAX_STRIDE 1
+#define MSGDMA_RX_PREFETCHER_CSR_NAME "/dev/msgdma_rx_prefetcher_csr"
+#define MSGDMA_RX_PREFETCHER_CSR_PACKET_ENABLE 1
+#define MSGDMA_RX_PREFETCHER_CSR_PACKET_ENABLE_DERIVED 1
+#define MSGDMA_RX_PREFETCHER_CSR_PREFETCHER_ENABLE 1
+#define MSGDMA_RX_PREFETCHER_CSR_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_RX_PREFETCHER_CSR_RESPONSE_PORT 2
+#define MSGDMA_RX_PREFETCHER_CSR_SPAN 32
+#define MSGDMA_RX_PREFETCHER_CSR_STRIDE_ENABLE 0
+#define MSGDMA_RX_PREFETCHER_CSR_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_RX_PREFETCHER_CSR_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_RX_PREFETCHER_CSR_TYPE "altera_msgdma"
+
+
+/*
+ * msgdma_tx_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_tx_csr altera_msgdma
+#define MSGDMA_TX_CSR_BASE 0x18403d00
+#define MSGDMA_TX_CSR_BURST_ENABLE 0
+#define MSGDMA_TX_CSR_BURST_WRAPPING_SUPPORT 0
+#define MSGDMA_TX_CSR_CHANNEL_ENABLE 0
+#define MSGDMA_TX_CSR_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_TX_CSR_CHANNEL_WIDTH 8
+#define MSGDMA_TX_CSR_DATA_FIFO_DEPTH 32
+#define MSGDMA_TX_CSR_DATA_WIDTH 32
+#define MSGDMA_TX_CSR_DESCRIPTOR_FIFO_DEPTH 8
+#define MSGDMA_TX_CSR_DMA_MODE 1
+#define MSGDMA_TX_CSR_ENHANCED_FEATURES 0
+#define MSGDMA_TX_CSR_ERROR_ENABLE 1
+#define MSGDMA_TX_CSR_ERROR_ENABLE_DERIVED 1
+#define MSGDMA_TX_CSR_ERROR_WIDTH 1
+#define MSGDMA_TX_CSR_IRQ -1
+#define MSGDMA_TX_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define MSGDMA_TX_CSR_MAX_BURST_COUNT 2
+#define MSGDMA_TX_CSR_MAX_BYTE 2048
+#define MSGDMA_TX_CSR_MAX_STRIDE 1
+#define MSGDMA_TX_CSR_NAME "/dev/msgdma_tx_csr"
+#define MSGDMA_TX_CSR_PACKET_ENABLE 1
+#define MSGDMA_TX_CSR_PACKET_ENABLE_DERIVED 1
+#define MSGDMA_TX_CSR_PREFETCHER_ENABLE 1
+#define MSGDMA_TX_CSR_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_TX_CSR_RESPONSE_PORT 2
+#define MSGDMA_TX_CSR_SPAN 32
+#define MSGDMA_TX_CSR_STRIDE_ENABLE 0
+#define MSGDMA_TX_CSR_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_TX_CSR_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_TX_CSR_TYPE "altera_msgdma"
+
+
+/*
+ * msgdma_tx_prefetcher_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_tx_prefetcher_csr altera_msgdma
+#define MSGDMA_TX_PREFETCHER_CSR_BASE 0x18403ca0
+#define MSGDMA_TX_PREFETCHER_CSR_BURST_ENABLE 0
+#define MSGDMA_TX_PREFETCHER_CSR_BURST_WRAPPING_SUPPORT 0
+#define MSGDMA_TX_PREFETCHER_CSR_CHANNEL_ENABLE 0
+#define MSGDMA_TX_PREFETCHER_CSR_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_TX_PREFETCHER_CSR_CHANNEL_WIDTH 8
+#define MSGDMA_TX_PREFETCHER_CSR_DATA_FIFO_DEPTH 32
+#define MSGDMA_TX_PREFETCHER_CSR_DATA_WIDTH 32
+#define MSGDMA_TX_PREFETCHER_CSR_DESCRIPTOR_FIFO_DEPTH 8
+#define MSGDMA_TX_PREFETCHER_CSR_DMA_MODE 1
+#define MSGDMA_TX_PREFETCHER_CSR_ENHANCED_FEATURES 0
+#define MSGDMA_TX_PREFETCHER_CSR_ERROR_ENABLE 1
+#define MSGDMA_TX_PREFETCHER_CSR_ERROR_ENABLE_DERIVED 1
+#define MSGDMA_TX_PREFETCHER_CSR_ERROR_WIDTH 1
+#define MSGDMA_TX_PREFETCHER_CSR_IRQ 2
+#define MSGDMA_TX_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define MSGDMA_TX_PREFETCHER_CSR_MAX_BURST_COUNT 2
+#define MSGDMA_TX_PREFETCHER_CSR_MAX_BYTE 2048
+#define MSGDMA_TX_PREFETCHER_CSR_MAX_STRIDE 1
+#define MSGDMA_TX_PREFETCHER_CSR_NAME "/dev/msgdma_tx_prefetcher_csr"
+#define MSGDMA_TX_PREFETCHER_CSR_PACKET_ENABLE 1
+#define MSGDMA_TX_PREFETCHER_CSR_PACKET_ENABLE_DERIVED 1
+#define MSGDMA_TX_PREFETCHER_CSR_PREFETCHER_ENABLE 1
+#define MSGDMA_TX_PREFETCHER_CSR_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_TX_PREFETCHER_CSR_RESPONSE_PORT 2
+#define MSGDMA_TX_PREFETCHER_CSR_SPAN 32
+#define MSGDMA_TX_PREFETCHER_CSR_STRIDE_ENABLE 0
+#define MSGDMA_TX_PREFETCHER_CSR_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_TX_PREFETCHER_CSR_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_TX_PREFETCHER_CSR_TYPE "altera_msgdma"
+
+
+/*
+ * onchip_flash_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_onchip_flash_csr altera_onchip_flash
+#define ONCHIP_FLASH_CSR_BASE 0x18403d60
+#define ONCHIP_FLASH_CSR_BYTES_PER_PAGE 8192
+#define ONCHIP_FLASH_CSR_IRQ -1
+#define ONCHIP_FLASH_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define ONCHIP_FLASH_CSR_NAME "/dev/onchip_flash_csr"
+#define ONCHIP_FLASH_CSR_READ_ONLY_MODE 0
+#define ONCHIP_FLASH_CSR_SECTOR1_ENABLED 1
+#define ONCHIP_FLASH_CSR_SECTOR1_END_ADDR 0x7fff
+#define ONCHIP_FLASH_CSR_SECTOR1_START_ADDR 0
+#define ONCHIP_FLASH_CSR_SECTOR2_ENABLED 1
+#define ONCHIP_FLASH_CSR_SECTOR2_END_ADDR 0xffff
+#define ONCHIP_FLASH_CSR_SECTOR2_START_ADDR 0x8000
+#define ONCHIP_FLASH_CSR_SECTOR3_ENABLED 1
+#define ONCHIP_FLASH_CSR_SECTOR3_END_ADDR 0x6ffff
+#define ONCHIP_FLASH_CSR_SECTOR3_START_ADDR 0x10000
+#define ONCHIP_FLASH_CSR_SECTOR4_ENABLED 1
+#define ONCHIP_FLASH_CSR_SECTOR4_END_ADDR 0xb7fff
+#define ONCHIP_FLASH_CSR_SECTOR4_START_ADDR 0x70000
+#define ONCHIP_FLASH_CSR_SECTOR5_ENABLED 1
+#define ONCHIP_FLASH_CSR_SECTOR5_END_ADDR 0x15ffff
+#define ONCHIP_FLASH_CSR_SECTOR5_START_ADDR 0xb8000
+#define ONCHIP_FLASH_CSR_SPAN 8
+#define ONCHIP_FLASH_CSR_TYPE "altera_onchip_flash"
+
+
+/*
+ * onchip_flash_data configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_onchip_flash_data altera_onchip_flash
+#define ONCHIP_FLASH_DATA_BASE 0x18200000
+#define ONCHIP_FLASH_DATA_BYTES_PER_PAGE 8192
+#define ONCHIP_FLASH_DATA_IRQ -1
+#define ONCHIP_FLASH_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define ONCHIP_FLASH_DATA_NAME "/dev/onchip_flash_data"
+#define ONCHIP_FLASH_DATA_READ_ONLY_MODE 0
+#define ONCHIP_FLASH_DATA_SECTOR1_ENABLED 1
+#define ONCHIP_FLASH_DATA_SECTOR1_END_ADDR 0x7fff
+#define ONCHIP_FLASH_DATA_SECTOR1_START_ADDR 0
+#define ONCHIP_FLASH_DATA_SECTOR2_ENABLED 1
+#define ONCHIP_FLASH_DATA_SECTOR2_END_ADDR 0xffff
+#define ONCHIP_FLASH_DATA_SECTOR2_START_ADDR 0x8000
+#define ONCHIP_FLASH_DATA_SECTOR3_ENABLED 1
+#define ONCHIP_FLASH_DATA_SECTOR3_END_ADDR 0x6ffff
+#define ONCHIP_FLASH_DATA_SECTOR3_START_ADDR 0x10000
+#define ONCHIP_FLASH_DATA_SECTOR4_ENABLED 1
+#define ONCHIP_FLASH_DATA_SECTOR4_END_ADDR 0xb7fff
+#define ONCHIP_FLASH_DATA_SECTOR4_START_ADDR 0x70000
+#define ONCHIP_FLASH_DATA_SECTOR5_ENABLED 1
+#define ONCHIP_FLASH_DATA_SECTOR5_END_ADDR 0x15ffff
+#define ONCHIP_FLASH_DATA_SECTOR5_START_ADDR 0xb8000
+#define ONCHIP_FLASH_DATA_SPAN 1441792
+#define ONCHIP_FLASH_DATA_TYPE "altera_onchip_flash"
+
+
+/*
+ * output_pio configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_output_pio altera_avalon_pio
+#define OUTPUT_PIO_BASE 0x18403c40
+#define OUTPUT_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define OUTPUT_PIO_BIT_MODIFYING_OUTPUT_REGISTER 1
+#define OUTPUT_PIO_CAPTURE 0
+#define OUTPUT_PIO_DATA_WIDTH 8
+#define OUTPUT_PIO_DO_TEST_BENCH_WIRING 0
+#define OUTPUT_PIO_DRIVEN_SIM_VALUE 0
+#define OUTPUT_PIO_EDGE_TYPE "NONE"
+#define OUTPUT_PIO_FREQ 50000000
+#define OUTPUT_PIO_HAS_IN 0
+#define OUTPUT_PIO_HAS_OUT 1
+#define OUTPUT_PIO_HAS_TRI 0
+#define OUTPUT_PIO_IRQ -1
+#define OUTPUT_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define OUTPUT_PIO_IRQ_TYPE "NONE"
+#define OUTPUT_PIO_NAME "/dev/output_pio"
+#define OUTPUT_PIO_RESET_VALUE 0
+#define OUTPUT_PIO_SPAN 32
+#define OUTPUT_PIO_TYPE "altera_avalon_pio"
+
+
+/*
+ * sensor_interface configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_sensor_interface sensor_recon
+#define SENSOR_INTERFACE_BASE 0x18403d50
+#define SENSOR_INTERFACE_IRQ -1
+#define SENSOR_INTERFACE_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define SENSOR_INTERFACE_NAME "/dev/sensor_interface"
+#define SENSOR_INTERFACE_SPAN 16
+#define SENSOR_INTERFACE_TYPE "sensor_recon"
+
+
+/*
+ * sys_clk_timer configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
+#define SYS_CLK_TIMER_ALWAYS_RUN 0
+#define SYS_CLK_TIMER_BASE 0x18403c60
+#define SYS_CLK_TIMER_COUNTER_SIZE 32
+#define SYS_CLK_TIMER_FIXED_PERIOD 0
+#define SYS_CLK_TIMER_FREQ 50000000
+#define SYS_CLK_TIMER_IRQ 0
+#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define SYS_CLK_TIMER_LOAD_VALUE 499999
+#define SYS_CLK_TIMER_MULT 0.001
+#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
+#define SYS_CLK_TIMER_PERIOD 10
+#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
+#define SYS_CLK_TIMER_RESET_OUTPUT 0
+#define SYS_CLK_TIMER_SNAPSHOT 1
+#define SYS_CLK_TIMER_SPAN 32
+#define SYS_CLK_TIMER_TICKS_PER_SEC 100
+#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
+
+
+/*
+ * sysid configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
+#define SYSID_BASE 0x18403d68
+#define SYSID_ID -87110914
+#define SYSID_IRQ -1
+#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define SYSID_NAME "/dev/sysid"
+#define SYSID_SPAN 8
+#define SYSID_TIMESTAMP 1728634208
+#define SYSID_TYPE "altera_avalon_sysid_qsys"
+
+
+/*
+ * ucosii configuration
+ *
+ */
+
+#define OS_ARG_CHK_EN 0
+#define OS_CPU_HOOKS_EN 1
+#define OS_DEBUG_EN 0
+#define OS_EVENT_NAME_SIZE 32
+#define OS_FLAGS_NBITS 16
+#define OS_FLAG_ACCEPT_EN 1
+#define OS_FLAG_DEL_EN 1
+#define OS_FLAG_EN 1
+#define OS_FLAG_NAME_SIZE 32
+#define OS_FLAG_QUERY_EN 1
+#define OS_FLAG_WAIT_CLR_EN 1
+#define OS_LOWEST_PRIO 20
+#define OS_MAX_EVENTS 60
+#define OS_MAX_FLAGS 20
+#define OS_MAX_MEM_PART 60
+#define OS_MAX_QS 20
+#define OS_MAX_TASKS 5
+#define OS_MBOX_ACCEPT_EN 1
+#define OS_MBOX_DEL_EN 1
+#define OS_MBOX_EN 1
+#define OS_MBOX_POST_EN 1
+#define OS_MBOX_POST_OPT_EN 1
+#define OS_MBOX_QUERY_EN 1
+#define OS_MEM_EN 1
+#define OS_MEM_NAME_SIZE 32
+#define OS_MEM_QUERY_EN 1
+#define OS_MUTEX_ACCEPT_EN 1
+#define OS_MUTEX_DEL_EN 1
+#define OS_MUTEX_EN 1
+#define OS_MUTEX_QUERY_EN 1
+#define OS_Q_ACCEPT_EN 1
+#define OS_Q_DEL_EN 1
+#define OS_Q_EN 1
+#define OS_Q_FLUSH_EN 1
+#define OS_Q_POST_EN 1
+#define OS_Q_POST_FRONT_EN 1
+#define OS_Q_POST_OPT_EN 1
+#define OS_Q_QUERY_EN 1
+#define OS_SCHED_LOCK_EN 1
+#define OS_SEM_ACCEPT_EN 1
+#define OS_SEM_DEL_EN 1
+#define OS_SEM_EN 1
+#define OS_SEM_QUERY_EN 1
+#define OS_SEM_SET_EN 1
+#define OS_TASK_CHANGE_PRIO_EN 1
+#define OS_TASK_CREATE_EN 1
+#define OS_TASK_CREATE_EXT_EN 1
+#define OS_TASK_DEL_EN 1
+#define OS_TASK_IDLE_STK_SIZE 512
+#define OS_TASK_NAME_SIZE 32
+#define OS_TASK_PROFILE_EN 1
+#define OS_TASK_QUERY_EN 1
+#define OS_TASK_STAT_EN 0
+#define OS_TASK_STAT_STK_CHK_EN 0
+#define OS_TASK_STAT_STK_SIZE 512
+#define OS_TASK_SUSPEND_EN 1
+#define OS_TASK_SW_HOOK_EN 1
+#define OS_TASK_TMR_PRIO 0
+#define OS_TASK_TMR_STK_SIZE 512
+#define OS_THREAD_SAFE_NEWLIB 1
+#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC
+#define OS_TICK_STEP_EN 0
+#define OS_TIME_DLY_HMSM_EN 1
+#define OS_TIME_DLY_RESUME_EN 1
+#define OS_TIME_GET_SET_EN 1
+#define OS_TIME_TICK_HOOK_EN 1
+#define OS_TMR_CFG_MAX 16
+#define OS_TMR_CFG_NAME_SIZE 16
+#define OS_TMR_CFG_TICKS_PER_SEC 10
+#define OS_TMR_CFG_WHEEL_SIZE 2
+#define OS_TMR_EN 0
+
+
+/*
+ * udp_generator configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_udp_generator udp_generator
+#define UDP_GENERATOR_BASE 0x18403cc0
+#define UDP_GENERATOR_IRQ -1
+#define UDP_GENERATOR_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define UDP_GENERATOR_NAME "/dev/udp_generator"
+#define UDP_GENERATOR_SPAN 32
+#define UDP_GENERATOR_TYPE "udp_generator"
+
+#endif /* __SYSTEM_H_ */